Dual ported network physical layer

A switching physical layer (PHY) device comprises a first termination network, a switching transmitter, and a switching receiver. The first termination network communicates with a first network connector. The switching transmitter includes first and second outputs, which communicate with the first termination network and a second termination network, respectively. The switching transmitter selectively outputs a transmit signal to a selected one of the first and second termination networks based on a control signal. The switching receiver includes first and second inputs, which communicate with the first and second termination networks, respectively. The switching receiver receives a receive signal from the selected one of the first and second termination networks.

FIELD

The present disclosure relates to analog switching circuits, and more particularly to analog switching circuits for semiconductor devices, network devices, and other integrated circuits.

BACKGROUND

Many circuits selectively receive inputs from and/or provide outputs to two or more other circuits. A switching circuit that includes transistors may be used to select between the inputs and/or outputs. For example inFIGS. 1A and 1B, first and second circuits10and12are selectively connected by a switching circuit14to a third circuit16. In some implementations, the first and second circuits10and12are selectively connected by transistors Q1and Q2and Q3and Q4, respectively. Switching inputs S1andS1are used to select the first circuit10or the second circuit12. When S1is in a first state, the first circuit10is connected and the second circuit12is not connected. When S1is in a second state, the second circuit12is connected and the first circuit10is not connected.

In some situations, the output signal of the first and second circuits10and/or12may exceed the voltage supply and/or breakdown voltage of the transistors Q1, Q2, Q3and Q4that are used in the switching circuit14. For example, a voltage supply that supplies the switching circuit14may provide 2.5V. The switching circuit14may be used to switch between first and second transmitters in an Ethernet network device. The voltage output of an exemplary transmitter in a 100BASET network may be operated with a maximum voltage of 3.5V, a minimum voltage of 1.5V, and a common mode voltage of 2.5V. The maximum voltage level of the transmitter outputs may cause operational problems such as breakdown of the transistors Q1, Q2, Q3, and Q4.

Another situation that may require analog switching includes switching between MDI and MDIX configurations in 100BASET or 10BASET network devices. Referring now toFIGS. 2A and 2B, first and second network devices20and22include physical layers (PHYs)24and26, respectively, that are connected by network cables. For example, the network device20can be a personal computer or printer and the network device22can be a network switch. Each of the network devices20and22is connected by at least two pairs of twisted pair wires that are labeled1,2and3,6inFIGS. 2A and 2B.

When in an MDI configuration inFIG. 2A, the PHY24has a first pair1,2that is configured as a transmitter30and a second pair3,6that is configured as a receiver34. When in an MDIX configuration inFIG. 2B, the PHY24has first pair1,2that is configured as a receiver46and a second pair3,6that is configured as a transmitter48. When in an MDIX configuration, the PHY26has a first pair1,2that is configured as a receiver40and a second pair3,6that is configured as a transmitter44. When the network devices20and22have different configurations, a standard or straight network cable50is used. When the network devices20and22have the same configuration, a crossover network cable52is used. When the incorrect network cable is employed for a particular situation (as inFIG. 2B), either the cable must be changed or the transmitter and receiver connections for one of the network devices needs to be switched.

Referring now toFIG. 12, a functional block diagram of a laptop docking system according to the prior art is presented. A laptop402is removably connected to a docking station404. The laptop402includes a motherboard406and a first network connector408. A physical layer (PHY) device410communicates with a switch412and a media access control (MAC) device416, which are all arranged on the motherboard406.

The PHY device410provides an interface to a physical medium such as coaxial cable, fiber optic cable, or twisted pair. The MAC device416provides an interface between the PHY device410and a host, such as a processor of the laptop402. The docking station404includes a second network connector414. The first and second network connectors408and414communicate with the switch412.

The first and second network connectors408and414may include RJ-45 connectors. The switch412selectively connects the first network connector408or the second network connector414to the PHY device410. When the laptop402is connected to the docking station404, the switch412may automatically select the second network connector414. Once the laptop402is removed from the docking station404, the switch412may automatically select the first network connector408.

The switch412, however, has an inherent resistance. The resistance causes a voltage drop between the PHY device410and the first and second network connectors408and414, which degrades performance. Incoming signals are attenuated, leading to a greater error rate in identifying received symbols. If the incoming signals are already attenuated, such as by a long twisted pair transmission line, the additional attenuation caused by the switch may cause the incoming signals to violate a minimum voltage specification.

The switch412causes similar attenuation problems for transmit signals. In order to decrease the resistance of the switch412, the size of the switch412can be increased, as shown by a relationship illustrated inFIG. 13A. However, as the size of the switch412increases, the capacitance of the switch412also increases, as shown by a relationship illustrated inFIG. 13B.

As capacitance increases, the bandwidth of the switch412is limited, as shown inFIG. 13C. When the switch412is small enough to maintain adequate bandwidth for a protocol such as Gigabit Ethernet, it may have a resistance of approximately 5 ohms. With a termination resistance of 50 ohms, such as is typical of Ethernet, the resistance of the switch412causes an approximate 10% decrease in signal strength.

Referring now toFIG. 14A, a functional block diagram of a network interface according to the prior art with a single network connector is presented. A transmission line500communicates with the first network connector408. The first network connector408communicates with a transformer504, which couples signals from the transmission line500to a termination resistance506. The termination resistance506communicates with a transmitter508and a receiver510. A control module512transmits data to the transmitter508and receives data from the receiver510. The control module512communicates with the MAC device416.

Referring now toFIG. 14B, a functional schematic diagram of the network interface ofFIG. 14Ais presented. The transmission line500is coupled to the first network connector408, which communicates with the transformer504. The transformer504communicates with the termination resistance506. The transmitter508provides a current Itx520to first and second ends of the termination resistance506. The receiver510detects a voltage Vtx522across the first and second ends of the termination resistance506.

Referring now toFIG. 15A, a functional block diagram of a switched network interface according to the prior art including two network connectors is presented. The docking station404includes the second network connector414. For purposes of illustration, the transmission line500is shown coupled to the first network connector408. The switch412selectively couples one of the first and second network connectors408and414to the transformer504.

Referring now toFIG. 15B, a functional schematic diagram of the switched network interface ofFIG. 15Ais presented. For purposes of illustration, the transmission line500is coupled to the first network connector408. The switch412selectively couples one of the first and second network connectors408and414to the transformer504. The voltage Vtx522measured across the termination resistance506is reduced by the voltage drop in the switch412.

Referring now toFIG. 16A, a functional block diagram of another switched network interface according to the prior art is presented. For purposes of illustration, the transmission line500is connected to the first network connector408, which couples the transmission line500to the termination resistance506via the transformer504. The termination resistance506communicates with the transmitter508and the receiver510.

The termination resistance506may communicate with the transmitter508and the receiver510via a hybrid (not shown). The transmitter508and the receiver510communicate with the control module512. The second network connector414communicates with a second transformer540. The second transformer540communicates with a second termination resistance542.

The second termination resistance542communicates with a second transmitter544and a second receiver546. The second termination resistance542may communicate with the second transmitter544and the second receiver546via a hybrid (not shown). The second transmitter544and the second receiver546communicate with a second control module548.

A switch550selectively connects the control module512and the second control module548to the MAC device416. The docking station404includes the second network connector414and may also include the second transformer540, the second termination resistance542, the second transmitter544, the second receiver546, and the second control module548. The expense of duplicating all these components makes this solution unattractive.

Referring now toFIG. 16B, a functional schematic diagram of the switched network interface ofFIG. 16Ais presented. For purposes of illustration, the transmission line500is coupled to the first network connector408. The first network connector408communicates with the transformer504, which in turn communicates with the termination resistance506. The termination resistance506communicates with a transceiver module560.

The transceiver module560includes a transmitter and a receiver, such as the transmitter508and the receiver510ofFIG. 16A, and indicated by the current Itx520and the voltage Vtx522, respectively. The second network connector414communicates with the second transformer540, which in turn communicates with the second termination resistance542. The second termination resistance542communicates with a second transceiver module562. The switch550selectively connects the first and second transceiver modules560and562to the MAC device416ofFIG. 16A.

SUMMARY

A switching physical layer (PHY) device comprises a first termination network, a switching transmitter, and a switching receiver. The first termination network communicates with a first network connector. The switching transmitter includes first and second outputs, which communicate with the first termination network and a second termination network, respectively. The switching transmitter selectively outputs a transmit signal to a selected one of the first and second termination networks based on a control signal. The switching receiver includes first and second inputs, which communicate with the first and second termination networks, respectively. The switching receiver receives a receive signal from the selected one of the first and second termination networks.

In other features, the switching PHY device further comprises first and second hybrids. The first input of the switching receiver communicates with the first termination network via the first hybrid and the second input of the switching receiver communicates with the second termination network via the second hybrid. The first output of the switching transmitter communicates with the first termination network via the first hybrid and the second output of the switching transmitter communicates with the second termination network via the second hybrid.

In further features, the switching transmitter outputs a replica transmit signal based on the transmit signal to the switching receiver. The switching receiver sums the replica transmit signal with the receive signal at a first summing node. The switching PHY device further comprises an amplifier that includes an input. The switching receiver sums the replica transmit signal with a second receive signal from a second one of the first and second termination networks at a second summing node; and a switch module that connects one of the first summing node and the second summing node to the input of the amplifier based on the control signal.

In still other features, the switching transmitter comprises a first cascode transistor that selectively passes the transmit signal to the first output based on the control signal and a second cascode transistor that selectively passes the transmit signal to the second output based on the control signal. A laptop includes the switching PHY device. A system comprises the laptop and a docking station including a second network connector that communicates with the second termination network. The docking station includes the second termination network.

In other features, the laptop includes a control module that generates the control signal to select the second termination network after the laptop is connected to the docking station. The control module generates the control signal to select the first termination network after the laptop is disconnected from the docking station. An integrated circuit comprises the switching PHY device. The integrated circuit further comprises a media access control (MAC) device that communicates with the switching PHY device.

A switching physical layer (PHY) device comprises first terminating means for terminating a network signal and for communicating with a first network connector; switching transmitter means for selectively outputting a transmit signal to a selected one of the first terminating means and a second termination network based on a control signal, where the switching transmitter means includes first and second outputs that communicate with the first terminating means and the second termination network, respectively; and switching receiver means for receiving a receive signal from the selected one of the first terminating means and the second termination network. The switching receiver means includes first and second inputs that communicate with the first terminating means and the second termination network, respectively.

In other features, the switching PHY device further comprises first hybrid means for coupling the first input of the switching receiver means with the first terminating means; and second hybrid means for coupling the second input of the switching receiver means with the second termination network. The first output of the switching transmitter means communicates with the first terminating means via the first hybrid means and the second output of the switching transmitter means communicates with the second termination network via the second hybrid means.

In further features, the switching transmitter means outputs a replica transmit signal based on the transmit signal to the switching receiver means. The switching receiver means sums the replica transmit signal with the receive signal at a first summing node. The switching PHY device further comprises amplifying means for amplifying an input. The switching receiver means sums the replica transmit signal with a second receive signal from a second one of the first terminating means and the second termination network at a second summing node; and switching means for connecting one of the first summing node and the second summing node to the input of the amplifying means based on the control signal.

In still other features, the switching transmitter means comprises first cascode switching means for selectively passing the transmit signal to the first output based on the control signal; and second cascode switching means for selectively passing the transmit signal to the second output based on the control signal. A laptop includes the switching PHY device. A system comprises the laptop and docking means for receiving the laptop. The docking means includes a second network connector that communicates with the second termination network. The docking means includes the second termination network.

In other features, the laptop includes control means for generating the control signal to select the second termination network after the laptop is connected to the docking means. The control means generates the control signal to select the first terminating means after the laptop is disconnected from the docking means. An integrated circuit comprises the switching PHY device. The integrated circuit further comprises media access control (MAC) means for communicating with the switching PHY device.

A switching physical layer (PHY) device comprises a first termination network, a switch module, and a receiver. The first termination network communicates with a first network connector. The switch module includes a terminal that communicates with the first termination network and a second termination network, and selectively connects a selected one of the first and second termination networks to the terminal based on a control signal. The receiver receives a receive signal from the terminal of the switch module.

In other features, the switching PHY device further comprises a hybrid interposed between the receiver and the terminal of the switch module; and a transmitter that outputs a transmit signal to the terminal of the switch module via the hybrid. The switching PHY device further comprises a first hybrid interposed between the switch module and the first termination network; a second hybrid interposed between the switch module and the second termination network; a second switch module that includes a second terminal, that communicates with the first and second termination networks via the first and second hybrids, respectively, and that connects the selected one of the first and second termination networks to the second terminal; and a transmitter that outputs a transmit signal to the second terminal of the second switch module.

In further features, the switching PHY device further comprises a transmitter that outputs a replica of a transmit signal to the receiver. The transmitter outputs the transmit signal to the terminal of the switch module. The switching PHY device further comprises a second switch module that includes a second terminal, that communicates with the first termination network and the second termination network, and that connects the selected one of the first and second termination networks to the second terminal. The transmitter outputs the transmit signal to the second terminal of the second switch module. The receiver subtracts the replica of the transmit signal from the receive signal. A laptop includes the switching PHY device.

In still other features, a system comprises the laptop and a docking station including a second network connector that communicates with the second termination network. The docking station includes the second termination network. The laptop includes a control module that generates the control signal to select the second termination network after the laptop is connected to the docking station. The control module generates the control signal to select the first termination network after the laptop is disconnected from the docking station. An integrated circuit comprises the switching PHY device. The integrated circuit further comprises a media access control (MAC) device that communicates with the switching PHY device.

A switching physical layer (PHY) device comprises first terminating means for terminating a network signal and for communicating with a first network connector; switching means for selectively connecting a selected one of the first terminating means and a second termination network to a terminal of the switching means based on a control signal; and receiving means for receiving a receive signal from the terminal of the switching means.

In other features, the switching PHY device further comprises hybrid means for coupling the receiving means with the terminal of the switching means; and transmitting means for outputting a transmit signal to the terminal of the switching means via the hybrid means. The switching PHY device further comprises first hybrid means for coupling the switching means with the first terminating means; second hybrid means for coupling the switching means with the second termination network; second switching means for connecting the selected one of the first terminating means and the second termination network to a second terminal of the second switching means.

In further features, the second switching means communicates with the first terminating means and the second termination network via the first and second hybrid means, respectively; and transmitting means for outputting a transmit signal to the second terminal of the second switching means. The switching PHY device further comprises transmitting means for outputting a replica of a transmit signal to the receiving means. The transmitting means outputs the transmit signal to the terminal of the switching means.

In still other features, the switching PHY device further comprises second switching means for connecting the selected one of the first terminating means and the second termination network to a second terminal. The transmitting means outputs the transmit signal to the second terminal of the second switching means. The receiving means subtracts the replica of the transmit signal from the receive signal. A laptop includes the switching PHY device. A system comprises the laptop and docking means for receiving the laptop. The docking means includes a second network connector that communicates with the second termination network.

In other features, the docking means includes the second termination network. The laptop includes control means for generating the control signal to select the second termination network after the laptop is connected to the docking means. The control means generates the control signal to select the first terminating means after the laptop is disconnected from the docking means. An integrated circuit comprises the switching PHY device. The integrated circuit further comprises media access control (MAC) means for communicating with the switching PHY device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 3,4, and5illustrate several exemplary but not limiting uses of the analog switching circuit according to the present disclosure. Skilled artisans will appreciate that the analog switching circuit can be used in other environments than those depicted.FIGS. 6-10illustrate the analog switching circuit in further detail.

Referring now toFIG. 3, a network device100includes a physical layer102with various physical layer circuits104. An autocrossover circuit106communicates with the receiver46, the transmitter48, and an analog switching circuit108according to the present disclosure, which will be described more fully below. The autocrossover circuit106may also communicate with the physical layer circuits104. The autocrossover circuit106automatically detects when the incorrect cable type is being used and generates a change configuration signal that is output to the analog switching circuit108. Additional details relating to the autocrossover circuit106can be found in commonly assigned U.S. patent application Ser. No. 10/106,720, filed Mar. 26, 2002, which is hereby incorporated by reference in its entirety.

Referring now toFIG. 4, a functional block diagram of a multi-port switch130includes first and second ports136and138. The ports136and138are selectively coupled by an analog switching circuit144according to the present disclosure to a third port148. Each port136,138and148includes first and second conductors150and152,154and156and160and162, respectively. The analog switching circuit144selectively switches the conductors150and152or154and156to the conductors160and162.

The sub-functional units in a row perform the same lower level function. Typically, there are no connections between the functional units other than ground and power. There are, however, connections between the sub-functional units in a functional unit. The connections may be one-way or two-way and may include one or more connecting wires.

For example, four or eight Gigabit physical layer devices may be fabricated on the semiconductor. The physical layer device includes a first sub-functional unit that performs physical coding sub-layer (PCS), Flow Control Token (FCT), and Decision Feedback Sequence Estimation (DFSE) functions. A second sub-functional unit implements a finite impulse response (FIR) filter function. A third sub-functional unit performs echo and near end crosstalk (NEXT) functions. Fourth and fifth sub-functional units implement digital and analog front end (AFE) functions, respectively. As can be appreciated, the functional units can be separated into other sub-functional units. If the yield for each individual functional unit is 90%, then the yield for the semiconductor with x identical functional units is (0.9)x. For example, if a semiconductor includes eight functional units each having a yield of 90%, the yield of the semiconductor is 43%, which is not an acceptable yield.

Referring again toFIG. 5A, a spare functional unit200-S is fabricated on a semiconductor190in addition to the functional units200-1,200-2, . . . , and200-6. In addition, switching circuits194according to the present disclosure are located at inputs and outputs of one of more of the sub-functional units. In the exemplary embodiment illustrated inFIG. 5A, the spare functional unit200-S is located between the functional units200. As can be appreciated, however, the spare functional unit200-S can be located in any position on the semiconductor190. For example, the spare functional unit200-S can be located to the left or right of any of the functional units200.

The switching circuits194and the spare functional unit200-S allow the semiconductor190to replace one non-operable functional unit200-1,200-2,200-3,200-4,200-5or200-6. In the example inFIG. 5A, the spare functional unit200-S allows any number of sub-functional units in one functional unit to fail. By allowing the replacement of non-operable functional units, the yield of the semiconductor190is significantly improved. If one or any combination of the sub-functional units11,21,31, and/or41in the functional unit200-1fail (as shown by cross-hatched shading), the analog switching circuits194are reconfigured to replace the non-operable sub-functional units11,21,31, and41with the sub-functional units in the spare functional unit200-S. InFIG. 5B, a controller201communicates with the functional units200and the switching circuits194. The controller201may perform diagnostics to identify when a functional unit is not operating correctly. The controller201replaces the identified functional unit using the switching circuits194.

After reconfiguration, the first functional unit200-1includes sub-functional units12,22,32, and42. The second functional unit200-2includes sub-functional units13,23,33, and43. The third functional unit200-3includes sub-functional units1S,2S,3S, and4S. The fourth functional unit200-4includes sub-functional units14,24,34, and44. The fifth functional unit200-5includes sub-functional units15,25,35, and45. The sixth functional unit200-6includes sub-functional units16,26,36, and46. This exemplary embodiment allows replacement on a functional unit basis only. However, additional switches can be used between sub-functional units to switch out one or more individual sub-functional units as described more fully in commonly assigned U.S. patent application Ser. No. 10/358,709, filed Feb. 5, 2003.

Referring now toFIG. 6, an electrical schematic of an exemplary analog switching circuit204according to the present disclosure is shown. A first and second pair differential signals210,212and214,216are output by first and second circuits206and208, respectively, to one end of resistors R1, R2, R3and R4. The first and second differential signals have first and second common mode voltages, and maximum and minimum voltages. Opposite ends of the resistors R1, R2, R3and R4are connected to switches218,220,222, and224. The switches218,220,222, and224selectively output either the first pair of signals210,212or the second pair of input signals214,216to inputs of an operational amplifier226. The operational amplifier226includes feedback resistors R5and R6, which are connected between inputs and outputs of the operational amplifier226.

The operational amplifier226outputs a pair of output signals228,230to a third circuit233. When switches218and220are closed, switches222and224are open and the first pair of input signals210,212is output to the operational amplifier226. When switches218and220are open, switches222and224are closed and the second pair of input signals214,216is output to the operational amplifier226. A common mode feedback (CMFB) circuit232is connected to the inputs of the operational amplifier226to maintain a substantially fixed common mode voltage input that is lower than the first and second common mode voltages.

Referring now toFIG. 7, one exemplary implementation of the CMFB circuit232for the switching circuit194is shown. Referring back toFIG. 1C, an example of the input signals210,212and214,216is shown. The voltage level of the input signals may vary, or “swing,” as high as 3.5 volts or as low as 1.5 volts and have a common mode voltage of 2.5V. The supply voltage of the transistors in the switching circuit14may only be around 2.5 volts or less. If the voltage level swings as high as 3.5 volts, the voltage level may exceed the breakdown voltage of the transistors in the switching device14and cause breakdown or other problems.

As shown inFIG. 7, voltage signals234,236(VAIP, VAIN) and a constant common mode voltage238are input to an amplifier240. The amplifier outputs adjust first and second controllable current sources242and244. The current outputs of the current sources242and244adjust the voltage signals VAIPand VAINto maintain the common mode voltage of the operational amplifier226. The common mode voltage is limited to a common mode voltage that is less than the first and second common mode voltages. In the example set forth above, the common mode voltage of the operational amplifier is limited to 1.5V.

Referring now toFIG. 8, an electrical schematic of one exemplary implementation of the analog switching circuit204according to the present disclosure is shown. The first pair of input signals210,212is output via resistors R1Aand R1Band R2Aand R2Bto a first pair of transistors250,252, respectively. The second pair of input signals214,216is output via resistors R3Aand R3Band R4Aand R4Bto a second pair of transistors254,256, respectively. A pair of switching signals258,260controls the states of the first and second pairs of transistors250,252and254,256(and other transistors described below). In the preferred embodiment, the transistors250,252and254,256are PMOS transistors. However, other suitable transistors, such as NMOS transistors, may also be used. If the transistors250,252are on, the transistors254,256are off. Either the first pair of input signals210,212or the second pair of input signals224,226are output as output signals.

Referring now toFIG. 9, an electrical schematic of another exemplary implementation of the switching circuit according to the present disclosure is shown. The switching circuit inFIG. 9is similar toFIG. 8. However, additional switches300and302are added to eliminate the gain error caused by switching resistance, as will be described below.

Referring now toFIGS. 10 and 11, gain error that is introduced by the switching resistance for the circuits inFIGS. 8 and 9is illustrated. InFIG. 10, the gain is defined as follows:

A⁡(gain)=-R2R1+Rsif⁢⁢Rs=0.1⁢⁢R1,⁢then⁢⁢A=-R21.1⁢⁢R1=-0.909⁢R2R1
Where Rsis the switching resistance. This gain error may be acceptable when used in some receivers, such as 10BASET and 100BASE-T receivers. However, this gain error may not be acceptable in other implementations such as Gigabit or 802.3ab compliant receivers.

InFIG. 11, the additional switches are added eliminate the gain error. The gain is defined as follows:

A=-R2+RsR1+Rsif⁢⁢Rs=0.1⁢⁢R1,⁢and⁢⁢R2=R1,⁢then⁢⁢A=-1.1⁢R21.1⁢R1=-R2R1
Therefore, the additional switches300and302eliminate the gain error.

Referring now toFIG. 17, a functional block diagram of an exemplary laptop docking system according to the principles of the present disclosure is presented. A laptop600is removably connected to a docking station602. The laptop600and the docking station602include first and second network connectors604and606, respectively. The first and second network connectors604and606communicate with a switching physical layer (PHY) device610.

The switching PHY device610selects between the first and second network connectors604and606. This selection may be made based upon whether the laptop600is connected to the docking station602. In various implementations, the switching PHY device610may automatically select the second network connector606when the laptop600is connected to the docking station602.

In the prior art, signals from network connectors are switched before the signals are terminated, as shown inFIGS. 15A-15B. The switch creates a voltage divider, and a portion of the signal voltage is lost across the switch. This reduces the signal strength of incoming signals received by the near-end receiver, as well as outgoing signals transmitted to the far-end receiver. Instead of switching signals prior to termination, the switching PHY device610switches signals after the signals have been terminated.

By actively switching the signals after they have been terminated, the switch resistance of the switching PHY device610does not reduce the magnitude of the signals across the termination networks. Switches within the switching PHY device610are thus not subject to an unworkable tradeoff between higher capacitance and lower resistance, as shown inFIGS. 13A-13C. The switches can be made smaller to achieve adequate bandwidth performance, while the associated increased resistance does not reduce signal strength.

The switching PHY device610communicates with a media access control (MAC) device612. A network interface module614includes the switching PHY device610, the MAC device612, and optionally a host interface (not shown). In various implementations, the switching PHY device610and/or the MAC device612may be integrated in single integrated circuits611and613, respectively. In various implementations, the network interface module614may be integrated as a single integrated circuit.

The MAC device612may communicate with an input/output (I/O) interface616or may communicate with the I/O interface616via the optional host interface. A processor618communicates with memory620and with the I/O interface616. The network interface module614, the I/O interface616, the processor618, and memory620may be located on a motherboard626of the laptop600. The motherboard626may communicate with other components such as a power supply628and a display630.

Referring now generally toFIGS. 18A-25B, various implementations of switching PHY devices according to the present disclosure are shown. These switching PHY devices perform switching after signals have been terminated, in contrast to the prior art, such asFIGS. 15A-15B. In addition, these switching PHY devices do not implement an entire duplicate PHY associated with the docking station602, as does another switching system of the prior art, depicted inFIGS. 16A-16B.

More particularly,FIGS. 18A-21Bdepict various switching PHY devices according to the principles of the present disclosure. FIGs. having a B suffix depict exemplary schematic implementations of FIGs. having an A suffix. InFIGS. 18A and 20A, the transmitters and receivers implement transformerless hybrids, whileFIGS. 19A and 21Ainclude external hybrids, such as magnetic hybrids.

FIGS. 18A and 19Ainclude switch modules shared by the transmitter and receiver, whileFIGS. 20A and 21Ainclude separate switch modules for the transmitter and receiver.FIGS. 22A-22Binclude switching functionality integrated into the transmitter and into the receiver.FIGS. 23-25Bpresent exemplary schematic implementations of components ofFIGS. 22A-22B.

Referring now toFIG. 18A, a functional block diagram of an exemplary switching network interface according to the principles of the present disclosure is presented. The first and second network connectors604and606communicate with first and second transformers702and704, respectively. The first and second transformers702and704communicate with first and second termination networks706and708, respectively.

The first and second termination networks706and708may include resistances and/or reactive components. A switch710communicates with the first and second termination networks706and708. The switch710selectively couples one of the first and second termination networks706and708to both a transmitter712and a receiver714. A control module716transmits data to the transmitter712and receives data from the receiver714.

The control module716communicates with the MAC device612. The control module716controls the switch710to select one of the first and second network connectors604and606. The control module716also performs processing tasks associated with the physical layer. These tasks may include modulation, line coding, error correction coding, bit synchronization, signaling and flow control, carrier sense and collision detection, equalization filtering, pulse shaping, and other signal processing of physical signals.

The transmitter712and the receiver714implement a transformerless hybrid, whereby a hybrid feedback signal is output by the transmitter712to the receiver714. The hybrid feedback signal allows the receiver714to filter out the contribution of the transmitter712from a combined transmit and receive signal when operating in full-duplex mode.

According to the present disclosure, an integrated circuit may integrate the first termination network706, the switch710, the transmitter712, the receiver714, and/or the control module716. The integrated circuit may also integrate switching modules, additional termination networks, hybrids, and/or transformers.

Referring now toFIG. 18B, an exemplary functional schematic diagram of the switching network interface ofFIG. 18Ais presented. For purposes of illustration, a transmission line720is connected to the first network connector604. While the transmission line720is shown as a single twisted pair, the teachings of the present disclosure apply to multiple twisted pairs.

Multiple twisted pairs, such as are used in Gigabit Ethernet, may be switched using similar circuit structures that are controlled in parallel. The first and second network connectors604and606communicate with the first and second transformers702and704, respectively. The first and second transformers702and704communicate with the first and second termination networks706and708, respectively.

The transistors724may be metal oxide semiconductor field-effect transistors (MOSFETs), and may have control terminals and first and second terminals. The first and second terminals of the first transistor724-1communicate with the first and second ends of the second termination network708via the first and second resistances722-1and722-2, respectively.

The first and second terminals of the second transistor724-2communicate with the first and second ends of the first termination network706via the third and fourth resistances722-3and7224, respectively. The first terminals of the third and fourth transistors724-3and724-4communicate with the second and first terminals of the first transistor724-1via the fifth and sixth resistances722-5and722-6, respectively.

The first terminals of the fifth and sixth transistors724-5and724-6communicate with the second and first terminals of the second transistor724-2via the seventh and eighth resistances722-7and722-8, respectively. A current source Itx730includes first and second ends and provides a transmit current Itx. First and second ends of the current source Itx730communicate with the first and second terminals of the first transistor724-1via the seventh and eighth transistors724-7and724-8.

The first and second terminals of the current source Itx730communicate with the first and second terminals of the second transistor724-2via the ninth and tenth transistors724-9and724-10, respectively. A voltage Vtx732is measured across the first and second terminals of the current source Itx730. A control signal is received by the switch710and communicated to the control terminals of the second, fourth, third, seventh, and eighth transistors724-2,724-3,724-4,724-7, and724-8.

The control signal may be inverted by an inverter734, whose output is communicated to the first, fifth, sixth, ninth, and tenth transistors724-1,724-5,724-6,724-9, and724-10. In various implementations, the first, second, seventh, eighth, ninth, and tenth transistors724-1,724-2,724-7,724-8,724-9, and724-10may be PMOS transistors. In various implementations, the third, fourth, fifth, and sixth transistors724-3,724-4,724-5, and724-6may be NMOS transistors.

When the control signal is high, the first network connector604is connected to the current source Itx730via the ninth and tenth transistors724-9and724-10. Meanwhile, the seventh and eighth transistors724-7and724-8disconnect the second network connector606from the current source Itx730. The first transistor724-1shorts together the first and second resistances722-1and722-2coming from the second network connector606.

In addition, the third and fourth transistors724-3and7244tie the second ends of the first and second resistances722-1and722-2to ground. When the polarity of the control signal is reversed, the transistors724assume opposite roles and the second network connector606is connected to the current source Itx730while the first network connector604is grounded.

Referring now toFIG. 19A, a functional block diagram of a switching network interface according to the principles of the present disclosure including a hybrid is depicted. The switch710communicates with a hybrid750. The hybrid750communicates transmit signals from a transmitter752to the switch710. The hybrid750communicates received signals from the switch710to a receiver754without including the transmit signals from the transmitter752. The hybrid750thus allows full duplex communication by separating out received signals from the transmit signals going to the switch710.

Referring now toFIG. 19B, an exemplary functional schematic diagram of the switching network interface ofFIG. 19Ais presented. The hybrid750separates transmit signals, as represented by the current source Itx730, from received signals, as represented by the voltage Vtx732. The hybrid750communicates with the seventh, eighth, ninth, and tenth transistors724-7,724-8,724-9, and724-10.

Referring now toFIG. 20A, a functional block diagram of an exemplary switching network interface according to the principles of the present disclosure including separate transmitter/receiver switches is presented. The control module716controls operation of first and second switch modules802and804. The first switch module802selectively connects the first and second termination networks706and708to the receiver714.

The second switch module804selectively connects the first and second termination networks706and708to the transmitter712. The transmitter712and the receiver714implement a transformerless hybrid. In various implementations, the transmitter712communicates a hybrid feedback signal to the receiver714. This hybrid feedback signal may be proportional to the transmit signal generated by the transmitter712. The receiver714can then remove the effect of the transmit signal from the combined transmit/receive signal to obtain a receive signal.

Referring now toFIG. 20B, an exemplary functional schematic diagram of the switching network interface ofFIG. 20Ais presented. The first and second network connectors604and606accept connection of the transmission line720. For purposes of illustration, the transmission line720is shown connected to the first network connector604.

The first and second network connectors604and606communicate with the first and second transformers702and704, respectively. The first and second ends of the first transformer702communicate with the first and second ends of the first termination network706, depicted graphically as a resistance. The first and second ends of the second transformer704communicate with the first and second ends of the second termination network708, depicted graphically as a resistance.

The first and second switch modules802and804include first, second, third, fourth, fifth, sixth, seventh, and eighth switches820-1,820-2,820-3,820-4,820-5,820-6,820-7, and820-8. The first and second switches820-1and820-2selectively connect first and second outputs of a first amplifier822to the first and second ends of the second termination network708, respectively.

The third and fourth switches820-3and820-4selectively connect the first and second outputs of the first amplifier822to the first and second ends of the first termination network706. The fifth and sixth switches820-5and820-6selectively connect first and second inputs of a second amplifier824to first ends of first and second resistances826-1and826-2, respectively.

Opposite ends of the first and second resistances826-1and826-2communicate with the first and second ends of the second termination network708. The seventh and eighth switches820-7and820-8selectively connect the first and second inputs of the second amplifier824to first ends of third and fourth resistances826-3and826-4, respectively. Opposite ends of the third and fourth resistances826-3and826-4communicate with the first and second ends of the first termination network706.

The current source Itx730is applied to first and second inputs of the first amplifier822. The voltage Vtx732is measured from first and second outputs of the second amplifier824. A fifth resistance834communicates with the first input and the first output of the first amplifier822. A sixth resistance836communicates with the second input and the second output of the first amplifier822.

A seventh resistance838communicates with the first output and the first input of the second amplifier824. An eighth resistance840communicates with the second output and the second input of the second amplifier824. The switches820determine which one of the first and second network connectors604and606will be connected to the first and second amplifiers822and824.

To select the first network connector604, the third, fourth, seventh, and eighth switches820-3,820-4,820-7, and820-8are closed, as shown inFIG. 20B. Meanwhile, the first, second, fifth, and sixth switches820-1,820-2,820-5, and820-6are opened. A common mode feedback module848communicates with the first and second inputs of the second amplifier824. The common mode feedback module848is optional, as indicated by the dashed lines. The common mode feedback module848may be used to shift incoming signals to a voltage range that is more compatible with a device receiving the voltage Vtx732. An exemplary implementation of the common mode feedback module848is depicted inFIG. 7.

Referring now toFIG. 21A, a functional block diagram of an exemplary switching network interface according to the principles of the present disclosure including separate transmitter/receiver switches and hybrids is presented. The control module716controls operation of the first and second switch modules802and804. The first switch module802selectively connects a first hybrid852and a second hybrid854to the receiver754. The second switch module804selectively connects the first and second hybrids852and854to the transmitter752. The first and second hybrids852and854communicate with the first and second termination networks706and708, respectively.

Referring now toFIG. 21B, an exemplary functional schematic diagram of the switching network interface ofFIG. 21Ais presented. The first hybrid852communicates with the first termination network706and with the first and second switch modules802and804. The second hybrid854communicates with the second termination network708and with the first and second switch modules802and804.

Referring now toFIG. 22A, a functional block diagram of an exemplary switching network interface with switching functionality integrated into the transmitter and receiver according to the principles of the present disclosure is presented. A switching transmitter902includes a transmitter front-end904and a switching output stage906. The switching output stage communicates with the first and second termination networks706and708.

The switching output stage906includes output drivers that selectively output signals from the transmitter front-end904to the first and second termination networks706and708. The switching output stage906also outputs a copy of the signals from the transmitter front-end904to a transmitter replica908. The transmitter replica908may be included within the switching transmitter902.

The transmitter replica908outputs transmit signals to first ends of first and second resistances910and912. The node at which the switching output stage906communicates with the first termination network706and the node at which the switching output stage906communicates with the second termination network708communicate with first ends of third and fourth resistances914and916, respectively.

Opposite ends of the second and third resistances912and914communicate with each other and with a first switch918. Opposite ends of the first and fourth resistances910and916communicate with each other and with a second switch920. The first and second switches918and920selectively connect their inputs to an inverting amplifier922. The first and second switches918and920together form a switch module923.

The inverting amplifier922outputs an amplified signal to a receiver back end924. The receiver back-end924communicates data to the control module716, which communicates data to the transmitter front-end904. The inverting amplifier922serves as a summing amplifier. When the first switch918is conducting and the second switch920is non-conducting, the inverting amplifier922sums signals from the transmitter replica908and the first termination network706.

These signals are received at the first switch918via the second and third resistances912and914, respectively. When the second switch920is conducting and the first switch918is non-conducting, the inverting amplifier922sums the signals from the transmitter replica908and the second termination network708. These signals are received at the second switch920via the first and fourth resistances910and916, respectively.

The inverting amplifier922, the receiver back-end924, the switches918and920, and the resistances910,912,914, and916form a switching receiver926. The switching receiver926may include the transmitter replica908, and may be integrated with the switching transmitter902and/or the control module716. In addition, the first and/or second termination networks706and708may be integrated with the switching transmitter902and/or the switching receiver926.

Voltages at the first and second termination networks706and708may exceed the operating limits of the first and second switches918and920. For instance, operating limits of the first and second switches may be limited by their size or by their power supply voltage. The inputs to the first and second switches918and920, however, are summing nodes. The voltages experienced by the first and second switches918and920have therefore been reduced by transmit signals, such as from the transmitter replica908. This reduces the power supply and power handling requirements of the switches918and920, allowing them to be smaller, use lower power supplies, and be more easily integrated into an integrated circuit.

Referring now toFIG. 22B, a functional block diagram of an exemplary switching network interface including hybrids and having switching functionality integrated with the transmitter and receiver according to the principles of the present disclosure is presented. A switching transmitter928includes the transmitter front-end904and a switching output stage930, which may be similar to the switching output stage906ofFIG. 22A. The switching output stage930communicates with the first and second hybrids852and854.

The first hybrid852communicates transmit signals from the switching output stage930to the first termination network706and communicates receive signals from the first termination network706to a first switch932. The second hybrid854communicates transmit signals from the switching output stage930to the second termination network708and communicates received signals from the second termination network708to a second switch934.

The first and second switches932and934form a switch module935and may be similar to the first and second switches918and920ofFIG. 22A. A switching receiver931includes the first and second switches932and934, an amplifier936, and the receiver back-end924. The first and second switches932and934selectively connect the first and second hybrids852and854, respectively, to the amplifier936. The amplifier936communicates amplified signals to the receiver back-end924.

Referring now toFIG. 23, a functional schematic diagram of an exemplary switching output stage, such as the switching output stage906ofFIG. 22Aor the switching output stage930ofFIG. 22B, according to the principles of the present disclosure is presented. Transmitters often include cascode transistors to protect the drive transistors of the transmitter. As described below, these cascode transistors can be used to switch the output of the transmitter. Because cascode transistors are already present, this approach adds very little capacitive load to the transmitter.

The first and second network connectors604and606communicate with the first and second transformers702and704. For purposes of illustration, the transmission line720is connected to the first network connector604. The first termination network706ofFIG. 22Ais represented here as first and second termination resistances940and942. The first and second termination resistances940and942communicate between a supply potential and the first and second ends of the first transformer702, respectively.

The second termination network708ofFIG. 22Ais represented as third and fourth termination resistances944and946. The third and fourth termination resistances944and946communicate between the supply potential and the first and second ends of the second transformer704, respectively. First, second, third, fourth, fifth, and sixth transistors950-1,950-2,950-3,950-4,950-5, and950-6may be metal oxide semiconductor field-effect transistors (MOSFETs) that have control terminals and first and second terminals.

The first terminals of the first and second transistors950-1and950-2communicate with the first and second ends of the second transformer704, respectively. The first terminals of the third and fourth transistors950-3and950-4communicate with the first and second terminals of the first transformer702, respectively.

The second terminals of the first and third transistors950-1and950-3communicate with the first terminal of the fifth transistor950-5. The second terminals of the second and fourth transistors950-2and950-4communicate with the first terminal of the sixth transistor950-6. The first and second transistors950-1and950-2are arranged as cascode transistors and their control terminals receive a first cascode voltage.

When the first cascode voltage is lowered, the first and second transistors950-1and950-2turn off, disconnecting the second transformer704from the fifth and sixth transistors950-5and950-6. The third and fourth transistors950-3and9504are arranged as cascode transistors and their control terminals receive a second cascode voltage. When the second cascode voltage is lowered, the third and fourth transistors950-3and9504turn off, disconnecting the first transformer702from the fifth and six transistors950-5and950-6. The first and second cascode voltages therefore control whether signals are transmitted to the first and second network connectors604and606.

The fifth and sixth transistors950-5and950-6are drive transistors whose control terminals communicate with outputs of first and second operational amplifiers960and962, respectively. Non-inverting inputs of the first and second operational amplifiers960and962receive first and second differential voltages from the transmitter front-end904ofFIG. 22A.

Inverting inputs of the first and second operational amplifiers960and962communicate with the second terminals of the fifth and sixth transistors950-5and950-6, respectively. The second terminals of the fifth and sixth transistors950-5and950-6communicate with a ground potential via first and second resistances964-1and964-2, respectively.

Referring now toFIG. 24, a functional schematic diagram of an exemplary switching receiver, such as the switching receiver926ofFIG. 22A, according to the principles of the present disclosure is presented. The first and second ends of the first termination network706communicate with first ends of first and second resistances1010-1and1010-2.

The first and second ends of the second termination network708communicate with first ends of third and fourth resistances1010-3and1010-4, respectively. The transmitter replica908is shown with a differential output including first and second signals. The first output signal of the transmitter replica908communicates with first ends of fifth and sixth resistances1012-1and1012-2.

The second output signal of the transmitter replica908communicates with first ends of seventh and eighth resistances1012-3and1012-4. The first switch918ofFIG. 22Amay be composed of first and second transistors1014-1and1014-2. The second switch920ofFIG. 22Amay be composed of third and fourth transistors1016-1and1016-2.

The transistors1014and1016may be metal oxide semiconductor field-effect transistors (MOSFETs) that have control terminals and first and second terminals. The first terminal of the first transistor1014-1communicates with second ends of the first and sixth resistances1010-1and1012-2. The first terminal of the second transistor1014-2communicates with second ends of the second and eighth resistances1010-2and1012-4.

The first terminal of the third transistor1016-1communicates with second ends of the third and fifth resistances1010-3and1012-1. The first terminal of the fourth transistor1016-2communicates with second ends of the fourth and seventh resistances1010-4and1012-3. The second terminals of the first and third transistors1014-1and1016-1communicate with a first input of an amplifier1020.

The second terminals of the second and fourth transistors101-4-2and1016-2communicate with a second input of the amplifier1020. First and second outputs of the amplifier1020communicate with the receiver back-end924. A ninth resistance1022-1communicates with the first input and the first output of the amplifier1020. A tenth resistance1022-2communicates with the second input and the second output of the amplifier1020.

A control signal is received from the control module716ofFIG. 22Aby the control terminals of the third and fourth transistors1016-1and1016-2. The control signal may be inverted by an inverter1024before being communicated to the control terminals of the first and second transistors1014-1and1014-2. The first and second transistors1014selectively connect the first termination network706to the amplifier1020. The third and fourth transistors1016-1and1016-2selectively connect the second termination network708to the amplifier1020.

Referring now toFIG. 25A, a functional schematic of a transmitter replica, such as the transmitter replica908ofFIG. 22A, according to the principles of the present disclosure is presented. A transmit current source Itx1050includes first and second terminals that communicate with first ends of first and second resistances1052and1054, respectively. Second ends of the first and second resistances1052and1054communicate with a supply potential. A replica transmit voltage Vtx1056is measured between the first ends of the first and second resistances1052and1054.

The resistance value of the first and second resistances1052and1054may be equal or proportional to that of the termination resistances940,942,944, and946ofFIG. 23. The current provided by the current source Itx1050may be equal or inversely proportional to that sourced by the fifth and sixth transistors950-5and950-6ofFIG. 23. In this way, an inversely proportional current is applied to proportional resistances, and the measured replica transmit voltage Vtx1056should be approximately equal to the actual voltage transmitted through the transmission line.

Referring now toFIG. 25B, a functional schematic diagram of another exemplary transmitter replica according to the principles of the present disclosure is presented. The transmitter replica908includes an amplifier1080having first and second inputs and first and second outputs. First ends of first and second resistances1082-1and1082-2communicate with the inverting inputs of the first and second operational amplifiers960and962ofFIG. 23, respectively.

Opposite ends of the first and second resistances1082-1and1082-2communicate with the first and second inputs of the amplifier1080. Third and fourth resistances1084-1and1084-2communicate with the first and second inputs and the first and second outputs of the amplifier1080, respectively. A replica transmit voltage Vtx1086is measured between the first and second outputs of the amplifier1080.

Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present disclosure can be implemented in a variety of forms. Therefore, while this disclosure has been described in connection with particular examples thereof, the true scope of the disclosure should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.