Method of and system for handling conference calls in digital telephone exchange

A telephone exchange linked via PCM channels with subscribers engaged in a conference call includes switching circuits for transmitting to each participating subscriber, during an assigned time slot, the albegraic sum of the digitized voice-current samples from all the other participants. The digitized samples are logarithmically coded, each code consisting of a polarity bit, three range bits and four quantum bits; in order to facilitate correct addition or subtraction of the quantum bits of two codes to be summed (unless these codes signify the two lowest-ranking ranges), according to whether their sign bits are identical or different, the quantum bits of a lower-ranking code are shifted in a register toward less significant bit positions in which they would have their original numerical weight when prefaced by the range bits of the higher-ranking code. The range bits are not summed but only those of the higher-ranking code are preserved, their numerical value being incremented by one in the case of addition but left unchanged or decremented by one (if a negative carry is present) in the case of subtraction. If the difference in rank exceeds the number of quantum bits, i.e. four, the lower-ranking code is ignored.

FIELD OF THE INVENTION 
Our present invention relates to a method of and a system for handling 
conference calls among three or more telephone subscribers in a central 
office or exchange of digital type linked with these subscribers by 
pulse-code-modulation (PCM) channels. 
BACKGROUND OF THE INVENTION 
The digitization of voice samples in time-division-multiplex (TDM) 
telecommunication systems is well known. Thus, a code word of 12 bits -- 
including a polarity-indicating sign bit -- can be used to express 
2.sup.11 = 2048 distinct amplitude levels of a bipolar signal divided into 
eight ranges which are of identical widths on a logarithmic scale, i.e. a 
lowest range of 0- 15 units (e.g. millivolts), a second range of 16- 31 
units, a third range of 32- 63 units etc., up to a highest range of 1024- 
2047 units. As taught in commonly owned U.S. Pat. Nos. 3,755,808 and 
3,789,392 issued in the name of Giampiero Candiani, such ordinary digital 
code words can be compressed into eight-bit codes and then re-expanded 
into their original 12 bits, with only minor loss of information, by 
expressing the rank of each code -- i.e. the order number of its amplitude 
range -- in binary form by means of three range bits which immediately 
follow the sign bit and are in turn succeeded by four quantum bits X, Y, 
Z, W representing the most significant bits following directly after the 
first "one" (or after the eighth "zero" in the case of the lowermost 
range) in the original code word. In more general terms, such a compressed 
code word consists in descending order of a sign or polarity bit, m range 
bits and n quantum bits. 
A peculiarity of this type of compressed code word is the fact that the 
numerical weight of its quantum bits doubles from the second-lowest to the 
highest range while being the same in the two lowermost ranges. This 
prevents the direct positive or negative algebraic summing (i.e. adding or 
subtracting) of the range bits of two such codes, derived from a pair of 
coincident voice samples, unless they happen to be either of the same rank 
or of the two lowest ranks, referred to hereinafter as rank 0 and rank 1. 
Such algebraic summation is necessary in a conference call in which each 
participating subscriber is to receive superposed voice samples from all 
the other participants. It has therefore been the practice, in an exchange 
serving PCM channels of this type engaged in a conference call, to expand 
the incoming compressed codes for linear superposition and to recompress 
the resulting codes for transmission to PCM terminals serving the 
receiving subscribers. Such double conversion requires complex and 
correspondingly expensive central-office equipment. 
OBJECT OF THE INVENTION 
The object of our present invention, therefore, is to provide a simplified 
method of and system for linearly superposing significant portions of such 
logarithmically coded voice samples without expansion and recompression. 
SUMMARY OF THE INVENTION 
This object is realized, in accordance with our present invention, by 
separately storing a higher-ranking code and a lower-ranking code which 
are to be arithmetically combined, downshifting the quantum bits of the 
lower-ranking code to less significant bit positions in which they would 
have their original numerical weights if prefaced by the range bits of the 
higher-ranking code, comparing the polarity bits of the two codes, and 
subjecting the quantum bits of the higher-ranking code and the downshifted 
bits of the lower-ranking code to an algebraic summing operation of 
positive or negative sign, i.e. addition or subtraction, depending on the 
relative values of the corresponding polarity bits. 
Since homologous quantum bits of codes of rank 0 and rank 1 have the same 
numerical weight, such a downshift will not occur if neither code has a 
rank higher than 1. Therefore, if the numerical difference of their ranks 
-- as expressed by their respective combinations of range bits -- has a 
value .DELTA.t, the downshifting will be by a number of bit positions 
equal to .DELTA.t except where the lower-ranking code is of rank 0; in the 
latter case, the number of bit positions involved in the shift will be 
.DELTA.t - 1. 
By this downshifting operation we achieve a linearization of the quantum 
bits, i.e. of the significant bits X, Y, Z, W according to the 
above-identified Candiani patents, which are predominantly responsible for 
the transmission of voice frequencies and whose linear superposition is 
therefore essential for conference-type telephone communication. No such 
high fidelity is needed for the range bits, especially if one of two 
simultaneously speaking subscribers has a substantially louder voice than 
the other. It will generally be sufficient, as we shall demonstrate 
hereinafter, to disregard the range bits of the lower-ranking code in 
forming the algebraic sum and to preserve only those of the higher-ranking 
code in a composite code resulting from the summing operation, with 
possible incrementation or decrementation of their numerical value by one. 
With additive summing, we prefer increasing the range number by +1 in all 
instances except where both codes are of rank 0, along with a compensatory 
downshifting of the resultant quantum bits by one bit position. If the 
lower-ranking code has the rank 0, or if the ranks of the two codes are 
identical, this procedure is equivalent to linear addition of the entire 
codes. A positive carry produced by the adding of the quantum bits is 
accommodated in a bit position vacated by the last-mentioned downshift. 
With subtractive summing, conversely, a change in the range number of the 
higher-ranking code by -1 is necessary only when the calculation of the 
numerical difference of the two sets of quantum bits yields a negative 
carry; this decrease in the numerical value of the preserved range bits is 
to be compensated by a corresponding upshifting of the resultant quantum 
bits by one bit position, except in the case where the higher-ranking code 
is of rank 1 so that the downshift does not change the numerical weight of 
the quantum bits. 
A system for carrying out this method comprises code-receiving means with 
two storage circuits, each including a first register for storing polarity 
and range bits and a second register for storing quantum bits of 
respective codes to be arithmetically combined, a first arithmetic unit 
connected to the first register for determining the difference in ranks 
between the two codes, linearization means connected to the second 
register and controlled by this arithmetic unit for carrying out the 
aforedescribed downshift of the quantum bits of the lower-ranking code, a 
second arithmetic unit connected to the second register and controlled by 
the contents of the first register for additive or subtractive summing of 
the two sets of quantum bits respectively held in the second registers of 
the two storage circuits, and evaluation means connected to the two 
arithmetic units for deriving a composite code from the range bits of the 
higher-ranking code and the quantum bits resulting from the algebraic 
summing operation. In the preferred embodiment or our invention more 
particularly described hereinafter, the evaluator includes a memory 
controlled by a program counter whose operation may be modified by 
associated logical circuitry under certain conditions such as, for 
example, the presence of two codes of rank 0 or the absence of a carry.

SPECIFIC DESCRIPTION 
FIG. 1 illustrates three telephone subscribers T.sub.1, T.sub.2 and T.sub.3 
assumed to be engaged in a conference call. For the sake of simplicity 
these subscribers have been shown as connected to a common terminal CT 
linked by outgoing and incoming PCM/TDM channels with a remote transit 
exchange TR, even though in practice such an exchange generally will not 
intervene in calls among subscribers served by the same terminal. Voice 
signals A, B and C respectively sent out by the three intercommunicating 
subscribers are converted in terminal CT, with the aid of a coder CC, into 
compressed eight-bit codes of the type discussed above and described in 
the two Candiani patents referred to. The coded signals are transmitted in 
respective channels (not necessarily consecutive, as indicated) of a PCM 
frame to a switching network RT of transit exchange TR which forwards 
them, in adjoining time slots, to a conference circuit CF where the codes 
are algebraically combined in conformity with our invention for 
retransmission, again via network RT, to terminal CT in combinations B+C, 
A+C and A+B in channels assigned to them by the network. A decoder ED 
reconverts these composite eight-bit compressed codes into analog signals 
and sends them on to their respective destinations, i.e. signals B+C to 
subscriber T.sub.1, signals A+C to subscriber T.sub.2 and signals A+B to 
subscriber T.sub.3. The compounding of each pair of codes in circuit CF 
takes place in the course of an eight-bit time slot so that, in principle, 
all the subscribers using the available PCM channels could participate 
simultaneously in three-way or possibly four-way conference calls. 
In FIG. 2 we have shown the conference circuit CF of FIG. 1 as comprising 
an input unit UI receiving incoming codes on a lead label "in", and 
working into a preprocessor UP feeding range bits to a first processor UT 
and quantum bits to a second processor US. The two processors deliver the 
results of their operations to an output unit UU which periodically 
discharges the composite codes via a lead labeled "out". The three 
processing units UP, UT and US form part of an evaluation section which 
also includes an operating unit UO coacting therewith. 
Input unit UI, illustrated more fully in FIG. 3, is under the control of a 
timer including a frequency divider DF to which clock pulses CK.sub.4 are 
fed from a nonillustrated generator with a cadence equaling twice the bit 
rate. Divider DF halves this cadence so as to produce a train of pulses 
CK.sub.2 which step an 8-bit pulse counter CN.sub.1 reaching its full 
count with the arrival of the last bit of the code word in a time slot of 
a periodically recurring PCM frame assumed to contain 32 such time slots, 
each recurrent time slot constituting a TDM transmission channel as is 
well known per se. Another pulse counter CN.sub.2 of 32-pulse capacity is 
stepped by the counter CN.sub.1 at the beginning of each new time slot to 
count the 32 channels. The several stage outputs of counter CN.sub.2 are 
connected to a read-only memory RI which energizes a different output lead 
during each time slot of a frame, only six output leads z.sub.1 -- z.sub.6 
having been illustrated. 
The bits of a code successively arriving over input lead "in" are fed in 
parallel to a number of registers of which only three, labeled RS.sub.1, 
RS.sub.2 and RS.sub.3, have been illustrated. These registers are provided 
with enabling inputs including respective AND gates N.sub.1, N.sub.2, 
N.sub.3 each receiving the clock pulses CK.sub.2. The other inputs of 
these AND gates are respectively connected to output leads z.sub.1, 
z.sub.2 and z.sub.3 of memory RI whereby only one register receives the 
clock pulses CK.sub.2 in the course of a given time slot. In the case here 
assumed, register RS.sub.1 is serially loaded in the first time slot of a 
frame with the coded voice sample A (see FIG. 1), registers RS.sub.2 and 
RS.sub.3 respectively receiving the codes B and C during the 
next-following two time slots. In response to a start pulse SP emitted by 
counter CN.sub.1 upon the completion of its count, registers RS.sub.1, 
RS.sub.2 and RS.sub.3 are discharged in parallel over respective 8-lead 
multiples into associated registers RS'.sub.1, RS'.sub.2 and RS'.sub.3, 
respectively, so as to become available for the storage of new codes in 
the following cycle. The bits stored in ancillary registers RS'.sub.1, 
RS'.sub.2 and RS'.sub.3 are serially read out, under the control of memory 
outputs z.sub.4 - z.sub.6 as described below, via leads y.sub.1, y.sub.2 
and y.sub.3 extending to a pair of multiplexers MX.sub.1 and MX.sub.2 
forming part of preprocessor UP as shown in FIG. 4. 
Multiplexer MX.sub.1 has two inputs connected to output lead y.sub.1 of 
register RS'.sub.1 and a third input connected to output lead y.sub.2 of 
register RS'.sub.2. Multiplexer MX.sub.2 has two inputs connected to 
output lead y.sub.3 of register RS'.sub.3 and a third input connected to 
output lead y.sub.2 of register RS'.sub.2. Both multiplexers are 
simultaneously switchable by signals on leads z.sub.4, z.sub.5 and z.sub.6 
to direct the bits of a selected pair of stored codes to their respective 
outputs, i.e. codes B and C upon the energization of lead z.sub.4, codes A 
and C upon the energization of lead z.sub.2 and codes A and B upon the 
energization of lead z.sub.6. The following discussion will be limited to 
the period of energization of lead z.sub.6, this being the time slot 
during which the composite code A + B is to be produced for transmission 
via PCM terminal CT to subscriber T.sub.3 as described above with 
reference to FIG. 1. 
The bits of codes A and B are thus concurrently read out, in sequence, from 
multiplexers MX.sub.1 and MX.sub.2 into respective branches of 
preprocessor UP, i.e. a first branch including two registers T.sub.a, 
H.sub.a and a second branch including two registers T.sub.b, H.sub.b. 
Registers T.sub.a and T.sub.b are of 4-bit capacity designed to 
accommodate the polarity bit S.sub.a or S.sub.b and the three range bits 
of their respective codes, collectively designated t.sub.a, t.sub.b . 
Registers H.sub.a and H.sub.b also have four stages each, designed to 
receive the quantum bits of their respective codes, collectively 
designated h.sub.a, h.sub.b, as well as a fifth stage for the storage of a 
supplemental bit f.sub.a, f.sub.b indicating by its presence that the 
corresponding code is of a rank higher than zero. This fifth stage is 
shown only for convenience as part of register H .sub.a or H.sub.b but may 
in fact be considered a separate 1-bit store. The contents of the other 
four stages, containing the quantum bits, are shiftable to the right under 
the control of respective signals K.sub.1 or K.sub.2 for the purpose and 
under the conditions described hereinafter, such a shift occurring upon 
the occurrence of basic clock pulses CK.sub.4. These four stages can also 
be immediately emptied by means of clearing pulses K.sub.1 ' and K.sub.2 
', respectively. 
The writing inputs of registers T.sub.a and T.sub.b are connected directly 
to the outputs of the associated multiplexers MX.sub.1 and MX.sub.2 
whereas the writing inputs of registers H.sub.a and H.sub.b are connected 
to the same outputs by way of further multiplexers MX.sub.3 and MX.sub.4. 
The loading of these registers is controlled by timing signals issuing 
from a read-only memory RP in unit UO controlled by a program counter CP 
as shown in FIG. 8. More specifically, registers T.sub.a and T.sub.b are 
loaded under the control of a signal c.sub.1 whereas registers H.sub.a and 
H.sub.b are loaded under the control of a subsequent signal c.sub.3 in the 
presence of a switching signal c.sub.2 controlling the multiplexers 
MX.sub.3 and MX.sub.4. The range bits t.sub.a and t.sub.b appearing in 
three of the four stage outputs of registers t.sub.a and t.sub.b are fed 
to three comparators ID.sub.1, ID.sub.2 and ID.sub.3 serving to identify 
the respective codes A and B in terms of relative rank. Comparators 
ID.sub.1 and ID.sub.2 have a threshold level 0 so as to emit respective 
signals t.sub.a &gt; 0 and t.sub.b &gt; 0 if these codes are of other than rank 
-0. These two signals are applied to respective inputs of a pair of AND 
gates N.sub.4 and N.sub.5 also receiving a control signal c.sub.5 from 
memory RP of FIG. 8; AND gates N.sub.4 and N.sub.5 are connectable via 
multiplexers MX.sub.3 and MX.sub.4 upon the disappearance of signal 
c.sub.2, to the writing inputs of registers H.sub.a and H.sub.b to store 
therein the bits f.sub.a and f.sub.b if the respective comparators 
ID.sub.1 and ID.sub.2 have an output. The third comparator ID.sub.3 
receives both sets of range bits t.sub.a and t.sub.b to energize one of 
three output leads with a respective signal t.sub.a &gt; t.sub.b, t.sub.a = 
t.sub.b or t.sub.a &lt; t.sub.b, collectively designated t. A fourth 
comparator ID.sub.4 receives the two sets of quantum bits h.sub.a and 
h.sub.b from registers H.sub.a and H.sub.b, energizing one of three output 
leads with a respective signal h.sub.a &gt; h.sub.b, h.sub.a = h.sub.b or 
h.sub.a &lt; h.sub.b, collectively designated h. 
Processor UT, shown in FIG. 5, comprises two multiplexers MX.sub.5 and 
MX.sub.6 receiving the range bits t.sub.a and t.sub.b in parallel from 
registers T.sub.a and T.sub.b. These multiplexers, whose inputs are 
simultaneously switchable by a signal f.sub.c generated by a logic network 
RL, work into respective inputs x.sub.1 and x.sub.2 of an arithmetic unit 
AU. Logic network RL receives the output signals t.sub.a &gt; 0, t.sub.b &gt; 0. 
t and h from comparators ID.sub.1 and ID.sub.4 as well as a control signal 
c.sub.4 from memory RP (FIG. 8) and the output of arithmetic unit AU which 
is either the numerical difference .DELTA.t of the bit combinations fed to 
its inputs x.sub.1 and x.sub.2 or only the numerical value t* of the 
combination of range bits at input x.sub.1, depending on the absence or 
presence of a timing signal c.sub.6 delivered to an inverting input of an 
AND gate N.sub.10 which is interposed between multiplexers MX.sub.6 and 
input x.sub.2. Switching signal f.sub.c comes into existence whenever the 
combination of bits t.sub.a and h.sub.a has a numerical value larger than 
that of the combination of bits t.sub.b and h.sub.b, i.e. when the 
absolute magnitude of the coded signal A exceeds that of the coded signal 
B. Thus, 
EQU f.sub.c = (t.sub.a &gt; t.sub.b) + (t.sub.a = t.sub.b) .multidot. (h.sub.a &gt; 
h.sub.b) (1) 
with f.sub.c = 1, bit groups t.sub.a and t.sub.b are respectively supplied 
to inputs x.sub.1 and x.sub.2 ; with f.sub.c = 0 the converse is the case. 
Unit AU, accordingly, always received the range bits of the code of larger 
absolute magnitude on its input x.sub.1 and those of the code of smaller 
absolute magnitude on its input x.sub.2. If the two codes happen to be of 
equal magnitude, the position of the multiplexers will be immaterial; in 
that case, as will be described hereinafter, the arithmetic unit AU does 
not intervene in this operating phase in which c.sub.6 = 0. 
The values .DELTA.t and t* issuing in different operating phases from unit 
AU are loaded, under the control of a signal c.sub.7 from memory RP, into 
a reversible counter CS designed to be stepped backward by clock pulse 
CK.sub.4 in the presence of signal c.sub.4 applied to a countdown input 
thereof. Counter CS also has a "subtract 1" input, energizable by an 
output signal a.sub.8 of a logic network LR of unit UO (FIG. 8), and an 
"add 1" input, energizable via an AND gate N.sub.6 by a control signal 
c.sub.13 from memory RP in the presence of a signal i.sub.s indicating 
identity of the polarity bits s.sub.a, s.sub.b as determined by an 
Exclusive-OR gate EO in unit US (FIG. 6). Counter CS has three outputs 
delivering range bits Q.sub.2, Q.sub.3 and Q.sub.4 to an eight-bit final 
register RC of output unit UU shown in FIG. 7. The three counter outputs 
are further connected to logic network RL and to three logic gates in 
parallel, namely a NOR gate O.sub.1, an AND gate N.sub.8 with two 
inverting inputs for bits Q.sub.2 and Q.sub.3, and an AND gate N.sub.9 
without inverting inputs. NOR gate O.sub.1 generates a signal 
EQU i.sub.0 = Q.sub.2 .multidot. Q.sub.3 .multidot. Q.sub.4 (2) 
whenever the count of component CS is 0. AND gate N.sub.8 generates a 
signal 
EQU i.sub.1 = Q.sub.2 .multidot. Q.sub.3 .multidot. Q.sub.4 (3) 
when the count has a value of 1. AND gate N.sub.9 generates a signal 
EQU i.sub.7 = Q.sub.2 .multidot. Q.sub.3 .multidot. Q.sub.4 (4) 
in the presence of a maximum count of numerical value 7. 
Signals K.sub.1 and K.sub.2, designed to cause a downshift of the quantum 
bitsh.sub.a and h.sub.b in registers H.sub.a and H.sub.b of FIG. 4, can be 
expressed by 
EQU K.sub.1 = c.sub.4 .multidot. (t.sub.a &lt; t.sub.b) .multidot.(t.sub.a = 0) 
.multidot.(.DELTA.t =1) (5) 
and 
EQU K.sub.2 = c.sub.4 .multidot.(t.sub.a &gt; t.sub.b) .multidot.(t.sub.b =0) 
.multidot.(.DELTA.t = 1) (6) 
clearing signals K.sub.1 ' and K.sub.2 ' can be written as 
EQU k.sub.1 ' = c.sub.4 .multidot.(t.sub.b &gt; t.sub.a) .multidot. (.DELTA.t &gt; 4) 
(7) 
and 
EQU K.sub.2 ' = c.sub.4 .multidot. (t.sub.b &lt; t.sub.a) .multidot. (.DELTA.t &gt; 
4) (8) 
Equations (5) and (6) indicate that the register involved in the downshift 
is the one which carries the quantum bits of the smaller of the two codes 
A and B, i.e. register H.sub.a in the case of t.sub.a &lt; t.sub.b and 
H.sub.b in the case of t.sub.b &lt; t.sub.a. These equations also show that 
no shift occurs, if the smaller code is of rank 0 and the difference 
.DELTA.t between the two ranks is 1, i.e. if the larger code is of rank 1. 
Since the extent of the downshift is determined by the numerical differnce 
.DELTA.t, as will be more fully described hereinafter, a shift of the four 
quantum bits by more than three bit positions would completely empty the 
register stages assigned to these quantum bits. It is for this reason that 
clearing signals K.sub.1 ' and K.sub.2 ' will generated under the 
conditions indicated by equations (7) and (8), i.e. with the numerical 
difference .DELTA.t exceeding the value 4. 
Unit US, shown in FIG. 6, comprises two multiplexers MX.sub.7 and MX.sub.8 
which are analogous to multiplexers MX.sub.5 and MX.sub.6 of unit UT and 
are also controlled by the switching signal f.sub.c. These multiplexers 
receive the quantum bits h.sub.a and h.sub.b from registers H.sub.a and 
H.sub.b (FIG. 4) and deliver them in parallel to respective inputs x.sub.2 
' and x.sub.2 ' of an arithmetic unit AU'. Again, the bits of the larger 
code (as determined by signal f.sub.c) are invariably applied to input 
x.sub.1 ' whereas those of the smaller code go to input x.sub.2 '. Unit 
AU' performs either an addition or a subtraction, depending on the 
presence or absence of the polarity-discriminating signal i.sub.s issuing 
from XOR gate EO. Gate EO has an output i.sub.s = 1 only if bits s.sub.a 
and s.sub.b have different values, indicating opposite polarities of the 
voice samples represented by codes A and B. Bits s.sub.a and s.sub.b are 
available at the first stage outputs of registers T.sub.a and T.sub.b of 
preprocessor UP (FIG. 4). In the case of such diversity the quantum bits 
h.sub.a and h.sub.b must be summed differentially, rather than additively 
as when the two samples are of like polarity. Unit AU' works through an OR 
gate O.sub.2 into a shift register RU with a storage capacity of four 
bits. Under certain conditions giving rise to a signal a.sub.9 in the 
output of logic network LR (FIG. 8), more fully described hereinafter, 
register RU can be loaded with an all-1 bit combination from a store ST 
via OR gate O.sub.2. The bits stored in register RU can be shifted either 
to the left (up) or to the right (down) under the control of respective 
signals a.sub.7 and c.sub.13. An upshift can be inhibited by a signal 
a.sub.5 and the entire register can be reset to zero by a clearing signal 
a.sub.2. Signals a.sub.2, a.sub.5 and a.sub.7 are generated by the logic 
network LR of FIG. 8 under conditions to be described. A carry signal 
f.sub.0, originating at a read-only memory RZ of unit UO (FIG. 8), can be 
used to insert a bit into the first stage (at extreme left) of register RU 
vacated by a downshift. The register has four stage outputs carrying the 
quantun bits Q.sub.5, Q.sub.6, Q.sub.7 and Q.sub.8 of the composite code 
corresponding to the bits designated X, Y, Z and W of the above-identified 
CANDIANI patents. 
Register RC of output unit UU, illustrated in FIG. 7, has its last four 
stage inputs connected to the stage outputs of register RU to receive the 
bits Q.sub.5 -Q.sub.8 therefrom, together with the bits Q.sub.2 -Q.sub.4 
from the counter CS of unit UT (FIG. 5). A multiplexer MX.sub.9 controlled 
by a switching signal f.sub.c delivers either the polarity bit s.sub.a or 
the polarity bit s.sub.b to the first stage of register RC to form the 
corresponding bit Q.sub.s of the outgoing composite code, depending on 
whether code A or code B has the larger absolute value. 
As shown in FIG. 8, the operational unit UO includes a logic section UL in 
addition to a program counter CP in memory RP. Logic section UL comprises 
the aforementioned network LR and memory RZ along with two multiplexers 
MX.sub.10 and MX.sub.11 feeding the bits f.sub.a and f.sub.b from the 
unshiftable sections of registers H.sub.a and H.sub.b to respective inputs 
of memory RZ under the control of switching signal f.sub.c. Thus, the 
presence of a signal a* in the output of multiplexer MX.sub.10 indicates 
that the larger of the two codes A and B has a rank greater than zero; 
similarly, the signal b* is present in the output of multiplexer MX.sub.11 
if the smaller code is also at least of rank 1. Signal a*, whose absence 
represents the condition t.sub.a = t.sub.b = 0, is also fed to the logic 
network LR along with timing signals c.sub.4 and c.sub.8 -c.sub.11 from 
memory RP, output signals i.sub.0, i.sub.1 and i.sub.7 of counter CS (FIG. 
5), signal .DELTA.t from arithmetic unit AU and signals t, h, from 
comparators ID.sub.3, ID.sub.4 of FIG. 4. Network LR generates the various 
command signals a.sub.1 -a.sub.9 partly referred to above. Program counter 
CP has an operating cycle of 16 phases representing as many cycles of the 
basic clock signal CK.sub.4. In phase .phi..sub.0 its program is arrested 
and the contents of register RC (FIG. 7) are read out. The program is 
started by the pulse SP (see FIG. 3) and can be foreshortened by the 
de-energization of a reset input normally receiving voltage from an AND 
gate N.sub.7 with inputs receiving signals a.sub.2, c.sub.10 and a.sub.4. 
A "hold" input arrests the program in the absence of a signal a.sub.3. Two 
other inputs, normally receiving signals a.sub.1 and a.sub.6, cause a jump 
of the program to phase .phi..sub.11 or .phi..sub.15 upon the 
disappearance of these signals in phases .phi..sub.9 and .phi..sub.11, 
respectively. 
The sequence in which the output signals c.sub.1 -c.sub.13 are generated by 
memory RP, in the various phases of program counter CP, has been indicated 
in the flow chart of FIG. 9. 
In the first four phases, .phi..sub.1 -.phi..sub.4, signal c.sub.1 is 
present and causes the loading of registers T.sub.a and T.sub.b with 
polarity bits s.sub.a and s.sub.b and range bits t.sub.a, t.sub.b, 
respectively. In the next four phases .phi..sub.5 -.phi..sub.8, signals 
c.sub.2 and c.sub.3 enter the quantum bits h.sub.a and h.sub.b in the 
registers H.sub.a, H.sub.b. In phase .phi..sub.9 the multiplexers MX.sub.3 
and MX.sub.4 are switched by the disappearance of signal c.sub.2 ; with 
signal c.sub.5 generated and with registers H.sub.a and H.sub.b still 
enabled by signal c.sub.3, these multiplexers write the bits f.sub.a and 
f.sub.b in the first stages of these registers, displacing the quantum 
signals already there by one bit position. Signal c.sub.9 is also 
generated at this point. 
With the appearance of signal c.sub.9, logic LR explores the possibility 
that the two codes to be combined are of equal rank. If this happens to be 
the case, the command a.sub.1 is generated according to the formula 
EQU a.sub.1 = c.sub.9 .multidot. (t.sub.a = t.sub.b) (9) 
Signal a.sub.1 causes a jump to state .phi..sub.11 unless overridden by a 
signal a.sub.2 according to the formula 
EQU a.sub.2 = c.sub.9 .multidot. (t.sub.a = t.sub.b) .multidot. (h.sub.a = 
h.sub.f) .multidot. i.sub.s (10) 
indicating that the two samples are of the same amplitude but opposite 
sign. The occurrence of signal a.sub.2 resets the program counter CP to 
its state .phi..sub.0 whereby register RC of input unit UU (FIG. 7) is 
unloaded with an all-0 code since the same signal a.sub.2 resets the 
register RU of FIG. 6 (state .phi..sub.9 ' in FIG. 10) and since the 
counter CS is empty at this instant as will presently become apparent. 
If t.sub.a .noteq. t.sub.b, signal c.sub.7 generated in phase .phi..sub.10 
causes the unit CS to be loaded with the difference .DELTA.t computed in 
the interim by the arithmetic unit AU. If .DELTA.t &gt; 4, clearing signal 
K.sub.1 ' or K.sub.2 ' is generated according to equation (7) or (8) to 
empty the register H.sub.a or H.sub.b of quantum bits as already described 
(state .phi..sub.10 ' ). 
If the value of .DELTA.t is &gt; 1 but does not exceed 4, signal a.sub.3 
disappears according to the formula 
EQU a.sub.3 = i.sub.1 .multidot. (.DELTA.t &lt; 4) .multidot. c.sub.4 (11) 
under the control of signal c.sub.4 generated in this phase. Program 
counter CP is thus put on "hold" for as many clock cycles as is necessary 
to reduce the count of component CS to 1. At the same time the quantum 
bits in register H.sub.a or H.sub.b (whichever happens to carry part of 
the larger code) are downshifted by as many positions by signal K.sub.1 or 
K.sub.2 until the program is restarted by the appearance of signal a.sub.3 
with i.sub.1 = 1. At this instant the logic network RL receives from 
counter CS an output signal equivalent to .DELTA.t = 1 so that signal 
K.sub.1 or K.sub.2 terminates if the smaller code happens to be of rank 0, 
i.e. if t.sub.b = 0 or t.sub.a = 0 as the case may be. In that instance 
the downshifting of register H.sub.a or H.sub.b stops but the counter CS 
takes one further step to 0. If, however, the smaller code has a rank 
higher than 0, the downshift goes on until the disappearance of signal 
c.sub.4 which may occur in the 11th, 12th, 13th or 14th phase according to 
the number of clock signals required to step down the counter CS. The 
program counter CP then reaches the state .phi..sub.11 which therefore 
does not necessarily coincide with the 11th phase. 
In state .phi..sub.11 the signals c.sub.6 and c.sub.8 come into existence 
while signal c.sub.7 recurs. Signal c.sub.6 blocks the input x.sub.2 of 
arithmetic unit AU so that only the range bits of the larger codes are 
received by unit AU at its input x.sub.1 and are passed through to 
encounter CS. The following alternatives will now have to be considered: 
Polarity-discriminating signal i.sub.s may be either 0 or 1. In the first 
instance, the addition of the quantum bits present on inputs x.sub.1 ', 
and x.sub.2 ' of arithmetic unit AU' (FIG. 6) may or may not give rise to 
a positive carry. In the second instance, since the numerical value of the 
quantum bits of the larger code may be less than that of the quantum bit 
of the smaller code, the subtraction performed in the unit AU' may result 
in a negative carry. The occurrence of either type of carry is marked by 
an output signal r of unit AU' delivered together with signal i.sub.s to 
memory RZ of operating unit UO. The carry signal f.sub.0 is given by: 
EQU f.sub.0 = i.sub.s .multidot. r .multidot. (a* + i .multidot. b*) + i.sub.s 
.multidot. r (12) 
Thus, in the case of an adding operation (i.sub.s = 0) the presence of a 
signal r will produce the signal f.sub.0 only if at least one of the two 
codes has a rank higher than 1. In the case of subtraction, signal f.sub.0 
will be generated as long as signal r is absent. 
With the occurrence of signal c.sub.8 in state .phi..sub.11 the signal 
a.sub.4 will disappear if no carry is present and if at least one of the 
codes has the rank 0, according to the formula: 
EQU a.sub.4 = c.sub.8 .multidot. (i.sub.s .multidot. r .multidot. b* + 
i.sub.s .multidot. f.sub.0 + i.sub.s .multidot. a* + i.sub.s .multidot. r 
.multidot. i.sub.7 + i.sub.s .multidot. i.sub.7 .multidot. b*) (13) 
This immediately resets the program counter PC and fills the register RC 
with the bits held in counter CS and register RU. 
If, in the additive case, a carry is present and/or the smaller code is of 
a rank greater than 0, signal a.sub.9 comes into being according to the 
formula 
EQU a.sub.9 = i.sub.s .multidot. i.sub.7 .multidot. (r + b*) (14) 
This loads the register RU with a bit combination 1 - 1 - 1 - 1 so that an 
all-1 code is delivered to register RC. 
If the aforedescribed conditions are not met, program counter CP continues 
to its next state .phi..sub.12 in which signals c.sub.10 and c.sub.13 are 
generated. Signal c.sub.13 now increases the count of component CS by 1 
and simultaneously downshifts the contents of register RU by one bit 
position unless such shift is inhibited by a signal a.sub.5 according to 
the formula : 
EQU a.sub.5 = i.sub.0 .multidot. c.sub.10 (15) 
indicating that the larger code is of rank 0. Signal c.sub.10 then steps 
the counter CP to its initial state .phi..sub.0 while a bit corresponding 
to signal f.sub.0 is introduced into the stage of register RU vacated by 
the 1-position downshift caused by signal c.sub.13. 
If the two voice samples are of opposite polarities, signal a.sub.6 
disappears in state .phi..sub.11 according to the formula: 
EQU a.sub.6 = i.sub.s .multidot. c.sub.8 (16) 
and causes a jump to state .phi..sub.15 with generation of signal c.sub.11, 
producing in turn the signal a.sub.8 given by 
EQU a.sub.8 = i.sub.s .multidot. c.sub.11 (17) 
Signal a.sub.8 diminishes the count of component CS by 1 and is accompanied 
by a 1-position upshift of the contents of register RU by 1-bit position 
under the control of signal a.sub.7 as long as counter CS has an output 
other than i.sub.7, according to the formula: 
EQU a.sub.7 = i.sub.1 .multidot. c.sub.11 (18) 
From state .phi..sub.15 the program counter reaches a final state 
.phi..sub.0 to stop the program. 
Since equation (13) includes the terms of equation (14), a resetting of the 
program counter occurs also under the conditions in which an all-1 code is 
entered in register RC. Counter CS is cleared during each such resetting. 
EXAMPLES 
______________________________________ 
Numerical 
Code Value 
______________________________________ 
I 000 - 1100 .DELTA.t 
= 0 12 
+II 000 - 1000 r = 1 8 
I+II 001 - 0100 f.sub.0 
= 0 20 
I 001 - 1100 .DELTA.t 
= 1 28 
+II 000 - 1000 r = 1 8 
0100 f.sub.0 
= 0 
DOWNSHIFT 0010 
I+II 010 - 0010 36 
I 010 - 1000 .DELTA.t 
= 2 48 
+II 000 - 0100 r = 0 4 
0100 f.sub.0 
= 0 
DOWNSHIFT 0010 
I+II 010 - 1010 52 
I 010 - 1110 .DELTA.t 
= 0 60 
+II 101 - 1100 r = 1 56 
1010 f.sub.0 
= 1 
DOWNSHIFT 0101 
I+II 011 - 1101 116 
I 010 - 0001 .DELTA.t 
= 2 34 
-II 000 - 0100 r = 1 -4 
DOWNSHIFT 0010 f.sub.0 
= 0 
1111 
UPSHIFT 1110 
I -II 001 - 1110 30 
______________________________________ 
In FIG. 9 we have shown a modification of exchange TR to handle a 
conference call among four subscribers sending out voice codes A, B, C and 
D in respective time slots 101-104 and receiving compound codes B+C+D, 
A+C+D, A+B+D and A+B+C in respective time slots 201-204. Within exchange 
TR the codes are transmitted from network RT to conference unit CF in six 
time slots 301-306 and, after compounding, returned to the network in six 
time slots 401-406. The codes A and B alternate in time slot 306 even as 
codes C and D alternate in time slot 303. Thus, these codes may be 
considered as grouped in two conference combinations cf.sub.1 and 
cf.sub.2. The compound codes A+B and C+D, occurring in time slots 403 and 
406, are not utilized by the switching network RT.