Manufacturing integrated circuits and testing on-die power supplies using distributed programmable digital current sinks

A method for designing and testing on-die power supply, power distribution, and noise suppression techniques for integrated circuits such as microprocessors is described. A network of time varying loads is distributed along the power supply grid to facilitate testing of new power supplies and grids and noise suppression techniques before design of the chip is completed. Several programmable current sinks are described for presenting loads according to a preferred test-waveform current. Transient, including droop detection, and static testing is easily performed using the described methods and circuitry.

TECHNICAL FIELD

This invention relates to integrated circuits and to methods for manufacturing and testing integrated circuits, and more particularly to power distribution on integrated circuits.

BACKGROUND

The trend in the electronics industry is to achieve ever faster switching speeds and increased circuit densities at the component and system levels. Another trend has been to reduce operating voltages and power consumption. These trends are placing more stringent demands on the on-die power distribution systems of integrated circuits, such as microprocessors. For example, higher switching speeds and clock frequencies lead to increased current demands and to higher inductive noise (L di/dt) on the power grid. Power saving modes of operation lead to large and rapid swings in current demand from the power distribution system. The lowering of operating voltages concomitantly narrows the voltage regulation window of the on-die supply voltage level (for example maintaining the supply voltage within 10% peak-to-peak). Increased power noise (from switching currents and power saving modes) and narrowing of the voltage regulation window (from reduced operating voltages) have pushed designers to explore on-die voltage regulation and power distribution techniques to achieve successful chip level and system level designs.

SUMMARY

DETAILED DESCRIPTION

The present invention provides techniques for accurately testing on-die voltage regulation, power distribution, and noise reduction techniques allowing designers to evaluate new design techniques prior to production of the completed integrated circuit. Design techniques for accurate repeatable modeling of the di/dt power noise are provided to perform on-die testing of proposed designs. Time varying loads may be provided to mimic the expected changing current demands and may be distributed along the on-die power distribution grid. The loads may be used to design and evaluate power distribution systems, to accurately model load requirements, and predictably test power noise suppression techniques before time consuming and costly incorporation into an integrated circuit. Programmable current sinks may be used on the die for controlled repeatable testing. Illustrative examples using a microprocessor are discussed below with reference toFIG. 1.

The power supply current drawn by a microprocessor often changes dramatically depending upon its state. Many modern microprocessors have at least one power-saving state in which portions of the architecture are deactivated thereby conserving power. The stop-clock state is one example of a power saving state.FIG. 1shows the supply current, Icc, (as a fraction of the maximum supply current, Icc max) drawn by a microprocessor in the stop-clock and active states. From time t0to time t1, the microprocessor is in the stop-clock power saving mode. At time t1, the microprocessor begins the transition from the stop-clock state into the active state. As various portions of the microprocessor circuitry are activated, the supply current, Icc, increases until reaching the full on state at time t3. At time t4, the microprocessor begins the transition back into the power saving stop-clock state. As portions of the microprocessor circuitry are deactivated during this transition, the supply current, Icc, decreases until reaching the stop-clock state at time t7. The supply current may drop to about 25 percent of maximum as shown inFIG. 1due to leakage current and because not all sections of the microprocessor may be deactivated in the stop clock state. Some portions of the microprocessor may take longer than others to make the transition to the active state or to the stop-clock state, which is accounted for in the stepped slope of the current waveform inFIG. 1.FIG. 1is an example of the severe on-die transient power demands in a microprocessor.

For the microprocessor example, time varying loads may be used to mimic the transient power demands (such as those illustrated inFIG. 1) to test proposed power distribution grids for example, Vcc grids, ground grids, noise suppression techniques, and voltage regulation circuitry and techniques. Referring toFIG. 15, a network of time-varying loads501A–501N may be distributed along a power supply grid515for testing. The number of time varying loads, N, may be small or large depending upon the application. More accurate modeling and testing of the on-die power-distribution grid may be achieved by distributing the time-varying loads501along the grid515according to planned or extant circuit requirements. The aggregation of the distributed loads may be chosen to model the aggregate current demands of the circuit. For a microprocessor example, the current characteristics illustrated inFIG. 2may be chosen as a test-current waveform for the time varying loads501inFIG. 15. Although the current characteristics ofFIG. 2will be discussed as an example of a test-current waveform, other current characteristics, such as exponential waveforms, may be used.

As illustrated inFIG. 2, the test-current waveform includes a dual sloped leading edge, an on period, and a dual sloped trailing edge. The current rises with a slope of M1from zero at time t0to I1at time t1and then rises with a slope of M2from time t1to t2reaching a final value of I2. The rise time of the waveform, Trise, may be defined as the period from time t0and to t2inFIG. 2. Similarly, the current declines from I2to I3with a slope of M3from time t3to t4and then continues to decline from I3to zero with a slope of M4from time t4to t5. The on period extends from time t2to t3. Two types, “staggered” and “pulsed,” of programmable current sinks will be described which may be used for the time varying loads501inFIG. 15. Each current sink501may be programmed to mimic the test-current waveform ofFIG. 2or other waveforms as desired.

The “staggered” approach may generate the test-current waveform by summing two or more time-staggered currents. Referring toFIG. 5, six current sources, Is1–Is6, each having its own current value may be connected through switches, SW1–SW6, to create a time-varying load for connection to a power supply under test. Assume that each current source may be programmed to sink a specific value of current and that each switch may be programmed connect and disconnect the current sink at specific times. The load presented to the power supply under test will vary depending upon the number of the current sinks connected and their respective values.

Referring toFIG. 3, six time-staggered vertically stacked rectangular areas representing the current presented by each current sink element, Is1–Is6, to the power supply under test are shown. The load current for the circuit ofFIG. 5(which is the sum of the currents presented by each sink element) is shown in bold with the leading edge, peak, and trailing edge labeled inFIG. 3. Assume that switches SW1–SW6are open and the load current is zero just prior to time t0. At time t0, switch SW1may be closed raising the load current by Is1. At time t1, switch SW2may be closed raising the load current by Is2. Switches SW3, SW4, SW5, and SW6may be closed in succession respectively at times t2, t3, t4, and t5to incrementally raise the load current as shown by the leading edge of the load current inFIG. 3. After time t5, all switches SW1–SW6may be closed to produce the peak load current. At time t6, switch SW1may be opened disconnecting sink element Is1and reducing the load current by Is1. At time t7, switch SW2may be opened disconnecting sink element Is2and reducing the load current by Is2. Switches SW3, SW4, SW5, and SW6may be opened in succession respectively at times t8, t9, t10, and t11to incrementally lower the load current as shown by the trailing edge of the load current inFIG. 3. The magnitudes and the timing of the currents may be scaled to provide the desired rise and fall transition characteristics. For example, inFIG. 3currents, Is1–Is3and Is4–Is6may be scaled in magnitude and timing to produce the slopes M1and M2. For reasons of economy (as will be apparent from the discussion that follows) each switch SW1–SW6may be held closed for the same fixed period of time (i.e., periods t0–t6, t1–t7, t2–t8, t3–t9, t4–t10, and t5–t11inFIG. 3may be equal). Therefore, the trailing edge may be an inversion of the leading edge (i.e., slope M1=−M3and slope M2=−M4).

As can be seen fromFIG. 3, the load current produced by the staggered sink elements may closely approximate the test current waveform ofFIG. 2shown as a dashed line inFIG. 3. As discussed below, the sink elements may be turned on and off gradually to produce a smooth ramp more closely approximating the dashed line. Although six current sink elements are shown inFIGS. 3 and 5, any number may be used for the programmable current sink to increase (or decrease) the resolution of the test-current waveform. The duration of the peak, Ton, may be increased or decreased by varying the total on time of the switches. Although variations in turn on times (e.g., to–t1≠t4–t5) are shown inFIG. 3, using a constant delay between each turn on time can help reduce circuit requirements. Conversely providing a programmable on time for each switch can increase the versatility of the current sink (to produce more complex test-current waveforms such as asymmetrical leading and trailing edges) at the expense of circuit size and complexity.

The “pulsed” approach may generate the test-current waveform using a series of current pulses without overlapping. The pulsed approach may be used to produce test-current waveforms having asymmetric leading and trailing edges. All pulses may have the same duration and be programmed in amplitude to provide any desired test current waveform as shown by the example inFIG. 4. A variation discussed below in connection withFIG. 11may provide a variable duration pulse for Ton. Referring again toFIG. 5, assume that current sources Is1–Is6sink currents I1–I6, that each switch SW1–SW6is programmed to remain on for a fixed time, and that the switches are turned on and then off in order: switch SW1turns on at time t0and off at time t1, switch SW2turns on at time t1and off at time t2, switch SW3turns on at time t2and off at time t3, switch SW4turns on at time t3and off at time t4, switch SW5turns on at time t4and off at time t5, and switch SW6turns on at time t5and off at time t6. Assume also that there is no dead zone between, and there is no overlap of, the current pulses. Referring toFIG. 4, operating the switches and current sinks ofFIG. 5as described results in the first six pulses in the series labeled P1–P6having current values of I1–I6and producing the portion of the test-current waveform from to–t6. It should be apparent that the leading edge, peak, and falling edge characteristics of the test-current waveform may be determined by the amplitude and timing of current pulses. Similarly, the resolution of the test-current waveform may be determined by the number of current sinks and the sampling rate, i.e., the speed of operating the switches in the example ofFIG. 5.

A schematic diagram of a scaleable N-bit current sink element100for use in a programmable current sink is shown inFIG. 6. The number of bits, N, is unrelated to the number of time varying loads, N, discussed above in connection withFIG. 15. The current sink element100includes nMOS transistors104A,104B, . . .104N scaled geometrically in powers of 2 to sink a current I, 2I, . . . 2(N−1)I, respectively (e.g., 10, 20, and 40 micro amps for a 3 bit element). The sink element100may be programmed to sink any integer multiple of current I up to the maximum of (2N−1)I. The drain of each transistor may be connected to the output115at which point the transistor sink currents are summed. The gate of each transistor,104A–104N, may be driven by a respective NAND gate,102A–102N, followed by an inverter driver,103A–103N. The NAND gates,102A–102N, each may have one input driven by a common enable control line110and a second input driven by the output, Q, of a respective flip flop,101A–101N. The enable line110may be used to turn the transistors off regardless of the state of the flip-flops to disable the output115. Flip flops101A–101N may be connected serially forming a shift register having a data input line111, a data output line112, and a clock input line113. The flip-flops101, NAND gates102, and inverters103, may be powered by an auxiliary power supply114to avoid introducing any unwanted noise or fluctuations in the test-current. All or some of the support circuitry may be powered by the auxiliary power supply114.

In operation, the sink current for the sink element may be programmed by serially shifting a scan data chain into the flip-flops using the clock113and the data111inputs. A “1” may be loaded into a flip-flop to turn on its respective transistor. Assume, for example, that the sink element ofFIG. 6has only 3 bits, that transistors104A–104N have been respectively sized to sink 10, 20 and 40 micro amps when turned on, and that a 50 micro amp current is required. The current sink element100may be programmed to sink 50 micro amps by setting flip flops101A and101N and clearing flip flop101B thereby turning on transistors104A and104N when the enable signal is provided. Although three-bits are shown, the sink element may have as many (or few) bits (transistors with respective flip flops, NAND gates, and drivers) as required to satisfy the current resolution and range requirements of the programmable current sink. A four-bit current sink element100(with four transistors, flip flops, NAND gates, and drivers) may provide a good range of sink current without undue circuit complexity. The inverter drivers103may be scaled according to the characteristics of their respective transistors104to provide an on-off/off-on transition time suitable to the application.

A first embodiment of a programmable N-stage staggered current sink200is schematically shown inFIG. 7. The number of stages, N, of the current sink200is unrelated to the number of bits, N, in each sink element and the number of time varying loads, N. Each stage (A, B, . . . N) may comprise a current sink element100, a delay element201, and a switch202. The outputs115A,115B,115N of the sink elements100may be connected to the current sink output215(actually the element outputs115and the sink output215sink current and may be connected directly to the power supply grid being tested) where they may be summed to create a test-current waveform having the desired leading edge, peak, and trailing edge characteristics as described above in connection withFIG. 3. All or some of the support circuitry may be powered by an auxiliary power supply separate from the supply under test. Although three stages are shown inFIG. 7and the programmable current sink200may be scaled to include any desired number of stages, N, nine stages may be sufficient.

Each current sink element,100, may be of the type shown inFIG. 6having a data input111, a data output,112, and a clock input (113inFIG. 6) for receiving a scan data chain for setting its sink current level. As shown inFIG. 7, the data inputs111and outputs112of the sink elements100may be daisy-chained to form a shift register allowing all of the elements100in the programmable sink200to be programmed via a single data line211using concatenated scan data chains. Similarly, all (or groups) of the programmable current sinks200throughout the test chip may have the data inputs and outputs daisy chained to allow programming of all (or groups) of the current sinks200via one (or more) serial scan data lines.

The delay elements201(each of which may comprise two 20 pico-second-propagation-delay inverters to create a 40 pico-second delay) are connected to form a delay line. The delay select switches202, which may be 1-to-2 demultiplexers, may route the output of each delay element to the next delay element or to OR gate203. The delay select switches202may be controlled by respective flip flops (not shown) which may be programmed by another (or the same) scan data chain similar to the arrangement for programming the current level of the current sink elements100. Only one of switches202A to202N should be switched to position “0” during operation. When the switch is in the “0” position, the input of the subsequent delay element may be grounded to ensure that the subsequent delay and current sink elements remain off. The output of OR gate203may be fed back through inverter204to the input of the first delay element201A in, and the input of, the delay line, providing feedback for oscillation of the delay line. The state of the delay select switches may therefore determine how many of the N stages of the sink will be utilized and the period of the oscillator. The enable input,110A,110B, . . .110N, of each sink element100A,100B, . . .100N, may be connected to the output of its respective delay element,201A,201B, . . .201N. As a pulse propagates through the delay line, the sink elements100may be turned on in succession and then off in succession.

For example, assume an initial state, T0, in which the outputs and inputs of all delay elements are low and assume that delay select switches,202A,202B and202N, are set to the1,1, and0positions, respectively. All of the sink elements100will be off since the enable lines110A–N will also be low and the output of the OR gate203presented to the input of the inverter204will be low. After a small delay determined by the inverter propagation time, the inverter, output will go high. After a first delay (determined by the first delay element201A), the output of the first delay element201A will go high turning on sink element100A. After a second delay (determined by the second delay element201B), the output of the second delay element201B will go high turning on sink element100B. The succession will continue until the output of delay element201N goes high turning on current element100N and presenting a high input to OR gate203. The output of inverter204will then go low after the propagation delay of OR gate203and inverter204and a low state will propagate through the delay elements201turning the current elements100off in succession. When the last delay element201N goes low the entire cycle will repeat.

It should be clear from the description of current sink200that (1) the rise time, Trise, and fall time, Tfall, of the test waveform will be equal, (2) the rise and fall times, Trise, and Tfall, may be controlled using the delay select switches202(3) the on time and off time of the test waveform will be equal and may be determined by the propagation delay of the OR gate203and inverter204, (4) the oscillator period is equal to the sum of the rise time and the fall plus time twice the on time of the test current waveform (Tosc=2Ton+Trise+Tfall), (5) the leading and trailing edge characteristics may be determined by the sink elements100as discussed above in connection withFIG. 3, and (6) the oscillator may run continuously provided that at least one of the delay select switches is set to provide feedback. The oscillator waveform on the output of the inverter204may be used as a reference signal for making test measurements or for synchronizing other current sinks. Current sink200may therefore supply a controllable periodic load current with a synchronization signal for transient testing, such as droop detection.

Variations of the current sink200may include one or more of the following features. The delay select switches202may be moved to the inputs of OR gate203leaving direct connections between delay elements201. An input for selecting an external clock signal may be provided to synchronize the current sink200with test equipment or other current sinks. The sink elements100may have their inverter drivers (103FIG. 6) scaled to provide on-off/off-on transitions having the same duration as the propagation delay of delay elements201making the test current waveform into a smooth ramp as compared to discontinuous steps.

In operation, the scan data chain for setting the current level of each sink element100and the scan data chain for setting the state of the delay select switches202may be loaded first and then the power supply response may be observed.

Referring toFIG. 8, a programmable N-stage staggered current sink250with variable on and off time is shown. The sink250is similar to sink200ofFIG. 7, however that the delay select switches202and the OR gate203have been removed and a variable delay251has been added. The removal of the delay select switches202and OR gate203may restrict the ability to program the rise and fall times of the test-current waveform. However, the addition of the variable delay251allows for programming the on and off times. The on and off times of the test-current waveform produced by the current sink250will be equal to the sum of the delays from variable delay251and inverter204. All of the stages of sink250may be enabled in succession, however, one or more sink elements100may be programmed for zero current potentially extending the on and off times. The variable delay251may be implemented using a programmable delay line and may be controlled by a set of respective flip flops (not shown) which may be programmed by another (or the same) scan data chain similar to the arrangement for programming the current level of the current sink element100described in connection withFIG. 6. In operation, the scan data chain for setting the current level of each sink element100and the scan data chain for setting the variable delay may be loaded first and then the power supply response may be observed.

Referring toFIG. 10, a programmable N-stage time-staggered current sink260with a disable switch is shown. The sink260is similar to the sink250inFIG. 8, however, switch261has been added between the inverter204and the delay element201A. The disable switch261, when open, disables the oscillator, causes all delay elements to return low, and disables all current elements100. The disable switch261may be used to avoid overloads or unnecessary power dissipation, for example during the scan data loading operation.

One implementation of switch261is shown inFIG. 12. The switch261has a control line404, a data input405, and a data output406. Two complementary, pMOS and nMOS, transistors,402and403, are connected in parallel to form the data path between input405and output406. A transistor407may be connected between the output406and ground to force the output406low when the switch261is disabled. Inverter401provides a complement of the control signal for driving the gates of transistors402and407. When the control input404is high, transistors402and403are on and transistor407is off allowing data to pass from the input to the output. When the control input is low, transistors402and403are off blocking transmission of data from the input to the output, and transistor407is on pulling the output low. Switch261and a complement of switch261may be combined to form a 1-to-2 demultiplexer implementing the delay select switches202of FIG.7. A flip-flop (not shown) may provide memory for the control input404and may be programmed using a scanned data chain as described above.

Referring toFIG. 13, another N-stage programmable time-staggered current sink270is shown. Current sink270is similar to current sink200shown inFIG. 7, however, a programmable delay251(FIG. 8) and a disable switch261(FIG. 10) have been added. Current sink270provides greater flexibility in creating test current waveforms. For example, the rise and fall times may be programmed using the delay select switches202, the leading and trailing edges may be programmed using the sink elements100, the on and off times may be programmed using the variable delay251, and the sink may be disabled using switch261.

Referring toFIG. 14, another N-stage programmable time-staggered current sink280is shown. The current sink ofFIG. 14is similar to the current sink270ofFIG. 13, however, the delay select switches202and OR gate203have been replaced with a multiplexer271and the variable delay251has been moved. The multiplexer271may include inputs272A–272N for connection to a respective delay element201A–201N, input272ND connected to the output of the variable delay251, input275for connection to an external clock, selector control lines274, and an output273. The multiplexer selection lines274may be used to program the rise and fall time of the test-current waveform by selecting inputs272A–N in the same way that the rise and fall times were set using the delay select switches202in current sink200discussed above in connection withFIG. 7. The multiplexer271may be programmed to select input272ND to enable the on and off time set by the variable delay251. Finally, an external clock (e.g., from test equipment or from another current sink200) may be provided on input275and selected using the selection lines274. Alternatively, the sink280may be modified to provide a variable delay element between the multiplexer271and the inverter204to provide on and off time programmability in combination with rise and fall time combination if desired. The multiplexer271may be implemented using switches261(FIG. 12) omitting the output-clamping transistor407and may be controlled by respective flip flops (not shown) which may be programmed by another scan data chain similar to the arrangement for programming the current level of the current sink element100described in connection withFIG. 6. In operation, the scan data chain for setting the current level of each sink element100, the scan data chain for setting the variable delay, and the scan data chain for setting the multiplexer selection may be loaded first and then the power supply response may be observed.

Referring toFIG. 9, a programmable N-stage pulsed current sink300is shown schematically. The sink elements100may be implemented as discussed above in connection withFIG. 6. A pulse generator302produces pulses having a duration set to determine the desired current pulse duration (e.g., the period t0–t1inFIG. 4) and a period set to determine the frequency (repetition rate) of the test-current waveform. The pulse generator may feed a delay line having a series of delay elements301A–301N. All of the delay elements301may have a delay period set equal to the pulse width. The delay period and pulse width may need to be lengthened in the programmable pulsed current sinks300and350by comparison with the programmable staggered current sinks200,250,260,270, and280to maintain a smooth test current waveform. The output of each delay element301may be fed to the enable input110of a respective sink element100. The sink elements100may be cascaded as described above to allow for serial loading of the scan data. Also, all or some of the support circuitry may be powered by an auxiliary power supply separate from the power supply or power grid under test.

Assume there are only three stages (A, B, and N), that all delay elements are cleared, and the output of the pulse generator302is low, thus all sink elements100are off. Referring toFIG. 16, the pulse generator produces a pulse beginning at time t-1and ending at time t0. After one delay period (preferably equal to the pulse width) at time t0, the output of delay element301A goes high turning on sink element110A. After a second delay period at time t1, the output of delay line301A returns low turning off element100A. At the same time t1, the output of delay element301B will go high turning on sink element100B. After another delay period at time t2, the output of delay element301B will return low turning off sink element100B and the output of delay element301N will go high turning on sink element100N, and so on. In this way a series of N current pulses (corresponding to the number of stages, N, in the current sink) may be generated to produce a test-current waveform as described in connection withFIG. 4above. In operation, the scan data chain for programming the current level of each sink element100may be loaded first and then the power supply performance may be observed.

The delay elements301may be matched with the pulse width of the pulse generator302by first determining the propagation delay of the delay elements and then designing the pulse generator to produce a matching pulse width and a period greater than the sum of the delay elements. Variations between the delay elements301may be reduced using device dimensions, channel widths or lengths, greater than the minimum allowed by the process. For example, a 0.1 micrometer process tolerance may represent a 10% variation in a 1 micrometer-width device, but only 5% variation in a 4 micrometer-width device. Reductions in variation also may be achieved by increasing the channel length of the devices. However, increased channel lengths may produce increased propagation delays. Using the same layout for all of the delay elements may also reduce variations.

Another embodiment of a programmable N-stage pulsed current sink350, which avoids the need to match the delay time of delay elements301to the width of the pulses produced by the pulse generator302, is shown schematically inFIG. 11. Each of the N stages may include a delay element301, an exclusive OR (“XOR”) gate303, and a sink element100. The delay elements301may be connected in series to form a delay line. In each stage, the XOR gate303inputs may be connected to the input and output of the respective delay element301with the XOR gate303output driving the enable input110of the sink element. Since the XOR gate303enables the sink element100only when the input and output of its respective delay element do not match, the propagation of the delay element301in each stage may be used to determine the duration of the current pulse produced by that stage. For simplicity, all of the stages may use delay elements301having the same propagation delay except for the middle stage N/2 that may use a variable delay element301(N/2) (similar to variable delay251inFIGS. 8,10,13, and14). The variable delay301(N/2) may be used to extend the on time of the test-current waveform without needlessly increasing the requisite number of stages for the current sink350. The output of the last delay element301N may be complemented by inverter304and switchably fed back to the input of the first delay element301A via disable switch361(similar to disable switch261inFIGS. 10,13,14) to create an oscillator (similar toFIGS. 10). Another variable delay351(shown in dashed lines) may optionally be added to provide a programmable off time for the test-current waveform.

Assuming that disable switch361is open and the inputs and outputs of all delay elements301A–N (and optional variable delay351) are low, all XOR gates303will disable the sink elements100and the output of inverter304will be high. When switch361is closed, the high signal at the input of delay element301A causes XOR gate303A to enable sink element100A until the high state propagates through delay element301A. As the first stage is being turned off, the second stage will turn on. The XOR gates may be matched to each other to provide smooth on and off of transitions of adjacent stages. The process continues turning each stage on and then off in succession. After the last stage turns off and after any delay introduced by inverter304and the optional variable delay element351, the process may begin again with switch361closed. It should be apparent that the leading edge, trailing edge, on-time, and off-time of the test-current waveform produced by sink350may be determined by the stages before N/2, stages after N/2, stage N/2, and delay element351, respectively. The disable switch361may be opened to disable the oscillator.

Referring back toFIG. 15, a plurality (having a number, N) of the programmable current sinks501, for example the staggered or pulsed type discussed above, may be distributed along the power supply grid for testing. A small number (perhaps 9 or fewer) of current sinks501may be used to test small integrated circuits and a larger number (perhaps 36 or more) may be used to test larger integrated circuits such as microprocessors. The sink outputs215may be connected to grid515. The current sinks501are shown with their respective scan data inputs211and outputs212cascaded so that a single serial data stream may be used to program the entire network of current sinks501. The clock output213A of sink501A is shown feeding the synchronization clock inputs275of the current sinks501via clock line513to synchronize the test-current waveforms. Alternatively, the current sinks501may be synchronized by cascading the clock outputs213and synchronization inputs275via connections514as shown in broken lines inFIG. 15. Some of the current sinks may be programmed to run independently of the external clock as discussed above in connection with the current sink280ofFIG. 14utilizing a multiplexer.

A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, an alternative embodiment of the pulsed current sinks300,350may include an input for selecting an external clock signal to synchronize the sink with an external clock, for example from another current sink. Yet another alternative embodiment of the pulsed current sinks300,350may have programmable delay elements for one or more of the stages. An alternative embodiment of the staggered current sink may allow each sink element to be programmed to switch on and off for programmable durations. It will be appreciated that the power distribution grid and test circuitry may be implemented in silicon or modeled in a computer simulation system for testing. Accordingly, other embodiments are within the scope of the following claims.