Method and arrangement for detecting and localizing errors or faults in a multi-plane unit incorporated in a digital time switch

A method and device for detecting errors in a digital time switch that does not require the signal to be synchronous throughout a multi-plane processing unit in a digital time switch. The present invention allows for the detection and localization of errors occurring in one section of one plane in a multi-plane unit. The invention is preferably included in a telecommunications system operating with pulse code modulation and time multiplex. In a multi-plane portion of a digital time switch, there is generated for each one of corresponding parallel planes at corresponding locations a compressed version of the data signal and the corresponding compressed data signals are compared. An alarm is given when the comparison shows a difference between the compressed signals.

TECHNICAL FIELD 
The present invention relates to a digital time switch, of the kind which 
is provided with equipment i.e., processors and related electronics, in 
several electrically identical parallel working planes. The digital time 
switch is included in a telecommunication system which operates with pulse 
code modulation and time multiplex. More specifically, the invention 
relates to a method and an arrangement for error/fault detection and 
error/fault localization in a multi-plane processing unit incorporated in 
a switch of the aforesaid kind. 
BACKGROUND ART 
In order to achieve a high degree of reliability in extensive 
telecommunication systems, it is normal for functional units in the system 
switch to utilize several, mutually-parallel planes, each containing 
mutually-identical equipment. As used throughout this application, the 
terms "mutually-identical" and "electrically identical" equipment mean 
electronic circuitry configures such that when an electrical signal is 
input to two or more pieces of such equipment, when functioning without 
error, the outputs from such equipment will be the same. The terms 
"equipment" and "processing means" include but are not limited to 
processors, memories and/or other electronic circuitry. The data-flow 
entering such a multi-plane unit is distributed to the parallel planes 
contained therein. The data-flow passes through the equipment in each of 
said planes and an output data signal is then delivered from respective 
planes. The occurrence of an error, or a fault, in any one of the planes 
can be discovered, by comparing the data signals delivered by the various 
planes, bit for bit, and a majority-selection of data-flow can be 
delivered from the unit by making a majority selection on the basis of 
said comparison. The comparison and the majority-selection are effected in 
a comparator/majority-selection device connected to the multi-plane unit. 
As before mentioned, the comparator/majority-selection device is operative 
to make a comparison between the data signals exiting from the planes, 
bit-for-bit in real time, and delivers an output signal which constitutes 
a majority decision. In order for this to be possible, the output data 
signals must be delivered from the parallel planes synchronously, i.e. the 
delays through the three planes must be of mutually equal value, since 
otherwise the comparator/majority-selection device will produce an 
erroneous signal. 
Swedish Patent Application SE 8705065-4 describes a time switch which is 
based on three synchronously operating planes and which operates with 
bit-for-bit comparison and majority-selection between corresponding 
information deriving from the three planes. The comparison and 
majority-selection are utilized to correct errors/faults in information 
occurring in any one plane in the switch. Each plane includes switch 
storage devices SSA, SSB, SSC, control storage devices CSA, CSB, CSC, 
re-write devices RWA, RWB, RWC and information selecting devices MD1A . . 
. MD4C. Each information selector device is operative to make a comparison 
between the information from the three planes and to make a 
majority-selection on the basis of this comparison, therewith correcting 
any error/fault that may occur in any one of the three planes. 
Japanese Patent Specification JP 60-10996 describes a time selector which 
has time selecting devices in three planes. Each plane includes selector 
storage devices 1a, 1b, 1c and control storage devices 3a, 3b, 3c. A 
majority-selection is made from the connection information from the three 
planes in a majority selector device 8 and the majority-selected 
connection information is delivered to the selector storage devices 1a, 
1b, 1c. A majority selection is made on information from the selector 
storage devices 1a, 1b, 1c in a majority-selection device 7, and delivered 
from the selector storage devices 1a, 1b, 1c on an output line 5. 
British Patent Specification GB 1570 113 describes an invention relating to 
electronic systems which include equipment in parallel planes. The 
equipment operates with majority-selection, so as to obtain correct output 
signals even though an error/fault might occur. The object of the 
invention is to provide an arrangement for localizing errors/faults in the 
system. The error/fault localization is program-controlled and functions 
on the concept of testing one unit at a time. The selection information 
comes from a programmable read only memory (PROM). Each plane includes a 
device WSU for wave shape selection, these devices WSU being operative to 
cause the unit selected for testing to carry out a given operation so that 
a waveshape corresponding to said operation is formed. The generated 
waveshapes produced in the parallel planes in said unit are sent to a 
comparator CCU, in which they are compared, therewith enabling the 
detection of an error/fault in any one of the planes. 
SUMMARY OF THE INVENTION 
The present invention is a method and a device for detecting errors in a 
multi-plane processing unit of a digital time switch without the need to 
compare large quantities of data or the requirement that signals be 
synchronous through the digital time switch in all cases. 
The multi-plane unit of the digital switch preferably comprises three 
electrically identical planes, i.e., triplicated equipment arranged in 
three planes. Each plane has a plurality of sections and each section 
comprise equipment that is electrically identical to equipment in 
corresponding sections in the other planes, i.e., equipment in the first 
section of plane A is electrically identical to equipment in the first 
section of planes B and C. Similarly, equipment in the nth section of 
plane A is electrically identical to equipment in nth section of planes B 
and C. 
When data is input to the multi-plane unit of the time switch, the same 
data is input to each first section in each plane. Equipment, e.g., the 
processor, in each first section of each plane processes the data. The 
output from each such processor is connected to the input of the equipment 
in the immediately subsequent section of each respective plane. In other 
words, the sections in a plane are connected in series. The data continues 
to flow through each plane in this manner until reaching the final 
section. The output of the final section of each plane is input to a 
majority selection device. If there are no errors in the time switch, the 
output from each final section of each plane will be the same and the 
majority selection device will output the data output from the final 
sections. If an error has occurred in the time switch, the majority 
selection device will compare the outputs from the final sections of the 
three planes, and if two of the three outputs are the same, will output 
that data. 
Each section in each plane also contains a data signal compressor which may 
be connected either to the input or the output of the equipment, e.g., the 
processor, in the section. Compressed data signals ar generated over 
certain time intervals. For example, if the data flowing through the time 
switch has a frame format or similar configuration, an appropriate time 
interval would be one compression per frame. The compressed data signal in 
corresponding sections is compared. If the switch does not experience an 
error, the compressed data from corresponding sections in each plane will 
be the same and when this compressed data is compared, the comparator will 
not indicate an alarm. When a difference is detected between the 
compressed data signals in corresponding sections, the comparator 
comparing the compressed data signals will indicate an error in those 
sections. 
Because compressed signals are used for comparison rather than basing the 
comparison on the whole of the data flow through the switch, neither the 
signal flowing through the switch nor the processors are affected by the 
error detecting of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
A multi-plane unit utilizes a comparator/majority-selection device for 
delivering a correct output data signal from the multi-plane unit. It is 
therefore important that a certain error/fault will not occur 
simultaneously in two or more of the planes, since the majority-selection 
device would otherwise deliver an erroneous output data signal. 
Consequently, if a first error/fault occurs in one of the planes, it is 
necessary to remedy this error/fault as quickly as possible, in order to 
avoid the risk of the same error/fault occurring in a parallel plane 
before the first error/fault is remedied. 
Accordingly, the object of the present invention provides a method and an 
arrangement by means of which an error/fault occurring in one plane in a 
multi-plane unit can be detected and the faulty equipment accurately 
localized. 
Application of the method described in Swedish Patent Application SE 
8705065-4 employing bit-for-bit comparison between corresponding 
information originating from parallel planes for the purpose of solving 
the aforedescribed technical problem places high demands on synchronism in 
the multi-plane unit and also requires large quantities of data to be 
processed, particularly when the system operates with high bit-speeds and 
when comparisons are effected at many locations in the planes. When using 
an arrangement according to the Swedish patent application, it is 
necessary for the data-flow through the multi-plane unit to be synchronous 
at all of the locations at which comparisons are made, since the 
comparisons are made bit-for-bit on the whole of the data-flow. In the 
case of high-speed data-flow, such comparison becomes complicated and 
therewith expensive. 
The British Patent GB 1 570 113 attempts to solve the aforesaid problem by 
localizing errors/faults in a system which utilizes equipment in several 
parallel planes. The drawback with this method is that a large amount of 
equipment is required, since error/fault localization is program 
controlled and since the localization of errors/faults does not utilize 
the through-passing data-flow. 
The present invention is characterized by the features set forth in the 
following claims, and in brief, comprises the step of generating in a 
multi-plane unit having sections of equipment in three parallel working 
planes, for each of corresponding parallel sections at corresponding 
locations, a compressed version of the data signal entering the section 
and/or of the data signal exiting from said section. Corresponding 
compressed data-signals are then compared, and an alarm is given when the 
comparison shows that the compared, compressed data signals differ from 
one another. The compressed data signals are generated over given time 
intervals. If the data-flow through the multi-plane unit has a 
frame-format of some configuration or other, an appropriate time interval 
in this regard is one compression per frame. 
The inventive method and arrangement results in a reduction in the quantity 
of data handled during the comparison process, since the comparison is 
made on the basis of compressed signals instead of on the basis of the 
whole of the data-flow. Because the comparison material has been made much 
smaller, there is less need for the comparison to manage large quantities 
of data. 
The requirement for the signals through the multi-plane unit to be 
synchronous, is limited to those signals which are delivered to the 
comparator/majority-section device from the last section in each of said 
planes. In other respects, the data signals through the unit need not be 
synchronous, since comparisons are made between compressed versions of the 
data-flow. On the other hand, comparisons must, of course, be made between 
compressed signals which derive from one and the same time interval or one 
and the same frame of the through-passing data-flow. 
Since the compressed signals include a smaller quantity of information per 
frame than the original signals, the comparison can be made under 
relatively quiet conditions, which means that the comparison need not be 
made in the immediate physical vicinity of each section, but can be 
carried out centrally, and also enables several section units to utilize 
one and the same time-shared comparator. A section unit includes 
corresponding parallel sections having mutually identical equipment. 
FIG. 1 is a block schematic of a multi-plane unit 10 incorporated in a 
digital time switch. The multi-plane unit 10 has three parallel working 
planes A, B, C each provided with mutually identical equipment 11. The 
equipment 11 in each of the planes A, B, C is divided into sections, and 
the planes are also divided into sections in a corresponding manner. The 
plane A is divided into n number of sections 12, designated A.sub.1, 
A.sub.2.. . . , A.sub.n. The remaining planes B, C are divided 
correspondingly into sections 12, designated B.sub.1, B.sub.2. . . , 
B.sub.n and C.sub.1, C.sub.2. . . , C.sub.n. Corresponding parallel 
sections 12 in the three parallel working planes, for instance the 
sections A.sub.1, B.sub.1, C.sub.1, contain mutually identical equipment 
11 and form a section unit 13. The equipment incorporated in the section 
units may, for instance, have the form of different types of data storage 
devices. The first section unit 13 includes the sections A.sub.1, B.sub.1, 
C.sub.1, the second section unit (not shown in the FIGURE) includes the 
sections A.sub.2, B.sub.2, C.sub.2, and so on. The equipment 11 associated 
with the plane A is connected together by data lines 14 entering the 
sections A.sub.1, A.sub.2, . . . , A.sub.n of the plane and by data lines 
15 exiting from said plane sections. The equipment associated with the 
plane B and the equipment associated with the plane C are respectively 
connected in a corresponding manner. 
Data-flow DATA.sub.in entering the multi-plane unit 10 is distributed to 
the parallel sections A.sub.1, B.sub.1, C.sub.1 in the first section unit 
13. The equipment 11 in each of the sections A.sub.1, B.sub.1, C.sub.1 
therewith receives an incoming data signal IN on the data input line 14 of 
each section. The incoming data signals IN in the first section unit 13 
thus correspond to the data-flow DATAin entering the multi-plane unit 10. 
The equipment 11 in each of the sections A.sub.1, B.sub.1, C.sub.1 in the 
first section unit processes the incoming data signal IN, whereafter said 
equipment 11 delivers an outgoing data signal OUT on the section-output 
data line 15. 
The data output signals OUT are conveyed further to the next section unit 
13 and, prior to having passed through the equipment of said second unit, 
constitute incoming data signals IN. Incoming data signals IN and outgoing 
data signals OUT pass through the equipment in remaining section units 13 
in a similar manner, wherein said data signals constitute a data-flow 
which passes through the multi-plane unit. When the through-passing 
data-flow has passed the equipment 11 in the last section unit 13 in line, 
the output data signals OUT are transmitted from said last unit to a 
comparitor/majority selection device 16. The signals entering the device 
16 are compared bit-for-bit and are majority selected, and a 
majority-selected output data-flow DATA.sub.out is delivered from the 
multi-plane unit 10. 
In order to enable an error/fault in the unit 10 to be detected and 
localized accurately, each section 12 includes a compression device 17 
connected to the output data line 15 of the section 12. The compression 
device 17 is operative to generate a compressed version of the output data 
signal OUT without influencing said signal. This signal generation results 
in a compressed data signal CO. If the data-flow in the multi-plane unit 
10 is divided into frames, a compressed signal CO will be conveniently 
formed for each frame information in the output data signals OUT. It is 
also possible to form the compressed signal CO from information in some 
other interval. Each of the compression devices 17 is connected to a 
register 18 in which a compressed signal CO can be temporarily stored. The 
register 18 also contains information relating to the frame from which the 
compressed signal CO originated. The registers 18 corresponding to 
sections A.sub.1, B.sub.1, C.sub.1 in the first section unit 13 are 
designated Reg A.sub.1, Reg B.sub.1, Reg C.sub.1 illustrated in FIG. 1. 
The registers 18 connected to remaining sections are designated in a 
corresponding manner. In order to enable errors/faults to be localized, a 
comparitor 19 is connected to the registers 18 associated with one and the 
same section unit, so as to compare compressed signals CO from 
corresponding sections 12. A comparitor 19 is therefore connected to the 
registers 18 designated Reg A.sub.1, Reg B.sub.1, Reg C.sub.1, and a 
further comparitor 19 is connected to registers 18 designated Reg.sub.An, 
Reg.sub.Bn, Reg.sub.Cn, and so on. The comparison entails comparing 
compressed signals CO which have their origin in output data signals OUT 
from one and the same frame, wherein the compared signals derive from one 
and the same data quantity. When the compared compressed-signals CO are 
identical, no error and/or fault is detected, but if one of the compared 
compressed-signals CO differs from the other two in some way or another, 
this will indicate a fault or error in the equipment 11 in the section 12 
from which the deviating signal was delivered, which results in the issue 
of an alarm signal AL by the comparitor 19. 
The aforesaid generation of compressed signals CO may be effected, for 
instance, in accordance with the Cyclic Redundancy Check (CRC) principle, 
in which case the compression device 17 includes shift registers and 
exclusive-or-gates. Depending on the frame-size of the through put 
data-flow and the desired probability of error/fault discovery, there is 
selected an appropriate compression algorithm which decides how shift 
registers and exclusive-orgates shall be arranged in the compression 
devices 17. When a compression device 17 has received information from a 
frame in the output data signal OUT, the shift registers will obtain a 
reduced quantity of information, i.e. a reduced number of bits in relation 
to the number of bits in a frame. The reduced quantity of information is 
delivered from the shift register of the compression device 17 to the 
register 18 in the form of a compressed signal CO. As before described, a 
comparison is then made between the information contained in three 
registers 18 associated with sections 12 of one and the same section unit 
13, this comparison being made in the comparator 19 connected to said 
section unit. One comparison at a time compares corresponding bits from 
the three registers 18. If one of the compared bits differs from the two 
remaining bits, the aforesaid alarm signal AL is given, this signal also 
indicating the parallel section from which the deviating bit arrived. The 
equipment in the faulty section can therewith be replaced. 
The aforedescribed procedure enables errors/faults to be detected in a 
multi-plane unit, both with respect to single intermittent errors/faults 
and with respect to a continuous error/fault state. A deviation in any one 
of the sections results, with desired probability, in the compressed 
version of the output data signal of the faulty section to deviate from 
the other output data signals. 
It is not necessary to generate the compressed signal CO at that location 
in the section at which the output data signal OUT is transported, since 
the signal can also be generated at other locations in said section. The 
main criterion is that the compressed version is generated at 
corresponding locations in sections associated with one and the same 
section unit, so that the data quantity from which the compared compressed 
signals CO originate is one and the same. For instance, it is possible 
instead to generate, for each section, a compressed version of the 
incoming data signal IN and to effect a comparison in the aforedescribed 
manner, wherein a detected error/fault indicates a fault in the preceding 
section unit. Alternatively, there may be generated for each section both 
a compressed version of the incoming data signal IN and a compressed 
version of the outgoing data signal OUT, so as to detect both error/fault 
in the equipment and in the data transmission between two section units. 
Since the compressed signals CO, for each frame, include a smaller quantity 
of information than the original signals, the comparisons can be made 
under relatively quiet conditions, therewith enabling the comparisons to 
be made centrally and remote from the immediate physical vicinity of the 
sections. This also enables a time-shared comparitor to be used in common 
by several section units. 
FIG. 2 illustrates a time-shared comparator 20 which is operative to 
carry-out comparisons on compressed signals CO from the first section 
unit, these signals being stored intermediately in registers 18 designated 
Reg A.sub.1, Reg B.sub.1, Reg C.sub.1, and also to carry-out comparisons 
on compressed signals CO from the second section unit, these signals being 
stored intermediately in the registers 18 designated Reg A.sub.2, Reg 
B.sub.2, Reg C.sub.2. The comparison carried-out on the signals from the 
two section units is effected i.e. implemented, alternately under the 
control of a control signal CONTROL, wherein a comparison is made on the 
signals from both the first and the second section units during the period 
of one frame. The control signal CONTROL therewith controls three register 
switches 21 in a manner such that the registers Reg A.sub.1, Reg B.sub.1, 
Reg C.sub.1 of the first section unit are connected to a comparator 22 
during a first part of a frame. During this first part of said frame, the 
control signal CONTROL is also operative to control an alarm switch 23 in 
a manner to cause an alarm signal AL.sub.1 associated with the first 
section unit to be given if an error/fault is detected during said 
comparison. During a second part of said frame, the control signal CONTROL 
is operative to control said register switch 21 in a manner to connect the 
registers Reg A.sub.2, Reg B.sub.2, Reg C.sub.2 of the second section unit 
to the comparator 22 instead. During this second part of the frame, the 
alarm switch 23 is controlled so that an alarm signal AL.sub.2 associated 
with the second section unit is given when an error/fault is detected.