Configurable mixed-signal systems

An electronic system includes a configurable processing device. The configurable processing device includes a processor that performs digital processing, a first input that receives digital signal, a first output that sends digital signal and a converter that converts between analog and digital signals. The converter includes a delta-sigma modulator.

FIELD OF THE INVENTION

The present invention relates to the design of electronic systems in general and, more particularly, to mixed-signal electronic systems implemented with digital programmable circuitry.

BACKGROUND OF THE INVENTION

Electronic systems are driving innovation in daily life for many. An aspect of this is sometimes called ubiquitous computing or ambient intelligence. Electronic systems can perceive the environment by processing data from individual sensors or from entire sensor networks. Such electronic systems working with the internet can form Cyber-Physical Systems (CPS) that can make daily life more safe, more secure, more energy efficient, or simply more convenient.

Electronic systems need to interface with the “real” world by reading heterogeneous information, data, or signals from sensors, for example to process that data in some way and to output the results to interact with the environment via actuators. An embedded system is an electronic processing system that is functionally integrated with a target system. The target system typically is a mechanical system (or has at least some mechanical components or aspects), such as, for example a washing machine, a printing machine, a vehicle, an airplane, a manufacturing robot, or a medical diagnostic system. One or more embedded systems become a component of target system, as further discussed in Wolf, W. H. (2001), “Computers as Components: Principles of Embedded Computing System Design”, Morgan Kaufman, which is herein incorporated by reference. The design of embedded systems, including, for example, hardware, software, firmware, computer architecture, real-time functionally, and so on, is well researched and documented, for example in Marwedel, P. (2010), “Embedded and cyber-physical systems in a nutshell” DAC.COM Knowledge Center Article. Connection of embedded systems to the Internet is discussed, for example, in “Cyber-Physical Systems” Lee, E. A. (2008); “Cyber Physical Systems: Design Challenges”; International Symposium on Object/Component/Service-Oriented Real-Time—ISORC 2008 which is herein incorporated by reference.

To be applicable and economically feasible, embedded systems must provide sufficient flexibility, for example, to adjust to changes in the data processing or to alterations in inputs and/or outputs. Therefore, it is highly desirable if an embedded system is built as a configurable system where changes can be applied over its lifecycle. Configurable Processing Devices (CPDs) are established semiconductor parts for implementing configurable systems. CPDs have a strong foothold in certain industries where configurability is key. For example, in networking, telecommunications, and military industries, embedded systems are used to implement entire data processing systems or at least significant portions thereof.

Field programmable gate arrays (FPGAs) are one type of CPD and are, for example, available from Xilinx Corporation, Altera Corporation, Lattice Semiconductors and other sources.

TERMINOLOGY

The following discussions will be made clearer by a brief review of the relevant terminology as it is typically (but not exclusively) used. Accordingly, to assist readers in understanding the terminology used herein, the following definitions are provided.

“Software” is defined as, but not limited to, programming language content written using a programming language. Examples of programming languages include C, C++, Basic, assembly, and Java.

“HDL” is a Hardware Description Language. A hardware description language is defined as any programming language that can describe the hardware portion of an electronic system. Examples of HDLs include VHDL which is described in the IEEE Standard 1076-2008 available from the Institute of Electrical and Electronic Engineers in Piscataway, N.J., which is hereby included in its' entirety by reference; Verilog HDL which is described in the IEEE Standard 1364-2005 available from the Institute of Electrical and Electronic Engineers in Piscataway, N.J., which is hereby included in its' entirety by reference; the various extensions of Verilog HDL, for example, OVL or SystemVerilog as, for example, described in “SystemVerilog 3.0—Accellera's Extensions to Verilog”, both published by the Accellera Organization, Inc. in Napa Calif.; the SuperLog language from Co-Design Automation in Los Altos, Calif.; the Sugar verification language, originally developed by IBM Haifa Research Lab, Haifa, Israel; the “e” Verification Language from Verisity, Inc. in Mountain View, Calif.; and SystemC which is described in the IEEE Standard 1666-2011 available from the Institute of Electrical and Electronic Engineers in Piscataway, N.J., which is hereby included in its' entirety by reference; General purpose programming languages such as JAVA, C++, C, and assembly languages may also be used as a HDL.

“Verilog-AMS” is a derivative of the Verilog HDL. It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator, which solves the differential equations in analog-domain.

A “RAM” is a Random Access Memory—defined as an electronic component capable of storing data.

“ASIC” is an Application Specific Integrated Circuit. An ASIC device is an electronic component of a system. ASICs are custom devices created for a specific purpose within the electronic system.

ASIC devices are easier and faster to create with respect to a full custom semiconductor device. An ASIC may be described using HDL and implemented using synthesis and may be a digital, or a mixed-signal, or an analog integrated circuit optimized and built for a specific application.

A “Programmable Circuit” is an integrated circuit device which can be user-programmed, or configured, without a manufacturing step, typically by uploading a configuration bit file into the device after power-up.

An “FPGA” is a Field Programmable Gate Array. FPGAs are electronic components that have a configurable function. These devices are able to change their functionality via a configuration information stream transferred to the device and are available from a number of different suppliers in a wide range of sizes and speeds. An FPGA design may be described using HDL and implemented using synthesis.

A “PLD” is an Programmable Logic Device. PLDs are electronic components that have a configurable function. These devices are able to change their functionality via a configuration information stream transferred to the device and are available from a number of different suppliers in a wide range of sizes and speeds. A PLD design may be described using HDL and implemented using synthesis.

An “FPAA” is a Field-Programmable Analog-Array, a special analog Programmable Circuit device.

A “CPLD” is a Complex Programmable Logic Device, another special Programmable Circuit device.

A “CPD” is a Configurable Processing Device which is an electronic component that has a configurable function and which includes some portion of a programmable, digital circuit, or programmable logic gates and/or spatial computing fabric.

A “Central Processing Unit” or “CPU” is circuitry controlling the interpretation and execution of software programmed instructions, performs arithmetic and logical operations on data, and controls input/output functions. For the following descriptions the term CPU may be used to also denote other processing elements such as microprocessors, digital signal processors, microcontrollers, etc.

A “FSM” is a Finite State Machine which can be implemented in a digital circuit—defined as an electronic system control structure. The design and implementation of FSM is described in great detail in Synthesis and Optimization of Digital Circuits, by Giovanni DeMicheli, McGraw Hill, 1994.

A “NCO” is a “Numerically Controlled Oscillator” which is an electronic component to operate as a digital signal generator which creates a synchronous, clocked discrete-time, discrete-valued representation of a waveform.

A “DSP” is a Digital Signal Processor, a CPU highly optimized towards processing digital signal values.

An “ASSP” is an Application-Specific Standard Processor which is an integrated digital circuit device which includes one, or more, CPUs, plus application-specific circuitry.

A “Microcontroller” or “MCU” is a digital and/or mixed-signal integrated circuit device which includes one, or more, CPUs plus special-purpose peripherals and inputs/outputs.

A “SOC” is a “System-on-a-Chip” which is defined as a device large enough to contain an entire electronic system implementations. SOC devices can integrate a number of electronic devices into one device and are digital and/or mixed-signal integrated circuit device which includes one, or more, CPUs, special-purpose peripherals, inputs/outputs, application-specific circuitry, memory, etc.

A “PSOC” is a “Programmable System-on-a-Chip” which is a SOC which is implemented using Programmable Circuits and which are a special form of CPD.

An “EPP” is an “Extensible processing platform” which is a special form of a CPD where programmable logic is combined with an integrated CPU, typically as a Hard Block.

A “register” is an element in digital circuitry which can store one or more bits. Examples for registers are the various types of flip-flops and latches.

“Electronic Components” are defined as but not limited to, transistors, logic gates, integrated circuits, semi-custom integrated circuits, full custom integrated circuits, application specific integrated circuits (ASICs), gate arrays, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), CPUs, Random Access Memory (RAM), mixed signal integrated circuits, systems on a chip (SOC), and systems on a printed circuit board.

An “Electronic System” is defined as a system that contains one or more digital and/or analog Electronic Components connected together to perform specific operations or functions. An Electronic System can be implemented entirely of hardware (Electronic Components) or consist of a mix of hardware and software (programming language content).

“Mixed-signal Systems” are defined as Electronic Systems which incorporate both digital and analog signals.

The “HDL Design” is referred to as the portion of the electronic system which is described in HDL and implemented in hardware.

An “HDL description” is the textual description of an HDL Design.

“HDL source code” is referring to the text files which contain the HDL description.

“Synthesis” is defined as the process of creating an electronic implementation from the functional description of a system. An example of a tool that performs this operation is Design Compiler from Synopsys, Inc. in Mountain View, Calif., which reads electronic system descriptions written in a synthesizable subset of VHDL and Verilog and produces a technology mapped design as an output.

A “Functional Specification” is defined as the documentation that describes the necessary features and operations of a system.

A “Functional Simulator” or “Simulator” is a tool that mimics the functional behavior of a model of an electronic system which is described using HDL.

A “Hard Block” is an electronic system which has a pre-defined functionality and which can be incorporated into another electronic system. Commonly, the form of the Hard Block is such that the functionality of the Hard Block can not be altered. An example of a hard block is an HDL Design which implements an industry standard bus controller.

“SPICE” is “Simulation Program with Integrated Circuit Emphasis” is used to simulate integrated circuits and board-level design to predict the circuit behavior.

“MATLAB” is a numerical computing environment developed by The MathWorks, Inc.

“Real-time” means a task, process or response occurs substantially immediately. The term is used to describe a number of different computer features. For example, real-time operating systems are systems that respond to input immediately. Real-time is also used for describing tasks in which the computer must react to a steady flow of new information without interruption. Real-time can also refer to events simulated by a computer at the same speed that they would occur in real life.

“Security” is information security as applied to computers, embedded systems and networks, and means the collective processes and mechanisms by which sensitive and valuable information and services are protected from publication, tampering or collapse by unauthorized activities or untrustworthy individuals and unplanned events respectively.

“Safety” is the state of being safe, of being protected against consequences of failure, damage, error, accidents, harm. Functional Safety is freedom from unacceptable risk of physical injury or of damage to the health of people either directly or indirectly (through damage to property or to the environment).

“SIL” is Safety Integrity Level and is defined as a relative level of risk-reduction provided by a safety function, or to specify a target level of risk reduction. In simple terms, SIL is a measurement of performance required for a safety instrumented function according to the European Functional Safety standards based on the IEC 61508 standard, as it is defined in David, S. and Kennath, S. (2004).

Functional Safety, A Straighforward Guide to Applying IEC 61508 and Related Standards. Elsevier Butterworth-Heinemann, which is hereby included in its' entirety by reference, or in Alessandro, B.

(2007). Reliability Engineering—Theory and Practice. Springer Verlag, which is hereby included in its' entirety by reference. ASIL is Automotive Safety Integrity Level, as it is defined in DIN/ISO 26262, which is hereby included in its' entirety by reference.

An “Embedded System” is a computer system designed for specific control functions within a larger system, typically with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts, as it is defined in Marwedel, P. (2010). Embedded and cyber-physical systems in a nutshell. DAC.COM Knowledge Center Article, which is hereby included in its' entirety by reference.

A “PCB” is a Printed Circuit Board.

An “ECU” is an “Electronic Control Unit” and is a generic term for any embedded system that controls one or more of the electrical systems or subsystems in a motor vehicle.

“PLB” is the “Processor Local Bus” which is defined by IBM's CoreConnect on-chip architecture.

“AXI” is the Advanced eXtensible Interface which is part of the Advanced Microcontroller Bus Architecture (AMBA) defined by ARM Ltd.

“OS” is “Operating System” which is Software code for resource, task, and user management of a data processing system.

“GSM” stands for Global System for Mobile Communications and is a standard set developed by the European Telecommunications Standards Institute to describe technologies for second generation digital cellular networks.

“UMTS” stands for Universal Mobile Telecommunications System and is a third generation mobile cellular technology for networks based on the GSM standard.

“LTE” stands for Long-Term Evolution and is a fourth generation mobile cellular technology for networks based on the GSM standard.

“GPS” is Global Positioning System which is a space-based satellite navigation system that provides location and time information in all weather, anywhere on or near the Earth.

“CAN” is Controller Area Network which is a vehicle bus standard ISO 11898 designed to allow microcontrollers and devices to communicate with each other within a vehicle without a host computer.

“MOST” is Media Oriented Systems Transport which is a high-speed multimedia network technology optimized by the automotive industry.

“Flexray” is an automotive network communications protocol developed by the FlexRay Consortium, and which is currently being converted into an ISO standard.

“LIN” is Local Interconnect Network which is a vehicle bus standard or computer networking bus system used within current automotive network architectures.

“ISDN” is “Integrated Services Digital Network” which describes a set of telecommunications standards for simultaneous transmission of voice, video, data, and other network services. and which are defined by the CCITT.

“AFDX” is Avionics Full-Duplex Switched Ethernet which is a data network for safety-critical applications that utilizes dedicated bandwidth while providing deterministic Quality of Service. AFDX is based on IEEE 802.3 Ethernet technology and is described specifically by the ARINC 664 specification.

“SPI” is Serial Peripheral Interface Bus which is a synchronous serial data link standard, named by Motorola, that operates in full duplex mode.

“IIC” is Inter-Integrated Circuit which is a multi-master serial single-ended computer bus invented by Philips that typically is used to attach low-speed peripherals.

“GPIO” is General Purpose Input/Output is generic pins on an integrated circuit whose behavior (including whether it is an input or output pin) can be controlled through software.

“Ethernet” is a family of computer networking technologies for local area networks and is standardized in IEEE 802.3.

“EtherCat” is Ethernet for Control Automation Technology which is an open high performance Ethernet based fieldbus system.

“ProfiNET” is the open industrial Ethernet standard of PROFIBUS & PROFINET International for automation.

“Sercos” is Serial Real-Time Communication System Interface which is a globally standardized open digital interface for the communication between industrial controls, motion devices (drives) and input output devices (I/O) and is classified as standard IEC 61491 and EN 61491.

“TTCAN” is Time-Triggered communication on CAN which is defined by the ISO 11898-4 standard.

“CANOpen” is a communication protocol and device profile specification for embedded systems used in automation. The basic CANopen device and communication profiles are given in the CiA 301 specification released by CAN in Automation.

“UDP” is User Datagram Protocol which is one of the core members of the Internet Protocol Suite, the set of network protocols used for the Internet.

“TCP/IP” is Transmission Control Protocol/Internet Protocol is a descriptive framework for the Internet Protocol Suite of computer network protocols created in the 1970s by DARPA. TCP/IP has four abstraction layers and is defined in RFC 1122.

“IPSec” is Internet Protocol Security which is a protocol suite for securing Internet Protocol (IP) communications by authenticating and encrypting each IP packet of a communication session. IPsec also includes protocols for establishing mutual authentication between agents at the beginning of the session and negotiation of cryptographic keys to be used during the session.

“RS232” is Recommended Standard 232 which is the traditional name for a series of standards for serial binary single-ended data and control signals connecting between a DTE (Data Terminal Equipment) and a DCE (Data Circuit-terminating Equipment).

“RS485” also known as EIA-485, also known as TIA/EIA-485 is a standard defining the electrical characteristics of drivers and receivers for use in balanced digital multi-point systems. This standard is published by the ANSI Telecommunications Industry Association/Electronic Industries Alliance (TIA/EIA).

“USB” is Universal Serial Bus which is an industry standard developed in the mid-1990s that defines the cables, connectors and communications protocols used in a bus for connection, communication and power supply between computers and electronic devices.

“PATA” is Parallel ATA which is an interface standard for the connection of storage devices such as hard disks, solid-state drives, floppy drives, and optical disc drives in computers.

“SATA” is Serial Advanced Technology Attachment which is a computer bus interface for connecting host bus adapters to mass storage devices such as hard disk drives and optical drives.

“PCIe” also known as PCI Express (Peripheral Component Interconnect Express) is a computer expansion bus standard maintained and developed by the PCI Special Interest Group.

“WiFi” is a mechanism that allows electronic devices to exchange data wirelessly over a computer network using the IEEE 802.11 family of standards.

“Bluetooth” is a proprietary open wireless technology standard for exchanging data over short distances, creating personal area networks with high levels of security, a standard which is maintained by the Bluetooth Special Interest Group.

“IRIG” is the “Inter-Range Instrumentation Group” time codes standardized by the Range Commanders Council in IRIG Standard 200-04, for example.

“HART” is the “Highway Addressable Remote Transducer” Protocol which is a standard for connecting smart devices, for example, which is from the Hart Communication Foundation, Austin, Tex.

“SNR” is signal-to-noise ratio and describes the proportion of the wanted Signal to the background noise.

“SFDR” is the Spurious-Free Dynamic Range is the strength ratio of the fundamental signal to the strongest spurious signal in the output.

DETAILED DESCRIPTION

CPDs have exceptional flexibility for interfacing with digital information, data, or signals but lack configurable analog connectivity. Herein is described a new class of electronic systems, so-called configurable mixed-signal systems (CMSS) and how these can be generated based on existing CPDs. Embodiments are discussed below with the accompanying figures. Those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes as the invention extends beyond these limited embodiments.

One embodiment of a CMSS is set out inFIG. 1. A CMSS1001is implemented using a CPD1040. CPD1040includes, for example, a DSP1041, a CPU1042and programming logic1043. CPD1040, for example, has one or more high-speed serialized inputs represented by high-speed serialized inputs1010. CPD1040, for example, has one or more high-speed serialized outputs represented by high-speed serialized outputs1011.

Alternatively, the CMSS1001can, for example, interface with one, or more, high-speed serialized outputs1011, embedded inside CPD1040. Alternatively, the CMSS1001can, for example, interface with one, or more, digital inputs1020, embedded inside CPD1040. Alternatively, the CMSS1001can, for example, interface with one, or more, digital outputs1021, embedded inside CPD1040. Alternatively, the CMSS1001can, for example, interface with one, or more, analog inputs1030, embedded inside CPD1040. Alternatively, the CMSS1001can, for example, interface with one, or more, analog outputs1031, embedded inside CPD1040.

Data processing can be done inside the CPD1040, for example using programmable logic1043, one, or more, digital signal processors (DSP)1041or one, or more, CPU1042. It is obvious, that using multi-chip partitioning for example, CMSS can be implemented using more than one CPD. The high-speed serial inputs1010and/or the high-speed serial outputs1011and/or the digital inputs1020and/or the digital outputs1021can, for example be used to implement certain standard or de facto standard connectivity such as USB, Ethernet, DDR3 memory interfaces, SATA, SPI, I2C, etc.

In one embodiment there is implemented one, or more, analog inputs1030and/or the one, or more, correspondent analog outputs1031using a technique called delta-sigma modulator. Delta-sigma modulator, or sometimes also called sigma-delta modulators, or sigma-delta converters, or delta-sigma converters are an innovative approach for converting information, data, or signals between the analog domain and the digital domain. Delta-sigma modulators are, for example, described in Aziz, P., Sorensen, H., and van der Spiegel, J. (1996), “An overview of sigma-delta converters”, Signal Processing Magazine, IEEE, 13(1):61-84, which is hereby included in its' entirety by reference.

When used for converting information, data, or signals from the analog to the digital domain (as so-called analog-to-digital converters, ADC) the delta-sigma modulator can be the ADC component1202ofFIG. 2. An analog signal1101which is an input to the analog-to-digital converter1102is converted into the digital signal1103which is an output to analog-to-digital converter1102.

Typically, a delta-sigma modulator used as analog-to-digital converter includes a summation element1111, a integrator element1112, a one-bit ADC element1113, a sampling element1114, a feedback loop1115, and a one-bit digital-to-analog converter element1116. When used for converting information, data, or signals from the digital domain to the analog domain (as so-called digital-to-analog converters, DAC) the delta-sigma modulator can be the DAC component1202ofFIG. 3. A digital signal1201which is an input to the digital-to-analog converter1202is converted into the analog signal1203which is an output to digital-to-analog converter1202.

Typically a delta-sigma modulator used as digital-to-analog converter includes the summation element1211, the delay element1212, the quantizer element1213, the feedback loop1215.

Another embodiment is a method for generating the necessary components for a CMSS to interface with and to process digital and analog information, data, or signals.FIG. 4describes a method for generating a CMSS, for example the CMSS1001ofFIG. 1. In step4001the requirements are gathered. These requirements can be supplied by a system designer or a design engineer. Requirements gathered can include the sample frequency, the sample resolution, internal data representations, their precision, signal-to-noise ratios, etc. In step4002this method accesses simulation models of the relevant CMSS components. Simulation models can, for example, be SPICE models of transistor level netlists for the CMSS, or Verilog-AMS models of the gate-level netlist of the CMSS, or MATLAB models of the functional description of the CMSS. In step4003, using the simulation models of step4002and based on the requirements from step4001various combinations of parameter settings for different delta-sigma modulator implementations are analyzed and, once requirements are met, are kept as the parameter set4004of a possible solution.

The resulting parameters4004are then used to build a description4005of a CMSS. Such a description can, for example, be a RTL netlist in HDL, or any other synthesizable description suitable for generating a CMSS. In step4006this CMSS description4005is synthesized. Synthesis typically includes place and route for the target architecture of the CPD. The outcome of the synthesis4006is CPD configuration data, for example a CPD bitfile, suitable for configuration and/or programming the CPD in such a manner that the CPD implements the CMSS.

While many approaches for delta-sigma modulator components are known in the art, none of them are suitable for building CMSS. For example, the technique presented in U.S. Pat. No. 7,616,143 issued to Zhu for a Reconfigurable delta sigma analog-to-digital converter and customized digital filters with embedded FLASH FPGA and FLASH memory is hereby included in its' entirety by reference, makes use of dedicated analog-to-digital converter components outside an FPGA device which significantly diminishes the flexibility and, for example, does not allow adding additional analog inputs once the system is manufactured on a PCB. U.S. Pat. No. 8,212,100, which is hereby included in its' entirety by reference, teaches the use of delta-sigma modulator inside FPGA devices but fails to teach how to perform proper signal conditioning and how to obtain the implementation of delta-sigma modulator solely from using programmable logic gates and programmable inputs and/or outputs of a digital FPGA.

Delta-sigma modulator components are very suitable for implementing CMSS with FPGA or other CPD. In one embodiment, the DSM ADC component ofFIG. 5is used which corresponds with a first-order delta-sigma modulator. The DSM ADC component ofFIG. 5utilizes the LVDS input pin pair of CPD5040together with an LVTTL pin of CPD5040for the feedback loop through a network of passive components, namely resistor R1, resistor R2and capacitor C. One input of the LVDS pin pair is driven by reference voltage5002. A flip-flop implemented inside CPD5040is clocked by the sample frequency5004. The information, data, or signals driving DSM ADC input5001is thereby converted into a serial bitstream of output5003to represent the digital sample values. Other than the passive components R1, R2and C all other parts can be embedded inside the CPD5040thereby giving maximal flexibility for implementing analog inputs of a CMSS. Sometimes, it is advantageous to improve the signal-to-noise ratio of the DSM ADC. This can, for example, be done using the concept described inFIG. 6. There, an additional OpAmp5107improves the gain of the input signal5101. Similar toFIG. 5, a network of passive components, namely resistor R1, resistor R2, and capacitor C, is used outside the CPD5140.

Embedded inside CPD5140is a flip-flop clocked with sample frequency5104producing a serial bitstream of DSM ADC output5103.FIG. 7shows another embodiment featuring a second-order delta-sigma modulator. There, the analog input5201goes through a network of passive components resistor R1, resistor R2, resistor R3, resistor R4, capacitor C1, capacitor C2outside the CPD5240. Again, similar toFIG. 5andFIG. 6, an LVDS pin pair is used embedded inside CPD5240clocked by sample frequency5204to compute a serial bitstream of DSM ADC output5203which represents the digital sample values of information, data, or signals at input5201.

The above mentioned DSM ADC components fromFIG. 5,FIG. 6,FIG. 7, as well as their obvious variants, enable a flexible and cost efficient implementation of analog inputs of a CMSS, so-called configurable mixed-signal system input (CMSSI).FIG. 8,FIG. 9, and their obvious variants, then enable flexible and cost efficient implementations for analog outputs of a CMSS, so-called configurable mixed-signal system output (CMSSO).FIG. 8describes a DSM DAC in accordance to one embodiment. Inside the CPD6040digital information, data, or signals at DSM DAC input6001gets converted into a width-modulated signal driving LVTTL pin of CPD6040. This signal then gets converted using the reconstruction filter of passive components resistor R, capacitor C outside CPD6040to become an analog signal driving DSM DAC output6003.FIG. 9shows a variant of the DSM DAC fromFIG. 8that uses a second-order delta-sigma modulator embedded inside CPD6140. Similar toFIG. 8, the resulting width-modulated bitstream drives LVTTL pin of CPD6140which then get converted using the reconstruction filter of passive components resistor R, capacitor C outside of CPD6140to become an analog signal driving DSM DAC output6103. While second-order delta-sigma modulator can result in much better signal-to-noise ratio, they are also less stable which can manifest itself in so-called limit-cycles, signal aliasing or other signal distortions or noise.

Therefore, there is deployed special techniques to stabilize the delta-sigma modulator components and to generate a CMSS with very good quality-of-results. One such enhancement is described inFIG. 10. There, a so-called linear feedback shift register (LSFR) can be used to add some artificial noise to the delta-sigma modulator. Typically inserted in the feedback loop to the DSM DAC, the LSFR takes the serial bitstream result of the DSM DAC as an input6201, generates a slightly noisy signal at output6203to be fed into the DSM DAC. Simulation and experimental results show that this technique can significantly enhance the quality-of-results of the DSM DAC.

One of the key benefits of using delta-sigma modulator for analog connectivity in a CMSS is a Delta-Sigma Modulator's superior signal-to-noise ratio. This advantageous signal-to-noise ratio results from the oversampling and the noise-shaping effects of delta-sigma modulator. However, delta-sigma modulator are also known to be inherently unstable when operating outside a certain parameter space. Obtaining a proper configuration for the analog inputs and outputs of a CMSS is not trivial because one must find a stable and robust operating point for the underlying delta-sigma modulator.

This problem gets even more difficult when the delta-sigma modulator is to be implemented over a wide range of different CPDs, each with different electronic characteristics. Managing and controlling the analog behavior of what was designed, manufactured and tested to conform to digital electronic functioning specifications is the challenge.

Therefore, it is shown how to properly obtain stable and robust delta-sigma modulator configurations for CPD implementations that deliver good signal-to-noise ratio for the analog communication.

One embodiment is a method for finding proper parameter settings for delta-sigma modulator. This method utilizes behavioral models of the circuitry components to build a delta-sigma modulator, for example DSM ADC ofFIG. 5or DSM DAC ofFIG. 8. Fundamental to this novel method is an in-depth understanding of the LVDS Common-Mode behavior behind the LVDS pin pairs of the CMSS, including the behavior of LVDS comparator5009ofFIG. 5or5109ofFIG. 6. This LVDS Common-Mode is, for example explained in Texas Instruments (2008). LVDS Owner's Manual. Texas Instruments, which is hereby included in its' entirety by reference, and which is also denoted by the area7010ofFIG. 11. According to the above referenced LVDS standard this Common-Mode shall be between 250 mV to 350 mV of voltage swing.

During extensive analysis we have found that a typical CPD LVDS comparator delivers a much finer resolution of that voltage swing, sometimes lower than 30 mV. This has a significant impact on the stability and robustness of a delta-sigma modulator built from such a CPD LVDS comparator and, obviously, determines the signal-to-noise ratio and the overall quality-of-results of the CMSS analog processing.

Therefore, it is important to have a close look at the CPD elements used to implement a CMSS. These elements are the LVDS comparator5009ofFIG. 5, or LVDS comparator5109ofFIG. 6or LVDS comparator5209ofFIG. 7, the LVTTL output pin5008ofFIG. 5, the LVTTL output pin5108ofFIG. 6, the LVTTL output pin5208ofFIG. 7, the LVTTL output pin6008ofFIG. 8, the LVTTL output pin6108ofFIG. 9, the CPD flip-flop element5006ofFIG. 5, the CPD flip-flop element5016ofFIG. 6, or the CPD flip-flop elements used to implement delay element6006ofFIG. 8or delay elements6106and6116ofFIG. 9or the delay elements6206ofFIG. 10.

FIG. 12shows a transistor-level circuit description of a typical differential amplifier used for implementing an LVDS comparator. Inputs8001and8002are driven by the analog input signals and the result can be seen at output8003. Other examples of LVDS comparator implementations used in the art for CPD elements can be found in U.S. Pat. No. 7,265,586 issued to Shi-dong Zhou for Programmable differential signaling system, which is hereby included in its' entirety by reference, or in U.S. Pat. No. 7,710,149 issued to Jonathan Chung et al. for Input buffer for multiple differential I/O standards, which is hereby included in its' entirety by reference.

FIG. 13shows a transistor-level circuit description of a typical LVTTL driver which is used for implementing an LVTTL output pin. Other examples of LVTTL output pin implementations used in the art for CPD elements can be found in U.S. Pat. No. 6,271,679 issued to Cameron McClintock et al. for I/O cell configuration for multiple I/O standards which is hereby included in its' entirety by reference, or in U.S. Pat. No. 6,236,237, issued to Wong, M. W. and Chan, M. for Output buffer predriver with edge compensation, which is hereby included in its' entirety by reference.

FIG. 14shows a transistor-level circuit description of a typical flip-flop which is used for implementing a CPD flip-flop. Other examples of flip-flop implementations used in the art for CPD elements can be found in U.S. Pat. No. 6,819,156 issued to Nix, M. A. for High-speed differential flip-flop, which is hereby included in its' entirety by reference, or in U.S. Pat. No. 5,670,896 issued to Sholeh Diba, W. Y. K. for High speed product term assignment for output enable, clock, inversion and set/reset in a programmable logic device, which is hereby included in its' entirety by reference, or in U.S. Pat. No. 4,677,318 issued to Veenstra, K. S. for Programmable logic storage element for programmable logic devices, which is hereby included in its' entirety by reference.

These CPD elements typically show non-linear behavior which must be taken into account when implementing stable and robust delta-sigma modulator for CMSS.FIG. 15shows this non-linear behavior, in an exemplary fashion, for a typical LVDS comparator in a typical CPD, for example the LVDS ofFIG. 12. The voltage swing which corresponds to the LVDS Common-Mode, for example LVDS Common-Mode7010ofFIG. 11, changes significantly depending on the sample frequency, for example sample clock5004ofFIG. 5.FIG. 16shows the non-linear behavior of LVTTL output pin, for example LVTTL output pin9003ofFIG. 13.FIG. 17shows the voltage swing over the sample frequency of the passive filter, for example the passive filter made by passive components R1, R2, C ofFIG. 5or by passive components R, C ofFIG. 8. With this understanding of the electrical behavior of the CPD elements it is now possible to compute proper parameter settings which lead to stable and robust DSM ADC and DSM DAC components for a CMSS.

One embodiment is the method ofFIG. 18for computing proper parameter settings for a DSM ADC. In a first step14001an initial set of parameters is produced. This parameter set can include values for the resistors and capacitors, for example resistors R1and R2ofFIG. 5, capacitor C ofFIG. 5and sample frequency5004ofFIG. 5, for example. Together with a model description14010of the CPD elements which can include a model of the LVDS comparators behavior as described inFIG. 15and/or a model of the LVTTL pin behavior as described inFIG. 16, and/or a model of the passive filter behavior as described inFIG. 17, the initial parameter set is then used for simulating the DSM ADC. Simulation is done in step14002. Such simulation can, for example, be a MATLAB/Simulink simulation, or it can be a SPICE simulation, or it can be any other simulation suitable for analyzing the behavior of the DSM ADC. This simulation14002then computes the bitstream of the DSM ADC, which corresponds to bitstream1103ofFIG. 3, for example for a given analog input signal, corresponding to input signal1101inFIG. 2. The input signal can be any analog signal, although a sine-wave signal with a predetermined frequency is best suitable for latter Fourier-Transformation and spectral analysis. In step14003this bitstream is then passed through a Fourier-Transformation (FFT) to obtain a spectrum of the digital sample output of the DSM ADC.

In step14004the signal-to-noise ratio (SNR) and/or SFDR values or any other metric suitable for analyzing the sample output signal quality, are computed. In decision14005it is checked whether the current parameter settings result is the so-far best sampling quality. If this is the case, in step14006the current parameter settings are stored as the best parameter set. Then, in decision14007it is checked whether any additional parameter settings shall be analyzed. If so, then the next parameter settings is operated on in step14008and the algorithm goes back to the simulation step14002to analyze the quality of this next parameter settings. If no more parameter settings shall be analyzed, the algorithm is finished and the parameter settings providing the best quality-of-results which were stored in step14006, can be retrieved.

Because in a typical scenario many different parameter settings must be analyzed and thus many simulation runs (in step1402) must be performed, it is crucial to select a simulation method, and obviously simulation models14010, that provide a good trade-off between simulation accuracy and simulation runtime.FIG. 29shows an exemplary model of a DSM ADC model suitable for simulation with MATLAB. Module25010shows the whole MATLAB model which is generated from the Simulink blocks for the sine source, the summation element, the Integrator, the comparator, the zero order hold module and the data type conversion module. In general, MATLAB models simulate in very short runtime but may lack the accuracy for certain applications of CMSS.FIG. 30shows an exemplary model of a DSM ADC suitable for simulation in Verilog-AMS. Module26010shows the different elements, the delta-sigma modulator is built from which are the stimulus, the reference voltage, the low-pass filter, the comparator, the flip-flop and the LVTTL pin. In general Verilog-AMS models take more runtime during simulation but typically can be more accurate than MATLAB models.

FIG. 31shows a SPICE simulation model of a DSM ADC suitable for simulation with SPICE. In general, SPICE models are very accurate models but may take long run-times during simulation.

FIG. 32shows an exemplary model of a DSM DAC suitable for simulation with MATLAB.FIG. 33shows an exemplary model of a DSM DAC suitable for simulation with Verilog-AMS. Sometimes not only a model of the CPD is available but their precise individual semiconductor integrated circuit. In this case, the CPD element circuitry can be characterized, for example at transistor-level or at geometry-level and a very precise model for the CPD elements can be obtained which greatly enhances the outcome of the algorithm ofFIG. 18andFIG. 19, for example.

The overall quality of analog signal processing in a CMSS is greatly influenced by proper parameterization of the underlying delta-sigma modulator, but also by other system-level aspects. This adds to the complexity as obviously a holistic design approach must be taken. This includes digital signal processing methods suitable and optimized for post processing the sample values received from a delta-sigma modulator in a CPD, for example.

FIG. 20describes the structure of analog input signal processing inside a CMSS, in accordance to one embodiment. A CMSS input component (CMSSI)16001is implemented inside a CPD16040. The analog signal at the input16001is first converted by DSM ADC16011. This DSM ADC16011can, for example, be the DSM ADC ofFIG. 5, or the DSM ADC ofFIG. 6, or the DSM ADC ofFIG. 6, or a DSM ADC computed by the method ofFIG. 18. The bitstream output16011of DSM ADC can then be processed by the moving-average low-pass filter16012. This moving-average low-pass filter can, for example be the moving-average low-pass filter ofFIG. 22, where a bitstream is processed and results in the k-bit wide data representation18003. A typical moving-average low-pass filter can have1024taps. Many techniques are known in the art for implementing moving-average low-pass filter for example using program instructions for a CPU, for example CPU1042ofFIG. 1, or program instructions for a DSP, for example DSP1041ofFIG. 1. From a resource perspective the moving-average low-pass filter can be very efficiently implemented using programmable logic gates, for example programmable logic gates1043ofFIG. 1. The k-bit wide response from the moving-average low-pass filter16012can then be processed by the decimation filter16013.

This decimation filter16013can, for example, be the decimation filter ofFIG. 23, where the k-bit wide data stream at decimation filter input19001gets processed and results in the n-bit wide data representation observable at decimation filter output19003. Many techniques are known in the art for implementing decimation filter, for example using program instructions for a CPU, for example CPU1042ofFIG. 1, or program instructions for a DSP, for example DSP1041ofFIG. 1. From a resource perspective the decimation filter can be very efficiently implemented using programmable logic gates, for example programmable logic gates1043ofFIG. 1. The n-bit wide response from the decimation filter16013can then be processed by a calibration filter ofFIG. 24, where a zero offset in the n-bit sample values can be corrected, depending on a negative offset (seeFIG. 24top) or a positive offset (seeFIG. 24bottom). Many techniques are known in the art for implementing calibration filters, for example using program instructions for a CPU, for example CPU1042ofFIG. 1, or program instructions for a DSP, for example DSP1041ofFIG. 1. From a resource perspective the calibration filter can be very efficiently implemented using programmable logic gates, for example programmable logic gates1043ofFIG. 1. The n-bit wide response from the decimation filter16014can then, optionally, be processed by the zero-offset filter16015. This zero-offset filter16015can for example be the zero-offset filter ofFIG. 25, where a n-bit wide data stream witch may have a “ripple” around a median value gets adjusted into a flattened n-bit wide value. Many techniques are known in the art for implementing calibration filter, for example using program instructions for a CPU, for example CPU1042ofFIG. 1, or program instructions for a DSP, for example DSP1041ofFIG. 1. From a resource perspective the calibration filter can be very efficiently implemented using programmable logic gates, for example programmable logic gates1043ofFIG. 1. The n-bit wider response from the calibration filter16014or, optionally, the n-bit wide response from the zero-offset filter16015then represents the input16001. The analog-to-digital converted and filtered sample values are now suitable for further digital signal processing inside the CMSS. It is obvious how to select a representation in n-bit wide data words where the bit-width n matches the processing system's data representation, say 16 bit, for example.

FIG. 21describes the structure of analog output signal processing for a CMSS, in accordance to one embodiment. A CMSS output component (CMSSO) signal17003is obtained by a DSM DAC17011, which can, for example, be computed by the method described inFIG. 19. DSM DAC17011receives digital signal data on its input17001and performs digital-to-analog conversion embedded inside the CPD17040. This is followed by a subsequent reconstruction filter17021, which converts the information, data, or signals into a proper analog signal, observable at the CMSSO17003. This reconstruction filter can, for example be the reconstruction filter21010ofFIG. 26, or the reconstruction filter21020ofFIG. 26, which each receives a serial bitstream at its reconstruction filter input21011, or21021resp., and reconstructs the analog signal, now observable at reconstruction filter output21013, or21023resp. While the reconstruction filter21010, or reconstruction filter21020are built entirely from passive components it is obvious how a reconstruction filter can be built using active comparators such as OpAmps, for example.

Mixed-signal FPGA are a special class of CMSS where functionality is implemented inside an FPGA, or any other CPD, and via using the above mentioned techniques for analog-to-digital converter and digital-to-analog converter the digital FPGA can now connect to analog signals. Such Mixed-Signal FPGA extend the digital-only application domain from FPGA into mixed-signal Domain, but unlike FPGA with dedicated analog inputs or outputs, mixed-signal FPGA can turn almost any of the configurable digital inputs and/or outputs into inputs and/or outputs which can handle analog signals as well. The design of mixed-signal FPGA requires special techniques because the space for theoretically possible but not necessarily well working (nor feasible) solutions is quite large and may require repeated computations, for example the computations performed inFIG. 18, orFIG. 19.

We therefore present a novel computer-aided design (CAD) of mixed-signal FPGA. To become a practical CAD approach, this CAD approach can build on top of existing techniques of electronic design automation for FPGA, or other CPD. Obviously, these techniques can also be used for design automation of CMSS.

FIG. 27shows the method for generating components for a CMSSI, for example CMSSI ofFIG. 20. In a first step23010the initial parameter settings for the DSM ADC are determined. This step23010can, for example, be step14001ofFIG. 18. In the next step23011the analog parameters are retrieved from simulation. This step23011can, for example, be the outcome of the method inFIG. 18where the best parameter settings can be retrieved as a result from step14006. The analog to-digital converter which can be, for example, DSM ADC ofFIG. 5, or DSM ADC ofFIG. 6, or DSM ADC ofFIG. 7is now properly parameterized. In a next step23012the parameter settings for the moving-average low-pass filter are determined. This moving-average low-pass filter can, for example be the moving-average low-pass filter16012ofFIG. 20. The parameter settings of the moving-average low-pass filter can be determined by user interaction, for example via a GUI, or can be computed by a simulation-based optimization routine. In a subsequent step23013the parameter settings for the decimation filter are determined. This decimation filter can, for example be the decimation filter16013ofFIG. 20. The parameter settings of the decimation filter can be determined by user interaction, for example via a GUI, or can be computed by a simulation-based optimization routine. Then the decision23014decides whether additional mixed-signal calibration is needed. If this is the case, then in step23015the calibration filter parameter settings are determined.

This calibration filter can, for example, be the calibration filter16014fromFIG. 20. The parameter settings of the calibration filter can be determined by user interaction, for example via a GUI, or can be computed by a simulation-based optimization routine. Then the decision23016decides whether additional analog-digital filtering is needed. If this is the case, then in step23017the zero-offset filter parameter settings are determined. This zero-offset filter can, for example be the zero-offset filter16015ofFIG. 20. The parameter settings of the zero-offset filter can be determined by user interaction, for example via a GUI, or can be computed by a simulation-based optimization routine. The outcome of the method inFIG. 27is the CMSSI component including the DSM ADC and subsequent signal conditioning, filtering and processing optimized for the application.

FIG. 28describes the method for generating components for a CMSSO, for example CMSSO ofFIG. 21. In a first step24010the initial parameter settings for the DSM DAC are determined. This step24010can, for example, be step15001ofFIG. 19. In the next step24011the digital parameters are retrieved from simulation. This step24011can, for example be the outcome of the method inFIG. 19where the best parameter settings can be retrieved as a result from step15006. The DSM DAC which can, for example, be DSM DAC ofFIG. 8, or DSM DAC ofFIG. 9is now properly parameterized.

In a next step24012the parameter settings for the reconstruction filter are determined. This reconstruction filter can, for example, be the reconstruction filter17013ofFIG. 21. In a subsequent decision24013the reconstruction filter is analyzed for suitability. If the reconstruction filter is determined as not suitable, for example because insufficient signal-to-noise ratio or other electrical signal analysis results, the step24012is repeated. If the reconstruction filter is suitable, the algorithm for the CMSSO computation is finished. The outcome of the method inFIG. 28is a CMSSO component including the DSM DAC and subsequent signal conditioning and filtering, optimized for the application.

CMSS are typically implemented by mounting one, or more, CPD on PCB. PCB manufacturing variations, aging effects or environmental effects may lead to different quality-of-results for one and the same implementation, either over a batch of manufactured and assembled systems, or variations over the lifetime. To counter those adverse effects,FIG. 34describes a system architecture that can calibrate a CMSS automatically, to work around above mentioned effects, for example.

Inside CPD30040is instantiated the analog-to-digital converter30010and the digital-to-analog converter30030. Analog-to-digital converter30010can, for example, be the DSM ADC ofFIG. 5, or ofFIG. 6, or ofFIG. 7, or the CMSSI generated by the method described inFIG. 18, or the CMSSO generated by the method described inFIG. 27. Digital-to-analog converter30030can, for example, be the DSM DAC ofFIG. 8, or ofFIG. 9, or the CMSSO generated by the method described inFIG. 19, or the CMSSO generated by the method described inFIG. 28.

The sample values which are the output from analog-to-digital converter30010are processed by the Auto-Calibration Module30020, The result from the auto calibration module30020is input into the digital-to-analog converter30030. The input of analog-to-digital converter30010is driven by the output of said digital-to-analog converter30030via loopback cable30050. The auto calibration module30030can now generate certain digital signals to be converted into the analog domain by digital-to-analog converter30030and converted back into the digital domain by analog-to-digital converter30010. By looking at the original signal data and by comparing it with the response from digital-to-analog converter and analog-to-digital converter the auto calibration module30020can perform optimization and testing of the signal path, for example, the auto calibration module can adjust parameter settings for the analog-to-digital converter30010, or can adjust parameter settings for the digital-to-analog converter30030, or both. Adjustments may include delta-sigma modulator parameters, or settings for the filters used in the CMSSI and/or the CMSSO. These optimizations may be user-controlled or may be performed in an automated manner.

It is obvious that this system may not only serve for calibrating the CMSS, but it may also be used for analysis and characterization of the signal paths, including the signal path inside the CPD30040, outside of CPD30040, for example on a PCB, or the loopback cable. Thus, in one embodiment, this system serves as a characterization means for analog signal connections such as the loopback cable30050. In one other embodiment, this system serves as a characterization means for one, or more, CPD, in yet another embodiment, this system serves as a characterization means for the PCB.

It is obvious to those trained in the art that the system ofFIG. 34may also have two, or more, signal paths, each with the same analog-to-digital converter or with two, or more, different Analog-to-Digital Converters. Alternatively, the system ofFIG. 34may also have two, or more, signal paths, each with the same digital-to-analog converter or with two, or more, different analog-to-digital converters. Alternatively, the system ofFIG. 34may also have two, or more, signal paths, each with the same CPD or with two, or more, different CPD.

These components can be connected with each other via one, or more, system buses, or via on-chip interconnect such as, for example, PLB, AXI, etc. The digital-to-analog converter components40010can, for example, be the CMSSO components as described inFIG. 21, or the CMSSO components generated by the method described inFIG. 28. The analog-to-digital converter components40020can, for example, be the CMSSI components ofFIG. 20, or the CMSSO components generated by the method described inFIG. 27. It is obvious that using multichip partitioning, for example, the CMSS system ofFIG. 35can be implemented in one single CPD or the CMSS ofFIG. 35can be implemented in two, or more, CPD. It is also obvious that this system manifests itself either as a PCB with one, or more, CPD integrated on said PCB, and where the one, or more, CPD are configured to perform the functioning of the CMSS. Alternatively, the system manifests itself as CMSS configuration data which makes the one, or more, CPD perform said CMSS functioning.

As shown inFIG. 36, embedded inside CPD41040is the microprocessor41200. This microprocessor41200has one, or more, peripherals implemented either also embedded inside CPD41040, or external to CPD41040. Such peripherals can include external RAM41100, or general-purpose input/output (GPIO)41140. Also connected to the microprocessor41200is one, or more, DSM DAC41110and one, or more, DSM ADC41120, both of which are embedded inside the CPD41040. This effectively turns the digital embedded CPD-based microprocessor system into a CMSS. With almost all key components being configurable, i.e. implemented in programmable/configurable logic, such a CMSS can be altered, changed, fixed, augmented, extended during the development and the deployment cycle without major changes to the underlying hardware (the PCB, for example). This has many benefits, including the ability and flexibility to respond to changes in the specification, adoption of evolving protocols, and/or to counter parts obsolescence.

In yet another embodiment is the system ofFIG. 37where embedded inside CPD42040is a so-called Hard Processor System42041which, for example, can include a Dual-Core ARM Cortex-A9 microprocessor core from ARM Ltd., and can also include one, or more, peripheral blocks for USB, Ethernet, UART, SPI, for example. Said Hard Processor System42041is implemented as a so-called hard block. Hard semiconductor IP blocks are not as configurable as the same functionality implemented in programmable logic but, typically, are more compact and as such can be more cost-efficiently be manufactured. Said Hard Processor System42041can be combined with FPGA Fabric42042and FPGA General Purpose I/O42010to implement the configurable portions of a system. For example, FPGA Fabric42042together with FPGA General Purpose I/O42010, despite being digital circuitry, can be used to implement CMSSI and/or CMSSO based on the techniques described herein.

In yet another embodiment, is shown the system ofFIG. 38where embedded inside CPD43040is a so-called Processing System43041which, for example, can include a Dual-Core ARM Cortex-A9 microprocessor core from ARM Ltd., and can also include one, or more, peripheral blocks for USB, Ethernet, UART, SPI, for example. Said Processing System43041is implemented as a so-called hard block. Said Processing System43041can be combined with Programmable Logic43042and Multi Standards I/O43010to implement the configurable portions of a system. Furthermore, Programmable Logic43042together with Multi Standards I/O43010, despite being digital circuitry, can be used to implement CMSSI and/or CMSSO based on the techniques described herein.

Following Moore's Law closely, CPD enjoy a significant increase in programmable logic resources. One effect is that CPD today can be used to implement entire systems within a single programmable device, such as a PSOC. Combined with the techniques described herein, CPD can now be used to migrate digital and analog functionality into one single CPD. One outcome of this is that significant portions of the functionality that used to be spread over many components mounted on a PCB now are inside one single device, which is configurable, an aspect which can be called programmable PCB, or “soft” PCB. When looking at analog-to-digital converter functionality which typically is implemented by mounting dedicated analog-to-digital converter devices on a PCB, the techniques described herein can be seen as a programmable analog-to-digital converter, or “soft” analog-to-digital converter. Similarly, when looking at digital-to-analog converter functionality which typically is implemented by mounting dedicated digital-to-analog converter devices on a PCB, the techniques described herein can be seen as a programmable digital-to-analog converter, or “soft” digital-to-analog converter. Alternatively, when looking at implementations of so-called ASSP which typically are implemented by mounting dedicated ASSP devices on a PCB, the techniques described herein can be seen as a programmable ASSP, or “soft” ASSP.

According to another embodiment,FIG. 39describes a CMSS implemented inside CPD44040which utilizes the DSM ADC and the DSM DAC described herein to interface with Amplitude-Modulated (AM) signals. The element44070is the AM Signal which, for example, can be an ISDN signal, or any other amplitude-modulated signal. The element44010is an analog-to-digital converter which, for example, can be the DSM ADC fromFIG. 5,FIG. 6, orFIG. 7, or generated by the methods fromFIG. 18orFIG. 27. The element44020is a digital-to-analog converter which, for example, can be the DSM DAC fromFIG. 8, orFIG. 9, or generated by the methods fromFIG. 19orFIG. 28. The element44050is a Demodulator for the information, data, or signals generated by the DSM ADC from element44010. This can, for example, be done using an NCO and multipliers. The element44080performs the Signal Processing which can, for example, be the DSP1041, or the CPU1042, or the Programmable Logic1043fromFIG. 1. The element44060is a Modulator for the data generated by element44080and which can be implemented, for example, by an NCO and multipliers.

According to yet another embodiment,FIG. 40describes a CMSS implemented inside CPD45040which utilizes the DSM ADC and the DSM DAC described herein to interface with IRIG signals. The element45010is an ADC which, for example, can be the DSM ADC fromFIG. 5,FIG. 6, orFIG. 7, or generated by the methods fromFIG. 18orFIG. 27. The element45020is a DAC which, for example, can be the DSM DAC fromFIG. 8, orFIG. 9, or generated by the methods fromFIG. 19orFIG. 28. The element45050is a demodulator for the data generated by the DSM ADC from element45010. This can, for example, be done using an NCO and multipliers. The element45055is the decoder for the IRIG data. The element45080performs the signal processing which can, for example, be the DSP1041, or the CPU1042, or the programmable logic1043fromFIG. 1. The element45065is the coder which generates the IRIG Frame from the data received by element45080. The element45060is a Modulator for the data generated by element45065. It can be implemented, for example, by an NCO and multipliers.

According to yet another embodiment,FIG. 41describes a CMSS implemented inside CPD46040which utilizes the DSM ADC and the DSM DAC described herein to interface with HART signals. The element46072is the HART signal complying the HART standard. The element46010is an ADC which, for example, can be the DSM ADC fromFIG. 5,FIG. 6, orFIG. 7, or generated by the methods fromFIG. 18orFIG. 27. The element46020is a DAC which, for example, can be the DSM DAC fromFIG. 8, orFIG. 9, or generated by the methods fromFIG. 19orFIG. 28. The element46050is a Demodulator for the data generated by the DSM ADC from element45010. This can, for example, be done using an NCO and multipliers. The element46056is the decoder for the HART data. The element46080performs the Signal Processing which can, for example, be the DSP1041, or the CPU1042, or the Programmable Logic1043fromFIG. 1.

The element46066is the Coder which generates the HART Frame from the data received by element46080. The element46060is a Modulator for the data generated by element46066. It can be implemented, for example, by an NCO and multipliers.

According to yet another embodiment,FIG. 42describes a CMSS implemented inside CPD47040which utilizes the DSM ADC and the DSM DAC described herein for general audio processing systems. The element47073is a audio system which can deliver or receive audio data or both, deliver and receive. It can for example be a microphone, a CD recorder or a line out socket in a PC. The element47010is an ADC which, for example, can be the DSM ADC fromFIG. 5,FIG. 6, orFIG. 7, or generated by the methods fromFIG. 18orFIG. 27. The element47020is a DAC which, for example, can be the DSM DAC fromFIG. 8, orFIG. 9, or generated by the methods fromFIG. 19orFIG. 28. The element47080performs the Signal Processing which can, for example, be the DSP1041, or the CPU1042, or the Programmable Logic1043fromFIG. 1.

According to yet another embodiment,FIG. 43describes a CMSS implemented inside CPD48040which utilizes the DSM ADC and the DSM DAC described herein for spatial audio processing. The element48074is a microphone array with two or more microphones arranged in a line or a 2 dimensional pattern. The element48010is an ADC which, for example, can be the DSM ADC fromFIG. 5,FIG. 6, orFIG. 7, or generated by the methods fromFIG. 18orFIG. 27. The element48080is the Signal The element47080performs the Signal Processing which can, for example, be the DSP1041, or the CPU1042, or the Programmable Logic1043fromFIG. 1. It calculates from the data of the element48010the spatial data seen in element48090.

According to yet another embodiment,FIG. 44describes a CMSS implemented inside CPD49040which utilizes the DSM ADC and the DSM DAC described herein document for measuring the parameters of a battery consisting of one or more battery modules. This can, for example, be used in an electrical vehicle. The element49075is the battery array which can consist of one or more batteries. The element49010is an ADC which, for example, can be the DSM ADC fromFIG. 5,FIG. 6, orFIG. 7, or generated by the methods fromFIG. 18orFIG. 27. The element48080performs the Signal Processing which can, for example, be the DSP1041, or the CPU1042, or the Programmable Logic1043fromFIG. 1. It calculates from the data of the element49010the electrical parameters of the battery array.

According to yet another embodiment,FIG. 45describes a CMSS implemented inside CPD50040which utilizes the DSM ADC and the DSM DAC described herein to build a control loop. The element50076is an example system which is to be controlled.

The element50010is an ADC which, for example, can be the DSM ADC fromFIG. 5,FIG. 6, orFIG. 7, or generated by the methods fromFIG. 18orFIG. 27. The element50020is a DAC which, for example, can be the DSM DAC fromFIG. 8, orFIG. 9, or generated by the methods fromFIG. 19orFIG. 28.

The element50081is the control loop of the controller which can, for example, be the DSP1041, or the CPU1042, or the Programmable Logic1043fromFIG. 1.

According to yet another embodiment,FIG. 46describes a CMSS implemented inside CPD51040which utilizes the DSM ADC and the DSM DAC described herein to build a motor controller. The element51010is an ADC which, for example, can be the DSM ADC fromFIG. 5,FIG. 6, orFIG. 7, or generated by the methods fromFIG. 18orFIG. 27. The element51020is a DAC which, for example, can be the DSM DAC fromFIG. 8, orFIG. 9, or generated by the methods fromFIG. 19orFIG. 28. The element51082is the motor control unit which can, for example, be the DSP1041, or the CPU1042, or the Programmable Logic1043fromFIG. 1.

According to yet another embodiment,FIG. 47describes a CMSS implemented inside CPD52040which utilizes the DSM ADC and the DSM DAC described herein to build a lightning system using LEDs. The element52078is a LED module. Each system can have one or more LED modules. The element52010is an ADC which, for example, can be the DSM ADC fromFIG. 5,FIG. 6, orFIG. 7, or generated by the methods fromFIG. 18orFIG. 27. The element52020is a DAC which, for example, can be the DSM DAC fromFIG. 8, orFIG. 9, or generated by the methods fromFIG. 19orFIG. 28. The element52083is the Control Unit which can, for example, be the DSP1041, or the CPU1042, or the Programmable Logic1043fromFIG. 1. It can control each LED module and have input parameters such as the ambient light or the temperature of the LED modules.

And, according to yet another embodiment,FIG. 48describes a CMSS implemented inside CPD52040which utilizes the DSM ADC and the DSM DAC described herein to build a class s amplifier which can, for example, be an audio amplifier, or a LED application. The element53083is the control unit which generates the data for the DSM DAC. This can be audio data, or motor control data, or the control commands to a valve. The element53020is a DAC which, for example, can be the DSM DAC fromFIG. 8, orFIG. 9, or generated by the methods fromFIG. 19orFIG. 28. The element53100is the driver circuit which generates the voltages needed driving the power electronics shown on element53110. The element53120is the load which can for example be a speaker, or an LED, or an Motor.

It is obvious that many other amplitude-modulated protocols which have some analog input behavior and/or analog output behavior can be implemented in CMSS using today's CPD, and/or FPGA devices. Thereby, our embodiments disclosed herein enable the efficient and cost-effective realization of electronic systems for sensor fusion, for example, allows enhanced component integration for reducing the foot-print which is required when inserting an electronic system in confined spaces. Furthermore, embodiments disclosed herein allow reduction of the Bill-of-Materials by integrating many analog components into one, or more, CPDs. It also helps reducing the number of variants because with our invention one and the same PCB can be configured to suit different applications.