Channel architecture for memory devices

Systems, apparatuses, and methods related to channel architecture for memory devices are described. Various applications can access data from a memory device via a plurality of channels. The channels can be selectively enabled or disabled based on the behavior of the applications. For instance, an apparatus in the form of a memory system can include an interface coupled to a controller and a plurality of channels. The controller can be configured to determine an aggregate amount of bandwidth used by a plurality of applications accessing data from a memory device coupled to the controller via the plurality of channels and disable one or more channels of the plurality of channels based, at least in part, on the aggregate amount of bandwidth used by the plurality of applications.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, systems, and methods for channel architecture for memory devices.

BACKGROUND

Memory devices may be coupled to a host (e.g., a host computing device) to store data, commands, and/or instructions for use by the host and/or applications running on the host while the computer or electronic system is operating. For example, data, commands, and/or instructions can be transferred between the host and the memory device(s) during operation of an application running on a host, computing, or other electronic system.

DETAILED DESCRIPTION

Systems, apparatuses, and methods related to channel architecture for memory devices are described. Various applications can access data from a memory device via a plurality of channels. The channels can be selectively enabled or disabled based on the behavior of the applications. For instance, an apparatus in the form of a memory system can include an interface coupled to a controller and a plurality of channels. The controller can be configured to determine an aggregate amount of bandwidth used by a plurality of applications accessing data from a memory device coupled to the controller via the plurality of channels and disable one or more channels of the plurality of channels based, at least in part, on the aggregate amount of bandwidth used by the plurality of applications.

Memory devices, such as flash memory devices, may be used to store data in a computing system and can transfer such data between a host associated with the computing system, and/or between applications running on the host associated with the computing system. The data stored in a memory device can be important or even critical to operation of the computing system and/or the application(s) running on the host. Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.

Memory devices that store data within memory cells may be included in a memory system. The data can be accessed by applications running on a host via channels coupled to a controller (e.g., a media controller, a memory device controller, etc.). The channels can comprise back end channels of the controller. The memory device controller can be a media controller such as a non-volatile memory express (NVMe) controller that is tightly coupled to the memory device (e.g., the memory cells, blocks, sectors, etc. of the memory device).

A channel can communicatively couple the application to a memory device and facilitate transmission of data to and from the memory device to the application for execution. Running applications on a host can utilize power from the memory system when the channels are enabled to transmit data from the memory device to the applications. The amount of power used may depend on a quantity of channels that are enabled to facilitate the execution of applications. For example, when the applications are accessing data from a memory device coupled to the controller an amount of power used may depend on characteristics of the applications, which can correspond to the quantity of channels that are enabled.

The amount of power consumed in execution of the applications can be determined by the bandwidth demand of the applications and be referred to herein as a bandwidth demand. In some embodiments, the applications may be running on a front end of the memory system and the amount of bandwidth needed to execute the operations of the applications can be referred to as a front end bandwidth demand. However, in some approaches, additional channels may be enabled than are needed to execute the applications and satisfy the bandwidth demand. Applications can have the same and/or differing bandwidth requirements to execute operations and can correspond to an individual channel to receive data from a memory device or multiple applications may share an individual channel to receive data. In some approaches, each enabled channel may consume a threshold amount of power regardless of the application or applications to which it is providing data. Power consumption of a memory system can increase a temperature of the memory system, waste resources, and/or decrease efficiency. As such, disabling excessive channels can conserve resources, and increase efficiency.

In some approaches, memory systems may be designed to run a limited number of applications to maintain a homeostatic temperature and a level of efficiency. As a number of applications requesting data from the memory devices of the memory system increase, the memory system can experience application execution failures, or an increase in temperature that can cause failures in the execution of the applications. In some approaches, such temperature increases can be mitigated through the use of cooling systems that can reduce application execution failures and other adverse thermal effects. However, such cooling systems can require space (e.g., a footprint) in the memory system and/or additional processing resources to maintain an appropriate temperature for the efficient operation for the applications extracting data from the memory devices.

Because the amount of space (and hence, the amount of space available to provide processing resources and/or cooling systems) available on a memory device can be limited due to various constraints such as form factors, cell densities, memory array architectures, power limitations, and/or desired storage capacities, it can be difficult to provide adequate processing resources on the memory device to operate additional channels and/or provide cooling to the memory system while supplying data stored by a memory device. As a result, due to form factor and/or power consumption limitations, performance efficiency of the memory device can, in some approaches, be limited.

As the storage capability of memory devices increases, these effects can become more pronounced as more and more data is able to be stored by the memory device and therefore accessible to applications running on the host. This can lead to an increase in the number of channels required to provide the data stored to applications. These effects can be further exacerbated by the limitations of some approaches to power management on memory systems described above, especially as the amount of data stored in memory devices increases and the speed at which data retrieval is expected increases.

In contrast, embodiments herein are directed to a channel architecture to provide data to applications using a modularized design based on the amount of bandwidth required by applications accessing data and/or an amount of bandwidth consumed in execution of the applications. For example, in some embodiments, the memory system can reduce its power usage by disabling channels that are not necessary to provide data to the applications. Operations of applications can be consolidated to utilize less channels thereby decreasing an amount of power used by the memory system.

As described herein, the controller can determine a bandwidth demand of applications running and/or communicable with/on the host. The controller may selectively disable one or more channels that are not necessary to provide data to the applications and fulfil the bandwidth demand. In some examples, the disabled channels may not have been utilized to provide data to the applications. In other examples, the operations formerly performed by the selectively disabled channels may be shifted to different (e.g., enabled) channels. The action of shifting operations from a channel selected to be disabled to an enabled channel may be referred to herein as “consolidation.” Disabling channels reduces the amount of power of the memory system which can save resources and decrease a temperature of the memory system.

In addition, in some embodiments, the controller can be prompted to aggregate an amount of bandwidth consumed in execution of applications by an increase in temperature of the memory device, or the addition/reduction of applications accessing data. The aggregation of the amount of bandwidth required can include the controller checking a quantity, an activity level, and/or a priority level of the applications connected to the host. The controller can enable and/or disable the channels providing data to the applications independently such that any encryption, error-correction, or media management logic is conserved while the channels are enabled, disabled, and/or consolidated.

As used herein, designators such as “N,” “M,” “P,” “Q,” etc., particularly with respect to reference numerals in the drawings, indicate that a number of the particular feature so designated can be included. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” can include both singular and plural referents, unless the context clearly dictates otherwise. In addition, “a number of,” “at least one,” and “one or more” (e.g., a number of memory devices) can refer to one or more memory devices, whereas a “plurality of” is intended to refer to more than one of such things. Furthermore, the words “can” and “may” are used throughout this application in a permissive sense (i.e., having the potential to, being able to), not in a mandatory sense (i.e., must). The term “include,” and derivations thereof, means “including, but not limited to.” The terms “coupled,” and “coupling,” mean to be directly or indirectly connected physically or for access to and movement (transmission) of commands and/or data, as appropriate to the context. The terms “data” and “data values” are used interchangeably herein and can have the same meaning, as appropriate to the context.

The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify an element or component in the figure. Similar elements or components between different figures may be identified by the use of similar digits. For example,106may reference element “06” inFIG. 1, and a similar element may be referenced as206inFIG. 2. A group or plurality of similar elements or components may generally be referred to herein with a single element number. For example, a plurality of reference elements112-1, . . . ,112-N (e.g.,112-1to112-N) may be referred to generally as112. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, the proportion and/or the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present disclosure and should not be taken in a limiting sense.

FIG. 1is a functional block diagram in the form of a computing system100including an apparatus including a memory system104in accordance with a number of embodiments of the present disclosure. As used herein, an “apparatus” can refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuitry, a die or dice, a module or modules, a device or devices, or a system or systems, for example. The memory system104can be a solid-state drive (SSD), for instance, and can include an interface108, a controller110, e.g., a processor and/or other control circuitry, and a number of memory devices112-1to112-N, e.g., solid state memory devices such as NAND flash devices, which provide a storage volume for the memory system104. In a number of embodiments, the controller110, a memory device112-1to112-N, and/or the interface108can be physically located on a single die or within a single package, e.g., a managed NAND application. Also, in a number of embodiments, a memory, e.g., memory devices112-1to112-N, can include a single memory device.

As illustrated inFIG. 1, the controller110can be coupled to the interface108and to the memory devices112-1to112-N via one or more channels114-1to114-P and can be used to transfer data between the memory system104and a host102. A channel (e.g.,114-1to114-P) can be a path for signaling or communication between the memory devices (e.g.,112-1to112-N) and the controller110or the controller110and the interface108. Channels114may be physical connections made with a conductor (e.g., metal traces, semiconductor material, etc.). Channels114may be enabled or disabled by operating switches (e.g., one or more transistors) coupled to the channel114and the controller110or the memory device112(or interface108), or the like. In some examples, disabling a channel114means opening a switch or switches to physically or electrically disconnect (or decouple) a channel114thereby removing or opening a signaling path between components or devices.

The interface108can be in the form of a standardized interface. For example, when the memory system104is used for data storage in a computing system100, the interface108can be a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe), or a universal serial bus (USB), a double data rate (DDR) interface, among other connectors and interfaces. In general, however, interface108can provide an interface for passing control, address, data, and other signals between the memory system104and a host102having compatible receptors for the interface108.

The host102can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, an internet-of-things (IoT) enabled device, or a memory card reader, graphics processing unit (e.g., a video card), among various other types of hosts. The host102can include a system motherboard and/or backplane and can include a number of memory access devices, e.g., a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). One of ordinary skill in the art will appreciate that “a processor” can intend one or more processors, such as a parallel processing system, a number of coprocessors, etc. The host102can be coupled to an interface108of the memory system104by a communication channel106.

In some embodiments, the host102can be responsible for executing an operating system for a computing system100that includes the memory system104. Accordingly, in some embodiments, the host102can be responsible for controlling operation of the memory system104. For example, the host102can execute instructions (e.g., in the form of an operating system) that manage the hardware of the computing system100such as scheduling tasks, executing one or more applications116-1to116-M, controlling peripherals, etc.

The computing system100can include separate integrated circuits on the host102, the memory system104, the applications116-1to116-M, the interface108, the controller110, and/or the memory devices112-1to112-N can be on the same integrated circuit. The computing system100can be, for instance, a server system and/or a high-performance computing (HPC) system and/or a portion thereof. Although the example shown inFIG. 1illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures, which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

In some approaches, the memory system104(e.g., the controller110), can use the channels114-1to114-P (collectively referred herein as the channels114) to access data (e.g., a memory cell and/or a group of cells, e.g., a data word, or sector) stored in the memory devices112-1to112-N (collectively referred herein as the memory devices112), for the execution of the applications116-1,116-M (collectively referred herein as the applications116). The applications116can be executed on the host102using data stored in the memory devices112. The term “executed on” may be used interchangeably with other terms such as “resident on”, “deployed on” or “located on,” herein. The channels114are enabled by the controller110to provide the data stored in the memory devices112to the applications116. When the channels116are enabled, they utilize power of the memory system104. A disabled channel draws less power from the memory system104than a channel that is enabled.

In some embodiments, the controller110can determine a bandwidth demand (e.g., a front end bandwidth demand) by determining an aggregate amount of bandwidth used by the applications116running on the host102accessing data from the memory devices112. The controller110may detect the applications116running on the host102to determine the bandwidth requirements and/or a priority of the applications116.

Some applications116may be of a higher priority than other applications116. For example, a high priority application may include applications that provide important information and/or operations to a user of the application and/or the host102, and/or system-critical applications that must be executed in order for a computing system to operate. An application of a lower priority can include an application116that provides entertainment, or less important information to a user for the application and/or the host102. To reduce power consumption and/or to reduce a temperature of the memory system104, the controller110may consolidate data requested for applications116via the channels114to reduce power of the memory system104. For example, the controller110may selectively disable one or more channels114based at least in part on the aggregate amount of bandwidth used by the applications116and/or a level of priority associated with the applications116.

The controller110can selectively disable some channels114while refraining from disabling other channels114. For example, a channel114-1may be providing data from the memory device112-1to application116-1. The channel114-P may be providing data from the memory device112-N to the application116-M. The controller110can determine the aggregate bandwidth used to execute the applications116-1and116-M and, based on the determination of the aggregate bandwidth, selectively disable the channel114-P and consolidate the operations required to execute the application116-M to the channel114-1. Because the controller110can access the memory devices112-1to112-N, the application116-M can still access data from the memory device112-N via the channel114-1. The disabled channel114-P may still be drawing power from the memory system104, but the amount of power used by a disabled channel114-P is less than the amount of power used by the enabled channel114-1. Embodiments are not so limited, however, and in some embodiments, the disabled channel114-P may draw a vanishing (e.g., zero or near-zero) amount of power from the memory system104. In this way, the applications116-1and116-M remain operational while the memory system104reduces power. In other words, the applications116-1and116-M can access data via the channel114-1that remains enabled subsequent to selectively disabling the channel114-P.

Further, the controller110can be configured to disable the channel114-P in an independent manner. The controller110can be configured to move operations between channels such that any media management logic can be preserved. For example, the application116-M can include media management logic such as data error-correction (e.g., ECC) or data encryption which can be preserved as the operations of the application116-M are moved (e.g., consolidated) from the channel114-P to the channel114-1. In this way, the operation of the application116-1and the application116-M can be independent of the channel architecture.

In some embodiments, as described herein, the controller110can determine when an application has become inactive (e.g., dormant, disabled, removed, or otherwise less actively executing operations) and adjust a quantity of channels that are enabled and/or disabled to reduce power usage. When an application116is inactive, it may not be receiving data from a memory device114and/or it may not be receiving data as frequently. In such examples, the bandwidth demand (e.g., the aggregate bandwidth usage of the applications116) may decrease, and the controller110can selectively disable some channels114to reduce the power usage of the memory system104.

In other embodiments, the controller110can determine when an application has become active (e.g., a new application is connected to the host102, a previously inactive application has become active, etc.) and adjust a quantity of channels114that are enabled and/or disabled to accommodate the bandwidth demand. When an application116is active, it may be receiving data from a memory device, the application116may be new to the computing system100, and/or it may be requesting/receiving data frequently and/or at an increased frequency. In such examples, the bandwidth demand may increase, and the controller110can enable the channels114(e.g., previously disabled channels) to fulfil the bandwidth demand of the memory system104.

Embodiments are not limited to approaches where channels are enabled to fulfil a bandwidth demand. In a non-limiting example, the applications116can be of differing levels of priority and can be ranked by the controller110. The controller110can determine that the application116-1is a higher priority than the application116-M. To conserve power, the memory system104may enable the channel114-1to provide data from the memory devices112-1to112-N to the applications116-1and116-N, and may selectively disable the channel114-P. For example, the controller110may prioritize a request for data from the application116-1via the channel114-1ahead of a request from the application116-M to receive data via the channel114-1. In this way, the memory system104can reduce power consumption by refraining from enabling disabled channels114-P to fulfil a bandwidth demand.

The controller110can communicate with the memory devices112-1to112-N to control data read, write, and erase operations, among other operations. The controller110can include, for example, a number of components in the form of hardware and/or firmware, e.g., one or more integrated circuits, such as application-specific integrated circuit(s) (ASIC(s)), field-programmable gate array(s) (FPGA(s)), and/or software for controlling access to the number of memory devices112-1to112-N and/or for facilitating data transfer between the host102and memory devices112-1to112-N. The controller110can include various components not illustrated so as not to obscure embodiments of the present disclosure to control data read, write, erase, etc. operations. Such components may not be components of controller110in some embodiments, e.g., the components to control data read, write, erase, etc. operations can be independent components located within the memory system104.

The memory devices112-1to112-N can include a number of arrays of memory cells. The arrays can be flash arrays with a NAND architecture, for example. However, embodiments are not limited to a particular type of memory array or array architecture. The memory cells can be grouped, for instance, into a number of blocks including a number of physical pages. A number of blocks can be included in a plane of memory cells and an array can include a number of planes.

The memory devices112can include volatile memory and/or non-volatile memory. In a number of embodiments, memory devices112can include a multi-chip device. A multi-chip device can include a number of different memory types and/or memory modules. For example, a memory system can include non-volatile or volatile memory on any type of a module. In embodiments in which the memory devices112include non-volatile memory, the memory devices112can be flash memory devices such as NAND or NOR flash memory devices. Embodiments are not so limited, however, and the memory devices112can include other non-volatile memory devices such as non-volatile random-access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM), “emerging” memory devices such as 3-D Crosspoint (3D XP) memory devices, etc., or combinations thereof. A 3D XP array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, 3D XP non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased.

The memory devices112can provide main memory for the computing system100or can be used as additional memory or storage throughout the computing system100. Each memory device112can include one or more arrays of memory cells, e.g., volatile and/or non-volatile memory cells. The arrays can be flash arrays with a NAND architecture, for example. Embodiments are not limited to a particular type of memory device. For instance, the memory device can include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, among others.

The embodiment ofFIG. 1can include additional circuitry that is not illustrated so as not to obscure embodiments of the present disclosure. For example, the memory system104can include address circuitry to latch address signals provided over I/O connections through I/O circuitry. Address signals can be received and decoded by a row decoder and a column decoder to access the memory devices112. It will be appreciated by those skilled in the art that the number of address input connections can depend on the density and architecture of the memory devices112.

FIG. 2is a functional block diagram in the form of an apparatus201including a front end bandwidth demand218in accordance with a number of embodiments of the present disclosure. The apparatus201can include applications216-1,216-2,216-3,216-4,216-5, and216-M which may be collectively referred to as applications216and be analogous to the applications116described in connection withFIG. 1. Although not illustrated as to not obscure the examples of the disclosure, the applications216may be executed on a host (e.g., the host102ofFIG. 1). During execution of the applications, the applications may access data from a memory system204according to commands generated by a controller210. The memory system204and the controller210may be analogous to memory system104and controller110described in connection withFIG. 1. The applications216can access data from one or more memory devices212which are analogous to the memory devices112-1to112-N described in connection withFIG. 1. The memory device212can be included within the memory system204as illustrated by memory device112ofFIG. 1, or external to the memory system204as illustrated inFIG. 2.

The channels214-1,214-2,214-3,214-4,214-5,214-6,214-7, and214-P can be collectively referred to as the channels214and can be analogous to the channels114-1to114-P ofFIG. 1. Data may be transferred via each of the channels214during execution of an individual application (e.g., the application216-1, the application216-2, etc.) and/or multiple applications216-1to216-M. As described in more detail below, execution of the application(s)216can consume a threshold amount of bandwidth, which can be referred to herein as a “bandwidth demand” (e.g., the front end bandwidth demand218, a back end bandwidth demand, etc.). As used herein, the term “back end” refers to a connection between the controller (e.g., the controller210) and a device (e.g., a memory device214and/or another computing device). As used herein, the term “front end” refers to a connection between a controller (e.g., the controller210) and a computing device (e.g., a host102, an interface108, and/or an application116, etc.).

The front end bandwidth demand218can be an aggregate amount of bandwidth required to execute the applications216. For example, because the channels214can draw power from the memory system204when the channels214are enabled to access data from the memory device212during execution of the applications216, a front end bandwidth demand218may correspond to an amount of power drawn from the memory system204as a result of execution of the applications216. In order to mitigate an amount of power drawn from the memory system204, the controller210may monitor the front end bandwidth demand218. The controller210can reduce power consumption by selectively disabling an individual channel214and/or a portion (e.g., a sub-set) of channels214based on the front end bandwidth demand218. That is, in contrast to approaches in which each channel is generally active, embodiments herein can allow for an amount of power consumed in execution of applications to be reduced by selectively disabling one or more of the channels214based on the front end bandwidth demand218.

In some embodiments, the amount of bandwidth used by each application216can be determined at least in part by the controller210determining an aggregate amount of bandwidth needed by all of the applications216executed by the host. Each of the applications216may include a different bandwidth demand, similar bandwidth demands, or combinations thereof, for execution. In a non-limiting example, application216-1can require 2 GB/s of bandwidth and application216-2can require 10 GB/s of bandwidth, while the remaining applications216-3,216-4,216-5,216-M are inactive. As such, the front end bandwidth demand218is the aggregate amount of bandwidth used by the channels214in providing data from the memory device212to execute applications216-1and216-2(e.g., 12 GB/s in this example). Because the remaining applications216-3,216-4,216-5, and216-M are inactive in this example, the controller210can selectively disable one or more channels214(e.g., channels that would be used by the applications216-3,216-4,216-5, and216-M if the applications216-3,216-4,216-5, and216-M were active) to reduce the amount of power used by the memory system204, while fulfilling the front end bandwidth demand218. Such power reductions can conserve resources, lower temperature, and increase efficiency of a computing system in comparison to approaches that do not allow for channels to be selectively disabled based on the front end bandwidth demand218.

The controller210can selectively enable channels (e.g., previously disabled channels214) when the front end bandwidth demand218increases. For example, the controller210may determine an aggregate amount of bandwidth used by applications216-1and216-2(e.g., the active applications) which are accessing data from memory device212via an individual channel214-1, when channels214-2,214-3,214-4,214-5,214-6,214-7, and214-P are disabled. Subsequently, the controller210can determine a different front end bandwidth demand218when new applications are added and/or become active. In a non-limiting example, applications216-3and216-4can be added and/or become active, and the front end bandwidth demand218may increase. In response to the increased front end bandwidth demand218, the controller210can select a sub-set of channels from the disabled channels (e.g., the channels214-2,214-3,214-4,214-5,214-6,214-7, and214-P) to fulfil the front end bandwidth demand218to execute the newly active applications216-3and216-4. For example, the controller210can cause a sub-set of channels (e.g., the channels214-2and214-3) to be enabled to provide data from memory device212to fulfil the front end bandwidth demand218including the newly active applications216-3and216-4.

In some embodiments, the controller210can monitor the active applications216-1,216-2,216-3, and/or216-4and identify when the applications216have become inactive. When active applications become inactive, the front end bandwidth demand218may decrease, and the controller210can disable a channel214and/or a sub-set of channels214to reduce power consumption. For example, the controller210can determine that applications216-1and216-3have become inactive. For example, during the operation of the memory system204, the controller210can monitor application traffic originating front the host to determine whether an application (e.g., the application(s)216) is active or inactive. That is, the controller210can determine if the applications216-1and216-3have exhibited a reduced bandwidth requirement as a result of no longer being executed. In this example, the controller210can determine which of the channels214correspond to execution of the applications216-1and216-3and disable the corresponding channels214. Continuing with this example, if the application216-1is using the channel214-1to receive data from the memory device212and the application216-3is using the channel214-3to receive data from the memory device212, the controller210may disable one (and consolidate the operations of the newly disabled channel) or both channels (e.g., the channels214-1and214-3) to conserve power based on the determination that the applications216-1and216-3have exhibited a reduced bandwidth requirement due, for example, to no longer being active.

FIG. 3is another functional block diagram in the form of an apparatus301including a front end bandwidth demand318and a machine learning component324in accordance with a number of embodiments of the present disclosure. Although not illustrated inFIG. 3as to not obscure examples of the disclosure, the apparatus301can include a memory system that is analogous to the memory system104and204described in connection withFIGS. 1 and 2. The apparatus301can facilitate execute applications316-1,316-2,316-3,316-4,316-5, and316-M, which may be collectively referred to as applications316and be analogous to the applications116and216described in connection withFIGS. 1 and 2. Although not illustrated as to not obscure the examples of the disclosure, the applications316may be executed on a host (e.g., the host102ofFIG. 1). Although not illustrated as to not obscure the examples of the disclosure, the applications316may be coupled to a memory system (e.g., the memory system104and204ofFIGS. 1 and 2) and a controller210which is analogous to controller110and210described in connection withFIGS. 1 and 2.

The applications316can receive data from one or more memory devices312which are analogous to the memory devices112and212described in connection withFIGS. 1 and 2. The applications316can receive data from the memory device312via channels314-1,314-2,314-3,314-4,314-5,314-6,314-7, and314-P which can be collectively referred to as the channels314and can be analogous to the channels114and214described in connection withFIGS. 1and2. The memory device312can be included within the memory system, or can be external to the memory system.

The front end bandwidth demand318can be an aggregate of the amount of bandwidth used by the channels314to provide data to the applications316from the memory device312during execution of the application316. The controller310can determine an amount of bandwidth used by each of the applications316based, at least in part, on the aggregate amount of bandwidth used to execute the applications316. For example, the controller310can determine a front end bandwidth demand318, and based on the quantity of active applications316, determine which applications316are requiring bandwidth and/or are of a higher priority.

As shown inFIG. 3, the controller310may also include a machine learning component324. The machine learning component324can include, for example, a number of components in the form of hardware and/or firmware, e.g., one or more integrated circuits, such as application-specific integrated circuit(s) (ASIC(s)), and/or field-programmable gate array(s) (FPGA(s)), to monitor application bandwidth demands and/or learn application bandwidth behavior over time.

The controller310and/or the machine learning component324can be configured to determine an aggregate bandwidth usage of the applications316accessing data from the memory device312coupled to the controller310via the channels314. The controller310may identify a portion of the channels314used to access the data and selectively disable a sub-set322of the portion of the channels314based, at least in part on the aggregate bandwidth usage of the applications316. The portion of the channels314may include all of the channels314-1,314-2,314-3,314-4,314-5,314-6,314-7, and314-P or some of the channels (e.g., the channels314-1,314-3, and314-7although embodiments are not limited to disabling these particular channels). The controller310may determine that the front end bandwidth demand318, which can represent the aggregate bandwidth usage of the applications316, can be provided by a quantity of channels314that is less than the portion of channels314supplying the data to the applications316. Responsive to this determination, the controller310can disable the subset322of channels314to conserve power. In a non-limiting example, the sub-set322of channels are illustrated as channels314-6,314-7, and314-P, indicated by the broken circle.

In some embodiments, applications316may access data via the channels314-6,314-7, and314-P prior to the controller310disabling the subset322including the channels314-6,314-7,314-P. In such an example, the applications316utilizing the channels314-6,314-7, and314-P can be transferred to a number of enabled channels (e.g.,314-1,314-2,314-3,314-4, and/or314-5).

In some embodiments, the one or more channels314from the sub-set322can be selectively disabled by the controller310responsive to an indication from the machine learning component324. The indication from the machine learning component324can include information corresponding to an application316being removed from communication with the controller310. For example, the applications316may be running on a host (e.g., the host102ofFIG. 1) and connected to the controller via an interface (e.g., the interface108ofFIG. 1). An application316can be removed from communication with the controller310when the application316is no longer used, has been replaced, is outdated, defunct, etc.

The machine learning component324can indicate to the controller310information corresponding to a reduction in an amount of power used by the applications316. A reduction in an amount of power can indicate that an application316has been removed from communication with the controller310and/or that an application316is accessing (e.g., requesting to access) less data from the memory device312via a controller314than previously (e.g., the application316may be less active). The controller310can receive the indication from the machine learning component324in the form of signaling.

For example, the controller310can receive signaling (e.g., an alert) that indicates when one or more applications316-5and316-M have ceased to receive data from the memory device312. The signaling received by the controller310may prompt the controller310to aggregate the amount of bandwidth used to operate the applications316and determine a new front end bandwidth demand318. Responsive to a new front end bandwidth demand318, the controller310may disable a sub-set322of channels314to reduce power consumption. The machine learning component324and/or the controller310can determine when an application316has increased activity and/or when a new application316has been added to communicate with the controller310and access data via a channel314.

The controller310can receive an indication and/or an alert generated by the machine learning component324responsive to a detected increase in front end bandwidth demand318. An application316can increase the front end bandwidth demand318when it increases in activity (e.g., when the application316increases an amount of data accessed from the memory device). Activity of an application316can increase when the application316is connected to the controller310(e.g., a new application is added to communicate with the controller310), or the application316is accessing data form the memory device312more frequently. The alert received by the controller310may prompt the controller310to aggregate the amount of bandwidth used to execute the applications316and determine a new front end bandwidth demand318to reflect the increase in activity of the application316. Responsive to a new front end bandwidth demand318, the controller310may re-enable the sub-set322of channels314(or a portion of the sub-set322) to accommodate the new front end bandwidth demand318. In some embodiments, the machine learning component324may include circuitry of the controller310that can monitor the applications316for changes in power requirements (e.g., new applications added, applications removed, and/or increases and decreases in activity levels of the applications316).

The machine learning component324can anticipate a front end bandwidth demand318such that the controller310can enable and/or disable channels314to fulfil the front end bandwidth demand318and conserve power. In a non-limiting example, the machine learning component324can monitor the applications316-1,316-2,316-3,316-4,316-5, and316-M and determine that a portion of the applications320(including the applications316-5and316-M) are active (e.g., newly connected to the controller310and/or accessing data from the memory device312). The machine learning component324can transmit an indication to the controller310, and the controller310can aggregate the bandwidth used by the applications to determine a front end bandwidth demand318. The machine learning component324can identify the sub-set322of channels disabled by the controller310based, at least in part, on an anticipated amount of power required in operation of the channels314during execution of the portion of applications320. Based on the determination of the machine learning component324, the controller310can re-enable the sub-set322of channels based at least in part on the anticipated amount of power when the portion of the applications320are included in the front end bandwidth demand318.

FIG. 4is another functional block diagram in the form of a computing system403including a memory system404in accordance with a number of embodiments of the present disclosure. The computing system403can be similar to the computing system100described in connection withFIG. 1. As shown inFIG. 4, the computing system403includes a memory system404, and a controller410which are analogous to the memory systems104,204, and the controller110,210, and310, described in connection withFIGS. 1, 2, and 3. In addition,FIG. 4illustrates memory devices412-1to412-N (which may be collectively referred to as memory devices412and can be analogous to the memory devices112,212, and312described in connection withFIGS. 1, 2, and 3

Although not illustrated inFIG. 4, the memory system404may be connected to a host (e.g., the host device102described in connection withFIG. 1). The memory system404can further include an interface, such as the peripheral interconnect express (PCIe) interface. Although the interface illustrated inFIG. 4is shown as a PCIe408, it will be appreciated that other interfaces, buses, an/or communication paths may be used without departing from the spirit of the disclosure. The PCIe408can be used to connect a host to the memory system404. Further, although not illustrated inFIG. 4as to not obscure examples of the disclosure, applications (e.g., applications116,216, and316described in connection withFIGS. 1, 2, and 3) can be executed (e.g., run on) the host. The applications can be communicatively connected to the controller410via the PCIe408.

The controller410may include a front end bandwidth demand (e.g., the front end bandwidth demand218and318described in connection withFIGS. 2 and 3). As described above, the front end bandwidth demand can be an aggregate of the amount of bandwidth used by the channels414-1to414-P to provide data to the applications from the memory devices412during execution of the applications by the host. The controller410can reduce and/or increase the amount of power used by the memory system404by selectively disabling and/or selectively enabling the channels414-1, to414-P based at least in part on the front end bandwidth demand.

The scheduler425can be provisioned with computing resources and circuitry to orchestrate execution of the applications. For example, the scheduler425can queue requests for data from the applications. In some examples, the controller410may determine a priority level of the applications to conserve power and the scheduler425may facilitate the priority of the requests based the determination of the controller410. Low priority applications may include applications that request data less frequently compared to high priority applications and/or may not be critical applications. A high priority application may include applications that frequently request data compared to low priority applications and/or may be critical to operation of the host and/or the memory system404. For example, some high priority applications may request data from the memory devices412infrequently but the data when executed may be critical to operation of the host and/or the memory system404.

The controller410may selectively disable a portion of the channels414-1to414-P to conserve power, and the scheduler425may prioritize the retrieval of data from high priority applications over the retrieval of data for lower priority applications. Said differently, the controller410may induce a latency in lower priority applications to conserve power for the memory system404. The scheduler425may be coupled to a multiplexer426and selection pins428-1and428-Q. The multiplexer426can be a device that selects between analog and digital input signals received by the selection pins428-1and428-Q and forwards the input signal to an output line (e.g., connected to translator430).

The translator430can receive a selection command from the multiplexer426that can cause one or more of the channels414-1to414-P are to be selectively enabled or disabled. The channel controllers432-1to432-R can be coupled to the channels414-1to414-P and can switch corresponding channels414-1,414-P to an enabled or disabled state responsive to a command or other output from the translator430.

As described above, in some embodiments, the controller410can determine an amount of bandwidth consumed in execution of respective applications executed on the host. The amount of bandwidth consumed can be aggregated to a front end bandwidth demand received by the controller410. The scheduler425may determine a queue of the data requests based on the front end bandwidth demand, a priority of the applications, and/or a signal from the controller410. The controller410can then selectively assert a signal to pins428-1to428-Q coupled to the multiplexer426to cause a respective channel controller432-1to432-R to switch a corresponding channel414-1to414-P to an enabled or disabled state responsive to the asserted (or de-asserted signal).

In some embodiments, the signal(s) asserted to the selection pins428-1and428-Q can be Boolean logical signals (e.g., signals that have a logical value of “0” or a logical value of “1”). If there are two selection pins428-1and428-Q, as shown inFIG. 4, four possible combinations of values can be asserted on the selection pins428-1and428-Q. For example, a logical value of “0” can be asserted on both of the selection pins428-1and428-Q, which corresponds to the channels414-1and414-P being disabled. Similarly, if a logical value of “1” is asserted on both of the selection pins428-1and428-Q, both the channels414-1and414-P can be enabled. Mixed value signals (e.g., a logical value of “0” being asserted on the selection pin428-1while a logical value of “1” is asserted on the selection pin428-Q, or vice versa) can result in one of the channels414-1or414-P being enabled. Embodiments are not limited to the above enumerated scenarios and greater than or fewer than two selection pins428may be provided in the memory device404.

The selection pins428-1to428-Q can correspond to different channels414-1to414-P. In some embodiments, the selection pin428-1can correspond to the channel414-1and the second selection pin428-Q can correspond to the channel414-P. In such embodiments, the controller410can de-assert a signal to the selection pin428-1(e.g., the controller410can assert a logical value of “0” on the selection pin428-1) corresponding to the channel414-1which may be utilized by an application. The translator430may receive a signal corresponding to the de-asserted signal corresponding to the channel414-1and transmit a signal to the channel controller432-1to disable the channel414-1.

Based on the de-assertion signal of the controller410, the channel controller432-1can transfer the access of data from memory device412-1for the application corresponding to the channel414-1to the channel414-P. In this way, the controller410can transfer the execution operation for the application corresponding to the channel414-1to the channel414-P responsive to the de-assertion of the signal to the selection pin428-1.

The controller410can cause the independent operation of the selection pins428-1to428-Q coupled to the multiplexer426. In some embodiments, the controller410can disable channel414-1by de-asserting the signal to the selection pin428-1and assert a different signal to the selection pin428-Q, as described above. The assertion of the different signal to the selection pin428-Q is independent of the de-asserted signal to the selection pin428-1such that the selection pin428-Q refrains from altering its operation responsive to the de-asserted selection pin428-1. For example, the controller410can determine to disable one or more channels414-1to414-P and transfer data access to a different enabled channel. In some embodiments, when data access is transferred to the different enabled channel, the media management logic of the application corresponding to the disabled channel (e.g., encryption, etc.) can be conserved when the operations are transferred. In this way, the controller410can cause the selective independent operation of the selection pins428-1to428-Q to enable and disable the channels414-1and414-P. Said differently, the assertion or de-assertion of the selection pins428-1to428-Q may not affect the operation of the enabled channels.

FIG. 5is a flow diagram505for channel architecture for memory devices in accordance with a number of embodiments of the present disclosure. The flow diagram505includes a controller510which is analogous to the controller110,210,310, and410described in connection withFIGS. 1, 2, 3, and 4.

At block540, the controller510can be configured to aggregate a bandwidth usage. The bandwidth usage may be aggregated by the controller510as a front end bandwidth demand (e.g., the front end bandwidth demand218and318ofFIGS. 2 and 3) and be an aggregate of the amount of bandwidth used by channels (e.g., channels114,214,314, and414ofFIGS. 1, 2, 3, and 4) to provide data to the applications (e.g., applications116,216, and316, ofFIGS. 1, 2, and 3) from the memory device (e.g., memory device112,212,312, and412ofFIGS. 1, 2, 3, and 4) during execution of applications.

The controller510can aggregate a bandwidth usage periodically or responsive to an indication and/or an alert. The aggregation of bandwidth at540may be used to determine a number of channels to selectively enable (to provide increased bandwidth to applications) or selectively disable (to conserve power and/or lower temperature). The controller510can receive an indication from a machine learning component (e.g., the machine learning component324ofFIG. 3) that an application has been added to the computing system (e.g., coupled to the host), and/or an application has been disabled (e.g., removed, dormant, or is no longer being executed). This indication may prompt the controller510to aggregate bandwidth usage to determine if the controller510can selectively disable channels from the computing system.

In some embodiments, the controller510can receive an alert related to a temperature of the computing system that can prompt the controller510to aggregate bandwidth usage in execution of applications to determine if a power usage of a number of enabled channels can be decreased. Temperature can increase when applications are added to the computing system and/or multiple channels are enabled. For example, at box542, the controller may determine the applications that are active (e.g., receiving data from the memory devices) and at block544, determine which application are inactive. Because temperature increases can decrease efficiency of the computing system (e.g., the memory device coupled to the computing system), by selectively disabling one or more channels to reduce the amount of power consumed by a computing system, improved performance of the computing system may be realized in comparison to approaches in which channels are not selectively disabled based on the aggregate bandwidth usage corresponding to execution of applications.

In some embodiments, an inactive application (e.g., the inactive applications544) can become active (e.g., the active applications542) which may increase a power usage and/or increase the temperature of the computing system. To maintain efficiency, the controller510may determine if power consumption (e.g., power consumed by enabled channels) can be reduced. For example, the controller510can receive an alert corresponding to a temperature increase in a memory device coupled to the controller510corresponding to execution of an application. Responsive to the alert, the controller510can determine, at box546, a new aggregate bandwidth usage corresponding to execution of the applications.

The controller510can use the new aggregate bandwidth usage to determine if the temperature can be decreased by selectively disabling one or more channels and/or consolidating the execution of applications. As described above, part of the determination by the controller510may be based on a priority of the applications. For example, at block548, the controller510can determine a priority of the applications whose execution comprise the new aggregate bandwidth usage determined at block546.

In some embodiments, the applications may be of a high priority where the controller510directs a scheduler (e.g., the scheduler425ofFIG. 4) to handle requests for data from the applications as high priority. Said differently, the requests for data to execute the application(s) can be accommodated as they are received as opposed to creating a latency to execute some applications before others. In such an embodiment, at block550, the controller510can refrain from disabling one or more channels. In this way, multiple channels can remain available to provide data from the memory device to the applications.

In some embodiments, one or more of the applications may be of a low priority where the controller510directs a scheduler (e.g., the scheduler425ofFIG. 4) to cause the applications to be executed based on the priority of the applications. For example, the scheduler can create a queue with the high priority applications executed first and lower priority applications executed subsequently to the high priority applications. Said differently, the requests for data to execute the applications can be accommodated based on priority by creating a latency between execution of applications such that some applications are executed before others based on the priority of the applications. In such an embodiment, at block552, the controller510can disable one or more channels, as described above. In this way, power usage and/or temperature can be decreased. In other words, the controller510can determine if it is more important to decrease power and/or lower temperature or handle the execution of all of the applications with the same level of priority.

FIG. 6is a flow diagram representing an example method660of channel architecture for memory devices in accordance with a number of embodiments of the present disclosure. At block662, the method660can include determining, by a controller, an aggregate amount of bandwidth used in execution of one or more applications. The controller and applications can be analogous to the controller110and the applications116discussed in connection withFIG. 1herein.

At block664, the method660can include determining, by the controller, channels between the controller and one or more memory devices used to access data as part of an execution of the applications. The channels can be analogous to the channels114ofFIG. 1. The amount of bandwidth determined by the controller can be a front end bandwidth demand (e.g., the front end bandwidth demand318ofFIG. 3) which can be an aggregate of the amount of bandwidth used by the channels to provide data to the applications from the memory device during execution of the applications.

At block666, the method660can include disabling one or more of the channels based at least in part on the aggregate amount of bandwidth used in execution of the plurality of applications. The controller may selectively disable channels that allow data access between the memory devices and the applications. The enabled channels may have the capacity to provide data to more than one application, as such, the controller may consolidate the provisioning of data from multiple applications to a portion of channels and selectively disable a sub-set (e.g., the sub-set322ofFIG. 3) of channels.

In some embodiments, the method660can include the controller determining that a new application has been executed by the host and is requesting data from a memory device coupled via a back end channel. In such embodiments, the method660can include determining a new aggregate amount of bandwidth used by the applications (including the newly connected application). The controller can selectively re-enable at least one of the sub-set of channels that had been previously disabled to accommodate the new aggregated amount of bandwidth needed to execute the applications. The method660can include the controller managing the channels between the controller and the one or more memory devices based at least in part on the new aggregate amount of bandwidth.

In some embodiments, the method660can include receiving, by the controller, signaling that indicates a temperature increase in a memory device coupled to the controller corresponding to the execution of the additional application and/or determining, by the controller, a new aggregate amount of bandwidth used to execute the plurality of applications based at least in part on the signaling. In response to the alert, the method660can further include selectively disabling another portion of channels by the controller.

FIG. 7is another flow diagram representing another example method770for channel architecture for memory devices in accordance with a number of embodiments of the present disclosure. At block772, the method770can include determining, by a controller, that a channel coupling the controller to a memory device is disabled. The controller can be analogous to the controller110discussed in connection withFIG. 1, herein. A disabled channel may be coupled to the controller and the memory device but not usable for transmission of data from the memory device to an application (e.g., the application116ofFIG. 1). A disabled channel may be utilizing a small amount of power while an enabled channel may draw a comparatively large amount of power.

At block774, the method770, can include identifying, by the controller, applications using the channels to access data stored by the memory device. The applications can be analogous to the applications116discussed in connection withFIG. 1, herein. The identified channels may be a portion of channels that are enabled to transmit data to the applications such that the applications may be executed on a host (e.g., the host102ofFIG. 1) coupled to the controller. As described above, the enabled channels may be using an amount of power from the memory system (e.g., the memory system104ofFIG. 1).

At block776, the method770, can include determining, by the controller, an aggregate amount of bandwidth used in execution of the applications. The aggregate amount of bandwidth can include the amount of bandwidth used by each application to execute using data provided via each channel from the memory device to its respective application. In some embodiments, there can be more than one application using each channel. The aggregate amount of bandwidth can be determined by the controller and be referred to as a front end bandwidth demand (e.g., the front end bandwidth demand318ofFIG. 3). The aggregate amount of bandwidth can be determined periodically, and/or responsive to an alert (e.g., temperature alert, etc.), an indication (e.g., that an application is active and/or inactive, added and/or removed from communication with the controller, etc.). In some embodiments, the method770can include, determining, by the controller an increase in the aggregate amount of bandwidth used in the execution of the of applications. The increase in aggregate bandwidth can correspond to at least one application exhibiting an increased bandwidth requirement. Embodiments are not so limited, however, and in some embodiments, the controller can also detect a decrease in bandwidth (e.g., a decrease in aggregate amount of bandwidth used).

In some embodiments, the method770can include determining a decrease in the aggregate amount of bandwidth used in execution of the applications and associate each application to respective channels. Further, the controller can disable a portion of the channels based in part on a bandwidth requirement of the applications. Said differently, the controller can determine that more channels are enabled than are necessary to accommodate the bandwidth requirement (e.g., the front end bandwidth demand) of the applications. As such, the controller can selectively disable a portion (e.g., one or more) of the enabled channels to save power, thereby reducing a temperature of the memory device. The controller can transfer the applications that were previously accessing data via the newly disabled channels to enabled channels (e.g., consolidation). This channel consolidation can be accomplished in an independent manner where disabling one or more channels of the plurality of channels can include (e.g., disabling the portion of the channels) refrains from altering the operation of remaining enabled channels.

At block778, the method770, can include comparing, by the controller, the aggregate amount of bandwidth used in the execution of the applications and a quantity of channels coupling the controller to the memory device. In some embodiments, the controller can compare the applications accessing data to the quantity of enabled channels to determine if some channels may be disabled to save resources. In other embodiments, the controller can compare the applications accessing data to the quantity of enabled applications to determine if there are enough channels enabled to provide data efficiently to the applications.

At block780, the method770, can include enabling, by the controller, a disabled channel based at least in part on the comparison. To avoid unwanted latency in the execution of applications the controller may enable channels that had been previously disabled to increase the access of data from the memory devices. The enabling of previously disabled channels provides additional connection to the memory device for the applications to access data stored by the memory device.