Method of determining a data rate and apparatus therefor

A data rate determination apparatus includes an edge detection and clock generation circuit for receiving an input bit stream. The edge detection and clock generation circuit generates a pulse for each edge detected in the input bit stream. The pulses are passed to a programmable re-triggerable monostable multivibrator circuit coupled to a binary counter, which counts how many pulses are received within a time period determined by the number of pulses received at a rate higher than a predetermined rate. The binary counter is coupled to a Gray code counter coupled to a processing unit. The processing unit uses different counts that are accumulated over different sampling periods with different predetermined rates to establish statistical data, which can be compared to known data for different data rate standards or formats.

RELATED APPLICATIONS

The present application is based on, and claims priority from GB Application Number 0400134.3, filed Jan. 6, 2004, the disclosure of which is hereby incorporated by reference herein in its entirety

FIELD OF INVENTION

The present invention related to a method of determining a rate of a data signal, for example, of the type corresponding to an optical data signal for communicating data in an optical communications network. The present invention also relates to an apparatus for determining the rate of the data signal.

BACKGROUND OF INVENTION

In the field of optical communications, optoelectronic modules typically comprise a transmitter and a receiver module. Overall, an optoelectronic module is currently designed to provide optimum performance at a single data rate, for example, 2.5 Gbps. In this particular context, optimal performance is considered to be configuration of operating characteristics of the receiver module to produce a longest achievable transmission distance at the single data rate. However, such optoelectronic modules are also capable of providing sub-optimal performance at other data rates, for example 1.25 Gbps. It is possible to optimise performance of the receiver module for the other data rates in order to provide a longest possible transmission distance for each data rate desired.

In providing the possibility of operating the optoelectronic module at different data rates, a need to determine the data rate of received signals follows. In the context of the OSI communications model, known data rate sensing techniques are typically carried out at a higher level than the physical level by detecting packets or bytes containing balanced data. However, such techniques require the use of a considerable quantity of additional circuitry running at the data rate to be identified, and almost inevitably result in unacceptably high power demands and design complexity. Additionally, such detection techniques are usually dedicated to a particular data format and so modification of the detection technique is required for different data formats, for example Synchronous Optical NETwork (SONET), Ethernet or Fibre Channel (FC) system signals, communicated through an optical communications network employing multi-data rate optoelectronic modules.

As an alternative to automatic data rate recognition, the data rate at which the receiver module operates can be set manually from an external source, for example via a hardware connector Input/Output (I/O) line or a software register or memory address. In many known systems the host, which is the source of the data signal, identifies the data rate and transmits that information to the receiver module, at which operation is to take place. For example, the host could extract the datarate from information coded at a higher level in the data packets—such as particular pre agreed bit sequences, otherwise known as a training sequence. Alternatively both ends of a link could start-up in the lowest data rate mode, establish a link and then have an agreed protocol to test the link at higher and higher rates until the maximum usable rate is identified. All these type of systems require the host to tell the receiver module what rate to run at, so the host is the controlling party, not the receiver module.

SUMMARY OF INVENTION

Accordingly, in a first aspect, the present invention provides a method of determining a data rate of a bit stream, the method comprising the steps of receiving the bit stream, and processing at least part of the bit stream to determine the data rate of the bit stream; the processing of the at least part of the bit stream comprises the steps of decimating the at least part of the bit stream, generating statistical data relating to the decimated at least part of the bit stream, and analysing the statistical data to determine the data rate of the bit stream.

The step of decimating the at least part of the bit stream may comprise counting edges of the at least part of the bit stream.

The step of decimating the at least part of the bit stream may comprise integration of the at least part of the bit stream. Alternatively, the step of decimating the at least part of the bit stream may comprise low-pass filtering the at least part of the bit stream.

The step of generating statistical data may comprise the step of calculating frequencies of occurrence of data edges within a first predetermined period of time. The step of decimating the at least part of the bit stream may comprise counting edges in the at least part of the bit stream over a second period of time, counting the edges in the at least part of the bit stream over the first period of time, the first period of time being shorter than and within the second period of time, and determining a proportion of successive edges of the at least part of the bit stream occurring within the first period of time.

The method may further comprise the step of dynamically modifying the first period of time. Gray code may be employed to count the edges.

The step of decimating the at least part of the bit stream may comprise the steps of decimating at least a first part of the bit stream using a first decimation parameter, and decimating at least a second part of the bit stream using a second decimation parameter.

The first and second decimation parameters may determine different periods of time over which the bit stream is decimated.

According to a second aspect, the invention provides a measurement apparatus for measuring a data rate of a bit stream comprising a receiver for receiving the bit stream, and a processing unit arranged to process at least part of the bit stream to determine the data rate of the bit stream, a data decimation unit for decimating the at least part of the bit stream, and the processing unit being further arranged to generate statistical data relating to the at least part of the bit stream decimated by the data decimation unit, and to analyse the statistical data.

Preferably, the processing unit is arranged to determine the data rate of the bit stream based on the analysis thereby of the statistical data.

The data decimation unit may comprise a monostable multivibrator coupled to a counter so as to count, when in use, edges of the at least part of the bit stream.

The counter may be clocked, when in use, by the at least part of the bit stream.

The data decimation unit may comprise an integrator for integrating the at least part of the bit stream with respect to time.

The data decimation unit may alternatively comprise a low-pass filter for filtering the at least part of the bit stream.

The processing unit may be further arranged to calculate frequencies of occurrence of data edges within a first predetermined period of time.

The decimation unit may be arranged to count edges in the at least part of the bit stream over a second period of time, and count the edges in the at least part of the bit stream over the first period of time, the first period of time being shorter than and within the second period of time; and determine a proportion of successive edges of the at least part of the bit stream occurring within the first period of time.

The processing unit may be further arranged to dynamically modify the first period of time.

The apparatus may further comprise a Gray code counter for counting the edges.

It is thus possible to provide a method of determining a data rate and a method therefore that requires minimal use of additional high-speed, power hungry, expensive circuitry. Additionally, external intervention to set the data rate is avoided and knowledge of the format of the data being transmitted is not required.

DETAILED DESCRIPTION OF THE DRAWING

Throughout the following description, identical reference numerals will be used to identify like parts.

Referring to the figure, a data rate determination apparatus100comprises an edge detection and clock generation circuit102comprising an input terminal104for receiving a bit stream106. The input terminal104is coupled to a first input terminal108of an Exclusive OR (XOR) logic gate110, and a first terminal of a resistor112. A second terminal of the resistor112is coupled to a first terminal of a first capacitor114and a second input terminal116of the XOR logic gate110. A second terminal of the first capacitor is coupled to ground potential118.

An output terminal of the XOR logic gate110constitutes an output terminal120of the edge detection and clock generation circuit102and is coupled to an input terminal122of a programmable re-triggerable monostable multivibrator circuit124. The monostable multivibrator circuit124comprises an n-channel field effect transistor (FET)126having a gate terminal coupled to the input terminal122of the programmable re-triggerable monostable multivibrator circuit124. A drain terminal of the FET126is coupled to a voltage supply rail128, and a source terminal of the FET126is coupled to a first terminal of a variable resistor (or a digital potentiometer)130and a first terminal of a second capacitor132, as well as an input terminal134of a buffer136. A second terminal of the variable resistor130and a second terminal of the second capacitor132are coupled to ground potential118. An output terminal of the buffer136constitutes an output terminal138of the programmable re-triggerable monostable multivibrator circuit124.

The output terminal138of programmable re-triggerable monostable multivibrator circuit124is coupled to a count-up/hold terminal140of a binary counter142. The binary counter142comprises a carry-out terminal144and a clocking input terminal146, the clocking input terminal146being coupled to the output terminal120of the edge detection and clock generation circuit102.

The carry-out terminal144is coupled to a carry-in terminal148of a Gray code counter150. The Gray code counter150comprises a databus output152and a clocking input terminal154, the clocking input terminal154being coupled to the output terminal120of the edge detection and clock generation circuit102.

The databus output152is coupled to a first databus input156of a processing unit158, such as a microcontroller, the processing unit158having a databus output160.

In operation, the bit stream106is received at the first input terminal104and the edge detection and clock generation circuit102generates a pulse in response to each edge (both rising and falling) of the bit stream106. The bit stream106is input to the first input terminal108of the XOR gate and is delayed slightly by the RC circuit formed by the resistor112and capacitor114before passing to the second input terminal116of the XOR gate. Consequently, the XOR gate receives each edge of the bit stream106at both input terminals, but with the edges at the second input terminal being slightly delayed as compared to the first input terminal. Since the property of the XOR gate is that it provides a high whenever its two inputs are different, it generates a pulse whenever an edge occurs in the input bit stream to generate a stream of pulses (one for each edge of the input bit stream.

This stream of pulses from the edge detection and clock generation circuit102is used to trigger the monostable multivibrator circuit124having a predetermined hold time controlled by the variable resistor130and the second capacitor132. Thus, in response to a pulse at the input terminal122, the FET126causes a signal to appear on the input terminal134of buffer136. In response to the FET126being switched off, the signal decays via the resistor130in a time set by the values of the resistor130and the capacitor132, as is well known. The buffer136essentially comprises a comparator that compares the signal level at the input terminal134with a preset threshold and provides a digital output signal indicating whether the signal is above or below the threshold. Therefore, in response to a first pulse being received at the input terminal122of monostable multivibrator circuit124, the FET126is switched on to produce a signal at the input terminal134of the buffer136, thereby producing a leading edge of the stretched pulse at the output terminal138of the monostable multivibrator circuit124. In response to a following pulse arriving at the input terminal122of the monostable multivibrator circuit124before the signal level at the input terminal134of buffer136decays below the threshold, the signal is “refreshed” and the stretched pulse at the output terminal138is maintained and “stretched” further. On the other hand, in response to the signal level at the input terminal134of buffer136decaying below the threshold before another pulse is received at the input terminal122of the monostable multivibrator circuit124, the stretched pulse at the output terminal138is terminated. Thus, the length of the stretched pulse is dependent on how many pulses arrive in the stream of pulses at the input terminal122of the monostable multivibrator circuit124without the signal level at the input terminal134of the buffer136having decayed below the threshold, the decay rate being determined by the values of the variable resistor130and the capacitor132.

The stretched pulse generated by the monostable multivibrator circuit124is applied to the count-up/hold terminal140of the binary counter142. Since the binary counter142is clocked at the rate of the output of the edge detection and clock generation circuit, if a bit edge occurs in the stream of pulses output from the edge detection and clock generation circuit102while a stretched pulse is applied to the binary counter142, the binary counter142is incremented by one. In other words, if the next edge is detected before the end of the stretched pulse, the counter is incremented because the stretched pulse enables the counter while it is high, and the counter counts every new edge occurring within the stretched pulse.

Each time a carry-out bit is generated by the binary counter142, the Gray code counter150is incremented by unity by changing only a single bit, thereby reducing reading errors that can occur between the Gray code counter150and the processing unit158. Consequently, the processing unit158is provided with a count of the number of edges in the bit stream106that have occurred over a first predetermined period of time controlled by the values of the variable resistor130and the capacitor132. The input bit stream106has therefore been decimated in that that the processing unit is provided with an indication of the number of bits in the bit stream that are closer together (have a data rate higher) than a predetermined rate (set by the predetermined period of time).

If, then, the predetermined rate (set by the predetermined period of time) is changed to a second, different, rate (by a second, different, predetermined period of time), the processing unit will be provided with an indication of the number of bits in the bit stream that are closer together (have a data rate higher) than that second predetermined rate. The two indications of data rates can then be used by the processing unit to generate statistical data, which can be used to try to determine the data rate of the signal based on predetermined knowledge of particular possible data rates for different standards or systems.

In order to provide the second predetermined period of time, the variable resistor can be controlled by the processing unit so as to change the RC characteristics of the monostable multivibrator circuit124and therefore the decay rate.

The processing unit158is therefore provided with a first count of a number of successive edges of the bit stream106occurring within the first predetermined period of time, and a second count of a number of successive edges of the bit stream106occurring during the second predetermined period of time. Thus, as the stretch pulse length is changed the number of edge pairs occurring closer than the stretch length varies. Recording or plotting the number of close edge pairs in a unit time interval against the stretch length gives a characteristic signature for the data on the link, which can be compared with known characteristics of different standards or formats. This gives a more powerful overview of the data than simply counting only the total number of data edges in a given time. The shape of the data can show not only the average number of edges per second, but also the length of a databit. As the stretched pulse is made narrower than a databit, a clean signal, with little noise, has a distinctive cliff edge on the data statistics, as the count value rapidly falls to zero. How rapidly it falls to zero at this cliff edge gives an indication of the noise and jitter on the link. All this is information that a straight edge density measurement can not provide alone. However, by setting the stretch to infinity (always on) the same circuit can also issue the straight edge density measurement—but rather than being an isolated measurement point it becomes, in this system, simply the limiting case of the more general edge spacing measurement. Hence such statistics indicate a great deal about the signal on the link. The advantage of this circuit is that all this information can be easily harvested by a microcontroller running at a system clock rate thousands of times slower than the data stream it is monitoring.

Thus, this circuit provides an indication of how many edges in a given time occur at spacings of less then the stretch length from the previous edge. If the same data edges are also tested against the circuit with a longer stretched pulse length, there is a higher counter value in the same elapsed time. Provided the data is truly random, one circuit can be used and the test repeated for different stretch lengths, being careful to count over the same time interval. However, if answers are required more quickly, or the data is not always random, it may be preferable to have one or more copies of the circuit set to different time delays.

Therefore, instead of having a variable resistor130, the resistor can be fixed and a parallel circuit is provided comprising a second, similar, edge detection and clock generation circuit coupled to a second, similar, monostable multivibrator circuit. The monostable multivibrator circuit is coupled to a second, similar, binary counter and a second, similar, Gray code counter. The Gray code counter is coupled to a second databus input of the processing unit158. In this case, the decay rate of the monostable multivibrator circuit is changed by changing the value of one or both of the resistor and/or capacitor.

If desired, a still further parallel circuit set to a still different decay rate could be provided.

In an alternative embodiment, the processing unit158averages the edge count over a large number of bits and so a normal binary counter can be provided for the 8 least significant bits (LSBs) and a Gray code counter for the 8 most significant bits (MSBs). In such an arrangement, the processing unit can, if desirable for computational efficiency, simply read the 8 MSBs and disregard the 8, non-Gray-Code, LSBs.

Thus, in the described embodiment, a data rate determination apparatus100includes an edge detection and clock generation circuit102for receiving an input bit stream106. The edge detection and clock generation circuit102generates a pulse for each edge detected in the input bit stream. The pulses are passed to a programmable re-triggerable monostable multivibrator circuit124coupled to a binary counter142, which counts how many pulses are received within a time period determined by the number of pulses received at a rate higher than a predetermined rate. The binary counter142is coupled to a Gray code counter150coupled to a processing unit158. By performing the count over different sampling periods with different predetermined rates, the counts can be used by the processing unit to establish statistical data, which can be compared to known data for different data rate standards or formats.

It will be appreciated that although only one particular embodiment of the invention has been described in detail, various modifications and improvements can be made by a person skilled in the art without departing from the scope of the present invention.