Memory device and memory module including same

A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0063542 filed on May 27, 2020 in the Korean Intellectual Property Office, the subject matter of which is hereby incorporated by reference.

BACKGROUND

Embodiments of the inventive concept relate generally to semiconductor memory devices, and more particularly, to memory systems and memory devices providing an improved error correction function. Embodiments of the inventive concept relate to memory modules including at least one memory device providing an improved error correction function.

Memory devices may be variously configured to store data received from an external host device, and thereafter, provide the stored data in response to a request received from the external host device. Error(s) may occur when data is programmed (or written) to the memory device, while the data is stored in the memory device, and/or when the data is retrieved (or read) from the memory device.

One or more error(s) occurring in data may cause a system error or processing failure in the external host device using the data. To prevent such failures, the external host device may include a data integrity function capable of detecting and/or correcting error(s).

As the data integrity function provided by the external host device improves in its ability to detect and/or correct error(s), the probability of a system error or processing failure decreases. However, improved (or emerging) data integrity functions (e.g., data detection and/or correction functions) demand considerable memory system resources.

SUMMARY

Embodiments of the inventive concept provide a memory device having a structure supporting a function for correcting an error and, a memory module having an improved error correction function or capable of reducing the amount of resource necessary for error correction by including the memory device.

According to an embodiment, a memory device includes banks and a peripheral circuit configured to receive a command and an address from an external host device, transfer the command and the address to the banks, and communicate data between the external host device and the banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

According to an embodiment, a memory module includes; first memory devices, a second memory device, a driver configured to receive a command and an address from an external host device, and transfer the command and the address to the first memory devices and the second memory device, and a power management circuit configured to receive an external power signal from the external host device, generate an internal power signal from the external power signal, and provide the internal power signal to at least one of the first memory devices, the second memory device and the driver. Each of the first memory devices and the second memory device is configured to communicate data with the external host device in accordance with a burst length, and each of the first memory devices and the second memory device respectively provides two error-independent coverages with regard to the burst length.

According to an embodiment, a memory device includes a memory module includes; eight (8) first memory devices, a second memory device, a driver configured to receive a command and an address from an external host device, and transfer the command and the address to the first memory devices and the second memory device, and a power management circuit configured to receive an external power signal from the external host device, generate an internal power signal from the external power signal, and provide the internal power signal to at least one of the first memory devices, the second memory device and the driver. Each of the first memory devices and the second memory device is configured to communicate data with the external host device in accordance with a burst length. Each of the first memory devices and the second memory device provides at least two error-independent coverages with regard to the burst length, and the second memory device is configured to store cyclic redundancy code and parity for correcting an error in data stored in at least one of the eight (8) first memory devices.

DETAILED DESCRIPTION

Below, embodiments of the inventive concept may be described in detail and clearly to such an extent that an ordinary one in the art easily implements the inventive concept.

Figure (FIG.)1is a block diagram illustrating a computing system1000according to embodiments of the inventive concept. Referring toFIG. 1, the computing system1000may include a memory module1100and an external host device1200.

The memory module1100may include a driver1110, first memory devices1121to1125, second memory devices1126to1130, a driver connector1150, first memory connectors1161to1165, second memory connectors1166to1170, a power management circuit1180and a power connector1190.

For example, the driver1110may receive various unidirectional signal(s) from the external host device1200, exchange various bidirectional signal(s) with the external host device1200, and/or transmit various unidirectional signal(s) to the external host device1200.

Additionally, the driver1110may transmit command signal(s) CMD and/or address(es) ADDR to the first memory devices1121to1125through a first channel CH1and/or transmit control signal(s) CTRL received from the external host device1200to the first memory devices1121to1125through the first channel CH1.

The driver1110may also transmit control signals received from the first memory devices1121to1125through the first channel CH1to the external host device1200. Here, the control signals CTRL communicated by the driver1110with the external host device1200may the same, partially the same, or different from the control signals communicated by the driver1110with the first memory devices1121to1125.

The foregoing description related to the driver1110, the first memory devices1121to1125and the first channel CH1, may be similarly applied to the driver1110, the second memory devices1126to1130and a second channel CH2.

In some embodiments, the driver1110may be a register clock driver (RCD) defined in accordance with one or more technical standard(s) associated with Dual In-line Memory Module(s) (DIMMs), such as the dual data rate fifth-generation synchronous dynamic random access memory (DDR5 SRAM) DIMM.

The first memory devices1121to1125may communicate with the external host device1200through the first memory connectors1161to1165. For example, the first memory devices1121to1125may communicate data signals DQ and data strobe signals DQS with the external host device1200. (See, e.g.,FIG. 2).

The second memory devices1126to1130may communicate with the external host device1200through the second memory connectors1166to1170. For example, the second memory devices1126to1130may communicate the data signals DQ and the data strobe signals DQS with the external host device1200.

In some embodiments, the first memory devices1121to1125and the second memory devices1126to1130may be a DDR5 SDRAM. Accordingly, the first memory devices1121to1125and the second memory devices1126to1130may communicate with the external host device1200using a protocol defined in accordance with one or more technical standard(s) associated with DIMMs, such as the DDR5 SDRAM DIMM.

Depending on a request of the external host device1200, the first memory devices1121to1125and the second memory devices1126to1130may simultaneously (e.g., at least partially overlapping in time) receive the data signals DQ and may write the received data signals DQ. Depending on a request of the external host device1200, the first memory devices1121to1125and the second memory devices1126to1130may simultaneously read the data signals DQ and may write the read data signals DQ.

The first memory devices1121to1125and the second memory devices1126to1130may sequentially receive, or may sequentially transmit the data signals DQ in accordance with a defined burst length BL. For example, according to standard(s) associated with the DDR5 SDRAM DIMM, a burst length BL of 16 may be used.

In some embodiments, the number of data signals DQ of the DDR5 SDRAM may decrease, as compared with legacy memory device(s)—e.g., the DDR4 SDRAM and older DDR memory devices. In contrast, the external host device1200may be configured to communicate the data signals DQ of 64 bytes with one memory device. To support compatibility of 64 bytes, the first memory devices1121to1125and the second memory devices1126to1130may be configured to have the burst length BL of 16.

That is, in response to one write request or one read request received from the external host device1200, the first memory devices1121to1125and the second memory devices1126to1130may continuously receive the data signals DQ over16time periods or may continuously transmit the data signals DQ over16time periods. In some embodiments, each of the first memory devices1121to1125and each of the second memory devices1126to1130may be an (×8) memory device capable of communicating eight (8) data signals DQ with the external host device1200.

The power management circuit1180may receive one or more external power signal(s) from the external host device1200through the power connector1190. The power management circuit1180may then generate one or more internal power signal(s) from the one or more external power signal(s), and variously provide the one or more internal power signal(s) to the driver1110, the first memory devices1121to1125and/or the second memory devices1126to1130.

In some embodiments, the power management circuit1180may be a power management integrated circuit (PMIC) designed in accordance with one or more technical standard(s) associated with the DDR5 SDRAM DIMM. In the illustrated example ofFIG. 1, the memory module1100is assumed to be a registered DIMM (RDIMM). Alternately, however, the memory module1100may be an unbuffered DIMM (UDIMM), a load reduced DIMM (LRDIMM), or a fully buffered DIMM (FBDIMM). In this regard, those skilled in the art will recognize that differently configured memory modules may vary in constituent components and functions, as compared with standard-complying DIMMs (e.g., a RDIMM).

The external host device1200may include a processor1210, a power supply1220, a host power management circuit1230, and a device driver1240. The processor1210may include a general-purpose processor such as a central processing unit (CPU), and a special purpose processor such as an application processor (AP), a graphic processing unit (GPU), a neuromorphic processor (NP), or a neuromorphic processor.

The processor1210may include a memory controller1211. The memory controller1211may control the memory module1100and may communicate with the memory module1100. The communication with the external host device1200described with reference to the memory module1100may be performed by the memory controller1211.

The memory controller1211may include an error correction circuit (ECC)1212. The ECC1212may be configured to generate an error correction code. When the memory controller1211writes data DT into the memory module1100, the memory controller1211may generate the error correction code for error correction from the data DT.

The memory controller1211may write the data DT to the first memory devices1121to1124(hereinafter, “first memory devices for data”) being a part of the first memory devices1121to1125, and may write the error correction code to the first memory device1125(hereinafter, “first memory device for ECC”) being the remaining memory device of the first memory devices1121to1125.

The memory controller1211may write the data DT to the second memory devices1127to1130(hereinafter, “second memory devices for data”) being a part of the second memory devices1126to1130, and may write the error correction code to the second memory device1126(hereinafter, “second memory device for ECC”) being the remaining memory device of the second memory devices1126to1130.

In some embodiments, the error correction code may include a cyclic redundancy code “C” for detecting an error, and parity information “P” (hereafter, “parity”) for correcting the detected error. (See, e.g.,FIG. 7). The memory controller1211may read the data DT and the error correction code from the memory module1100and perform error detection and correction functions.

The power supply1220of the external host device1200may generate power required to variously drive the computing system1000. The power may be provided to the host power management circuit1230. The host power management circuit1230may generate an internal power necessary to drive the external host device1200. The host power management circuit1230may be a PMIC that is designed and manufactured depending on a system demand of the external host device1200. The host power management circuit1230may supply the internal power to the processor1210and components of the external host device1200.

The device driver1240may control various additional devices under control of the processor1210. For example, the device driver1240may be connected with various devices such as a storage device, a modem, and a user interface device and may arbitrate the communication between the various devices and the processor1210.

Here, the number of first memory devices1121to1125and the number of second memory devices1126to1130may vary by design and are not limited to only the illustrated examples ofFIG. 1.

FIG. 2is a block diagram further illustrating in one example a memory device100according to embodiments of the inventive concept. Here, the exemplary memory device100may correspond to one of the first memory devices1121to1125and/or one of the second memory devices1126to1130ofFIG. 1. In some embodiments, the first memory devices1121to1125and the second memory devices1126to1130may have the same structure and/or configuration, and may perform one or more of the same operation(s).

Referring toFIGS. 1 and 2, the memory device100may include a first bank group BG1and a second bank group BG2, wherein the first bank group BG1includes first to fourth banks BANK1to BANK4, and the second bank group BG2includes first to fourth banks BANK1to BANK4. Here, in some embodiments, each memory bank group and each bank may respectively have the same structure and may perform the same operation(s).

Each of the first to fourth banks BANK1to BANK4may include a plurality of memory cells, wherein the memory cells may be used to store the data DT and/or the error correction code communicated with the external host device1200.

The memory device100ofFIG. 2further includes a peripheral circuit110capable of variously communicating data signal(s) DQ and DQS, control signal(s) CTRL, address(es) ADDR, and/or clock signal(s) CK with the external host device1200. In some embodiments, the peripheral circuit110may select a bank according to a received address ADDR from among the first to fourth banks BANK1to BANK4of the first bank group BG1and/or the second bank group BG2.

The peripheral circuit110may then control the selected bank such that an operation indicated by the received command CMD (e.g., a write operation or a read operation) is performed on memory cells indicated by the received address ADDR from among the memory cells of the selected bank. The peripheral circuit110may then communicate data signals DQ and/or data strobe signals DQS with the external host device1200, wherein the data strobe signals DQS may be used to control latch timing for the data signals DQ.

The peripheral circuit110may include an input and output circuit120configured to exchange the data signals DQ and the data strobe signals DQS with the external host device1200. The peripheral circuit110may further include control logic130configured to control the selected bank in response to the command CMD, the address ADDR, the clock signal CK, and the control signals CTRL.

The number of bank groups, as well as the number of banks within each bank group may vary with design and is not limited to only the illustrated example ofFIG. 2.

FIG. 3is a block diagram further illustrating in one example a bank200according to embodiments of the inventive concept. Here, the bank200may correspond to be one of the first to fourth banks BANK1to BANK4of the first bank group BG1and/or the second bank group BG2ofFIG. 2.

Referring toFIGS. 1, 2 and 3, the bank200may include a memory cell array210, a row decoder220, a first bit line sense amplifier (BLSA)240, a second bit line sense amplifier250and a column decoder260.

The memory cell array210may include memory cells arranged along a row direction and a column direction. The memory cell array210may include 0-th to 15-th regions R0to R15, wherein, collectively, the 0-th to 15-th regions, R0to R15may correspond (e.g.,) to a burst length BL of 16. However, assuming a burst length BL of 8, the number of regions of the memory cell array210may be 8, and assuming a burst length BL of 32, the number of regions of the memory cell array210may be 32, as examples.

The row decoder220may be connected with memory cells in rows through word lines WL1to WLn (where ‘n’ is a positive integer). The row decoder220may receive a row address RA of the address ADDR and may select one of the 1-st to n-th word lines WL1to WLn in response to the row address RA. For example, the row decoder220may apply a voltage for activation (e.g., a positive voltage) to the selected word line.

The first bit line sense amplifier240and the second bit line sense amplifier250may be connected with memory cells in columns through bit lines. Bit lines connected with the first bit line sense amplifier240may be different from bit lines connected with the second bit line sense amplifier250. For example, the first bit line sense amplifier240may be connected with even-numbered (or odd-numbered) bit lines along the row direction, and the second bit line sense amplifier250may be connected with odd-numbered (or even-numbered) bit lines along the row direction.

The first bit line sense amplifier240and the second bit line sense amplifier250may apply voltages to the bit lines or may sense voltages of the bit lines. By adjusting or sensing voltages of the bit lines, the first bit line sense amplifier240and the second bit line sense amplifier250may perform the write operation or the read operation on memory cells of the selected row.

The column decoder260may receive a column address CA of the address ADDR. The column decoder260may electrically connect a part of the bit lines with the peripheral circuit110in response to the column address CA. In some embodiments, the column decoder260may output the data DT or the error correction code ECC corresponding to the burst length BL of 16 by sequentially selecting the 0-th to 15-th regions R0to R15and outputting data read from memory cells of the sequentially selected regions.

For example, the memory cell array210ofFIG. 3is assumed to include the 0-th to 15-th regions R0to R15. However, the memory cell array210may include a plurality of sub-arrays, and each sub-array may include the 0-th to 15-th regions R0to R15. During the write operation or the read operation, one of a plurality of sub-arrays may be selected, and the write operation or the read operation may be performed in the 0-th to 15-th regions R0to R15in the selected sub-array in units of the burst length BL.

In the illustrated embodiment ofFIG. 3, it is assumed that the column decoder260is included in the bank200. However, the column decoder260may be included in the peripheral circuit110, not the bank200. In the case where the column decoder260is included in the peripheral circuit110, the column decoder260may control an input or an output of the data DT or the error correction code ECC associated with one bank selected from the first to fourth banks BANK1to BANK4of the first bank group BG1and the second bank group BG2. That is, the column decoder260may be applied in common to the first to fourth banks BANK1to BANK4of the first bank group BG1and the second bank group BG2.

FIG. 4is a conceptual diagram illustrating, in relevant portion, the memory cell array210ofFIG. 3. Referring toFIGS. 1, 2, 3 and 4, the memory cell array210may include memory cells MC (marked as small white circles). The memory cells MC may be connected with sub-word line drivers SD through sub-word lines SWL. The sub-word line drivers SD may be connected with word lines, for example, the third to sixth word lines WL3to WL6.

The 0-th to 15-th regions R0to R15may respectively correspond to timing periods associated with a burst length of 16. That is, memory cells of the 0-th region R0may correspond to 0-th data communicated in a 0-th burst length BL0of the 16 burst lengths BL, memory cells of the 1-st first region R1may correspond to 1-st data communicated in a 1-st burst length BL1of the 16 burst lengths BL, etc. Accordingly, the 0-th to 15-th regions R0to R15may be said to correspond to the 0-th to 15-th burst lengths BL0to BL15, respectively.

In the 0-th region R0, the memory cells MC corresponding to the fourth word line WL4and the sixth word line WL6may be connected with sub-word lines placed on the right of the corresponding sub-word line drivers SD. The memory cells MC corresponding to the third word line WL3and the fifth word line WL5may be connected with sub-word lines placed on the left of the corresponding sub-word line drivers SD.

During the write operation or the read operation, at least one of the sub-word line drivers SD (or sub-word lines SWL) connected with a selected word line may also be selected. The write operation or the read operation may be performed on the memory cells MC connected with sub-word lines SWL connected with at least one selected sub-word line driver SD or on the memory cells MC connected with at least one selected sub-word line SWL.

In some embodiments, decoding lines for selecting at least one of sub-word line drivers SD connected with a selected word line, or at least one of sub-word lines SWL may be further provided. The decoding lines may be controlled by the row decoder220in response to the row address RA. Hereafter, the decoding lines will be omitted from the drawings for clarity.

Thus, the sub-word line drivers SD connected with the third to sixth word lines WL3to SW6may be disposed, in turn, on the left and the right of the 0-th region R0along the column direction. Likewise, in each of the 1-st to 15-th regions R1to R15, the sub-word line drivers SD may be disposed, in turn, on the left and the right of the corresponding region along the column direction.

In each of the 0-th to 15-th regions R0to R15, the first bit line sense amplifier240may be connected with even-numbered bit lines. In each of the 0-th to 15-th regions R0to R15, the second bit line sense amplifier250may be connected with odd-numbered bit lines.

In some embodiments, eight (8) memory cells MC may be connected with one sub-word line SWL. Memory cells MC connected with one sub-word line SWL may be simultaneously written to, or simultaneously read from. That is, the memory device100may receive or transmit eight (8) data signals DQ (e.g., eight (8) bits) at a time.

In some embodiments, a plurality of memory cell groups may be connected with one sub-word line SWL. Each of the plurality of memory cell groups may include memory cells MC corresponding to the number of data signals DQ that the memory device100simultaneously receives or transmits (e.g., eight (8) memory cells MC).

During the write operation or the read operation, one of the plurality of memory cell groups connected with one sub-word line SWL may be selected, and the write operation or the read operation may be performed on memory cells of the selected memory cell group.

FIG. 5is a conceptual diagram illustrating an example in which data DT or error correction code ECC is read from the memory cell array210during a read operation. Referring toFIGS. 1 and 5, it is assumed that the word line WL5has been selected.

During (a period of time corresponding to) the 0-th burst length BL0, the data DT or the error correction code ECC may be read from the memory cells MC in the 0-th region R0using the first bit line sense amplifier240and the second bit line sense amplifier250. The data DT or the error correction code ECC thus read may be simultaneously transmitted from the memory device100as the data signals DQ.

Thereafter, during the 1-st to 15-th burst lengths BL1to BL15, the data DT or the error correction code ECC may be respectively read from the first to 15-th regions R1to R15, and the resulting data DT or the error correction code ECC may be simultaneously transmitted from the memory device100as the data signals DQ.

Extending the assumptions described above, for example, the memory device100may transmit eight (8) data signals (e.g., data bits) DQ during sixteen (16) consecutive time periods corresponding to the entire burst length of 16.

The write operation may be similarly performed, except the memory device100receives a sequence of data signals DQ instead of transmitting the sequence of data signals DQ. In this manner, data DT or the error correction code ECC may be written to the memory cells MC.

FIG. 6is a conceptual diagram illustrating an example of a data block that may be used to exchange data between each of the first memory devices for data1121to1124and the second memory devices for data1127to1130and the external host device1200. Referring toFIGS. 1 to 6, it is assume that the memory device1100simultaneously receives or transmits first to eighth data signals DQ1to DQ8.

Thus, the memory device1100may continuously receive or transmit the first to eighth data signals DQ1to DQ8during a number of time periods corresponding to the number of 0-th to 15-th burst lengths BL0to BL15, here again assuming a burst length of 16. Under such assumptions, the data block ofFIG. 6may be understood as a unit in which the memory device100exchanges data DT with the external host device1200, including (e.g.,) 128 bits.

Further, continuing with the previous assumption that the memory module1100includes the four (4) first memory devices for data1121to1124and the four (4) second memory devices for data1127to1130, the memory module1100may exchange data DT with the external host device1200in units of 1024 bits.

FIG. 7is a conceptual diagram illustrating another example of a data block that may be used to exchange data between the first memory device for ECC1125and the second memory device for ECC1126with the external host device1200. The data block (e.g., 128 bits) ofFIG. 6is, here again, assumed as an example. However, in the illustrated example ofFIG. 7, half of the 128 bit data block (e.g., a first half corresponding to the 0-th to 7-th burst lengths BL0to BL7) may be used to communicate cyclic redundancy code “C”. Further, the other half of the 128 bit data block (e.g., a second half corresponding to the 8-th to 15-th burst lengths BL8to BL15) may be used to communicate parity “P”.

In this manner, the first memory device for ECC1125and the second memory device for ECC1126of the memory module1100may communicate the error correction code ECC (including e.g., 256 bits) with the external host device1200.

FIG. 8is a conceptual diagram illustrating an example of five (5) data blocks including four (4) data block of data DT, one-half (½) of a block of cyclic redundancy code “C”, and one-half (½) of a block of parity “P” communicated from the first memory devices1121to1125using the first channel CH1of the memory module1100. Data blocks of the second memory devices1126to1130of the second channel CH2may be the same as those described with reference toFIG. 8, except for the respective locations of data blocks. Thus, referring toFIGS. 1 to 8, the first memory devices1121to1125of the first channel CH1may communicate with the external host device1200in units of four (4) data blocks including the data DT, plus one (1) data block of error correction code ECC including (e.g.,) cyclic redundancy code “C” and parity “P”.

Accordingly, in the foregoing example, data blocks of the first memory devices1121to1125, a ratio of first memory devices for data (e.g.,1121to1124) and first memory device for ECC (e.g.,1125) is 4-to-1. And as a result, a RAS (Reliability, Availability, Serviceability) coverage for the first memory devices1121to1130of the memory module1100ofFIG. 1—assuming x8 memory devices communicating eight (8) data signals DQ1to DQ8—may be understood as a single error, correction double error detection (SECDED) type of device.

FIG. 9is a conceptual diagram illustrating an example in which a data block corresponding to data DT provides two or more error-independent coverages. Referring toFIGS. 1, 2, 3 and 9, the term “coverage”, as used in this context, may be understood as a subset of data blocks, wherein each data block is a unit in which the memory device100exchanges data DT with the external host device1200. For example, the 0-th to 7-th burst lengths BL0to BL7may constitute a first coverage, and the 8-th to 15-th burst lengths BL8to BL15may constitute a second coverage, wherein the first coverage includes first data DT1and the second coverage includes second data DT2.

With this configuration, as an example, an error occurring in the first coverage will not affect the second coverage, and an error occurring in the second coverage will not affect the first coverage. Hence, the first coverage and the second coverage may be said to be “error-independent coverages.” As a result, and again extending the working assumptions above, the memory device100may be said to provide two error-independent coverages with respect to the burst length BL of 16. Those skilled in the art will also understand that more than two error-independent coverages may be provided with respect to burst lengths of arbitrary length in other embodiments of the inventive concept.

Referring again toFIG. 3, the 0-th to 15-th regions R0to R15respectively corresponding to the 0-th to 15-th burst lengths BL0to BL15may be arranged in a row direction. Accordingly, two or more error-independent coverages may correspond to two or more “sections”—independent of each other—with regard to a row-dependent error. Here, the term “section” denotes a subset within the memory cell array210, wherein each section may include two or more regions of the 0-th to 15-th regions R0to R15.

FIG. 10is a conceptual diagram illustrating an example in which an exemplary (e.g., 128 bit) data block including cyclic redundancy code “C” and parity “P” may provide two or more error-independent coverages. Here, the 0-th to 7-th burst lengths BL0to BL7may constitute a first coverage and the 8-th to 15-th burst lengths BL8to BL15may constitute a second coverage.

Referring toFIGS. 1, 2, 3, 9, and 10, data blocks of the first memory devices for data1121to1124may be data blocks for data, and data blocks of the first memory device for ECC1125may be a data block for ECC. When the data blocks for data provide error-independent coverages, the external host device1200may independently perform error correction encoding/decoding on the error-independent coverages.

In this regard, the error correction encoding may generate the cyclic redundancy code “C” and the parity “P” from the data DT during a write operation. And during a read operation, the error correction decoding may detect error(s) in the read data DT using the cyclic redundancy code “C” and correct the detected error(s) using the parity “P”.

As illustrated inFIG. 10, the data block for ECC may include first cyclic redundancy code C1and first parity P1for the first coverage of the data blocks for data, as well as second cyclic redundancy code C2and second parity P2for the second coverage of the data blocks for data.

For example, the data block for ECC of the first channel CH1may include the first cyclic redundancy codes C1, the second cyclic redundancy codes C2, the first parities P1, and the second parities P2corresponding to the data blocks for data of the first channel CH1. The data block for ECC of the second channel CH2may include the first cyclic redundancy codes C1, the second cyclic redundancy codes C2, the first parities P1, and the second parities P2corresponding to the data blocks for data of the second channel CH2.

FIG. 11is a conceptual diagram illustrating another example of data blocks of the first memory devices1121to1125corresponding to one channel (e.g., the first channel CH1) of the memory module1100ofFIGS. 1, 2 and 3. Data blocks of the second memory devices1126to1130corresponding to another channel (e.g., the second channel CH2) may be the same as those described with reference toFIG. 11. except for the respective locations of the data blocks.

Referring toFIGS. 1, 2, 3, 9, 10 and 11, each of data blocks for data belonging to the first memory devices for data1121to1124may include first data DT1and second data DT2for each of first coverages1121ato1124aand second coverages1121bto1124b.

A first coverage1125aof a data block for ECC belonging to the first memory device for ECC1125may include first cyclic redundancy codes C1and second cyclic redundancy codes C2, respectively corresponding to the first data DT1, and second data DT2of the first coverages1121ato1124aand second coverages1121bto1124bof the data blocks for data.

A second coverage1125bof the data block for ECC belonging to the first memory device for ECC1125may include first parities P1and second parities P2respectively corresponding to the first data DT1and the second data DT2of the first coverages1121ato1124aand the second coverages1121bto1124bof the data blocks for data.

The first coverages1121ato1124aand the second coverages1121bto1124bare error-independent, and as a functional result, may be considered as independent, separate and distinct memories. Accordingly, a data range over which the memory controller1211is required to error correction encoding/decoding may effectively decreased.

Accordingly, as the memory controller1211maintains a desired performance level for error detection and/or correction, the amount of correspondingly required cyclic redundancy code and parity may be decreased. For example, when the amount of data of an error-dependent coverage is equal to the total amount of data of two coverages being error-independent of each other, the amount of error correction code required to maintain the same level of error detection and/or correction performance may be halved, since the two coverages are error-independent.

As illustrated inFIG. 11, the amount of cyclic redundancy code and the amount of parity may be the same. (CompareFIG. 8). Accordingly, the performance of error correction of the memory controller1211may be improved. For example, the RAS coverage for error-independent coverages of the memory module1100may be expanded to the single device data correction (SDDC).

As a data block may be implemented with two or more, error-independent coverages, and as memory cells may be divided into two independent sections with regard to the row-dependent error(s), the error correction capability of the memory module1100may be improved. An example of two (2) error-independent coverages and two (2) independent sections has been described above, but those skilled in the art will recognize from the foregoing that embodiments of the inventive concept may include examples having more than two coverages and/or more than two sections. In this regard, as the number of error-independent coverages and/or the number of independent sections increase, the error correction capability of the memory module1100may further improve.

FIG. 12is a conceptual diagram illustrating, in relevant portion, memory cell array supporting error-independent coverages and/or independent sections with regard to row-dependent error(s).

Referring toFIGS. 1, 2, 3 and 12, in the 7-th region R7and the 8-th region R8, respectively corresponding to the seventh burst length BL7and the eighth burst length BL8, the sub-word line drivers SD may be provided independent of each other. That is, the sub-word lines SWL of the 7-th region R7may be driven independent of the sub-word lines SWL of the 8-th region R8.

Referring to the comparative example ofFIG. 4, a memory cell array structure wherein a sub-word line driver is shared between two regions may result in an error associated with a sub-word line driver SD shared by the 7-th region R7and the 8-th region R8causing error(s) in both the 7-th region R7and the 8-th region R8. In contrast, in the memory cell array structure ofFIG. 12, even though an error occurs at one of the sub-word line drivers SD associated with the 0-th to 7-th regions R0to R7, the error will not affect the 8-th to 15-th regions R8to R15. Likewise, an error occurring in one of the sub-word line drivers SD associated with the 8-th to 15-th regions R8to R15will not result in an error affecting the 0-th to 7-th regions R0to R7.

Accordingly, the 0-th to 7-th regions R0to R7and the 8-th to 15-th regions R8to R15are independent sections with regard to a row-dependent error. In other words, the 0-th to 7-th burst lengths BL0to BL7and the 8-th to 15-th burst lengths BL8to BL15of a memory block provide two (2) error-independent coverages.

FIG. 13is a conceptual diagram illustrating an example of a bank300having a structure that supports multiple, error-independent coverages or independent sections with regard to a row-dependent error. Referring toFIGS. 1, 2, and13, the bank300may include a memory cell array310, a first row decoder320, a second row decoder330, a first bit line sense amplifier340, a second bit line sense amplifier350and a column decoder360.

Here, the structure and operation of the bank300may generally be the same as the bank200ofFIG. 3, except that both the first row decoder320and the second row decoder330are provided.

As a result of this structure, the first row decoder320may be connected with 11-th to 1n-th word lines WL11to WL1n, wherein the 11-th to 1n-th word lines WL11to WL1nmay be connected with memory cells of the 0-th to 7-th regions R0to R7. In like manner, the second row decoder330may be connected with 21-th to 2n-th word lines WL21to WL2n, wherein the 21-th to 2n-th word lines WL21to WL2nmay be connected with memory cells of the 8-th to 15-th regions R8to R15.

FIG. 14is a conceptual diagram further illustrating in relevant portion the memory cell array310ofFIG. 13. Referring toFIGS. 1, 2, 13, and 14, (and as indicated by a bold dotted line), the 13-th to 16-th word lines WL13to WL16and the 23-th to 26-th word lines WL23to WL26may be electrically and physically isolated between the 7-th region R7and the 8-th region R8. Accordingly, the sub-word line drivers SD in the 7-th region R7and the 8-th region R8are not shared.

In this regard, the 11-th to 1n-th word lines WL11to WL1n(e.g., a first set of word lines) may pass through a first section including the 0-th to 7-th regions R0to R7, yet may not pass through a second section including the 8-th to 15-th regions R8to R15. Further, the 21-th to 2n-th word lines WL21to WL2n(e.g., a second set of word lines) may pass through the second section including the 8-th to 15-th regions R8to R15, yet may not pass through the first section including the 0-th to 7-th regions R0to R7.

Referring toFIGS. 3, 12, 13 and 14and as a result of the structure of the illustrated embodiments of the inventive concept, an error associated with the sub-word line driver SD belonging to the first section including the 0-th to 7-th regions R0to R7will not affect the 8-th to 15-th regions R8to R15of the second section. In like manner, an error associated with the sub-word line driver SD in the 8-th to 15-th regions R8to R15will not affect the 0-th to 7-th regions R0to R7. Additionally, an error resulting from a fault occurring in the 11-th to 1n-th word lines WL11to WL1n, will not affect the 8-th to 15-th regions R8to R15, and an error resulting from a fault occurring in the 21-th to 2n-th word lines WL21to WL2n, will not affect the 0-th to 7-th regions R0to R7. Accordingly, error-independent coverages may also be provided with regard to faults occurring at the word line level, as well as faults occurring at the sub-word line driver level. In addition, faults associated with the first row decoder320will not result in faults associated with the second row decoder330, and faults associated with the second row decoder330will not result in faults associated with the first row decoder320. Accordingly, error-independent coverages may be provided with regard to fault at the row decoder level.

FIG. 15is a conceptual diagram illustrating an example of a bank400having a structure that supports error-independent coverages or independent sections with regard to a row-dependent error. Referring toFIGS. 1, 2, and 15, the bank400may include a memory cell array410, a row decoder420, a first bit line sense amplifier440, a second bit line sense amplifier450, and a column decoder460.

Here, the structure and operation of the bank400may be the same as the bank200ofFIG. 3, except the number of word lines WL1to WL2nconnected with the row decoder420has been doubled.

FIG. 16is a conceptual diagram further illustrating in relevant portion the memory cell array410ofFIG. 15. Referring toFIGS. 1, 2, 15, and 16, the first to 2n-th word lines WL1to WL2nmay be connected in turn with memory cells of the first section including the 0-th to 7-th regions R0to R7and memory cells of the second section including the 8-th to 15-th regions R8to R15.

In some embodiments, odd-numbered word lines including the fifth word line WL5, the seventh word line WL7, and the ninth word line WL9may be connected with the memory cells of the first section including the 0-th to 7-th regions R0to R7. Thus, the odd-numbered word lines may pass through the second section to reach the first section. Analogously, even-numbered word lines including the sixth word line WL6, the eighth word line WL8, and the tenth word line WL10may be connected with the memory cells of the second section including the 9-th to 15-th regions R8to R15.

As described with reference toFIG. 12, and as a result of the structures described in relation toFIGS. 15 and 16, an error occurring in the sub-word line driver SD belonging to the first section including the 0-th to 7-th regions R0to R7will not affect the 8-th to 15-th regions R8to R15of the second section. Further, an error occurring in the sub-word line driver SD belonging to the second section including the 8-th to 15-th regions R8to R15will not affect the 0-th to 7-th regions R0to R7of the first section. In addition, an error associated with a fault occurring in an odd-numbered word line, will not affect the 8-th to 15-th regions R8to R15, and an error associated with a fault occurring in an even-numbered word line, will not affect the 0-th to 7-th regions R0to R7. Accordingly, error-independent coverages may be provided with regard to faults at a word line level, as well as faults at a sub-word line driver level.

FIG. 17is a flowchart summarizing in one example an operating method for the computing system1000ofFIG. 1. Referring toFIGS. 1 and 17, the memory controller1211may detect a power-on (S110). The memory controller1211may then recognize an isolated x8 memory module operating according to a defined burst length BL (S120). For example, the memory controller1211may receive information from a serial presence detect (SPD) of the memory module1100indicating the properties of the isolated x4 memory module as well as its burst length BL.

The isolated x8 memory module may be a memory module that supports two or more error-independent coverages with respect to the burst length BL, as described by way of examples illustrated inFIGS. 9 to 16(e.g., two or more error-independent coverages with regard to a row-dependent error) and based on memory devices receiving or transmitting data DT or the error correction code ECC via eight (8) data signals (×8).

The memory controller1211may perform error correction encoding on first data DT1corresponding to a first partial (e.g., a first half) burst length of the whole burst length BL to generate the first cyclic redundancy code C1and the first parity P1(S130). Additionally, the memory controller1211may perform error correction encoding on the second data DT2corresponding to a second partial (e.g., a second half) burst length of the whole burst length BL to generate the second cyclic redundancy code C2and the second parity P2(S140).

The memory controller1211may write the first data DT1and the second data DT2to first memory devices (e.g., the first memory devices for data1121to1124) during the first partial burst length and the second partial burst length (S150).

The memory controller1211may write the first cyclic redundancy code C1, the second cyclic redundancy code C2, the first parity P1, and the second parity P2to a second memory device (e.g., the first memory device for ECC1125) during the first partial burst length and the second partial burst length.

Two or more of the foregoing operating method steps (e.g., S110to S160) may be performed in, wholly or partially, in parallel for the second memory devices1126to1130using the second channel CH2, as well as the first channel CH1.

FIG. 18is another flowchart summarizing in one example a read operation that may be performed by the computing system1000ofFIG. 1. Referring toFIGS. 1 and 18, the memory controller1211may receive third data from first memory devices (e.g., the first memory devices for data1121to1124) and fourth data from a second memory device (e.g., the first memory device for ECC1125) (S210).

The memory controller1211may then perform error correction decoding on a first partial burst length of the third data using a portion of the fourth data (e.g., first cyclic redundancy code C1and first parity P1) (S220), and the memory controller1211may perform error correction decoding on a second partial burst length of the third data using the remaining portion of the fourth data (e.g., the second cyclic redundancy code C2and second parity P2) (S230).

Here, two or more of the read operation steps (e.g., S210to S230) may be performed, wholly or partially, in parallel on the second memory devices1126to1130using the second channel CH2, as well as the first channel CH1.

FIG. 19is a block diagram illustrating a computing system2000according to embodiments of the inventive concept. Referring toFIG. 19, the computing system2000may include a memory module2100and an external host device2200of the memory module2100.

The memory module2100may include a driver2110, first memory devices2121to2125and2131to2135, second memory devices2126to2130and2136to2140, a driver connector2150, first memory connectors2161to2165, second memory connectors2166to2170, a power management circuit2180, and a power connector2190.

A configuration and operation of the memory module2100may be the same as the memory module1100ofFIG. 1, except that the number of first memory devices2121to2125and2131to2135of the first channel CH1is 10 and the number of second memory devices2126to2130and2136to2140of the second channel CH2is increased from5to10.

In the illustrated embodiment ofFIG. 19, each of the first memory devices2121to2125and2131to2135and the second memory devices2126to2130and2136to2140may be implemented such that the number of memory cells MC connected with one sub-word line SWL is four (4).

Thus, each of the first memory devices2121to2125and2131to2135and the second memory devices2126to2130and2136to2140may be an x4 memory device that communicates four (4) data signals DQ (e.g., 4 bits) with a memory controller2211. Connectors of eight (8) data signals DQ used by the x8 memory device ofFIG. 1may be divided into two, vertically stacked memory devices.

The external host device2200may include a processor2210, a power supply2220, a host power management circuit2230, and a device driver2240. The processor2210may include the memory controller2211. The memory controller2211may include an error correction circuit2212. The configuration and operation of the external host device2200may be similar to that of the external host device1200described with reference toFIG. 1.

FIG. 20is a conceptual diagram illustrating an example of a data block that may be used in relation to the first memory devices2121to2125and2131to2135and the second memory devices2126to2130and2136to2140of the memory module2100ofFIG. 19. Referring toFIGS. 19 and 20, a data block may include 512 bits corresponding to first to fourth data signals DQ1to DQ4and the 0-th to 15-th burst lengths BL0to BL15.

The first memory devices for data2121to2124and2131to2134and the second memory devices for data2127to2130and2137to2140may store the data DT and may communicate the data DT with the memory controller2211. The first memory devices for ECC2125and2135and the second memory devices for ECC2126and2136may store the error correction code ECC including cyclic redundancy code “C” and parity “P”, and may communicate the error correction code ECC with the memory controller2211.

FIG. 21is a conceptual diagram illustrating in one example of data blocks including the data DT, the cyclic redundancy code “C” and the parity “P” of the first memory devices2121to2125and2131to2135of one channel (e.g., the first channel CH1) of the memory module2100. Data blocks of the second memory devices2126to2130and2136to2140of the second channel CH2may be the same as those described with reference toFIG. 21, except for the respective locations where the data blocks.

Referring toFIGS. 19, 20 and 21, the first memory devices2121to2125and2131to2135of the first channel CH1may communicate with the external host device2200in units of eight data blocks including the data DT and two data blocks including the cyclic redundancy code “C” and the parity “P”.

As described with reference toFIG. 11, two (2), error-independent memory devices for ECC may be provided with respect to eight (8), error-independent memory devices for data. Accordingly, the RAS coverage of the memory module2100may be the SDDC.

FIG. 22is a conceptual diagram illustrating on one example a data block for data providing two or more, error-independent coverages. Referring toFIGS. 19, 20, 21 and 22, and as described with reference toFIGS. 12, 13, 14, 15, and 16, two or more error-independent coverages may be provided based on two or more independent sections with regard to a row-dependent error.

The first coverage corresponding to the 0-th to 7-th burst lengths BL0to BL7may include the first data DT1. The second coverage corresponding to the 8-th to 15-th burst lengths BL8to BL15may include the second data DT2.

FIG. 23is a conceptual diagram illustrating in one example a data block for ECC providing two or more error-independent coverages. Referring toFIGS. 19, 20, 21, 22 and 23, and as described with reference toFIGS. 12, 13, 14, 15 and 16, two or more error-independent coverages may be provided based on two or more independent sections with regard to a row-dependent error.

The first coverage corresponding to the 0-th to 7-th burst lengths BL0to BL7may include the first cyclic redundancy code C1and/or the first parity P1corresponding to the first data DT1. The second coverage corresponding to the 8-th to 15-th burst lengths BL8to BL15may include the second cyclic redundancy code C2and/or the second parity P2corresponding to the second data DT2.

FIG. 24is a conceptual diagram illustrating in one example data blocks of the first memory devices2121to2125and2131to2135associated with one channel (e.g., the first channel CH1) of the memory module2100. Data blocks of the second memory devices2126to2130and2136to2140of the second channel CH2may be the same as those described with reference toFIG. 24, except for the respective locations of the data blocks.

Referring toFIGS. 22, 23 and 24, each of data blocks for data belonging to the first memory devices for data2121to1125and2131to1135may include the first data DT1and the second data DT2for each of first coverages2121ato2124aand2131ato2134aand second coverages2121bto2124band2131bto2134b.

Compared to the data blocks ofFIG. 21, the range of an error-independent space decreases from a memory device level to a coverage level. Accordingly, a range over which the memory controller2211may perform error correction encoding and decoding may decrease. As described with reference toFIG. 11, the amount of cyclic redundancy code and parity necessary to the memory controller2211to maintain a desired level of error correction performance may be halved.

As illustrated inFIG. 24, the amount of first and second cyclic redundancy code C1and C2and the amount of first and second parity may be halved, as compared with the illustrated example ofFIG. 21. Accordingly, even though one of the first memory devices for ECC2125and2135is removed from the memory module2100, the RAS of the memory module2100may maintain the SDDC.

In a state where the RAS of the SDDC is maintained, the memory module2100may remove one of the first memory devices2121to2125and2131to2135and may remove one of the second memory devices2126to2130and2136to2140. Accordingly, cost of the memory module2100may decrease in a state where the performance of the memory module2100is maintained. Also, power consumption of the memory module2100may decrease.

Connectors for the first memory device removed and data signals and data strobe signals assigned to the first memory device removed may be used for the driver2110to transmit signals for informing the external host device2200of information about a status of the memory module2100or to transmit any other necessary signals. Accordingly, the flexibility of the memory module2100may be improved.

The memory module1100according to embodiments of the inventive concept may include x8 memory devices and may expand the RAS from the SECDED to the SDDC without the reduction of bandwidth or the reduction of performance. Also, the memory module2100according to an embodiment of the inventive concept may include x4 memory devices and may maintain the RAS at the SDDC without the reduction of bandwidth or the reduction of performance, in a state where one memory device is used to store the error correction code ECC.

FIG. 25is a conceptual diagram illustrating in another example, data blocks of the first memory devices2121to2125and2131to2135associated with one channel (e.g., the first channel CH1) of the memory module2100. Data blocks of the second memory devices2126to2130and2136to2140of the second channel CH2may be the same as those described with reference toFIG. 24, except for the respective locations of the data blocks.

Referring toFIGS. 19, 22, 23, and 25, each of data blocks for data belonging to the first memory devices for data2121to1125and2131to1135may include the first data DT1and the second data DT2for each of the first coverages2121ato2124aand2131ato2134aand the second coverages2121bto2124band2131bto2134b.

Compared to the data blocks ofFIG. 21, a range of an error-independent space decreases from a memory device level to a coverage level. Accordingly, a range over which the memory controller2211may perform error correction encoding and decoding may decrease. As described with reference toFIG. 11, the amount of cyclic redundancy code and parity necessary to the memory controller2211to maintain a performance of error correction may be halved.

As illustrated inFIG. 25, the amount of first and second cyclic redundancy code C1and C2and the amount of first and second parity may be maintained to be the same as the illustrated example ofFIG. 21. Accordingly, the performance of error correction of the memory module2100, and the RAS may be improved compared to the example ofFIG. 21.

The foregoing embodiments describe some locations within a data block at which cyclic redundancy code “C” and parity “P” may be stored. However, such locations may vary with design, and the inventive concept is not limited to only the illustrated examples. In some embodiments, the arrangement and location of cyclic redundancy code “C” and parity “P” stored in a data block may be randomly determined by the external host device1200.

In the foregoing embodiments, components according to the inventive concept have been described in terms of “first”, “second”, “third”, and the like. However, the terms “first”, “second”, “third”, and the like may be used to distinguish components from each other and do not limit the inventive concept. For example, the terms “first”, “second”, “third”, and the like do not involve an order or a numerical meaning of any form.

In the above embodiments, components according to embodiments of the inventive concept are described by using blocks. The blocks may be implemented with various hardware devices, such as an integrated circuit, an application specific IC (ASCI), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software. Also, the blocks may include circuits implemented with semiconductor elements in an integrated circuit or circuits enrolled as intellectual property (IP).

According to embodiments of the inventive concept, a memory device has been described as including sections whose row-dependent errors are independent of each other. Accordingly, a memory device having a structure supporting a function for correcting an error is provided. Also, the memory device including sections whose row-dependent errors are independent of each other may provide two or more error-independent coverages with regard to data corresponding to one burst length. Accordingly, a memory module having an improved error correction function or capable of reducing the amount of resource necessary for error correction is provided.