Transient voltage suppressor apparatus

A transient voltage suppressor (TVS) apparatus includes a plurality of input/output (I/O) pins, a plurality of ground pins, and a substrate. The substrate includes a plurality of division parts and a carrier part. The carrier part carries a chip. The division parts are disposed between each of the I/O pins and the ground pins. The chip is electrically connected to the I/O pins and the ground pins, and the division parts are electrically insulated from the I/O pins and the ground pins.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application Ser. No. 105133626, filed on Oct. 19, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

Field of the Invention

The invention relates to a transient voltage suppressor (TVS); more specifically, the invention relates to a TVS apparatus.

Description of Related Art

Please refer toFIG. 1.FIG. 1illustrates a chip package structure according to the related art. The package structure100is configured to package a chip110that is, for instance, a transient voltage suppressor (TVS) chip. The package structure100includes a plurality of ground pins GP and a plurality of input/output (I/O) pins IO1-IO4. The chip110has a plurality of solder pads thereon, and the solder pads are connected to the ground pins GP and the I/O pins IO1-IO4through wire bonding. To reduce packaging costs, the ground pins GP and a lead frame111in the conventional package structure100are integrated, so as to reduce the number of wires between the chip110and the ground pins GP.

In the conventional package structure100, a plurality of parasitic capacitors are formed between each of the I/O pins IO1-IO4and an adjacent ground pin of the ground pins GP. For instance, parasitic capacitors C1-C3are formed between the exemplary I/O pin103and the adjacent ground pin GP. The parasitic capacitors C1-C3are coupled in parallel between the I/O pin IO3and the ground pin GP. Due to the arrangement of the parasitic capacitors, noticeable equivalent capacitance is generated. Thereby, signals received by the I/O pin IO3may be affected by the parasitic capacitors C1-C3and may then be distorted, and signal transmission quality may be deteriorated.

In another aspect, with the requirements for the reduced number of the required pins in the package structure100and the narrowed gap among the pins, the equivalent capacitance generated by the parasitic capacitors is increased, and the signal transmission quality is lessened.

SUMMARY OF THE INVENTION

The invention provides a transient voltage suppressor (TVS) apparatus having a chip package structure, wherein the equivalent capacitance between input/output (I/O) pins and ground pins is reduced.

In an embodiment of the invention, a TVS apparatus includes a plurality of I/O pins, a plurality of ground pins, and a substrate. The substrate includes a carrier part and a plurality of division parts. The carrier part is configured to carry a chip. The division parts extend from the carrier part, and each of the division parts is disposed between one of the I/O pins and one of the ground pins. The chip is electrically connected to the I/O pins and the ground pins, and the division parts are electrically insulated from the I/O pins and the ground pins.

According to an embodiment of the invention, at least one first capacitor is formed between each of the I/O pins and a corresponding division part of the division parts, and a plurality of second capacitors are formed between each of the ground pins and a corresponding division part of the division parts. The at least one capacitor and the second capacitors are serially coupled.

According to an embodiment of the invention, the substrate further includes a ground part, and parts of the ground pins and the ground part are integrally formed and arranged on the substrate.

According to an embodiment of the invention, the chip has a plurality of I/O solder pads and a plurality of ground solder pads. The I/O solder pads and the ground pads are electrically connected to the I/O pins and the ground pins through wire bonding.

In view of the foregoing, the division parts are formed in a conductive substrate of the chip package structure, and each of the I/O pins is separated from one of the ground pins by the floated division parts. Thereby, the serially connected capacitors can be formed among the I/O pins, the division parts, and the ground pins, so as to reduce the capacitance of the parasitic capacitors between the I/O pins and the ground pins and better prevent signal attenuation caused by signal transmission on the I/O pins.

DESCRIPTION OF EMBODIMENTS

Please refer toFIG. 2.FIG. 2is a schematic diagram of a TVS apparatus according to an embodiment of the invention. The TVS apparatus200includes a plurality of I/O pins IO1-IO4, a plurality of ground pins GP1-GP6, and a substrate210. The substrate210includes a carrier part211and a plurality of division parts212. The carrier part211is configured to carry a chip220. In the present embodiment, the substrate210may be a conductive substrate or a lead frame, and the chip220may be a TVS chip. The division parts212are arranged between the I/O pins IO1-IO4and the ground pins GP1-GP6. The division parts212are in a floated state. While the division parts212are in the so-called floated state, voltages in any form are not applied to the division parts212.

In the present embodiment, the division parts212and the carrier part211are coupled, and the division parts212extend outwardly from the carrier part211. The division parts212are arranged in a multi-finger manner (or in a herringbone-like manner) between the I/O pins IO1-IO4and the adjacent ground pins GP1-GP6. For instance, the division parts212are located between the I/O pin IO1and the adjacent ground pins GP1and GP2for separating the I/O pin IO1and the adjacent ground pins GP1and GP2. The division parts212are electrically insulated from the I/O pins IO1-IO4and electrically insulated from the ground pins GP1-GP6.

The chip220is disposed on the carrier part211, and the substrate of the chip220can be electrically insulated from the carrier part211. A plurality of solder pads are located on a first surface of the chip220, ground solder pads PD1-PD4are electrically coupled to the ground pins GP1, GP2, GP3, and GP5through a plurality of packaging wires, and I/O solder pads PD5-PD8are electrically coupled to the I/O pins IO1-IO4through a plurality of packaging wires.

The TVS apparatus200may include a package cover to cover the I/O pins IO1-IO4, the ground pins GP1-GP6, the conductive substrate10, and the chip220.

Please refer toFIG. 3AandFIG. 3B.FIG. 3Ais a schematic diagram illustrating a parasitic capacitor in the TVS apparatus200according to the embodiment depicted inFIG. 2.FIG. 3Bis a cross-sectional view taken along a line segment A-A′ inFIG. 3A. As shown inFIG. 3A, by the division parts212-1-212-4which have potential different form the I/O pins IO1-IO4and the ground pins GP1-GP6, a plurality of parasitic capacitors are formed between the I/O pins IO1-IO4and the adjacent division parts212-1-212-4and between the ground pins GP1-GP6and the adjacent division parts212-1-212-4.

As shown by the line segment A-A′ inFIG. 3B, the parasitic capacitor C1is formed between the ground pin GP6and the division part212-1, the parasitic capacitor C2is formed between the I/O pin IO3and the division part212-1, the parasitic capacitor C3is formed between the I/O pin IO3and the division part212-2, the parasitic capacitor C4is formed between the ground pin GP5and the division part212-2, the parasitic capacitor C5is formed between the ground pin GP5and the division part212-3, the parasitic capacitor C6is formed between the I/O pin IO4and the division part212-3, the parasitic capacitor C7is formed between the I/O pin IO4and the division part212-4, and the parasitic capacitor C8is formed between the ground pin GP4and the division part212-4.

Since the potential of the division parts is different from the potential of the I/O pins and the potential of the ground pins (e.g., floated), the arrangement of the division parts between the I/O pins and the ground pins allows the parasitic capacitors between the I/O pins and the adjacent ground pins to become serially coupled parasitic capacitors. For instance, two serially coupled parasitic capacitors C2and C1are located between the I/O pin IO3and the ground pin GP6, and two serially coupled parasitic capacitors C3and C4are located between the I/O pin IO3and the ground pin GP5. The equivalent capacitance CE between the I/O pin IO3and the ground pin may be represented as:

CE=11C⁢⁢1+1C⁢⁢2+11C⁢⁢3+1C⁢⁢4+CDIE,
wherein CDIEis the parasitic capacitance provided by the chip220.

As provided above, the equivalent capacitance of the parasitic capacitors between the I/O pins IO1-IO4and the ground pins can be effectively decreased, and signal distortion (caused by the parasitic capacitors) on the I/O pins IO1-IO4can be significantly reduced.

From another perspective, to reduce the number of the packaging wires between the chip220and the ground pins GP1-GP6, one or more ground parts221and222may be arranged in the TVS apparatus200according to an embodiment of the invention. Some of the pins GP1-GP6(e.g., the ground pins GP1and GP6) may be connected to the ground part221, and other ground pins (e.g., the ground pins GP3and GP4) are connected to the ground part222. If the ground solder pads on the chip220are required to be electrically connected to the ground pins GP1and GP6, the ground solder pads may be connected to the ground part221through one packaging wire, and thereby the ground solder pads on the chip220can be electrically coupled to the ground pins GP1and GP6through one packaging wire. Owing to the ground parts221and222, the connectible range of the ground pins GP1and GP6and the ground pins GP3and GP4can be expanded. Thereby, the length of the packaging wires connected to the ground pins GP1, GP6, GP3, and GP4can be reduced, and thus possible inductance resulting from the packaging wire may be prevented to a better extent.

In the TVS apparatus200, the ground part221and the ground pins GP1and GP6may be formed by one conductive metal layer made of one material and may be integrally formed. The ground part222and the ground pins GP3and GP4may be formed by one conductive metal layer made of one material and may be integrally formed. In other words, the arrangement of the ground parts221and222does not complicate the manufacture of the TVS apparatus200.

Please refer toFIG. 4.FIG. 4is a schematic diagram illustrating a manufacturing method of the TVS apparatus according to the embodiment depicted inFIG. 2andFIG. 3. InFIG. 4, a lead frame array includes a plurality of lead frames401-404. During the process of manufacturing the TVS apparatus, a plurality of chips are held by the lead frames401-404. A wire bonding process and a compound molding process are implemented, and a cutting process is performed along cutting way SW (shown by dotted lines inFIG. 4) to obtain a plurality of TVS apparatuses.

Please refer toFIG. 5AandFIG. 5B.FIG. 5Ais a schematic diagram illustrating a TVS apparatus according to another embodiment of the invention, andFIG. 5Bis a cross-sectional view taken along a line segment B-B′ inFIG. 5A. InFIG. 5A, the chip520is formed in the TVS apparatus500through flip-chip packaging. Flip-chip packaging is a packaging technology through which the chip can be directly connected to the substrate. During the packaging process, the chip is turned upside down, such that the solder pads on the active surface of the chip are directly connected to the circuit patterns (e.g., printed circuits of a printed circuit board) on the substrate.

The TVS apparatus500includes a substrate510, and the substrate510includes a plurality of I/O pins IO1-IO4, a plurality of ground pins GP1-GP6, and a division part512. The division part512includes branches512-1-512-4. The I/O pins IO1-IO4are respectively separated from the adjacent ground pins GP1-GP6through the branches512-1-512-4. Each of the branches512-1-512-4is electrically insulated from the I/O pins IO1-IO4and electrically insulated from the ground pins GP1-GP6and is in the floated state because no voltage is applied in any form to the branches512-1-512-4. Thereby, the equivalent capacitance provided by the parasitic capacitors between the I/O pins IO1-IO4and the ground pins GP1-GP6can be reduced.

The I/O solder pads PD5-PD8and the solder pads PD1-PD4, PD9, and PD10on the chip520are bonded to the ground pins GP1-GP6and the I/O pins IO1-IO4. As shown by the line segment B-B′ inFIG. 5B, the ground solder pad PD10, the I/O solder pad PD8, the ground solder pad PD4, the I/O solder pad PD7, and the ground solder pad PD9are electrically coupled to the ground pin GP6, the I/O pin IO3, the ground pin GP5, the I/O pin IO4, and the ground pin GP4through conductive bumps B-1-B-4, respectively.

In the present embodiment, the parasitic capacitor C1is formed between the ground pin GP6and the branch512-1, the parasitic capacitor C2is formed between the I/O pin IO3and the branch512-1, the parasitic capacitor C3is formed between the I/O pin IO3and the branch512-2, the parasitic capacitor C4is formed between the ground pin GP5and the branch512-2, the parasitic capacitor C5is formed between the ground pin GP5and the branch512-3, the parasitic capacitor C6is formed between the I/O pin IO4and the branch512-3, the parasitic capacitor C7is formed between the I/O pin IO4and the branch512-4, and the parasitic capacitor C8is formed between the ground pin GP4and the branch512-4. That is, two serially connected parasitic capacitors may be located between any of the I/O pins and the adjacent ground pins, so as to reduce the equivalent capacitance provided by the parasitic capacitors between any of the I/O pins and the adjacent ground pins.

The conductive bumps B1-B4may be gold bumps, tin-lead balls, or the conductive bumps that are made of any material and may be configured to perform electrical connection in flip-chip packaging, as known to people having ordinary skill in the pertinent art.

To sum up, the floated division parts are configured between each of the I/O pins and the adjacent ground pin. Since the potential of the (e.g., floated) division parts is different from the potential of the I/O pins and the potential of the ground pins, the arrangement of the division parts between the I/O pins and the ground pins allows the parasitic capacitors between the I/O pins and the adjacent ground pins to become serially coupled parasitic capacitors, and the equivalent capacitance provided by the parasitic capacitors between the I/O pins and the ground pins can be effectively reduced. As such, the impact of the parasitic capacitors on distortion of signals transmitted on the I/O pins can be lessened, and the signal transmission accuracy can be enhanced.