Split write operation for resistive memory cache

A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.

TECHNICAL FIELD

The present disclosure generally relates to resistive memories such as magnetic random access memory (MRAM) devices or resistive random access memory (RRAM) devices. More specifically, the present disclosure relates to improving resistive memory cache performance by splitting write operations.

BACKGROUND

Unlike conventional random access memory (RAM) chip technologies, in magnetic RAM (MRAM) data is not stored as electric charge, but is instead stored by magnetic polarization of storage elements. The storage elements are formed from two ferromagnetic layers separated by a tunneling layer. One of the two ferromagnetic layers, which is referred to as the fixed layer or pinned layer, has a magnetization that is fixed in a particular direction. The other ferromagnetic magnetic layer, which is referred to as the free layer, has a magnetization direction that can be altered to two different states. These different states of the free layer are used to represent either a logic “1” when the free layer magnetization is anti-parallel to the fixed layer magnetization or a logic “0” when the free layer magnetization is parallel to the fixed layer magnetization, or vice versa. One such device having a fixed layer, a tunneling layer, and a free layer is a magnetic tunnel junction (MTJ). The electrical resistance of an MTJ depends on whether the free layer magnetization and fixed layer magnetization are parallel or anti-parallel with each other. A memory device such as MRAM is built from an array of individually addressable MTJs.

To write data in a conventional MRAM, a write current, which exceeds a critical switching current, is applied through an MTJ. The write current exceeding the critical switching current is sufficient to change the magnetization direction of the free layer. When the write current flows in a first direction, the MTJ can be placed into or remain in a first state, in which its free layer magnetization direction and fixed layer magnetization direction are aligned in a parallel orientation. When the write current flows in a second direction, opposite to the first direction, the MTJ can be placed into or remain in a second state, in which its free layer magnetization and fixed layer magnetization are in an anti-parallel orientation.

To read data in a conventional MRAM, a read current may flow through the MTJ via the same current path used to write data in the MTJ. If the magnetizations of the MTJ's free layer and fixed layer are oriented parallel to each other, the MTJ presents a resistance that is different than the resistance the MTJ would present if the magnetizations of the free layer and the fixed layer were in an anti-parallel orientation. In a conventional MRAM, two distinct states are defined by two different resistances of an MTJ in a bitcell of the MRAM. The two different resistances represent a logic 0 and a logic 1 value stored by the MTJ.

To determine whether data in a conventional MRAM represents a logic 1 or a logic 0, the resistance of the MTJ in the bitcell is compared with a reference resistance. The reference resistance in conventional MRAM circuitry is a midpoint resistance between the resistance of an MTJ having a parallel magnetic orientation and an MTJ having an anti-parallel magnetic orientation. One way of generating a midpoint reference resistance is coupling in parallel an MTJ known to have a parallel magnetic orientation and an MTJ known to have an anti-parallel magnetic orientation in parallel with each other.

SUMMARY

In one aspect of the present disclosure, a method of reading from and writing to a resistive memory cache is disclosed. The method includes receiving a write command. The method also includes dividing the write command into a set of write sub-commands. The method further includes receiving a read command. The method also includes executing the read command before executing a next write sub-command.

In another aspect, a resistive memory cache is disclosed. The resistive memory cache includes a multiplexer including at least one input port and at least one output port. The resistive memory cache also includes a memory coupled to the output port(s) of the multiplexer. The resistive memory cache further includes a write buffer coupled to the input port(s) of the multiplexer. The write buffer also has at least one write buffer entry including data, an address and a write command pulse counter.

Another aspect discloses a resistive memory cache. The resistive memory cache includes a multiplexer having at least one input port and at least one output port. The resistive memory cache also includes means for storing data coupled to the output port(s) of the multiplexer. The resistive memory cache further includes means for buffering write commands coupled to the input port(s) of the multiplexer. The means for buffering write commands also has at least one write buffer entry including a data, an address and a write command pulse counter.

DETAILED DESCRIPTION

For an accurate resistive memory device, the probability of successfully switching a resistive memory bit cell from “0” to “1” or from “1” to “0” should be close to 100%. The switching probability can be calculated from the below equation (1):

Where Psw is the switching probability, exp(x) is the exponential function, tswis the switching pulse, τ0is the normalized delay, Δ is the thermal stability, J is the switching current and JCis the critical current. The normalized delay (τ0), thermal stability (Δ) and critical current (JC) are all parameters related to the materials of magnetic random access memories (MRAM) or other similar resistive memories.

Generally, to reach a high switching probability (Psw) close to 100%, a large switching current (J) and a long switching pulse (tsw) are used. Because a resistive memory device cannot be read during a write pulse, long write pulses create longer write latency. This leads to slower memory and system performance.

In one aspect of the disclosure, multiple short write pulses are applied to the resistive memory device instead of one long write pulse. Applying multiple short write pulses to the resistive memory device allows for read operations to be performed within the same time period as one long write pulse. For example, one long write pulse can be expressed in the below equation (2) with the switching pulse of tsw:

Psw,1,long=1-exp⁡(-tswτ0⁢B)(2)
where B represents the below quantity assuming a fixed switching current (J) and critical current (JC) value, as shown in equation (3):

If one long pulse is expressed by the above equation (2), then one short write pulse can be expressed by equation (4). The same overall switching pulse value tswis applied, but each write pulse is a short 1/n fraction of a single switching pulse (tsw/n) as seen below.

Therefore, applying n short write pulses can be expressed by the below equation (5), and ends up being equal to one long write pulse.

In one aspect of the disclosure, a method of reading from and writing to a resistive memory cache includes receiving a write command and converting that write command into a number of smaller write command pulses instead of processing it as one large write command pulse. The method may also include receiving a read command and executing that read command before executing a next write command pulse.

A write buffer entry may also be created in response to receiving the write command. The entry includes data, an address, and a number of write command pulses remaining. The number of write command pulses remaining may be implemented as a counter and may start from zero and count up, or start from n and count down. Every time a write command is executed, the number of write command pulses is modified (either incremented or decremented) to represent that n write command pulses have been executed.

FIG. 1illustrates a memory cell100including a magnetic tunnel junction (MTJ)102coupled to an access transistor104. A free layer110of the MTJ102is coupled to a bit line112. The access transistor104is coupled between a fixed layer106of the MTJ102and a fixed potential node122. A tunnel barrier layer114is coupled between the fixed layer106and the free layer110. The access transistor104includes a gate116coupled to a word line118.

Synthetic anti-ferromagnetic materials may be used to form the fixed layer106and the free layer110. For example, the fixed layer106may comprise multiple material layers including a Cobalt Iron Boron (CoFeB) layer, a Ruthenium (Ru) layer and a Cobalt Iron (CoFe) layer. The free layer110may be an anti-ferromagnetic material, such as CoFeB, and the tunnel barrier layer114may be Magnesium Oxide (MgO), for example. The memory cell100is an example of a resistive memory element making up a cache memory or other resistive memory device.

FIG. 2is a diagram of an example cache memory200including a cache controller240according to an aspect of the present disclosure. A cache memory200includes a page number202, a set number204, a byte number206, a cache way208, a tag portion210, a data portion212, a cache block214, one or more cache sets216, a tag sense amplifier218a, a data sense amplifier218b, a tag output220, a comparator222, a logic gate224, a cache group226, select circuitry228, and a word output230.

An address in the cache memory200may include the page number202, the set number204and the byte number206. In one implementation, the page number202may be a virtual page number. The set number204corresponds to one of the cache sets216. The cache block214includes the tag portion210and the data portion212. The tag portion210may contain part of the address of the actual data in the data portion212, or other identifying information to locate the data in the data portion212. The data portion212contains the actual data. One of the cache sets216is one set of cache blocks214, as can be seen by the horizontal grouping inFIG. 2. The cache way208is another group of cache blocks214, but in a vertical grouping, as can be seen inFIG. 2. The tag sense amplifier218aand data sense amplifier218bsense logic levels from the cache entries so the data is properly interpreted (as a logic 1 or 0) when output.

The data at the tag output220, which is the output of the tag sense amplifier218a, may contain a page frame number, a valid bit and coherence bits. The data from the tag output220is then compared to the page number202by the comparator222, which determines if the two values are equal. If the values are equal, then the output of the comparator222is input, along with the output of the data sense amplifier218b, into the logic gate224. The output of the logic gate224appears in the cache group226. In one implementation, one of the cache groups226contains multiple words. The cache group226is input into select circuitry228, which uses the byte number206as a select input. The output of the select circuitry228using the byte number206as the select input is the word output230.

FIG. 2is an example block diagram for an n-way set-associative cache, however, there may be other types of caches used in accordance with the present disclosure. A set-associative cache can be made of several direct-mapped caches operating in parallel (for example, one direct-mapped cache could be a cache entry including the tag portion210and the data portion212). The data readout may be controlled by a tag comparison with the page number202as well as the block-valid bit (which can be part of the tag or metadata entry) and the page permissions (part of the page number202). The cache column size may also equal the virtual memory page size, and the cache index may not use bits from the page number202or virtual page number.

FIG. 3is a schematic of a resistive memory cache300illustrating a read path and a write path according to an aspect of the present disclosure. The signals input to the resistive memory cache300include a first input data write signal HWDATAS1, a second input data write signal HWDATAS2, a first input data read signal HRDATAM0, and a second input data read signal HRDATAM1. The signals output from the resistive memory cache300include a first output data read signal HRDATAS0, a second output data read signal HRDATAS1, a first output data write signal HWDATAM1 and a second output data write signal HWDATAM2. The resistive memory cache300includes a first multiplexer302that outputs the HRDATAS0 signal, a second multiplexer304that outputs the HRDATAS1 signal, a third multiplexer306that receives the HWDATAS1 signal and the HWDATAS2 signal, a fourth multiplexer308that receives input from a first line read buffer318, a fifth multiplexer310that receives input from a second line read buffer320, a sixth multiplexer322that receives input from a first line fill buffer336, a seventh multiplexer324that receives input from a second line fill buffer338, a main multiplexer328, and an eighth multiplexer334that outputs the HWDATAM2 signal.

The resistive memory cache300also includes a write buffer312that receives input from the third multiplexer306and outputs data to the main multiplexer328, to a write allocate buffer326, and to the eighth multiplexer334. The write allocate buffer326receives input from the second line fill buffer338and the write buffer312. An eviction buffer332receives input from a memory330and outputs to the eighth multiplexer334.

The first line read buffer318receives input from the memory330and outputs to the fourth multiplexer308and the second line read buffer320receives input from the memory330and outputs to the second multiplexer304. The first line fill buffer336receives input from the HRDATAM0 signal and outputs to the sixth multiplexer322and the second line fill buffer338receives input from the HRDATAM1 signal and outputs to the seventh multiplexer.

The memory330stores data that is written to and read from by the various components in the resistive memory cache300. The memory330has an output340and an input342. In one implementation, the output340and the input342share the same port341. Data intended to be written comes from the main multiplexer328and transfers into the memory330via the input342. Data to be read from the memory330is output via the output340and sent to the first line read buffer318.

The resistive memory cache300also includes an event monitor316. Cache events314are input to the event monitor316. Cache events314represent relevant events that occur in the resistive memory cache300.

The read path is expressed as data transferred from the memory330via the output340to the first line read buffer318and the second line read buffer320. The read path may also be on a critical path, the longest necessary path through components of the resistive memory cache300in order to perform a read or write operation.

The write path is expressed as data transferring from the write buffer312and the write allocate buffer326on one end (the top) and data from the first line fill buffer336and the second line fill buffer338on another end (the bottom) to the main multiplexer328. Then, the data flows from the main multiplexer328to the memory330. The write path may not be on the critical path.

Although the read path and the write path are separate, they may share the same port341. A long write latency may block the input342and/or the output340because the shared input/output port341will be occupied by the long write operation. This in turn delays the read access. That is, the read operation may not be performed until the write operation is completed. As a result, the speed of the resistive memory cache300is made slower.

FIGS. 4A-4Bare timing diagrams illustrating different write pulse configurations according to aspects of the present disclosure. A first timing diagram400shows the timing operation of a typical resistive memory device that uses a long write pulse. The first timing diagram400shows a clock signal402, an arrival timing of a command404, and an execution timing of a command406. The command arrival timing404and the command execution timing406show arrival and execution of a number of read or write commands, shown here as “RD0”, “RD1”, “WR0”, “RD2” and “RD3.” Each of the arriving commands executes at a delayed time after the arrival.

In the example of the first timing diagram400, a read operation takes two clock cycles and a write operation (“WR0”) takes ten clock cycles. Therefore, as can be seen in the first timing diagram400, the “WR0” command executes as a long, (e.g., ten clock cycle) “WR0” command. For this reason, the execution of the “RD2” and “RD3” commands are delayed, and can only be executed after completing execution of the “WR0” command. Because the read command(s) are forced to wait until the write command(s) is executed, the performance and speed of the resistive memory device is reduced.

A second timing diagram410shown inFIG. 4Billustrates the timing operation of a resistive memory device according to an aspect of the present disclosure that uses multiple short write pulses instead of one long write pulse. The second timing diagram410also shows the clock signal402, the command arrival timing404and a revised command execution timing408. In the second timing diagram410, the arriving “WR0” command is divided into separate and smaller sub-commands. In this example, “WR0” is divided into five write sub-commands or pulses: “WR0-p1”, “WR0-p2”, “WR0-p3”, “WR0-p4” and “WR0-p5” to be executed. Each of these shorter write operation sub-commands only takes two clock cycles to execute, which in this example is the same time it takes for a read operation to execute. Because the shorter “WR0-p1” sub-command is executed first, the read commands “RD2” and “RD3” can be executed sooner, or in between any of the write pulses. Then, the rest of the “WR0” sub-commands (p2-p5) are executed. Although this example describes the write pulse width as equal to the read pulse width, the shorter write pulse width can be of any length.

Distributing smaller write pulses around higher priority operations allows for the overall read/write operation to be improved. Therefore, the resistive memory device may be able to finish operations faster and in a more efficient manner. For example, the second timing diagram410has a performance improvement412of nearly eight (8) clock cycles in that all the read commands (“RD0” to “RD3”) are completed nearly eight clock cycles before the read commands are executed in the first timing diagram400.

When an incoming write command is received, the command is divided into sub-commands. The write command and/or the sub-commands can be stored in a write buffer. Each write buffer entry may contain data and an address. Moreover, each entry can also include the number of remaining write sub-commands associated with the write command. The number of remaining sub-commands can be implemented as a counter.

In one aspect of the present disclosure, an algorithm to improve resistive memory cache performance has four main steps.

First, the number of sub-commands, N, the write command will be divided into is determined. For example, a long write pulse operation may be split into N=5 sub-commands, as shown inFIG. 4B. Each sub-command will have a length corresponding to a number of clock cycles and can be uniform. In another implementation, every sub-command has different clock cycle lengths.

Second, when a new write command arrives and the write buffer is not full, the data and the address information entries are emptied. There is also a counter that tracks how many write sub-commands there are. The counter may start from N and count down, or may start from 0 and count up to N−1, or start from 1 and count up to N. The counter may be implemented in hardware.

Third, entries from the write buffer are drained whenever the read queue becomes empty. The oldest write buffer entry may be drained first. The short write pulses are applied one-by-one, and the counter is modified (either by decrementing (starting from N) or incrementing (starting from 0 or 1)). Once the counter reaches 0 (in the case of starting from N), then that write buffer entry is removed.

Fourth, when a new write command arrives and the write buffer is full, the read queue is blocked if the read queue is not empty. Then, the write sub-commands are executed until the oldest write buffer entry is freed. The second step above (emptying the data and address information entries) may also be repeated until the oldest write buffer entry is freed. The read queue may also be unblocked at this time, if desired.

FIG. 5is a process flow diagram illustrating a method500of reading from and writing to a resistive memory cache according to an aspect of the present disclosure. In block502, a write command is received. In block504, the write command is divided into a set of write sub-commands. In block506, a read command is received. In block508, the read command is executed before executing a next write sub-command. In one implementation, the method500also includes determining whether a write buffer is full, executing the read command when the write buffer is not full, and executing the next write sub-command when the write buffer is full, instead of executing the read command. In another implementation, the method500also creates a write buffer entry in response to receiving the write command. The entry includes data, an address, and a number of write sub-commands remaining. In that case, the method500may also include executing a write sub-command and modifying the number of write command sub-commands remaining after executing the write sub-command. Furthermore, the method500may also include removing the write buffer entry when the set of write sub-commands is executed.

Although blocks are shown in a particular sequence, the present disclosure is not so limited. Provided is a method to improve the performance of a resistive memory cache by splitting the write operation into smaller write pulses. If used correctly, the approach of the present disclosure can improve the performance of typical resistive memory devices. CPU performance may also be increased.

In the above, a resistive memory device or a resistive memory element can include a magnetic tunnel junction (MTJ), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), or any resistive memory with a reference system.

According to a further aspect of the present disclosure, a resistive memory cache is provided. The resistive memory cache also includes means for storing data. The means for storing data includes the memory330. In another configuration, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

The resistive memory cache also includes means for buffering write operations. The means for buffering includes the write buffer312as well as the line read buffers318and320, the line fill buffers336and338, and the eviction buffer332. In another configuration, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.

FIG. 6is a block diagram showing an exemplary wireless communication system600in which an aspect of the disclosure may be advantageously employed. For purposes of illustration,FIG. 6shows three remote units620,630, and650and two base stations640. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units620,630, and650include IC devices625A,625C, and625B that include the disclosed resistive memory devices or resistive memory caches. It will be recognized that other devices may also include the disclosed resistive memory devices, such as the base stations, switching devices, and network equipment.FIG. 6shows forward link signals680from the base station640to the remote units620,630, and650and reverse link signals690from the remote units620,630, and650to base stations640.

InFIG. 6, remote unit620is shown as a mobile telephone, remote unit630is shown as a portable computer, and remote unit650is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, GPS enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, or other devices that store or retrieve data or computer instructions, or combinations thereof. AlthoughFIG. 6illustrates remote units according to the aspects of the disclosure, the disclosure is not limited to these exemplary illustrated units. Aspects of the disclosure may be suitably employed in many devices, which include the disclosed resistive memory devices.

FIG. 7is a block diagram illustrating a design workstation700used for circuit, layout, and logic design of a semiconductor component, such as the resistive memory devices disclosed above. A design workstation700includes a hard disk701containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation700also includes a display702to facilitate design of a circuit710or a semiconductor component712such as a resistive memory device. A storage medium704is provided for tangibly storing the circuit design710or the semiconductor component712. The circuit design710or the semiconductor component712may be stored on the storage medium704in a file format such as GDSII or GERBER. The storage medium704may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation700includes a drive apparatus703for accepting input from or writing output to the storage medium704.

Data recorded on the storage medium704may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium704facilitates the design of the circuit design710or the semiconductor component712by decreasing the number of processes for designing semiconductor wafers.