Flash memory cell with a flair gate

An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

BACKGROUND

Due to the inevitable requirements to further shrink design rules while still maintaining sufficient oxide thickness for isolation, there is a trend in the semiconductor field away from Local Oxidation of Silicon (LOCOS) and toward Shallow Trench Isolation (STI) because STI has superior scalability. However, STI is not without its disadvantages.

FIG. 1illustrates a conventional flash memory structure100using STI. Flash memory structure100has a plurality of bitlines110and a wordlines120. A memory cell is formed by the intersection of a bitline and a wordline. In between the bitlines110are the STI trenches. Due to damage caused at the bitline-STI edge during manufacturing, current variations are seen at the bitline-STI edge. In other words, the current through the a bitline110has both a center current component130and an edge current component140. The edge current component140is much slower than the center current component130. The presence of the slower edge currents140causes increased programming time, thus limiting the programming speed of the memory cell. Consequently, conventional memory cells using STI technology achieve less than optimal programming speeds.

SUMMARY

An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

Thus, embodiments of the present invention pertain to devices and methods that provide improved memory cell performance, and in particular, a reduction in bitline-STI edge current. By reducing bitline-STI edge current, embodiments provide for memory cells that have improved programming speed.

DETAILED DESCRIPTION

Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations for fabricating semiconductor devices. These descriptions and representations are the means used by those skilled in the art of semiconductor device fabrication to most effectively convey the substance of their work to others skilled in the art. A procedure, logic block, process, etc., is herein, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Unless specifically stated otherwise as apparent from the following discussions, is appreciated that throughout the present application, discussions utilizing terms such as “forming,” “performing,” “producing,” “depositing,” or “etching,” or the like, refer to actions and processes of semiconductor device fabrication.

Briefly stated, embodiments reduce the effect of bitline-STI edge currents in memory cells by using a “flair” gate structure. In other words, for each memory cell, the wordline width at the center of the cell represents the wordline width of the cell. At the bitline-STI edges of the memory cell, the wordline flares wider. The wider wordline width at the edges forces the majority of the current to go through the central portion of the bitline, thus effectively minimizing the effect of the bitline-STI edge.

FIG. 2Aillustrates a cross-sectional view of an exemplary semiconductor device, in accordance with various embodiments of the present invention. In one embodiment, the semiconductor device is a NAND memory cell. The device includes a substrate210and a gate structure220formed over the substrate210. It should be appreciated that gate structure220may be achieved in many ways. For example, gate structure220may be a charge trapping structure or a floating gate structure. Gate structure220may include an oxygen layer221, a nitrogen layer222, and a second oxygen layer223.

As shown inFIG. 2B, mask pattern230is formed over the gate structure220. Mask pattern230can be one of a number of different types of masks, including optical photoresist responsive to visible engineer UV light, deep UV resistant, and the like. Alternatively, mask pattern230can be inorganic resist layer, and x-ray resist layer, and the like. In one embodiment, mask pattern230is a hard mask structure. In one embodiment, mask pattern230is silicon dioxide or silicon nitride.

Mask pattern230(if photosensitive resist) is exposed to radiation of the appropriate wavelength and developed to form a mask pattern overlying substrate210, as illustrated inFIG. 2B. Alternatively, mask230can be deposited as a hard mask using process is well-known in the art. Mask pattern230allows for exposing a selected region of the gate structure220. The selected region will form an STI trench after subsequent processing steps.

As shown inFIG. 2C, after the mask pattern230is formed, the etching process removes a portion of material from gate structure220and substrate210to form trenches240in the selected regions. The etching presses removes material from the gate structure220and the substrate210that is not protected by the mask pattern230.

FIG. 2Dillustrates a cross-sectional view of an exemplary semiconductor device after filling the trenches240. In one embodiment, trenches240are filled with an oxide250that is appropriate for STI technology.

FIG. 2Eillustrates a cross-section of an exemplary semiconductor device after forming STI regions and after a polishing step has been done to remove excess material (i.e., mask pattern230and oxide material). Polishing can be done in many ways that are known in the art, and one embodiment, a chemical mechanical planarization (CMP) is done to smooth the surface of the semiconductor device so the surface is level with the gate structure220. The CMP is also done to remove the mask pattern230so subsequent layers can be formed over the gate structure220. Once the STI regions have been formed, the portion of the substrate210adjacent to the STI regions consequently becomes an active region215of the substrate210. As shown inFIG. 2F, a polysilicon layer260may then be formed over the gate structure220and over the STI regions.

FIGS. 2G-2Iillustrate a top views of an exemplary semiconductor device after forming STI regions and after a polishing step.FIGS. 2G-2Iare provided for illustrative purposes to show a memory cell and portions of two adjacent memory cells, and it should be appreciated that the actual device may extend beyond what is shown (i.e., longer bitlines and longer wordlines). As shown inFIGS. 2G-2I, a second mask pattern270is placed over the device. The shape of mask pattern270is such that its width over a bitline-STI edge is greater than its width over an active region215of the substrate210. For example, mask pattern270aofFIG. 2Gemploys an “H” pattern, while mask pattern270bofFIG. 2Hemploys more of sawtooth pattern, and further still mask pattern270cofFIG. 2Iemploys a somewhat sinusoidal pattern. It should be appreciated that other shapes of mask patterns may be used instead of the patterns depicted inFIGS. 2G-2I, so long that the width over the bitline-STI edge is greater than the width over the center of the active region215of the substrate210.

Once the mask pattern270is in place, the portions of the poly layer260and the gate structure220not covered by the mask270are etched. The mask pattern270is subsequently removed, revealing a gate structure similar in shape to that of the mask pattern270.

FIG. 3illustrates a portion of a memory array300, in accordance with various embodiments of the present invention. In one embodiment, memory array300is a flash memory array. InFIG. 3, for simplicity of discussion and illustration, a limited number of wordlines320and bitlines310are illustrated. However, it is understood that a memory array may actually utilize a different number of wordlines and bitlines. That is, memory array300will in actuality extend further to the left and right and also horizontally and vertically (left, right, horizontal, and vertical being relative directions). Wordlines may be referred to as rows and bitlines may be referred to as columns; however, it is understood that those are relative terms. It is also understood that only certain elements of a memory array are illustrated; that is, a memory array may actually include elements other than those shown.

The bitlines310are substantially parallel to each other, and wordlines320are substantially orthogonal to the bitlines310. STI regions run between the bitlines310. The wordlines320and the bitlines310overlap (but are not connected) at a number of nodes. Corresponding to each of these nodes is a memory cell. The memory cells may be a single bit memory cell or a mirror bit memory cell. Of particular interest is the shape of the wordlines320. Wordlines320are formed such that their width over a bitline-STI edge (WE) is greater than their width over the center of a bitline (WC). The presence of the wider wordline width at the edge forces the majority of the current330to go through the central portion of the wordline, thereby dramatically reducing currents along the bitline-STI edges.

FIG. 4is a flowchart of a process400for forming a memory cell, in accordance with various embodiments of the present invention. In one embodiment, the memory cell is a NAND memory cell. Furthermore, although specific steps are disclosed in process400, such steps are exemplary. That is, the present invention is well-suited to performing various other steps or variations of the steps recited in process400. For simplicity of discussion illustration, process400is described for single memory cell, although in actuality multiple memory cells may be formed.

Is appreciated other processes and steps associated with the fabrication of a memory cell may be performed along with process400illustrated inFIG. 4; that is, there may be a number of process steps before and after the steps shown in described byFIG. 4. Importantly, embodiments can be implemented in conjunction with these other (conventional) processes and steps without significantly perturbing them. Generally speaking, process steps associated with the various embodiments of the present invention can be added to conventional process without significantly affecting the peripheral processes and steps.

At block410a gate structure is formed over a substrate. In one embodiment, the gate structure may comprise an ONO charge trapping structure. In another embodiment, the gate structure may comprise a floating gate structure.

At block420, a mask pattern is formed over the gate structure. The mask pattern can be one of a number of different types of masks, including optical photoresist responsive to visible engineer UV light, deep UV resistant, and the like. Alternatively, the mask pattern can be inorganic resist layer, and x-ray resist layer, and the like. In one embodiment, the mask pattern is a hard mask structure. In one embodiment, the mask pattern is silicon dioxide or silicon nitride.

At block430, a trench is etched into the substrate and the gate structure. For example, the mask pattern (if photosensitive resist) is exposed to radiation of the appropriate wavelength and developed to form a mask pattern overlying the substrate, as illustrated inFIG. 2B. Alternatively, the mask can be deposited as a hard mask using processes well-known in the art. The mask pattern allows for exposing a selected region of the gate structure. The selected region will form an STI trench after subsequent processing steps.

At block440, the trench is filled with an oxide to form an STI region. At block450, the device is polished in order to remove excess material such as the mask pattern and any residual oxide material. Polishing can be done in many ways that are known in the art, and one embodiment, a chemical mechanical planarization (CMP) is done to smooth the surface of the semiconductor device so surfaces level with the gate structure. The CMP is also done to remove the mask pattern so subsequent layers can be formed over the gate structure. Once the STI regions have been formed, the portion of the substrate adjacent to the STI regions effectively becomes an active region of the substrate (e.g., active region215ofFIG. 2E). At block460, a polysilicon layer260is formed over the gate structure and over the STI region.

At block470, the memory cell is masked with a flair gate mask. The shape of the flair gate mask is such that its width over a bitline-STI edge is greater than its width over an active region of the substrate. It should be appreciated that a variety of flair gate mask shapes may be created that conform to these requirements.

At block480, the portions of the polysilicon layer and the gate structure that are not covered by the flair gate mask are etched. At block490, the mask is then removed, revealing a flair gate structure similar in shape to that of the flair gate mask pattern (e.g., gate structure of memory cells depicted inFIG. 3).

In summary, embodiments of the present invention pertain to devices and methods that provide improved memory cell performance, and in particular, a reduction in bitline-STI edge current. By reducing bitline-STI edge current, embodiments provide for memory cells that have improved programming speed.