Pixel electrode structure having via holes disposed on common line with high display quality

A pixel electrode structure includes a transparent substrate, a data line, a common line, a first array pixel, and a second array pixel disposed on the transparent substrate. The first/second array pixels respectively include a thin film transistor, a pixel electrode, and a gate line, and the common line is disposed at a lateral side of the gate line. A first via hole and a second via hole are respectively disposed on common line and in contact with an extending portion of the first thin film transistor and an extending portion of the second thin film transistor. A dummy line is disposed at a side of the data line, and a third via hole is disposed both on the dummy line and on the common line. The present invention can not only increase the aperture ratio of the pixel, but have a better stability of the common voltage signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a pixel electrode structure, and more particularly, to a pixel electrode structure with high display quality.

2. Description of the Prior Art

Please refer toFIG. 1. In a conventional active matrix type liquid crystal display (LCD), each pixel of a single-gate circuit structure includes a thin-film transistor10. A gate electrode of the thin film transistor10is connected to a horizontal gate line12, a source electrode of the thin film transistor10is connected to a vertical data line14, and a drain electrode of the thin film transistor10is connected to a pixel electrode. Each thin film transistor10in a same row is connected to a different data line14.

In the following, a basic method of operating the conventional single-gate circuit structure is described. Each thin film transistor10in a same horizontal row has a gate electrode electrically connected to a same gate line12, such that the gate electrodes are also electrically connected to each other. Thus, voltages applied to the gate electrodes of the thin film transistors electrically connected to the same gate line12are approximately equal, and are changed together. If a sufficiently large positive voltage is applied to a gate line12, all thin film transistors10connected to the gate line12will be turned on. The pixel electrodes disposed along the gate line12are electrically connected to corresponding vertical data lines14, and corresponding data signals are transferred into the vertical data lines14to charge the corresponding pixel electrodes to appropriate voltages. Next, a sufficiently large negative voltage is applied to the gate electrodes to turn off the thin film transistors10. During the period when the thin film transistors10are turned off, the electric charges of the data signals are thus stored in the liquid crystal capacitors until next data signals are to be written. The next horizontal gate line12is then turned on, and the corresponding data signals are transferred into the corresponding data lines14. As a result, the data signals of a whole frame can be written into the thin film transistors10in sequence according to the aforementioned method. Thereafter, the process of transferring the data signals can start again from the first gate line.

Because number of the plurality of data lines14is high, and the number of expensive source chips used is increasing accordingly, cost of the display panel is high in the aforementioned single-gate circuit structure. In order to reduce the cost, a dual-gate circuit structure is provided, as shown inFIG. 2. Each pair of adjacent columns of thin film transistors16share a same data line18, so that the number of the data lines18can be reduced, and the number of the source chips can be accordingly reduced. Therefore, the manufacturing cost of the display panel is reduced due to the number of source chips used by the display panel being reduced. In addition, a dummy line20is disposed between each two adjacent data lines18to reduce crosstalk resulting from electromagnetic interference (EMI) caused in pixels corresponding to the two adjacent columns between the two adjacent data lines18in the display panel. The dummy line20receives a data signal having polarity opposite that of the data line18, to improve display quality of the panel.

As shown inFIG. 3, in the circuit layout of the aforementioned prior art, a common line22is an opaque metal layer disposed under an electrode layer24in a transmissive region. Due to the common line22partially shielding the electrode layer24, area of the transmissive region of an electrode layer24is reduced, and aperture ratio of the whole display panel is reduced.

SUMMARY OF THE INVENTION

It is one of the objectives of the present invention to provide a pixel electrode structure with high display quality by disposing the common line between the adjacent gate lines to reduce the number of the common lines and to raise the aperture ratio of the pixel in the display panel.

It is another one of the objectives of the present invention to provide a pixel electrode structure with high display quality by connecting the common line to the dummy line to have a better stability of the common voltage signal. When the data line is disconnected, a method of laser repairing can be performed to detour the data line to the dummy line for enhancing yields.

According to a preferred embodiment of the present invention, a pixel electrode structure with high display quality is provided. The pixel electrode structure includes a transparent substrate. A data line, a common line, a first array pixel, and a second array pixel are disposed on the transparent substrate. The first array pixel includes a first thin film transistor, a first pixel electrode, and a first gate line. The common line is disposed at a lateral side of the first gate line. The second array pixel includes a second thin film transistor, a second pixel electrode, and a second gate line. The common line is also disposed at a lateral side of the second gate line. In addition, a first via hole and a second via hole are respectively disposed on common line and in contact with an extending portion of the first thin film transistor and an extending portion of the second thin film transistor. A dummy line is disposed at a side of the data line, and a third via hole is disposed on both the dummy line and the common line.

DETAILED DESCRIPTION

In the liquid crystal display panel of the present invention, a pixel electrode structure with high displaying quality by connecting a dummy line to a common line, wherein the common line is connected to a common electrode. Please refer to a circuit layout of a liquid crystal display panel according to a first embodiment shown inFIG. 4andFIG. 5.FIG. 5is an enlarged schematic diagram of a pixel electrode structure marked by a dotted block shown inFIG. 4. Components in the dotted block include two pixel electrodes formed by an electrode layer50, two thin film transistors26,28and a circuit layout surrounding the thin film transistors26,28. The pixel electrode structure in the dotted block inFIG. 4is taken as a unit, and the pixel electrode structures are connected to each other through gate lines30, data lines32, dummy lines34, and common lines36. Because the pixel electrode structures on the display panel are arranged in a matrix, the pixel electrode structures in a same column share the same data line32and the same dummy line34, and the pixel electrode structures in a same row share the same gate line30and the same common line36. The connecting relations and the relative positions of all components in each pixel electrode structure are the same, and one pixel electrode structure is taken as an example in the following description.

In order to describe embodiments clearly, please refer toFIG. 5andFIG. 6together in the following description.FIG. 6is a cross-sectional view of the circuit layout structure, taken along a line A-A′ ofFIG. 5, andFIG. 6may represent stacking relationships of the components inFIG. 5.FIG. 5shows a pixel electrode structure including a transparent substrate38, a first array pixel, and a second array pixel disposed on the transparent substrate38. The first array pixel includes a first thin film transistor26, a first pixel electrode33and a first gate line60, and the second array pixel includes a second thin film transistor28, a second pixel electrode35and a second gate line62. The first array pixel and the second array pixel are formed by a first metal layer40, an insulating layer42, a semiconductor layer44, a second metal layer46, a passivation layer48and an electrode layer50. The insulating layer42and the passivation layer48include an insulating material. The insulating material of the passivation layer48and the insulating layer42includes silicon nitride. A material of the electrode layer50includes indium tin oxide (ITO). The first pixel electrode33and the second pixel electrode35, which are respectively connected to the first thin film transistor26and the second thin film transistor28, are formed by the electrode layer50.

The first metal layer40is disposed on the transparent substrate38to form a first gate electrode56of the first thin film transistor26, a second gate electrode58of the second thin film transistor28, a first gate line60, a second gate line62and a common line64disposed between the first gate line60and the second gate line62. When the first metal layer40is formed, the first gate line60is formed to be connected to the gate electrode56of the first thin film transistor26, and the second gate line62is formed to be connected to the gate electrode58of the second thin film transistor28. After forming the first metal layer40, the insulating layer42is formed on the first metal layer40, and the insulating layer42disposed on the gate electrode56of the first thin film transistor26and disposed on the gate electrode58of the second thin film transistor28respectively serves as a gate insulating layer. The semiconductor layer44is disposed on the insulating layer42, and the semiconductor44includes a two-layer structure with a top layer and a bottom layer. The bottom layer is an amorphous silicon (a-Si) layer52, and is directly disposed on the insulating layer42. The top layer is an ohmic contact layer54of the amorphous silicon doped with n-type doping (n+a-Si). A second metal layer46is disposed on the ohmic contact layer54and on the insulating layer42to form a source electrode66and a drain electrode70of the first thin film transistor26, a source electrode68and a drain electrode72of the second thin film transistor28, a data line78, and a dummy line74between the two data lines78. The data line78connects the source electrode66of the first thin film transistor26and the source electrode68of the second thin film transistor28, and the first thin film transistor26and the second thin film transistor28are disposed at two opposite sides of the data line78. The first thin film transistor26is disposed at one lateral side of the first gate line60and the second gate line62, and the second thin film transistor28is disposed at the other lateral side of the first gate line60and the second gate line62opposite the one lateral side of the first gate line60and the second gate line62. The source electrode66and the drain electrode70of the first thin film transistor26are disposed on the gate electrode56of the first thin film transistor26, and the source electrode68and the drain electrode72of the second thin film transistor28are disposed on the gate electrode58of the second thin film transistor28. The amorphous layer52and the ohmic contact layer54are disposed under the source electrode66and the drain electrode70of the first thin film transistor26and the source electrode68and the drain electrode72of the second thin film transistor28. The dummy line74and the data line78are disposed parallel to each other, and the dummy line74and the data line78are perpendicular to the common line64, the first gate line60and the second gate line62.

Furthermore, according toFIG. 5, the first pixel electrode33is disposed at a lateral side of the second gate line62, and overlaps the common line64and the second gate line62respectively to form a corresponding first overlapping area and a second overlapping area. The second overlapping area disposed at one lateral side of the common line64is less than the first overlapping area between the first gate line60and the second gate line62. The second pixel electrode35is disposed at a lateral side of the first gate line60, and overlaps the common line64and the first gate line60respectively to form a third overlapping area and a fourth overlapping area. The fourth overlapping area disposed at the other lateral side of the common line64is less than the third overlapping area between the first pixel electrode60and the second pixel electrode62.

Please refer toFIG. 5,FIG. 6, andFIG. 7together in the following description.FIG. 7is a cross-sectional view of the circuit layout structure, taken along a line B-B′ ofFIG. 5. The ohmic contact layer54and the second metal layer46are covered with the passivation layer48. The passivation layer48has a first via hole80and a second via hole81that are respectively disposed on both a portion of the drain electrode70and a portion of the semiconductor layer44of the first thin film transistor26, and disposed on both a portion of the drain electrode72and a portion of the semiconductor layer44of the second thin film transistor28, and the passivation layer48has a third via hole82disposed on both a portion of the dummy line74and a portion of the common line64. A portion of the dummy line74is covered with the passivation layer48, and the insulating layer42disposed thereunder is penetrated through by the third via hole82. When the passivation layer48is etched to form the first via hole80and the second via hole81, the semiconductor layer44and the insulating layer42corresponding to the first via hole80and the second via hole81can not be etched through. Accordingly, depth of the first via hole80and depth of the second via hole81may only reach the semiconductor layer44. The first via hole80is the unconnected part of the passivation layer48shown in the cross-sectional view ofFIG. 6, and the third via hole82is the unconnected part of the passivation layer48and the unconnected part of the insulating layer42shown in the cross-sectional view ofFIG. 7.

The electrode layer50is disposed on the passivation layer48. The electrode layer50may be in contact with the drain electrode70and the semiconductor layer44of the corresponding first thin film transistor26through the first via hole80. The electrode layer50may also be in contact with the drain electrode72and the semiconductor layer44of the corresponding second thin film transistor28through the second via hole81. And, the electrode layer50may further be in contact with the dummy line74and the common line64through the third via hole82. As shown inFIG. 6, due to the first via hole80, the second metal layer46(regarded as the drain electrode70) and the semiconductor layer44are exposed, and can be in contact with the electrode layer50. As shown inFIG. 7, due to the third via hole82, the second metal layer46(regarded as the dummy line74) and the first metal layer40(regarded as the common line64) are also exposed, and both can be in contact with the electrode layer50. The electrode layer50here is an independent electrode layer. The independent electrode layer may electrically connect the dummy line74to the common line64.

In addition, a portion of the electrode layer50is in contact with the drain electrode of the thin film transistor, and an overlapping part of the portion of the electrode layer50, the first metal layer40, and the second metal layer46forms a storage capacitor. For example, an overlapping part of a portion of the drain electrode70extending to the common line64, the common line64, and the electrode layer50forms a storage capacitor of the first thin film transistor26. Also, an overlapping part of a portion of the drain electrode72of the second thin film transistor28extending to the common line64, the common line64, and the electrode layer50forms a storage capacitor of the second thin film transistor28.

Furthermore, the electrode layer50at the lateral side of the first thin film transistor26does not overlap the first gate line60which is disposed at the lateral side of the drain electrode70of the first thin film transistor26. The electrode layer50at the lateral side of the second thin film transistor28does not overlap the second gate line62which is disposed at the lateral side of the drain electrode72of the second thin film transistor28. As a result, a light-shielding layer, such as black matrix, may be disposed between the color filters corresponding to the edge of the electrode layer at the lateral side of each thin film transistor. Light leakage induced by misalignment of liquid crystal molecules near the edge of each pixel will be shielded by the light-shielding layer when the display panel is utilized to form a liquid crystal display device. Accordingly, the adjacent pixels will not have color crosstalk.

As shown inFIG. 4, the liquid crystal display panel manufactured by using the aforementioned circuit layout can be compared with the liquid crystal display panel of the prior art inFIG. 3. Two electrode layers50between the adjacent gate lines30and the adjacent data lines32, respectively, form display regions of two pixels. In the design of the present invention, the common line36may not shield an area of the transmissive region of the electrode layer50. Further, for a same number of thin film transistors, the number of common lines36used inFIG. 4is less than the number used inFIG. 3. For example, two common lines are required in the present invention for eight thin film transistors, but three common lines are required in the prior art. In other words, the aperture ratio of the pixel can be raised according to the aforementioned design of the present invention.

Next, please refer to a circuit layout of a second embodiment shown inFIG. 8andFIG. 9. The electrode layer50at a lateral side of the first thin film transistor26partially overlaps the first gate line60which is disposed at a lateral side of the drain electrode70of the first thin film transistor26. The electrode layer50at a lateral side of the second thin film transistor28partially overlaps the second gate line62which is disposed at a lateral side of the drain electrode72of the second thin film transistor28. For this reason, the light shielding layer is not required to be disposed between the color filters corresponding to the edge of the electrode layer at a lateral side of each thin film transistor. The area of the storage capacitor may also be increased in this design to reduce the probability of flicker.

Please refer to an equivalent circuit diagram of a liquid crystal display panel of the present invention inFIG. 10. As shown inFIG. 10, the equivalent circuit of the liquid crystal display panel of the present invention includes a plurality of gate lines86parallel to each other and a plurality of data lines84parallel to each other. The gate lines86include a first gate line862and a second gate line864, and are perpendicular to the data lines84and are parallel to a plurality of common lines88. The data lines84include a first data line842. The common lines88include a first common line882.

The liquid crystal display panel of the present invention further includes a plurality of dual-gate pixel units92arranged in a matrix and connected to each other through the data lines84, the gate lines86and the common lines88. Each dual-gate pixel unit92is electrically connected to a data line84, two gate lines86and a common line88. The dual-gate pixel units92in a same column share a same data line84, and the dual-gate pixel units92in a same row share a same gate line86and a same common line88. The components of each dual-gate pixel unit92have the same connecting relationships and relative positions. The present invention takes one dual-gate pixel unit92as an example, and the connecting relationships and the relative positions among the first gate line862, the second gate line864, the first data line842, the first common line882and a dual-gate pixel unit92are mentioned in the following description.

Please refer toFIG. 10andFIG. 11together. Each dual-gate pixel unit92includes a first thin film transistor922, a first liquid crystal capacitor925and a first storage capacitor926correspondingly connected to the first thin film transistor922. Each dual-gate pixel unit92further includes a second thin film transistor924, and a corresponding second liquid crystal capacitor927and a second storage capacitor928correspondingly connected to the second thin film transistor924. The first thin film transistor922and the corresponding first liquid crystal capacitor925and the corresponding first storage capacitor926connected to the first thin film transistor922are disposed at one lateral side of the first gate line862and the second gate line864, and the second thin film transistor924and the corresponding second liquid crystal capacitor927and the corresponding second storage capacitor928connected to the second thin film transistor924are disposed at the other lateral side of the first gate line862and the second gate line864opposite to the one lateral side of the first gate line862and the second gate line864. The first thin film transistor922and the corresponding first liquid crystal capacitor925and the corresponding first storage capacitor926connected to the first thin film transistor922and the second thin film transistor924and the corresponding second liquid crystal capacitor927and the corresponding second storage capacitor928connected to the second thin film transistor924are respectively disposed at two opposite sides of the first data line842. The first gate line862and the second gate line864are disposed at two opposite sides of the first common line882, and the first common line882is disposed at a region between the first gate line862and the second gate line864.

A gate electrode of the first thin film transistor922is electrically connected to the first gate line862, and a source electrode of the first thin film transistor922is electrically connected to the first data line842. A drain electrode of the first thin film transistor922is electrically connected to an end of the first liquid crystal capacitor925and an end of the first storage capacitor926. The other end of the first liquid crystal capacitor925is connected to a common electrode of a color filter for receiving a first common voltage signal, and the other end of the first storage capacitor926is connected to the first common line882. The first data line842and the first common line882respectively transfer a data signal and a second common voltage signal to the first thin film transistor922, and the first gate line862controls the first thin film transistor922to receive the data signal, so that charging/discharging of the first liquid crystal capacitor925is controlled. The first storage capacitor926is utilized to hold a voltage drop between two ends of the first liquid crystal capacitor925in order to prevent current leakage of the first liquid crystal capacitor925.

Similarly, a gate electrode of the second thin film transistor924is electrically connected to the second gate line864, and a source electrode of the second thin film transistor924is electrically connected to the first data line842. A drain electrode of the second thin film transistor924is connected to an end of the second liquid crystal capacitor927and an end of the second storage capacitor928. The other end of the second liquid crystal capacitor927is connected to the common electrode of the color filter for receiving the first common voltage signal, and the other end of the second storage capacitor928is connected to the first common line882. The first data line842and the first common line882respectively transfer the data signal and the second common voltage signal to the second thin film transistor924, and the second gate line864controls the second thin film transistor924to receive the data signal, so that charging/discharging of the second liquid crystal capacitor927is controlled. The second storage capacitor928is used to hold a voltage drop between two ends of the second liquid crystal capacitor927in order to prevent current leakage of the second liquid crystal capacitor927.

The liquid crystal display panel further includes a plurality of dummy lines90. Each one of the dummy lines90is respectively disposed between two adjacent dual-gate pixel units92in the same row and is connected to the common line88. In the process of transferring the second common voltage signal via the second common line88, the second common voltage signal in the center region of the liquid display panel is unstable. The common lines88are connected to the dummy lines90to improve the stability of the second common voltage signal.

FIG. 10can be compared withFIG. 2of the prior art. For the same number of thin film transistors, the number of common lines inFIG. 10is less than that inFIG. 2, which is a similar result as when comparing circuit layouts. In other words, the design of the present invention raises the aperture ratio of the pixel. The design of the circuit layout structure may be applied to pixel design for vertical alignment type (VA type), twisted nematic type (TN type), and in-plane switching type (IPS type) liquid crystal structures, or to pixel design of organic film.

Please refer toFIG. 10again. Operation of the liquid crystal display panel of the present invention is described in the following. First, each common line88and each data line84respectively transfers a first common voltage signal and a data signal to the storage capacitor98connected to the common line88and the thin film transistor94connected to the data line84, and each liquid crystal capacitor96receives a first common voltage signal. Since each common line88is respectively connected to the dummy line90, the second common voltage signal in each common line88is rather stable. Next, the gate lines86from top to bottom respectively control the corresponding thin film transistors94in each row to receive the data signal, so that charging/discharging of the liquid crystal capacitor96is controlled. Also, the storage capacitor98connected to the liquid crystal capacitor96is utilized to hold the voltage drop between two ends of the liquid crystal capacitor96.

Finally, please refer toFIG. 12. The design of the circuit structure of the liquid crystal display panel described above has another advantage. When the data line842is disconnected, the lines may be cut off by a laser at locations marked by square blocks (dotted lines), and the first data line842and the common line88can be connected to each other by a laser at a location marked by an oval (dotted line). Accordingly, the first dummy line902can be utilized to take the place of the disconnected data line842, and product yield can be improved.

In conclusion, the present invention not only increases the aperture ratio of the pixel in the panel, but also provides better stability in the common voltage signal by electrically connecting the common line to the dummy line.