Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereof

A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.

FIELD

The present disclosure relates generally to the field of semiconductor devices and specifically to vertical field effect transistors including multiple gate electrodes, and methods of making the same.

BACKGROUND

A two-dimensional array of vertical field effect transistors can be employed as access transistors for vertical conductive lines such as local bit lines of a three-dimensional memory device. Ideally, vertical field effect transistors need to provide a high on-current and a low off-current with a well-defined threshold voltage. Typical vertical field effect transistors have degradation in performance due to various factors, which include high leakage current and low on-current due to crystalline defects and limitation on the spatial extent of the depletion zone. Vertical field effect transistors providing superior performance are desired.

SUMMARY

According to an aspect of the present disclosure, a semiconductor device comprising at least one instance of a vertical field effect transistor is provided. Each instance of the field effect transistor comprises: at least one inner gate electrode extending along a first horizontal direction; a pair of inner gate dielectrics contacting a respective sidewall of the at least one inner gate electrode and vertically extending above topmost edges of the at least one inner gate electrode; a pair of vertical semiconductor channel strips, each including a first sidewall contacting a respective one of the pair of inner gate dielectrics, a second sidewall that is parallel to the first sidewall, and two transverse sidewalls each adjoining the first sidewall and the second sidewall; a pair of outer gate dielectrics contacting a respective one of the pair of vertical semiconductor channel strips; a pair of outer gate electrodes contacting a respective one of the pair of outer gate dielectrics; at least one bottom active region contacting the pair of vertical semiconductor channel strips and electrically shorted to a bottom electrode line; and a pair of top active regions contacting a top portion of a respective one of the pair of vertical semiconductor channel strips and electrically shorted to each other via a conductive structure.

According to another aspect of the present disclosure, a method of forming a semiconductor device comprising at least one instance of a vertical field effect transistor is provided. Matrix rail structures are formed over a substrate. Each of the matrix rail structures includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A plurality of vertical semiconductor channel strips is formed on portions of the lengthwise sidewalls of the matrix rail structures. Each of the plurality of vertical semiconductor channel strips includes a first sidewall contacting a respective portion of the lengthwise sidewalls of the at least one matrix rail structure, a second sidewall that is parallel to the first sidewall, and two transverse sidewalls each adjoining the first sidewall and the second sidewall. A laterally-undulating gate dielectric layer is formed on the second sidewall of the plurality of vertical semiconductor channel strips and on additional portions of the lengthwise sidewalls of the matrix rail structures. At least one laterally-undulating gate electrode line is formed between each neighboring pair of matrix rail structures. Each sidewall of the plurality of vertical semiconductor channel strips is physically contacted by a dielectric surface of a combination of portions of the laterally-undulating gate dielectric layer and a respective straight-sidewalled gate dielectric.

DETAILED DESCRIPTION

As discussed above, the present disclosure is directed to vertical field effect transistors including multiple gate electrodes, and methods of making the same, the various aspects of which are described below. The embodiments of the disclosure can be employed to form various semiconductor devices employing a two-dimensional array of vertical field effect transistors as access transistors such as three-dimensional monolithic memory array devices comprising ReRAM devices.

The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element.

As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and/or may have one or more layer thereupon, thereabove, and/or therebelow.

As used herein, a “field effect transistor” refers to any semiconductor device having a semiconductor channel through which electrical current flows with a current density modulated by an external electrical field. As used herein, an “active region” refers to a source region of a field effect transistor or a drain region of a field effect transistor. A “top active region” refers to an active region of a field effect transistor that is located above another active region of the field effect transistor. A “bottom active region” refers to an active region of a field effect transistor that is located below another active region of the field effect transistor. As used herein, a first material is removed “selective to” a second material if the rate of removal of the first material is at least twice (such as at least 10 times) the removal rate of the second material.

As used herein, a “line” or a “line structure” refers to a structure in which the structure predominantly extends along a lateral direction with, or without, one or more lateral jogs. The general direction along which a line extends is referred to as a “lengthwise” direction of the line. A line or a line structure may, or may not, have a uniform vertical cross-sectional shape within vertical planes perpendicular to the lengthwise direction of the line or the line structure.

As used herein, a “rail” or a “rail structure” refers to a structure that laterally extends along a lengthwise direction by a greater distance than the maximum dimension of the structure along a widthwise direction with a same vertical cross-sectional shape along vertical planes that are perpendicular to the lengthwise direction. Thus, a rail or a rail structure is a line having a uniform vertical cross-sectional shape along vertical planes that are perpendicular to the lengthwise direction of the line irrespective of the location of the vertical cross-section.

As used herein, a “laterally-undulating sidewall” or an “undulating sidewall” refers to at least one sidewall (i.e., a sidewall or a set of sidewalls) that includes lateral shifts from a general propagation direction of the sidewall in a plan view such that the lateral shifts alternate between two opposite lateral directions that are perpendicular to the general propagation direction. As used herein, a “laterally-undulating” structural element or an “undulating” structural element refers to a structural element that includes a “laterally-undulating sidewall.”

As used herein, a “straight-sidewalled” structural element or a “straight” structural element refers to a structural element including sidewalls none of which is a laterally-undulating sidewall. Thus, a rail or a rail structure may be straight-sidewalled. A laterally undulating element is not a rail or a rail structure.

As used herein, an element has a “modulation” in width or has a “modulating width” if the width of the element varies along the lengthwise direction of the element.

Referring toFIGS. 1A-1C, a first exemplary structure according to a first embodiment of the present disclosure is provided, which is an in-process structure for forming at least one vertical field effect transistor such as a two-dimensional array of field effect transistors. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

The first exemplary structure includes a substrate6, which includes an insulating layer at an upper portion thereof. In one embodiment, the substrate6can be a stack of at least two material layers such as a stack of an underlying substrate material layer and an overlying substrate insulating layer. The substrate material layer can be a semiconductor material layer, a conductive material layer, or an insulating material layer that can provide structural support to the overlying structures, and may have a thickness greater than 50 microns, and typically in a range between 300 microns and 3 mm In one embodiment, the substrate material layer can be a semiconductor wafer, such as a silicon wafer as known in the art. The substrate insulating layer can include an insulating material, and can have a thickness in a range from 100 nm to 3 microns, although lesser and greater thicknesses can also be employed.

In case the substrate material layer includes a semiconductor material, peripheral semiconductor devices for operation of a memory array device can be formed in, or on, the substrate material layer. For example, sense amplifiers, input-output (I/O) circuitry, control circuitry, and any other necessary peripheral circuitry can be formed on, or in, the substrate material layer. Additional devices that can be formed in, or on, the substrate material layer include, but are not limited to, bottom electrode line select transistors for selecting bottom electrode lines to be activated, and/or word line select transistor for selecting word lines to be activated.

Bottom electrode lines10are formed over the substrate6. The bottom electrode lines10are parallel electrically conductive lines that are laterally spaced apart in a first horizontal direction hd1, and extending in a second horizontal direction hd2. The bottom electrode lines10can be formed, for example, by depositing at least one conductive material layer, and patterning the at least one conductive material layer employing a combination of lithographic methods and an anisotropic etch. The at least one conductive material layer can include, for example, at least one elemental metal (such as W, Co, Cu, and Al), a conductive doped semiconductor material, an intermetallic alloy including at least two elemental metals, a conductive metallic nitride, or a conductive metallic carbide. For example, the at least one conductive material layer can include a metallic barrier layer (such as a layer of TiN, TaN, or WN) and a metal layer (such as a layer of W, Ti, Ta, Cu, Al, or an alloy thereof).

In one embodiment, each bottom electrode line10can include a vertical stack of a metallic bottom electrode line portion10A and a doped semiconductor bottom electrode line portion10B. The type of doping of the doped semiconductor bottom electrode line portions10B is herein referred to as a first conductivity type, which can be p-type or n-type. For example, each metallic bottom electrode line portion10A can include a metallic nitride material (such as TiN), an elemental metal (such as W, Co, Ni, Ti, Ta, Ru, or Al), or a combination thereof. Each doped semiconductor bottom electrode line portion10B can include doped polysilicon. The dopant concentration in the doped semiconductor bottom electrode line portions10B can be in a range from 1.0×1019/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed.

The thickness of each metallic bottom electrode line portion10A can be in a range from 3 nm to 100 nm, although lesser and greater thicknesses can also be employed. The thickness of each doped semiconductor bottom electrode line portion10B can be in a range from 10 nm to 300 nm, although lesser and greater thicknesses can also be employed.

The space between the bottom electrode lines10can be filled with a dielectric material (such as silicon oxide). The dielectric material can be subsequently planarized to remove excess portions from above a horizontal plane including the top surfaces of the bottom electrode lines10to form bottom electrode isolation structures12. Each bottom electrode lines10and each bottom electrode isolation structures12can extend along the second horizontal direction hd2. A one-dimensional array of the bottom electrode lines10and the bottom electrode isolation structures12can extend along the first horizontal direction hd2with a periodicity that is equal to the sum of the width of a bottom electrode line10and the width of a bottom electrode isolation structure12.

Alternatively, the one-dimensional array of the bottom electrode lines10and the bottom electrode isolation structures12may be formed by depositing a dielectric material layer, forming trenches extending along the second horizontal direction hd2and laterally spaced from one another along the first horizontal direction hd1, and filling the trenches with at least one conductive material to form the bottom electrode lines10therein. Thus, a laterally alternating stack of bottom electrode lines10and bottom electrode isolation structures12can be formed over the substrate6.

Referring toFIGS. 2A and 2B, a layer stack of a first dielectric material layer and a second dielectric material layer can be formed over the laterally alternating stack of bottom electrode lines10and bottom electrode isolation structures12, and can be patterned to form dielectric rail structures (21,23) laterally extending along the first horizontal direction hd1. For example, the first dielectric material layer can be a silicon oxide layer having a thickness that is on the order of the channel length of the vertical field effect transistors to be subsequently formed. In one embodiment, the thickness of the first dielectric material layer can be in a range from 50 nm to 2,000 nm, although lesser and greater thicknesses can also be employed. The second dielectric material layer can be a silicon nitride layer having a thickness that is on the order of the height of the top active regions to be subsequently formed. In one embodiment, the thickness of the second dielectric material layer can be in a range from 5 nm to 100 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer can be applied over the second dielectric material layer, and can be lithographically patterned with a periodic line and space pattern, i.e., by lithographic exposure and development. Each line pattern in the developed photoresist material can laterally extend along the first horizontal direction hd1, which may be perpendicular to the lengthwise direction of the bottom electrode lines10which is the second horizontal direction. At least one anisotropic etch process can be performed to transfer the pattern of the developed photoresist material portions through the second dielectric material layer and the first dielectric material layer. The bottom electrode lines10may be employed as an etch stop layer and/or as an end point detection layer.

Each remaining portion of the second dielectric material layer constitutes an upper dielectric rail structure23. Each remaining portion of the first dielectric material layer constitutes a lower dielectric rail structure21. A vertical stack of a lower dielectric rail structure21and an upper dielectric rail structure23constitutes a dielectric rail structure (21,23), which laterally extends along the first horizontal direction hd1. In one embodiment, each dielectric rail structure (21,23) can have a uniform width throughout. In one embodiment, the lower dielectric rail structures21can include silicon oxide, and the upper dielectric rail structures23can include silicon nitride. The width of each dielectric rail structure (21,23) can be in a range from 30 nm to 500 nm, although lesser and greater widths can also be employed.

Referring toFIGS. 3A and 3B, a dielectric spacer25can be formed on each dielectric rail structure (21,23). The dielectric spacer25includes a different dielectric material than the dielectric material of the lower dielectric rail structures21. For example, the dielectric spacer25can include silicon nitride. The dielectric spacers25can be formed by conformal deposition of a dielectric material layer (for example, by chemical vapor deposition) and a subsequent anisotropic etch that removes horizontal portions of the conformal dielectric material layer. Each remaining vertical portion of the dielectric material layer constitutes a dielectric spacer25. The thickness of each dielectric spacer25can be in a range from 3 nm to 60 nm, although lesser and greater thicknesses can also be employed. Each contiguous combination of a dielectric rail structure (21,23) and a dielectric spacer25constitutes a matrix rail structure (21,23,25).

The matrix rail structures (21,23,25) laterally extend along the first horizontal direction hd1. Each matrix rail structure (21,23,25) includes a pair of lengthwise sidewalls252that extend along the first horizontal direction hd1. Each matrix rail structure (21,23,25) is at least partially subsequently replaced with a set of at least one gate electrode rail extending along the first horizontal direction hd1and straight-sidewalled gate dielectrics, which can be portions of a straight-sidewalled gate dielectric layer that contact sidewalls of vertical semiconductor channel strips to be subsequently formed.

Referring toFIGS. 4A and 4B, a semiconductor channel material layer30L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The semiconductor channel material layer30L can be formed over each matrix rail structure (21,23,25) and on the entirety of the lengthwise sidewalls252of each matrix rail structure (21,23,25). The semiconductor channel material layer30L includes a semiconductor material that is subsequently employed for vertical semiconductor channel strips of field effect transistors. For example, the semiconductor channel material layer30L can include polysilicon, amorphous silicon (which can be converted into polysilicon in a subsequent anneal process), a polycrystalline or amorphous silicon-germanium alloy, a polycrystalline III-V compound semiconductor material (such as polycrystalline GaN), or any other semiconductor material.

In one embodiment, the semiconductor channel material layer30L may include a layer stack of at least two semiconductor materials such as a layer of a silicon-germanium alloy including germanium at an atomic concentration in a range from 20% to 40% and a polycrystalline cap layer. In another embodiment, the semiconductor channel material layer30L can include a hydrogen-doped semiconductor material such as hydrogen-doped polysilicon. The atomic percentage of hydrogen atoms in the hydrogen-doped semiconductor material may be in a range from 2% to 10%. If present, hydrogen atoms in the semiconductor material of the semiconductor channel material layer30L can remove traps through dangling bonds, and enhance mobility of charge carriers therein. The thickness of the semiconductor channel material layer30L can be uniform throughout the entirety thereof, and can be in a range from 2 nm to 30 nm, such as from 3 nm to 10 nm, although lesser and greater thicknesses can also be employed. The thickness of the semiconductor channel material layer30L may be selected to enable full depletion of vertical semiconductor channel strips during operation of the vertical field effect transistors.

The semiconductor channel material layer30L can have a doping of second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the semiconductor channel material layer30L can be in a range from 1.0×1015/cm3to 1.0×1018/cm3, although lesser and greater dopant concentrations can also be employed.

Referring toFIGS. 5A and 5B, a cap material layer31can be formed over the semiconductor channel material layer30L by a conformal or a non-conformal deposition process. The cap material layer31can include a material that can prevent outdiffusion of electrical dopants therethrough during a subsequent anneal process. For example, the cap material layer31can include a diffusion barrier dielectric material such as silicon nitride. The thickness of the cap material layer31can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed.

An anneal process can be performed to diffuse electrical dopants from the doped semiconductor bottom electrode line portions10B into bottom portions of the semiconductor channel material layer30L (which is a semiconductor material portion) to form bottom active regions32. The bottom active regions32have a doping of the same conductivity type as the doped semiconductor bottom electrode line portions10B, i.e., the first conductivity type. The dopant concentration of the bottom active regions32can be in a range from 1.0×1019/cm3to 1.0×1020/cm3, although lesser and greater dopant concentrations can also be employed. The vertical portions of the semiconductor channel material layer30L include vertical semiconductor channel strips of field effect transistors to be formed. The temperature and the duration of the anneal process can be selected to optimize the location of the p-n junction between the bottom active regions32and the portions of the semiconductor channel material layer30L that retain the doping of the second conductivity type.

Referring toFIGS. 6A and 6B, at least one fill material is deposited in the line trenches between the matrix rail structures (21,23,25). The at least one fill material may include a dielectric material such as silicon oxide, or a semiconductor material such as germanium or polysilicon. The at least one fill material is subsequently planarized to remove portions that are located above a horizontal plane including the top surfaces of the upper dielectric rail structures23. For example, a recess etch or chemical mechanical planarization (CMP) may be employed to planarized the at least one fill material. Each remaining portion of the at least one fill material constitutes a fill material line structure33R.

Top portions of the cap material layer31and the semiconductor channel material layer30L can be removed from above the a horizontal plane including the top surfaces of the upper dielectric rail structures23by the planarization process. Each remaining portion of the cap material layer31L constitutes a cap material line structure31R. Each contiguous pair of a cap material line structure31R and a fill material line structure33R constitutes a sacrificial fill line structure (31R,33R). The matrix rail structures (21,23,25) are laterally spaced apart along the second horizontal direction hd2by the sacrificial fill line structures (31R,33R). Each remaining portion of the semiconductor channel material layer30L laterally extends along the first horizontal direction hd1, and is herein referred to as a semiconductor channel material line30R. The top surface of each semiconductor channel material line30R can be in the same horizontal plane as the top surface of the upper dielectric rail structures23.

Referring toFIGS. 7A-7C, etch masks47can be formed over the matrix rail structures (21,23,25) and the sacrificial fill line structures (31R,33R). The plurality of etch masks47can laterally extend along the second horizontal direction hd2, and can be laterally spaced apart among one another along the first horizontal direction hd1, and can extend over the remaining portions of the semiconductor channel material layer30L, i.e., over the semiconductor channel material lines30R. Each etch mask47can have a uniform thickness throughout. In one embodiment, the etch masks47can be patterned portions of a photoresist layer. In this case, the etch masks47can be formed, for example, by applying and lithographically patterning a photoresist layer. Alternatively, the etch masks47can be a hard mask layer that is patterned by transfer of a pattern in a patterned photoresist layer by an anisotropic etch.

The width of each etch mask47can be selected to be on the order of the width of vertical semiconductor channel strips to be subsequently formed underneath the etch mask47. The spacing between each neighboring pair of etch masks47can be on the order of the spacing between a neighboring pair of vertical semiconductor channel strips to be subsequently formed. In one embodiment, the width of each etch mask47can be the same, and can be in a range from 20 nm to 600 nm, although lesser and greater widths can also be employed. In one embodiment, the spacing between neighboring pairs of etch mask47can be the same, and can be in a range from 20 nm to 600 nm, although lesser and greater spacings can also be employed.

Subsequently, remaining portions of the at least one fill material (i.e., the fill material line structures33R) and remaining portions of the semiconductor channel material layer30L (i.e., the semiconductor channel material lines30R) are removed from within areas that are not covered by the plurality of etch masks47. Specifically, an anisotropic etch can be performed to remove the material of the fill material line structures33R selective to the dielectric spacers25and the upper dielectric rail structures23employing the etch masks47semiconductor channel material layer structure. Isolation cavities49are formed in each volume of the fill material line structures33R that are not covered by the etch masks47. In one embodiment, the anisotropic etch process can be selective to the material of the cap material line structures31R. In one embodiment, the cap material line structures31R can include silicon nitride, the fill material line structures33R can include doped or undoped silicon oxide or organosilicate glass, and the anisotropic etch process can remove unmasked portions of the fill material line structures33R selective to the material of the cap material line structures31R. Each remaining discrete portion of the fill material line structures33R can have a substantially rectangular pillar shape, and is herein referred to as a fill material pillar structure33, as shown inFIG. 7A.

Subsequently, a first isotropic etch process can be performed to remove portions of the cap material line structures31R that are physically exposed to the isolation cavities49, i.e., to remove portions of the cap material line structures31R that are not covered by the etch masks47. For example, if the cap material line structures31R include silicon nitride, a wet etch employing hot phosphoric acid can be employed to remove portions of the cap material line structures31R located between areas covered by the etch masks47. Each remaining discrete portion of the cap material line structures31R can have a horizontal portion adjoined by two vertical portions, and is herein referred to as a cap material liner portion31.

A second isotropic etch process can be performed to remove portions of the semiconductor channel material lines30R that are physically exposed to the isolation cavities49, i.e., to remove portions of the semiconductor channel material lines30R that are not covered by the etch masks47. For example, if the semiconductor channel material lines30R include polysilicon, a wet etch employing a KOH solution can be employed to remove portions of the semiconductor channel material lines30R located between areas covered by the etch masks47. Each remaining discrete portion of the semiconductor channel material lines30R constitutes a vertical semiconductor channel strip30that extends between the bottom active regions32and a bottom surface of the etch masks47.

Portions of the bottom active regions32that are not covered by the etch masks47can be collaterally removed during the second isotropic etch process. Each bottom active region32located between a neighboring pair of matrix rail structures (21,23,25) can be divided into a plurality of bottom active regions32connecting a respective pair of vertical semiconductor channel strips30. A pair of vertical semiconductor channel strips30can contact a common bottom active region32.

Thus, the semiconductor channel material layer30L can be patterned into a plurality of vertical semiconductor channel strips30between each neighboring pair of matrix rail structures (21,23,25). Instances of the plurality of vertical semiconductor channel strips30can be repeated between neighboring pairs of matrix rail structures (21,23,25) along the second horizontal direction hd2to form a two-dimensional array of vertical semiconductor channel strip pairs31. Sidewalls of each vertical semiconductor channel strip30, each cap material liner portion31, each fill material pillar structure33, and each bottom active region32can be physically exposed to the isolation cavities49.

A plurality of vertical semiconductor channel strips30are formed on portions of the lengthwise sidewalls252of the matrix rail structures (21,23,25). As shown inFIG. 7A, each of the plurality of vertical semiconductor channel strips30includes a first sidewall301contacting a respective portion of the lengthwise sidewalls252of the matrix rail structures (21,23,25), a second sidewall302that is parallel to the first sidewall301, and two transverse sidewalls each adjoining the first sidewall301and the second sidewall302.

Referring toFIGS. 8A-8D, the etch masks47can be removed selective to the vertical semiconductor channel strips30, for example, by ashing. Remaining portions of the at least one fill material (i.e., the fill material pillar structures33) and remaining portions of the cap material layer31L (i.e., the cap material liner portions31) are removed. An isotropic etch or an anisotropic etch can be performed to remove the material of the fill material pillar structures33selective to the vertical semiconductor channel strips30. For example, if the fill material pillar structures33include silicon oxide, a wet etch employing hydrofluoric acid can be performed to remove the fill material pillar structures33. Subsequently, an isotropic etch can be performed to remove the cap material liner portions31selective to the vertical semiconductor channel strips30. For example, if the cap material liner portions31include silicon nitride, a wet etch employing hot phosphoric acid can be employed to remove the cap material liner portions31.

The second sidewalls302and the transverse sidewalls30T of each vertical semiconductor channel strip30are physically exposed to laterally-undulating gate electrode trenches49L, each of which includes a continuous volume between a neighboring pair of matrix rail structures (21,23,25). The first sidewalls301of each vertical semiconductor channel strip30can contact the lengthwise sidewalls252of the matrix rail structures (21,23,25). Each laterally-undulating gate electrode trench49L includes laterally-undulating sidewalls (such as the combination of physically exposed portions of a lengthwise sidewall252of a matrix rail structure (21,23,25) and the physically exposed sidewalls of the vertical semiconductor channel strips30located directly on the lengthwise sidewall252).

Referring toFIGS. 9A-9C, a laterally-undulating gate dielectric layer50L can be formed by deposition of a continuous dielectric material layer and/or thermal oxidation and/or nitridation of surface portions of the vertical semiconductor channel strips30. The laterally-undulating gate dielectric layer50L includes laterally-undulating sidewalls such as a sidewall (or a set of sidewalls) that includes physically exposed portions of a lengthwise sidewall252of a matrix rail structure (21,23,25) and the physically exposed sidewalls of the vertical semiconductor channel strips30located directly on the lengthwise sidewall252, or a sidewall that is exposed to a laterally-undulating gate electrode trench49L. The laterally-undulating sidewalls of the laterally-undulating gate dielectric layer SOL generally extend along the first horizontal direction hd1, and have lateral shifts or “jogs” along the second horizontal direction hd2. In this embodiment, the laterally-undulating gate dielectric layer SOL is an inner gate dielectric layer that includes inner gate dielectrics for field effect transistors to be subsequently formed.

While the present disclosure is described employing an embodiment in which the laterally-undulating gate dielectric layer SOL is formed as a continuous dielectric material layer, embodiments are expressly contemplated in which the laterally-undulating gate dielectric layer SOL is formed as discrete dielectric material portions formed by oxidation and/or nitridation of surface portions of the vertical semiconductor channel strips30. The laterally-undulating gate dielectric layer SOL can be formed directly on the second sidewall302and the two transverse sidewalls30T of each of the plurality of vertical semiconductor channel strips30and on portions of the lengthwise sidewalls252of the matrix rail structures (21,23,25). Each portion of the laterally-undulating gate dielectric layer SOL that is formed on the second sidewalls302and the transverse sidewalls30T of the vertical semiconductor channel strips30constitutes an inner gate dielectric502, which can be clam-shaped. As used herein, an element is “claim-shaped” if the element includes three sides that are generally arranged in a “C” shape. The laterally-undulating gate dielectric layer50L can include silicon oxide and/or a dielectric metal oxide (such as aluminum oxide), and can have a thickness in a range from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed.

Referring toFIGS. 10A-10C, a laterally-undulating gate electrode layer52L can be formed on the laterally-undulating gate dielectric layer50L. The laterally-undulating gate electrode layer52L includes laterally-undulating sidewalls such as a continuous set of vertical interfaces with the laterally-undulating gate dielectric layer50L that generally extends along the first horizontal direction hd1includes lateral shifts or lateral jogs of alternating opposite directions along (or against) the second horizontal direction hd2. The laterally-undulating gate electrode layer52L can be an inner gate electrode layer. The laterally-undulating gate electrode layer52L can include a metallic material such as titanium nitride, tantalum nitride, tungsten nitride, tungsten, titanium, tantalum, cobalt, ruthenium, an alloy thereof, and/or a layer stack thereof. In one embodiment, the laterally-undulating gate electrode layer52L can include a layer of titanium nitride. Alternatively or additionally, the laterally-undulating gate electrode layer52L can include a doped semiconductor material such as doped polysilicon. The thickness of the laterally-undulating gate electrode layer52L can be in a range from 2 nm to 200 nm, although lesser and greater thicknesses can also be employed. The laterally-undulating gate electrode layer52L can be formed by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The laterally-undulating gate electrode trenches49L can have a lesser width in a region between an adjacent pair of vertical semiconductor channel strips30than in a region between a pair of interfaces between the gate dielectric layers50L and a neighboring pair of matrix rail structures (21,23,25).

Referring toFIGS. 11A-11C, an anisotropic etch that etches the material of the laterally-undulating gate electrode layer52L selective to the material of the laterally-undulating gate dielectric layer SOL or selective to the material of the upper dielectric rail structures23can be performed to etch horizontal portions of the laterally-undulating gate electrode layer52L. Each remaining vertical portion of the laterally-undulating gate electrode layer52L constitutes an inner gate electrode line52. Each inner gate electrode line52is a laterally-undulating structure including laterally-undulating sidewalls, and thus, is a laterally-undulating gate electrode line. Further, an overetch can be performed to vertically recess the top surfaces of the inner gate electrode lines52so that the top surfaces of the inner gate electrode lines52after the overetch can be approximately at the height at which p-n junctions between the vertical semiconductor channel strips of final vertical field effect transistor structures and top active regions of the final vertical field effect transistor structures.

In the semiconductor device to be subsequently formed, multiple instances of a vertical field effect transistor can be provided around a matrix rail structure (21,23,25) such that the multiple instances are spaced apart along the first horizontal direction hd1. Each instance of the vertical field effect transistor can include a pair of inner gate electrodes522. Each of the pair of inner gate electrodes522of the multiple instances of the vertical field effect transistor to be formed around the matrix rail structure (21,23,25) can be a respective portion of a pair of inner gate electrode lines52that is shared among each of the multiple instances of the vertical field effect transistor. Each pair of inner gate electrodes522can contact respective sidewalls of a pair of inner gate dielectrics. Each inner gate electrode522is a portion of an inner gate electrode line52that extends along the first horizontal direction hd1. Thus, a pair of inner gate electrode lines52is provided around each matrix rail structure (21,23,25). Each of the pair of inner gate electrode lines52laterally extends generally along the first horizontal direction hd1through each of the multiple instances of the vertical field effect transistor with bends524at instances of the lateral jogs504of the pair of inner gate dielectric layers50.

Referring toFIGS. 12A-12C, dopants of the first conductivity type can be implanted into upper portions of the vertical semiconductor channel strips30to convert upper portions of each vertical semiconductor channel strip30into top active regions34. The atomic concentration of dopants of the second conductivity type in the top active regions34can be in a range from 1.0×1019/cm3to 2.0×1021/cm3, although lesser and greater atomic concentrations can also be employed. P-n junctions can be formed between the top active regions34and remaining portions of the vertical semiconductor channel strips30. The height of the p-n junctions between the top active regions34and the vertical semiconductor channel strips30can be about the height of the top surfaces of the inner gate electrodes, which are portions of the inner gate electrode lines52.

Referring toFIGS. 13A-13C, a dielectric material such as silicon oxide can be deposited in remaining volumes of the laterally-undulating gate electrode trenches49L by a conformal deposition process or a combination of a non-conformal deposition process and a reflow process. Excess portions of the deposited dielectric material can be removed from above the horizontal plane including the top surfaces of the upper dielectric rail structures23by a planarization process. Chemical mechanical planarization (CMP) or a recess etch may be employed for the planarization process. Each remaining portion of the deposited dielectric material constitutes an inner isolation dielectric line58that extends along the first horizontal direction hd1. The inner isolation dielectric lines58can be formed over the inner gate electrode lines52.

Referring toFIGS. 14A-14D, inner isolation dielectric lines58can be vertically recessed with respect to the top surfaces of the matrix rail structures (21,23,25) and the top surfaces of the top active regions34by an etch process, which may be an isotropic etch process or an anisotropic etch process. In an illustrative embodiment, the inner isolation dielectric lines58can include doped or undoped silicate glass or organosilicate glass, and a wet etch employing hydrofluoric acid can be employed to vertically recess the top surfaces of the inner isolation dielectric lines58relative to the top surfaces of the matrix rail structures (21,23,25) and the top surfaces of the top active regions34. Line trenches59can be formed in the recessed regions overlying the inner isolation dielectric lines58. The duration of the etch process can be selected such that the recessed top surfaces of the inner isolation dielectric lines58are located above the horizontal plane including the top surfaces of the inner gate electrode lines52. Thus, the inner gate electrode lines52are not physically exposed after formation of the line trenches59. The line trenches59can have a laterally-undulating width along the second horizontal direction hd2. In other words, the width of each line trench59as measured along the second horizontal direction hd2can undulate as the location of measurement of the width moves along the first horizontal direction hd1.

Referring toFIGS. 15A-15C, top electrode connection layers36L can be formed in the line trenches59. For example, at least one conductive material can be deposited to fill the line trenches59. The at least one conductive material can include a doped semiconductor material (such as polysilicon) having a doping of the first conductivity type, and/or a metallic material such as TiN, TaN, WN, W, Co, Ru, Ta, Ti, alloys thereof, and/or layer stacks thereof. In one embodiment, the at least one conductive material can include doped polysilicon. Excess portions of the at least one conductive material can be removed from above the horizontal plane including the top surfaces of the matrix rail structures (21,23,25) by a planarization process, which can include, for example, chemical mechanical planarization (CMP) and/or a recess etch. Each top electrode connection layer36L extends between a neighboring par of matrix rail structures (21,23,25), and laterally extends through multiple neighboring pairs of vertical semiconductor channel strips30along the first horizontal direction hd1.

Subsequently, each matrix rail structure (21,23,25) can be replaced with a respective set of at least one gate electrode rail (i.e., at least one rail embodying a gate electrode) and straight-sidewalled gate dielectrics (i.e., gate dielectrics free of laterally-undulating sidewalls). Each set of the at least one gate electrode rail and straight-sidewalled gate dielectrics may include a pair of gate electrode rail gate electrodes and a straight-sidewalled gate dielectric layer including the straight-sidewalled gate dielectrics therein.

Referring toFIGS. 16A-16C, second dielectric material portions23and an upper portion of each first dielectric material portion21can be removed by a series of etch processes. For example, a first etch process can be performed to remove the second dielectric material portions23, and a second etch process can be performed to remove the upper portions of the first dielectric material portions21. In an illustrative example, the second dielectric material portions23can include silicon nitride, and the first etch process can include a wet etch process employing hot phosphoric acid. The second dielectric material portions21can include silicon oxide, and the second etch process can include a wet etch process employing hydrofluoric acid or dry etch process employing HF vapor.

The duration of the second etch process can be selected such that a bottom portion of each first dielectric material portion21remains over the laterally alternating stack of bottom electrode lines10and bottom electrode isolation structures12. Each remaining portion of the first dielectric material portion21is herein referred to as a dielectric pedestal22. The height of the dielectric pedestals22can be selected such that the top surfaces of the dielectric pedestals22can be about the level of the top surfaces of the bottom active regions32. The vertical offset between the top surfaces of the dielectric pedestals22and the top surfaces of the bottom active regions32can be selected to optimize the performance of vertical field effect transistors to be subsequently formed. In one embodiment, the vertical offset between the top surfaces of the dielectric pedestals22and the top surfaces of the bottom active regions32can be the overlap distance between outer gate electrodes to be subsequently formed and the bottom active regions32.

An outer gate electrode cavity29can be formed in volumes from which the second dielectric material portions23and the upper portions of the first dielectric material portions21are removed. Each outer gate electrode cavity29can laterally extend along the first horizontal direction hd1. If the etch process that vertically recesses the first dielectric material portions21to form the dielectric pedestals22is selective to the dielectric material of the dielectric spacers25, the lower portion of each outer gate electrode cavity29can be laterally bounded by sidewalls of the dielectric spacers25.

Referring toFIGS. 17A-17C, at least an upper portion of each dielectric spacer25can be removed selective to the semiconductor material of the vertical semiconductor channel strips30, the top active regions34, and the bottom active regions32by an etch process. The etch process can be an isotropic etch process that is selective to the semiconductor materials of the vertical semiconductor channel strips30, the lower active regions32, and the upper active regions34. A predominant portion of each dielectric spacer26can be removed. As used herein, a “predominant portion” of an element refers to a portion that includes more than 50% of the entirety of the element.

In one embodiment, a remaining portion of each dielectric spacer25may be present on sidewalls of each dielectric pedestal22. In another embodiment, the entirety of each dielectric spacer25may be removed to physically expose portions of top surfaces of the lower electrode lines10between each dielectric pedestal22and a neighboring bottom active region32. The duration of the etch process can be selected to preserve the bottom portions of the dielectric spacers25or to remove the entirety of each dielectric spacers25depending on embodiments. The processing steps ofFIGS. 16A-16C and 17A-17Cremove a predominant portion of each matrix rail structure (21,23,25). Second sidewalls of each of the plurality of vertical semiconductor channel strips30can be physically exposed by removal of the predominant portion of each of the matrix rail structures (21,23,25).

Referring toFIGS. 18A-18C, outer gate dielectrics602can be formed on the physically exposed surfaces of the vertical semiconductor channel strips30by conformal deposition of a gate dielectric material and/or by thermal oxidation and/or nitridation of the physically exposed surface portions of the vertical semiconductor channel strips30. For example, a continuous outer gate dielectric layer60L (which is a straight-sidewalled gate dielectric layer that is free of laterally-undulating sidewalls) can be deposited by a conformal deposition process on the physically exposed second sidewalls of the vertical semiconductor channel strips30. The continuous outer gate dielectric layer60L is continuous layer including outer gate dielectrics602therein as portions thereof, i.e., an outer gate dielectric layer that extends continuously over the entirety of the first exemplary structure. The continuous outer gate dielectric layer60L can include a dielectric material such as silicon oxide and/or a dielectric metal oxide (such as aluminum oxide), and can have a thickness in a range from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed.

In one embodiment, the continuous outer gate dielectric layer60L can extend over the entirety of the first exemplary structure and physically contacts each second sidewall of the plurality of vertical semiconductor channel strips30. The outer gate dielectrics602can comprise portions of the continuous outer gate dielectric layer60L adjacent to the plurality of vertical semiconductor channel strips30. While the present disclosure is described employing an embodiment in which a continuous outer gate dielectric layer60L is employed to provide outer gate dielectrics602, embodiments are expressly contemplated herein in which discrete dielectric material layers are formed by thermal and/or plasma oxidation and/or nitridation of physically exposed second sidewalls of the vertical semiconductor channel strips to provide outer gate dielectrics602.

Referring toFIGS. 19A-19C, a straight-sidewalled gate electrode layer62L can be formed on the continuous outer gate dielectric layer60L. The straight-sidewalled gate electrode layer62L is a straight-sidewalled structure that is free of laterally-undulating sidewalls. The straight-sidewalled gate electrode layer62L can include a metallic material such as titanium nitride, tantalum nitride, tungsten nitride, tungsten, titanium, tantalum, cobalt, ruthenium, an alloy thereof, and/or a layer stack thereof. In one embodiment, the straight-sidewalled gate electrode layer62L can include a layer of titanium nitride. Alternatively or additionally, the straight-sidewalled gate electrode layer62L can include a doped semiconductor material such as doped polysilicon. The thickness of the straight-sidewalled gate electrode layer62L can be selected to be less than one half of the width of each laterally-undulating gate electrode trench29as provided in the processing steps ofFIGS. 18A-18C. In one embodiment, the thickness of the straight-sidewalled gate electrode layer62L can be in a range from 2 nm to 200 nm, although lesser and greater thicknesses can also be employed. The straight-sidewalled gate electrode layer62L can be formed by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Each remaining portion of the laterally-undulating gate electrode trenches29laterally extends along the first horizontal direction hd1, and can have a substantially uniform width throughout.

Referring toFIGS. 20A-20C, an anisotropic etch that etches the material of the straight-sidewalled gate electrode layer62L selective to the material of outer gate dielectric layer60L or selective to the material of the top electrode connection layers36L can be performed to etch horizontal portions of the straight-sidewalled gate electrode layer62L. Each remaining vertical portion of the straight-sidewalled gate electrode layer62L constitutes an outer gate electrode line62. Further, an overetch can be performed to vertically recess the top surfaces of the outer gate electrode lines62so that the top surfaces of the outer gate electrode lines62after the overetch can be approximately at the height of p-n junctions between the vertical semiconductor channel strips30and the top active regions34. The vertical overlap between each outer gate electrode line62and the top active regions34can be optimized for performance of the vertical field effect transistors. Each outer gate electrode line62can have a uniform vertical cross-sectional shape along the vertical planes that are perpendicular to the first horizontal direction hd1, and thus, can be a gate electrode rail located on outer sidewalls of the vertical semiconductor channel strips30, i.e., an outer gate electrode rail. Further, each outer gate electrode line62is a straight-sidewalled structure that is free of laterally-undulating sidewalls.

Specifically, remaining vertical portion of the straight-sidewalled gate electrode layer62L comprises the two outer gate electrode lines62that are spaced apart by an outer gate electrode cavity29. Thus, the two outer gate electrode lines62are straight-sidewalled gate electrode lines62that are free of laterally-undulating sidewalls. Multiple portions of the continuous outer gate dielectric layer60L around the two outer gate electrode lines62constitute outer gate dielectrics602. The two outer gate electrode lines62can contact a respective portion of a top surface of a horizontal portion60H of the continuous outer gate dielectric layer60L that extends from a bottom end of a first vertical portion of the continuous outer gate dielectric layer60L that includes a first subset of the respective multiple portions of the continuous outer gate dielectric layer60L to a second vertical portion of the continuous outer gate dielectric layer60L that includes a second subset of the respective multiple portions of the continuous outer gate dielectric layer60L.

In one embodiment, each outer gate electrode line62can have a uniform width along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1throughout the multiple instances of the vertical field effect transistor located around a same outer gate electrode cavity29. In one embodiment, a pair of outer gate electrode lines62having a uniform width throughout and laterally spaced apart from each other along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1can be provided around each outer gate electrode cavity29. In one embodiment, each of the two outer gate electrode lines62can have a uniform vertical cross-sectional shape along vertical directions perpendicular to the first horizontal direction hd1, and thus, can be gate electrode rails, which are also referred to as outer gate electrode rails. Each outer gate electrode622of the multiple instances of the vertical field effect transistor around the outer gate electrode cavity29can be a respective portion of the pair of outer gate electrode lines62.

Each portion of the outer gate electrode lines62that is adjacent to a vertical semiconductor channel strip30constitutes an outer gate electrode622of a vertical field effect transistor. Multiple instances of a vertical field effect transistor can be formed around each laterally-undulating gate electrode trench29. Each instance of the vertical field effect transistor can include a pair of outer gate electrodes622. Each of the pair of outer gate electrodes622of the multiple instances of the vertical field effect transistor formed around an outer gate electrode cavity29can be a respective portion of a pair of outer gate electrode lines62that is shared among each of the multiple instances of the vertical field effect transistor located around the outer gate electrode cavity29and arranged as a one-dimensional array extending along the first horizontal direction hd1. Each pair of outer gate electrodes622can contact respective second sidewalls of the pair of outer gate dielectrics, which are portions of the continuous outer gate dielectric layer60L. Each outer gate electrode622is a portion of an outer gate electrode line62that extend along the first horizontal direction hd1. Thus, a pair of outer gate electrode lines62is provided around outer gate electrode cavity29. Each of the pair of outer gate electrode lines62laterally extends generally along the first horizontal direction hd1through each of the multiple instances of the vertical field effect transistor.

Referring toFIGS. 21A-21D, a dielectric material such as doped or undoped silicate glass or organosilicate glass can be deposited in the outer gate electrode cavities29to fill the entire volumes of the outer gate electrode cavities29. Excess portions of the deposited dielectric material can be removed from above a horizontal plane including top surfaces of the top electrode connection layers36L. Each remaining portion of the deposited dielectric material filling a respective outer gate electrode cavity29constitutes an outer isolation dielectric line68, which can have a top surface within a same horizontal plane as the top surfaces of the top electrode connection layers36L. Each outer isolation dielectric line68can laterally extend along the first horizontal direction hd1. Each outer isolation dielectric line68can be formed over two outer gate electrode lines62and directly on a region of a top surface of the horizontal portion of an outer gate dielectric layer60and between the two outer gate electrode lines62.

The continuous outer gate dielectric layer60L can be divided into outer gate dielectric layers60extending along the first horizontal direction hd1and including a horizontal portion60H overlying a dielectric pedestal22, a first vertical portion vertically extending upward from a first edge of the horizontal portion60H of the dielectric pedestal22and contacting a first set of vertical semiconductor channel strips30, and a second vertical portion vertically extending upward from a second edge of the horizontal portion60H of the dielectric pedestal22and contacting a second set of vertical semiconductor channel strips30. In one embodiment, multiple instances of the vertical field effect transistor can be formed around a same outer isolation dielectric line68.

Referring toFIGS. 22A-22C, a photoresist layer67can be applied over the top electrode connection layers36, the inner isolation dielectric lines58, and the outer isolation dielectric lines68, and can be lithographically patterned. The patterned photoresist layer67can include line portions that laterally extend along the second horizontal direction hd2and overlie the vertical semiconductor channel strips30. Each vertical semiconductor channel strip30can be covered by a portion of the photoresist layer67.

An etch process can be performed to etch the portions of the top electrode connection layers36L that are not covered by the patterned photoresist layer67selective to the material of the inner isolation dielectric lines58and the outer isolation dielectric lines68. For example, if the top electrode connection layers36L include doped polysilicon, a wet etch employing KOH or a dry etch employing a fluorocarbon gas or a hydrofluorocarbon gas can be employed to etch the material of the top electrode connection layers36L selective to the materials of the inner isolation dielectric lines58and the outer isolation dielectric lines68. Each volume from which a portion of the top electrode connection layers36L is removed by the etch process constitutes a recess region59. Each remaining portion of the top electrode connection layers36L is a top electrode connector36that connects a pair of top active regions34that overlie a pair of inner gate electrodes52. The photoresist layer67can be subsequently removed, for example, by ashing.

Referring toFIGS. 23A-23C, a dielectric material can be deposited in the recess regions59. Excess portions of the deposited dielectric material can be removed by a planarization process, which can include chemical mechanical planarization and/or a recess etch. Each remaining portion of the dielectric material that fills the recess regions59is herein referred to as a top electrode separation dielectric72.

Each of the pair of inner gate dielectrics of the multiple instances of the vertical field effect transistor is a respective portion of an inner gate dielectric layer50(which is a laterally-undulating gate dielectric layer) that laterally extends generally along the first horizontal direction hd1through each of the multiple instances of the vertical field effect transistor with lateral jogs at instances of the transverse sidewalls along the second horizontal direction hd2. An outer gate dielectric contacts a first sidewall of each vertical semiconductor channel strip30, and an inner gate dielectric contacts a second sidewall of each vertical semiconductor channel strip30. Each transverse sidewall of the vertical semiconductor channel strips30contacts a respective inner gate dielectric.

Each vertical field effect transistor includes a pair of vertical semiconductor channel strips30. A pair of bottom active regions32can contact a pair of vertical semiconductor channel strips30, and can be electrically shorted to each other via a bottom electrode line10. A pair of top active regions34contacts top portions of the pair of vertical semiconductor channel strips30, and can be electrically shorted to each other via a conductive structure such as a top electrode connector36.

Referring toFIGS. 23D and 23E, an alternate embodiment of the first exemplary structure is illustrated, which can be derived from the first exemplary structure of by modifying the processing steps of17A-17C to completely remove the dielectric spacers25. In this case, the outer gate dielectric layers60can contact the lower electrode lines10and the bottom electrode isolation structures12.

Multiple instances of the vertical field effect transistor illustrated inFIG. 23A-23C or 23D-23Ecan be implemented as a two-dimensional rectangular array of a plurality of instances of the vertical field effect transistor.

Referring toFIGS. 24A-24C, a second exemplary structure according to a second embodiment of the present disclosure can be derived from the first exemplary structure illustrated inFIGS. 9A-9Cby filling entire volumes of the laterally-undulating gate electrode trenches49L within a laterally-undulating gate electrode layer52L. The laterally-undulating gate electrode layer52L includes laterally-undulating sidewalls such as a continuous set of vertical interfaces with the laterally-undulating gate dielectric layer SOL that generally extends along the first horizontal direction hd1includes lateral shifts or lateral jogs of alternating opposite directions along (or against) the second horizontal direction hd2. The laterally-undulating gate electrode layer52L can be an inner gate electrode layer. The laterally-undulating gate electrode layer52L can be formed by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The laterally-undulating gate electrode trenches49L can have a lesser width in a region between an adjacent pair of vertical semiconductor channel strips30than in a region between a pair of interfaces between the gate dielectric layers SOL and a neighboring pair of matrix rail structures (21,23,25).

Referring toFIGS. 25A-25C, an anisotropic etch that etches the material of the laterally-undulating gate electrode layer52L selective to the material of the laterally-undulating gate dielectric layer50L or selective to the material of the upper dielectric rail structures23can be performed to etch horizontal portions of the laterally-undulating gate electrode layer52L. Each remaining vertical portion of the laterally-undulating gate electrode layer52L constitutes an inner gate electrode line52. Each inner gate electrode line52is a laterally-undulating structure including laterally-undulating sidewalls, and thus, is a laterally-undulating gate electrode line. Further, an overetch can be performed to vertically recess the top surfaces of the inner gate electrode lines52so that the top surfaces of the inner gate electrode lines52after the overetch can be approximately at the height at which p-n junctions between the vertical semiconductor channel strips of final vertical field effect transistor structures and top active regions of the final vertical field effect transistor structures.

In the semiconductor device to be subsequently formed, multiple instances of a vertical field effect transistor can be provided around a matrix rail structure (21,23,25) such that the multiple instances are spaced apart along the first horizontal direction hd1. Each instance of the vertical field effect transistor can include a single inner gate electrode522. Each inner gate electrodes522of the multiple instances of the vertical field effect transistor formed around the matrix rail structure (21,23,25) can be a respective portion of an inner gate electrode lines52that is shared among each of the multiple instances of the vertical field effect transistor. Each inner gate electrode522can contact respective sidewalls of a pair of inner gate dielectrics. Each inner gate electrode522is a portion of an inner gate electrode line52that extends along the first horizontal direction hd1. Thus, a pair of inner gate electrode lines52is provided around each matrix rail structure (21,23,25). Each of the pair of inner gate electrode lines52laterally extends generally along the first horizontal direction hd1through each of the multiple instances of the vertical field effect transistor with bends524at instances of the lateral jogs504of the pair of inner gate dielectric layers50.

Dopants of the first conductivity type can be implanted into upper portions of the vertical semiconductor channel strips30to convert upper portions of each vertical semiconductor channel strip30into top active regions34. The atomic concentration of dopants of the second conductivity type in the top active regions34can be in a range from 1.0×1019/cm3to 2.0×1021/cm3, although lesser and greater atomic concentrations can also be employed. P-n junctions can be formed between the top active regions34and remaining portions of the vertical semiconductor channel strips30. The height of the p-n junctions between the top active regions34and the vertical semiconductor channel strips30can be about the height of the top surfaces of the inner gate electrodes, which are portions of the inner gate electrode lines52.

Referring toFIGS. 26A-26D, a dielectric material such as silicon oxide can be deposited in remaining volumes of the laterally-undulating gate electrode trenches49L. Excess portions of the deposited dielectric material can be removed from above the horizontal plane including the top surfaces of the upper dielectric rail structures23by a planarization process. Chemical mechanical planarization (CMP) or a recess etch may be employed for the planarization process. Each remaining portion of the deposited dielectric material constitutes an inner isolation dielectric line58that extends along the first horizontal direction hd1. The inner isolation dielectric lines58can be formed over the inner gate electrode lines52.

The inner isolation dielectric lines58can be vertically recessed with respect to the top surfaces of the matrix rail structures (21,23,25) and the top surfaces of the top active regions34by an etch process, which may be an isotropic etch process or an anisotropic etch process. In an illustrative embodiment, the inner isolation dielectric lines58can include doped or undoped silicate glass or organosilicate glass, and a wet etch employing hydrofluoric acid can be employed to vertically recess the top surfaces of the inner isolation dielectric lines58relative to the top surfaces of the matrix rail structures (21,23,25) and the top surfaces of the top active regions34. Line trenches59can be formed in the recessed regions overlying the inner isolation dielectric lines58. The duration of the etch process can be selected such that the recessed top surfaces of the inner isolation dielectric lines58are located above the horizontal plane including the top surfaces of the inner gate electrode lines52. Thus, the inner gate electrode lines52are not physically exposed after formation of the line trenches59. The line trenches59can have a laterally-undulating width along the second horizontal direction hd2. In other words, the width of each line trench59as measured along the second horizontal direction hd2can undulate as the location of measurement of the width moves along the first horizontal direction hd1.

Referring toFIGS. 27A-27C, top electrode connection layers36L can be formed in the line trenches59. For example, at least one conductive material can be deposited to fill the line trenches59. The at least one conductive material can include a doped semiconductor material (such as polysilicon) having a doping of the first conductivity type, and/or a metallic material such as TiN, TaN, WN, W, Co, Ru, Ta, Ti, alloys thereof, and/or layer stacks thereof. In one embodiment, the at least one conductive material can include doped polysilicon. Excess portions of the at least one conductive material can be removed from above the horizontal plane including the top surfaces of the matrix rail structures (21,23,25) by a planarization process, which can include, for example, chemical mechanical planarization (CMP) and/or a recess etch. Each top electrode connection layer36L extends between a neighboring par of matrix rail structures (21,23,25), and laterally extends through multiple neighboring pairs of vertical semiconductor channel strips30along the first horizontal direction hd1.

Subsequently, each matrix rail structure (21,23,25) can be replaced with a respective set of at least one gate electrode rail (i.e., at least one rail embodying a gate electrode) and straight-sidewalled gate dielectrics (i.e., gate dielectrics free of laterally-undulating sidewalls). Each set of the at least one gate electrode rail and straight-sidewalled gate dielectrics may include a pair of gate electrode rail gate electrodes and a straight-sidewalled gate dielectric layer including the straight-sidewalled gate dielectrics therein.

Each of the pair of inner gate dielectrics of the multiple instances of the vertical field effect transistor is a respective portion of an inner gate dielectric layer50(which is a laterally-undulating gate dielectric layer) that laterally extends generally along the first horizontal direction hd1through each of the multiple instances of the vertical field effect transistor with lateral jogs at instances of the transverse sidewalls along the second horizontal direction hd2. An outer gate dielectric contacts a first sidewall of each vertical semiconductor channel strip30, and an inner gate dielectric contacts a second sidewall of each vertical semiconductor channel strip30. Each transverse sidewall of the vertical semiconductor channel strips30contacts a respective inner gate dielectric.

Each vertical field effect transistor includes a pair of vertical semiconductor channel strips30. A pair of bottom active regions32can contact a pair of vertical semiconductor channel strips30, and can be electrically shorted to each other via a bottom electrode line10. A pair of top active regions34contacts top portions of the pair of vertical semiconductor channel strips30, and can be electrically shorted to each other via a conductive structure such as a top electrode connector36.

Referring toFIGS. 29A and 29B, a third exemplary structure according to a third embodiment of the present disclosure is shown after formation of matrix rail structures (122,152,150). The matrix rail structures (122,152,150) include a dielectric pedestal122, gate dielectric layer150, and an electrically conductive inner gate electrode rail152, which can be formed on the first exemplary structure illustrated inFIGS. 1A-1C.

For example, a layer stack of a dielectric material layer and a conductive material layer can be formed over the laterally alternating stack of bottom electrode lines10and bottom electrode isolation structures12, and can be patterned to form composite rail structures (122,152) laterally extending along the first horizontal direction hd1. For example, the dielectric material layer can be a silicon oxide layer having a thickness that is on the order of the height of bottom active regions to be subsequently formed. In one embodiment, the thickness of the dielectric material layer can be in a range from 5 nm to 100 nm, although lesser and greater thicknesses can also be employed. The conductive material layer can be a doped silicon layer or a metallic material layer including a metallic material (such as TiN, TaN, W, Co, Ru, Al, an alloy thereof, or a combination thereof) having a thickness that is greater than the height of inner gate electrodes for vertical field effect transistors to be subsequently formed. In one embodiment, the thickness of the conductive material layer can be in a range from 50 nm to 2,000 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer can be applied over the conductive material layer, and can be lithographically patterned with a periodic line and space pattern, i.e., by lithographic exposure and development. Each line pattern in the developed photoresist material can laterally extend along the first horizontal direction hd1, which may be perpendicular to the lengthwise direction of the bottom electrode lines10which is the second horizontal direction. At least one anisotropic etch process can be performed to transfer the pattern of the developed photoresist material portions through the second dielectric material layer and the first dielectric material layer. The bottom electrode lines10may be employed as an etch stop layer and/or as an end point detection layer.

Each remaining portion of the conductive material layer constitutes an inner gate electrode rail152, which is a straight-sidewalled inner gate electrode line, i.e., free of any lateral undulation of sidewalls. Each remaining portion of the dielectric material layer constitutes a dielectric pedestal122, which is a rail structure. A vertical stack of a dielectric pedestal122and an inner gate electrode rail152constitutes a composite rail structure (122,152), which laterally extends along the first horizontal direction hd1. In one embodiment, each composite rail structure (122,152) can have a uniform width throughout. The width of each composite rail structure (122,152) can be in a range from 30 nm to 500 nm, although lesser and greater widths can also be employed.

A continuous inner gate dielectric layer including a gate dielectric material can be deposited by a conformal deposition such as atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD). The continuous inner gate dielectric layer can include any material that can be employed for the laterally-undulating gate dielectric layer SOL or the continuous outer gate dielectric layer60L of the first and second embodiments. The continuous inner gate dielectric layer is a straight-sidewalled gate dielectric layer that is free of laterally-undulating sidewalls. An anisotropic etch may be performed to remove horizontal portions of the continuous inner gate dielectric layer. Each remaining vertical portion of the continuous inner gate dielectric layer constitutes a straight-sidewalled gate dielectric layer150, which functions as an inner gate dielectric layer and is free of laterally-undulating sidewalls. Each contiguous set of a composite rail structure (122,152) and a pair of straight-sidewalled gate dielectric layer150constitutes a matrix rail structure (122,152,150).

The matrix rail structures (122,152,150) laterally extend along the first horizontal direction hd1. Each matrix rail structure (122,152,150) includes a pair of lengthwise sidewalls that extend along the first horizontal direction hd1. Upon formation, each matrix rail structure (122,152,150) includes a set of a gate electrode rail (i.e., an inner gate electrode rail152) extending along the first horizontal direction hd1and straight-sidewalled gate dielectrics, which can be portions of two straight-sidewalled gate dielectric layers150that contact sidewalls of vertical semiconductor channel strips to be subsequently formed. The matrix rail structures (122,152,150) can form a one-dimensional periodic array along the second horizontal direction hd2. Line trenches149L extending along the first horizontal direction hd1are present between the matrix rail structures (122,152,150).

Referring toFIGS. 30A and 30B, a semiconductor channel material layer30L and a sacrificial dielectric layer131can be sequentially formed over the matrix rail structures (122,152,150). The semiconductor channel material layer30L can be formed over the matrix rail structures (122,152,150) and on the entirety of the lengthwise sidewalls of the matrix rail structures (122,152,150). The semiconductor channel material layer30L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The semiconductor channel material layer30L can include the same material as in the first and second embodiments. The thickness of the semiconductor channel material layer30L can be uniform throughout the entirety thereof, and can be in a range from 2 nm to 30 nm, such as from 3 nm to 10 nm, although lesser and greater thicknesses can also be employed. The thickness of the semiconductor channel material layer30L may be selected to enable full depletion of vertical semiconductor channel strips during operation of the vertical field effect transistors.

The semiconductor channel material layer30L can have a doping of second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the semiconductor channel material layer30L can be in a range from 1.0×1015/cm3to 1.0×1018/cm3, although lesser and greater dopant concentrations can also be employed.

The sacrificial dielectric layer131can be formed over the semiconductor channel material layer30L by a conformal or a non-conformal deposition process. The sacrificial dielectric layer131includes a dielectric material that can be subsequently removed selective to the semiconductor material of the semiconductor channel material layer30L. For example, the sacrificial dielectric layer131can include silicon oxide. The thickness of the sacrificial dielectric layer131can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed.

At least one fill material is deposited in the line trenches149L between the matrix rail structures (122,152,150). The spaces among the plurality of matrix rail structures (122,152,150) are filled with the at least one fill material after formation of the semiconductor channel material layer30L. The at least one fill material may include a semiconductor material such as germanium or polysilicon. The at least one fill material is subsequently planarized to remove portions overlying the matrix rail structures (122,152,150). For example, a recess etch or chemical mechanical planarization (CMP) may be employed to planarized the at least one fill material. Each remaining portion of the at least one fill material constitutes a fill material line structure148R, which are rail structures. Thus, each line trench149L is filled with a fill material line structure148R.

Referring toFIGS. 32A-32C, etch masks137can be formed over the matrix rail structures (122,152,150) and the fill material line structures148R. The plurality of etch masks137can laterally extend along the second horizontal direction hd2, and can be laterally spaced apart among one another along the first horizontal direction hd1. Each etch mask137can have a uniform thickness throughout. In one embodiment, the etch masks137can be patterned portions of a photoresist layer. In this case, the etch masks137can be formed, for example, by applying and lithographically patterning a photoresist layer. Alternatively, the etch masks137can be a hard mask layer that is patterned by transfer of a pattern in a patterned photoresist layer by an anisotropic etch.

The width of each etch mask137can be selected to be on the order of the width of vertical semiconductor channel strips to be subsequently formed underneath the etch mask137. The spacing between each neighboring pair of etch masks137can be on the order of the spacing between a neighboring pair of vertical semiconductor channel strips to be subsequently formed. In one embodiment, the width of each etch mask137can be the same, and can be in a range from 20 nm to 600 nm, although lesser and greater widths can also be employed. In one embodiment, the spacing between neighboring pairs of etch mask137can be the same, and can be in a range from 20 nm to 600 nm, although lesser and greater spacings can also be employed.

Subsequently, portions of the fill material line structures148R and portions of the semiconductor channel material layer30L are removed from within areas that are not covered by the plurality of etch masks137. Specifically, an anisotropic etch can be performed to remove the material of the fill material line structures148R selective to the sacrificial dielectric layer131employing the etch masks137semiconductor channel material layer structure. Isolation cavities149are formed in each volume of the fill material line structures148R that are not covered by the etch masks137. Each remaining portion of the fill material line structures148R constitutes a fill material pillar structure148.

Subsequently, a first isotropic etch process can be performed to remove portions of the sacrificial dielectric layer131that are physically exposed to the isolation cavities49, i.e., to remove portions of the sacrificial dielectric layer131that are not covered by the etch masks137. For example, if the sacrificial dielectric layer131include silicon oxide, a wet etch employing hydrofluoric acid can be employed to remove portions of the sacrificial dielectric layer131located between areas covered by the etch masks137.

A second isotropic etch process can be performed to remove portions of the semiconductor channel material layer that are not covered by the etch masks137. For example, if the semiconductor channel material layer30L include polysilicon, a wet etch employing a KOH solution can be employed to remove portions of the semiconductor channel material layer30L located between areas covered by the etch masks137. Each remaining discrete portion of the semiconductor channel material layer constitutes a semiconductor channel material strip130that extends along the second horizontal direction hd2and over multiple matrix rail structures (122,152,150). Each semiconductor channel material strip130includes a plurality of vertical semiconductor channel strips30, which are vertical portions of the semiconductor channel material strip130.

Each semiconductor channel material strip130includes horizontal portions and vertical portions. Each vertical portion of a semiconductor channel material strip130includes a vertical semiconductor channel strip of vertical field effect transistors to be subsequently formed. Specifically, each vertical portion of a semiconductor channel material strip130between the two horizontal planes including the top surfaces of the inner gate electrode rails152and the bottom surfaces of the inner gate electrode rails152constitutes a vertical semiconductor channel strip.

Thus, the semiconductor channel material layer30L can be patterned into a plurality of semiconductor channel material strips130straddling multiple matrix rail structures (122,152,150). The plurality of semiconductor channel material strips130can form a one-dimensional array that is repeated along the first horizontal direction hd1. Each semiconductor channel material strip130can overlie a respective bottom electrode line10. Portions of the lengthwise sidewalls of the multiple matrix rail structures (122,152,150) are physically exposed to isolation cavities149between each neighboring pair of etch masks137.

A third isotropic etch can be performed to etch physically exposed portions of the straight-sidewalled gate dielectric layer150. Each straight-sidewalled gate dielectric layer150can be divided into straight-sidewalled gate dielectrics, which are herein referred to as inner gate dielectrics502. Each inner gate dielectric502is free of lateral undulation.

Referring toFIGS. 33A-33C, the etch masks137can be removed selective to the composite rail structures (122,152), for example, by ashing. A sacrificial material different from the materials of the composite rail structures (122,152) and the semiconductor channel material strips130can be deposited in the isolation cavities149, and excess portions of the sacrificial material can be removed from above the composite rail structures (122,152). For example, the sacrificial material may be removed by a planarization process (such as chemical mechanical planarization or a recess etch) employing one of the material portions selected from the topmost portions of the sacrificial dielectric layer131, topmost portions of the semiconductor channel material strips130, and topmost portions of the composite rail structures (122,152). Remaining portions of the sacrificial material form sacrificial protection structures138that fill each isolation cavity149. In one embodiment, the sacrificial protection structures138can include silicon nitride. The sacrificial protection structures138protect the inner gate dielectrics502during subsequent removal of the fill material pillar structures148and the sacrificial dielectric liners131.

Referring toFIGS. 34A-34C, the fill material pillar structures148can be removed selective to the sacrificial protection structures138. For example, if the fill material pillar structures148include polysilicon, a wet etch employing KOH may be employed to remove the fill material pillar structures148selective to the sacrificial protection structures138. Subsequently, the sacrificial dielectric liners131and the sacrificial protection structures138can be removed. Removal of the sacrificial protection structures138may be performed after, or prior to, removal of the sacrificial dielectric liners131. If the sacrificial dielectric liners131include silicon oxide, a wet etch employing hydrofluoric acid can be employed to remove the sacrificial dielectric liners131selective to the semiconductor channel material strips130. If the sacrificial protection structures138include silicon nitride, a wet etch employing hot phosphoric acid can be employed to remove the sacrificial protection structures138.

A laterally-undulating gate electrode trench159is formed between each neighboring pair of composite rail structures (122,152). Each laterally-undulating gate electrode trench159includes a pair of laterally-undulating sidewalls that include physically exposed surfaces of the composite rail structures (122,152) and the semiconductor channel material strips130.

Referring toFIGS. 35A-35C, a laterally-undulating gate dielectric layer160L can be formed by deposition of a continuous dielectric material layer and/or thermal oxidation and/or nitridation of surface portions of the semiconductor channel material strips130. The laterally-undulating gate dielectric layer160L includes laterally-undulating sidewalls such as a sidewall (or a set of sidewalls) that includes physically exposed portions of a lengthwise sidewall of a composite rail structure (122,152) and the physically exposed sidewalls of the semiconductor channel material strips130located directly on the lengthwise sidewall, or a sidewall that is exposed to a laterally-undulating gate electrode trench159. The laterally-undulating sidewalls of the laterally-undulating gate dielectric layer160L generally extend along the first horizontal direction hd1, and have lateral shifts or “jogs” along the second horizontal direction hd2. In this embodiment, the laterally-undulating gate dielectric layer160L is an outer gate dielectric layer that includes outer gate dielectrics for field effect transistors to be subsequently formed.

While the present disclosure is described employing an embodiment in which the laterally-undulating gate dielectric layer160L is formed as a continuous dielectric material layer, embodiments are expressly contemplated in which the laterally-undulating gate dielectric layer160L is formed as discrete dielectric material portions formed by oxidation and/or nitridation of surface portions of the vertical semiconductor channel strips30. The laterally-undulating gate dielectric layer160L can be formed directly on the second sidewall302and the two transverse sidewalls30T of each of the plurality of vertical semiconductor channel strips30and on portions of the lengthwise sidewalls252of the matrix rail structures (21,23,25). Each portion of the laterally-undulating gate dielectric layer160L that is formed on the second sidewalls302and the transverse sidewalls30T of the vertical semiconductor channel strips30constitutes an outer gate dielectric602, which can be clam-shaped. The laterally-undulating gate dielectric layer160L can include silicon oxide and/or a dielectric metal oxide (such as aluminum oxide), and can have a thickness in a range from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed.

Referring toFIGS. 36A-36C, a laterally-undulating gate electrode layer162L can be formed on the laterally-undulating gate dielectric layer160L. The laterally-undulating gate electrode layer162L includes laterally-undulating sidewalls such as a continuous set of vertical interfaces with the laterally-undulating gate dielectric layer160L that generally extends along the first horizontal direction hd1includes lateral shifts or lateral jogs of alternating opposite directions along (or against) the second horizontal direction hd2. The laterally-undulating gate electrode layer162L can be an outer gate electrode layer. The laterally-undulating gate electrode layer162L can include a metallic material such as titanium nitride, tantalum nitride, tungsten nitride, tungsten, titanium, tantalum, cobalt, ruthenium, an alloy thereof, and/or a layer stack thereof. In one embodiment, the laterally-undulating gate electrode layer162L can include a layer of titanium nitride. Alternatively or additionally, the laterally-undulating gate electrode layer162L can include a doped semiconductor material such as doped polysilicon. The thickness of the laterally-undulating gate electrode layer162L can be in a range from 2 nm to 200 nm, although lesser and greater thicknesses can also be employed. The laterally-undulating gate electrode layer162L can be formed by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The laterally-undulating gate electrode trenches159can have a lesser width in a region between an adjacent pair of vertical semiconductor channel strips30than in a region between a pair of interfaces between the laterally-undulating gate dielectric layer160L and a neighboring pair of composite rail structures (122,152).

Referring toFIGS. 37A-37C, at least one anisotropic etch process is performed, which etches horizontal portions of the laterally-undulating gate electrode layer162L, the laterally-undulating gate dielectric layer160L, and the semiconductor channel material strips130. Each remaining portion of the laterally-undulating gate electrode layer162L forms a gate electrode, which is adjacent to an outer sidewall of a set of vertical semiconductor channel strips30, and is therefore, referred to as an outer gate electrode line162. Each outer gate electrode line162is a laterally-undulating gate electrode line. Each remaining portion of the laterally-undulating gate dielectric layer160L is an outer gate dielectric layer160, which is a laterally-undulating structure including a pair of laterally-undulating sidewalls. Each remaining portion of the semiconductor channel material strips130constitutes an L-shaped semiconductor channel strip30′ that includes a vertical portion (which is a vertical semiconductor channel strip30) and a horizontal portion adjoined to the vertical portion.

On overetch can be performed to vertically recess the top surfaces of the outer gate electrode lines162so that the top surfaces of the outer gate electrode lines162after the overetch can be approximately at the height at which p-n junctions between the vertical semiconductor channel strips30of final vertical field effect transistor structures and top active regions of the final vertical field effect transistor structures.

The semiconductor device can comprise multiple instances of a vertical field effect transistor that are spaced apart along the first horizontal direction. Multiple instances of a vertical field effect transistor can be provided around each matrix rail structure (122,152,150) as provided at the processing steps ofFIGS. 29A and 29Bsuch that the multiple instances are spaced apart along the first horizontal direction hd1. Each instance of the vertical field effect transistor can include an inner gate electrode which is a portion of an inner gate electrode rail152. A pair of outer gate electrodes can contact a respective one of a pair of outer gate dielectrics of a vertical field effect transistor. Each of the pair of outer gate electrodes of the multiple instances of the vertical field effect transistor can be a respective portion of a pair of outer gate electrode lines162that is shared among each of the multiple instances of the vertical field effect transistor. In one embodiment, each of the pair of outer gate electrode lines162laterally extends generally along the first horizontal direction hd1through each of the multiple instances of the vertical field effect transistor with bends at instances of the lateral jogs of the pair of outer gate dielectric layers160. The multiple instances of the vertical field effect transistor can be repeated along the second direction hd2to form a two-dimensional array of vertical field effect transistors.

Referring toFIGS. 38A-38C, a dielectric material such as silicon oxide can be deposited in remaining volumes of the laterally-undulating gate electrode trenches159by a conformal deposition process or a combination of a non-conformal deposition process and a reflow process. A planarization process can be performed to remove excess portions of the deposited dielectric material from above the inner gate electrode rails152. Chemical mechanical planarization (CMP) or a recess etch may be employed for the planarization process. Each remaining portion of the deposited dielectric material constitutes an outer isolation dielectric line168that extends along the first horizontal direction hd1. The outer isolation dielectric lines168can be formed directly on the lower electrode lines10and the bottom electrode isolation structures12. The outer isolation dielectric lines168are laterally-undulating structures, each of which includes a pair of laterally-undulating sidewalls.

In one embodiment, a chemical mechanical planarization process can be performed to provide planarized top surfaces for the inner gate electrode rails152, the inner gate dielectrics502, the L-shaped semiconductor channel strips30′, the outer gate dielectric layers160, the outer gate electrode lines162, and the outer isolation dielectric lines168. In one embodiment, the planarized top surfaces of the inner gate electrode rails152, the inner gate dielectrics502, the L-shaped semiconductor channel strips30′, the outer gate dielectric layers160, the outer gate electrode lines162, and the outer isolation dielectric lines168may be located within a same horizontal plane.

Referring toFIGS. 39A-39C, physically exposed top surfaces of the inner gate electrode rails152and the outer gate electrode lines162can be vertically recessed simultaneously or sequentially. The depth of recess of the inner gate electrode rails152and the outer gate electrode lines162can be selected to be about the height of top active regions to be subsequently formed. Specifically, the depth of recess of the inner gate electrode rails152and the outer gate electrode lines162can be determined such that the recessed top surfaces of the depth of recess of the inner gate electrode rails152and the outer gate electrode lines162provide optimal overlap with top active regions to be subsequently formed by conversion of top portions of the L-shaped semiconductor channel strips30′, each of which includes a respective vertical semiconductor channel strip30. In one embodiment, the inner gate electrode rails152and the outer gate electrode lines162can include a same conductive material such as TiN, and vertical recessing of the inner gate electrode rails152and the outer gate electrode lines162can be performed simultaneously. In one embodiment, the recess depth of the inner gate electrode rails152and the outer gate electrode lines162can be in a range from 5 nm to 100 nm, although lesser and greater recess depths can also be employed. Each portion of an inner gate electrode rail152that contacts an inner gate dielectric502is an inner gate electrode. Each inner gate electrode rail152includes multiple inner gate electrodes for a set of vertical field effect transistors arranged along the first horizontal direction hd1.

A dielectric material such as silicon oxide can be deposited in the vertical recesses, for example, by a conformal deposition process and an optional reflow process. Excess portions of the dielectric material can be removed from above the top surfaces of the L-shaped semiconductor channel strips30′ and the outer isolation dielectric lines168by a planarization process. An inner cap dielectric line158(which can be a rail structure) can be formed within each vertical recess overlying an inner gate electrode rail152. An outer cap dielectric line166can be formed within each vertical recess overlying an outer gate electrode line162.

Referring toFIGS. 40A-40C, top active regions134and bottom active regions132are formed by doping of top portions and bottom portions of the L-shaped semiconductor channel strips30′ with dopants of the first conductivity type. Each portion of the L-shaped semiconductor channel strip30′ that is not converted into the top active regions134or the bottom active regions132is a vertical semiconductor channel strip30that has a vertical strip shape and functions as a vertical semiconductor channel. For example, dopants of the first conductivity type can be implanted into top portions of the along the L-shaped semiconductor channel strips30′ by an ion implantation process. The angle and the energy of the ion implantation process can be selected to provide a suitable overlap between the top active regions134and the inner gate electrode rails152and the outer gate electrode lines162. An activation anneal can be performed at an elevated temperature, which can be in a range from 850 degrees Celsius to 1,050 degrees Celsius. Dopants of the first conductivity type diffuse upward from the doped semiconductor bottom electrode line portions10B into bottom portions of the L-shaped semiconductor channel strips30′ during the activation anneal to form the bottom active regions132. The duration and the temperature of the activation anneal can be selected such that a suitable vertical overlap is provided between each bottom active regions132and a respective electrically coupled pair of an inner gate electrode rail152and an outer gate electrode line162.

Each pair of top active regions134for a vertical field effect transistor can be electrically shorted to each other by a conductive structure280, which can contact the pair of top active regions134from above. Each pair of top active regions134can contact a top portion of a respective pair of vertical semiconductor channels30, and can be electrically shorted to each other via a respective conductive structure280. In one embodiment, the conductive structures280can be contact via structures (e.g., vertical local bit line) formed through a dielectric material layer (not shown).

FIG. 41illustrates a three-dimensional memory device employing an array of vertical field effect transistors of an embodiment of the present disclosure. The vertical field effect transistors300TC function as select transistors of a three dimensional memory device1000, such as a three dimensional resistive random access memory ReRAM device. A pair of top active regions (34,134) of each vertical field effect transistor300TC can be connected to a vertical access line (such as a local bit line)280of the three-dimensional memory device1000. Each vertical field effect transistor controls the activation (i.e., selection) of the respective vertical access line280. The three-dimensional memory device1000includes a vertical stack400of memory elements and a vertical stack of word lines500separated by insulating layers. In one embodiment, the vertical stack400of memory elements can include a vertical stack of resistive random access memory (ReRAM) elements, such as metal oxide (e.g., titanium oxide or nickel oxide) or chalcogenide elements located at the intersections of the vertical access lines280and word lines500. The ReRAM elements change their resistivity in response to an application of a voltage between a respective vertical access line and word line that sandwich the respective ReRAM element. The three-dimensional memory device1000can include a two-dimensional array of vertical stacks400to provide a three-dimensional array of memory elements. The three-dimensional array of memory elements can be accessed by a two-dimensional array of vertical field effect transistors300TC described above.

WhileFIG. 41illustrated only one instance of a vertical field effect transistor, multiple vertical field effect transistors300can be connected to a common bottom electrode line10(i.e., to a global bit line) provided at the global bitline (GB) level, which is one of the metal interconnect levels located in or above the substrate6. The substrate6may include a silicon wafer600containing various semiconductor devices (e.g., CMOS transistors of a driver circuit) within an active region AA and including various structures at various levels between the memory device1000and the silicon wafer600such as a gate conductor level GC (e.g., containing gate electrodes for the CMOS transistors of the driver circuit), a contact level CS, a first line level MO, a first via level V0, a second line level MF, a second via level V1, a third line level M1, a third via level V2, and connection level such as Z0. These levels may interconnect the driver circuit with the vertical select field effect transistors300TC, with word lines500and/or with an external contact. In addition, overlying metal interconnect levels such as M2may be provided which is used to contact the word lines500at a stepped terrace contact region using connection level Z1. The various gate electrodes (52,62,152,162) of the present disclosure may be select gate electrodes which are provided at a select gate level SG. The gate electrodes may function as select gate electrodes for a plurality of vertical select transistors (i.e., for a plurality of discrete channels).

The various embodiments of the present disclosure provide at least one vertical field effect transistor. The vertical field effect transistor can include at least one inner gate electrode (522,152) extending along a first horizontal direction hd1; a pair of inner gate dielectrics502contacting a respective sidewall of the at least one inner gate electrode (522,152) and vertically extending above topmost edges of the at least one inner gate electrode (522,152); a pair of vertical semiconductor channel strips30, each including a first sidewall301contacting a respective one of the pair of inner gate dielectrics502, a second sidewall302that is parallel to the first sidewall301, and two transverse sidewalls30T each adjoining the first sidewall301and the second sidewall302; a pair of outer gate dielectrics (602,160) contacting a respective one of the pair of vertical semiconductor channel strips30; a pair of outer gate electrodes (622,162) contacting a respective one of the pair of outer gate dielectrics (602,160); at least one bottom active region (32,132) contacting the pair of vertical semiconductor channel strips30and electrically shorted to a bottom electrode line10; and a pair of top active regions (34,134) contacting a top portion of a respective one of the pair of vertical semiconductor channel strips30and electrically shorted to each other via a conductive structure (36,280).

In some embodiments, each transverse sidewall30T of the pair of vertical semiconductor channel strip30contacts a respective one of the pair of outer gate dielectrics (602,160) or a respective one of the pair of inner gate dielectrics522. In some embodiments, the semiconductor device comprises multiple instances of the vertical field effect transistor that are spaced apart along the first horizontal direction hd1; and each of the pair of outer gate electrodes (622,162) of the multiple instances of the vertical field effect transistor is a respective portion of a pair of outer gate electrode lines (62,162) that is shared among each of the multiple instances of the vertical field effect transistor.

Each of the pair of outer gate dielectrics160of the multiple instances of the vertical field effect transistor can be a respective portion of a pair of outer gate dielectric layers160that laterally extends generally along the first horizontal direction hd1through each of the multiple instances of the vertical field effect transistor with lateral jogs along a second horizontal direction hd2at instances of the transverse sidewalls30T as illustrated in the third exemplary structure.

The at least one inner gate electrode522can comprise at least one portion of at least one inner gate electrode line52that laterally extends generally along the first horizontal direction hd1through each of the multiple instances of the vertical field effect transistor and has laterally-undulating sidewalls as illustrated in the first and second embodiments.

In some embodiments, each of the at least one inner gate electrode (522,152) of the multiple instances of the vertical field effect transistor can be a respective portion of at least one inner gate electrode line (52,152) that is shared among each of the multiple instances of the vertical field effect transistor. Each of the pair of outer gate electrode lines62can have a uniform width along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1throughout the multiple instances of the vertical field effect transistor as illustrated in the first and second exemplary structures.

The at least one inner gate electrode line52can be a single inner gate electrode line having a laterally-undulating width as a function of a location along the first horizontal direction hd1, and each of the at least one inner gate electrode522of the multiple instances of the vertical field effect transistor can be a respective portion of the single inner gate electrode line52as illustrated in the second exemplary structure.

The at least one inner gate electrode line52can be a pair of inner gate electrode lines52laterally spaced apart from each other along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1, a lateral separation distance between the pair of inner gate electrode lines52can modulate along the first horizontal direction hd1, and each of the at least one inner gate electrode522of the multiple instances of the vertical field effect transistor can be a respective portion of the pair of inner gate electrode lines52as illustrated in the first embodiment.

Each inner gate dielectric502within the multiple instances of the vertical field effect transistor can be a respective portion of at least one inner gate dielectric layer50that laterally extends along the first horizontal direction hd1and contacts the pair of outer gate dielectric layers60between neighboring instances of the field effect transistors within the multiple instances of the vertical field effect transistor as illustrated in the first and second exemplary structures.

Each inner gate dielectric502within the multiple instances of the vertical field effect transistor can be a discrete dielectric material portion that is physically spaced apart from other inner gate dielectrics502and has a same lateral extent along the first horizontal direction hd1as a vertical semiconductor channel strip30that each inner gate dielectric502contacts as illustrated in the third exemplary structure.

In some embodiments, the at least one instance of a vertical field effect transistor can comprise a two-dimensional rectangular array of a plurality of instances of the vertical field effect transistor.

The entirety of the vertical semiconductor channel strip30can be a depletion zone in each of the vertical field effect transistors of the present disclosure. Thus, the vertical field effect transistors of the present disclosure functions as fully depleted field effect transistor that displays electrical characteristics of fully depleted silicon-on-insulator field effect transistors with a modification in the direction of the channel. Each vertical semiconductor channel strip30can be fully laterally enclosed (i.e., surrounded) by an inner gate dielectric and an outer gate dielectric. Further, each vertical semiconductor channel strip30is controlled by a pair of gate electrodes that includes an inner gate electrode (522,152) and an outer gate electrode (622,162). Each vertical field effect transistor includes a pair of vertical semiconductor channel strips30that are parallel to each other, and are laterally spaced from each other by at least one inner gate electrode (522,152).

The at least one inner gate electrode (522,152) can be a single inner electrode or a pair of inner electrodes. Two outer gate electrodes (622,162) are provided per vertical field effect transistor. Thus, a total of three gate electrodes or four gate electrodes are provided for two vertical channels of each vertical field effect transistor. The voltages of the three or four gate electrodes can be controlled to provide full depletion in both of the vertical semiconductor channel strips30during operation of the vertical field effect transistor, thereby enhancing the current-voltage characteristics of the vertical field effect transistor. Specifically, the on-current of the vertical field effect transistor of the present disclosure can be greater than the on-current of a comparative exemplary vertical field effect transistor having the same channel length (along the direction of the current flow) and the same channel width (i.e., the total interface area with the gate dielectrics) and operating at the same operating voltage due to the complete control of the channel through full depletion. Further, the three or four gate electrodes of the vertical field effect transistors of the present disclosure in conjunction with the thin vertical semiconductor channel strips30that enables full depletion can provide a lesser off-current than the off-current of a comparative exemplary vertical field effect transistor having the same channel length and the same channel width and operating at the same operating voltage due to the complete control of the channel through full depletion.

Referring toFIGS. 42A-42C, a fourth exemplary structure according to a fourth embodiment of the present disclosure can be derived from the from the second exemplary structure ofFIGS. 27A-27Cby performing the processing steps ofFIGS. 16A-16C and 17A-17C. Outer gate electrode cavities29can be formed between inner gate electrode lines52, which are laterally-undulating structures including laterally-undulating sidewalls, and thus, is a laterally-undulating gate electrode line.

Referring toFIGS. 43A-43D, the processing steps ofFIGS. 18A-18Ccan be performed to form outer gate dielectrics60on the physically exposed surfaces of the vertical semiconductor channel strips30, for example, by conformal deposition of a gate dielectric material and/or by thermal oxidation and/or nitridation of the physically exposed surface portions of the vertical semiconductor channel strips30.

A conductive material is deposited and vertically recessed to form outer gate electrode rails352, each of which can be straight-sidewalled. The outer gate electrode rails352can include the same material as the straight-sidewalled gate electrode layer62L of the first embodiment. Thus, the outer gate electrode rails352can be made of a different electrically conductive material than the inner gate electrode lines52. For example, the outer gate electrode rails352can be made of a metallic material (e.g., metal or metal alloy, such as titanium nitride or tungsten), while the inner gate electrode lines52can be made of heavily doped semiconductor material, such as heavily doped polysilicon. Subsequently, a dielectric material such as doped or undoped silicate glass or organosilicate glass can be deposited over the outer gate electrode rails352to form outer isolation dielectric lines68can laterally extend along the first horizontal direction hd1. Each outer isolation dielectric line68can be formed over a single outer gate electrode rail352.

In the configuration of the fourth exemplary structure, each outer gate electrode lines352can be shared by a pair of vertical field effect transistors that are laterally spaced apart along the second horizontal direction. Current flow within a pair of vertical semiconductor channel strips30of a field effect transistor can be controlled by an inner gate electrode line52and a pair of outer gate electrode rails352. Each outer gate electrode rail352can be shared between a pair of vertical field effect transistors that are laterally spaced apart along the second horizontal direction hd2. Voltages to the inner gate electrode lines52and/or the outer gate electrode rails352can be applied such that current flow through each vertical semiconductor channel strip30is enabled. The fourth exemplary structure can replace any of the first, second, and third exemplary structures.

The fourth exemplary structure includes a semiconductor device comprising at least one vertical field effect transistor. Each vertical field effect transistor includes: an inner gate electrode522(i.e., a portion of an inner gate electrode line52, as shown inFIG. 43C) extending along a first horizontal direction hd1; a pair of inner gate dielectrics (i.e., portions of two laterally-undulating gate dielectric layers SOL) contacting a respective sidewall of the inner gate electrode522and vertically extending above topmost edges of the inner gate electrode522; a pair of vertical semiconductor channel strips30, each including a first sidewall contacting a respective one of the pair of inner gate dielectrics, a second sidewall that is parallel to the first sidewall, and two transverse sidewalls each adjoining the first sidewall and the second sidewall; a pair of outer gate dielectrics (i.e., portions of an outer gate dielectric layer60) contacting a respective one of the pair of vertical semiconductor channel strips30; a pair of outer gate electrodes (i.e., portions of two outer gate electrode rails352) contacting a respective one of the pair of outer gate dielectrics; at least one bottom active region32contacting the pair of vertical semiconductor channel strips30and electrically shorted to a bottom electrode line10; and a pair of top active regions34contacting a top portion of a respective one of the pair of vertical semiconductor channel strips30and electrically shorted to each other via a conductive structure (e.g., a top electrode connector36), as shown inFIG. 43A.

Each of the inner gate electrode lines/rails can be electrically biased independently by a respective inner gate electrode driver circuit. Each of the outer gate electrode lines/rails can be electrically biased independently by a respective outer gate electrode driver circuit. In one embodiment, a set of at least one inner gate electrode rail and at least one outer gate electrode rail for a single vertical field effect transistor may be electrically coupled and/or shorted (e.g., electrically connected to the same select gate line). This mode of operation may be carried out with vertical field effect transistors of the first, second and third embodiments. Alternatively, at least one inner gate electrode rail and at least one outer gate electrode rail for a single vertical field effect transistor may be electrically isolated and independently controlled (e.g., at least one inner gate electrode is electrically connected to different select gate line from at least one of the pair of outer gate electrodes). In this case, each of the outer gate electrode rails/lines can be biased independently (e.g., at different voltages) of the inner gate electrode rails/lines in the same field effect transistor. Likewise, each of the inner gate electrode rails/lines can be biased independently of the outer gate electrode rails/lines in the same field effect transistor. This mode of operation may be carried out with vertical field effect transistors of the first, second, third, and fourth embodiments. In the fourth embodiment, the inner gate electrode can be made of a different material from the two outer gate electrodes and can be biased differently from the two outer gate electrodes. Furthermore, the two outer gate electrodes and electrically connected to each other and biased together at the same voltage.