Packaging of semiconductor device with antenna and heat spreader

A semiconductor package includes an integrated circuit (IC), a heat dissipation structure, a molding layer and an antenna. The IC is mounted on a first surface of a first redistribution layer (RDL). The heat dissipation structure is mounted on a second surface of the first RDL. The molding compound is disposed over the first surface of the first RDL. The antenna is disposed on the second surface of the first RDL, wherein the antenna is disposed side-by-side to the heat dissipation structure.

BACKGROUND

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). Since passive components and chips which are packed in a semiconductor package generate heat while operating, heat dissipation for the semiconductor package is one of the major concerns in the semiconductor industry. However, a semiconductor package with heat dissipation structure is usually thickness overhead which would be an issue in the development of the semiconductor industry.

Therefore, there is a need to integrate heat dissipation structure in a semiconductor package and to reduce the thickness of the semiconductor package.

DETAILED DESCRIPTION

FIG. 1is a schematic cross-sectional view of a semiconductor device100in accordance with some embodiments of the disclosure. Referring toFIG. 1, the semiconductor device100includes a semiconductor package110and a printed circuit board120. The semiconductor package110includes an integrated circuit (IC)112, a heat dissipation structure114, a molding layer116and an antenna118. Additionally, the semiconductor package110may further include redistribution layers (RDLs)113,115and117, thermal paste layers TP1and TP2, and the connecting components or solder balls119. The semiconductor package110is mounted on the printed circuit board120through the solder balls119. In some embodiments of the disclosure, the semiconductor package110may be an integrated fan-out (InFO) package which integrates the heat dissipation structure114to improve the heat dissipation capability of the InFO package.

In some embodiments of the disclosure, the IC112may be or include a radio-frequency (RF) chip which is configured to generate or process RF signals. The RF chip may be used in numerous electronic devices such as cellular telephones and wireless communication devices. The IC112has an active side AS and a back side BS, where the backside BS is coupled to the heat dissipation structure114through the RDLs113,115and the thermal paste layers TP1and TP2. As such, the heat generated by the IC112may be dissipated by the heat dissipation structure114. The active side AS of the IC112is electrically coupled to the solder balls119through the RDL117to communicate with circuits in the printed circuit board120.

The heat dissipation structure114is disposed on a surface of the RDL113with a thermal paste layer TP2in between the heat dissipation structure114and the RDL113. The heat dissipation structure114has a high coefficient of thermal expansion to increase the heat dissipation performance. The material of the heat dissipation structure114may be copper, copper compound, aluminum, aluminum compound, ceramic material or a combination thereof. The thermal conduction coefficients of copper and aluminum are about 389 W/m-K and 210 W/m-K, respectively. It should be noted that the material and the shape of the heat dissipation structure114are not limited in the disclosure.

To improve the thermal conductivity and thermal dissipation performance, the thermal paste is disposed between the heat dissipation structure114and the RDL113and between the RDL115and the IC112. The thermal paste may be thermally conductive (e.g., high thermal conductivity) and electrically insulating (high electrical conductivity) compound. The material for the thermal paste is not limited in the disclosure.

In some embodiments of the disclosure, the antenna118may be a double-patch antenna which includes at least one antenna patch118aand at least one antenna patch118b. The antenna patch118ais separated from the antenna patch118bby at least one dielectric layer, and the at least one dielectric layer may include at least one air cavity118cfor improving the performance of the antenna118. In some embodiments, the supporting frame118dis used to form the air cavity118c. However, the dielectric layer with air cavity118cshould not be limited to the disclosure. The at least one dielectric layer may be filled up with other dielectric material instead of the air, and the antenna design may be adapted according to the design needs. The antenna118may further include a ground plane which may be the RDL117in an embodiment of the disclosure.

In some embodiments, the materials of the antenna patches118aand118bmay be different from the material of the heat dissipation structure114to avoid the signal interferences between the heat dissipation structure114and the antenna118. The antenna118may be separated from the heat dissipation structure114by a gap (e.g., an air gap) to reduce the influence of the heat from the heat dissipation structure114to the performance of the antenna118. The materials for the antenna patches118a,118band the heat dissipation structure114, and the width of the air gap between the antenna118and the heat dissipation structure114are selected according to designed needs.

The antenna118is disposed on the RDL113and is arranged in side-by-side with the heat dissipation structure114. In this way, the thickness of the semiconductor package110is reduced while the performance of the antenna118and the heat dissipation structure is improved.

The molding layer116may be served as a protective layer that protect the IC212and other components of the semiconductor package110. In addition, the molding layer116may also be served as a part of the antenna118. For example, the RDL117may serve as a ground plane of the antenna118, and the molding layer116may serve as a dielectric layer which separate the ground plane from the antenna patch118a.

FIG. 2AtoFIG. 2Iare schematic cross-sectional views illustrating a manufacturing method of a semiconductor package according to some embodiments of the disclosure. Referring toFIG. 2A, a RDL213is formed on a carrier substrate200. The carrier substrate200may be a glass substrate or a glass supporting board. Alternatively, other suitable materials may be adapted for the carrier substrate200as long as the materials are able to withstand the subsequent manufacturing processes and support the elements formed thereon.

In some embodiments of the disclosure, an adhesive layer (not shown) is formed between the carrier substrate200and the RDL213to enhance the adhesion between the carrier substrate200and the other structures subsequently formed thereon, and to improve the rigidity of the overall package structure during the manufacturing process. In some embodiments, the adhesive layer may be a light-to-heat-conversion (LTHC) adhesive layer, and such layer enables room temperature de-bonding from the carrier substrate by applying laser irradiation.

The RDL213is formed on the carrier substrate200or on the adhesive layer (not shown) on the surface of the carrier substrate200. In some embodiments, the RDL213includes conductive portions (or conductive via)213awhich penetrates through the RDL213. The conductive portions213amay be formed by a plating process or a photomask process or any other suitable processes. The conductive portions213amay include copper, aluminum, gold, silver, tin, or a compound including at least one of them.

Referring toFIG. 2B, after forming the RDL213on the carrier substrate200, the RDL215are formed on the RDL213. The RDL215may include antenna patches218aand a conductive portion215awhich serves as a chip-placement area. The antenna patches218aand the chip-placement area215aare made of conductive materials such as copper, aluminum, gold, silver, tin, or a compound including at least one of them. The conductive materials of the antenna patches218amay be the same or different from the chip-placement area215a, and the conductive materials of the RDL215may be the same or different from the materials of the RDL213. The RDL213and RDL215inFIG. 2A to 21may be the same as the RDL113and RDL115, respectively shown inFIG. 1.

The conductive portion215aof the RDL215may directly contact to the conductive portion213aof the RDL213. The techniques for forming the RDL215are not limited in the present disclosure.

Referring toFIG. 2C, the IC212is mounted on the conductive portion215aof the RDL215. The IC212may have an active side AS and a back side BS, where the back side BS is mounted on the conductive portion215aof the RDL215. In some embodiments of the disclosure, the back side BS of the IC212is mounted on the RDL215through a thermal paste layer TP1disposed between the IC212and the RDL215. The thermal paste layer TP1includes thermal paste that is configured to improve the thermal conductivity between the IC212and the RDL215, thereby improving the heat dissipation efficiency.

The active side AS of the IC212may have at least one connecting terminal or connecting pad212afor electrically connecting the IC212with other circuits. At least one passivation layer PL may be formed on the active side AS of the IC212, where the at least one passivation layer PL has at least one opening that expose the connecting pad212aof the IC212. The passivation layer PL may be formed on the IC212before mounting the IC212to the RDL215or after mounting the IC212to the RDL215. The IC212shown inFIG. 2A to 21may be the same as the IC112shown inFIG. 1.

Referring toFIG. 2D, a molding process is performed to form a molding layer216over the RDL215. The molding layer216may be the same as the molding layer116shown inFIG. 1. The molding layer216has molding compound that may be a protective resin such as, for example, an epoxy, polyimide or other dielectric composition. It should be noted that the molding compound is only provided on the area of the RDL215where the IC212is not occupied. In other words, the active side AS of the IC212is not encapsulated by the molding compound, but is exposed for further processing. In some embodiments of the disclosure, the thickness of the molding layer is substantially equal to the thickness of the IC212, but the disclosure is not limited thereto.

Referring toFIG. 2E, the RDL217is formed on the molding layer216and the IC212. The RDL217is electrically coupled to the IC212through the connecting pad212aof the IC212. The IC212may be coupled to other circuits outside the semiconductor package through the RDL217. The RDL217may include a plurality of conductive pads (not shown). The conductive pads are for example, under-ball metallurgy (UBM) patterns used for ball mount. In some other embodiments, the conductive pads (UBM patterns) are omitted.

Referring toFIG. 2F, the solder balls219are mounted to the RDL217so that the IC212is electrically coupled to the solder balls219through the RDL217. The RDL217and the solder balls219shown inFIG. 2may be the same as the RDL117and the solder balls119, respectively shown inFIG. 1.

Referring toFIG. 2G, the semiconductor package is flipped over (or turned up side down) and is placed on a tape300, where the solder balls219contact the tape300. The tape300may be formed of a material which withstands the subsequent processes. The tape300is detachable, and the tape300is removed from the semiconductor package after the completion of manufacturing process.

As shown inFIG. 2G, the carrier substrate200is de-bonded from the semiconductor package to expose the RDL213. In an embodiment where the adhesive layer is formed between the carrier substrate200and the RDL213, the carrier substrate200may be de-bonded by using laser irradiation.

Referring toFIG. 2H, the heat dissipation structure214is mounted on the exposed surface of the RDL213. In some embodiments of the disclosure, the heat dissipation structure214is mounted on the RDL213through a thermal paste layer TP2which is disposed between the heat dissipation structure214and the RDL213. The materials of the thermal paste layer TP2may be the same as or different from the material of the thermal paste layer TP1. The thermal paste layers TP1, TP2and the RDLs213and215forms a thermal dissipation path between the IC212and the heat dissipation structure214. As such, heat generated by the IC212is transferred to the heat dissipation structure214via the formed thermal path, and is dissipated by the heat dissipation structure214. In some embodiments, the heat generated by the IC212may be dissipated through structure214to an external heat dissipation structure of a device. For example, the external heat dissipation structure may be a LCD shield plate in the device, but the disclosure is not limited thereto. The device may include stationary and mobile computing devices such as mobile phone, cameras, television sets, and the like. It should be noted that the shape of the heat dissipation structure214as shown inFIG. 2His for illustration purpose only, any shape and structure of heat dissipation structure falls within the scope of the disclosure. The heat dissipation structure214may be the same as the heat dissipation structure114shown inFIG. 1.

InFIG. 2H, the antenna218is arranged side-by-side with the heat dissipation structure214. The antenna218may include at least one antenna patch218a, at least one antenna patch218b, a dielectric layer that is formed by at least one air cavity218cand a supporting frame218d. In the example shown inFIG. 2H, the cavity218cis the air cavity, but the disclosure is not limited thereto. The material to fill up the cavity218cmay be selected according to the designed requirements.

In some embodiments of the disclosure, the air cavity218cmay be for red by performing a chemical etching or physical cutting or any other suitable process which is capable of generating the air cavity between antenna patches. The antenna218as shown inFIG. 2A to 21may be the same as the antenna118shown inFIG. 1.

InFIG. 2I, the tape300is removed to get the semiconductor package210.

FIG. 3is a schematic flowchart indicating the manufacturing method of a semiconductor package in accordance with some embodiments of the disclosure. In step S310, a first redistribution layer (RDL) is provided on a carrier substrate. Step S310is illustrated inFIG. 2Bof the disclosure and is described above, thus the detailed description about step S310is omitted herein.

In step S320, an integrated circuit (IC) is mounted on a first surface of the first RDL. The steps S320is illustrated inFIG. 2Cof the disclosure and is described above, thus the detailed description about step S320is omitted herein.

In step S330, the heat dissipation structure is mounted on a second surface of the first RDL; and in step S340, an antenna is provided on the second surface of the first RDL, wherein the antenna is disposed side-by-side to the heat dissipation structure. The steps S330and S340are illustrated inFIG. 2DandFIG. 2H, and are described above, thus the detailed description about steps S330and S340are omitted herein.

In accordance with some embodiments of the disclosure, a semiconductor package includes an integrated circuit (IC), a heat dissipation structure, a molding compound, and an antenna. The IC is mounted on a first surface of a first redistribution layer (RDL). The heat dissipation structure is mounted on a second surface of the first RDL. The antenna is disposed on the second surface of the first RDL, wherein the antenna is disposed side-by-side to the heat dissipation structure.

In accordance with some embodiments of the disclosure, a semiconductor device includes a semiconductor package and a printed circuit board. The semiconductor package includes an integrated circuit (IC), a heat dissipation structure, and an antenna. The IC is mounted on a first surface of a first redistribution layer (RDL). The heat dissipation structure is mounted on a second surface of the first RDL. The antenna is disposed on the second surface of the first RDL, wherein the antenna is disposed side-by-side to the heat dissipation structure. The printed circuit board is connected to the semiconductor package by at least one solder ball.