Random number generation device and method of generating random numbers

A random number generation device includes: a plurality of first uniform random number generators configured to respectively generate a plurality of first uniform random numbers; a plurality of first normal random number generators configured to respectively generate a plurality of first normal random numbers based on the plurality of first uniform random numbers; a plurality of second uniform random number generators configured to perform a logical operation on bit values of two or more of the first uniform random numbers to respectively generate a plurality of second uniform random numbers; and at least one second normal random number generator configured to generate at least one second normal random number based on the plurality of second uniform random numbers.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2019475609, filed on Sep. 26, 2019, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a random number generation device and a method of generating random numbers,

BACKGROUND

A method is known in which, in a random number generation device that generates random numbers, an M-sequence cyclic code generator generates a seed value and sequentially supplies the seed value to a plurality of M-sequence cyclic code generators, thereby reducing the number of seed registers and suppressing an increase in the scale of hardware. In addition, a method is known in which bits of uniform random numbers generated by a plurality of uniform random number generators are rearranged to generate a plurality of uniform random numbers, and then the same terms of the uniform random numbers are summed to generate a normally distributed random numbers while avoiding correlation between sequences.

Related art is disclosed in Japanese Laid-open Patent Publication No. 2007-87064 and Japanese Laid-open Patent Publication No. 2005-38229.

SUMMARY

According to an aspect of the embodiments, a random number generation device includes: a plurality of first uniform random number generators configured to respectively generate a plurality of first uniform random numbers; a plurality of first normal random number generators configured to respectively generate a plurality of first normal random numbers based on the plurality of first uniform random numbers; a plurality of second uniform random number generators configured to perform a logical operation on bit values of two or more of the first uniform random numbers to respectively generate a plurality of second uniform random numbers; and at least one second normal random number generator configured to generate at least one second normal random number based on the plurality of second uniform random numbers.

DESCRIPTION OF EMBODIMENTS

Nowadays, in order to improve accuracy of calculation of various simulations and numerical analyses by the Monte Carlo method or the like, the number of normal random numbers used for calculation tends to increase, and the number of random number generation devices used for calculation tends to increase. As a result, the scale of the hardware of the random number generation devices mounted in the information processing apparatus that executes calculation such as simulation increases, and the cost for generating random numbers increases.

In one aspect, the present embodiment generates a larger number of normal random numbers while suppressing an increase in circuit scale.

FIG.1illustrates an example of a random number generation device according to an embodiment. The random number generation device100illustrated inFIG.1includes a normal random number generation units NGEN (NGEN1, NGEN2, NGEN3). The normal random number generation unit NGEN1includes a plurality of uniform random number generators10and a normal random number generator11. The normal random number generation unit NGEN2includes a plurality of uniform random number generators20and a normal random number generator21. The normal random number generation unit NGEN3includes a plurality of uniform random number generators30and a normal random number generator31.

The uniform random number generators10generate respective uniform random numbers URN1, and the normal random number generator11generates normal random numbers NRN1based on the uniform random numbers URN1generated by the respective uniform random number generators10. The uniform random number generators20generate respective uniform random numbers URN2, and the normal random number generator21generates normal random numbers NRN2based on the uniform random numbers URN2generated by the respective uniform random number generators20.

Each of the uniform random numbers URN1, URN2is an example of a first uniform random number, and each of the normal random numbers NRN1, NRN2is an example of a first normal random number. Uniform random numbers URN3are examples of a second uniform random number, and a normal random number NRN3is an example of a second normal random number. Each of the uniform random number generators10,20is an example of a first uniform random number generator, and each of the normal random number generators11,21is an example of a first normal random number generator. Each of the uniform random number generators30is an example of a second uniform random number generator, and the normal random number generator31is an example of a second normal random number generator.

The uniform random number generators30generate the respective uniform random numbers URN3based on two uniform random numbers URN1, URN2out of a plurality of uniform random numbers URN1and a plurality of uniform random numbers URN2generated by the uniform random number generators10,20. Although the uniform random number generators30each receive a single uniform random number URN1and a single uniform random number URN2inFIG.1, the uniform random number generator30may receive two uniform random numbers URN1or two uniform random numbers URN2.

For example, the uniform random number generators30each include a logical operation circuit (logical operation unit) that performs a bitwise bit operation on a plurality of bits of the uniform random numbers URN1, URN2. The normal random number generator31generates normal random numbers NRN3based on the uniform random numbers URN3generated by the respective uniform random number generators30.

For example, the random number generation device100includes twelve uniform random number generators10, twelve uniform random number generators20, and twelve uniform random number generators30. Thus, each of the normal random number generation units NGEN1, NGEN2, NGEN3are able to generate the normal random numbers NRN (NRN1, NRN2, NRN3) from the plurality of uniform random numbers URN1, URN2, URN3in accordance with the central limit theorem.

In the random number generation device100illustrated inFIG.1, the uniform random number generators30each generate the uniform random number URN3based on two uniform random numbers out of the uniform random numbers URN1, URN2generated by the uniform random number generators10,20. However, the uniform random number generator30may generate the uniform random number URN3based on three or more uniform random numbers URN (URN1, URN2, or URN1and URN2).

According to the present embodiment, the uniform random numbers URN3used to generate the normal random numbers NRN3are generated by using the uniform random numbers URN1, URN2generated by the uniform random number generators10,20. Thus, the uniform random number generators30may be configured as a simple circuit compared to that of the uniform random number generators10,20. This may allow downscaling of the circuit of the random number generation device100compared to that of other normal random number generation devices that generate the same number of normal random numbers NRN. For example, a larger number of normal random numbers NRN may be generated while suppressing the circuit scale of the random number generation device100. For example, when a circuit size (the number of logic gates or the like) usable for the random number generation device100is fixed, a large number of the normal random numbers NRN may be generated compared to other normal random number generation devices.

FIG.2illustrates an example of a system in which the random number generation device100illustrated inFIG.1is installed. A system210illustrated inFIG.2includes, for example, a server system300that functions as a cloud computer. The server system300includes a plurality of calculation servers310and a management server320that manages operations of the calculation servers310. The server system300is accessible from a plurality of user terminals500via a network NW such as the Internet.

Accordingly, for example, the user is able to cause the server system300to execute various types of information processing via the user terminal500. Examples of information processing executable by the server system300include, for example, numerical analyses, image processing, financial simulations, various simulations in the design of large-scale integration (LSI), and machine learning such as deep learning. The server system300may be used for Web search systems or cloud services.

For example, each of the calculation servers310includes a central processing unit (CPU), a plurality of graphics processing units (GPUs), and a plurality of field-programmable gate arrays (FPGAs). The calculation server310may include two or more CPUs mounted therein. For example, the GPUs and the FPGAs operate as accelerators based on instructions from the CPU. The calculation server310may include only FPGAs or may include FPGAs and a digital signal processor (DSP).

A plurality of random number generation devices100illustrated inFIG.1are provided in the FPGA by transferring circuit information of the random number generation device100to one or more FPGAs. The normal random numbers NRN1, NRN2, NRN3generated by the random number generation device100are used for, for example, numerical analyses, image processing, or various simulations.

According to the present embodiment, the circuit scale of the random number generation device100that generates normal random numbers may be reduced compared to the circuit scale of other random number generation devices. Thus, for example, a larger number of the random number generation devices100may be installed in an area for the random number generation device100allocated in the FPGA. Accordingly, even when the number of normal random numbers used for calculation is increased for improvement of accuracy of numerical calculation or the like, a problem in that the number of normal random numbers to be generated is insufficient may be suppressed. The random number generation device100may be installed in application-specific integrated circuits (ASICs) or the like mounted on the calculation server310.

For example, in a financial simulation, the number of normal random numbers to be used exponentially increases by increasing the number of stock brands. In an LSI design simulation, the number of normal random numbers to be used exponentially increases by increasing the number of parameters. In a cloud service in which an FPGA is mounted, for example, when a Monte Carlo simulation is executed in parallel by a large number of users (user terminals500), a large number of normal random numbers are used.

FIG.3illustrates another example of the system in which the random number generation device100illustrated inFIG.1is installed. A system220illustrated inFIG.3is a server system400that includes, for example, a plurality of calculation servers410and a management server420. The calculation servers410are coupled to each other via a system bus and coupled to the management server420via a management bus.

As is the case with the calculation servers310illustrated inFIG.2, the calculation servers410each include a CPU, a plurality of FPGAs, and a plurality of GPUs that function as accelerators. The calculation server410may include a DSP. A plurality of random number generation devices100illustrated inFIG.1are provided in the FPGA by transferring the circuit information of the random number generation device100to at least one FPGA, As is the case with the server system300illustrated inFIG.2, the normal random numbers NRN generated by the random number generation device100are used for numerical analyses, image processing, financial simulations, various simulations in LSI design, and machine learning such as deep learning.

As described above, according to the embodiment illustrated inFIGS.1to3, the uniform random number generator30may be configured as a simple circuit compared to the uniform random number generators10,20. This may reduce the circuit scale of the random number generation device100compared to the circuit scale of other normal random number generation devices. For example, a larger number of normal random numbers NRN may be generated while suppressing the circuit scale of the random number generation device100. Since the normal random number generation unit NGEN3includes twelve uniform random number generators30, the normal random number generation unit NGEN3is able to generate the normal random number NRN3from the plurality of uniform random numbers URN1, URN2in accordance with the central limit theorem.

FIG.4illustrates an example of a random number generation device according to another embodiment. Detailed description of the same elements as those illustrated inFIG.1is omitted. For example, a random number generation device102illustrated inFIG.4is provided in the FPGA or an ASIC (not illustrated) of the calculation server310illustrated inFIG.2or in the FPGA or an ASIC (not illustrated) of the calculation server410illustrated inFIG.3.

The random number generation device102includes three normal random number generation units NGEN (NGEN1, NGEN2, NGEN3). For example, the normal random number generation unit NGEN1includes twelve uniform random number generators10(#1to12) and an adder12. For example, the normal random number generation unit NGEN2includes 12 uniform random number generators20(#1to12) and an adder22. The adders12,22are examples of the first normal random number generator.

For clear understanding of description,FIG.4illustrates an example which the random number generation device102includes three normal random number generation units NGEN1to NGEN3. Actually, the random number generation device102includes a plurality of sets of three normal random number generation units NGEN1to NGEN3in accordance with a circuit area allocated in the FPGA. This allows the random number generation device102to generate a large number of normal random numbers NRN (NRN1, NRN2, NRN3).

In the normal random number generation unit NGEN1, the uniform random number generators10(#1to12) generate, based on seed values (not illustrated), twelve uniform random numbers URN1(#1to12) that are different from each other. Since there are different seed values for the different uniform random number generators10(#1to12), the twelve uniform random numbers URN1(#1to12) are not correlated to each other.

The adder12adds up a plurality of uniform random numbers URN1to generate a normal random number NRN1. For example, the adder12adds up twelve uniform random numbers URN1(#1to12) not correlated to each other. This allows generation of the normal random number NRN1by the central limit theorem.

In the normal random number generation unit NGEN2, the uniform random number generators20(#1to12) generate, based on seed values (not illustrated), twelve uniform random numbers URN2(#1to12) that are different from each other. Since there are different seed values for the different uniform random number generators20(#1to12), the twelve uniform random numbers URN2(#1to12) are not correlated to each other.

The adder22adds up a plurality of uniform random numbers URN2to generate a normal random number NRN2. For example, the adder22adds up twelve uniform random numbers URN2(#1to12) not correlated to each other. This allows generation of the normal random number NRN2in accordance with the central limit theorem.

For example, the normal random number generation unit NGEN3includes twelve exclusive OR circuits XOR1(#1to12) and an adder32. Each of the exclusive OR circuits XOR1is an example of the logical operation unit and an example of a first exclusive OR circuit. The adder32is an example of the second normal random number generator. Hereinafter, the exclusive OR circuit XOR1is also simply referred to as an XOR1.

Each of the XOR1s (#1to12) performs a logical operation on two uniform random numbers URN1generated by two uniform random number generators10or two uniform random numbers URN2generated by two uniform random number generators20, thereby generating a uniform random number URN3. For example, each of the XOR1s performs a bit operation of an exclusive OR on a plurality of bits of two uniform random numbers URN1(or URN2) bitwise, thereby generating the uniform random number URN3. For example, each of the XOR1s takes an exclusive OR of the bit values of the same bit numbers in two uniform random numbers URN1(or URN2), thereby generating bit values of the uniform random number URN3.

For example, inFIG.4, the XOR1(#1) generates the uniform random number URN3(#1) based on the uniform random numbers URN1(#1, #2), and the XOR1(#2) generates the uniform random number URN3(#2) based on the uniform random numbers URN1(#3, #4). The XOR1(#6) generates the uniform random number URN3(#6) based on the uniform random numbers URN1(#11/#12). When the variable n is any of 1 to 6, the XOR1(#n) generates the uniform random number URN3(#n) based on the uniform random numbers URN1(#2n-1) and URN1(#2n).

The XOR1(#7) generates the uniform random number URN3(#7) based on the uniform random numbers URN2(#1, #2), and the XOR1(#8) generates the uniform random number URN3(#8) based on the uniform random numbers URN2(#3, #4). The XOR1(#12) generates the uniform random number URN3(#12) based on the uniform random numbers URN2(#11, #12). When the variable n is any of 7 to 12, the XOR1(#n) generates the uniform random number URN3(#n) based on the uniform random numbers URN2(#2(n-6)-1) and URN2(#2(n-6)).

The two uniform random numbers (URN1or URN2) supplied to any one of the XOR1s (#1to12) are generated based on different seed values, and accordingly, not correlated to each other. it has been confirmed that the XOR1(any one of #1to12) generates the uniform random number URN3correlated to neither of two uniform random numbers when the two uniform random numbers having been input are not correlated to each other.

The adder32adds up a plurality of uniform random numbers URN3to generate a normal random number NRN3. For example, the adder32adds up twelve uniform random numbers URN3(#1to12) not correlated to each other. This allows generation of the normal random number NRN3in accordance with the central limit theorem.

For example, the uniform random number generators10,20are provided by utilizing Xorshift128, which is one of pseudorandom number generators. The uniform random number generators10,20by the Xorshift128include, for example, four exclusive OR circuits (XORs) coupled in series. When the XOR includes four NAND gates, each of the uniform random number generators10,20with Xorshift128includes 16 NAND gates. Accordingly, a logic scale of the normal random number generation unit NGEN1except for the logic of the adder12corresponds to a logic scale of 192 NAND gates. Likewise, a logic scale of the normal random number generation unit NGEN2except for the logic of the adder22corresponds to a logic scale of 192 NAND gates.

The normal random number generation unit NGEN3except for the logic of the adder32includes twelve XOR1s, corresponding to a logic scale of48NAND gates. Therefore, the logic scale of the uniform random number generator10,20and the XOR1s of the random number generation device102is432(192+192+48) in terms of NAND gates.

When the normal random number generation unit NGEN3is configured with twelve uniform random number generators10as is the case with the normal random number generation unit NGEN1, the logic scale of the normal random number generation unit NGEN3except for the logic scale of the adder32corresponds to the logic scale of192NAND gates. In this case, the logic scale of the normal random number generation device including three normal random number generation units NGEN1, NGEN2, NGEN3of the same logic configurations is576(192+192+192) in terms of NAND gates. Accordingly, the logic scale of the random number generation device102except for the adders12,22,32is able to be reduced by 25% ((576-432)/576) compared to the logic scale of a normal random number generation device including three normal random number generation units that are identical to each other.

As has been described, according to the embodiment illustrated inFIG.4, as is the case with the embodiment illustrated inFIG.1, the uniform random numbers URN1, URN2generated by the uniform random number generators10,20are used to generate the uniform random number URN3by using the XOR1s which are a type of the logical operation unit. Accordingly, the circuit scale of the uniform random number generators (XOR1s) that generate twelve uniform random numbers URN3to be supplied to the adder32is able to be reduced compared to the circuit scale of the twelve uniform random number generators10(or20). As a result, a larger number of normal random numbers NRN1, NRN2, NRN3may be generated while suppressing the circuit scale of the random number generation device102.

According to the present embodiment, the uniform random numbers URN1, URN2generated by the uniform random number generators10,20are used to generate the uniform random number URN3by using the XOR1s, and the normal random number NRN3is generated by adding up the uniform random numbers URN1, URN2, URN3. Thus, the normal random numbers NRN3conforming to a high-quality normal distribution may be generated in accordance with the central limit theorem.

FIG.5illustrates an example of a random number generation device according to another embodiment. Elements similar to or the same as those illustrated inFIG.4are denoted by the same reference signs and detailed description thereof is omitted. For example, a random number generation device104illustrated inFIG.5is provided in the FPGA or the ASIC (not illustrated) of the calculation server310illustrated inFIG.2or in the FPGA or the ASIC (not illustrated) of the calculation server410illustrated inFIG.3. The random number generation device104includes three normal random number generation units NGEN1, NGEN2, NGEN3. Since the normal random number generation units NGEN1, NGEN2have the same configuration as those of the normal random number generation units NGEN1, NGEN2illustrated inFIG.4, illustration thereof is omitted.

For example, the normal random number generation unit NGEN3includes eight XOR1s, four XOR2s, and the adder32. Each of the XOR1s is an example of the first exclusive OR circuit, and each of the XOR2s is an example of a second exclusive OR circuit. For example, each of the XOR1s generates the uniform random number URN3based on two uniform random numbers URN1generated by two uniform random number generators10(FIG.4) or two uniform random numbers URN2generated by two uniform random number generators20(FIG.4).

Each of the XOR2s generates a uniform random number URN4based on two uniform random numbers URN3generated by 2 XOR1s. For example, each of the XOR2s performs a bit operation of an exclusive OR on a plurality of bits of two uniform random numbers URN3bitwise, thereby generating the uniform random number URN4. For example, each of the XOR2s takes an exclusive OR of the bit values of the same bit numbers in two uniform random numbers URN3, thereby generating bit values of the uniform random number URN4.

The adder32adds up a plurality of uniform random numbers URN3, URN4to generate the normal random number NRN3. For example, the adder22adds up twelve uniform random numbers URN3, URN4not correlated to each other. This allows generation of the normal random number NRN3in accordance with the central limit theorem. For example, it is confirmed in advance that the uniform random numbers URN4generated by the XOR2s are not correlated to the URN3generated by the XOR1s or any one of the URN4is not correlated to another UNR4by giving various seed values to the uniform random number generators10,20(FIG.4).

FIG.6illustrates an example of the scale of the circuit used for generating the normal random number NRN3in the random number generation device104illustrated inFIG.5.FIG.6illustrates a configuration of a circuit that generates two normal random numbers NRN1, two normal random numbers NRN2, and three normal random numbers NRN3. In this case, the circuit scale of the24uniform random number generators10,24uniform random number generators20, and 36 XOR1s and XOR2s included in the random number generation device104is912in terms of NAND gates.

When 36 uniform random number generators10are provided instead of the 36 XOR1s and XOR2s, the circuit scale of the random number generation device is1344in terms of NAND gates. Accordingly, the logic scale of the random number generation device104except for the adders12,22,32is able to be reduced by 32% ((1344-912)11344) compared to the logic scale of a normal random number generation device including seven normal random number generators that are identical to each other.

As has been described, according to the embodiment illustrated inFIGS.5and6, a larger number of normal random numbers NRN may be generated while further suppressing the circuit scale of the random number generation device104compared to the embodiments illustrated inFIGS.1and4. Furthermore, the normal random numbers NRN3conforming to a high-quality normal distribution may be generated in accordance with the central limit theorem when the uniform random numbers URN3, URN4used to generate the normal random numbers NRN3are generated by using the XOR1s and XOR2s.

FIG.7illustrates an example of a random number generation device according to another embodiment. Elements similar to or the same as those illustrated inFIG.4are denoted by the same reference signs and detailed description thereof is omitted. For example, a random number generation device106illustrated inFIG.7is provided in the FPGA or the ASIC (not illustrated) of the calculation server310illustrated inFIG.2or in the FPGA or the ASIC (not illustrated) of the calculation server410illustrated inFIG.3. The random number generation device106includes three normal random number generation units NGEN1, NGEN2, NGEN3. The normal random number generation units NGEN1, NGEN2have the same configuration as those of the normal random number generation units NGEN1, NGEN2illustrated inFIG.4.

In the normal random number generation unit NGEN3, cyclic shifters CSFT1are coupled to inputs of each of the XOR1s of the normal random number generation unit NGEN3illustrated inFIG.4. Each of the shifters CSFT1is an example of a first shifter. The configuration of the random number generation device106is similar to or the same as that of the random number generation device102illustrated inFIG.4except for addition of the shifters CSFT1.

Each of the shifters CSFT1cyclically shifts the bits of the uniform random number URN1(or URN2) output from the uniform random number generator10(or20) and outputs the shifted uniform random number URN1(or URN2) to the XOR1. The number of bits to be shifted in24shifters CSFT corresponding to a single adder32may be equal to each other or different from each other.

According to the present embodiment, the uniform random numbers URN1(or URN2) are input to the XOR1s via the cyclic shifters CSFT. Accordingly, for example, even when the uniform random number generators10(or20) generate the uniform random numbers URN1(or URN2) based on the same seed value, twelve uniform random numbers URN3are able to be generated with the correlation therebetween abolished. The number of bits to be shifted by the shifters CSFT is predetermined so that the uniform random numbers URN3respectively generated by a plurality of the XOR1s are not correlate to each other. Thus, the normal random numbers NRN3conforming to a high-quality normal distribution may be generated in accordance with the central limit theorem,

With the shifters CSFT1, the circuit scale of the random number generation device106becomes larger than the circuit scale of the random number generation device102illustrated inFIG.4. However, with the shifters CSFT1, for example, even when the uniform random number generators10(or20) use a common seed value, the correlation between the uniform random numbers URN1, URN2used for generating the normal random numbers NRN3may be lowered. Thus, for example, a generation circuit that generates a plurality of seed values may be omitted, and a larger number of normal random numbers NRN3conforming to a high-quality normal distribution may be generated while suppressing an increase in the circuit scale when the entirety of the random number generation device106is seen.

As has been described, according to the embodiment illustrated inFIG.7, for example, even when the uniform random numbers URN1, URN2are generated based on the same seed value, twelve uniform random numbers URN3the correlation between which are abolished may be generated by coupling the cyclic shifters CSFT to the inputs of the XOR1s. As a result, a larger number of normal random numbers NRN3conforming to a high-quality normal distribution may be generated while suppressing an increase in the circuit scale.

FIG.8illustrates an example of a random number generation device according to another embodiment. Elements similar to or the same as those of the above-described embodiments are denoted by the same reference signs and detailed description thereof is omitted. For example, a random number generation device108illustrated inFIG.8is provided in the FPGA or the ASIC (not illustrated) of the calculation server310illustrated inFIG.2or in the FPGA or the ASIC (not illustrated) of the calculation server410illustrated inFIG.3.

In the normal random number generation unit NGEN3, cyclic shifters CSFT2are coupled to inputs of each of the XOR2s of the normal random number generation unit NGEN3illustrated inFIG.5. Each of the shifters CSFT2is an example of a second shifter. The configuration of the random number generation device108is similar to or the same as that of the random number generation device104illustrated inFIG.5except for addition of the shifters CSFT2.

Each of the shifters CSFT2cyclically shifts the bits of the uniform random number URN3output from the XOR1and outputs the shifted uniform random number URN3to the XOR2. The number of bits to be shifted in 16 shifters CSFT1and eight shifters CSFT2corresponding to a single adder32may be equal to each other or different from each other. The numbers of bits to be shifted by the shifters CSFT1, CSFT2are predetermined so that the uniform random numbers URN3, URN4respectively generated by a plurality of the XOR1s and a plurality of the XOR2s are not correlate to each other, Thus, the normal random numbers NRN3conforming to a high-quality normal distribution may be generated in accordance with the central limit theorem.

According to the present embodiment, as is the case with the random number generation device106illustrated inFIG.7, even when the uniform random number generators10,20generate the uniform random numbers URN1, URN2based on the same seed value, twelve uniform random numbers URN3, URN4are able to be generated with the correlation therebetween abolished.

As is the case with the random number generation device104illustrated inFIG.5, each of the XOR2s generates a different uniform random number URN4by using the uniform random numbers URN3generated by the XOR1s. Thus, a larger number of uniform random numbers URN3, URN4may be generated by a small number of uniform random number generators10,20.

FIG.9illustrates an example of a random number generation device according to another embodiment. Elements similar to or the same as those of the above-described embodiments are denoted by the same reference signs and detailed description thereof is omitted. For example, a random number generation device110illustrated inFIG.9is provided in the FPGA or the ASIC (not illustrated) of the calculation server310illustrated inFIG.2or in the FPGA or the ASIC (not illustrated) of the calculation server410illustrated inFIG.3.

The normal random number generation unit NGEN3has a configuration in which the cyclic shifters CSFT1are, similarly to those illustrated inFIG.7, added to inputs of each of the XOR1s of the normal random number generation unit NGEN3illustrated inFIG.8. According to the present embodiment, the effects similar to those of the embodiments illustrated inFIGS.7and8may be obtained.

Regarding the embodiments illustrated inFIGS.1to9, the following appendices are further disclosed.

Features and advantages of the embodiments will be apparent from the foregoing detailed description. The scope of claims is intended to cover the features and advantages of the embodiments as described above without departing from the spirit and scope of the claims. Any person skilled in the art may readily conceive of any improvements and changes. Accordingly, there is no intention to limit the scope of the inventive embodiments to those described above, and it is possible to rely on appropriate modifications and equivalents included in the scope disclosed in the embodiments.