MEMORY SYSTEM AND METHOD OF OPERATING THE SAME

A memory system for efficiently processing data in performing a job may include a plurality of memory devices configured to store data, a main data processor configured to access the plurality of memory devices, a sub data processor group including a plurality of sub data processors each configured to access the plurality of memory devices, respectively, a host interface configured to receive, from a host, a request for a job, and a job controller configured to perform the job by using one of the main data processor and the sub data processor group depending on whether accesses to the plurality of memory devices are related to each other for the job.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2022-0180903 filed on Dec. 21, 2022, the entire disclosure of which is incorporated by reference herein.

BACKGROUND

1. Field of Invention

Various embodiments of the present disclosure generally relate to a semiconductor device, and more particularly to data processing in performing a job in a memory system.

2. Description of Related Art

A memory system is a semiconductor system or a semiconductor device for storing data under the control of a host. A computational memory solution (CMS) which integrates a computer express link (CXL)-based memory with a calculation function may be applied to the memory system. Accordingly, the memory system may have an increased data processing rate by not only storing data but also by performing calculation of the data.

The memory system may include a processor unit for performing the calculation function. In this case, there may be a difference in accessibility to the memory device, data access rate, etc., depending on the position of the processor unit in the memory system.

SUMMARY

Various embodiments of the present disclosure are directed to a memory system and a method of operating the memory system, which are capable of efficiently processing data in performing a job.

An embodiment of the present disclosure may provide for a memory system. The memory system may include a plurality of memory devices configured to store data, a main data processor configured to access the plurality of memory devices, a sub data processor group including a plurality of sub data processors each configured to access the plurality of memory devices, respectively, a host interface configured to receive, from a host, a request for a job, and a job controller configured to perform the job using one of the main data processor and the sub data processor group depending on whether accesses to the plurality of memory devices are related to each other for the job.

An embodiment of the present disclosure may provide for a method of operating a memory system. The method may include receiving, from a host, a request for a job, determining whether processes of data stored in a plurality of memory devices are related to each other for the job, performing the job by using one of a main data processor and a sub data processor group including a plurality of sub data processors according to a result of the determining, and providing, to the host, a result of performing the job.

An embodiment of the present disclosure may provide for a memory system. The memory system may include a plurality of memory devices, a main controller chip including a main data processor configured to access the plurality of memory devices, and a plurality of sub controller chips each including a sub data processor configured to access the plurality of memory devices, respectively, and communicate with the main controller chip through an internal interface.

An embodiment of the present disclosure may provide for a memory system including: a plurality of memory devices; a main data processor coupled to a host at a first distance; a plurality of sub data processors coupled to the host at a second distance longer than the first distance; and a job controller configured to: receive, from a host, a request associated with a job; determine whether the job is related to accesses to all of the plurality of memory devices; when it is determined that the job is related to accesses to all of the plurality of memory devices, control the main data processor to perform the job for the plurality of memory devices; and when it is determined that the job is related to an access to a memory device selected from among the plurality of memory devices, control a sub data processor corresponding to the selected memory device to perform the job for the selected memory device.

DETAILED DESCRIPTION

Specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification are only for description of the embodiments of the present disclosure. The descriptions should not be construed as being limited to the embodiments described in the specification.

FIG.1is a diagram illustrating an example of a memory system1000aaccording to an embodiment of the present disclosure.

Referring toFIG.1, the memory system1000amay include a system controller100and a plurality of memory devices200-1to200-n.

The system controller100may control general operation of the memory system1000a.

In an embodiment of the present disclosure, the system controller100may be implemented as a system on chip (SoC).

In an embodiment of the present disclosure, the system controller100may include a system processor110, a system memory120, a host interface130, a main data processor140, a plurality of memory controllers150-1to150-n,and a communication bus160.

The system processor110may control operation of the system controller100.

In an embodiment of the present disclosure, the system processor110may include a job controller111.

In an embodiment of the present disclosure, the job controller111may determine a data processor to perform a job in response to a request for the job from a host. For example, the job controller111may determine a data processor to perform the job depending on whether accesses to the plurality of memory devices200-1to200-nare related to each other for the job.

Furthermore, the job controller111may control the job to be performed by using the determined data processor. In this case, the data processor may be one of the main data processor140and the sub data processor group SUB GROUP.

The system memory120may store various pieces of information required for an operation of the system controller100in the form of firmware.

The host interface130may communicate with the host. For example, the host interface130may receive a request for a job from the host, and provide a result of the job to the host in response to the request.

In an embodiment of the present disclosure, the request for the job may include at least one of a type of the job, query data of the job and an address of an area in which data used for the job is stored. The type of the job may include various jobs for which a calculation function of the memory system1000ais used, such as page rank, embedding, filtering, aggregation, etc. The query data of the job corresponds to various pieces of information used for the job, which may include a condition of the job, target data of the job, etc. The address may be information representing an address of a memory cell that stores data. In an embodiment, the request for the job may include various pieces of information relating to the job in addition to the aforementioned information.

The main data processor140may be a processor for performing the job.

In an embodiment of the present disclosure, the main data processor140is able to access the plurality of memory devices200-1to200-n.For example, the main data processor140may read data from the plurality of memory devices200-1to200-nand process the data.

In an embodiment, the main data processor140may be located in an area of the memory system1000aadjacent to the host. For example, the main data processor140may have a relatively short access distance to the host, compared with a plurality of sub data processors151-1to151-n.In this case, the access distance may refer to a physical distance, a communication distance, etc.

The plurality of memory controllers150-1to150-nmay control the plurality of memory devices200-1to200-n,respectively. For example, the plurality of memory controllers150-1to150-nmay control a read operation of reading data stored in the plurality of memory devices200-1to200-n,respectively. The plurality of memory controllers150-1to150-nmay transmit data, a command to instruct an operation, an address, etc., to the plurality of memory devices200-1to200-nor receive data from the plurality of memory devices200-1to200-nthrough a memory interface (not illustrated).

In an embodiment of the present disclosure, the plurality of memory controllers150-1to150-nmay include the plurality of sub data processors151-1to151-n,respectively.

The plurality of sub data processors151-1to151-nare processors for performing a job, and may be included in a sub data processor group SUB GROUP.

In an embodiment of the present disclosure, the plurality of sub data processors151-1to151-nis able to access the plurality of memory devices200-1to200-n,respectively. For example, each of the plurality of sub data processors151-1to151-nmay read data from the accessible memory device and process the data.

In an embodiment, each of the plurality of sub data processors151-1to151-nmay be located in an area adjacent to the accessible memory device. For example, the plurality of sub data processors151-1to151-nmay have a relatively short access distance to the plurality of memory devices200-1to200-n,compared with the main data processor140.

In an embodiment, the main data processor140and the plurality of sub data processors151-1to151-nmay be devices such as a near data processor (NDP), which performs various calculation operations based on the data.

The system processor110, the system memory120, the host interface130, the main data processor140and the plurality of memory controllers150-1to150-nmay communicate via the communication bus160. In an embodiment of the present disclosure, the communication bus160may have a bandwidth wider than bandwidths allocated to the plurality of memory controllers150-1to150-ncombined.

The plurality of memory devices200-1to200-nmay store data. Each of the plurality of memory devices200-1to200-nmay include a plurality of memory cells for storing data.

FIG.2is a diagram illustrating an example of performing a job by a main data processor140according to an embodiment of the present disclosure.

Referring toFIG.2, at operation S21, the host interface130may receive a request REQ for a job from the host. Accesses to the plurality of memory devices200-1to200-nare related to each other for the job, and the job may be performed by the main data processor140. In an embodiment, the main data processor140may perform the job by processing data stored in each of the plurality of memory devices200-1to200-n.

At operation S22, the main data processor140may read data DATA from the plurality of memory devices200-1to200-nthrough the plurality of memory controllers150-1to150-n.

At operation S23, the main data processor140may process the data DATA according to the job. For example, the main data processor140may perform various calculation operations involved in the job based on the data read from the plurality of memory devices200-1to200-n.

At operation S24, the host interface130may provide, to the host, a result RESULT of the job performed by the main data processor140in response to the request REQ.

In an embodiment, whether accesses to the plurality of memory devices200-1to200-nare related to each other for the job may correspond to whether processes of the data stored in the plurality of memory devices200-1to200-nare related to each other. For example, when processes of the data stored in the plurality of memory devices200-1to200-nare dependent on each other, accesses to the plurality of memory devices200-1to200-nmay be related to each other. In an example, when processes of the data stored in the plurality of memory devices200-1to200-nare independent from each other, accesses to the plurality of memory devices200-1to200-nmay not be related to each other.

An example in which accesses to the plurality of memory devices200-1to200-nare related to each other is described in detail with reference toFIGS.3A,3B and4.

FIGS.3A and3Bare diagrams illustrating an example in which accesses to a plurality of memory devices are related to each other for a job according to an embodiment of the present disclosure.

Referring toFIG.3A, an example of performing one of the types of the job, i.e., page rank, is illustrated. Page rank may be an algorithm that gives a weight to a document having a hyperlink structure such as the world wide web depending on the relative importance.

What is illustrated on the left ofFIG.3Amay represent a graph used for page rank. The graph may include nodes and links connecting the nodes. InFIG.3A, there are nodes from node0to node7. When a page rank calculation is performed on node3, page rank scores for course A, course B and course C may be calculated.

What is illustrated on the right ofFIG.3Amay represent a sequence in which data is processed when the page rank calculation is performed on node3. For example, to perform the page rank calculation on node3, data is processed in the reverse order of course A, data is processed in the reverse order of course B, and data is processed in the reverse order of course C. This may be because a data process for a node at a starting point of the link of each course is dependent on a data process for a node in an ending direction of the link. For example, in course B, a data process for node1may need to precede the data process for node3. In this case, data for each node may represent a weight for the node.

Referring toFIG.3B, an example of accessing the plurality of memory devices200-1to200-nto calculate a page rank score for course C ofFIG.3Ais illustrated. For example, to calculate the page rank score for course C, data may be read sequentially from data for node3to data for node1.

Specifically, at operation S31, the main data processor140may read data for node3from the memory device200-2and process the data.

At operation S32, the main data processor140may read data for node5from the memory device200-3and process the data. The main data processor140may process the data for node5by referring to a result of the data process for node3.

At operation S33, the main data processor140may read data for node7from the memory device200-4and process the data. The main data processor140may process the data for node7by referring to a result of the data process for node5.

At operation S34, the main data processor140may read data for node6from the memory device200-4and process the data. The main data processor140may process the data for node6by referring to a result of the data process for node7.

At operation S35, the main data processor140may read data for node4from the memory device200-3and process the data. The main data processor140may process the data for node4by referring to a result of the data process for node6.

At operation S36, the main data processor140may read data for node2from the memory device200-2and process the data. The main data processor140may process the data for node2by referring to a result of the data process for node4.

At operation S37, the main data processor140may read data for node0from the memory device200-1and process the data. The main data processor140may process the data for node0by referring to a result of the data process for node2.

At operation S38, the main data processor140may read data for node1from the memory device200-1and process the data. The main data processor140may process the data for node1by referring to a result of the data process for node0.

FIG.4is a diagram illustrating an example in which accesses to a plurality of memory devices are related to each other for a job according to an embodiment of the present disclosure.

Referring toFIG.4, an example of performing one of the types of the job, i.e., embedding, is illustrated. In this example, embedding may be an algorithm to change categorical data into a numerical vector.

Index0, index2and index4in an embedding table are received from the host while receiving a request for embedding from the host. The embedding table may be a table including a plurality of embedding vectors.

At operation S41, the main data processor140may read an embedding vector (vector0) corresponding to index0from the memory device200-1, an embedding vector (vector2) corresponding to index2from the memory device200-2and an embedding vector (vector4) corresponding to index4from the memory device200-3.

At operation S42, the main data processor140may perform an embedding calculation using the embedding vectors read (i.e., vector0, vector2and vector4). In an embodiment, embedding vectors stored in the respective memory devices are required for the embedding calculation, and thus, accesses to the plurality of memory devices200-1,200-2and200-3may be related to each other.

FIG.5is a diagram illustrating an example of performing a job by a sub data processor group according to an embodiment of the present disclosure.

Referring toFIG.5, at operation S51, the host interface130may receive a request REQ for a job from the host. When accesses to the plurality of memory devices200-1to200-nare not related to each other for the job, the job may be performed with the plurality of sub data processors151-1to151-n.In an embodiment, the job may be divided and sent to the plurality of sub data processors151-1to151-n.The plurality of sub data processors151-1to151-nmay process data stored in the respectively accessible memory devices200-1to200-nin parallel to perform the job.

At operation S52, the plurality of sub data processors151-1to151-nmay read data DATA from the respectively accessible memory devices200-1to200-n.

At operation S53, the plurality of sub data processors151-1to151-nmay process the data DATA according to the job. For example, the plurality of sub data processors151-1to151-nmay perform various calculation operations involved in the job based on the data DATA read.

At operation S54, the main processor140may receive data process results SUB RESULTS from the plurality of sub data processors151-1to151-n.

At operation S55, the main processor140may combine the data process results SUB RESULTS of the plurality of sub data processors151-1to151-nto generate a process result MAIN RESULT.

At operation S56, the host interface130may provide, to the host, the process result MAIN RESULT combined by the main data processor140in response to the request REQ.

FIG.6is a flowchart illustrating a method of operating a memory system according to an embodiment of the present disclosure.

The method illustrated inFIG.6may be performed by the memory system1000aillustrated inFIG.1or a memory system1000billustrated inFIG.7, which will be described later. In the illustrated example ofFIG.6, the memory system1000aillustrated inFIG.1will be described.

At operation S601, the memory system1000amay receive a request for a job from the host.

At operation S603, the memory system1000amay determine whether processes of data stored in the plurality of memory devices are related to each other for the job.

When it is determined that the processes of data are related to each other (S603-YES), the memory system1000amay proceed to operation S605.

At operation S605, the memory system1000amay perform the job with the main data processor.

When it is determined that the processes of data are not related to each other (S603-NO), the memory system1000amay proceed to operation S607.

At operation S607, the memory system1000amay perform the job with the sub data processor group.

At operation S609, after performing S605or S607, the memory system1000amay provide a result of the job to the host.

FIG.7is a diagram illustrating an example of a memory system1000baccording to an embodiment of the present disclosure.

Referring toFIG.7, the memory system1000bmay include a system controller700including the system processor110, the system memory120, the host interface130, the main data processor140, the plurality of memory controllers150-1to150-n,the communication bus160, and the plurality of memory devices200-1to200-n.The aforementioned operations associated withFIG.1will be equally applied to the system processor110, the system memory120, the host interface130, the main data processor140, the plurality of memory controllers150-1to150-n,the communication bus160, and the plurality of memory devices200-1to200-nillustrated inFIG.7.

In an embodiment of the present disclosure, the system controller700may include a main controller chip710and a plurality of sub controller chips720-1to720-n.The main controller chip710and the plurality of sub controller chips720-1to720-nmay each be implemented as a SoC.

The main controller chip710may include the system processor110, the system memory120, the host interface130, the main data processor140, the communication bus160and a plurality of first internal interfaces711-1to711-n.

The plurality of sub controller chips720-1to720-nmay include the plurality of memory controllers150-1to150-nand a plurality of second internal interfaces721-1to721-n.

The main controller chip710and the plurality of sub controller chips720-1to720-nmay communicate through the plurality of first internal interfaces711-1to711-nand the plurality of second internal interfaces721-1to721-n.

In an embodiment of the present disclosure, the plurality of first internal interfaces711-1to711-nand the plurality of second internal interfaces721-1to721-nmay perform communication in a serial scheme.

In accordance with the present disclosure, a memory system and a method of operating the memory system, which are capable of efficiently processing data in performing a job is provided.

Furthermore, in accordance with the present disclosure, semiconductor silicon characteristics related to routing may be improved by adding each of a main data processor and a plurality of sub data processors to a separate chip.

It should be noted that although the technical spirit of this disclosure has been described in connection with embodiments thereof, this is merely for description purposes and should not be interpreted as limiting. It should be appreciated by one of ordinary skill in the art that various changes may be made thereto without departing from the technical spirit of the disclosure and the following claims.