Write driver, variable resistance memory apparatus including the same, and operation method

A write driver is configured to determine a magnitude and an application time of a pre-emphasis current pulse in response to control codes generated according to parasitic components on a path from a write driver to a program target cell and a resistance value of the program target cell, and supply a preset program current to a memory circuit block by adding a pre-emphasis current to the preset program current in a program mode.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2014-0100444, filed on Aug. 8, 2014, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor integrated circuit, and more particularly, to a write driver, a variable resistance memory apparatus including the same, and an operation method.

2. Related Art

Among nonvolatile memories, variable resistance memory elements such as the phase change RAM and the resistive RAM define information storage states according to the resistant state of the data storage material. In the variable resistance memory elements, program current is applied in a program operation in such a manner that the data storage material may have a desired resistant state.

A decrease in a rising slope of the program current pulse means that a required amount of current is not transferred to a target cell and target data is not written. Therefore, in order to write the target data, it is necessary to repeat program and verify processes several times.

Under this situation, a method of compensating for a program current pulse in consideration of a time constant determined according to a path from a write driver to a cell may be adopted. However, if only a time constant determined according to a path from a write driver to a cell is considered, an overshoot phenomenon is likely to occur according to the resistant state of the cell before program.

SUMMARY

In an embodiment, a write driver may be configured to determine a magnitude and an application time of a pre-emphasis current pulse in response to control codes generated according to parasitic components existing on a path from a write driver to a program target cell and a resistance value of the program target cell. In addition, the write driver may be configured to supply a preset program current to a memory circuit block by adding a pre-emphasis current to the preset program current in a program mode.

In an embodiment, a variable resistance memory apparatus may include a memory circuit block including a plurality of variable resistance memory cells. The variable resistance memory apparatus may also include a controller configured to generate control codes according to parasitic components on a path from a write driver to a program target cell and a resistance value of the program target cell in a write mode. In addition, the variable resistance memory apparatus may include a write driver configured to determine a magnitude and an application time of a pre-emphasis current pulse in response to the control codes, and supply a preset program current to the memory circuit block by adding a pre-emphasis current to the preset program current.

In an embodiment, a program method of a variable resistance memory apparatus may include reading a resistance value of a program target cell in response to a write command. The program method may also include generating control codes according to parasitic components on a path from a write driver to the program target cell and the resistance value of the program target cell. Further, the program method may include supplying a pre-emphasis current pulse with a magnitude and an application time determined according to the control codes to the program target cell by adding the pre-emphasis current pulse to program current.

DETAILED DESCRIPTION

Hereinafter, a write driver, a variable resistance memory apparatus including the same, and an operation method will be described below with reference to the accompanying drawings through various examples.

Referring toFIG. 1, a configuration diagram illustrating a representation of an example of a variable resistance memory apparatus in accordance with an embodiment is shown.

A variable resistance memory apparatus10may include a memory circuit block200, a controller110, a read circuit block120, and a write driver130.

The memory circuit block200may have a plurality of variable resistance memory cells electrically coupled between word lines and bit lines, and a row selection unit and a column selection unit to access the respective memory cells.

The controller110may receive a command, an address and data from an exterior. In addition, the controller110may program the data in the memory circuit block200by controlling the write driver130. Further, the controller110may receive a command and an address from the exterior, read data from the memory circuit block200by controlling the read circuit block120, and output read data to the exterior.

More specifically, in a program operation, the controller110reads in advance the resistant state of a target cell by controlling the read circuit block120. Further, a control code generation unit1110provided in the controller110generates control codes to control a pre-emphasis current pulse, based on the parasitic components existing on the path from the write driver130to the target cell and the resistant state of the target cell which is read in advance.

In an embodiment, the control code generation unit1110may determine the pulse magnitude and the pulse application time (the pulse width) of pre-emphasis current, based on the parasitic components existing on the path to the target cell and the resistant state of the target cell.

In an embodiment, the control code generation unit1110may preset the magnitude of a pre-emphasis current pulse. In addition, the control code generation unit1110may generate the control codes such that the application time of the pre-emphasis current pulse may be changed according to the parasitic components existing on the path from the write driver130to the target cell and the resistant state of the target cell.

Further, the control code generation unit1110may set the magnitude of the pre-emphasis current pulse in such a way as to become different according to the distance from the write driver130to the target cell. Further, the control code generation unit1110may generate the control codes such that the application time of the pre-emphasis current pulse may be changed based thereon.

In an embodiment, the control code generation unit1110may calculate in advance the application time of the pre-emphasis current pulse according to a preset standard. The control code generation unit1110may also generate the control codes such that the magnitude of the pre-emphasis current pulse may be changed according to the parasitic components existing on the path from the write driver130to the target cell and the resistant state of the target cell.

The write driver130may perform the program operation by supplying the pre-emphasis current determined according to the control codes to the target cell along with preset program current.

Referring toFIG. 2, a configuration diagram illustrating a representation of an example of the control code generation unit1110shown inFIG. 1is illustrated.

The control code generation unit1110may be configured to include a first control code generation circuit1111and a second control code generation circuit1113.

The first control code generation circuit1111generates first control codes CODE1<0:x> based on control information CTR_IF and a resistant state PRE_RD of the target cell. The control information CTR_IF may include preset program current IPGM. The control information CTR_IF may also include the parasitic components existing on the path from the write driver130to the target cell, for example, parasitic resistance RPand parasitic capacitance CP. In an embodiment, the first control codes CODE1<0:x> may be configured to determine the magnitude, or, the level, of the pre-emphasis current pulse.

The second control code generation circuit1113generates second control codes CODE2<0:x> based on the resistant state PRE_RD of the target cell. In an embodiment, the second control codes CODE2<0:x> may be configured to determine the application time of the pre-emphasis current pulse.

An example of the principle of generating the first control codes CODE1<0:x> and the second control codes CODE2<0:x> in the control code generation unit1110will be described below.

In general, a voltage V, current I and resistance R have the relationship expressed in the following Equation 1.
V=IR[Equation 1]

It is known that, when considering a time constant τ by the parasitic components existing on the path from the write driver130to the target cell, that is, the parasitic resistance RPand the parasitic capacitance CP, a charge voltage for a parasitic capacitor may be expressed as in Equation 2.

Here, VOmeans the charge voltage, VINmeans an input voltage, and t is a charge time.

When assuming a situation in which a desired voltage is applied to the target cell by supplying current which results from adding pre-emphasis current IPREto the preset program current IPGM, Equation 3 may be derived from Equation 1 and Equation 2.

In Equation 3, RPATHmay be expressed as RPATH=RP±Rcellthat is the sum of the parasitic resistance RPexisting on the path to the target cell and resistance Rcellof the target cell. The program current IPGMis a preset value, and the time constant τ is determined as τ=(RP±Rcell)×CP=RPATHCPin consideration of the parasitic resistance RPand the parasitic capacitance CPexisting on the path from the write driver130to the target cell and the resistance Rcellof the target cell itself.

By rewriting Equation 3 with respect to the pre-emphasis current IPRE, Equation 4 is obtained.

As a result, it may be seen that the magnitude of the pre-emphasis current IPREis related with the application time of the pre-emphasis current IPRE.

Based on this fact, in the embodiment, two pre-emphasis schemes are proposed. One is a time variable program scheme and the other is a current variable program scheme.

First, the time variable program scheme will be described below.

In an embodiment, the pre-emphasis current IPRE=g*IPGMwhich results from increasing the program current IPGMby the same multiple g for all target cells is supplied. Further, the supply times t of the pre-emphasis current IPREare changed in consideration of the time constants τ=(RP+Rcell)×CP=RPATHCP. It is the matter of course that the parasitic resistance RPand the parasitic capacitance CPmay have different values according to the distances from the write driver130to the target cells. In addition, the time constants T are determined by the parasitic components existing on the paths and the pre-read operation.

Therefore, the pre-emphasis current IPREof the constant magnitude g*IPGMmay be supplied for the times t that are calculated from Equation 4 according to the positions and the resistant states of the target cells.

In an embodiment of the time variable program scheme, the pre-emphasis current IPREwhich results from increasing the program current IPGMby multiples g1 to gm differently determined according to the distances from the write deriver130to respective target cells may be supplied. Even in this case, the supply time t of the pre-emphasis current IPREmay be changed in consideration of the time constants determined according to the parasitic components existing on paths to the target cells and the resistant states of the target cells. In other words, the program current IPGMis increased by the same multiple g1 for all target cells which are at a first distance from the write driver130. Moreover, the program current IPGMis increased by the same multiple g2 different from the first multiple g1 for all target cells which are at a second distance from the write driver130, and so forth. In this way, the magnitudes of the pre-emphasis current IPREmay be set in such that the program current IPGMis increased by the same multiple for target cells of the same position and is increased by another the same multiple for target cells of another the same position. Furthermore, the application times t of the pre-emphasis current IPREmay be calculated based on the multiples g1 to gm set according to the positions of the target cells and Equation 4.

Describing the time variable program scheme in detail, the pre-read operation is performed in advance for all target cells to be programmed. Further, the time constants T are calculated, based on the parasitic components RPand CPto the target cells.

Then, the value or values that results or result from increasing the program current IPGMby the predetermined multiple g or the predetermined multiples g1 to gm are set as the level or levels of the pre-emphasis current IPRE, and based on the level or levels of the pre-emphasis current IPRE, the supply times t of the pre-emphasis current IPREare calculated. Thereafter, at the same time the program current IPGMis supplied, the pre-emphasis current IPREis supplied to the target cells according to the level or levels of the pre-emphasis current IPREand the calculated pre-emphasis current supply times t.

In an embodiment, a multiple H to increase the program current IPGMfor a specific cell, for example, a cell farthest away from the write driver130, is determined. Then, the supply time t of pre-emphasis current IPRE,faris calculated, based on the determined multiple H and the time constant τ=(RP+Rcell,far)×CP=RPATHCPobtained from the corresponding cell, that is, the farthest cell. Accordingly, the pre-emphasis current IPRE,farwhich results from increasing the program current IPGMH times may be supplied to the cell farthest away from the write driver130, for the calculated pre-emphasis current supply time t.

With respect to cells except the farthest cell, multiples to increase the program current IPGMare determined for the respective cells, based on the time constants of the respective cells, the pre-emphasis current supply time t obtained through the above process, and Equation 4. Then, the pre-emphasis current IPREincreased by the multiples determined for the respective cells is supplied for the pre-emphasis current supply time t.

In an embodiment of the current variable program scheme, an initial increase multiple H may be subdivided according to the resistance Rcellof a cell itself and target resistance Rtarget. For example, a cell of which resistance Rcellis discriminated, as a result of pre-read, to be higher than the target resistance Rtargetmay be determined to require a relatively large amount of pre-emphasis current, and a cell of which resistance Rcellis discriminated, as a result of pre-read, to be lower than the target resistance Rtargetmay be determined to require a relatively small amount of pre-emphasis current.

Therefore, in the case of the cell of which resistance Rcellis discriminated, as a result of pre-read, to be higher than the target resistance Rtarget, an initial increase multiple may be set as H1 as a value larger than H. Further, in the case of the cell of which resistance Rcellis discriminated, as a result of pre-read, to be lower than the target resistance Rtarget, an initial increase multiple may be set as H2 as a value smaller than H.

Describing the current variable program scheme in detail, the resistance Rcellof respective cells is first checked for all memory cells to be programmed, through a pre-read operation. In addition, time constants τ are calculated therefrom.

Thereafter, the pre-emphasis current supply time t is calculated. To this end, it is assumed that the pre-emphasis current IPRE,farwhich results from increasing the program current IPGMby a preset multiple (H, H1 or H2) is supplied to a memory cell which is disposed at a specified position. The specified position may be for example, farthest away from the write driver130. The pre-emphasis current supply time t is calculated for the memory cell farthest away from the write driver130by using Equation 4.

For the remaining cells, multiples to increase the program current IPGMare calculated in consideration of the pre-emphasis current supply time t and the time constants T of the respective cells or in additional consideration of the target resistance Rtargetfor the respective cells. Then, the pre-emphasis current IPREincreased by the calculated multiples is supplied for the pre-emphasis current supply time t calculated in advance.

As a result, the first control code generation circuit1111may generate the first control codes CODE1<0:x> such that a pre-emphasis current pulse may be supplied with a magnitude determined by any one of the time variable program scheme and the current variable program scheme. Moreover, the second control code generation circuit1113may generate the second control codes CODE2<0:x> such that pre-emphasis current may be supplied for a time determined by any one of the time variable program scheme and the current variable program scheme.

Referring toFIG. 3, a configuration diagram illustrating a representation of an example of the write driver130in accordance with an embodiment is shown.

The write driver130may be configured to include a reference current generation circuit1310and a pulse generation circuit1320.

The reference current generation circuit1310generates reference current of preset magnitudes. In an embodiment, the reference current generation circuit1310may include a first reference current generation circuit1311which generates first reference current IREF1and a second reference current generation circuit1313which generates second reference current IREF2.

The pulse generation circuit1320mirrors the reference current IREF1and IREF2generated by the reference current generation circuit1310in response to the control codes CODE1<0:x> and CODE2<0:x>. Accordingly, the pulse generation circuit1320generates the pre-emphasis current IPREwhich has the magnitude and the width determined according to the parasitic components existing on the path from the write driver130to a cell and the resistance of the cell itself. The pulse generation circuit1320generates the program current IPGMincluding the pre-emphasis current IPRE, and supplies the program current IPGMto the memory circuit block200. In an embodiment, the pulse generation circuit1320may include a pulse magnitude control unit1321which controls the magnitude of the pre-emphasis current IPREin response to the first reference current IREF1and the first control codes CODE1<0:x>. Further, the pulse generation circuit1320may include a pulse time control unit1323which controls the supply time of the pre-emphasis current IPREin response to the second reference current IREF2and the second control codes CODE2<0:x>.

The pre-emphasis current IPRE, which has the magnitude and the width determined by the pulse magnitude control unit1321and the pulse time control unit1323, is added with the mirroring results of the reference current IREF1and IREF2. The pre-emphasis current IPREis also generated as the program current IPGM, and is supplied to a target cell electrically coupled with the corresponding write driver130.

Referring toFIG. 4, a circuit diagram illustrating a representation of an example of a write driver130-1in accordance with an embodiment is shown.

A first reference current generation unit1311generates first reference current IREF1determined by a write voltage VPWR in response to a write pulse enable signal WPUL. Similarly, a second reference current generation unit1313generates second reference current IREF2determined by the write voltage VPWR in response to the write pulse enable signal WPUL.

A pulse magnitude control unit1321may include a first current mirror section13211and a magnitude determining section13213. The first current mirror section13211mirrors the first reference current IREF1and generates first pre-program current IPGM_re1. The magnitude determining section13213is electrically coupled between the first current mirror section13211and a pulse time control unit1323. Further, the magnitude determining section13213generates pre-emphasis current IPREwith a magnitude that is determined according to the first control codes CODE1<0:x>. Accordingly, the pre-emphasis current IPREwith the magnitude determined by the magnitude determining section13213is added to the first pre-program current IPGM_re1generated by the first current mirror section13211. In an embodiment, the magnitude determining section13213may be configured by a plurality of switching elements driven according to the respective control bits of the first control codes CODE1<0:x>. Further, the sizes of the respective switching elements may be designed to be the same with or different from one another.

The pulse time control unit1323may include a second current mirror section13231and a time determining section13233. The second current mirror section13231mirrors the second reference current IREF2. In addition, the second current mirror section13231generates second pre-program current IPGM_re2and supplies the second pre-program current IPGM_re2to the output terminal of the pre-emphasis current IPRE. The time determining section13233is electrically coupled between the output terminal of the pulse magnitude control unit1321, in detail, the output terminal of the magnitude determining section13213and the memory circuit block200. The time determining section13233determines the supply time of the pre-emphasis current IPREgenerated by the pulse magnitude control unit1321, in response to the second control codes CODE2<0:x>. Accordingly, the pre-emphasis current IPREwith the time determined by the time determining section13233is added to the second pre-program current IPGM_re2generated by the second current mirror section13231, and the output current of the time determining section13233is determined as the final program current IPGM. In an embodiment, the time determining section13233may be configured by a plurality of switching elements driven according to the respective control bits of the second control codes CODE2<0:x>. Further, the sizes of the respective switching elements may be designed to be the same with or different from one another. In an embodiment, the first control codes CODE1<0:x> and the second control codes CODE2<0:x> may allow the program current IPGMto be applied to a target cell of the memory circuit block200for the preset program current application time. The first control codes CODE1<0:x> and the second control codes CODE2<0:x> may also determine the pre-emphasis current IPREwith the preset magnitude to be supplied for a preset time in an initial period of a program current application period.

Referring toFIG. 5, a representation of an example of a timing diagram to assist in the explanation of the operations of the variable resistance memory apparatus in accordance with an embodiment is shown. Further,FIGS. 6 and 7are representations of examples of flow charts to assist in the explanation of the operations of the variable resistance memory apparatus in accordance with an embodiment.

Referring toFIGS. 5 and 6, after a write enable signal WE is enabled in synchronization with a clock signal CLK, a pre-read operation is performed for a target memory cell to be programmed, in response to a pre-read signal PRE_RD (S101).

Control codes to determine the magnitude and the supply time of pre-emphasis current IPREare generated according to the result of the pre-read operation (S103).FIG. 5shows a time variable program scheme, that is, an example of supplying program current IPGMincreased by the same multiple g, to respective target cells, as the pre-emphasis current IPRE. The application time of the pre-emphasis current IPREmay be set long for a cell discriminated as a high resistant state as a result of the pre-read, among target cells intended to have the same resistance distribution. In addition, the application time of the pre-emphasis current IPREmay be set short for a cell which is discriminated as a low resistant state as a result of the pre-read, among the target cells intended to have the same resistance distribution.

As the pre-emphasis current IPREdetermined in this way is supplied to a target cell by being added to the program current IPGMduring an initial period T2or T3of a period T1during which the program current IPGMis supplied, a program operation may be performed (S105).

Referring toFIG. 7, an operation in the case where the write operation according to an embodiment is applied to a program and verify scheme is shown.

Before a program operation is performed or after a program operation of a previous stage is performed (S301), the resistant states of target cells are pre-read (S201). According to a result of the pre-read, control codes to determine the magnitude and the supply time of pre-emphasis current IPREare generated (S203). A detailed method to generate the control codes are the same as described above.

Thereafter, as the pre-emphasis current IPREis supplied to a target cell by being added to program current IPGMduring an initial period of a period during which the program current IPGMis supplied according to the generated control codes, a program operation may be performed (S205).

After the program is performed, a verification read operation is performed for the target cell to discriminate whether the target cell has a target resistant state or not (S207). According to a discrimination result, the program process is ended or returns to the step S203to repeat subsequent steps.

Referring toFIG. 8, a representation of an example of a diagram to assist in the explanation of the shapes of program current pulses which are scaled by the time constants of target cells, in accordance with an embodiment is shown. In this regard, it was described above that a time constant is determined from parasitic components from a write driver to a target cell and a result of pre-reading the resistant state of the target cell.

In the case where a pre-emphasis technology is not applied, the shapes of program current pulses supplied to a cell with a relatively small time constant and a cell with a relatively large time constant are different from each other (a1and b1).

In the case where the pre-emphasis technology as in an embodiment is applied, pre-emphasis current IPREmay be additionally supplied during an initial period corresponding to a first time T4in a period T1during which program current IPGMis supplied to the cell with the relatively small time constant (a2).

In addition, the pre-emphasis current IPREmay be additionally supplied during an initial period corresponding to a second time T5longer than the first time T4in the period T1during which the program current IPGMis supplied to the cell with the relatively large time constant (b2).

As a result, program pulses with the same shape may be supplied to the cell with the relatively small time constant and the cell with the relatively large time constant (a3and b3).

Referring toFIG. 8, an example that the pre-emphasis current IPREis set to a fixed multiple of the program current IPGMand the supply time of the pre-emphasis current IPREis changed according to parasitic components and a pre-read result is shown.

In the case of supplying the pre-emphasis current IPREin this way, a result as shown inFIG. 9may be confirmed. In the case where the pre-emphasis technology is not applied, first program current IPGM1with a slope lower than input program current IPGMis supplied to a target cell according to the time constant of the target cell, whereby it is difficult to obtain a desired program result.

In the case where the pre-emphasis technology is applied, first pre-emphasis current IPRE1may be supplied to a cell with a relatively small time constant, for a relatively short period, in addition to the program current IPGM. Accordingly, a second program current IPGM2in which an initial period is compensated for by the first pre-emphasis current IPRE1may be supplied to the cell with the relatively small time constant. In addition, a second pre-emphasis current IPRE2may be supplied to a cell with a relatively large time constant, for a relatively long period, in addition to the program current IPGM. As a result, a third program current IPGM3in which an initial period is compensated for by the second pre-emphasis current IPRE2may be supplied to the cell with the relatively long time constant.

Referring toFIGS. 10 to 14, representations of examples of diagrams to assist in the explanations of systems in accordance with embodiments are shown.

FIG. 10is a configuration diagram illustrating a representation of an example of a processor in accordance with an embodiment.

Referring toFIG. 10, a processor20may include a control unit210, a calculation unit220, a storage unit230, and a cache memory unit240.

The control unit210receives signals, such as commands and data, from an external device. The control unit210also decodes commands, performs input or output of data, and processes data, thereby controlling the general operations of the processor20.

The calculation unit220performs various operations according to results of decoding commands by the control unit210. The calculation unit220may include at least one arithmetic and logic unit (ALU).

The storage unit230may serve as a register and is a part which stores data in the processor20. The storage unit230may include a data register, an address register, a floating point register, and various other registers. The storage unit230may store data to be calculated by the calculation unit220, calculation result data, and addresses at which those data are stored.

The storage unit230may include, for example, a memory circuit block configured by variable resistance memory elements. The storage unit230may also include a controller including a control code generation unit, a read circuit block, and a write circuit block. In an embodiment, the storage unit230may be the variable resistance memory apparatus shown inFIG. 1. Accordingly, when performing write for a memory region according to the write command and the write data provided from the control unit210, the resistant state of a target memory cell may be pre-read. In addition, it is possible to compensate for the initial period of program current by a pre-emphasis current pulse with a magnitude and a width determined based on a pre-read result and parasitic components.

The cache memory unit240serves as a temporary storage space.

The processor20illustrated inFIG. 10may be a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP), an application processor (AP) or the like of an electronic apparatus.

FIGS. 11 and 12are configuration diagrams illustrating representations of examples of data processing systems in accordance with embodiments.

The data processing system30illustrated inFIG. 11may include a main controller310, an interface320, a main memory device330, and an auxiliary memory device340.

The data processing system30may perform input, processing, output, communication, and storage to perform a series of operations to process data. The data processing system30may be an electronic apparatus such as a computer server, a personal digital assistant, a notebook computer, a web tablet computer, a wireless terminal, a mobile communication terminal, a digital contents player, a camera, a global positioning system, a video camera, a recorder, a telematics device, an AV system, a smart TV, and the like.

In an embodiment, the data processing system30may be a data storage device. Further, the data processing system30may be a disk type such as a hard disk, an optical drive, a solid state disk, a DVD, or the like, or a card type such as a universal serial bus (USB) memory, a secure digital (SD) card, a memory stick, a smart media card, an internal/external multimedia card, a compact flash card, or the like.

The main controller310controls data exchange through the main memory device330and the interface320. To this end, the main controller310controls general operations of decoding the commands inputted through the interface320from an external device, and calculating and comparing the data stored in the system.

The interface320provides an environment in which commands and data may be exchanged between the external device and the data processing system30. The interface320may be a man-machine interface device, a card interface device or a disk interface device, depending on the applied environment of the data processing system. The man-machine interface device may include an input device such as a keyboard, a keypad, a mouse and a voice recognition device and an output device such as a display and a speaker. The disk interface device may include IDE (Integrated Drive Electronics), SCSI (Small Computer System Interface), SATA (Serial Advanced Technology Attachment), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), or the like.

The main memory device330is configured to store applications, control signals, and data needed for the data processing system30to operate. The main memory device330serves as a storage to and from which program or data may be transferred from the auxiliary memory device340and may be executed. The main memory device330may be realized using a memory device having nonvolatile properties. For example, the variable resistance memory apparatus shown inFIG. 1may be used as the main memory device330.

The auxiliary memory device340is a space to store program codes or data, and may include a high-capacity memory device. For example, the variable resistance memory apparatus illustrated inFIG. 1may be used as the auxiliary memory device340.

More specifically, the main memory device330and/or the auxiliary memory device340may include, for example, a memory circuit block configured by variable resistance memory elements, a controller including a control code generation unit, a read circuit block, and a write circuit block. Accordingly, when performing write for a memory region according to the write command and the write data provided from the main controller310, the resistant state of a target memory cell may be pre-read. In addition, it is possible to compensate for the initial period of program current by a pre-emphasis current pulse with a magnitude and a width determined based on a pre-read result and parasitic components.

The data processing system40illustrated inFIG. 12may include a memory controller410and a variable resistance memory apparatus420.

The memory controller410may be configured to access the variable resistance memory apparatus420in response to a request from a host. To this end, the memory controller410may include a processor411, a working memory413, a host interface415, and a memory interface417.

The processor411may control the general operations of the memory controller410. In addition, the working memory413may store applications, data, control signals, and so forth, which are needed for the memory controller410to operate.

The host interface415may perform protocol conversion for exchange of data/control signals between the host and the memory controller410. In addition, the memory interface417may perform protocol conversion for exchange of data/control signals between the memory controller410and the variable resistance memory apparatus420.

The variable resistance memory apparatus420may use, for example, the variable resistance memory apparatus shown inFIG. 1. The variable resistance memory apparatus420may also include a memory circuit block configured by variable resistance memory elements, a controller including a control code generation unit, a read circuit block, and a write circuit block. Accordingly, when performing write for a memory region according to the write command and the write data provided from the memory controller410, the resistant state of a target memory cell may be pre-read. Further, it is possible to compensate for the initial period of program current by a pre-emphasis current pulse with a magnitude and a width determined based on a pre-read result and parasitic components.

The data processing system40illustrated inFIG. 12may be utilized as a disk device, an internal/external memory card of a portable electronic appliance, an image processor, or an application chip set.

Furthermore, the working memory413provided in the memory controller410may also be realized using the memory apparatus illustrated inFIG. 1.

FIGS. 13 and 14are configuration diagrams illustrating electronic systems in accordance with embodiments.

The electronic system50illustrated inFIG. 13may include a processor501, a memory controller503, a variable resistance memory apparatus505, an input/output device507, and a function module500.

The memory controller503may control a data processing operation of the variable resistance memory apparatus505, for example, a write or read operation, under the control of the processor501.

The data written in the variable resistance memory apparatus505may be outputted through the input/output device507under the control of the processor501and the memory controller503. The input/output device507may include a display device, a speaker device, and so forth.

The input/output device507may also include an input device through which a control signal to control the operation of the processor501or data to be processed by the processor501may be inputted.

In an embodiment, the memory controller503may be realized as a part of the processor501or a chip set separate from the processor501.

The variable resistance memory apparatus505may include, for example, a memory circuit block configured by variable resistance memory elements, a controller including a control code generation unit, a read circuit block, and a write circuit block. In an embodiment, the variable resistance memory apparatus505may be the variable resistance memory apparatus shown inFIG. 1. Thus, when performing write for a memory region according to the write command and the write data provided from the memory controller503, the resistant state of a target memory cell may be pre-read. In addition, it is possible to compensate for the initial period of program current by a pre-emphasis current pulse with a magnitude and a width determined based on a pre-read result and parasitic components.

The function module500may be a module capable of performing a selected function according to an application example of the electronic system50illustrated inFIG. 13.FIG. 13illustrates a communication module509and an image sensor511as an example of the function module500.

The communication module509may provide a communication environment in which the electronic system50may access a wired or wireless communication network and exchange data and control signals.

The image sensor511converts an optical image into digital image signals and transmits the digital image signals to the processor501and the memory controller503.

When the electronic system50ofFIG. 13is provided with the communication module509, the electronic system50may operate as a portable communication appliance such as a wireless communication terminal. When the electronic system50is provided with the image sensor511, the electronic system50may be an electronic system (for example, a PC, a notebook computer, a mobile communication terminal or the like) which is attached with a digital camera or a digital camcorder.

The electronic system60illustrated inFIG. 14may include a card interface601, a memory controller603, and a variable resistance memory apparatus605.

The electronic system60illustrated inFIG. 14is an embodiment of a memory card or a smart card, and may be any one of a PC card, a multimedia card, an embedded multimedia card, a secure digital card, and a USB drive.

The card interface601interfaces exchange of data between a host and the memory controller603, according to the protocol of the host. In an embodiment, the card interface601may mean a hardware capable of supporting the protocol used by the host, a software mounted on the hardware which supports the protocol used by the host, or a signal transmission scheme.

The memory controller603controls exchange of data between the variable resistance memory apparatus605and the card interface601.

The variable resistance memory apparatus605may use the variable resistance memory apparatus shown inFIG. 1. More specifically, the variable resistance memory apparatus605may include a memory circuit block configured by variable resistance memory elements, a controller including a control code generation unit, a read circuit block, and a write circuit block. Accordingly, when performing write for a memory region according to the write command and the write data provided from the memory controller603, the resistant state of a target memory cell may be pre-read. Further, it is possible to compensate for the initial period of program current by a pre-emphasis current pulse with a magnitude and a width determined based on a pre-read result and parasitic components.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the write driver, the variable resistance memory apparatus including the same, and the operation method described should not be limited based on the described embodiments.