Signal switch with reduced on resistance and undershoot protection

An electronic switch applies ground potential to the backgate of a MOS pass transistor when the transistor is in the off state and the switch is open, during normal conditions. When the transistor is switched to the on state and the switch is closed, the gate voltage is applied to the backgate of the pass transistor in order to reduce the threshold voltage and the on resistance. During an undershoot condition, the gate of the pass transistor is connected to the negative voltage applied to an input port and this voltage is also connected to the backgate of the pass transistor to prevent the pass transistor from being biased on or the parasitic NPN transistor from being biased on and transmitting the input glitch to the output.

TECHNICAL FIELD OF THE INVENTION

This invention relates to an electronic switch and in particular a NMOS switch.

BACKGROUND OF THE INVENTION

Electronic switches, such as cross bar switches, often consist of a single NMOS transistor connected between an input port and an output port. When the switch is open, there is a high impedance path between the input and the output to provide circuit isolation. When the switch is closed, it provides a low resistance path from the input to the output. These switches allow for signal propagation in either direction. Therefore, either port could be an input or an output port.

As these switches are utilized to propagate signals at higher and higher frequencies, the switches must have a lower RC network value to pass the higher frequency signals and a small resistance delta across the input voltage in order to minimize signal distortion.

One known solution to the high frequency data switching problem is to use a charge pump to increase the voltage on the gate of the pass transistor. This requires an on-chip oscillator and produces a higher current drain than is desired. Another known solution to this problem is to bias the back gate of the pass transistor to either the source or the drain input voltage in order to make VBSequal to zero volts. This biasing technique causes the NMOS threshold voltage to lower and the drive strength to increase, which reduces the on resistance. However, this circuit arrangement can compromise the isolation of the output from the input if the voltage applied to the input terminal goes far enough below ground to turn on the parasitic NPN transistor or cause the pass transistor to conduct because the VGSvoltage increases. If the output is high, this can cause the output to be pulled down which can cause a glitch in the output. If the glitch is of sufficient magnitude, it can cause the output to change state.

Accordingly, there is a need for a switch circuit which has a reduced on resistance and provides undershoot protection.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide a switch circuit which has a reduced ON resistance and provides undershoot protection.

This and other objects and features are provided in accordance with one aspect of the invention by a signal switch comprising a MOS pass transistor coupled between a first port and a second port. A drive circuit coupled to a gate and a back gate of the MOS pass transistor. An undershoot detection circuit coupled to the path between ports for detecting an undershoot condition. An undershoot protection circuit is coupled to an output of the undershoot detection circuit and to the gate and back gate of the MOS pass transistor for preventing the MOS pass transistor from being turned on by the undershoot and creating a bus disturbance.

Another aspect of the invention includes a signal switch having a MOS pass transistor coupled between a signal input and a signal output. A driver circuit comprises a first biasing circuit coupled to a back gate of the MOS pass transistor for reducing the VTof the MOS pass transistor when the MOS pass transistor is turned ON to allow a signal at the signal input to propagate to the signal output. A second biasing circuit is coupled to a gate and the back gate of the MOS pass transistor to prevent an undershoot from propagating to the signal output.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

FIG. 1shows an electronic switch according to the present invention generally as100. Terminals126and136function as input/output terminals for the switch. As is well known to those skilled in the art, either terminal126,136can serve as an input terminal, and the other terminal serve as an output terminal. That is, the signal propagation can go from126to136or from136to126. A capacitor128is connected between terminal126and ground and a capacitor134is connected between terminal136and ground. Terminal102receives this signal OE which is the output enable signal used to control the NMOS pass transistor switch into either the open or closed mode. An NMOS pass transistor switch120is coupled between the terminals126and136by lines130and132, respectively. The gate of pass transistor120is coupled to the terminal102by inverter104, output line106, inverter108and output line110. A circuit150is used to determine whether there is a negative glitch on either port126or port136and to apply an appropriate negative power supply voltage to inverter108via line152. Circuits capable of performing the function of block150are known in the art and need not be described in detail here.

Line110is also coupled to the drain of NMOS transistor112, the gate of which is connected to ground. The back gate of transistor112is connected to its source and the source is connected to line140which is connected via line124to the back gate of NMOS pass transistor120. Line140is also coupled to the cathode of a Schottky diode142which has its anode connected to the drain of NMOS transistor144. The source of NMOS transistor144is connected to ground and the gate thereof is connected to line106via line164. Three PMOS transistors114,116,118have their source-drain paths connected in series between lines110and140. Each of these transistors has long channel gate lengths in order to provide a high impedance path between lines110and140. The gates of all three transistors are connected together and connected to node S5at line154.

The gates of transistors114,116,118are coupled to a bias circuit comprising NMOS transistors156and158and PMOS transistors160and162connected in series. Each of the transistors has its gate connected to its source, so that the VGSvoltage is equal to zero volts and all the transistors are biased in their off state. However, there is enough sub-threshold leakage current through the transistor stack to be the equivalent of a resistor divider circuit. Since the NMOS and PMOS transistors have similar sub-threshold leakage values, the bias voltage on node S5is approximately the input voltage VCCdivided by four. Thus, the biasing circuit comprising transistors156,158,160and162acts like a high impedance resistor divider.

In the embodiment of the present invention illustrated inFIG. 1, the circuit is built using a P substrate process. In order to change the back gate on the NMOS pass transistor120, it is necessary to provide for isolation of this transistor by the use of a guard ring. The guard ring is coupled via line122to VCC. This enables the back gate voltage to be changed instead of having the back gate tied to ground. The use of an isolated pass transistor is not required for an N substrate process.

Under normal operating conditions, the back gate of pass transistor120is biased to ground with the switch in the OFF state. When the output enable control signal OE goes low, the N-channel transistor (not shown) of inverter108is on and pulls the gate voltage of the pass transistor120to ground. In addition, the gate of transistor144is tied to the output of inverter104, and therefore to a voltage equal to VCC, which pulls node S31low via line124and through the series combination of Schottky diode142and NMOS transistor144. This enables the switch to operate in a low leakage mode to avoid any bus disturbance.

When the output enable signal goes high, the output of inverter104will be low and the output of inverter108will be high. Thus, the gate of pass transistor120will be high and the transistor will be on. The gate of transistor144is connected to the output of inverter104and is therefore connected to ground which eliminates the pull down path from node S31. The P channel transistor (not shown) of inverter108is turned on and connected to the pass transistor120back gate through the series stack of transistors114,116and118via line124. The three transistors114,116and118provide a high impedance path between the pass transistor120and its back gate. The high impedance is provided by the long channel gate lengths and by biasing the gates of the three transistors at a voltage of approximately one quarter VCCinstead of ground. This gate reference voltage is provided by the sub-leakage currents of transistors156,158,160and162and requires only a few microamperes of current. Node S31will be pulled to the power supply rail through the P channel transistor of inverter108. This will cause the VGSof pass transistor120to be a positive voltage for any I/O port voltage, on terminals126or136, that is below VCC. The highest the voltage VGScan be is the Vforwardof the parasitic PN diode. It is formed between the backgate and the source of transistor120. If the path through transistors114,116and118was not a high impedance path, there would be a low impedance path from the power supply via the P channel transistor in inverter108and through the parasitic diode of pass transistor120to the I/O port126or136. This would cause the circuit to consume considerably more current.

Referring now toFIG. 2, there are four graphed lines showing the effect of the present invention. Graphed lines202and206represent the prior art technique where the backgate is tied to ground for two different NMOS pass transistors120. Graphed lines204and208represent the same two transistors in which the present invention is implemented so that the backgate of NMOS pass transistor120is tied to the bias voltage. As can be seen by comparing the two sets of graphed lines, the overall resistance of the switch RONis less for graphed lines204and208and remains in the linear region for a greater range of input voltage. This reduces the attenuation of the signal through the switch and reduces distortion of the signal as the input voltage VINincreases.

Biasing the pass transistor120backgate to a positive voltage with respect to the source and drain, that is, VGSis greater than zero volts, causes the NMOS transistor threshold voltage to be lower which increases the drive strength when the transistor is on. This, in turn, results in a lower and flatter on resistance input voltage graphed line for the switch. The on resistance improvement becomes even more dramatic as the input voltage increases, as shown by the longer flat area inFIG. 2.

Returning now toFIG. 1, another aspect of the invention is to provide undershoot protection of the switch when it is open. Without the undershoot protection circuit of the present invention, when the gate of pass transistor120is tied to ground, and an undershoot event occurs in which the input signal goes below ground, the VGSof the pass transistor120would become positive. For a large negative glitch, the pass transistor120would turn on and attempt to pull down the bus connected to the output of the switch. If the output were high, a glitch would appear on the output bus and if the voltage of the glitch was high enough, it could cause the bus to change state.

In order to avoid such bus disruptions, both the gate and the backgate of pass transistor120are tied to the negative voltage so both the NMOS and parasitic NPN transistors are kept off and the switch remains open. The circuits150is used to detect a negative glitch applied to either port126or136. The output of the circuit150to the lower supply voltage of inverter108and is at ground during normal operation. During an undershoot event, this voltage is tied to a negative voltage. This voltage then appears at the output of inverter108on line110which is tied to the gate of NMOS pass transistor120when the output signal OE is low. This allows the negative voltage applied to either port126or136to be translated to line110which will keep the VGSof the pass transistor120equal to zero volts. In addition, transistor112is utilized to connect the backgate of the pass transistor120to the negative voltage glitch. Transistor112is off during normal conditions because its gate is tied to ground. This isolates the gate and backgate of pass transistor120. When an undershoot event occurs, the negative voltage on lines152and110causes the VGSof transistor112to be positive and allows node S31to also be connected to a negative voltage level. The backgate of transistor120is also the base of the parasitic NPN transistor formed from the source to drain so that connecting node S31to the negative voltage glitch keeps this NPN transistor off.

Schottky diode142is required to prevent, during an undershoot event, the backgate of pass transistor120remaining at ground potential, which could result in a bus disturbance. The Schottky diode142, during an undershoot event, becomes reversed bias and blocks the current path from node S31to ground.

FIG. 3shows the plot of a simulation of the undershoot protection provided by the circuit shown inFIG. 1. The Graphed line A is the input voltage to the switch. The plot of the input voltage shows an undershoot condition having an input voltage of −2 volts for about 20 nanoseconds. The Graphed line B is the output voltage of the switch. As can be seen from this Graphed line, there is only a very small change in the output voltage during the undershoot. This is because the node S31voltage follows the undershoot voltage to keep the parasitic NPN transistor turned off during the glitch in the input voltage, so that the switch remains open.

While the invention has been shown and described with reference to preferred embodiments thereof, it is well understood by those skilled in the art that various changes and modifications can be made in the invention without departing from the spirit and scope of the invention as defined by the appended claims.