Multiple layer wide bandgap collector structure for bipolar transistors

Generally, and in one form of the invention, a multiple layer wide bandgap collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14. Other devices, systems and methods are also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS 
The following coassigned patent application is hereby incorporated herein 
by reference: Ser. No. 07/722984, filing date Jun. 28, 1991, now U.S. Pat. 
No. 5,171,697. 
FIELD OF THE INVENTION 
This invention generally relates to a multiple layer wide bandgap collector 
structure for bipolar transistors. 
BACKGROUND OF THE INVENTION 
Without limiting the scope of the invention, its background is described in 
connection with heterojunction bipolar transistors (HBTs), as an example. 
Heretofore, in this field, two of the most important figures of merit in 
power HBT design have been the emitter-collector breakdown voltage, 
BV.sub.ceo, and the maximum operating current density prior to base 
pushout, J.sub.max. For a transistor under a given bias condition, its 
output power is directly proportional to the product of the operating 
emitter-collector voltage and the collector current density. Therefore, 
one would like to design a power transistor to operate at large 
emitter-collector voltage and collector current density. However, when the 
emitter-collector voltage is increased to an extreme, the base-collector 
junction breakdown eventually occurs and the transistor ceases to operate. 
The voltage at which the breakdown occurs is essentially the 
emitter-collector breakdown voltage, BV.sub.ceo. 
On the other hand, power can also be increased by increasing the operating 
collector current density level. As with the case of increasing 
emitter-collector voltage, there is a limit to the operating collector 
current density level, J.sub.max, beyond which the transistor ceases to 
function properly. The physical effect imposing this limit of current 
density level is called the base pushout effect (also known as the Kirk 
effect). When the operating collector current density is larger then 
J.sub.max, the number of free carriers entering the base-collector 
space-charge region becomes so large that the carriers greatly modify the 
background charge in that region. Consequently, the electric field at the 
base side of the base-collector junction decreases to zero, and the base 
majority carriers spill over into the junction. At this point, the 
effective base width suddenly increases and current gain dramatically 
decreases, causing the transistor to cease to function properly. 
In practice, both of these parameters are heavily influenced by the design 
of the collector, which can be varied in both thickness and doping 
concentration. The collector thickness of an HBT designed for high power 
applications is generally required to be as thick as possible, so that a 
large reverse base-collector junction voltage can be sustained. However, 
when carried to an extreme, the collector space charge transit time 
becomes so large that the transistor cannot effectively function at 
frequencies of interest. As the thickness of the collector is increased, 
the time required for carriers to cross the collector (known as the 
collector space charge transit time, or collector transit time) also 
increases. When the collector transit time becomes a substantial fraction 
of one period or cycle at the frequency of operation, the current gain and 
efficiency of the transistor are drastically reduced at that frequency. 
With a thicker collector, a larger reverse base-collector junction voltage 
can be sustained and, therefore, BV.sub.ceo becomes larger. Typically, for 
HBTs designed for X-band operation (6.2 GHz-10.9 GHz), the collector 
thickness is constrained to 1 .mu.m or less. Consequently, the breakdown 
voltage is limited to a certain value determined by the material 
properties of the collector, such as the maximum breakdown electric field. 
In the case of a GaAs collector, the maximum attainable emitter collector 
breakdown voltage, BV.sub.ceo, is roughly 24 V. The only remaining design 
option when using GaAs is thus the collector doping. With only this one 
design parameter to work with, the collector doping profile must be a 
tradeoff between the maximization of BV.sub.ceo or J.sub.max. At one 
extreme, it is desired to make this collector doping level, N.sub.coll, as 
heavy as possible so that the base pushout effects start at a much higher 
current density, given as: 
EQU J.sub.max =q.times.N.sub.coll .times.V.sub.sat 
where: 
q is the electronic charge 
V.sub.sat is the saturation velocity of the carriers 
Consequently, J.sub.max is large and the transistor can be operated at 
higher current levels. 
At the other extreme, it is desired to make the collector doping profile as 
light as possible, so that a higher voltage can be sustained across the 
base-collector junction before the junction breakdown occurs. In this 
manner, BV.sub.ceo can be increased, and the transistor can be operated at 
higher voltages. 
Therefore, a problem faced with the conventional single-layer GaAs 
collector has been that there is virtually no design freedom for 
substantially independent and simultaneous increase of both BV.sub.ceo and 
J.sub.max by varying just the collector doping level. Another problem 
faced has been that the maximum attainable BV.sub.ceo has been limited to 
roughly 24 V. Accordingly, improvements which overcome any or all of these 
problems are presently desirable. 
SUMMARY OF THE INVENTION 
It is herein recognized that a need exists for a bipolar transistor with 
independent control of J.sub.max and BV.sub.ceo. The present invention is 
directed towards meeting those needs. 
Generally, and in one form of the invention, a multiple layer wide bandgap 
collector structure is provided which comprises a relatively thick, low 
doped or non-intentionally doped layer and a relatively thin, highly doped 
layer. 
In another form of the invention, there is provided a high power bipolar 
transistor comprising a substrate, subcollector layer on the substrate, a 
graded layer on the subcollector layer, a relatively thick and low doped 
or non-intentionally doped first collector layer on the graded layer, a 
relatively thin and highly doped second collector layer on the first 
collector layer, a base layer on the second collector layer, and an 
emitter layer on the base layer. 
In yet another form of the invention, there is provided a method for making 
a multiple layer wide bandgap collector structure comprising the steps of 
forming a relatively thick and low doped or non-intentionally doped layer 
and epitaxially depositing a relatively thin and highly doped layer on the 
low doped or non-intentionally doped layer. 
In still another form of the invention, a method for making a high power 
bipolar transistor is provided, comprising the steps of forming a 
substrate, epitaxially depositing a subcollector layer on the substrate, 
epitaxially depositing a graded layer on the subcollector layer, 
epitaxially depositing a first collector layer on the graded layer, the 
first collector layer being relatively thick and low doped or 
non-intentionally doped, epitaxially depositing a second collector layer 
on the first collector layer, the second collector layer being relatively 
thin and highly doped, epitaxially depositing a base layer on the second 
collector layer, and epitaxially depositing an emitter layer on the base 
layer. 
An advantage of the invention is that it allows the relatively independent 
control of J.sub.max and BV.sub.ceo in a bipolar transistor.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
With reference to FIG. 1, a first preferred embodiment of the present 
invention is described hereinbelow which solves the dilemmas of 
constrained BV.sub.ceo and of choosing between mutually exclusive 
collector doping profiles in attempting to maximize the values of 
BV.sub.ceo and J.sub.max by utilizing a novel two-layer collector 
structure incorporating AlGaAs. 
The first preferred embodiment of the present invention is comprised of a 
transistor indicated generally at 10, having a collector composed of two 
distinct layers 12 and 14. The first collector layer 12 is disposed next 
to a base 16, the second collector layer 14 is disposed between the first 
collector layer 12 and a graded layer 17. The first collector layer 12 is 
composed of Al.sub.x Ga.sub.1-x As, with the aluminum composition graded 
from 0% at the junction with the base 16 to 100%, for example, at the 
junction with the second collector layer 14. The first collector layer 12 
has a width (measured in the direction of current flow) W.sub.C1 of 400 
Angstroms, for example, and is doped at a relatively high concentration 
level N.sub.C1, such as 1.times.10.sup.18 atoms/cm.sup.3. The second 
collector layer 14 is also composed of Al.sub.x Ga.sub.1-x As, but has a 
uniform aluminum composition of 100%, for example (AlAs is used as an 
example since the bandgap of Al.sub.x Ga.sub.1-x As is highest at this 
particular composition. However, this design is completely general, and 
the aluminum composition is not restricted to 100%). The second collector 
layer 14 has a width (measured in the direction of current flow) W.sub.C2 
of 1 .mu.m, for example, and does not have any intentional doping 
N.sub.C2. The graded layer 17 is made of Al.sub.x Ga.sub.1-x As with a 
100% aluminum composition (AlAs), for example, at the interface with 
collector layer 14, decreasing to 0% (GaAs) at the interface with the 
subcollector 18. The graded layer 17 is preferably 300 .ANG. thick and 
doped with Si to a concentration of approximately 5.times.10.sup.18 
cm.sup.-3. The exact doping concentration of layer 17 is not critical 
since it is not part of the active collector layer (layers 12 and 14). A 
relatively high doping concentration will make the extra (though small) 
resistance associated with this layer 17 negligible. 
The first collector layer 12, which is adjacent to the base 16, is doped 
heavily, but its width W.sub.C1 must be thin enough so that this layer is 
depleted, preferably even at zero external base-collector bias. This is 
because during the operation of a high frequency power bipolar transistor, 
the base-emitter bias is continuously varied from zero to a value limited 
by BV.sub.ceo. If during any part of the cycle the collector is not fully 
depleted, part of the power will be dissipated in the undepleted portion 
of the collector, which constitutes essentially a parasitic collector 
resistance. Consequently, if the collector can be fully depleted even at 
zero bias, then there will be no parasitic power dissipation associated 
with the collector at any given bias condition. The purpose of this thin, 
heavily doped layer 12 is to create a large magnitude of electric field in 
the junction area close to the base layer 16. This large field prevents 
the base pushout effects from occurring at lower current levels and, 
consequently, J.sub.max increases. 
When a carrier travels in a base-collector junction, it travels, on 
average, a "mean free path", before interacting with an atom in the 
lattice and losing its energy. However, if the emitter-collector bias 
increases toward BV.sub.ceo, the electric field in the junction becomes 
large. Consequently, the carrier can gain sufficient energy from the field 
while traveling within its mean free path, such that it breaks the bond 
between the atom core and one of the bound electrons upon impacting the 
lattice. The initial carrier, as well as the hole and electron created by 
the collision are then free to leave the region of the collision. This 
process is called impact ionization. When the emitter-collector bias is 
larger than BV.sub.ceo, the events of impact ionization are so numerous 
that the collector current due to the ionized carrier becomes infinitely 
large and the transistor ceases to function properly. At this point, the 
transistor is said to reach the emitter-collector breakdown condition. It 
should be noted that carriers in GaAs must acquire a threshold energy of 
1.7 eV before impact ionization can occur. Therefore, it is important that 
the first collector layer 12 be made thin (i.e. small W.sub.C1) so that 
even when carriers traverse this high field region, the amount of energy 
the carriers pick up from the electric field is below 1.7 eV and therefore 
they have not acquired enough energy to cause avalanche breakdown. With 
this design principle, most of the impact ionizations actually occur in 
the second collector layer 14, rather than in the high field region of the 
first collector layer 12. Consequently, it is desirable that the second 
collector layer 14 be made thick (i.e. large W.sub.C2) and lightly doped 
(i.e. small N.sub.C2) so that it will sustain a large voltage drop before 
the junction breakdown occurs. Therefore, BV.sub.ceo increases. 
The fact that avalanche breakdown initiates from this low field second 
collector layer 14 has been verified with a computer simulation which 
utilizes the most recent electron and hole impact ionization coefficients. 
It has been calculated that, despite the fact that the first collector 
layer 12 is a high field region, it only contributes approximately 5% of 
the impact ionizations at the onset of avalanche breakdown. Consequently, 
to increase the breakdown voltage BV.sub.ceo even further, the second 
collector layer 14 is made of Al.sub.x Ga.sub.1-x As, which can sustain a 
higher voltage drop before avalanche breakdown occurs due to its larger 
bandgap compared to GaAs. The breakdown voltage BV.sub.ceo is 
approximately proportional to the 3/2 power of the bandgap. For a 1 .mu.m 
GaAs collector structure, the BV.sub.ceo is calculated to be 24 V. On the 
other hand, with the use of Al.sub.1.00 Ga.sub.0.00 As in the second 
collector layer 14, the BV.sub.ceo is expected to reach 44.4 V, which is 
nearly a 185% increase. 
It is not necessary to have the first collector layer 12 be composed of 
Al.sub.x Ga.sub.1-x As since the major portion of the impact ionization 
contributing to the eventual avalanche breakdown originates from the 
second collector layer 14. In fact, the first collector layer 12 is graded 
so that an abrupt band discontinuity does not exist at the base-collector 
junction. The undesirable effects of quantum reflection and dramatic 
carrier collection reduction associated with an abrupt junction thus do 
not appear. In addition, this first layer is sufficiently thin so that the 
entire collector is fully depleted, even at zero external base-collector 
bias. Its thickness W.sub.C1 is thus typically between 200 .ANG. and 500 
.ANG., which, fortuitously, is the grading distance required for typical 
epitaxial growth techniques. 
It can therefore be seen that with the first preferred embodiment of the 
invention, J.sub.max can be increased by heavily doping a thin collector 
layer 12 adjacent to the base 16, while BV.sub.ceo can also be increased 
by simply inserting a thick, unintentionally doped Al.sub.x Ga.sub.1-x As 
collector layer 14 between the first collector layer 12 and the 
subcollector 18. Both J.sub.max and BV.sub.ceo can thus essentially be 
simultaneously and independently increased, without any trade off. 
FIG. 2 illustrates the results of a computer simulation program used to 
calculate J.sub.max and BV.sub.ceo for the various device structures 
listed in Table I (the numbered points on the graph of FIG. 2 correspond 
to the device numbers of Table I). 
TABLE I 
______________________________________ 
Device N.sub.C1 W.sub.C1 N.sub.C2 
W.sub.C2 
______________________________________ 
1 5 .times. 10.sup.16 
1 .mu.m 
2 2 .times. 10.sup.16 
1 .mu.m 
3 1 .times. 10.sup.14 
1 .mu.m 
4 1 .times. 10.sup.17 
1000 .ANG. 1 .times. 10.sup.14 
1 .mu.m 
5 5 .times. 10.sup.17 
500 .ANG. 1 .times. 10.sup.14 
1 .mu.m 
6 1 .times. 18.sup.18 
400 .ANG. 1 .times. 10.sup.14 
1 .mu.m 
______________________________________ 
The software used to run the simulation was implemented with accurate base 
pushout analyses and avalanche coefficients for electrons and holes in 
GaAs. The results were then translated using the 3/2 power rule to obtain 
the equivalent BV.sub.ceo data for AlAs. Preliminary experimentation 
correlates well with the program calculations. It is readily evident from 
the first three data points plotted in FIG. 2, which represent the 
performance of a standard one-layer collector structure as shown in Table 
I, that there is an almost perfect inverse relationship between J.sub.max 
and BV.sub.ceo for these devices. By contrast, data points 4, 5 and 6, 
which represent the performance of devices constructed according to the 
first preferred embodiment of the present invention as shown in Table I, 
illustrate that J.sub.max can substantially be increased independent of 
any effect on BV.sub.ceo, by simply changing the thickness W.sub.C1 and 
the doping concentration N.sub.C1 of the first collector layer 12. 
Additionally, a sensitivity analysis has been performed which shows that 
for HBTs designed for X-band applications in which the collector thickness 
W.sub.C2 is limited to 1 .mu.m, the unintentionally doped second collector 
layer 14 can have a doping concentration N.sub.C2 as high as 
1.times.10.sup.16 atoms/cm.sup.3 (donor or acceptor) before a sudden drop 
of BV.sub.ceo takes place. Since growth techniques such as molecular beam 
epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) can 
reproducibly grow unintentionally doped layers at doping concentrations 
below 1.times.10.sup.15 atoms/cm.sup.3, and often achieving a 
concentration of 1.times.10.sup.14 atoms/cm.sup.3, the proposed structure 
of the first preferred embodiment of the present invention can be 
practically fabricated. 
The method for fabricating a second preferred embodiment of the present 
invention includes the following steps as illustrated in cross sectional 
elevation views in FIGS. 3A-3E. It incorporates a heterojunction bipolar 
transistor (HBT) design that is described in copending application Ser. 
No. 07/576,540, which is incorporated herein by reference. Although the 
second preferred embodiment is illustrated with a heterojunction device, 
the present invention may be practiced with any bipolar structure. 
(a) A substrate material for this process is shown in FIG. 3A; note that 
the vertical is exaggerated in the drawings for clarity. It is composed of 
a semi-insulating semiconductor material 11 (such as GaAs) of (100) 
orientation. 
(b) a subcollector layer 18 of n-type GaAs, for example, is epitaxially 
grown on the substrate 11 by a suitable process (such as Metal Organic 
Chemical Vapor Deposition, or MOCVD) to a thickness of 1 micron and doped 
with Si to a concentration of approximately 5.times.10.sup.18 cm.sup.-3. 
An Al.sub.x Ga.sub.1-x As graded layer 17 is next epitaxially grown on top 
of subcollector 18. The thickness of layer 17 is typically 300 .ANG., and 
the aluminum composition is graded from 0% (GaAs) at the subcollector 18 
interface to, for example, 100% (AlAs) at the opposite end (i.e. if AlAs 
is the chosen material for collector layer 14). The doping of this layer 
is also with Si to a concentration of approximately 5.times.10.sup.18 
cm.sup.-3. 
(c) a collector layer 14 is epitaxially grown on graded layer 17 to a 
thickness of 1 .mu.m and is preferably made of AlAs. The doping of layer 
14 is preferably unintentional and as low as possible (.about.10.sup.14 
cm.sup.-3). However, as mentioned previously, sensitivity analysis 
indicates that a doping as high as .about.10.sup.16 cm.sup.-3 is 
tolerable. A second collector layer 12 is epitaxially grown on collector 
layer 14 and is of graded Al.sub.x Ga.sub.1-x As, with aluminum 
composition varying from 100% (AlAs) at the collector 14 interface to 0% 
(GaAs) at the opposite end. Layer 12 is grown to a thickness of 
approximately 400 .ANG. and is doped with Si, for example, to 
approximately 1.times.10.sup.18 cm.sup.-3. 
(d) a base epilayer 16 of GaAs, for example, is deposited onto collector 
layer 12 to a thickness of 0.08 .mu.m and doped with C, for example, to a 
concentration of approximately .gtoreq.3.times.10.sup.19 cm.sup.-3. 
Emitter epilayer 20 of n-type Al.sub.x Ga.sub.1-x As is then deposited 
onto base layer 16 at a thickness of 0.05 micron by epitaxy. Next, 500 
Angstrom thick AuGe emitter ohmic contact metal, followed by 140 Angstrom 
Ni and 2000 Angstrom Au layers are evaporated onto the surface. Insulator 
layer 28 is then formed of a suitable material (such as SiO.sub.2 or 
Si.sub.3 N.sub.4) at a thickness of 4000 Angstroms by chemical vapor 
deposition (CVD). A photoresist 30 is then spun on the previous layers and 
patterned to define the location of the HBT emitters. The emitter locating 
insulator islands 28 are then created by a reactive ion etch (RIE) of the 
insulator material not protected by the photoresist using CF.sub.4 and 
O.sub.2. Photoresist 30 may optionally be removed after RIE. This yields 
the structure of FIG. 3B. 
(e) Ohmic contact layer 22 is then removed from areas not protected by the 
insulator islands 28 by ion milling using Ar, preferably at a 30.degree. 
angle to minimize backsputtering, creating emitter contact 22. Photoresist 
26 is then stripped if not done so previously. Sidewalls 32 are formed by 
depositing a 4000 Angstrom Si.sub.3 N.sub.4 (or SiO.sub.2) layer over the 
entire surface using CVD techniques. This assures an isotropic coverage. 
The insulator is then etched in low pressure (about 10-20 mTorr) CF.sub.4 
/O.sub.2 RIE, making sure that the etch is anisotropic. The etch is 
continued until all of the insulator material on the flat wafer surface is 
removed. Due to the anisotropic nature of the etch, a portion of the 
insulator material remains along the edges of insulator islands 24 and 
emitter contacts 22 as shown in FIG. 3C. Next, the areas of emitter 
epilayer 20 that are not protected by insulator islands 28 and sidewalls 
32 are chemically etched down to base epilayer 16 in, for example, a 
solution of H.sub.2 SO.sub.4 :H.sub.2 O.sub.2 :H.sub.2 O in the ratio of 
1:8:160 (by volume) as shown in FIG. 3C. 
(f) Photoresist is again spun on and patterned to define the location of 
the base contacts 34; this exposes insulator islands 28 and sidewalls 32 
in addition to a portion of the base epilayer 16. Ti/Pt/Au metals are 
evaporated in sequence at thicknesses of 500, 250 and 1500 Angstroms, 
respectively, onto the photoresist and exposed areas. The overhanging 
sidewalls 32 shadow the part of the base epilayer 16 adjacent to emitter 
36, so the evaporated metal does not contact emitter 36. The photoresist 
is then removed which lifts off the metal except the portion 34 which is 
on the base epilayer 16 and the portion 38 which is on insulator island 28 
and sidewalls 32. See FIG. 3D. 
(g) A photoresist mask (not shown) is then deposited and patterned to 
define the connection to the subcollector layer 18. Layers 16, 12 and 14 
are then etched using a solution of H.sub.2 SO.sub.4 :H.sub.2 O.sub.2 
:H.sub.2 O in the ratio of 1:8:160 (by volume), for example. Afterwards, 
AuGe/Ni/Au metals are evaporated onto the wafer to thicknesses of 
500/140/2000 .ANG., respectively, to form the collector contact 40. Then 
photoresist layer is then stripped, which lifts off all excess 
metallization. 
The most important design criterion for more independent control of 
J.sub.max and BV.sub.ceo is the formation of a first thin high-field 
region adjacent to a base and a second thick low-field region between the 
first region and the subcollector. The thickness of the first region 
should be such that the energy acquired by carriers traversing through the 
layer is less than the energy required for impact ionization in the 
material. As demonstrated, this is readily achieved with the device of the 
first preferred embodiment of the invention. 
However, other structures potentially can achieve the same electric field 
profile. For example, a third preferred embodiment of the present 
invention is illustrated in FIG. 4 which meets this criterion. The third 
preferred embodiment of the present invention is comprised of a transistor 
indicated generally at 20, which is similar to the device of the first 
preferred embodiment of the present invention with the addition of a third 
collector layer 22 inserted between the base 16 and the first collector 
layer 12. The third collector layer 22 has a width (measured in the 
direction of current flow) W.sub.C3 of 300 Angstroms, for example, and is 
doped at a relatively low concentration level N.sub.C3, such as 10.sup.14 
atoms/cm.sup.3. To achieve maximum BV.sub.ceo, layers 12 and 14 are made 
of AlAs and layer 22 is made of graded AlGaAs, with the aluminum 
composition varying from 100% (AlAs) at the interface with layer 12 to 0% 
(GaAs) at the interface with the base layer 16. Additionally, it is 
possible to let layer 12 remain as graded AlGaAs (as in the first 
preferred embodiment) and layer 22 be pure GaAs. Since this three-layer 
collector structure results in essentially the same electric field profile 
as the two-layer structure of the first preferred embodiment of the 
present invention, it will also allow substantially independent control of 
J.sub.max and BV.sub.ceo. 
An additional and important advantage of the present invention is that it 
will greatly reduce or eliminate the change in base-collector capacitance 
of a transistor in response to the base-collector bias. This change in 
capacitance can cause parametric oscillations and other problems in a 
bipolar transistor amplifier output. 
A few preferred embodiments have been described in detail hereinabove. It 
is to be understood that the scope of the invention also comprehends 
embodiments different from those described, yet within the scope of the 
claims. For example, the combination of GaAs and AlGaAs has been used 
throughout the specification by way of illustration only. It will be 
obvious to those skilled in the art that the present invention may be 
practiced with any combination of materials having a disparity in their 
respective bandgaps as a mere design choice. 
Words of inclusion are to be interpreted as nonexhaustive in considering 
the scope of the invention. 
Internal and external connections can be ohmic, capacitive, direct or 
indirect, via intervening circuits or otherwise. Implementation is 
contemplated in discrete components or fully integrated circuits in 
silicon, gallium arsenide, or other electronic materials families, as well 
as in optical-based or other technology-based forms and embodiments. 
While this invention has been described with reference to illustrative 
embodiments, this description is not intended to be construed in a 
limiting sense. Various modifications and combinations of the illustrative 
embodiments, as well as other embodiments of the invention, will be 
apparent to persons skilled in the art upon reference to the description. 
It is therefore intended that the appended claims encompass any such 
modifications or embodiments.