Transistor switch

A circuit is disclosed, including a transistor switch having a first terminal to receive an input voltage, a second terminal to output an output voltage and a gate terminal; a determination circuit, coupled to the first terminal and the second terminal of the transistor switch, to determine a lower or higher voltage between the input voltage and the output voltage; a voltage generator, coupled to the determination circuit, to generate a sum voltage or difference voltage using the lower or higher voltage; and a control circuit, coupled to the voltage generator and the gate terminal of the transistor switch, to apply the sum voltage or difference voltage to the gate terminal of the transistor switch during a first time interval.

BACKGROUND

1. Technical Field

This invention relates to transistor switches in general and more particularly to boot-strapped field effect transistor switches.

2. Background Information

Field effect transistors can be used as switches, for example when CMOS (Complementary Metal Oxide Semiconductor) technology is employed. The source and drain terminals of a field effect transistor then form the input and output terminals of a switch, while the gate terminal of the field effect transistor is a control terminal of the switch. However, field effect transistors have non-idealities which, for example, will cause the on-resistance of the switch to vary depending on the applied voltages. Furthermore transition effects may occur when the switch changes its state.

A problem with field effect transistors is the voltage dependent on-resistance. A field effect transistor used as a switch has a non-zero on-resistance Ron, which can roughly be approximated as:

where KP is the product of the mobility μ of the charge carriers and the oxide capacitance Cox, W and L are the width and the length of the channel region, respectively, and VS, VD, VGand VTare the source voltage, the drain voltage, the gate voltage and the threshold voltage, respectively. According to equation (1) the on-resistance Ronis a function of the source voltage VS, the on-resistance Rondepends on the input voltage Vin.

Another problem with field effect transistors is the dependency of the threshold voltage VTon the bulk-source voltage VBS. This effect can be approximated as:
VT=VT0±γ·(√{square root over (2·|φF|−VBS)}−√{square root over (2·|φF|)})  (2)

where γ is a technology constant which depends on the used process and φFis the Fermi level.

As equation (2) is a function of the source voltage VS, the threshold voltage VTdepends on the input voltage Vin. According to equation (1), this also influences the on-resistance Ronof the switch.

Another non-ideality of field effect transistors is charge injection. Charge injection is a transition effect, which will distort the input and output voltages of the switch when the switch turns off. When a field effect transistor turns off, the charge that has been built up in the channel must disappear. This charge will divide between the source and drain side, depending on the total capacitance at these terminals. The effect ΔV on the source voltage VSof the switch is approximated by equation (3). Parameter A is dependent on the total capacitance of the source and drain terminals of the field effect transistor.

wherein Cox, CGS, CBSand Csampleare the oxide capacity, the gate-source capacity, the bulk-source capacity and the loading capacitance of the switch when it is used in a sample-and-hold structure, respectively, and 0<A<1.

Another transition effect, which distorts the source and drain voltages of the switch when the switch turns off, is clock-feedthrough. The parasitic gate-source capacitance CGSof the transistor switch, together with the load capacitance at the source form a voltage divider between the clock signal and the output terminal. This results in feedthrough of the control signal driving the switch. This effect can be approximated as:

where VG,offand VG,onare the gate voltages when the switch is turned off and on, respectively.

A known solution for the non-linear on-resistance Ron(see equation (1)) of a transistor switch is bootstrapping. Bootstrapping makes the gate-source voltage VGSof the switch constant during the sampling phase, resulting in a signal independent on-resistance Ron. Bootstrapping is implemented, for example, by applying a constant voltage, for example a supply voltage Vdd, between the source and gate terminals when the switch is turned on.

A disadvantage of the bootstrapping technique is that the gate voltage VGis boosted to a certain value above the source voltage VS, which may result in reliability problems.

BRIEF SUMMARY

According to one embodiment of the invention, a circuit includes a field effect transistor switch, a determination circuit, a voltage generator and a control circuit. The transistor switch has a first terminal to receive an input voltage, a second terminal to output an output voltage and a gate terminal. If the transistor switch is an n-type transistor, the determination circuit determines a lower voltage between the input voltage and the output voltage, and the voltage generator generates a sum voltage by adding a first predetermined voltage to the lower voltage. If the transistor switch is a p-type transistor, the determination circuit determines a higher voltage between the input voltage and the output voltage, and the voltage generator generates a difference voltage by subtracting a first predetermined voltage from the higher voltage. The control circuit applies the sum voltage or the difference voltage to the gate terminal of the transistor switch during a first time interval.

According to a further embodiment of the invention, a circuit includes a field effect transistor switch, a determination circuit and a control circuit. The transistor switch has a first terminal to receive an input voltage, a second terminal to output an output voltage and a bulk terminal. If the transistor switch is an n-type transistor, the determination circuit determines a lower voltage between the input voltage and the output voltage, and the control circuit applies the lower voltage or a sum voltage being the sum of a predetermined voltage and the lower voltage to the bulk terminal of the transistor switch during a first time interval. If the transistor switch is a p-type transistor, the determination circuit determines a higher voltage between the input voltage and the output voltage, and the control circuit applies the higher voltage or a sum voltage being the sum of a predetermined voltage and the higher voltage to the bulk terminal of the transistor switch during a first time interval.

According to a further embodiment of the invention, a circuit includes a field effect transistor switch, a voltage generator and a control circuit. The transistor switch has a first terminal to receive an input voltage, a second terminal to output an output voltage and a gate terminal. The voltage generator generates a sum voltage by adding a predetermined voltage to the input or output voltage and a difference voltage by subtracting the predetermined voltage from the input or output voltage. The control circuit applies the sum voltage to the gate terminal of the transistor switch during a first time interval and applies the difference voltage to the gate terminal of the transistor switch during a second time interval.

According to a further embodiment of the invention, an analog-to-digital converter includes one of the circuits described above.

DETAILED DESCRIPTION

In the following embodiments of the invention are described with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of embodiments of the invention. It may be evident, however, to one skilled in the art that one or more aspects of the embodiments of the invention may be practiced with a lesser degree of these specific details. In other instances, known structures and devices are shown in block diagram form in order to facilitate describing one or more aspects of the embodiments of the invention. The following description is therefore not to be taken in a limiting sense, and the scope of the invention is defined by the appended claims.

Referring toFIG. 1, a block diagram of a circuit100is shown which serves as an exemplary embodiment of a first aspect of the invention. The circuit100comprises a transistor MSA, a determination circuit101, a voltage generator102and a control circuit103.

The transistor MSA functions as a field effect transistor switch and receives an input voltage Vinat its first terminal and provides an output voltage Voutat its second terminal when the switch is turned on, i.e. the channel of the transistor MSA is conducting. The channel of the transistor MSA may be n-doped or p-doped.

The transistor MSA may, for example, form part of a discrete time analog sampling circuit, which samples the input voltage Vinin order to convert an analog signal into a digital value.

The determination circuit101has two input terminals, one of the two input terminals is connected to the first terminal of the transistor MSA and the other input terminal is connected to the second terminal of the transistor MSA. An output terminal of the determination circuit101is connected to an input terminal of the voltage generator102, an output terminal of which is wired to an input terminal of the control circuit103. An output terminal of the control circuit103drives the gate terminal of the transistor MSA.

If the transistor MSA is an n-type transistor, the function of the determination circuit101is to determine which one of the input voltage Vinand the output voltage Voutis lower. For example, this measurement is undertaken at the moment when the switch closes, i.e. when the transistor MSA is switched from a not conducting state to a conducting state. The lower voltage Vlowbetween the input voltage Vinand the output voltage Voutis transferred to the voltage generator102which adds a predetermined voltage to the lower voltage Vlow. The predetermined voltage is a fixed voltage which does not vary while the transistor MSA is conducting. For example, the predetermined voltage may be a supply voltage Vdd, which provides the power supply for the circuit100, or may be a fixed voltage derived from the supply voltage Vdd, wherein the fixed voltage is smaller than the supply voltage Vdd. The sum voltage Vsumof the lower voltage Vlowand the predetermined voltage, i.e. for example (Vlow+Vdd), is provided to the control circuit103. The control circuit103applies the sum voltage Vsumto the gate terminal of the transistor MSA during a first time interval. During a second time interval a ground potential Vssmay, for example, be applied to the gate terminal of the transistor MSA.

For example, during the first time interval, the transistor MSA is in the “on” state. The sum voltage Vsumis applied to the gate terminal and a low on-resistance is established from drain to source. When the circuit100is used as a part of an analog-to-digital converter, the analog input signal is sampled during the first time interval. During the second time interval the gate terminal of the transistor MSA is grounded so that the transistor MSA is in the “off” state.

If the transistor MSA is a p-type transistor, the functions of the determination circuit101, the voltage generator102and the control circuit103slightly differ from their functions when the transistor MSA is an n-type transistor. For a p-doped transistor channel the determination circuit101determines which one of the input voltage Vinand the output voltage Voutis higher. For example, this measurement is undertaken at the moment when the switch closes, i.e. when the transistor MSA is switched from a not conducting state to a conducting state. The higher voltage Vhighbetween the input voltage Vinand the output voltage Voutis transferred to the voltage generator102which subtracts a predetermined voltage, for example the supply voltage Vdd, from the higher voltage Vhigh. The predetermined voltage is a fixed voltage which does not vary while the transistor MSA is conducting. The difference voltage Vdifferenceof the higher voltage Vhighand the predetermined voltage, i.e. for example (Vhigh−Vdd), is provided to the control circuit103. The control circuit103applies the difference voltage Vdifferenceto the gate terminal of the transistor MSA during the first time interval. During the second time interval the supply voltage Vddmay, for example, be applied to the gate terminal of the transistor MSA.

The gate terminal of the transistor MSA may be set at the minimum (or maximum in case of a p-type transistor MSA) of the source and drain voltages, raised (or diminished) with the predetermined fixed voltage, for example the supply voltage Vdd. This minimal (or maximal) voltage is determined at the moment the switch closes. During the time the switch is closed, the gate voltage keeps following this voltage. By choosing the minimal (or maximal) voltage side, the differences between gate and source voltage and between gate and drain voltage will not exceed the supply voltage Vdd. This may help to solve the reliability problem addressed above.

Referring toFIG. 2, a block diagram of a circuit200. The circuit200comprises a transistor MSA, a determination circuit201and a voltage generator202. The circuit200may also comprise a control circuit203to drive the gate terminal of the transistor200.

As in the circuit100, the transistor MSA functions as a field effect transistor switch and receives an input voltage Vinat its first terminal and provides an output voltage Voutat its second terminal when the switch is turned on, i.e. the channel of the transistor MSA is conducting. The channel of the transistor MSA may be n-doped or p-doped.

The determination circuit201has two input terminals, one of the two input terminals is connected to the first terminal of the transistor MSA and the other input terminal is connected to the second terminal of the transistor MSA. An output terminal of the determination circuit201is connected to an input terminal of the control circuit202. An output terminal of the control circuit202is wired to the bulk terminal of the transistor MSA.

When the transistor MSA is an n-type transistor, the function of the determination circuit201is to determine which one of the input voltage Vinand the output voltage Voutis lower. For example, this measurement is undertaken at the moment when the switch closes, i.e. when the transistor MSA is switched from a not conducting state to a conducting state. The lower voltage Vlowbetween the input voltage Vinand the output voltage Voutis transferred to the control circuit202which applies the lower voltage Vlowto the bulk terminal of the transistor MSA during a first time interval. Alternatively, the control circuit202may add a predetermined fixed voltage to the lower voltage Vlowand may apply this sum voltage to the bulk terminal during the first time interval. During a second time interval a ground potential Vssmay, for example, be applied to the bulk terminal of the transistor MSA. For example, during the first and second time interval the transistor MSA is in the “on” and “off” state, respectively.

When the transistor MSA is a p-type transistor, the determination circuit201determines which one of the input voltage Vinand the output voltage Voutis higher. This higher voltage Vhighor a sum voltage of a predetermined voltage and the higher voltage Vhighis applied to the bulk terminal of the transistor MSA during the first time interval. During the second time interval the supply voltage Vddmay, for example, be applied to the bulk terminal of the transistor MSA.

The transistor MSA may comprise a triple-well transistor. A triple-well transistor comprises a first well formed in a substrate. A second well is formed in the first well. One or more third wells, which are for example source and drain, are formed in the second well.

The bulk-source voltage VBSmay be fixed since the bulk terminal is driven with the chosen minimal (or maximal) voltage. Consequently, no variation of the threshold voltage VTcan occur (see equation (2)).

According to one embodiment of the invention, the first and second aspects of the invention, which are exemplarily explained above, can be combined. InFIG. 3a block diagram of a circuit300is shown which serves as an exemplary embodiment of a combination of the first and second aspects of the invention. In the circuit300, the channel of the field effect transistor MSA is n-doped. The determination circuit, which determines the lower voltage Vlowbetween the input voltage Vinand the output voltage Vout, is denoted by301inFIG. 3. Furthermore, inFIG. 3a clock signal φ and an inverted clock signalφare shown. The clock signal φ controls the switch state of the transistor switch MSA. During the first time intervals the clock signal φ is high (the inverted clock signalφis low) and the switch is closed meaning the source-drain path of the transistor MSA is conducting. During the second time intervals the clock signal φ is low (the inverted clock signalφis high) and the switch is open meaning the source-drain path of the transistor MSA is not conducting.

When the clock signal φ is low, transistors MN1and MN2are closed, charging capacitor C1to the supply voltage Vdd. Transistors MN3and MN4are also closed, thus keeping the gate terminal of the transistor MSA to the ground potential Vss, hence the transistor MSA is not conducting and the switch is open. Transistor MP1keeps the gate terminal of transistor MP2at the supply voltage Vdd. Hence the transistor MP2is not conducting and isolates a circuit node302from the gate terminal of the transistor MSA.

When the clock signal φ changes to a high voltage, the source-drain path of the transistor MSA becomes conductive and the switch will close. The clock signal φ also triggers the determination circuit301to select between the input voltage Vinand the output voltage Vout. Because the transistor MSA may be an n-type transistor, the determination circuit301decides which one of the input voltage Vinand the output voltage Voutis lower and closes an appropriate transmission gate TG1or TG2. This decision does not change until the clock signal φ goes low again. The transistors MN1, MN2, MP1and MP4are all opened by the change of the clock signal φ. As a result, a circuit node303changes to the lower voltage Vlowselected by the determination circuit301. Because the capacitor C1was charged to the supply voltage Vddduring the second time interval, the voltage at the circuit node302raises to (Vlow+Vdd). Transistor MN5will lower the gate voltage of transistor MP2, closing the transistor MP2. Closing the transistor MP2results in raising the gate of the transistor MSA to (Vlow+Vdd). This will close transistor MN6, which further helps to bring the gate of the transistor MP2to the lower voltage Vlow, making a low-resistance connection between the boost capacitance C1and the gate of the transistor MSA. As the gate of the transistor MSA is now at (Vlow+Vdd), the switch is closed and the on-resistance is signal-independent as its gate-source voltage VGSequals the supply voltage Vdd.

In the circuit300the MSA transistor is a triple-well transistor, and the circuit node303is connected to the bulk terminal of the transistor MSA. Consequently, when the transistor MSA is conducting, its bulk voltage VBis equal to its source voltage VS(namely the lower voltage Vlow). This results in a fixed bulk-source voltage VBSwhich makes the threshold voltage VTsignal-independent and cancels the above mentioned body effect. During the second time intervals the circuit node303is set to the ground potential Vss, so no forward biasing of the bulk diodes is possible.

The transistor MN2is driven by a clock signalφbo, which is the inverted clock signalφraised with the supply voltage Vdd. This may allow design of the circuit300without reliability problems as no gate-source voltage VGSor gate-drain voltage VGDexceeds the nominal supply voltage Vdd.

According to equation (3) the charge injection depends on the gate-source voltage VGS, the gate-source capacitance CGSand the bulk-source capacitance CBS. As in the circuit300, the gate-source voltage VGSand the bulk-source voltage VBSare fixed during the first time intervals when the switch is closed, the parasitic transistor capacitors are also fixed. Therefore, the voltage jump due to charge injection is independent of the input voltage Vin. This allows, for example, design of switched capacitor systems without the necessity of delayed clocks.

FIG. 4shows a possible implementation of the determination circuit301. The determination circuit301shown inFIG. 4is designed in a manner that it determines the lower voltage Vlowwhen the clock signal φ goes high. Furthermore, transistors MN7and MN8keep the output terminals outn and outp of the determination circuit301to the ground potential Vsswhen the inverted clock signalφis high. This ensures that both transmission gates TG1and TG2are open. Cross-coupled transistors MP3, MP4, MN9and MN10regenerate the voltage difference between the input terminals inp and inn of the determination circuit301.

Referring toFIG. 5, a block diagram of a circuit500is shown which serves as an exemplary embodiment of a third aspect of the invention. The circuit500includes a transistor MSA, a voltage generator501and a control circuit502.

The transistor MSA comprises a field effect transistor switch and receives an input voltage Vinat its first terminal and provides an output voltage Voutat its second terminal when the switch is turned on, i.e. the channel of the transistor MSA is conducting. The channel of the transistor MSA may be n-doped or p-doped.

The transistor MSA may, for example, comprise part of a discrete time analog sampling circuit, which samples the input voltage Vinto convert an analog signal into a digital value.

The voltage generator501includes an input terminal, which is connected to the first terminal of the transistor MSA. An output terminal of the voltage generator501is wired to an input terminal of the control circuit502. An output terminal of the control circuit502is connected to the gate terminal of the transistor MSA.

The voltage generator501generates a sum voltage by adding a predetermined voltage to the input voltage Vinand to generate a difference voltage by subtracting the predetermined voltage from the input voltage Vin. The predetermined voltage may, for example, be the supply voltage Vdd. In this case the voltage generator501produces the sum voltage (Vin+Vdd) and the difference voltage (Vin−Vdd). The control circuit502applies the sum voltage to the gate terminal of the transistor MSA during a first time interval and applies the difference voltage to the gate terminal of the transistor MSA during a second time interval.

If the channel of the transistor MSA is n-doped, the transistor MSA is conducting during the first time interval and not conducting during the second time interval. If the channel of the transistor MSA is p-doped, the transistor MSA is not conducting during the first time interval and conducting during the second time interval.

When comparing the gate voltages of the transistor MSA during the first time interval and the second time interval, there is a difference in gate voltage that equals two times the predetermined voltage, for example 2·Vdd. Because this voltage difference is independent of the input voltage Vin, equation (4) is also independent of the input voltage Vin(since VG,off−VG,on=2·Vdd). Hence clock-feedthrough of circuit500results in a voltage jump which is independent of the input voltage Vin.

InFIG. 6, a block diagram of a circuit600is shown, which is a variation of the circuit500shown inFIG. 5. Instead of being connected to the input terminal of the transistor MSA, a voltage generator601of the circuit600is connected to the output terminal of the transistor MSA. The function of the voltage generator601is to generate a sum voltage by adding a predetermined voltage to the output voltage Voutand to generate a difference voltage by subtracting the predetermined voltage from the output voltage Vout. The predetermined voltage may, for example, be the supply voltage Vdd. In this case the voltage generator601produces the sum voltage (Vout+Vdd) and the difference voltage (Vout−Vdd). A control circuit602, which is coupled to the voltage generator601, applies the sum voltage to the gate terminal of the transistor MSA during the first time interval and applies the difference voltage to the gate terminal of the transistor MSA during the second time interval.

InFIG. 7, a block diagram of a circuit700is shown, which is a combination of the circuits500and600. In the circuit700both the input terminal and the output terminal of the transistor MSA are connected to a voltage generator701. The voltage generator701may generate sum voltages by adding a predetermined voltage to the input voltage Vinor the output voltage Voutand may generate difference voltages by subtracting the predetermined voltage from the input voltage Vinor the output voltage Vout. A control circuit702, which is coupled to the voltage generator701and the gate terminal of the transistor MSA, applies the generated sum and difference voltages to the gate of the transistor MSA during first and second time intervals. In case the predetermined voltage is the supply voltage Vdd, the following combinations are possible:

It may be provided that the control circuit702selects an appropriate combination among the four combinations listed above for each time interval, wherein the supply voltage Vddcan be replaced by any predetermined voltage. As an example, the second combination may be advantageous over the first combination due to the following reasons. The gate-drain capacitance CGDof the transistor MSA may result in feedthrough of the gate signal to the output terminal. Thus, when using a boosted input voltage Vinduring the second time interval, the input signal will be fed through to the output voltage Vout(diminished by a factor of CGD/(CGD+Csample)). This effect may disappear when a lowered version of the output voltage Voutis used.

InFIG. 8, a block diagram of a circuit800is shown which serves as a further exemplary embodiment of the third aspect of the invention. In the circuit800, the channel of the transistor MSA is n-doped. As inFIG. 3a clock signal φ and an inverted clock signalφdetermine the state of the switch. During the first time intervals the clock signal φ is high (the inverted clock signalφis low) and the switch is closed meaning the source-drain path of the transistor MSA is conducting. During the second time intervals the clock signal φ is low (the inverted clock signalφis high) and the switch is open meaning the source-drain path of the transistor MSA is not conducting.

During the second time intervals transistors Mt4and Mt5are closed and charge capacitor C2to the supply voltage Vdd. Transistor Mb1passes the input voltage Vinto capacitor C3charging the capacitor C3to −Vdd. Transistor Mb6closes transistor Mb2, lowering the drain of transistor Mb3to (Vin−Vdd). As a result the transistor Mb2closes, bringing the gate of the transistor MSA to (Vin−Vdd), what opens the switch.

During the first time intervals the operation is reversed. Now the capacitor C3is recharged to −Vdd, while transistors Mt1and Mt6are closed, closing transistor Mt2. This brings the bottom node of the capacitor C2to (Vin+Vdd). The transistor Mt2transfers this voltage and closes transistor Mt3. This brings the gate of the transistor MSA to (Vin+Vdd), what closes the switch.

As a result, the difference in gate voltage of the transistor MSA during the first and second time intervals is 2·Vddand is independent of the input voltage Vin. Therefore the effect of clock-feedthrough is independent of the input voltage Vin.

Transistors Mt3and Mb3are used to ensure that the gate-drain voltage VGDof the transistors Mt2and Mb2do not exceed the supply voltage Vdd.

The transistor Mt5is driven by a clock signalφbo, which is the inverted clock signalφraised with the supply voltage Vdd. Transistor Mb5is driven by a clock signalφab, which is the inverted clock signalφlowered with the supply voltage Vdd.

According to one embodiment of the invention, the transistors of the circuits100,200,300,500,600,700or800are Metal Oxide Semiconductor (MOS) transistors and are implemented in CMOS technology.

All three aspects of the invention, the exemplary embodiments of which are shown inFIGS. 1 to 8, may be combined in any manner. For example, the first and the third aspect may be combined by driving an n-type transistor MSA with the voltage (Vlow+Vdd) during the first time intervals and the voltage (Vlow−Vdd) during the second time intervals. In case of a p-type transistor MSA, the voltage (Vhigh−Vdd) would be applied during the first time intervals and the voltage (Vhigh+Vdd) during the second time intervals.