Semiconductor device

A semiconductor device includes first and second electrodes, a first semiconductor region between the first and second electrodes, a second semiconductor region between the first semiconductor region and the second electrode, a third semiconductor region between the first semiconductor region and the second electrode, a fourth semiconductor region between the first semiconductor region and the first electrode, a third electrode between the first electrode and the first semiconductor region, a first insulating film between the third electrode and both the first electrode and the first semiconductor region, a fifth semiconductor region between the fourth semiconductor region and the first electrode and in contact with the first electrode, a sixth semiconductor region between the fourth semiconductor region and the first electrode and in contact with the first electrode, and a seventh semiconductor region between the fourth semiconductor region and the first insulating film and in contact with the first semiconductor region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-018529, filed Feb. 3, 2017, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

As one high breakdown voltage (for example, 300 V or higher) power semiconductor element, an insulated gate bipolar transistor (IGBT) is known.

In most cases, the IGBT is used with backflow diodes being connected to each other in a reversely-parallel manner. Generally, there is a need to provide these diodes in another chip because the IGBT does not have diode regions that are arranged to be reversely in parallel with each other. As a semiconductor device in which an IGBT and diode are integrated, there is a reversely conductive-type IGBT. However, in the reversely conductive-type IGBT, injection of many holes occurs as a result of impurity elements that are implanted into a p type base region of the IGBT, and thus in some cases, it is difficult to further increase the switching speed of a diode.

DETAILED DESCRIPTION

Embodiments provide a semiconductor device that is capable of improving the switching speed of a semiconductor device such as an IGBT.

In general, according to one embodiment, there is provided a semiconductor device including a first electrode, a second electrode, the first and second electrodes spaced from each other in a first direction, a first semiconductor region of a first conductivity type between the first electrode and the second electrode, a second semiconductor region of a second conductivity type between the first semiconductor region and the second electrode, a third semiconductor region of the first conductivity type between the first semiconductor region and the second electrode, wherein the third semiconductor region is adjacent to the second semiconductor region in a second direction orthogonal to the first direction, and has a higher first impurity type concentration than the first semiconductor region, a fourth semiconductor region of the second conductivity type between the first semiconductor region and the first electrode, a first insulating film between the first semiconductor region and the first electrode, a third electrode between the first electrode and the first semiconductor region, with a first insulating film interposed between the third electrode and the first electrode and the first semiconductor region, a fifth semiconductor region of the first conductivity type, between a portion of the fourth semiconductor region and the first electrode and in contact with the first electrode, a sixth semiconductor region of the second conductivity type between a portion of the fourth semiconductor region and the first electrode and in contact with the first electrode, wherein the sixth semiconductor region has a higher second conductivity type impurity concentration than the fourth semiconductor region, and a seventh semiconductor region of the first conductivity type between the fourth semiconductor region and the first insulating film and in contact with the first semiconductor region.

Embodiments will be described below with reference to the drawings. In the following description, like elements are given like reference numerals, and repetitious descriptions of the same element are suitably avoided.

It is noted that a relationship between the thickness and width of each component in the drawings, a ratio in size between components, and the like are not necessarily the same as those of an actual device. Furthermore, in some cases, even the same elements are expressed having different dimensions or different ratios among the drawings.

In the following description, notations, n+, n, n−, p+, and p, indicates relative high and low levels of impurity concentrations of the respective conductivity types. That is, the impurity concentration is indicated as being relatively high in this order: a region to which “+” is attached, a region to which any notation is not attached, a region to which “−” is attached. Furthermore, the expression “impurity concentration is high” may be replaced with the expression “carrier concentration is high”.

Each embodiment that will be described herein may be implemented with the p type and n type regions of each semiconductor region being reversed.

First Embodiment

A first embodiment of the present disclosure is described with reference toFIGS. 1A, 1B, 2A, and 2B.FIG. 1Ais a schematic cross-sectional diagram taken along line A-A′ ofFIG. 1Billustrating a semiconductor device according to the first embodiment.FIG. 1Bis a schematic plan view of the semiconductor device ofFIG. 1A. A three-dimensional coordinate system (XYZ coordinate system) is introduced into the figures referred to for description, in order to express a direction with reference to the semiconductor device. The X direction and the Y direction are orthogonal to each other on the same plane. Furthermore, the Z direction is orthogonal to the X direction and to the Y direction.

The semiconductor device1according to the first embodiment has a vertical electrode structure. The semiconductor device1includes an emitter electrode10and a collector electrode19. The direction from the collector electrode19to the emitter electrode10is the Z direction. It is noted that in the semiconductor device1, an IGBT that functions as a transistor and a free wheeling diode (FWD) that functions as a backflow diode are integrated.

In the semiconductor device1, an n− type semiconductor region15and an n type semiconductor region16(both of which together forma first semiconductor region25) are provided between the emitter electrode10and the collector electrode19. The n type semiconductor region16is positioned between the collector electrode19and the n− type semiconductor region15in the Z direction. It is noted that the n− type semiconductor region15may be considered to be an n− type base region and the n type semiconductor region16considered as an n type buffer region, in an exchanged manner.

A p+ type collector region17and an n+ type cathode region18are provided between the n type semiconductor region16and the collector electrode19. Furthermore, the p+ type collector region17and the n+ type cathode region18are located adjacent to each other in the Y direction. The p+ type collector region17and the n+ type cathode region18electrically connect to the collector electrode19.

In the Z direction, a p type base region12is provided between the n− type semiconductor region15and the emitter electrode10. An n+ type emitter region11is provided between a portion of the p type base region12and the emitter electrode10. The p type base region12and the n+ type emitter region11are both electrically connected to the emitter electrode10.

In a diode operation, the emitter electrode10functions as an anode electrode and the collector electrode19functions as a cathode electrode.

Furthermore, a gate electrode13is in located adjacent to, and spaced from, the n− type semiconductor region15, the p type base region12, and the n+ type emitter region11, by a gate insulating film14located therebetween.

The gate electrode13extends in the X direction and the Z direction. Furthermore, a plurality of gate electrodes13are provided spaced from each other in the Y direction. The structure of the gate electrode13that is illustrated inFIG. 1Ais a so-called trench gate structure, but the gate electrode13may be a planar type.

The semiconductor device1has a narrowed n type channel region20that extends between at least a part of the p type base region12and the gate insulating film14. In the present embodiment, the n type semiconductor region which is interposed between the p type base region12and the gate insulating film14is defined as the narrowed n type channel region20. That is, the narrowed n type channel region20is positioned, in the Y direction, between the p type base region12and the gate insulating film14. Furthermore, the narrowed n type channel region20is in contact with, and extends in the z-direction from, the n− type semiconductor region15. The narrowed n type channel region20and the n− type semiconductor region15may be collectively defined as the n− type semiconductor region15, without the narrowed n type channel region20being regarded as a part of the n− type semiconductor region15. Additionally, a p+ type contact region9is formed between the narrowed n type channel region20and the emitter electrode10. That is, the narrowed n type channel region20is located, in the Z direction, between the n− type semiconductor region15and the p+ type contact region9. Accordingly, the narrowed n type channel region20is bounded by the p+ type contact region9, the p type base region12, and the gate insulating film14over the gate electrode13.

Furthermore, although not illustrated, a gate electrode13that is interposed between p+ type contact regions9and narrowed n type channel regions20in the Y direction does not function as a gate and thus, may be connected to the emitter electrode10. In this construct, the total gate capacitance can be reduced, which is advantageous for an increase in speed.

An example of a material of each constituent element is described.

For example, a main component of each of the plurality of semiconductor regions that are provided between the collector electrode19and the emitter electrode10is silicon (Si). The main component of each of the plurality of semiconductor regions may also be silicon carbide (SiC), gallium nitride (GaN), or the like. As an impurity element that is of a conductivity type, such as an n+ type, an n type, or an n− type, for example, phosphorus (P), arsenic (As), or the like is used. As an impurity element that is of a conductivity type, such as a p+ type, a p type, or the like, for example, boron (B) or the like is used. Furthermore, in the semiconductor device1, the conductivity types that are a p type and an n type can be switched for implantation, and the same effect is obtained.

Each of the material of the collector electrode19and the material of the emitter electrode10, for example, is a metal that includes at least one metal which is selected from a group of aluminum (Al), titanium (Ti), nickel (Ni), tungsten (W), gold (Au), and the like. Materials of each of the gate electrode13and an emitter potential electrode23, for example, include polysilicon. Furthermore, materials of an insulating film, for example, include silicon oxide, silicon nitride, and the like.

Operations and Effects

Operations and effects according to the present embodiment are described here with reference toFIGS. 1A to 3.

Operations of the semiconductor device1according to the first embodiment are described.

FIGS. 2A and 2Bare schematic cross-sectional diagrams illustrating an ON state of the semiconductor device1according to the first embodiment.

Operations in an ON state of an IGBT unit and an ON state of a FWD unit are described with reference toFIG. 2. In the semiconductor device1, the IGBT unit and the FWD unit are integrated. Thus, for the purpose of description, the functional portions of the device are referred to as the IGBT unit and the FWD unit, respectively.

First, operation of the IGBT unit in the semiconductor device1described with reference toFIG. 2A.FIG. 2Ais a schematic cross-sectional diagram illustrating operation that results when the IGBT unit is in the ON state.

Higher potential is applied to the collector electrode19than to the emitter electrode10, and a potential equal to or higher than threshold potential Vth is supplied to the gate electrode13. In this case, an n type channel region is formed on the surface of the p type base region12along the gate insulating film14, and the IGBT unit is in the ON state. More precisely, an electron current e flows from the n+ type emitter region11to the p type base region12, the n− type base region15, the n type buffer region16, and the p+ type collector region17in this order. Likewise, a hole current h flows from the p+ type collector region17to the n type buffer region16, the n− type base region15, and the p type base region12in this order.

In the FWD unit, portions of the semiconductor regions16and18are considered as an n type cathode region, a portion of the semiconductor region15as an intrinsic region, and the electrode10as an anode electrode10and electrode19as a cathode electrode19in a switched, and thus a PIN diode which includes the anode electrode10, an anode region (which is the p type base region)12, an intrinsic region15, cathode regions16and18, and a cathode electrode19is formed. While the IGBT unit is in the ON state, because higher potential is applied to the anode electrode10than to the cathode electrode19, with respect to the PIN diode of the FWD unit, a reverse bias voltage is applied. Accordingly, current does not flow through the FWD unit.

At this point, because the narrowed n type channel region20is an n type semiconductor region, the hole current h is divided into a component that flows directly into the p type base region12, a component that flows into the p type base region12through the narrowed n type channel region20, and a component that flows into the p+ type contact region9through the narrowed n type channel region20.

Next, operation of the FWD unit in the semiconductor device1is described with reference toFIG. 2B.FIG. 2Bis a schematic cross-sectional diagram illustrating operation that results when the FWD unit is in the ON state.

Generally, immediately before the IGBT unit enters the ON state, regenerative current flows within the PIN diode of the FWD unit and the PIN diode operates as the backflow diode. While the backflow diode operates, the bias voltage is temporarily applied in the forward direction between a cathode and an anode.

The n+ type cathode region18is in an ohmic contact with the cathode electrode19. Therefore, the electron current e flows from the n+ type cathode region18through the first semiconductor region25and the p type base region12and then into the anode electrode10. The potential of the narrowed n type channel region20is lower than that of the p type base region12. Therefore, the electrons flow into the narrowed n type channel region20. Additionally, the p+ type contact region9has a higher p type impurity concentration than does the p type base region12. Therefore, the potential of the p type base region12becomes lower than that of the p+ type contact region9. As a result, in a lower portion of the p+ type contact region9, the electrons flow to the p type base region12side. Accordingly, an electron current e is formed between the cathode electrode (e.g., the collector electrode19) and the anode electrode (e.g., the emitter electrode10).

That is, when the electrons flow in the direction from the cathode electrode (e.g., the collector electrode19) side to the anode electrode (e.g., the emitter electrode10) side and reach the vicinity of the p+ type contact region9, the electrons move in the horizontal direction, that is, in the direction that is approximately in parallel with the Y direction. With this movement of the electrons, the portion of the p+ type contact region9in contact with the anode electrode (e.g., the emitter electrode10) becomes a positive electrode, and the narrowed n type channel region20that is positioned under an anode region21becomes a negative electrode with respect to the p+ type contact region9. With bias on the positive electrode and the negative electrode, an energy barrier with respect to holes between the p+ type contact region9and the narrowed n type channel region20is lowered. Accordingly, holes are injected from the p+ type contact region9to the narrowed n type channel region20, and flow toward the cathode electrode (e.g., the collector electrode19). It is noted that the holes are also injected from the p type base region12, but because the p type base region12has a relatively low p type impurity concentration as compared to that of the p+ type contact region9, the amount of the injected holes from the p type base region12is smaller than that from the p+ type contact region9. The injected holes form the whole current h in the semiconductor device1. In this manner, in the FWD unit in the ON state, holes flow from the anode electrode (e.g., the emitter electrode10) side to the cathode electrode (e.g., the collector electrode19) side, and electrons flow from the cathode electrode (e.g., the collector electrode19) side to the anode electrode (e.g., the emitter electrode10) side.

The hole current h increases if the width of the p+ type contact region9in the Y direction or a contact area between the p+ type contact region9and the anode electrode10is increased. An amount of holes injected from the anode side is adjusted by adjusting the width or the contact area of the p+ type contact region9and the p type impurity concentration thereof compared to that of the p type base region12.

At this point, as described above, under the anode electrode (e.g., the emitter electrode10), the amount of holes injected from the p type base region12with the relatively lower impurity concentration is small, but an amount of holes injected from the p+ type contact region9with the higher concentration is large. However, the narrowing of the width of the p+ type contact region9can reduce the amount of hole injection from the p+ type contact region9. Furthermore, in the FWD unit, in the Y direction, it is easy to modify the region where the p+ type contact region9is provided and the region where the p+ type contact region9is not provided. Accordingly, the contact area between the p+ type contact region9and the anode electrode10can be decreased. The decrease in the contact area reduces the amount of holes injected from the anode side in operation of the FWD. Because the amount of injected holes can be reduced as described above, the recovery speed becomes high.

FIG. 3is a schematic cross-sectional diagram illustrating a recovery state of the FWD unit of the semiconductor device according to the first embodiment.

When the FWD unit is in the recovery state, the IGBT unit is in an OFF state.

FIG. 3illustrates a state where the voltage between the anode and the cathode is a reverse bias. More precisely, a voltage is applied between the cathode and the anode in such a manner that the anode electrode10is a negative electrode and the cathode electrode19is a positive electrode.

In a state where forward bias is applied between the anode and the cathode, where reverse bias is then applied between the anode and the cathode, holes that are present in the first semiconductor region25move toward the anode electrode10side of the device. Furthermore, electrons that are present in the first semiconductor region25move toward the cathode electrode19side of the device.

When a reverse bias is applied to the device, electrons flow into the cathode electrode19through the cathode region18, and holes flow into the anode electrode10through the anode region (which is the p type base region)12.

At the time of the recovery, while the electron current e is flowing through the cathode electrode19and the hole current h is flowing through the anode electrode10, a depletion region grows from the junction of the anode region12with the first semiconductor region25. Accordingly, in the FWD unit, conduction between the anode electrode10and the cathode electrode19is gradually reduced and eventually prevented.

At this time, the smaller the number of carriers in the vicinity of the junction portion of the anode region12with the first semiconductor region25, the more easily the depletion region is increased in size and the higher the speed at which a voltage increases. For this reason, as described above, with the structure of the p type base region12, the narrowed n type channel region20, and the p+ type contact region9, the reduction in the amount of injected holes can increase the speed of the resulting increase in voltage.

On the other hand, when a positive bias voltage is applied to the gate electrode13in order to cause the anode electrode10and the cathode electrode19of the IGBT to become electrically connected, an n type channel region needs to be formed on a surface of the p type base region12of the IGBT. For this reason, if the structure in which the p type base region12, the narrowed n type channel region20, and the p+ type contact region9are combined, which is disclosed in the present application, is not employed, a large amount of holes are injected into the n− type base region15from the p type base region12, and thus it becomes difficult to increase the switching speed of the device.

In contrast, as described with reference toFIGS. 2A and 2B, with the semiconductor device1according to the first embodiment, electrons that are injected from the n+ type cathode region18in a conductive state of the FWD flow into the anode electrode10through the narrowed n type channel region, without entering the portion of the p type base region12of the IGBT directly over the first semiconductor region25. Accordingly, holes can be suppressed from being injected from the p type base region12into the first semiconductor region25, and the increase in speed of the FWD can be realized. In this manner, according to the exemplary embodiment of the present disclosure, an IGBT region can also be used as the FWD, and an IGBT and a FWD can be easily integrated.

Next, operation of the semiconductor device according to a reference example is described.

FIG. 4is a schematic cross-sectional diagram illustrating operation of a semiconductor device3according to a first reference example.

The semiconductor device3has an IGBT region101and a FWD region102, and has a structure in which the IGBT region101and the FWD region102are in direct contact with each other.

FIG. 4illustrates a state where the PIN diode of the FWD region102functions as the backflow diode. In this case, in the FWD region102, the electron current e flows from the cathode side to the anode side, and the hole current h flows from the anode side to the cathode side.

In the meantime, a state where the potential of the cathode electrode19is higher than the potential of the anode electrode10occurs temporarily. At this point, the cathode electrode19and the anode electrode10are shared by the IGBT region101and the FWD region102.

Therefore, a forward bias voltage is also applied to a parasitic diode (formed by the p type base region12aand the n− type base region15a) in the IGBT region101, and holes are injected from the p type base region12ainto the n− type base region15a.

Furthermore, an n+ type cathode region18having a high n-type impurity concentration is adjacent to the p type collector region17. Thereover, the IGBT region101and the FWD region102are in direct contact with each other. For this reason, electrons e2that are emitted from the n+ type cathode region18are diffused into the IGBT region101.

Then, when the electrons that are diffused from the n+ type cathode region18into the IGBT region101form a charge which exceed an energy barrier at the parasitic diode (the p type base region12aand the n− type base region15a), holes are injected from the p type base region12ainto the n− type base region15a.

In this manner, holes are diffused into the IGBT region101. InFIG. 4, the holes that are diffused from the p type base region12aof the IGBT into the FWD region102are expressed holes h2. Accordingly, when the PIN diode is conductive, carriers are diffused into the IGBT region101.

On the other hand, in a case where the PIN diode in the FWD region102is turned off, a state where reverse bias is applied to the PIN diode of the FWD region102is reached.

In this case, a voltage is applied between the cathode and the anode in such a manner that the anode electrode10is a negative electrode and the cathode electrode19is a positive electrode. That is, in the FWD region102, holes that are present in the second portion25bof the first semiconductor region25move to the anode electrode10side of the device and electrons that are present in the second portion25bof the first semiconductor region25move to the cathode electrode19side of the device.

Furthermore, under these conditions, holes that are present in a first portion25aof the first semiconductor region25of the IGBT region101are discharged to the emitter electrode10through the p-type base region12a.

In this manner, in the semiconductor device3, before and after a recovery operation, not only do carriers stay in the FWD region102, but the carriers also stay in the IGBT region101. Accordingly, there is a problem in that a limitation is imposed on an increase in the recovery speed of the PIN diode.

FIG. 5is a schematic cross-sectional diagram illustrating operation of a semiconductor device according to a second reference example.

A separation region103is provided in the semiconductor device4between the IGBT region101and the diode region102of the device as illustrated inFIG. 5. A relatively thick p+ type eighth semiconductor region30in the Z direction is provided in the separation region103. The eighth semiconductor region30extends from the anode electrode10side of the device toward the cathode electrode19side of the device. An insulating region31is provided between portions of the eighth semiconductor region30and the anode electrode10.

The eighth semiconductor region30and the anode electrode10are electrically separated from each other in the separation region. At least a part of the eighth semiconductor region30contacts the third portion25cof the first semiconductor region25. The depth of the eighth semiconductor region30extending inwardly of the anode10side of the device is greater than the depth of the gate insulating film14.

Furthermore, the p type collector region17and the cathode region18are disposed adjacent to each other in the separation region103.

The provision of the separation region103keeps the IGBT region101and the FWD region102separated by a distance from each other. Therefore, when the PIN diode in the FWD region102is turned on, although holes are injected from a p type base region12of the IGBT, these holes h easily recombine with electrons. Accordingly, when compared with the first reference example, in a FWD state, the number of carriers that are accumulated in the n− type base region can be reduced and an increase in speed is possible.

However, due to the creation of the separation region, a region that does not contribute to conduction between the emitter10and collector19results, and this region cannot be effectively used in the IGBT.

In contrast, in the semiconductor device1, the IGBT and the diode are integrated, and a part of the p type base region12that is formed between trenches of the IGBT is the narrowed n type channel region20, and the p+ type contact region9is formed on the narrowed n type channel region20.

With this structure, in the conductive state of the FWD, electrons that are injected from an n+ cathode region18flow into the anode electrode10through the narrowed n type channel region20and then through the p type base region12, without entering the p type base region12of the IGBT along the interface of the p type base region12and the first semiconductor region25. Accordingly, holes formation is suppressed, as is hole injection from the p type base region12into the first semiconductor region25, and the increase in speed of the FWD can be realized.

First Modification Example of the First Embodiment

A first modification example of the first embodiment is illustrated inFIGS. 6A and 6B.FIG. 6Ais a schematic cross-sectional view of the semiconductor deviceFIG. 6Btaken along line B-B′ illustrating a semiconductor device according to the first modification example of the first embodiment.FIG. 6Bis a schematic plan view of the semiconductor device ofFIG. 6A. A difference as compared with the first embodiment is that in the p base regions12, as it comes closer to the p+ type contact region9, the corner of at least one or more of the p base regions12take the form of a gradual curve. This can be easily formed by diffusion of impurities in the horizontal direction where the p base region12is formed by a diffusion method. With this structure, it is possible to reduce the p layer impurity concentration in the narrowed n type channel region20side of the p base region12without exerting any influence on a channel region of the IGBT, and holes can be suppressed from being injected from the p type base region12of the IGBT at the time of the operation of the FWD. Because of this, the increase in the switching speed of the diode is possible.

Second Modification Example of the First Embodiment

A second modification example of the first embodiment is illustrated inFIGS. 7A and 7B.FIG. 7Ais a schematic cross-sectional diagram taken along line C-C′ ofFIG. 7Billustrating a semiconductor device according to the second modification example of the first embodiment.FIG. 7Bis a schematic plan view of the semiconductor device ofFIG. 7A. A difference from the first modification example is that the p+ type contact region9is covered with a gradually curved portion of the p type base region12. The n type channel region20is not formed by lowering an impurity concentration of the p type base region12. In the same manner as in the first embodiment of the present disclosure, because the holes can be suppressed from being injected the lower portion of the p type base region12of the IGBT, the increase in the switching speed of the diode is possible.

Second Embodiment

Next, a second embodiment is described.FIG. 8Ais a schematic cross-sectional diagram illustrating a semiconductor device according to the second embodiment taken along line D-D′ ofFIG. 8B.FIG. 8Bis a schematic plan diagram of the semiconductor device ofFIG. 8A.

A semiconductor device2according to the second embodiment is a semiconductor device that has a vertical electrode structure. The semiconductor device2includes the emitter electrode10, the collector electrode19, the IGBT region101and the FWD region102. In the semiconductor device2, the IGBT region101as a transistor and the FWD region102as a backflow diode are directly connected to each other.

In the semiconductor device2, an n− type semiconductor region15and an n type semiconductor region16are provided between the emitter electrode10and the collector electrode19. The n type semiconductor region16is positioned between the collector electrode19and the n− type semiconductor region15. An impurity concentration of the semiconductor region16is higher than an impurity concentration of the semiconductor region15.

The semiconductor region15is positioned to be shared between the IGBT region101and the FWD region102. The semiconductor region15has a portion15athat is provided in the IGBT region101, and a portion15bthat is provided in the FWD region102.

The semiconductor region16is positioned to be shared between the IGBT region101and the FWD region102. The semiconductor region16has a portion16athat is provided in the IGBT region101, and a portion16bthat is provided in the FWD region102. In the embodiment, a combination of the semiconductor region15and the semiconductor region16that are of the same conductivity type is defined as the first semiconductor region25.

Therefore, a combination of the portion15aof the semiconductor region15and the portion16aof the semiconductor region16is defined as the first portion25aof the first semiconductor region25. A combination of the portion15bof the semiconductor region15and the portion16bof the semiconductor region16is defined as the second portion25bof the first semiconductor region25.

At this point, the IGBT region has a configuration as illustrated inFIG. 1.

In the FWD region102, the second portion25bof the first semiconductor region25is provided between the cathode electrode19and the anode electrode10. The n+ type cathode region18is provided between the second portion25bof the first semiconductor region25and the cathode electrode19. The n+ type cathode electrode18is in contact with the cathode electrode19. An impurity concentration of the cathode region16bis higher than an impurity concentration of the first semiconductor region25.

The p type anode region22is provided between the second portion25bof the first semiconductor region25and the anode electrode10. A portion of the anode region22is in contact with the anode electrode10. This portion of the anode region22is in Schottky contact with the anode electrode10or is in low resistance contact with the anode electrode10.

The p+ type anode region21is selectively provided between the anode electrode10and portions of the anode region22. The anode region21extends in the Z direction. A plurality of anode regions21are arranged in the Y direction. The anode region21is in contact with the anode electrode10. The anode region21is in ohmic contact with the anode electrode10. An impurity concentration of the anode region21is higher than an impurity concentration of the anode region22. It is noted that the anode region21may be removed from the semiconductor device1. For example, a structure that results from removing the anode region21in a structure that is illustrated inFIGS. 7A and 7Bfall within the scope of the embodiment.

Furthermore, in the FWD region102, the portion16bof the n type buffer region16may considered as an n type buffer region16b, the portion15bof the base region15as an intrinsic region15b, the anode electrode10as the cathode electrode19, and the cathode electrode19as the anode electrode10, in an exchanged manner.

Furthermore, in the FWD region102, the emitter potential electrode23that is in electrical contact with the anode electrode10is provided. The emitter potential electrode23is spaced from the second portion25bof the first semiconductor region25, the anode region22, and the anode region21by the insulating film24. The emitter potential electrode23extends from the anode electrode10side to the cathode electrode19side, and extends in the X direction. A plurality of emitter potential electrodes23are arranged in the Y direction.

In this manner, in the FWD region102, the PIN diode that includes the anode electrode, the anode region, the intrinsic region, the cathode region, and the cathode electrode is provided.

At this point, operations and effects according to the second embodiment are described with a focus on differences with those according to the first embodiment and the comparative example.

The difference from the first embodiment is that because the IGBT region and the FWD region are separated from each other, the FWD can be designed independently of the IGBT. Accordingly, the speed of the FWD can be further increased. In addition, the connection of a trench electrode of the FWD region to the cathode electrode can reduce the gate capacitance. Furthermore, in comparison with the comparative example, a carrier is suppressed from staying in the FWD region before and after the recovery operation, and because there is no need to form the region, an element area can be effectively utilized.

Modification Example of the Second Embodiment

A modification example of the second embodiment of the present disclosure is illustrated inFIGS. 9A and 9B.FIG. 9Ais a schematic cross-sectional diagram illustrating a semiconductor device according to the modification example of the second embodiment taken along line E-E′ ofFIG. 9B.FIG. 9Bis a schematic plan diagram of the semiconductor device ofFIG. 9A. A difference with the second embodiment is that as the p type base region12becomes closer to the p+ type contact region9, at least one or more of the p type base regions12take the form that results from drawing a gradual curve. Although the narrowed n type channel region20is not formed, an injection depth of the p type base region12is adjusted and thus holes can be suppressed from being injected from the p type base region of the IGBT in the same manner as in the second embodiment of the present disclosure. Because of this, the increase in the switching speed of the diode is possible.

It is noted that the FWD structure in the second embodiment is specifically described, but that the IGBT structure101according to the exemplary embodiment of the present disclosure, of course, can be integrated with other FWD structures and in such a case, can contribute to the increase in the speed of the FWD as well.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. Specific configuration of each of the elements included in the embodiments may be chosen from the art that is known to one skilled artisan. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.