Semiconductor device, circuit board, electronic apparatus, and method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes (a) forming electrical interconnections over a surface of a semiconductor substrate having integrated circuits, (b) providing a plurality of bonding pads disposed on the surface of the semiconductor substrate, (c) electrically connecting the electrical connections to respective bonding pads of the plurality of bonding pads, (d) electrically connecting the plurality of bonding pads to each of the integrated circuits, (e) forming resin layers so as to cover the electrical interconnections, (f) forming concave portions by a first process, each of the concave portions being disposed in a corresponding portion of the resin layers that cover the electrical interconnections, (g) curing the resin layers having the concave portion, (h) forming through-holes by removing bottoms of the concave portions by a second process that differs from the first process and (i) forming external connection terminals, each being disposed on a corresponding area of the electrical interconnections exposed through the through-holes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, a circuit board, and an electronic apparatus.

2. Description of the Related Art

A process for manufacturing a semiconductor device may include a step of forming resin layers, for example, solder resist layers, over electrical interconnections. Another step is forming apertures in the resin layers and a further step is forming external connection terminals, for example, solder balls on the respective electrical interconnections exposed through the apertures. Conventionally, the resin layers are cured between the step of forming the apertures in the resin layers and the step of forming the external connection terminals. This curing step causes the electrical interconnections exposed through the apertures to be passivated; for example, oxide films are formed. Consequently, an activation step, for example, a step of removing the oxide films is required.

Accordingly, an advantage of the present invention is to simplify the method by eliminating an activation step of the electrical interconnections.

SUMMARY OF THE INVENTION

A method for manufacturing a semiconductor device includes the steps of forming electrical interconnections over a surface of a semiconductor substrate, the electrical interconnections being electrically connected to respective bonding pads disposed on the surface of the semiconductor substrate including integrated circuits, a plurality of the bonding pads being electrically connected to each of the integrated circuits, forming resin layers so as to cover the electrical interconnections, forming concave portion by a first process, each of the concave portion being disposed in the corresponding portion of the resin layers that cover the respective electrical interconnections and curing the resin layers having the concave portion. The method also includes the steps of forming through-holes by removing the respective bottoms of the concave portion by a second process that differs from the first process and forming external connection terminals, each being disposed on the corresponding area of the electrical interconnections exposed through the through-holes. According to the present invention, in the step of curing the resin layers, the resin layers have the concave portion, but the electrical interconnections are not exposed; hence, passivation of the electrical interconnections can be blocked.

In this method for manufacturing a semiconductor device, the resin layers may be formed using a thermosetting resin precursor in the forming resin layers step and the thermosetting resin may be heated in the curing the resin layers step. Also, in this method for manufacturing a semiconductor device, the resin layers may be formed using a radiation-sensitive resin precursor in the forming resin layers step and the first process may involve a step of irradiating the resin precursor with radiation and a step of developing the irradiated resin precursor.

In this method for manufacturing a semiconductor device, the second process may be dry etching and each of the resin layers may be composed of solder resist.

A semiconductor device according to the present invention is manufactured by any one of methods described above A circuit board according to the present invention mounts the semiconductor device described above and an electronic apparatus according to the present invention includes the semiconductor device described above.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIGS. 1to5andFIGS. 13to16illustrate a method for manufacturing a semiconductor device according to a first embodiment of the present invention. In this embodiment, a semiconductor substrate10as shown inFIG. 1is used. The semiconductor substrate10includes a plurality of integrated circuits12. When the semiconductor substrate10is cut into a plurality of separated semiconductor chips, the separated semiconductor chips have the respective integrated circuits12.

A passivation layer14may be formed on a surface of the semiconductor substrate10. For example, the passivation layer14may be formed of an inorganic material such as silicon dioxide (SiO2) or silicon nitride (SiN). The passivation layer14may include a plurality of sublayers. In this case, at least one sublayer (for example, the uppermost sublayer) may be formed of an organic material. The bonding pads16are formed on the upper surface of the semiconductor substrate10. Bonding pads16are electrically connected to the integrated circuits12(for example, semiconductor integrated circuits). The passivation layer14is not disposed on at least the middle area of each of the bonding pads16.

Stress relieving layers18may be formed on the semiconductor substrate10. The stress relieving layers18may be formed on the semiconductor substrate10by applying or spin-coating a resin precursor, for example, a thermosetting resin precursor. Each of the stress relieving layers18may include a plurality of sublayers or a single layer. The stress relieving layers18are electrical insulators. The stress relieving layers18may be formed of, for example, a polyimide resin, a silicone-modified polyimide resin, an epoxy resin, a silicone-modified epoxy resin, a benzocyclobutene (BCB), or polybenzoxazole (PBO). The stress relieving layers18cannot contain electrically conductive particles. The stress relieving layers18may be formed of a light shielding material.

The stress relieving layers18may be formed of a radiation-sensitive resin precursor that is sensitive to radiation such as light (ultraviolet light and visible light), X-rays, and an electron beam. The radiation-sensitive resin precursor such as a photosensitive resin precursor includes a negative type in which a radiation exposed area of the resin precursor becomes insoluble and a positive type in which a radiation exposed area of the resin precursor has increased solubility.

The stress relieving layers18need not be disposed on the respective bonding pads16. The stress relieving layers18need not be disposed on areas for cutting the semiconductor substrate10. The stress relieving layers18may be formed by patterning after the resin precursor layer is continuously or integrally formed with the semiconductor substrate10. The stress relieving layers18may be formed on the respective areas (each of the areas having the corresponding integrated circuit12) on the semiconductor substrate10. Spaces are provided between adjacent stress relieving layers18.

Electrical interconnections20are formed on the respective stress relieving layers18. The electrical interconnections20may be formed of a single layer or multiple layers. For example, a titanium tungsten (TiW) layer and a copper (Cu) layer are laminated by sputtering, and then a Cu layer may be further formed on the laminated layers by plating. Known methods can be applied for forming the electrical interconnections20. Each of the electrical interconnections20extends over the corresponding bonding pads16, in other words, is electrically connected to the corresponding bonding pad16. Each of the electrical interconnections20extends over the corresponding bonding pad16and the corresponding stress relieving layer18. The electrical interconnections20may have respective lands which have a width greater than that of the electrical interconnections. The lands are areas to provide respective external connection terminals28.

Resin layers22are formed on the stress relieving layers18. In this embodiment, the resin layers22include both uncured (unpolymerized resin precursor) layers and cured (polymerized resin) layers. Each of the resin layers22is formed of a solder resist. The resin layers22cover, for example, the entity of the respective electrical interconnections20. The resin layers22may be formed so as to cover, for example, the entity of the respective stress relieving layers18. The resin layers22may be disposed so that areas for cutting the semiconductor substrate10are exposed, in other words, the resin layers22need not be disposed on areas for cutting the semiconductor substrate10. The resin layers22cannot contain electrically conductive particles. The resin layers22may be formed of a light shielding material. The resin layers22may be formed by patterning after a resin precursor layer is continuously or integrally formed with the semiconductor substrate10. The resin layers22may be formed on the respective areas (each of the plurality of areas having the corresponding integrated circuit12) on the semiconductor substrate10. Spaces are provided between adjacent resin layers22.

The resin layers22may be formed of a radiation-sensitive resin precursor that is sensitive to radiation, for example, light (ultraviolet light and visible light), X-rays, or an electron beam.

As shown inFIG. 2, concave portions23(first concave portions) are formed in the resin layers22. Each of the concave portions23is formed in a corresponding portion of the resin layers22overlapped with the respective electrical interconnections20, for example, lands. The concave portions23are formed by a first process. The first process may include lithography. For example, the resin layers22may be formed of a radiation-sensitive resin precursor and then by patterning (for example, developing) with radiation. The radiation-sensitive resin precursor such as a photosensitive resin precursor includes a negative type in which an area of the resin precursor exposed to radiation (for example, light) becomes insoluble and a positive type in which an area of the resin precursor exposed to radiation (for example, light) has increased solubility. Each of the concave portions23may have a width that decreases with the depth. The inner surfaces of the concave portions23need not have sharp edges. The concave portions23may have gently curved inner surfaces.

A first process for forming the concave portions23will now be described in detail. In examples shown inFIGS. 13 and 14, the concave portions23are formed by decreasing an irradiation dosage (for example, shortening of the irradiation time and/or decreasing the intensity of light) in an exposure step. As shown inFIG. 13, a mask50is disposed above the resin layers22, and then the resin layers22are irradiated with radiation60through the mask50. In this embodiment, a positive type radiation-sensitive resin precursor is used as an example. The mask50has a shielding area52blocking the radiation60and transparent areas54that transmit the radiation60. The mask50includes a glass-based material. Hence, the resin layers22may be irradiated with the radiation60through the glass-based material.

In this step, the irradiation dosage of the radiation60is less than that of the conventional case (for example, in the case of forming apertures that have walls perpendicular to the semiconductor substrate in the resin layers22). Thus, the radiation60cannot reach the bottoms, which are in contact with the electrical interconnections20, of the resin layers22. The radiation60is not only perpendicularly incident on the resin layers22but also obliquely incident. The radiation60is perpendicularly incident on the resin layers22corresponding to the pattern of the mask50(i.e., corresponding to the transparent areas54). The radiation60is deflected at boundaries of the shielding area52and the transparent areas54, whereby the deflected radiation60is obliquely incident on the resin layers22. Consequently, in the vicinities of portions located directly below the respective transparent area54, the radiation60that is incident on the resin layers22gradually decreases in intensity away from each of the centers of the portions located directly below the respective transparent areas54; hence, the depth of the radiation60that is incident on the resin layers also gradually decreases away from each of the centers of the portions located directly below the respective transparent areas54. In this way, concave shaped portions having increased solubility can be formed in the respective resin layers22by being irradiated with the radiation60. Subsequently, the concave portions having increased solubility in the resin layers22are dissolved and removed by developing, whereby the concave portions23can be formed as shown in FIG.14.

In a modification of the first process for forming the concave portions23shown inFIGS. 15 and 16, in a developing step, the concave portions23are formed by a decreased amount of dissolved resin layer by development (for example, by decreasing the developing time and/or decreasing the developer concentration). An exposure step is performed as shown in FIG.15. The description given in the above-mentioned embodiment (seeFIG. 13) is also applicable to this step. In this modification, the resin layers are sufficiently irradiated with the radiation60(for example, the degree to which the apertures having walls perpendicular to the semiconductor substrate in the resin layers22can be formed). Thus, the radiation60reaches the bottoms, which are in contact with the electrical interconnections20, of the resin layers22. The radiation60is incident on the portions of the resin layers22, each of the portions being located directly below the corresponding transparent area54. As shown inFIG. 15, the radiation60may be obliquely incident on the resin layers22, so that the radiation60is incident on the portions having a width greater than that of the corresponding transparent areas54. Subsequently, the portions having increased solubility in the resin layers22are dissolved by developing. In this modification, the amount of dissolved resin layers22by developing decreases; hence, as shown inFIG. 16, only part of each of the portions having increased solubility in the corresponding resin layers22can be removed. Developer penetrates into each of the resin layers22through the corresponding upper surface, which is opposite to the electrical interconnections20, of the resin layer22. The penetration depth gradually decreases away from each of the centers of the portions having increased solubility. In this way, as shown inFIG. 16, the concave portions23can be formed.

Furthermore, even when typical steps of exposing and developing are performed, resin residue often remains in the apertures. In this case, each of the apertures in the resin layers22cannot have a wall perpendicular to the semiconductor substrate in the corresponding resin layer22. The thickness of the resin residue increases away from each of the centers of the apertures. The concave portions23may be formed by the resin residue.

As shown inFIG. 3, the resin layers22are cured. The step of curing the resin layers22may cause the electrical interconnections20to be passivated. (For example, the oxide film is formed on the surface of the electrical interconnections20.) For example, when the resin layers22are formed of a thermosetting resin precursor, the thermosetting resin precursor is cured (polymerized) by heating. In this embodiment, when the resin layers22are cured, the resin layers22have the concave portions23, but the electrical interconnections20are not exposed; hence, the electrical interconnections20do not undergo passivation. Accordingly, the method can be simplified by eliminating an activation step of the electrical interconnections20.

As shown inFIG. 4, through-holes24are formed in the resin layers22. The through-holes24are formed after the resin layers22are cured. The through-holes24are formed by removing the bottoms of the concave portions23. The through-holes24are formed by a second process. The second process differs from the first process for forming the concave portions23. The second process may be, for example, dry etching.

The concave portions26(second concave portions) may be formed in the electrical interconnections20. Each of the concave portions26may be overlapped with the corresponding through-holes24. Each of the apertures of the concave portions26may be entirely included within the corresponding through-hole24. The concave portions26may be formed by, for example, dry etching. The process for forming the concave portions26may be the same as the process for forming the through-holes24. After the through-holes24are formed, the concave portions26may be subsequently formed. Each of the concave portions26may have a width that decreases with the depth. The inner surfaces of the concave portions26need not have sharp edges. The concave portions26may have gently curved inner surfaces.

As shown inFIG. 5, the external connection terminals28are formed. The external connection terminals28are formed on the respective areas of the electrical interconnections20exposed through the through-holes24(for example, the concave portions26). The external connection terminals28are bonded to the respective electrical interconnections20, for example, the concave portions26of the electrical interconnections20. The external connection terminals28may be in contact with the respective inner faces of the through-holes24in the resin layers22. The external connection terminals28may be composed of either soft solder or hard solder. Lead-free solder may be used for the soft solder. Lead-free solder such as tin-silver (Sn—Ag), tin-bismuth (Sn—Bi), tin-zinc (Sn—Zn), and tin-copper (Sn—Cu) based alloys may be used. These alloys may further contain at least one of silver, bismuth, zinc, and copper. A known method can be applied to form the external connection terminals28.

As shown inFIG. 5, second resin layers30may be formed on the respective resin layers22. The description of the stress relieving layers18given above may also be applied to the second resin layers30. Each of the second resin layers30is formed so as to surround the corresponding plurality of external connection terminals28. Each of the second resin layers30may cover a part (for example, the base portion) of the external connection terminals28. The second resin layers30may be formed so as to cover, for example, the entire respective resin layers22. The second resin layers30may be formed by patterning a solid resin layer that is formed so as to cover the entire semiconductor substrate10. Alternatively, the second resin layers30may be formed of a solid resin layer on the entity of the external connection terminals28and then by removing the solid resin layer at the top ends of the external connection terminals28. The description of the patterning for the stress relieving layers18given above is also applicable to the patterning for the second resin layers30. Alternatively, parts of the second resin layers30may be removed by laser irradiation or ashing.

A semiconductor wafer according to an embodiment of the present invention includes the semiconductor substrate10. The semiconductor substrate10includes a plurality of the integrated circuits12(seeFIG. 1) and bonding pads16on a surface of the semiconductor substrate. Each of the bonding pads16is electrically connected to the corresponding integrated circuit12. The electrical interconnections20are electrically connected to the respective bonding pads16. The resin layers22are formed on the electrical interconnections20. The external connection terminals28are formed on the respective electrical interconnections20. The second resin layers30may surround the external connection terminals28.

The resin layers22have through-holes24. The electrical interconnections20may have respective concave portions26. Each of the concave portions26may be overlapped with corresponding through-hole24. Each of the apertures of the concave portions26may be entirely included within the corresponding through-hole24. The external connection terminals28may be in contact with the respective inner faces of the through-holes24in the resin layers22.

In this embodiment, the external connection terminals28are bonded to the respective concave portions26, whereby the bonding strength between the electrical interconnections20and the external connection terminals28can be improved by the concave portions26. Furthermore, contact areas between the electrical interconnections20and the external connection terminals28increase by forming the concave portions26; hence, the electrical connection performance between the electrical interconnections20and the external connection terminals28is improved. Other details are the same as described above.

As shown inFIG. 5, the semiconductor substrate10is cut by, for example, scribing or dicing with, for example, a cutter (or blade)32. In this way, semiconductor devices can be obtained.

FIGS. 6 and 7illustrate a semiconductor device according to this embodiment.FIG. 6is a cross-sectional view taken along the line VI—VI in FIG.7. The semiconductor device has a semiconductor chip40. The semiconductor chip40may be cut from the semiconductor substrate10. Other details of the semiconductor device are the same as the descriptions of the semiconductor wafer.

Second Embodiment

FIG. 8illustrates a method for manufacturing a semiconductor device according to a second embodiment of the present invention. In this embodiment, concave portions36that are formed in the respective electrical interconnections20have a different shape from the concave portions26in the first embodiment. Each of the concave portions36includes a portion having a width greater than that of the corresponding aperture at the bottom thereof Each of the concave portions36has first and second widths at first and second positions, respectively, with the first width having a width greater than that of an aperture of the same concave hole at the first position and the second width having a width less than that of an aperture of the same concave hole at the second position. The first position is located at a position above that of the second position. The concave portions36having this shape are formed by isotropic-etching of the respective electrical interconnections20. For example, each of the through-holes24is formed in the corresponding resin layer22, and then the concave portions36may be formed by wet etching. Other details are the same as the descriptions of the first embodiment.

FIG. 9illustrates a semiconductor device according to the second embodiment of the present invention. The semiconductor device may be manufactured with a semiconductor wafer shown in FIG.8. In this embodiment, external connection terminals38are bonded to the respective concave portions36formed in the electrical interconnections20. Accordingly, the bonding strength between the electrical interconnections20and external connection terminals38is improved with the concave portions36. Furthermore, contact areas between the electrical interconnections20and the external connection terminals38increase by forming the concave portions36; hence, the electrical connection performance between the electrical interconnections20and external connection terminals38is improved. Other details are the same as the descriptions of the first embodiment.

FIG. 10illustrates a circuit board1000on which the semiconductor device1described in the above-mentioned embodiment is mounted.FIGS. 11 and 12illustrate a notebook personal computer2000and a cellular phone3000as electronic apparatuses including this semiconductor device.

The present invention is not limited to above-mentioned embodiments and can include a variety of modifications. For example, the present invention includes a structure which is substantially equivalent to the structure described in the embodiments. The substantially equivalent structure is, for example, a structure that has the same function, method, and result, or the same advantage and result. Further, the present invention includes a structure in which an extrinsic part of the structure described in the embodiments is replaced. Furthermore, the present invention includes a structure that has the same effect or can achieve the same advantage as the structure described in the embodiments. In addition, the present invention includes a structure according to one of the above embodiments in combination with known art.