Semiconductor device and electronics device

A plurality of switch circuits are disposed so as to correspond to a plurality of circuit blocks, respectively. Each of the plurality of switch circuits is connected between a power supply terminal of a corresponding circuit block and a power supply line. A setting circuit is disposed to set each of the plurality of switch circuits to be in a valid or invalid state. A switch control circuit turns on each of the plurality of switch circuits according to a first control signal for indicating an operation state of the plurality of circuit blocks when each of the plurality of switch circuits is set in a valid state by the setting circuit and turns on each of the plurality of switch circuits regardless of the first control signal when each of the plurality of switch circuits is set in an invalid state by the setting circuit.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2006-040379, filed on Feb. 17, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor device and an electronics device composed of the same.

2. Description of the Related Art

In recent years, portable electronics devices (a mobile phone, etc.) driven with a battery have been popular. There has been a strong demand for semiconductor devices mounted in the portable electronics devices to operate at a high-speed with low power consumption in order to realize advanced functions of the electronics devices and a long-term use of a battery.

Furthermore, along with the miniaturization of the structure of semiconductor devices, a power supply voltage applied to the semiconductor devices has been lowered. A small difference between the power supply voltage and a threshold voltage of the transistor due to low power supply voltage makes it difficult for the transistor to turn on, thereby decreasing the operating speed of the semiconductor device. To realize the high-speed operation of the semiconductor device with a low power supply voltage, it is necessary to set low the threshold voltage of the transistor. However, sub-threshold leakage current (off-state leakage current) of the transistor during an off state increases as the threshold voltage of the transistor lowers or an operation temperature rises. As a result, at a low set threshold voltage of the transistor, the high-speed operation of the semiconductor device is achievable, however, power consumption in the standby period of the semiconductor device increases.

In a semiconductor device including a plurality of circuit blocks, for example, a threshold voltage of the transistor within the circuit block is set low in order to realize the high-speed operation, and a switch transistor (a leakage cut-off transistor) is disposed between the power supply terminal of the circuit block and the power supply line to turn on in the active period and turn off in the standby period, in order to achieve low power consumption by reducing off-state leakage current of the transistor in the standby period.

Also, WO00/11486 discloses a technique to easily, accurately detect whether there is leakage current larger than a predetermined value in a semiconductor device.

The semiconductor device with the function of curtailing off-state leakage current (a leakage cut-off function) using the leakage cut-off transistor includes a test mode (the leakage cut-off function is invalid) in which the leakage cut-off transistor is constantly turned on regardless of an operation state of the semiconductor device, in addition to a normal mode (the leakage cut-off function is valid) in which the leakage cut-off transistor is turned on according to an operation state of the semiconductor device.

In a test process of the semiconductor device as described above, a function test is performed in the normal mode. When a result of the test is a fail, the function test is performed again in the test mode. It is possible to determine whether defects have occurred due to the leakage cut-off function based on the result of the test, pass/fail, in the test mode. It is, however, not possible to find details of the defects such as to identify a circuit block having the defects due to the leakage cut-off function from a plurality of circuit blocks. Because of this, defect analysis cannot be efficiently performed, consuming an enormous amount of time.

SUMMARY OF THE INVENTION

It is an object of the invention to efficiently analyze defects due to the leakage cut-off function in a short period of time.

According to an aspect of the invention, a semiconductor device mounted in an electronics device includes a plurality of circuit blocks, a plurality of switch circuits, a setting circuit and a switch control circuit. The plurality of switch circuits are disposed so as to correspond to the plurality of circuit blocks, respectively. Each of the plurality of switch circuits is connected between a power supply terminal of a corresponding circuit block and a power supply line. The setting circuit is disposed to set each of the plurality of switch circuits to be in a valid or invalid state. When each of the switch circuits is set in the valid state by the setting circuit, the switch control circuit turns on each switch circuit in accordance with a first control signal, and when each of the switch circuits is set in the invalid state by the setting circuit, turns on each switch circuit regardless of the first control signal. The first control signal indicates an operation state (an active state or a standby state) of the plurality of circuit blocks.

Accordingly, being set to be valid by the setting circuit, each of the switch circuits turns on in the active period of the plurality of circuit blocks (the active period of the semiconductor device) and turns off in the standby period of the plurality of circuit blocks (the standby period of the semiconductor device). Therefore, for example, when all of the switch circuits are set to ‘valid’ by the setting circuit, it is possible to reduce off-state leakage current of all the circuit blocks in the standby period of the semiconductor device. This accordingly makes both of high-speed operation and low power consumption of the semiconductor device feasible at the same time, even when a threshold voltage of a transistor in each circuit block is set low in order to realize the high-speed operation.

In the test process of such a semiconductor device, the function test is performed in a state that all of the switch circuits are set to ‘valid’ by the setting circuit. When the result of the function test is a fail, the function test is sequentially performed while the state (valid or invalid) of each switch circuit is changed by the setting circuit. Based on the results of the function tests, pass/fail, and on the state of each switch circuit, it is possible to find where a defect occurs due to the leakage cut-off function. Therefore, defect analysis can be performed efficiently in a short period of time.

In a preferable example of one aspect of the invention, the setting circuit includes a test mode circuit. In a normal mode the test mode circuit inactivates a plurality of test mode signals corresponding to the plurality of switch circuits respectively. In a test mode the test mode circuit activates one of the plurality of test mode signals designated by test mode information. The switch control circuit turns on each of the plurality of switch circuits in accordance with the first control signal when a corresponding test mode signal is inactivated, and turns on each of the plurality of switch circuits regardless of the first control signal when the corresponding test mode signal is activated.

In the test process of such a semiconductor device, the function test is performed in the normal mode. When the result of the function test is a fail, the function test is sequentially performed while the state (active or inactive) of each test mode signal is changed according to the test mode information. Based on the results of the function tests, pass/fail, and on the state of each test mode signal, it is possible to find which one of the plurality of circuit blocks has a defect due to the leakage cut-off function.

In a preferable example of the aspect of the invention, the setting circuit includes a plurality of storage circuits. The plurality of storage circuits are disposed so as to correspond to the plurality of switch circuits, respectively. Each of the plurality of storage circuits stores validity or invalidity of a corresponding switch circuit and activates a storage state signal when storing the invalidity. For example, each of the plurality of storage circuits may include a fuse circuit programming validity or invalidity of the corresponding switch circuit. The switch control circuit turns on each of the plurality of switch circuits in accordance with the first control signal when a corresponding storage state signal is inactivated and turns on each of the plurality of switch circuits regardless of the first control signal when the corresponding storage state signal is activated.

In the test process of such a semiconductor device, the function test is performed in a state that all of the storage circuits store validity. When the result of the function test is a fail, the function test is sequentially performed while the number of the storage circuits storing the invalidity is increased. Based on the results of the function tests, pass or fail, and on the state (that validity or invalidity is stored) of each storage circuit, it is possible to find which one of the plurality of circuit blocks has a defect due to the leakage cut-off function.

In a preferred example of the aspect of the invention, the setting circuit includes a test mode circuit, a plurality of storage circuits and a uniting circuit. In the normal mode the test mode circuit inactivates a plurality of test mode signals corresponding to the plurality of switch circuits, respectively. In a test mode the test mode circuit activates one of the plurality of test mode signals designated by the test mode information. The plurality of storage circuits are disposed so as to correspond to the plurality of switch circuits respectively, store validity or invalidity of a corresponding switch circuit, and activates a storage state signal when storing the invalidity. For example, each of the plurality of storage circuits may include a fuse circuit programming validity or invalidity of the corresponding switch circuit. The uniting circuit activates each of a plurality of second control signals corresponding to the plurality of switch circuits respectively when one of a corresponding test mode signal and a corresponding storage state signal is activated. The switch control circuit turns on each of the plurality of switch circuits in accordance with the first control signal when a corresponding second control signal is inactivated, and turns on each of the plurality of switch circuits regardless of the first control signal when the corresponding second control signal is activated.

In the test process of such a semiconductor device, the function test is performed in the normal mode in a state that all of the storage circuits store validity. When the result of the function test is a fail, the function test is sequentially performed in the test mode while the state of each test mode signal is changed according to test mode information. Based on the results of the function tests, pass/fail, and on the state of each test mode signal, it is possible to find which one of the plurality of circuit blocks has a defect due to the leakage cut-off function.

Furthermore, once the invalidity is stored in a storage circuit corresponding to a circuit block having a defect, the result of the function test of the circuit block in the normal mode will be “pass”. However, in the circuit block, the off-state leakage current is not reduced, thereby slightly increasing power consumption of the semiconductor device in the standby period. However, if the power consumption increase is not a big problem for a user of the semiconductor device, the semiconductor device can be provided as a good product without waiting for correcting the defect.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the invention will be described with reference to the accompanying drawings.FIG. 1shows a first embodiment of the invention.FIGS. 2(a) to2(d) show an electronics device in which a semiconductor device ofFIG. 1is mounted. The semiconductor device SD10according to the first embodiment may be mounted in an electronics device having a function block construction as shown inFIGS. 2(a) to2(d). The semiconductor device SD10may implement at least one of the function blocks (a memory, a processor, or a memory controller). Furthermore, the electronics devices may be constructed by using any one of MCP (Multi Chip Package), SiP (System in Package) and SoC (System on Chip) techniques.

The semiconductor device SD10includes a control signal generating circuit CGCT, a test mode signal generating circuit TGC (a test mode circuit), leakage cut-off control circuits LCC0to LCC3(a switch control circuit), circuit blocks BLK0to BLK3and leakage cut-off transistors LTP0to LTP3and LTN0to LTN3(switch circuits).

When the control signal generating circuit CGCT analyzes a command signal CMD received through a command terminal CMD and detects a test mode entry command, the control signal generating circuit CGCT temporarily activates a test mode entry signal ENTRY to ‘1’. When the control signal generating circuit CGCT analyzes the command signal CMD and detects a test mode exit command, the control signal generating circuit CGCT temporarily activates a test mode exit signal /EXIT to ‘0’. The control signal generating circuit CGCT also temporarily activates a start signal /START to ‘0’ when the semiconductor device SD10is powered.

The test mode signal generating circuit TGC outputs test mode signals T0to T3on the basis of the test mode entry signal ENTRY, the test mode exit signal /EXIT, the start signal /START, and address signals TA0and TA1(test mode information) for identifying a test mode of the command signal CMD. When the operation mode of the semiconductor device SD10is a normal mode, all of the test mode signals T0to T3are inactivated to ‘0’. When the operation mode of the semiconductor device SD10is a test mode, at least one of the test mode signals T0to T3is activated to ‘1’.

The leakage cut-off control circuit LCCi (i=0, 1, 2, 3) has inverters I00and I01and a NAND gate G00. The inverter I00inverts the test mode signal Ti and outputs the inverted signal. The NAND gate G00performs a NAND operation for a leakage cut-off control signal POFF (first control signal) and an output signal of the inverter I00and outputs the result as a leakage cut-off control signal /OFFi. The inverter I01inverts the leakage cut-off control signal /OFFi (output signal of the NAND gate G00) and outputs the inverted signal as a leakage cut-off control signal OFFi. Furthermore, the leakage cut-off control signal POFF is activated to ‘1’ in the standby period of the semiconductor device SD10(standby period of the circuit blocks BLK0to BLK3) and is inactivated to ‘0’ in the active period of the semiconductor device SD10(active period of the circuit blocks BLK0to BLK3).

Therefore, if the test mode signal Ti is inactivated to ‘0’, the leakage cut-off control signals OFFi and /OFFi are activated to ‘1’ and ‘0’, respectively, in the standby period of the semiconductor device SD10and are inactivated to ‘0’ and ‘1’, respectively, in the active period of the semiconductor device SD10. Meanwhile, if the test mode signal Ti is activated to ‘1’, the leakage cut-off control signals OFFi and /OFFi are respectively inactivated to ‘0’ and ‘1’ regardless of the operation state of the semiconductor device SD10(operation state of the circuit blocks BLK0to BLK3).

The circuit block BLKi outputs an internal signal /SIGi+1 on the basis of an internal signal /SIGi. The internal signal /SIG0is temporarily activated to ‘0’ only in the active period of the semiconductor device SD10at a desired timing. The leakage cut-off transistor LTPi includes a PMOS transistor and is connected between a power supply terminal PHi of the circuit block BLKi and a power supply line VDD. A leakage cut-off transistor LTNi includes an nMOS transistor and is connected between a power supply terminal PLi of the circuit block BLKi and a ground line VSS. The leakage cut-off transistor LTPi has a gate to which the leakage cut-off control signal OFFi is applied. The leakage cut-off transistor LTNi has a gate to which the leakage cut-off control signal and /OFFi is applied.

Therefore, if the test mode signal Ti is inactivated to ‘0’, the leakage cut-off transistors LTPi and LTNi are turned on in the active period of the semiconductor device SD10and are turned off in the standby period of the semiconductor device SD10. Meanwhile, if the test mode signal Ti is activated to ‘1’, the leakage cut-off transistors LTPi and LTNi are always turned on regardless of the operation state of the semiconductor device SD10. In other words, the leakage cut-off transistors LTPi and LTNi are set to ‘valid’ when the test mode signal Ti is inactivated to ‘0’ and is set to ‘invalid’ when the test mode signal Ti is activated to ‘1’.

FIG. 3shows a circuit block inFIG. 1. The circuit block BLki includes pMOS transistors TP10to TP13and nMOS transistors TN10to TN13. The pMOS transistor TP10has a source connected to the power supply terminal PHi. In other words, the source of the pMOS transistor TP10is connected to the power supply line VDD through the leakage cut-off transistor LTPi. A drain of the pMOS transistor TP10is connected to a drain of the nMOS transistor TN10. The nMOS transistor TN10has a source connected to the ground line VSS. Gates of the pMOS transistor TP10and the nMOS transistor TN10are applied with the internal signal /SIGi.

The PMOS transistor TP11has a source connected to the power supply line VDD. A drain of the pMOS transistor TP11is connected to a drain of the nMOS transistor TN11. The nMOS transistor TN11has a source connected to the power supply terminal PLi. In other words, the source of the nMOS transistor TN11is connected to the ground line VSS through the leakage cut-off transistor LTNi. Gates of the pMOS transistor TP11and the nMOS transistor TN11are applied with a signal generated in the connection node of the pMOS transistor TP10and the nMOS transistor TN10.

The pMOS transistor TP12has a source connected to the power supply terminal PHi. In other words, the source of the pMOS transistor TP12is connected to the power supply line VDD through the leakage cut-off transistor LTPi. A drain of the pMOS transistor TP12is connected to a drain of the nMOS transistor TN12. The nMOS transistor TN12has a source connected to the ground line VSS. Gates of the pMOS transistor TP12and the nMOS transistor TN12are applied with a signal generated in the connection node of the pMOS transistor TP11and the nMOS transistor TN11.

The pMOS transistor TP13has a source connected to the power supply line VDD. A drain of the pMOS transistor TP13is connected to a drain of the nMOS transistor TN13. The nMOS transistor TN13has a source connected to the power supply terminal PLi. In other words, the source of the nMOS transistor TN13is connected to the ground line VSS through the leakage cut-off transistor LTNi. Gates of the PMOS transistor TP13and the nMOS transistor TN13are applied with a signal generated in the connection node of the pMOS transistor TP12and the nMOS transistor TN12. A signal generated in the connection node of the pMOS transistor TP13and the nMOS transistor TN13is output as the internal signal /SIGi+1. As described above, the circuit block BLki includes the four inverters connected in series.

Furthermore, to realize the high speed operation of the circuit block BLki, threshold voltages of the pMOS transistors TP10and TP12, which are turned on when the internal signal /SIGi is activated, may be set lower than those of the pMOS transistors TP11and TP13, which are turned off when the internal signal /SIGi is activated. Similarly, threshold voltages of the nMOS transistors TN11and TN13, which are turned on when the internal signal /SIGi is activated, may be set lower than those of the nMOS transistors TN10and TN12, which are turned off when the internal signal /SIGi is activated.

In the standby period of the semiconductor device SD10, since the internal signal /SIG0is inactivated to ‘1’, the internal signals /SIG1to /SIG4are also inactivated to ‘1’. Accordingly, in the standby period of the semiconductor device SD10, the pMOS transistors TP10and TP12and the nMOS transistors TN11and TN13in which the threshold voltages are set low are turned off. Furthermore, sources of the PMOS transistors TP10and TP12are connected to the power supply line VDD through the leakage cut-off transistor LTPi. Sources of the nMOS transistors TN11and TN13are connected to the ground line VSS through the leakage cut-off transistor LTNi. When the operation mode of the semiconductor device SD10is the normal mode, the leakage cut-off transistors LTPi and LTNi are turned off in the standby period of the semiconductor device SD10. As a result, in the standby period of the semiconductor device SD10, off-state leakage current occurring in the circuit blocks BLK0to BLK3can be significantly reduced. Consequently, it is possible to prevent the power consumption of the semiconductor device SD10from being increased when the threshold voltages of the pMOS transistors TP10and TP12and the threshold voltages of the nMOS transistors TN11and TN13are set low. Therefore, both the high-speed operation and low power consumption of the semiconductor device SD10can be realized. Furthermore, in the present embodiment, it has been described that the circuit blocks BLK0to BLK3have the same internal construction. However, the circuit blocks BLK0to BLK3may have different internal constructions.

FIG. 4shows a test mode signal generating circuit inFIG. 1. The test mode signal generating circuit TGC includes input circuits IC0and IC1, a decode circuit DEC, and output circuits OC0to OC3. The input circuit IC0(IC1) has a transfer gate TG and inverters I20to I23. The transfer gate TG includes a PMOS transistor and an nMOS transistor, which are connected in parallel. A gate of the PMOS transistor of the transfer gate TG is applied with the test mode entry signal ENTRY through the inverter I20. A gate of the nMOS transistor of the transfer gate TG is applied with the test mode entry signal ENTRY. Therefore, the transfer gate TG is turned on when the test mode entry signal ENTRY is activated, and supplies an address signal TA0(TA1), which is received through one end, to the other end. The transfer gate TG is turned off when the test mode entry signal ENTRY is inactivated and stops to supply the address signal TA0(TA1) to the other end. The inverters I21and I22are connected in a ring form so as to form a latch circuit. A connection node of an input terminal of the inverter I21and an output terminal of the inverter I22is connected to the other end of the transfer gate TG. The inverter I23inverts the output signal of the inverter I21and outputs the inverted signal.

In the input circuit IC0(IC1) constructed as described above, if the command signal CMD for indicating the test mode entry command is input to the control signal generating circuit CGCT and the test mode entry signal ENTRY supplied from the control signal generating circuit CGCT is activated, the transfer gate TG is turned on and the address signal TA0(TA1) is supplied to the latch circuit including the inverters I21and I22. Therefore, the output signal of the inverter I23is set to the same logic level as that of the address signal TA0(TA1) of the command signal CMD for indicating the test mode entry command.

The decode circuit DEC includes inverters I30to I35and NAND gates G30to G33. The inverter I30inverts the output signal (the output signal of the inverter I23of the input circuit IC0) of the input circuit IC0and outputs the inverted signal. The inverter I31inverts the output signal (the output signal of the inverter I23of the input circuit IC1) of the input circuit IC1and outputs the inverted signal. The NAND gate G30performs an NAND operation for the output signal of the inverter I30and the output signal of the inverter I31and outputs the operation result. The NAND gate G31performs an NAND operation for the output signal of the input circuit IC0and the output signal of the inverter I31and outputs the operation result. The NAND gate G32performs an NAND operation for the output signal of the inverter I30and the output signal of the input circuit IC1and outputs the operation result. The NAND gate G33performs an NAND operation for the output signal of the input circuit IC0and the output signal of the input circuit IC1and outputs the operation result. The inverter I32inverts the output signal of the NAND gate G30and outputs the inverted signal as the test mode signal PT0. The inverter I33inverts the output signal of the NAND gate G31and outputs the inverted signal as the test mode signal PT1. The inverter I34inverts the output signal of the NAND gate G32and outputs the inverted signal as the test mode signal PT2. The inverter I35inverts the output signal of the NAND gate G33and outputs the inverted signal as the test mode signal PT3.

Through such a circuit construction, the test mode signal PT0is activated to ‘1’ when the output signal of the input circuit IC0is set to ‘0’ and the output signal of the input circuit IC1is set to ‘0’. The test mode signal PT1is activated to ‘1’ when the output signal of the input circuit IC0is set to ‘0’ and the output signal of the input circuit IC1is set to ‘1’. The test mode signal PT2is activated to ‘1’ when the output signal of the input circuit IC0is set to ‘1’ and the output signal of the input circuit IC1is set to ‘0’. The test mode signal PT3is activated to ‘1’ when the output signal of the input circuit IC0is set to ‘1’ and the output signal of the input circuit IC1is set to ‘1’.

A delay circuit DLY delays the test mode entry signal ENTRY by a predetermined time and outputs the delayed signal as a test mode entry signal ENTRYD. The predetermined time may be set such that the test mode entry signal ENTRYD is activated after any one of the test mode signals PT0to PT3is activated when the test mode entry signal ENTRY is activated.

The output circuit OCi includes NAND gates G40to G42and inverters I40and I41. The NAND gate G40performs an NAND operation for the test mode signal PTi and the test mode entry signal ENTRYD and outputs the operation result. The NAND gate G41performs an NAND operation for the output signal of the NAND gate G40and an output signal of the NAND gate G42and outputs the operation result. The NAND gate G42performs an NAND operation for the output signal of the NAND gate G41, the test mode exit signal /EXIT and the start signal /START and outputs the operation result. The inverter I40inverts the output signal of the NAND gate G41and outputs the inverted signal. The inverter I41inverts the output signal of the inverter I40and outputs the inverted signal as the test mode signal Ti.

FIG. 5illustrates an operation of a test mode signal generating circuit inFIG. 4. If the semiconductor device SD10is powered, the power supply voltage VDD rises ((a) ofFIG. 5). When the start signal /START supplied from the control signal generating circuit CGCT is activated to ‘0’ ((b) ofFIG. 5), the test mode signal Ti supplied from the output circuit OCi of the test mode signal generating circuit TGC is inactivated to ‘0’ ((c) ofFIG. 5).

Thereafter, if the command signal CMD for indicating the test mode entry command (the address signals TA0and TA1indicate a decimal ‘i’) is input to the control signal generating circuit CGCT and the test mode entry signal ENTRY supplied from the control signal generating circuit CGCT is activated to ‘1’ ((d) ofFIG. 5), the test mode signal PTi supplied from the decode circuit DEC of the test mode signal generating circuit TGC is activated to ‘1’ ((e) ofFIG. 5). Furthermore, if the test mode entry signal ENTRYD supplied from the delay circuit DLY is activated to ‘1’ after a predetermined time elapses from the activation of the test mode entry signal ENTRY ((f) ofFIG. 5), the test mode signal Ti is activated to ‘1’ ((g) ofFIG. 5). Thereafter, if the command signal CMD for indicating the test mode exit command is input to the control signal generating circuit CGCT and the test mode exit signal /EXIT supplied from the control signal generating circuit CGCT is activated to ‘0’ ((h) ofFIG. 5), the test mode signal Ti is inactivated to ‘0’ ((i) ofFIG. 5).

FIG. 6illustrates an operation example (without defect) during a normal mode in a semiconductor device ofFIG. 1. In this operation example, the operation mode of the semiconductor device SD10is the normal mode and the test mode signals T0to T3supplied from the test mode signal generating circuit TGC are respectively inactivated to ‘0’. In other words, all of the leakage cut-off transistors LTP0to LTP3and LTN0to LTN3are set to ‘valid’.

In this state, if the semiconductor device SD10shifts from the standby state to the active state, the leakage cut-off control signal POFF is inactivated to ‘0’ ((a) ofFIG. 6). The leakage cut-off control signals /OFF0to /OFF3supplied from the leakage cut-off control circuits LCC0to LCC3are respectively inactivated to ‘1’ in response to the inactivation of the leakage cut-off control signal POFF ((b) ofFIG. 6). The leakage cut-off control signals OFF0to OFF3supplied from the leakage cut-off control circuits LCC0to LCC3are respectively inactivated to ‘0’ in response to the inactivation of the leakage cut-off control signals /OFF0to /OFF3((c) ofFIG. 6). Since the leakage cut-off transistors LTP0to LTP3and LTN0to LTN3are turned on, each of voltages of nodes NL0to NL3within the circuit blocks BLK0to BLK3is set to the ground voltage VSS ((d) ofFIG. 6) and each of voltages of nodes NH0to NH3within the circuit blocks BLK0to BLK3is set to the power supply voltage VDD ((e) ofFIG. 6). In addition, if the internal signal /SIG0is activated to ‘0’ ((f) ofFIG. 6), the internal signals /SIG1, /SIG2, /SIG3and /SIG4are sequentially activated to ‘0’ ((g), (h), (i) and (j) ofFIG. 6).

Meanwhile, if the semiconductor device SD10shifts from the active state to the standby state, the leakage cut-off control signal POFF is activated to ‘1’ ((k) ofFIG. 6). The leakage cut-off control signals /OFF0to /OFF3are respectively activated to ‘0’ in response to the activation of the leakage cut-off control signal POFF ((l) ofFIG. 6). The leakage cut-off control signals OFF0to OFF3are respectively activated to ‘1’ in response to the activation of the leakage cut-off control signals /OFF0to /OFF3((m) ofFIG. 6). Since the leakage cut-off transistors LTP0to LTP3and LTN0to LTN3are turned off, voltages of the nodes NL0to NL3and voltages of the nodes NH0to NH3become undefined ((n) and (o) ofFIG. 6). If the semiconductor device SD10operates as in the operation example ofFIG. 6in the normal mode, the result of the function test during the normal mode in the test process is a pass. Accordingly, the semiconductor device SD10is determined to be a good product.

FIG. 7illustrates an operation example (with defect) during a normal mode in a semiconductor device ofFIG. 1. In this operation example, the activation timing of the leakage cut-off control signal POFF is earlier than that of the operation example ofFIG. 6(a dotted line in the drawing) ((a) ofFIG. 7). Therefore, the activation timings of the leakage cut-off control signals /OFF0to /OFF3and OFF0to OFF3are earlier than those of the operation example ofFIG. 6((b) and (c) ofFIG. 7). Due to this, off timings of the leakage cut-off transistors LTP0to LTP3and LTN0to LTN3come earlier and voltages of the nodes NL0to NL3and the nodes NH0to NH3go unstable immediately after the internal signal /SIG3is inactivated ((d) and (e) ofFIG. 7). Consequently, the internal signal /SIG4is not activated ((f) ofFIG. 7). If the semiconductor device SD10operates as in the operation example ofFIG. 7during the normal mode, the result of the function test during the normal mode in the test process will be a fail. Accordingly, the semiconductor device SD10is determined to be a defective product.

In the test process of the semiconductor device SD10, if the result of the function test during the normal mode is a fail, defect analysis of the semiconductor device SD10can be performed as follows. First, the command signal CMD for indicating the test mode entry command is input four times while sequentially setting the address signals TA[1:0] (the address signals TA1and TA0) to ‘00’, ‘01’, ‘10’ and ‘11’, respectively, thereby activating all of the test mode signals T0to T3to ‘1’. As a result, all of the leakage cut-off transistors LTP0to LTP3and LTN0to LTN3are set to ‘invalid’. When the result of the function test is a pass in this state, it is determined that defects have occurred due to the leakage cut-off function. When it is determined that defects have occurred due to the leakage cut-off function, all of the test mode signals T0to T3are inactivated to ‘0’ by inputting the command signal CMD for indicating the test mode exit command. Accordingly, all of the leakage cut-off transistors LTP0to LTP3and LTN0to LTN3are set to ‘valid’.

Next, in a state where the address signal TA[1:0] is set to ‘00’, the test mode signal T0is activated to ‘1’ by inputting the command signal CMD for indicating the test mode entry command. As a result, only the leakage cut-off transistors LTP0and LTN0are set to ‘invalid’. In this state, if the result of the function test is a pass, it is determined that defects have occurred in the circuit block BLK0due to the leakage cut-off function. Meanwhile, if the result of the function test is a fail, the test mode signal T0is inactivated to ‘0’ by inputting the command signal CMD for indicating the test mode exit command. Accordingly, the leakage cut-off transistors LTP0and LTN0are set to ‘valid’ again.

Next, in a state where the address signal TA[1:0] is set to ‘01’, the test mode signal T1is activated to ‘1’ by inputting the command signal CMD for indicating the test mode entry command. As a result, only the leakage cut-off transistors LTP1and LTN1are set to ‘invalid’. In this state, if the result of the function test is a pass, it is determined that defects have occurred in the circuit block BLK1due to the leakage cut-off function. Meanwhile, if the result of the function test is a fail, the test mode signal T1is inactivated to ‘0’ by inputting the command signal CMD for indicating the test mode exit command. Accordingly, the leakage cut-off transistors LTP1and LTN1are set to ‘valid’ again.

Next, in a state where the address signal TA[1:0] is set to ‘10’, the test mode signal T2is activated to ‘1’ by inputting the command signal CMD for indicating the test mode entry command. As a result, only the leakage cut-off transistors LTP2and LTN2are set to ‘invalid’. In this state, if the result of the function test is a pass, it is determined that defects have occurred in the circuit block BLK2due to the leakage cut-off function. Meanwhile, if the result of the function test is a fail, the test mode signal T2is inactivated to ‘0’ by inputting the command signal CMD for indicating the test mode exit command. Accordingly, the leakage cut-off transistors LTP2and LTN2are set to ‘valid’ again.

Thereafter, in a state where the address signal TA[1:0] is set to ‘11’, the test mode signal T3is activated to ‘1’ by inputting the command signal CMD for indicating the test mode entry command. As a result, only the leakage cut-off transistors LTP3and LTN3are set to ‘invalid’. In this state, if the result of the function test is a pass, it is determined that defects have occurred in the circuit block BLK3due to the leakage cut-off function. For example, if the semiconductor device SD10operates in the same manner as the operation example ofFIG. 7during the normal mode, a pass is determined as the result of the function test in this state and it is determined that defects have occurred in the circuit block BLK3due to the leakage cut-off function.

FIG. 8illustrates an operation example (with defect) during a test mode in a semiconductor device ofFIG. 1. This operation example corresponds to the operation of the semiconductor device SD10during the test mode, which operates in the same manner as the operation example ofFIG. 7during the normal mode. In this operation example, the operation mode of the semiconductor device SD10is the test mode, and the test mode signals T0to T2are respectively inactivated to ‘0’ and the test mode signal T3is activated to ‘1’. Accordingly, the leakage cut-off control signal /OFF3is always inactivated to ‘1’ ((a) ofFIG. 8) and the leakage cut-off control signal OFF3is always inactivated to ‘0’ ((b) ofFIG. 8). In other words, the leakage cut-off transistors LTP3and LTN3are set to ‘invalid’. Therefore, a voltage of the node NL3within the circuit block BLK3is always set to the ground voltage VSS ((c) ofFIG. 8) and a voltage of the node NH3within the circuit block BLK3is always set to the power supply voltage VDD ((d) ofFIG. 8). For this reason, even when the semiconductor device SD10operates in the same manner as the operation example ofFIG. 7during the normal mode, the internal signal /SIG4is activated to ‘0’ ((e) ofFIG. 8) in the same manner as the operation example ofFIG. 6. Therefore, in the case where in the test process of the semiconductor device SD10, the result of the function test performed in the normal mode is a fail, through the above-mentioned processings, the result will be a pass when the function test is performed in a state where only the test mode signal T3is activated to ‘1’. This can lead to specifying that the circuit block BLK3is the one having defects due to the leakage cut-off function. As described above, in the semiconductor device SD10according to the first embodiment, it is possible to easily determine a location at which a defect has been occurred due to the leakage cut-off function and to improve the easiness of defect analysis.

FIG. 9shows a comparison example of the invention. In describing the comparison example, the same parts as those of the first embodiment are represented by the same reference numerals, and the descriptions thereof will be omitted. A semiconductor device SD10aincludes a leakage cut-off control circuit LCC0, circuit blocks BLK0to BLK3and leakage cut-off transistors LTP0and LTN0. The leakage cut-off control circuit LCC0receives a test mode signal TEST as an input signal of an inverter100. The test mode signal TEST is inactivated to ‘0’ when the operation mode of the semiconductor device SD10ais the normal mode and is activated to ‘1’ when the operation mode of the semiconductor device SD10ais the test mode. Therefore, the leakage cut-off transistors LTP0and LTN0are set to ‘valid’ when the operation mode of the semiconductor device SD10ais the normal mode and are set to ‘invalid’ when the operation mode of the semiconductor device SD10ais the test mode.

A power supply terminal PH1of the circuit block BLK1, a power supply terminal PH2of the circuit block BLK2and a power supply terminal PH3of the circuit block BLK3are connected to a power supply line VDD through the leakage cut-off transistor LTP0in the same manner as a power supply terminal PH0of the circuit block BLK0. A power supply terminal PL1of the circuit block BLK1, a power supply terminal PL2of the circuit block BLK2and a power supply terminal PL3of the circuit block BLK3are connected to a ground line VSS through the leakage cut-off transistor LTN0in the same manner as a power supply terminal PL0of the circuit block BLK0.

FIG. 10illustrates an operation example (with defect) during a test mode in a semiconductor device ofFIG. 9. This operation example corresponds to the operation of the semiconductor device SD10aduring the test mode, which operates in the same manner as the operation example ofFIG. 7during the normal mode. In the operation example, the operation mode of the semiconductor device SD10ais the test mode and the test mode signal TEST is activated to ‘1’. Due to this, the leakage cut-off control signal /OFF0is always inactivated to ‘1’ ((a) ofFIG. 10) and the leakage cut-off control signal OFF0is always inactivated to ‘0’ ((b) ofFIG. 10). In other words, the leakage cut-off transistors LTP0and LTN0are set to ‘invalid’. Therefore, voltages of nodes NL0to NL3within the circuit blocks BLK0to BLK3are always set to the ground voltage VSS ((c) ofFIG. 10) and voltages of nodes NH0to NH3within the circuit blocks BLK0to BLK3are always set to the power supply voltage VDD ((d) ofFIG. 10). Therefore, even when the semiconductor device SD10aoperates in the same manner as the operation example ofFIG. 7during the normal mode, the internal signal /SIG4is activated to ‘O’ ((e) ofFIG. 10) in the same manner as the operation example ofFIG. 6.

Accordingly, in the test process of the semiconductor device SD10a, if the result of the function test during the normal mode is a fail, the result will become a pass when the function test is performed again in the test mode. This reveals that defects have occurred due to the leakage cut-off function. However, it is not able to specify that the circuit block BLK3is the one having defects due to the leakage cut-off function. As described above, in the semiconductor device SD10aof the comparison example, it is not possible to specify a location at which a defect has been occurred due to the leakage cut-off function. Therefore, efficient defect analysis is not feasible, consuming an enormous amount of time.

FIG. 11shows a second embodiment of the invention. In describing the second embodiment, the same parts are represented by the same reference numerals, and the descriptions thereof will be omitted. A semiconductor device SD20according to the second embodiment may be mounted in an electronics device having the function block construction as shown inFIGS. 2(a) to2(d) in the same manner as the semiconductor device SD10according to the first embodiment. The semiconductor device SD20may implement at least one of the function blocks. The semiconductor device SD20includes a control signal generating circuit CGCF, fuse circuits FC0to FC3(storage circuits), leakage cut-off control circuits LCC0to LCC3, circuit blocks BLK0to BLK3and leakage cut-off transistors LTP0to LTP3and LTN0to LTN3.

The control signal generating circuit CGCF temporarily activates a fuse reset signal /FSR to ‘0’ when the semiconductor device SD20is powered. The control signal generating circuit CGCF temporarily activates a fuse set signal FSS to ‘1’ after the fuse reset signal /FSR is inactivated. The fuse circuit FCi (i=0, 1, 2, 3) outputs a fuse state signal Fi (a storage state signal) for indicating whether a fuse FS is blown or not on the basis of the fuse reset signal /FSR and the fuse set signal FSS. The leakage cut-off control circuit LCCi receives the fuse state signal Fi as an input signal of an inverter100. Therefore, the leakage cut-off transistors LTPi and LTNi are set to ‘valid’ when the fuse state signal Fi is inactivated to ‘0’ and are set to ‘invalid’ when the fuse state signal Fi is activated to ‘1’.

FIG. 12shows a fuse circuit inFIG. 11. The fuse circuit FCi includes pMOS transistors TP50and TP51, nMOS transistors TN50to TN52, the fuse FS and inverters I50and I51. The PMOS transistor TP50has a source connected to the power supply line VDD. A drain of the pMOS transistor TP50is connected to a drain of the nMOS transistor TN50. The nMOS transistor TN50has a source connected to the ground line VSS through the fuse FS. The pMOS transistor TP50has a gate to which the fuse reset signal /FSR is input. The nMOS transistor TN50has a gate to which the fuse set signal FSS is input.

The pMOS transistor TP51has a source connected to the power supply line VDD. A drain of the PMOS transistor TP51is connected to a drain of the nMOS transistor TN51. A source of the nMOS transistor TN51is connected to a source of the nMOS transistor TN52. The nMOS transistor TN52has a source connected to the ground line VSS. The pMOS transistor TP51and the nMOS transistor TN51have gates to which the output signal of the inverter I50is input. The nMOS transistor TN52has a gate to which the fuse reset signal /FSR is input. A connection node of the pMOS transistor TP50and the nMOS transistor TN50, a connection node of the PMOS transistor TP51and the nMOS transistor TN51and an input terminal of the inverter I50are interconnected. The inverter I51inverts the output signal of the inverter I50and outputs the inverted signal as the fuse state signal Fi.

FIG. 13illustrates an operation of a fuse circuit inFIG. 12. If the semiconductor device SD20is powered, the power supply voltage VDD rises ((a) ofFIG. 13). If the fuse reset signal /FSR supplied from the control signal generating circuit CGCF is activated to ‘0’ ((b) ofFIG. 13), the PMOS transistor TP50of the fuse circuit FCi is turned on and the nMOS transistor TN52of the fuse circuit FCi is turned off. Since the output signal of the inverter I50of the fuse circuit FCi is set to ‘0’, the fuse state signal Fi supplied from the inverter151of the fuse circuit FCi is activated to ‘1’ ((c) ofFIG. 13). Furthermore, if the fuse reset signal /FSR is inactivated to ‘1’, the pMOS transistor TP50of the fuse circuit FCi is turned off and the nMOS transistor TN52of the fuse circuit FCi is turned on.

If the fuse set signal FSS supplied from the control signal generating circuit CGCF is activated to ‘1’ after the fuse reset signal /FSR is inactivated to ‘1’ ((d) ofFIG. 13), the nMOS transistor TN50of the fuse circuit FCi is turned on. If the fuse FS of the fuse circuit FCi has not been blown, the output signal of the inverter I50of the fuse circuit FCi changes from ‘0’ to ‘1’. Accordingly, the fuse state signal Fi is inactivated to ‘0’ ((e) ofFIG. 13). Meanwhile, if the fuse FS of the fuse circuit FCi has been blown, the fuse state signal Fi is activated to ‘1’ since the output signal of the inverter I50of the fuse circuit FCi does not change from ‘0’ to ‘1’. Therefore, the leakage cut-off transistors LTPi and LTNi are set to ‘valid’ when the fuse FS of the fuse circuit FCi is not blown and are set to ‘invalid’ when the fuse FS of the fuse circuit FCi is blown.

In the test process of the semiconductor device SD20constructed as described above, the function test is performed in order to make a pass/fail determination. It is then determined whether the semiconductor device SD20is good or defective based on the pass/fail determination. Furthermore, at this point, the fuses FS of the fuse circuits FC0to FC3are not blown. If the result of the function test is a fail, the function test can be sequentially performed while the fuses FS is blown in order of the fuse circuits FC0, FC1, FC2and FC3. A location at which a defect has been occurred due to the leakage cut-off function can be easily determined based on the pass/fail determination and the state (blown or non-blown state) of the fuses FS at the fuse circuits FC0to FC3. For example, if the semiconductor device SD20can be operated in the same manner as the operation example ofFIG. 7in a state where all of the fuses FS of the fuse circuits FC0to FC3are not blown, a pass is obtained through the function test performed in a state where the fuse FS of the fuse circuit FC3is blown. Accordingly, it is possible to specify that the circuit block BLK3is the one having defects due to the leakage cut-off function. As described above, in the semiconductor device SD20according to the second embodiment, a location at which a defect has been occurred due to the leakage cut-off function can be easily determined so as to improve the easiness of defect analysis in the same manner as the semiconductor device SD10according to the first embodiment.

FIG. 14shows a third embodiment of the invention. In the third embodiment, the same parts are represented by the same reference numerals as those of the first and second embodiments, and the descriptions thereof will be omitted. A semiconductor device SD30according to the third embodiment may be mounted in an electronics device having the function block construction as shown inFIGS. 2(a) to2(d) in the same manner as the semiconductor device SD10according to the first embodiment. The semiconductor device SD30may implement at least one of the function blocks.

The semiconductor device SD30includes a control signal generating circuit CGCT, a test mode signal generating circuit TGC, a control signal generating circuit CGCF, fuse circuits FC0to FC3, EOR circuits EC0to EC3(a uniting circuit), leakage cut-off control circuits LCC0to LCC3, circuit blocks BLK0to BLK3and leakage cut-off transistors LTP0to LTP3and LTN0to LTN3. The EOR circuit ECi (i=0, 1, 2, 3) performs an exclusive OR operation on a test mode signal Ti received from the test mode signal generating circuit TGC and a fuse state signal Fi received from the fuse circuit FCi and outputs the operation result as a control signal TFi (a second control signal). The leakage cut-off control circuit LCCi receives the control signal TFi as an input signal of an inverter100. Therefore, the leakage cut-off transistors LTPi and LTNi are set to ‘valid’ when the control signal TFi is inactivated to ‘0’ and are set to ‘invalid’ when the control signal TFi is activated to ‘1’.

FIG. 15shows an EOR circuit inFIG. 14. The EOR circuit ECi includes inverters I60and I61and NAND gates G60to G62. The inverter I60inverts the fuse state signal Fi received from the fuse circuit FCi and outputs the inverted signal. The inverter I61inverts the test mode signal Ti received from the test mode signal generating circuit TGC and outputs the inverted signal. The NAND gate G60performs an NAND operation for the test mode signal Ti and an output signal of the inverter I60and outputs the operation result. The NAND gate G61performs an NAND operation for an output signal of the inverter I61and the fuse state signal Fi and outputs the operation result. The NAND gate G62performs an NAND operation for an output signal of the NAND gate G60and an output signal of the NAND gate G61and outputs the operation result. Through such a circuit construction, the control signal TFi is activated to ‘1’ when either the test mode signal Ti or the fuse state signal Fi is activated to ‘1’. The control signal TFi is inactivated to ‘0’ when both the test mode signal Ti and the fuse state signal Fi are inactivated to ‘0’ or when both the test mode signal Ti and the fuse state signal Fi are activated to ‘1’.

In the case where the semiconductor device SD30constructed as described above operates in the same manner as the operation example ofFIG. 7during the normal mode, the result of the function test performed during the normal mode in the test process will be a fail. In this case, it is possible to specify that the circuit block having defects due to the leakage cut-off function is the circuit block BLK3, by performing the same defect analysis as that of the first embodiment. Therefore, defect analysis can be also performed within a short period of time in the semiconductor device SD30of the third embodiment as in the semiconductor device SD10according to the first embodiment.

Furthermore, if the fuse FS of the fuse circuit FC3corresponding to the circuit block BLK3having defects is blown, the result of the function test performed in the normal mode will be a pass. However, off-state leakage current is not reduced in the circuit block BLK3and power consumption in the standby period of the semiconductor device SD30slightly increases. However, if the power consumption increase does not cause a problem to a user of the semiconductor device SD30, the semiconductor device SD30can be provided as a good product without waiting for correcting defects.