Electronic device and method of manufacturing the same

A semiconductor memory may include: variable resistance layers and insulating layers alternately stacked; conductive pillars passing through the variable resistance layers and the insulating layers; a slit insulating layer passing through the insulating layers and extending in a first direction; and conductive layers interposed between the slit insulating layer and the variable resistance layers. The variable resistance layers may remain in an amorphous state during a program operation.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2019-0175654, filed on Dec. 26, 2019, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

1. Technical Field

Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to an electronic device including a semiconductor memory and a method of manufacturing the electronic device.

2. Related Art

Recently, with requirement of miniaturization, low power consumption, high performance, and diversification of electronic apparatuses, semiconductor devices configured to store information are needed in various electronic apparatuses such as computers and portable communication apparatuses. Therefore, there has been research on semiconductor devices configured to store data using characteristics of switching between different resistance phases depending on applied voltage or current. Examples of such semiconductor devices include a resistive random access memory (RRAM), a phase-change random access memory (PRAM), a ferroelectric random access memory (FRAM), a magnetic random access memory (MRAM), an E-fuse, and so forth.

SUMMARY

Various embodiments of the present disclosure are directed to an electronic device having improved operating characteristics and reliability of memory cells, and a method of manufacturing the electronic device.

An embodiment of the present disclosure may provide for an electronic device including a semiconductor memory. The semiconductor memory may include: variable resistance layers and insulating layers alternately stacked; conductive pillars passing through the variable resistance layers and the insulating layers; a slit insulating layer passing through the insulating layers and extending in a first direction; and conductive layers interposed between the slit insulating layer and the variable resistance layers. The variable resistance layers may remain in an amorphous state during a program operation.

An embodiment of the present disclosure may provide for an electronic device including a semiconductor memory. The semiconductor memory may include: insulating layers stacked; first variable resistance layers alternately stacked with the insulating layers and each extending in a first direction; vertical bit lines passing through the first variable resistance layers and the insulating layers; a first slit insulating layer passing through the insulating layers and extending in the first direction; a second slit insulating layer passing through the insulating layers and extending in the first direction; first word lines each interposed between the first slit insulating layer and each of the first variable resistance layers; and second word lines each interposed between the second slit insulating layer and each of the first variable resistance layers. First memory cells may be respectively disposed between the vertical bit lines and the first word lines, second memory cells may be respectively disposed between the vertical bit lines and the second word lines, and each of the first memory cells and each of the second memory cells are disposed adjacent in a second direction and share a corresponding one of the first variable resistance layers.

An embodiment of the present disclosure may provide for a method of manufacturing an electronic device including a semiconductor memory. The method may include: alternately forming first variable resistance layers and insulating layers; forming conductive pillars passing through the first variable resistance layers and the insulating layers; forming a slit passing through the first variable resistance layers and the insulating layers and extending in a first direction; forming openings by etching the first variable resistance layers exposed through the slit; and forming conductive layers in the respective openings.

DETAILED DESCRIPTION

Specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are only for description of the embodiments of the present disclosure. The descriptions should not be construed as being limited to the embodiments described in the specification or application.

FIGS. 1A and 1Beach illustrate a memory cell array of an electronic device in accordance with an embodiment of the present disclosure.

Referring toFIG. 1A, the electronic device in accordance with an embodiment of the present disclosure may include a semiconductor memory. The semiconductor memory may include word lines WL, and bit lines BL intersecting with the word lines WL. For reference, the notions of the terms “word lines WL” and “bit lines BL” may be relative to each other. Hence, the word lines WL may be bit lines, and the bit lines BL may be word lines.

The semiconductor memory may include memory cells MC coupled between the word lines WL and the bit lines BL. A plurality of memory cells MC may share one bit line BL. The memory cells MC that share the bit line BL may be respectively coupled to different word lines WL.

Each of the memory cells MC may include a memory element, a select element, or a memory element and a select element. Each of the memory cells MC may include a variable resistance layer. The variable resistance layer may have characteristics of making a reversible transition between different resistance states depending on voltage or current applied thereto. The variable resistance layer may be included in the memory element or the select element. Alternatively, the variable resistance layer may function as not only a memory element but also a select element.

The variable resistance layer may include resistance material. The variable resistance layer may include transition metal oxide, or metal oxide such as perovskite-based material. Hence, data may be stored in the memory cell MC by generating or removing an electrical path in the variable resistance layer.

The variable resistance layer may have an MTJ structure. The variable resistance layer may include a magnetization pinned layer, a magnetization free layer, and a tunnel barrier layer interposed therebetween. For example, the magnetization pinned layer and the magnetization free layer may include magnetic material. The tunnel barrier layer may include oxide such as magnesium (Mg), aluminum (Al), zinc (Zn), and titanium (Ti). Here, the magnetization direction of the magnetization free layer may change depending on spin torque of electrons in current applied thereto. Therefore, depending on a change in magnetization direction of the magnetization free layer with respect to the magnetization direction of the magnetization pinned layer, data may be stored in the memory cell MC.

The variable resistance layer may include phase-change material, and may include chalcogenide-based material. The variable resistance layer may include chalcogenide glass, a chalcogenide-based alloy, etc. The variable resistance layer may include silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn), selenium (Se), or a combination thereof. For example, the variable resistance layer may have a Ge—Sb—Te (GST) structure, and be formed of Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, or Ge1Sb4Te7. The variable resistance layer may change in phase depending on a program operation. The variable resistance layer may have a low-resistance crystalline state by a set operation. The variable resistance layer may have a high-resistance amorphous state by a reset operation. Therefore, data may be stored in the memory cell MC by using a difference in resistance depending on the phase of the variable resistance layer.

The variable resistance layer may include variable resistance material which changes in resistance without a phase change, and may include chalcogenide-based material. The variable resistance layer may include germanium (Ge), antimony (Sb), tellurium (Te), arsenic (As), selenium (Se), silicon (Si), indium (In), tin (Sn), sulfur (S), gallium (Ga), or a combination thereof. The variable resistance layer may have one phase and retain the phase thereof during a program operation. For example, the variable resistance layer may have an amorphous state, and the phase thereof may not be changed into a crystalline state. Therefore, the threshold voltage of the memory cell MC may change depending on a program pulse applied to the memory cell MC, so that the memory cell MC may be programmed to at least two types of states. The variable resistance layer may have a high-resistance amorphous state by a reset operation, so that the memory cell MC may be programmed to a reset state having a high threshold voltage. The variable resistance layer may have a low-resistance amorphous state by a set operation, so that the memory cell MC may be programmed to a set state having a low threshold voltage.

Referring toFIG. 1B, the semiconductor memory may include odd word lines O_WL, even word lines E_WL, vertical bit lines V_BL, and memory cells MC. The odd word lines O_WL and the even word lines E_WL each may extend in a first direction I.

The vertical bit lines V_BL may each extend in a third direction III. The memory cells MC that are coupled between the vertical bit lines V_BL and the odd word lines O_WL may be referred to as odd memory cells. The memory cells MC that are coupled between the vertical bit lines V_BL and the even word lines E_WL may be referred to as even memory cells. An even memory cell and an odd memory cell that are disposed in the same level with respect to the third direction III and are adjacent to each other in a second direction II may share an identical vertical bit line V_BL. Even memory cells that are disposed in the same level with respect to the third direction III and are adjacent to each other in the first direction I may share an identical even word line E_WL. Odd memory cells that are disposed in the same level with respect to the third direction III and are adjacent to each other in the first direction I may share an identical odd word line O_WL. Here, the second direction II may be a direction intersecting with the first direction I. Here, the third direction III may be a direction intersecting with the first direction I and the second direction II. For example, the third direction III may be a direction perpendicular to a plane defined by the first direction I and the second direction II.

The semiconductor memory may further include switches SW for selecting the vertical bit lines V_BL. Connection between the vertical bit lines V_BL and the bit lines BL may be controlled by the switches SW. The switches SW may include a transistor, a vertical transistor, a diode, etc. In addition, the semiconductor memory may include word lines WL for selectively driving the switches SW.

The word lines WL and the bit lines BL may be used to select a switch SW. One word line WL may be selected from the plurality of word lines WL, and one bit line BL may be selected from the plurality of bit lines BL. Thereby, one switch SW may be selected from the plurality of switches SW.

The switches SW may be used to select a vertical bit line V_BL. When the selected switch SW is turned on, the corresponding bit line BL may be coupled with the corresponding vertical bit line V_BL. Hence, one vertical bit line V_BL may be selected from the plurality of vertical bit lines V_BL. Furthermore, one odd word line O_WL may be selected from the plurality of odd word lines O_WL or one even word line E_WL may be selected from the plurality of even word lines E_WL. Thereby, a memory cell MC coupled between the selected vertical bit line V_BL and the selected word line O_WL or E_WL may be selected.

FIGS. 2A and 2Bare diagrams illustrating the structure of a semiconductor device in accordance with an embodiment of the present disclosure.FIG. 2Aillustrates a plan view, andFIG. 2Billustrates a cross section taken along a line A-A′ in the second direction II ofFIG. 2A. Hereinbelow, repetitive explanation will be omitted for the interest of brevity.

Referring toFIGS. 2A and 2B, the semiconductor device may include variable resistance layers21, insulating layers22, conductive pillars23, conductive layers24, and a slit insulating layer25.

The variable resistance layers21and the insulating layers22are alternately stacked. The variable resistance layers21and the insulating layers22may enclose sidewalls of the conductive pillars23and be stacked in the third direction III. The variable resistance layers21may have characteristics of making a reversible transition between different resistance states depending on voltage or current applied thereto. The variable resistance layers21may include resistance material, phase-change material, variable resistance material, an MTJ structure, chalcogenide material, etc. The insulating layers22may be provided to separate the stacked variable resistance layers21from each other. The insulating layers22may include insulating material such as oxide or nitride.

Each variable resistance layer21and each insulating layer22may have different widths in the second direction II. Each of the variable resistance layers21may have a first width W1. Each of the insulating layers22may have a second width W2. For example, each of the insulating layers22may have the second width W2greater than that W1of the variable resistance layers21. The insulating layers22may protrude in the second direction II compared to the variable resistance layers21. For example, a second portion (e.g., a right portion) of the insulating layer22may protrude farther from the conductive pillar23than a second portion (e.g., a right portion) of the variable resistance layer21in the second direction II, the second portion of the insulating layer22and the second portion of the variable resistance layer21being disposed adjacent to each other in the third direction III. A first portion (e.g., a left portion) of the insulating layer22may protrude farther from the conductive pillar23than a first portion (e.g., a left portion) of the variable resistance layer21in a direction opposite to the second direction II, the first portion of the insulating layer22and the first portion of the second variable resistance layer21being disposed adjacent to each other in the third direction III. Portions of each insulating layer22that protrude compared to the variable resistance layer21, in other words, portions of the insulating layer22that do not overlap with the variable resistance layer21with respect to the third direction III, may be defined as protrusions. For example, a portion of the insulating layer22may protrude compared to a variable resistance layer21such that the portion of the insulating layer22protrudes from the variable resistance layer21in a cross-sectional view, and the portion of the insulating layer22may be referred to as a protrusion. Each of the insulating layers22may include a first protrusion P1and a second protrusion P2. The first protrusion P1may protrude compared to a first sidewall of the variable resistance layer21. The second protrusion P2may protrude compared to a second sidewall of the variable resistance layer21. For example, the first protrusion P1may protrude from the first sidewall of the variable resistance layer21and the second protrusion P2may protrude from the second sidewall of the variable resistance layer21, in a cross-sectional view.

The slit insulating layer25may pass through the insulating layers22and extend in the first direction I. The slit insulating layers25may include insulating material such as oxide or nitride.

The conductive pillars23each may extend in the third direction III and pass through the variable resistance layers21and the insulating layers22. The conductive pillars23may be arranged in the first direction I and the second direction II. The conductive pillars23that are arranged in the first direction I may form one pillar column. Each variable resistance layer21may enclose the sidewalls of the conductive pillars23belonging to a corresponding identical pillar column and extend in the first direction I. For example, each of the variable resistance layer21may extend in the first direction I and have a plurality of inner surfaces that respectively enclose a plurality of portions of the sidewalls of the conductive pillars23arranged in the first direction I. Therefore, the variable resistance layer21may be interposed between the conductive pillars23that are adjacent to each other in the first direction I. In other words, a plurality of portions of the variable resistance layer21each may be interposed between a pair of the conductive pillars23that are adjacent to each other in the first direction I, thereby filling spaces between the conductive pillars23. The conductive pillars23may be bit lines or vertical bit lines.

The conductive layers24may be interposed between the slit insulating layer25and the variable resistance layers21. Therefore, the variable resistance layer21may be interposed between the conductive layers24that are adjacent to each other in the second direction II. The conductive layers24may be disposed in the same level as that of the variable resistance layers21. For example, with respect to the orientation ofFIG. 2B, a top surface of a conductive layer24may be substantially coplanar with a top surface of a corresponding variable resistance layer21, or a bottom surface of the conductive layer24may be substantially coplanar with a bottom surface of the corresponding variable resistance layer21, or both. The conductive layers24may be disposed between the protrusions P1and P2that are adjacent to each other in the third direction III. For example, a conductive layer24may be disposed between a first pair of protrusions P1and P2and a second pair of protrusions P1and P2, the first pair being disposed adjacent to the second pair in the third direction III. The conductive layers24and the protrusions P1and P2may be alternately stacked.

Each of the conductive layers24may be a word line, in detail, an odd word line or an even word line. The conductive layer24that is disposed on a first side (e.g., a left side) of the variable resistance layer21may be a first word line24A. The conductive layer24that is disposed on a second side (e.g., a right side) of the variable resistance layer21may be a second word line24B. For example, the second word line24B may be interposed between a first slit insulating layer25A and the variable resistance layer21. In addition, the first word line24A may be interposed between a second slit insulating layer25B disposed adjacent to the first slit insulating layer25A in the second direction II and the variable resistance layer21. The first word line24A may be an even word line, and the second word line24B may be an odd word line. Alternatively, the first word line24A may be an odd word line, and the second word line24B may be an even word line.

For reference, although not illustrated, electrode layers may be respectively interposed between the conductive pillars23and the variable resistance layers21or between the variable resistance layers21and the conductive layers24. In addition, although not illustrated, electrode layers may be respectively interposed between the conductive pillars23and the variable resistance layers21and between the variable resistance layers21and the conductive layers24.

According to the above-mentioned structure, memory cells MC1and MC2may be disposed in areas in which the conductive pillars23and the conductive layers24intersect with each other. Each of the memory cells MC1and MC2may include the conductive layer24, the variable resistance layer21, and the conductive pillar23.

The first memory cells MC1may be disposed in areas in which the conductive pillars23and the first word lines24A intersect with each other. The second memory cells MC2may be disposed in areas in which the conductive pillars23and the second word lines24B intersect with each other. The first memory cells MC1may be arranged in the first direction I. The first memory cells MC1that are disposed in the same level may share the variable resistance layer21and the first word line24A. The second memory cells MC2may be arranged in the first direction I. The second memory cells MC2that are disposed in the same level may share the variable resistance layer21and the second word line24B. Furthermore, the first memory cell MC1and the second memory cell MC2that are adjacent to each other in the second direction II may share the variable resistance layer21and the conductive pillars23whereas the first and second memory cells MC1and MC2may be respectively coupled to different word lines24A and24B.

In an embodiment, the variable resistance layers21may include amorphous chalcogenide. The amorphous chalcogenide may have resistance corresponding to that of insulating material under a threshold electric field value. Hence, even if the memory cells MC1and MC2share the variable resistance layer21, a program operation may be selectively performed. In a selected memory cell, an electric field having an electric field value greater than the threshold electric field value may be formed in the variable resistance layer21, and a memory operation may be operated in the corresponding area. On the other hand, in the case of unselected memory cells, an electric field having an electric field value equal to or less than the threshold electric field value is formed in the variable resistance layer21. Therefore, the variable resistance layer21may have insulating characteristics. Consequently, leakage current may be prevented from occurring in the unselected memory cells.

FIGS. 3A and 3Bare diagrams illustrating the structure of a semiconductor device in accordance with an embodiment of the present disclosure.FIG. 3Aillustrates a plan view, andFIG. 3Billustrates a cross section taken along a line A-A′ in the second direction II ofFIG. 3A. Hereinbelow, repetitive explanation will be omitted for the interest of brevity.

Referring toFIGS. 3A and 3B, the semiconductor device may include first variable resistance layers31, second variable resistance layers (e.g., phase-change layers)36, insulating layers32, conductive pillars33, conductive layers34, and a slit insulating layer35.

The first variable resistance layers31and the insulating layers32are alternately stacked. Each of the insulating layers32may have a width greater than that of each of the first variable resistance layers31. For example, each of the insulating layers32may have a width in a second direction II greater than that of each of the first variable resistance layers31. The insulating layers32may protrude in the second direction II compared to the first variable resistance layers31. For example, a second portion (e.g., a right portion) of the insulating layer32may protrude farther from the conductive pillar33than a second portion (e.g., a right portion) of the first variable resistance layer31in the second direction II, the second portion of the insulating layer32and the second portion of the first variable resistance layer31being disposed adjacent to each other in the third direction III. A first portion (e.g., a left portion) of the insulating layer32may protrude farther from the conductive pillar33than a first portion (e.g., a left portion) of the first variable resistance layer31in a direction opposite to the second direction II, the first portion of the insulating layer32and the first portion of the first variable resistance layer31being disposed adjacent to each other in the third direction III. Each of the insulating layers32may include a first protrusion P1and a second protrusion P2. The first protrusion P1may protrude compared to a first sidewall of the first variable resistance layer31. The second protrusion P2may protrude compared to a second sidewall of the first variable resistance layer31. For example, the first protrusion P1may protrude from the first sidewall of the first variable resistance layer31and the second protrusion P2may protrude from the second sidewall of the first variable resistance layer31, in a cross-sectional view.

The conductive pillars33each may extend in the third direction III and pass through the first variable resistance layers31and the insulating layers32. Each first variable resistance layer31may enclose the sidewalls of the conductive pillars33belonging to a corresponding identical pillar column and extend in the first direction I. For example, each of the first variable resistance layer31may extend in the first direction I and have a plurality of inner surfaces that respectively enclose a plurality of portions of the sidewalls of the conductive pillars33arranged in the first direction I. Therefore, the first variable resistance layer31may be interposed between the conductive pillars33that are adjacent to each other in the first direction I. The conductive pillars33may be bit lines or vertical bit lines.

The slit insulating layer35may pass through the insulating layers32and extend in the first direction I. The conductive layers34may be interposed between the slit insulating layer35and the first variable resistance layers31. The second variable resistance layers36may be interposed between the first variable resistance layers31and the conductive layers34.

The first variable resistance layers31, the second variable resistance layers36, and the conductive layers34may be disposed in substantially the same level. The second variable resistance layers36and the conductive layers34may be disposed between the protrusions P1and P2that are adjacent to each other in the third direction III. The second variable resistance layers36and the conductive layers34may be alternately stacked with the protrusions P1and P2in the third direction III.

Each of the conductive layers34may be a word line, in detail, an odd word line or an even word line. The first word lines34A may be alternately stacked with the first protrusions P1. The second word lines34B may be alternately stacked with the second protrusions P2.

The first variable resistance layers31and the second variable resistance layers36may have characteristics of making a reversible transition between different resistance states depending on voltage or current applied thereto. The first variable resistance layers31and the second variable resistance layers36may include resistance material, phase-change material, variable resistance material, an MTJ structure, chalcogenide material, etc. In an embodiment, the first variable resistance layers31may include chalcogenide and remain in an amorphous state during a program operation. The second variable resistance layers36may include phase-change material. In an embodiment, the second variable resistance layers36may include chalcogenide and be phase-changed into an amorphous state or a crystalline state during the program operation.

For reference, although not illustrated, electrode layers may be respectively interposed between the conductive pillars33and the first variable resistance layers31, or between the first variable resistance layers31and the second variable resistance layers36, or between the second variable resistance layers36and the conductive layers34. Alternatively, electrode layers may be provided on at least some of interfaces of the conductive pillars33, the first variable resistance layer31, the second variable resistance layer36, and the conductive layer34. For example, electrode layers may be provided on two or more of a first interface between a conductive pillar33and a first variable resistance layer31, a second interface between the first variable resistance layer31and a second variable resistance layer36, and a third interface between the second variable resistance layer36and the conductive layer34.

According to the above-mentioned structure, memory cells MC1and MC2may be disposed in areas in which the conductive pillars33and the conductive layers34intersect with each other. Each of the memory cells MC1and MC2may include the conductive layer34, the first variable resistance layer31, the second variable resistance layer36, and the conductive pillar33. The first memory cell MC1and the second memory cell MC2that are adjacent to each other in the second direction II may share the first variable resistance layer31, and each may include the second variable resistance layer36. The first variable resistance layer31may be interposed between a second variable resistance layer36A of the first memory cell MC1and a second variable resistance layer36B of the second memory cell MC2, so that the second variable resistance layer36A and the second variable resistance layer36B may be separated from each other. Here, the first variable resistance layer31may function as a select element. The second variable resistance layer36may function as a memory element.

FIGS. 4A and 4Bare diagrams illustrating the structure of a semiconductor device in accordance with an embodiment of the present disclosure.FIG. 4Aillustrates a plan view, andFIG. 4Billustrates a cross section taken along a line A-A′ in the second direction II ofFIG. 4A. Hereinbelow, repetitive explanation will be omitted for the interest of brevity.

Referring toFIGS. 4A and 4B, the semiconductor device may include first variable resistance layers41, second variable resistance layers46, insulating layers42, conductive pillars43, electrode layers47, conductive layers44, and a slit insulating layer45.

The first variable resistance layers41and the insulating layers42are alternately stacked. The conductive pillars43may extend in the third direction III and pass through the first variable resistance layers41and the insulating layers42. The slit insulating layer45may pass through the insulating layers42and extend in the first direction I.

The conductive layers44may be interposed between the slit insulating layer45and the first variable resistance layers41. Each of the conductive layers44may be a word line, in detail, an odd word line or an even word line. The second variable resistance layers46may be interposed between the first variable resistance layers41and the conductive layers44. The second variable resistance layers46may extend between the conductive layers44and the insulating layers42, and each may have a C-shaped cross-section. For example, a second variable resistance layer46may have a first portion extending in the second direction II, a second portion extending in the section direction II and spaced apart from the first portion by a given distance in the third direction III, and a third portion connecting the first portion and the second portion, each of the first portion and the second portion being disposed between a conductive layer44and an insulating layer42. The electrode layers47may be interposed between the first variable resistance layers41and the second variable resistance layers46. The electrode layers47may extend between the conductive layers44and the insulating layers42, and each may have a C-shaped cross-section. For example, each C-shaped second variable resistance layer46may be formed in the corresponding C-shaped electrode layer47. Each electrode layer44may be formed in the corresponding C-shaped second variable resistance layer46.

For reference, although not illustrated, additional electrode layers may be interposed between the conductive pillars43and the first variable resistance layers41or between the second variable resistance layers46and the conductive layers44. Alternatively, additional electrode layers may be interposed between the conductive pillars43and the first variable resistance layers41and between the second variable resistance layers46and the conductive layers44.

According to the above-mentioned structure, memory cells MC may be disposed in areas in which the conductive pillars43and the conductive layers44intersect with each other. Each of the memory cells MC1and MC2may include the conductive pillar43, the first variable resistance layer41, the electrode layers47, the second variable resistance layer46, and the conductive layer44.

FIGS. 5A, 5B, and 5Care diagrams illustrating a method of manufacturing an electronic device in accordance with an embodiment of the present disclosure. Hereinbelow, repetitive explanation will be omitted for the interest of brevity.

Referring toFIG. 5A, variable resistance layers51and insulating layers52may be alternately stacked. The variable resistance layers51may include one or more materials having characteristics of making a reversible transition between different resistance states depending on voltage or current applied thereto. The variable resistance layers51may include resistance material, phase-change material, variable resistance material, an MTJ structure, chalcogenide material, etc. For example, each of the variable resistance layers51may include an amorphous chalcogenide layer. Each of the insulating layers52may include an oxide layer, a nitride layer, etc.

Thereafter, conductive pillars53passing through the variable resistance layers51and the insulating layers52may be formed. The conductive pillars53may be bit lines or vertical bit lines. Thereafter, a slit SL passing through the variable resistance layers51and the insulating layers52may be formed. The slit SL may be disposed between adjacent conductive pillars53and extend in one direction. For example, the slit SL may be disposed between conductive pillars53that are adjacent in a second direction (e.g., the horizontal direction inFIG. 5A) and extend in a third direction (e.g., the vertical direction inFIG. 5A) intersecting the second direction. The slit SL may further extend in a first direction that is perpendicular to the plane defined by the second and third directions.

Referring toFIG. 5B, openings OP may be formed by removing portions of the variable resistance layers51through the slit SL. The openings OP may be formed by etching the respective portions of the variable resistance layers51to a predetermined depth from the slit SL. The openings OP may be formed by selectively etching the variable resistance layers51. Therefore, each of the insulating layers52may have a width greater than that of each of the remaining variable resistance layers51′. Each of the insulating layers52may include a protrusion P that protrudes compared to the variable resistance layers51′. The openings OP may be disposed between the protrusions P and extend in one direction. For example, each of the openings OP may be disposed between a pair of protrusions P adjacent in the third direction (e.g., the vertical direction inFIG. 5B) and extend in the second direction (e.g., the horizontal direction inFIG. 5B). Each of the openings OP may further extend in the first direction that is perpendicular to the plane defined by the second and third directions.

Referring toFIG. 5C, conductive layers54may be formed in the respective openings OP. For example, conductive material may be formed in the openings and the slit SL. The conductive material may be formed to have a thickness such that the openings OP are substantially completely filled with the conductive material whereas the slit SL is not completely filled with the conductive material. Subsequently, the conductive material may be removed from the slit SL. Thereby, the conductive layers54that are separated from each other may be formed. Each of the conductive layers54may be a word line, in detail, an odd word line or an even word line. The conductive layers54may include polysilicon, or metal such as tungsten. Thereafter, a slit insulating layer55may be formed in the slit SL.

As a result, memory cells MC may be formed in areas in which the conductive pillars53and the conductive layers54intersect with each other. Each of the memory cells MC may include the conductive pillar53, the variable resistance layer51, and the conductive layer54.

According to the above-mentioned manufacturing method, the variable resistance layers51and the insulating layers52may be alternately formed. Subsequently, the variable resistance layers51are selectively etched and the remaining variable resistance layers51′ may function as a memory element, or a select element, or both in a memory cell MC. In a conventional technique, a plurality of openings may be formed and then a material may be deposited over the plurality of openings to form variable resistance layers therein. Thus, a deposition method with a good step coverage is required for the conventional technique to form the variable resistance layers in the plurality of openings. Compared to the conventional technique in which the variable resistance layers are formed in the openings, a deposition process for the variable resistance layers51may be simplified. For example, an evaporation scheme, such as physical vapor deposition (PVD) scheme, having a relatively poor step coverage may be used to form the variable resistance layers51. Thus, evaporation of multi-component material such as chalcogenide may be facilitated, and formation of a chalcogenide layer may be easily controlled. In addition, a memory cell MC, which includes the remaining variable resistance layer51′ including amorphous chalcogenide and functions as not only a memory element but also a select element, may be implemented.

FIGS. 6A, 6B, and 6Care diagrams illustrating a method of manufacturing an electronic device in accordance with an embodiment of the present disclosure. Hereinbelow, repetitive explanation will be omitted for the interest of brevity.

Referring toFIG. 6A, first variable resistance layers61and insulating layers62may be alternately formed. Thereafter, conductive pillars63passing through the first variable resistance layers61and the insulating layers62may be formed. Thereafter, a slit SL passing through the variable resistance layers61and the insulating layers62may be formed. The slit SL may be disposed between adjacent conductive pillars63and extend in one direction. For example, the slit SL may be disposed between conductive pillars63that are adjacent in a second direction (e.g., the horizontal direction inFIG. 6A) and extend in a third direction (e.g., the vertical direction inFIG. 6A) intersecting the second direction. The slit SL may further extend in a first direction that is perpendicular to the plane defined by the second and third directions.

Referring toFIG. 6B, openings OP may be formed by etching the first variable resistance layers61through the slit SL. The openings OP may be disposed in substantially the same level as that of the remaining first variable resistance layers61′ and interposed between the insulating layers62.

Referring toFIG. 6C, second variable resistance layers66may be formed in the respective openings OP. The second variable resistance layers66may be formed to have a thickness such that the openings OP are not completely filled with the second variable resistance layers66. For example, the second variable resistance layers66may be selectively evaporated on surfaces of the first variable resistance layers61′ through a selective evaporation process.

Thereafter, conductive layers64may be formed in the respective openings OP, and then a slit insulating layer65may be formed in the slit SL. As a result, memory cells MC may be formed in areas in which the conductive pillars63and the conductive layers64intersect with each other. Each of the memory cells MC1and MC2may include the conductive pillar63, the first variable resistance layer61, the second variable resistance layer66, and the conductive layer64.

FIGS. 7A, 7B, 7C, and 7Dare diagrams illustrating a method of manufacturing an electronic device in accordance with an embodiment of the present disclosure. Hereinbelow, repetitive explanation will be omitted for the interest of brevity.

Referring toFIG. 7A, first variable resistance layers71and insulating layers72may be alternately formed. Thereafter, conductive pillars73passing through the first variable resistance layers71and the insulating layers72may be formed. Thereafter, a slit SL passing through the variable resistance layers71and the insulating layers72may be formed. The slit SL may be disposed between adjacent conductive pillars73and extend in one direction. For example, the slit SL may be disposed between conductive pillars73that are adjacent in a second direction (e.g., the horizontal direction inFIG. 7A) and extend in a third direction (e.g., the vertical direction inFIG. 7A) intersecting the second direction. The slit SL may further extend in a first direction that is perpendicular to the plane defined by the second and third directions.

Referring toFIG. 7B, openings OP may be formed by etching the first variable resistance layers71through the slit SL. The openings OP may be disposed in substantially the same level as that of the remaining first variable resistance layers71′ and interposed between the insulating layers72.

Referring toFIG. 7C, an electrode layer77, a second variable resistance layer76, and a conductive layer74may be formed. The electrode layer77and the second variable resistance layer76may be formed along inner surfaces of the openings OP and surfaces of the insulating layers72. The electrode layer77and the second variable resistance layer76may be formed to have thicknesses such that the openings OP are not completely filled with the electrode layer77and the second variable resistance layer76. For example, a sum of a thickness of the electrode layer77and a thickness of the second variable resistance layer76may be smaller than a width of the opening OP in the third direction (e.g., the vertical direction inFIG. 7B). The conductive layer74may be formed on the second variable resistance layer76and fill the openings OP. Thereby, the electrode layer77, the second variable resistance layer76, and the conductive layer74may be formed in the openings OP and the slit SL.

Referring toFIG. 7D, the electrode layer77, the second variable resistance layer76, and the conductive layer74may be removed from the slit SL. Portions of the electrode layer77, the second variable resistance layer76, and the conductive layer74may be removed through the slit SL. Thereby, each of the openings OP may be filled with the remaining electrode layer77, the remaining second variable resistance layer76, and the remaining conductive layer74′.

Thereafter, a slit insulating layer75may be formed in the slit SL. As a result, memory cells MC may be formed in areas in which the conductive pillars73and the conductive layers74intersect with each other. Each of the memory cells MC1and MC2may include the conductive pillar73, the first variable resistance layer71′, the electrode layer77′, the second variable resistance layer76′, and the conductive layer74′.

FIG. 8is a diagram illustrating the configuration of a microprocessor1000which embodies a memory device in accordance with the embodiment.

Referring toFIG. 8, the microprocessor1000may perform tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. For example, the microprocessor1000may include a memory1010, an operating component1020, and a controller1030.

The microprocessor1000may be various data processors such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP) and an application processor (AP).

The memory1010may be a circuit configured to store data in the microprocessor1000as a processor register, a register, or the like. For example, the memory1010may include a data register, an address register, and a floating point register. In addition, the memory1010may include various registers. The memory1010may perform the function of temporarily storing data for which operations are to be performed by the operating component1020, result data of performing the operations, and addresses where data for performing of the operations are stored.

The memory1010may include one or more the embodiments of the above-described electronic devices. For example, the memory1010may include: variable resistance layers and insulating layers which are alternately stacked; conductive pillars which pass through the variable resistance layers and the insulating layers; a slit insulating layer which passes through the insulating layers and extends in the first direction; and conductive layers interposed between the slit insulating layer and the variable resistance layers. The variable resistance layers may retain an amorphous state during a program operation. Thereby, read performance characteristics of the memory1010may be improved. Consequently, the read operation characteristics of the microprocessor1000may be improved.

The operating component1020may perform various four-arithmetical operations or logical operations based on results of decoding commands by the controller1030. For example, the operating component1020may include at least one arithmetic logic unit (ALU).

The controller1030may receive signals from, e.g., the memory1010, the operating component1020, and an external device of the microprocessor1000, perform extraction or decoding of commands, and controlling input and output of signals of the microprocessor1000, and execute processing represented by programs.

The microprocessor1000in accordance to the present embodiment may further include a cache memory1040which may temporarily store data to be input from an external device other than the memory1010or to be output to an external device. In this case, the cache memory1040may exchange data with the memory1010, the operating component1020, and the controller1030through a bus interface1050.

FIG. 9is a diagram illustrating the configuration of a processor1100which embodies a memory device in accordance with the embodiment.

Referring toFIG. 9, the processor1100may improve performance and realize multi-functionality by including various functions other than those of a microprocessor which performs tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The processor1100may include a core1110which functions as a microprocessor, a cache memory1120configured to temporarily store data, and a bus interface1130configured to transfer data between internal and external devices. The processor1100may include various system-on-chips (SoCs) such as a multi-core processor, a graphic processing unit (GPU), and an application processor (AP).

The core1110in accordance with the present disclosure may be a circuit which performs arithmetic logic operations for data input from an external device, and may include a memory1111, an operating component1112, and a controller1113.

The memory1111may be a circuit configured to store data in the processor1100as a processor register, a register, or the like. For example, the memory1111may include a data register, an address register, and a floating point register. In addition, the memory1111may include various registers. The memory1111may perform the function of temporarily storing data for which operations are to be performed by the operating component1112, result data of performing the operations, and addresses where data for performing of the operations are stored. The operating component1112may be a circuit configured to perform operations in the processor1100, and perform, e.g., various four-arithmetical operations or logical operations, based on results of decoding commands by the controller1113. For example, the operating component1112may include at least one arithmetic logic unit (ALU). The controller1113may receive signals from, e.g., the memory1111, the operating component1112, and an external device of the processor1100, perform extraction or decoding of commands, and controlling input and output of signals of the processor1100, and execute processing represented by programs.

The cache memory1120may be a circuit which temporarily stores data to compensate for a difference in data processing speed between the core1110operating at a high speed and an external device operating at a low speed. The cache memory1120may include a primary storage section1121, a secondary storage section1122and a tertiary storage section1123. Generally, the cache memory1120includes the primary and secondary storage sections1121and1122, and may include the tertiary storage section1123in the case where high storage capacity is required. As needed, the number of storage sections included in the cache memory1120may be increased. In other words, the number of storage sections included in the cache memory1120may be changed depending on design. Here, the speeds at which the primary, secondary and tertiary storage sections1121,1122and1123store and discriminate data may be the same or different from each other. In the case where the speeds of the respective storage sections1121,1122and1123are different, the speed of the primary storage section1121may be largest. At least one storage section of the primary storage section1121, the secondary storage section1122and the tertiary storage section1123of the cache memory1120may include one or more of the electronic devices in accordance with the above-described embodiments. For example, the cache memory1120may include: variable resistance layers and insulating layers which are alternately stacked; conductive pillars which pass through the variable resistance layers and the insulating layers; a slit insulating layer which passes through the insulating layers and extends in the first direction; and conductive layers interposed between the slit insulating layer and the variable resistance layers. The variable resistance layers may retain an amorphous state during a program operation. Thereby, read performance characteristics of the cache memory1120may be improved. Consequently, the read operation characteristics of the processor1100may be improved.

AlthoughFIG. 9illustrates that all of the primary, secondary, and tertiary storage sections1121,1122and1123are disposed inside the cache memory1120, all of the primary, secondary and tertiary storage sections1121,1122and1123of the cache memory1120may be disposed outside the core1110and may compensate for a difference in data processing speed between the core1110and the external device. Alternatively, the primary storage section1121of the cache memory1120may be disposed inside the core1110, and the secondary storage section1122and the tertiary storage section1123may be disposed outside the core1110to reinforce the function of compensating for a difference in data processing speed. As a further alternative, the primary and secondary storage sections1121and1122may be disposed inside the core1110and the tertiary storage section1123may be disposed outside the core1110.

The bus interface1130may be a circuit which connects the core1110, the cache memory1120and an external device and enhances data transmission efficiency.

The processor1100in accordance with the present embodiment may include a plurality of cores1110. The plurality of cores1110may share the cache memory1120. The plurality of cores1110and the cache memory unit1120may be directly connected or be connected through the bus interface1130. The plurality of cores1110may be configured in the same way as the above-described configuration of the core1110. In the case where the processor1100includes the plurality of cores1110, the primary storage section1121of the cache memory1120may be configured in each core1110based on the number of cores1110, and the secondary storage section1122and the tertiary storage section1123may be configured outside the plurality of cores1110in such a way as to be shared through the bus interface1130. Here, the processing speed of the primary storage section1121may be higher than that of the secondary or tertiary storage section1122or1123. In an embodiment, the primary storage section1121and the secondary storage section1122may be configured in each core1110based on the number of cores1110, and the tertiary storage section1123may be configured outside the plurality of cores1110in such a way as to be shared through the bus interface1130.

The processor1100in accordance with the present embodiment may further include, e.g., an embedded memory1140configured to store data, a communication module1150configured to transceive data with an external device in a wired or wireless manner, a memory controller1160configured to drive an external memory device, and a media processor1170configured to process the data processed in the processor1100or the data input from an external input device and output the processed data to an external interface device. In addition, the processor1100may include a plurality of modules and devices. In this case, the plurality of modules that are additionally provided may exchange data with the cores1110and the cache memory1120and with one another, through the bus interface1130.

The embedded memory1140may include not only a volatile memory but also a nonvolatile memory. Examples of the volatile memory may include, e.g., a dynamic random access memory (DRAM), a mobile DRAM, a static random access memory (SRAM), and a memory having functions similar to that of the foregoing memories. Examples of the nonvolatile memory may include a read only memory (ROM), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and a memory having functions similar to that of the foregoing memories.

The communication module1150may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network, or both of them. The wired network module may include, e.g., a local area network (LAN), a universal serial bus (USB), an Ethernet, or power line communication (PLC), which is operated in a manner similar to that of various devices configured to transceive data through transfer lines. The wireless network module may include infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (CDMA), or ultra wideband (UWB), in a manner similar to that of various devices configured to transceive data without a separate transfer line.

The memory controller1160may process and manage data which is transmitted between the processor1100and external storage devices configured to operate according to different communication standards. The memory controller1160may include various memory controllers, for example, controllers which may control integrated device electronics (IDE), serial advanced technology attachment (SATA), small computer system interface (SCSI), redundant array of independent disks (RAID), a solid state disk (SSD), external SATA (eSATA), personal computer memory card international association (PCMCIA), a universal serial bus (USB), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CE) card.

The media processor1170may process the data processed in the processor1100or the data input in the forms of image, sound, and others from the external input device, and output the data to the external interface device. The media processor1170may include, e.g., a graphic processing unit (GPU), a digital signal processor (DSP), a high definition audio device (HD audio), a high definition multimedia interface (HDMI) controller.

FIG. 10is a diagram illustrating the configuration of a system1200which embodies a memory device in accordance with the embodiment.

Referring toFIG. 10, the system1200may function as a device for processing data and perform input, processing, output, communication, storage, etc. to conduct a series of operations of managing data. The system1200may include, e.g., a processor1210, a main memory device1220, an auxiliary memory device1230, and an interface device1240. Examples of the system1200in accordance with the present embodiment may include various electronic systems configured to operate using processors such as a computer, a server, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a portable multimedia player (PMP), a camera, a global positioning system (GPS), a video camera, a voice recorder, telematics, an audio visual (AV) system, and a smart television.

The processor1210may control operations of decoding input commands and processing calculation, comparison, etc. for the data stored in the system1200. The processor1210may include, e.g., a microprocessor unit (MPU), a central processing unit (CPU), a single/multi-core processor, a graphic processing unit (GPU), an application processor (AP), and a digital signal processor (DSP).

The main memory device1220may be a memory which can receive, when programs are executed, program codes or data from the auxiliary memory device1230and store and execute the program codes or data and can conserve memorized contents even when the power supply is interrupted. The main memory device1220may include one or more of the electronic devices in accordance with the above-described embodiments. For example, the main memory device1220may include: variable resistance layers and insulating layers which are alternately stacked; conductive pillars which pass through the variable resistance layers and the insulating layers; a slit insulating layer which passes through the insulating layers and extends in the first direction; and conductive layers interposed between the slit insulating layer and the variable resistance layers. The variable resistance layers may retain an amorphous state during a program operation. Thereby, read performance characteristics of the main memory device1220may be improved. Consequently, the read operation characteristics of the system1200may be improved.

The main memory device1220may further include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is interrupted. Unlike this, the main memory device1220may not include the electronic devices in accordance with the foregoing embodiment, but may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when the power supply is interrupted.

The auxiliary memory device1230may be a memory device configured to store program codes or data. Although the speed of the auxiliary memory device1230is slower than the main memory device1220, the auxiliary memory device1230can store a relatively large amount of data. The auxiliary memory device1230may include one or more of the electronic devices in accordance with the above-described embodiments. For example, the auxiliary memory device1230may include: variable resistance layers and insulating layers which are alternately stacked; conductive pillars which pass through the variable resistance layers and the insulating layers; a slit insulating layer which passes through the insulating layers and extends in the first direction; and conductive layers interposed between the slit insulating layer and the variable resistance layers. The variable resistance layers may retain an amorphous state during a program operation. Thereby, read performance characteristics of the auxiliary memory device1230may be improved. Consequently, the read operation characteristics of the system1200may be improved.

Also the auxiliary memory device1230may further include, e.g., a data storage system (refer to reference numeral1300ofFIG. 11) such as a magnetic tape or a magnetic disk using magnetism, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card. Unlike this, the auxiliary memory device1230may not include the electronic devices in accordance with the foregoing embodiment, but may further include, e.g., data storage systems (refer to reference numeral1300ofFIG. 11) such as a magnetic tape or a magnetic disk using magnetism, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card.

The interface device1240may perform exchange of commands and data between the system1200of the present embodiment and an external device. For example, the interface device1240may be a keypad, a keyboard a mouse, a speaker, a mike, a display, various human interface devices (HIDs), or a communication device. The communication device may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network, or both of them. The wired network module may include, e.g., a local area network (LAN), a universal serial bus (USB), an Ethernet, or a power line communication (PLC), which is operated in a manner similar to that of various devices configured to transceive data through transfer lines. The wireless network module may include, e.g., infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), or ultra wideband (UWB), which is operated in a manner similar to that of various devices configured to transceive data without a separate transfer line.

FIG. 11is a diagram illustrating the configuration of a data storage system1300which embodies a memory device in accordance with the embodiment.

Referring toFIG. 11, the data storage system1300may include a storage device1310which has a nonvolatile characteristic as a component for storing data, a controller1320configured to control the storage device1310, an interface1330for connection with an external device, and a temporary storage device1340configured to temporarily store data. The data storage system1300may be a disk type such as a hard disk drive (HDD), a compact disc read only memory (CDROM), a digital versatile disc (DVD), or a solid state disk (SSD), or a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), or a compact flash (CF) card.

The storage device1310may include a nonvolatile memory which stores data semi-permanently. Examples of the nonvolatile memory may include a read only memory (ROM), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), and a magnetic random access memory (MRAM).

The controller1320may control data exchange between the storage device1310and the interface1330. To this end, the controller1320may include a processor1321for performing, e.g., an operation for processing commands input through the interface1330from an external device provided outside the data storage system1300.

The interface1330may perform exchange of commands and data between the data storage system1300and an external device. In the case where the data storage system1300is a card type system, the interface1330may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card, or be compatible with interfaces which are used in devices similar to the foregoing devices. In the case where the data storage system1300is a disk type system, the interface1330may be compatible with interfaces such as an integrated device electronics (IDE), a serial advanced technology attachment (SATA), a small computer system interface (SCSI), an external SATA (eSATA), a personal computer memory card international association (PCMCIA), and a universal serial bus (USB), or be compatible with the interfaces similar to the foregoing interfaces. The interface1330may be compatible with one or more interfaces having different types.

The temporary storage device1340may temporarily store data to improve data transfer efficiency between the interface1330and the storage device1310according to diversifications and high performance of an interface with an external device, a controller and a system. The temporary memory device1340may include one or more of the electronic devices in accordance with the foregoing embodiments. For example, the temporary storage device1340may include: variable resistance layers and insulating layers which are alternately stacked; conductive pillars which pass through the variable resistance layers and the insulating layers; a slit insulating layer which passes through the insulating layers and extends in the first direction; and conductive layers interposed between the slit insulating layer and the variable resistance layers. The variable resistance layers may retain an amorphous state during a program operation. Thereby, read performance characteristics of the temporary storage device1340may be improved. Consequently, the read operation characteristics of the data storage system1300may be improved.

FIG. 12is a diagram illustrating the configuration of a memory system1400which embodies a memory device in accordance with the embodiment.

Referring toFIG. 12, the memory system1400may include, e.g., a memory1410having nonvolatile characteristics as a component for storing data, a memory controller1420configured to control the memory1410, an interface1430for connection with an external device. Also the auxiliary memory device1400may be a card type system such as a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), or a compact flash (CF) card.

The memory1410configured to store data may include one or more of the electronic devices in accordance with the foregoing embodiments. For example, the memory1410may include: variable resistance layers and insulating layers which are alternately stacked; conductive pillars which pass through the variable resistance layers and the insulating layers; a slit insulating layer which passes through the insulating layers and extends in the first direction; and conductive layers interposed between the slit insulating layer and the variable resistance layers. The variable resistance layers may retain an amorphous state during a program operation. Thereby, read performance characteristics of the memory1410may be improved. Consequently, the read operation characteristics of the memory system1400may be improved.

Examples of the nonvolatile memory in accordance with the present embodiment may include a read only memory (ROM), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), and a magnetic random access memory (MRAM).

The memory controller1420may control data exchange between the memory1410and the interface1430. To this end, the memory controller1420may include a processor1421for performing, e.g., an operation for processing commands input through the interface1430from an external device provided outside the data storage system1400.

The interface1430may perform exchange of commands and data between the memory system1400and the external device. The interface1430may be compatible with interfaces which are used in devices, such as a universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, or be compatible with interfaces which are used in devices similar to the foregoing devices. The interface1430may be compatible with one or more interfaces having different types.

The memory system1400in accordance with the present embodiment may further include a buffer memory1440for improving data transfer efficiency between the interface1430and the memory1410according to diversification and high performance of an interface with an external device, a memory controller, and a memory system. The buffer memory1440configured to temporarily store data may include one or more of the electronic devices in accordance with the foregoing embodiments. For example, the buffer memory1440may include: variable resistance layers and insulating layers which are alternately stacked; conductive pillars which pass through the variable resistance layers and the insulating layers; a slit insulating layer which passes through the insulating layers and extends in the first direction; and conductive layers interposed between the slit insulating layer and the variable resistance layers. The variable resistance layers may retain an amorphous state during a program operation. Consequently, the read operation characteristics of the memory system1400may be improved.

In addition, examples of the buffer memory1440in accordance with the present embodiment may further include, e.g., a static random access memory (SRAM), and a dynamic random access memory (DRAM), which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), and a magnetic random access memory (MRAM), which have a nonvolatile characteristic. Unlike this, examples of the buffer memory1440may not include the electronic device in accordance with the foregoing embodiment, but may further include, e.g., a static random access memory (SRAM), and a dynamic random access memory (DRAM), which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), and a magnetic random access memory (MRAM), which have a nonvolatile characteristic.

Various embodiments of the present disclosure may provide an electronic device having improved operating characteristics and reliability of memory cells.