Method for power reduction and a device having power reduction capabilities

A device that includes a dual edge triggered flip-flop that has state retention capabilities, the dual edge triggered flip-flop includes: a retention latch that includes a first inverter, a second inverter and a first transfer gate; wherein the first and second inverters receive power during a power gating period; a second latch that includes a third inverter, a fourth inverter and a second transfer gate; wherein the third and fourth inverters are powered down during a power gating period; a third transfer gate that is coupled between input nodes of the retention latch and the second latch; wherein the third transfer gate is opened during the power gating period; wherein the first transfer gate is controlled by a control signal and the second transfer gate is controlled by an inverted control signal; wherein the retention latch stores, at the end of the power gating period a retention value; wherein the retention value is selected, in response to a value of the control signal when the power gating period starts, out of a first initial value stored at the retention latch at the beginning of the power gating period and a second initial value stored at the second latch at the beginning of the power gating period.

FIELD OF THE INVENTION

The present invention relates to a method for power consumption reduction and a device having power consumption reduction capabilities.

BACKGROUND OF THE INVENTION

Power Gating

In modern wireless devices one of the most important figures of merit is power consumption. In order to reduce power consumption, device defines low-power states.

The power consumed by a circuit includes leakage power and switching power. Leakage power is attributed to leakage current that flows through circuit components (such as transistors, diodes, and the like) while switching power is attributed to switching activities of these circuit components.

Power gating techniques involve operating a circuit (such as a processor) at a maximal frequency at nominal supply voltage level during activation periods and shutting down the circuit power supply during deactivation periods, also known as low power periods or power gating periods. Under certain circumstances the logic values stored at memory, registers, flip-flops, latches and the like must be preserved during deactivation periods. This assumes supplying a keep-alive (retention) power to those specific elements and their control elements. Such technique is named State Retention Power Gating (SRPG).

The main concern for SRPG flip-flop is the number of semiconductor devices (e.g. MOSFETs) that must remain powered by a retention power supply. The fewer devices in the SRPG flip-flop will remain powered during the low-power period, the less leakage power will be consumed. Therefore those skilled in the art may appreciate that conventionally only one latch cell (out of two for a classical flip-flop) in the SRPG flip-flop remains powered during the low-power period.

Dual Edge Triggered Flip Flops

Dual edge triggered flip flops include a pair of latching cells—one latches data in response to a positive edge of a clock signal while the other latches data in response to a negative edge of the clock signal. The latch that is selected to output the output value of the dual edge trigger flip flop depends on the logic level of the clock signal and is arbitrary when a power gating period starts. This ambiguity complicates any state retention scheme, when one can not know which latch cell (out of two) must remain powered and retain its value.

SUMMARY OF THE INVENTION

The present invention provides a method and a device as described in the accompanying claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following specification, the invention will be described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.

It has been shown that by powering a retention latch of a dual edge triggered flip-flop and storing a retention value that has either a first or second initial value, a dual edge triggered flip flop with state retention capabilities can be provided.

FIG. 1schematically shows an example of an embodiment of device10. Device10includes one or more dual edge triggered (DET) flip-flops such as DET flip-flop100. Device10can be an integrated circuit, can include one or more integrated circuits, and can be used in a mobile phone, a media player, a computer, a server and the like.

DET flip-flop100has state retention capabilities. It includes retention latch110, second latch120, third transfer gate133, multiple transfer gates130,132,136,138,140and fifth inverter142.

DET flip-flop100can be controlled by one or more control signals such a clock signal (denoted CLK), an inverted clock signal (denoted CLKN), a buffered (i.e. twice inverted) clock signal (denoted CLKNN) a power gating signal (denoted PD), an inverted power gating signal (denoted PDN). These control signals can open transfer gates or can close transfer gates. A transfer gate is open (i.e. transfers a signal between its ports) when it enables current flow through it.

The inverted control signals (CLKN, PDN) and signals derived from these inverted control signals (such as CLKNN which is an inverted signal of CLKN) can be generated per DET flip-flop or per multiple DET flip-flops of device10.

A power gating period is a period during which a gated supply voltage is turned off and conventionally all signals driven by devices connected to gated power supply receive low logic value (although those signals will not get exact zero voltage due to a finite leakage current through the closed power supply switch and whole the power-gated devices in power-gate circuit). Thus if the level of CLK was low when the power gating period started it remains at a low value throughout the power gating period. If the level of CLK was high when the power gating period starts it falls to a low value after a short intermediate period.

Retention latch110includes first inverter114, second inverter116and first transfer gate112. First and second inverters114and116receive power during a power gating period and during other periods. The input of first inverter114is connected to an input node of retention latch110. The output of first inverter114is connected to an output node of retention latch110. The input of second inverter116is connected to the output node of the retention latch. The output of second inverter116is connected to an input of first transfer gate112. The output of first transfer gate112is connected to the input node of retention latch110.

Second latch120does not receive power during the power gating period.

Second latch120includes third inverter124, fourth inverter126and second transfer gate122. The input of third inverter124is connected to an input node of second latch120. The output of third inverter126is connected to an output node of second latch120. The input of fourth inverter126is connected to the output node of second latch120. The output of fourth inverter126is connected to an input of second transfer gate122. The output of second transfer gate122is connected to the input node of second latch120.

Third transfer gate133is connected between the input nodes of retention latch110and second latch120and is opened during the power gating period.

First transfer gate112is controlled by a control signal and second transfer gate122is controlled by an inverted control signal. InFIG. 1the control signal is CLK and the inverted clock signal is CLKN.

Referring to the CMOS logic, a transfer gate includes a PMOS transistor that is connected in parallel to an NMOS transistor. These CMOS transistors receive a pair of control signals. A transfer gate is controlled by a control signal if the gate of its NMOS transistor receives that control signal and the gate of its PMOS transistor receives a complementary control signal.

Just before a power gating period starts and at the beginning of the power gating period retention latch110stores a first initial value and second latch stores a second initial value. These values can differ from each other or be equal to each other. Each power gating period is associated with a first initial value and a second initial value.

At the end of the power gating period retention latch110stores a retention value that is selected from the first and second initial values. The selection is responsive to the value of a control signal (such as CLK) when the power gating period starts.

The retention value can equal the first initial value if the control signal is low when the power gating period starts. The retention value can equal the second initial value if the control signal is high when the power gating period starts.

The control signal can be the clock signal or can be affected by the value of the control signal and even one or more other signals such as the power gating signal.

If the control signal (for example CLK) is high at the beginning of the power gating period it is low after an intermediate period that is shorter than the power gating period and remains low after the power gating period.

Assuming that at the beginning of the power gating period second transfer gate122is open and first transfer gate112is closed then the second initial value (which is latched by second latch120) must be preserved during the power gating period. Since the retention is done in the first latch110, the second initial value is therefore written (via third transfer gate133) to the input node of retention latch110. At this stage (at the beginning of the intermediate period) the retention latch110does not latch this value—because first transfer gate112is closed and thus the feedback loop of the retention latch110is open. Nevertheless, at the end of the intermediate period CLK falls to the voltage, corresponding to low logic value (coupled to the gated power supply voltage), first transfer gate112is opened and second transfer gate122is closed so that retention latch110latches the second initial value.

Assuming that at the beginning of the power gating period second transfer gate122is closed and first transfer gate112is open then the first initial value is stored at retention latch110during the entire power gating period.

Retention latch110and second latch120can be at least partially isolated from the input node and, additionally or alternatively, from the output node of DET flip-flop100.

This isolation can assist in additional leakage prevention (or at least reduce the leakage of DET flip-flop100), and can prevent outside signals (including e.g. retention supply noises, cross-coupling-caused noises and the like) to affect the value that is latched in retention latch110.

Fourth transfer gate130is connected between input node101of DET flip-flop100and inputs of fifth and sixth transfer gates132and136. The output of the fifth transfer gate132is connected to the input node of retention latch110. The output of the sixth transfer gate136is connected to the input node of second latch120.

Seventh transfer gate138is connected between the output node of retention latch110and an input of fifth inverter142. Eighth transfer gate140is connected between the output node of second latch120and the input of fifth inverter142. The output of fifth inverter142is connected to an output node102of DET flip-flop.

Fourth transfer gate130is controlled by PDN and is closed during the power gating period and open outside the power gating period. Fifth transfer gate132and eighth transfer gate140are controlled by CLKNN and are closed during the entire power gating period if at the beginning of the power gating period CLK was low. If CLK was high at the beginning of the power gating period than fifth transfer gate132and eighth transfer gate140are opened until the intermediate period ends and CLK is going to low logic value.

Sixth transfer gate136and seventh transfer gate138are controlled by CLKN are open during the entire power gating period if at the beginning of the power gating period CLK was low (and CLKN was high). If CLK was high at the beginning of the power gating period than sixth transfer gate136and seventh transfer gate138are opened after the intermediate period ends.

During the power gating period first inverter114, second inverter116, sixth inverter144and seventh inverter146are powered i.e. they receive a non-gated supply voltage (retention supply). Other inverters such as third, fourth, and eighth inverters124,126and148are not powered. They receive a gated supply voltage that is not provided during a power gating period.

FIG. 2andFIG. 3are examples of timing diagrams. They illustrate signals such as a gated supply voltage (Vddg)302, CLK304, PD306, first (retention) latch data (A)308, and second latch data (B)312.

Tables 1 and 2 illustrate various values of these signals (as well as an output signal Q of DET flip-flop100) at different points in time—before (T0) the power gating period (PGP), during PGP (T1-T3) and when PGP ends (T4).

TABLE 2VddgCLKPDABQCommentT0H10VaVbVbBefore PGPT1H11Vb—PGP starts and intermediate periodstart, second latch latches Vb andsends Vb to the first (retention)latchT2H01VbVb—Vddg and CLK start to fallT3L01Vb——CLK and Vddg are lowT4H00Vb—VbPGP ends. Vddg is raised beforeT4, retention value = Vb

FIG. 4schematically shows another example of an embodiment of device11. Device11includes one or more dual edge triggered (DET) flip-flops such as DET flip-flop101. Device11can be an integrated circuit, can include one or more integrated circuits, can be a mobile phone, a media player, a computer, a server and the like.

DET flip-flop101differs from DET flip flop100of FIG, by not including fourth transfer gate130, by including a pull-down circuit195and by including logic circuit200instead of sixth, seventh and eighth inverters144,146and148. In addition, the transfer gates (112,122,132,133,136,138and140) of DET flip flop101are controlled by control signals such as CP, CPN, CNP and CPP and not by control signals PD, CLK and CLKN. Control signals CP, CPN, CNP and CPP are generated by logic circuit200. Logic circuit200is powered during the power gating period.

CPP controls third transfer gate133so that third transfer gate133is maintained closed immediately before the power gating period starts and during the power gating period if a value of the clock signal at the beginning of the power gating period is low. In addition, third transfer gate133is closed after the intermediate period ends if at the beginning of the power gating period the clock signal was high.

Logic circuit includes a first NAND gate140, a second NAND gate160, a third NAND gate180, and ninth till eleventh inverters150,170and190.

First NAND gate140receives as inputs PD and CLK and outputs CPPN. CPPN is provided to ninth inverter150that outputs CPP. Second NAND gate160receives at an inverting input PD and at a non inverting input CLK and outputs CPN. CPN is provided to tenth inverter170that outputs CP. Second NAND gate160receives at an inverting input PD and at a non inverting input CLK and outputs CPN. CPN is provided to tenth inverter170that outputs CP. Third NAND gate180receives at its inverting inputs PD and CLK and outputs CNPN. CNPN is provided to eleventh inverter190that outputs CNP.

CPN controls first and sixth transfer gates112and136. CP controls fifth and eighth transfer gates132and140. CPP controls third transfer gate133. CNPN controls second transfer gate122. Pull-down circuit195is controlled by PD and serves for providing a signal having deterministic logic value (low in this example of the embodiment of the invention) to the gate of the fifth inverter142when PD signal is high.

EDT flip flop101reduces leakage by maintaining third transfer gate133closed unless the second initial value should be sent to the retention latch110. The provision of a pull-down signal by pull-down circuit195and the lack of fourth transfer gate130can also contribute to the reduction of leakage and especially leakage through the gates of transistors that are included in transfer gates and inverters. Those skilled in the art may appreciate that the device101is applicable for e.g. semiconductor technology with high MOSFET gate leakage and less applicable for semiconductor technology with relatively low MOSFET gate leakage.

Stage310includes storing at retention latch of a dual edge triggered (DET) flip-flop, immediately before a power gating period starts, a first initial value.

Stage320includes storing at a second latch of a dual edge triggered flip-flop, immediately before a power gating period starts, a second initial value.

Stages310and320are followed by stage330of receiving a power gating signal indicative of a start of a power gating period.

Stage340includes powering, during the power gating period first and second inverters of the retention latch and preventing power from third and fourth inverters of the second latch during the power gating period.

Stage345includes determining if a control criterion is fulfilled. This involves checking the value of at least one control signal at the beginning of the power gating period.

Referring to the example set fourth inFIG. 1, the control criteria is fulfilled if at the beginning of the power gating period CLK is high.

Stage345is followed by stage350of sending (if a control criterion is fulfilled) the second initial value to the retention latch via a third transfer gate. If, for example the control criteria is fulfilled than at the beginning of the power gating period and during an intermediate period—the retention latch is “not storing” (as its feedback loop is open) while the feedback loop of the second latch is closed and it latches the second initial value. Accordingly—when the third transfer gate is open the second initial value is written to the retention latch. At the end of the intermediate period the clock signal goes low together with the gated power supply voltage and the retention latch latches the second initial value. It is noted that the third transfer gate can be closed after the power is prevented from third and fourth inverters.

Else, stage345is followed by stage355of storing at the retention latch the first initial value. If, for example the control criteria is not fulfilled than at the beginning of the power gating mode and during an intermediate period—the second latch is “not storing” (as its feedback loop is open) while the feedback loop of the retention latch is closed so that the it latches the first initial value.

Accordingly, if the control criteria is fulfilled the retention value equals the second initial value and if not it equals the first initial value.

Stage365can include closing, during the power gating period, transfer gates connected before and, additionally or alternatively, after the retention latch or the second latch. For example, stage365can include closing a fourth transfer gate that has an input that is connected to an input node of the dual edge triggered flip flop.

Stages350and355are followed by stage370of storing, at the retention latch, at an end of the power gating period a retention value.

Stage370is followed by stage377of receiving a power gating period indicative that the power gating period ended.

Stage377is followed by stage380of outputting the retention value after the power gating period ends.

Method300can be implemented by device10. For example, the retention value can equal the first initial value if the control signal is low when the power gating period starts; and the retention value can equal the second initial value if the control signal is high when the power gating period starts.

Method300can also include stage305of generating control signals that control the DET flip-flop. Stage305can include, for example, inverting, by a seventh inverter the control signal to provide an inverted control signal. Stage340can include powering the seventh inverter during the power gating period.

Stage305can include generating a control signal that is a clock signal, wherein that clock signal is gated during the power gating period.

Stage305can include generating control signals such as an inverted power gating signal.

Stage310includes storing at the retention latch of a dual edge triggered (DET) flip-flop, immediately before a power gating period starts, a first initial value.

Stage320includes storing, at a second latch of a dual edge triggered flip-flop, immediately before a power gating period starts, a second initial value.

Stages310and320are followed by stage330of receiving a power gating signal indicative of a start of a power gating period.

Stage340includes powering, during the power gating period first and second inverters of the retention latch and preventing power from third and fourth inverters of the second latch during the power gating period. It is noted that the power can be prevented only after the third transfer gate transfers an initial value from the retention latch to the second latch or from the second latch to the retention latch.

Stage345includes determining if a control criterion is fulfilled. This involves checking the value of at least one control signal at the beginning of the power gating period.

Referring to the example set fourth inFIG. 2, the control criteria is fulfilled if at the beginning of the power gating period CPP is high. CPP is generated by applying an AND operation of on a clock signal CLK and a power gating signal PD. This can be achieved by applying a NAND operation and then inverting the outcome of the NAND operation.

Stage345is followed by stage350of sending (if a control criterion is fulfilled) the second initial value to the retention latch via a third transfer gate. If, for example the control criteria is fulfilled than at the beginning of the power gating mode and during an intermediate period—the retention latch is “not storing” (as its feedback loop is open) while the feedback loop of the second latch is closed and it latches the second initial value. Accordingly—when the third transfer gate is open the second initial value is written to the retention latch. At the end of the intermediate period the clock signal is low and the retention latch latches the second initial value.

Else, stage345is followed by stage355. Stage355includes storing at the retention latch the first initial value. If, for example the control criteria is not fulfilled than at the beginning of the power gating mode and during an intermediate period—the second latch is “not storing” (as its feedback loop is open) while the feedback loop of the retention latch is closed so that the retention latch latches the first initial value.

Accordingly, if the control criteria is fulfilled the retention value equals the second initial value and if not it equals the first initial value.

Stage365can include closing, during the power gating period, transfer gates connected before and, additionally or alternatively, after the retention latch or the second latch. For example, stage365can include closing a fourth transfer gate that has an input that is connected to an input node of the dual edge triggered flip flop.

Stage355is followed by stage370of storing, at the retention latch, at an end of the power gating period a retention value.

Stage350is followed by stage375of closing the third transfer gate after an intermediate period ends. The clock signal CLK is low (its driver is powered by the gated power supply) at the end of the intermediate period so that CPP is also low at the end of the intermediate period. This reduces the leakage from the dual edge triggered flip flop. Stage375is followed by stage370.

Stages370and385are followed by stage377of receiving a power gating period indicative that the power gating period ended.

Stage377is followed by stage380of outputting the retention value after the power gating period ends.

Method301can be implemented by device11. For example, the retention value can equal the first initial value if the control signal is low when the power gating period starts; and the retention value can equal the second initial value if the control signal is high when the power gating period starts.

Method301can also include stage305of generating control signals that control the DET flip-flop. Stage305can include, for example, generating control signals that are responsive to a clock signal and to a power gating signal. For example, it can include generating, from clock signal and power gating signal PD the following control signals: CPP, CPPN, CP, CPN, CNPN and CNP. At least some of these signals can be providing during the power gating period and stage340can include powering, during the power gating period, a circuit logic that generates these control signals.

Stage385includes providing, during the power gating period, a reference signal (that can be a pull down signal) of a fixed value to outputs of transfer gates that are connected to output nodes of the retention latch and the second latch. This can reduce leakage through gates of transistors of these latches.

Any reference herein and before to a logic signal level “1”, “high”, “H” or “set” means logic high level, while any reference to a signal logic level “0”, “low”, “L” or “reset” means logic low level. Conventionally, logic high level corresponds to a level equal (or close within some tolerance) to continuous power supply voltage, while logic low level corresponds to a level equal (or close within some tolerance) to the ground voltage. Conventionally, during the power down period the gated power supply reaches the logic low level due to e.g. gated circuit leakage or special pull-down mechanisms.

In addition, the invention is not limited to physical devices or units implemented in non-programmable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code. Furthermore, the devices may be physically distributed over a number of apparatuses, while functionally operating as a single device.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps from those listed in a claim. Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.