Inverted MOSFET with scaling advantage

After forming a gate structure wrapping around a suspended channel portion of a semiconductor fin located on an insulator layer, a gate cap is formed atop the gate structure. Portions of an interlevel dielectric (ILD) layer laterally surrounding the gate structure and the gate cap are then removed to form source/drain contact openings. Epitaxial source/drain regions are subsequently grown from surfaces of the semiconductor fin exposed by the source/drain contact opening. Next, source/drain contact structures are formed on top of the epitaxial source/drain regions. Entire sidewalls of the source/drain contact structure are in contact with the gate cap.

BACKGROUND

The present application relates to semiconductor device fabrication, and more particularly to formation of metal-oxide-semiconductor field effect transistors (MOSFETs) with improved scaling and reduced parasitic capacitance.

In the semiconductor industry, there is a constant demand to increase the operating speed of integrated circuits (ICs). The demand for increased speed, in turn, has resulted in a continual size reduction of the semiconductor devices including field effect transistors (FETs). However, the aggressive scaling or size reduction of the FETs raises various technical issues relating to contact spacing and parasitic capacitance, namely gate-to-source/drain contact capacitance, which need to be addressed in order to meet the requirements for both device performance and manufacturing yield.

SUMMARY

The present application provides an inverted MOSFET with improved scaling and reduced parasitic capacitance. The inverted MOSFET includes a gate structure having a lower portion formed beneath a channel region of a semiconductor fin and an upper portion formed above the channel region, and a gate cap located on the gate structure. The height of the upper portion of the gate structure is selected such that the source/drain contact structures only contact the gate cap, but not the gate structure. Such a device structure allows minimization of overlap between the gate structure and source/drain contact structure, which leads to reduced parasitic capacitance.

According to an aspect of the present application, a semiconductor structure is provided. The semiconductor structure includes a semiconductor fin located over a substrate, a gate structure wrapping around a channel region of the semiconductor fin, a gate cap located on the gate structure, epitaxial source/drain regions located on portions of the semiconductor fin that laterally surround the channel region, and source/drain contact structures located on the epitaxial source/drain regions. Entire sidewalls of the source/drain contact structures are in contact with sidewalls of the gate cap.

According to another aspect of the present application, a method of forming a semiconductor structure is provided. The method includes first forming an interlevel dielectric (ILD) layer over a semiconductor fin located on a substrate. A gate trench is then formed extending through the ILD layer and into the substrate such that a channel region of the semiconductor fin is suspended in the gate trench. After forming a gate structure within the gate trench and wrapping around the channel region of the semiconductor fin, a gate cap is formed on the gate structure and within the gate trench. Source/drain contact openings are then formed extending through the ILD layer to expose portions of the semiconductor fin on opposite sides of the gate structure. After forming epitaxial source/drain regions on the exposed portions of the semiconductor fin, source/drain contract structures are formed on the epitaxial source/drain regions and within the source/drain contact opening. Entire sidewalls of the source/drain contact structures are in contact with sidewalls of the gate cap.

DETAILED DESCRIPTION

Referring toFIGS. 1A and 1B, an exemplary semiconductor structure according to an embodiment of the present application is provided. The semiconductor structure includes a semiconductor-on-insulator (SOI) substrate8and a dielectric cap layer16formed over the SOI substrate8. As shown inFIG. 1B, the SOI substrate8includes, from bottom to top, a handle substrate10, a buried insulator layer12and a top semiconductor layer14.

The handle substrate10may include a semiconductor material, such as, for example, silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), an III-V compound semiconductor, an II-VI compound semiconductor, or any combinations thereof. Multilayers of semiconductor materials can also be used as the semiconductor material of the handle substrate10. In one embodiment, the handle substrate10is composed of single crystalline silicon. The thickness of the handle substrate10can be from 50 μm to 2 mm, although lesser and greater thicknesses can also be employed.

The buried insulator layer12that is formed on the handle substrate10may include a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, or a combination thereof. The buried insulator layer12may be formed using a deposition process including, but not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition CVD (PECVD), or physical vapor deposition (PVD). Alternatively, the buried insulator layer12may be formed by thermal nitridation and/or thermal oxidation of a surface portion of the handle substrate10. The buried insulator layer12may also be formed by implanting oxygen atoms into a bulk semiconductor substrate and thereafter annealing the structure. The thickness of the buried insulator layer12can be from 100 nm to 300 nm, although lesser and greater thicknesses can also be employed.

The top semiconductor layer14may include any semiconductor material as mentioned above for the handle substrate10. Exemplary semiconductor materials that can be employed as the top semiconductor layer include, but are not limited to, Si, Ge, SiGe, SiC, and SiGeC, and III/V compound semiconductors such as, for example, InAs, GaAs, and InP. The semiconductor materials of the top semiconductor layer14and the handle substrate10may be the same or different. In one embodiment, the top semiconductor layer14includes single crystalline silicon. The top semiconductor layer14may be formed by CVD or PECVD. The thickness of the top semiconductor layer14can be from 20 nm to 50 nm, although lesser or greater thicknesses can also be employed. Alternatively, the top semiconductor layer14may be formed using a Smart Cut process where two semiconductor wafers are bonded together with an insulator in between.

The dielectric cap layer16that is formed on the top semiconductor layer14may include a dielectric material such as, for example, silicon dioxide, silicon nitride, silicon oxynitride, a dielectric metal oxide, or a combination thereof. In one embodiment, the dielectric cap layer16is composed of silicon dioxide. The dielectric cap layer16may be formed by a deposition process including CVD, PECVD, or PVD, or by a thermal growing process such as thermal oxidation or thermal nitridation. The thickness of the dielectric cap layer16can be from 5 nm to 20 nm, although lesser and greater thicknesses can also be employed. The dielectric cap layer16is optional and can be omitted in some embodiments of the present application.

Referring now toFIGS. 2A and 2B, there are illustrated the exemplary semiconductor structure ofFIGS. 1A and 1Bafter forming a plurality of fin stacks on the buried insulator layer12. Each fin stack includes a semiconductor fin18and a fin cap20atop the semiconductor fin18.

The fin stacks (18,20) can be formed by patterning the dielectric cap layer16and the top semiconductor layer14. For example, a photoresist layer (not shown) can be applied over a top surface of the dielectric cap layer16and lithographically patterned to provide a patterned photoresist layer atop portions of the dielectric cap layer16. Portions of the dielectric cap layer16that are not covered by the patterned photoresist layer are subsequently removed by an anisotropic etch, exposing portions of the top semiconductor layer14. The anisotropic etch can be a dry etch such as, for example, reactive ion etch (RIE) or a wet etch including a chemical etchant that removes the dielectric material of the dielectric cap layer16selective to the semiconductor material of the top semiconductor layer14. Remaining portions of the dielectric cap layer after the lithographic patterning constitute the fin caps20. Another anisotropic etch is then performed to remove the exposed portions of the top semiconductor layer14utilizing the fin caps20as an etch mask. Remaining portions of the top semiconductor layer14after the lithographic patterning constitute the semiconductor fins20. After transferring the pattern in the photoresist layer into the dielectric cap layer16and the top semiconductor layer14, the patterned photoresist layer can be removed utilizing a conventional resist stripping process such as, for example, ashing. Other methods known in the art, such as sidewall image transfer (SIT) or directional self-assembly (DSA), can also be used to pattern the dielectric cap layer16and the top semiconductor layer14.

Referring now toFIGS. 3A and 3B, there are illustrated the exemplary semiconductor structure ofFIGS. 2A and 2Bafter forming an interlevel dielectric (ILD) layer30over the buried insulator layer12and fin stacks (18,20). The ILD layer30includes a dielectric material that is self-planarizing or can be planarized, for example, by chemical mechanical polishing (CMP). For example, the ILD layer30may include silicon dioxide, silicon nitride, silicon oxynitride or organosilicate glass (OSG). The ILD layer30may be formed, for example, by CVD, ALD, PVD, or spin coating. The ILD layer30is deposited to a thickness such that an entirety of the top surface of the ILD layer30is formed above the top surfaces of the fin caps20. In one embodiment, the thickness of the ILD layer30can be from 100 nm to 200 nm, although lesser and greater thicknesses can also be employed.

Referring now toFIGS. 4A-4C, there are illustrated the exemplary semiconductor structure ofFIGS. 3A and 3Bafter forming gate trenches32extending through the ILD layer30and the fin caps20and into the buried insulator layer12. A channel region18C of each semiconductor fin18is suspended within a respective gate trench32. A distance between a bottom surface of each gate trench32and the bottom surface of the channel region18C of each semiconductor fin18can be from 20 nm to 30 nm, although lesser and greater distances can also be employed.

The gate trenches32can be formed by lithography and etching. The lithographic process includes forming a photoresist layer (not shown) over the ILD layer30, exposing the photoresist layer to a desired pattern of radiation and developing the exposed photoresist layer utilizing a conventional resist developer. An anisotropic etch is then performed to remove portions of the ILD layer30, the fin caps20and the buried insulator layer12that are not covered by the patterned photoresist layer. The anisotropic etch can be a dry etch, such as, for example, RIE or a wet chemical etch that removes the dielectric materials of the ILD layer30, the fin caps20and the buried insulator layer12selective to the semiconductor material of the semiconductor fins18. The exposed portions of the buried insulator layer12thus are recessed relative to the top surface of the buried insulator layer12.

Subsequently, a portion of the buried insulator layer12beneath a channel region18C of each semiconductor fin20exposed by a respective gate trench32is removed. A ‘short’ isotropic etch can be performed to undercut the buried insulator layer12from beneath each side of the channel regions18C. By ‘short’ it is meant that the etch is performed for a time period of 60 seconds or less depending on the concentration of the etchant used. In one embodiment and when the semiconductor fins18are composed of silicon and the buried insulator layer12is composed of silicon dioxide, a buffered oxide etch comprising hydrogen fluoride (HF) can be utilized. In the present application, and since the fin width is small, a slight undercut (about ½ fin width) ensures complete removal of the portion of the buried insulator layer12beneath each channel region18C of the semiconductor fins18. The channel regions18C of the semiconductor fins18are thus suspended in the gate trench32. After formation of gate trenches32, the patterned photoresist layer can be removed, for example, by ashing.

Referring now toFIGS. 5A-5C, there are illustrated the exemplary semiconductor structure ofFIGS. 4A-4Cafter forming a gate dielectric layer portion34directly on the bottom surface and sidewall surfaces of a respective gate trench32as well as on sidewall surfaces, a top surface and a bottom surface of a channel region18C of each semiconductor fin18and forming a gate electrode layer portion36on the gate dielectric layer portion34.

The gate dielectric layer portion34may include a high-k dielectric material having a dielectric constant greater than silicon dioxide. Exemplary high-k dielectric materials include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. In some embodiments, the gate dielectric layer portion34may have a multilayer structure comprising different gate dielectric materials, e.g. silicon dioxide, and a high-k gate dielectric material can be formed. The thickness of the gate dielectric layer portion34can be from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed.

The gate electrode layer portion36may include any conductive metal. Exemplary conductive metals that can be employed in the metal gate electrode layer include, but are not limited to, W, Ti, Ta, Al, Ni, Ru, Pd, and Pt. In one embodiment, the gate electrode layer portion36is comprised of W. In some embodiments of the present application, the gate electrode layer portion36also contains a work function metal such as, for example, TiAlN, TiN, or TaN.

The gate dielectric layer portion34and the gate electrode layer portion36can be formed by forming a conformal gate dielectric layer (not shown) on exposed surfaces of the gate trenches32, the semiconductor fins18and the ILD layer30and subsequently forming a gate electrode layer (not shown) on the gate dielectric layer to completely fill the gate trenches32. Each of the gate dielectric layer and gate electrode layer can be formed, for example, by CVD, PECVD, PVD, or ALD. After deposition of the gate electrode layer and the gate dielectric layer, a planarization process such as, for example, CMP, may be performed to remove portions of the gate dielectric layer and the gate electrode layer from above the top surface of the ILD layer30. A remaining portion of the gate dielectric layer within a respective gate trench32constitutes the gate dielectric layer portion34, while a remaining portion of the gate electrode layer within a respective gate trench32constitutes the gate electrode layer portion36. The top surfaces of the gate electrode layer portion36and the gate dielectric layer portion34are coplanar with the top surface of the ILD layer30.

Referring now toFIGS. 6A-6C, there are illustrated the exemplary semiconductor structure ofFIGS. 5A-5Cafter forming a gate structure within each gate trench32and wrapping around a channel region18C of each semiconductor fin18, and forming a gate cap38atop the gate structure. Each gate structure includes a gate dielectric34P located on exposed surfaces of the semiconductor fins18and a gate electrode36P located over the gate dielectric34P. Each gate structure (34P,36P) includes an upper portion located atop a channel regions18C of each semiconductor fin18, and a lower portion located within the buried insulator layer12and in direct contact with a bottom surface of the channel regions18C of each semiconductor fin18. The height of the upper portion of each gate structure (34P,36P) is typically less than 10 nm. In one embodiment, the top surface of the upper portion of each gate structure (32P,34P) is coplanar with the top surface of each fin cap20.

The gate structures (34P,36P) can be formed by first recessing the gate electrode layer portion36below the top surface of the ILD layer30by an etch. The etch can be a dry etch or a wet etch that removes the conductive metal that provides the gate electrode portion36selective to the dielectric materials that provide the gate dielectric layer portion34and the ILD layer30. A remaining portion of the gate electrode portion36located within a respective gate trench32constitutes the gate electrode36P. The gate electrode layer portion36may be recessed until a top surface of each gate electrode36P is coplanar with, or below, the top surface of each fin cap20. In one embodiment and as shown, the top surface of each gate electrode36P is coplanar with the top surface of each fin cap20.

Next, vertical portions of the gate dielectric layer portion34are recessed selective to the ILD layer30. The recessed of the gate dielectric layer portion34can be performed by any suitable etching techniques known in the art. In one embodiment and when the gate dielectric layer portion34is composed of HfO2, the gate dielectric layer portion34may be recessed by a dry etch including N2, H2and CF3or a chemical wet etch utilizing an HF etchant. A remaining portion of the gate dielectric portion34located within a respective gate trench32constitutes the gate dielectric34P. Within each gate trench32, the top surface of the gate dielectric34P is coplanar with the top surface of the gate electrode36P and a void is formed on top of the gate dielectric34P and gate electrode36P.

A dielectric material is then deposited over gate dielectric34P and gate electrode36P within each gate trench32to completely fill each void. The deposition of the dielectric material can be performed utilizing a deposition process such as, for example, CVD or PECVD. The deposited dielectric material is then planarized, for example, by CMP using the top surface of the ILD layer30as an etch stop to form the gate cap38. Each gate cap38thus can have a top surface coplanar with the top surface of the ILD layer30. Exemplary dielectric materials that can be employed in the gate cap38include, but are not limited to, silicon nitride, SiCN, and SiBCN.

Referring now toFIGS. 7A-7C, there are illustrated the exemplary semiconductor structure ofFIGS. 6A-6Cafter forming source/drain contact openings40extending through the ILD layer30and the fin caps20. The source/drain contact openings40expose sidewalls of the gate structures (34P,36P) and portions of the semiconductor fins18located on opposite sides of the gate structures (34P,36P). The source/drain contact openings40can be formed by applying a photoresist layer (not shown) over the ILD layer30and the gate caps38and then lithographically patterning the photoresist layer to form openings therein. The openings expose portions of the ILD layer30located on opposite sides of the gate caps38. The physically exposed portions of the ILD layer30and underlying portions of fin caps20are subsequently removed by at least one etch. The at least one etch can be a dry etch or a wet etch that removes the dielectric materials that provide the ILD layer30and fin caps20selective to the dielectric materials that provides the gate caps38and the gate dielectrics34P as well as the semiconductor material that provides the semiconductor fins18. In one embodiment, multiple RIE may be performed. After forming the source/drain contact openings40, the patterned photoresist layer can be removed, for example, by ashing.

Referring now toFIGS. 8A-8C, there are illustrated the exemplary semiconductor structure ofFIGS. 7A-7Cafter growing an epitaxial source region and an epitaxial drain region (collectively referred to as epitaxial source/drain regions42) from top and sidewall surfaces of physically exposed portions of semiconductor fins18located on opposite sides of each gate structure (34P,36P). The epitaxial source/drain regions42may include any semiconductor material as mentioned above for the semiconductor fins18. In one embodiment of the present application, the epitaxial source/drain regions42include a semiconductor material the same as the semiconductor material that provides the semiconductor fins18. For example, both the epitaxial source/drain regions42and the semiconductor fins18may be composed of silicon. In another embodiment of the present application, the epitaxial source/drain regions42include a semiconductor material different from the semiconductor material that provides the semiconductor fins18. For example, the epitaxial source/drain regions42may be composed of SiGe and the semiconductor fins18may be composed of silicon.

The epitaxial source/drain regions42also contain p-type or n-type dopants. The term “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. Examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium and indium. “N-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. Examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic and phosphorous. The dopant concentration of the epitaxial source/drain regions42can be from 1×1020atoms/cm3to 1×1022atoms/cm3, although lesser and greater dopant concentration can also be employed.

The epitaxial source/drain regions42may be formed by a selective epitaxial growth process. The selective epitaxial growth process grows the semiconductor material that provides epitaxial source/drain regions42only from the semiconductor surfaces (i.e., exposed top and sidewall surfaces of the semiconductor fins18), but not from dielectric surfaces, such as surfaces of the ILD layer30, the gate caps38, the fin caps20and gate dielectrics34P. Examples of various epitaxial growth processes that are suitable for use in forming the epitaxial source/drain regions42include, but are not limited to, molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD). The dopants can be provided during selective epitaxial growth process by in-situ doping, or after selective epitaxial growth process by ion implantation or gas phase doping. In one embodiment and as shown, the selective epitaxial growth process can be continued until the epitaxial source/drain regions42merge neighboring semiconductor fins18. After epitaxial growth, the top surfaces of epitaxial source/drain regions42are located above the bottom surfaces of the gate caps38.

The dopants in the epitaxial source/drain regions42can be activated for example, by a rapid thermal anneal process. In some embodiments of the present application, the annealing may result in a diffusion of dopants from the epitaxial source/drain regions42into the portions of the semiconductor fins20underlying the epitaxial source/drain regions42. Doped fin regions18D thus are formed within portions of the semiconductor fins18that are not covered by the gate structures (34P,36P) to laterally surround the channel region18C. Collectively, the doped fin region18D and the doped epitaxial semiconductor region40constitute source/drain regions for FETs.

Referring now toFIGS. 9A-9C, there are illustrated the exemplary semiconductor structure ofFIGS. 8A-8Cafter forming source/drain contact structures50over the epitaxial source/drain regions42to completely fill the source/drain contract openings40. The source/drain contract structures50can be formed by deposition of a conductive material (e.g., tungsten) into the source/drain contract openings40and on the top surfaces of the ILD layer30and gate caps38and by planarization to remove excess portions of the deposited conductive material from above the top surfaces of the ILD layer30and the gate caps38. Optionally, contact liners (not shown) may be formed on the sidewalls the source/drain contact openings40and on the top surfaces of the epitaxial source/drain regions42before filling the source/drain contact openings40with the conductive material. In one embodiment, the contact liners may include titanium.

Since only a minor portion of the gate structure (34P,36P) is present on top of the semiconductor fin18, the source/drain contact structures50can only form direct contact with the gate cap38, but not with the gate structure (34P,36). The overlap between the gate structure (34P,26P) and the source/drain contact structures50is eliminated. As a result, the parasitic capacitance between gate structure and source/drain contact structures can be minimized. In additional, since dielectric spacers are no longer needed in the present application to separate gate structures (34P,36P) from the source/drain contact structures50as is typically the case with prior art structures, a significant area saving can result, and improved FET scaling can be obtained.

Referring now toFIGS. 10A-10C, there are illustrated the exemplary semiconductor structure ofFIGS. 9A-9Cafter forming gate contract structures60. Each gate contract structure60extends through a gate cap38to form direct contract with the gate electrode34P in a respective gate structure (34P,36P). The gate contract structures60can be formed by formation of gate contact openings (not shown) through the gate caps38utilizing a combination of lithographic patterning and anisotropic etch followed by deposition of a conductive material (e.g., tungsten) and planarization that removes excessed portions of the conductive material from above the top surfaces of the ILD layer30and the gate caps38. In some embodiments of the present application, contact liners (not shown) may also be formed on sidewalls and bottom surfaces of the gate contact openings before deposition of the conductive material.

While the methods and structures disclosed herein have been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the methods and structures disclosed herein not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.