Method of forming shallow trench isolation with chamfered corners

A method of forming shallow trench isolation with chamfered corners. First, a pad insulating layer, a first mask layer, and a second mask layer are sequentially formed on a substrate. The second mask layer, the first mask layer, and the pad insulating layer are patterned to form an opening exposing a portion of the substrate. Next, the substrate is etched using the patterned second mask layer as a mask to form a trench therein. Next, part of the second mask layer is removed to expose the first mask layer adjacent to the trench and result in the second mask layer having a tapered profile. Finally, the second mask layer, the first mask layer, the pad insulating layer, and the substrate are etched along the tapered profile of the second mask layer to chamfer corners of the trench.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a process of forming shallow trench isolation. More particularly, the present invention relates to a manufacturing method of forming shallow trench isolation with chamfered corners.

2. Description of the Related Art

Recently, as the manufacturing techniques of semiconductor integrated circuits develop, the number of devices in a chip has increased. The size of the device also decreases as the degree of integration increases. The line width used in manufacturing, lines has decreased from sub-micron to quarter-micron, or even smaller. Regardless of the reduction of the size of the device, adequate insulation or isolation must be provided among individual devices in the chip so that good element characteristics can be achieved. This technique is called device isolation technology. The main object is to form an isolation region, reducing the size of the isolation as much as possible while assuring good isolation effect to allow larger chip space for more devices.

Among different device isolation techniques, LOCOS and shallow trench isolation region manufacturing methods are the two most used methods. In particular, as the latter has a small isolation region and can keep the substrate level after the process is finished, it is the semiconductor manufacturing method obtaining the most attention.

The conventional manufacturing method for a shallow trench isolation region comprises forming a dielectric layer to fill a trench on a substrate by chemical vapor deposition (CVD), and etching back the dielectric layer on the substrate to remove the redundant dielectric layer. However, as the density of the semiconductor integrated circuits increases and the size of the elements decreases, the above mentioned deposition experiences problems in step coverage and cannot completely fill the trench. This influences the isolation effect among elements.

As a result of filling the entire trench which has a high aspect ratio, recently, high-density plasma chemical vapor deposition (HDPCVD) is used to form a dielectric layer on the substrate instead of CVD. In HDPCVD, the dielectric layer is deposited using O2and SiH4gases.

FIGS. 1A-1Cshow a conventional fabrication process of a shallow trench isolation. InFIG. 1A, a pad oxide layer12is deposited on a substrate10such as Si substrate, wherein the thickness of the pad oxide layer12is about 50-200 Å. The pad oxide layer12is formed using thermal oxidation or CVD. Thereafter, a silicon nitride layer14is deposited on the pad oxide layer12using CVD, and the thickness of the silicon oxide layer14is 500-2000 Å. A mask layer thereby consists of the pad oxide layer12and the silicon nitride layer14. Next, a patterned photoresist layer13is defined on the silicon nitride layer14and the pad oxide layer12using photolithography and etching techniques to expose a portion of the substrate10where the shallow trench isolation is formed.

Next. InFIG. 1B, the exposed portion of the substrate10is etched using the silicon nitride layer14and the pad oxide layer12as a mask to form a trench15, and the depth of the trench15is about 3500-5000 Å. Then, a thin liner layer16is formed on the sidewall of the trench15using thermal oxidation process, and the thickness of the liner layer16D is 180 Å.

As shown inFIG. 1C, in HDPCVD, a dielectric layer18is deposited and fills the trench15, wherein O2and SiH4are reactants.

As shown inFIG. 2, due to the opening of the trench narrowing and/or the aspect ratio of the trench increasing, for example the opening width may be less than 0.11 μm and/or the aspect ratio larger than 4, the dielectric layer18deposited on the silicon nitride layer14may cover the opening of the trench15in the HDPCVD process, such that the dielectric layer18cannot fill the trench15completely and a void20is formed in the trench, resulting in poor insulation quality of the shallow trench isolation region.

Because the properties of the dielectric layer18are similar to those of the pad oxide layer12, when etchant is used to dip pad oxide layer12, the shallow trench isolation region28is inevitably etched so that the corner22of the trench15is exposed and an indentation30is formed adjacent to the corner22of the trench15.

Thus, when the gate oxide layer and gate conductive layer are formed later, the conductive layer deposited in the indentation30is not easily removed and a short circuit between the adjacent transistors easily occurs. In addition, since the gate oxide layer at the corner22of the the trench15is thinner than other places, a parasitic transistor is formed. When current goes through this parasitic transistor, as the curvature radius of the corner22of the trench15is small, the electric fields concentrate and the Fowler-Nordheim current increases, hence the insulating property of the gate oxide layer of the corner22degrades, resulting in abnormal element characteristics. For example, there may be a kink effect in I-V curvature of Id and Vg, which generates a double hump.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a method of forming shallow trench isolation with chamfered corners to promote isolation among elements and avoid voids by increasing the gap-filling ability of the shallow trench isolation with improved corner configuration when the dielectric layer is filled thereinto.

Moreover, the present invention provides a manufacturing method, which avoids forming a trench isolation region of parasitic transistors at the corner of the trench.

Furthermore, the present invention provides a manufacturing method of forming a trench isolation region, which avoids short circuit between adjacent transistors.

To achieve the above mentioned objects, the method of forming shallow trench, isolation with chamfered corners according to the present invention includes the following steps. First, a pad insulating layer, a first mask layer, and a second mask layer are sequentially formed on a substrate. The second mask layer, the first mask layer, and the pad insulating layer are patterned to form an opening exposing a portion of the substrate. Next, the substrate is etched using the patterned second mask layer as a mask to form a trench therein. Next, part of the second mask layer is removed to expose the first mask layer adjacent to the trench and result in the second mask layer having a tapered profile. Finally, the second mask layer, the first mask layer, the pad insulating layer, and the substrate are etched along the tapered profile of the second mask layer to chamfer corners of the trench.

One aspect of the invention, before the insulator layer is formed, further comprises forming a shield layer on the surface of the substrate, the trench, and the chamfered corners.

In the present invention, after chamfering the corners of the trench, the method of forming shallow trench isolation with chamfered corners according to the present invention further comprises the following steps. The second mask layer is completely removed. The first mask layer and the pad insulating layer are etched to remove a predetermined width thereof to expose a portion of the substrate adjacent to the trench. An insulator layer is blanketly formed on the exposed surface of the substrate and the chamfered corners thereof to fill the trench. The first mask layer and the pad insulating layer are removed to form the trench isolation region.

Another aspect of the invention, before the insulator layer is formed, further comprises forming a lining oxide layer on the surface of the substrate, the trench, and the chamfered corners.

The present invention also provides another method of forming shallow trench isolation with chamfered corners, including the following steps. First, a pad insulating layer, a first mask layer, and a second mask layer are sequentially formed on a semiconductor substrate. Then, the second mask layer, the first mask layer, and the pad insulating layer are patterned to form an opening exposing a portion of the semiconductor substrate. Next, the semiconductor substrate is etched using the patterned second mask layer as a mask to form a trench therein. Next, part of the second mask layer is removed to expose the first mask layer adjacent to the trench and result in the second mask layer having a tapered profile. Next, the second mask layer, the first mask layer, the pad insulating layer, and the substrate are etched along the tapered profile of the second mask layer to chamfer corners of the trench. Furthermore, the second mask layer is completely removed. A shield layer is formed on the surface of the substrate, the trench, and the chamfered corners. An insulator layer is blanketly formed on the shield layer to fill the trench. Finally, the first mask layer and the pad insulating layer are removed to form the trench isolation region.

According to another aspect of the invention, the method of the present invention further comprises, after removing the second mask layer, etching the first mask layer and the pad insulating layer to remove a predetermined width thereof and expose a portion of the semiconductor substrate adjacent to the trench.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 4Ato4J are cross sections of the manufacturing process of a shallow trench isolation region with chamfered corners in accordance with the present invention.

First, referring toFIG. 4A, a semiconductor substrate100, for example silicon substrate, is provided. Herein, use of the term substrate includes devices formed within a semiconductor wafer and the layers overlying the wafer. Next, a pad insulation layer102, a first mask layer104and a second mask layer106are formed sequentially on the surface of the semiconductor substrate100. Preferably, the pad insulation layer102such as pad oxide layer with a thickness of 50 Å to 200 Å is formed using thermal oxidation at 850-950° C., APCVD, or LPCVD. The first mask layer104such as silicon nitride with a thickness of 5000 Å to 2000 Å is formed using LPCVD at 750-800° C., wherein SiCl2H2and NH3are reactants. As well, the first mask layer104may also be silicon oxy-nitride formed by LPCVD, wherein SiH4, N2O, and NH3are reactants.

Suitable material for the second mask layer106is silicide such as boro phosphor silicate glass (BPSG), phosphor silicate glass (PSG), boro silicate glass (BSG), and arsenic silicate glass (AsSG). Preferably, the second mask layer106, of BSG with a thickness of 1000 Å to 4000 Å is formed by LPCVD, wherein SiH4, BF3, and B2H6are reactants.

Subsequently, a patterned photoresist (PR) layer (not shown inFIG. 4A) is coated on the surface of the second mask layer106, and photolithography performed to define the photoresist pattern required. Moreover, the second mask layer108, the first mask layer104, and the pad insulating layer102are etched anisotropically (for example reactive ion etching), with the patterned photoresist acting as a mask.

Furthermore, the patterned photoresist layer is used as a mask to anisotropically etch the second mask layer106, the first mask layer104, and the pad insulating layer102, for example reactant ion etching, to transfer the pattern of the photoresist layer to the second mask layer106, the first mask layer104, and the pad insulating layer102to form opening103, such-that the semiconductor substrate100in the opening103is exposed, and the size of the opening103is substantially that of the isolation region. Then, suitable solution or dry etching is performed to remove the photoresist layer.

Subsequently, referring toFIG. 4B, the patterned second mask layer106is used as a mask to anisotropically etch semiconductor substrate100, for example reactant ion etching, and a trench105with a depth120of 1800 Å to 2400 Å is formed.

Subsequently, referring toFIG. 4C, a wet treatment is then performed. The wet treatment includes using etchant, such as a solution of ammonium hydrogen peroxide mixture (APM), to etch both sides of the second mask layer106adjacent to the opening103. After etching, part of the second mask layer106adjacent to the opening103with a width between 150-250 Å is removed and the second mask layer106with tapered profiles108adjacent to the opening103is formed. Preferably, the ratio of NH4OH:H2O2:deionized water (DIW) is about 1:1:5 and the etching temperature is 60° C. or higher.

Subsequently, referring toFIG. 4D, anisotropic etching, for example RIE, is performed along the tapered profiles108of the second mask layer106to remove part of the second mask layer106, the first mask layer104, the pad insulating layer102, and the semiconductor substrate100around the trenches105. Then, the corners of the trench105are chamfered, and Y-shaped trench105ais further formed. The depth120a(for example, between 2700-3800 Å) of the Y-shaped trench105ais deeper than that of the original trench105, and the aspect ratio of the Y-shaped trench is between 4-6.

Subsequently, referring toFIG. 4E, the second mask layer106is completely removed by appropriate etching, for example, wet treatment with buffered hydrofluoric acid as etchant to etch the second mask layer106composed of BSG. Next, wet treatment etches both sides of the first mask layer-104and the pad insulating layer102adjacent to the trench105auntil a width between 50-300 Å thereof is removed, as shown in FIG.4F. Preferably, a hydrofluoric acid/ethylene glycol mix (HF/EG) etches the first mask layer104and the pad insulating layer102.

Subsequently, referring toFIG. 4G, a thermal oxidation process is performed to grow a shield layer116such as a liner oxide layer with a thickness of 50 Å to 350 Å in the bottom, sidewall, and chamfered corners of the trench105aand the surface117of the substrate100.

Subsequently, referring toFIG. 4H, an insulator layer118, such as a silicon dioxide layer, with a thickness of 3000-5000 Å is formed on the shield layer116by HDPCVD using O2and SiH4as reactants with Ar sputtering. Finally, referring toFIG. 41, chemical mechanical polishing removes uneven insulator layer118to cover the shield layer116and leave the insulator layer118inside the trench105a. The fist mask layer104and the pad insulating layer102are then removed using adequate liquid or etching to expose the element region, as shown in FIG.4J. Accordingly, the shallow trench isolation region150of the present invention is achieved. Preferably, the fat mask layer104is removed by, for example, a hot phosphoric acid solution and the pad insulating layer102is removed by, for example, a HF solution.

Compared to the prior art, the manufacturing method of forming shallow trench isolation with chamfered corners in the present invention has several advantages.

First, the present invention prevents void in the high aspect ratio shallow trench isolation region to promote the insulation quality thereof. Particularly, the method according the present invention can be used to fill the trench having aspect ratio exceeding 6 with insulator layer by HDPCVD.

Second, the corners of the trench in the present invention are already chamfered and thickness of the shield layer subsequently formed in this region is the same as in the other regions, thus no parasitic transistors will form and problems with the parasitic transistors will not occur, so the method in the present invention avoids short circuit between adjacent transistors.

Since the corner of the trench of the present invention is already chamfered, the conductive material subsequently formed in this region has no space blockage and is easily removed, thus preventing short circuit between the adjacent transistors. Therefore, the shallow trench isolation region of the invention has good electrical insulation.