Field effect transistor

A method of forming a field effect transistor (FET) includes providing a substrate; forming an nFET source/drain region on the substrate; forming a pFET source/drain region on the substrate and adjacent to the nFET region, the nFET source/drain region directly contacting the pFET source/drain region; forming a first insulator layer on the nFET source/drain region and the pFET source/drain region; etching away a portion of the first insulator layer between the nFET source/drain region and the pFET source/drain region down to a level of the substrate, thereby breaking the contact between the nFET source/drain region and the pFET source/drain region; and forming a second insulator layer between the nFET source/drain region and the pFET source/drain region in a space formed by the etching, the second insulator layer extending from the substrate to a top of the first insulator layer. The second insulator layer is harder than the first insulator layer.

BACKGROUND

The present disclosure relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present disclosure relates to fabrication methods and resulting structures for field effect transistors (FETs).

In certain semiconductor device fabrication processes, a large number of semiconductor devices, such as n-type field effect transistors (nFETs) and p-type field effect transistors (pFETs), may be fabricated on a single wafer. Non-planar transistor device architectures (e.g., fin-type FETs (FinFETs) and nanosheet FETs) can provide increased device density and increased performance over planar transistors. Other FET devices may have adjacent nFET and pFET regions, which may take up additional space. As semiconductor integrated circuits (ICs) and/or chips become smaller, it may be desirable to reduce the device footprint and increase the density of the devices.

SUMMARY

Embodiments of the present disclosure relate to a method of forming a field effect transistor (FET) device. The method includes providing a substrate; forming an nFET source/drain region on the substrate; forming a pFET source/drain region on the substrate and adjacent to the nFET region, the nFET source/drain region directly contacting the pFET source/drain region; forming a first insulator layer on the nFET source/drain region and the pFET source/drain region; etching away a portion of the first insulator layer between the nFET source/drain region and the pFET source/drain region down to a level of the substrate, thereby breaking the contact between the nFET source/drain region and the pFET source/drain region; and forming a second insulator layer between the nFET source/drain region and the pFET source/drain region in a space formed by the etching, the second insulator layer extending from the substrate to a top of the first insulator layer. A material of the second insulator layer is harder than a material of the first insulator layer.

Other embodiments relate to a field effect transistor (FET) device. The device includes a substrate; an nFET source/drain region formed on the substrate; a pFET source/drain region formed on the substrate and adjacent to the nFET region; a first insulator layer formed on sides of the nFET source/drain region and the pFET source/drain region; and a second insulator layer formed between the nFET source/drain region and the pFET source/drain region, the second insulator layer extending from the substrate to a top of the first insulator layer. A material of the second insulator layer is harder than a material of the first insulator layer.

DETAILED DESCRIPTION

The present disclosure describes FET devices and methods of manufacturing the FET devices. In particular, the present disclosure describes FET devices that are manufactured with a single cut (or etching operation) through the contact (CA) layer (or gate metal layer) and through the source/drain epitaxial region, which may allow for a reduction in the distance between the nFET side and the pFET side of the FET device. This may result in a decreased pitch and overall footprint of the device, which may allow for an increased density of the FET devices.

The flowcharts and cross-sectional diagrams in the Figures illustrate methods of manufacturing FET devices according to various embodiments. In some alternative implementations, the manufacturing steps may occur in a different order that that which is noted in the Figures, and certain additional manufacturing steps may be implemented between the steps noted in the Figures. Moreover, any of the layered structures depicted in the Figures may contain multiple sublayers.

Referring now to the drawings in which like numerals represent the same or similar elements and initially toFIG. 1A, a plan view of an example field effect transistor (FET) device100is shown at an intermediate stage of the manufacturing process. As shown inFIG. 1, a first epitaxial layer102is provided, and an nFET active region106is provided below the first epitaxial layer102. Also, a second epitaxial layer104is provided, and a pFET active region108is provided below the second epitaxial layer104. Gate electrodes110are provided that extend across the first epitaxial layer102and the second epitaxial layer104. Also, a nFET contact112is provided across the first epitaxial layer102and a pFET contact114is provided across the second epitaxial layer104. In order to reduce the footprint of the FET device100(in at least one dimension), it may be desirable to reduce the distance (i.e., indicated as N/P Distance onFIG. 1A) between the nFET active region106and the pFET active region108. InFIG. 1A, this distance is indicated as N/P Distance, and is equal to X1+2*X2, where X1 represents a distance between the nFET contact112and the pFET contact114, and where X2 represents a thickness of the respective epitaxial layer regions (i.e., the first epitaxial layer102and the second epitaxial layer104) around the active regions (i.e., the nFET active region106and the pFET active region108).

Referring not toFIG. 1B, a plan view of the FET device100ofFIG. 1Ais shown, according to embodiments. As shown inFIG. 1B, a cut mask115area is shown, and represents an area where the device will be etched at a given stage of the manufacturing process. It should be noted that inFIG. 1Bthe contact113is shown in a pre-cut (or pre-etched) state, whereas inFIG. 1A, the contact is already cut into an nFET contact112and a pFET contact114. InFIG. 2B, a smaller N/P Distance may be achieved relative to the device shown inFIG. 1Abecause X4<X2 and X3<X1. When the etching operation is applied to the FET device100using the cut mask115, each of the contact113, an interlayer dielectric (ILD) layer (see,FIG. 3BILD layer220), and the first and second epitaxial layers102and104are etched in a single manufacturing step. An etching composition may be suitably selected such that the contact113, the ILD and first and second epitaxial layers102and104may be etched with etching selectivity relative to the gate electrode hardmask (see,FIG. 2Agate hardmask208).

In certain embodiments, the dimension of X4 shown inFIG. 1Bis less than the dimension of X2 shown inFIG. 1Abecause the etching cut is not made as a line end. Also, the dimension of X3 shown inFIG. 1Bis less than the dimension of X1 shown inFIG. 1Abecause the first epitaxial layer102and the second epitaxial layer104are partially cut through (or removed). One effect of using a single cut mask115(i.e., rather than two or more) is that the contact113is self-aligned to the first epitaxial layer102and the second epitaxial layer104post etching operation. Another effect is that by using only one cut mask115(i.e., only one etching operation), the manufacturing efficiencies may be increased.

Referring now toFIGS. 2A-2Cand initially toFIG. 2A, this figure shows a plan view of a semiconductor FET device200at an intermediate stage of a semiconductor fabrication process flow, according to embodiments.FIG. 2Ashows the FET device200at, for example, after nFET and pFET epitaxial processes have been performed, and after a replacement metal gate (RMG) operation has been performed. As shown inFIG. 2B(which is a cross-sectional view of the semiconductor FET device ofFIG. 2Ataken along line B-B), a substrate210is provided and a shallow trench isolation (STI) region212can be formed between the nFET active region204(see,FIG. 2A) and the pFET active region206(see,FIG. 2A). The STI region212can separate the nFET source/drain region216(see,FIG. 2C, which is a cross-sectional view of the semiconductor FET device ofFIG. 2Ataken along line A-A) from the pFET source/drain region217(see,FIG. 2C). In certain embodiments, the pFET source/drain region includes a p-type work function (pWF) metal layer and the nFET source/drain region includes an n-type work function (nWF) metal layer. In general, shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components. STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. Referring again toFIG. 2B, a deposited layer202is provided over the STI region212and over the substrate210. The deposited layer202may be an oxide material or any other suitable material.

Referring now toFIG. 2B, this figure is a cross-sectional view of the semiconductor FET device ofFIG. 2Ataken along line B-B, according to embodiments. As shown inFIG. 2B, gate electrodes214are formed, and a gate hardmask208is formed over the gate electrodes214. The gate hardmask208is also shown inFIG. 2B. It should be appreciated that in certain embodiments, a chemical-mechanical planarization (CMP) process (or other planarization process) may be performed after the formation of the gate hardmask208and the deposited layer202such that the top surfaces of these layers are at least substantially coplanar. It is also understood that in certain cases the nFET source/drain216and the pFET source/drain217may be merged which is not shown inFIG. 2AandFIG. 2B.

As shown inFIG. 2B, the gate electrodes214are formed on the STI region212, which is formed into the substrate210. In certain embodiments, the gate hardmask208covers side surfaces and the top surface of the gate electrodes214. In certain embodiments, the gate hardmask208may include one or more nitride based materials.

Referring now toFIG. 2C, this figure is a cross-sectional view of the semiconductor FET device200ofFIG. 2Ataken along line A-A, according to embodiments. As shown in FIG.2C, the nitride liner layer209is formed to coat all exposed surfaces of the nFET source/drain region216and the pFET source/drain region217. As also shown inFIG. 2C, the STI regions212are formed between the nFET source/drain region216and the pFET source/drain region217. In certain embodiments, the nFET source/drain region216and the pFET source/drain region217are initially formed close to or in contact with each other. The close proximity or contact between the nFET source/drain region216and the pFET source/drain region217may allow for a smaller N/P Distance, as shown and described above with respect toFIG. 1B. This initial contact between the nFET source/drain region216and the pFET source/drain region217will be eliminated upon further processing steps, as described in further detail below.

Referring now toFIGS. 3A-3C, this figure is a plan view of the semiconductor FET device200ofFIG. 2Aafter additional fabrication operations, according to embodiments. As shown inFIGS. 3A-3C, an interlayer dielectric (ILD) layer220(or first insulator layer) is formed to cover the deposited layer202and the gate hardmask208. As indicated above,FIG. 3Bis a cross-sectional view of the semiconductor FET device ofFIG. 2Aafter additional fabrication operations and taken along line B-B, andFIG. 3Cis a cross-sectional view of the semiconductor FET device ofFIG. 2Aafter additional fabrication operations and taken along line A-A, according to embodiments. It should be appreciated that any suitable material or materials may be used for the ILD layer220.

Referring now toFIGS. 4A-4Cand initially toFIG. 4A, this figure is a plan view of the semiconductor FET device200ofFIG. 3Aafter additional fabrication operations, according to embodiments. As shown inFIG. 4A, an etching operation (or other suitable material removal process known to a person of skill in the art) is performed on the FET device200with a mask, and the material is removed in the cut mask area250. As shown inFIG. 4A, the material of both the ILD layer220and the deposited layer202is removed with a single mask and etch operation, thus exposing top surfaces of (or at least portions of the top surfaces of) the gate hardmask208and the underlying STI regions212. As shown inFIGS. 4A and 4B, three different gate electrodes214are exposed (more specifically, the gate hardmask208covering the gate electrodes214are exposed) during the etching process, and the further gate electrode to the right214is not exposed. However, it should be appreciated that this is merely one example, and different numbers of gates may be exposed (or not exposed) depending on the connection requirements between the different transistors. As indicated aboveFIG. 4Bis a cross-sectional view of the semiconductor FET device ofFIG. 3Aafter additional fabrication operations and taken along line B-B.

Referring now toFIG. 4C, this figure is a cross-sectional view of the semiconductor FET device200ofFIG. 3Aafter additional fabrication operations and taken along line A-A, according to embodiments. As shown inFIG. 4C, the etching operation also separates the nFET source/drain region216from the pFET source/drain region217. As discussed above with regard toFIG. 2C, the nFET source/drain region216and the pFET source/drain region217are initially formed close to or in contact with each other in order to minimize the N/P Distance (or X3+2*X4 shown inFIG. 1B) to decrease the device footprint and to increase the density of the transistor array. Thus, there may be an effect that only one etching operation is required to separate the nFET source/drain region216from the pFET source/drain region217, whereas related techniques may have the need to use additional cut masks and etching operations.

Referring now toFIGS. 5A-5Cand initially toFIG. 5Ais a plan view of the semiconductor FET device200ofFIG. 4Aafter additional fabrication operations, according to embodiments. InFIG. 5A, a hardened insulator layer222(or second insulator layer) is provided to fill in the areas removed in the etching step described above with respect toFIGS. 4A-4C.FIG. 5Bis a cross-sectional view of the semiconductor FET device ofFIG. 4Ataken along line B-B, andFIG. 5Cis a cross-sectional view of the semiconductor FET device ofFIG. 4Ataken along line A-A.FIGS. 5B and 5Calso show this hardened insulator layer222. As shown inFIG. 5C, the hardened insulator layer222now covers the previously exposed side surfaces of the nFET source/drain region216and the pFET source/drain region217, thus providing a new insulator material to separate these two regions. In certain embodiments, the material of the hardened insulator layer222may be one or more of BN, SiBN, Al2O3, AlN and HfO. In certain embodiments, this material of the hardened insulator layer222is a harder material than the material of the ILD layer220. In certain embodiments, the hardened insulator layer222can be deposited and planarized using CMP.

Referring now toFIGS. 6A-6Cand initially toFIG. 6A, this figure is a plan view of the semiconductor FET device200ofFIG. 5Aafter additional fabrication operations, according to embodiments. As shown inFIG. 6A, a contact lithography and etching process are performed to expose portions of the underlying nFET source/drain region216and the pFET source/drain region217(in particular, to expose the nitride liner layer209covering the nFET source/drain region216and the pFET source/drain region217).FIG. 6Bis a cross-sectional view of the semiconductor FET device ofFIG. 5Ataken along line B-B, and it is shown after the etching operation is performed, and in certain examples this leaves a space260between the two rightmost adjacent gate electrodes214.FIG. 6Cis a cross-sectional view of the semiconductor FET device ofFIG. 5Ataken along line A-A, and after the etching operation has been performed. As shown inFIG. 6C, the etching exposes the nitride liner layer209covering the nFET source/drain region216and the pFET source/drain region217. In the example shown inFIG. 6A, there are three contact regions that are created by this etching step and that correspond to the three nitride liner layers219. The left two contact regions (i.e., the left two nitride liner layers219) inFIG. 6Atraverse the hardened insulator layer222, and the right contact region (i.e., the rightmost nitride layer219) does not traverse a portion of the hardened insulator layer222. In certain embodiments, the etchant for the material removal step shown inFIGS. 6A-6Chas an etching selectivity for the ILD layer220and the deposited layer202. Thus, this material is removed without removing the hardened insulator layer222. As such, as shown inFIG. 6C, the sidewalls of the hardened insulator layer222are exposed.

Referring now toFIGS. 7A-7Cand initially toFIG. 7A, this figure is a plan view of the semiconductor FET device200ofFIG. 6Aafter additional fabrication operations, according to embodiments. As shown inFIG. 7A, a contact metal230is deposited to fill in the spaces (i.e., spaces260shown inFIGS. 6B and 6C) formed in the etching step described above with respect toFIGS. 6A-6C.FIG. 7Bis a cross-sectional view of the semiconductor FET device ofFIG. 6Aafter additional fabrication operations and taken along line B-B, andFIG. 7Cis a cross-sectional view of the semiconductor FET device ofFIG. 6Aafter additional fabrication operations and taken along line A-A, according to embodiments. The contact metal230is also shown in the cross-sectional views ofFIGS. 7B and 7C. In certain embodiments, a CMP process is performed on the FET device200to planarize the surface thereof. As shown inFIG. 7Cthe N/P Distance of X3+2*X4 corresponds generally to the same dimension shown inFIG. 1B. Thus, in certain embodiments, the dimension of X4 shown inFIG. 7Cis less than the dimension of X2 shown inFIG. 1Abecause the etching cut is not made on a line end. Also, the dimension of X3 shown inFIG. 7Cis less than the dimension of X1 shown inFIG. 1Abecause the deposited layer202and the ILD layer220are partially cut through (or removed). One effect of using a single cut mask (i.e., rather than two or more) is that the contact metal230is self-aligned to the deposited layer202and the ILD layer220post etching operation. Another effect is that by using only one cut mask (i.e., only one etching operation), the manufacturing efficiencies may be increased. Because the dimension X3 can be reduced related to other manufacturing techniques, the footprint of the FET device200may be decreased in at least one dimension and the device density may be increased (i.e., thus allowing more device to fit into a smaller area).