Semiconductor packages and methods of formation thereof

In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle, and an encapsulant disposed around the die paddle. The semiconductor package has a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a corner region. A tie bar is disposed within the encapsulant. The tie bar couples the die paddle and extends away from the die paddle. A dummy lead is disposed in the corner region. The dummy lead is not electrically coupled to another electrically conductive component within the semiconductor package. The distance between the dummy lead and the tie bar is less than a shortest distance between the tie bar and other leads or other tie bars in the semiconductor package.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, and more particularly to semiconductor packages and methods of formation thereof.

BACKGROUND

Semiconductor devices are used in many electronic and other applications. Semiconductor devices comprise integrated circuits or discrete devices that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits.

The semiconductor devices are typically packaged within a ceramic or a plastic body to protect from physical damage and corrosion. The packaging also supports the electrical contacts required to connect to the devices. Many different types of packaging are available depending on the type and the intended use of the die being packaged. Typical packaging, e.g., dimensions of the package, pin count, may comply with open standards such as from Joint Electron Devices Engineering Council (JEDEC). Packaging may also be referred as semiconductor device assembly or simply assembly.

Packaging may be a cost intensive process because of the complexity of connecting multiple electrical connections to external pads while protecting these electrical connections and the underlying chips.

SUMMARY OF THE INVENTION

In accordance with an embodiment of the present invention, a semiconductor package comprises a die paddle, and an encapsulant disposed around the die paddle. The semiconductor package has a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a corner region. A tie bar is disposed within the encapsulant. The tie bar couples the die paddle and extends away from the die paddle. A dummy lead is disposed in the corner region. The dummy lead is not electrically coupled to another electrically conductive component within the semiconductor package. The distance between the dummy lead and the tie bar is less than a shortest distance between the tie bar and other leads or other tie bars in the semiconductor package.

In accordance with an alternative embodiment of the present invention, a semiconductor package comprises a package body having a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a edge. A plurality of leads is disposed along the first sidewall. Each lead is electrically coupled to another component within the semiconductor package. A conductor is disposed proximate the edge within the package body, the conductor not being coupled to another electrically conductive component within the semiconductor package. Each lead of the plurality of leads is spaced apart from another lead of the plurality of leads by a minimum creepage distance. The distance between the conductor and a lead of the plurality of leads is less than the creepage distance.

In accordance with an alternative embodiment of the present invention, a leadframe comprises a frame having an opening, and a die paddle disposed within the opening. The die paddle is configured to mount a plurality of dies. A plurality of leads is arranged along a side of the die paddle. The plurality of leads extend away from the die paddle. A tie bar connects the die paddle to the frame. A dummy lead is disposed in a corner region. The minimum creepage distance between each lead and the tie bar is larger than a distance between the dummy lead and the tie bar.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In a semiconductor package, leads provide electrical connection to various dies within the package. The leads also mechanically secure the package over the component to which it is attached (e.g., circuit board). However, the number of electrical leads may be limited especially in case of power semiconductor packages. Further, the electrical leads may have strict design rules. Therefore, in many cases, the various limitations on the size and placement of electrical leads may hinder the formation of a mechanically secure package. For example, in a small sized package such as a 12×12 mm2, additional electrical leads may not be introduced due to the limitations imposed by the creepage and clearance requirements. For example, the creepage distance may be about a few millimeters at high voltages above 100V, e.g., about 2.5 mm at about 400V. As a consequence, the number of functional leads is limited, which may result in improper anchoring of the semiconductor package to a circuit board. Various embodiments of the present invention overcome these and other problems.

A structural embodiment of a semiconductor package will be described usingFIG. 1. Further structural embodiments of the semiconductor package will be described usingFIGS. 2-4,9, and10.FIGS. 5-9will be used to describe an assembly process to form a semiconductor package in accordance with embodiments of the invention. An embodiment of a lead frame strip will be described usingFIGS. 5 and 11.

FIG. 1, which includesFIGS. 1A-1C, illustrates a semiconductor package in accordance with an embodiment of the invention.FIG. 1Aillustrates a plan view,FIG. 1Billustrates a cross-sectional view, andFIG. 1Cillustrates a bottom view.

In various embodiments, the semiconductor package1is a multi-chip module comprising a plurality of chips. In various embodiments, the semiconductor package1comprises a power module, e.g., supporting power dies operating at high voltages (e.g., greater than 100 V).

Referring toFIG. 1A, the semiconductor package1includes a die paddle50embedded within an encapsulating material80. A first die101and a second die102are disposed over the die paddle50. In one or more embodiments, the first die101and the second die102may comprise discrete power dies. Examples of the first die101and the second die102may include PIN or Schottky diodes, MISFET, JFET, BJT, IGBT, or thyristor.

The die paddle50may have been supported by tie bars during the packaging process, and may therefore include portions of the tie bar, which are left after dicing the lead frame strip. For example, the die paddle50may be coupled to a portion of a vertical tie bar51and another portion of a horizontal tie bar52.

The vertical tie bar51and the horizontal tie bar52may be coupled to a first potential node thereby coupling the bottom surfaces of the first die101and the second die102to the first potential node. In one embodiment, the first potential node may be a high voltage node, e.g., may be higher than about 100V. For example, in one embodiment, the first potential node may be coupled to voltages between 100V to about 500V, and about 400V in one embodiment.

A plurality of leads30is disposed along the edges of the encapsulating material80. The first die101and the second die102are coupled to the plurality of leads30via interconnects90. The interconnect90may comprise wire bonds, clip, and other structures in various embodiments.

Additionally, one or more dummy leads130are disposed along the edges of the package in various embodiments. The dummy leads130may be positioned in corner regions of the semiconductor package in one or more embodiments. In further embodiments, the dummy leads130are not coupled to other components within the semiconductor package1. For example, the dummy leads130are not electrically coupled to the first die101or the second die102by interconnects90. Further, the dummy leads130are also not coupled thermally to the first die101or the second die102.

Rather, in various embodiments, the dummy leads130are provided to improve mechanical stability. In various embodiments, the dummy leads130improve the stability of the package body from mechanical stress related failures. For example, the corners of the package may be subject to a stress concentration, which may result in the failure of the package over a life time of the product. As an illustration, the contact pads (solder) at the corner regions may crack or delaminate the encapsulation. Embodiments of the invention improve the reliability of the semiconductor package by improving the susceptibility of the semiconductor package to mechanical stress.

Referring toFIG. 1A, embodiments of the invention introduce dummy leads130without degrading the electrical isolation of the semiconductor package. For example, the creepage distance is a minimum distance between electrical components or conductive components within the semiconductor package as measured along the surface of the package body. In various embodiments, the introduction of the dummy leads130does not degrade the creepage distance because the dummy leads130are not coupled to electrical circuitry.

Similarly, in various embodiments, the dummy leads130are introduced without degrading the clearance distance, which is the distance between conductive components as measured along a path outside (air) the package body. Thus, in various embodiments, the addition of the dummy leads130does not significantly impact the clearance, which is needed to prevent dielectric breakdown associated to ionization of air.

In various embodiments, dummy leads130are provided to securely anchor the semiconductor package to a board. In various embodiments, additional leads, lead like structures, or other conductive structures are introduce to generate a uniform stress concentration along the semiconductor package. However, the additional leads are not electrically or thermally connected to other components. Therefore, these dummy leads130do not follow the more stringent spacing requirements for the plurality of leads30.

FIG. 1Billustrates a cross-sectional view and illustrates that the die paddle50is coupled to the first die101through an adhesive layer70. In various embodiments, the adhesive layer70may be a thermal and/or electrical conductive layer. Thus, the first die101is coupled to the die paddle50.FIG. 1Cillustrates a bottom view of the semiconductor package1showing the exposed plurality of leads30, the dummy leads130. In some embodiments, the dummy leads130may be fully covered from the back surface. Therefore, in the bottom view, the dummy leads130may not be visible. The die paddle50may be coupled through bottom contact pads55to a circuit board or a substrate.

FIG. 2, which includesFIGS. 2A-2E, illustrates a power semiconductor package in accordance with an embodiment of the present invention.FIG. 2Aillustrates a plan view,FIGS. 2B and 2Cillustrate cross-sectional views,FIG. 2Dillustrates a bottom view, andFIG. 2Eillustrates a schematic circuit of the power semiconductor package.

Referring toFIG. 2A, the semiconductor package1comprises a first die paddle50and a plurality of second die paddles150disposed proximate the first die paddle50. The first die paddle50and the plurality of second die paddles150are supported by vertical tie bars51and horizontal tie bars52along with one or more central tie bars53.

A first die101, a second die102, and a third die103are disposed over the first die paddle50. Similarly, a fourth die104is disposed over a die pad of the plurality of second die paddles150, a fifth die105is disposed over a die pad of the plurality of second die paddles150, and a sixth die106is disposed over a die pad of the plurality of second die paddles150. Unlike the first die paddle50, each of the plurality of second die paddle150support only a single die in the illustrated embodiment. However, in various embodiments, the multichip module may have different configurations with regard to the number and size of die paddles and the number of dies.

In various embodiments, each die includes contact openings, which would expose a plurality of contact pads. As illustrated inFIG. 2A, each die such as the first die101includes a contact opening201. The first die101may include a plurality of contact pads such as a primary contact pad202and an auxiliary contact pad203. The primary contact pad202may be coupled to a source/drain region of a discrete transistor die in one or more embodiments. Alternatively, the primary contact pad202may be coupled to an emitter/collector region of the discrete transistor die. The auxiliary contact pad203may be coupled to a gate region or alternatively to a base region of a transistor.

As illustrated inFIG. 2A, the primary contact pad202and the auxiliary contact pad203are coupled to the plurality of leads30through interconnects90. Further, the interconnects90may also interconnect the dies internally. For example, the primary contact pad202of the first die101is coupled to the second die paddle150supporting the fourth die104. Similarly, the primary contact pad202of the second die102is coupled to the second die paddle150supporting the fifth die105.

Referring to cross-sectional views ofFIGS. 2B and 2C, each die is supported to the corresponding die paddle by an adhesive layer70, which may be an electrically conductive layer in some embodiments.

FIG. 2Dillustrates a bottom view of the semiconductor package1in one or more embodiments. The die paddles may be contacted using bottom contact pads55. As illustrated inFIG. 2D, in one or more embodiments, the dummy leads130are exposed along with the plurality of leads30.

FIG. 2Eillustrates a schematic diagram of the multi-chip module in accordance with an embodiment of the invention.

In the illustration, a three-phase motor control circuit is illustrated as an example. However, in other embodiments, the multichip module may be any power module and may include converters, full bridge circuits and half bridge circuits, e.g., used in inverters and universal power supply, and others.

Referring toFIG. 2E, the module comprises the first die101, the second die102, and the third die103coupled to a high voltage node (HV). The module further comprises the fourth die104, the fifth die105, and the sixth die106coupled to a low voltage node (LV). The first die101, the second die102, and the third die103form the high-side switches of the three-phase motor control circuit while the fourth die104, the fifth die105, and the sixth die106forms the low side switches. The three phase output supply is outputted through the first, the second, and the third voltage nodes V1, V2, and V3.

FIG. 3, which includesFIGS. 3A-3B, illustrates alternative embodiments of the semiconductor package.FIG. 3Aillustrates a different configuration of the multi-chip module showing a plurality of dummy leads having different sizes and shapes.FIG. 3Billustrates an alternative embodiment showing the placement of the dummy leads relative to functional leads.

Referring toFIG. 3A, the dummy leads130may have different sizes depending on the location with respect to other leads as well as the structure of the semiconductor package. In various embodiments, the dummy leads130may be used for anchoring the semiconductor package1to a circuit board. The dummy leads130are not coupled to any components within the semiconductor package1and therefore provide flexibility in their placement. Unlike the plurality of leads30, which are spaced apart by the creepage distance, the dummy leads130may not have such limitations.

As an illustration, the first die101may comprise an integrated chip with a plurality of leads that may be closely spaced due to the lower voltages. However, the second die102and the third die103may comprise power chips operating at higher voltages. Therefore, the corner regions around the third die103(right top and bottom sides of the page) do not have sufficient room for placing additional functional leads. In contrast, in various embodiments, a plurality of dummy leads130may be placed to improve the mechanical stability of the semiconductor package1. Similarly, the larger dummy leads130may be placed on the sides of the semiconductor package1.

FIG. 3Billustrates an alternative embodiment showing the placement of the dummy leads relative to functional leads. As illustrated inFIG. 3B, the dummy lead130may be spaced apart from one of the plurality of leads30by a dummy lead distance (DDL), which may be smaller than the minimum distance of adjacent leads of the plurality of leads30, which is the creepage distance (CD). In the illustrated design, a electrical lead of the plurality of leads30may not be placed in the corner region of the semiconductor package1because that would violate the creepage requirements. In contrast, the dummy leads may be placed without compromising creepage while providing mechanical stability to the semiconductor package1.

FIG. 4illustrates a semiconductor package mounted on a circuit board in accordance with an embodiment of the invention.

The semiconductor package1comprises a plurality of contact pads55and a plurality of leads30for connecting the semiconductor dies within the semiconductor package1to various external components. The semiconductor package may be mounted over a circuit board500using a plurality of board contacts510. For example, the plurality of contact pads55and the plurality of leads30are joined to the circuit board500at active circuit pads520. The physical connection also provides electrical connection to the semiconductor package1.

In various embodiments, the dummy leads130are also coupled to the circuit board500at anchor circuit pads530. However, the anchor circuit pads530on the circuit board500are different from the active circuit pads520. Unlike the active circuit pads520, which are coupled to other components on the circuit board, the anchor circuit pads530have no further connection or metal traces emanating from them. The anchor circuit pads530help to anchor the semiconductor package1and provide no electrical or thermal connection.

FIGS. 5-9will be used to describe an assembly process to form a semiconductor package in accordance with embodiments of the invention.

FIG. 5, which includesFIGS. 5A and 5B, illustrates a semiconductor package during a stage of fabrication.FIG. 5Aillustrates a cross-sectional view whileFIG. 5Billustrates a top view.

Referring toFIG. 5A, the lead frame300is placed over a carrier200. The carrier200may be any suitable substrate to facilitate the assembly of the semiconductor module in various embodiments. The carrier200provides mechanical support and stability during processing. In various embodiments, the carrier200may be an adhesive tape, a frame, a plate made of a rigid material, for example, a metal such as nickel, steel, or stainless steel, a laminate, a film, or a material stack.

As illustrated inFIG. 5B, the lead frame300may be a part of a lead frame strip, which includes a plurality of lead frame units arranged in a matrix. Each lead frame300in the lead frame strip may have a central opening in which a plurality of die paddles is formed. Further, each lead frame300includes a first die paddle50and a plurality of second die paddles150connected to the outer frame through tie bars such as the vertical tie bar51and the horizontal tie bar52. One or more central tie bars53may be used to connect the various die paddles together depending on the circuitry of the module being formed.

The lead frame300also includes a number of dummy leads130, which as will be evident, are not configured to be connected to other components. Rather, the dummy leads130may violate some of the design rules associated with the design and placement of the leads30and tie bars. Examples of such design rules include creepage and clearance distances.

Each unit or lead frame300is separated from an adjacent lead frame30by a gap (dashed line), which form dicing streets210. After completing the assembly process, the individual lead frame300may be separated by physically separating them along these dicing streets210. Alternatively, the lead frame strip may be diced to form individual lead frame units prior to the assembly process.

FIG. 6, which includesFIGS. 6A and 6B, illustrates a semiconductor package during a subsequent stage of fabrication after attaching dies to the lead frames.FIG. 6Aillustrates a cross-sectional view whileFIG. 6Billustrates a top view.

As next illustrated inFIG. 6A, semiconductor dies are attaches to the die paddles of the lead frame300. As illustrated inFIG. 6B, a first die101, a second die102, and a third die103are attached to the first die paddle50. Similarly, a fourth die104, a fifth die105, and a sixth die106are attached to each of the plurality of second die paddles150. In some embodiments, each of the first, the second, the third, the fourth, the fifth, and the sixth dies101,102,103,104,105, and106(hereinafter “dies101-106”) may be different from each other. Alternatively, one or more of the dies101-106may be similar to each other. Each of these dies101-106may be fabricated separately in various embodiments. The dies101-106may be formed on a silicon substrate such as a bulk silicon substrate or a silicon on insulator (SOI) substrate. Alternatively, each of the dies101-106may be a device formed on silicon carbide (SiC). Embodiments of the invention may also include devices formed on compound semiconductor substrates and may include devices on hetero-epitaxial substrates. In one embodiment, each of the dies101-106is a device formed at least partially on gallium nitride (GaN), which may be a GaN on sapphire or silicon substrate.

In various embodiments, each of the dies101-106may comprise a power die, which, for example, draw large currents (e.g., greater than 30 amperes). In various embodiments, the dies101-106may comprise a discrete vertical device such as a two or a three terminal power device. Examples of the dies101-106include PIN or Schottky diodes, MISFET, JFET, BJT, IGBT, or thyristor.

In various embodiments, each of the dies101-106may be a vertical semiconductor device configured to operate at about 20 V to about 1000 V. In one embodiment, each of the dies101-106may be configured to operate at about 20 V to about 100 V. In another embodiment, each of the dies101-106may be configured to operate at about 100 V to about 500 V. In yet another embodiment, each of the dies101-106may be configured to operate at about 500 V to about 1000 V. Because of the high voltages used, creepage is an important aspect of the design of the semiconductor package.

The dies101-106may include an insulated-gate bipolar transistor (IGBT) in some embodiments. In one embodiment, each of the dies101-106may be an NPN transistor. In another embodiment, each of the dies101-106may be a PNP transistor. In yet another embodiment, each of the dies101-106may be an n-channel MISFET. In a further embodiment, each of the dies101-106may be a p-channel MISFET. In one or more embodiments, each of the dies101-106may comprise a plurality of devices such as a vertical MISFET and a diode, or alternatively two MISFET devices separated by an isolation region.

Each of the dies101-106is placed over the lead frame300. In various embodiments, each of the die may be sequentially attached in some embodiments. For example, a plurality of the first dies101may be attached to (placed over) all the plurality of lead frames300of the lead frame strip before attaching the plurality of second dies102.

In various embodiments, the dies101-106may be attached to the lead frame300using an adhesive layer70, which may be an insulating layer in one embodiment. In some embodiments, the adhesive layer70may be conductive, for example, may comprise a nano-conductive paste. In alternative embodiments, the adhesive layer70is a solderable material.

In one embodiment, the adhesive layer70comprises a polymer such as a cyanide ester or epoxy material and may comprise silver particles. In one embodiment, the adhesive layer70may be applied as conductive particles in a polymer matrix so as to form a composite material after curing. In an alternative embodiment, a conductive nano-paste such as a silver nano-paste may be applied. Alternatively, in another embodiment, the adhesive layer70comprises a solder such as lead-tin material. In various embodiments, any suitable conductive adhesive material including metals or metal alloys such as aluminum, titanium, gold, silver, copper, palladium, platinum, nickel, chromium or nickel vanadium, may be used to form the adhesive layer70.

The adhesive layer70may be dispensed in controlled quantities under the dies101-106. The adhesive layer70having a polymer may be cured at about 125° C. to about 200° C. while a solder based adhesive layer70may be cured at 250° C. to about 350° C. Using the adhesive layer70, the dies101-106are attached to the die paddles of the lead frame300.

FIG. 7, which includesFIGS. 7A and 7B, illustrates a semiconductor package during a subsequent stage of fabrication after forming interconnects in accordance with embodiments of the invention.FIG. 7Aillustrates a cross-sectional view whileFIG. 7Billustrates a top view.

In various embodiments, ball bonding or wedge bonding may be used to form interconnects90. In various embodiments, the interconnects90, e.g., comprising wire bonds may be formed using thermosonic bonding, ultrasonic bonding, or thermo-compression bonding. Thermosonic bonding utilizes temperature, ultrasonic, and low impact force, and ball/wedge methods. Ultrasonic bonding utilizes ultrasonic and low impact force, and the wedge method only. Thermo-compression bonding utilizes temperature and high impact force, and the wedge method only.

For example, in one case, thermosonic bonding may be used with gold and copper wires. Two wire bonds are formed for each interconnection, one at contact regions of the first die101and another at a lead of the plurality of the leads30of the lead frame300. Bonding temperature, ultrasonic energy, and bond force and time may have to be closely controlled to form a reliable connection from the first die101to the lead frame300. In an alternative embodiment, the interconnects90may be formed using a galvanic process (electro chemical deposition). The interconnects90between the first die101and the lead frame300and between the dies101-106may be different especially between power dies in some embodiments.

FIG. 8illustrates a semiconductor package during a subsequent stage of fabrication after forming the package body in accordance with embodiments of the invention.

Referring toFIG. 8, an encapsulating material80is deposited over the lead frame300, the dies101-106, and the interconnects90. In various embodiments, the encapsulating material80is coated over the entire carrier200. The dies101-106are thus embedded within the encapsulating material80. In one embodiment, the encapsulating material80is applied using a compression molding process. In compression molding, the encapsulating material80may be placed into a molding cavity, then the molding cavity is closed to compress the encapsulating material80. Compression molding may be used when a single pattern is being molded. In an alternative embodiment, the encapsulating material80is applied using a transfer molding process. In other embodiments, the encapsulating material80may be applied using injection molding, granulate molding, powder molding, or liquid molding. Alternatively, the encapsulating material80may be applied using printing processes such as stencil or screen printing.

In various embodiments, the encapsulating material80comprises a dielectric material and may comprise a mold compound in one embodiment. In other embodiments, the encapsulating material80may comprise a polymer, a biopolymer, a fiber impregnated polymer (e.g., carbon or glass fibers in a resin), a particle filled polymer, and other organic materials. In one or more embodiments, the encapsulating material80comprises a sealant not formed using a mold compound, and materials such as epoxy resins and/or silicones. In various embodiments, the encapsulating material80may be made of any appropriate duroplastic, thermoplastic, or thermosetting material, or a laminate. The material of the encapsulating material80may include filler materials in some embodiments. In one embodiment, the encapsulating material80may comprise epoxy material and a fill material comprising small particles of glass or other electrically insulating mineral filler materials like alumina or organic fill materials.

The encapsulating material80may be cured, i.e., subjected to a thermal process to harden thus forming a hermetic seal protecting the dies101-106, the adhesive layer70, the interconnects90, and the lead frame300.

Thus, a plurality of semiconductor packages is formed. A singulation process may be used to separate the plurality of semiconductor packages into individual units. In one embodiment, a dicing tool250may be used to mechanically separate the leadframe strip to form physically separate semiconductor packages. The packages may be subsequently separated from the carrier200. Although a batch process is illustrated above, in various embodiments, a sequential process may be used in which each semiconductor package is fabricated separately.

FIG. 9, which includesFIGS. 9A-9C, illustrates an alternative embodiment of the semiconductor package using a different dummy lead.FIG. 9Aillustrates a cross-sectional view whileFIGS. 9B and 9Cillustrate alternative top views.

As illustrated inFIG. 9A, in various embodiments, the dummy leads130may have a different shape and size relative to the plurality of leads30. The design of the dummy leads130may, for example, be optimized to improve mechanical stability. As an illustration, inFIG. 9A, the dummy lead130includes a top opening131and a neck region132, which is exposed on the bottom surface of the semiconductor package1. The top opening131may be designed to stabilize the structure and prevent delamination between the encapsulating material80and the dummy lead130.

FIGS. 9B and 9Cillustrate alternative top views of the dummy lead130shown inFIG. 9A. For example, in one embodiment, the dummy lead130may have a concentric shape.FIG. 9Cillustrates an alternative finger structure in which the neck region132is formed as a rectangular central line around which a plurality of fingers is arranged. Such a finger structure may be used to improve the adhesion between the dummy lead130and the encapsulating material80further.

FIG. 10illustrates a semiconductor package using an alternative dummy lead in accordance with an embodiment of the invention.

InFIG. 10, the dummy lead130includes a top opening131and a bottom opening133. This may be used to strengthen the joint between the circuit board and the semiconductor package1. In other words, the design of the dummy lead130may improve anchoring. Such design changes may help to homogenize the stress (minimize stress concentration) within the encapsulating material80in various embodiments.

FIG. 11illustrates a lead frame strip having a number of dummy leads in accordance with various embodiments of the invention.

Referring toFIG. 11, the dummy leads130may be placed along the dicing street in one or more embodiments. In particular, in various embodiments, additional dummy leads130may be placed as long as they are surrounded by tie bars or leads of the plurality of leads30at the same potential. For example, as illustrated inFIG. 11, additional dummy leads130have been placed along the corners of the dicing street. These dummy leads are surrounded by portions of the vertical and horizontal tie bars51and52, which are both connected to the same die paddle supporting the sixth die106.

In various embodiments, different design rules may be adopted for the placement of the dummy leads130. For example, in one embodiment, the dummy leads130may not be placed between two leads coupled to different potentials. For example, inFIG. 11, one of the dummy leads130is placed between the vertical tie bar51and the horizontal tie bar52coupled to the die paddle holding the sixth die106because the tie bars surrounding this dummy lead130are both coupled to a same potential. In contrast, the corner region C1 adjacent the horizontal tie bar52coupled to the fourth die104may not include a dummy lead because the horizontal tie bar52is coupled to a different potential than the leads30proximate the dummy lead position.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. As an illustration, the embodiments described inFIGS. 1-11may be combined with each other in various embodiments. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention.