Circuit board and manufacturing method thereof and electronic device

A circuit board includes a first substrate, a second substrate, a third substrate, a plurality of conductive structures and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate has an opening and includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The opening penetrates the first dielectric layer and the second dielectric layer, and the third dielectric layer fully fills the opening. The conductive via structure penetrates the first substrate, the second substrate, the third dielectric layer of the third substrate, and is electrically connected to the first substrate and the third substrate to define a signal path. The first substrate, the second substrate, and the third substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.

BACKGROUND

Technical Field

The disclosure relates to a substrate structure and a manufacturing method thereof, and in particular, to a circuit board and a manufacturing method thereof and an electronic device adopting the circuit board.

Description of Related Art

In a conventional circuit board, a design of a coaxial via requires one or more layers of insulating layers between an inner conductor layer and an outer conductor layer for isolation. The insulating layers are formed through press-fitting and a build-up process. Therefore, there may be impedance mismatch and a gap of electromagnetic interference (EMI) shielding at the two ends of the coaxial via, affecting high-frequency signal integrity. In addition, in the design of the coaxial via, the two ends of a signal path and the two ends of a ground path are respectively located on different planes, and noise interference cannot be reduced.

SUMMARY

The disclosure is directed to a circuit board having a good signal circuit and exhibiting favorable signal integrity.

The disclosure further provides a manufacturing method of a circuit board to manufacture the circuit board.

The disclosure further provides an electronic device including the circuit board and exhibiting favorable electromagnetic interference (EMI) shielding and impedance matching effects, thereby enhancing reliability of signal transmission.

The circuit board of the disclosure includes a first substrate, a second substrate, a third substrate, multiple conductive structures, and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate has an opening and includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The opening penetrates the first dielectric layer and the second dielectric layer, and the opening is fully filled with the third dielectric layer. The conductive via structure penetrates the first substrate, the second substrate, and the third dielectric layer of the third substrate and is electrically connected to the first substrate and the third substrate to define a signal path. The first substrate, the second substrate, and the third substrate are electrically connected through the conductive structures to define a ground path. The ground path surrounds the signal path.

In an embodiment of the disclosure, the conductive structures include multiple first conductive vias, multiple conductive pillars, and a conductive connection layer. The first substrate includes a core layer, a first external circuit layer, a first circuit layer, and first conductive vias. The first external circuit layer and the first circuit layer are respectively disposed on two opposite sides of the core layer. The first conductive vias penetrate the core layer and are electrically connected to the first external circuit layer and the first circuit layer. The second substrate includes a base and the conductive pillars penetrating the base. The third substrate further includes a second circuit layer, a third circuit layer, a second external circuit layer, multiple second conductive vias, and the conductive connection layer. The second circuit layer and the third circuit layer are located at two opposite sides of the first dielectric layer, and the second dielectric layer covers the third circuit layer and located between the third circuit layer and the second external circuit layer. The second conductive vias penetrate the second dielectric layer and are electrically connected to the second external circuit layer and the third circuit layer. The conductive connection layer covers an inner wall of the opening and is connected to the second circuit layer, the third circuit layer, and the second external circuit layer. The conductive via structure includes a via and a conductive material. The via penetrates the core layer of the first substrate, the base of the second substrate, and the third dielectric layer of the third substrate. The conductive material covers an inner wall of the via and is electrically connected to the first external circuit layer and the second external circuit layer.

In an embodiment of the disclosure, the first external circuit layer includes a first signal circuit and a first ground circuit. The second external circuit layer includes a second signal circuit and a second ground circuit. The first signal circuit, the conductive material, and the second signal circuit define the signal path. The first ground circuit, the first conductive vias, the first circuit layer, the conductive pillars, the second circuit layer, the conductive connection layer, and the second ground circuit define the ground path.

In an embodiment of the disclosure, the circuit board further includes a fourth dielectric layer fully filling the via. A first surface and a second surface of the fourth dielectric layer that are opposite to each other are respectively flush with an upper surface of the first external circuit layer and a lower surface of the second external circuit layer.

In an embodiment of the disclosure, the circuit board further includes a capping layer disposed on the upper surface of the first external circuit layer, the lower surface of the second external circuit layer, and the first surface and the second surface of the fourth dielectric layer.

The manufacturing method of the circuit board of the disclosure includes the following. A first substrate, a second substrate, and a third substrate are provided. The third substrate has an opening and includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The opening penetrates the first dielectric layer and the second dielectric layer, and the opening is fully filled with the third dielectric layer. The first substrate, the second substrate, and the third substrate are press-fitted so that the second substrate is located between the first substrate and the third substrate. Multiple conductive structures are formed so that the first substrate, the second substrate, and the third substrate are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, and the third dielectric layer of the third substrate. The conductive via structure is electrically connected to the first substrate and the third substrate to define a signal path. The ground path surrounds the signal path.

In an embodiment of the disclosure, providing the first substrate, the second substrate, and the third substrate includes the following. The first substrate is provided. The first substrate includes a core layer, a first conductive layer, and a first circuit layer. The first conductive layer and the first circuit layer are respectively disposed on two opposite sides of the core layer. The second substrate is provided. The second substrate includes a base and multiple conductive pillars penetrating the base. The third substrate is provided. The third substrate further includes a second circuit layer, a third circuit layer, a second conductive layer, and a conductive connection layer. The second circuit layer and the third circuit layer are located at two opposite sides of the first dielectric layer. The second dielectric layer covers the third circuit layer and is located between the third circuit layer and the second conductive layer. The conductive connection layer covers an inner wall of the opening and is connected to the second circuit layer, the third circuit layer, and the second conductive layer.

In an embodiment of the disclosure, the conductive structures include multiple first conductive vias, the conductive pillars, and the conductive connection layer.

In an embodiment of the disclosure, forming the first conductive vias of the conductive structures and forming the conductive via structure include the following. Multiple first blind vias, multiple second blind vias, and a via are formed. The first blind vias extend from the first conductive layer to the first circuit layer, and the second blind vias extend from the second conductive layer to the third circuit layer. The via penetrates the core layer of the first substrate, the base of the second substrate, and the third dielectric layer of the third substrate. A conductive material layer is formed to fully fill the first blind vias and the second blind vias and extend to cover the first conductive layer, the second conductive layer, and an inner wall of the via. The conductive material layer fully filling the first blind vias defines the first conductive vias. The conductive material layer fully filling the second blind vias defines multiple second conductive vias. The conductive material layer, the first conductive layer, and the second conductive layer are patterned to form a first external circuit layer, a second external circuit layer, and a conductive material covering the inner wall of the via and electrically connected to the first external circuit layer and the second external circuit layer. The first external circuit layer is located on the core layer of the first substrate. The second external circuit layer is located on the second dielectric layer of the third substrate. The via and the conductive material define the conductive via structure.

In an embodiment of the disclosure, the first external circuit layer includes a first signal circuit and a first ground circuit. The second external circuit layer includes a second signal circuit and a second ground circuit. The first signal circuit, the conductive material, and the second signal circuit define the signal path. The first ground circuit, the first conductive vias, the first circuit layer, the conductive pillars, the second circuit layer, the conductive connection layer, and the second ground circuit define the ground path.

In an embodiment of the disclosure, the manufacturing method of the circuit board further includes the following. After the conductive material layer is formed and before the conductive material layer, the first conductive layer, and the second conductive layer are patterned, a fourth dielectric layer is filled in the via. The via is fully filled with the fourth dielectric layer, and a first surface and a second surface of the fourth dielectric layer that are opposite to each other are respectively flush with an upper surface and a lower surface of the conductive material layer.

In an embodiment of the disclosure, the manufacturing method of the circuit board further includes the following. After the fourth dielectric layer is filled in the via and before the conductive material layer, the first conductive layer, and the second conductive layer are patterned, a metal layer is formed on the conductive material layer. The metal layer covers the upper surface and the lower surface of the conductive material layer and the first surface and the second surface of the fourth dielectric layer. When the conductive material layer, the first conductive layer, and the second conductive layer are patterned, the metal layer is patterned at the same time to form a capping layer. The capping layer covers the first external circuit layer, the second external circuit layer, and the first surface and the second surface of the fourth dielectric layer.

The electronic device of the disclosure includes a circuit board and an electronic element. The circuit board includes a first substrate, a second substrate, a third substrate, multiple conductive structures, and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate has an opening and includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The opening penetrates the first dielectric layer and the second dielectric layer, and the opening is fully filled with the third dielectric layer. The conductive via structure penetrates the first substrate, the second substrate, and the third dielectric layer of the third substrate and is electrically connected to the first substrate and the third substrate to define a signal path. The first substrate, the second substrate, and the third substrate are electrically connected through the conductive structures to define a ground path. The ground path surrounds the signal path. The electronic element is electrically connected to the circuit board.

In an embodiment of the disclosure, the electronic device further includes multiple connection members disposed between the third substrate of the circuit board and the electronic element. The electronic element is electrically connected to the circuit board through the connection members.

Based on the above, in the design of the circuit board of the disclosure, the conductive via structure penetrates the first substrate, the second substrate, and the third dielectric layer of the third substrate and is electrically connected to the first substrate and the third substrate to define the signal path. The first substrate, the second substrate, and the third substrate are electrically connected through the conductive structures to define the ground path. The ground path surrounds the signal path. Hence, the favorable high-frequency and high speed signal circuit may be formed, and in further application of integrated circuits and antennas, signal interference on the same plane may be eliminated. Signal energy loss and noise interference may be reduced to enhance the reliability of signal transmission.

In order to make the aforementioned features and advantages of the disclosure comprehensible, embodiments accompanied with drawings are described in detail below.

DESCRIPTION OF THE EMBODIMENTS

FIG.1AtoFIG.1Eare schematic cross-sectional diagrams of a manufacturing method of a circuit board according to an embodiment of the disclosure.FIG.1Fis a top-view of a circuit board ofFIG.1E. In the manufacturing method of the circuit board according to the embodiment, referring toFIG.1A, a first substrate110, a second substrate120, a third substrate130are provided.

Specifically, in the embodiment, the first substrate110includes a core layer112, a first conductive layer114, and a first circuit layer116. The first conductive layer114and the first circuit layer116are respectively disposed on two opposite sides of the core layer112. The first conductive layer114is not patterned and completely covers a side surface of the core layer112, and the first circuit layer116is exposed out of a portion of another side surface of the core layer112. Here, a material of the core layer112is, for example, a dielectric material. A dielectric constant (Dk) of the core layer112, for example, ranges from 2 to 3.5, and a dielectric dissipation factor (DO of the core layer112is, for example, less than 0.006. A material of the first conductive layer114and the first circuit layer116is, for example, copper; however, the disclosure is not limited thereto.

The second substrate120includes a base122and multiple conductive pillars124penetrating the base122. Providing the second substrate120includes the following. First, the base122is provided. The base122is currently in a B phase state. That is, the base122is not completely cured. Next, release films may be attached to two opposite sides of the base122. A material of the release films is, for example, polyethylene terephthalate (PET). Next, a drilling process is performed on the base122to form a via. The drilling process is, for example but not limited to, laser drilling or mechanical drilling. The via is filled with a conductive adhesive through printing or injection to form the conductive pillars124. Next, the release films attached to the two opposite sides of the base122are removed so that two opposite surfaces of the conductive pillars124respectively protrude out of the two opposite sides of the base122, and the manufacture of the second substrate120is completed.

The third substrate130includes an opening137and includes a first dielectric layer131, a second dielectric layer133, a third dielectric layer135, a second circuit layer132, a third circuit layer134, a second conductive layer136, and a conductive connection layer138. The second circuit layer132and the third circuit layer134of the third substrate130are located at two opposite sides of the first dielectric layer131. The second dielectric layer133covers the third circuit layer134and is located between the third circuit layer134and the second conductive layer136. The opening137penetrates the first dielectric layer131and the second dielectric layer133, and the opening137is fully filled with the third dielectric layer135. The conductive connection layer138covers an inner wall of the opening137and is connected to the second circuit layer132, the third circuit layer134, and the second conductive layer136. Here, a dielectric constant (Dk) of the first dielectric layer131, for example, ranges from 2.4 to 4.0, and a dielectric dissipation factor (DO of the first dielectric layer131is, for example, less than 0.02. A dielectric constant (Dk) of the second dielectric layer133, for example, ranges from 2.0 to 3.5, and a dielectric dissipation factor (DO of the second dielectric layer133is, for example, less than 0.008. A dielectric constant (Dk) of the third dielectric layer135, for example, ranges from 2.1 to 5.0, and a dielectric dissipation factor (DO of the third dielectric layer135is, for example, less than 0.025.

Furthermore, providing the third substrate130includes first providing the first dielectric layer131and two conductive layers disposed at two opposite sides of the first dielectric layer131. The two conductive layers completely cover the two opposite sides of the first dielectric layer131. Next, a patterning process is performed on the two conductive layers to form the second circuit layer132and the third circuit layer134. Next, the second dielectric layer133and the second conductive layer136disposed on the second dielectric layer133are provided. The second dielectric layer133is press-fitted on the third circuit layer134so that the second dielectric layer133is located between the third circuit layer134and the second conductive layer136. The second conductive layer136is not patterned, and the second conductive layer136completely covers a side of the second dielectric layer133relatively away from the first dielectric layer131. Next, the opening137is formed to penetrate the second circuit layer132, the first dielectric layer131, the third circuit layer134, the second dielectric layer133, and the second conductive layer136. The conductive connection layer138is formed at the inner wall of the opening137and is electrically connected to the second circuit layer132, the third circuit layer134, and the second conductive layer136. Lastly, a plugging process is performed to fill the third dielectric layer135in the opening137. The opening137is fully filled with the third dielectric layer135, and the manufacture of the third substrate130is completed.

Next, referring toFIG.1B, the first substrate110, the second substrate120, and the third substrate130are press-fitted so that the second substrate120is located between the first substrate110and the third substrate130. Here, since a thermal compressing process is adopted, the base122of the second substrate120may be converted from the B phase state into a C phase state, which is the state of being completely cured. Hence, the first substrate110and the third substrate130are connected and fixed on the second substrate120. The conductive pillars124of the second substrate120are deformed due to abutting against the first circuit layer116and the second circuit layer132, and the conductive pillars124are electrically connected to the first circuit layer116of the first substrate110and the second circuit layer132of the third substrate130.

Next, referring toFIG.1C, multiple first blind vias H1, multiple second blind vias H2, and a via T are formed. The first blind vias H1extend from the first conductive layer114to the first circuit layer116, and the second blind vias H2extend from the second conductive layer136to the third circuit layer134. The via T penetrates the first conductive layer114and the core layer112of the first substrate110, the base122of the second substrate120, and the third dielectric layer135of the third substrate130. Here, a method for forming the first blind vias H1and the second blind vias H2is, for example, laser drilling, and a method for forming the via T is, for example, mechanical drilling; however, the disclosure is not limited thereto.

Next, referring toFIG.1D, a conductive material layer140is formed to fully fill the first blind vias H1and the second blind vias H2and extend to cover the first conductive layer114, the second conductive layer136, and an inner wall of the via T. The conductive material layer140fully filling the first blind vias H1defines multiple first conductive vias118of conductive structures. The conductive material layer140fully filling the second blind vias H2defines multiple second conductive vias139of the conductive structures. Here, a method for forming the conductive material layer140is, for example, electroless plating or electrolytic plating process, and the conductive material layer140is, for example, copper; however, the disclosure is not limited thereto.

Lastly, referring toFIG.1DandFIG.1Etogether, the conductive material layer140, the first conductive layer114, and the second conductive layer136are patterned through a photolithography process to form a first external circuit layer C1, a second external circuit layer C2, and a conductive material145covering the inner wall of the via T and electrically connected to the first external circuit layer C1and the second external circuit layer C2. The first external circuit layer C1is located on the core layer112of the first substrate110. The second external circuit layer C2is located on the second dielectric layer133of the third substrate130. The via T and the conductive material145define a conductive via structure150.

Here, the conductive structures are formed (i.e. the first conductive vias118, the conductive pillars124, and the conductive connection layer138) so that the first substrate110, the second substrate120, and the third substrate130are electrically connected through the conductive structures to define a ground path L2. The conductive via structure150is formed to penetrate the first substrate110, the second substrate120, and the third dielectric layer135of the third substrate130. The conductive via structure150is electrically connected to the first substrate110and the third substrate130to define a signal path L1, and the ground path L2surrounds the signal path L1. Furthermore, the first external circuit layer C1includes a first signal circuit C11and a first ground circuit C12. The second external circuit layer C2includes a second signal circuit C21and a second ground circuit C22. The first signal circuit C11, the conductive material145, and the second signal circuit C21define the signal path L1. The first ground circuit C12, the first conductive vias118, the first circuit layer116, the conductive pillars124, the second circuit layer132, the conductive connection layer138, and the second ground circuit C22define the ground path L2. The manufacture of a circuit board100ais completed.

With respect to a structure, referring toFIG.1EandFIG.1Ftogether, the circuit board100aincludes a first substrate110a, the second substrate120, a third substrate130a, the conductive structures, and the conductive via structure150. The second substrate120is disposed between the first substrate110aand the third substrate130a. The third substrate130ahas the opening137and includes the first dielectric layer131, the second dielectric layer133, and the third dielectric layer135. The opening137penetrates the first dielectric layer131and the second dielectric layer133, and the opening137is fully filled with the third dielectric layer135. The conductive via structure150penetrates the first substrate110a, the second substrate120, and the third dielectric layer135of the third substrate130aand is electrically connected to the first substrate110aand the third substrate130ato define the signal path L1. The first substrate110a, the second substrate120, and the third substrate130aare electrically connected through the conductive structures to define the ground path L2. The ground path L2surrounds the signal path L1.

Specifically, in the embodiment, the conductive structures include the first conductive vias118, the conductive pillars124, and the conductive connection layer138. The first substrate110aincludes the core layer112, the first external circuit layer C1, the first circuit layer116, and the first conductive vias118. The first external circuit layer C1and the first circuit layer116are respectively disposed on the two opposite sides of the core layer112. The first conductive vias118penetrate the core layer112and are electrically connected to the first external circuit layer C1and the first circuit layer116. The second substrate120includes the base122and the conductive pillars124penetrating the base122. The third substrate130afurther includes the second circuit layer132, the third circuit layer134, the second external circuit layer C2, the second conductive vias139, and the conductive connection layer138. The second circuit layer132and the third circuit layer134are located at the two opposite sides of the first dielectric layer131, and the second dielectric layer133covers the third circuit layer134and is located between the third circuit layer134and the second external circuit layer C2. The second conductive vias139penetrate the second dielectric layer133and are electrically connected to the second external circuit layer C2and the third circuit layer134. The conductive connection layer138covers the inner wall of the opening137and is connected to the second circuit layer132, the third circuit layer134, and the second external circuit layer C2. The conductive via structure150includes the via T and the conductive material145. The via T penetrates the core layer112of the first substrate110a, the base122of the second substrate120, and the third dielectric layer135of the third substrate130a. The conductive material145covers the inner wall of the via T and is electrically connected to the first external circuit layer C1and the second external circuit layer C2.

Here, the first external circuit layer C1includes the first signal circuit C11and the first ground circuit C12. The second external circuit layer C2includes the second signal circuit C21and the second ground circuit C22. The first signal circuit C11, the conductive material145, and the second signal circuit C21define the signal path L1. The first ground circuit C12, the first conductive vias118, the first circuit layer116, the conductive pillars124, the second circuit layer132, the conductive connection layer138, and the second ground circuit C22define the ground path L2. Since the signal path L1is surrounded by the ground path L2in a closed manner, a favorable high-frequency and high speed circuit may be formed. In addition, by providing the first conductive vias118, the conductive pillars124, and the conductive connection layer138, a gap of a shield may be filled to form a complete shield, which means a closed shielding surface is formed without an electromagnetic interference (EMI) gap region. As a result, signal energy loss and noise interference may be effectively reduced, and reliability of the signal transmission and high-frequency signal integrity may be increased. In addition, the first signal circuit C11and the first ground circuit C12of the first external circuit layer C1are on the same plane, thereby exhibiting coplanarity and favorable flatness. As a result, in a further packaging process, an element (e.g. a chip) may not be damaged so that a product yield and structural reliability may be increased.

In summary, in the embodiment, the signal path L1defined by the first signal circuit C11, the conductive material145, and the second signal circuit C21is surrounded by the ground path L2defined by the first ground circuit C12, the first conductive vias118, the first circuit layer116, the conductive pillars124, the second circuit layer132, the conductive connection layer138, and the second ground circuit C22. That is, the ground path L2with favorable closure is provided around the signal path L1capable of transmitting the high-frequency and high speed signal such as the5G signal so that the favorable high-frequency and high speed circuit may be formed and the circuit board100aof the embodiment may exhibit favorable signal integrity. Here, the high-frequency refers to a frequency greater than 1 GHz, and the high speed refers to a data transmission speed greater than 100 Mbps. It is generally known that data transmission speed and quality are important to a high-frequency circuit, and the main factors affecting the data transmission speed and quality are electrical properties of a transmission material, that is, a dielectric constant (Dk) and a dielectric dissipation factor (DO of the material. By reducing a dielectric constant and a dielectric dissipation factor of a substrate, signal propagation delay time may be effectively reduced. Moreover, a signal transmission speed may be increased, and signal transmission loss may be reduced.

In addition, the second substrate120provided in the embodiment is a circuit board final product, and the first substrate110and the third substrate130are circuit board semi-final products. The first substrate110, the second substrate120, the third substrate130are integrated by press-fitting. Therefore, compared to the conventional technology in which an inner conductor layer and an outer conductor layer of a coaxial via are blocked through a build up process of press-fitting an insulating layer, the manufacturing method of the circuit board100aof the embodiment may prevent high-frequency signal integrity from being affected by impedance mismatch. In addition, the manufacturing process thereof is simplified and the cost is reduced. Furthermore, the first conductive vias118, the conductive pillars124, and the second conductive vias139of the embodiment are not located on the same axis, thereby enhancing reliability of thermal stress of stacked vias.

It should be noted here that the following embodiments adopt the reference numbers and partial contents of the foregoing embodiments, wherein the same reference numbers are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the same content will not be iterated in the following embodiments.

FIG.2AtoFIG.2Bare schematic cross-sectional diagrams of some steps of another manufacturing method of a circuit board according to another embodiment of the disclosure. Referring toFIG.1DandFIG.2A, a manufacturing method of a circuit board100bin the embodiment is similar to the manufacturing method of the circuit board100aabove, and the difference lies in the following. After forming the conductive material layer140as shown inFIG.1D, a fourth dielectric layer160is filled in the via T. The via T is fully filled with the fourth dielectric layer160, and a first surface161and a second surface163of the fourth dielectric layer160that are opposite to each other are respectively flush with an upper surface141and a lower surface143of the conductive material layer140. Here, a dielectric constant (Dk) of the fourth dielectric layer160, for example, ranges from 2.0 to 4.8, and a dielectric dissipation factor (DO of the fourth dielectric layer160is, for example, less than 0.021.

Next, referring toFIG.2AandFIG.2Btogether, the conductive material layer140, the first conductive layer114, and the second conductive layer136are patterned through the photolithography process to form the first external circuit layer C1, the second external circuit layer C2, and the conductive material145covering the inner wall of the via T and electrically connected to the first external circuit layer C1and the second external circuit layer C2. The first external circuit layer C1is located on the core layer112of the first substrate110. The second external circuit layer C2is located on the second dielectric layer133of the third substrate130. The via T and the conductive material145define the conductive via structure150. The manufacture of the circuit board100bis completed.

FIG.3AtoFIG.3Bare schematic cross-sectional diagrams of some steps of another manufacturing method of a circuit board according to another embodiment of the disclosure. Referring toFIG.2AandFIG.3A, a manufacturing method of a circuit board100cin the embodiment is similar to the manufacturing method of the circuit board100babove, and the difference lies in the following. After filling the fourth dielectric layer160in the via T as shown inFIG.2A, referring toFIG.3A, a metal layer170is formed on the conductive material layer140. The metal layer170covers the upper surface141and the lower surface143of the conductive material layer140and the first surface161and the second surface163of the fourth dielectric layer160. Here, a method for forming the metal layer170is, for example, electroless plating or electrolytic plating process, and the metal layer170is, for example, copper; however, the disclosure is not limited thereto.

Next, referring toFIG.3AandFIG.3Btogether, the metal layer170, the conductive material layer140, the first conductive layer114, and the second conductive layer136are patterned through the photolithography process to form the first external circuit layer C1, the second external circuit layer C2, the conductive material145covering the inner wall of the via T and electrically connected to the first external circuit layer C1and the second external circuit layer C2, and a capping layer175. The first external circuit layer C1is located on the core layer112of the first substrate110. The second external circuit layer C2is located on the second dielectric layer133of the third substrate130. The via T and the conductive material145define the conductive via structure150. The capping layer175covers the first external circuit layer C1, the second external circuit layer C2, and the first surface161and the second surface163of the fourth dielectric layer160. The manufacture of the circuit board100cis completed.

FIG.4is a schematic cross-sectional diagram of an electronic device according to an embodiment of the disclosure. Referring toFIG.4, in the embodiment, an electronic device10aincludes, for example, the circuit board100aofFIG.1Eand an electronic device200. The electronic device200is electrically connected to the circuit board100a. The electronic device200includes multiple pads210. In addition, the electronic device10aof the embodiment further includes multiple connection members300disposed between the second external circuit layer C2of the third substrate130aof the circuit board100aand the electronic device200. The electronic device200is electrically connected to the circuit board100athrough the connection members300. The connection members300are, for example, solder balls; however, the disclosure is not limited thereto. In application, an antenna structure may be provided at another side of the circuit board100aopposite to the electronic device200, and the antenna structure and the circuit board100aare electrically connected. In application of integrated circuits and antennas, in the circuit board100aof the embodiment, signal interference on the same plane may be eliminated. Signal energy loss and noise interference may be reduced to enhance the reliability of signal transmission.

FIG.5is a schematic cross-sectional diagram of an electronic device according to another embodiment of the disclosure. Referring toFIG.5, in the embodiment, an electronic device10bincludes, for example, the circuit board100bofFIG.2Band the electronic device200. The electronic device200is electrically connected to the circuit board100b. The electronic device200includes the multiple pads210. In addition, the electronic device10bof the embodiment further includes the multiple connection members300disposed between the second external circuit layer C2of the third substrate130aof the circuit board100band the electronic device200. The electronic device200is electrically connected to the circuit board100bthrough the connection members300. The connection members300are, for example, the solder balls; however, the disclosure is not limited thereto. In application, an antenna structure may be provided at another side of the circuit board100bopposite to the electronic device200, and the antenna structure and the circuit board100bare electrically connected. In application of integrated circuits and antennas, in the circuit board100bof the embodiment, signal interference on the same plane may be eliminated. Signal energy loss and noise interference may be reduced to enhance the reliability of signal transmission.

FIG.6is a schematic cross-sectional diagram of an electronic device according to another embodiment of the disclosure. Referring toFIG.6, in the embodiment, an electronic device10cincludes, for example, the circuit board100cofFIG.3Band the electronic device200. The electronic device200is electrically connected to the circuit board100c. The electronic device200includes the multiple pads210. In addition, the electronic device10cof the embodiment further includes the multiple connection members300disposed between the capping layer175of the circuit board100cand the electronic device200. The electronic device200is electrically connected to the circuit board100cthrough the connection members300. The connection members300are, for example, the solder balls; however, the disclosure is not limited thereto. In application, an antenna structure may be provided at another side of the circuit board100copposite to the electronic device200, and the antenna structure and the circuit board100care electrically connected. In application of integrated circuits and antennas, in the circuit board100cof the embodiment, signal interference on the same plane may be eliminated. Signal energy loss and noise interference may be reduced to enhance the reliability of signal transmission.

In summary of the above, in the design of the circuit board of the disclosure, the conductive via structure penetrates the first substrate, the second substrate, and the third dielectric layer of the third substrate and is electrically connected to the first substrate and the third substrate to define the signal path. The first substrate, the second substrate, and the third substrate are electrically connected through the conductive structures to define the ground path. The ground path surrounds the signal path. Hence, the favorable high-frequency and high speed signal circuit may be formed, and in further application of integrated circuits and antennas, signal interference on the same plane may be eliminated. Signal energy loss and noise interference may be reduced to enhance the reliability of signal transmission.

Although the disclosure has been described with reference to the above embodiments, they are not intended to limit the disclosure. It will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit and the scope of the disclosure. Accordingly, the scope of the disclosure will be defined by the attached claims and their equivalents and not by the above detailed descriptions.