Silicon oxide silicon nitride stack stair step etch

A method for forming a stair-step structure in a stack on a substrate is provided. The method comprises at least one stair step cycle. Each stair step cycle comprises trimming the mask and etching the stack. Etching the stack is provided in a plurality of cycles wherein each cycle comprises etching a SiO2 layer and etching a SiN layer. Etching a SiO2 layer comprises flowing a SiO2 etching gas into the plasma processing chamber, wherein the SiO2 etching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of SF6 and NF3, generating a plasma from the SiO2 etching gas, providing a bias, and stopping the SiO2 layer etch. The etching a SiN layer comprises flowing a SiN etching gas into the plasma processing chamber, comprising a hydrofluorocarbon and oxygen, generating a plasma from the SiN etching gas, providing a bias, and stopping the SiN layer etch.

BACKGROUND

The present disclosure relates to the formation of semiconductor devices. More specifically, the disclosure relates to the formation of stair-step semiconductor devices.

During semiconductor wafer processing, stair-step features are sometimes required. For example, in 3D flash memory devices, multiple cells are stacked up together in chain format to save space and increase packing density. The stair-step structure allows electrical contact with every gate layer. Such stair-step structures may be formed by a plurality of alternating layers of silicon oxide (SiO2) and silicon nitride (SiN), where such stacks are designated as ONON stacks. ONON stacks may also be used to form other semiconductor devices in addition to stair-step semiconductor devices.

SUMMARY

To achieve the foregoing and in accordance with the purpose of the present disclosure, a method for forming a stair-step structure in a stack on a substrate in a plasma processing chamber, wherein the stack comprises a plurality of silicon oxide and silicon nitride bilayers under a mask is provided. The method comprises at least one stair step cycle. Each stair step cycle comprises trimming the mask and etching the stack. Etching the stack is performed in a plurality of cycles wherein each cycle comprises etching a SiO2layer and etching a SiN layer. Etching a SiO2layer comprises flowing a SiO2etching gas into the plasma processing chamber, wherein the SiO2etching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of sulfur hexafluoride (SF6) and nitrogen trifluoride (NF3), generating a plasma from the SiO2etching gas, providing a bias, and stopping the SiO2layer etch. The etching a SiN layer comprises flowing a SiN etching gas into the plasma processing chamber, wherein the SiN etching gas comprises a hydrofluorocarbon and oxygen, generating a plasma from the SiN etching gas, providing a bias, and stopping the SiN layer etch.

These and other features of the present disclosure will be described in more detail below in the detailed description of the disclosure and in conjunction with the following figures.

DETAILED DESCRIPTION OF THE EMBODIMENTS

A traditional approach in etching a stack of silicon oxide (SiO2) and silicon nitride (SiN) bilayers is using a SiO2layer as a mask to etch a SiN layer in a first process and then using SiN as a mask to etch a SiO2layer in a second process. Since a SiN layer is used to act as a mask to etch a SiO2layer and vice versa, selectivity needs to be very high. To provide the desired selectivity, previous methods generated enough polymer to cause tapering of the etch stack sidewalls.

Three dimensional “not and” (3D NAND) staircase etching is an important process. The industry is moving to stacks of 96 bilayers of SiO2and SiN and beyond. Fast throughput is needed for this process to keep the cost down. However, there are always trade-offs between various parameters including, e.g., profile angle, line edge roughness (LER), etch selectivity, and throughput. How to shorten process time while maintaining vertical profile angle of multiple bilayers, good LER, and free corner rounding/faceting becomes extremely challenging.

To facilitate understanding,FIG.1is a high level flow chart of a process that may be used in an embodiment of the disclosure. The embodiment is used to form a stair-step structure in a stack. An organic mask is formed over a stack of alternating SiO2and SiN (ONON) layers (step104).

FIG.2Ais a cross sectional view of a stack200comprising a plurality of layers of memory stacks204formed over a wafer208. In this embodiment, each memory stack of the plurality of memory stacks is formed by bilayers of a layer of SiO2216on top of a layer of SiN212forming an ONON stack. A mask220is formed over the memory stacks204(step104). The mask220may be a photoresist mask that is formed using a spin on process and a photolithographic patterning. In the alternative, the mask220may be a spun on or otherwise applied organic layer, without photolithographic patterning.

The mask220is trimmed (step108). If the mask220is an organic mask, an organic trimming process may be used to trim the mask220.FIG.2Bis a cross sectional view of the stack200after the mask220has been trimmed.

After the mask220is trimmed (step108), a plurality of cycles of etching the SiO2layer (step112) and etching the SiN layer (step116) is provided.FIG.3is a more detailed flow chart of the etching the SiO2layer (step112). A SiO2etching gas is flowed into a processing chamber (step304). The SiO2etching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of sulfur hexafluoride (SF6) and nitrogen trifluoride (NF3). In this example, the SiO2etching gas consists essentially of 10 to 100 standard cubic centimeters per minute (sccm) SF6, 50-250 sccm fluoroform (CHF3), 100-500 sccm helium (He), and 10-200 sccm NF3. CHF3is the hydrofluorocarbon. He is the inert bombardment gas. The SiO2etching gas is formed into a plasma (step308). Inductively coupled radio frequency (RF) power is provided at 13.56 megahertz (MHz) with a power of at least 2000 watts. A low bias of less than 150 volts (V) is provided (step312) to cause ion bombardment from helium ions to activate a surface of the stack for ion-assisted etching, wherein the in-situ plasma etches the activated surface of the stack. A chamber pressure of 10 to 20 millitorr (mTorr) is provided. The etch process is stopped after 5 seconds. The etch process may be stopped by stopping the flow of the SiO2etching gas (step316). In addition, the RF power may be stopped.FIG.2Cis a cross-sectional view of the stack200after a top SiO2layer216has been etched (step112) in the stack200. A benefit of the separate SiO2recipe is that the SiO2recipe has a lean oxide etch chemistry. The lean oxide etch chemistry provides a vertical ONON etch profile.

After the etch of the top SiO2layer216is completed (step112) the top SiN layer212is etched (step116).FIG.4is a more detailed flow chart of the etching the SiN layer (step116). A SiN etching gas is flowed into the processing chamber (step404). The SiN etching gas comprises a hydrofluorocarbon and oxygen (O2). In this example, the SiN etching gas consists essentially of 50 to 150 sccm carbon tetrafluoride (CF4), 50 to 200 sccm fluoromethane (CH3F), and 50 to 150 sccm O2. CH3F is the hydrofluorocarbon. The SiN etching gas is formed into a plasma (step408). Inductively coupled RF power is provided at 13.56 MHz with a power of at least 2000 watts. A bias of 150 to 400 volts is provided (step412). A chamber pressure of 30 to 100 mTorr is provided. The etch process is stopped after 5 seconds. The etch process may be stopped by stopping the flow of the SiN etching gas (step416). In addition, the RF power may be stopped.FIG.2Dis a cross-sectional view of the stack200after a top SiN layer212has been etched (step116) in the stack200. Since the etch is selective, the SiO2layer216acts as an etch stop. The top SiO2layer216may act as an etch mask.

The etching of a SiO2layer216(step112) and the etching of a SiN layer212(step116) are repeated (step120) twice.FIG.2Eis a cross-sectional view of the stack200after the etching of a SiO2layer216(step112) and the etching of a SiN layer212(step116) are repeated (step120) twice. A first step224of a height of three bilayers has been etched.

The stair is not complete (step124) and the process is returned to the step of trimming the mask (step108). An example of a recipe for trimming an organic mask provides a pressure between 30 to 400 mTorr. A trim gas is flowed into a process chamber, where the trimming gas is 1000 sccm O2, 40 sccm N2, and 50 sccm C4F6or NF3. The trimming gas is formed into a plasma. The trimming gas is stopped when the trim is completed.FIG.2Fis a cross-sectional view of the stack200, after the mask220is trimmed.

The steps of etching a SiO2layer216(step112) and etching a SiN layer212(step116) are cyclically performed three times. The stair step etching in this embodiment is completed (step124).FIG.2Gis a cross-sectional view of the stack200after a second stair-step228has been etched. In this example, three bilayers of SiO2and SiN are etched to form the second step228, while deepening the first step224. The deepening of the first step224etches the first step, without using a mask and provides a vertical sidewall and a corner, without faceting.

The completed stair provides an improved structure over stairs created using other processes in a manner that is faster than other processes. The above embodiment has less tapering than using a process that uses more polymer to increase selectivity. Because the process uses a low bias for etching at least one layer of each bilayer, faceting and corner rounding is reduced. Normally, a lower bias would result in a lower throughput. However, the chemistries of the SiO2etching gas and the SiN etching gas are able to provide a high throughput with a low bias. In addition, a higher bias may be used for etching only one layer of the bilayer. In addition, this embodiment decreases line edge roughness. Since each step in this embodiment is three bilayers, in this embodiment, the stack has at least six bilayers of SiO2and SiN.

The stair-steps may be formed in one or more directions (X or Y) in other embodiments. In other embodiments, other feature shapes may be etched into a plurality of silicon oxide and silicon nitride bilayers. Various embodiments reduce corner faceting and sidewall etching on non-stair step structures, while increasing the etch rate of the bilayers.

In other embodiments, the first layer is a silicon nitride layer. In various embodiments, subsequent steps may be provided, such as removing any remaining mask220. Various embodiments may be used to etch high aspect ratio features, such as contacts.

In various embodiments, the SiO2etch gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of SF6or NF3. In various embodiments, the SiO2etch gas is oxygen free. The presence of oxygen during etching the SiO2layer (step112), can cause the organic mask220to be laterally etched during the SiO2vertical etch (step112). The lateral etch of the organic mask reduces profile control. In various embodiments, the hydrofluorocarbon may be at least one of CH2F2, CH3F, or CHF3.

In various embodiments, the bias provided during the etching the SiN layer (step116) has a magnitude that is greater than the magnitude of the bias during the etching the SiO2layer (step112). For example, in some embodiments, the etching the SiN layer (step116) has a bias magnitude of between 150 to 400 volts, inclusive, and the etching the SiO2layer (step112) has a bias of less than 150 volts. In other embodiments, the etching the SiN layer (step116) has a bias magnitude of between 150 to 700 volts and the etching the SiO2layer (step112) has a bias between 20 to 100 volts, inclusive.

In various embodiments, the chamber pressure during the etching the SiN layer (step116) is greater than the chamber pressure during the etching the SiO2layer (step112). For example, in some embodiments, the etching the SiN layer (step116) has a chamber pressure greater than 30 mTorr, such as between 30 mTorr and 100 mTorr, and the etching the SiO2layer (step112) has a chamber pressure less than 20 mTorr.

Various embodiments provide a fast etch process and increased throughput. For example, the etching of the SiO2layer (step112) may be performed in no more than 10 seconds. In various embodiments, the etching of the SiN layer (step116) may be performed in no more than 10 seconds. In various embodiments, the etching of the SiN layer (step116) may be performed in no more than 5 seconds. In various embodiments, the etching of a bilayer of SiN and SiO2may be performed in no more than 15 seconds.

In various embodiments, the etching the SiN layer (step116) selectively etches the SiN layer212with respect to SiO2layer216with a selectivity in the range of 2:1 to 4:1. The etching the SiN layer (step116) also selectively etches the SiN layer212with respect to the mask220. In various embodiments, the etching of the SiO2layer (step112) selectively etches the SiO2layer216with respect to the mask220. The etching the SiO2layer (step112) does not selectively etch the SiO2layer216with respect to the SiN layer212. Endpoint control is used to stop the etching of the SiO2layer216.

In an embodiment, the stack comprises at least six bilayers of silicon oxide and silicon nitride. In another embodiment, the stack comprises more than 60 bilayers of silicon oxide and silicon nitride. In the above embodiment, each stair step is three bilayers. In other embodiments, each stair step may be from three to ten bilayers. In such embodiments, the etching of the SiO2layer (step112) and the etching of the SiN layer (step116) are cyclically repeated for three to ten times for each stair step. If a stack has more than 60 bilayers and there are three bilayers in each step, a stair step etch process may be repeated at least twenty times. In such an embodiment, depending on the thickness of the mask220and the selectivity of an etch process, the mask220may be only useful for forming around seven stair steps. In such a case, a new mask220may be formed every seven stair steps, so that at least three masks220are applied during the etching of the at least twenty stair steps.

In an embodiment, during the flowing of the SiN etching gas, at least some of the hydrofluorocarbon is flowed from sides of the plasma processing chamber in a direction with a component that is parallel to a top surface of the top of the stack200. As a result, the hydrofluorocarbon flowed from the sides of the plasma processing chamber flows first over the sides of the substrate208towards the center of the substrate208, where in this example the substrate208is in the form of a disk. The ratio of the flow of hydrofluorocarbon from the top of the plasma processing chamber to the flow of the hydrofluorocarbon from the sides of the plasma processing chamber may be used as a tuning knob. The tuning knob allows tuning to improve process uniformity. In this embodiment, hydrofluorocarbon is not flowed from the sides of the plasma processing chamber during the flowing of the SiO2etching gas.

FIG.5schematically illustrates an example of a plasma processing system500which may be used to process the substrate208in accordance with one embodiment. The plasma processing system500includes a plasma reactor502having a plasma processing chamber504, enclosed by a chamber wall562. A plasma power supply506, tuned by a match network508, supplies power to a transformer coupled plasma (TCP) coil510located near a power window512to create a plasma514in the plasma processing chamber504by providing an inductively coupled power. The TCP coil (upper power source)510may be configured to produce a uniform diffusion profile within the plasma processing chamber504. For example, the TCP coil510may be configured to generate a toroidal power distribution in the plasma514. The power window512is provided to separate the TCP coil510from the plasma processing chamber504while allowing energy to pass from the TCP coil510to the plasma processing chamber504. A wafer bias voltage power supply516tuned by a match network518provides power to an electrode520to set the bias voltage on the substrate208. The electrode520provides a chuck for the substrate208, where the electrode520acts as an electrostatic chuck. A substrate temperature controller566is controllably connected to a Peltier heater/cooler568. A controller524sets points for the plasma power supply506, the substrate temperature controller566, and the wafer bias voltage power supply516.

The plasma power supply506and the wafer bias voltage power supply516may be configured to operate at specific radio frequencies such as, 13.56 MHz, 27 MHz, 2 MHz, 400 kilohertz (kHz), or combinations thereof. Plasma power supply506and wafer bias voltage power supply516may be appropriately sized to supply a range of powers in order to achieve desired process performance. For example, in one embodiment, the plasma power supply506may supply the power in a range of 50 to 5000 Watts, and the wafer bias voltage power supply516may supply a bias voltage in a range of 20-1500 V. In addition, the TCP coil510and/or the electrode520may be comprised of two or more sub-coils or sub-electrodes, which may be powered by a single power supply or powered by multiple power supplies.

As shown inFIG.5, the plasma processing system500further includes a gas source530. The gas source530provides gas or remote plasma to a center feed536and a side feed538. The center feed536and the side feed538are in the form of nozzles. The center feed536is located approximately above the center of the substrate208. The side feed538may be one or more nozzles located closer to sides of the substrate208than the center of the substrate208. The center feed536provides gas with more of a vertical component. The vertical component is perpendicular to the surface of the substrate208, as shown by arrow V. The side feed538has more of a horizontal component than the center feed. The horizontal component is parallel to the surface of the substrate208, as shown by arrow H. As shown, the gas from the side feed538passes from the sides of the substrate208towards the center of the substrate208. The process gases and byproducts are removed from the plasma processing chamber504via a pressure control valve542and a pump544, which also serve to maintain a particular pressure within the plasma processing chamber504. The gas source530is controlled by the controller524. A Kiyo by Lam Research Corp. of Fremont, Calif., may be used to practice an embodiment.

FIG.6is a high level block diagram showing a computer system600, which is suitable for implementing a controller524used in embodiments of the present disclosure. The computer system may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge super computer. The computer system600includes one or more processors602, and further can include an electronic display device604(for displaying graphics, text, and other data), a main memory606(e.g., random access memory (RAM)), storage device608(e.g., hard disk drive), removable storage device610(e.g., optical disk drive), user interface devices612(e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communication interface614(e.g., wireless network interface). The communication interface614allows software and data to be transferred between the computer system600and external devices via a link. The system may also include a communications infrastructure616(e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices/modules are connected.

Information transferred via communications interface614may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface614, via a communication link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and/or other communication channels. With such a communications interface, it is contemplated that the one or more processors602might receive information from a network, or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments of the present disclosure may execute solely upon the processors or may execute over a network such as the Internet, in conjunction with remote processors that share a portion of the processing.

The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.

The controller524is used to provide a tuned ratio of the flow of hydrofluorocarbon flowed through the center feed536and the flow of the hydrofluorocarbon flowed through the side feed538. The tuning allows control of the ratio of the flow of the hydrofluorocarbon perpendicular to the surface of the substrate208with respect to the flow of the hydrofluorocarbon parallel to the surface of the substrate208.

While this disclosure has been described in terms of several preferred embodiments, there are alterations, permutations, and various substitute equivalents, which fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure.