Lithography process modeling of asymmetric patterns

A lithography process model is generated to account for asymmetric printing of a feature of a target pattern to help better predict how the target pattern will print. The process model for one embodiment may be generated based on data generated from measurements of spacings between symmetrically defined features of printed test patterns to help predict edge offsets of the feature relative to the target pattern when printed and/or to help predict a dimension of the feature when printed. The process model may be used to help design, manufacture, and/or inspect a mask to help print the target pattern more accurately and therefore help manufacture an integrated circuit (IC), for example, that more accurately matches its intended layout.

BACKGROUND

1. Field of the Invention

The present invention relates generally to the field of lithography processing. More particularly, the present invention relates to the field of lithography process modeling.

2. Description of Related Art

Lithography process modeling may be used to account for process effects at various stages in manufacturing integrated circuits (ICs), for example, to help produce ICs that more accurately match their intended layout. Process modeling therefore helps increase IC yield and/or allows ICs to be designed with relatively smaller features to help increase performance and reduce power consumption.

Process models may be used to help account for optical proximity effects, phase shifting effects, distortions introduced by resist processes, and/or etching process effects, for example, in performing optical proximity correction (OPC), phase shifting, silicon verification, and/or mask defect prediction, for example. The N-abled™ Process developed by Numerical Technologies, Inc. of San Jose, Calif., for example, enables the generation of such process models.

A process model may be initially generated from various stepper and optical lithography parameters that are to be used in printing a target pattern. To account for optical and/or chemical effects not captured in the initial model, the model may be calibrated based on actual linewidth measurements on wafer of test patterns printed using those parameters. The calibrated model may then be used, for example, to help predict one or more critical dimensions (CDs) for the target pattern in designing, manufacturing, and/or inspecting a mask to print the target pattern.

As one example, a process model may be used to help predict the printed width of a polysilicon line of a target pattern. If the line is to be printed using phase shifting proximate to and on only one side of the line, however, the line will be printed asymmetrically, that is with different edge offsets, relative to the target pattern. Because the model does not account for such asymmetric printing of features and therefore presumes features will be printed symmetrically, that is with substantially the same edge offsets relative to the target pattern, any resulting mask may not print the target pattern with sufficient accuracy because the line will be printed in a position different than that expected from the model.

The performance of OPC on the target pattern using the model may therefore lead to contact misplacement, bridging, and/or a minimum spacing violation, for example. Because such error conditions may not be revealed until a mask is manufactured and either inspected or used to print the target pattern, any resulting mask and the time and resources expended to manufacture and inspect the mask may be wasted unless the mask can be repaired. This is so even if the resulting mask layout is verified against the target pattern by simulating the printing of the mask layout because the simulated printing of the mask layout will be based on the same model.

SUMMARY

Methods and apparatuses for lithography process modeling of asymmetric patterns are described. A lithography process model is generated to account for asymmetric printing of a feature of a target pattern to help better predict how the target pattern will print. The process model may therefore be used to help design, manufacture, and/or inspect a mask to help print the target pattern more accurately and therefore help manufacture an integrated circuit (IC), for example, that more accurately matches its intended layout.

For one method, data is received to account for asymmetric printing of a feature of a pattern. A process model is generated based on the received data to help predict how the pattern will print.

For one embodiment, data resulting from a first measurement of a first spacing between two features of a printed first test pattern and from a second measurement of a second spacing between two features of a printed second test pattern is received.

The first test pattern for one embodiment is printed using one mask defining a phase shifter to expose a region of a layer over a substrate to radiation through the phase shifter and another mask to define in the layer two features on generally opposite sides of the exposed region.

The second test pattern for one embodiment is printed using one mask defining two phase shifters to expose respective regions of a layer over a substrate to radiation through the two phase shifters and using another mask to define two features in the layer generally between the two exposed regions with one feature proximate to one of the two exposed regions and the other feature proximate to the other one of the two exposed regions.

The process model for one embodiment may be used to perform optical proximity correction (OPC) on a layout. The process model may therefore be used to help minimize or avoid creating a contact misplacement, bridging, or a minimum spacing violation, for example, in performing OPC.

The process model for one embodiment may be used to simulate how a mask layout will print. The process model may therefore be used to help identify errors, such as out-of-tolerance regions for example, in a mask layout more accurately when verifying the simulated print against, for example, an integrated circuit layout.

The process model for one embodiment may be used to simulate how a mask will print. The process model may therefore be used to help assess the severity of any defects and contaminants in a mask with more accuracy.

A computer-readable medium having instructions which, when executed by a computer system, cause the computer system to perform the method is also described.

An apparatus comprises means for receiving data to account for asymmetric printing of a feature of a pattern and means for generating a process model based on the received data to help predict how the pattern will print.

For one embodiment, the receiving means comprises means for receiving data resulting from a first measurement of a first spacing between two features of a printed first test pattern and from a second measurement of a second spacing between two features of a printed second test pattern.

The apparatus for one embodiment comprises means for performing optical proximity correction on a layout using the process model. The apparatus for one embodiment comprises means for simulating how a mask layout will print using the process model. The apparatus for one embodiment comprises means for simulating how a mask will print using the process model.

A system comprises a model generator to generate a process model and a model calibrator to calibrate the process model to account for asymmetric printing of a feature.

For one embodiment, the model calibrator is to calibrate the process model based on data resulting from a first measurement of a first spacing between two features of a printed first test pattern and from a second measurement of a second spacing between two features of a printed second test pattern.

The system for one embodiment comprises an optical proximity correction tool to perform optical proximity correction on a layout using the process model. The system for one embodiment comprises a layout verification tool to simulate how a mask layout will print using the process model. The system for one embodiment comprises a mask inspection tool to simulate how a mask will print using the process model.

A mask is manufactured in accordance with a mask layout produced by performing optical proximity correction on a layout defining a pattern using a process model that accounts for asymmetric printing of a feature of the pattern.

An integrated circuit comprises a layer over a substrate. The layer comprises a feature defined by performing optical proximity correction on a layout using a process model that accounts for asymmetric printing of the feature.

DETAILED DESCRIPTION

The following detailed description sets forth an embodiment or embodiments in accordance with the present invention for lithography process modeling of asymmetric patterns.

Embodiments of the invention include methods, apparatuses, systems, and computer-readable media having instructions for generating a lithography process model that accounts for asymmetric printing of one or more features of a target pattern to help better predict how the target pattern will print. Embodiments of the invention also include methods, apparatuses, systems, and computer-readable media having instructions for using a lithography process model that accounts for asymmetric printing of one or more features of a target pattern to help design, manufacture, and/or inspect a mask to help print the target pattern more accurately and therefore help manufacture an integrated circuit (IC), for example, that more accurately matches its intended layout. Embodiments of the invention also include masks, mask sets, and integrated circuits (ICs) manufactured using a lithography process model that accounts for asymmetric printing of one or more features.

An example of a feature that prints asymmetrically is first described with reference toFIGS. 1 and 2. Embodiments of the invention are then described, with reference toFIGS. 3,4, and5, in the context of how a lithography process model is generated to account for asymmetric printing of one or more features, using the feature ofFIGS. 1 and 2as an example. Embodiments of the invention are then described, with reference toFIG. 6, in the context of a system that generates and uses a lithography process model that accounts for asymmetric printing of one or more features to help manufacture an integrated circuit (IC) that more accurately matches its intended layout.

Example Asymmetric Pattern

FIG. 1illustrates an example of a phase-shifting mask (PSM) portion110and a trim mask portion120that, when used to print a target pattern in a layer130over a substrate, cause a feature of the pattern to be printed asymmetrically, that is with different edge offsets, relative to the target pattern. In the example ofFIG. 1, PSM portion110and trim mask portion120cause a line132to be printed asymmetrically because PSM portion110phase shifts radiation projected onto layer130in a region proximate to and on only one side131of line132as defined by trim mask portion120.FIG. 2illustrates the asymmetric printing of line132.

As illustrated in the example ofFIG. 1, PSM portion110and trim mask portion120are used to print line132and another line138in layer130. Layer130comprises a suitable radiation-sensitive material, such as a suitable photoresist material for example.

PSM portion110is first used to expose layer130to suitable radiation, such as visible light or ultra-violet light for example, passing through a phase shifter112and a phase shifter114to help define line138with a width less than the wavelength of the radiation. Phase shifter112may be, for example, an approximately 0° phase shifter, and phase shifter114may be, for example, an approximately 180° phase shifter. PSM portion110defines phase shifters112and114in a dark field116to help prevent radiation from passing through other regions of PSM portion110onto layer130.

Trim mask portion120is then used to expose layer130to suitable radiation passing through a bright field122. Trim mask portion120defines in bright field122a trim region124shaped to define lines132and138and to help protect areas of layer130previously exposed to phase shifted radiation through PSM portion110from being exposed to radiation projected onto trim mask portion120.

As the exposure to radiation modifies the molecular composition of layer130, layer130may then be processed to remove the exposed regions to form lines132and138. Line132and138may then be transferred to an underlying layer by using layer130as a mask in selectively etching only those regions of the underlying layer exposed through layer130. The underlying layer may comprise polysilicon, for example, to form corresponding polysilicon lines for an integrated circuit (IC), for example.

Because line132is proximate to a region of layer130exposed to radiation phase shifted through phase shifter114on only one side131and because line132is not proximate to a region of layer130exposed to phase shifted radiation on at least one other side, such as a side133opposite side131for example, line132is defined asymmetrically in layer130relative to the target pattern as illustrated inFIG. 2.FIG. 2illustrates how line132is defined with side131having a larger edge offset135as compared to the edge offset136on side133.

Modeling of Asymmetric Patterns

To account for asymmetric printing of a feature of a target pattern, a lithography process model for one embodiment may be generated based on data generated from measurements of spacings between symmetrically defined features of printed test patterns. A test pattern may be designed and printed with generally symmetric features with sides that face one another and that are defined similarly as one side of the feature of the target pattern. The edge offset of the one side of the feature of the target pattern when printed may then be estimated for one embodiment, for example, by measuring the spacing defined by the facing sides of the generally symmetric features of the printed test pattern, subtracting the known distance between the generally symmetric features of the test pattern as defined by its design or layout, and dividing the difference by two. By designing and printing test patterns to estimate edge offsets on opposite sides of the feature of the target pattern when printed, a dimension of the feature defined by the opposite sides of the feature may also be estimated, for example, by subtracting the sum of the estimated edge offsets from the known dimension defined by the design or layout of the target pattern. A lithography process model generated based on such measurements or estimates may therefore be used to help better predict how the target pattern will print.

FIG. 3illustrates, for one embodiment, a flow diagram300to generate a lithography process model that accounts for the asymmetric printing of a feature. Although described in the context of being generated to account for the asymmetric printing of line132ofFIG. 1due to the proximity of line132to a region exposed to phase shifted radiation on only one side131, a lithography process model may be generated in accordance with flow diagram300to account for the asymmetric printing of any suitable one or more features of any suitable target pattern due to any suitable circumstance.

For block302ofFIG. 3, a first test pattern and a second test pattern are printed in a layer over a substrate. The first and second test patterns used may depend, for example, on the feature of the target pattern to be printed. The first test pattern for one embodiment may be designed and printed with generally symmetric features with sides that face one another and that are defined similarly as one side of the feature of the target pattern. The second test pattern for one embodiment may be designed and printed with generally symmetric features with sides that face one another and that are defined similarly as an opposite side of the feature of the target pattern. The dimensions of features of the first and second test patterns may depend, for example, on the anticipated size of the feature of the target pattern to be printed.

The first and second test patterns for one embodiment may be printed in a layer of the same or similar material in accordance with a predetermined set of lithography process parameters to be used to print the target pattern. Suitable lithography process parameters include, without limitation, stepper specifications such as wavelength (λ), numerical aperture (NA), and incoherence factor (σ), for example; illumination; photoresist; thin film; aberrations; multiple exposures; process analysis; and/or multiple mask types.

FIG. 4illustrates one example of a first test pattern that may be used to help account for the asymmetric printing of line132ofFIG. 1. The first test pattern in the example ofFIG. 4comprises two generally parallel lines432and434printed in a layer430using a PSM portion410and a trim mask portion420. PSM portion410and trim mask portion420for one embodiment are designed and manufactured in accordance with a first test pattern layout, for example, in GDS-II stream format.

As illustrated inFIG. 4, PSM portion410defines a phase shifter414in a dark field416to expose a region of layer430to radiation passing through phase shifter414. Phase shifter414for one embodiment shifts the phase of radiation passing through phase shifter414similarly as phase shifter114inFIG. 1. Trim mask portion420defines in a bright field422a trim region424shaped to define lines432and434in layer430in a generally parallel relationship and proximate to and on generally opposite sides of the region in layer430exposed to radiation through PSM portion410. Trim region424also helps protect areas of layer430previously exposed to radiation through PSM portion410from being exposed to radiation projected onto trim mask portion420.

The first test pattern for one embodiment may be used to model the edge offset for side131of line132ofFIG. 1when printed because PSM portion410and trim mask portion420define the sides of lines432and434that face one another similarly as side131of line132ofFIG. 1, that is with phase shifting proximate to and on only the same one side131of line132.

Although described as using PSM portion410first and then using trim mask portion420to print the first test pattern, trim mask portion420for another embodiment may be used prior to using PSM portion410.

FIG. 5illustrates one example of a second test pattern that may be used to help account for the asymmetric printing of line132ofFIG. 1. The second test pattern in the example ofFIG. 5comprises four generally parallel lines531,532,533, and534printed in a layer530using a PSM portion510and a trim mask portion520. PSM portion510and trim mask portion520for one embodiment are designed and manufactured in accordance with a second test pattern layout, for example, in GDS-II stream format.

As illustrated inFIG. 5, PSM portion510defines phase shifters511,512,513, and514in a dark field516to expose regions of layer530to radiation passing through phase shifters511–514. Phase shifters511and514for one embodiment shift the phase of radiation passing through phase shifter511and514, respectively, similarly as phase shifter112inFIG. 1. Phase shifters512and513for one embodiment shift the phase of radiation passing through phase shifter512and513, respectively, similarly as phase shifter114inFIG. 1.

Trim mask portion520defines trim regions524and526in a bright field522. Trim region524is shaped to define line531in layer530proximate to and between regions exposed to radiation through phase shifters511and512of PSM portion510. Trim region524is also shaped to define lines531and532in layer530in a generally parallel relationship and proximate to and on generally opposite sides of the region exposed to radiation through phase shifter512of PSM portion510. Trim region526is shaped to define line534in layer530proximate to and between regions exposed to radiation through phase shifters513and514of PSM portion510. Trim region526is also shaped to define lines533and534in layer530in a generally parallel relationship and proximate to and on generally opposite sides of the region exposed to radiation through phase shifter513of PSM portion510. Trim mask portion520defines trim regions524and526to define lines532and533in a generally parallel relationship generally between the regions exposed to radiation through phase shifters512and513of PSM portion510with line532proximate to the region exposed to radiation through phase shifter512and with line533proximate to the region exposed to radiation through phase shifter513. Trim regions524and526also help protect areas of layer530previously exposed to radiation through PSM portion510from being exposed to radiation projected onto trim mask portion520.

The second test pattern for one embodiment may be used to model the edge offset for side133of line132ofFIG. 1when printed because PSM portion510and trim mask portion520define the sides of lines532and533that face one another similarly as side133of line132ofFIG. 1, that is with phase shifting proximate to and on only the opposite one side131of line132.

Although described as using PSM portion510first and then using trim mask portion520to print the second test pattern, trim mask portion520for another embodiment may be used prior to using PSM portion510.

For one embodiment for block302ofFIG. 3, PSM portion410ofFIG. 4and PSM portion510ofFIG. 5are portions of the same PSM, and trim mask portion420ofFIG. 4and trim mask portion520ofFIG. 5are portions of the same trim mask.

For another embodiment, PSM portion410and PSM portion510are portions of different masks, and trim mask portion420and trim mask portion520are portions of different masks. The first test pattern and the second test pattern for one embodiment may then be printed on layers over different substrates.

For block304ofFIG. 3, an underlying layer exposed through the layer printed with the first and second test patterns may be etched using a suitable etching process to transfer the first and second test patterns to the underlying layer. The underlying layer for one embodiment may comprise the same or similar material as that of the layer to be patterned with the target pattern. For one embodiment where the target pattern is to be transferred to a layer comprising polysilicon, for example, the first and second test patterns for block304may be transferred to a layer comprising polysilicon. The etching process to transfer the first and second test patterns to an underlying layer for one embodiment may be the same or a similar etching process to be used in similarly transferring the target pattern to an underlying layer.

Performing operations for block304helps capture etching process effects in generating a process model and therefore may be done to help better predict how a target pattern will print. Performing operations for block304is nevertheless optional as a layer printed with the first and second test patterns without being subjected to an etching process may also be used in generating a process model.

For another embodiment where the first test pattern and the second test pattern are printed on layers over different substrates, operations for block304may be performed to transfer the first and second test patterns onto respective underlying layers over their respective substrates.

For block306ofFIG. 3, the spacing between the two generally symmetrically defined features of the first test pattern is measured. This spacing may be measured in any suitable manner using any suitable equipment. The spacing may, for example, be measured manually or automatically using suitable equipment comprising a scanning electron microscope (SEM).

Using the example test pattern ofFIG. 4, a spacing435defined by the sides of lines432and434facing one another is measured. Spacing435spans the region of layer430previously exposed to radiation through PSM portion410. As side131of line132ofFIG. 1is also proximate to a region previously exposed to phase shifted radiation, the measurement of spacing435in the actual printed test pattern may be used to help model the edge offset at side131of line132relative to its target pattern when printed.

For one embodiment where the first test pattern is transferred to an underlying layer, the spacing between features of either the layer printed with the first test pattern for block302or of the underlying layer may be measured.

For block308ofFIG. 3, the spacing between the two generally symmetrically defined features of the second test pattern is measured. This spacing may be measured in any suitable manner using any suitable equipment. The spacing may, for example, be measured manually or automatically using suitable equipment comprising a scanning electron microscope (SEM).

Using the example test pattern ofFIG. 5, a spacing535defined by the sides of lines532and533facing one another is measured. Spacing535spans the region of layer530on an opposite side of line532from the region of layer530previously exposed to radiation through phase shifter512and on an opposite side of line533from the region of layer530previously exposed to radiation through phase shifter513. As side133of line132ofFIG. 1is similarly opposite the side131of line132proximate to a region previously exposed to phase shifted radiation, the measurement of spacing535in the actual printed test pattern may be used to help model the edge offset at side133of line132relative to its target pattern when printed.

For one embodiment where the second test pattern is transferred to an underlying layer, the spacing between features of either the layer printed with the second test pattern for block302or of the underlying layer may be measured.

For block310ofFIG. 3, data resulting from the measurements of the first and second test patterns is generated. Any suitable data may be generated from measurements of the first and second test patterns. For one embodiment, the values of the measurements are generated in the form of digital signals. For another embodiment, estimated values of printed edge offsets are calculated from the measurements and generated in the form of digital signals. An estimated value of a printed edge offset for one embodiment may be manually or automatically calculated, for example, by subtracting the known distance between the generally symmetric features of a test pattern as defined by its layout from the measured spacing between the generally symmetric features of the corresponding printed test pattern and dividing the difference by two.

The generated measurement data for one embodiment is arranged or stored in a measurement file. For one embodiment, measurement data may be manually entered into a measurement file. For another embodiment, measurement data may be automatically entered into a measurement in response to the generation of the measurement data. As one example, equipment used to perform measurements may interface with a computer system to transmit values of measurements to the computer system. The computer system for one embodiment may then automatically enter the measurement values into a measurement file. The computer system for another embodiment may automatically calculate estimated edge offset values and enter them into a measurement file.

For block312, a lithography process model is generated based on the measurement data generated for block310. The process model may be generated in any suitable manner based on the measurement data generated for block310. The process model for one embodiment may be generated by generating an initial optical model from a predetermined set of lithography process parameters and calibrating the initial optical model based on the measurement data. The process model for another embodiment may be generated by receiving an initial process model and calibrating the received process model based on the measurement data. The initial process model may either be an optical model newly generated from a set of lithography process parameters or a process model previously calibrated based on other measurement data.

The resulting process model may then be used to help predict edge offsets of a feature relative to a target pattern when printed and/or to help predict a dimension of the feature when printed. The resulting process model may therefore be used to help better predict how the target pattern will print.

Although described in the context of blocks302–312, the operations for flow diagram300may be performed in any suitable order. Also, the performance of any suitable operation may or may not overlap in time the performance of any other suitable operation. As one example, operation(s) for block308may be performed prior to or as operation(s) for block306are performed.

A process model for one embodiment may be generated by executing suitable instructions by one or more processors of a computer system. Such instructions may be stored on any suitable computer-readable medium from which the instructions may be transmitted to the computer system. The computer system may receive instructions from a suitable computer-readable medium that is a part of the computer system and/or from a suitable computer-readable medium external to the computer system at a local or remote location. The computer system may store any data, such as the generated process model for example, on a suitable computer-readable medium that is a part of the computer system and/or on a suitable computer-readable medium external to the computer system at a local or remote location. As used in this description, suitable computer-readable media include, without limitation, a hard disk device, an optical disk device such as a compact disc (CD) or digital versatile disc (DVD) device for example, a Bernoulli disk device such as a Jaz or Zip disk device for example, a flash memory device, a file server, and/or any other suitable memory device.

Example Uses of Modeling of Asymmetric Patterns

A lithography process model that accounts for asymmetric printing of a feature of a target pattern may be used for any suitable purpose. The process model may be used, for example, to help design, manufacture, and/or inspect a mask to help print the target pattern more accurately. The process model may therefore be used to help manufacture an integrated circuit (IC), for example, that more accurately matches its intended layout. Although described in the context of ICs, the present invention may be used to help print target patterns in manufacturing any suitable objects.

FIG. 6illustrates, for one embodiment, a system600to help manufacture an integrated circuit695that more accurately matches its intended layout by generating and using a lithography process model that accounts for the asymmetric printing of one or more features. As illustrated inFIG. 6, system600comprises a process model generator610, a process model calibrator620that accounts for asymmetric patterns, an integrated circuit layout generator630, a phase-shifting mask (PSM) tool641, an optical proximity correction (OPC) tool642, a layout verification tool650, a mask data preparation (MDP) tool660, mask manufacturing equipment670, a mask inspection tool680, and lithography equipment690.

Process model generator610receives a predetermined set of lithography process parameters612to be used to print a target pattern in manufacturing IC695. Process model generator610generates a preliminary process model614based on the predetermined set of lithography process parameters612.

Process model calibrator620receives preliminary process model614and measurement data622generated from measurements of test patterns printed using the predetermined set of lithography process parameters612to account for optical and/or chemical effects not captured by preliminary process model614. Measurement data622for one embodiment includes measurement data generated from measurements of printed test patterns, such as those ofFIGS. 4 and 5for example, to account for asymmetric printing of one or more features. Process model calibrator620calibrates preliminary process model614based on measurement data622to generate calibrated process model624.

IC layout generator630generates an IC layout635defining a target pattern for one or more layers of IC695. PSM tool641and OPC tool642process the IC layout635for a layer to produce a mask layout645. PSM tool641introduces phase-shifting mask (PSM) regions in IC layout635to help define features with dimensions less than the wavelength of the radiation to be used in printing IC layout635. OPC tool642applies OPC structures to IC layout635to compensate for nonlinear distortions caused by optical diffraction and resist process effects, for example, to help enhance the printability of IC layout635. OPC tool642for one embodiment may use calibrated process model624to better predict how IC layout635will print in applying OPC structures to IC layout635.

Layout verification tool650verifies mask layout645against one or more design rules and/or against IC layout635. Layout verification tool650for one embodiment may simulate how mask layout645will print and verify the simulated print against IC layout635to help identify any errors, such as out-of-tolerance regions for example. Layout verification tool650for one embodiment may use calibrated process model624to better predict how mask layout645will print.

MDP tool660generates mask data based on mask layout645, and mask manufacturing equipment670manufactures one or more masks in a mask set675based on the generated mask data.

Mask inspection tool680may be used to inspect the manufactured mask(s) of mask set675for defects and/or contamination to help ensure IC695will function. If a defect or contaminant is identified in a mask, mask inspection tool680for one embodiment may simulate how the mask will print and verify the simulated print against IC layout635to help assess the severity of the defect or contaminant. Mask inspection tool680for one embodiment may use calibrated process model624to better predict how a mask will print.

Lithography equipment690is used to help print the target pattern defined by IC layout635in a corresponding layer of IC695using mask set675. IC695is manufactured by printing the target pattern defined by a corresponding IC layout for one or more layers of IC695.

For one embodiment, process model generator610, process model calibrator620, IC layout generator630, PSM tool641, OPC tool642, layout verification tool650, MDP tool660, and mask inspection tool680may each be implemented in whole or in part by executing suitable instructions by one or more processors of a computer system. Such instructions may be stored on any suitable computer-readable medium from which the instructions may be transmitted to the computer system. The computer system may receive instructions from a suitable computer-readable medium that is a part of the computer system and/or from a suitable computer-readable medium external to the computer system at a local or remote location. The computer system may store any data, such as a process model or layout for example, on a suitable computer-readable medium that is a part of the computer system and/or on a suitable computer-readable medium external to the computer system at a local or remote location.

In the foregoing description, one or more embodiments of the present invention have been described. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit or scope of the present invention as defined in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.