High-voltage metal oxide semiconductor device and fabrication method thereof

A high-voltage metal oxide semiconductor device comprising a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first conductivity type, and a second well of the second conductivity type is provided. The conductive structure has a first portion and a second portion. The first portion is extended from an upper surface of the main body into the main body. The second portion is extended along the upper surface of the main body. The first well is located in the main body and below the second portion. The first well is kept away from the first portion with a predetermined distance. The source region is located in the first well. The second well is located in the main body and extends from a bottom of the first portion to a place close to a drain region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a high-voltage metal oxide semiconductor device and a fabrication method thereof, and more particularly relates to a high-voltage metal oxide semiconductor device with a vertical well and a fabrication method thereof.

2. Description of Related Art

Among various power semiconductor devices, the metal oxide semiconductor field effect transistor, with the advantages of fast switching, low switching loss, and low driving loss, has been widely used for high-frequency power conversion. However, it is hard for the traditional power semiconductor device to withstand high voltage. In order to enhance withstanding voltage, on-resistance of the power semiconductor may increase disproportionately, which results in huge conduction loss and also seriously restricts the application of the power semiconductor device.

Referring toFIGS. 1 and 1A, on-resistance of the traditional high-voltage semiconductor field effect transistor (RDS(on)) is dominated by the resistance of the drift zone, which includes Rch, Ra, and Repias shown. The voltage blocking capability of the high-voltage semiconductor field effect transistor is mainly decided by the distance of the drift zone and the doping. That is, in order to increase withstanding voltage, the epitaxial layer should be thickened and the doping concentration should be lightened. However, the thickened epitaxial layer and the lightened doping concentration results in disproportionate increasing of on-resistance.

The percentage of the epitaxial layer contributed to the overall on-resistance varies with the withstanding voltage. As shown, for the metal oxide semiconductor designed to withstand the voltage (VGD) of 30V, the epitaxial layer contributes only 29% of the total on-resistance, whereas, for the metal oxide semiconductor designed to withstanding the voltage (VGD) of 600V, the epitaxial layer contributes 96.5% of the total on-resistance.

There are two typical methods to reduce the total on-resistance of the high-voltage metal oxide semiconductor device. The first one is to increase the cross-section area of the transistor so as to reduce on-resistance crossing the epitaxial layer. However, the integration density must be reduced and the cost is increased. The other one is to introduce minority carriers. However, this method not only slow down the switching speed but also result in the existence of tail current that increases switching loss.

Since both the above two methods have the unsolvable drawbacks, it is eager to find out a new high-voltage metal oxide semiconductor device with both low on-resistance and high voltage blocking capability.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a high-voltage metal oxide semiconductor device with low on-resistance for reducing power loss and high voltage blocking capability.

A high-voltage metal oxide semiconductor device is provided in the present invention. The high-voltage metal oxide semiconductor device comprises a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first conductivity type, and a second well of the second conductivity type. The conductive structure has a first portion and a second portion. The first portion is extended from an upper surface of the main body into the main body. The second portion is extended along the upper surface of the main body. The first well is located in the main body and below the second portion. The first well is kept away from the first portion with a predetermined distance. The source region is located in the first well. The second well is located in the main body and extends from a bottom of the first portion to a place close to a drain region.

In an embodiment of the present invention, the first portion is connected to the second portion and the second portion is electrically connected to a gate electrode.

In an embodiment of the present invention, the first portion and the second portion are separated by a dielectric layer. The first portion is electrically connected to a gate electrode, whereas the second portion is electrically connected to the source region.

A fabrication method of a high-voltage metal oxide semiconductor device is also provided in the present invention. The fabrication method comprises the steps of: (a) providing a substrate; (b) forming a first epitaxial layer of a first conductivity type on the substrate; (c) defining a doping region in the first epitaxial layer by using a mask and implanting dopants of a second conductivity type in the first epitaxial layer to form a first doped region; (d) repeating steps (b) and (c) more than once; (e) forming a second epitaxial layer of the first conductivity type on the first epitaxial layers; (f) forming a trench exposing the uppermost first doped region; (g) forming a conductive structure with a first portion and a second portion on the second epitaxial layer, the first portion located in the trench, and the second portion extended along an upper surface of the second epitaxial layer; (h) implanting dopants of the second conductivity type in the second epitaxial layer by using the conductive structure as a mask to form a plurality of first wells, which is away from the first portion with a predetermined distance; and (i) forming a plurality of source regions of the first conductivity type in the first wells.

Another high-voltage metal oxide semiconductor device is provided in the present invention. The high-voltage metal oxide semiconductor device comprises a main body of a first conductivity type, a gate conductive layer, two first wells of a second conductivity type, two source regions of the first conductivity type, and a second well of the second conductivity type. The gate conductive layer extends along an upper surface of the main body. The two first wells are located in the main body and corresponding to the two opposite edges of the gate conductive layer respectively. The two source regions are located in the two first wells and beneath the two opposite edges of the gate conductive layer respectively. The second well is located in the main body and extended beneath the gate conductive layer to a place close to a substrate. The second well should be electrically connected to a gate electrode or a source electrode. The second well is away from the two first wells with a predetermined distance. In addition, the distance between the second well and the gate conductive layer is greater than depth of the first well.

Another fabrication method of a high-voltage metal oxide semiconductor device is provided in the present invention. The fabrication method comprises the steps of: (a) providing a substrate; (b) forming a first epitaxial layer of a first conductivity type on the substrate; (c) defining a doping region in the first epitaxial layer by using a mask and implanting dopants of a second conductivity type in the first epitaxial layer to form a first doped region; (d) repeating steps (b) and (c) more than once; (e) forming a second epitaxial layer of the first conductivity type on the first epitaxial layers, wherein the first doped regions are expanded by heat and mutually connected to form a vertical well; (f) forming a guard ring of the second conductivity type in the second epitaxial layer to define an active region, and the guard ring being planarly overlapped with the vertical well; (g) forming a gate conductive layer on an upper surface of the second epitaxial layer and aligned to the vertical well; (h) implanting dopants of the second conductivity type in the second epitaxial layer by using the gate conductive layer as a mask and driving in the dopants to form a plurality of first wells away from the vertical well with a predetermined distance, meanwhile, the guard ring being expanded downward to connect to the vertical well; and (i) forming a plurality of source regions of the first conductivity type in the first wells

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

FIGS. 2A and 2Bare schematic views showing a preferred embodiment of a high-voltage metal oxide semiconductor device in accordance with the present invention. An N-type metal oxide semiconductor device field effect transistor (MOSFET) is described below as an example. As shown, the high-voltage metal oxide semiconductor device has an N-type epitaxial layer120, a conductive structure150, a P-type first well160, an N-type source region170, and a P-type second well130. The N-type epitaxial layer120is located on an N-type substrate110as the main body of the high-voltage metal oxide semiconductor device. The conductive structure150is located on the N-type epitaxial layer120. The conductive structure150showing a T-shaped cross-section has a first portion152and a second portion154. The first portion152is extended from an upper surface of the N-type epitaxial layer120into the N-type epitaxial layer120. The second portion154is extended along the upper surface of the N-type epitaxial layer120. The conductive structure150is electrically connected to a gate electrode G.

The P-type first well160is located in the N-type epitaxial layer120below the second portion154of the conductive structure150. In addition, the first well160is kept away from the first portion152of the conductive structure150with a predetermined distance. That is, there is an N-type area interposed between the P-type first well160and the first portion152of the conductive structure150. The N-type source region170is located in the P-type first well160and is corresponding to the edge of the second portion154of the conductive structure150. The N-type source region170and the N-type epitaxial layer120are separated by the P-type first well160. The source region170is electrically connected to a source electrode S.

The P-type second well130is located in the epitaxial layer120and is extended from a bottom of the first portion152downward to a place close to the N-type substrate110. The bottom of the P-type second well130and the N-type substrate110are separated by N-type area with enough thickness. In addition, the P-type second well130is not in contact with the first portion152of the conductive structure150. The P-type second well130is separated from the first portion152by at least one oxide layer140. However, the P-type second well130can't be far away from the first portion152of the conductive structure150. In order to ensure that the charges in the second well130can be induced by the potential of the first portion152, the P-type second well130should be adjacent to the first portion152. Moreover, there should be an N-type area with enough thickness left between the P-type second well130and the P-type first well160as a conduction path when the metal oxide semiconductor device is conducting.

Referring toFIG. 2A, as the voltage difference (VGS) between the gate electrode G and the source electrode S of the metal oxide semiconductor device is smaller than a threshold voltage (VTH), the channel connecting the source region170and the N-type epitaxial layer120does not exist in the P-type first well160. Meanwhile, when a forward bias is applied between the drain electrode D and the source electrode S, the range of the depletion region on the interface between the P-type first well160, which is electrically connected to the source electrode S, and the N-type epitaxial layer120, which is electrically connected to the drain D, is expanded as the dashed line shows.

It is noted that the voltage levels of the gate electrode G and the source electrode S are substantially the same when the metal oxide semiconductor device is turned off. The forward bias applied between the drain electrode D and the source electrode S also expands the depletion region on the interface between the P-type second well130, which is adjacent to the conductive structure150to access the potential of the gate electrode G, and the N-type epitaxial layer120, which is electrically connected to the drain electrode D, as the dashed line shows. The depletion regions formed on the interfaces between the first well160and the epitaxial layer120and between the second well130and the epitaxial layer120may block the conduction path from the N-type substrate110to the source region170. Because the depletion region shows perfect voltage blocking capability, the withstanding voltage of the metal oxide semiconductor device is thus enhanced dramatically.

Referring toFIG. 2B, when the voltage difference (VGS) between the gate electrode G and the source electrode S is greater than a threshold voltage (VTH), a channel is formed in the P-type first well160under the second portion154to connect the N-type source region170and the N-type epitaxial layer120. At this time, free electrons in the source region170are injected into the depletion region through the channel to recover the conductivity of the N-type epitaxial layer120to form the conduction path extended from the source region170, through the channel under the second portion154, turned downward by the side of the first portion152and the second well130to the N-type substrate110.

As shown, for a preferred embodiment, the width of the second well130is greater than the width of the first portion152to restrict the thickness of N-type area interposed between the first well160and the second well130so as to control the time needed to retrieve the conductivity of the N-type epitaxial layer120when the metal oxide semiconductor device is turned on. In addition, the upper edge of the second well130covers the bottom of the first portion152of the conductive structure150to ensure that the charges in the second well130can quickly respond the potential of the first portion152. Moreover, withstanding voltage of the high-voltage metal oxide semiconductor device in accordance with the present invention is positively dependent to the extending distance of the second well130. The extending distance of the second well130should be much greater than the length of the first portion152in practice.

The above mentioned embodiment describes a high-voltage metal oxide semiconductor field effect transistor. However, the scope of the present invention should not be limited thereto. For example, if the N-type substrate110in the above mentioned embodiment is replaced by a P-type substrate, an insulated gate bipolar transistor (IGBT) in accordance with the present invention is shown.

FIG. 3is a schematic view showing another preferred embodiment of the high-voltage metal oxide semiconductor device in accordance with the present invention. In contrast with the embodiment as shown inFIGS. 2A and 2B, the conductive structure150′ in the present embodiment has an dielectric layer156, such as an oxide layer, interposed between the first portion152′ and the second portion154′ so as to electrically isolate the first portion152′ and the second portion154′. Moreover, in the present embodiment, the second portion154′ of the conductive structure150′ is electrically connected to the gate electrode G, whereas the first portion152′ of the conductive structure150′ is electrically connected to the source electrode S.

Referring toFIGS. 2A and 2B, potential of the second well130of the high-voltage metal oxide semiconductor device is decided by the potential of the gate electrode G. In contrast, potential of the second well130of the present embodiment is decided by the potential of the source electrode S. When the high-voltage metal oxide semiconductor device is turned off and the voltage difference (VGS) between the gate electrode G and the source electrode S is smaller than the threshold voltage (VTH), there are depletion regions formed on the interfaces between the P-type first well160and the N-type epitaxial layer120and between the P-type second well130and the N-type epitaxial layer120to block the conduction path from the N-type substrate110to the source region170and provide perfect voltage blocking capability.

FIGS. 4A to 4Hare schematic views showing a preferred embodiment of the fabrication method of a high-voltage metal oxide semiconductor device in accordance with the present invention. The fabrication method of an N-type metal oxide semiconductor device is shown as an example. Referring toFIG. 4A, firstly, an N-type substrate210is provided. Then, as shown inFIG. 4B, an N-type first epitaxial layer220ais formed on the substrate210. Afterward, a photoresist pattern layer PR is formed on the first epitaxial layer220aby using a mask to define a doping region in the first epitaxial layer220a. P-type dopants are then implanted in the first epitaxial layer220athrough the photoresist pattern layer PR to form a P-type first doped region230a.

Afterward, as shown inFIG. 4C, the fabrication steps ofFIG. 4B, including the steps of forming the N-type first epitaxial layer220aand forming the P-type first doped region230a, are repeated more than once. The number of repeated cycles is positive correlated to the withstanding voltage of the high-voltage metal oxide semiconductor. For example, as the metal oxide semiconductor device is designed to withstand a voltage of 600V, the fabrication steps ofFIG. 4Bare repeated six times to stack six first epitaxial layers200aon the substrate210with six first doped regions230aformed therein.

The fabrication steps ofFIG. 4Bneeds a mask to define the doping region in the first epitaxial layer220a. In the present embodiment, the repeated fabrication steps use the same mask for defining the first doped regions230ain each of the first epitaxial layers220aso that size of the first doped regions230aare substantially the same and the first doped regions are vertically aligned. In addition, because the epitaxial layer is grown at a high temperature, the range of the first doped regions230awould be expanded by heat during the step of growing epitaxial layers. In the present embodiment, as shown inFIG. 4C, by properly controlling the depth and concentration of the implanted dopants as well as the thickness of the respective first epitaxial layer220a, the first doped regions230ain the first epitaxial layers220aare able to connect with each other to form a single P-type vertical well230(corresponding to the second well130inFIGS. 2A and 2B). However, a predetermined distance must be kept between the P-type vertical well230and the N-type substrate210.

Afterward, referring toFIG. 4D, an N-type second epitaxial layer220bis formed on the stacked first epitaxial layers220a. The second epitaxial layer220band the stacked first epitaxial layers220acompose an epitaxial layer220as the main body of the metal oxide semiconductor device. Thereafter, a trench248is formed in the epitaxial layer220to expose the uppermost first doped region230a(or the upper edge of the P-type vertical well230). Afterward, referring toFIG. 4E, an oxide layer240is formed on the exposed surface of the second epitaxial layer220b. Then, a conductive layer, such as a polysilicon layer (not shown), is deposited on the second epitaxial layer220band fills the trench248. After using a mask to define the conductive structure250in the polysilicon layer and removing the unwanted polysilicon material by etching, the conductive structure250has a first portion252and a second portion254is formed on the second epitaxial layer220b. As shown, the first portion252is located in the trench248and the second portion254is extended along the upper surface of the epitaxial layer220b.

Afterward, referring toFIG. 4F, P-type dopants are implanted in the second epitaxial layer200bby using the conductive structure250as a mask so that a plurality of P-type first wells260away from the first portion252with a predetermined distance is formed in the epitaxial layer220. That is, there is an N-type area located between the first well260and the first portion252. In addition, there is also an N-type area with enough width located between the P-type first well260and the P-type vertical well230acting as the conduction path when the metal oxide semiconductor is turned on.

Afterward, referring toFIG. 4G, a photoresist pattern layer PR is formed on the first wells260by using a source mask (not shown) to define a plurality of the source regions270. Then, N-type dopants are implanted through the photoresist pattern layer PR to form the source regions270in the first wells260, respectively. Thereafter, as shown inFIG. 4H, a dielectric layer280is deposited over the exposed surface. Then, a plurality of contact windows282are formed in the dielectric layer280to expose the source regions270and the first wells260under the dielectric layer280. Afterward, P-type dopants are implanted in the first wells260by using the dielectric layer280as a mask to form a plurality of P-type heavily doped regions290in the first wells260respectively.

Referring toFIG. 4H, in the above mentioned embodiment, the first doped regions230ain the epitaxial layer220are connected with each other to form a vertical well230. However, it should not be used to restrict the scope of the present invention. For example, referring toFIG. 5, each of the first doped regions330ain the epitaxial layer220may be separated with each other under the limitation that the spacing between neighboring first doped regions330ashould be small enough to ensure that the charges of each of the first doped regions330acan be induced by the first portion252of the conductive structure250.

FIGS. 6A to 6Eare schematic views showing another preferred embodiment of a high-voltage metal oxide semiconductor device in accordance with the present invention. Following the step ofFIG. 4D, referring toFIG. 6A, a first oxide layer241is then formed on the exposed surface of the second epitaxial layer220b. Afterward, a first polysilicon layer is deposited on the second epitaxial layer220bas a whole and fills the trench248. Part of the first polysilicon layer is then removed by etching back and only the polysilicon material in the trench248is left to construct the first portion352of the conductive structure350.

Afterward, referring toFIG. 6B, a second oxide layer242is formed on the exposed surface of the first portion352. Then, a second polysilicon layer is deposited as a whole to cover the second oxide layer242. Thereafter, the second portion354of the conductive structure350is defined by using a mask (not shown) and the unwanted polysilicon material is removed so as to form the second portion354of the conductive structure350.

Afterward, referring toFIG. 6C, P-type dopants are implanted in the second epitaxial layer220bdirectly by using the second portion354of the conductive structure350as a mask so as to form a plurality of first wells260. Thereafter, referring toFIG. 6D, a photoresist pattern layer PR is formed on the first wells260to define a plurality of source regions270. Then, N-type dopants are implanted in the first wells260to form the source regions in the first wells respectively. Thereafter, as shown inFIG. 6E, a dielectric layer280is deposited over the exposed surface. Then, a plurality of contact windows282are formed in the dielectric layer280to expose the source regions270and the first wells260under the dielectric layer280. Afterward, P-type dopants are implanted in the first wells260by using the dielectric layer280as a mask to form a plurality of P-type heavily doped regions290in the first wells260respectively.

Referring toFIGS. 6A and 6B, the first portion352and the second portion354of the conductive structure350are separated by the second oxide layer242. The second portion354is electrically connected to the gate electrode G to control the switching of the metal oxide semiconductor device, whereas the first portion352may be electrically connected to the source electrode S. Referring toFIG. 7, in order to electrically connect the first portion352and the source electrode S, as a preferred embodiment, there is an opening284formed in the dielectric layer280adjacent to the edge of the high-voltage metal oxide semiconductor device to expose the first portion352and a source metal layer295connecting the source regions270is filled into the opening284to connect the first portion352.

FIG. 8is a schematic view showing another preferred embodiment of the high-voltage metal oxide semiconductor device in accordance with the present invention. An N-type high-voltage metal oxide semiconductor field effect transistor is described below as an example. As shown, the high-voltage metal oxide semiconductor device has an N-type epitaxial layer120, a gate conductive layer450, two P-type first wells160, two N-type source regions170, and a P-type second well130. The N-type epitaxial layer120is located on an N-type substrate110as a main body of the high-voltage metal oxide semiconductor device. The gate conductive layer450is extended along the upper surface of the N-type epitaxial layer120. The two first wells160are located in the N-type epitaxial layer120and corresponding to the two opposite edges of the gate conductive layer450respectively. In addition, the two first wells160are spaced apart from each other.

The two source regions170are located in the two first wells160and beneath the two opposite edges of the gate conductive layer450, respectively. The P-type second well130is located in the N-type epitaxial layer120and extended beneath the gate conductive layer450to a place close to the N-type substrate110, which may be regarded as an N-type drain region. The P-type second well130is away from the two P-type first wells160with a predetermined distance and is electrically connected to the gate electrode G or the source electrode S. As a preferred embodiment, the distance between the second well130and the gate conductive layer450should be greater than the depth of the first well160.

Also referring toFIGS. 9A and 9B, in order to electrically connect the second well to the gate electrode G or the source electrode S of the high-voltage metal oxide semiconductor device, the guard ring460located near the edge of the high-voltage metal oxide semiconductor device may be used as an interconnection structure. As shown, the P-type guard ring460is formed in the N-type epitaxial layer120and surrounding the P-type first well160in the active region A. The depth of the guard ring460is greater than the depth of the P-type first well160. The P-type second well130is extended from the active region A to the edge of the high-voltage metal oxide semiconductor device and connected to the guard ring460.

Referring toFIG. 9A, an opening186is formed in the dielectric layer180to expose the guard ring460and a source metal layer195deposited on the dielectric layer is connected to the source region170and the guard ring460. Thereby, the P-type second well130is electrically connected to the source electrode S through the guard ring460and the source metal layer195. Referring toFIG. 9B, the gate conductive layer450′ near the edge of the active region A is extended toward the upper surface of the guard ring460and connected to the guard ring460. Thereby, the P-type second well130is electrically connected to the gate electrode G through the guard ring460and the gate conductive layer450′.

FIGS. 10A to 10Care schematic views showing a preferred embodiment of the fabrication method of the metal oxide semiconductor device as shown inFIG. 8with the guard ring460. Following the step ofFIG. 4C, referring toFIG. 10A, the second epitaxial layer220bis then formed on the stacked first epitaxial layers220aand a P-type guard ring460is formed in the second epitaxial layer220bto define an active region A. Turns to the top view, the guard ring460would be planarly overlapped with the P-type vertical well230(corresponding to the second well130ofFIG. 8) in the epitaxial layer220. Then, a gate conductive layer450is formed on the upper surface of the second epitaxial layer220band vertically aligned to the vertical well230.

Afterward, referring toFIG. 10B, P-type dopants are implanted in the second epitaxial layer220bby using the gate conductive layer450as a mask. The implanted P-type dopants are then driven into the second epitaxial layer220bby heat to form a plurality of P-type first wells260away from the vertical well230with a predetermined distance. It is noted that the above mentioned step of driving-in the P-type dopants also drives the P-type dopants of the guard ring460into the second epitaxial layer220bso as to expand the range of the guard ring460downward to connect with the P-type vertical well230.

Afterward, referring toFIG. 10C, the location of a plurality of source regions270is defined by using a source mask (not shown), and then N-type dopants are implanted in the first wells260to form the source regions270. Thereafter, a dielectric layer280is deposited over the exposed surface. Then, a plurality of contact windows282are formed in the dielectric layer280to expose the source regions270and the first wells260under the dielectric layer280. Afterward, P-type dopants are implanted in the first wells260through the dielectric layer280to form a plurality of P-type heavily doped regions290in the first wells260.

The high-voltage metal oxide semiconductor device provided in the present invention has the following advantages:

Firstly, referring toFIGS. 2A and 2B, as the voltage difference (VGS) between the gate electrode G and the source electrode S of the metal oxide semiconductor device is smaller than a threshold voltage (VTH), the forward bias applied between the drain electrode D and the source electrode S may result in the expansion of depletion regions to block the N-type area between the first well160and the second well130. The depletion region shows perfect voltage blocking capability. Therefore, the withstanding voltage of the metal oxide semiconductor device can be dramatically increased. On the other hand, as the voltage difference (VGS) between the gate electrode G and the source electrode S of the metal oxide semiconductor device is greater than a threshold voltage (VTH), a channel is formed in the P-type first well160between the N-type source region170and the N-type epitaxial layer120. Free electrons of the source region170are injected to the depletion region through the channel to recover the conductivity of the N-type area to rebuild the conduction path from the source region170to the substrate110. It is noted that the on-resistance of the metal oxide semiconductor device is related to the dope concentration of the N-type epitaxial layer120but the withstanding voltage is not. Therefore, it is possible to achieve the object of low on-resistance by increasing dope concentration but remain high voltage blocking capability at the same time.

Secondly, referring toFIG. 2A, the depletion region for blocking the conduction path is formed between the first well160and the second well130. The distance between the first well160and the second well130is smaller than the distance between two neighboring first wells160. Therefore, in contrast with the traditional high-voltage metal oxide semiconductor devices with lateral PN junctions, such as Coolmos™ and super junction device, which need to recover the conductivity of the depletion region with a width substantially identical to the distance between neighboring first wells160to rebuild the conduction path, the time needed to rebuild the conduction path in accordance with the high-voltage metal oxide semiconductor device in accordance with the present invention is much faster.

In addition, referring toFIG. 2A, there are two intrinsic zener diodes, one is located between the heavily doped region190, the first well160, and the N-type epitaxial layer120, and the other is located between the second well130and the N-type epitaxial layer120. When avalanche breakdown happens, avalanche current would be shared by the two zener diodes rather than concentrated to the zener diode between the heavily doped region190, the first well160, and the N-type epitaxial layer120. Therefore, the current flowing through the resistor traversing the epitaxial layer below the second portion154is reduced so as to prevent the bipolar junction transistor between the N-type epitaxial layer120, P-type first well160, and the source region170from being damaged by large current.