Semiconductor Structure and Method of Making the Same

A semiconductor structure and a method making it are disclosed. The method includes: providing a substrate, and sequentially forming a bitline contact structure and a bitline on the substrate; the bitline includes a connection layer connected to the bitline contact structure. The bitline contact structure and the sidewalls of the connection layer are etched back. A first silicide layer covering the sidewalls of the bitline contact structure, and a second silicide layer covering the sidewalls of the connection layer are formed. This structure can reduce the contact resistance between the bitline contact structure and the bitline, as well as the parasitic capacitance between the bitline contact structure and the adjacent conductive structures, thereby improving the electrical performance and reliability of the semiconductor structure and improving the semiconductor yield.

CROSS REFERENCES TO RELATED APPLICATIONS

This disclosure claims the priority of a Chinese patent with application number 202210560956.1, and entitled “Semiconductor Structure and Method of Making the Same”, filed with the China National Intellectual Property Administration on May 23, 2022, the entire contents of which are incorporated herein by reference Public.

TECHNICAL FIELD

The present disclosure relates to the technical field of semiconductor integrated circuit manufacturing, and in particular, to a semiconductor structure and a preparation method thereof.

BACKGROUND

Dynamic Random Access Memory (DRAM) is a type of semiconductor storage device commonly used in electronic devices such as computers, and includes multiple storage units. One storage unit includes: a storage capacitor and a transistor electrically connected to the storage capacitor. A transistor includes a gate, source and drain regions. The gates of the transistors are used for electrical connection with the word lines. The source region of the transistor is used to form a bitline contact region to be electrically connected to the bitline through the bitline contact structure. The drain region of the transistor is used to form a storage node contact region to be electrically connected to the storage capacitor through the storage node contact structure.

However, with the development of semiconductor technology, the feature sizes of devices in integrated circuits are getting smaller and smaller. After the semiconductor process enters the deep sub-micron stage, the sizes of the DRAMs are getting smaller and smaller, and the sizes of the bitline contact structures and the bitline are also reduced accordingly. A large parasitic capacitance between the line contact structures and the adjacent conductive structures occurs, which adversely affects the electrical performance of the semiconductor device.

SUMMARY

According to various embodiments of the present disclosure, a semiconductor structure and a method of fabricating it are provided.

According to some embodiments, an embodiment of the present disclosure provides a method for fabricating a semiconductor structure, including the following steps:providing a substrate is, and forming a bitline contact structure and a bitline sequentially on the substrate; the bitline includes a connection layer connected with the bitline contact structure;etching back the bitline contact structure and the sidewalls of the connection layer; andforming a first silicide layer covering the sidewalls of the bitline contact structure, and a second silicide layer covering the sidewalls of the connection layer.

According to some embodiments, the bitline further includes a conductive layer on a side of the connection layer facing away from the substrate; wherein the first silicide layer and the second silicide layer are on the substrate. The orthographic projection of is at least within the range of the orthographic projection of the conductive layer on the substrate.

According to some embodiments, the thickness of the first silicide layer is greater than the thickness of the second silicide layer.

According to some embodiments, the etch-back thickness of the bitline contact structure and the sidewalls of the connection layer ranges from 2 nm to 10 nm.

According to some embodiments, the height of the connection layer is 35%˜65% of the height of the bitline.

According to some embodiments, forming a first silicide layer covering the sidewalls of the bitline contact structure and a second silicide layer covering the sidewalls of the connection layer includes the following steps.

A metal material layer is deposited on the sidewalls after the bitline contact structure and the connection layer are etched back.

The resulting structure is annealed to obtain the first silicide layer and the second silicide layer.

In some embodiments, after annealing the obtained structure to obtain the first silicide layer and the second silicide layer, the preparation method further includes: removing the remaining metal material layer.

According to some embodiments, the annealing temperature for annealing the obtained structure is 300° C. to 700° C.

According to some embodiments, the step of depositing a metal material layer on the sidewalls of the bitline contact structure and the connection layer after being etched back includes: on the sidewalls of the bitline contact structure after being etched back depositing a first metal material layer; depositing a second metal material layer on the sidewalls after the connection layer is etched back; wherein, the first metal material layer or the second metal material layer includes a single-layer metal material layer or a stack of layers of metallic materials.

According to some embodiments, after the forming of the first silicide layer covering the sidewalls of the bitline contact structure and the second silicide layer covering the sidewalls of the connection layer, the preparation method further includes: an isolation structure formed on the sidewalls of the first silicide layer; and spacers formed on the sidewalls of the second silicide layer and the sidewalls of the bitline are not covered by the second silicide layer.

According to some embodiments, after forming spacers on the sidewalls of the second silicide layer and the sidewalls of the bitline not covered by the second silicide layer, the preparation method further includes: forming a storage node contact structure; the storage node contact structure is insulated from the first silicide layer by the isolation structure, and the storage node contact structure is insulated from the second silicide layer by the spacer.

According to some embodiments, on the other hand, some embodiments of the present disclosure provide a semiconductor structure, which is obtained by using the manufacturing method described in some of the above embodiments. The semiconductor structure includes: a substrate, a bitline contact structure, a first silicide layer, a bitline and a second silicide layer. The substrate has bitline contact holes. The bitline contact structure is disposed in the bitline contact hole. The first silicide layer is disposed on the sidewalls of the bitline contact structure. The bitline includes a connection layer connected to the bitline contact structure. The second silicide layer is disposed on the sidewalls of the connection layer.

According to some embodiments, the bitline further includes a conductive layer on a side of the connection layer facing away from the substrate; wherein the first silicide layer and the second silicide layer are on the substrate The orthographic projection of is at least within the range of the orthographic projection of the conductive layer on the substrate.

According to some embodiments, the orthographic projection of the second silicide layer on the substrate is within the orthographic projection of the conductive layer on the substrate, and the second silicide layer is on the substrate. There is a separation between the orthographic boundary on the conductive layer and the orthographic boundary of the conductive layer on the substrate.

According to some embodiments, the thickness of the first silicide layer is greater than the thickness of the second silicide layer.

According to some embodiments, the height of the connection layer is 35%˜65% of the height of the bitline.

According to some embodiments, the semiconductor structure further includes an isolation structure and a spacer. The isolation structure is disposed on the sidewalls of the first silicide layer. The sidewalls spacers are disposed on the sidewalls of the second silicide layer and the sidewalls of the bitline not covered by the second silicide layer.

According to some embodiments, the semiconductor structure further includes: a storage node contact structure; the storage node contact structure is insulated from the first silicide layer by the isolation structure, and the storage node contact structure is passed through the spacer is insulated from the second silicide layer.

The embodiments of the present disclosure at least have the following advantages:

In the embodiment of the present disclosure, by etching back the sidewalls of the bitline contact structure and the sidewalls of the connection layer in the bitline, a first silicide layer can be formed on the sidewalls of the bitline contact structure after the thickness reduction, a second silicide layer is formed on the sidewalls of the bitline connection layer after the thickness. In this way, the first silicide layer and the second silicide layer can be used to effectively reduce the contact resistance between the bitline contact structure and the bitline under the condition that the design dimensions of the bitline and the bitline contact hole are kept unchanged. Thereby, the electrical properties of the semiconductor structure are improved, so as to improve the reliability and yield of the semiconductor structure.

In addition, in the embodiment of the present disclosure, by setting the thicknesses of the first silicide layer and the second silicide layer, for example, setting the orthographic projection of the first silicide layer and the second silicide layer on the substrate at least in the bitline is conductive. The orthographic projection of the layer on the substrate, in particular, the orthographic projection of the second silicide layer on the substrate is located within the orthographic projection of the conductive layer on the substrate, and the orthographic projection of the second silicide layer on the substrate The boundary is spaced from the orthographic boundary of the conductive layer on the substrate. This can not only reduce the contact resistance between the bitline contact structure and the bitline, but also increase the bitline contact structure and the bitline and adjacent conductive structures under the condition that the design size of the bitline and the bitline contact hole is kept unchanged. The distance between them can effectively reduce the parasitic capacitance. Therefore, the electrical properties of the semiconductor structure can be further improved, so as to further improve the reliability and yield of the semiconductor structure.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

To facilitate understanding of the present disclosure, the present disclosure will be described more fully hereinafter with reference to the related drawings. Embodiments of the present disclosure are presented in the accompanying drawings. However, the present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein in the specification of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure.

It will be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” other elements or layers, it can be directly on the other elements or layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” other elements or layers, there are no intervening elements or layers present.

Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms “a,” “an,” and “the/the” can include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms “comprising/comprising” or “having” etc. designate the presence of stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more Possibilities of other features, integers, steps, operations, components, parts or combinations thereof. Also, in this specification, the term “and/or” includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown may be contemplated due, for example, to manufacturing techniques and/or tolerances. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes do not represent the actual shape of a region of a device and do not limit the scope of the present disclosure.

Referring toFIG.1, some embodiments of the present disclosure provide a method for fabricating a semiconductor structure, including the following steps.S100, providing a substrate, and forming a bitline contact structure and a bitline are sequentially on the substrate, and the bitline includes a connection layer connected to the bitline contact structure;S200, etching back the sidewalls of the bitline contact structure and the connection layer; andS300, forming a first silicide layer covering the sidewalls of the bitline contact structure and a second silicide layer covering the sidewalls of the connection layer.

In the embodiment of the present disclosure, by etching back the sidewalls of the bitline contact structure and the sidewalls of the connection layer in the bitline, a first silicide layer can be formed on the sidewalls of the bitline contact structure after the thickness reduction, a second silicide layer is formed on the sidewalls of the bitline connection layer after the thickness. In this way, the first silicide layer and the second silicide layer can be used to effectively reduce the contact resistance between the bitline contact structure and the bitline while ensuring that the designed dimensions of the bitline and the bitline contact structure remain unchanged. Thereby, the electrical properties of the semiconductor structure are improved, so as to improve the reliability and yield of the semiconductor structure.

In step S100, referring to S100inFIG.1andFIG.2, a substrate1is provided, and a bitline contact structure2and a bitline3are sequentially formed on the substrate1. The bitline3includes a connection layer31connected to the bitline contact structure2.

In some embodiments, the substrate1may include semiconductor materials, insulating materials, conductor materials, or any combination thereof. The substrate1may have a single-layer structure or a multi-layer structure. For example, the substrate1may be, for example, a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an arsenic Indium phosphide (InAs) substrates, indium phosphide (InP) substrates or other III/V semiconductor substrates or II/VI semiconductor substrates. Alternatively, also for example, the substrate1may be a layered substrate comprising eg Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on insulator.

In one example, the substrate1includes, but is not limited to, a silicon substrate or a silicon-based substrate. The substrate1has a shallow trench isolation structure10, and the shallow trench isolation structure10isolates an active region within the substrate1. Optionally, the shallow trench isolation structure10is a silicon oxide (SiO2) isolation structure. The shallow trench isolation structure10can isolate a plurality of active regions arranged in an array in the substrate1.

Continue to refer toFIG.2for some embodiments, a bitline contact hole (BLC for short)11is provided in the active area on the substrate1, and the bitline contact structure2is filled in the corresponding bitline inside the line contact hole11. The bitline contact hole11may be a round hole, a square hole or a special-shaped hole. The shape and size of the bitline contact hole11are not limited in the embodiment of the present disclosure.

In some embodiments, the connection layer31of the bitline3may be formed by using doped polysilicon, silicon germanium and other materials with conductive functions. The material of the bitline contact structure2may be the same as or different from the material of the connection layer31in the bitline3. Alternatively, the material of the bitline contact structure2can be the same as the material of the connection layer31in the bitline3, but the doping concentration of the two can be different, the etching rates of the two can be different when they are formed, and the sidewalls of the two can be etched back. The etching rate can also be different at different times, and the specific setting can be selected according to actual needs. This embodiment of the present disclosure does not limit this, and also does not limit the shapes of the bitline contact structure2and the connection layer31after being etched.

In an example, please continue to refer toFIG.2, the part of the bitline3other than the connection layer31connecting with the bitline contact structure2is insulated from the substrate1by the dielectric layer12. Optionally, the dielectric layer12may be an insulating layer such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. The thickness of the dielectric layer12can be selected and set according to actual requirements.

In one example, the connection layer31in the bitline3and the bitline contact structure2are both doped polysilicon layers, and the doping concentration of the two can be the same.

It can be understood that, in some embodiments, please continue to refer toFIG.2, the bitline3further includes a first barrier layer32, a conductive layer33and a top isolation layer34which are sequentially arranged on one side of the connection layer31along the direction away from the substrate1.

Optionally, the first barrier layer32includes, but is not limited to, a titanium nitride layer. For example, the first barrier layer32may also be a titanium layer.

Optionally, the conductive layer33includes, but is not limited to, a tungsten metal layer. For example, the conductive layer33can also be a copper metal layer or a gold metal layer.

Optionally, the top isolation layer34includes, but is not limited to, a silicon nitride layer. For example, the top isolation layer34may also be a silicon oxynitride layer.

The above-mentioned first barrier layer32, conductive layer33and top isolation layer34can be obtained by patterning each material layer through a patterning process after depositing the corresponding material layer. Optionally, the top isolation layer34can be formed by using a hard mask material to be used as a hard mask during the formation of the conductive layer33, the first barrier layer32and the connection layer31.

Here, the deposition process includes but is not limited to low pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer chemical vapor deposition (ALCVD) and other processes. The patterning process includes but is not limited to wet etching or dry etching, wherein the dry etching at least includes reactive ion etching (RIE), inductively coupled plasma etching (ICP) or high concentration plasma etching (HDP)) any of them.

In some embodiments, the height of the connection layer31is 35% 65% of the height of the bitline3. For example, the height of the connection layer31is 35%, 40%, 45%, 50%, 55%, 60% or 65% of the height of the bitline3.

Here, please refer toFIG.2, in the example in which the bitline3adopts the aforementioned structure, the height H of the bitline3refers to the sum of the heights of the connection layer31, the first barrier layer32, the conductive layer33and the top isolation layer34That is, H=H1+H2+H3+H4, wherein H1is the height of the connecting layer31, H2is the height of the first barrier layer32, H3is the height of the conductive layer33, and H4is the height of the top isolation layer34.

In step S200, referring to S200inFIG.1andFIG.3, the sidewalls of the bitline contact structure2and the connection layer31are etched back.

Here, according to the formation materials of the bitline contact structure2and the connection layer31, an etching process can be reasonably selected for etching back. The etching process includes but is not limited to wet etching or dry etching, wherein the dry etching may at least include reactive ion etching (RIE), inductively coupled plasma etching (ICP) or high concentration plasma etching (HDP) either.

In addition, the etch-back thicknesses of the sidewalls of the bitline contact structure2and the connection layer31can be selected according to actual requirements. In addition, the etched back thicknesses of the sidewalls of the bitline contact structure2and the connection layer31may be the same or different.

In addition, please understand with reference toFIG.3, the bitline contact structure2is formed in the bitline contact hole11, and the etching of the sidewalls of the bitline contact structure2can be performed by the trench G formed on the side thereof, for example, the trench G is used to fill the isolation material to form the isolation structure corresponding to the bitline contact structure2.

In step S300, referring toFIG.1andFIG.4, a first silicide layer4covering the sidewalls of the bitline contact structure2and a second silicide layer5covering the sidewalls of the connection layer31are formed.

The first silicide layer4and the second silicide layer5may be the same silicide layer, or may be different silicide layers. Correspondingly, the first silicide layer4and the second silicide layer5may be formed simultaneously or in steps. This embodiment of the present disclosure does not limit this.

In some embodiments, referring toFIG.4andFIG.5, the bitline3further includes a conductive layer33located on the top side of the connection layer31away from the substrate1. The first silicide layer4is formed on the sidewalls after the bitline contact structure2is etched back, and the second silicide layer5is formed on the sidewalls after the connection layer31is etched back. The first silicide layer4and the orthographic projection of the second silicide layer5on the substrate1is at least within the range of the orthographic projection of the conductive layer33on the substrate1.

Here, the orthographic projections of the first silicide layer4and the second silicide layer5on the substrate1are at least within the range of the orthographic projection of the conductive layer33on the substrate1, including: the first silicide layer4and the first silicide layer5, each of the silicide layers5includes a portion located directly below the bottom of the conductive layer33(i.e., under), or the first silicide layer4and/or the second silicide layer5includes a portion located directly under the conductive layer33(i.e., vertically). In addition to the part directly under), it also includes the part whose orthographic projection is located outside the orthographic projection of the conductive layer33on the substrate1.

In one example, as shown inFIG.5, the orthographic projection of the second silicide layer5on the substrate1is located within the orthographic projection of the conductive layer33on the substrate1. There is a separation gap W between the orthographic projection of the second silicide layer5on the substrate1and the orthographic projection of the conductive layer33on the substrate1.

From the above, in conjunction withFIG.4andFIG.5, the thickness D1of the first silicide layer4and the thickness D2of the second silicide layer5may be the same or different.

In one example, referring toFIG.4, the thickness D1of the first silicide layer4is equal to the thickness D2of the second silicide layer5.

In one example, referring toFIG.5, the thickness D1of the first silicide layer4is greater than the thickness D2of the second silicide layer5.

In the embodiment of the present disclosure, by setting the thicknesses of the first silicide layer4and the second silicide layer5, it is possible to not only reduce the size of the bitline3while ensuring the design dimensions of the bitline3and the bitline contact hole11remain unchanged. The contact resistance with the bitline contact structure2can also increase the distance between the bitline contact structure2and the bitline3and adjacent conductive structures, so as to effectively reduce the parasitic capacitance. Therefore, the electrical properties of the semiconductor structure can be further improved, so as to further improve the reliability and yield of the semiconductor structure.

It is worth mentioning that the first silicide layer4and the second silicide layer5can be formed simultaneously or in steps. Also, the first silicide layer4and the second silicide layer5may be deposited directly or obtained by performing a metallization process on polysilicon. In addition, the first silicide layer4and the second silicide layer5may be a single-layer structure or a multi-layer structure, which may be selected and set according to actual requirements.

For examples for illustration, the following embodiments have the bitline contact structure2and the connection layer31as doped polysilicon layers and describe the preparation process of the first silicide layer4and the second silicide layer5in detail.

Referring toFIG.6, in some embodiments, forming a first silicide layer covering the sidewalls of the bitline contact structure and a second silicide layer covering the sidewalls of the connection layer in step S300includes the following steps.S310, depositing a metal material layer on the sidewalls after the bitline contact structure and the connection layer are etched back.S320, annealing the obtained structure to obtain a first silicide layer and a second silicide layer.

Please continue to refer toFIG.6, in some embodiments, after annealing the obtained structure in step S320to obtain the first silicide layer and the second silicide layer, the method further includes: S330, removing residual metal material layer.

In step S310, referring to S310inFIG.6andFIG.7, a metal material layer41is deposited on the sidewalls of the bitline contact structure2and the connection layer31after being etched back.

Here, the metal material layer41is, for example, a metal element layer or a metal compound layer. Alternatively, the metal material layer41may also be a single material layer or multiple material layers. Optionally, the metal material layer41is a tantalum (Ta) metal layer, a stack of tantalum (Ta) and tantalum titanium (TaTi), a tungsten nitride (WN) material layer, a cobalt (Co) metal layer, or the like.

In step S320, referring to S320inFIG.6andFIG.8, the obtained structure shown inFIG.7is annealed to obtain the first silicide layer4and the second silicide layer5.

Here, it can be understood that after the structure shown inFIG.7is annealed, the portions of the metal material layer41located on the sidewalls of the bitline contact structure2and the sidewalls of the connection layer31can be correspondingly converted into silicide layers.

Optionally, the annealing temperature for annealing the obtained structure is 300° C. to 700° C. For example, the annealing temperature may be 300° C., 400° C., 500° C., 600° C. or 700° C.

In step S330, referring to S330inFIG.6andFIG.8, the remaining metal material layer42is removed.

Here, the residual metal material layer42means that the metal material layer41is transformed to form other parts than the first silicide layer4and the second silicide layer5.

It is worth mentioning that, in some embodiments, the first silicide layer4and the second silicide layer5may be formed of different materials and formed in steps. Based on this, in step S310, depositing the metal material layer41on the sidewalls of the bitline contact structure2and the connection layer31after being etched back may include: depositing the first metal material layer41on the sidewalls of the bitline contact structure2after being etched back. A metal material layer; a second metal material layer is deposited on the sidewalls after the connection layer31is etched back; wherein, the first metal material layer or the second metal material layer includes: a single-layer metal material layer or a multi-layer metal material layer of the stack. Correspondingly, after the first metal material layer and the second metal material layer are formed, steps S320and S330in the foregoing embodiments may be referred to prepare the first silicide layer4and the second silicide layer5. This embodiment of the present disclosure will not describe this in detail.

Referring toFIG.9, in some embodiments, after forming the first silicide layer4covering the sidewalls of the bitline contact structure2and the second silicide layer5covering the sidewalls of the connection layer31in step S300, the method also includes the following steps.S400, forming an isolation structure on the sidewalls of the first silicide layer.S500, forming spacers on the sidewalls of the second silicide layer and the sidewalls of the bitline not covered by the second silicide layer.

Here, it should be understood that the execution of steps S400and S500is not strictly limited in sequence, and these steps may be executed simultaneously or in other sequences. Moreover, in the embodiment of the present disclosure, at least a part of the steps of the preparation method may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed and completed at the same moment, but may be performed at different moments. The execution order of these sub-steps or phases is not necessarily performed sequentially, but may be performed alternately or alternately with other steps or at least a part of the sub-steps or phases of other steps.

In step S400, referring toFIG.9, isolation structures6are formed on the sidewalls of the first silicide layer4.

The above-mentioned isolation structure6can be formed by using a dielectric material with a relatively high dielectric constant, and the isolation structure6is, for example, a single-layer dielectric layer, or a stack of multiple dielectric layers. The isolation structure6may be formed by filling the trench G in the foregoing example. The isolation structure6is used to insulate the corresponding bitline contact structure2, and the isolation structure6covers the sidewalls of the first silicide layer4; that is to say, the first silicide layer4can be an equivalent bitline contact structure. A component to ensure that the size of the equivalent bitline contact structure can meet the design requirements. (The equivalent bitline contact structure may be composed of the bitline contact structure2and the first silicide layer4together).

In step S500, referring toFIG.9, spacers7are formed on the sidewalls of the second silicide layer5and the sidewalls of the bitline3not covered by the second silicide layer5.

The spacer7may be formed of a dielectric material with a lower dielectric constant, for example, the spacer7is a single-layer dielectric layer, or a stack of multiple dielectric layers. The spacers7are used to insulate the corresponding bitline3, and the spacers7cover the second silicide layer5and the side walls of the bitline3; that is to say, the second silicide layers5can be equivalent to the bitline. A component to ensure that the size of the equivalent bitline can meet the design requirements. In addition, the thickness of the side wall7can be selected and set according to actual needs.

Optionally, the isolation structure6and the sidewalls spacers7respectively adopt a structure formed by stacking a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer. The isolation structure6and the sidewalls7can be formed simultaneously.

In the embodiment of the present disclosure, the formation of the first silicide layer4and the second silicide layer5is arranged before the formation of the isolation structure6corresponding to the bitline contact structure2and the sidewalls spacer7corresponding to the bitline3, which is beneficial to simplify The preparation process of the semiconductor structure reduces the difficulty of preparing the semiconductor structure, thereby improving the production efficiency and yield of the semiconductor structure.

Please continue to refer toFIG.9andFIG.10, in some embodiments, the method further includes: S600, forming the storage node contact structure8. The storage node contact structure8is insulated from the first silicide layer4by the isolation structure6, and the storage node contact structure8is insulated from the second silicide layer5by the spacer7.

It can be understood that the storage node contact structure8is usually formed in the corresponding storage node contact hole. Illustratively, storage node contact holes may be formed on the resulting structure after forming the isolation structures6and the spacers7to form the storage node contact structures8within the storage node contact holes and between adjacent storage node contact structures8. The insulating layer9is used to effectively insulate the adjacent storage node contact structures8by the insulating layer9.

Optionally, the storage node contact structure8includes a first conductive layer81, a conductive transition layer82, a second barrier layer83and a second conductive layer84that are stacked in sequence along a direction away from the substrate1. But it doesn't stop there. The first conductive layer81is, for example, a doped polysilicon layer. The conductive transition layer82is, for example, a cobalt silicide layer. The second barrier layer83is, for example, a titanium nitride layer. The second conductive layer84is, for example, a tungsten metal layer.

Optionally, the insulating layer9may be a silicon nitride layer, such as one or more silicon nitride layers. In addition, the insulating layer9may be formed at one time, or may be formed gradually in layers during the preparation of other layer structures. That is, the insulating layer9here refers to the entire insulating portion between adjacent storage node contact structures8.

Some embodiments of the present disclosure provide a semiconductor structure, which is prepared by using the preparation methods described in some of the above embodiments. The technical advantages that can be achieved by the above preparation method are also possessed by the semiconductor structure, which will not be described in detail here.

Referring toFIG.10, the semiconductor structure includes: a substrate1, a bitline contact structure2, a bitline3, a first silicide layer4and a second silicide layer5. The substrate1has bitline contact holes11. The bitline contact structure2is disposed in the bitline contact hole11. The first silicide layer4is disposed on the sidewalls of the bitline contact structure2. The bitline3includes a connection layer31connected to the bitline contact structure2. The second silicide layer5is disposed on the sidewalls of the connection layer31.

Optionally, the substrate1is a silicon substrate or a silicon-based substrate, the substrate1has a shallow trench isolation structure10, and the shallow trench isolation structure10isolates an active region in the substrate1. The shallow trench isolation structure10is, for example, a silicon oxide (SiO2) isolation structure. The shallow trench isolation structure10can isolate a plurality of active regions arranged in an array in the substrate1. The bitline contact hole11is provided in the active region of the substrate1.

Optionally, the bitline3includes a connection layer31, a first barrier layer32, a conductive layer33and a top isolation layer34which are arranged in sequence along a direction away from the substrate1.

In some embodiments, the connection layer31of the bitline3may be a doped polysilicon layer or a silicon germanium layer with a conductive function. The bitline contact structure2may be the same as or different from the connection layer31in the bitline3.

In one example, the connection layer31in the bitline3and the bitline contact structure2are both doped polysilicon layers, and the doping concentration of the two can be the same.

In one example, the first barrier layer32is a titanium nitride layer or a titanium layer.

In one example, the conductive layer33is a tungsten metal layer, a copper metal layer, or a gold metal layer.

In one example, the top isolation layer34is a silicon nitride layer or a silicon oxynitride layer.

In one example, the part of the bitline3other than the connection layer31connecting with the bitline contact structure2is insulated from the substrate1by the dielectric layer12. Optionally, the dielectric layer12may be an insulating layer such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. The thickness of the dielectric layer12can be selected and set according to actual requirements.

In some embodiments, the height of the connection layer31is 35%˜65% of the height of the bitline3. For example, the height of the connection layer31is 35%, 40%, 45%, 50%, 55%, 60% or 65% of the height of the bitline3.

In some embodiments, the first silicide layer4and the second silicide layer5may be the same silicide layer, or may be different silicide layers.

Optionally, the orthographic projections of the first silicide layer4and the second silicide layer5on the substrate1are at least within the range of the orthographic projection of the conductive layer33on the substrate1.

Here, the orthographic projections of the first silicide layer4and the second silicide layer5on the substrate1are at least within the range of the orthographic projection of the conductive layer33on the substrate1, including: the first silicide layer4and the first silicide layer5, each of the silicide layers5includes a portion located directly under the conductive layer33(i.e., vertically under), or the first silicide layer4and/or the second silicide layer5includes a portion located directly under the conductive layer33(i.e., vertically below). In addition to the part directly under, it also includes the part whose orthographic projection is located outside the orthographic projection of the conductive layer33on the substrate1.

In one example, the orthographic projection of the second silicide layer5on the substrate1is located within the orthographic projection of the conductive layer33on the substrate1, and the orthographic projection boundary of the second silicide layer5on the substrate1is the same as the conductive layer33has a space between the orthographic boundaries on the substrate1.

From the above, the thickness of the first silicide layer4and the thickness of the second silicide layer5can be the same or different.

In one example, the thickness of the first silicide layer4is equal to the thickness of the second silicide layer5.

In one example, the thickness of the first silicide layer4is greater than the thickness of the second silicide layer5.

In the embodiment of the present disclosure, by setting the thicknesses of the first silicide layer4and the second silicide layer5, it is possible to not only reduce the size of the bitline3while ensuring the design dimensions of the bitline3and the bitline contact hole11remain unchanged. The contact resistance with the bitline contact structure2can also increase the distance between the bitline contact structure2and the bitline3and adjacent conductive structures, so as to effectively reduce the parasitic capacitance. Therefore, the electrical properties of the semiconductor structure can be further improved, so as to further improve the reliability and yield of the semiconductor structure.

Please continue to refer toFIG.10, in some embodiments, the semiconductor structure further includes: an isolation structure6and a spacer7. The isolation structure6is disposed on the sidewalls of the first silicide layer4. The sidewalls spacers7are disposed on the sidewalls of the second silicide layer5and the sidewalls of the bitline3not covered by the second silicide layer5.

Optionally, the isolation structure6is formed of a dielectric material with a higher dielectric constant, such as a single-layer dielectric layer, or a stack of multiple dielectric layers. The isolation structure6is used to insulate the corresponding bitline contact structure2, and the isolation structure6is arranged on the sidewalls of the first silicide layer4; that is to say, the first silicide layer4can be an equivalent bitline contact structure. A component to ensure that the size of the equivalent bitline contact structure can meet the design requirements. (The equivalent bitline contact structure may be composed of the bitline contact structure2and the first silicide layer4together).

Optionally, the sidewalls7may be formed of a dielectric material with a lower dielectric constant, such as a single-layer dielectric layer, or a stack of multiple dielectric layers. The spacers7are used to insulate the corresponding bitline3, and the spacers7cover the second silicide layer5and the side walls of the bitline3; that is to say, the second silicide layers5can be equivalent to the bitline s. A component to ensure that the size of the equivalent bitline can meet the design requirements. (The equivalent bitline may include the bitline3and the second silicide layer5together). In addition, the thickness of the side wall7can be selected and set according to actual needs.

In one example, the isolation structure6and the spacer7are respectively formed by stacking a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer.

Please continue to refer toFIG.10, in some embodiments, the semiconductor structure further includes: a storage node contact structure8. The storage node contact structure8is insulated from the first silicide layer4by the isolation structure6, and the storage node contact structure8is insulated from the second silicide layer5by the spacer7.

Optionally, the storage node contact structure8includes a first conductive layer81, a conductive transition layer82, a second barrier layer83and a second conductive layer84that are stacked in sequence along a direction away from the substrate1. But it doesn't stop there. The first conductive layer81is, for example, a doped polysilicon layer. The conductive transition layer82is, for example, a cobalt silicide layer. The second barrier layer83is, for example, a titanium nitride layer. The second conductive layer84is, for example, a tungsten metal layer.

Optionally, an insulating layer9is further provided between adjacent storage node contact structures8. The insulating layer9may be a silicon nitride layer, for example, one or more layers of silicon nitride layers. Here, the insulating layer9refers to the entire insulating portion between adjacent storage node contact structures8.

In conclusion, the semiconductor structure and the manufacturing method thereof provided by the embodiments of the present disclosure can not only reduce the distance between the bitline contact structure2and the bitline3under the condition that the design dimensions of the bitline3and the bitline contact hole11are kept unchanged. The contact resistance can also increase the distance between the bitline contact structure2and the bitline3and the adjacent conductive structures, so as to effectively reduce the parasitic capacitance. Therefore, the electrical properties of the semiconductor structure can be effectively improved, so as to further improve the reliability and yield of the semiconductor structure.

The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above-described embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be regarded as the scope described in this specification.

The above-mentioned embodiments only represent several embodiments of the present disclosure, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the scope of the patent application. It should be noted that, for those skilled in the art, without departing from the concept of the present disclosure, several modifications and improvements can be made, which all belong to the protection scope of the present disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the appended claims.