High definition multimedia interface (HDMI) apparatus including termination circuit

A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal. The termination circuit conditionally provides a termination resistance without a leakage current. The termination resistance may be varied by using an n-bit control code.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2011-0033694, filed on Apr. 12, 2011 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

TECHNICAL FIELD

Exemplary embodiments relate to a termination circuit, and more particularly to a termination circuit for a HDMI (High Definition Multimedia Interface) transmitter, a HDMI transmitter including the termination circuit, and a multimedia source apparatus including the HDMI transmitter.

DISCUSSION OF THE RELATED ART

HDMI (High-Definition Multimedia Interface) is a compact audio/video interface for transmitting uncompressed digital data. It is a digital alternative to consumer analog standards, such as radio frequency (RF) coaxial cable, composite video, S-Video, SCART, component video, D-Terminal, or VGA (also called D-sub or DE-15F). HDMI connects digital audio/video sources (such as set-top boxes, DVD players, Blu-ray Disc players, personal computers (PCs), video game consoles, AV receivers, tablet computers, and mobile phones) to compatible digital audio devices, computer monitors, video projectors, and digital televisions. HDMI, is a digital audio, video and control signal format defined by 7 of the largest consumer electronics manufacturers. HDMI 1.0 was released Dec. 9, 2002 and is a single-cable digital audio/video connector interface with a maximum TMDS bandwidth of 4.9 Gbit/s and the Dual-Link could handle about 10 Gbps. HDMI 1.0 supports up to 3.96 Gbit/s of video bandwidth (1080 p/60 Hz or UXGA) and 8 channel LPCM/192 kHz/24-bit audio. HDMI 1.3 was released Jun. 22, 2006 and increased the single-link bandwidth to 340 MHz (10.2 Gbit/s). Thus, HDMI 1.3 doubles the maximum data rate from 5 to 10 Gbps, and the color depth is increased from 24 bit to 30, 36 or 48 bit.

Data rate refers to total number of digital bits in a second for a given signal. The higher resolution, refresh rate, color depth, the higher the data rate. For cables, data rate is critical because a cable is a passive device that does not know the signal content. When the cable length increases, the image quality is perceived to be perfect by human eyes until a length corresponding to too much noise. After that length, the image is either not viewable or disappears all together. According to the HDMI standard, a HDMI transmitter transmits data using a driver having the open drain form. Thus, the HDMI transmitter operates using a voltage of about 3.3V provided by a HDMI receiver. In general, a driver having the open drain form has a very large output resistance on the order of kilo ohms or mega ohms. Therefore, as the data transmission speed increases, a signal reflection on the output resistance of an open drain driver of the HDMI transmitter increases such that signal integrity is degraded.

The longer cables and un-known devices introduce the potential for communication error. The error rate overwhelms the built-in error correction technology used in digital transmission. The symptoms of communication error can range from no picture, jumping picture, snowy picture, wrong resolution and no audio. The display can tolerate a certain amount of error bits per second; the picture would still be perfect as long as the error rate is below that threshold. Once the error rate through the cable exceeds the capability of the display, signal recovery may fail altogether. Better termination of signal reflection allows for the use of less expensive and/or longer HDMI cables.

SUMMARY

Some aspects of the invention provide a termination circuit capable of conditionally providing a termination resistance.

Some aspects of the invention provide a HDMI transmitter including the termination circuit.

Some aspects of the invention provide a multimedia source apparatus including the HDMI transmitter.

In various to exemplary embodiments, a termination circuit includes a bias unit and a termination resistor unit connected between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistor (e.g., a fixed or variable predetermined termination resistance) between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal.

The bias unit and the termination resistor unit may be connected in parallel between the positive transmission pin and the negative transmission pin.

The bias unit may include two PMOS transistors, where gates and drains of the two PMOS transistors are cross-coupled.

In some exemplary embodiments, the bias unit comprises a first PMOS transistor formed on an n-type well region, and a second PMOS transistor formed on an n-type well region. The first PMOS transistor includes a gate, a drain connected to the positive transmission pin, and a source connected to a first node. The second PMOS transistor includes a gate connected to the drain of the first PMOS transistor, a source connected to the first node, and a drain connected to the negative transmission pin and the gate of the first PMOS transistor. The n-type well region may be connected to the first node, and the bias unit may provide the bias voltage at the first node.

The bias unit may further comprise a first protection resistor connected between the positive transmission pin and the drain of the first PMOS transistor and a second protection resistor connected between the negative transmission pin and the drain of the second PMOS transistor.

The termination resistor unit may comprise a PMOS transistor formed on the well region and having its gate configured to receive the termination resistor control signal, a first termination resistor connected between the positive transmission pin and the source of the PMOS transistor, and a second termination resistor connected between the negative transmission pin and the drain of the PMOS transistor.

The termination resistor unit may comprise a plurality of termination resistor blocks connected in parallel between the positive transmission pin and the negative transmission pin. Each of the plurality of the termination resistor blocks may comprise a PMOS transistor formed on the well region and having its gate configured to receive the termination resistor control signal, a first termination resistor connected between the positive transmission pin and the source of the PMOS transistor, and a second termination resistor connected between the negative transmission pin and the drain of the PMOS transistor.

The termination resistor unit may comprise a first PMOS transistor formed on the well region and including a drain, a source, and having its gate configured to receive the termination resistor control signal, a second PMOS transistor formed on the well region and including a drain, a source connected to the drain of the first PMOS transistor, and having its gate configured to receive the termination resistor control signal, a first termination resistor connected between the positive transmission pin and the source of the first PMOS transistor, and a second termination resistor connected between the negative transmission pin and the drain of the second PMOS transistor.

The termination resistor unit may comprise a plurality of termination resistor blocks connected in parallel between the positive transmission pin and the negative transmission pin. Each of the plurality of the termination resistor blocks may comprise a first PMOS transistor formed on the well region and including a drain, a source, and having its gate receiving the termination resistor control signal, a second PMOS transistor formed on the well region and including a drain, having its source connected to the drain of the first PMOS transistor, and having its gate receiving the termination resistor control signal, a first termination resistor connected between the positive transmission pin and the source of the first PMOS transistor, and a second termination resistor connected between the negative transmission pin and the drain of the second PMOS transistor.

The termination circuit may further comprise a control unit configured to convert a voltage level of an ON/OFF control signal to generate the termination resistor control signal.

The bias unit, the termination resistor unit, and the control unit may operate using only the first voltage and the second voltage.

Each of the bias unit, the termination resistor unit, and the control unit may include a MOS transistor having a voltage tolerance of about 1.8V or less.

The termination resistor control signal generated by the control unit may have a voltage equal to or higher than 1.5V when the termination resistor control signal is at a logic low level.

The control unit may convert the voltage level of the ON/OFF control signal using the first voltage and the second voltage.

The control unit may comprise a common voltage generation unit configured to generate a common voltage using the first voltage and the second voltage, where the common voltage has a voltage between the first voltage and the second voltage, a voltage drop unit configured to generate an inner control voltage by dropping a voltage of the common voltage, and a voltage conversion unit configured to generate the termination resistor control signal in response to the ON/OFF control signal using the common voltage and the inner control voltage, where the termination resistor control signal has a voltage substantially equal to the common voltage when the ON/OFF control signal is at a logic low level and has a voltage lower than the common voltage when the ON/OFF control signal is at a logic high level.

The common voltage generation unit may comprise a first resistor connected between the positive transmission pin and a second node, and a second resistor connected between the negative transmission pin and the second node, where the common voltage generation unit provides the common voltage at the second node.

The voltage drop unit may comprise a third resistor connected between the second node and a third node, and a fourth resistor connected between the third node and a ground voltage, where the voltage drop unit provides the inner control voltage at the third node.

The voltage conversion unit may comprise a fifth resistor connected between the second node and a fourth node, a sixth resistor, where a first end of the sixth resistor is connected to the fourth node, a first NMOS transistor including a source, having its gate configured to receive the inner control voltage, and having its drain connected to a second end of the sixth resistor, and a second NMOS transistor having its source connected to the ground voltage, having its gate receiving the ON/OFF control signal, and having its drain connected to the source of the first NMOS transistor, where the voltage conversion unit provides the termination resistor control signal at the fourth node.

The control unit may convert the voltage level of the ON/OFF control signal using the bias voltage.

The control unit may comprise a voltage drop unit (e.g. a voltage divider unit) configured to generate an inner control voltage by dropping (e.g., dividing) a voltage of the bias voltage, and a voltage conversion unit configured to generate the termination resistor control signal using the bias voltage and the inner control voltage, where the termination resistor control signal has a voltage substantially equal to the bias voltage when the ON/OFF control signal is at a logic low level and has a voltage lower than the bias voltage when the ON/OFF control signal is at a logic high level.

In various exemplary embodiments, a HDMI transmitter includes a first NMOS transistor, a second NMOS transistor, a current source, and a termination circuit. The first NMOS transistor includes a source, and has its drain connected to a negative transmission pin, and has its gate receiving a data signal. The second NMOS transistor has its source connected to the source of the first NMOS transistor, its drain connected to a positive transmission pin, and its gate configured to receive an inverted data signal, where the inverted data signal is an inverted version of the data signal. The current source is connected between the source of the second NMOS transistor and a ground voltage. The termination circuit conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to an ON/OFF control signal, where a part of the termination circuit is formed on a well region. The well region is biased by a bias voltage higher than the lowest voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. Preferably, the well region is biased by the highest voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin.

The termination circuit may comprise a bias unit connected between the positive transmission pin and the negative transmission pin and configured to generate a bias voltage by selecting the higher (i.e., highest) voltage among the first voltage and the second voltage, a control unit configured to convert a voltage level of the ON/OFF control signal to generate a termination resistor control signal, and a termination resistor unit formed on the semiconductor well region biased by the bias voltage and conditionally providing the termination resistance between the positive transmission pin and the negative transmission pin in response to the termination resistor control signal.

In various exemplary embodiments, a multimedia source apparatus includes a storage device, a HDMI transmitter, and a processor. The storage device stores multimedia data. The HDMI transmitter transmits the multimedia data through a positive transmission pin and a negative transmission pin, and conditionally provides a termination resistor between the positive transmission pin and the negative transmission pin in response to an ON/OFF control signal. The processor provides the multimedia data stored in the storage device and the ON/OFF control signal to the HDMI transmitter. The HDMI transmitter comprises a first NMOS transistor including a source, having its drain connected to the negative transmission pin, and having its gate configured to receive a data signal, a second NMOS transistor having its source connected to the source of the first NMOS transistor, having its drain connected to the positive transmission pin, and having its gate configured to receive an inverted data signal, where the inverted data signal is an inverted version of the data signal, a current source connected between the source of the second NMOS transistor and a ground voltage, and a termination circuit configured to conditionally provide the termination resistor between the positive transmission pin and the negative transmission pin in response to the ON/OFF control signal, where a part of the termination circuit is formed on a semiconductor well region biased by the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

FIG. 1is a block diagram of a termination circuit according to an exemplary embodiment.

The termination circuit100ofFIG. 1may be used for a HDMI (High Definition Multimedia Interface) transmitter.

Referring toFIG. 1, the termination circuit100includes a bias unit110and a termination resistor unit120. The bias unit110is connected between a positive transmission pin TXP and a negative transmission pin TXN. The bias unit110receives a first voltage V1through the positive transmission pin TXP and a second voltage V2through the negative transmission pin TXN. The bias unit110generates a bias voltage Vbias by selecting the higher voltage among the first voltage V1and the second voltage V2. Thus, the bias unit110selects the higher (i.e., highest) voltage selected from among the first voltage V1and the second voltage V2and outputs the selected (higher) voltage as the bias voltage Vbias.

The termination resistor unit120includes a well region of a semiconductor material biased by the bias voltage Vbias. The termination resistor unit120is formed on the well region. The termination resistor unit120conditionally provides a termination resistance between the positive transmission pin TXP and the negative transmission pin TXN in response to a termination resistor control signal CON_ST.

The bias unit110and the termination resistor unit120are preferably both connected in parallel between the positive transmission pin TXP and the negative transmission pin TXN.

The bias unit110and the termination resistor unit120need not include any power source and may operate using only the first voltage V1and the second voltage V2as its power source.

Multimedia data may be transmitted through the positive transmission pin TXP and the negative transmission pin TXN in the form of a differential signal.

The termination circuit100may be operated to meet the requirements of each of the current and future HDMI standards. Because, as data transmission speed increases, a signal reflection on the output resistance of an open drain driver of the HDMI transmitter increases, the HDMI standard allows connection of a termination resistor between the positive transmission pin and the negative transmission pin when the data transmission speed is greater than 1.65 Gbps (Giga bit per second).

The termination circuit100ofFIG. 1according to exemplary embodiments may be used in a HDMI transmitter and conditionally provides a termination resistor (i.e., a termination resistance) between the positive transmission pin TXP and the negative transmission pin TXN in response to the termination resistor control signal CON_ST.

FIG. 2is a circuit diagram of an example110aof a bias unit110included in the termination circuit100ofFIG. 1.

Referring toFIG. 2, the bias unit110amay include a first PMOS (P-type Metal Oxide Semiconductor) transistor MP1and a second PMOS transistor MP2. Gates and drains of the first PMOS transistor MP1and the second PMOS transistor MP2may be cross-coupled. Thus, the higher voltage among V1of the positive transmission pin TXP and V2of the negative transmission pin TXN (relative to node N1) will be selected and output at node N1as Vbias.

Thus, the first PMOS transistor MP1may have its gate connected to the drain of the second PMOS transistor MP2, its drain connected to the positive transmission pin TXP, and its source connected to a first node N1. The second PMOS transistor MP2may have its gate connected to the drain of the first PMOS transistor MP1, its source connected to the first node N1, and its drain connected to the negative transmission pin TXN and the gate of the first PMOS transistor MP1. Thus the bias unit110aprovides the selected bias voltage Vbias at the first node N1.

The first PMOS transistor MP1and the second PMOS transistor MP2may be formed on the same N-type well region of a semiconductor substrate. The N-type well region may be coupled to the first node N1. Therefore, the N-type well region on which the first PMOS transistor MP1and the second PMOS transistor MP2are formed may be biased by the bias voltage Vbias outputted at the first node N1.

Hereinafter, the operation of the bias unit110awill be described with reference toFIG. 2.

According to the HDMI standard, a HDMI transmitter operates using a voltage of about 3.3V received from a HDMI receiver through the positive transmission pin TXP and the negative transmission pin TXN. During a data transmission, the first voltage V1of the positive transmission pin TXP and the second voltage V2of the negative transmission pin TXN may be about 3.3V or about 2.7V, respectively. For example, when the HDMI transmitter transmits a data signal having a logic high level, the first voltage V1of the positive transmission pin TXP may be about 3.3V and the second voltage V2of the negative transmission pin TXN may be about 2.7V. Alternatively, when the HDMI transmitter transmits a data signal having a logic low level, the first voltage V1of the positive transmission pin TXP may be about 2.7V and the second voltage V2of the negative transmission pin TXN may be about 3.3V.

Referring toFIG. 2, when the first voltage V1of the positive transmission pin TXP is about 3.3V and the second voltage V2of the negative transmission pin TXN is about 2.7V, thus, the first voltage V1is higher than the second voltage V2, the first PMOS transistor MP1may be turned ON and the second PMOS transistor MP2may be turned OFF. Therefore, charges may be transferred to the first node N1through the positive transmission pin TXP and the first PMOS transistor MP1, and the charges may be accumulated in the N-type well region, on which the first PMOS transistor MP1and the second PMOS transistor MP2are formed, since the N-type well region is connected to the first node N1. As such, the N-type well region may be biased by the first voltage V1and the bias unit110amay output the first voltage V1at the first node N1as the bias voltage Vbias.

Alternatively, when the first voltage V1of the positive transmission pin TXP is about 2.7V and the second voltage V2of the negative transmission pin TXN is about 3.3V, thus, the second voltage V2is higher than the first voltage V1, the first PMOS transistor MP1may be turned OFF and the second PMOS transistor MP2may be turned ON. Therefore, charges may be transferred to the first node N1through the negative transmission pin TXN and the second PMOS transistor MP2, and the charges may be accumulated in the N-type well region, on which the first PMOS transistor MP1and the second PMOS transistor MP2are formed, since the N-type well region is connected to the first node N1. As such, the N-type well region may be biased by the second voltage V2and the bias unit110amay output the second voltage V2at the first node N1as the bias voltage Vbias.

Therefore, the bias unit110amay selectively output the higher voltage among the first voltage V1received through the positive transmission pin TXP and the second voltage V2received through the negative transmission pin TXN as the bias voltage Vbias. In addition, the N-type well region on which the first PMOS transistor MP1and the second PMOS transistor MP2are formed may become biased by the higher voltage among the first voltage V1and the second voltage V2, selected as the bias voltage Vbias.

The sources of the first PMOS transistor MP1and the second PMOS transistor MP2include a region doped with P+ impurities, and the higher voltage among the first voltage V1and the second voltage V2is applied to the sources of the first PMOS transistor MP1and the second PMOS transistor MP2. Therefore, if the N-type well region is biased by a voltage lower than the highest voltage among the first voltage V1and the second voltage V2, a forward voltage may be applied to a diode junction between the sources of the first PMOS transistor MP1and the second PMOS transistor MP2and the N-type well region. As such, a leakage current may flow from the sources of the first PMOS transistor MP1and the second PMOS transistor MP2to the N-type well region.

However, as described above, the N-type well region is biased by the higher voltage among the first voltage V1and the second voltage V2, e.g., the bias voltage Vbias. Therefore, the bias unit110amay prevent the leakage current effectively.

Since the first PMOS transistor MP1and the second PMOS transistor MP2are series connected between the positive transmission pin TXP and the negative transmission pin TXN, the gate-source voltage and the gate-drain voltage of the first PMOS transistor MP1and the second PMOS transistor MP2are lower than the voltage difference between the positive transmission pin TXP and the negative transmission pin TXN. As described above, since one of the first voltage V1and the second voltage V2is about 3.3V and the other of the first voltage V1and the second voltage V2is about 2.7V, the voltage difference between the positive transmission pin TXP and the negative transmission pin TXN may be about 0.6V, such that the gate-source voltage and the gate-drain voltage of the first PMOS transistor MP1and the second PMOS transistor MP2may be lower than about 0.6V. Therefore, the first PMOS transistor MP1and the second PMOS transistor MP2may have a voltage tolerance lower than about 3.3V without degrading reliability of the termination circuit100. For example, the first PMOS transistor MP1and the second PMOS transistor MP2may have a voltage tolerance of about 1.8V or less.

FIG. 3is a circuit diagram of another example of a bias unit included in the termination circuit ofFIG. 1.

Referring toFIG. 3, the bias unit110bincludes a first PMOS transistor MP1, a second PMOS transistor MP2, a first protection resistor Resd1and a second protection resistor Resd2. Gates and drains of the first PMOS transistor MP1and the second PMOS transistor MP2are cross-coupled.

Comparing the bias unit110bto the bias unit110aofFIG. 2, the bias unit110bmay further include the first protection resistor Resd1and the second protection resistor Resd2. The first PMOS transistor MP1and the second PMOS transistor MP2included in the bias unit110bmay have the same structure and ON/OFF operation as the first PMOS transistor MP1and the second PMOS transistor MP2included in the bias unit110a. The structure and ON/OFF operation of the first PMOS transistor MP1and the second PMOS transistor MP2included in the bias unit110aare described above with reference toFIGS. 1 and 2. Therefore, a redundant detailed description of the first PMOS transistor MP1and the second PMOS transistor MP2included in the bias unit110bwill be omitted.

The first protection resistor Resd1is connected between the positive transmission pin TXP and the drain of the first PMOS transistor MP1. The second protection resistor Resd2is connected between the negative transmission pin TXN and the drain of the second PMOS transistor MP2.

The first protection resistor Resd1and the second protection resistor Resd2may have the same resistance.

The first protection resistor Resd1may block an electrostatic discharge (ESD) flowing into the first PMOS transistor MP1through the positive transmission pin TXP, so that the first protection resistor Resd1may protect the first PMOS transistor MP1. The second protection resistor Resd2may block an electrostatic discharge (ESD) flowing into the second PMOS transistor MP2through the negative transmission pin TXN, so that the second protection resistor Resd2may protect the second PMOS transistor MP2.

As described above, one or the other of the first PMOS transistor MP1and the second PMOS transistor MP2will be turned OFF during operation. Therefore, current that flows through the first protection resistor Resd1and through the second protection resistor Resd2may be substantially zero.

FIG. 4is a circuit diagram of an example of a termination resistor unit included in the termination circuit ofFIG. 1.

Referring toFIG. 4, the termination resistor unit120aincludes a first termination resistor Rt1, a second termination resistor Rt2and a third PMOS transistor MP3.

The first termination resistor Rt1may be connected between the positive transmission pin TXP and the source of the third PMOS transistor MP3.

The second termination resistor Rt2may be connected between the negative transmission pin TXN and the drain of the third PMOS transistor MP3.

The first termination resistor Rt1and the second termination resistor Rt2may have the same resistance. For example, a resistance of each of the first termination resistor Rt1and the second termination resistor Rt2may be about 150 ohms.

The third. PMOS transistor MP3may be formed on the semiconductor well region biased by the bias voltage Vbias provided from the bias unit110. The well region may be N-type well formed of a semiconductor material doped with N-type impurities. The third PMOS transistor MP3includes its source connected to the first termination resistor Rt1, its drain connected to the second termination resistor Rt2, and its gate configured to receive the termination resistor control signal CON_ST.

The third PMOS transistor MP3switchably connects the first termination resistor Rt1and the second termination resistor Rt2in series between the positive transmission pin TXP and the negative transmission pin. TXN in response to a logic (voltage) level of the termination resistor control signal CON_ST. For example, when the termination resistor control signal CON_ST is at a logic high level, the third PMOS transistor MP3is turned OFF such that the first termination resistor Rt1and the second termination resistor Rt2are not connected in series between the positive transmission pin TXP and the negative transmission pin TXN. Alternatively, when the termination resistor control signal CON_ST is at a logic low level, the third PMOS transistor MP3is turned ON such that the first termination resistor Rt1and the second termination resistor Rt2are connected in series between the positive transmission pin TXP and the negative transmission pin TXN.

As described above, the N-type well region on which the third PMOS transistor MP3is formed is biased by the bias voltage Vbias, and preferably the bias voltage Vbias is the highest voltage among the first voltage V1and the second voltage V2. Therefore, the N-type well region will be biased by the higher voltage among the first voltage V1and the second voltage V2. The source and the drain of the third PMOS transistor MP3may include a semiconductor region doped with P+ type impurities, and a voltage applied between the source and the drain of the third PMOS transistor MP3may be lower than about 3.3V. Therefore, a forward voltage will not be applied across P-N diode junctions formed between the source of the third PMOS transistor MP3and the N-type well region and between the drain of the third PMOS transistor MP3and the N-type well region. As such, the termination resistor unit120acan effectively prevent a leakage current that conventionally flows from the source of the third PMOS transistor MP3to the N-type well region and from the drain of the third PMOS transistor MP3to the N-type well region.

The third PMOS transistor MP3may have a voltage tolerance of about 1.8V or less. Therefore, since the highest voltage applied to the source or the drain of the third PMOS transistor MP3may be up to about 3.3V, a voltage of a logic low level of the termination resistor control signal CON_ST, which is applied to the gate of the third PMOS transistor MP3, may be higher than about 1.5V.

FIG. 5is a circuit diagram of another example of a termination resistor unit included in the termination circuit ofFIG. 1.

Referring toFIG. 5, a termination resistor unit120bmay include a plurality of termination resistor blocks121-1,121-2, . . . ,121-n(wherein n is a positive integer) connected in parallel between the positive transmission pin TXP and the negative transmission pin TXN.

The first termination resistor block121-1includes a first termination resistor Rt1, a second termination resistor Rt2and a third PMOS transistor MP3. The second termination resistor block121-2includes a third termination resistor Rt2, a fourth termination resistor Rt4and a third PMOS transistor MP3. Each n-th termination resistor block121-nmay include a fifth termination resistor Rt5, a sixth termination resistor Rt6and a third PMOS transistor MP3.

Each of the plurality of n termination resistor blocks121-1,121-2, . . . ,121-nhas the same structure as the termination resistor unit120aofFIG. 4. Thus, the termination resistor unit120bofFIG. 5may include a plurality of the termination resistor units120aofFIG. 4connected in parallel between the positive transmission pin TXP and the negative transmission pin TXN. Therefore, a redundant detailed description of each of the plurality of n termination resistor blocks121-1,121-2, . . . ,121-nwill be omitted.

In some exemplary embodiments, the first to the sixth termination resistors Rt1, Rt2, Rt3, Rt4, Rt5and Rt6may have the same resistance. In some other exemplary embodiments, the first to the sixth termination resistors Rt1, Rt2, Rt3, Rt4, Rt5and Rt6may have a different resistances.

The termination resistor control signal CON_ST may include n bits, and the third PMOS transistor MP3included in each of the plurality of termination resistor blocks121-1,121-2, . . . ,121-nmay be controlled by a corresponding one bit of the n-bit termination resistor control signal CON_ST. For example, the third PMOS transistor MP3included in the first termination resistor block121-1may be controlled by the first bit of the n-bit termination resistor control signal CON_ST<0>, the third PMOS transistor MP3included in the second termination resistor block121-2may be controlled by the second bit of the n-bit termination resistor control signal CON_ST<1>, and the third PMOS transistor MP3included in the n-th termination resistor block121-nmay be controlled by the n-th bit of the n-bit termination resistor control signal CON_ST<n−1>.

As illustrated inFIG. 5, the termination resistor unit120bmay adjust the total resistance of a conditional termination resistor connected between the positive transmission pin TXP and the negative transmission pin TXN by individually controlling a number of the termination resistor blocks turned ON using the n-bit termination resistor control signal CON_ST. For example, considering a case that the first to the sixth termination resistors Rt1, Rt2, Rt3, Rt4, Rt5and Rt6has the same resistance of 150 ohms, the termination resistor unit120bcan provide a maximum total termination resistance of 300 ohm between the positive transmission pin TXP and the negative transmission pin TXN by turning ON only one of the termination resistor blocks, and can provide a total termination resistance of 150 ohms between the positive transmission pin TXP and the negative transmission pin TXN by turning ON two termination resistor blocks.

FIG. 6is a circuit diagram of still another example of a termination resistor unit included in the termination circuit ofFIG. 1.

Referring toFIG. 6, a termination resistor unit120cmay include a first termination resistor Rt1, a second termination resistor Rt2, a fourth PMOS transistor MP4and a fifth PMOS transistor MP5.

The first termination resistor Rt1is connected between the positive transmission pin TXP and the source of the fourth PMOS transistor MP4.

The second termination resistor Rt2is connected between the negative transmission pin TXN and the drain of the fifth PMOS transistor MP5. The drain of the fourth PMOS transistor MP4and the source of the fifth PMOS transistor MP5are connected.

The first termination resistor Rt1and the second termination resistor Rt2may have the same resistance. For example, the resistance of the first termination resistor Rt1and of the second termination resistor Rt2may each be about 150 ohms.

The fourth PMOS transistor MP4and the fifth PMOS transistor MP5may be formed on the semiconductor well region biased by the bias voltage Vbias provided from the bias unit110. The well region may be an N-type well doped with N-type impurities. The fourth PMOS transistor MP4includes a source connected to the first termination resistor Rt1, a drain connected to the source of the fifth PMOS transistor MP5, and a gate connected to receive the termination resistor control signal CON_ST. The fifth PMOS transistor MP5includes a source connected to the drain of the fourth PMOS transistor MP4, a drain connected to the second termination resistor Rt2, and a gate receiving the termination resistor control signal CON_ST.

The fourth PMOS transistor MP4and the fifth PMOS transistor MP5are configured to switchably (conditionally) connect the first termination resistor Rt1and the second termination resistor Rt2in series between the positive transmission pin TXP and the negative transmission pin TXN in response to a logic level of the termination resistor control signal CON_ST. For example, when the termination resistor control signal CON_ST is at a logic high level, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5are turned OFF such that the first termination resistor Rt1and the second termination resistor Rt2are not connected between the positive transmission pin TXP and the negative transmission pin TXN. Alternatively, when the termination resistor control signal CON_ST is at a logic low level, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5are turned ON such that the first termination resistor Rt1and the second termination resistor Rt2are connected in series between the positive transmission pin TXP and the negative transmission pin TXN.

As described above, the N-type well region on which the fourth PMOS transistor MP4and the fifth PMOS transistor MP5are formed may be biased by the bias voltage Vbias, and the bias voltage Vbias can reliably expected to be the higher voltage among the first voltage V1and the second voltage V2. Therefore, the N-type well region will be reliably biased by the higher voltage among the first voltage V1and the second voltage V2. The sources and the drains of the fourth PMOS transistor MP4and the fifth PMOS transistor MP5may include a semiconductor region doped with P+ type impurities, and the voltage applied to the sources and the drains of the fourth PMOS transistor MP4and the fifth PMOS transistor MP5may be lower than about 3.3V. Therefore, a forward voltage may not be applied to P-N diode junctions between the N-type well region and the sources and the drains of the fourth PMOS transistor MP4and the fifth PMOS transistor MP5. As such, the termination resistor unit120cmay effectively prevent a leakage current that conventionally flows from the sources and the drains of the fourth PMOS transistor MP4and the fifth PMOS transistor to the N-type well region.

The fourth PMOS transistor MP4and the fifth PMOS transistor MP5may have a voltage tolerance of about 1.8V or less. Therefore, since a voltage applied to the sources and the drains of the fourth PMOS transistor MP4and the fifth PMOS transistor MP5may be up to about 3.3V, a voltage of a logic low level of the termination resistor control signal CON_ST, which is applied to the gates of the fourth PMOS transistor MP4and the fifth PMOS transistor MP5, may be higher than about 1.5V.

Comparing the termination resistor unit120cofFIG. 6to the termination resistor unit120aofFIG. 4, while the termination resistor unit120aincludes only one PMOS transistor MP3for controlling the connection of the first termination resistor Rt1and the second termination resistor Rt2in series between the positive transmission pin TXP and the negative transmission pin TXN, the termination resistor unit120cinclude two series-connected PMOS transistors MP4and MP5for controlling a connection of the first termination resistor Rt1and the second termination resistor Rt2in series between the positive transmission pin TXP and the negative transmission pin TXN.

As described above, one of the first voltage V1and the second voltage V2is about 3.3V and the other of the first voltage V1and the second voltage V2is about 2.7V. According to the termination resistor unit120aofFIG. 4, when a voltage of a logic high level of the termination resistor control signal CON_ST is lower than about 3.3V, the third PMOS transistor MP3may be weakly turned ON even if the gate-source voltage of the third PMOS transistor MP3is lower than the threshold voltage of the third PMOS transistor MP3. Therefore, the termination resistor unit120amay not completely disconnect the first termination resistor Rt1and the second termination resistor Rt2from between the positive transmission pin TXP and the negative transmission pin TXN even if the termination resistor control signal CON_ST is at a logic high level.

On the other hand, according to the termination resistor unit120cofFIG. 6, when a voltage of a logic high level of the termination resistor control signal CON_ST is lower than about 3.3V but higher than the median of the first voltage V1and the second voltage V2, (e.g., higher than about 3.0V), one of the fourth PMOS transistor MP4and the fifth PMOS transistor MP5may be weakly turned ON but the other of the fourth PMOS transistor MP4and the fifth PMOS transistor MP5will be completely turned OFF since the voltage applied to its gate is equal to or higher than the voltage of its source. Therefore, the termination resistor unit120cwill reliably completely disconnect the first termination resistor Rt1and the second termination resistor Rt2between the positive transmission pin TXP and the negative transmission pin TXN when the termination resistor control signal CON_ST is at a logic high level.

FIG. 7is a circuit diagram of still another example of a termination resistor unit included in the termination circuit ofFIG. 1.

Referring toFIG. 7, a termination resistor unit120dmay include a plurality of termination resistor blocks123-1,123-2, . . . ,123-n(n is a positive integer) connected in parallel between the positive transmission pin TXP and the negative transmission pin TXN.

The first termination resistor block123-1includes a first termination resistor Rt1, a second termination resistor Rt2, a fourth PMOS transistor MP4and a fifth PMOS transistor MP5. The second termination resistor block123-2includes a third termination resistor Rt2, a fourth termination resistor Rt4, a fourth PMOS transistor MP4and a fifth PMOS transistor MP5. Each n-th termination resistor block123-nincludes a fifth termination resistor Rt5, a sixth termination resistor Rt6, a fourth PMOS transistor MP4and a fifth PMOS transistor MP5.

Each of the plurality of termination resistor blocks123-1,123-2, . . . ,123-nmay have the same structure as the termination resistor unit120cofFIG. 6. Thus, the termination resistor unit120dofFIG. 7may include a plurality of the termination resistor units120cofFIG. 6connected in parallel between the positive transmission pin TXP and the negative transmission pin TXN. Therefore, a redundant detailed description of the plurality of termination resistor blocks123-1,123-2, . . . ,123-nwill be omitted.

In some exemplary embodiments, the first to the sixth termination resistors Rt1, Rt2, Rt3, Rt4, Rt5and Rt6all have the same resistance. In some other exemplary embodiments, the first to the sixth termination resistors Rt1, Rt2, Rt3, Rt4, Rt5and Rt6may have different resistances from each other.

The termination resistor control signal CON_ST may comprise n bits, and the fourth PMOS transistor MP4and the fifth PMOS transistor MP5included in each of the plurality of termination resistor blocks123-1,123-2, . . . ,123-nmay be controlled by a corresponding one bit of the n-bit termination resistor control signal CON_ST. For example, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5included in the first termination resistor block123-1may be controlled by a first bit of the n-bit termination resistor control signal CON_ST<0>, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5included in the second termination resistor block123-2may be controlled by a second bit of the n-bit termination resistor control signal CON_ST<1>, and the fourth PMOS transistor MP4and the fifth PMOS transistor MP5included in the n-th termination resistor block123-nmay be controlled by the n-th bit of the termination resistor control signal CON_ST<n−>.

As illustrated inFIG. 7, the termination resistor unit120dmay adjust the total resistance of a conditional termination resistor connected between the positive transmission pin TXP and the negative transmission pin TXN by controlling the number of the termination resistor blocks that are turned ON using the n-bit termination resistor control signal CON_ST. For example, considering a case that the each of the first to the sixth termination resistors Rt1, Rt2, Rt3, Rt4, Rt5and Rt6has a resistance of 150 ohms, the termination resistor unit120dmay provide a maximum total termination resistance of 300 ohm between the positive transmission pin TXP and the negative transmission pin TXN by turning on one termination resistor block, and provide a termination resistor of 150 ohms between the positive transmission pin TXP and the negative transmission pin TXN by turning on two termination resistor blocks.

FIG. 8is a cross sectional view of an example of the termination circuit ofFIG. 1.

The termination circuit100aofFIG. 8is an example of the termination circuit100when the termination circuit100includes the bias unit110bofFIG. 3and the dual-transistor termination resistor unit120cofFIG. 6.

Referring toFIG. 8, an N-type well region N-WELL is formed on a P-type semiconductor substrate P-SUBSTRATE. The first PMOS transistor MP1and the second PMOS transistor MP2included in the bias unit110band the fourth PMOS transistor MP4and the fifth PMOS transistor MP5included in the termination resistor unit120ceach include gate electrodes formed on the N-type well region.

As described above, the bias unit110boutputs the bias voltage Vbias at the first node N1by selecting the higher voltage among the first voltage V1received through the positive transmission pin TXP and the second voltage V2received through the negative transmission pin TXN. The first node N1may be connected to the N-type well region through an area formed in the N-type well region and doped with N+ impurities. Therefore, the N-type well region on which the first PMOS transistor MP1, the second PMOS transistor MP2, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5are formed may be biased by the bias voltage Vbias.

Since the N-type well region is biased by the higher voltage among the first voltage V1and the second voltage V2, a forward voltage will not be applied to P-N diode junctions between the N-type well region and sources and drains of the first PMOS transistor MP1, the second PMOS transistor MP2, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5. Therefore, the termination circuit100amay effectively prevent a leakage current that conventionally flows from the sources and the drains of the first PMOS transistor MP1, the second PMOS transistor MP2, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5to the N-type well region.

The circuit structure of the termination circuit100athat includes the bias unit110bofFIG. 3and the termination resistor unit120cofFIG. 6is described above with reference toFIG. 8. The termination circuit100that includes the bias unit110aand one of the termination resistor units120a,120band102dmay have similar circuit structure as the termination circuit100aofFIG. 8.

As described with reference toFIGS. 1 to 8, the bias unit110and the termination resistor unit120need not include a separate power source but may operate using only the first voltage V1and the second voltage V2.

FIG. 9is a block diagram of a termination circuit according to exemplary embodiments.

An exemplary implementation of termination circuit200ofFIG. 9may be used for a HDMI transmitter.

Referring toFIG. 9, the termination circuit200includes a bias unit210, a termination resistor unit220and a control unit230.

Comparing to the termination circuit100ofFIG. 1, the termination circuit200further includes the control unit230. The bias unit210and the termination resistor unit220included in the termination circuit200may have the same structure and manner of operation as the bias unit110and the termination resistor unit120included in the termination circuit100. The structure and operation of the bias unit110and the termination resistor unit120included in the termination circuit100are thus described above with reference toFIGS. 1 to 8. Therefore, a redundant detailed description of the bias unit210and the termination resistor unit220included in the termination circuit200will be omitted.

The control unit230converts the voltage level of an ON/OFF control signal ON_OFF to generate the termination resistor control signal CON_ST. The ON/OFF control signal ON_OFF may be provided from an external device.

The control unit230need not include any additional power source and may generate the termination resistor control signal CON_ST by converting a voltage level of the ON/OFF control signal ON_OFF using only the first voltage V1and the second voltage V2. The control unit230may generate the termination resistor control signal CON_ST by converting voltages of a logic high level and of a logic low level of the ON/OFF control signal ON_OFF into voltages that are able to drive individual PMOS transistors included in the termination resistor unit220without exceeding the voltage tolerance of the PMOS transistors. As described above, the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5included in the termination resistor unit220may have a voltage tolerance of about 1.8V or less. Since the voltage applied to the sources and the drains of the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5may be up to about 3.3V, the active voltage of the termination resistor control signal CON_ST, which is applied to the gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5, may be equal to or higher than about 1.5V.

FIG. 10is a circuit diagram of an example of a control unit included in the termination circuit ofFIG. 9.

Referring toFIG. 10, the control unit230may include a common voltage generation unit231, a voltage drop unit233and a voltage conversion unit235.

The common voltage generation unit231generates a common voltage Vcomm using the first voltage V1and the second voltage V2. The common voltage Vcomm may have a voltage between the first voltage V1and the second voltage V2. As described above, since one of the first voltage V1and the second voltage V2is about 3.3V and the other of the first voltage V1and the second voltage V2is about 2.7V, the common voltage Vcomm may be about 3.0V.

The common voltage generation unit231may include a first resistor R1and a second resistor R2. The first resistor R1is connected between the positive transmission pin TXP and a second node N2. The second resistor R2is connected between the negative transmission pin TXN and the second node N2. The first resistor R1and the second resistor R2may have the same resistance. Thus the common voltage generation unit231may output the common voltage Vcomm at the second node N2.

The voltage drop unit233may generate an inner control voltage Vic by dividing the voltage of the common voltage Vcomm.

The voltage drop unit233may include a third resistor R3and a fourth resistor R4. The third resistor R3is connected between the second node N2and a third node N3. The fourth resistor R4is connected between the third node N3and a ground voltage GND. The voltage drop unit233may thus divide the common voltage Vcomm using the third resistor R3and the fourth resistor R4and thus output the inner control voltage Vic at the third node N3having a voltage lower than the common voltage Vcomm.

As will be described below, the inner control voltage Vic may be used to control the first NMOS(N-type Metal Oxide Semiconductor) transistor MN1included in the voltage conversion unit235. Therefore, the ratio of the third resistor R3to the fourth resistor R4may be adjusted such that the inner control voltage Vic is able to drive the first NMOS transistor MN1without exceeding the voltage tolerance of the first NMOS transistor MN1.

According to the HDMI standard, a HDMI transmitter may conduct a current up to 200 uA from a voltage of about 3.3V received from a HDMI receiver even if the HDMI transmitter is turned OFF. Therefore, the first resistor R1and the second resistor R2included in the common voltage generation unit231and the third resistor R3and the fourth resistor R4included in the voltage divider unit233preferably have a very large resistance such as mega ohms, so that the transmitter-OFF current that flows through the common voltage generation unit231and the voltage divider unit233will be lower than 200 uA.

The voltage conversion unit235generates the termination resistor control signal CON_ST in response to the ON/OFF control signal ON_OFF using the common voltage Vcomm and the inner control voltage Vic. The termination resistor control signal CON_ST has a voltage substantially equal to the common voltage Vcomm when the ON/OFF control signal ON_OFF is at a logic low level, and has a voltage lower than the common voltage Vcomm when the ON/OFF control signal ON_OFF is at a logic high level. The resulting ON/OFF control signal ON_OFF may have a voltage of about 0V in a logic low level and have a voltage of about 1.8V or less in a logic high level. Thus, the control unit230inverts and level-shifts the ON/OFF control signal ON_OFF.

The voltage conversion unit235may include a fifth resistor R5, a sixth resistor R6, the first NMOS transistor MN1and a second NMOS transistor MN2.

The fifth resistor R5is connected between the second node N2and a fourth node N4. The sixth resistor R6is connected between the fourth node N4and the drain of the first NMOS transistor MN1. The first NMOS transistor MN1includes its source connected to the drain of the second NMOS transistor MN2, its gate connected to receive the inner control voltage Vic, and its drain connected to the sixth resistor R6. The second NMOS transistor MN2includes its source connected to the ground voltage GND, its gate configured to receive the ON/OFF control signal ON_OFF, and its drain connected to the source of the first NMOS transistor MN1.

The voltage conversion unit235outputs the termination resistor control signal CON_ST at the fourth node N4.

The first NMOS transistor MN1and the second NMOS transistor MN2may have a voltage tolerance of about 1.8V or less. Therefore, the gate-source voltages and the gate-drain voltages of the first NMOS transistor MN1and the second NMOS transistor MN2may need to be kept lower than about 1.8V.

The ON/OFF control signal ON_OFF may have a voltage of about 0V in a logic low level and have a voltage of about 1.8V or less in a logic high level. For example, the ON/OFF control signal ON_OFF may have a voltage of about 0V in a logic low level and have a voltage of about 1.0V in a logic high level. Therefore, the gate-source voltage of the second NMOS transistor MN2may be kept lower than about 1.8V.

If the voltage conversion unit235does not include the first NMOS transistor MN1so that the sixth resistor R6is directly connected to the drain of the second NMOS transistor MN2, reliability of the control unit230may be degraded. Thus, when the ON/OFF control signal ON_OFF of a logic low level, which has a voltage of about 0V, is applied to the gate of the second NMOS transistor MN2, the second NMOS transistor MN2may be turned OFF and the common voltage Vcomm may be applied to the drain of the second NMOS transistor MN2since no current flows from the second node N2through the voltage conversion unit235. As described above, since the common voltage Vcomm may have a voltage of about 3.0V, the gate-drain voltage of the second NMOS transistor MN2may become about 3.0V, which exceeds the voltage tolerance of the second NMOS transistors MN2.

However, since the voltage conversion unit235includes the first NMOS transistor MN1between the sixth resistor R6and the drain of the second NMOS transistor MN2, the common voltage Vcomm will not be applied to the drain of the second NMOS transistor MN2even if the ON/OFF control signal ON_OFF of a logic low level, which has a voltage of about 0V, is applied to the gate of the second NMOS transistor MN2. Therefore, the second NMOS transistor MN2may operate without exceeding the voltage tolerance of the second NMOS transistor MN2.

As described above, the voltage drop unit233may provide the voltage conversion unit235with the inner control voltage Vic that is able to drive the first NMOS transistor MN1without exceeding the voltage tolerance of the first NMOS transistor MN1. Therefore, the gate-source voltage and the gate-drain voltage of the first NMOS transistor MN1may be kept lower than about 1.8V.

Hereinafter, the preferred operation of the control unit230will be described with reference toFIGS. 9 and 10.

When the ON/OFF control signal ON_OFF is at a logic low level, the second NMOS transistor MN2is turned OFF such that no current flows from the second node N2through the voltage conversion unit235. Therefore, the voltage of the fourth node N4may be the same as a voltage of the second node N2, being at the common voltage Vcomm. As such, the control unit230then outputs the common voltage Vcomm at the fourth node N4to the termination resistor unit220as the termination resistor control signal CON_ST of a logic high level.

Alternatively, when the ON/OFF control signal ON_OFF is at a logic high level, the second NMOS transistor MN2may be turned ON such that a current flows from the second node N2through the voltage conversion unit235. Therefore, the voltage of the fourth node N4may be lower than the voltage of the second node N2, (e.g., the common voltage Vcomm). As such, the control unit230then outputs a voltage lower than the common voltage Vcomm at the fourth node N4to the termination resistor unit220as the termination resistor control signal CON_ST of a logic low level.

As described above, the termination resistor control signal CON_ST may be applied to the gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5included in the termination resistor unit220, and the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5may have a voltage tolerance of about 1.8V or less. Since the voltage applied to the sources and the drains of the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5may be up to about 3.3V, resistances of the fifth resistor R5and the sixth resistor R6of the voltage conversion unit235will preferably be determined such that the voltage of a logic low level of the termination resistor control signal CON_ST may be equal to or higher than about 1.5V. Therefore, the termination circuit200may operate without degrading reliability.

As described with reference toFIG. 10, the control unit230need not include any additional power source but can operate using only the first voltage V1and the second voltage V2.

FIG. 11is a block diagram of a termination circuit according to exemplary embodiments.

The termination circuit300ofFIG. 11may be used for a HDMI transmitter.

Referring toFIG. 11, the termination circuit300includes a bias unit310, a termination resistor unit320and a control unit330.

Compared with the termination circuit100ofFIG. 1, the termination circuit300further includes the control unit330. The bias unit310and the termination resistor unit320included in the termination circuit300may have the same structure and operation as the bias unit110and the termination resistor unit120included in the termination circuit100. The structure and operation of the bias unit110and the termination resistor unit120included in the termination circuit100are described above with reference toFIGS. 1 to 8. Therefore, a redundant detailed description of the bias unit310and the termination resistor unit320included in the termination circuit300will be omitted.

The control unit330converts a voltage level of an ON/OFF control signal ON_OFF to generate the termination resistor control signal CON_ST. The ON/OFF control signal ON_OFF may be provided from an external device.

The control unit330need not include any additional power source and may generate the termination resistor control signal CON_ST by converting the voltage level of the ON/OFF control signal ON_OFF using only the bias voltage Vbias received from the bias unit310. The control unit330may generate the termination resistor control signal CON_ST by converting voltages of a logic high level and a logic low level of the ON/OFF control signal ON_OFF into voltages that are suited to drive PMOS transistors included in the termination resistor unit320without exceeding the voltage tolerance of the PMOS transistors. As described above, the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5included in the termination resistor unit320may have a voltage tolerance of about 1.8V or less. Since a voltage applied to the sources and the drains of the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5may be up to about 3.3V, a voltage of the termination resistor control signal CON_ST, which is applied to the gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5, may be equal to or higher than about 1.5V.

FIG. 12is a circuit diagram of an example of a control unit included in the termination circuit ofFIG. 11.

Referring toFIG. 12, the control unit330includes a voltage drop unit333and a voltage conversion unit335.

The voltage drop unit333receives the bias voltage Vbias from the bias unit310and generates an inner control voltage Vic by dropping (e.g., dividing) the voltage of the bias voltage Vbias.

The voltage conversion unit335generates the termination resistor control signal CON_ST in response to the ON/OFF control signal ON_OFF using the bias voltage Vbias and the inner control voltage Vic. The termination resistor control signal CON_ST thus has a voltage substantially equal to the bias voltage Vbias when the ON/OFF control signal ON_OFF is at a logic low level, and has a voltage lower than the bias voltage Vbias when the ON/OFF control signal ON_OFF is at a logic high level. Thus, the control unit330inverts and level-shifts the ON/OFF control signal ON_OFF.

Compared with the control unit230ofFIG. 10, the control unit330does not include a common voltage generation unit that outputs a common voltage at the second node N2but instead receives the bias voltage Vbias at the second node N2from the bias unit310. Thus, the voltage drop unit333and the voltage conversion unit335included in the control unit330have the same structure and operation as the voltage drop unit233and the voltage conversion unit235included in the control unit230. The structure and preferred operation of the voltage drop unit233and the voltage conversion unit235included in the control unit230are described above with reference toFIG. 10. Therefore, a redundant detailed description of the voltage drop unit333and the voltage conversion unit335included in the control unit330will be omitted.

Hereinafter, the operation of the control unit330will be described with reference toFIGS. 11 and 12.

When the ON/OFF control signal ON_OFF is at a logic low level, the second NMOS transistor MN2is turned OFF such that no current flows from the second node N2through the voltage conversion unit335. Therefore, the voltage of the fourth node N4will be the same as the voltage of the second node N2, e.g., the bias voltage Vbias. As such, the control unit330then outputs the bias voltage Vbias at the fourth node N4to the termination resistor unit320as the termination resistor control signal CON_ST of a logic high level.

Alternatively, when the ON/OFF control signal ON_OFF is at a logic high level, the second NMOS transistor MN2is turned ON such that a current flows from the second node N2through the voltage conversion unit335. Therefore, the voltage of the fourth node N4will be lower than the voltage of the second node N2, e.g., the bias voltage Vbias. As such, the control unit330then outputs a voltage lower than the bias voltage Vbias at the fourth node N4to the termination resistor unit320as the termination resistor control signal CON_ST of a logic low level.

As described above, the termination resistor control signal CON_ST may be applied to the gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5included in the termination resistor unit320, and the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5may have a voltage tolerance of about 1.8V or less. Since the voltage applied to the sources and the drains of the third PMOS transistor MP3, the fourth PMOS transistor MP4and the fifth PMOS transistor MP5may be up to about 3.3V, resistances of the fifth resistor R5and the sixth resistor R6of the voltage conversion unit335will preferably be determined such that the voltage of a logic low level of the termination resistor control signal CON_ST will be equal to or higher than about 1.5V. Therefore, the termination circuit300may operate without degrading reliability.

As described with reference toFIG. 12, the control unit330need not include any additional power source but operate using only the bias voltage Vbias provided from the bias unit310.

In a conventional termination circuit, a well region on which MOS transistors are formed is not biased at all or is biased by a voltage lower than either one of the voltage received through the positive transmission pin and the voltage received through the negative transmission pin. Therefore, a leakage current may conventionally flow from the sources and the drains of the MOS transistors to the well region.

On the other hand, as described above with reference toFIGS. 1 to 12, the conditional termination circuits100,200and300may be formed on the well region biased by the highest voltage selected from among the first voltage V1received through the positive transmission pin TXP and the second voltage V2received through the negative transmission pin TXN. Therefore, the termination circuits100,200and300may effectively prevent the conventional leakage current.

Conventional termination circuits are embodied using MOS transistors having a voltage tolerance of about 3.3V. However, as a semiconductor process technique advances, such as a deep submicron process, it becomes difficult to produce MOS transistors having a voltage tolerance up to 3.3V. Therefore, it becomes difficult to produce a conventional termination circuit on a chip.

On the other hand, the conditional termination circuits100,200and300may include MOS transistors having a voltage tolerance lower than about 3.3V without degrading reliability. Therefore, the termination conditional circuits100,200and300may be embodied on a chip even by an advanced process technique, such as a deep submicron process.

FIG. 13is a flow chart of a method of providing a conditional termination resistor according to exemplary embodiments.

The method of providing a conditional termination resistor ofFIG. 13may be used for a HDMI transmitter.

The method of providing a conditional termination resistor ofFIG. 13may be performed by the conditional termination circuits100,200and300.

Referring toFIGS. 1 to 13, the bias voltage Vbias is generated by selecting the higher voltage among the first voltage V1received through the positive transmission pin TXP and the second voltage V2received through the negative transmission pin TXN S100. For example, the bias voltage Vbias may be generated using the first PMOS transistor MP1and the second PMOS transistor MP2connected between the positive transmission pin TXP and the negative transmission pin TXN. The gates and the drains of the first PMOS transistor MP1and the second PMOS transistor MP2may be cross-coupled.

The termination resistor control signal CON_ST is generated by converting (e.g., inverting and level-shifting) a voltage level of the ON/OFF control signal ON_OFF S200. The ON/OFF control signal ON_OFF may be provided from an external device.

In some exemplary embodiments, the termination resistor control signal CON_ST may be generated by converting a voltage level of the ON/OFF control signal ON_OFF using the first voltage V1and the second voltage V2S210. In this case, the common voltage Vcomm having a voltage between the first voltage V1and the second voltage V2may be generated using the first voltage V1and the second voltage V2S211, the inner control voltage Vic may be generated by dropping (e.g., dividing) the voltage of the common voltage Vcomm S213, and the termination resistor control signal CON_ST may be generated in response to (e.g., by inverting) the ON/OFF control signal ON_OFF using the common voltage Vcomm and the inner control voltage Vic S215. The termination resistor control signal CON_ST may have a voltage substantially equal to the common voltage Vcomm when the ON/OFF control signal ON_OFF is at a logic low level, and have a voltage lower than the common voltage Vcomm when the ON/OFF control signal ON_OFF is at a logic high level.

In other exemplary embodiments, the termination resistor control signal CON_ST may be generated by converting (e.g., inverting and level-shifting) the voltage level of the ON/OFF control signal ON_OFF using the bias voltage Vbias S220. In this case, the inner control voltage Vic may be generated by dropping (e.g., dividing) the voltage of the bias voltage Vbias S223, and the termination resistor control signal CON_ST may be generated in response to (e.g., by inverting) the ON/OFF control signal ON_OFF using the bias voltage Vbias and the inner control voltage Vic S225. The resulting termination resistor control signal CON_ST has a voltage substantially equal to the bias voltage Vbias when the ON/OFF control signal ON_OFF is at a logic low level, and has a voltage lower than the bias voltage Vbias when the ON/OFF control signal ON_OFF is at a logic high level.

The well region on which PMOS transistors are formed are biased by the bias voltage Vbias, and a termination resistance is conditionally provided between the positive transmission pin TXP and the negative transmission pin TXN in response to the termination resistor control signal CON_ST S300. For example, at least one PMOS transistor receiving the termination resistor control signal CON_ST as a control signal may operate as an ON/OFF switch so that a termination resistor is not connected between the positive transmission pin TXP and the negative transmission pin TXN while the termination resistor control signal CON_ST is at a logic high level, and the termination resistor is connected between the positive transmission pin TXP and the negative transmission pin TXN while the termination resistor control signal CON_ST is at a logic low level.

The method of providing a termination resistor ofFIG. 13may be used for a HDMI transmitter for conditionally providing the termination resistance between the positive transmission pin TXP and the negative transmission pin TXN. A HDMI transmitter operates using a voltage of about 3.3V provided by a HDMI receiver. However, the method of providing a conditional termination resistor ofFIG. 13may be performed by the termination circuit100,200and300that includes the PMOS transistors having a voltage tolerance of about 1.8V or less. Therefore, a voltage of a logic low level of the termination resistor control signal CON_ST, which is used for controlling the PMOS transistor, may be controlled to be equal to or higher than about 1.5V.

FIG. 14is a block diagram of a HDMI transmitter according to exemplary embodiments.

Referring toFIG. 14, a HDMI transmitter400includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a constant current source IO and a conditional termination circuit410.

The fourth NMOS transistor MN4includes its source connected to the current source IO, its drain connected to the negative transmission pin TXN, and its gate configured to receive a data signal D.

The third NMOS transistor MN3includes its source connected to the current source IO, its drain connected to the positive transmission pin TXP, and its gate connected to receive an inverted data signal Db, which is an inverted version of the data signal D.

The constant current source is connected between the ground voltage GND and each of the third NMOS transistor MN3and the fourth NMOS transistor MN4.

The third NMOS transistor MN3and the fourth NMOS transistor MN4can operate as a driver that transmits the data signal D to a HDMI receiver as current alternately through the positive transmission pin TXP and through the negative transmission pin TXN as a form of a differential signal.

The conditional termination circuit410conditionally provides a predetermined (e.g., dynamically selected) termination resistance between the positive transmission pin TXP and the negative transmission pin TXN in response to the ON/OFF control signal ON_OFF. At least a part of the conditional termination circuit410is formed on a well region biased by the higher voltage among the first voltage V1received through the positive transmission pin TXP and the second voltage V2received through the negative transmission pin TXN.

The conditional termination circuit410may include a bias unit411, a termination resistor unit413and a control unit415.

The bias unit411may be connected between the positive transmission pin TXP and the negative transmission pin TXN. The bias unit411may generate the bias voltage Vbias by selecting and outputting the higher voltage among the first voltage V1and the second voltage V2.

The control unit415may convert (e.g., invert and/or level-shift) a voltage level of the ON/OFF control signal ON_OFF to generate the termination resistor control signal CON_ST.

The termination resistor unit413may be formed on the well region biased by the bias voltage Vbias, and conditionally provides the termination resistance between the positive transmission pin TXP and the negative transmission pin TXN in response to the termination resistor control signal CON_ST.

The termination circuit410may be implemented as either one of the termination circuit200ofFIG. 9and the termination circuit300ofFIG. 11. The structure and operation of the termination circuit200and the termination circuit300are described above with reference toFIGS. 9 and 12. Therefore, a redundant detailed description of the termination circuit410will be omitted.

An operation of the HDMI transmitter400will be described below with reference toFIG. 15.

FIG. 15is a block diagram of a HDMI system according to exemplary embodiments.

Referring toFIG. 15, a HDMI system500includes a HDMI transmitter400, a HDMI receiver510and a transmission line Z0.

The HDMI transmitter400included in the HDMI system500may be implemented as the HDMI transmitter400ofFIG. 14.

The positive transmission pin TXP and the negative transmission pin TXN of the HDMI transmitter400are connected to the HDMI receiver510through the transmission line Z0.

According to the HDMI standard, the HDMI receiver510alternately provides a supply voltage AVcc of about 3.3V to the positive transmission pin TXP and the negative transmission pin TXN of the HDMI transmitter400through the transmission line Z0. The HDMI transmitter400may operate using the voltage of about 3.3V received through the positive transmission pin TXP and through the negative transmission pin TXN from the HDMI receiver510.

The HDMI receiver510may include a termination resistor Rrx between the supply voltage AVcc and the transmission line Z0for decreasing a signal reflection on the HDMI receiver510. The termination resistor Rrx may have the same impedance as the transmission line Z0. For example, when an impedance of the transmission line Z0is 50 ohms, the termination resistor Rrx may have an impedance of 50 ohms.

The HDMI transmitter400may receive the data signal D and the inverted data signal Db, which are to be transmitted to the HDMI receiver510, from an external device. As illustrated inFIGS. 14 and 15, the data signal D may be provided to the gate of the fourth NMOS transistor MN4and the inverted data signal Db may be provided to the gate of the third NMOS transistor MM3.

When the data signal D is at a logic low level, the third NMOS transistor MN3is turned ON, such that the current may flow from the supply voltage AVcc of the HDMI receiver510to the ground voltage GND through the transmission line Z0, the positive transmission pin TXP and the third NMOS transistor MN3. Therefore, the first voltage V1of the positive transmission pin TXP may be about 2.7V and lower than the supply voltage AVcc since the supply voltage AVcc may drop along the transmission line Z0.

In addition, when the data signal D is at a logic low level, the fourth NMOS transistor MN4is turned OFF, such that substantially no current may flow from the supply voltage AVcc of the HDMI receiver510to the ground voltage GND through the transmission line Z0, the negative transmission pin TXN and the fourth NMOS transistor MN4. Therefore, the second voltage V2of the negative transmission pin TXN may be substantially equal to the supply voltage AVcc, which is about 3.3V.

Alternatively, when the data signal D is at a logic high level, the third NMOS transistor MN3is turned OFF and the fourth NMOS transistor MN4may be turned ON. Therefore, the first voltage V1of the positive transmission pin TXP may be substantially equal to the supply voltage AVcc, which is about 3.3V, and the second voltage V2of the negative transmission pin TXN may be about 2.7V and lower than the supply voltage AVcc since the supply voltage AVcc may drop along the transmission line Z0.

A comparator511included in the HDMI receiver510may determine the logic level of the data signal D by comparing the voltage of a signal transmitted through the positive transmission pin TXP with the voltage of a signal transmitted through the negative transmission pin TXN.

As described above, if the HDMI transmitter400does not include a termination resistor between the positive transmission pin TXP and the negative transmission pin TXN, as a data transmission speed increases, signal reflection on the HDMI transmitter400increases such that signal integrity is degraded. For this reason, the HDMI standard allows for a HDMI transmitter to couple a termination resistor between a positive transmission pin and a negative transmission pin when the data transmission speed is greater than 1.65 Gbps (Giga bit per second).

As illustrated inFIGS. 14 and 15, the HDMI transmitter400includes the conditional termination circuit410between the positive transmission pin TXP and the negative transmission pin TXN. The conditional termination circuit410conditionally provides a predetermined termination resistance between the positive transmission pin TXP and the negative transmission pin TXN in response to the ON/OFF control signal ON_OFF.

The termination circuit410may be implemented as one of the termination circuit200ofFIG. 9and the termination circuit300ofFIG. 11. The structure and operation of the termination circuit200and the termination circuit300are described above with reference toFIGS. 9 and 12. Therefore, a redundant detailed description of the termination circuit410will be omitted.

FIG. 16is a block diagram of a multimedia source apparatus according to exemplary embodiments.

Referring toFIG. 16, a multimedia source apparatus600includes a processor610, a storage device620and a HDMI transmitter630.

The storage device620stores multimedia data. The storage device620may include a non-volatile memory device such as a flash memory device, a solid state drive (SSD), a hard disk drive (HHD), a CD-ROM, etc. The storage device620may be embodied as a removable memory card, such as an SD memory card.

The HDMI transmitter630transmits the multimedia data through the positive transmission pin TXP and the negative transmission pin TXN. The HDMI transmitter630conditionally provides a predetermined termination resistance between the positive transmission pin TXP and the negative transmission pin TXN in response to the ON/OFF control signal ON_OFF.

The HDMI transmitter630may be implemented as the HDMI transmitter400ofFIG. 14. The structure and operation of the HDMI transmitter400are described above with reference toFIGS. 1 and 15. Therefore, a redundant detailed description of the HDMI transmitter630will be omitted.

The processor610controls the storage device620and the HDMI transmitter630. The processor610reads the multimedia data from the storage device620and provides the multimedia data to the HDMI transmitter630. The processor610provides the ON/OFF control signal ON_OFF to the HDMI transmitter630.

The processor610may perform specific calculations, or computing functions for various tasks. For example, the processor610may include a microprocessor, a central processing unit (CPU), etc. The processor610may be connected to the storage device620and the HDMI transmitter630via an address bus, a control bus, and/or a data bus. In addition, the processor610may be connected to an extended bus such as a peripheral component interconnection (PCI) bus.

The processor610may be embodied as a single core architecture or a multi core architecture. For example, the processor610may be embodied as a single core architecture when an operating frequency of the processor610is less than 1 GHz, and the processor610may be embodied as a multi core architecture when an operating frequency of the processor610is greater than 1 GHz. The processor610is embodied as a multi core architecture and may communicate with peripheral devices via an advanced extensible interface (AXI) bus.

The multimedia source apparatus600may further include a memory device640, a user interface650and an input/output device660. Although not illustrated inFIG. 16, the multimedia source apparatus600may further include ports to communicate with a video card, a sound card, a memory card, a universal serial bus (USB) device, etc.

The memory device640may store data for operations of the multimedia source apparatus600. For example, the memory device640may include at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, etc. and/or at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, etc.

The user interface650may include devices required for a user to control the multimedia source apparatus600. The input/output device660may include an input device (e.g., a keyboard, a keypad, a mouse, etc.), an output device (e.g., a printer, a monitor, a speaker, etc.).

The multimedia source apparatus600may comprise any of several types of electronic devices, such as a digital versatile disk (DVD) player, a set-top box, a cellular phone, a smart phone, a personal digital assistant (PDA), a desktop computer, a laptop computer, a personal media player (PMP), a digital camera, etc.

The foregoing is illustrative of the present inventive concept and is not to be construed as limiting thereof. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims.