Display device and data driver

A data driver for a display device comprises a first boost circuit, a first gate clock generation circuit, a first level shift circuit, and a data drive circuit. The first boost circuit is used to receive a supply voltage value and generate at least one preset voltage value. The first gate clock generation circuit is electrically coupled to the first boost circuit, and is used to receive a plurality of timing signals and at least one preset voltage value, and generate at least one first timing signal. The first level shift circuit is used to receive the at least one first timing signal and generate at least one gate timing signal. The data drive circuit is used to receive the timing signals, and generate a plurality of display data signals.

BACKGROUND

Technical Field

The present invention relates a display device and a data driver thereof, and in particular, a display device suitable for a narrow bezel and a data driver thereof.

Related Art

With the rapid development of science and technology, the life quality is improved, and consumers have increasingly high requirements on electronic devices, for example, pursuing for a lighter and thinner design, a higher speed, or a better visual effect. One method for improving the visual effect of an electronic device is to increase the display range of the electronic device. However, as the display range is increased, the area occupied by the bezel is reduced, and consequently the area for configuring hardware elements and circuit wirings is reduced, leading to difficulties in design.

SUMMARY

To achieve the foregoing objective of reducing the bezel in a more convenient manner, the present invention provides an embodiment of a data driver applicable to a display device, the data driver including a first boost circuit, a first gate clock generation circuit, a first level shift circuit, and a data drive circuit, where the first boost circuit is used to receive a supply voltage value, and generate at least one preset voltage value; the first gate clock generation circuit is electrically coupled to the first boost circuit, and is used to receive a plurality of timing signals and the at least one preset voltage value, and generate at least one first timing signal; the first level shift circuit is used to receive the at least one first timing signal and generate at least one first gate timing signal; and the data drive circuit is used to receive the timing signals, and generate a plurality of display data signals.

The present invention further provides a display device, including a power supply circuit, a timing controller, a first data driver, a gate driver, and a plurality of pixel units, where the power supply circuit is used to provide a supply voltage value; the timing controller is used to provide a plurality of timing signals; the first data driver is electrically coupled to the timing controller and the power supply circuit, and is used to receive the plurality of timing signals and the supply voltage value, and generate a plurality of display data signals and a plurality of first gateway timing signals; the gate driver is electrically coupled to the first data driver, and is used to receive the plurality of first gateway timing signals, and generate a plurality of gate driving signals; and the plurality of pixel units are electrically coupled to the first data driver and the gate driver, and are used to determine, according to the corresponding gate driving signals, whether to receive the corresponding display data signals.

Based on the above, because the data driver includes the first boost circuit, the first gate clock generation circuit, the first level shift circuit, and the data drive circuit, the number of elements and the volume of a printed circuit board can be effectively reduced, so that the area of a bezel of the display device can be reduced. In addition, because the timing controller is independent of the data driver, the data driver of the present invention receives timing signals output by a same timing controller, and when a single display device needs to be driven by a plurality of data drivers, the plurality of data drivers can perform operations without requiring any additional synchronization signal. In this way, the wiring space of the printed circuit board is released, thereby greatly facilitating the design of circuit wirings of the display device.

To make the aforementioned and other objectives, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

DETAILED DESCRIPTION

First, referring toFIG. 1,FIG. 1is a schematic diagram of an embodiment of a display device10provided in the present invention. The display device10includes a power supply circuit11, a timing controller12, a data driver13, a gate driver14, and a plurality of pixel units15. The power supply circuit11is used to provide a supply voltage value V1to the data driver13. The timing controller12is used to provide a plurality of different timing signals TS to the data driver13. The timing signals TS are, for example, a first clock signal (CLK) and a second clock signal (XCK) with mutually inverted timings. The data driver13is electrically coupled to the power supply circuit11, the timing controller12, the gate driver14, and the plurality of pixel units15. The data driver13is used to generate corresponding display data signals D1, D2, . . . , DNaccording to the supply voltage value V1, the plurality of timing signals, and a plurality of pieces of display data information DS received, and transmit the display data signals D1, D2, . . . , DNto the corresponding plurality of pixel units15. In addition, the data driver13is further used to generate a plurality of gate timing signals and transmit the gate timing signals to the gate driver14. The gate driver14is used to generate a plurality of gate driving signals according to the received plurality of gate timing signals GS, and transmit the plurality of gate driving signals to corresponding gate lines, so that the pixel units15electrically coupled to the gate lines determine, according to the gate driving signals, whether to receive and display one of the display data signals D1, D2, . . . , DN.

Next, referring toFIG. 2A,FIG. 2Ais a schematic diagram of an embodiment of a data driver13of the present invention. In this embodiment, the data driver13includes a boost circuit131, a gate clock generation circuit132, a data drive circuit133, a first level shift circuit134, and a second level shift circuit134b. The boost circuit131is used to receive the supply voltage value V1, and generate a plurality of preset voltage values Voutaccording to the supply voltage value V1. The preset voltage values Voutare, for example, a high voltage level and a low voltage level. The gate clock generation circuit132is electrically coupled to the boost circuit131, and the gate clock generation circuit132is used to receive the preset voltage values Voutand the timing signals TS, and generate a plurality of initial timing signals ICK with different timings according to the preset voltage values Voutand the timing signals TS, for example, a plurality of successive first timing signals ICK1, ICK2, . . . , ICKL, where L is a positive integer greater than zero. The data drive circuit133is used to receive the plurality of pieces of display data information DS and the timing signals TS, and generate the display data signals D1, D2, . . . , DNaccording to the display data information DS and the timing signals TS, where N is a positive integer greater than zero. The data drive circuit133transmits the display data signals D1, D2, . . . , DNto the corresponding plurality of pixel units15. The level shift circuit134ais electrically coupled to the boost circuit131and the gate clock generation circuit132. The level shift circuit134ais used to receive the preset voltage values Voutand the plurality of initial timing signals ICK, and perform level adjustment to generate a plurality of first gate drive timing signals, that is, the foregoing gate timing signals GS, for example, a plurality of gate clock signals CLK1, CLK2, . . . , CKLM, where M is a positive integer greater than zero. The level shift circuit134atransmits the plurality of first gate drive timing signals to the gate driver14, so that the gate driver14generates a corresponding plurality of gate driving signals according to the plurality of gate drive timing signals. The second level shift circuit134bis electrically coupled to the gate clock generation circuit132, and is used to receive the initial timing signals ICK, for example, a second timing signal having a timing different from that of the first timing signal, and generate a plurality of second gate drive timing signals according to the initial timing signals ICK. Therefore, in this embodiment, the gate driver14generates a corresponding plurality of gate driving signals according to the first gate drive timing signals and the second gate drive timing signals. For example, the first gate drive timing signals are used to generate gate driving signals of odd-numbered rows of gate lines, and the second gate drive timing signals are used to generate gate driving signals of even-numbered rows of gate lines, but the present invention is not limited thereto. In other embodiments, the level shift circuit134aand the level shift circuit134bmay be configured on opposite sides, that is, may be configured on the left and right sides of the data driver13.

Referring toFIG. 2B,FIG. 2Bis a schematic diagram of an embodiment of the level shift circuit134. The level shift circuit134may include a level shift sub-circuit1341and a buffer circuit1342. The level shift sub-circuit1341is used to adjust levels of received initial timing signals ICK according to requirements and output adjusted clock signals DCK obtained after the adjustment. After receiving the adjusted clock signals DCK, the buffer circuit1342buffers the plurality of adjusted clock signals DCK and then outputs the adjusted clock signals DCK as the gate timing signals GS. Therefore the output plurality of gate timing signals GS are non-overlapping with each other, that is, ON periods of the plurality of gate timing signals GS are non-overlapping. For example, periods in which the plurality of gate timing signals GS are at a logical high level are non-overlapping with each other.

Next, referring toFIG. 3andFIG. 4,FIG. 3is a schematic diagram of an embodiment of configuration of the display device10, andFIG. 4shows an embodiment of configuration of the data driver. The display device10includes a display area161for display and a bezel area162. The plurality of pixel units15is configured on a substrate163of the display device10and a user can watch a displayed image by using the display area161. The power supply circuit11, the timing controller12, the data driver13, and the gate driver14may be configured in the bezel area162. In this embodiment, the display device10may include two data drivers13and two gate drivers14, that is, a first data driver13a, a second data driver13b, a first gate driver14a, and a second gate driver14bas shown inFIG. 3. The first data driver13a, the second data driver13b, the first gate driver14a, and the second gate driver14bare configured on the substrate163, and the first data driver13aand the second data driver13bmay be individually configured on the left and right sides of the display device10, and respectively electrically coupled to the first gate driver14aand the second gate driver14b. In this embodiment, the first gate driver14amay be used to drive odd-numbered rows of gate lines, and the second gate driver14bmay be used to drive even-numbered rows of gate lines, but the present invention is not limited thereto. The user may configure gate lines that need to be driven by the first gate driver14aand the second gate driver14baccording to requirements. According to the foregoing content, because the level shift circuit134has been integrated into the data driver13, and the data driver13can be configured on the substrate163of the pixel unit15, the wiring distance between the level shift circuit134and the gate driver14is effectively reduced. In this way, not only the wiring space is saved, but also a short wiring distance can effectively alleviate signal attenuation or distortion. Moreover, in this embodiment, only the power supply circuit11and the timing controller12are configured on a printed circuit board17, and therefore the volume needed by the printed circuit board17is greatly reduced. The power supply circuit11and the timing controller12are electrically coupled to the first data driver13aand second data driver13bby the printed circuit board17. Because timing signals TS needed by the first data driver13aand the second data driver13bare both provided by the timing controller12, although the first data driver13aand the second data driver13bare used to drive different gate lines, no additional synchronization signal is needed to keep synchronization between them. The timing signals TS provided by the timing controller12enable the first data driver13aand the second data driver13bto correctly output a corresponding plurality of initial timing signals ICK according to the required timing, so that the first gate driver14aand the second gate driver14bcan correctly generate corresponding gate control signals to control the plurality of pixel units15to display. Therefore, the present invention can further release the wiring space of the printed circuit board17. Further, according to the foregoing other embodiments, as shown inFIG. 2A, each data driver13may further include two level shift circuits134. Therefore, the first data driver13anot only includes a boost circuit131a, a gate clock generation circuit132a, a data drive circuit133a, and a level shift circuit134a, but also further includes a level shift circuit134b, where the data drive circuit133ais used to output a plurality of display data signals D11, D12. . . D1N, and the boost circuit131ais used to output a first voltage value Vout1; the second data driver13bnot only includes a boost circuit131b, a gate clock generation circuit132b, a data drive circuit133b, and a level shift circuit134c, but also further includes a level shift circuit134d, where the data drive circuit133bis used to output a plurality of display data signals D21, D22. . . D2N, and the boost voltage131bis used to output a second voltage value Vout2, as shown inFIG. 4. Therefore, the user can determine, according to requirements, whether the data driver13synchronously uses two level shift circuits134. That is, in some embodiments, the first data driver13aand the second data driver13bcan drive all the pixel units15by using only one level shift circuit134, or a single data driver13drives all the pixel units15by using two level shift circuits134, for example, the level shift circuits134aand134b. In other embodiments, if the display device10has a large number of pixel units15, the first data driver13aand the second data driver13bneed to use all the level shift circuits134to drive the pixel units15. When two level shift circuits134of two data drivers13need to be used for the number of pixel units15, the level shift circuit134aand the level shift circuit134dcan be individually electrically coupled to the first gate driver14aand the second gate driver14bby directly using the substrate163because the level shift circuit134aand the level shift circuit134dare configured on the left side of the first data driver13aand on the right side of the second data driver13b. In addition, because no synchronization is required between the first data driver13aand the second data driver13band the wiring space on the printed circuit board17is released, and the level shift circuit134band the level shift circuit134care configured on the right side of the first data driver13aand on the left side of the second data driver13b, the level shift circuit134band the level shift circuit134ccan be electrically coupled to the gate driver14with a minimum wiring distance by using the wiring space released by the printed circuit board17, so that the driving capability of the first data driver13aand the second data driver13bcan be improved without increasing the area of the bezel area162.

In the embodiment of the display device10inFIG. 4, the display device10includes the first data driver13aand the second data driver13b, so that the display device10has a good pixel driving capability. An output end of the boost circuit131bof the second data driver13bmay be electrically coupled to an input end of the boost circuit131aof the first data driver13a, and an output end of the boost circuit131aof the first data driver13amay be electrically coupled to an input end of the boost circuit131bof the second data driver13b. Because the first data driver13aand the second data driver13bare used to drive different gate lines, and the gate lines are individually driven, only one boost circuit131is used to drive the gate lines at a time. When one of the boost circuit131band the boost circuit131aneeds to output the first voltage value Vout1or the second voltage value Vout2to drive the gate lines, to avoid the occurrence of under-voltages or severe voltage ripples occur in the boost circuit131due to an excessively large drawn current of the pixel units15when the gate lines are driven, taking the use of the boost circuit131ato drive the gate lines as an example, the boost circuit131bmay output the second voltage value Vout2as an input to the boost circuit131a. When the pixel units15are driven, the second voltage value Vout2output by the boost circuit131bnot only can increase the voltage driving capability of the first voltage value Vout1, but also can compensate for the first voltage value Vout1in time when the pixel units15are driven, so as to avoid the occurrence of under-voltages or severe voltage ripples. In addition, because two boost circuits, that is, the boost circuit131aand the boost circuit131b, are used to share the burden of outputting a voltage value, the occurrence of over-temperature in the case where a single data driver13is used to drive the pixel units15can be effectively avoided.

In conclusion, because the data driver13of the present invention further includes the boost circuit131, the gate clock generation circuit132, and the level shift circuit134in addition to the data drive circuit133, the volume of the printed circuit board17is effectively reduced. In addition, because the data driver13can be electrically coupled to the gate driver14without using wirings of the printed circuit board17, not only the wiring distance can be reduced, but also signal attenuation can be alleviated. Further, because a plurality of data drivers13receive timing signals generated by a same timing controller12, that is, the plurality of data drivers13can achieve an effect of clock synchronization by using the timing controller12, no additional synchronization signal needs to be electrically coupled between the plurality of data drivers13, so that the wiring space of the printed circuit board17can be released more effectively. Therefore, by means of the released wiring space and the plurality of level shift circuits134, the pixel driving capability of the display device is further improved. Moreover, because the boost circuit131aof the first data driver13ais electrically coupled to the boost circuit131bof the second data driver13b, the boost circuit131amay output the first voltage value Vout1as an input to the boost circuit131b, and the boost circuit131bmay output the second voltage value Vout2as an input to the boost circuit131a, the voltage value Voutoutput by one boost circuit131can be used to assist in stabilizing the preset voltage value Voutoutput by the other boost circuit131. When an element draws a voltage, the assisting preset voltage value Voutis used to compensate for the drawn preset voltage value Vout, so as to avoid the occurrence of under-voltages or severe voltage ripples in the boost circuit131of a single data driver13due to an excessively large drawn current. Furthermore, using more than one boost circuit131to share the burden of outputting a voltage value can further effectively avoid the occurrence of over-temperature in the case where a single data driver13is used.

The present invention is disclosed through the foregoing embodiments; however, these embodiments are not intended to limit the present invention. Various changes and modifications made by persons of ordinary skill in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. The protection scope of the present invention is subject to the appended claims.