Semiconductor package with its surface edge covered by resin

A semiconductor package includes a semiconductor chip; a resin part configured to cover a side surface of the semiconductor chip; and a wiring structure formed on a circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip, wherein the resin part is formed so as to cover a part of a surface of the semiconductor chip situated at an opposite side to the circuit forming surface of the semiconductor chip.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application is based upon and claims the benefit of priority of Japanese Patent Application No. 2009-201299 filed on Sep. 1, 2009, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor packages and manufacturing methods of the semiconductor packages. More specifically, the present invention relates to a semiconductor package including a semiconductor chip, a resin part configured to cover a part of the semiconductor chip, and a wiring structure configured to electrically connect to the semiconductor chip; and a manufacturing method of the semiconductor package.

2. Description of the Related Art

Conventionally, a semiconductor package including a semiconductor chip, a resin part configured to cover a part of the semiconductor chip, and a wiring structure configured to be electrically connected to a semiconductor chip has been known. An example of such a semiconductor package is discussed below.

FIG. 1is a cross-sectional view showing a related art semiconductor package. As shown inFIG. 1, a semiconductor package100includes a semiconductor chip200, a resin part300, and a wiring structure400.

The semiconductor chip200includes a chip main body210and electrode pads220. The chip main body210has a structure where a semiconductor integrated circuit (not shown inFIG. 1) and others are formed on a thin plate semiconductor substrate (not shown inFIG. 1) made of silicon. The electrode pads220are formed on the chip main body210. Surfaces220aof the electrode pads220are exposed from a surface of the chip main body210. The electrode pads220are electrically connected to the semiconductor integrated circuit (not shown inFIG. 1) of the chip main body210. A surface200aof the semiconductor chip200, which is a surface of the chip main body210where the electrode pads220are formed, is flat. In other words, the surfaces220aof the electrode pads220are substantially flush with the surface of the chip main body210.

The resin part300is provided so as to cover a surface200bwhich is a side surface of the semiconductor chip200. The resin part300is not provided on the surface200aof the semiconductor chip200and a surface200cwhich is an opposite surface of the surface200a. The surfaces200aand200cof the semiconductor chip200are completely exposed from (not covered by) the resin part300. In other words, the resin part300comes in contact with only the surface200bof the semiconductor chip200and does not come in contact with the surfaces200aand200cof the semiconductor chip200. A surface300aof the resin part300is substantially flush with the surface200aof the semiconductor chip200(the surfaces220aof the electrode pads220and the surface of the chip main body210). In addition, a surface300bof the resin part300is substantially flush with the surface200cof the semiconductor chip200. In the semiconductor chip200, the surface200amay be called a circuit forming surface; the surface200bmay be called a side surface; and the surface200cmay be called a rear surface.

The wiring structure400includes a first wiring layer410, a second wiring layer420, a third wiring layer430, a first insulation layer440, a second insulation layer450, a third insulation layer460, and a solder resist layer470.

The first insulation layer440is formed on the surface200aof the semiconductor chip200and the surface300aof the resin part300. The first wiring layer410is formed on the first insulation layer440. The first wiring layer410is electrically connected to the electrode pads220of the semiconductor chip200via first via-holes440xpiercing the first insulation layer440. The second insulation layer450is formed on the first insulation layer440so as to cover the first wiring layer410.

The second wiring layer420is formed on the second insulation layer450. The second wiring layer420is electrically connected to the first wiring layer410via second via holes450xpiercing the second insulation layer450. The third insulation layer460is formed on the second insulation layer450so as to cover the second wiring layer420. The third wiring layer430is formed on the third insulation layer460. The third wiring layer430is electrically connected to the second wiring layer420via third via holes460xpiercing the third insulation layer460.

The solder resist layer470is formed on the third insulation layer460so as to cover the third wiring layer430. The solder resist layer470has opening parts470xin which parts of the third wiring layer430are exposed. The third wiring layer430exposed in the opening parts470xof the solder resist layer470functions as electrode pads connected to a motherboard and others.

FIG. 2throughFIG. 6are views showing a manufacturing process of the related art semiconductor package. InFIG. 2throughFIG. 6, parts that are the same as the parts shown inFIG. 1are given the same reference numerals, and explanation thereof may be omitted. In each ofFIG. 2throughFIG. 5, (a) is a plan view and (b) is a cross-sectional view taken along a line A-A. The manufacturing process of the related art semiconductor package is discussed with reference toFIG. 2throughFIG. 6. InFIG. 2throughFIG. 5, illustration of the electrode pads220is omitted.

First, in a step shown inFIG. 2, a semiconductor wafer is cut into pieces so that plural semiconductor chips200are manufactured. Then, the plural semiconductor chips200are provided on a surface500aof a supporting body500so that the surfaces (circuit forming surface)200aface a surface500aof the supporting body500. Plural semiconductor chips200can be fixed to the surface500aof the supporting body500by, for example, an adhesive material (not shown inFIG. 2).

Next, in a step shown inFIG. 3, the resin part300is formed on the surface500aof the supporting body500by press molding or the like. The resin part300is configured to seal plural semiconductor chips200. More specifically, epoxy resin or the like which is a material of the resin part300is applied on the surface500aof the supporting body500so that plural semiconductor chips200are sealed. In addition, by heating and pressing the epoxy resin or the like, the epoxy resin is cured so that the resin part300is formed.

Next, in a step shown inFIG. 4, the supporting body500is removed. The supporting body500can be removed by using, for example, an etching technique. Furthermore, in a case where the supporting body is fixed to the semiconductor chip200and the resin part300by a heat peeling tape, the supporting body500can be removed by applying designated heat. As a result of this, the surfaces200aof the semiconductor chips200are exposed from the surface300aof the resin part300.

Next, in a step shown inFIG. 5, a part of the resin part300covering the surfaces200cof the semiconductor chips200is removed so that the surfaces200cof the semiconductor chips200are exposed from the surface300bof the resin part300. As a result of this, the resin part300comes in contact with only the surface (side surface)200bof the semiconductor chip200and therefore the surfaces200aand200care exposed from the resin part300. The reason why a part of the resin part300covering the surface200cof the semiconductor chip200is removed is to transfer the heat generated by the semiconductor chip200. If a part of the resin part300covering the surface200cof the semiconductor chip200is not removed, the temperature of the semiconductor chip200is increased so that operation of the semiconductor chip200may be obstructed.

Next, in a step shown inFIG. 6, by a known method, the first insulation layer440, the first wiring layer410, the second insulation layer450, the second wiring layer420, the third insulation layer460, the third wiring layer430, and the solder resist layer470having the opening parts470xare formed, in this order, on the surface200aof the semiconductor chip200and the surface300aof the resin part300. After the step shown inFIG. 6, by cutting the structural body shown inFIG. 6in cutting positions C, the semiconductor package100shown inFIG. 1is completed. See International Publication Official Gazette No. 02/33751 and International Publication Official Gazette No. 02/15266.

However, in the manufacturing method of the related art semiconductor package, as shown inFIG. 5, in order to transfer heat generated by the semiconductor chip200, the surface (rear surface)200cof the semiconductor chip200is exposed from the resin part300. As a result of this, the semiconductor chip200is fixed to the resin part300by only the surface (side surface)200b. Therefore, it is not possible to secure a sufficient area of the contact part between the semiconductor chip200and the resin part300. As a result of this, the semiconductor chip200may fall down (separate) from the resin part300and the strength of the semiconductor package100may not be sufficient.

SUMMARY OF THE INVENTION

Accordingly, embodiments of the present invention may provide a novel and useful semiconductor package and manufacturing method of the semiconductor package solving one or more of the problems discussed above.

More specifically, the embodiments of the present invention may provide a semiconductor package whereby it is possible to prevent a semiconductor chip from falling down from a resin part so that strength of the semiconductor package can be improved, and also provide a manufacturing method of the semiconductor package.

Another aspect of the embodiments of the present invention may be to provide a semiconductor package, including:

a semiconductor chip;

a resin part configured to cover a side surface of the semiconductor chip; and

a wiring structure formed on a circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip,

wherein the resin part is formed so as to cover a part of a surface of the semiconductor chip situated at an opposite side to the circuit forming surface of the semiconductor chip.

Another aspect of the embodiments of the present invention may be to provide a manufacturing method of a semiconductor package, including:

a step of forming a metal layer on an opposite surface with respect to a circuit forming surface of a semiconductor chip so that a part of the opposite surface is exposed;

a step of mounting the semiconductor chip where the metal layer is formed on a supporting body;

a step of forming a resin part so as to cover a side surface of the semiconductor chip and the part of the opposite surface of the semiconductor chip, the part being exposed with respect to the metal layer;

a step of removing the metal layer;

a step of removing the supporting body; and

a step of forming a wiring structure on the circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description is given below, with reference to theFIG. 7throughFIG. 31of embodiments of the present invention. In the plan views and bottom views which will be referred to, for the purpose of making relationship with cross sectional views clear, the same hatching as that applied to the cross-sectional views may be applied to the plan views and the bottom views.

First Embodiment

Structure of Semiconductor Package of the First Embodiment

FIG. 7is a view showing a semiconductor package10of a first embodiment of the present invention. InFIG. 7, (a) is a cross-sectional view and (b) is a bottom view. As shown inFIG. 7, the semiconductor package10includes a semiconductor chip20, a resin part30, and a wiring structure40.

The semiconductor chip20includes a semiconductor substrate21, a semiconductor integrated circuit22, plural electrode pads23, and a protection film24. The semiconductor chip20may have a size (in planar view) of, for example, approximately 5 mm×approximately 10 mm. The semiconductor chip20may have a thickness T1equal to or greater than approximately 100 μm and equal to or smaller than approximately 800 μm, for example, approximately 800 μm. In the following explanation, in the semiconductor chip20, a surface at a side where the electrode pads23are formed may be called a circuit forming surface.

The semiconductor substrate21may be, for example, a Si substrate. The semiconductor integrated circuit22includes a diffusion layer, an insulation layer, vias, a wiring, and others (not shown inFIG. 7). The electrode pads23are provided on and electrically connected to the semiconductor integrated circuit22. As a material of the electrode pad23, for example, Al or the like may be used. The electrode pad23may be where an Al layer is formed on a Cu layer or where the Al layer is formed on an Si layer being formed on the Cu layer.

The protection film24is provided on the semiconductor integrated circuit22. The protection film24is configured to protect the semiconductor integrated circuit22. The protection film24may be called a passivation film. As the protection film24, for example, a SiN film, a PSG film, or the like can be used. A layer made of polyimide or the like may be further stacked on a layer made of the SiN film, the PSG film, or the like. A surface24aof the protection film24is substantially flush with surfaces23aof the electrode pads23.

The resin part30is formed so as to cover a surface (side surface)20cof the semiconductor chip20and cover an external edge part of the surface (rear surface)20bin a frame manner. In the semiconductor chip20, the surface (rear surface)20bis a surface situated at a side opposite to the circuit forming surface. A surface30aof the resin part30is substantially flush with the surfaces23aof the electrode pads23and the surface24aof the protection film24of the semiconductor chip20. A thickness T2of a portion of the resin part30which covers the external edge part of the surface (rear surface)20bin the frame manner may be equal to or greater than approximately 50 μm and equal to or smaller than approximately 150 μm, for example, approximately 100 μm. A width W1of the portion of the resin part30which covers the external edge part of the surface (rear surface)20bin the frame manner may be equal to or greater than approximately 50 μm and equal to or smaller than approximately 150 μm, for example, approximately 50 μm. It is not necessary for this entire frame-shaped portion to have the same fixed width. In addition, the width W3of the resin part may be equal to or greater than approximately 2 mm and equal to or smaller than approximately 5 mm, for example, approximately 2.5 mm.

The wiring structure40includes a first wiring layer41, a second wiring layer42, a third wiring layer43, a first insulation layer44, a second insulation layer45, a third insulation layer46, and a solder resist layer47.

The wiring structure40is formed on the circuit forming surface of the semiconductor chip20and the surface30aof the resin part30being situated at the same side as the circuit forming surface in a state where the semiconductor chip20and the resin part30configured to cover the surface (side surface)20cof the semiconductor chip20are a base body. A thickness T3of the wiring structure40may be, for example, equal to or greater than approximately 50 μm and equal to or smaller than approximately 100 μm, for example, approximately 50 μm. In other words, the thickness T3of the wiring structure40(equal to or greater than approximately 50 μm and equal to or smaller than approximately 100 μm) is extremely less than the thickness T1of the semiconductor chip20(equal to or greater than approximately 100 μm and equal to or smaller than approximately 800 μm).

The first insulation layer44is formed on the surfaces23aof the electrode pads23and the surface24aof the protection film24of the semiconductor chip20and the surface30aof the resin part30. The first wiring layer41is formed on the first insulation layer44. The first wiring layer41is electrically connected to the electrode pads23of the semiconductor chip20via first via holes44xpiercing the first insulation layer44. The second insulation layer45is formed on the first insulation layer44so as to cover the first wiring layer41.

The second wiring layer42is formed on the second insulation layer45. The second wiring layer42is electrically connected to the first wiring layer41via second via holes45xpiercing the second insulation layer45. The third insulation layer46is formed on the second insulation layer45so as to cover the second wiring layer42. The third wiring layer43is formed on the third insulation layer46. The third wiring layer43is electrically connected to the second wiring layer42via third via holes46xpiercing the third insulation layer46.

The solder resist layer47is provided on the third insulation layer46so as to cover the third wiring layer43. The solder resist layer47has opening parts47x. Parts of the third wiring layer43are exposed in the opening parts47x. The third wiring layer43exposed in the opening parts47xof the solder resist layer47functions as electrode pads configured to be connected to a motherboard or the like.

A metal layer may be formed on the third wiring layer43exposed in the opening parts47xof the solder resist layer47. As an example of the metal layer, an Au layer, a Ni/Au layer where a Ni layer and the Au layer are stacked in this order, a Ni/Pd/Au layer where the Ni layer, a Pd layer, and the Au layer are stacked in this order, or the like may be applied. In addition, instead of providing the metal layer, an OSP (Organic Solderability Preservative) process may be applied onto the third wiring layer43exposed in the opening parts47xof the solder resist layer47.

Thus, in the semiconductor package10, the wiring structure40is formed on the circuit forming surface of the semiconductor chip20and the surface30aof the resin part30being situated at the same side as the circuit forming surface in a state where the semiconductor chip20and the resin part30configured to cover the surface (side surface)20cof the semiconductor chip20are a base body. The resin part30is further formed so as to cover the external edge part of the surface (rear surface)20bof the semiconductor chip20in a frame manner. Because of this, a part of the surface (rear surface)20bof the semiconductor chip20is covered with the resin part30. Another part of the surface (rear surface)20bof the semiconductor chip20is exposed from the resin part30. As a result of this, it is possible to prevent the semiconductor chip20from falling down from the resin part30without obstructing transfer of the heat generated by the semiconductor chip20. In addition, it is possible to improve the strength of the semiconductor package10.

[Manufacturing Method of Semiconductor Package of the First Embodiment]

Next, a manufacturing method of a semiconductor package of the first embodiment of the present invention is discussed.FIG. 8throughFIG. 23are views showing a manufacturing process of the semiconductor package of the first embodiment. InFIG. 8throughFIG. 23, parts that are the same as the parts shown inFIG. 7are given the same reference numerals, and explanation thereof is omitted. In each ofFIG. 8throughFIG. 14,FIG. 16, andFIG. 17, (a) is a plan view; and (b) is a cross-sectional view taken along a line D-D in (a).

First, in a step shown inFIG. 8, a semiconductor wafer11having plural of the semiconductor chips20is provided. In the semiconductor wafer11, a scribe region B is where the semiconductor chips20are to be separated from each other. A cutting position C is where the semiconductor wafer11is to be cut by a dicing blade or the like. A diameter φ1of the semiconductor wafer11may be, for example, approximately 200 mm. The semiconductor wafer11may have a thickness T1equal to or greater than approximately 100 μm and equal to or smaller than approximately 800 μm, for example, approximately 800 μm. Details of the semiconductor chip20are as discussed above.

Next, in a step shown inFIG. 9, a seed layer12is formed on the surface (rear surface)11bof the semiconductor wafer11by, for example, a sputtering method or the like. The seed layer12functions as a power feeding layer when a metal layer14is formed in a step shown inFIG. 14. As a material of the seed layer12, for example, copper (Cu), nickel (Ni), or the like can be used. The thickness T4of the seed layer12can be, for example, several μm.FIG. 9throughFIG. 17are shown by reversingFIG. 8in an up-side-down manner.

Next, in a step shown inFIG. 10, a resist layer13having an opening part13xis formed on a surface12aof the seed layer12. More specifically, resist liquid is applied to the seed layer12and the applied resist liquid is exposed and developed, so that the opening part13xis formed. The resist layer13having the opening part13xmay be formed of a laminate of sheet-like resist materials (dry film resist). A photosensitive resin composition including, for example, an epoxy group resin, imide group resin, or the like can be used as a material of the resist layer13. The resist layer13may have a thickness T5equal to or greater than approximately 50 μm and equal to or smaller than approximately 150 μm, for example, approximately 100 μm. In the first embodiment, in each of the semiconductor chips20, the resist layer13is formed on the surface12aof the seed layer12in a frame manner so as to cover only a part overlapping, in a bottom view, an external edge part of the surface (rear surface)20bof the semiconductor chip20. The scribe area B separating the semiconductor chips from each other is also covered with the resist layer13. The width W2of a frame shape part of the resist layer13can be equal to or greater than approximately 50 μm and equal to or smaller than approximately 150 μm, for example, approximately 50 μm. It is not necessary for the entire frame shape part of the resist layer13to have the same fixed width.

Next, in a step shown inFIG. 11, by an electrolytic plating method where the seed layer is used as the power feeding layer, the metal layer14is formed on the surface12aof the seed layer12exposed in the opening part13xof the resist layer13. As a material of the metal layer14, for example, copper (Cu) or the like can be used. The thickness T6of the metal layer14can be substantially equal to the thickness T5of the resist layer13, for example, approximately 50 μm through approximately 100 μm.

Next, in a step shown inFIG. 12, the resist layer13shown inFIG. 11is removed and a part of the seed layer12not covered with the metal layer14is removed. The resist layer13can be removed by etching using an alkaline solution such as sodium hydroxide (NaOH). The seed layer12not covered with the metal layer14can be removed by etching using, for example, a ferric chloride solution or the like.

Next, in a step shown inFIG. 13, the semiconductor wafer11shown inFIG. 12is cut in the cutting positions C by the dicing blade or the like so that the semiconductor chips20are formed. Then, each of the semiconductor chips20where the seed layer12and the metal layer14are stacked on the surface (rear surface)20bis provided on a surface16aof a supporting body16via an adhesive member15so that the circuit forming surface of the semiconductor chip20faces a surface15aof the adhesive member15, and then is pressed. As a result of this, each of the semiconductor chips20is fixed on the surface16aof the supporting body16via the adhesive member15in a face-down state. A gap between neighboring semiconductor chips20may be optional. As a material of the adhesive member15, for example, a polyimide group resin or the like can be used. The adhesive member15may have thickness T7of, for example, approximately 25 μm. As a material of the supporting body16, for example, copper (Cu) or the like can be used. The supporting body16may have thickness T8of, for example, approximately 200 μm. InFIG. 13,FIG. 14, andFIG. 16throughFIG. 23, a one-dotted line E indicates a position where a structural body shown inFIG. 23is cut after the step shown inFIG. 23.

Next, in a step shown inFIG. 14, the resin part30is formed on the surface15aof the adhesive member15by a press-mold method or the like. The resin part30is configured to seal the seed layer12, the metal layer14, and the semiconductor chip20. More specifically, as shown inFIG. 15, the structural body shown inFIG. 13is mounted on a lower mold18, and then the epoxy group resin or the like which is a material of the resin part30is applied on the surface15aof the adhesive member15so as to seal the seed layer12, the metal layer14, and the semiconductor chip20. After that, the epoxy group resin or the like which is a material of the resin part30is heated and pressed from a side opposite to the lower mold18by an upper mold19. As a result of this, the epoxy group resin or the like is made uniform and cured so that the resin part30is formed. The heating process may be performed at the heating temperature of, for example, approximately 150° C. and for approximately five minutes. The thickness T9from the surface15aof the adhesive member15to a surface30bof the resin part30can be, for example, equal to or greater than approximately 900 μm.

Next, in a step shown inFIG. 16, the surface30bof the resin part30is ground until the surface14aof the metal layer14is exposed. For example, a grinder or the like can be used for grinding the resin part30. The thickness T10from the surface15aof the adhesive member15to the surface30bof the resin part30can be, for example, approximately 900 μm.

Next, in a step shown inFIG. 17, the seed layer12, the metal layer14, the adhesive member15, and the supporting body16shown inFIG. 16are removed. The seed layer12, the metal layer14, and the supporting body16can be removed by etching using, for example, ferric chloride solution or the like. The adhesive member15can be mechanically peeled off after the seed layer12, the metal layer14, and the supporting body16are removed by etching. As a result of this, the resin part30is formed so as to cover the surface (side surface)20cof the semiconductor chip20and also cover, in a frame manner, the external edge part of the surface (rear surface)20b. As a result of this, it is possible to prevent the semiconductor chip20from falling down from the resin part. In addition, strength of the semiconductor package10can be improved when the semiconductor package10is eventually completed. The thickness T2of a portion of the resin part30which covers the external edge part of the surface (rear surface)20bin the frame manner may be equal to or greater than approximately 50 μm and equal to or smaller than approximately 150 μm, for example, approximately 100 μm. The width W1of the portion of the resin part30which covers the external edge part of the surface (rear surface)20bin the frame manner may be equal to or greater than approximately 50 μm and equal to or smaller than approximately 150 μm, for example, approximately 50 μm. It is not necessary for this entire frame-shaped portion to have the same fixed width.

Next, in a step shown inFIG. 18, the first insulation layer44is formed on the surfaces23aof the electrode pads23, the surface24aof the protection film24, and the surface30aof the resin part30. As a material of the first insulation layer44, resin such as epoxy group resin or polyimide group resin can be used. The first insulation layer44can be formed by, for example, laminating a resin film on the surfaces23aof the electrode pads23, the surface24aof the protection film24, and the surface30aof the resin part30, then pressing the resin film, and then applying heat at approximately 190° C. so that the resin film is cured.FIG. 18throughFIG. 23are shown by reversingFIG. 17in an up-side-down manner.

Next, in a step shown inFIG. 19, the first via holes44xpiercing the first insulation layer44are formed in the first insulation layer44by a laser process method or the like so that the electrode pads23are exposed. The first via holes44xmay be formed by patterning with a photolithography technique where the photosensitive resin is used as the first insulation layer44. Alternatively, the first via holes44xmay be formed by patterning a resin film having an opening part formed by a screen printing method.

Next, in a step shown inFIG. 20, the first wiring layer41is formed on the first insulation layer44. The first wiring layer41is electrically connected to the electrode pads23exposed in the first via holes44x. As a material of the first wiring layer41, for example, copper (Cu) or the like can be used. The first wiring layer41is formed by, for example, a semi-additive process. The first wiring layer41includes via conductors in the first via holes44xand a wiring pattern on the first insulation layer44.

Details of forming the first wiring layer41by the semi-additive process are as follows. First, a Cu seed layer (not illustrated) is formed on internal walls of the first via holes44xand the first insulation layer44by an electroless plating method or a sputtering method. After that, a resist layer (not illustrated) having an opening part corresponding to the first wiring layer41is formed on this Cu seed layer (not illustrated). Next, a Cu pattern (not illustrated) is formed in the opening part of the resist layer by an electrolytic plating method where the Cu seed layer is used as a power feeding layer.

Next, after the resist layer is removed, the first wiring layer41is formed by etching the Cu seed layer where the Cu layer pattern is used as a mask. As a forming method of the first wiring layer41, various kinds of wiring forming methods such as a subtractive process, in addition to the above-mentioned semi-additive process, can be used.

Next, in a step shown inFIG. 21, by repeating the substantially same processes, the first wiring layer41through the third wiring layer43and the first insulation layer44through the third insulation layer46are stacked. In other words, after the second insulation layer45covering the first wiring layer41is formed, the second via holes45xare formed in the second insulation layer45on the first wiring layer41.

The second wiring layer42is formed on the second insulation layer45. The second wiring layer42is connected to the first wiring layer41via the second via holes45x. As a material of the second wiring layer42, for example, copper (Cu) or the like can be used. The second wiring layer42is formed by, for example, a semi-additive process.

In addition, after the third insulation layer46covering the second wiring layer42is formed, the third via holes46xare formed in the third insulation layer46on the second wiring layer42. Furthermore, the third wiring layer43connected to the second wiring layer42via the third via holes46xis formed on the third insulation layer46. As a material of the third wiring layer43, for example, copper (Cu) or the like can be used. The third wiring layer43is formed by, for example, a semi-additive process.

Thus, a built-up wiring layer is formed on the surfaces23aof the electrode pads23, the surface24aof the protection film24, and the surface30aof the resin part30. Although the built-up wiring layer is formed by three layers (the first wiring layer41through the third wiring layer43) in this embodiment, a built-up wiring layer of n (n is an integer equal to or greater than 1) layers may be formed.

Next, in a step shown inFIG. 22, solder resist is applied on the third insulation layer46so as to cover the third wiring layer43so that the solder resist layer47is formed. As a material of the solder resist layer47, for example, a photosensitive resin composition including, for example, an epoxy group resin, imide group resin, or the like can be used.

Next, in a step shown inFIG. 23, the solder resist layer47is exposed and developed so that the opening parts47xare formed. As a result of this, a part of the third wiring layer43is exposed in the opening parts47xof the solder resist layer47. The third wiring layer43exposed in the opening parts47xof the solder resist layer47functions as electrode pads connected to a motherboard and others.

A metal layer may be formed on the third wiring layer43exposed in the opening parts47xof the solder resist layer47. As an example of the metal layer, an Au layer, a Ni/Au layer where a Ni layer and the Au layer are stacked in this order, a Ni/Pd/Au layer where the Ni layer, a Pd layer, and the Au layer are stacked in this order, or the like may be applied. In addition, instead of providing the metal layer, an OSP (Organic Solderability Preservative) process may be applied onto the third wiring layer43exposed in the opening parts47xof the solder resist layer47.

After the step shown inFIG. 23, the structural body shown inFIG. 23is cut in the positions indicated by one-dotted lines E so that the semiconductor package10shown inFIG. 7is completed.

According to the first embodiment, in the semiconductor package, the wiring structure is formed on the circuit forming surface of the semiconductor chip and the surface of the resin part being situated at the same side as the circuit forming surface in a state where the semiconductor chip and the resin part configured to cover the surface (side surface) of the semiconductor chip are a base body. The resin part is further formed so as to cover the external edge part of the rear surface of the semiconductor chip in a frame manner. Because of this, a part of the rear surface of the semiconductor chip is covered with the resin part. Another part of the rear surface of the semiconductor chip is exposed from the resin part. As a result of this, it is possible to prevent the semiconductor chip from falling down from the resin part without obstructing transfer of the heat generated by the semiconductor chip. In addition, it is possible to improve the strength of the semiconductor package.

Modified Example of the First Embodiment

In the semiconductor package10of the first embodiment, the resin part configured to cover the side surface20cof the semiconductor chip20is further formed so as to cover the external edge part of the rear surface20bof the semiconductor chip20in a frame manner. However, it is not always necessary to form the resin part30on the rear surface20bof the semiconductor chip20in a frame manner. In a modified example of the first embodiment, the resin part30is formed on the rear surface20bof the semiconductor chip20in a different manner (having a configuration other than a frame shape).

FIG. 24is a bottom view showing an example of configurations of the resin part formed on the rear surface of the semiconductor chip. InFIG. 24, (a) shows, in an expanded manner, one of the semiconductor chips20shown in (a) ofFIG. 17. In other words, (a) inFIG. 17shows the example of the first embodiment where the resin part30is formed on the rear surface20bof the semiconductor chip20in a frame manner. InFIG. 24, (b) and (c) show modified examples of the first embodiment where the resin part30is formed on the rear surface20bof the semiconductor chip20in different manners (having a configuration other than a frame shape). The resin part30formed on the rear surface20bof the semiconductor chip20may have a configuration shown in (b) or (c) ofFIG. 24instead of the configuration (frame shape) shown in (a) ofFIG. 24.

In the example shown in (b) ofFIG. 24, the resin part30is formed so as to cover four corners of the rear surface20bof the semiconductor chip20. In the example shown in (b) ofFIG. 24compared to the example shown in (a) ofFIG. 24, an exposed area of the rear surface20bof the semiconductor chip20is larger and therefore it is advantageous for radiation of heat generated by the semiconductor chip20. In addition, it is possible to easily attach a component such as a heat spreader to the rear surface20bof the semiconductor chip20for the purpose of the radiation of heat generated by the semiconductor chip20. On the other hand, the example shown in (a) ofFIG. 24has more advantages than the example shown in (b) ofFIG. 24regarding improvement of the strength of the semiconductor package10.

In the example shown in (c) ofFIG. 24, the resin part30is formed on the rear surface20bof the semiconductor chip20in a diagonal manner. In the example shown in (c) ofFIG. 24compared to the example shown in (a) ofFIG. 24, an exposed area of the rear surface20bof the semiconductor chip20is larger and therefore it is advantageous for radiation of heat generated by the semiconductor chip20. In addition, it is also advantageous to improve the strength of the semiconductor package10. On the other hand, the example shown in (a) ofFIG. 24has more advantages than the example shown in (c) ofFIG. 24in that it is possible to easily attach a component such as a heat spreader to the rear surface20bof the semiconductor chip20for the purpose of the radiation of heat generated by the semiconductor chip20in the example shown in (a) ofFIG. 24.

According to the modified examples of the first embodiment, it is possible to achieve the effect same as that achieved by the first embodiment and also achieve the following effect. That is, it is possible to achieve heat radiation or easy mounting of the component by properly selecting the configuration of the resin part formed in the rear surface of the semiconductor chip.

The configurations of the resin part shown inFIG. 24are just examples. The configuration of the resin part formed in the rear surface of the semiconductor chip is not limited to the configurations shown inFIG. 24. The configuration of the resin part formed in the rear surface of the semiconductor chip may be a configuration where a part of the rear surface of the semiconductor chip is covered and another part of the rear surface of the semiconductor chip is exposed.

Second Embodiment

In the second embodiment, the semiconductor chip where a bump or a post is formed on an electrode pad is formed and the semiconductor chip is mounted on a supporting body in a face-up manner (where the bump faces upward). In the second embodiment, explanation of portions that are the same as portions discussed in the first embodiment is omitted and portions that are different from the portions discussed in the first embodiment are mainly discussed. The reason why the semiconductor chip is mounted on a supporting body in a face-up manner (where the bump faces upward) is as follows. If the semiconductor chip where the bump is formed on the electrode pad is mounted on a supporting body in a face-down manner (where the bump faces downward), the resin flows in a gap between the bump and the supporting body so that the resin may cover the bump surface.

[Structure of the Semiconductor Package of the Second Embodiment]

FIG. 25is a view showing the semiconductor package of the second embodiment of the present invention. More specifically, (a) inFIG. 25) is a cross-sectional view and (b) inFIG. 25is a bottom view. As shown inFIG. 25, a semiconductor package10A is different from the semiconductor package shown inFIG. 7in that the semiconductor chip20and the resin part30are replaced with a semiconductor chip20A and a resin part30A. In the following explanation, explanation of portions of the semiconductor package10A that are the same as portions of the semiconductor package10is omitted and portions of the semiconductor package10A that are different from the portions of the semiconductor package10are mainly discussed.

The semiconductor chip20A has the same structure as that of the semiconductor chip20except that the bumps25are formed on the surfaces23aof the electrode pads23of the semiconductor chip20A. As the bump25, for example, a gold (Au) bump, a solder bump, a copper (Cu) bump, or the like can be used. The bump25may be formed in a pillar shape. A thickness T11of the bump25can be equal to or greater than approximately 20 μm and equal to or less than approximately 50 μm, for example, approximately 30 μm. In the following explanation, a surface of the semiconductor chip20A where the electrode pads23and the bumps25are formed may be called a circuit forming surface.

The resin part30A is formed so as to cover a surface (side surface)20eof the semiconductor chip20A and cover an external edge part of the surface (rear surface)20din a frame manner. The resin part30A is formed so as to cover the surface24aof the protection film24of the semiconductor chip20A. In the semiconductor chip20A, the surface (rear surface)20dis a surface situated at a side opposite to the circuit forming surface. The surface30cof the resin part30A is substantially flush with surfaces (upper end surfaces)25aof the bumps25of the semiconductor chip20A. A thickness T2of a portion of the resin part30A which covers the external edge part of the surface (rear surface)20dof the semiconductor chip20A in the frame manner may be equal to or greater than approximately 50 μm and equal to or smaller than approximately 150 μm, for example, approximately 100 μm. A width W1of a portion of the resin part30A which covers the external edge part of the surface (rear surface)20dof the semiconductor chip20A in the frame manner may be equal to or greater than approximately 50 μm and equal to or smaller than approximately 150 μm, for example, approximately 50 μm. It is not necessary for this entire frame-shaped portion to have the same constant width.

A thickness of a portion of the resin part30A covering the surface24aof the protection film24is substantially equal to the thickness T11of the bumps25and is relatively thin (for example, approximately 30 μm). Accordingly, it is not sufficient by only this part to achieve the strength of the semiconductor package10A. On the other hand, the part of the resin part30A covering the external edge part of the surface (rear surface)20dof the semiconductor chip20A in the frame manner is relatively thick (for example, approximately 100 μm). Accordingly, it is possible, by this part, to achieve the strength of the semiconductor package10A.

In the wiring structure40, the first insulation layer44is formed on the surfaces25aof the bumps25and the surface30cof the resin part30A of the semiconductor chip20A. The first wiring layer41is formed on the first insulation layer44. The first wiring layer41is electrically connected to the bumps25of the semiconductor chip20A via the first via holes44xpiercing the first insulation layer44. A thickness T3of the wiring structure40may be, for example, equal to or greater than approximately 50 μm and equal to or smaller than approximately 100 μm, for example, approximately 50 μm. In other words, the thickness T3of the wiring structure40(equal to or greater than approximately 50 μm and equal to or smaller than approximately 100 μm) is extremely less than the thickness T1of the semiconductor chip20(equal to or greater than approximately 100 μm and equal to or smaller than approximately 800 μm).

Thus, in the semiconductor package10A, the wiring structure40is formed on the circuit forming surface of the semiconductor chip20A and the surface30cof the resin part30A being situated at the same side as the circuit forming surface in a state where the semiconductor chip20A and the resin part30A configured to cover the surface (side surface)20eof the semiconductor chip20A are a base body. The resin part30A is further formed so as to cover the external edge part of the surface (rear surface)20dof the semiconductor chip20A in a frame manner. Because of this, a part of the surface (rear surface)20dof the semiconductor chip20A is covered with the resin part30A. Another part of the surface (rear surface)20dof the semiconductor chip20A is exposed from the resin part30A. As a result of this, it is possible to prevent the semiconductor chip20A from falling down from the resin part30A without obstructing the transfer of the heat generated by the semiconductor chip20A. In addition, it is possible to improve the strength of the semiconductor package10A.

[Manufacturing Method of Semiconductor Package of the Second Embodiment]

Next, a manufacturing method of a semiconductor package of the second embodiment of the present invention is discussed.FIG. 26throughFIG. 30are views showing a manufacturing process of the semiconductor package of the second embodiment. InFIG. 26throughFIG. 30, parts that are the same as the parts shown inFIG. 25are given the same reference numerals, and explanation thereof is omitted.

First, in a step shown inFIG. 26, a semiconductor wafer11A having plural semiconductor chips20A is provided. In the semiconductor wafer11A, scribe regions B are where the semiconductor chips20A are to be separated from each other. Cutting positions C are where the semiconductor wafer11A is to be cut by a dicing blade or the like. A diameter φ1of the semiconductor wafer11A may be, for example, approximately 200 mm. The semiconductor wafer11A may have a thickness T1equal to or greater than approximately 100 μm and equal to or smaller than approximately 800 μm, for example, approximately 800 μm.

The semiconductor chip20A has the same structure as that of the semiconductor chip20except that the bumps25are formed on the surfaces23aof the electrode pads23of the semiconductor chip20A. As the bump25, for example, a gold (Au) bump, a solder bump, a copper (Cu) bump, or the like can be used. The bump25may be formed in a pillar shape. A thickness T11of the bump25can be equal to or greater than approximately 20 μm and equal to or less than approximately 50 μm, for example, approximately 30 μm.

Next, in a step shown inFIG. 27, by the processes shown inFIG. 9throughFIG. 12of the first embodiment, the seed layer12and the metal layer14are stacked on the rear surface20dof the semiconductor chip20A. In addition, the semiconductor wafer11A is cut in the cutting positions C by the dicing blade or the like so that the semiconductor chips20A are formed. Then, each of the semiconductor chips20A where the seed layer12and the metal layer14are stacked on the surface (rear surface)20dis provided on the surface16aof the supporting body16via the adhesive member15so that the surface14aof the metal layer14faces the surface15aof the adhesive15, and then is pressed. As a result of this, each of the semiconductor chips20is fixed on the surface16aof the supporting body16via the adhesive member15in a face-up state. A gap size between neighboring semiconductor chips20A may be optional.

Next, in a step shown inFIG. 28, the resin part30A is formed on the surface15aof the adhesive member15by a press-mold method or the like. The resin part30A is configured to seal the seed layer12, the metal layer14, and the semiconductor chip20A. Details of forming the resin part30A are already discussed with reference toFIG. 15. The thickness T12from the surface15aof the adhesive member15to the surface30cof the resin part30A can be, for example, equal to or greater than approximately 950 μm.

Next, in a step shown inFIG. 29, the surface30cof the resin part30A shown inFIG. 28is ground until the surfaces (upper end surfaces)25aof the bumps25are exposed. For example, a grinder or the like can be used for grinding the resin part30A. The thickness T13from the surface15aof the adhesive member15to the surface30cof the resin part30A can be, for example, approximately 930 μm.

Next, in a step shown inFIG. 30, the seed layer12, the metal layer14, the adhesive member15, and the supporting body16shown inFIG. 29are removed. The seed layer12, the metal layer14, and the supporting body16can be removed by etching using, for example, a ferric chloride solution or the like. As a result of this, the resin part30A is formed so as to cover the surface (side surface)20eof the semiconductor chip20A and also cover, in a frame manner, the external edge part of the surface (rear surface)20d. As a result of this, it is possible to prevent the semiconductor chip20A from falling down from the resin part30A. In addition, strength of the semiconductor package10A can be improved when the semiconductor package10A is eventually completed. The thickness T2of a portion of the resin part30A which covers the external edge part of the surface (rear surface)20din the frame manner may be equal to or greater than approximately 50 μm and equal to or smaller than approximately 150 μm, for example, approximately 100 μm. The width W1of the portion of the resin part30which covers the external edge part of the surface (rear surface)20din the frame manner may be equal to or greater than approximately 50 μm and equal to or smaller than approximately 150 μm, for example, approximately 50 μm. It is not necessary for this entire frame-shaped portion to have the same fixed width.

Next, a structural body manufactured by the substantially same processes as the processes shown inFIG. 18throughFIG. 23of the first embodiment is cut so that the semiconductor package10A shown inFIG. 25is completed.

Thus, in the second embodiment, the step where the semiconductor chip having the bumps is formed and provided on the supporting body in the face-up manner (where the bumps face upward) is provided. Therefore, in the semiconductor package, the wiring structure is formed on the circuit forming surface of the semiconductor chip and the surface of the resin part being situated at the same side as the circuit forming surface in a state where the semiconductor chip and the resin part configured to cover the surface (side surface) of the semiconductor chip are a base body. The resin part is further formed so as to cover the external edge part of the rear surface of the semiconductor chip in a frame manner. Therefore, it is possible to achieve the same effect as that of the first embodiment.

The configuration of the resin part30A formed on the surface20dof the semiconductor chip20A may be the same as that of the modified example of the first embodiment. In this case, it is possible to achieve the same effect as that of the modified example of the first embodiment.

Modified Example of the Second Embodiment

In the modified example of the second embodiment, instead of the press molding method, a transfer molding method is used for molding the resin part30A.

In the transfer molding method, as shown inFIG. 31, the structural body shown inFIG. 27is sandwiched by a lower mold18and an upper mold19. As a result of this, the surfaces25aof the bumps25are adhered to the surface19aof the upper mold19. In addition, an epoxy group resin or the like which is a material of the resin part30A is heated and flows in the periphery part of the structural body shown inFIG. 27. After being pressed, the epoxy group resin or the like is cured. The heating process may be performed at the heating temperature of, for example, approximately 150° C. and for approximately five minutes. Since the surfaces (upper end surfaces)25aof the bumps25are adhered to the surface19aof the upper mold19, the resin part30A is not formed on the surfaces25aof the bumps25. Therefore, the surfaces25aof the bumps25are exposed from the resin part30A. As a result of this, the grinding process shown inFIG. 29is not necessary.

According to the modified example of the second embodiment, it is possible to achieve not only the substantially same effect as that achieved by the second embodiment but also the following effect. That is, since the resin part is not formed on the upper surface of the bumps when the resin part is formed by the transfer molding method, it is not necessary to provide the step where the resin part is ground so that the upper surfaces of the bumps are exposed. Hence, it is possible to simplify the manufacturing method of the semiconductor package.

Instead of the press molding method, the transfer molding method may be used in the processes shown inFIG. 14andFIG. 15of the first embodiment. In this case, the grinding process exposing the metal layer14shown inFIG. 61is not necessary. Hence, it is possible to simplify the manufacturing method of the semiconductor package.

For example, in the semiconductor package10or the like, the wiring layer may be provided at a part of the wiring structure40above the surface30aof the resin part30and the electrode pads may be provided on the wiring layer. In other words, it is possible to provide a fan-out structure in the semiconductor package of the embodiments of the present invention.

In addition, in the semiconductor package10or the like, a heat radiation component such as a heat spreader or the like may be connected to the rear surface20bor the like of the semiconductor chip20.

Furthermore, in the semiconductor package10or the like, it is not necessary to remove the metal layer14so that the metal layer14may remain. In this case, since the rear surface of the semiconductor package10or the like is flat, it is possible to achieve the effect where the heat radiation component such as a heat spreader or the like may be easily connected.

According to the above-discussed embodiments of the present invention, it is possible to provide a semiconductor package whereby it is possible to prevent a semiconductor chip from falling down from a resin part so that strength of the semiconductor package can be improved, and a manufacturing method of the semiconductor package.