Semiconductor package system with thermal die bonding

A semiconductor package system includes providing a substrate having a plurality of thermal vias extending through the substrate. A solder mask is positioned over the plurality of thermal vias. A plurality of thermally conductive bumps is formed on at least some of the plurality of thermal vias using the solder mask. An integrated circuit die is attached to the plurality of thermally conductive bumps. An encapsulant encapsulates the integrated circuit die.

TECHNICAL FIELD

The present invention relates generally to semiconductor package systems, and more particularly to a semiconductor package system providing enhanced thermal conductivity.

BACKGROUND ART

In the electronics industry, the continuing goal has been to reduce the size of electronic devices such as camcorders and portable telephones while increasing performance and speed. Integrated circuit packages for complex systems typically are comprised of a multiplicity of interconnected integrated circuit chips. The integrated circuit chips usually are made from a semiconductor material such as silicon or gallium arsenide. Semiconductor devices are formed in the various layers of the integrated circuit chips using photolithographic techniques. The integrated circuit chips may be mounted in packages that are then mounted on printed wiring boards.

Recently, there has been rapid development in semiconductor technology and, as a result, semiconductors are becoming smaller, circuitry within semiconductors is becoming increasingly dense to provide higher speeds. As the density increases however, higher power is used in these semiconductor components. Higher power results in greater heat generation in such semiconductors. Thus, heat dissipation is becoming more critical as semiconductor technology develops to address the increasing demand for semiconductors having higher power and speed.

Various techniques may be used to remove or dissipate heat generated by a semiconductor. One such technique involves the use of a mass of conductive material in thermal contact with the semiconductor. The mass of conductive material typically is referred to as a heat spreader. One of the primary purposes of a heat spreader is to absorb and dissipate the heat generated by the electronic circuitry on the semiconductor and to spread the heat away from the semiconductor. The heat spreader thereby removes the heat from the semiconductor and reduces the likelihood of the occurrence of hot spots that can have an adverse effect on the performance and reliability of the semiconductor.

Heat spreaders are made of a thermally conductive material such as aluminum, electro-plated copper, copper alloy, or ceramic, for example. A heat spreader is positioned in thermal contact with a semiconductor by use of a thermally conductive material, such as thermally conductive gels, greases, or solders, as well as to provide thermal conductivity between the semiconductor and the heat spreader.

An electronic device may comprise at least one semiconductor coupled to a heat spreader and a substrate carrier. Passive electronic components such as capacitors also may be attached to the substrate carrier. Typically, the semiconductor is attached to one side of the substrate carrier by means of a number of solder balls, solder bumps, or other alternative connections. The heat spreader may be formed out of a suitable thermally conductive material such as copper, aluminum, carbon composites, or alternative suitable materials. The heat spreader is typically positioned in thermal contact with the semiconductor by means of a thermal adhesive.

A semiconductor device is produced by mounting, on the multilayer circuit board thus formed, a semiconductor chip or chips and required circuit parts. In recent years, semiconductor elements have had increasingly improved performances, thereby increasing the amount of heat generated therefrom. Conventional methods for dealing with an increased amount of heat generated from such a semiconductor element include a method of dissipating the generated heat by attaching a heat spreader (or heat sink) to the semiconductor element and using a fan. Also, a metal sheet with good heat-dissipating properties is used as a core substrate in order to improve the heat-dissipating properties of a multilayer circuit board on which a semiconductor element is mounted.

However, even with a multilayer circuit board using a metal sheet for a core substrate, the heat-dissipating properties are not always enough considering the increasing amount of heat generated from a semiconductor element, and a multilayer circuit board having better heat-dissipating properties is required to remove the heat generated from a semiconductor element.

It is known to use a member made of a metal to cover a semiconductor element mounted on a multilayer circuit board, to thereby dissipate heat generated by the semiconductor element from the top face of the metallic member to the environment. Again, with a multilayer circuit board using such a cover member, heat-dissipating properties are not always enough to increase amount of heat removed from a semiconductor element, and a multilayer circuit board having improved heat-dissipating properties is again required.

To increase thermal performance of packages, most packages are manufactured using high thermal conductivity epoxy where increasing conductive filler content or solvent loading increases the thermal conductivity. In these cases, the material cost is increased around double compared with conventional epoxy material. At the same time, it is very hard to get stable workability and reliable performance with these packages.

DISCLOSURE OF THE INVENTION

The present invention provides a semiconductor package system that includes providing a substrate having a plurality of thermal vias extending through the substrate. A solder mask is positioned over the thermal vias. A plurality of thermally conductive bumps is formed on at least some of the plurality of thermal vias using the solder mask. An integrated circuit die is attached to the plurality of thermally conductive bumps. An encapsulant encapsulates the integrated circuit die.

Certain embodiments of the invention have other advantages in addition to or in place of those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.

BEST MODE FOR CARRYING OUT THE INVENTION

Likewise, the drawings showing embodiments of the device are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the FIGs. In addition, where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration and description thereof like features one to another will ordinarily be described with like reference numerals.

The term “thermal” as used herein describes structures used only for heat transfer and specifically excludes structures used for electrical transfer. This is to differentiate structures of the present invention from electrically conductive structures whose primary purpose is for conducting electricity but which may incidentally conduct heat since they are made of heat conductive materials as described for the present invention.

Referring now toFIG. 1, therein is shown a cross-sectional view of a semiconductor package100at an intermediate stage of manufacture in accordance with an embodiment of the present invention. The semiconductor package100includes a substrate102, such as a printed circuit board (PCB). The substrate102has a number of thermal vias104formed through the central portion of the substrate102where an integrated circuit die (not shown) is to be attached.

Typically, the thermal vias104are about 100 microns in width. Each of the thermal vias104is lined with a thin thermally conductive coating, such as copper (Cu), having a thickness of about 10 microns. The thermally conductive coating also is formed on the surfaces of the substrate to provide a wettable layer for subsequent application of thermally conductive bumps as discussed below. The substrate typically is provided with the thermal vias104formed in the substrate102by the substrate manufacturer. There is thus provided a substrate102having a number of thermal vias104formed therethrough.

It has been discovered that the thermally conductive adhesive is applied efficiently using a screen printing process. A solder mask is positioned over the thermal vias104in a suitable pattern as discussed below. The thermally conductive adhesive is formed over the area to which the integrated circuit will be attached in a pattern depending upon the semiconductor package100being manufactured as discussed below.

The thermally conductive adhesive typically is reflowed, defluxed, and pre-baked if necessary before attachment of the integrated circuit as described below.

The substrate102also includes a number of contacts106formed in the upper and lower surfaces of the substrate. The contacts106typically are connected using an interconnect array108in accordance with the requirements of the semiconductor package100being manufactured. As will be discussed below in more detail, the contacts106in the upper surface of the substrate102are used to electrically connect the integrated circuit die to the substrate102. The contacts in the lower surface of the substrate102are used to electrically connect the substrate102to another surface, such as a printed circuit board (PCB), such as by forming a number of solder balls.

Referring now toFIG. 1A, therein is shown an enlarged cross-sectional view of a thermal via104. The thermal via104typically has a width of about 100 microns or greater. The thermal via104is lined with a liner122of a thermally conductive material, such as copper. The liner122typically has a thickness of about 10 microns. The liner122provides a wettable surface for a high thermal conductivity filler material126, such as a high thermal conductivity solder. The thermal vias typically are formed in the central portion of the substrate102.

Referring now toFIG. 2, therein is shown a top plan view of the structure ofFIG. 1. The semiconductor package100includes the substrate102. Typically, the contacts106are formed around the periphery of the substrate102. The central portion of the substrate102has the number of thermal vias104.

Referring now toFIG. 3A, therein is shown a plan view of a solder mask300having a number of openings302of a circular shape formed in a close packed square pattern.

Referring now toFIG. 3B, therein is shown a plan view of a solder mask310having a number of openings312of a quadrangle shape formed in a close packed square pattern.

Referring now toFIG. 3C, therein is shown a plan view of a solder mask320having a number of openings322of a hexagonal shape formed in a close packed square pattern.

It will be apparent to those skilled in the art upon a reading of this description that other shapes and arrangements of the thermal vias may be used in a particular design.

Referring now toFIG. 4A, therein is shown a plan view of a solder mask400having a number of openings402of a circular shape arranged in a first open array pattern404. The first open array pattern404has an outer array406of the openings402around the periphery of the solder mask400except at the corners thereof. An inner array408of the openings402is formed interior to the outer array406except at the corners thereof. The area central to the inner array408has none of the openings402.

Referring now toFIG. 4B, therein is shown a plan view of a solder mask410having a number of openings412of a circular shape arranged in a second open array pattern414. The second open array pattern414has an outer array416of the openings412around the periphery of the solder mask410except at the corners thereof. The openings412in the outer array416are spacer farther apart from each other than the openings412in the first open array pattern404referred to inFIG. 4A. An inner array418of the openings412is formed interior to the outer array416except at the corners thereof. The openings412in the inner array418also are spaced farther apart than the openings402in the inner array408shown inFIG. 4A. The area central to the inner array418has none of the openings412.

Referring now toFIG. 4C, therein is shown a plan view of a solder mask420having a number of openings422of a circular shape arranged in a third open array pattern424. The third open array pattern424has an outer array426of the openings422around the periphery of the solder mask420including at the corners thereof. The openings422in the outer array426are spacer closer together to each other than the openings402in the first open array pattern404referred to inFIG. 4Aand the second open array pattern414referred to inFIG. 4B. An inner array428of the openings422is formed interior to the outer array426except at the corners thereof. The openings422in the inner array428also are spaced closer together to each other than the openings412in the inner array418shown inFIG. 4B. The area central to the inner array428has none of the openings422.

The variety of examples of array patterns shown inFIGS. 4A,4B, and4C are shown to demonstrate the flexibility available to provide various patterns of openings in the solder mask depending upon the particular design considerations for a given semiconductor package. It will be apparent to those skilled in the art upon a reading of this description that other array patterns may be used as well. The heat dissipation characteristics of a particular semiconductor package thus can be relatively closely controlled by the design of the solder mask being used.

Referring now toFIG. 5, therein is shown the structure ofFIG. 1with an integrated circuit die500attached. An inactive side of the integrated circuit die500is attached to the thermal vias104using a number of thermally conductive bumps502. The thermally conductive bumps502typically comprise a thermally conductive material, such as at least one of a high thermal epoxy, a eutectic solder paste, a tin-silver solder paste, compounds thereof, alloys thereof, and combinations thereof.

High thermal epoxies are those epoxies having a thermal coefficient of at least about 20 W/mK. Typical eutectic solder pastes are tin-lead (Sn/Pb) solder pastes with a composition of about 63% Sn to about 37% Pb having a thermal coefficient of at least about 50 W/mK. Suitable tin-silver (Sn/Ag) solder pastes with a composition of about 96% Sn to about 4% Ag have a thermal coefficient of at least about 221 W/mK.

It has been discovered that the use of a particular thermally conductive material to form the thermally conductive bumps502in combination with the arrays of the thermal vias104shown and described above with reference toFIGS. 3A,3B,3C,4A,4B, and4C provide a wide range of design capabilities that variously can be used to meet the design requirements of a the semiconductor package100.

An adhesive504is used to physically attach the integrated circuit die500to the substrate102. The adhesive can be any suitable adhesive, such as an epoxy, that is used in semiconductor manufacturing processes. It will be noted by one skilled in the art upon a reading of this description that the adhesive504can be selected primarily for its adhesive capabilities without regard for its thermal conductivity. The thermal conductivity from the integrated circuit die500through the thermal vias104is provided by the thermally conductive bumps502. Consequently, a less expensive adhesive can be used to physically attach the integrated circuit die500to the substrate102.

Additionally, the screen printing can be performed at the same time as the integrated circuit die500is mounted thereby requiring no significant additional processing.

Referring now toFIG. 6, therein is shown the structure ofFIG. 5after encapsulation. The integrated circuit die500is electrically connected to the contacts106on the substrate102using a number of wires600. The wires600are connected to the integrated circuit die500and the contacts106in the substrate102using a wire bonding process. The wires600may be connected to the contacts using a solder bump602.

A number of passive components604also may be attached to the substrate102depending upon the design requirements of the semiconductor package100in question.

An encapsulant606is formed over the substrate102using a molding process to encapsulate the integrated circuit die500. A heat sink608also may be placed in the encapsulant606to provide a means for dissipating heat generated by the semiconductor package100during operation.

A number of solder balls610are formed on the bottom of the substrate102in contact with the contacts106in the lower surface of the substrate102and in contact with the lower surfaces of the thermal vias104.

It has been discovered that the semiconductor package system of the present invention provides a variably controllable system for dissipating heat from a semiconductor package without the use of expensive thermally conductive epoxies having increased filler content or solvent loading. The present system can be used in a variety of semiconductor packages to control heat dissipation using conventional manufacturing processes and technologies.

In terms of process flow, a screen print process is performed to form the thermally conductive bumps502. A solder mask is positioned over the substrate102in a selected pattern. Solder then is formed over the solder mask. The solder typically is reflowed, defluxed and a pre-bake process is performed. The integrated circuit die500is attached using the adhesive504. The adhesive504is then cured. The integrated circuit die500is then wire bonded to the contacts106on the upper surface of the substrate102. The heat sink608typically is then attached during the encapsulant molding process. The solder balls610are then attached, and a singulation process is performed to form the semiconductor package100.

Referring now toFIG. 7, therein is shown a flow chart of a semiconductor package system700in accordance with the present invention. The semiconductor package system700includes providing a substrate having a plurality of thermal vias extending through the substrate in a block702; providing a solder mask over the plurality of thermal vias in a block704; forming a plurality of thermally conductive bumps on at least some of the plurality of thermal vias using the solder mask in a block706; attaching an integrated circuit die to the plurality of thermally conductive bumps in a block708; and encapsulating the integrated circuit die in a block710.

Thus, it has been discovered that the semiconductor package system of the present invention furnish important and heretofore unavailable solutions, capabilities, and functional advantages for dissipating heat. The resulting process and configurations are straightforward, economical, uncomplicated, highly versatile and effective, use conventional technologies, and are thus readily suited for manufacturing semiconductor devices that are fully compatible with conventional manufacturing processes and technologies.