Semiconductor memory device and manufacturing method thereof

An active region is provided which includes a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions. Floating electrodes and control electrodes are provided on the active region columns. An interlayer insulating film formed as a layer below an upper wiring is provided on the active region and the control electrodes. Conductive sections that electrically connect the upper wiring and the active region are respectively provided on the concave portions on the active region rows.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a structure of a semiconductor memory device (particularly, nonvolatile memory) having a laminated gate structure and a method of manufacturing the same.

2. Description of the Related Art

In a semiconductor memory device having a laminated gate structure, contacts have heretofore been provided at intersecting points of active region columns and active region rows, respectively. Incidentally, the active region columns correspond to an active region extending in a first direction, whereas the active region rows correspond to an active region extending in a second direction substantially orthogonal to the first direction.

FIGS. 3-1and3-2are respectively diagrams showing structures of such a conventional semiconductor memory device. A description will be made here of a nonvolatile memory having floating gates as the semiconductor memory device.FIG. 3-1(a) shows a planar structure of a memory cell of the nonvolatile memory,FIG. 3-1(b) shows a sectional structure of the memory cell, which is taken along line A-A′ shown inFIG. 3-1(a), andFIG. 3-1(c) shows a sectional structure of the memory cell, which is taken along line B-B′ shown inFIG. 3-1(a), respectively.FIG. 3-2(a) illustrates a planar structure of the memory cell of the nonvolatile memory, andFIG. 3-2(b) depicts an equivalent circuit of the nonvolatile memory shown inFIG. 3-2(a), respectively. The semiconductor memory device having such a structure has been disclosed in, for example, Japanese Unexamined Patent Publication No. Hei 1(1989)-181572 (patent document 1).

As shown inFIG. 3-1, an active region101and device isolation regions102are formed within a silicon substrate100. Incidentally, the active region101comprises a plurality of active region columns52extending in a first direction (corresponding to a vertical direction as viewed inFIG. 3-1), and a plurality of active region rows53extending in a second direction (corresponding to a horizontal direction as viewed inFIG. 3-1) substantially orthogonal to the first direction. The active region101and the device isolation regions102are formed with the boundaries of their side surfaces aslant as shown inFIG. 3-1(b) andFIG. 3-1(c) (InFIG. 3-1(a), however, only the upper surface portion of the active region101is shown and the boundaries of the slanted side surfaces of the active region101and the device isolation regions102are shown in an omitted form).

A first gate insulating film107is formed on its corresponding part of the active region101(seeFIG. 3-1(a) andFIG. 3-1(c)).

A floating gate103, which serves as each floating electrode, is formed on each of the first gate insulating film107and the device isolation regions102(seeFIG. 3-1(a) andFIG. 3-1(c)). The floating gate103is a conductive film made principally of polysilicon doped with an impurity and is formed by the known CVD/photolitho/etching technology.

A control gate104, which serves as each control electrode through the second gate insulating film108, is formed on the device isolation regions102of between adjacent floating gates with on the floating gates and in the rows direction of the floating gates. (seeFIG. 3-1(b) andFIG. 3-1(c))

A control gate104, which serves as each control gate, is formed on its corresponding second gate insulating film108(seeFIG. 3-1(a) andFIG. 3-1(c)). The control gate104is a conductive film principally made up of two-layer film polycide of polysilicon doped with an impurity and silicide and is formed by the known CVD/photolitho/etching technology. Incidentally, each control gate104serves even as a word line.

An interlayer insulating film109is formed on the control gate104, the first gate insulating film107, and the device isolation regions102. An upper wiring110is formed on the interlayer insulating film109. (seeFIG. 3-1(b) andFIG. 3-1(c)).

Contacts106, which extend through the interlayer insulating film109and make electrical connections between the active region101and the upper wiring110to be described later, are formed within the interlayer insulating film109(seeFIG. 3-1(a) andFIG. 3-1(b)). The contacts106are formed by firstly forming contact holes extending through the interlayer insulating film109by the know CVD/photolitho/etching technology and then embedding a contact embedding material corresponding to a conductive substance into the contact holes. Incidentally, tungsten is principally used as the contact embedding material.

Further, the upper wiring110is formed on the interlayer insulating film109(seeFIG. 3-1(b) andFIG. 3-1(c)). Incidentally, sinceFIG. 3-1(b) andFIG. 3-1(c) show configurations at the time that the contacts106have been formed, the upper wiring110formed subsequently is shown with a dotted line.

In such a conventional semiconductor memory device51, the contacts106are respectively provided at intersecting points of the active region columns52and the active region rows53as shown inFIG. 3-1(a). If such a conventional semiconductor memory device51is shown in the form of functional components or constituent elements such as bit lines BL, word lines WL, source lines (called also source/drain) SL, etc., it is then represented as shown inFIG. 3-2(a). If the semiconductor memory device51is expressed in an equivalent circuit, it is then represented as shown inFIG. 3-2(b). Incidentally, the source lines SL correspond to portions that do not overlap the contacts106and the word lines WL in the active region101. InFIG. 3-2(a), diagonally-shaped areas indicate fields. In such a conventional semiconductor memory device51, the active region101is formed with the boundary between the side surfaces of the active region101and the device isolation region102aslant at the intersecting point of the active region column52and the active region row53. In contrast, the active region101is vertically formed at a location (an intermediate point of line A-A′ inFIG. 3-1(a) by way of example) other than each intersecting point without slanting the boundary between the side surfaces of the active region101and the device isolation region102. Therefore, each contact106provided at the intersecting point increases in area brought into contact with the active region101at the bottom as compared with the case in which the contact106provided at each intersection point is placed in the location (intermediate point of line A-A′ inFIG. 3-1(a) by way example) other than the intersecting point. Thus, the conventional semiconductor memory device enables a reduction in contact resistance.

Patent Document 1:

In the conventional semiconductor memory device, the contacts have been provided at the intersecting points of the active region columns52and the active region rows53respectively as described above.

In such a conventional semiconductor memory device, the part of first gate insulating film107is etched excessively when the floating gate103is patterned. The first gate insulating film107is etched when the floating gate is removed after the control gate104and the second gate insulating film108are patterned. The floating gate103is formed with polysilicon etc. Liquid into which polysilicon is easy to etch is used in etching process. The first gate insulating film107is removed completely for the twice overetching. Furthermore, the silicon of active region is also etched.

Meanwhile, patterning is being miniaturized or scaled down in recent years in particular. With its scaled-down, the wiring width and depth of a source line is becoming very narrow. Each overetched portion (i.e., concave portion)105that serves as the source line contact is etched deep as the wiring width of the source line becomes small, thereby causing an increase in resistance value. Therefore, the conventional semiconductor memory device has the problem that upon data writing, for example, a current value is reduced so that charge retention characteristics are markedly degraded.

SUMMARY OF THE INVENTION

With the foregoing problems in view, a semiconductor memory device according to the present invention comprises an active region comprising a plurality of active region columns extending in a first direction, and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions, floating electrodes and control electrodes provided on the active region columns, an interlayer insulating film formed as a layer below an upper wiring, which is provided on the active region and the control electrodes, and conductive sections electrically connecting the upper wiring and the active region, which are respectively provided on the concave portions on the active region rows.

The semiconductor memory device according to the present invention includes contacts corresponding to the conductive sections provided on their corresponding concave portions lying on the active region rows. Therefore, an increase in resistance value can be suppressed since a conductive substance is embedded into the concave portions.

A method of manufacturing the semiconductor memory device having such a configuration comprises the following steps of forming an active region comprising a plurality of active region columns extending in a first direction, and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions, forming floating electrodes and control electrodes on the active region columns, forming an interlayer insulating film provided as a layer below an upper wiring, on the active region and the control electrodes, and forming conductive sections which electrically connect the upper wiring and the active region, on the concave portions lying on the active region rows.

The semiconductor memory device according to the present invention is capable of suppressing an increase in resistance value since the conductive substance is embedded in the concave portions. It is, therefore, possible to prevent degradation in charge retention characteristics due to a reduction in current value upon writing of data, for example.

DETAILED DESCRIPTION OF THE INVENTION

In a semiconductor memory device according to the present invention, contacts corresponding to conductive sections are respectively provided on concave portions lying on active region rows. That is, they are respectively provided between respective adjacent intersecting points of active region columns and the active region rows and on portions that overlap in etching upon forming floating and control gates in a planar structure. Incidentally, if semiconductor memory devices each having a laminated gate structure are adopted, then the present invention is applicable to all.

Preferred embodiments of the present invention will be explained hereinbelow with reference to the accompanying drawings. Incidentally, the respective drawings are merely approximate illustrations to such a degree that the present invention can be understood. Thus, the present invention is not limited to the illustrated embodiments alone. In the respective drawings, common constituent elements and similar constituent elements are respectively identified by the same reference numerals, and the description of their common constituent elements will therefore be omitted.

(Configuration of Semiconductor Memory Device)

A configuration of a semiconductor memory device according to an embodiment of the present invention will be explained below usingFIG. 1-1andFIG. 1-2.

FIGS. 1-1and1-2are respectively diagrams showing structures of the semiconductor memory device according to the present invention. Incidentally, a description will be made here of a nonvolatile memory having floating gates as the semiconductor memory device.FIG. 1-1(a) shows a planar structure of a memory cell of the nonvolatile memory,FIG. 1-1(b) shows a sectional structure of the memory cell, which is taken along line A-A′ shown inFIG. 1-1(a), andFIG. 1-1(c) shows a sectional structure of the memory cell, which is taken along line B-B′ shown inFIG. 1-1(a), respectively.FIG. 1-2(a) illustrates a planar structure of the memory cell of the nonvolatile memory, andFIG. 1-2(b) depicts an equivalent circuit of the nonvolatile memory shown inFIG. 1-2(a), respectively.

As shown inFIG. 1-1, an active region101and device isolation regions102are formed within a silicon substrate100. Incidentally, the active region101comprises a plurality of active region columns52extending in a first direction (corresponding to a vertical direction as viewed inFIG. 1-1), and a plurality of active region rows53extending in a second direction (corresponding to a horizontal direction as viewed inFIG. 1-1) substantially orthogonal to the first direction. A first gate insulating film107is formed on its corresponding part of the active region101A floating gate103, which serves as each floating electrode, is selectively formed on each of the first gate insulating film107and the device isolation regions102. A control gate104, which serves as each control electrode through the second gate insulating film108, is formed on the device isolation regions102of between adjacent floating gates with on the floating gates and in the rows direction of the floating gates. Incidentally, a transistor comprises the floating gate103and the control gate104. An interlayer insulating film109is formed on the control gate104, the first gate insulating film107, and the device isolation regions102. An upper wiring110is formed on the interlayer insulating film109. Contacts106, which extend through the interlayer insulating film109and provide electrical connections between the active region101and the upper wiring110, are formed within the interlayer insulating film109. The upper wiring110is formed on the interlayer insulating film109.

As shown inFIG. 1-1(a), the contacts106are respectively disposed on portions (concave portions)105that overlap in etching upon formation of a plurality of the gates103and104, so as to cover the entire surfaces of the concave portions105. That is, the contacts106are respectively disposed between respective adjacent intersecting points of the active region columns52and the active region rows53and placed so as to cover the entire surfaces of portions interposed between respective extension lines (line C-C′ and line D-D′ inFIG. 1-1(a)) of longitudinal sides on the mutually adjoining sides of the two floating gates103adjacent in the transverse direction. Here, the term “cover the entire surfaces of the concave portions105” or “cover the entire surfaces of the portions interposed between the respective extension lines of the longitudinal sides on the mutually adjoining sides of the two floating gates103” means that the concave portions105are hidden from view by the contacts106each identical to or larger than the concave portion105. The contacts106disposed in this way are formed of a contact embedding material which is of a conductive substance. Incidentally, tungsten is principally used as the contact embedding material.

In the semiconductor memory device1having such a configuration, the contacts106are respectively provided between the respective adjacent intersecting points of the active region columns52and the active region rows53as shown inFIG. 1-1(a). If the semiconductor memory device1constructed in this way is represented in the form of functional constituent elements such as bit lines BL, word lines Wl, source lines (called also source/drain) SL, etc., it is then configured as shown inFIG. 1-2(a). If the semiconductor memory device is expressed in an equivalent circuit, it is then represented as illustrated inFIG. 1-2(b).

Incidentally, such a semiconductor memory device1includes a plurality of the transistors each consisting of the floating electrode (floating gate103) and the control electrode (control gate104), and the interlayer insulating film109and the upper wiring110formed on the transistors. Further, the semiconductor memory device1is provided with the active region101comprising the plurality of active region columns52and the plurality of active region rows53that connect the plurality of active region columns52. The semiconductor memory device1also has a configuration wherein regions (concave portions105) removed upon patterning of the floating electrodes are respectively provided on the active region rows53, and the upper wiring110and the regions removed upon patterning of the floating electrodes, which are lying on the active region rows53, are electrically connected.

<Manufacturing Method of Semiconductor Memory Device>

A method of manufacturing a semiconductor memory device will be explained below usingFIGS. 2-1through2-5.

FIGS. 2-1through2-5are diagrams showing the method of manufacturing the semiconductor memory device, according to the present invention.FIGS. 2-1(a) through2-5(a) respectively show a planar structure of a memory cell.FIGS. 2-1(b) through2-5(b) respectively show a sectional structure of the memory cell and are respectively sectional diagrams taken along lines A-A′ ofFIGS. 2-1(a) through2-5(a).FIGS. 2-1(c) through2-5(c) respectively show a sectional structure of the memory cell and are respectively sectional diagrams taken along lines B-B′ ofFIGS. 2-1(a) through2-5(a). Incidentally,FIGS. 2-1through2-5show processes for manufacturing the semiconductor memory device1shown inFIGS. 1-1and1-2and can suitably be changed depending on the configuration of the semiconductor memory device1.

As shown inFIGS. 2-1(a) through2-1(c), an active region101and device isolation regions102are formed in a silicon substrate100.

Next, as shown inFIGS. 2-2(a) through2-2(c), a first gate insulating film107is formed on its corresponding part on the active region101, and each of floating gates103is formed on each of the first gate insulating film107and the device isolation regions102. Incidentally, the floating gate103is a conductive film (which principally makes use of polysilicon doped with an impurity) and is formed by the known CVD/photolitho/etching technology.

The floating gate is patterned after formed overall. In this case the first gate insulating film107is etched excessively on the position, which the floating gate103removed on the active region. The first gate insulating film107is usually etched 50 through 70%.

Next, as shown inFIG. 2-3(a) through2-3(c), the second gate insulating film108is formed overall, and the control gate104is formed on the second gate insulating film108. The control gate104and the second gate insulating film108, without which serve as each word line WL, are removed by the known CVD/photolitho/etching technology.

Next, as shown inFIG. 2-4(a) through2-4(c), the floating gates103other than the floating gate103under the word line WL is removed by etching processing. Next, as shown inFIG. 2-5(a) through2-5(c), the interlayer insulating film109is formed overall. The interlayer insulating film109at the portions (concave portions)105that overlap in etching between respective adjacent intersecting points of the active region columns52and the active region rows53and upon formation of the floating gates103and the control gates104, is removed by etching processing. A contact embedding material (principally tungsten) corresponding to a conductive substance is embedded into holes (contact holes) formed by the above processing to thereby form contacts106. Incidentally, “the portions (concave portions)105that overlap in etching between the respective adjacent intersecting points of the active region columns52and the active region rows53and upon formation of the floating gates103and the control gates104” correspond to portions interposed between respective extension lines (lines C-C′ and D-D′ inFIG. 1-1(a)) of longitudinal sides on the mutually adjoining sides of the two floating gates103adjacent in a transverse direction in the planar structure. The portions (concave portions)105that overlap in etching are formed as trenches or grooves deeper than other regions by etching upon formation of the floating gates103and the control gates104. The contacts106are respectively disposed so as to cover the entire surfaces of the concave portions105. Thus, since the conductive substance (principally tungsten or the like) is embedded into the grooves formed by etching, the semiconductor memory device1is capable of suppressing a rise in source line resistance. Incidentally, it is necessary to reliably implant an implant between tungsten embedded in the contact holes and the active region101corresponding to a semiconductor layer upon formation of the contacts106. This is done by ion-implanting an impurity (n-type impurity where the active region101is of an n type) of the same type as the active region101by a known ion implantation technique after formation of the contact holes by the known CVD/photolitho/etching technology and thereafter embedding tungsten therein.

Thus, the method of manufacturing the semiconductor memory device1, according to the present embodiment includes a step for forming the active region101comprising a plurality of the active region columns52extending in a first direction, and a plurality of the active region rows53extending in a second direction substantially orthogonal to the first direction and having the concave portions105, a step for forming floating electrodes (floating gates103) and control electrodes (control gates104) on the active region columns52, a step for forming the interlayer insulating film109configured as a layer below an upper wiring110on the active region101and the control electrodes, and a step for forming conductive sections (contacts106) which provide electrical connections between the upper wiring110and the active region101, on the concave portions105lying on the active region rows53.

The method of manufacturing the semiconductor memory device1, according to the present embodiment is a method of manufacturing a semiconductor memory device1comprising a plurality of transistors consisting of floating electrodes (floating gate103) and control electrodes (control gates104), and an interlayer insulating film109and an upper wiring110formed on the transistors. The method includes a step for forming an active region101comprising a plurality of active region columns52and a plurality of active region rows53which connect the plurality of active region columns52, a step for patterning the floating electrodes and removing predetermined regions (i.e., regions which come to the portions105) on the active region rows53, and a step for forming conductive sections (contacts106) which provide electrical connections between the upper wiring110and the removed predetermined regions on the active region rows53.

The method of manufacturing the semiconductor memory device1, according to the present embodiment includes a step for forming in a silicon substrate100, an active region101comprising a plurality of active region columns52extending in a first direction and a plurality of active region rows53extending in a second direction substantially orthogonal to the first direction and having concave portions105, and device isolation regions102, a step for forming a first gate insulating film107on its corresponding part of the active region101, a step for forming each of floating gates103on the first gate insulating film107and the device isolation region102, a step for forming a second gate insulating film108on the floating gates103in regions in which the floating gates103are formed, and on the active region101in regions in which no floating gates103are formed, a step for forming control gates104on the second gate insulating film108, a step for forming an interlayer insulating film109configured as a layer below the upper wiring110on the active region101and the control gates104, and a step for forming contacts106for providing electrical connections of the upper wiring110and the active region101on the concave portions105lying on the active region rows53.

<Operation of Semiconductor Memory Device>

In the semiconductor memory device1according to the present invention, the concave portion105sends an electrical charge to its corresponding floating gate103upon writing of data, whereas it functions as a source line SL which becomes a diffusion layer of each transistor formed of the floating gate103and the control gate104, upon reading of data.

The semiconductor memory device1according to the present invention has the following advantageous effects.

The contacts106are respectively disposed so as to cover the entire surfaces of the portions (concave portions)105that overlap in etching between the respective adjacent intersecting points of the active region columns52and the active region rows53and upon formation of the floating gates103and the control gates104. Further, the contacts106are embedded with the contact embedding material corresponding to the conductive substance. Therefore, the semiconductor memory device1according to the present invention is capable of avoiding an increase in source line resistance as viewed in a current path direction (direction taken along line A-A′ shown inFIG. 1-1(a)) of each source line, which is caused by a deep dug portion (i.e., trench formed by etching upon formation of the floating gate103and the control gate104) of the silicon substrate104and reducing the source line resistance as compared with the conventional semiconductor memory device51.

Also the contacts106are respectively disposed between the respective adjacent intersecting points of the active region columns52and the active region rows53. Therefore, the area where the contact106makes contact with the active region101at its bottom, becomes small as compared with the case in which the contacts106are disposed on the intersecting points of the active region columns52and the active region rows53as in the conventional semiconductor memory device (seeFIG. 3-1(a)). The influence of an increase in contact resistance is considered here. However, with miniaturization of patterning in recent years, divots due to wet processing in an STI forming process occur at the boundary between the active region101and each device isolation region102where, for example, the device isolation method is changed from the conventional LOCOS method to the STI (Shallow Trench Isolation) method. Therefore, excessive etching is required to etch the conductive film of each divot in the process of forming the control gates104, thus causing a further increase in substrate digging of each source line SL. However, the substrate digging of the source line SL greatly influences the resistance of the entire current path rather than the area where each contact106makes contact with the active region101at its bottom. Therefore, the semiconductor memory device1according to the present invention acts in the direction to avoid the influence of the substrate digging of the source line SL. As a result, the semiconductor memory device1according to the present invention is capable of improving charge retention characteristics since a current value at the writing of data increases.

As shown inFIG. 2-5(a), the contacts106are disposed sufficiently distant from the device isolation regions102. Therefore, the semiconductor memory device1according to the present invention is capable of increasing an allowable rage for patterning alignment displacements in the transverse direction (direction taken along line A-A′) of the planar structure at the pattern formation of each contact106and enhancing stability of yields.

It is preferable that in the semiconductor memory device1according to the present invention, the contacts106are formed small and the control gates104lying in the vicinity of the contacts106are formed on a large scale, as viewed in the transverse direction (direction taken along line A-A′) of the planar structure. Thus, the semiconductor memory device1according to the present invention is capable of remarkably reducing the wiring width of each control gate104and achieving a further reduction in source line resistance.

The semiconductor memory device1includes a plurality of transistors comprising floating electrodes (floating gates103) and control electrodes (control gates104), and an interlayer insulating film109and an upper wiring110formed on the transistors. The semiconductor memory device1also includes an active region101comprising a plurality of active region columns52and a plurality of active region rows53which connect the plurality of active region columns52. Further, the semiconductor memory device1has a configuration wherein regions (concave portions105) removed upon patterning of the floating electrodes are respectively provided on the active region rows53, and the upper wiring110and the regions removed upon patterning of the floating electrodes, which are provided on the active region rows53, are electrically connected.

Thus, the upper wiring110formed on the transistors and the regions (concave portions105) removed upon patterning of the floating electrodes, which are provided on the active region rows53, are electrically connected in the semiconductor memory device1. It is, therefore, possible to suppress an increase in resistance value.

The present invention is not necessarily limited to the above embodiments. Various applications and modifications are considered within the scope not departing from the substance of the present invention.

If semiconductor memory devices each having a laminated gate structure are adopted, then the present invention is applicable to all of them.