Circuit board and method for manufacturing same

Disclosed herein are a circuit board and a method of fabricating the same. The circuit board includes: a base substrate having a device mount area defined thereon; a first wiring pattern formed on a first surface of the base substrate; a dummy pattern formed on the base substrate, wherein at least a part of the device mount area is filled with the dummy pattern; a first protective layer covering the first wiring pattern and the dummy pattern; and a lead pattern formed on the first protective layer, wherein the lead pattern is extended to the device mount area.

TECHNICAL FIELD

The present disclosure relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board including a dummy pattern and a method of fabricating the same.

BACKGROUND ART

Recently, as the size of electronic devices is ever reduced, a chip on film (COF) package technology using a flexible circuit board is being employed. Flexible circuit boards and the COF package technology using the same are used in flat panel display (FPD) devices, such as liquid-crystal crystal display (LCD) device and organic light-emitting diode (OLED) display devices. A display driving IC (DDIC) for driving a flat panel display device, for example, may be mounted on such a circuit board.

FIG. 11is a cross-sectional view of an existing circuit board.

InFIG. 11, wiring patterns20are formed on a base substrate10, and a first protective layer30is formed to cover the wiring patterns20. Since the wiring patterns20protrude from the base substrate10, the first protective layer30covering the wiring patterns20may have the uneven surface along the shape of the upper surface of the wiring patterns20. In addition, during a reflow process for mounting a device, the surface of the first protective layer30already formed on the substrate may be deformed or become uneven.

Moreover, a lead pattern40is formed to connect a DDIC mounted on the circuit board with the wiring patterns20. The lead pattern40may become curvy or uneven along the shape of the upper surface of the first protective layer30described above. As a result, there is a problem that a device or a bump may fail to be reliably bonded to the upper surface41of the lead pattern during a reflow process.

DISCLOSURE

Technical Problems

Aspects of the present disclosure provide a circuit board including a dummy pattern and a method of fabricating the same.

This and other aspects, embodiments and advantages of the present disclosure will become immediately apparent to those of ordinary skill in the art upon review of the Detailed Description and Claims to follow.

Technical Solutions

According to an aspect of the present disclosure, there is provided a circuit board including: a base substrate having a device mount area defined thereon; a first wiring pattern formed on a first surface of the base substrate; a dummy pattern formed on the base substrate, wherein at least a part of the device mount area is filled with the dummy pattern; a first protective layer covering the first wiring pattern and the dummy pattern; and a lead pattern formed on the first protective layer, wherein the lead pattern is extended to the device mount area.

The lead pattern may include a bonding portion where a device is mounted in the device mount area, and wherein the dummy pattern is expanded outwardly of the bonding portion by a first distance.

The first distance may range from 0.1 μm to 100 μm.

The dummy pattern may include a hole via which the first surface of the base substrate in the device mount area is exposed; and a periphery around the hole.

The circuit board may further include: a through hole formed through the first protective layer, wherein the first wiring pattern is exposed via the through hole; and a connection wiring electrically connecting the lead pattern with the first wiring pattern, wherein the through hole is filled with the connection wiring.

The circuit board may further include: a second protective layer formed to cover the lead pattern above the first protective layer.

The dummy pattern may not be connected to the first wiring pattern.

The circuit board may further include: a second wiring pattern formed on a second surface of the base substrate; and the second wiring pattern may be electrically connected to the first wiring pattern by a via penetrating through the base substrate.

The circuit board may be implemented as a stack of n layers, where n is a natural number equal to or greater than two.

According to another aspect of the present disclosure, there is provided a method of fabricating a circuit board, the method including: providing a base substrate having a device mount area defined thereon; forming a wiring pattern and a dummy pattern in the device mount area, on a first surface of the base substrate; forming a first protective layer to cover the wiring pattern and the dummy pattern; and forming a lead pattern extended from the device mount area on the first protective layer.

The forming the lead pattern may include forming a through hole through the first protective layer to expose the wiring pattern; forming a connection wiring so that the via hole is filled with it; plating a surface of the connection wiring.

The method may include simultaneously forming the connection wiring and the lead pattern.

The circuit board may further include: a second protective layer formed to cover the lead pattern above the first protective layer.

The method may further include: forming an additional lead pattern on the second protective layer, and an additional protective layer covering the additional lead pattern, to form a circuit board made up of n layers, wherein n is a natural number equal to or greater than two.

The method may further include: bonding another circuit board connected to the wiring pattern or the lead pattern to form a circuit board made up of n layers.

Other particulars of the present disclosure will be described in the detailed description with reference to the accompanying drawings.

Advantageous Effects

According to an exemplary embodiment of the present disclosure, a dummy pattern is formed in a device mount area of a circuit board, and accordingly the surface of an insulating layer or a protective layer covering the mount area can be formed evenly, thereby ensuring the connection between the device and lead patterns. Additionally, the unevenness can be reduced by the dummy pattern and the efficiency of heat dissipation can be improved.

It should be noted that effects of the present disclosure are not limited to the above-described effects, and other effects of the present disclosure will be apparent to those skilled in the art from the following descriptions.

BEST MODES FOR CARRYING OUT THE INVENTION

Advantages and features of the present disclosure and methods to achieve them will become apparent from the descriptions of exemplary embodiments hereinbelow with reference to the accompanying drawings. However, the present disclosure is not limited to exemplary embodiments disclosed herein but may be implemented in various different ways. The exemplary embodiments are provided for making the disclosure of the present disclosure thorough and for fully conveying the scope of the present disclosure to those skilled in the art. It is to be noted that the scope of the present disclosure is defined only by the claims. In the drawings, the sizes of the elements may be exaggerated and not drawn on scale for illustrative purposes. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views. The term “and/or” used herein includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being “on” another element or layer, the element or layer can be directly on another element or layer or intervening elements or layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there is no intervening element present.

Terms used herein are for illustrating the embodiments rather than limiting the present disclosure. As used herein, the singular forms are intended to include plural forms as well, unless the context clearly indicates otherwise. Throughout this specification, the word “comprise” and variations such as “comprises” or “comprising,” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

Although terms such as first, second, etc. are used to distinguish arbitrarily between the elements such terms describe, and thus these terms are not necessarily intended to indicate temporal or other prioritization of such elements. Theses terms are used to merely distinguish one element from another. Accordingly, as used herein, a first element may be a second element within the technical scope of the present disclosure.

FIG. 1is a top view of a circuit board according to some exemplary embodiments of the present disclosure.FIG. 2is a cross-sectional view of a circuit board according to some exemplary embodiments of the present disclosure, taken along line A-A′ ofFIG. 1. InFIG. 1, a second protective layer140and a device160are not depicted for convenience of illustration.

Referring toFIG. 1, a circuit board according to some exemplary embodiments of the present disclosure may include a base substrate100, a first wiring pattern110, a first protective layer120, lead patterns130, and a second protective layer140, a dummy pattern150, etc.

The base substrate100may be, for example, a flexible film, and more specifically, may include an insulation film such as a polyimide film, a polyethylene terephthalate (PET) film, a polyethylene naphthalate film and a polycarbonate film, or a metal foil such as aluminum oxide foil.

It is, however, to be understood that the present disclosure is not limited thereto. The base substrate100may be a rigid circuit board. More specifically, the base substrate100may include an epoxy or phenol resin.

In the following description, a polyimide film will be described as an example of the base substrate100.

A device mount area200where a device is to be mounted may be defined in the base substrate100. In the device mount area200of the circuit board according to some exemplary embodiments of the present disclosure, a device160is to be mounted, and the device mount area200may include longer sides and shorter sides. More specifically, the device mount area200may include the entire surface formed on the inner side of the area where the lead patterns130overlap the dummy pattern150, which will be described later.

Specifically, the device160to be mounted in the device mount area200may be, for example, a semiconductor device such as a display driving IC (DDI), but the present disclosure is not limited thereto. The device160may be a passive element such as a resistor, a capacitor and an inductor.

When the device160is a passive element, a connector170for connecting the device160with the lead patterns130may include solder.

When the device160is a semiconductor device, a connector170for connecting the device160with the lead patterns130may include a bump. According to some exemplary embodiments of the present disclosure, the device160may include a semiconductor device bonded to the lead patterns130by flip-chip bonding.

The first wiring pattern110may be formed on a surface of the base substrate100. The first wiring pattern110may transmit an electrical signal transmitted to the device160. The first wiring pattern110may include, but is not limited to, a conductive material such as copper. Specifically, the first wiring pattern110may include a material having electrical conductivity such as gold and aluminum. In a circuit board according to some exemplary embodiments of the present disclosure, the wiring pattern110includes copper.

Although the first wiring pattern110is not extended to the device mount area200in the example shown inFIG. 1, the present disclosure is not limited thereto. A part of the first wiring pattern110may be extended to the device mount area200.

The first protective layer120may be formed to cover the first wiring pattern110. The first protective layer120may be formed to cover the base substrate100including the first wiring pattern110partially or entirely. The first protective layer120may include, for example, a non-conductive material, and specifically, may include a solder resist or a coverlay film.

In addition, as shown inFIG. 2, a through hole180may be formed in the first protective layer120. The through hole180may be filled with a connection line181. The connection line181may electrically connect the lead patterns130formed on the first protective layer120with the first wiring pattern110. In the views ofFIGS. 2 and 3, the through hole180has a trapezoidal cross section, but this is merely illustrative. The through hole180may have a rectangular cross section having the width of the upper surface equal to the width of the lower surface. The through hole180may have, but is not limited to, a circular cross section when viewed from the top.

The lead patterns130may be formed on the first protective layer120. At least some of the lead patterns130may be extended toward the device mount area200to include a bonding portion190where a device is mounted.

Although seven lead patterns130are formed on each of the longer sides and two lead patterns130are formed on each of the shorter sides of the device mount area200in the example shown inFIG. 1, this is merely illustrative. The number of the plurality of lead patterns130may vary depending on the configuration of the elements arranged in the device mount area200.

The lead patterns130may be disposed so that it may at least partially overlap with the first wiring pattern110or the dummy pattern150formed in the device mount area200of the base substrate100, which will be described later.

The lead patterns130may include, but is not limited to, a metal wire with a plated surface, e.g., a copper wire plated with tin, nickel, or aluminum.

The second protective layer140may be formed to cover the first protective layer120and the lead patterns130. The second protective layer140may cover the lead patterns130, except a part of the lead patterns130bonded to the device160.

The second protective layer140may include, for example, a non-conductive material, and specifically, may include a solder resist or a coverlay film.

According to some exemplary embodiments of the present disclosure, the second protective layer140may also be formed on the first protective layer120overlapping the device160. In addition, although not shown in the drawings, the second protective layer140may surround the bottom of the device160and the connector170as an underfill of the device160.

In such case, the second protective layer140on the lead patterns130that surrounds the device160bonded in the device mount area200and the second protective layer140under the device160may be formed simultaneously. It is, however, to be understood that the present disclosure is not limited thereto. For example, the second protective layer140on the lead patterns130may be formed first, and the second protective layer140under the device160may be formed later.

The dummy pattern150may be formed entirely in the device mount area200on the base substrate100, and the dummy pattern150may not be connected to the adjacent first wiring pattern110.

The dummy pattern150may include the same conductive material as the first wiring pattern110, but the present disclosure is not limited thereto. For example, the dummy pattern150may include, for example, a metal material such as gold, silver and copper or an epoxy resin, a polyimide resin, a carbon resin, etc.

The dummy pattern150formed of the above-listed materials may overlap the device160mounted in the device mount area200. Therefore, when the device160is driven, a part of the heat generated from the device160may be discharged to the outside through the dummy pattern150.

In addition, the first wiring pattern110and the dummy pattern150may be formed simultaneously. It is, however, to be understood that the present disclosure is not limited thereto. They may be formed at different processes.

As the dummy pattern150is formed on the base substrate100in the device mount area200where the first wiring pattern110is not formed, the profile of the upper surface of the first protective layer120in the device mount area200can be made flat.

For the existing circuit board described above with reference toFIG. 11, due to the plurality of wiring patterns20formed in the device mount area and spaces21therebetween, the upper surface of the first protective layer31covering them and the lead pattern41formed thereon may become uneven. In contrast, for the circuit board according to the exemplary embodiment of the present disclosure, the spaces21in the device mount area200are filled with the dummy pattern15, and then the first protective layer120covers them, so that the upper surface of the first protective layer120can be made flat.

In addition, the upper surface of the dummy pattern150may be on the same plane as the first wiring pattern110. Thus, the distance from the base substrate100to the upper surface of the dummy pattern150may be equal to the distance from the base substrate100to the upper surface of the first wiring pattern110.

Accordingly, in the circuit board according to some exemplary embodiments of the present disclosure, the unevenness of the upper surface of the first protective layer120can be avoided by virtue of the dummy pattern150formed in the device mount area200, so that the device160can be mounted more reliably.

In addition, as shown inFIGS. 2 and 3, the dummy pattern150may be expanded so that it may be equal to or larger than the area of the device160in the device mount area200. Specifically, the dummy pattern150may be extended outwardly from the bonding portion between the connector170and the lead pattern130by a predetermined distance D. The distance D may be, for example, from 0.1 μm to 100 μm.

The dummy pattern150may be formed in the device mount area200. The device mount area200may be filled with the dummy pattern150. The dummy pattern150may not be connected to the first wiring pattern110.

Hereinafter, shapes of dummy patterns150according to some exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. The shape of a dummy pattern151may be different from the shape of the dummy pattern150according to the above-described exemplary embodiment.

FIG. 3is a top view of a circuit board according to some exemplary embodiments of the present disclosure. Hereinafter, the redundant description will be omitted and description will be made focusing on the differences.

Referring toFIG. 3, in some exemplary embodiments of the present disclosure, the dummy pattern151may include a hole201via which a part of the device mount area is exposed, and a periphery202around the hole201.

As such, when the device mount area200is not completely filled with the dummy pattern150, flexibility of the base substrate100can be increased. In particular, when the base substrate100is a flexible circuit board, the base substrate100on which the device160is mounted may be bent or folded in an electronic device. At this time, the dummy pattern151having the hole201formed therein can suppress the deterioration of the flexibility of the device mount area200.

FIGS. 4 and 5are top views of circuit boards according to some exemplary embodiments of the present disclosure. Likewise, the redundant description will be omitted and description will be made focusing on the differences.

The dummy patterns shown inFIGS. 4 and 5are different from the dummy pattern of the flexible circuit board shown inFIG. 1which has the rectangular shape in that a dummy pattern250ofFIG. 4has an elliptical shape and a dummy pattern350ofFIG. 5has an amorphous shape depending on the design of the pattern formed on the circuit board.

When the dummy pattern is formed in an elliptical shape, the shape of the outer circumferential surface of the dummy pattern250ofFIG. 4may not only have a continuous inclination, but also have a larger area for the patterns110and130when the first wiring pattern110and the lead patterns130of an inner lead part or an outer lead part are concentrated at the center of the device160due to the pattern design such as a radial shape. Therefore, it is possible to reduce the unevenness due to the patterns110and130and to improve the efficiency of heat dissipation.

When the dummy pattern350is formed in an amorphous shape as shown inFIG. 5, the distances D1, D2and D3between the longer side of the device mount area and different positions of the dummy pattern may be different from one another. Accordingly, it is possible to reduce the surface unevenness even if patterns are formed in a staggered manner.

FIG. 6is a cross-sectional view of a circuit board in accordance with some exemplary embodiments of the present disclosure, taken along the line A-A′ ofFIG. 1. Hereinafter, the redundant description will be omitted and description will be made focusing on the differences.

Referring toFIG. 6, a circuit board according to some exemplary embodiments of the present disclosure may further include a second wiring pattern210formed on the other surface of the base substrate100.

The second wiring pattern210may be formed on the other surface, which is the opposite surface of one surface of the base substrate100on which the first wiring pattern110is formed. The second wiring pattern210may include the same material as the first wiring pattern110, and more specifically, may include a material having electrical conductivity such as copper, gold and aluminum.

The first wiring pattern110may be electrically connected to the second wiring pattern210through a via281. Specifically, a via hole280may be formed through the base substrate100, and the via hole280may be filled with the via281.

As shown inFIG. 6, the shape of the via281may have, but is not limited to, a trapezoidal shape in which the lower surface in contact with the second wiring pattern210has a larger width. This shape may be because the via hole280is formed from the other surface of the base substrate100when the via hole280is formed. The via hole280in which the upper surface has a larger width than the lower surface and a via281filling the via hole280may be formed depending on the direction in which the via hole280is formed.

In the foregoing description, the circuit board according to some exemplary embodiments of the present disclosure has been described as having the structure in which the wiring pattern110made up of a single layer is formed on the surface. Alternatively, the circuit board may have a structure including n wiring layers, where n is a natural number equal to or greater than two. That is to say, the circuit board may further have a structure of two or more layers in which another lead pattern is formed on the second protective layer140and a protective layer covering the lead pattern is formed. Alternatively, another circuit board may be bonded to the circuit board having the structure ofFIG. 2 or 6so that a multiple-layer substrate structure may be implemented. When the structure includes n layers, the layers may be electrically connected to one another via conductive via holes, etc.

FIGS. 7 to 10are cross-sectional views for illustrating processing steps of a method of fabricating a circuit board according to some exemplary embodiments of the present disclosure.

Referring toFIG. 7, a first wiring pattern110and a dummy pattern150are formed on a base substrate100.

The base substrate100may be a flexible circuit board or a rigid circuit board. The first wiring pattern110may be formed on the base substrate100, for example, by forming a thin metal layer on the base substrate100to etch and pattern it (photoetching); by forming resist patterns on the base substrate100having an underlying layer, electroplating a conductive material between the resist patterns to remove the resist patterns and the underlying layer so that the first wiring pattern110is formed (semi-additive process); or printing a conductive paste to form the first wiring pattern110(printing).

According to some exemplary embodiments of the present disclosure, the dummy pattern150may be formed simultaneously with the first wiring pattern110. That is to say, when the first wiring pattern110is formed, the shape of the dummy pattern150in the device mount area200may be formed by one of the photoetching, the semi-additive process, and the printing.

Referring toFIG. 8, a first protective layer120is formed to cover the first wiring pattern110and the dummy pattern150.

The first protective layer120may be formed by printing or laminating a solder resist or coverlay film on the base substrate100.

Referring toFIG. 9, a through hole180penetrating through the first protective layer120is formed, and lead patterns130and a connection wiring181filling the through hole180are formed. The lead patterns130may be electrically connected to the first wiring pattern110by the connection wiring181.

For example, the through hole180may be formed by forming a mask pattern on the first protective layer120and etching the first protective layer120using the mask pattern as an etch mask. It is, however, to be understood that the present disclosure is not limited thereto.

The connection wiring181and the lead patterns130may be formed by forming a seed layer on the inner side wall of the through hole180and the upper surface of the first protective layer120, electrolytically or electrolessly plating it to form copper wire, and plating the surface of the copper wire with tin or the like.

Referring toFIG. 10, a device160is mounted on the lead patterns130. When the device160is a passive element, the device160may be bonded to the lead patterns130by solder. When the device160is a semiconductor device, a bump of the device160may be disposed on the lead pattern130and bonded to it via a reflow process.

Subsequently, referring back toFIG. 2, a second protective layer140is formed to cover the lead pattern130. The second protective layer140may expose the lead pattern130on the device mount area200.

The second protective layer140may be formed by printing or laminating a solder resist or coverlay film.

In addition, a process for fabricating the circuit board ofFIG. 6may be additionally carried out.

Specifically, the method of fabricating the circuit board according to an exemplary embodiment of the present disclosure may further include forming a via hole280through the base substrate100, and forming a via281and a second wiring pattern210. The forming the via281and the second wiring pattern210may include, for example, forming a seed layer inside the via hole280and on the other surface of the substrate100, and electrolytically or electrolessly plating it.

According to some exemplary embodiments of the present disclosure, the via281and the second wiring pattern210may be formed simultaneously. It is, however, to be understood that the present disclosure is not limited thereto. The via281may be formed first by filling the via hole280with a conductive material, and then the second wiring210may be formed.

In addition to the above process, a process for fabricating a circuit board including an n wiring layers may be additionally performed, where n is a natural number equal to or greater than two. For example, a process for forming another lead pattern on the second protective layer140and a protective layer covering the lead pattern may be further performed.

Alternatively, a process of bonding another circuit board to the circuit board formed according to the method described above with reference toFIGS. 7 to 10may be further performed. In other words, the n-layer circuit board may be fabricated by bonding another circuit board electrically connected to the wiring pattern110or the lead patterns130.

In fabricating the n-layer circuit board, a process of forming conductive via holes or the like so that the layers are electrically connected to one another may be further added.

Although the exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art will readily appreciated that various modifications and alterations may be made without departing from the technical idea or essential features of the present disclosure. Therefore, it should be understood that the above-mentioned embodiments are not limiting but illustrative in all aspects.