Semiconductor device and method of manufacturing the same

Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a second insulation layer on the first insulation layer, the second insulation layer including a metal head pattern, a thin film resistor pattern on the metal head pattern, a third insulation layer on the thin film resistor pattern, an upper metal line on the third insulation layer, a first via passing through the first, second, and third insulation layers to connect the lower metal line to the upper metal line, and a second via passing through the third insulation layer and the thin film resistor pattern to connect the metal head pattern to the upper metal line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2011-0105471, filed Oct. 14, 2011, which is hereby incorporated by reference.

BACKGROUND

Passive devices perform important functions in an electronic system. Recently, the making of miniaturized, multi-functional, and economical electronic appliances has gained popularity and given rise to requirements for passive devices to be fabricated in the form of an array, a network, and a built-in passive device. Such passive devices sense, monitor, transmit, reduce, and control voltage.

Resistors as passive devices may suppress a flow of electric charge current, thereby controlling the amount of current. Such passive devices may be classified as a thin film resistor, in which a metal layer is thinly deposited to form a pattern, and an active layer resistor using an active layer area. Among these, the thin film resistor is generally positioned between metal lines of a semiconductor device.

FIGS. 1 and 2are sectional views of a semiconductor device including a thin film resistor pattern according to the related art. Referring toFIG. 1, a semiconductor device includes a first insulation layer21disposed on a semiconductor substrate10, lower metal lines30and31disposed on the first insulation layer21, and a thin film resistor pattern40connecting the lower metal lines30and31to each other.FIG. 1illustrates a simple process in which the thin film resistor pattern40is directly formed after the lower metal lines30and are formed. However, the thin film resistor pattern40is generally formed using a sputtering process. Thus, it is difficult to uniformly form the thin film resistor pattern40on edge portions of the lower metal lines30and31because the thin film resistor pattern40has a thickness of at least about an order of magnitude less than that of each of the lower metal lines30and31. Thus, it is difficult to precisely form a thin film resistor by this process.

In the semiconductor device ofFIG. 2, a thin film resistor head contact pattern51and a thin film resistor head pattern52are formed on a thin film resistor pattern40, and the thin film resistor head pattern52and a via71are connected to each other. The semiconductor device ofFIG. 2a relatively complicated manufacturing process because four patterning and etching processes are required to form the thin film resistor40, thin film resistor head contact pattern51, thin film resistor head pattern52, and via71. Also, to prevent the thin film resistor pattern40from being damaged in the etching process, both dry and wet etching processes (oxide etch, HF-based) are performed. The HF-based process is used in a front end of the line (FEOL) process, but is not used in a back end of the line (BEOL) process. To prevent metallic contamination, equipment designated for patterning the thin film resistor is required.

Also, stress generated by a thermal expansion difference between the thin film resistor head pattern52and the thin film resistor pattern40may be increased as the thin film resistor head pattern52is increased in size. This may cause non-uniform resistance of the thin film resistor head pattern52and increase resistance dispersion.

SUMMARY

Embodiments of the present disclosure provide a semiconductor device including a thin film resistor pattern having a relatively stable resistance and a method of manufacturing the same.

In one embodiment, the semiconductor device may include a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line; a second insulation layer on the first insulation layer, the second insulation layer including a metal head pattern; a thin film resistor pattern on the metal head pattern; a third insulation layer on the thin film resistor pattern; an upper metal line on the third insulation layer; a first via passing through the first, second, and third insulation layers to connect the lower metal line to the upper metal line; and a second via passing through the third insulation layer and the thin film resistor pattern to connect the metal head pattern to the upper metal line.

In the semiconductor device according to an embodiment, a trench may be defined in the metal head pattern, and the second via is connected to the metal head pattern in the trench. Thus, a contact interface between the metal head pattern and the second via may have a regular profile. The semiconductor device according to the present disclosure may have stable resistance characteristics, and also any mismatch of the resistances of the metal head pattern and the second via may be reduced, minimized, or eliminated.

Also, in the method of manufacturing the semiconductor device according to an embodiment, the metal head pattern may be formed prior to the thin film resistor pattern, to reduce stress due to a thermal expansion difference between the metal head pattern and the thin film resistor pattern, thereby forming a relatively stable thin film resistor.

The details of various embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

DETAILED DESCRIPTION

Hereinafter, semiconductor devices and methods of manufacturing the same according to embodiments of the present disclosure will be described with reference to the accompanying drawings.

FIGS. 3 and 4are cross-sectional views of a semiconductor device according to one embodiment of the present disclosure.FIGS. 5 to 15are cross-sectional views illustrating various steps in a process of manufacturing a semiconductor device according to embodiments of the present disclosure.

Referring toFIG. 3, a semiconductor device according to an exemplary embodiment includes a first insulation layer200on a semiconductor substrate100. In exemplary embodiments, the first insulation layer200includes a lower metal line300. The semiconductor device also includes a second insulation layer400on the first insulation layer200, including metal head patterns510and520formed therein. A thin film resistor pattern600is on the metal head patterns510and520, and a third insulation layer700is on the thin film resistor pattern600. The semiconductor device also includes upper metal lines910and920a-bon the third insulation layer700. A first via810passes through the first, second, and third insulation layers200,400, and700, respectively, to connect the lower metal line300to the upper metal line910; and second vias820a-bpassing through the third insulation layer700and the thin film resistor pattern600to connect the metal head patterns510and520to the upper metal lines920a-b.

FIG. 4is a detailed cross-sectional view of the metal head patterns510and520, the thin film resistor pattern600, and the second vias820a-baccording to an embodiment.

The metal head patterns510and520include a first metal head pattern510on the first insulation layer200and a second metal head pattern520on an area adjacent to the first metal head pattern510. Although two metal head patterns510and520are illustrated inFIGS. 3 and 4, the present disclosure is not limited thereto. For example, two, three or more metal head patterns may be provided.

The metal head patterns510and520may comprise or consist essentially of at least one material selected from the group consisting of Ti, TiN, Al, Ta, TaN, W, Cu, and combinations thereof. Also, each of the metal head patterns510and520may have a width of about 0.1 μm to about 2 μm (e.g., 0.25 μm to 1.5 μm, 0.35 μm to 1.0 μm, or any value or range of values therein), but the present invention is not limited thereto.

Referring toFIGS. 3 and 4, the metal head patterns510and520and the second insulation layer400may have a same height or thickness as each other, but the present invention is not limited thereto. That is, each of the metal head patterns510and520may have a height or thickness less than that of the second insulation layer400, and the second insulation layer400may cover the metal head patterns510and520. Also, each of the metal head patterns510and520may have a trench T structure.

The thin film resistor pattern600is on the metal head patterns510and520. In some embodiments, the thin film resistor patterns600may be formed between the first metal head pattern510and the second metal head pattern520(e.g., in a layout or top-down view).

Also, the thin film resistor pattern600may correspond to the metal head patterns510and520. That is, the thin film resistor pattern600may vertically overlap the metal head patterns510and520. For example, the thin film resistor pattern600may be formed to include areas in which the metal head patterns510and520are formed, but the present invention is not limited thereto.

The thin film resistor pattern600may include openings for exposing top surfaces of the metal head patterns510and520. The entire top surfaces of the metal head patterns510and520or a portion of top surfaces of the metal head patterns510and520may be exposed by the openings. Also, the second vias820a-bmay be connected to the metal head patterns510and520through the openings.

As previously described above, a trench T may be formed in each of the metal head patterns510and520. The trench T can be exposed by an opening in the thin film resistor pattern600. Thus, each of the second vias820a-bmay be in or may extend into the trench T.

That is, in the semiconductor device according to an embodiment, each of the metal head patterns510and520may connect to the second vias820a-bin the trench T. Thus, a contact interface between each of the metal head patterns510and520and the second vias820a-bmay have a regular (e.g., cup-shaped) profile. In addition, the semiconductor device according to an embodiment may have stable resistance characteristics, and a mismatch thereof (e.g., at the interface[s] between the second via[s]820a-b, thin film resistor600and/or metal head pattern[s]510/520) may be reduced, minimized, or eliminated.

FIGS. 5 to 15are cross-sectional views illustrating an exemplary process of manufacturing a semiconductor device according to embodiments of the present disclosure. The manufacturing methods will be described with reference to the above-described semiconductor device.

Referring toFIG. 5, a first insulation layer200, including a lower metal line300, is formed on a semiconductor substrate100. The first insulation layer200may comprise or consist essentially of an oxide layer (e.g., a silane-based silicon dioxide, which may be doped with [i] fluorine or [ii] boron and/or phosphorous, and formed by chemical vapor deposition from a silicon source such as silane or tetraethyl-orthosilicate (TEOS) and an oxygen source such as dioxygen [O2] or ozone [O3], etc.), but the disclosure is not limited thereto. For example, the first insulation layer200may further comprise a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride) or oxycarbide (e.g., SiOC or SiOCH), or any other suitable insulating material known in the art.

The first insulation layer200may have a thickness of about 5,000 Å to about 10,000 Å(e.g., 6,000 Å to 8,000 Å, or any value or range of values therein), and may be formed using any method known in the art. For example, in some embodiments, the first insulating layer200may be formed by chemical vapor deposition (CVD), which may be plasma-assisted, plasma-enhanced, or high density plasma (HDP) CVD. Thereafter, an etch back or chemical mechanical polishing process may be performed to planarize the first insulation layer200.

Also, the first insulation layer200may be formed as a single layer or a plurality of layers (e.g., silicon nitride, silicon dioxide on silicon nitride, a silicon dioxide/fluorosilicate glass/silicon dioxide stack, etc.). For example, the first insulation layer200may include a first insulation sub-layer210and a second insulation sub-layer220on the semiconductor substrate100. Here, the first insulation sub-layer210may be a pre-metal-dielectric (PMD), and the second insulation sub-layer220may be an inter metal dielectric (IMD). Although not shown in the figures, the first insulation layer200may include a plurality of metal patterns (not shown), but the disclosure is not limited thereto. The metal patterns (not shown) may be regularly or irregularly formed.

Referring toFIGS. 6 and 9, a second insulation layer400, including metal head patterns510and520, may be formed on the first insulation layer200. For example, any suitable insulating material (e.g., silicon dioxide, silicon nitride, etc.) or combination of materials may be deposited on the first insulation layer200using any method known in the art (e.g., CVD, PVD, blanket deposition and patterning, etc.). The second insulation layer200may have a thickness of about 1,000 Å to about 5,000 Å, or any value or range of values therein.

Referring toFIG. 6, a photoresist pattern PR having openings corresponding to areas in which the metal head patterns will be formed, is formed on the second insulation layer400using a photolithography process. Thereafter, as shown inFIG. 7, an etching process is performed to etch portions of the second insulation layer400. Thereafter, the photoresist pattern (PR) is removed through an asking or stripping process.

Sequentially, referring toFIG. 8, a metal head material500is deposited on the etched area of the second insulation layer400. In the deposition process, the metal head material500may also be deposited on the etched second insulation layer400. For example, the metal head material500may be formed by depositing at least one material selected from the group consisting of Ti, TiN, Al, Ta, TaN, W, Cu, and combinations, alloys, and conductive compounds thereof through physical vapor deposition (PVD), chemical vapor deposition (CVD), or any other suitable method known in the art. For example, in some embodiments, the metal head layer500may comprise tungsten, aluminum or an aluminum alloy (e.g., Al with up to 4 wt. % Cu, up to 2 wt. % Ti, and/or up to 1 wt. % Si), and may be deposited by sputtering or CVD on a conventional adhesion and/or barrier layer (e.g., Ti and/or TiN, such as a TiN-on-Ti bilayer). In another embodiment, the metal head layer500may comprise copper, electroplated on a TaN-on-Ta bilayer (which may have a thin Cu, Ru, Ta or other seed metal layer thereon).

Thereafter, referring toFIG. 9, a process for planarizing the metal head material500is performed. For example, an etch back process or a chemical mechanical polishing (CMP) process may be used as the planarization process. In the planarization process, the metal head material500deposited in areas other than the etched area of the second insulation layer400is removed, and only the metal head material500deposited in the etched area of the second insulation layer400remains.

Thus, the second insulation layer400including the metal head patterns510and520may be manufactured. The metal head patterns510and520may serve as an etch stop layer in an etching process for forming the first via810and the second vias820a-b(FIGS. 3-4).

Referring toFIGS. 10 and 11, a thin film resistor pattern600is formed on the metal head patterns510and520.

A thin film resistor material610may be deposited on the second insulation layer400, including the metal head patterns510and520, using any suitable method known in the art, and then portions of the thin film resistor material610may be etched to form the thin film resistor pattern600(FIG. 11).

Materials ordinarily used as thin film resistor in the art may be used as the thin film resistor material610without specific limitations. For example, the thin film resistor material610may comprise or consist essentially of at least one compound selected from the group consisting of CrSi, NiCr, TaN, CrSi2, CrSiN, CrSiO, and combinations thereof, but the disclosure is not limited thereto. For example, the thin film resistor material610may be formed by depositing SiCr or NiCr on the second insulation layer400at a thickness of about 10 Å to about 1,000 Å (e.g., about 25 Å to about 500 Å, about 50 Å to about 400 Å, about 100 Å to about 350 Å, or any value or range of values therein) through a sputtering process.

Thereafter, a photoresist pattern (PR) is formed on the thin film resistor material610, and then a photolithography process and an etching process may be performed to form the thin film resistor pattern600.

The thin film resistor pattern600may vertically overlap the metal head patterns510and520under the thin film resistor pattern600. That is, the thin film resistor pattern600may be formed to correspond to the metal head pattern510and520. In some embodiments, the thin film resistor pattern600may be formed on the metal head patterns510and520. For example, the thin film resistor pattern600may include and thus overlap areas in which the metal head patterns510and520are formed, but the present disclosure is not limited thereto.

In the method of manufacturing the semiconductor device according to various embodiments of the present disclosure, the metal head patterns510and520may be deposited prior to the thin film resistor pattern600to reduce stress due to a thermal expansion difference between the metal head patterns510and520and the thin film resistor pattern600, thereby forming the relatively stable thin film resistor pattern600.

Referring toFIGS. 12 and 13, a third insulation layer700may be formed on the second insulation layer400and the thin film resistor pattern600, and a portion of the third insulation layer700may be etched to form a first via hole811and second via holes821a-b. The third insulation layer700may comprise or consist essentially of any suitable insulating material known in the art (e.g., silicon dioxide, which may be doped with [i] fluorine or [ii] boron and/or phosphorous, silicon nitride, combinations thereof, etc.), and can be formed using any method known in the art (e.g., CVD, PVD, blanket deposition and etching, etc.).

For example, a photoresist layer (PR) having openings corresponding to the lower metal line300and the metal head patterns510and520is formed on the third insulation layer700, and a photolithography process and an etching process are performed. The third insulation layer700, the second insulation layer400, and a portion of the first insulation layer200are etched through the opening corresponding to the lower metal line300to form the first via hole811exposing a top surface of the lower metal line300. Simultaneously, the third insulation layer700and the thin film resistor pattern600are etched through the opening corresponding to each of the metal head patterns510and520to form the second via hole821exposing each of the metal head patterns510and520. In some embodiments, depending on the etch selectivity of thin film resistor material610, one or more of the second via holes820a-bmay not completely penetrate the thin film resistor600. In the process for forming the second via holes821a-b(FIG. 14), a portion of each of the metal head patterns510and520may be etched to form the trench T, but the invention is not limited thereto. After the etching process is completed, the photoresist pattern PR is removed, for example, through an asking or stripping process.

Each of the first and second via holes811and821a-bformed by the above-described method may have a width of about 0.5 μm or more and a depth of about 1,000 Å to about 9,000 Å.

Referring toFIGS. 14 and 15, a metal material is deposited into the first and second via holes811and821a-bto form a first via810and second vias820a-b. The metal material may also be deposited into the trench T formed in each of the metal head patterns510and520to form the second vias820a-bwithin the trench T. The metal material may comprise any conductive or conventional via material known in the art (e.g., tungsten, doped silicon, aluminum, copper, etc.), and the metal material may be deposited using any suitable method known in the art for depositing such metal material to form a via.

Thus, in the method of manufacturing the semiconductor device according to an embodiment, a contact interface between each of the metal head patterns510and520and the second vias820a-bmay have a regular profile. In addition, the semiconductor device according to the present disclosure may have relatively stable resistance characteristics, and also a mismatch thereof (e.g., at the interface[s] between the second via[s]820a-b, thin film resistor600and/or metal head pattern[s]510/520) may be reduced, minimized, or eliminated.

A planarization process may be additionally performed after the metal material is deposited, but the invention is not limited thereto. Sequentially, as shown inFIG. 15, upper metal lines910and920a-bmay be formed on the first and second vias810and820a-b. The upper metal lines910and920a-bmay include various conductive materials such as metals, alloys and/or conductive compounds such as metal nitrides and/or silicides. For example, the upper metal lines910and920a-bmay include aluminum, copper, titanium, tungsten and the like. The upper metal lines910and920a-bmay be formed using any suitable method known in the art (e.g., blanket deposition and patterning). One portion of the upper metal line910may be connected to the lower metal line300through the first via810, and another portion of the upper metal lines920a-bmay be connected to the metal head patterns820a-band the thin film resistor pattern600through the second vias820a-b.