INFORMATION PROCESSING SYSTEM

An information processing system includes a first information processing device, second information processing devices, and a relay device. The second information processing devices each include a second connector connected to the relay device, and a first restarter that restarts the second information processing devices. The relay device communicably connects the first and second information processing devices and includes a power supply control unit for power supply to the first and second information processing devices during restart of the relay device, and a second restarter that restarts the relay device in response to detection of a communication failure. The first information processing device includes a hot pluggable, first connector connected to the relay device, a first detector that detects restart of the relay device, and an initializer that initializes settings relating to communications via the relay device in response to detection of the relay device by the first detector.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Applications No. 2019-155024 and No. 2019-161497, both filed on Sep. 4, 2019, the entire contents of all of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to an information processing system.

BACKGROUND

Conventionally, information processing systems have been proposed, which include a plurality of information processing devices to be connected to a relay device for data communications among the information processing devices.

Among such information processing systems, a single device incorporating both a plurality of information processing devices and a relay device is available, in which the information processing device communicates with one another via the relay device. Such an information processing system includes various types of information processing devices depending on data to process. In the information processing system, the relay device may be restarted at the time of occurrence of a failure. In such a case, the information processing devices in the information processing system are to perform processing such as initialization in response to the restart of the relay device, in order to continue mutual communications via the relay device.

However, the information processing system includes various kinds of information processing devices that support or do not support hot plugging (for example, hot plug detect (HPD)), therefore, the information processing system is to be perform processing suitable for the various kinds of information processing devices, at the time of restart of the relay device.

SUMMARY

An information processing system according to one or more embodiments enables information processing devices to continuously communicate with one another via a relay device.

According to one or more embodiments, an information processing system includes a first information processing device including a first connector that supports hot plugging representing insertion and removal at the time of power-on; a plurality of second information processing devices; and a relay device that communicably connects the first information processing device and the second information processing devices. The second information processing devices each include second connector to be connected to the relay device, and a first restarter that restarts the second information processing devices. The relay device includes a power supply control unit that supplies power to the first information processing device and the second information processing devices during restart of the relay device, and a second restarter that restarts the relay device in response to detection of a communication failure. The first information processing device includes the first connector to be connected to the relay device, a first detector that detects the restarted relay device, and an initializer that initializes settings relating to communications via the relay device in response to detection of the relay device by the first detector.

DETAILED DESCRIPTION

Embodiments of an information processing system will be described below in detail with reference to the accompanying drawings. The embodiments are presented for illustrative purpose only and not intended to limit the scope of the present invention.

FIG. 1is a diagram illustrating an exemplary overall configuration of a computer1including a built-in relay device according to one or more embodiments. The computer1with a built-in relay device serves as an information processing system and includes a platform10-1, a plurality of platforms10-2to10-8, and a relay device30. The platform10-1includes an interface hot pluggable, that is, insertable and removable at the time of power-on. The platform10-1and the platforms10-2to10-8are communicably connected to one another via the relay device30. As illustrated inFIG. 1, the computer1of one or more embodiments includes the platforms10-1to10-8and the relay device30.

The platforms10-1to10-8are mutually connected via the relay device30in a communicable manner. The platforms10-1to10-8are inserted into, for example, slots on a board on which the relay device30is mounted. Any of the slots can be vacant with no platforms10-1to10-8inserted thereto. In the following, the platforms10-1to10-8will be referred to as platform or platforms10unless the platforms10-1to10-8are to be distinguished from each other.

The platform10-1is an exemplary first information processing device. The platform10-1serves as a main information processing device and controls the platforms10-2to10-8to execute various kinds of process.

The platform10-1is connected to a monitor21and an input device22. The monitor21serves to display a variety of screens such as a liquid crystal display device. The input device22is exemplified by a keyboard and a mouse, and receives various operations.

The platforms10-2to10-8are an exemplary second information processing device. The platforms10-2to10-8serve as subordinate information processing devices and execute, for example, artificial intelligence (AI) inference and image processing in response to a request from the platform10-1. The platforms10-2to10-8may include individually different functions, or every two or more of the platforms10-2to10-8may include different functions.

The platforms10-1to10-8include root complexes (RC)11-1to11-8operable as a host. In the following, the root complexes11-1to11-8will be referred to as root complex or root complexes11unless the root complexes11-1to11-8are to be distinguished from each other.

The root complexes11work to communicate with endpoints30-1to30-8of the relay device30. That is, the platforms10and the relay device30are communicably connected to each other in compliance with a communications standard such as peripheral component interconnect express (PCIe). The platforms10and the relay device30may be mutually connected by another communication standard in addition to by PCIe.

The relay device30includes endpoints (EPs)30-1to30-8. The relay device30relays communications among the platforms10including the root complexes11connected to the endpoints30-1to30-8.

The endpoints30-1to30-8serve to execute communications with the root complexes11of the platforms10. In the following, the endpoints30-1to30-8will be referred to as endpoint or endpoints30unless the endpoints30-1to30-8are to be distinguished from each other.

Next, the hardware configuration of the respective elements of the computer1with a built-in relay device will be described.FIG. 2is a diagram illustrating an exemplary hardware configuration of the respective elements of the computer1with a built-in relay device. Herein, the hardware configuration of the platform10-1will be described as an example. The platforms10-2to10-8have the same configuration as the platform10-1.

The platform10-1represents a computer which performs computations such as AI processing and image processing. The platform10includes the root complex11-1, a processor12-1, a memory13-1, a storage14-1, and a communicator15-1, which are communicably connected to one another via a bus.

The processor12-1serves to control the entire platform10-1. The processor12-1may be a multiprocessor. Further, the processor12-1may be, for example, any of a central processing unit (CPU), a micro processing unit (MPU), a graphics processing unit (GPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), and a field programmable gate array (FPGA). The processor12may be a combination of two or more of a CPU, a MPU, a GPU, a DSP, an ASIC, a PLD, and a FPGA. In the following, the processors12-1to12-8will be referred to as processor or processors12unless the processors12-1to12-8are to be distinguished from each other.

The memory13-1serves as a storage memory including a read only memory (ROM) and a random access memory (RAM). The ROM of the memory13-1contains various software programs and data for use on the programs. The processor12reads and executes the software programs from the memory13-1when appropriate. The RAM of the memory13-1is used as a primary storage memory or a working memory. In the following, the memories13-1to13-8will be referred to as memory or memories13unless the memories13-1to13-8are to be distinguished from each other.

The storage14-1represents a storage device such as a hard disk drive (HDD), a solid state drive (SSD), and a storage class memory (SCM), and stores various kinds of data. For example, the storage14-1stores various kinds of software programs. In the following, the storages14-1to14-8will be referred to as storage or storages14unless the storage14-1to14-8are to be distinguished from each other.

In the platform10, the processor12executes the software programs stored in the memory13and the storage14, thereby implementing various functions.

The various software programs may not be stored in the memory13or the storage14. For example, the platform10may read and execute an information processing program from a storage medium readable by a medium reader. Examples of the storage medium readable by the platforms10include a portable recording medium such as a CD-ROM, a DVD disk, a universal serial bus (USB) memory, a semiconductor memory such as a flash memory, or a hard disk drive. Alternatively, the information processing program may be stored in a device connected to a public line, the Internet, a LAN, or the like, and the platform10may read and execute the information processing program from the device.

The communicator15-1serves as an interface for communicating with the power supply control unit40. For example, the communicator15-1performs communications in compliance with a communication standard as an inter-integrated circuit (I2C). In the following, the communicators15-1to15-8will be referred to as communicator or communicators15unless the communicators15-1to15-8are to be distinguished from each other.

The relay device30will now be described. The relay device30includes the endpoints30-1to30-8corresponding to the respective platforms10, a processor32, a memory33, a storage34, an internal bus35, a PCIe bus36, and a power supply control unit40. In the following, the endpoints30-1to30-8will be referred to as endpoint or endpoints30unless the endpoints30-1to30-8are to be distinguished from each other.

The endpoints30are provided for the respective platforms10and serve to transmit and receive data. For example, the endpoint30receives data from the connected platform10and transmits the received data to the endpoint30connected to another platform10being a destination via the PCIe bus36.

The root complex11transmits data to another platform10by direct memory access (DMA) transfer, for example. The endpoint30receives data from another endpoint connected to the platform10being a transmission source via the PCIe bus36, and transmits the received data to the connected platform10.

The processor32serves to control the entire relay device30. The processor32may be a multiprocessor. Further, the processor32may be, for example, any of a CPU, a MPU, a GPU, a DSP, an ASIC, a PLD, and a FPGA. The processor32may be a combination of two or more of a CPU, a MPU, a GPU, a DSP, an ASIC, a PLD, and a FPGA.

The memory33represents a storage device including a ROM and a RAM. The ROM contains various kinds of software programs and data for use on the software programs. The processor32reads and executes the programs from the memory33. The RAM is used as a working memory.

The storage34represents a storage device such as a hard disk drive, a SSD, or a storage class memory, and stores various kinds of data. For example, the storage34stores various software programs.

The internal bus35communicably connects the processor32, the memory33, the storage34, and the PCIe bus36to one another.

The PCIe bus36serves to communicably connect the endpoints30and the internal bus35. That is, the PCIe bus36connects the endpoints30to one another to allow data transfer thereamong. The PCIe bus36is, for example, a bus compliant with the PCIe standard.

The power supply control unit40serves to control power supply to the platforms10. The power supply control unit40represents, for example, an integrated circuit such as a microcomputer or a microcontroller. The power supply control unit40supplies power to the platforms10during restart of the relay device30. The power supply control unit40is connected to the platform10-1and the processor32of the relay device30.

The hardware configuration of the power supply control unit40will now be described.FIG. 3is a diagram illustrating an exemplary hardware configuration of the power supply control unit40.

The power supply control unit40includes a processor41, a memory42, a first connector43, and a second connector44. The processor41, the memory42, the first connector43, and the second connector44are communicably connected to one another via a bus45.

The processor41serves to control the entire power supply control unit40. The processor41may be a multiprocessor. The processor41may be, for example, any of a CPU, a MPU, a GPU, a DSP, an ASIC, a PLD, and a FPGA. Further, the processor41may be a combination of two or more of a CPU, a MPU, a GPU, a DSP, an ASIC, a PLD, and a FPGA.

The memory42represents a storage device including a ROM and a RAM. The ROM contains various kinds of software programs and data for use on the software programs. The processor41reads and executes the programs from the memory42. Further, the RAM is used as a working memory.

The first connector43serves as an interface for connecting to the platform10-1. The first connector43is exemplified by an I2C interface.

The second connector44serves as an interface for connecting to the processor32of the relay device30. For example, the second connector44is connected to the processor32via a general-purpose input output (GPIO).

The following will describe an exemplary communication process between the platform10-1and the platform10-2both connected to the relay device30.FIG. 4illustrates an exemplary communication process among the platforms10according to one or more embodiments. Herein, the communication process between the platform10-1and the platform10-2will be described by way of example. The other platforms10perform communications in the same or like manner as the platform10-1and the platform10-2.

As illustrated inFIG. 4, the computer1with a built-in relay device includes a layer structure defined by the PCIe standard, for example. The computer1with a built-in relay device establishes communications among the platforms10through the respective layers.

The platform10-1serving as a transmission source transfers software-designated data to the physical layer (PHY) of the relay device30through a transaction layer, a data link layer, and a physical layer (PHY).

The relay device30receives the data from the platform10-1being a transmission source and sends it to the transaction layer via the physical layer (PHY) and the data link layer. In the transaction layer the relay device30transfers the data to the endpoint30corresponding to the platform10-2being a destination by tunneling. The relay device30transfers the data to the physical layer (PHY) of the platform10-2being a destination through the transaction layer, the data link layer, and the physical layer (PHY). In this manner, the relay device30transfers the data from a transmission source, i.e., the platform10-1to a destination i.e., the platform10-2by tunneling the data between the endpoints30.

In the platform10-2being a destination, the data is transferred to the software through the physical layer (PHY), the data link layer, and the transaction layer.

Unless the data transfer concentrates on one of the platforms10connected to the relay device30, data is transferrable in parallel between any different combinations of the platforms10.

To establish communication from the platform10-2and the platform10-3to the platform10-1, for example, the relay device30performs communications with the platform10-2and the platform10-3in serial. While the different platforms10are in communication with each other and the communication is not concentrating on the specific platform10, the relay device30performs communications among the platforms10in parallel.

The following will describe the characteristic functions of the respective elements of the computer1with a built-in relay device of one or more embodiments.FIG. 5is a functional block diagram illustrating an example of functions of the respective elements included in the computer1with a built-in relay device.

The processor12-1of the platform10-1implements the functions illustrated inFIG. 5by executing the programs stored in the memory13-1and the storage14-1. Specifically, the processor12-1includes a communication controller1011, a connection detector1012, an initialization controller1013, a status acquirer1014, and a display setter1015as functional elements.

The communication controller1011is an exemplary first connector. The communication controller1011controls the root complex11-1to establish communications with the platforms10-2to10-8via the relay device30. That is, the communication controller1011connects to the relay device30. Then, the communication controller1011receives and transmits data from and to the relay device30. The platform10-1is set as a device supporting HPD in system basic input output system (BIOS). That is, the communication controller1011is hot pluggable, that is, insertable or removable at the time of power-on. The platform10-1can thus communicate with the relay device30while inserted or removed at the time of power-on.

The connection detector1012is an exemplary first detector. The connection detector1012detects the connection of the relay device30. The connection detector1012detects, for example, restart of the relay device30when it occurs.

The initialization controller1013is an exemplary initializer. In response to detection of the relay device30by the connection detector1012, the initialization controller1013initializes settings as to the communications via the relay device30. Specifically, the initialization controller1013initializes various settings in response to detection of the connection of the relay device30by BIOS. For example, the initialization controller1013initializes a base address register (BAR), an interrupt register, and other registers.

The status acquirer1014acquires information representing that the relay device30is restarted. Specifically, the status acquirer1014controls the communicator15-1to request the power supply control unit40to send an error status indicating the restart of the relay device30. Then, the status acquirer1014acquires the error status, which is transmitted from the relay device30as a response.

The connection between the platform10and the relay device30can be also disconnected through “device and printer” of the Windows (registered trademark) control panel. In view of this, the display setter1015switches the display to the non-display by directly rewriting a registry value in an INF file. Thereby, the display setter1015prevents the connection between the platform10and the relay device30from being disconnected. That is, the display setter1015enables the platforms10to continue their communications via the relay device30.

The relay device30will now be described.

The processor32of the relay device30implements the functions illustrated inFIG. 5by executing the programs stored in the memory33and the storage34. Specifically, the processor32includes a relay controller3001, a failure detector3002, a restart controller3003, and a message controller3004as functional elements.

The relay controller3001serves to control the communications among the platforms10. Specifically, the relay controller3001controls data transfer among the platforms10as illustrated inFIG. 4.

The failure detector3002detects a failure in the communications among the platforms10, when it occurs. For example, the failure detector3002detects a failure when communications are not established within a given period.

The restart controller3003is an exemplary second restarter. The restart controller3003serves to restart the relay device30in response to detection of a communication failure by the failure detector3002.

The power supply control unit40will now be described.

The processor41of the power supply control unit40implements the functions illustrated inFIG. 5by executing the programs stored in the memory42, for example. Specifically, the processor41includes a power controller4001, a restart detector4002, and a status controller4003as functional elements.

The power controller4001serves to control power supply to the platforms10. The power controller4001supplies power to the platforms10at the time of restart of the relay device30.

The restart detector4002is an exemplary second detector. The restart detector4002detects the restart of the relay device30. Specifically, the restart detector4002receives information representing the restart of the relay device30via the second connector44. For example, the restart detector4002receives, via GPIO, a flag indicating the restart of the relay device30at the time of start-up of firmware (FW).

In response to receipt of a request for the information representing the restart of the relay device30, the status controller4003transmits information indicating status change in the relay device30via the first connector43. That is, in response to receiving a request for an error status indicating the restart of the relay device30, the status controller4003transmits an error status as a response via the I2C.

The platforms10-2to10-8will now be described.

The processors12-2to12-8of the platforms10-2to10-8implement the functions illustrated inFIG. 5by executing the programs stored in the memories13-2to13-8and the storages14-2to14-8. Specifically, the processors12-2to12-8each include a communication controller1021, a restart controller1022, and an initialization controller1023as functional elements.

The communication controller1021is an exemplary second connector. The communication controller1021serves to control the root complexes11-2to11-8to communicate with the platforms10via the relay device30. That is, the communication controller1021is connected to the relay device30. The communication controller1021transmits and receives data to and from the relay device30.

The restart controller1022is an exemplary first restarter. The restart controller1022serves to restart the platforms10-2to10-8. Specifically, the restart controller1022causes the corresponding one of the platforms10-2to10-8to restart if a failure occurs therein.

Along with the restart of the platforms10-2to10-8, the initialization controller1023initializes the platforms10-2to10-8. Specifically, the initialization controller1023loads a driver. The initialization controller1023initializes registers such as BAR and allocates base addresses thereto.

The following will describe a recovery process. FIG. is a sequence diagram illustrating an exemplary recovery process in one or more embodiments. The recovery process refers to a process for recovering the communications among the platforms10via the relay device30from a communication failure.

The respective elements of the computer1with a built-in relay device are in a running state (Step S1).

The respective elements of the computer1with a built-in relay device establish communications thereamong via the relay device30(Step S2). For example, the communication controller1011of the platform10-1being a transmission source designates the platforms10-2to10-8to be a destination and transmits transmit data to the relay device30. The relay controller3001of the processor32in the relay device30transmits the transmit data to the designated platforms10-2to10-8. The communication controllers1021of the platforms10-2to10-8being a destination receive the transmit data.

A bus fault occurs in the failure detector3002of the processor32. (Step S3). That is, the PCIe bus36of the failure detector3002has a communication failure.

The failure detector3002of the processor32transmits a bus transaction error to the platform10-1(Step S4). That is, the failure detector3002transmits thereto a notice that a communication error has occurred between the platforms10.

The restart controller3003of the processor32restarts the relay device30(Step S5). The restart controller3003initializes various settings (Step S6).

After completion of the restart in Step S6, the restart controller3003of the processor32transmits a startup-completion notice (Step S7). Specifically, the restart controller3003validates a startup completion signal to transmit the startup-completion notice.

The restart detector4002of the power supply control unit40detects the restart of the processor32from the startup-completion notice (Step S9). The restart detector4002of the power supply control unit40transmits a detection notice indicating the restart of the processor32to the platforms10-2to10-8(Step S10).

The restart controller3003of the processor32ends transmitting the startup-completion notice (Step S11). Specifically, the restart controller3003invalidates the startup completion signal to end the transmission of the startup-completion notice.

The platform10-1and the relay device30are placed in PCIe link-up (Step S12). That is, the platform10-1and the relay device30are communicably connected to each other by PCIe.

The connection detector1012of the platform10-1detects connection to the relay device30after completion of the restart of the processor32(Step S14).

The initialization controller1013of the platform10-1executes BIOS initialization (Step S15). That is, the initialization controller1013initializes registers and allocates base addresses thereto.

The initialization controller1013of the platform10-1initializes the driver (Step S16).

After detecting the restart of the processor32, the restart controllers1022of the platforms10-2to10-8start a restart process of the corresponding platforms (Step S17). In response to an occurrence of communication failure in the corresponding platform, for example, the restart controller1022executes a restart process.

The restart controllers1022of the platforms10-2to10-8start up, following the restart in Step S3(Step S18).

The initialization controllers1023of the platforms10-2to10-8load the driver (Step S19). The initialization controllers1023initialize registers (Step S20). That is, the initialization controllers1023allocate base addresses thereto.

The relay device30and the platforms10-2to10-8are placed in PCIe link-up (Step S21). That is, the platforms10-2to10-8and the relay device30are communicably connected to each other by PCIe.

The message controller3004of the processor32issues a DRS message (Step S22).

The respective elements of the computer1with a built-in relay device are in a running state (Step S23).

The status acquirer1014of the platform10-1issues an error status request (Step S24).

Responding to the error status request, the status controller4003of the power supply control unit40transmits an error status (Step S25).

As described above, the computer1with a built-in relay device according to one or more embodiments includes the platforms10-1to10-8communicably mutually connected via the relay device30. Among the platforms10-1to10-8, at least the platform10-1supports HPD. However, any of the platforms10-2to10-8does not support HPD. In such a case, in response to occurrence of a communication failure via the relay device30due to the restart of the platforms10-2to10-8, the relay device30restarts itself. This is equivalent to a hot pluggable state of the connected platforms10and relay device30. After detecting the restart of the relay device30, the platform10-1initializes the settings relating to the communications established via the relay device30, such as drivers and register values. Thereby, the computer1with a built-in relay device enables the platforms10to communicate with one another via the relay device30without restarting the platform10-1. Thus, the computer1with a built-in relay device can continue the communications via the relay device30.

The above embodiments have described PCIe as an example of bus (for example, expansion bus) or I/O interface for each element, however, the bus or I/O interface is not limited to PCIe. For example, the bus or I/O interface for each element may be a data transfer bus through which data is transferrable between the device (peripheral controller) and the processor. The data transfer bus may be a general-purpose bus through which data is transferrable at a higher speed in a local environment in one housing, such as one system or one device. The I/O interface may be either a parallel interface or a serial interface.

In the case of serial transfer, the I/O interface may be point-to-point connectable and able to transfer data on a packet basis. In the case of serial transfer, the I/O interface may have a plurality of lanes. The layer structure of the I/O interface may include a transaction layer for packet generation and decoding, a data link layer for error detection, and a physical layer for serial and parallel conversion. Further, the I/O interface may include a root complex of uppermost hierarchy with one or more ports, an endpoint serving as an I/O device, a switch for increasing the number of ports, and a bridge serving to convert a protocol. The I/O interface may use a multiplexer to multiplex transmit data and a clock signal for transmission. In this case, the receive side may use a demultiplexer to separate the data and the clock signal.

The information processing system of one or more embodiments can prevent the information processing devices from becoming non-communicable via the relay device.