SELF-DIAGNOSIS CIRCUIT AND SEMICONDUCTOR DEVICE

A self-diagnosis circuit (BST1) configured to diagnose a fault detection circuit (20) including a first comparator (CMP1) configured to be fed with a voltage based on a fault sensing target voltage (Vo1) and a first reference voltage (Vref1) includes a voltage switch circuit (50) configured to switch the level of a voltage based on a second reference voltage (Vref2) and output the resulting voltage, a first path switch circuit (51) configured to switch between a path through which the voltage output from the voltage switch circuit is fed to the first comparator and a path through which the voltage based on the fault sensing target voltage is fed to the first comparator, and a control circuit (15) configured to control the voltage switch circuit and the path switch circuit.

TECHNICAL FIELD

The present disclosure relates to a self-diagnosis circuit.

BACKGROUND ART

Conventionally, various types of ICs such as power supply ICs often have fault detection/protection functions. Examples of such functions include an undervoltage detection/protection function for the output voltage of a power supply circuit, an overvoltage detection/protection function for the output voltage, an undervoltage detection/protection function (UVLO) for the supply voltage to an IC, and an overheat detection/protection function (TSD) for an IC chip (see Patent Document 1 for one example of the UVLO function).

LIST OF CITATIONS

Patent Literature

SUMMARY OF THE INVENTION

Problem to be Solved by the Invention

Nowadays, in vehicle-mounted equipment and the like, a self-diagnosis (BIST: built-in self test) function is gaining importance. Thus, ICs are expected to have a self-diagnosis function for diagnosing whether a fault detection/protection function as mentioned above is functioning normally.

In view of the situation described above, the present disclosure is aimed at providing a self-diagnosis circuit that can provide an effective configuration for diagnosing whether a circuit for detecting a fault is functioning normally.

Means for Solving the Problem

According to one aspect of what is disclosed herein, a self-diagnosis circuit is configured to diagnose a fault detection circuit that includes a first comparator configured to be fed with a voltage based on a fault sensing target voltage and a first reference voltage, and includes a voltage switch circuit configured to switch the level of a voltage based on a second reference voltage and output the resulting voltage, a first path switch circuit configured to switch between a path through which the voltage output from the voltage switch circuit is fed to the first comparator and a path through which the voltage based on the fault sensing target voltage is fed to the first comparator, and a control portion configured to control the voltage switch circuit and the path switch circuit.

Advantageous Effects of the Invention

With a self-diagnosis circuit according to the present disclosure, it is possible to provide an effective configuration for diagnosing whether a circuit for detecting a fault is functioning properly.

DESCRIPTION OF EMBODIMENTS

1. Comparative Example

Prior to a description of embodiments of the present disclosure, first a description will be given of a comparative example to be compared with the embodiments of the present disclosure. The description of the comparative example will help clarify the significance of the present disclosure.

FIG.6is a diagram showing a configuration of a fault detection circuit according to the comparative example.FIG.6shows a configuration of an undervoltage sense circuit101as a fault detection circuit.FIG.6shows, in addition to the fault detection circuit, also a configuration of a self-diagnosis circuit BST101. The circuit configuration shown inFIG.6is included in a power supply IC. The power supply IC has a DC-DC converter function.

The undervoltage sense circuit101is a circuit for detecting an undervoltage in an output voltage Vo (a DC output voltage) produced by the above-mentioned DC-DC converter function. Specifically, the undervoltage sense circuit101includes a comparator CMP11, an inverter IV11, resistors R11to R15, and an NMOS transistor (n-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) NM11.

One terminal of the resistor R11is connected to an FB terminal. The FB terminal is fed with the output voltage Vo. The other terminal of the resistor R11is, at a node N11, connected to one terminal of the resistor R12. The node N11is connected to the non-inverting input terminal (+) of the comparator CMP11. One terminal of the resistor R13is connected to an application terminal for a reference voltage Vref. The other terminal of the resistor R13is, at a node N13, connected to one terminal of the resistor R14. The node N13is connected to the inverting input terminal (−) of the comparator CMP11. The output terminal of the comparator CMP11is, at a node N15, connected to the input terminal of the inverter IV11. The node N15is connected to the gate of the NMOS transistor NM11. The source of the NMOS transistor NM11is connected to an application terminal for the ground potential. The drain of the NMOS transistor NM11is connected to a node N14to which the other terminal of the resistor R14and one terminal of the resistor R15are connected. The other terminal of the resistor R15is connected to the application terminal for the ground potential.

The self-diagnosis circuit BST101includes an NMOS transistor NM12, a resistor R16, and a control logic circuit100. One terminal of the resistor R16is, at a node N12, connected to the other terminal of the resistor R12. The other terminal of the resistor R16is connected to the application terminal for the ground potential. The drain of the NMOS transistor NM12is connected to the node N12. The source of the NMOS transistor NM12is connected to the application terminal for the ground potential. The control logic circuit100applies a BIST signal Bst12, as a gate signal, to the gate of the NMOS transistor NM12.

During normal operation, the BIST signal Bst12is low, and the NMOS transistor NM12is off. Thus, a comparator input signal CMP11INp that appears at the node N11as a result of the output voltage Vo being divided with the resistors R11, R12, and R16is fed to the non-inverting input terminal (+) of the comparator CMP11.

The NMOS transistor NM11and the resistor R15serve to produce hysteresis. Specifically, when the output of the comparator CMP11is low, the NMOS transistor NM11is off, and a comparator input signal CMP11INn that appears at the node N13as a result of the reference voltage Vref being divided with the resistors R13to R15is fed to the inverting input terminal (−) of the comparator CMP11. When the output of the comparator CMP11is high, the NMOS transistor NM11is on, and a comparator input signal CMP11INn that appears at the node N13as a result of the reference voltage Vref being divided with the resistors R13and R14is fed to the inverting input terminal (−) of the comparator CMP11.

When the comparator input signal CMP11INp exceeds the comparator input signal CMP11INn to turn the output of the comparator CMP11to high level, an undervoltage sense signal UVD, which is the output of the inverter IV11, turns to low level. By contrast, when the comparator input signal CMP11INp is equal to or lower than the comparator input signal CMP11INn and the output of the comparator CMP11is low, the undervoltage sense signal UVD is high. The undervoltage sense signal UVD is fed to the control logic circuit100and, based on the undervoltage sense signal UVD being high, the control logic circuit100judges that the output voltage Vo is in an undervoltage fault state and performs protection operation.

In a BIST mode (diagnosis mode), the control logic circuit100outputs the BIST signal Bst12at different (low and high) levels alternately. When the BIST signal Bst12is low, the NMOS transistor NM12is off; thus, a comparator input signal CMP11INp that appears at the node N11as a result of the output voltage Vo being divided with the resistors R11, R12, and R16is fed to the non-inverting input terminal (+) of the comparator CMP11.

When the BIST signal Bst12is high, the NMOS transistor NM12is on; thus, a comparator input signal CMP11INp that appears at the node N11as a result of the output voltage Vo being divided with the resistors R11and R12is fed to the non-inverting input terminal (+) of the comparator CMP11.

Thus, while the comparator CMP11is operating normally, after the power supply IC starts up and the output voltage Vo rises, in the BIST mode, if the BIST signal Bst12is low, the output of the comparator CMP11is high, and the undervoltage sense signal UVD is low. By contrast, in the BIST mode, if the BIST signal Bst12is high, the output of the comparator CMP11is low, and the undervoltage sense signal UVD is high.

In this way, the self-diagnosis circuit BST101can forcibly change the level of the comparator input signal CMP11INp and sense whether the level of the undervoltage sense signal UVD changes to judge whether the undervoltage sense circuit101is operating normally.

However, the self-diagnosis operation described above is to be performed after the output voltage Vo has risen up and stabilized. In that case, the self-diagnosis operation takes a certain time; thus, if there is a fault in the fault detection function, before a fault in the fault detection function is found by self-diagnosis and the IC is shut down, an abnormal output voltage Vo may be output.

One possible solution is to perform the self-diagnosis operation before the output voltage Vo rises up. In this case, when there is a fault in the fault detection function, the IC can be shut down without raising the output voltage Vo. However, the output voltage Vo is left indefinite in accordance with the timing at which the IC starts up, and, depending on the output voltage Vo, the self-diagnosis operation may not operate properly. For example, when the output voltage Vo is 0 V during start-up, with the configuration shown inFIG.6, switching the level of the BIST signal Bst12only makes the comparator input signal CMP11INp OV; thus, it is not possible to switch the output logic level of the comparator CMP11. That is, the self-diagnosis operation cannot be performed.

In view of the above problems found out through an unparalleled study, the present inventors have devised a configuration that permits self-diagnosis operation regardless of the value of a fault sensing target voltage (the output voltage Vo in the example inFIG.6) as the target of fault sensing by a fault detection circuit. Now, embodiments of the present disclosure will be described.

2. Configuration of a PMIC

Here, a configuration of a PMIC (power management IC) according to an exemplary embodiment of the present disclosure will be described.FIG.1is a diagram showing a configuration with respect to the external connection of the PMIC1according to the exemplary embodiment of the present disclosure.FIG.2is a diagram showing an internal configuration of the PMIC1.

The PMIC1shown inFIGS.1and2is a semiconductor device (power supply IC package) including a plurality of power supply circuits for supplying electric power to a vehicle-mounted CMOS sensor device30. The CMOS sensor device30is incorporated in a vehicle-mounted camera system.

As shown inFIG.1, the PMIC1has, as external terminals for establishing electrical connection with the outside, a VIN terminal, a VREG50terminal, a VREG15terminal, a BOOT1terminal, an SW1terminal, a PGND1terminal, an FB1terminal, an FB2terminal, a PVIN2terminal, an SW2terminal, a PGND23terminal, an SW3terminal, a PVIN3terminal, an FB3terminal, a VO4terminal, a RSTOUT terminal, a WAROUT terminal, an SCL terminal, an SDA terminal, and a GND terminal.

As shown inFIG.2, the PMIC1includes an internal voltage generator2, an internal voltage generator3, a reference voltage generator4, a supply voltage UVLO (undervoltage lock-out) circuit5, an internal voltage UVLO circuit6, an internal voltage UVLO circuit7, an OTP (one-time programmable ROM)8, a TSD (thermal shutdown) circuit9, a TW (thermal warning) circuit10, a first DC-DC circuit11, a second DC-DC circuit12, a third DC-DC circuit13, an LDO (low dropout)14, a control logic circuit15, an I2C input/output circuit16, a reset input/output circuit17, and a warning input/output circuit18.

The PMIC1further includes, as shown inFIG.2, a first overvoltage sense circuit19, a first undervoltage sense circuit20, a second overvoltage sense circuit21, a second undervoltage sense circuit22, a second undervoltage protection circuit23, a third overvoltage sense circuit24, a third undervoltage sense circuit25, a third undervoltage protection circuit26, a fourth overvoltage sense circuit27, a fourth undervoltage sense circuit28, and a fourth undervoltage protection circuit29.

The VIN terminal is connected to an application terminal for a supply voltage (input supply voltage) Vin. The internal voltage generator2generates an internal voltage Vreg50(=5.0 V) based on the supply voltage Vin fed in via the VIN terminal. The internal voltage Vreg50serves as the supply voltage to the internal voltage generator3and the first DC-DC circuit11. The internal voltage Vreg50can be fed out via the VREG50terminal.

The internal voltage generator3generates an internal voltage Vreg15(=1.5 V) based on the internal voltage Vreg50. The internal voltage Vreg15serves as the supply voltage to different parts in the PMIC1. The internal voltage Vreg15is used as a reference voltage in the first, second, and third DC-DC circuits11,12, and13and in the LDO14. The internal voltage Vreg15can be fed out via the VREG15terminal.

The reference voltage generator4generates a first reference voltage Vref1and a second reference voltage Vref2based on the internal voltage Vreg15. The first reference voltage Vref1is used as a reference voltage in different fault detection circuits and the fault protection circuits in the PMIC1. The second reference voltage Vref2is used as a reference voltage in the self-diagnosis circuit described later.

The supply voltage UVLO circuit5is a fault protection circuit for detecting a low voltage fault in the supply voltage Vin. The supply voltage UVLO circuit5outputs a UVLO signal UVLOVIN to the control logic circuit15. When a low voltage fault is detected in the supply voltage Vin, the control logic circuit15shuts down the IC.

The internal voltage UVLO circuit6is a fault protection circuit for detecting a low voltage fault in the internal voltage Vreg50. The internal voltage UVLO circuit6outputs a UVLO signal UVLOREG50to the control logic circuit15. When a low voltage fault is detected in the internal voltage Vreg50, the control logic circuit15carries out a shift to a safe mode state.

The internal voltage UVLO circuit7is a fault protection circuit for detecting a low voltage fault in the internal voltage Vreg15. The internal voltage UVLO circuit7outputs a UVLO signal UVLOREG15to the control logic circuit15. When a low voltage fault is detected in the internal voltage Vreg15, the control logic circuit15carries out a shift to a stand-by state.

An OTP8is a one-time writable ROM, which stores various kinds of data. The control logic circuit15reads data from the OTP8.

The TSD circuit9is an overheat protection circuit and outputs an overheat protection signal TSD to the control logic circuit15. When the TSD circuit9senses that the junction temperature of an IC chip has exceeded a first predetermined temperature (for example, 175° C.), the control logic circuit15shuts down the IC.

The TW circuit10is an overheat sense circuit and outputs an overheat warning signal TW to the control logic circuit15. On sensing that the junction temperature of the IC chip has exceeded a second predetermined temperature (higher than the first predetermined temperature, for example, 140° ° C., the TW circuit10warns of an overheat fault.

The first DC-DC circuit11, together with an inductor L1, an output capacitor Co1, and a boot capacitor Cb1arranged outside the PMIC1, constitutes a first DC-DC converter41(seeFIG.1). The first DC-DC converter41is a buck (step-down) converter that takes as its input the supply voltage Vin (for example, 15.0 V) and that outputs an output voltage Vo1(for example, 3.7 V).

The SW1terminal is a terminal to which the switching output of the first DC-DC circuit11is fed. The SW1terminal is connected to one terminal of the inductor L1. The other terminal of the inductor L1is connected to one terminal of the output capacitor Co1. The other terminal of the output capacitor Co1is connected to the PGND1terminal. The PGND1terminal is connected to the application terminal for the ground potential and is a ground terminal for the first DC-DC circuit11. The boot capacitor Cb1constitutes a bootstrap. One terminal of the boot capacitor Cb1is connected to the BOOT1terminal. The other terminal of the boot capacitor Cb1is connected to the SW1terminal. A boot voltage that appears at the BOOT1terminal is fed to a high-side driver in the first DC-DC circuit11.

Through switching control by the first DC-DC circuit11, the output voltage Vo1appears at the node to which the inductor L1and the output capacitor Co1are connected. The output voltage Vo1is fed to the PVIN2terminal and to the PVIN3terminal as the input power sources for the second and third DC-DC circuits12and13respectively.

The output voltage Vo1is fed to the FB1terminal. The FB1terminal is a terminal for feeding the output voltage Vo1back to the first DC-DC circuit11. The output voltage Vo1fed to the FB1terminal is used also as the input power source for the LDO14.

The second DC-DC circuit12, together with an inductor L2and an output capacitor Co2arranged outside the PMIC1, constitutes a second DC-DC converter42(seeFIG.1). The second DC-DC converter42is a buck (step-down) converter that takes as its input the output voltage Vo1fed to the PVIN2terminal and that outputs an output voltage Vo2(for example, 1.1 V).

The SW2terminal is a terminal to which the switching output of the second DC-DC circuit12is fed. The SW2terminal is connected to one terminal of the inductor L2. The other terminal of the inductor L2is connected to one terminal of the output capacitor Co2. The other terminal of the output capacitor Co2is connected to the PGND23terminal. The PGND23terminal is connected to the application terminal for the ground potential and is a ground terminal for the second and third DC-DC circuits12and13.

Through switching control by the second DC-DC circuit12, the output voltage Vo2appears at the node to which the inductor L2and the output capacitor Co2are connected. The output voltage Vo2is fed to the CMOS sensor device30as the supply voltage. The output voltage Vo2is fed to the FB2terminal. The FB2terminal is a terminal for feeding the output voltage Vo2back to the second DC-DC circuit12.

The third DC-DC circuit13, together with an inductor L3and an output capacitor Co3arranged outside the PMIC1, constitutes a third DC-DC converter43(seeFIG.1). The third DC-DC converter43is a buck (step-down) converter that takes as its input the output voltage Vo1fed to the PVIN3terminal and outputs an output voltage Vo3(for example, 1.8 V).

The SW3terminal is a terminal to which the switching output of the third DC-DC circuit13is fed. The SW3terminal is connected to one terminal of the inductor L3. The other terminal of the inductor L3is connected to one terminal of the output capacitor Co3. The other terminal of the output capacitor Co3is connected to the PGND23terminal.

Through switching control by the third DC-DC circuit13, the output voltage Vo3appears at the node to which the inductor L3and the output capacitor Co3are connected. The output voltage Vo3is fed to the CMOS sensor device30as the supply voltage. The output voltage Vo3is fed to the FB3terminal. The FB3terminal is a terminal for feeding the output voltage Vo3back to the third DC-DC circuit13.

The LDO14is a linear regulator that takes as its input the output voltage Vo1fed to the FB1terminal and that outputs an output voltage Vo4(for example, 3.3 V). The output voltage Vo4is fed out via the VO4terminal to be fed to the CMOS sensor device30as the supply voltage. The VO4terminal is used also as a terminal for feeding the output voltage Vo4back to the LDO14.

The control logic circuit15is a control circuit that controls the PMIC1comprehensively.

The I2C input/output circuit16performs I2C communication with the CMOS sensor device30via the SDA and SCL terminals. I2C is a kind of serial interface. The SDA terminal is used for input and output of serial interface data. The SCL terminal is used for input of a serial interface clock.

The reset input/output circuit17outputs a reset output signal Rsto to the CMOS sensor device30via the RSTOUT terminal. The reset output signal Rsto is, as will be described later, at a level (for example, low) indicating a fault on its detection by the fault protection circuit.

3. Fault Detection Circuit

The first overvoltage sense circuit19, the second overvoltage sense circuit21, the third overvoltage sense circuit24, and the fourth overvoltage sense circuit27are fault detection circuits for detecting an overvoltage fault.

The first overvoltage sense circuit19is a circuit for detecting an overvoltage in the output voltage Vo1fed to the FB1terminal and outputs an overvoltage sense signal OVD1. The second overvoltage sense circuit21is a circuit for detecting an overvoltage in the output voltage Vo2fed to the FB2terminal and outputs an overvoltage sense signal OVD2. The third overvoltage sense circuit24is a circuit for detecting an overvoltage in the output voltage Vo3fed to the FB3terminal and outputs an overvoltage sense signal OVD3. The fourth overvoltage sense circuit27is a circuit for detecting an overvoltage in the output voltage Vo4fed to the VO4terminal and outputs an overvoltage sense signal OVD4.

The first undervoltage sense circuit20, the second undervoltage sense circuit22, the third undervoltage sense circuit25, and the fourth undervoltage sense circuit28are fault detection circuits for detecting an undervoltage fault.

The first undervoltage sense circuit20is a circuit for detecting an undervoltage in the output voltage Vo1fed to the FB1terminal and outputs an undervoltage sense signal UVD1. The second undervoltage sense circuit22is a circuit for detecting an undervoltage in the output voltage Vo2fed to the FB2terminal and outputs an undervoltage sense signal UVD2. The third undervoltage sense circuit25is a circuit for detecting an undervoltage in the output voltage Vo3fed to the FB3terminal and outputs an undervoltage sense signal UVD3. The fourth undervoltage sense circuit28is a circuit for detecting an undervoltage in the output voltage Vo4fed to the VO4terminal and outputs an undervoltage sense signal UVD4.

The TW circuit10is a fault detection circuit for detecting an overheat fault.

When a fault is detected by any of the fault detection circuits described above, the control logic circuit15, while maintaining an active state (normal operation state), outputs the warning output signal Wo at a level (for example, low) indicating a fault to warn the CMOS sensor device30. Here, the reset output signal Rsto is at a level (for example, high) indicating normal operation.

4. Fault Protection Circuit

The second undervoltage protection circuit23, the third undervoltage protection circuit26, and the fourth undervoltage protection circuit29are fault protection circuits for detecting an undervoltage fault.

The second undervoltage protection circuit23is a circuit for detecting an undervoltage in the output voltage Vo2fed to the FB2terminal and outputs an undervoltage protection signal UVP2. The third undervoltage protection circuit26is a circuit for detecting an undervoltage in the output voltage Vo3fed to the FB3terminal and outputs an undervoltage protection signal UVP3. The fourth undervoltage protection circuit29is a circuit for detecting an undervoltage in the output voltage Vo4fed to the VO4terminal and outputs an undervoltage protection signal UVP4.

The supply voltage UVLO circuit5, the internal voltage UVLO circuits6,7, and the TSD circuit9are all fault protection circuits.

When a fault is detected by any of the fault protection circuits described above, the control logic circuit15carries out a shift to one of the shut-down state, the safe mode state, and the stand-by state. When a fault is detected by one of the undervoltage protection circuits described above, the control logic circuit15carries out a shift to the safe mode. Here, the control logic circuit15switches the warning output signal Wo and the reset output signal Rsto both to a level (for example, low) indicating a fault and notifies the CMOS sensor device30of the fault.

Here, the fault protection circuit has a function of detecting a fault, and thus it can be understood as a fault detection circuit.

The PMIC1according to the embodiment has a self-diagnosis (BIST: Built-In Self Test) function for diagnosing whether the fault detection circuits and the fault protection circuits are operating normally. Now, the self-diagnosis function will be described.

As shown inFIG.2, self-diagnosis circuits are provided so as to correspond to the first to fourth overvoltage sense circuits19,21,24, and27, the first to fourth undervoltage sense circuits20,22,25,28, and the second to fourth undervoltage protection circuits23,26, and29(see “A-BIST” inFIG.2).

5-1. Configuration of the Self-Diagnosis Circuit

Here, with reference toFIG.3, a configuration of a self-diagnosis circuit BST1for diagnosing the undervoltage sense circuit20and the overvoltage sense circuit19will be described.

The undervoltage sense circuit20includes the comparator CMP1, the inverter IV1, the resistors R1to R3, and the NMOS transistor NM1. More specifically, one terminal of the resistor R1is connected to the FB1terminal. The other terminal of the resistor R1is, at the node N1, connected to one terminal of the resistor R2. The node N1is connected to one terminal of a second path switch SW_UVD2included in the self-diagnosis circuit BST1, which will be described later. The other terminal of the second path switch SW_UVD2is, at a node N3, connected to the non-inverting input terminal (+) of the comparator CMP1. The inverting input terminal (−) of the comparator CMP1is connected to the application terminal for the first reference voltage Vref1generated by the reference voltage generator4. The output terminal of the comparator CMP1is connected to the input terminal of the inverter IV1.

The NMOS transistor NM1and the resistor R3serve to produce hysteresis. The output terminal of the inverter IV1is connected to the gate of the NMOS transistor NM1. The source of the NMOS transistor NM1is connected to the application terminal for the ground potential. The drain of the NMOS transistor NM1is connected to a node N2to which the other terminal of the resistor R2and one terminal of the resistor R3are connected. The other terminal of the resistor R3is connected to the application terminal for the ground potential.

The self-diagnosis circuit BST1includes a first path switch SW_UVD1, a second path switch SW_UVD2, a first path switch SW_OVD1, a second path switch SW_OVD2, a high-side switch SW_BIST_H, a low-side switch SW_BIST_L, resistors R7to R9, and a control logic circuit15. The first path switch SW_UVD1, the second path switch SW_UVD2, the first path switch SW_OVD1, the second path switch SW_OVD2, the high-side switch SW_BIST_H, and the low-side switch SW_BIST_L are turned on and off by the control logic circuit15.

One terminal of the resistor R7is connected to an application terminal for the second reference voltage Vref2generated by the reference voltage generator4. The other terminal of the resistor R7is, at a node N4, connected to one terminal of the resistor R8. The other terminal of the resistor R8is, at a node N5, connected to one terminal of the resistor R9. The other terminal of the resistor R9is connected to the application terminal for the ground potential.

The node N4is connected to one terminal of the high-side switch SW_BIST_H. The other terminal of the high-side switch SW_BIST_H is, at a node N6, connected to one terminal of the first path switch SW_UVD1. The other terminal of the first path switch SW_UVD1is connected to the node N3.

The node N5is connected to one terminal of the low-side switch SW_BIST_L. The other terminal of the low-side switch SW_BIST_L is, at a node N7, connected to the node N6.

The overvoltage sense circuit19includes a comparator CMP2, an inverter IV2, resistors R4to R6, and the NMOS transistor NM2.

The interconnections in the overvoltage sense circuit19is similar to those in the undervoltage sense circuit20; thus, no overlapping description will be repeated. The node N7is connected to one terminal of the first path switch SW_OVD1. The other terminal of the first path switch SW_OVD1is connected to a node N8to which the second path switch SW_OVD2and the non-inverting input terminal (+) of the comparator CMP2are connected.

5-2. Operation of Fault Detection Circuit and Self-Diagnosis Circuit

Next, the operation of the above configuration shown inFIG.3will be described. In normal operation or the like, the first path switch SW_UVD1is off and the second path switch SW_UVD2is on. In this case, the high-side switch SW_BIST_H and the low-side switch SW_BIST_L are both off. In this way, the voltage generated by dividing the output voltage Vo1fed to the FB1terminal with the resistors R1to R3is fed via the second path switch SW_UVD2to, as a comparator input signal CMP1IN, the non-inverting input terminal (+) of the comparator CMP1. The comparator CMP1compares the comparator input signal CMP1IN with the first reference voltage Vref1.

Thus, when the comparator input signal CMPIIN, which is a voltage based on the output voltage Vo1, is higher than the first reference voltage Vref1, the output of the comparator CMP1is high and the undervoltage sense signal UVD1, which is the output of the inverter IV1, is low. By contrast, when the comparator input signal CMP1IN is equal to or lower than the first reference voltage Vref1, the output of the comparator CMP1is low and the undervoltage sense signal UVD1, which is the output of the inverter IV1, is high. The undervoltage sense signal UVD1is fed to the control logic circuit15. In this way, when an undervoltage occurs in the output voltage Vo1, it is possible to notify the control logic circuit15of the undervoltage sense signal UVD1at high level indicating a fault.

In normal operation or the like, the first path switch SW_OVD1is off and the second path switch SW_OVD2is on. In this case, the voltage generated by dividing the output voltage Vo1fed to the FB1terminal with the resistors R4to R6is fed via the second path switch SW_OVD2to, as a comparator input signal CMP2IN, the non-inverting input terminal (+) of the comparator CMP2. The comparator CMP2compares the comparator input signal CMP2IN with the first reference voltage Vref1.

Thus, when the comparator input signal CMP2IN, which is a voltage based on the output voltage Vo1, is equal to or lower than the first reference voltage Vref1, the overvoltage sense signal OVD1, which is the output of the comparator CMP2, is low. By contrast, when the comparator input signal CMP2IN is higher than the first reference voltage Vref1, the overvoltage sense signal OVD1, which is the output of the comparator CMP2, is high. The overvoltage sense signal OVD1is fed to the control logic circuit15. In this way, when an overvoltage occurs in the output voltage Vo1, it is possible to notify the control logic circuit15of the overvoltage sense signal OVD1at high level indicating a fault.

During the self-diagnosis operation by the undervoltage sense circuit20, the control logic circuit15keeps the first path switch SW_UVD1on and the second path switch SW_UVD2off. The control logic circuit15keeps the first path switch SW_OVD1off. In this case, the control logic circuit15switches between a first state in which the high-side switch SW_BIST_H is on and the low-side switch SW_BIST_L is off and a second state in which the high-side switch SW_BIST_H is off and the low-side switch SW_BIST_L is on.

In this way, in the first state, the voltage (a voltage with a first level) generated at the node N4by dividing the second reference voltage Vref2with the resistors R7to R9is fed via the high-side switch SW_BIST_H and the first path switch SW_UVD1to, as the comparator input signal CMP1IN, the non-inverting input terminal (+) of the comparator CMP1. In this case, if the comparator CMP1is operating normally, the output of the comparator CMP1is high, and the undervoltage sense signal UVD1is low.

By contrast, in the second state, the voltage (a voltage with a second level) generated at the node N5by dividing the second reference voltage Vref2with the resistors R7to R9is fed via the low-side switch SW_BIST_L and the first path switch SW_UVD1to, as the comparator input signal CMP1IN, the non-inverting input terminal (+) of the comparator CMP1. In this case, if the comparator CMP1is operating normally, the output of the comparator CMP1is low, and the undervoltage sense signal UVD1is high.

Thus, the control logic circuit15can check whether the level of the undervoltage sense signal UVD1has been switched between high and low to diagnose whether the undervoltage sense circuit20is normal.

During the self-diagnosis operation by the overvoltage sense circuit19, the control logic circuit15keeps the first path switch SW_OVD1on and the second path switch SW_OVD2off. The control logic circuit15keeps the first path switch SW_UVD1off. In this case, the control logic circuit15switches between the first and second states described above.

In this way, in the first state described above, the voltage generated at the node N4by dividing the second reference voltage Vref2with the resistors R7to R9is fed via the high-side switch SW_BIST_H and the first path switch SW_OVD1to, as the comparator input signal CMP2IN, the non-inverting input terminal (+) of the comparator CMP2. In this case, if the comparator CMP2is operating normally, the overvoltage sense signal OVD1, which is the output of the comparator CMP2, is high.

By contrast, in the second state described above, the voltage generated at the node N5by dividing the second reference voltage Vref2with the resistors R7to R9is fed via the low-side switch SW_BIST_L and the first path switch SW_OVD1to, as the comparator input signal CMP2IN, the non-inverting input terminal (+) of the comparator CMP2. In this case, if the comparator CMP2is operating normally, the overvoltage sense signal OVD1, which is the output of the comparator CMP2, is low.

Thus, the control logic circuit15can check whether the level of the overvoltage sense signal OVD1has been switched between high and low to diagnose whether the overvoltage sense circuit19is normal.

In this way, in the embodiment, the resistors R7to R9, the high-side switch SW_BIST_H, and the low-side switch SW_BIST_L constitute a voltage switch circuit50that switches the level of a voltage that is based on the second reference voltage Vref2and that outputs the resulting voltage. The first path switches SW_UVD1and SW_OVD1and the second path switches SW_UVD2and SW_OVD2constitute path switch circuits51and52that switch between the first path through which a voltage based on the second reference voltage Vref2is fed to the comparator and the second path through which a voltage based on the output voltage Vo1is fed to the comparator. The first path switch circuit51is constituted by the first and second path switches SW_UVD1and SW_UVD2. The second path switch circuit52is constituted by the first and second path switches SW_OVD1and SW_OVD2.

In self-diagnosis operation, the first path switches SW_UVD1and SW_OVD1are kept on and the second path switches SW_UVD2and SW_OVD2are kept off, so that the second path is cut off and the first path is secured. In that state, the first and second states are switched with the high-side switch SW_BIST_H and the low-side switch SW_BIST_L, so that the voltage switch circuit50outputs a voltage with a different level regardless of the output voltage Vo1to feed the resulting voltage to the comparator. In this way, the control logic circuit15can diagnose the fault detection circuit based on whether the output level of the comparator is switched.

In this way, in the embodiment, it is possible to diagnose the fault detection circuit regardless of the value of the output voltage Vo1, which is a fault sensing target voltage. Thus, as will be described later, it is possible to perform self-diagnosis operation before the output voltage Vo1rises during IC start-up.

Self-diagnosis operation for the undervoltage sense circuit20and self-diagnosis operation for the overvoltage sense circuit19are performed in temporal sequence but in any order.

Switching between the first and second states with the high-side switch SW_BIST_H and the low-side switch SW_BIST_L can be started in either state, and switching can be performed any number of times more than once.

In the fault detection circuit different from the one that performs self-diagnosis operation, the on/off states of the second path switches SW_UVD2and SW_OVD2do not matter.

Also the second overvoltage sense circuit21and the second undervoltage sense circuit22can be provided with self-diagnosis circuits with a configuration similar to that inFIG.3. For the second undervoltage protection circuit23and its self-diagnosis circuit, circuit blocks similar to the first undervoltage sense circuit20, the first path switch SW_UVD1, and the second path switch SW_UVD2shown inFIG.3can be added to the second overvoltage sense circuit21and the second undervoltage sense circuit22.

The third overvoltage sense circuit24, the third undervoltage sense circuit25, the third undervoltage protection circuit26, and their self-diagnosis circuits, as well as the fourth overvoltage sense circuit27, the fourth undervoltage sense circuit28, the fourth undervoltage protection circuit29, and their self-diagnosis circuits can be configured similarly to the second overvoltage sense circuit21, the second undervoltage sense circuit22, the second undervoltage protection circuit23, and their self-diagnosis circuits.

Although, in the above embodiment, the fault detection target voltages are the output voltages Vo1and Vo4of the power supply circuit, this is not meant as any limitation; instead, a self-diagnosis circuit can be configured in a similar way as described above with respect to, as a target voltage, the supply voltage Vin, the internal voltage (e.g. Vreg50), or a detection voltage of the junction temperature. That is, a self-diagnosis circuit can be applied to a UVLO circuit or an overheat sense/protection circuit.

6. An Example of Operation During IC Start-Up

FIG.4is a timing chart showing an example of the operation of the PMIC1during start-up. InFIG.4, first, the control logic circuit15is in a stand-by state, and the IC is out of operation. In this state, when, at time point t1, the supply voltage Vin starts rising, together with it, also the internal voltages Vreg50and Vreg15start rising.

Then, when, at time point t2, UVLO release with respect to the internal voltage Vreg15is detected by the internal voltage UVLO circuit7, the control logic circuit15makes a shift from the stand-by state to a digital self-diagnosis mode state (D-BIST).

If, in the digital self-diagnosis mode state, the diagnosis result is normal, the control logic circuit15makes a shift to an OTP load state. Here, the control logic circuit15reads data from an OTP8and initializes the settings.

When the OTP load state ends, the control logic circuit15carries out a shift to an analogue self-diagnosis mode state (A-BIST). In the analogue self-diagnosis mode state, self-diagnosis operation is performed with respect to the various overvoltage sense circuits, undervoltage sense circuits, and undervoltage protection circuits described earlier. Here, self-diagnosis operation with respect to the UVLO circuit and the overheat fault sense/protection circuit may be performed as described earlier.

If, in the analogue self-diagnosis mode state, the diagnosis results are normal with respect to all the circuits and in addition the supply voltage Vin and the internal voltage Vreg50are in a UVLO release state, the control logic circuit15carries out a shift from the analogue self-diagnosis mode state to a start-up state.

In the start-up state, the control logic circuit15controls the first to third DC-DC circuits11,12, and13and the LDO14to raise the output voltages Vo1to Vo4in this order. More specifically, first, the control logic circuit15starts raising the output voltage Vo1and, on detecting that the output voltage Vo1is released from an undervoltage state and the output voltage Vo1has risen normally, it starts raising the output voltage Vo2. Then, on detecting that the undervoltage state of the output voltage Vo2is released and the output voltage Vo2has risen normally, the control logic circuit15starts raising the output voltage Vo3. Then, on detecting that the undervoltage state of the output voltage Vo3is released and the output voltage Vo3has risen normally, the control logic circuit15starts raising the output voltage Vo4.

Then, on detecting that the undervoltage state of the output voltage Vo4is released and the output voltage Vo4has risen normally, the control logic circuit15raises the warning output signal Wo to high level. If no fault is detected by the fault protection circuit after the warning output signal Wo is raised to high level until a predetermined delay time passes, the control logic circuit15raises the reset output signal Rsto to high level and carries out a shift from the start-up state to the active state (normal operation state).

In this way, with the startup operation shown inFIG.4, it is possible to perform self-diagnosis operation (A-BIST) before the output voltages Vo1to Vo4rise. Thus, it is possible to perform diagnosis without outputting abnormal output voltages Vo1to Vo4. When the diagnosis result indicates a fault, the control logic circuit15carries out a shift to the safe mode.

7. Example of Self-Diagnosis Operation

FIG.5is a timing chart showing one example of the self-diagnosis operation in the first undervoltage sense circuit20(FIG.3) in the analogue self-diagnosis mode state (A-BIST) and the like. InFIG.5, for switches, high level indicates the on-state and low level the off-state.

As shown inFIG.5, in the analogue self-diagnosis mode state, the first path switch SW_UVD1is on, and the second path switch SW_UVD2is off. By contrast, the on/off states of the high-side switch SW_BIST_H and the low-side switch SW_BIST_L are switched from the first state to the second state and then to the first state. Thus, the comparator input signal CMP1IN is switched from high to low and then to high. In the example inFIG.5, the comparator CMP11is normal; thus, the undervoltage sense signal UVD1is switched from low to high and then to low. Accordingly, the control logic circuit15diagnoses the undervoltage sense circuit20as normal.

As shown inFIG.5, the control logic circuit15can carry out a shift from the active state to the self-diagnosis mode state (SELF TEST). This shift is performed in accordance with an instruction from the CMOS sensor device30by I2C communication. Also in this self-diagnosis mode state, as in the analogue self-diagnosis mode state, self-diagnosis operation for the undervoltage sense circuit20is performed.

8. Other Modifications

The various technical features disclosed herein may be implemented in any other manners than in the embodiments described above, and allow for any modifications made without departure from their technical ingenuity. That is, the above embodiments should be understood to be in every aspect illustrative and not restrictive. The scope of the present disclosure is defined not by the description of the embodiments given above but by the appended claims, and should be understood to encompass any modifications made in a sense and scope equivalent to those of the claims.

As described above, for example, according to one aspect of what is disclosed herein, a self-diagnosis circuit (BST1) is configured to diagnose a fault detection circuit (20) including a first comparator (CMP1) configured to be fed with a voltage based on a fault sensing target voltage (Vo1) and a first reference voltage (Vref1), and includes a voltage switch circuit (50) configured to switch the level of a voltage based on a second reference voltage (Vref2) and output the resulting voltage, a first path switch circuit (51) configured to switch between a path through which the voltage output from the voltage switch circuit is fed to the first comparator and a path through which the voltage based on the fault sensing target voltage is fed to the first comparator, and a control circuit (15) configured to control the voltage switch circuit and the path switch circuit (a first configuration).

In the first configuration described above, preferably, the voltage switch circuit (50) includes a first switch (SW_BIST_H) having one terminal connected to a first node (N4) at which a first-level voltage based on the second reference voltage (Vref2) appears and a second switch (SW_BIST_L) having one terminal connected to a second node (N5) at which a second-level voltage based on the second reference voltage appears and having the other terminal connected to the other terminal of the first switch. The first and second switches may be configured to be turned on and off by the control circuit (15) (a second configuration).

In the second configuration described above, preferably, the voltage switch circuit (50) includes a first resistor (R7) having one terminal connected to an application terminal for the second reference voltage (Vref2), a second resistor (R8) having one terminal connected to the other terminal of the first resistor at the first node (N4), and a third resistor (R9) having one terminal connected to the other terminal of the second resistor at the second node (N5) (a third configuration).

In any of the first to third configurations described above, preferably, the first path switch circuit (51) includes a third switch (SW_UVD1) that is arranged between a third node (N6) to which the voltage output from the voltage switch circuit (50) is fed and the input terminal of the first comparator (CMP1) and a fourth switch (SW_UVD2) that is arranged between a fourth node (N1) to which the voltage based on the fault sensing target voltage (Vo1) is fed and the input terminal of the first comparator (a fourth configuration).

In the fourth configuration described above, preferably, the fault detection circuit (20) includes a fourth resistor (R1) having one terminal connected to an application terminal for the fault sensing target voltage, a fifth resistor (R2) having one terminal connected to the other terminal of the fourth resistor at the fourth node (N1), a sixth resistor (R3) having one terminal connected to the other terminal of the fifth resistor at a fifth node (N2), and an NMOS transistor (NM1) having the gate driven based on the output of the first comparator and having the drain connected to the fifth node (a fifth configuration).

In any of the first to fifth configurations described above, preferably, the first reference voltage (Vref1) is fed to one input terminal of the first comparator (CMP1). The fault detection circuit (20,19) may include a second comparator (CMP2) having one input terminal to which the first reference voltage is fed. The self-diagnosis circuit (BST1) may include a second path switch circuit (52) configured to switch between a path through which the voltage output from the voltage switch circuit (50) is fed to the other input terminal of the second comparator and a path through which the voltage based on the fault sensing target voltage (Vo1) is fed to the other input terminal of the second comparator (a sixth configuration).

In any of the first to sixth configurations described above, preferably, the fault sensing target voltage (Vo1) is the output voltage of a power supply circuit (41) (a seventh configuration).

The seventh configuration described above is, preferably, configured to perform self-diagnosis operation before the output voltage (Vo1) rises during the start-up of an IC (1) including the self-diagnosis circuit (BST1) (an eighth configuration).

According to another aspect of what is disclosed herein, a semiconductor device (1) includes the self-diagnosis circuit (BST1) according to any of the first to eighth configurations described above (a ninth configuration).

The ninth configuration described above, preferably, further includes a power supply circuit (14) for supplying electric power to a vehicle-mounted device (30). The fault sensing target voltage (Vo4) may be the output voltage of the power supply circuit (a tenth configuration).

INDUSTRIAL APPLICABILITY

The present disclosure finds application in, for example, vehicle-mounted PMICs.

LIST OF REFERENCE SIGNS