Counter, pixel circuit, display panel and display device

Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Chinese Patent Application No. 201910916483.2 filed on Sep. 26, 2019, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the field of display technology, and in particular to a counter, a pixel circuit, a display panel, and a display device.

BACKGROUND

Binary counters are usually adopted to count, so as to obtain a square wave pulse sampling signal via a combinational logic circuit at each count.

SUMMARY

In a first aspect of the present disclosure, a counter is provided, including: a start-up circuit, configured to generate a start-up signal according to an inputted clock signal and output the start-up signal; and M first combinational logic circuits and M second combinational logic circuits, where the M first combinational logic circuits and the M second combinational logic circuits are alternate and cascaded, and M is an integer greater than or equal to 1; where an input terminal of the first combinational logic circuit is coupled to an output terminal of the start-up circuit or an output terminal of the second combinational logic circuit of a previous stage, an input terminal of the second combinational logic circuit is coupled to an output terminal of the first combinational logic circuit of a previous stage, and each of a clock signal terminal of the first combinational logic circuit and a clock signal terminal of the second combinational logic circuit is configured to input the clock signal; and where the first combinational logic circuit is configured to output the clock signal in a first time period and continuously output a low level signal in a second time period, and the second combinational logic circuit is configured to output an inverted signal of the clock signal in a third time period and continuously output a low level signal in a fourth time period.

In addition, the counter according to the above embodiments of the present disclosure may also have the following additional technical features.

According to some embodiments of the present disclosure, the start-up circuit is configured to: generate the start-up signal of a current moment according to the clock signal and a start-up signal of a previous moment, where the start-up signal of the previous moment is fed back by the start-up circuit.

According to some embodiments of the present disclosure, the start-up circuit includes: a first NOR gate, where a first input terminal of the first NOR gate is configured to input the clock signal, and an output terminal of the first NOR gate is configured to output the start-up signal; and a first NOT gate, where an input terminal of the first NOT gate is coupled to the output terminal of the first NOR gate, and an output terminal of the first NOT gate is coupled to a second input terminal of the first NOR gate.

According to some embodiments of the present disclosure, the first combinational logic circuit is configured to: output the clock signal in the first time period and continuously output the low level signal in the second time period, according to the start-up signal or a signal of the output terminal of the second combinational logic circuit of the previous stage and according to a signal fed back by the first combinational logic circuit at a previous moment.

According to some embodiments of the present disclosure, the first combinational logic circuit includes: a second NOR gate, where a first input terminal of the second NOR gate is coupled to the output terminal of the start-up circuit or the output terminal of the combinational logic circuit of the previous stage; a first transistor, where a control electrode of the first transistor is coupled to an output terminal of the second NOR gate, a first electrode of the first transistor is coupled to a second input terminal of the second NOR gate, and a second electrode of the first transistor is grounded; a first transmission gate, where an input terminal of the first transmission gate is configured to input the clock signal, a first control terminal of the transmission gate is coupled to the output terminal of the second NOR gate, an output terminal of the first transmission gate is coupled to the output terminal of the first combinational logic circuit, and the output terminal of the first transmission gate is configured to output the clock signal when the first transmission gate is turned on and continuously output a low level signal when the first transmission gate is turned off; and a second NOT gate, where an input terminal of the second NOT gate is coupled to the output terminal of the second NOR gate, and an output terminal of the second NOT gate is coupled to a second control terminal of the first transmission gate.

According to some embodiments of the present disclosure, the second combinational logic circuit is configured to: output the inverted signal of the clock signal in the third time period and continuously output the low level signal in the fourth time period, according to a signal of the output terminal of the first combinational logic circuit of the previous stage and a signal fed back by the second combinational logic circuit at a previous moment.

According to some embodiments of the present disclosure, the second combinational logic circuit includes: a third NOR gate, where a first input terminal of the third NOR gate is coupled to the output terminal of the combinational logic circuit of the previous stage, and a second input terminal of the third NOR gate is coupled to the output terminal of the second combinational logic circuit; a third NOT gate, where an input terminal of the third NOT gate is coupled to an output terminal of the third NOR gate; a second transistor, where a control electrode of the second transistor is coupled to the output terminal of the third NOT gate, and a first electrode of the second transistor is configured to input a direct current power signal; a fourth NOT gate, where an input terminal of the fourth NOT gate is coupled to a second electrode of the second transistor, and an output terminal of the fourth NOT gate is coupled to the output terminal of the second combinational logic circuit; and a second transmission gate, where an input terminal of the second transmission gate is configured to input the clock signal, a first control terminal of the second transmission gate is coupled to the output terminal of the third NOR gate, a second control terminal of the second transmission gate is coupled to an output terminal of the third NOT gate, an output terminal of the second transmission gate is coupled to the input terminal of the fourth NOT gate, and the output terminal of the second transmission gate is configured to output the clock signal when the second transmission gate is turned on and continuously output a high level signal when the second transmission gate is turned off.

Further, in a second aspect of the present disclosure, a pixel circuit is provided, including the counter described above.

Further, in a third aspect of the present disclosure, a display panel is provided, including the pixel circuit described above.

Further, in a fourth aspect of the present disclosure, a display device is provided, including a housing and the display panel described above.

Some of the additional aspects and advantages of the present disclosure will be provided in the following descriptions, and some will become apparent from the following descriptions or be understood through the practice of the present disclosure.

DETAILED DESCRIPTION

The embodiments of the present disclosure are described in detail hereinafter. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numbers represent the same or similar elements or elements with the same or similar functions. The embodiments described with reference to the accompanying drawings hereinafter are exemplary and intended to explain the present disclosure, and should not be construed as limiting the present disclosure.

A counter, a pixel circuit, a display panel, and a display device according to embodiments of the present disclosure are described hereinafter with reference to the drawings.

FIG. 1is a design principle diagram of a pulse sampling signal generated by a binary counter in the related technologies.

As shown inFIG. 1, a modulo-16 counter is taken as an example. Four D flip-flops are coupled in series and controlled uniformly by a clock signal. An output of each D flip-flop may generate a required control signal through a combinational logic circuit.

Further, as shown inFIG. 2, in an ideal situation, Q3, Q2, Q1and Q0may form a binary number to represent the (16-N)-th rising edge, for example, the binary number 0000 may represent the sixteenth rising edge. Q3, Q2, Q1and Q0may be synthesized into pulse signals through combinational logics, to control other logics.

It can be seen that, if a pulse signal for sampling needs to be generated for each step (for example, as shown inFIGS. 2, S1, S2, S3and S4may be generated by the combinational logic circuits of Comb_1, Comb_2, Comb_3and Comb_4respectively), and if the modulo-16 counter generates 16 pulse sampling signals, then 16 combinational logic circuits are required. As a result, a large number of combinational logic gates need to be added to the circuit structure, occupying a relatively large layout area and resulting in relatively high power consumption.

It can be seen that in the related technologies, when a binary counter is used for counting and in a case that multiple square wave pulse sampling signals need to be generated, multiple combinational logic circuits may be required at the same time to achieve this. However, the multiple combinational logic circuits occupy a relatively large layout area and have relatively high power consumption.

To address the problems in the related technologies described above, embodiments of the present disclosure provide a counter.

According to some embodiments of the present disclosure, the counter may include: a start-up circuit, configured to generate a start-up signal according to an inputted clock signal and output the start-up signal; and M first combinational logic circuits and M second combinational logic circuits, where the M first combinational logic circuits and the M second combinational logic circuits are alternate and cascaded, and M is an integer greater than or equal to 1. An input terminal of the first combinational logic circuit is coupled to an output terminal of the start-up circuit or an output terminal of the second combinational logic circuit of a previous stage, and an input terminal of the second combinational logic circuit is coupled to an output terminal of the first combinational logic circuit of a previous stage. Each of a clock signal terminal of the first combinational logic circuit and a clock signal terminal of the second combinational logic circuit is configured to input the clock signal. The first combinational logic circuit is configured to output the clock signal in a first time period and continuously output a low level signal in a second time period. The second combinational logic circuit is configured to output an inverted signal of the clock signal in a third time period and continuously output a low level signal in a fourth time period.

In some embodiments of the present disclosure, M may be an integer greater than or equal to 2.

FIG. 3is a block diagram of a counter according to some embodiments of the present disclosure.

As shown inFIG. 3, the counter100includes: a start-up circuit1, a first combinational logic circuit2and a second combinational logic circuit3.

The start-up circuit1is configured to generate a start-up signal according to an inputted clock signal, and output the start-up signal. As shown inFIG. 4, the first combinational logic circuit2(corresponding to A0and A1inFIG. 4) and the second combinational logic circuit3(corresponding to B0and B1inFIG. 4) are alternately cascaded. The input terminal of the first combinational logic circuit2is coupled to the output terminal of the start-up circuit1or the output terminal of the second combinational logic circuit3of the previous stage. The input terminal of the second combinational logic circuit3is coupled to the output terminal of the first combinational logic circuit2of the previous stage. A clock signal terminal of the first combinational logic circuit2and a clock signal terminal of the second combinational logic circuit3are each configured to input the clock signal. The first combinational logic circuit2is configured to output the clock signal or continuously output a low level signal; the second combinational logic circuit3is configured to output an inverted signal of the clock signal or continuously output a low level signal. For example, the first combinational logic circuit2is configured to output the clock signal in a first time period and continuously output a low level signal in a second time period; and the second combinational logic circuit3is configured to output an inverted signal of the clock signal in a third time period and continuously output a low level signal in a fourth time period.

That is, in the embodiments of the present disclosure, the counter100may generate and output the start-up signal according to the inputted clock signal via the start-up circuit1, then, output the clock signal inputted to the clock signal terminal of the first combinational logic circuit2or continuously output the low level signal via the first combinational logic circuit2, and output the inverted signal of the clock signal inputted to the clock signal terminal of the second combinational logic circuit3or continuously output the low level signal via the second combinational logic circuit3, so as to divide the clock signal to generate multiple sampling pulse signals.

Specifically, the input terminal of the first combinational logic circuit2may be coupled to the output terminal of the start-up circuit1or the output terminal of the second combinational logic circuit3of the previous stage, to receive a signal from the output terminal of the start-up circuit1or to receive a signal from the output terminal of the second combinational logic circuit3of a previous stage, and output the clock signal inputted to the clock signal terminal of the first combinational logic circuit2or continuously output the low level signal via the first combinational logic circuit2. The input terminal of the second combinational logic circuit3may be coupled to the output terminal of the first combinational logic circuit2of the previous stage, to receive the signal from the output terminal of the first combinational logic circuit2of the previous stage, and output the inverted signal of the clock signal inputted to the clock signal terminal of the second combinational logic circuit3or continuously output the low level signal via the combinational logic circuit3. In this way, the clock signal is divided to generate multiple sampling pulse signals.

According to some embodiments of the present disclosure, the start-up circuit1is further configured to: generate the start-up signal of the current moment according to the clock signal and the output signal of the previous moment fed back by itself.

That is to say, the start-up circuit1may generate the start-up signal of the current moment according to the clock signal and the output signal of the previous moment fed back by itself, to output the start-up signal of the current moment and output it to the input terminal of the first combinational logic 2 via the output terminal of the start-up circuit1.

According to some embodiments of the present disclosure, as shown inFIG. 5, the start-up circuit1includes: a first NOR gate11and a first NOT gate12.

The first input terminal of the first NOR gate11is configured to input the clock signal, and the output terminal of the first NOR gate11is configured to output the start-up signal; and the input terminal of the first NOT gate12is coupled to the output terminal of the first NOR gate11, and the output terminal of the first NOT gate12is coupled to the second input terminal of the first NOR gate11.

For example, in embodiments of the present disclosure, if the signal at the first input terminal of the first NOR gate11is a low level signal, and the signal at the second input terminal of the first NOR gate11is a low level signal (no input), then the output terminal of the first NOR gate11outputs the start-up signal (high level signal), and the output terminal of the first NOT gate12outputs a low level signal.

It should be noted that if the signal at the second input terminal of the first NOR gate11is a high level signal, the output terminal of the first NOR gate11stops outputting the start-up signal (no output), and the output terminal of the first NOT gate12continuously outputs a high level signal. In other words, when the signal at the second input terminal of the first NOR gate11is a high level signal, regardless of whether the clock signal at the first input terminal of the first NOR gate11is a high level signal or a low level signal, the output terminal of the first NOR gate11outputs a low level signal (no output) and the output terminal of the first NOT gate12outputs a high level signal.

According to some embodiments of the present disclosure, the first combinational logic circuit2is specifically configured to: output the clock signal or continuously output the low level signal, according to the start-up signal or a signal of the output terminal of the second combinational logic circuit3of the previous stage and according to a signal fed back by the first combinational logic circuit2at a previous moment. For example, the first combinational logic circuit2is specifically configured to: output the clock signal in the first time period and continuously output the low level signal in the second time period, according to the start-up signal or a signal of the output terminal of the second combinational logic circuit3of the previous stage and according to a signal fed back by the first combinational logic circuit2at a previous moment.

In other words, the first combinational logic circuit2may output the clock signal or continuously output the low level, according to the start-up signal or the signal at the output terminal of the second combinational logic circuit3of the previous stage, and according to the output signal of the previous moment fed back by itself. In this way, the clock signal is divided to generate multiple sampling pulse signals.

According to some embodiments of the present disclosure, as shown inFIG. 6, the first combinational logic circuit2includes: a second NOR gate21, a first transistor22, a first transmission gate23and a second NOT gate24.

The first input terminal of the second NOR gate21is coupled to the output terminal of the start-up circuit1or the output terminal of the combinational logic circuit2of the previous stage; the control electrode of the first transistor22is coupled to the output terminal of the second NOR gate21, the first electrode of the first transistor22is coupled to the second input terminal of the second NOR gate21, and the second electrode of the first transistor22is grounded. The input terminal of the first transmission gate23is configured to input the clock signal, the first control terminal of the first transmission gate23is coupled to the output terminal of the second NOR gate21, and the output terminal of the first transmission gate23is coupled to the output terminal of the first combinational logic circuit2. The output terminal of the first transmission gate23is configured to output the clock signal when the first transmission gate23is turned on, and continuously output a low level signal when the first transmission gate23is turned off. The input terminal of the second NOT gate24is coupled to the output terminal of the second NOR gate21, and the output terminal of the second NOT gate24is coupled to the second control terminal of the first transmission gate23.

For example, in embodiments of the present disclosure, if the signal at the output terminal of the start-up circuit1or the signal at the output terminal of the second combinational logic circuit3of the previous stage is a high level signal, that is, the signal at the first input terminal of the second NOR gate21being a high level signal, then the signal at the output terminal of the second NOR gate21is a low level signal, the control electrode of the first transistor22is in a low level, the signal at the first control terminal of the first transmission gate23is a low level signal, the signal at the output terminal of the second NOT gate24is a high level signal, and the signal at the second control terminal of the first transmission gate23is a high level signal. In this case, the first transmission gate23is turned on, the first transistor22is turned off, and the output terminal of the first transmission gate23outputs the clock signal.

If the signal at the output terminal of the start-up circuit1or the signal at the output terminal of the second combinational logic circuit3of the previous stage is a low level signal, and the signal fed back by the first combinational logic circuit2at the previous moment is a low level signal, that is, the signals at the first input terminal and the second input terminal of the second NOR gate21both being low level signals, then the signal at the output terminal of the second NOR gate21is a high level signal, the control electrode of the first transistor22is in a high level, and the signal at the first control terminal of the transmission gate23is a high level signal. In this case, the first transmission gate23is turned off, the first transistor22is turned on, and the output terminal of the first transmission gate23continuously outputs a low level signal.

According to some embodiments of the present disclosure, the second combinational logic circuit3is specifically configured to: output the inverted signal of the clock signal or continuously output the low level signal, according to a signal of the output terminal of the first combinational logic circuit2of the previous stage and a signal fed back by the second combinational logic circuit3at a previous moment. For example, the second combinational logic circuit3is specifically configured to: output the inverted signal of the clock signal in the third time period and continuously output the low level signal in the fourth time period, according to a signal of the output terminal of the first combinational logic circuit2of the previous stage and a signal fed back by the second combinational logic circuit3at a previous moment.

In other words, the second combinational logic circuit3may output the inverted signal of the clock signal or continuously output the low level according to the signal at the output terminal of the first combinational logic circuit2of the previous stage and the output signal of the previous moment fed back by itself. In this way, the clock signal is divided to generate multiple sampling pulse signals.

According to some embodiments of the present disclosure, as shown inFIG. 7, the second combinational logic circuit3includes: a third NOR gate31, a third NOT gate32, a second transistor33, a fourth NOT gate34, and a second transmission gate35.

The first input terminal of the third NOR gate31is coupled to the output terminal of the combinational logic circuit2of the previous stage, and the second input terminal of the third NOR gate31is coupled to the output terminal of the second combinational logic circuit3. The input terminal of the third NOT gate32is coupled to the output terminal of the third NOR gate31; the control electrode of the second transistor33is coupled to the output terminal of the third NOT gate32, and the first electrode of the second transistor33is configured to input a direct current power signal; the input terminal of the fourth NOT gate34is coupled to the second electrode of the second transistor33, and the output terminal of the fourth NOT gate34is coupled to the output terminal of the second combinational logic circuit3. The input terminal of the second transmission gate35is configured to input the clock signal, the first control terminal of the second transmission gate35is coupled to the output terminal of the third NOR gate31, the second control terminal of the second transmission gate35is coupled to the third NOT gate32, and the output terminal of the second transmission gate35is coupled to the input terminal of the fourth NOT gate34. The output terminal of the second transmission gate35is configured to output the clock signal when the second transmission gate35is turned on, and continuously output a high level signal when the second transmission gate35is turned off.

For example, in embodiments of the present disclosure, if the signal at the output terminal of the first combinational logic circuit2of the previous stage is a high level signal, that is, the signal at the first input terminal of the third NOR gate31being a high level signal, then the signal at the output terminal of the third NOR gate31is a low level signal, the signal at the output terminal of the third NOT gate32is a high level signal, the control electrode of the second transistor33is in a high level, the signal at the first input terminal of the second transmission gate35is a low level signal, and the signal at the second input terminal of the second transmission gate35is a high level signal. In this case, the second transmission gate35is turned on, the second transistor33is turned off, and the output terminal of the second transmission gate35outputs, via the output terminal of the fourth NOT gate34, the inverted signal of the clock signal.

If the signal at the output terminal of the first combinational logic circuit2of the previous stage is a low level signal, and the signal fed back by the second combinational logic circuit3at the previous moment is a low level signal, that is, the signals at the first input terminal and the second input terminal of the third NOR gate31being low level signals, then the signal at the output terminal of the third NOR gate31is a high level signal, the signal at the output terminal of the third NOT gate32is a low level signal, the control electrode of the second transistor33is in a low level, and the signal at the first input terminal of the second transmission gate35is a high level signal. In this case, the second transmission gate35is turned off, the second transistor33is turned on, and the output terminal of the second transmission gate35continuously outputs, via the output terminal of the fourth NOT gate34, a low level signal.

Specifically, according to some specific embodiments of the present disclosure, in conjunction withFIG. 4,FIG. 6,FIG. 7andFIG. 8, the design principle of the counter according to the embodiments of the present disclosure is further described. The first combinational logic circuit2(for example, A0and A1inFIG. 4) may control the switch-on and switch-off of the first transmission gate23according to the start-up signal or the output signal of the second combinational logic circuit3of the previous stage, to output the clock signal or continuously output the low level signal. For example, when the first transmission gate23is turned on according to the start-up signal or the output signal of the second combinational logic circuit3of the previous stage, the first combinational logic circuit2outputs the clock signal; and when the first transmission gate23is turned off according to the start-up signal or the output signal of the second combinational logic circuit3of the previous stage, the first combinational logic circuit2continuously outputs the low level signal. In addition, the second combinational logic circuit3(for example, B0and B1inFIG. 4) may control the switch-on and switch-off of the second transmission gate35according to the output signal of the first combinational logic circuit2of the previous stage, to output the clock signal or continuously output the low level signal. For example, when the second transmission gate35is turned on according to the output signal of the first combinational logic circuit2of the previous stage, the second combinational logic circuit3outputs the clock signal, and when the second transmission gate35is turned off according to the output signal of the combinational logic circuit2of the previous stage, the second combinational logic circuit3continuously outputs the low level signal.

It should be noted that, as shown inFIGS. 4, 6 and 9, when the first combinational logic circuit2controls, according to the output of the second combinational logic circuit3of the previous stage, the first transmission gate23to be turned on, there is a certain delay, the signal at the output terminal of the first combinational logic circuit2may follow the clock signal to become high, and further, the first transmission gate23is continuously turned on, so that the output signal continuously follows the clock signal until the clock signal changes to a low level signal. In this case, the first transmission gate23is turned off, and the output terminal of the first combinational logic circuit2is grounded and continuously output the low level signal.

In other words, the counter100according to the embodiments of the present disclosure may divide the high level signals of the clock signal via the first combinational logic circuit2and divide the low level signals of the clock signal via the second combinational logic circuit3. In this way, based on the first combinational logic circuits2and the second combinational logic circuits3that are alternately cascaded, the pulse sampling signal corresponding to the high level of the clock signal and the pulse sampling signal corresponding to the low level of the clock signal in each clock cycle are obtained.

In summary, with the counter according to the embodiments of the present disclosure, the start-up signal is generated and outputted by the start-up circuit according to the inputted clock signal, then, the clock signal is outputted or the low level signal is continuously outputted by the first combinational logic circuit, and the inverted signal of the clock signal is outputted or the low level signal is continuously outputted by the second combinational logic circuit. As a result, the counter can divide the clock signal to generate multiple sampling pulse signals, and can reduce circuit power consumption and layout area.

FIG. 10is a block diagram of a pixel circuit according to embodiments of the present disclosure.

As shown inFIG. 10, in embodiments of the present disclosure, the pixel circuit1000includes the counter100.

In the pixel circuit according to the embodiments of the present disclosure, the counter is adopted, so that multiple sampling pulse signals can be generated by dividing the clock signal, and the power consumption of the circuit and the layout area are reduced.

FIG. 11is a block diagram of a display panel according to embodiments of the present disclosure.

As shown inFIG. 11, in embodiments of the present disclosure, the display panel2000may include the pixel circuit1000.

In display panel according to the embodiments of the present disclosure, the pixel circuit is adopted, so that the clock signal can be divided to generate multiple sampling pulse signals, and the power consumption of the circuit and the layout area are reduced.

FIG. 12is a block diagram of a display device according to embodiments of the present disclosure.

As shown inFIG. 12, in embodiments of the present disclosure, the display device3000may include a housing300and the display panel2000.

In the display device according to the embodiments of the present disclosure, the display panel is adopted, hence, the clock signal can be divided to generate multiple sampling pulse signals, and circuit power consumption and layout area can be reduced.

In some embodiments of the present disclosure, the display device may be, for example, any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, or a navigator.

In addition, the terms of “first” and “second” are merely used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, a feature defined with “first” or “second” may explicitly or implicitly includes at least one of the features. In the descriptions of the present disclosure, the term of “multiple” means at least two, such as two, three, etc., unless otherwise specifically defined.

In the present disclosure, unless otherwise expressly stipulated and defined, the terms of “installed”, “connecting”, “connected”, “coupled”, “fixed” and other terms should be understood in a broad sense. For example, they may represent fixed connection or may represent detachable connection or may represent integrated formation; they may represent mechanical connection or electrical connection; they may represent direct connection or indirect connection through an intermediary; and they may represent internal communication of two components or interaction between two components, unless otherwise specifically defined. For those of ordinary skill in the art, the specific meaning of the above-mentioned terms in the present disclosure may be understood according to specific circumstances.

In the descriptions of this specification, descriptions with reference to the terms of “an embodiment”, “some embodiments”, “examples”, “specific examples”, or “some examples” etc., mean that specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the illustrative representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics as described may be combined in any one or more embodiments or examples in an appropriate manner. In addition, without contradicting each other, those skilled in the art may join and combine different embodiments or examples and features of the different embodiments or examples described in this specification.

Although the embodiments of the present disclosure are illustrated and described in the above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Changes, modifications, substitutions and variations of the above embodiments can be made by those of ordinary shill in the art within the scope of the present disclosure.