SEMICONDUCTOR DEVICE

A semiconductor device includes: a substrate having an obverse and a reverse face; wirings on the obverse face such as a first and a second drive wiring; a semiconductor element connected to the first and second drive wirings; a first drive conductor on the same side as the semiconductor element with respect to the substrate outside of the semiconductor element as viewed in a thickness direction and connected to the first drive wiring; a second drive conductor on the same side as the semiconductor element with respect to the substrate outside of the semiconductor element as viewed in the thickness direction and connected to the second drive wiring; and a sealing resin covering the wirings and the semiconductor element, while also covering the first and second drive conductor such that their faces opposite to the substrate in the thickness direction are exposed. The first and the second drive conductor are separated in a direction parallel to the obverse face. The first drive conductor is smaller in volume than the second drive conductor.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device. The present disclosure also relates to a manufacturing method of the semiconductor device.

BACKGROUND ART

A conventionally known semiconductor device may include a semiconductor element with a plurality of electrodes, an insulation layer covering the reverse face of the semiconductor element on which the plurality of electrodes are formed, and a plurality of wirings formed on the insulation layer and electrically connected to the respective electrodes (see, for example, Patent document 1).

In addition, micro electro mechanical systems (MEMS) have come to be widely utilized in recent years. In the manufacturing process of the MEMS, a silicon (Si) substrate is subjected to micro-fabrication, so that various types of semiconductor elements are formed on the Si substrate. For example, a semiconductor device disclosed in Patent document 2 includes a Si substrate (base material), a semiconductor element (light emitting element) and a wiring layer (wiring pattern), and the semiconductor element is mounted on the Si substrate. The wiring layer is formed on the Si substrate, and electrically connected to the semiconductor element. The wiring layer serves as a terminal, when the semiconductor device is mounted on a circuit board of an electronic device or the like. The wiring layer is formed on the upper face of the Si substrate.

The manufacturing method of the semiconductor device configured as above includes, for example, a step of forming a wiring layer on a Si wafer, a step of mounting a plurality of semiconductor elements on the Si wafer, and a step of dicing the Si wafer into individual pieces each having the semiconductor element mounted thereon.

PRIOR ART DOCUMENT

Patent Documents

SUMMARY OF INVENTION

Problem to be Solved by Invention

The above-noted semiconductor device (paragraph [0002]) may, for example, include a substrate formed of silicon (Si), a plurality of wirings formed on the substrate obverse face, which is one of the faces of the substrate in a thickness direction, a semiconductor element located at a central region of the substrate obverse face and formed on the plurality of wirings, a plurality of conductors located on an outer side of the semiconductor element, and formed on the plurality of wirings, and a sealing resin covering the semiconductor element and the plurality of conductors. The plurality of conductors are exposed from a face of the sealing resin on the opposite side of the substrate in the thickness direction.

The plurality of conductors include a plurality of drive conductors that drive the semiconductor element, and a plurality of control conductors that control the action of the semiconductor element. As viewed in the thickness direction, the plurality of drive conductors are located on both sides of the semiconductor element in a predetermined direction, and aligned in a direction orthogonal to the predetermined direction and the thickness direction. The plurality of control conductors are located on both sides of the semiconductor element in the direction in which the plurality of drive conductors are aligned, and aligned along the predetermined direction.

It is preferable that the plurality of drive conductors are capable of accepting a relatively large current. Accordingly, the volume of each of the drive conductors is made larger than that of the control conductors, to which only a small current is supplied. As result, the electrical resistance of the drive conductor can be reduced.

However, in the case where the drive conductors are made larger in volume, the base material may be warped, upon being heated during the formation process of the sealing resin, after the drive conductors are formed on the wirings formed on the obverse face of the base material, yet to be divided into individual pieces each constituting a plurality of substrates, in the manufacturing process of the semiconductor device. This impedes the base material from being properly transported, or from being accurately divided into individual pieces, thus making it difficult to efficiently manufacture the semiconductor devices.

In the case of the conventional manufacturing method (paragraph [0004]), the base material is diced into individual pieces each having the semiconductor element, after the wiring layer is formed, and therefore no wiring layer is formed on the side face of the Si substrate, obtained after the dicing process. Accordingly, when the semiconductor device is mounted with solder on the circuit board of an electronic device, X-ray inspection equipment has to be employed, to check the bonding condition of the solder.

The present disclosure has been accomplished in view of the aforementioned situation, to provide a semiconductor device that can be stably manufactured. In another aspect, the present disclosure provides a semiconductor device that enables the bonding condition of solder to be easily checked, when the semiconductor device is mounted on a circuit board. In still another aspect, the present disclosure provides a manufacturing method appropriate for manufacturing the mentioned semiconductor device.

Means to Solve the Problem

As an embodiment of a first aspect, the present disclosure provides a semiconductor device including: a substrate having a substrate obverse face and a substrate reverse face that are oriented to opposite sides to each other in a thickness direction; wirings located on the substrate obverse face and including a first drive wiring and a second drive wiring; a semiconductor element electrically connected to the first drive wiring and the second drive wiring; a first drive conductor located on a same side as the semiconductor element with respect to the substrate in a region on an outer side of the semiconductor element as viewed in the thickness direction and electrically connected to the first drive wiring; a second drive conductor located on the same side as the semiconductor element with respect to the substrate in a region on an outer side of the semiconductor element as viewed in the thickness direction and electrically connected to the second drive wiring; and a sealing resin covering the wirings and the semiconductor element, and also covering the first drive conductor and the second drive conductor such that respective faces of the first drive conductor and the second drive conductor that are opposite to the substrate in the thickness direction are exposed from the sealing resin. The first drive conductor and the second drive conductor are aligned with a spacing between each other in a predetermined direction parallel to the substrate obverse face, where the first drive conductor is smaller in volume than the second drive conductor.

The inventor of the present disclosure possesses the knowledge that, with an increase in volume of the first drive conductor and the second drive conductor, a base material constituting a plurality of substrates becomes more likely to be warped upon being heated, for example during formation of the sealing resin, in the manufacturing process of the semiconductor device.

In this semiconductor device, therefore, the first drive conductor is made smaller in volume than the second drive conductor. Such a configuration can minimize the warp of the base material constituting a plurality of substrates, despite being heated, for example during the formation of the sealing resin, in the manufacturing process of the semiconductor device. Consequently, the semiconductor device can be stably manufactured.

As another embodiment of the first aspect, the present disclosure provides a semiconductor device including a substrate having a substrate obverse face and a substrate reverse face, oriented to opposite sides to each other in a thickness direction, wirings located on the substrate obverse face, and including a first drive wiring and a second drive wiring, a semiconductor element mounted on the substrate obverse face, and electrically connected to the first drive wiring and the second drive wiring, a first drive conductor penetrating through the substrate in the thickness direction, so as to be exposed on the substrate obverse face and the substrate reverse face, and electrically connected to the first drive wiring, a second drive conductor penetrating through the substrate in the thickness direction, so as to be exposed on the substrate obverse face and the substrate reverse face, and electrically connected to the second drive wiring, and a sealing resin covering the wirings and the semiconductor element. The first drive conductor and the second drive conductor are aligned, with a spacing between each other, in a predetermined direction as viewed from the substrate reverse face, and the first drive conductor is smaller in volume than the second drive conductor.

The inventor of the present disclosure possesses the knowledge that, with an increase in volume of the first drive conductor and the second drive conductor, a base material constituting a plurality of substrates becomes more likely to be warped, upon being heated, for example during formation of the sealing resin, in the manufacturing process of the semiconductor device.

In this semiconductor device, therefore, the first drive conductor is made smaller in volume than the second drive conductor. Such a configuration can minimize the warp of the base material constituting a plurality of substrates, despite being heated, for example during the formation of the sealing resin, in the manufacturing process of the semiconductor device. Consequently, the semiconductor device can be stably manufactured.

As an embodiment of a second aspect, the present disclosure provides a semiconductor device including a semiconductor element formed with an element electrode, a wiring layer located on one side of the semiconductor element, in a thickness direction of the semiconductor element, and electrically connected to the element electrode, a first columnar electrode protruding from the wiring layer to the other side in the thickness direction, and a resin member covering the semiconductor element. The resin member includes a resin obverse face and a resin reverse face spaced apart from each other in the thickness direction, a first resin side face connected to the resin obverse face, and a second resin side face connected to the resin reverse face. The first resin side face is located on an inner side of the second resin side face, as viewed in the thickness direction. The first columnar electrode includes a first exposed side face exposed from the resin member, a first covered side face covered with the resin member, and a first top face connected to the first exposed side face and flush with the resin obverse face. The first exposed side face is located on an inner side of the first covered side face as viewed in the thickness direction, and flush with the first resin side face. The first covered side face and the second resin side face are each oriented in a first direction orthogonal to the thickness direction, and the first covered side face overlaps with the second resin side face, as viewed in the first direction.

As another embodiment of the second aspect, the present disclosure provides a manufacturing method of a semiconductor device. The method includes a substrate preparation process including preparing a substrate having a substrate obverse face and a substrate reverse face spaced apart from each other in a thickness direction, a wiring layer formation process including forming a wiring layer on the substrate obverse face, a first columnar electrode formation process including forming a first columnar electrode on the wiring layer, an element mounting process including mounting a semiconductor element, a resin formation process including forming a resin member on the substrate so as to cover the semiconductor element, a first cutting process including cutting the first columnar electrode and the resin member, to a halfway position of the first columnar electrode and the resin member respectively, in the thickness direction, thereby forming a first cutaway portion, and a second cutting process including cutting away an entirety of the resin member in the first cutaway portion, in the thickness direction of the resin member. Through the first cutting process, the first exposed side face exposed from the resin member and the first covered side face covered with the resin member are formed on the first columnar electrode, and also the first resin side face is formed on the resin member. Through the second cutting process, the second resin side face is formed on the resin member. The first resin side face is located on the inner side of the second resin side face, as viewed in the thickness direction, and the first exposed side face is located on the inner side of the first covered side face, as viewed in the thickness direction, and flush with the first resin side face. The first covered side face and the second resin side face are each oriented in a first direction orthogonal to the thickness direction, and the first covered side face overlaps with the second resin side face, as viewed in the first direction.

Advantages of Invention

With the mentioned manufacturing method, for example, the semiconductor device can be stably manufactured. In addition, when the semiconductor device is mounted on a circuit board, the bonding condition of the solder can be easily checked visually.

MODE FOR CARRYING OUT INVENTION

Hereafter, a semiconductor device (and a manufacturing method thereof) according to embodiments of a first aspect of the present disclosure, and variations thereof, will be described, with reference toFIG.1toFIG.48. In addition, a semiconductor device (and a manufacturing method thereof) according to some embodiments of a second aspect of the present disclosure, and variations thereof, will be described, with reference toFIG.49toFIG.76. Reference numerals inFIG.1toFIG.48(first aspect) and those inFIG.49toFIG.76(second aspect) are independently used, and therefore the same numeral may represent different elements, and different numerals may represent the same (or similar) element. As to the embodiments of the same aspect, the same or similar elements are given the same numeral, and the description thereof may be skipped, as the case may be. The embodiments of the first and second aspects, and the variations thereof described hereunder merely exemplify the configurations and methods for realizing technical ideas, and are in no way intended to limit the material, shape, structure, location, and size of the elements to those described below. Various modifications may be made to the following embodiments and variations.

Referring toFIG.1toFIG.11, a configuration of a semiconductor device1A according to a first embodiment of the first aspect will be described hereunder. As shown inFIG.1andFIG.2, the semiconductor device1A is formed in a rectangular flat plate shape. The semiconductor device1A includes a substrate10of a flat plate shape, a plurality of terminals20, and a sealing resin30. The plurality of terminals20are provided on a face of the sealing resin30opposite to another face on which the substrate10is located. As shown inFIG.2andFIG.3, the plurality of terminals20are located on an inner side of the peripheral edge of the face of the sealing resin30on which the plurality of terminals20are provided. As is apparent from the above, the semiconductor device1A according to this embodiment is of a surface-mounting type.

As shown inFIG.3andFIG.4, the semiconductor device1A also includes a plurality of wirings40, a plurality of conductors50, and a semiconductor element60. The plurality of wirings40and the plurality of conductors50constitute conduction paths for electrically connecting the semiconductor element60and the plurality of terminals20. The plurality of wirings40are each electrically connected to the semiconductor element60, and the plurality of conductors50are electrically connected to the respective wirings40and the respective terminals20. The plurality of wirings40, the plurality of conductors50, and the semiconductor element60are covered by the sealing resin30.

As shown inFIG.4, the semiconductor element60includes a first circuit61having a plurality of switching circuits that convert power, and a second circuit62having a control circuit that controls the switching circuits of the first circuit61. The second circuit62controls the switching circuits of the first circuit61, according to electrical signals inputted from outside of the semiconductor device1A.

The semiconductor device1A constitutes a part of a power conversion device such as a DC/DC converter. The semiconductor device1A is configured as a resin package to be surface-mounted on a circuit board of the power conversion device. This package is known as a quad flat non-leaded (QFN) package.

In the subsequent description, the thickness direction of the substrate10will be defined as z-direction, and two directions orthogonal to the z-direction, and also orthogonal to each other, will be defined as x-direction and y-direction, respectively. In this embodiment, the semiconductor device1A has a rectangular shape having long sides and short sides, as viewed in the z-direction. In this embodiment, the direction along the long sides of the semiconductor device1A will be defined as the x-direction, and the direction along the short sides will be defined as the y-direction. In addition, for the sake of convenience, a direction from the substrate10toward the sealing resin30in the z-direction will be defined as “upward”, and a direction from the sealing resin30toward the substrate10will be defined as “downward”.

Referring toFIG.1, the substrate10is formed of a monocrystalline intrinsic semiconductor material. In this embodiment, the substrate10is formed of silicon (Si). The substrate10includes a substrate obverse face11and a substrate reverse face12oriented to opposite sides in the z-direction. Between the substrate obverse face11and the substrate reverse face12in the z-direction, four substrate side faces13,14,15, and16are provided. As shown inFIG.4, the substrate side faces13and14are spaced apart from each other in the x-direction, and oriented to opposite sides to each other in the x-direction. The substrate side faces13and14each extend along the y-direction. The substrate side faces15and16are spaced apart from each other in the y-direction, and oriented to opposite sides to each other in the y-direction. The substrate side faces15and16each extend along the x-direction. As shown inFIG.4, the substrate10has a rectangular shape with the long sides extending in the x-direction and the short sides extending in the y-direction, as viewed in the z-direction. Accordingly, the substrate side faces13and14constitute the short sides, and the substrate side faces15and16constitute the long sides of the substrate10, as viewed in the z-direction. Thus, the x-direction may be referred to as a first direction representing the longitudinal direction of the substrate10, and the y-direction may be referred to as a second direction representing the width direction of the substrate10.

As shown inFIG.4andFIG.8toFIG.10, the plurality of wirings40, the plurality of conductors50, and the semiconductor element60are arranged on the substrate obverse face11. As shown inFIG.8toFIG.10, the sealing resin30is provided on the substrate obverse face11, so as to cover the plurality of wirings40, the plurality of conductors50, and the semiconductor element60. In this embodiment, the sealing resin30is formed over the entirety of the substrate obverse face11, as shown inFIG.1andFIG.2. The substrate reverse face12is to constitute the upper face, when the semiconductor device1A is mounted on a circuit board. As shown inFIG.8, an insulation film17is formed on an end face of the substrate10in the z-direction, on the side of the sealing resin30. The insulation film17includes an oxide layer (SiO2) and a nitride layer (Si3N4) stacked on the oxide layer. The substrate obverse face11corresponds to the surface of the insulation film17. Therefore, the plurality of wirings40are formed on the surface of the insulation film17.

As shown inFIG.11andFIG.12, the plurality of wirings40each include an underlying layer40A and a plated layer408. The underlying layer40A is in contact with the insulation film17(substrate obverse face11). The underlying layer40A includes a barrier layer formed in contact with the substrate obverse face11, and a seed layer stacked on the barrier layer. The barrier layer is, for example, formed of titanium (Ti). The seed layer is, for example, formed of copper (Cu). The plated layer408is stacked on the underlying layer40A. The plated layer40B is thicker than the underlying layer40A. In each of the plurality of wirings40, the plated layer40B serves as the primary conduction path. The plated layer40B is, for example, formed of Cu.

As shown inFIG.5, the plurality of wirings40include first power wirings41A and41B, first output wirings42A and428, a first ground wiring43, second power wirings44A and449, second output wirings45A and459, a second ground wiring46, and a plurality of control wirings47. In this embodiment, the first power wirings41A and41B, and the second power wirings44A and449correspond to the first drive wiring, and the first output wirings42A and42B, the first ground wiring43, the second output wirings45A and45B, and the second ground wiring46correspond to the second drive wiring.

The first power wirings41A and419, the first output wirings42A and42B, the first ground wiring43, the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46are each electrically connected to the first circuit61(seeFIG.4). The first power wirings41A and41B and the second power wirings44A and44B each serve to supply a current to the first circuit61of the semiconductor element60. The first output wirings42A and42B and the second output wirings45A and45B each serve to supply a current outputted from the first circuit61of the semiconductor element60to outside of the semiconductor device1A. The first ground wiring43and the second ground wiring46each serve to provide the ground for the first circuit61. The plurality of control wirings47are each electrically connected to the second circuit62(seeFIG.4) of the semiconductor element60. The plurality of control wirings47each serve to input an electrical signal from outside of the semiconductor device1A to the second circuit62, or to output an electrical signal outputted from the second circuit62to outside of the semiconductor device1A.

As shown inFIG.5, the first power wirings41A and41B, the first output wirings42A and42B, and the first ground wiring43are located in the vicinity of the substrate side face13, in the x-direction. The first power wirings41A and41B, the first output wirings42A and42B, and the first ground wiring43are located at the same position in the x-direction, and aligned in the y-direction with a spacing between each other. The first ground wiring43is located at the central position in the y-direction, among the first power wirings41A and41B, the first output wirings42A and428, and the first ground wiring43. In this embodiment, the first ground wiring43is located in the central region of the substrate10in the y-direction. The first output wirings42A and42B are separately located on the respective sides of the first ground wiring43in the y-direction. In this embodiment, the first output wiring42A is located on the side of the substrate side face15with respect to the first ground wiring43, in the y-direction. The first output wiring420is located on the side of the substrate side face16with respect to the first ground wiring43, in the y-direction. The first power wiring41A is located on the opposite side of the first ground wiring43with respect to the first output wiring42A, in the y-direction. The first power wiring41B is located on the opposite side of the first ground wiring43with respect to the first output wiring42B, in the y-direction. Thus, the first power wirings41A and41B are separately located on the respective outer sides of the first output wirings42A and42B and the first ground wiring43in the y-direction.

The first power wirings41A and41B, the first output wirings42A and428, and the first ground wiring43each extend in the x-direction. To be more detailed, the first power wirings41A and41B, the first output wirings42A and42B, and the first ground wiring43each extend along the x-direction, from one of the end portions of the substrate10in the x-direction on the side of the substrate side face13, toward the center of the substrate10in the x-direction. As shown inFIG.5, the first power wirings41A and41B, the first output wirings42A and42B, and the first ground wiring43each extend from the outer side of the semiconductor element60to the inner side thereof, in the x-direction. Therefore, the first power wirings41A and41B, the first output wirings42A and42B, and the first ground wiring43each include a portion overlapping with the semiconductor element60, as viewed in the z-direction.

As shown inFIG.5, the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46are located in the vicinity of the substrate side face13, in the x-direction. The second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46are located at the same position in the x-direction, and aligned in the y-direction with a spacing between each other. The second ground wiring46is located at the central position in the y-direction, among the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46. In this embodiment, the second ground wiring46is located in the central region of the substrate10in the y-direction. The second output wirings45A and45B are separately located on the respective sides of the second ground wiring46in the y-direction. In this embodiment, the second output wiring45A is located on the side of the substrate side face15with respect to the second ground wiring46, in the y-direction. The second output wiring45B is located on the side of the substrate side face15with respect to the second ground wiring46, in the y-direction. The second power wiring44A is located on the opposite side of the second ground wiring46with respect to the second output wiring45A, in the y-direction. The second power wiring44B is located on the opposite side of the second ground wiring46with respect to the second output wiring45B, in the y-direction. Thus, the second power wirings44A and44B are separately located on the respective outer sides of the second output wirings45A and45B and the second ground wiring46in the y-direction.

The second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46each extend in the x-direction. To be more detailed, the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46each extend along the x-direction, from the other end portion of the substrate10in the x-direction on the side of the substrate side face14, toward the center of the substrate10in the x-direction. As shown inFIG.5, the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46each extend from the outer side of the semiconductor element60to the inner side thereof, in the x-direction. Therefore, the second power wirings44A and440, the second output wirings45A and45B, and the second ground wiring46each include a portion overlapping with the semiconductor element60, as viewed in the z-direction.

As shown inFIG.5, the first power wirings41A and41B, the first output wirings42A and42B, and the first ground wiring43are spaced apart from the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46, in the x-direction. The first power wiring41A is located so as to overlap with the second power wiring44A, and the first power wiring41B is located so as to overlap with the second power wiring44B, as viewed in the x-direction. The first power wiring42A is located so as to overlap with the second power wiring45A, and the first power wiring42B is located so as to overlap with the second power wiring45B, as viewed in the x-direction. The first ground wiring43is located so as to overlap with the second ground wiring46, as viewed in the x-direction. As shown inFIG.5, further, the first power wirings41A and41B, the first output wirings42A and42B, and the first ground wiring43, and also the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46are each located so as to overlap with the semiconductor element60, as viewed in the x-direction.

As shown inFIG.5, the plurality of control wirings47are aligned along the end portions of the substrate10in the y-direction, with a spacing between each other in the x-direction. The plurality of control wirings47are separately located on both sides of the first power wirings41A and41B, the first output wirings42A and428, and the first ground wiring43in the y-direction. Further, the plurality of control wirings47are separately located on both sides of the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46, in the y-direction. For the sake of convenience, the plurality of control wirings47aligned along one of the end portions of the substrate10in the y-direction on the side of the substrate side face15will be referred to as “control wirings47A”, and the plurality of control wirings47aligned along the other end portion of the substrate10in the y-direction on the side of the substrate side face16will be referred to as “control wirings47B”. The control wirings47A each include a wiring end section47aof a rectangular shape, located at the other end portion of the substrate10in the y-direction on the side of the substrate side face16, a connecting wiring section47bextending from the wiring end section47atoward the inner region of the substrate10, and a connecting end section47clocated at the distal end of the connecting wiring section47b. The control wirings478each include a wiring end section47aof a rectangular shape, located at the end portion of the substrate10in the y-direction on the side of the substrate side face15, a connecting wiring section47bextending from the wiring end section47atoward the inner region of the substrate10, and a connecting end section47clocated at the distal end of the connecting wiring section47b. As shown inFIG.5, the respective wiring end sections47aof the control wirings47A and47B are located on the outer side of the semiconductor element60, in the y-direction. The wiring end sections47aof the control wirings47A are located between the semiconductor element60and the substrate side face15in the y-direction, as viewed in the z-direction. The wiring end sections47aof the control wirings47B are located between the semiconductor element60and the substrate side face16in the y-direction, as viewed in the z-direction. The respective connecting wiring sections47bof the control wirings47A and47B extend from outside of the semiconductor element60to the inner side thereof, as viewed in the z-direction. The respective connecting end sections47cof the control wirings47A and47B are located so as to overlap with the semiconductor element60, as viewed in the z-direction.

As described above, the semiconductor device1A is what is known as a fan-out semiconductor device, in which the plurality of wirings40each extend from the position overlapping with the semiconductor element60in the z-direction, to outside thereof, and the plurality of conductors50are located on the outer side of the semiconductor element60.

As shown inFIG.4andFIG.8, the semiconductor element60is mounted on the plurality of wirings40. As shown inFIG.8, the semiconductor element60includes an element obverse face60sand an element reverse face60r, oriented to the opposite sides in the z-direction. The element obverse face60sis oriented to the same side as is the substrate obverse face11in the z-direction, and the element reverse face60ris oriented to the same side as is the substrate reverse face12in the z-direction. On the element reverse face60r, an insulation film60xand a plurality of element electrodes60aare formed. As shown inFIG.4andFIG.8, the semiconductor element60according to this embodiment is of a flip-chip mounting type.

As shown inFIG.8,FIG.11, andFIG.12, a plurality of element electrodes60aare bonded to the plurality of wirings40, via a solder layer48. The plurality of element electrodes60aeach include a conductive section60band a barrier layer60c. The conductive section60bis, for example, formed of Cu. The barrier layer60cis formed of a nickel (Ni) layer. The barrier layer60cis stacked on the conductive section60b, so as to cover the end face of the conductive section60b. The presence of the barrier layer60cin the element electrode60asuppresses the conductive section60b, which is formed of Cu, from permeating into the solder layer48. Here, the barrier layer60cmay include a Ni layer, a palladium (Pd) layer, and a gold (Au) layer stacked on each other.

The insulation film60xcovers the element reverse face60r, and also the peripheral edge of the element electrode60a. The insulation film60xis, for example, formed of a polyimide resin. The insulation film60xcovers a part of the element electrode60a, so as to expose a part of the surface of the element electrode60a, as a connection terminal. Here, the insulation film60xmay be formed of silicon nitride (SiN).

As shown inFIG.4toFIG.10, the plurality of conductors50are respectively located on the plurality of wirings40. As shown inFIG.4, the plurality of conductors50are located on the outer side of the semiconductor element60, as viewed in the z-direction. In other words, the semiconductor element60is surrounded by the plurality of conductors50. As shown inFIG.8toFIG.10, the conductor50is stacked on the face of the wiring40on the opposite side of the substrate10, in the z-direction. Accordingly, the conductor50may be described as protruding in the direction away from the substrate obverse face11, in the z-direction. As shown inFIG.4andFIG.5, the plurality of conductors50are located on the inner side of the substrate side faces13to16, as viewed in the z-direction. In other words, the plurality of conductors50are located so as to overlap with the substrate obverse face11, as viewed in the z-direction. Therefore, as shown inFIG.3, the plurality of conductors50are located on the inner side of the peripheral edge of the sealing resin30, as viewed in the z-direction. The plurality of conductors50are each formed of Cu. The plurality of conductors50each include a top face50A, oriented to the same side as is the substrate obverse face11, in the z-direction. The top face50A of each of the plurality of conductors50is exposed from the sealing resin30, in the z-direction.

As shown inFIG.4, the plurality of conductors50include first power conductors51A and51B, first output conductors52A and52B, a first ground conductor53, second power conductors54A and54B, second output conductors55A and55B, a second ground conductor56, and a plurality of control conductors57. The first power conductors51A and51B, the first output conductors52A and52B, the first ground conductor53, the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56are each electrically connected to the first circuit61of the semiconductor element60. The plurality of control conductors57are electrically connected to the second circuit62of the semiconductor element60. In this embodiment, the first power conductors51A and51B and the second power conductors54A and54B correspond to the first drive conductor, and the first output conductors52A and52B, the first ground conductor53, the second output conductors55A and55B, and the second ground conductor56correspond to the second drive conductor.

As shown inFIG.4, the first power conductors51A and51B, the first output conductors52A and52B, the first ground conductor53, the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56each have a top face50A having a rectangular shape, with the long sides extending in the x-direction, and the short sides extending in the y-direction, as viewed in the z-direction. The control conductors57each have a rectangular shape, with the sides extending in the x-direction and the sides extending in the y-direction, as viewed in the z-direction.

Here, the shape of the top face50A of the first power conductors51A and51B, the first output conductors52A and528, the first ground conductor53, the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56, viewed in the z-direction, may be modified as desired. For example, the first power conductors51A and51B, the first output conductors52A and52B, the first ground conductor53, the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56may each have a top face50A having an elliptical shape, with the major axis extending in the x-direction and the minor axis extending in the y-direction, as viewed in the z-direction. The control conductors57may each have a circular or elliptical shape, as viewed in the z-direction.

The first power conductor51A is electrically connected to the first power wiring41A of the wiring40. Accordingly, the first power conductor51A is electrically connected to the first circuit61, via the first power wiring41A. The first power conductor51B is electrically connected to the first power wiring41B of the wiring40. Accordingly, the first power conductor51B is electrically connected to the first circuit61, via the first power wiring41B.

The first output conductor52A is electrically connected to the first output wiring42A of the wiring40. Accordingly, the first output conductor52A is electrically connected to the first circuit61, via the first output wiring42A. The first output conductor52B is electrically connected to the first output wiring42B of the wiring40. Accordingly, the first output conductor52B is electrically connected to the first circuit61, via the first output wiring42B.

The first ground conductor53is electrically connected to the first ground wiring43of the wiring40. Accordingly, the first ground conductor53is electrically connected to the first circuit61, via the first ground wiring43.

The second power conductor54A is electrically connected to the second power wiring44A of the wiring40. Accordingly, the second power conductor54A is electrically connected to the first circuit61, via the second power wiring44A. The second power conductor54B is electrically connected to the second power wiring44B of the wiring40. Accordingly, the second power conductor54B is electrically connected to the first circuit61, via the second power wiring44B.

The second output conductor55A is electrically connected to the second output wiring45A of the wiring40. Accordingly, the second output conductor55A is electrically connected to the first circuit61, via the second output wiring45A. The second output conductor55B is electrically connected to the second output wiring45B of the wiring40. Accordingly, the second output conductor55B is electrically connected to the first circuit61, via the second output wiring453.

The second ground conductor56is electrically connected to the second ground wiring46of the wiring40. Accordingly, the second ground conductor56is electrically connected to the first circuit61, via the second ground wiring46.

The plurality of control conductors57are electrically connected to the respective control wirings47of the wiring40. Accordingly, the plurality of control conductors57are electrically connected to the second circuit62, via the plurality of control wirings47.

The first power conductors51A and51B, the first output conductors52A and52B, and the first ground conductor53are located along one of the end portions of the substrate obverse face11in the x-direction, on the side of the substrate side face13. The first power conductors51A and51B, the first output conductors52A and52B, and the first ground conductor53are located at the same position in the x-direction, and aligned in the y-direction with a spacing between each other. The second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56are located along the other end portion of the substrate obverse face11in the x-direction, on the side of the substrate side face14. The second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56are located at the same position in the x-direction, and aligned in the y-direction with a spacing between each other.

As described above, the first power conductors51A and51B, the first output conductors52A and528, and the first ground conductor53are aligned in the y-direction, corresponding to the width direction of the substrate10, and extend in the x-direction corresponding to the longitudinal direction of the substrate10. The second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56are aligned in the y-direction, corresponding to the width direction of the substrate10, and extend in the x-direction corresponding to the longitudinal direction of the substrate10.

As shown inFIG.1andFIG.2, the sealing resin30is formed in a rectangular flat plate shape, and in contact with the substrate obverse face11. The sealing resin30is thinner than the substrate10. In other words, substrate10is thicker than the sealing resin30. The sealing resin30is formed of an electrically insulative resin material. The sealing resin30is, for example, formed of a thermosetting resin. In this embodiment, the sealing resin30is formed of a black epoxy resin.

As shown inFIG.2,FIG.3, andFIG.8toFIG.10, the sealing resin30includes a mounting surface31oriented to the same side as is the substrate obverse face11in the z-direction, and four resin side faces32to35. As shown inFIG.3, the resin side faces32and33are spaced apart from each other in the x-direction, and oriented to the opposite sides to each other in the x-direction. The resin side faces32and33each extend along the y-direction. The resin side faces34and35are spaced apart from each other in the y-direction, and oriented to the opposite sides to each other in the y-direction. The resin side faces34and35each extend along the x-direction. As shown inFIG.3, the sealing resin30has a rectangular shape with the long sides extending in the x-direction, and the short sides extending in the y-direction, as viewed in the z-direction. Accordingly, the resin side faces32and33constitute the short sides, and the resin side faces34and35constitute the long sides, of the sealing resin30viewed in the z-direction. In this embodiment, as shown inFIG.9, the substrate side face13and the resin side face32are flush with each other, and the substrate side face14and the resin side face33are flush with each other. Likewise, as shown inFIG.10, the substrate side face15and the resin side face34are flush with each other, and the substrate side face16and the resin side face35are flush with each other.

As shown inFIG.3andFIG.8toFIG.10, the mounting surface31is to oppose the circuit board, when the semiconductor device1A is mounted thereon. The top face50A of each of the plurality of conductors50is exposed from the mounting surface31. On the top face50A of the plurality of conductors50, exposed from the mounting surface31, the plurality of terminals20are respectively provided. Here, the top face50A of each of the conductors50is oriented in the same direction as is the mounting surface31(substrate obverse face11), in the z-direction.

As shown inFIG.2andFIG.3, the plurality of terminals20are each exposed to outside of the semiconductor device1A. In other words, although the respective top faces50A of the plurality of conductors50are exposed from the mounting surface31as shown inFIG.3andFIG.8toFIG.10, the top faces50A are respectively covered with the plurality of terminals20, and therefore the top faces50A are not exposed to outside of the semiconductor device1A. By bonding the plurality of terminals20to the circuit board, for example via solder, the semiconductor device1A can be mounted on the circuit board. The plurality of terminals20are each formed of a plurality of metal layers, namely a Ni layer, a Pd layer, and an Au layer stacked in this order from the side of the top face50A of the plurality of conductors50.

Hereunder, a detailed configuration of the semiconductor element60, and a detailed connection arrangement among the semiconductor element60, the plurality of wirings40, the plurality of conductors50, and the plurality of terminals20, will be described. In this embodiment, as shown inFIG.4, the first circuit61includes a first switching unit61A, a second switching unit618, a third switching unit61C, and a fourth switching unit61D. The switching units61A to61D each include two switching elements connected in series to act as a plurality of switching circuit that convert power, and two driver circuits that drive the respective switching element. The second circuit62includes a control circuit that controls, for example, each of the switching units61A to61D. For example, a metal-oxide-semiconductor field-effect transistor (MOSFET) is employed as the switching element. In this case, in each of the switching units61A to61D, the source of the MOSFET constituting the upper arm and the drain of the MOSFET constituting the lower arm are connected. When the MOSFET is employed as the switching element, the driver circuits each provide electrical signals for controlling the action of the MOSFET, to the gate of the MOSFET. Here, the switching element may be constituted of a different transistor such as an insulated gate bipolar transistor (IGBT), without limitation to the MOSFET. In addition, the driver circuit of the first switching unit61A may include a driver circuit that drives one of the two switching elements of the first switching unit61A, and another driver circuit that drives the other switching element. The driver circuit of each of the switching units61B to61D may also be modified in the same way as that of the first switching unit61A.

In this embodiment, as shown inFIG.4, a circuit region RD, on which the second circuit62is formed, has an H-shape including two recesses RD1and RD2receding in the opposite directions to each other in the x-direction, as viewed in the z-direction. The circuit region RD is formed generally over the entirety of the semiconductor element60, as viewed in the z-direction. The recess RD1is a rectangular recess, receding from one of the edges of the circuit region RD in the x-direction on the side of the substrate side face13, toward the center of the semiconductor element60in the x-direction. The recess RD2is a rectangular recess, receding from the other edge of the circuit region RD in the x-direction on the side of the substrate side face14, toward the center of the semiconductor element60in the x-direction.

Hereinafter, a circuit region where the first switching unit61A is formed will be referred to as circuit region RSA, a circuit region where the second switching unit61B is formed will be referred to as circuit region RSB, a circuit region where the third switching unit61C is formed will be referred to as circuit region RSC, and a circuit region where the fourth switching unit61D is formed will be referred to as circuit region RSD. In this embodiment, the circuit regions RSA to RSD each have a rectangular shape, as viewed in the z-direction. Further, the circuit regions RSA to RSD have the same size as one another, as viewed in the z-direction.

The circuit regions RSA and RSB are each located inside the recess RD1of the circuit region RD. The circuit regions RSA and RSB are located at the same position in the x-direction, and aligned in the y-direction with a spacing between each other. The circuit region RSA is located closer to the substrate side face15in the y-direction, than is the circuit region RSB. In other words, circuit region RSB is located closer to the substrate side face16in the y-direction, than is the circuit region circuit region RSA.

The circuit regions RSC and RSD are each located inside the recess RD2of the circuit region RD. The circuit regions RSC and RSD are located at the same position in the x-direction, and aligned in the y-direction with a spacing between each other. The circuit region RSC is located closer to the substrate side face15in the y-direction, than is the circuit region RSD. In other words, circuit region RSD is located closer to the substrate side face16in the y-direction, than is the circuit region circuit region RSC. As viewed in the x-direction, the circuit region RSC overlaps with the circuit region RSA, and the circuit region RSD overlaps with the circuit region RSB.

As shown inFIG.4, the second circuit62is electrically connected to one of the control wirings47, at each of the four corners of the semiconductor element60, as viewed in the z-direction. Hereinafter, regarding the circuit region RD where the second circuit62is formed, a region close to each of the substrate side faces13and15will be referred to as first region R1, a region close to each of the substrate side faces13and16will be referred to as second region R2, a region close to each of the substrate side faces14and15will be referred to as third region R3, and a region close to each of the substrate side faces14and16will be referred to as fourth region R4.

The control wirings47A are connected to the second circuit62, in the first region R1and the third region R3. One of the control wirings47A located on the side of the substrate side face13is connected to the second circuit62in the first region R1, and the other control wiring47A located on the side of the substrate side face14is connected to the second circuit62in the third region R3. The control wirings47B are connected to the second circuit62, in the second region R2and the fourth region R4. One of the control wirings47B located on the side of the substrate side face13is connected to the second circuit62in the second region R2, and the other control wiring47B located on the side of the substrate side face14is connected to the second circuit62in the fourth region R4.

As shown inFIG.4, the first switching unit61A is electrically connected to the first power wiring41A, the first output wiring42A, and the first ground wiring43. The second switching unit618is electrically connected to the first power wiring41B, the first output wiring42B, and the first ground wiring43.

As shown inFIG.6, the first ground wiring43extends along the x-direction. In this embodiment, the width of the first ground wiring43constant, along the x-direction. The first ground wiring43is wider than the connecting wiring section47bof the control wiring47. Here, the width of the first ground wiring43refers to the length of the portion thereof extending in the direction orthogonal to the direction in which the first ground wiring43extends, as viewed in the z-direction. In this embodiment, the width of the first ground wiring43corresponds to the length thereof in the y-direction. At the central portion of the first ground wiring43in the y-direction, a slit43ais formed so as to extend in the x-direction. The slit43aextends in the x-direction over the range between the edge of the first ground wiring43on the side of the center of the substrate10in the x-direction, and a position on the side of the substrate side face13. The portions of the first ground wiring43, divided by the slit43aso as to be spaced apart from each other in the y-direction, will be respectively referred to as a first wiring section43band a second wiring section43c. The first wiring section43bis located closer to the first output wiring42A, than is the second wiring section43c. In other words, the second wiring section43cis located closer to the first output wiring42B than is the first wiring section43b.

As viewed in the z-direction, on the portion of the first wiring section43boverlapping with the semiconductor element60, a plurality of (in this embodiment, five) element electrodes60aare bonded. These element electrodes60aare located at the same position in the y-direction, and aligned in the x-direction with a spacing between each other.

As viewed in the z-direction, on the portion of the first wiring section43coverlapping with the semiconductor element60, a plurality of (in this embodiment, five) element electrodes60aare bonded. These element electrodes60aare located at the same position in the y-direction, and aligned in the x-direction with a spacing between each other.

The first output wiring42A includes a wide wiring section42awhich is relatively wider, and a narrow wiring section42bwhich is relatively narrower. The first output wiring42A is wider than the connecting wiring section47bof the control wiring47. The width of the first output wiring42A refers to the length of the portion thereof extending in the direction orthogonal to the direction in which the first output wiring42A extends, as viewed in the z-direction.

The wide wiring section42ais located closer to the substrate side face13than is the narrow wiring section42b, in the x-direction. In other words, the narrow wiring section42bis located closer to the semiconductor element60than is the wide wiring section42ain the x-direction. The wide wiring section42ais located closer to the substrate side face13than is the semiconductor element60, as viewed in the z-direction. The narrow wiring section42boverlaps with the semiconductor element60, as viewed in the z-direction.

The narrow wiring section42bextends along the x-direction. To the narrow wiring section42b, a plurality of (in this embodiment, ten) element electrodes60aare bonded. As shown inFIG.5, two rows of the element electrodes60a, each including five of the ten element electrodes60alocated at the same position in the y-direction and aligned in the x-direction with a spacing between each other, are aligned in the y-direction with a spacing between each other.

The wide wiring section42aincludes a sloped section42c, formed adjacent to the narrow wiring section42b, so as to be narrower in the direction toward the narrow wiring section42bin the x-direction. The sloped section42cis formed along the edge of the wide wiring section42aon the side of the first power wiring41A, in the y-direction. Accordingly, the first output wiring42A includes a recessed region42ddefined by the sloped section42cand the narrow wiring section42b, so as to recede in the y-direction.

The first power wiring41A includes a wide wiring section41awhich is relatively wider, a narrow wiring section41bwhich is relatively narrower, and a connecting wiring section41cconnecting between the wide wiring section41aand the narrow wiring section41b. The first power wiring41A is wider than the connecting wiring section47bof the control wiring47. Here, the width of the first power wiring41A refers to the length of the portion thereof extending in the direction orthogonal to the direction in which the first power wiring41A extends, as viewed in the z-direction. The width of the connecting wiring section47brefers to the length of the portion thereof extending in the direction orthogonal to the direction in which the connecting wiring section47bextends, as viewed in the z-direction.

The wide wiring section41ais located closer to the substrate side face13than is the narrow wiring section41b, in the x-direction. In other words, the narrow wiring section41bis located closer to the semiconductor element60than is the wide wiring section41a, in the x-direction. The wide wiring section41ais located closer to the substrate side face13, than is the semiconductor element60. The wide wiring section41aextends along the x-direction, from the end portion of the substrate obverse face11on the side of the substrate side face13. The wide wiring section41ais narrower than the wide wiring section42aof the first output wiring42A. In other words, the wide wiring section42ais wider than the wide wiring section41aof the first power wiring41A. The width of the wide wiring section41arefers to the length of the portion thereof extending in the direction orthogonal to the direction in which the wide wiring section41aextends, as viewed in the z-direction. In this embodiment, the width of the wide wiring section41acorresponds to the length thereof in the y-direction. The width of the wide wiring section42arefers to the length of the portion thereof extending in the direction orthogonal to the direction in which the wide wiring section42aextends, as viewed in the z-direction. In this embodiment, the width of the wide wiring section42acorresponds to the length thereof in the y-direction.

The narrow wiring section41bis located closer to the first output wiring42A than is the wide wiring section41a, in the y-direction. The narrow wiring section41boverlaps with the semiconductor element60, as viewed in the z-direction. The narrow wiring section41bextends along the x-direction. The narrow wiring section41bis narrower than the narrow wiring section42bof the first output wiring42A. In other words, the narrow wiring section42bis wider than the narrow wiring section41bof the first power wiring41A. The width of the narrow wiring section41brefers to the length of the portion thereof extending in the direction orthogonal to the direction in which the narrow wiring section41bextends, as viewed in the z-direction. In this embodiment, the width of the narrow wiring section41bcorresponds to the length thereof in the y-direction. The width of the narrow wiring section42brefers to the length of the portion thereof extending in the direction orthogonal to the direction in which the narrow wiring section42bextends, as viewed in the z-direction. In this embodiment, the width of the narrow wiring section42bcorresponds to the length thereof in the y-direction.

To the narrow wiring section41b, a plurality of (in this embodiment, five) element electrodes60aare bonded. These element electrodes60aare located at the same position in the y-direction, and aligned in the x-direction with a spacing between each other.

The connecting wiring section41cobliquely extends, so as to be closer to the first output wiring42A in the y-direction, in the direction from the wide wiring section41atoward the narrow wiring section41bin the x-direction. A part of the connecting wiring section41coverlaps with the semiconductor element60, as viewed in the z-direction. As viewed in the y-direction, the connecting wiring section41coverlaps with the sloped section42cof the first output wiring42A. The width of the connecting wiring section41c(length thereof in the y-direction) is wider than that of the narrow wiring section41b.

The first power wiring41A includes a recessed region41ddefined by the narrow wiring section41band the connecting wiring section41c, so as to recede in the y-direction. The recessed region41doverlaps with the semiconductor element60, as viewed in the z-direction. In the recessed region41d, the respective connecting end sections47cof five of the control wirings47A, located on the side of the substrate side face13, are located. By forming thus the recessed region41dto secure the space for locating the connecting end sections47cof the control wirings47A, the portion of the first power wiring41A on the side of the center of the substrate10in the x-direction becomes narrower. For such reason, the narrow wiring section41bof the first power wiring41A is formed.

The narrow wiring section41band the connecting wiring section41care located inside the recessed region42dof the first output wiring42A. This allows the narrow wiring section41bto be located closer to the center of the substrate10in the y-direction, than is the wide wiring section41a, thereby enabling the connecting end sections47cof the five control wirings47A close to the substrate side face13, to be located so as to overlap with the first region R1(seeFIG.4) of the semiconductor element60, as viewed in the z-direction.

The first output wiring42B is symmetrical to the first output wiring42A, with respect to an imaginary center line of the substrate obverse face11, passing the center thereof in the y-direction and extending in the x-direction. Accordingly, the first output wiring42B includes, like the first output wiring42A, the wide wiring section42a, the narrow wiring section42b, and the sloped section42c. The first output wiring42B also includes the recessed region42d. To the narrow wiring section42b, ten element electrodes60aare bonded. The arrangement pattern of these ten element electrodes60ais the same as that of the ten element electrodes60aon the narrow wiring section42bof the first output wiring42A.

The first power wiring41B is symmetrical to the first power wiring41A, with respect to the imaginary center line of the substrate obverse face11, passing the center thereof in the y-direction and extending in the x-direction. Accordingly, the first power wiring41B includes, like the first power wiring41A, the wide wiring section41a, the narrow wiring section41b, and the connecting wiring section41c. To the narrow wiring section41b, five element electrodes60aare bonded. The arrangement pattern of these five element electrodes60ais the same as that of the five element electrodes60aon the narrow wiring section41bof the first power wiring41A. The narrow wiring section41band the connecting wiring section41care, like the narrow wiring section41band the connecting wiring section41cof the first power wiring41A, each located inside the recessed region42dof the first output wiring42B. Therefore, the connecting end sections47cof the four control wirings47B close to the substrate side face13can be located so as to overlap with the second region R2(seeFIG.4) of the semiconductor element60, as viewed in the z-direction.

As shown inFIG.6, the area of the first output wiring42A viewed in the z-direction, and the area of the first ground wiring43viewed in the z-direction are larger than the area of the first power wiring41A viewed in the z-direction. The area of the first output wiring42B viewed in the z-direction, and the area of the first ground wiring43viewed in the z-direction are larger than the area of the first power wiring413viewed in the z-direction.

As shown inFIG.4, the third switching unit61C is electrically connected to the second power wiring44A, the second output wiring45A, and the second ground wiring46. The fourth switching unit61D is electrically connected to the second power wiring44B, the second output wiring45B, and the second ground wiring46.

As shown inFIG.7, the second ground wiring46extends along the x-direction. To be more detailed, the shape of the second ground wiring46viewed in the z-direction is symmetrical to that of the first ground wiring43viewed in the z-direction, with respect to an imaginary line, passing the center of the substrate10in the x-direction and extending in the y-direction. Accordingly, the second ground wiring46includes a slit46acorresponding to the slit43aof the first ground wiring43, and a first wiring section46band a second wiring section46c, respectively corresponding to the first wiring section43band the second wiring section43c. The first wiring section46bis located closer to the second output wiring45A, than is the second wiring section46c. In other words, the second wiring section46cis located closer to the second output wiring45B, than is the first wiring section46b.

As viewed in the z-direction, on the portion of the first wiring section46boverlapping with the semiconductor element60, a plurality of (in this embodiment, five) element electrodes60aare bonded. These element electrodes60aare located at the same position in the y-direction, and aligned in the x-direction with a spacing between each other.

As viewed in the z-direction, on the portion of the second wiring section46coverlapping with the semiconductor element60, a plurality of (in this embodiment, five) element electrodes60aare bonded. These element electrodes60aare located at the same position in the y-direction, and aligned in the x-direction with a spacing between each other.

The second output wiring45A extends along the x-direction. To be more detailed, the shape of the second output wiring45A viewed in the z-direction is symmetrical to that of the first output wiring42A viewed in the z-direction, with respect to the imaginary line, passing the center of the substrate10in the x-direction and extending in the y-direction. Accordingly, the second output wiring45A includes a wide wiring section45a, a narrow wiring section45b, and a sloped section45c, respectively corresponding to the wide wiring section42a, the narrow wiring section42b, and the sloped section42cof the first output wiring42A. Further, the second output wiring45A includes a recessed region45dcorresponding to the recessed region42dof the first output wiring42A.

The wide wiring section45ais located closer to the substrate side face14than is the narrow wiring section45b, in the x-direction. In other words, the narrow wiring section45bis located closer to the semiconductor element60(seeFIG.4), than is the wide wiring section45a, in the x-direction. The wide wiring section45ais located closer to the substrate side face14, than is the semiconductor element60, as viewed in the z-direction. The narrow wiring section45boverlaps with the semiconductor element60, as viewed in the z-direction.

To the narrow wiring section45b, a plurality of (in this embodiment, ten) element electrodes60aare bonded. The arrangement pattern of these element electrodes60ais the same as that of the ten element electrodes60aon the first output wiring42A.

The second power wiring44A extends along the x-direction. To be more detailed, the shape of the second power wiring44A viewed in the z-direction is symmetrical to that of the first power wiring41A viewed in the z-direction, with respect to the imaginary line, passing the center of the substrate10in the x-direction and extending in the y-direction. Accordingly, the second power wiring44A includes a wide wiring section44a, a narrow wiring section44b, and a connecting wiring section44c, respectively corresponding to the wide wiring section41a, the narrow wiring section41b, and the connecting wiring section41cof the first power wiring41A. Further, the second power wiring44A includes a recessed region44dcorresponding to the recessed region41dof the first power wiring41A.

The wide wiring section44ais located closer to the substrate side face14than is the narrow wiring section44b, in the x-direction. In other words, the narrow wiring section44bis located closer to the semiconductor element60than is the wide wiring section44a, in the x-direction. The wide wiring section44aincludes a portion located closer to the substrate side face14, than is the semiconductor element60.

The narrow wiring section44bis located closer to the second output wiring45A than is the wide wiring section44a, in the y-direction. To the narrow wiring section44b, a plurality of (in this embodiment, five) element electrodes60aare bonded. These element electrodes60aare located at the same position in the y-direction, and aligned in the x-direction with a spacing between each other.

The connecting wiring section44cobliquely extends, so as to be closer to the second output wiring45A in the y-direction, in the direction from the wide wiring section44atoward the narrow wiring section44bin the x-direction. In the recessed region44d, the respective connecting end sections47cof four of the control wirings47A, located on the side of the substrate side face14, are located. By forming thus the recessed region44dto secure the space for locating the connecting end sections47cof the control wirings47A, the portion of the second power wiring44A on the side of the center of the substrate10in the x-direction becomes narrower. For such reason, the narrow wiring section44bof the second power wiring44A is formed.

The narrow wiring section44band the connecting wiring section44care located in the recessed region44dof the second output wiring45A. This allows the narrow wiring section44bto be located closer to the center of the substrate10in the y-direction, than is the wide wiring section44a, thereby enabling the connecting end sections47cof the four control wirings47A close to the substrate side face14, to be located so as to overlap with the third region R3(seeFIG.4) of the semiconductor element60, as viewed in the s-direction.

The second output wiring45B is symmetrical to the second output wiring45A, with respect to the imaginary center line of the substrate obverse face11, passing the center thereof in the y-direction and extending in the x-direction. Accordingly, the second output wiring45B includes, like the second output wiring45A, the wide wiring section45a, the narrow wiring section45b, and the sloped section45c. The second output wiring45B also includes the recessed region45d. To the narrow wiring section45b, ten element electrodes60aare bonded. The arrangement pattern of these ten element electrodes60ais the same as that of the ten element electrodes60aon the narrow wiring section45bof the second output wiring45A.

The second power wiring44B is symmetrical to the second power wiring44A, with respect to the imaginary center line of the substrate obverse face11, passing the center thereof in the y-direction and extending in the x-direction. Accordingly, the second power wiring440includes, like the second power wiring44A, the wide wiring section44a, the narrow wiring section44b, and the connecting wiring section44c. The wide wiring section44ais located closer to the substrate side face14than is the semiconductor element60, as viewed in the z-direction. The narrow wiring section44boverlaps with the semiconductor element60, as viewed in the z-direction.

To the narrow wiring section44b, five element electrodes60aare bonded. The arrangement pattern of these five element electrodes60ais the same as that of the five element electrodes60aon the narrow wiring section44bof the second power wiring44A. The narrow wiring section44band the connecting wiring section44care, like the narrow wiring section44band the connecting wiring section44cof the second power wiring44A, each located inside the recessed region45dof the second output wiring45B. Therefore, the connecting end sections47cof the four control wirings47B close to the substrate side face14can be located so as to overlap with the fourth region R4(seeFIG.4) of the semiconductor element60, as viewed in the z-direction.

As shown inFIG.7, the second output wiring45A and the second ground wiring46are larger in area viewed in the z-direction, than the second power wiring44A. The second output wiring45B and the second ground wiring46are larger in area viewed in the z-direction, than the second power wiring44B.

As shown inFIG.5, the respective wiring end sections47aof two of the control wirings47A located at the respective end portions in the x-direction, are larger in area viewed in the z-direction, than the wiring end sections47aof the remaining control wirings47A. The wiring end section47aof the control wiring47A located at the center in the x-direction, among the control wirings47A, is larger in area viewed in the z-direction than the respective wiring and sections47aof the control wirings47A other than the two control wirings47A located at the respective end portions in the y-direction. The wiring end section47aof the control wiring47A located at the center in the x-direction, among the control wirings47A, has a rectangular shape with the long sides extending in the x-direction and the short sides extending in the y-direction, as viewed in the z-direction.

Among the control wirings47A, the control wiring47A located adjacent to the control wiring47A located at the center in the x-direction, on the side of the substrate side face13in the x-direction, includes two connecting wiring sections47band two connecting end sections47c. This control wiring47A includes an extended wiring section47dextending from one of the connecting end sections47ctoward the second power wiring44B, a connecting end section47eprovided at the distal end of the extended wiring section47d, an extended wiring section47fextending from the other connecting end section47ctoward the first power wiring41B, and a connecting end section47gprovided at the distal end of the extended wiring section47f. To the connecting end section47e, the element electrode60ain the fourth region R4(seeFIG.4) of the semiconductor element60is bonded, via the solder layer48. To the connecting end section47g, the element electrode60ain the second region R2(seeFIG.4) of the semiconductor element60is bonded, via the solder layer48.

As shown inFIG.6, the first power conductor51A is located on the wide wiring section41aof the first power wiring41A. In this embodiment, the first power conductor51A is located on the end portion of the wide wiring section41aof the first power wiring41A on the side of the substrate side face13in the x-direction. To be more detailed, as viewed in the z-direction, one of the edges of the first power conductor51A in the x-direction on the side of the substrate side face13, is aligned with the edge of the wide wiring section41aof the first power wiring41A on the side of the substrate side face13, in the x-direction.

The top face50A of the first power conductor51A is shorter in the y-direction, than the width of the wide wiring section41aof the first power wiring41A. The first power conductor51A is located close to one of the edges of the wide wiring section41aof the first power wiring41A in the y-direction on the side of the substrate side face16(first output wiring42A). Accordingly, the distance between the first power conductor51A and the edge of the wide wiring section41aof the first power wiring41A in the y-direction on the side of the substrate side face16(first output wiring42A), is shorter than the distance between the first power conductor51A and another edge of the wide wiring section41aof the first power wiring41A in the y-direction on the side of the substrate side face15. In this embodiment, as viewed in the z-direction, one of the edges of the first power conductor51A in the y-direction on the side of the substrate side face16is aligned with the edge of the wide wiring section41aof the first power wiring41A in the y-direction on the side of the substrate side face16.

The top face50A of the first power conductor51A is shorter in the x-direction, than the wide wiring section41aof the first power wiring41A. In this embodiment, the length of the top face50A of the first power conductor51A in the x-direction is equal to or shorter than a half of the length of the wide wiring section41aof the first power wiring41A in the x-direction.

The first power conductor51B is located on the wide wiring section41aof the first power wiring419. In this embodiment, the first power conductor51B is located on the end portion of the wide wiring section41aof the first power wiring41B on the side of the substrate side face13in the x-direction. To be more detailed, as viewed in the z-direction, one of the edges of the first power conductor51B in the x-direction on the side of the substrate side face13, is aligned with the edge of the wide wiring section41aof the first power wiring41B on the side of the substrate side face13, in the x-direction.

The top face50A of the first power conductor51B is shorter in the y-direction, than the width of the wide wiring section41aof the first power wiring41B. The first power conductor51B is located close to one of the edges of the wide wiring section41aof the first power wiring41B in the y-direction on the side of the substrate side face15. Accordingly, the distance between the first power conductor51B and the edge of the wide wiring section41aof the first power wiring41B in the y-direction on the side of the substrate side face15, is shorter than the distance between the first power conductor51B and another edge of the wide wiring section41aof the first power wiring41B in the y-direction on the side of the substrate side face16. In this embodiment, as viewed in the z-direction, one of the edges of the first power conductor51B in the y-direction on the side of the substrate side face15is aligned with the edge of the wide wiring section41aof the first power wiring41B in the y-direction on the side of the substrate side face15.

The top face50A of the first power conductor51B is shorter in the x-direction, than the wide wiring section41aof the first power wiring41B. In this embodiment, the length of the top face50A of the first power conductor51B in the x-direction is equal to or shorter than a half of the length of the wide wiring section41aof the first power wiring41B in the x-direction.

The top face50A of the first power conductor51B has the same length in the x-direction, as the top face50A of the first power conductor51A, and the top face50A of the first power conductor51B has the same length in the y-direction as the top face50A of the first power conductor51A. Accordingly, the top face50A of the first power conductor51B has the same area as the top face50A of the first power conductor51A. Here, when the difference in area between the top face50A of the first power conductor51B and the top face50A of the first power conductor51A is, for example, within 5% of the area of the top face50A of the first power conductor51A, the area of the top face50A of the first power conductor51B may be regarded as being equal to that of the top face50A of the first power conductor51A. Since the first power conductors51A and510are both rectangular parallelepipeds, the length in the x-direction or y-direction, of the portion of the first power conductor51A closer to the substrate10than is the top face50A, is equal to that of the top face50A of the first power conductor51A, and the length in the x-direction or y-direction, of the portion of the first power conductor51B closer to the substrate10than is the top face50A, is equal to that of the top face50A of the first power conductor51B.

Though not shown, the first power conductor51B has the same thickness as the first power conductor51A. Accordingly, the first power conductor51B has the same volume as the first power conductor51A. Here, when the difference in volume between the first power conductor51B and the first power conductor51A is, for example, within 5% of the volume of the first power conductor51A, the volume of the first power conductor51B may be regarded as being equal to that of the first power conductor51A.

As shown inFIG.6, the first output conductor52A is located on the wide wiring section42aof the first output wiring42A. In this embodiment, the first output conductor52A is located on the end portion of the wide wiring section42aof the first output wiring42A on the side of the substrate side face13in the x-direction. To be more detailed, as viewed in the z-direction, one of the edges of the first output conductor52A in the x-direction on the side of the substrate side face13, is aligned with the edge of the wide wiring section42aof the first output wiring42A on the side of the substrate side face13, in the x-direction.

The top face50A of the first output conductor52A is shorter in the y-direction, than the width of the wide wiring section42aof the first output wiring42A. The length of the top face50A of the first output conductor52A in the y-direction is between ½ and ⅔, both ends inclusive, of the width of the wide wiring section42aof the first output wiring42A. The first output conductor52A is located on the side of one of the edges of the wide wiring section42aof the first output wiring42A in the y-direction, on the side of the substrate side face16(first ground wiring43). Accordingly, the distance between the first output conductor52A and the edge of the wide wiring section42aof the first output wiring42A in the y-direction, on the side of the substrate side face16(first ground wiring43), is shorter than the distance between the first output conductor52A and the other edge of the wide wiring section42aof the first output wiring42A in the y-direction, on the side of the substrate side face15(first power wiring41A).

The first output conductor52A is shorter in the x-direction, than the wide wiring section42aof the first output wiring42A. The first output conductor52A is located on the side of the substrate side face13in the x-direction, than is the sloped section42cof the first output wiring42A.

The top face50A of the first output conductor52A is longer in the x-direction, than the top face50A of the first power conductor51A. In other words, the top face50A of the first power conductor51A is shorter in the x-direction, than the top face50A of the first output conductor52A. In this embodiment, the length of the top face50A of the first power conductor51A in the x-direction is between ½ and ⅔, both ends inclusive, of the top face50A of the first output conductor52A. The top face50A of the first output conductor52A has the same length in the y-direction, as the top face50A of the first power conductor51A. Accordingly, the top face50A of the first power conductor51A is smaller in area than the top face50A of the first output conductor52A. Since the area of the top face50A of the first power conductor51A is equal to that of the top face50A of the first power conductor51B, the top face50A of the first power conductor51B is smaller in area than the top face50A of the first output conductor52A. In other words, the top face50A of the first output conductor52A is larger in area than the top face50A of the first power conductor51A, and also than the top face50A of the first power conductor51B. Here, since the first output conductor52A is a rectangular parallelepiped, the length in the x-direction or y-direction, of the portion of the first output conductor52A closer to the substrate10than is the top face50A, is equal to that of the top face50A of the first power conductor51A.

Though not shown, the first output conductor52A has the same thickness as the first power conductor51A. Accordingly, the first output conductor52A is larger in volume than the first power conductor51A. In other words, the first power conductor51A is smaller in volume than the first output conductor52A. Here, when the difference in volume between the first output conductor52A and the first power conductor51A is, for example, within 5% of the volume of the first power conductor51A, the volume of the first output conductor52A may be regarded as being equal to that of the first power conductor51A. Since the first power conductor51A has the same volume as the first power conductor51B, the volume of the first power conductor51B may be regarded as being smaller than that of the first output conductor52A.

As shown inFIG.6, the first output conductor52B is located on the wide wiring section42aof the first output wiring42B. In this embodiment, the first output conductor52B is located on the end portion of the wide wiring section42aof the first output wiring42B on the side of the substrate side face13in the x-direction. To be more detailed, as viewed in the z-direction, one of the edges of the first output conductor52B in the x-direction on the side of the substrate side face13, is aligned with the edge of the wide wiring section42aof the first output wiring42B on the side of the substrate side face13, in the x-direction.

The top face50A of the first output conductor52B is shorter in the y-direction, than the width of the wide wiring section42aof the first output wiring42B. The length of the top face50A of the first output conductor52B in the y-direction is between ½ and ⅔, both ends inclusive, of the width of the wide wiring section42aof the first output wiring42B. The first output conductor52B is located closer to one of the edges of the wide wiring section42aof the first output wiring420in the y-direction, on the side of the substrate side face15(first ground wiring43). Accordingly, the distance between the first output conductor52B and the edge of the wide wiring section42aof the first output wiring42B in the y-direction, on the side of the substrate side face15(first ground wiring43), is shorter than the distance between the first output conductor52B and the other edge of the wide wiring section42aof the first output wiring420in the y-direction, on the side of the substrate side face16(first power wiring41B).

The first output conductor52B is shorter in the x-direction, than the wide wiring section42aof the first output wiring42B. The first output conductor52B is located closer to the substrate side face13in the x-direction, than is the sloped section42cof the first output wiring42B.

The top face50A of the first output conductor52B has the same length in the x-direction, as the top face50A of the first output conductor52A, and the top face50A of the first output conductor52B has the same length in the y-direction as the top face50A of the first output conductor52A. Accordingly, the top face50A of the first output conductor52B has the same area as the top face50A of the first output conductor52A. Here, when the difference in area between the top face50A of the first output conductor52B and the top face50A of the first output conductor52A is, for example, within 5% of the area of the top face50A of the first output conductor52A, the area of the top face50A of the first output conductor52B may be regarded as being equal to that of the top face50A of the first output conductor52A. Since the top face50A of the first output conductor52B has the same area as the top face50A of the first output conductor52A, the top face50A of the first output conductor52B is larger in area than the top face50A of the first power conductor51A, and the top face50A of the first power conductor51B. In other words, the top face50A of the first power conductor51A and the top face50A of the first power conductor51B are each smaller in area than the top face50A of the first output conductor520. Here, since the first output conductor52B is a rectangular parallelepiped, the length in the x-direction or y-direction, of the portion of the first output conductor52B closer to the substrate10than is the top face50A, is equal to that of the top face50A of the first output conductor52B.

Though not shown, the first output conductor52B has the same thickness as the first output conductor52A. Accordingly, the first output conductor52B has the same volume as the first output conductor52A. Here, when the difference in volume between the first output conductor52B and the first output conductor52A is, for example, within 5% of the volume of the first output conductor52A, the volume of the first output conductor52B may be regarded as being equal to that of the first output conductor52A. Since the first output conductor52B has the same volume as the first output conductor52A, the first output conductor528is larger in volume than the first power conductor51A and the first power conductor51B. In other words, the first power conductor51A and the first power conductor51B are each smaller in volume than the first output conductor52B.

As shown inFIG.6, the first ground conductor53is located on one of the end portions of the first ground wiring43in the x-direction, on the side of the substrate side face13. To be more detailed, as viewed in the z-direction, one of the edges of the first ground conductor53in the x-direction on the side of the substrate side face13is aligned with the edge of the first ground wiring43on the side of the substrate side face13, in the x-direction.

The top face50A of the first ground conductor53is shorter in the y-direction, than the width of the first ground wiring43. The length of the top face50A of the first ground conductor53in the y-direction is between ½ and ⅔, both ends inclusive, of the width of the first ground wiring43. The first ground conductor53is located on the central portion of the first ground wiring43, in the y-direction.

The top face50A of the first ground conductor53has the same length in the x-direction, as the top face50A of the first output conductor52A. The top face50A of the first ground conductor53has the same length in the y-direction as the top face50A of the first output conductor52A. Accordingly, the top face50A of the first ground conductor53has the same area as the top face50A of the first output conductor52A. Here, when the difference in area between the top face50A of the first ground conductor53and the top face50A of the first output conductor52A is, for example, within 5% of the area of the top face50A of the first output conductor52A, the area of the top face50A of the first ground conductor53may be regarded as being equal to that of the top face50A of the first output conductor52A. Since the top face50A of the first ground conductor53has the same area as the top face50A of the first output conductor52A as above, the top face50A of the first ground conductor53is larger in area than the top face50A of the first power conductor51A, and the top face50A of the first power conductor51B. In other words, the top face50A of the first power conductor51A and the top face50A of the first power conductor51B are each smaller in area than the top face50A of the first ground conductor53. Here, since the first ground conductor53is a rectangular parallelepiped, the length in the x-direction or y-direction, of the portion of the first ground conductor53closer to the substrate10than is the top face50A, is equal to that of the top face50A of the first ground conductor53.

Though not shown, the first ground conductor53has the same thickness as the first output conductor52A. Accordingly, the first ground conductor53has the same volume as the first output conductor52A. Here, when the difference in volume between the first ground conductor53and the first output conductor52A is, for example, within 5% of the volume of the first output conductor52A, the volume of the first ground conductor53may be regarded as being equal to that of the first output conductor52A. Since the first ground conductor53has the same volume as the first output conductor52A as above, the first ground conductor53is larger in volume than the first power conductor51A and the first power conductor519. In other words, the first power conductor51A and the first power conductor519are each smaller in volume than the first ground conductor53.

As shown inFIG.7, the second power conductor54A is located on the wide wiring section44aof the second power wiring44A. In this embodiment, the second power conductor54A is located on the end portion of the wide wiring section44aof the second power wiring44A on the side of the substrate side face14in the x-direction. To be more detailed, as viewed in the z-direction, one of the edges of the second power conductor54A in the x-direction on the side of the substrate side face14, is aligned with the edge of the wide wiring section44aof the second power wiring44A on the side of the substrate side face14, in the x-direction.

The top face50A of the second power conductor54A is shorter in the y-direction, than the width of the wide wiring section44aof the second power wiring44A. The width of the wide wiring section44aof the second power wiring44A refers to the size of the portion thereof extending in the direction orthogonal to the direction in which the wide wiring section44aof the second power wiring44A extends, as viewed in the s-direction. In this embodiment, the width of the wide wiring section44aof the second power wiring44A corresponds to the length thereof in the y-direction. The second power conductor54A is located close to one of the edges of the wide wiring section44aof the second power wiring44A in the y-direction on the side of the substrate side face16(second output wiring45A). Accordingly, the distance between the second power conductor54A and one of the edges of the wide wiring section44aof the second power wiring44A in the y-direction on the side of the substrate side face16(second output wiring45A), is shorter than the distance between the second power conductor54A and another edge of the wide wiring section44aof the second power wiring44A in the y-direction on the side of the substrate side face15. In this embodiment, as viewed in the z-direction, one of the edges of the second power conductor54A in the y-direction on the side of the substrate side face16is aligned with the edge of the wide wiring section44aof the second power wiring44A in the y-direction on the side of the substrate side face16(second output wiring45A).

The second power conductor54A is shorter than the wide wiring section44aof the second power wiring44A, in the x-direction. In this embodiment, the length of the second power conductor54A in the x-direction is equal to or shorter than ½ of that of the wide wiring section44aof the second power wiring44A.

As shown inFIG.5, the top face50A of the second power conductor54A has the same length in the x-direction, as the top face50A of the first power conductor51A, and the top face50A of the second power conductor54A has the same length in the y-direction as the top face50A of the first power conductor51A. Accordingly, the top face50A of the second power conductor54A has the same area as the top face50A of the first power conductor51A. Here, when the difference in area between the top face50A of the second power conductor54A and the top face50A of the first power conductor51A is, for example, within 5% of the area of the top face50A of the first power conductor51A, the area of the top face50A of the second power conductor54A may be regarded as being equal to that of the top face50A of the first power conductor51A. Accordingly, the top face50A of the second power conductor54A is smaller in area than the top face50A of the first output conductor52A, the top face50A of the first output conductor52B, and the top face50A of the first ground conductor53. Since the second power conductor54A is a rectangular parallelepiped, the length in the x-direction or y-direction, of the portion of the second power conductor54A closer to the substrate10than is the top face50A, is equal to that of the top face50A of the second power conductor54A.

Though not shown, the second power conductor54A has the same thickness as the first power conductor51A. Accordingly, the second power conductor54A has the same volume as the first power conductor51A. Here, when the difference in volume between the second power conductor54A and the first power conductor51A is, for example, within 5% of the volume of the first power conductor51A, the volume of the second power conductor54A may be regarded as being equal to that of the first power conductor51A. Accordingly, the second power conductor54A is smaller in volume than the first output conductor52A, the first output conductor528, and the first ground conductor53.

As shown inFIG.7, the second power conductor54B is located on the wide wiring section44aof the second power wiring44B. In this embodiment, the second power conductor54B is located on the end portion of the wide wiring section44aof the second power wiring44B on the side of the substrate side face14in the x-direction. To be more detailed, as viewed in the z-direction, one of the edges of the second power conductor54B in the x-direction on the side of the substrate side face14, is aligned with the edge of the wide wiring section44aof the second power wiring44B on the side of the substrate side face14, in the x-direction.

The top face50A of the second power conductor54B is shorter in the y-direction, than the width of the wide wiring section44aof the second power wiring44B. The width of the wide wiring section44aof the second power wiring44B refers to the size of the portion thereof extending in the direction orthogonal to the direction in which the wide wiring section44aof the second power wiring44B extends, as viewed in the z-direction. In this embodiment, the width of the wide wiring section44aof the second power wiring44B corresponds to the length thereof in the y-direction. The second power conductor54B is located close to one of the edges of the wide wiring section44aof the second power wiring44B in the y-direction on the side of the substrate side face15(second output wiring45B). Accordingly, the distance between the second power conductor54B and one of the edges of the wide wiring section44aof the second power wiring44B in the y-direction on the side of the substrate side face15(second output wiring45B), is shorter than the distance between the second power conductor54B and another edge of the wide wiring section44aof the second power wiring44B in the y-direction on the side of the substrate side face16. In this embodiment, as viewed in the z-direction, one of the edges of the second power conductor54B in the y-direction on the side of the substrate side face15(second output wiring45B) is aligned with the edge of the wide wiring section44aof the second power wiring44B in the y-direction on the side of the substrate side face15(second output wiring45B).

The second power conductor54B is shorter than the wide wiring section44aof the second power wiring44B, in the x-direction. In this embodiment, the length of the second power conductor54B in the x-direction is equal to or shorter than ½ of that of the wide wiring section44aof the second power wiring44B.

As shown inFIG.5, the top face50A of the second power conductor54B has the same length in the x-direction, as the top face50A of the second power conductor54A, and the top face50A of the second power conductor54B has the same length in the y-direction as the top face50A of the second power conductor54A. Accordingly, the top face50A of the second power conductor54B has the same area as the top face50A of the second power conductor54A. Here, when the difference in area between the top face50A of the second power conductor54B and the top face50A of the second power conductor54A is, for example, within 5% of the area of the top face50A of the second power conductor54A, the area of the top face50A of the second power conductor54B may be regarded as being equal to that of the top face50A of the second power conductor54A. Since the top face50A of the second power conductor54A has the same area as the top face50A of the first power conductor51A, the top face50A of the second power conductor54A is smaller in area than the top face50A of the first output conductor52A, the top face50A of the first output conductor52B, and the top face50A of the first ground conductor53. Here, since the second power conductor54B is a rectangular parallelepiped, the length in the x-direction or y-direction, of the portion of the second power conductor54B closer to the substrate10than is the top face50A, is equal to that of the top face50A of the second power conductor54B.

Though not shown, the second power conductor54B has the same thickness as the second power conductor54A. Accordingly, the second power conductor54B has the same volume as the second power conductor54A. Here, when the difference in volume between the second power conductor54B and the second power conductor54A is, for example, within 5% of the volume of the second power conductor54A, the volume of the second power conductor54B may be regarded as being equal to that of the second power conductor54A. Since the second power conductor54A has the same volume as the first power conductor51A, the second power conductor54B is smaller in volume than the first output conductor52A, the first output conductor52B, and the first ground conductor53.

The second output conductor55A is located on the wide wiring section45aof the second output wiring45A. In this embodiment, the second output conductor55A is located on the end portion of the wide wiring section45aof the second output wiring45A on the side of the substrate side face14in the x-direction. To be more detailed, as viewed in the z-direction, one of the edges of the second output conductor55A in the x-direction on the side of the substrate side face14, is aligned with the edge of the wide wiring section45aof the second output wiring45A on the side of the substrate side face14, in the x-direction.

The top face50A of the second output conductor55A is shorter in the y-direction, than the width of the wide wiring section45aof the second output wiring45A. The length of the top face50A of the second output conductor55A in the y-direction is between ½ and ⅔, both ends inclusive, of the width of the wide wiring section45aof the second output wiring45A. The width of the wide wiring section45aof the second output wiring45A refers to the size of the portion thereof extending in the direction orthogonal to the direction in which the wide wiring section45aof the second output wiring45A extends, as viewed in the z-direction. In this embodiment, the width of the wide wiring section45aof the second output wiring45A corresponds to the length thereof in the y-direction. The second output conductor55A is located closer to one of the edges of the wide wiring section45aof the second output wiring45A in the y-direction, on the side of the substrate side face16. Accordingly, the distance between the second output conductor55A and the edge of the wide wiring section45aof the second output wiring45A in the y-direction, on the side of the substrate side face16, is shorter than the distance between the second output conductor55A and the other edge of the wide wiring section45aof the second output wiring45A in the y-direction, on the side of the substrate side face15.

The second output conductor55A is shorter in the x-direction, than the wide wiring section45aof the second output wiring45A. The second output conductor55A is located closer to the substrate side face14in the x-direction, than is the sloped section45cof the second output wiring45A.

The top face50A of the second output conductor55A is longer in the x-direction, than the top face50A of the second power conductor54A. In other words, the top face50A of the second power conductor54A is shorter in the x-direction, than the top face50A of the second output conductor55A. The length of the top face50A of the second power conductor54A in the x-direction is between ½ and ⅔, both ends inclusive, of the top face50A of the second output conductor55A. The top face50A of the second output conductor55A has the same length in the y-direction, as the top face50A of the second power conductor54A. Accordingly, the top face50A of the second power conductor54A is smaller in area than the top face50A of the second output conductor55A. Since the area of the top face50A of the second power conductor54A is equal to that of the top face50A of the second power conductor54B, the top face50A of the second power conductor54B is smaller in area than the top face50A of the second output conductor55A. In other words, the top face50A of the second output conductor55A is larger in area than the top face50A of the second power conductor54A, and also than the top face50A of the second power conductor54B. Here, since the second output conductor55A is a rectangular parallelepiped, the length in the x-direction or y-direction, of the portion of the second output conductor55A closer to the substrate10than is the top face50A, is equal to that of the top face50A of the second output conductor55A.

Though not shown, the second output conductor55A has the same thickness as the second power conductor54A. Accordingly, the second output conductor55A is larger in volume than the second power conductor54A. In other words, the second power conductor54A is smaller in volume than the second output conductor55A. Here, when the difference in volume between the second output conductor55A and the second power conductor54A is, for example, within 5% of the volume of the second power conductor54A, the volume of the second output conductor55A may be regarded as being equal to that of the second power conductor54A. Since the second power conductor54A has the same volume as the second power conductor54B, the volume of the second power conductor54B may be regarded as being smaller than that of the second output conductor55A.

As shown inFIG.5, the top face50A of the second output conductor55A has the same length in the x-direction, as the top face50A of the first output conductor52A, and the top face50A of the second output conductor55A has the same length in the y-direction as the top face50A of the first output conductor52A. Accordingly, the top face50A of the second output conductor55A has the same area as the top face50A of the first output conductor52A. Here, when the difference in area between the top face50A of the second output conductor55A and the top face50A of the first output conductor52A is, for example, within 5% of the area of the top face50A of the first output conductor52A, the area of the top face50A of the second output conductor55A may be regarded as being equal to that of the top face50A of the first output conductor52A. Accordingly, the top face50A of the second output conductor55A is larger in area than the top face50A of the first power conductor51A, and the top face50A of the first power conductor51B. In other words, the top face50A of the first power conductor51A and the top face50A of the first power conductor51B are each smaller in area than the top face50A of the second output conductor55A.

Though not shown, the second output conductor55A has the same thickness as the first output conductor52A. Accordingly, the second output conductor55A has the same volume as the first output conductor52A. Here, when the difference in volume between the second output conductor55A and the first output conductor52A is, for example, within 5% of the volume of the first output conductor52A, the volume of the second output conductor55A may be regarded as being equal to that of the first output conductor52A. Since the second output conductor55A has the same volume as the first output conductor52A, the second output conductor55A is larger in volume than the first power conductor51A and the first power conductor51B. In other words, the first power conductor51A and the first power conductor51B are each smaller in volume than the second output conductor55A.

The second output conductor55B is located on the wide wiring section45aof the second output wiring45B. In this embodiment, the second output conductor55B is located on the end portion of the wide wiring section45aof the second output wiring45B on the side of the substrate side face14in the x-direction. To be more detailed, as viewed in the z-direction, one of the edges of the second output conductor55B in the x-direction on the side of the substrate side face14, is aligned with the edge of the wide wiring section45aof the second output wiring45B on the side of the substrate side face14, in the x-direction.

The top face50A of the second output conductor55B is shorter in the y-direction, than the width of the wide wiring section45aof the second output wiring45B. The length of the top face50A of the second output conductor55B in the y-direction is between ½ and ⅔, both ends inclusive, of the width of the wide wiring section45aof the second output wiring45B. The width of the wide wiring section45aof the second output wiring45B refers to the size of the portion thereof extending in the direction orthogonal to the direction in which the wide wiring section45aof the second output wiring45B extends, as viewed in the z-direction. In this embodiment, the width of the wide wiring section45aof the second output wiring45B corresponds to the length thereof in the y-direction. The second output conductor55B is located closer to one of the edges of the wide wiring section45aof the second output wiring45B in the y-direction, on the side of the substrate side face15. Accordingly, the distance between the second output conductor55B and the edge of the wide wiring section45aof the second output wiring45B in the y-direction, on the side of the substrate side face15, is shorter than the distance between the second output conductor55B and the other edge of the wide wiring section45aof the second output wiring45B in the y-direction, on the side of the substrate side face16.

The second output conductor55B is shorter in the x-direction, than the wide wiring section45aof the second output wiring45B. The second output conductor55B is located closer to the substrate side face14in the x-direction, than is the sloped section45cof the second output wiring45B.

The top face50A of the second output conductor55B has the same length in the x-direction, as the top face50A of the second output conductor55A, and the top face50A of the second output conductor55B has the same length in the y-direction as the top face50A of the second output conductor55A. Accordingly, the top face50A of the second output conductor55B has the same area as the top face50A of the second output conductor55A. Here, when the difference in area between the top face50A of the second output conductor55B and the top face50A of the second output conductor55A is, for example, within 5% of the area of the top face50A of the second output conductor55A, the area of the top face50A of the second output conductor55B may be regarded as being equal to that of the top face50A of the second output conductor55A. Since the top face50A of the second output conductor55B has the same area as the top face50A of the second output conductor55A, the top face50A of the second output conductor55B is larger in area than the top face50A of the second power conductor54A, and the top face50A of the second power conductor54B. In other words, the top face50A of the second power conductor54A and the top face50A of the second power conductor54B are each smaller in area than the top face50A of the second output conductor55B. Here, since the second output conductor55B is a rectangular parallelepiped, the length in the x-direction or y-direction, of the portion of the second output conductor55B closer to the substrate10than is the top face50A, is equal to that of the top face50A of the second output conductor55B.

Though not shown, the second output conductor55B has the same thickness as the second output conductor55A. Accordingly, the second output conductor55B has the same volume as the second output conductor55A. Here, when the difference in volume between the second output conductor553and the second output conductor55A is, for example, within 5% of the volume of the second output conductor55A, the volume of the second output conductor55B may be regarded as being equal to that of the second output conductor55A. Since the second output conductor55B has the same volume as the second output conductor55A, the second output conductor55B is larger in volume than the second power conductor54A and the second power conductor54B. In other words, the second power conductor54A and the second power conductor54B are each smaller in volume than the second output conductor55B.

As shown inFIG.5, the top face50A of the second output conductor55B has the same length in the x-direction, as the top face50A of the first output conductor52B, and the top face50A of the second output conductor55B has the same length in the y-direction as the top face50A of the first output conductor52B. Accordingly, the top face50A of the second output conductor55B has the same area as the top face50A of the first output conductor529. Here, when the difference in area between the top face50A of the second output conductor55B and the top face50A of the first output conductor52B is, for example, within 5% of the area of the top face50A of the first output conductor52B, the area of the top face50A of the second output conductor559may be regarded as being equal to that of the top face50A of the first output conductor52B. Accordingly, the top face50A of the second output conductor559is larger in area than the top face50A of the first power conductor51A, and the top face50A of the first power conductor51B. In other words, the top face50A of the first power conductor51A and the top face50A of the first power conductor51B are each smaller in area than the top face50A of the second output conductor55B.

Though not shown, the second output conductor55B has the same thickness as the first output conductor528. Accordingly, the second output conductor55B has the same volume as the first output conductor52B. Here, when the difference in volume between the second output conductor55B and the first output conductor52B is, for example, within 5% of the volume of the first output conductor52B, the volume of the second output conductor55B may be regarded as being equal to that of the first output conductor52B. Accordingly, the second output conductor55B is larger in volume than the first power conductor51A and the first power conductor51B. In other words, the first power conductor51A and the first power conductor51B are each smaller in volume than the second output conductor55B.

As shown inFIG.7, the second ground conductor56is located on one of the edges of the second ground wiring46in the x-direction, on the side of the substrate side face14. To be more detailed, as viewed in the z-direction, one of the edges of the second ground conductor56in the x-direction on the side of the substrate side face14is aligned with the edge of the second ground wiring46on the side of the substrate side face14, in the x-direction.

The top face50A of the second ground conductor56is shorter in the y-direction, than the width of the second ground wiring46. The length of the top face50A of the second ground conductor56in the y-direction is between ½ and ⅔, both ends inclusive, of the width of the second ground wiring46. The width of the second ground wiring46refers to the size of the portion thereof extending in the direction orthogonal to the direction in which the second ground wiring46extends, as viewed in the z-direction. In this embodiment, the width of the second ground wiring46corresponds to the length thereof in the y-direction. The second ground conductor56is located on the central portion of the second ground wiring46, in the y-direction.

The top face50A of the second ground conductor56has the same length in the x-direction, as the top face50A of the second output conductor55A. The top face50A of the second ground conductor56has the same length in the y-direction as the top face50A of the second output conductor55A. Accordingly, the top face50A of the second ground conductor56has the same area as the top face50A of the second output conductor55A. Here, when the difference in area between the top face50A of the second ground conductor56and the top face50A of the second output conductor55A is, for example, within 5% of the area of the top face50A of the second output conductor55A, the area of the top face50A of the second ground conductor56may be regarded as being equal to that of the top face50A of the second output conductor55A. Since the top face50A of the second ground conductor56has the same area as the top face50A of the second output conductor55A as above, the top face50A of the second ground conductor56is larger in area than the top face50A of the second power conductor54A, and the top face50A of the second power conductor54B. In other words, the top face50A of the second power conductor54A and the top face50A of the second power conductor54B are each smaller in area than the top face50A of the second ground conductor56. Here, since the second ground conductor56is a rectangular parallelepiped, the length in the x-direction or y-direction, of the portion of the second ground conductor56closer to the substrate10than is the top face50A, is equal to that of the top face50A of the second ground conductor56.

Though not shown, the second ground conductor56has the same thickness as the second output conductor55A. Accordingly, the second ground conductor56has the same volume as the second output conductor55A. Here, when the difference in volume between the second ground conductor56and the second output conductor55A is, for example, within 5% of the volume of the second output conductor55A, the volume of the second ground conductor56may be regarded as being equal to that of the second output conductor55A. Since the second ground conductor56has the same volume as the second output conductor55A as above, the second ground conductor56is larger in volume than the second power conductor54A and the second power conductor54B. In other words, the second power conductor54A and the second power conductor54B are each smaller in volume than the second ground conductor56.

As shown inFIG.5, the top face50A of the second ground conductor56has the same length in the x-direction, as the top face50A of the first ground conductor53, and the top face50A of the second ground conductor56has the same length in the y-direction as the top face50A of the first ground conductor53. Accordingly, the top face50A of the second ground conductor56has the same area as the top face50A of the first ground conductor53. Here, when the difference in area between the top face50A of the second ground conductor56and the top face50A of the first ground conductor53is, for example, within 5% of the area of the top face50A of the first ground conductor53, the area of the top face50A of the second ground conductor56may be regarded as being equal to that of the top face50A of the first ground conductor53. Accordingly, the top face50A of the second ground conductor56is larger in area than the top face50A of the first power conductor51A, and the top face50A of the first power conductor51B. In other words, the top face50A of the first power conductor51A and the top face50A of the first power conductor51B are each smaller in area than the top face50A of the second ground conductor56.

Though not shown, the second ground conductor56has the same thickness as the first ground conductor53. Accordingly, the second ground conductor56has the same volume as the first ground conductor53. Here, when the difference in volume between the second ground conductor56and the first ground conductor53is, for example, within 5% of the volume of the first ground conductor53, the volume of the second ground conductor56may be regarded as being equal to that of the first ground conductor53. Accordingly, the second ground conductor56is larger in volume than the first power conductor51A and the first power conductor51B. In other words, the first power conductor51A and the first power conductor51B are each smaller in volume than the second ground conductor56.

As shown inFIG.5, the plurality of control conductors57include a plurality of (in this embodiment, nine) control conductors57A respectively located on the wiring end section47aof the plurality of control wirings47A, and a plurality of (in this embodiment, nine) control conductors573respectively located on the wiring end section47aof the plurality of control wirings47B. However, the number of pieces of the control conductors57A and57B may be changed as desired. In an example, the number of pieces of the control conductors57A and that of the control conductors57B may be different from each other.

The plurality of control conductors57A include two distal control conductors57C, a central control conductor57D, and six intermediate control conductors57E. The distal control conductors57C, the central control conductor57D, and the intermediate control conductors57E are each formed in a rectangular parallelepiped shape. As viewed in the z-direction, the top face50A of the distal control conductor57C has a rectangular shape having the sides extending along the x-direction and the sides extending along the y-direction and, in this embodiment, a square shape. As viewed in the z-direction, the top face50A of the central control conductor57D has a generally rectangular shape having the sides extending along the x-direction and the sides extending along the y-direction. In this embodiment, the sides along the x-direction correspond to the long sides, and the sides along the y-direction correspond to the short sides. As viewed in the z-direction, the top face50A of the intermediate control conductor57E has a rectangular shape having the sides extending along the x-direction and the sides extending along the y-direction and, in this embodiment, a square shape.

Here, the shape viewed in the z-direction of the top face50A of the distal control conductor57C, the top face50A of the central control conductor57D, and the top face50A of the intermediate control conductor57B may be modified as desired. In an example, the shape viewed in the z-direction of the top face50A of the distal control conductor57C, the top face50A of the central control conductor57D, and the top face50A of the intermediate control conductor57E may each be circular, or elliptical.

The two distal control conductors57C are located at the respective ends of the plurality of control conductors57A, in the x-direction. The distal control conductor57C on the side of the substrate side face13in the x-direction is aligned with the first power conductor51A in the x-direction, and spaced therefrom in the y-direction. The top face50A of the distal control conductor57C has the same length in the x-direction, as the top face50A of the first power conductor51A, and the top face50A of the distal control conductor57C is longer in the y-direction, than the top face50A of the first power conductor51A. Accordingly, the top face50A of the distal control conductor57C is larger in area than the top face50A of the first power conductor51A. In other words, the top face50A of the first power conductor51A is smaller in area than the top face50A of the distal control conductor57C. In addition, the top face50A of the distal control conductor57C is smaller in area than the top face50A of the first output conductor52A, the top face50A of the first output conductor52B, and the top face50A of the first ground conductor53. Since each of the distal control conductors57C is a rectangular parallelepiped, the length in the x-direction or y-direction, of the portion of the distal control conductor57C closer to the substrate10than is the top face50A, is equal to that of the top face50A of the distal control conductor57C.

Though not shown, the distal control conductor57C has the same thickness as the first power conductor51A. Accordingly, the distal control conductor57C is larger in volume than the first power conductor51A. In other words, the first power conductor51A is smaller in volume than the distal control conductor57C. In addition, the distal control conductor57C located close to the substrate side face13in the x-direction is smaller in volume than the first output conductor52A, the first output conductor52B, and the first ground conductor53.

The distal control conductor57C on the side of the substrate side face14in the x-direction is aligned with the second power conductor54A in the x-direction, and spaced therefrom in the y-direction. The top face50A of the distal control conductor57C has the same length in the x-direction, as the top face50A of the second power conductor54A, and the top face50A of the distal control conductor57C is longer in the y-direction, than the top face50A of the second power conductor54A. Accordingly, the top face50A of the distal control conductor57C is larger in area than the top face50A of the second power conductor54A. In addition, the top face50A of the distal control conductor57C is smaller in area than the top face50A of the second output conductor55A, the top face50A of the second output conductor55B, and the top face50A of the second ground conductor56.

Though not shown, the distal control conductor57C has the same thickness as the second power conductor54A. Accordingly, the distal control conductor57C is larger in volume than the first power conductor51B. In other words, first power conductor51B is smaller in volume than the distal control conductor57C. In addition, the distal control conductor57C located close to the substrate side face14in the x-direction is smaller in volume than the second output conductor55A, the second output conductor55B, and the second ground conductor56.

The central control conductor57D is located between the power conductors51A and51B, the output conductors52A and52B and the first ground conductor53, and the power conductors54A and54B, the output conductors55A and55B and the second ground conductor56, in the x-direction. The central control conductor57D includes a cutaway portion57xfor indicating the orientation of the semiconductor device1A. The top face50A of the central control conductor57D is longer in the x-direction, than the top face50A of the first power conductor51A, and the top face50A of the central control conductor57D has the same length in the y-direction, as the top face50A of the first power conductor51A. Accordingly, the top face50A of the central control conductor57D is larger in area than the top face50A of the first power conductor51A. In other words, the top face50A of the first power conductor51A is smaller in area than the top face50A of the central control conductor57D. In addition, the top face50A of the central control conductor57D is smaller in area than the top face50A of the first output conductor52A, the top face50A of the first output conductor52B, and the top face50A of the first ground conductor53. Since the central control conductor57D is a rectangular parallelepiped, the length in the x-direction or y-direction, of the portion of the central control conductor57D closer to the substrate10than is the top face50A, is equal to that of the top face50A of the central control conductor57D.

Though not shown, the central control conductor57D has the same thickness as the first power conductor51A. Accordingly, the central control conductor57D is larger in volume than the first power conductor51A. In other words, the first power conductor51A is smaller in volume than the central control conductor57D. In addition, the central control conductor57D is smaller in volume than the first output conductor52A, the first output conductor52B, and the first ground conductor53.

Three out of the six intermediate control conductors57B are located between the distal control conductor57C on the side of the substrate side face13and the central control conductor57D in the x-direction, in alignment with one another in the y-direction and with a spacing between each other in the x-direction.

The remaining three intermediate control conductors57E are located between the distal control conductor57C on the side of the substrate side face14and the central control conductor57D in the x-direction, in alignment with one another in the y-direction and with a spacing between each other in the x-direction.

The top face50A of each of the intermediate control conductors57B is shorter in the x-direction, than the top face50A of the first power conductor51A, and the top face50A of each of the intermediate control conductors57E has the same length in the y-direction, as the top face50A of the first power conductor51A. Accordingly, the top face50A of each of the intermediate control conductors57B is smaller in area than the top face50A of the first power conductor51A. In other words, the top face50A of the first power conductor51A is larger in area than the top face50A of each of the intermediate control conductors579. Since the intermediate control conductor57E is a rectangular parallelepiped, the length in the x-direction or y-direction, of the portion of the intermediate control conductor57E closer to the substrate10than is the top face50A, is equal to that of the top face50A of the intermediate control conductor57E.

Though not shown, the intermediate control conductors57B each have the same thickness as the first power conductor51A. Accordingly, each of the intermediate control conductors57E is smaller in volume than the first power conductor51A. In other words, the first power conductor51A is greater in volume than each intermediate control conductor57E.

The plurality of control conductors57B include two distal control conductors57C and seven intermediate control conductors57E. The distal control conductors57C and the intermediate control conductor579each have a rectangular parallelepiped shape. The two distal control conductors57C are located at the respective end portions of the plurality of control conductors57A in the x-direction. The seven intermediate control conductors57E are located between the two distal control conductors57C, in the x-direction. The seven intermediate control conductors57E are aligned with each other in the y-direction, and spaced apart from each other in the x-direction.

The top face50A of the distal control conductor57C in the control conductors57B has the same area as the top face50A of the distal control conductor57C in the control conductors57A. Accordingly, the top face50A of the distal control conductor57C in the control conductors57B, located close to the substrate side face13, is larger in area than the top face50A of the first power conductor51B. Likewise, the top face50A of the distal control conductor57C in the control conductors57B, located close to the substrate side face14, is larger in area than the top face50A of the second power conductor54B. In addition, the top face50A of the distal control conductor57C close to the substrate side face13is smaller in area than the top face50A of the first output conductor52A, the top face50A of the first output conductor52B, and the top face50A of the first ground conductor53. Likewise, the top face50A of the distal control conductor57C close to the substrate side face14is smaller in area than the top face50A of the second output conductor55A, the top face50A of the second output conductor55B, and the top face50A of the second ground conductor56.

Though not shown, the distal control conductors57C each have the same thickness as the first power conductor51B and the second power conductor54B. Accordingly, the distal control conductors57C are each larger in volume than the first power conductor51B and the second power conductor54B. In other words, the first power conductor51B and the second power conductor54B are each smaller in volume, than each of the distal control conductors57C. In addition, the distal control conductor57C close to the substrate side face13is smaller in volume than the first output conductor52A, the first output conductor52B, and the first ground conductor53. Likewise, the distal control conductor57C close to the substrate side face14is smaller in volume than the second output conductor55A, the second output conductor55B, and the second ground conductor56.

The top face50A of each of the intermediate control conductors57E in the control conductors57B has the same area as the top face50A of the intermediate control conductors579in the control conductors57A. Accordingly, the top face50A of each of the intermediate control conductors57B in the control conductors579is smaller in area than the top face50A of the first power conductor51A.

Though not shown, the intermediate control conductors57B in the control conductors57B each have the same thickness as the intermediate control conductors57E in the control conductors57A. Accordingly, each of the intermediate control conductors57E in the control conductors57B has the same volume as the intermediate control conductors57B in the control conductors57A. Therefore, each of the intermediate control conductors57E in the control conductors57B is smaller in volume than the first power conductor51A.

As shown inFIG.3, the plurality of terminals20include first power terminals21A and21B, first output terminals22A and22B, a first ground terminal23, second power terminals24A and24B, second output terminals25A and25B, a second ground terminal26, and a plurality of control terminals27. In this embodiment, the first power terminals21A and21B and the second power terminals24A and24B correspond to the first drive terminal, and the first output terminals22A and22B, the first ground terminal23, the second output terminals25A and25B, and the second ground terminal26correspond to the second drive terminal.

The first power terminal21A covers the top face50A of the first power conductor51A in the plurality of conductors50. The first power terminal21B covers the top face50A of the first power conductor51B. The first output terminal22A covers the top face50A of the first output conductor52A in the plurality of conductors50. The first output terminal22B covers the top face50A of the first output conductor52B in the plurality of conductors50. The first ground terminal23covers the top face50A of the first ground conductor53in the plurality of conductors50. The second ground terminal26covers the top face50A of the second ground conductor56in the plurality of conductors50. The plurality of control terminals27respectively covers the top face50A of the plurality of control conductors57.

The relation in size viewed in the z-direction, among the first power terminals21A and21B, the first output terminals22A and22B, the first ground terminal23, the second power terminals24A and24B, the second output terminals25A and25B, the second ground terminal26, and the plurality of control terminal27is the same as the relation in size of the top face50A viewed in the z-direction, among the first power conductors51A and51B, the first output conductors52A and52B, the first ground conductor53, the second power conductors54A and54B, the second output conductors55A and55B, the second ground conductor56, and the plurality of control conductors57.

Referring toFIG.13toFIG.25, an exemplary manufacturing method of the semiconductor device1A will now be described hereunder. Referring toFIG.13, the manufacturing method of the semiconductor device1A includes a process of forming an insulation film817on a base material810. To be more detailed, first the base material810of a flat plate-shape is prepared. In this embodiment, a silicon wafer is employed as the base material810. Then the insulation film817is formed on one of the surfaces of the base material810in the thickness direction. The insulation film817can be formed through depositing an oxide layer on the one surface of the base material810in the thickness direction by thermal oxidation, and then depositing a nitride layer on the oxide layer by plasma chemical vapor deposition (CVD). The surface of the insulation film817formed as above, oriented in the thickness direction, will hereinafter be referred to as base material obverse face811. The face of the base material810oriented in the opposite direction to the base material obverse face811in the thickness direction, will hereinafter be referred to as base material reverse face812.

Referring toFIG.14andFIG.15, the manufacturing method of the semiconductor device1A includes a process of forming a plurality of wirings840. To be more detailed, first an underlying layer840A is formed so as to cover the base material obverse face811, as shown inFIG.14. The underlying layer840A can be formed through depositing a barrier layer all over the base material obverse face811by a sputtering method, and then depositing a seed layer on the barrier layer, by a sputtering method. The barrier layer is formed of Ti, in a thickness between 100 nm and 300 nm, both ends inclusive. The seed layer is formed of Cu, in a thickness between 200 nm and 600 nm, both ends inclusive. Turning toFIG.15, a plurality of plated layers840B are formed on the underlying layer840A. The plurality of plated layers840B can be formed through applying a lithographic patterning on the underlying layer840A, and performing an electrolytic plating process using the underlying layer840A as the conduction path. The plurality of plated layers8409are each formed of Cu, in a thickness between 5 μm and 25 μm, both ends inclusive.

Turning toFIG.16, the manufacturing method of the semiconductor device1A includes a process of forming a plurality of conductors850. To be more detailed, the plurality of conductors850are formed on the respective plated layers840B. The conductors850are, for example, formed of Cu. The plurality of conductors850can be formed through applying a lithographic patterning on the plurality of plated layers840B, and performing an electrolytic plating process using the underlying layer840A and the plated layer840B as the conduction path.

The plurality of conductors850have the same size as each other, in the thickness direction. Further, as shown inFIG.17, the plurality of conductors850each have a rectangular shape having the long sides and short sides, as viewed in the thickness direction. Some of the plurality of conductors850are longer in the longitudinal direction, than the remaining conductors850. Thus, the plurality of conductors850are each formed in a rectangular parallelepiped shape.

To be more detailed, as shown inFIG.17, the plurality of conductors850include first power conductors851A and851B, first output conductors852A and852B, a first ground conductor853, second power conductors854A and854B, second output conductors855A and855B, a second ground conductor856and a plurality of control conductors857. The plurality of wirings840include first power wirings841A and841B, first output wirings842A and842B, a first ground wiring843, second power wirings844A and844B, second output wirings845A and845B, a second ground wiring846, and a plurality of control wirings847. The first power conductor851A is connected to the first power wiring841A, and the first power conductor851B is connected to the first power wiring841B. The first output conductor852A is connected to the first output wiring842A, and the first output conductor852B is connected to the first output wiring842B. The first ground conductor853is connected to the first ground wiring843. The second power conductor854A is connected to the second power wiring844A, and the second power conductor854B is connected to the second power wiring844B. The second output conductor855A is connected to the second output wiring845A, and the second output conductor855B is connected to the second output wiring845B. The second ground conductor856is connected to the second ground wiring846. The plurality of control conductors857are respectively connected to the plurality of control wirings847. Accordingly, the arrangement pattern of the first power conductors851A and851B, the first output conductors852A and852B, and the first ground conductor853is the same as that of the first power conductors51A and51B, the first output conductors52A and52B, and the first ground conductor53shown inFIG.3. The arrangement pattern of the second power conductors854A and854B, the second output conductors855A and855B, and the second ground conductor856is the same as that of the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56shown inFIG.3.

As shown inFIG.17, the first power conductors851A and851B, the first output conductors852A and852B, the first ground conductor853, the second power conductors854A and854B, the second output conductors855A and855B, and the second ground conductor856each have a rectangular shape having the long sides extending in the x-direction and the short sides extending in the y-direction, as viewed in the z-direction.

The respective top faces850A of the first power conductors851A and851B are shorter in the x-direction, than the respective top faces850A of the first output conductors852A and852B and the first ground conductor853. The respective top faces850A of the first power conductors851A and851B have the same length in the x-direction, as the respective top faces850A of the first output conductors852A and852B and the first ground conductor853. Though not shown, the plurality of conductors850all have the same thickness as one another. Accordingly, the first power conductors851A and851B are each smaller in volume than the first output conductors852A and852B and the first ground conductor853.

The respective top faces850A of the second power conductors854A and854B are shorter in the x-direction, than the respective top faces850A of the second output conductors855A and855B and the second ground conductor856. The respective top faces850A of the second power conductors854A and854B have the same length in the x-direction, as the respective top faces850A of the second output conductors855A and855B and the second ground conductor856. Since the plurality of conductors850have the same thickness as one another as mentioned above, the second power conductors854A and854B are each smaller in volume than the second output conductors855A and855B and the second ground conductor856.

Referring toFIG.18, the manufacturing method of the semiconductor device1A includes a process of removing a part of the underlying layer840A. To be more detailed, the portion of the underlying layer840A uncovered with the plated layer840B is removed. The portion of the underlying layer840A uncovered with the plated layer840B can be removed by a wet etching method using mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). As result, the residual portion of the underlying layer840A and the plurality of plated layers840B stacked on the underlying layer840A constitute the plurality of wirings40of the semiconductor device1A.

Referring toFIG.19, the manufacturing method of the semiconductor device1A includes a process of mounting the semiconductor element60. To be more detailed, the semiconductor element60is bonded onto the plurality of wirings40, via the solder layer48. In this embodiment, the semiconductor element60is flip-chip bonded onto the plurality of wirings40. More specifically, first the solder layer48(seeFIG.12) is applied to each of the element electrodes60aof the semiconductor element60. Then the plurality of element electrodes60aof the semiconductor element60are tentatively attached to the respective wirings40via the solder layer48, using a collet (not shown), and the plurality of solder layers48are molten through a reflow process. Finally, the plurality of solder layers48are solidified by cooling, so that the semiconductor element60is fixed to the plurality of wirings40.

Referring toFIG.20, the manufacturing method of the semiconductor device1A includes a process of forming a resin layer830. To be more detailed, the resin layer830is formed in contact with the base material obverse face811, and so as to cover the plurality of wirings40, the semiconductor element60, and the plurality of conductors850. For example, a thermosetting resin is employed as the resin layer830. In this embodiment, a black epoxy resin is employed. The resin layer830is formed through a compression molding process.

Referring toFIG.21, the manufacturing method of the semiconductor device1A includes a process of removing the resin layer830in the thickness direction. To be more detailed, the portion of the resin layer830located on the opposite side of the substrate obverse face11in the thickness direction is removed by mechanical grinding. By the mechanical grinding, the portion of the plurality of conductors850located on the opposite side of the base material obverse face811in the thickness direction is also removed at the same time. As result, the thickness of the resin layer830is reduced, and the plurality of conductors50are formed.

As shown inFIG.22, the plurality of conductors50are exposed from a mounting surface831of the resin layer830. In other words, the respective top faces50A of the plurality of first power conductors51A and51B, the plurality of first output conductors52A and52B, the plurality of first ground conductors53, the plurality of second power conductors54A and54B, the plurality of second output conductors55A and55B, the plurality of second ground conductors56, and the plurality of control conductors57are exposed from the mounting surface831. Here, the mounting surface831is formed when the resin layer830is removed by the mechanical grinding, and oriented to the same side as the base material obverse face811(seeFIG.21).

Referring toFIG.23, the manufacturing method of the semiconductor device1A includes a process of removing the base material810in the thickness direction. To be more detailed, the portion of the base material810including the base material reverse face812is removed, by the mechanical grinding. As result, the thickness of the base material810is reduced.

Referring toFIG.24, the manufacturing method of the semiconductor device1A includes a process of forming the plurality of terminals20. To be more detailed, the plurality of terminals20are formed in contact with the respective top faces50A of the plurality of conductors50, exposed from the mounting surface831of the resin layer830. The plurality of terminals20are each formed through a non-electrolytic plating process.

Referring toFIG.25, the manufacturing method of the semiconductor device1A includes a process of individuating the semiconductor device1A. To be more detailed, a dicing blade is used to cut the base material810and the resin layer830along cutting lines CL, to thereby divide into a plurality of individual pieces. Each of the individual pieces includes one semiconductor element60, and constitutes the semiconductor device1A. Through the foregoing process, the semiconductor device1A can be obtained.

In the manufacturing method of the semiconductor device1A, the plurality of conductors850are each formed of Cu. In the mentioned manufacturing method, the resin layer830is formed by molding, after the plurality of conductors850are respectively formed on the plurality of wirings840. The resin layer830is formed from a black epoxy resin, through the compression molding process.

During the formation process of the resin layer830, the assembled body, composed of the base material810and the resin layer830stacked on each other in the z-direction, may be warped. The warp of the assembled body herein refers to such a deformation that the periphery of the assembled body is elevated in the z-direction with respect to the central portion of the assembled body. Whereas the assembled body is adsorbed to a suction device for transportation in a subsequent process, the assembled body may fail to be properly adsorbed, because of the warp. In addition, the warp of the assembled body may impede the assembled body from being accurately cut by the dicing blade, in the individuation process. Thus, the warp may make it difficult to stably manufacture the semiconductor device1A.

In the case of the semiconductor device1A according to this embodiment, the assembled body is warped more largely in the x-direction, in which a first group including the first power conductors51A and51B, the first output conductors52A and52B, and the first ground conductor53, and a second group including the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56are aligned, than in the y-direction in which the control conductors57A and57B are aligned. On the basis of such a phenomenon, the inventor of the present disclosure has found out that the assembled body is warped more largely, with an increase in total volume of the first power conductors51A and51B, the first output conductors52A and52B, the first ground conductor53, the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56, for the following reasons.

In the compression molding process, the temperature in the cavity of the tooling increases, during the loading of the epoxy resin to be formed into the resin layer830, or during the solidification of the epoxy resin. Accordingly, the Cu constituting the plurality of conductors850is recrystallized. The Cu is condensed, in other words the plurality of conductors50are condensed because of the recrystallization, and therefore a stress is applied to the base material810and the resin layer830, which leads to the warp of the assembled body. Here, although the plurality of wirings40are also formed of Cu, the volume thereof is smaller than that of the plurality of conductors50, and therefore it can be assumed that the impact of the plurality of wirings40to the warp of the assembled body is smaller, than the impact of the plurality of conductors50.

Accordingly, in the plurality of conductors850, the total volume of the first power conductors851A and851B, the first output conductors852A and852B, the first ground conductor853, the second power conductors854A and854B, the second output conductors855A and855B, and the second ground conductor856, which are the cause of the large warp of the assembled body, is to be reduced. To be more detailed, the first power conductors851A and851B and the second power conductors854A and854B are each formed in a smaller volume than the first output conductors852A and852B, the first ground conductor853, the second output conductors855A and855B, and the second ground conductor856. Such a configuration reduces the stress originating from the condensation of the plurality of conductors850in the formation process of the resin layer830, thereby suppressing the warp of the assembled body.

The semiconductor device1A according to this embodiment provides the following advantageous effects.

(1-1) A larger current flows through the first circuit61than through the second circuit62, in the semiconductor element60. Accordingly, among the plurality of conductors50, the first power conductors51A and51B, the first output conductors52A and520, the first ground conductor53, the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56, which are electrically connected to the first circuit61, are each formed in a larger volume than the control conductors57, to reduce the electrical resistance in the conduction path between the first circuit61and the terminals20connected thereto. On the other hand, as described above, increasing the volume of the first power conductors51A and51A, the first output conductors52A and52B, the first ground conductor53, the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56leads to a larger warp of the assembled body composed of the base material810and the resin layer830, during the formation process of the resin layer830in the manufacturing process of the semiconductor device1A.

In this embodiment, therefore, the first power conductors51A and51B are each formed in a smaller volume, than the first output conductors52A and52B and the first ground conductor53. Likewise, the second power conductors54A and54B are each formed in a smaller volume, than the second output conductors55A and55B and the second ground conductor56. In this case, during the formation of the plurality of conductors850in the manufacturing process of the semiconductor device1A, the first power conductors851A and851B are each formed in a smaller volume than the first output conductors852A and852B and the first ground conductor853, and the second power conductors854A and854B are each formed in a smaller volume than the second output conductors855A and855B and the second ground conductor856. Therefore, the warp of the assembled body composed of the base material810and the resin layer830can be suppressed, during the formation process of the resin layer830. Such an arrangement facilitates the assembled body to be transported, and to be properly diced, in the subsequent process. Consequently, the electrical resistance in the conduction path between the first circuit61and the terminals20connected thereto can be reduced, and the semiconductor device1A can be stably manufactured.

(1-2) The respective top faces50A of the first power conductors51A and51B, exposed from the sealing resin30in the z-direction, are smaller in area than the respective top faces50A of the first output conductors52A and52B and the first ground conductor53, exposed from the sealing resin30in the z-direction. The respective top faces50A of the second power conductors54A and54B, exposed from the sealing resin30in the z-direction, are smaller in area than the respective top faces50A of the second output conductors55A and55B and the second ground conductor56, exposed from the sealing resin30in the z-direction. To attain such a configuration, the first power conductors851A and851B are each formed in a smaller volume than the first output conductors852A and852B and the first ground conductor853, and the second power conductors854A and854B are each formed in a smaller volume than the second output conductors855A and855B and the second ground conductor856, during the formation of the plurality of conductors850in the manufacturing process of the semiconductor device1A. Then by removing the resin layer830thereby reducing the thickness thereof, the respective top faces50A of the first power conductors51A and51B, exposed from the sealing resin30in the z-direction, are made smaller in area than the respective top faces50A of the first output conductors52A and52B and the first ground conductor53, exposed from the sealing resin30in the z-direction, and the respective top faces50A of the second power conductors54A and54B, exposed from the sealing resin30in the z-direction, are made smaller in area than the respective top faces50A of the second output conductors55A and55B and the second ground conductor56, exposed from the sealing resin30in the z-direction. Thus, the warp of the assembled body is suppressed owing to the relation in area among the top faces of the conductors850, exposed from the resin layer830in the z-direction as result of the grinding of the resin layer830. Therefore, the shape of the conductors850can be simplified, which facilitates the formation of the conductors850.

(1-3) The first output conductors52A and52B, the first ground conductor53, the second output conductors55A and55B, and the second ground conductor56are each larger in volume than the control conductors57. Such a configuration reduces the electrical resistance in the conduction path between the first circuit61, where a relatively large current flows, and the terminals20electrically connected to the first circuit61, thereby improving the heat dissipation performance of the semiconductor device1A.

(1-4) The respective top faces50A of the first output conductors52A and52B, the first ground conductor53, the second output conductors55A and55B, and the second ground conductor56are each larger in area, than the respective top faces50A of the control conductors57. Such a configuration enables the first output conductors52A and52B, the first ground conductor53, the second output conductors55A and55B, and the second ground conductor56to accept a larger current, than a current applied to the control conductors57.

In addition, the first output terminals22A and22B, the first ground terminal23, the second output terminals25A and25B, and the second ground terminal26are larger in area than the control terminals27, as viewed in the z-direction. Accordingly, when the semiconductor device1A is mounted on a circuit board (not shown), the bonding area between the wiring pattern of the circuit board, and the first output terminals22A and22B, the first ground terminal23, the second output terminals25A and25B, and the second ground terminal26becomes larger than the bonding area between the wiring pattern of the circuit board and the control terminals27. As result, the electrical resistance between the circuit board and the first output terminals22A and22B, the first ground terminal23, the second output terminals25A and25B, and the second ground terminal26becomes lower than the electrical resistance between the circuit board and the control terminals27. Consequently, the first output terminals22A and22B, the first ground terminal23, the second output terminals25A and25B, and the second ground terminal26can each accept a larger current than a current applied to the control terminals27.

(1-5) The plurality of control conductors57are located on the outer side in the y-direction, with respect to the first power conductors51A and51B, the first output conductors52A and52B, the first ground conductor53, the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56. Such a configuration enables the volume of the first output conductors52A and52B, the first ground conductor53, the second output conductors55A and55B, and the second ground conductor56to be increased, by increasing the length in the x-direction of the first output conductors52A and52B, the first ground conductor53, the second output conductors55A and55B, and the second ground conductor56. Therefore, the volume of the first output conductors52A and52B, the first ground conductor53, the second output conductors55A and55B, and the second ground conductor56can be increased, while suppressing an increase in size of the semiconductor device1A in the y-direction.

In addition, the plurality of control conductors57can be located so as to overlap with the first power conductors51A and51B, the first output conductors52A and52B, or the first ground conductor53as viewed in the y-direction, and so as to overlap with the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56as viewed in the y-direction. Therefore, the space for locating the plurality of control conductors57can be secured in the x-direction.

(1-6) The control conductors57include four distal control conductors57C respectively located at the four corners of the substrate10, and the intermediate control conductors57E located between two of the distal control conductors57C spaced apart from each other in the x-direction. The top face50A of the distal control conductor57C is larger in area than the top face50A of the intermediate control conductor579. With such a configuration, since the distal control conductors57C are larger in area, a higher bonding strength between the control conductor57and the circuit board can be attained at the four corners of the substrate10, when the semiconductor device1A is mounted on the circuit board, for example via solder. Therefore, concentration of thermal stress at the four corners of the substrate10, originating from the heat generated during the use of the semiconductor device1A, can be mitigated. As result, the solder between the semiconductor device1A and the circuit board can be exempted from suffering a crack.

(1-7) The respective top faces50A of the first output conductors52A and52B, the first ground conductor53, the second output conductors55A and55B, and the second ground conductor56are longer in the x-direction, than the respective top faces50A of the control conductors57. In other words, the respective top faces50A of the first output conductors52A and52B and the first ground conductor53are made longer in the x-direction, orthogonal to the y-direction in which the first power conductors51A and51B, the first output conductors52A and528, and the first ground conductor53are aligned. Likewise, the respective top faces50A of the second output conductors55A and55B and the second ground conductor56are made longer in the x-direction, orthogonal to the y-direction in which the first power conductors51A and51B, the first output conductors52A and52B, and the first ground conductor53are aligned. Such a configuration reduces the electrical resistance in the first output conductors52A and52B, the first ground conductor53, the second output conductors55A and55B, and the second ground conductor56, while suppressing an increase in size of the semiconductor device1A in the y-direction.

Further, increasing the length in the x-direction of the first output conductors52A and528and the first ground conductor53, opposed to the first circuit61in the x-direction, allows the first output conductors52A and52B and the first ground conductor53to be located closer to the first circuit61. In this case, the conduction path between the first output terminals22A and22B and the first ground terminal23, and the first circuit61, is shortened, and therefore the electrical resistance between the first output terminals22A and220and the first ground terminal23, and the first circuit61, can be reduced.

Likewise, increasing the length in the x-direction of the second output conductors55A and55B and the second ground conductor56, opposed to the first circuit61in the x-direction, allows the second output conductors55A and55B and the second ground conductor56to be located closer to the first circuit61. In this case, the conduction path between the second output terminals25A and25B and the second ground terminal26, and the first circuit61, is shortened, and therefore the electrical resistance between the second output terminals25A and25B and the second ground terminal26, and the first circuit61, can be reduced.

(1-8) Among the plurality of wirings40, the first power wirings41A and41B, the first output wirings42A and42B, the first ground wiring43, the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46are wider than the connecting wiring section47bof the control wiring47. Such a configuration reduces the electrical resistance of the wirings40connected to the first circuit61, where a larger current flows than in the second circuit62.

(1-9) The wiring40connected to one of the plurality of conductors50aligned in the y-direction along the end portions of the substrate10in the x-direction, having a larger volume, is wider than the wiring40connected to the conductor50having a smaller volume. In this embodiment, the first output wirings42A and42B and the first ground wiring43are each wider than the first power wirings41A and41B. The second output wirings45A and45B and the second ground wiring46are each wider than the second power wirings44A and44B. Increasing thus the width of the wirings40close to the first circuit61reduces the electrical resistance of the conduction path between the first circuit61and the terminal20.

(1-10) The plurality of control conductors57are each located on the outer side in the y-direction, with respect to the semiconductor element60. Such a configuration enables the space for locating the plurality of control conductors57to be secured in the x-direction. Therefore, a space between the control conductors57located adjacent to each other in the x-direction can be secured, which prevents the occurrence of a short circuit between the control conductors57, after the semiconductor device1A is mounted on the circuit board.

(1-11) The first output wirings42A and42B each include the sloped section42c, and the second output wirings45A and45B each include the sloped section45c. Such a configuration reduces the area of one of the end portions of the wide wiring section42aof the first output wirings42A and42B in the x-direction, closer to the narrow wiring section42b, and also reduces the area of one of the end portions of the wide wiring section45aof the second output wirings45A and45B in the x-direction, closer to the narrow wiring section45b. Therefore, the electrical resistance of the first output wirings42A and42B and the second output wirings45A and45B can be reduced.

(1-12) The respective narrow wiring sections41bof the first power wirings41A and41B are located closer to the center of the substrate10in the y-direction, than is the wide wiring section41a, and the respective narrow wiring sections44bof the second power wirings44A and44B are located closer to the center of the substrate10in the y-direction, than is the wide wiring section44a. Such a configuration allows the respective wide wiring sections42aof the first output wirings42A and42B to be made wider, and the respective wide wiring sections45aof the second output wirings45A and45B to be made wider. Therefore, the electrical resistance of each of the first output wirings42A and420, and the electrical resistance of each of the second output wirings45A and45B can be reduced.

(1-13) The semiconductor element60is flip-chip bonded onto the plurality of wirings40. Such a structure allows the sealing resin30to be thinner, compared with, for example, the case where the element obverse face60sof the semiconductor element60and the plurality of wirings40are connected via wires. Therefore, the semiconductor device1A can be formed in a lower height.

(1-14) The first ground wiring43includes the slit43a. The element electrodes60aof the semiconductor element60are bonded to the first ground wiring43, on both sides of the slit43a. In other words, the element electrodes60aon the first switching unit61A of the semiconductor element60are bonded to the first ground wiring43on the side of the substrate side face15with respect to the slit43a, and the element electrodes60aon the second switching unit61B are bonded to the first ground wiring43on the side of the substrate side face16with respect to the slit43a. Such a configuration prevents the noise generated from the first switching unit61A or the second switching unit61B from interfering with the other switching unit, when the semiconductor device1A is in use.

The second ground wiring46includes the slit46a. The element electrodes60aof the semiconductor element60are bonded to the second ground wiring46, on both sides of the slit46a. In other words, the element electrodes60aon the third switching unit61C of the semiconductor element60are bonded to the second ground wiring46on the side of the substrate side face15with respect to the slit46a, and the element electrodes60aon the fourth switching unit61D are bonded to the second ground wiring46on the side of the substrate side face16with respect to the slit46a. Such a configuration prevents the noise generated from the third switching unit61C or the fourth switching unit61D from interfering with the other switching unit, when the semiconductor device1A is in use.

(1-15) The plurality of conductors50are located on the inner side of the peripheral edge of the sealing resin30, as viewed in the z-direction. Accordingly, the plurality of conductors50are exempted from being cut by the dicing blade, when the resin layer830and the base material810are cut into individual pieces, in the manufacturing process of the semiconductor device1A. Therefore, the plurality of conductors50can be prevented from suffering a damage.

Referring now toFIG.26toFIG.28, a semiconductor device1B according to a second embodiment of the first aspect will be described hereunder. The semiconductor device1B according to this embodiment is different from the semiconductor device1A according to the first embodiment, in the configuration of the plurality of terminals, the plurality of wirings, the plurality of conductors, and the semiconductor element. In the following description, the elements employed in common with the semiconductor device1A according to the first embodiment are given the same numeral, and the description thereof may be skipped.

As shown inFIG.27andFIG.28, the semiconductor device1B includes a plurality of wirings40X, a plurality of conductors50X, and a semiconductor element60X. The semiconductor element60X includes the first circuit61and the second circuit62. The first circuit61includes a fewer number of switching units, than the first circuit61(seeFIG.4) of the first embodiment. The first circuit61includes the first switching unit61A and the second switching unit61B. In other words, the first circuit61according to this embodiment is without the third switching unit61C and the fourth switching unit61D. The switching units61A and61B have the same configuration as the switching units61A and61B of the first embodiment. The second circuit62includes a control circuit that controls the switching units61A and61B.

In this embodiment, as shown inFIG.27, the circuit region RD where the second circuit62is formed has the same size and shape, as the circuit region RD of the first embodiment. In other words, the circuit region RD according to this embodiment includes two recesses RD1and RD, and the regions R1to R4.

The circuit region RSA, where the first switching unit61A according to this embodiment is formed, is larger than the circuit region RSA of the first embodiment. The circuit region RSA according to this embodiment is approximately twice as large in area, as the circuit region RSA of the first embodiment. The circuit region RSA according to this embodiment has a rectangular shape having the long sides extending in the y-direction and the short sides extending in the x-direction, as viewed in the z-direction.

The circuit region RSB, where the second switching unit61B according to this embodiment is formed, is larger than the circuit region RSB of the first embodiment. The circuit region RSB according to this embodiment is approximately twice as large in area, as the circuit region RSB of the first embodiment. The circuit region RSB according to this embodiment has a rectangular shape having the long sides extending in the y-direction and the short sides extending in the x-direction, as viewed in the z-direction. The circuit region RSB has the same size as the circuit region RSA.

The circuit region RSA is located inside the recess RD1of the circuit region RD, and the circuit region RSB is located inside the recess RD2of the circuit region RD. The circuit region RSA is aligned with the circuit region RSB in the y-direction, and spaced therefrom in the x-direction.

The plurality of wirings40X include a first power wiring41, a first output wiring42, the first ground wiring43, a second power wiring44, a second output wiring45, and the second ground wiring46. In other words, the plurality of wirings40X according to this embodiment are different from the plurality of wirings40of the first embodiment, in only including one each of the first power wiring, the first output wiring, the second power wiring, and the second output wiring. The plurality of wirings40X include the plurality of control wirings47. The number of the plurality of control wirings47is equal to that of the plurality of control wirings47in the plurality of wirings40of the first embodiment. In this embodiment, the first power wiring41and the second power wiring44correspond to the first drive wiring, and the first output wiring42, the first ground wiring43, the second output wiring45, and the second ground wiring46correspond to the second drive wiring.

The first power wiring41, the first output wiring42, and the first ground wiring43are electrically connected to the first switching unit61A. In other words, the first power wiring41serves to supply a current from an external power source (not shown) to the first switching unit61A, the first output wiring42serves to output the current from the first switching unit61A to outside of the semiconductor device18, and the first ground wiring43serves to provide the ground for the first switching unit61A.

The first power wiring41, the first output wiring42, and the first ground wiring43are located close to the substrate side face13, in the x-direction. The first power wiring41, the first output wiring42, and the first ground wiring43are aligned with each other in the x-direction, and spaced apart from each other in the y-direction. The first ground wiring43is located at the central position of the substrate obverse face11, in the y-direction. The first power wiring41and the first output wiring42are separately located on the respective sides of the first ground wiring43, in the y-direction. The first power wiring41is located on the side of the substrate side face15in the y-direction, with respect to the first ground wiring43. The first output wiring42is located on the side of the substrate side face16in the y-direction, with respect to the first ground wiring43.

The second power wiring44, the second output wiring45, and the second ground wiring46are electrically connected to the second switching unit618. In other words, the second power wiring44serves to supply a current from an external power source (not shown) to the second switching unit618, the second output wiring45serves to output the current from the second switching unit61B to outside of the semiconductor device1B, and the second ground wiring46serves to provide the ground for the second switching unit618.

The second power wiring44, the second output wiring45, and the second ground wiring46are located close to the substrate side face14, in the x-direction. The second power wiring44, the second output wiring45, and the second ground wiring46are aligned with each other in the x-direction, and spaced apart from each other in the y-direction. The second ground wiring46is located at the central position of the substrate obverse face11, in the y-direction. The second power wiring44and the second output wiring45are separately located on the respective sides of the second ground wiring46, in the y-direction. The second power wiring44is located on the side of the substrate side face15in the y-direction, with respect to the second ground wiring46. The second output wiring45is located on the side of the substrate side face16in the y-direction, with respect to the second ground wiring46.

The second power wiring44, the second output wiring45, and the second ground wiring46are spaced apart from the first power wiring41, the first output wiring42, and the first ground wiring43, in the x-direction. As viewed in the x-direction, the second power wiring44overlaps with the first power wiring41, the second output wiring45overlaps with the first output wiring4, and the second ground wiring46overlaps with the first ground wiring43.

Further, the first power wiring41, the first output wiring42, the first ground wiring43, the second power wiring44, the second output wiring45, and the second ground wiring46are different in shape, compared with the plurality of wirings40of the first embodiment.

As shown inFIG.28, the first power wiring41includes the wide wiring section41aand the narrow wiring section41b. In other words, the first power wiring41is without the connecting wiring section41c, unlike the first power wirings41A and41B of the first embodiment. The wide wiring section41ais wider than the wide wiring section41aof the first power wirings41A and41B of the first embodiment. The narrow wiring section41bis wider than the narrow wiring section41bof the first power wirings41A and41B of the first embodiment. To the narrow wiring section41b, eight element electrodes60aof the semiconductor element60X are bonded. The eight element electrodes60aare arranged in two rows, each including four element electrodes60aaligned with each other in the y-direction and spaced apart from each other in the x-direction. The two rows of the element electrodes60aare aligned with each other in the x-direction, and spaced apart from each other in the y-direction.

The narrow wiring section41bis located on the side of the first ground wiring43(substrate side face16) in the y-direction, with respect to the wide wiring section41a. Accordingly, the first power wiring41includes the recessed region41d. In the recessed region41d, the connecting end section47cof the control wiring47, electrically connected to the first region R1(seeFIG.27) of the second circuit62, is located.

The shape of the first output wiring42viewed in the z-direction is generally symmetrical to that of the first power wiring41, with respect to an imaginary center line of the substrate10, passing the center thereof in the y-direction and extending in the x-direction. Accordingly, the first output wiring42includes, like the wide wiring section41aand the narrow wiring section41bof the first power wiring41, the wide wiring section42aand the narrow wiring section42b. To the narrow wiring section42b, eight element electrodes60aare bonded. The arrangement pattern of these eight element electrodes60aon the narrow wiring section42bis the same as that of the eight element electrodes60aon the narrow wiring section41bof the first output wiring42A. In addition, the first output wiring42includes the recessed region42d, like the recessed region41dof the first power wiring41. In the recessed region42d, the connecting end section47cof the control wiring47, electrically connected to the second region R2(seeFIG.27) of the second circuit62, is located.

The first ground wiring43extends along the x-direction. The first ground wiring43is without the slit43a. The shape of the second power wiring44viewed in the z-direction is symmetrical to that of the first power wiring41, with respect to the imaginary center line of the substrate10, passing the center thereof in the x-direction and extending in the y-direction. Accordingly, the second power wiring44includes, like the wide wiring section41aand the narrow wiring section41bof the first power wiring41, the wide wiring section44aand the narrow wiring section44b. To the narrow wiring section44b, eight element electrodes60aare bonded. The arrangement pattern of these eight element electrodes60aon the narrow wiring section44bis the same as that of the eight element electrodes60aon the narrow wiring section41b. In addition, the second power wiring44includes the recessed region44d, like the recessed region41dof the first power wiring41. In the recessed region44d, the connecting end section47cof the control wiring47, electrically connected to the third region R3(seeFIG.27) of the second circuit62, is located.

The shape of the second output wiring45viewed in the z-direction is symmetrical to that of the first output wiring42, with respect to the imaginary center line of the substrate10, passing the center thereof in the x-direction and extending in the y-direction. Accordingly, the second output wiring45includes, like the wide wiring section42aand the narrow wiring section42bof the first output wiring42, the wide wiring section45aand the narrow wiring section45b. In addition, the second output wiring45includes the recessed region45d, like the recessed region42dof the first output wiring42. In the recessed region45d, the connecting end section47cof the control wiring47, electrically connected to the fourth region R4(seeFIG.27) of the second circuit62, is located.

The shape of the second ground wiring46viewed in the z-direction is symmetrical to that of the first ground wiring43, with respect to the imaginary center line of the substrate10, passing the center thereof in the x-direction and extending in the y-direction. The second ground wiring46is without the slit46a. Here, the number of element electrodes60abonded to each of the wirings41to46may be changed as desired.

The plurality of conductors50X according to this embodiment include a first power conductor51, a first output conductor52, the first ground conductor53, a second power conductor54, a second output conductor55, and the second ground conductor56. In other words, the plurality of conductors50X according to this embodiment are different from the plurality of conductors50of the first embodiment, in only including one each of the first power wiring, the first output wiring, the second power wiring, and the second output wiring. The plurality of conductors50X also include the plurality of control conductors57. The number of the plurality of control conductors57is equal to that of the plurality of control conductors57, in the plurality of conductors50of the first embodiment. In this embodiment, the first power conductor51and the second power conductor54correspond to the first drive conductor, and the first output conductor52, the first ground conductor53, the second output conductor55, and the second ground conductor56correspond to the second drive conductor.

The first power conductor51has the same size and shape, as the first power conductor51A of the first embodiment. Accordingly, the top face50A of the first power conductor51has the same area as the top face50A of the first power conductor51A. The first power conductor51has the same volume as the first power conductor51A.

The first output conductor52has the same size and shape, as the first output conductor52A of the first embodiment. Accordingly, the top face50A of the first output conductor52has the same area as the top face50A of the first output conductor52A. The first output conductor52has the same volume as the first output conductor52A.

The first ground conductor53has the same size and shape, as the first ground conductor53of the first embodiment. Accordingly, the top face50A of the first ground conductor53according to this embodiment has the same area as the top face50A of the first ground conductor53of the first embodiment. The first ground conductor53according to this embodiment has the same volume as the first ground conductor53of the first embodiment.

Therefore, the top face50A of the first power conductor51is smaller in area than the top face50A of the first output conductor52and the top face50A of the first ground conductor53. The top face50A of the first output conductor52has the same area as the top face50A of the first ground conductor53. The first power conductor51is smaller in volume than the first output conductor52and the first ground conductor53. The first output conductor52has the same volume as the first ground conductor53.

In this embodiment, further, since the number of first power wirings and the number of first output wirings are fewer than those of the first embodiment, the first power wiring41and the first output wiring42each have an increased width.

As shown inFIG.26, the first power wiring41is equal to or more than twice as wide as the length of the top face50A of the first power conductor51in the y-direction. In this embodiment, the width of the first power wiring41is between twice and three times, both ends inclusive, of the width of the first power conductor51. The first output wiring42is equal to or more than twice as wide as the length of the top face50A of the first output conductor52in the y-direction. In this embodiment, the width of the first output wiring42is between twice and three times, both ends inclusive, of the length of the top face50A of the first output conductor52in the y-direction.

The second power conductor54has the same size and shape as the second power conductor54A of the first embodiment. Accordingly, the top face50A of the second power conductor54has the same area as the top face50A of the second power conductor54A. The second power conductor54has the same volume as the second power conductor54A.

The second output conductor55has the same size and shape as the second output conductor55A of the first embodiment. Accordingly, the top face50A of the second output conductor55has the same area as the top face50A of the second output conductor55A. The second output conductor55has the same volume as the second output conductor55A.

The second ground conductor56has the same size and shape, as the second ground conductor56of the first embodiment. Accordingly, the top face50A of the second ground conductor56according to this embodiment has the same area as the top face50A of the second ground conductor56of the first embodiment. The second ground conductor56according to this embodiment has the same volume as the second ground conductor56of the first embodiment.

Therefore, the top face50A of the second power conductor54is smaller in area than the top face50A of the second output conductor55and the top face50A of the second ground conductor56. The top face50A of the second output conductor55has the same area as the top face50A of the second ground conductor56. The second power conductor54is smaller in volume than the second output conductor55and the second ground conductor56. The second output conductor55has the same volume as the second ground conductor56.

In this embodiment, further, since the number of second power wirings and the number of second output wirings are fewer than those of the first embodiment, the second power wiring44and the second output wiring45each have an increased width.

As shown inFIG.28, the second power wiring44is equal to or more than twice as wide as the length of the top face50A of the second power conductor54in the y-direction. In this embodiment, the width of the second power wiring44is between twice and three times, both ends inclusive, of the length of the top face50A of the second power conductor54in the y-direction. The second output wiring45is equal to or more than twice as wide as the length of the top face50A of the first output conductor52in the y-direction. In this embodiment, the width of the second output wiring45is between twice and three times, both ends inclusive, of the length of the top face50A of the second output conductor55in the y-direction.

As shown inFIG.26, the semiconductor device18includes a plurality of terminals20X. The plurality of terminals20X include a first power terminal21, a first output terminal22, the first ground terminal23, a second power terminal24, a second output terminal25, and the second ground terminal26. In other words, the plurality of terminals20X according to this embodiment is different from the plurality of terminals20of the first embodiment, in only including one each of the first power terminal, the first output terminal, the second power terminal, and the second output terminal. The plurality of terminals20X also include the plurality of control terminals27. The number of the plurality of control terminals27is equal to that of the plurality of control terminals27in the plurality of terminals20of the first embodiment. In this embodiment, the first power terminal21and the second power terminal24correspond to the first drive terminal, and the first output terminal22, the first ground terminal23, the second output terminal25, and the second ground terminal26correspond to the second drive terminal.

The semiconductor device1B according to this embodiment provides the following advantageous effects, in addition to those provided by the first embodiment.

(2-1) The first power conductor51, the first output conductor52, and the first ground conductor53are aligned along one of the end portions of the sealing resin30in the x-direction, and the second power conductor54, the second output conductor55, and the second ground conductor56are aligned along the other end portion of the sealing resin30in the x-direction. Thus, a fewer number of conductors50larger in volume than the control conductor57are provided, compared with the first embodiment. Therefore, the warp of the assembled body composed of the resin layer830and the base material810(seeFIG.25for both) can be minimized.

In addition, a fewer number of wirings40are connected to the first circuit61, compared with the first embodiment. In other words, a fewer number of wirings40are aligned in the y-direction. Accordingly, the first power wiring41and the first output wiring42are each made wider, in this embodiment. In addition, the second power wiring44and the second output wiring45are each made wider. Therefore, the electrical resistance of each of the first power wiring41, the first output wiring42, the second power wiring44, and the second output wiring45can be reduced.

(2-2) The first power wiring41is equal to or more than twice as wide as the length of the top face50A of the first power conductor51in the y-direction, and the second power wiring44is equal to or more than twice as wide as the length of the top face50A of the second power conductor54. Therefore, the electrical resistance of each of the first power wiring41and the second power wiring44can be reduced. Such a configuration is appropriate for supplying a larger current to each of the first switching unit61A and the second switching unit61B of the first circuit61.

(2-3) The first output wiring42is equal to or more than twice as wide as the length of the top face50A of the first output conductor52in the y-direction, and the second output wiring45is equal to or more than twice as wide as the length of the top face50A of the second output conductor55. Therefore, the electrical resistance of each of the first output wiring42and the second output wiring45can be reduced. Such a configuration is appropriate for supplying a larger current to each of the first switching unit61A and the second switching unit618of the first circuit61.

The foregoing embodiments merely exemplify possible configurations of the semiconductor device according to the present disclosure, and are in no way intended to limit the configuration. The semiconductor device according to the present disclosure may assume a form different from those exemplified by the embodiments. For example, a part of the configuration of the foregoing embodiments may be substituted, modified, or excluded, and a new element may be added to the foregoing embodiments. Further, the variations described hereunder may be combined with each other, unless a technical contradiction is incurred. In the following variations, the elements employed in common with the embodiments are given the same numeral, and the description thereof will not be repeated.

In the first embodiment, the shape of each of the first power wirings41A and41B, the first output wirings42A and428, the first ground wiring43, the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46may be modified. For example, the shape of these wirings may be modified to a first example shown inFIG.29, or a second example shown inFIG.30.

In the first example, as shown inFIG.29, the plurality of wirings40are narrower than the plurality of wirings40of the first embodiment. To be more detailed, the first power wirings41A and41B each include, like the first power wiring41A of the first embodiment, the wide wiring section41a, the narrow wiring section41b, and the connecting wiring section41c. The wide wiring section41aof the first power wiring41A is narrower than the wide wiring section41aof the first power wiring41A of the first embodiment, and the wide wiring section41aof the first power wiring41B is narrower than the wide wiring section41aof the first power wiring41B of the first embodiment. In the illustrated example, the wide wiring section41aof the first power wiring41A has the same width as the length of the top face50A of the first power conductor51A in the y-direction, and the wide wiring section41aof the first power wiring41B has the same width as the length of the top face50A of the first power conductor51B in the y-direction. Here, when the difference between the width of the wide wiring section41aof the first power wiring41A and the length of the top face50A of the first power conductor51A in the y-direction is, for example, within 5% of the length of the top face50A of the first power conductor51A in the y-direction, the width of the wide wiring section41aof the first power wiring41A may be regarded as being equal to the length of the top face50A of the first power conductor51A in the y-direction. Likewise, when the difference between the width of the wide wiring section41aof the first power wiring41B and the length of the top face50A of the first power conductor51B in the y-direction is, for example, within 51 of the length of the top face50A of the first power conductor51B in the y-direction, the width of the wide wiring section41aof the first power wiring41B may be regarded as being equal to the length of the top face50A of the first power conductor51B in the y-direction.

In the illustrated example, the connecting wiring section41cof the first power wiring41A is narrower than the connecting wiring section41cof the first power wiring41A of the first embodiment, and the connecting wiring section41cof the first power wiring41B is narrower than the connecting wiring section41cof the first power wiring41B of the first embodiment. In the illustrated example, the connecting wiring section41cof the first power wiring41A has the same width as the narrow wiring section41bof the first power wiring41A, and the connecting wiring section41cof the first power wiring419has the same width as the narrow wiring section41bof the first power wiring41B.

The first output wirings42A and42B each include an outer wiring section42eand an inner wiring section42f. The inner wiring section42fof the first output wiring42A corresponds to the narrow wiring section42bof the first output wiring42A of the first embodiment, and the inner wiring section42fof the first output wiring42B corresponds to the narrow wiring section42bof the first output wiring42B of the first embodiment. The outer wiring section42eof the first output wiring42A is located on the outer side (on the side of the substrate side face13) in the x-direction, with respect to the inner wiring section42fof the first output wiring42A. The outer wiring section42eof the first output wiring42B is located on the outer side (on the side of the substrate side face13) in the x-direction, with respect to the inner wiring section42fof the first output wiring42b.

In the illustrated example, the outer wiring section42eof the first output wiring42A is narrower than the inner wiring section42fof the first output wiring42A. On the outer wiring section42e, the first output conductor52A is located. The outer wiring section42ehas the same width as the length of the top face50A of the first output conductor52A in the y-direction. Here, when the difference between the width of the outer wiring section42eand the length of the top face50A of the first output conductor52A in the y-direction is, for example, within 5% of the length of the top face50A of the first output conductor52A in the y-direction, the width of the outer wiring section42emay be regarded as being equal to the length of the top face50A of the first output conductor52A in the y-direction.

In the illustrated example, the outer wiring section42eof the first output wiring42B is narrower than the inner wiring section42fof the first output wiring42B. On the outer wiring section42e, the first output conductor52B is located. The outer wiring section42ehas the same width as the length of the top face50A of the first output conductor52B in the y-direction. Here, when the difference between the width of the outer wiring section42eand the length of the top face50A of the first output conductor52B in the y-direction is, for example, within 5% of the length of the top face50A of the first output conductor52B in the y-direction, the width of the outer wiring section42emay be regarded as being equal to the length of the top face50A of the first output conductor52B in the y-direction.

The first ground wiring43includes an outer wiring section43dand an inner wiring section43e. The inner wiring section43eincludes the slit43aextending in the x-direction. The inner wiring section43ecorresponds to the portion of the first ground wiring43where the slit43ais formed in the x-direction, and overlaps with the semiconductor element60see (FIG.4), as viewed in the z-direction. The inner wiring section43eincludes a first wiring section43band a second wiring section43c, defined by the slit43a. The outer wiring section43dis located on the outer side (on the side of the substrate side face13) in the x-direction, with respect to the inner wiring section43e. The outer wiring section43dmay also be described as being located on the outer side (on the side of the substrate side face13) in the x-direction, with respect to the slit43a.

In the illustrated example, the inner wiring section43eis narrower than the first ground wiring43of the first embodiment. The outer wiring section43dis narrower than the inner wiring section43e. The outer wiring section43dhas the same width as the length of the top face50A of the first ground conductor53in the y-direction. Here, when the difference between the width of the outer wiring section43dand the length of the top face50A of the first ground conductor53in the y-direction is, for example, within 5% of the length of the top face50A of the first ground conductor53in the y-direction, the width of the outer wiring section43dmay be regarded as being equal to the length of the top face50A of the first ground conductor53in the y-direction.

The shape of the second power wirings44A and44B viewed in the z-direction is symmetrical to that of the first power wirings41A and41B, with respect to the imaginary center line of the substrate10, passing the center thereof in the x-direction and extending in the y-direction. Accordingly, the wide wiring section44aof the second power wiring44A corresponds to the wide wiring section41aof the first power wiring41A, the narrow wiring section44bof the second power wiring44A corresponds to the narrow wiring section41bof the first power wiring41A, and the connecting wiring section44cof the second power wiring44A corresponds to the connecting wiring section41cof the first power wiring41A. Likewise, the wide wiring section44aof the second power wiring44B corresponds to the wide wiring section41aof the first power wiring41B, the narrow wiring section44bof the second power wiring44B corresponds to the narrow wiring section41bof the first power wiring41B, and the connecting wiring section44cof the second power wiring44B corresponds to the connecting wiring section41cof the first power wiring41B.

On the wide wiring section44aof the second power wiring44A, the second power conductor54A is located, and on the wide wiring section44aof the second power wiring44B, the second power conductor54B is located. The wide wiring section44aof the second power wiring44A has the same width as the length of the top face50A of the second power conductor54A in the y-direction, and the wide wiring section44aof the second power wiring44B has the same width as the length of the top face50A of the second power conductor54B in the y-direction. Here, when the difference between the width of the wide wiring section44aof the second power wiring44A and the length of the top face50A of the second power conductor54A in the y-direction is, for example, within 5% of the length of the top face50A of the second power conductor54A in the y-direction, the width of the wide wiring section44aof the second power wiring44A may be regarded as being equal to the length of the top face50A of the second power conductor54A in the y-direction. Likewise, when the difference between the width of the wide wiring section44aof the second power wiring44B and the length of the top face50A of the second power conductor54B in the y-direction is, for example, within 5% of the length of the top face50A of the second power conductor54B in the y-direction, the width of the wide wiring section44aof the second power wiring44B may be regarded as being equal to the length of the top face50A of the second power conductor54B in the y-direction.

The shape of the second output wirings45A and45B viewed in the z-direction is symmetrical to that of the first output wirings42A and42B, with respect to the imaginary center line of the substrate10, passing the center thereof in the x-direction and extending in the y-direction. Accordingly, the second output wirings45A and45B each include an outer wiring section45eand an inner wiring section45f. The outer wiring section45ecorresponds to the outer wiring section42e, and the inner wiring section45fcorresponds to the inner wiring section42f.

On the outer wiring section45eof the second output wiring45A, the second output conductor55A is located, and on the outer wiring section45eof the second output wiring45B, the second output conductor55B is located. The outer wiring section45eof the second output wiring45A has the same width as the length of the top face50A of the second output conductor55A in the y-direction, and the outer wiring section45eof the second output wiring45B has the same width as the length of the top face50A of the second output conductor55B in the y-direction. Here, when the difference between the width of the outer wiring section45eof the second output wiring45A and the length of the top face50A of the second output conductor55A in the y-direction is, for example, within 5% of the length of the top face50A of the second output conductor55A in the y-direction, the width of the outer wiring section45eof the second output wiring45A may be regarded as being equal to the length of the top face50A of the second output conductor55A in the y-direction. Likewise, when the difference between the width of the outer wiring section45eof the second output wiring45B and the length of the top face50A of the second output conductor55B in the y-direction is, for example, within 5% of the length of the top face50A of the second output conductor55B in the y-direction, the width of the outer wiring section45eof the second output wiring45B may be regarded as being equal to the length of the top face50A of the second output conductor55B in the y-direction.

The shape of the second ground wiring46viewed in the z-direction is symmetrical to that of the first ground wiring43, with respect to the imaginary center line of the substrate10, passing the center thereof in the x-direction and extending in the y-direction. Accordingly, the second ground wiring46includes an outer wiring section46dand an inner wiring section46e. The outer wiring section46dcorresponds to the outer wiring section43d, and the inner wiring section46ecorresponds to the inner wiring section43e.

On the outer wiring section46d, the second ground conductor56is located. The outer wiring section46dhas the same width as the length of the top face50A of the second ground conductor56in the y-direction. Here, when the difference between the width of the outer wiring section46dand the length of the top face50A of the second ground conductor56in the y-direction is, for example, within 5% of the length of the top face50A of the second ground conductor56in the y-direction, the width of the outer wiring section46dmay be regarded as being equal to the length of the top face50A of the second ground conductor56in the y-direction. With the mentioned configuration, the same advantageous effects as (1-1) to (1-8), (1-11), and (1-15) from the first embodiment can be attained.

In the second example, as shown inFIG.30, the respective shapes viewed in the z-direction, of the first power wirings41A and41B, the first output wirings42A and428, the second power wirings44A and44B, and the second output wirings45A and45B are different from those of the first power wirings41A and41B, the first output wirings42A and42B, the second power wirings44A and44B, and the second output wirings45A and45B of the first embodiment.

The first power wiring41A is different from the first power wiring41A of the first embodiment, in being without the connecting wiring section41c, in the position of the narrow wiring section41bwith respect to the wide wiring section41ain the y-direction, and in the width of the wide wiring section41a. To be more detailed, the narrow wiring section41bextends from the wide wiring section41ain the x-direction, toward the center of the substrate10. As viewed in the x-direction, the narrow wiring section41boverlaps with the wide wiring section41a. The narrow wiring section41bis slightly shifted in the y-direction toward the first output wiring42A, with respect to the wide wiring section41a. The wide wiring section41ais wider than the wide wiring section41aof the first power wiring41A of the first embodiment. In the illustrated example, the width of the wide wiring section41ais approximately 150% of the length of the top face50A of the first power conductor51A in the y-direction. The first power conductor51A is located in the region of the wide wiring section41aon the side of the substrate side face15(opposite side of the first output wiring42A) in the y-direction. The wide wiring section41aincludes a sloped section41g, formed in the vicinity of the narrow wiring section41bin the x-direction. The sloped section41gis formed in the wide wiring section41aat the position on the side of the substrate side face15(opposite side of the first output wiring42A) in the y-direction, and obliquely extends so as to be closer to the first output wiring42A (substrate side face16), toward the narrow wiring section41bin the x-direction.

The narrow wiring section41bincludes a widened section41f, where the width of the narrow wiring section41bis increased. The widened section41fprotrudes from the narrow wiring section41bin the y-direction, to the opposite side of the first output wiring42A. The widened section41fhas a trapezoidal shape, as viewed in the z-direction.

The first power wiring41B is different from the first power wiring41B of the first embodiment, in the position of the narrow wiring section41bwith respect to the wide wiring section41ain the y-direction, and in the width of the wide wiring section41a. To be more detailed, the narrow wiring section41bis located so as to overlap with the wide wiring section41a, as viewed in the x-direction. The narrow wiring section41bis slightly shifted in the y-direction toward the first output wiring42B, with respect to the wide wiring section41a. The wide wiring section41ais wider than the wide wiring section41aof the first power wiring41B of the first embodiment. In the illustrated example, the width of the wide wiring section41ais approximately 150% of the length of the top face50A of the first power conductor51B in the y-direction. The first power conductor51B is located in the region of the wide wiring section41aon the side of the substrate side face16(opposite side of the first output wiring42B) in the y-direction. The wide wiring section41aincludes the sloped section41g, formed in the vicinity of the narrow wiring section41bin the x-direction. The sloped section41gis formed in the wide wiring section41aat the position on the side of the substrate side face16(opposite side of the first output wiring42B) in the y-direction, and obliquely extends so as to be closer to the first output wiring42B (substrate side face15), toward the narrow wiring section41bin the x-direction.

The narrow wiring section41bincludes the widened section41f, like the narrow wiring section41bof the first power wiring41A. The widened section41fprotrudes from the narrow wiring section41bin the y-direction, to the opposite side of the first output wiring428. The widened section41fhas a trapezoidal shape, as viewed in the z-direction.

The first output wiring42A is different from the first output wiring42A of the first embodiment, in the shape of the wide wiring section42a. The wide wiring section42aof the first output wiring42A shown inFIG.30is narrower than the wide wiring section42aof the first output wiring42A of the first embodiment. The wide wiring section42aof the first output wiring42A is wider than the length of the top face50A of the first output conductor52A in the y-direction, but narrower than 150% of the length of the top face50A of the first output conductor52A in the y-direction. The wide wiring section42ais slightly wider than the narrow wiring section42b.

The first output wiring420is different from the first output wiring42B of the first embodiment, in the shape of the wide wiring section42a. The wide wiring section42aof the first output wiring42B shown inFIG.30is narrower than the wide wiring section42aof the first output wiring42B of the first embodiment. The wide wiring section42aof the first output wiring428is wider than the length of the top face50A of the first output conductor52B in the y-direction, but narrower than 150% of the length of the top face50A of the first output conductor52B in the y-direction. The wide wiring section42ais slightly wider than the narrow wiring section42b.

The shape of the second power wirings44A and44B viewed in the z-direction is symmetrical to that of the first power wirings41A and41B, with respect to the imaginary center line of the substrate10, passing the center thereof in the x-direction and extending in the y-direction. Accordingly, the second power wirings44A and44B each include a sloped section44gformed in the wide wiring section44a, and a widened section44fformed in the narrow wiring section44b.

The sloped section44gof the second power wiring44A is formed in the wide wiring section44aat the position on the side of the substrate side face15(opposite side of the second output wiring45A) in the y-direction, and obliquely extends so as to be closer to the second output wiring45A (substrate side face16), toward the narrow wiring section44bin the x-direction. The widened section44fof the second power wiring44A protrudes from the narrow wiring section44b, to the opposite side of the second output wiring45A.

The sloped section44gof the second power wiring44B is formed in the wide wiring section44aat the position on the side of the substrate side face16(opposite side of the second output wiring45B) in the y-direction, and obliquely extends so as to be closer to the second output wiring45B (substrate side face15), toward the narrow wiring section44bin the x-direction. The widened section44fof the second power wiring44B protrudes from the narrow wiring section44b, to the opposite side of the second output wiring45B.

The shape of the second output wirings45A and45B viewed in the z-direction is symmetrical to that of the first output wirings42A and42B, with respect to the imaginary center line of the substrate10, passing the center thereof in the x-direction and extending in the y-direction. The wide wiring section45aof the second output wiring45A has the same width as the wide wiring section42aof the first output wiring42A, and the wide wiring section45aof the second output wiring45B has the same width as the wide wiring section42aof the first output wiring42B.

The mentioned configuration provides the following advantageous effects, in addition to (1-1) to (1-8), (1-11), and (1-15) from the first embodiment. The wide wiring section41aof each of the first power wirings41A and41B includes the sloped section41g, formed in the vicinity of the narrow wiring section41b. Such a configuration suppresses a reduction in area of the region between the wide wiring section41aand the narrow wiring section41b, thereby reducing the electrical resistance of the first power wirings41A and41B. Likewise, the wide wiring section44aof each of the second power wirings44A and44B includes the sloped section41g, formed in the vicinity of the narrow wiring section44b. Such a configuration reduces the electrical resistance of the second power wirings44A and44B, as in the case of the first power wirings41A and41B.

In addition, the narrow wiring section41bof each of the first power wirings41A and41B includes the widened section41f, and the narrow wiring section44bof each of the second power wirings44A and44B includes the widened section44f. Therefore, the electrical resistance of the first power wirings41A and41B and the second power wirings44A and44B can be reduced.

In the variation shown inFIG.30, the element electrode60aof the semiconductor element60may be bonded to the widened section41fof the first power wirings41A and41B. Likewise, the element electrode60amay be bonded to the widened section44fof the second power wirings44A and44B. Further, the plurality of wirings40X of the semiconductor device1B according to the second embodiment may also be made narrower, like the plurality of wirings40shown inFIG.29andFIG.30.

In the first embodiment, the respective top faces50A of the first power conductors51A and51B, the first output conductors52A and52B, the first ground conductor53, the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56, which are exposed from the sealing resin30in the z-direction, may each be formed in a different shape as desired. For example, the shape of those top faces50A may be modified as a first example shown inFIG.31, a second example shown inFIG.32, a third example shown inFIG.33, a fourth example shown inFIG.34, or a fifth example shown inFIG.35. InFIG.31toFIG.35, the plurality of terminals20are omitted for the sake of clarity.

In the first example, as shown inFIG.31, the top face50A of each of the first power conductors51A and51B has the same length in the x-direction, as the top face50A of the first output conductors52A and52B, and the top face50A of the first ground conductor53. On the other hand, the top face50A of each of the first power conductors51A and51B is shorter in the y-direction, than the top face50A of the first output conductors52A and52B, and the top face50A of the first ground conductor53. Accordingly, the top face50A of each of the first power conductors51A and51B is smaller in area, than the top face50A of the first output conductors52A and523, and the top face50A of the first ground conductor53.

Though not shown, the first power conductors51A and51B have the same thickness as the first output conductors52A and52B, and the first ground conductor53. Accordingly, the first power conductors51A and51B are smaller in volume, than the first output conductors52A and52B and the first ground conductor53.

In addition, as shown inFIG.31, the top face50A of each of the second power conductors54A and54B has the same length in the x-direction, as the top face50A of the second output conductors55A and55B, and the top face50A of the second ground conductor56. On the other hand, the top face50A of each of the second power conductors54A and54B is shorter in the y-direction, than the top face50A of the second output conductors55A and55B, and the top face50A of the second ground conductor56. Accordingly, the top face50A of each of the second power conductors54A and54B is smaller in area, than the top face50A of the second output conductors55A and55B, and the top face50A of the second ground conductor56.

Though not shown, the second power conductors54A and54B have the same thickness as the second output conductors55A and55B, and the second ground conductor56. Accordingly, the second power conductors54A and54B are smaller in volume, than the second output conductors55A and55B and the second ground conductor56.

In the second example, as shown inFIG.32, the top face50A of each of the first power conductors51A and51B has the same length in the x-direction, as the top face50A of the first output conductors52A and52B, and the top face50A of the first ground conductor53. On the other hand, a portion of the top face50A of each of the first power conductors51A and51B, on the side of the center of the substrate10in the x-direction, is formed in a tapered shape so as to be narrower toward the center of the substrate10in the x-direction. Accordingly, the top face50A of each of the first power conductors51A and51B is smaller in area, than the top face50A of the first output conductors52A and52B, and the top face50A of the first ground conductor53.

Though not shown, the first power conductors51A and51B have the same thickness as the first output conductors52A and52B, and the first ground conductor53. Accordingly, the first power conductors51A and51B are smaller in volume, than the first output conductors52A and52B and the first ground conductor53.

In addition, as shown inFIG.32, the top face50A of each of the second power conductors54A and54B has the same length in the x-direction, as the top face50A of the second output conductors55A and55B, and the top face50A of the second ground conductor56. On the other hand, a portion of the top face50A of each of the second power conductors54A and54B, on the side of the center of the substrate10in the x-direction, is formed in a tapered shape so as to be narrower toward the center of the substrate10in the x-direction. Accordingly, the top face50A of each of the second power conductors54A and54B is smaller in area than the top face50A of the second output conductors55A and55B, and the top face50A of the second ground conductor56.

Though not shown, the second power conductors54A and54B have the same thickness as the second output conductors55A and55B, and the second ground conductor56. Accordingly, the second power conductors54A and54B are smaller in volume than the second output conductors55A and55B and the second ground conductor56. Therefore, the same advantageous effects as (1-1) and (1-2) from the first embodiment can be attained.

In the third example, as shown inFIG.33, the top face50A of each of the first power conductors51A and51B has the same length in the x-direction, as the top face50A of the first output conductors52A and52B, and the top face50A of the first ground conductor53. On the other hand, a portion of the top face50A of each of the first power conductors51A and51B, on the side of the center of the substrate10in the x-direction, is formed in a stepped shape, such that the length of the top face50A in the y-direction is reduced. Accordingly, the top face50A of each of the first power conductors51A and51B is smaller in area, than the top face50A of the first output conductors52A and52B, and the top face50A of the first ground conductor53.

Though not shown, the first power conductors51A and51B have the same thickness as the first output conductors52A and52B, and the first ground conductor53. Accordingly, the first power conductors51A and51B are smaller in volume, than the first output conductors52A and52B and the first ground conductor53.

In addition, as shown inFIG.33, the top face50A of each of the second power conductors54A and54B has the same length in the x-direction, as the top face50A of the second output conductors55A and55B, and the top face50A of the second ground conductor56. On the other hand, a portion of the top face50A of each of the second power conductors54A and54B, on the side of the center of the substrate10in the x-direction, is formed in a stepped shape, such that the length of the top face50A in the y-direction is reduced. Accordingly, the top face50A of each of the second power conductors54A and55B is smaller in area than the top face50A of the second output conductors55A and55B, and the top face50A of the second ground conductor56.

Though not shown, the second power conductors54A and54B have the same thickness as the second output conductors55A and55B, and the second ground conductor56. Accordingly, the second power conductors54A and54B are smaller in volume than the second output conductors55A and55B and the second ground conductor56. Therefore, the same advantageous effects as (1-1) from the first embodiment can be attained.

Here, in the first to the third examples shown inFIG.31toFIG.33, the length of the top face50A of the first power conductors51A and51B in the x-direction may be changed as desired. For example, the top face50A of the first power conductors51A and51B may be shorter in the x-direction, than the top face50A of the first output conductors52A and52B and the top face50A of the first ground conductor53. In addition, provided that the top face50A of the first power conductors51A and51B becomes smaller in area than the top face50A of the first output conductors52A and52B and the top face50A of the first ground conductor53, the top face50A of the first power conductors51A and51B may be longer in the x-direction, than the top face50A of the first output conductors52A and52B and the top face50A of the first ground conductor53.

Likewise, the length of the top face50A of the second power conductors54A and54B in the x-direction may be changed as desired. For example, the top face50A of the second power conductors54A and54B may be shorter in the x-direction, than the top face50A of the second output conductors55A and55B and the top face50A of the second ground conductor56. In addition, provided that the top face50A of the second power conductors54A and54B becomes smaller in area than the top face50A of the second output conductors55A and55B and the top face50A of the second ground conductor56, the top face50A of the second power conductors54A and54B may be longer in the x-direction, than the top face50A of the second output conductors55A and55B and the top face50A of the second ground conductor56.

In the fourth example, as shown inFIG.34, the top face50A of each of the first power conductors51A and51B is shorter in the x-direction, than the top face50A of the first ground conductor53. In the illustrated example, the top face50A of each of the first output conductors52A and528is longer in the x-direction, than the top face50A of the first power conductors51A and51B. In other words, the top face50A of the first power conductors51A and51B is shorter in the x-direction, than the top face50A of the first output conductors52A and52B. Accordingly, the top face50A of each of the first output conductors52A and52B is smaller in area than the top face50A of the first ground conductor53, and larger in area than the top face50A of the first power conductors51A and51B. In other words, the top face50A of the first power conductors51A and51B is smaller in area than the top face50A of the first output conductors52A and52B, and the top face50A of the first ground conductor53.

Though not shown, the first output conductors52A and528each have the same thickness as the first power conductors51A and51B, and the first ground conductor53. Accordingly, the first output conductors52A and52B are smaller in volume than the first ground conductor53, and larger in volume than the first power conductors51A and51B. In other words, the first power conductors51A and51B are each smaller in volume than the first output conductors52A and52B and the first ground conductor53.

In addition, as shown inFIG.34, the top face50A of each of the second output conductors55A and55B is shorter in the x-direction, than the top face50A of the second ground conductor56. In the illustrated example, the top face50A of each of the second output conductors55A and55B is longer in the x-direction, than the top face50A of the second power conductors54A and54B. In other words, the top face50A of the second power conductors54A and54B is shorter in the x-direction, than the top face50A of the second output conductors55A and55B. Accordingly, the top face50A of each of the second output conductors55A and55B is smaller in area than the top face50A of the second ground conductor56, and larger in area than the top face50A of the second power conductors54A and54B. In other words, the top face50A of the second power conductors54A and54B is smaller in area than the top face50A of the second output conductors55A and55B, and the top face50A of the second ground conductor56.

Though not shown, the second output conductors55A and55B each have the same thickness as the second power conductors54A and54B, and the second ground conductor56. Accordingly, the second output conductors55A and55B are smaller in volume than the first ground conductor53, and larger in volume than the second power conductors54A and54B. In other words, the second power conductors54A and54B are each smaller in volume than the second output conductors55A and55B and the second ground conductor56. Therefore, the same advantageous effects as (1-1) and (1-2) from the first embodiment can be attained.

In the fifth example, as shown inFIG.35, the top face50A of the first ground conductor53is shorter in the x-direction, than the top face50A of the first output conductors52A and523. In the illustrated example, the top face50A of the first ground conductor53is longer in the x-direction, than the top face50A of the first power conductors51A and51B. Accordingly, the top face50A of the first ground conductor53is smaller in area than the top face50A of the first output conductors52A and52B, and larger in area than the top face50A of the first power conductors51A and51D. In other words, the top face50A of the first power conductors51A and51B is smaller in area than the top face50A of the first output conductors52A and52B, and the top face50A of the first ground conductor53.

Though not shown, the first ground conductor53has the same thickness as the first power conductors51A and51B, and the first output conductors52A and52B. Accordingly, the first ground conductor53is smaller in volume than the first output conductors52A and528, and larger in volume than the first power conductors51A and513. In other words, the first power conductors51A and51B are smaller in volume than the first output conductors52A and52B and the first ground conductor53.

In addition, as shown inFIG.35, the top face50A of the second ground conductor56is shorter in the x-direction, than the top face50A of the second output conductors55A and55B. In the illustrated example, the top face50A of the second ground conductor56is longer in the x-direction, than the top face50A of the second power conductors54A and54B. Accordingly, the top face50A of the second ground conductor56is smaller in area than the top face50A of the second output conductors55A and55B, and larger in area than the top face50A of the second power conductors54A and54B. In other words, the top face50A of the second power conductors54A and54B is smaller in area than the top face50A of the second output conductors55A and55B, and the top face50A of the second ground conductor56.

Though not shown, the second ground conductor56has the same thickness as the second power conductors54A and54B, and the second output conductors55A and55B. Accordingly, the second ground conductor56is smaller in volume than the second output conductors55A and55B, and larger in volume than the second power conductors54A and54B. In other words, the second power conductors54A and54B are smaller in volume than the second output conductors55A and55B and the second ground conductor56. Therefore, the same advantageous effects as (1-1) and (1-2) from the first embodiment can be attained. Here, the modifications illustrated inFIG.31toFIG.35may be applied to the plurality of conductors50X of the semiconductor device10according to the second embodiment.

In the manufacturing method of the semiconductor devices1A and1B according to the respective embodiments, the plurality of conductors850are formed in the same thickness as one another. However, a different process may be adopted. For example, as shown inFIG.36, among the plurality of conductors850, the first power conductors851A and851B may be thinner than the first output conductors852A and852B and the first ground conductor853. In this case, in the process of removing the resin layer830in the thickness direction, the resin layer830is removed so as to make the thickness of the first power conductors851A and851B, the first output conductors852A and852B, and the first ground conductor853the same as one another.

With such an arrangement, the same advantageous effects as (1-1) from the first embodiment can be attained. Though not shown, the second power conductor may be thinner than the second output conductor and the second ground conductor.

Although the plurality of conductors50are exposed from the sealing resin30in the z-direction in the foregoing embodiments, a different configuration may be adopted. For example, the plurality of conductors50may be exposed in the z-direction, from the substrate supporting the semiconductor element60.

In an example, as shown inFIG.37andFIG.38, a semiconductor device1C includes a substrate210, the plurality of terminals20, a sealing resin230, the plurality of wirings40, the plurality of conductors50, and the semiconductor element60.

The substrate210is a support member that serves as the base for the semiconductor device1C, and formed of an electrically insulative material. Examples of such a material include a synthetic resin predominantly composed of an epoxy resin, ceramics, and glass. In the illustrated example, the substrate210is formed of a synthetic resin predominantly composed of an epoxy resin. The substrate210includes a substrate obverse face211and a substrate reverse face212, oriented to opposite sides to each other in the z-direction. Here, the z-direction may also be referred to as thickness direction of the substrate210. As viewed in the z-direction, the substrate10has a rectangular shape with the long sides extending in the x-direction, and the short sides extending in the y-direction.

The plurality of wirings40are formed on the substrate obverse face211. The plurality of wirings40include, as in the first embodiment, the first power wirings41A and41B, the first output wirings42A and42B, the first ground wiring43, the second power wirings44A and44B, the second output wirings45A and45B, the second ground wiring46, and the plurality of control wirings47. The respective shapes of the plurality of wirings40viewed in the z-direction are the same as those of the plurality of wirings40of the first embodiment. The plurality of wirings40each extend, as in the first embodiment, from inside the semiconductor element60to outside of the semiconductor element60.

As shown inFIG.38, the semiconductor element60is located on the opposite side of the substrate210with respect to the plurality of wirings40in the z-direction, and bonded to the plurality of wirings40via the solder layer48.

The plurality of conductors50are located on the opposite side of the semiconductor element60with respect to the plurality of wirings40, in the z-direction. The plurality of conductors50are formed so as to penetrate through the substrate210in the z-direction. Accordingly, the plurality of conductors50are exposed in each of the substrate obverse face211and the substrate reverse face212. The plurality of conductors50exposed in the substrate obverse face211are respectively bonded to the plurality of wirings40. In other words, the plurality of conductors50are electrically connected to the respective wirings40. As shown inFIG.37, as viewed in the z-direction, the plurality of conductors50are located in the region outside the semiconductor element60, so as to surround the semiconductor element60.

The plurality of conductors50include, as in the first embodiment, the first power conductors51A and51B, the first output conductors52A and52B, the first ground conductor53, the second power conductors54A and54B, the second output conductors55A and55B, the second ground conductor56, and the plurality of control conductor57.

As shown inFIG.37, the arrangement of the plurality of conductors50and the plurality of terminals20, viewed in the z-direction from the substrate reverse face212, is similar to that of the plurality of conductors50and the plurality of terminals20according to the first embodiment, for example shown inFIG.3. The plurality of conductors50each include the top face50A, exposed from the substrate reverse face212.

To be more detailed, the top face50A of each of the first power conductors51A and51B is shorter in the x-direction, than the top face50A of the first output conductors52A and52B and the top face50A of the first ground conductor53. The top face50A of each of the first power conductors51A and51B has the same length in the y-direction, as the top face50A of the first output conductors52A and52B and the top face50A of the first ground conductor53. Accordingly, the top face50A of each of the first power conductors51A and51B is smaller in area, than the top face50A of the first output conductors52A and52B and the top face50A of the first ground conductor53. Here, when the difference in length in the y-direction between the top face50A of the first power conductors51A and51B and the top face50A of the first output conductors52A and52B is, for example, within 5% of the length in the y-direction of the top face50A of the first output conductors52A and52B, the length in the y-direction of the top face50A of the first power conductors51A and51B may be regarded as being equal to that of the top face50A of the first output conductors52A and52B. Likewise, when the difference in length in the y-direction between the top face50A of the first power conductors51A and51B and the top face50A of the first ground conductor53is, for example, within 5% of the length in the y-direction of the top face50A of the first ground conductor53, the length in the y-direction of the top face50A of the first power conductors51A and51B may be regarded as being equal to that of the top face50A of the first ground conductor53.

In addition, since the first power conductors51A and51B, the first output conductors52A and52B, and the first ground conductor53have the same thickness as one another, the first power conductors51A and51B are smaller in volume than the first output conductors52A and52B and the first ground conductor53.

Likewise, the top face50A of each of the second power conductors54A and54B is shorter in the x-direction, than the top face50A of the second output conductors55A and55B and the top face50A of the second ground conductor56. The top face50A of each of the second power conductors54A and54B has the same length in the y-direction, as the top face50A of the second output conductors55A and55B and the top face50A of the second ground conductor56. Accordingly, the top face50A of each of the second power conductors54A and54B is smaller in area, than the top face50A of the second output conductors55A and55B and the top face50A of the second ground conductor56. Here, when the difference in length in the y-direction between the top face50A of the second power conductors54A and54B and the top face50A of the second output conductors55A and55B is, for example, within 5% of the length in the y-direction of the top face50A of the second output conductors55A and55B, the length in the y-direction of the top face50A of the second power conductors54A and54B may be regarded as being equal to that of the top face50A of the second output conductors55A and55B. Likewise, when the difference in length in the y-direction between the top face50A of the second power conductors54A and54B and the top face50A of the second ground conductor56is, for example, within 5% of the length in the y-direction of the top face50A of the second ground conductor56, the length in the y-direction of the top face50A of the second power conductors54A and54B may be regarded as being equal to that of the top face50A of the second ground conductor56.

In addition, since the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56have the same thickness as one another, the second power conductors54A and54B are smaller in volume than the second output conductors55A and559and the second ground conductor56.

Hereunder, a manufacturing method of the semiconductor device1C will be described, with reference toFIG.39toFIG.46. Referring toFIG.39, the manufacturing method of the semiconductor device1C includes a process of preparing a support substrate900. The support substrate900is, for example, formed of an intrinsic monocrystalline material of Si. The support substrate900includes an upper face901and a lower face902oriented to opposite sides to each other in the z-direction.

Referring toFIG.39, the manufacturing method of the semiconductor device1C includes a process of forming a terminal pillar950. To be more detailed, a plurality of terminal pillars950are formed on the upper face901of the support substrate900. The terminal pillars950are, for example, formed of Cu or a Cu-based alloy, and formed through an electrolytic plating process.

To be more detailed, the terminal pillars950are formed through a process of forming a seed layer, a process of forming a mask on the seed layer by photolithography, and a process of forming the terminal pillars950in contact with the seed layer. The seed layer is formed on the upper face901of the support substrate900, for example by a sputtering method. Then the seed layer is covered with a photosensitive resist layer, and the resist layer is exposed and developed, to form a mask having openings. Then the electrolytic plating is performed using the seed layer as the conduction path, to thereby precipitate the plated metal on the surface of the seed layer exposed from the mask, thus forming the terminal pillars950. After the formation of the terminal pillars950, the mask is removed. Here, a Cu columnar material may be employed to form the terminal pillars950. The plurality of terminal pillars950have the same thickness as one another.

Though not shown, the plurality of terminal pillars950are to be formed into the plurality of conductors50. Accordingly, the terminal pillars950to be formed into the first power conductors51A and51B are smaller in volume, than the terminal pillars950to be formed into the first output conductors52A and52B, and the terminal pillars950to be formed into the first ground conductor53. To be more detailed, as viewed in the z-direction, the plurality of terminal pillars950to be formed into the first power conductors51A and51B, the first output conductors52A and528, and the first ground conductor53each have a rectangular shape with the long sides extending in the x-direction, and short sides extending in the y-direction. The terminal pillars950to be formed into the first power conductors51A and51B are shorter in the x-direction, than the terminal pillars950to be formed into the first output conductors52A and520, and the terminal pillars950to be formed into the first ground conductor53. The terminal pillars950to be formed into the first power conductors51A and51B have the same length in the y-direction, as the terminal pillars950to be formed into the first output conductors52A and52B, and the terminal pillars950to be formed into the first ground conductor53.

Referring toFIG.40, the manufacturing method of the semiconductor device1C includes a process of forming a base material910. The base material910is formed so as to cover the upper face of the terminal pillar950. To form the base material910, the material to form the substrate210shown inFIG.38may be employed. In the illustrated example, a synthetic resin material predominantly composed of an epoxy resin is employed as the material for the base material910.

Referring toFIG.41, a part of each of the base material910and the terminal pillar950in the z-direction is ground, to form the plurality of conductors50exposed in the upper face911of the base material910. The base material910is ground so as to make the thickness of the base material910equal to that of the substrate210.

Referring toFIG.42, the plurality of wirings40are formed on the upper face911of the base material910, and the upper face of the plurality of conductors50exposed in the upper face911. The plurality of wirings40are formed on the respective conductors50. To be more detailed, the plurality of wirings40are formed through a process of forming a metal layer, a process of forming a mask on the metal layer by photolithography, and a process of forming a conductive layer in contact with the metal layer.

First, the metal layer is formed, for example by a sputtering method. For example, a Ti layer is formed on the upper face911of the base material910and the upper face of the plurality of conductors50, and a Cu layer is formed in contact with the Ti layer. Then the metal layer is covered with a photosensitive resist layer, and the resist layer is exposed and developed, to form a mask having openings. Then the electrolytic plating is performed using the metal layer as the conduction path, to thereby precipitate the plated metal on the upper face of the metal layer exposed from the mask, thus to be engaged with the conductive layer. The plurality of wirings40can be formed through the mentioned process. After the formation of the plurality of wirings40, the mask is removed.

Referring toFIG.43, the manufacturing method of the semiconductor device1C includes a process of mounting the semiconductor element60. The process of mounting the semiconductor element60is the same as the process of mounting the semiconductor element60according to the first embodiment.

Referring toFIG.44, the manufacturing method of the semiconductor device1C includes a process of forming a resin layer930. The resin layer930is to be formed into the sealing resin230shown inFIG.38. The resin layer930is, for example, formed of a synthetic resin predominantly composed of an epoxy resin. The resin layer930can be formed, for example, by a transfer molding method. Here, although one resin layer930is formed to cover one semiconductor element60in the illustrated example, the resin layer930may be formed so as to cover all of the semiconductor elements60.

Referring toFIG.45, the manufacturing method of the semiconductor device1C includes a process of removing the support substrate900shown inFIG.44. Here,FIG.45is turned upside down formFIG.44. The support substrate900can be removed, for example by grinding.

Referring toFIG.45, the manufacturing method of the semiconductor device1C includes a process of forming the plurality of terminals20. The plurality of terminals20are formed of plated metals. The plated metals, such as Ni, Pd, and Au may be precipitated in this order, for example through a non-electrolytic plating process, so that the plurality of terminals20are formed.

Referring toFIG.46, the manufacturing method of the semiconductor device1C includes a process of forming the individual pieces of the semiconductor device1C. To be more detailed, a dicing tape DT is stuck to the lower face of the resin layer930. Then the base material910and the resin layer930are cut in this order, for example by a dicing blade, along the cutting lines CL indicated by broken lines. Through the foregoing process, the semiconductor device1C can be obtained.

Here, although the plurality of terminals20, the plurality of wirings40, and the plurality of conductors50of the semiconductor device1C are configured in the same way as those of the first embodiment as shown inFIG.37andFIG.38, the plurality of terminals20, the plurality of wirings40, and the plurality of conductors50may be formed in the same way as the plurality of terminals20X, the plurality of wirings40X, and the plurality of conductors50X of the second embodiment. In other words, the semiconductor device1C may include the first power wiring41, the first output wiring42, the first ground wiring43, the second power wiring44, the second output wiring45, the second ground wiring46, and the plurality of control wirings47. The semiconductor device1C may include the first power conductor51, the first output conductor52, the first ground conductor53, the second power conductor54, the second output conductor55, the second ground conductor56, and the plurality of control conductors57. The semiconductor device1C may include the first power terminal21, the first output terminal22, the first ground terminal23, the second power terminal24, the second output terminal25, the second ground terminal26, and the plurality of control terminals27.

Although the first power conductors51A and510are smaller in volume than the first output conductors52A and52B and the first ground conductor53, in the first embodiment, a different configuration may be adopted. For example, the first output conductors52A and52B may be made smaller in volume than the first power conductors51A and51B and the first ground conductor53, or the first ground conductor53may be made smaller in volume than the first power conductors51A and51B and the first output conductors52A and52B. The above also applies to the second power conductors54A and54B, the second output conductors55A and55, and the second ground conductor56.

In addition, the type of the conductor to be made smaller in volume is not limited to one, but two types of the conductors may be made smaller in volume. For example, the first power conductors51A and51B and the first output conductors52A and52B may be made smaller in volume than the first ground conductor53. The first power conductors51A and51B and the first ground conductor53may be made smaller in volume than the first output conductors52A and52B. The first output conductors52A and52B and the first ground conductor53may be made smaller in volume than the first power conductors51A and51B. The above also applies to the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56. Further, the configuration in which the conductors are made smaller in volume may be applied to one of the configurations according to the foregoing embodiments and the variations thereof.

Although the same type of conductors are made smaller in volume in the first embodiment, such that the first power conductors51A and51B are smaller in volume than the first output conductors52A and528and the first ground conductor53, a different configuration may be adopted. For example, different types of conductors may be made smaller in volume. More specifically, one to four conductors, optionally selected out of the five conductors namely the first power conductors51A and51B, the first output conductors52A and52B, and the first ground conductor53, may be made smaller in volume than the remaining conductors. For example, the first power conductor51A and the first output conductor52A may be made smaller in volume than the first power conductor51B, the first output conductor52B, and the first ground conductor53. The above also applies to the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56. Further, the configuration in which the conductors are made smaller in volume may be applied to one of the configurations according to the foregoing embodiments and the variations thereof.

Although the same type of conductors, located close to the substrate side face13and the substrate side face14respectively, are made smaller in volume in the first embodiment, such that the first power conductors51A and51B and the second power conductors54A and54B are each made smaller in volume, a different configuration may be adopted. Different types of conductors, out of those located close to the substrate side face13and close to the substrate side face14, may be made smaller in volume. In other words, the type of the conductor made smaller in volume, out of the first power conductors51A and51B, the first output conductors52A and528, and the first ground conductor53, and the type of the conductor made smaller in volume, out of the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56, may be different from each other. For example, the first power conductors51A and51B may be made smaller in volume than the first output conductors52A and52B and the first ground conductor53, and the second output conductors55A and55B may be smaller in volume than the second power conductors54A and54B and the second ground conductor56. Here, the configuration in which the conductors are made smaller in volume may be applied to one of the configurations according to the foregoing embodiments and the variations thereof.

Although the first power conductor51is smaller in volume than the first output conductor52and the first ground conductor53in the second embodiment, a different configuration may be adopted. For example, the first output conductor52may be made smaller in volume than the first power conductor51and the first ground conductor53, or the first ground conductor53may be made smaller in volume than the first power conductor51and the first output conductor52.

The type of the conductor to be made smaller in volume is not limited to one, but two types of the conductors may be made smaller in volume. For example, the first power conductor51and the first output conductor52may be made smaller in volume than the first ground conductor53. The first power conductor51and the first ground conductor53may be made smaller in volume than the first output conductor52. The first output conductor52and the first ground conductor53may be made smaller in volume than the first power conductor51. The above also applies to the second power conductor54, the second output conductor55, and the second ground conductor56. Further, the configuration in which the conductors are made smaller in volume may be applied to one of the configurations according to the foregoing embodiments and the variations thereof.

Although the same type of conductors, located close to the substrate side face13and the substrate side face14respectively, are made smaller in volume in the first embodiment, such that the first power conductor51and the second power conductor54are each made smaller in volume, a different configuration may be adopted. Different types of conductors, out of those located close to the substrate side face13and close to the substrate side face14, may be made smaller in volume. In other words, the type of the conductor made smaller in volume, out of the first power conductor51, the first output conductor52, and the first ground conductor53, and the type of the conductor made smaller in volume, out of the second power conductor54, the second output conductor55, and the second ground conductor56, may be different from each other. For example, the first power conductor51may be made smaller in volume than the first output conductor52and the first ground conductor53, and the second output conductor55may be made smaller in volume than the second power conductor54and the second ground conductor56. Here, the configuration in which the conductors are made smaller in volume may be applied to one of the configurations according to the foregoing embodiments and the variations thereof.

In the first embodiment, the arrangement pattern of the first power wirings41A and41B, the first output wirings42A and42B, and the first ground wiring43in the y-direction may be modified as desired. For example, the first power wirings41A and41B may be separately located on the respective sides of the first ground wiring43located at the center of the substrate10in the y-direction, the first output wiring42A may be located on the opposite side of the first ground wiring43in the y-direction with respect to the first power wiring41A, and the first output wiring42B may be located on the opposite side of the first ground wiring43in the y-direction with respect to the first power wiring41B. Because of such modification, the arrangement pattern of the first power conductors51A and51B, the first output conductors52A and52B, and the first ground conductor53in the y-direction is also modified.

Likewise, the arrangement pattern of the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46in the y-direction may be modified as desired. For example, the second power wirings44A and44B may be separately located on the respective sides of the second ground wiring46located at the center of the substrate10in the y-direction, the second output wiring45A may be located on the opposite side of the second ground wiring46in the y-direction with respect to the second power wiring44A, and the second output wiring45B may be located on the opposite side of the second ground wiring46in the y-direction with respect to the second power wiring44B. Because of such modification, the arrangement pattern of the second power conductors54A and54B, second output conductors55A and55B, and the second ground conductor56in the y-direction is also modified. Here, the arrangement pattern of the second power wirings44A and44B, the second output wirings45A and45B, and the second ground wiring46in the y-direction may be different from that of the first power wirings41A and41B, the first output wirings42A and428, and the first ground wiring43.

In the foregoing embodiments, the control conductors57include the distal control conductors57C, the central control conductor57D, and the intermediate control conductors57E, which are different in area of the top face50A. However, a different configuration may be adopted. For example, the control conductors57may include the distal control conductors57C and the intermediate control conductors57E. In other words, the central control conductor57D may be substituted with the intermediate control conductor57E. Alternatively, the control conductors57may only include the intermediate control conductors57E. In other words, the distal control conductors57C and the central control conductor57D may each be substituted with the intermediate control conductor57E.

In the foregoing embodiments, the length in the x-direction and the y-direction, of the top face50A of each of the four distal control conductors57C may be changed as desired. For example, the top face50A of the distal control conductor57C may be longer or shorter in the x-direction, than the top face50A of the first power conductors51A and51B and the top face50A of the second power conductors54A and54B. The top face50A of the distal control conductor57C may have the same length in the y-direction, as the top face50A of the first power conductors51A and51B and the top face50A of the second power conductors54A and54B. Further, the top face50A of the distal control conductor57C may be shorter in the y-direction, than the length in the x-direction of the top face50A of the first power conductors51A and51B, and the length in the x-direction of the top face50A of the second power conductors54A and54B.

In the foregoing embodiments, the length in the x-direction and the y-direction, of the top face50A of each of the plurality of intermediate control conductors57E may be changed as desired. For example, the top face50A of the intermediate control conductor57E may have the same length in the x-direction, as the top face50A of the first power conductors51A and51B, and the top face50A of the second power conductors54A and54B. The top face50A of the intermediate control conductor57E may be longer in the x-direction, than the top face50A of the first power conductors51A and51B, and the top face50A of the second power conductors54A and54B. The top face50A of the intermediate control conductor578may be longer or shorter in the y-direction, than the top face50A of the first power conductors51A and51B, and the top face50A of the second power conductors54A and54B.

In the foregoing embodiments, the length in the x-direction and the y-direction of the central control conductor57D may be changed as desired. For example, the central control conductor57D may have the same length in the x-direction, as the top face50A of the first power conductors51A and51B, and the top face50A of the second power conductors54A and54B. The top face50A of the central control conductor57D may be shorter in the x-direction, than the top face50A of the first power conductors51A and51B, and the top face50A of the second power conductors54A and54B. The top face50A of the central control conductor57D may be longer or shorter in the y-direction, than the top face50A of the first power conductors51A and51B, and the top face50A of the second power conductors54A and54B.

In the foregoing embodiments, at least one of the top face50A of the first power conductors51A and51B and the top face50A of the second power conductors54A and54B may have the same area as the top face50A of the control conductor57. Alternatively, at least one of the top face50A of the first power conductors51A and51B and the top face50A of the second power conductors54A and54B may have the same area as the top face50A of the intermediate control conductor57E, among the control conductors57.

In the foregoing embodiments, at least one of the first power conductors51A and51B and the second power conductors54A and54B may have the same volume as the control conductor57. Alternatively, at least one of the first power conductors51A and51B and the second power conductors54A and54B may have the same volume as the intermediate control conductor578, among the control conductors57.

In the foregoing embodiments, the position of the first power conductors51A and51B, with respect to the first output conductors52A and523and the first ground conductor53in the x-direction, may be changed as desired. The position of the second power conductors54A and54B, with respect to the second output conductors55A and55B and the second ground conductor56in the x-direction, may be changed as desired. For example, the respective positions of the first power conductors51A and51B and the second power conductors54A and54B in the x-direction may be shifted, as a first example shown inFIG.47, and a second example shown inFIG.48.

As shown inFIG.47andFIG.48, one of the edges of the top face50A of the first power conductors51A and51B in the x-direction, on the side of the resin side face32, will be defined as edge51a, and the other edge on the opposite side of the resin side face32will be defined as edge51b. One of the edges of the top face50A of the first output conductors52A and528in the x-direction, on the side of the resin side face32, will be defined as edge52a, and the other edge on the opposite side of the resin side face32will be defined as edge52b. One of the edges of the top face50A of the first ground conductor53in the x-direction, on the side of the resin side face32, will be defined as edge53a, and the other edge on the opposite side of the resin side face32will be defined as edge53b. One of the edges of the top face50A of the second power conductors54A and54B in the x-direction, on the side of the resin side face33, will be defined as edge54a, and the other edge on the opposite side of the resin side face33will be defined as edge54b. One of the edges of the top face50A of the second output conductors55A and55B in the x-direction, on the side of the resin side face33, will be defined as edge55a, and the other edge on the opposite side of the resin side face33will be defined as edge55b. One of the edges of the top face50A of the second ground conductor56in the x-direction, on the side of the resin side face33, will be defined as edge56a, and the other edge on the opposite side of the resin side face33will be defined as edge56b.

In the first example, as shown inFIG.47, the edge51bof the first power conductors51A and51B is aligned with the edge52bof the first output conductors52A and52B and the edge53bof the first ground conductor53, in the x-direction. The edge54bof the second power conductors54A and54B is aligned with the edge55bof the second output conductors55A and55B and the edge56bof the second ground conductor56, in the x-direction.

In the second example, as shown inFIG.48, the edge51bof the first power conductors51A and51B is located closer to the substrate side face13in the x-direction, than are the edge52bof the first output conductors52A and52B and the edge53bof the first ground conductor53. In addition, the edge51aof the first power conductors51A and51B is located farther from the substrate side face13in the x-direction, than are the edge52aof the first output conductors52A and528and the edge53aof the first ground conductor53. More specifically, the first power conductors51A and51B, the first output conductors52A and52B, and the first ground conductor53are located such that, as indicated by a dash-dot line inFIG.48, the center of the first power conductors51A and51B in the x-direction, the center of the first output conductors52A and52B in the x-direction, and the center of the first ground conductor53in the x-direction are aligned with each other in the x-direction.

Likewise, the edge54bof the second power conductors54A and54B is located closer to the substrate side face14in the x-direction, than are the edge55bof the second output conductors55A and55B and the edge56bof the second ground conductor56. In addition, the edge54aof the second power conductors54A and54B is located farther from the substrate side face14in the x-direction, than are the edge55aof the second output conductors55A and55B and the edge56aof the second ground conductor56. More specifically, the second power conductors54A and543, the second output conductors55A and55B, and the second ground conductor56are located such that, as indicated by a dash-dot line inFIG.48, the center of the second power conductors54A and54B in the x-direction, the center of the second output conductors55A and55B in the x-direction, and the center of the second ground conductor56in the x-direction are aligned with each other in the x-direction.

The position of the first power conductors51A and51B in the x-direction and the position of the second power conductors54A and54B in the x-direction are changed as shown inFIG.47andFIG.48, by reducing the volume of the first power conductors51A and51B and the second power conductors54A and54B. However, a different arrangement may be adopted. The position in the x-direction of any of the first power conductors51A and51B, the first output conductors52A and52B, and the first ground conductor53, the volume of which is reduced by reducing the length of the top face50A in the x-direction, may be changed. Likewise, the position in the x-direction of any of the second power conductors54A and54B, the second output conductors55A and55B, and the second ground conductor56, the volume of which is reduced by reducing the length of the top face50A in the x-direction, may be changed. The above also applies to the first power conductor51, the first output conductor52, the first ground conductor53, the second power conductor54, the second output conductor55, and the second ground conductor56according to the second embodiment.

The technical ideas that can be perceived from the embodiments of the first aspect and the variations thereof will be described in the following clauses.

A manufacturing method of a semiconductor device, the method including:a wiring formation process including forming wirings including a first drive wiring and a second drive wiring, on a base material obverse face of a base material having the base material obverse face and a base material reverse face, oriented to opposite sides to each other in a thickness direction;a conductor formation process including forming a first drive conductor on the first drive wiring, and forming a second drive conductor on the second drive wiring;an element mounting process including mounting a semiconductor element on the first drive wiring and the second drive wiring; anda resin layer formation process including forming a resin layer covering the wiring, the semiconductor element, the first drive conductor, and the second drive conductor,in which the conductor formation process includes forming the first drive conductor so as to make the first drive conductor smaller in volume than the second drive conductor.

In the mentioned manufacturing method, the first drive conductor is made smaller in volume than the second drive conductor. Such a configuration can minimize the warp of the base material constituting the substrates, despite being heated during the resin layer formation process. Consequently, the semiconductor device can be stably manufactured.

The method according to Clause A1, further including a resin layer processing process including reducing a thickness of the resin layer, and processing the resin layer so as to expose an end face of the first drive conductor in the thickness direction, and an end face of the second drive conductor in the thickness direction, from the resin layer.

A manufacturing method of a semiconductor device, the method including:a wiring formation process including forming a wiring including a first drive wiring and a second drive wiring, on a base material obverse face of a base material having a base material obverse face and the base material reverse face, oriented to opposite sides to each other in a thickness direction;a conductor formation process including forming a first drive conductor on the first drive wiring, and forming a second drive conductor on the second drive wiring;an element mounting process including mounting a semiconductor element on the first drive wiring and the second drive wiring;a resin layer formation process including forming a resin layer covering the wiring, the semiconductor element, the first drive conductor, and the second drive conductor; anda resin layer processing process including reducing a thickness of the resin layer, a thickness of the first drive conductor, and a thickness of the second drive conductor,in which the conductor formation process includes forming the first drive conductor so as to make the first drive conductor smaller in volume than the second drive conductor.the conductor formation process making the first drive conductor thinner than the second drive conductor, and the resin layer processing process includes making the thickness of the first drive conductor and the second drive conductor equal to each other.

In the mentioned manufacturing method, the first drive conductor is made smaller in volume than the second drive conductor, in the process preceding the resin layer formation process. Such a configuration can minimize the warp of the base material, despite being heated during the resin layer formation process. Consequently, the semiconductor device can be stably manufactured.

A manufacturing method of a semiconductor device, the method including:a terminal pillar formation process including forming a plurality of terminal pillars, on a base material obverse face of a base material having the base material obverse face and a base material reverse face, oriented to opposite sides to each other in a thickness direction;a substrate formation process including forming a substrate by molding with an electrically insulative resin so as to insulate between the plurality of terminal pillars;a wiring formation process including forming a plurality of wirings electrically connected to the terminal pillars, on one of faces of the substrate in the thickness direction; andan element mounting process including mounting a semiconductor element on the plurality of wirings,in which the plurality of terminal pillars include a first drive terminal pillar and a second drive terminal pillar in which a driving current for the semiconductor element flows, and the terminal pillar formation process includes making the first drive terminal pillar smaller in volume than the second drive terminal pillar.

In the mentioned manufacturing method, the first drive terminal pillar is made smaller in volume than the second drive terminal pillar. Such a configuration can minimize the warp of the base material constituting the substrates, despite being heated during the molding operation in the substrate formation process. Consequently, the semiconductor device can be stably manufactured.

The method according to Clause C1, further including a substrate processing process including reducing a thickness of the substrate, and processing the substrate so as to expose respective end faces of the plurality of terminal pillars in the thickness direction from the substrate.

A semiconductor device including:a substrate having a substrate obverse face and a substrate reverse face, oriented to opposite sides to each other in a thickness direction;wirings located on the substrate obverse face, and including a first drive wiring and a second drive wiring;a semiconductor element electrically connected to the first drive wiring and the second drive wiring;a first drive conductor located on a same side as the semiconductor element with respect to the substrate, in a region on an outer side of the semiconductor element as viewed in the thickness direction, and electrically connected to the first drive wiring;a second drive conductor located on the same side as the semiconductor element with respect to the substrate, in a region on an outer side of the semiconductor element as viewed in the thickness direction, and electrically connected to the second drive wiring; anda sealing resin covering the wirings and the semiconductor element, and covering the first drive conductor and the second drive conductor such that respective faces of the first drive conductor and the second drive conductor, on an opposite side of the substrate in the thickness direction, are exposed,in which the first drive conductor and the second drive conductor are aligned, with a spacing between each other, in a predetermined direction along the substrate obverse face, andthe first drive conductor is smaller in volume than the second drive conductor.

The semiconductor device according to Clause D1,in which the first drive conductor and the second drive conductor each include a top face exposed from a side of the sealing resin opposite to the substrate in the thickness direction, andthe top face of the first drive conductor is smaller in area than the top face of the second drive conductor.

The semiconductor device according to Clause D2,in which, when an alignment direction of the first drive conductor and the second drive conductor is defined as a first direction, and a direction orthogonal to the thickness direction and the first direction is defined as a second direction,the respective top faces of the first drive conductor and the second drive conductor have a rectangular shape having short sides extending in the first direction and long sides extending in the second direction, as viewed in the thickness direction, and the top face of the first drive conductor is shorter in the second direction, than the top face of the second drive conductor.

The semiconductor device according to Clause D2,in which, when an alignment direction of the first drive conductor and the second drive conductor is defined as a first direction, and a direction orthogonal to the thickness direction and the first direction is defined as a second direction,the respective top faces of the first drive conductor and the second drive conductor have a rectangular shape having short sides extending in the first direction and long sides extending in the second direction, as viewed in the thickness direction, andthe top face of the first drive conductor is shorter in the first direction, than the top face of the second drive conductor.

The semiconductor device according to any one of appendices D1 to D4,in which the second drive conductor is located closer to a center of the substrate obverse face than is the first drive conductor, in the alignment direction of the first drive conductor and the second drive conductor.

The semiconductor device according to any one of appendices D1 to D5,in which, when an alignment direction of the first drive conductor and the second drive conductor is defined as a first direction, and a direction orthogonal to the thickness direction and the first direction is defined as a second direction,the semiconductor element includes a control circuit,a plurality of control conductors electrically connected to the control circuit are provided,the plurality of control conductors are aligned in the second direction with a spacing between each other, andthe second drive conductor is larger in volume than the control conductor.

The semiconductor device according to Clause D6,in which the first drive conductor, the second drive conductor, and the control conductor each include a top face exposed from the face of the sealing resin on the opposite side of the substrate in the thickness direction, andthe top face of the second drive conductor is larger in area than the top face of the control conductor.

The semiconductor device according to Clause D7,in which the top face of the second drive conductor has a rectangular shape having the short sides extending in the first direction and the long sides extending in the second direction, as viewed in the thickness direction,the top face of the control conductor has a rectangular shape having sides extending in the first direction and sides extending in the second direction, as viewed in the thickness direction, andthe top face of the second drive conductor is longer in the second direction, than a length of the top face of the control conductor in the first direction, and a length in the second direction.

The semiconductor device according to any one of appendices D6 to D8,in which the plurality of control conductors are located on an outer side in the first direction, with respect to the first drive conductor and the second drive conductor.

The semiconductor device according to Clause D9,in which the substrate has a rectangular shape having the sides extending in the first direction and the sides extending in the second direction, as viewed in the thickness direction,the control conductors include distal control conductors respectively located at four corners of the substrate viewed in the thickness direction, and intermediate control conductors located between two of the distal control conductors in the second direction,the distal control conductors and the intermediate control conductors each include a top face exposed from the face of the sealing resin on the opposite side of the substrate in the thickness direction, andthe top face of the distal control conductor is larger in area than the top face of the intermediate control conductor.

The semiconductor device according to Clause D10,in which the second drive conductor is larger in volume than the distal control conductor.

The semiconductor device according to Clause D11,in which the second drive conductor includes a top face exposed from the face of the sealing resin on the opposite side of the substrate in the thickness direction, andthe top face of the second drive conductor is larger in area than the top face of the distal control conductor.

The semiconductor device according to Clause D12,in which the top face of the second drive conductor has a rectangular shape having the short sides extending in the first direction and the long sides extending in the second direction, as viewed in the thickness direction,the top face of the distal control conductor has a rectangular shape having the sides extending in the first direction and the sides extending in the second direction, as viewed in the thickness direction, andthe top face of the second drive conductor is longer in the second direction, than a length of the top face of the distal control conductor in the first direction, and a length in the second direction.

The semiconductor device according to any one of appendices D6 to D9,in which a volume of the first drive conductor is equal to or larger than a volume of the control conductor.

The semiconductor device according to any one of appendices D10 to D13,in which the first drive conductor is smaller in volume than the distal control conductor.

The semiconductor device according to Clause D15,in which the first drive conductor includes a top face exposed from the face of the sealing resin on the opposite side of the substrate in the thickness direction, and the top face of the first drive conductor is smaller in area than the top face of the distal control conductor.

The semiconductor device according to Clause D16,in which the top face of the first drive conductor has a rectangular shape having the short sides extending in the first direction and the long sides extending in the second direction, as viewed in the thickness direction, andthe top face of the first drive conductor is shorter in the second direction, than at least one of the length of the top face of the distal control conductor in the first direction, and the length in the second direction.

The semiconductor device according to any one of appendices D10 to D13,in which the volume of the first drive conductor is equal to or larger than a volume of the intermediate control conductor.

The semiconductor device according to Clause D18,in which the first drive conductor includes a top face exposed from the face of the sealing resin on the opposite side of the substrate in the thickness direction, andan area of the top face of the first drive conductor is equal to or larger than an area of the top face of the intermediate control conductor.

The semiconductor device according to any one of appendices D10 to D19,in which the wiring includes a control wiring connecting the control circuit and the control conductor, andthe first drive wiring and the second drive wiring are each wider than the control wiring.

The semiconductor device according to any one of appendices D10 to D20,in which the plurality of control conductors are each located on an outer side of the semiconductor element.

A semiconductor device including:a substrate having a substrate obverse face and a substrate reverse face, oriented to opposite sides to each other in a thickness direction;wirings located on the substrate obverse face, and including a first drive wiring and a second drive wiring;a semiconductor element mounted on the substrate obverse face, and electrically connected to the first drive wiring and the second drive wiring;a first drive conductor penetrating through the substrate in the thickness direction, so as to be exposed on the substrate obverse face and the substrate reverse face, and electrically connected to the first drive wiring;a second drive conductor penetrating through the substrate in the thickness direction, so as to be exposed on the substrate obverse face and the substrate reverse face, and electrically connected to the second drive wiring; anda sealing resin covering the wirings and the semiconductor element,in which the first drive conductor and the second drive conductor are aligned, with a spacing between each other, in a predetermined direction as viewed from the substrate reverse face, andthe first drive conductor is smaller in volume than the second drive conductor.

The semiconductor device according to Clause D22,in which the first drive conductor and the second drive conductor each include a top face exposed from the substrate reverse face, andthe top face of the first drive conductor is smaller in area than the top face of the second drive conductor.

The semiconductor device according to Clause D23,in which, when an alignment direction of the first drive conductor and the second drive conductor is defined as a first direction, and a direction orthogonal to the thickness direction and the first direction is defined as a second direction,the respective top faces of the first drive conductor and the second drive conductor have a rectangular shape having short sides extending in the first direction and long sides extending in the second direction, as viewed in the thickness direction, and the top face of the first drive conductor is shorter in the second direction, than the top face of the second drive conductor.

The semiconductor device according to Clause D23,in which, when an alignment direction of the first drive conductor and the second drive conductor is defined as a first direction, and a direction orthogonal to the thickness direction and the first direction is defined as a second direction,the respective top faces of the first drive conductor and the second drive conductor have a rectangular shape having short sides extending in the first direction and long sides extending in the second direction, as viewed in the thickness direction, andthe top face of the first drive conductor is shorter in the first direction, than the top face of the second drive conductor.

The semiconductor device according to any one of appendices D22 to D25,in which the second drive conductor is located closer to a center of the substrate obverse face than is the first drive conductor, in the alignment direction of the first drive conductor and the second drive conductor.

The semiconductor device according to any one of appendices D22 to D26,in which, when an alignment direction of the first drive conductor and the second drive conductor is defined as a first direction, and a direction orthogonal to the thickness direction and the first direction is defined as a second direction,the semiconductor element includes a control circuit,a plurality of control conductors electrically connected to the control circuit are provided,the plurality of control conductors are aligned in the second direction with a spacing between each other, andthe second drive conductor is larger in volume than the control conductor.

The semiconductor device according to Clause D27,in which the first drive conductor, the second drive conductor, and the control conductor each include a top face exposed from the substrate reverse face, andthe top face of the second drive conductor is larger in area than the top face of the control conductor.

The semiconductor device according to Clause D28,in which the top face of the second drive conductor has a rectangular shape having the short sides extending in the first direction and the long sides extending in the second direction, as viewed in the thickness direction.the top face of the control conductor has a rectangular shape having sides extending in the first direction and sides extending in the second direction, andthe top face of the second drive conductor is longer in the second direction, than a length of the top face of the control conductor in the first direction, and a length in the second direction.

The semiconductor device according to any one of appendices D27 to D29,in which the plurality of control conductors are located on an outer side in the first direction, with respect to the first drive conductor and the second drive conductor.

The semiconductor device according to Clause D30.in which the substrate has a rectangular shape having the sides extending in the first direction and the sides extending in the second direction, as viewed in the thickness direction,the control conductors include distal control conductors respectively located at four corners of the substrate viewed in the thickness direction, and intermediate control conductors located between two of the distal control conductors in the second direction,the distal control conductors and the intermediate control conductors each include a top face exposed from the substrate reverse face, andthe top face of the distal control conductor is larger in area than the top face of the intermediate control conductor.

The semiconductor device according to Clause D31,in which the second drive conductor is larger in volume than the distal control conductor.

The semiconductor device according to Clause D32.in which the second drive conductor includes a top face exposed from the substrate reverse face, andthe top face of the second drive conductor is larger in area than the top face of the distal control conductor.

The semiconductor device according to Clause D33,in which the top face of the second drive conductor has a rectangular shape having the short sides extending in the first direction and the long sides extending in the second direction, as viewed in the thickness direction,the top face of the distal control conductor has a rectangular shape having the sides extending in the first direction and the sides extending in the second direction, andthe top face of the second drive conductor is longer in the second direction, than a length of the top face of the distal control conductor in the first direction, and a length in the second direction.

The semiconductor device according to any one of appendices D27 to D30,in which a volume of the first drive conductor is equal to or larger than a volume of the control conductor.

The semiconductor device according to any one of appendices D31 to D34,in which the first drive conductor is smaller in volume than the distal control conductor.

The semiconductor device according to Clause D36,in which the first drive conductor includes a top face exposed from the substrate reverse face, andthe top face of the first drive conductor is smaller in area than the top face of the distal control conductor.

The semiconductor device according to Clause D37,in which the top face of the first drive conductor has a rectangular shape having the short sides extending in the first direction and the long sides extending in the second direction, as viewed in the thickness direction, andthe top face of the first drive conductor is shorter in the second direction, than the length of the top face of the distal control conductor in the first direction.

The semiconductor device according to any one of appendices D31 to D34,in which the volume of the first drive conductor is equal to or larger than a volume of the intermediate control conductor.

The semiconductor device according to Clause D39,in which the first drive conductor includes a top face exposed from the substrate reverse face, andan area of the top face of the first drive conductor is equal to or larger than an area of the top face of the intermediate control conductor.

The semiconductor device according to any one of appendices D31 to D40,in which the wiring includes a control wiring connecting the control circuit and the control conductor, andthe first drive wiring and the second drive wiring are each wider than the control wiring.

The semiconductor device according to any one of appendices D31 to D41,in which the plurality of control conductors are each located on an outer side of the semiconductor element.

The semiconductor device according to any one of appendices D1 to D42,in which the first drive conductor is thicker than the first drive wiring, andthe second drive conductor is thicker than the second drive wiring.

The semiconductor device according to any one of appendices D1 to D43,in which the first drive wiring includes a wide wiring section which is relatively wider, and a narrow wiring section which is relatively narrower,on the wide wiring section, the first drive conductor is located, andthe narrow wiring section is located on an inner side with respect to the wide wiring section, in the direction in which the first drive wiring extends.

The semiconductor device according to Clause D44,in which the wide wiring section is wider than the length of the top face of the first drive conductor in the first direction.

The semiconductor device according to Clause D44 or D45,in which the narrow wiring section of the first drive wiring includes a widened section where a width of the narrow wiring section is increased.

The semiconductor device according to any one of appendices D1 to D46,in which the second drive wiring includes a wide wiring section which is relatively wider, and a narrow wiring section which is relatively narrower,on the wide wiring section, the second drive conductor is located, andthe narrow wiring section is located on an inner side with respect to the wide wiring section, in the direction in which the second drive wiring extends.

The semiconductor device according to Clause D47,in which the wide wiring section of the second drive wiring is wider than the length of the second drive conductor in the first direction.

The semiconductor device according to Clause D47 or D48,in which a portion of the second drive wiring connecting the wide wiring section and the narrow wiring section includes a sloped section, inclined so as to be narrower in a direction from the wide wiring section toward the narrow wiring section.

The semiconductor device according to any one of appendices D1 to D21, further including a first drive terminal and a second drive terminal,in which the first drive conductor and the second drive conductor each include a top face exposed from the face of the sealing resin on the opposite side of the substrate in the thickness direction,the first drive terminal is formed so as to cover the top face of the first drive conductor, andthe second drive terminal is formed so as to cover the top face of the second drive conductor.

The semiconductor device according to any one of appendices D22 to D42, further including a first drive terminal and a second drive terminal,in which the first drive conductor and the second drive conductor each include a top face exposed from the substrate reverse face,the first drive terminal is formed so as to cover the top face of the first drive conductor, andthe second drive terminal is formed so as to cover the top face of the second drive conductor.

The semiconductor device according to any one of appendices D1 to D21,in which the substrate includes a monocrystalline intrinsic semiconductor material.

The semiconductor device according to any one of appendices D1 to D52,in which the sealing resin includes a thermosetting resin.

Hereunder, a semiconductor device (and a manufacturing method thereof) according to some embodiments and variations of a second aspect of the present disclosure, will be described with reference toFIG.49toFIG.76.

The terms “first”, “second”, “third”, and so forth used in the present disclosure merely serve as a label, and are not intended to specify an order or grade with respect to the objects accompanied with these terms. The term “flush” used in the present disclosure refers to the state where surfaces located adjacent to each other are smoothly connected to each other, as result of the manufacturing method exemplified in the present disclosure. However, a discontinuous portion or a stepped portion may inevitably be formed between such surfaces, owing to, for example, the manufacturing method, a manufacturing error, or a difference in thermal expansion coefficient of the material.

In the description of the present disclosure, the expressions “An object A is formed in an object B”, and “An object A is formed on an object B” imply the situation where, unless otherwise specifically noted, “the object A is formed directly in or on the object B”, and “the object A is formed in or on the object B, with something else interposed between the object A and the object B”. Likewise, the expression “An object A is arranged in an object B”, and “An object A is arranged on an object B” imply the situation where, unless otherwise specifically noted, “the object A is arranged directly in or on the object B”, and “the object A is arranged in or on the object B, with something else interposed between the object A and the object B”. Further, the expression “An object A is located on an object B” implies the situation where, unless otherwise specifically noted, “the object A is located on the object B, in contact with the object B”, and “the object A is located on the object B, with something else interposed between the object A and the object B”. Further, the expression “An object A is stacked in an object B”, and “An object A is stacked on an object B” imply the situation where, unless otherwise specifically noted, “the object A is stacked directly in or on the object B”, and “the object A is stacked in or on the object B, with something else interposed between the object A and the object B”. Still further, the expression “An object A overlaps with an object B as viewed in a certain direction” implies the situation where, unless otherwise specifically noted, “the object A overlaps with the entirety of the object B”, and “the object A overlaps with a part of the object B”.

FIG.49toFIG.59illustrate a semiconductor device A1according to a second aspect of the first embodiment. The semiconductor device A1includes a semiconductor element10, a substrate20, an insulation film29, a plurality of wiring layers30, a plurality of second columnar electrodes41, a plurality of first columnar electrodes42, a plurality of bonding sections50, a plurality of external electrodes60, and a resin member70.

FIG.49is a perspective view showing the semiconductor device A1.FIG.50is a plan view showing the semiconductor device A1.FIG.51is a plan view corresponding toFIG.50, with a plurality of external electrodes excluded, and a semiconductor element10and a resin member70indicated by imaginary lines (dash-dot-dot lines).FIG.52is a front view showing the semiconductor device A1.FIG.53is a side view (left-side view) showing the semiconductor device A1.FIG.54is a cross-sectional view taken along a line54-54inFIG.51.FIG.55is a partially enlarged cross-sectional view fromFIG.54.FIG.56is a cross-sectional view taken along a line56-56inFIG.51.FIG.57is a partially enlarged cross-sectional view fromFIG.56.FIG.58is a cross-sectional view taken along a line58-58inFIG.51.FIG.59is a partially enlarged cross-sectional view fromFIG.58.

For the sake of convenience in description, three directions orthogonal to each other will be defined as x-direction, y-direction, and z-direction. The z-direction corresponds to the thickness direction of the semiconductor device A1. The x-direction corresponds to the left-right direction in the plan view (seeFIG.50) of the semiconductor device A1. The y-direction corresponds to the up-down direction in the plan view (seeFIG.50) of the semiconductor device A1. If necessary, one side in the x-direction will be defined as x1-side, and the other side in the x-direction will be defined as x2-side. Likewise, one side in the y-direction will be defined as y1-side, and the other side will be defined as y2-side, and one side in the z-direction will be defined as z1-side, and the other side will be defined as z2-side. The z1-side may be referred to as lower side, and the z2-side may be referred to as upper side.

The semiconductor device A1is to be surface-mounted on a circuit board of an electronic device or the like. To mount the semiconductor device A1on the circuit board, for example solder is employed (hereinafter, “mount solder”). When the semiconductor device A1is mounted on the circuit board, the face of the semiconductor device A1oriented to the z2-side is opposed to the circuit board, in contact with the mount solder. The thickness (size in the z-direction) of the semiconductor device A1is, for example, approximately 550 μm.

The semiconductor element10serves as the functional center of the semiconductor device A1. The semiconductor element10may be one of, for example, an integrated circuit (IC) such as a large-scale integration (LSI), a voltage control element such as a low drop out (LDO), an amplifying element such as an operational amplifier, and a discrete part such as a transistor or a diode. The semiconductor element10has a structure that allows the surface mounting. The semiconductor element10has a rectangular shape as viewed in the z-direction (or “in plan view” where appropriate), though the plan-view shape is not specifically limited. The semiconductor element10is conductively bonded to the plurality of wiring layers30, via the plurality of bonding sections50.

As shown inFIG.54,FIG.56, andFIG.58, the semiconductor element10includes an element obverse face101and an element reverse face102. The element obverse face101and the element reverse face102are spaced apart from each other in the z-direction. The element obverse face101is oriented to the z2-side, and the element reverse face102is oriented to the z1-side. As shown inFIG.59, a plurality of element electrodes11are formed on the element reverse face102. The plurality of element electrodes11are each formed of aluminum (Al). The plurality of element electrodes11each serve as a terminal of the semiconductor element10. The plurality of element electrodes11overlap with the plurality of bonding section50, in plan view. The number and position of the plurality of element electrodes11may be changed as appropriate, depending on the design of the semiconductor element10.

The substrate20supports the semiconductor element10. The substrate20is formed of a monocrystalline intrinsic semiconductor material (e.g., silicon (Si)). The substrate20has, for example, a rectangular shape in plan view. The substrate20includes a substrate obverse face201, a substrate reverse face202, a plurality of first substrate side faces203, a plurality of second substrate side faces204, and a plurality of substrate connecting surfaces205.

As shown inFIG.52toFIG.58, the substrate obverse face201and the substrate reverse face202are spaced apart from each other in the z-direction. The substrate obverse face201is oriented to the z2-side, and the substrate reverse face202is oriented to the z1-side. The substrate obverse face201is opposed to the semiconductor element10. The substrate obverse face201and the substrate reverse face202are flat.

As shown inFIG.52toFIG.58, the plurality of first substrate side faces203and the plurality of second substrate side faces204are each located between the substrate obverse face201and the substrate reverse face202, in the z-direction. The plurality of first substrate side faces203and the plurality of second substrate side faces204are flat. The edge on the z2-side of each of the first substrate side faces203is connected to the substrate obverse face201, and the edge on the z1-side of each of the second substrate side faces204is connected to the substrate reverse face202. The first substrate side faces203are smaller in size in the z-direction, than the second substrate side faces204. For example, the size in the z-direction of the first substrate side face203is approximately 50 μm, and the size in the z-direction of the second substrate side face204is approximately 310 μm. The substrate20includes, as shown inFIG.50andFIG.51, a pair of first substrate side face203and second substrate side face204each oriented to the x1-side, a pair of first substrate side face203and second substrate side face204each oriented to the x2-side, a pair of first substrate side face203and second substrate side face204each oriented to the y1-side, and a pair of first substrate side face203and second substrate side face204each oriented to the y2-side. In each of the mentioned pairs, the first substrate side face203is located on the inner side of the second substrate side face204.

As shown inFIG.52toFIG.58, the plurality of substrate connecting surfaces205are each connected to the pair of first substrate side face203and second substrate side face204. The substrate connecting surfaces205are oriented to the z2-side. The substrate connecting surfaces205are flat. The substrate connecting surface205may be inclined or curved, with respect to a x-y plane. The width d1of the substrate connecting surfaces205(seeFIG.55andFIG.57) is, for example, approximately 10 μm. The width d1of the substrate connecting surface205refers to the length of a line segment between the edge of the substrate connecting surface205connected to the first substrate side face203and the edge connected to the second substrate side face204, and parallel to the x-direction or y-direction. Therefore, the separation distance between the pair of first substrate side face203and second substrate side face204in plan view is, for example, approximately 10 μm.

The insulation film29is formed on the substrate obverse face201, as shown inFIG.54toFIG.59. The insulation film29covers the entirety of the substrate obverse face201. The insulation film29is, for example, formed of an oxide film (SiO2) and a nitride film (Si3N4) stacked on the oxide film.

The plurality of wiring layers30are, as shown inFIG.51andFIG.54toFIG.58, formed on the substrate obverse face201of the substrate20, via the insulation film29. The plurality of wiring layers30constitute a part of the conduction path between the semiconductor element10and the circuit board on which the semiconductor device A1is mounted. The plurality of wiring layers30are spaced apart from one another.

The plurality of wiring layers30each include an underlying layer301and a plated layer302, as shown inFIG.54toFIG.58. The underlying layer301is in contact with the insulation film29. The underlying layer301includes a barrier layer formed in contact with the insulation film29, and a seed layer stacked on the barrier layer. The barrier layer is, for example, formed of titanium (Ti). The seed layer is, for example, formed of copper (Cu). The underlying layer301can be formed, for example, by a sputtering method. The plated layer302is stacked on the underlying layer301. In each of the wiring layers30, the plated layer302serves as the primary conduction path. The plated layer302is, for example, formed of Cu. The plated layer302can be formed, for example, through an electrolytic plating process. The thickness (size in the z-direction) of the underlying layer301is, for example, approximately 200 nm to 900 nm, and the thickness (size in the z-direction) of the plated layer302is, for example, approximately 5 μm to 25 μm. The thickness (size in the z-direction) of each of the wiring layers30is, for example, approximately 5 μm to 25 μm.

The plurality of wiring layers30include a plurality of wiring sections31and a plurality of wiring sections32, as shown inFIG.51andFIG.54toFIG.58. The plurality of wiring sections31are each electrically connected to one of the power terminals of the semiconductor element10or one of the ground terminals of the semiconductor element10. The plurality of wiring sections32are each electrically connected to the terminal of the semiconductor element10, other than the power terminal and the ground terminal (e.g., signal terminal).

The plurality of second columnar electrodes41and the plurality of first columnar electrodes42are formed on the plurality of wiring layers30, as shown inFIG.51andFIG.56toFIG.58. The plurality of second columnar electrodes41and the plurality of first columnar electrodes42are spaced apart from one another. The plurality of second columnar electrodes41and the plurality of first columnar electrodes42are located on the outer side of the semiconductor element10, in plan view. In other words, the semiconductor element10is surrounded by the plurality of second columnar electrodes41and the plurality of first columnar electrodes42. The plurality of second columnar electrodes41and the plurality of first columnar electrodes42each protrude to the z2-side from the wiring layer30, in plan view. The plurality of second columnar electrodes41and the plurality of first columnar electrodes42are each located on the inner side of the peripheral edge of both of the substrate20and the resin member70in plan view, as shown inFIG.51. The plurality of second columnar electrodes41and the plurality of first columnar electrodes42are, for example, formed of Cu. The plurality of second columnar electrodes41and the plurality of first columnar electrodes42can be formed, for example, through an electrolytic plating process.

The plurality of second columnar electrodes41are formed on the plurality of wiring sections31, as shown inFIG.56andFIG.57. The second columnar electrodes41each include a second top face411, a second contact surface412, a second exposed side face413, a second covered side face414, and a second connecting surface415.

The second top face411and the second contact surface412are spaced apart from each other in the z-direction, as shown inFIG.57. The second top face411is oriented to the z2-side, and the second contact surface412is oriented to the z1-side. The second top face411is exposed from the resin member70. The second contact surface412is in contact with the wiring sections31.

The second exposed side face413and the second covered side face414are oriented to the outer side of the semiconductor device A1from the second columnar electrode41, as shown inFIG.57. The second exposed side face413and the second covered side face414are located between the second top face411and the second contact surface412, in the z-direction. The edge on the z2-side of the second exposed side face413is connected to the second top face411, and the edge on the z1-side of the second covered side face414is connected to the second contact surface412. The second exposed side face413is exposed from the resin member70, and the second covered side face414is covered with the resin member70. The size of the second exposed side face413in the z-direction is, for example, approximately 100 μm, and the size of the second covered side face414in the z-direction is, for example, approximately 60 μm to 90 μm.

The second connecting surface415is connected to the second exposed side face413and the second covered side face414, as shown inFIG.57. The second connecting surface415is exposed from the resin member70. The second connecting surface415overlaps with the semiconductor element10, as viewed in the x-direction or y-direction. The width d2(seeFIG.57) of the second connecting surface415is, for example, approximately 15 μm. The width d2of the second connecting surface415refers to the length of a line segment between the edge of the second connecting surface415connected to the second exposed side face413and the edge connected to the second covered side face414, and parallel to the x-direction or y-direction.

The plurality of first columnar electrodes42are formed on the plurality of wiring sections32, as shown inFIG.58. The first columnar electrodes42each include a first top face421, a first contact surface422, a first exposed side face423, a first covered side face424, and a first connecting surface425. Four out of the plurality of first columnar electrodes42, located at the respective corners of the semiconductor device A1in plan view, each include two each of the first exposed side faces423, the first covered side faces424, and the first connecting surfaces425.

The first top face421and the first contact surface422are spaced apart from each other in the z-direction, as shown inFIG.58. The first top face421is oriented to the z2-side, and the first contact surface422is oriented to the z1-side. The first top face421is exposed from the resin member70. The first contact surface422is in contact with the wiring sections32. In the example shown inFIG.50andFIG.51, the four out of the plurality of first columnar electrodes42, located at the respective corners of the semiconductor device A1in plan view, are larger in plan-view area of the first top face421, than the remaining first columnar electrodes42.

The first exposed side face423and the first covered side face424are oriented to the outer side of the semiconductor device A1from the first columnar electrode42, as shown inFIG.58. The first exposed side face423and the first covered side face424are located between the first top face421and the first contact surface422, in the z-direction. The edge on the z2-side of the first exposed side face423is connected to the first top face421, and the edge on the z1-side of the first covered side face424is connected to the first contact surface422. The first exposed side face423is exposed from the resin member70, and the first covered side face424is covered with the resin member70. The size of the first exposed side face423in the z-direction is, for example, approximately 100 μm, and the size of the first covered side face424in the z-direction is, for example, approximately 60 μm to 90 μm.

The first connecting surface425is connected to the first exposed side face423and the first covered side face424, as shown inFIG.58. The first connecting surface425is exposed from the resin member70. The first connecting surface425overlaps with the semiconductor element10, as viewed in the x-direction or y-direction. The width of the first connecting surface425is, for example, approximately 15 μm. The width of the second connecting surface415refers to the length of a line segment between the edge of the first connecting surface425connected to the first exposed side face423and the edge connected to the first covered side face424, and parallel to the x-direction or y-direction.

As shown inFIG.50andFIG.51, the second top face411of each of the second columnar electrodes41is larger in plan-view area, than the first top face421of each of the first columnar electrodes42. In the example shown inFIG.50andFIG.51, the second top face411of each of the second columnar electrodes41extends farther into the semiconductor device A1, than the first top face421of each of the first columnar electrodes42. Here, the plan-view area of the second top face411may be equal to or smaller than that of the first top face421, without limitation to being larger.

The plurality of bonding sections50are for bonding the semiconductor element10to the plurality of wiring layers30. The bonding sections50are, for example, formed of solder. The bonding sections50are, for example, what is known as a solder bump. The bonding sections50are, as shown inFIG.59, each interposed between the element electrode11of the semiconductor element10and the wiring layer30, to conductively bond these components.

The plurality of external electrodes60each serve as a terminal of the semiconductor device A1. The plurality of external electrodes60include, as shown inFIG.50,FIG.52, andFIG.53, those covering the second top face411and the second exposed side face413of the second columnar electrodes41, and those covering the first top face421and the first exposed side face423of the first columnar electrodes42. The external electrodes60each include, for example, a nickel (Ni) layer, a palladium (Pd) layer, and a gold (Au) layer, stacked in this order from the side in contact with the second columnar electrode41or the first columnar electrode42. Here, the Pd layer may be excluded. The external electrodes60can be formed, for example, through a non-electrolytic plating process.

The resin member70is formed on the substrate20. The resin member70is a sealing material covering the semiconductor element10, as shown inFIG.54,FIG.56, andFIG.58. The resin member70is, for example, formed of a black epoxy resin. The resin member70may be formed of any electrically insulative resin material, without limitation to the epoxy resin. The resin member70can be formed, for example, through a molding process. The resin member70has, for example, a rectangular shape in plan view. The resin member70includes a resin obverse face71, a resin reverse face72, a plurality of first resin side faces731, a plurality of second resin side faces732, and a plurality of resin connecting surfaces733.

The resin obverse face71and the resin reverse face72are spaced apart from each other in the z-direction, as shown inFIG.54,FIG.56, andFIG.58. The resin obverse face71is oriented to the z2-side, and the resin reverse face72is oriented to the z1-side. The resin obverse face71is flat. The resin obverse face71is flush with the second top faces411(second columnar electrodes41) and the first top faces421(first columnar electrodes42). The second top faces411and the first top faces421are exposed from the resin obverse face71. When the semiconductor device A1is mounted on the circuit board, the resin obverse face71is opposed to the circuit board. The resin reverse face72is in contact with the insulation film29.

The plurality of first resin side faces731and the plurality of second resin side faces732are each located between the resin obverse face71and the resin reverse face72in the z-direction, as shown inFIG.54toFIG.58. The plurality of first resin side faces731and the plurality of second resin side faces732are flat. The edge on the z2-side of each of the first resin side faces731is connected to the resin obverse face71, and the edge on the z1-side of each of the second resin side faces732is connected to the resin reverse face72. The size of each of the first resin side faces731in the z-direction is, for example, approximately 100 μm, and the size of each of the second resin side faces732in the z-direction is, for example, approximately 90 μm. The first resin side faces731are each flush with the second exposed side faces413(second columnar electrodes41) or the first exposed side faces423(first columnar electrodes42). The second exposed side faces413and the first exposed side faces423are exposed from the first resin side face731. The second resin side faces732are each flush with the first substrate side face203. The second resin side faces732each include a portion overlapping with the second covered side faces414(second columnar electrodes41) or the first covered side faces424(first columnar electrodes42), as viewed in the x-direction or y-direction.

The resin member70includes, as shown inFIG.50, a pair of first resin side face731and second resin side face732each oriented to the x1-side, a pair of first resin side face731and second resin side face732each oriented to the x2-side, a pair of first resin side face731and second resin side face732each oriented to the y1-side, and a pair of first resin side face731and second resin side face732each oriented to the y2-side. In each of such pairs, the first resin side face731is located on the inner side of the second resin side face732, in plan view.

The plurality of resin connecting surfaces733are each connected to the pair of first resin side face731and second resin side face732, as shown inFIG.55andFIG.57. The resin connecting surfaces733are each oriented to the z2-side. For example, the resin connecting surfaces733may be flat. The resin connecting surfaces733may be inclined or curved, with respect to the x-y plane. The resin connecting surfaces733are flush with the second connecting surfaces415(second columnar electrodes41) and the first connecting surfaces425(first columnar electrodes42). The second connecting surfaces415and the first connecting surfaces425are exposed from the resin connecting surface733. The resin connecting surfaces733each overlap with the semiconductor element10, as viewed in the x-direction or y-direction. The width d3of the resin connecting surface733(seeFIG.55) is, for example, approximately 45 μm. The width d3of the resin connecting surface733refers to the length of a line segment between the edge of the resin connecting surface733connected to the first resin side face731and the edge connected to the second resin side face732, and parallel to the x-direction or y-direction. In the semiconductor device A1, since the width d2of the second connecting surface415(seeFIG.57) is for example approximately 15 μm, the separation distance d4(seeFIG.57) between the second resin side face732and the second covered side face414in plan view is, for example, approximately 30 μm. This also applies to the separation distance between the second resin side face732and the first covered side face424.

Referring now toFIG.60toFIG.73, a manufacturing method of the semiconductor device A1according to the first embodiment of the second aspect will be described hereunder. The manufacturing method described hereunder is for manufacturing a plurality of semiconductor devices A1.FIG.60toFIG.73are cross-sectional views each showing a process in the manufacturing method of the semiconductor device A1, and correspond to the cross-sectional view ofFIG.56showing the semiconductor device A1, exceptFIG.69andFIG.73.FIG.69is a partially enlarged cross-sectional view fromFIG.68, andFIG.73is a partially enlarged cross-sectional view fromFIG.72.

Referring first toFIG.60, a substrate820is prepared, and an insulation film829is formed on the substrate820. The substrate820is formed of a monocrystalline intrinsic semiconductor material. The intrinsic semiconductor material may be, for example, Si. In the process of preparing the substrate820(substrate preparation process), for example a Si wafer is prepared as the substrate820. The substrate820includes a substrate obverse face820aand a substrate reverse face820bspaced apart from each other in the z-direction. The substrate obverse face820ais oriented to the z2-side, and the substrate reverse face820bis oriented to the z1-side. In the process of forming the insulation film829(insulation film formation process), the insulation film829is formed on the substrate obverse face820a, as shown inFIG.60. The insulation film829can be formed, by depositing an oxide film (e.g., SiO2) on the substrate obverse face820aof the substrate820by thermal oxidation, and then depositing a nitride film (Si3N4) on the oxide film, by plasma chemical vapor deposition (CVD).

Turning toFIG.61, an underlying layer830ais formed so as to cover the insulation film829. In the process of forming the underlying layer830a(underlying layer formation process), the underlying layer830ais formed by depositing a barrier layer over the entire surface of the insulation film829by a sputtering method, and depositing a seed layer on the barrier layer by the sputtering method. The barrier layer is, for example, formed of Ti in a thickness of 100 nm to 300 nm, and the seed layer is, for example, formed of Cu in a thickness of 200 nm to 600 nm.

Turning toFIG.62, a plurality of plated layers830bare formed. In the process of forming the plurality of plated layers830b(plated layer formation process), the plurality of plated layers830bare formed by applying a lithographic pattern on the underlying layer830a, and performing an electrolytic plating process using the underlying layer830aas the conduction path. The plated layer830bis, for example, formed of Cu in a thickness of 5 μm to 25 μm.

Turning toFIG.63, a plurality of columnar electrodes840are formed on the plurality of plated layers830b. The columnar electrodes840each correspond to one of the second columnar electrode41and the first columnar electrode42of the semiconductor device A1. In the process of forming the plurality of columnar electrodes840(columnar electrode formation process), the plurality of columnar electrodes840are formed by applying a lithographic pattern on a part of the underlying layer830aand a part of the plated layer830b, and performing the electrolytic plating process using the underlying layer830aand the plated layer830bas the conduction path. The plurality of columnar electrodes840are, for example, formed of Cu. The plurality of columnar electrodes840include those to be subsequently formed into the plurality of second columnar electrodes41, and those to be subsequently formed into the plurality of first columnar electrodes42. SinceFIG.63is the cross-sectional view corresponding toFIG.56, the plurality of columnar electrodes840shown inFIG.63are all to be subsequently formed into the plurality of second columnar electrodes41of the semiconductor device A1.

Turning toFIG.64, a part of the underlying layer830ais removed. The part of the underlying layer830ato be removed is the region where the plurality of plated layers830bare not formed. In the process of removing the underlying layer830a(underlying layer removing process), the underlying layer830ais removed by a wet etching method using mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). Through the mentioned process, the residual portion of the plurality of underlying layers830aand the plurality of plated layers830bstacked thereon constitute the plurality of wiring layers830. The plurality of wiring layers830correspond to the plurality of wiring layers30of the semiconductor device A1. The plurality of wiring layers830include those to be subsequently formed into the plurality of wiring sections31, and those to be subsequently formed into the plurality of wiring sections32. The plurality of wiring layers830each having the columnar electrode840formed thereon are subsequently formed into the plurality of wiring sections31, and the plurality of wiring layers830without the columnar electrode840are subsequently formed into the plurality of wiring sections32.

Turning toFIG.65, a semiconductor element810is mounted. The semiconductor element810corresponds to the semiconductor element10of the semiconductor device A1. The semiconductor element810includes an element obverse face810aoriented to the z2-side and an element reverse face810boriented to the z1-side, and an element electrode (not shown) is formed on the element reverse face810b. On each of the plurality of element electrodes of the semiconductor element810, a bonding material850is formed. The bonding material850is, for example, a ball-shaped solder bump. In the process of mounting the semiconductor element810(element mounting process), the bonding material850(solder bump) is made to contact the wiring layer830, and the bonding material85(solder bump) is heated in a reflow device. Then the bonding material850is cooled so as to be solidified, so that the element electrodes of the semiconductor element810and the wiring layers830are conductively bonded to each other, via the bonding material850(solder bump).

Turning toFIG.66, a resin member870is formed. In the process of forming the resin member870(resin formation process), for example a molding process is employed. The molding method may be transfer molding, or compression molding. The resin member870is, for example, formed of a material containing a black epoxy resin. The resin member870formed through the resin formation process is located on the insulation film829(substrate obverse face820aof the substrate820), and covers the semiconductor element810. In addition, the face of the resin member870oriented to the z2-side (resin obverse face871) is located ahead of the face of the columnar electrodes840oriented to the z2-side. In other words, the columnar electrodes840are covered with the resin member870, immediately after the resin formation process.

Turning toFIG.67, the resin member870is ground so as to expose the columnar electrodes840from the resin obverse face871. In the process of grinding the resin member870(resin grinding process), for example a mechanical grinding machine is employed, to grind the resin member870toward the z1-side from the resin obverse face871, with a grinding stone. In this process, the resin member870is ground until the columnar electrodes840are exposed from the resin obverse face871. In the resin grinding process, the plurality of columnar electrodes840are also partially removed. Through the resin grinding process, the thickness of the resin member870is reduced. In addition, a top face840aexposed from the resin member870appears, on each of the plurality of columnar electrodes840. The resin obverse face871and the respective top faces840aof the columnar electrodes840are flush with each other, and grinding marks resultant from the grinding operation are formed so as to stride over the resin obverse face871and the top faces840a.

Turning toFIG.68andFIG.69, a plurality of first cutaway portions891are formed. To be more detailed, the plurality of first cutaway portions891are formed by cutting the plurality of columnar electrodes840and the resin member870to a halfway position thereof in the thickness direction (z-direction). The process of forming the plurality of first cutaway portions891(first cutting process) is, for example, a half-cut dicing process using a dicing blade. In the first cutting process, the plurality of first cutaway portions891are formed by performing the half-cut dicing, for example along cutting lines L1shown inFIG.67. InFIG.67, the cutting line L1is illustrated in a rectangular shape, in consideration of the thickness of the dicing blade to be employed. The width of each of the plurality of first cutaway portions891formed through the first cutting process is, for example, approximately 180 μm. This width is determined depending on the thickness of the dicing blade to be employed. As result of the first cutting process, a part of each of the columnar electrodes840is scraped off, and exposed side faces840cconnected to the top face840aappear. In addition, a part of the resin member870is scraped off, and first resin side faces873aconnected to the resin obverse face871appear.

Turning toFIG.70, external electrodes860are formed. In the process of forming the external electrode860(external electrode formation process), for example a Ni layer, a Pd layer, and an Au layer are sequentially precipitated through a non-electrolytic plating process, to thereby form the external electrodes860. To be more detailed, this process includes forming the Ni layer so as to cover the top face840aand the exposed side face840cof each of the columnar electrodes840, in contact therewith, forming the Pd layer on the Ni layer, and forming the Au layer on the Pd layer. The external electrode860may only include the Ni layer and the Au layer, instead of the Ni layer, the Pd layer, and the Au layer.

Turning toFIG.71, a part of the substrate820is ground. In the process of grinding the substrate820(substrate grinding process), for example a mechanical grinding machine is employed, to grind the substrate820toward the z2-side from the substrate reverse face820b, with a grinding stone. Accordingly, the thickness of the substrate820is reduced. On the substrate reverse face820b, grinding marks resultant from the grinding operation are formed. It is preferable to perform the substrate grinding process after the external electrode formation process, to stably transport the semi-finished semiconductor device to the non-electrolytic plating tank, in the mentioned external electrode formation process.

Turning toFIG.72andFIG.73, a plurality of second cutaway portions892are further formed, in the respective first cutaway portions891formed through the first cutting process. To be more detailed, the plurality of second cutaway portions892are formed by completely cutting the resin member870in the z-direction in each of the plurality of first cutaway portions891, and cutting the substrate820to a halfway position thereof in the thickness direction (s-direction). In the process of forming the plurality of second cutaway portions892(second cutting process), as in the first cutting process, the half-cut dicing is performed with the dicing blade. In the second cutting process, the plurality of second cutaway portions892are formed by performing the half-cut dicing, for example along cutting lines L2shown inFIG.71. InFIG.71, the cutting line L2is illustrated in a rectangular shape, in consideration of the thickness of the dicing blade to be employed. The width of each of the plurality of second cutaway portions892formed through the second cutting process is, for example, approximately 90 μm. This width is determined depending on the thickness of the dicing blade to be employed. As result of the second cutting process, the resin member870is cut in the z-direction, into a plurality of pieces each including the semiconductor element10. After the second cutting process, the second resin side face873bappears in the resin member870. After the second cutting process, further, the first substrate side face820cconnected to the substrate obverse face820aappears in the substrate820. The second resin side face873band the first substrate side face820care flush with each other.

Then the substrate820is divided into a plurality of individual pieces, each including the semiconductor element10. In the process of dividing into individual pieces (third cutting process), the substrate820is cut in the z-direction at each of the plurality of second cutaway portions892, for example by blade dicing, along cutting lines L3shown inFIG.72. The thickness of the dicing blade used in the third cutting process is, for example, approximately 70 μm. InFIG.72, the cutting line L3is illustrated in a rectangular shape, in consideration of the thickness of the dicing blade to be employed. Here, the cutting method is not limited to the blade dicing, but a different dicing method such as laser dicing or plasma dicing may be employed. As result of the third cutting process, the substrate820is cut in the z-direction. At this point, the second substrate side face (second substrate side face204of the semiconductor device A1), located on the outer side of the first substrate side face820cin plan view, is formed in the substrate820. Each of the individual pieces divided in the third cutting process corresponds to the semiconductor device A1shown inFIG.49toFIG.59.

The semiconductor device A1can be manufactured through the foregoing process. More specifically, the manufacturing method of the semiconductor device A1includes the substrate preparation process, the insulation film formation process, the underlying layer formation process, the plated layer formation process, the columnar electrode formation process, the underlying layer removing process, the element mounting process, the resin formation process, the resin grinding process, the first cutting process, the external electrode formation process, the substrate grinding process, the second cutting process, and the third cutting process. The underlying layer formation process, the plated layer formation process, and the underlying layer removing process may be collectively referred to as “wiring layer formation process”. The foregoing manufacturing method of the semiconductor device A1is merely exemplary. For example, the plurality of columnar electrodes840to be subsequently formed into the plurality of second columnar electrodes41, and the plurality of columnar electrodes840to be subsequently formed into the plurality of first columnar electrodes42may be formed through separate processes, in the columnar electrode formation process. In addition, the substrate grinding process may be skipped.

The semiconductor device A1and the manufacturing method thereof provide the following advantageous effects.

The semiconductor device A1includes the first columnar electrode42and the resin member70. The resin member70includes the first resin side face731and the second resin side face732. The first resin side face731is located on the inner side of the second resin side face732, in plan view. The first columnar electrode42includes the first exposed side face423. The first exposed side face423is exposed from the resin member70, in the first resin side face731. With such a configuration, the side face of the semiconductor device A1includes a stepped portion, and the first columnar electrode42is exposed from the resin member70, in the recessed portion of the stepped portion. Accordingly, when the semiconductor device A1is mounted on a circuit board of an electronic device or the like, with the mount solder, a solder fillet is formed so as to cover the first exposed side face423. Because of the presence of the solder fillet, the bonding condition of the semiconductor device A1(bonding condition of the mount solder) can be visually checked, without the need to employ X-ray inspection equipment. Consequently, the semiconductor device A1makes it easy to check the bonding condition of the mount solder.

In the semiconductor device A1, the separation distance d4(seeFIG.57) is longer than the width d2of the second connecting surface415(seeFIG.57). With such a configuration, the portion of the resin member70covering the second covered side face414(second columnar electrode41) is given an appropriate thickness (size in the x-direction or y-direction), and therefore the resin member70can be prevented from being separated from the second columnar electrode41. Consequently, the reliability of the semiconductor device A1can improved. Likewise, since the separation distance d4is longer than the width of the first connecting surface425, the resin member70can be prevented from being separated from the first columnar electrode42.

In the semiconductor device A1, the respective second top faces411of the second columnar electrodes41are larger in plan-view area, than the respective top faces421of the first columnar electrodes42. With such a configuration, the electrical resistance of the second columnar electrodes41becomes lower than that of the first columnar electrodes42, and therefore the second columnar electrodes41can accept a relatively larger current, compared with the first columnar electrode42. In the semiconductor device A1, for example, the second columnar electrodes41are each electrically connected to the element electrode11, serving as the power terminal or ground terminal of the semiconductor element10, via the wiring section31. The first columnar electrodes42are each electrically connected to the element electrode11, serving as the terminal other than the power terminal or ground terminal (e.g., signal terminal) of the semiconductor element10, via the wiring section32. The power terminal or the ground terminal can accept a relatively larger current, compared with other terminals. Consequently, in the semiconductor device A1, a conduction loss, for example originating from parasitic capacitance, can be suppressed.

In the semiconductor device A1, the first columnar electrodes42(first top face421) respectively located at the four corners in plan view are larger in plan-view area, than the remaining first columnar electrodes42(first top face421). The temperature in the semiconductor device A1fluctuates, owing to the operation thereof and the external environment. When the semiconductor device A1is mounted on a circuit board of an electronic device or the like, with the mount solder, the mount solder bonding the semiconductor device A1and the circuit board to each other is subjected to thermal stress, owing to the fluctuation in temperature. The thermal stress originates from a difference in thermal contraction between the circuit board and the semiconductor device A1. When the mount solder is repeatedly subjected to the thermal stress, the mount solder may suffer a crack. In particular, when the semiconductor device A1is mounted on the circuit board, relatively larger thermal stress is applied to the mount solder located at the four corners of the semiconductor device A1. In the semiconductor device A1, therefore, the first columnar electrodes42(first top faces421) located at the four corners are made larger in plan-view area than the remaining first columnar electrodes42(first top faces421), to improve the bonding strength of the mount solder at the four corners. Consequently, the resistance against temperature cycle can be improved, in the semiconductor device A1.

The manufacturing method of the semiconductor device A1includes the first cutting process and the second cutting process. In the first cutting process, the plurality of columnar electrodes840and the resin member870are cut at a time. In the second cutting process, the resin member870and the substrate820are cut at a time. Accordingly, in the manufacturing method of the semiconductor device A1includes two cutting processes, namely the first cutting process and the second cutting process, so that the plurality of columnar electrodes840and the substrate820are kept from being cut at a time. It is difficult to cut the plurality of columnar electrodes840and the substrate820at a time, because of the difference in material. However, since the semiconductor device A1is manufactured without cutting the plurality of columnar electrodes840and the substrate820at a time, the semiconductor device A1can be manufactured free from technical difficulty.

In the semiconductor device A1, the first substrate side faces203are smaller in size in the z-direction, than the second substrate side faces204. As described above, the first substrate side faces203, in other words the first substrate side faces820c, are formed in the second cutting process where the resin member870and the substrate820are diced at a time. In contrast, the second substrate side faces204are formed in the third cutting process, where only the substrate820is diced. In general, higher processing accuracy and higher processing speed can be attained, when a single type of material is diced, than when two types of materials are diced. Accordingly, by making the size of the first substrate side faces203in the z-direction smaller than that of the second substrate side faces204, a smaller amount of the substrate820is diced away in the second cutting process, than in the third cutting process. Therefore, with the manufacturing method of the semiconductor device A1, higher processing accuracy and higher processing speed can be attained, in the dicing process of the substrate820.

FIG.74illustrates a semiconductor device A2according to a second embodiment of the second aspect.FIG.74is a cross-sectional view showing the semiconductor device A2, corresponding to the cross-section of the semiconductor device A1shown inFIG.56.

The semiconductor device A2is different from the semiconductor device A1, in that the substrate20is without the plurality of second substrate side faces204. In other words, the side face of the substrate20is without the stepped portion. In addition, the substrate20of the semiconductor device A2is smaller in thickness (size in the z-direction) than the substrate20of the semiconductor device A1. Accordingly, the semiconductor device A2can be made thinner than the semiconductor device A1.

The semiconductor device A2can be manufactured, for example, by grinding off a larger amount of the substrate820, in the substrate grinding process of the manufacturing method of the semiconductor device A1. In the manufacturing method of the semiconductor device A2, the resin member870is completely cut, and the substrate820is also completely cut, in the second cutting process. As result, the substrate820is divided into the individual pieces each including the semiconductor element10, and the semiconductor device A2is obtained. Therefore, the third cutting process is skipped.

In the semiconductor device A2also, as in the semiconductor device A1, the side face of the semiconductor device A2includes a stepped portion, and a part of the first columnar electrode42is exposed, in the recessed portion of the stepped portion. Accordingly, the semiconductor device A2enables, like the semiconductor device A1, the bonding condition of the mount solder to be visually checked. Consequently, the semiconductor device A2makes it easy to check the bonding condition of the mount solder.

FIG.75illustrates a semiconductor device A3according to a third embodiment of the second aspect. The semiconductor device A3is without the substrate20, unlike the semiconductor device A1.FIG.75is a cross-sectional view showing the semiconductor device A3, corresponding to the cross-section of the semiconductor device A1shown inFIG.56.

The semiconductor device A3can be manufactured, for example, by completely grinding off the substrate820(removing the entirety of the substrate820), in the substrate grinding process of the manufacturing method of the semiconductor device A1. At this point, the insulation film829may also be removed at a time, or be left unremoved.FIG.75illustrates the example where the insulation film829has also been removed, and therefore the semiconductor device A3is without the insulation film29.

As described above, the semiconductor device A3shown inFIG.75is without the insulation film29. Therefore, the wiring layers30are exposed from the resin member70(resin reverse face72). When the wiring layers30are exposed from the resin member70, an accidental short circuit may occur between a plurality of wiring layers30. Accordingly, in the semiconductor device A3without the insulation film29, it is preferable to form a protective film39, so as to cover at least the portion of the wiring layers30exposed from the resin reverse face72, as shown inFIG.75. In the example shown inFIG.75, the protective film39is formed all over the resin reverse face72, so as to stride over the plurality of wiring layers30. The protective film39may be formed of, for example, an insulative material such a polyimide resin or a phenol resin.

In the semiconductor device A3also, as in the semiconductor device A1, the side face of the semiconductor device A3includes a stepped portion, and a part of the first columnar electrode42is exposed, in the recessed portion of the stepped portion. Accordingly, the semiconductor device A3enables, like the semiconductor device A1, the bonding condition of the mount solder to be visually checked. Consequently, the semiconductor device A3makes it easy to check the bonding condition of the mount solder.

Since the semiconductor device A3is without the substrate20, the semiconductor device A3can be made even thinner, than the semiconductor device A2.

In the first to the third embodiments of the second aspect, the configuration of the bonding section50is not limited to the above.FIG.76illustrates the bonding section50according to a variation.FIG.76is a partially enlarged cross-sectional view showing the bonding section50, corresponding to the partially enlarged cross-sectional view ofFIG.59.

The bonding section50according to this variation is applicable to any of the semiconductor devices A1to A3. The plurality of bonding sections50according to this variation each include a protective layer51and a bonding layer52, as shown inFIG.76.

In each of the bonding sections50, the protective layer51is formed on the wiring layer30, as shown inFIG.76. The protective layers51are each formed in a frame shape with an opening at the center, in plan view. The protective layers51each surround the bonding layer52, in plan view. The protective layers51each have, for example, a rectangular annular shape in plan view. The plan-view annular shape of the protective layer51is not limited to the rectangular annular shape, but may be a circular annular shape, an elliptical annular shape, or a polygonal annular shape. The protective layers51are, for example, formed of a polyimide resin, without limitation thereto.

In each of the bonding sections50, the bonding layer52serves to conductively bond the element electrode11of the semiconductor element10and the wiring layer30to each other. The bonding layers52are each formed on the wiring layer30(plated layer302). The bonding layer52covers the surface of the opening in the protective layer51. A part of the bonding layer52is filled in in the opening of the protective layer51.

The bonding layers52each include, as shown inFIG.76, a first layer521, a second layer522, and a third layer523stacked on each other. The first layer521is formed on the wiring layer30(plated layer302), in contact with the plated layer302. The first layer521is, for example, formed of a metal containing Cu. The second layer522is formed on the first layer521, in contact therewith. The second layer522is, for example, formed of a metal containing Ni. The third layer523is formed on the second layer522, in contact therewith. The third layer523is also in contact with the element electrode11of the semiconductor element10. The third layer523is, for example, formed of an alloy containing Sn. Examples of such alloy include a lead-free solder such as a Sn—Sb alloy or a Sn—Ag alloy. The configuration of the bonding layer52is not limited to the above, provided that the element electrode11of the semiconductor element10and the wiring layer30can be conductively bonded to each other.

The plurality of bonding sections50according to this variation each include the protective layer51, surrounding the bonding layer52in plan view. Such a configuration prevents a part of the bonding layer52(third layer523, in the example ofFIG.76) from spreading to an undesired region, when the bonding layer52is molten by the heat of the reflow operation in the element mounting process. Accordingly, for example an accidental short circuit between the plurality of element electrodes11, and between the plurality of wiring layers30can be prevented, and therefore a malfunction of the semiconductor device A1to A3can be prevented.

In the example shown inFIG.76, the element electrode11is not protruding from the element reverse face102. However, in the case where the element electrode11is formed so as to protrude from the element reverse face102, unlike in the foregoing example, the protective layer51facilitates the element electrode11to self-align with the wiring layer30.

The semiconductor device according to the second aspect of the present disclosure, and the manufacturing method thereof, are not limited to the foregoing embodiments. The specific configuration of the elements of the semiconductor device, and the specific processes in the manufacturing method of the semiconductor device may be modified as desired. The technical ideas that can be perceived from the embodiments of the second aspect and the variations thereof will be described in the following clauses.

A semiconductor device including:a semiconductor element formed with an element electrode;a wiring layer located on one side of the semiconductor element, in a thickness direction of the semiconductor element, and electrically connected to the element electrode;a first columnar electrode protruding from the wiring layer to the other side in the thickness direction; anda resin member covering the semiconductor element,in which the resin member includes a resin obverse face and a resin reverse face spaced apart from each other in the thickness direction, a first resin side face connected to the resin obverse face, and a second resin side face connected to the resin reverse face,the first resin side face is located on an inner side of the second resin side face, as viewed in the thickness direction,the first columnar electrode includes a first exposed side face exposed from the resin member, a first covered side face covered with the resin member, and a first top face connected to the first exposed side face and flush with the resin obverse face,the first exposed side face is located on an inner side of the first covered side face as viewed in the thickness direction, and flush with the first resin side face,the first covered side face and the second resin side face are each oriented in a first direction orthogonal to the thickness direction, andthe first covered side face overlaps with the second resin side face, as viewed in the first direction.

The semiconductor device according to Clause E1,in which the first columnar electrode further includes a first connecting surface connected to the first exposed side face and the first covered side face, andthe first connecting surface overlaps with the semiconductor element, as viewed in the first direction.

The semiconductor device according to Clause E2,in which the resin member further includes a resin connecting surface connected to the first resin side face and the second resin side face, andthe resin connecting surface and the first connecting surface are flush with each other.

The semiconductor device according to Clause E3,in which the resin connecting surface is larger in size in the first direction, than the first connecting surface.

The semiconductor device according to any one of Clause E1 to Clause E4, further including an external electrode covering the first top face and the first exposed side face.

The semiconductor device according to any one of Clause E1 to Clause E5, further including a bonding section conductively bonding the semiconductor element and the wiring layer to each other,in which the semiconductor element includes an element reverse face oriented to the same side as is the resin reverse face,the element electrode is formed on the element reverse face, andthe bonding section is interposed between the element electrode and the wiring layer.

The semiconductor device according to any one of Clause E1 to Clause E6, further including a substrate formed of a semiconductor material,in which the substrate is located on the one side in the thickness direction, with respect to the resin member.

The semiconductor device according to Clause E7,in which the substrate includes a substrate obverse face and a substrate reverse face spaced apart from each other in the thickness direction, a first substrate side face connected to the substrate obverse face, and a second substrate side face connected to the substrate reverse face,the wiring layer is formed on the substrate obverse face, andthe first substrate side face is flush with the second resin side face, and located on an inner side of the second substrate side face, as viewed in the thickness direction.

The semiconductor device according to Clause E8,in which the first substrate side face is smaller in size in the thickness direction, than the second substrate side face.

The semiconductor device according to any one of Clause E7 to Clause E9, further including an insulation film interposed between the substrate and the wiring layer.

The semiconductor device according to any one of Clause E7 to Clause E10, in which the semiconductor material includes Si.

The semiconductor device according to any one of Clause E1 to Clause E11, further including a second columnar electrode protruding from the wiring layer toward the other side in the thickness direction,in which the second columnar electrode includes a second exposed side face exposed from the resin member, a second covered side face covered with the resin member, and a second top face connected to the second exposed side face and flush with the resin obverse face,the first columnar electrode and the second columnar electrode are spaced apart from each other, as viewed in the thickness direction, andthe second top face is larger in plan-view area than the first top face.

A manufacturing method of a semiconductor device, the method including:a substrate preparation process including preparing a substrate having a substrate obverse face and a substrate reverse face spaced apart from each other in a thickness direction;a wiring layer formation process including forming a wiring layer on the substrate obverse face;a first columnar electrode formation process including forming a first columnar electrode on the wiring layer;an element mounting process including mounting a semiconductor element;a resin formation process including forming a resin member covering the semiconductor element, on the substrate;a first cutting process including cutting each of the first columnar electrode and the resin member to a halfway position thereof in the thickness direction, thereby forming a first cutaway portion; anda second cutting process including completely cutting the resin member in the thickness direction thereof, at the first cutaway portion,in which, in the first cutting process, a first exposed side face exposed from the resin member, and a first covered side face covered with the resin member are formed on the first columnar electrode, and a first resin side face is formed in the resin member,in the second cutting process, a second resin side face is formed in the resin member,the first resin side face is located on an inner side of the second resin side face, as viewed in the thickness direction,the first exposed side face is located on an inner side of the first covered side face, as viewed in the thickness direction, and flush with the first resin side face,the first covered side face and the second resin side face are each oriented in a first direction orthogonal to the thickness direction, andthe first covered side face overlaps with the second resin side face, as viewed in the first direction.

The method according to Clause E13, further including a substrate grinding process including grinding the substrate in the thickness direction, from the side of the substrate reverse face.

The method according to Clause E14,in which the substrate grinding process includes completely removing the substrate.

The method according to Clause E14,in which the second cutting process further includes cutting the substrate to a halfway position thereof in the thickness direction, thereby forming a second cutaway portion.

The method according to Clause E16, further including a third cutting process including completely cutting the substrate in the thickness direction, at the second cutaway portion.

The method according to any one of Clause E13 to Clause E17, further including an external electrode formation process including forming an external electrode,in which the first columnar electrode further includes a first top face exposed from the resin member,the first top face is connected to the first exposed side face, and oriented to the same side as is the substrate obverse face, andthe external electrode covers the first top face and the first exposed side face.