Desmear with metalized protective film

Embodiments herein may relate to a technique for generating a via in a substrate. Specifically, the technique may include coupling a polyethylene terephthalate (PET) layer, a protective metal layer, and a build-up layer to a metal layer. The process may further include etching a via in the PET layer, the protective metal layer, and at least a portion of the build-up layer. The process may further include performing a plasma desmear process on the substrate and then peeling the PET layer to remove the PET layer and the protective metal layer. Other embodiments may be described and/or claimed.

TECHNICAL FIELD

The present disclosure relates generally to the field of generating vias in substrates of integrated circuit (IC) packages, and more particularly to the field of desmear of said vias.

BACKGROUND

Traditionally in substrate build-up layer manufacturing, a wet desmear etching process may serve to both clean remaining laser via residue and to roughen the surface of a dielectric build-up layer for later electroless copper (Cu) adhesion. However, recent demand for finer pitch routing and high frequency data transfer integrity in high density interconnect substrates has highlighted the importance of low loss dielectric material and low interfacial surface roughness between the metal layer that results from the electroless Cu adhesion and the dielectric build-up layer.

Generally, legacy wet desmear processes may not be able to clean extremely low loss dielectric materials. One alternative process that may be used to adequately clean vias in extremely low loss dielectric materials subsequent to laser drilling of the vias may be to perform a plasma desmear process. Plasma desmear may be generally accomplished by capacitively coupled plasma (CCP), inductively coupled plasma (ICP), reactive ion etching (RIE), and/or some other type of plasma system using oxygen (O2) and/or fluorinated gases to etch organic layers of the dielectric material. While process conditions related to the plasma desmear may be optimized to reduce surface etching of the dielectric material, some etching will inevitably occur. This etching may potentially expose dielectric fillers, increase dielectric roughness, and/or potentially reduce adhesion strength to the electroless Cu.

DETAILED DESCRIPTION

Embodiments herein may relate to substrates that include vias that were generated in the substrate by applying a polyethylene terephthalate (PET) layer and a protective metal layer to a build-up layer prior to generation of the via. The via may be generated in the PET layer, protective metal layer, and at least part of the build-up layer. A plasma desmear process may then be performed to remove at least a portion of the build-up layer and expose a metal layer on a side of the build-up layer opposite the PET layer. The PET layer may then be removed, which may in turn remove the protective metal layer.

The above described process provides benefits that may not have been present in legacy desmear processes. For example, one legacy process that may have been used to prevent surface etching of the build-up material during the desmear process may have been to apply a metallic mask to the build-up layer. For example, the metallic mask may have been a metal film that was sputtered onto the build-up layer prior to laser drilling of the via, and then the mask may have been etched away after the plasma desmear process was complete. However, the above described metallic mask may have had the negative consequence of increasing the cost of the resultant substrate, both due to the application of the mask and the subsequent etching process to remove the mask. The use of the metallic mask may also increase the surface roughness of the surface of the build-up layer to which the metallic mask was applied.

An alternative legacy process may have been to apply a PET layer to the build-up layer prior to generation of the via. However, this technique may have a disadvantage in that the reactive species used for the plasma desmear process may also react with the PET layer. Therefore, a large majority of the reactive species may be consumed prior to entering the via. The consumed reactive species may become non-reactive, and therefore may not be adequate to remove the remnants of the build-up layer at the bottom of the via. One way to overcome this deficiency may be to provide a very large amount of reactive species, but doing so may significantly deform the shape of the via, leading to structural weaknesses.

In contrast to the two above described legacy processes or techniques, embodiments herein may allow for production of build-up layers with significantly decreased surface roughness and well-formed vias in a cost-efficient manner.

In various embodiments, the phrase “a first layer formed on a second layer” may mean that the first layer is formed over the second layer, and at least a part of the first layer may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other layers between the first layer and the second layer) with at least a part of the second layer.

FIG. 1is a simplified cross-sectional view of a substrate100that includes a via125, in accordance with various embodiments herein. Specifically, the substrate100may include a metal layer120coupled to a dielectric build-up layer105. In embodiments, the metal layer120may be copper, while in other embodiments the metal layer may be some other type of interconnect metal such as aluminum (Al) or tungsten (W), and/or some other type of appropriate interconnect metal. Similarly, the dielectric build-up layer105may include a material such as an Ajinomoto Build-up Film (ABF), a prepreg build-up film, or some other type of mold, dielectric, resist, reinforced, or laminate type film that has various properties including but not limited to low dielectric loss, low coefficient of thermal expansion (CTE), high thermal conductivity, high mechanical stability, or some other type of appropriate property.

The via125may go from a first surface110of the build-up layer105to the second surface155of the build-up layer105, and expose a surface115of the metal layer120in the via125. As can be seen, the via125may have relatively smooth sides130with a generally constant slope and direction from the first surface110of the build-up layer105to the second surface155of the build-up layer105.

Generally, the via125may be described in three dimensions as frustoconical, i.e., as a cone with the tip of the cone removed. As shown inFIG. 1, the diameter of the frustoconical via125at the surface110of the build-up layer105may be larger than the diameter of the frustoconical via125at the surface155of build-up layer105. However, in other embodiments the via125may have an oblong shape, an oval shape, a square shape, or some other type of shape when viewed from the top of the substrate100looking into the via125.

As will be described in greater detail below, the substrate100may have been formed by applying a PET layer and a protective metal layer to the surface110of the build-up layer105prior to generation of the via125. The via125may be generated in the PET layer, protective metal layer, and at least part of the build-up layer105. A plasma desmear process may then be performed to remove at least a portion of the build-up layer and expose a surface115of the metal layer120. The PET layer may then be removed, which may in turn remove the protective metal layer exposing the surface110of the build-up layer105. Through this process, the surface110of the build-up layer105may have an average roughness (Ra) of between approximately 50 nanometers (nm) and approximately 100 nm. Additionally, as mentioned above, the sides130of the via125may be relatively smooth and well formed, with a generally uniform slope from the surface110to the surface155of the build-up layer105.

FIG. 2depicts a stage of a process of generation of the substrate100ofFIG. 1, in accordance with various embodiments herein. In an initial configuration200, a build-up layer205(which may be similar to build-up layer105) may be coupled with a surface215of a metal layer220(which may be similar to metal layer120). A PET layer240and a protective metal layer245may be coupled with a surface210of the build-up layer205opposite the metal layer220. In embodiments the PET layer240may be polyethylene terephthalate, polyethylene naphthalate PET, or some other type of PET layer. In embodiments, polyethylene naphthalate may be referred to as “PEN,” but for the sake of consistency the term PET will be used herein and it will be understood that PET may refer to PET, PEN, or some other similar material. The protective metal layer245may be or may include aluminum (Al) or some other appropriate material.

In some embodiments, the PET layer240may be laminated together with build-up layer205prior to coupling of the build-up layer205to the metal layer220. For example, in some embodiments, PET film may be manufactured and rolled. The build-up material may be laminated to the PET film and the PET/build-up material may be re-rolled. To generate the configuration200, the laminated build-up material and PET film may be coupled with the metal layer220to form the metal layer220, the build-up layer205, and the PET layer240. The protective metal layer245may be formed through deposition techniques such as sputtering or some other appropriate deposition technique.

In other embodiments, the protective metal film used in the protective metal layer245may be sputtered or otherwise deposited onto the PET film, and then the build-up layer205may be laminated to the PET film on a side of the PET film opposite the protective metal film. The combined protective metal film, PET film, and build-up layer205may be coupled with the metal layer220to generate the configuration200ofFIG. 2.

It will be understood that the above described examples are intended as two example techniques that may be used to generate the configuration200ofFIG. 2, and other embodiments may be based on other techniques or processes. Subsequent to generation of the configuration200ofFIG. 2, a cure process may be performed on the metal layer220, build-up layer205, PET layer240, and/or protective metal layer245.

FIG. 3depicts another stage of the process of generation of the substrate ofFIG. 1, in accordance with various embodiments herein. Specifically,FIG. 3depicts a configuration300that may occur subsequent to generation of the configuration200ofFIG. 2. In embodiments, the configuration300may include a metal layer320, build-up layer305, PET layer340, and protective metal layer345that may be respectively similar to metal layer220, build-up layer205, PET layer240, and protective metal layer245.

A via325may be generated through the protective metal layer345, the PET layer340, the first surface310of the build-up layer305, and at least part of the build-up layer305as shown. Specifically, the via325may be formed through laser drilling, though in other embodiments the via325may be formed through some other optical, mechanical and/or chemical etching or drilling process. As shown, at least a portion of the build-up layer305may remain at the bottom of the via325such that the surface315of the metal layer320is not exposed in the via325.

If the via325is formed through laser drilling, the via325may be generally frustoconical and have relatively smooth sidewalls330that have a larger diameter at a part of the via325near the protective metal layer345than a part of the via325near the metal layer320, as shown. However, as noted above a frustoconical shape is one example and in other embodiments the shape of the via325may be different dependent on the process or technique used to generate the via325.

FIG. 4depicts another stage of the process of generation of the substrate ofFIG. 1, in accordance with various embodiments herein. Specifically,FIG. 4depicts a configuration400that may occur subsequent to generation of the configuration300ofFIG. 3. In embodiments, the configuration400may include a metal layer420, build-up layer405with first surface410, PET layer440, a protective metal layer445, and a via425with sidewalls430that may be respectively similar to metal layer320, build-up layer305with first surface310, PET layer340, protective metal layer345, via325and sidewalls330.

As shown inFIG. 4, a plasma desmear process may be performed on configuration400. As noted above, the plasma desmear process may be generally accomplished by CCP, ICP, REI, or some other type of plasma systems using oxygen (O2) and/or fluorinated gases to etch organic layers of the dielectric material. The plasma desmear process may result in reactive species450and consumed species455being present within the via425. The reactive species450may be particles or molecules that may chemically react with the build-up material of the build-up layer405. This reaction may remove a portion of the build-up layer405and generate consumed species455.

Generally, the protective metal layer445may not be reactive with the reactive species450of the plasma desmear process. Therefore, a greater amount of reactive species450may enter the via425and interact with the build-up layer405to expose the surface415of the metal layer420.

In some embodiments, the thickness of the PET layer440may affect the rate or quality of the etch of the build-up layer405performed by the plasma desmear process. Specifically, the aspect ratio of the via425, that is the ratio between the depth of the via425and the diameter of the via425, may decrease by decreasing the thickness of the PET layer440.

FIG. 5depicts another stage of the process of generation of the substrate ofFIG. 1, in accordance with various embodiments herein. Specifically,FIG. 5depicts a configuration500that may occur subsequent to generation of the configuration400ofFIG. 4. In embodiments, the configuration500may include a metal layer520, build-up layer505with first surface510, PET layer540, protective metal layer545, and a via525with sidewalls530that may be respectively similar to metal layer420, build-up layer405with first surface410, PET layer440, protective metal layer445, via425, and sidewalls430.

As shown inFIG. 5, the desmear process may have removed the remainder of the build-up layer505within the via525, exposing the surface515of the metal layer520. As shown, the sidewalls530of the via525may be relatively unaffected by the desmear process, and still retain a generally uniform slope from the part of the via525near the protective metal layer545to the part of the via525near the metal layer520.

Finally, to generate the substrate100ofFIG. 1, the PET layer540and the protective metal layer545may be removed from the build-up layer505, for example, by peeling the PET layer540from the build-up layer505. Peeling the PET layer540may result in removal of the protective metal layer545, which is coupled with the PET layer540(for example, by lamination of the PET layer540to the protective metal layer545). As noted above, through this process, the surface110of the build-up layer105may have an Ra value of between approximately 50 nm and approximately 100 nm. Additionally, as mentioned above, the sides130of the via125may be relatively smooth and well formed, with a generally uniform slope from the surface110to the surface155of the build-up layer105. Finally, the substrate100may be generated without the relatively high-cost process of applying a protective metal layer directly to the build-up layer and then subsequently removing the protective metal layer by way of a mask etch process. Additionally, the substrate100may be generated without requiring a reactive gas in plasma systems such as carbon tetrafluoride (CF4), which may be more cost friendly.

FIG. 6depicts an example image600for a legacy desmear process that utilizes only a PET layer without a protective metal layer, and an image610for a desmear process that utilizes both a PET layer and a protective metal layer in accordance with various embodiments. Image605depicts a more detailed image of the bottom of the via of image600. As can be seen, there may still be a resin smear within the via of images600and605. This resin smear may be a result of, for example, reaction of the reactive species of the plasma desmear material with the PET layer.

By contrast, image615depicts a more detailed image of the bottom of the via (which may be similar, for example, to via125) of image615. As can be seen inFIG. 6, the sidewalls and the bottom of the via of images610and615may be relatively clean and free of the resin smear shown inFIGS. 600 and 605.

FIG. 7depicts an example process for forming the substrate ofFIG. 1, in accordance with various embodiments herein. Initially, a PET layer such as PET layer240, a build-up layer such as build up layer205, and a protective metal layer such as protective metal layer245may be coupled with a metal layer such as metal layer220at710. As discussed above, in some embodiments the different layers may be deposited in different orders such that certain of the layers may be coupled with one another before another of the layers.

Subsequently, a via such as via325may be generated in a PET layer such as PET layer340, a protective metal layer such as protective metal layer345, and at least part of a build-up layer such as build-up layer305at715.

Subsequently, a plasma desmear process may be performed at720to expose the metal layer such as metal layer520at720.

Subsequently, the PET layer and the protective metal layer may be removed at725to generate the substrate100ofFIG. 1.

Embodiments of the present disclosure may be implemented into a system using the packages and manufacturing techniques disclosed herein.FIG. 8schematically illustrates a computing device800, in accordance with some implementations, which may include the substrate100ofFIG. 1.

The computing device800may be, for example, a mobile communication device or a desktop or rack-based computing device. The computing device800may house a board such as a motherboard802. In embodiments, the motherboard802may be constructed of the substrate100ofFIG. 1. The motherboard802may include a number of components, including (but not limited to) a processor804and at least one communication chip806. Any of the components discussed herein with reference to the computing device800may include the substrate100ofFIG. 1. For example, the substrate100may be part of a component such as a processor, a memory, a storage device, a system on chip (SoC), or an element thereof such as an interposer, a patch, and/or a die.

The computing device800may include a storage device808. In some embodiments, the storage device808may include one or more solid state drives. Examples of storage devices that may be included in the storage device808include volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory, ROM), flash memory, and mass storage devices (such as hard disk drives, compact discs (CDs), digital versatile discs (DVDs), and so forth).

Depending on its applications, the computing device800may include other components that may or may not be physically and electrically coupled to the motherboard802. These other components may include, but are not limited to, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and a camera.

The computing device800may include a plurality of communication chips806. For instance, a first communication chip806may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip806may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In some embodiments, the communication chip806may support wired communications. For example, the computing device800may include one or more wired servers.

The processor804and/or the communication chip806of the computing device800may include one or more dies or other components in an IC package. Such an IC package may be coupled with an interposer or another package using any of the techniques disclosed herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The following paragraphs provide examples of various ones of the embodiments disclosed herein.

Example 1 may include a substrate comprising: a metal layer with a first side and a second side opposite the first side; a build-up layer with a first side coupled with the first side of the metal layer, and a second side opposite the first side, the second side having an average roughness (Ra) of between approximately 50 nanometers (nm) and approximately 100 nm; and a frustoconical via in the build-up layer, wherein a first diameter of a first side of the frustoconical via at the first side of the build-up layer is smaller than a second diameter of a second side of the frustoconical via at the second side of the build-up layer.

Example 2 may include the substrate of example 1, wherein the second side includes one or more traces with a respective trace width of less than approximately 3 micrometers (μm) and a trace space of less than approximately 3 μm.

Example 3 may include the substrate of example 1, wherein the metal layer includes copper.

Example 4 may include the substrate of example 1, wherein the frustoconical via has an approximately linear slope between the first side of the frustoconical via and the second side of the frustoconical via.

Example 5 may include the substrate of any of examples 1-4, wherein the metal layer is exposed at the first side of the frustoconical via.

Example 6 may include the substrate of any of examples 1-4, wherein the build-up layer includes an organic resin and a hardener with an inorganic filler.

Example 7 may include a method comprising: coupling a polyethylene terephthalate (PET) layer, a protective metal layer, and a build-up layer to a metal layer such that the build-up layer is between the PET layer and the metal layer, and the PET layer is between the protective metal layer and the build-up layer; generating a frustoconical via in the protective metal layer, the PET layer, and the build-up layer; performing a desmear process such that the metal layer is exposed in the frustoconical via; and removing the PET layer from the build-up layer.

Example 8 may include the method of example 7, wherein removing the PET layer includes peeling the PET layer.

Example 9 may include the method of example 7, wherein removing the PET layer includes removing the protective metal layer.

Example 10 may include the method of example 7, wherein the desmear process is a plasma desmear process.

Example 11 may include the method of any of examples 7-10, wherein the PET layer and the protective metal layer are coupled to one another prior to coupling the PET layer and the protective metal layer to the build-up layer.

Example 12 may include the method of any of examples 7-10, wherein generating the frustoconical via includes laser drilling the frustoconical via.

Example 13 may include the method of any of examples 7-10, wherein the frustoconical via has a first diameter that is coplanar with the protective metal layer and that is larger than a second diameter of the frustoconical via that is coplanar with the build-up layer.

Example 14 may include the method of any of examples 7-10, wherein the PET film is a polyethylene naphthalate PET film.

Example 15 may include a package comprising: a die coupled with a substrate; wherein the substrate includes: a metal layer with a first side and a second side opposite the first side; a build-up layer with a first side coupled with the first side of the metal layer, and a second side opposite the first side, the second side having an average roughness (Ra) of between approximately 50 nanometers (nm) and approximately 100 nm and one or more traces with a trace width of less than approximately 3 micrometers (μm) and a trace space of less than approximately 3 μm; and a frustoconical via in the build-up layer, wherein a first diameter of a first side of the frustoconical via at the first side of the build-up layer is smaller than a second diameter of a second side of the frustoconical via at the second side of the build-up layer.

Example 16 may include the package of example 15, wherein the metal layer includes copper.

Example 17 may include the package of example 15, wherein the frustoconical via has an approximately linear slope between the first side of the frustoconical via and the second side of the frustoconical via.

Example 18 may include the package of any of examples 15-17, wherein the metal layer is exposed at the first side of the frustoconical via.

Example 19 may include the package of any of examples 15-17, wherein the build-up layer includes an organic resin and a hardener with an inorganic filler.

Example 20 may include the package of any of examples 15-17, wherein the die is a processor or a memory.