Field-effect transistors including multiple gate lengths

Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A semiconductor fin having a channel region, a nanowire arranged over the channel region of the semiconductor fin, a source/drain region connected with the channel region of the semiconductor fin and the nanowire, and a gate structure that overlaps with the channel region of the semiconductor fin and the nanowire. The nanowire has a first gate length, and the channel region of the semiconductor fin has a second gate length that is greater than the first gate length.

BACKGROUND

The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a field-effect transistor and methods of forming a structure for a field-effect transistor.

Device structures for a field-effect transistor generally include a source, a drain, and a gate electrode configured to switch carrier flow in a channel formed in a semiconductor body arranged between the source and drain. The semiconductor body and channel of a planar field-effect transistor are arranged beneath the top surface of a substrate on which the gate electrode is supported. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, the flow of carriers in the channel produces a device output current.

A fin-type field-effect transistor is a type of non-planar device structure that may be more densely packed in an integrated circuit than planar field-effect transistors. A fin-type field-effect transistor may include a fin, a source and a drain, and a gate electrode that wraps around a channel region located in the fin between the source and the drain. The wrapped arrangement between the gate structure and fin may improve control over the channel and reduce the leakage current when the fin-type field-effect transistor is in its ‘Off’ state in comparison with a planar transistor. This, in turn, may enable the use of lower threshold voltages than in planar transistors, and may result in improved performance and lowered power consumption.

Nanosheet field-effect transistors have been developed as a type of non-planar field-effect transistor that may permit additional increases in packing density in an integrated circuit. The body of a nanosheet field-effect transistor includes multiple nanosheet channel layers that are arranged in a layer stack. The nanosheet channel layers are initially arranged in a layer stack with sacrificial layers containing a material (e.g., silicon-germanium) that can be etched selectively to the material (e.g., silicon) constituting the nanosheet channel layers. The sacrificial layers are etched and removed in order to release the nanosheet channel layers and to provide spaces for the formation of a gate stack. Sections of the gate stack may surround all sides of the individual nanosheet channel layers in a gate-all-around arrangement. Similarly, nanowires may be substituted for nanosheets to form nanowire field-effect transistors.

Improved structures for a field-effect transistor and methods of forming a structure for a field-effect transistor are needed.

SUMMARY

In embodiments of the invention, a structure is provided for a field-effect transistor. The structure includes a semiconductor fin having a channel region, a nanowire arranged over the channel region of the semiconductor fin, a source/drain region connected with the channel region of the semiconductor fin and the nanowire, and a gate structure that overlaps with the channel region of the semiconductor fin and the nanowire. The nanowire has a first gate length, and the channel region of the semiconductor fin has a second gate length that is greater than the first gate length.

In embodiments of the invention, a method is provided for forming a field-effect transistor. The method includes forming a semiconductor fin and a nanowire arranged over a channel region of the semiconductor fin, epitaxially growing a source/drain region that is connected with the channel region of the semiconductor fin and the nanowire, and forming a gate structure that overlaps with the channel region of the semiconductor fin and the nanowire. The nanowire has a first gate length, and the channel region of the semiconductor fin has a second gate length that is greater than the first gate length.

DETAILED DESCRIPTION

With reference toFIG. 1and in accordance with embodiments of the invention, a semiconductor layer10and a semiconductor layer12are arranged in a patterned layer stack on a substrate14. The semiconductor layers10,12may be formed on the substrate14by an epitaxial growth process during which the composition is alternated as the semiconductor layers10,12are formed and the substrate14provides a crystal structure template for epitaxy. The substrate14may be composed of a semiconductor material, such as single-crystal silicon.

The semiconductor layer10is composed of a semiconductor material, and the semiconductor layer12is composed of a semiconductor material with a composition that is selected to be removed selective to the semiconductor materials of the semiconductor layer10and the substrate14. As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process. The respective compositions of the semiconductor layers10,12are chosen through growth conditions during epitaxial growth. In an embodiment, the semiconductor material constituting the semiconductor layer10may be single-crystal silicon (Si), and the semiconductor material constituting the semiconductor layer12may be single-crystal silicon-germanium (SiGe) that can be etched at a higher rate than single-crystal silicon due to its germanium content. In an embodiment, the germanium content of the semiconductor layer12may range from twenty percent (20%) to thirty-five percent (35%).

With reference toFIG. 2in which like reference numerals refer to like features inFIG. 1and at a subsequent fabrication stage of the processing method, the semiconductor layer10, the semiconductor layer12, and a portion of the substrate14may be patterned using, for example, self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), or direct-print single-exposure EUV patterning. The patterning of the portion of the substrate14forms fins16,18that project from the recessed top surface of the non-patterned portion of the substrate14and that have a given height relative to the non-patterned portion of the substrate14.

The patterning of the semiconductor layer10forms a nanowire11that is arranged over the fin16, and a nanowire13that is arranged over the fin18. The nanowire11may be aligned with the fin16, and the nanowire13may be aligned with the fin18. A portion of the patterned semiconductor layer12is arranged in a vertical direction between the nanowire11and the fin16, and another portion of the semiconductor layer12is arranged in a vertical direction between the nanowire13and the fin18.

The height or thickness of the nanowires11,13, which is established by the thickness of the semiconductor layer10, is less than the height of the fins16,18. The nanowires11,13may have a thickness that is equal to the thickness of the semiconductor layer10and a width that is established when the semiconductor layer10is patterned. The width of the nanowire11may be equal to its thickness and, similarly, the width of the nanowire13may be equal to its thickness. The nanowire11may have the same width as the fin16, and the nanowire13may have the same width as the fin18.

The utilization of nanowires, instead of nanosheets having a different aspect ratio due to a larger width, may have certain benefits. For example, a nanowire may outperform a nanosheet in electrostatics with lower drain-induced barrier lowering (DIBL) and a lower subthreshold swing (SSsat). For equivalent electrostatics, a nanowire may have a shorter gate length than a nanosheet.

Shallow trench isolation regions20may be formed that surround a lower portion of each of the fins16,18. The shallow trench isolation regions20may be composed of a dielectric material, such as an oxide of silicon (e.g., silicon dioxide (SiO2)), that is deposited by chemical vapor deposition (CVD) and recessed with an etch-back process.

A thin dielectric layer22is formed on the nanowires11,13and fins16,18, and may be composed of, for example, silicon dioxide (SiO2). A blanket layer19is formed over the nanowires11,13and fins16,18and directly on the thin dielectric layer22. The blanket layer19may be composed of a sacrificial dummy gate material, such as amorphous silicon (α-Si), that is deposited by, for example, chemical vapor deposition (CVD) and planarized using, for example, chemical mechanical polishing (CMP). A hardmask layer21is formed on the blanket layer19. The hardmask layer21may be composed of a dielectric material, such as silicon nitride (Si3N4), silicon dioxide (SiO2), etc., that is deposited by, for example, chemical vapor deposition (CVD).

With reference toFIGS. 3, 4, 4A, 4Bin which like reference numerals refer to like features inFIG. 2and at a subsequent fabrication stage of the processing method, multiple sacrificial gate structures23,24,25are formed from the blanket layer19. The sacrificial gate structures23,24,25overlap with and wrap around the nanowires11,13and fins16,18. Sections of the sacrificial gate structures23,24,25are also arranged along their respective lengths on the shallow trench isolation regions20. The sacrificial gate structures23,24,25have a spaced-apart arrangement along the length of the nanowires11,13and fins16,18, and the sacrificial gate structures23,24,25may be aligned transverse to the nanowires11,13and fins16,18.

The sacrificial gate structures23,24,25may be formed by patterning the hardmask layer21with an etching process, such as reactive ion etching (ME), to form hardmask caps27arranged on the blanket layer19. The pattern is then transferred from the hardmask caps27to the blanket layer using an etching process, such as reactive ion etching (ME). Following the etching process, the hardmask caps27are arranged over the sacrificial gate structures23,24,25. The etching process forming the sacrificial gate structures23,24,25is selective to the dielectric material constituting the dielectric layer22that encapsulates the nanowires11,13, the fins16,18, and the semiconductor layer12.

Each of the sacrificial gate structures23,24,25includes multiple width dimensions arranged along its height. Specifically, over the shallow trench isolation regions20and adjacent to the respective sidewalls of the fins16,18, each of the sacrificial gate structures23,24,25includes an upper section28with a critical dimension or width dimension CD1, a lower section30with a critical dimension or width dimension CD2, and an intermediate section29of varying width arranged in a vertical direction between the upper section28and the lower section30. The width dimension CD2of the lower section30is greater than the width dimension CD1of the upper section28. The intermediate sections29taper in the vertical direction from the width dimension CD2to the width dimension CD1. The intermediate section29of the sacrificial gate structures23,24,25is arranged to be at the same height in the vertical direction as the portion of to semiconductor layer12over each of the respective fins16,18. Over the respective top surfaces of the fins16,18and the semiconductor layers12,13, each of the sacrificial gate structures23,24,25only includes the upper section28of the narrower width dimension CD1.

The multiple widths of the sacrificial gate structures23,24,25are provided by modulating the etching process to change the lateral component of the etch rate as a function of time. The modulation may be generating by adjusting the bias applied on the chuck holding the substrate14during the etching process, the chemistry of the etching process, and/or polymerization during the etching process. The portion of the etching process with the higher lateral etch rate component forms the upper sections28and the portion of the etching process with the lower lateral etch rate component forms the lower sections30. The tapering of the intermediate section29of each of the sacrificial gate structures23,24,25reflects the transition between the portion of the etching process with the higher lateral etch rate and the portion of the etching process with the lower lateral etch rate component.

With reference toFIGS. 5, 5Ain which like reference numerals refer to like features inFIGS. 4, 4Aand at a subsequent fabrication stage of the processing method, sidewall spacers32are formed on the sidewalls of the sacrificial gate structures23,24,25. The sidewall spacers32may be formed by depositing a conformal layer of a low-k dielectric material, such as SiBCN, and etching the conformal layer with a directional etching process, such as reactive ion etching (ME). The conformal layer and the sidewall spacers32formed from the conformal layer follow the tapered contour of the sidewalls provided by the multiple-width sections28,29,30of the sacrificial gate structures23,24,25.

With reference toFIGS. 6, 6Ain which like reference numerals refer to like features inFIGS. 5, 5Aand at a subsequent fabrication stage of the processing method, trenches34are formed that extend through the nanowires11,13, the semiconductor layer12, and the fins16,18by a self-aligned etching process in which the respective sacrificial gate structures23,24,25operate as an etch mask. The self-aligned etching process, which may be a reactive ion etching (ME) process, may utilize one or more etch chemistries to etch the different semiconductor materials. The trenches34include sections of different width dimensions that arranged over the trench depth and that are provided by modulating the etching process, which may be a reactive ion etching (ME) process. The modulation may be generating by adjusting the bias applied on the chuck holding the substrate14during the etching process, the chemistry of the etching process, and/or sidewall polymerization during the etching process to adjust the lateral etch component.

The nanowire11and the section of the semiconductor layer12over the fin16are respectively divided into multiple nanowires11and multiple sections of semiconductor layers12of respective shorter lengths by the trenches34. Similarly, the nanowire13and the section of the semiconductor layer12over the fin18are respectively divided into multiple nanowires13and multiple sections of the semiconductor layer12of shorter lengths by the trenches34. The divided nanowires11,13have a length dimension L1that coincides in a vertical direction with the widest portion of the trenches34. The narrowest portions of the trenches34are located in the fins16,18and form channel regions36in the fins16,18. Each of channel regions36has a length dimension L2that is greater than the length dimension L1of the nanowires11,13. The trenches34taper between the nanowires11and the channel regions36in the fins16and between the nanowires13and the channel regions36in the fins18over the height of the sections of the semiconductor layer12. The sections of the semiconductor layer12taper inversely from the length dimension L1to the length dimension L2.

The tapered sections of the semiconductor layer12and the tapered intermediate sections29of the sacrificial gate structures23,24,25are aligned in a lateral direction. In an embodiment, the upper and lower surfaces of the tapered sections of the semiconductor layer12may be respectively coplanar with the upper and lower surfaces of the tapered intermediate sections29of the sacrificial gate structures23,24,25. In an embodiment, the taper angle of the sections of the semiconductor layer12may be equal to the taper angle of the intermediate sections29of the sacrificial gate structures23,24,25. The channel regions26in the fins16,18and the lower sections30of the sacrificial gate structures23,24,25are aligned in a lateral direction. The upper sections28of the sacrificial gate structures23,24,25are arranged to overlap with the nanowires11,13to the level of the top surfaces of the fins16,18.

With reference toFIGS. 7, 7Ain which like reference numerals refer to like features inFIGS. 6, 6Aand at a subsequent fabrication stage of the processing method, the sections of the semiconductor layer12are laterally recessed relative to the nanowires11,13and channel regions36of the fins16,18with a dry or wet isotropic etching process that etches the semiconductor material constituting the semiconductor layer12selective to the semiconductor materials constituting the nanowires11,13and the fins16,18. The lateral recessing of the sections of the semiconductor layer12generates indents44because of the etch selectivity of the isotropic etching process. The length dimension of the sections of the semiconductor layer12at the nanowires11,13is less than the length dimension L1of the nanowires11,13. In an embodiment, the recessed sections of the semiconductor layer12may taper in the vertical direction from a width dimension equal to the width dimension CD2of the lower sections30of the sacrificial gate structures23,24,25at the top surface of the channel regions36to a width dimension equal to the width dimension CD1of the upper sections28of the sacrificial gate structures23,24,25at the nanowires11,13.

With reference toFIG. 8, 8Ain which like reference numerals refer to like features inFIGS. 7, 7Aand at a subsequent fabrication stage of the processing method, inner spacers46are subsequently formed in the indents44and are arranged adjacent to the recessed ends of the sections of the semiconductor layer12. The inner spacers46may be formed by depositing a conformal layer (not shown) composed of a dielectric material, such as silicon nitride (Si3N4) deposited by atomic layer deposition (ALD), that fills the indents44by pinch-off. The conformal layer outside of the indents44is removed with an etching process, such as a wet chemical etching process using a heated solution containing phosphoric acid (H3PO4), which leaves the inner spacers46resident in the indents44.

With reference toFIGS. 9, 9Ain which like reference numerals refer to like features inFIGS. 8, 8Aand at a subsequent fabrication stage of the processing method, source/drain regions48are formed by the epitaxial growth of an epitaxial semiconductor material. The semiconductor material of the source/drain regions grows from growth seeds provided by the nanowires11,13and the channel regions36of the fins16,18and grows from the substrate14at the bottom of the trenches34. The different growth fronts merge during epitaxial growth in the spaces between adjacent channel regions36to form the source/drain regions48. As used herein, the term “source/drain region” means a doped region of semiconductor material that can function as either a source or a drain of a field-effect transistor.

The semiconductor material of the epitaxial semiconductor layer may be heavily doped to have either p-type electrical conductivity or n-type electrical conductivity. In an embodiment, the epitaxial semiconductor layer may be doped during epitaxial growth with an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P) and/or arsenic (As)) that provides n-type electrical conductivity. In an alternative embodiment, the semiconductor material of the epitaxial semiconductor layer may be doped during epitaxial growth with a p-type dopant from Group III of the Periodic Table (e.g., boron (B), aluminum (Al), gallium (Ga), and/or indium (In)) that provides p-type electrical conductivity.

The semiconductor material forming the source/drain regions48is physically constrained during epitaxial growth to reproduce the shape of the trenches34. Each source/drain region48includes an upper portion37that is arranged above the sections of the semiconductor layer12, a lower portion39that is arranged below the sections of the semiconductor layer12and that is narrower than the upper portion, and an intermediate portion38that is tapered to provide a transition between the wider upper portion and the narrower lower portion. The intermediate portions38are aligned in a lateral direction with the sections of the semiconductor layer12. The shape of the sacrificial gate structures23,24,25inversely mirrors the shape of the trenches34and source/drain regions48. The wider upper portion37of each source/drain region48is arranged above the tapered intermediate portion38of each source/drain region48, and the wider lower section30of the sacrificial gate structures23,24,25is arranged below the narrower upper section28. The tapered intermediate portion38of each source/drain region48is aligned in a lateral direction with the intermediate sections29of the sacrificial gate structures23,24,25.

With reference toFIGS. 10, 10Ain which like reference numerals refer to like features inFIGS. 9, 9Aand at a subsequent fabrication stage of the processing method, an interlayer dielectric layer50is deposited and planarized by chemical mechanical polishing (CMP). The interlayer dielectric layer50may be composed of a dielectric material, such as silicon dioxide (SiO2). The planarization of the interlayer dielectric layer50may remove the hardmask caps27from the sacrificial gate structures23,24,25and thereby reveal the sacrificial gate structures23,24,25.

After forming the interlayer dielectric layer50, the sacrificial gate structures23,24,25are removed with an etching process to form spaces49, and the thin dielectric layer22is stripped from the nanowires11,13, the fins16,18, and the sections of the semiconductor layer12with an etching process. The removal of the sacrificial gate structures23,24,25and the thin dielectric layer22exposes the sections of the semiconductor layer12, which are then removed with the same or a different etching process to form spaces51. The nanowires11,13, which are respectively arranged over the channel regions36of the fins16,18, are released by the etching process(es).

The dimensions of the spaces49may be equal to the dimensions of the sacrificial gate structures23,24,25, and the dimensions of the spaces51may be equal to the dimensions of the sections of the tapered sections of the semiconductor layer12. The spaces49merge with the spaces51around the sides of the nanowires11,13such that each of the merged spaces49,51extend about the circumference of one of the nanowires11,13. Over the shallow trench isolation regions20, the spaces49have stacked dual-width sections that extend to the shallow trench isolation regions20. Specifically, each space49has a wider lower section that is arranged in a vertical direction between a narrower upper section and the shallow trench isolation regions20.

Over the nanowires11,13and fins16,18, the narrower upper section of each space49extends to the upper surface of the nanowires11,13and along the side edges of the nanowires11,13. Spaces51are arranged in a vertical direction between the nanowires11and the channel regions36of the fin16and between the nanowires13and the channel regions of the fin18. The spaces51may have a height in a vertical direction equal to the thickness of the removed sections of the semiconductor layer12. The inner spacers46bound the spaces51in a lateral direction. The recessing of the sections of the semiconductor layer12forming the indents44may be used to select the lateral dimensions of the spaces51.

With reference toFIGS. 11, 11Ain which like reference numerals refer to like features inFIGS. 10, 10Aand at a subsequent fabrication stage of the processing method, gate structures52are formed in the spaces49,41as part of a replacement metal gate process to fabricate a multiple-gate field-effect transistor. Each of the gate structures52may be formed from a gate stack that includes an interface layer, a gate dielectric layer, and a metal gate electrode. The interface layer coats the exterior surfaces of the nanowires11,13and the fins16,18, and the gate dielectric layer is arranged in the gate stack between the metal gate electrode and the interface layer. Self-aligned contact (SAC) caps54composed of a dielectric material, such as silicon nitride (Si3N4), are formed in the spaces between the sidewall spacers32over each of the gate structures52.

The interface layer of the gate structures52may be composed of a dielectric material, such as an oxide of silicon (e.g., silicon dioxide (SiO2)). The gate dielectric layer of the gate structures52may be composed of a dielectric material, such as a high-k dielectric material like hafnium oxide (HfO2). The metal gate electrode of the gate structures52includes one or more conformal barrier metal layers and/or work function metal layers, such as layers composed of titanium aluminum carbide (TiAlC) and/or titanium nitride (TiN), and a metal gate fill layer composed of a conductor, such as tungsten (W). The metal gate electrode of the gate structures52may include different combinations of the conformal barrier metal layers and/or work function metal layers. For example, the metal gate electrode may include conformal work function metal layers characteristic of a p-type field-effect transistor. As another example, the metal gate electrode may include conformal work function metal layers characteristic of an n-type field-effect transistor.

The gate structures52have multiple widths dimensions arranged along their respective heights that reflect the multiple width dimensions of the removed and replaced sacrificial gate structures23,24,25and the removed and replaced sections of the semiconductor layer12. Over the shallow trench isolation regions20and adjacent to the respective sidewalls of the fins16,18, each of the gate structures52includes an upper section60with a length dimension GL1, a lower section62with length dimension GL2that is greater than length dimension GL1, and a tapered intermediate section61arranged in a vertical direction between the lower section62and the upper section60. The lower sections62are arranged adjacent to the side edges of the channel regions36of the fins16,18such that the channel regions36have a gate length equal to the length dimension GL2. The gate length GL2may be equal to the width dimension CD2of the section30of the sacrificial gate structures23,24,25. The gate length GL2represents the effective length of the distance in the channel regions36of the fins16,18between the nearest edges of the source/drain regions48.

Over the nanowires11,13and fins16,18, each of the gate structures52includes the upper section60with a length dimension GL1over the nanowires11,13and a tapered lower section64. The tapered lower sections64, which are formed in the spaces51, are arranged in the vertical direction between the channel regions36of the fins16,18and the nanowires11,13. Each of the tapered lower sections64may have the length dimension GL1at the nanowires11,13and the length dimension GL2at the top surface of the channel regions36that is greater than the length dimension GL1. The nanowires11,13may have a gate length on all sides equal to the length dimension GL1. The gate length GL1represents the effective length of the distance in the nanowires11,13between the nearest edges of the source/drain regions48. At their respective top surfaces, the channel regions36may have a gate length equal to the length dimension GL2, which is consistent with the gate length at their side edges.

In an alternative embodiment, the recessing of the sections of the semiconductor layer12forming the indents44may be used to select the lateral dimensions of the spaces51such that the gate lengths at the tapered section64differ from the length dimensions GL1and GL2.

The nanowires11,13and the fins16,18collectively form a hybrid field-effect transistor that includes a fin-type field-effect transistor (FinFET) and a nanowire field-effect transistor over the FinFET. The nanowires11,13and the fins16,18are connected with the same source/drain regions48. Each of the gate structures52includes a section that is wrapped about the nanowires11,13in a gate-all-around (GAA) design. As described above, the nanowires11,13, where surrounded by the gate structures52, may have a gate length GL1that is less than the gate length GL2for the channel regions36of the fins16,18where surrounded on multiple sides by the gate structures52. The different gate lengths of the nanowires11,13and the channel regions36of the fins16,18are produced by the modulated etching processes forming the dual-width trenches34and the dual-width sacrificial gate structures23,24,25and the removal of the sections of the semiconductor layer12.

With reference toFIGS. 12, 12Ain which like reference numerals refer to like features inFIGS. 11, 11Aand at a subsequent fabrication stage of the processing method, trench silicide (TS) contacts56are formed that extend vertically to the source/drain regions48. The TS contacts56may include a metal silicide, such as titanium silicide (TiSi2), tungsten silicide (WSi2), nickel silicide (NiSi), or cobalt silicide (CoSi2) deposited by chemical vapor deposition (CVD), as well as an overlying conductor, such as tungsten (W) or cobalt (Co) that may also be deposited by chemical vapor deposition (CVD). The TS contacts56may be planarized by chemical mechanical polishing (CMP) to the level of the caps54.

The increased width of the upper portion37of the source/drain regions48may permit the size of the TS contacts56to be increased without incurring a loss of effective width (Weff) that is correlated with the transistor on-current. The contact resistance between the source/drain regions48and TS contacts56may be improved because the effective surface area of the source/drain regions48available for contact by the TS contacts56is increased in comparison with conventional source/drain regions in a stacked nanowire/fin field-effect transistor lacking the multiple widths.

The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.

A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.