Chiplets 3D SoIC system integration and fabrication methods

A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

BACKGROUND

In the packaging of integrated circuits, multiple chiplets may be bonded to a same larger bottom chip. The chiplets may need to communicate to each other. Conventionally, the communication was made through the through-silicon vias that penetrate through the substrate of the bottom chip, and further through the interconnect structure in the bottom chip. With the increasingly demanding requirement for the integrated circuits, such connection scheme cannot meet the demanding requirements. For example, the wiring paths of the packages adopting this scheme are long, and may not be able to meet the high power-efficiency and low latency requirements.

DETAILED DESCRIPTION

A package including backside bridge structures and the method of forming the same are provided in accordance with some embodiments. In accordance with some embodiments of the present disclosure, the backside bridge structures are formed on the backside of a first-tier chip. A plurality of second-tier chips are bonded to the first-tier chip through a face-to-back bonding scheme, and electrical paths are formed between the second-tier chips. The electrical paths include the pre-formed backside bridge structures in the first-tier chip. With the bridge structures formed on the backside of the bottom chip, the electrical paths are short, and hence the resulting package may meet the power efficiency and latency requirements. Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

FIGS. 1-9 and 12illustrate the cross-sectional views of intermediate stages in the formation of a package in accordance with some embodiments of the present disclosure. The corresponding processes are also reflected schematically in the process flow200as shown inFIG. 21.

FIG. 1illustrates the cross-sectional view of wafer20. In accordance with other embodiments, wafer20is device wafer, which includes integrated circuits28therein. Integrated circuits28may include active devices such as transistors, and/or passive devices such as capacitors, resistors, inductors, and/or the like. In accordance with some embodiments, wafer20is an interposer wafer, which is free from active devices, and may or may not include passive devices.

Wafer20includes substrate26, and through-vias30(sometimes referred to as through-silicon vias or through-substrate vias) extending into substrate26. The active devices such as transistors in integrated circuits28may extend into substrate26. Throughout the description, the side of the semiconductor substrate26having the active devices, and/or the side from which through-vias30extend into semiconductor substrate26, is referred to as the front side of substrate26, and the opposing side is referred to as the backside of substrate26. Accordingly, the side of wafer20on the front side of substrate26is referred to as the front side of wafer20, and the opposing side is referred to as the backside of wafer20. In the example shown inFIG. 1, the top side is the front side of substrate26and wafer20, and the bottom side is the back side. In accordance with some embodiments of the present disclosure, substrate26is a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, a carbon-doped silicon substrate, a III-V compound substrate, or the like. When substrate26is formed of a semiconductor material, through-vias30are encircled by dielectric rings, which electrically insulate through-vias30from substrate26. Through-vias30extend to an intermediate level between the top surface and the bottom surface of substrate26. Through-vias30are conductive, and may be formed of copper, aluminum, tungsten, or the like.

In accordance with some embodiments, dielectric layer32(which may be an inter-layer dielectric) is formed over substrate26. Through-vias30may extend into dielectric layer32in accordance with some embodiments. The top surfaces of through-vias30may be level with the top surface of substrate26, level with the top surface of dielectric layer32, or may be level with the top surface of any dielectric layer over dielectric layer32.

Wafer20includes chips22, which are parts of the un-sawed wafer20. Chips22may be device chips, interposer chips, or the like. In accordance with some embodiments, chips22are input/output (IO) chips, computing chips (such as Central Processing Unit (CPU) chips, Graphics Processing Unit (GPU) chips, Deep Trench Capacitor (DTC) interposers, Integrated Voltage Regulator (IVR) chips, or the like. Chips22may also be any other types of chips that include transistors and passive devices therein.

Over dielectric layer32may reside interconnect structure34, which includes dielectric layers36and conductive features38formed in dielectric layers36(also referred to as Inter-metal Dielectrics (IMDs)). It is appreciated that there may be a plurality of dielectric layers36and a plurality of layers of conductive features38, which are represented by the illustrated dielectric layers36and conductive features38. In accordance with some embodiments, the conductive features38include metal lines and vias interconnecting the metal lines in neighboring layers. The metal lines at a same level are collectively referred to as a metal layer hereinafter. In accordance with some embodiments of the present disclosure, interconnect structure34includes a plurality of metal layers interconnected through vias. In accordance with some embodiments of the present disclosure, dielectric layers36are formed of low-k dielectric materials. The dielectric constants (k values) of the low-k dielectric materials may be lower than about 3.0, for example. Dielectric layers36may be formed of or comprise a carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. In accordance with some embodiments of the present disclosure, the formation of dielectric layers36includes depositing a porogen-containing dielectric material and then performing a curing process to drive out the porogen, and hence the remaining dielectric layers36are porous. Conductive features38may be formed of copper or copper alloys, which may be formed of damascene (single damascene and dual damascene processes).

Conductive features38include damascene structures, which may further include single damascene structures and dual damascene structure. It is noted that conductive features38are illustrated schematically, and the illustrated conductive features38may represent a plurality of layers of damascene structures. Example single damascene structures may have the similar structure and formed of similar materials as conductive features50shown inFIG. 10. Example dual damascene structures may have the similar structure and formed of similar materials as the dual damascene structures60/62as shown inFIG. 10. Furthermore, in a dual damascene structure, the conductive line is on the upper side of the respective via(s) in the same dual damascene structure.

Dielectric layer39and Under-Bump Metallurgies (UBMs)40are formed over and electrically coupling to conductive features36. In accordance with some embodiments, solder regions42are formed on UBMs40. In accordance with alternative embodiments, solder regions42are formed at a later stage, for example, after the process as shown inFIG. 9, or after the bonding and encapsulation processes as shown inFIG. 12, and possibly before the sawing process as shown inFIG. 12.

Referring toFIG. 2, a backside grinding process is performed to remove a portion of substrate26, until through-vias30are revealed. The respective process is illustrated as process202in the process flow200as shown inFIG. 21. Next, as shown inFIG. 3, substrate26may be recessed slightly (for example, through etching), so that through-vias30protrude out of the back surface of substrate26. The respective process is illustrated as process204in the process flow200as shown inFIG. 21. Next, a dielectric layer44is deposited, followed by a planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process to re-expose through-vias30, forming the structure shown inFIG. 4. The respective process is illustrated as process206in the process flow200as shown inFIG. 21. In the resulting structure, through-vias30penetrate through both of substrate26and dielectric layer44. In accordance with some embodiments, dielectric layer44is formed of or comprises silicon oxide, silicon nitride, or the like.

Subsequently, a backside interconnect structure49(FIG. 9), which includes one or a plurality of metal layers and bridge structures formed therein, is formed. The backside interconnect structure49may include a single damascene structure only, a dual damascene structure only, or the combinations of one or a plurality of single damascene structures and one or a plurality of dual damascene structures.FIGS. 5 and 6illustrate the formation of dielectric layer46and conductive features50using a single damascene process in accordance with some embodiments. In accordance with alternative embodiments, the formation of dielectric layer46and conductive features50is skipped, and the vias in the subsequently formed dual damascene processes are in direct contact with through-vias30. Referring toFIG. 5, dielectric layer46is deposited and then etched. The respective process is illustrated as process208in the process flow200as shown inFIG. 21. In accordance with some embodiments, dielectric layer46is formed of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicate glass, or the like. The material of dielectric layer46may be different from the material of dielectric layer44so that in the subsequent etching of dielectric layer46, dielectric layer44is not etched-through. A lithography process is performed to etch dielectric layer46, so that openings48are formed. Through-vias30are exposed to openings48.

Referring toFIG. 6, conductive features50are formed. The respective process is illustrated as process210in the process flow200as shown inFIG. 21. Conductive features50may include the metal pads for landing the subsequently formed vias, and may or may not include traces for rerouting electrical connections. In accordance with some embodiments, the formation of conductive features50includes depositing a conformal diffusion barrier layer (similar to layer50A inFIG. 10), plating a metallic material (such as copper, similar to material50B inFIG. 10) over the diffusion barrier layer, and performing a planarization process such as a CMP process or a mechanical grinding process to remove excess materials.

It is appreciated that dielectric layer46and conductive features50as shown inFIG. 6may be formed, or the formation of these features may be skipped in accordance with other embodiments. In the embodiments in which the formation processes of dielectric layer46and conductive features50are skipped, the subsequent vias will be in direct contact with through-vias30, as is shown inFIG. 12as a example.

FIGS. 7 through 9illustrate the formation of bridge structures through a dual damascene process. It is appreciated that although single-layer bridge structures are illustrated as an example, there may be bridge structures including a plurality of layers of single and/or dual damascene structures, depending on the desirable count of bridge structures for interconnecting neighboring chips. Referring toFIG. 7, etch stop layer52and dielectric layer54are formed through deposition. The respective process is illustrated as process212in the process flow200as shown inFIG. 21. In accordance with some embodiments, etch stop layer52is formed of silicon nitride, silicon carbide, silicon oxynitride, silicon oxy-carbo-nitride, or the like. Next, dielectric layer54is deposited. Dielectric layer54may be formed of a silicon-containing dielectric material, which may be silicon oxide, silicon nitride, silicon oxynitride or the like. When dielectric layer54is not a top dielectric layer in wafer20, and there are more dielectric layer(s) formed over dielectric layer54, dielectric layer54may be formed of a low-k dielectric material. Otherwise, dielectric layer54may be formed of a non-low-k dielectric material as aforementioned. In accordance with some embodiments, dielectric layer54includes sub layer54A, and sub layer54B over sub layer54A, wherein sub layers54A and54B are formed of different materials, so that sub layer54A is used for forming via openings, and sub layer54B is used for forming trenches. Sub layer54A is further used to stop the etching for forming the trenches. In accordance with alternative embodiments, an entirety of dielectric layer54is formed of a homogeneous material.

Referring toFIG. 8, trenches56and via openings58are formed. The respective process is illustrated as process214in the process flow200as shown inFIG. 21. In accordance with some embodiments in which dielectric layer54includes sub layers54A and54B, the formation of trenches56is performed using dielectric layer54A as an etch stop layer to etch dielectric layer54B. In accordance with alternative embodiments in which dielectric layer54is a homogeneous layer, time mode is used to control when to stop the etching for forming trenches56, so that trenches56may stop at an intermediate level between the top surface and the bottom surface of dielectric layer54. Via openings58are formed to penetrate through sub layer54A (if any) and etch stop layer52, so that conductive features50are revealed.

FIG. 9illustrates the formation of bridge structures64, which include metal lines60and possibly vias62in accordance with some embodiments. Metal line60and vias62in combination form dual damascene structures. The respective process is illustrated as process216in the process flow200as shown inFIG. 21. Some details of example dual damascene structures may be found referring toFIG. 10, which illustrates a magnified view of a single damascene structure and a dual damascene structure. In accordance with some embodiments, the formation of metal lines60and vias62may include depositing a conformal diffusion barrier layer (refer to layer61A inFIG. 10), plating a metallic material (such as copper, refer to61B inFIG. 10) over the diffusion barrier layer, and performing a planarization process such as a CMP process or a mechanical grinding process to remove excess materials. The top surfaces of a metal line60, which also comprises bond pads60A and metal trace60B, are coplanar with the top surface of dielectric layer54.

In accordance with some embodiments, dielectric layer54and metal lines60are the top features of wafer20, and the top features are used for bonding to package components such as package components68as shown inFIGS. 12 through 16. In accordance with alternative embodiments, additional dielectric layers may be formed, and single or dual damascene structures may be formed over dielectric layer54and electrically connecting to metal lines60. The structures and the formation processes may be similar to what have been shown and discussed referring toFIGS. 5 through 9, and hence are not repeated herein.

Some of metal lines60(and possibly vias62) form bridge structures64, which are used for the electrical connection between two chips, as shown inFIGS. 12 through 16. Referring toFIG. 11, two example bridge structures64are illustrated, with each of the bridge structures including two portions60A, which are also referred to as bond pads60A, and portion60B, which is also referred to as metal trace60B. Metal trace60B interconnects bond pads60A. InFIG. 11, metal trace60B shown on the left side is narrower than the respective metal pads60A, and the metal trace60B shown on the right side has a same width as the respective metal pads60A.

Referring back toFIG. 9, a bridge structure64includes two bond pads60A, and an electrical path interconnecting bond pads60A. In the example embodiment as shown inFIG. 9, the electrical path includes metal trace60B. In accordance with alternative embodiments in which there are two or more metal layers (and the corresponding damascene structures) on the backside of wafer20, instead of having the metal trace in the same layer as the bond pads60A, the electrical paths may include two vias62, and an underlying metal trace (not shown) in an underlying metal layer, with the underlying metal trace electrically intercoupling the two vias62. In an example embodiment, vias62land on the respective underlying metal pads, which are interconnected through a metal trace in between.

In accordance with some embodiments, for example, when the bridge structure includes the metal trace60B in the top metal layer, the underlying vias62may or may not be formed, depending on the requirements of circuits. In accordance with some embodiments, there are two vias62, two conductive features50, and two through-vias30(as shown inFIG. 9) underlying and electrically connecting to the same bridge structure64. In accordance with alternative embodiments, there is one via62, one conductive feature50, and one through-via30(as shown inFIG. 9) electrically connecting to bridge structure64. For example, one of vias62, one of conductive features50, and one of through-vias30are illustrated as being dashed to indicate these features may or may not be formed. In yet alternative embodiments, a bridge structure is not connected directly to any underlying via62, conductive feature50, and through-vias30. Whether a bridge structure has any underlying connecting via62, conductive feature50and through via30depends on the circuit requirements, and a chip22may include any combination of these structures.

FIGS. 12 through 16illustrate the formation of packages66based on wafer20in accordance with some embodiments. The wafer20and the corresponding chip22as shown inFIGS. 12 through 16are illustrated schematically, and the details of wafer20may be found referring to the discussion ofFIG. 1 through 9. Furthermore, the solder regions42inFIG. 9are not shown inFIGS. 12 through 16, while the solder regions may or may not be formed in the packages shown inFIGS. 12 through 16. The formation of packages66are briefly discussed referring toFIG. 12, and the disclosure can also be applied to the formation of the packages66as shown inFIGS. 13 through 16. Throughout the description, chips22are referred to as first-tier chips.

Referring toFIG. 12, second-tier chips68are bonded to the first-tier chip22in wafer20. The respective process is illustrated as process218in the process flow200as shown inFIG. 21. Second-tier chips68may be chips selected from, and not limited to, computing chips, volatile memories such as Static Random Access Memories (SRAMs), Non-Volatile Memories (NVMs) such as Dynamic Random Access Memories (DRAMs), Artificial Intelligence (AI) accelerators, or the like. Second-tier chips68may include digital chips and analog chips. Furthermore, second-tier chips68may be stacked chips (cubes) or single chips. For example, SRAM chips, DRAM chips, and NVM chips may be stacked to form memory cubes. The memory cubes may not have controllers therein. In accordance with some embodiments, the controllers, like other second-tier chips68, may be placed aside of the memory cubes. The controllers are signally connected to, and communicate with, the memory cubes through bridge structures64. The integrated circuit devices (not shown) are formed in second-tier chips68, which integrated circuit devices may include transistors formed on the front side (the side facing down) of the corresponding substrate76.

In accordance with some embodiments, second-tier chips68include surface dielectric layer70, and bond pads72in surface dielectric layer70, with the surfaces of surface dielectric layer70and bond pads72being coplanar. In accordance with some embodiments, dielectric layer70is formed of silicon oxide. Dielectric layer70may also be formed of other silicon-containing dielectric material such as silicon nitride, silicon carbide, silicon oxynitride, silicon oxy-carbo-nitride, or the like. Bond pads72may be formed of copper or a copper alloy in accordance with some embodiments. Second-tier chips68may also include semiconductor substrates76, and interconnect structures74between the semiconductor substrates76and the corresponding bond pads72. Interconnect structures74also include dielectric layers, and metal lines and vias, which are not shown in details. Some of the bond pads72in neighboring second-tier chips68are bonded to opposite ends of bridge structures64, and are electrically connected to each other through bridge structures64.

In accordance with some embodiments, through-vias78are formed to extend into semiconductor substrate76. In accordance with other embodiments, through-vias78are not formed in the second-tier chips68. It is appreciated that since second-tier chips68are top-tier chips in accordance with these embodiments, through-vias78are not used for electrical functions, while they may be formed for, for example, helping heat dissipation. Accordingly, package66may be (or may not be) polished, until through-vias78are exposed, and a heat sink may be placed over and contacting through-vias78, so that the heat generated in second-tier chips68and first-tier chip22may be dissipated to the heat sink effectively. The through-vias78in accordance with these embodiments may be electrically floating or electrically grounded in accordance with some embodiments. Through-vias78are electrically and physically insulated from semiconductor substrate76by insulation layers79. In subsequentFIGS. 13 through 20, insulation layers79are not illustrated, while they still exist.

The bonding of second-tier chips68to the first-tier chip22may be through face-to-back bonding in accordance with some embodiments, in which the front sides of second-tier chips68are bonded to the backside of first-tier chip22. In accordance with some embodiments, the bonding is performed through hybrid bonding, in which the dielectric layers70of second-tier chips68are bonded to dielectric layer44in first-tier chip22through fusion bonding, and bond pads72are bonded to metal pads60A through direct metal-to-metal bonding. The fusion bonding may be achieved through the generation of Si—O—Si bonds, with Si in one of dielectric layers70and44, and O—Si in the other one of dielectric layers70and44. In the top view of the bonded structure, first-tier chip22is larger than at least one, and possibly the combination of two or more of the overlying second-tier chips68. First-tier chip22may extend laterally beyond the combined regions including all of the second-tier chips68bonded thereon.

In accordance with some embodiments, the dielectric layer54including the dual damascene structures60/62is a single layer formed of a homogeneous material. In accordance with alternative embodiments, the dielectric layer54including the dual damascene structures60/62therein is a dual layer including sub layers54A and54B (refer toFIG. 9).

After the bonding of second-tier chips68to first-tier chip22, gap-filling material80is applied to fill the gaps between, and to encapsulate, second-tier chips68. The respective process is illustrated as process220in the process flow200as shown inFIG. 21. Gap-filling material80may be formed of or comprises an organic material such as molding compound, a molding underfill, an epoxy, a resin, or the like. Alternatively, gap-filling material80may also be formed of an inorganic material(s) such as silicon nitride, silicon oxide, or the like. For example, gap-filling material may include a silicon nitride layer as an adhesion layer (which is also a liner), and a silicon oxide layer on the silicon nitride layer. The applied gap-filling material80, if formed in a flowable form, is then cured. A planarization process such as a CMP process or a mechanical grinding process is then performed to level the top surface of gap-filling material80. In accordance with some embodiments, the planarization process is stopped when there is still a portion of gap-filling material80covering second-tier chips68, as shown inFIG. 12. In accordance with alternative embodiments, the planarization process is performed until through-vias78are exposed. In accordance with yet other embodiments, the planarization process is performed after isolation layers79, which insulate through-vias78from substrate26, are exposed, but before the top portions of isolation layers79are polished-through. Accordingly, through-vias78are covered and surrounded by isolation layers79.

The bonding of second-tier chips68to wafer20may be at wafer level, wherein a plurality of groups of second-tier chips68are bonded to the corresponding first-tier chips22. A sawing process may be performed to saw-through gap-filling material80, so that a plurality of packages66are formed. The respective process is illustrated as process222in the process flow200as shown inFIG. 21.

FIG. 12illustrates electrical path82, which includes bridge structure64. Electrical path82is used for the electrical connection and signal communication between neighboring second-tier chips68. Furthermore, bridge structure64may be used for transferring and redistributing power. For example, electrical path82shows an example power transferring route, wherein power is provided by a power source (not shown) that is either inside or underlying first-tier chip22. For example, chip22may be an IVR chip in accordance with some embodiments. The power is passed through one of through-vias30, and is fed to second-tier chip68A. The power is further transferred in the interconnect structure74in second-tier chip68A, and to bridge structure64, so that power is provided to the second-tier chip68B. Through this power supplying scheme, the power and signal paths are short because the signal communication and power transfer between the second-tier chips68do not need to go to the front side of first-tier chip22, as shown by dashed route83.

FIG. 13illustrates package66in accordance with alternative embodiments. These embodiments are similar to the embodiments as shown inFIG. 12, except that inFIG. 12, vias62of the damascene structure are in physical contact with through-vias30, while inFIG. 13, conductive features50are formed over and contacting through-vias30, and vias62are in contact with conductive features50, which may be formed using a single damascene process. Also, as shown inFIG. 13, the dashed line drawn between dielectric layers54A and54B indicate that dielectric layer54may be formed of a homogeneous material, or may include two dielectric layers.

FIG. 14illustrates package66in accordance with alternative embodiments. These embodiments are similar to the embodiments as shown inFIG. 12, except that there are three second-tier chips68(including68A,68B, and68C) bonding to the same first-tier chip22. Each of second-tier chips68A,68B, and68C may be electrically connected to the neighboring second-tier chips through bridge structures64. In accordance with some embodiments, the power is transferred from the front side of chip22, through one of through-vias30, and distributed to all of second-tier chips68through bridge structure64and the interconnect structures74in the second-tier chips68. An example power re-distribution path86is illustrated. Signals are also transferred through the bridge structures64between second-tier chips68. Also, as shown inFIG. 14, the dashed line drawn between dielectric layers54A and54B indicate that dielectric layer54may be formed of a homogeneous material, or may include two dielectric layers.

FIG. 15illustrates package66in accordance with alternative embodiments. These embodiments are similar to the embodiments as shown inFIG. 14, except that a plurality of third-tier chips84(including84A,84B, and84C) are bonded to the corresponding second-tier chips68(including68A,68B, and68C) through face-to-back bonding. Accordingly, bridge structures87are formed on the backside of second-tier chips68. The bridge structures87may have the similar structures, and are formed using similar methods and similar materials, as bridge structures64. Each of third-tier chips84A,84B, and84C may be electrically connected to the neighboring third-tier chips through bridge structures87. In accordance with some embodiments, power is transferred through one of through-vias30, and distributed to second-tier chips68. The power is further transferred through one or more of through-vias78, and distributed to all of third-tier chips84through bridge structures87and the interconnect structures88in the third-tier chips84. Signals are also transferred through the bridge structures87between third-tier chips84. Also, as shown inFIG. 15, the dashed lines drawn between dielectric layers54A and54B indicate that dielectric layer54may be formed of a homogeneous material, or may include two dielectric layers. The dashed lines drawn between dielectric layers89A and89B indicate that dielectric layer89may be formed of a homogeneous material, or may include two dielectric layers.

In the embodiments shown inFIGS. 12 through 15, hybrid bonding is used to bond upper-tier chips to the lower-tier chips. In accordance with alternative embodiments, the bonding scheme as shown inFIGS. 12 through 15may be replaced with other bonding schemes such as micro-bump direct bonding, solder bonding, or the like. For example,FIG. 16illustrates an embodiment similar to the embodiments shown inFIG. 12, except that micro-bumps90are used to bond second-tier chips68to the first-tier chip22. Micro-bumps90may be metal pillars, solder regions, or the composite structures including metal pillars and solder regions on the metal pillars. In accordance with some embodiments, underfill92is dispensed between the upper-tier chips (such as68) and the corresponding lower-tier chip(s) (such as22).

The packages66may be used in various applications, withFIGS. 17 through 20illustrating some of the example applications. The packages66as shown inFIGS. 17 through 20may be any of the packages as shown inFIGS. 12 through 16, or the combinations and/or modifications, of these embodiments. Referring toFIG. 17, package110is formed. Package66is used in a fan-Out package102, which includes package66, through-molding vias104, and encapsulant105encapsulating package66and through-molding vias104therein. Interconnect structure106is formed as a fan-out structure extending laterally beyond the edges of package66. In accordance with some embodiments, Integrated Passive Device (IPD)108, which may be a capacitor die, a resistor die, an inductor die, or the like, is bonded to interconnect structure106. Package102is further bonded to fan-Out package107. Package107may include, for example, memory dies, memory cubes, or the like.

FIG. 18illustrates flip-chip chip-level package112, which includes package66bonding to package component114. Package component114may be formed of or comprise a package substrate, an interposer, a printed circuit board, or the like. The bonding may include hybrid bonding, solder (flip-chip) bonding, metal-to-metal direct bonding, or the like. Underfill116may be dispensed in the gap between package66and package component114. Encapsulant118may further be dispensed to encapsulate package66.

FIG. 19illustrates (flip-chip) chip-level package124, which includes package66bonding to package component128. Package component128may be an interposer chip, a device chip, or the like. Through-vias130are formed in package component128, and penetrate through the substrate of package component128. Package component128is further bonded to package component134, which may be a package substrate, a printed circuit board, or the like. In accordance with some embodiments, packages components126, which may be device chips, packages, memory cubes, or the like, are further bonded to package component128, and are electrically connected to package66, for example, through the redistribution lines in package component128. Underfills116and131and encapsulant118are further dispensed.

FIG. 20illustrates a Chip-on-Wafer-on-Substrate (CoWoS) structure138, in which package66acts as a chip, and is bonded to interposer140. The bonding may be performed with interposer140being in an interposer wafer, hence the resulting structure is referred to as a Chip-on-Wafer (CoW) structure. The resulting CoW structure is then sawed in to packages, and one of the packages is bonded to package substrate142. Interposer140may be free from active devices, and may be free from or include passive devices. Underfill148is dispensed between interposer140and package substrate142. Furthermore, package component144, which may be a device chip, a package, a memory cube, or the like, is bonded to package component140. Encapsulant146encapsulates package66and package component144therein.

The embodiments of the present disclosure have some advantageous features. By forming bridge structures on the backside of lower-chips, the upper chips bonding to the lower chips may be electrically interconnected and signally communicating with each other through the bridge structures. The electrical connection and the signal communication do not need to go through the front side of the lower chip (through through-vias in the lower chips), so that power efficiency is improved, and latency is reduced. Furthermore, the bridge structures may be formed using damascene structures, and the line widths and pitches of the bridge structures may be small, so that the density and the total count of signal paths may be increased.

In accordance with some embodiments of the present disclosure, a method includes forming integrated circuits on a front side of a first chip; performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip; forming a first bridge structure on a backside of the first chip using a damascene process, wherein the first bridge structure comprises a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad; and bonding a second chip and a third chip to the first chip through face-to-back bonding, wherein a third bond pad of the second chip is bonded to the first bond pad of the first chip, and a fourth bond pad of the third chip is bonded to the second bond pad of the first chip. In an embodiment, the forming the first bridge structure comprises a dual damascene process. In an embodiment, a dual damascene structure formed by the dual damascene process comprises a via and the conductive trace over and joined with the via, and wherein the via is in physical contact with a through-via in the plurality of through-vias. In an embodiment, the forming the first bridge structure comprises a single damascene process. In an embodiment, the method further comprises forming a first metal pad and a second metal pad on the backside of the first chip and in contact with a first through-via and a second through-via in the plurality of through-vias, wherein the first metal pad and the second metal pad are electrically connected to the first chip and the second chip, respectively. In an embodiment, the first chip, the second chip, and the third chip in combination comprises a power supplying path, and the power supplying path comprises: a through-via in the plurality of through-vias; a first interconnect structure in the first chip; the first bridge structure; and a second interconnect structure in the second chip. In an embodiment, the method further comprises forming a second bridge structure in the first chip, wherein the second bridge structure comprises a fifth bond pad and a sixth bond pad, and wherein the second chip is further bonded to the fifth bond pad; and bonding a fourth chip to the sixth bond pad of the first chip, wherein the power supplying path further comprises the second bridge structure. In an embodiment, entireties of the second chip and the third chip overlap the first chip, and the first chip extends laterally beyond all edges of the second chip and the third chip. In an embodiment, the method further comprises encapsulating the second chip and the third chip in an encapsulant; and sawing through the encapsulant and a wafer that comprises the first chip to separate the first chip, the second chip, and the third chip into a package. In an embodiment, the method further comprises packaging the package into an additional package. In an embodiment, the method further comprises forming an additional bridge structure on backsides of the second chip and the third chip; bonding a fourth chip over the second chip; and bonding a fifth chip over the third chip, wherein the fourth chip is electrically connected to the fifth chip through the additional bridge structure. In an embodiment, the additional bridge structure comprises a first via and a second via connected to through-vias in the second chip and the third chip, respectively.

In accordance with some embodiments of the present disclosure, a package includes a first chip comprising a semiconductor substrate; an integrated circuit at a front side of the semiconductor substrate; a plurality of through-vias penetrating through the semiconductor substrate; and a bridge structure on a backside of the semiconductor substrate, wherein the bridge structure comprises: a first bond pad; a second bond pad; and a conductive trace electrically coupling the first bond pad to the second bond pad; a second chip bonding to the first chip through face-to-back bonding, the second chip comprising a third bond pad bonding to the first bond pad; and a third chip bonding to the first chip through face-to-back bonding, the third chip comprising a fourth bond pad bonding to the second bond pad. In an embodiment, the bridge structure further comprises a first via in physical contact with a first through-via of the plurality of through-vias. In an embodiment, the bridge structure further comprises a second via in physical contact with a second through-via of the plurality of through-vias. In an embodiment, the first via, the first bond pad, the second bond pad, and the conductive trace are parts of a same dual damascene structure.

In accordance with some embodiments of the present disclosure, a package includes a first chip comprising a semiconductor substrate; a first interconnect structure on a front side of the semiconductor substrate, wherein the first interconnect structure comprises first damascene structures; a bridge structure on a backside of the semiconductor substrate, wherein the bridge structure comprises second damascene structures; and a through-via penetrating through the semiconductor substrate, wherein the through-via interconnects the first interconnect structure and the bridge structure; and a second chip and a third chip with front sides bonding to the first chip, wherein the second chip and the third chip are bonding to, and are in physically contact with, the bridge structure. In an embodiment, the package comprises a power supplying path, wherein the power supplying path comprises the through-via, a second interconnect structure of the second chip, the bridge structure, and a third interconnect structure of the third chip. In an embodiment, the first chip comprises a dual damascene structure on the backside of the semiconductor substrate, and wherein the dual damascene structure comprises a via, and the via is in physical contact with the through-via. In an embodiment, the package comprises a single damascene structure on the backside of the semiconductor substrate, wherein the single damascene structure is in physical contact with the through-via; and a dual damascene structure on the backside of the semiconductor substrate, wherein the dual damascene structure comprises a via, and the via is in physical contact with the single damascene structure.