Power supply control device and power supply control method for controlling switching device of boost chopper

A power supply control device includes a switch control unit configured to control ON/OFF of a switching device of a boost chopper by using an oscillation wave, a comparison voltage generating unit configured to charge or discharge comparison capacitor that generates a comparison voltage for comparison with the oscillation wave in correspondence with a DC output voltage outputted from the boost chopper, an input increase detecting unit configured to detect whether a detection value corresponding to current flowing through the boost chopper has increased to or above a detection criterion, an output voltage detecting unit configured to detect whether the DC output voltage is at or above the lower limit voltage, a discharging unit configured to discharge the comparison capacitor when the detection value has increased to or above the detection criterion and the DC output voltage is at or above the lower limit voltage.

The contents of the following Japanese patent application are incorporated herein by reference:2018-189008 filed in JP on Oct. 4, 2018 and;PCT/JP2019/033426 filed on Aug. 27, 2019.

BACKGROUND

1. Technical Field

The present invention relates to a power supply control device and power supply control method.

2. Related Art

Conventionally, a power supply control device including a boost chopper uses an error amplifier (transconductance amplifier) to perform feedback control in order to maintain an output voltage (for example, see Patent document 1 to 3). For example, the error amplifier outputs current corresponding to a voltage difference between a divided voltage of a DC output voltage inputted to an inverting input terminal and a reference voltage connected to a non-inverting input terminal. An output terminal of the error amplifier is connected to a capacitor charged by the output current from the error amplifier and a pulse width modulation comparator that controls an ON-width of a switching device. Thus, the ON-width of the switching device is controlled in correspondence with the voltage difference between the DC output voltage and the reference voltage to maintain the output voltage.[Patent document 1] Japanese Unexamined Patent Application, Publication No. 2002-51563[Patent document 2] Japanese Unexamined Patent Application, Publication No. Hei 5-199757[Patent document 3] WO2012/105200

In a conventional power supply control device, when an input is suddenly increased, switching control will be performed without reduction of the charge amount of a capacitor. As a result, the ON-width may be widened to cause overvoltage of an output voltage, which may destruct components of the power supply control device.

SUMMARY

In order to solve the above-mentioned problem, a first aspect of the present invention provides a power supply control device. The power supply control device may include a switch control unit configured to control ON/OFF of a switching device of a boost chopper by using an oscillation wave. The power supply control device may include a comparison voltage generating unit configured to charge or discharge a comparison capacitor that generates a comparison voltage for comparison with the oscillation wave in correspondence with a DC output voltage outputted from the boost chopper. The power supply control device may include an input increase detecting unit configured to detect whether a detection value corresponding to current flowing through the boost chopper has increased to or above a detection criterion. The power supply control device may include an output voltage detecting unit configured to detect whether the DC output voltage is at or above the lower limit voltage. The power supply control device may include a discharging unit configured to discharge the comparison capacitor when the detection value has increased to or above the detection criterion and the DC output voltage is at or above the lower limit voltage.

The input increase detecting unit may include a sampling circuit configured to sample a detection value corresponding to the current flowing through the boost chopper depending on the timing of switching the switching device from ON to OFF. The input increase detecting unit may include an increase detecting circuit configured to detect whether the detection value corresponding to the current flowing through the boost chopper has increased to or above the detection criterion relative to the detection value sampled by the sampling circuit.

The input increase detecting unit may input, as the detection value, a voltage generated at a current detecting resistor connected in series to an inductor and the switching device of the boost chopper.

The power supply control device may further include a switching stop unit configured to control the switching device to be OFF for a predetermined period when the detection value corresponding to the current flowing through the boost chopper has increased to or above the detection criterion and the DC output voltage is at or above the lower limit voltage.

The input increase detecting unit may detect that the detection value corresponding to the current flowing through the boost chopper has increased to or above the detection criterion when a rated value of an input AC voltage is raised due to switching of a power source that supplies electrical power to the boost chopper.

The comparison voltage generating unit may charge or discharge the comparison capacitor by charging or discharging current corresponding to the difference between the DC output voltage and the reference voltage.

A second aspect of the present invention provides a power supply control method. The power supply control method may include controlling ON/OFF of a switching device of a boost chopper by using an oscillation wave. The power supply control method may include charging or discharging a comparison capacitor that generates a comparison voltage for comparison with the oscillation wave in correspondence with a DC output voltage outputted from the boost chopper. The power supply control method may include detecting whether a detection value corresponding to current flowing through the boost chopper has increased to or above a detection criterion. The power supply control method may include detecting whether the DC output voltage is at or above the lower limit voltage. The power supply control method may include discharging the comparison capacitor when the detection value has increased to or above the detection criterion and the DC output voltage is at or above the lower limit voltage.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, the present invention will be described through the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all of the combinations of features described in the embodiments are essential to the solving means of the invention.

[1. Configuration of a Power Supply Device]

FIG. 1shows a power supply device1according to the present embodiment. The power supply device1is configured to output a DC output voltage Vout(as an example, 400 V) and is connected to a load, for example, of about 250 W. The power supply device1includes an AC power supply2, a full-wave rectifying circuit3for full-wave rectifying an AC input voltage of the AC power supply2, and a boost chopper4for boosting a DC output voltage of the full-wave rectifying circuit3.

A boost chopper4is connected between a positive-terminal output side and a negative-terminal output side of the full-wave rectifying circuit3, and, in the present embodiment, as an example, serves as a power-factor correction circuit such as a critical control mode). The boost chopper4includes a smoothing capacitor C0, a transformer T, and a diode D1that are connected in series to a positive-terminal output side of the full-wave rectifying circuit3, a boost switching device Q1, an output capacitor C1connected between the cathode side of the diode D1and the negative-terminal output side of the full-wave rectifying circuit3, voltage dividing resistors R1, R2connected in parallel to the output capacitor C in order to detect a output voltage Vout, a timing resistor R0, a current detecting resistor R3, a zero cross detecting resistor R4, a voltage error detecting and compensating circuit5, and a power supply control device6.

The smoothing capacitor C0smoothes current flowing through the positive-terminal output side of the full-wave rectifying circuit3. The transformer T includes a primary inductor L1that is provided on the positive-terminal output side of the full-wave rectifying circuit3and a secondary inductor L2that is grounded at one end. The inductor L1rectifies current flowing through the positive-terminal output side of the full-wave rectifying circuit3, and boosts the DC output voltage of the full-wave rectifying circuit3by using an inductive voltage, in association with operations inside the boost chopper4. Inductor current IL1flowing through the primary inductor L1may be, as an example, harmonic pulsating current of 10 kHz to 1000 kHz. The diode D1serves as a backflow prevention diode. The switching device Q1is, for example, an N-channel MOS transistor. Instead, the switching device Q1may be another type of a MOS transistor or an IGBT, etc. The drain and the source of the switching device Q1is electrically connected to a connecting point of the inductor L1and the anode side of the diode D1, and the negative-terminal output side of the full-wave rectifying circuit3, respectively. The gate of the switching device Q1is driven by a drive signal from the power supply control device6. As an example, the switching device Q1is driven by PWM. The output capacitor C1removes high-frequency components caused by switching operation from the voltage outputted from the power supply device1. The voltage dividing resistors R1, R2are connected in series to each other. The timing resistor R0is configured to determine a gradient of an oscillation wave of an oscillator60described below, and is grounded at one end. The current detecting resistor R3is configured to detect a voltage corresponding to the inductor current ILL, and is connected in series to the inductor L1and the switching device Q1. For example, the current detecting resistor R3may be connected between the negative-terminal output side of the full-wave rectifying circuit3and the ground. The zero cross detecting resistor R4is configured to detect a voltage corresponding to the inductor current IL1(that is, in the present embodiment, as an example, a voltage corresponding to the inductor current IL2flowing through the secondary inductor L2), and is connected to the secondary inductor L2of the transformer T at one end.

[1-1-1. Voltage Error Detecting and Compensating Circuit5]

The voltage error detecting and compensating circuit5is configured to remove ripple components of an error signal VCOMPthat will be described below, and is connected between the power supply control device6and the ground. The voltage error detecting and compensating circuit5includes a capacitor C51and a RC phase compensation circuit50that are connected in parallel. The RC phase compensation circuit50includes a resistor R50and a capacitor C50that are connected in series. The capacitor C51and/or capacitor C50, which is an example of a comparison capacitor, generate an error signal VCOMPas a comparison voltage for comparison with the oscillation wave in correspondence with the charge amount.

[1-1-2. Power Supply Control Device6]

The power supply control device6, which may be an IC for example, includes a feedback terminal FB as an output voltage detecting terminal, an output terminal OUT, a voltage error detecting and compensating terminal COMP, a resistor connecting terminal RT, a current detecting terminal CS configured to detect the inductor current IL1(in the present embodiment, as an example, the inductor current IL2), and a zero cross detecting terminal ZCD. Note that the power supply control device6may further include a power source terminal and a ground terminal. The feedback terminal FB is connected to a connecting point between the voltage dividing resistors R1, R2, and receives a feedback voltage VFBobtained by dividing the output voltage Voutof the power supply device1. The output terminal OUT is connected to the gate of the boost switching device Q1, and outputs a drive signal SVDthat is pulse-width modulated in order to drive the switching device Q1. The voltage error detecting and compensating terminal COMP is connected to the voltage error detecting and compensating circuit5. The resistor connecting terminal RT is connected to the other end (the ungrounded end) of the timing resistor R0. The current detecting terminal CS is connected to a connecting point between the full-wave rectifying circuit3and the current detecting resistor R3, and receives a detection voltage VCScorresponding to the inductor current IL1flowing through the current detecting resistor R3. The zero cross detecting terminal ZCD is connected to the other end (the end opposite to the secondary inductor L2) of the zero cross detecting resistor R4, and receives a detection voltage VZCDcorresponding to the inductor current IL2flowing through the zero cross detecting resistor R4.

The power supply control device6includes an oscillator60, a comparison voltage generating unit61, a protection circuit62, a switch control unit63, an input increase detecting unit64, an output voltage detecting unit65, a switching stop unit66, and a discharging unit67.

The oscillator60generates an oscillation wave. In the present embodiment, as an example, the oscillator60generates a ramp wave Ramp as the oscillation wave. The ramp wave Ramp may be triangular-wave shaped (as an example, sawtooth shaped). For example, the oscillator60is connected to the timing resistor R0via the resistor connecting terminal RT of the power supply control device6, and generates a sawtooth shaped ramp wave Ramp with a gradient corresponding to the resistance value of the timing resistor R0. The oscillator60provides the ramp wave Ramp to the switch control unit63. The oscillator60may start generating a ramp wave Ramp when a trigger signal is inputted (in the present embodiment, as an example, when a high-level positive output signal QQ is inputted from an RS flip-flop63fdescribed below), and stop generating the ramp wave Ramp to be reset when the trigger signal is not inputted (in the present embodiment, as an example, when a low-level positive output signal QQ is inputted).

The comparison voltage generating unit61charges or discharges the comparison capacitors C50, C51in correspondence with the DC output voltage Voutoutputted from the boost chopper4. In the present embodiment, as an example, the comparison voltage generating unit61charges or discharges the comparison capacitors C50, C51in correspondence with the feedback voltage VF. The comparison voltage generating unit61includes an error amplifier61a. The error amplifier61aamplifies the voltage difference between the feedback voltage VF and the reference voltage V61. An inverting input side of the error amplifier61areceives the feedback voltage VFB, and a non-inverting input side of the error amplifier61areceives the reference voltage V61corresponding to a target output voltage. The error amplifier61amay be a transconductance amplifier. The error amplifier61amay generate current corresponding to the voltage difference between the feedback voltage VF and the reference voltage V61(also called “charging or discharging current”), and generate an error signal VCOMPby charging or discharging the capacitors C50, C51of the voltage error detecting and compensating circuit5connected to the voltage error detecting and compensating terminal COMP with charging or discharging current. Generating an error signal VCOMPby using the voltage error detecting and compensating circuit5smoothes ripple components included in the output current of the error amplifier61aand causes the error signal VCOMPto be a substantially DC voltage in a steady state. The error signal VCOMPwill be provided to the switch control unit63, etc. Note that the reference voltage V61may be the maximum feedback voltage Vfb.

The protection circuit62protects components of the power supply control device6in the event of overvoltage or short circuit. The protection circuit62includes an overvoltage detecting comparator62a, a short circuit detecting comparator62b, and an overcurrent detecting comparator62c.

The overvoltage detecting comparator62ais configured to detect overvoltage of the DC output voltage Vout. A non-inverting output terminal of the overvoltage detecting comparator62ais connected to the feedback terminal FB to receive a feedback voltage VFB, and an inverting input terminal of the overvoltage detecting comparator62areceives a reference voltage V62aas a threshold for detecting overvoltage. Thus, when the feedback voltage VFBis higher than the reference voltage V62a, an output signal of the overvoltage detecting comparator62abecomes high-level to indicate overvoltage. The overvoltage detecting comparator62aprovides the output signal to the switch control unit63. As detailed below, when the high-level output signal is provided from the overvoltage detecting comparator62ato the switch control unit63, the switch control unit63turns OFF the switching device Q1to eliminate the overvoltage state.

The short circuit detecting comparator62bis configured to detect short circuit. A non-inverting output terminal of the short circuit detecting comparator62breceives a reference voltage V62bas a threshold for detecting short circuit, and an inverting output terminal of the short circuit detecting comparator62bis connected to the feedback terminal FB to receive a feedback voltage VFB. Thus, when the feedback voltage VFBis lower than the reference voltage V62b, an output signal of the short circuit detecting comparator62bbecomes high-level to indicate short circuit. The short circuit detecting comparator62bprovides the output signal to the switch control unit63. As detailed below, when the high-level output signal is provided from the short circuit detecting comparator62bto the switch control unit63, the switch control unit63turns OFF the switching device Q1to eliminate the short circuit state.

The overcurrent detecting comparator62cis configured to detect overcurrent of the current flowing through the boost chopper4. A non-inverting output terminal of the overcurrent detecting comparator62cis connected to the current detecting terminal CS to receive a detection voltage VCS, and an inverting input terminal of the overcurrent detecting comparator62creceives a reference voltage V62cas a threshold for detecting overcurrent. Thus, when the detection voltage VCSis higher than the reference voltage V62c, an output signal of the overcurrent detecting comparator62cbecomes high-level to indicate overcurrent. The overcurrent detecting comparator62cprovides the output signal to the switch control unit63. As detailed below, when the high-level output signal is provided from the overcurrent detecting comparator62cto the switch control unit63, the switch control unit63turns OFF the switching device Q1to eliminate the overcurrent state.

The switch control unit63controls ON/OFF of the switching device Q1by using an oscillation wave (in the present embodiment, as an example, a ramp wave Ramp). The switch control unit63includes a zero cross detecting comparator63a, a restart timer63b, an OR gate63c, a pulse width modulation comparator63d, an OR gate63e, an RS flip-flop63f, and a driver63g.

The zero cross detecting comparator63adetects that current flowing through the boost chopper4(in the present embodiment, as an example, the inductor current IL2) is zero. A non-inverting input terminal of the zero cross detecting comparator63areceives a reference voltage Vzcd, and an inverting input terminal of the zero cross detecting comparator63ais connected to the zero cross detecting terminal ZCD to receive a detection voltage VZCDcorresponding to the inductor current IL2. The reference voltage Vzcdmay be a voltage when the inductor current IL2is zero (or substantially zero). Thus, an output signal of the zero cross detecting comparator63a(also called “zero cross detecting signal”) becomes high-level when the inductor current IL2is zero, and becomes low-level when the inductor current IL2is not zero. The zero cross detecting comparator63aprovides the output signal to a set terminal of the RS flip-flop63fvia the OR gate63c. Thus, the RS flip-flop63fwill be set when the current flowing through the boost chopper4becomes zero current. The zero cross detecting comparator63amay have hysteresis characteristics. When no zero current is detected during a preset period, the restart timer63bprovides an output signal to the set terminal of the RS flip-flop63fvia the OR gate63c.

The pulse width modulation comparator63doutputs a pulse width modulation signal to modulate the pulse width of a drive signal for the switching device Q1. A non-inverting input terminal of the pulse width modulation comparator63dreceives an oscillation wave (in the present embodiment, as an example, a ramp wave Ramp) from the oscillator60, and an inverting input terminal of the pulse width modulation comparator63dreceives an error signal VCOMPgenerated by the error amplifier61aand the voltage error detecting and compensating circuit5. Thus, the output signal of the pulse width modulation comparator63dbecomes low-level when an instantaneous value of the oscillation wave is below the error signal VCOMP, and becomes high-level when the instantaneous value of the oscillation wave is equal to or above the error signal VCOMP. The pulse width modulation comparator63doutputs the output signal to the OR gate63e. Note that the error signal VCOMPis constant when the magnitude of a load connected to the power supply device1is constant, so that the time period during which the output signal of the pulse width modulation comparator63dis high-level or low-level may be constant.

The OR gate63eprovides a signal of the logical sum of a pulse width modulation signal from the pulse width modulation comparator63dand each output signal from the protection circuit62, to the RS flip-flop63f. A reset terminal R of the RS flip-flop63freceives an output signal of the OR gate63e, and the set terminal S of the RS flip-flop63freceives an output signal of the OR gate63c. The RS flip-flop63foutputs a high-level positive output signal QQ in a set state, and outputs a low-level positive output signal QQ in a reset state. The RS flip-flop63fprovides the positive output signal QQ from a positive output terminal Q to the oscillator60, the driver63g, and a sampling circuit70. The driver63goutputs a drive signal SVDto the gate of the switching device Q1via the output terminal OUT. For example, when a high-level positive output signal QQ is inputted to the driver63g, the driver63gmay turn ON the switching device Q1by outputting a high-level drive signal SVD. Note that, as described above, in the present embodiment, the positive output signal QQ from the RS flip-flop63fis also provided to the oscillator60as a trigger signal. Therefore, the oscillator60starts generating an oscillation wave at the same timing as the switching device Q1being turned ON.

The input increase detecting unit64detects whether a detection value corresponding to the inductor current IL1(in the present embodiment, as an example, a detection voltage VCSdetected by the current detecting resistor R3) has increased to or above the detection criterion. The input increase detecting unit64includes a sampling circuit70and an increase detecting circuit71.

The sampling circuit70samples a detection voltage VCSat the timing of switching the switching device Q1from ON to OFF. The sampling circuit70includes a current source70a, an N-channel MOSFET70b, a capacitor70c, an NOR gate70d, and an N-channel MOSFET70e. The current source70aprovides constant current to a parallel circuit that consists of the N-channel MOSFET70band the capacitor70c. The N-channel MOSFET70bis connected between the current source70aand the ground, and is driven by a positive output signal QQ from the RS flip-flop63fof the switch control unit63. The capacitor70cis connected in parallel to the N-channel MOSFET70b. The capacitor70cis charged by current from the current source70awhen the N-channel MOSFET70bis OFF, and is discharged when the N-channel MOSFET70bis ON. The NOR gate70dprovides an inverted signal of the logical sum of the positive output signal QQ from the RS flip-flop63fand the charge voltage of the capacitor70c, to the gate of the N-channel MOSFET70e. The charge voltage inputted to the NOR gate70dmay be considered low-level when the charge voltage is below a logical threshold, and may be considered high-level when the charge voltage is at or above the logical threshold. The N-channel MOSFET70eis connected between the current detecting terminal CS and the increase detecting circuit71. When the output signal from the NOR gate70dis high-level, the N-channel MOSFET70eturns ON to sample a detection voltage Vs, and provides the sampled detection voltage to the increase detecting circuit71. An integrating circuit70fmay be provided between the N-channel MOSFET70eand the increase detecting circuit71. The integrating circuit integrates a detection voltage VCSprovided from the N-channel MOSFET70e, and provides the integrated value to the increase detecting circuit71.

In the sampling circuit70as described above, when the positive output signal QQ from the RS flip-flop63fis high-level (that is, when the switching device Q1is ON), the N-channel MOSFET70bbeing in the ON state, so that the capacitor70cwill be discharged to maintain the charge voltage to the low-level. In addition, when the positive output signal QQ is high-level, which means that the output signal of the NOR gate70dis low-level, the N-channel MOSFET70eis in the OFF state, so that no detection voltage VCSwill be sampled. Subsequently, when the positive output signal QQ falls to low-level in order to turn OFF the switching device Q1, the N-channel MOSFET70bturns OFF to raise the charge voltage of the capacitor70c. At this point, when the charge voltage is below the logical threshold of the NOR gate70d, the output signal of the NOR gate70dbecomes high-level. Thus, the N-channel MOSFET70eis turned ON to start sampling a detection voltage VCS. When the charge voltage reaches the logical threshold of the NOR gate70d, the output signal of the NOR gate70dfalls to low-level. Thus, the N-channel MOSFET70eis turned OFF to finish sampling the detection voltage VCS. Thus, the detection voltage VCSis sampled during a certain time period at the timing of turning OFF the switching device Q1.

The increase detecting circuit71detects whether the detection voltage VCSfrom the current detecting terminal CS has increased to or above the detection criterion relative to the detection voltage VCSsampled by the sampling circuit70. The increase detecting circuit71includes a differential amplifier71aand a comparator71e. The differential amplifier71aincludes an amplifier71band voltage dividing resistors71c,71d. Anon-inverting input terminal of the amplifier71breceives a detection voltage VCSsampled by the sampling circuit70, and an inverting input terminal of the amplifier71breceives a voltage obtained by dividing the output voltage of the amplifier71bwith the voltage dividing resistors71c,71d. In this context, the gain of the differential amplifier71ais an example of the detection criterion. In the present embodiment, as an example, the gain of the differential amplifier71ais expressed as (R71c+R71d)/R71d, where R71c, R71dare the resistance values of the voltage dividing resistors71c,71drespectively. Thus, the output signal V71bof the amplifier71bis a voltage obtained by multiplying the sampled detection voltage VCSby the gain (R71c+R71d)/R71das a detection criterion. Anon-inverting input terminal of the comparator71ereceives a present detection voltage VCS, and an inverting input terminal of the comparator71ereceives an output signal V71bof the differential amplifier71a(that is, a detection voltage VCSwhich is sampled by the sampling circuit70and multiplied by the gain of the differential amplifier71a). Thus, an output signal of the comparator71ebecomes high-level to indicate sudden increase of the input when the detection voltage VCShas increased to or above the detection criterion relative to the detection voltage VCSfrom the sampling circuit70, and becomes low-level to indicate absence of sudden increase of the input when the detection voltage VCShas not increased to or above the detection criterion. The comparator71eprovides the output signal to the switching stop unit66.

The output voltage detecting unit65detects whether the DC output voltage Voutis at or above the lower limit voltage. The lower limit voltage may be, for example, the lower limit of the voltage that the DC output voltage Voutmay have without sudden increase of the load. The output voltage detecting unit65includes a comparator65a. A non-inverting input terminal of the comparator65ais connected to the feedback terminal FB, and receives the feedback voltage VFBas an example of the DC output voltage Vout, and an inverting input terminal of the comparator65areceives a reference voltage V65as an example of the lower limit voltage. The reference voltage V65may be a voltage that serves as a threshold for detecting sudden increase of the load. Thus, an output signal of the comparator65abecomes high-level to indicate absence of sudden increase of the load when the feedback voltage VFBis at or above the reference voltage V65, and becomes low-level to indicate sudden increase of the load when the feedback voltage VFBis below the reference voltage V65. The comparator65aprovides the output voltage to a switching stop unit66.

When the detection voltage VCShas increased to or above the detection criterion and the DC output voltage Voutis at or above the lower limit voltage, the switching stop unit66controls the switching device Q1to be OFF during a predetermined period (also called a “delay period”). The switching stop unit66includes an NAND gate66aand a counter66b.

The NAND gate66aoutputs an inverted signal of the logical product of the output signal of the output voltage detecting unit65and the output signal of the input increase detecting unit64. Thus, the output signal of the NAND gate66abecomes low-level when the output signal of the output voltage detecting unit65indicates the high-level (in the present embodiment, as an example, absence of sudden increase of the load) and the output signal of the input increase detecting unit64indicates the high-level (in the present embodiment, as an example, sudden increase of the input), and becomes high-level otherwise. The NAND gate66aprovides the output signal to the counter66b.

The counter66breceives a clock signal at a clock terminal, and receives an output signal from the NAND gate66aat a reset terminal. When a low-level signal is inputted to the reset terminal, the counter66boutputs a signal Vc that remains high-level during the delay period. The counter66bprovides the output signal Vc to the OR gate63eof the switch control unit63. Thus, when the detection voltage VCShas increased to or above the detection criterion and the DC output voltage Voutis at or above the lower limit voltage, the switching device Q1is controlled to be OFF during the delay period.

The counter66bmay further provide the output signal Vc to the discharging unit67. Note that the switching stop unit66may provide a signal of the logical product of the output signal of the output voltage detecting unit65and the output signal of the input increase detecting unit64to the discharging unit67, instead of the output signal Vc of the counter66b.

When the detection voltage VCShas increased to or above the detection criterion and the DC output voltage Voutis at or above the lower limit voltage, the discharging unit67discharges the capacitors C50, C51. The discharging unit67includes a resistor67aand an N-channel MOSFET67b. The resistor67ais a current limiting resistor, and limits current flowing through the N-channel MOSFET67b. The N-channel MOSFET67bis connected between the voltage error detecting and compensating terminal COMP and the ground, and the gate of the N-channel MOSFET67bis driven by the output signal Vc from the switching stop unit66. Thus, when the output signal from the switching stop unit66becomes high-level, the N-channel MOSFET67bturns ON to discharge the capacitors C50, C51.

In the power supply control device6as described above, when a detection value corresponding to current flowing through the boost chopper4(in the present embodiment, as an example, a detection voltage VCS) has increased to or above the detection criterion and the DC output voltage Voutis at or above the lower limit voltage, the capacitors C50, C51that generate the error signal VCOMPare discharged. Therefore, when the input current is suddenly increased without sudden increase of the load, the capacitors C50, C51are discharged to extend the time period during which the error signal VCOMPis smaller than the ramp wave Ramp. This extends the time period during which the RS flip-flop63fis reset and reduces the ON-width of the switching device Q1. This can prevent component destruction due to increase of the maximum current flowing to the switching device Q1from the boost chopper4during the original ON time upon increase of the input voltage (as an example, component destruction due to a surge voltage upon turning OFF the switching device Q1).

Also, when the detection voltage VCShas increased to or above the detection criterion and the DC output voltage Voutis at or above the lower limit voltage, the switching device Q1is controlled to be OFF during the delay period. This can reliably prevent the switching device Q1from being turned ON and causing overvoltage of the DC output voltage Vout.

In addition, the sampling timing of the sampling circuit70corresponds to the timing of the switching device Q1switching from ON to OFF, so that the detection criterion of the detection voltage VCSis set in correspondence with the peak value of the detection voltage VCSduring the previous ON period. This can prevent discharge of the capacitors C50, C51in a normal condition in which the detection voltage VCSis gradually increased in correspondence with the waveform of the AC input voltage, and allow discharge of the capacitors C50, C51in an abnormal condition in which the AC input voltage is suddenly increased.

In addition, the detection voltage VCSgenerated at the current detecting resistor R3is used as a detection value for detecting increase of the input. Thus, the power supply control device1can be simpler than a power supply control device1provided with a dedicated terminal for detecting the input voltage.

In addition, charging or discharging current is generated at the error amplifier61ain correspondence with the difference between the feedback voltage VFBcorresponding to the DC output voltage Voutand the reference voltage V61to charge or discharge the capacitors C50, C51. Thus, when the load fluctuates and the DC output voltage Voutdeviates from the reference voltage, the capacitors C50, C51are charged or discharged by charging or discharging current and the error signal VCOMPfluctuates, so that the ON/OFF widths of the switching device Q1change. Thus, the DC output voltage Voutcan be maintained at the reference voltage when the load changes.

FIG. 2shows some operation waveforms of the power supply control device6. InFIG. 2, a vertical axis indicates a voltage, and a horizontal axis indicates the time. Note that the “input voltage” inFIG. 2indicates the voltage inputted from the full-wave rectifying circuit3to the boost chopper4.

In the steady state, when the switching device Q1is turned ON and turned OFF, a detection voltage VCSis sampled by the sampling circuit70at the timing of turning OFF, and the differential amplifier71aoutputs an output signal V71bobtained by multiplying the detection voltage VCSby the gain. At the time point t1, the detection voltage VCSrises as the input voltage is suddenly increased (as an example, the AC power supply2is switched from a 90 V AC power supply to a 264 V AC power supply). Note that the detection voltage VCSrises at the timing of the drive signal SVDas a voltage of the output terminal OUT switching from the low-level to the high-level, and has a peak voltage at the timing of the drive signal SVDswitching from the high-level to the low-level. The comparator71ecompares the output signal V71bobtained by multiplying the detection voltage VCSsampled by the sampling circuit70upon the last turning OFF by the gain with the present detection voltage VCS, and, when the present detection voltage VCSis determined to be larger than the output signal V71b, outputs a high-level output signal that indicates sudden increase of the input. Note that, although not shown inFIG. 2, at this time in the present embodiment, there is no sudden increase of the load and the output signal from the output voltage detecting unit65is high-level. Thus, the output signal of the NAND gate66abecomes low-level and the output signal Vc of the counter66bbecomes high-level during the delay period (as an example, 1 μs to 10 μs), so that the OFF state of the switching device Q1is maintained and the capacitors C50, C51are discharged by the discharging unit67to reduce the error voltage VCOMP. At the time point t2, when the delay period ends, the output signal Vc of the counter66bbecomes low-level. Thus, the switching device Q1restarts its switching operation in a state where the error voltage VCOMPis low.

FIG. 3shows some operations of the power supply control device6. The power supply control device6controls the boost chopper4while preventing component destruction by performing processes of steps S11to S19.

In step S11, the switch control unit63controls ON/OFF of the switching device Q1of the boost chopper4by using a ramp wave Ramp. For example, the switch control unit63controls the switching device Q1so that the switching device Q1turns OFF in a time period when the ramp wave Ramp becomes larger than the error signal VCOMP.

In step S13, the error amplifier61aof the comparison voltage generating unit61charges or discharges the capacitors C50, C51that generate the error signal VCOMPin correspondence with the DC output voltage Voutoutputted from the boost chopper4. For example, the error amplifier61agenerates charging or discharging current corresponding to the voltage difference between the feedback voltage VFBand the reference voltage V61and charges or discharges the capacitors C50, C51.

In step15, the input increase detecting unit64detects whether the detection voltage VCShas increased to or above the detection criterion. For example, when the rated value of the input AC voltage is raised due to switching of the AC power supply2that supplies electrical power to the boost chopper4, the input increase detecting unit64may detect that the detection voltage VCShas increased to or above the detection criterion.

In step S17, the output voltage detecting unit65detects whether the DC output voltage Voutis at or above the lower limit voltage. Thus, presence or absence of sudden increase of the load is detected.

In step S19, when the detection voltage VCShas increased to or above the detection criterion and the DC output voltage Voutis at or above the lower limit voltage, the discharging unit67discharges the capacitors C50, C51. Thus, when the input current is suddenly increased without sudden increase of the load, the capacitors C50, C51are discharged to reduce the ON-width of the switching device Q1. This prevents component destruction. Afterwards, the power supply control device6repeats the processes of steps S11to S19. Note that the power supply control device6may move to the process of step S11without discharging the capacitors C50, C51when the detection voltage VCShas not increased to or above the detection criterion or when the DC output voltage Voutis below the lower limit voltage.

According to the operations described above, when the rated value of the input AC voltage is raised due to switching of the AC power supply2, increase of the detection voltage VCSto or above the detection criterion is detected, and therefore component destruction due to switching of the power source can be prevented.

Note that, although in the above-mentioned embodiment the power supply device1is provided with an AC power supply2and a full-wave rectifying circuit3, at least one of those components may be externally connected to the power supply device1without being provided in the power supply device1.

In addition, although the input increase detecting unit64described above uses a detection voltage detected by the current detecting resistor R3as the detection value, the input increase detecting unit64may use a detection voltage detected by the zero cross detecting resistor R4as the detection value.

In addition, although the power supply control device6described above includes an oscillator60, a protection circuit62, and a switching stop unit66, at least one of those components may be omitted from the power supply control device6. For example, the power supply control device6may include an AND gate that provides a logical product of the output signal of the output voltage detecting unit65and the output signal of the input increase detecting unit64to the N-channel MOSFET67bof the discharging unit67, instead of the switching stop unit66.

EXPLANATION OF REFERENCES