Solid-state imaging device, manufacturing method of solid-state imaging device, and electronic apparatus

There is provided a solid-state imaging device including a first substrate having a pixel circuit including a pixel array unit formed thereon, and a second substrate having a plurality of signal processing circuits formed thereon so as to be arranged through a scribe region. The first substrate and the second substrate are stacked.

BACKGROUND ART

In the past, in a case of manufacturing a solid-state imaging device having an area greater than the exposure range of an exposure apparatus, the solid-state imaging device is divided into a plurality of regions, and separate exposure for exposing respective separated regions is used (for example, see PTL 1).

Further, in the past, in order to improve the aperture ratio of the solid-state imaging device, a stacking technology has been used in which a pixel circuit including a pixel array unit and a signal processing circuit are respectively formed on different semiconductor substrates, and the two semiconductor substrates are stacked and electrically connected (for example, see PTL 2).

Then, for example, in a case of manufacturing a solid-state imaging device of a stacked structure having an area greater than the exposure range of an exposure apparatus, separate exposure is performed on respective semiconductor substrates.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

However, in the separate exposure, different photomasks are used for the separated regions or high-precision alignment is necessary in a portion connecting the separated regions, and thus a manufacturing process is complicated and a manufacturing cost increases.

Thus, the present technology is made to be able to reduce the manufacturing cost of the solid-state imaging device.

Solution to Problem

A solid-state imaging device according to a first embodiment of the present technology includes a first substrate having a pixel circuit including a pixel array unit formed thereon and

a second substrate having a plurality of signal processing circuits formed thereon, wherein the plurality of signal processing circuits are arranged adjacent to one another and include a spacing region therebetween, and

wherein the first substrate and the second substrate are stacked.

A manufacturing method of a solid state imaging device according to a second embodiment of the present disclosure includes forming a pixel circuit including a pixel array unit so as to be two-dimensionally arranged through a scribe region on a first semiconductor substrate, by using one or more separate exposures, forming a signal processing circuit that processes a pixel signal of each pixel in the pixel array unit so as to be two-dimensionally arranged through a scribe region on a second semiconductor substrate, by using a one-shot exposure;

stacking the first semiconductor substrate and the second semiconductor substrate such that the scribe region of the first semiconductor substrate overlaps the scribe region of the second semiconductor substrate, and cutting a semiconductor substrate including the first semiconductor substrate and the second semiconductor substrate that are stacked, along the scribe region of the first semiconductor substrate.

An electronic apparatus according to a third embodiment includes a solid-state imaging device including a first substrate having a pixel circuit including a pixel array unit formed thereon and a second substrate having a plurality of signal processing circuits formed thereon, wherein the plurality of signal processing circuits are arranged adjacent to one another and include a spacing region therebetween, and wherein the first substrate and the second substrate are stacked.

Advantageous Effects of Invention

According to the first to third embodiments of the present technology, it is possible to reduce the manufacturing cost of the solid-state imaging device.

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments for carrying out the present technology (hereinafter, referred to as embodiments) will be described. In addition, a description will be made in the following order.

1. First embodiment (example of signal processing circuit not being electrically connected)

2. Second embodiment (example of signal processing circuit being electrically connected in logic board)

3. Third embodiment (example of signal processing circuit being electrically connected in pixel substrate)

1. First Embodiment

FIG. 1is a perspective view schematically illustrating a configuration example of a solid-state imaging device1according to a first embodiment of the present technology. In addition, here, a case where the solid-state imaging device1is a CMOS image sensor will be described as an example, but the present technology is not limited to application to the CMOS image sensor.

The solid-state imaging device1is a semiconductor chip of a structure in which a pixel substrate11and a logic board12are stacked (so-called, a stacked structure). Further, the solid-state imaging device1is a back-illuminated type CMOS image sensor in which a wiring layer of the pixel substrate11and a wiring layer of the logic board12are stacked so as to be adjacent to each other. In addition, the present technology is not limited to application to the back-illuminated type CMOS image sensor.

The pixel substrate11is a semiconductor substrate in which a pixel circuit21is formed, and the pixel circuit21includes a pixel array unit (a pixel unit)31in which each of the unit pixels32includes a photoelectric conversion element and is arranged two-dimensionally in a matrix. In addition, for example, pads for providing external electrical connection and vias for electrical connection with the logic board12, which are not shown, are provided in a peripheral portion surrounding a pixel array unit31of the pixel circuit21. A pixel signal obtained from each unit pixel32of the pixel array unit31is an analog signal, and the analog pixel signal is transmitted from the pixel substrate11to the logic board12through the vias or the like.

The logic board12is a semiconductor substrate in which a signal processing circuit41L and a signal processing circuit41R having the same circuit pattern are formed so as to be arranged to the left and right through a spacing region, such as a scribe region42. In addition, inFIG. 1, the width of the scribe region42is widely exaggerated for clarity of illustration. This is also applied to the following drawings.

The signal processing circuit41L performs, for example, a predetermined signal process, including digitalization (AD conversion) of the analog pixel signal that is read from each unit pixel32in the left half region of the pixel array unit31, and stores the pixel data, which is subjected to the signal process. Further, the signal processing circuit41L reads, for example, the stored pixel data in a predetermined order, and outputs the pixel data to the outside of the chip. Thus, the pixel data obtained from the unit pixels32in the left half region of the pixel array unit31is output from the signal processing circuit41L.

The signal processing circuit41R performs, for example, a predetermined signal process, including digitalization (AD conversion) of the analog pixel signal read from each unit pixel32in the right half region of the pixel array unit31, and stores the pixel data, which is subjected to the signal process. Further, the signal processing circuit41R reads, for example, the stored pixel data in a predetermined order, and outputs the pixel data to the outside of the chip. Thus, the pixel data obtained from the unit pixels32in the right half region of the pixel array unit31is output from the signal processing circuit41R.

Further, the signal processing circuit41L and the signal processing circuit41R control respective units of the solid-state imaging device1while synchronizing, for example, the pixel circuit21.

Thus, it is possible to make the area of the pixel substrate11substantially equal to the area of the pixel array unit31by using a stacked structure of the pixel substrate11and the logic board12. As a result, it is possible to reduce the size of the solid-state imaging device1, and thus, it is possible to reduce the overall size of the chip. Further, it is possible to improve the aperture ratio of the solid-state imaging device1.

In addition, since it is possible to perform a process suitable for making the unit pixel32or the like on the pixel substrate11and perform a process suitable for making the signal processing circuits41L and41R on the logic board12, it is possible to optimize the process during manufacturing of the solid-state imaging device1.

In addition, the area of the pixel circuit21is greater than the exposure range of an exposure apparatus, and thus separate exposure is necessary. Meanwhile, each of the areas of the signal processing circuit41L and the signal processing circuit41R is smaller than the exposure range of the exposure apparatus, and thus one-shot exposure is possible.

In addition, hereinafter, if there is no need to distinguish the signal processing circuit41L and the signal processing circuit41R, they are simply referred to as a signal processing circuit41.

FIG. 2is a circuit diagram illustrating a specific configuration of the pixel circuit21on the pixel substrate11and the signal processing circuits41L and41R on the logic board12of the solid-state imaging device1. In addition, as described above, the pixel circuit21and the signal processing circuits41L and41R are electrically connected through vias, not shown.

First, the configuration of the pixel circuit21on the pixel substrate11will be described. In addition to the pixel array unit31, in which the unit pixels32are arranged two-dimensionally in a matrix, a row selection unit33that selects each unit pixel32of the pixel array unit31in units of rows based on an address signal applied from the logic board12is provided in the pixel circuit21. In addition, here, although the row selection unit33is provided on the pixel substrate11, it is also possible to provide the row selection unit33on the logic board12.

The unit pixel32includes, for example, a photodiode51as a photoelectric conversion element. Further, the unit pixel32includes four transistors, for example, a transfer transistor (transfer gate)52, a reset transistor53, an amplifying transistor54, and a selection transistor55, in addition to the photodiode51.

Here, for example, N channel transistors are used as the four transistors52to55. However, here, a combination of the conductivity types of the transfer transistor52, the reset transistor53, the amplifying transistor54, and the selection transistor55is only an example, and a combination is not limited to the combination. In other words, as necessary, it is possible to use a combination of P-channel transistors.

A transfer signal TRG, a reset signal RST, and a selection signal SEL which are drive signals for driving the unit pixel32are appropriately supplied to the unit pixel32from the row selection unit33. In other words, the transfer signal TRG, the reset signal RST, and the selection signal SEL are respectively applied to the gate electrode of the transfer transistor52, the gate electrode of the reset transistor53, and the gate electrode of the selection transistor55.

The photodiode51has an anode electrode connected to a power supply of a low potential (e.g., ground), and accumulates the photoelectric charges by converting the received light (incident light) into photoelectric charges (here, photoelectrons) of the charge quantity corresponding to the light quantity. The cathode electrode of the photodiode51is electrically connected to the gate electrode of the amplifying transistor54through the transfer transistor52. A node56electrically connected to the gate electrode of the amplifying transistor54is referred to as a floating diffusion (FD) region portion.

The transfer transistor52is connected between the cathode electrode of the photodiode51and the FD portion56. The transfer signal TRG of a high level (e.g., VDDlevel), which is active (hereinafter, referred to as “High active”), is applied to the gate electrode of the transfer transistor52from the row selection unit33. The transfer transistor52becomes conductive in response to the transfer signal TRG, and the photoelectric charges obtained through the photoelectric conversion by the photodiode51are transferred to the FD portion56.

The reset transistor53includes a drain electrode connected to a pixel power supply VDDand a source electrode connected to the FD portion56. The High active reset signal RST is applied to the gate electrode of the reset transistor53from the row selection unit33. The reset transistor53becomes conductive in response to the reset signal RST, and the FD portion56is reset by discarding the charges in the FD portion56to the pixel power supply VDD.

The amplifying transistor54includes a gate electrode connected to the FD portion56, and a drain electrode connected to a pixel power supply VDD. Then, the amplifying transistor54outputs the potential of the FD portion56after being reset by the reset transistor53, as a reset signal (reset level) Vreset. The amplifying transistor54outputs the potential of the FD portion56after the signal charges thereof being transferred by the transfer transistor52, as a light accumulation signal (signal level) Vsig.

The selection transistor55includes, for example, a drain electrode connected to the source electrode of the amplifying transistor54and a source electrode connected to a signal line34. The High active selection signal SEL is applied to the gate electrode of the selection transistor55from the row selection unit33. The selection transistor55becomes conductive in response to the selection signal SEL, and the signals output from the amplifying transistor54are read to the signal line34, with the unit pixel32as the selected state.

As is apparent from the above description, the potential of the FD portion56after being reset is read as a reset level Vreset, and the potential of the FD portion56after the signal charges being transferred is read as a signal level Vsig from the unit pixel32, to the signal line34, in order. In addition, the signal level Vsig also includes the component of the reset level Vreset.

In addition, here, a circuit configuration is used in which the selection transistor55is connected between the source electrode of the amplifying transistor54and the signal line34, but it is possible to employ a circuit configuration in which the selection transistor55is connected between the pixel power supply VDDand the drain electrode of the amplifying transistor54.

Further, the unit pixel32is not limited to a pixel structure including the above four transistors. For example, a pixel structure including three transistors, in which the amplifying transistor54also has the function of the selection transistor55, or a pixel structure in which a plurality of photoelectric conversion elements (i.e., pixels) share transistors following the FD portion56may be used, and the configuration of the pixel circuit does not matter.

Next, the configuration of the signal processing circuits41L and41R on the logic board12will be described. In addition, as described above, the signal processing circuit41L and the signal processing circuit41R have the same circuit pattern, and thus here, the configuration of the signal processing circuit41L will be mainly described.

The signal processing circuit41L is a circuit for mainly processing pixel signals from the unit pixel32in the left half region of the pixel array unit31. The signal processing circuit41L is configured to include a current source61L, a decoder62L, a control unit63L, a row decoder64L, a signal processing unit65L, a column decoder/sense amplifier66L, a memory unit67L, a data processing unit68L, and an interface (IF) unit69L.

The current source61L is connected to each signal line34from which a signal is read for each pixel column from each unit pixel32of the pixel array unit31. The current source61L has a so-called load MOS circuit configuration, which includes a MOS transistor, of which the gate potential is biased at a constant potential so as to provide, for example, a constant current to the signal line34. The current source61L of the load MOS circuit configuration causes the amplifying transistor54to operate as a source follower, by supplying a constant current to the amplifying transistor54of the unit pixel32of the selected row.

The decoder62L applies an address signal for specifying the address of the selected row to the row selection unit33, when selecting each unit pixel32of the pixel array unit31in units of rows, under the control of the control unit63L.

The row decoder64L specifies a row address when writing pixel data to the memory unit67L or reading pixel data from the memory unit67L under the control of the control unit63L.

The signal processing unit65L includes at least AD converters81L-1to81L-n that digitize (AD conversion) analog pixel signals which are read out from each unit pixel32of the pixel array unit31through the signal line34. Then, the signal processing unit65L is configured so as to perform a signal process on the analog pixel signal in parallel in units of pixel columns (column parallel AD). In addition, if there is no need to distinguish the AD converters81L-1to81L-n, hereinafter, they are simply referred to as an AD converter81L.

The signal processing unit65L further includes a reference voltage generation unit82L that generates a reference voltage used during the AD conversion in each AD converter81L. The reference voltage generation unit82L generates a reference voltage of a so-called ramp waveform (a slope-like waveform) of which a voltage value varies in a stepwise manner over time. The reference voltage generation unit82L can be configured by using, for example, a digital-analog conversion (DAC) circuit.

The AD converter81L is provided, for example, for each pixel column of the pixel array unit31, that is, for each signal line34. In other words, the AD converter81L is a so-called column parallel AD converter, and the column parallel AD converters of the number of pixel columns in the left half of the pixel array unit31are arranged. Then, the AD converter81L generates a pulse signal having for example, a size in the time-axis direction corresponding to the size of the level of a pixel signal (i.e., pulse width), and performs the AD conversion process by measuring the length of the period of the pulse width of the pulse signal.

More specifically, for example, the AD converter81L-1is configured to include at least a comparator (COMP)91L-1and a counter92L-1, as illustrated inFIG. 2. The comparator91L-1regards the analog pixel signals (the signal level Vsig and the reset level Vreset, which are described previously), which are read from the unit pixel32through the signal line34as a comparative input, regards a reference voltage Vref of a ramp wave, which is supplied from the reference voltage generation unit82L as a reference input, and compares both inputs.

Then, in the comparator91L-1, for example, when the reference voltage Vref is greater than the pixel signal, the output becomes a first state (e.g., a high level), and when the reference voltage Vref is equal to or less than the pixel signal, the output becomes a second state (e.g., a low level). The output signal of the comparator91L-1is a pulse signal having a pulse width corresponding to the magnitude of the level of pixel signal.

For example, an up/down counter is used as the counter92L-1. The clock CK is applied to the counter92L-1, at the same timing as the supply start timing of the reference voltage Vref for the comparator91L. Since the counter92L-1, which is the up/down counter, performs down-counting or up-counting in synchronization with the clock CK, the counter92L-1measures the duration of the pulse width of the output pulse of the comparator91L-1, that is, a comparison period from the start of the comparison operation to the end of the comparison operation. During the measurement operation, with respect to the reset level Vreset and the signal level Vsig, which are read in order from the unit pixel32, the counter92L-1performs down-counting for the reset level Vreset and up-counting for the signal level Vsig.

It is possible to obtain a difference between the signal level Vsig and the reset level Vreset by the operation of the down counter/up counter. As a result, the AD converter81L-1performs a correlated double sampling (CDS) process in addition to AD conversion process. The CDS process is a process of removing a pixel-specific fixed pattern noise, such as a reset noise of the unit pixel32and threshold variations in the amplifying transistor54, by obtaining a difference between the signal level Vsig and the reset level Vreset. Then, the count result (i.e., count value) of the counter92L-1is a digital value obtained by digitizing the analog pixel signals.

In addition, the AD converters81L-2to81L-n have the same configuration as that of the AD converter81L-1, and thus the redundant description thereof will be omitted. Further, when there is no need to distinguish the comparators91L-1to91L-n, hereinafter, they are simply referred to as a comparator91L, and when there is no need to distinguish the counters92L-1to92L-n, hereinafter, they are simply referred to as a counter92L.

FIG. 3is a block diagram illustrating an example of a specific configuration of the signal processing unit65L. The signal processing unit65L includes a data latch unit83L and a parallel-serial conversion unit84L, in addition to the AD converter81L and the reference voltage generation unit82L. The signal processing unit65L has a pipeline configuration for pipeline-transferring the pixel data digitized by the AD converter81L to the memory unit67L. In this case, the signal processing unit65L performs a digitization process by the AD converter81L within one horizontal period, and performs a process of transferring the digitized pixel data to the data latch unit83L in the next one horizontal period.

Meanwhile, the column decoder/sense amplifier66L is provided as a peripheral circuit in the memory unit67L. While the row decoder64L described above (seeFIG. 2) specifies the row address for the memory unit67L, the column decoder specifies the column address for the memory unit67L. Further, the sense amplifier amplifies a weak voltage, which is read through the hit lines from the memory unit67L, to a level that can be handled as a digital level. Then, the pixel data read out through the column decoder/sense amplifier66L is output to the outside of the logic board12through the data processing unit68L and the interface unit69L.

In addition, here, the case of having one column parallel AD converter81L is described as an example, but the present embodiment is not limited thereto, and it is possible to employ a configuration in which two or more AD converters81L are provided, and the two or more AD converters81L are subjected to the digitization process in parallel.

In this case, two or more AD converters81L are arranged, for example, in the extending direction of the signal line34of the pixel array unit31, in other words, they are arranged by being divided into upper and lower sides of the pixel array unit31. When two or more AD converters81L are provided, respectively, two or more (two systems) of the data latch units83L, the parallel-serial conversion units84L, and the memory units67L are provided corresponding thereto.

Thus, in a solid-state imaging device1employing a structure in which for example, two systems of AD converters81L and the like are provided, the row scanning is performed in parallel for every two pixel rows. Then, signals of the respective pixels of one pixel row are read to one side in the vertical direction of the pixel array unit31, and signals of the respective pixels of the other pixel row are read to the other side in the vertical direction of the pixel array unit31, and the signals are digitized in parallel by two AD converters81L. Similarly, the subsequent signal processes are performed in parallel. As a result, as compared with the case of performing row scan for each one pixel row, it is possible to perform high-speed readout of pixel data.

In addition, although detailed illustration and description thereof is omitted, the signal processing circuit41R also has the same configuration as that of the signal processing circuit41L. Then, the signal processing circuit41R mainly processes pixel signals from the unit pixel32in the right half region of the pixel array unit31.

In addition, hereinafter, the reference symbols of the respective units of the signal processing circuit41R, not shown, are denoted by replacing L in the reference symbols of the respective units of the signal processing circuit41L with R.

{1-3. Layout of Logic Board12}

FIG. 4illustrates an example of a layout of the logic board12. As illustrated inFIG. 4, the signal processing circuit41L and the signal processing circuit41R of the logic board12have the layouts of the same symmetry.

In the signal processing circuit41L, an AD conversion unit101L-1, a memory unit102L-1, a logic unit103L, a memory unit102L-2, and an AD conversion unit101L-2are stacked in order from the top. In addition, an interface unit104L-1and an interface unit104L-2are located on the left and right sides of the stacked portion. Furthermore, vias105L-1to105L-4are arranged in the upper, lower, right and left ends of the signal processing circuit41L.

For example, the current source61L, the AD converters81L-1to81L-n, the reference voltage generation unit82L, the data latch unit83L, and the parallel-serial conversion unit84L, which are illustrated inFIGS. 2 and 3, are disposed and arranged in the AD conversion units101L-1and101L-2.

In addition, in this example, the AD converter81L and the circuit portion associated therewith are arranged to be stacked in each of the three stages, in the AD conversion units101L-1and101L-2. In other words, the AD converter81L and the circuit portion associated therewith are arranged while being divided into six systems in the signal processing circuit41L. Then, the signal processing circuit41L performs row scanning, for example, for every six pixel rows in parallel.

Further, the pixel signal from each unit pixel32in the pixel array unit31is supplied to the respective AD converters81L disposed in the AD conversion units101L-1and101L-2through the vias105L-1to105L-4.

For example, the column decorder/sense amplifier66L and the memory unit67L, which are illustrated inFIG. 3, are dispersed and arranged in the memory units102L-1and102L-2. Then, the memory unit102L-1stores pixel data supplied from the AD conversion unit101L-1, and the memory unit102L-2stores pixel data supplied from the AD conversion unit101L-2.

For example, the decoder62L, the control unit63L, the row decoder64L, and the data processing unit68L, which are illustrated inFIG. 2, are arranged in the logic unit103L.

For example, the interface unit69L illustrated inFIG. 2is arranged in the interface units104L-1and104L-2, respectively.

In addition, since the signal processing circuit41R has the same layout as that of the signal processing circuit41L, the description thereof is omitted to avoid redundance.

Further, the configurations and layouts of the signal processing circuits41L and41R described above are examples, and a configuration and a layout other than those described above are possible.

{1-4. Imaging Process of Solid-State Imaging Device1}

Next, an imaging process of the solid-state imaging device1will be simply described with reference toFIG. 5andFIG. 6.

FIG. 5illustrates an example of a method of connecting the signal processing circuits41L and41R of the solid-state imaging device1and the external signal processing LSI121. Specifically, the signal processing LSI121is connected to the interface unit104L-1of the signal processing circuit41L and the interface unit104R-2of the signal processing circuit41R.

For example, when the solid-state imaging device1captures an image of an object141ofFIG. 6, pixel signals from the unit pixel32in the left half region of the pixel array unit31are supplied to the signal processing circuit41L, and pixel signals from the unit pixel32in the right half region are supplied to the signal processing circuit41R, in other words, the pixel signals corresponding to the left half part of the object141are supplied to the signal processing circuit41L, and the pixel signals corresponding to the right half part of the object141are supplied to the signal processing circuit41R.

The signal processing circuit41L generates the pixel data142L corresponding to the left half part of the object141, based on the pixel signals supplied from the pixel circuit21. Similarly, the signal processing circuit41R generates the pixel data142R corresponding to the right half part of the object141, based on the pixel signals supplied from the pixel circuit21.

Then, the signal processing circuit41L outputs the generated pixel data142L from the interface unit104L-1, and supplies the pixel data to the signal processing LSI121. The signal processing circuit41R outputs the generated pixel data142R from the interface unit104R-2, and supplies the pixel data to the signal processing LSI121.

The signal processing LSI121generates one piece of pixel data143by combining the pixel data142L and the pixel data142R, and outputs the generated pixel data143.

In this manner, since the left and right parts of pixel data are generated independently in the solid-state imaging device1, it is possible to speed up the process.

{1-5. Configuration Method of Left and Right Signal Processing Circuits41}

As described above, the respective signal processing circuits41have the common circuit pattern and the same function. Meanwhile, as described above, the signal processing circuit41L generates pixel data of the left half part of the object, and outputs the generated pixel data from the interface unit104L-1on the left side. Further, the signal processing circuit41R generates pixel data of the right half part of the object, and outputs the generated pixel data from the interface unit104R-2on the right side. In other words, the signal processing circuit41L operates as a circuit, which is located on the left side of the logic board12, and the signal processing circuit41R operates as a circuit, which is located on the right side of the logic board12.

Thus, each signal processing circuit41has both functions so as to be able to operate as either the signal processing circuit41L on the left side or the signal processing circuit41R on the right side. Then, each of the signal processing circuits41is configured so as to operate as the signal processing circuit41L on the left side or the signal processing circuit41R on the right side by a signal from the outside. In other words, a valid function and an invalid function of each of the signal processing circuits41are set by the signal from the outside.

Specifically, for example, as schematically illustrated inFIG. 7, the signal processing circuits41L and41R are respectively connected to an external substrate161, by bonding wires162L and162R. In addition, the substrate161may be provided in the solid-state imaging device1and the same package, or may be provided outside the package.

Then, the substrate161supplies a selection signal to the signal processing circuit41L through the bonding wire162L. The selection signal is, for example, one of the values of the power supply level (High) and the ground level (Low). The signal processing circuit41L includes a multiplexer171L and a core172L which are illustrated inFIG. 8. Then, the selection signal from the substrate161is input to the multiplexer171L, and the multiplexer171L supplies a setting signal indicating a value of 0 or 1 according to the selection signal to the core172L.

With respect to a setting signal, when performing the setting for the left circuit (signal processing circuit41L), the value is 0, and when performing the setting for the right circuit (signal processing circuit41R), the value is 1. Then, the core172L stores the value of the setting signal in a register, which is not shown, and the signal processing circuit41L operates according to the value of the register. For example, the value of the register of the signal processing circuit41L is set to 0, and the signal processing circuit41L operates as the signal processing circuit on the left side.

In addition, without being illustrated, a multiplexer171R and a core172R are also provided in the signal processing circuit41R, similar to the signal processing circuit41L. Then, the signal processing circuit41R is configured so as to operate as the signal processing circuit on the right side by the selection signal supplied from the substrate161through the bonding wire162R, by using the same method as in the signal processing circuit41L.

Further, since the signal processing circuit41L and the signal processing circuit41R have the same function, the function is duplicated. Thus, for the function, which may be performed by only one of the signal processing circuits41, the function of one of the signal processing circuits41is enabled and the function of the other of the signal processing circuits41is disabled by the selection signal.

{1-6. Manufacturing Method of Solid-State Imaging Device1}

Next, a manufacturing method of the solid-state imaging device1will be described with reference toFIG. 9toFIG. 13. In addition, inFIG. 9toFIG. 13, for clarity of illustration, only the pixel circuit21and the signal processing circuit41are illustrated, and the illustration of a wafer (semiconductor substrate) having the pixel circuit21and the signal processing circuit41formed thereon is omitted.

First, as illustrated inFIG. 9, pixel circuits21-1,21-2, . . . are formed on the wafer (semiconductor substrate) not shown. In this case, since the area of each pixel circuit21is greater than the exposure range of an exposure apparatus, separate exposure is used for exposure of each pixel circuit21.

Further, a scribe region22is provided in a longitudinal direction and a transverse direction between the adjacent pixel circuits21. In addition, inFIG. 9, the width of the scribe region22is shown while being widely exaggerated in order to facilitate understanding of illustration. This is also applied to the following drawings.

Further, inFIG. 9, only two pixel circuits21of 2 rows*1 column are illustrated, but in fact, pixel circuits21of numbers greater than two are formed so as to be two-dimensionally arranged.

Further, according to a manufacturing process other than inFIG. 9, as illustrated inFIG. 10, signal processing circuits41L-1,41R-1,41L-2,42R-2, . . . are formed on the wafer (semiconductor substrate) which is not illustrated. Among them, the signal processing circuit41L-1and the signal processing circuit41R-1are arranged on the same logic board12, and the signal processing circuit41L-2and the signal processing circuit41R-2are arranged on the same logic board12. In this case, since the area of the each signal processing circuit41is smaller than the exposure range of an exposure apparatus, one-shot exposure is used for the exposure of each signal processing circuit41.

Further, a scribe region42is provided in a longitudinal direction and a transverse direction between signal processing circuits41. It is of course that the scribe region42is provided between signal processing circuits41, which are arranged on the same logic board12.

Further, inFIG. 10, only four signal processing circuits41of 2 rows*2 columns are illustrated, but in fact, a larger number of signal processing circuits41are formed so as to be two-dimensionally arranged.

Next, as illustrated inFIG. 11, the wafer (hereinafter, referred to as a pixel wafer) having the pixel circuit21formed thereon and the wafer (hereinafter, referred to as a logic wafer) having the signal processing circuit41formed thereon are bonded, and the pixel wafer and the logic wafer are stacked.

Here, the areas of the signal processing circuits41and the pixel circuits21, which are respectively adjacent to the left and right through the scribe region42, are substantially the same, and the pixel wafer and the logic wafer are stacked such that the scribe region22of the pixel wafer and the scribe region42of the logic wafer are overlapped. Thus, the pixel circuits21are perfectly overlapped on the signal processing circuits41, which are adjacent to the left and right. For example, the pixel circuit21-1is perfectly overlapped on the signal processing circuit41L-1and the signal processing circuit41R-1, which are adjacent to the left and right through the scribe region42.

Further, the solid-state imaging device1is a back-illuminated type, and the pixel wafer and the logic wafer are stacked such that the substrate layer having the pixel circuit21of the logic wafer provided therein faces above and the wiring layer of the logic wafer and the wiring layer of the pixel wafer are adjacent.

In addition, hereinafter, a wafer in which the pixel wafer and the logic wafer are stacked is referred to as a stacked wafer.

Next, as indicated by thick dotted lines inFIG. 12, the stacked wafer is cut into units of chips. In other words, the stacked wafer is cut along the scribe region22of the pixel wafer provided around each pixel circuit21. In addition, the scribe region42of the logic wafer, which does not overlap with the scribe region22of the pixel wafer, is left as it is without being cut.

Thus, a solid-state imaging device in which the pixel circuit21is stacked on the signal processing circuits41, which are adjacent to the left and right, while the scribe region42is left is singulated. For example, as illustrated inFIG. 13, a solid-state imaging device1-1, in which the pixel circuit21-1is stacked on the signal processing circuits41L-1and41R-1, which are adjacent through the scribe region42, is singulated.

In this manner, even when the area of the pixel circuit21on the pixel substrate11is greater than the exposure range of an exposure apparatus, and separate exposure is necessary, each signal processing circuit41on the logic board12is manufactured by one-shot exposure, without using the separate exposure. Further, regardless of whether each signal processing circuit41is disposed in either one of the left and right of the solid-state imaging device1, the signal processing circuits41of the same circuit pattern are formed so as to be two-dimensionally arranged at a certain distance (i.e., scribe region42). Thus, for example, it is possible to reduce the types of the photomasks necessary for manufacture of the logic board12, and even an exposure apparatus without a photomask changing apparatus can manufacture the logic board12.

2. Second Embodiment

As described above, in the solid-state imaging device1, two signal processing circuits each independently performs a process while not being electrically connected. In contrast, in a second embodiment of the present technology, two signal processing circuits perform some processes in cooperation with each other while being electrically connected.

FIG. 14is a perspective view schematically illustrating a configuration example of a solid-state imaging device201according to the second embodiment of the present technology. In addition, here, inFIG. 14, the portions corresponding toFIG. 1are denoted by the same reference numerals, and the description of the portions of the same process is redundant, so the description thereof will be appropriately omitted.

As illustrated inFIG. 14, the solid-state imaging device201is a semiconductor chip of a structure (so-called, a stacked structure) in which the pixel substrate11and the logic board211are stacked, similar to the solid-state imaging device1.

The logic board211is different from the logic board12in that signal processing circuits241L and241R are provided instead of the signal processing circuits41L and41R. Further, the logic board211is different from the logic board12in that a wiring layer (hereinafter, referred to as inter-circuit wiring layer) for electrically connecting the signal processing circuit241L and the signal processing circuit241R is provided on the top of the logic board12. In other words, the pattern denoted by oblique lines on the logic board211ofFIG. 14represents a wiring pattern of the inter-circuit wiring layer, and the signal processing circuit241L and the signal processing circuit241R are electrically connected in the inter-circuit wiring layer.

Further, part of the layout of the signal processing circuits241L and241R is different from that of the signal processing circuits41L and41R, as described later with reference toFIG. 15.

In addition, when there is no need to distinguish the signal processing circuit241L and the signal processing circuit241R, hereinafter, they are simply referred to as a signal processing circuit241.

{2-2. Layout of Logic Board211}

FIG. 15illustrates an example of a layout of the logic board211. In addition, inFIG. 15, the illustration of the inter-circuit wiring layer is omitted. Further, inFIG. 15, the portions corresponding toFIG. 4are denoted by the same reference numerals, and the description of the portions of the same process will be omitted.

The signal processing circuit241L is different from the signal processing circuit41L ofFIG. 4in that the interface unit104L-1is omitted, and only the interface unit104L-2is provided. Similarly, the signal processing circuit241R is different from the signal processing circuit41R ofFIG. 4in that the interface unit104R-1is omitted, and only the interface unit104R-2is provided.

{2-3. Imaging process of solid-state imaging device201}

Next, an imaging process of the solid-state imaging device201will be simply described with reference toFIG. 6andFIG. 15.

For example, when the solid-state imaging device201captures an object141ofFIG. 6, pixel signals from the unit pixels32in the left half region of the pixel array unit31are supplied to the signal processing circuit241L and pixel signals from the unit pixels32in the right half region are supplied to the signal processing circuit241R, in other words, the pixel signals corresponding to the left half part of the object141are supplied to the signal processing circuit241L, and the pixel signals corresponding to the right half part of the object141are supplied to the signal processing circuit241R.

The signal processing circuit241L generates the pixel data142L corresponding to the left half part of the object141, based on the pixel signals supplied from the pixel circuit21. Similarly, the signal processing circuit241R generates the pixel data142R corresponding to the right half part of the object141, based on the pixel signals supplied from the pixel circuit21.

The processes up to here are the same as in the solid-state imaging device1described above.

Then, logic unit103L of the signal processing circuit241L supplies the generated pixel data142L to the logic unit103R of the signal processing circuit241R through the inter-circuit wiring layer, which is not shown.

The logic unit103R generates one piece of pixel data143by combining the pixel data142L supplied from the signal processing circuit241L and the pixel data142R that the logic unit103R generates. Then, the logic unit103R outputs the generated pixel data143to the outside through the interface unit104R-2.

In this manner, the solid-state imaging device201can generate and output one completed pixel data without using a device, such as an external LSI, differently from the solid-state imaging device1. Therefore, the signal processing LSI121does not have to be externally provided and it is possible to reduce costs.

In addition, even in the solid-state imaging device201, similar to the solid-state imaging device1, the signal processing circuit241L and the signal processing circuit241R are configured so as to operate as either one of the left and right signal processing circuits by the method described with reference toFIG. 7andFIG. 8.

Next, a manufacturing method of the solid-state imaging device201will be described with reference toFIG. 9andFIG. 10, which are previously illustrated, andFIG. 16toFIG. 19. In addition, inFIG. 16toFIG. 19, similar toFIG. 9toFIG. 13, for clarity of illustration, only the pixel circuit21and the signal processing circuit241are illustrated, and the illustration of a wafer (semiconductor substrate) having the pixel circuit21and the signal processing circuit241formed thereon is omitted.

First, a pixel wafer in which pixel circuits21are arranged two-dimensionally through the scribe region22, and a logic wafer in which signal processing circuits241are arranged two-dimensionally through the scribe region42are manufactured by a method similar to the method described above with reference toFIG. 9andFIG. 10.

Next, as illustrated inFIG. 16, the inter-circuit wiring layer is formed on the top layer of the logic wafer. In addition, since the inter-circuit wiring layer has a size substantially the same as that of the pixel circuit21of the pixel substrate11, it is formed by using separate exposure. Two signal processing circuits241(for example, the signal processing circuit241L-1and the signal processing circuit241R-1), which are disposed in the same solid-state imaging device201, are electrically connected through the inter-circuit wiring layer.

In addition, for example, a manufacturer of the logic wafer may manufacture a logic wafer before exposure on which only a metal film for an inter-circuit wiring layer is formed, and deliver it to a manufacturer of the solid-state imaging device201. Then, for example, the manufacturer of the solid-state imaging device201may stack the pixel wafer and the logic wafer after forming the inter-circuit wiring layer of the logic wafer by the separate exposure. Thus, even a manufacturer without having separate exposure equipment can manufacture the logic wafer.

Next, as illustrated inFIG. 17, the pixel wafer and the logic wafer are stacked by a method similar to the method described above with reference toFIG. 11.

Then, as illustrated inFIG. 18, the stacked wafer is cut into units of chips similar to the manufacturing process described above with reference toFIG. 12. Thus, for example, as illustrated inFIG. 19, the solid-state imaging device201-1, in which the pixel circuit21-1is stacked on the signal processing circuits241L-1and241R-1, which are adjacent through the scribe region42, is singulated.

In addition, although the example described above represents an example in which the inter-circuit wiring layer is formed on the top layer of the logic board211, the inter-circuit wiring layer may be formed on the layer below the top layer. For example, when a plurality of wiring layers are provided in the signal processing circuit241, the signal processing circuit241L and the signal processing circuit241R may be connected in the wiring layer, which is formed on the layer below the top layer of the logic board211.

Further, for example, the signal processing circuit241L and the signal processing circuit241R may be connected through a plurality of wiring layers. In other words, a plurality of the inter-circuit wiring layers may be formed. Further, not only a wiring for connecting the signal processing circuit241L and the signal processing circuit241R, but also an internal wiring of each signal processing circuit241(for example, a wiring between elements) may be provided in the inter-circuit wiring layer.

Further, even when the inter-circuit wiring layer is disposed in any layer of the logic board211, for example, among respective layers of the logic board211, the inter-circuit wiring layer is formed by separate exposure, and the other layer is formed by one-shot exposure. In addition, when the inter-circuit wiring layer is formed by different manufacturers as described above, it is preferable to form the inter-circuit wiring layer on the top layer of the logic board211.

In a third embodiment of the present technology, the left and right signal processing circuits are electrically connected by a method different from that in the second embodiment.

Specifically,FIG. 20is a perspective view schematically illustrating a configuration example of a solid-state imaging device301according to the third embodiment of the present technology. Similar to the solid-state imaging device1and the solid-state imaging device201, the solid-state imaging device301is a semiconductor chip of a structure (i.e., a stacked structure) in which the pixel substrate311(FIG. 21) having the pixel circuit321formed thereon and the logic board312(FIG. 21) having the signal processing circuits341L and341R formed thereon are stacked.

A pixel array unit331, similar to the pixel array unit31of the pixel circuit21ofFIG. 1, is formed on the pixel circuit321. Further, the pixel circuit321has the same circuit configuration as that of the pixel circuit21described above with reference toFIG. 2. The signal processing circuits341L and341R have the same circuit configuration as that of the signal processing circuits41L and41R described above with reference toFIG. 2andFIG. 3. The logic board312has the same layout as that of the logic board12described above with reference toFIG. 4. In this manner, the solid-state imaging device301has substantially the same circuit configuration and layout as that of the solid-state imaging device1.

However, the solid-state imaging device301is different from the solid-state imaging device1, and the signal processing circuit341L and the signal processing circuit341R are electrically connected in the pixel substrate311.

Specifically,FIG. 21illustrates a XXI-XXI sectional view of the solid-state imaging device301ofFIG. 20. In other words,FIG. 21is an outside of the pixel array unit331of the pixel circuit321, and illustrates a cross section of the solid-state imaging device301on the front side inFIG. 20.

Since the solid-state imaging device301is a back-illuminated type imaging element, the wiring layer of the pixel substrate311and the wiring layer of the logic board312are arranged so as to be adjacent. Thus, the substrate layer of the pixel substrate311is disposed on the top, and the substrate layer of the logic board312is disposed on the bottom.

On the substrate layer of the pixel substrate311, wirings351L and351R are formed on the outside of the pixel array unit331. The wiring351L is disposed above the signal processing circuit341L, and the wiring351R is disposed above the signal processing circuit341R.

Then, the wiring351L is connected to the wiring layer of the signal processing circuit341L, through a via352L formed in the pixel substrate311. Further, the wiring351L is connected to a wiring354L through a via353L. The wiring354L is connected to a wiring356L through a via355L. The wiring356L is connected to a wiring358through a via357L.

Then, the wiring351R is connected to the wiring layer of the signal processing circuit341R, through a via352R formed in the pixel substrate311. Further, the wiring351R is connected to a wiring354R through a via353R. The wiring354R is connected to a wiring356R through a via355R. The wiring356R is connected to a wiring358through a via357R.

Thus, the wiring layer of the signal processing circuit341L and the wiring layer of the signal processing circuit341R are electrically connected through the via352L, the wiring351L, the via353L, the wiring354L, the via355L, the wiring356L, the via357L, the wiring358, the via357R, the wiring356R, the via355R, the wiring354R, the via353R, the wiring351R, and the via352R.

Accordingly, the solid-state imaging device301can also generate and output one piece of pixel data obtained by capturing an object, by the method described above with reference toFIG. 6andFIG. 15, similar to the solid-state imaging device201.

In addition, the wirings351L and351R, the vias352L and352R, and the like of the pixel circuit321are formed, for example, during the manufacture of the pixel wafer described above with reference toFIG. 9.

Further, the number of layers of the wiring layer of the pixel substrate311ofFIG. 21is an example, and it is possible to set any number of layers. Further, for example, a wiring358for electrically connecting the signal processing circuit341L and the signal processing circuit341R in the wiring layer of the pixel substrate311may be provided in any wiring layer of the pixel substrate311, and also, for example, may be formed by being divided into a plurality of wiring layers.

Hereinafter, modifications of the embodiments of the present technology described above will be described.

{4-1. Modifications of Configuration of Solid-State Imaging Device}

(Modification of Logic Board)

The example of providing two signal processing circuits on the logic board has been described above, but three or more signal processing circuits may be provided.

Further, the circuit patterns and the sizes of the signal processing circuits provided on a single logic board are not necessary all the same, and it is also possible to mix signal processing circuits having different circuit patterns and sizes. Here, the manufacturing process is simpler and the manufacturing cost is less in the case of providing signal processing circuits of the same circuit pattern on the logic board, as compared to the case of mixing signal processing circuits having different circuit patterns and sizes.

Further, the example has been described above in which the solid-state imaging device has a stacked structure of two layers of the pixel substrate and the logic board, but the present technology can be applied to a stacked structure of three layers or more. For example, a logic board may be further stacked under the logic board12ofFIG. 1(in other words, a surface opposite to the surface adjacent to the pixel substrate11of the logic board12). In this case, for example, placing the memory units102L-1to102R-2included in the signal processing circuits41L and41R on the logic board of the added bottom layer is considered.

Further, in the case of providing two or more logic boards, not all layers of the logic boards have to be manufactured by using one-shot exposure, and some logic boards may be manufactured by using separate exposure. For example, in the example described above, the logic board of the bottom layer having the memory units102L-1to102R-2provided therein may be manufactured by using separate exposure.

Further, as described above, in the case where the signal processing circuits are connected in the inside of the logic board, not all layers of the logic boards have to be manufactured by using one-shot exposure, and some layers may be manufactured by using separate exposure.

(Modification of Method of Connecting Signal Processing Circuit)

In addition, the second and third embodiments of the present technology describe the example in which the left and right signal processing circuits are electrically connected in the solid-state imaging device, but they may be connected in the outside of the solid-state imaging device.

FIG. 22illustrates an example in which the signal processing circuit41L and the signal processing circuit41R of the solid-state imaging device1are connected, in the outside of the solid-state imaging device1. In addition, in this example, the solid-state imaging device1is mounted on the package. Further, inFIG. 22, for clarity of illustration, only the signal processing circuits41L and41R are illustrated in the solid-state imaging device1.

The signal processing circuit41L is connected to the conductive pattern412formed in the package401through bonding wire411L. Similarly, the signal processing circuit41R is connected to the conductive pattern412through bonding wire411R. Accordingly, the signal processing circuit41L and the signal processing circuit41R are electrically connected through the bonding wires411L,411R and the conductive pattern412.

In addition thereto, the signal processing circuit41L and the signal processing circuit41R may be externally electrically connected through a lead frame or the like.

Further, when the signal processing circuit41L and the signal processing circuit41R are connected, in the outside of the solid-state imaging device1, as compared to the case of being internally connected, the number of wirings that can be mounted is limited. Therefore, the case where it is difficult to synthesize the left and right parts of pixel data in the solid-state imaging device1is assumed. In this case, for example, the analog signals may be shared by connecting signal lines of predetermined same analog signals (e.g., a signal line of a reference voltage, a ground line, and the like) between the signal processing circuit41L and the signal processing circuit41R.

For example, in the case of generating the left and right parts of pixel data in the different signal processing circuits41, differences occur in the color and brightness of the left and right parts of pixel data due to the difference in the characteristics of the respective signal processing circuits41, and the boundary of the synthetic part of two pieces of pixel data may be seen sometimes. Therefore, sharing a predetermined analog signal of each signal processing circuit41enables reducing the difference in characteristics of each signal processing circuit41and makes the boundary of the synthetic part of pixel data inconspicuous.

(Modification of AD Conversion Method)

Further, although the case of employing a column-parallel AD conversion method in the solid-state imaging device has been described above with reference toFIG. 2, a pixel AD parallel conversion method may be employed.

FIG. 23schematically illustrates the configurations of a pixel substrate511and a logic board512in the case of employing a pixel AD conversion method.

A pixel circuit521including a pixel array unit531is formed on the pixel substrate511, similar to the pixel substrate11ofFIG. 1. Further, a signal processing circuit541L and a signal processing circuit541R having the same circuit pattern are formed so as to be arranged to the left and right through the scribe region42, on the logic board512, similar to the logic board12ofFIG. 1.

Then, in the pixel array unit531of the pixel substrate511, pixel units (groups) are two-dimensionally arranged in a matrix, with a region including a two-dimensional arrangement of pixels of a predetermined number as one unit, and a via532is formed for each pixel unit. Meanwhile, in the signal processing circuit541L and the signal processing circuit541R, a circuit unit (inFIG. 23, pixel AD unit) including the AD converter81(FIG. 2), the memory unit67(FIG. 2), and the like is provided for each pixel unit of the pixel array unit531. Further, a via23is formed corresponding to the pixel unit, for each pixel AD unit.

In this manner, since it is possible to speed up the reading speed of the pixel signal by employing the pixel parallel AD conversion method, it is possible to lengthen the stop period of the AD converter81, and as a result, it is possible to reduce power consumption.

The moisture-resistant ring (also referred to as a seal ring or a guard ring or a structure) of the logic board can be basically formed by the same method as the past method. For example, the moisture-resistant ring is formed by the same method as the general method so as to surround each signal processing circuit individually. However, when the inter-circuit wiring layer electrically connecting the signal processing circuits is formed on the logic board as the second embodiment described above with reference toFIG. 14, if the moisture-resistant ring is made by the same method as in the past, the wiring and the moisture-resistant ring of the inter-circuit wiring layer interfere with each other. In other words, the moisture-resistant ring formed at the end of the signal processing circuit and the wiring of the inter-circuit wiring layer interfere with each other in a portion at which the wiring of the inter-circuit wiring layer passes through the end of the signal processing circuit.

Thus, hereinafter, a method of avoiding the interference between the wiring of the inter-circuit wiring layer and the moisture-resistant ring will be described.

First, a first method of avoiding the interference between the wiring of the inter-circuit wiring layer and the moisture-resistant ring will be described with reference toFIG. 24toFIG. 26.

FIG. 24is a plan view schematically illustrating a configuration example of a logic board601so as to avoid the interference between the wiring of the inter-circuit wiring layer and the moisture-resistant ring.

The logic board601is different from the logic board211ofFIG. 14described above in that a signal processing circuit611L and a signal processing circuit611R having the same circuit pattern are provided through the scribe region42, instead of the signal processing circuits241L and241R. Further, the inter-circuit wiring layer electrically connecting the signal processing circuit611L and the signal processing circuit611R are formed on the top layer of the logic board601, similar to the logic board211. In this example, the signal processing circuit611L and the signal processing circuit611R are electrically connected by the wirings612-1to612-3of the inter-circuit wiring layer.

Further, a moisture-resistant ring613is formed so as to surround the outer periphery of the signal processing circuits611L and611R along the vicinity of the outer periphery of the logic board601.

Here, the structure of the moisture-resistant ring613will be described with reference toFIG. 25andFIG. 26.FIG. 25is a cross-sectional view schematically illustrating a cross section of the moisture-resistant ring613, andFIG. 26is a perspective view schematically illustrating a part of the moisture-resistant ring613.

The moisture-resistant ring613includes a wall621made of a material of a contact, dummy wirings622-1to622-6, walls623-1to623-5made of a material of a via, a wall624, and a dummy wiring625.

The dummy wirings622-1to622-6and the dummy wiring625are respectively formed in different wiring layers of the logic board601, and are not used for signal transfers. In this example, the wiring layers of the logic board601are stacked in seven layers on a substrate layer631made of, for example, a silicon substrate. Then, the dummy wiring622-1is formed on a first wiring layer at the bottom of the logic board601. The dummy wirings622-2to622-6are formed on the second to sixth wiring layers of the logic board601. The dummy wiring625is formed on a seventh wiring layer at the top of the logic board601.

The dummy wirings622-1to622-6and the dummy wiring625have substantially the same rectangular ring-like shape, and are formed so as to surround the outer peripheries of the signal processing circuits611L and611R, along the vicinity of the outer periphery of the logic board601, in each wiring layer.

The wall621, the walls623-1to623-5, and the wall624have substantially the same rectangular ring-like shape, and are formed so as to surround the outer peripheries of the signal processing circuits611L and611R, along the vicinity of the outer periphery of the logic board601.

The wall621is formed by the same process as that of a contact for connecting the substrate layer631and the first wiring layer so as to connect the substrate layer631and the dummy wiring622-1.

The walls623-1to623-5are formed by the same process as that of a via for connecting respective wiring layers, from the first wiring layer to the sixth wiring layer. The wall623-1connects the dummy wiring622-1and the dummy wiring622-2. The wall623-2connects the dummy wiring622-2and the dummy wiring622-3. The wall623-3connects the dummy wiring622-3and the dummy wiring622-4. The wall623-4connects the dummy wiring622-4and the dummy wiring622-5. The wall623-5connects the dummy wiring622-5and the dummy wiring622-6.

The wall624is formed by the same process as that of a via for connecting the sixth wiring layer and the seventh wiring layer, and connects the dummy wiring622-6and the dummy wiring625.

For example, copper is used for the first wiring layer to the sixth wiring layer, the wall621is made of tungsten, and the dummy wirings622-1to622-6and the walls623-1to623-5are made of copper. Further, an insulating film made of, for example, a low-K material having a low dielectric constant is used for the interlayer insulation film632from the surface of the substrate layer631to the upper end of the sixth wiring layer. Then, the first to sixth wiring layers are used for the transmission of high-speed signals, for example.

Meanwhile, for example, aluminum is used for the seventh wiring layer, and the dummy wiring625is made of aluminum. Further, the wall624is made of, for example, tungsten. Further, an oxide film (for example, a silicon oxide film) having a higher dielectric constant and water resistance than those of an interlayer insulation film632are used for the upper end of the sixth wiring layer to the interlayer insulation film633thereabove. Then, the seventh wiring layer is used for, for example, the transmission of low-speed signals such as a power supply. Further, the seventh wiring layer is the inter-circuit wiring layer.

In this manner, the moisture-resistant ring613forms a wall surrounding the logic board601, by the wall621to the dummy wiring625, and prevents infiltration of moisture from the side of the logic board601to the signal processing circuits611L and611R.

Further, the moisture-resistant ring613is not provided between the signal processing circuit611L and the signal processing circuit611R. Accordingly, the wirings612-1to612-3connecting the signal processing circuit611L and the signal processing circuit611R do not interfere with the moisture-resistant ring613.

In addition, the size of the outer periphery of the moisture-resistant ring613is substantially the same as that of the pixel circuit21and greater than the exposure range of an exposure apparatus. Accordingly, separate exposure is used during the formation of the layer (including the moisture-resistant ring613) above the substrate layer631of the logic board601.

Further, the moisture-resistant ring613does not necessarily have to be formed so as to surround all of the periphery of the logic board601, and may be formed so as to surround only a part of the periphery of the logic board601, for example, in a range in which the moisture resistance can be ensured.

Further, for example, similar to the case where three or more signal processing circuits are disposed on the logic board, the moisture-resistant ring may be formed so as to include all the signal processing circuits in the inside or surround the periphery or a part of the periphery of the logic board.

Next, a second method for avoiding the interference between the wiring and the moisture-resistant ring of the inter-circuit wiring layer will be described with reference toFIG. 27toFIG. 33.

FIG. 27is a plan view schematically illustrating a configuration example of a logic board651formed so as to avoid the interference between the wiring and the moisture-resistant ring of the inter-circuit wiring layer.

The logic board651is different from the logic board601ofFIG. 24described above in that a signal processing circuits661L and a signal processing circuit661R having the same circuit pattern are provided through the scribe region42, instead of the signal processing circuits611L and611R. Further, an inter-circuit wiring layer for electrically connecting the signal processing circuit661L and the signal processing circuit661R is formed on the top layer of the logic board651, similar to the logic board601. In the example, the signal processing circuit661L and the signal processing circuit661R are electrically connected by the wirings662-1to662-3of the inter-circuit wiring layer.

Further, the logic board651is different from the logic board601in that moisture-resistant rings663L and663R are formed instead of the moisture-resistant ring613. The moisture-resistant ring663L is formed so as to surround the periphery of the signal processing circuit661L, along the vicinity of the outer periphery of the signal processing circuit661L. The moisture-resistant ring663R is formed so as to surround the periphery of the signal processing circuit661R, along the vicinity of the outer periphery of the signal processing circuit661R.

Here, the structure of the moisture-resistant ring663R will be described with reference toFIG. 28toFIG. 33. In addition, although the detailed description is omitted, the moisture-resistant ring663L also has substantially the same structure as that of the moisture-resistant ring663R. Further, hereinafter, the reference symbols of the portions of the moisture-resistant ring663L corresponding to the respective portions of the moisture-resistant ring663R are represented by replacing “R” with “L” in the reference symbols of the respective portions of the moisture-resistant ring663R.

FIG. 28is a cross-sectional view schematically illustrating a cross section of the portions other than the regions A1R-1to A1R-3and regions A2R-1to A2R-3of the moisture-resistant ring663R.FIG. 29is a perspective view schematically illustrating a part of the portions other than the regions A1R-1to A1R-3and regions A2R-1to A2R-3of the moisture-resistant ring663R.

FIG. 30is a cross-sectional view schematically illustrating a cross section of a portion through which the wiring662-1of the region A1L-1of the moisture-resistant ring663L and the region A1R-1of the moisture-resistant ring663R passes.FIG. 31is a perspective view schematically illustrating the vicinity of the region A1R-1of the moisture-resistant ring663R.

FIG. 32is a cross-sectional view schematically illustrating a cross section at the same position as that of the portion through which the wiring662-1passes in the region A1L-1of the moisture-resistant ring663L, in the region A2R-1of the moisture-resistant ring663R.FIG. 33is a perspective view schematically illustrating the vicinity of the region A2R-1of the moisture-resistant ring663R. In addition, inFIG. 33, only a dummy wiring675R of the top layer is transmitted.

The moisture-resistant ring663R includes a wall671R, dummy wirings672R-1to672R-6, walls673R-1to673R-5, a wall674R, and a dummy wiring675R, and has substantially the same structure as that of the moisture-resistant ring613described above with reference toFIG. 25andFIG. 26. In other words, the moisture-resistant ring663R has a stacked structure of seven layers, similar to the moisture-resistant ring613, and is made of the same material as that of the moisture-resistant ring613.

An insulation film made of a low-K material is used for an interlayer insulation film682from the surface of the substrate layer681to the top of the sixth wiring layer, for example, similarly to the interlayer insulation film632of the logic board601. Further, an oxide film (for example, a silicon oxide film) is used for an interlayer insulation film683above the top of the sixth wiring layer, for example, similarly to the interlayer insulation film633of the logic board601.

However, the moisture-resistant ring663R is different from the moisture-resistant ring613, the wall674R and the dummy wiring675R are not formed in some parts, and discontinuous. Specifically, the wall674R and the dummy wiring675R are discontinuous in a part through which the wirings662-1to662-3in the regions A1R-1to A1R-3pass in the left side of the moisture-resistant ring663R.

For example, as illustrated inFIG. 30andFIG. 31, the wall674R and the dummy wiring675R are discontinuous so as not to interfere with the wiring662-1in the part through which the wiring662-1of the region A1R-1passes. Further, without being illustrated, the wall674R and the dummy wiring675R are discontinuous so as not to interfere with the wirings662-2and662-3, in the part through which the wiring662-2of the region A1R-2passes and the part through which the wiring662-3of the region A1R-3passes.

Similarly, the wall674L of the moisture-resistant ring663L and the dummy wiring675L are discontinuous so as not to interfere with the wirings662-1to662-3in a part through which the wirings662-1to662-3in the regions A1L-1to A1L-3pass in the right side of the moisture-resistant ring663L.

Further, the wall674R of the moisture-resistant ring663R is discontinuous in a part corresponding to a discontinuous portion of the wall674L in the regions A1L-1to A1L-3of the moisture-resistant ring663L. For example, in the wall674R, in the region A2R-1on the right side of the moisture-resistant ring663L, the same portion as the discontinuous portion of the wall674L in the region A1L-1on the right side of the moisture-resistant ring663L is discontinuous, as illustrated inFIG. 32andFIG. 33. Further, without being illustrated, in the regions A2R-2and A2R-3on the right side of the moisture-resistant ring663R of the wall674R, the same portions as the discontinuous portions of the wall674L in the regions A1L-2and A1L-3on the right side of the moisture-resistant ring663L are discontinuous.

Similarly, in the wall674L of the moisture-resistant ring663L, the portions corresponding to the discontinuous portions of the wall674R in the regions A1R-1to A1R-3of the moisture-resistant ring663R are discontinuous.

Thus, the discontinuous portion of the wall674L of the moisture-resistant ring663L and the discontinuous portion of the wall674R of the moisture-resistant ring663R are same, and the wall674R and the wall674L have a shape of the same symmetry.

In addition, the dummy wiring675R is continuous without interruption in the regions A2R-1to A2R-3. Similarly, the dummy wiring675L is continuous without interruption in the regions A2L-1to A2L-3.

As described above, in the moisture-resistant ring663R, the wall671R to dummy wiring675R form a wall surrounding the periphery of the signal processing circuit661R so as to prevent infiltration of moisture to the signal processing circuits661R from the side of the logic board651. Similarly, in the moisture-resistant ring663L, the wall671L to the dummy wiring675L form a wall surrounding the periphery of the signal processing circuit661L so as to prevent infiltration of moisture to the signal processing circuits661L from the side of the logic board651.

Further, as described above, the moisture-resistant rings663L and663R do not interfere with the wirings662-1to662-3connecting the signal processing circuit661L and the signal processing circuit661R.

Further, since the discontinuous interval of the wall674R and the dummy wiring675R of the moisture-resistant ring663R are very short and the water resistance of the interlayer insulation film683is also high, the moisture performance of moisture-resistant ring663R is hardly deteriorated. Similarly, since the discontinuous interval of the wall674L and the dummy wiring675L of the moisture-resistant ring663L are very short and the water resistance of the interlayer insulation film683is also high, the moisture performance of moisture-resistant ring663L is hardly deteriorated.

Further, since the wall674L of the moisture-resistant ring663L and the wall674R of the moisture-resistant ring663R have the same shape, the wall674L and the wall674R can be exposed by using, for example, the same photomask, and thus it is possible to reduce costs.

In addition, the moisture-resistant rings663L and663R do not necessarily have to be formed so as to surround all peripheries of the signal processing circuits661L and661R, and may be formed so as to surround only a part of the peripheries, in a range capable of ensuring the moisture resistance.

Further, a discontinuous portion of the wall674L and the wall674R other than the portion through which the wirings662-1to662-3pass is not necessarily provided. However, if the discontinuous portion is not provided, the wall674L and the wall674R do not have the same shape, and thus it becomes necessary to use separate exposure.

In addition, for example, even when three or more signal processing circuits are disposed on the logic hoard, it is possible to form moisture-resistant rings of respective signal processing circuits so as to avoid interference of the wiring connecting respective signal processing circuits, in the same manner.

Next, a manufacturing method of moisture-resistant rings663L and663R of the logic board651will be described with reference toFIG. 34toFIG. 40.

In addition, hereinafter, the left sides ofFIG. 34toFIG. 40each schematically illustrates a cross section of a portion at which the wirings662-1to662-3do not pass, in a portion at which the right side of the moisture-resistant ring663L and the left side of the moisture-resistant ring663R are adjacent. In contrast, the right sides ofFIG. 34toFIG. 40each schematically illustrates a cross section of a portion at which the wiring662-1passes, in a portion at which the right side of the moisture-resistant ring663L and the left side of the moisture-resistant ring663R are adjacent.

Further, hereinafter, the wall671L to the dummy wiring672L-6of the moisture-resistant ring663L, the wall671R to the dummy wiring672R-6of the moisture-resistant ring663R, and the interlayer insulation film682have already been formed, and a step of forming a portion above the interlayer insulation film682will be described. In addition, one-shot exposure is used for the exposure in the processes up to here.

First, as illustrated inFIG. 34, an oxide film691is deposited on the interlayer insulation film682.

Next, as illustrated inFIG. 35, the oxide film691is etched so as to form grooves692L and692R. The groove692L is formed so as to substantially overlap the wall673L-5through the dummy wiring672L-6, as viewed from above. However, the groove692L is intended to form the wall674L of the moisture-resistant ring663L, and is not formed in the portion in which the wall674L described above is discontinuous. Similarly, the groove692R is formed so as to substantially overlap the wall673R-5through the dummy wiring672R-6, as viewed from above. However, the groove692R is intended to form the wall674R of the moisture-resistant ring663R, and is not formed in the portion in which the wall674R described above is discontinuous.

Further, as described above, since the wall674R and the wall674L have the same shape, the groove692L and the groove692R have the same shape. Accordingly, the groove692L and the groove692R can be respectively formed by using the same photomask, through one-shot exposure.

Further, as illustrated inFIG. 36, a metal film693made of tungsten is deposited on the oxide film691. In this case, the metal film693is deposited thick such that the grooves692L and692R are completely buried.

Next, as illustrated inFIG. 37, the metal film693is left in the grooves692L and692R, and the metal film693on the oxide film691is removed by polishing. This allows the walls674L and674R made of tungsten to be formed.

Next, as illustrated inFIG. 38, the metal film694made of aluminum is deposited on the oxide film691.

Next, as illustrated inFIG. 39, the metal film694is etched. Thus, the inter-circuit wiring layer including the wirings662-1to662-3and the dummy wirings675L and675R are formed. The separate exposure described above is used for forming the inter-circuit wiring layer.

Last, as illustrated inFIG. 40, an oxide film is deposited on the inter-circuit wiring layer. Thus, an interlayer insulation film683is formed in conjunction with the oxide film691deposited in the process described with reference toFIG. 34. In addition, for example, a protective film made of polyimide is further formed on the interlayer insulation film.

In addition, the number and material of layers of the moisture-resistant ring and the material of the interlayer insulation film which are described above are an example, and can be changed as necessary.

{4-2. Modification of Imaging Process}

Although the example in which one sheet of pixel data is divided into the left and right and generated by respective signal processing circuits has been described above, a method of dividing pixel data may be freely varied depending on the number or the layout of the signal processing circuit provided in the logic board. For example, the pixel data may be divided vertically, or may be divided into n (n is 3 or more).

Further, for example, without dividing the pixel data, a plurality of (for example, two) signal processing circuits respectively generate entire pixel data, and pixel data obtained by adding the pixel values of a plurality of pieces of the generated pixel data may be generated. Thus, it is possible to reduce random noise or absorb the difference in the characteristics of the AD converter81, thereby allowing the image quality to be improved.

In this case, the pixel values of a plurality of pieces of pixel data may be weighted and added. For example, two signal processing circuits respectively generate entire pixel data, and the respective pieces of pixel data are weighted with a weight of 0.5 and added, such that it is possible to achieve pixel data, which is an average value of the pixel values of the two pieces of entire pixel data.

Further, for example, in addition to dividing the pixel data, the pixel data of the same region may be generated by a plurality of signal processing circuits and added. For example, the left signal processing circuit and the right signal processing circuit may be respectively provided in duplicate so as to create two pieces of pixel data of the left half of the subject and two pieces of pixel data of the right half of the subject. Then, for example, the pixel data obtained by adding the pixel values of two pieces of pixel data of the left half and the pixel data obtained by adding the pixel values of two pieces of pixel data of the right half may be added.

{4-3. Modification of Scope of the Present Technology}

Although the case where the present technology is applied to the solid-state imaging device has been described, the present technology can be applied to other semiconductor devices of a stacked structure in which the chip size is greater than the exposure range of the exposure apparatus.

5. Electronic Equipment

It is possible to use the solid-state imaging device employing the present technology as an imaging unit (i.e., image-capturing unit), in general, an electronic apparatus, such as an imaging device like a digital still camera and a video camera, a portable terminal device having an imaging function, such as a mobile phone, and a copying machine using the solid-state imaging device as the image-reading unit. Further, there is also the case in which the above modular form is mounted on the electronic apparatus; in other words, a camera module is used as the imaging device.

FIG. 41is a block diagram illustrating a configuration example of an imaging device (e.g., camera device)701as an example of an electronic apparatus employing the present technology.

As illustrated inFIG. 41, the imaging device701includes an optical system including a lens group711and the like, an imaging element712, a DSP circuit713which is a camera signal processing unit, a frame memory714, a display device715, a recording device716, an operation system717, a power supply system718, and the like. The DSP circuit713, the frame memory714, the display device715, the recording device716, the operation system717, and the power supply system718are configured to be connected to each other through a bus line719.

The lens group711receives incident light (i.e., image light) from a subject and focuses the incident light on the imaging plane of the imaging element712. The imaging element712converts the incident light focused on the imaging plane by the lens group711into an electrical signal in units of pixels, and outputs a pixel signal.

The display device715is a panel-type display device, such as a liquid crystal display device or an organic electro luminescence (EL) display device, and displays a moving image or a still image captured by the imaging element712. The recording device716records the moving image or the still image captured by the imaging element712in a recording medium, such as a memory card, a video tape, or a digital versatile disc (DVD).

The operation system717issues operation commands for various functions of the imaging device701, under the operation by the user. The power supply system718appropriately supplies various power types, which are operating power of the DSP circuit713, the frame memory714, the display device715, the recording device716, and the operation system717, to these supply targets.

Such imaging device701is applied to a video camera or a digital still camera, and a camera module for a mobile device, such as a smartphone and a mobile phone. Then, it is possible to use a solid-state imaging device according to the embodiments described above as the imaging element712, in the imaging device701. This makes it possible to reduce the cost of the imaging device701.

In addition, the embodiments of the present technology are not limited to the embodiments described above, and various modifications can be made without departing from the scope of the present technology.

Further, for example, the present technology can have the following configurations.

A solid-state imaging device including:

a first substrate having a pixel circuit including a pixel array unit formed thereon; and

a second substrate having a plurality of signal processing circuits formed thereon, wherein the plurality of signal processing circuits are arranged adjacent to one another and include a spacing region therebetween, and

wherein the first substrate and the second substrate are stacked.

The solid-state imaging device according to (1), wherein each of the signal processing circuits have a same set of functions.

The solid-state imaging device according to any one of (1) to (2), wherein the same set of functions includes operating as a same signal processing circuit.

The solid-state imaging device according to any one of (2) to (3), wherein a function to be enabled and a function to be disabled are configured in each of the signal processing circuits in response to one or more external signals.

The solid-state imaging device according to any one of (1) to (4), wherein a first signal processing circuit of the plurality of signal processing circuits is configured to generate first pixel data based on a pixel signal of a pixel in a first region of the pixel array unit, and

wherein a second signal processing circuit of the plurality of signal processing circuits is configured to generate second pixel data based on a pixel signal of a pixel in a second region different from the first region of the pixel array unit.

The solid-state imaging device according to any one of (1) to (5), wherein a first signal processing circuit of the plurality of signal processing circuits and a second signal processing circuit of the plurality of signal processing circuits are electrically connected.

The solid-state imaging device according to (6), wherein the first signal processing circuit and the second signal processing circuit are electrically connected through a first wiring layer formed on the second substrate.

The solid-state imaging device according to (7), wherein the first wiring layer is formed on a top layer of a wiring layer of the second substrate.

The solid-state imaging device according to any one of (7) to (8), further comprising: a first moisture-resistant structure that surrounds at least a part of a periphery of the first signal processing circuit; and a second moisture-resistant structure that surrounds at least a part of a periphery of the second signal processing circuit.

The solid-state imaging device according to (9), wherein the first signal processing circuit and the second signal processing circuit have a common circuit pattern, wherein the first wiring layer is formed on the top layer of the wiring layer of the second substrate, and includes a top layer of the first moisture-resistant structure and a top layer of the second moisture-resistant structure,

wherein the top layer of the first moisture-resistant structure, and a first wall connecting the top layer of the first moisture-resistant structure and a layer one below the top layer are not formed at a first portion through which a wiring of the first wiring layer of the first moisture-resistant structure passes, and

wherein the top layer of the second moisture-resistant structure, a second wall connecting the top layer of the second moisture-resistant structure, and a layer one below the top layer are not formed at a second portion through which a wiring of the first wiring layer of the second moisture-resistant structure passes.

The solid-state imaging device according to (10), wherein the first wall is not formed at a third portion of the first moisture-resistant structure corresponding to the second portion of the second moisture-resistant structure, and

wherein the second wall is not formed at a fourth portion of the second moisture-resistant structure corresponding to the first portion of the first moisture-resistant structure.

The solid-state imaging device according to (10), wherein a wiring layer except for the first wiring layer of the second substrate is formed by a one-shot exposure, and the first wiring layer is formed by a separate exposure.

The solid-state imaging device according to (10), wherein interlayer insulation films of second and subsequent wiring layers are made of a low-K film, the second wiring layer being one below the first wiring layer, and

wherein an interlayer insulation film above the second wiring layer is made of an insulation film having a water resistance higher than that of the low-K film.

The solid-state imaging device according to (7), further comprising a moisture-resistant structure that surrounds at least a part of a periphery of the second substrate.

The solid-state imaging device according to (14), wherein at least a portion of one or more layers of the respective signal processing circuits are formed by a one-shot exposure, and

wherein a layer having a moisture-resistant structure formed thereon is formed by the separate exposure.

The solid-state imaging device according to (6), wherein the first signal processing circuit and the second signal processing circuit are electrically connected through a wiring formed on the first substrate.

The solid-state imaging device according to (16), wherein the wiring formed on the first substrate is formed in an area outside of the pixel array unit, and

wherein the first signal processing circuit and the second signal processing circuit are connected to the wiring formed on the first substrate through a via formed on the first substrate.

The solid-state imaging device according to (6), wherein the first signal processing circuit and the second signal processing circuit are electrically connected to each other in an area that is external to the solid-state imaging device.

The solid-state imaging device according to (18), wherein the solid-state imaging device is mounted to a package and the first signal processing circuit and the second signal processing circuit are electrically connected through a conductive pattern on the package.

The solid-state imaging device according to any one of (18) to (19), wherein signal lines of a same analog signal of the first signal processing circuit and the second signal processing circuit are electrically connected, in an area that is external to the solid-state imaging device.

The solid-state imaging device according to (6), wherein the first signal processing circuit and the second signal processing circuit are electrically connected to a substrate by one or more bond wires, and wherein the substrate is at least one of provided in the solid-state imaging device, provided in a same package, and provided outside the package.

The solid-state imaging device according to any one of (6) to (21), wherein the first signal processing circuit is configured to generate first pixel data based on a pixel signal of a pixel in a first region of the pixel array unit, and supply the generated first pixel data to the second signal processing circuit, and

wherein the second signal processing circuit is configured to generate second pixel data based on a pixel signal of a pixel in a second region different from the first region of the pixel array unit, and combine the generated second pixel data with the first pixel data.

The solid-state imaging device according to any one of (6) to (21), wherein the first signal processing circuit is configured to generate first pixel data based on a pixel signal of a pixel in a predetermined region of the pixel array unit, and supply the generated first pixel data to the second signal processing circuit, and

wherein the second signal processing circuit is configured to generate second pixel data based on a pixel signal of a pixel of the pixel array unit in the same region as that of the first signal processing circuit, and generate third pixel data by adding the first pixel data and the second pixel data.

The solid-state imaging device according to any one of (1) to (23), wherein a third substrate is stacked on a surface on an opposite side of a surface adjacent to the first substrate of the second substrate.

The solid-state imaging device according to (24), further comprising a memory on the third substrate that is configured to store pixel data obtained by analog-to-digital converting a pixel signal of each pixel in the pixel array unit.

The solid-state imaging device according to any one of claim (1) to (25), further comprising an analog-to-digital (AD) conversion unit on the second substrate, wherein the AD conversion unit is configured to convert a pixel signal of each pixel in the pixel array unit in units of columns of the pixel array unit.

The solid-state imaging device according to any one of (1) to (25), further comprising an analog-to-digital (AD) conversion unit on the second substrate, wherein the AD conversion unit is configured to convert a pixel signal of each pixel in the pixel array unit in units of regions that include a two-dimensional array of pixels of a predetermined number in the pixel array unit.

The solid-state imaging device according to any one of (1) to (27), wherein the pixel circuit is formed by a separate exposure, and

wherein at least a portion of one or more layers of respective signal processing circuits are formed by a one-shot exposure.

The solid-state imaging device according to any one of (1) to (28), wherein a first signal processing circuit of the plurality of signal processing circuits and a second signal processing circuit of the plurality of signal processing circuits are formed by a same one-shot exposure.

The solid-state imaging device according to any one of (1) to (29), wherein the spacing region between the plurality of signal processing circuits is a scribe region.

A manufacturing method of a solid-state imaging device, including:

forming a pixel circuit including a pixel array unit so as to be two-dimensionally arranged through a scribe region on a first semiconductor substrate, by using one or more separate exposures;

forming a signal processing circuit that processes a pixel signal of each pixel in the pixel array unit so as to be two-dimensionally arranged through a scribe region on a second semiconductor substrate, by using a one-shot exposure;

stacking the first semiconductor substrate and the second semiconductor substrate such that the scribe region of the first semiconductor substrate overlaps the scribe region of the second semiconductor substrate; and

cutting a semiconductor substrate including the first semiconductor substrate and the second semiconductor substrate that are stacked, along the scribe region of the first semiconductor substrate.

The manufacturing method of a solid-state imaging device according to (31), wherein the signal processing circuit includes a first signal processing circuit and a second signal processing circuit arranged adjacent to one another and include the scribe region of the second semiconductor substrate therebetween, and wherein a wiring layer that electrically connects the first signal processing circuit and the second signal processing circuit which are disposed in the same solid-state imaging device is formed on the second semiconductor substrate.

The manufacturing method of a solid-state imaging device according to (32), wherein the wiring layer is formed on a top layer of a wiring layer of the second semiconductor substrate.

The manufacturing method of a solid-state imaging device according to any one of (32) to (33), further including:

forming a first moisture-resistant structure that surrounds at least a part of a periphery of the first signal processing circuit; and

forming a second moisture-resistant structure that surrounds at least a part of a periphery of the second signal processing circuit.

The manufacturing method of a solid-state imaging device according to any one of (32) to (33), further including:

forming a moisture-resistant structure that surrounds at least a part of an outer periphery of the first and second signal processing circuits which are disposed on the same solid-state imaging device.

The manufacturing method of a solid-state imaging device according to any one of (31), wherein the signal processing circuit includes a first signal processing circuit and a second signal processing circuit arranged adjacent to one another and include the scribe region of the second semiconductor substrate therebetween, and wherein a wiring and a via for electrically connecting the first signal processing circuit and the second signal processing circuit which are disposed on the same solid-state imaging device are formed on the first semiconductor substrate.

An electronic apparatus including:

a solid-state imaging device including a first substrate having a pixel circuit including a pixel array unit formed thereon and a second substrate having a plurality of signal processing circuits formed thereon, wherein the plurality of signal processing circuits are arranged adjacent to one another and include a spacing region therebetween, and wherein the first substrate and the second substrate are stacked.

REFERENCE SIGNS LIST