SEMICONDUCTOR DEVICE FABRICATION METHOD USING A DEPOSITION APPARATUS WITH A CONTOURED WAFER CARRIER RING

A method includes placing a wafer on a step of a carrier ring in a first vacuum enclosure such that a backside surface of the wafer contacts the step, depositing a film on an exposed portion of the backside surface of the wafer while the backside surface of the wafer is in contact with the step, and depositing a semiconductor device on a front side of the wafer which is opposite to the backside surface of the wafer. The carrier ring includes a bottom surface surrounding an opening in the carrier ring, an upper top surface, a lower top surface of the step, and an inner surface which connects the upper top surface and the lower top surface, and which is inclined outward at a non-zero taper angle relative to the vertical direction which perpendicular to the lower top surface of the step.

FIELD

The present disclosure relates generally to the field of semiconductor manufacturing, and specifically to a semiconductor device fabrication method using a deposition apparatus with a contoured wafer carrier ring.

BACKGROUND

A wafer carrier ring can be employed in a semiconductor manufacturing equipment to support a wafer at a peripheral portion while exposing a backside surface of the wafer to a deposition ambient. A backside film can be deposited on the backside surface of the wafer. Reliable placement of the wafer on the wafer carrier ring requires an increase in the contact area between the wafer and the wafer carrier ring, which decreases an effective area for deposition of the backside film. Reduction of the contact area between the wafer and the carrier ring can result in misplacement or tilting of the wafer, which results in misprocessing of the wafer.

SUMMARY

According to an aspect of the present disclosure, a method includes placing a wafer on a step of a carrier ring in a first vacuum enclosure such that a backside surface of the wafer contacts the step; depositing a film on an exposed portion of the backside surface of the wafer while the backside surface of the wafer is in contact with the step; and depositing a semiconductor device on a front side of the wafer which is opposite to the backside surface of the wafer. The carrier ring includes a bottom surface surrounding an opening in the carrier ring, an upper top surface, a lower top surface of the step, and an inner surface which connects the upper top surface and the lower top surface, and which is inclined outward at a non-zero taper angle relative to the vertical direction which perpendicular to the lower top surface of the step.

According to another aspect of the present disclosure, a carrier ring for a deposition apparatus, comprises an annular bottom surface having a circular bottom inner periphery; an upper top surface having a circular upper outer periphery and having a closed upper inner periphery; a lower top surface vertically offset downward relative to the upper top surface and comprising a circular lower inner periphery that defines an opening in the carrier ring and comprising a closed lower outer periphery; and a contoured inner sidewall that connects the closed upper inner periphery and the closed lower outer periphery and comprising at least one edge at which a respective pair of inner sidewall segments are adjoined to each other at a respective angle that is greater than or less than 180 degrees.

DETAILED DESCRIPTION

As discussed above, the embodiments of the present disclosure are directed to a semiconductor device fabrication method and to a deposition apparatus with a contoured wafer carrier ring and methods for operating the same, the various aspects of which are described below.

Conventional carrier rings in a backside deposition chamber include tabs for supporting peripheral portions of the backside surface of the wafer. While increasing the size of the tabs prevents accidental dropping of the wafer into an opening in a carrier ring, the large tabs increase the peripheral area on the backside surface of the wafer on which a backside film is not deposited. Conversely, decreasing the size of the tabs decreases the peripheral area without the deposited backside film but increases the probability of misplacement of the wafer on the carrier ring and/or “fall-through” of the wafer through an opening in the carrier ring. The embodiments of the present disclosure provide a contoured carrier ring that improvise the reliability of the placement of a wafer on the carrier while minimizing the area of a peripheral portion of the bottom surface on which the backside film is not deposited.

Referring toFIGS.1A and1B, an exemplary deposition apparatus10according to an embodiment of the present disclosure is illustrated in a plan view. The exemplary deposition apparatus10may comprise a cluster tool which comprises a loading/unloading unit1000and at least one deposition unit2000that is enclosed within a vacuum enclosure190. Suitable load locks (not shown) may be provided between the loading/unloading unit1000and the at least one deposition unit2000, and between the loading/unloading unit1000and the ambient. In one embodiment, the at least one deposition unit2000may comprise a plurality of deposition units2000. If the deposition unit2000comprises a plasma-type unit, such as a plasma enhanced chemical vapor deposition (PECVD) chamber, then a radio-frequency (RF) generator1500may be provided for each deposition unit2000, and may be electrically coupled to the bottom electrode and the top electrode of each deposition unit2000. Alternatively, RF generator1500may be omitted if the deposition unit comprises a non-plasma type deposition unit, such as a low pressure chemical vapor deposition chamber or an atomic layer deposition chamber.

The loading/unloading unit1000is configured to mount at least one open cassette, at least one SMIF (Standard Manufacturing Interface) pod, and/or at least one FOUP (Front Opening Unified Pod). Each cassette, each SMIF pod, and/or each FOUP are configured to hold a plurality of wafers (e.g., silicon wafers), such as 25-30 wafers. The SMIF and the FOUP are an airtight container that can house a wafer cassette, and can be sealed to provide an airtight environment to wafers located within the wafer cassette. At least one transfer robot (not shown) can be provided within the loading/unloading unit1000and/or within the at least one deposition unit2000to transport wafers between the loading/unloading unit1000and the at least one deposition unit2000.

Referring toFIGS.2A and2B, a deposition unit2000of the deposition apparatus10ofFIGS.1A and1Bis illustrated. The deposition unit2000is a deposition apparatus that includes a support20, a carrier ring40having an opening therethrough and overlying the support20, and at least one dielectric spacer30interposed between the support20and the carrier ring40and providing mechanical support to the carrier ring40. In one embodiment, if the deposition unit2000comprises a plasma-type deposition unit, such as a PECVD chamber, then the support20may comprise a bottom electrode, and the deposition unit2000additionally includes a top electrode60overlying the carrier ring40.

A vacuum enclosure190(shown inFIGS.1A and1B) encloses the bottom electrode20, the carrier ring40, the at least one dielectric spacer30, and the top electrode60. The bottom electrode20can be vertically spaced from a bottom wall of the vacuum enclosure190by an insulating support structure18, which may comprise an electrical feedthrough that electrically connects the bottom electrode20to a driver output node of the RF generator1500. Another driver output node (such as a ground node) of the RF generator1500can be electrically connected to the top electrode60.

The deposition unit2000comprises a processing gas distribution manifold24that is configured to supply at least one processing gas into the vacuum enclosure190. In one embodiment, the processing gas distribution manifold24may comprise a showerhead including an array of holes26therethrough and functioning as a top plate of the bottom electrode20. In this case, a processing gas feedthrough pipe28may extend through the vacuum enclosure190and the insulating support structure18and may be connected to an opening in the bottom electrode20so that the at least one processing gas can be supplied into and can be distributed out of the bottom electrode60toward the backside surface52of the wafer50. In one embodiment, the processing gas may comprise a mixture of silane and at least one of ammonia, nitrous oxide and/or nitrogen to deposit a silicon nitride stress compensation film94on the backside surface52of the wafer50, as described below with respect toFIG.8. Other suitable processing gases used to deposit a film by CVD or ALD may also be used.

The deposition unit2000also optionally comprises a purge gas distribution manifold64that is configured to supply at least one purge and/or cleaning gas into the vacuum enclosure190. In one embodiment, the purge gas distribution manifold64may comprise a showerhead including an array of holes66therethrough and functioning as a bottom plate of the top electrode60. In this case, a purge gas feedthrough pipe62may extend through the vacuum enclosure190and may be connected to an opening in the top electrode60so that the at least one purge and/or cleaning gas can be supplied into and can be distributed out of the top electrode60. In one embodiment, the purge gas may comprise nitrogen gas and the cleaning gas may comprise a mixture of NF3and argon.

The bottom electrode20, the top electrode60, and the carrier ring40may have a continuous rotational symmetry (i.e., a symmetry that provides invariance upon rotation at any angle) around a vertical axis VA passing through a geometrical center GC of the carrier ring40except for patterns of discrete openings in the bottom electrode20and optionally except for the pattern of the holes (26,66) in the respective gas distribution manifolds (24,64). As used herein, a geometrical center of an element refers to the center of gravity of a hypothetical element occupying the same volume as the element.

A set of K discrete holes21that are azimuthally spaced apart around the vertical axis VA by an angle 2p/K can be provided within the bottom electrode20, where K is an integer greater than one. For example, 2≤K≤8. In the embodiment shown inFIG.2B, K=3. A set of K lift pins22can vertically extend through the set of K discrete holes21. The set of K lift pins22can be configured to move vertically during placement and lifting of a wafer50on the carrier ring40. The wafer50that is placed on the carrier ring40comprises a front surface51that faces the top electrode60and a backside surface52that faces the bottom electrode20. A plasma zone27is provided between the backside surface52of the wafer50and the top surface of the bottom electrode20. During generation of plasma in the plasma zone27, i.e., during a deposition process, the set of K lift pins22can be retracted into or below the bottom electrode20to prevent damages to the lift pins22and to prevent arcing.

The at least one dielectric spacer30may comprise a plurality of discrete dielectric spacers30that are laterally spaced apart from each other. Lateral openings32are present between the discrete dielectric spacers30so that the at least one purge and/or cleaning gas that flows out of the gas distribution manifold64can diffuse into the volume of the plasma zone27during a deposition step. A vacuum port (not illustrated) can be provided in a wall of the vacuum enclosure190.

If present, the radio-frequency signal generator1500(illustrated inFIG.1B) can be configured to apply a radio-frequency electrical bias voltage across the bottom electrode20and the top electrode60and to generate a plasma of the at least one processing gas in the plasma zone27between the bottom electrode20and a horizontal plane including the annular bottom surface48of the carrier ring40.

The carrier ring40includes geometrical features that facilitate self-aligned placement of the wafer50over an opening46in the carrier ring40and minimizes the area of a peripheral portion of the backside surface52of the wafer50that contacts the carrier ring40.FIGS.3A-3Care various vertical cross-sectional profiles of a carrier ring40within the first configuration of the deposition unit illustrated inFIGS.2A and2B.

Referring collectively toFIGS.2A,2B, and3A-3C, the carrier ring40comprises an annular bottom surface48having a circular bottom inner periphery CBIP and facing the top surface of the bottom electrode20. The circular bottom inner periphery CBIP defines a lateral extent of the opening46through the carrier ring40, and has a shape of a circle having a center at the vertical axis VA that passes through the geometrical center GC of the carrier ring40. The diameter of the circular bottom inner periphery CBIP is herein referred to as an opening diameter DO.

The carrier ring40further comprises an upper top surface43facing a bottom surface of the top electrode60, having a circular upper outer periphery CUOP, and having a closed upper inner periphery CUIP. The circular upper outer periphery CUOP has a shape of a circle having a center at the vertical axis VA. The circular upper outer periphery CUOP has a shape of a circle in the first configuration illustrated inFIGS.2B and3A-3C, but generally may have a non-circular shape in other configurations. The closed upper inner periphery CUIP is connected to a top periphery of a contoured inner sidewall41. The diameter of the closed upper inner periphery CUIP is herein referred to as a sidewall top diameter DST.

In addition, the carrier ring40comprises a step140which protrudes outward from the bottom end of the contoured inner sidewall41. The step140includes a lower top surface42configured to support the wafer50during deposition of a film on the bottom surface52of the wafer50. The lower top surface42vertically offset downward relative to the upper top surface43and comprising a circular lower inner periphery CLIP that defines the opening46of the carrier ring40and comprising a closed lower outer periphery CLOP. The circular lower inner periphery CLIP may be congruent with the circular bottom inner periphery CBIP. The closed lower outer periphery CLOP is connected to a bottom periphery of the contoured inner sidewall41. The diameter of the closed lower outer periphery CLOP is herein referred to as a sidewall bottom diameter DSB. Generally, the sidewall bottom diameter DSB is greater than the opening diameter DO, and is less than the sidewall top diameter DST. An outer periphery of the backside surface52of the wafer50contacts the lower top surface42of the step140upon placement of the wafer50on the carrier ring40.

The contoured inner sidewall41connects the closed upper inner periphery CUIP and the closed lower outer periphery CLOP. The contoured inner surface41may be inclined outward at a non-zero taper angle relative to the vertical direction, as shown inFIG.3A. For example, the contoured inner surface41may be a flat surface that is inclined outward away from the opening46at the taper angle of 10 to 60 degrees, such as 30 to 45 degrees, relative to the vertical direction which is perpendicular to the lower top surface42of the step140. As used herein, inclined outward away from the opening46means that the closed upper inner periphery CUIP at the top of the sidewall41is located farther in the radial outward direction from the circular lower inner periphery CLIP than the closed lower outer periphery CLOP at the bottom of the sidewall41is located from the circular lower inner periphery CLIP.

In another embodiment, the contoured inner sidewall41may be inclined outward and comprise and/or consist of a laterally-concave surface, as shown inFIG.3B. As used herein, a laterally-concave surface refers to a surface having a concave vertical cross-sectional profile, as shown inFIG.3B. In the embodiment shown inFIG.3B, the contoured inner sidewall41may comprise a plurality of inner sidewall segments (411,412) and at least one edge, such as an arc-shaped horizontally-extending edge49H, at which a respective pair of inner sidewall segments (411,412) are adjoined to each other at an angle less than 180 degrees. In other words, the outward taper angles (as measured relative the vertical direction in a vertical cross-sectional view) of the inner sidewall segments (411,412) may be different from each other, such that the bottom surface segment411has a greater outward taper angle than the top surface segment412. As used herein, an arc refers to a segment of a circle having any angle not greater than 2p.

In another embodiment, the contoured inner sidewall41may be inclined outward and comprise and/or consist of a laterally-convex surface, as shown inFIG.3C. As used herein, a laterally-convex surface refers to a surface having a convex vertical cross-sectional profile, as shown inFIG.3C. In the embodiment shown inFIG.3C, the contoured inner sidewall41may comprise a plurality of inner sidewall segments (411,412) and at least one edge, such as an arc-shaped horizontally-extending edge49H, at which a respective pair of inner sidewall segments (411,412) are adjoined to each other at an angle greater than 180 degrees. In other words, the outward taper angles (as measured relative the vertical direction in a vertical cross-sectional view) of the inner sidewall segments (411,412) may be different from each other, such that the top surface segment412has a greater outward taper angle than the bottom surface segment411.

In general, a contoured inner sidewall41may comprise at least one an arc-shaped horizontally-extending edge49H having an azimuthal angle of at least p/24 around a vertical axis VA passing through a geometrical center GC of the carrier ring40. In the illustrated example ofFIGS.2B and3B-3C, the azimuthal angle g can be 2p. In one embodiment, the contoured inner sidewall41comprises a first surface segment411having a first outward taper angle relative to a vertical direction, and a second surface segment412having a second outward taper angle relative to the vertical direction that is different from the first outward taper angle. In one embodiment, the first horizontally-concave surface segment411may have a bottom edge that coincides with the closed lower outer periphery CLOP, and the second horizontally-concave surface segment412may have a top edge that coincides with the closed upper inner periphery CUIP.

FIGS.4A-4Dare sequential schematic vertical cross-sectional views of a deposition unit2000during a wafer50transfer and placement according to an embodiment of the present disclosure.

Referring toFIG.4A, a robot blade70may carry a wafer50over the carrier ring40while the lift pins22are raised above the bottom electrode20. The wafer50can be laterally centered relative to the carrier ring40. In other words, the center of the wafer50may be aligned to the vertical axis passing through the geometrical center of the carrier ring40.

Referring toFIG.4B, the robot blade70may be lowered until the wafer50is suspended on the lift pins22. Subsequently, the robot blade70may be laterally retracted so that the robot blade70does not have any areal overlap with the wafer50in a top-down view.

Referring toFIG.4C, the lift pins22are vertically retracted, i.e., moved downward, until the wafer50contacts the lower top surface42of the step140of the carrier ring40. The wafer50is positioned on the carrier ring40such that a periphery of a bottom surface of the wafer50contacts the lower top surface42of the carrier ring40.

Referring toFIG.4D, the lift pins22are further retracted until the top tips of the lift pins22are positioned below the horizontal plane including the top surface of the bottom electrode20. An insulating, semiconductor or conductive film can be subsequently deposited on a backside surface52of the wafer50by providing the processing gases through the processing gas manifold24.

FIG.5is a top-down view of a second configuration of the deposition unit of FIG.2A.FIGS.6A-6Care various vertical cross-sectional profiles of a carrier ring40within the second configuration of the deposition unit illustrated inFIGS.2A and5along the vertical plane X-X′ ofFIG.5.FIGS.7A-7Fare various vertical cross-sectional profiles of the carrier ring40within the second configuration of the deposition unit illustrated inFIGS.2A and5along the vertical plane Y-Y′ ofFIG.5.

Referring collectively toFIGS.2A,5,6A-6C, and7A-7F, the “circular” upper outer periphery CUOP of the upper top surface43of the carrier ring40may have a non-circular shape. In one embodiment, the carrier ring40may comprise a contoured inner sidewall (44,45,47) including first inner sidewall surface segments44, second inner sidewall surface segments45and vertical surface segments47. The first inner sidewall surface segments44have a respective arc-shaped top periphery located at a distance of a first radius R1from a vertical axis VA passing through a geometrical center GC of the carrier ring40. The second inner sidewall surface segments45have a respective arc-shaped top periphery located at a distance of a second radius R2from the vertical axis VA. The second radius R2is greater than the first radius R1. In one embodiment, the arc-shaped top peripheries of the first inner sidewall surface segments44and the second inner sidewall surface segments45are located within a same horizontal plane, such as the horizontal plane including the upper top surface43of the carrier ring40.

In one embodiment, the closed lower outer periphery CLOP of the lower top surface42has a shape of a circle. In one embodiment, the closed upper inner periphery CUIP of the upper top surface43has a stepped, non-circular shape as illustrated inFIG.5.

The first inner sidewall surface segments44have a respective arc-shaped bottom periphery located at a distance of a third radius R3from the vertical axis VA passing through the geometrical center GC of the carrier ring40. The second inner sidewall surface segments45have a respective arc-shaped bottom periphery, which may or may not be located at the distance of the third radius R3from the vertical axis VA. The third radius R3is less than the first radius R1, and is greater than the maximum radius of the wafer50that is placed over the carrier ring40. The arc-shaped bottom peripheries of the first inner sidewall surface segments44and the second inner sidewall surface segments45coincide with the closed lower outer periphery CLOP of the lower top surface42.

Generally, the closed lower outer periphery CLOP of the lower top surface42may or may not be a circle. In one embodiment, the closed lower outer periphery CLOP of the lower top surface42may be a circle, and the second inner sidewall surface segments45have a respective arc-shaped bottom periphery located at the distance of the third radius R3from the vertical axis VA. In another embodiment, the closed lower outer periphery CLOP of the lower top surface42may not be a circle, and the second inner sidewall surface segments45have a respective arc-shaped bottom periphery located at the distance that is greater than the third radius R3from the vertical axis VA.

The lower top surface42has a circular lower inner periphery CLIP having a shape of a circle. The radius of this circle is herein referred to as a fourth radius R4. The fourth radius R4can be one half of the opening diameter DO.

The vertical surface segments47can be contained within a respective vertical plane including the vertical axis VA and azimuthally spaced apart from one another around the vertical axis VA. In one embodiment, each of the vertical surface segments47may be adjoined to a slanted edge49S of a respective one of the first inner sidewall surface segments44and to a slanted edge49S of a respective one of the second inner sidewall surface segments45. As used herein, a slanted edge refers to an edge contained entirely within a vertical plane and having a uniform or non-uniform slant angle, i.e., a taper angle, with respective to a vertical direction.

In one embodiment, a total of 2N vertical surface segments47can be provided, in which N is an integer greater than 2. The contoured inner sidewall (44,45,47) may have an N-fold rotational symmetry around the vertical axis VA. In one embodiment, the vertical surface segments47comprise: first vertical surface segments471, within which each neighboring pair is azimuthally spaced from each other around the vertical axis VA by 2p/N, N being an integer greater than 2; and second vertical surface segments472, within which each neighboring pair is azimuthally spaced from each other around the vertical axis VA by 2p/N.

In one embodiment, a neighboring pair of the first vertical surface segment471and the second vertical surface segment472separated by a respective one of the second inner sidewall surface segments45is azimuthally spaced from each other around the vertical axis VA by a first angle a that is not greater than p/N. Another neighboring pair of the first vertical surface segment471and a second vertical surface segment472separated by a respective one of the first inner sidewall surface segments44is azimuthally spaced from each other around the vertical axis VA by a second angle b that is not greater than p/N. The sum of the first angle a and the second angle b may equal p/N. In one embodiment, each first inner sidewall surface segments44may have an azimuthal extent of the first angle a, and each second inner sidewall surface segments45may have an azimuthal extent of the second angle b.

In the embodiment ofFIG.6A, the first inner sidewall surface segments44may be inclined outward at a non-zero taper angle relative to the vertical direction. For example, the first inner sidewall surface segments44may be a flat surface that is inclined outward away from the opening46at the taper angle of 10 to 60 degrees, such as 30 to 45 degrees, relative to the vertical direction which is perpendicular to the lower top surface42of the step140.

In the embodiment ofFIG.6B, the first inner sidewall surface segments44may comprise horizontally-concave surface segments. In one embodiment, each of the first inner sidewall surface segments44comprises a continuous horizontally-concave surface segment.

In the embodiment ofFIG.6C, the first inner sidewall surface segments44may comprise horizontally-convex surface segments. In one embodiment, each of the first inner sidewall surface segments44comprises a continuous horizontally-convex surface segment.

In some embodiments, such as embodiments illustrated inFIGS.7B and7E, the second inner sidewall surface segments45may comprise horizontally-concave surface segments. In the embodiment ofFIG.7B, each of the second inner sidewall surface segments45comprises a continuous horizontally-concave surface segment. In the embodiment ofFIG.7E, each of the second inner sidewall surface segments45comprises a plurality of inner sidewall segments (451,452) and at least one edge, such as an arc-shaped horizontally-extending edge49H, at which a respective pair of inner sidewall segments (451,452) are adjoined to each other at an angle less than 180 degrees. In other words, the outward taper angles (as measured relative the vertical direction in a vertical cross-sectional view) of the inner sidewall segments (451,452) may be different from each other, such that the bottom surface segment451has a greater outward taper angle than the top surface segment452. The surface segments451and452are located at different heights from each other. The arc-shaped horizontally-extending edge49H has a radius of curvature Rc less than the second radius R2.

In other embodiments, such as embodiments illustrated inFIGS.7D and7F, the second inner sidewall surface segments45may comprise horizontally-convex surface segments. In the embodiment ofFIG.7F, each of the second inner sidewall surface segments45comprises a continuous horizontally-convex surface segment. In the embodiment ofFIG.7D, each of the second inner sidewall surface segments45comprises a plurality of inner sidewall segments (451,452) and at least one edge, such as an arc-shaped horizontally-extending edge49H, at which a respective pair of inner sidewall segments (451,452) are adjoined to each other at an angle greater than 180 degrees. In other words, the outward taper angles (as measured relative the vertical direction in a vertical cross-sectional view) of the inner sidewall segments (451,452) may be different from each other, such that the top surface segment452has a greater outward taper angle than the bottom surface segment451. The surface segments451and452are located at different heights from each other. The arc-shaped horizontally-extending edge49H has a radius of curvature Rc less than the first radius R1and the second radius R2.

In some embodiments, the contoured inner sidewall (44,45,47) may comprise connecting surface segments453that connects a respective pair of surface segments (451,452) that are inclined outward at a non-zero taper angle. In one embodiment, the connecting surface segments453may comprise horizontal sector-shaped surface segments having an azimuthal extent of the second angle b.

In some embodiments illustrated inFIGS.7C,7D, and7E, arc-shaped bottom peripheries of the first inner sidewall surface segments44coincide with first segments of the closed lower outer periphery CLOP of the lower top surface42, and arc-shaped bottom peripheries of the second inner sidewall surface segments (such as the bottom surface segments452) coincide with second segments of the closed lower outer periphery CLOP of the lower top surface42. As discussed above, the closed lower outer periphery CLOP of the lower top surface42may, or may not, have a shape of a circle.

In some embodiments, arc-shaped bottom peripheries of the second inner sidewall surface segments45coincide with segments of the closed lower outer periphery CLOP of the lower top surface42as illustrated inFIGS.7A-7F. In some embodiments, the second inner sidewall surface segments45have a concave or convex vertical cross-sectional profile as illustrated inFIGS.7B and7F.

In summary, the contoured inner sidewall (44,45,47) connects the closed upper inner periphery CUIP of the upper top surface43and the closed lower outer periphery CLIP of the lower top surface42, and comprises at least one edge (49H,49S) at which a respective pair of inner sidewall segments {(451,452,453); (44,47); or (45,47)} are adjoined to each other at a respective angle, which may be orthogonal if the edge is vertical, or may be non-orthogonal if the edge is horizontal.

In some embodiments, the contoured inner sidewall (44,45,47) comprises vertical surface segments47contained within a respective vertical plane including a vertical axis VA passing through a geometrical center GC of the carrier ring40; the vertical surface segments47are azimuthally spaced apart from one another around the vertical axis VA; and the at least one edge comprises a plurality of slanted edges49S at which a respective one of the vertical surface segments47is adjoined to a respective azimuthally-extending surface segment (44,45) of the contoured inner sidewall {41, (44,45,47)}.

In some embodiments, the at least one edge comprises an arc-shaped horizontally-extending edge49H having an azimuthal angle (g, a, or b) of at least p/24 around a vertical axis VA passing through a geometrical center GC of the carrier ring40. In some embodiments, the contoured inner sidewall {41, (44,45,47)} comprises: a first (e.g., bottom) horizontally-concave surface segment (411or451) having a first outward taper angle relative to a vertical direction; and a second (e.g., top) horizontally-concave surface segment (412or452) having a second outward taper angle relative to the vertical direction, which is different from the first outward taper angle. In some embodiments, the first horizontally-concave surface segment (411or451) is adjoined to the second horizontally-concave surface segment (412or452) at the arc-shaped horizontally-extending edge49H. In some embodiments, the first horizontally-concave surface segment451is adjoined to the second horizontally-concave surface segment452through a horizontal surface segment453that has an edge which coincides with at the arc-shaped horizontally-extending edge49H.

In one embodiment, a contoured inner sidewall41may comprise at least one an arc-shaped horizontally-extending edge49H having an azimuthal angle of at least p/24 around a vertical axis VA passing through a geometrical center GC of the carrier ring40. In the illustrated example ofFIGS.2B and3B-3C, the azimuthal angle g can be 2p. Alternatively, the azimuthal angle (a or b) is not greater than p/3 as illustrated inFIGS.5,6A-6C, and7A-7C.

In one embodiment, the first (e.g., bottom) horizontally-concave surface segment (411or451) may have a bottom edge that coincides with the closed lower outer periphery CLOP, and the second (e.g., top) horizontally-concave surface segment (412or452) may have a top edge that coincides with the closed upper inner periphery CUIP.

FIG.8illustrates a semiconductor device80, such as a three-dimensional NAND memory device located on the front surface51of the wafer50. The device80includes a vertically alternating stack of insulating layers82and electrically conductive layers86, and a two-dimensional array of memory openings vertically extending through the vertically alternating stack (82,86). The electrically conductive layers86may comprise word lines of the three-dimensional NAND memory device. A memory opening fill structure88may be formed within each memory opening. The memory opening fill structure88may include a memory film and a vertical semiconductor channel contacting the memory film. The memory film may include a blocking dielectric, a tunneling dielectric and a charge storage material located between the blocking and tunneling dielectric. The charge storage material may comprise charge trapping layer, such as a silicon nitride layer, or a plurality of discrete charge trapping regions, such as floating gates or discrete portions of a charge trapping layer. In this case, each memory opening fill structure88and adjacent portions of the electrically conductive layers86constitute a vertical NAND string. Alternatively, the memory opening fill structures88may include any type of non-volatile memory elements such as resistive memory elements, ferroelectric memory elements, phase change memory elements, etc. The electrically conductive layers86may be patterned to provide a terrace region. Contact via structures (not shown) may be formed on the electrically conductive layers86in the terrace region to provide electrical connection to the electrically conductive layers86. Dielectric material portions90may be formed around each vertically alternating stack (82,86) to provide electrical isolation between neighboring vertically alternating stacks (82,86). Bit lines92may electrically contact drain regions located above the semiconductor channel at the top of the memory opening fill structures88.

The multiple word lines86typically extend in a single word line direction and generate significant stress at a wafer level, which can distort the wafer50. Wafer warpage may degrade lithographic patterning processes and/or induce arcing during plasma-enhanced chemical vapor deposition processes.

In one embodiment, the method and apparatus of the embodiments of the present disclosure described above may be used to deposit a backside stress compensation film94on the backside surface52of the semiconductor wafer50. The backside stress compensation film94reduces the wafer warpage to make the wafer50more planar. The backside stress compensation film94may be formed on the backside surface52of the wafer50before or after forming the semiconductor device80over the front surface51of the wafer50. The semiconductor device80may be deposited over the front surface51of the wafer50in at least one additional vacuum chamber other than the vacuum chamber190used to deposit the backside stress compensation film94in the same and/or different deposition apparatus as the apparatus10containing the vacuum chamber190.

The backside stress compensation film94, such as a silicon nitride layer, may be in compressive or tensile stress depending on the RF power applied during the PECVD process described above. For example, a lower RF power (e.g.,400W to650W) results in layer with a positive sign of the stress (i.e., tensile stress), while a higher RF power (e.g.,750W to1000W) results in a layer with a negative sign of the stress (i.e., compressive stress).

The various embodiments of the present disclosure can be employed to provide a carrier ring40which induces self-centering of the wafer50on the lower top surface42of the step140of the carrier ring40. The contoured inner sidewall {41, (44,45,47)} helps to prevent misplacement of the wafer50on the carrier ring40. In addition, the contoured inner sidewall {41, (44,45,47)} of the carrier ring40provides an opening46diameter DO (i.e., twice the fourth radius R4) that minimizes the contact area between the backside surface52of the wafer50and the lower top surface42of the carrier ring40, and thus, minimizes the backside surface52area of the wafer50that is blocked by the carrier ring40during the stress compensation film94deposition process.