Pin layer reversal detection

A circuit to detect pin layer reversal including an input circuit to receive an input signal having a first portion to indicate a pin layer reversal and having a second portion to indicate a servo sync mark, a first servo sync mark detector for detecting a positive servo sync mark from the input signal, a second servo sync mark detector for detecting a negative servo sync mark from the input signal, and a circuit responsive to the positive servo sync mark and the negative servo sync mark to generate a signal to indicate if the servo sync mark has been reversed and to generate a signal to indicate the pin layer reversal.

FIELD OF THE INVENTION

The present invention relates to a storage system and to a read channel which is used in the storage system. More particularly, the present invention relates to a circuit for the read channel that detects both pin layer reversal and detects if the polarity is reversed.

BACKGROUND OF THE INVENTION

An MR sensor detects magnetic field signals through the resistance changes of a magneto-resistive element, fabaricated of a magnetic material, as a function of the strength and direction of magnetic flux being sensed by the element. The conventional MR sensor operates on the basis of the anisotropic magneto-resistive (AMR) effect in which a component of the element resistance varies as the square of the cosine of the angle between the magnetization in the element and the direction of sense or bias current flow through the element.

MR sensors have application in magnetic recording systems because recorded data can be read from a magnetic medium when the external magnetic field from the recorded magnetic medium (the signal field) causes a change in the direction of magnetization in an MR head. This in turn causes a change in electrical resistance in the MR read head and a corresponding change in the sensed current or voltage.

A different and more pronounced magneto-resistance, called a giant magneto-resistance (GMR), has been observed in a variety of magnetic multilayered structures, the essential feature being at least two ferromagnetic metal layers separated by a nonferromagnetic metal layer. This GMR effect has been found in a variety of systems, such as Fe/Cr or Co/Cu multilayers exhibiting strong antiferromagnetic coupling of the ferro-magnetic layers as well as in essentially uncoupled layered structures in which the magnetization orientation in one of the two ferro-magnetic layers is fixed or pinned. The physical origin is the same in all types of GMR structures; namely, the application of an external magnetic field causes a variation in the relative orientation of the magnetizations of neighboring ferro-magnetic layers. This in turn causes a change in the spin-dependent scattering of conductive electrons and, thus, the electrical resistance of the structure. The resistance of the structure changes as the relative alignment of the magnetizations of the ferromagnetic layers changes.

A particularly useful application of GMR is a sandwich structure including two essentially uncoupled ferro-magnetic layers separated by a nonmagnetic metallic spacer layer in which the magnetization of one of the ferro-magnetic layers in “pinned.” The pinning may be achieved by depositing the ferro-magnetic layer to be pinned onto an antiferro-magnetic layer, such as an iron-manganese (Fe—Mn) layer, to create an interfacial exchange coupling between the two layers. The spin structure of the antiferromagnetic layer can be aligned along a desired direction (in the plane of the layer) by heating beyond the “blocking” temperature of the antiferromagnetic layer and cooling in the presence of a magnetic field. The blocking temperature is the temperature at which exchange anisotropy vanishes because the local anisotropy of the antiferro-magnetic layer, which decreases with temperature, has become too small to anchor the antiferromagnetic spins to the crystallographic lattice. The unpinned or “free” ferromagnetic layer may also have the magnetization of its extensions (those portions of the free layer on either side of the central active sensing region) also fixed, but in a direction perpendicular to the magnetization of the pinned layer so that only the magnetization of the free-layer central active region is free to rotate in the presence of an external field. The magnetization in the free-layer extensions may be fixed by longitudinal hard biasing or exchange coupling to an antiferromagnetic layer. However, if exchange coupling is used, the antiferromagnetic material is different from the antiferromagnetic material used to pin the pinned layer and is typically nickel-manganese (Ni—Mn). This resulting structure is called a “spin valve” (SV) MR sensor.

The spin-valve head has the same stabilization issues as conventionally designed GMR heads. In particular, these problems are exacerbated by its multilayer structure. Typically, there are three films whose domain structures contribute directly to the sensitivity, signal-to-noise, and stability of the sensor. Namely, the antiferromagnetic (AF) pinning layer, the Co alloy pinned layer, and the NiFe free layer. With respect to conventional MR heads, the spin valve has an additional serious and unique reliability concern in that the AF/Co alloy structure is unstable and can be easily induced to rotate its magnetization. The sensor output is strongly influenced by the AF orientation and, as a result, the disturbed sensor may show poor asymmetry, degraded sensitivity, and increased noise compared to its performance in the intended orientation. The stability of the antiferromagnetic layer is the Achilles' heel of the spin valve. The misorientation of the AF magnetic pinning field can occur spontaneously or as a result of heating from electrical overstress, thermal asperities, or external influences. Heat, together with the magnetic field from the sense current, inverts the magnetization of the AF film. The creation of a thermally stable, antiferromagnetic film has become an important design criterion for spin valves. Thus, it is important to detect the pin layer reversal. This is especially true during servo operation.

In addition, during servo operation, it has been found that the polarity of the bits can be reversed. Thus, when reading data, it is important to detect the occurrences when this polarity has been reversed. For example, a pattern of bits or sync field are required to be identified. A bit reversal can make this identification difficult.

In conventional rotating disk data storage systems, it is common to employ some type of servo system to determine the radial position of the read/write transducer head over the disk surface and to maintain the transducer head over the center line of one of the concentric recording tracks during data reading and data writing operations. This is accomplished by providing servo information on one or more of the disk surfaces for access by the read/write transducer heads. In prior art, disk drives have included various known types of head positioning servo systems. In a pertinent prior art type of servo system, often referred to as an imbedded servo, the prerecorded servo information occupies positions (servo sectors) of each disk's recording surface, with the servo sectors being angularly spaced apart and interspersed among the data sectors of each concentric track. Servo sectors are prerecorded on the recording surface in arcuate sections, called frames, that run radially along the disk surface from the center to the outer edge. Frames are typically written at discrete angular intervals such that as the recording surface is rotated beneath an active read/write transducer head, servo sectors pass beneath the active head in time-quantifiable phases. Each servo phase represents the angular position of that servo frame on the recording surface, and the length of each servo phase defines a time period for servo processing circuitry in which servo information contained in the servo sector is presumed valid.

Furthermore, a servo sync field word includes a robust sync pattern which is written radially phase coherently by the servo writer as part of the manufacturing process such that the synchronization can always be achieved during a seek mode where an active read/write head may be positioned along the tracks.

SUMMARY OF THE INVENTION

The present invention provides a circuit that detects both pin layer reversal and detects if the polarity of the bits is reversed. The present invention uses information before the postcode circuit so that the polarity stream and the pin layer reversal information are not lost.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The following invention is described with reference to figures in which similar or the same numbers represent the same or similar elements. While the invention is described in terms for achieving the invention's objectives, it can be appreciated by those skilled in the art that variations may be accomplished in view of these teachings without deviation from the spirit or scope of the invention.

FIGS. 11 and 12show a side and top view, respectively, of the disk drive system designated by the general reference1100within an enclosure1110. The disk drive system1100includes a plurality of stacked magnetic recording disks1112mounted to a spindle1114. The disks1112may be conventional particulate or thin film recording disk or, in other embodiments, they may be liquid-bearing disks. The spindle1114is attached to a spindle motor1116which rotates the spindle1114and disks1112. A chassis1120is connected to the enclosure1110, providing stable mechanical support for the disk drive system. The spindle motor1116and the actuator shaft1130are attached to the chassis1120. A hub assembly1132rotates about the actuator shaft1130and supports a plurality of actuator arms1134. The stack of actuator arms1134is sometimes referred to as a “comb.” A rotary voice coil motor1140is attached to chassis1120and to a rear portion of the actuator arms1134.

A plurality of head suspension assemblies1150are attached to the actuator arms1134. A plurality of inductive transducer heads1152are attached respectively to the suspension assemblies1150, each head1152including at least one inductive write element. In addition thereto, each head1152may also include an inductive read element or a MR (magneto-resistive) read element. The heads1152are positioned proximate to the disks1112by the suspension assemblies1150so that during operation, the heads are in electromagnetic communication with the disks1112. The rotary voice coil motor1140rotates the actuator arms1134about the actuator shaft1130in order to move the head suspension assemblies1150to the desired radial position on disks1112.

A controller unit1160provides overall control to the disk drive system1100, including rotation control of the disks1112and position control of the heads1152. The controller unit1160typically includes (not shown) a central processing unit (CPU), a memory unit and other digital circuitry, although it should be apparent that these aspects could also be enabled as hardware logic by one skilled in the computer arts. Controller unit1160is connected to the actuator control/drive unit1166which is in turn connected to the rotary voice coil motor1140. A host system1180, typically a computer system or personal computer (PC), is connected to the controller unit1160. The host system1180may send digital data to the controller unit1160to be stored on the disks, or it may request that digital data at a specified location be read from the disks1112and sent back to the host system1180. A read/write channel1190is coupled to receive and condition read and write signals generated by the controller unit1160and communicate them to an arm electronics (AE) unit shown generally at1192through a cut-away portion of the voice coil motor1140. The AE unit1192includes a printed circuit board1193, or a flexible carrier, mounted on the actuator arms1134or in close proximity thereto, and an AE module1194mounted on the printed circuit board1193or carrier that comprises circuitry preferably implemented in an integrated circuit (IC) chip including read drivers, write drivers, and associated control circuitry. The AE module1194is coupled via connections in the printed circuit board to the read/write channel1190and also to each read head and each write head in the plurality of heads1152. The read/write channel1190includes the pin layer reversal detection circuit of the present invention.

InFIG. 1, the various circuits associated with the channel operation during servo operation, and more particularly for servo mark detection operation, are illustrated. The output from the PR4 Viterbi detector100is input to postcoder102. Detection circuit104receives the output from the postcoder circuit102. The encoded signal which has been stored in the servo sync mark register106is compared in the servo sync mark detector104. The output is output to 9/3 decoder108.

One aspect of the servo sync mark detector circuit illustrated inFIG. 1is the fact that the postcoder102is output to servo sync mark detection circuit104. The postcoder output from postcoder102is polarity independent and, consequently, it is impossible to determine whether or not a polarity reversal has occurred by solely using the output of the postcoder102.

FIG. 2illustrates a block diagram of the circuit of FIG.1. Here, the precoder202outputs to the channel and PR4 equalizer204. The output from the channel and PR4 equalizer204is input to the PR4 decoder206. The output of the PR4 decoder is input to the postcoder208. Additionally, the output of the postcoder208is input to the error correction unit212and sync mark detector210. The output of the error correction unit212is input to the decoder214.

FIG. 3illustrates another circuit to provide a synchronous servo mark detector signal. This circuit includes four stages of delay circuits, namely delay circuit302,304,306and308. These delay circuits302,304,306and308provide the function 1+D−D2−D3. Thus, four samples with the approximate delay predetermined are used to indicate if a set of pulses has occurred to indicate synchronization. These delay circuits are used in conjunction with a frame detector circuit310to output a data signal and an index signal to a servo sync mark detector circuit312and a gray code detector circuit314. The sync mark detector circuit312outputs a servo sync mark detector signal, and the gray code detector circuit314outputs a gray code. However, these circuits suffer from the defect of not providing a circuit to detect the polarity and whether or not a pin reversal has occurred.

Turning now toFIG. 4, a broad circuit diagram of the present invention is illustrated. The PR4 Viterbi detector402is connected to shift register circuit408. The precoded format signal, for example a signal being looked for in the servo sync mark signal, is input to the servo sync mark register404, which may be a 17-bit register. The servo sync mark register404is connected both to the servo sync mark detection circuit406and the servo sync mark detection circuit410. Both the servo sync mark detection circuit406and the servo sync mark detection circuit410are connected to the shift register408, which may be a 17-bit shift register. The shift register408is connected to a postcoder412. The postcoder412is connected to the decoder circuit414, which may be a 9/3 decoder circuit, and the decoder circuit414is connected to the nonreturn to zero circuit416. The precoded format signal is input to the servo sync mark register404. The precoded format signal is output from the servo sync mark register404and is input both to the servo sync mark detection circuit406and the servo sync mark detection circuit408. The PR4 Viterbi detector402receives the input signal from disk and outputs the input signal to shift register408. The input signal is shifted along shift register408. The output of shift register circuit408is input both to the servo sync mark detector circuit406and the servo sync mark detector circuit410. The bits in servo sync mark detector circuit410are reversed. If a match is obtained between the precoded format signal and the signal input to the Viterbi detector404and servo sync mark detection circuit410, then a pin layer reversal (PLR) signal is detected. If the servo sync mark detection circuit406obtains a match between the precoded format signal and the output of the PR4 Viterbi detector404, namely the input signal, then no pin layer reversal detection signal is output. Next, the postcoder circuit412eliminates the coding imposed upon the input signal from a precoder (not shown). The decoder circuit414decodes the coded signal output from the postcode circuit412. The nonreturn to zero circuit416performs.

FIG. 5illustrates a decoder circuit in accordance with the present invention such as illustrated inFIG. 8in element802. An exclusive OR circuit506receives the input signal into exclusive OR circuit506. The output of exclusive OR circuit506is input to delay circuit502. The signal is delayed by a predetermined time period in delay circuit502. The delay circuit502outputs a delayed signal to delay circuit504. The delay circuit504delays by another predetermined time period the delayed signal input to delay circuit504. The predetermined delay time period could be the same. The output of delay circuit504is input to exclusive OR circuit506.

FIG. 6illustrates a postcoder used in accordance with the present invention such as inFIG. 8in element808. The input signal to the postcoder is input to exclusive OR circuit602and additionally input into delay circuit606. The delay circuit606delays by a predetermined time period the input signal and outputs a delayed signal to delay circuit604. The delay circuit604delays by a predetermined time period, which may be different, the delayed input signal to output a double delayed output signal. The double delayed output signal from delay circuit604is input to exclusive OR circuit602. The exclusive OR circuit performs an exclusive OR function on the input signals.

Turning now toFIG. 7,FIG. 7illustrates PR4 MF circuit702. The output of PR4 MF circuit702is input to a negative terminal of comparator704and to a plus terminal of comparator706. The comparator circuits704and706additionally input a threshold voltage. The threshold voltage is input to the plus terminal of comparator704while the threshold voltage is input to the negative terminal of comparator706. The output of comparator704is input to switch718which is controlled by frame detect circuit710. The output of comparator706is input to switch716which is controlled by frame detect circuit708.

Turning now toFIG. 8,FIG. 8illustrates a portion of the read channel and a detection circuit for both pin layer reversal and detecting if the polarity has been reversed.

FIG. 10illustrates a servo sync detection circuit in accordance with the present invention. The sync detector illustrated inFIG. 10could be implemented as element816or element818. As illustrated inFIG. 10, a shift register1002receives an input signal. The input signal is shifted along the shift register1002. The output of shift register1002is input to a series of exclusive OR circuits, all of which receives the program sync signal and the output from the shift register circuit1002. These determine the number of errors in the bits contained in the shift register circuit1002. Although two exclusive OR circuits1004and1006are shown, additional exclusive OR circuits could be used, corresponding to each output of shift register1002. The output of the exclusive OR circuits1004and1006is input to a series of summing circuits illustrated as sum circuits1008and1010. The output of the sum circuits1008and1010are input to a compare circuit1012which compares the output of the sum circuits1008and1010to a program error threshold signal, and if the summation of errors is less than the program error threshold, a servo sync mark detect signal has been established. This indicates the servo sync detect signal has been found.

Turning now toFIG. 8,FIG. 8includes a precoder802connected to a channel PR4 equalizer804, and the channel PR4 equalizer804is connected to PR4 detector806. The input signal is input to the precoder802. The precoder802precodes the input signal and outputs a precoded signal to the channel PR4 equalizer804. The channel PR4 equalizer804performs equalization and various timing functions. The output of channel PR4 equalizer804is input to PR4 decoder806. The PR4 decoder806decodes the signal output from the channel PR4 equalizer804. The PR4 detector806is connected to the postcoder808. However, the output from the decoder806is input to the servo sync mark detect circuit816through switch810. The switch810is controlled by a pin layer reverse enable signal. Additionally, the output of the PR4 decoder806is input to the servo sync mark detector circuit818. Although order is not important, the sync mark detection circuit816detects a normal sync mark, while the sync mark detector circuit818detects a negative sync mark (bit position reversed). The output of sync mark detector circuit816is input to OR circuit822. Also, the input to OR circuit822is connected to the output of sync mark detector circuit816and sync mark detector circuit818. The output of the decoder806is input to both sync mark detector circuits816and818. Sync mark detector circuit816detects the normal signal while sync mark detector circuit818detects the inverted signal, and correspondingly, upon detection of the normal signal or the inverted signal, the corresponding sync mark detector circuit816or818outputs a signal to the exclusive OR circuit822. Additionally, the output of the sync mark detection circuit816is input to AND circuit826, and the output of sync mark detection circuit818is input to AND circuit824. Additionally, input to the AND circuit826and the AND circuit824is a positive polarity signal. The output of AND circuit826and the output of AND circuit824is input to exclusive OR circuit828. The AND circuit826performs a logical AND operation upon the input from the sync mark detection circuit816and the positive polarity signal. The AND circuit824performs a logical AND operation on the output of servo sync mark detector818on the positive polarity signal. The output of exclusive OR circuit828is the pin layer detection circuit, and the output of OR circuit822is the sync mark detection circuit signal. The pin layer detection signal provides an indication if there has been a pin layer reversal or if the servo data has been inverted.

Turning now toFIG. 9, this implementation does not require a Viterbi detector and does not require an equalizer. InFIG. 9, a series of delay circuits, namely delay circuit902, delay circuit904, delay circuit906and delay circuit908are connected in series. The output of delay circuit902is connected to a summing circuit903. The output of delay circuit904is additionally connected to the summing circuit903. The summing circuit903is connected to a summing circuit909. The summing circuit903is connected to the negative input of summing circuit909. Additionally, the output of delay circuit906is connected to summing circuit911, and the output of delay circuit908is connected to summing circuit911. The summing circuit911is connected to a plus input of summing circuit909. The summing circuit909is connected to a negative input of comparator910. The delay circuit902is connected to the delay circuit904. The delay circuit904is connected to the delay circuit906, which is in turn connected to the delay circuit908. An input to the FIR circuit (not shown) is input to the delay circuit902. The delay circuit902delays the FIR input signal and outputs a first delayed signal to delay circuit904and summing circuit903. The delay circuit904delays the first delay signal output from the delay circuit902and outputs a second delay signal which is input to the delay circuit906and to the summing circuit903. The summing circuit903sums the output of delay circuit902and delay circuit904, namely the first delay signal and the second delay signal, to produce a first summed signal which is input to delay circuit909. The second delay signal is delayed by delay circuit906which outputs a third delay signal both to delay circuit908and to the plus input of summing circuit911. The delay circuit908delays the third delay signal and outputs a fourth delayed signal which is input to the plus input of summing circuit911. The output of summing circuit911is input to the plus input of summing circuit909. Additionally, the output from summing circuit911is subtracted by the output of summation of903. The resulting signal from summing circuit909is input to comparator910as well as comparator912.

The circuit930outputs a dibit signal indicating if a dibit has occurred or a dibit has not occurred. This dibit signal is directly input to comparator910. The output of circuit930is inverted by inversion circuit913, and the inverted output signal from the inversion circuit913is input to a negative input of comparator circuit912. The comparator circuit910compares the output from circuit930with the output from summing circuit909and outputs a first compared signal to a frame detect circuit914. The inverted output signal from inverse circuit913is compared with the output of summing circuit909by comparator912, and the output from comparator912, a second compared signal, is output to frame detect circuit916. The frame detect circuit914may detect normal signals while the frame detect circuit916detects inverted signals. Both frame detect circuit914and frame detect circuit916output a data signal as well as an index signal. The frame detect circuit914outputs a first data signal and a first index signal. The frame detect circuit916outputs a second data signal and a second index signal. The data signal is a and the index signal is a. The output, namely first data signal and first index signal, from the frame detect circuit914is input to the servo sync mark detect circuit918. Likewise, the output, namely the second data signal and the second index signal, of frame detect circuit916is output to the servo sync mark detect circuit920. Similar to the frame detect circuit914, the servo sync mark detect circuit918detects normal servo sync marks while the servo sync mark detect circuit920detects negative servo sync marks. The first data signal and the first index signal from frame detect circuit914is input to mux circuit922. Additionally, the second data signal and the second index signal from frame detect circuit916is input to mux circuit922. The mux circuit922muxes the first data signal from frame detect circuit914with the second data signal from the frame detect circuit916to output a mux data signal. Additionally, the first index signal from frame detect circuit914is muxed with the second index signal from the frame detect circuit916to output a muxed index signal. The mux circuit922is controlled by the output of the servo sync mark detect circuit918and, in addition, is controlled by the output of servo sync mark detect circuit920. When a normal servo sync mark detect signal is detected, the data and index from frame detect circuit914is output from mux circuit922to the gray code circuit926. Likewise, when the servo sync mark detect circuit922detects an inverted sync mark detect signal, the data and index from frame detect circuit916is output to the gray code circuit926. Thus, the gray code circuit926always has correct information. Likewise, the output from the servo sync mark detect circuit918and the servo sync mark detect circuit920is logically ANDed together in AND circuit924. The output of AND circuit924is a servo sync mark detect signal. The output from gray code detector926is a gray code detected signal.