Locating short circuits in printed circuit boards

One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit.

BACKGROUND

1. Field of the Invention

The present invention relates to printed circuit boards, and more particularly to locating a short circuit in a multi-layered circuit board.

2. Background of the Related Art

Modern electronic packages are complex and contain multiple conductive layers, including power and ground layers, where each layer is formed in a different plane between nonconductive layers. Even a minuscule short circuit between two different conductive layers is sufficient to cause a package to fail. The short circuit may occur, for example, because a damaged component like a capacitor has been used during the assembly process. Alternatively, the short circuit may occur where a rework operation resulted in a minute solder splash bridging two voltage traces. A technique such as In-Circuit Test (ICT) can detect the existence of the short circuit, but not its location. A conventional approach for locating the short circuit is to physically depopulate each component between the power and ground planes, one at a time, until the short circuit disappears. However, this can be a very invasive, laborious, and time-consuming process.

BRIEF SUMMARY

One embodiment of the present invention provides a method of locating a short circuit between two layers of a printed circuit board. The method includes selecting first, second, and third non-collinear test points in one of the two layers. A test signal is injected at each of the three test points, resulting in signal reflections at the short-circuit. The distance between each test point and the short circuit is determined from the time required for each signal reflection to reach the respective test point. The location of the short circuit is then uniquely determined from its distance from of each of the three test points.

DETAILED DESCRIPTION

Embodiments of the present invention include methods of locating a short circuit between two layers of a multi-layered printed circuit board (PCB). Typically, the short circuit to be detected will electrically bridge a power layer and a ground layer. A technique such as In-Circuit Test (ICT) can be used to detect the existence of the short circuit in the printed circuit board during manufacturing, although ICT does not generally indicate the location of the short circuit. Furthermore, ICT is not able to indicate the location of a short circuit after the boards are loaded with components and when the short circuit occurs when mounting passive and active devices to the board. As an alternative to ICT, the existence of the short circuit may be inferred from an observed malfunction of the PCB.

The location of the short circuit can then be determined according to an embodiment of the invention by injecting test signals at different test points within the PCB. Each test signal will be partially reflected at the short circuit and propagate back to the test point from which the test signal originated. The signal reflection may be detected according to its effect on the voltage value of the test signal. For example, the signal reflection may cause a steep drop in voltage at the instant the signal reflection reaches the test point from which the test signal originated. The time required for the signal reflection to reach the point of origin of the test signal may be used to determine the distance between the test point and the short circuit. Generally, the distance between each of three, non-collinear test points and the short circuit can be used to pinpoint the location of the short circuit. In some cases, the use of as few as two test points is sufficient to locate the short circuit.

FIG. 1is a schematic diagram of a circuit board testing system10that may be used to identify the location of a short circuit28in a printed circuit board (PCB)20according to an embodiment of the invention. The testing system10includes a computer14having a display16and a test probe12connected to the computer14. The computer14may be a specialized computer system, a general purpose computer such as a PC, or a combination thereof. For example, the computer14may include a personal computer (PC) in communication with an oscilloscope, or having software for emulating signal-analysis features of an oscilloscope. The test probe12may be, for example, a co-axial test probe known in the art apart from its application to the present invention. The computer system14may include testing software or firmware, including one or more drivers for controlling the test probe12to generate test signals and one or more analysis modules for analyzing the time-dependent behavior of the test signals to locate the short circuit28.

The PCB20under test is a multilayered circuit board, such as a motherboard, an application card, or an interposer of a chip package. The PCB20is not drawn to scale, and has certain features enlarged for clarity. The PCB20will typically have many layers, such as signal layers, dielectric layers, resistive layers, one or more ground layers, and one or more power layers. To simplify illustration of the PCB20, only selected layers are shown, including a power layer (“P”) and a ground layer (“G”). A large number of vias are typically provided throughout the PCB20, although only one via24is shown for simplicity of illustration. A via, generally, is a plated through hole extending through one or more layers of a PCB, providing electrical pathways between layers. For example, a via may connect a signal trace in one layer with a signal trace in another layer. A via may also provide a signal path for connecting a microcircuit (e.g. transistor) in one layer to a ground layer or power layer. The via24in this example extends from a surface22of the PCB20to the power layer P. An exposed contact pad26is provided on the surface22of the PCB20. The contact pad26is a metal plated feature that is electrically connected with the power via24. The contact pad26and power via24may be integrally formed, such as by electroplating the contact pad26and power via24in an electroplating step.

The short circuit28in the PCB20is a defect in, or damaged area of, the PCB20that electrically bridges the power layer P with the ground layer G. The short circuit28typically will not be apparent to the naked eye. The existence of the short circuit28may be determined using ICT, for example. Alternatively, the existence of the short circuit28may be detectable indirectly, such as due to an electrical malfunction in the PCB20. Due to the complexity of the PCB20, however, manually locating the short circuit28could be very time consuming. The testing system10can be used to locate the short circuit28without visually observing the short circuit. Specifically, according to an embodiment of the invention, the test probe12may be used to inject a test signal at each of multiple test points throughout the PCB20. Each test signal may be analyzed using the computer14to determine the distance from each test point to the short circuit28. The location of the short circuit28may then be determined according to the distance between each of the test points and the short circuit28.

A test signal having a desired waveform is generated by the computer14and “injected” at a selected test point within a selected layer of the PCB20using the test probe12. The test signal is preferably a step signal, such as a zero to 1 volt transition that remains at 1 volt. Generally, the test signal may be injected at the selected test point within the selected layer by introducing the test signal into a via connected to the selected layer at the selected test point. The via then carries the signal into the PCB20to the selected layer. The large number of vias usually present within the PCB20for electronic contact with surface mounted components gives rise to a large number of test points from which to select. Here, by way of example, a test signal30is injected into the power layer P at the location of the power via24by contacting the probe12with the contact pad26that is concentric with the via24, and generating the test signal30. The test signal30travels through the via24to the power layer P, where the test signal30then propagates radially outwardly within the power layer P from the location where the via24intersect with the power layer P. When the propagated test signal reaches the short circuit28, the test signal is partially reflected. The resulting signal reflection32propagates back through the via24to the contact pad26. Where the test signal is a step signal, the response is a step response, such as a standing step response that is not periodic.

The test probe may be a co-axial probe having two electrical leads, including one lead for transmitting the test signal and the other lead for grounding. The test signal may be an electrical signal having a voltage that remains constant throughout the test. The test signal30is optionally plotted on the display16, such as by plotting the voltage of the test signal as a function of time. The display16may be an oscilloscope display, which may show a graphical representation of the test signal over time. The signal reflection32has an observable influence on the voltage being monitored by the computer14, such as causing a steep voltage drop at the time the signal reflection32reaches the via24, which is the point of origin of the test signal30in this example. As further explained below, the effect of the reflection32on each test signal may be analyzed by the computer14to ascertain the distance between the test point and the short circuit28. For example, the computer14may identify a steep voltage drop indicative of the signal reflection32reaching the via24and determine how much time that has elapsed at the instant the sharp voltage drop begins. The distances between other test points and the short circuit may be similarly determined, and used to locate the short circuit28.

FIG. 2is a plan view of the PCB20illustrating a method of locating the short circuit28by injecting a test signal at each of three different test points P1, P2, P3within a test region40that includes the short circuit28, and analyzing the voltage response of the test signals. The selected test region40of the PCB20inFIG. 2may either represent the entire PCB20or just a portion of the PCB20. For example, if the PCB20under test has a relatively small surface area, such as the interposer of a chip package, the entire area of the PCB20may be selected as the test region40. In a larger PCB, such as the motherboard of a server, the test region40may be a sub-region of the PCB known to contain the short circuit. Selecting the smallest possible test region40known to include the short circuit may desirably improve the ease of locating the short by reducing the maximum distance between the short circuit and the selected test points. For example, using a small test region may allow the point of the short circuit to be identified with measurements at only two test points. In some cases, information about the malfunctioning of the PCB20may provide a clue as to a particular region where the short circuit28is likely to be located, in which case the test region40may be narrowed to that particular region, and need not include the entire PCB20. By way of example, the test region40illustrated inFIG. 2is a 50 mm by 50 mm square region, which may be the entire area of a 50 mm by 50 mm PCB or just a 50 mm by 50 mm sub-region of a PCB that is larger than 50 mm by 50 mm.

A test signal is separately injected at each of three selected test points P1, P2, P3within the boundaries of the selected test region40. A minimum of three test points are selected in this example to avoid the possibility of indeterminate results in locating the short circuit28, although as few as two test points may be sufficient to determine the location of the short circuit28under certain circumstances, as discussed below. The test points P1, P2, P3are selected to be non-collinear, which may also help avoid indeterminate results, although this may also not be required under certain circumstances. The size and shape of a test region may depend on the circumstances, and is not limited to having a rectangular shape. For ease of illustration, the test region40in this example is a rectangular area having four edges41,42,43,44. Test point P1is optionally selected near the intersection of adjacent edges41,44of the test region40. Test points P2and P3are each selected near the edge42. This particular selection of the test points P1-P3is provided merely as an example; any three non-collinear test points within the test region40may be used to locate the short circuit28.

A first test signal is injected at the first test point P1. The test signal (30) and signal reflection (32) are labeled for reference. The voltage response of the test signal is analyzed (as discussed further below) to determine a first distance R1between the test point P1and the short circuit28. R1defines the radius of a circle or arc51along which the short circuit28lies, with test point P1at the center of this arc51. Similarly, a second test signal is injected at the second test point P2, and the voltage response is analyzed to determine a second distance R2between the test point P2and the short circuit28. R2defines the radius of a circle or arc52along which the short circuit28lies, with the second test point P2at the center of this arc52. Arcs51and52intersect at two different points of intersection including the location of the short circuit28sought and another location29. Thus, knowledge of R1and R2narrow the location of the short circuit28to two possible points (28and29). However, because both points lie on the PCB20, the location of the short circuit28is indeterminate when only R1and R2are known in this particular example. A third test signal is injected at the third test point P3, and the voltage response is analyzed to determine a third distance R3between the test point P3and the short circuit28. R3defines the radius of a circle or arc53along which the short circuit28lies, with the third test point P3at the center of this arc53. The three arcs51,52,53intersect at a unique point, which coincides with the location of the short circuit28. Thus, the distances R1, R2, R3of each of three non-collinear test points P1, P2, P3from the short circuit28may be used to pinpoint the location of the short circuit28.

InFIG. 2, the location of the short circuit28has been determined precisely, so as to “pinpoint” the location of the short circuit28. However, due to the inherent uncertainty in scientific measurements, the distances R1, R2, R3obtained using this method may include a percentage of uncertainty. The result of this analysis, therefore, may be to identify a smaller sub-region of the test region40within which the short circuit28is likely to be, without necessarily pinpointing the precise location of the short circuit28. Even without pinpointing the location of the short circuit28, identifying a smaller sub-region of the test region40wherein the short circuit28is likely to be, may greatly speed up the process of locating the short. A technician testing the PCB20may then examine the PCB20within the small area of the sub region, without having to examine the entire test region40, to locate the short circuit28. The process may be able to identify the location of the short circuit with an accuracy of about 100 mils (0.1 inch).

Thus, having determined the distances R1, R2, R3as indicated inFIG. 2, the location of the short circuit28may be identified as a unique point (or at least a sub-region of the test area40) that is the distance R1from the test point P1, the distance R2from the test point P2, and the distance R3from the test point P3. This unique point may be determined manually, or using a computer, such as the computer14ofFIG. 1. For example, the location of the short circuit28may be manually determined by drawing the three arcs51,52,53centered about the respective test points P1, P2, P3, and determining the intersection of the three arcs51,52,53. Alternatively, the short circuit28may be computed, such as using the computer14ofFIG. 1, with the three test points P1, P2, P3and the distances R1, R2, R3as inputs to a formula or mathematical algorithm. Mathematical approaches generally known in the art apart from application to the present invention, such as vector algebra, geometric or trigonometric relationships, or combinations thereof, may be employed. The computed location of the short circuit28may then be output and displayed on the display16ofFIG. 1, such as in the form of rectangular or polar coordinates, or by graphically displaying a representation of the PCB under test and the relative location of the short circuit28.

FIG. 3is a graph of voltage versus time for each of three different test signals from which the distances R1, R2, R3may be graphically determined. The graph includes a first curve61representing the voltage versus time of the first test signal, a second curve62representing the voltage versus time of the second test signal, and a third curve63representing the voltage versus time of the third test signal. Each curve represents the voltage response of the respective test signal when the short circuit28ofFIG. 2is present in the PCB under test. A fourth curve64, by comparison, represents the expected voltage response of a test signal in the absence of a short circuit. Each curve61-63has a generally downward trend over the indicated timeframe. The reflection of each test signal is evidenced by a particularly sharp downward drop in the voltage. Specifically, a voltage drop71in the first curve61indicates a signal reflection has reached the location of origin (the test point P1ofFIG. 2) at 1310 ps. The known propagation rate of signals in the conductive material of layer P is one inch per 220 ps. Thus, the distance between the test point P1and the short circuit28is ½*1310 ps*1 inch/220 ps=3.0 inches. A voltage drop72in the second curve62occurs at 910 ps, which, applying a similar analysis, indicates a distance of 2.1 inches between the second test point P2and the short circuit28. A voltage drop73in the third curve63occurs at 630 ps, which, again applying a similar analysis, indicates a distance of 1.4 inches between the third test point P3and the short circuit28.

FIG. 4is a plan view of another PCB120illustrating a method of locating a short circuit128by injecting a test signal at each of only two different test points P1and P2. The two points P1, P2are intentionally selected near to an edge141of the PCB120. For example, P2and P2are preferably within 1 cm of the edge141. A first test signal is injected at the first test point P1, and the voltage response is analyzed (as discussed above) to determine a first distance R1between the test point P1and the short circuit128. R1defines the radius of a circle or arc151along which the short circuit128lies, with test point P1at the center of this arc151. A second test signal is injected at the second test point P2, and the voltage response is analyzed to determine a second distance R2between the test point P2and the short circuit128. R2defines the radius of a circle or arc152along which the short circuit128lies, with the second test point P2at the center of this arc152. Arcs151and152intersect at two different points of intersection including the location of the short circuit128sought and another location129. However, in this example, because test points P1and P2were selected very near the edge141of the PCB120, only one point (coincident with the location of the short circuit28) lies on the PCB20. The other point129is outside the PCB120, and may therefore be eliminated. Thus, using only two points P1and P2, the location of the short circuit128can be determined by selecting the two test points P1and P2along the edge141of the PCB120.

FIG. 5is a flowchart generally outlining a method of locating a short circuit according to an embodiment of the invention. In step200, first, second, and third non-collinear test points in one of two layers of a PCB are selected. The two layers may be a ground layer and a power layer, for example. In step202, a first test signal is injected at the first test point. A first distance to the short circuit is determined according to a voltage response from the injected first test signal. In step204, a second test signal is injected at the second test point. A second distance to the short circuit is determined according to a voltage response from the injected second test signal. In step206, a third test signal is injected at the third test point. A third distance to the short circuit is determined according to the voltage response from the injected third test signal. In step208, the location of the short circuit is identified as being the first distance from the first test point, the second distance from the second test point, and the third distance from the third test point. The location of the short circuit may be narrowed to a small sub-region of a test area, or the location of the short circuit may even be pinpointed, depending on the level of precision by which the first, second, and third distances were determined.