Data on clock lane of source synchronous links

A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

BACKGROUND

Technical Field

The present disclosure relates to the field of clock links for data transmission. The present disclosure relates more particularly to the field of source synchronous links and coding data and clocks into the same signal.

Description of the Related Art

Clock circuits regulate transmission of data between components in computer systems, such as between two integrated circuit dies on a printed circuit board.

When data is to be transmitted from a data transmitting device to a data receiving device, data is output from the transmitting device in conjunction with a clock signal generated by a clock signal generator. When the data receiving device receives the data from the data transmitting device, the data receiving device extracts the data in conjunction with the clock signal in order to properly retrieve the data.

Many schemes have been devised for synchronizing a data receiving device with the clock signal by which the data was output from the data transmitting device.

One interchip scheme is a source synchronous clock link in which the data transmitting device transmits data to the receiving device via one or more data lanes. In traditional source synchronous clock schemes, the data transmitting device also transmits the clock signal to the receiving device via a dedicated clock lane. Source synchronous clock schemes are advantageous in that the receiving device can synchronize with the clock signal without complex clock recovery circuitry. However, additional dedicated clock signal lanes connect the transmitting and receiving devices.

BRIEF SUMMARY

One embodiment is to include data and clock information on the very same signal, thus reducing the power required by a chip. It also reduces the unber of output pins needed on a particular chip.

According to one embodiment, the absolute amplitude of a clock signal is modulated to carry data on the clock channels of any source synchronous link. This saves power because otherwise, the clock channel signal will consume power just for be able to output the clock ticks for the of the data channels. This embodiment provides a way to make clock channel also carry data. If there is not data channel at all, the clock channel is sufficient to transmit both data and clock tics at the same time on the same signal line.

One embodiment is a source synchronous data transmission system including a data transmitting device and a data receiving device. The data transmitting device includes a clock signal generator and a clock data driver coupled to the clock signal generator. The clock signal generator generates a clock signal. The clock data driver receives the clock signal and generates a modulated clock signal by modulating an amplitude of the clock signal, thereby encoding data into the modulated clock signal. The variable absolute value of the amplitude of the modulated clock signal reflects the data encoded into the modulated clock signal by the clock driver. The data transmitting device transmits the modulated clock signal to the receiving device on a dedicated clock lane. The data transmitting device can also transmit a data signal with a norma, unmodulated amplitude, including second data to the data receiving device on one or more dedicated data lanes.

The data receiving device receives the modulated clock signal and the data signal via the clock and data lanes. The data receiving device retrieves the data from the modulated clock signal and the second data from the data signal. The data receiving device times the retrieval of the second data by utilizing the modulated clock signal.

DETAILED DESCRIPTION

FIG. 1Ais a block diagram of a source synchronous data transmission system20according to one embodiment. The source synchronous data transmission system20includes a data transmitting device22and a data receiving device24. The data transmission device includes a clock signal generator26, a data driver28coupled to the clock signal generator26, a clock data driver30coupled to the clock signal generator26, and the data source32coupled to the clock signal generator26, the data driver28, and the clock data driver30. The data transmission device22further includes a data output34coupled to the data driver28and a clock output36coupled to the clock data driver30.

The data receiving device24includes a clock and data receiver38, a data retrieval circuit40coupled to the clock and data receiver38, and a memory42coupled to the clock and data receiver38and the data retrieval circuit40. The data receiving device24further includes a data input44coupled to the data retrieval circuit40, and a clock input46coupled to the clock and data receiver38.

The system20includes a data transmission lane48and a clock transmission lane50. The data transmission lane48is coupled between the data output34of the data transmitting device22and the data input44of the data receiving device24. The clock transmission lane50is coupled between the clock output36of the data transmitting device22and the clock input46of the data receiving device24.

The clock signal generator26of the data transmitting device22generates an oscillating clock signal. The clock signal has a particular frequency of oscillation, typically in a range between 100 MHz and 3 GHz, though frequencies outside this range can also be used. An example of the clock signal generated by the clock signal generator26is shown in the timing diagram ofFIG. 2, discuss further below.

The clock signal generator26can be a any type of clock generation circuit of which many are well known in the art. The type of clock signal generator used is not material to the use of the inventive concept and can include, for example, a PLL, crystal oscillator, voltage controlled oscillator, current controlled oscillator, or any other type of clock oscillator that generates an oscillating signal suitable for use as a clock signal in an electronic circuit. Alternatively, the clock signal generator26can be a frequency multiplier/divider that receives an external clock signal from a separate clock signal generator external to the data transmitting device22and outputs a clock signal that has a frequency that is a multiple of the frequency of the external clock signal according to a multiplication/division factor. Additionally, the clock signal generator26can be a clock signal buffer that receives the external clock signal and output the clock signal having a same frequency as the external clock signal. The buffer can be considered a frequency multiplier with a multiplication factor of 1.

The clock data driver30receives the clock signal from the clock signal generator26and generates a modulated clock signal based on the clock signal and data to be encoded with the modulated clock signal. In particular, the clock data driver30generates the modulated clock signal by modulating an amplitude of the clock signal. The modulated clock signal has the same frequency as the clock signal, but the amplitude of the modulated clock signal varies based on first data that is encoded with the modulated clock signal. The modulated clock signal therefore carries both the clock signal and first data.

The clock data driver30receives first data from the data source32and encodes the first data into the modulated clock signal by modulating the amplitude of the clock signal. In one example, the clock data driver modulates the clock signal between one of two amplitudes. The lower amplitude can represent a digital “0”, while the higher amplitude can represent a digital “1”. While the amplitude of the modulated clock signal changes, the frequency of the modulated clock signal remains constant. The value of the data is based on the absolute value of the amplitude of the clock signal. Thus, the modulated clock signal can act as a reliable timing signal even though the amplitude of the modulated clock signal changes.

The data source32can be any acceptable source of data. In one embodiment, the data source32is a data storage device such as a flash memory array, a magnetic hard drive, an optical storage device, or other types of memory or data storage devices. Alternatively, the data source32can include one or more of a register, a shift register, a hard drive, a sensor signal, a FIFO, a RAM cache, or other types of temporary data storage. Further, the data source32can be a CPU or a camera sensor. The inventive concept is beneficial in sensors which have limited battery and output pins, one example of which is a camera in a cell phone or another device. The data sensed by the camera when picture is taken can be transferred from the camera sensor, usually a type of CCD, to a data destination42using just the clock pin alone, thus saving power and pin count on the chips. Or, the data can be transferred on two pins, one having just data and the other clock plus data, as shown inFIG. 1A. The clock pin can also operate as the data pin so that only a single output is provided from the sensor, with both clock and data on same pin, in some embodiments, seeFIG. 1B.

The modulated clock signal is output to the data receiving device24via the clock output36and the clock lane50. The data receiving device24receives the modulated clock signal at the clock input46and passes the modulated clock signal to the clock and data receiver38. The data receiving device24uses the modulated clock signal as the timing signal for synchronizing the retrieval of data with the clock signal of the data transmission device22as is typical in source synchronous data links.

The source synchronous data transmission system20ofFIG. 1Ahas a further advantage of also transmitting data on the dedicated clock lane50. This is because the modulated clock signal includes data reflected in the changing absolute amplitude of the modulated clock signal. Therefore, the clock transmission lane50carries both the clock signal for the data receiving device24, and data. An example of a modulated clock signal is shown in the timing diagram ofFIG. 2, discussed further below.

In addition to the first data transmitted with the modulated clock signal, the data transmission device22also transmits second data to the data receiving device24on a dedicated data transmission lane48coupled between the data output34of the data transmitting device22and the data input44of the data receiving device24. In particular, the data driver28retrieves second data from the data source32and transmits a data signal to the data receiving device24via the data output34and the data transmission lane48. The data signal is encoded with the second data read from the data source32.

The data receiving device24receives the data signal at the data input44and passes the data signal to the data retrieval circuit40. The data retrieval circuit40also receives the modulated clock signal from the clock and data receiver38. The data retrieval circuit40uses the modulated clock signal to synchronize with the data transmitting device22, thereby enabling the data retrieval circuit40to properly retrieve the second data from the data signal. Additionally, the data retrieval circuit40retrieves the first data from the modulated clock signal. The data retrieval circuit40then passes the first and second data to the data destination42.

In one embodiment, the data destination42is a data storage device such as a flash memory array, a magnetic hard drive, an optical storage device, or other types of data storage devices or memory. Alternatively, the data destination42can include one or more of a register, a shift register, a FIFO, a RAM cache, or other types of temporary data storage. The data destination42can be any circuit that receives data, such as an CPU, a controller, a DSP, or another device that makes use of data.

While a single data transmission lane48is shown with respect toFIG. 1A, in practice many data lanes48can be present, each of which can carry a separate data signal. In one example, seven data lanes48are present, which, when used with a clock signal that also carries data provides 8 bits transmitted at the same time. Thus, the seven dedicated data lanes48together with the clock lane50allow 8 bits to be transmitted on each edge of the modulated clock signal. This corresponds to a Word of data being read from the data source32and transmitted to the data receiving device24on each edge of the modulated clock signal. Those of skill in the art will recognize that and number of data lines can be use, many more than seven data lanes48can be present if desired. This permits one less pin to be use for data, which will be beneficial in many types of circuits.

FIG. 1Bis an embodiment in which only a clock and data signal line are provided. There is no separate data line. If desired, a separate data recovery circuit47can be provided as part of the system, or likeFIG. 1A, the data can be recovered from the clock signal in the clock and data receiving circuit38.FIG. 1Btherefore provides an example of transfer circuit in which no data line is present. Rather, there is only a clock line. The value of the data to be transferred is embedded in the clock signal based on the absolute value of that clock signal.

FIG. 2is a timing diagram illustrating a clock signal, a modulated clock signal and a data signal according to one embodiment. In the example ofFIG. 2, each signal includes a two complimentary voltage signals. Transmitting data and clock signals in this manner allows for increased reliability in accurately receiving the data and clock signals. However, those of skill in the art will recognize that each signal may include only a single voltage signal.

The clock signal, generated by the clock signal generator26ofFIG. 1A, oscillates at a fixed frequency and has a fixed amplitude. At time T0the clock signal has an edge event in which both voltage signals transition from high to low or low to high. Each edge event can be considered a rising or falling edge of the clock signal depending on which voltage signal is analyzed. For example, if we refer to the voltage signal that is at the high value before time T0as the first voltage signal and the bottom signal as the second voltage signal, then it time T0a falling edge of the first voltage signal occurs, while a rising edge of the second voltage signal occurs. At time T1the first voltage signal has a rising edge in which the first voltage signal goes from the low value to the high-value. At time T2the first voltage signal has a falling edge event. The time elapsed between T0and T2is a full period T of oscillation of the clock signal. The frequency f of the clock signal is the inverse of the period T, or f=1/T. The frequency f of the clock signal ofFIG. 2is, for example, 500 MHz. The data signal is a double data rate DDR data signal. This means that a bit of data is transmitted with each edge of the clock signal. Thus, two bits of data can be transmitted on the data signal with each clock period T. InFIG. 2, the data signal is transmitted such that transitions in the data signal occur between transitions of the clock signal. The data edges and the clock edges keep a quadrature relation to maintain enough setup and hold time at the receiver end for the data lanes. However, it is not mandatory that the clock edges and data edges keep a quadrature relationship. The clock edge at the receiver can also be adjusted by several techniques known to clock in the data. The explanation and signal arrangement with respect to the quadrature related DDR data & clock has been provided as one example.

Each transition in the data signal corresponds to the value of the current bit changing from the previous value. For example, at time T0the current bit of the data signal is a logical “1”. After T0, a transition in the data signal occurs, indicating that the current bit is the opposite of the previous bit, a logical “0”. After T1, the data signal again transitions indicating that the current bit is the opposite of the previous bit, now a logical “1”. After T2a transition in the data signal occurs indicating that the current bit is now “0”. After time T3, no transition occurs in the data signal indicating that the current bit is still “0”. After time T4a transition in the data signal occurs indicating that the current bit is “1”. The transition does not occur after time T5, therefore indicating that the current bit is still “1”.

The modulated clock signal oscillates at the same frequency as the clock signal. Each transition in the clock signal corresponds to a transition in the modulated clock signal. However, the absolute value of the amplitude of the modulated clock signal can have either a first value V0or a second value V1. The value of the amplitude of the modulated clock signal indicates a particular bit of data. An example ofFIG. 2, the smaller amplitude V0indicates a logical “0” while the higher amplitude V1indicates a logical “1”. Thus, not only does the modulated clock signal oscillate in accordance with the clock signal, but it also carries data.

Between times T0and T1, the amplitude of the modulated clock signal is V0, indicating a logical “0”. At time T1the modulated clock signal transitions to amplitude V1, indicating a logical “1”. At time T2, the modulated clock signal transitions back to amplitude V0, indicating a logical “0”. At time T3the modulated clock signal transitions to amplitude V1, indicating a logical “1”. At time T4the amplitude of the modulated clock signal remains at V1, indicating a logical “1”. At time T5the modulated clock signal transitions to amplitude V0, indicating a logical “0”.

As can be seen fromFIG. 2, the modulated clock signal is a DDR data carrying clock signal. Each transition of the modulated clock signal corresponds to a new bit of data. Thus, each oscillation period T of the modulated clock signal carries two bits of data.

FIG. 3is systematic diagram of the clock data driver28according to one embodiment. This is one possible example for use of the present invention. The clock data driver28is coupled between two power supply rails, 2V1and ground. A plurality of resistors having values R1, R2, or R4are coupled between the high voltage supply 2V1and a respective first switch SV1+, SV1−, SV0+ or SV0−. A plurality of resistors having values R0, R3, and R5are coupled between an output pin36a/36band a respective second switch SV1+, SV1−, SV0+ or SV0−. The second switches are coupled to ground. The resistor Rris a resistance associated with the receiving device24as a termination resistor and, while not part of the clock data driver28, is shown to better illustrate the amplitude of the modulated clock signal as received at the clock and data receiver38of the data receiving device24. Rr=100Ω. The example values of the resistor R1=R0=50Ω. R2∥R3=R4∥R5=50Ω. 2*V1is, for example 400 mV.

The clock data driver28generates the modulated clock signal on the outputs36a,36bby selectively opening and closing the switches SV1+, SV1_, SV0+, SV0−in a particular manner in synchronization with the clock signal generated by the clock signal generator26. In this manner, the voltage difference between outputs36a,36bis modulated between the values V0and V1and has a frequency of oscillation identical to the clock signal.

In one embodiment, when a digital “1” is to be encoded into the modulated clock signal, all switches SV1+ are closed in one half cycle of the modulated clock signal while all switches SV1−are open. In the next half cycle, all switches SV1+ are opened and all switches SV1−are closed. Thus, when the value of the data in the modulated clock signal is “1”, the switches SV1+and SV1−are alternately opened and closed with each edge event. Meanwhile, SV0+and SV0−are opened while a digital “1” is encoded in the modulated clock signal. This causes the amplitude of the voltage between the output pins36a,36bto be V1, with the polarity switching after each half cycle (i.e. with each edge event) of the clock signal.

In one embodiment, when a digital “0” is to be encoded into the modulated clock signal, all switches SV0+ are closed in one half cycle of the modulated clock signal while all switches SV0−are open. In the next half cycle, all switches SV0+ are opened and all switches SV0−are closed. Thus, when the value of the data in the modulated clock signal is “0”, the switches SV0+ and SV0−are alternately opened and closed with each edge event. Meanwhile, SV1+and SV1−are continually held open when a digital “0” is encoded in the modulated clock signal. This causes the amplitude of the voltage between the output pins36a,36bto be V0, with the polarity switching after each half cycle (ie with each edge event) of the clock signal. The value of V0is half the value of V1, or about 100 mV.

FIG. 4is a schematic diagram of the clock data driver28according to one embodiment. The clock data driver28ofFIG. 4includes four supply voltages 2V1, 1.5V1, 0.5V1, selectively coupled between output pins36a,36bby respective switches. In particular, the supply voltage 2V1is coupled to the output pin36aby a first switch SV1+. The supply voltage 2V1is coupled to the output pin36bby first switch SV1−. The supply voltage 1.5 V1is coupled to the output pin36aby a first switch SV0+. The supply voltage 1.5 V1is coupled to the output pin36bby a first switch SV0−. The supply voltage 0.5V1is coupled to the output pin36aby a second switch SV0−. The supply voltage 0.5 V1is coupled to the output pin36bby a second switch SV0+. The supply voltage ground is coupled to the output pin36aby a second switch SV1−. The supply voltage ground is coupled to the output pin36bby a second switch SV1+. The resistors Rtare resistances associated with the data transmitting device22. Rt=50Ω. The resistor Rris a resistance associated with the receiving device24and, while not part of the clock data driver28, is shown to better illustrate the amplitude of the modulated clock signal as received at the clock and data receiver38of the data receiving device24. Rr=100Ω.

In one embodiment, when a digital “1” is to be encoded into the modulated clock signal, all switches SV1+ are closed in one half cycle of the modulated clock signal while all switches SV1−are open. In the next half cycle, all switches SV1+ are opened and all switches SV1−are closed. Thus, when the value of the data in the modulated clock signal is “1”, the switches SV1+and SV1−are alternately opened and closed with each edge event. Meanwhile, SV0+and SV0−are opened while a digital “1” is encoded in the modulated clock signal. This causes the amplitude of the voltage between the output pins36a,36bto be V1, with the polarity switching after each half cycle (ie with each edge event) of the clock signal.

In one embodiment, when a digital “0” is to be encoded into the modulated clock signal, all switches SV0+ are closed in one half cycle of the modulated clock signal while all switches SV0−are open. In the next half cycle, all switches SV0+ are opened and all switches SV0−are closed. Thus, when the value of the data in the modulated clock signal is “0”, the switches SV0+ and SV0−are alternately opened and closed with each edge event. Meanwhile, SV1+and SV1−are continually held open when a digital “0” is encoded in the modulated clock signal. This causes the amplitude of the voltage between the output pins36a,36bto be V0, with the polarity switching after each half cycle (ie with each edge event) of the clock signal. The value of V0is half the value of V1, or about 100 mV.

FIG. 5is an example schematic diagram of a data receiving device24according to one embodiment. The data receiving device24includes a clock and data receiver38and a data retrieval circuit40coupled to the clock and data receiver38. The clock and data receiver38is coupled to clock inputs46a,46b. The data retrieval circuit40is coupled to data inputs44a,44b.

The clock and data receiver38includes a first differential difference amplifier58, a second differential difference amplifier60, a comparator62, an XOR gate64, and a delay circuit66. The clock input pins46a,46breceive the modulated clock signal from the data transmission device22via the dedicated clock Lane50. In particular, the modulated clock signal is received in two complementary signals on the clock input pins46a,46b. As described previously, the modulated clock signal can have one of two amplitudes. When the modulated clock signal has amplitude V1, the voltage difference between the clock inputs46a,46bis V1. When the modulated clock signal has amplitude V0, the voltage difference between the clock inputs46a,46bis V0, approximately half of V1. In one embodiment, V1=200 mV and V0equals 100 mV.

The first differential difference amplifier58has four signal inputs, an upper non-inverting input +, an upper inverting input −, a lower non-inverting input +, and a lower inverting input −. The modulated clock signal is passed from the clock inputs46a,46bto the upper inverting and non-inverting inputs of the first differential difference amplifier58. A threshold voltage Vthis provided between the lower non-inverting and inverting inputs of the first differential difference amplifier58. The absolute value of the threshold voltage Vthis between V0and V1and has a value selected so that the first differential difference amplifier58can reliably detect whether the modulated clock signal is at V1or V0.

The first differential difference amplifier58outputs a high voltage, or logical “1”, if the voltage difference between the input pin46aand46bis greater than Vthand positive. The first differential difference amplifier58outputs a low-voltage, or logical “0”, for all other cases.

The second differential difference amplifier60is configured similar to the first differential difference amplifier58except that a threshold voltage −Vthis received between the lower non-inverting and inverting inputs of the differential difference amplifier60. The second differential difference amplifier60outputs a high voltage, or logical “1”, if the voltage difference between the input pin46aand46bis greater in magnitude than Vthand negative. The second differential difference amplifier60outputs a low voltage, or logical “0”, for all other cases.

The first and second differential difference amplifiers58,60each provide their outputs to a respective input of the XOR gate64. If either of the outputs of the differential difference amplifier58,60is high, then the XOR gate64outputs a high voltage or logical “1”. If both of the outputs of the differential difference amplifier's58,60are low, then the XOR gate64outputs a low-voltage or logical “0”. The output of the XOR gate64is indicative of the data encoded into the modulated clock signal. The XOR gate64passes its output to the data retrieval circuit40.

The modulated clock signal is also passed from the clock inputs46a,46bto the comparator62. The comparator62outputs a high voltage, or logical “one” if the voltage at the non-inverting input is greater than the voltage on the inverting input. The comparator62outputs a low-voltage, or logical “0” if the voltage at the non-inverting input is less than the voltage on the inverting input. The output of the comparator62reflects the clock signal without amplitude modulation because the comparator62only outputs a logical high or a logical low.

The output of the comparator62is passed to a variable delay circuit66which introduces a selected delay into the clock signal output from the comparator62in order to properly synchronize the data retrieving circuit40with the data received by the data receiving device24. The output of the variable delay circuit66is the clock signal by which the data retrieval circuit40is synchronized to the data transmitting device22. In one embodiment, the variable delay circuit66includes a plurality of buffer circuits connected in series. The number of buffer circuits active in the series can be increased or decreased to increase or decrease the delay by operating switches coupled to the buffer circuit66.

In one embodiment, the proper delay can be calibrated by encoding only “0s” into the modulated clock signal while sending a stream of training data on the data lane48. The delay circuit66can be adjusted until data signal is properly synchronized with the modulated clock signal.

The data retrieval circuit40includes a comparator56coupled to data inputs44a,44bwhich receive the data signal from the data transmission device22via the data Lane48. The comparator56outputs a high voltage, or logical “1” if the voltage at the non-inverting input is greater than the voltage on the inverting input. The comparator62outputs a low-voltage, or logical “0” if the voltage at the non-inverting input is less than the voltage on the inverting input. The output of the comparator56is indicative of the data encoded in the data signal. The output of the comparator56will remain constant until a new data value is received.

The output of the comparator56passed to the set inputs S of two flip-flops70c,70d. The flip-flops70c,70dalso receive on their clock inputs the output of the variable delay circuit66. In one embodiment, the variable delay clock circuit provides a different delay for different channels of data to deskew data and clock the proper amounts. This is illustrated in the figure as a separate output from variable delay circuit66, but it can also be realized by having a different variable delay circuit66for each channel. The clock input of the flip-flop70cis inverted with respect to the clock input of the flip-flop70d. The outputs Q of the flip-flops70d,70ccorrespond to the retrieve data from the data signal. The outputsQof the flip-flops70c,70dare the logical opposites of the outputs Q of the flip-flops70D,70C

The output of the XOR gate64is passed to the set inputs S of two flip-flops70a,70b. The flip-flops70a,70balso receive on their clock inputs the output of the variable delay circuit66. The clock input of the flip-flop70ais inverted with respect to the clock input of the flip-flop70b. The outputs Q of the flip-flops70a,70bcorrespond to the retrieved data from the modulated clock signal. The outsQof the flip-flops70a,70bare the logical opposites of the outputs Q of the flip-flops70a,70b.

To ensure reliable retrieval of the first data from the modulated clock signal, in one embodiment the threshold voltage Vthcan be calibrated to ensure reliable detection of amplitudes V0and V1of the of the modulated clock signal. In one example, during a calibration process the clock data driver28can encode1-0-1-0into the modulated clock signal. The data receiving device24can adjust the threshold voltage Vthuntil the data retrieval circuit40can reliably detect1-0-1-0in the modulated clock signal. The data receiving device24can include a digital-to-analog converter to generate and incrementally adjust Vthduring calibration.

FIG. 6is a schematic diagram of one example of the differential difference amplifier58ofFIG. 5according to one embodiment. The differential difference amplifier58includes a pair PMOS transistor74,76each receiving on its source terminal the output of a current source ID1. The gate terminal of the transistor74is coupled to the clock input46a, while the gate terminal of the transistor76is coupled to the clock input46b. The drain terminal of the transistor74is coupled to the inverting input of the comparator78. The drain terminal of the transistor76is coupled to the non-inverting input of the comparator78. Two resistors R6are coupled between ground and a respective input of the comparator78. The differential difference amplifier58further includes a second pair of PMOS transistors80,82. The source terminals of the transistors80,82are coupled to a second current source ID2. The gate terminals of the transistors80,82receive Vthbetween them.

The first differential difference amplifier58outputs a high voltage, or logical “1”, if the voltage difference between the input pin46aand46b(V46a-V46b) is greater than Vthand positive. The first differential difference amplifier58outputs a low voltage, or logical “0”, for all other cases.

Though not shown in the Figures, the second differential difference amplifier60can be substantially identical to the first differential difference amplifier58except that −Vthis applied between the equivalents of transistors80,82.

FIG. 7is a timing diagram showing a clock signal and a modulated clock signal according to one embodiment. In particular, the timing diagram ofFIG. 7illustrates that the modulated clock signal can carry multiple bits per half cycle. For example, the clock data driver28can modulate the amplitude of the modulated clock signal between one of four amplitudes, V00, V01, V10, V11as shown inFIG. 7. This is type of signal is different from a standard pulse amplitude modulation signal, where positive and negative amplitudes with same absolute value is considered two different symbols. In the embodiments descried herein, V00, V11etc. carries symbols as per the absolute values of the clock, i.e., differential negative or positive. Thus, V00will mean the same symbol, so on. Toggling of positive and negative differential value is to carry clock edge information only.

At time T0, the amplitude of the modulated clock signal transitions to amplitude V01, indicating that the current data bits have digital value “01”. At time T1, the amplitude of the modulated clock signal transitions to amplitude V10, indicating that the current data bits have digital value “10”. V10is greater than V01. At time T2, the amplitude of the modulated clock signal transitions to amplitude V00, indicating that the current data bits have digital value “00”. V00is less than V01. At time T3, the amplitude of the modulated clock signal transitions to amplitude V11, indicating that the current data bits have digital value “11”. V11is less than V10. At time T4, the amplitude of the modulated clock signal transitions to amplitude V00, indicating that the current data bits have digital value “00”. At time T5, the amplitude of the modulated clock signal transitions to amplitude V01, indicating that the current data bits have digital value “01”. The reception also happens similarly with multiple decision thresholds. Those of skill in the art will understand, in light of the present disclosure, that more than two bits can be included in each half cycle of the modulated clock signal.