Uninterruptible power supply system

A plurality of gate drive circuits each drive a gate of a corresponding one of a plurality of switching elements included in a converter and an inverter. Each gate drive circuit includes a gate driver and a power source circuit. The gate driver drives the gate potential of the switching element to a potential corresponding to H or L level, in accordance with the gate signal input from a controller to the gate electrode of the switching element. The power source circuit supplies power to the gate driver. When a first switch is ON and a second switch is OFF, the controller, upon detection of an abnormality of the power source circuit of the gate drive circuit, turns on the second switch and turns off the first switch. The gate drive circuit maintains the gate potential of the switching element during the period from when the abnormality of the power source circuit is detected to when the second switch is turned on.

TECHNICAL FIELD

The present invention relates to an uninterruptible power supply system.

BACKGROUND ART

For example, Japanese Patent Laying-Open No. 11-178243 (PTL 1) discloses an uninterruptible power supply system including a converter that converts AC power from a commercial power source into DC power, and an inverter that converts DC power into AC power to supply the AC power to a load. The uninterruptible power supply system described in PTL 1 includes an output switch between the inverter and the load, and a thyristor switch between the commercial power source and the load. The uninterruptible power supply system is configured to switch between the commercial power source and the inverter for power supply to the load, based on an ON instruction to the output switch or thyristor switch.

In the system of PTL 1, when an abnormality is detected in the control power source for a control means that generates the ON instruction during the inverter power supply mode, a circuit for detecting abnormality in the control power source sends an abnormality detection signal while the control power source is backed up by a capacitor. With this configuration, an abnormality of the control power source causes switching from the inverter to the commercial power source, thereby allowing uninterrupted power supply to the load.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

Such an uninterruptible power supply system typically includes gate drive circuits for driving the gates of a plurality of switching elements included in the converter and inverter. Each gate drive circuit is configured to drive the gate potential of a corresponding switching element to a logical high (H) level or logical low (L) level in accordance with a gate signal from a controller.

When an abnormality occurs in a power source for such a gate drive circuit, the power source cannot properly supply a source voltage to the gate drive circuit. This may cause an unsteady gate potential of the switching element until the power supply to the load is switched from the inverter to the commercial power source. During this time, the switching element may malfunction, such as being erroneously turned on or erroneously turned off.

The present invention has been made to solve such a problem. An object of the present invention is to provide an uninterruptible power supply system that can switch from an inverter to a bypass AC power source for power supply to a load, upon occurrence of an abnormality of the power source for a gate drive circuit, without causing malfunctions of a switching element.

Solution to Problem

An uninterruptible power supply system according to the present invention includes a first terminal connected to a commercial AC power source, a second terminal connected to a bypass AC power source, a third terminal connected to a load, a converter, an inverter, a first switch, a second switch, a controller, and a plurality of gate drive circuits. The converter includes a plurality of switching elements, and converts AC power supplied from the commercial AC power source through the first terminal into DC power. The inverter includes a plurality of switching elements, and converts DC power generated by the converter or DC power from a power storage device into AC power. The first switch has one terminal that receives an output voltage of the inverter, and the other terminal connected to the third terminal. The second switch is connected between the second terminal and the third terminal. The controller controls on and off of the plurality of switching elements included in the converter and the inverter. The plurality of gate drive circuits each drive a gate of a corresponding switching element of the plurality of switching elements. Each of the plurality of gate drive circuits includes a gate driver and a power source circuit. The gate driver drives a gate potential of the switching element to a potential corresponding to an H level or an L level, in accordance with a gate signal input from the controller to a gate electrode of the switching element. The power source circuit supplies power to the gate driver. The controller includes an abnormality detection circuit that detects an abnormality of the power source circuit of each of the plurality of gate drive circuits. When the first switch is ON and the second switch is OFF, the controller, upon detection of the abnormality of the power source circuit by the abnormality detection circuit, turns on the second switch and turns off the first switch. The gate drive circuit maintains the gate potential of the switching element during a period from when the abnormality of the power source circuit is detected to when the second switch is turned on.

Advantageous Effects of Invention

The present invention provides an uninterruptible power supply system that can switch from an inverter to a bypass AC power source for power supply to a load, upon occurrence of an abnormality of the power source for a gate drive circuit, without causing malfunctions of a switching element.

DESCRIPTION OF EMBODIMENTS

An embodiment of the present invention will now be described in detail with reference to the drawings. Identical or corresponding parts in the drawings are denoted by identical reference signs, and the description of such parts is not basically repeated.

FIG. 1is a circuit block diagram showing a configuration of an uninterruptible power supply system according to an embodiment of the present invention. An uninterruptible power supply system1converts three-phase AC power from a commercial AC power source21into DC power, and converts the DC power into three-phase AC power to supply the AC power to a load24. For simplicity of the illustration and description,FIG. 1shows a circuit for only a single phase (e.g., U phase) of the three phases (U, V, and W phases).

Uninterruptible power supply system1has an inverter power supply mode (first mode) and a bypass power supply mode (second mode). The inverter power supply mode is an operation mode in which AC power is supplied from an inverter10to load24. The bypass power supply mode is an operation mode in which AC power is supplied from a bypass AC power source22to load24through a semiconductor switch15(second switch).

In the inverter power supply mode, AC power supplied from commercial AC power source21is converted into DC power by a converter6, and the DC power is converted into AC power by inverter10to be supplied to load24. The inverter power supply mode allows stable power supply to load24.

In the bypass power supply mode, AC power supplied from bypass AC power source22is supplied to load24through semiconductor switch15(second switch), i.e., not through converter6and inverter10. The bypass power supply mode does not involve power losses at converter6and inverter10, allowing increased operating efficiency of uninterruptible power supply system1.

InFIG. 1, uninterruptible power supply system1includes an AC input terminal T1, a bypass input terminal T2, a battery terminal T3, and an AC output terminal T4. AC input terminal T1receives AC power having a commercial frequency from commercial AC power source21. Bypass input terminal T2receives AC power having a commercial frequency from bypass AC power source22. Bypass AC power source22may be a commercial AC power source or a generator.

Battery terminal T3is connected to a battery (power storage device)23. Battery23stores DC power. Instead of battery23, a capacitor may be connected. AC output terminal T4is connected to load24. Load24is driven by AC power.

Electromagnetic contactor2and reactor5are connected in series between AC input terminal T1and the input node of converter6. Capacitor4is connected to a node N1between electromagnetic contactor2and reactor5. Electromagnetic contactor2is turned on at the time of use of uninterruptible power supply system1, and is turned off at the time of, for example, maintenance of uninterruptible power supply system1.

The instantaneous value of AC input voltage Vi appearing at node N1is detected by controller18. Based on the instantaneous value of AC input voltage Vi, controller18determines, for example, whether a power outage has occurred. Current detector3detects an AC input current Ii flowing through node N1, and provides a signal Iif indicating the detection value to controller18.

Capacitor4and reactor5form a low-pass filter. The low-pass filter allows AC power having a commercial frequency from commercial AC power source21to pass to converter6, and blocks a signal having a switching frequency generated at converter6from passing to commercial AC power source21.

Converter6is controlled by controller18. At normal times, in which AC power is supplied from commercial AC power source21, converter6converts AC power into DC power and outputs the DC power to a DC line L1. At the time of a power outage, in which supply of AC power from commercial AC power source21is stopped, the operation of converter6is stopped. The output voltage of converter6can be controlled into a desired value.

Capacitor9is connected to DC line L1and smooths the voltage in DC line L1. The instantaneous value of DC voltage VDC appearing in DC line L1is detected by controller18. Bidirectional chopper7has a high-voltage node connected to DC line L1, and a low-voltage node connected to battery terminal T3via electromagnetic contactor8.

Electromagnetic contactor8is turned on at the time of use of uninterruptible power supply system1, and is turned off at the time of, for example, maintenance of uninterruptible power supply system1and battery23. The instantaneous value of a voltage VB between the terminals of battery23appearing at battery terminal T3is detected by controller18.

Bidirectional chopper7is controlled by controller18. At normal times, in which AC power is supplied from commercial AC power source21, bidirectional chopper7supplies DC power generated by converter6to battery23for storage therein. At the time of a power outage, in which supply of AC power from commercial AC power source21is stopped, bidirectional chopper7supplies DC power from battery23to inverter10via DC line L1.

When bidirectional chopper7supplies DC power to battery23for storage therein, bidirectional chopper7steps down DC voltage VDC in DC line L1, and provides the stepped-down voltage to battery23. When bidirectional chopper7supplies DC power from battery23to inverter10, bidirectional chopper7boosts voltage VB between the terminals of battery23, and outputs the boosted voltage to DC line L1. DC line L1is connected to the input node of inverter10.

Inverter10is controlled by controller18, so that inverter10converts DC power supplied from converter6or bidirectional chopper7via DC line L1into AC power having a commercial frequency, and outputs the AC power. Specifically, at normal times, inverter10converts DC power supplied from converter6via DC line L1into AC power; and at the time of a power outage, inverter10converts DC power supplied from battery23via bidirectional chopper7into AC power. The output voltage of inverter10can be controlled into a desired value.

Inverter10has an output node10aconnected to one terminal of reactor12. The other terminal of reactor12(node N2) is connected to AC output terminal T4via electromagnetic contactor14. Capacitor13is connected to node N2.

Current detector11detects the instantaneous value of an output current Io of inverter10, and provides a signal Iof indicating the detection value to controller18. The instantaneous value of an AC output voltage Vo appearing at node N2is detected by controller18.

AC power having a commercial frequency generated at inverter10to pass to AC output terminal T4, and blocks a signal having a switching frequency generated at inverter10from passing to AC output terminal T4.

Electromagnetic contactor14is controlled by controller18to be turned on in the inverter power supply mode, and to be turned off in the bypass power supply mode. In this specification, electromagnetic contactor14is also referred to as an “output switch” for supplying the output power of inverter10to load24. Electromagnetic contactor14corresponds to an example of the “first switch”.

Semiconductor switch15, which includes thyristors, is connected between bypass input terminal T2and AC output terminal T4. Semiconductor switch15is controlled by controller18to be turned off in the inverter power supply mode, and to be turned on in the bypass power supply mode. Semiconductor switch15corresponds to an example of the “second switch”. For example, a failure of inverter10occurring in the inverter power supply mode immediately turns on semiconductor switch15, thereby supplying AC power from bypass AC power source22to load24. The instantaneous value of an AC input voltage Vi2appearing at node N3between bypass input terminal T2and semiconductor switch15is detected by controller18. The instantaneous values of AC input voltage Vi2and AC output voltage Vo are used to determine whether or not the voltage of bypass AC power source22and the output voltage of inverter10are synchronized.

Operation unit17includes, for example, a plurality of buttons to be operated by the user of uninterruptible power supply system1, and an image display that displays various pieces of information. The user can operate operation unit17to power on and off uninterruptible power supply system1and select any one of the bypass power supply mode and the inverter power supply mode.

Controller18controls the overall uninterruptible power supply system1based on, for example, the signal from operation unit17, AC input voltages Vi, Vi2, AC input current Ii, DC voltage VDC, battery voltage VB, AC output current Io, and AC output voltage Vo. Specifically, controller18determines whether or not a power outage has occurred based on the detection value of AC input voltage Vi, and controls converter6and inverter10in synchronization with the phase of AC input voltage Vi.

Controller18controls converter6so that, at normal times, in which AC power is supplied from commercial AC power source21, DC voltage VDC will be a desired target voltage VDCT; and at the time of a power outage, in which supply of AC power from commercial AC power source21is stopped, the operation of converter6is stopped.

Controller18also controls bidirectional chopper7so that, at normal times, battery voltage VB will be a desired target battery voltage VBT; and at the time of a power outage, DC voltage VDC will be desired target voltage VDCT.

FIG. 2is a circuit diagram showing the major portion of uninterruptible power supply system1shown inFIG. 1. AlthoughFIG. 1shows a portion related to only a single phase of a three-phase AC voltage,FIG. 2shows a portion related to three phases.FIG. 2does not show electromagnetic contactors2,14, semiconductor switch15, operation unit17, and controller18.

AC input terminals T1a, T1b, and T1crespectively receive AC voltages in three phases (U-, V-, and W-phases) from commercial AC power source21(FIG. 1). AC voltages in three phases respectively synchronized with AC voltages in three phases from commercial AC power source21are output to AC output terminals T4a, T4b, T4c. The AC voltages in three phases from AC output terminals T4a, T4b, T4care used to drive load24.

Reactors5a,5b,5ceach have one terminal connected to a corresponding one of AC input terminals T1a, T1b, T1c; and the other terminal connected to a corresponding one of input nodes6a,6b,6cof converter6. Capacitors4a,4b,4ceach have one electrode connected to one terminal of a corresponding one of reactors5a,5b,5c; and the other electrode connected to a neutral point NP.

Capacitors4a,4b,4cand reactors5a,5b,5cform a low-pass filter. The low-pass filter allows three-phase AC power having a commercial frequency from AC input terminals T1a, T1b, T1cto pass to converter6, and blocks a signal having a switching frequency generated at converter6. The instantaneous value of AC input voltage Vi appearing at one terminal of reactor5ais detected by controller18(FIG. 1). Current detector3detects AC input current Ii flowing through node N1(i.e., AC input terminal T1a), and provides signal Iif indicating the detection value to controller18.

Converter6includes insulated gate bipolar transistors (IGBTs) Q1to Q6and diodes D1to D6. The IGBTs correspond to the “switching elements”. IGBTs Q1, Q2, Q3have their respective collectors all connected to DC line L1, and have their respective emitters connected to input nodes6a,6b,6c. IGBTs Q4, Q5, Q6have their respective collectors connected to input nodes6a,6b,6c, and have their respective emitters all connected to DC line L2. Diodes D1to D6are connected in antiparallel to IGBTs Q1to Q6, respectively.

IGBTs Q1, Q2, Q3are respectively turned on when gate signals Au, Av, Aw transition to the “logical high (H)” level, and are respectively turned off when gate signals Au, Av, Aw transition to the “logical low (L)” level. IGBTs Q4, Q5, Q6are respectively turned on when gate signals Bu, By, Bw transition to the “H” level, and are respectively turned off when gate signals Bu, By, Bw transition to the “L” level.

Each of gate signals Au, Bu, Av, By, Aw, Bw, which is a train of pulse signals, is a pulse width modulation (PWM) signal. Gate signals Au, Bu; gate signals Av, By; and gate signals Aw, Bw are shifted in phase by 120° relative to each other. Gate signals Au, Bu, Av, By, Aw, Bw are generated by controller18.

For example, when AC input terminal T1ahas a higher voltage level than AC input terminal T1b, IGBTs Q1, Q5are turned on. In this case, a current flows from AC input terminal T1athrough reactor5a, IGBT Q1, DC line L1, capacitor9, DC line L2, IGBT Q5, and reactor5bto AC input terminal T1b, so that capacitor9is charged with a positive voltage.

When AC input terminal T1bhas a higher voltage level than AC input terminal T1a, IGBTs Q2, Q4are turned on. In this case, a current flows from AC input terminal T1bthrough reactor5b, IGBT Q2, DC line L1, capacitor9, DC line L2, IGBT Q4, and reactor5ato AC input terminal T1a, so that capacitor9is charged with a positive voltage. Similar things apply for other cases.

A three-phase AC voltage provided to input nodes6a,6b,6ccan be converted into a DC voltage VDC (a voltage between the terminals of capacitor9) by turning on and off IGBTs Q1, Q2, Q3, Q4, Q5, Q6via gate signals Au, Bu, Av, By, Aw, Bw at predetermined timings, and adjusting the “on” time of IGBTs Q1, Q2, Q3, Q4, Q5, Q6.

Inverter10includes IGBTs Q11to Q16and diodes D11to D16. The IGBTs correspond to the “switching elements”. IGBTs Q11, Q12, Q13have their respective collectors all connected to DC line L1, and have their respective emitters connected to output nodes10a,10b,10c. IGBTs Q14, Q15, Q16have their respective collectors connected to output nodes10a,10b,10c, and have their respective emitters all connected to DC line L2. Diodes D11to D16are connected in antiparallel to IGBTs Q11to Q16, respectively.

IGBTs Q11, Q12, Q13are respectively turned on when gate signals Xu, Xv, Xw transition to the H level, and are respectively turned off when gate signals Xu, Xv, Xw transition to the L level. IGBTs Q14, Q15, Q16are respectively turned on when gate signals Yu, Yv, Yw transition to the H level, and are respectively turned off when gate signals Yu, Yv, Yw transition to the L level.

Each of gate signals Xu, Yu, Xv, Yv, Xw, Yw, which is a train of pulse signals, is a PWM signal. Gate signals Xu, Yu; gate signals Xv, Yv; and gate signals Xw, Yw are shifted in phase by 120° relative to each other. Gate signals Xu, Yu, Xv, Yv, Xw, Yw are generated by controller18.

For example, when IGBTs Q11, Q15are turned on, positive DC line L1is connected to output node10avia IGBT Q11, and negative DC line L2is connected to output node10bvia IGBT Q15. This causes a positive voltage to be output between output nodes10a,10b.

When IGBTs Q12, Q14are turned on, positive DC line L1is connected to output node10bvia IGBT Q12, and negative DC line L2is connected to output node10avia IGBT Q14. This causes a negative voltage to be output between output nodes10a,10b.

A DC voltage between DC lines L1and L2can be converted into a three-phase AC voltage by turning on and off IGBTs Q11, Q12, Q13, Q14, Q15, Q16via gate signals Xu, Yu, Xv, Yv, Xw, Yw at predetermined timings, and adjusting the “on” time of IGBTs Q11, Q12, Q13, Q14, Q15, Q16.

Reactors12a,12b,12ceach have one terminal connected to a corresponding one of output nodes10a,10b,10cof inverter10; and the other terminal connected to a corresponding one of AC output terminals T4a, T4b, T4c. Capacitors13a,13b,13ceach have one electrode connected to the other terminal of a corresponding one of reactors12a,12b,12c; and the other electrode connected to neutral point NP.

Reactors12a,12b,12cand capacitors13a,13b,13cform a low-pass filter. The low-pass filter allows three-phase AC power having a commercial frequency from inverter10to pass to AC output terminals T4a, T4b, T4c, and blocks a signal having a switching frequency generated at inverter10.

Current detector11detects AC output current Io flowing through reactor12a, and provides signal Iof indicating the detection value to controller18. The instantaneous value of AC output voltage Vo appearing at the other terminal of reactor12a(node N2) is detected by controller18(FIG. 1).

FIG. 3is a block diagram showing a configuration of a portion related to control of a switching element in each of converter6and inverter10shown inFIG. 1. InFIG. 3, IGBTs Q1to Q6in converter6and IGBTs Q11to Q16in inverter10are generically referred to as IGBT Qx.

With reference toFIG. 3, IGBT Qx is connected to a gate drive circuit30. Gate drive circuit30includes a gate driver30A that drives IGBT Qx in accordance with a gate signal from controller18, and a power source circuit30B that supplies power to gate driver30A.

Power source circuit30B converts AC power supplied from AC power source31into a DC voltage, and outputs the DC voltage to DC buses PL1, NL1. AC power source31is typically a commercial AC power source that supplies an AC voltage having a predetermined frequency (e.g., 50 or 60 Hz). The DC voltage output from power source circuit30B is hereinafter also simply referred to as an output voltage. The output voltage is supplied to gate driver30A electrically connected between DC positive bus PL1and DC negative bus NL1.

The configuration of power source circuit30B will now be described. Power source circuit30B includes AC power source31, a transformer32, a rectifier33, DC positive bus PL1, DC negative bus NL1, a DC neutral point bus CL1, and smoothing capacitors C1, C2.

Transformer32includes a primary winding and a secondary winding. The primary winding is electrically connected to AC power source31. The AC voltage supplied from AC power source31is applied to the primary winding. The amplitude of the AC voltage is converted in accordance with the turn ratio between the primary winding and the secondary winding, and the AC voltage with the converted amplitude is output to the secondary winding. The AC voltage output to the secondary winding has the same frequency as the AC voltage of the primary winding.

Rectifier33has a diode bridge. Rectifier33performs full-wave rectification of the AC voltage output to the secondary winding of transformer32, and outputs the rectified AC voltage to DC positive bus PL1and DC negative bus NL1.

Smoothing capacitors C1, C2are connected in series between DC positive bus PL1and DC negative bus NL1. Smoothing capacitors C1, C2are, for example, electrolytic capacitors. Smoothing capacitors C1, C2smooth the voltage rectified by rectifier33. Smoothing capacitors C1, C2thus allow the voltage between DC positive bus PL1and DC negative bus NL1to be maintained at a DC voltage corresponding to the amplitude of the output voltage from the secondary winding of transformer32. Thus, power from AC power source31can provide a source voltage to gate driver30A. The connection point between smoothing capacitors C1and C2is connected to DC neutral point bus CL1. DC neutral point bus CL1is electrically connected to the emitter of IGBT Qx.

The configuration of gate driver30A will now be described. Gate driver30A includes an npn transistor Tr1, a pnp transistor Tr2, and a gate resistor R1. Npn transistor Tr1has a collector connected to DC positive bus PL1, and an emitter connected to the collector of pnp transistor Tr2. Pnp transistor Tr2has an emitter connected to DC negative bus NL1. Gate resistor R1is electrically connected between the connection point between npn transistor Tr1and pnp transistor Tr2, and the gate electrode of IGBT Qx.

Npn transistor Tr1and pnp transistor Tr2have a control electrode (base) to receive a gate signal applied by controller18. Npn transistor Tr1and pnp transistor Tr2are complementarily turned on and off in accordance with the gate signal. Specifically, while the gate signal is at the H level, npn transistor Tr1is ON and pnp transistor Tr2is OFF. During this time, a drive current for charging the gate electrode of IGBT Qx is supplied from DC positive bus PL1to the gate electrode through npn transistor Tr1. The charging path via gate resistor R1causes the gate electrode to be driven to the higher potential. This cause the gate-source voltage of IGBT Qx to exceed a threshold voltage, in response to which IGBT Qx is turned on.

While the gate signal is at the L level, npn transistor Tr1is OFF and pnp transistor Tr2is ON. This forms a discharging path extending from the gate electrode of IGBT Qx to DC negative bus NL1via gate resistor R1, and causes the gate-source voltage to drop below the threshold voltage, in response to which IGBT Qx is turned off.

In this way, gate driver30A can receive power supply from power source circuit30B to turn on and off IGBT Qx in accordance with the gate signal supplied from controller18.

Controller18generates a gate signal for IGBT Qx included in each of converter6and inverter10, generates a control instruction for controlling the on and off of semiconductor switch15(second switch) (hereinafter also referred to as a “semiconductor switch ON instruction”), and generates a control instruction for controlling the on and off of output switch14(first switch) (hereinafter also referred to as an “output switch ON instruction”).

Semiconductor switch15is turned on when the semiconductor switch ON instruction transitions to the H level, and is turned off when the semiconductor switch ON instruction transitions to the L level. Output switch14is turned on when the output switch ON instruction transitions to the H level, and is turned off when the output switch ON instruction transitions to the L level.

Specifically, in the inverter power supply mode, controller18generates an H-level output switch ON instruction and generates an L-level semiconductor switch ON instruction. While output switch14is ON, AC power generated by inverter10is supplied to load24.

In the bypass power supply mode, controller18generates an H-level semiconductor switch ON instruction and generates an L-level output switch ON instruction. While semiconductor switch15is ON, AC power from bypass AC power source22is supplied to load24.

Controller18is further configured to detect an abnormality of AC power source31in gate drive circuit30in the inverter power supply mode. Upon detecting an abnormality of AC power source31, controller18shifts the output switch ON instruction from the H level to the L level, and shifts the semiconductor switch ON instruction from the L level to the H level. This causes uninterruptible power supply system1to shift from the inverter power supply mode to the bypass power supply mode. Uninterruptible power supply system1can thus uninterruptedly supply power to load24even after an abnormality occurs in AC power source31.

Controller18is powered by a control power source19, provided separately from AC power source31. Thus, controller18can perform switching between the inverter power supply mode and the bypass power supply mode even with an abnormality of AC power source31.

However, when an abnormality of AC power source31occurs, power source circuit30B cannot properly supply a source voltage to gate driver30A. This may cause an unsteady potential at the gate electrode of IGBT Qx until semiconductor switch15is turned on. IGBT Qx may thus malfunction, such as being erroneously turned on or erroneously turned off.

With reference toFIGS. 4 and 5, the problems associated with an abnormality of an AC power source in a gate drive circuit according to a comparative example will now be described.

FIG. 4shows a gate drive circuit100according to a comparative example. Gate drive circuit100according to the comparative example includes a gate driver100A and a power source circuit100B, as with gate drive circuit30shown inFIG. 3. Gate driver100A and power source circuit100B are respectively similar in configuration to gate driver30A and power source circuit30B shown inFIG. 3, except for smoothing capacitors C10, C20. Smoothing capacitors C10, C20are film capacitors, for example.

In gate drive circuit100shown inFIG. 4, one end of the primary winding of transformer32is denoted by “point A”, the connection point between DC positive bus PL1and one end of smoothing capacitor C10is denoted by “point B”, the control electrode of npn transistor Tr1in gate driver100A is denoted by “point C”, and the gate electrode of IGBT Qx is denoted by “point D”.

FIG. 5is a waveform chart schematically showing the temporal changes in potential at points A to D inFIG. 4when an abnormality occurs in AC power source31for gate drive circuit100according to the comparative example.

With reference toFIG. 5, the potential at point A shows the power source potential supplied from AC power source31. The potential at point B shows the potential in DC positive bus PL1. The potential at point C shows the potential of the gate signal supplied from controller18. The potential at point D shows the potential at the gate electrode of IGBT Qx. In the example ofFIG. 5, the control electrode of npn transistor Tr1and pnp transistor Tr2is receiving input of an H-level gate signal from a controller (not shown).

When AC power source31is normal, the AC voltage supplied from AC power source31undergoes amplitude conversion at transformer32, then undergoes full-wave rectification at rectifier33, and is then output to DC positive bus PL1. The potential in DC positive bus PL1(point B) is smoothed by smoothing capacitor C10and maintained at a DC voltage having an amplitude proportional to the amplitude of the power source potential (point A). Npn transistor Tr1, when receiving an H-level gate signal (point C) at its control electrode, is turned on. This causes the potential at the gate electrode of IGBT Qx (point D) to be driven to an H-level potential corresponding to the potential in DC positive bus PL1. IGBT Qx, in response to its gate-source voltage exceeding a threshold voltage, is turned on.

Here, suppose an abnormality, disappearance of the source voltage from AC power source31, occurs at time t1.

When AC voltage supply from AC power source31is stopped, energy accumulated in smoothing capacitor C10is released, causing a gradual decrease in the potential in DC positive bus PL1(point B) after time t1. The collector-emitter voltage of npn transistor Tr1is gradually decreased, accordingly.

Meanwhile, the control electrode of npn transistor Tr1is receiving input of an H-level gate signal (point C). However, npn transistor Tr1, with its collector-emitter voltage decreasing, cannot be maintained in the on-state, causing an unsteady gate potential of IGBT Qx. When the collector-emitter voltage of npn transistor Tr1reaches0, the gate potential transitions to the L level (grounding potential) to turn off IGBT Qx.

Thus, in gate drive circuit100according to the comparative example, an abnormality of the power source may cause an unsteady gate potential of IGBT Qx, leading to malfunctions of IGBT Qx. This may cause malfunctions of converter6or inverter10during the period from time t1at which the abnormality of the power source occurs to the time at which the uninterruptible power supply system shifts from the inverter power supply mode to the bypass power supply mode.

In uninterruptible power supply system1according to the present embodiment, controller18and gate drive circuit30are configured to maintain the gate potential of IGBT Qx during the period from when an abnormality of the power source for gate drive circuit30is detected to when semiconductor switch15is turned on. This allows uninterruptible power supply system1to shift to the bypass power supply mode without causing malfunctions of IGBT Qx.

FIG. 6is a block diagram showing a configuration of a portion of controller18shown inFIG. 3related to control of IGBT Qx.

With reference toFIG. 6, controller18includes a control instruction generation circuit40, an abnormality detection circuit42, a switching instruction generation circuit44, and an AND circuit46.

Control instruction generation circuit40generates a control instruction for controlling the operation of uninterruptible power supply system1. This control instruction includes a gate signal for controlling the on and off of each IGBT Qx included in converter6and inverter10, a synchronization signal, a switching instruction, an output switch ON instruction, and a power source stop instruction.

The gate signal includes gate signals Au, Bu, Av, By, Aw, Bw and gate signals Xu, Yu, Xv, Yv, Xw, Yw shown inFIG. 2. Each gate signal, which is a train of pulse signals, is a PWM signal.

The synchronization signal is a signal indicating whether or not the AC voltage generated by inverter10is synchronized with the AC voltage supplied from bypass AC power source22. When the output voltage of inverter10is synchronized with the voltage of bypass AC power source22, the synchronization signal is at the H level. When the output voltage of inverter10is not synchronized with the voltage of bypass AC power source22, the synchronization signal is at the L level.

The switching instruction is a control instruction for switching the operation mode of uninterruptible power supply system1between the inverter power supply mode and the bypass power supply mode. The switching instruction is generated based on an operation on operation unit17(FIG. 1). When the user operates operation unit17to select the inverter power supply mode, an L-level switching instruction is generated; whereas when the user operates operation unit17to select the bypass power supply mode, an H-level switching instruction is generated.

The output switch ON instruction is a control instruction for controlling the on and off of output switch14. An H-level output switch ON instruction turns on output switch14, whereas an L-level output switch ON instruction turns off output switch14. When the user operates operation unit17to select the inverter power supply mode, control instruction generation circuit40generates an L-level switching instruction and an H-level output switch ON instruction.

The power source stop instruction is a control instruction for controlling the execution and stop of power supply from power source circuit30B to gate driver30A in gate drive circuit30. The power source stop instruction is generated based on an operation on operation unit17(FIG. 1). When the user operates operation unit17to turn on the power source of uninterruptible power supply system1, an L-level power source stop instruction is generated; whereas when the user operates operation unit17to turn off the power source of uninterruptible power supply system1, an H-level power source stop instruction is generated. While the power source stop instruction is at the L level, power is supplied from power source circuit30B to gate driver30A. When the power source stop instruction transitions to the H level, power supply from power source circuit30B to gate driver30A is stopped.

Abnormality detection circuit42is configured to detect an abnormality of AC power source31in gate drive circuit30. Abnormality detection circuit42detects the AC voltage supplied from AC power source31, and uses the detection value to determine whether AC power source31is normal or abnormal. When determining that AC power source31is normal, abnormality detection circuit42generates an L-level abnormality detection signal; whereas when determining that AC power source31is abnormal, abnormality detection circuit42generates an H-level abnormality detection signal.

Further, abnormality detection circuit42outputs an H-level power source stop instruction to gate drive circuit30upon receiving an H-level power source stop instruction from control instruction generation circuit40or upon detecting an abnormality of AC power source31. Gate drive circuit30, upon receiving the H-level power source stop instruction, stops power supply from power source circuit30B to gate driver30A.

Switching instruction generation circuit44receives the synchronization signal, the switching instruction, and the output switch ON instruction from control instruction generation circuit40, and receives the abnormality detection signal from abnormality detection circuit42. Based on these input signals, switching instruction generation circuit44controls the on and off of output switch14and semiconductor switch15, and controls the on and off of each IGBT Qx included in converter6and inverter10.

Specifically, switching instruction generation circuit44generates a semiconductor switch ON instruction, an output switch ON instruction, and a gate OFF instruction, based on the synchronization signal, the switching instruction, the output switch ON instruction, and the abnormality detection signal. The gate OFF instruction is a control instruction for forcibly turning off IGBT Qx. To turn off IGBT Qx, switching instruction generation circuit44shifts the gate OFF instruction to the active H level.

AND circuit46receives the gate OFF instruction and the gate signal, and performs a logical operation to calculate the AND of them. AND circuit26provides the logical operation result to gate drive circuit30(gate driver30A) as a gate signal.

AND circuit46has a first input terminal that receives input of the gate signal, and a second input terminal that receives input of an inverted signal of the gate OFF instruction. When the gate OFF instruction is at the L level, a gate signal corresponding to the gate signal generated by control instruction generation circuit40is input from AND circuit46to gate drive circuit30. When the gate OFF instruction is at the H level, an L-level gate signal is input to gate drive circuit30regardless of the gate signal generated by control instruction generation circuit40. In other words, when the gate OFF instruction transitions to the active H level, the gate signal is forcibly driven to the L level, thereby forcibly turning off IGBT Qx.

With reference toFIG. 7, abnormality detection circuit42includes a rectifier circuit50, a filter51, comparators52,53, and OR circuits54,55.

Rectifier circuit50performs full-wave rectification of the AC voltage from AC power source31, and outputs the rectified AC voltage to filter51. Filter51filters out a high-frequency component from the voltage rectified by rectifier circuit50. The output voltage of filter51is maintained at a DC voltage corresponding to the amplitude of the AC voltage from AC power source31. Rectifier circuit50and filter51form the “voltage detector” for detecting the amplitude of the supply voltage from AC power source31.

Comparator52compares the amplitude of the supply voltage from AC power source31with a first reference value VL, and outputs a signal indicating the comparison result. First reference value VL is set to the amplitude of the supply voltage of when AC power source31is excessively low (including when the power source has disappeared). When the amplitude of the supply voltage is higher than first reference value VL, the output signal from comparator52is at the L level. When the amplitude of the supply voltage is not higher than first reference value VL, the output signal from comparator52is at the H level.

Comparator53compares the amplitude of the supply voltage with a second reference value VH, and outputs a signal indicating the comparison result. Second reference value VH is set to the amplitude of the supply voltage of when AC power source31is excessively high. When the amplitude of the supply voltage is higher than second reference value VH, the output signal from comparator53is at the H level. When the amplitude of the supply voltage is not higher than second reference value VH, the output signal from comparator53is at the L level.

OR circuit54receives the output signal from comparator52and the output signal from comparator53, and performs a logical operation to calculate the OR of them. The logical operation result from OR circuit54is the H level when any one of the output signal from comparator52and the output signal from comparator53is at the H level, i.e., when the amplitude of the supply voltage is not higher than first reference value VL or higher than second reference value VH. OR circuit54outputs the logical operation result to switching instruction generation circuit44(FIG. 6) as an abnormality detection signal. In this way, when the supply voltage from AC power source31is excessively high or low, abnormality detection circuit42determines that AC power source31of gate drive circuit30is abnormal, and outputs an H-level abnormality detection signal to switching instruction generation circuit44.

When the amplitude of the supply voltage from AC power source31is higher than first reference value VL and is not higher than second reference value VH, the logical operation result from OR circuit54is the L level. In this case, abnormality detection circuit42determines that AC power source31of gate drive circuit30is normal, and thus outputs an L-level abnormality detection signal to switching instruction generation circuit44.

OR circuit55receives the abnormality detection signal output from OR circuit54and the power source stop instruction output from control instruction generation circuit40, and performs a logical operation to calculate the OR of them. The logical operation result from OR circuit55is output to gate drive circuit30as a power source stop instruction. Gate drive circuit30receives an H-level power source stop instruction when an H-level power source stop instruction is generated by control instruction generation circuit40or an H-level abnormality detection signal is generated by abnormality detection circuit42(corresponding to when an abnormality of AC power source31is detected). Gate drive circuit30, upon receiving the H-level power source stop instruction, stops power supply from power source circuit30B to gate driver30A.

FIG. 8further illustrates a configuration of switching instruction generation circuit44shown inFIG. 6.

With reference toFIG. 8, switching instruction generation circuit44includes OR circuits60,67,69, an inversion device61, a D flip-flop62, an RS flip-flop63, AND circuits64,65,70, and on-delay circuits66,68.

OR circuit60receives the abnormality detection signal from abnormality detection circuit42(FIG. 7) and receives the switching instruction from control instruction generation circuit40(FIG. 6), and performs a logical operation to calculate the OR of them. The logical operation result from OR circuit60is the H level when the abnormality detection signal is at the H level (i.e., when an abnormality of the power source for gate drive circuit30is detected), or when the switching instruction is at the H level (i.e., when the bypass power supply mode is selected through an operation on operation unit17(FIG. 1)). The logical operation result from OR circuit60is the L level when the switching instruction is at the L level (i.e., when the inverter power supply mode is selected through an operation on operation unit17) and the abnormality detection signal is at the L level (i.e., when AC power source31of gate drive circuit30is normal).

RS flip-flop63has a set terminal S that receives input of the logical operation result from OR circuit60as a switching set instruction. RS flip-flop63has a reset terminal R that receives input of an inverted signal of the switching set instruction (switching reset instruction) through inversion device61. RS flip-flop63has an output terminal Q connected to a first input terminal of each of AND circuits64,65,70. To the first input terminal of AND circuit70, an inverted signal of the output signal from RS flip-flop63is input.

With an H-level switching set instruction, RS flip-flop63is in a set state and has an H-level output signal. With an L-level switching set instruction, RS flip-flop63is in a reset state and has an L-level output signal.

D flip-flop62has a trigger terminal T that receives input of the switching set instruction. D flip-flop62has a delay terminal D that receives input of the synchronization signal. D flip-flop62has an output terminal Q connected to a second input terminal of each of AND circuits64,65. To the second input terminal of AND circuit65, an inverted signal of the output signal from D flip-flop62is input. D flip-flop62takes in the synchronization signal in response to a rise of the switching set instruction, and outputs the synchronization signal.

AND circuit64receives the output signal from D flip-flop62and the output signal from RS flip-flop63, and performs a logical operation to calculate the AND of them. AND circuit64outputs an H-level signal when the synchronization signal is at the H level and the switching set instruction is at the H level. AND circuit64outputs an L-level signal when the synchronization signal is at the L level or the switching set instruction is at the L level. The output signal from AND circuit64is input to the first input terminal of OR circuit69, and is also input to the first input terminal of OR circuit67through on-delay circuit66. On-delay circuit66outputs an H-level signal a predetermined time period after receiving input of an H-level signal.

AND circuit65receives an inverted signal of the output signal from D flip-flop62and receives the output signal from RS flip-flop63, and performs a logical operation to calculate the AND of them. AND circuit65outputs an H-level signal when the synchronization signal is at the L level and the switching set instruction is at the H level. AND circuit65outputs an L-level signal when the synchronization signal is at the11level or switching set instruction is at the L level. The output signal from AND circuit65is input to the second input terminal of OR circuit67, and is also input to the second input terminal of OR circuit69through on-delay circuit68. On-delay circuit68outputs an H-level signal a predetermined time period after receiving input of an H-level signal.

OR circuit67receives the output signal from on-delay circuit66and the output signal from AND circuit65, and performs a logical operation to calculate the OR of them. OR circuit67outputs an H-level signal when the output signal from on-delay circuit66is at the H level or the output signal from AND circuit65is at the H level. OR circuit67outputs an L-level signal when the output signal from on-delay circuit66is at the L level and the output signal from AND circuit65is at the L level. The output signal from OR circuit67is input to the first input terminal of AND circuit46as a gate OFF instruction.

The gate OFF instruction is at the H level when the synchronization signal is at the H level and the switching set instruction is at the H level, or when the synchronization signal is at the L level and the switching set instruction is at the H level. When the synchronization signal is at the H level and the switching set instruction is at the H level, the gate OFF instruction transitions to the H level a predetermined time period after the transition of the switching set instruction to the H level.

AND circuit46receives the gate signal and an inverted signal of the gate OFF instruction, and performs a logical operation to calculate the AND of them. The output signal from AND circuit46is input to gate drive circuit30as a gate signal. When the gate OFF instruction is at the L level, the gate signal input to AND circuit46is output from AND circuit46to gate drive circuit30. When the gate OFF instruction is at the H level, an L-level gate signal is input to gate drive circuit30. In other words, when the gate OFF instruction transitions to the H level, the gate signal forcibly transitions to the L level.

OR circuit69receives the output signal from AND circuit64and the output signal from on-delay circuit68, and performs a logical operation to calculate the OR of them. OR circuit69outputs an H-level signal when the output signal from on-delay circuit68is at the H level or the output signal from AND circuit64is at the H level. OR circuit69outputs an L-level signal when the output signal from on-delay circuit68is at the L level and the output signal from AND circuit64is at the L level. The output signal from OR circuit69is input to semiconductor switch15(FIG. 1) as a semiconductor switch ON instruction.

The semiconductor switch ON instruction is at the H level when the synchronization signal is at the H level and the switching set instruction is at the H level, or when the synchronization signal is at the L level and the switching set instruction is at the H level. When the synchronization signal is at the L level and the switching set instruction is at the H level, the semiconductor switch ON instruction transitions to the H level a predetermined time period after the transition of the switching set instruction to the H level.

In summary, when the synchronization signal is at the H level, a transition of the switching set instruction to the H level causes a transition of the gate OFF instruction to the H level a predetermined time period after a transition of the semiconductor switch ON instruction to the H level. That is, when the output voltage of inverter10is synchronized with the voltage of bypass AC power source22, the gate signal transitions to the L level a predetermined time period after a transition of the semiconductor switch ON instruction to the H level.

When the synchronization signal is at the L level, a transition of the switching set instruction to the L level causes the semiconductor switch ON instruction to be turned on a predetermined time period after a transition of the gate OFF instruction to the H level. That is, when the output voltage of inverter10is not synchronized with the voltage of bypass AC power source22, the semiconductor switch ON instruction is turned on a predetermined time period after a transition of the gate signal to the L level.

AND circuit70receives an inverted signal of the output signal from RS flip-flop63, receives the output switch ON instruction, and performs a logical operation to calculate the AND of them. The output signal from AND circuit70is input to output switch14(FIG. 1) as an output switch ON instruction.

The output switch ON instruction is at the H level when the switching set instruction is at the L level and the output switch ON instruction is at the H level. When the switching set instruction transitions to the H level, the output switch ON instruction transitions to the L level.

With reference toFIG. 9, the operation of uninterruptible power supply system1according to the present embodiment will now be described. In the following description, in gate drive circuit30shown inFIG. 7, one end of the primary winding of transformer32is denoted by “point A”, the connection point between DC positive bus PL1and one end of smoothing capacitor C1is denoted by “point B”, the control electrode of npn transistor Tr1in gate driver30A is denoted by “point C”, and the gate electrode of IGBT Qx is denoted by “point D”. In abnormality detection circuit42shown inFIG. 7, the output terminal of filter51is denoted by “point E”, and the output terminal of OR circuit54is denoted by “point F”. In switching instruction generation circuit44shown inFIG. 8, the synchronization signal is denoted by “point G”, the output terminal of OR circuit69is denoted by “point H”, the output terminal of OR circuit67is denoted by “point I”, and the output terminal of AND circuit70is denoted by “point J”.

FIG. 9is a waveform chart schematically showing the temporal changes in potential at points A to J inFIGS. 7 and 8when an abnormality occurs in AC power source31of gate drive circuit30.

With reference toFIG. 9, the potential at point A shows the power source potential supplied from AC power source31. The potential at point B shows the potential in DC positive bus PL1. The potential at point C shows the potential of the gate signal supplied from controller18. The potential at point D shows the potential at the gate electrode of IGBT Qx. The potential at point E shows the amplitude of the voltage from AC power source31detected by a voltage detector (rectifier circuit50and filter51). The potential at point F shows the potential of the abnormality detection signal. The potential at point G shows the potential of the synchronization signal. The potential at point H shows the potential of the semiconductor switch ON instruction. The potential at point I shows the potential of the gate OFF instruction. The potential at point J shows the potential of the output switch ON instruction. In the example ofFIG. 9, the control electrode of npn transistor Tr1and pnp transistor Tr2is receiving input of an H-level gate signal from controller18.

When AC power source31is normal, the AC voltage supplied from AC power source31undergoes amplitude conversion at transformer32, then undergoes full-wave rectification at rectifier33, and is then output to DC positive bus PL1. The potential in DC positive bus PL1(point B) is smoothed by smoothing capacitor C1and maintained at a DC voltage having an amplitude proportional to the amplitude of the power source potential (point A). The detection value from the voltage detector (rectifier circuit50and filter51) (point E) has an amplitude proportional to the amplitude of the power source potential (point A).

Npn transistor Tr1, when receiving an H-level gate signal (point C) at its control electrode, is turned on. This causes the potential at the gate electrode of IGBT Qx (point D) to be driven to an H-level potential corresponding to the potential in DC positive bus PL1. IGBT Qx, in response to its gate-source voltage exceeding a threshold voltage, is turned on. The potential of the synchronization signal (point G) is maintained at the H level because the output voltage of inverter10is synchronized with the voltage of bypass AC power source22.

Here, suppose an abnormality, disappearance of the source voltage from AC power source31, occurs at time t1.

When AC voltage supply from AC power source31is stopped, energy accumulated in smoothing capacitor C1is released, causing a gradual decrease in the potential in DC positive bus PL1(point B) after time t1. The collector-emitter voltage of npn transistor Tr1is gradually decreased, accordingly.

After time t1, the detection value from the voltage detector (point E) is also gradually decreased. When the detection value drops to first reference value VL or less (time t2), abnormality detection circuit42determines that AC power source31is abnormal, and outputs an H-level abnormality detection signal (point F) to switching instruction generation circuit44(FIG. 8).

Switching instruction generation circuit44(FIG. 8), upon receiving the H-level abnormality detection signal from abnormality detection circuit42, generates an H-level switching set instruction. The H-level switching set instruction causes the potential of the output switch ON instruction (point J) to transition from the H level to the L level (time t3).

The H-level switching set instruction also causes the potential of the semiconductor switch ON instruction (point H) to transition from the L level to the H level, and causes the potential of the gate OFF instruction (point I) to transition from the L level to the H level. Note that the potential of the semiconductor switch ON instruction (point H) transitions to the H level at time t3, whereas the potential of the gate OFF instruction (point I) transitions to the H level at time t4, where time t4is later than time t3by a time lag corresponding to the delay time of on-delay circuit66.

A transition of the potential of the gate OFF instruction (point I) to the H level (time t4) causes a transition of the potential of the gate signal (point C) from the H level to the L level. Input of an L-level gate signal to the control electrode of npn transistor Tr1in gate driver30A turns off npn transistor Tr1. This causes the gate potential of IGBT Qx (point D) to transition to the L level to turn off IGBT Qx.

As shown inFIG. 9, when an abnormality of the power source for gate drive circuit30is detected (time t2), the output switch ON instruction transitions to the L level and the semiconductor switch ON instruction transitions to the H level, thereby turning off output switch14and turning on semiconductor switch15. This causes uninterruptible power supply system1to shift from the inverter power supply mode to the bypass power supply mode. The gate signal applied to the control electrode of npn transistor Tr1is maintained at the H level until time t4, which is later than time t3at which semiconductor switch15is turned on.

After the source voltage from AC power source31disappears at time t1, if the collector-emitter voltage of npn transistor Tr1can be maintained as long as the gate signal is maintained at the H level, npn transistor Tr1can be maintained in an on-state until semiconductor switch15is turned on at time t3.

In the present embodiment, power source circuit30B of gate drive circuit30includes high-capacitance smoothing capacitors C1, C2. Smoothing capacitors C1, C2have capacitance such that smoothing capacitors C1, C2can store energy for compensating for the collector-emitter voltage of npn transistor Tr1for a period from the disappearance of the source voltage from AC power source31and lasting as long as the gate signal is maintained at the H level (the period from time t1to time t4inFIG. 9). Smoothing capacitors C1, C2are electrolytic capacitors, for example. Smoothing capacitors C1, C2may be film capacitors if they can store energy for compensating for the collector-emitter voltage of npn transistor Tr1.

Such a configuration allows the gate potential of IGBT Qx (point D) to be maintained at the H level with an H-level gate signal, even after AC power source31disappears. The configuration can thus prevent IGBT Qx from malfunctioning during the period from time t1(i.e., the time at which an abnormality of the power source occurs) to time t3(i.e., the time at which semiconductor switch15is turned on). This allows uninterruptible power supply system1to shift to the bypass power supply mode without causing malfunctions of IGBT Qx.

When the output voltage of inverter10is not synchronized with the voltage of bypass AC power source22, the potential of the synchronization signal (point G) is at the L level. In this case, when switching instruction generation circuit44receives an H-level abnormality detection signal and generates an H-level switching set instruction, the potential of the gate OFF instruction (point I) transitions to the H level and then the potential of the semiconductor switch ON instruction (point H) transitions to the H level, where the point-H transition is later than the point-I transition by a time lag corresponding to the delay time of on-delay circuit68.

When the output voltage of inverter10is not synchronized with the voltage of bypass AC power source22, e.g., when these voltages are shifted in phase by 180°, an overvoltage may occur in response to output switch14being turned off and semiconductor switch15being turned on, which may damage load24. To address this, semiconductor switch15is turned on after a delay time that is preset for on-delay circuit68, as shown inFIG. 9. This can prevent or reduce an overvoltage on load24, although involving some instantaneous interruption. Even in this case, the gate potential of IGBT Qx can be maintained at the H level during the period from when an abnormality of the power source occurs to when output switch14is turned off, thus preventing malfunctions of IGBT Qx until semiconductor switch15is turned on.

As described above, the uninterruptible power supply system according to the present embodiment can maintain the gate potential of the switching element during the period from when an abnormality of the power source for gate drive circuit30is detected to when semiconductor switch15is turned on in the inverter power supply mode. This allows the uninterruptible power supply system to shift to the bypass power supply mode without causing malfunctions of the switching element.

With reference toFIGS. 10 and 11, a variation of uninterruptible power supply system1according to the present embodiment will now be described.

FIG. 10is a block diagram showing a first variation of abnormality detection circuit42shown inFIG. 6.

With reference toFIG. 10, abnormality detection circuit42according to the first variation is different from abnormality detection circuit42inFIG. 7in that comparators52,53and OR circuit54are replaced with a shunt resistor R2and a comparator56.

Shunt resistor R2is electrically connected between AC power source31and the primary winding of transformer32in power source circuit30B. Shunt resistor R2produces a voltage corresponding to the current flowing between AC power source31and the primary winding of transformer32. A high current through shunt resistor R2causes a high voltage between the terminals of shunt resistor R2. The voltage produced between the terminals of shunt resistor R2is input to rectifier circuit50.

Rectifier circuit50performs full-wave rectification of the voltage across shunt resistor R2, and outputs the rectified voltage to filter51. Filter51filters out a high-frequency component from the voltage rectified by rectifier circuit50. The output voltage of filter51is maintained at a DC voltage corresponding to the amplitude of the voltage across shunt resistor R2. Shunt resistor R2, rectifier circuit50, and filter51form the “current detector” for detecting the current supplied from AC power source31.

Comparator56compares the output voltage of filter51with a reference value Vth, and outputs a signal indicating the comparison result. Reference value Vth is set to the amplitude of the voltage that is produced across shunt resistor R2when the supply current from AC power source31is an overcurrent. When the output voltage of filter51is higher than reference value Vth, the output signal from comparator56is at the H level. When the output voltage of filter51is not higher than reference value Vth, the output signal from comparator56is at the L level. The output signal from comparator56is provided to switching instruction generation circuit44(FIG. 8) as an abnormality detection signal.

In this way, when the supply current from AC power source31is an overcurrent, abnormality detection circuit42determines that AC power source31of gate drive circuit30is abnormal, and outputs an H-level abnormality detection signal to switching instruction generation circuit44. The H-level abnormality detection signal causes switching instruction generation circuit44to generate an H-level gate OFF instruction, an H-level semiconductor switch ON instruction, and an L-level output switch ON instruction, as described with reference toFIG. 8.

When the supply current from AC power source31is normal, abnormality detection circuit42determines that AC power source31of gate drive circuit30is normal, and thus outputs an L-level abnormality detection signal to switching instruction generation circuit44.

OR circuit55receives the abnormality detection signal output from comparator56and the power source stop instruction output from control instruction generation circuit40(FIG. 6), and performs a logical operation to calculate the OR of them. The logical operation result from OR circuit55is output to gate drive circuit30as a power source stop instruction. Gate drive circuit30receives an H-level power source stop instruction when an H-level power source stop instruction is generated by control instruction generation circuit40or an H-level abnormality detection signal is generated by abnormality detection circuit42(corresponding to when an abnormality of AC power source31is detected). Gate drive circuit30, upon receiving the H-level power source stop instruction, stops power supply from power source circuit30B to gate driver30A.

FIG. 11is a block diagram showing a second variation of abnormality detection circuit42shown inFIG. 6.

With reference toFIG. 11, abnormality detection circuit42according to the second variation is shared by a plurality of gate drive circuits30. Abnormality detection circuit42according to the second variation has the same configuration as abnormality detection circuit42inFIG. 6.

In this variation, AC power source31is shared by a plurality of gate drive circuits30. Abnormality detection circuit42, which detects an abnormality of AC power source31, can also be shared by a plurality of gate drive circuits30. Such a configuration requires only one AC power source31and only one abnormality detection circuit42for a plurality of IGBTs included in uninterruptible power supply system1, contributing to reduction in size and cost of uninterruptible power supply system1.

The embodiments disclosed herein should be considered illustrative in all respects, not limitative. The present invention is defined not by the above description but by the terms of the claims, and is intended to include any modification in the meaning and scope equivalent to the terms of the claims.

REFERENCE SIGNS LIST