Computationally efficient nano-scale conductor resistance model

Disclosed is technology for evaluating the performance of various conducting structures in an integrated circuit. A three-dimensional circuit representation of a circuit design is provided. The three-dimensional circuit representation includes a plurality of conducting structures including a first conducting structure which has a length L. A plurality of longitudinally adjacent volume elements is identified in the conducting structure. A width Wn and a height Hn are estimated for each volume element n in the conducting structure. Furthermore, the local resistivity ρn for each volume element n is estimated based on a function that is dependent upon the length L of the conducting structure and the width Wn and height Hn of the volume element n. The resistance of a conducting structure is estimated in dependence upon the resistivity ρn for each of the volume elements n in the plurality of volume elements in the conducting structure.

FIELD OF THE INVENTION

This invention relates to the modeling of integrated circuit devices in computer-aided design (CAD) and electronic design automation (EDA) systems, and more specifically to modeling and simulating conductors in an integrated circuit (IC).

BACKGROUND

An integrated circuit (IC) is a set of electronic circuits that integrates a large number of semiconducting transistors into a small chip. Among the most advanced integrated circuits are microprocessors, memory chips, programmable logic sensors, power management circuits, etc. Advances in IC technology have led to size reduction of transistors, enabling greater densities of devices and circuits in IC chips and enhanced performance.

Metal wires have been used for IC interconnects since the invention of IC in early 70's. For the first several decades, the wires were manufactured with aluminum, but since the late 90's copper wires have been replacing aluminum for most of the ICs. Initially, due to the larger design rules, the wires were several microns wide. Currently, at 14 nm FinFET ICs, the copper interconnect wires on lower interconnect layers are about 30 nm wide. At the upcoming 7 nm and 5 nm technology nodes, the wire width is expected to reduce down to 15 nm, where ˜4 nm are taken by barrier layers that sheath the copper, with just 11 nm left for the copper wire. At such wire widths, copper resistivity is expected to more than double with respect to bulk copper resistivity. Resistivity is sharply increasing with the wire width scaling due to the increased electron scattering at the copper interfaces and grain boundaries, and grain size is proportional to the wire width.

The increase in wire resistance leads to increased delay of signal propagation through the wire from one circuit block to the next. To mitigate it, circuit designers are using so-called via pillars which is a structure that contains several vias propagating a connection from transistors that are below metal 0 to the high metal layers, say metal 5 or metal 6. The wires at high metal layers are wider and therefore provide lower resistance and lower signal delay. However, wider wires mean that there are fewer such wires available to connect circuit elements to each other. Besides, the via pillars take a considerable area and therefore increase the cost of IC manufacturing. An accurate model to quantify different interconnect routing options is necessary to optimize the performance of each particular IC to achieve its spec requirements.

A simulation model has been developed for modeling resistance of an interconnect wire using a 3-D coordinate system as described in U.S. Non-Provisional application Ser. No. 15/823,252 filed on Nov. 27, 2017, the entire contents of which are hereby incorporated by reference herein. Roughly described, for each of a plurality of volume elements in the specified structure, the simulation model specifies a location and one a first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as a function of resistivity of volume elements within a neighborhood of the volume element and a specified transition region length λ. The model prefers accuracy over computational inefficiency as it assumes local metal resistivity inside the wire to be an exponential function of the distance from wire surface, with a characteristic length of about 3 nanometers. To be accurate with such a sharply varying function, very fine mesh spacing may be needed, which results in a large overall number of mesh points and a long computing time.

It is therefore desirable to provide an efficient simulation tool that can calculate the resistance of IC interconnects on a coarse mesh.

SUMMARY

Roughly described, a system and a method are provided that can be used to evaluate the resistance of various conducting structures of arbitrary shapes in an integrated circuit. Locations for a plurality of conducting structures in a three-dimensional circuit representation are provided to the system. The plurality of conducting structures includes a first conducting structure. The first conducting structure has a length L in a longitudinal dimension. Its width and height in two orthogonal dimensions orthogonal to the longitudinal dimension varies along the longitudinal dimension. A plurality of longitudinally adjacent volume elements are identified in the first conducting structure, and a width Wnand a height Hnare estimated for each volume element n in the plurality of volume elements. A resistivity ρnis estimated for each of the volume elements n in the plurality of volume elements in the first conducting structure. The resistivity ρnof a volume element n is a function of the length L of the first conducting structure, and the width Wnand height Hnof the volume element n. The resistance of the first conducting structure is estimated in dependence upon the resistivity ρnfor each of the volume elements n in the plurality of volume elements of the first conducting structure.

In some embodiments, the resistivity ρnfor each volume element n in the plurality of volume elements comprises estimating a single resistivity ρnfor the entire volume element n. In some embodiments, the first conducting structure comprises a core material and the resistivity ρnof the volume element n in the first conducting structure is further dependent on material dependent parameters β and α, where the material dependent parameters β and α are dependent upon the core material. In some embodiments, the core material of the first conducting structure is sheathed by a second material of the first conducting structure, and the material dependent parameters β and α are further dependent upon the second material. In some embodiments, the material dependent parameters β and α are further dependent upon the fabrication process of the first conducting structure.

In some embodiments, the resistance of the first conducting structure is estimated by calculating the local electric potential μnfor each volume element n in the plurality of volume elements in dependence upon the resistivity ρnof the volume element n by Laplace's equation, estimating current I through a first cross-section SAin dependence upon the resistivity ρmand the local electric potential μmof each volume element m in a set of volume elements bounded by the first cross-section SA, and estimating the resistance of the first conducting structure in dependence upon the current I and a difference between the voltage applied across the first conducting structure in the longitudinal dimension.

The method may be utilized to develop and optimize semiconductor processing technologies and devices. The method may be applied to various applications for nano-scale interconnects such as CMOS, power, memory, image sensors, solar cells, and analog/RF devices. In addition, the method may be utilized for interconnect modeling and extraction, providing critical parasitic information for optimizing chip performance.

The simulation may facilitate (1) the analysis of complex on-chip, nano-scale interconnect structures and the influence of process variation, the creation of a parasitic database for both foundries and designers to study the effect of design rule change, (3) the generation of accurate capacitance rules for Parasitic RC Extraction (PEX) tools, (4) creating and analyzing arbitrary and complex 3D shapes using standard CAD operations or process emulation steps, and (5) visualization of output characteristics such as the potential distribution inside complex 3D shapes.

One or more embodiments of the invention or elements thereof can be implemented in the form of a computer product including a non-transitory computer readable storage medium with computer usable program code for performing the method steps indicated. Furthermore, one or more embodiments of the invention or elements thereof can be implemented in the form of an apparatus including a memory and at least one processor that is coupled to the memory and operative to perform exemplary method steps. Yet further, in another aspect, one or more embodiments of the invention or elements thereof can be implemented in the form of means for carrying out one or more of the method steps described herein; the means can include (i) hardware module(s), (ii) software module(s) executing on one or more hardware processors, or (iii) a combination of hardware and software modules; any of (i)-(iii) implement the specific techniques set forth herein, and the software modules are stored in a computer readable storage medium (or multiple such media).

DETAILED DESCRIPTION

Aspects of the invention can be used to support an integrated circuit design flow.FIG. 1shows a simplified representation of an illustrative digital integrated circuit design flow. At a high level, the process starts with the product idea (step100) and is realized in an EDA (Electronic Design Automation) software design process (step110). When the design is finalized, it can be taped-out (step127). At some point after tape out, the fabrication process (step150) and packaging and assembly processes (step160) occur resulting, ultimately, in finished integrated circuit chips (result170).

The EDA software design process (step110) is itself composed of a number of steps112-130, shown in linear fashion for simplicity. In an actual integrated circuit design process, the particular design might have to go back through steps until certain tests are passed. Similarly, in any actual design process, these steps may occur in different orders and combinations. This description is therefore provided by way of context and general explanation rather than as a specific, or recommended, design flow for a particular integrated circuit.

A brief description of the component steps of the EDA software design process (step110) will now be provided.

System design (step112): The designers describe the functionality that they want to implement, they can perform what-if planning to refine functionality, check costs, etc. Hardware-software architecture partitioning can occur at this stage. Example EDA software products from Synopsys, Inc. that can be used at this step include Model Architect, System Studio, and DesignWare® products.

Logic design and functional verification (step114): At this stage, the VHDL or Verilog code for modules in the system is written, and the design is checked for functional accuracy. More specifically, the design is checked to ensure that it produces correct outputs in response to particular input stimuli. Example EDA software products from Synopsys, Inc. that can be used at this step include VCS, VERA, DesignWare®, Magellan, Formality, ESP and LEDA products.

Synthesis and design for test (step116): Here, the VHDL/Verilog is translated to a netlist. The netlist can be optimized for the target technology. Additionally, the design and implementation of tests to permit checking of the finished chip occurs. Example EDA software products from Synopsys, Inc. that can be used at this step include Design Compiler®, Physical Compiler, DFT Compiler, Power Compiler, FPGA Compiler, TetraMAX, and DesignWare® products.

Netlist verification (step118): At this step, the netlist is checked for compliance with timing constraints and for correspondence with the VHDL/Verilog source code. Example EDA software products from Synopsys, Inc. that can be used at this step include Formality, PrimeTime, and VCS products.

Design planning (step120): Here, an overall floor plan for the chip is constructed and analyzed for timing and top-level routing. Example EDA software products from Synopsys, Inc. that can be used at this step include Astro and Custom Designer products.

Physical implementation (step122): The placement (positioning of circuit elements) and routing (connection of the same) occurs at this step, as can selection of library cells to perform specified logic functions. Example EDA software products from Synopsys, Inc. that can be used at this step include the Astro, IC Compiler, and Custom Designer products.

Analysis and extraction (step124): At this step, the circuit function is verified at a transistor level, this, in turn, permits what-if refinement. Example EDA software products from Synopsys, Inc. that can be used at this step include AstroRail, PrimeRail, PrimeTime, and Star-RCXT products.

Physical verification (step126): At this step, various checking functions are performed to ensure correctness for manufacturing, electrical issues, lithographic issues, and circuitry. Example EDA software products from Synopsys, Inc. that can be used at this step include the Hercules product.

Tape-out (step127): This step provides the “tape out” data to be used (after lithographic enhancements are applied if appropriate) for production of masks for lithographic use to produce finished chips. Example EDA software products from Synopsys, Inc. that can be used at this step include the IC Compiler and Custom Designer families of products.

Resolution enhancement (step128): This step involves geometric manipulations of the layout to improve manufacturability of the design. Example EDA software products from Synopsys, Inc. that can be used at this step include Proteus, ProteusAF, and PSMGen products.

Mask data preparation (step130): This step provides mask-making-ready “tape-out” data for production of masks for lithographic use to produce finished chips. Example EDA software products from Synopsys, Inc. that can be used at this step include the CATS(R) family of products. The method for actually making the masks can use any mask making technique, either known today or developed in the future. As an example, masks can be printed using techniques set forth in U.S. Pat. Nos. 6,096,458; 6,057,063; 5,246,800; 5,472,814; and 5,702,847, all incorporated by referenced herein for their teachings of mask printing techniques.

Once the process flow is ready, it can be used for manufacturing multiple circuit designs coming from various designers in various companies. The EDA flow112-130will be used by such designers. A combination of the process flow and the masks made from step130are used to manufacture any particular circuit.

A Design Technology Co-Optimization (DTCO) process flow provides a simulation flow that enables technology development and design teams to evaluate various transistors, interconnects and process options using a design and technology co-optimization methodology that starts in the pre-wafer research phase. Using techniques described herein, the DTCO process flow may take into account parasitic interconnect resistance of various conductors or interconnects in an IC. The DTCO process flow can be used to evaluate the performance, power, area, and cost of a new or significantly modified IC fabrication technology, including interconnect fabrication technology. Achieving transistor performance and power targets of new IC technology requires consideration of new material options for interconnects, and sometimes also new interconnect mapping in the IC. Parasitic resistances of interconnects are taken into account during the performance evaluation of the new technology.

FIG. 2illustrates a flowchart detail of a conducting structure simulation system200according to aspects of the invention. The conducting structure simulation system200starts with a 3-D circuit representation in database202. As used herein, no distinction is intended between whether a database is disposed “on” or “in” a computer readable medium. Additionally, as used herein, the term “database” does not necessarily imply any unity of structure. For example, two or more separate databases, when considered together, still constitute a “database” as that term is used herein. Thus inFIG. 2, the databases202can be a single combination database, or a combination of two or more separate databases. The databases202can be stored on a hard drive, a storage device or in a memory location or in one or more non-transitory computer readable media.

The 3-D circuit representation202represents a circuit design. The 3-D circuit representation202indicates the surfaces and interfaces among different components and materials in the circuit design, and takes account of line edge variation and corner rounding from photolithographic patterning and etching. The circuit design may include any combination of electronic devices, pins and interconnects. Electronic devices are components for controlling the flow of electrical currents for the purpose of information processing, information storage, and system control. Examples of electronic devices include transistors, diodes, capacitors, and tunnel junctions. Electronic devices are connected to the circuit through their terminals, e.g., the gate, source, and drain of a transistor. Pins in the circuit design pass signals from and to other circuit designs and power supply lines. Transistors and pins in a circuit design are connected through metallic conductors referred to herein as interconnects, where the transistor terminals and pins act as the endpoints of interconnects.

Interconnects in an IC can span several layers, each layer separated from the previous layer by a dielectric. Where interconnections are required from one layer to another, an opening is formed through the intervening dielectric layer and filled with a conductive material. There are many variations on this structure. The interconnections between layers sometimes are referred to as ‘vias’ if they interconnect two metal interconnect layers. The interconnections between layers sometimes are referred to as ‘contacts’ if they connect the first metal interconnect layer to the silicon or gate layers in transistors. The first layer of metal is referred to herein as “metal 0”, or M0 for short. For simplicity of discussion, no distinction is made herein between ‘contacts’ and ‘vias,’ and the two terms are used interchangeably herein. During fabrication, the M0 layer is formed over the underlying dielectric and then patterned to form individual conductors. The next dielectric layer is then formed above M0, vias are opened as required in this layer, and then a Metal 1 (M1) layer is formed and patterned. This process continues on up through M3, M4, and so on to the highest metal layer.

The 3-D circuit representation202includes at least one conducting structure. As used herein, “conducting structure” is a broader term than “interconnect.” Not all “conducting structures” are interconnects because a design might include a conducting structure which does not interconnect one terminal or pin to another. A conducting structure comprises a core material. The core material is the innermost material of the conducting structure. In some embodiments, the core material can be the entire conducting structure. In some embodiments, the core material can be sheathed by a second material. If the second material is a conductor, it is considered herein to be a part of the same “conducting structure” or interconnect as the core material.

FIG. 3illustrates a cross-section of an example 3-D circuit representation202. The various features illustrated inFIG. 3are symbolic and do not necessarily represent an actual device. As shown inFIG. 3, the 3-D circuit representation202includes a substrate310, a plurality of active devices312, and a top passivation layer319. The 3-D circuit representation further includes a plurality of conducting structures, such as interconnect layers314, and first and second contacts316,318. The conducting structures may be superconducting (e.g., the structure may comprise of a core material such as YBCO), or metallic (e.g., the structure may comprise of a core material such as Ni, Pt, Au, Cu, Al, Ru, W). In some embodiments, the conducting structure may be sheathed by a second dielectric layer (e.g., SiO2, TiO2). In some embodiments, the conducting structure may be semiconducting (e.g., Si, InP, GaN). In some embodiments, the conducting structures can be nanowires. Nanowires can be present in electronic, optoelectronic and nano-electromechanical devices, nanoscale quantum devices, field-emitters and biomolecular nanosensors. Therefore, a 3-D circuit representation of any of the devices mentioned above can be used as an input for the conducting structure simulation system200.

Referring toFIG. 2, the structure location identifier204identifies various conducting structures in the 3-D circuit representation202. For the 3-D circuit representation202inFIG. 3, at least one conducting structure is identified from the plurality of conducting structures, such as interconnect layers314, and first and second contacts316,318. In some embodiments, the structure location identifier204may identify a part of a conductor as a conducting structure. In other embodiments, the structure location identifier204may identify the entire conductor as a conducting structure. The structure location identifier204outputs the identified conducting structures to a conducting structure database208.

FIG. 4illustrates an example of a distorted conducting structure with varying local resistivity406shown along the structure surfaces. The conducting structure ofFIG. 4may be, for example, one of the conducting segments314,316,318inFIG. 3, excluding any vias. The distortion in the conducting structure causes variances in the width and height of the metal interconnect along the length of the wire. In the embodiment ofFIG. 4the width dimension is perpendicular to the page and only the height varies. Resistivity is represented in grayscale. The darkest shade represents the highest resistivity area in the wire. The lightest shade represents the lowest resistivity area in the wire. Local resistivity increases towards the narrower parts402of the wire. Metal resistivity is lowest in the wider part404of the wire.

Referring toFIG. 2, identified conducting structures in database208, such as the conducting structure400, are provided to a volume element identifier210. The volume element identifier210may also receive any parameters to be used in generating volume elements in a conducting structure. The volume element identifier210creates a grid of volume elements in the conducting structure to be modeled. A volume element data structure is populated for each volume element, which includes an indication of the position of the grid volume element in the conducting structure (in three dimensions), and values for various properties of the conducting structure at that volume element. In some embodiments, the volume elements may be cross-section volumes of the conducting structure as illustrated inFIG. 5A. It will be evident to a person skilled in the art that various modifications of the shape of the volume element may be made within the scope of the invention. In some embodiments, volume elements in a conducting structure can be of arbitrary shapes. However, the volume elements are longitudinally adjacent to each other as to form a continuous longitudinal conducting path spanning the two surfaces of the conducting structure across which the resistance is to be estimated.

The volume element identifier210outputs a grid of volume elements212. An example grid of volume elements is illustrated inFIG. 5A. Twenty-five volume elements (n=1, 2, 3 . . . 25) define the conducting structure400. Each volume element in the conducting structure400is associated with a local resistivity in the embodiment inFIG. 5A. A volume element502numbered n=1 (FIG. 5B) and a volume element506number n=25 are located at the two longitudinally opposite ends of the conducting structure400. Volume elements1and25have the lowest local resistivity. Volume element13(504inFIG. 5C) in the middle has the highest local resistivity. In some embodiments, resistivity is assumed to be uniform within a volume element. Each volume element is also associated with a width Wnand a height Hn. As shown inFIG. 5B, volume element1(n=1) has a width W1510and a height H1508, and as shown inFIG. 6C, volume element13(n=13) has a width W13516and a height H13514. Although the longitudinal dimension inFIG. 5Ais shown as being the same as the longest dimension of the conductive structure, that is not necessary in all embodiments. In another embodiment the longitudinal dimension may be chosen as the dimension that appears vertical in the drawing, and in yet another embodiment the longitudinal dimension may be chosen as a diagonal of the structure in the drawing. In each embodiment, the length L is the length of the structure in whatever dimension is defined as the longitudinal dimension, and the width and height dimensions are adjusted accordingly.

Referring toFIG. 2, the grid of volume elements212is provided to the volume element resistivity estimator214. Material dependent parameters218are also provided to the volume element resistivity estimator214. Material dependent parameters may include bulk resistivity ρbulkof the core material of the conducting structure, a fitting parameter β (Ohm nm), and a fitting parameter α (dimensionless). The material dependent parameters, such as fitting parameter β and α, may be dependent on the core material of the conducting structure and may be further dependent on the sheathing second barrier layer. The material dependent parameters β and α may also be dependent on the fabrication process of the conducting structure. The volume element resistivity estimator214is phenomenological in nature, meaning that it may not predict behavior of arbitrary new materials and involves calibration to provided data. Once the model is calibrated to a set of reference test structures, it may be applied to a variety of conducting structures with tapered sidewalls and lithography distorted shapes. A model calibrated to simple reference structures for wire sizes scaled towards the future technology volume elements may be applied to predict the physical behavior of the future interconnect conducting structures.

The volume element resistivity estimator214estimates the local resistivity ρnat each volume element n in the grid of volume elements for the conducting structure. The local resistivity ρnis calculated according to the following expression:
ρn=max((βLα+βWnα+βHnα),ρbulkEquation (1)
where L is the length of the conducting structure in the longitudinal dimension, Wnis the volume element width for volume element n, and Hnis the volume element height for volume element n. L, Wn, and Hnare greater than zero in Equation 1. ρbulkis the bulk resistivity of the core material of the conducting structure. In some embodiments, functions of other forms of function dependent on L, Wnand Hncan model the local volume element resistivity ρn. Some functions will work better than Equation (1), while some functions may not. For some functions, the fit may be better in some circumstances than others. In general, an equation of the following form can be used in place of Equation (1):
ρn=ƒ(L,Wn,Hn)  Equation (2)
where ƒ is a chosen function.

Equation (1) can be applied to available experimental data, and a curve fitting method can be used to extract parameters β and α for the specific material and fabrication process to be stored in material dependent parameter database218. Such calibration is done for the data that is available, which is often measured resistances for a set of conducting structures with various dimensions. Once the model is calibrated to a specific material and fabrication process, it should handle different sizes and different aspect ratios of conducting structures.

The volume element resistivity estimator214provides the output volume element resistivity216for each volume element in the grid of volume element212of the conducting structure208to the conducting structure resistance estimator220.

The conducting structure resistance estimator220estimates the resistance222of the conducting structure208. The total resistance introduced by the conducting structure from a point A in the conducting structure to a point B in the conducting structure can be calculated by estimating the current I flowing through the conducting structure at any cross-section of the wire between point A and point B. Let point A be the first cross-section SA520with a first voltage VAand point B be a second cross-section SB522with a second voltage VBas illustrated inFIG. 5. SAand SBare at opposite ends of the first conducting structure longitudinally. The local electric potential μnof any volume bounded by the first cross-section SAis the first voltage VAand the local electric potential μnof any volume element bounded by the second cross-section SAis the second voltage VB. Therefore, volume element1of the conducting structure400will have a local resistivity μ1of first voltage VA, and volume element25will have a local resistivity μ25of second voltage VB.

At each volume element n in the grid of volume elements between first cross-section SAand second cross-section SB, local electric potential μncan be calculated using Laplace's equation:

∇Gn·∇μn=∇(1ρn)·∇μn=0Equation⁢⁢(3)
where Gnis the conductivity of volume element n and is the inverse of the local resistivity ρn. The boundary conditions for the Laplace's equation are the electric potentials or voltages, VAand VB, applied at the volume elements in the first cross-section SA520and second cross-section SB522respectively.

The current I flowing at the cross-section SAcan be calculated by integrating local conductivities in the volume elements bounded by cross-section SA:
I=∫m in SAGm∇μmdSA=∫m in SA(1/ρm)∇μmdSAEquation (4)

The current I flowing at the cross-section SBis equal to the current flowing at the cross-section SA.

The total resistance introduced by the wire from cross-section SAin the wire to cross-section SBin the wire can be calculated from the electric potential or voltage difference between the two cross-sections (V=VA−VB) in the wire and the current I flowing at the cross-section SAof point A or cross-section SBof point B. The resistance is given by R=V/I.

The resistance222may be provided to a user by a reporting module. In one embodiment the resistance222is written to a non-transitory computer readable medium such as a disk drive, a storage device or computer memory, and in a further embodiment the resistance222can be provided to a visualization module which presents the distribution of the resistances across the conducting structures in the 3-D circuit representation202in a visual form which simplifies user interpretation of the results.

The resistance222is then used, in various embodiments, for a variety of real-world aspects of building or improving integrated circuit devices. In one embodiment, for example, the results are used to develop or improve a fabrication process flow for conductors in an IC. In another embodiment, the resistance222is used to characterize or improve interconnects, vias, contact pads and nanowires. In other embodiments, the results are used to develop HSPICE models of the integrated circuit devices, in order to enable designers to develop better circuit designs and layouts. In yet other embodiments the results are used to improve process flow to achieve the desired transistor and capacitor performance. Thus the resistance222obtained by the methods and systems described herein are used for real-world technological development or implementation of semiconductor manufacturing processes or circuit designs.

Referring toFIG. 2, the sequence of operation of the structure location identifier204, the volume element identifier210, the volume element resistivity estimator214, and the conducting structure resistance estimator220can be controlled automatically by a flow controller232. Flow controller232may be a module that executes scripts to call each of the individual processing modules in the sequence set forth inFIG. 2, and defines the data flow among them. Flow controller232may be implemented, for example, with Sentaurus Workbench, available from Synopsys, Inc.

FIG. 6illustrates the effectiveness of Equation (1) in estimating local resistivity.FIG. 6is a plot illustrating how the equation is used to extract fitting parameters β and α for a number of metals, fabrication process and conducting structure cross-section aspect ratio combinations: (i) metal A, fabrication process 1, and conducting structure cross-section aspect ratio of 1.5:1, (ii) metal B, fabrication process 2 and conducting structure cross-section aspect ratio of 1.5:1, and (iii) metal B, fabrication process 3, and conducting structure cross-section aspect ratios of 1:1, 2:1, 3:1, and 4:1. The markers indicate experimental data while the lines represent data from the model. Once the model is calibrated to a specific metal and fabrication process, the model can typically handle different conducting structure sizes and conducting structure cross-section aspect ratios with the calibrated parameters β and α. It can be seen that the equation predicts resistivities that are very close to the observed data. Equation (1) can be accurate even for absurdly coarse mesh as long as the conducting structure geometry is represented properly. For realistic geometries that include wire shape distortions due to such phenomena as optical proximity effects, etch micro-loading, and line edge roughness, the structure should have at least enough mesh points to accurately represent the geometry. And that should be enough for the model herein to provide accurate wire resistivity calculation.

FIG. 7is a simplified block diagram of a computer system710that can be used to implement any of the methods herein. Particularly it can be used to implement modules204,210,214,216,222, and/or232in various embodiments. It also includes or accesses the databases202,208,212,216,218, and/or222.

Computer system710typically includes a processor subsystem714which communicates with a number of peripheral devices via bus subsystem712. These peripheral devices may include a storage subsystem724, comprising a memory subsystem726and a file storage subsystem728, user interface input devices722, user interface output devices720, and a network interface subsystem716. The input and output devices allow user interaction with computer system710. Network interface subsystem716provides an interface to outside networks, including an interface to the communication network718, and is coupled via communication network718to corresponding interface devices in other computer systems. Communication network718may comprise many interconnected computer systems and communication links. These communication links may be wireline links, optical links, wireless links, or any other mechanisms for communication of information, but typically it is an IP-based communication network. While in one embodiment, communication network718is the Internet, in other embodiments, communication network718may be any suitable computer network.

The physical hardware component of network interfaces are sometimes referred to as network interface cards (NICs), although they need not be in the form of cards: for instance they could be in the form of integrated circuits (ICs) and connectors fitted directly onto a motherboard, or in the form of macrocells fabricated on a single integrated circuit chip with other components of the computer system.

Storage subsystem724stores the basic programming and data constructs that provide the functionality of certain embodiments of the present invention. For example, the various modules implementing the functionality of certain embodiments of the invention may be stored in storage subsystem724. These software modules are generally executed by processor subsystem714. The databases202,208,212,216,218, and/or222may reside in storage subsystem724.

Memory subsystem726typically includes a number of memories including a main random access memory (RAM)734for storage of instructions and data during program execution and a read-only memory (ROM)732in which fixed instructions are stored. File storage subsystem728provides persistent storage for program and data files, and may include a hard disk drive, a floppy disk drive along with associated removable media, a CD ROM drive, an optical drive, or removable media cartridges. The databases and modules implementing the functionality of certain embodiments of the invention may have been provided on a computer readable medium such as one or more CD-ROMs, and may be stored by file storage subsystem728. The host memory726contains, among other things, computer instructions which, when executed by the processor subsystem714, cause the computer system to operate or perform functions as described herein. As used herein, processes and software that are said to run in or on “the host” or “the computer,” execute on the processor subsystem714in response to computer instructions and data in the host memory subsystem726including any other local or remote storage for such instructions and data.

Bus subsystem712provides a mechanism for letting the various components and subsystems of computer system710communicate with each other as intended. Although bus subsystem712is shown schematically as a single bus, alternative embodiments of the bus subsystem may use multiple busses.

Computer system710itself can be of varying types including a personal computer, a portable computer, a workstation, a computer terminal, a network computer, a television, a mainframe, a server farm, or any other data processing system or user device. Due to the ever-changing nature of computers and networks, the description of computer system710depicted inFIG. 7is intended only as a specific example for purposes of illustrating the preferred embodiments of the present invention. Many other configurations of computer system710are possible having more or less components than the computer system depicted inFIG. 7.

In addition, while the present invention has been described in the context of a fully functioning data processing system, those of ordinary skill in the art will appreciate that the processes herein are capable of being distributed in the form of a computer readable medium of instructions and data and that the invention applies equally regardless of the particular type of signal bearing media actually used to carry out the distribution. As used herein, a computer readable medium is one on which information can be stored and read by a computer system. Examples include a floppy disk, a hard disk drive, a RAM, a CD, a DVD, flash memory, a USB drive, and so on. The computer readable medium may store information in coded formats that are decoded for actual use in a particular data processing system. A single computer readable medium, as the term is used herein, may also include more than one physical item, such as a plurality of CD ROMs or a plurality of segments of RAM, or a combination of several different kinds of media. As used herein, the term does not include mere time-varying signals in which the information is encoded in the way the signal varies over time.

As used herein, a given value is “responsive” to a predecessor value if the predecessor value influenced the given value. If there is an intervening processing element, step or time period, the given value can still be “responsive” to the predecessor value. If the intervening processing element or step combines more than one value, the signal output of the processing element or step is considered “responsive” to each of the value inputs. If the given value is the same as the predecessor value, this is merely a degenerate case in which the given value is still considered to be “responsive” to the predecessor value. “Dependency” of a given value upon another value is defined similarly.

As used herein, the “identification” of an item of information does not necessarily require the direct specification of that item of information. Information can be “identified” in a field by simply referring to the actual information through one or more layers of indirection, or by identifying one or more items of different information which are together sufficient to determine the actual item of information. In addition, the term “indicate” is used herein to mean the same as “identify”.

The foregoing description of preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. In particular, and without limitation, any and all variations described, suggested or incorporated by reference in the background section of this patent application are specifically incorporated by reference into the description herein of embodiments of the invention. In addition, any and all variations described, suggested or incorporated by reference herein with respect to any one embodiment are also to be considered taught with respect to all other embodiments. The embodiments described herein were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.