Stride-based translation lookaside buffer (TLB) prefetching with adaptive offset

A processing device implementing stride-based translation lookaside buffer (TLB) prefetching with adaptive offset is disclosed. A processing device of the disclosure includes a data prefetcher to generate a data prefetch address based on a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, and a TLB prefetch address computation component to generate a TLB prefetch address based on the linear address, the stride, the prefetch distance, or an adaptive offset. The processing device also includes a cross page detection component to determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and cause a TLB prefetch request to be written to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) based on the data prefetch address or the TLB prefetch address.

TECHNICAL FIELD

The embodiments of the disclosure relate generally to processing devices and, more specifically, relate to stride-based translation lookaside buffer (TLB) prefetching with adaptive offset.

BACKGROUND

Data prefetching, or early fetching of data into a cache, is a feature implemented in a processor to augment a probability of having requested data in a timely manner and thereby maintain a high processing efficiency. When the data is available at a first cache level, a number of cycles where the processor stalls may be reduced. For example, a processor may stall when waiting for data to come back from more distant (with respect to the processor) cache levels or memory.

Currently, many data prefetchers in modern state-of-the art processors work within page boundaries. Every prefetch request that crosses a page boundary is dropped by the data prefetcher. This is because every time the processor crosses the page boundary, it should guarantee it can obtain a translation from virtual to physical addresses. The translation lookaside buffer (TLB) may not always have the address translation and the data prefetcher cannot access the TLB to obtain the address translation. As a result, a data prefetcher may be very aggressive in making data requests in advance of next addresses, but if it crosses a page boundary, it cannot generate that request because it does not have the physical translation. As the accuracy of data prefetchers increases, this inability to move beyond page boundaries can result in processor latency and performance setbacks.

DETAILED DESCRIPTION

Embodiments of the disclosure provide stride-based translation lookaside buffer (TLB) prefetching with adaptive offset. In one embodiment, a TLB prefetch component generates TLB prefetches ahead of data prefetches to increase a TLB hit rate and allow data prefetchers to increase their prefetch distance and, therefore, reduce the number of cache misses. The TLB prefetch component of embodiments of the invention adapts to data prefetch conditions as they occur, and identifies situations where the TLB prefetcher arrives too late and delays the data prefetcher. In this case, the TLB prefetch component adjusts its aggressiveness to prevent the same situation in the future.

Previously, data prefetchers would drop a data prefetch request if the request crossed a page boundary. Embodiments of the invention send a TLB prefetch request to the TLB ahead of pending data prefetch requests. As a result, the data prefetcher no longer has to drop data prefetch requests that cross page boundaries. An advantage of this technique over previous solutions includes reducing TLB misses, as most of the prefetched TLB translations are consumed by future instructions (due to current implementations of data prefetchers having high prediction accuracy). Another advantage of embodiments of the invention over previous solution is the reduction of data cache misses. This is because any data prefetch requests that cross a page boundary are no longer dropped, so more data cache lines are prefetched ahead of the consuming instruction; thus decreasing the cache miss rate.

Although the following embodiments may be described with reference to specific integrated circuits, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™. And may be also used in other devices, such as handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below.

Although the following embodiments are described with reference to a processor, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments of the present invention can be applied to other types of circuits or semiconductor devices that can benefit from higher pipeline throughput and improved performance. The teachings of embodiments of the present invention are applicable to any processor or machine that performs data manipulations. However, the present invention is not limited to processors or machines that perform 512 bit, 256 bit, 128 bit, 64 bit, 32 bit, or 16 bit data operations and can be applied to any processor and machine in which manipulation or management of data is performed. In addition, the following description provides examples, and the accompanying drawings show various examples for the purposes of illustration. However, these examples should not be construed in a limiting sense as they are merely intended to provide examples of embodiments of the present invention rather than to provide an exhaustive list of all possible implementations of embodiments of the present invention.

As more computer systems are used in internet, text, and multimedia applications, additional processor support has been introduced over time. In one embodiment, an instruction set may be associated with one or more computer architectures, including data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O).

In one embodiment, the instruction set architecture (ISA) may be implemented by one or more micro-architectures, which includes processor logic and circuits used to implement one or more instruction sets. Accordingly, processors with different micro-architectures can share at least a portion of a common instruction set. For example, Intel® Pentium 4 processors, Intel® Core™ processors, and processors from Advanced Micro Devices, Inc. of Sunnyvale Calif. implement nearly identical versions of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. Similarly, processors designed by other processor development companies, such as ARM Holdings, Ltd., MIPS, or their licensees or adopters, may share at least a portion a common instruction set, but may include different processor designs. For example, the same register architecture of the ISA may be implemented in different ways in different micro-architectures using new or well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a Register Alias Table (RAT), a Reorder Buffer (ROB) and a retirement register file. In one embodiment, registers may include one or more registers, register architectures, register files, or other register sets that may or may not be addressable by a software programmer.

In one embodiment, an instruction may include one or more instruction formats. In one embodiment, an instruction format may indicate various fields (number of bits, location of bits, etc.) to specify, among other things, the operation to be performed and the operand(s) on which that operation is to be performed. Some instruction formats may be further broken defined by instruction templates (or sub formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields and/or defined to have a given field interpreted differently. In one embodiment, an instruction is expressed using an instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and specifies or indicates the operation and the operands upon which the operation will operate.

FIG. 1Ais a block diagram illustrating a micro-architecture for a processor100that implements stride-based TLB prefetching with adaptive offset in which one embodiment of the disclosure may be used. Specifically, processor100depicts an in-order architecture core and a register renaming logic, out-of-order issue/execution logic to be included in a processor according to at least one embodiment of the invention.

Processor100includes a front end unit130coupled to an execution engine unit150, and both are coupled to a memory unit170. The processor100may include a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, processor100may include a special-purpose core, such as, for example, a network or communication core, compression engine, graphics core, or the like. In one embodiment, processor100may be a multi-core processor or may part of a multi-processor system, such as system600described further below with respect toFIG. 1B.

The front end unit130includes a branch prediction unit132coupled to an instruction cache unit134, which is coupled to an instruction translation lookaside buffer (TLB)136, which is coupled to an instruction fetch unit138, which is coupled to a decode unit140. The decode unit140(also known as a decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decoder may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. The instruction cache unit134is further coupled to the memory unit170. The decode unit140is coupled to a rename/allocator unit152in the execution engine unit150.

The execution engine unit150includes the rename/allocator unit152coupled to a retirement unit154and a set of one or more scheduler unit(s)156. The scheduler unit(s)156represents any number of different schedulers, including reservations stations (RS), central instruction window, etc. The scheduler unit(s)156is coupled to the physical register file(s) unit(s)158. Each of the physical register file(s) units158represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc., status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. The physical register file(s) unit(s)158is overlapped by the retirement unit154to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s), using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.).

Generally, the architectural registers are visible from the outside of the processor or from a programmer's perspective. The registers are not limited to any known particular type of circuit. Various different types of registers are suitable as long as they are capable of storing and providing data as described herein. Examples of suitable registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. The retirement unit154and the physical register file(s) unit(s)158are coupled to the execution cluster(s)160. The execution cluster(s)160includes a set of one or more execution units162and a set of one or more memory access units164. The execution units162may perform various operations (e.g., shifts, addition, subtraction, multiplication) and operate on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).

While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)156, physical register file(s) unit(s)158, and execution cluster(s)160are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s)164). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units164is coupled to the memory unit170, which may include a data prefetcher180, a data TLB unit172, a data cache unit (DCU)174, and a level 2 (L2) cache unit176, to name a few examples. In some embodiments DCU174is also known as a first level data cache (L1 cache). The DCU174may handle multiple outstanding cache misses and continue to service incoming stores and loads. It also supports maintaining cache coherency. The data TLB unit172is a cache used to improve virtual address translation speed by mapping virtual and physical address spaces. In one exemplary embodiment, the memory access units164may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit172in the memory unit170. The L2 cache unit176may be coupled to one or more other levels of cache and eventually to a main memory.

In one embodiment, the data prefetcher180speculatively loads/prefetches data to the DCU174by automatically predicting which data a program is about to consume. Prefeteching may refer to transferring data stored in one memory location of a memory hierarchy (e.g., lower level caches or memory) to a higher-level memory location that is closer (e.g., yields lower access latency) to the processor before the data is actually demanded by the processor. More specifically, prefetching may refer to the early retrieval of data from one of the lower level caches/memory to a data cache and/or prefetch buffer before the processor issues a demand for the specific data being returned.

Data prefetching may be used beneficially to improve cache performance. The data prefetcher180may analyze memory operation information to detect patterns in the execution of memory operations. In some embodiments, detected patterns are used to predict information about subsequent memory operations in order to prefetch the data corresponding to the predicted memory operations.

In one embodiment, a TLB prefetch component185is embedded in the data prefetcher180. The TLB prefetch component185may generate TLB prefetches ahead of data prefetches to increase TLB hit rate and to allow the data prefetcher180to increase its prefetch distance without having to drop prefetch requests when crossing page boundaries. The TLB prefetch component185may be implemented in hardware, software, firmware, or any combination of the above. In some embodiments, the TLB prefetcher185adapts to the conditions of the data prefetcher180and identifies situations where a TLB prefetch arrives too late and delays the data prefetcher180. In this case, the TLB prefetcher185adjusts its aggressiveness to prevent the same situation in the future. Additional description and details of the TLB prefetcher185is provided below with respect toFIG. 2below.

The processor100may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.).

FIG. 1Bis a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline implemented by processing device100ofFIG. 1according to at least one embodiment of the invention. The solid lined boxes inFIG. 1Billustrate an in-order pipeline, while the dashed lined boxes illustrates an register renaming, out-of-order issue/execution pipeline. InFIG. 1B, a processor pipeline700includes a fetch stage702, a length decode stage704, a decode stage706, an allocation stage708, a renaming stage710, a scheduling (also known as a dispatch or issue) stage712, a register read/memory read stage714, an execute stage716, a write back/memory write stage718, an exception handling stage722, and a commit stage724.

Referring now toFIG. 1C, shown is a block diagram illustrating a system800in which an embodiment of the disclosure may be used. As shown inFIG. 1C, multiprocessor system800is a point-to-point interconnect system, and includes a first processor870and a second processor880coupled via a point-to-point interconnect850. While shown with only two processors870,880, it is to be understood that the scope of embodiments of the invention is not so limited. In other embodiments, one or more additional processors may be present in a given processor. In one embodiment, the multiprocessor system800may implement stride-based TLB prefetching with adaptive offset as described herein.

Processors870and880are shown including integrated memory controller units872and882, respectively. Processor870also includes as part of its bus controller units point-to-point (P-P) interfaces876and878; similarly, second processor880includes P-P interfaces886and888. Processors870,880may exchange information via a point-to-point (P-P) interface850using P-P interface circuits878,888. As shown inFIG. 1C, IMCs872and882couple the processors to respective memories, namely a memory832and a memory834, which may be portions of main memory locally attached to the respective processors.

Processors870,880may each exchange information with a chipset890via individual P-P interfaces852,854using point to point interface circuits876,894,886,898. Chipset890may also exchange information with a high-performance graphics circuit838via a high-performance graphics interface839.

Chipset890may be coupled to a first bus816via an interface896. In one embodiment, first bus816may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As shown inFIG. 1C, various I/O devices814may be coupled to first bus816, along with a bus bridge818which couples first bus816to a second bus820. In one embodiment, second bus820may be a low pin count (LPC) bus. Various devices may be coupled to second bus820including, for example, a keyboard and/or mouse822, communication devices827and a storage unit828such as a disk drive or other mass storage device which may include instructions/code and data830, in one embodiment. Further, an audio I/O824may be coupled to second bus820. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 1C, a system may implement a multi-drop bus or other such architecture.

FIG. 2illustrates a block diagram of the micro-architecture for a processor200that includes logic circuits to perform stride-based TLB prefetching with adaptive offset in accordance with one embodiment of the present invention. In some embodiments, an instruction in accordance with one embodiment can be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc., as well as datatypes, such as single and double precision integer and floating point datatypes. In one embodiment the in-order front end201is the part of the processor200that fetches instructions to be executed and prepares them to be used later in the processor pipeline. The front end201may include several units. In one embodiment, the instruction prefetcher226fetches instructions from memory and feeds them to an instruction decoder228which in turn decodes or interprets them. For example, in one embodiment, the decoder decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called micro op or uops) that the machine can execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that are used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, the trace cache230takes decoded uops and assembles them into program ordered sequences or traces in the uop queue234for execution. When the trace cache230encounters a complex instruction, the microcode ROM232provides the uops needed to complete the operation.

Some instructions are converted into a single micro-op, whereas others need several micro-ops to complete the full operation. In one embodiment, if more than four micro-ops are needed to complete a instruction, the decoder228accesses the microcode ROM232to do the instruction. For one embodiment, an instruction can be decoded into a small number of micro ops for processing at the instruction decoder228. In another embodiment, an instruction can be stored within the microcode ROM232should a number of micro-ops be needed to accomplish the operation. The trace cache230refers to a entry point programmable logic array (PLA) to determine a correct micro-instruction pointer for reading the micro-code sequences to complete one or more instructions in accordance with one embodiment from the micro-code ROM232. After the microcode ROM232finishes sequencing micro-ops for an instruction, the front end201of the machine resumes fetching micro-ops from the trace cache230.

The out-of-order execution engine203is where the instructions are prepared for execution. The out-of-order execution logic has a number of buffers to smooth out and re-order the flow of instructions to optimize performance as they go down the pipeline and get scheduled for execution. The allocator logic allocates the machine buffers and resources that each uop needs in order to execute. The register renaming logic renames logic registers onto entries in a register file. The allocator also allocates an entry for each uop in one of the two uop queues, one for memory operations and one for non-memory operations, in front of the instruction schedulers: memory scheduler, fast scheduler202, slow/general floating point scheduler204, and simple floating point scheduler206. The uop schedulers202,204,206, determine when a uop is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops need to complete their operation. The fast scheduler202of one embodiment can schedule on each half of the main clock cycle while the other schedulers can only schedule once per main processor clock cycle. The schedulers arbitrate for the dispatch ports to schedule uops for execution.

Register files208,210, sit between the schedulers202,204,206, and the execution units212,214,216,218,220,222,224in the execution block211. There is a separate register file208,210, for integer and floating point operations, respectively. Each register file208,210, of one embodiment also includes a bypass network that can bypass or forward just completed results that have not yet been written into the register file to new dependent uops. The integer register file208and the floating point register file210are also capable of communicating data with the other. For one embodiment, the integer register file208is split into two separate register files, one register file for the low order 32 bits of data and a second register file for the high order 32 bits of data. The floating point register file210of one embodiment has 128 bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

The execution block211contains the execution units212,214,216,218,220,222,224, where the instructions are actually executed. This section includes the register files208,210, that store the integer and floating point data operand values that the micro-instructions need to execute. The processor200of one embodiment is comprised of a number of execution units: address generation unit (AGU)212, AGU214, fast ALU216, fast ALU218, slow ALU220, floating point ALU222, floating point move unit224. For one embodiment, the floating point execution blocks222,224, execute floating point, MMX, SIMD, and SSE, or other operations. The floating point ALU222of one embodiment includes a 64 bit by 64 bit floating point divider to execute divide, square root, and remainder micro-ops. For embodiments of the present invention, instructions involving a floating point value may be handled with the floating point hardware. In one embodiment, the ALU operations go to the high-speed ALU execution units216,218. The fast ALUs216,218, of one embodiment can execute fast operations with an effective latency of half a clock cycle. For one embodiment, most complex integer operations go to the slow ALU220as the slow ALU220includes integer execution hardware for long latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. Memory load/store operations are executed by the AGUs212,214. For one embodiment, the integer ALUs216,218,220, are described in the context of performing integer operations on 64 bit data operands. In alternative embodiments, the ALUs216,218,220, can be implemented to support a variety of data bits including 16, 32, 128, 256, etc. Similarly, the floating point units222,224, can be implemented to support a range of operands having bits of various widths. For one embodiment, the floating point units222,224, can operate on 128 bits wide packed data operands in conjunction with SIMD and multimedia instructions.

In one embodiment, the uops schedulers202,204,206, dispatch dependent operations before the parent load has finished executing. As uops are speculatively scheduled and executed in processor200, the processor200also includes logic to handle memory misses. If a data load misses in the data cache, there can be dependent operations in flight in the pipeline that have left the scheduler with temporarily incorrect data. A replay mechanism tracks and re-executes instructions that use incorrect data. Only the dependent operations need to be replayed and the independent ones are allowed to complete. The schedulers and replay mechanism of one embodiment of a processor are also designed to catch instruction sequences for text string comparison operations.

The processor200also includes logic to implement stride-based TLB prefetching with adaptive offset according to embodiments of the invention. As uops are speculatively scheduled and executed in processor200, the processor200may utilize this logic in conjunction with a data prefetcher in order in order to speculative prefetch data needed for the operations, and perform TLB lookups for the data prefetches.

The term “registers” may refer to the on-board processor storage locations that are used as part of instructions to identify operands. In other words, registers may be those that are usable from the outside of the processor (from a programmer's perspective). However, the registers of an embodiment should not be limited in meaning to a particular type of circuit. Rather, a register of an embodiment is capable of storing and providing data, and performing the functions described herein. The registers described herein can be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In one embodiment, integer registers store thirty-two bit integer data. A register file of one embodiment also contains eight multimedia SIMD registers for packed data. For the discussions below, the registers are understood to be data registers designed to hold packed data, such as 64 bits wide MMX™ registers (also referred to as ‘mm’ registers in some instances) in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. These MMX registers, available in both integer and floating point forms, can operate with packed data elements that accompany SIMD and SSE instructions. Similarly, 128 bits wide XMM registers relating to SSE2, SSE3, SSE4, or beyond (referred to generically as “SSEx”) technology can also be used to hold such packed data operands. In one embodiment, in storing packed data and integer data, the registers do not need to differentiate between the two data types. In one embodiment, integer and floating point are either contained in the same register file or different register files. Furthermore, in one embodiment, floating point and integer data may be stored in different registers or the same registers.

FIG. 3is a block diagram illustrating a memory management system300implementing stride-based TLB prefetching with adaptive offset in which embodiments of the disclosure may be used. System300may include the TLB prefetch component185fromFIG. 1operating in conjunction with a prefetch address computation component310, a data prefetch queue350, a TLB370, and a page miss handler (PMH)380. The TLB prefetch component185may include a TLB prefetch address computation component320, a cross page detection component330, a TLB prefetch/lookup request queue360, an adaptive offset table340, and an adaptive offset threshold345. In embodiments of the invention, the components of system300may be implemented in hardware, software, firmware, or any combination of the above.

In one embodiment, a data prefetcher, such as data prefetcher180ofFIG. 1, may be trained and a resulting memory access pattern is detected. At this point, a stride may be calculated that represents a fixed memory address offset between successive memory operations. In some embodiments data prefetcher180may be a type of data prefetcher that does not compute stride. In such an implementation, embodiments of the TLB prefetch component185may utilize another data prediction value in place of the stride value. In addition, a prefetch distance is determined that represents a number of memory references ahead, in a stream of upcoming demanded memory references to be made by a program, that a prefetch request is made. The stride and prefetch distance are passed, along with a linear address representing a current memory reference of the program, to both of the data prefetch address computation component310and the TLB prefetch address computation component320. The data prefetch address computation component310calculates a data prefetch offset in parallel with the TLB prefetch address computation component calculating a TLB prefetch offset. These offsets are added to the linear address to provide the data prefetch address and the TLB prefetch address.

In one embodiment, the data prefetch address is calculated as follows: pref_addr=lin_addr+(stride*pref_dist), where pref_addr is the data prefetch offset, lin_addr is the linear address, and pref_dist is the prefetch distance.

In another embodiment, the TLB prefetch offset is calculated as follows: TLB_pref_addr=lin_addr+(stride*(pref_dist+adap_offset)), where the TLB_pref_Addr is the TLB prefetch offset, and adap_offset is the adaptive offset applied by the TLB prefetch component185. Further details of the adaptive offset are discussed later below.

After the data prefetch address and TLB prefetch address calculations are made, these addresses are passed to the cross page detection component330. In one embodiment, cross page detection logic330determines whether either of two prefetch conditions occurs. The first prefetch condition occurs when the TLB prefetch address crosses a page boundary for the first time with respect to the linear address. The second prefetch condition occurs when the data prefetch address crosses a page boundary for the first time with respect to the linear address. If either prefetch condition occurs, the cross page boundary sets a cross page flag to indicate that TLB prefetch request should be made, as discussed further below. In one embodiment, the second prefetch condition has priority over the first prefetch condition, so that if both conditions are found, the operations associated with the second prefetch condition are performed.

To determine whether the first prefetch condition (TLB prefetch address crosses page boundary) occurs, the cross page detection component330compares the linear address to the TLB prefetch address. For example, in the case of a 4 KB memory page, the cross page detection component330may determine whether linear_addr[12]!=tlb_pref_addr[12], which determines whether the 13thleast significant bit of each of the linear address and the TLB prefetch address are the same. For the 4 KB memory page, the lower 12 bits represent the offset of an address within a page. As a result, it is the 13thleast significant bit (i.e., [12]) indicates whether there is a difference in pages between two linear addresses. Other pages sizes may also be used with embodiments of the invention, and different comparison techniques may be implemented for each memory page size, as appropriate. If the comparison is not equal, then a page cross boundary occurs between the two addresses.

When the first prefetch condition is determined to occur, the cross page detection logic may set a first cross page flag that specifically indicates that the first prefetch condition is valid. This first cross page flag may cause the calculated TLB prefetch address to be passed from the TLB prefetch address computation component320to a TLB prefetch request queue364of the TLB prefetch/lookup request queue360. In one embodiment, the TLB prefetch request queue364is implemented as staging latches.

In one embodiment, a new linear page number (LPN) is generated from the TLB prefetch address for storage in the TLB prefetch request queue364along with the TLB prefetch request. In one example, the new LPN is concatenated as follows: LPN[0]=tlb_prefetch_addr[12], LPN[35:1]=linear_addr[47:13]. Various address widths may be utilized depending on the particular computer architecture implementation, and the above example is not limiting to embodiments of the invention. A TLB prefetch request is generated and written along with the new LPN into the TLB prefetch request queue364, if there is no previous entry in TLB prefetch request queue364requesting the same LPN translation already. The TLB prefetch request queue364should hold all information used for arbitration and dispatching of a prefetch request to the TLB370.

The second prefetch condition may occur when the data prefetch address crosses a page boundary due to, for example, a race condition or before a TLB prefetch for the page has resolved. If this happens, the data prefetch requests are not dropped, but are instead allocated in the data prefetch request queue350. To determine whether the second prefetch condition occurs, the cross page detection component330compares the linear address to the data prefetch address. For example, the cross page detection component330may determine whether linear_addr[12]!=data_pref_addr[12], which determines whether the 13thleast significant bit of each of the linear address and the data prefetch address are the same. If the comparison is not equal, then a page cross boundary occurs between the two addresses.

When the second prefetch condition is determined to occur, the cross page detection logic may set a second cross page flag that specifically indicates that the second prefetch condition is valid. This second cross page flag may cause the calculated data prefetch address to be passed from the data prefetch address computation component310to a TLB lookup request queue362of the TLB prefetch/lookup request queue360. In one embodiment, the TLB lookup request queue362is implemented as staging latches.

In one embodiment, a new linear page number (LPN) is generated from the data prefetch address for storage in the TLB lookup request queue362along with the TLB prefetch request. In one example, the new LPN is concatenated as follows: LPN[0]=data_prefetch_addr[12], LPN[35:1]=linear_addr[47:13]. A TLB prefetch request is generated and written along with the new LPN into the TLB lookup request queue364, if there is no previous entry in TLB lookup request queue362requesting the same LPN translation already. The TLB lookup request queue362should hold all information used for arbitration and dispatching of a prefetch request to the TLB370.

In embodiments of the invention, both of the TLB prefetch request queue364and the TLB lookup request queue362hold the same information, namely TLB prefetch requests for a linear page number. Both queues362,364may take part in the arbitration as a lowest priority dispatch agent, however the dispatch of the TLB lookup request queue362requests may have higher priority than the TLB prefetch request queue364. This is because, in the case of the second prefetch condition (data prefetch request crossing a page boundary), there are data prefetch requests allocated in the data prefetch request queue350that are waiting for the physical page number (PPN) (e.g., PPN=physical_address[38:12]). However, in some embodiments, a single TLB prefetch/lookup request queue360may be implemented, with prioritization mechanisms utilized within to differentiate between requests resulting from the first prefetch condition or the second prefetch condition.

Requests from both queues362,364(TLB prefetch and TLB lookup) access the TLB370. In the case of a TLB miss, the prefetch requests trigger a PMH380that performs a page table walk to locate the address translation. When the TLB370hits or the miss is resolved by the PMH380, the PPN is updated in data prefetch request queue350. In case of a page fault or when the PPN is not delivered on time, the data prefetch request queue may overflow.

In one embodiment, the TLB offset calculation may be adaptive to respond to runtime conditions experienced by the data prefetcher, such as the TLB prefetch component185being unable to detect a page boundary cross ahead of the data prefetch request. When this occurs, it is an indicator that the TLB offset is not large enough. To adjust to this inefficient speculation, an adaptive offset may be utilized to adjust the TLB offset based on runtime conditions experience during operation of the data prefetcher and TLB prefetch component185. Every time the second prefetch condition occurs, a counter is incremented at the adaptive offset counter table340. If the value of this counter340exceeds an adaptive offset threshold345, the adaptive offset (adap_offset) is incremented. In one embodiment, the adaptive offset is increment up to a limit, in order to avoid crossing more than one page boundary. In some embodiment, the adaptive offset threshold and limit may be configured by a system administrator and programmable in software. In one embodiment, the adaptive offset is incremented by multiples of the constant stride value, as indicated in the formula provided above.

FIG. 4is a flow diagram illustrating a method400for stride-based TLB prefetching with adaptive offset according to an embodiment of the disclosure. Method400may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as instructions run on a processing device), firmware, or a combination thereof. In one embodiment, method400is performed by TLB prefetch component185ofFIG. 1Aand/orFIG. 3.

Method400begins at block410where a linear address, stride, and prefetch distance associated with a data prefetch request are received. In one embodiment, the data prefetch request is performed by a data prefetcher of a memory unit of a processor. At block420, a TLB offset is calculated and used to generate a TLB prefetch address. In one embodiment, the TLB prefetch address is a function of the linear address, the stride, the prefetch distance, and an adaptive offset. Then, at block430, it is determined that the TLB prefetch address crosses a page boundary for the first time with respect to the linear address. In one embodiment, a TLB prefetch queue is examined to determine whether an entry requesting the LPN of the crossed page exists. If not, then it is assumed this is the first time the page boundary cross has occurred. In one embodiment, TLB prefetch address[12] is compared to linear address[12]. If they are different, then a page boundary cross occurs with the TLB prefetch address.

Subsequently, at block440, a first page cross condition flag is set as valid to indicate the occurrence of a first prefetch condition. Then, at block450, an LPN is generated using the TLB prefetch address and the linear page address. In one embodiment, the LPN is concatenated as follows: LPN[0]=tlb_prefetch_addr[12], LPN[35:1]=linear_addr[47:13]. At block460, a TLB prefetch request is generated and written along with the generated LPN into a TLB prefetch request queue. In one embodiment, the TLB prefetch request and LPN are written when there are no previous entries in the TLB prefetch request queue requesting the same LPN translation already. Lastly, at block470, the TLB prefetch request is arbitrated and dispatched to the TLB in order to obtain a translated LPN address for the data prefetch request.

FIGS. 5A and 5Bare flow diagrams illustrating another method500for stride-based TLB prefetching with adaptive offset according to another embodiment of the disclosure. Method500may be performed by processing logic that may comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (such as instructions run on a processing device), firmware, or a combination thereof. In one embodiment, method500is performed by TLB prefetch component185ofFIG. 1and/orFIG. 2.

Referring toFIG. 5A, method500begins at block505where a linear address, stride, and prefetch distance associated with a data prefetch request are received. In one embodiment, the data prefetch request is performed by a data prefetcher of a memory unit of a processor. At block510, a TLB offset is calculated and used to generate a TLB prefetch address. In one embodiment, the TLB prefetch address is a function of the linear address, the stride, the prefetch distance, and an adaptive offset.

Then, at block515, it is determined that a data prefetch address crosses a page boundary for the first time with respect to the linear address. In one embodiment, a TLB prefetch queue is examined to determine whether an entry requesting the LPN of the crossed page exists. If not, then it is assumed this is the first time the page boundary cross has occurred. In one embodiment, the data prefetch address is generated by a data prefetcher and provided to cross page boundary logic of the TLB prefetch component. For example, in the case of 4 KB memory pages, a data prefetch address[12] may be compared to linear address[12]. If they are different, then a page boundary cross occurs with the data prefetch address.

Subsequently, at block520, a second page cross condition flag is set as valid to indicate the occurrence of a second prefetch condition. Then, at block525, an LPN is generated using the data prefetch address and the linear page address. In one embodiment, the LPN is concatenated as follows: LPN[0]=data_prefetch_addr[12], LPN[35:1]=linear_addr[47:13]. At block530, a TLB prefetch request is generated and written along with the generated LPN into a TLB lookup request queue. Then, at block535, the TLB prefetch request is arbitrated and dispatched to the TLB in order to obtain a translated LPN address for the data prefetch request. In one embodiment, the TLB lookup request queue receives priority over a TLB prefetch request queue in terms of the arbitration and dispatching to the TLB.

Referring toFIG. 5B, method500proceeds to decision block540, where it is determined whether a TLB miss occurred for the TLB prefetch request. If not, method500ends. However, if a TLB miss does occur, then method500continues to block545where an adaptive offset counter is incremented. In one embodiment, the adaptive offset counter incrementing is dependent on the occurrence of the second prefetch condition. Then, at decision block550, it is determined whether the adaptive offset counter is greater than an adaptive offset threshold. In one embodiment, the adaptive offset threshold may be configured by a system administrator of a processing device having the TLB prefetch component.

If the counter is not greater than the threshold, then method500ends. On the other hand, if the counter is greater than the threshold, then method500proceeds to decision block555, where it is determined whether the adaptive offset exceeds an adaptive offset limit. In one embodiment, the adaptive offset limit is also set by the system administrator. If the adaptive offset does not exceed the limit, the method500continues to block560, where the adaptive offset is increased for purposes of further TLB offset calculations to generate the TLB prefetch address. If the adaptive offset does not exceed the adaptive offset limit, then method500ends.

The computer system600includes a processing device602, a main memory604(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or DRAM (RDRAM), etc.), a static memory606(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device618, which communicate with each other via a bus630.

Processing device602represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computer (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device602may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. In one embodiment, processing device602may include one or processing cores. The processing device602is configured to execute the processing logic626for performing the operations and steps discussed herein. In one embodiment, processing device602is the same as processing engine100described with respect toFIG. 1that implements stride-based TLB prefetching with adaptive offset as described herein with embodiments of the disclosure.

The computer system600may further include a network interface device608communicably coupled to a network620. The computer system600also may include a video display unit610(e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device612(e.g., a keyboard), a cursor control device614(e.g., a mouse), and a signal generation device616(e.g., a speaker). Furthermore, computer system600may include a graphics processing unit622, a video processing unit628, and an audio processing unit632.

The data storage device618may include a machine-accessible storage medium624on which is stored software626implementing any one or more of the methodologies of functions described herein, such as implementing a stride-based TLB prefetching with adaptive offset as described above. The software626may also reside, completely or at least partially, within the main memory604as instructions626and/or within the processing device602as processing logic626during execution thereof by the computer system600; the main memory604and the processing device602also constituting machine-accessible storage media.

The machine-readable storage medium624may also be used to store instructions626implementing a TLB prefetch component that implements stride-based TLB prefetching with adaptive offset, such as described with respect to TLB prefetch component138inFIGS. 1 and 2, and/or a software library containing methods that call the above applications. While the machine-accessible storage medium628is shown in an example embodiment to be a single medium, the term “machine-accessible storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-accessible storage medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instruction for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term “machine-accessible storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

The following examples pertain to further embodiments. Example 1 is a processing device for implementing stride-based TLB prefetching with adaptive offset comprising a data prefetcher to generate a data prefetch address based on at least one of a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, a translation lookaside buffer (TLB) prefetch address computation component communicably coupled to the data prefetcher, the TLB prefetch address computation component to generate a TLB prefetch address based on at least one of the linear address, the stride, the prefetch distance, or an adaptive offset. In Example 1, the processing device further includes a cross page detection component communicably coupled to the data prefetcher and the TLB prefetch address computation component, the cross page detection component to determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and cause a TLB prefetch request to be written to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) that is based on at least one of the data prefetch address or the TLB prefetch address.

In Example 2, the subject matter of Example 1 can optionally include wherein the TLB prefetch request in the TLB request queue is sent to a TLB for the translation of the address. In Example 3, the subject matter of any one of Examples 1-2 can optionally include wherein the TLB request queue further comprises a TLB prefetch request queue and a TLB lookup request queue.

In Example 4, the subject matter of any one of Examples 1-3 can optionally include wherein the TLB prefetch request queue to store one or more TLB prefetch requests for LPNs generated based on the TLB prefetch address. In Example 5, the subject matter of any one of Examples 1-4 can optionally include wherein the TLB lookup request queue to store one or more TLB prefetch requests for LPNs generated based on the data prefetch address.

In Example 6, the subject matter of any one of Examples 1-5 can optionally include wherein when the TLB prefetch address is determined to cross the page boundary, the cross page detection component further to set a first cross page flag to indicate occurrence of a first prefetch condition. In Example 7, the subject matter of any one of Examples 1-6 can optionally include wherein when the first cross page flag is set to indicate the occurrence of the first prefetch condition, the TLB prefetch address is concatenated with the linear page address to generate the LPN for the TLB prefetch request. In Example 8, the subject matter of any one of Examples 1-7 can optionally include wherein when the data prefetch address is determined to cross the page boundary, the cross page detection component further to set a second cross page flag to indicate occurrence of a second prefetch condition.

In Example 9, the subject matter of any one of Examples 1-8 can optionally include wherein when the second cross page flag is set to indicate the occurrence of the second prefetch condition, the data prefetch address is concatenated with the linear page address to generate the LPN for the TLB prefetch request. In Example 10, the subject matter of any one of Examples 1-9 can optionally include wherein when the second prefetch condition occurs, the cross page detection component to increment an adaptive offset counter. In Example 11, the subject matter of any one of Examples 1-10 can optionally include wherein when the adaptive offset counter exceeds an adaptive offset counter threshold and when a value of the adaptive offset is less than an adaptive offset limit, the adaptive offset is increased. All optional features of the apparatus described above may also be implemented with respect to the method or process described herein

Example 12 is a method for implementing stride-based TLB prefetching with adaptive offset comprising receiving, by a translation lookaside buffer (TLB) prefetch component of a processing device, a data prefetch address based on at least one of a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, generating a TLB prefetch address based on at least one of the linear address, the stride, the prefetch distance, or an adaptive offset, determining that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and writing a TLB prefetch request to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) that is based on at least one of the data prefetch address or the TLB prefetch address.

In Example 13, the subject matter of Examples 12 can optionally include further comprising sending the TLB prefetch request in the TLB request queue is sent to a TLB for the translation of the address. In Example 14, the subject matter of any one of Examples 12-13 can optionally include wherein the TLB request queue further comprises a TLB prefetch request queue to store one or more TLB prefetch requests for LPNs generated based on the TLB prefetch, and a TLB lookup request queue to store one or more TLB prefetch requests for LPNs generated based on the data prefetch address.

In Example 15, the subject matter of any one of Examples 12-14 can optionally include further comprising when the TLB prefetch address is determined to cross the page boundary, setting a first cross page flag to indicate occurrence of a first prefetch condition. In Example 16, the subject matter of any one of Examples 12-15 can optionally include further comprising when the first cross page flag is set to indicate the occurrence of the first prefetch condition, concatenating the TLB prefetch address with the linear page address to generate the LPN for the TLB prefetch request. In Example 17, the subject matter of any one of Examples 12-16 can optionally include further comprising when the data prefetch address is determined to cross the page boundary, setting a second cross page flag to indicate occurrence of a second prefetch condition.

In Example 18, the subject matter of any one of Examples 12-17 can optionally include further comprising when the second cross page flag is set to indicate the occurrence of the second prefetch condition, concatenating the data prefetch address with the linear page address to generate the LPN for the TLB prefetch request. In Example 19, the subject matter of any one of Examples 12-18 can optionally include further comprising when the second prefetch condition occurs, incrementing an adaptive offset counter. In Example 20, the subject matter of any one of Examples 12-19 can optionally include wherein when the adaptive offset counter exceeds an adaptive offset counter threshold and when a value of the adaptive offset is less than an adaptive offset limit, increasing the adaptive offset.

Example 21 is a system for implementing stride-based TLB prefetching with adaptive offset. In Example 21 the system includes a memory and a processing device communicably coupled to the memory, the processing device comprising a translation-lookaside buffer (TLB) prefetch component to receive a data prefetch address based on at least one of a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, generate a TLB prefetch address based on at least one of the linear address, the stride, the prefetch distance, or an adaptive offset, determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and send a TLB prefetch to a TLB of the processing device, the TLB prefetch request for translation of an address of a linear page number (LPN) that is based on at least one of the data prefetch address or the TLB prefetch address.

In Example 22, the subject matter of Example 21 can optionally include wherein the TLB request is sent from a TLB request queue that comprises a TLB prefetch request queue to store one or more TLB prefetch requests for LPNs generated based on the TLB prefetch, and a TLB lookup request queue to store one or more TLB prefetch requests for LPNs generated based on the data prefetch address. In Example 23, the subject matter of any one of Examples 21-22 can optionally include further comprising when the TLB prefetch address is determined to cross the page boundary, the processing device to set a first cross page flag to indicate occurrence of a first prefetch condition. In Example 24, the subject matter of any one of Examples 21-23 can optionally include further comprising when the first cross page flag is set to indicate the occurrence of the first prefetch condition, the processing device to concatenate the TLB prefetch address with the linear page address to generate the LPN for the TLB prefetch request.

In Example 25, the subject matter of any one of Examples 21-24 can optionally include further comprising when the data prefetch address is determined to cross the page boundary, the processing device to set a second cross page flag to indicate occurrence of a second prefetch condition. In Example 26, the subject matter of any one of Examples 21-25 can optionally include further comprising when the second cross page flag is set to indicate the occurrence of the second prefetch condition, the processing device to concatenate the data prefetch address with the linear page address to generate the LPN for the TLB prefetch request.

In Example 27, the subject matter of any one of Examples 21-26 can optionally include further comprising when the second prefetch condition occurs, the processing device to increment an adaptive offset counter. In Example 28, the subject matter of any one of Examples 21-27 can optionally include wherein when the adaptive offset counter exceeds an adaptive offset counter threshold and when a value of the adaptive offset is less than an adaptive offset limit, the processing device to increase the adaptive offset. All optional features of the system described above may also be implemented with respect to the method or process described herein.

Example 29 is non-transitory computer-readable medium for implementing stride-based TLB prefetching with adaptive offset. In Example 29, the non-transitory machine-readable medium includes data that, when accessed by a processing device, cause the processing device to perform operations comprising receiving, by a translation lookaside buffer (TLB) prefetch component of a processing device, a data prefetch address based on at least one of a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, generating a TLB prefetch address based on at least one of the linear address, the stride, the prefetch distance, or an adaptive offset, determining that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and writing a TLB prefetch request to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) that is based on at least one of the data prefetch address or the TLB prefetch address.

In Example 30, the subject matter of Example 29 can optionally include further comprising sending the TLB prefetch request in the TLB request queue is sent to a TLB for the translation of the address. In Example 31, the subject matter of any one of Examples 29-30 can optionally include wherein the TLB request queue further comprises a TLB prefetch request queue to store one or more TLB prefetch requests for LPNs generated based on the TLB prefetch, and a TLB lookup request queue to store one or more TLB prefetch requests for LPNs generated based on the data prefetch address.

In Example 32, the subject matter of any one of Examples 29-31 can optionally include further comprising when the TLB prefetch address is determined to cross the page boundary, setting a first cross page flag to indicate occurrence of a first prefetch condition. In Example 33, the subject matter of any one of Examples 29-32 can optionally include further comprising when the first cross page flag is set to indicate the occurrence of the first prefetch condition, concatenating the TLB prefetch address with the linear page address to generate the LPN for the TLB prefetch request. In Example 34, the subject matter of any one of Examples 29-33 can optionally include further comprising when the data prefetch address is determined to cross the page boundary, setting a second cross page flag to indicate occurrence of a second prefetch condition.

In Example 35, the subject matter of any one of Examples 29-34 can optionally include further comprising when the second cross page flag is set to indicate the occurrence of the second prefetch condition, concatenating the data prefetch address with the linear page address to generate the LPN for the TLB prefetch request. In Example 36, the subject matter of any one of Examples 29-35 can optionally include further comprising when the second prefetch condition occurs, incrementing an adaptive offset counter. In Example 37, the subject matter of any one of Examples 29-36 can optionally include wherein when the adaptive offset counter exceeds an adaptive offset counter threshold and when a value of the adaptive offset is less than an adaptive offset limit, increasing the adaptive offset.

Example 38 is an apparatus for implementing stride-based TLB prefetching with adaptive offset comprising means for receiving a data prefetch address based on at least one of a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, means for generating a translation lookaside buffer (TLB) prefetch address based on at least one of the linear address, the stride, the prefetch distance, or an adaptive offset, means for determining that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and means for writing a TLB prefetch request to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) that is based on at least one of the data prefetch address or the TLB prefetch address. In Example 39, the subject matter of Example 38 can optionally include the apparatus further configured to perform the method of any one of the Examples 13 to 20.

Example 40 is at least one machine readable medium comprising a plurality of instructions that in response to being executed on a computing device, cause the computing device to carry out a method according to any one of Examples 12-20. Example 41 is an apparatus for implementing stride-based TLB prefetching with adaptive offset, configured to perform the method of any one of Examples 12-20. Example 42 is an apparatus comprising means for performing the method of any one of Examples 12-20. Specifics in the Examples may be used anywhere in one or more embodiments.