Methods of forming patterns on substrates

Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the carbon-comprising material. Etching is conducted only partially into the carbon-comprising material and spaced second features are formed within the carbon-comprising material which comprise the partially etched carbon-comprising material. Spacers can be formed along sidewalls of the spaced second features. The carbon-comprising material can be etched through to the base material using the spacers as a mask. Spaced third features can be formed which comprise the anisotropically etched spacers and the carbon-comprising material.

TECHNICAL FIELD

Embodiments disclosed herein pertain to methods of forming patterns on substrates.

BACKGROUND

Integrated circuits are typically formed on a semiconductor substrate such as a silicon wafer or other semiconducting material. In general, layers of various materials which are either semiconducting, conducting or insulating are utilized to form the integrated circuits. By way of example, the various materials are doped, ion implanted, deposited, etched, grown, etc. using various processes. A continuing goal in semiconductor processing is to continue to strive to reduce the size of individual electronic components thereby enabling smaller and denser integrated circuitry.

One technique for patterning and processing semiconductor substrates is photolithography. Such includes deposition of a patternable masking layer commonly known as photoresist. Such materials can be processed to modify their solubility in certain solvents, and are thereby readily usable to form patterns on a substrate. For example, portions of a photoresist layer can be exposed to actinic energy through openings in a radiation-patterning tool, such as a mask or reticle, to change the solvent solubility of the exposed regions versus the unexposed regions compared to the solubility in the as-deposited state. Thereafter, the exposed or unexposed regions can be removed, depending on the type of photoresist, thereby leaving a masking pattern of the photoresist on the substrate. Adjacent areas of the underlying substrate next to the masked portions can be processed, for example by etching or ion implanting, to effect the desired processing of the substrate adjacent the masking material. In certain instances, multiple different layers of photoresist and/or a combination of photoresists with non-radiation sensitive masking materials are utilized.

The continual reduction in feature sizes places ever greater demands on the techniques used to form the features. For example, photolithography is commonly used to form patterned features, such as conductive lines. A concept commonly referred to as “pitch” can be used to describe the sizes of the features in conjunction with spaces immediately adjacent thereto. Pitch may be defined as the distance between an identical point in two neighboring features of a repeating pattern in a straight line cross section, thereby including the maximum width of the feature and the space to the next immediately adjacent feature. However, due to factors such as optics and light or radiation wave length, photolithography techniques tend to have a minimum pitch below which a particular photolithographic technique cannot reliably form features. Thus, minimum pitch of a photolithographic technique is an obstacle to continued feature size reduction using photolithography.

Pitch multiplication, such as pitch doubling, is one proposed method for extending the capabilities of photolithographic techniques beyond their minimum pitch. Such typically forms features narrower than minimum photolithography resolution by depositing spacer-forming layers to have a lateral thickness which is less than that of the minimum capable photolithographic feature size. The spacer-forming layers are commonly anisotropically etched to form sub-lithographic features, and then the features which were formed at the minimum photolithographic feature size are etched from the substrate. Using such technique where pitch is actually halved, such reduction in pitch is conventionally referred to as pitch “doubling”. More generally, “pitch multiplication” encompasses increase in pitch of two or more times and also of fractional values other than integers. Thus, conventionally, “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor.

Transistor gates are one general type of integrated circuit device component that may be used in many different types of integrated circuitry, for example in memory circuitry such as flash. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that may be erased and reprogrammed in blocks. Many modern personal computers have BIOS stored on a flash memory chip. Such BIOS is sometimes called flash BIOS. Flash memory is also popular in wireless electronic devices as it enables manufacturers to support new communication protocols as they become standardized, and provides the ability to remotely upgrade the devices for enhanced features.

A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. The cells are usually grouped into blocks. Each of the cells within a block may be electrically programmed by charging a floating gate. The charge may be removed from the floating gate by a block erase operation. Data is stored in a cell as charge in the floating gate.

NAND is a basic architecture of flash memory. A NAND cell unit comprises at least one select gate coupled in series to a serial combination of memory cells (with the serial combination being commonly referred to as a NAND string).

Flash memory incorporates charge storage structures into transistor gates, and incorporates control gate structures over the charge storage structures. The charge storage structures may be immediately over gate dielectric. The charge storage structures comprise material capable of storing/trapping charge and which is collectively referred to herein as floating gate material. The amount of charge stored in the charge storage structures determines a programming state. In contrast, standard field effect transistors (FETs) do not utilize charge storage structures as part of the transistors, but instead have a conductive gate directly over gate dielectric material.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments of methods of forming a pattern on a substrate are initially described with reference toFIGS. 1-11with respect to a substrate10. Such may comprise a semiconductor substrate or other substrate, and in some embodiments be used in the fabrication of integrated circuitry. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.

Substrate10comprises a base substrate or material12, a carbon-comprising material14over base material12, a hardmask material16over carbon-comprising material14, and a masking material20over hardmask material16. Base material12may be homogenous or non-homogenous, and may comprise different composition layers. Such may comprise any one or combination of semiconductive material, insulative material, and conductive material.

Carbon-comprising material14may be homogenous or non-homogenous. Examples include amorphous carbon, transparent carbon, and carbon-containing polymers. Example carbon-containing polymers include spin-on-carbons (SOCs). Carbon-comprising material14may consist essentially of any one or more of these example materials. An example thickness range for carbon-comprising material14is from about 700 Angstroms to about 2,000 Angstroms.

Hardmask material16may be homogenous or non-homogenous, and may comprise multiple different composition layers. In one embodiment, hardmask material16comprises an antireflective coating, for example a coating comprising SixOyNz. Regardless, in one embodiment, hardmask material16is inorganic. Hardmask material may also comprise a bottom antireflective coating (BARC), for example between a SixOyNz-comprising material and masking material20. An example thickness range for hardmask material16is from 200 Angstroms to 400 Angstroms. Hardmask material16is not required in all embodiments.

Masking material20may be homogenous or non-homogenous, and may comprise multiple different composition layers. One example material is photoresist.FIG. 1depicts masking material20as having been patterned to form spaced primary features18over hardmask material16. Such are depicted as being equal in size and shape relative one another and equally spaced relative to each immediately adjacent feature18, although alternate configurations are of course contemplated. In one embodiment in the fabrication of integrated circuitry, substrate10may be considered as comprising an array circuitry area22and a peripheral circuitry area24, wherein features18are at least provided within array circuitry area22. The same or other features might additionally be provided in peripheral circuitry area24. Periphery circuitry area24, by way of example only, is shown as being largely masked by material20in theFIG. 1configuration. Primary features18may or may not be fabricated above, at, or below the minimum photolithographic feature size with which the substrate will ultimately be processed where photolithographic processing is used. Further, primary features18may be treated or coated after initial formation.

Referring toFIG. 2, primary features18ofFIG. 1have been processed to laterally trim their respective widths, thereby forming spaced first features26within array circuitry area22. Masking material20in periphery area24is also shown as being laterally trimmed. Such may be conducted by an isotropic etch which removes material approximately equally from the sides and top of spaced primary features18ofFIG. 1, as is shown. Alternately, chemistries and conditions may be used which tend to etch greater material from the lateral sides of spaced primary features18than from the respective tops. Alternately, chemistries and conditions may be used which tend to etch greater material from the tops of spaced mask features18than from the lateral sides.

For example, the construction depicted byFIG. 2may be derived by plasma etching the substrate ofFIG. 1within an inductively coupled reactor. Example etching parameters which will achieve essentially isotropic etching where material of spaced mask features18is photoresist and/or other organic-comprising material are pressure from about 2 mTorr to about 50 mTorr, substrate temperature from about 0° C. to about 100° C., source power from about 150 watts to about 500 watts, and bias voltage at less than or equal to about 25 volts. An example etching gas is a combination of Cl2from about 20 sccm to about 100 sccm and O2from about 10 sccm to about 50 sccm. Where material of spaced primary features18comprises a photoresist, such will isotropically etch mask features18at a rate from about 0.2 nanometers per second to about 3 nanometers per second. While such an example etch is essentially isotropic, greater lateral etching of the spaced mask features will occur as two sides are laterally exposed as compared to only a single top surface thereof.

If even more lateral etching is desired in comparison to vertical etching, example parameter ranges in an inductively coupled reactor include pressure from about 2 mTorr to about 20 mTorr, source power from about 150 watts to about 500 watts, bias voltage at less than or equal to about 25 volts, substrate temperature of from about 0° C. to about 110° C., Cl2and/or HBr flow from about 20 sccm to about 100 sccm, O2flow from about 5 sccm to about 20 sccm, and CF4flow from about 80 sccm to about 120 sccm.

It may be desired that the stated etching provide greater removal from the top of the spaced mask features than from the sides, for example to either achieve equal elevation and width reduction or more elevation than width reduction. The example parameters for achieving greater etch rate in the vertical direction as opposed to the lateral direction includes pressure from about 2 mTorr to about 20 mTorr, temperature from about 0° C. to about 100° C., source power from about 150 watts to about 300 watts, bias voltage at greater than or equal to about 200 volts, Cl2and/or HBr flow from about 200 sccm to about 100 sccm, and O2flow from about 10 sccm to about 20 sccm.

FIGS. 1 and 2depict but one example of forming spaced first features26which will be used as an etch mask in example embodiments described below. Any other existing or yet-to-be developed techniques might be used to form spaced first features, and whether or not such are sub-lithographic. Regardless, the spaced first features may or may not be in direct physical touching contact with carbon-comprising material14.FIG. 2shows one embodiment wherein spaced first features26are spaced from carbon-comprising material14by hardmasking material16. Regardless, in one embodiment, the spaced first features and the carbon-comprising material are of different compositions.

Referring toFIG. 3, first etching has been conducted through hardmask material16using spaced first features26as a mask. In theFIG. 3example, such etching has been conducted selectively (rate 2:1 or greater) relative to carbon-comprising material14, although such is not required. For example, the act of etching through hardmask material16may also etch into carbon-comprising material14. Further and regardless, some, none, or all of masking material20might be etched during the etching of hardmask material16.FIG. 3depicts some etching having been conducted of masking material20, and wherein at least some of the thickness of masking material20remains after completion of the etching through masking material16. Where hardmask material16comprises SixOyNz, example etching chemistries include any of HBr, CF4, or other fluorocarbon chemistries. If all of material20were removed in theFIG. 3etch (not shown), material16may be considered as spaced first features.

References are made herein to acts of first etching, second etching, and third etching. Such references to first, second, and third are defined as only being temporally related to each other, and do not preclude other etching having been conducted to the stated material or other material before such acts of etching. For example, etching of such material or other material may or may not occur before and/or after the stated etching. Further, additional etching of one or more stated materials might occur between the stated first, second, and third etchings.

Referring toFIG. 4, etching has been conducted only partially into carbon-comprising material14. Such partial etching may be into less than one half, one half, or more than one half of thickness of carbon-comprising material14. Such may be determined or controlled by time of etch.FIG. 4depicts an example wherein the partial etching has been into less than one half of thickness of carbon-comprising material14. Regardless, in one example wherein carbon-comprising material14has a thickness of from about 700 Angstroms to about 2,000 Angstroms, such partial etching into carbon-comprising material14is into from about 300 Angstroms to about 1,500 Angstroms of material14. Where carbon-comprising material14is amorphous carbon or transparent carbon, an example anisotropic etching chemistry comprises a combination of O2and SO2. Example parameters for such etching include a pressure from about 1 mTorr to about 30 mTorr, source power from about 200 Watts to about 1,500 Watts, bias voltage from about 50 volts to about 500 volts, substrate temperature at from about 10° C. to about 70° C., and combined SO2and O2flow from about 20 sccm to about 500 sccm. An alternate example chemistry includes a combination of O2, N2, and HBr. Example parameters for such etching include a pressure from about 1 mTorr to about 30 mTorr, source power from about 200 Watts to about 1,500 Watts, bias voltage from about 50 volts to about 500 volts, substrate temperature at from about 10° C. to about 70° C., O2flow from about 10 sccm to about 300 sccm, N2flow from about 10 sccm to about 500 sccm, and HBr flow from about 10 sccm to about 300 sccm.

FIG. 4depicts an embodiment wherein the partial etching has formed spaced second features30within carbon-comprising material14which comprise partially etched carbon-comprising material14and hardmask material16. As stated above, some or all of spaced first features26ofFIG. 2may or may not remain at the conclusion of the exampleFIG. 3etching. Further, spaced second features30may or may not comprise material of spaced first features26. Regardless, the spaced first features may or may not be completely removed from the substrate at some point. In one embodiment where such are completely removed from the substrate, such act of removing might be completed during the act of etching only partially into carbon-comprising material14. InFIG. 4, all remnant of spaced first features26fromFIG. 2have been etched completely away from the substrate at or prior to completion of the partial etching into carbon-comprising material14.

Referring toFIG. 5, a spacer-forming layer32has been deposited over/as part of substrate10. Such may be homogenous or non-homogenous, and may comprise a material different in composition from that of carbon-comprising material14. Example materials include silicon, silicon-dioxide, and/or silicon nitride. Thickness of spacer-forming layer32may be largely determinative of feature width dimensions as will be apparent from the continuing discussion.

Referring toFIG. 6, spacer-forming layer32has been anisotropically etched to form spacers34along sidewalls of spaced second features30. In one embodiment and as shown, anisotropically etched spacers34are formed in direct physical touching contact with carbon of carbon-comprising material14. In one embodiment and as shown, formation of anisotropically etched spacers34leaves alternating outwardly exposed regions35of carbon-comprising material14and hardmask material16between immediately adjacent of anisotropically etched spacers34.

In one embodiment, a method of forming a pattern on a material additionally includes lithographically patterning the peripheral circuitry area after the partial etching into the carbon-comprising material, and in one embodiment after forming the anisotropically etched spacers. Such is shown by way of example only inFIG. 7wherein a suitable masking material36has been deposited and lithographically patterned within peripheral circuitry area24. Example masking material36may be homogenous or non-homogenous, and may comprise multiple different composition layers. Regardless,FIG. 7depicts masking material36having been patterned to form an example feature opening38within peripheral circuitry area24. Other and/or additional features (not shown) would likely also be formed in peripheral circuitry area24.

Referring toFIG. 8, second etching has been conducted of hardmask material16(not shown) from between anisotropically etched spacers34. Such has also been conducted relative to example feature opening38in peripheral circuitry area24. Suitable etching chemistries and conditions may be selected by the artisan for the depicted removal of the hardmasking material16as exemplified byFIG. 8. Such is shown as having been conducted substantially selectively relative to carbon-comprising material14and masking material36, although such is not required.

Referring toFIG. 9, third etching has been conducted through carbon-comprising material14to base material12using anisotropically etched spacers34as a mask. Some or none of anisotropically etched spacers34may be etched during such etching of carbon-comprising material14.FIG. 9depicts one example embodiment wherein etching of carbon-comprising material14has been conducted substantially selectively relative to material32of anisotropically etched spacers and selectively relative to hard masking material16in peripheral circuitry area24. Example etching chemistry and conditions to produce theFIG. 9construction are the same as that described above in conducting theFIG. 4etch.

Regardless,FIG. 9depicts formation of spaced third features45which comprise anisotropically etched spacers34and carbon-comprising material14.FIG. 9also depicts one example pattern formed on a substrate.

Pattern formation may continue relative to substrate10. For example, base material12may be processed through a mask pattern comprising spaced third features45. For example, base material12may be ion implanted or otherwise doped through mask openings defined between spaced third features45. Additionally or alternately, such processing might comprise etching into base material12, as shown by way of example only inFIG. 10. One or more different etching chemistries might be utilized depending upon the composition or compositions of material of base material12being etched.FIG. 10depicts partial etching into base material12, andFIG. 11depicts subsequent removal of materials14,30and16(not shown) from outwardly of base material12. Some, none, or all of materials14,30, and16may be removed (i.e., etched) during theFIG. 10etching. Regardless,FIG. 11depicts but one example of another pattern formed on a substrate by one or more aspects of the above embodiments.

In one embodiment, base material12may be used to form a pattern of charge storage transistor gate constructions for use in NAND circuitry. Example NAND circuitry is described with reference toFIGS. 12 and 13.FIG. 12is a simplified block diagram of an example memory system100. Such includes an integrated circuit NAND flash memory device102that includes an array of floating-gate memory cells104, an address decoder106, row access circuitry108, column access circuitry110, control circuitry112, input/output (I/O) circuitry114, and an address buffer116. Memory system100includes an external microprocessor120electrically connected to memory device102for memory accessing as part of an electronic system. Memory device102receives control signals from processor120over a control link122. The memory cells are used to store data that is accessed via a data (DQ) link124. Address signals are received via an address link126, and are decoded at address decoder106to access the memory array104. Address buffer circuit116latches the address signals. The memory cells may be accessed in response to the control signals and the address signals.

FIG. 13is a schematic of a NAND memory array200. Such may be a portion of memory array104ofFIG. 18. Memory array200includes access lines (i.e., wordlines)2021to202N, and intersecting local data lines (i.e., bitlines)2041to204M. The number of wordlines202and the number of bitlines204may be each some power of two, for example 64 wordlines and 64 bitlines. The local bitlines204may be coupled to global bitlines (not shown) in a many-to-one relationship.

Memory array200includes NAND strings2061to206M. Each NAND string includes floating gate transistors2081to208N. The floating gate transistors are located at intersections of wordlines202and a local bitlines204. The floating gate transistors208represent non-volatile memory cells for storage of data, or in other words are comprised by flash transistor gates. The floating gate transistors208of each NAND string206are connected in series source to drain between a source select gate210and a drain select gate212. Each source select gate210is located at an intersection of a local bitline204and a source select line214, while each drain select gate212is located at an intersection of a local bitline204and a drain select line215.

A source of each source select gate210is connected to a common source line216. The drain of each source select gate210is connected to the source of the first floating-gate transistor208of the corresponding NAND string206. For example, the drain of source select gate2101is connected to the source of floating-gate transistor2081of the corresponding NAND string2061.

The drain of each drain select gate212is connected to a local bitline204for the corresponding NAND string at a drain contact228. For example, the drain of drain select gate2121is connected to the local bitline2041for the corresponding NAND string2061at drain contact2281. The source of each drain select gate212is connected to the drain of the last floating-gate transistor208of the corresponding NAND string206. For example, the source of drain select gate2121is connected to the drain of floating gate transistor208Nof the corresponding NAND string2061.

Floating gate transistors208(i.e., flash transistors208) include a source230and a drain232, a floating gate234, and a control gate236. Floating gate transistors208have their control gates236coupled to a wordline202. A column of the floating gate transistors208are those NAND strings206coupled to a given local bitline204. A row of the floating gate transistors208are those transistors commonly coupled to a given wordline202.

Floating gate transistors208may be considered as comprising charge storage transistor gate constructions in NAND memory circuitry. For example, base material12may be fabricated to comprise an appropriate stack for forming such constructions. By way of example only,FIG. 14depicts one example stack of materials with respect to a substrate fragment10afrom which an example charge storage transistor gate construction may be fabricated in accordance with any of the above techniques. Like numerals from the above-described embodiments have been utilized where appropriate, with some construction differences being indicated with the suffix “a” or with different numerals. InFIG. 14, base material12ais depicted as comprising a stack of different materials. For example, material50may be semiconductor material, such as lightly background-doped monocrystalline silicon of a first or second conductivity type. A dielectric material52which will function as a tunnel dielectric has been deposited over semiconductor material50. Any existing or yet-to-be developed material is contemplated, with silicon dioxide being an example. Tunnel dielectric52may be homogenous or non-homogenous, for example comprising multiple different composition dielectric layers. Floating gate material54has been deposited over tunnel dielectric material52. Such may be homogenous or non-homogenous, with suitably doped silicon being one example.

Gate dielectric material66has been deposited over floating gate material54. Such may be homogenous or non-homogenous, with a depicted example showing such being comprised of three layers56,58, and60. Example materials include one or more of silicon dioxide, hafnium oxide, aluminum oxide, zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, etc. Regardless, conductive control gate material62has been deposited over gate dielectric material66. Such also may be homogenous or non-homogenous, and may include multiple different conductive compositions and layers. Examples include conductively doped semiconductive material (i.e., silicon), elemental metals, alloys of elemental metals, and conductive metal compounds. A protective sacrificial material64(i.e., SiO2and/or Si3N4) has been deposited over conductive control gate material62.

The exampleFIG. 14stack of a base material12amay be etched to form a pattern of charge storage transistor gate constructions using a mask pattern comprising spaced third features as by way of example only described above in connection withFIG. 10.

The above-described processing may or may not be conducted to result in pitch reduction. Some existing pitch reduction techniques provide a low temperature-deposited spacer directly against photoresist which might be avoided in practice of embodiments of the invention. For example in one embodiment, carbon-comprising material14does not comprise photoresist.