OPTICAL RECEIVER, MASTER STATION DEVICE, OPTICAL COMMUNICATION SYSTEM

An optical receiver includes an APD, a preamplifier, a limiting amplifier, and an upper-level system. The preamplifier includes a core amplifier circuit that amplifies a current signal, an AGC that changes a conversion gain of the core amplifier circuit by adjusting a first adjustment value, a single phase differential conversion circuit that converts a single-phase signal from the core amplifier circuit into a differential signal, an ATC that changes a threshold for use in the single phase differential conversion circuit by adjusting a second adjustment value, and a processing unit that associates the first adjustment value obtained by adjustment by the AGC based on an output of the core amplifier circuit and the second adjustment value obtained by adjustment by the ATC based on the output of the core amplifier circuit with identification information of one of the slave station devices to store them in a storage unit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates to an optical receiver and a master station device each for use in an optical communication system, and to an optical communication system.

2. Description of the Related Art

In recent years, an access optical communication system called passive optical network (PON) system has been widely used, which allows multiple users to share a single optical fiber. A PON system includes a single optical line terminal (OLT), serving as a master station device, and multiple optical network units (ONUs), each of which is a subscriber terminal device and also called slave station device. The OLT and the ONUs are connected to each other via an optical star coupler, which is a passive element requiring no power supply and serves as an optical splitter for splitting an optical signal.

In upstream communication from the ONUs to the OLT, a PON system uses a time division multiplexing scheme, in which the OLT grants permission with respect to the transmission time and the amount of transmission data, to each of the ONUs. The ONU performs upstream communication at timing permitted by the OLT in the amount of transmission data permitted by the OLT.

The distance between the OLT and each of the ONUs depends on the installation locations of the ONU, resulting in different levels of intensity of upstream optical signals received by the OLT. This causes the OLT to receive intermittently upstream signals having various levels of intensity from multiple ONUs. The range of intensity of an optical signal to be received by the OLT is specified in standards and the like, and is accordingly limited to some extent. That range is, for example, from a weak signal having a power level of about −30 dBm or the like to a strong signal having a power level of about −10 dBm or the like. Thus, an OLT is required to receive optical signals different in intensity by 100 times or more.

When a received optical signal has low intensity, the OLT needs to amplify the signal with a high conversion gain to perform processing such as clock and data recovery. A preamplifier is thus widely used that has a high conversion gain and is capable of converting a current signal from a light-receiving device into a voltage signal. However, when an amplifier receives an optical signal having high intensity with a same conversion gain as the conversion gain to be used for an optical signal having low intensity, the optical signal having high intensity will undergo distortion in the waveform in the amplifier. A method is thus widely used in which the conversion gain of the amplifier is adjusted after the optical signal is received. Note that the preamplifier includes a single phase differential conversion circuit to generate a differential signal as the input to the downstream amplifier, and the threshold for use in the single phase differential conversion circuit also needs adjustment when the conversion gain has been adjusted. The method in which the conversion gain and the threshold are adjusted after the optical signal is received fails to allow the preamplifier to output a normal waveform during the settling time from the start of reception of the optical signal until completion of the adjustment. Thus, providing as short a settling time as possible is preferable.

To reduce the settling time, Japanese Patent No. 5811955 suggests a method in which the time constant of the automatic gain adjustment circuit for adjusting the conversion gain and the time constant of the automatic threshold control circuit for adjusting the threshold are each switched from one to another according to a signal detection result. An automatic gain adjustment circuit is hereinafter referred to as automatic gain control (AGC) circuit, and an automatic threshold control circuit is hereinafter referred to as automatic threshold control (ATC) circuit. This method is performed such that the time constants of the AGC circuit and of the ATC circuit are decreased during the adjustment period, and are increased after the adjustments are completed. This can reduce the settling time.

However, the foregoing conventional technology indeed allows reduction of the settling time, but the settling time still remains, and a further reduction of the settling time is demanded.

SUMMARY OF THE INVENTION

In order to solve the above-described problems and achieve the object, an optical receiver according to the disclosure to be installed in a master station device that receives an optical signal in a time division multiplexing scheme from a plurality of slave station devices, the master station device being connected to the slave station devices via an optical transmission channel, the optical receiver includes: a photoelectric conversion element to convert the optical signal into a current signal; a preamplifier to amplify the current signal output from the photoelectric conversion element and to convert the amplified current signal into a voltage signal; a limiting amplifier to further amplify the voltage signal output from the preamplifier and to limit an amplified amplitude of the voltage signal within a predetermined range; and an upper-level system to output a reset signal to the preamplifier in accordance with timing of reception of the optical signal, wherein the preamplifier includes a core amplifier circuit to amplify the current signal, an automatic gain control circuit to change a conversion gain of the core amplifier circuit by adjusting a first adjustment value, a single phase differential conversion circuit to convert a single-phase signal output from the core amplifier circuit into a differential signal, an automatic threshold control circuit to change a threshold for use in the single phase differential conversion circuit by adjusting a second adjustment value, and a processing unit to associate the first adjustment value obtained by adjustment performed by the automatic gain control circuit on a basis of an output of the core amplifier circuit and the second adjustment value obtained by adjustment performed by the automatic threshold control circuit on a basis of the output of the core amplifier circuit with identification information of a corresponding one of the slave station devices received from the upper-level system, and to store the first adjustment value, the second adjustment value, and the identification information in association with one another in a storage unit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An optical receiver, a master station device, and an optical communication system according to embodiments of the present disclosure will be described in detail below with reference to the drawings.

First Embodiment

FIG.1is a diagram illustrating a configuration of an optical communication system5according to a first embodiment. The optical communication system5is a PON system including an OLT1and a plurality of ONUs2-1to2-3. The OLT1is also called master station device, and is connected to the plurality of ONUs2-1to2-3using an optical splitter3and an optical fiber4, where the optical splitter3branches the optical transmission channel. Note that when no distinction is needed among the plurality of ONUs2-1to2-3, the ONUs2-1to2-3are each referred to simply as ONU2. The ONU2is also called slave station device. AlthoughFIG.1illustrates an example in which the single OLT1is connected to the three ONUs2, the number of the ONUs2to be connected to the single OLT1is not limited to three. The number of the ONUs2connected to the single OLT1may be two or four or more.

In upstream communication from the ONUs2to the OLT1, the optical communication system5uses a time division multiplexing scheme, in which the OLT1grants permission with respect to the transmission time and the amount of transmission data, to each of the plurality of ONUs2. As such, the OLT1knows in advance which ONU2among the ONUs2-1to2-3is the ONU2that is the source of the optical signal received. The OLT1includes an optical receiver10for receiving the optical signal.

FIG.2is a diagram illustrating a configuration of the optical receiver10illustrated inFIG.1. The optical receiver10includes an avalanche photodiode (APD)100, which is a photoelectric conversion element for converting an optical signal into a current signal; a preamplifier200, which amplifies the current signal output from the APD100and converts the amplified current signal into a voltage signal; a limiting amplifier300, which further amplifies the voltage signal output from the preamplifier200and limits an amplified amplitude of the voltage signal within a predetermined range; and an upper-level system400, which has a clock and data recovery function to extract and reproduce a clock and data from the signal output from the limiting amplifier300. The upper-level system400also performs operations such as providing a reset signal to each of the preamplifier200and the limiting amplifier300, supplying ONU information to the preamplifier200, and managing the time of arrival of a signal from each of the plurality of ONUs2and identification information of the ONUs2. The ONU information include, for example, identification information of the ONU2that is the source of an optical signal to be received next.

The APD100converts a received optical signal into a current signal, and outputs the current signal to the preamplifier200. The preamplifier200amplifies the current signal output by the APD100, converts the amplified current signal into a voltage signal, and outputs the voltage signal to the limiting amplifier300. The limiting amplifier300further amplifies the voltage signal output by the preamplifier200, limits an amplified amplitude of the voltage signal within a predetermined range, and outputs the voltage signal having the limited amplitude to the upper-level system400. The upper-level system400extracts and reproduces a clock and data from the signal output by the limiting amplifier300. In addition, the preamplifier200controls operation of the preamplifier200on the basis of a reset signal output by the upper-level system400and on the basis of ONU information including identification information of the ONUs2, details of which are described later.

The preamplifier200includes a core amplifier circuit201; an AGC202, which is an automatic gain control circuit; an ATC203, which is an automatic threshold control circuit; a single phase differential conversion circuit204; an analog-to-digital converter (ADC)205; a digital-to-analog converter (DAC)206; a storage unit207; and a processing unit208.

The core amplifier circuit201amplifies the current signal from the APD100. The conversion gain of the core amplifier circuit201is adjusted by the AGC202. The output of the core amplifier circuit201is connected to each of the AGC202, the ATC203, and the single phase differential conversion circuit204.

The AGC202has functionality to adjust the conversion gain of the core amplifier circuit201. The AGC202is capable of changing the conversion gain of the core amplifier circuit201by adjusting the value of a first adjustment value to be output to the core amplifier circuit201. The AGC202has a function to adjust the first adjustment value and to thereby adjust the conversion gain so as to cause the output of the core amplifier circuit201to be set at a predetermined level, on the basis of the output of the core amplifier circuit201. The AGC202also has a function to change the conversion gain by outputting the first adjustment value received from the DAC206to the core amplifier circuit201upon reception of the first adjustment value from the DAC206. The first adjustment value is a voltage value, and is provided to a feedback resistor unit (not illustrated) of the core amplifier circuit201. The feedback resistor unit is typically a parallel circuit of a resistor and a metal-oxide-semiconductor field-effect transistor (MOSFET). The first adjustment value acts as a gate voltage of the MOSFET included in the feedback resistor unit of the core amplifier circuit201. Adjustment of the value of the first adjustment value causes the gate voltage of the MOSFET to be changed, and a change in the resistance value of the feedback resistor unit then causes the signal amplification gain of the core amplifier circuit201to be changed. A higher resistance value of the feedback resistor unit provides a higher gain, and a lower resistance value thereof provides a lower gain.

The ATC203has a function to adjust the threshold for use in the single phase differential conversion circuit204. The ATC203is capable of changing the threshold to be input to the single phase differential conversion circuit204by adjusting a second adjustment value to be output to the single phase differential conversion circuit204. The ATC203has a function to adjust the second adjustment value on the basis of the output of the core amplifier circuit201to thereby adjust the threshold for use in the single phase differential conversion circuit204. The ATC203also has a function to adjust the threshold by outputting the second adjustment value received from the DAC206to the single phase differential conversion circuit204upon reception of the second adjustment value from the DAC206. The second adjustment value is a voltage value, and is used as an input voltage of one of two inputs of a differential amplifier circuit constituting the single phase differential conversion circuit204.

The single phase differential conversion circuit204receives, as the input, the output of the core amplifier circuit201and the output of the ATC203, i.e., the threshold, and converts a single-phase signal into a differential signal. For example, the output of the core amplifier circuit201can be used as the in-phase input of the single phase differential conversion circuit204, and the output of the ATC203, i.e., the threshold, can be used as the antiphase input of the single phase differential conversion circuit204. The differential amplifier circuit constituting the single phase differential conversion circuit204is a current model logic (CML) circuit based on a general MOSFET, an emitter-coupled logic (ECL) based on a bipolar transistor, or the like. When the single phase differential conversion circuit204is configured by using a CML circuit, the second adjustment value acts as a gate voltage of the MOSFET included in the CML circuit. When the single phase differential conversion circuit204is configured by using an ECL, the second adjustment value acts as a base voltage of the bipolar transistor included in the ECL. Now, let DC1denote the in-phase input signal center of the single phase differential conversion circuit204, and let DC2denote the antiphase input signal center thereof. In this case, the value of a direct current (DC) offset “DC1-DC2” is ideally 0 mV for achieving a high amplification factor and an output differential signal without distortion. An example of signal without distortion is a sine wave having a duty cycle of 50%. In this respect, when the DC offset “DC1-DC2” has a value different from 0 mV, an amplification factor of the single phase differential conversion circuit204is lowered, thereby causing the output differential signal to have a distorted signal waveform. That is, even when the output voltage of the core amplifier circuit201has a constant amplitude, a DC offset “DC1-DC2” having a value deviated more from 0 mV results in a smaller output voltage amplitude of the single phase differential conversion circuit204, thereby also causing the duty cycle to deviate more from 50%. The optical receiver10thus performs control to make the value of DC2approach DC1so as to make the value of “DC1-DC2” approach 0 mV. The value of DC2is the output of the ATC203, i.e., the second adjustment value, and is the threshold for use in the single phase differential conversion circuit204. Thus, the optical receiver10performs control to cause the second adjustment value to approach the value of DC1, i.e., the output signal center of the core amplifier circuit201. The differential signal output by the single phase differential conversion circuit204is input to the limiting amplifier300.

The ADC205converts an analog value into a digital value. The ADC205is capable of converting the first adjustment value and the second adjustment value output respectively by the AGC202and the ATC203, which are analog values, into digital values, and outputting the digital values obtained by conversion to the storage unit207.

The DAC206converts a digital value into an analog value. The DAC206is capable of converting the first adjustment value stored in the storage unit207from a digital value to an analog value, and outputting the first adjustment value that is now an analog value obtained by the conversion, to the AGC202. The DAC206is also capable of converting the second adjustment value stored in the storage unit207from a digital value to an analog value, and outputting the second adjustment value that is now an analog value obtained by the conversion, to the ATC203.

The storage unit207has a function to store the first adjustment value and the second adjustment value output by the ADC205, which are each a digital value. The storage unit207is capable of outputting the first adjustment value and the second adjustment value stored therein to the DAC206, according to an instruction from the processing unit208.

The processing unit208is a simple circuit that controls operation of the preamplifier200. The processing unit208is capable of receiving a reset signal and ONU information from the upper-level system400, and controlling the operation of the preamplifier200on the basis of the information received from the upper-level system400. The control performed by the processing unit208will be described in detail later.

FIG.3is a diagram illustrating observation points in the preamplifier200illustrated inFIG.2.FIG.4is a diagram illustrating a simplified example of waveforms over time at the observation points illustrated inFIG.3. The observation points illustrated inFIG.3will first be described. Observation point A is an input point to the APD100, at which observation is made of the optical signal to be input to the APD100. Observation point B is an output point of the core amplifier circuit201, at which observation is made of the signal obtained by amplification performed by the core amplifier circuit201. Observation point C is an output point from the AGC202to the core amplifier circuit201, at which the first adjustment value is observed. Observation point D is an output point of the ATC203, at which the second adjustment value is observed. Observation point E is an input point from the upper-level system400to the processing unit208, at which the reset signal is observed.

As observed at observation point A, an optical signal from one of the ONUs2is received at time T. At this time, because timing of arrival of the optical signal from the ONU2is known, a reset signal is provided so as to be observed at observation point E in conjunction with the arrival of the optical signal at time T. After receiving the optical signal, the core amplifier circuit201performs inverting amplification to cause the output of the core amplifier circuit201to have a largely reduced direct current (DC) level so as to be observed at observation point B. The broken line illustrated in the graph of observation point B represents the output level of the core amplifier circuit201at an appropriate conversion gain.

The dashed-and-dotted lines respectively represent the waveforms over time at observation point C and at observation point D that would be obtained when the AGC202and the ATC203respectively adjust the conversion gain and the threshold by adjusting the values of the first adjustment value and of the second adjustment value on the basis of the output of the core amplifier circuit201as conventionally performed.

First, after receiving the optical signal, the AGC202determines whether the output of the core amplifier circuit201is at a higher or lower level than an appropriate level. When the AGC202determines that the conversion gain is higher than an appropriate value thereby causing the output of the core amplifier circuit201to be at a lower level than an appropriate level as illustrated inFIG.4, the AGC202adjusts the first adjustment value to reduce the conversion gain. Note that this example assumes that a higher value of the first adjustment value observed at observation point C provides a lower conversion gain, but on the contrary, a lower value of the first adjustment value may provide a lower conversion gain. The time required for the AGC202to perform the adjustment is herein designated by t1. The time t1is about several tens of nanoseconds in a fast case.

Next, the ATC203is often designed to follow the output of the core amplifier circuit201. In this case, the value at observation point D behaves similarly to the value at observation point B. There may be cases, however, in which this will not apply, depending on the design of the circuit. The second adjustment value observed at observation point D is preferably a value adapted to the DC level of the output of the core amplifier circuit201observed at observation point B. The second adjustment value may therefore be generated by removing high-frequency components from the waveform at observation point B using a low-pass filter or the like. In this case, the waveform at observation point D varies moderately over time. When the ATC203is operated to follow the output of the core amplifier circuit201, the adjustment operation of the ATC203will be completed after the adjustment operation of the AGC202is completed. Denoting by t2the time required for the ATC203to perform adjustment, t2has a value greater than t1.

A method of adjustment of the first adjustment value and the second adjustment value when the optical receiver10of the present embodiment receives an optical signal will next be described. The optical receiver10has stored a preregistered first adjustment value and second adjustment value in the storage unit207on a per-ONU2basis. In the optical receiver10, the timing of arrival of an optical signal from each of the ONUs2is known. The optical receiver10can accordingly reduce the time required for the adjustments by changing the conversion gain and the threshold in conjunction with the arrival of the optical signal using the preregistered first adjustment value and second adjustment value. The waveforms over time at observation point C and at observation point D ofFIG.4in this case are represented by the broken lines. The times t1and t2required for the adjustments can theoretically be reduced to zero. A concrete operation is as follows. The upper-level system400of the optical receiver10outputs a reset signal to the preamplifier200in accordance with the known timing of signal reception, and the processing unit208of the preamplifier200provides the first adjustment value and the second adjustment value stored in the storage unit207respectively to the AGC202and to the ATC203at the timing in accordance with the reset signal. The AGC202changes the conversion gain by using the first adjustment value provided, and the ATC203changes the threshold by using the second adjustment value provided.

Note that performing adjustment of the first adjustment value and the second adjustment value instantaneously in conjunction with the arrival of the optical signal as described above requires preregistration of the first adjustment value and the second adjustment value to be used. Registration operation of the first adjustment value and the second adjustment value will next be described.

FIG.5is an illustrative diagram with respect to processing of registration of the first adjustment value and the second adjustment value performed by the optical receiver10illustrated inFIG.2.FIG.5illustrates reception signals of the OLT1, transmission signals of the OLT1, internal signals of the OLT1, outputs of the AGC202in the preamplifier200of the OLT1, the state of the preamplifier200, reception signals of the ONU2, and transmission signals of the ONU2. The internal signals of the OLT1refer to signals transmitted and received inside the OLT1, for example, between the upper-level system400and the preamplifier200. The ONU2is one of the ONUs2-1to2-3illustrated inFIG.1.

The processing ofFIG.5begins at the time when the ONU2is first connected to a network. To check whether there is a newly connected ONU2in the network, the OLT1transmits a Gate signal (step S1). In synchronization with the Gate signal transmitted to the ONU2, a Gate signal is provided to the preamplifier200as an internal signal (step S2). In this respect, the electrical path to provide the Gate signal to the preamplifier200may be the signal line for providing the reset signal illustrated inFIG.2, the signal line for providing the ONU information illustrated inFIG.2, or another signal line different from these signal lines that is separately installed.

Upon reception of the Gate signal, the preamplifier200transitions to “Reg. stand-by” state, in which processing of registration of the first adjustment value and the second adjustment value is performed. Note that the following description may refer to each of the first adjustment value and the second adjustment value simply as adjustment value. Upon reception of the Gate signal, the ONU2transmits, to the OLT1, a registration request including necessary information for registration for the ONU2itself in the network (step S3).

Upon reception of the registration request from the ONU2, the OLT1performs processing of adjustment of the adjustment values on the basis of the output of the core amplifier circuit201in a conventional manner because adjustment values suitable for this ONU2are unknown at this stage of operation. After completion of adjustment of the adjustment values, the OLT1provides, to the preamplifier200, a reset signal indicating that a signal has been received from the ONU2, as an internal signal (step S4). The preamplifier200converts the adjustment values at the time of reception of this reset signal into digital signals, and registers the adjustment values in the storage unit207. At this stage of operation, the registered adjustment values are not associated with the identification information of the ONU2. Upon reception of another reset signal as an internal signal (step S5), the preamplifier200terminates an adjustment value registering state.

After reception of the registration request, the OLT1determines the transmission timing and the amount of transmission data of the ONU2, and then transmits a “Register+gate” signal, which is a signal containing these assignment information and is a registration confirmation message for the ONU2(step S6). In this operation, the OLT1provides a data sequence containing the identification information of the ONU2to the preamplifier200as an internal signal (step S7). Upon reception of this identification information, the preamplifier200associates the adjustment values already stored in the storage unit207with the identification information received, and registers these adjustment values and the identification information in association with each other. For example, the preamplifier200can associate the adjustment values with the identification information by associating a register address with the identification information of the ONU2.

Upon reception of the “Register+gate” signal, the ONU2transmits an Ack signal for acknowledgment of the reception (step S8). Because the timing of arrival of the signal from the ONU2is known at this stage of operation, the OLT1provides a reset signal and the identification information for identifying the ONU2that is the source of the signal received, as internal signals, in accordance with timing of reception of the Ack signal (step S9).

Because the adjustment values have already been registered, the preamplifier200reads, in accordance with the reset signal, the adjustment values which are associated with the provided identification information and stored in the storage unit207, and provides the adjustment values respectively to the AGC202and to the ATC203. Adjustment of the adjustment values is thus completed instantaneously. Adjustment of the adjustment values results in adjustment of the conversion gain and of the threshold. Upon termination of the signal from the ONU2, the OLT1provides a reset signal to the preamplifier200as an internal signal (step S10). The preamplifier200terminates an adjustment value reading state at timing in accordance with this reset signal.

As described above, the optical receiver10according to the first embodiment is the optical receiver10to be installed in the OLT1, which is a master station device that is connected to the ONUs2via an optical transmission channel to receive an optical signal in a time division multiplexing scheme from the plurality of ONUs2, which are a plurality of slave station devices. The optical receiver10includes the APD100, which is a photoelectric conversion element that converts an optical signal into a current signal; the preamplifier200, which amplifies the current signal output from the APD100and converts the amplified current signal into a voltage signal; the limiting amplifier300, which further amplifies the voltage signal output from the preamplifier200, and limits an amplified amplitude of the voltage signal within a predetermined range; and the upper-level system400, which outputs a reset signal to the preamplifier200in accordance with timing of reception of an optical signal. The preamplifier200includes the core amplifier circuit201; the AGC202, which is an automatic gain control circuit that changes the conversion gain of the core amplifier circuit by adjusting the first adjustment value; the single phase differential conversion circuit204, which converts a single-phase signal output by the core amplifier circuit201into a differential signal; the ATC203, which is an automatic threshold control circuit that changes the threshold for use in the single phase differential conversion circuit204by adjusting the second adjustment value; and the processing unit208, which associates the first adjustment value obtained by adjustment performed by the AGC202on the basis of the output of the core amplifier circuit201and the second adjustment value obtained by adjustment performed by the ATC203on the basis of the output of the core amplifier circuit201with the identification information of each corresponding one of the ONUs2received from the upper-level system400, and stores the first adjustment value, the second adjustment value, and the identification information in association with one another, in the storage unit207. The processing of the processing unit208of associating the first adjustment value and the second adjustment value with the identification information and of storing these data is performed, for example, as part of initial registration processing when the corresponding one of the ONUs2is first connected to the network.

Such configuration enables the first adjustment value and the second adjustment value that are appropriate at the time of reception of an optical signal from each of the ONUs2to be associated with, and be stored together with, the identification information of each corresponding one of the ONUs2. The time required for the adjustments can thus be reduced by using the adjustment values stored in advance when the conversion gain of the core amplifier circuit201and the threshold for use in the single phase differential conversion circuit204are adjusted.

The AGC202changes the conversion gain of the core amplifier circuit201using the first adjustment value stored in the storage unit207at timing in accordance with a reset signal, and the ATC203changes the threshold using the second adjustment value stored in the storage unit207at timing in accordance with the reset signal. In this manner, adjustment of the conversion gain and of the threshold can be completed at timing in accordance with a reset signal provided in accordance with known reception timing, thereby enabling the preamplifier200to output a normal waveform from the beginning.

Second Embodiment

FIG.6is a diagram illustrating a configuration of an optical receiver10A according to a second embodiment. The optical receiver10A is installed in the OLT1. The optical receiver10A includes the APD100, a preamplifier200A, the limiting amplifier300, and the upper-level system400, and includes the preamplifier200A in place of the preamplifier200of the optical receiver10. The following description will be primarily presented in the context of differences from the optical receiver10according to the first embodiment, and detailed description of portions common to the first embodiment will be omitted.

The preamplifier200A includes, in addition to the components of the preamplifier200, an adjustment-purpose core amplifier circuit209, which amplifies the current signal from the APD100; an AGC210, which is an adjustment-purpose automatic gain control circuit that changes the conversion gain of the adjustment-purpose core amplifier circuit209by adjusting a third adjustment value on the basis of an output of the adjustment-purpose core amplifier circuit209; and an ATC211, which is an adjustment-purpose automatic threshold control circuit that adjusts a fourth adjustment value on the basis of the output of the adjustment-purpose core amplifier circuit209. The processing unit208is capable of causing the ADC205to convert the third adjustment value obtained by adjustment performed by the AGC210and the fourth adjustment value obtained by adjustment performed by the ATC211into digital values, of updating the first adjustment value stored in the storage unit207using the third adjustment value obtained by conversion, and of updating the second adjustment value stored in the storage unit207using the fourth adjustment value obtained by adjustment performed by the ATC211. In this operation, the processing unit208updates the first adjustment value and the second adjustment value that were in use when the third adjustment value and the fourth adjustment value were adjusted.

This enables the optical receiver10A to update the first adjustment value and the second adjustment value that have been once registered in the storage unit207. Thus, even when the appropriate adjustment values have changed due to an environmental change, aging degradation, and/or the like, such changes can be addressed.

Third Embodiment

FIG.7is a diagram illustrating a configuration of an optical receiver10B according to a third embodiment. The optical receiver10B is installed in the OLT1. The optical receiver10B includes the APD100, a preamplifier200B, the limiting amplifier300, and the upper-level system400, and includes the preamplifier200B in place of the preamplifier200of the optical receiver10. The following description will be primarily presented in the context of differences from the optical receiver10according to the first embodiment, and detailed description of portions common to the first embodiment will be omitted.

The preamplifier200B includes, in addition to the components of the preamplifier200, a signal detection circuit212for detecting the signal included in the output of the core amplifier circuit201, and a selector213, which switches the connection to the input terminal of the single phase differential conversion circuit204on the basis of a signal detection result of the signal detection circuit212. The selector213is capable of switching states between a first state in which the output of the ATC203is connected to the differential input of the single phase differential conversion circuit204and a second state in which the output of the ATC203is connected to the single-phase input of the single phase differential conversion circuit204. In the second state, the output of the ATC203is connected to one-side input of the single-phase inputs of the single phase differential conversion circuit204, and the output of the core amplifier circuit201is connected to the other one-sided input thereof. The selector213selects the first state during a time period after completion of adjustment of the conversion gain of the core amplifier circuit201and of the threshold for use in the single phase differential conversion circuit204until the signal detection circuit212detects a signal, and selects the second state after the signal detection circuit212detects the signal. This can prevent occurrence of a DC offset between the differential outputs of the preamplifier200B in a no-signal section after a reset signal is input. When a DC offset occurs between the differential outputs of the preamplifier200B, that is, when the value of aforementioned “DC1-DC2” is not 0 mV, a case may occur where the amplification factor of the single phase differential conversion circuit204is reduced, and the single phase differential conversion circuit204undergoes distortion of the output waveform. Moreover, a DC offset large enough to exceed the input-output range of the single phase differential conversion circuit204may result in a situation in which no waveform is output from the single phase differential conversion circuit204. Elimination of the DC offset enables such situation to be avoided, and enables the OLT1to continue stable operation.

The configurations described in the foregoing embodiments are merely examples. These configurations may be combined with another known technology, and configurations of different embodiments may be combined together. Moreover, part of such configurations may be omitted and/or modified without departing from the spirit thereof.

For example, although the foregoing embodiments have been described in the context of an avalanche photodiode as an example of photoelectric conversion element, the photoelectric conversion element may be a photoelectric conversion element other than an avalanche photodiode. For example, the photoelectric conversion element may be a PIN junction-type photodiode.

In addition, although the foregoing embodiments have been described in which the output of the core amplifier circuit201is input to the in-phase input of the single phase differential conversion circuit204, and the output of the ATC203, i.e., the threshold, is input to the antiphase input of the single phase differential conversion circuit204, however, the output of the ATC203, i.e., the threshold, may be input to the in-phase input of the single phase differential conversion circuit204, and the output of the core amplifier circuit201may be input to the antiphase input of the single phase differential conversion circuit204.

An optical receiver according to the present disclosure provides an advantage in capability of further reducing the settling time, which is the time required from the start of reception of an optical signal until completion of adjustment of the conversion gain and of the threshold.