INTEGRATED PHOTODETECTOR WITH EMBEDDED SEMICONDUCTOR REGION

In some embodiments, the present disclosure provides an optical module. A waveguide includes a rib, and further includes a first protrusion and a second protrusion respectively on opposite sides of the rib. Further, the waveguide is formed of a first semiconductor material. A photodetector is in the waveguide and comprises a PN junction in the rib. A P type region of the PN junction extends to the first protrusion, and an N type region of the PN junction extends to the second protrusion. Further, the first and second protrusions accommodate heavily doped P and N type contact regions. A semiconductor region is on the PN junction. The semiconductor region comprises a second semiconductor material different the first semiconductor material. For example, the second semiconductor material may have a smaller bandgap than the first semiconductor material to enhance quantum efficiency.

BACKGROUND

At high frequencies or high data rates, electrical transmission is reaching its limit due to high energy loss over long distances. As such, electrical chips that depend on long distance transmission are turning to optical transmission. Such electrical chips may, for example, include switch chips or system-on-chip (SoC) chips. Such SoC chips may, for example, include application-specific integrated circuit (ASIC) chips, central processing unit (CPU) chips, graphics processing unit (GPU) chips, and so on.

DETAILED DESCRIPTION

An optical module may comprise a waveguide and a photodetector. The waveguide passes an optical signal to the photodetector, which generates an electrical signal based on the optical signal. Conventionally, some photodetectors designed to function with both optical circuits and electronic circuits use a flip-chip method of integration, where optical circuits and electronic circuits are fabricated on separate chips before the circuits are bonded together using solder bumps. However, the flip-chip method of integration depends on precise alignment between the chips being bonded in order to effectively pass signals between the two chips. Chips used in flip-chip bonding additionally have a minimum area to support the coupling and separation of individual solder bumps. Therefore, a single chip solution is desirable to reduce the area used by the photodetector, enhance the flexibility of designs, and mitigate the risks associated with misalignment between chips.

Various embodiments of the present disclosure relate to an optical module comprising a photodetector integrated into a ribbed waveguide. In some embodiments, the optical module comprises the ribbed waveguide, where a portion of the ribbed waveguide is divided into a P-type region and an N-type region. The P-type region and the N-type region form a PN junction approximate to a center of the ribbed waveguide. Further, a biasing circuit is coupled to first and second protrusions extending from the P-type region and the N-type region, respectively. The biasing circuit reverse biases the PN junction, widening a depletion region proximate to the center of the ribbed waveguide. Due to the photoelectric effect, photons traveling through the ribbed waveguide may enter the depletion region and generate carriers. The carriers generated in the depletion region are prevented from recombining by the electric field present across the PN junction, which then pulls the carriers towards separate protrusions (e.g., the first and second protrusions) and into the biasing circuit, creating a measurable current.

The integration of a photodetector into the ribbed waveguide increases the flexibility of designs utilizing both photonic and electronic circuits. For example, a device that uses photonic circuits for high speed and/or long distance communications between different chips may convert the photonic signal to an electronic signal without using more than one chip, mitigating or removing issues related to chip bonding, alignment, and minimum space requirements.

FIGS.1A-1Billustrate a cross-sectional view100aand a top layout view100b, respectively, of some embodiments of an optical module comprising a photodetector101integrated with a ribbed waveguide104.

FIG.1Ashows the ribbed waveguide104extending over a handle substrate102. An insulative layer106separates the ribbed waveguide104from the handle substrate102. The handle substrate102, the insulative layer106, and the ribbed waveguide104may comprise layers of a silicon-on-insulator (SOI) substrate. The ribbed waveguide104is surrounded by a plurality of dielectric layers108a-108dand comprises a slab104a. A rib104bextends from a center of the slab104a. A first protrusion104cand a second protrusion104dextend from the slab104a, on opposite sides of the rib104b. In some embodiments, the rib104bmay be regarded as a central rib, and the first protrusion104cand the second protrusion104dmay be regarded as peripheral ribs.

A first-doping-type region112extends from the first protrusion104cto the rib104b, and a second-doping-type region114extends from the second protrusion104dto the rib104b. In some embodiments, the first-doping-type region112is a P-type region and the second-doping-type region114is an N-type region. In other embodiments, the first-doping-type region112is an N-type region and the second-doping-type region114is a P-type region. The first-doping-type region112and the second-doping-type region114form a PN junction113extending through the slab104aand the rib104b. In some embodiments, the PN junction113is approximately at a midpoint between outer sidewalls of the rib104band/or at a center between the first protrusion104cand the second protrusion104d.

A semiconductor region110is on the PN junction113. In some embodiments, the semiconductor region110may be regarded as a semiconductor cap or the like. The ribbed waveguide104comprises a first semiconductor material, such as monocrystalline silicon or the like. The semiconductor region110comprises a second semiconductor material, such as germanium (Ge), or a III-V semiconductor material, such as gallium arsenide (GaAs), indium arsenide (InAs), gallium nitride (GaN), indium phosphide (InP), or the like. The second semiconductor material has a higher absorption coefficient for target radiation than the first semiconductor material and may, for example, have a higher electron mobility and/or differing bandgap energies relative to the first semiconductor material. In some embodiments, the semiconductor region110is devoid of a P-type doping and an N-type doping, whereby the semiconductor region110may be regarded as intrinsic.

The use of the second semiconductor material in the semiconductor region110may increase the quantum efficiency of the photodetector101over the desired range of wavelengths. For example, use of germanium or silicon germanium for the semiconductor region110may improve quantum efficiency for near infrared radiation due to a narrow bandgap relative to silicon. This increase in the quantum efficiency leads to a proportional increase in the electronic output signal of the photodetector101for the same photonic input signal. An increased output signal reduces the effect of noise on the output, which in turn may result in less errors and a more accurate data transfer between the photonic and electronic circuits.

In some embodiments, the semiconductor region110corresponds to a free carrier concentration modulation peak of the photodetector101. Further, in some embodiments, a location at both a height-wise center of the ribbed waveguide104and a width-wise center of the ribbed waveguide104corresponds to a peak of a photoelectric field during use of the photodetector101. Therefore, because a bottom surface of the semiconductor region110is elevated relative to a top surface of the ribbed waveguide104, the carrier modulation peak is above the peak of the photodetector field in some embodiments.

A first heavily doped region116is in the first protrusion104c. The first heavily doped region116has the same doping type as the first-doping-type region112, but has a greater concentration of dopants. A second heavily doped region118is in the second protrusion104d. The second heavily doped region118has the same doping type as the second-doping-type region114, but has a greater concentration of dopants. In some embodiments, the first-doping-type region112and the second-doping-type region114have doping concentrations approximately between 2e16 to 9e18 atoms/cm3, approximately between 2015 to 9e17 atoms/cm3, approximately between 2e17 to 9e19 atoms/cm3, or the like. In further embodiments, the first heavily doped region116and the second heavily doped region118have doping concentrations approximately between 1e18 and 9e20 atoms/cm3, approximately between 1e17 and 9c19 atoms/cm3, approximately between 1e19 and 9c21 atoms/cm3, or the like. In some embodiments, the first heavily doped region116and the first-doping-type region112overlap in a portion of the slab104a. The second-doping-type region114and the second heavily doped region118may also overlap in a portion of the slab104a.

Contacts120are coupled to the first protrusion104c, the second protrusion104d, and the semiconductor region110. The contacts120connect the first protrusion104c, the second protrusion104d, and the semiconductor region110to a wire layer122.

FIG.1Bshows the wire layer122connecting the first protrusion104cto a first pad124, the second protrusion104dto a second pad126, and the semiconductor region110to a third pad128. Note that the plurality of dielectric layers108a-108dare not shown inFIG.1Bto better show the photodetector101. The first pad124and the second pad126are electrically coupled to a bias circuit132and, in some embodiments, the third pad128is electrically grounded. The bias circuit132reverse biases the PN junction113, thereby increasing the area of a depletion region that extends across the PN junction113. A photonic signal130is shown traveling through the ribbed waveguide104towards the photodetector101, where the photonic signal130generates carriers in the depletion region. The reverse biasing of the PN junction113further provides an electric field to pull the generated carriers from the ribbed waveguide104towards an electronic circuit (not shown) coupled to the photodetector101.

The integration of the photodetector101into a single chip capable of holding a photonic circuit and an electronic circuit increases the flexibility of designs utilizing both photonic and electronic circuits, mitigating or removing issues related to chip bonding, alignment, and minimum area requirements of bonded chips.

FIGS.2A-2Billustrate some top layout views200a-200bof various embodiments of an optical coupler202connecting to a photodetector101. InFIG.2A, the photodetector101may, for example, be as inFIGS.1A and1B. InFIG.2B, the photodetector101may, for example, be as inFIGS.1A and1Bexcept that the semiconductor region110is omitted.

The optical coupler202is coupled to the ribbed waveguide104by a strip waveguide204and a transition waveguide206. The optical coupler202may, for example, be a grating coupler, an edge coupler, or the like. At the transition waveguide206, a width of the transition waveguide206increases from a width of the strip waveguide204to a width of the rib104bof the ribbed waveguide104. Further, the slab104atransitions from having a width of the strip waveguide204to having a width of the ribbed waveguide104. One or more additional photonic circuit components (e.g., a power spreader, a Mach-Zehnder modulator (MZM), or the like) may, for example, be coupled to the strip waveguide204or the ribbed waveguide104.

The PN junction113is at the rib104b, formed by the first-doping-type region112and the second-doping-type region114. The first-doping-type region112and the second-doping-type region114extend from the PN junction113respectively to the first protrusion104cand the second protrusion104d. Further, the first protrusion104cand the second protrusion104drespectively accommodate the first heavily doped region116and the second heavily doped region118. Focusing onFIG.2A, and in contrast withFIG.2B, the semiconductor region110overlaps with the rib104band the PN junction113.

FIGS.3A-3Jillustrate some cross-sectional views300a-300jof alternative embodiments of the optical module ofFIG.1A.

Photons entering the ribbed waveguide104may be represented by an electromagnetic field traveling along the ribbed waveguide104. The magnitude of the electromagnetic field is highest near the center of the ribbed waveguide104. The square of the magnitude of the electromagnetic field is proportional to the number of photons concentrated in that position. Therefore, the highest concentration of photons in the ribbed waveguide104is at the center of the ribbed waveguide104, which is approximately at a width-wise center of the rib104band is approximately at a height-wise center of the ribbed waveguide104. Efforts to increase the efficiency of carrier generation (e.g., quantum efficiency) are therefore focused on the center of the ribbed waveguide as described hereafter with regard toFIGS.3A-3J.

As shown in the cross-sectional view300aofFIG.3a, the semiconductor region110is implanted into the rib104bof the ribbed waveguide104. In other words, the second semiconductor material is implanted into the rib104b. Therefore, the semiconductor region110comprises both the first semiconductor material and the second semiconductor material. For example, to the extent that the first semiconductor material is or comprises silicon and the second semiconductor material is or comprises germanium, the semiconductor region110may be or comprise silicon germanium. Other suitable materials are, however, amenable. In some embodiments, the semiconductor region110has a doping concentration of the second semiconductor material approximately between 1e18 to 9e25 atoms/cm3.

During use of the photodetector101, electromagnetic field traveling along the ribbed waveguide104may enter the semiconductor region110. As noted above, the second semiconductor material of the semiconductor region110may have a higher absorption coefficient for incident radiation than the first semiconductor material and may therefore enhance quantum efficiency. In other words, the second semiconductor material increases the number of carriers generated and converted to photoelectric current. Because the semiconductor region110is implanted into the rib104b, the semiconductor region110overlaps with a center of the ribbed waveguide104. Further, because the concentration of photons is highest towards the center of the ribbed waveguide104, greater quantum efficiency is achieved.

In some embodiments, the semiconductor region110corresponds to a free carrier concentration modulation peak of the photodetector101. Further, in some embodiments, the center of the ribbed waveguide104corresponds to a peak of a photoelectric field during use of the photodetector101. Therefore, because the semiconductor region110is at the center of the ribbed waveguide104, the carrier modulation peak is coincident with the peak of the photodetector field in some embodiments.

As shown in the cross-sectional view300bofFIG.3B, the rib104bof the ribbed waveguide104is instead replaced with the semiconductor region110deposited over the PN junction113. Depositing the semiconductor region110may, for example, provide a greater concentration of the second semiconductor material above the PN junction113than implanting the material in the ribbed waveguide104. Therefore, depositing the semiconductor region110may increase the quantum efficiency further at a position approximately coinciding with a peak of the electromagnetic field in the ribbed waveguide104, thereby increasing the magnitude of the electrical output signal further.

As shown in the cross-sectional view300cofFIG.3C, the semiconductor region110extends into the slab104aof the ribbed waveguide104, substantially coinciding with a center of the ribbed waveguide104. The implanted second semiconductor material covers a greater area at the center of the ribbed waveguide104, coinciding with a peak of the electromagnetic field in the ribbed waveguide104, increasing the efficiency of the photodetector101. In some embodiments, a width Wsr of the semiconductor region110is about 100-350 percent of a width Wrb of the rib104b. Other suitable percentages are, however, amenable.

As shown in the cross-sectional view300dofFIG.3D, the semiconductor region110is deposited directly onto the slab104a, and a polysilicon substitute for the rib104bis directly over the semiconductor region110. The configuration shown provides the more concentrated second semiconductor material of the deposited semiconductor region110in a position closer to the center of the ribbed waveguide104than the position of the semiconductor region110in the embodiment shown inFIG.1A, which may lead to better quantum efficiency. In some embodiments, a width Wsr of the semiconductor region110is about 100-350 percent of a width Wrb of the rib104b. Other suitable percentages are, however, amenable.

As shown in the cross-sectional view300eofFIG.3E, the semiconductor region110is centered on the rib104bbetween a lower slab104fand an upper slab104e. The upper slab104eextends over the semiconductor region110, and has a lower surface above an upper surface of the lower slab104f. The first protrusion104cextends from the upper slab104e, and the second protrusion104dextends from the lower slab104f. The first protrusion104cand the second protrusion104dhave upper surfaces that are level with one another.

The first-doping-type region112is in the upper slab104eand extends to an upper boundary of the semiconductor region110, and the second-doping-type region114is in the lower slab104fand extends to a lower boundary of the semiconductor region110. The first-doping-type region112, the semiconductor region110, and the second-doping-type region114together result in a PIN junction or the like.

In some embodiments, a fill layer302separates the upper slab104efrom the insulative layer106. In some embodiments, the fill layer302is or comprises silicon oxide and/or the like. In some embodiments, the upper slab104cis or comprises polysilicon and/or the like, whereas the lower slab104fis or comprises monocrystalline silicon and/or the like.

The semiconductor region110is directly between the first-doping-type region112and the second-doping-type region114in a center of the ribbed waveguide104. The greatest concentration of photons passes through the ribbed waveguide104at the position of the semiconductor region110, so an increase to the quantum efficiency of the photodetector101at this point results in a greater change in quantum efficiency. The semiconductor region110may be either implanted or deposited before formation of the upper slab104c.

As shown in the cross-sectional view300fofFIG.3F, the semiconductor region110extends vertically between the first-doping-type region112and the second-doping-type region114. The semiconductor region110extends through the center of the ribbed waveguide104, which coincide with the peak of the electromagnetic field. The depletion region formed at the PIN junction may have a greater cross-sectional area when the semiconductor region110extends vertically, thereby increasing the amount of charge carriers that may be generated due to the photoelectric effect.

As shown in the cross-sectional view300gofFIG.3G, the semiconductor region110extends horizontally between the first-doping-type region112and the second-doping-type region114, and also overlaps with the first-doping-type region112and the second-doping-type region114in first-type overlap region304and second-type overlap region306. This overlap results in the semiconductor region110covering a wider portion of the depletion region, increasing the efficiency of carrier generation over a larger area while still being positioned at the center of the ribbed waveguide104.

As shown in the cross-sectional view300hofFIG.3H, the semiconductor region110has a lower portion that extends vertically between the first-doping-type region112and the second-doping-type region114and an upper portion horizontally between the first-doping-type region112and the second-doping-type region114. This configuration has the semiconductor region110extending through a center of the ribbed waveguide104while further increasing the area of the semiconductor region110without overlapping with the first-doping-type region112or the second-doping-type region114. The increased area of the semiconductor region110due to the horizontal extension increases the area of the depletion region.

As shown in the cross-sectional view300iofFIG.3I, a second semiconductor region110bextends beneath a first semiconductor region110aand the PN junction113. The multiple semiconductor regions110a,110bcover portions of the ribbed waveguide104near the center while maintaining a direct PN junction113between the first-doping-type region112and the second-doping-type region114. The PN junction113extends vertically between the first-doping-type region112and the second-doping-type region114and horizontally between the first-doping-type region112and the second-doping-type region114, increasing the area of the depletion region near the center of the ribbed waveguide104.

As shown in the cross-sectional view300jofFIG.3J, the semiconductor region110covers portions of the lower slab104fextending from the first protrusion104cto the second protrusion104d. The first-doping-type region112extends into the rib104band over the second-doping-type region114, overlapping with the semiconductor region110at the first-type overlap regions304. The second-doping-type region114extends beneath the rib104b, overlapping with the semiconductor region110, resulting in the second-type overlap region306. The semiconductor region110has an extended width and a larger horizontal separation between the first-doping-type region112and the second-doping-type region114, which results in a larger depletion region and increased quantum efficiency across the extended depletion region.

FIG.4illustrates a cross-sectional view400of the optical module ofFIGS.1A and1Bin which the dimensions of the ribbed waveguide are described.

In some embodiments, the rib104bhas a first width W1 approximately between 300 and 2000 nanometers, approximately between 200 and 1500 nanometers, approximately between 400 and 2500 nanometers, or within another suitable range. In some embodiments, the first protrusion104chas a second width W2 approximately between 120 and 200 percent of the first width W1. In some embodiments, the second protrusion104dhas a third width W3 approximately between 120 and 200 percent of the first width W1. In some embodiments, a first portion of the slab104aextending between the first protrusion104cand the rib104bhas a fourth width W4 approximately between 100 and 200 percent of the first width W1. In some embodiments, a second portion of the slab104aextending between the second protrusion104dand the rib104bhas a fifth width W5 approximately between 100 and 200 percent of the first width W1. In some embodiments, a distance D1between the semiconductor region110and the second heavily doped region118is approximately between 35 and 99 percent of the fifth width W5. In some embodiments, the semiconductor region110has a sixth width W6 approximately between 100 and 350 percent of the first width W1.

In some embodiments, the first heavily doped region116has a seventh width W7 approximately between 150 and 230 percent of the first width W1. In some embodiments, the first heavily doped region116extends past sidewalls of the first protrusion104c. In some embodiments, the second heavily doped region118has an eighth width W8 approximately between 150 and 230 percent of the first width W1. In some embodiments, the second heavily doped region118extends past sidewalls of the second protrusion104d. In some embodiments, the first-doping-type region112outside of the first heavily doped region116has a ninth width W9 approximately between 50 and 100 percent of a combination of the first width W1, the second width W2, and the fourth width W4. In some embodiments, the second-doping-type region114outside of the second heavily doped region118has a tenth width W10 approximately between 50 and 100 percent of a combination of the first width W1, the second width W2, and the fourth width W4. The first-doping-type region112and the first heavily doped region116overlap by approximately 100 nanometers, 120 nanometers, 150 nanometers, or the like. The second-doping-type region114and the second heavily doped region118overlap by approximately 100 nanometers, 120 nanometers, 150 nanometers, or the like.

In some embodiments, the distance from an upper surface of the rib104bto a bottom surface of the slab104ahas a first height approximately between 50 and 1000 nanometers, approximately between 40 and 800 nanometers, approximately between 60 and 1200 nanometers, or within another suitable range. In some embodiments, the rib104bhas a second height H2approximately between 10 and 90 percent of the first height H1. In some embodiments, the semiconductor region has a third height H3approximately between 1 and 50 percent of the second height H2. In some embodiments, the slab104ahas a fourth height H4approximately between 10 and 90 percent of the first height H1. In some embodiments, the insulative layer106has a fifth height approximately between 2000 and 5000 nanometers, approximately between 1800 and 4500 nanometers, approximately between 2200 and 5500 nanometers, or within another suitable range.

FIG.5illustrates a top down view500of an array of photodetectors.

FIG.5shows a plurality of optical couplers202a-202dcoupled to an array of photodetectors101a-101d. The photodetectors101a-101dare coupled to a plurality of first pads124a-124d, a plurality of second pads126a-126d, and a plurality of third pads128a-128d. The array of photodetectors101a-101dreceived photonic signals and convert the photonic signals into electric signals. The electric signals are separately delivered to an electronic circuit through the plurality of first pads124a-124d, the plurality of second pads126a-126d, and the plurality of third pads128a-128d. The photodetectors101a-101dmay, for example, each be as the photodetector101is described in any one or combination of the foregoing embodiments.

FIGS.6A-6Billustrate top layout views600a-600bof an array of photodetectors integrated into a photonic circuit.

FIG.6Ashows a plurality of optical couplers202a-202dcoupled to an array of photodetectors101a-101dsurrounding a central region601. The photodetectors101a-101dcomprise individual first protrusions104/104c, second protrusions104/104d, and semiconductor regions110a-110d. The photodetectors101a-101dmay, for example, each be as the photodetector101is described in any one or combination of the foregoing embodiments.

In some embodiments, the ribbed waveguides104extending through the array of photodetectors101a-101dterminate at the central region601. The photonic signals that pass through the array of photodetectors101a-101dmay, for example, be absorbed in the central region601. In some embodiments, the central region601has a semiconductor cap (not shown) that is configured to absorb the remainder of the photonic signals in the central region601.

The central region601may have a polygonal shape (e.g., a diamond shape, a pentagon shape, etc.). The photodetectors101a-101dare evenly spaced around the central region601. In some embodiments, the photodetectors101a-101dare coupled to the vertices of the polygonal shape. By coupling the array of photodetectors101a-101dto the central region601, the area normally used to absorb the photonic signals output from individual photodetectors in a column array is reduced, increasing the space efficiency of the design. Additionally, embodiments comprising one or more additional photodetectors coupled to the central region601will not (or will minimally) increase the area taken by the array, increasing flexibility in the number of photodetectors used and the scalability of the design.

As shown inFIG.6B, in some embodiments, the individual first protrusions104/104cand the individual second protrusions104/104dare connected to a single first pad124and a single second pad126, respectively. In further embodiments, individual semiconductor regions110a-110dare coupled to a single third pad128.

Amplitude modulation or frequency modulation may, for example, be used to encode the information from the individual photodetectors101a-101dinto one or more digital signals. In some embodiments, a clock signal is used to add delays to individual output signals from the individual photodetectors101a-101d, such that each photodetector has a different delay amount. In some embodiments, modulators602a-602dalter the amplitudes and/or frequencies of the photonic signals130to be different from one another. The amplitudes of the photonic signals130are proportionate to the output current of the photodetectors101a-101d, as the number of carriers generated is proportional to the number of photons entering the depletion region. Because the individual first protrusions104care coupled to the first pad124and because the individual second protrusions104dare coupled to the second pad126, the electrical signals from the array of photodetectors101a-101dmay add and/or combine into an output signal.

In some embodiments, the modulators602a-602dmay be coupled to a fourth pad604. An electric signal from the fourth pad604may be used to control the modulators602a-602d. In some embodiments, attenuators606may be coupled to the ribbed waveguides104to further control the amplitude of the photonic signals130. The attenuators606may be controlled by signals received from a fifth pad608. In some embodiments, the positioning of the plurality of pads124,126,128,604, and608may vary from what is shown inFIG.6.

Because the individual photodetectors101a-101dshare the same set of pads, space efficiency is enhanced. Less area is wasted on pads. Further, the pitch between photodetectors may be reduced. Accordingly, there may be more photodetectors per given area than would otherwise be possible (e.g., with a layout like that ofFIG.5).

With reference toFIGS.7-20, a series of views of some embodiments of a method for forming an integrated photodetector with a semiconductor region is provided. AlthoughFIGS.7to20are described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

As illustrated by a cross-sectional view700ofFIG.7, a SOI substrate is provided or otherwise formed. The SOI substrate comprises a handle substrate102, an insulator layer106overlying the handle substrate102, and a semiconductor layer702overlying the insulator layer106. The semiconductor layer702is undoped or otherwise lightly doped. The light doping may, for example, be a doping concentration that is less than about 5e16 atoms/cm3or some other suitable value.

As illustrated by a cross-sectional view800ofFIG.8, a first masking layer802(e.g., a photoresist) is deposited over the semiconductor layer702and patterned. The patterning may, for example, be performed by a photolithography or some other suitable patterning process.

As illustrated by a cross-sectional view900ofFIG.9, an etching process902is performed, etching first openings904in the semiconductor layer702according to the first masking layer802. The etching process may, for example, be a plasma dry etch or some other suitable patterning process. The etching process removes portions of the semiconductor layer702surrounding the ribbed waveguide104(seeFIG.1A) formed hereafter. The first masking layer802is subsequently removed.

As illustrated by a cross-sectional view1000ofFIG.10, the first openings904surrounding the semiconductor layer702are filled with a first dielectric layer108a. In some embodiments, the first dielectric layer108ais formed by depositing a dielectric material over the semiconductor layer702, then subsequently performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) to remove portions of the dielectric material above the semiconductor layer702.

As illustrated by a cross-sectional view1100ofFIG.11, a second masking layer1102(e.g., a photoresist) is deposited over the semiconductor layer702and patterned. The patterning may, for example, be performed by a photolithography or some other suitable patterning process.

As illustrated by a cross-sectional view1200ofFIG.12, an etching process1202is performed, etching second openings1204in the semiconductor layer702(seeFIG.11) according to the second masking layer1102. The etching process may, for example, be a plasma dry etch or some other suitable patterning process. The etching process exposes inner sidewalls of the ribbed waveguide104. The second masking layer1102is subsequently removed.

As illustrated by a cross-sectional view1300ofFIG.13, the ribbed waveguide104is doped, forming the first-doping-type region112, the second-doping-type region114, the first heavily doped region116, and the second heavily doped region118. In some embodiments, the semiconductor region110(seeFIGS.3A,3B,3D,3F,3G,3H,3I, and3J) is also formed by doping the ribbed waveguide104. The doping of the ribbed waveguide104may be performed by selective ion implantation with a mask in place or by some other suitable doping process. The mask may, for example, be a photoresist mask or a hard mask.

As illustrated by a cross-sectional view1400ofFIG.14, a second dielectric layer108bis formed over the ribbed waveguide104. In some embodiments, the second dielectric layer108bis or comprises a dielectric material such as silicon oxide (SiO2) or the like. In some embodiments, the second dielectric layer is formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other suitable deposition process, or a combination of the foregoing.

As illustrated by a cross-sectional view1500ofFIG.15, a third masking layer1502(e.g., a photoresist) is deposited over the second dielectric layer108band patterned. The patterning may, for example, be performed by a photolithography or some other suitable patterning process.

As illustrated by a cross-sectional view1600ofFIG.16, an etching process1602is performed, etching third openings1604in the second dielectric layer108baccording to the third masking layer1502. The etching process may, for example, be a plasma dry etch or some other suitable patterning process. The etching process exposes an upper surface of the rib104bof the ribbed waveguide104. The second masking layer1102is subsequently removed.

As illustrated by a cross-sectional view1700ofFIG.17, in some embodiments, a second semiconductor layer1702is deposited over the ribbed waveguide104and the second dielectric layer108b. The second semiconductor layer1702is or comprises a second semiconductor material, such as germanium (Ge), or a III-V semiconductor material, such as gallium arsenide (GaAs), indium arsenide (InAs), gallium nitride (GaN), indium phosphide (InP), or the like. The second semiconductor layer1702fills the third opening1604.

As illustrated by a cross-sectional view1800ofFIG.18, portions of the second semiconductor layer1702(seeFIG.17) above the second dielectric layer108bare removed, leaving the semiconductor region110on the ribbed waveguide104. In some embodiments, the portions are removed using a planarization process (e.g., a CMP process). The semiconductor region110is positioned directly above the rib104band the PN junction113,

As illustrated by a cross-sectional view1900ofFIG.19, a third dielectric layer108cis formed over the second dielectric layer108band the semiconductor region110. Contacts120are subsequently formed. The contacts120extend through a third dielectric layer108cand the second dielectric layer108b, and are coupled to the semiconductor region110, the first protrusion104c, and the second protrusion104d. In embodiments where the semiconductor region110is implanted (seeFIGS.3B,3D,3F,3G,3H,3I, and3J) instead of deposited (seeFIGS.3A,3C,3E), the contacts120are either coupled to the implanted semiconductor region110in the ribbed waveguide104or are not coupled to the ribbed waveguide104beyond the first and second protrusions104c.104d.

As illustrated by a cross-sectional view2000ofFIG.20, a wire layer122is formed over the contacts120is a fourth dielectric layer108d. The wire layer122is coupled to the contacts120and carries the electrical signal from the photodetector101to the first and second pads124,126(seeFIG.1B).

With reference toFIG.21, a block diagram2100of some embodiments of the method ofFIGS.7-20is provided.

At2102, a semiconductor layer is patterned to form a first waveguide on a substrate. See, for example,FIGS.11and12.

At2104, the first waveguide is doped to form a first PN junction. See, for example,FIG.13.

At2106, a first semiconductor region is formed on the first PN junction using one or both of an implantation process and a deposition process, wherein the semiconductor layer comprises a first semiconductor material and the first semiconductor region comprises a second semiconductor material different from the first semiconductor material. See, for example,FIGS.16-18.

In some embodiments, the present disclosure provides an optical module, including: a waveguide including a rib and further including a first protrusion and a second protrusion respectively on opposite sides of the rib; a photodetector comprising a PN junction in the rib; and a semiconductor region on the PN junction, where the waveguide comprises a first semiconductor material, and the semiconductor region comprises a second semiconductor material different from the first semiconductor material.

In some embodiments, the present disclosure provides another optical module, including: waveguides arranged around and ending at a central region; photodetectors integrated into the waveguides around the central region; a first pad coupled to N-type regions of the photodetectors; and a second pad coupled to P-type regions of the photodetectors.

In some embodiments, the present disclosure provides a method for forming an optical module, including: patterning a semiconductor layer to form a first waveguide in the semiconductor layer; doping the first waveguide to form a first PN junction; forming a first semiconductor region on the first PN junction using one of an implantation process or a deposition process, wherein the semiconductor layer comprises a first semiconductor material and the first semiconductor region comprises a second semiconductor material different from the first semiconductor material.