Mask design and OPC for device manufacture

Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.

TECHNICAL FIELD

This disclosure relates generally to the field of lithographic masks for the manufacture of microelectronic devices, and more particularly to design of a set of masks to be successively imaged to print a target pattern in a single level of the device (e.g., double patterning).

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips.

A photolithographic mask comprises geometric patterns of polygons corresponding to the circuit components to be integrated onto a wafer. The patterns used to create such masks are typically generated utilizing CAD (computer-aided design) programs via an EDA (electronic design automation) process. Most CAD programs follow a set of predetermined design rules in order to position the polygons to create functional masks. These rules are set by manufacturing process and circuit design limitations. For example, design rules define the space tolerance between circuit components (such as gates, capacitors, etc.) or interconnect lines to ensure a high device yield. The design rule limitations are typically referred to as “critical dimensions” (CD). A CD of a circuit can be defined as the smallest length of a line or trench or the smallest space between two lines or two trenches. Thus, the CD determines the overall size and density of the designed circuit.

Recently device scaling has outpaced the development of lithography systems (e.g., scanners). Patterning interconnect geometries, for example, at the 22 nm node, using a 193 nm wavelength scanner may require a nesting of every narrow drawn line to force a circuit design to an optimal pitch (e.g., having a design-rule minimum space CD for every minimum CD line) with several compliance features and a drawing of large end-to-ends in an effort to reduce the mask error enhancement factor (MEEF) of the lithographic process to an acceptable level for the lithographic technology node. The resulting increase in circuit footprint can, however, negate the benefit of scaling the CD down to the 22 nm technology node.

DETAILED DESCRIPTION

Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Further described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.

The multiple patterning mask design embodiments described herein generate first and second masks which are to be successively printed on a substrate at a first masking level and a second masking level, respectively. Generally, the first mask pattern is synthesized through an addition of a sacrificial enabling pattern, at least some of which is to be printed onto the substrate by the lithography system at a first masking level, to a drawn design target pattern and thereby approximate a grating pattern. This grating pattern is then used to create a first level mask pattern that includes the target pattern, as a subset of the grating pattern. The second mask is generated based on at least the enabling pattern to eliminate, from the printed first level, the sacrificial enabling pattern. As such, it should be appreciated that the double patterning described herein is distinct from conventional techniques which decompose a target pattern into pattern subsets which are printed at separate levels. Rather, embodiments herein print the entire target pattern as well as the sacrificial enabling pattern in a single patterning level and then use the second patterning level to remove the sacrificial enabling pattern from a substrate.

Thus, rather than seeking to reduce a target pattern's density through the use of multiple mask imaging, embodiments herein leverage a second patterning operation to enable the imaging performance for a target pattern to be improved (e.g., by a increasing a regularity of edges) through the printing of sacrificial features onto the substrate. Absent the second patterning operation, such enabling features would not be sacrificial and the device design rules would need to be modified to incorporate permanent patterning artifacts. However, as described further elsewhere herein, embodiments of the present invention require little, if any, modification of device design rules.

As one of ordinary skill in the art will appreciate, the multiple pattern mask designs described herein may be utilized to print a double pattern on a substrate using a wide variety of photolithographic patterning techniques and systems. As one example,FIG. 1depicts a “grating and plug” double patterning method100.FIG. 1illustrates selected operations of the grating and plug double patterning method100along with an exemplary cross-section representation of a substrate as it is processed through the selected operations. The grating and plug double patterning method100begins at operation110with coating a wafer111with a first layer of photoresist112. Any conventional coating process and photoresist (negative or positive) known in the art may be employed.

At operation115, a first mask is printed as the first patterning level to expose a trench region113of the first photoresist layer112. In the exemplary embodiment, the first level pattern approximates a grating and includes a target pattern comprising bidirectional polygons, as discussed in detail elsewhere herein. Any lithography system known in the art may be used to image the first patterning level on the wafer111, such as but not limited to, conventional UV-illuminated steppers or scanners employing a 193 nm wavelength radiation source. In alternative embodiments, shorter wavelengths (e.g., 157 nm or an extreme ultraviolet (EUV)) may also be employed. At operation120, the first photoresist layer112is developed and/or baked to form the first level pattern topography. The trench121is formed in the first photo resist layer112having a longest dimension L1longer than the target pattern with a shortest dimension (CD) equal to a fraction of the imaging wavelength λ/x where x is, for example, at least 4. As discussed further elsewhere herein, features having a smaller CD (and resulting in a higher MEEF) have been subsumed into the grating approximation. At operation130, the wafer111is coated with a second layer of photoresist131, substantially filling the patterned topography (e.g., trenches) present in the first layer of photoresist112. Depending on the embodiment, the second layer of photoresist131may be of the same or different composition as that employed for the first layer of photoresist112.

At operation140, a second mask is printed as the second patterning level to expose a portion141of the second photoresist layer131. In the exemplary embodiment, the second level pattern reduces the grating printed at the first pattern layer to the target pattern, as further discussed elsewhere herein. In the grating and plug double patterning method100where the first level pattern is to form trench regions113, the second level pattern “plugs” the portion of the trench regions113which do not correspond to a target pattern. Prior to the operation140, the first photoresist layer112is rendered non-photosensitive using various techniques, such as a hard bake or chemical treatment. Any lithography system known in the art may be employed at operation140, such as but not limited to, UV-based steppers or scanners employing 193 nm, 157 nm or an extreme ultraviolet (EUV) wavelength radiation source. In the preferred embodiment, the wavelength employed at operation140is the same as that employed at operation115.

At operation150the second photoresist layer131is developed and/or baked to form the target pattern with the remaining portions of both the first and second resist layers112,131. As shown, the second level pattern has a trench151with a longest length L2that is now to be equal to the polygon target. With the shortened length (minimum end-to-ends are now present), the trench151is to retain the shortest length CD equal to that which was printed at the first level (e.g., a fraction of the imaging wavelength). Yet, because this CD and end-to-end spacing is a result of overlap between the first and second resist layer112,131, the second level patterning may also have a low MEEF (e.g., edges having dimensions greater than those of the trench151). Following operation150, the grating and plug double patterning method100is substantially complete and the wafer may be further processed as known in the art (etch, etc.).

While the exemplary grating and plug double patterning method100illustrates one application whereby trenches formed in the first level patterning are subsequently filled and partially reopened, the multiple patterning techniques described herein may also be applied to double patterning techniques employing a single layer of resist. For example, the first mask level described herein may also be applied to print a grating approximation comprising unexposed lines which include both the target pattern and the sacrificial enabling pattern and the second mask level described may also be applied to remove the sacrificial unexposed lines to arrive at the target pattern.

FIG. 2illustrates a mask design and generation method200for composing polygons of a first mask level and a second mask level into a target pattern of polygons to be formed on a substrate by sequentially printing the first mask level and the second mask level. Method200begins at operation210with receipt of a drawn design layout, for example as generated by a layout description language such as GDS-II or OASIS.FIG. 2also illustrates an exemplary target pattern211representing a portion of an interconnect design, for example, as received from an IC designer, which is to be reproduced onto a level of a semiconductor wafer. The target pattern211includes the polygons212which are eventually to be faithfully imaged onto the wafer at the designed dimensions by lithographic printing. In an embodiment, the target pattern211is bidirectional, including polygons having a longest length in two directions.

FIG. 3Afurther illustrates an exemplary target pattern311, as drawn. As shown, the polygon312has a longest length L along the x-dimension and a shortest length, CD1along the y-dimension. The polygon313has a longest length along the y-dimension and a shortest length along the x-dimension such that the target pattern311is bidirectional. In the exemplary embodiment depicted inFIG. 3A, the target pattern311further includes polygon314with segments which run along both the x and y dimensions.

Returning toFIG. 2, at operation215a sacrificial enabling pattern is synthesized, based on the target pattern. The sacrificial enabling pattern is to be added to the target pattern (e.g., with a Boolean OR operation) to improve imaging performance of the first mask level for a given lithographic tool beyond what would be achieved with a mask including only the target pattern. For example, a sacrificial enabling pattern216containing a single polygon is generated, to have a particular position, shape and size based on the input target pattern211. Although a number of rules and objectives may control generation of the sacrificial enabling pattern, in one embodiment, the generation of the enabling pattern216is performed with an objective function that drives the target pattern211to increase a regularity of edges toward an approximation of a diffraction grating. In a particular embodiment, at operation215, a plurality of sacrificial enabling polygons are generated which result in both the grating pattern (including the sacrificial polygons) and the second level pattern used to remove the sacrificial polygons from the grating pattern having a mask error enhancement factor (MEEF) below that of the target pattern. Within this bound, sacrificial polygons may be synthesized to drive an arbitrary target pattern to converge at a grating pattern which can be imaged and then “cleaned up” with a second patterning more easily than directly imaging only the target pattern.

At operation220, a Boolean OR operation is performed on the drawn target pattern211and the sacrificial enabling pattern216to generate a synthesized grating pattern221. As further depicted inFIG. 3B, a synthesized diffraction grating pattern321is a Boolean OR of the drawn target pattern311ofFIG. 3Aand a sacrificial enabling pattern316(e.g., generated at operation215ofFIG. 2). In one particular embodiment, the enclosed polygons are to form open regions in a mask with the surrounding region to be lower transmittance (i.e., chrome). The synthesized diffraction grating pattern321includes polygons having a minimum pitch resolvable by the optical projection system, PitchG, and defines a shortest length of all polygons in one of the two mask dimensions (e.g., CD1). It will be appreciated by those of ordinary skill in the art that a diffraction grating pattern can be printed with a minimum pitch smaller than is possible for a non-periodic pattern. It is therefore possible to print the target polygons312, as embedded within a grating pattern, with a reduced CD1(or with a reduced spacing, S1, along the y-dimension between adjacent polygons312).

In one embodiment, as illustrated inFIG. 3B, the sacrificial enabling pattern316extends a first length of the target polygon312with an enabling polygon317has a shortest length (CD) that is no greater than that of the target polygon312. As shown, the enabling polygon317and the target polygon312are drawn to substantially the same critical dimension (CD1). Extension of the target polygon312with the enabling polygon317serves to improve the edge regularity or periodicity of the synthesized grating pattern321by extending the longest edge of the target polygon312to be adjacent to the entirety of the longest edge of the target polygon327.

In another embodiment, also illustrated inFIG. 3B, an enabling polygon318joins the target polygon312to an adjacent target polygon319to eliminate the end-to-end space320present in the drawn target pattern311(FIG. 3A). With the joining of adjacent target polygons, the sacrificial enabling pattern316may greatly reduce the MEEF of the first pattern level, particularly where the end-to-end space320is a sized at the design rule minimum space. This elimination of minimum end-to-end spaces, along with the ability to print grating structures at a reduced pitch, is an important aspect of the double patterning methods described herein.

In further embodiments, end-to-end spaces between target polygon having different CDs are also advantageously eliminated. Enabling polygon325, for example, eliminates an end-to-end space between the target polygon326and the target polygon327even though the target polygon326has a larger CD than the target polygon327and is also offset from the target polygon327in the y-dimension. Nevertheless, a diffraction grating is approximated by drawing the enabling polygon325with a first length to join the target polygons326,327and with a second length equal to the y-dimension overlap between the target polygons326,327. As such, the shortest length of the enabling polygon325is smaller than that of either the target polygons326,327. For particular embodiments where the shortest length of the polygon327is equal to the design rule minimum dimension (e.g., CD1), the shortest drawn length of the enabling polygon325is below the minimum dimension design rule for the drawn target pattern311. Such sub-design rule connectors are created to eliminate pullback concerns due to high MEEF as well as eliminate mask manufacturing inspection constraints. In particular embodiments, sub-design rule connectors like the enabling polygon325are sized during a subsequent correction step (e.g., OPC operation225discussed elsewhere herein) to the minimum size required at mask manufacture. Because the enabling polygon325will likely be sub-resolution when imaged onto a wafer (e.g., operation115ofFIG. 1), the enabling polygon325patterns marginally, if at all, and is never the less cleaned out in the subsequent level two patterning (e.g., operation140ofFIG. 1).

In another embodiment a sacrificial enabling pattern is synthesized to nest a target polygon with one or more enabling polygons having an edge positioned adjacent to the longest edge of the target polygon. As an example, inFIG. 3Ba target polygon330is nested with the enabling polygon331having an edge adjacent to the longest edge of the target polygon330. Such nesting may allow the target polygon330to print with the reduced minimum dimension, CD1, because the synthesized grating pattern321is extended past the target polygon330. In another embodiment, an enabling polygon joins less than all of a longest length of a first target polygon to a second target polygon to provide a continuous edge that is proximate to a longest edge of a third target polygon. For example, inFIG. 3B, a portion of the longest edge of the target polygon332is joined to a portion of the longest edge of the target polygon333by the enabling polygon334. The shortest edges of the target polygons332,333combine with an edge of the enabling polygon334to form a continuous edge of the synthesized grating pattern321. This continuous edge, in turn, benefits the imaging of the adjacent target polygon330, which is particularly advantageous where the target polygon330is a narrow feature having a shortest edge drawn to a minimum dimension design rule for the target pattern (e.g., CD1).

Returning toFIG. 2, with the grating pattern221synthesized, the method200proceeds to correct the drawn grating at the OPC operation225. The OPC performed is to compute and adjust extension of edges of the opaque/non-transparent (e.g., chrome), very low transmittance (e.g., 6% in embedded phase shift masks), etc. areas of a mask that will be used to print the synthesized grating pattern221. The OPC treatment at operation225may include the addition of assist features227(i.e., scatter bars), serif structures, and the like to the synthesized grating pattern221to generate a corrected grating pattern226.

At operation230, a synthesized second level (plug) pattern231is generated from the synthesized enabling pattern216. As with the synthesized enabling pattern216, the plug pattern231does not form a part of the electrically active set of polygons and so polygons comprising the plug pattern231are therefore also referred to herein as “synthesized.” In one embodiment, as illustrated inFIG. 2, the plug pattern is synthesized at operation230to fully cover the sacrificial enabling polygons while maintaining a mask error enhancement factor (MEEF) below that of the target pattern. In a further embodiment, the polygons of the synthesized enabling pattern216are synthesized to overlap the drawn sacrificial enabling polygons.FIG. 3Cfurther depicts an exemplary plug pattern351generated to remove the sacrificial enabling patterns316from the synthesized grating pattern321. In one particular embodiment, the polygons352form high transmittance regions in a mask with the surrounding regions353being opaque. One of skill in the art will appreciate however, that the methods described herein may be adapted to utilize a plug pattern351having an opposite polarity as that depicted in the exemplary embodiment depicted inFIG. 3C.

FIG. 3Ddepicts the plug pattern351overlayed on the synthesized grating pattern321to illustrate how the two mask levels are to compose the target pattern311. In one particular embodiment where the enclosed polygons312are to form open regions in the first level mask corresponding to the target pattern, the enclosed polygons322are to form open regions in the first level mask corresponding to the sacrificial enabling structures, and the enclosed polygons352are to form closed regions in the second level mask, the double pattern310results in a trench in photoresist rendering the target pattern. Such an embodiment is advantageous for a metal interconnect level, for example.

As shown inFIG. 3D, the plug pattern351essentially fully covers the sacrificial enabling pattern316without covering any substantial portion of the target pattern311. The plug pattern351, although not complex, removes the sacrificial enabling pattern316without generating a plug polygon that touches a longest edge of a target polygon having a shortest edge drawn to a minimum dimension design rule (CD1) for the target pattern311. Notably, the plug pattern351need only touch longest edges of target polygons oriented along the y-axis. Scumming concerns may be reduced with polygons oriented along the y-axis being less narrow than those oriented along the x-axis of the grating.

At operation240, an OPC process is performed on the drawn plug pattern. Because the double patterning mask design has stringent overlay requirements, in one embodiment, the OPC process performed at operation240is based on a predicted grating pattern contour251. The contour251may be generated by a Constant Threshold Model, or a Variable Threshold Resist (VTR) model. For such embodiments, the OPC performed on the second level pattern is dependent on the OPC performed on the first level patterning. Generally, the OPC performed at operation240takes, as an input, the output of the first level (grating pattern) OPC and generates the predicted grating pattern contour251.

At operation250, the expected or predicted grating pattern contour251is generated from the corrected grating pattern221. In a particular embodiment, the grating pattern contour251is a model prediction of the grating pattern's imaging performance. The model prediction may be based on one or more statistical and phenomenological models characterizing a lithographic process that is to be used to print the grating pattern (e.g., at operation115ofFIG. 1), such as, but not limited to, diffractive, diffusive and fluidic mechanics.

In the exemplary embodiment depicted inFIG. 2, the model predicted grating pattern contour251is utilized in the correction of the second level pattern (e.g., “plug” pattern) to bound a sizing of the plug pattern at operation260. It should be noted the exemplary plug OPC embodiments herein avoid a rule-based approach to pre-compensating the plug pattern for potential grating upsizing or grating pattern contour shifts because such rule-based approaches may require significantly more die-area.FIG. 4Aillustrates a layout view of a portion411of the target pattern311depicted inFIG. 3Awith a corresponding portion421of the synthesized grating pattern321is further shown inFIG. 4B.FIG. 4Cillustrates a predicted grating contour451for the grating pattern portion421. The grating contour may deviate substantially from the synthesized grating pattern, as shown with contour regions452and453for example.

FIG. 4Dillustrates a plug pattern431synthesized to fully cover the sacrificial enabling polygons (as synthesized).FIG. 4Eillustrates a predicted plug contour471generated in accordance with an embodiment of the present invention which corrects the plug pattern431based on the predicted grating pattern contour451. As such, the plug OPC process is made aware of where the grating does not converge exactly to the synthesized grating target so that the plug grows out to meet a specification for coverage or overlap of the sacrificial enabling structures. Following this paradigm, the second level OPC described herein avoids forming a bridge472between two adjacent target structures or an artifact473of the sacrificial enabling pattern that may have formed had the plug pattern431not been corrected in a manner “aware” of the predicted grating contour451.

FIG. 5illustrates a flow diagram depicting selected operations in the OPC process500performed at operation240, in accordance with an embodiment. Generally, the OPC process500is to determine a distance between the plug contour and grating contour, and then assign a corresponding displacement to the synthesized plug pattern to ensure the plug contour encloses the sacrificial grating contour. As shown, the second-level OPC process begins at operation510by reading in the OPC output for the grating pattern (first level pattern). The grating contour is then generated at operation520. At operation512, the synthesized plug pattern (second level pattern) is read in. In the exemplary embodiment, polygons of the synthesized plug pattern are segmented at operation522. For example, each polygon may be segmented into n segments where the number n may depend on the complexity of the plug polygon. Beginning with a first segment of a first plug polygon, a distance between the nearest plug contour and the nearest grating contour is determined. In the exemplary embodiment shown inFIG. 6, an outside distance Dout, as measured externally from the drawn plug edge to the nearest the grating contour451, is determined. In a further embodiment, an inside distance Din, as measured internally from the drawn plug edge to the nearest the grating contour451, is also determined for each segment. The inside and outside distances are then used to bound and drive a displacement of the plug segment from its drawn position.

Returning toFIG. 5, at operation513, the drawn target pattern and synthesized grating pattern is read in. At operation530, an outside distance between the plug segment and the nearest drawn target polygon edge is determined so that the plug segment is not displaced over a target polygon in the effort to expand the plug polygon edges to meet a nearest grating contour451. At operation540, the plug polygon segment is displaced toward the nearest grating contour without covering a drawn target pattern, based on the distances determined at operations525and530which define a relationship (inside/outside/collinear) between the drawn plug segment and both the drawn target and the grating contour.

One or more objective functions may be applied at operation540. For example, a segment may be displaced to maintain a minimum distance between the segment and a target pattern polygon edge. In an alternative embodiment, a plug segment is displaced to be outside of the sacrificial enabling pattern if the determined distances indicate the nearest grating contour is outside of the sacrificial enabling pattern and the target pattern by more than a threshold tolerance. Such a threshold tolerance may be based on an empirically determined lithographic process tolerance. Segment displacement proceeds iteratively until all segments of a plug polygon have meet the objective function and the OPC method500completes when a similar sizing algorithm has been executed for all plug polygons.

In a further embodiment, the second level OPC is based on a model predicted pattern contour which is derived from a second level resist profile model as a function of underlying topography (e.g., topography resulting from the first level pattern). A resist profile is an output of a simulation of the chemically altered portion of the resist layer corresponding to the spatial distribution of a radiation intensity through the thickness of the resist layer as would be formed by a patterned mask. Because the second level photoresist is applied over the first level pattern, topographical effects are much more significant than for the first level photoresist which is applied to a more ideally planar substrate surface as typically encountered in contemporary photolithography.

The modeled resist profile embodiments described herein are three to four orders of magnitude faster than a rigorous computation of the radiation intensity which may be performed with a 3D field solver using a finite-difference time-domain (FTD) method combined with a photoresist chemistry solver. As such the modeled resist profile embodiments described herein are full-chip capable. Rigorous methods are prohibitively slow for chip-scale OPC due to the enormous number of image calculations that OPC algorithms must carry out. For OPC, multiple intensity calculations are made to characterize the image rendering any given one of the hundreds of millions of features in a mask level, and pattern adjustments are also typically iterated to accommodate the interaction of each adjusted feature with its neighbors.

In addition to the modeled resist profile embodiments described herein being very fast, because they are physics-based rather than rule-based they may be applied to arbitrary polygon shapes and arbitrary topographies. In contrast, rule-based models or models which adopt empirically derived topography rules that don't otherwise account for topography are inherently limited to a finite set of tabulated correction factors. Furthermore, because bulk intensity and photoresist development models contain many fitting parameters, which do not correspond to measurable physical phenomena relating to topography, they are difficult to adjust to accommodate topographic effects.

While the photoresist profile model is described herein for the specific application of multi-level patterning process such as illustrated inFIG. 1, it should be appreciated that the methodology is readily applicable to modeling of any resist profile where the substrate is inhomogeneous. For example, the above two component model is suitable for conditions where no topographic feature is present under a photoresist to be modeled, but there is a variation in the composition of the underlying materials across a given area of photoresist which present a different index contrast that may impact the resist profile. As another example, underlying topography may impact the resist profile even where a single layer of photoresist is applied because the substrate may not be completely planar (e.g., after short recess etches, cleans, etc.). In this situation too, the photoresist profile model described herein advantageously improves an OPC calculation that assumes planarity or is limited to an application of an empirically-based topographic rule set. As such, the resist profiling embodiments described herein are not limited to multiple-patterning processes.

Generally, the topography dependent resist profile model employs a two-step approach. First, a base intensity is computed as a function of both a first intensity modeled for a first homogenous substrate and a second intensity modeled for a second homogenous substrate. Second, the base intensity is corrected for edge effects on each of scattering and diffusion. As such, the resist profile is model predicted in a manner which accounts for topography based on two distinct spaces. The first space, optical scattering, is affected by index contrast at the interface between the photoresist and the topographic material (e.g., first level photoresist feature). The second space, chemical diffusion, is affected by the physical barriers presented by the surface of the topographic material (e.g., first level photoresist feature).

Both optical scattering and diffusion effects are modeled as edge-driven perturbations from the nominal bulk value which are correlated to the known location of the underlying topographic edges. In the exemplary double-patterning embodiment, these underlying topographic edges are known from a model of the first level pattern contour and may be input in to the second level OPC algorithm to model the second level photoresist profile. In alternative embodiments, because substrate inhomogeneity is usually a direct result of a previously lithographic operation, the relevant prior layer pattern contour may be used to identify the edge locations for determining the subsequent photoresist profile.

It has been found that separating the model into a diffusion and scattering correction function is accurate, as compared to a rigorous, method and yet fast enough for full-chip OPC applications. Furthermore, bifurcating the profile computation into the above two steps enables the model to be generated very quickly because only the first step need be calculated for evaluation points sufficiently far from an edge of a topographic feature. Also, in treating each of these effects separately, physically meaningful fitting parameters may be included in each correction function to tune a resist profile model to the particular lithographic process employed in wafer manufacture.

FIG. 7Aillustrates a flow diagram of an exemplary method700for modeling a resist profile in the presence of topography. The method700begins at operation701with reading in the first level pattern from which edge locations may be determined using any technique known in the art for such purposes. In one embodiment, the model-predicted grating pattern contour251(FIG. 2) is read in at operation701. At operation702, the uncorrected second level pattern is read in at a first iteration of operation701or a second level pattern as corrected by a previous iteration of method700is read in for a subsequent iteration. At operation750, the resist profile for the second level pattern (e.g., plug pattern231ofFIG. 2) is computed based on the first level pattern.

Operation750is expanded inFIG. 7B. Referring toFIG. 7B, at operations755and756, a first and second blur intensity is computed. Each of the first and second blur intensities may be computed at each evaluation point using conventional techniques known in the art for a homogeneous substrate. In one embodiment, a commercially available resist profile modeling package is utilized to first generate the first blur intensity and then generate the second blur intensity.

The first blur intensity is computed from a model that assumes the substrate is a planar homogeneous film of a first type (e.g., the first level grating pattern photo resist). The second blur intensity is then computed from a model that assumes the substrate is a planar homogeneous film of a second type which is present where the underlying topographic feature is absent (e.g., the substrate material where upon which the grating pattern is disposed). At operation760a base intensity as a function of each of the first and second blur intensities is computed. The “mixture” of blur intensities calculated at operation760represents a nominal intensity for the inhomogeneous substrate present at the second patterning level where each of the first and second substrate materials are disposed below different areas of the first photoresist layer. In one embodiment, the base intensity is a sum of the first and second intensities scaled based on the topographic pattern. In the exemplary embodiment:
Ibase(x)=I1(x)C1(x)+I2(x)(1−C1(x)),  (1)
where Ibaseis the base intensity computed as a function of the first blur intensity (I1) obtained based on top of the first substrate (grating level), the second blur intensity (I2) obtained based on the second substrate (with no grating present) and the convolution (C1) of the topography layer (e.g., grating represented by one or more rectangular functions) and the Gaussian function.

With the base intensity computed, the method700proceeds to operation765to apply an optical scattering correction function, Fscatto the base intensity. In the exemplary embodiment, operation765determines a multiple of the base intensity and the optical scattering correction function at the evaluation point:
Ibase(|Fscat(d)|)  (2)

The optical scattering correction is a function of a distance, d, between the evaluation point and the topographic edge for which the scattering is attributed (Fscat(d)) and generally represents a perturbation of the base intensity induced by the index contrast of the topographic edge at the evaluation point. The optical scattering correction function may take any number of forms, depending on the fitting parameters utilized. In an exemplary embodiment, the optical scattering correction function is an exponential function. However, one of skill in the art may determine other suitable functions (square, polynomial, etc.) by fitting rigorous field computation results to various functions scaling the base intensity.

In the exemplary embodiment, at operation770, a diffusion scattering correction function, Fdiffis applied to the base intensity. Like the optical scattering correction function, the diffusion correction function may take any number of forms, depending on the fitting parameters utilized. In an exemplary embodiment, the diffusion scattering correction function is a sinusoidal function. However, one of skill in the art may determine other suitable functions (exponential, polynomial, etc.) by quantifying a photoresist chemistry solver's modification of an output from rigorous field computation output and fitting that quantification to various functions scaling the base intensity.

In the exemplary embodiment, the diffusion correction factor is applied to the base intensity in dimensional components to arrive the diffusion perturbation resulting from an edge. Generally, to model how an exposure chemistry gradient would deviant from the nominal case (no topography) one needs to know where a gradient of the second level exposure chemistry coincides with an edge of a topographic feature. At that location, the nominal diffusion function is hindered by the presence of the edge surface/interface. In one embodiment therefore, a first diffusion perturbation component is determined at operation770based on the diffusion correction function, a slope of the base intensity in a first dimension, and a slope of the topographic edge in the x-dimension:

GxGx2+Gy2⁢Fdiff⁡(d)⁢ⅆIbaseⅆx,(3)
and in the y-dimension:

GyGx2+Gy2⁢Fdiff⁡(d)⁢ⅆIbaseⅆy,(4)
where Gxis the topography x slope and Gyis the topography y slope. In further embodiments, a z-dimension (thickness) diffusion perturbation component may also be determined at operation770.

At operation775, the optical scattering (Eq. (2)) and diffusion perturbations (Eq. (2) and (3)) are summed with the base intensity (Eq. (1)) to compute the topography dependent blur intensity:

An example of an output from the OPC method700is illustrated inFIG. 7C. The second patterning level contour271(solid line) is generated based on an embodiment of the topography dependent resist profile model described herein. As shown, the topography from grating pattern221results in a significant resist break at the second level (as compared to the uncorrected synthesized plug pattern231). The dashed line272represents a second patterning level contour output by a conventional resist profile simulator which does not model topography (rule-based). As shown, the dashed line272does not display any substantial resist breaking. A second patterning level contour273(dotted line) as generated by a rigorous 3D simulation is also depicted inFIG. 7C. The improved performance of the topography dependent resist profile model algorithms described herein are evident by the better fit of the patterning level contour271to the rigorous contour273. Returning toFIG. 2, at operation270, a plug contour, such as that depicted inFIG. 7C, may then be generated for the corrected plug pattern261for points where the modeled resist profile crosses a threshold.

In one embodiment of the present invention, the verification algorithm employed at operation280is configured for a multiple patterning process which captures the interpolate of the first and second masks (e.g., grating and plug masks). Proper verification of layers in double patterning processes rely on a computation of a resist profile that results from a composite effect of two masks. For example, for the grating and plug mask patterns described herein, the composite effect of the first and second mask levels is a subtraction of the plug level from the grating level. At verification therefore, a subtraction of the modeled contour of the plug mask from the modeled contour of the grating mask should arrive at the target pattern, and if not, indicate a violation. In an alternative pitch doubling embodiment where a final mask is a sum of two masks, a final contour is a sum of two contours, a Boolean OR operation with the contours of each mask. In still another embodiment, the Boolean of two contours is employed in an algorithm to verify differences between two models which may be due to two different processes. The difference function contour can provide information for how different the two contours or processes are at different patterning regions. Although software packages exist which are capable of performing geometric Booleans of arbitrary shaped contours, such a computation is a relatively slow process. For the purposes of mask OPC and verification of a double patterning mask set, performing a Boolean of the billions of polygons present in the mask patterns is prohibitive.

In an embodiment of the present invention, the verification algorithm employed at operation280generates a composite contour281based on a function of the resist signals from each of at least two mask patterns.FIG. 8Aillustrates an exemplary fast method800for performing a Boolean operation of arbitrarily shaped contour. Method800begins with reading in a first resist signal (“A”) for the first mask level of a double patterning process at operation801and reading in a second resist signal (“B”) for the second mask level of the double patterning process at operation802. The image intensity signal may be generated using a conventional grid-based aerial image model that calculates an expected image intensity I(x,y) at a regular series of fixed grid points.

At operation805a Boolean function of the first and second level resist patterns is mapped to a function, ƒ(A,B) of the first and second resist signals. The functional form of ƒ(A,B) is based on the Boolean operation being performed by the double pattering and the polarity of the mask patterns. For example, in the grating and plug double patterning embodiment described elsewhere herein, the second level plug mask is a deduction from the first level grating mask. Because the polarity of the masks for the exemplary grating and plug embodiment are the same, the mask level relationship is:
Grating Contour−Plug Contour  (6)
so that ƒ(A,B) takes the form (A−B). For other mask polarities, the signage of the signals A and B may change so that the ƒ(A,B) takes the form (A+B), (B−A), etc.

At operation810, ƒ(A,B) is mapped to the functions which are evaluated by the resist simulator for computing a pattern contour. The functions to which ƒ(A,B) is mapped is dependent on the type of model being used to generate the contour. As one example, where a VTR model is employed with a grid of evaluation points positioned across the mask area, local image intensities, various derivatives of the image intensity, and the variable resist threshold with which the resist material will be cleared are functions to which ƒ(A,B) may be mapped. While any method of generating a contour from such image data may be used, in an exemplary embodiment a marching square algorithm is used to detect threshold crossings. The marching square algorithm performs it's searching function as known in the art, and evaluates ƒ(A,B) to output a zero crossing which corresponds to the Boolean operation mapped to the resist modeling functions.

At operation815, the composite contour is output by the resist simulator as a result of mapping the Boolean function to the functions from which the pattern contour is generated through thresholding. As such, the method800modifies the modeling functions at the resist signal level to generate a Boolean contour of the signals, which can be performed much more quickly than can a geometric Boolean of two arbitrary shaped contours.FIG. 8Billustrates an exemplary output in which ƒ(A,B) takes the form (A-B) and a difference contour881is generated. The first level contour251(A signal or grating contour), the second level contour271(B signal or plug contour), and the patterns321,351from which the resist models were generated are also depicted. As shown inFIG. 8B, the difference contour881produced by the marching square algorithm corresponds to regions where the first level contour251extends beyond the second level contour271. The region822, where the second level contour251extends beyond the first level contour271is thresholded out (e.g., A-B is below the zero crossing).

FIG. 8Dillustrates an example of a topographic effect which may not be accurately captured by a verification process absent the embodiments described herein which are designed for multi-level composite patterns. In the layout view shown, the first level contour251predicts the imaging performance of the synthesized grating pattern321while the second level contour271predicts the imaging performance of the plug pattern352. As shown, upon arriving at the composite effect of the two mask levels (either by the method800or by a conventional geometric Boolean operation of the pattern contours), the sliver882would result in a pinch error violation because portions of the synthesized grating pattern321are bridged. However, if contour271should snap toward the second level pattern352because of effects of the double-patterning process, a verification algorithm which merely operates on pattern contours generated as independent layers will result in numerous false violations.

To reduce such false violations, the method800is expanded in a further embodiment to include an additional operation. One or more of the image intensity signals is first modified with a cross term from the other of the image intensity signals before generating, based on a Boolean operation of the second mask level and the first mask level, a function of the image intensity signals.FIG. 8Eillustrates an exemplary method850which begins with operations851and852at which the first and second resist signals (“A” and “B”) are read in, as discussed elsewhere herein. At operation853, at least one of the signals is modified with a cross term from the other of the resist signals. In the exemplary embodiment, both resist signals are modified with a cross term.

Generally, the cross term is to impart some dependency of one or both of the masks on the other in a double patterning mask set to capture the sequence and topography-based lithographic effects that occur during double-patterning processes. For example, as depicted inFIG. 8D, where the first level contour271results in a false violation, the resist signal from which the first level contour271was generated is modified at operation853to include a cross term from the resist signal B to arrive at: A′=ƒ1(B). A similar modification can be made to the resist signal of the second patterning level to introduce a cross term from the first level resist signal to arrive at: B′=ƒ2(A).

In one embodiment, the cross term comprises a proximity influence term which increases in magnitude as the first and second image intensity signals become more proximate to each other within the mask area. This causes the magnitude of the modification to increase with proximity (i.e., as the first and second level patterns approach colinearity), and the modified signal is to deviate from the nominal by a greater amount. In a particular embodiment, the proximity influence term in the modified image intensity signal is an exponential function of the other image intensity signal (e.g., A′=ƒ1(B)=e(B).

In a further embodiment, the cross term is applied to the resist signal as a function of a curvature or slope of the resist signal to capture second order effects that are not captured by proximity alone. Generally this term is to limit signal modification to a subset of the greatest topography of the mask level for which the signal being modified corresponds. As one embodiment, the cross term (e.g., proximity influence term) is multiplied by a curvature of the electric field (slope of signal A). For example, for a modification to first pattern level signal: A′=ƒ1(B)=Slope of ƒA*e(B)) Similar treatments may be applied to the signal B in further embodiments.

Next, at operation855, a function of the image intensity signals, as modified, is generated based on a Boolean operation of the second mask level and the first mask level substantially as described elsewhere herein for an unmodified signal. At operation860the composite contour from the function of the first and second image intensity signals is determined at output at operation865as a modified prediction of an image that results on a substrate from successively printing the first and second mask levels on the substrate.

FIG. 8Cillustrates a difference contour881employing the method850. As shown, many of the areas that are identified as a difference between the first and second patterns321,352inFIG. 8Bare no longer so identified. In this manner the method of850may be employed to incorporate composite mask effects into a composite contour to arrive at a better model of a double-patterning process and reduce the number of false violations.

Returning toFIG. 2, upon verification, the mask design and generation process outputs instructions from which a mask shop can manufacture the first level (grating) mask at operation290and the second level (plug) mask at operation295. The masks generated may then be utilized by a microelectronics manufacturer to practice a double patterning process, such as that depicted inFIG. 1.

Embodiments of the present invention may include apparatuses for performing the operations herein. The simulation algorithms of the present invention may be implemented on a stand-alone or networked computer system based on a number of instructions that are executed by the computer(s) to simulate how a mask pattern will print on a wafer. From the estimate of how the mask pattern will print, one or more of the resolution enhancement techniques, such as OPC or subresolution assist features (SRAFs) can be used in order to produce mask pattern data that will be used to generate a mask which is projected onto a wafer to print the target pattern into a thin film layer of a microelectronic device.

An apparatus may be specially constructed for the desired purposes, or it may comprise a general purpose computing device selectively activated or reconfigured by a program stored in the device. Such a program may be stored on a storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, compact disc read only memories (CD-ROMs), magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), electrically programmable read-only memories (EPROMs), electrically erasable and programmable read only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions, and capable of being coupled to a system bus for a computing device.

The exemplary computer system900includes a processor902, a main memory904(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory906(e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory918(e.g., a data storage device), which communicate with each other via a bus930.

The computer system900may further include a network interface device908. The computer system900also may include a video display unit910(e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device912(e.g., a keyboard), a cursor control device914(e.g., a mouse), and a signal generation device916(e.g., a speaker).

The secondary memory918may include a machine-accessible storage medium (or more specifically a computer-readable storage medium)931on which is stored one or more sets of instructions (e.g., software922) embodying any one or more of the methodologies or functions described herein. The software922may also reside, completely or at least partially, within the main memory904and/or within the processor902during execution thereof by the computer system900, the main memory904and the processor902also constituting machine-readable storage media. The software922may further be transmitted or received over a network920via the network interface device908.

In the foregoing specification, embodiments of the invention have been described with reference to specific exemplary features thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and figures are, accordingly, to be regarded in an illustrative rather than a restrictive sense.