Video decoders and electronic systems including the same

A video decoder may perform, based on an operation mode, at least one of a first decoding operation to restore a first bin value based on a first context value, a second decoding operation to restore a second bin value based on an updated first context value or a second context value, a third decoding operation to restore a third bin value based on the updated first context value or a third context value, and a fourth decoding operation to restore at least one bypass bin value without a context value. Based on the operation mode, the video decoder may output the first bin value, the at least one bypass bin value, the first bin value and the at least one bypass bin value, the first bin value and one of the second and third bin values, or at least one of the first, second, and third bin values.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2016-0120445, filed on Sep. 21, 2016 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

1. Technical Field

Example embodiments relate generally to video or image processing, and more particularly to video decoders using context-based adaptive binary arithmetic coding (CABAC) and electronic systems including the video decoders.

2. Description of the Related Art

According to increasing demands for high resolution and high quality videos, such as high definition (HD) videos, ultra HD (UHD) videos, etc., research has focused on video data compression and decompression for achieving improved compression performance. A context-based adaptive binary arithmetic coding (CABAC), which is a kind of entropy coding, has a relatively complex algorithm and a relatively long coding time. Research has been conducted on techniques of efficiently decoding video data that is encoded by CABAC.

SUMMARY

Accordingly, the present inventive concepts are provided to substantially reduce or eliminate one or more problems due to limitations and disadvantages of the related art.

At least one example embodiment of the present inventive concepts provides a video decoder capable of efficiently and expeditiously performing multi-bin decoding.

At least one example embodiment of the present inventive concepts provides an electronic system including the video decoder.

According to example embodiments of the present inventive concepts, a video decoder may include a multi-bin decoding block and a decoding mode control block. The multi-bin decoding block performs at least one of a first decoding operation, a second decoding operation, a third decoding operation and a fourth decoding operation based on an operation mode. The first decoding operation represents a first operation of restoring a first bin value based on a first context value. The second decoding operation represents a second operation of restoring a second bin value based on one of an updated first context value and a second context value. The updated first context value is obtained after the first decoding operation. The third decoding operation represents a third operation of restoring a third bin value based on one of the updated first context value and a third context value. The fourth decoding operation represents a fourth operation of restoring at least one bypass bin value without a context value. The decoding mode control block is configured to perform an output operation to output the first bin value, to output the at least one bypass bin value, to output the first bin value and the at least one bypass bin value, to output the first bin value and one of the second and third bin values, or to output at least one of the first, second, and third bin values based on the first bin value. The output operation of the decoding mode control block is performed based on the operation mode.

According to example embodiments of the present inventive concepts, an electronic system may include a video source and a video decoder. The video source provides an encoded bit stream. The video decoder decodes the encoded bit stream to generate a restored video. The video decoder includes a multi-bin decoding block and a decoding mode control block. The multi-bin decoding block performs at least one of a first decoding operation, a second decoding operation, a third decoding operation, and a fourth decoding operation based on an operation mode. The first decoding operation represents a first operation of restoring a first bin value based on a first context value. The second decoding operation represents a second operation of restoring a second bin value based on one of an updated first context value and a second context value. The updated first context value is obtained after the first decoding operation. The third decoding operation represents a third operation of restoring a third bin value based on one of the updated first context value and a third context value. The fourth decoding operation represents an operation of restoring at least one bypass bin value without a context value. The decoding mode control block is configured to perform an output operation to output the first bin value, to output the at least one bypass bin value, to output the first bin value and the at least one bypass bin value, to output the first bin value and one of the second and third bin values, or to output at least one of the first, second and third bin values based on the first bin value. The output operation of the decoding mode control block is performed based on the operation mode.

According to example embodiments of the present inventive concepts, a video decoder may include a multi-bin decoding circuit that includes a first decoding circuit, a second decoding circuit, a third decoding circuit, and a fourth decoding circuit. The first decoding circuit may be configured to receive as input a first context value, an input range, and an input offset, and configured to output an updated first context value, a first range, a first offset, and a first bin value responsive to a first decoding operation. The second decoding circuit may be configured to receive as input the updated first context value or a second context value, and configured to output an updated second context value and a second bin value responsive to a second decoding operation. The third decoding circuit may be configured to receive as input the updated first context value or a third context value, and configured to output an updated third context value and a third bin value responsive to a third decoding operation. The fourth decoding circuit may be configured to receive as input the first range and the first offset, or the input range and the input offset, and configured to output at least one bypass bin value responsive to a fourth decoding operation.

Video decoders according to example embodiments of the present inventive concepts may employ a multi-bin decoding in which at least two bin values are sequentially processed or decoded, may support a plurality of operation modes for sequentially decoding more than two bin values, and may selectively output results from various scenarios of the multi-bin decoding depending on the operation mode. Accordingly, video decoders according to the present inventive concepts may have a relatively increased decoding speed and enhanced performance, and may efficiently restore high quality videos.

DETAILED DESCRIPTION

Various example embodiments of the present inventive concepts will be described more fully with reference to the accompanying drawings, in which embodiments of the present inventive concepts are shown. The present inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout this application.

FIG. 1is a block diagram illustrating a video decoder according to example embodiments of the present inventive concepts.

Referring toFIG. 1, a video decoder10may include a multi-bin decoding block300and a decoding mode control block400. The video decoder10may further include a context index control block100, a context buffer200and a range/offset buffer500. In some embodiments, the blocks ofFIG. 1may represent circuits and/or collections of circuits configured to implement the operations described herein. In some embodiments, the blocks ofFIG. 1may represent computer operations performed by at least one processor which may be further instantiated as a computer program product.

The video decoder10according to example embodiments may operate (e.g., may perform a decoding operation) based on and/or using context-based adaptive binary arithmetic coding (CABAC). The video decoder10according to example embodiments may sequentially decode a plurality of binary values (e.g., a logical 0 or 1), or “bins.” As used herein, “bin,” “bin values,” and “binary values” may be used interchangeably to refer the individual binary values (e.g. logical 0 or 1) processed by the video decoder10. The individual logical values may be physically represented in multiple ways within the video decoder10, as would be understood by one of ordinary skill in the art. For example, the logical value of a respective binary value may be represented as a particular electrical level (e.g., low or high) of a signal and/or memory location accessed by the video decoder10. The video decoder10according to example embodiments may substantially simultaneously and/or concurrently output the plurality of binary values that are sequentially decoded based on an operation mode of the video decoder10.

Hereinafter, the example embodiments will be explained in detail with reference to examples of sequentially decoding two binary values using CABAC.

The multi-bin decoding block300may perform at least one of a first decoding operation, a second decoding operation, a third decoding operation, and a fourth decoding operation based on an operation mode. The first decoding operation may represent an operation of restoring a first bin value based on a first context value CTX1. As used herein, the term “restoring” may include operations which decode a previously-encoded value. The first context value CTX1may be updated during the first decoding operation, and an updated first context value (e.g., UCTX1inFIG. 2) may be obtained after the first decoding operation. The second decoding operation may represent an operation of restoring a second bin value based on one of the updated first context value and a second context value CTX2. The third decoding operation may represent an operation of restoring a third bin value based on one of the updated first context value and a third context value CTX3. Similar to the first context value CTX1, the second and third context values CTX2and CTX3may be updated after the second and third decoding operations, respectively (e.g., UCTX2, UCTX3inFIG. 2). The fourth decoding operation may represent an operation of restoring at least one bypass bin value without a context value.

As described above, the multi-bin decoding block300may sequentially decode two binary values (e.g., two bin values). The first decoding operation may represent an operation of decoding a first bin value among the two bin values. Each of the second and third decoding operations may represent an operation of decoding a second bin value among the two bin values. The fourth decoding operation may be referred to as a bypass decoding operation. Each of the first bin value, the second bin value, the third bin value, and the at least one bypass bin value generated by the first, second, third, and fourth decoding operations may be a logical 0 or 1.

The decoding mode control block400may output a result of at least one of the first, second, third, and fourth decoding operations based on an operation mode of the video decoder10. The output operation of the decoding mode control block400may be performed based on the operation mode. For example, the decoding mode control block400may output only the first bin value, may output only the at least one bypass bin value, may output the first bin value and the at least one bypass bin value, may output the first bin value and one of the second and third bin values, or may output at least one of the first, second, and third bin values based on the first bin value. In other words, a bin value BOUT output from the decoding mode control block400may include a single bin value or a plurality of bin values based on the operation mode.

The decoding mode control block400may further output an updated context value UCTX as a result of at least one of the first, second, third, and fourth decoding operations. For example, the updated context value UCTX may include at least one of an updated first context value, an updated second context value, and an updated third context value. In some example embodiments, the updated context value UCTX may not be output.

The multi-bin decoding block300may additionally use an input range IRNG and/or an input offset IOFS for performing at least one of the first, second, third, and fourth decoding operations. The input range IRNG and/or the input offset IOFS may be updated before or after each decoding operation, and then the decoding mode control block400may further output an updated range URNG and/or an updated offset UOFS as a result of at least one of the first, second, third, and fourth decoding operations.

In some example embodiments, a decoding mode control signal DS that is received by the multi-bin decoding block300and the decoding mode control block400may represent the operation mode of the video decoder10. Examples of the operation mode will be explained in detail with reference toFIGS. 3, 4, 5, 6, 7, and 8.

The context index control block100may select at least one of the first, second, and third context values CTX1, CTX2, and CTX3among a plurality of context values based on at least one of a first context index CTXIDX1, a second context index CTXIDX2, and a third context index CTXIDX3, and may provide at least one of the first, second, and third context values CTX1, CTX2, and CTX3to the multi-bin decoding block300. For example, although not illustrated inFIG. 1, the context index control block100may receive an encoded bit stream, and may obtain at least one of the first, second, and third context indexes CTXIDX1, CTXIDX2, and CTXIDX3from the encoded bit stream at an initial operation time.

The context buffer200may store the plurality of context values, and may store the updated context value UCTX after at least one of the first, second, third, and fourth decoding operations is performed.

The range/offset buffer500may provide the input range IRNG and the input offset IOFS to the multi-bin decoding block300, and may store the updated range URNG and/or the updated offset UOFS after at least one of the first, second, third, and fourth decoding operations is performed. For example, although not illustrated inFIG. 1, the range/offset buffer500may receive an encoded bit stream, and may obtain the input range IRNG and the input offset IOFS from the encoded bit stream at an initial operation time.

CABAC is an entropy coding scheme used in a main profile of the H.264/AVC (Advanced Video Coding) video compression standard. In CABAC, each symbol is dynamically coded using statistical features to update its relative probability, thereby improving compression efficiency.

A bit stream encoded using CABAC consists of a set of syntax elements, similar to that of other moving picture compression standards. Although not illustrated inFIG. 1, the bit stream includes a plurality of slices. Each slice includes a slice header and slice data. Each slice data includes a plurality of macro blocks and a plurality of neighbor identifiers. Each macro block includes a plurality of syntax elements. Each syntax element consists of a bin string including a plurality of bin values.

CABAC decoding is a process of sequentially decoding a plurality of bin values (logical 0 or 1), from a syntax element which was encoded by a CABAC encoder. To decode a bin value, several unit operations may be used, including a context selection operation, a context model loading operation, a binary arithmetic decoding operation, a binarization matching operation, and/or a context model update operation.

In the context selection operation, context models used to decode each bin value may be selected. In the context model loading operation, the selected context models may be read. In some embodiments, the selected context models may be read into a memory of the video decoder10. The context selection operation and the context model loading operation may be performed by the context index control block100and the context buffer200. In the binary arithmetic decoding operation, a bin value may be generated, and a context value corresponding to a current context model may be selectively modified based on the generated bin value. In the binarization matching operation, it may be checked whether the generated bin value constitutes a valid bin string. In the context model update operation, if the context value is modified in the binary arithmetic decoding operation, the modified context value may be stored in a memory. These operations may have data dependency with each other such that a current bin value may not be decoded without decoding a previous bin value, and thus it may be difficult to rapidly decode a plurality of consecutive bin values.

The video decoder10according to example embodiments may employ a multi-bin decoding operation in which a plurality of bin values (e.g., two or more bin values) are sequentially processed (e.g., decoded), and may output the plurality of bin values restored by the multi-bin decoding operation in various ways, based on the operation mode. Accordingly, the video decoder10may have a relatively increased decoding speed and enhanced performance.

FIG. 2is a block diagram illustrating an example of the multi-bin decoding block300and a decoding mode control block400included in the video decoder10(seeFIG. 1) according to example embodiments of the present inventive concepts.

Referring toFIG. 2, a multi-bin decoding block300amay include a first decoding circuit310, a second decoding circuit320, a third decoding circuit330, and a fourth decoding circuit340. The multi-bin decoding block300amay be an example embodiment of the multi-bin decoding block300ofFIG. 1. The multi-bin decoding block300amay further include a first multiplexer325, a second multiplexer335, and a third multiplexer345.

The first decoding circuit310may perform the first decoding operation. For example, the first decoding circuit310may generate a first bin value BOUT1based on the input range IRNG, the input offset IOFS, and/or the first context value CTX1. For example, a bit stream may be encoded using CABAC. When a syntax element in the encoded bit stream is decoded using CABAC, a bin string may be obtained. Each bin value included in the bin string may have a logical value of 0 or 1. A bin value which has a higher probability of occurrence in all of the syntax elements may be referred to as a most probable symbol (MPS), and a bin value which has a lower probability of occurrence in all of the syntax elements may be referred to as a least probable symbol (LPS). The first decoding circuit310may determine the first bin value BOUT1as one of the MPS and/or the LPS based on the input range IRNG, the input offset IOFS, and the first context value CTX1.

While the first bin value BOUT1is generated, the first decoding circuit310may update (e.g., adjust and/or change) the first context value CTX1to generate an updated first context value UCTX1, and may update the input range IRNG and the input offset IOFS to generate a first range RNG1and a first offset OFS1. In CABAC, a symbol may be dynamically coded (e.g., encoded or decoded) using statistical features to update its relative probability, and thus the first context value CTX1, the input range IRNG, and the input offset IOFS may be updated to generate the first range RNG1and the first offset OFS1, respectively.

In some example embodiments, a probability of occurrence of the MPS in all of the syntax elements may be referred to as a symbol probability. The symbol probability may be any value in a range of about 0 to 1, however, the symbol probability may be finitely represented based on quantization. Therefore, the symbol probability may be represented as a probability state index having a predetermined number of bits. A context model corresponding to the first context value CTX1may include the probability state index. The symbol probability corresponding to the probability state index may be used for updating the input range IRNG to generate the first range RNG1. The first bin value BOUT1may be determined by comparing the updated range (e.g., the first range RNG1) with the input offset IOFS. For example, the first bin value BOUT1may become the MPS when the input offset IOFS is less than the first range RNG1. The first bin value BOUT1may become the LPS when the input offset IOFS is equal to or greater than the first range RNG1. After the first bin value BOUT1is determined, the input offset IOFS may also be updated to generate the first offset OFS1.

The second decoding circuit320may perform the second decoding operation. For example, the second decoding circuit320may generate a second bin value BOUT2based on the first range RNG1, the first offset OFS1, and one of the updated first context value UCTX1and the second context value CTX2. While the second bin value BOUT2is generated, the second decoding circuit320may update the second context value CTX2to generate an updated second context value UCTX2, and may update the first range RNG1and the first offset OFS1to generate a second range RNG2and a second offset OFS2.

The third decoding circuit330may perform the third decoding operation. For example, the third decoding circuit330may generate a third bin value BOUT3based on the first range RNG1, the first offset OFS1and one of the updated first context value UCTX1and the third context value CTX3. While the third bin value BOUT3is generated, the third decoding circuit330may update the third context value CTX3to generate an updated third context value UCTX3, and may update the first range RNG1and the first offset OFS1to generate a third range RNG3and a third offset OFS3.

In some example embodiments, the second and third decoding operations may be performed substantially concurrently. As used herein, operations that are performed substantially concurrently include at least one portion of both operations being performed at a same moment in time. An operation of determining the second bin value BOUT2in the second decoding circuit320and an operation of determining the third bin value BOUT3in the third decoding circuit330may be similar to the operation of determining the first bin value BOUT1in the first decoding circuit310.

As described above with reference toFIG. 1, the multi-bin decoding block300amay sequentially decode two binary values. The bin value BOUT1generated by the first decoding operation may correspond to a first binary value among the two binary values. Each of the bin values BOUT2and BOUT3generated by the second and third decoding operations may correspond to a second binary value among the two binary values. For example, the second decoding operation may represent an operation for restoring the second binary value when the first binary value is determined to be the MPS. The third decoding operation may represent an operation for restoring the second binary value when the first binary value is determined to be the LPS. In other words, the second binary value may be pre-calculated for both cases (e.g., for a case in which the first binary value is the MPS, and for a case in which the first binary value is the LPS). Thus, a time required to decode two consecutive binary values may be reduced.

The fourth decoding circuit340may perform the fourth decoding operation. For example, the fourth decoding circuit340may generate at least one bypass bin value BOUTBP based on the input range IRNG and the input offset IOFS, or based on the first range RNG1and the first offset OFS1. In some embodiments, a plurality of bypass bin values BOUTBP may be generated (e.g. BOUTBP1, BOUTBP2inFIG. 4). While the at least one bypass bin value BOUTBP is generated, the fourth decoding circuit340may update the input range IRNG and the input offset IOFS to generate a range RNGA and a offset OFSA, or may update the first range RNG1and the first offset OFS1to generate the range RNGA and the offset OFSA.

The decoding mode control block400may output the at least one bin value BOUT, the updated context value UCTX, the updated range URNG, and/or the updated offset UOFS based on the decoding mode control signal DS.

The outputs of the decoding mode control block400may be changed depending on the operation mode that is controlled by the decoding mode control signal DS. For example, the at least one bin value BOUT may include at least one of the first bin value BOUT1, the second bin value BOUT2, the third bin value BOUT3, and the bypass bin value BOUTBP. The updated context value UCTX may include at least one of the updated first context value UCTX1, the updated second context value UCTX2, and the updated third context value UCTX3. The updated range URNG may include at least one of the first range RNG1, the second range RNG2, the third range RNG3, and the range RNGA. The updated offset UOFS may include at least one of the first offset OFS1, the second offset OFS2, the third offset OFS3, and the offset OFSA.

In some example embodiments, the operation mode may include a first operation mode, a second operation mode, a third operation mode, a fourth operation mode, and a fifth operation mode. In the first operation mode, the first bin value BOUT1may be output. In the second operation mode, one bypass bin value (e.g., BOUTBP1inFIG. 4) may be output. In the third operation mode, a plurality of bypass bin values (e.g., BOUTBP1and BOUTBP2inFIG. 5) may be output. In the fourth operation mode, the first bin value BOUT1and at least one bypass bin value (e.g., BOUTBP2inFIG. 6) may be output. In the fifth operation mode, the first bin value BOUT1and one of the second and third bin values BOUT2and BOUT3may be output.

In some example embodiments, the operation mode may include a sixth operation mode, a seventh operation mode, an eighth operation mode, a ninth operation mode, a tenth operation mode, and an eleventh operation mode. In the sixth operation mode, the first and second bin values BOUT1and BOUT2may be output if the first bin value BOUT1is a logical 0. In the seventh operation mode, the first and third bin values BOUT1and BOUT3may be output if the first bin value BOUT1is a logical 0. In the eighth operation mode, the first bin value BOUT1may be output if the first bin value BOUT1is a logical 0. In the ninth operation mode, the first and second bin values BOUT1and BOUT2may be output if the first bin value BOUT1is a logical 1. In the tenth operation mode, the first and third bin values BOUT1and BOUT3may be output if the first bin value BOUT1is a logical 1. In the eleventh operation mode, the first bin value BOUT1may be output if the first bin value BOUT1is a logical 1.

The first multiplexer325may provide one of the updated first context value UCTX1and the second context value CTX2to the second decoding circuit320based on a first selection signal S1. For example, the first multiplexer325may provide the updated first context value UCTX1to the second decoding circuit320when the second context value CTX2is substantially the same as the first context value CTX1. The first multiplexer325may provide the second context value CTX2to the second decoding circuit320when the second context value CTX2is different from the first context value CTX1.

The second multiplexer335may provide one of the updated first context value UCTX1and the third context value CTX3to the third decoding circuit330based on a second selection signal S2. An operation of the second multiplexer335may be similar to that of the first multiplexer325. For example, the second multiplexer335may provide the updated first context value UCTX1to the third decoding circuit330when the third context value CTX3is substantially the same as the first context value CTX1. The second multiplexer335may provide the third context value CTX3to the third decoding circuit330when the third context value CTX3is different from the first context value CTX1.

The third multiplexer345may provide the input range IRNG and the input offset IOFS to the fourth decoding circuit340based on the decoding mode control signal DS, or may provide the first range RNG1and the first offset OFS1to the fourth decoding circuit340based on the decoding mode control signal DS. For example, the third multiplexer345may provide the input range IRNG and the input offset IOFS to the fourth decoding circuit340in the second and third operation modes in which the decoding mode control block400outputs the at least one bypass bin value BOUTBP as the at least one bin value BOUT. The third multiplexer345may provide the first range RNG1and the first offset OFS1to the fourth decoding circuit340in the fourth operation mode in which the decoding mode control block400outputs both the first bin value BOUT1and the at least one bypass bin value BOUTBP as the at least one bin value BOUT.

In some example embodiments, the decoding mode control signal DS, the first selection signal S1, and the second selection signal S2may be combined into a single signal.

In some example embodiments, at least a part of the multi-bin decoding block300amay be implemented as hardware. For example, in some embodiments, at least one of the first decoding circuit310, the second decoding circuit320, the third decoding circuit330, and the fourth decoding circuit340may be implemented as electrical circuits, and at least one of the first context value CTX1, the second context value CTX2, and the third context value CTX3may be electrical signals provided over conductive elements to respective ones of the at least one of the first decoding circuit310, the second decoding circuit320, and the third decoding circuit330.

FIGS. 3, 4, 5, 6, 7 and 8are diagrams for describing an operation of a video decoder based on an operation mode according to example embodiments of the present inventive concepts.

Referring toFIG. 3, the multi-bin decoding block300amay perform the first decoding operation in the first operation mode as indicated by the decoding mode control signal DS. For example, the first decoding circuit310may generate the first bin value BOUT1based on the input range IRNG, the input offset IOFS, and the first context value CTX1, and may update the first context value CTX1, the input range IRNG, and the input offset IOFS to generate the updated first context value UCTX1, the first range RNG1, and the first offset OFS1.

The decoding mode control block400may output results of the first decoding operation in the first operation mode. For example, the decoding mode control block400may output the first bin value BOUT1, the updated first context value UCTX1, the first range RNG1, and the first offset OFS1based on the decoding mode control signal DS. The updated context UCTX inFIG. 1may be stored into the context buffer200inFIG. 1based on the updated first context value UCTX1. The updated range URNG and the updated offset UOFS inFIG. 1may be stored into the range/offset buffer500inFIG. 1based on the first range RNG1and the first offset OFS1. The first operation mode may be referred to as a single-bin decoding mode.

In some example embodiments, as illustrated inFIG. 3, the second and/or third decoding operations may be further performed in the first operation mode. In other example embodiments, although not illustrated inFIG. 3, the second and/or third decoding operations may not be performed in the first operation mode. Similarly, in some embodiments, the fourth decoding operation may not be performed in the first operation mode.

Referring toFIG. 4, the multi-bin decoding block300amay perform the fourth decoding operation in the second operation mode as indicated by the decoding mode control signal DS. For example, the third multiplexer345may provide the input range IRNG and the input offset IOFS to the fourth decoding circuit340based on the decoding mode control signal DS. The fourth decoding circuit340may generate a first bypass bin value BOUTBP1and a second bypass bin value BOUTBP2based on the input range IRNG and the input offset IOFS, and may update the input range IRNG and the input offset IOFS to generate the range RNGA and the offset OFSA.

The decoding mode control block400may output some of results of the fourth decoding operation in the second operation mode. For example, the decoding mode control block400may output the first bypass bin value BOUTBP1, the range RNGA, and the offset OFSA based on the decoding mode control signal DS. The updated range URNG and the updated offset UOFS inFIG. 1may be stored into the range/offset buffer500inFIG. 1based on the range RNGA and the offset OFSA. The second operation mode may be referred to as a single-bypass decoding mode.

Referring toFIG. 5, the multi-bin decoding block300amay perform the fourth decoding operation in the third operation mode as indicated by the decoding mode control signal DS. For example, the fourth decoding operation illustrated inFIG. 5may be substantially the same as the fourth decoding illustrated inFIG. 4.

The decoding mode control block400may output the whole of results of the fourth decoding operation in the third operation mode. For example, the decoding mode control block400may output the first bypass bin value BOUTBP1, the second bypass bin value BOUTBP2, the range RNGA, and the offset OFSA based on the decoding mode control signal DS. The updated range URNG and the updated offset UOFS inFIG. 1may be stored into the range/offset buffer500inFIG. 1based on the range RNGA and the offset OFSA. The third operation mode may be referred to as a multi-bypass decoding mode.

AlthoughFIGS. 4 and 5illustrate an example where two bypass bin values BOUTBP1and BOUTBP2are generated as a result of the fourth decoding operation, more than two bypass bin values may be generated as a result of the fourth decoding operation, and then the more than two bypass bin values may be output in the third operation mode. The first, second, and third decoding operations may not always be performed in the second and/or third operation modes, and thus an updated context value may not be generated.

Referring toFIG. 6, the multi-bin decoding block300amay perform the first and fourth decoding operations in the fourth operation mode as indicated by the decoding mode control signal DS. For example, the first decoding operation illustrated inFIG. 6may be substantially the same as the first decoding operation illustrated inFIG. 3. The third multiplexer345may provide the first range RNG1and the first offset OFS1to the fourth decoding circuit340based on the decoding mode control signal DS. The fourth decoding circuit340may generate the second bypass bin value BOUTBP2based on the first range RNG1and the first offset OFS1, and may update the first range RNG1and the first offset OFS1to generate the range RNGA and the offset OFSA.

The decoding mode control block400may output results of the first and fourth decoding operations in the fourth operation mode. For example, the decoding mode control block400may output the first bin value BOUT1, the second bypass bin value BOUTBP2, the updated first context value UCTX1, the first range RNG1, the range RNGA, the first offset OFS1, and the offset OFSA based on the decoding mode control signal DS. The updated context value UCTX inFIG. 1may be stored into the context buffer200inFIG. 1based on the updated first context value UCTX1. The updated range URNG and the updated offset UOFS inFIG. 1may be stored into the range/offset buffer500inFIG. 1based on the first range RNG1, the range RNGA, the first offset OFS1, and the offset OFSA. The fourth operation mode may be referred to as a bin-bypass decoding mode.

The second and third decoding operations may not be performed in the fourth operation mode.

Referring toFIGS. 7 and 8, the multi-bin decoding block300amay perform the first, second, and third decoding operations in the fifth operation mode as indicated by the decoding mode control signal DS. For example, the first decoding operation illustrated inFIGS. 7 and 8may be substantially the same as the first decoding operation illustrated inFIG. 3. The second decoding circuit320may generate the second bin value BOUT2based on the first range RNG1, the first offset OFS1, and one of the updated first context value UCTX1and the second context value CTX2, and may update the second context value CTX2, the first range RNG1, and the first offset OFS1to generate the updated second context value UCTX2, the second range RNG2, and the second offset OFS2. The third decoding circuit330may generate the third bin value BOUT3based on the first range RNG1, the first offset OFS1, and one of the updated first context value UCTX1and the third context value CTX3, and may update the third context value CTX3, the first range RNG1, and the first offset OFS1to generate the updated third context value UCTX3, the third range RNG3, and the third offset OFS3.

In some example embodiments, as illustrated inFIG. 7, the decoding mode control block400may output results of the first and second decoding operations in the fifth operation mode. For example, the decoding mode control block400may output the first and second bin values BOUT1and BOUT2, the updated first and second context values UCTX1and UCTX2, the first and second ranges RNG1and RNG2, and the first and second offsets OFS1and OFS2based on the decoding mode control signal DS. The updated context value UCTX inFIG. 1may be stored into the context buffer200inFIG. 1based on the updated first and second context values UCTX1and UCTX2. The updated range URNG and the updated offset UOFS inFIG. 1may be stored into the range/offset buffer500inFIG. 1based on the first and second ranges RNG1and RNG2and the first and second offsets OFS1and OFS2. The fifth operation mode may be referred to as a bin-bin decoding mode.

In some example embodiments, as illustrated inFIG. 8, the decoding mode control block400may output results of the first and third decoding operations in the fifth operation mode as indicated by the decoding mode control signal DS. For example, the decoding mode control block400may output the first and third bin values BOUT1and BOUT3, the updated first and third context values UCTX1and UCTX3, the first and third ranges RNG1and RNG3, and the first and third offsets OFS1and OFS3based on the decoding mode control signal DS. The updated context value UCTX inFIG. 1may be stored into the context buffer200inFIG. 1based on the updated first and third context values UCTX1and UCTX3. The updated range URNG and the updated offset UOFS inFIG. 1may be stored into the range/offset buffer500inFIG. 1based on the first and third ranges RNG1and RNG3and the first and third offsets OFS1and OFS3.

The fourth decoding operation may not always be performed in the fifth operation mode.

Although not illustrated inFIGS. 3, 4, 5, 6, 7 and 8, an operation of the multi-bin decoding block300ain the sixth and ninth operation modes may be similar to the operation of the multi-bin decoding block300aillustrated inFIG. 7, an operation of the multi-bin decoding block300ain the seventh and tenth operation modes may be similar to the operation of the multi-bin decoding block300aillustrated inFIG. 8, and an operation of the multi-bin decoding block300ain the eighth and eleventh operation modes may be similar to the operation of the multi-bin decoding block300aillustrated inFIG. 3. In other words, the multi-bin decoding block300amay perform the first, second and third decoding operations in each of the sixth, seventh, ninth, and tenth operation modes, and may perform the first decoding operation in each of the eighth and eleventh operation modes. Each of the sixth, seventh, eighth, ninth, tenth, and eleventh operation modes may be referred to as a conditional decoding mode.

AlthoughFIGS. 1 through 8illustrate examples where two binary values in a syntax element are sequentially decoded, the video decoder10according to example embodiments of the present inventive concepts may sequentially decode a plurality of binary values in a syntax element in units of two bins. For example, the video decoder10may decode first and second binary values in a first syntax element, may decode third and fourth binary values in the first syntax element based on a result of decoding the first and second binary values, and may decode fifth and sixth binary values in the first syntax element based on a result of decoding the third and fourth binary values.

The video decoder10according to example embodiments may employ the multi-bin decoding, and may selectively output results from various scenarios of the multi-bin decoding depending on the operation mode (e.g., based on the decoding mode control signal DS). Accordingly, the video decoder10may have a relatively increased decoding speed and enhanced performance, and may efficiently restore high quality videos (e.g., videos having a relatively high bit rate).

FIG. 9is a block diagram illustrating another example of a multi-bin decoding block300band a decoding mode control block400included in the video decoder according to example embodiments of the present inventive concepts.

Referring toFIG. 9, a multi-bin decoding block300bmay include a first decoding circuit310, a second decoding circuit320, a third decoding circuit330, and a fourth decoding circuit340. The multi-bin decoding block300bmay be an example embodiment of the multi-bin decoding block300ofFIG. 1. The multi-bin decoding block300bmay further include a first multiplexer325b, a second multiplexer335b, a third multiplexer345, and a fourth multiplexer315, and a context keeper350.

The multi-bin decoding block300binFIG. 9may be substantially the same as the multi-bin decoding block300ainFIG. 2, except that the multi-bin decoding block300bfurther includes the context keeper350and the fourth multiplexer315, and additionally operations of the first and second multiplexers325band335b, and the decoding circuits310,320, and330, are changed.

The context keeper350may temporarily store the updated first context value UCTX1, the updated second context value UCTX2, and/or the updated third context value UCTX3that are results of a current decoding operation of the multi-bin decoding block300b. In addition, the context keeper350may output a first previous context value PCTX1, a second previous context value PCTX2, and/or a third previous context value PCTX3that are results of a previous decoding operation of the multi-bin decoding block300b. In some embodiments, the context keeper350may be a storage circuit configured to store the updated first context value UCTX1, the updated second context value UCTX2, and/or the updated third context value UCTX3.

The fourth multiplexer315may provide one of the first context value CTX1and the first previous context value PCTX1to the first decoding circuit310based on a selection signal S0. For example, the fourth multiplexer315may provide the first previous context value PCTX1to the first decoding circuit310when the first context value CTX1is substantially the same as the first previous context value PCTX1. When the first previous context value PCTX1is provided to the first decoding circuit310, a context selection operation and a context model loading operation for obtaining the first context value CTX1may be omitted. The fourth multiplexer315may provide the first context value CTX1to the first decoding circuit310when the first context value CTX1is different from the first previous context value PCTX1.

The first decoding circuit310may perform the first decoding operation based on one of the first context value CTX1and the first previous context value PCTX1. In addition, after at least one of the first, second, third, and fourth decoding operations is performed, the first decoding circuit310may restore a fourth bin value based on one of the updated first context value UCTX1temporarily stored in the context keeper350and a fourth context value, and may update the fourth context value to generate an updated fourth context value.

The first multiplexer325bmay provide one of the second context value CTX2, the second previous context value PCTX2, and the updated first context value UCTX1to the second decoding circuit320based on the selection signal S1. For example, the first multiplexer325bmay provide the second previous context value PCTX2to the second decoding circuit320when the second context value CTX2is substantially the same as the second previous context value PCTX2. When the second previous context value PCTX2is provided to the second decoding circuit320, a context selection operation and a context model loading operation for obtaining the second context value CTX2may be omitted. The first multiplexer325bmay provide the updated first context value UCTX1to the second decoding circuit320when the second context value CTX2is substantially the same as the first context value CTX1. The first multiplexer325bmay provide the second context value CTX2to the second decoding circuit320when the second context value CTX2is different from the first context value CTX1and the second previous context value PCTX2.

The second decoding circuit320may perform the second decoding operation based on one of the second context value CTX2, the second previous context value PCTX2, and the updated first context value UCTX1. In addition, after at least one of the first, second, third, and fourth decoding operations is performed, the second decoding circuit320may restore a fifth bin value based on one of the updated second context value UCTX2temporarily stored in the context keeper350, the updated fourth context value, and a fifth context value, and may update the fifth context value to generate an updated fifth context value.

The second multiplexer335bmay provide one of the third context value CTX3, the third previous context value PCTX3, and the updated first context value UCTX1to the third decoding circuit330based on the selection signal S2. An operation of the second multiplexer335bmay be similar to that of the first multiplexer325b.

The third decoding circuit330may perform the third decoding operation based on one of the third context value CTX3, the third previous context value PCTX3, and the updated first context value UCTX1. In addition, after at least one of the first, second, third, and fourth decoding operations is performed, the third decoding circuit330may restore a sixth bin value based on one of the updated third context value UCTX3temporarily stored in the context keeper350, the updated fourth context value, and a sixth context value, and may update the sixth context value to generate an updated sixth context value.

In some example embodiments, the decoding mode control signal DS and the selection signals S0, S1, and S2may be combined into a single signal.

AlthoughFIGS. 1 through 9illustrate examples where the multi-bin decoding operation is implemented for sequentially decoding two binary values, the video decoder10according to example embodiments of the present inventive concepts may be implemented for sequentially decoding more than two binary values. For example, in an example of the multi-bin decoding operation for sequentially decoding three binary values, a multi-bin decoding block300may include one decoding circuit for restoring a first binary value among the three binary values, two decoding circuits for restoring a second binary value among the three binary values, four decoding circuit for restoring a third binary value among the three binary values, and one bypass decoding circuit. In addition, in the example of the multi-bin decoding for sequentially decoding three binary values, at least one operation mode for outputting three binary values may be further included.

FIG. 10is a flow chart illustrating a method of operating a video decoder according to example embodiments of the present inventive concepts.

Referring toFIGS. 1, 2 and 10, in a method of operating the video decoder10according to example embodiments, an operation mode of the video decoder10and context values may be selected (step S100). For example, in the example of sequentially decoding two binary values using CABAC, one of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh operation modes may be selected based on the decoding mode control signal DS. The context index control block100and the context buffer200may select the first, second, and/or third context values CTX1, CTX2and/or CTX3by performing the context selection operation and the context model loading operation.

Based on the selected operation mode and/or the selected context values, a multi-bin decoding operation may be performed (step S200), and at least one of the bin values that are results of the multi-bin decoding operation may be output depending on the operation mode (step S300). For example, in the example of sequentially decoding two binary values using CABAC, the multi-bin decoding block300amay perform at least one of the first, second, third, and fourth decoding operations. The decoding mode control block400may output a result of at least one of the first, second, third, and fourth decoding operations based on the decoding mode control signal DS. The decoding mode control block400may output only the first bin value BOUT1, may output only the at least one bypass bin value BOUTBP, may output the first bin value BOUT1and the at least one bypass bin value BOUTBP, may output the first bin value BOUT1and one of the second and third bin values BOUT2and BOUT3, or may output at least one of the first, second, and third bin values BOUT1, BOUT2, and BOUT3based on the first bin value BOUT1.

After at least one of the bin values are output, the context values, ranges, and offsets may be updated (step S400). For example, the updated context value UCTX may be stored into the context buffer200based on at least one of the updated first, second, and third context values UCTX1, UCTX2, and UCTX3. The updated range URNG and the updated offset UOFS may be stored into the range/offset buffer500based on at least one of the ranges RNG1, RNG2, RNG3, and RNGA and at least one of the offsets OFS1, OFS2, OFS3, and OFSA.

It may be checked whether the results of the multi-bin decoding operation or the bin values obtained by steps S200and S300are valid (step S500). If it is determined that a bin string that is currently generated and includes current two bins is valid by the binarization matching operation (step S500: YES), a decoding operation for the current two bins is completed, and then a decoding operation for subsequent two bins may be performed. If it is determined that the bin string that is currently generated and includes the current two bins is invalid (step S500: NO), steps S100, S200, S300, and S400may be performed again for the current two bins.

As will be appreciated by those skilled in the art, the present inventive concepts may be embodied as a system, method, computer program product, and/or a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. The computer readable program code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may be any tangible medium that can store a program for use by and/or in connection with an instruction execution system, apparatus, and/or device. For example, the computer readable medium may be a non-transitory computer readable medium.

In some example embodiments, a video encoder and the video decoder according to example embodiments of the present inventive concepts may be merged in the same integration circuit and/or corresponding software, and then the merged device may be referred to as a video coder/decoder (codec).

FIG. 11is a block diagram illustrating an electronic system according to example embodiments of the present inventive concepts.

Referring toFIG. 11, an electronic system1000may include a video source1010and a video codec1020. The electronic system1000may further include at least one processor1030, a connectivity module1040, an input/output (I/O) device1050, and a power supply1060.

The video source1010provides an encoded bit stream. For example, the video source1010may include a storage device that pre-stores the encoded bit stream or downloads the encoded bit stream (e.g., from a content supply system or a cloud computing system) to store the downloaded encoded bit stream.

The video codec1020may include a video decoder according to example embodiments. The video decoder decodes the encoded bit stream to generate a restored, e.g., decoded, video. The video decoder may be the video decoder10ofFIG. 1, may include the multi-bin decoding block300, and may support a plurality of operation modes for sequentially decoding at least two bin values. Accordingly, the video codec1020may have a relatively increased decoding speed and enhanced performance, and may efficiently restore high quality videos. Though illustrated as separate elements inFIG. 11, it will be understood that, in some embodiments, the video codec1020may constitute executable code stored in a memory of the electronic system1000that may be executed by the at least one processor1030.

The at least one processor1030may control overall operations of the electronic system1000. The connectivity module1040may communicate with an external device (not shown). The I/O device1050may include at least one input device such as, for example, a keypad, a button, a microphone, a touch screen, etc., and/or at least one output device such as, for example, a speaker, a display device, etc. The power supply1060may provide power to the electronic system1000.

The present inventive concepts may be applied to various devices and systems that include the video decoder. For example, the present disclosure may be applied to systems such as be a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistants (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a wearable system, an internet of things (IoT) system, a three-dimensional (3D) geometry reconstruction system, an array camera system, a virtual reality (VR) system, an augmented reality (AR) system, etc.

It will be understood that although the terms “first,” “second,” etc. are used herein to describe members, regions, layers, portions, sections, components, and/or elements in example embodiments of the inventive concepts, the members, regions, layers, portions, sections, components, and/or elements should not be limited by these terms. These terms are only used to distinguish one member, region, portion, section, component, or element from another member, region, portion, section, component, or element. Thus, a first member, region, portion, section, component, or element described below may also be referred to as a second member, region, portion, section, component, or element without departing from the scope of the inventive concepts. For example, a first element may also be referred to as a second element, and similarly, a second element may also be referred to as a first element, without departing from the scope of the inventive concepts.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the inventive concepts pertain. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Like numbers refer to like elements throughout. Thus, the same or similar numbers may be described with reference to other drawings even if they are neither mentioned nor described in the corresponding drawing. Also, elements that are not denoted by reference numbers may be described with reference to other drawings.