Differential current buffer

Apparatus and methods provide a differential current buffer. The current buffer has cross-coupled feedback and offers relatively good common-mode rejection and a relatively low and linear input impedance, which can reduce intermodulation distortion. The current buffer can be used in, for example, an RF modulator, such as a quadrature modulator.

BACKGROUND

1. Field of the Invention

The invention generally relates to electronics, and in particular, to communications circuits.

2. Description of the Related Art

Communications circuits can exhibit certain input characteristics and certain output characteristics. For example, some devices may have current outputs, while others may have voltage outputs. Some devices may have current-driven inputs, whereas other devices may have voltage-driven inputs. Even when the input and output characteristics of devices apparently match, buffering may be used because of non-linearity in the input and/or output characteristics.

For example, a filter can be sensitive to the non-linearity of a load, such as a mixer. A buffer circuit can be used to isolate the non-linearity of the load from the filter, which could otherwise cause intermodulation distortion. Intermodulation distortion is typically an undesirable characteristic, as it can corrupt the spectrum and decrease the number of channels that can be carried by a signal to maintain a particular signal to noise ratio.

Thus, buffering circuits are relatively common in electronic circuits. Some buffering circuits can also convert from voltage to current or from current to voltage. Other buffering circuits simply buffer current or voltage.

FIG. 1illustrates an example of a conventional buffer circuit100. The buffer circuit100receives currents Iip, Iinas inputs and generates currents Iop, Ionas outputs. The buffer circuit100has resistors Ri102,104, transistors Q1-Q4, resistors Re106,108, and current sources110,112. The resistors Ri102,104form a current-to-voltage converter. The transistors Q1-Q4, the resistors Re106,108, and the current sources110,112form a voltage-to-current converter.

The current-to-voltage conversion operates as follows. The current through the bases of the transistors Q3, Q4is negligible compared to the current through the resistors Ri102,104. Thus, the input currents Iip, Iinflow through the resistors Ri102,104. The voltage drop across the resistors Ri102,104converts the input currents Iip, Iinto the voltages Vip, Vin.

The voltage-to-current conversion operates as follows. A voltage loop from the base of the transistor Q4, to the emitter of the transistor Q4, to the base of the transistor Q2, to the emitter of the transistor Q2, and across the resistor Re106is considered. The voltage at the base of the transistor Q4is the voltage Vip. The base to emitter of the transistor Q4adds a VBEvoltage, and the base to emitter of the transistor Q2subtracts a VBEvoltage. The circuit can be designed such that the two VBEvoltages approximately match and thus cancel. The voltage Vipthen appears across the resistor Re106, which then passes a current of the voltage Vip divided by the resistance Re. Assuming that the collector current Iopof the transistor Q2is about the same as the emitter current of Q2, which flows through the resistor Re106, then the collector current Iopis approximately equal to the voltage Vip divided by the resistance Re. The approximate relationship between the output current Iopand the input current Iipis expressed in Eq. 1.

The currents Iin, Ionand the voltage Vincan be analyzed in the same manner. The current sources110,112provide biasing for operation.

SUMMARY OF THE DISCLOSURE

The invention includes a differential current buffer. The current buffer has cross-coupled feedback and offers relatively good common-mode rejection and a relatively low and linear input impedance, which can reduce intermodulation distortion. The current buffer can be used in, for example, a radio frequency (RF) modulator, such as a quadrature modulator.

One embodiment includes an apparatus, which includes: a first current buffer comprising: a first input configured to receive a non-inverted input signal current; a second input configured to receive an inverted input signal current; a first transistor of a first type, the first transistor having a base, an emitter, and a collector or a gate, a source, and a drain, wherein the base or gate of the first transistor is coupled to the first input; a second transistor of the first type, the second transistor having a base, an emitter, and a collector or a gate, a source, and a drain, wherein the base or gate of the second transistor is coupled to the second input; a first current source having an end coupled to the emitter or source of the first transistor; a second current source having an end coupled to the emitter or source of the second transistor; a first resistor having a first end coupled to the base or gate of the first transistor and a second end coupled to a reference voltage; a second resistor having a first end coupled to the base or gate of the second transistor and a second end coupled to the reference voltage; a third transistor of a second type different from the first type, the third transistor having a base, an emitter, and a collector or a gate, a source, and a drain, wherein the base or gate of the third transistor is coupled to the emitter or source of the first transistor, wherein the emitter or source of the third transistor is coupled to the base or gate of the second transistor, wherein the collector or drain of the third transistor is configured to provide a non-inverted output current signal; and a fourth transistor of the second type, the fourth transistor having a base, an emitter, and a collector or a gate, a source, and a drain, wherein the base or gate of the fourth transistor is coupled to the emitter or source of the second transistor, wherein the emitter or source of the fourth transistor is coupled to the base or gate of the first transistor, wherein the collector or drain of the fourth transistor is configured to provide an inverted output current signal.

One embodiment includes an apparatus, which includes: a first current buffer comprising: a first buffer circuit comprising at least an input stage cascaded with an output stage, wherein the input stage has a first input node configured to receive a non-inverted input signal current of a differential input signal, wherein the output stage has a low-impedance node and a first output node, wherein the output stage is configured to generate a non-inverted output signal at the first output node; a second buffer circuit comprising at least an input stage cascaded with an output stage, wherein the input stage has a second input node configured to receive an inverted input signal current of the differential input signal, wherein the output stage has a low-impedance node and a second output node, wherein the output stage is configured to generate an inverted output signal at the second output node; and a cross-coupled feedback circuit configured to connect the low-impedance node of the second buffer circuit to the first input node and to connect the low-impedance node of the first buffer circuit to the second input node such that the first node and the second node are configured to have input impedances less than input impedances without the presence of the cross-coupled feedback circuit.

One embodiment includes an apparatus, which includes: a first current buffer comprising: a first buffer circuit comprising at least an input stage cascaded with an output stage, wherein the input stage has a first input node configured to receive a non-inverted input signal current of a differential input signal, wherein the output stage has a low-impedance node and a first output node, wherein the output stage is configured to generate a non-inverted output signal at the first output node; a second buffer circuit comprising at least an input stage cascaded with an output stage, wherein the input stage has a second input node configured to receive an inverted input signal current of the differential input signal, wherein the output stage has a low-impedance node and a second output node, wherein the output stage is configured to generate an inverted output signal at the second output node; and a means for cross-coupling feedback from the low-impedance node of the second buffer circuit to the first input node and from the low-impedance node of the first buffer circuit to the second input node such that an input impedance of the first node and an input impedance of the second node are less than the input impedances without the presence of the cross-coupled feedback circuit.

One embodiment includes a method for buffering current, the method including: receiving a non-inverted input signal current of a differential input signal at a first input node of an input stage of a first buffer circuit, wherein the first buffer circuit further comprises an output stage cascaded with the input stage, wherein the output stage has a low-impedance node and a first output node; generating a non-inverted output signal at the first output node from the non-inverted input signal current; receiving an inverted input signal current of the differential input signal at a second input node of an input stage of a second buffer circuit, wherein the second buffer circuit further comprises an output stage cascaded with the input stage, wherein the output stage has a low-impedance node and a second output node; generating an inverted output signal at the second output node from the inverted input signal current; and cross-coupling feedback from the low-impedance node of the second buffer circuit to the first input node and from the low-impedance node of the first buffer circuit to the second input node such that an input impedance of the first node and an input impedance of the second node are less than the input impedances without the presence of the cross-coupled feedback circuit.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Although particular embodiments are described herein, other embodiments of the invention, including embodiments that do not provide all of the benefits and features set forth herein, will be apparent to those of ordinary skill in the art. In this description, reference is made to the drawings in which like reference numerals indicate identical or functionally similar elements.

FIG. 2illustrates a current buffer200according to an embodiment of the invention. The illustrated current buffer200includes a first PNP bipolar transistor202, a second PNP bipolar transistor204, a first NPN bipolar transistor206, a second NPN bipolar transistor208, a first current source210, a second current source212, a first resistor214, and a second resistor216. In the illustrated embodiment, the resistors Ri102,104(FIG. 1) are not present, which helps to reduce thermal noise.

In one embodiment, the bipolar transistors are fabricated using a silicon-germanium process. An alternative mirror image embodiment is also applicable and can be implemented by exchanging the PNP bipolar transistors for NPN bipolar transistors, exchanging the NPN bipolar transistors for PNP bipolar transistors, reversing the direction of the current sources, and exchanging the voltage supplies VDDand VSS. In addition, while illustrated in the context of bipolar transistors, the principles and advantages described herein are also applicable to MOS transistors, wherein PMOS transistors are substituted for the PNP bipolar transistors and NMOS transistors are substituted for the NPN bipolar transistors for either the illustrated embodiment or the alternative mirror image embodiment such that a gate, a source, and a drain of a MOS transistor substitutes for a base, emitter, and a collector of a bipolar transistor. In addition to silicon bipolar transistors, the principles and advantages described herein are also applicable to heterojunction bipolar transistors (HBTs), such as GaAs HBTs and InP HBTs.

Certain components should be matched. Pairs that should be matched include the first PNP bipolar transistor202and the second PNP bipolar transistor204, the first NPN bipolar transistor206and the second NPN bipolar transistor208, the first current source210and the second current source212, and the first resistor214and the second resistor216. In addition, the base-emitter voltage VBEdrops of the NPN transistors and the PNP transistors should approximately match for relatively good cancellation of the base-emitter voltage VBEdrops.

Returning now to the illustrated embodiment, the current buffer200has a first input receiving a non-inverted input signal with current IIPand voltage VIP, a second input receiving an inverted input signal with current IINand voltage VIN, and generates a non-inverted output current signal IOPand an inverted output current signal ION.

The base of the first PNP bipolar transistor202is coupled to the first input. The emitter of the first PNP bipolar transistor202is coupled to a first end the first current source210and to the base of the first NPN bipolar transistor206. The second end of the first current source210is coupled to a power supply voltage VDD, which can be, for example, about 5 volts. The collector of the first PNP bipolar transistor202is coupled to the power supply voltage VSS, which can be ground.

The base of the second PNP bipolar transistor204is coupled to the second input. The emitter of the second PNP bipolar transistor204is coupled to a first end of the second current source212and to the base of the second NPN bipolar transistor208. The second end of the second current source212is coupled to a power supply voltage VDD. The collector of the first PNP bipolar transistor202is coupled to the power supply voltage VSS, which can be ground.

The emitter of the second NPN bipolar transistor208is coupled to a first end of the first resistor214, and the collector of the second NPN bipolar transistor208provides the inverted output current signal ION. The emitter of the first NPN bipolar transistor206is coupled to a first end of the second resistor216, and the collector of the first NPN bipolar transistor206provides the non-inverted output current signal IOP.

In addition, the node that connects the emitter of the second NPN bipolar transistor208and the first end of the first resistor214is cross-coupled to the first input node, which includes the base of the first PNP bipolar transistor202. The node that connects the emitter of the first NPN bipolar transistor206and the first end of the second resistor216is cross-coupled to the second input node, which includes the base of the second PNP bipolar transistor204. This cross-coupling is new and the operation of the new circuit configuration is described as follows.

For the following analysis, each of the first resistor214and the second resistor216are assumed to have the same resistance RE. In one embodiment, the value of the resistance REis about 25 ohms. However, the value of the resistance REcan vary in a very broad range and can be, for example, in a range from about 1 to 10,000 ohms, alternatively from about 5 ohms to about 5,000 ohms, or alternatively in a range of about 2 ohms to about 2,000 ohms. The power supply voltage VSSis assumed to be ground. The current sources210,212are matched, the PNP transistors202,204are matched, and the NPN transistors206,208are matched. In addition, base currents of the transistors202,204,206,208are considered to be negligible.

The voltages VIPand VINat the input nodes should be defined by the voltage drops across the first resistor214and the second resistor216, respectively. Ignoring base currents, the voltages VIPand VINare then as expressed in Eq. 2 and Eq. 3.
VIP=(IIP+ION)REEq. 2
VIN=(IIN+IOP)REEq. 3

Eq. 4 expresses the voltage around the loop from the second input node with voltage VINto the first input node with voltage VIP. A positive base-emitter voltage is encountered from the base to the emitter of the second PNP transistor204, then a negative base to emitter voltage is encountered from the base to the emitter of the second NPN bipolar transistor208, and then the loop encounters the first input node with voltage VIP, as expressed in Eq. 4. The positive and the negative base-emitter voltages should at least approximately cancel out, and it can be observed that the input voltage VIPat the first input node and the input voltage VIN at the second input node VINshould be about equal.
VIN=VBE−VBE+VIP=VIPEq. 4

Since the input voltages VIP, VINare equal, the expressions to the right in Eq. 2 and Eq. 3 are also equal, as expressed in Eq. 5.
(IIN+IOP)RE=(IIP+ION)REEq. 5

Rearranging terms, it can be observed that the differential output current IOPminus IONis equal to the differential input current IIPminus IIN, as expressed in Eq. 7. As illustrated in Eq. 7, the current buffer200exhibits relatively good common mode signal rejection characteristics.
IOP−ION=IIP−IINEq. 7

FIG. 3illustrates an enhanced current buffer300. In the enhanced current buffer300, the resistors302,304are added to the current buffer200. The resistors302,304should be matched to each other. An ideal characteristic for a current buffer would be for the input to look like a short circuit. However, it can sometimes be more important to have a linear input impedance rather than the lowest possible input impedance. For example, an LC filter can be provided at outputs of a digital-to-analog converter with current outputs, and the filtered current can be provided as an input to the current buffer300. Non-linearities in the input impedance of the current buffer300can result in intermodulation distortion, and the addition of some real resistance increases the linearity of the input impedance, thereby decreasing intermodulation distortion. In one embodiment, the resistors302,304have a resistance of about 2.5 ohms each. Other values for the resistance can be used and will be readily determined by one of ordinary skill in the art. For example, a range of resistance from about 1 ohm to about 100 ohms can be applicable. In another example, the resistors302,304have a resistance in the range of about 1 ohm to about 10 ohms. In addition, it should be noted that the resistors302,304correspond to explicit resistance and not to mere parasitic resistance.

FIG. 4illustrates an example of a quadrature modulator400embodying two current buffer circuits402,404. Of course, a simple radio frequency (RF) modulator without quadrature can also be implemented. The quadrature modulator400further includes a first mixer406, a second mixer408, a summing circuit410, and a differential-to-single-ended stage412. The quadrature modulator400can be fabricated on an integrated circuit. The current buffer circuits402,404can correspond to either the current buffer200or the current buffer300described earlier in connection withFIGS. 2 and 3. The inputs can be either baseband or intermediate frequency. The first current buffer circuit402receives a first baseband input signal IBBP, IBBN in differential form intended for the in-phase channel. The second current buffer circuit404receives a second baseband input signal QBBP, QBBN in differential form intended for the quadrature-phase channel. A typical source for the first baseband input signal IBBP, IBBN or the second baseband input signal QBBP, QBBN is a digital-to-analog converter with current outputs. There can also be LC filters disposed in the signal path between the digital-to-analog converters and the current buffer circuits402,404.

The current-mode outputs of the first current buffer circuit402and the second current buffer circuit404are provided as inputs to a first mixer406and to a second mixer408. The mixers406,408can be double-balanced mixers and implemented by Gilbert cells. The first mixer406is driven by an in-phase local oscillator signal LOI, and the second mixer408is driven by a quadrature-phase local oscillator signal LOQ. The quadrature modulator400can further include a phase splitter for generating one of the LOI signal or the LOQ signal from the other.

The mixers406,408operate at higher speeds than the current buffer circuits402,404. Accordingly, in one embodiment, the mixers406,408are implemented with NPN bipolar transistors or with NMOS transistors for better speed than with PNP bipolar transistors or with PMOS transistors, the transistors204,202(FIG. 2) are implemented with PNP bipolar transistors or with PMOS transistors, and the transistors206,208(FIG. 2) are implemented with NPN bipolar transistors or with NMOS transistors. In an alternative embodiment (not shown), the mixers406,408are implemented with PNP bipolar transistors or with PMOS transistors, the transistors204,202(FIG. 2) are implemented with NPN bipolar transistors or with NMOS transistors, and the transistors206,208(FIG. 2) are implemented with PNP bipolar transistors or with PMOS transistors, with reversal of current direction and swapping of power supply biases.

The outputs of the mixers406,408can be differential currents. These currents can be summed in a load by the summing circuit410to generate a quadrature-modulated signal, which can then be converted from differential form to single-ended form by the a differential-to-single-ended stage412and then provided as an output for, for example, power amplification.

Embodiments of the invention exhibit improved linearity and reduced intermodulation distortion, reduced thermal noise, and improved common-mode rejection characteristics. These improvements can, for example, be used to increase the dynamic range performance and improve the spectral purity of the output of an RF modulator, such as quadrature modulator, incorporating the buffer circuits. Of course, the use of current buffer circuits is ubiquitous and the current buffer circuits can be used in other devices, such as, but not limited to analog-to-digital converters, digital-to-analog converters, demodulators, and as the input for baseband, IF, and RF amplifiers.

The foregoing description and claims may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated to the contrary, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated to the contrary, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the drawings illustrate various examples of arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment.

As used herein, a “node” refers to any internal or external reference point, connection point, junction, signal line, conductive element, or the like at which a given signal, logic level, voltage, data pattern, current, or quantity is present.

The MOS transistors described herein can correspond to transistors known as metal-oxide-semiconductor field-effect transistors (MOSFETs). While the terms “metal” and “oxide” are present in the name of the device, it will be understood that these transistors can have gates made out of materials other than metals, such as polysilicon, and that the dielectric oxide region can also be implemented not just with silicon oxide, but with other dielectrics, such as high-k dielectrics.

Various embodiments have been described above. Although described with reference to these specific embodiments, the descriptions are intended to be illustrative and are not intended to be limiting. Various modifications and applications may occur to those skilled in the art.