Methods of fabricating semiconductor devices including storage node landing pads separated from bit line contact plugs

A method can include forming gate lines on a semiconductor substrate and forming a first interlayer dielectric layer for insulating the gate lines from each other. First and second contact plugs are formed on the semiconductor substrate and landing pads are formed on the first contact plugs and the first interlayer dielectric layer to overlap portions of the first contact plugs. Recessed contact plugs are formed to have recessed portions by etching the second contact plugs, to be located below an upper surface of the first interlayer dielectric layer, where a cross-sectional total distance between the landing pads and the recessed contact plugs increases due to the recessed portions.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application claims the benefit of Korean Patent Application No. 10-2008-0033874, filed on Apr. 11, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

FIELD OF THE INVENTION

The present invention relates to methods of fabricating a semiconductor device, and more particularly, to methods of fabricating a semiconductor device including contact plugs.

BACKGROUND

In general, semiconductor devices can include wires for electrically connecting separate devices, such as transistors or capacitors, to each other. The wires can contact the separate devices via contact plugs that penetrate an interlayer dielectric layer.

SUMMARY

In some embodiments according to the present invention, a method includes forming gate lines on a semiconductor substrate and forming a first interlayer dielectric layer for insulating the gate lines from each other. First and second contact plugs are formed on the semiconductor substrate and landing pads are formed on the first contact plugs and the first interlayer dielectric layer to overlap portions of the first contact plugs. Recessed contact plugs are formed to have recessed portions by etching the second contact plugs, to be located below an upper surface of the first interlayer dielectric layer, where a cross-sectional total distance between the landing pads and the recessed contact plugs increases due to the recessed portions.

DESCRIPTION OF EMBODIMENTS ACCORDING TO THE INVENTION

It will be understood that when an element, such as a layer, is referred to as being “connected to,” “coupled to” or “responsive to” (and/or variants thereof) another element, it can be directly connected, coupled or responsive to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected to,” “directly coupled to” or “directly responsive to” (and/or variants thereof) another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising” (and/or variants thereof), when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” (and/or variants thereof) when used in this specification, specifies the stated number of features, integers, steps, operations, elements, and/or components, and precludes additional features, integers, steps, operations, elements, and/or components.

In some embodiments according to the present invention, a large capacity dynamic random access memory (DRAM) is described as an example of the semiconductor device; however, embodiments according to the present invention are not limited thereto. Each of a plurality of memory cells in the DRAM device includes an access transistor and a capacitor. The access transistor includes a gate line and source/drain electrodes formed on a semiconductor substrate, and the capacitor includes a storage node (storage electrode), a dielectric layer, and a plate electrode. The source/drain electrodes are respectively connected to the storage node or bit lines via first and second contact plugs that penetrate an interlayer dielectric layer on the semiconductor substrate.

In some embodiments according to the present invention, a landing pad is located on a first contact plug connected to a storage node in order to increase a contact area between the first contact plug and a storage node contact plug. However, as appreciated by the present inventors, as the semiconductor device becomes more highly integrated, a distance between the first contact plug connected to the storage node and a second contact plug connected to a bit line can decrease, and thus, electrical shorts may be generated between the landing pad, on the first contact plug connected to the storage node, and the second contact plug connected to the bit line. In some embodiments according to the present invention, the second contact plug connected to the bit line, on which a landing pad is not formed, is recessed to form a recessed contact plug, which may reduce the risk of electrical shorts therebetween.

In other words, in some embodiments according to the present invention, an upper surface of the second contact plug (connected to the bit line) is recessed below a lower surface of the landing pad connected to the storage node. The lower surface of the landing pad can face the upper surface of the second contact plug. Furthermore, an upper surface of the first contact plug (on which the lower surface of the landing pad is formed) is above the upper surface of the second contact plug, so that the upper surface of the second contact plug is recessed below both the lower surface of the landing pad and the upper surface of the first contact plug. Therefore, in some embodiments according to the present invention, a total distance between the first contact plug/landing pad and the second contact can be increased even as the spacing between devices is reduced. In some embodiments according to the present invention, the total distance includes a lateral and a vertical spacing. In other words, in some embodiments according to the present invention, the upper surface of the second contact can have increased spacing both the lateral and vertical directions.

In some embodiments according to the present invention, a contact plug is recessed to reduce electrical shorts between a landing pad that is formed on an immediately adjacent one of the contact plugs. In particular, a recessed contact plug can be formed simultaneously with the landing pad using the same process, and thus, electrical shorts between the landing pad and the contact plug can be reduced without performing an additional process for forming the recessed contact plug.

FIG. 1is a schematic cross-sectional view of a semiconductor device in some embodiments according to the present invention. Referring toFIG. 1, the semiconductor device of the present embodiment includes a device isolation layer102and active regions103formed in a semiconductor substrate101, for example, a silicon substrate. A gate insulating layer106and gate lines108(word lines) are formed on the active regions103. Each of the gate lines108includes a gate electrode (not shown) formed on the gate insulating layer106and a capping layer (not shown) covering the gate electrode.

A first interlayer dielectric layer110for insulating the gate lines108from each other is formed on the entire surface of the semiconductor substrate101, on which the gate lines108are formed. First contact plugs114and recessed contact plugs126that contact the active region103between the gate lines108by penetrating the first interlayer dielectric layer110are formed. Each of the recessed contact plugs126has a recessed portion124, wherein the recessed contact plugs126are disposed lower than an upper surface of the first interlayer dielectric layer110. The first contact plugs114are contact plugs that are electrically connected to storage node contact plugs. The recessed contact plugs126are contact plugs that are electrically connected to bit line contact plugs.

Landing pads122are formed as islands on the first contact plugs114and the first interlayer dielectric layer110so as to overlap a part of the first contact plugs114. The landing pads122are connected to respective storage node contact plugs134. The landing pads122are formed to increase a contact area between the first contact plugs114and the storage node contact plugs134. That is, the landing pads122are formed so as to increase the contact area between the first contact plugs114and the storage node contact plugs134when the first contact plugs114and the storage node contact plugs134deviate from each other vertically.

In particular, in some embodiments according to the present invention, a cross-sectional distance between the landing pads122and the recessed contact plugs126increases due to the recessed portions124as shown in reference numeral127. The distance can include both a lateral spacing shown by “a” and a vertical spacing shown by “b” inFIG. 1. That is, if the plug126were not recessed, the distance between the landing pads122and the plug126is “a”; however, in some embodiments according to the present invention, the total distance between the landing pads122and the recessed contact plugs126includes “a”+“b” due to the recessed portions124. Therefore, electrical shorts between the landing pads122and the recessed contact plugs126can be reduced despite when the semiconductor device is highly integrated.

A second interlayer dielectric layer128is formed on the entire surface of the semiconductor device, on which the first contact plugs114and the recessed contact plugs126are formed. Then, the second interlayer dielectric layer128is etched to form contact holes129exposing the upper surfaces of the recessed contact plugs126. Accordingly, third contact plugs130that are connected to the recessed contact plugs126by penetrating the contact holes129are formed. The third contact plugs130are bit line contact plugs that are connected to a bit line132.

Hereinafter, methods of fabricating the semiconductor device ofFIG. 1in some embodiments according to the invention will be described in detail.FIGS. 2 through 12are schematic cross-sectional and plan views illustrating methods of fabricating a semiconductor device, in some embodiments according to the present invention. Here, the semiconductor device is a DRAM device, as an example.FIGS. 2 through 12illustrate an exemplary method of fabricating the semiconductor device, and the present invention is not limited thereto.

Referring toFIGS. 2 and 3,FIG. 2is a plan view of the semiconductor device, andFIG. 3is a cross-sectional view of the semiconductor device taken along a line III-III ofFIG. 2. Referring toFIG. 3, device isolation layers102are formed in a semiconductor substrate101, for example, a silicon substrate, to define a plurality of active regions103. Referring toFIG. 2, the active regions103are formed on a plane, and the device isolation layers102are formed between the active regions103. The device isolation layers102may be formed using a shallow trench isolation method.

A gate insulating layer106is formed on the active regions103of the semiconductor substrate101. In addition, a plurality of gate lines108(word lines) are formed to cross the active regions103of the semiconductor substrate101. Each of the gate lines108includes a gate electrode (not shown) formed on a gate insulating layer, and a capping layer (not shown) covering the gate electrode. The gate lines108may be formed by depositing a polysilicon layer pattern and a metal silicide layer pattern, and may include spacers on both sidewalls of the gate electrodes.

Referring toFIG. 3, a first interlayer dielectric layer110insulating the gate lines108is formed on the entire surface of the semiconductor substrate101, on which the gate lines108are formed. The first interlayer dielectric layer110may include silicon oxide. In addition, first contact plugs114and second contact plugs112, which are respectively connected to the active regions103between the gate lines108by penetrating the first interlayer dielectric layer110, are formed. The first and second contact plugs114and112may be polysilicon layers doped with impurities. The first contact plugs114are electrically connected to storage node contact plugs subsequently. The second contact plugs112are electrically connected to bit lines contact plugs subsequently.

Referring toFIGS. 4 and 5, a conductive layer116for forming landing pads is formed on the first contact plugs114, the second contact plugs,112, and the first interlayer dielectric layer110. The conductive layer116for the landing pads may comprise a polysilicon layer doped with impurities or a metal layer such as a tungsten layer. When the conductive layer116for the landing pads comprises a metal layer such as a tungsten layer, contact resistance between the conductive layer116and fourth contact plugs (134ofFIG. 12) may decrease, and the polysilicon layer forming the second contact plugs112can be subsequently etched. Referring toFIG. 5, a mask layer118for forming the landing pads is formed on the conductive layer116. The mask layer118for forming the landing pads is formed to expose upper portions of the second contact plugs112. The mask layer118for the landing pads may be formed using a photolithographic process.

FIG. 6is a plan view of the semiconductor device, andFIG. 7is a cross-sectional view of the semiconductor device taken along a line VII-VII ofFIG. 6. As denoted by reference numeral120, the conductive layer116for forming the landing pads is etched using the mask layer118as an etching mask. The conductive layer116may be etched using a dry etching method. Then, landing pads122are formed as islands overlapping portions of the first contact plugs114, and upper surfaces of the second contact plugs112are exposed.

Referring toFIG. 8, the second contact plugs112are etched using the mask layer118as an etching mask to form the recessed contact plugs126having recessed portions124(also referred to herein as “recesses124”), so that the upper surfaces of the recessed contact plugs126are located below the upper surface of the first interlayer dielectric layer110. After forming the recessed contact plugs126, the mask layer118for forming the landing pads122is removed.

In some embodiments according to the present invention, according toFIG. 5-8for example, the conductive layer116and the underlying second contact plugs112are etched simultaneously to form the recessed contact plugs126. Accordingly, the recessed contact plugs126can be formed without performing an additional fabrication step.

In particular, the total distance between the landing pads122and the recessed contact plugs126can be increased due to the recesses124above the upper surfaces of the recessed contact plugs126as denoted by the portion ofFIG. 8associated with reference numeral127. Accordingly, electrical shorts between the landing pads122and the recessed contact plugs126can be reduced.

FIG. 9is a plan view of the semiconductor device, andFIG. 10is a cross-sectional view of the semiconductor device taken along a line X-X ofFIG. 9in some embodiments according to the present invention. Referring toFIG. 9, a planar (sometimes referred to herein as “lateral”) distance between the landing pads122and the recessed contact plugs126is represented as “a.” Accordingly, the recesses124are formed to increase the total cross-sectional distance between the landing pads122and the recessed contact plugs126.

Referring toFIGS. 9 and 10, a second interlayer dielectric layer128is formed on the entire surface of the semiconductor substrate101, on which the first contact plugs114, the landing pads122, and the recessed contact plugs126are formed. The second interlayer dielectric layer128may be formed of a silicon oxide. The landing pads122and the recessed contact plugs126are insulated from each other by the second interlayer dielectric layer128. Contact holes129exposing the upper surfaces of the recessed contact plugs126are formed by penetrating the second interlayer dielectric layer128.

In addition, third contact plugs130that are connected to the recessed contact plugs126are formed. The third contact plugs130are bit line contact plugs that are subsequently connected to bit lines. Next, bit lines132contacting the third contact plugs130are formed. The bit lines132are formed in a direction perpendicular to the direction in which the gate lines108are formed.

FIG. 11is a plan view of the semiconductor device, andFIG. 12is a cross-sectional view of the semiconductor device taken along a line XII-XII ofFIG. 11in some embodiments according to the present invention. Referring toFIGS. 11 and 12, fourth contact plugs134that are connected to the landing pads122by penetrating the second interlayer dielectric layer128are formed. The fourth contact plugs134are storage node contact plugs that are subsequently connected to storage nodes (not shown).

FIGS. 13 through 19are schematic cross-sectional and plan views illustrating methods of fabricating a semiconductor device, in some embodiments according to the present invention. The semiconductor device ofFIGS. 13 through 19is a DRAM semiconductor device, as an example.FIGS. 13 through 19illustrate an exemplary method of fabricating the semiconductor device, and the present invention is not limited thereto.

In some embodiments according to the present invention, the fabrication steps of the method of fabricating the semiconductor device are the same as those illustrated byFIGS. 1-3except for forming the recessed contact plugs126. Therefore, after performing the fabrication steps illustrated byFIGS. 1-3, the following steps can be performed.

FIG. 13is a plan view of the semiconductor device of the present embodiment, andFIG. 14is a cross-sectional view of the semiconductor device taken along a line XIX-XIX ofFIG. 13in some embodiments according to the present invention. Referring toFIGS. 13 and 14, a mask layer202for forming recessed contact plugs and exposing the second contact plugs112is formed on the first contact plugs114and the first interlayer dielectric layer110. As denoted by reference numeral204, the second contact plugs112are etched using the mask layer202as an etching mask to form the recessed contact plugs126having the recesses124thereon. In addition, the mask layer202is removed.

Referring toFIGS. 15 and 16, buried insulating layers206that fill in the recesses124are formed. The buried insulating layers206are formed by forming an insulating layer on the entire surface of the semiconductor substrate101so as to fill the recesses124, and then, planarizing the formed insulating layer. In addition, as illustrated inFIG. 16, the conductive layer116for forming the landing pads is formed on the first contact plugs114, the buried insulating layer206, and the first interlayer dielectric layer110.

FIG. 17is a plan view of the semiconductor device, andFIG. 18is a cross-sectional view of the semiconductor device taken along a line XVII-XVII ofFIG. 17in some embodiments according to the present invention. Referring toFIGS. 17 and 18, a mask layer208for forming the landing pads is formed on the conductive layer116for the landing pads. The mask layer208is absent from portions of the substrate110so that the upper portions (or surfaces) of the buried insulation layers206are exposed.

In addition, the conductive layer116is etched using the mask layer208as an etching mask as denoted by arrows210so as to form the landing pads122that overlap portions of the first contact plugs114. Then, the mask layer208for forming the landing pads is removed. In some embodiments according to the present invention, the buried insulation layers206are removed simultaneously with the conductive layer116(exposed outside the mask208) or are removed simultaneously with the mask208, or are removed separately before or after removal of the mask208.

Referring toFIG. 19, the second interlayer dielectric layer128is formed on the entire surface of the semiconductor substrate101, on which the first contact plugs114, the landing pads122, and the buried insulating layers206are formed. In addition, the contact holes129are formed by penetrating the second interlayer dielectric layer128to expose the upper surfaces of the recessed contact plugs126. In some embodiments according to the invention, the buried insulation layers206are removed with the second interlayer dielectric layer128to expose the upper surfaces of the recessed contact plugs126. Next, the third contact plugs130that contact the recessed contact plugs126are formed. The third contact plugs130are bit line contact plugs that are subsequently connected to bit lines. In addition, the bit lines132contacting the third contact plugs130are formed.

After that, the fourth contact plugs134that are connected to the landing pads122by penetrating the second interlayer dielectric layer128are formed as illustrated inFIGS. 11 and 12. The fourth contact plugs134are storage node contact plugs that are subsequently connected to storage nodes (not shown).

The semiconductor device according to the present invention includes landing pads formed on first contact plugs in order to increase the contact area between the first contact plugs and storage node contact plugs. In addition, according to the present invention, second contact plugs connected to bit lines, on which landing pads are not formed, are recessed to form recessed contact plugs in order to reduce the likelihood of electrical shorts.

Accordingly, the cross-sectional total, lateral and vertical, distance between the landing pads and the recessed contact plugs can be increased due to the recessed portions, and thus, electrical shorts between the landing pads and the recessed contact plugs can be reduced despite when the semiconductor device is highly integrated.