Semiconductor structure and manufacturing method

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a gate structure, a spacer structure and a source/drain structure that are formed on a surface of the semiconductor layer. The gate structure includes a dielectric structure, a metal structure and an insulator structure. The dielectric structure is formed on the surface of the semiconductor layer. A bottom of the metal structure contacts a top of the dielectric structure. The bottom of the insulator structure contacts a top of the metal structure and the insulator structure protrudes over the top of the metal structure. The spacer structure is configured to extend underneath the bottom of the insulator structure and contact a sidewall of the metal structure. The spacer structure is configured to space between the gate structure and the source/drain structure. The source/drain structure includes a source/drain doped structure, a silicide structure and a metal contact plug.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. The introduction of gate stack materials, such as high dielectric constant (high-k) gate insulator layers, metal gate (MG) electrode, and the like has enable the resumption of Moore's law as technology nodes shrink. The high-k/MG gate stack materials can be integrated in a gate-first process or a gate-last process. In a gate-first process, the gate structure is formed before a formation of the source-drain structure. In a gate-last process, the gate structure is formed after a formation of the source-drain structure.

DETAILED DESCRIPTION

Aspects of the disclosure provide a gate-first process that forms mandrel structures of reversed gate patterns, thus recess portions that are surrounded by the mandrel structures are of the gate patterns. Then, the gate-first process utilizes process steps that are similar to gate-last metal fill process steps to form the gate structures at the recess portions. After the formation of the gate structures at the recess portions, the mandrel structures are removed, and then the gate-first process continues to form spacer structures and to form the source/drain structures. Accordingly, in an example, the gate-first process achieves the benefit of the gate-last metal fill advantages, such as straighter gate profile, dual metal patterning, no metal etching and the like. In addition, in some embodiments, the gate-first process allows a self-aligned formation of source/drain structures. In some embodiments, the mandrel structures have relatively large aspect ratio compared to a related gate-last example that uses mandrel structures of gate patterns, thus mandrel structure bending and collapse issues are of less concern in the present disclosure.

FIG. 1shows a cross sectional view of a semiconductor device100that is fabricated by a gate-first process in accordance with some embodiments.

The semiconductor device100refers to any suitable device, for example, one or more transistors, integrated circuits (e.g., memory circuits and/or logic circuits), a semiconductor chip (or die) with integrated circuits formed on the semiconductor chip, a semiconductor wafer with multiple semiconductor dies formed on the semiconductor wafer, a stack of semiconductor chips, a semiconductor package that includes one or more semiconductor chips assembled on a package substrate, and the like.

In theFIG. 1example, the semiconductor device100includes a transistor101formed in an active region on a semiconductor layer110. The transistor101includes a gate structure103, source/drain (SD) structures105and spacer structures104between the gate structure103and the SD structures105.

In an example, the semiconductor layer110includes an elementary semiconductor, such as silicon or germanium in crystal, polycrystalline, or an amorphous structure. In another example, the semiconductor layer110includes a compound semiconductor, such as gallium arsenic, gallium phosphide, silicon carbide, indium phosphide, indium arsenide, and/or indium antimonide. In another example, the semiconductor layer110includes an alloy semiconductor, such as SiGe, GaAsP, AlGaAs, AlinAs, GalnAs, GaInP, and/or GaInAsP. In some embodiments, the semiconductor layer110has a fin structure, and the transistor101is referred to as a fin field effect transistor (FinFET).

FIG. 2is a perspective view of the semiconductor device100in accordance with some embodiments. The semiconductor device100includes a substrate201with semiconductor fins110disposed above the substrate201. In some embodiments, the substrate201is an insulating layer, and the semiconductor fins110are partially embedded in the insulating layer. In some examples, the substrate201is semiconductor substrate with the semiconductor fins110that are formed on the substrate201. The semiconductor fins110are separated by an isolation structure202, such as shallow trench isolation (STI), and the like. The semiconductor fin110can be formed of any suitable semiconductor material, such as silicon, silicon-germanium, germanium, and the like. The gate structure103is formed over a top surface and sidewalls of the semiconductor fin110. In some examples, spacer structures104and the SD structures105are also formed over the top surface and sidewalls of the semiconductor fin110. Thus, the channel of the transistor101is defined along the top surface and sidewalls of the semiconductor fin110, and is extended between SD structures105in the semiconductor fin110.FIG. 1corresponds to a cross sectional view of the semiconductor fin110along a line A-A′ in an embodiment.

Referring back toFIG. 1, the gate structure103includes a dielectric structure120, a metal gate (MG) electrode structure130(also referred to as metal structure in some examples) and a self-aligned contact (SAC) hard mask structure140(also referred to as insulator structure in some examples).

The dielectric structure120includes one or more gate insulator layers. In some embodiments, at least one of the gate insulator layers has a relative large dielectric constant, such as higher than 3.9 (silicon dioxide dielectric constant), and is referred to as high-k dielectric layer. In theFIG. 1example, the dielectric structure120includes an interfacial layer122that is formed on the surface of the semiconductor layer110, and a high-k dielectric layer124that is formed between the interfacial layer122and a bottom of the MG electrode structure130. Initially, the high-k dielectric layer124is formed to have a U-shape that includes vertical portions124′ that are in direct contact with sidewalls of the MG electrode structures130. The vertical portions124′ are etched away in an etching process and are subsequently replaced with spacer material in a spacer deposition step.

In some embodiments, the interfacial layer122is formed to provide high quality interface (e.g., SiO2/Si interface). In an embodiment, the interfacial layer122is thermally oxidized and grown dielectric (e.g., silicon dioxide), and is formed on the exposed surface of the semiconductor layer110. In another embodiment, the interfacial layer122is formed by deposition, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and the like, thus the interfacial layer122initially has the U shape and vertical portions of the U shape are then etched away, in a similar manner as the high-k dielectric layer124.

In some embodiments, the high-k dielectric layer124is configured to have a relatively large dielectric constant compared to silicon dioxide. The high-k dielectric layer124can include any suitable material that provide the relatively large dielectric constant, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), and barium strontium titanate (BaxSr1-xTiO3, BST), where x is between 0 and 1. The high-k dielectric layer124can be formed using any suitable deposition process, such as ALD, CVD, metalorganic CVD (MOCVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhance ALD (PEALD), thermal oxidation, combinations thereof, or other suitable technique.

The MG electrode structure130includes multiple metal layers, such as a metal barrier layer, a work function layer, a metal filling layer, and the like. In theFIG. 1example, the MG electrode structure130includes a metal barrier layer132, work function metal layers134-136and a metal filling layer138.

The metal barrier layer132is configured to conduct electricity and prevent inter-diffusion and reaction between metals, silicon or dielectric materials. The metal barrier layer132has a U-shape at the longitudinal cross-section (e.g., along line A-A′) of the transistor101, and forms a metal barrier recess that is surrounded by the metal barrier layer132. The metal barrier recess is then filled with other metal layers, such as the work function metal layers134-136, the metal filling layer138and the like. The outer surface of the metal barrier layer132is in contact with the spacer structures104. The candidates for the metal barrier material include refractory metals, such as titanium (Ti), tantalum (Ta) and their nitrides, such as TiN, TaN, W2N, TiSiN, TaSiN, and the like. The metal barrier layer132can be formed by suitable deposition process, such as PVD, CVD, ALD, metal-organic chemical vapor deposition (MOCVD) and the like.

The work function metal layers134-136are configured to adjust the work function of the MG electrode structure130and thus adjust the threshold voltage of the transistor101. The work function metal layers134-136can include one or multiple layers. In theFIG. 1example, the work function layers134-136include a first work function metal layer134and a second work function metal layer136. The first work function metal layer134is formed on the metal barrier layer132and the second work function metal layer136is formed on the first work function metal layer134. The first and second work function metal layers134and136have a U-shape at the longitudinal cross-section (e.g., along line A-A′ or along the channel length) of the transistor101. The outer surface of the first work function metal layer134is in contact with the metal barrier layer132, and the outer surface of the second work function metal layer136is in contact with the first work function layer134.

In some embodiments, the first work function metal layer134includes a mid-gap work function metal with a work function in a middle of band-gap between a conduction band and a valence band of a semiconductor material, such as silicon. The first work function metal layer134can be a metal layer, a metal alloy layer, multiple metal layers, and/or metal compound layers. In an example, the first work function metal layer134includes a metal, such as titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), or lanthanum oxide (La2O3).

In some embodiments, the second work function metal layer136includes a mid-gap work function metal with a work function in the middle of band-gap between conduction band and a valence band of a semiconductor material, such as silicon. The second work function metal layer136can be a metal layer, multiple metal layers, a metal alloy layer and/or metal compound layers. In an example, the second work function metal layer136includes a metal, such as titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), or lanthanum oxide (La2O3).

It is noted that the first work function metal layer134and the second work function metal layer136can be fabricated by the same material or different materials. Further, the first work function metal layer134and the second work function metal layer136can have the same thickness or different thicknesses.

In some examples, a threshold voltage of a transistor is a function of a thickness of the work function metal layers134-136. In an embodiment, the semiconductor device100is manufactured to have multiple transistors with different threshold voltages. In an example, a first transistor has the first work function metal layer134but not the second work function metal layer136, a second transistor has the second work function metal layer136but not the first work function metal layer134, and a third transistor has both the first work function metal layer134and the second work function metal layer136.

It is noted that, other suitable techniques, such as lattice matching, Fermi level pining mechanism, and the like can be suitably applied to adjust the effective work function of MG electrodes and thus adjust the threshold voltages of transistors.

The metal filling layer138is formed on the work function metal layers134-136. The metal filling layer138has a vertical bar shape at the longitudinal cross-section (e.g., along line A-A′) of the transistor101. The work function metal layers134-136surround side and bottom surfaces of the metal filling layer138. The metal filling layer138includes a metal having high conductivity, such as tungsten (W), copper (Cu) and the like.

The SAC hard mask structure140is formed on the MG electrode structure130. The SAC hard mask structure140has a bar shape at the longitudinal cross section (along line A-A′) of the transistor101. The bottom of the SAC hard mask structure140is in contact with the metal filing layer138and the upper portions of the U-shape of the metal barrier132and the work function metal layers134-136. The SAC hard mask structure140includes one or more insulator layers. In some examples, the SAC hard mask structure140includes silicon nitride, such as Si3N4, SiN, and other suitable N/Si ratios.

It is noted that the gate structure103has a T shape at the longitudinal cross section (along line A-A′) of the transistor101. For example, at the longitudinal cross section of the transistor101, the length of the SAC hard mask structure140is labeled as L1, and the length of the metal structure130is labeled as L2. The length of the metal structure L2is smaller than the length of the SAC hard mask structure L1on each side by D. In an example, the thickness of the high-k layer124is about D. In another example, a thickness sum of the high-k layer124and the interfacial layer122is about D. The T shape is formed due to an etching process (will be discussed in detail with reference toFIG. 3andFIG. 10) that removes the vertical portions124′ of the U-shape of the high-k layer124(or the high-k layer124and the interfacial layer122) in an example. It is noted that, in some examples, the etching process also etches the bottom of the U-shape of the high-k layer124, and causes undercuts at the bottom of the U-shape, as shown by125in theFIG. 1example. In some examples, the width ratio (L1/L2) of the SAC hard mask structure140to the metal structure130is in the range of 1.1 to 1.4 depending on the technology and gate length L2.

The spacer structures104are formed on the outer surfaces of dielectric structures120, the MG electrode structure130and the SAC hard mask structure140. The spacer structures120are located between the gate structure103and the SD structures105in a horizontal level at the longitudinal cross-section (along A-A′) along the channel length of the transistor101. The inner surfaces of the spacer structures104are in contact with the outer surfaces of the dielectric structure120, the MG electrode structure130and the SAC hard mask structure140. Outer ends of the spacer structures104are in contact with inner ends of the SD structures105in some examples.

It is noted that, due to the T shape of the gate structure103, the spacer structures104protrude under the SAC hard mask structure140, and fill the space of the vertical portions124′ that were previously occupied by the high-k layer124(or the high-k layer124and the interfacial layer122). The spacer structures104also fill the space of the undercuts at the bottom of the U-shape of the high-k layer124(and/or the interfacial layer122).

The spacer structures104can be formed of one or more layers. In some embodiments, the spacer structures104include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, and/or combinations thereof. The spacer structures104are formed by suitable deposition process, such as ALD, CVD, metalorganic CVD (MOCVD), PVD, plasma enhanced CVD (PECVD), plasma enhance ALD (PEALD), combinations thereof, or other suitable techniques.

In theFIG. 1example, each of the SD structures105includes a SD doped structure161, a self-aligned silicide (SALICIDE) structure162and a metal contact plug163.

The SD doped structures161have a conductive type associated with the channel type of the transistor101. In some embodiments, the SD doped structures161are formed by an epitaxial layer. The epitaxial layer forms raised source/drain regions. In some examples, epitaxial growths can impart suitable tensile strain or compressive strain to the channel region. In some embodiments, an N-type transistor includes epitaxially grown SD doped structures161, imparting a tensile strain to the channel region; a P-type transistor includes epitaxially grown SD doped structures161, imparting a compressive strain to a channel region. The SD doped structures161have suitable doping profile.

In theFIG. 1example, the SALICIDE structures162are formed on the SD doped structures161. The SALICIDE structures162can be any suitable silicide, such as titanium silicide, nickel silicide, cobalt silicide, and the like. In an example, the SALICIDE structures162are formed by a SALICIDE process. During the SALICIDE process, a layer of a silicide forming metal, such as titanium, nickel, cobalt and the like is deposited over the entire wafer by a suitable deposition process, such as RF sputtering, CVD, PVD, and the like. Then, the wafer is given a rapid thermal anneal (RTA), to cause the deposited metal to be converted to silicide wherever the deposited metal is in direct contact with silicon, such as on the top surface of the SD doped structures161. A selective etchant, such as hydrogen peroxide is then used to remove unreacted metal, i.e. metal that is in contact with the spacer structures104, the top surface of SAC hard mask structure140, and the like.

In some embodiments, the contact plugs163are formed in the openings above the SALICIDE structures162. In some examples, the contact plugs163include any suitable conductive material, such as aluminum, copper, titanium nitride, tungsten, titanium, tantalum, tantalum nitride, TaC, TaSiN, TaCN, TiAl, TiAlN, other suitable materials, and/or combinations thereof. In some embodiments, the conductive material is blanket-deposited (e.g., by CVD) into openings above the SALICIDE structures162. Subsequently, an etch-back (e.g., dry plasma) removes excess blanket layers. In some embodiments, a planarization, such as CMP, is used to remove the excess blanket layers, and form the contact plugs163above the SALICIDE structures162.

FIG. 3shows a flow chart outlining a process300for semiconductor fabrication according some embodiments of the disclosure. In an example, the process300is used to fabricate the semiconductor device100.

FIGS. 4-13show various longitudinal cross sectional views of the semiconductor device100at intermediate stages during the process300in accordance with some embodiments.

Referring toFIG. 3andFIG. 4, the process starts at S301, and proceeds to S310. At S310, mandrel structures460are formed on the semiconductor layer110. In some embodiments, the mandrel structures460have reversed gate patterns for metal gates, thus the recesses470that are surrounded by the mandrel structures460have the patterns for metal gate.

In some examples, the mandrel structures460are formed in a process that includes a deposition process, a photolithography process and an etching process. The deposition process forms one or more layers of material or composition over the semiconductor layer110. In an example, the deposition process deposits a first mandrel layer461and a second mandrel layer462. The first mandrel layer461can be for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to suitable techniques. The second mandrel layer462can be for example, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, metals and the like. In one embodiment, amorphous silicon is deposited and recrystallized to create polysilicon. The first mandrel layer461and the second mandrel layer462can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other suitable techniques.

In some embodiments, the photolithography process includes resist coating, soft baking, exposing, post-exposure baking, developing, and hard baking. In an embodiment, the reversed gate patterns are formed in developed photoresist, and then transferred into the first mandrel layer461and the second mandrel layer462by the etching process to form the mandrel structures. In another embodiment, the reversed gate patterns are formed in developed photoresist, and transferred into a hard mask by the etching process. Further, the hard mask is used to transfer the reversed gate patterns into the first mandrel layer461and the second mandrel layer462by the etching process to form the mandrel structures460.

Generally, the gate patterns have relatively small feature sizes, such as a minimum gate length as shown by464inFIG. 4. The reverse gate patterns are of relatively large feature sizes as shown by466inFIG. 4. Thus, the mandrel structures460have relatively large feature sizes compared to the recesses470. In a related gate-last example, mandrel structures are used to form dummy gates of the gate patterns. Further, the related gate-last example includes more planarization steps (e.g., three chemical mechanical planarization steps) that can cause gate high loss than in the present disclosure (e.g., two chemical mechanical planarization steps). Thus, the mandrel structures460can be fabricated with smaller height than in the related gate-last example. Then, the mandrel structures460have relatively large aspect ratio (width/height) compared to the mandrel structures of the dummy gates in the related gate-last example. Thus, mandrel bending and collapse issues are of less concern in the present disclosure compared to the related gate-last example.

It is noted that, in some embodiments, suitable clean process is performed, thus the semiconductor layer110is exposed at the bottom471of the recesses between the mandrel structures460.

Referring toFIG. 3andFIG. 5-6, at S320, dielectric structures and metal structures are formed. Specifically, inFIG. 5, dielectric layers520and metal layers530are formed on the surface of the semiconductor device100including the surface465of the mandrel structures460, sidewalls467of the mandrel structures460and the bottom471of the recesses between the mandrel structures460.

The dielectric layers520include a high-k dielectric layer524. The high-k dielectric layer524is deposited on the surface465of the mandrel structures460, sidewalls467of the mandrel structures460and the bottom471of the recesses between the mandrel structures460. Thus, the high-k dielectric layer524has a U-shape in the recess between the mandrel structures460, and the space in the U-shape is referred to as a dielectric recess. The U shape of the high-k dielectric layer524includes a bottom portion524and vertical portions524′ that contact the sidewalls467of the mandrel structures460.

In some embodiments, the dielectric layers520include an interfacial layer522. In an example, the interfacial layer522is thermally oxidized and grown dielectric (e.g., silicon dioxide), and is formed on the exposed surface of the semiconductor layer110, such as the bottom471of the recesses between the mandrel structures460as shown inFIG. 5. In another embodiment, the interfacial layer522is formed by deposition, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and the like. The interfacial layer522inFIG. 5is drawn according the example in which the interfacial layer522is thermally oxidized. The example of deposited interfacial layer522is not shown inFIG. 5. When the interfacial layer522is deposited before the high-k dielectric layer524, and the deposited interfacial layer522has a U-shape in the recess between the mandrel structures460.

In some embodiments, the high-k dielectric layer524is configured to have a relatively large dielectric constant compared to silicon dioxide. The high-k dielectric layer524can include any suitable material that provide the relatively large dielectric constant, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), and barium strontium titanate (BaxSr1-xTiO3, BST), where x is between 0 and 1. The high-k dielectric layer524can be formed using any suitable deposition process, such as ALD, CVD, metalorganic CVD (MOCVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhance ALD (PEALD), thermal oxidation, combinations thereof, or other suitable techniques. In some examples, the thickness of the high-k dielectric layer524has a thickness of about 1-3 nm for 3D-FinFET device, and about 1-5 nm for planar bulk devices.

The metal layers530includes multiple metal layers, such as a metal barrier layer532, work function metal layers534-536and a metal filling layer538.

The metal barrier layer532is configured to conduct electricity and prevent inter-diffusion and reaction between metals, silicon or dielectric materials. The metal barrier layer532is deposited above the dielectric layers520. The metal barrier layer532has a U-shape in the dielectric recess, and the space in the U-shape is referred to as a metal barrier recess. The outer surface of the U shape metal barrier layer532in contact with the vertical portions524′ of the dielectric layers520. The candidates for the metal barrier material include refractory metals, such as titanium (Ti), tantalum (Ta) and their nitrides, such as TiN, TaN, W2N, TisiN, TaSiN, and the like. The metal barrier layer532can be formed by suitable deposition process, such as PVD, CVD, ALD, metal-organic chemical vapor deposition (MOCVD) and the like.

The work function metal layers534-536can include one or multiple layers. In theFIG. 5example, the work function metal layers534-536include a first work function metal layer534and a second work function metal layer536. The first work function metal layer534is formed on the metal barrier layer532and the second work function metal layer536is formed on the first work function metal layer534. The first and second work function metal layers534and536have a U-shape in the metal barrier recess. The outer surface of the U-shape first work function metal layer534is in contact with the metal barrier layer532, and the outer surface of the U-shape second work function metal layer536is in contact with the first work function layer534.

In some examples, the first work function metal layer534includes a metal, such as titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), or lanthanum oxide (La2O3); and the second work function metal layer536includes a metal, such as titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), or lanthanum oxide (La2O3). In an embodiment, the second work function metal layer536has different thickness from the first work function metal layer534. The first work function metal layer534and the second work function metal layer536can of the same material or different materials and can of the same thickness or different thicknesses. The work function metal layers534-536can be respectively deposited using suitable deposition process, such as sputtering, ALD, PVD, CVD, metal-organic chemical vapor deposition (MOCVD) and the like.

It is noted that, while the transistor101to be fabricated has both the first work function metal layer534and the second work function metal layer536as shown inFIG. 5, other transistors on the semiconductor device100can be fabricated with one of the first work function metal layer534and the second work function metal layer536by suitable patterning technology.

Further, the metal filling layer538is deposited above the work function metal layers534-536to overfill recesses between the mandrel structures460. The metal filling layer538includes a metal having high conductivity, such as tungsten (W), copper (Cu) and the like. In some embodiments, a metal material, such as Al, W, WN, TaN, or Ru is sputtered and deposited to form the metal filing layer538. In some embodiments, the metal filling layer538includes a composite film stack structure such as TaN, TiN, W, WN, and WCN, or any combination thereof, and can be deposited using suitable deposition process, such as sputtering, ALD, PVD, CVD, metal-organic chemical vapor deposition (MOCVD) and the like.

FIG. 6shows a cross sectional view of the semiconductor device100after a planarization process. In an example, a chemical mechanical planarization (CMP) operation (referred to as first CMP step) is performed on the semiconductor device100after the deposition of the metal filing layer538. The CMP operation removes the excessive materials above the mandrel structures460, such as the excessive metal filling layer538, the excessive work function metal layer534-536, the excessive metal barrier layer532, and the excessive dielectric layer520. It is noted that a top surface of the mandrel structures460is also removed. It is also noted that portions of the dielectric layers520and the metal layers530remain in the recesses between the mandrel structures460. The portion of the dielectric layers520remaining in the recesses between the mandrel structures460has the U shape that forms the dielectric recess. The portion of the metal barrier layer532remaining in the recess between the mandrel structures460has the U shape that forms metal barrier recess. The work function metals534-536remaining in the recesses between the mandrel structures460have the U shape and the portion of the metal filling layer538remaining in the recess between the mandrel structures460has the bar shape.

FIG. 7shows a cross sectional view of the semiconductor device100after an etching back process. By the etching back process, an upper part of the metal gate (e.g., including the dielectric layers520and the metal layers530that remain in the recesses between the mandrel structures460) is etched back to define a gate trench770between the mandrel structures460. In some embodiments, the etching back process of the metal gate is a wet etching process. In some embodiments, an etchant used in the wet etching process is phosphoric acid. It is noted that after the etching back process, the MG electrode structure130has been formed.

FIG. 8shows a cross sectional view of the semiconductor device100after a deposition of an inter-layer dielectric (ILD) layer840. The ILD layer840is used to form the SAC hard mask structure140. In some embodiments, the ILD layer840includes silicon nitride, such as Si3N4, SiN, and other suitable N/Si ratios. The ILD layer840can be deposited by any suitable deposition process, such as CVD, PECVD, high density plasma CVD (HDPCVD), and the like.

FIG. 9shows a cross sectional view of the semiconductor device100after a planarization process. In an example, CMP operation (referred to as second CMP step) is performed on the semiconductor device100after the deposition of the ILD layer840. The CMP operation removes the excessive ILD layer840above the mandrel structures460. It is noted that a top surface of the mandrel structures460is also removed. It is also noted that after CMP operation, the SAC hard mask140has been formed.

FIG. 10shows a cross sectional view of the semiconductor device100after an etching process that removes the mandrel structures460. The etching process also removes the vertical portions524′ of the high-k dielectric layer524, and undercuts the interfacial layer122and the high-k dielectric layer124to from the dielectric structure120. In some embodiments, the etching process is an anisotropic dry etching process. For example, the etching process uses reaction gas(es) that selectively etches the mandrel structures460, the high-k dielectric layer, the interfacial layer without etching the SAC hard mask structure140and the MG electrode structure130. In some embodiments, the etching process could be a wet etching process or a combination of dry to remove mandrel while wet removing high-k and/or interfacial layer without etching the SAC hard mask structure140and the MG electrode structure130.

In an wet etch example, the etchants include one or more of hydrofluoric acid (HF), buffered HF (bHF), hydrogen peroxide (H2O2), tetramethylammonium hydroxide (TMAH), dilute hydrofluoric acid and citric acid, etc. In a dry etch example, the etching gas includes nitrogen, oxygen and fluorine gas, etc. The processing duration really depends on the Mandrel thickness being used and generally the etching process is designed to have ˜50-100% over-etching timing under reasonable etch selectivity.

FIG. 11shows a cross sectional view of the semiconductor device100after a deposition of a spacer layer1104. The spacer layer1104covers the surfaces of the gate structure103, such as the top surface1141and sidewalls1142of the SAC hard mask structure140, the outer surface1131of vertical portions of the metal barrier132, the undercut portions1121of the dielectric structure120, and the exposed surface1111of the semiconductor layer110. The spacer layer1104fills the space under the SAC hard mask structure130, the space was previously occupied by the vertical portion524′ of the high-k dielectric layer524.

The spacer layer1104can include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, and/or combinations thereof. The spacer layer1104is deposited by suitable deposition process, such as low pressure chemical vapor deposition (LPCVD), ALD, CVD, metalorganic CVD (MOCVD), PVD, plasma enhanced CVD (PECVD), plasma enhance ALD (PEALD), combinations thereof, or other suitable techniques.

FIG. 12shows a cross sectional view of the semiconductor device100after an etching process. In an example, the etching process is an anisotropic etching process that removes the spacer layer1104with a vertical etching speed much faster than a lateral etching speed. Thus, the spacer layer1104on the surface1111of the semiconductor layer110, and the spacer layer1104on the top surface1141of the SAC hard mask structure140are removed. The spacer layer1104at the sidewalls1142of the SAC hard mask structure140, the outer surface1131of vertical portions of the metal barrier132, and the undercut portions1121of the dielectric structure120remains and forms the spacer structures104.

FIG. 13shows a cross sectional view of the semiconductor device100after the SD doped structures161are formed. In an example, an etching process is performed to etch the semiconductor layer110to form source/drain recesses. In some embodiments, the spacer structures104and the gate structures103can be used as etching mask, thus the recesses are formed in the source/drain regions. Then, an epitaxial process is performed to grow epitaxial layer at the source/drain recesses to form the SD doped structures161. The SD doped structures161are suitably doped during the epitaxial process. In some examples, suitable strain is imparted in the channel region during the epitaxial process.

Referring toFIG. 3andFIG. 14, at S370, the SALICIDE structures and the contact plugs are formed.

FIG. 14shows a cross sectional view of the semiconductor device100after the SD structures105are formed, which is the same as the semiconductor device100shown inFIG. 1.

In an example, during a SALICIDE process, a layer of a silicide forming metal, such as titanium, nickel, cobalt and the like is deposited over the entire wafer by a suitable deposition process, such as RF sputtering, CVD, PVD, and the like. Then, the wafer is given a rapid thermal anneal (RTA), to cause the deposited metal to be converted to silicide wherever the deposited metal is in direct contact with silicon, such as on the top surface of the SD doped structures161to form the SALICIDE structure162. A selective etchant such as hydrogen peroxide is then used to remove unreacted metal, i.e. metal that is in contact with the spacer structures104, the top surface of SAC hard mask structure140, and the like.

In some embodiments, the contact plugs163are formed in the openings above the SALICIDE structures162. In some examples, the contact plugs163include any suitable conductive material, such as aluminum, copper, titanium nitride, tungsten, titanium, tantalum, tantalum nitride, TaC, TaSiN, TaCN, TiAl, TiAlN, other suitable materials, and/or combinations thereof. In some embodiments, the conductive material is blanket-deposited (e.g., by CVD) into openings above the SALICIDE structures162. Subsequently, an etching back process (e.g., dry plasma) removes some excess blanket layers. In some embodiments, a planarization, such as CMP, is used to remove the excess blanket layers.

Referring toFIG. 3, at S380, further processes are subsequently performed on the semiconductor device100, such as gate-cut, forming back-end-of-line structures, and the like. Referring toFIG. 3, the process300then proceeds to S399and terminates.

It is noted that during the process300, two CMP process steps (first CMP step and second CMP step) can cause gate height loss. In a related gate-last process, mandrel structures are used to form dummy gate. The related gate-last process includes three CMP process steps that can cause gate height loss. The mandrel structures in the present disclosure can be fabricated initially with a smaller height than in the related gate-last process. Further, the mandrel structures in the present disclosure are of the reversed gate patterns, and thus have relatively large width than the related gate-first process. Thus, the mandrel structures in the present disclosure have relatively large aspect ratio compared to the related gate-last example, and mandrel structure bending and collapse issues are of less concern in the present disclosure.

It is also noted that the gate-first process in the present disclosure uses metal filling techniques to pattern gate and thus can achieve straighter gate profile, dual metal patterning, no metal etching and the like. In addition, in some embodiments, the gate-first process allows a self-aligned formation of source/drain structures. It is also noted that the gate-first process is generally compatible with regular logic CMOS process, and can be more easily integrated into a manufacture facility that uses regular logic CMOS process.

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a gate structure, a spacer structure and a source/drain structure that are formed on a surface of the semiconductor layer. The gate structure includes a dielectric structure, a metal structure and an insulator structure. The dielectric structure is formed on the surface of the semiconductor layer. A bottom of the metal structure contacts a top of the dielectric structure. The bottom of the insulator structure contacts a top of the metal structure and the insulator structure protrudes over the top of the metal structure. The spacer structure is configured to extend underneath the bottom of the insulator structure and contact a sidewall of the metal structure. The spacer structure is configured to space between the gate structure and the source/drain structure. The source/drain structure includes a source/drain doped structure in the semiconductor layer, a silicide structure on a surface of the source/drain doped structure and a metal contact plug formed on the silicide structure.

Aspects of the disclosure also provide a method for semiconductor manufacturing. The method includes forming mandrels on a semiconductor layer with a recess that is surrounded by the mandrels and forming, in the recess, a gate structure. The gate structure includes a dielectric structure on a surface of the semiconductor layer, a metal structure on the dielectric structure, and an insulator structure on the metal structure. Further, the method includes removing the mandrels, forming a spacer structure that spaces between the gate structure and a source/drain structure, and forming the source/drain structure adjacent to the spacer structure.

Aspects of the disclosure provide a semiconductor device having a semiconductor fin. The semiconductor device includes a gate structure, and a spacer structure. The gate structure is formed at a region of the semiconductor fin. The gate structure includes a dielectric structure that is formed on sidewalls and a top surface of the semiconductor fin, a metal structure that covers the dielectric structure on the sidewalls and the top surface of the semiconductor fin and an insulator structure that covers the metal structure, and extends beyond the metal structure. The spacer structure is configured to extend underneath the insulator structure and contact a sidewall of the metal structure.