Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips

Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermitically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.

TECHNICAL FIELD

Embodiments of the present invention are generally in the field of microelectronic packaging, and more specifically relate to package level integration of sensors with integrated circuits (ICs).

BACKGROUND

Many techniques are employed to integrate sensors, such as accelerometers, gyros, and the like, with IC chips, such as those employed to condition and/or process the signals generated by the sensors. While monolithic integration of sensors and IC has been done in certain applications, monolithic integration is an expensive option typically requiring a sensor to be fabricated on top of an already complicated IC stack. As the complexity of ICs and sensors continues to increase, monolithic solutions become less attractive because of cost and the intimate association of the IC with the sensor limits a product portfolio's flexibility/diversity.

Board-level integration is another technique in which packaged sensor chips and packaged IC chips are placed onto a printed circuit board (PCB). At this level of integration, there is little difference between a sensor chip and an IC chip, so assembly techniques are advantageously straight forward, however a major disadvantage of board-level integration is the significant increase in size incurred through the many packaged devices. Each package typically includes an organic package substrate that has been built up to millimeters in thickness and an encapsulant increases chip lateral chip dimensions as well. Pick and place tool alignment limitations further limit the packing density of devices during PCB assembly.

Package-level integration is a third technique which falls somewhere between the monolithic and board-level integration techniques. Package-level integration generally entails bonding a plurality of chips onto a single organic package substrate.FIG. 1is a cross-sectional illustration of an integrated package100including sensor chip108and an IC109affixed to an organic package substrate120having a core125with build-up layers130,131in which interconnect traces135are embedded. For package-level integration, differences between sensor chips and IC chips become apparent. For example, while the IC109is often flip-chip bonded to the organic package substrate120, the sensor chip108typically cannot be flip-chip bonded because the sensor chip108, as received from a sensor supplier, has a ceramic cap110providing protection and hermetic sealing the sensor105within a cavity207. As such, to provide electrical connections116between the sensor105and the organic package substrate120, a through silicon via (TSV)115is formed through the silicon substrate101. TSVs however, are difficult to form and therefore expensive. Another problem faced by package-level integration is that the thickness of the organic package substrate120is considerable so that with chips108,109affixed to one side of the organic package substrate120, the thickness T1is on the order of 500 μm, or more. If additional devices are affixed to a second side of the organic package substrate120, the thickness increases even more. As such, even where the integrated package100is bonded to a PCB (e.g., with solder bump140), the integrated package100requires considerably more physical space than if monolithically integrated. Not only does this greater physical size limit the form factor of the end-user device, performance of the sensor may be reduced relative to a monolithic implementation because of the greater interconnect trace lengths between the sensor105and the IC chip109.

As such, techniques for integrating sensors and IC chips and there resulting structures which overcome the aforementioned limitations of the conventional techniques are advantageous.

DETAILED DESCRIPTION

The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer with respect to other layers. As such, for example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer.

Embodiments of the present invention employ an interposer to hermetically seal a sensor within a cavity and to provide a point of physical and electrical coupling of a sensor chip and an IC chip. While the following description makes many technical advantages apparent to the skilled reader, an advantage of the interposer of initial note is that multiple sensor chips may be mounted to the same interposer so that a hermetic seal is provided for all sensor chips, regardless of their function or source of supply. Another notable advantage of the interposer is that an IC chip may be mounted on a side opposite that to which a sensor chip is mount with a though via electrically coupling the two for an interconnect length that is much closer to that of monolithic integration. Another advantage is a low material cost for the interposer and low cost to form the through vias, relative to a silicon substrate and TSV. While these advantages all contribute to reduced physical size, embodiments where the interposer is mounted directly to a PCB enjoy a further reduction in physical dimension by eliminating any organic packaging substrate. Another notable advantage is that lateral interconnect traces may be formed on the interposer at low cost to provide I/O to the various chips affixed to the interposer and between the interposer and the PCB.

FIG. 2is a cross-sectional illustration of an exemplary system200integrating first and second IC chips205A,205B with first, second, and third sensor chips208A,208B,208C on an interposer201, in accordance with an embodiment of the present invention. Generally, the sensor and IC chips are affixed to both sides of the interposer201. In the illustrative embodiment, the first sensor chip208A, disposed on a first substrate, is affixed to a first side202of the interposer201and the IC chip205A, disposed on a second substrate, is affixed to a second side203of the interposer201by flip chip (C4) connections222A. As such, expensive TSVs are not need through a substrate of the IC chip205A or a substrate of the first sensor chip208A.

While the IC chips affixed to the interposer201may be any analog, digital, or mixed signal circuitry known in the art for control of the sensor chips208A,208B, and/or208C or for processing of their signals, in the exemplary embodiment the first IC chip205A has a function correspondence with the sensor chip disposed most opposite to the IC chip. For example, first IC chip205A has a functional correspondence with the first sensor chip208A, while the second IC chip205B has a functional correspondence with the second and third sensor chips208B,208C. In one such embodiment, the first IC chip205A includes an amplifier circuit to amplify a signal received from the first sensor chip208A (i.e., as generated by sensor105). As the sensor105may provide a signal with relatively low signal-to-noise ratio (SNR), it is advantageous to conduct the sensor I/O to the first IC chip205A by the through via250A for minimal signal loss and cross-talk. In the illustrated embodiment, the first sensor chip208A and first IC chip205A are approximately aligned across a thickness of the interposer permitting electrical coupling of the two with through via interconnect250A that is of minimum length as defined essentially by the interposer thickness T2. In a further embodiment, the interposer thickness T2is less than a lateral pitch between devices placed on a same side of the interposer (e.g., side202), so that the though via250A minimizes interconnect trace length between an amplifier circuit and the sensor105. For example, depending on the material chosen for the interposer201and whether an additional package substrate is to be utilized, the interposer thickness T2may range from between about 100 μm and about 500 μm while the sensor chip lateral side dimension S1may range for 1 mm-2 mm, or more, with the lateral gap between adjacent devices G1anywhere from 200 μm to 1 mm. In another embodiment illustrated byFIG. 2, the second IC chip205A is coupled to both the second and third sensor chips208B and208C to send input signals to one of the second and third sensor chips208B,208C based on a output signal received from the other of the second and third sensor chips208B,208C. With through vias250B routing to both the second and third sensor chips208B,208C, the three chips205B,208B and208C may be closely placed and intimately associated at a level rivaling monolithic integration without the concomitant costs and loss of device-level flexibility.

As further shown inFIG. 2, the first sensor chip208A includes a sensor chip substrate101A and is affixed to the interposer201with a hermetic seal210A between the sensor chip substrate101A and the interposer201enclosing the sensor105within the cavity207. As such, the sensor chip208A is essentially flip-chip bonded to bond pads on the interposer201with the interposer201forming a hermetic cap material covering the sensor105. Depending on the sensor chip lateral side dimension S1and the tolerance of the sensor105to contamination, electrical connections between the sensor and the through vias are within the hermetic cavity (e.g., connections212A and through vias250A) or electrical connections between the sensor and the through vias are disposed outside of the hermetic seal (e.g., connections212C and though vias250B) to maintain the cavity207solder-free. With the electrical connections212A being on a same side of the sensor chip208A as the sensor105, there is no need to form a TSV through the sensor substrate101A, which is typically of silicon having a 50-500 μm thickness.

The second and third sensor chips208B,208C disposed on second and third substrates101B,101C, are also affixed to the first side202of the interposer201. Although second and third sensor chips208B,208C may alternatively be affixed to the second side203of the interposer201, as describe elsewhere herein, sealing a plurality of sensor chips may be relatively easier where all the sensor chips are on a same side of the interposer. While each of the sensor chips208A,208B,208C may be identical, in advantageous embodiments, the sensor chips are at least of a different manufacture and preferably also of different function. In an embodiment, at least one of the sensor chips208A,208B,208C requires a cavity207to function. In one such embodiment, at least one of the sensor chips208A,208B,208C includes micro-electro-mechanical system (MEMs) having a released structure that is anchored to the sensor chip substrate101in a manner which enables the released restructure to be physically displaced within the cavity207relative to the sensor chip substrate101. For example, the first sensor chip208A may include any MEMs accelerometer known in the art and as embodiments of the present invention are not limited in this respect, no further description is provided herein. In a further embodiment, the second sensor chip208B entails a second MEMs device with a function other than an accelerometer. In the exemplary embodiment, the second sensor chip208B, including any MEMs gyroscope known in the art, is joined to the interposer201by the hermetic seal210B, which may be of the same or different structure than the hermetic seal210A. The third sensor chip208C may be any other MEMs-based or non-MEMs sensor known in the art. In the exemplary embodiment, the third sensor chip208C, including any MEMs resonate known in the art, is joined to the interposer201by the hermetic seal210C, which may be of the same or different structure than the hermetic seals210A and210B.

In an embodiment, the interposer201includes lateral electrical interconnect traces251to electrically couple together one or more of the first, second, and third sensor chips208A,208B,208C to each other and/or to an IC chip affixed to the first interposer side202, and/or to electrically couple the first IC chip205A to a second IC chip205B affixed to the second interposer side203. The lateral electric interconnect traces251may further rout electrical traces from all devices affixed to the interposer201to electrical connections232which in the exemplary embodiment are directly affixed to a PCB260to form the integrated system200. In an alternative embodiment, the electrical connections232are affixed to an organic package substrate (not depicted) which is then affixed to the PCB260. In either implementation, the lateral electrical interconnect traces251may be of copper or aluminum, etc. if conventional wafer-level thin film fabrication techniques are used, or advantageously of an anisotropic conductive adhesive (ACA) which is laminated or printed onto the interposer201if LCD fabrication techniques are used. ACA techniques include anisotropic conductive films (ACF), anisotropic conductive pastes (ACP), and the like. The lateral electrical interconnect traces251may be of any ACA material known in the art of liquid crystal displays (LCD) or thin film transistors (TFT). The lateral interconnect traces251are formed in dielectric layers240and241deposited on the interposer201. The dielectric layers240and241may be for example silicon dioxide, or preferably silicon nitride which forms a hermetic barrier at lower thicknesses than silicon dioxide.

In an embodiment, the interposer201is a glass of 100-500 μm in thickness. Generally, any glass known to be suitable for LCD applications may be utilized, with the exemplary interposer201being of boro-aluminasilicate glass. Such LCD glass embodiments have a coefficient of thermal expansion (CTE) well-matched to that of the sensor chips208A,208B,208C and IC chips205A,205B. LCD glass materials are also inexpensive relative to many other potential interposer materials, such as silicon. As described elsewhere herein, LCD glass is also amenable to the formation of the through vias250A,250B, allowing vertical electrical interconnects to be formed at a lower cost that TSV requiring ablation and/or deep silicon plasma etch processes. LCD glass is also a low contaminant material which provides a good hermetic seal for the sensor chips208A,208B, and208C.

With the general architecture and materials employed in embodiments of the present invention exemplified by the integrated system200.FIGS. 3A, 3B, 3C, and 3Dare cross-sectional illustrations further depicting electrical and hermetic bonding structures which may be employed in accordance embodiments of the present invention. As previously described, it is possible to mix sensor chips and IC chips on the same side of the interposer as it is possible to mix the assembly bonding sequence. However, in advantageous embodiments, sensor chips needing a hermetic cavity are disposed on one interposer surface (side) and the IC chips are disposed on the opposite interposer surface (side). Such embodiments enable the hermetic cavities to be bonded to a very clean surface (e.g., glass), for example first in a bonding sequence under clean conditions. In exemplary embodiments illustrated inFIGS. 3A, 3B, 3C, and 3D, the hermetic seals to the interposer are flux-less. In further embodiments where the sensor is highly sensitive to contaminants, the bonding material has a low vapor pressure at the bonding temperature.

In a first embodiment, illustrated inFIG. 3A, electrical connections are achieved with direct metal compression bonding between sensor pads327and interposer pads328, each of which may be of gold (Au) or copper (Cu) for example, to form a joint of essentially Au or Cu. One or more of the interposer pads328may be directly coupled to the through via250A. As further shown inFIG. 3A, the hermetic seal210A is achieved with a continuous ring of glass frit. Glass frit has the advantage of being bondable directly to the bulk surface (i.e., no pad) of the sensor chip and the interposer (having a glass or other dielectric surface). In the exemplary embodiment the sensor pads327are disposed on a pedestal318to standoff the sensor chip sufficiently to accommodate the hermetic seal210A. In alternate embodiments, a the pedestal318may be disposed on the interposer201to accommodate sensors chips from different sources and/or of structure. More generally, any of the hermetic seal210A, pads327,328may be disposed on a mechanical stand-off as needed.

In a second embodiment, illustrated inFIG. 3B, both electrical connections and a hermetic seal are provided by a metal-metal compression bond. For this embodiment, both a sensor metal ring pad337and an interposer metal ring pad338are joined to form a joint, of essentially Au or Cu for example, that continuously surrounds the sensor105and seals the cavity207. Like the individual electrical connections, the sensor metal ring pad337is disposed on a pedestal319, though interposer metal ring pad338may also be disposed on a standoff in combination with, or in place of pedestal319. Along with the compression bonded Au—Au or Cu—Cu hermetic seal, the electrical connections including the sensor pads327and interposer pads328are compression bonded Au—Au or Cu—Cu, as described for the embodiment inFIG. 3A.

In a third embodiment, illustrated inFIG. 3C, the electrical connections include a solder joint348coupling the sensor pad327to the interposer pad328, while the hermitic seal210A is of glass frit. In this embodiment, the solder is preferably deposited using conventional techniques (e.g., plated, microball, solder paste, reflow, etc.) on the interposer201with the sensor pads327finished with a metal coating that minimizes oxidation (so that flux may be avoided) and is compatible with the chosen solder. In particular embodiments, the sensor pads327include at least one of Au, Pt or Pd.

In a fourth embodiment, illustrated inFIG. 3D, both the electrical connections and the hermetic seal include solder joints348,358, respectively. Such solder embodiments advantageously relax flatness or leveling constraints relative to compression bonded embodiments. Like for the compression bonded embodiments, solder seal rings include both a sensor metal ring pad337and an interposer metal ring pad338. A solder joint358joining the sensor metal ring pad337and an interposer metal ring pad338is preferably of a same solder composition as the electrical solder joint348.

Embodiments employing solder joints coupling the sensor chip to the interposer may employ different types of solder.FIGS. 4A and 4Bare cross-sectional illustration of solder joints, in accordance with two such embodiments. In a first embodiment, illustrated inFIG. 4A, a solder joint358bonding a sensor chip to an interposer is of a fixed solder composition having a sufficiently high melting temperature that subsequent solder bonds between the interposer and an IC chip and/or PCB (e.g., electrical connections222A and232) made with a solder composition having a lower melting temperature are not detrimental to the solder joint358. For embodiments employing a plurality of sensor chips on a single interposer, the same solder composition may be utilized for all sensor chips. As illustrated byFIG. 4A, the sensor pad337and interposer pad338merely serve as mechanical substrates for the solder joint358with minimal solder-pad reactions so that the bulk composition of the solder joint358is the substantially the same as the composition of the metallic alloy constituents in the as-deposited solder. Exemplary, high temperature solder alloys which may be employed include, but are not limited to, cadmium-silver binary alloys (e.g., Cd95Ag5), zinc-tin binary alloys (e.g., Zn95Sn5), gold-silicon binary alloys (Au96.8Si3.2), gold-germanium binary alloys (e.g., Au87.5Ge12.5), and gold-indium binary alloys (e.g., Au82In18).12.

For such embodiments, in the integrated system200(FIG. 2), the hermetic seal210A and/or the electrical connections212A to the interposer201may be with first solder joints having the high melting temperature composition while the first IC chip205A is physically attached to the interposer201by electrical connections222A that include second solder joints of a lower melting temperature composition (e.g., a binary SnAg alloy).

In a second embodiment, illustrated inFIG. 4B, a solder joint358bonding a sensor chip to an interposer is of a reactive solder. The solder joint358has a composition with a low melting temperature, but reacts to form an intermetallic compound or solid solution having a sufficiently higher melting temperature that subsequent solder bonds between the interposer and an IC chip and/or PCB (e.g., electrical connections222A and232) are not detrimental to the solder joint358. As illustrated byFIG. 4B, the sensor pad337and interposer pad338react during bonding to form a solder joint358A having a composition that is includes constituents from both the pads337,338and the solder as-deposited. After higher temperature annealing, a full solder-pad reaction achieves the intermetallic or solid solution358B. Exemplary, low temperature solder alloys which may be employed to form such intermetallic or solid solutions include, but are not limited to, indium (In) and its alloys. For the exemplary In solder and Cu pads337,338, a solid solution of CuxIn1−x having a high melting temperature than In is formed. For the exemplary In solder and Au pads337,338, a solid solution of AuxIn1−x having a high melting temperature than In is formed.

For such embodiments, in the integrated system200(FIG. 2), the hermetic seal210A and/or the electrical connections212A to the interposer201may be with first solder joints having the reacted intermetallic composition while the first IC chip205A is physically attached to the interposer201by electrical connections222A that include second solder joints of a lower melting temperature composition (e.g., a binary SnAg alloy).

Depending on the embodiment, IC chips may be bonded to the interposer with or without underfill.FIG. 5Ais cross-sectional illustration of the first IC chip205A flip-chip bonded to an interposer201without underfill (e.g., voids between the electrical connections222A.FIG. 5Bis a cross-sectional illustration of the first IC chip205A flip-chip bonded to the interposer201with underfill255between the electrical connections222A. The underfill255may not be needed from a mechanical perspective for glass interposer embodiments because the CTE mismatch between the interposer and IC chip (substantially silicon) is small. To achieve this simplification in the architecture however, the IC chip should be bonded with a solder having composition with a high melting temperature than for the solder composition employed for subsequent bonding of the interposer (e.g. to a PCB) so that the electrical connections222A are not disrupted during the subsequent solder reflows. For embodiments where a higher temperature solder composition is utilized for attachment of the sensor chip therefore, three solder compositions having three melting temperatures are be utilized. For example, in the embodiment illustrated inFIG. 2, electrical connections212A,212B212C and/or hermetic seals210A,210B,210C include first solder joint of a first composition having a highest melting temperature, electrical connections222A include a second solder of a second composition having an intermediate melting temperature, and electrical connections232include a third solder joint of a third composition having a melting temperature lower than a that of both a first and second solder joints.

FIG. 6is a functional block diagram of a mobile computing platform700which employs the integrated system200, in accordance with an embodiment of the present invention. The mobile computing platform700may be any portable device configured for each of electronic data display, electronic data processing, and wireless electronic data transmission. For example, mobile computing platform700may be any of a tablet, a smart phone, laptop computer, etc. and includes a display screen705which in the exemplary embodiment is a touchscreen (capacitive, inductive, resistive, etc.), the board-level integrated device710, and a battery713. As illustrated, the greater the level of integration of the board-level integrated device710, the greater the portion of the mobile computing device700that may be occupied by the battery713or a memory (not depicted), such as a solid state drive, for greatest platform functionality. As such, the ability to integrate sensor chips with IC chips on an interposer disposed directly on a PCB, as described herein, enables further performance and form factor improvements of the mobile computing platform700.

The board-level integrated device710is further illustrated in the expanded view720. Depending on the embodiment, the board-level integrated device710includes the PCB260upon one or more of a power management integrated circuit (PMIC)715, RF integrated circuit (RFIC)725including an RF transmitter and/or receiver, a controller thereof711, and one or more central processor cores730,731for processing input received integrated with the integrated system200. Functionally, the PMIC715performs battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to the battery713and has an output provide a current supply to all the other functional modules in the board-level integrated device710, including, for example, the first IC205A and/or the sensor208A in the integrated system200. As further illustrated, in the exemplary embodiment the RFIC725has an output coupled to an antenna to provide a carrier frequency of around 2 GHz (e.g., a 1.9 GHz in an RFIC725designed for 3G or GSM cellular communication) and may further have an input coupled to a communication modules on the board-level integrated device710, such as an RF analog and digital baseband module (not depicted).

FIGS. 7 and 8A-8Care flow diagrams illustrating methods of integrating sensor chips and IC chips on an interposer, in accordance with embodiments of the present invention. The method800inFIG. 7begins with operation810where each of an interposer, one or more sensor chips and one or more IC chips are received. In one embodiment, the sensor chips are received from a source as one of many unencapsulated sensors still in wafer form with sensor chip singulation to be performed as part of operation810. At operation820, all sensor chips to be integrated onto the interposer are affixed to one or both sides of the interposer. In the exemplary embodiment, all sensor chips to be integrated onto the interposer are affixed to bond pads on the interpose that are disposed on a same, first side of the interposer. At operation850, all the IC chips to be integrated onto the interposer are affixed to the interposer, for example on the second side of the interposer, by bonding them to at least one bond pad that is electrically coupled to a through via in the interposer which is further coupled to at least one bond pad on the first side of the interposer that is coupled to a sensor chip. At operation895, the interposer is attached, for example by solder bumps, to an organic package substrate or directly to a PCB.

FIG. 8Afurther illustrates a method801for forming an interposer which may be employed in the method800, in accordance with an embodiment. Method801begins at operation805with receipt of a glass interposer substrate. At operation806columnar defects are induced within the glass at predetermined locations where through vias are to be provided. The columnar defects are in one embodiment formed through exposure to laser radiation of a desired energy for a desired time. The glass interposer is then submerged in a wet etchant solution which selectively etches the regions of the glass interposer having the columnar defects thereby opening through vias in the glass interposer. Conventional plating techniques are then used to form vertical electrical interconnects. At operation807lateral interconnect traces are formed by printing or laminating an anisotropic conductive adhesive (ACA). For example, an anisotropic conductive paste is printed on the glass interposer and cured or an anisotropic conductive film is laminated on the glass interposer. At operation808, dielectric layers are built up on one or both sides of the glass interposer by thin film deposition techniques (e.g., chemical vapor deposition) or by spin on coating techniques (e.g., spin on glass, etc.). Operations807and808are repeated until a predetermined number of lateral interconnect layers are formed. The method801then returns to operation810of method800.

FIG. 8Billustrates a method802further describing specific embodiments of the operations820and850in the method800. Method802begins at operation811with receipt of a plurality of sensor chips and an interposer, for example the glass interposer formed by method801. At operation821, pressure is applied to the plurality of sensor chips to hold each sensor chip that is to be integrated onto the interposer against a first side of the interposer. In the exemplary embodiment the pressure applied is light, merely to keep the sensor chips in physical contact with the interposer. At operation825heat is applied either locally to each sensor chip or globally across the entire interposer to cause solder bumps present between the each sensor chip and the interposer to join. In an alternative embodiment with direct pad-pad metal bonding, operations821and825are performed in the absence of solder and at higher pressure and/or temperatures. After permanently affixing the plurality of sensor chips to the interposer, the solder chip(s) are affixed to the second side of the interposer at operation851, for example with any flip-chip (C4) bonding technique known in the art. Method802then returns to operation895(FIG. 7).

FIG. 8Cillustrates a method803further describing specific embodiments of the operations821and851in the method802. Method803begins at operation822where bond pads of the interpose (e.g., on a first side) are joined to bond pads of each of the plurality of sensor chips with a first solder joint at a first solder temperature. At operation852, bond pads of the interposer (e.g., on a second side) are joined to bond pads of the IC chip(s) with a second solder joint at a second soldering temperature which does not cause the first solder joint to reflow. In a first embodiment where the first solder joint comprises a solder which forms an intermetallic with the bond pads, the first soldering temperature and the second soldering temperature are approximately the same. In a second embodiment, where the first solder joint comprises a solder which does not form an intermetallic with the bond pads, the first soldering temperature is higher than the second soldering temperature. Method803then returns to operation895where, if the IC chip is not underfilled, bond pads of the interposer (e.g., on the second side) are joined to bond pads on a package substrate or PCB with a third solder joint at a third soldering temperature that is lower than both the first and second soldering temperatures of operations822and852.

It is to be understood that the above description is illustrative, and not restrictive. For example, while flow diagrams in the figures show a particular order of operations performed by certain embodiments of the invention, it should be understood that such order may not be required (e.g., alternative embodiments may perform the operations in a different order, combine certain operations, overlap certain operations, etc.). Furthermore, many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Although the present invention has been described with reference to specific exemplary embodiments, it will be recognized that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.