DMA controller and DMA transfer method

A DMA channel data quantity setting section sets a data transfer quantity of each of a plurality of DMA channels in accordance with a data quantity or a ratio in advance. A channel select control circuit determines whether each DMA channel is active. A data transfer control circuit transfers the data of the DMA channel determined to be active by the channel select control circuit in accordance with the data transfer quantity of each DMA channel set by the DMA channel data quantity setting section. By doing so, a plurality of DMA requests are accepted per bus hold request, and the number of bus management right arbitration procedures and the latency between the channels are decreased.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.2002-252704, filed on Aug. 30, 2002, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1) Field of the Invention

The present invention relates to a direct memory access (DMA) controller that performs DMA transfer for a plurality of data transfer channels, and a DMA transfer method therefor.

2) Description of the Related Art

A system that employs a central processing unit (“CPU”) conventionally has a DMA transfer function. The DMA transfer function means performing data transfer without causing the CPU to intervene so as to transfer data between a plurality of peripherals and a memory at high rate. This DMA transfer function is controlled by a DMA controller, the basic operation of which will be explained below.

If a DMA request is issued from a peripheral allocated to each channel, to the DMA controller, the DMA controller issues a bus hold request to the CPU. If a plurality of DMA requests are issued from peripherals, the DMA controller prepares for data transfer for the highest priority channel in accordance with preset priorities.

If the CPU accepts the bus hold request from the DMA controller, the CPU hands over a bus management right to the DMA controller. The DMA controller starts the data transfer between the memory and the peripherals using the bus as a DMA transfer data path. The data transfer is performed while DMA requests are continuously issued. In a burst mode, the data transfer of a preset size can be performed.

However, the conventional technique is always required to take arbitration procedures for the bus management right between the DMA controller and the CPU as a preparation for starting the DMA transfer. As a result, if the DMA transfer is frequently performed, the arbitration procedures disadvantageously deteriorate data transfer efficiency.

Although it is possible to decrease DMA transfer frequency by using the burst mode, the burst mode increases a data length and bus occupation time per channel tends to increase, accordingly. This results in an increase in wait time until a DMA request is processed, disadvantageously causing latency to the data between the channels. Besides, a buffer necessary to hold data needs to be large in size.

SUMMARY OF THE INVENTION

The DMA controller according to one aspect of the present invention comprises a data quantity setting unit that sets a data transfer quantity of each of a plurality of DMA channels; a channel select control unit that determines whether each DMA channel is active; and a data transfer control unit that transfers data of each of the DMA channels determined to be active by the channel select control unit, in accordance with the data transfer quantity of each DMA channel set by the data quantity setting unit.

According to the above aspect, DMA requests from a plurality of peripherals existing on the same bus are simultaneously accepted when a right to use the bus is acquired once, it is determined whether each of the DMA channels is active, and DMA transfer is performed based on the preset data transfer quantity of each of the DMA channels. At this moment, the data transfer quantity of each DMA channel for a total quantity of the data to be transferred when the right to use the bus is acquired is transferred in accordance with a fixed data quantity or a channel specific ratio.

DETAILED DESCRIPTION

Exemplary embodiments of the DMA controller and the DMA transfer method according to the present invention will be explained hereinafter in detail with reference to the accompanying drawings. A channel band guarantee type DMA controller according to the present invention processes DMA requests from a plurality of peripherals that exist on the same bus when a right to use the bus is acquired once.

FIG. 1is a block diagram that shows the basic configuration of the DMA controller according to the present invention. Peripherals (peripheral-1to peripheral-n)2ato2nfor a plurality of DMA channels (hereinafter “channels”) Ch1to Chn, a CPU3, and a memory4are connected to the DMA controller (DMAC)1. The DMA transfer is performed between the peripherals2ato2nand the memory4through a bus (hereinafter “data/address bus”)5under the control of the DMA controller1.

The DMA controller1includes an interface (I/F) circuit10, a channel select control circuit11, a DMA channel data quantity setting section12, a burst length counter (hereinafter “1ChBurst counter”)13, a channel control circuit14, and a data transfer control circuit15. The I/F circuit10controls the data transfer for the data of the peripherals2ato2non the respective channels. The channel select control circuit11determines whether the DMA channels are active based on transfer requests DREQ output from the peripherals2ato2n, and selects the execution of the DMA transfer of the data of one active DMA channel. The DMA channel data quantity setting section12presets the data transfer quantity of each channel. The burst length counter13counts the burst length of each channel. The channel control circuit14counts the data and address of each channel. The data transfer control circuit15arbitrates a bus use right between the DMA controller1and the CPU3, and controls data transfer operations such as DMA read/write.FIG. 2is a block diagram that shows detailed configuration of the DMA controller1. This DMA controller is configured to set the data quantity of each DMA channel in accordance with the ratio of the data quantity of each channel to a total data quantity to be transferred by the DMA controller when one bus right is acquired.

The DMA controller1comprises the DMA channel data quantity setting section12. The DMA channel data quantity setting section12includes a channel ratio register20, a burst length arithmetic circuit (hereinafter “1ChBurst length arithmetic circuit”)21, a burst length holding circuit22, and a total burst length register23. The channel ratio register20sets the ratio of each data quantity to the total data quantity. The burst length arithmetic circuit21operates a data quantity from the ratio of the data quantity to the total data quantity. The burst length holding circuit22holds the data quantity of each channel thus operated. The total burst length register23sets the burst length of the total transfer quantity.

FIGS. 3A and 3Bare tables that show one example of the configuration of the channel ratio register20. The channel ratio register20sets the ratio of the data quantity of each DMA channel to the total data quantity. It is possible to set four ratios as shown inFIG. 3Busing two bits of RT1and RT0shown inFIG. 3Afor each channel Ch. For example, for a certain channel, if the bit RT1is set at “0” and the bit RT0is set at “1”, it is possible to set the ratio of the data quantity of the certain channel to the total data quantity at 25% of the total transfer rate. If the number of bits shown inFIG. 3Bincreases, it is possible to set ratios more minutely.

The configuration of the1ChBurst length arithmetic circuit21can be changed, depending on whether an empty area is used. That is, it is possible to determine whether to transfer the data of active DMA channels during the transfer time (empty time) of an inactive DMA channel.

FIG. 4is a block diagram that shows one example of the setting of the1ChBurst length arithmetic circuit21. With this configuration, no empty area is used. Mask circuits Ch1(31a) to Chn (31n) are provided to correspond to the respective channels. Active signals (ACT_Ch1to ACT_Chn) from the channel select control circuit11and channel ratio signals (Ch1_Ratio to Chn_Ratio) from the channel ratio register20are input into the mask circuits31ato31nfor the respective channels.

The mask circuits for channels1(Ch1) to n (Chn)31ato31noperate the ratios of the data quantities of the respective channels based on the ratios of the corresponding channel ratio signals when the corresponding active signals are active, and output the operation results to corresponding multipliers32ato32n. A total data quantity (TotalBurst length) is input into the multipliers32ato32nfrom the total burst length register23. The multipliers32ato32noperate the data quantities of the corresponding channels (Ch1Burst length to ChnBurst length) and output the operation results, respectively. If the corresponding active signals are inactive, the mask circuits31ato31noutput 0(%) as the ratios of the data quantities of the respective channels.

A fixed data quantity is allocated to each channel, irrespective of the state of the channel (active or inactive). Therefore, during empty time, the data of other active DMA channels is not transferred and the bus use right is abandoned.

FIG. 5is a timing chart that explains a DMA transfer processing in the first embodiment. Setting conditions are as follows. The total burst length of the total burst length register23is 16-bytes, and the Ch1_Ratio, Ch2_Ratio, and Chn_Ratio of the channel ratio register20is 50%, 25%, and 25%, respectively.

Among the peripherals2ato2n, the peripherals2aand2bfirst output transfer requests DREQ_1and DREQ_2, respectively (at time T1). If a transfer request DREQ_n is delayed (output at time T2), the channel select control circuit11determines that only the channels Ch1and Ch2are active (outputs ACT_Ch1and ACT_Ch2) based on the rise of the initially output transfer requests DREQ_1and DREQ_2. The data transfer control circuit15outputs one bus hold request (HOLD) to the CPU3.

Thereafter, the1ChBurst length arithmetic circuit21operates the ratio of the data quantity of each channel, and DMA transfer is performed for the active channels based on the corresponding ratios. In the example ofFIG. 5, the channel select control circuit11determines that only the channels Ch1and Ch2are active, 50% of 16-bytes that is TotalBurst length, i.e., the data of 8-bytes of the channel Ch1is DMA-transferred, and 25% of 16-bytes that is TotalBurst length, i.e., the data of 4-bytes of the channel Ch2is DMA-transferred.

Consequently, the data of only the channels Ch1and Ch2for which DMA transfer requests are issued from the corresponding peripherals and which are determined active, is DMA-transferred by one bus use right. At this moment, since the empty capacity is not used, only the data of 12-bytes of the channels Ch1and Ch2among 16-bytes that is the total quantity of data to be used, is transferred. During transfer expected time (time T3) allocated to the channel Chn, the bus use right is abandoned.

FIG. 6is a block diagram that shows another example of the configuration of the1ChBurst length arithmetic circuit as a second embodiment of the present invention. An empty area is reset in accordance with the ratio of the data quantity of each DMA channel. The mask circuits31ato31nare provided for each of the channels1(Ch1) to n (Chn). The active signals (ACT_Ch1to ACT_Chn) from the channel select control circuit11and the channel ratio signals (Ch113Ratio to Chn_Ratio) from the channel ratio register20are input into the mask circuits31ato31nfor the respective channels.

The mask circuits31ato31noperate the ratios (%) of the data quantities of the respective channels based on the ratios of the corresponding channel ratio signals, and output the operation results to corresponding dividers34ato34nprovided in rear of the mask circuits31ato31n, respectively, and to an adder33. The adder33adds the ratios of the data quantities of all the active channels, and outputs the addition result to the dividers34ato34n. Therefore, the dividers34ato34ncan operate again the ratios (%) of the data quantities of the respective channels in accordance with the ratios of the corresponding channel ratio signals based on the ratios (%) of the data quantities of all the active channels.

Thereafter, the ratios (%) of the data quantities of the channels are output to the multipliers32ato32n, respectively. The total data quantity (Totalburst length) is input into the multipliers32ato32nfrom the total burst length register23. The multipliers32ato32noperate the data quantities of the corresponding channels (Ch1Burst length to ChnBurst length) and output the operation results, respectively.

If an empty area occurs, it is possible to allocate data quantities to all the active channels based on the corresponding channel ratios.

FIG. 7is a timing chart that explains a DMA transfer processing in the second embodiment. Setting conditions are as follows. The total burst length of the total burst length register23is 16-bytes, and the Ch1_Ratio, Ch2_Ratio, and Chn_Ratio of the channel ratio register20is 50%, 25%, and 25%, respectively.

Among the peripherals2ato2n, the peripherals2aand2bfirst output transfer requests DREQ_1and DREQ_2, respectively (at the time T1). If a transfer request DREQ_n is delayed (output at the time T2), the channel select control circuit11determines that only the channels Ch1and Ch2are active (outputs ACT_Ch1and ACT_Ch2) based on the rise of the initially output transfer requests DREQ_1and DREQ_2. The data transfer control circuit15outputs one bus hold request (HOLD) to the CPU3.

Thereafter, the1ChBurst length arithmetic circuit21operates the ratio of the data quantity of each channel, the total data quantity of the active channels is divided by the ratio of each channel and DMA transfer is performed based on the corresponding ratios. In the example ofFIG. 7, the channel select control circuit11determines only the channels Ch1and Ch2are active. At this moment, the ratios of the data quantities of the channels Ch1and Ch2are adjusted to be equal to 100%. The ratios of the channels Ch1and Ch2are Ch1:Ch2=50%:25%=2:1. Therefore, if the ratios are recalculated based on the total ratio (100%), the ratios of the data quantities of the channels Ch1and Ch2are Ch1=⅔=66.6% and Ch2=⅓=33.3%. As a result, 66.6% of 16-bytes that is TotalBurst length, i.e., the data of 10-bytes of the channel Ch1is DMA transferred, and 33.3% of 16-bytes that is TotalBurst length, i.e., the data of 6-bytes of the channel Ch2is DMA transferred (at time T3).

Consequently, the data of only the channels Ch1and Ch2for which DMA transfer requests are issued from the corresponding peripherals and which are determined active, are DMA-transferred by one bus use right. At this moment, an empty capacity is re-allocated to each channel in accordance with the ratios of the active channels. Thus, it is possible to transfer the data of all the data quantity 16-bytes to be used as the data of only the active channels Ch1and Ch2at all the time including the Chn transfer expected time.

As a third embodiment of the present invention, the DMA transfer of the data of the channels Ch1to Chn that become active is executed in the period of one bus hold request (HOLD), irrespective of whether a plurality of DMA transfer requests are output simultaneously.FIG. 8is a timing chart that explains a DMA transfer processing in the configuration of the third embodiment. Setting conditions are the same as those in the preceding embodiments. Namely, the total burst length of the total burst length register23is 16-bytes, and the Ch1_Ratio, Ch2_Ratio, and Chn_Ratio of the channel ratio register20is 50%, 25%, and 25%, respectively.

It is assumed herein that the peripherals2aand2b, for example, among the peripherals2ato2nfirst output transfer requests DREQ_1and DREQ_2(at the time T1), and the transfer request DREQ_n is delayed (output at the time T2). If so, the channel select control circuit11first determines that the channels Ch1and Ch2are active (outputs ACT_Ch1and ACT_Ch2) based on the rise of the transfer requests DREQ_1and DREQ_2.

The data quantity of each channel is such that the empty area is not used. The1ChBurst length arithmetic circuit21operates the ratio of the data quantity of each channel, and DMA transfer is executed based on the ratios for the active channels. In the example shown, only the channels Ch1and Ch2are determined to be active, 50% of 16-bytes that is TotalBurst length, i.e., the data of 8-bytes of the channel Ch1is DMA transferred, and 25% of 16-bytes that is TotalBurst length, i.e., the data of 4-bytes of the channel Ch2is DMA transferred.

One bus hold request (HOLD) is output to the CPU3, whereby pieces of data of the channels Ch1and Ch2are sequentially DMA-transferred. If the following channel (Chn) becomes active before the data of the final channel (channel Ch2in this example) for which the DMA transfer is performed is finished (at the time T2), the channel select control circuit11executes DMA transfer (4-bytes) of the channel Chn that becomes active in the period in which this one bus use right is acquired (at the time T3).

According to the third embodiment, even if an additional DMA transfer request is output for a certain channel, DMA transfer operations can be continuously executed as long as this additional request is output before the DMA transfer of the active channel is finished, irrespective of whether a plurality of DMA transfer requests are simultaneously output.

FIG. 9is a block diagram that shows the configuration of a fourth embodiment of the channel band guarantee type DMA controller according to the present invention. In the fourth embodiment, the data quantity of each channel to be transferred by the DMA controller by one bus right acquisition is preset in bytes. The DMA channel data quantity setting section12consists of a channel burst length register40that sets the data quantity of each channel in bytes, and a selector41that outputs the data quantities of currently active channels from the channel burst length register40to a read1ChBurst counter13.

FIG. 10is a table that shows one example of the configuration of the channel burst length register40. The channel burst length register40sets a fixed data quantity (in bytes) to be transferred at each of the bits (Bit0to Bit7) of the respective channels. By setting so, it is possible to specify the data quantities to be transferred of a plurality of channels when one bus use right is acquired.

As explained so far, the channel band guarantee type DMA controller in the embodiments of the present invention can transfer the data of a plurality of channels in accordance with respective predetermined ratios whenever one bus use right is acquired.

According to the present invention, when one bus hold request is issued, the band is guaranteed for each channel and the data of the respective channels is continuously DMA-transferred in response to a plurality of DMA transfer requests output from a plurality of peripherals existing on the same bus. It is, therefore, possible to decrease the number of bus management right arbitration procedures and the latency between the channels, to improve transfer efficiency, and to guarantee the minimum transfer rate of each channel. It is thereby possible to facilitate the management of the bus at the time of designing a system.