Apparatus and associated method

A semiconductor arrangement comprising; a normally-on transistor having first and second main terminals and a control terminal, a normally-off transistor having first and second main terminals and a control terminal, the transistors connected in a cascode arrangement by a connection between one of the main terminals of the normally-on transistor and one of the main terminals of the normally-off transistor, a current-source arrangement connected to a node on the connection and configured to provide for control of the voltage at said node between the normally-on and normally-off transistors by providing for a predetermined current flow, wherein the semiconductor arrangement comprises a first semiconductor die of III-V semiconductor type having the normally-on transistor formed therein and a second semiconductor die having the normally-off transistor formed therein, the current-source arrangement formed in the first and/or second semiconductor dies.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority under 35 U.S.C. § 119 of European Patent application no. 16151746.1, filed on Jan. 18, 2016, the contents of which are incorporated by reference herein.

The present disclosure relates to the field of semiconductor arrangements. In particular, it relates to a cascode arrangement of a normally-on transistor and a normally-off transistor.

According to a first aspect of the present disclosure there is provided a semiconductor arrangement comprising;a normally-on transistor having first and second main terminals and a control terminal,a normally-off transistor having first and second main terminals and a control terminal,the normally-on transistor and the normally-off transistor connected in a cascode arrangement by a connection between one of the first and second main terminals of the normally-on transistor and one of the first and second main terminals of the normally-off transistor,a current-source arrangement connected to a node on the connection and configured to provide for control of the voltage at said node between the normally-on and normally-off transistors by providing for a predetermined current flow,wherein the semiconductor arrangement comprises a first semiconductor die of III-V semiconductor type having the normally-on transistor formed therein and a second semiconductor die having the normally-off transistor formed therein, the current-source arrangement formed in the first and/or second semiconductor dies.

This is advantageous as the current-source arrangement has been found to be advantageous for controlling a floating-node voltage in a cascode arrangement. Further, the current-source arrangement can be implemented effectively and efficiently in a cascade arrangement that includes components in a III-V semiconductor die.

In one or more embodiments, the current-source arrangement comprises;a transistor having a drain, a source and a gate;the source of the transistor connected to the gate of the transistor through a resistor element; andwherein the node is connected to the drain of the transistor.

In one or more embodiments, the source of the transistor is configured to be connected to a nominal voltage, such as ground, or any other circuit voltage depending on the implementation of the arrangement. In one or more embodiments, the transistor is formed in the first semiconductor die. In one or more embodiments, the resistor element is formed in first semiconductor die.

In one or more embodiments, the current-source arrangement comprises;a first transistor having a drain, a source and a gate and a second transistor having a drain, a source and a gate;the source of the first transistor connected to the drain of the second transistor;the source of the first transistor connected to gate of the first transistor;the source of the second transistor connected to the gate of the second transistor through a resistor element;wherein the node is connected to the drain of the first transistor.

In one or more embodiments, the source of the second transistor is configured to be connected to a nominal voltage, such as ground, or any other circuit voltage depending on the implementation of the arrangement.

In one or more embodiments, the first transistor and the second transistor are formed in the first semiconductor die.

In one or more embodiments, the resistor element is formed in first semiconductor die. In one or more embodiments, the resistor element comprises, at least in part, a track formed in a two dimensional electron gas region of the first semiconductor die. This is advantageous as the resistance of the semiconductor die may be conveniently used to form the resistor element by isolating a track in the die.

In one or more embodiments, the resistor element is formed in the second semiconductor die. In one or more embodiments, the resistor element is a discrete component.

In one or more embodiments, the first and/or second transistors are HEMTs. In one or more embodiments the HEMTS are of Schottky-gate or insulated-gate type. In one or more embodiments, the first and/or second transistors are selected from MOS transistors, HEMTs, MISHEMTs, SiC transistors and BJTs.

In one or more embodiments, the normally-on transistor is selected from a high-electron-mobility transistor (HEMT or MISHEMT) and a power transistor.

In one or more embodiments, the normally-off transistor is selected from a MOS transistor and a LVMOS transistor.

In one or more embodiments, the first semiconductor die is of Gallium Nitride or Gallium Arsenide, Indium Phosphide, Aluminium Nitride, Indium Gallium Nitride, Gallium Oxide (Ga2O3) or any other III-V semiconductor material suitable for power switching applications. In one or more embodiments, the first semiconductor die is of a material for forming normally-on devices.

In one or more embodiments, the second semiconductor die is of silicon, Silicon Germanium (SiGe), Silicon Carbide (SiC) or any other semiconducting material suitable for power applications.

In one or more embodiments, the current-source is configured to provide a current flow of between 0.1 and 10 μA and the normally-off transistor has a breakdown voltage of less than 40 V. In one or more embodiments, the current-source is configured to provide a current flow of substantially 5 μA and the normally-off transistor has a breakdown voltage of substantially 40 V.

In one or more embodiments, the first semiconductor die and the second semiconductor die comprise the only dies in the semiconductor package incorporating the cascode arrangement and the current-source arrangement.

According to a second aspect of the present disclosure there is provided a semiconductor package including the semiconductor arrangement of the first aspect.

In one or more examples, the first semiconductor die and the second semiconductor die comprise the only dies in the semiconductor package implementing the cascode arrangement and the current-source arrangement. This is advantageous as the semiconductor arrangement and the semiconductor package provide a two-die implementation of a cascode arrangement in III-V and IV semiconductor material with floating-node voltage control. Control over the floating-node voltage ensures that the floating-node voltage is correctly set, which in turn ensures that during switching from on-state to off-state the normally-on device is maintained correctly in its off-state and the normally-on device does not suffer from excursions into its avalanche breakdown mode of operation.

According to a third aspect of the present disclosure there is provided an electronic device including the semiconductor arrangement of the first aspect or the semiconductor package of the second aspect. The electronic device may comprise an amplifier, a cell tower for a mobile phone network, a power supply in a variety of applications, an inverter, a power factor correction (PFC) circuit, half- or full-bridge as well as other power circuit topologies.

According to a fourth aspect of the present disclosure there is provided a method comprising;driving a normally-on transistor with a normally-off transistor, the normally-on transistor and the normally-off transistor connected in a cascode arrangement by a connection between one of first and second main terminals of the normally-on transistor and one of first and second main terminals of the normally-off transistor,providing for a predetermined, fixed, current flow from a node on the connection by way of a current-source arrangement connected to the node and configured to provide for control of the voltage at said node when in the off-state,wherein the normally-on transistor is formed in a first semiconductor die of III-V semiconductor type and the normally-off transistor is formed in a second, different, semiconductor die, the current-source arrangement formed in the first and/or second semiconductor dies.

In cascode arrangements that utilise a III-V based normally-on transistor, a normally-off transistor is used to realise a normally-off switch. Such a cascode arrangement includes a floating-node between the normally-on transistor and the normally-off transistor. The voltage at the floating-node may, in some situations, be sufficient to cause avalanche breakdown of the normally-off transistor. It therefore may be advantageous to control the voltage at the floating-node.

With reference toFIGS. 1 to 4, an example semiconductor arrangement100is shown comprising a normally-on transistor101having first and second main terminals102,103and a control terminal104. The arrangement100further comprises a normally-off transistor105having first and second main terminals106,107and a control terminal108. The normally-on transistor101and the normally-off transistor105connected in a cascode arrangement110by a connection111between one of the first and second main terminals102,103of the normally-on transistor101and one of the first and second main terminals106,107of the normally-off transistor105. It will be appreciated that for a transistor the main terminals are those that connect to the main current path through the transistor (typically termed source and drain), while the control terminal is configured to receive a signal to control the conductance of the main current path (typically termed gate).

When the cascode arrangement inFIG. 3switches from on-state to off-state, the voltage at the floating-node112on the connection111is controlled, in this example, by a current-source arrangement113connected to the node112and configured to provide for control of the voltage between the normally-on and normally-off transistors by providing for a predetermined current flow. After a switching event, the voltage at which the floating-node settles plays an important role in ensuring that transistor101remains turned off and that transistor105transistor does not experience avalanche. Thus, by virtue of the nature of a current-source arrangement, a predetermined and dominant (with respect to other available leakage paths) current flow can be set between node112and ground, which has been found to effectively control the voltage that may be reached at the node112. The current flow comprises a leakage current. The leakage current is established and controlled by the combined resistance of128and124within the current-source. When correctly chosen, this leakage current may perform the dual role of maintaining the normally-on transistor101in its off-state and preventing the normally-off transistor105from reaching its avalanche breakdown voltage.

The semiconductor arrangement100comprises a first semiconductor die114of III-V semiconductor type having the normally-on transistor101formed therein and a second semiconductor die115having the normally-off transistor105formed therein. The current-source arrangement113may be formed substantially wholly within the first semiconductor die114, substantially wholly within the second semiconductor die115or may be distributed over the first and second semiconductor dies114,115.

The first semiconductor die114, in this example, is of Gallium Nitride (GaN). In other examples, it may be of Gallium Arsenide (GaAs), Indium Phosphide, Aluminium Nitride, Indium Gallium Nitride, Gallium Oxide (Ga2O3) or other III-V semiconductors. The second semiconductor die115is of silicon but equally it could be made of other semiconducting materials such as SiGe or SiC.

In this example, the normally-on transistor101, which is a III-V transistor, is a high-electron-mobility transistor with an insulated gate (MISHEMT). However, it will be appreciated that the normally-on transistor may be another type of a power transistor configured to operate in depletion mode, such as a JFET. In this example, the normally-off transistor105is a MOS transistor and, in particular, an LVMOS (low voltage MOS transistor). It will be appreciated that in other examples, the normally-off transistor may comprise a different type of power transistor such as a trench MOS transistor, DMOS, smart-power, SiC, BJT and other enhancement-mode device for power applications.

The first and second main terminals102,103of the HEMT101comprise drain and source respectively. The control terminal104of the HEMT101comprises a gate. The drain102is configured to be connected to a supply voltage, Vdd. The first and second main terminals106,107of the MOS transistor105comprise drain and source respectively. The control terminal108of the MOS transistor comprises a gate. The connection111is formed between the source103of the HEMT101and the drain106of the MOS transistor105. Accordingly, the node111may be considered to be at the source103of the HEMT or the drain106of the MOS transistor. The connection111may be implemented as a bond wire extending between a respective source bond pad and drain bond pad of the HEMT101and the MOS transistor105, between the semiconductor dies.

With reference to the cascade arrangement110, the source of the MOS transistor105is configured to be connected to a nominal voltage, such as ground. Further, in this example, the source107of the MOS transistor105(normally-off transistor) is connected to the gate of the HEMT104(normally-on transistor). A control voltage Vg is provided at the gate108of the MOS transistor for control of the cascade arrangement110.

In this example, the current-source arrangement113has two terminals comprising a first terminal116and a second terminal117. The first terminal116is connected to the node112. The second terminal117is configured to be connected to a nominal voltage, such as ground.

The current-source arrangement113may comprise a diode and a transistor in series, the transistor configured to be connected to a nominal voltage, such as ground, via a resistor element. The first terminal116may be provided by a first terminal of the diode, wherein a second terminal of the diode is connected to the transistor. The gate of the transistor may be configured to be connected to the nominal voltage such as ground. The diode arrangement may comprise a transistor where its source is connected to its gate and its drain comprises the first terminal116of the current-source arrangement113.

In this example, the current-source arrangement113, with reference toFIG. 4, comprises a first transistor120having a drain121, a source122and a gate123(such as a Schottky gate) and a second transistor124having a drain125, a source126and a gate127. The first and second transistors are arranged in series. The source122of the first transistor120is connected to the drain125of the second transistor124. The source122of the first transistor120is connected to gate123of the first transistor120, which effectively forms a diode arrangement. The source126of the second transistor124is connected to the gate127of the second transistor124through a resistor element128. Further, the source126of the second transistor124is configured to be connected to a nominal voltage, such as ground, through the resistor element128. The first terminal116of the current-source arrangement thus comprises the drain121of the first transistor120, which is connected to the floating-node112.

In another example, the current-source arrangement113does not include the transistor120and the drain125of the second transistor124comprises the first terminal116of the current-source arrangement. Accordingly, the drain125of the second transistor120is connected to the floating-node112. It will be appreciated that in this example, the “second” transistor may be renamed as the transistor of the current source.

In the arrangements ofFIGS. 1 and 2, the first transistor120and the second transistor124of the current-source arrangement113are formed in the first semiconductor die114. However, it will be appreciated that they may be formed in the second semiconductor die in other examples or be implemented in a separate third die. In this example, the first transistor120and the second transistor124of the current-source arrangement113comprise HEMTs. The HEMTs120,124of the current-source arrangement may be of substantially equal size, such as around 200 μm in gate width. The HEMTs120,124of the current-source arrangement may be smaller (much smaller) than the HEMT101of the cascode arrangement110. While the transistors120,124of the current-source arrangement113comprise HEMTs in this example, they may be a different type of transistor, such as MISHEMTs implemented in GaN or silicon transistors comprising a current-source implemented on a separate die and connected to the floating-node112via bond wires.

In this example, the resistor element is between 100 kΩ and 10 MΩ or 500 kΩ and 1.5 MΩ, or substantially 1 MΩ. In particular, the resistor element may be sized to achieve a current flow through the current-source arrangement113of between 1 and 10 μA, such as substantially 5 μA. Such a current flow has been found to provide for effective control of the voltage at the floating-node112.

The current through the current-source113is chosen so that it dominates the leakage in the cascode circuit once transistor101reaches its off-state condition. This ensures that the floating-node112settles at a predictable voltage that is substantially entirely controlled by the current-source113.

The off-state condition of transistor101is met when the floating-node voltage rises above the threshold voltage (VT) of transistor101. The VTof transistor101is typically −10V to −20V, which means that the floating-node voltage will settle a little above this value.

A safe and dominant leakage current flowing through the current source113may be at least 50× or 100× greater than a leakage current of transistor101and/or105, which will typically leak 10 s of nA each. Hence, the current flow provided by the current source may be several μA.

For the purpose of illustration, let us assume that the threshold voltage VTof the transistor101is −20V and that the leakage of the transistor101and/or transistor105is 20 nA, which means that the leakage through the current-source113may be set to 100×20 nA=2 μA (100× leakage current).

Knowing the required current-source leakage of 2 μA, one can use Ohm's law to work out the required total resistance of the current source arrangement113:

R113=VT⁢⁢101I113=20⁢⁢V2⁢⁢μA=10⁢⁢MOhm
Where R113is the resistance of the current source arrangement113, VT101is the threshold voltage of the transistor101and I112, is the desired current through the current-source arrangement.

Accordingly, the current source arrangement may be configured such that the 10 MOhms in this example is made up of resistor128and the resistance of transistor124, determined by its sub-threshold operation transconductance. The transconductance of any transistor is set by its manufacturing technology and will vary from product to product. Therefore, it is necessary to select the value of resistor128until the combined resistance of128and124is approximately 10 MOhms. It will be appreciated that transistors with a wide range of resistances may be used for transistor124and accordingly the value of the resistor128may be between 100 kOhm and 5 MOhm.

By way of further explanation the reasons for making the leakage in the current-source113substantially dominant are explained below.

During transient events the floating-node voltage is set by the ratio of a COSScapacitance in transistor101and105, while in steady-state operation (away from transients) the floating-node voltage may settle at an intersection803,804of the current-source113loadline800and a leakage curve801,802(curve801represents a typical leakage curve at 25° C. and curve802represents a typical leakage curve at 100° C.) of the transistor101or105, as illustrated schematically inFIG. 8.FIG. 8shows the drain-source current of the transistor101versus the source-gate current of the transistor101. In the left part ofFIG. 8there is shown the drain-source current of the transistor101versus the source-gate current of the transistor101, while in the right part ofFIG. 8there is shown schematically the leakage and breakdown voltage curve (805and806) of the transistor105versus the source-gate current of the transistor101.

When the transistor101enters its off-state, there will be competition between a gate leakage IDGof the transistor101and a drain leakage IDSof transistor105. As a result, the floating-node voltage may be poorly defined and inconsistent from device to device.

To counteract this competition and to set the floating-node voltage accurately, the current source arrangement113provides a parallel leakage path, which may be higher than the floating-node to ground leakage path. This way control over the floating-node voltage is established and substantially determined by the current-source arrangement113.

It may be desirable, for reliable operation, for the floating-node voltage to settle above the VTof transistor101and below breakdown voltage BVOSSof transistor105, such as half-way between these two voltages. This is indicated schematically inFIG. 8as loadline intersections803,804.

The intersection point803and thus the current provided by the current source arrangement may be chosen in accordance with one or more of the following conditions (with reference toFIG. 8):the current is such that the voltage at the node112may be greater than VTof transistor101, such as by 1-5 volts;the current is such that the voltage at the node112may be such that the current-source113loadline intersects the transistor101and/or105's leakage curve at point803, which represents a current much greater than the background leakage of transistor101and/or105. In this example, the intersection point is at 2 μA vs a leakage of 20 nA, that is, a factor of 100× greater;the current is such that the voltage at the node112voltage may be below the breakdown voltage of transistor105transistor by substantially 3-5 volts.

In another example, not shown, the transistors120,124of the current-source arrangement113are provided in the second semiconductor die115with the MOS transistor105. In another example, not shown, one of the transistors120,124of the current-source arrangement113is provided in the first semiconductor die114and the other is provided in the second semiconductor die115.

InFIG. 1, the resistor element128is formed in the first, GaN, semiconductor die114. Thus, the current-source arrangement is formed substantially exclusively in the first semiconductor die114. InFIG. 2, an alternative layout is provided in which the current-source arrangement113is split over the two semiconductor dies114,115. The transistors120,124of the current-source arrangement113are, in this example, located in the first semiconductor die114represented by box130and the resistor element128is located in the second semiconductor die115represented by box131. The resistor element128may comprise a discrete component or comprise a thin film resistor. In a further example, the resistor element128is provided over both the first and second semiconductor dies114,115.

It will be appreciated that however the resistor element is formed it essentially comprises a path of resistive material, which can include connections between parts of the dies. Thus, while the majority of the resistance provided by the resistor element128may be located on one of the dies114,115it will be appreciated that connections between the dies may contribute to its desired total resistance.

Considering first the layout ofFIG. 1, the resistor element128is formed within the III-V semiconductor material. Thus, a track formed by component isolation techniques is arranged in the first, III-V, semiconductor die114having the desired resistance. For a semiconductor die of GaN, the conductive two dimensional electron gas region (2DEG) has a sheet resistance of approximately 650 Ω/sq. Thus, for a track width of approximately 5 μm and a track length of 7.7 mm a resistor element of resistance IMO may be achieved.

FIG. 5shows an example layout in the second semiconductor die114of the current-source arrangement113.FIG. 5shows the first transistor120connected to the second transistor124and a resistive track132providing the resistor element128connected between the source126and the gate127of the second transistor124.

FIG. 6shows a package600including the semiconductor arrangement100described above. The package600may include only two semiconductor dies comprising the first, III-V, semiconductor die114and the second semiconductor die115. The package600typically includes leads for connection to other components (not shown). The package is shown as part of an electronic device601. The electronic device601may comprise an amplifier, a mobile cell tower, a communication device, a power supply with half-bride or full bridge circuit topology, a PFC control circuit or an inverter in solar panels.

FIG. 7shows a method of operating a cascode arrangement of a normally-on transistor driven by a normally-off transistor. The method comprises driving701a normally-on transistor101with a normally-off transistor105, the normally-on transistor101and the normally-off transistor105connected in a cascode arrangement110by a connection111between one of first and second main terminals103of the normally-on transistor and one of first and second main terminals106of the normally-off transistor. The method comprises providing702for a predetermined, fixed, current flow from a node112on the connection by way of a current-source arrangement113connected to the node and configured to provide for control of the voltage at said node, wherein, the normally-on transistor is formed in a first semiconductor die114of III-V semiconductor type and the normally-off transistor is formed in a second, different, semiconductor die115, the current-source arrangement formed in the first and/or second semiconductor dies114,115.

Various terminals are described above as connected to a supply voltage, Vdd, or a nominal voltage. It will be appreciated that the arrangement disclosed herein may be connected to other circuitry in a variety of ways and therefore the nominal voltage may be a different supply voltage to the supply voltage Vdd, or may be ground.