Device, system and method of delay calibration

System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.

BACKGROUND

Voltage-controlled or current-controlled delay cells have numerous applications in circuit design. In delay-locked loops (DLLs) a cascade of delay cells forms a delay line that is controlled through feedback action by a charge pump and/or a phase detector to set the overall delay to a specific value. Controllable-delay cells are also used in ring oscillators. Multi-stages DLLs or ring oscillators are used to generate multi-phase signals. Multi-stage DLLs are further used to implement a frequency divider or multiplier with a fractional division or multiplication ratio, for example, by using a multiplexer known as an edge-combiner.

In typical implementations, process variations may produce considerable mismatches between the multiple delay cells that form the DLL or the ring oscillator. This may cause an error in the different phases generated through the DLL or ring oscillator. For example, a mismatch in the delay of the stages may cause frequency spurs. Furthermore, if the phase difference between the various outputs is not equal, a periodic time error may appear at the output. These spurs may substantially limit the application of the DLL as a frequency divider/multiplier where high spectral purity clock is required. For example, if one of the multiple delay cells exhibits a delay mismatch of approximately 10 percent, the power of the output spur would be approximately −32 dBc (namely, approximately 0.32 decibels below the carrier). However, some wireless communication standards may require spurs to be as low as −65 dBc for the local oscillator.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of some embodiments of the invention. However, it will be understood by persons of ordinary skill in the art that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, units and/or circuits have not been described in detail so as not to obscure the discussion.

Some embodiments of the invention may be used in conjunction with various devices and systems, for example, a transmitter, a receiver, a transceiver, a transmitter-receiver, a wireless communication station, a wireless communication device, a wireless access point (AP), a modem, a wireless modem, a personal computer, a desktop computer, a mobile computer, a laptop computer, a notebook computer, a tablet computer, a handheld computer, a server computer, a personal digital assistant (PDA) device, a handheld PDA device, a network, a wireless network, a local area network (LAN), a wireless LAN (WLAN), a metropolitan area network (MAN), a wireless MAN (WMAN), wide area network (WAN), wireless WAN (WWAN), a personal area network (PAN), a wireless PAN (WPAN), devices and/or networks operating in accordance with existing Institute of Electrical and Electronics Engineers (IEEE) standards such as IEEE 802.11, 802.11a, 802.11b, 802.11g, 802.11n, 802.16, 802.16d, 802.16e, and other derivatives, long-term evolution (LTE) standards and/or future versions of the above standards, units and/or devices which are part of the above networks, one way and/or two-way radio communication systems, cellular radio-telephone communication systems, a cellular telephone, a cellular smartphone, a wireless telephone, a personal communication systems (PCS) device, a PDA device which incorporates a wireless communication device, a mobile or portable global positioning system (GPS) device, a device which incorporates a GPS receiver or transceiver or chip, a device which incorporates a radio frequency identification element or chip, a multiple input multiple output (MIMO) transceiver or device, a single input multiple output (SIMO) transceiver or device, a multiple input single output (MISO) transceiver or device, a multi receiver chain (MRC) transceiver or device, a transceiver or device having “smart antenna” technology or multiple antenna technology, a device having one or more internal antennas and/or external antennas, a wired or wireless handheld device, a wireless application protocol (WAP) device, or the like.

In some embodiments, the system and method disclosed herein may be implemented in many wireless, handheld and portable communication devices. By way of example, wireless, handheld and portable communication devices may include wireless and cellular telephones, smart telephones, personal digital assistants (PDAs), web-tablets and any device that may provide wireless access to a network such, an intranet or the internet. Some embodiments of the invention may be used in conjunction with one or more types of wireless communication signals and/or systems, for example, radio frequency (RF), infra red (IR), frequency-division multiplexing (FDM), orthogonal FDM (OFDM), orthogonal frequency-division multiple access (OFDMA), s-OFDMA, time-division multiplexing (TDM), time-division multiple access (TDMA), extended TDMA (E-TDMA), general packet radio service (GPRS), extended GPRS, code-division multiple access (CDMA), wideband CDMA (WCDMA), CDMA 2000, multi-carrier modulation (MDM), discrete multi-tone (DMT), Bluetooth®, global positioning system (GPS), WiFi, WiMax, ZigBee™, ultra-wideband (UWB), global system for mobile communication (GSM), 2G, 2.5G, 3G, 3.5G, or the like. Embodiments of the invention may be used in various other devices, systems and/or networks.

Discussions utilizing terms such as, for example, “processing,” “computing,” “calculating,” “determining,” “establishing”, “analyzing”, “checking”, or the like, may refer to operation(s) and/or process(es) of a computer, a computing platform, a computing system, or other electronic computing device, that manipulate and/or transform data represented as physical (e.g., electronic) quantities within the computer's registers and/or memories into other data similarly represented as physical quantities within the computer's registers and/or memories or other information storage medium that may store instructions to perform operations and/or processes. In addition, the terms “plurality” and “a plurality” as used herein include, for example, “multiple” or “two or more”. The terms “plurality” or “a plurality” may be used throughout the specification to describe two or more components, devices, elements, units, parameters, or the like.

Although portions of the discussion herein may relate, for demonstrative purposes, to a wireless communication system, a wireless transmitter and/or a wireless receiver, embodiments of the invention are not limited in this regard, and may be used, for example, in conjunction with non-wireless (e.g., wired) communication systems, transmitters and/or receivers, for example, PCI (Peripheral Component Interconnect) Express (PCIe) communications and/or systems.

FIG. 1schematically illustrates a communication system100in accordance with some demonstrative embodiments of the invention. System100may include one or more communication stations or devices, for example, devices110,120, and130. System100may optionally include other communication devices, for example, a wireless access point (AP), a base station, a servicing station, or the like. Devices110,120, and130may communicate using a shared access medium190, for example, through wireless communication links191,192, and193respectively.

In some embodiments, system100may be or may include one or more wireless communication networks, for example, an a synchronic wireless network, an asynchronous wireless network, a synchronic wireless network, a burstable wireless network, a non-burstable wireless network, a hybrid network, a combination of one or more networks, or the like. In some other embodiments, system100need not be implemented as a wireless communication system, and may be implemented, for example, as a computing platform, a processing platform, a PCIe device, a PCIE transmitter/receiver, a Serializer/Deserializer (SerDes) device, a SerDes transmitter/receiver, or the like.

Devices110,120, and130may each be associated with one or more radio frequency antennas, for example, antennas117,127, and137, respectively, to facilitate communication via wireless links191-193. Each of antennas117,127, and137may include or may be, for example, an internal and/or external RF antenna, a dipole antenna, a monopole antenna, an omni-directional antenna, an end-fed antenna, a circularly polarized antenna, a micro-strip antenna, a diversity antenna, or any other type of antenna suitable for transmitting and/or receiving wireless communication signals, blocks, frames, transmission streams, packets, messages and/or data. Optionally, each of antennas117,127, and137may be implemented using a common antenna, a common set of multiple antennas, or other suitable component(s).

Wireless links191-193may each include a downlink and an uplink for carrying traffic between a transmitting device and a receiving device. The network traffic carried via links191-193may include packets, flames, or other collections of signals and/or data, such as, for example, media access controller (MAC) protocol data units (MPDUs) and/or physical layer (PHY) protocol data units (PPDUs), that may make up a transmission of wireless signals.

Device110may be or may include, for example, a computing station, a computing device, a computer, a personal computer (PC), a server computer, a client/server system, a mobile computer, a portable computer, a laptop computer, a notebook computer, a tablet computer, a mobile phone, a cellular phone, a handheld device, a network of multiple inter-connected devices, or the like.

Device110may include, for example, a processor111, a memory unit112, a storage unit113, a clock114, and a transceiver115. Device110may optionally include other suitable hardware components and/or software components. In some embodiments, some or all of the components of device110may be enclosed in a common housing or packaging, and may be interconnected or operably associated using one or more wired or wireless links. In other embodiments, components of device110may be distributed among multiple or separate sub-units, devices or locations.

Processor111includes, for example, a central processing unit (CPU), a digital signal processor (DSP), one or more processor cores, a single-core processor, a dual-core processor, a multiple-core processor, a microprocessor, a host processor, a controller, a plurality of processors or controllers, a chip, a microchip, one or more circuits, circuitry, a logic unit, an integrated circuit (IC), an application-specific IC (ASIC), a CMOS chip, or any other suitable multi-purpose or specific processor or controller. Processor111may executes instructions, for example, of an operating system (OS) of device110or of one or more applications.

Memory unit112includes, for example, a random access memory (RAM), a read only memory (ROM), a dynamic RAM (DRAM), a synchronous DRAM (SD-RAM), a flash memory, a volatile memory, a non-volatile memory, a cache memory, a buffer, a short-term memory unit, a long-term memory unit, or other suitable memory units. Storage unit113includes, for example, a hard disk drive, a floppy disk drive, a compact disk (CD) drive, a CD-ROM drive, a digital versatile disk (DVD) drive, or other suitable removable or non-removable storage units. Memory unit112and/or storage unit113, for example, may store data processed by station110.

Clock114may include, for example, a real-time clock, a system clock, a counter, a timer, a component able to perform timing or counting operations, a component able to track time, a component able to provide time data or time parameters, or the like. In some embodiments, clock114may be operationally associated with transceiver115.

Device110further includes one or more transceivers, for example, a wireless transceiver115able to operate in accordance with IEEE 802.11 standard and/or IEEE 802.16 standard and/or other suitable wireless communication standards or protocols. In some embodiments, transceiver115may be a wired or wireless transceiver, for example, a PCIe transceiver or a SerDes transceiver.

Transceiver115may include a transmitter and/or a receiver, a transmitter-receiver, or other circuitry or sub-units able to transmit and/or receive wired or wireless signals, radio frequency (RF) signals, blocks, frames, transmission streams, packets, messages and/or data, e.g., through antenna117. Transceiver115may be co-located with other communication components, for example, using a common housing, packaging, card, circuit, modem unit, wireless network interface card (NIC), or communication unit.

Transceiver115may include or may be operatively associated with a Clock and Data Recovery (CDR) unit116, for example, to recover embedded clocking information in received signals. The CDR unit116may, for example, detect an optimal or neatly optimal sampling point of one or more data bits in the signal received by transceiver115, and may generate a correcting signal to automatically correct the data sampling point.

CDR unit116may include, or may be associated with, a delay-mismatch calibrating unit199able to calibrate delay(s) for the CDR unit116. The delay-mismatch calibrating unit199may include components and/or functionalities similar to the components and/or functionalities of system200, as described herein with reference toFIG. 2.

FIG. 2schematically illustrates a system200for delay-mismatch calibration in accordance with a demonstrative embodiment of the invention. System200may be implemented in connection with, for example, a delay-locked loop (DLL), a phase-locked loop (PLL), a ring oscillator, a voltage-controlled oscillator (VCO), a frequency synthesizer, a fractional frequency divider, or the like. For example, system200may be used to calibrate delay for a CDR unit (e.g., CDR116ofFIG. 1), a high-speed clock generation unit, or the like.

Some embodiments utilize a calibration technique and algorithm to calibrate the mismatch of several delay cells and equalize their individual delays. The technique is demonstrated herein as applied to a demonstrative DLL architecture, but it may be used to calibrate substantially any number of delay cells in other architectures where delay mismatch correction is required, such as ring oscillators, to multi-stage DLLs, and so forth.

In some embodiments, system200includes a clock source201, a main (or primary) DLL208, and an auxiliary (or replica, or secondary) DLL209. System200further includes a sampling capacitor280(e.g., to store an output voltage281), an analog-to-digital converter (ADC)295(e.g., to convert the output signal) and a memory and/or storage element296, denoted DEL, for use in the calibration method as described herein with reference toFIGS. 3 and 4.

The main DLL208includes a plurality of delay elements arranged in a cascade, for example, voltage-controlled delay cells211-214having two separate control ports. A first control port may be controlled by the DLL feedback action to provide the same control voltage261for all of the delay cells211-214. The feedback of DLL208may be controlled by a phase detector and/or a charge pump292(e.g., to set the overall delay and to align clock signal edges), a switch265(to lock the loop, denoted LOCK_A), and a capacitor260(to store the feedback voltage261). A second control port may be used to adjust the delay of each of the delay cells211-214separately, for example, to compensate for mismatches between the individual delay cells211-214. For example, in some embodiments delay cell211may be controlled by a correcting voltage221, delay cell212may be controlled by a correcting voltage222, delay cell213may be controlled by a correcting voltage223, and delay cell214may be controlled by a correcting voltage224. The correcting voltage for the second control port of each delay cell211-214may be calibrated according to the method described herein with reference toFIGS. 3 and 4.

The auxiliary DLL209may be a replica of the main DLL208. For example, auxiliary DLL209may include voltage-controlled delay cells241-244that are replicas of delay cells211-214, respectively. However, for the auxiliary DLL209, the separate control ports for delay mismatch correction are not included and/or are not used. Delay cells241-244may be controlled by control voltage271based on the DLL feedback loop. The feedback of DLL209may be controlled by a phase detector and/or a charge pump294(e.g., to set the overall delay and to align clock signal edges), a switch275(to lock the loop, denoted LOCK_B), and a capacitor270(to store the feedback voltage271).

DLLs208and209may each be associated with an additional delay element, for example, delay cells210and240, respectively. Delay elements210and240may receive a clock signal202from the clock source201, and delay it by a fixed or constant amount, for example, to provide an offset buffer for measuring and/or adjusting the relative delay of the first delay element in the DLL. In some embodiments, the delay cell210associated with the main DLL208may produce a delayed clock signal230having a fixed delay; and the delay cell240associated with the auxiliary DLL209may be adjustable, e.g., to produce a delayed clock signal250that is aligned with the delayed clock signal230.

In some embodiments, DLLs208and209may be associated with multiplexers and/or edge combiners291and293, respectively. In DLL208, each of the delay cells210-214may output a delayed clock signal according to the delay of the respective element, for example, delayed signals230-234(also denoted O0A-O4A), respectively. Multiplexer291may be controlled by a selection signal204(denoted SEL_A) to select which of the delayed clock signals230-234is output as a clock signal205, denoted CKA. In DLL209, each of the delay cells240-244may output a delayed clock signal according to the delay of the respective element, for example, delayed signals250-254(also denoted O0B-04B), respectively. Multiplexer293may be controlled by a selection signal206(denoted SEL_B) to select which of the delayed clock signals250-254is output as a clock signal207, denoted CKB. Signals CKAand CKBmay be used as input to the phase detector with charge pump294.

FIG. 3is a schematic flow-chart of a method300of estimating gain in accordance with a demonstrative embodiment of the invention. Operations of the method may be used, for example, by system200ofFIG. 2and/or by other suitable units, devices and/or systems. In some embodiments, method300may be used to estimate the gain (in terms of seconds of delay per volt of applied control signal, s/V) of a port used to correct delay mismatches, for example, the gain of one or more of correction ports221-224ofFIG. 2(also denoted corr1-corr4).

As indicated at block310, the loop in the main DLL208is closed (lock_A=1), e.g., using switch265, and sufficient time is waited to let the loop to properly lock (block312). As indicated at block314, when the main DLL208is completely locked, outputs O0A (from delay element210of DLL208) and O0B (from delay element240of DLL209) are selected using the multiplexer controls SEL_A and SEL_B, respectively. The auxiliary loop209is closed (lock_B=1), e.g., using switch275, to allow for lock. Capacitor280(CD) integrates the charge dumped by the PFD and charge pump294of the auxiliary loop for a given number of input clock cycles of CKA205from the main loop208. After that, the voltage281(VD) is sampled by the ADC295, the value stored in the variable DEL and the capacitor CDis reset, so that the integration cycle may be restarted.

As indicated at block316, when the sampled value of VDis zero, the system recognizes that CKAand CKBare aligned, that is, that the auxiliary loop209is locked. As indicated at block318, at this point both loops may be opened. For example, switch265of the primary DLL may be opened (lock_A=0), with the proper control voltage preserved on capacitor260(CA); and switch275of the auxiliary DLL may be opened (lock_B=0), with the proper control voltage stored on capacitor270(CB). With both loops opened, the output O1A of the primary DLL may then be selected by SEL_A and fed to CKA. Accordingly, the time difference at the input of the auxiliary PFD between CKAand CKBmay now equal the delay of the cell221in the main DLL208, including all the interconnections up to the output of the multiplexer291. This delay is integrated on the capacitor CD, sampled by the ADC295and stored in DEL. As indicated at blocks318-324, this measurement is repeated with the correction for cell211set to minimum and maximum values.

As indicated at block326, the gain for the correction port may be estimated based on the following equation, denoted Equation 1, where del1maxand del1minare the delay of cell1measured with the maximum (corr1max) and minimum (corr1min) applied correction respectively:
GAIN≈(del1max−del1min)/(corr1max−corr1min)  Equation 1

This sequence may be repeated to measure the gain of the correction port for each delay cell. Measuring the gain of each delay cell correction port may allow for a faster convergence of the delay mismatch calibration algorithm described with reference toFIG. 4. However, in some embodiments, the calibration method described herein may be used based on the gain calculated for just one delay cell.

Other suitable operations may be used, and other suitable orders of operation may be used. One or more operations may be repeated, for example, for a pre-defined time period, for a pre-defined number of iterations, substantially continuously, at pre-defined time intervals, until a pre-defined condition holds true, or based on other criteria.

FIG. 4is a schematic flow-chart of a method400of calibrating delay in accordance with a demonstrative embodiment of the invention. Operations of the method may be used, for example, by system200ofFIG. 2and/or by other suitable units, devices and/or systems. In some embodiments, method400may provide the delay mismatch correction itself, for example, as a continuation of the gain estimation method described with reference toFIG. 3.

As indicated at block410, the main loop208is closed (lock_A=1) and let to lock (block412). As indicated at block414, outputs O0A and O0B are selected and fed to CKAand CKB, respectively. The auxiliary DLL209is also closed (lock_B=1) and the system waits for DEL to go to zero as an indication of the achieved lock (block416). Now, the signal CKAcoming from O0A and the signal CKBcoming from O0B may be aligned.

As indicated at block418, at this point, the auxiliary loop209is opened (lock_B=0) and the output O1A from delay cell211is routed to CKAby the multiplexer291. The time difference at the input of the auxiliary PFD294may represent the delay of the first cell211in the main DLL208, including all the interconnections up to the output of the multiplexer291. This delay is sampled and stored in DEL.

To measure the delay of the second cell212in the main DLL208, the output O1B from the auxiliary DLL209may be selected for CKB(block420). The auxiliary loop209is closed again to realign CKAand CKB(block420). When the sampled value of DEL becomes zero (block422), the auxiliary loop209is opened (block424), and the output O2A from the main DLL is selected (block424) so that the delay of cell212may be measured as integrated charge on CDand stored in DEL (block424). As indicated at block426, the same sequence may be repeated to measure the delay of each stage in the main DLL, with each repetition advancing the selected outputs.

At the end of the process, four measured delays, del1, del2, del3and del4, may be available in the storage element DEL296, corresponding to the four delay elements211-214of the main DLL208. These values may be different due to delay mismatch. Accordingly, as indicated at block428, the delay-mismatch calibration system may calculate the updated values for the corrections221-224to be applied to each DLL stage as a function of how much each measured delay deviates from the average. For example, the updated correction value for the first delay cell may be estimated according to the following equation, denoted Equation 2:

In the example architecture ofFIG. 2, there are four stages in the main DLL, so i ranges from 1 to 4 in Equation 2, and total_stages=4. It can be shown that this algorithm converges so that at the end corr(n+1)=corr(n) and all the delays are ultimately equal.

In some embodiments, method400may be repeated until the updated correction parameters remain unchanged. Other suitable operations may be used, and other suitable orders of operation may be used. One or more operations may be repeated, for example, for a pre-defined time period, for a pre-defined number of iterations, substantially continuously, at pre-defined time intervals, until a pre-defined condition holds true, or based on other criteria.

In some embodiments, the calibration algorithm may be applied to a divide-by-125 architecture similar to the architecture shown inFIG. 2. For example, the main DLL may include eight stages; the ADC used to measure the delays may have ten bits; each delay cell correction value may be generated using a 6-bit digital-to-analog converter (DAC); the input frequency from the clock source may be 7.5 GHz; and the output frequency when the edge-combiner (multiplexer) is activated may be 7.5 GHz divided by 1.25, namely, 6 GHz. All the parameters of the delay cells (correction gain, main control gain, and intrinsic delay) may be statistically generated using Gaussian distribution, for example, with a 3sigma of 50 percent. In such a configuration, the spurs may be reduced from −28 dBc to −60 dBc, namely, more than 30 dBc reduction.

In some embodiments, the ADC is in close proximity and connected to a clock generation circuit, to allow utilization of the calibration scheme. The ADC may include capacitors and/or other structure, and the clock generation circuit may have RF routing to a VCO (e.g., cell with inductor).

Some embodiments may include a replica DLL close to the main DLL to allow utilization of the calibration technique. The DLL may have a structure (e.g., several identical delay cells repeated) associated with clock routing going from the VCO (circuit with the inductor) to the DLL, and form the DLL to each transmitter and/or receiver.

In some embodiments, calibration may run at power up or between packets, and monitoring TX/RX output (possibly through leakage) may indicate usage of the calibration scheme. In some embodiments, spurs with decreasing power over time are an indication of a delay calibration being performed. The frequency of the spurs may be estimated based on output frequency and frequency of VCO, for example, as measured with an antenna.

In some embodiments, the calibration technique is robust, since it relies on the relative measurement of the same quantity. The algorithm may force the measured delays to be equal; as the difference between the delays is reduced, so is the relative error introduced by any absolute errors due to non-idealities in the several circuit blocks used for the calibration, such as the PFD, the CP and the sampling capacitors. When the algorithm converges, any error may affect the measurement of each delay in the same manner, thus canceling out in the estimation of the updated corrections. This is true also for the estimation of the gain of the correction port. Even if each delay cell has a different gain for its correction port and the algorithm uses the gain estimated from one of them to update all the corrections, the initial error generated by a wrong estimated gain may converge to zero as the delay mismatches are corrected.

The calibration algorithm includes measuring the delay of one single cell at a time by moving the time reference generated by an auxiliary DLL. Some embodiments utilize the robustness of the technique (the effect of measurements error is canceled out) and the possibility of maximizing the circuit dynamic range for the measurement of one single delay. For example, since the system measures the delay of just one cell at a time, the full dynamic range of the auxiliary charge pump, sampling capacitor and ADC can be used for each measurement, thus relaxing their circuit design for a given resolution.

In some embodiments, the calibration technique allows the use of multi-phase DLLs or ring oscillators in high-spectral purity applications, such as new generation wireless radios, where requirements on spurs and/or I&Q matching are very stringent. The calibration of the multi-stage DLL allows the use of a fractional DLL based divider in high-speed, high process spread CMOS technologies without penalty on output spurs. The use of such fractional divider may allow for more flexible frequency plan for the local oscillator (LO) generation. Moreover, such divider can offset the frequency of the oscillator that is generating the LO signal from the output frequency of the PA, thus avoiding pulling issues.

Some embodiments may obviate the need to use single-sideband (SSB) mixing; the SSB mixer requires large inductors and considerable filtering in order to meet the stringent spur and image-rejection requirements. The calibration technique may therefore allow the use of fractional DLL based divider for this kind of applications, thus reducing the overall silicon area by eliminating inductors and additional filtering in the LO generation. This will improve integration, reduce cost and deliver a digital-friendly architecture that scales very well in future CMOS process nodes, thus reducing the product time-to-market.

Some embodiments of the invention, for example, may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment including both hardware and software elements. Some embodiments may be implemented in software, which includes but is not limited to firmware, resident software, microcode, or the like.

In some embodiments, the method described herein may be implemented in machine-executable instructions. These instructions may be used to cause a general-purpose or special-purpose processor that is programmed with the instructions to perform the operations described. Alternatively, the operations may be performed by specific hardware that may contain hardwired logic for performing the operations, for example, an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA), or by any combination of programmed computer components and custom hardware components. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the desired method.

Furthermore, some embodiments of the invention may take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For example, a computer-usable or computer-readable medium may be or may include any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

In some embodiments, the medium may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Some demonstrative examples of a computer-readable medium may include a semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. Some demonstrative examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W), and DVD.

In some embodiments, a data processing system suitable for storing and/or executing program code may include at least one processor coupled directly or indirectly to memory elements, for example, through a system bus. The memory elements may include, for example, local memory employed during actual execution of the program code, bulk storage, and cache memories which may provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.

In some embodiments, input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) may be coupled to the system either directly or through intervening I/O controllers. In some embodiments, network adapters may be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices, for example, through intervening private or public networks. In some embodiments, modems, cable modems and Ethernet cards are demonstrative examples of types of network adapters. Other suitable components may be used.