Transistor Isolation Regions and Methods of Forming the Same

In an embodiment, a device includes: first source/drain regions; a first insulating fin between the first source/drain regions, the first insulating fin including a first lower insulating layer and a first upper insulating layer; second source/drain regions; and a second insulating fin between the second source/drain regions, the second insulating fin including a second lower insulating layer and a second upper insulating layer, the first lower insulating layer and the second lower insulating layer including the same dielectric material, the first upper insulating layer and the second upper insulating layer including different dielectric materials.

BACKGROUND

DETAILED DESCRIPTION

According to various embodiments, insulating fins are formed between source/drain regions. The insulating fins block epitaxial growth, thereby allowing the source/drain regions to remain separated after the epitaxial growth. Upper portions of the insulating fins between the source/drain regions are replaced with a material that provides better electrical isolation between adjacent source/drain regions. This can reduce leakage, thereby improving the performance of the resulting nano-FETs. Advantageously, the upper portions of the insulating fins that will be replaced are formed of different materials in different regions. Specifically, the upper portions of the insulating fins in dense regions are formed of a first dielectric material, and the upper portions of the insulating fins in sparse regions are formed of a second dielectric material that is different from the first dielectric material. The upper portions of the insulating fins in the different regions thus have etching selectivity from one another, allowing separate etching processes to be used when replacing the upper portions of the insulating fins in the different regions, thereby avoiding pattern loading effects.

Embodiments are described in a particular context, a die including nano-FETs. Various embodiments may be applied, however, to dies including other types of transistors (e.g., fin field-effect transistors (finFETs), planar transistors, or the like) in lieu of or in combination with the nano-FETs.

FIG.1illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like), in accordance with some embodiments.FIG.1is a three-dimensional view, where some features of the nano-FETs are omitted for illustration clarity. The nano-FETs may be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), or the like.

The nano-FETs include nanostructures66(e.g., nanosheets, nanowires, or the like) over semiconductor fins62on a substrate50(e.g., a semiconductor substrate), with the nanostructures66acting as channel regions for the nano-FETs. The nanostructures66may include p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions72, such as shallow trench isolation (STI) regions, are disposed between adjacent semiconductor fins62, which may protrude above and from between adjacent isolation regions72. Although the isolation regions72are described/illustrated as being separate from the substrate50, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although the bottom portions of the semiconductor fins62are illustrated as being separate from the substrate50, the bottom portions of the semiconductor fins62may be single, continuous materials with the substrate50. In this context, the semiconductor fins62refer to the portion extending above and from between the adjacent isolation regions72.

Gate structures140are over top surfaces of the semiconductor fins62and along top surfaces, sidewalls, and bottom surfaces of the nanostructures66. Epitaxial source/drain regions118are disposed on the semiconductor fins62at opposing sides of the gate structures140. The epitaxial source/drain regions118may be shared between various semiconductor fins62. For example, adjacent epitaxial source/drain regions118may be electrically connected, such as through coupling the epitaxial source/drain regions118with a same source/drain contact.

Insulating fins92, also referred to as hybrid fins or dielectric fins, are disposed over the isolation regions72, and between adjacent epitaxial source/drain regions118. The insulating fins92block epitaxial growth to prevent coalescing of some of the epitaxial source/drain regions118during epitaxial growth. For example, the insulating fins92may be formed at cell boundaries to separate the epitaxial source/drain regions118of adjacent cells.

FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A/B-A/B′ is along a longitudinal axis of a gate structure140and in a direction, for example, perpendicular to a direction of current flow between the epitaxial source/drain regions118of a nano-FET. Cross-section C-C′ is along a longitudinal axis of a semiconductor fin62and in a direction of, for example, a current flow between the epitaxial source/drain regions118of the nano-FET. Cross-section D-D′ is parallel to cross-section A/B-A/B′ and extends through epitaxial source/drain regions118of the nano-FETs. Cross-section E/F-E/F′ is parallel to cross-section C-C′ and is along a longitudinal axis of an insulating fin92. Subsequent figures refer to these reference cross-sections for clarity.

FIGS.2-25Fare views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.FIGS.2,3, and4are three-dimensional views.FIGS.5A,5B,6A,6B,7A,7B,8A,8B,9A,9B,10A,10B,11A,11B,12A,12B,13A,13B,14A,14B,15A,15B,16A, and16B are cross-sectional views illustrated along a similar cross-section as either of reference cross-sections A/B-A/B′ or D-D′ inFIG.1.FIGS.17A,17B,18A,18B,19A,19B,20A,20B,21A,21B,22A,22B,23A,23B,24A,24B,25A, and25B are cross-sectional views illustrated along a similar cross-section as reference cross-section A/B-A/B′ inFIG.1.FIGS.17C,18C,19C,20C,21C,22C,23C,24C, and25Care cross-sectional views illustrated along a similar cross-section as reference cross-section C-C′ inFIG.1.FIGS.17D,18D,19D,20D,21D,22D,23D,24D, and25Dare cross-sectional views illustrated along a similar cross-section as reference cross-section D-D′ inFIG.1.FIGS.16E,16F,19E,19F,25E, and25Fare cross-sectional views illustrated along a similar cross-section as reference cross-section E/F-E/F′ inFIG.1.

The substrate50has an n-type region50N and a p-type region50P. The n-type region50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs, and the p-type region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs. The n-type region50N may be physically separated (not separately illustrated) from the p-type region50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region50N and the p-type region50P. Although one n-type region50N and one p-type region50P are illustrated, any number of n-type regions50N and p-type regions50P may be provided.

The substrate50may be lightly doped with a p-type or an n-type impurity. An anti-punch-through (APT) implantation may be performed on an upper portion of the substrate50to form an APT region. During the APT implantation, impurities may be implanted in the substrate50. The impurities may have a conductivity type opposite from a conductivity type of source/drain regions that will be subsequently formed in each of the n-type region50N and the p-type region50P. The APT region may extend under the source/drain regions in the nano-FETs. The APT region may be used to reduce the leakage from the source/drain regions to the substrate50. In some embodiments, the doping concentration in the APT region is in the range of 1018cm−3to 1019cm−3.

A multi-layer stack52is formed over the substrate50. The multi-layer stack52includes alternating first semiconductor layers54and second semiconductor layers56. The first semiconductor layers54are formed of a first semiconductor material, and the second semiconductor layers56are formed of a second semiconductor material. The semiconductor materials may each be selected from the candidate semiconductor materials of the substrate50. In the illustrated embodiment, the multi-layer stack52includes three layers of each of the first semiconductor layers54and the second semiconductor layers56. It should be appreciated that the multi-layer stack52may include any number of the first semiconductor layers54and the second semiconductor layers56. For example, the multi-layer stack52may include from one to ten layers of each of the first semiconductor layers54and the second semiconductor layers56.

In the illustrated embodiment, and as will be subsequently described in greater detail, the first semiconductor layers54will be removed and the second semiconductor layers56will patterned to form channel regions for the nano-FETs in both the n-type region50N and the p-type region50P. The first semiconductor layers54are sacrificial layers (or dummy layers), which will be removed in subsequent processing to expose the top surfaces and the bottom surfaces of the second semiconductor layers56. The first semiconductor material of the first semiconductor layers54is a material that has a high etching selectivity from the etching of the second semiconductor layers56, such as silicon germanium. The second semiconductor material of the second semiconductor layers56is a material suitable for both n-type and p-type devices, such as silicon.

In another embodiment (not separately illustrated), the first semiconductor layers54will be patterned to form channel regions for nano-FETs in one region (e.g., the p-type region50P), and the second semiconductor layers56will be patterned to form channel regions for nano-FETs in another region (e.g., the n-type region50N). The first semiconductor material of the first semiconductor layers54may be a material suitable for p-type devices, such as silicon germanium (e.g., SixGe1-x, where x can be in the range of 0 to 1), pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The second semiconductor material of the second semiconductor layers56may be a material suitable for n-type devices, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first semiconductor material and the second semiconductor material may have a high etching selectivity from the etching of one another, so that the first semiconductor layers54may be removed without removing the second semiconductor layers56in the n-type region50N, and the second semiconductor layers56may be removed without removing the first semiconductor layers54in the p-type region50P.

InFIG.3, trenches60are patterned in the substrate50and the multi-layer stack52to form semiconductor fins62, nanostructures64, and nanostructures66. The semiconductor fins62are semiconductor strips patterned in the substrate50. The nanostructures64and the nanostructures66include the remaining portions of the first semiconductor layers54and the second semiconductor layers56, respectively. The trenches60may be patterned by any acceptable etching process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic.

In some embodiments, the semiconductor fins62and the nanostructures64,66each have widths in a range of 8 nm to 40 nm. In the illustrated embodiment, the semiconductor fins62and the nanostructures64,66have substantially equal widths in the n-type region50N and the p-type region50P. In another embodiment, the semiconductor fins62and the nanostructures64,66in one region (e.g., the n-type region50N) are wider or narrower than the semiconductor fins62and the nanostructures64,66in another region (e.g., the p-type region50P). Further, while each of the semiconductor fins62and the nanostructures64,66are illustrated as having a consistent width throughout, in other embodiments, the semiconductor fins62and/or the nanostructures64,66may have tapered sidewalls such that a width of each of the semiconductor fins62and/or the nanostructures64,66continuously increases in a direction towards the substrate50. In such embodiments, each of the nanostructures64,66may have a different width and be trapezoidal in shape.

InFIG.4, STI regions72are formed over the substrate50and in the trenches60between adjacent semiconductor fins62. The STI regions72are disposed around at least a portion of the semiconductor fins62such that at least a portion of the nanostructures64,66protrude from between adjacent STI regions72. In the illustrated embodiment, the top surfaces of the STI regions72are below the top surfaces of the semiconductor fins62. In some embodiments, the top surfaces of the STI regions72are above or coplanar (within process variations) with the top surfaces of the semiconductor fins62.

The STI regions72may be formed by any suitable method. For example, an insulation material can be formed over the substrate50and the nanostructures64,66, and in the trenches60between adjacent semiconductor fins62. The insulation material may be an oxide, such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof, which may be formed by a chemical vapor deposition (CVD) process, such as high density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In some embodiments, the insulation material is silicon oxide formed by FCVD. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers the nanostructures64,66. Although the STI regions72are each illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not separately illustrated) may first be formed along surfaces of the substrate50, the semiconductor fins62, and the nanostructures64,66. Thereafter, an insulation material, such as those previously described may be formed over the liner.

A removal process is then applied to the insulation material to remove excess insulation material outside of the trenches60, which excess material is over the nanostructures64,66. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. In some embodiments, the planarization process may expose the mask58or remove the mask58. After the planarization process, the top surfaces of the insulation material and the mask58or the nanostructures64,66are coplanar (within process variations). Accordingly, the top surfaces of the mask58(if present) or the nanostructures64,66are exposed through the insulation material. In the illustrated embodiment, the mask58remains on the nanostructures64,66. The insulation material is then recessed to form the STI regions72. The insulation material is recessed such that at least a portion of the nanostructures64,66protrude from between adjacent portions of the insulation material. Further, the top surfaces of the STI regions72may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof by applying an appropriate etch. The insulation material may be recessed using any acceptable etching process, such as one that is selective to the material of the insulation material (e.g., selectively etches the insulation material of the STI regions72at a faster rate than the materials of the semiconductor fins62and the nanostructures64,66). For example, an oxide removal may be performed using dilute hydrofluoric (dHF) acid as an etchant.

The process previously described is just one example of how the semiconductor fins62and the nanostructures64,66may be formed. In some embodiments, the semiconductor fins62and/or the nanostructures64,66may be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the semiconductor fins62and/or the nanostructures64,66. The epitaxial structures may include the alternating semiconductor materials previously described, such as the first semiconductor material and the second semiconductor material. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together.

Further, appropriate wells (not separately illustrated) may be formed in the nanostructures64,66, the semiconductor fins62, and/or the substrate50. The wells may have a conductivity type opposite from a conductivity type of source/drain regions that will be subsequently formed in each of the n-type region50N and the p-type region50P. In some embodiments, a p-type well is formed in the n-type region50N, and an n-type well is formed in the p-type region50P. In some embodiments, a p-type well or an n-type well is formed in both the n-type region50N and the p-type region50P.

In embodiments with different well types, different implant steps for the n-type region50N and the p-type region50P may be achieved using mask (not separately illustrated) such as a photoresist. For example, a photoresist may be formed over the semiconductor fins62, the nanostructures64,66, and the STI regions72in the n-type region50N. The photoresist is patterned to expose the p-type region50P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in the range of 1013cm−3to 1014cm−3. After the implant, the photoresist may be removed, such as by any acceptable ashing process.

Following or prior to the implanting of the p-type region50P, a mask (not separately illustrated) such as a photoresist is formed over the semiconductor fins62, the nanostructures64,66, and the STI regions72in the p-type region50P. The photoresist is patterned to expose the n-type region50N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in the range of 1013cm−3to 1014cm−3. After the implant, the photoresist may be removed, such as by any acceptable ashing process.

After the implants of the n-type region50N and the p-type region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments where epitaxial structures are epitaxially grown for the semiconductor fins62and/or the nanostructures64,66, the grown materials may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.

FIGS.5A-25Billustrate various additional steps in the manufacturing of embodiment devices.FIGS.5A-25Billustrate features in either of the n-type region50N and the p-type region50P. For example, the structures illustrated may be applicable to both the n-type region50N and the p-type region50P. Differences (if any) in the structures of the n-type region50N and the p-type region50P are described in the text accompanying each figure. Further,FIGS.5A-25Billustrate features in a dense region50D and a sparse region50S. The gates structures in the dense region50D have channel regions with short lengths, which may be desirable for some types of devices, such as devices that operate at high speeds. The gates structures in the sparse region50S have channel regions with long lengths, which may be desirable for some types of devices, such as devices that operate at high power. More generally, the channel regions of the devices in the sparse region50S are longer than the channel regions of the devices in the dense region50D. Each of the regions50D,50S can include devices from both of the regions50N,50P. In other words, the dense region50D and the sparse region50S can each include n-type devices and p-type devices.

As will be subsequently described in greater detail, insulating fins92will be formed between the semiconductor fins62.FIGS.5A,6A,7A,8A,9A,10A,11A,12A,13A,14A,15A,16A,17A,18A,19A,20A,21A,22A,23A,24A, and25Aeach illustrate two semiconductor fins62and portions of the insulating fins92and the STI regions72that are disposed between the two semiconductor fins62in the dense region50D.FIGS.5B,6B,7B,8B,9B,10B,11B,12B,13B,14B,15B,16B,17B,18B,19B,20B,21B,22B,23B,24B, and25Beach illustrate two semiconductor fins62and portions of the insulating fins92and the STI regions72that are disposed between the two semiconductor fins62in the sparse region50S.FIGS.16C,17C,18C,19C,20C,21C,22C,23C,24C, and25Cillustrate a semiconductor fin62and structures formed on it in either of the regions50D,50S.FIGS.16D,17D,18D,19D,20D,21D,22D,23D,24D, and25Ceach illustrate two semiconductor fins62and portions of the insulating fins92and the STI regions72that are disposed between the two semiconductor fins62in either of the regions50D,50S.FIGS.16E,19E, and25Eillustrate an insulating fin92and structures formed on it in the dense region50D.FIGS.16F,19F, and25Fillustrate an insulating fin92and structures formed on it in the sparse region50S.

InFIGS.5A-5B, sacrificial spacers76are formed on the sidewalls of the mask58, the semiconductor fins62and the nanostructures64,66, and further on the top surface of the STI regions72. The sacrificial spacers76may be formed by conformally forming a sacrificial material in the trenches60and patterning the sacrificial material. The sacrificial material may be a semiconductor material selected from the candidate semiconductor materials of the substrate50, which may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. For example, the sacrificial material may be silicon or silicon germanium. The sacrificial material may be patterned using an etching process, such as a dry etch, a wet etch, or a combination thereof. The etching process may be anisotropic. As a result of the etching process, the portions of the sacrificial material over the mask58and the nanostructures64,66are removed, and the STI regions72between the nanostructures64,66are partially exposed. The sacrificial spacers76include the remaining portions of the sacrificial material in the trenches60.

In subsequent process steps, a dummy gate layer94is deposited over portions of the sacrificial spacers76(see below,FIGS.14A-14B), and the dummy gate layer94is patterned to form dummy gates104(see below,FIGS.16A-16F). The dummy gates104, the underlying portions of the sacrificial spacers76, and the nanostructures64are then collectively replaced with functional gate structures. Specifically, the sacrificial spacers76are used as temporary spacers during processing to delineate boundaries of insulating fins, and the sacrificial spacers76and the nanostructures64will be subsequently removed and replaced with gate structures that are wrapped around the nanostructures66. The sacrificial spacers76are formed of a material that has a high etching selectivity from the etching of the material of the nanostructures66. For example, the sacrificial spacers76may be formed of the same semiconductor material as the nanostructures64so that the sacrificial spacers76and the nanostructures64may be removed in a single process step. Alternatively, the sacrificial spacers76may be formed of a different material from the nanostructures66.

FIGS.6A-13Billustrate a formation of insulating fins92(also referred to as hybrid fins or dielectric fins) between the sacrificial spacers76adjacent to the semiconductor fins62and nanostructures64,66. The insulating fins92may insulate and physically separate subsequently formed source/drain regions (see below,FIGS.18A-18D) from each other. The insulating fins92are formed by forming insulating layer(s)78(seeFIGS.6A-6B) for lower portions of the insulating fins92, and then forming insulating layer(s)80(seeFIGS.8A-12B) for upper portions of the insulating fins92. The insulating layer(s)78may be referred to as lower insulating layer(s) of the insulating fins92, and the insulating layer(s)80may be referred to as upper insulating layer(s) of the insulating fins92. The insulating layer(s)80are formed of one or more dielectric material(s) having a high etching selectivity from the etching of the insulating layer(s)78, so that the insulating layer(s)80may act as a hard mask to protect the insulating layer(s)78during subsequent processing.

InFIGS.6A-6B, one or more insulating layer(s)78for lower portions of insulating fins are formed in the trenches60. As will be subsequently described, the insulating layer(s)78may be formed of one or more dielectric material(s) having a high etching selectivity from the etching of the semiconductor fins62, the nanostructures64,66, and the sacrificial spacers76. The insulating layer(s)78are formed of the same dielectric material in the dense region50D and the sparse region50S. In some embodiments, the insulating layer(s)78include a liner78A and a fill material78B over the liner78A.

The liner78A is conformally formed over exposed surfaces of the mask58, the semiconductor fins62, the nanostructures64,66, the STI regions72, and the sacrificial spacers76. In some embodiments, the liner78A is formed of a nitride such as silicon nitride, silicon carbonitride, silicon oxycarbonitride, or the like, which may be formed by any acceptable deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. The liner78A may reduce oxidation of the sacrificial spacers76during the subsequent formation of the fill material78B, which may be useful for a subsequent removal of the sacrificial spacers76.

The fill material78B is conformally formed over the liner78A, and fills the remaining portions of the trenches60which are not filled by the sacrificial spacers76or the liner78A. In some embodiments, the fill material78B is formed of an oxide such as silicon oxide, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, or the like, which may be formed by any acceptable deposition process such as ALD, CVD, PVD, or the like. The fill material78B may form the bulk of the lower portions of the insulating fins to insulate subsequently formed source/drain regions (see below,FIGS.18A-18D) from each other.

InFIGS.7A-7B, upper portions of insulating layer(s)78above top surfaces of the mask58may be removed using one or more acceptable planarization and/or etching processes. The planarization process may be a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like. The etching process may be selective to the insulating layer(s)78(e.g., selectively etches the materials of the liner78A and the fill material78B at a faster rate than the materials of the sacrificial spacers76and/or the mask58). After the etching process, top surfaces of insulating layer(s)78are below top surfaces of the mask58and the sacrificial spacers76. The etching process re-forms portions of the trenches60. The trenches60S in the sparse region50S are wider than the trenches60D in the dense region50D.

FIGS.8A-12Billustrate a formation of insulating layer(s)80for upper portions of insulating fins in the trenches60. The insulating layer(s)80fill the remaining portions of the trenches60which are not filled by the insulating layer(s)78, and the insulating layer(s)80S are wider than the insulating layer(s)80D due to the different widths of the trenches60D,60S. The insulating layer(s)80(including insulating layer(s)80D and insulating layer(s)80S, seeFIGS.13A-13B) are formed of different materials in the dense region50D and the sparse region50S. In the illustrated embodiment, the insulating layer(s)80are formed of different materials by repeated deposition and conversion processes. Specifically, an insulating layer80may be formed by depositing a first dielectric material in the regions50D,50S, and then converting at least a portion of the insulating layer80S in the sparse region50S to a second dielectric material, while a portion of the insulating layer80D in the dense region50D remains the first dielectric material. The deposition and conversion processes may be repeated to build up the insulating layer(s)80D,80S in the regions50D,50S. A removal process is then applied to remove unconverted portions of the insulating layer(s)80(which are formed of the first dielectric material) from the sparse region50S and to remove converted portions of the insulating layer(s)80(which are formed of the second dielectric material) from the dense region50D. Accordingly, the insulating layer(s)80D in the dense region50D are formed of the first dielectric material and the insulating layer(s)80S in the sparse region50S are formed of the second dielectric material. Forming the insulating layer(s)80of different materials in the dense region50D and the sparse region50S allows the insulating layer(s)80D,80S in the regions50D,50S have a high etching selectivity from the etching of one another.

InFIGS.8A-8B, a first insulating layer80A is conformally formed over exposed surfaces of the mask58, the sacrificial spacers76, and the insulating layer(s)78. The first insulating layer80A is formed of a first dielectric material such as silicon carbide, silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or the like, which may be formed by any acceptable deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), conformal CVD (e.g., flowable CVD), physical vapor deposition (PVD), or the like. In some embodiments, the first insulating layer80A includes a material under a tensile strain. In some embodiments, the first insulating layer80A is formed to a thickness in the range of 0.02 nm to 4 nm.

InFIGS.9A-9B, a portion of the first insulating layer80A is converted from the first dielectric material to a second dielectric material by a conversion process82. Converting the first dielectric material to the second dielectric material includes modifying the composition, density, porosity, and/or stress of the first dielectric material. The first dielectric material is different from the second dielectric material, and in this context, the dielectric materials are different when they have different compositions, densities, porosities, and/or stresses. The resulting second dielectric material depends on the first dielectric material and the type of conversion process82, and will be subsequently described in greater detail. The insulating layer(s)78are not modified by the conversion process82.

More of the first insulating layer80A in the sparse region50S is affected by the conversion process82than the first insulating layer80A in the dense region50D, thereby allowing only portion of the first insulating layer80A to be modified by the conversion process82. Specifically, the conversion process82is a chemical process, and because the trenches60S in the sparse region50S are larger than the trenches60D in the dense region50D, the chemical process can more easily penetrate to the bottoms of the trenches60S than to the bottoms of the trenches60D, such as due to less crowding in the trenches60S. As a result, the lower portions86S of the first insulating layer80A in the sparse region50S (e.g., at the bottoms of the trenches60S) are converted to the second dielectric material, while the lower portions86D of the first insulating layer80A in the dense region50D (e.g., at the bottoms of the trenches60D) remain as the first dielectric material. Put another way, the conversion process82modifies the portions of the first insulating layer80A in the trenches60S more than it modifies the portions of the first insulating layer80A in the trenches60D. The conversion process82may also increase the surface bonding ability of the first insulating layer80A.

In some embodiments, the conversion process82includes modifying the composition of a portion of the first insulating layer80A. As such, the first dielectric material has a different composition than the second dielectric material. In some embodiments, the first insulating layer80A is initially formed of silicon carbide, silicon nitride, or silicon oxide, and the conversion process82modifies the composition of the converted portion of the first insulating layer80A so that it is silicon carbonitride, silicon oxycarbide, or silicon oxycarbonitride, respectively. An example of a composition modification process is a radical treatment, in which the converted portion of the first insulating layer80A is exposed to nitrogen free radicals, oxygen free radicals, or a combination thereof. The radical treatment may be performed in a processing chamber. A gas source is dispensed in the processing chamber. The gas source includes one or more radical precursor gas(es) and a carrier gas. Acceptable radical precursor gases for nitrogen free radicals include nitrogen gas (N2), ammonia (NH3), methane (CH4), combinations thereof, or the like. Acceptable radical precursor gases for oxygen free radicals include carbon dioxide (CO2), oxygen gas (O2), combinations thereof, or the like. Acceptable carrier gases include inert gases such as helium (He), xenon (Xe), neon (Ne), krypton (Kr), Radon (Rn), combinations thereof, or the like. A plasma is generated from the gas source. The plasma may be generated by a plasma generator such as a transformer-coupled plasma generator, inductively coupled plasma system, magnetically enhanced reactive ion etching system, electron cyclotron resonance system, remote plasma generator, or the like. The plasma generator generates radio frequency power that produces a plasma from the gas source by applying a voltage above the striking voltage to electrodes in the processing chamber containing the gas source. In some embodiments, the plasma is generated at a pressure in the range of 0.05 Torr to 10.0 Torr (such as in the range of 1 Torr to 2 Torr), at a temperature in the range of 25° C. to 400° C. (such as in the range of 50° C. to 200° C.), and for a duration in the range of 1 second to 10 minutes or in the range of 0.5 seconds to 3 seconds. When the plasma is generated, free radicals (e.g., nitrogen and/or oxygen free radicals) and corresponding ions are generated. The free radicals readily bond with open bonds of silicon atoms of the converted portion of the first insulating layer80A, thereby nitrating and/or oxidizing the converted portion of the first insulating layer80A, such that the second dielectric material is composed of more nitrogen or oxygen than the first dielectric material.

In some embodiments, the conversion process82includes modifying the density of a portion of the first insulating layer80A. As such, the first dielectric material has a different density than the second dielectric material. In some embodiments, the first insulating layer80A is initially formed of low-density silicon carbide, and the conversion process82increases the density of the converted portion of the first insulating layer80A so that it is high-density silicon carbide. An example of a density modification process is an argon radical treatment, in which the converted portion of the first insulating layer80A is exposed to argon free radicals. The argon radical treatment may be performed in a processing chamber. A gas source is dispensed in the processing chamber. The gas source includes a radical precursor gas and a carrier gas. Acceptable radical precursor gases for argon free radicals include Ar or the like. Acceptable carrier gases include He, N2, combinations thereof, or the like. A plasma is generated from the gas source. The plasma may be generated by a plasma generator such as a transformer-coupled plasma generator, inductively coupled plasma system, magnetically enhanced reactive ion etching system, electron cyclotron resonance system, remote plasma generator, or the like. The plasma generator generates radio frequency power that produces a plasma from the gas source by applying a voltage above the striking voltage to electrodes in the processing chamber containing the gas source. When the plasma is generated, free radicals (e.g., argon free radicals) and corresponding ions are generated. The argon free radicals bombard the converted portion of the first insulating layer80A, thereby densifying the converted portion of the first insulating layer80A, such that the second dielectric material is denser than the first dielectric material. In some embodiments, the ratio of the density of the second dielectric material to the density of the first dielectric material is about 2.28.FIG.27illustrates a reaction when converting a low-density silicon carbide to a high-density silicon carbide. In the reaction, the low-density silicon carbide contains C—H bonds or functional groups, and the conversion process82removes hydrogen terminations to cause Si—C—Si crosslinking and form the high-density silicon carbide.

In some embodiments, the conversion process82includes modifying the porosity of a portion of the first insulating layer80A. As such, the first dielectric material has a different porosity than the second dielectric material. In some embodiments, the first insulating layer80A is initially formed of impermeable silicon carbide, silicon nitride, or silicon oxycarbide, and the conversion process82increase the porosity of the converted portion of the first insulating layer80A so that it is porous silicon carbide, silicon oxide, silicon oxynitride, or silicon oxycarbonitride. An example of a porosity modification process is a anneal process, in which the converted portion of the first insulating layer80A is annealed while it is exposed to an ambient containing nitrogen and/or oxygen. In some embodiments the anneal process is a dry anneal performed at a temperature in the range of 300° C. to 900° C. using 02 or N2as the process gas, although other process gases may be used. The anneal process drives carbon out of the converted portion of the first insulating layer80A and/or drives oxygen or nitrogen into the converted portion of the first insulating layer80A, thereby increasing the porosity of the converted portion of the first insulating layer80A, such that the second dielectric material is more porous than the first dielectric material.

In some embodiments, the conversion process82includes modifying the stress of a portion of the first insulating layer80A. As such, the first dielectric material is under a different stress than the second dielectric material. In some embodiments, the first insulating layer80A is initially formed of silicon nitride or silicon carbonitride under a tensile strain, and the conversion process82decreases the stress of the converted portion of the first insulating layer80A so that it is silicon nitride, silicon oxynitride, or silicon oxycarbonitride under a neutral or compressive strain. An example of a stress modification process is a radical treatment, in which the converted portion of the first insulating layer80A is exposed to argon free radicals or oxygen free radicals. The radical treatment may be performed in a processing chamber. A gas source is dispensed in the processing chamber. The gas source includes a radical precursor gas and a carrier gas. Acceptable radical precursor gases for argon free radicals include argon gas (Ar) or the like. Acceptable radical precursor gases for oxygen free radicals include oxygen gas (O2) or the like. Acceptable carrier gases include inert gases such as helium (He), xenon (Xe), neon (Ne), krypton (Kr), Radon (Rn), combinations thereof, or the like. A plasma is generated from the gas source. The plasma may be generated by a plasma generator such as a transformer-coupled plasma generator, inductively coupled plasma system, magnetically enhanced reactive ion etching system, electron cyclotron resonance system, remote plasma generator, or the like. The plasma generator generates radio frequency power that produces a plasma from the gas source by applying a voltage above the striking voltage to electrodes in the processing chamber containing the gas source. When the plasma is generated, free radicals (e.g., argon or oxygen free radicals) and corresponding ions are generated. The free radicals bombard the converted portion of the first insulating layer80A, thereby modifying (e.g., decreasing) the stress of the converted portion of the first insulating layer80A, such that the first dielectric material is under a tensile strain and the second dielectric material is under a compressive strain. In some embodiments, the first dielectric material has a stress in the range of 0.8 GPa to 1.4 GPa, and the second dielectric material has a stress in the range of −0.2 GPa to 0.2 GPa.

Although each type of conversion process has been separately described, it should be appreciated that a given process may include aspects of several types of conversion processes. For example, a conversion process may modify both the composition and porosity of a portion of the first insulating layer80A. Similarly, a conversion process may modify both the composition and density of a portion of the first insulating layer80A.

InFIGS.10A-11B, the steps described forFIGS.8A-9Bare repeated. For example, a second insulating layer80B is conformally formed over exposed surfaces of the first insulating layer80A (seeFIGS.10A-10B) and a portion of the second insulating layer80B is converted from the first dielectric material to a second dielectric material by performing a conversion process84(seeFIGS.11A-11B). The second insulating layer80B is formed of the first dielectric material which the first insulating layer80A was initially formed of. The second insulating layer80B maybe be formed to the same thickness as the first insulating layer80A, or may be formed to a different thickness. In some embodiments, the second insulating layer80B is formed to a thickness in the range of 0.02 nm to 4 nm. The conversion process84may be the same as the conversion process82, or may be different than the conversion process82.

InFIGS.12A-12B, the steps described forFIGS.8A-9Bare again repeated a desired quantity of times until a desired quantity of the insulating layer(s)80have been formed. After formation is complete, the lower portions86S of the insulating layer(s)80S in the sparse region50S (e.g., the portions between the sacrificial spacers76) are converted to the second dielectric material, while the lower portions86D of the insulating layer(s)80in the dense region50D (e.g., the portions between the sacrificial spacers76) remain as the first dielectric material. During formation of the insulating layer(s)80, they may seam together such that vertical seams88are formed. In some areas, such as in the sparse region50S, the portions of the insulating layer(s)80proximate the vertical seams88are not converted to the second dielectric material and remain as the first dielectric material. In some embodiments, the process for forming the insulating layer(s)80(including the formation of the first dielectric material and the conversion to the second dielectric material) may be performed in the same processing tool (e.g., deposition chamber), without breaking a vacuum in the processing tool between each deposition and conversion step.

InFIGS.13A-13B, a removal process is applied to the insulating layer(s)80to remove excess portions of the insulating layer(s)80over the sacrificial spacers76, the nanostructures64,66, and the mask58. A planarization process such as a chemical mechanical polish (CMP), an etching process, combinations thereof, or the like may be utilized. After the planarization process, top surfaces of the mask58and the insulating layer(s)80are coplanar (within process variations).

As a result, insulating fins92are formed between and contacting the sacrificial spacers76. The insulating fins92include the insulating layer(s)78and the insulating layer(s)80. The insulating layer(s)78form the lower portions of the insulating fins92, and the insulating layer(s)80form the upper portions of the insulating fins92. The sacrificial spacers76space the insulating fins92apart from the nanostructures64,66, and a size of the insulating fins92may be adjusted by adjusting a thickness of the sacrificial spacers76.

In this embodiment, the removal process is performed until the upper portions of the insulating layer(s)80are removed, such that only the lower portions86D,86S of the insulating layer(s)80remain. As a result, all of the first dielectric material in the sparse region50S is removed and all of the second dielectric material in the dense region50D is removed. Accordingly, the insulating fins92D in the dense region50D include the insulating layer(s)80D which are formed of the first dielectric material, and the insulating fins92S in the sparse region50S include the insulating layer(s)80S which are formed of the second dielectric material. In another embodiment (subsequently described forFIGS.25A-26F), some of the first dielectric material may remain in the sparse region50S and/or some of the second dielectric material may remain in the dense region50D after the removal process. In either case, it should be appreciate that a majority of the portions of the insulating layer(s)80D in the dense region50D include the first dielectric material, and that a majority of the portions of the insulating layer(s)80S in the sparse region50S include the second dielectric material.

InFIGS.14A-14B, the mask58is removed. The mask58may be removed using an etching process, for example. The etching process may be a wet etch that selective removes the mask58without significantly etching the insulating fins92. The etching process may be anisotropic. Further, the etching process (or a separate, selective etching process) may also be applied to reduce a height of the sacrificial spacers76to a similar level (e.g., same within processing variations) as the nanostructures64,66. After the etching process(es), a top surface of the nanostructures64,66and a top surface of the sacrificial spacers76may be exposed and may be lower than a top surface of the insulating fins92.

InFIG.15A-15B, a dummy gate layer94is formed on the insulating fins92, the sacrificial spacers76, and the nanostructures64,66. Because the nanostructures64,66and the sacrificial spacers76extend lower than the insulating fins92, the dummy gate layer94may be disposed along exposed sidewalls of the insulating fins92. The dummy gate layer94may be deposited and then planarized, such as by a CMP. The dummy gate layer94may be formed of a conductive or non-conductive material, such as amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), a metal, a metallic nitride, a metallic silicide, a metallic oxide, or the like, which may be deposited by physical vapor deposition (PVD), CVD, or the like. The dummy gate layer94may also be formed of a semiconductor material (such as one selected from the candidate semiconductor materials of the substrate50), which may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. The dummy gate layer94may be formed of material(s) that have a high etching selectivity from the etching of insulation materials, e.g., the insulating fins92. A mask layer96may be deposited over the dummy gate layer94. The mask layer96may be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer94and a single mask layer96are formed across the n-type region50N and the p-type region50P.

InFIGS.16A-16F, the mask layer96is patterned using acceptable photolithography and etching techniques to form masks106. The pattern of the masks106is then transferred to the dummy gate layer94by any acceptable etching technique to form dummy gates104. The dummy gates104cover the top surfaces of the nanostructures64,66that will be exposed in subsequent processing to form channel regions. The pattern of the masks106may be used to physically separate adjacent dummy gates104. The dummy gates104may also have lengthwise directions substantially perpendicular (within process variations) to the lengthwise directions of the semiconductor fins62. The masks106can optionally be removed after patterning, such as by any acceptable etching technique.

The dummy gates104, the sacrificial spacers76, and the nanostructures64collectively extend along the portions of the nanostructures66that will be patterned to form channel regions68. Subsequently formed gate structures will replace the dummy gates104, the sacrificial spacers76, and the nanostructures64. Forming the dummy gates104over the sacrificial spacers76allows the subsequently formed gate structures to have a greater height.

As noted above, the dummy gates104may be formed of a semiconductor material. In such embodiments, the nanostructures64, the sacrificial spacers76, and the dummy gates104are each formed of semiconductor materials. In some embodiments, the nanostructures64, the sacrificial spacers76, and the dummy gates104are formed of a same semiconductor material (e.g., silicon germanium), so that during a replacement gate process, the nanostructures64, the sacrificial spacers76, and the dummy gates104may be removed together in a same etching step. In some embodiments, the nanostructures64and the sacrificial spacers76are formed of a first semiconductor material (e.g., silicon germanium) and the dummy gates104are formed of a second semiconductor material (e.g., silicon), so that during a replacement gate process, the dummy gates104may be removed in a first etching step, and the nanostructures64and the sacrificial spacers76may be removed together in a second etching step. In some embodiments, the nanostructures64are formed of a first semiconductor material (e.g., silicon germanium) and the sacrificial spacers76and the dummy gates104are formed of a second semiconductor material (e.g., silicon), so that during a replacement gate process, the sacrificial spacers76and the dummy gates104may be removed together in a first etching step, and the nanostructures64may be removed in a second etching step.

Referring specifically toFIGS.16E-16F, the pattern of the masks106is also transferred to the insulating layer(s)80of the insulating fins92by any acceptable etching technique to form recesses110in portions of the insulating fins92. The recesses110are in the portions of the insulating fins92which will disposed between subsequently formed source/drain regions (see below,FIGS.18A-18D). The recesses110will be subsequently filled with an inter-layer dielectric (ILD) (see below,FIGS.19A-19D). The subsequently formed ILD has a lower relative permittivity than the insulating layer(s)80, and replacing the portions of the insulating layer(s)80between the subsequently formed source/drain regions with a material that provides better electrical isolation may reduce leakage and improve the performance of the resulting nano-FETs.

The insulating layer(s)80D in the dense region50D and the insulating layer(s)80S in the sparse region50S are patterned by different etching processes when forming the recesses110. Patterning the insulating layer(s)80in the dense region50D and the sparse region50S by different etching processes advantageously avoids the use of a single etching process to pattern the insulating layer(s)80in both the dense region50D and the sparse region50S. Because the features in the dense region50D are denser than the features in the sparse region50S, pattern loading would occur if a single etching process were used to pattern the insulating layer(s)80in both the dense region50D and the sparse region50S, which may result in over-etching of the insulating layer(s)80S in the sparse region50S and/or under-etching of the insulating layer(s)80D in the dense region50D. Avoiding under-etching and/or over-etching of the insulating layer(s)80increase manufacturing yield of the resulting nano-FETs.

As described above, the insulating layer(s)80of the insulating fins92are formed of different materials in the dense region50D and the sparse region50S. Specifically, the insulating layer(s)80D,80S have a high etching selectivity from the etching of one another. As a result, the insulating layer(s)80D,80S in a respective region50D,50S may be patterned without using a mask (such as a photoresist) to cover the other respective region50D,50S. Avoiding the use of a mask when patterning the insulating layer(s)80may reduce manufacturing costs. The insulating layer(s)80D,80S in a respective region50D,50S are thus exposed to an etching process used to pattern the recesses110in the other respective region50D,50S. For example, the recesses110D in the insulating fins92D may be patterned by an acceptable etching process, such as one that is selective to the insulating layer(s)80D (e.g., selectively etches the material(s) of the insulating layer(s)80D at a faster rate than the material(s) of the insulating layer(s)80S). Similarly, the recesses1105in the insulating fins92S may be patterned by an acceptable etching process, such as one that is selective to the insulating layer(s)80S (e.g., selectively etches the material(s) of the insulating layer(s)80S at a faster rate than the material(s) of the insulating layer(s)80S). The etching processes for patterning the recesses110D,1105have different etching parameters. For example, when the first dielectric material of the insulating layer(s)80D has a different composition than the second dielectric material of the insulating layer(s)80S, the etching processes may utilize different etchants. In some embodiments, the recesses110D are patterned by a dry etch performed using a first mixture of argon (Ar), methane (CH4), a fluorine-based etchant such as hydrogen fluoride (HF), and (optionally) oxygen (O2) gases as an etchant; the recesses1105are patterned by a dry etch performed using a second mixture of those same gases as an etchant; and the ratio of the gases in the first mixture is different from the ratio of the gases in the second mixture. The recesses1105in the sparse region50S are wider than the recesses110D in the dense region50D.

Gate spacers108are formed over the nanostructures64,66, and on exposed sidewalls of the masks106(if present) and the dummy gates104. The gate spacers108may be formed by conformally depositing one or more dielectric material(s) on the dummy gates104and subsequently etching the dielectric material(s). Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by a conformal deposition process such as CVD, ALD, or the like. Other dielectric materials formed by any acceptable process may be used. Any acceptable etching process, such as a dry etch, a wet etch, the like, or a combination thereof, may be performed to pattern the dielectric material(s). The etching may be anisotropic. The dielectric material(s), when etched, have portions left on the sidewalls of the dummy gates104(thus forming the gate spacers108). After etching, the gate spacers108can have curved sidewalls or can have straight sidewalls.

Further, implants may be performed to form lightly doped source/drain (LDD) regions (not separately illustrated). In the embodiments with different device types, similar to the implants for the wells previously described, a mask (not separately illustrated) such as a photoresist may be formed over the n-type region50N, while exposing the p-type region50P, and appropriate type (e.g., p-type) impurities may be implanted into the semiconductor fins62and/or the nanostructures64,66exposed in the p-type region50P. The mask may then be removed. Subsequently, a mask (not separately illustrated) such as a photoresist may be formed over the p-type region50P while exposing the n-type region50N, and appropriate type impurities (e.g., n-type) may be implanted into the semiconductor fins62and/or the nanostructures64,66exposed in the n-type region50N. The mask may then be removed. The n-type impurities may be any of the n-type impurities previously described, and the p-type impurities may be any of the p-type impurities previously described. During the implanting, the channel regions68remain covered by the dummy gates104, so that the channel regions68remain substantially free of the impurity implanted to form the LDD regions. The LDD regions may have a concentration of impurities in the range of 1015cm−3to 1019cm−3. An anneal may be used to repair implant damage and to activate the implanted impurities.

It is noted that the previous disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized, additional spacers may be formed and removed, and/or the like. Furthermore, the n-type devices and the p-type devices may be formed using different structures and steps.

InFIGS.17A-17D, source/drain recesses112are formed in the nanostructures64,66and the sacrificial spacers76. In the illustrated embodiment, the source/drain recesses112extend through the nanostructures64,66and the sacrificial spacers76into the semiconductor fins62. The source/drain recesses112may also extend into the substrate50. In various embodiments, the source/drain recesses112may extend to a top surface of the substrate50without etching the substrate50; the semiconductor fins62may be etched such that bottom surfaces of the source/drain recesses112are disposed below the top surfaces of the STI regions72; or the like. The source/drain recesses112may be formed by etching the nanostructures64,66and the sacrificial spacers76using an anisotropic etching process, such as a RIE, a NBE, or the like. The gate spacers108and the dummy gates104collectively mask portions of the semiconductor fins62and/or the nanostructures64,66during the etching processes used to form the source/drain recesses112. A single etching process may be used to etch each of the nanostructures64,66and the sacrificial spacers76, or multiple etching processes may be used to etch the nanostructures64,66and the sacrificial spacers76. Timed etching processes may be used to stop the etching of the source/drain recesses112after the source/drain recesses112reach a desired depth.

Optionally, inner spacers114are formed on the sidewalls of the nanostructures64, e.g., those sidewalls exposed by the source/drain recesses112. As will be subsequently described in greater detail, source/drain regions will be subsequently formed in the source/drain recesses112, and the nanostructures64will be subsequently replaced with corresponding gate structures. The inner spacers114act as isolation features between the subsequently formed source/drain regions and the subsequently formed gate structures. Further, the inner spacers114may be used to substantially prevent damage to the subsequently formed source/drain regions by subsequent etching processes, such as etching processes used to subsequently remove the nanostructures64.

As an example to form the inner spacers114, the source/drain recesses112can be laterally expanded. Specifically, portions of the sidewalls of the nanostructures64exposed by the source/drain recesses112may be recessed. Although sidewalls of the nanostructures64are illustrated as being straight, the sidewalls may be concave or convex. The sidewalls may be recessed by any acceptable etching process, such as one that is selective to the nanostructures64(e.g., selectively etches the materials of the nanostructures64at a faster rate than the material of the nanostructures66). The etching may be isotropic. For example, when the nanostructures66are formed of silicon and the nanostructures64are formed of silicon germanium, the etching process may be a wet etch performed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like as an etchant. In another embodiment, the etching process may be a dry etch performed using a fluorine-based gas such as hydrogen fluoride (HF) gas as an etchant. In some embodiments, the same etching process may be continually performed to both form the source/drain recesses112and recess the sidewalls of the nanostructures64. The inner spacers114are then formed on the recessed sidewalls of the nanostructures64. The inner spacers114can be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material may be silicon nitride or silicon oxynitride, although any suitable material, such as a low-k dielectric material, may be utilized. The insulating material may be deposited by a conformal deposition process, such as ALD, CVD, or the like. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch such as a RIE, a NBE, or the like. Although outer sidewalls of the inner spacers114are illustrated as being flush with respect to the sidewalls of the gate spacers108, the outer sidewalls of the inner spacers114may extend beyond or be recessed from the sidewalls of the gate spacers108. In other words, the inner spacers114may partially fill, completely fill, or overfill the sidewall recesses. Moreover, although the sidewalls of the inner spacers114are illustrated as being straight, the sidewalls of the inner spacers114may be concave or convex.

InFIGS.18A-18D, epitaxial source/drain regions118are formed in the source/drain recesses112. The epitaxial source/drain regions118are formed in the source/drain recesses112such that each dummy gate104(and corresponding channel region68) is disposed between respective adjacent pairs of the epitaxial source/drain regions118. In some embodiments, the gate spacers108and the inner spacers114are used to separate the epitaxial source/drain regions118from, respectively, the dummy gates104and the nanostructures64by an appropriate lateral distance so that the epitaxial source/drain regions118do not short out with subsequently formed gates of the resulting nano-FETs. A material of the epitaxial source/drain regions118may be selected to exert stress in the respective channel regions68, thereby improving performance.

The epitaxial source/drain regions118in the n-type region50N may be formed by masking the p-type region50P. Then, the epitaxial source/drain regions118in the n-type region50N are epitaxially grown in the source/drain recesses112in the n-type region50N. The epitaxial source/drain regions118may include any acceptable material appropriate for n-type devices. For example, if the nanostructures66are silicon, the epitaxial source/drain regions118in the n-type region50N may include materials exerting a tensile strain on the channel regions68, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon arsenide, silicon phosphide, or the like. The epitaxial source/drain regions118in the n-type region50N may be referred to as “n-type source/drain regions.” The epitaxial source/drain regions118in the n-type region50N may have surfaces raised from respective surfaces of the semiconductor fins62and the nanostructures64,66, and may have facets.

The epitaxial source/drain regions118in the p-type region50P may be formed by masking the n-type region50N. Then, the epitaxial source/drain regions118in the p-type region50P are epitaxially grown in the source/drain recesses112in the p-type region50P. The epitaxial source/drain regions118may include any acceptable material appropriate for p-type devices. For example, if the nanostructures66are silicon, the epitaxial source/drain regions118in the p-type region50P may include materials exerting a compressive strain on the channel regions68, such as silicon germanium, boron doped silicon germanium, silicon germanium phosphide, germanium, germanium tin, or the like. The epitaxial source/drain regions118in the p-type region50P may be referred to as “p-type source/drain regions.” The epitaxial source/drain regions118in the p-type region50P may have surfaces raised from respective surfaces of the semiconductor fins62and the nanostructures64,66, and may have facets.

The epitaxial source/drain regions118, the nanostructures64,66, and/or the semiconductor fins62may be implanted with impurities to form source/drain regions, similar to the process previously described for forming LDD regions, followed by an anneal. The epitaxial source/drain regions118may have an impurity concentration in the range of 1019cm−3to 1021cm−3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously described. In some embodiments, the epitaxial source/drain regions118may be in situ doped during growth.

The epitaxial source/drain regions118may include one or more semiconductor material layers. For example, the epitaxial source/drain regions118may each include a liner layer118A, a main layer118B, and a finishing layer118C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source/drain regions118. Each of the liner layer118A, the main layer118B, and the finishing layer118C may be formed of different semiconductor materials and may be doped to different impurity concentrations. In some embodiments, the liner layer118A may have a lesser concentration of impurities than the main layer118B, and the finishing layer118C may have a greater concentration of impurities than the liner layer118A and a lesser concentration of impurities than the main layer118B. In embodiments in which the epitaxial source/drain regions include three semiconductor material layers, the liner layers118A may be grown in the source/drain recesses112, the main layers118B may be grown on the liner layers118A, and the finishing layers118C may be grown on the main layers118B.

As a result of the epitaxy processes used to form the epitaxial source/drain regions118, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the semiconductor fins62and the nanostructures64,66. However, the insulating fins92(where present) block the lateral epitaxial growth. Therefore, adjacent epitaxial source/drain regions118remain separated after the epitaxy process is completed as illustrated byFIG.18D. The epitaxial source/drain regions118contact the sidewalls of the insulating fins92. In the illustrated embodiment, the epitaxial source/drain regions118are grown so that the upper surfaces of the epitaxial source/drain regions118are disposed below the top surfaces of the insulating fins92. In various embodiments, the upper surfaces of the epitaxial source/drain regions118are disposed above the top surfaces of the insulating fins92; the upper surfaces of the epitaxial source/drain regions118have portions disposed above and below the top surfaces of the insulating fins92; or the like.

InFIGS.19A-19F, a first ILD124is deposited over the epitaxial source/drain regions118, the gate spacers108, the masks106(if present) or the dummy gates104. The first ILD124may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, or the like. Acceptable dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other dielectric materials formed by any acceptable process may be used.

In some embodiments, a contact etch stop layer (CESL)122is formed between the first ILD124and the epitaxial source/drain regions118, the gate spacers108, and the masks106(if present) or the dummy gates104. The CESL122may be formed of a dielectric material having a high etching selectivity from the etching of the first ILD124, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which may be formed by any suitable method, such as CVD, ALD, or the like.

Referring specifically toFIGS.19E-19F, the CESL122and the first ILD124are formed in the recesses110(seeFIGS.16E-16F and18D). As such, the CESL122and the first ILD124extend into a portion of the insulating fins92(e.g., through the insulating layer(s)80of the insulating fins92. The insulating fins92and portions of the CESL122and the first ILD124thus collectively separate adjacent epitaxial source/drain regions118(see also,FIG.19D) from each other. The dielectric materials of the CESL122and the first ILD124provide better electrical isolation than the material(s) of the insulating layer(s)80they replaced. As such, leakage between adjacent epitaxial source/drain regions118may be reduced, thereby improving the performance of the resulting nano-FETs.

InFIGS.20A-20D, a removal process is performed to level the top surfaces of the first ILD124with the top surfaces of the masks106(if present) or the dummy gates104. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process may also remove the masks106on the dummy gates104, and portions of the gate spacers108along sidewalls of the masks106. After the planarization process, the top surfaces of the gate spacers108, the first ILD124, the CESL122, and the masks106(if present) or the dummy gates104are coplanar (within process variations). Accordingly, the top surfaces of the masks106(if present) or the dummy gates104are exposed through the first ILD124. In the illustrated embodiment, the masks106remain, and the planarization process levels the top surfaces of the first ILD124with the top surfaces of the masks106.

InFIGS.21A-21D, the masks106(if present) and the dummy gates104are removed in an etching process, so that recesses126are formed. In some embodiments, the dummy gates104are removed by an anisotropic etching process. For example, the etching process may include a dry etching performed using reaction gas(es) that selectively etch the dummy gates104at a faster rate than the first ILD124or the gate spacers108. Each recess126exposes and/or overlies portions of the channel regions68. Portions of the nanostructures66which act as the channel regions68are disposed between adjacent pairs of the epitaxial source/drain regions118.

The remaining portions of the sacrificial spacers76are then removed to expand the recesses126, such that openings128are formed in regions between semiconductor fins62and the insulating fins92. The remaining portions of the nanostructures64are also removed to expand the recesses126, such that openings130are formed in regions between the nanostructures66. The remaining portions of the nanostructures64and the sacrificial spacers76can be removed by any acceptable etching process that selectively etches the material(s) of the nanostructures64and the sacrificial spacers76at a faster rate than the material of the nanostructures66. The etching may be isotropic. For example, when the nanostructures64and the sacrificial spacers76are formed of silicon germanium and the nanostructures66are formed of silicon, the etching process may be a wet etch performed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like as an etchant. In some embodiments, a trim process (not separately illustrated) is performed to decrease the thicknesses of the exposed portions of the nanostructures66.

InFIGS.22A-22D, a gate dielectric layer134is formed in the recesses126. A gate electrode layer136is formed on the gate dielectric layer134. The gate dielectric layer134and the gate electrode layer136are layers for replacement gates, and each wrap around all (e.g., four) sides of the nanostructures66. Thus, the gate dielectric layer134and the gate electrode layer136are formed in the openings128,130(seeFIGS.21A-21C).

The gate dielectric layer134is disposed on the sidewalls and/or the top surfaces of the semiconductor fins62; on the top surfaces, the sidewalls, and the bottom surfaces of the nanostructures66; on the sidewalls of the inner spacers114adjacent the epitaxial source/drain regions118and the gate spacers108on top surfaces of the top inner spacers114; and on the top surfaces and the sidewalls of the insulating fins92. The gate dielectric layer134may also be formed on the top surfaces of the first ILD124and the gate spacers108. The gate dielectric layer134may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, combinations thereof, multi-layers thereof, or the like. The gate dielectric layer134may include a high-k dielectric material (e.g., a dielectric material having a k-value greater than about 7.0), such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although a single-layered gate dielectric layer134is illustrated inFIGS.22A-22D, the gate dielectric layer134may include any number of interfacial layers and any number of main layers.

The gate electrode layer136may include a metal-containing material such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multi-layers thereof, or the like. Although a single-layered gate electrode layer136is illustrated inFIGS.22A-22D, the gate electrode layer136may include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and a fill material.

The formation of the gate dielectric layers134in the n-type region50N and the p-type region50P may occur simultaneously such that the gate dielectric layers134in each region are formed of the same materials, and the formation of the gate electrode layers136may occur simultaneously such that the gate electrode layers136in each region are formed of the same materials. In some embodiments, the gate dielectric layers134in each region may be formed by distinct processes, such that the gate dielectric layers134may be different materials and/or have a different number of layers, and/or the gate electrode layers136in each region may be formed by distinct processes, such that the gate electrode layers136may be different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.

InFIGS.23A-23D, a removal process is performed to remove the excess portions of the materials of the gate dielectric layer134and the gate electrode layer136, which excess portions are over the top surfaces of the first ILD124and the gate spacers108, thereby forming gate structures140. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The gate dielectric layer134, when planarized, has portions left in the recesses126(thus forming gate dielectrics for the gate structures140). The gate electrode layer136, when planarized, has portions left in the recesses126(thus forming gate electrodes for the gate structures140). The top surfaces of the gate spacers108; the CESL122; the first ILD124; and the gate structures140are coplanar (within process variations). The gate structures140are replacement gates of the resulting nano-FETs, and may be referred to as “metal gates.” The gate structures140each extend along top surfaces, sidewalls, and bottom surfaces of a channel region68of the nanostructures66. Additionally, the gate structures140each extend along top surfaces of the insulating layer(s)80for the insulating fins92, and along sidewalls of the insulating layer(s)78,80for the insulating fins92. The gate structures140fill the area previously occupied by the nanostructures64, the sacrificial spacers76, and the dummy gates104.

In some embodiments, isolation regions142are formed extending through some of the gate structures140. An isolation region142is formed to divide (or “cut”) a gate structure140into multiple gate structures140. The isolation region142may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which may be formed by a deposition process such as CVD, ALD, or the like. As an example to form the isolation regions142, openings can be patterned in the desired gate structures140. Any acceptable etching process, such as a dry etch, a wet etch, the like, or a combination thereof, may be performed to pattern the openings. The etching may be anisotropic. One or more layers of dielectric material may be deposited in the openings. A removal process may be performed to remove the excess portions of the dielectric material, which excess portions are over the top surfaces of the gate structures140, thereby forming the isolation regions142.

InFIGS.24A-24D, a second ILD146is deposited over the gate spacers108, the CESL122, the first ILD124, and the gate structures140. In some embodiments, the second ILD146is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD146is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, which may be deposited by any suitable method, such as CVD, PECVD, or the like.

In some embodiments, an etch stop layer (ESL)144is formed between the second ILD146and the gate spacers108, the CESL122, the first ILD124, and the gate structures140. The ESL144may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a high etching selectivity from the etching of the second ILD146.

InFIGS.25A-25F, gate contacts152and source/drain contacts154are formed to contact, respectively, the gate structures140and the epitaxial source/drain regions118. The gate contacts152are physically and electrically coupled to the gate structures140. The source/drain contacts154are physically and electrically coupled to the epitaxial source/drain regions118.

As an example to form the gate contacts152and the source/drain contacts154, openings for the gate contacts152are formed through the second ILD146and the ESL144, and openings for the source/drain contacts154are formed through the second ILD146, the ESL144, the first ILD124, and the CESL122. The openings may be formed using acceptable photolithography and etching techniques. A liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD146. The remaining liner and conductive material form the gate contacts152and the source/drain contacts154in the openings. The gate contacts152and the source/drain contacts154may be formed in distinct processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the gate contacts152and the source/drain contacts154may be formed in different cross-sections, which may avoid shorting of the contacts.

Optionally, metal-semiconductor alloy regions156are formed at the interfaces between the epitaxial source/drain regions118and the source/drain contacts154. The metal-semiconductor alloy regions156can be silicide regions formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed of a metal germanide (e.g. titanium germanide, cobalt germanide, nickel germanide, etc.), silicon-germanide regions formed of both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions156can be formed before the material(s) of the source/drain contacts154by depositing a metal in the openings for the source/drain contacts154and then performing a thermal anneal process. The metal can be any metal capable of reacting with the semiconductor materials (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source/drain regions118to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals or their alloys. The metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. After the thermal anneal process, a cleaning process, such as a wet clean, may be performed to remove any residual metal from the openings for the source/drain contacts154, such as from surfaces of the metal-semiconductor alloy regions156. The material(s) of the source/drain contacts154can then be formed on the metal-semiconductor alloy regions156.

Embodiments may achieve advantages. Depositing the insulating layer(s)80for the insulating fins92as a first dielectric material in the regions50D,50S and then converting a portion of the insulating layer(s)80in the sparse region50S to a second dielectric material allows the resulting insulating fins92D,92S to have upper portions formed of different dielectric materials. As such, the upper portions of the insulating fins92D,92S have a high etching selectivity from the etching of one another, thereby allowing the insulating fins92D,92S in a respective region50D,50S to be etched without using a mask (such as a photoresist) to cover the other respective region50D,50S. Separate etching processes may thus be used to pattern the insulating fins92D,92S, thereby avoiding pattern loading effects, without incurring the costs of using a mask. Replacing a portion of the insulating layer(s)80of the insulating fins92with material(s) that provide better electrical isolation between adjacent epitaxial source/drain regions118can reduce leakage, thereby improving the performance of the resulting nano-FETs.

FIGS.26A-26Fare views of nano-FETs, in accordance with some other embodiments. In this embodiment, some of the first dielectric material remains in the sparse region50S after the removal process described forFIGS.13A-13B. Although some of the insulating layer(s)80S of the insulating fins92S contain some of the first dielectric material, a majority of the insulating layer(s)80S of the insulating fins92S contain the second dielectric material. Therefore, a desired etching selectivity between the insulating layer(s)80D,80S may still be achieved.

In an embodiment, a device includes: first source/drain regions; a first insulating fin between the first source/drain regions, the first insulating fin including a first lower insulating layer and a first upper insulating layer; second source/drain regions; and a second insulating fin between the second source/drain regions, the second insulating fin including a second lower insulating layer and a second upper insulating layer, the first lower insulating layer and the second lower insulating layer including the same dielectric material, the first upper insulating layer and the second upper insulating layer including different dielectric materials. In some embodiments of the device, the first upper insulating layer includes a first dielectric material, the second upper insulating layer includes a second dielectric material, and the first dielectric material has a different composition than the second dielectric material. In some embodiments of the device, the first upper insulating layer includes a first dielectric material, the second upper insulating layer includes a second dielectric material, and the first dielectric material has a different density than the second dielectric material. In some embodiments of the device, the first upper insulating layer includes a first dielectric material, the second upper insulating layer includes a second dielectric material, and the first dielectric material has a different porosity than the second dielectric material. In some embodiments of the device, the first upper insulating layer includes a first dielectric material, the second upper insulating layer includes a second dielectric material, and the first dielectric material is under a different stress than the second dielectric material. In some embodiments of the device, the second upper insulating layer is wider than the first upper insulating layer. In some embodiments, the device further includes: an inter-layer dielectric on the first source/drain regions, the first insulating fin, the second source/drain regions, and the second insulating fin, where the first insulating fin and a first portion of the inter-layer dielectric collectively separate the first source/drain regions from each other, and where the second insulating fin and a second portion of the inter-layer dielectric collectively separate the second source/drain regions from each other.

In an embodiment, a device includes: a first insulating fin including a first lower insulating layer and a first upper insulating layer, the first upper insulating layer including a first dielectric material; a first gate structure extending along a sidewall of the first lower insulating layer and along a top surface of the first upper insulating layer; a second insulating fin including a second lower insulating layer and a second upper insulating layer, the second upper insulating layer including a second dielectric material, the second dielectric material different from the first dielectric material; and a second gate structure extending along a sidewall of the second lower insulating layer and along a top surface of the second upper insulating layer. In some embodiments of the device, the second dielectric material is composed of more nitrogen or oxygen than the first dielectric material. In some embodiments of the device, the second dielectric material is denser than the first dielectric material. In some embodiments of the device, the second dielectric material is more porous than the first dielectric material. In some embodiments of the device, the first dielectric material is under a tensile strain and the second dielectric material is under a compressive strain. In some embodiments of the device, the first gate structure is on a first channel region, the second gate structure is on a second channel region, and the first channel region is longer than the second channel region.

In an embodiment, a method includes: patterning a multi-layer stack to form a first trench between first nanostructures and to form a second trench between second nanostructures, the first trench wider than the second trench; depositing a first dielectric layer in the first trench and the second trench, the first dielectric layer including a first dielectric material; converting a first portion of the first dielectric layer at a first bottom of the first trench to a second dielectric material, a second portion of the first dielectric layer at a second bottom of the second trench remaining as the first dielectric material; and removing portions of the first dielectric layer above the first nanostructures and the second nanostructures to form a first insulating fin in the first trench and to form a second insulating fin in the second trench. In some embodiments, the method further includes: etching a first recess in the first insulating fin with a first etching process, the first etching process selectively etching the second dielectric material at a faster rate than the first dielectric material; and etching a second recess in the second insulating fin with a second etching process, the second etching process selectively etching the first dielectric material at a faster rate than the second dielectric material. In some embodiments of the method, the first insulating fin is exposed to the second etching process and the second insulating fin is exposed to the first etching process. In some embodiments of the method, converting the first portion of the first dielectric layer to the second dielectric material includes: modifying a composition of the first portion of the first dielectric layer. In some embodiments of the method, converting the first portion of the first dielectric layer to the second dielectric material includes: modifying a density of the first portion of the first dielectric layer. In some embodiments of the method, converting the first portion of the first dielectric layer to the second dielectric material includes: modifying a porosity of the first portion of the first dielectric layer. In some embodiments of the method, converting the first portion of the first dielectric layer to the second dielectric material includes: modifying a stress of the first portion of the first dielectric layer.