Chip package having die structures of different heights and method of forming same

Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.

BACKGROUND

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also use a smaller package that utilizes less area or a smaller height, in some applications.

New packaging technologies have been developed to improve the density and functions of semiconductor devices. These relatively new types of packaging technologies for semiconductor devices face manufacturing challenges.

DETAILED DESCRIPTION

Some embodiments of the disclosure are described.FIGS. 1A-1Fare cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. Additional operations can be provided before, during, and/or after the stages described inFIGS. 1A-1F. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.

As shown inFIG. 1A, a semiconductor chip10and chip stacks20and30are bonded over a substrate180, in accordance with some embodiments. In some embodiments, the semiconductor chip10is higher than the chip stack20or30. In some embodiments, the semiconductor chip10includes a semiconductor substrate100and an interconnection structure (not shown) formed on the semiconductor substrate100. For example, the interconnection structure is formed on a bottom surface of the semiconductor substrate100. The interconnection structure includes multiple interlayer dielectric layers and multiple conductive features formed in the interlayer dielectric layers. These conductive features include conductive lines, conductive vias, and conductive contacts. Some portions of the conductive features may be used as conductive pads.

In some embodiments, various device elements are formed in the semiconductor substrate100. Examples of the various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), diodes, or other suitable elements.

The device elements are interconnected through the interconnection structure to form integrated circuit devices. The integrated circuit devices include logic devices, memory devices (e.g., static random access memories, SRAMs), radio frequency (RF) devices, input/output (I/O) devices, system-on-chip (SoC) devices, other applicable types of devices, or a combination thereof. In some embodiments, the semiconductor chip10is a system-on-chip (SoC) chip that includes multiple functions.

In some embodiments, each of the chip stacks20and30includes multiple semiconductor dies that are stacked. As shown inFIG. 1A, the chip stack20includes semiconductor dies200,202A,202B,202C,202D,202E,202F,202G, and202H. In some embodiments, the chip stack20includes a molding compound layer210that encapsulates and protects these semiconductor dies. The molding compound layer210may include an epoxy-based resin with fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof.

In some embodiments, the semiconductor dies202A,202B,202C,202D,202E,202F,202G, and202H are memory dies. The memory dies may include memory devices such as static random access memory (SRAM) devices, dynamic random access memory (DRAM) devices, other suitable devices, or a combination thereof. In some embodiments, the semiconductor die200is a control die that is electrically connected to the memory dies stacked thereon. The chip stack20may function as a high bandwidth memory (HBM). In some embodiments, the chip stack30is also a high bandwidth memory that includes multiple stacked memory dies.

Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, one of the chip stacks20and30includes only a single chip. In these cases, the reference number20or30can be used to designate a semiconductor chip.

In some embodiments, conductive bonding structures206are formed between these semiconductor dies200,202A,202B,202C,202D,202E,202F,202G, and202H to bond them together, as shown inFIG. 1A. In some embodiments, each of the conductive bonding structures206includes metal pillars and/or solder bumps. In some embodiments, underfill elements208are formed between these semiconductor dies to surround and protect the conductive bonding structures206. In some embodiments, the underfill element208includes an epoxy-based resin with fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof. In some embodiments, the size and/or density of the fillers dispersed in the underfill element208is smaller than those dispersed in the molding compound layer210.

In some embodiments, multiple conductive features282are formed in some of the semiconductor dies in the chip stack20, as shown inFIG. 1A. Each of the conductive features282penetrates through one of the semiconductor dies200,202A,202B,202C,202D,202E,202F,202G, and202H and is electrically connected to one of the conductive bonding structures206. The conductive features282are used as through substrate vias (TSVs). Electrical signals can be transmitted between these vertically stacked semiconductor dies through the conductive features282.

As shown inFIG. 1A, the semiconductor chip10and the chip stacks20and30are bonded onto the substrate180through conductive bonding structures106, in accordance with some embodiments. In some embodiments, the conductive bonding structures106include solder bumps, metal pillar bumps, other suitable structures, or a combination thereof. In some embodiments, each of the conductive bonding structures106includes a metal pillar bump102, a solder element104, and a metal pillar bump184, as shown inFIG. 1A. For example, the metal pillar bumps102and184are substantially made of copper.

In some embodiments, a number of metal pillar bumps102are formed over the bottom surfaces of the semiconductor chip10and the chip stacks20and30. In some embodiments, a number of metal pillar bumps184are formed over the substrate180before the bonding with the semiconductor chip10and the chip stacks20and30.

In some embodiments, solder material, such as solder paste, is applied on one or both of the metal pillar bumps102and184before the bonding process. Afterwards, the metal pillar bumps102and184are bonded together through the solder material. The solder material forms the solder elements104between the metal pillar bumps102and184. As a result, the conductive bonding structures106are formed, as shown inFIG. 1A. In some embodiments, the solder material is an alloy material that includes tin (Sn). The solder material also includes another element. The element may include lead, silver, copper, nickel, bismuth, another suitable element, or a combination thereof. In some embodiments, the solder material does not include lead.

In some embodiments, the substrate180includes a semiconductor material, a ceramic material, an insulating material, a polymer material, another suitable material, or a combination thereof. In some embodiments, the substrate180is a semiconductor substrate. The semiconductor substrate may be a semiconductor wafer, such as a silicon wafer.

As shown inFIG. 1A, a number of conductive features182are formed in the substrate180, in accordance with some embodiments. In some embodiments, the conductive features182are formed before the formation of the metal pillar bumps184. In some embodiments, each of the conductive features182is electrically connected to one of the metal pillar bumps184. Interconnection structures (not shown) including, for example, redistribution layers may be used to form electrical connections between the conductive features182and the metal pillar bumps184. In some embodiments, insulating elements (not shown) are formed between the conductive features182and the substrate180to prevent short circuiting between different conductive features182.

In some embodiments, the conductive features182are made of copper, aluminum, titanium, tungsten, cobalt, gold, platinum, another suitable material, or a combination thereof. In some embodiments, the insulating elements are made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof. In some embodiments, one or more photolithography and etching processes are used to form a number of openings that define the positions of the conductive features182. Afterwards, an insulating layer and a conductive layer are sequentially deposited over the substrate180to fill the openings. A planarization process is then performed to remove the portions of the insulating layer and the conductive layer outside of the openings. As a result, the remaining portions of the insulating layer and the conductive layer in the openings form the insulating elements and the conductive features182, respectively.

As shown inFIG. 1B, an underfill layer108is formed to surround and protect the conductive bonding structures106, in accordance with some embodiments. In some embodiments, the underfill layer108is in direct contact with the conductive bonding structures106. In some embodiments, a liquid underfill material is dispensed by capillary action and cured to form the underfill layer108. In some embodiments, the underfill layer108includes an epoxy-based resin with fillers dispersed therein. The fillers may include fibers, particles, other suitable elements, or a combination thereof.

As shown inFIG. 1C, a package layer110is formed over the substrate180to encapsulate the semiconductor chip10and the chip stacks20and30, in accordance with some embodiments. In some embodiments, the package layer110fills gaps between the semiconductor chip10and the chip stack20or30. In some embodiments, the package layer110is in direct contact with the underfill layer108. In some embodiments, the package layer110is not in direct contact with the conductive bonding structures106. In some embodiments, the package layer110is in direct contact with the molding compound layers210of the chip stacks20and30.

In some embodiments, the package layer110includes a polymer material. In some embodiments, the package layer110is a molding compound layer. The molding compound layer may include an epoxy-based resin with fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof. In some embodiments, the size and/or density of the fillers dispersed in the package layer110is greater than those dispersed in the underfill layer108.

In some embodiments, a liquid molding compound material is applied, and a thermal operation is then applied to cure the liquid molding compound material. As a result, the liquid molding compound material is hardened and transformed into the package layer110. In some embodiments, the thermal operation is performed at a temperature in a range from about 200 degrees C. to about 230 degrees C. The operation time of the thermal operation may be in a range from about 1 hour to about 3 hours.

As shown inFIG. 1D, the package layer110is planarized such that the top surface of the semiconductor chip10is exposed, in accordance with some embodiments. In some embodiments, the top surfaces of the semiconductor chip10and the package layer110are substantially coplanar with each other. In some embodiments, the package layer110is planarized using a grinding process, a chemical mechanical polishing (CMP) process, another applicable process, or a combination thereof. In some embodiments, the top surface of the chip stack20or30remains covered by the package layer110. In some embodiments, the chip stacks20and30are protected by the package layer110during the planarization process. The chip stacks20and30are not ground during the planarization process. Therefore, the chip stacks20and30are prevented from being damaged during the planarization process. The quality and reliability of the chip stacks20and30are significantly improved.

In some embodiments, the package layer110covers the top and the sidewalls of the chip stacks20and30, as shown inFIG. 1D. In some embodiments, the top surface of the semiconductor chip10is not covered by the package layer110. In some embodiments, the top surface of the package layer110is substantially coplanar with the top surface of the semiconductor chip10, which may facilitate subsequent processes.

As shown inFIG. 1E, the substrate180is thinned to expose the conductive features182, in accordance with some embodiments. In some embodiments, each of the conductive features182penetrates through the substrate180. In some embodiments, each of the conductive features182is electrically connected to one of the conductive bonding structures106. In some embodiments, the structure shown inFIG. 1Dis turned upside down. Afterwards, the substrate180is thinned using a planarization process to expose the conductive features182. The planarization process may include a CMP process, a grinding process, an etching process, another applicable process, or a combination thereof.

Afterwards, conductive elements are formed over the substrate180, as shown inFIG. 1Ein accordance with some embodiments. In some embodiments, the conductive elements include metal pillars114and solder elements116, as shown inFIG. 1E. However, many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the conductive elements have different structures. For example, the conductive elements do not include metal pillars. The conductive elements may only include solder bumps. In some embodiments, a buffer layer112is formed to protect the conductive elements. In some embodiments, each of the metal pillars114is electrically connected to one of the conductive features182. In some embodiments, the buffer layer112extends along portions of the sidewalls of the metal pillars114, as shown inFIG. 1E. In some embodiments, the buffer layer112is made of silicon nitride, silicon oxynitride, silicon oxide, polyimide, epoxy resin, polybenzoxazole (PBO), another suitable material, or a combination thereof.

As shown inFIG. 1F, the structure shown inFIG. 1Eis bonded onto a substrate118, in accordance with some embodiments. In some embodiments, the substrate118is a circuit board such as a printed circuit board. In some other embodiments, the substrate118is a ceramic substrate. In some embodiments, conductive elements120and124are formed on opposite surfaces of the substrate118, as shown inFIG. 1F. In some embodiments, the conductive elements120and124are solder bumps such as controlled collapse chip connection (C4) bumps and/or ball grid array (BGA) bumps. In some embodiments, the conductive elements120and the solder elements116are reflowed and bonded together, as shown inFIG. 1F.

In some embodiments, each of the conductive elements120is electrically connected to one of the conductive elements124through conductive features (not shown) formed in the substrate118. The conductive features may include conductive lines and conductive vias. In some embodiments, an underfill layer122is then formed between the substrate118and the substrate180to protect the conductive bonding structures therebetween.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG. 2is a cross-sectional view of a chip package, in accordance with some embodiments. In some embodiments, the underfill layer108is not formed. In some embodiments, the package layer110fills the space between the substrate180and the semiconductor chips including the semiconductor chip10and the chip stacks20and30. The package layer110surrounds the conductive bonding structures106. In some embodiments, since the underfill layer108is not formed, the package layer110is in direct contact with the conductive bonding structures106.

In some embodiments, the substrate180is used as an interposer. In some embodiments, the interposer does not include active devices therein. In some other embodiments, the interposer includes one or more active devices formed therein. In some embodiments, the substrate180is a silicon interposer. The substrate180may be used to improve the structural strength and reliability of the chip package. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, the substrate180is not formed.

FIGS. 3A-3Eare cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. As shown inFIG. 3A, the semiconductor chip10and the chip stacks20and30are attached on a carrier substrate300, in accordance with some embodiments. An adhesion layer (not shown) may be used to attach the semiconductor chip10and the chip stacks20and30onto the carrier substrate300. In some embodiments, the carrier substrate300includes a glass substrate, a ceramic substrate, a semiconductor substrate, a polymer substrate, another suitable substrate, or a combination thereof. In some embodiments, the carrier substrate300is a temporary substrate to support the semiconductor chip10and the chip stacks20and30during subsequent processes. Afterwards, the carrier substrate300may be removed.

As shown inFIG. 3B, a package layer310is formed over the carrier substrate300to encapsulate the semiconductor chip10and the chip stacks20and30, in accordance with some embodiments. In some embodiments, the package layer310fills gaps between the semiconductor chip10and the chip stack20or30. In some embodiments, the package layer310is in direct contact with the molding compound layers210of the chip stacks20and30.

In some embodiments, the package layer310includes a polymer material. In some embodiments, the package layer310is a molding compound layer. The molding compound layer may include an epoxy-based resin with fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof.

In some embodiments, a liquid molding compound material is applied, and a thermal operation is then applied to cure the liquid molding compound material. As a result, the liquid molding compound material is hardened and transformed into the package layer310. In some embodiments, the thermal operation is performed at a temperature in a range from about 200 degrees C. to about 230 degrees C. The operation time of the thermal operation may be in a range from about 1 hour to about 3 hours.

As shown inFIG. 3C, the package layer310is planarized so that the top surface of the semiconductor chip10is exposed, in accordance with some embodiments. In some embodiments, the package layer310is planarized using a grinding process, a chemical mechanical polishing (CMP) process, another applicable process, or a combination thereof. In some embodiments, the top surface of the chip stack20or30remains covered by the package layer310. In some embodiments, the chip stacks20and30are protected by the package layer310during the planarization process. The chip stacks20and30are not ground during the planarization process. Therefore, the chip stacks20and30are prevented from being damaged during the planarization process. The quality and reliability of the chip stacks20and30are significantly improved.

In some embodiments, the package layer310covers the top and the sidewalls of the chip stacks20and30, as shown inFIG. 3C. In some embodiments, the top surface of the semiconductor chip10is not covered by the package layer310. In some embodiments, the top surface of the package layer310is substantially coplanar with the top surface of the semiconductor chip10, which may facilitate subsequent processes.

As shown inFIG. 3D, the carrier substrate300is removed such that the bottom surfaces of the semiconductor chip10, the chip stacks20and30, and the package layer310are exposed, in accordance with some embodiments. In some embodiments, the bottom surfaces of the semiconductor chip10, the chip stacks20and30, and the package layer310are substantially coplanar with each other.

Afterwards, conductive elements are formed over the bottom surfaces of the semiconductor chip10and the chip stacks20and30, as shown inFIG. 3Din accordance with some embodiments. In some embodiments, the conductive elements include metal pillars314and solder elements316, as shown inFIG. 1E. In some other embodiments, the conductive elements include other configurations. In some embodiments, a buffer layer (not shown) is formed to protect the conductive elements.

As shown inFIG. 3E, the structure shown inFIG. 3Dis bonded onto a substrate318, in accordance with some embodiments. In some embodiments, the substrate318is a circuit board such as a printed circuit board. In some other embodiments, the substrate318is a ceramic substrate. In some embodiments, conductive elements320and324are formed on opposite surfaces of the substrate318, as shown inFIG. 3E. In some embodiments, the conductive elements320and324are solder bumps such as controlled collapse chip connection (C4) bumps and/or ball grid array (BGA) bumps. In some embodiments, the conductive elements320and the solder elements316are reflowed and bonded together, as shown inFIG. 3E.

In some embodiments, each of the conductive elements320is electrically connected to one of the conductive elements324through conductive features (not shown) formed in the substrate318. The conductive features may include conductive lines and conductive vias. In some embodiments, an underfill layer322is then formed between the substrate318and the chips including the semiconductor chip10and the chip stacks20and30to protect the conductive bonding structures therebetween. In some embodiments, the package layer310is not in direct contact with the conductive bonding structures therebetween.

In some embodiments, due to the protection of the package layer310, the chip stacks20and30are prevented from being damaged during the fabrication processes. For example, the stress generated from the planarization of the package layer310and the bonding process to the substrate318is buffered. The quality of the chip package is improved.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG. 4is a cross-sectional view of a chip package, in accordance with some embodiments. In some embodiments, the underfill layer108not only surrounds the conductive bonding structures106but further extends on sidewalls, of the semiconductor chip10. Portions of the sidewalls of the semiconductor chip10are covered by the underfill layer108. In some embodiments, the underfill layer108extends on the chip stacks20and30. Portions of the sidewalls of the chip stacks20and30are covered by the underfill layer108.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG. 5is a cross-sectional view of a chip package, in accordance with some embodiments. The structure shown inFIG. 5is similar to that shown in FIG. IF. In some embodiments, the semiconductor chip10is positioned between the chip stack20and a semiconductor chip40. In some embodiments, the semiconductor chip10is higher than the chip stack20or the semiconductor chip40. In some embodiments, the heights of the semiconductor chip40and the chip stack20are different from each other. In some embodiments, the semiconductor chip40is higher than the chip stack20.

In some embodiments, the semiconductor chip40includes a semiconductor substrate400and an interconnection structure (not shown) formed on the semiconductor substrate400. For example, the interconnection structure is formed on a bottom surface of the semiconductor substrate400. The interconnection structure includes multiple interlayer dielectric layers and multiple conductive features formed in the interlayer dielectric layers. These conductive features include conductive lines, conductive vias, and conductive contacts. Some portions of the conductive features may be used as conductive pads.

In some embodiments, similar to the semiconductor substrate100, various device elements are formed in the semiconductor substrate400. Examples of the various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), diodes, or other suitable elements.

The device elements are interconnected through the interconnection structure to form integrated circuit devices. The integrated circuit devices include logic devices, memory devices (e.g., static random access memories, SRAMs), radio frequency (RF) devices, input/output (I/O) devices, system-on-chip (SoC) devices, other applicable types of devices, or a combination thereof. In some embodiments, the semiconductor chip40is a system-on-chip (SoC) chip that includes multiple functions. In some embodiments, one or more of the functions of the semiconductor chips10and40are different from each other.

Embodiments of the disclosure form a chip package including a first semiconductor chip and a second semiconductor chip that may be a chip stack. The heights of the first semiconductor chip and the second semiconductor chip are different. A package layer, such as a molding compound layer, is formed to encapsulate the first semiconductor chip and the second semiconductor chip. The package layer is thinned to expose the first semiconductor chip. During the thinning process, the second semiconductor chip is protected by the package layer without being directly ground. The second semiconductor chip (or chip stack) is prevented from negatively affected due to the protection of the package layer during the thinning process. The performance and reliability of the chip package are significantly improved.

In accordance with some embodiments, a chip package is provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.

In accordance with some embodiments, a chip package is provided. The chip package includes a first semiconductor chip and a second semiconductor chip. The chip package also includes a molding compound layer surrounding the first semiconductor chip and the second semiconductor chip. The molding compound layer covers a top surface of the first semiconductor chip, and a top surface of the molding compound layer is substantially coplanar with a top surface of the second semiconductor chip.

In accordance with some embodiments, a method for forming a chip package is provided. The method includes bonding a first semiconductor chip and a second semiconductor chip over a substrate. The method also includes forming a package layer over the substrate to encapsulate the first semiconductor chip and the second semiconductor chip. The method further includes planarizing the package layer so that a top surface of the second semiconductor chip is exposed, and a top surface of the first semiconductor chip is covered by the package layer.