Serial advanced technology attachment dual in-line memory module

A serial advanced technology attachment dual in-line memory module (SATA DIMM) includes a control chip having a first input output (I/O) pin and a second I/O pin, first and second switches, a resistor, and a number of storage chips connected to the control chip. First terminals of the first and second switches are respectively connected to the first and second I/O pins. Second terminals of the first and second switches are grounded. The first and second I/O pins receive different signals through controlling the first and second switches, to change work modes of the storage chips.

BACKGROUND

1. Technical Field

The present disclosure relates to solid state drives (SSD), and particularly to a serial advanced technology attachment dual in-line memory module (SATA DIMM).

2. Description of Related Art

Solid state drives (SSD) store data on chips instead of on magnetic or optical discs. One type of SSD has the form factor of a DIMM module and it is called a SATA DIMM module. The SATA DIMM module includes a plurality of storage chips and can be inserted into a memory slot of a motherboard, to add storage capacity. However, different types of storage chips have different work modes. Thus, layout of the SATA DIMM module needs to be changed when the storage chip needs to be replaced, causing inconvenience.

DETAILED DESCRIPTION

The disclosure, including the drawing, is illustrated by way of example and not by way of limitation. References to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one.

Referring to the FIGURE, a serial advanced technology attachment dual in-line memory module (SATA DIMM)1can be inserted into a memory slot, such as a double data rate three type (DDR3) memory slot of a computer (not shown), to add storage capacity. The SATA DIMM module1in accordance with an exemplary embodiment includes a control chip10, switches S1and S2, a resistor30, and a plurality of storage chips40connected to the control chip10.

A first terminal of the switch S1is connected to an input output (I/O) pin general purpose input output (GPIO)10of the control chip10. A first terminal of the switch S2is connected to an I/O pin GPIO11of the control chip10. Second terminals of the switches S1and S2are grounded through the resistor30.

The I/O pins GPIO10and GPIO11of the control chip10receive different signals according to the states of the switches S1and S2, and control the work modes of the storage chips40according to the received level signals. For example, when the I/O pins GPIO10and GPIO11receive low level signals, the storage chips40work in a first work mode, such as an Async mode. When the I/O pin GPIO10is at a high level state and the I/O pin GPIO11receives a low level signal, the storage chips40work in a second work mode, such as a Toggle mode. When the I/O pin GPIO10receives a low level signal and the I/O pin GPIO11is at a high level state, the storage chips40work in a third work mode, such as an ONFI2 mode. When the I/O pins GPIO10and GPIO11are both at high level states, the storage chips40work in a fourth work mode, such as an Old async mode.

In use, when the storage chips40need to work in the first work mode, the switches S1and S2are both closed, the I/O pins GPIO10and GPIO11of the control chip10receive low level signals. The control chip10controls the storage chips40to work in the first work mode. When the storage chips40need to work in the second work mode, the switch S1is opened, and the switch S2is closed. The I/O pin GPIO10is at a high level state and the I/O pin GPIO11receives a low level signal. The control chip10controls the storage chips40to work in the second work mode. When the storage chips40need to work in the third work mode, the switch S1is closed and the switch S2is opened. The I/O pin GPIO10receives a low level signal and the I/O pin GPIO11is at a high level state. The control chip10controls the storage chips40to work in the third work mode. When the storage chips40need to work in the fourth work mode, the switches Si and S2are opened. The I/O pins GPIO10and GPIO11are both at high level states. The control chip10controls the storage chips40to work in the fourth work mode.

The SATA DIMM module1can change the work modes of the storage chips40through the switches S1and S2, which is convenient.