Semiconductor memory device having a charge accumulating layer including aluminum, oxygen, and nitrogen

A semiconductor memory device includes: a first and a second electrodes aligned in a first direction; a first semiconductor layer provided between the first and the second electrodes; a second semiconductor layer provided between the first semiconductor layer and the second electrode; a first charge accumulating layer provided between the first electrode and the first semiconductor layer; and a second charge accumulating layer provided between the second electrode and the second semiconductor layer. At least one of the first and the second charge accumulating layers include: a first and a second regions including nitrogen, aluminum, and oxygen and having different positions in a second direction; and a third region provided between the first and the second regions in the second direction. Oxygen is not included in the third region or a concentration of oxygen in the third region is lower than that in the first and the second regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of Japanese Patent Application No. 2019-054582, filed on Mar. 22, 2019, the entire contents of which are incorporated herein by reference.

Field

Embodiments described below relate to a semiconductor memory device.

BACKGROUND

Description of the Related Art

There is known a semiconductor memory device that includes: a substrate; a plurality of gate electrodes laminated in a direction intersecting a surface of this substrate; a semiconductor layer facing these plurality of gate electrodes; and a gate insulating layer provided between the gate electrodes and the semiconductor layer. The gate insulating layer includes a memory section capable of storing data, such as a silicon nitride (Si3N4) layer or a floating gate, for example.

DETAILED DESCRIPTION

A semiconductor memory device according to an embodiment includes: a first electrode and a second electrode aligned in a first direction; a first semiconductor layer provided between the first electrode and the second electrode, the first semiconductor layer facing the first electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, the second semiconductor layer facing the second electrode; a first charge accumulating layer provided between the first electrode and the first semiconductor layer, the first charge accumulating layer including nitrogen and aluminum; and a second charge accumulating layer provided between the second electrode and the second semiconductor layer, the second charge accumulating layer including nitrogen and aluminum. At least one of the first charge accumulating layer and the second charge accumulating layer includes: a first region including oxygen in addition to nitrogen and aluminum and having a first position as a position in a second direction, the second direction intersecting the first direction; a second region including oxygen in addition to nitrogen and aluminum and having a second position as a position in the second direction, the second position being different from the first position; and a third region having a third position as a position in the second direction, the third position being between the first position and the second position. Oxygen is not included in the third region or a concentration of oxygen in the third region is lower than concentrations of oxygen in the first region and the second region.

Next, semiconductor memory devices according to embodiments will be described in detail with reference to the drawings. Note that these embodiments are merely examples, and are not shown with the intention of limiting the present invention.

Moreover, the drawings are each schematic, and part of a configuration, and so on, of the drawings is sometimes omitted. Moreover, portions that are common to each of the embodiments are assigned with common symbols, and descriptions thereof are sometimes omitted.

Moreover, in the present specification, a certain direction parallel to a surface of a substrate will be called an X direction, a direction parallel to the surface of the substrate and perpendicular to the X direction will be called a Y direction, and a direction perpendicular to the surface of the substrate will be called a Z direction.

Moreover, in the present specification, sometimes, a direction along a certain plane will be called a first direction, a direction intersecting the first direction along this certain plane will be called a second direction, and a direction intersecting this certain plane will be called a third direction. These first direction, second direction, and third direction may, but need not, each respectively correspond to any one of the X direction, the Y direction, and the Z direction.

Moreover, in the present specification, expressions such as “up” or “down” will be defined with reference to the substrate. For example, an orientation of moving away from the substrate along the above-described Z direction will be called up, and an orientation of coming closer to the substrate along the Z direction will be called down. Moreover, when a lower surface or a lower end is referred to for a certain configuration, this will be assumed to mean a surface or end section on a substrate side of this configuration, and when an upper surface or an upper end is referred to for a certain configuration, this will be assumed to mean a surface or end section on an opposite side to the substrate of this configuration. Moreover, a surface intersecting the X direction or the Y direction will be called a side surface, and so on.

Moreover, in the present specification, when a “length” or a “thickness” in a certain direction is referred to for a configuration, a member, and so on, this will sometimes mean a length or a thickness in a cross section observed by the likes of SEM (Scanning Electron Microscopy) or TEM (Transmission Electron Microscopy), and so on.

Moreover, in the present specification, a “distance” between two configurations will mean the shortest distance in the observed cross section, not the distance between the center of gravity or center position of two configurations.

First Embodiment

FIG. 1is a schematic equivalent circuit diagram of a semiconductor memory device according to a first embodiment.

The semiconductor memory device according to the present embodiment includes: a memory cell array MA; and a control circuit CC that controls the memory cell array MA.

The memory cell array MA includes a plurality of memory units MU. These plurality of memory units MU each include two electrically independent memory strings MSa, MSb. One ends of these memory strings MSa, MSb are respectively connected to drain select transistor STD, and are connected to a common bit line BL via this drain select transistor STD. The other ends of the memory strings MSa, MSb are connected to a common source select transistor STS, and are connected to a common source line SL via this source select transistor STS.

The memory strings MSa, MSb each include a plurality of memory cells MC connected in series. The memory cell MC is a field effect type of transistor that includes: a semiconductor layer; a gate insulating layer; and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating layer includes a charge accumulating layer capable of storing data. A threshold voltage of the memory cell MC changes according to an amount of charge in the charge accumulating layer. The gate electrode is part of a word line WL.

The select transistors (STD, STS) are each a field effect type of transistor that includes: a semiconductor layer; a gate insulating layer; and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of the drain select transistor STD is part of a drain select gate line SGD. The gate electrode of the source select transistor STS is part of a source select gate line SGS.

The control circuit CC generates a voltage required in a read operation, a write operation, and an erase operation, and applies the generated voltage to the bit line BL, the source line SL, the word line WL, and the select gate lines (SGD, SGS), for example. The control circuit CC includes a plurality of transistors and wirings provided on the same chip as the memory cell array MA, for example. Note that the control circuit CC may include another chip such as a controller chip controlling a memory chip including the memory cell array MA, for example.

Next, a schematic configuration example of the semiconductor memory device according to the present embodiment will be described with reference toFIGS. 2 and 3.

The semiconductor memory device according to the present embodiment includes: a substrate110; and the memory cell array MA provided above the substrate110. Moreover, the memory cell array MA includes a plurality of laminated body structures LS arranged in the Y direction via trenches AT. The laminated body structure LS includes a plurality of conductive layers120laminated in the Z direction. Moreover, the memory cell array MA includes a plurality of memory holes MH aligned in the X direction along each of the trenches AT. There are provided in each of the memory holes MH: a semiconductor section130extending in the Z direction; gate insulating layers140a,140bprovided between the laminated body structures LS and the semiconductor section130; and an insulating layer150of the likes of silicon oxide (SiO2), provided between the semiconductor section130and the trench AT. An insulating layer151of the likes of silicon oxide (SiO2) is embedded in the trench AT. Moreover, a wiring layer160is connected to a lower end of the semiconductor section130.

The substrate110is a semiconductor substrate of the likes of single crystal silicon (Si), for example. The substrate110has a double well structure where, for example, an n type impurity layer is included in an upper surface of the semiconductor substrate, and a p type impurity layer is further included in this n type impurity layer. Note that a surface of the substrate110may be provided with the likes of transistors or wirings configuring the control circuit CC, for example.

The conductive layer120is a substantially plate-like conductive layer extending in the X direction, and is a conductive layer of the likes of a laminated film of titanium nitride (TiN) and tungsten (W), or the likes of polycrystalline silicon (Si) implanted with an impurity, for example. These conductive layers120respectively function as the word lines WL and gate electrodes of the memory cells MC (FIG. 1), or as the drain select gate lines SGD and gate electrodes of the drain select transistors STD (FIG. 1).

Below the plurality of conductive layers120, a conductive layer121including a material similar to that of the conductive layer120, for example, is provided. The conductive layer121functions as the source select gate line SGS and gate electrodes of the source select transistors STS (FIG. 1).

Between the plurality of conductive layers120, between the lowermost layer conductive layer120and the conductive layer121, and between the conductive layer121and the wiring layer160, an insulating layer122of the likes of silicon oxide (SiO2) is provided.

Hereafter, in the case of focusing on two laminated body structures LS adjacent in the Y direction, the plurality of conductive layers120included in one of the laminated body structures LS will sometimes be called first conductive layers120a. Moreover, the plurality of conductive layers120included in the other of the laminated body structures LS will sometimes be called second conductive layers120b.

The semiconductor section130includes: a first semiconductor layer130aand a second semiconductor layer130bthat are aligned in the Y direction via the trench AT; and a semiconductor layer133connected to lower ends of these.

The first semiconductor layer130ais a semiconductor layer of the likes of non-doped polycrystalline silicon (Si), for example. The first semiconductor layer130aextends in the Z direction, and faces the plurality of first conductive layers120alaminated in the Z direction. The first semiconductor layer130afunctions as channel regions of the plurality of memory cells MC and the drain select transistor STD included in the memory string MSa (FIG. 1).

The second semiconductor layer130bis a semiconductor layer of the likes of non-doped polycrystalline silicon (Si), for example. The second semiconductor layer130bextends in the Z direction, and faces the plurality of second conductive layers120blaminated in the Z direction. The second semiconductor layer130bfunctions as channel regions of the plurality of memory cells MC and the drain select transistor STD included in the memory string MSb (FIG. 1).

The semiconductor layer133faces two conductive layers121adjacent in the Y direction. The semiconductor layer133is a semiconductor layer of the likes of polycrystalline silicon (Si), and functions as a channel region of the source select transistor STS (FIG. 1). An insulating layer135of the likes of silicon oxide (SiO2) is provided between the semiconductor layer133and the conductive layer121.

The gate insulating layer140ais provided between the first semiconductor layer130aand the first conductive layer120a. The gate insulating layer140aincludes: a first tunnel insulating layer141a; a first charge accumulating layer142a; and a first block insulating layer143a. The first tunnel insulating layer141aand the first block insulating layer143aare insulating layers of the likes of silicon oxide (SiO2), for example. The first charge accumulating layer142awill be mentioned later.

The gate insulating layer140bis provided between the second semiconductor layer130band the second conductive layer120b. The gate insulating layer140bincludes: a second tunnel insulating layer141b; a second charge accumulating layer142b; and a second block insulating layer143b. The second tunnel insulating layer141band the second block insulating layer143bare insulating layers of the likes of silicon oxide (SiO2), for example. The second charge accumulating layer142bwill be mentioned later.

The wiring layer160is a plate-like conductive layer extending in the X direction and the Y direction. The wiring layer160is a conductive layer of the likes of polycrystalline silicon (Si) implanted with an impurity, for example, and functions as the source line SL (FIG. 1). Note that a structure of the source line SL may be appropriately changed. For example, the source line SL may be part of the surface of the substrate110. Moreover, the source line SL may include a metal layer of the likes of titanium nitride (TiN) and tungsten (W). Moreover, the source line SL may be connected to a lower end of the semiconductor section130, or may be connected to a side surface in the Y direction of the semiconductor section130.

FIG. 3is an XY cross-sectional view in which the structure shown inFIG. 2has been cut in the direction of the arrows along the line A-A′ and viewed in −Z direction.

As mentioned above, the semiconductor memory device according to the present embodiment includes pluralities of the conductive layers120arranged in the Y direction via the trenches AT. Moreover, the semiconductor memory device includes the substantially circular memory holes MH arranged in the X direction along each trench AT. Each of the memory holes MH is provided with the first semiconductor layer130a, the first tunnel insulating layer141a, the first charge accumulating layer142a, and the first block insulating layer143athat are provided between the trench AT and the first conductive layers120a. Moreover, each of the memory holes MH is provided with the second semiconductor layer130b, the second tunnel insulating layer141b, the second charge accumulating layer142b, and the second block insulating layer143bthat are provided between the trench AT and the second conductive layers120b.

Now, the conductive layers120includes facing surfaces123facing the first semiconductor layer130aand the second semiconductor layer130b. The facing surfaces123are formed concavely following a shape of the memory hole MH. On the other hand, the conductive layers120includes contacting surfaces124contacting the insulating layer151(portions of the conductive layers120provided between two memory holes MH aligned in the X direction). The contacting surfaces124are formed linearly following a shape of the trench AT. Moreover, connecting portions of the facing surfaces123and the contacting surfaces124are provided with corners125.

Moreover, the first semiconductor layer130a, the second semiconductor layer130b, and the gate insulating layers140a,140beach includes facing surfaces facing the facing surface123of the conductive layer120. These facing surfaces are formed convexly following the shape of the memory hole MH. On the other hand, the first semiconductor layer130a, the second semiconductor layer130b, and the gate insulating layers140a,140beach includes contacting surfaces contacting the insulating layer151. These contacting surfaces are formed linearly following a shape of the trench AT. Moreover, connecting portions of the facing surfaces and the contacting surfaces are provided with corners.

Moreover, the first charge accumulating layer142aof the gate insulating layer140aaccording to the present embodiment includes: a first region142a_1provided at one end in the X direction; a second region142a_2provided at the other end in the X direction; and a third region142a_3provided between these in the X direction. The first region142a_1and the second region142a_2have different positions in the X direction from each other and contact the insulating layer151. The first region142a_1and the second region142a_2are provided between the corners125of the conductive layer120and the corners of the first semiconductor layer130a, respectively. The third region142a_3has a position in the X direction between the position in the X direction of the first region142a_1and the position in the X direction of the second region142a_2. The first region142a_1and the second region142a_2include oxygen (O) and aluminum (Al), for example. For example, the first region142a_1and the second region142a_2include the likes of aluminum oxide (AlO), aluminum oxynitride (AlON), aluminum silicon oxide (AlSiO), or aluminum silicon oxynitride (AlSiON). The third region142a_3includes nitrogen (N) and aluminum (Al). For example, the third region142a_3includes the likes of aluminum nitride (AlN) or aluminum silicon nitride (AlSiN). Concentrations of oxygen in the first region142a_1and the second region142a_2are higher than a concentration of oxygen in the third region142a_3. The third region142a_3may, but need not, include oxygen. Note that range of the first region142a_1, the second region142a_2, and the third region142a_3in the first charge accumulating layer142acan be freely determined.

Moreover, the second charge accumulating layer142bof the gate insulating layer140baccording to the present embodiment includes: a first region142b_1provided at one end in the X direction; a second region142b_2provided at the other end in the X direction; and a third region142b_3provided between these in the X direction. The first region142b_1and the second region142b_2have different positions in the X direction from each other and contact the insulating layer151. The first region142b_1and the second region142b_2are provided between the corners125of the conductive layer120and the corners of the second semiconductor layer130b, respectively. The third region142b_3has a position in the X direction between the position in the X direction of the first region142b_1and the position in the X direction of the second region142b_2. The first region142b_1and the second region142b_2include oxygen (O) and aluminum (Al). For example, the first region142b_1and the second region142b_2include the likes of aluminum oxide (AlO), aluminum oxynitride (AlON), aluminum silicon oxide (AlSiO), or aluminum silicon oxynitride (AlSiON). The third region142b_3includes nitrogen (N) and aluminum (Al). For example, the third region142b_3includes the likes of aluminum nitride (AlN) or aluminum silicon nitride (AlSiN). Concentrations of oxygen in the first region142b_1and the second region142b_2are higher than a concentration of oxygen in the third region142b_3. The third region142b_3may, but need not, include oxygen. Note that range of the first region142b_1, the second region142b_2, and the third region142b_3in the second charge accumulating layer142bcan be freely determined.

Note that inFIG. 3, a distance in the Y direction between the first region142a_1of the first charge accumulation layer142aand the first region142b_1of the second charge accumulation layer142bis shown as a distance d1. Additionally, a distance in the Y direction between the second region142a_2of the first charge accumulation layer142aand the second region142b_2of the second charge accumulation layer142bis shown as a distance d2. Moreover, a distance in the Y direction between the third region142a_3of the first charge accumulation layer142aand the third region142b_3of the second charge accumulation layer142bis shown as a distance d3. In the illustrated example, the distance d1and the distance d2are substantially the same. On the other hand, the distance d3is larger than the distances d1and d2.

Additionally, aside surface of the insulating layer151according to the embodiment includes: a section151aand a section151bseparated in the X direction from each other and contacting the conductive layer120; a section151cand a section151dprovided between the sections151a,151band contacting the first semiconductor layer130aor the second semiconductor layer130b; a section151eprovided between the section151aand the section151cand contacting the first region142a_1of the first charge accumulation layer142aor the first region142b_1of the second charge accumulation layer142b; and a section151fprovided between the section151band the section151dand contacting the second region142a_2of the first charge accumulation layer142aor the second region142b_2of the second charge accumulation layer142b.

Next, a manufacturing method of the semiconductor memory device according to the present embodiment will be described with reference toFIGS. 4-16.

As shown inFIG. 4, in same manufacturing method, the wiring layer160is formed above an unillustrated substrate. In addition, a plurality of the insulating layers122and sacrifice layers170are alternately laminated on an upper surface of the wiring layer160. The sacrifice layer170is configured from the likes of silicon nitride (Si3N4), for example. Deposition of the wiring layer160, the insulating layers122, and the sacrifice layers170is performed by the likes of CVD (Chemical Vapor Deposition), for example.

Next, as shown inFIG. 5(an XY cross-sectional view corresponding to a cross section of the portion indicated by the line A-A′ inFIG. 2) andFIG. 6, the memory holes MH are formed in the insulating layers122and the sacrifice layers170. The memory holes MH are formed by, for example, forming on an upper surface of the structure shown inFIG. 4an insulating layer having openings in portions corresponding to the memory holes MH, and performing the likes of RIE (Reactive Ion Etching: RIE) with this insulating layer as a mask. A shape in XY cross section of the memory hole MH may be substantially circular, or may be substantially oval, for example. As shown inFIG. 6, the memory hole MH extends in the Z direction and penetrates the plurality of insulating layers122and sacrifice layers170to expose the upper surface of the wiring layer160.

Next, as shown inFIG. 7, the semiconductor layer133is formed in a bottom section of the memory hole MH. The semiconductor layer133is formed by the likes of epitaxial growth, for example.

Next, as shown inFIG. 8, a block insulating layer143, a charge accumulating layer142, a tunnel insulating layer141, and an amorphous silicon layer130A are deposited on a bottom surface and a side surface of the memory hole MH. This step is performed by a method such as CVD, for example.

Next, as shown inFIG. 9, parts of the deposited films (143,142,141,130A) are removed to expose an upper surface of the semiconductor layer133and an upper surface of the insulating layer122. This step is performed by the likes of RIE, for example.

Next, as shown inFIG. 10, an amorphous silicon layer and the insulating layer150are deposited on an inside of the memory hole MH. In addition, heat treatment, and so on, is performed, and a crystal structure of the amorphous silicon layer is reformed to form a semiconductor layer130B of the likes of polycrystalline silicon (Si).

Next, as shown inFIGS. 11 and 12, upper sections of the insulating layer150and the semiconductor layer130B are removed, and the upper surface of the insulating layer122is exposed to divide the semiconductor layer130B into portions corresponding to the respective memory holes MH.

Next, as shown inFIGS. 13 and 14, the trenches AT are formed in the insulating layers122and the sacrifice layers170. The trenches AT are formed by, for example, forming on an upper surface of the structure shown inFIG. 12an insulating layer having openings in portions corresponding to the trenches AT, and performing the likes of RIE with this insulating layer as a mask. The trench AT extends in the X direction as shown inFIG. 13. As shown inFIG. 14, the trench AT extends in the Z direction, and penetrates the plurality of insulating layers122and sacrifice layers170, and the layers (143,142,141,130B,150) in the memory hole MH to divide a configuration of these in the Y direction.

Due to this step, the first semiconductor layer130aand the second semiconductor layer130b, the first tunnel insulating layer141aand the second tunnel insulating layer141b, the first charge accumulating layer142aand the second charge accumulating layer142b, and the first block insulating layer143aand the second block insulating layer143bare formed.

Next, as shown inFIG. 15, end sections of the first charge accumulating layer142aand the second charge accumulating layer142bare oxidized. Due to this step, the first region142a_1, the second region142a_2, and the third region142a_3are formed in the first charge accumulating layer142a. Moreover, the first region142b_1, the second region142b_2, and the third region142b_3are formed in the second charge accumulating layer142b.

This step is performed by the likes of thermal oxidation, for example. An oxidation reaction proceeds from the trench AT. Hence, in the first charge accumulating layer142a, the likes of aluminum oxide (AlO), aluminum oxynitride (AlON), aluminum silicon oxide (AlSiO), or aluminum silicon oxynitride (AlSiON) are formed in the first region142a_1and the second region142a_2provided in a vicinity of the trench AT. On the other hand, in the third region142a_3separated from the trench AT, the likes of aluminum nitride (AlN) or aluminum silicon nitride (AlSiN) remain without being oxidized. The same applies also to the second charge accumulating layer142b.

Next, the sacrifice layers170are removed via the trenches AT, and upper surfaces and lower surfaces of the insulating layers122are exposed. This step is performed by a method such as wet etching, for example.

Next, as shown inFIG. 16, the insulating layer135is formed in a side surface of the semiconductor layer133by oxidation treatment, or the like. In addition, the conductive layers120are formed on the upper surfaces and the lower surfaces of the insulating layers122. This step is performed by a method such as CVD, for example. Moreover, the insulating layer151is formed in the trench AT by CVD, or the like. As a result, a structure of the kind shown inFIG. 2is formed.

The semiconductor memory device according to the first embodiment is formed by, for example, forming a plurality of the memory holes MH aligned in the X direction as described with reference toFIGS. 5 and 6, forming the semiconductor section130, and so on, in this memory hole MH as described with reference toFIG. 8, and so on, and forming the trench AT extending in the X direction as described with reference toFIGS. 13 and 14.

Such a structure makes it possible to form two electrically independent memory strings MSa, MSb in one memory hole MH, and makes it possible to provide a semiconductor memory device of large storage capacity.

However, in such a structure, a plurality of the corners125is formed in the conductive layer120, as described with reference toFIG. 3. It is easy for an electric field to concentrate in such a corner125, which sometimes causes a malfunction. For example, in the read operation, a channel of electrons is formed in an end section in the X direction of the first semiconductor layer130aby the electric field from the corner125, and a memory cell MC that should be read as OFF state is read as ON state, sometimes.

Now, in the present embodiment, regions of high oxygen concentration are provided in end sections in the X direction of the first charge accumulating layer142aand the second charge accumulating layer142b.

Now, the likes of aluminum oxide (AlO), aluminum oxynitride (AlON), aluminum silicon oxide (AlSiO), or aluminum silicon oxynitride (AlSiON) have a negative fixed charge. Hence, by providing end section regions of the first charge accumulating layer142aand the second charge accumulating layer142bwith the likes of a material having such a negative fixed charge, it is possible to prevent the unintended channel of electrons to be formed in end sections in the X direction of the first semiconductor layer130aand the second semiconductor layer130b. This makes it possible to provide a semiconductor memory device that suppresses effects of a fringe electric field from the corner125, and operates suitably.

Note that positions, ranges, and densities of charge of regions having negative fixed charge can be measured by using AFM (Atomic Force Microscopy). For example, by scanning a flat cross section of a semiconductor memory device with a cantilever while a voltage is applied to the cantilever, density of the negative fixed charge can be measured as electrostatic force between the device and the cantilever.

Second Embodiment

Next, a semiconductor memory device according to a second embodiment will be described with reference toFIGS. 17 and 18. Note that in the description below, portions similar to in the first embodiment will be assigned with the same symbols as in the first embodiment, and descriptions thereof will be omitted.

The memory cell array MA according to the present embodiment includes a plurality of laminated body structures LS' arranged in the Y direction via memory trenches MT. The laminated body structure LS' includes a plurality of conductive layers220laminated in the Z direction. Moreover, there are provided in each of the memory trenches MT: a plurality of semiconductor sections230arranged in the X direction via holes AH; gate insulating layers240a,240bprovided between the laminated body structures LS' and the semiconductor section230; and an insulating layer250of the likes of silicon oxide (SiO2), provided in a central portion of the semiconductor section230. An insulating layer251of the likes of silicon oxide (SiO2) is embedded in the hole AH. Moreover, the wiring layer160is connected to a lower end of the semiconductor section230.

The conductive layer220is basically configured similarly to the conductive layer120according to the first embodiment.

The semiconductor section230includes: a first semiconductor layer230aand a second semiconductor layer230bthat are aligned in the Y direction via the insulating layer250; and a semiconductor layer233connected to lower ends of these. These first semiconductor layer230a, second semiconductor layer230b, and semiconductor layer233are basically configured similarly to the first semiconductor layer130a, second semiconductor layer130b, and semiconductor layer133according to the first embodiment.

The gate insulating layer240aincludes: a first tunnel insulating layer241a; a first charge accumulating layer242a; and a first block insulating layer243a. The gate insulating layer240bincludes: a second tunnel insulating layer241b; a second charge accumulating layer242b; and a second block insulating layer243b. These are basically configured similarly to the first tunnel insulating layer141a, first charge accumulating layer142a, first block insulating layer143a, the second tunnel insulating layer141b, second charge accumulating layer142b, and second block insulating layer143baccording to the first embodiment.

However, as shown inFIG. 18, the conductive layers220includes, for example, facing surfaces223facing the first semiconductor layers230aor the second semiconductor layers230b. The facing surfaces223are formed linearly following a shape of the memory trench MT. On the other hand, the conductive layers220includes contacting surfaces224contacting the insulating layers250(a portion corresponding to the hole AH). The contacting surfaces are formed concavely following a shape of the hole AH. Moreover, connecting portion of the facing surface223and the contacting surface224is provided with a corner225.

Moreover, the first semiconductor layer230a, the second semiconductor layer230b, and the gate insulating layers240a,240beach includes facing surfaces facing the facing surfaces223of the conductive layer220. These facing surfaces are formed linearly following the shape of the memory trench MT. On the other hand, the first semiconductor layer230a, the second semiconductor layer230b, and the gate insulating layers240a,240beach includes contacting surfaces contacting the insulating layer251. These contacting surfaces are formed concavely following a shape of the hole AH. Moreover, a connecting portion of the facing surfaces and contacting surfaces are provided with a corner.

Moreover, the first charge accumulating layer242aof the gate insulating layer240aaccording to the present embodiment includes: a first region242a_1provided at one end in the X direction; a second region242a_2provided at the other end in the X direction; and a third region242a_3provided between these in the X direction. The first region242a_1and the second region242a_2have different positions in the X direction from each other and contact the insulating layer251. The first region242a_1and the second region242a_2are provided between the corners225of the conductive layer220and the corners of the first semiconductor layer230a, respectively. The third region242a_3has a position in the X direction between the position in the X direction of the first region242a_1and the position in the X direction of the second region242a_2. The first region242a_1and the second region242a_2include oxygen (O) and aluminum (Al). For example, the first region242a_1and the second region242a_2include the likes of aluminum oxide (AlO), aluminum oxynitride (AlON), aluminum silicon oxide (AlSiO), or aluminum silicon oxynitride (AlSiON). The third region242a_3includes nitrogen (N) and aluminum (Al). For example, the third region242a_3includes the likes of aluminum nitride (AlN) or aluminum silicon nitride (AlSiN). Concentrations of oxygen in the first region242a_1and the second region242a_2are higher than a concentration of oxygen in the third region242a_3. The third region242a_3may, but need not, include oxygen. Note that range of the first region242a_1, the second region242a_2, and the third region242a_3in the first charge accumulating layer242acan be freely determined.

Moreover, the second charge accumulating layer242bof the gate insulating layer240baccording to the present embodiment includes: a first region242b_1provided at one end in the X direction; a second region242b_2provided at the other end in the X direction; and a third region242b_3provided between these in the X direction. The first region242b_1and the second region242b_2have different positions in the X direction from each other and contact the insulating layer251. The first region242b_1and the second region242b_2are provided between the corners225of the conductive layer220and the corners of the second semiconductor layer230b, respectively. The third region242b_3has a position in the X direction between the position in the X direction of the first region242b_1and the position in the X direction of the second region242b_2. The first region242b_1and the second region242b_2include oxygen (O) and aluminum (Al). For example, the first region242b_1and the second region242b_2include the likes of aluminum oxide (AlO), aluminum oxynitride (AlON), aluminum silicon oxide (AlSiO), or aluminum silicon oxynitride (AlSiON). The third region242b_3includes nitrogen (N) and aluminum (Al). For example, the third region242b_3includes the likes of aluminum nitride (AlN) or aluminum silicon nitride (AlSiN). Concentrations of oxygen in the first region242b_1and the second region242b_2are higher than a concentration of oxygen in the third region242b_3. The third region242b_3may, but need not, include oxygen. Note that range of the first region242b_1, the second region242b_2, and the third region242b_3in the second charge accumulating layer242bcan be freely determined.

Note that inFIG. 18, an insulating layer251_1and an insulating layer2512embedded in two memory holes MH aligned in the X direction is illustrated. Additionally, a length in the Y direction of the insulating layer251_1is shown as a length d21, and a length in the Y direction of the insulating layer251_2is shown as a length d22. Moreover, a distance in the Y direction between the facing surface223aof the conductive layer220afacing the first semiconductor layer230aand the facing surface223bof the conductive layer220bfacing the first semiconductor layer230bis shown as a distance d23. In the illustrated example, the length d21and the length d22are substantially the same. On the other hand, the distance d23is smaller than the lengths d21and d22.

Next, a manufacturing method of the semiconductor memory device according to the present embodiment will be described with reference toFIGS. 19-30.

In same manufacturing method, first, a step similar to the step described with reference toFIG. 4will be performed.

Next, as shown inFIG. 19(an XY cross-sectional view corresponding to a cross section of the portion indicated by the line A-A′ inFIG. 17) andFIG. 20, the memory trenches MT are formed in the insulating layers122and the sacrifice layers170. The memory trenches MT are formed by, for example, forming on an upper surface of the structure shown inFIG. 4an insulating layer having openings in portions corresponding to the memory trenches MT, and performing the likes of RIE with this insulating layer as a mask. The memory trench MT extends in the X direction. As shown inFIG. 20, the memory trench MT extends in the Z direction and penetrates the insulating layers122and sacrifice layers170to expose the upper surface of the wiring layer160.

Next, as shown inFIG. 21, the semiconductor layer233is formed in a bottom section of the memory trench MT. The semiconductor layer233is formed by the likes of epitaxial growth, for example.

Next, as shown inFIG. 22, the block insulating layer143, the charge accumulating layer142, the tunnel insulating layer141, and the amorphous silicon layer130A are deposited on a bottom surface and side surfaces of the memory trench MT. This step is performed by a method such as CVD, for example.

Next, as shown inFIG. 23, parts of the deposited layers (143,142,141,130A) are removed to expose an upper surface of the semiconductor layer233and the upper surface of the insulating layer122. This step is performed by the likes of RIE, for example.

Next, as shown inFIG. 24, an amorphous silicon layer and the insulating layer250are deposited on an inside of the memory trench MT. In addition, heat treatment, and so on, is performed, and a crystal structure of the amorphous silicon layer is reformed to form the semiconductor layer130B of the likes of polycrystalline silicon (Si).

Next, as shown inFIGS. 25 and 26, upper sections of the insulating layer250and the semiconductor layer130B are removed, and the upper surface of the insulating layer122is exposed to divide the semiconductor layer130B into portions corresponding to the respective memory trenches MT.

Next, as shown inFIGS. 27 and 28, the holes AH are formed. The holes AH are formed by, for example, forming on an upper surface of the structure shown inFIG. 26an insulating layer having openings in portions corresponding to the holes AH, and performing the likes of RIE with this insulating layer as a mask. A shape in XY cross section of the hole AH may be substantially circular, or may be substantially oval, for example. As shown inFIG. 28, the hole AH extends in the Z direction and penetrates the layers (250,130B,141,142,143) in the memory trench MT to divide a structure in the memory trench MT in the X direction. This step is performed by the likes of RIE, for example.

Due to this step, the first semiconductor layer230aand the second semiconductor layer230b, the first tunnel insulating layer241aand the second tunnel insulating layer241b, the first charge accumulating layer242aand the second charge accumulating layer242b, and the first block insulating layer243aand the second block insulating layer243bare formed.

Next, as shown inFIG. 29, end sections of the first charge accumulating layer242aand the second charge accumulating layer242bare oxidized. Due to this step, the first region242a_1, the second region242a_2, and the third region242a_3are formed in the first charge accumulating layer242a. Moreover, the first region242b_1, the second region242b_2, and the third region242b_3are formed in the second charge accumulating layer242b.

This step is performed similarly to the step described with reference toFIG. 15, for example.

Next, the sacrifice layers170are removed via the holes AH, and upper surfaces and lower surfaces of the insulating layers122are exposed. This step is performed by a method such as wet etching, for example.

Next, as shown inFIG. 30, the insulating layer135is formed in a side surface of the semiconductor layer233by oxidation treatment, or the like. In addition, the conductive layers220are formed on the upper surfaces and the lower surfaces of the insulating layers122. This step is performed by a method such as CVD, for example. Moreover, the insulating layer251is formed in the hole AH by CVD, or the like. As a result, a structure of the kind shown inFIG. 17is formed.

Other Embodiments

That concludes exemplification of the semiconductor memory devices according to the first and second embodiments. However, the above configurations are merely exemplifications, and it is possible for specific configurations, and so on, to be appropriately adjusted.

For example, a single layer structure of the likes of aluminum nitride (AlN) or aluminum silicon nitride (AlSiN) was exemplified as the first charge accumulating layer142aand the second charge accumulating layer142baccording to the first embodiment (FIG. 3), and as the first charge accumulating layer242aand the second charge accumulating layer242baccording to the second embodiment (FIG. 18). However, a structure of the charge accumulating layer may be appropriately adjusted.

FIG. 31shows a first another example of the configuration according to the first embodiment.FIG. 31is a schematic XY cross-sectional view exemplifying a configuration of part of a semiconductor memory device according to the first another example.

In the first another example, a charge accumulating layer144ais provided between the first charge accumulating layer142aand the first tunnel insulating layer141a. In addition, a charge accumulating layer145ais provided between the first charge accumulating layer142aand the first block insulating layer143a.

Moreover, in the first another example, a charge accumulating layer144bis provided between the second charge accumulating layer142band the second tunnel insulating layer141b. In addition, a charge accumulating layer145bis provided between the second charge accumulating layer142band the second block insulating layer143b.

The charge accumulating layers144a,144b,145a,145bare charge accumulating layers that include nitrogen (N), for example. The charge accumulating layers144a,144b,145a,145binclude a nitride material of the likes of silicon nitride (SiN), hafnium nitride (HfN), or zirconium nitride (ZrN), for example.

Note thatFIG. 31exemplified a charge accumulating layer of three-layered structure configured from the charge accumulating layer144a, the first charge accumulating layer142a, and the charge accumulating layer145a. However, a charge accumulating layer of two-layered structure may be adopted by omitting one of the charge accumulating layers144a,145a, for example. The same applies also to the second charge accumulating layer142b.

Moreover,FIG. 31showed an example where the charge accumulating layer has a laminated structure in the configuration according to the first embodiment. However, as shown inFIG. 32, for example, in the configuration according to the second embodiment too, the charge accumulating layer may have the above-mentioned kind of laminated structure.

FIG. 33shows a second another example of the configuration according to the first embodiment.FIG. 33is a schematic XY cross-sectional view exemplifying a configuration of part of a semiconductor memory device according to the second another example.

A first charge accumulating layer142a′ and a second charge accumulating layer142b′ according to the second another example are basically configured similarly to the first charge accumulating layer142aand the second charge accumulating layer142baccording to the first embodiment. However, respective parts of configurations of the first regions142a_1′,142b_1′ and the second regions142a_2′,142b_2′, of the first charge accumulating layer142a′ and the second charge accumulating layer142b′ according to the second another example, differ from in the first embodiment.

The first charge accumulating layer142a′ and the second charge accumulating layer142b′ are basically configured similarly to in the first embodiment. However, the first charge accumulating layer142a′ and the second charge accumulating layer142b′ each have a structure projecting to a trench AT side.

InFIG. 33, a distance in the Y direction between the first region142a_1′ of the first charge accumulating layer142a′ and the first region142b_1′ of the second charge accumulating layer142b′ is shown as a distance d31. Additionally, a distance in the Y direction between the first semiconductor layer130aand the second semiconductor layer130bis shown as a distance d32. In the illustrated example, the distance d31is smaller than the distance d32.

Note thatFIG. 33exemplified a charge accumulating layer of three-layered structure. However, one or both of the charge accumulating layers144a,145amay be omitted, or one or both of the charge accumulating layers144b,145bmay be omitted, for example.

Moreover,FIG. 33exemplified a structure where part of the charge accumulating layer projects to the trench AT side in the configuration according to the first embodiment. However, as shown inFIG. 34, for example, in the configuration according to the second embodiment too, the first region242a_1′ and the second region242a_2′ of the first charge accumulating layer242a′, and the first region242b_1′ and the second region242b_2′ of the second charge accumulating layer242b′ may project to a hole AH side.

Note that inFIG. 34, a length in the X direction of the first charge accumulating layer242a′ is shown as a length d41. Additionally, a length in the X direction of the first semiconductor layer230ais shown as a length d42. In the illustrated example, the length d41is larger than the length d42.

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