Methods for fabricating FinFETs having different fin numbers and corresponding FinFETs thereof

Fin patterning methods disclosed herein achieve advantages of fin cut first techniques and fin cut last techniques while providing different numbers of fins in different IC regions. An exemplary method implements a spacer lithography technique that forms a fin pattern that includes a first fin line and a second fin line in a substrate. The first fin line and the second fin line have a first spacing in a first region corresponding with a single-fin FinFET and a second spacing in a second region corresponding with a multi-fin FinFET. The first spacing is greater than the second spacing, relaxing process margins during a fin cut last process, which partially removes a portion of the second line in the second region to form a dummy fin tip in the second region. Spacing between the dummy fin tip and the first fin in the second region is greater than the second spacing.

BACKGROUND

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, ICs often implement fin-like field effect transistors (FinFETs) having different numbers of fins to optimize performance, such as a first FinFET device having an odd number of fins (for example, one) adjacent to a second FinFET device having an even number of fins (for example, two). Multiple patterning processes implemented to meet shrinking fin widths and/or fin pitches required for advanced IC technology nodes typically fabricate an even number of fin lines, such that a fin cutting process is needed to provide an odd number of fin lines in a region of the IC corresponding with the first FinFET. The shrinking fin widths and/or fin pitches has placed constraints on the fin cutting process and significantly limited fin patterning process margins. Although existing fin patterning techniques have been generally adequate for achieving different numbers of fins in different regions of an IC, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

The present disclosure relates generally to integrated circuit (IC) devices, and more particularly, to fin-like field effect transistor (FinFET) devices.

For advanced IC technology nodes, FinFETs (also referred to as non-planar transistors) have become a popular and promising candidate for high performance and low leakage applications. IC s often implement FinFETs having different numbers of fins to optimize performance for different applications. For example, single-fin FinFETs typically exhibit low leakage current and low power consumption, yet operate at lower speeds, whereas multi-fin FinFETs can operate at high speeds, yet often exhibit higher leakage current and higher power consumption than single-fin FinFETs. Accordingly, to optimize IC performance, ICs often implement multi-fin FinFETs in high speed circuits and/or applications and single-fin FinFETs for low speed and/or non-speed critical circuits and/or applications. Such configurations can allow a system-on-chip (SOC), which is a device that integrates various functions on a single chip, to provide high speed logic operations with overall lower power consumption

As FinFET technologies progress towards smaller IC technology nodes (for example, 22 nm, 16 nm, 10 nm, 7 nm, and below), fins are formed by a multiple patterning process, which combines lithography processes and self-aligned processes to create fin patterns that have, for example, pitches or spacings smaller than what is otherwise obtainable using a single, direct lithography process. Spacer lithography (patterning) is a popular multiple patterning process that can achieve narrower fin widths and smaller fin pitches desired for advanced IC technology nodes. Spacer lithography forms a fin etching mask that is used for removing portions of a substrate (or patterning layer) to form fins in the substrate (or in the patterning layer, which is subsequently used to pattern the substrate). An example spacer lithography process for forming the fin etching mask includes forming a patterned sacrificial layer (which includes sacrificial features having widths that correspond with desired spacings between fins) over the substrate using a lithography process, forming a spacer layer over the patterned sacrificial layer and the substrate, etching the spacer layer to form spacers along sidewalls of each sacrificial feature (for example, the spacer layer is removed from top surfaces of the sacrificial features and a portion of a top surface of the substrate (or patterning layer)), and removing the patterned sacrificial layer, leaving spacers having spacings therebetween. The spacings may be substantially equal to the widths of the sacrificial features, such that the spacings between the spacers correspond with the desired spacings between fins. The spacers form the fin etching mask, which includes openings that expose a portion of the substrate (or patterning layer).

Since a pair of spacers is formed along sidewalls of each sacrificial feature, spacer lithography typically generates pairs of fin lines (or even numbers of fin lines), where each pair of fin lines corresponds with a respective pair of spacers. A fin cut process (including lithography processes and etching processes) is thus needed to provide single fin lines (or odd numbers of fin lines) in desired IC regions. The fin cut process removes unwanted fin lines or unwanted portions of the fin lines (often referred to as dummy fins or dummy portions of the fin lines) to achieve different numbers of fin lines in different IC regions. A fin cut first technique removes spacers that correspond with the unwanted fin lines from the fin etching mask before the fin etching mask is used for etching the substrate. In contrast, a fin cut last technique removes the unwanted fin lines after the fins have been formed in the substrate using the fin cut mask. Tighter fin pitches in advanced IC technology nodes have led to tighter cut lithography overlay margins to ensure that unwanted fin lines are completely removed without damaging wanted fin lines. Though the fin cut first technique provides larger cut lithography overlay margins, the fin cut last technique provides a uniform environment during the fin etch (for example, a uniform density) that minimizes etching loading effects, which minimizes bending of the wanted fin lines and achieves more vertical fin line profiles.

The present disclosure thus proposes fin patterning methods that achieve advantages of both the fin cut first technique, such as increased cut lithography overlay margins, and the fin cut last technique, such as fins that exhibit more vertical fin profiles and minimum bending. The proposed fin patterning methods achieve these advantages while providing different numbers of fins in different IC regions (more particularly, even numbers of fins and odd numbers of fins), such that standard cells for SoCs can be fabricated with FinFETs designed for both high speed and/or low power consumption applications. For example, an IC device may include a single-fin FinFET adjacent to a two-fin FinFET, where the single-fin FinFET is configured for low power consumption and the two-fin FinFET is configured for high speed operation. In some implementations, the single-fin FinFET has an operating frequency that is less than or equal to about 1 GHz, and the two-fin FinFET has an operating frequency that is greater than or equal to about 2 GHz. The fins for such IC device are formed by a spacer lithography technique configured to form a fin pattern that includes a first fin line and a second fin line in a substrate, where the first fin line and the second fin line have a first spacing in a first region corresponding with the single-fin FinFET and a second spacing in a second region corresponding with the two-fin FinFET. The first spacing is greater than the second spacing, enabling larger process margins (for example, larger cut lithography overlay windows and improved critical dimension uniformity control during etching) during a fin cut last process that is used to remove a portion of the second fin line in the second region. The fin cut last process partially removes the portion of the second in line in the second region, such that a dummy fin tip remains in the second region. A spacing between the dummy fin tip and the first fin in the second region is greater than the second spacing between the first fin and the second fin in the first region. The fin cut last process allows for a dummy portion of the second fin line to be formed adjacent to the first line in the first region, which creates a denser fin environment in the first region during formation of the fin pattern in the substrate. The denser fin environment minimizes etch loading effects, providing the first fin line in the first region with a more vertical fin profile than would be achieved with fin cut first techniques. Different embodiments may have different advantages, and no particular advantage is necessarily required of any embodiment.

FIG. 1is a flow chart of a method10for fabricating an IC device according to various aspects of the present disclosure. At block20, method10includes forming a dummy pattern over a substrate. The dummy pattern has a first width in a first region corresponding with a first FinFET device and a second width in a second region corresponding with a second FinFET device. The second width being greater than the first width. At block30, method10proceeds with forming spacers along sidewalls of the dummy pattern. At block40, method10proceeds with removing the dummy pattern, thereby forming a spacer pattern having a first spacing between spacers in the first region and a second spacing between spacers in the second region, wherein the second spacing is greater than the first spacing. Method10continues at block50with transferring the spacer pattern to the substrate, thereby forming a first fin and a second fin separated by the first spacing in the first region and separated by the second spacing in the second region. At block60, method10proceeds with partially removing the second fin from the second region to form a dummy fin tip. Method10can continue to fabricate additional features of the IC device. Additional steps can be provided before, during, and after method10, and some of the steps described can be moved, replaced, or eliminated for additional embodiments of method10.

FIGS. 2A-2C, 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C,FIGS. 11A-11F, andFIGS. 12A-12Fare fragmentary diagrammatic views of an IC device100, in portion or entirety, at various fabrication stages of a method, such as method10ofFIG. 1, according to various aspects of the present disclosure. In particular,FIGS. 2A-12Aare simplified schematic top views of IC device100(for example, in an x-y plane);FIGS. 2B-12Bare diagrammatic cross-sectional views of IC device100along line B-B respectively ofFIGS. 2A-12A(for example, in an x-z plane);FIGS. 2C-12Care diagrammatic cross-sectional views of IC device100along line C-C respectively ofFIGS. 2A-12A(for example, in the x-z plane);FIGS. 11D-12Dare diagrammatic cross-sectional views of IC device100along line D-D respectively ofFIGS. 11A-12A(for example, in the x-z plane);FIGS. 11E-12Eare diagrammatic cross-sectional views of IC device100along line E-E respectively ofFIGS. 11A-12A(for example, in the x-z plane); andFIGS. 11F-12Fare diagrammatic cross-sectional views of IC device100along line F-F respectively ofFIGS. 11A-12A(for example, in the x-z plane). IC device100can be included in a microprocessor, a memory cell, and/or other IC device. In some implementations, IC device100is a portion of an IC chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. In some implementations, IC device100is a portion of a standard cell that includes FinFETs configured for both high speed and/or low power consumption applications.FIGS. 2A-2C, 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C,FIGS. 11A-11F, andFIGS. 12A-12Fhave been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in IC device100, and some of the features described below can be replaced, modified, or eliminated in other embodiments of IC device100.

Turning toFIGS. 2A-2C, IC device100includes a substrate (wafer)102. In the depicted embodiment, substrate102is a bulk substrate that includes silicon. Alternatively or additionally, the bulk substrate includes another elementary semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadnium sulfide, and/or cadmium telluride; an alloy semiconductor, such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; other group III-V materials; other group II-IV materials; or combinations thereof. Alternatively, substrate102is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. Substrate102includes various doped regions, such as a doped region104A and a doped region104B, configured according to design requirements of IC device100. In some implementations, substrate102includes p-type doped regions (for example, p-type wells) doped with p-type dopants, such as boron (for example, BF2), indium, other p-type dopant, or combinations thereof. In some implementations, substrate102includes n-type doped regions (for example, n-type wells) doped with n-type dopants, such as phosphorus, arsenic, other n-type dopant, or combinations thereof. In some implementations, substrate102includes doped regions formed with a combination of p-type dopants and n-type dopants. In the depicted embodiment, doped region104A is configured for at least one p-type FinFET to be formed in a p-type FinFET region106A and doped region104B of IC device100is configured for at least one n-type FinFET to be formed in an n-type FinFET region106B of IC device100. For example, in the depicted embodiment, doped region104A is an n-type well and doped region104B is a p-type well. The various doped regions can be formed directly on and/or in substrate102, for example, providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, or combinations thereof. An ion implantation process, a diffusion process, and/or other suitable doping process can be performed to form the various doped regions.

A patterning layer110is formed over substrate102. Patterning layer110includes a material that is different than a material of substrate102to achieve etching selectivity during a fin etching process, such that substrate102can be selectively etched with minimal (or no) etching of patterning layer110. In the depicted embodiment, patterning layer110includes multiple layers to achieve processing flexibility, such as a pad layer112, a first mask layer114, and a second mask layer116, where pad layer112is disposed on substrate102, first mask layer114is disposed on pad layer112, and second mask layer116is disposed on first mask layer114. In some implementations, pad layer112includes silicon and oxygen (for example, silicon oxide), first mask layer114includes silicon and nitrogen (for example, silicon nitride and/or silicon oxynitride), and second mask layer116includes silicon and oxygen (for example, silicon oxide). In some implementations, pad layer112and/or second mask layer116are silicon oxide layers formed by thermal oxidation and/or other suitable process, and first mask layer114is a silicon nitride layer formed by chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), thermal nitridation (for example, of silicon), other suitable process, or combinations thereof. In some implementations, pad layer112includes a material that promotes adhesion between substrate102and first mask layer114and/or functions as an etch stop layer when etching first mask layer114. The present disclosure contemplates other materials for and/or methods for forming pad layer112, first mask layer114, and/or second mask layer116, along with other configurations of patterning layer110.

Turning toFIGS. 3A-3C, a patterned dummy layer120(also referred to as a sacrificial layer) is formed over patterning layer110and substrate102. Patterned dummy layer120includes dummy patterns (also referred to as sacrificial patterns), such as a dummy pattern122disposed over patterning layer110in p-type FinFET region106A and a dummy pattern124disposed over patterning layer110in n-type FinFET region106B. In some implementations, patterned dummy layer120can be referred to as a mandrel layer and dummy patterns122,124can be referred to as mandrels, which serve as temporary support structures for subsequently formed spacers. Patterned dummy layer120includes a material that is different than a material of patterning layer110(or substrate102, for example, in implementations where patterning layer110is omitted) to achieve etching selectivity during an etching process, such that patterned dummy layer120can be selectively removed using a corresponding etchant with minimal (or no) etching of patterning layer110. The materials of patterned dummy layer120and patterning layer110thus have different etch sensitivity. For example, where a first material and a second material have a 10:1 sensitivity ratio to a given etchant, the first material may be etched by the given etchant to a selected depth and/or amount while removing only about 10% as much of the second material. Accordingly, dummy patterned layer120includes a semiconductor material and/or a dielectric material that is different than a material of second mask layer116of patterning layer110. For example, patterned dummy layer120includes silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof. In the depicted embodiment, patterned dummy layer120includes amorphous silicon or polysilicon and second mask layer116includes silicon oxide, as these materials exhibit different etch sensitivity. In another example, patterned dummy layer120includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof.

Dummy pattern122and dummy pattern124each have a width along the x-direction, where the width corresponds with a spacing (or pitch) between active fins to be formed in a portion of substrate102. IC device100includes IC regions configured with FinFETs having different numbers of fins, such as an IC region130A configured for FinFETs having an even number of fins and an IC region130B configured for FinFETs having an odd number of fins. In the present embodiment, FinFETs having two fins (referred to as multi-fin FinFETs) will be formed in IC region130A, while FinFETs having one fin (referred to as single-fin FinFETs) will be formed in IC region130B. As described further herein, to increase process margins during subsequent processing, including during a fin cut last process where portions of active fins formed in the portion of substrate102are removed to achieve different numbers of fins for IC regions130A,130B, dummy patterns122,124each have a width that varies as it spans IC regions130A,130B. For example, dummy patterns122,124have a width W1in IC region130A, which is configured for two-fin FinFETs, and a width W2in IC region130B, which is configured for single-fin FinFETs, where width W2is greater than width W1. Width W1is substantially equal to a desired spacing between active fins to be formed in IC region130A. In some implementations, width W1is greater than a desired spacing between active fins to compensate for consumption of patterning layers (for example, spacers and/or patterning layer110) and/or substrate used to form the fins during subsequent processing (for example, to compensate for etch loading effects), such that the active fins have the desired spacing upon completion of fabrication of IC device100. Width W2is configured to increase a process margin during a fin cut last process, where portions of active fins formed in the portion of substrate102are removed to achieve odd numbers of fins, and in the present example, single fins in IC region130B. In the depicted embodiment, a ratio of width W2to width W1is configured to relax lithography overlay margins during the fin cut last process, improve critical dimension uniformity (CDU) control of the active fins, and/or relax etching process parameters used during subsequent processing. For example, a ratio of width W2to width W1is about 1.05 to about 2.

Patterned dummy layer120is formed over patterning layer110using any suitable process. In some implementations, a combination of deposition, lithography, and/or etching processes are performed to define dummy pattern122and dummy pattern124of patterned dummy layer120as illustrated inFIGS. 3A-3C. For example, forming dummy patterns122,124includes depositing a dummy layer (for example, a polysilicon layer) over patterning layer110, forming a patterned resist layer over the dummy layer using a lithography process, etching the dummy layer using the patterned resist layer as an etch mask, and removing the patterned resist layer (for example, by a resist stripping process), leaving patterned dummy layer120that includes dummy patterns122,124. The lithography processes can include forming a resist layer (for example, by spin-on coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a developing process. During the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light), where the mask blocks, transmits, and/or reflects radiation to the resist layer depending on a mask pattern of the mask and/or mask type (for example, binary mask, phase shift mask, or EUV mask), such that an image is projected onto the resist layer that corresponds with the mask pattern. Since the resist layer is sensitive to radiation energy, exposed portions of the resist layer chemically change, and exposed (or non-exposed) portions of the resist layer are dissolved during the developing process depending on characteristics of the resist layer and characteristics of a developing solution used in the developing process. After development, the patterned resist layer includes a resist pattern that corresponds with the mask. The patterned resist layer can then be used as an etch mask during an etching process to remove portions of an underlying layer, such as the dummy layer. The etching process can include a dry etching process (for example, a reactive ion etching (RIE) process), a wet etching process, other suitable etching process, or combinations thereof. The patterned resist layer can be removed before or after the etching process. In some implementations, the exposure process can implement maskless lithography, electron-beam writing, ion-beam writing and/or nanoprint technology.

The present disclosure proposes modifying a mask pattern of a mask used during the lithography process for forming patterned dummy layer220, such that dummy pattern122includes a portion122′ that corresponds with a first jog inserted into a mask layout and dummy pattern124includes a portion124′ that corresponds with a second jog inserted into a mask layout. In some implementations, an IC design layout (also referred to as an IC design pattern) is generated for fabricating fins of the two-fin FinFETs and single-fin FinFETs of IC device100. In some implementations, the IC design layout includes six geometrical shapes (for example, lines (rectangles)) that correspond with the fins to be formed in a substrate. For example, the IC design layout includes a first region (corresponding with p-type FinFET region106A) directly adjacent to a second region (corresponding with n-type FinFET region106B), where the first region and the second region each include a first sub-region (corresponding with IC region130A) that is directly adjacent to a second sub-region (corresponding with IC region130B). The first region includes a first line and a second line separated by a first spacing in the first sub-region of the first region, where the first line and the second line correspond with two fins to be formed in the substrate. The first region further includes a third line in the second sub-region of the first region, where the third line corresponds with a single fin to be formed in the substrate. The second region includes a fourth line and a fifth line separated by the first spacing in the first sub-region of the second region, where the fourth line and the fifth line correspond with two fins to be formed in the substrate. The second region further includes a sixth line in the second sub-region of the second region that corresponds with a single fin to be formed in the substrate. The first, second, third, fourth, fifth, and sixth lines are arranged to have lengths that extend in a first direction, such as the y-direction, and widths that extend in a second direction that is substantially perpendicular to the first direction, such as the x-direction. The first, second, fourth, and fifth lines are arranged substantially parallel to one another, and the third and sixth lines are arranged substantially parallel to one another. The third line is aligned with the first line along the y-direction, and the sixth line is aligned with the fifth line along the y-direction. The IC design layout is presented in one or more data files having information of the circuit patterns (geometrical patterns). For example, the IC design layout is expressed in a Graphic Database System file format (such as GDS or GDSII) or another suitable file format, such as Open Artwork System Interchange Standard file format (such as OASIS or OAS).

A mask pattern (mask layout) is then generated for forming patterned dummy layer120based on a target pattern (here, six lines) defined by the IC design layout. The mask layout can therefore be referred to as a dummy pattern layout. The mask layout includes a first mask region (corresponding with p-type FinFET region106A) directly adjacent to a second mask region (corresponding with n-type FinFET region106B), where the first mask region and the second mask region each include a first mask sub-region (corresponding with IC region130A) that is directly adjacent to a second mask sub-region (corresponding with IC region130B). In some implementations, the mask layout includes dummy pattern that includes a first dummy line and a second dummy line. The first dummy line spans continuously from the first mask sub-region of the first mask region to the second mask sub-region of the first mask region, and the second dummy line that spans continuously from the first mask sub-region of the second mask region to the second mask sub-region of the second mask region. The first dummy line has a width that is substantially the same as the spacing between the first line and the second line in the IC design layout, and the second dummy line has a width that is substantially the same as the spacing between the fourth line and the fifth line in the IC design layout. The widths of the first dummy line and the second dummy line thus correspond with a desired spacing (or pitch) between fins of two-fin FinFETs. The first dummy line corresponds with dummy pattern122, and the second dummy line corresponds with dummy pattern124.

To increase lithography process margins during a fin cut, the mask layout is modified in the second mask sub-regions, which correspond with IC region130B, of the first mask region and the second mask region. For example, a jog pattern is inserted into the dummy pattern to increase a final spacing between fins in regions of IC device100where single or odd numbers of fins will be formed in the substrate (and thus regions of IC device100where a fin cut process will remove fins). In some implementations, the jog pattern includes a first jog line disposed adjacent to the first dummy line in the second mask sub-region of the first mask region and a second jog line disposed adjacent to the second dummy line in the second mask sub-region of the second mask. The first jog line and the second jog line extend substantially parallel respectively to the first dummy line and the second dummy line. In some implementations, the first jog line and the second jog line extend an entire length respectively of the first jog line and the second jog line in the second mask sub-regions. A width of the first jog line is configured such that a sum of the width of the first dummy line and the width of the first jog line in the second mask sub-region is greater than the width of the first dummy line in the first mask sub-region. A width of the second jog line is configured such that a sum of the width of the second dummy line and the width of the second jog line in the second mask sub-region is greater than the width of the second dummy line in the first mask sub-region. Jogs are therefore inserted next to any dummy line or portion of a dummy line corresponding with a region of an IC device where FinFETs will include an odd number of fins (here, single fins). A mask fabricated using the modified mask layout (including the mask pattern and the jog pattern) will have a final mask pattern that corresponds with the modified mask layout, such that the mask includes a first mask feature and a second mask feature. The first mask feature and the second mask feature have a first width in a first region and a second width in a second region, where the second width is less than the first width. Accordingly, when the mask is used for forming patterned dummy layer120, dummy pattern122includes portion122′ corresponding with the first jog line and dummy pattern124includes a portion124′ corresponding with the second jog line, and dummy patterns122,124have widths that vary along the y-direction. In particular, widths of dummy patterns122,124increase from IC region130A to IC region130B.

A fin cut pattern layout is also generated for removing unwanted fins and/or unwanted portions of the fins, such that IC device100includes fins that correspond with the target pattern (here, six lines) defined by the IC design layout. The cut pattern layout is generated based on the modified mask layout, which includes the mask pattern and the jog pattern. The cut pattern layout includes a cut pattern that defines one or more openings. In some implementations, the cut pattern defines an opening have a width greater than a sum of a width of the first jog line, a width of the second jog line, and a spacing between the first jog line and the second jog line. In such implementations, the opening completely overlaps and exposes the first jog line and the second jog line and partially overlaps the first dummy line and the second dummy line in the second mask sub-regions of the first mask region and the second mask region. In some implementations, the cut pattern defines a first opening having a first width that is greater than a sum of a width of the first jog line, and a second opening having a second width that is greater than a width of the second jog line. In such implementations, the first opening completely overlaps and exposes the first jog line and partially overlaps the first dummy line in the second mask sub-region of the first mask region, and the second opening completely overlaps and exposes the second jog line and partially overlaps the second dummy line in the second mask sub-region of the second mask region. Other configurations of the openings defined by the cut pattern are contemplated by the present disclosure. A fin cut mask fabricated using the fin cut pattern layout (including the cut pattern) will have a final cut pattern that corresponds with the fin cut pattern layout. Accordingly, the fin cut mask includes at least one fin cut feature that corresponds with an opening to be formed in a patterning layer during a fin cut process. Since the first jog line and the second jog line increase widths of the a spacing between spacers (and eventually fins) formed during the fin patterning process, lithography overlay requirements are relaxed during the fin cut process using the fin cut mask. For example, as described further below, the disclosed fin patterning process can tolerate greater shifts of the at least one cut feature along the x-direction relative to the fins.

Turning toFIGS. 4A-4C, a deposition process is performed to form a spacer layer140over patterning layer110and patterned dummy layer120. Spacer layer140includes a material that is different than a material of patterned dummy layer120and a material of patterning layer110to achieve etching selectivity during an etching process, such that spacer layer140can be selectively removed using a corresponding etchant with minimal (or no) etching of patterned dummy layer120and patterning layer110. Spacer layer140thus includes a semiconductor material and/or a dielectric material that is different than a material of patterned dummy layer120and a material of second mask layer116to achieve different etch sensitivity. For example, spacer layer140includes silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium oxide, titanium nitride, or combinations thereof). In the depicted embodiment, where patterned dummy layer120includes amorphous silicon or polysilicon and second mask layer116includes silicon oxide, spacer layer140includes silicon nitride. In some implementations, spacer layer140includes a high-k dielectric material. Spacer layer140is deposited over patterning layer110and dummy patterned layer120using atomic layer deposition (ALD), CVD, PECVD, other suitable deposition process, or combinations thereof. For example, in the depicted embodiment, an ALD process conformally deposits spacer layer140over patterning layer110and dummy patterned layer120, such that spacer layer140has a substantially uniform thickness over top surfaces of patterning layer110, top surfaces of dummy patterns122,124, and sidewalls of dummy patterns122,124.

Turning toFIGS. 5A-5C, an etching process is performed on spacer layer140to form spacers140A along sidewalls of dummy patterns122,124. The etching process is configured to remove spacer layer140from the top (and/or horizontal) surfaces of patterning layer110and top (and/or horizontal) surfaces of dummy patterns122,124. In some implementations, the etching process is an anisotropic etch process (for example, a plasma etch process) configured to selectively remove the spacer layer140with minimal (to no) removal of second mask layer116and dummy patterns122,124, such that only portions of spacer layer140disposed on sidewalls of dummy patterns122,124remain. Spacers140A have widths along the x-direction that correspond with widths of active fins to be formed in a portion of substrate102. For example, spacers140A have a width W3in p-type FinFET region106A and spacers140A have a width W4in n-type FinFET region106B, where width W3corresponds with a desired width for fins of p-type FinFETs of IC device100and width W4corresponds with a desired width for fins of n-type FinFETs of IC device100. In the depicted embodiment, width W3is substantially the same as width W4. In some implementations, width W3is different than width W4depending on design requirements of IC device100. In some implementations, width W3and/or width W4are equivalent to a minimum fin width. In some implementations, the minimum fin width generally refers to a smallest fin width achievable by a lithography process and/or a fin fabrication process (including deposition, lithography, and/or etching processes) of a given IC technology node. In some implementations, the minimum fin width generally refers to a smallest fin width specified by design requirements for IC device100. In some implementations, deposition and etching of spacer layer140can be configured for more precise control of the widths of spacers140A than that achieved by lithography alone. For example, a thickness of spacer layer140as deposited and etching parameters of the etching process can be tuned to precisely control widths W3, W4of spacers140A. In some implementations, spacers140A are trimmed before or after removing dummy patterns122,124to further achieve desired widths W3, W4of spacers140A.

Turing toFIGS. 6A-6C, an etching process is performed to remove dummy pattern122and dummy pattern124, leaving spacers140A disposed over patterning layer110. The etching process selectively etches patterned dummy layer120with minimal (to no) etching of spacers140A and patterning layer110(particularly, second mask layer116), such that dummy patterns122,124are removed and spacers140A remain over patterning layer110. The etching process is a dry etching process, a wet etching process, or combinations thereof. Spacers140A are separated by a spacing S1in IC region130A and a spacing S2in IC region130B. Spacing S1corresponds with width W1of dummy patterns122,124, and spacing S2corresponds with width W2of dummy patterns122,124. For example, spacing S1is equal to width W1(S1≈W1), spacing S2is equal to width W2(S2≈W2), and a ratio of spacing S2to spacing S1is about 1.05 to about 2 (1.05≤S2:S1≤2). Spacing S1thus defines a desired spacing between active fins to be formed in a portion of substrate102, and spacing S2defines a spacing that relaxes subsequent processing requirement and/or margins, including during a fin cut last process used to remove portions of the active fins.

Turning toFIGS. 7A-7C, a fin etching process is performed to define a fin150A, a fin150B, a fin150C, and a fin150D (collectively referred to as a fin layer) in a portion of substrate102using spacers140and/or patterning layer110as an etch mask. Fins150A,150B are disposed in p-type FinFET region106A and span IC regions130A,130B, and fins150C,150D are disposed in n-type FinFET region106B and span IC regions130A,130B. Fins150A-150D are oriented substantially parallel to one another, each having a width defined in the x-direction, a length defined in the y-direction, and a height defined in the z-direction. Because dummy patterns122,124had varying widths, spacing between fin150A and fin150B varies along the lengths of fins150A,150B, and spacing between fin150C and fin150D varies along the lengths of fins150C,150D. In the depicted embodiment, fin150A is separated from fin150B by spacing S3in IC region130A and spacing S4in IC region130B, fin150C is separated from fin150D by spacing S3in IC region130A and spacing S4in IC region130B, and spacing S4is greater than spacing S3. Spacing of spacers140A is transferred to the fin layer. For example, spacing S3is substantially equal to spacing S1(S3≈S1), spacing S4is substantially equal to spacing S2(S4≈S2), and a ratio of spacing S4to spacing S3is about 1.05 to about 2 (1.05≤S4:S3≤2). Spacing S3is thus substantially equal to desired spacing between active fins of IC device100, and spacing S4sufficiently relaxes subsequent processing requirements and/or margins. In the depicted embodiment, where substrate102is a bulk substrate that includes silicon, fins150A-150D include silicon. In some implementations, where substrate102includes a semiconductor layer stack disposed over a bulk substrate, fins150A-150D are defined in the semiconductor layer stack, such that fins150A-150D include one or more semiconductor material layers. In furtherance of the depicted embodiment, after the fin etching process, trenches155are defined between fins150A-150D, where trenches155have sidewalls defined by sidewalls of fins150A-150D and bottoms defined by top surfaces of substrate102.

The fin etching process selectively etches portions of patterning layer110and substrate102that are not covered (or protected) by spacers140A with minimal (to no) etching of spacers140A, such that spacers140A serve as an etch mask for removing portions of patterning layer110and/or substrate102. The etching process is a dry etching process, a wet etching process, or combinations thereof. In some implementations, the fin etching process is an anisotropic dry etching process (for example, a RIE process) configured to substantially remove patterning layer110and a portion of substrate102along the z-direction with minimal (to no) removal of patterning layer110and the portion of substrate102along the x-direction and the y-direction. In some implementations, a dry etching process uses a fluorine-containing precursor (for example, CF4, SF6, NF3, CH2F2, CHF3, and/or C2F6), an oxygen-containing precursor, a chlorine-containing precursor (for example, Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing precursor (for example, HBr and/or CHBR3), an iodine-containing precursor, other suitable precursor (which can be used to generate an etchant gas and/or etching plasma), or combinations thereof. In some implementations, a wet etching process implements an etching solution that includes TMAH, NH4OH, H2O2, H2SO4, HF, HCl, other suitable wet etching constituent, or combinations thereof. Various etching parameters can be tuned to selectively etch patterning layer110and substrate102, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof. The present disclosure contemplates any combination of etching processes and/or other processes for defining fins150A-150D. For example, spacers140A are removed after (or during) etching of patterning layer110, such that spacers140A serve as an etching mask for etching patterning layer110and patterning layer110serves as an etching mask for etching substrate102. In another example, spacers140A are removed after (or during) etching of substrate102, such that spacers140A serve as an etching mask for etching patterning layer110and substrate102. In some implementations, spacers140A and/or patterning layer110may be partially removed during the fin etching process. In some implementations, patterning layer110is omitted. In such implementations, spacers140A include a material that is different than substrate102to achieve etching selectivity during an etching process, such that portions of substrate102can be selectively etched with minimal (or no) etching of spacers140A, and vice versa.

Turning toFIGS. 8A-8C, IC device100is depicted after removing spacers140A and patterning layer110. As noted above, spacers140A and/or patterning layer110can be removed during or after the fin etching process. Fins150A,150B have a width W5, and fins150C,150D have a width W6. Widths of spacers140A is transferred to the fin layer. For example, width W5is substantially equal to width W3(W5≈W3), and width W6is substantially equal to width W4(W6≈W4). Because spacing between fins150A,150B and fins150C,150D varies along their lengths, each pair of fins has a fin (here, fin150B and fin150C) that includes an active fin region160, a dummy fin region162, and a fin connecting region164that connects the active fin region160and the dummy fin region160. Active fin region160corresponds with an active fin of a FinFET, and dummy fin region162corresponds with a dummy fin, which is an extra fin feature that is included within the fin layer to maintain fin feature density (and thus minimize patterning effects, such as fin etch loading effects, that can affect CDU of active fins, such as active fins150A,150D in IC region130B) and/or correspond with a dummy tip fin feature (also referred to as a residual fin feature) to be formed in a portion of substrate102, where the dummy fin and/or the dummy tip fin feature are electrically non-functional features of IC device100.

Turning toFIGS. 9A-9C, a fin cut last process is performed to remove portions of fins150A-150D from regions of IC device100configured for FinFETs having odd numbers of fins. In the depicted embodiment, where IC region130A is configured for two-fin FinFETs and IC region130B is configured for single-fin FinFETs, the fin cut last process removes dummy fin regions162of fins150B,150C in IC region130B. The fin cut last process partially removes dummy fin regions162, such that a dummy fin tip150B′ remains in p-type FinFET region106A and a dummy fin tip150C′ remains in n-type FinFET region106B. Dummy fin tips150B′,150C′ can be referred to as residual fin features. Fins150A-150D have a height H1and dummy fin tips150B′,150C′ have a height H2that is less than height H1. In some implementations, height H1is about 90 nm to about 300 nm, and height H2is less than about 30 nm. In some implementations, height H2is at least 70 nm less than H1(in other words, H1-H2≥70 nm). In IC region130B, fin150A is separated from dummy tip fin150B′ by spacing S5, and dummy tip fin150C′ is separated from fin150D by spacing S5. The fin cut process is configured to ensure that spacing S5is greater than spacing S3between fins150A,150B in IC region130A and between fins150C,150D in IC region130A. In the depicted embodiment, a ratio of spacing S5to spacing S3is about 1.05 to about 2 (1.05≤S5:S3≤2). In some implementations, the fin cut last process also partially removes fin connecting regions164of fins150B,150C. The fin cut last process may completely or partially remove fin connecting regions164along the x-direction. For example, where partially removed along the x-direction, a first portion of fin connecting regions164that is not removed has height H1and a second portion of fin connecting regions164that is removed has height H2. The present disclosure contemplates variations in the portions of fins150A-150D removed during the fin cut last process.

The fin cut last process includes forming a patterned masking layer over fins150A-150D and isolation layer170, where the patterned masking layer includes a cut pattern defining protected portions of fins150A-150D (here, fin150A, active fin region160of fin150B, active fin region160of fin150C, and fin150D) and unprotected (unwanted) portions of fins150A-150D (here, dummy fin regions162and fin connecting regions164of fins150B,150C). In the depicted embodiment, the cut pattern defines an opening in the patterned masking layer that exposes dummy fin regions162and fin connecting regions164of fins150B,150C in IC region130B. In some implementations, the cut pattern defines an opening in the patterned masking layer that exposes only dummy fin regions162of fins150B,150C in IC region130B. In some implementations, the patterned masking layer is a patterned resist layer formed by a lithography process, such as those described herein. In some implementations, the patterned masking layer is a patterned hard mask layer, which is formed by depositing a hard mask layer over fins150A-150D, forming a patterned resist layer having the cut pattern using a lithography process, such as those described herein, and etching the hard mask layer using the patterned resist layer as an etch mask, such that the patterned hard mask layer includes the cut pattern exposing the unprotected portions of fins150A-150D. In some implementations, the patterned masking layer has a multi-layer structure. The fin cut last process further includes etching the unprotected portions of fins150A-150D using the patterned masking layer as an etch mask. In some implementations, a selective etching process removes dummy fin regions162and fin connecting regions164of fins150B,150C with minimal (to no) removing of the patterned masking layer. The etching process is a dry etching process, a wet etching process, or combinations thereof. Various etching parameters can be tuned to selectively remove dummy fin regions162and fin connecting regions164of fins150B,150C, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof. In some implementations, a wet etching process uses an etching solution that includes tetramethylammonium hydroxide (TMAH), hydrofluoric acid (HF), sulfuric acid (H2SO4), hydrogen chloride (HCl), ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), other suitable wet etching constituent, or combinations thereof. Thereafter, the patterned masking layer is removed (for example, by a resist stripping process and/or a selective etching process), leaving dummy fin tips150B′,150C′ as depicted inFIGS. 9A-9C.

Increasing the spacing between the fins in IC regions where FinFETs having odd numbers of fins will be formed (here, spacing S4between fins150A, fin150B and between fins150C,150D in IC region130B is greater than spacing S3between fins150A,150B and between fins150C,150D in IC region130A) relaxes lithography overlay margins during the fin cut last process. For example, referring toFIG. 9A, the opening in the patterned masking layer defined by the cut pattern fully exposes unprotected portions of fins150A-150D in IC region130B (here, dummy fin regions162and fin connecting regions164), where an overlay window constrains alignment of the opening with underlying fins150A-150D. The overlay window defines boundaries for cut edges in the patterned masking layer that define the opening, ensuring that fins150A,150D in IC region130B remain covered by the patterned masking layer, while fins150B,150C are exposed by the opening in the patterned masking layer. These boundaries are constrained by spacing between fins150A,150B and spacing between fins150C,150D. For example, conventional fin cut processes often specify an overlay (cut) budget that is a fraction of the spacing between fins150A,150B and spacing between fins150C,150D. For example, to ensure that fins150A,150D remain covered and protected during the fin cut process, the overlay budget may be set to spacing/2, such that the cut edges can shift left (L) no more than a distance equal to spacing/2 from the sidewall of fin150B that is directly adjacent to fin150A and shift (R) no more than a distance equal to spacing/2 from the sidewall of fin150C that is directly adjacent to fin150D. As IC technologies continually progress towards smaller feature sizes (such as 32 nanometers, 28 nanometers, 20 nanometers, and below), scaling down of pitch is shrinking spacing between fins, drastically decreasing the overlay budget. The present disclosure overcomes these challenges because spacing between fins150A-150D in IC region130B is greater than spacing between fins150A-150D in IC region130A (in particular, spacing S4is greater than spacing S3, where a ratio of spacing S4to spacing S3is about 1.05 to about 2). The increased spacing in IC region130B relaxes the overlay budgets by allowing greater left/right shift and/or greater widths of the opening in the patterned masking layer.

Turning toFIGS. 10A-10C, an isolation layer170is formed over substrate102to isolate various regions, such as various device regions, of IC device100. For example, isolation layer170separates and isolates active device regions and/or passive device regions from each other, such as a p-type FinFET that includes fins150A,150B in IC region130A from an n-type FinFET that includes fins150C,150D in IC region130B, a p-type FinFET that includes fin150A in IC region130B from an n-type FinFET that includes fin150D in IC region130B, the p-type FinFET that includes fin150A from dummy fin tip150B′ in IC region130B, and the n-type FinFET that includes fin150D from dummy fin tip150C′ in IC region130B. Isolation layer170further separates and isolates fins150A-150D from one another. In the depicted embodiment, isolation layer170surrounds a bottom portion of fins150A-150D, thereby defining upper fin active regions of fins150A-150D (generally referring to a portion of fins150A-150D that extend from a top surface of isolation layer170). In furtherance of the depicted embodiment, isolation layer170completely covers dummy fin tips150B′,150C′. For example, isolation layer170has a thickness T that is less than height H1of fins150A-150D and greater than height H2of dummy fin tips150B′,150C′ (H1>T>H2). In some implementations, thickness T is about 40 nm to about 250 nm. Isolation layer170includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material (for example, including silicon, oxygen, nitrogen, carbon, or other suitable isolation constituent), or combinations thereof. Isolation layer170can be configured to form shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and/or local oxidation of silicon (LOCOS) structures to define active regions of IC device100and/or between fins150A-150D. In the depicted embodiment, STI features are formed by depositing an insulator material over substrate102after the fin cut last process (for example, by using a CVD process or a spin-on glass process), such that the insulator material fills trenches155between fins150A-150D and covers dummy tip fins150B′,150C′), and performing a chemical mechanical polishing (CMP) process to remove excessive insulator material. The CMP process may be performed until exposing top surfaces of fins150A-150D (or, in some implementations, until masking layer disposed over the tops surfaces of fins150A-150D), where the fins150A-150D (or the masking layer) act as a CMP stop layer. An etching back of the insulator material layer can then be performed on the isolation layer170to form the isolation features. Dummy fin tips150B′,150C′ can improve isolation feature formation. For example, dummy fin tips150B′,150C′ maintain a uniform feature density in IC regions130A,130B, which can improve gap filling characteristics, such as filling of trenches155. Without dummy fin tips150B′,150C′, active fin-fin spacing creates a fully isolated environment (for example, spacing between fin150A and fin150D in IC region130B) and a dense environment (for example, spacing between fins150A-150D in IC region130A), where isolation layer170needs to fill both the fully isolated environment and the dense environment without gaps. Dummy fins tips150B′,150C′ create a semi-isolated environment in IC region130B, facilitating more uniform coverage and filling of isolation layer170in IC regions130A,130B. In some implementations, isolation layer170includes a multi-layer structure that partially fills trenches155, such as a bulk dielectric layer disposed over a liner dielectric layer, where the bulk dielectric layer and the liner dielectric layer include materials depending on design requirements of IC device100(for example, a bulk dielectric layer that includes silicon nitride disposed over a liner dielectric layer that includes thermal oxide). In some implementations, isolation layer170includes a dielectric layer disposed over a doped liner layer (including, for example, boron silicate glass (BSG) or phosphosilicate glass (PSG)).

Turning toFIGS. 11A-11F, various gate structures are formed over fins150A-150D, such as a gate structure180A, a gate structure180B, a gate structure180C, a gate structure180D, a gate structure180E, and a gate structure180F. Gate structures180A-180F extend along the x-direction (for example, substantially perpendicular to fins150A-150D) and traverse fins150A-150D, such that gate structures180A-180F wrap upper fin active regions of respective fins150A-150D. In the depicted embodiment, gate structure180A, gate structure180B, and gate structure180C are disposed over channel regions of fins150A-150D. Gate structures180A-180C wrap respective channel regions of fins150A-150D, thereby interposing respective source/drain regions of fins150A-150D. Gate structures180A-180C each engage the respective channel regions of fins150A-150D, such that current can flow between the respective source/drain regions of fins150A-150D during operation. Gate structure180D wraps portions of fins150A-150D, positioned such that a source/drain region of fins150A-150D is disposed between gate structure180D and gate structure180A; gate structure180E wraps portions of fins150A-150D, positioned such that a source/drain region of fins150A-150D is disposed between gate structure180E and gate structure180C; and gate structure180F wraps portions of fins150A,150D, positioned such that a source/drain region of fins150A,150D is disposed between gate structure180F and gate structure180C and a source/drain region of fins150A,150D is disposed between gate structure180F and gate structure180B. Gate structures180C,180E,180F also span over dummy tip fins150B′,150C′, such that isolation layer170is disposed between gate structures180C,180E,180F and dummy tip fins150B′,150C′.

In some implementations, gate structures180A-180C are active gate structures, whereas gate structures180D-180F are dummy gate structures. “Active gate structure” generally refers to an electrically functional gate structure of IC device100, whereas “dummy gate structure” generally refers to an electrically non-functional gate structure of IC device100. In some implementations, a dummy gate structure mimics physical properties of an active gate structure, such as physical dimensions of the active gate structure, yet is inoperable (in other words, does not enable current to flow). In some implementations, gate structures180D-180F enable a substantially uniform processing environment, for example, enabling uniform epitaxial material growth in source/drain regions of fins150A-150D (for example, when forming epitaxial source/drain features), uniform etch rates in source/drain regions of fins150A-150D (for example, when forming source/drain recesses), and/or uniform, substantially planar surfaces (for example, by reducing (or preventing) CMP-induced dishing effects). In some implementations, gate structures180D-180F are configured to electrically and/or physically isolate FinFETs of IC device100. For example, gate structure180F electrically isolates multi-fin FinFETs in IC region130A from single-fin FinFETs in IC region130B. In the depicted embodiment, gate structure180F electrically isolates a source/drain region of a two-fin p-type FinFET (which includes gate structure180B) in IC region130A from a single-fin p-type FinFET (which includes gate structure180C) in IC region130B. In furtherance of the depicted embodiment, gate structure180F also electrically isolates a source/drain region of a two-fin n-type FinFET (which includes gate structure180B) in IC region130A from a single-fin n-type FinFET (which includes gate structure180C) in IC region130B.

Gate structures180A-180F include gate stacks configured to achieve desired functionality according to design requirements of IC device100, such that gate structures180A-180F include the same or different layers and/or materials. In the depicted embodiment, gate structures180D,180E (dummy gate structures) are configured the same as gate structures180A-180C (active gate structures). Since gate structures180A-180E span p-type FinFET region106A and n-type FinFET region106B, gate structures180A-180E may have different layers in regions corresponding with p-type FinFET region106A and n-type FinFET region106B. For example, gate structures180A-180E have gate stacks182A in p-type FinFET region106A and gate stacks182B in n-type FinFET region106B, where gate stacks182A are different than gate stacks182B to achieve different threshold voltages for the p-type FinFETs in p-type FinFET region106A and the n-type FinFETs in n-type region106B. A number, configuration, and/or materials of layers of gate stacks182A corresponding with p-type FinFET region106A may be different than a number, configuration, and/or materials of layers of gate stacks182B corresponding with n-type FinFET region106B. In the depicted embodiment, gate stacks182A include a gate dielectric184A and a gate electrode186A, gate stacks182B include a gate dielectric184B and a gate electrode186B. A number, configuration, and/or materials of layers of gate dielectric184A and/or gate electrode186A may be the same or different than a number, configuration, and/or materials of layers of gate dielectric184B and gate electrode186B. In some implementations, gate stacks182A,182B can share one or more layers, such that the one or more layers extend continuously from gate stacks182A to gate stacks182B (for example, a gate dielectric). In some implementations, one or more layers shared by gate stacks182A,182B may be configured to achieve different characteristics.

Gate electrodes186A,186B are respectively disposed over gate dielectrics184A,184B. Gate electrodes186A,186B include an electrically conductive material. In some implementations, gate electrodes186A,186B includes multiple layers, such as one or more capping layers, work function layers, glue/barrier layers, and/or metal fill (or bulk) layers. In the depicted embodiment, gate electrodes186A have layers configured to achieve a p-type work function, while gate electrodes186B have layers configured to achieve an n-type work function. A capping layer can include a material that prevents or eliminates diffusion and/or reaction of constituents between gate dielectrics184A,184B and other layers of gate structures180A-180E (in particular, gate layers including metal). In some implementation, the capping layer includes a metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or combinations thereof. A work function layer can include a conductive material tuned to have a desired work function (such as an n-type work function or a p-type work function), such as n-type work function materials and/or p-type work function materials. P-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type work function material, or combinations thereof. N-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function material, or combinations thereof. A glue/barrier layer can include a material that promotes adhesion between adjacent layers, such as the work function layer and the metal fill layer, and/or a material that blocks and/or reduces diffusion between gate layers, such as such as the work function layer and the metal fill layer. For example, the glue/barrier layer includes metal (for example, W, Al, Ta, Ti, Ni, Cu, Co, other suitable metal, or combinations thereof), metal oxides, metal nitrides (for example, TiN), or combinations thereof. A metal fill layer can include a suitable conductive material, such as Al, W, and/or Cu. In some implementations, a hard mask layer (including, for example, silicon nitride or silicon carbide) is disposed over at least a portion of gate electrodes186A,186B. Gate electrodes186A,186B are formed by various deposition processes, such as ALD, CVD, PVD, and/or other suitable process, such as those described herein. A CMP process can be performed to remove any excess material of gate dielectrics184A,184B and/or gate electrodes186A,186B, planarizing gate structures180A-180E.

In furtherance of the depicted embodiment, since gate structure180F is configured to achieve isolation between FinFETs of IC region130A,130B, gate structure180F (dummy gate structure) is configured differently than gate structures180D,180E (dummy gate structures) and gate structures180A-180C (active gate structures). For example, gate structure180F has a gate stack182C that includes a gate dielectric184C. Gate dielectric184C includes a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbonitride, other suitable dielectric material for isolation (for example, including silicon, oxygen, nitrogen, carbon, or other suitable isolation constituent), or combinations thereof. Gate dielectric184C can include a single dielectric layer or multiple dielectric layers depending on design requirements of IC device100. In some implementations, gate dielectric184C includes a low-k dielectric material and/or a high-k dielectric material, such as those described herein (including, but not limited to, SiO2, SiOC, SiON, SiOCN, a carbon-comprising oxide, a nitrogen-comprising oxide, a metal-comprising oxide, hafnium oxide (for example, HfO2), tantalum oxide (for example, Ta2O5), titanium oxide (for example, TiO2), zirconium oxide (for example, ZrO2), aluminum oxide (Al2O3), yttrium oxide (for example, Y2O3), other suitable dielectric material, or combinations thereof). In some implementations, gate dielectric184C is free of metal material, such as that found in gate electrodes186A,186B. Gate dielectric184C is formed by various processes, such as ALD, CVD, PVD, and/or other suitable process, such as described herein. In the depicted embodiment, FinFETs in IC region130A are also physically isolated from FinFETs in IC region130B. For example, upper fin active regions of fins150A-150D are removed underlying gate stack182C, such that upper fin active regions of fins150A-150D do not extend uninterrupted between IC regions130A,130B. In some implementations, fins150A-150D are etched back to remove upper fin active regions of fins150A-150D during a gate replacement process. For example, upper fin active regions of fins150A-150D are removed when the dummy gate is removed from gate structure180F (for example, while removing a dummy gate dielectric). Referring toFIG. 11AandFIG. 11F, upper fin active regions of fins150A,150D of the two-fin p-type FinFET and two-fin n-type FinFET of IC region130A are not physically connected respectively to upper fin active regions of fins150A,150D of the single-fin p-type FinFET and the single-fin n-type FinFET of IC region130B. Accordingly, in contrast to gate dielectrics184A,184B that wrap upper fin active regions of respective fins150A,150D, gate dielectric184C is conformally disposed over isolation layer170and top surfaces of portions of fins150A,150D that are surrounded by isolation layer170, such that gate dielectric184C has a substantially uniform thickness. In some implementations, a portion of upper fin active regions of fins150A,150D may remain underlying gate stack182C, where a top surface of the remaining portion is lower than a top surface of the upper fin active regions of fins150A,150D of the two-fin FinFETs in IC region130A and the single-fin FinFETs in IC region130B. In such implementations, gate stack182C can wrap the remaining portion of upper fin active regions of fins150A,150D (for example, top surfaces and sidewall surfaces).

Gate structures180A-180F are fabricated according to a gate last process, a gate first process, or a hybrid gate last/gate first process. In gate last process implementations, gate structures180A-180F include dummy gate stacks that are subsequently replaced with gate stacks182A, gate stacks182B, and/or gate stacks182C. The dummy gate stacks include, for example, an interfacial layer (including, for example, silicon oxide) and a dummy gate electrode layer (including, for example, polysilicon). In such implementations, the dummy gate electrode layer is removed, thereby forming openings (trenches) in which gate stacks182A-182C are formed. In some implementations, the dummy gate stacks are formed before forming an interlayer dielectric layer, and the dummy gate stacks are replaced with gate stacks182A-182C after forming the interlayer dielectric layer. In some implementations, dummy gate stacks remain in one or more of gate structures180A-180F, such that one or more of gate structures180A-180F include a polysilicon gate. Gate last processes and/or gate first processes can implement deposition processes, lithography processes, etching processes, other suitable processes, or combinations thereof. The deposition processes include CVD, PVD, ALD, high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), PECVD, LPCVD, atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable methods, or combinations thereof. The lithography processes include resist coating (for example, spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the resist, rinsing, drying (for example, hard baking), other suitable processes, or combinations thereof. Alternatively, the lithography exposure process is assisted, implemented, or replaced by other methods, such as maskless lithography, electron-beam writing, or ion-beam writing. The etching processes include dry etching processes, wet etching processes, other etching processes, or combinations thereof.

Gate structures180A-180F further include respective gate spacers188disposed adjacent to (for example, along sidewalls of) gate stacks182A-182C. Gate spacers188are formed by any suitable process and include a dielectric material. The dielectric material can include silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the depicted embodiment, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, can be deposited over substrate110and gate stacks182A-182C and subsequently anisotropically etched to form gate spacers188. In some implementations, gate spacers188include a multi-layer structure, such as a first dielectric layer that includes silicon nitride and a second dielectric layer that includes silicon oxide. In some implementations, gate spacers188include more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers, formed adjacent to the gate stacks. In such implementations, the various sets of spacers can include materials having different etch rates. For example, a first dielectric layer including silicon and oxygen can be deposited over substrate102and gate stacks182A-182C and subsequently anisotropically etched to form a first spacer set adjacent to the gate stacks, and a second dielectric layer including silicon and nitrogen can be deposited over substrate102and gate stacks182A-182C and subsequently anisotropically etched to form a second spacer set adjacent to the first spacer set. Implantation, diffusion, and/or annealing processes may be performed to form lightly doped source and drain (LDD) features and/or heavily doped source and drain (HDD) features (both of which are not shown) in source/drain (S/D) regions of fins150A-150D before and/or after forming gate spacers188.

Source features and drain features (referred to as source/drain features) are formed in source/drain regions of fins150A-150D. For example, semiconductor material is epitaxially grown on fins150A-150D, forming epitaxial source/drain features190A on fins150A-150D in p-type FinFET region106A and epitaxial source/drain features190B on fins150A-150D in n-type FinFET region106B. In the depicted embodiment, a fin recess process (for example, an etch back process) is performed on source/drain regions of fins150A-150D, such that epitaxial source/drain features190A and epitaxial source/drain features190B are grown from bottom portions of fins150A-150D. In some implementations, source/drain regions of fins150A-150D are not subjected to a fin recess process, such that epitaxial source/drain features190A,190B are grown from and wrap at least a portion of upper fin active regions of fins150A-150D. In furtherance of the depicted embodiment, epitaxial source/drain features190A,190B extend (grow) laterally along the x-direction (in some implementations, substantially perpendicular to fins150A-150D), such that epitaxial source/drain features190A,190B are merged epitaxial source/drain features that span more than one fin (for example, epitaxial source/drain features190A span fin150A and fin150B in IC region130A and epitaxial source/drain features190B span fin150C and fin150D in IC region130B). In some implementations, epitaxial source/drain features190A and/or epitaxial source/drain features190B include partially merged portions (with interruption (or gaps) between epitaxial material grown from adjacent fins150A-150D) and/or fully merged portions (without interruption (or gaps) between epitaxial material grown from adjacent fins150A-150D).

An epitaxy process can implement CVD deposition techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxy process can use gaseous and/or liquid precursors, which interact with the composition of fins150A-150D. Epitaxial source/drain features190A,190B are doped with n-type dopants and/or p-type dopants. In the depicted embodiment, epitaxial source/drain features190A,190B are configured depending on a type of FinFET fabricated in their respective FinFET device region. For example, in p-type FinFET region106A, epitaxial source/drain features190A can include epitaxial layers including silicon and/or germanium, where the silicon germanium containing epitaxial layers are doped with boron, carbon, other p-type dopant, or combinations thereof (for example, forming an Si:Ge:B epitaxial layer or an Si:Ge:C epitaxial layer). In furtherance of the example, in n-type FinFET region106B, epitaxial source/drain features190B can include epitaxial layers including silicon and/or carbon, where silicon-containing epitaxial layers or silicon-carbon-containing epitaxial layers are doped with phosphorous, arsenic, other n-type dopant, or combinations thereof (for example, forming an Si:P epitaxial layer, an Si:C epitaxial layer, an Si:As epitaxial layer, or an Si:C:P epitaxial layer). In some implementations, epitaxial source/drain features190A,190B include materials and/or dopants that achieve desired tensile stress and/or compressive stress in the channel regions. In some implementations, epitaxial source/drain features190A,190B are doped during deposition by adding impurities to a source material of the epitaxy process. In some implementations, epitaxial source/drain features190A,190B are doped by an ion implantation process subsequent to a deposition process. In some implementations, annealing processes are performed to activate dopants in epitaxial source/drain features190A, epitaxial source/drain features190B, and/or other source/drain features of IC device100, such as HDD regions and/or LDD regions.

An interlevel dielectric (ILD) layer195is formed over substrate102, particularly over epitaxial source/drain features190A,190B, gate structures180A-180F, and fins150A-150D. In some implementations, ILD layer195is a portion of a multilayer interconnect (MLI) feature that electrically couples various devices (for example, transistors, resistors, capacitors, and/or inductors) and/or components (for example, gate structures and/or source/drain features) of IC device100, such that the various devices and/or components can operate as specified by design requirements of IC device100. ILD layer195includes a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS formed oxide, PSG, BPSG, low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB, SILK (Dow Chemical, Midland, Mich.), polyimide, other low-k dielectric material, or combinations thereof. In some implementations, ILD layer195has a multilayer structure having multiple dielectric materials. In some implementations, a contact etch stop layer (CESL) is disposed between ILD layer195and epitaxial source/drain features190A,190B, fins150A-150D, and/or gate structures180A-180F. The CESL includes a material different than ILD layer195, such as a dielectric material that is different than the dielectric material of ILD layer195. In the depicted embodiment, where ILD layer195includes a low-k dielectric material, the CESL includes silicon and nitrogen (for example, silicon nitride or silicon oxynitride). ILD layer195and/or the CESL are formed over substrate102, for example, by a deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof). In some implementations, ILD layer195is formed by a flowable CVD (FCVD) process that includes, for example, depositing a flowable material (such as a liquid compound) over substrate102and converting the flowable material to a solid material by a suitable technique, such as thermal annealing and/or ultraviolet radiation treating. Subsequent to the deposition of ILD layer195and/or the CESL, a CMP process and/or other planarization process is performed until reaching (exposing) top surfaces of gate stacks182A-182F.

Turning toFIGS. 12A-12F, IC device100can undergo further processing. In some implementations, various contacts of the MLI feature are formed to source/drain regions and/or gate structures of IC device100to facilitate operation of IC device100. The MLI feature includes a combination of dielectric layers and electrically conductive layers (for example, metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect features, such as device-level contacts and/or vias, and/or horizontal interconnect features, such as conductive lines. Vertical interconnect features typically connect horizontal interconnect features in different layers (or different planes) of the MLI feature. During operation of IC device100, the interconnect features are configured to route signals between the devices (here, the p-type FinFETs of p-type FinFET region106A and the n-type FinFETs of n-type FinFET region106B) and/or the components of IC device100and/or distribute signals (for example, clock signals, voltage signals, and/or ground signals) to the devices and/or the components of IC device100. The present disclosure contemplates the MLI feature including any number and/or configuration of dielectric layers and/or conductive layers depending on design requirements of IC device100.

The MLI feature can include additional ILD layers formed over substrate102. In the depicted embodiment, an ILD layer200, which is a portion of the MLI feature, is disposed over ILD layer195and gate structures180A-180F. ILD layer200is similar to ILD layer195. In some implementations, ILD layer200is a first level ILD of the MLI feature (for example, ILD-1). In some implementations, a CESL is disposed between ILD layer200and ILD layer195, which is similar to the CESLs described herein. In furtherance of the depicted embodiment, device-level contacts210A-210J, vias220A-220H, and conductive lines (not shown) (collectively referred to as a metal layer, such as a metal one (M1) layer, of the MLI feature) are disposed in the ILD layers of the MLI feature to form interconnect structures. Device-level contacts210A-210J, vias220A-220H, and conductive lines include any suitable electrically conductive material, such as Ta, Ti, Al, Cu, Co, Ru, W, TiN, TaN, other suitable conductive materials, or combinations thereof. Various conductive materials can be combined to provide device-level contacts210A-210J, vias220A-220H, and/or conductive lines with various layers, such as one or more barrier layers, adhesion layers, liner layers, bulk layers, other suitable layers, or combinations thereof. In some implementations, device-level-contacts210A-210J include Ti, TiN, and/or Co; vias220A-220H include Ti, TiN, and/or W; and conductive lines include Cu, Co, and/or Ru. Device-level contacts210A-210J, vias220A-220H, and conductive lines are formed by patterning ILD layer195, ILD layer200, and/or other ILD layers of the MLI feature. Patterning the ILD layers can include lithography processes and/or etching processes to form openings (trenches), such as contact openings, via openings, and/or line openings in respective ILD layers. In some implementations, the lithography processes include forming a resist layer over respective ILD layers, exposing the resist layer to patterned radiation, and developing the exposed resist layer, thereby forming a patterned resist layer that can be used as a masking element for etching opening(s) in respective ILD layers. The etching processes include dry etching processes, wet etching processes, other etching processes, or combinations thereof. Thereafter, the opening(s) are filled with one or more conductive materials. The conductive material(s) can be deposited by PVD, CVD, ALD, electroplating, electroless plating, other suitable deposition process, or combinations thereof. Thereafter, any excess conductive material(s) can be removed by a planarization process, such as a CMP process, thereby planarizing a top surface of the ILD layers (for example, ILD layer200), device-level contacts210A-210J, vias220A-220H, and/or conductive lines.

Device-level contacts210A-210J (also referred to as local interconnects or local contacts) electrically couple and/or physically couple IC device features, such as features of the p-type FinFETs of p-type FinFET region106A and the n-type FinFETs of n-type FinFET region106B to the MLI feature. For example, device-level contacts210A-210J are metal-to-device (MD) contacts, which generally refer to contacts to a conductive region, such as source/drain regions, of IC device100. Device-level contacts210A-210E are disposed on respective epitaxial source/drain features190A, such that device-level contacts210A-210E physically (or directly) connect the source/drain regions of the p-type FinFETs of p-type FinFET region106A to the MLI feature (for example, to respective vias220A-220D); and device-level contacts210F-210J are disposed on respective epitaxial source/drain features190B, such that device-level contacts210F-210J physically (or directly) connect the source/drain regions of the n-type FinFETs of n-type FinFET region106B to the MLI feature (for example, to respective vias220E-220H). Vias220A-220D are disposed respectively on device-level contacts210A-210C and device-level contact210E, such that vias220A-220D physically (or directly) respectively connect device-level contacts210A-210C and device-level contact210E to a conductive line of the MLI feature; and vias220E-220H are disposed respectively on device-level contacts210F-210H and device-level contact210J, such that vias220E-220H physically (or directly) respectively connect device-level contacts210F-210H and device-level contact210J to a conductive line of the MLI feature. Device-level contacts210A-210J and vias220A-220H extend through ILD layer200and/or ILD layer195, though the present disclosure contemplates embodiments where device-level contacts210A-210J and vias220A-220H extend through more or less ILD layers and/or CESLs of the MLI feature. The present disclosure contemplates any configuration of device-level contacts, vias, and/or conductive lines.

In some implementations, the MLI feature includes a device-level contact that is a gate contact (CG) or metal-to-poly (MP) contact, which generally refers to a contact to a gate structure, such as a poly gate structure or a metal gate structure of IC device100. Such device-level contacts electrically couple and/or physically couple one or more of gate structures180A-180F to the MLI feature. In some implementations, one or more of gate structures180A-180F have a device-level contact disposed thereon, such that the device-level contact physically (or directly) respectively connects the respective one of gate structures180A-180F to the MLI feature (for example, to respective vias). In some implementations, the MLI feature includes vias that electrically couple and/or physically couple one or more of gate structures180A-180F to the MLI feature. In such implementations, the vias are disposed on gate structures180A-180F or the device-level contacts connected to the one or more of gate structures180A-180F, such that the vias physically (or directly) and/or electrically connect respective gate structures180A-180F to the MLI feature (for example, to respective conductive lines). Device-level contacts and vias to gate structures180A-180F extend through ILD layer200and/or ILD layer195, though the present disclosure contemplates embodiments where such device-level contacts and vias extend through more or less ILD layers and/or CESLs of the MLI feature.

In some implementations, silicide layers are disposed between epitaxial source/drain features190A,190B and device-level contacts215A-215D. In some implementations, silicide layers230are formed by depositing a metal layer over epitaxial source/drain features190A,190B before or after forming ILD layer195and/or ILD layer200. The metal layer includes any material suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metal, or combinations thereof. IC device100is then heated (for example, subjected to an annealing process) to cause constituents of epitaxial source/drain features190A,190B (for example, silicon and/or germanium) to react with the metal. Silicide layers230thus include metal and a constituent of epitaxial source/drain features190A,190B (for example, silicon and/or germanium). In some implementations, silicide layers230include nickel silicide, titanium silicide, or cobalt silicide. Any un-reacted metal, such as remaining portions of the metal layer, is selectively removed by any suitable process, such as an etching process. In some implementations, silicide layers230and epitaxial source/drain features190A,190B are collectively referred to as the epitaxial source/drain features. In some implementations, silicide layers230are considered a portion of device-level contacts215A-215D.

InFIGS. 12A-12F, IC region130A is a first circuit that includes a CMOS FET that includes a two-fin p-type FinFET in p-type FinFET region106A and a two-fin n-type FinFET in n-type FinFET region106B, and IC region130B is a second circuit that includes a CMOS FET that includes a single-fin p-type FinFET in p-type FinFET region106A and a single-fin n-type FinFET in n-type FinFET region106B. The two-fin p-type FinFET includes gate structure180B disposed over a channel region of fins150A,150B, such that gate structure180B is disposed between source/drain regions of fins150A,150B; and the two-fin n-type FinFET includes gate structure180B disposed over a channel region of fins150C,150D, such that gate structure180B is disposed between source/drain regions of fins150C,150D. Epitaxial source/drain features190A are disposed over source/drain regions of fins150A,150B, and epitaxial source/drain features190B are disposed over source/drain regions of fins150C,150D. The single-fin p-type FinFET includes gate structure180C disposed over a channel region of fin150A, such that gate structure180C is disposed between source/drain regions of fin150A; and the single-fin n-type FinFET includes gate structure180C disposed over a channel region of fin150D, such that gate structure180C is disposed between source/drain regions of fin150D. Epitaxial source/drain features190A are disposed over source/drain regions of fin150A, and epitaxial source/drain features190B are disposed over source/drain regions of fin150D. In the depicted embodiment, IC device100is configured such that via220A and device-level contact210A are connected to a source node of the single-fin p-type FinFET, via220B and device-level contact210B are connected to a drain node of the single-fin p-type FinFET, via220C and device-level contact210C are connected to a drain node of the two-fin p-type FinFET, via220D and device-level contact210E are connected to a source node of the two-fin p-type FinFET, via220E and device-level contact210F are connected to a source node of the single-fin n-type FinFET, via220F and device-level contact210G are connected to a drain node of the single-fin n-type FinFET, via220G and device-level contact210H are connected to a drain node of the two-fin n-type FinFET, and via220H and device-level contact210J are connected to a source node of the two-fin n-type FinFET. In such configuration, the first circuit is disposed directly adjacent to and abuts the second circuit, and gate structure180F isolates drain nodes of the two-fin FinFETs in the first circuit from drain nodes of the single-fin FinFETs in the second circuit. IC device100is further configured with source nodes of the p-type FinFETs in p-type FinFET region106A electrically connected to a power supply voltage VDD(in some implementations, configured as a positive supply voltage) vias220A,220D and device-level contacts210A,210E and source nodes of the n-type FinFETs in n-type FinFET region106B electrically connected to a power supply voltage VSS(in some implementations, configured as ground and/or a negative supply voltage) by vias220E,220H and device-level contacts210F,210J. Gate structure180D isolates the two-fin p-type FinFET and the two-fin n-type FinFET in IC region130A from other adjacent circuits of IC device100, gate structure180E isolates the single-fin p-type FinFET and the single-fin n-type FinFET in IC region130B from other adjacent circuits of IC device100, and gate structure180F isolates the two-fin p-type FinFET and the two-fin n-type FinFET in IC region130A respectively from the single-fin p-type FinFET and the single-fin n-type FinFET in IC region130B.

In some implementations, contacts to the drain nodes of the two-fin FinFETs are configured differently than contacts to the drain nodes of the single-fin FinFETs. InFIGS. 12A-12F, device-level contacts210C,210H to the drain nodes of the two-fin FinFETs and device-level contacts210B,210G to the drain nodes of the single-fin FinFETs have rectangular-shaped cross-sections in an x-y plane, such that device-level contacts210C,210H to the drain nodes of the two-fin FinFETs and device-level contacts210B,210G to the drain nodes of the single-fin FinFETs have a length along the x-direction (and substantially parallel to a gate length direction) and a width along the y-direction (and substantially parallel to a fin length direction). In some implementations, device-level contacts210C,210H have a length X1and a width Y1, and device-level contacts210B,210G have a length X2and a width Y2, where length X1is greater than length X2. It has been observed that implementing longer contacts for two-fin FinFET devices, which have higher on-current (Ion), reduces contact resistance, while implementing shorter contacts for single-fin FinFET devices, which have lower on-current (Ion) and often serve low power and/or low speed circuits, lowers capacitance (for example, contact to gate) that enables power reduction. In some implementations, a ratio of length X1to length X2is about 1.1 to about 1.6 (1.1≤X1:X2≤1.6.), and width Y1is substantially the same as width Y2. In some implementations, the ratio of length X1to length X2is about 1.1 to about 1.6 (1.1≤X1:X2≤1.6.), and width Y1is less than width Y2. In such implementations, a ratio of width Y2to width Y1can be about 1.05 to about 1.1 (1.05≤Y2:Y1≤1.1). In some implementations, a maximum width of device-level contacts210C,210H is greater than a maximum width of device-level contacts210B,210G by at least 10% (in other words, Y2≤0.9*Y1).

In some implementations, the first circuit (IC region130A) and the second circuit (IC region130B) are each a standard cell having a predetermined function. For example, the transistors and interconnect (or routing) structures of the IC region130A and/or IC region130B can combine to provide a logic function (for example, AND, NAND, OR, NOR, NOT, XOR, and/or XNOR) and/or a storage function (for example, flip flop, latch, and/or buffer). Implementing the fin fabrication methods disclosed herein allows for IC device100to have a standard cell structure that arranges standard cells having even number of fins FinFETs (for example, two-fin FinFETs in IC region130A) directly adjacent to and abutting standard cells having odd number of fins FinFETs (for example, single-fin FinFETs in IC region130B), along with a standard cell structure that arranges standard cells configured for high speed applications directly adjacent to and abutting standard cells configured for low power consumption applications. Such standard cell structures enable SoC products that can offer high speed performance with low power consumption. In some implementations, the first circuit and the second circuit are a portion of a memory cell for storing a bit of data of a memory array, such as static random access memory (SRAM) array, which often incorporates FinFETs to enhance performance. In some implementations, the first circuit is in a core (logic) region of an IC device, and the second circuit is in an input/output (I/O) region of the IC device.

FIG. 13is a simplified schematic top view of an IC device300(for example, in an x-y plane), in portion or entirety, according to various aspects of the present disclosure. IC device300is similar in many respects to IC device100. Accordingly, similar features inFIG. 13andFIGS. 12A-12Fare identified by the same reference numerals for clarity and simplicity. InFIG. 13, IC device300has a different configuration of dummy gate structures than IC device100. For example, gate structure180D and gate structure180E include gate stacks182C that span p-type FinFET region106A and n-type FinFET region106B in IC device300, instead of gate stacks182A in p-type FinFET region106A and n-type FinFET region106B. Gate structure180D electrically isolates source/drain regions of the two-fin FinFETs (which include gate structures180A,180B) in IC region130A from other devices and/or regions of IC device300. Gate structure180E electrically isolates source/drain region of the single-fin FinFETs (which include gate structure180C) in IC region130B from other devices and/or regions of IC device300. IC device300can be fabricated using the fabrication processes described herein with reference toFIG. 1,FIGS. 2A-2C, 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C,FIGS. 11A-11F, andFIGS. 12A-12F.FIG. 13has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in IC device300, and some of the features described below can be replaced, modified, or eliminated in other embodiments of IC device300.

FIG. 14is a simplified schematic top view of an IC device400(for example, in an x-y plane), in portion or entirety, according to various aspects of the present disclosure. IC device400is similar in many respects to IC device100. Accordingly, similar features inFIG. 14andFIGS. 12A-12Fare identified by the same reference numerals for clarity and simplicity. InFIG. 14, IC device400has a different configuration of dummy gate structures than IC device100. For example, dummy gate structure180F includes gate stack182A in p-type FinFET region106A and gate stack182B in n-type FinFET region106B, instead of gate stack182C spanning p-type FinFET region106A and n-type FinFET region106B. Gate stack182A and gate stack182B are surrounded by gate spacers188, such that gate stack182A and gate stack182B are physically and electrically separated from each other. Gate stack182A is electrically connected to a power supply voltage VDD(in some implementations, configured as a positive supply voltage), and gate stack182B is electrically connected to a power supply voltage VSS(in some implementations, configured as ground and/or a negative supply voltage). Gate stack182and gate stack182B are respectively electrically connected to power supply voltage VDDand power supply voltage VSSby device-level contacts (not shown), vias (not shown), and/or metal lines (not shown) of the MLI feature. In such configuration, IC device400includes isolation MOSFETs that electrically isolate the first circuit of IC region130A from the second circuit of IC region130B. For example, an isolation MOSFET in p-type FinFET region106A includes a portion of gate structure180F including gate stack182A disposed over fins150A,150B, such that gate stack182A is disposed between source/drain regions of fins150A,150B in IC region130A and a source/drain region of fin150A in IC region130B. Epitaxial source/drain features190A are disposed over source/drain regions of fins150A,150B in IC regions130A,130B. In some implementations, upper fin active region of fin150A of the two-fin p-type FinFET is not physically isolated or separated from the upper fin active region of fin150A of the single-fin p-type FinFET, such that that fin150A extends continuously between IC regions130A,130B. In furtherance of the example, an isolation MOSFET in n-type FinFET region106B includes a portion of gate structure180F including gate stack182B disposed over fins150C,150D, such that gate stack182B is disposed between source/drain regions of fins150C,150D in IC region130A and a source/drain region of fin150D in IC region130B. Epitaxial source/drain features190B are disposed over source/drain regions of fins150C,150D in IC regions130A,130B. In some implementations, upper fin active region of fin150D of the two-fin n-type FinFET is not physically isolated or separated from the upper fin active region of fin150D of the single-fin n-type FinFET, such that that fin150D extends continuously between IC regions130A,130B. IC device400can be fabricated using the fabrication processes described herein with reference toFIG. 1,FIGS. 2A-2C, 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C,FIGS. 11A-11F, andFIGS. 12A-12F.FIG. 14has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in IC device400, and some of the features described below can be replaced, modified, or eliminated in other embodiments of IC device400.

FIGS. 15A-15Fare fragmentary diagrammatic views of an IC device500, in portion or entirety, according to various aspects of the present disclosure. In particular,FIG. 15Ais a simplified schematic top view of IC device500;FIG. 15Bis a diagrammatic cross-sectional view of IC device500along line B-B ofFIG. 15A;FIG. 15Cis a diagrammatic cross-sectional view of IC device500along line C-C ofFIG. 15A;FIG. 15Dis a diagrammatic cross-sectional view of IC device500along line D-D ofFIG. 15A;FIG. 15Eis a diagrammatic cross-sectional view of IC device500along line E-E ofFIG. 15A; andFIG. 15Fis a diagrammatic cross-sectional view of IC device500along line F-F ofFIG. 15A. IC device500is similar in many respects to IC device100. Accordingly, similar features inFIGS. 15A-15FandFIGS. 12A-12Fare identified by the same reference numerals for clarity and simplicity. InFIGS. 15A-15F, IC device500has a different configuration of FinFETs than IC device100. For example, in IC device500, the second circuit of IC region130B includes a CMOS FET that includes a two-fin p-type FinFET in p-type FinFET region106A, instead of a single-fin p-type FinFET, and a single-fin n-type FinFET in n-type FinFET region106B. The two-fin p-type includes gate structure180C disposed over a channel region of fins150A,150B in IC region130B, such that gate structure180C is disposed between source/drain regions of fins150A,150B in IC region130B. Epitaxial source/drain features190A are disposed over the source/drain regions of fins150A,150B in IC region130A. Device-level contacts210A,210B are also configured with different dimensions in IC device500. For example, device-level contact210A to the source node of the two-fin p-type FinFET in IC region130B is configured similar as device-level contact210E to the source node of the two-fin p-type FinFET in IC region130A, and device-level contact210B to the drain node of the two-fin p-type FinFET in IC region130B is configured similar as device-level contact210C to the drain node of the two-fin p-type FinFET in IC region130A. For example, device-level contacts210A,210B span over and extend beyond fins150A,150B in IC region130B. In some implementations, device-level contact210B has a length that is substantially equal to length X1of device-level contact210C and a width that is substantially equal to width Y1of device-level contact210C. IC device500can be fabricated using the fabrication processes described herein with reference toFIG. 1,FIGS. 2A-2C, 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C,FIGS. 11A-11F, andFIGS. 12A-12F. During fabrication, a width of dummy pattern122would be substantially the same between fin150A and150B in IC regions130A,130B, such that spacing between fins150A,150B in IC regions130A,130B is the same in p-type FinFET region106A. For example, in p-type FinFET region106A, fin150A and fin150B have spacing S3in IC region130A and IC region130B.FIGS. 15A-15Chave been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in IC device500, and some of the features described below can be replaced, modified, or eliminated in other embodiments of IC device500.

FIGS. 16A-16Care fragmentary diagrammatic views of an IC device600, in portion or entirety, according to various aspects of the present disclosure. In particular,FIG. 16Ais a simplified schematic top view of IC device600;FIG. 16Bis a diagrammatic cross-sectional view of IC device600along line B-B ofFIG. 16A;FIG. 16Cis a diagrammatic cross-sectional view of IC device600along line C-C ofFIG. 16A;FIG. 16Dis a diagrammatic cross-sectional view of IC device600along line D-D ofFIG. 16A;FIG. 16Eis a diagrammatic cross-sectional view of IC device600along line E-E ofFIG. 16A; andFIG. 16Fis a diagrammatic cross-sectional view of IC device600along line F-F ofFIG. 16A. IC device600is similar in many respects to IC device100. Accordingly, similar features inFIGS. 16A-16FandFIGS. 12A-12Fare identified by the same reference numerals for clarity and simplicity. InFIGS. 16A-16F, IC device600has a different configuration of FinFETs than IC device100. For example, in IC device600, the second circuit of IC region130B includes a CMOS FET that includes a two-fin n-type FinFET in n-type FinFET region106B, instead of a single-fin n-type FinFET, and a single-fin p-type FinFET in p-type FinFET region106A. The two-fin n-type includes gate structure180C disposed over a channel region of fins150C,150D in IC region130B, such that gate structure180C is disposed between source/drain regions of fins150C,150D in IC region130B. Epitaxial source/drain features190B are disposed over the source/drain regions of fins150C,150D in IC region130A. Device-level contacts210F,210G are also configured with different dimensions in IC device600. For example, device-level contact210F to the source node of the two-fin n-type FinFET in IC region130B is configured similar as device-level contact210J to the source node of the two-fin n-type FinFET in IC region130A, and device-level contact210G to the drain node of the two-fin n-type FinFET in IC region130B is configured similar as device-level contact210H to the drain node of the two-fin n-type FinFET in IC region130A. For example, device-level contacts210F,210G span over and extend beyond fins150C,150D in IC region130B. In some implementations, device-level contact210G has a length that is substantially equal to length X1of device-level contact210H and a width that is substantially equal to width Y1of device-level contact210H. IC device600can be fabricated using the fabrication processes described herein with reference toFIG. 1,FIGS. 2A-2C, 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C,FIGS. 11A-11F, andFIGS. 12A-12F. During fabrication, a width of dummy pattern124would be substantially the same between fin150C and150D in IC regions130A,130B, such that spacing between fins150C,150D in IC regions130A,130B is the same in n-type FinFET region106B. For example, in n-type FinFET region106B, fin150C and fin150C have spacing S3in IC region130A and IC region130B.FIGS. 16A-16Chave been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in IC device600, and some of the features described below can be replaced, modified, or eliminated in other embodiments of IC device600.

FIG. 17is a simplified block diagram of an IC design layout700, in portion or entirety, according to various aspects of the present disclosure. IC design layout700includes an array of standard cells, such as a standard cell710A, a standard cell710B, a standard cell710C, a standard cell710D, a standard cell710E, a standard cell710F, a standard cell710G, a standard cell710H, a standard cell710I, and a standard cell710J. Each of standard cells710A-710J includes transistors and interconnect (or routing) structures that combine to form a circuit that provides a logic function (for example, AND, NAND, OR, NOR, NOT, XOR, and/or XNOR) and/or a storage function (for example, flip flop, latch, and/or buffer). For example, standard cells710A-710J respectively provide circuits1-10. In the depicted embodiment, standard cells710A,710C,710F,710H, and710J include single-fin FinFETs, and standard cells710A,710D,710D,710G, and710I include two-fin FinFETs. The fin patterning methods described herein allow for standard cells configured with multi-fin FinFETs (implemented, for example, for high speed applications) to be arranged directly adjacent to and abutting standard cells configured for single-fin FinFETs (implemented, for example, for low power consumption). For example, standard cell710H is disposed directly adjacent to and abutting standard cells710G,710I, which include two-fin FinFETs, and standard cell710C, which includes single-fin FinFETs. Standard cells710A-710J are arranged to overlap an n-type well region720A, a p-type well region720B, and/or an n-type well region720C, such that p-type FinFET regions of standard cells710A-710J (which include p-type FinFETs) are disposed over n-type well region720A and/or n-type well region720C and n-type FinFET regions of standard cells710A-710J (which include n-type FinFETs) are disposed over p-type well region720B.FIG. 17has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in IC design layout700, and some of the features described below can be replaced, modified, or eliminated in other embodiments of IC design layout700.

The present disclosure provides for many different embodiments. Fin patterning methods are disclosed herein for improving FinFET performance and improving FinFET fabrication. An exemplary method includes forming a dummy pattern over a substrate. The dummy pattern has a first width in a first region corresponding with a first FinFET and a second width in a second region corresponding with a second FinFET. The second width is greater than the first width. The method further includes forming spacers along sidewalls of the dummy pattern and removing the dummy pattern, thereby forming a spacer pattern having a first spacing between spacers in the first region and a second spacing between spacers in the second region. The second spacing is greater than the first spacing. The method further includes transferring the spacer pattern to the substrate, thereby forming a first fin and a second fin separated by the first spacing in the first region and separated by the second spacing in the second region. The method further includes partially removing the second fin from the second region to form a dummy fin tip. The first fin and the dummy fin tip are separated by a spacing that is greater than the first spacing, such as the second spacing. In some implementations, a ratio of the second spacing to the first spacing is about 1.05 to about 2.

In some implementations, the method further includes forming an isolation feature over the substrate, wherein the isolation feature is disposed between the first fin and the second fin and the third fin and the dummy feature. In some implementations, forming the isolation feature includes depositing a dielectric material over the substrate and etching back the dielectric material, such that a portion of the first fin, the second fin, and the third fin extend above a top surface of the isolation feature. In some implementations, the method further includes forming a first gate structure that traverses the first fin and the second fin and forming a second gate structure that traverses the third fin. In some implementations, the second gate structure extends over the dummy feature and an isolation feature is disposed between the second gate structure and the dummy feature.

In some implementations, forming the dummy pattern includes depositing a dummy layer over the substrate, performing a lithography process to expose a portion of the dummy layer, and etching the exposed portion the dummy layer. In some implementations, the dummy layer includes a dielectric material. In some implementations, the dummy layer includes oxygen, nitrogen, carbon, or combinations thereof. In some implementations, performing the lithography process includes forming a patterned masking layer over the dummy layer, wherein the patterned masking layer includes a masking line having a width that increases from the first region to the second region. In some implementations, forming the spacers includes depositing a spacer layer over the substrate and etching the spacer layer. In some implementations, forming the spacers further includes performing a lithography process to expose a portion of the spacer layer and etching the exposed portion of the spacer layer. In some implementations, the spacer layer includes a dielectric material. In some implementations, the spacer layer includes oxygen, nitrogen, carbon, or combinations thereof.

In some implementations, removing the dummy pattern includes selectively etching the dummy pattern without substantial etching of the spacers. In some implementations, transferring the spacer pattern to the underlying layer includes etching the underlying layer using the spacer pattern as an etching mask. In some implementations, the method further includes removing any remaining spacer pattern after the etching. In some implementations, partially removing the fourth fin from the second region includes forming a patterned masking layer that exposes the fourth fin while covering the first fin, the second fin, and the third fin and etching the exposed fourth fin.

Another exemplary method includes forming a first mandrel and a second mandrel over a substrate. The first mandrel and the second mandrel have a first spacing therebetween in a first region corresponding with a first FinFET device and a second spacing therebetween in a second region corresponding with a second FinFET device. The second spacing is greater than the first spacing. The method further includes patterning an underlying layer using the first mandrel and the second mandrel, thereby forming a first fin and a second fin. The first fin and the second fin have the first spacing therebetween in the first region and the second spacing therebetween in the second region. The method further includes partially removing the second fin from the second region. The method further includes forming an isolation structure that electrically isolates a portion of the first fin in the first region from a portion of the first fin in the second region. In some implementations, a ratio of the second spacing to the first spacing is about 1.05 to about 2.

An exemplary integrated circuit device includes a first FinFET that includes a first fin structure having a first fin and a second fin separated by a first spacing and a second FinFET that includes a second fin structure having a third fin and a dummy structure separated by a second spacing. The second spacing is greater than the first spacing. An isolation structure is disposed between the first FinFET and the second FinFET, such that the isolation structure isolates the first fin structure from the second fin structure. In some implementations, a ratio of the first spacing to the second spacing is about 1.05 to about 2. In some implementations, a height of the dummy structure is less than a height of the third fin. In some implementations, the height of the dummy structure is at least 70 nm less than the height of the third fin. In some implementations, the height of the dummy structure is less than or equal to about 30 nm. In some implementations, a length of the dummy structure is about the same as a length of the third fin. In some implementations, the isolation structure is a dummy gate structure that physically separates the first fin from the third fin. In some implementations, the isolation structure is a gate structure that electrically separates source/drain features of the first fin from source/drain features of the third fin.

In some implementations, the first FinFET includes a first gate structure that traverses the first fin structure, such that the first gate structure is disposed between first source/drain features of the first fin and the second fin, and the second FinFET includes a second gate structure that traverses the second fin structure, such that the second gate structure is disposed between second source/drain features of the third fin and disposed over the dummy structure. In some implementations, the first fin, the second fin, the third fin, and the dummy structure extend along a first direction, and the first gate structure and the second gate structure extend along a second direction that is substantially perpendicular to the first direction.

In some implementations, the first fin, the second fin, the third fin, and the dummy structure extend along a first direction. In such implementation, the integrated circuit device can further include a first contact to source/drain features of the first fin and the second fin and a second contact to source/drain features of the third fin. The first contact has a first dimension along the first direction and a second dimension along a second direction, wherein the second direction is substantially parallel to the first direction. The second contact has a third dimension along the first direction and a fourth dimension along the second direction. The second dimension is greater than the fourth dimension. In some implementations, a ratio of the second dimension to the fourth dimension is about 1.1 to about 1.6. In some implementations, the first dimension is substantially the same as the third dimension. In some implementations, the first contact overlaps the first fin and the second fin. In some implementations, the second contact does not overlap the dummy structure.

Another exemplary method includes generating a dummy pattern layout for use in fabricating a first FinFET device and a second FinFET device. The dummy pattern includes a dummy line that spans a first region corresponding with the first FinFET device and a second region corresponding with the second FinFET device. The dummy line has a width that is substantially equal to a desired pitch between fins of the first FinFET device. The method further includes inserting a jog pattern into the dummy pattern layout, thereby modifying the dummy pattern layout. The jog pattern includes a jog line disposed adjacent to the dummy line in the second region, such that a sum of the width of the dummy line and a width of the jog line is greater than the width of the dummy line. The method further includes fabricating a mask using the modified dummy pattern layout. In some implementations, the method further includes generating a cut pattern layout for use in fabricating the first FinFET device and the second FinFET device. The cut pattern layout is generated based on the modified dummy pattern layout. The cut pattern layout includes a cut pattern having an opening that overlaps the jog line. In such implementations, the method further includes fabricating a cut mask using the cut pattern layout. In some implementations, the first region corresponds with an area of an IC device that includes FinFET devices having an even number of fins, and the second region corresponds with an area of the IC device that includes FinFET devices having an odd number of fins. In some implementations, the second region corresponds with a fin removal area.