Semiconductor device and method of forming high-frequency circuit structure and method thereof

A semiconductor device is made by providing an integrated passive device (IPD). Through-silicon vias (TSVs) are formed in the IPD. A capacitor is formed over a surface of the IPD by depositing a first metal layer over the IPD, depositing a resistive layer over the first metal layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the resistive and dielectric layers. The first metal layer and the resistive layer are electrically connected to form a resistor and the first metal layer forms a first inductor. A wafer supporter is mounted over the IPD using an adhesive material and a third metal layer is deposited over the IPD. The third metal layer forms a second inductor that is electrically connected to the capacitor and the resistor by the TSVs of the IPD. An interconnect structure is connected to the IPD.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device having an integrated passive device (IPD) connected to an inductor and capacitor formed over the IPD.

BACKGROUND OF THE INVENTION

Semiconductor devices perform a wide range of functions such as high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power generation, networks, computers, and consumer products. Semiconductor devices are also found in electronic products including military, aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or through the process of doping. Doping introduces impurities into the semiconductor material.

A semiconductor device contains active and passive electrical structures. Active structures, including transistors, control the flow of electrical current. By varying levels of doping and application of an electric field, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, diodes, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form logic circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size may be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

In most applications, semiconductor devices use one or more inductors and capacitors to implement the device's filters and to provide system functionality. In some packages, the inductors and capacitors are provided as part of a pre-fabricated integrated passive device (IPD) that is mounted to the semiconductor device and electrically connected to the other components of the semiconductor device. Unfortunately, the two-dimensional layout of an IPD limits the capacity of capacitors and inductors formed within its substrate. In applications requiring relatively large capacitors and inductors, therefore, it is difficult to provide the necessary inductors and capacitors within the IPD itself.

SUMMARY OF THE INVENTION

In one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing an integrated passive device (IPD), forming through-silicon vias (TSVs) in the IPD, and forming a capacitor over a surface of the IPD. The capacitor is formed by depositing a first metal layer over the IPD, depositing a resistive layer over the first metal layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the resistive and dielectric layers. The first metal layer and the resistive layer are electrically connected to form a resistor and the first metal layer forms a first inductor. The method includes mounting a wafer supporter over the IPD using an adhesive material, and depositing a third metal layer over the IPD. The third metal layer forms a second inductor. The second inductor is electrically connected to the capacitor and the resistor by the TSVs of the IPD. The method includes connecting an interconnect structure to the IPD.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing an integrated passive device (IPD) having a plurality of through-silicon vias (TSVs), and forming a capacitor over a first surface of the IPD. The capacitor is electrically connected to a TSV of the IPD. The method includes forming a resistor over the first surface of the IPD. The resistor is electrically connected to the capacitor. The method includes forming an inductor over a second surface of the IPD opposite the first surface. The inductor is electrically connected to the capacitor and the resistor by the TSVs of the IPD. The method includes connecting an interconnect structure to the IPD.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate having a through substrate via, and forming a capacitor over a first surface of the substrate. The capacitor is connected to the via. The method includes forming an inductor over a second surface of the substrate opposite the first surface. The inductor is connected to the capacitor by the through substrate via.

In another embodiment, the present invention is a semiconductor device comprising an integrated passive device (IPD) having a through-silicon via (TSV), and a capacitor formed over a first surface of the IPD. The capacitor is electrically connected to the TSV of the IPD. The device includes a resistor formed over the first surface of the IPD. The resistor is electrically connected to the capacitor. The device includes an inductor formed over a second surface of the IPD opposite the first surface. The inductor is electrically connected to the capacitor and the resistor by the TSV of the IPD. The device includes an interconnect structure connected to the IPD.

DETAILED DESCRIPTION OF THE DRAWINGS

Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.

Passive and active components are formed on the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into a permanent insulator, permanent conductor, or changing the way the semiconductor material changes in conductivity in response to an electric field. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of an electric field.

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electrolytic plating.

FIG. 1illustrates electronic device10having a chip carrier substrate or printed circuit board (PCB)12with a plurality of semiconductor packages mounted on its surface. Electronic device10may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1for purposes of illustration.

Electronic device10may be a stand-alone system that uses the semiconductor packages to perform an electrical function. Alternatively, electronic device10may be a subcomponent of a larger system. For example, electronic device10may be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.

InFIG. 1, PCB12provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces14are formed on a surface or within layers of PCB12using evaporation, electrolytic plating, electroless plating, screen printing, PVD, or other suitable metal deposition process. Signal traces14provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces14also provide power and ground connections to each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels. First level packaging is the technique for mechanically and electrically attaching the semiconductor die to a carrier. Second level packaging involves mechanically and electrically attaching the carrier to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB.

For the purpose of illustration, several types of first level packaging, including wire bond package16and flip chip18, are shown on PCB12. Additionally, several types of second level packaging, including ball grid array (BGA)20, bump chip carrier (BCC)22, dual in-line package (DIP)24, land grid array (LGA)26, multi-chip module (MCM)28, quad flat non-leaded package (QFN)30, and quad flat package32, are shown mounted on PCB12. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB12. In some embodiments, electronic device10includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using cheaper components and a shorter manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in lower costs for consumers.

FIG. 2aillustrates further detail of DIP24mounted on PCB12. DIP24includes semiconductor die34having contact pads36. Semiconductor die34includes an active area containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within semiconductor die34and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active area of die34. Contact pads36are made with a conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within die34. Contact pads36are formed by PVD, CVD, electrolytic plating, or electroless plating process. During assembly of DIP24, semiconductor die34is mounted to a carrier38using a gold-silicon eutectic layer or adhesive material such as thermal epoxy. The package body includes an insulative packaging material such as plastic or ceramic. Conductor leads40are connected to carrier38and wire bonds42are formed between leads40and contact pads36of die34as a first level packaging. Encapsulant44is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating die34, contact pads36, or wire bonds42. DIP24is connected to PCB12by inserting leads40into holes formed through PCB12. Solder material46is flowed around leads40and into the holes to physically and electrically connect DIP24to PCB12. Solder material46can be any metal or electrically conductive material, e.g., Sn, lead (Pb), Au, Ag, Cu, zinc (Zn), bismuthinite (Bi), and alloys thereof, with an optional flux material. For example, the solder material can be eutectic Sn/Pb, high-lead, or lead-free.

FIG. 2billustrates further detail of BCC22mounted on PCB12. Semiconductor die16is connected to a carrier by wire bond style first level packaging. BCC22is mounted to PCB12with a BCC style second level packaging. Semiconductor die16having contact pads48is mounted over a carrier using an underfill or epoxy-resin adhesive material50. Semiconductor die16includes an active area containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within semiconductor die16and are electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active area of die16. Contact pads48are made with a conductive material, such as Al, Cu, Sn, Ni, Au, or Ag, and are electrically connected to the circuit elements formed within die16. Contact pads48are formed by PVD, CVD, electrolytic plating, or electroless plating process. Wire bonds54and bond pads56and58electrically connect contact pads48of semiconductor die16to contact pads52of BCC22forming the first level packaging. Molding compound or encapsulant60is deposited over semiconductor die16, wire bonds54, contact pads48, and contact pads52to provide physical support and electrical isolation for the device. Contact pads64are formed on a surface of PCB12using evaporation, electrolytic plating, electroless plating, screen printing, PVD, or other suitable metal deposition process and are typically plated to prevent oxidation. Contact pads64electrically connect to one or more conductive signal traces14. Solder material is deposited between contact pads52of BCC22and contact pads64of PCB12. The solder material is reflowed to form bumps66which form a mechanical and electrical connection between BCC22and PCB12.

InFIG. 2c, semiconductor die18is mounted face down to carrier76with a flip chip style first level packaging. BGA20is attached to PCB12with a BGA style second level packaging. Active area70containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within semiconductor die18is electrically interconnected according to the electrical design of the die. For example, the circuit may include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within active area70of semiconductor die18. Semiconductor die18is electrically and mechanically attached to the carrier76through a large number of individual conductive solder bumps or balls78. Solder bumps78are formed on bump pads or interconnect sites80, which are disposed on active areas70. Bump pads80are made with a conductive material, such as Al, Cu, Sn, Ni, Au, or Ag, and are electrically connected to the circuit elements formed in active area70. Bump pads80are formed by PVD, CVD, electrolytic plating, or electroless plating process. Solder bumps78are electrically and mechanically connected to contact pads or interconnect sites82on carrier76by a solder reflow process.

BGA20is electrically and mechanically attached to PCB12by a large number of individual conductive solder bumps or balls86. The solder bumps are formed on bump pads or interconnect sites84. The bump pads84are electrically connected to interconnect sites82through conductive lines90routed through carrier76. Contact pads88are formed on a surface of PCB12using evaporation, electrolytic plating, electroless plating, screen printing, PVD, or other suitable metal deposition process and are typically plated to prevent oxidation. Contact pads88electrically connect to one or more conductive signal traces14. The solder bumps86are electrically and mechanically connected to contact pads or bonding pads88on PCB12by a solder reflow process. Molding compound or encapsulant92is deposited over semiconductor die18and carrier76to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die18to conduction tracks on PCB12in order to reduce signal propagation distance, lower capacitance, and achieve overall better circuit performance. In another embodiment, the semiconductor die18can be mechanically and electrically attached directly to PCB12using flip chip style first level packaging without carrier76.

FIGS. 3a-3eillustrate a method of forming semiconductor device100having an integrated passive device (IPD) with connections to an inductor and capacitor, the inductor and capacitor may be formed over different surfaces or substrates of IPD102. Turning toFIG. 3a, semiconductor substrate or high resistivity substrate102is first provided. The substrate of IPD102includes silicon (Si), other semi-conducting materials, or a high-resistivity substrate material and may include an optional pre-built circuit. An active region is formed within IPD102that includes one or more integrated circuits and passive or active devices used by semiconductor device100for implementing radio-frequency (RF), or other high-frequency applications. Vias are formed in the substrate of IPD102using deep reactive ion etching (DRIE), laser etching, laser drilling, or another etching process. Insulation layer104is formed over the substrate of IPD102. Insulation layer104is typically made with silicon dioxide (SiO2), but can also be made with silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), zircon (ZrO2), aluminum oxide (Al2O3), or other material having dielectric insulation properties. The deposition of insulation layer104involves CVD, or thermal oxidation, for example. Insulation layer104is formed conformally over the substrate of IPD102and a conductive material is deposited into the vias to form through-silicon vias (TSVs)106. TSVs106may be blind (as indicated by107onFIG. 3a) or may be exposed at the back-surface of the substrate of IPD102. Conductive materials are formed in TSVs106using an evaporation, electrolytic plating, electroless plating, screen printing, or another suitable metal deposition process and include Al, Cu, Sn, Ni, Au, or Ag or another conductive material.

Turning toFIG. 3b, various passive devices including capacitors, resistors and inductors are formed over a surface of the substrate of IPD102. Metal layer108is deposited over insulation layer104and is electrically connected to TSVs106. Resistive layer110is deposited over metal layer108and insulation layer104and includes tantalum silicide (TaxSiy) or other metal silicides, TaN, nichrome (NiCr), TiN, or doped poly-silicon. Dielectric layer112is deposited over resistive layer110. Dielectric layer112can be silicon nitride (Si3N4), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or a dielectric film material. In the present embodiment, resistive layer110, formed between dielectric layer112and metal layer108, is optional. Insulation layer114is deposited over insulation layer104, metal layer108, resistive layer110, and dielectric layer112. Metal layer116includes a conductive material and is deposited over insulation layer114using a PVD, CVD, electrolytic plating, or electroless plating process.

The combination of metal, insulation, dielectric, and resistive layers forms one or more passive devices over a surface of the substrate of IPD102. Box122shown onFIG. 3bindicates a resistor structure formed over the substrate of IPD102that includes portions of resistive layer110and metal layer116. Box124indicates a capacitor structure formed over IPD102that includes portions of metal layer108, resistive layer110, dielectric layer112and metal layer116. Portions of metal layers108and116form the electrodes of the capacitor indicated by box124. In alternative embodiments, different combinations of passive devices, RF circuitry, or other electronic circuits are formed over the substrate of IPD102to provide the necessary functionality of semiconductor device100. Insulation layer120is deposited over the substrate of IPD102to provide electrical isolation and physical protection to semiconductor device100. Insulation layer120is patterned to expose portions of metal layer116.

Turning toFIG. 3c, temporary wafer carrier126is mounted over device100using adhesion layer128. Temporary wafer carrier126includes a stiff material such as a glass wafer or flexible tape substrate and facilitates the build-up process performed over the back-surface of the substrate of IPD102. Temporary wafer carrier126can also include certain flexible tapes, such as high temperature back grinding tape, to support the wafer. Adhesion layer128is deposited using spin coating, or printing, and may include a laminated polymer adhesive or an ultra-violet (UV) curable liquid adhesive. In one embodiment, adhesion layer128is light, heat or mechanically releasable. After mounting temporary wafer carrier126, a backgrinding process is used to remove a portion of IPD102to expose conductive TSVs106. The backgrinding process may involve mechanical griding, chemical-mechanical polishing (CMP), wet etching, or plasma etching. After backgrinding, the metal in TSVs106is exposed.

Turning toFIG. 3d, additional conductive and insulation layers are formed over a back-surface of the substrate of IPD102. For example, insulation layer130is deposited over IPD102. Insulation layer130is patterned to expose TSVs106of the substrate of IPD102. Metal layer132is deposited and patterned over insulation layer130. Metal layer132is electrically connected to TSVs106. Using TSVs106, metal layer132is also connected to the resistor, capacitor, and other circuit elements formed over the back-surface of IPD102. Insulation layer134is deposited over metal layer132to provide electrical isolation and mechanical support to semiconductor device100. Insulation layer134may be deposited using spin coating, printing, lamination or molding, for example. As shown inFIG. 3d, metal layer132is patterned such that a portion of metal layer132forms an inductor structure indicated by box136. In alternative embodiments, additional metal, dielectric, or insulation layers may be formed over the substrate of IPD102to form additional passive circuit elements over a back-surface of IPD102.

Turning toFIG. 3e, temporary wafer carrier126and adhesion layer128are removed and an interconnect structure is connected to device100. As shown inFIG. 3e, the interconnect structure includes solder bumps138deposited over insulation layer120and electrically connected to metal layer116. Bumps138include an electrically conductive material such as solder or other electrically conductive material, e.g., Sn, Pb, Au, Ag, Cu, Zn, Bi, and alloys thereof. For example, the solder material can be eutectic Sn/Pb, high lead, or lead free. The solder material is deposited over the patterned regions of insulation layer120and is reflowed to form bumps138. In alternative embodiments, other interconnect structures such as stud bumping, wirebonds or conductive pillars are connected to semiconductor device100to allow for the connection of external system components.

Using the above method, a semiconductor device is formed that includes passive circuit elements formed over the surfaces of a semiconductor substrate. In one embodiment, the semiconductor substrate includes an IPD that provides integrated circuits and functionality for RF, or other high-frequency applications. As described above, a capacitor is formed over a first surface of the IPD, while an inductor is formed over the opposite surface of the IPD. By forming the capacitor opposite the inductor on the opposing surface of the substrate, larger capacitance values can be integrated with an inductor using a shorter connection path. The capacitor may also be formed vertically over a central region of the inductor. The dimensions of the capacitor are not limited by those of the inductor as when trying to form a capacitor at the center of the inductor. By forming the capacitor and inductor over opposing surfaces of the substrate, the dimensions of the IPD can be minimized while maintaining system performance and providing more design capability. The passive circuit elements are formed in an IPD and are connected with each other using 2D and 3D interconnections. A plurality of TSVs are formed within the substrate of the IPD. The TSVs allow for the formation of integrated circuits that interconnect the IPD with more flexibility and greater functionality.

FIG. 4illustrates semiconductor device200having an IPD connecting an inductor, resistor, and capacitor, an interconnect structure is formed over the inductor. The substrate of IPD202includes Si, other semi-conducting materials, or a high-resistivity substrate material. The substrate of IPD202may include an optional prebuilt circuit. An active region is formed over the substrate of IPD202that includes one or more integrated circuits and passive or active devices used by semiconductor device200. Vias are formed in the substrate of IPD202using DRIE, laser etching, laser drilling, or another etching process. Insulation layer204is formed over the substrate of IPD202and includes a material having dielectric insulation properties. The deposition of insulation layer204involves PVD, CVD, printing, sintering, or thermal oxidation, for example. Insulation layer204is formed conformally over the substrate of IPD202and a conductive material is deposited into the vias to form TSVs206. In one embodiment, TSVs206are exposed by backgrinding of the substrate of IPD202. The conductive materials of TSVs206are formed using an evaporation, electrolytic plating, electroless plating, screen printing, or another suitable metal deposition process and include Al, Cu, Sn, Ni, Au, or Ag or another conductive material.

Metal layer208is deposited over insulation layer204and is electrically connected to TSVs206. Resistive layer210is deposited over metal layer208and insulation layer204and includes TaxSiy or other metal silicides, TaN, NiCr, TiN, or doped poly-silicon. Dielectric layer212is deposited over resistive layer210. Dielectric layer212can be Si3N4, SiON, Ta2O5, HfO2, or a dielectric film material. Insulation layer214is deposited over insulation layer204, metal layer208, resistive layer210, and dielectric layer212. Metal layer216includes a conductive material and is deposited over insulation layer214using a PVD, CVD, electrolytic plating, or electroless plating process. The combination of metal, insulation, dielectric, and resistive layers forms one or more passive devices over a surface of IPD202. By patterning each layer, various resistors, inductors, or capacitors are formed over a surface of IPD202.

Encapsulant220, such as a molding compound, is deposited over metal layer216to provide electrical isolation and physical support to semiconductor device200. Molding compound220includes epoxy acrylate or other polymer material with or without filler, and is applied by paste printing, compressive molding, or other molding processes. In an alternative embodiment, however, molding compound220is replaced by a permanently bonding adhesive material. An optional mechanical carrier222is mounted to adhesive material220to provide additional physical support to device200. Mechanical carrier222may include a conductive layer to provide electro-magnetic interference (EMI) protection to device200. Similarly, mechanical carrier222may include heat sinks, thermal sheets, or heat spreaders to facilitate the removal of thermal energy from device200.

Insulation layer224is deposited over a back side of IPD202. Insulation layer224is patterned to expose TSVs206of IPD202. Metal layer226is deposited and patterned over insulation layer224. Metal layer226is electrically connected to TSVs206. Using TSVs206, metal layer226is also connected to the resistor, capacitor, and other circuit elements formed over the back-surface of IPD202. Insulation layer228is deposited over metal layer226to provide electrical isolation and mechanical support to semiconductor device200. Insulation layer228may be deposited using spin coating, printing, lamination or molding, for example. Metal layer226forms an inductor structure over the back surface of IPD202. In alternative embodiments, additional metal, dielectric, or insulation layers may be deposited over IPD202to form additional passive circuit elements.

An interconnect structure is connected to device200. As shown inFIG. 4, the interconnect structure includes solder bumps230deposited over insulation layer228and electrically connected to metal layer226. Bumps230include an electrically conductive material such as solder. The conductive material is deposited over the patterned regions of insulation layer228and is reflowed to form bumps230. In alternative embodiments, other interconnect structures such as stud bumping, wirebonds or conductive pillars are connected to semiconductor device200to allow for the connection of external system components.

FIG. 5illustrates semiconductor device300having an IPD connected to an inductor and capacitor, an inductor structure is formed over a front-surface of the IPD. The substrate of IPD302includes Si, other semi-conducting materials, or a high-resistivity substrate material. The substrate of IPD302may include an optional prebuilt circuit. An active region is formed over the substrate of IPD302that includes one or more integrated circuits and passive or active devices used by semiconductor device300. Vias are formed in IPD302using laser etching, laser drilling, or another etching process. Insulation layer304is formed over IPD302and includes a material having dielectric insulation properties. The deposition of insulation layer304involves PVD, CVD, printing, sintering, or thermal oxidation, for example. Insulation layer304is formed conformally over IPD302and a conductive material is deposited into the vias to form TSVs306. In one embodiment, TSVs306are exposed by backgrinding of IPD302. The conductive material of TSVs306is formed using an evaporation, electrolytic plating, electroless plating, screen printing, or another suitable metal deposition process and include Al, Cu, Sn, Ni, Au, or Ag or another conductive material.

Metal layer308is deposited over insulation layer304and is electrically connected to TSVs306. As shown inFIG. 5, metal layer308is patterned to form an inductor structure over the top surface of IPD302. The inductor is connected to TSVs306of IPD302. Insulation layer310is formed over metal layer308to provide electrical insulation and mechanical support for semiconductor device300. Insulation layer310is deposited using spin coating, printing, or molding, for example. In an alternative embodiment, additional resistive layers are formed over the top surface of IPD302to form a resistor structure connected to metal layer308.

Insulation layer312is deposited over a back surface of IPD302. Insulation layer312is patterned to expose TSVs306of IPD302. Metal layer314is deposited and patterned over insulation layer312. Metal layer314is electrically connected to TSVs306. Using TSVs306, metal layer314is also connected to the inductor structure and other circuitry formed over IPD302by metal layer308. Resistive layer316is deposited over metal layer314and insulation layer312and includes TaxSiy or other metal silicides, TaN, NiCr, TiN, or doped poly-silicon. Dielectric layer318is deposited over resistive layer316. Dielectric layer318can be Si3N4, Ta2O5, HfO2, or a dielectric film material. Insulation layer320is deposited over insulation layer312, metal layer314, resistive layer316, and dielectric layer318. Metal layer322includes a conductive material and is deposited over insulation layer320using a PVD, CVD, electrolytic plating, or electroless plating process. The combination of metal, insulation, dielectric, and resistive layers forms one or more passive devices over a surface of IPD302. By patterning each layer, various resistors, inductors, or capacitors are formed over a surface of IPD302. Insulation layer324is deposited over metal layer322. Insulation layer324provides electrical insulation and mechanical support to device300and is patterned to expose portions of metal layer322. Insulation layer324may be deposited using spin coating, printing, lamination or molding, for example.

An interconnect structure is connected to device300. As shown inFIG. 5, the interconnect structure includes solder bumps326deposited over insulation layer324and electrically connected to metal layer322. Bumps326include an electrically conductive material such as solder. The conductive material is deposited over the patterned regions of insulation layer324and is reflowed to form bumps326. In alternative embodiments, other interconnect structures such as stud bumping, wirebonds or conductive pillars are connected to semiconductor device300to allow for the connection of external system components.

FIG. 6illustrates semiconductor device400having an IPD connected to an inductor and capacitor, the metal in TSVs of the IPD is formed together with a bottom electrode of the capacitor. The substrate of IPD402includes Si, other semi-conducting materials, or a high-resistivity substrate material. An active region is formed over IPD402that includes one or more integrated circuits and passive or active devices used by semiconductor device400. Vias are formed in IPD402using DRIE, laser etching, laser drilling, or another etching process. Insulation layer404is formed over IPD402. The deposition of insulation layer404involves PVD, CVD, printing, sintering, or thermal oxidation, for example. Insulation layer404is formed conformally over IPD402. Metal layer406is deposited over insulation layer404and fills in the vias to form conductive TSVs in IPD402. Additional CMP processes may be applied to smooth the top surface of metal406. Resistive layer408is deposited over metal layer406and insulation layer404and includes TaxSiy or other metal silicides, TaN, NiCr, TiN, or doped poly-silicon. In one embodiment, the seed layer etching for plating metal layer406is performed after the patterning of resistive layer408is complete. Dielectric layer410is deposited over resistive layer408. Dielectric layer410can be Si3N4, Ta2O5, HfO2, or a dielectric film material. Insulation layer412is deposited over insulation layer404, metal layer406, resistive layer408, and dielectric layer410. Metal layer414includes a conductive material and is deposited over insulation layer412using a PVD, CVD, electrolytic plating, or electroless plating process.

The combination of metal, insulation, dielectric, and resistive layers forms one or more passive devices over a surface of IPD402. A capacitor is formed over IPD402(indicated by box426). One electrode of capacitor426is formed by a portion of metal layer406. Box428indicates a resistor structure formed over IPD402that includes portions of resistive layer408and metal layer414. In alternative embodiments, different combinations of passive devices, RF circuitry, or other electronic circuits are formed over IPD402to provide the necessary functionality of semiconductor device400. Insulation layer416is deposited over IPD402to provide electrical isolation and physical protection to semiconductor device400.

Additional conductive and insulation layers are formed over a back-surface of IPD402. Insulation layer420is deposited over IPD402. Insulation layer420is patterned to expose TSVs406of IPD402. Metal layer422is deposited and patterned over insulation layer420. Metal layer422is electrically connected to TSVs406. Using TSVs406, metal layer422is connected to the resistor and capacitor structures formed over the back-surface of IPD402. Insulation layer424is deposited over metal layer422to provide electrical isolation and mechanical support to semiconductor device400. Insulation layer424may be deposited using spin coating, printing, lamination or molding, for example.

An interconnect structure is connected to device400. As shown inFIG. 6, the interconnect structure includes solder bumps418deposited over insulation layer416and electrically connected to metal layer414. Bumps418include an electrically conductive material that is deposited over the patterned regions of insulation layer416and reflowed to form bumps418. In alternative embodiments, other interconnect structures such as stud bumping, wirebonds or conductive pillars are connected to semiconductor device400to allow for the connection of external system components.

FIG. 7illustrates semiconductor device500having an IPD connected to an inductor and capacitor, the inductor and capacitor are formed over the IPD, a second inductor is formed over a top surface of the IPD. IPD502includes Si, other semi-conducting materials, or a high-resistivity substrate material. An active region is formed over IPD502that includes one or more integrated circuits and passive or active devices used by semiconductor device500. Vias are formed in IPD502using laser etching, laser drilling, or another etching process. Insulation layer504is formed over IPD502. Insulation layer504is typically made with SiO2, but can also be made with Si3N4, SiON, Ta2O5, ZrO2, Al2O3, or other material having dielectric insulation properties. The deposition of insulation layer504involves PVD, CVD, printing, sintering, or thermal oxidation, for example. Insulation layer504is formed conformally over IPD502and a conductive material is deposited into the vias to form TSVs506.

Metal layer508is deposited over insulation layer504and is electrically connected to TSVs506. Resistive layer510is deposited over metal layer508and insulation layer504and includes TaxSiy or other metal silicides, TaN, NiCr, TiN, or doped poly-silicon. Dielectric layer512is deposited over resistive layer510. Dielectric layer512can be SiN, Ta2O5, HfO2, or a dielectric film material. Insulation layer514is deposited over insulation layer504, metal layer508, resistive layer510, and dielectric layer512. Metal layer516includes a conductive material and is deposited over insulation layer514using a PVD, CVD, electrolytic plating, or electroless plating process.

The combination of metal, insulation, dielectric, and resistive layers forms one or more passive devices over a surface of IPD502. Box518shown onFIG. 7indicates a resistor structure formed over IPD502that includes portions of resistive layer510and metal layer516. Box520indicates a capacitor structure formed over IPD502that includes portions of metal layer508, resistive layer510, dielectric layer512and metal layer516. Portions of metal layers508and516form the electrodes of the capacitor indicated by box520. Box522indicates an inductor structure formed by portions of metal layer516. In alternative embodiments, different combinations of passive devices, RF circuitry, or other electronic circuits are formed over IPD502to provide the necessary functionality of semiconductor device500. Insulation layer524is deposited over IPD502to provide electrical isolation and physical protection to semiconductor device500.

Additional conductive and insulation layers are formed over a back-surface of IPD502. Insulation layer528is deposited over IPD502. Insulation layer528is patterned to expose TSVs506of IPD502. Metal layer530is deposited and patterned over insulation layer528. Metal layer530is electrically connected to TSVs506. Using TSVs506, metal layer530is also connected to the resistor, capacitor, inductor and other circuit elements formed over the back-surface of IPD502. Insulation layer534is deposited over metal layer530to provide electrical isolation and mechanical support to semiconductor device500. Insulation layer534may be deposited using spin coating, printing, lamination or molding, for example. As shown inFIG. 7, metal layer530is patterned such that a portion of metal layer530forms an inductor structure indicated by box532. In alternative embodiments, additional metal, dielectric, or insulation layers may be formed over IPD502to form additional passive circuit elements over a back-surface of IPD502.

An interconnect structure is connected to device500. As shown inFIG. 7, the interconnect structure includes solder bumps526deposited over insulation layer524and electrically connected to metal layer516. Bumps526include an electrically conductive material deposited over the patterned regions of insulation layer524and reflowed to form bumps526. In alternative embodiments, other interconnect structures such as stud bumping, wirebonds or conductive pillars are connected to semiconductor device500to allow for the connection of external system components.