Analog to digital converter with low power control

A circuit comprises a reference voltage generating circuit, a first switch, a second switch, and a capacitive element. The reference voltage generating circuit has an input and output terminal for providing a reference voltage. The first switch has a first terminal coupled to a first power supply voltage terminal, a second terminal coupled to the input terminal of the reference voltage generating circuit, and a control terminal for receiving a first control signal. The second switch has a first terminal coupled to the output terminal of the reference voltage generating circuit, a second terminal, and a control terminal for receiving a second control signal. The capacitive element has a first plate electrode coupled to the second terminal of the second switch, and a second plate electrode coupled to a second power supply voltage terminal.

BACKGROUND

This disclosure relates generally to analog to digital converters, and more specifically, to analog to digital converters with low power control.

2. Related Art

Analog to digital converters (ADCs) are commonly used in processors where analog signals are present, such as automotive applications. For example, many measurements, such as temperature, are received as an analog signal and the processor must use or display that information digitally. Especially for applications involving a battery, which does include automotive applications, power savings is very important. One of the ways this is achieved is by operating the processor in a power savings mode when the processor is not actually performing desired functions. The processor, however, must be able to detect when it is time to come out of the power savings mode. Thus, the processor typically must be powered in some form in order to perform the determination that it is time to come out of the power savings mode. For an automotive application, for example, this cannot be predicted with any certainty. The time between uses can be measured in seconds or weeks. This is compounded by the various circuits that must be able to function in order to begin to come out of the power savings mode. Each of these circuits, including the ADCs, are potentially power consumers that can drain a battery.

Thus there is a need for a processor to utilize a power savings mode in which the circuits that it uses can reduce power consumption associated with the power savings mode.

DETAILED DESCRIPTION

In one aspect, a processing unit has a processor and an analog to digital converter (ADC) in which the processing unit has a power savings mode and an active mode. During the power savings mode, the processing unit switches between a low power mode and a check mode. During the check mode, the processor determines if the processing unit should switch to the active mode or stay in the power savings mode. During the check mode, power required for the ADC to provide a high precision output is not applied to the ADC. Instead, power is applied to the ADC that results in a less precise output but one that is achieved much more quickly. Thus the ADC provides a sufficiently accurate output for the processor to determine if the processing unit should enter the active mode more quickly than would be achieved using the more precise method. A particular way that the reduced power consumption is achieved is by preventing the charging of a capacitor during the check mode. The capacitor is important in reducing noise on a reference used by the ADC. The reduced noise allows the ADC to provide a more precise output. For the purposes of the processor determining if the active mode should be entered, the enhanced precision arising from the capacitor is not required. Thus, power is saved by not charging the capacitor when switching from the low power mode to the check mode and not having to spend nearly as much time in the check mode as would be required if the capacitor had to be charged in switching from the low power mode to the check mode. This is better understood by reference to the following description and the drawing.

Shown in the sole FIGURE is a processing unit10, which is preferably an integrated circuit, comprising a processor12, an analog to digital converter (ADC)14, a precharge circuit16, a multiplexer18, a P channel transistor20, a P channel transistor22, an external connection24, a reference voltage generating circuit26, and a node36. Reference voltage generating circuit26, which functions as a resistor divider, comprises resistors28,30,32, and34. Transistors20and22functions as switches. Also shown in the FIGURE is a capacitor38which is preferably external to processing unit10. As a capacitor, capacitor38has plate electrodes connected to terminals. Processor12receives power through a power supply terminal VDD. Power supply terminal VDD is for receiving the main power for logic operations of processing unit10. Processor12receives a data signal D from ADC14and provides a low power mode signal LP to a gate of transistor20, a precharge enable signal PE to precharge circuit16, an active mode bar signal AMB to a gate of transistor22, and a mux control signal MC to multiplexer18. ADC14and precharge circuit16receive power from an analog power supply terminal VDDA. Analog power supply terminal VDDA is for receiving power for use by analog circuits of processing unit10. The analog circuits need a less noisy power supply than do the logic circuits. Transistor20has a source connected to a voltage reference high terminal VRH. Voltage reference high terminal VRH is for powering voltage reference generating circuit26and has a particularly high requirement for being low noise. Resistor28has a first terminal connected to a drain of transistor20and a second terminal connected to a first reference input of ADC14and an output of precharge circuit16. Resistor30has a first terminal connected to the second terminal of resistor28and a second terminal connected to a second reference input of ADC14. The common connection of the second terminal of resistor28and the first terminal of resistor30with the first input of ADC14and the output of precharge circuit16is shown as node36. Resistor32has a first terminal connected to the second terminal of resistor30and a second terminal connected to a third reference input of ADC14. Resistor34has a first terminal connected to the second terminal of resistor32and a second terminal connected to a voltage reference low terminal. Voltage reference low terminal is for being connected to ground potential but in a way that preferably has as little current as possible through it and therefore is very low noise. Multiplexer18has a plurality of inputs for receiving signals external to processing unit10. These signals are shown as external signals, ext1, ext2, and ext N. These external signals are analog signals and are selectively coupled to ADC14as analog signal A under the control of processor12. ADC14converts the selected analog signal to data signal D which is a digital signal and which is received by processor12. Transistor22has a source connected to node36and a drain connected to an external terminal24. Capacitor38has a first terminal connected to external node24and a second terminal connected to voltage reference low terminal VRL.

In the case of processing unit10being in the active mode, processor12selects one of the analog external signals, ext1, ext2, or ext N, for coupling to ADC14. ADC14converts the received signal A to a digital data signal D received by processor12. Reference voltage generating circuit26divides the voltage applied at terminal VRH into fourths. This is easily achieved with resistors28,30,32, and34being of equal resistance. The actual value of the resistance is not particularly significant but it is important that they be the same resistance. This criterion is compatible with the capabilities of semiconductor processing. Thus at node36is a voltage that is 75 percent of the voltage at terminal VRH. At the node connecting resistors30and32, the voltage is 50 percent of the voltage at terminal VRH. At the node connecting resistors32and34, the voltage is 25 percent of the voltage at terminal VRH. These three equally spaced voltages are very useful in ADC14providing an accurate analog to digital conversion. The use of providing multiple reference voltages for providing an accurate analog to digital conversion is well understood in the art. Capacitor38provides for noise reduction on the three equally spaced reference voltages. Precharge circuit16is for improving the speed at which capacitor38becomes charged to its ultimate value of 75 percent of the voltage at terminal VRH, especially when coming out of the power savings mode. Even with the assistance of precharge circuit16, it can still take nearly 10 milliseconds for node36to reach the desired 75 percent value of the voltage at terminal VRH for recommended values for the capacitance of capacitor38. The recommended value may be 100 nanofarads. In the active mode, transistor22receives signal AMB at a logic low. In this case, the active mode is indicated by a logic low and is so designated by the “B” in AMB. Transistor22is thus conductive in the active mode and keeps capacitor38coupled to node36in the active mode.

For the case of transferring from the active mode to the power savings mode, signal LP and signal AMB become a logic high which causes transistors20and22become non-conductive. Transistor20, being non-conductive, blocks current flow from terminal VRH through reference voltage generating circuit26. With transistor22being non-conductive, the voltage on capacitor38dissipates to the voltage at VRL as a result of leakage. Precharge circuit16and ADC14are placed into a low power mode. Processor12may have power savings applied to portions of its internal workings. This initial portion of the power savings mode where the circuits are mostly not powered and have minimal functionality may be called a low power mode.

Processing unit also periodically checks to see if needs to become operational for its intended purpose. In the check mode ADC14, which becomes powered, needs to provide selected information to processor12. This information, however, does not have the same level of precision needed as for operation of ADC during the active mode. Thus, instead of charging capacitor38to obtain the benefits of low noise operation, transistor22is kept non-conductive by processor12keeping signal AMB at a logic high during the check mode. Processor12switches signal LP to a logic low so that transistor20becomes conductive. Reference voltage generating circuit26thus provides the voltages of 25, 50, and 75 percent of the voltage at terminal VRH to ADC14without being delayed by having to charge the capacitance of capacitor38. This can be accomplished in less than 20 microseconds which is nearly 3 orders of magnitude than that required with capacitor38coupled to node36. Thus, the functionality of ADC14needed during the check mode is available without requiring the charging of capacitor38. One beneficial affect of this is that processor12can perform the required check during the check mode without having to wait for capacitor38to become charged. This allows for a much faster to the low power mode if the check shows that the active mode does not have to be entered. Another benefit is that the current required to charge capacitor is not wasted as would be the case if capacitor38was charged but the active mode is not entered. Also, if capacitor38remained charged and reference voltage generating circuit remained activated during the low power mode, the low power mode would be less effective in reducing power drain.

If the check mode determines that the active mode is to be entered, processor12switches signal AMB to a logic low and signal PE to a logic high. When this happens, node36is dropped to a voltage near the voltage at terminal VRL but begins rising due to the charging of capacitor38by precharge circuit16, which becomes powered and to a lesser extent through resistor28and transistor20. Processor12must wait the needed time to bring node36to 75 percent of the voltage at terminal VRH and may then begin precision operations using ADC14.

If the check mode determines that processing system is to return to the low power mode portion of the power savings mode, then processor12switches signal LP back to a logic high so that transistor20becomes non-conductive so that power stops being applied to reference voltage generating circuit26. ADC14and precharge circuit16are returned to their low power mode. The resulting conditions are the same as previously described for the low power mode. Reducing time required in the check mode results in increasing the time in the low power mode and thus results in reducing power consumption in the power savings mode of processing unit10. Thus, the use of transistor22to isolate capacitor38during the check mode results in power savings during the power savings mode.

By now it should be appreciated that there has been provided a circuit including a reference voltage generating circuit having an input and an output terminal for providing a reference voltage. The circuit further includes a first switch having a first terminal coupled to a first power supply voltage terminal, a second terminal coupled to the input and the output terminal of the reference voltage generating circuit, and a control terminal for receiving a first control signal. The circuit further includes a second switch having a first terminal coupled to the input and the output terminal of the reference voltage generating circuit, a second terminal, and a control terminal for receiving a second control signal. The circuit further includes a capacitive element having a first plate electrode coupled to the second terminal of the second switch, and a second plate electrode coupled to a second power supply voltage terminal. The circuit may be further characterized by the first control signal being a low power mode signal provided by a processor. The circuit may further comprise an analog-to-digital converter having a reference voltage input terminal for receiving at least one reference voltage from the reference voltage generating circuit. The circuit may be further characterized by the analog-to-digital converter being a redundant signed division analog-to-digital converter. The circuit may be further characterized by the reference voltage generating circuit comprising a plurality of series-connected resistive elements. The circuit may further comprise a precharge circuit coupled to the first terminal of the second switch, the precharge circuit for precharging the capacitive element to a predetermined voltage in response to a mode control signal. The circuit may be further characterized by the second control signal being provided in response to setting a register bit field of a processor. The circuit may be further characterized by the circuit being implemented as a portion of an integrated circuit and the capacitive element is external to the integrated circuit. The circuit may be further characterized by the second control signal being an active mode control signal.

Also described is a circuit including a voltage divider comprising a plurality of series-connected resistive elements. The circuit further includes a first switch having a first terminal coupled to a first power supply voltage terminal, a second terminal coupled to the plurality of series-connected resistive elements, and a control terminal for receiving a first control signal. The circuit further includes a second switch having a first terminal coupled to the plurality of resistive elements, a second terminal, and a control terminal for receiving a second control signal. The circuit further includes a capacitive element having a first plate electrode coupled to the second terminal of the second switch, and a second plate electrode coupled to a second power supply voltage terminal. The circuit may be further characterized by the second control signal being provided in response to setting a register bit field of a processor. The circuit may be further characterized by the voltage divider being for providing a reference voltage for use by an analog-to-digital converter. The circuit may be further characterized by the circuit being formed on an integrated circuit and the capacitive element being external to the integrated circuit. The circuit may be further characterized by the first and second switches being implemented as P-channel transistors. The circuit may be further characterized by the plurality of series-connected resistive elements comprising a first resistive element having a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to the first terminal of the second switch, a second resistive element having a first terminal coupled to the second terminal of the first resistive element, and a second terminal, a third resistive element having a first terminal coupled to the second terminal of the second resistive element, and a second terminal, and a fourth resistive element having a first terminal coupled to the second terminal of the third resistive element, and a second terminal coupled to the second power supply voltage terminal. The circuit may further comprise a precharge circuit coupled to the first terminal of the second switch, the precharge circuit for precharging the capacitive element to a predetermined voltage in response to a mode control signal.

Described also is a method including determining that a circuit is needed to perform a first task requiring a first accuracy. The method also includes causing a reference voltage generating circuit to operate in an active mode. The method also includes providing a power supply voltage to the reference voltage generating circuit. The method also includes coupling a capacitor to the reference voltage generating circuit. The method also includes providing a reference voltage having the first accuracy from the reference voltage generating circuit to the circuit. The method also includes determining that the circuit is to operate in a low power mode. The method also includes causing the reference voltage generating circuit to enter the low power mode. The method also includes decoupling the power supply voltage from the reference voltage generating circuit. The method also includes decoupling the capacitor from the reference voltage generating circuit. The method also includes determining that the circuit is needed for a second task requiring a second accuracy, the second accuracy being less than the first accuracy. The method also includes providing the power supply voltage to the reference voltage generating circuit. The method also includes causing the reference voltage generating circuit to operate in a low accuracy active mode. The method also includes performing the second task at the second accuracy with the capacitor decoupled from the reference voltage generating circuit in the low accuracy active mode. The method may be further characterized by the providing a reference voltage having the first accuracy further comprising waiting a predetermined time period for the capacitor to fully charge. The method may be further characterized by the determining that a circuit is needed further comprising determining that an analog-to-digital converter circuit is needed. The method may be further characterized by the coupling a capacitor to the reference voltage generating circuit further comprising setting a control bit in a processor.