Analog-to-digital conversion device comprising two cascaded noise-shaping successive approximation register analog-to-digital conversion stages, and related electronic sensor

This analog-to-digital converting device comprises:

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a U.S. non-provisional application claiming the benefit of French Application No. 19 15610, filed on Dec. 26, 2019, which is incorporated herein by reference in its entirety.

FIELD

The present invention relates to an analog-to-digital converting device for converting an analog input signal into a digital output signal.

The invention also relates to an electronic sensor comprising such an analog-to-digital converting device.

BACKGROUND

This invention concerns the field of analog-to-digital converters, also denoted ADC, in particular in high-channel-density data-acquisition systems. Such analog-to-digital converters are typically used in biomedical and instrumentation applications.

Successive approximation register analog-to-digital converters, also denoted SAR ADC, are popular in multiplexed systems because of their low latency and fast response, even to a full-scale input step without any settling issues, as explained in the article “Demystifying High-Performance Multiplexed Data-Acquisition Systems” from M. Pachchigar, in Analog Dialogue, 2014. Successive approximation register analog-to-digital converters have been widely used in energy-efficient applications due to their simplicity and power efficiency.

A successive approximation register analog-to-digital converter typically includes a digital-to-analog converter, also denoted DAC, with an input and an output; a comparator with two inputs and an output, one input being connected to the output of the digital-to-analog converter and the other input being adapted to receive a reference signal; and a SAR logic unit connected to the output of the comparator, the SAR logic unit being adapted to control the digital-to-analog converter. The digital-to-analog converter generally contains a capacitor array.

US 2018/0183450 A1 concerns an interleaving successive approximation register analog-to-digital converter (SAR ADC) with noise-shaping having a first successive approximation register block, also called first SAR block, a second successive approximation register block, also called second SAR block, and a noise-shaping circuit. The first and second SAR blocks take turns to sample an input voltage for successive approximation of the input voltage and observation of a digital representation of the input voltage. The noise-shaping circuit receives a first residue voltage from the first SAR block and receives a second residue voltage from the second SAR block alternately, and outputs a noise-shaping signal to be fed into the first SAR block and the second SAR block. Such a successive approximation register analog-to-digital converter allows increasing the speed of the process, because when one SAR block is in conversion mode, the other one samples the next input.

However, successive approximation register analog-to-digital converters are suffering from significant noise of the comparator, as well as extra power needed to drive a large DAC capacitor array. Therefore, such successive approximation register analog-to-digital converters are barely used for more than 10-12 bit resolution applications.

SUMMARY

An object of the invention is therefore to provide an improved analog-to-digital converting device comprising at least one successive approximation register analog-to-digital converter.

For this purpose, the subject-matter of the invention is an analog-to-digital converting device for converting an analog input signal into a digital output signal, comprising:an input terminal for receiving the analog input signal;an output terminal for issuing the digital output signal;a first successive approximation register analog-to-digital conversion module, called first SAR ADC module, connected via its input to the input terminal and configured to deliver via its output a first digital signal;a first feedback module configured to receive a first residue signal from the first SAR ADC module and to process and inject it back at input of the first SAR ADC module;a second successive approximation register analog-to-digital conversion module, called second SAR ADC module, connected via its input to the first SAR ADC module to receive the first residue signal and configured to deliver via its output a second digital signal;a second feedback module configured to receive a second residue signal from the second SAR ADC module and to process and inject it back at input of the second SAR ADC module; anda multiplexing module connected to the output of the first SAR ADC module and to the output of the second SAR ADC module, the multiplexing module being configured to deliver the digital output signal at the output terminal.

The analog-to-digital converting device according to the invention therefore comprises two cascaded noise-shaping successive approximation register analog-to-digital conversion stages, also called NS-SAR ADC stages, namely a first NS-SAR ADC stage and a second NS-SAR ADC stage, each NS-SAR ADC stage including a SAR ADC module and a respective error feedback module to noise-shape a quantization noise of the SAR ADC module. The quantization noise of the first NS-SAR ADC stage, in particular of the first SAR ADC module, is fed into the second NS-SAR ADC stage to form a multi-stage noise-shaping (MASH) SAR ADC.

The skilled person will further note that the noise-shaping is performed by an error feedback technique such that the analog-to-digital converting device according to the invention is no longer using any operational transconductance amplifier (OTA). Therefore, it is indeed an OTA-free topology.

In optional addition, the multiplexing module is able to operate either in a first operating mode wherein the delivered digital output signal is the first digital signal or in a second operating mode wherein the delivered digital output signal is a combination of the first and second digital signals. Therefore, a further advantage of the analog-to-digital converting device according to the invention is the configurability such that it can be configured as either single-stage or multi-stage to support different bandwidths and resolutions.

In optional addition, each feedback module includes a respective second-order filter for filtering the respective residue signal before injecting it back at input of the respective SAR ADC module. Therefore, a further advantage of the analog-to-digital converting device according to the invention is to provide a fourth-order noise-shaping performance while being as stable as a second-order analog-to-digital converter.

According to other advantageous aspects of the invention, the analog-to-digital converting device comprises one or several of the following features, taken individually or according to any technically possible combination:the multiplexing module is configured to operate in a first operating mode wherein the delivered digital output signal is the first digital signal or in a second operating mode wherein the delivered digital output signal is a combination of the first and second digital signals;the converting device further comprises a selection module for selecting an operating mode among the first operating mode and the second operating mode of the multiplexing module;the first feedback module comprises a first filter for filtering the first residue signal before injecting it back at input of the first SAR ADC module,

the first filter being preferably a second-order filter;

the first filter being still preferably a finite impulse response filter;the second feedback module comprises a second filter for filtering the second residue signal before injecting it back at input of the second SAR ADC module,

the second filter being preferably a second-order filter;

the second filter being still preferably a finite impulse response filter;the first SAR ADC module comprises:a first digital-to-analog converter with an input and an output;a first comparator with two inputs and an output, one input being connected to the output of the first digital-to-analog converter and the other input being adapted to receive a reference signal; anda first successive approximation register logic unit connected to the output of the first comparator, the first successive approximation register logic unit being adapted to control the first digital-to-analog converter;the input of the first digital-to-analog converter forming the input of the first SAR ADC module;the output of the first comparator forming the output of the first SAR ADC module;the input of the second SAR ADC module is connected to the output of the first digital-to-analog converter;the second SAR ADC module comprises:a second digital-to-analog converter with an input and an output;a second comparator with two inputs and an output, one input being connected to the output of the second digital-to-analog converter and the other input being adapted to receive a reference signal; anda second successive approximation register logic unit connected to the output of the second comparator, the second successive approximation register logic unit being configured to control the second digital-to-analog converter;the input of the second digital-to-analog converter forming the input of the second SAR ADC module;the output of the second comparator forming the output of the second SAR ADC module;the multiplexing module comprises a digital cancellation logic unit adapted to apply a first transfer function to the first digital signal and a second transfer function to the second digital signal, so as to cancel the first residue signal.

The subject-matter of the invention is also an electronic sensor comprising an analog-to-digital converting device for converting an analog input signal into a digital output signal, the converting device being as defined above.

DETAILED DESCRIPTION

In the following description, NS stands for Noise-Shaping; SAR stands for Successive Approximation Register; and ADC stands for Analog-to-Digital Converter or Analog-to-Digital Conversion. Thus, NS-SAR ADC stands for a noise-shaping successive approximation register analog-to-digital converter, or conversion stage.

InFIG. 1, an electronic sensor8comprises an analog-to-digital converting device10for converting an analog input signal Vin(z) into a digital output signal Dout(z). The electronic sensor8is adapted to be used in various applications, such as biomedical and/or instrumentation applications.

The analog-to-digital converting device10is configured to convert the analog input signal Vin(z) into the digital output signal Dout(z) and comprises an input terminal12for receiving the analog input signal Vin(z) and an output terminal14for issuing the digital output signal Dout(z).

The analog-to-digital converting device10further comprises a first noise-shaping successive approximation register analog-to-digital conversion stage16, also called first NS-SAR ADC stage, and a second noise-shaping successive approximation register analog-to-digital conversion stage18, also called second NS-SAR ADC stage, the second NS-SAR ADC stage18being connected in a cascaded manner to the first NS-SAR ADC stage16, and a multiplexing module20connected respectively to the output of first NS-SAR ADC stage16and to the output of second NS-SAR ADC stage18, the multiplexing module20being configured to deliver the digital output signal Dout(z) at the output terminal14, from a first digital signal D1(z) coming from the first stage NS-SAR ADC16, or additionally from a second digital signal D2(z) coming from the second stage NS-SAR ADC18.

The skilled person will understand that the term “multiplexing” generally refers to the act of grouping information or signals from several channels on a single channel. The multiplexing module20shall then be understood as a module capable of grouping together at output terminal14the signals coming from several channels, i.e. the signals coming from the NS-SAR ADC stages16,18, the multiplexing module20being configured to deliver the digital output signal Dout(z) at the output terminal14, this from the first digital signal D1(z) coming from the first NS-SAR ADC16stage, or even additionally from the second digital signal D2(z) coming from the second NS-SAR ADC18stage, i.e. from the combination of the first digital signal D1(z) and the second digital signal D2(z).

As an optional addition, the multiplexing module20is configured to operate in a first operating mode M1wherein the delivered digital output signal Dout(z) is the first digital signal D1(z) or in a second operating mode M2wherein the delivered digital output signal Dout(z) is a combination of the first and second digital signals D1(z), D2(z).

According to this optional addition, the converting device10further comprises a selection module22configured to select an operating mode among the first operating mode M1and the second operating mode M2of the multiplexing module20.

The first NS-SAR ADC stage16includes a first successive approximation register analog-to-digital conversion module24, called first SAR ADC module24, also denoted SAR_ADC1, connected via its input26to the input terminal12and configured to deliver via its output28a first digital signal D1(z).

The first NS-SAR ADC stage16also includes a first feedback module30configured to receive via its input32a first residue signal E1(z) from the first SAR ADC module24and to process and inject it back, via its output34, at input26of the first SAR ADC module24.

In the example ofFIG. 1, the first NS-SAR ADC stage16includes a first adder36connected on one hand to the input terminal12and to the output34of the first feedback module30, and on the other hand to the input26of the first SAR ADC module24. The first adder36is configured for adding the signal processed by the first feedback module30, also denoted(z), to the analog input signal Vin(z) and for delivering this sum of signals(z)+Vin(z) to the input26of the first SAR ADC module24.

The second NS-SAR ADC stage18includes a second successive approximation register analog-to-digital conversion module28, called second SAR ADC module38, also denoted SAR_ADC2, connected via its input40to the first SAR ADC module24to receive the first residue signal E1(z) and configured to deliver via its output42a second digital signal D2(z).

The second NS-SAR ADC stage18also includes a second feedback module44configured to receive via its input46a second residue signal E2(z) from the second SAR ADC module38and to process and inject it back, via its output48, at input40of the second SAR ADC module38.

In the example ofFIG. 1, the second NS-SAR ADC stage18includes a second adder50connected on one hand to the first NS-SAR ADC stage16and to the output48of the second feedback module44, and on the other hand to the input40of the second SAR ADC module38. The second adder50is configured for adding the signal processed by the second feedback module44, also denoted(z), to the first residue signal E1(z) and for delivering this sum of signals(z)+E1(z) to the input40of the second SAR ADC module38.

The multiplexing module20is configured to deliver the digital output signal Dout(z) from the first digital signal D1(z) and the second digital signal D2(z). The multiplexing module20is connected to the output28of the first SAR ADC module24and to the output42of the second SAR ADC module38.

The multiplexing module20is preferably configured to deliver, as the digital output signal Dout(z) at the output terminal14, either the first digital signal D1(z) or the combination of the first D1(z) and second D2(z) digital signals.

The multiplexing module20includes a digital cancellation logic unit52, also denoted DCL, adapted to apply a first transfer function H1(z) to the first digital signal D1(z) and a second transfer function H2(z) to the second digital signal D2(z), as shown inFIG. 2. The digital cancellation logic unit52is adapted to cancel the first residue signal E1(z).

In the example ofFIG. 2, the first SAR ADC module24includes a first digital-to-analog converter54, also denoted C-DAC1, with an input56and an output58. The input56of the first digital-to-analog converter54forms the input26of the first SAR ADC module24.

The skilled person will observe that the input56, which forms the input of the first SAR ADC module24whose function is to perform analog-to-digital conversion, is an input of the first digital-to-analog converter54, but not its single input. The skilled person will then understand that the input56is an analog input corresponding to an additional input, known per se for a SAR ADC module, of said digital-to-analog converter54, and not the digital input intended to receive the digital signal for conversion to an analog signal. The additional input56is configured for receiving a reference voltage used to normalize said digital input. In the example ofFIG. 2, said reference voltage corresponds to the signal delivered by the first adder36to the first SAR ADC module24, i.e. corresponds to the sum of signals(z)+Vin(z).

The first SAR ADC module24also includes a first comparator60with two inputs62A,62B, namely a first input62A and a second input62B, and an output64. One input of the first comparator60, such as the first input62A, is connected to the output58of the first digital-to-analog converter54and the other input, such as the second input62A, is adapted to receive a reference signal, such a first reference voltage Vref1. The output64of the first comparator60forms the output28of the first SAR ADC module24.

The first SAR ADC module24further includes a first successive approximation register logic unit66, also called first SAR logic unit66and denoted SAR1, connected to the output64of the first comparator60, the first SAR logic unit66being adapted to control the first digital-to-analog converter54.

The first feedback module30includes a first filter68for filtering the first residue signal E1(z) before injecting it, as a first filtered residue signal(z), back at input26of the first SAR ADC module24.

In the example ofFIG. 2, the second SAR ADC module38includes a second digital-to-analog converter70, also denoted C-DAC2, with an input72and an output74. The input72of the second digital-to-analog converter70forms the input40of the second SAR ADC module38.

The skilled person will observe that the input72, which forms the input of the second SAR ADC module58whose function is to perform analog-to-digital conversion, is an input of the second digital-to-analog converter70, but not its single input. The skilled person will then understand that the input72is an analog input corresponding to an additional input, known per se for a SAR ADC module, of said digital-to-analog converter70, and not the digital input intended to receive the digital signal for conversion to an analog signal. The additional input72is configured for receiving a reference voltage used to normalize said digital input. In the example ofFIG. 2, said reference voltage corresponds to the signal delivered by the second adder50to the second SAR ADC module38, i.e. corresponds to the sum of signals(z)+E1(z).

The second SAR ADC module38also includes a second comparator76with two inputs78A,78B, namely a first input78A and a second input78B, and an output80. One input of the second comparator76, such as the first input78A, is connected to the output74of the second digital-to-analog converter70and the other input, such as the second input78B, is adapted to receive a reference signal, such a second reference voltage Vref2. The output80of the second comparator76forms the output42of the second SAR ADC module38.

The second SAR ADC module38further includes a second successive approximation register logic unit82, also called second SAR logic unit82and denoted SAR2, connected to the output80of the second comparator76, the second SAR logic unit82being adapted to control the second digital-to-analog converter70.

The second feedback module44includes a second filter84for filtering the second residue signal E2(z) before injecting it, as a second filtered residue signal(z), back at input40of the second SAR ADC module38.

The digital cancellation logic unit52is for example configure to apply the first transfer function H1(z) to the first digital signal D1(z) and the second transfer function H2(z) to the second digital signal D2(z), according to the following equation:
Dout(z)=H1(z)·D1(z)+H2(z)·D2(z)  [Math 1]

where Doutrepresents the digital output signal,

H1represents the first transfer function,

D1represents the first digital signal,

H2represents the second transfer function, and

D2represents the second digital signal.

The first digital signal D1(z) verifies for example the following equation:
D1(z)=STF1(z)·Vin(z)+NTF1(z)·E1(z)  [Math 2]

where D1represents the first digital signal,

STF1represents a first signal transfer function,

Vinrepresents the analog input signal,

NTF1represents a first noise transfer function, and

E1represents the first residue signal.

The second digital signal D2(z) verifies for example the following equation:
D2(z)=STF2(z)·E1(z)NTF2(z)·E2(z)  [Math 3]

where D2represents the second digital signal,

STF2represents a second signal transfer function,

E1represents the first residue signal,

NTF2represents a second noise transfer function, and

E2represents the second residue signal.

According to aforementioned equations (1), (2) and (3), the digital output signal Dout(z) verifies the following equation, written in a condensed manner:
Dout(z)=H1·[STF1·Vin(z)+NTF1·E1(z)]+H2·[STF2·E1(z)+NTF2·E2(z)]  [Math 4]

thereby leading to the following equation, written in a condensed manner:
Dout(z)=H1·STF1·Vin(z)+[H1·NTF1+H2·STF2]·E1(z)+H2·NTF2·E2(z)  [Math 5]

Therefore, according to equation (5), the following equation is verified so as to cancel the first residue signal E1(z):
H1(z)·NTF1(z)+H2(z)·STF2(z)=0  [Math 6]

In the example ofFIG. 2, the first digital-to-analog converter54, denoted C-DAC1, contains a first capacitor array86.

The first filter68is preferably a Finite Impulse Response filter, also called FIR filter, and accordingly denoted FIR1.

The first filter68is preferably a second-order filter.

The first noise transfer function NTF1(z) typically verifies the following equation:
NTF1(z)=1−HF1(z)  [Math 7]

where NTF1represents the first noise transfer function, and

HF1represents a transfer function of the first filter68.

In the example ofFIG. 2, the first filter68is preferably a second-order FIR filter. According to this example, the first filter68includes a first gain unit88for applying a gain G1to the first residue signal E1(z), a first first-stage delay unit90with gain a1connected to output of the first gain unit88, a first second-stage delay unit92with gain a2connected to output of the first first-stage delay unit90, and a third adder94connected to both outputs of the first first-stage delay unit90and the first second-stage delay unit92.

According to this example, the transfer function of the first filter68verifies the following equation:
HF1(z)=G1·(a1z−1+a2z−2)  [Math 8]

An ideal first noise transfer function NTF1(z) for second order noise shaping verifies the following equation, which requires G1=2, a1=1 and a2=−0.5 as parameter values:
NTF1(z)=(1−z−1)2[Math 9]

In the example ofFIG. 2, the second digital-to-analog converter70, denoted C-DAC2, contains a second capacitor array96.

The second filter84is preferably a Finite Impulse Response filter, also called FIR filter, and accordingly denoted FIR2.

The second filter84is preferably a second-order filter.

The second noise transfer function NTF2(z) typically verifies the following equation:
NTF2(z)=1−HF2(z)  [Math 10]

where NTF2represents the second noise transfer function, and

HF2represents a transfer function of the second filter84.

In the example ofFIG. 2, the second filter84is preferably a second-order FIR filter. According to this example, the second filter84includes a second gain unit98for applying a gain G2to the second residue signal E2(z), a second first-stage delay unit100with gain b1connected to output of the second gain unit98, a second second-stage delay unit102with gain b2connected to output of the second first-stage delay unit100, and a fourth adder104connected to both outputs of the second first-stage delay unit100and the second second-stage delay unit102.

According to this example, the transfer function of the second filter84verifies the following equation:
HF2(z)=G2·(b1z−1+b2z−2)  [Math 11]

An ideal second noise transfer function NTF2(z) for second-order noise-shaping verifies the following equation, which requires G2=2, b1=1 and b2=−0.5 as parameter values:
NTF2(z)=(1−z−1)2[Math 12]

Assuming that the first and second signal transfer functions STF1(z), STF2(z) are ideal and verify the following equation:
STF1(z)=STF2(z)=1  [Math 13]

and also considering that the first transfer function Ht(z) verifies the following equation:
H1(z)=1  [Math 14]

then aforementioned equations (6) and (9) lead to the following equation:
H2(z)=−NTF1(z)=−(1−z−1)2[Math 15]

Therefore, in this example and according to equations (5), (6) and (12) to (15), the digital output signal Dout(z) verifies the following equation:
Dout(z)=Vin(z)−(1−z−1)4·E2(z)  [Math 16]

Thus, the aforementioned equation (16) confirms that when each feedback module30,44includes a respective second-order filter68,84for filtering the respective residue signal E1(z), E2(z) before injecting it back at input of the respective SAR ADC module24,38, the analog-to-digital converting device10according to the invention provides a fourth-order noise-shaping performance.

The analog-to-digital converting device10according to the invention therefore allows obtaining improved results in comparison with state-of-the-art analog-to-digital converting devices, as it will be explained hereinafter in view ofFIGS. 3 and 4.

FIG. 3is a set of two curves200,210, namely a first curve200and a second curve210, each curve200,210representing a simulated power spectral density of the digital output signal Doutdelivered by the analog-to-digital converting device10, the first curve200corresponding to the linear model ofFIG. 1and the second curve210corresponding to the time-domain behavioral model ofFIG. 2.

FIG. 3therefore shows the power spectral density of the linear model and the behavioral model of the invention and demonstrates similar results for the two realizations. The 80 dB/Dec slope of each curve200,210further proves the fourth-order noise-shaping performance of the analog-to-digital converting device10according to the invention.

FIG. 4is a set of two pairs300,310of curves, namely a first pair300and a second pair310, each pair300,310representing a time-domain error signal and respectively a filtered error signal for the second NS-SAR ADC stage18. The first pair300corresponds to the linear model ofFIG. 1and the second pair310corresponds to the time-domain behavioral model ofFIG. 2.

InFIG. 4, the first pair300includes a third curve300A representing the time-domain error signal and a fourth curve300B representing the filtered error signal for the second NS-SAR ADC stage18, according to the linear model ofFIG. 1. Similarly, the second pair310includes a fifth curve310A representing the time-domain error signal and a sixth curve310B representing the filtered error signal for the second NS-SAR ADC stage18, according to the time-domain behavioral model ofFIG. 2.

FIG. 4therefore compares the time-domain error signal of the second NS-SAR ADC stage18for the two realizations. It also shows how filtering affects this error. As can be seen, it adds some noise to the analog-to-digital converting device10, but it is not significant and cannot destroy the performance of the analog-to-digital converting device10.

Thus, the analog-to-digital converting device10according to the invention offers several advantages in comparison to conventional noise-shaping successive approximation register analog-to-digital converters, as it will explained hereinafter.

First, the analog-to-digital converting device10according to the invention obtains a higher noise-shaping order by cascading NS-SAR ADC stages16,18with a lower noise-shaping order capability and without stability concerns.

Then, extra circuit components are not required for the extraction of the error signal in the first NS-SAR ADC stage16to feed it as the input of the second NS-SAR ADC stage18. So, the analog-to-digital converting device10has a simpler architecture because the analog error signal E1(z), E2(z) already exists on the respective digital-to-analog converter54,70, such as on the respective capacitor array86,96, at the end of a conversion. Further, the analog error signal E1(z) of the first digital-to-analog converter54, such as on the first capacitor array86, is usable as the input of the second NS-SAR ADC stage18.

This also makes the analog-to-digital converting device10according to the invention more precise than conventional MASH converters, because of removing a digital-to-analog conversion of the respective output28,42of SAR ADC module24,38, i.e. the quantizer's output, and also because of removing a subtracting step.

Further, each NS-SAR ADC stage16,18provides a digital signal, namely the respective first and second digital signals D1(z), D2(z), with a specific resolution, so that the analog-to-digital converting device10allows providing two different resolutions simultaneously, namely a first resolution corresponding to the first operating mode M1wherein the digital output signal Dout(z) delivered is the first digital signal D1(z), and a second resolution corresponding to the second operating mode M2wherein the digital output signal Dout(z) delivered is a combination of the first and second digital signals D1(z), D2(z), for example at output of the digital cancellation logic52.

The analog-to-digital converting device10according to the invention also offers flexibility for changing the noise-shaping order and resolution using a combination of the different NS-SAR ADC stages16,18, in particular via the selection module22, which is able to select an operating mode from the first operating mode M1and the second operating mode M2of the multiplexer module20. Therefore, the analog-to-digital converting device10provides a reconfigurable resolution architecture.

In addition, there is no restriction on the type of the feedback modules30,44, such as loops, loop filters or FIR filters, in the NS-SAR ADC stages16,18.

Further, the noise-shaping is performed by an error feedback technique, and the analog-to-digital converting device10according to the invention is no longer using operational transconductance amplifier (OTA). In other words, the analog-to-digital converting device10offers preferably an OTA-free topology.