Semiconductor device, electronic device module and network system

A semiconductor device includes an adjusting circuit that transmits a control signal to a device to be controlled according to a transmission cycle synchronized with a reference clock. The device to be controlled has a first period during which the control signal is allowed to be supplied to the device to be controlled and a second period during which the supplying of the control signal to the device to be controlled is not preferable compared to that in the first period. The adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese patent application No. 2014-262577, filed on Dec. 25, 2014, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The present disclosure relates to a semiconductor device, and can be suitably used, for example, for a semiconductor device that generates a signal to control a device used in a time-synchronized distributed system.

In a distributed system including a plurality of elements (nodes) connected to a network, each of the plurality of nodes operates based on its local clock. In some implementations, in order to accomplish synchronization of events occurring in the plurality of nodes, for example, the distributed system may need to time-synchronize the plurality of nodes (i.e., their local clocks). The time synchronization of the distributed system is accomplished by frequently exchanging messages (information) among the plurality of nodes in the distributed system. Typically, any one of the nodes in the distributed system that is predetermined or dynamically selected serves as a master clock node. The local clock of the master clock node is called a master clock. The master clock node exchanges messages (information) with other nodes (slave clock nodes) in the distributed system and thus each slave clock node synchronizes its local clock (i.e., slave clock) with the master clock.

Precision Time Protocol (PTP), which is defined in IEEE Standard 1588, is one of the representative examples of a time synchronization method of the distributed system. Further, generalized PTP (gPTP) defined in IEEE Standard 802.1AS, which is one of the standards that constitute Ethernet Audio/Video Bridging (AVB), is known as a time synchronization method using the PTP. The gPTP defines a time synchronization method in IEEE 802.3 network (i.e., Wired LAN) and IEEE 802.11 network (i.e., Wireless LAN). In the PTP, the master clock node is called a ground master clock and the slave clock node is called a clock slave. In order to accurately synchronize with the ground master clock, the clock slave exchanges messages (i.e., Sync, Follow_Up, Delay_Request, and Delay_Response) with the ground master clock, calculates network delay time based on the transmission time and the reception time of these messages, and adjusts its local clock using the calculated network delay time.

The distributed system that requires the time synchronization is, for example, a manufacturing system including an industrial robot and a metrology device therefor, a surveillance system including networked surveillance cameras, and an automotive camera system. The automotive camera system includes a surround view camera system, a bird view camera system, and a side view camera system. This automotive camera system uses a plurality of cameras and processes images taken by the plurality of cameras to assist parking, detect obstacles and the like.

Japanese Patent Application Publication No. 2005-286453 discloses a technique for synchronizing in time a plurality of cameras, each connected to a network, using a synchronization procedure similar to the PTP.

SUMMARY

As described above, a slave clock node in a distributed system exchanges messages with a master clock node via a network to synchronize its local clock (i.e., the slave clock) with the master clock. However, the frequency of a local clock oscillator (e.g., a crystal oscillator) within the slave clock node is naturally different from the frequency of a local clock oscillator (i.e., the master clock) within the master clock node due to initial manufacturing tolerances, changes in temperature and pressure, and aging degradation. Further, the network delay time varies due to forwarding delay jitter in networking devices (e.g., hubs and switches (bridges) in the IEEE 802.3 network) that connects nodes. In order to compensate for a decrease in the synchronization accuracy due to these unstable factors, the slave clock node continuously exchanges messages with the master clock node and corrects a local clock offset according to the results of the exchange of the messages.

When there is a time difference between the slave clock time and the master clock time, the offset (positive or negative value) is added to the slave clock time to cancel the time difference. The slave clock time may greatly vary due to the processing for adjusting the slave clock. That is, the slave clock time jumps backward when the slave clock time advances the master clock time and otherwise the slave clock time jumps forward.

Such a change in the slave clock time may cause a problem when the slave node controls a device using the slave clock. In particular, when the device to be controlled has timing constraints, the change in the slave clock time may have an influence on the operation of the device to be controlled. Assume a case, for example, in which the slave clock node generates a periodic synchronization signal (e.g., pulse signal) to be supplied to the device to be controlled according to the slave clock (local clock) time-synchronized with the master clock. When the slave clock time changes discontinuously, the phase of (the transmission cycle of) the synchronization signal changes discontinuously according to the change in the slave clock time, and the change in the phase of (the transmission cycle of) the synchronization signal may have an influence on the operation of the device to be controlled.

One example of the device to be controlled having the timing constraints is an image sensor device equipped with a Complementary Metal Oxide Semiconductor (CMOS)/Charge Coupled Device (CCD) image sensor. In one implementation, the image sensor device expects the reception of the synchronization signal of one frame period (e.g., 1/30 seconds) or one field period (e.g., 1/60 seconds) in order to control a shutter timing of the image sensor, an output of a pixel signal by the image sensor and image signal processing by an image signal processor (ISP). In this case, change in the phase of (the transmission cycle of) the synchronization signal may cause degradation or lack of the pixel signal and an image generated based on the pixel signal. In the case of an automotive camera system including a plurality of image sensor devices, if an image taken by one of the image sensor devices is degraded, the system may lack information on an obstacle that should be detected.

In the following description, a plurality of embodiments which can contribute to solution of at least one of problems including the aforementioned problem will be described. It should be noted that the aforementioned problem is merely one of problems that will be solved by the embodiments disclosed in this specification. Other problems and novel features will be apparent from the description of the specification and the accompanying drawings.

In one embodiment, a semiconductor device includes an adjusting circuit that transmits a control signal to a device to be controlled according to a transmission cycle synchronized with a reference clock. The device to be controlled has a first period during which the control signal is allowed to be supplied to the device to be controlled and a second period during which the supplying of the control signal to the device to be controlled is not preferable compared to that in the first period. The adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period.

In another embodiment, a semiconductor device is configured to generate a control signal to be supplied to a device to be controlled according to a transmission cycle synchronized with a reference clock. The semiconductor device further operates as follows when the timing for transmitting the control signal according to the transmission cycle no longer meets timing constraints of the device to be controlled due to a change in a phase of the transmission cycle. That is, the semiconductor device is configured to suppress transmission of the control signal that does not meet the timing constraints and transmit the control signal using a permissible range of the transmission timing within the timing constraints.

The above embodiments contribute to the solution of the aforementioned problem.

DETAILED DESCRIPTION

Specific embodiments will be described in detail with reference to the drawings. The same or corresponding elements are denoted by the same reference symbols throughout the drawings and repeated descriptions will be omitted as appropriate for the sake of clarification of the description.

First Embodiment

FIG. 1shows a configuration example of a network system (distributed system)1according to this embodiment. The network system1includes a plurality of nodes connected to a network40. These nodes perform time synchronization using distributed clock synchronization (e.g., PTP or gPTP). In some implementations, the network system1may be an automotive camera system. In the example shown inFIG. 1, a plurality of camera modules10, a master clock20, and an Electronic Control Unit (ECU)30are connected to the network40. The master clock20operates as a master clock node for distributed clock synchronization and each camera module10operates as a slave clock node. Each camera module10exchanges messages (information, signals and the like) with the master clock20to synchronize its local clock (slave clock) with a local clock of the master clock20. The master clock20may have a radio-controlled clock that receives standard time radio waves to synchronize the local clock of the master clock20with accurate reference time (real time) or may have a radio receiver to synchronize the local clock of the master clock20with a Global Positioning System (GPS) satellite or a mobile telephone base station.

Local clocks included in the plurality of camera modules10synchronize in time with the common master clock20, the plurality of camera modules10can capture images according to the common clock. The ECU30communicates with the camera modules10via the network40, controls the camera modules10to capture images, and receives the captured images obtained by the camera modules10. In some implementations, in order to assist parking, the ECU30may process images taken by the camera modules10substantially at the same time, generate a surround view image or a bird view image, and then display it on a display31. Further, in some implementations, the ECU30may use images taken by the camera modules10substantially at the same time to detect an obstacle. The ECU30is a computer system including at least one processor (e.g., microprocessor or microcontroller) and, in one implementation, may include one or more Integrated Circuit (IC) chips.

The network40may include an IEEE 802.3 network (i.e., Wired LAN), an IEEE 802.11 network (i.e., Wireless LAN), or a combination thereof. In these cases, the network40may include at least one switch (or hub) that relays Media Access Control (MAC) frames transmitted or received by a plurality of nodes including the camera modules10, the master clock20, and the ECU30.

Note that the configuration example shown inFIG. 1is merely one example and may be changed as appropriate. For example, the ECU30may also communicate with the master clock20and synchronize a local clock of the ECU30with the local clock of the master clock20. Alternatively, the master clock20may be integrally formed with the ECU30or, in other words, the hardware and function of the master clock20may be included in the ECU30. In one more alternative, the hardware and function of the master clock20may be included in at least one of the camera modules10.

In the following description, the configuration and the operation of each camera module10will be described in detail.FIG. 2is a Block diagram showing a configuration example of the camera module10. In the example shown inFIG. 2, the camera module10includes a PHY circuit100, a sensor controller120, and an image sensor device140. For example, although not shown inFIG. 2, the sensor controller120and the image sensor device140are mounted on a mounted substrate (e.g., wiring board, interposer substrate, and motherboard) and are electrically connected to each other via wirings formed on the mounted substrate. The PHY circuit100performs signal processing conforming to a physical layer (PHY layer) of the network40and transmits and receives physical layer signals to and from the network40.

The image sensor device140includes an image sensor141(e.g., CMOS image sensor or CCD image sensor) and an Image Signal Processor (ISP)142. The ISP142controls image capturing by the image sensor141, receives a pixel signal generated by the image sensor141, performs digital signal processing including color correction and white balance correction on the pixel signal, and thereby generates an image signal.

The sensor controller120is connected to the PHY circuit100and is configured to communicate with other network nodes including the master clock20and the ECU30via the network40. In order to perform this communication, in the configuration example shown inFIG. 2, the sensor controller120includes a network interface121. The network interface121includes a MAC unit122and a network protocol stack123. The MAC unit122provides, to the network protocol stack123, MAC layer (data link layer) services (i.e., signal processing and control) including media access control, error check, and assembly and disassembly of the MAC frames. The network protocol stack123provides services in layers (e.g., network layer and transport layer) higher than the MAC layer. In some implementations, the network protocol stack123may support the Internet Protocol (IP), the Transmission Control Protocol (TCP), and the User Datagram Protocol (UDP).

The sensor controller120is further configured to support the distributed clock synchronization and generate the local clock (slave clock) time-synchronized with the master clock20. In order to perform the distributed clock synchronization, in the configuration example shown inFIG. 2, the sensor controller120includes a Phase Locked Loop (PLL)124, a timestamp unit (TSU)125, a Central Processing Unit (CPU)126, and a memory127. The CPU126controls the PLL124to generate a local clock synchronized with the phase and frequency of the master clock20. The TSU125receives the local clock generated by the PLL124and generates local timestamps time-synchronized with the absolute time (real time) of the master clock20. The CPU126controls the TSU125to perform an offset correction for aligning its timestamps with timestamps generated by the master clock20.

The CPU126loads and executes software (programs) for the distributed clock synchronization (e.g., a PTP or gPTP program module) stored in the memory127and thereby controls the PLL124and the TSU125. In some implementations, the CPU126exchanges messages with the master clock20via the network interface121, calculates a network delay and the time difference between the local clock time and the absolute time of the master clock20, and controls the PLL124and the TSU125to correct the time difference. The memory127includes a volatile memory and a non-volatile memory. The volatile memory is, for example, a Static Random Access Memory (SRAM), a Dynamic RAM (DRAM), or a combination thereof. The non-volatile memory is, for example, a mask Read Only Memory (MROM), a Programmable ROM (PROM), a flash memory, or any combination thereof.

Further, the sensor controller120is configured to control the image capturing by the image sensor device140according to the local clock time (local timestamps generated by the TSU125) time-synchronized with the master clock20. Specifically, the sensor controller120supplies a synchronization signal150to the image sensor device140periodically with a transmission cycle according to the local clock time, which is time-synchronized with the master clock20. In order to achieve this purpose, the sensor controller120includes an adjusting circuit130. The adjusting circuit130includes a control circuit131and a signal generator132. The control circuit131determines the transmission cycle of the synchronization signal150based on the local time stamp supplied from the TSU125. The signal generator132generates the synchronization signal150according to the timing indicated by the control circuit131and supplies the synchronization signal150to the image sensor device140. The image sensor device140controls a shutter timing of the image sensor141, output of the pixel signal by the image sensor141and the image signal processing by the ISP142according to the periodic synchronization signal150. Although the transmission cycle (period) of the synchronization signal150depends on the image sensor device140, one frame period (e.g., 1/30 seconds) or one field period (e.g., 1/60 seconds) is typically employed as the transmission cycle (period) of the synchronization signal150.

Further, the sensor controller120is configured to receive the image signal that has been generated by the image sensor device140and transmit the received image signal to the ECU30via the network40. The network interface121receives the image signal from the image sensor device140and transmits the received image signal to the ECU30via the network40.

As already described above, in order to keep the time synchronization of the slave clock included in the sensor controller120, it is required to compensate for a degradation in the synchronization accuracy due to various uncertain factors (e.g., manufacturing tolerance of a local clock oscillator (crystal oscillator), frequency drift due to temperature, aging degradation, and delay jitter in a network). Therefore, the sensor controller120(CPU126) continuously exchanges messages with the master clock20and corrects the slave clock time (the PLL124and the TSU125). Specifically, when there is a time difference between the slave clock time and the master clock time, the sensor controller120adds the offset (positive or negative value) to the slave clock time to cancel the time difference.

However, as already described above, the slave clock time may greatly vary due to the processing for adjusting the slave clock. Such a change in the slave clock time may cause a problem when the sensor controller120controls the image sensor device140using the slave clock time. Specifically, the phase of (the transmission cycle of) the synchronization signal150also changes discontinuously according to the change in the slave clock time, and the change in the phase may have an influence on the operation of the image sensor device140. This is because, since the image sensor device140expects to periodically receive the synchronization signal150(e.g., one frame period (e.g., 1/30 seconds) or one field period (e.g., 1/60 seconds)) and controls the image sensor141and the ISP142according to the periodic synchronization signal150, the change in the phase of (the transmission cycle of) the synchronization signal150may cause degradation or lack of the pixel signal and the image signal generated based on the pixel signal. In the following description, the influence of the phase change in the synchronization signal150on the operation of the image sensor device140will be described, and the operation of the adjusting circuit130to reduce this influence will also be described.

FIG. 3is a diagram showing one example of timing constraints imposed on the image sensor device140. A transmission cycle300shown inFIG. 3shows one example of the transmission cycle of the synchronization signal150and a synchronization signal waveform320shows one example of the periodic synchronization signal150. In the example shown inFIG. 3, a period P1of the transmission cycle300is one frame period ( 1/30 seconds, i.e., about 33.3 milliseconds) and pulses302and304indicate transmission timings of the synchronization signal. The synchronization signal waveform320according to the transmission cycle300is a pulse wave having a period of 1/30 seconds (about 33.3 milliseconds) and includes pulses322and324.

A state340of the image sensor device140shown inFIG. 3indicates the timing constraints of the image sensor device140. That is, the state340includes an acceptable period (342,346) and an unacceptable period (344) that are alternately repeated. The acceptable period (342,346) means a period during which the image sensor device140can accept the synchronization signal150(i.e., synchronization signal pulses322and324shown inFIG. 3) or, in other words, the image sensor device140expects to receive the synchronization signal150. It can also be said that the acceptable period (342,346) is a preferred period for the image sensor device140to normally operate or is a period during which the image generated by the image sensor device140is not degraded. As shown inFIG. 3(362,364), the image sensor device140reads out (or outputs) the pixel signal from the image sensor141upon receiving the synchronization signal150(i.e., synchronization signal pulses322,324).

On the other hand, the unacceptable period (344) means a period during which it is not preferable to receive the synchronization signal150(i.e., synchronization signal pulses322and324inFIG. 3) in the image sensor device140. It can be said that the unacceptable period (344) is a period during which it is inappropriate to receive the synchronization signal150, a period during which the normal operation of the image sensor device140is not guaranteed, or a period during which the image generated by the image sensor device140is degraded. Although the image sensor device140is able to receive the synchronization signal150in the unacceptable period (344), the pixel signal and the image generated based on the pixel signal may be degraded or lost. In some implementations, the acceptable period (342,346) corresponds to a vertical blanking period in which the pixel signal is read out (or output) from each pixel of the image sensor141and the unacceptable period (344) corresponds to an exposure period (accumulation period) in which charge accumulation is performed in each pixel of the image sensor141. In this case, it can be said that the synchronization signal150specifies a “readout pulse” that indicates timing for reading out the pixel signal.

The timing constraints of the image sensor device140include a maximum length (PA) of the acceptable periods (342,346) and a predetermined length (PB) of the unacceptable period (344). As shown inFIG. 3, the unacceptable period (344) is a fixed period having a predetermined length PB (e.g., about 32.3 milliseconds) shorter than the transmission cycle of the synchronization signal150(e.g., one frame period, that is about 33.3 milliseconds). Now, a difference D (e.g., 1 millisecond) between the transmission cycle length of the synchronization signal150and the predetermined length of the unacceptable period (344) will be defined. Meanwhile, the acceptable period (342,346) is a non-fixed period that begins after the unacceptable period (344) and ends upon receiving the synchronization signal150(pulses322and324). The maximum length PA of the acceptable period (342,346) is equal to or longer than the difference D (e.g., 1 millisecond) but equal to or shorter than the length PB of the unacceptable period (344). In one example, the maximum length PA of the acceptable period may be twice as long as the difference D (e.g., 2 milliseconds).

FIG. 4shows an operation example of the image sensor device140when the above timing constraints are violated. In the example shown inFIG. 4, the phase of the transmission cycle400changes due to any factor such as adjustment of the slave clock time. Specifically, the phase of the transmission cycle400changes after a pulse402and thus the interval between the pulse402and a pulse404becomes shorter than the length (PB) of the unacceptable period. Note that a pulse406shown by a dashed line shows a normal transmission timing which would arrive next to the pulse402according to the normal period P1of the transmission cycle if the change in the phase of the transmission cycle did not occur.

A synchronization signal waveform420shown inFIG. 4shows transmission timings of the synchronization signal150when it is assumed that the timing adjustment of the synchronization signal150by the sensor controller120(adjusting circuit130) is not performed. That is, a synchronization signal pulse422is generated according to the transmission timing402before the phase change and a synchronization signal pulse424is generated according to the transmission timing404after the phase change. When the synchronization signal pulse424is transmitted, the image sensor device140is still in the unacceptable period (444). In one implementation, the image sensor device140interrupts the unacceptable period (444) and starts a new unacceptable period446, interrupts the readout (or output) of a pixel signal462, and attempts to output a new pixel signal according to the transmission cycle after the phase change. However, since the amount of electric charges accumulated in the pixels of the image sensor141is not sufficiently large, a pixel signal output464may degrade or lost.

In order to prevent the problem described with reference toFIG. 4, the sensor controller120(adjusting circuit130) according to this embodiment operates as follows.FIG. 5is a flowchart showing processing500that is one example of the processing performed by the adjusting circuit130. In Block501, according to the real time clock (e.g., local timestamp information supplied from the TSU125), the control circuit131in the adjusting circuit130detects the transmission timing of the synchronization signal150synchronized with the real time clock. As already described above, the transmission cycle of the synchronization signal150is normally constant. However, when the slave clock (local clock) is corrected to time-synchronize with the master clock20, the phase of the transmission cycle of the synchronization signal150may be changed.

In Block502, the control circuit131determines whether the transmission timing of the synchronization signal150is within the acceptable period of the image sensor device140. The determination in Block502may be performed by determining whether the time elapsed since the last transmission timing (transmission time of the synchronization signal150) is equal to or longer than the length PB of the unacceptable period of the image sensor device140.

When the detected transmission timing is within the acceptable period of the image sensor device140(YES in Block502), the control circuit131triggers the signal generator132to generate the synchronization signal150according to the detected transmission cycle. Accordingly, the signal generator132transmits the synchronization signal150according to the detected transmission cycle (Block503).

On the other hand, when the detected transmission timing is outside the acceptable period of the image sensor device140(NO in Block502), the control circuit131adjusts the transmission timing of the synchronization signal150so that the synchronization signal150will be transmitted within the acceptable period of the image sensor device140. As one example, the control circuit may operate as follows. The control circuit131suppresses transmission of the synchronization signal150outside the acceptable period. Further, the control circuit131triggers the signal generator132to transmit the synchronization signal150in a vicinity of the beginning of the acceptable period or in a vicinity of the end of the acceptable period based on the maximum length PA. Accordingly, the signal generator132transmits the synchronization signal150in the vicinity of the beginning of the acceptable period or in the vicinity of the end of the acceptable period regardless of the detected transmission cycle (Block504).

When the phase of the transmission cycle has been greatly changed, the adjusting circuit130can make the phase of the acceptable period of the image sensor device140approach the phase of the transmission cycle of the synchronization signal150step by step by repeating the processing shown inFIG. 5, especially the processing of Block504. In other words, the adjusting circuit130repeatedly transmits the synchronization signal150in the acceptable period of the image sensor device140, thereby making the transmission timing of the synchronization signal150gradually approach the transmission timing according to the real time clock (transmission cycle) after the correction. Consequently, the image sensor device140can follow the transmission cycle of the synchronization signal150after the phase change.

In the following description, with reference toFIGS. 6 and 7, specific examples of the operations of the adjusting circuit130when the transmission cycle phase of the synchronization signal150has been changed will be described.FIG. 6shows a case in which the transmission cycle phase of the synchronization signal150has been advanced. The case shown inFIG. 6occurs when, for example, the slave clock time jumps forward by a correction since the slave clock time lags behind the master clock time. In the example shown inFIG. 6, the phase of a transmission cycle600changes after a pulse602and thus the interval between the pulse602and a pulse604is shorter than the length (PB) of the unacceptable period. A pulse606which is shown by a dashed line indicates a normal transmission timing which would arrive next to the pulse602according to the normal period P1of the transmission cycle if the change in the phase of the transmission cycle did not occur.

A synchronization signal waveform620shown inFIG. 6shows how the timing adjustment of the synchronization signal150is performed by the adjusting circuit130. That is, the adjusting circuit130generates a synchronization signal pulse622according to the transmission timing602before the phase change. The position of the synchronization signal pulse622corresponds to an acceptable period642in a state640of the image sensor device140. The image sensor device140starts an output of the pixel signal (662) in response to the reception of the synchronization signal pulse622and makes a transition to an unacceptable period644in which the charge accumulation in the image sensor141is executed.

Next, the adjusting circuit130suppresses transmission of a synchronization signal pulse624according to the transmission timing604after the phase change. This is because the transmission timing604and the synchronization signal pulse624based on the transmission timing604are within the unacceptable period (644) in the state640of the image sensor device140. The adjusting circuit130promptly transmits a synchronization signal pulse626in a vicinity of the beginning of an acceptable period646that follows the unacceptable period644. The image sensor device140starts an output of the pixel signal (664) in response to the reception of the synchronization signal pulse626and makes a transition to an unacceptable period648in which the charge accumulation in the image sensor141is executed.

It should be noted with respect toFIG. 6that the transmission timing of the synchronization signal pulse626goes ahead of the pulse606shown by the dashed line, which is the normal transmission timing which would arrive next to the pulse602according to the normal period P1of the transmission cycle if the change in the phase of the transmission cycle did not occur. Therefore, by repeating the operation shown inFIG. 6by step by step, the phase of the acceptable period after the acceptable period646gradually advances and, consequently, the phase of the acceptable period can be adjusted to the phase of the transmission cycle after the phase change.

FIG. 7shows a case in which the transmission cycle phase of the synchronization signal150is delayed. The case shown inFIG. 7occurs when the slave clock time jumps backward due to a correction since the slave clock time advances the master clock time. In the example shown inFIG. 7, the phase of a transmission cycle700changes after a pulse702and thus the interval between the pulse702and a pulse706is longer than the sum of the length of the unacceptable period and the maximum length of an acceptable period746(i.e., PB+PA). A pulse704shown by a dashed line shows the normal transmission timing which would arrive next to the pulse702according to the normal period P1of the transmission cycle if the change in the phase of the transmission cycle did not occur.

A synchronization signal waveform720inFIG. 7shows how the timing adjustment of the synchronization signal150is performed by the adjusting circuit130. That is, the adjusting circuit130generates a synchronization signal pulse722according to the transmission timing702before the phase change. The position of the synchronization signal pulse722corresponds to an acceptable period742in a state740of the image sensor device140. The image sensor device140starts an output of the pixel signal (762) in response to the reception of the synchronization signal pulse722and makes a transition to an unacceptable period744in which the charge accumulation in the image sensor141is executed.

Next, when the transmission timing does not arrive around the transmission timing704expected base on the last transmission timing702, or in the acceptable period746, the adjusting circuit130transmits a synchronization signal pulse724in a vicinity of the end of the acceptable period746determined based on the maximum length PA. The image sensor device140starts an output of the pixel signal (764) in response to the reception of the synchronization signal pulse724and makes a transition to an unacceptable period748in which the charge accumulation in the image sensor141is executed. The adjusting circuit130suppresses transmission of the synchronization signal pulse726according to the transmission timing706after the phase change. This is because the transmission timing706and the synchronization signal pulse726based on the transmission timing706are within the unacceptable period (748) in the state740of the image sensor device140.

It should be noted with respect toFIG. 7that the transmission timing of the synchronization signal pulse724lags behind the pulse704shown by the dashed line, which is the normal transmission timing which would arrive next to the pulse702according to the normal period P1of the transmission cycle if the change in the phase of the transmission cycle did not occur. Therefore, by repeating the operation shown inFIG. 7by step by step, the phase of the acceptable period after the acceptable period746gradually delays and, consequently, the phase of the acceptable period can be matched to the phase of the transmission cycle after the phase change.

As will be understood from the above description, the adjusting circuit130is configured to, when the transmission timing of the synchronization signal150determined according to the transmission cycle does not meet the timing constraints of the image sensor device140, that is, when the transmission timing of the synchronization signal150is within the unacceptable period of the image sensor device140, adjust the transmission timing of the synchronization signal150so that the synchronization signal150will be transmitted within the acceptable period of the image sensor device140. In one example, the adjusting circuit130may be configured to suppress transmission of the synchronization signal150that does not meet the timing constraints of the image sensor device140and to transmit the synchronization signal150using the permissible range of the transmission timing within the timing constraints. By repeating this operation, the adjusting circuit130or the sensor controller120including the adjusting circuit130can gradually shift the phase of the acceptable period of the synchronization signal150conforming to the timing constraints so that the phase of the acceptable period approaches the phase of the transmission cycle after the phase change. Consequently, the image sensor device140can eventually follow the transmission cycle of the synchronization signal150after the phase change. The adjusting circuit130and the sensor controller120including the adjusting circuit130can thus follow the phase change of the transmission cycle of the synchronization signal150due to the correction or the like of the slave clock time, while avoiding degradation and lack of the image generated by the image sensor device140due to violation of the timing constraints of the image sensor device140.

Second Embodiment

In this embodiment, a specific example of the configuration and the operation of the adjusting circuit130described in the first embodiment will be described. The configuration examples of the network system and the sensor controller according to this embodiment may be similar to those shown inFIGS. 1 and 2described in the first embodiment.

FIG. 8is a Block diagram showing a configuration example of the adjusting circuit130. In the example shown inFIG. 8, the adjusting circuit130includes a memory805, in addition to the control circuit131and the signal generator132. The memory805includes a volatile memory or a combination of a volatile memory and a non-volatile memory. The memory805stores configuration data used by the control circuit131and the signal generator132and also stores data generated by the control circuit131.

More specifically, the memory805stores configuration information including the maximum value PA of the acceptable period of the image sensor device140, the predetermined length PB of the unacceptable period of the image sensor device140, and the drive period and the polarity of the synchronization signal150. The memory805further stores an arrival time T1of the transmission cycle based on the slave clock time and an immediately previous generation time S0of the synchronization signal150. The arrival time T1and the generation time S0are generated by the control circuit131. The control circuit131measures the arrival time T1and the generation time S0based on the local time in the control circuit131generated by a time controller802that will be described later.

The control circuit131shown inFIG. 8includes a reception determination unit801, a time controller802, a timing adjustment unit803, and an ignore flag generation unit804. In one implementation, the reception determination unit801receives from the TSU125the local timestamps indicating the absolute time (real time) synchronized with the master clock20and determines the arrival of the predetermined transmission cycle of the synchronization signal150based on the local timestamp. In another implementation, the reception determination unit801may receive a timing signal indicating the transmission cycle based on the slave clock time synchronized in time with the master clock time and determine the arrival of the transmission cycle of the synchronization signal150based on the timing signal. As one example, this timing signal may be a pulse signal such as transmission cycle waveforms (300,400,600and700) shown inFIGS. 3, 4, 6 and 7. In this case, the TSU125or a circuit coupled to the TSU125may generate the timing signal.

The reception determination unit801measures the arrival time T1of the transmission cycle of the synchronization signal150based on the local time generated by the time controller802and stores the measured arrival time T1in the memory805. The operation of the reception determination unit801varies according to whether the arrival time T1of the transmission cycle is within the acceptable period of the image sensor device140.

The timing adjustment unit803and the ignore flag generation unit804collaborate with the reception determination unit801and execute the transmission timing adjustment of the synchronization signal150described in the first embodiment. The ignore flag generation unit804manages the state of an ignore flag (ignore_flg) indicating whether to ignore the arrival of the transmission cycle of the synchronization signal150in the reception determination unit801.

FIGS. 9A and 9Bare flowcharts showing processing900that is an example of processing performed by the adjusting circuit130shown inFIG. 8. Blocks901to905are executed by the reception determination unit801. In Block901, the reception determination unit801receives timestamp information indicating the slave clock synchronized in time with the master clock20or receives the timing signal based on the slave clock time, and determines the arrival of the transmission cycle of the synchronization signal150. As described above, the timing signal maybe a pulse signal indicating the transmission timing of the synchronization signal150.

In response to the arrival of the transmission cycle of the synchronization signal150(YES in Block901), processing of Blocks902to906are executed. Otherwise these processing are skipped. In Block902, the reception determination unit801acquires, from the memory805, the maximum length (PA) of the acceptable period of the image sensor device140, the predetermined length (PB) of the unacceptable period of the image sensor device140, and the immediately previous generation time (S0) of the synchronization signal150. In Block903, the reception determination unit801determines whether the current local time (T) supplied from the time controller802is within the acceptable period of the image sensor device140(i.e., S0+PB<T<=S0+PB+PA).

When the local time (T) is within the acceptable period (YES in Block903), the reception determination unit801stores in the memory805the arrival time (T1) of the transmission cycle of the synchronization signal150based on the local time (T) (Block905). On the other hand, when the local time (T) is outside the acceptable period (NO in Block903), the reception determination unit801checks the state of the ignore flag (ignore_flg) (Block904). When the value of the ignore flag is zero (YES in Block904), the reception determination unit801stores in the memory805the arrival time (T1) of the transmission cycle of the synchronization signal150based on the local time (T) (Block905). When the value of the ignore flag is 1 (NO in Block904), the reception determination unit801does not store in the memory805the arrival time (T1) of the transmission cycle of the synchronization signal150.

Block906is executed by the ignore flag generation unit804. The ignore flag generation unit804sets (clears) the ignore flag to the value zero in Block906.

Blocks907to915except for Block913are executed by the timing adjustment unit803. Block913is executed by the ignore flag generation unit804. In Block907, the timing adjustment unit803acquires, from the memory805, the maximum length (PA) of the acceptable period of the image sensor device140, the predetermined length (PB) of the unacceptable period of the image sensor device140, the immediately previous generation time (S0) of the synchronization signal150, and the arrival time (T1) of the transmission cycle of the synchronization signal150. In Block908, the timing adjustment unit803determines whether the current local time (T) supplied from the time controller802is within the acceptable period of the image sensor device140(i.e., S0+PB<T<=S0+PB+PA). When the local time (T) is not in the acceptable period (NO in Block908), the processing of Block909to916are skipped, the adjusting circuit130updates the local time (T) (Block917), and the processing goes back to Block901.

On the other hand, when the local time (T) is within the acceptable period (YES in Block908), the timing adjustment unit803further checks the arrival time (T1) of the transmission cycle (Blocks909and910). More specifically, when the arrival time (T1) of the transmission cycle is before the acceptable period of the image sensor device140(i.e., S0<T1<=S0+PB) (YES in Block909), the timing adjustment unit803generates a trigger signal (sync_trg) to generate the synchronization signal150and supplies the trigger signal (sync_trg) to the signal generator132(Block914). The timing adjustment unit803stores in the memory805the generation time (S0) of the trigger signal (sync_trg) based on the local time (T) (Block915). This corresponds to the case in which the phase of the transmission cycle of the synchronization signal150is advanced, as described with reference toFIG. 6.

When the arrival time (T1) of the transmission cycle is within the acceptable period of the image sensor device140(i.e., S0+PB<T1<=S0+PB+PA) (YES in Block910), the timing adjustment unit803supplies the trigger signal (sync_trg) to the signal generator132to generate the synchronization signal150(Block914). The timing adjustment unit803stores in the memory805the generation time (S0) of the trigger signal (sync_trg) based on the local time (T) (Block915). This corresponds to the case in which the phase of the transmission cycle of the synchronization signal150is normal, as described with reference toFIG. 3.

When neither the determination condition in Block909(i.e., S0<T1<=S0+PB) nor the determination condition in Block910(i.e., S0+PB<T1<=S0+PB+PA) is satisfied and the local time (T) has reached the end (maximum length PA) of the acceptable period of the image sensor device140(i.e., T=S0+PB+PA, YES in Block911), the timing adjustment unit803generates a delay trigger signal (delay_trg) (Block912) and also generates a trigger signal (sync_trg) to generate the synchronization signal150(Block914). The timing adjustment unit803stores in the memory805the generation time (S0) of the trigger signal (sync_trg) based on the local time (T) (Block915). This corresponds to the case in which the phase of the transmission cycle of the synchronization signal150is delayed, as described with reference toFIG. 7. The ignore flag generation unit804sets the ignore flag (ignore_flg) to the value1in response to receiving the delay trigger signal (delay_trg) (Block913).

In Block916, in response to receiving the trigger signal (sync_trg) from the timing adjustment unit803, the signal generator132generates and supplies the synchronization signal150to the image sensor device140. In Block917, the time controller802updates the local time (T).

According to the configuration and the operation of the adjusting circuit130described in this embodiment, it is possible to obtain effects substantially the same as those in the adjusting circuit130described in the first embodiment.

Third Embodiment

In this embodiment, another specific example of the configuration and the operation of the adjusting circuit130described in the first embodiment will be described. The configuration examples of the network system and the sensor controller according to this embodiment may be similar to those shown inFIGS. 1 and 2.

In this embodiment, an improvement of the method for adjusting the transmission timing of the synchronization signal150is provided. In the method described in the first and second embodiments, when the transmission cycle phase of the synchronization signal150has been advanced, the adjusting circuit130repeats the operation of transmitting the synchronization signal150in the vicinity of the beginning of the acceptable period of the image sensor device140, thereby gradually advancing the phase of the acceptable period and, consequently, the phase of the acceptable period is adjusted to the transmission cycle phase of the synchronization signal150. This method may be not efficient, however, when the phase of the transmission cycle of the synchronization signal150has been greatly advanced. This is because the phase difference at most equal to the predetermined length (PB) of the unacceptable period has to be adjusted. Similarly, this method may be not efficient when the phase of the transmission cycle of the synchronization signal has been greatly delayed.

In order to address this problem, the method for adjusting the transmission timing of the synchronization signal150according to this embodiment is executed as follows. That is, when the phase of the transmission cycle of the synchronization signal150is greatly (e.g., a half or more of the length PB of the unacceptable period) advanced, the adjusting circuit130repeats the operation of transmitting the synchronization signal150in the vicinity of the end, determined based on the maximum length (PA), of the acceptable period of the image sensor device140. That is, in contrast to the operations in the first and second embodiments, the phase of the acceptable period is gradually delayed and, consequently, the phase of the acceptable period is eventually adjusted to the transmission cycle phase of the synchronization signal150.

FIG. 10is a diagram showing one example of the method for adjusting the transmission timing of the synchronization signal150according to this embodiment.FIG. 10shows a case in which the transmission cycle phase of the synchronization signal150is advanced by a half or more of the length PB of the unacceptable period. In the example shown inFIG. 10, the phase of a transmission cycle1000changes after a pulse1002and thus the interval between the pulse1002and a pulse1004is a half or less of the length (PB) of the unacceptable period.

A synchronization signal waveform1020shown inFIG. 10shows how the timing adjustment of the synchronization signal150is performed in the adjusting circuit130. That is, the adjusting circuit130generates a synchronization signal pulse1022according to the transmission timing1002before the phase change. The position of the synchronization signal pulse1022corresponds to an acceptable period1042in a state1040of the image sensor device140. The image sensor device140starts an output of the pixel signal (1062) in response to the reception of the synchronization signal pulse1022and makes a transition to an unacceptable period1044where the charge accumulation in the image sensor141is executed.

Next, the adjusting circuit130suppresses transmission of a synchronization signal pulse1024in response to the transmission timing1004after the phase change. This is because the transmission timing1004and the synchronization signal pulse1024based on the transmission timing1004are within an unacceptable period (1044) in the state1040of the image sensor device140.

The above description regardingFIG. 10is similar to the description regardingFIG. 6according to the first embodiment. However, the following processing of the adjustment method shown inFIG. 10is different from the adjustment method shown inFIG. 6. That is, the adjustment method shown inFIG. 6described above includes promptly transmitting the synchronization signal pulse626in the vicinity of the beginning of the acceptable period646, which follows the unacceptable period644. Meanwhile, the adjustment method shown inFIG. 10includes transmitting a synchronization signal pulse1026in the vicinity of the end, determined based on the maximum length PA, of an acceptable period1046following the unacceptable period1044.

That is, in the method shown inFIG. 10, when the interval from the immediately previous transmission time (S0) of the synchronization signal to the arrival time of the next transmission cycle is shorter than a half of the length (PB) of the unacceptable period, the adjusting circuit130gradually delays the phase of the acceptable period instead of gradually advancing the phase of the acceptable period. Accordingly, the phase difference that should be adjusted by the adjusting circuit130is about a half of the length (PB) of the unacceptable period at most. Therefore, according to the method shown inFIG. 10, when the transmission cycle phase of the synchronization signal150has been greatly varied, the transmission cycle phase of the synchronization signal150can be matched to the phase of the acceptable period of the image sensor device130more promptly.

FIG. 11is an example when the change of the transmission cycle phase of the synchronization signal150is small. More specifically, in the example shown inFIG. 11, the phase of a transmission cycle1100is changed after a pulse1102and the interval between the pulse1102and a pulse1104is larger than a half of the length (PB) of the unacceptable period but equal to or smaller than PB. Since the operation of the case shown inFIG. 11is similar to that ofFIG. 6, the detailed description will be omitted. That is, the transmission cycle1100, the pulse1102, and the pulse1104shown inFIG. 11respectively correspond to the transmission cycle600, the pulse602, and the pulse604shown inFIG. 6. Further, a synchronization signal waveform1120, a pulse1122, a pulse1124, and a pulse1126shown inFIG. 11respectively correspond to the synchronization signal waveform620, the pulse622, the pulse624, and the pulse626shown inFIG. 6. Further, a state1140, an acceptable period1142, an unacceptable period1144, an acceptable period1146, an unacceptable period1148, a pixel signal output1162, and a pixel signal output1164of the image sensor device shown inFIG. 11respectively correspond to the state640, the acceptable period642, the unacceptable period644, the acceptable period646, the unacceptable period648, the pixel signal output662, and the pixel signal output664shown inFIG. 6.

In the following description, a specific example of the configurations and the operations of the adjusting circuit130to execute the timing adjustment method of the synchronization signal150described in this embodiment will be described.FIG. 12is a

Block diagram showing a configuration example of the adjusting circuit130. In the example shown inFIG. 12, the adjusting circuit130includes a memory1205, in addition to the control circuit131and the signal generator132. The control circuit131shown inFIG. 12includes a reception determination unit1201, a time controller1202, and a timing adjustment unit1203. As will be clear from the comparison betweenFIG. 8andFIG. 12, the ignore flag generation unit804is omitted in the configuration example shown inFIG. 12. In order to execute the timing adjustment method of the synchronization signal150described in this embodiment, the operations of the reception determination unit1201and the timing adjustment unit1203are different from those of the reception determination unit801and the timing adjustment unit803shown inFIG. 8. The operation of the time controller1202may be similar to that of the time controller802.

FIGS. 13A and 13Bare flowcharts showing processing1300that is one example of processing performed by the adjusting circuit130shown inFIG. 12. Blocks1301to1304are executed by the reception determination unit1201. The processing of Block1301may be similar to the processing of Block901shown inFIG. 9A.

In response to the arrival of the transmission cycle of the synchronization signal150(YES in Block1301), processing of Blocks1302to1304are executed. Otherwise, these processing are skipped. In Block1302, the reception determination unit1201acquires, from the memory1205, the predetermined length (PB) of the unacceptable period of the image sensor device140and the immediately previous generation time (S0) of the synchronization signal150. In Block1303, the reception determination unit1201determines whether the current local time (T) supplied from the time controller1202is within the former part of the unacceptable period of the image sensor device140(i.e., S0<T<=S0+PB/2).

When the local time (T) is not within the former part of the unacceptable period (NO in Block1303), the reception determination unit1201stores in the memory1205the arrival time (T1) of the transmission cycle of the synchronization signal150based on the local time (T) (Block1304). On the other hand, when the local time (T) is within the former part of the unacceptable period (YES in Block1303), the reception determination unit1201does not store in the memory1205the arrival time (T1) of the transmission cycle of the synchronization signal150.

Blocks1305to1311are executed by the timing adjustment unit1203. The processing of Blocks1305and1306may be similar to the processing of Blocks907and908shown inFIG. 9B. When the local time (T) is not within the acceptable period (NO in Block1306), the processing of Blocks1307to1311are skipped, the adjusting circuit130updates the local time (T) (Block1313), and the processing goes back to Block1301.

On the other hand, when the local time (T) is within the acceptable period (YES in Block1306), the timing adjustment unit1203further checks the arrival time (T1) of the transmission cycle (Blocks1307and1308). Specifically, when the arrival time (T1) of the transmission cycle is within the latter part (i.e., S0+PB/2<T1<=S0+PB) of the unacceptable period of the image sensor device140(YES in Block1307), the timing adjustment unit1203generates the trigger signal (sync_trg) and supplies the trigger signal (sync_trg) to the signal generator132to generate the synchronization signal150(Block1310). The timing adjustment unit1203stores in the memory1205the generation time (S0) of the trigger signal (sync_trg) based on the local time (T) (Block1311). This corresponds to the case described with reference toFIG. 11.

When the arrival time (T1) of the transmission cycle is within the acceptable period of the image sensor device140(i.e., S0+PB<T1<=S0+PB+PA) (YES in Block1308), the timing adjustment unit1203supplies the trigger signal (sync_trg) to the signal generator132to generate the synchronization signal150(Block1310). The timing adjustment unit1203stores in the memory1205the generation time (S0) of the trigger signal (sync_trg) based on the local time (T) (Block1311). This corresponds to the case in which the phase of the transmission cycle of the synchronization signal150is normal, as described with reference toFIG. 3.

When neither the determination condition in Block1307(i.e., S0+PB/2<T1<=S0+PB) nor the determination condition in Block1308(i.e., S0+PB<T1<=S0+PB+PA) is satisfied and the local time (T) has reached the end (maximum length PA) of the acceptable period of the image sensor device140(i.e., T=S0+PB+PA, YES in Block1309), the timing adjustment unit1203supplies the trigger signal (sync_trg) to the signal generator132to generate the synchronization signal150(Block1310). The timing adjustment unit1203stores in the memory1205the generation time (S0) of the trigger signal (sync_trg) based on the local time (T) (Block1311). This corresponds to the case in which the phase of the transmission cycle of the synchronization signal150is delayed, as described with reference toFIG. 7, and the case in which the transmission cycle phase has been greatly advanced, as described with reference toFIG. 10.

The processing of Blocks1312and1313may be similar to the processing of Blocks916and917shown inFIG. 9B.

Fourth embodiment

In this embodiment, modification of the configuration and the operation of the adjusting circuit130described in the third embodiment will be described. The configuration examples of the network system and the sensor controller according to this embodiment may be similar to those shown inFIGS. 1 and 2described in the first embodiment.

FIG. 14is a Block diagram showing a configuration example of the adjusting circuit130. In the example shown inFIG. 14, the adjusting circuit130includes a memory1405, in addition to the control circuit131and the signal generator132. The control circuit131shown inFIG. 14includes a reception determination unit1401, a counter controller1402, and a timing adjustment unit1403. As will be clear from the comparison betweenFIG. 12andFIG. 14, in the configuration example shown inFIG. 14, the time controller1202is replaced by the counter controller1402. In accordance therewith, the timing adjustment unit1403needs not store the generation time (S0) of the synchronization signal150in the memory1405. Further, the reception determination unit1401supplies the synchronization flag (sync_flg) indicating the arrival of the transmission cycle to the timing adjustment unit1403, thereby eliminating the need to store the arrival time (T1) of the transmission cycle of the synchronization signal150in the memory1405.

According to the configuration example shown inFIG. 14, there is no need to store the immediately previous generation time (S0) of the synchronization signal150and the arrival time (T1) of the transmission cycle in the memory1405. Accordingly, the size of the circuit can be reduced compared to that in the configuration example shown inFIG. 12described in the third embodiment.

FIGS. 15A and 15Bshow a flowchart showing processing1500that is one example of processing performed by the adjusting circuit130shown inFIG. 14. The processing of Block1501may be similar to the processing of Block901shown inFIG. 9Aor the processing of Block1301shown inFIG. 13A.

The processing of Blocks1502to1504is substantially the same as the processing of Blocks1302to1304except for some changes therein due to the employment of the counter controller1402. That is, in response to the arrival of the transmission cycle of the synchronization signal150(YES in Block1501), the processing of Blocks1502to1504are executed, and otherwise this processing is skipped. In the Block1502, the reception determination unit1401acquires the predetermined length (PB) of the unacceptable period of the image sensor device140from the memory1405. In Block1503, the reception determination unit1401determines whether the counter value (T) corresponding to the current local time supplied from the counter controller1402is within the former part of the unacceptable period of the image sensor device140(i.e., 0<T<=PB/2).

When the counter value (T) is not within the former part of the unacceptable period (NO in Block1503), the reception determination unit1401sets the synchronization flag (sync_flg) to the value 1 to notify the timing adjustment unit1403of the arrival of the transmission cycle of the synchronization signal150(Block1504). On the other hand, when the counter value (T) is within the former part of the unacceptable period (YES in Block1503), the reception determination unit1401does not set the synchronization flag (sync_flg).

Blocks1505to1509are executed by the timing adjustment unit1403. In Block1505, the timing adjustment unit1403acquires, from the memory1405, the predetermined length (PB) of the unacceptable period and the maximum length (PA) of the acceptable period of the image sensor device140. In Block1506, the timing adjustment unit1403determines whether the current counter value (T) supplied from the counter controller1402is within the acceptable period of the image sensor device140(i.e., PB<T<=PB+PA). When the counter value (T) is not within the acceptable period (NO in Block1506), the processing of Blocks1507to1511are skipped, the adjusting circuit130updates the counter value (T) (i.e., local time) by incrementing the counter in the counter controller1402(Block1513), and the processing goes back to Block1501.

On the other hand, when the counter value (T) is within the acceptable period (YES in Block1506), the timing adjustment unit1403further checks the value of the synchronization flag (sync_flg). Specifically, when the value of the synchronization flag (sync_flg) is 1 (YES in Block1507), the timing adjustment unit1403generates a trigger signal (sync_trg) and supplies the trigger signal (sync_trg) to the signal generator132to generate the synchronization signal150(Block1509). That the value of the synchronization flag (sync_flg) is 1 corresponds to the case in which the arrival time (T1) of the transmission cycle is within the latter part of the unacceptable period of the image sensor device140(i.e., S0+PB/2<T1<=S0+PB) or the case in which the arrival time (T1) of the transmission cycle is within the acceptable period (i.e., S0+PB<T1<=S0+PB+PA). Therefore, this corresponds to the case described with reference toFIG. 11or the case described with reference toFIG. 3.

When the value of the synchronization flag (sync_flg) is 0 (NO in Block1507) and the counter value (T) has reached the end (maximum length PA) of the acceptable period of the image sensor device140(i.e., T=PB+PA, YES in Block1508), the timing adjustment unit1403supplies the trigger signal (sync_trg) to the signal generator132to generate the synchronization signal150(Block1509). This corresponds to the case in which the phase of the transmission cycle of the synchronization signal150has been delayed, as described with reference toFIG. 7, and the transmission cycle phase has been greatly advanced, as described with reference toFIG. 10.

The synchronization flag (sync_flg) is set (cleared) to the value zero after the trigger signal (sync_trg) has been generated. The processing of Block1511may be similar to the processing of Block916shown inFIG. 9Bor the processing of Block1312shown inFIG. 13B. In Block1512, upon generating the synchronization signal1511, the counter controller1402sets (resets) the counter that measures the local time to the value zero.

In the configurations and the operations described with reference toFIGS. 14, 15A and 15B, the counter controller1402operates to count from 0 to PB+PA. In one implementation, a state signal that indicates the acceptable period and the unacceptable period of the image sensor device140may be newly provided and the counter controller1402may count the acceptable period from 0 to PA and the unacceptable period from 0 to PB. In this case, in Block1503shown inFIG. 15A, besides determining whether the counter value (T) is 0<T<=PB/2, the reception determination unit1401may further determine whether the state signal indicates the unacceptable period. On the other hand, in Block1506inFIG. 15B, the timing adjustment unit1403may only determine whether the state signal indicates the acceptable period. Further, in Block1508inFIG. 15B, the timing adjustment unit1403may determine whether the counter value (T) is PA (T=PA) and the state signal indicates the acceptable period. It is therefore possible to eliminate an adder (PB+PA) to calculate the sum of PB and PA in the timing adjustment unit1403.

Other Embodiments

The processing of the control circuit131described in the above embodiments may be achieved by causing a computer system including at least one processor to execute a program. More specifically, one or more programs including instructions to cause a computer system to execute the algorithm described in the specification using the drawings including the flowcharts may be created and this program(s) maybe supplied to the computer system. The program(s) can be stored and provided to a computer using any type of non-transitory computer readable media. Non-transitory computer readable media include any type of tangible storage media. Examples of non-transitory computer readable media include magnetic storage media (such as flexible disks, magnetic tapes, hard disk drives, etc.), optical magnetic storage media (e.g., magneto-optical disks), Compact Disc Read Only Memory (CD-ROM), CD-R, CD-R/W, and semiconductor memories (such as mask ROM, Programmable ROM (PROM), Erasable PROM (EPROM), flash ROM, Random Access Memory (RAM), etc.). The program may be provided to a computer using any type of transitory computer readable media. Examples of transitory computer readable media include electric signals, optical signals, and electromagnetic waves. Transitory computer readable media can provide the program to a computer via a wired communication line (e.g., electric wires, and optical fibers) or a wireless communication line.

In the above embodiments, cases in which the device to be controlled is an image sensor device have been mainly described. However, the technical idea described in the above embodiments may be widely used to control a device to be controlled having timing constraints other than the image sensor device.

The above-described embodiments can be combined as appropriate or desirable by one of ordinary skill in the art.