Circuitry and methods for common-mode rejection calibration

Circuitry and methods are disclosed that may employ common mode calibration circuitry configured to at least partially calibrate out impedance differences or mismatches between the differential signal paths of differential signal circuitry. The common mode calibration circuitry may be integrated as an internal part of integrated differential signal circuitry that includes a differential amplifier to reject common mode noise, and may be used to reduce or substantially eliminate any external and/or internal difference in signal path resistance that exists between the differential signal paths of the integrated differential signal circuitry. A common mode calibration signal may be internally or externally applied to the signal inputs of differential signal circuitry, and used to determine a setting for the common mode calibration circuitry that at least partially calibrates out impedance differences or mismatches between the differential signal paths of differential signal circuitry.

FIELD OF THE INVENTION

This disclosure generally relates to common-mode rejection, and more particularly to circuitry for calibration of common mode rejection.

BACKGROUND OF THE INVENTION

Electrically noisy environments such as automobiles, factories, or other locations with large amounts of equipment in operation, typically use differential amplifiers to reject noise that couples onto both the positive and negative leads of an analog input. The noise, common to both the positive and negative input leads, is rejected by a differential amplifier.

FIG. 1illustrates conventional integrated analog audio front end circuitry100that includes differential programmable gain amplifier (PGA) circuitry120which rejects common mode noise and that is coupled to receive positive and negative input signals from multiplexer circuitry102and to provide positive and negative output signals to analog to digital converter (ADC)114. Multiplexer circuitry102is present to select among multiple analog differential audio input source pairs1041to104N, each of which includes respective positive and negative signal input pads103and105that provide a respective input for positive and negative signal lines of a given analog audio source. As shown, multiplexer circuitry102includes input multiplexer switching elements S1that are provided for selectively and separately coupling each individual differential source104one at a time to the differential programmable gain amplifier120as shown.

As further shown inFIG. 1, each of positive and negative input signal lines of the differential programmable gain amplifier120includes a respective input resistor R1that is coupled to gain control circuit components and differential amplifier106of circuitry120. Gain control circuit components include variable resistors R2that may be selectively coupled in parallel within a respective signal line in response to a control signal provided by a microcontroller (not shown).

Any resistive mismatches between the positive and negative signal paths of analog audio front end circuitry100that are present in external or internal integrated circuitry components will degrade the ability of differential PGA circuitry120to reject common-mode noise. In the past, permanently trimmable components, such as resistors or fuses, have been provided in each of the positive and negative signal paths of such circuitry, and laser trimming or fuse trimming was used to correct for integrated resistive mismatches.

SUMMARY OF THE INVENTION

Disclosed herein are circuitry and methods that may employ common mode calibration circuitry configured to at least partially calibrate out (i.e., reduce or substantially eliminate) impedance differences or mismatches between the differential signal paths of differential signal circuitry. Advantageously, the disclosed common mode calibration circuitry may be adjustable and readjustable in real time to at least partially calibrate and recalibrate out any impedance mismatches (e.g., such as due to resistive, capacitive, and/or inductive mismatches) between the differential signal paths of differential signal circuitry as conditions and/or impedance mismatches change, e.g., such as when external source of a differential signal changes, gain changes, and/or when the differential signal circuitry is powered down and then powered up again.

In one embodiment, common mode calibration circuitry may be integrated as an internal part of integrated differential signal circuitry e.g., such as integrated analog signal front end circuitry that employs a differential amplifier to reject common mode noise. In such an integrated configuration, any external and/or internal difference in signal path impedance between the differential signal paths of integrated differential signal circuitry may be internally reduced or substantially eliminated by applying an internal or external common mode calibration signal to the differential signal paths, while at the same time controlling variable impedance circuit elements of the integrated common mode calibration circuitry within at least one of the signal paths of the differential signal circuitry to calibrate out any impedance difference or mismatch between the signal path pair that manifests itself as a DC value at the output of the differential amplifier while the calibration signal is applied. The disclosed circuitry and methods may be particularly useful when implemented with other circuitry for digitization of analog signals received in an electrically noisy environment, such as automobiles, factories, etc. Moreover, unlike conventional permanently trimmable resistors or fuses, variable impedance elements of the disclosed common mode calibration circuitry may be temporarily adjusted and then later readjusted in one or both of the positive or negative signal paths as conditions or signal inputs change, e.g., to allow impedance to be increased and then later decreased in a given signal path, or vice versa, as with a change in signal inputs.

Advantageously, in one embodiment integrated variable impedance elements (e.g., such as variable resistance elements, variable capacitance elements, variable inductance elements, etc.) that are integrated within a differential signal circuit may be automatically controlled to initially calibrate out and/or later re-calibrate out differences in signal path impedance between a pair of analog differential signal paths as circuit configurations or other conditions change, e.g., as external input signal sources to the integrated circuit are changed over time. In this regard, any external and/or internal differences in signal path impedance between differential signal paths may be automatically and internally calibrated out using integrated variable impedance elements (e.g., such as variable resistance elements, variable capacitance elements, variable inductance elements, etc.) based at least in part on an external common mode reference or calibration signal that is applied to a pair of differential signal inputs of the integrated circuit. In another exemplary embodiment, an integrated common mode calibration signal source may be provided to supply an internal common mode calibration signal to internal differential signal paths of an integrated differential signal circuit, and any internal differences in signal path impedance between differential signal paths may be automatically and internally calibrated out using integrated variable impedance elements based at least in part this internal common mode calibration signal. Thus, the disclosed circuits and methods may be implemented in one exemplary embodiment in a low cost manner to improve the common-mode rejection ratio of an integrated circuit, and in another exemplary embodiment to provide a simple, integrated, and automatic method to calibrate out external differences in signal path impedance.

In one exemplary embodiment, more than one type of impedance mismatch may be at least partially calibrated out using sequential calibration operations, e.g., by first applying a common mode calibration signal and adjusting variable resistive elements to at least partially calibrate out any resistive mismatches, and then applying a common mode sine wave calibration signal and adjusting variable capacitive elements to at least partially calibrate out any capacitive mismatches.

In one respect, disclosed herein is differential signal circuitry having at least one differential input source configured to receive positive and negative signal components of an analog differential signal pair. The differential circuitry may include: a differential amplifier having a positive input coupled to receive the positive signal of the analog differential signal pair across a positive signal path from the differential input source, and a negative input coupled to receive the negative signal of the analog differential signal pair across a negative signal path from the differential input source; and common mode calibration circuitry coupled within at least one of the positive signal path or negative signal path between the differential input source and the inputs of the differential amplifier, the common mode calibration circuitry being configured to programmably vary the impedance of at least one of the positive signal path or negative signal path to reduce any difference in signal path impedance between the positive and negative signal paths.

In another respect, disclosed herein is a method of calibrating positive and negative signal paths of differential signal circuitry that includes a differential amplifier having a positive input coupled to receive a positive signal of an analog differential signal pair across a positive signal path from a differential input source, and that has a negative input coupled to receive a negative signal of the analog differential signal pair across a negative signal path from the differential input source. The method may include using common mode calibration circuitry to programmably vary the impedance of at least one of the positive signal path or negative signal path to reduce any difference in signal path impedance between the positive and negative signal paths.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 2illustrates a block diagram of differential signal circuitry200as it may be configured according one embodiment of the disclosed circuitry and methods. In one exemplary embodiment, circuitry200may be integrated analog audio front end circuitry, such as may be an integrated part of automotive radio tuner and/or amplifier circuitry. However, it will be understood that the disclosed circuitry and methods may be implemented with other types of differential signal circuitry, e.g., such as circuitry configured to receive analog data signals from electronic sensors or other instrumentation or circuitry (e.g., such as dynamic signal analyzers, industrial control loops, geophones, downhole well logging tools, avionics, etc.), circuitry for receiving analog audio signals from microphones, accelerometers or other sources, etc. In one embodiment described further herein in relation toFIG. 3, all components of differential signal circuitry200may be integrated on a single semiconductor chip. However, in other embodiments separate components of differential signal circuitry200may be partitioned between multiple semiconductor chips or implemented using other separate (e.g., external) and/or discrete circuitry configurations.

As shown inFIG. 2, circuitry200includes differential programmable gain amplifier (PGA) circuitry220that is coupled to receive positive and negative input signals from multiplexer circuitry202and to provide positive and negative output signals to analog to digital converter (ADC)214, which in turn produces digital output signals295for further processing by other circuitry. Differential PGA circuitry220may include gain control circuitry components as will be described further herein. It will be understood that although differential signal circuitry200includes multiplexer circuitry202in this embodiment, in other embodiments multiplexer circuitry202may be implemented using external or off-chip circuitry, and in yet other embodiments no multiplexer circuitry is required to be present. Moreover, it is not necessary that differential PGA circuitry220output differential signals directly to an ADC214as shown, but rather other circuitry may be coupled to receive differential signals that are output by differential PGA circuitry220.

Still referring toFIG. 2, readjustable and programmable common mode calibration circuitry216is coupled between multiplexer circuitry202and differential PGA circuitry220in each of positive and negative (+ and −) signal paths of differential signal circuitry200. As will be described further below, common mode calibration circuitry216may be controlled in real time (e.g., by an integrated on-chip microcontroller260or by one or more other suitable internal or external processing device and/or other control circuitry) to programmably (e.g., temporarily and selectively) tune or otherwise vary the resistance and/or other impedance value (e.g., such as capacitance) in each of positive and/or negative signal paths relative to each other in order to calibrate out any difference (mismatch) in signal path resistance and/or other type of impedance difference between the positive and negative signal paths, e.g., such that the electrical circuit resistance and/or other type of electrical circuit impedance of each of the positive and negative signal paths between the location of an injected internal or external common mode calibration signal and differential differential PGA circuitry220is substantially the same. Examples of signal path imbalances that may cause such resistive mismatches include, but are not limited to, series resistor/s provided in only one of the positive or negative signal paths, mismatched resistors in the positive and negative signal paths, parallel sections of positive and negative signal paths having different length relative to each other, etc.

Additionally, optional internal common mode calibration signal circuitry294may be provided as shown in the input signal path between multiplexer202and differential PGA circuitry220. Such internal common mode calibration signal circuitry294may be controlled (e.g., by microcontroller260or other suitable processing device) to selectively provide a common mode calibration signal on each of the internal positive and negative signal paths to differential PGA circuitry220while at the same time controlling common mode calibration circuitry216to programmably (e.g., temporarily and selectively) vary the signal path resistance of at least one of the positive and/or negative signal paths relative to each other in order to calibrate out any difference in signal path resistance between the positive and negative signal paths. In this regard, common mode calibration circuitry216may be controlled to programmably vary the difference in signal path resistance between the positive and/or negative signal paths relative to each other until the resulting DC signal value measured at the output of differential amplifier206(e.g., by ADC214) is minimized, e.g., until the signal path resistance of each of the positive and negative internal signal paths is substantially the same. In another embodiment, internal common mode calibration signal circuitry294may be controlled (e.g., by microcontroller260or other suitable processing device) to selectively provide a common mode calibration signal in the form of a sinusoidal wave on each of the internal positive and negative signal paths to differential PGA circuitry220while at the same time controlling common mode calibration circuitry216to programmably vary the difference in signal path capacitance between the positive and/or negative signal paths relative to each other until the resulting DC signal value measured at the output of differential amplifier206(e.g., by ADC214) is minimized.

Also shown inFIG. 2is storage memory261(e.g., non-volatile and/or volatile memory device/s) that are coupled to microcontroller260to allow storage and retrieval of calibration codes or values by microcontroller260for operation of differential signal circuitry200for different circuit states (e.g., PGA220gains, different selected inputs of204via202, control of common mode calibration signal circuitry294, etc.).

FIG. 3illustrates one exemplary of differential signal circuitry200as it may be integrated on a single semiconductor chip, it being understood that other suitable circuit configurations may be alternatively employed. As shown inFIG. 3, multiplexer circuitry202is present to select among multiple analog differential audio input source pairs2041to204N, such as balanced audio signal input pairs that each include positive and negative signal lines from a different analog audio source such as a portable MP3 player, an external CD player, a smart phone, etc. In this regard, each of input sources204may include respective positive and negative signal input pads203and205that provide a respective input for positive and negative signal lines of a given differential analog audio source. In this exemplary embodiment, multiplexer circuitry202includes input multiplexer switching elements S1that are provided for selectively and separately coupling each individual differential source204one at a time in signal communication with differential PGA circuitry220as shown. Switching elements S1of multiplexer circuitry202may be controlled in any suitable manner in response to user or system selection, e.g., by micro-controller260or other suitable processing device/s or control circuitry as illustrated and described in relation toFIG. 2.

As further shown inFIG. 3, each of positive and negative input signal lines of differential PGA circuitry220includes a respective input resistor R1that is coupled to gain control circuit components and differential amplifier206of circuitry220. Gain control circuit components include variable resistors R2that are each configured to be selectively coupled in parallel with capacitor C1and differential amplifier206. In this regard, each of series variable resistors R2may be controlled and selectively coupled into a respective signal line in response to a control signal, e.g., provided by microcontroller260ofFIG. 2. It will be understood that gain control circuitry may alternatively be implemented or integrated within differential amplifier206.

Also shown inFIG. 3is integrated common mode calibration circuitry216coupled between integrated multiplexer circuitry202and integrated differential PGA circuitry220in each of positive and negative signal paths of differential signal circuitry200. In this exemplary embodiment, common mode calibration circuitry216includes a fixed series resistive element R3and multiple selectable parallel resistive elements CR1to CRNthat are each paired with corresponding respective switching elements CS1to CSNin each of positive and negative signal paths of differential signal circuitry200.

In the illustrated configuration, each of resistive elements CR1to CRNmay be individually and selectively inserted within one of the positive and negative signal paths by closing its corresponding paired switching element CS1to SNsuch that it is coupled in parallel with the fixed resistive element R3within of the respective signal path in a manner that alters the electrical resistance of the internal signal path. Similarly, each of resistive elements CR1to CRNmay be individually and selectively removed from one of the positive and negative signal paths by opening its corresponding paired switching element CS1to CSNsuch that it is not coupled in parallel within the respective signal path to further alter the electrical resistance of the corresponding internal signal path. In this way, various combinations of resistive elements may be selectively inserted into one or both of the internal positive and/or negative signal paths of differential signal circuitry200to programmably vary and tune the signal path resistance of each of positive and/or negative signal paths relative to each other in order to substantially equalize the signal path resistance of the signal paths relative to each other e.g., to reduce or substantially eliminate any resistive mismatch between the positive and negative signal paths such that the total signal path resistance in each of the positive and negative signal paths between the point of application of an internal or external calibration signal and ADC214is substantially the same. In one embodiment, each of the switching elements CS1to CSNof positive and negative signal paths may be selectively and individually opened and closed under the control of microcontroller260or other suitable processing device.

AlthoughFIG. 3illustrates and is described with reference to a variable resistance embodiment of common mode calibration circuitry216that includes multiple selectable parallel resistive elements CR1to CRN, it will be understood that in other embodiments common mode calibration circuitry216may additionally or alternatively include other types of impedance elements (e.g., such as selectable parallel or series capacitance elements, varactor/s, selectable parallel or series inductance elements, etc.) that may be programmed to achieve other types of variable impedance adjustment.

Table 1 illustrates exemplary resistance values for parallel resistive elements R3and CR1to CRNas they may be selected in one exemplary embodiment for each of positive and negative signal paths of integrated common mode calibration circuitry216. In the exemplary embodiment of Table 1, one fixed parallel resistance element R3is provided for each signal path that is not removable from the given signal path, and six selectable resistance elements CR1to CR6are provided for each signal path that may be selectively inserted or removed from the given signal paths, e.g., by a corresponding switch CS1to S6as shown inFIG. 3. However, it will be understood that the number of selectable resistive elements CR that are provided in a given positive or negative signal path may vary from a single selectable resistive element to many selectable resistive elements, e.g., more than six selectable resistive elements.

TABLE 1Resistive Element inResistance ValueEach Signal Path(Ohms)Resistor TypeR3100FixedCR19900Selectable with Switch CS1CR24900Selectable with Switch CS2CR32400Selectable with Switch CS3CR41150Selectable with Switch CS4CR5809Selectable with Switch CS5CRN=CR6525Selectable with Switch CSN= S6

In the exemplary embodiment of Table 1, a fixed resistor R3is present in each signal path of calibration circuitry216to provide a baseline maximum resistance of 100 Ohms for each of the positive and negative signal paths, i.e., this condition occurs when all resistor control switches CS1to CS6are open so as to isolate all selectable resistors CR1to CR6from each signal path. Resistance of calibration circuitry within each signal path may be selectively reduced below 100 Ohms by closing one or more of switches CS1to CS6so as to insert any selected combination of respective resistors CR1to CR6in parallel with fixed resistive element R3so as to achieve a desired calibration circuitry resistance for either or both of positive and negative signal paths of circuitry200. For example, inserting one or more of the selectable resistive elements into a first one of the signal paths acts to reduce the calibration circuitry resistance in the first signal path to below 100 Ohms (i.e., by an amount based on the number and identity of inserted the resistors). At the same time, no selectable resistive elements may be inserted into the second one of the signal paths to leave the calibration circuitry resistance in the second signal path at 100 Ohms. In the particular exemplary embodiment of Table 1, the total number and resistance values of the resistive elements provided for each of the positive and negative signal paths has been selected so as to allow each of the positive and negative signal paths to be selectively reduced in 1 Ohm increments from the baseline resistance of 100 Ohms (e.g., to achieve resulting resistance values of 99, 98, 97, etc.). down to a minimum resistance of about 68 as shown in Table 2.

It will be understood that exemplary embodiment ofFIG. 3(as well as the number and particular combination of fixed and selectable resistive element values of Table 1, are exemplary only) and that any other number and/or resistive element values may be provided as needed or desired to fit the characteristics of a given circuit application. For example,FIG. 4illustrates one example alternate embodiment of integrated common mode calibration circuitry216, which includes a selectable resistive element CR1and corresponding resistor control switch CS1that is provided in parallel to selectable series resistive elements CR2to CRNwhich may be selectably and individually inserted and removed from the positive signal path by closing and opening switches CS2to CSN, respectively. As shown, no selectable resistive elements are provided in the negative signal path in this exemplary embodiment, although it is possible that a similar set of selectable resistive elements CR1to CRNand corresponding switches CS1to CSN(or alternatively a different configuration of one or more selectable resistive elements and corresponding resistor control switches) may also be provided in the negative signal path in an alternative embodiment. It is also possible that one or more fixed resistive elements may be provided without selectable resistive elements and corresponding resistor control switches in the negative signal path of circuitry216, or alternatively in combination with selectable resistive elements and corresponding resistor control switches in the negative signal path of circuitry216. Thus, it will be understood that any combination and/or number of selectable resistive elements may be provided in either one of or both of positive and negative signal paths (together with optional fixed resistive elements in either one of or both of positive and negative signal paths) that is suitable for varying the resistance of the positive and negative signal paths relative to each other in order to at least partially calibrate out resistive mismatches between the positive and negative signal paths. As with the embodiment ofFIG. 2, each of selectable switches of the embodiment ofFIG. 4may be controlled by on-chip microcontroller260or by one or more other suitable internal or external processing device and/or other control circuitry.

It will also be understood that in the practice of the disclosed circuits and methods, a given resistive element of any of the circuitry described herein may include a circuit element that provides resistance to the circuit or that acts as a resistor during circuit operations, or any combination of multiple circuit elements that together provide resistance to the circuit or that together act as a resistor during circuit operations. For example, a resistive element may itself be a single resistor, a combination of parallel or series resistors, etc. Moreover, it will be understood that the switching elements of any of the circuitry described herein may be implemented using any suitable switch circuit device or combination of switch circuit devices, e.g., such as PMOS and/or NMOS transistors.

Returning toFIG. 2, differential signal circuitry200may be provided with optional internal common mode calibration signal circuitry294in one exemplary embodiment. As shown, internal common mode calibration signal circuitry294may include a calibration signal (e.g., voltage and/or sinusoidal wave-generating) source290that may be operated (e.g., in response to control signal from microcontroller260) to supply a simultaneous common mode calibration signal to each of positive and negative signal paths of differential signal circuitry200. As further shown, internal common mode calibration signal circuitry294may be further configured to optionally isolate each of positive and negative signal paths of differential signal circuitry200from any external signals applied to pads203and205while it is supplying the common mode calibration signal. As will be described further herein, this internal calibration signal may be used together with common mode calibration circuitry216to calibrate out any internal resistive mismatch (or other impedance mismatch such as capacitive mismatch, inductive mismatch, etc.) between the internal positive and negative signal paths within differential circuitry200from the point of introduction of internal calibration signal from calibration signal source372(e.g., at nodes393and395) to the ADC214, e.g., by measuring the peak differential amplifier output while sweeping through all resistance (e.g., and/or capacitance/inductance) settings of calibration circuitry216until the peak value is minimized or the minimum peak value is identified.

FIG. 3illustrates one exemplary embodiment of integrated internal common mode calibration signal circuitry294as it may implemented within integrated differential signal circuitry200to selectively supply an internal calibration signal to positive and negative signal paths of integrated differential signal circuitry200. In this exemplary embodiment, calibration signal source290may be selectively coupled to, and isolated from, each of the internal positive and negative signal paths of integrated differential signal circuitry200by switching elements SA2as shown, although any other suitable combination of one or more switching elements may be employed. In this embodiment, input multiplexer switching elements S1may be opened to isolate each of internal positive and negative signal paths from any external signals of input sources204during internal calibration testing, although any other suitable circuitry configuration may be employed to isolate each of internal positive and negative signal paths during internal calibration.

Also illustrated inFIG. 3is optional external (non-integrated) common mode calibration signal circuitry370that may be optionally and temporarily coupled to supply an external common mode calibration signal (e.g., a 1 kHz tone) to shorted positive and negative signal paths of integrated differential signal circuitry200via positive and negative signal input pads203and205of a given input source204, e.g., using switching elements SA1and SB1as shown in similar manner as witching elements SA2and SB2, although any other suitable combination of one or more switching elements may be employed. In the illustrated embodiment, external common mode calibration signal circuitry370includes a common mode calibration signal (e.g., voltage and/or sinusoidal wave generating) source372. It will be understood that external common mode calibration signal circuitry370may be selectively coupled at any suitable matching locations of external positive and negative signal paths to allow calibration circuitry216to be used to calibrate out any combined external and internal resistive mismatch (or other impedance mismatch such as capacitive mismatch, inductance mismatch, etc.) between the positive and negative signal paths from the point of introduction of the external calibration signal from calibration signal source370(e.g., at nodes397and399) to the ADC214, e.g., by measuring the peak differential amplifier output while sweeping through all resistance (e.g., and/or capacitance/inductance) settings of calibration circuitry216until the peak value is minimized or the minimum peak value is identified.

For example, optional external differential signal circuitry374having external positive signal path377and external negative signal path379may be coupled to the positive and negative signal input pads203and205of a given input source204of circuitry200as shown. Examples of external differential circuitry374that may create a resistive mismatch include, but are not limited to, resistive voltage divider circuitry provided to reduce differential signal input voltage for high voltage signal sources (e.g., such as shown inFIG. 3), a series resistor/s provided in only one of the positive or negative signal paths to protect electrostatic discharge (ESD) clamp circuitry, mismatched resistors in the positive and negative signal paths, parallel sections of positive and negative signal lines having different length relative to each other, etc. It will be understood that in one embodiment, multiple different external differential circuits374may be selectively coupled to provide a differential pair to integrated differential signal circuitry200a unique and that a different external resistive mismatch may exist between the external positive signal path377and external negative signal path379of each particular configuration of external differential circuitry374, such that the external resistive mismatch between the external positive and negative signal paths377and379must be calibrated out by a different and unique setting of variable resistance of calibration circuitry216using external common mode calibration signal circuitry370.

Still referring to the embodiment ofFIG. 3, any internal and/or external resistive mismatch between the positive and negative signal paths of integrated differential signal circuitry200may be calibrated out in one exemplary embodiment by the steps of methodology500ofFIG. 5, e.g., under the control of microcontroller260or other suitable processing device. In one embodiment, such a calibration procedure may be initiated automatically, e.g., by microcontroller260upon each power up of a system such as radio tuner that includes circuitry200. Alternatively, such a calibration procedure may be initiated upon receipt of a command from an end-user, during integrated chip testing or system fabrication, etc. In yet another embodiment, a calibration procedure may be initiated every time a different input source204is selected for input, a different gain setting is selected for the PGA220, etc. It will be understood that a similar methodology asFIG. 5may be employed additionally or alternatively to at least partially calibrate out any other type of internal and/or external impedance mismatch (e.g., capacitive and/or inductive mismatch) between the positive and negative signal paths of integrated differential signal circuitry200using suitably configured calibration circuitry216.

First, in step502multiplexer circuitry202is controlled to disconnect all external input signals204from the positive and negative inputs of differential signal circuitry200, e.g., by opening all input switching elements S1. Next in optional step503, the positive and negative signal lines of circuitry200may be shorted by closing switching elements SA2with switching element SB2open to isolate calibration signal source290from the shorted signal paths, and the voltage offset (O0) of differential amplifier206may be measured and stored so that it can be subtracted from later measured DC values that result from resistive mismatches between positive and negative signal lines of circuitry200. In one exemplary embodiment, the offset (O0) of differential amplifier206may be separately removed or subtracted at the output of differential PGA circuitry220by ADC214and is therefore not considered when using variable resistance of calibration circuitry216to calibrate out resistive mismatches in later steps.

Next, in step504each of calibration circuitry switching elements SA2and SB2are closed, and calibration source290controlled to supply a common mode calibration signal simultaneously to each of positive and negative signal paths with common mode calibration circuitry216placed in an initial resistance setting. Such an initial resistance setting may be, for example, with all switching elements CS1to CSNopen in each of positive and negative signal paths such that no additional resistance is coupled in parallel to resistive element R3during step504. However, any other initial resistance setting may be arbitrarily or otherwise chosen by closing one or more of switches CS1to CSNin either of the positive and negative signal paths. In methodology500, a common mode calibration signal may be of any minimum or greater magnitude that is suitable for measurement at the output of differential amplifier206when a resistive mismatch is present between the positive and negative signal paths of circuitry200. For example, in one exemplary embodiment, calibration source290may provide a calibration signal that is substantially equal to the maximum allowable common mode voltage that differential amplifier206is capable of handling.

After step504, any resistive mismatch/es that is present between the positive and negative internal signal paths of circuitry200at the initial resistance setting of common mode calibration circuitry216will degrade the ability of differential amplifier206to reject the common-mode signal, resulting in a DC voltage error at the output of differential amplifier206that relative to the magnitude of the mismatch. This output DC voltage may be measured in real time during step506by ADC214, or using other suitable signal measurement circuitry and/or technique. In step508, the optional measured amplifier offset (O0) value from step503may be subtracted from the measured output DC value of step506, and the resulting value recorded or stored in step508, e.g., in non-volatile and/or volatile memory261that is accessible by microcontroller260. In some embodiments, the calibration codes/values for common mode calibration circuitry216(e.g.,FIG. 2) may be stored and held in volatile memory, e.g., such as in those embodiments where methodology500is performed at every system start up.

Next, in step510, the resistance setting of common mode calibration circuitry216may be changed to a new and different setting by altering the condition of at least one of switching elements CS1to CSNin a least one of the positive or negative signal paths from its initial setting used in step506, i.e., to produce a change in relative resistance between the positive and negative signal paths from that present in step506. The resulting new value of output DC voltage may then be measured in real time (e.g., by ADC214) during step512, and recorded or stored in step514in either its actual measured form or after amplifier offset (O0) value of optional step503has been subtracted. As shown in step516, steps510to514repeat until all possible relative resistance settings of common mode calibration circuitry216between the positive and negative signal paths have been tried (i.e., swept through) and their corresponding output DC voltage measured and recorded or stored. Then in step518, the stored resistance settings of common mode calibration circuitry216are compared, and the particular resistance setting of common mode calibration circuitry216that resulted in the minimum absolute value of measured DC voltage (less amplifier offset (O0) value) at the output of differential amplifier206is selected for use. Then, in step520common mode calibration circuitry216is returned to (or left unchanged at) the resistance setting that resulted in the minimum measured DC voltage at the output of differential amplifier206, e.g., by altering the condition of one or more of switching elements CS1to CSNas needed. At this point, calibration methodology500terminates, e.g., until circuitry power down and re-power up, until another calibration run is requested by a user, etc. In one exemplary embodiment, the last resistance setting of common mode calibration circuitry216may be stored in non-volatile memory during system power off conditions, and then retrieved from non-volatile memory and used on the next system start up.

It will be understood that the particular steps (and particular order of steps) of methodology500is exemplary only, and that any other combination of fewer, additional, and/or alternative steps may be employed that is suitable for use with common mode calibration circuitry216to calibrate out (i.e., reduce or substantially eliminate) differences or mismatches between the signal path resistance of the differential positive and negative signal paths of differential signal circuitry200. For example, in one alternative embodiment, output DC voltage of differential amplifier206may be measured at each of the available different resistance settings of common mode calibration circuitry216until all settings have been measured, and then common mode calibration circuitry216may be set at the resistance setting that resulted in the minimum measured DC voltage without requiring storage of any measured values in memory.

It will also be understood that a methodology similar to that ofFIG. 5may be employed using external common mode calibration signal circuitry370ofFIG. 3(e.g., to supply an external common mode calibration signal in step504) together with common mode calibration circuitry216to calibrate out resistive mismatches present in the external and internal positive and negative signal paths (including any resistive mismatches between external positive and negative signal paths in external circuitry374) between the external calibration signal circuitry370and differential amplifier206through a given signal input204. In such an alternative embodiment, it is not necessary that internal common mode calibration signal circuitry294be present, however circuitry configured to selectively short positive and negative paths (e.g., such as integrated switching elements SA2) may be optionally provided if amplifier offset is to be measured and factored in the calibration process, e.g., such as described with respect to steps503and518ofFIG. 5Although a common mode rejection calibration procedure using external common mode calibration signal circuitry370may be performed at any time (including by an end-user), in one embodiment external common mode calibration signal circuitry370may be used to calibrate out resistive mismatches present in the external and internal positive and negative signal paths during production, e.g., at time of circuit or system fabrication or system assembly.

In one exemplary embodiment, different resistance settings for common mode calibration circuitry216that are selected in step518ofFIG. 5for different corresponding external circuit configurations and/or different circuit conditions may be stored in a lookup table or other suitable data form in memory261for later retrieval and use each time a particular corresponding external circuit configuration is selected and/or a particular circuit condition is encountered, e.g., without requiring a repeat performance of calibration methodology500.

It will also be understood that one or more of the tasks, functions, or methodologies described herein (e.g., for microcontroller260) may be implemented, for example, as firmware or other computer program of instructions embodied in a non-transitory tangible computer readable medium that is executed by one or more processing devices such as CPU, controller, microcontroller, processor, microprocessor, FPGA, ASIC, or other suitable processing devices.