Method of forming differential etch stop layer using directional plasma to activate surface on device structure

Methods of forming a differential layer, such as a Contact Etch Stop Layer (CESL), in a semiconductor device are described herein, along with structures formed by the methods. In an embodiment, a structure includes an active area on a substrate, a gate structure over the active area, a gate spacer along a sidewall of the gate structure, and a differential etch stop layer. The differential etch stop layer has a first portion along a sidewall of the gate spacer and has a second portion over an upper surface of the source/drain region. A first thickness of the first portion is in a direction perpendicular to the sidewall of the gate spacer, and a second thickness of the second portion is in a direction perpendicular to the upper surface of the source/drain region. The second thickness is greater than the first thickness.

BACKGROUND

As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a Fin Field Effect Transistor (FinFET). FinFET devices typically include semiconductor fins with high aspect ratios and in which channel and source/drain regions are formed. A gate is formed over and along the sides of the fin structure (e.g., wrapping) utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices. However, with the decreasing in scaling, new challenges are presented.

DETAILED DESCRIPTION

Methods of forming a differential layer, such as a Contact Etch Stop Layer (CESL), in a semiconductor device, such as including a Fin Field-Effect Transistor (FinFET), are described herein, along with structures formed by the methods. Generally, a direction plasma activation process is implemented which permits some portions of a differential layer (e.g., on an upper surface having a horizontal component) to be deposited at a greater rate than other portions (e.g., on a vertical surface without a significant horizontal component). Hence, some portions of the differential layer can have a greater thickness than other portions of the differential layer. The differential layer may permit for greater protection of source/drain regions and/or may increase a process window for the formation of other components or features, among other possible advantages.

Example embodiments described herein are described in the context of forming a CESL on FinFETs. Implementations of some aspects of the present disclosure may be used to form a layer that is not an etch stop layer. Implementations of some aspects of the present disclosure may be used in other processes, in other devices, and/or for other layers. For example, other example devices can include planar FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other devices. Some variations of the example methods and structures are described. A person having ordinary skill in the art will readily understand other modifications that may be made that are contemplated within the scope of other embodiments. Although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than what is described herein.

FIG. 1illustrates an example of simplified FinFETs40in a three-dimensional view. Other aspects not illustrated in or described with respect toFIG. 1may become apparent from the following figures and description. The structure inFIG. 1may be electrically connected or coupled in a manner to operate as, for example, one transistor or more, such as four transistors.

The FinFETs40comprise fins46aand46bon a substrate42. The substrate42includes isolation regions44, and the fins46aand46beach protrude above and from between neighboring isolation regions44. Gate dielectrics48aand48bare along sidewalls and over top surfaces of the fins46aand46b, and gate electrodes50aand50bare over the gate dielectrics48aand48b, respectively. Source/drain regions52a-fare disposed in respective regions of the fins46aand46b. Source/drain regions52aand52bare disposed in opposing regions of the fin46awith respect to the gate dielectric48aand gate electrode50a. Source/drain regions52band52care disposed in opposing regions of the fin46awith respect to the gate dielectric48band gate electrode50b. Source/drain regions52dand52eare disposed in opposing regions of the fin46bwith respect to the gate dielectric48aand gate electrode50a. Source/drain regions52eand52fare disposed in opposing regions of the fin46bwith respect to the gate dielectric48band gate electrode50b.

In some examples, four transistors may be implemented by: (1) source/drain regions52aand52b, gate dielectric48a, and gate electrode50a; (2) source/drain regions52band52c, gate dielectric48b, and gate electrode50b; (3) source/drain regions52dand52e, gate dielectric48a, and gate electrode50a; and (4) source/drain regions52eand52f, gate dielectric48b, and gate electrode50b. As indicated, some source/drain regions may be shared between various transistors, and other source/drain regions that are not illustrated as being shared may be shared with neighboring transistors that are not illustrated, for example. In some examples, various ones of the source/drain regions may be connected or coupled together such that FinFETs are implemented as two functional transistors. For example, if neighboring (e.g., as opposed to opposing) source/drain regions52a-fare electrically connected, such as through coalescing the regions by epitaxial growth (e.g., source/drain regions52aand52dbeing coalesced, source/drain regions52band52ebeing coalesced, etc.), two functional transistors may be implemented. Other configurations in other examples may implement other numbers of functional transistors.

FIG. 1further illustrates reference cross-sections that are used in later figures. Cross-section A-A is in a plane along, e.g., channels in the fin46abetween opposing source/drain regions52a-f. Cross-section B-B is in a plane perpendicular to cross-section A-A and is across source/drain region52ain fin46aand across source/drain region52din fin46b. Subsequent figures refer to these reference cross-sections for clarity. The following figures ending with an “A” designation illustrate cross-sectional views at various instances of processing corresponding to cross-section A-A, and the following figures ending with a “B” designation illustrate cross-sectional views at various instances of processing corresponding to cross-section B-B. In some figures, some reference numbers of components or features illustrated therein may be omitted to avoid obscuring other components or features; this is for ease of depicting the figures.

FIGS. 2A-Bthrough12A-B are cross-sectional views of respective intermediate structures at intermediate stages in an example process of forming a semiconductor device in accordance with some embodiments. Aspects ofFIGS. 2A-Bthrough10A-B are applicable to a gate-first process and to a replacement gate process as described herein.FIGS. 11A-Band12A-B illustrate further aspects of a gate-first process as described herein.

FIGS. 2A and 2Billustrate a semiconductor substrate70. The semiconductor substrate70may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Generally, an SOI substrate comprises a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the semiconductor substrate may include an elemental semiconductor including silicon (Si) or germanium (Ge); a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, or GaInAsP; or a combination thereof.

FIGS. 3A and 3Billustrate the formation of fins74in the semiconductor substrate70. In some examples, a mask72(e.g., a hard mask) is used in forming the fins74. For example, one or more mask layers are deposited over the semiconductor substrate70, and the one or more mask layers are then patterned into the mask72. In some examples, the one or more mask layers may include or be silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another deposition technique. The one or more mask layers may be patterned using photolithography. For example, a photo resist can be formed on the one or more mask layers, such as by using spin-on coating, and patterned by exposing the photo resist to light using an appropriate photomask. Exposed or unexposed portions of the photo resist may then be removed depending on whether a positive or negative resist is used. The pattern of the photo resist may then be transferred to the one or more mask layers, such as by using a suitable etch process, which forms the mask72. The etch process may include a reactive ion etch (RIE), neutral beam etch (NBE), inductive coupled plasma (ICP) etch, the like, or a combination thereof. The etching may be anisotropic. Subsequently, the photo resist is removed in an ashing or wet strip processes, for example.

Using the mask72, the semiconductor substrate70may be etched such that trenches76are formed between neighboring pairs of fins74and such that the fins74protrude from the semiconductor substrate70. The etch process may include a RIE, NBE, ICP etch, the like, or a combination thereof. The etching may be anisotropic.

FIGS. 4A and 4Billustrate the formation of isolation regions78, each in a corresponding trench76. The isolation regions78may include or be an insulating material such as an oxide (such as silicon oxide), a nitride, the like, or a combination thereof, and the insulating material may be formed by a high density plasma CVD (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the isolation regions78include silicon oxide that is formed by a FCVD process. A planarization process, such as a Chemical Mechanical Polish (CMP), may remove any excess insulating material and any remaining mask (e.g., used to etch the trenches76and form the fins74) to form top surfaces of the insulating material and top surfaces of the fins74to be coplanar. The insulating material may then be recessed to form the isolation regions78. The insulating material is recessed such that the fins74protrude from between neighboring isolation regions78, which may, at least in part, thereby delineate the fins74as active areas on the semiconductor substrate70. The insulating material may be recessed using an acceptable etch process, such as one that is selective to the material of the insulating material. For example, a chemical oxide removal using a CERTAS® etch or an Applied Materials SICONI tool or dilute hydrofluoric (dHF) acid may be used. Further, top surfaces of the isolation regions78may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof, which may result from an etch process.

A person having ordinary skill in the art will readily understand that the processes described with respect toFIGS. 2A-Bthrough4A-B are just examples of how fins74may be formed. In other embodiments, a dielectric layer can be formed over a top surface of the semiconductor substrate70; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. In still other embodiments, heteroepitaxial structures can be used for the fins. For example, the fins74can be recessed (e.g., after planarizing the insulating material of the isolation regions78and before recessing the insulating material), and a material different from the fins may be epitaxially grown in their place. In an even further embodiment, a dielectric layer can be formed over a top surface of the semiconductor substrate70; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the semiconductor substrate70; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form fins. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the grown materials may be in situ doped during growth, which may obviate prior implanting of the fins although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material for an n-type device different from the material for a p-type device.

FIGS. 5A and 5Billustrate the formation of gate stacks on the fins74. The gate stacks are over and extend laterally perpendicularly to the fins74. Each gate stack comprises a dielectric layer80, a gate layer82, and a mask84. The gate stacks can be operational gate stacks in a gate-first process or can be dummy gate stacks in a replacement gate process.

In a gate-first process, the dielectric layer80may be a gate dielectric, and the gate layer82may be a gate electrode. The gate dielectrics, gate electrodes, and mask84for the gate stacks may be formed by sequentially forming respective layers, and then patterning those layers into the gate stacks. For example, a layer for the gate dielectrics may include or be silicon oxide, silicon nitride, a high-k dielectric material, the like, or multilayers thereof. A high-k dielectric material can have a k value greater than about 7.0, and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, multilayers thereof, or a combination thereof. The layer for the gate dielectrics may be thermally and/or chemically grown on the fins74, or conformally deposited, such as by plasma-enhanced CVD (PECVD), ALD, molecular-beam deposition (MBD), or another deposition technique. A layer for the gate electrodes may include or be silicon (e.g., polysilicon, which may be doped or undoped), a metal-containing material (such as titanium, tungsten, aluminum, ruthenium, or the like), or a combination thereof (such as a silicide or multiple layers thereof). The layer for the gate electrodes may be deposited by CVD, PVD, or another deposition technique. A layer for the mask84may include or be silicon nitride, silicon oxynitride, silicon carbon nitride, the like, or a combination thereof, deposited by CVD, PVD, ALD, or another deposition technique. The layers for the mask84, gate electrodes, and gate dielectrics may then be patterned, for example, using photolithography and one or more etch processes, like described above, to form the mask84, gate layers82, and dielectric layers80for each gate stack.

In a replacement gate process, the dielectric layer80may be an interfacial dielectric, and the gate layer82may be a dummy gate. The interfacial dielectric, dummy gate, and mask84for the gate stacks may be formed by sequentially forming respective layers, and then patterning those layers into the gate stacks. For example, a layer for the interfacial dielectrics may include or be silicon oxide, silicon nitride, the like, or multilayers thereof, and may be thermally and/or chemically grown on the fins74, or conformally deposited, such as by PECVD, ALD, or another deposition technique. A layer for the dummy gates may include or be silicon (e.g., polysilicon) or another material deposited by CVD, PVD, or another deposition technique. A layer for the mask84may include or be silicon nitride, silicon oxynitride, silicon carbon nitride, the like, or a combination thereof, deposited by CVD, PVD, ALD, or another deposition technique. The layers for the mask84, dummy gates, and interfacial dielectrics may then be patterned, for example, using photolithography and one or more etch processes, like described above, to form the mask84, gate layer82, and dielectric layers80for each gate stack.

In some embodiments, after forming the gate stacks, lightly doped drain (LDD) regions (not specifically illustrated) may be formed in the active areas. For example, dopants may be implanted into the active areas using the gate stacks as masks. Example dopants can include or be, for example, boron for a p-type device and phosphorus or arsenic for an n-type device, although other dopants may be used. The LDD regions may have a dopant concentration in a range from about 1015cm−3to about 1017cm−3.

FIGS. 6A and 6Billustrate the formation of gate spacers86. Gate spacers86are formed along sidewalls of the gate stacks (e.g., sidewalls of the dielectric layer80, gate layer82, and mask84) and over the fins74. Residual gate spacers86may also be formed along sidewalls of the fins74, for example, depending on the height of the fins74above the isolation regions78. The gate spacers86may be formed by conformally depositing one or more layers for the gate spacers86and anisotropically etching the one or more layers, for example. The one or more layers for the gate spacers86may include or be silicon carbon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, the like, multi-layers thereof, or a combination thereof, and may be deposited by CVD, ALD, or another deposition technique. The etch process can include a RIE, NBE, or another etch process.

FIGS. 7A and 7Billustrate the formation of recesses90for source/drain regions. As illustrated, the recesses90are formed in the fins74on opposing sides of the gate stacks. The recessing can be by an etch process. The etch process can be isotropic or anisotropic, or further, may be selective with respect to one or more crystalline planes of the semiconductor substrate70. Hence, the recesses90can have various cross-sectional profiles based on the etch process implemented. The etch process may be a dry etch, such as a RIE, NBE, or the like, or a wet etch, such as using tetramethyalammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or another etchant.

FIGS. 8A and 8Billustrate the formation of epitaxy source/drain regions92in the recesses90. The epitaxy source/drain regions92may include or be silicon germanium (SixGe1-x, where x can be between approximately 0 and 100), silicon carbide, silicon phosphorus, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, materials for forming a III-V compound semiconductor include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. The epitaxy source/drain regions92may be formed in the recesses90by epitaxially growing a material in the recesses90, such as by metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. As illustrated inFIGS. 8A and 8B, due to blocking by the isolation regions78, epitaxy source/drain regions92are first grown vertically in recesses90, during which time the epitaxy source/drain regions92do not grow horizontally. After the recesses90are fully filled, the epitaxy source/drain regions92may grow both vertically and horizontally to form facets, which may correspond to crystalline planes of the semiconductor substrate70. In some examples, different materials are used for epitaxy source/drain regions for p-type devices and n-type devices. Appropriate masking during the recessing or epitaxial growth may permit different materials to be used in different devices.

A person having ordinary skill in the art will also readily understand that the recessing and epitaxial growth ofFIGS. 7A-Band8A-B may be omitted, and that source/drain regions may be formed by implanting dopants into the fins74using the gate stacks and gate spacers86as masks. In some examples where epitaxy source/drain regions92are implemented, the epitaxy source/drain regions92may also be doped, such as by in-situ doping during epitaxial growth and/or by implanting dopants into the epitaxy source/drain regions92after epitaxial growth. Example dopants can include or be, for example, boron for a p-type device and phosphorus or arsenic for an n-type device, although other dopants may be used. The epitaxy source/drain regions92(or other source/drain region) may have a dopant concentration in a range from about 1019cm−3to about 1021cm−3. Hence, a source/drain region may be delineated by doping (e.g., by implantation and/or in situ during epitaxial growth, if appropriate) and/or by epitaxial growth, if appropriate, which may further delineate the active area in which the source/drain region is delineated.

FIGS. 9A and 9Billustrate the formation of a differential contact etch stop layer (CESL)96. Generally, an etch stop layer can provide a mechanism to stop an etch process when forming, e.g., contacts or vias. An etch stop layer may be formed of a dielectric material having a different etch selectivity from adjacent layers or components. The differential CESL96is formed on surfaces of the epitaxy source/drain regions92, sidewalls and top surfaces of the gate spacers86, top surfaces of the mask84, and top surfaces of the isolation regions78. The differential CESL96has horizontal portions96hand vertical portions96v. The horizontal portions96hare formed on supporting surfaces that have respective horizontal components. The supporting surfaces with a horizontal component can be activated by a directional plasma activation during the formation of the differential CESL96, as described in further detail below. The vertical portions96vare formed on supporting surfaces that do not have a significant horizontal component (e.g., such that those surfaces are not activated by the directional plasma activation). The horizontal portions96hhave a thickness (e.g., in a direction perpendicular to respective supporting surfaces) that is greater than a thickness of the vertical portions96v(e.g., in a direction perpendicular to respective supporting surfaces). The differential CESL96may comprise or be silicon nitride, silicon carbon nitride, carbon nitride, the like, or a combination thereof. The differential CESL96may be deposited by a deposition process including a directional plasma activation, such as a Plasma Enhanced ALD (PEALD), CVD, or another deposition technique. Additional details of example deposition processes and a differential CESL96are described below, such as with respect toFIGS. 17 through 23.

FIGS. 10A and 10Billustrate the formation of a first interlayer dielectric (ILD)100over the differential CESL96. The first ILD100may comprise or be silicon dioxide, a low-k dielectric material (e.g., a material having a dielectric constant lower than silicon dioxide), such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, a compound thereof, a composite thereof, the like, or a combination thereof. The interlayer dielectric may be deposited by spin-on, CVD, FCVD, PECVD, PVD, or another deposition technique.

The first ILD100may be planarized after being deposited, such as by a CMP. In a gate-first process, a top surface of the first ILD100may be above the upper portions of the differential CESL96and the gate stacks. Hence, the upper portions of the differential CESL96may remain over the gate stacks.

FIGS. 11A and 11Billustrate the formation of openings102through the first ILD100and the differential CESL96to the epitaxy source/drain regions92to expose at least portions of the epitaxy source/drain regions92, as an example. The first ILD100and the differential CESL96may be patterned with the openings102, for example, using photolithography and one or more etch processes.

FIGS. 12A and 12Billustrate the formation of conductive features104in the openings102to the epitaxy source/drain regions92. The conductive features104may include an adhesion and/or barrier layer and conductive material on the adhesion and/or barrier layer, for example. In some examples, the conductive features104may include silicide regions106on the epitaxy source/drain regions92, as illustrated. The adhesion and/or barrier layer can be conformally deposited in the openings102and over the first ILD100. The adhesion and/or barrier layer may be or comprise titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, the like, or a combination thereof, and may be deposited by ALD, CVD, or another deposition technique. Silicide regions106may be formed on upper portions of the epitaxy source/drain regions92by reacting upper portions of the epitaxy source/drain regions92with the adhesion and/or barrier layer. An anneal can be performed to facilitate the reaction of the epitaxy source/drain regions92with the adhesion and/or barrier layer.

The conductive material can be deposited on the adhesion and/or barrier layer and fill the openings102. The conductive material may be or comprise tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by CVD, ALD, PVD, or another deposition technique. After the material of the conductive features104is deposited, excess material may be removed by using a planarization process, such as a CMP, for example. The planarization process may remove excess material of the conductive features104from above a top surface of the first ILD100. Hence, top surfaces of the conductive features104and the first ILD100may be coplanar. The conductive features104may be or may be referred to as contacts, plugs, etc.

FIGS. 13A-Bthrough16A-B are cross-sectional views of respective intermediate structures at intermediate stages in another example process of forming a semiconductor device in accordance with some embodiments.FIGS. 13A-Band16A-B illustrate further aspects of a replacement gate process as described herein. Processing is first performed as described above with respectFIGS. 2A-Bthrough10A-B.

FIGS. 13A and 13Billustrate the replacement of gate stacks with replacement gate structures. The first ILD100and differential CESL96are formed with top surfaces coplanar with top surfaces of the gate layers82. A planarization process, such as a CMP, may be performed to level the top surface of the first ILD100and differential CESL96with the top surfaces of the gate layers82. The CMP may also remove the mask84(and, in some instances, upper portions of the gate spacers86) on the gate layers82. Accordingly, top surfaces of the gate layers82are exposed through the first ILD100and the differential CESL96.

With the gate layers82exposed through the first ILD100and the differential CESL96, the gate layers82and the dielectric layers80are removed, such as by one or more etch processes. The gate layers82may be removed by an etch process selective to the gate layers82, wherein the dielectric layers80act as etch stop layers, and subsequently, the dielectric layers80can be removed by a different etch process selective to the dielectric layers80. The etch processes can be, for example, a RIE, NBE, a wet etch, or another etch process. Recesses are formed between gate spacers86where the gate stacks are removed, and channel regions of the fins74are exposed through the recesses.

The replacement gate structures are formed in the recesses formed where the gate stacks were removed. The replacement gate structures each include one or more conformal layers120and a gate electrode122. The one or more conformal layers120include a gate dielectric layer and may include one or more work-function tuning layers. The gate dielectric layer can be conformally deposited in the recesses where gate stacks were removed (e.g., on top surfaces of the isolation regions78, sidewalls and top surfaces of the fins74along the channel regions, and sidewalls of the gate spacers86) and on the top surfaces of the first ILD100, the differential CESL96, and gate spacers86. The gate dielectric layer can be or include silicon oxide, silicon nitride, a high-k dielectric material, multilayers thereof, or other dielectric material. A high-k dielectric material may have a k value greater than about 7.0, and may include a metal oxide of or a metal silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof. The gate dielectric layer can be deposited by ALD, PECVD, MBD, or another deposition technique.

Then, if implemented, a work-function tuning layer may be conformally deposited on the gate dielectric layer. The work-function tuning layer may include or be tantalum, tantalum nitride, titanium, titanium nitride, the like, or a combination thereof, and may be deposited by ALD, PECVD, MBD, or another deposition technique. Any additional work-function tuning layers may be sequentially deposited similar to the first work-function tuning layer.

A layer for the gate electrodes122is formed over the one or more conformal layers120. The layer for the gate electrodes122can fill remaining recesses where the gate stacks were removed. The layer for the gate electrodes122may be or comprise a metal-containing material such as Co, Ru, Al, W, Cu. multi-layers thereof, or a combination thereof. The layer for the gate electrodes122can be deposited by ALD, PECVD, MBD, PVD, or another deposition technique.

Portions of the layer for the gate electrodes122and of the one or more conformal layers120above the top surfaces of the first ILD100, the differential CESL96, and gate spacers86are removed. For example, a planarization process, like a CMP, may remove the portions of the layer for the gate electrodes122and the one or more conformal layers120above the top surfaces of the first ILD100, the differential CESL96, and gate spacers86. The replacement gate structures comprising the gate electrodes122and one or more conformal layers120may therefore be formed as illustrated inFIG. 13A.

FIGS. 14A and 14Billustrate the formation of a second ILD130over the first ILD100, replacement gate structures, gate spacers86, and differential CESL96. Although not illustrated, in some examples, an etch stop layer (ESL) may be deposited over the first ILD100, etc., and the second ILD130may be deposited over the ESL. If implemented, the etch stop layer may comprise or be silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, the like, or a combination thereof, and may be deposited by CVD, PECVD, ALD, or another deposition technique. The second ILD130may comprise or be silicon dioxide, a low-k dielectric material, such as silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, a compound thereof, a composite thereof, the like, or a combination thereof. The second ILD130may be deposited by spin-on, CVD, FCVD, PECVD, PVD, or another deposition technique.

FIGS. 15A and 15Billustrate the formation of openings132through the second ILD130, the first ILD100, and the differential CESL96to the epitaxy source/drain regions92to expose at least portions of the epitaxy source/drain regions92, as an example. The second ILD130, the first ILD100, and the differential CESL96may be patterned with the openings132, for example, using photolithography and one or more etch processes.

FIGS. 16A and 16Billustrate the formation of conductive features134in the openings132to the epitaxy source/drain regions92. The conductive features134may include an adhesion and/or barrier layer and conductive material on the adhesion and/or barrier layer, for example. In some examples, the conductive features134may include silicide regions136on the epitaxy source/drain regions92, as illustrated. The adhesion and/or barrier layer can be conformally deposited in the openings132and over the second ILD130. The adhesion and/or barrier layer may be or comprise titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, the like, or a combination thereof, and may be deposited by ALD, CVD, or another deposition technique. Silicide regions136may be formed on upper portions of the epitaxy source/drain regions92by reacting upper portions of the epitaxy source/drain regions92with the adhesion and/or barrier layer. An anneal can be performed to facilitate the reaction of the epitaxy source/drain regions92with the adhesion and/or barrier layer.

The conductive material can be deposited on the adhesion and/or barrier layer and fill the openings132. The conductive material may be or comprise tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by CVD, ALD, PVD, or another deposition technique. After the material of the conductive features134is deposited, excess material may be removed by using a planarization process, such as a CMP, for example. The planarization process may remove excess material of the conductive features134from above a top surface of the second ILD130. Hence, top surfaces of the conductive features134and the second ILD130may be coplanar. The conductive features134may be or may be referred to as contacts, plugs, etc.

FIGS. 17 through 20are cross-sectional views of respective intermediate structures at intermediate stages in an example Plasma Enhanced ALD (PEALD) process of forming a differential CESL in a semiconductor device in accordance with some embodiments.FIG. 21is a flow chart of the example PEALD process ofFIGS. 17 through 20in accordance with some embodiments. Although described in the context of a differential CESL, the example PEALD process can be used to form any layer, such as a layer that is not an ESL.

FIG. 17illustrates a portion of the intermediate structure formed through the processing described above with respect toFIGS. 2A-Bthrough8A-B. The intermediate structure includes a semiconductor substrate with a fin74, an epitaxy source/drain region92in the fin74and laterally between gate spacers86, and gate stacks that include a mask84along the gate spacers86.

FIG. 18illustrates a monolayer formed on the intermediate structure by exposure to a first precursor in the PEALD process, such as in operation202ofFIG. 21. The intermediate structure ofFIG. 17is exposed to a first precursor, such as dichlorosilane SiH2Cl2(DCS) or another precursor depending on the material to be deposited, for example. In the illustrated example, a DCS precursor is used and forms a monolayer of SiH3along exterior surfaces of the intermediate structure exposed to the DCS precursor. The exterior surfaces include top surfaces of the mask84, sidewall and top surfaces of gate spacers86, upper surfaces of the epitaxy source/drain regions92, and top surfaces of isolation regions78(see, e.g.,FIGS. 8B and 9B). In other examples, a different precursor may be used, which may form a monolayer of a different material. Following exposure to the first precursor, the first precursor may be purged from the tool chamber used to expose the intermediate structure to the first precursor.

FIG. 19illustrates a directional plasma activation200performed on the monolayer, such as in operation204ofFIG. 21. The directional, or anisotropic, plasma activation activates portions of the monolayer for increased reactions with a subsequent precursor. Portions of the monolayer on respective upper surfaces of the intermediate structure that have horizontal components are activated by the directional plasma activation200, whereas portions of the monolayer on respective surfaces that do not have a horizontal component may not be activated by the directional plasma activation200. Activation of surfaces may increase based on an increased horizontal component of the surface. For example, surfaces with no or little horizontal component can have no or little activation, whereas surfaces with a greater horizontal component can have a greater activation.

In the illustrated example, the upper surfaces of the epitaxy source/drain regions92are faceted such that the respective upper surfaces of the epitaxy source/drain regions92have a horizontal component and a vertical component, as illustrated inFIG. 8B, for example. The monolayer on these upper surfaces of the epitaxy source/drain regions92are activated by the directional plasma activation200. The sidewalls of the gate spacers86, as illustrated, are vertical without a significant horizontal component, and hence, are not activated by the directional plasma activation200.

As illustrated inFIG. 19, an argon (Ar) directional plasma activates portions of the monolayer on upper surfaces of the intermediate structure that have a horizontal component to modify the SiH3in those portions to activated SiH2*. In some examples, the plasma process implemented to activate the monolayer can be a microwave remote plasma, although other plasma sources, such as a direct plasma, may be implemented. A flow rate of the argon (Ar) gas for the plasma can be in a range from about 1,000 sccm to about 9,000 sccm. A pressure of the plasma process can be in a range from about 0.5 Torr to about 50 Torr. A temperature of the plasma process can be in a range from about 200° C. to about 650° C. A power of the plasma generator of the plasma process can be in a range from about 50 W to about 4,000 W. A frequency of the plasma generator can be in a range from about 13.56 MHz to about 2.45 GHz. A substrate holder of the plasma process can be unbiased. A duration of the exposure of the intermediate structure to the plasma process can be in a range from 0.1 second to 120 seconds. In other examples, a different plasma, such as a different plasma process, conditions, and/or gas (such as an inert gas, nitrogen gas, or the like), may be used to activate portions of the monolayer. By activating the portions of the monolayer with the directional plasma activation200, more reaction sites may be created on the activated portions of the monolayer to react with a subsequent precursor in the PEALD process. The directional plasma activation200may be performed in situ in the same tool chamber used to expose the intermediate structure to the first precursor and, subsequently, a second precursor.

FIG. 20illustrates a layer formed on the intermediate structure by exposure to a second precursor in the PEALD process, such as in operation206ofFIG. 21. The intermediate structure ofFIG. 19is exposed to a second precursor, such as an ammonia (NH3) plasma or another precursor depending on the material to be deposited, for example. The second precursor reacts with activated portions of the monolayer more than portions of the monolayer that are not activated. For example, due to the increased reaction sites formed on the activated portions of the monolayer from the directional plasma activation200, more reactions between the monolayer at the activated portions and the second precursor will occur than between the monolayer at the non-activated portions and the second precursor. This causes the differential CESL96to be deposited at a greater rate on upper surfaces having a horizontal component, where activation occurs, than on vertical surfaces that do not have a significant horizontal component, where activation generally does not occur.

In the illustrated example ofFIG. 20, an ammonia (NH3) plasma precursor is used and reacts with most, or in some instances, all, of the activated SiH2* and some of the non-activated SiH3(e.g., less than the activated SiH2*) to form silicon nitride (e.g., SiNH2). For example, an ammonia (NH3) precursor gas can be flowed in the plasma process at a flow rate in a range from about 50 sccm to about 1,000 sccm. Hence, in the illustrated example, more SiNH2is deposited on upper surfaces having a horizontal component than on vertical surfaces that do not have a significant horizontal component. In other examples, a different precursor may be used, which may form a layer of a different material. Following exposure to the second precursor, the second precursor may be purged from the tool chamber used to expose the intermediate structure to the second precursor.

FIGS. 18 through 20, and operations202,204, and206ofFIG. 21, illustrate a cycle of the PEALD process. The processing described with respect toFIGS. 18 through 20, and operations202,204, and206ofFIG. 21, may be repeated any number of times, e.g., any number of cycles of the PEALD process may be implemented, such as illustrated by the looping in the flow ofFIG. 21, to achieve a differential CESL96having desired thicknesses.

In other examples, a CVD process with in situ plasma activation may be used for forming a differential CESL in a semiconductor device in accordance with some embodiments.FIG. 22is a flow chart of the example CVD process with in situ plasma activation in accordance with some embodiments. Although described in the context of a differential CESL, the example CVD process can be used to form any layer, such as a layer that is not an ESL.

For example, the intermediate structure ofFIG. 17may be transferred into a chamber of a CVD tool, and one or more precursors (e.g., a mixture including at least two precursors) are provided in the chamber of the CVD tool, as in operation222ofFIG. 22. By exposing the structure to the one or more precursors in the chamber, a layer may begin being deposited. The structure may be exposed to the one or more precursors for some duration less than a duration for depositing a layer with a finished thickness. The one or more precursors may be purged from the chamber of the CVD tool.

After purging the one or more precursors, a directional plasma activation is performed on the intermediate structure in the chamber of the CVD tool, as in operation224ofFIG. 22. The directional, or anisotropic, plasma activation activates upper surfaces of the portion of the layer that was deposited that have a horizontal component for increased reactions with reactants of one or more precursors (e.g., two or more precursors). Respective upper surfaces of the portion of the layer that have horizontal components are activated by the directional plasma activation, whereas respective surfaces that do not have a horizontal component may not be activated by the directional plasma activation, similar to what was described with respect toFIG. 19. For example, the upper surfaces of the portion of the layer on the epitaxy source/drain regions92are activated by the directional plasma activation, whereas surfaces of the portion of the layer on the sidewalls of the gate spacers86are vertical without a significant horizontal component and are not activated by the directional plasma activation. By activating the upper surfaces that have a horizontal component with the directional plasma activation, more reaction sites may be created on the activated upper surfaces to react with a reactant of one or more subsequent precursors in the CVD process.

After the directional plasma activation, one or more precursors (e.g., the mixture including at least two precursors) are provided, as in operation226ofFIG. 22, in the chamber of the CVD tool. Gas phase reactions may occur that provide reactants to surfaces on the intermediate structure. Activated upper surfaces provide more reaction sites for adsorption of and reaction with the reactants than non-activated surfaces. This causes the differential CESL96to be deposited at a greater rate on upper surfaces having a horizontal component, where activation occurs, than on vertical surfaces that do not have a significant horizontal component, where activation generally does not occur.

In some examples, periodically, the one or more precursors may be purged from the chamber of the CVD tool, and a directional plasma activation may be performed in situ in the chamber of the CVD tool. Thereafter, the one or more precursors can be provided in the chamber of the CVD tool. By repeating the directional plasma activation in this manner, such as illustrated by the looping in the flow ofFIG. 22, deposition rates on horizontal surfaces and on vertical surfaces may remain more proportional. The processing of performing a directional plasma activation, providing one or more precursors, and purging the one or more precursors may be repeated any number of times.

FIG. 23illustrates aspects of the differential CESL96formed using the PEALD process ofFIGS. 18 through 20, the CVD process with in situ directional plasma activation, or another differential deposition process. The differential CESL96includes horizontal portions96hon underlying upper surfaces having a horizontal component and includes vertical portions96von supporting vertical surfaces that do not have a significant horizontal component. The horizontal portions96hhave a thickness Th in a direction perpendicular to the supporting surface on which the respective horizontal portion is formed. The vertical portions96vhave a thickness Tv in a direction perpendicular to the supporting surface on which the respective horizontal portion is formed. The thickness Th of the horizontal portions96his greater than the thickness Tv of the vertical portions96v. In some examples, the thickness Th of the horizontal portions96his at least 2 nm more than the thickness Tv of the vertical portions96v. For example, the thickness Th of the horizontal portions96hcan be 4 nm, and the thickness Tv of the vertical portions96vcan be 2 nm. In some examples, a ratio of the thickness Th of the horizontal portions96hto and the thickness Tv of the vertical portions96vcan be equal to or greater than 2.

A first dimension D1is illustrated between facing sidewall surfaces of gate spacers86on which respective vertical portions96vof the differential CESL96are formed. A second dimension D2is illustrated between facing surfaces of vertical portions96vof the differential CESL96. Generally, the first dimension D1is equal to the second dimension D2plus two times the thickness Tv of the vertical portions96v.

Some embodiments may achieve advantages. In some implementations, the process window for forming a conductive feature (e.g., conductive feature104or134inFIGS. 12A and 16A) may be increased because the second dimension D2may be increased by reducing the thickness Tv of the vertical portions96vwhen compared to a CESL with a uniform thickness throughout. In other implementations, for a given process window in which to form a conductive feature (which may determine a minimum second dimension D2), the differential CESL96may permit for an increased thickness Th of horizontal portions96h, an increased width of the gate spacers86(e.g., in the direction of the second dimension D2), and/or an increased gate stack width when compared to a CESL with a uniform thickness throughout. If a width of the gate spacers86is relatively small, for example, the thickness Tv of the vertical portions96vmay be relatively large, which may permit the thickness Th of the horizontal portions96hto be proportionally larger. This can permit for greater protection of the epitaxy source/drain regions92and/or etch stop capability during an etch process that forms openings (e.g., openings102or132inFIGS. 11A-Band15A-B) for conductive features, for example. This can also permit for greater protection of the epitaxy source/drain regions92from oxidation. If the thickness Tv of the vertical portions96vis relatively small, for example, a width of the gate spacers86may be relatively large, which may permit more spacer material, such as a low-k material, for the gate spacers86to improve device performance by decreasing resistance-capacitance (RC) delay. If the width of the gate spacers86and thickness Th of horizontal portions96hremain the same compared to corresponding structures in a uniform CESL process, the thickness Tv of the vertical portions96vmay be reduced, which can permit an increased width of the gate stacks (e.g., parallel to a channel length direction between corresponding epitaxy source/drain regions92). Various permutations and combinations of dimensions and thicknesses may be achieved to permit various advantages to be achieved.

An embodiment is a structure. The structure includes an active area on a substrate, a gate structure over the active area, a gate spacer along a sidewall of the gate structure, and a differential etch stop layer. The active area includes a source/drain region, and the source/drain region is proximate the gate structure. The differential etch stop layer has a first portion along a sidewall of the gate spacer and has a second portion over an upper surface of the source/drain region. A first thickness of the first portion is in a direction perpendicular to the sidewall of the gate spacer, and a second thickness of the second portion is in a direction perpendicular to the upper surface of the source/drain region. The second thickness is greater than the first thickness.

Another embodiment is a method of semiconductor processing. A differential layer is formed over a device structure on a substrate. In a first exposure, the device structure is exposed to first one or more precursors. After the first exposure, an upper surface on the device structure is activated using a directional plasma activation. After activating the upper surface on the device structure, in a second exposure, the device structure is exposed to second one or more precursors. More reactions occur at the activated upper surface on the device structure than at a non-activated surface on the device structure while the device structure is exposed to the second one or more precursors.

A further embodiment is a method of semiconductor processing. A differential etch stop layer is formed having a first portion over an upper surface of a source/drain region and a second portion along a sidewall of a gate spacer. The source/drain region is in an active area, and the gate spacer is over the active area proximate the source/drain region. A thickness of the first portion is greater than a thickness of the second portion. Forming the differential etch stop layer includes performing a directional activation. An interlayer dielectric (ILD) is deposited over the differential etch stop layer. A conductive feature is formed through the ILD and the differential etch stop layer and contacting the source/drain region.