PERFORMING PRECONDITIONED OPERATION BASED ON QUEUE IDENTIFIER

Various embodiments provide for performing a preconditioned operation on a memory system (e.g., the memory sub-system) based on queue identifiers of command requests received from a host system, where the precondition can include detection of command requests to be performed (e.g., executed) with respect to a sequence of memory addresses.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory devices and, more specifically, to performing a preconditioned operation on a memory system (e.g., the memory sub-system) based on queue identifiers of command requests received from a host system.

BACKGROUND

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to performing a preconditioned operation on a memory system (e.g., the memory sub-system) based on queue identifiers of command requests received from a host system, where the precondition can include detection of command requests to be performed (e.g., executed) with respect to a sequence of memory addresses. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction withFIG.1. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can send access requests to the memory sub-system, such as to store data at the memory sub-system and to read data from the memory sub-system.

The host system can send access requests (e.g., write commands, read commands) to the memory sub-system, such as to store data on a memory device at the memory sub-system, read data from the memory device on the memory sub-system, or write/read constructs (e.g., such as submission and completion queues) with respect to a memory device on the memory sub-system. The data to be read or written, as specified by a host request (e.g., data access request or command request), is hereinafter referred to as “host data.” A host request can include logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location the host system associates with the host data. The logical address information (e.g., LBA, namespace) can be part of metadata for the host data.  Metadata can also include error handling data (e.g., error-correcting code (ECC) codeword, parity code), data version (e.g., used to distinguish age of data written), valid bitmap (which LBAs or logical transfer units contain valid data), and so forth.

The memory sub-system can initiate media management operations, such as a write operation, on host data that is stored on a memory device. For example, firmware of the memory sub-system can re-write previously written host data from a location of a memory device to a new location as part of garbage collection management operations. The data that is re-written, for example as initiated by the firmware, is hereinafter referred to as “garbage collection data.”

“User data” hereinafter generally refers to host data and garbage collection data. “System data” hereinafter refers to data that is created and/or maintained by the memory sub-system for performing operations in response to host requests and for media management. Examples of system data include, and are not limited to, system tables (e.g., logical-to-physical memory address mapping table (also referred to herein as a L2P table), data from logging, scratch pad data, and so forth).

A memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more die. Each die can be comprised of one or more planes. For some types of non-volatile memory devices (e.g., NOT-AND (NAND)-type devices), each plane is comprised of a set of physical blocks. For some memory devices, blocks are the smallest area that can be erased. Each block is comprised of a set of pages. Each page is comprised of a set of memory cells, which store bits of data. The memory devices can be raw memory devices (e.g., NAND), which are managed externally, for example, by an external controller. The memory devices can be managed memory devices (e.g., managed NAND), which are raw memory devices combined with a local embedded controller for memory management within the same memory device package.

Certain memory devices, such as NAND-type memory devices, comprise one or more blocks, (e.g., multiple blocks), with each of those blocks comprising multiple memory cells. For instance, a memory device can comprise multiple pages (also referred as wordlines), with each page comprising a subset of memory cells of the memory device. Generally, writing data to such memory devices involves  programming (by way of a program operation) the memory devices at the page level of a block, and erasing data from such memory devices involves erasing the memory devices at the block level (e.g., page level erasure of data is not possible).

A memory device can comprise one or more cache blocks and one or more non-cache blocks, where data written to the memory device is first written to one or more cache blocks, which can facilitate faster write performance; and data stored on the cache blocks can eventually be moved (e.g., copied) to one or more non-cache blocks at another time (e.g., a time when the memory device is idle), which can facilitate higher storage capacity on the memory device. A cache block can comprise a single-level cell (SLC) block that comprises multiple SLCs, and a non-cache block can comprise a multiple-layer cell (MLC) block that comprises multiple MLCs, a triple-level cell (TLC) block that comprises multiple TLCs, or a quad-level cell (QLC) block that comprises QLCs. Writing first to one or more SLCs blocks can be referred to as SLC write caching or SLC caching (also referred to as buffering in SLC mode). Generally, when using traditional full SLC caching, an SLC block is released of data after data is moved from the SLC block to a non-cache block (e.g., QLC block) and the non-cache block is verified to be free of errors.

A compaction (or a garbage collection) operation can be performed with respect to a cache block (containing one or more memory cells) of a memory device (e.g., NAND-type memory device), where the data stored in the cache block is copied (e.g., transferred) to a non-cache block. A compaction operation can be performed with respect to a set of cache blocks when, for instance, there are no available cache blocks to cache new data (e.g., cache new written data). As used herein, a block compaction operation is performed on a cache block and can comprise reading data stored on the cache block and writing the read data to a non-cache block (e.g., programming the non-cache block with the data read from the cache block), thereby copying the data from the cache block to the non-cache block An example block compaction operation can include a SLC-QLC block compaction operation. A block compaction operation can be performed, for instance, when available cache blocks on a memory device are full or nearing a fill limit.

For conventional memory devices that comprise NOT-AND (NAND) memory cells (hereafter referred to as NAND-type memory devices), writing and erasing sequentially generally leads to lower or reduced write amplification (e.g., a low write amplification factor (WAF)) and better data performance. While modern software on host systems (e.g., software applications, databases, and file systems) tend to read and write data sequentially with respect to a memory system (e.g., a memory sub-system coupled to a host system), when such software is executed by one or more multicore hardware processors of the host system, the sequentiality of data access request (e.g., read and write requests) to the memory system is usually lost. For instance, when modern software operates on one or more multicore hardware processors of a host system, a block layer of the host system typically divides work to be performed by each process (of the software) among two or more cores of a multicore hardware processor (e.g., in a way where work is uniformly divided across cores to achieve maximum throughput). While each core of a host system's hardware processor may still issue largely sequential data access requests to a memory system, the data access requests are usually intermingled (e.g., interleaved) with each other and appear random or pseudo-random from the perspective of the memory system. This can be due to data aggregation and request priority policy in a data link layer between the host system and the memory system. For instance, a memory system having a Non-Volatile Memory Express (NVMe) architecture is typically designed to have an out-of-order traffic handshake between the host system and a controller of the memory system for data performance reasons.

The architecture of conventional memory systems, such as those implemented by a NVMe standard, include multiple queues for processing data access requests (e.g., read and write requests) from host systems. For instance, a memory system based on a NVMe standard can comprise multiple pairs of queues, where each queue pair is associated with a different queue identifier (QID), and where each queue pair comprises a submission queue for incoming requests that need to be completed/processed and a completion queue for command requests already completed/processed by the memory system. As herein, a submission queue identifier (SQID) can refer to a submission queue of a given queue pair, and can be equal to the  QID of the given queue pair. A completion queue identifier (CQID) can refer to a completion queue of a given queue pair, and can be equal to the QID of the given queue pair. A QID can be included as a parameter (e.g., QID tag) in a data access request from a host system to a memory system, and can serve as a pointer to a submission queue on the memory system that is to receive the data access request. Generally, each core of a host system's hardware processor is individually associated with (e.g., assigned to, mapped to, attached to) a different QID (e.g., different queue pair on the memory system having a unique QID), and data access requests (e.g., read and write requests) from a given core are received and stored by a submission queue that has a queue identifier associated with the given core. Additionally, a given thread executing on a host system (e.g., of a software application or a database on the host system) tends to be started/run on the same core of the host system's hardware processor (e.g., threads on the host system tend to have core affinity). A given core of a host system's hardware processor can have multiple threads (e.g., four to five threads) that operate on and have affinity to the given core.

In conventional memory systems, submission queues of a memory system can be scanned for a command request (e.g., each submission queue is scanned) and a detected command request is added to a command queue (e.g., added to an entry of the command queue) for the memory system, where the command queue stores a list of commands requests awaiting processing (e.g., execution) by the memory system. Generally, command requests are added to the command queue in the order in which command requests are retrieved from the submission queues of the memory system and, as a result, the command queue usually stores a mix of command requests associated with different queue identifiers or operating on different memory addresses. Unfortunately, this mix can make it challenging for conventional memory systems to detect when conditions are satisfied for performing certain preconditioned operations. For instance, a read-look ahead operation or a command request merging operation can be performed based on detecting multiple command requests operating on a sequence of a memory address in a command request. However, conventional memory systems can be inefficient in detecting multiple command requests operating on a sequence of a memory address in the command queue.

Aspects of the present disclosure are directed to cure these and other deficiencies of conventional memory technologies. Various embodiments provide for performing a preconditioned operation on a memory system (e.g., the memory sub-system) based on queue identifiers of command requests received from a host system, where the precondition can include detection of command requests to be performed (e.g., executed) with respect to a sequence of memory addresses. In particular, the memory system of some embodiments determines (e.g., identifies) one or more command requests in a command queue of a memory system that meet or satisfy a precondition of a preconditioned operation, and determines the one or more command requests by filtering command requests in the command queue based on at least one queue identifier associated with those command requests. Additionally, the memory system of some embodiments determines the one or more command requests by filtering command requests in the command queue based on at least one queue identifier associated with those command requests and at least one namespace identifier associated with those command requests.

By filtering based on queue identifiers, namespace identifiers, or both, a memory system of an embodiment can separate out input command streams (e.g., an input read command stream comprising multiple read command requests, or an input write command stream comprising multiple write command requests) from a host system by queue identifier, namespace identifier, or both (e.g., a given input command stream being associated with a unique combination of a queue identifier and a namespace identifier), and determine whether to perform a preconditioned operation based on a given (separate) input command stream. Overall, a memory system of an embodiment described herein can use a preconditioned operation to coalesce and process multiple command requests in the command queue (e.g., coalesce read command requests in the backend of the memory system), thereby improving performance, reducing latency (e.g., read or write latency), or both in the memory system.

As used herein, a preconditioned operation can comprise an operation that is performed based on (e.g., detection of) one or more command requests (e.g., of an input command stream) in a command queue of the memory system that satisfy one  or more preconditions for a preconditioned operation. An example precondition can include one relating to a command type (e.g., read command type or a write command type), or one relating to a memory address (e.g., a pattern of memory addresses, such as a sequence of memory addresses). An example of a preconditioned operation can include an operation that is performed based on detecting a plurality of command requests of a given command type (e.g., a read command type, or a write command type) in a command queue of a memory system that are awaiting performance (e.g., execution) on a pattern (e.g., a sequence) of memory addresses (e.g., LBAs). For instance, the preconditioned operation can be a read-ahead (or read-look-ahead) operation, a merging operation (e.g., that merges multiple command requests into a single command request), or the like.

Data access request and command request are used interchangeably herein. As used herein, a data access request/command request can comprise a data access command for a memory system. Accordingly, a write request can comprise a write command for a memory system, and a read request can comprise a read command for a memory system.

As used herein, a superblock of a memory device (e.g., of a memory system) comprises a plurality (e.g., collection or grouping) of blocks of the memory device. For example, a superblock of a NAND-type memory device can comprise a plurality of blocks that share a same position in each plane in each NAND-type memory die of the NAND-type memory device.

As used herein, a namespace on a memory system (e.g., memory sub-system) can be a logical partition on the memory system for creating separate logical storage spaces on the memory system. Different portions of data storage space of a memory system can be allocated to different namespaces, and memory addresses (e.g., LBAs) within namespaces can be configured independently from each other. Accordingly, each namespace can identify a quantity of data storage space of the memory system addressable via LBA. A same LBA address can be used in different namespaces to identify different memory units (e.g., superblocks, blocks, or pages) in different portions of data storage space on the memory system. For example, a first namespace (e.g., having a first namespace identifier) can be allocated on a first portion  of data storage space of a memory system and can have LBA addresses ranging from 0 to n-1, and a second namespace (e.g., having a second namespace identifier) can be allocated on a second portion of the data storage space and can have LBA addresses ranging from 0 to m-1. For various embodiments, each namespace created on a memory system can be associated with (and identified by) a unique namespace identifier. A host system can send a request to a memory system for the creation, deletion, or reservation of a namespace. After a portion of the data storage space is allocated to a namespace, an LBA address in the respective namespace can logically represent a particular memory unit on a memory device (e.g., data storage media) of the memory system. A particular memory unit logically represented by an LBA address in the namespace can physically correspond to different memory units (e.g., superblocks, blocks, or pages) at different time instances.

As used herein, a read-ahead operation (or process) can be performed to improve memory access latency, optimize data retrieval, or both. Typically, performing a read-ahead operation on a memory system involves a memory system fetching (or pre-fetching) data from one of its memory devices before it is explicitly requested by the host system (e.g., a hardware processor of the host system or a software application running on the host system). Specifically, a read-ahead operation (also referred to as a read look-ahead operation) can take advantage of spatial locality of stored data on a memory device and that a host system (e.g., a software application running thereon) has a tendency of accessing data from contiguous memory locations. The memory system can predict that once a specific memory location on a memory device is accessed (or a sequence of specific memory locations on the memory device are accessed) at the request (e.g., read request) of a host system, the host system will likely explicitly request access of data from one or more subsequent memory locations on the memory device in a sequential manner. Based on this prediction, the memory system can initiate a read-ahead operation to fetch (or pre-fetch) the data from the subsequent memory locations into a cache, buffer, or some other temporary data storage area. Subsequently, when the host system explicitly requests the fetched/pre-fetched data from the memory system (e.g., via an explicit read request), the memory system already has the requested data  available in the cache or buffer, resulting in faster read access times. In this way, a read-ahead operation can reduce or help reduce read access latency.

Disclosed herein are some examples of performing a preconditioned operation on a memory system (e.g., the memory sub-system) based on queue identifiers of command requests received from a host system, as described herein.

The memory devices130,140can include any combination of the different types of non-volatile memory devices and/or volatile memory devices. The volatile memory devices (e.g., memory device140) can be, but are not limited to, random access memory (RAM), such as dynamic random-access memory (DRAM) and synchronous dynamic random-access memory (SDRAM).

Some examples of non-volatile memory devices (e.g., memory device130) include a NAND type flash memory and write-in-place memory, such as a three-dimensional (3D) cross-point memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. NAND type flash memory includes, for example, two-dimensional (2D) NAND and 3D NAND.

As used herein, a block comprising SLCs can be referred to as a SLC block, a block comprising MLCs can be referred to as a MLC block, a block comprising TLCs can be referred to as a TLC block, and a block comprising QLCs can be referred to as a QLC block.

Each of the memory devices130,140include a memory die150,160. For some embodiments, each of the memory devices130,140represents a memory  device that comprises a printed circuit board, upon which its respective memory die150,160is solder mounted.

The memory sub-system controller115includes a queue identifier-based operation performer113that enables or facilitates the memory sub-system controller115to perform a preconditioned operation on the memory sub-system110as described herein. For some embodiments, the queue identifier-based operation performer113can be part of a larger queue identifier-based request processor (not shown). Alternatively, some or all of the queue identifier-based operation performer113is included by the local media controller135, thereby enabling the local media controller135to enable or facilitate performance of a preconditioned operation on the memory sub-system110as described herein.

FIG.2is a diagram illustrating an example architecture200of the host system120and the memory sub-system110ofFIG.1, in accordance with some embodiments of the present disclosure. In the example architecture200, the host system120comprises multiple hardware processor cores214, a software application210operating on the multiple hardware processor cores214, and a kernel212(e.g., of an operating system) operating on the multiple hardware processor cores214. Additionally, in the example architecture200, the memory sub-system110comprises a data stream identifier220(e.g., which is part of a queue identifier-based request processor) and multiple pairs of queues222, which include queues pairs associated with queue identifier-1 (QID-1) through queue identifier-N (QID-N). The queue pair associated with queue identifier-1 (QID-1) comprises a submission queue 1 (SQ-1) and a completion queue (CQ-1), the queue pair associated with queue identifier-2 (QID-2) comprises a submission queue-2 (SQ-2) and a completion queue (CQ-2), the queue pair associated with queue identifier-3 (QID-3) comprises a submission queue-3 (SQ-3) and a completion queue (CQ-3), the queue pair associated with queue identifier-4 (QID-4) comprises a submission queue-4 (SQ-4) and a completion queue (CQ-4), and so on. During operation, the software application210can cause execution of processes (having process identifiers (PROCESS_IDs)) by the kernel212, where one or more of the processes can involve generation of sequential data access requests. The kernel212can execute at least one of the processes by dividing  the process into multiple threads (each having a thread identifier (THREAD_ID)) to be executed by the multiple hardware processor cores214. Each of the threads can be assigned for execution by one of the multiple hardware processor cores214(e.g., according to core affinity), and execution of a thread by a given hardware processor core can cause the given hardware processor core to generate and issue one or more data access requests to the memory sub-system110, where each generated/issued data access request includes a queue identifier (QID) of the given hardware processor core.

As data access requests are generated and issued by the multiple hardware processor cores214, the data access requests from each hardware processor core can be interleaved with those generated and issued by one or more other hardware processor cores. Accordingly, the data access request received by the memory sub-system110can appear random or pseudo-random to the memory sub-system110.

Upon receiving a given data access request, the memory sub-system110can use the data stream identifier220to determine a given queue identifier of the given data access request, and the memory sub-system110can cause the given data access request to be stored in a submission queue (e.g., stored to an entry added to the submission queue) of the queue pair (of the multiple pairs of queues222) that corresponds to (e.g., matches) the given queue identifier. When the given data access request has been processed (e.g., executed) by the memory sub-system110, the results of the given data access request can be stored (e.g., queued) to a completion queue (e.g., stored to an entry added to the completion queue) of the queue pair (of the multiple pairs of queues222) that corresponds to (e.g., matches) the given queue identifier, from which the host system120can obtain (e.g., collect) the results.

FIG.3is a flow diagram of an example method300for performing a preconditioned operation on a memory system based on queue identifiers of command requests received from a host system, in accordance with some embodiments of the present disclosure. The method300can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method300is performed by the memory sub-system  controller115ofFIG.1based on the queue identifier-based operation performer113. Additionally, or alternatively, for some embodiments, the method300is performed, at least in part, by the local media controller135of the memory device130ofFIG.1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are used in every embodiment. Other process flows are possible.

Referring now to the method300ofFIG.3, at operation302, a processing device (e.g., the processor117of the memory sub-system controller115) receives a set of command requests from a host system (e.g.,120), where each individual command request in the set of command requests is stored to an individual submission queue of a memory system (e.g., the memory sub-system110) associated with (e.g., that corresponds to) an individual queue identifier of the individual command request. For some embodiments, a command request received from the host system comprises a queue identifier (e.g., includes a QID tag) associated with the command request (e.g., based on the host-side submission queue from which the command request was sent).

Subsequently, at operation304, the processing device (e.g., the processor117) retrieves, from one of a submission queue of the plurality of submission queues of the memory system (e.g., the memory sub-system110), a command request (e.g., a read request or a write request) for the memory system, where the submission queue is associated with a queue identifier. For some embodiments, operation304is performed as part of the processing device (e.g., the processor117) scanning one or more submission queues (e.g., scan each submission queue) of the memory system (e.g., the memory sub-system110) for command requests to be executed.

At operation306, the processing device (e.g., the processor117) stores an entry for a command request in a command queue of the memory system, where the entry comprises a command queue sequence identifier, the queue identifier associated with the command request, and a memory address of the command request (e.g., the  memory address upon which the command request is operating). For some embodiments, the entry comprises a command type of the command request. The command type can include a read command type or a write command type. The entry can further comprise a data size (e.g., block size) for the command request, and a command identifier associated with the command request, which the host system can use to uniquely identify the command request. The memory address can comprise a LBA, and the memory address can correspond to a memory location (e.g., superblock, block, or a page) on a memory device of the memory system.

Thereafter, at operation310, the processing device (e.g., the processor117) causes execution of a preconditioned operation based on the plurality of command requests determined (e.g., identified) by operation308. For some embodiments, the preconditioned operation the common command type of the plurality of command requests (determined by operation308) is a read command type (e.g., the plurality of command requests is a plurality of read requests), and the preconditioned operation comprises a read-ahead operation configured to prefetch stored data from a set of memory addresses (e.g., a second sequence of memory addresses corresponding to a second sequence of memory locations on the memory  system) based on the (first) sequence of memory addresses of the plurality of command requests. The set of memory addresses can be determined by the read-ahead operation based on one or more factors traditionally considered by read-ahead operations. Additionally, for some embodiments, the preconditioned operation comprises a merging operation configured to merge the plurality of command requests into a single command request to be executed on the sequence of memory addresses. For example, the common command type can comprise a read command type (the plurality of command requests is a plurality of read requests), and each read request in the plurality of write requests is configured to read from its respective memory address. In such a case, the plurality of read requests can be merged into a single read request configured to read stored data from a range of memory addresses that corresponds to the sequence of memory addresses. Similarly, the common command type can comprise a write command type (the plurality of command requests is a plurality of write requests), and each write request in the plurality of write requests is configured to write a full block of its respective data to its respective memory address. In such a case, the merge operation can merge the plurality of write requests into a single write request configured to write the respective data across a range of memory addresses that corresponds to the sequence of memory addresses.

FIG.4is a flow diagram of an example method for block caching with queue identifiers, in accordance with some embodiments of the present disclosure. In particular,FIG.4illustrates a command stream410, a plurality of queue pairs420of a memory system (e.g., the memory sub-system110), and a command queue430of the memory system. As shown, as the command stream410flows into the memory system, a command request (e.g., read request or write request) from the command stream410is stored to a submission queue (e.g., SQ-4) of one of the queue pairs (of the plurality of queue pairs420) associated with the queue identifier (e.g., QID-4) of the command request. As the memory system scans submission queues of the plurality of queue pairs420for command requests (e.g., each submission queue is scanned for a new command request), the memory system can retrieve a detected command request from one of the submission queues and add the detected command request to the command queue430(e.g., added to an entry of the command queue).  The command queue430can serve as a central queue for processing (e.g., executing) command requests within the memory system. An entry for a given command request in the command queue430includes information describing: a command sequence identifier (CMD Sequence ID); a command type (CMD Type); a submission queue identifier (SQID); a completion queue identifier (CQID); a command identifier (CMD ID); a namespace identifier (NameSpace ID); a memory address (e.g., LBA); and a data size of the command (e.g., block size). The SQID and CQID of an entry typically have the same value. The SQID corresponds to a submission queue (of the plurality of queue pairs420) through which the given command request was received by the memory system, and the CQID corresponds to a completion queue (of the plurality of queue pairs420) through which the results of the given command request are to be passed back to a host system (e.g.,120). The CMD ID can be an identifier provided with (e.g., included in) the given command request when it is received from the host system, and can be used to uniquely identify the given command request within the memory system, the host system, or both. For instance, the CMD ID can be included with an entry added to the completion queue for the given command request so that the host system can match the result with the given command request. The NameSpace ID can identify the namespace in which the given command request is operating, and the memory address (e.g., LBA) can correspond to a memory location of the memory system upon which the given command request is to be processed (e.g., executed). For some embodiments, the identified namespace determines to which memory location the memory address corresponds.

During operation of an embodiment, the memory system can analyze the command queue430and identify command requests that satisfy the following preconditions: have a common command type; and operating on a sequence of memory addresses. To do so, the memory system can filter the command queue430based on (e.g., by) a single submission queue identifier, a single namespace identifier, or both. For instance, by filtering the command queue430for read requests associated with the SQID of 0x0003, the memory system can determine that a first set (e.g., sub-sequence) of entries432-1and a second set (e.g., sub-sequence) of entries432-2are operating on a sequence of memory addresses (e.g., LBAs  0x00000000, 0x00000004, 0x00000008, 0x0000000C). In response, the memory system can perform a preconditioned operation, such as a read-ahead operation or a merge operation, based on the sequence of memory addresses formed by the first and second sets of entries432-1,432-2. In another instance, if the memory system filtered the command queue430for read requests associated with the SQID of 0x0003 and a NameSpace ID of 4, the memory system can determine that a first set (e.g., sub-sequence) of entries432-1and a third set (e.g., sub-sequence) of entries432-3are operating on a sequence of memory addresses (e.g., LBAs 0x00000000, 0x00000004, 0x00000008, 0x0000000C). In response, the memory system can perform a preconditioned operation, such as a read-ahead operation or a merge operation, based on the sequence of memory addresses formed by the first and third sets of entries432-1,432-3. WhileFIG.4illustrates detection of a precondition of memory address sequentiality, it will be appreciated that for some embodiments, other preconditions can be detected for prior to execution of a relevant preconditioned operation.

The example computer system500includes a processing device502, a main memory504(e.g., ROM, flash memory, DRAM such as SDRAM or Rambus DRAM (RDRAM), etc.), a static memory506(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device518, which communicate with each other via a bus530.

The processing device502represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device502can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device502can also be one or more special-purpose processing devices such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device502is configured to execute instructions526for performing the operations and steps discussed herein. The computer system500can further include a network interface device508to communicate over a network520.

In one embodiment, the instructions526include instructions to implement functionality corresponding to performing one or more data read-ahead operations on the memory sub-system110as described herein (e.g., the queue identifier-based operation performer113ofFIG.1). While the machine-readable storage medium524is shown in an example embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.