Display device and gate driving circuit

A display device includes: a display panel; and a gate driving circuit, a kth driving stage from among driving stages for outputting a kth gate signal from among gate signals, where k is a natural number of two or more, including: at least one output transistor including a control electrode connected to a first node, an input electrode to receive a clock signal, and an output electrode to output an output signal; a first control transistor to output an activation signal to the first node before the kth gate signal is outputted; a capacitor to boost a voltage of the first node after the activation signal is provided to the first node; second and third control transistors connected in series between the first node and a voltage input terminal; and a first intermediate node between the second control transistor and the third control transistor for receiving the output signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2016-0000551, under 35 U.S.C. § 119, filed on Jan. 4, 2016, in the Korean Intellectual Property Office (KIPO), the entire content of which is hereby incorporated by reference.

BACKGROUND

One or more aspects of example embodiments of the present disclosure relate to a display device, and more particularly, to a display device including a gate driving circuit.

2. Description of the Related Art

A display device includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the plurality of gate lines and the plurality of data lines, respectively. The display device includes a gate driving circuit for providing gate signals to the plurality of gate lines, and a data driving circuit for outputting data signals to the plurality of data lines.

The gate driving circuit includes a shift register including a plurality of driving circuits (hereinafter referred to as driving stages). The plurality of driving stages respectively output gate signals corresponding to the plurality of gate lines. Each of the plurality of driving stages includes a plurality of operatively-connected transistors.

The above information disclosed in this Background section is for enhancement of understanding of the background of the inventive concept, and therefore, it may contain information that does not constitute prior art.

SUMMARY

One or more aspects of example embodiments of the present disclosure are directed toward a display device including a gate driving circuit integrated on the display device.

One or more aspects of example embodiments of the present disclosure are directed toward a display device including a less-defective gate driving circuit.

According to an example embodiment of the inventive concept, a display device includes: a display panel including a plurality of gate lines; and a gate driving circuit including a plurality of driving stages configured to output a plurality of gate signals to the gate lines, a kth driving stage from among the plurality of driving stages for outputting a kth gate signal from among the plurality of gate signals, where k is a natural number of two or more, the kth driving stage including: at least one output transistor including a control electrode connected to a first node, an input electrode configured to receive a clock signal, and an output electrode configured to output an output signal; a first control transistor configured to output an activation signal to turn on the at least one output transistor to the first node before the kth gate signal is outputted; a capacitor configured to boost a voltage of the first node after the activation signal is provided to the first node; and second and third control transistors connected in series between the first node and a voltage input terminal configured to receive a discharge voltage, wherein a first intermediate node between the second control transistor and the third control transistor is configured to receive the output signal.

In an embodiment, the at least one output transistor may include a first output transistor configured to output the kth gate signal, and a second output transistor configured to output a kth carry signal synchronized with the kth gate signal; and the first intermediate node may be configured to receive one of the kth gate signal and the kth carry signal as the output signal.

In an embodiment, the capacitor may be connected between an output electrode of the first output transistor and a control electrode of the first output transistor.

In an embodiment, the second and third control transistors may be configured to be turned on in response to a k+1th output signal outputted from a k+1th driving stage from among the driving stages.

In an embodiment, the activation signal may be a k−1th output signal outputted from a k−1th driving stage from among the driving stages.

In an embodiment, the display device may further include fourth and fifth control transistors connected in series between the first node and the voltage input terminal, the fourth and fifth control transistors being configured to be turned on during a period different from the second and third control transistors, and a second intermediate node between the fourth control transistor and the fifth control transistor may be configured to receive the output signal.

In an embodiment, the display device may further include inverter transistors configured to provide a switching signal to a second node connected to control electrodes of the fourth and fifth control transistors, and the inverter transistors may include: at least one output inverter transistor configured to output the clock signal to the second node; and at least one pull-down inverter transistor configured to pull down a voltage of the second node during a period when the kth gate signal is outputted.

In an embodiment, the display device may further include a pull-down transistor configured to provide the discharge voltage to the output electrode of the at least one output transistor after the kth gate signal is outputted.

According to an example embodiment of the inventive concept, a display device includes: a display panel including a plurality of gate lines; and a gate driving circuit including a plurality of driving stages electrically connected to the gate lines, respectively, a kth driving stage, where k is a natural number of two or more, from among the driving stages comprising: an output unit configured to generate a kth output signal based on a clock signal, and to output the kth output signal to an output terminal in response to a voltage of a first node; a first control unit configured to control the voltage of the first node; a second control unit configured to output a switching signal to a second node, the switching signal being generated based on the clock signal; and a pull-down unit configured to pull down a voltage of the output terminal after the kth output signal is outputted. The first control unit includes: a first control transistor configured to provide an activation signal for activating the output unit to the first node before the kth output signal is outputted; and second and third control transistors connected in series between the first node and a first voltage input terminal configured to receive a first discharge voltage. The kth output signal is to be provided to a first intermediate node between the second control transistor and the third control transistor.

In an embodiment, the kth output signal may include a kth gate signal and a kth carry signal, and the output terminal includes a first output terminal and a second output terminal, and the output unit may include: a first output transistor including a control electrode connected to the first node, an input electrode configured to receive the clock signal, and an output electrode configured to output the kth gate signal to the first output terminal; a second output transistor including a control electrode connected to the first node, an input electrode configured to receive the clock signal, and an output electrode configured to output the kth carry signal to the second output terminal; and a capacitor connected between the output electrode of the first output transistor and the control electrode of the first output transistor.

In an embodiment, the pull-down unit may include: a first pull-down unit configured to pull down the first output terminal after the kth gate signal is outputted; and a second pull-down unit configured to pull down the second output terminal after the kth carry signal is outputted.

In an embodiment, the first pull-down unit may include first and second pull-down transistors connected in series between the first output terminal and a second voltage input terminal configured to receive a second discharge voltage having a different level than that of the first discharge voltage; and the kth output signal may be provided to a second intermediate node between the first pull-down transistor and the second pull-down transistor.

In an embodiment, the first pull-down unit may further include third and fourth pull-down transistors connected in series between the first output terminal and the second voltage input terminal, the third and fourth pull-down transistors being configured to be turned on in a different period from a period when the first and second pull-down transistors are turned on; and the kth output signal may be provided to a third intermediate node between the third pull-down transistor and the fourth pull-down transistor.

In an embodiment, the second pull-down unit may include first and second pull-down transistors connected in series between the first output terminal and the first voltage input terminal; and the kth output signal may be provided to a second intermediate node between the first pull-down transistor and the second pull-down transistor.

In an embodiment, the second pull-down unit may further include third and fourth pull-down transistors connected in series between the first output terminal and the first voltage input terminal, the third and fourth pull-down transistors being configured to be turned on in a different period from a period when the first and second pull-down transistors are turned on; and the kth output signal may be provided to a third intermediate node between the third pull-down transistor and the fourth pull-down transistor.

In an embodiment, the second and third control transistors may be configured to be turned on in response to a k+1th output signal outputted from a k+1th driving stage from among the driving stages.

In an embodiment, the activation signal may be a k−1th output signal outputted from a k−1th driving stage.

In an embodiment, the first control unit may further include fourth and fifth control transistors connected in series between the first node and the first voltage input terminal and configured to be turned on in a different period from a period when the second and third control transistors are turned on; and the kth output signal may be provided to a second intermediate node between the fourth control transistor and the fifth transistor.

In an embodiment, the fourth and fifth control transistors may be configured to be turned on by the switching signal after the kth output signal is outputted.

DETAILED DESCRIPTION

FIG. 1is a plan view of a display device according to an embodiment of the inventive concept.FIG. 2is a timing diagram illustrating signals of a display device according to an embodiment of the inventive concept.

As shown inFIGS. 1 and 2, a display device according to an embodiment of the inventive concept includes a display panel DP, a gate driving circuit GDC, and a data driving circuit DDC. Although one gate driving circuit GDC and six data driving circuits DDC are shown exemplarily, the inventive concept is not limited thereto.

The display panel DP is not particularly limited, and may include various display panels, such as a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, and/or an electrowetting display panel. For convenience, the display panel DP is described here as a liquid crystal display panel. When the display panel DP is a liquid crystal display panel, a liquid crystal display device including the liquid crystal display panel may further include a polarizer and a backlight unit (e.g., a backlight or a backlight source).

The display panel DP includes a first display substrate DS1, a second display substrate DS2spaced from the first display substrate DS1, and a liquid crystal layer LCL (e.g., seeFIG. 4) disposed between the first display substrate DS1and the second display substrate DS2. On a plane, the display panel DP includes a display area DA including a plurality of pixels PX11to PXnm, and a non-display area NDA surrounding the display area DA.

The first display substrate DS1includes a plurality of gate lines GL1to GLn and a plurality of data lines DL1to DLm crossing the plurality of gate lines GL1to GLn. The plurality of gate lines GL1to GLn are connected to the gate driving circuit GDC. The plurality of data lines DL1to DLm are connected to the data driving circuit DDC. For convenience, only some of the plurality of gate lines GL1to GLn and only some of the plurality of data lines DL1to DLm are illustrated inFIG. 1. Additionally, the first display substrate DS1may include a dummy gate line GL-D disposed in the non-display area NDA. However, the inventive concept is not limited thereto, and according to an embodiment of the inventive concept, the dummy gate line GL-D may be omitted.

For convenience, only some of the plurality of pixels PX11to PXnm are illustrated inFIG. 1. The plurality of pixels PX11to PXnm are respectively connected to corresponding gate lines from among the plurality of gate lines GL1to GLn and corresponding data lines from among the plurality of data lines DL1to DLm. However, the dummy gate line GL-D is not connected to the plurality of pixels PX11to PXnm.

The plurality of pixels PX11to PXnm may be divided into a plurality of groups according to a color to be displayed. The plurality of pixels PX11to PXnm may display any one of primary colors. The primary colors may include red, green, blue, and/or white. However, the inventive concept is not limited thereto, and thus, the primary colors may further include (or alternatively include) various colors, such as yellow, cyan, magenta, etc.

As shown inFIGS. 1 and 2, the gate driving circuit GDC and the data driving circuit DDC receive a control signal from a first signal control unit SC (e.g., a first controller, for example, a timing controller). The first signal control unit may be mounted on the main circuit board MCB. The first signal control unit receives image data and control signals from an external first graphic control unit (e.g., a first graphic controller). The control signals may include vertical sync signals Vsync that are signals for distinguishing frame periods Fn−1, Fn, and Fn+1, horizontal sync signals Hsync that are signals for distinguishing horizontal periods HP (e.g., row distinction signals), data enable signals (that may be in high level only during a period where data is outputted to display a data incoming area), and clock signals.

The gate driving circuit GDC generates gate signals GS1to GSn on the basis of a control signal received from the first signal control unit SC during frame periods Fn−1, Fn, and Fn+1, and outputs the gate signals GS1to GSn to the plurality of gate lines GL1to GLn. The gate signals GS1to GSn may be sequentially outputted in correspondence to the horizontal periods HP. The gate driving circuit GDC and the pixels PX11to PXnm may be formed concurrently (e.g., simultaneously) through a thin film process. For example, the gate driving circuit GDC may be mounted in an Amorphous Silicon TFT Gate driver circuit (ASG) form or an Oxide Semiconductor TFT Gate driver circuit (OSG) form at (e.g., in) the non-display area NDA.

FIG. 1illustrates one gate driving circuit GDC connected to the left ends of the plurality of gate lines GL1to GLn. However the inventive concept is not limited thereto, and according to an embodiment of the inventive concept, a display device may include two gate driving circuits. One of the two gate driving circuits may be connected to the left ends of the plurality of gate lines GL1to GLn and the other one of the two may be connected to the right ends of the plurality of gate lines GL1to GLn. Further, or alternately, one of the two gate driving circuits may be connected to odd gate lines and the other one of the two may be connected to even gate lines.

As shown inFIGS. 1 and 2, the data driving circuit DDC generates gray level voltages according to image data provided from the first signal control unit SC on the basis of a control signal received from the first signal control unit SC. The data driving circuit DDC outputs the gray level voltages as data signals DDS to the plurality of data lines DL1to DLm.

The data signals DDS may include positive voltages each having a positive value with respect to a common voltage, and/or negative voltages each having a negative value with respect to the common voltage. Some of data signals applied to the data lines DL1to DLm may each have a positive polarity and others may each have a negative polarity during each of the horizontal periods HP. The polarity of the data signals DDS may be inverted according to the frame periods Fn−1, Fn, and Fn+1, in order to prevent or reduce the deterioration of liquid crystals. The data driving circuit DDC may generate data signals inverted by each frame period unit in response to an invert signal.

The data driving circuit DDC may include a driving chip DC and a flexible circuit board FPC on which the driving chip DC is mounted. The flexible circuit board FPC connects (e.g., electrically connects) the main circuit board MCB and the first display substrate DS1to each other. The plurality of driving chips DC provide data signals to corresponding data lines from among the plurality of data lines DL1to DLm.

FIG. 1illustrates a Tape Carrier Package (TCP) type (form) data driving circuit DDC exemplarily. However, the inventive concept is not limited thereto, for example, according to an embodiment of the inventive concept, the data driving circuit DDC may be disposed at (e.g., in) the non-display area NDA of the first display substrate DS1through a Chip on Glass (COG) method.

FIG. 3is an equivalent circuit diagram of a pixel PXij according to an embodiment of the inventive concept.FIG. 4is a sectional view of a pixel PXij in a display panel DP according to an embodiment of the inventive concept. Each of the plurality of pixels PX11to PXnm shown inFIG. 1may have the same or substantially the same circuit as that shown inFIG. 3.

As shown inFIG. 3, the pixel PXij includes a pixel thin film transistor (hereinafter referred to as a pixel transistor) TR, a liquid crystal capacitor Clc, and a storage capacitor Cst. Hereinafter, a transistor refers to a thin film transistor. According to an embodiment of the inventive concept, the storage capacitor Cst may be omitted.

The pixel transistor TR is electrically connected to an ith gate line GLi and a jth data line DLj. The pixel transistor TR outputs a pixel voltage corresponding to a data signal received from the jth data line DLj in response to a gate signal received from the ith gate line GLi.

The liquid crystal capacitor Clc is charged with the pixel voltage outputted from the pixel transistor TR. An arrangement of liquid crystal directors included in the liquid crystal layer LCL (seeFIG. 4) is changed according to a charge amount charged in the liquid crystal capacitor Clc. The light incident to the liquid crystal layer may be transmitted or blocked according to an arrangement of the liquid crystal directors.

The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc. The storage capacitor Cst maintains or substantially maintains an arrangement of the liquid crystal directors during a set or predetermined period.

As shown inFIG. 4, the pixel transistor TR is disposed on a first base substrate SUB1. The pixel transistor TR includes a control electrode GE connected to the ith gate line GLi (seeFIG. 3), an activation part AL overlapping with the control electrode GE, an input electrode DE connected to the jth data line DLj (seeFIG. 3), and an output electrode SE spaced from the input electrode DE.

The liquid crystal capacitor Clc includes a pixel electrode PE and a common electrode CE. The storage capacitor Cst includes the pixel electrode PE and a portion of a storage line STL overlapping with the pixel electrode PE.

The ith gate line GLi and the storage line STL are disposed on a surface (e.g., one surface) of the first base substrate SUB1. The control electrode GE is branched from the ith gate line GLi. The ith gate line GLi and the storage line STL may include a metal (for example, Al, Ag, Cu, Mo, Cr, Ta, Ti, etc.) or an alloy thereof. The ith gate line GLi and the storage line STL may have a multi-layer structure, and for example, may include a Ti layer and a Cu layer.

A first insulating layer10covering the control electrode GE and the storage line STL is disposed on a surface (e.g., one surface) of the first base substrate SUB1. The first insulating layer10may include at least one of an inorganic material and an organic material. The first insulating layer10may be an organic layer or an inorganic layer. The first insulating layer10may have a multi-layer structure, and for example, may include a silicon nitride layer and a silicon oxide layer.

The activation part AL overlapping with the control electrode GE is disposed on the first insulating layer10. The activation part AL may include a semiconductor layer and an ohmic contact layer. The semiconductor layer may include silicon. The semiconductor layer may include amorphous silicon or poly silicon. The semiconductor layer is disposed on the first insulating layer10, and the ohmic contact layer is disposed on the semiconductor layer. The ohmic contract layer may include a dopant doped with higher density than that of the semiconductor layer.

According to an embodiment of the inventive concept, the activation part AL may include a metal oxide semiconductor layer. The metal oxide semiconductor layer may include Indium Tin Oxide (ITO), Indium Gallium Zinc Oxide (IGZO), and Zinc Oxide (ZnO). The materials may be amorphous.

The input electrode DE and the output electrode SE are disposed on the activation part AL. The input electrode DE and the output electrode SE are spaced from each other. Each of the input electrode DE and the output electrode SE partially overlaps with the control electrode GE.

A second insulating layer20covering the activation part AL, the output electrode SE, and the input electrode DE is disposed on the first insulating layer10. The second insulating layer20may include at least one of an inorganic material and an organic material. The second insulating layer20may be an organic and/or inorganic layer. The second insulating layer20may have a multi-layer structure, and for example, may include a silicon nitride layer and a silicon oxide layer.

Although the pixel transistor TR having a staggered structure is shown inFIG. 1exemplarily, a structure of the pixel transistor TR is not limited thereto. For example, the pixel transistor TR may have a planar structure.

A third insulating layer30is disposed on the second insulating layer20. The third insulating layer30provides a flat surface. The third insulating layer30may include an organic material.

The pixel electrode PE is disposed on the third insulating layer30. The pixel electrode PE is connected to the output electrode SE through a contact hole CH penetrating through the second insulating layer20and the third insulating layer30. The pixel electrode PE may include a transparent conductive oxide. An alignment layer covering the pixel electrode PE may be disposed on the third insulating layer30.

A second display substrate DS2may include a second base substrate SUB2and a color filter layer CF disposed on (e.g., under) a surface (e.g., one surface) of the second base substrate SUB2. A common electrode CE is disposed on (e.g., under) the color filter layer CF. A common voltage is applied to the common electrode CE. The common voltage and the pixel voltage may have different values. An alignment layer covering the common electrode CE may be disposed on (e.g., under) the common electrode CE. Another insulating layer may be disposed between the color filter layer CF and the common electrode CE.

The pixel electrode PE and the common electrode CE with the liquid crystal layer LCL therebetween form the liquid crystal capacitor Clc. Additionally, portions of the pixel electrode PE and the storage line STL, which are disposed with the first insulating layer10, the second insulating layer20, and the third insulating layer30therebetween, form the storage capacitor Cst. The storage line STL receives a storage voltage having a different value than that of a pixel voltage. The storage voltage may have a value that is the same as or different from that of the common voltage.

On the other hand, a section of the pixel PXij shown inFIG. 3is just one example. For example, unlike those ofFIG. 3, at least one of the color filter layer CF and the common electrode CE may be disposed on the first display substrate DS1. That is, a liquid crystal display panel according to an embodiment of the inventive concept may include a pixel in a Vertical Alignment (VA) mode, a Patterned Vertical Alignment (PVA) mode, an in-plane switching (IPS) mode, a fringe-field switching (FFS) mode, or a Plane to Line Switching (PLS) mode.

FIG. 5is a block diagram illustrating a gate driving circuit GDC according to an embodiment of the inventive concept. As shown inFIG. 5, the gate driving circuit GDC includes a plurality of driving stages SRC1to SRCn. The plurality of driving stages SRC1to SRCn are connected in cascade to each other.

According to an embodiment of the inventive concept, the plurality of driving stages SRC1to SRCn are respectively connected to the plurality of gate lines GL1to GLn. The plurality of driving stages SRC1to SRCn respectively provide gate signals to the plurality of gate lines GL1to GLn. The gate driving circuit GDC may further include a dummy stage SRC-D connected to a last driving stage SRCn from among the plurality of driving stages SRC1to SRCn. The dummy stage SRC-D may be connected to the dummy gate line GL-D.

Each of the plurality of driving stages SRC1to SRCn includes an output terminal OUT, a carry terminal CR, an input terminal IN, a control terminal CT, a clock terminal CK, a first voltage input terminal V1, and a second voltage input terminal V2.

The output terminal OUT of each of the plurality of driving stages SRC1to SRCn is connected to a corresponding gate line from among the plurality of gate lines GL1to GLn. Gate signals generated from the plurality of driving stages SRC1to SRCn are provided to the plurality of gate lines GL1to GLn, respectively, through the corresponding output terminal OUT.

The carry terminal CR of each of the driving stages SRC1to SRCn is electrically connected to the input terminal IN of a next driving stage of a corresponding driving stage. The carry terminal CR of each of the plurality of driving stages SRC1to SRCn outputs a carry signal.

The input terminal IN of each of the plurality of driving stages SRC2to SRCn, other than the first driving stage SRC1, receives a carry signal of a previous driving stage of a corresponding driving stage. For example, the input terminal IN of the third driving stage SRC3receives the carry signal of the second driving stage SRC2, that is an immediately previous driving stage. The input terminal IN of the first driving stage SRC1from among the plurality of driving stages SRC1to SRCn receives a start signal SW for starting the driving of the gate driving circuit GDC, instead of a carry signal of a previous driving stage.

The control terminal CT of each of the driving stages SRC1to SRCn is electrically connected to the carry terminal CR of the next driving stage of a corresponding driving stage. The control terminal CT of each of the plurality of driving stages SRC1to SRCn receives the carry signal of the next driving stage of a corresponding driving stage. For example, the control terminal CT of the second driving stage SRC2receives a carry signal outputted from the carry terminal CR of the third driving stage SRC3, that is the immediately next driving stage of the second driving stage SRC2. However, the inventive concept is not limited thereto, and according to an embodiment of the inventive concept, the control terminal CT of each of the plurality of driving stages SRC1to SRCn may be electrically connected to the output terminal OUT of the next driving stage of a corresponding driving stage.

The control terminal CT of the driving stage SRCn disposed at the end (e.g., a last driving stage) receives a carry signal outputted from the carry terminal CR of the dummy stage SRC-D. The control terminal CT of the dummy stage SRC-D receives the start signal STV.

The clock terminal CK of each of the plurality of driving stages SRC1to SRCn receives one of a first clock signal CKV and a second clock signal CKVB. For example, each of the clock terminals CK of odd numbered driving stages (e.g., SRC1and SRC3) from among the plurality of driving stages SRC1to SRCn may receive the first clock signal CKV, and each of the clock terminals CK of even numbered driving stages (e.g., SRC2and SRCn) from among the plurality of driving stages SRC1to SRCn may receive the second clock signal CKVB. The first clock signal CKV and the second clock signal CKVB may have different phases from each other. For example, the second clock signal CKVB may be a signal obtained by inverting or delaying a phase of the first clock signal CKV.

The first voltage input terminal V1of each of the plurality of driving stages SRC1to SRCn receives a first discharge voltage VSS1. For example, the first discharge voltage VSS1may be about −7 V to about −7.5 V. The second voltage input terminal V2of each of the plurality of driving stages SRC1to SRCn receives a second discharge voltage VSS2. The second discharge voltage VSS2and the first discharge voltage VSS1may have different levels. For example, the second discharge voltage VSS2may have a lower level than that of the first discharge voltage VSS1. For example, the second discharge voltage VSS2may be about −10V to about −11.5V.

According to an embodiment of the present disclosure, depending on a circuit configuration, each of the plurality of driving stages SRC1to SRCn may omit one of the output terminal OUT, the input terminal IN, the carry terminal CR, the control terminal CT, the clock terminal CK, the first voltage input terminal V1, and the second voltage input terminal V2, or may further include other terminals. For example, the carry terminal CR may be omitted and/or one of the first voltage input terminal V1and the second voltage input terminal V2may be omitted. Additionally, the connection relationship of the plurality of driving stages SRC1to SRCn may be variously changed.

FIG. 6Ais a circuit diagram of a driving stage SRCk according to an embodiment of the inventive concept.FIG. 6Bis a signal waveform diagram of a driving stage SRCk shown inFIG. 6A. AlthoughFIG. 6Billustrates input/output signals as square waves for convenience, the input/output signals may be variously modified, for example, by external factors such as RC delay.

FIG. 6Aillustrates a kth driving stage SRCk from among the plurality of n driving stages SRC1to SRCn shown inFIG. 5. Each of the plurality of driving stages SRC1to SRCn shown inFIG. 5may have the same or substantially the same circuit structure as that of the kth driving stage SRCk.

Referring toFIGS. 6A and 6B, the kth driving stage SRCk includes an output unit100, a first control unit200, a second control unit300, a first pull-down unit400, and a second pull-down unit500. The circuit structure of the kth driving stage is just exemplary and may be variously changed.

The output unit100is activated in response to a voltage of a first node NQ, and the activated output unit100outputs output signals GSk and CRSk. The output unit100is turned on/off according to a voltage level of the first node NQ. The first control unit200controls a voltage of the first node NQ. The second control unit300outputs an invert signal, which is generated based on the clock signal CKV, to a second node NA. After the output signals GSk and CRSk are outputted, the first pull-down unit400pulls down a voltage of the output terminal OUT. After the output signals GSk and CRSk are outputted, the second pull-down unit500pulls down a voltage of the carry terminal CR. However, the inventive concept is not limited thereto, and in an embodiment, one of the first pull-down unit400and the second pull-down unit500may be omitted.

Referring toFIGS. 6A and 6B, the output signals GSk and CRSk may include a kth gate signal GSk and a kth carry signal CRSk, which are generated based on the clock signal CKV. The output unit100includes a first output unit110for outputting the kth gate signal GSk, and a second output unit120for outputting the kth carry signal CRSk. The kth carry signal CRSk may be a signal synchronized with the kth gate signal GSk. The term “synchronized with” refers to two signals having a high voltage level during the same or substantially the same period. However, the high voltage levels of the two signals may not need to be the same.

The first output unit110includes a first output transistor TR1-1. The first output transistor TR1-1includes a control electrode connected to the first node NQ, an input electrode for receiving a first clock signal CKV, and an output electrode for outputting a kth gate signal GSk. The second output unit120includes a second output transistor TR1-2. The second output transistor TR1-2includes a control electrode connected to the first node NQ, an input electrode for receiving a first clock signal CKV, and an output electrode for outputting a kth carry signal CRSk.

As shown inFIG. 6B, the first clock signal CKV and the second clock signal CKVB may be signals with an inverted phase from each other. For example, the first clock signal CKV and the second clock signal CKVB may have a phase difference of 180°. Each of the first clock signal CKV and the second clock signal CKVB includes low periods VL-C (or a low voltage) having a relatively low level and high periods VH-C (or a high voltage) having a relatively high level. Each of the first clock signal CKV and the second clock signal CKVB may include alternating low periods and high periods. The high voltage VH-C may be, for example, about 14 V to about 15 V. The low voltage VL-C, for example, may have a level corresponding to the second discharge voltage VSS2.

The kth gate signal GSk includes a low period having a relatively low level and a high period having a relatively high level. The kth gate signal GSk may have a low voltage VL-G during a low period and a high voltage VH-G during a high period. The low voltage VL-G of the kth gate signal GSk may have a level, for example, corresponding to the first discharge voltage VSS1. The low voltage VL-G may be, for example, about −7.0 V to about −7.5 V. The kth gate signal GSk may have a level corresponding to the low voltage VL-C of the first clock signal CKV during some periods (for example, the HPk−1 period ofFIG. 6B). The high voltage VH-G of the kth gate signal GSk may have a level corresponding to the high voltage VH-C of the first clock signal CKV. This will be described in more detail later.

The kth gate signal CRSk includes a low period having a relatively low level and a high period having a relatively high level. Because the kth carry signal CRSk is generated based on the first clock signal CKV, it has a similar or same low and high voltage levels to those of the first clock signal CKV.

Referring toFIGS. 6A and 6B, the first control unit200controls a voltage of the first node NQ. The first control unit200provides an activation signal to the first node NQ, and provides a discharge voltage VSS2to the first node NQ.

In the present embodiment, the activation signal may be a k−1th carry signal CRSk−1 outputted from a k−1th driving stage SRCk−1. The first control unit200provides the second discharge voltage VSS2to the first node NQ in response to a k+1th carry signal CRSk+1 outputted from a k+1th driving stage, and provides the second discharge voltage VSS2to the first node NQ in response to a switching signal outputted from the second control unit300.

The first control unit200includes a transistor TR2-1(hereinafter referred to as a first control transistor) for outputting the carry signal CRSk−1 to the first node NQ. The carry signal CRSk−1 is outputted to the first node NQ before the kth gate signal GSk is outputted.

FIG. 6Bis a view illustrating a horizontal period HPk (hereinafter referred to as a kth horizontal period) where a kth gate signal GSk is outputted, an immediately previous horizontal period HPk−1 (hereinafter referred to as a k−1th horizontal period), and an immediately next (e.g., after) horizontal period HPk+1 (hereinafter referred to as an k+1th horizontal period), from among a plurality of horizontal periods.

The first control transistor TR2-1includes a control electrode and an input electrode, which commonly receive the k−1th carry signal CRSk−1. The first control transistor TR2-1includes an output electrode connected to the first node NQ.

The first control unit200further includes control transistors TR2-21and TR2-22in a first group, and control transistors TR2-31and TR2-32in a second group. The control transistors TR2-21and TR2-22in the first group and the control transistors TR2-31and TR2-32in the second group deactivate the output unit100.

The control transistors TR2-21and TR2-22in the first group are connected in series between the second voltage input terminal V2and the first node NQ. The control transistors TR2-31and TR2-32in the second group are connected in series between the second voltage input terminal V2and the first node NQ. A configuration of the first control unit200is not limited to the above described configuration, and one of the groups of the control transistors TR2-21and TR2-22in the first group and the control transistors TR2-31and TR2-32in the second group may be omitted or variously changed.

The first group of control transistors TR2-21and TR2-22includes a second control transistor TR2-21(including a control electrode connected to the control terminal CT, an input electrode for receiving the second discharge voltage VSS2, and an output electrode), and a third control transistor TR2-22(including a control electrode connected to the control terminal CT, an input electrode connected to the output electrode of the second control transistor TR2-21, and an output electrode connected to the first node NQ). A node connected to the output electrode of the second control transistor TR2-21and the input electrode of the third control transistor TR2-22is referred to as a first intermediate node NM1.

The second group of control transistors TR2-31and TR2-32includes a fourth control transistor TR2-31(including a control electrode connected to the second node NA, an input electrode for receiving the second discharge voltage VSS2, and an output electrode), and a fifth control transistor TR2-32(including a control electrode connected to the second node NA, an input electrode connected to the output electrode of the fourth control transistor TR2-31, and an output electrode connected to the first node NQ). A node connected to the output electrode of the fourth control transistor TR2-31and the input electrode of the fifth control transistor TR2-32is referred to as a second intermediate node NM2.

One of output signals GSk and CRSk may be applied to each of the first intermediate node NM1and the second intermediate node NM2. In the present embodiment, the output signal may be the kth carry signal CRSk. As the kth carry signal CRSk is applied to each of the first intermediate node NM1and the second intermediate node NM2, a voltage level of the first node NQ may be maintained or substantially maintained at greater than a set or predetermined value. This will be described in more detail later.

The first control unit200includes a capacitor CAP for boosting a voltage of the first node NQ. The capacitor CAP is connected between the output electrode of the first output transistor TR1-1and the control electrode (or the first node NQ) of the first output transistor TR1-1.

As shown inFIG. 6B, a voltage of the first node NQ is raised to a first high voltage VQ1by an operation of the first control transistor TR2-1during the k−1th horizontal period HPk−1. When the k−1th carry signal CRSk−1 is applied to the first node NQ, the capacitor CAP is charged with a voltage corresponding thereto. During the kth horizontal period HPk, the first high voltage VQ1is boosted to a second high voltage VQ2, and the kth gate signal GSk is outputted.

During the k+1th horizontal period HPk+1 and subsequent periods, a voltage of the first node NQ is dropped to the second discharge voltage VSS2by operations of the first group of control transistors TR2-21and TR2-22and the second group of control transistors TR2-31and TR2-32. During the k+1th horizontal period HPk+1, the first group of control transistors TR2-21and TR2-22are turned on in response to the k+1th carry signal CRSk+1 to provide the second discharge voltage VSS2to the first node NQ, and during subsequent periods after the k+1th horizontal period HPk+1, the second group of control transistors TR2-31and TR2-32are turned on in response to a switching signal to provide the second discharge voltage VSS2to the first node NQ.

Until the kth gate signal GSk in the next frame period of the k+1th horizontal period HPk+1 is outputted, a voltage of the first node NQ is maintained or substantially maintained at the second discharge voltage VSS2. Accordingly, until the kth gate signal GSk in the next frame period of the k+1th horizontal period HPk+1 is outputted, the first output transistor TR1-1and the second output transistor TR1-2are maintained or substantially maintained in an off state.

Referring toFIGS. 6A and 6B, the second control unit300outputs a switching signal to the second node NA. The switching signal is a signal having a phase of the second node NA shown inFIG. 6B.

The second control unit300may include at least one output inverter transistor for outputting the first clock signal CKV to the second node NA, and at least one pull-down inverter transistor for pulling down a voltage of the second node NA during a period where the kth gate signal GSk is outputted.

In the present embodiment, the output inverter transistor may include first and second inverter transistors TR3-1and TR3-2. The first inverter transistor TR3-1includes an input electrode and a control electrode connected commonly to the clock terminal CK, and an output electrode connected to a control electrode of the second inverter transistor TR3-2. The second inverter transistor TR3-2includes the control electrode connected to the output electrode of the first inverter transistor TR3-1, an input electrode connected to the clock terminal CK, and an output electrode connected to the second node NA.

In the present embodiment, the pull-down inverter transistor may include third and fourth inverter transistors TR3-3and TR3-4. The third inverter transistor TR3-3includes an output electrode connected to the output electrode of the first inverter transistor TR3-1, a control electrode connected to the carry terminal CR, and an input electrode connected to the second voltage input terminal V2. The fourth inverter transistor TR3-4includes an output electrode connected to the second node NA, a control electrode connected to the carry terminal CR, and an input electrode connected to the second voltage input terminal V2. However, the inventive concept is not limited thereto, and according to an embodiment of the inventive concept, the control electrodes of the third and fourth inverter transistors TR3-3and TR3-4may be connected to the output terminal OUT, and the output electrodes of the third and fourth inverter transistors TR3-3and TR3-4may be connected to the first voltage input terminal V1.

As shown inFIG. 6B, the second node NA has a high period and a low period, which correspond to a high period and a low period of the first clock signal CKV, except for during the kth horizontal period HPk. During the kth horizontal period HPk, the third and fourth inverter transistors TR3-3and TR3-4are turned on in response to the kth carry signal CRSk. At this time, a high voltage VH-C of the first clock signal CKV outputted from the second inverter transistor TR3-2is discharged to the second discharge voltage VSS2. During periods other than the kth horizontal period HPk, a high voltage VH-C and a low voltage VL-C of the first clock signal CKV outputted from the second inverter transistor TR3-2are provided to the second node NA.

Referring toFIGS. 6A and 6B, the first pull-down unit400includes a first pull-down transistor TR4-1and a second pull-down transistor TR4-2. One of the first pull-down transistor TR4-1and the second pull-down transistor TR4-2may be omitted.

The first pull-down transistor TR4-1includes an input electrode connected to the first voltage input terminal V1, a control electrode connected to the control terminal CT, and an output electrode connected to the output terminal OUT. The second pull-down transistor TR4-2includes an input electrode connected to the first voltage input terminal V1, a control electrode connected to the second node NA, and an output electrode connected to the output terminal OUT. However, the inventive concept is not limited thereto, and according to an embodiment of the inventive concept, at least one of the input electrode of the first pull-down transistor TR4-1and the input electrode of the second pull-down transistor TR4-2may be connected to the second voltage input terminal V2.

A voltage of the kth gate signal GSk after the k+1th horizontal period HPk+1 corresponds to a voltage of the output terminal OUT. During the k+1th horizontal period HPk+1, the first pull-down transistor TR4-1provides the first discharge voltage VSS1to the output terminal OUT in response to the k+1th carry signal CRSk+1. After the k+1th horizontal period HPk+1, the second pull-down transistor TR4-2provides the first discharge voltage VSS1to the output terminal OUT in response to a switching signal outputted from the second node NA.

Referring toFIGS. 6A and 6B, the second pull-down unit500includes a third pull-down transistor TR5-1and a fourth pull-down transistor TR5-2. The third pull-down transistor TR5-1includes an input electrode connected to the second voltage input terminal V2, a control electrode connected to the control terminal CT, and an output electrode connected to the carry terminal CR. The fourth pull-down transistor TR5-2includes an input electrode connected to the second voltage input terminal V2, a control electrode connected to the second node NA, and an output electrode connected to the carry terminal CR. However, the inventive concept is not limited thereto, and according to an embodiment of the inventive concept, at least one of the input electrode of the third pull-down transistor TR5-1and the input electrode of the fourth pull-down transistor TR5-2may be connected to the first voltage input terminal V1.

A voltage of the kth carry signal CRSk after the k+1th horizontal period HPk+1 corresponds to a voltage of the carry terminal CR. During the k+1th horizontal period HPk+1, the third pull-down transistor TR5-1provides the second discharge voltage VSS2to the carry terminal CR in response to the k+1th carry signal CRSk+1. After the k+1th horizontal period HPk+1, the fourth pull-down transistor TR5-2provides the second discharge voltage VSS2to the carry terminal CR in response to a switching signal outputted from the second node NA.

FIG. 7Ais a graph illustrating a voltage-current relationship of a transistor.FIG. 7Bis a view illustrating voltages of electrodes in a transistor.FIGS. 7C and 7Dare signal waveform diagrams of driving stages according to a simulation result.

FIG. 7Aillustrates a voltage-current relationship of a transistor (hereinafter, a metal oxide transistor) including a metal oxide semiconductor layer. The X-axis represents a voltage difference (hereinafter referred to as a gate-source voltage) between a control electrode and an input electrode of a transistor, and the Y-axis represents a current intensity. Transistors described with reference toFIGS. 6A and 6Bmay be metal oxide transistors. The metal oxide transistors are designed to have voltage-current characteristics as shown in a first graph GP1, but may have voltage-current characteristics as shown in a second graph GP2due to the influences of processes for manufacturing a display panel. That is, the metal oxide transistor may have negative shifted voltage-current characteristics in comparison to designed values.

A transistor having voltage-current characteristics as shown in the second graph GP2may have a greater leakage current in a negative gate-source voltage Vgs in comparison to a transistor having voltage-current characteristics as shown in the first graph GP1. That is, when a transistor is turned off, a malfunction may occur (that is, a current path may be formed).

According to the present embodiment, even with negative shifted voltage-current in comparison to designed values, a voltage of the first node NQ may be maintained or substantially maintained at a greater level than a reference value. As described in more detail later, this is because the gate-source voltage Vgs of the third control transistor TR2-22is changed when the carry signal CRSk is applied to the first intermediate node NM1.

FIG. 7Billustrates a comparison between first group of control transistors TR-R1and TR-R2according to a comparative example and the first group of control transistors TR2-21and TR2-22according to the present embodiment. In the present embodiment, it is assumed, for example, that the first discharge voltage VSS1is about −7 V, the second discharge voltage VSS2is about −10 V, and the high voltage VH-C (seeFIG. 6B) of the first clock signal CKV is about 14 V.

Referring toFIGS. 6A and 6B, during the kth horizontal period HPk, the gate-source voltage Vgs of each of the first group of control transistors TR-R1and TR-R2according to the comparative example is about 0 V. If each of the first group of control transistors TR-R1and TR-R2according to the comparative example has voltage-current characteristics as shown in the second graph GP2ofFIG. 7A, leakage current occurs between the first node NQ and the first voltage input terminal V1. Accordingly, during the kth horizontal period HPk, the first node NQ may not maintain a voltage level of greater than a reference value.

In comparison, during the kth horizontal period HPk, the gate-source voltage Vgs of the third control transistor TR2-22according to the present embodiment is about −24 V. Even if each of the first group of control transistors TR2-21and TR2-22according to the present embodiment has voltage-current characteristics as shown in the second graph GP2ofFIG. 7A, leakage current between the first node NQ and the first voltage input terminal V1may be prevented or reduced by the third control transistor TR2-22.

FIG. 7Cillustrates a Q node voltage G-NQ and a gate signal G-GS of the kth driving stage SRCk including the first group of control transistors TR-R1and TR-R2according to the comparative example.FIG. 7Dillustrates a Q node voltage G-NQ and a gate signal G-GS of the kth driving stage SRCk including the first group control of transistors TR2-21and TR2-22according to the present embodiment.

Referring toFIG. 7C, when the threshold voltage Vth of the first group of control transistors TR-R1and TR-R2is set to about −3.5 V, a normal operation is provided, but when the threshold voltage Vth is set to a value less than about −3.5 V, an abnormal operation is provided. Referring toFIG. 7D, until the threshold voltage Vth of the first group of control transistors TR2-21and TR2-22is set to about −6.0 V, a normal operation is provided. A driving stage according to the present embodiment may have a broader shift range of the voltage-current characteristics of normally-operating transistors in comparison to a driving stage according to the comparative example.

FIG. 8is a circuit diagram of a driving stage SRCk1according to an embodiment of the inventive concept. Hereinafter, the driving stage SRCk1is described with reference toFIG. 8. However, detailed descriptions for components that are the same or substantially the same as those described with reference toFIGS. 1 through 7Dare not repeated.

The driving stage SRCk1shown inFIG. 8and the driving stage SRCk shown inFIG. 6Ahave the same or substantially the same configuration, except for the first pull-down unit400and400-1. According to the embodiment ofFIG. 8, the first pull-down unit400-1includes a first group of pull-down transistors TR4-11and TR4-12and a second group of pull-down transistors TR4-21and TR4-22.

The first group of pull-down transistors TR4-11and TR4-12includes a first transistor TR4-11and a second transistor TR4-12. The first transistor TR4-11and the second transistor TR4-12are connected in series between the first voltage input terminal V1and the output terminal OUT.

The first transistor TR4-11includes an input electrode connected to the first voltage input terminal V1, a control electrode connected to the control terminal CT, and an output electrode. The second transistor TR4-12includes an input electrode connected to the output electrode of the first transistor TR4-11, a control electrode connected to the control terminal CT, and an output electrode connected to the output terminal OUT. A node connected to the output electrode of the first transistor TR4-11and the input electrode of the second transistor TR4-12is referred to as a third intermediate node NM3.

The second group of pull-down transistors TR4-21and TR4-22includes a third transistor TR4-21and a fourth transistor TR4-22. The third transistor TR4-21and the fourth transistor TR4-22are connected in series between the first voltage input terminal V1and the output terminal OUT.

The third transistor TR4-21includes an input electrode connected to the first voltage input terminal V1, a control electrode connected to the second node NA, and an output electrode. The fourth transistor TR4-22includes an input electrode connected to the output electrode of the third transistor TR4-21, a control electrode connected to the second node NA, and an output electrode connected to the output terminal OUT. A node connected to the output electrode of the third transistor TR4-21and the input electrode of the fourth transistor TR4-22is referred to as a fourth intermediate node NM4.

One of output signals GSk and CRSk may be applied to each of the third intermediate node NM3and the fourth intermediate node NM4. In the present embodiment, the output signal may be a kth carry signal CRSk. As the kth carry signal CRSk is applied to each of the third intermediate node NM3and the fourth intermediate node NM4, leakage current may not occur from the first pull-down unit400-1during the kth horizontal period HPk (e.g., seeFIG. 6B). Accordingly, a level of the kth gate signal GSk may be maintained or substantially maintained at a value greater than a reference value.

FIG. 9is a circuit diagram of a driving stage SRCk2according to an embodiment of the inventive concept. Hereinafter, the driving stage SRCk2is described with reference toFIG. 9. However, detailed descriptions for components that are the same or substantially the same as those described with reference toFIGS. 1 through 7Dare not repeated.

The driving stage SRCk2shown inFIG. 9and the driving stage SRCk shown inFIG. 6Ahave the same or substantially the same configuration, except for the second pull-down unit500and500-1. According to the embodiment ofFIG. 9, the second pull-down unit500-1includes a first group of pull-down transistors TR5-11and TR5-12and a second group of pull-down transistors TR5-21and TR5-22.

The first group of pull-down transistors TR5-11and TR5-12includes a first transistor TR5-11and a second transistor TR5-12. The first transistor TR5-11and the second transistor TR5-12are connected in series between the second voltage input terminal V2and the carry terminal CR

The first transistor TR5-11includes an input electrode connected to the second voltage input terminal V2, a control electrode connected to the control terminal CT, and an output electrode. The second transistor TR5-12includes an input electrode connected to the output electrode of the first transistor TR5-11, a control electrode connected to the control terminal CT, and an output electrode connected to the carry terminal CR. A node connected to the output electrode of the first transistor TR5-11and the input electrode of the second transistor TR5-12is referred to as a third intermediate node NM30.

The second group of pull-down transistors TR5-21and TR5-22include a third transistor TR5-21and a fourth transistor TR5-22. The third transistor TR5-21and the fourth transistor TR5-22are connected in series between the second voltage input terminal V2and the carry terminal CR

The third transistor TR5-21includes an input electrode connected to the second voltage input terminal V2, a control electrode connected to the second node NA, and an output electrode. The fourth transistor TR5-22includes an input electrode connected to the output electrode of the third transistor TR5-21, a control electrode connected to the second node NA, and an output electrode connected to the carry terminal CR. A node connected to the output electrode of the third transistor TR4-21and the input electrode of the fourth transistor TR4-22is referred to as a fourth intermediate node NM40.

One of output signals GSk and CRSk may be applied to each of the third intermediate node NM30and the fourth intermediate node NM40. In the present embodiment, the output signal may be a kth carry signal CRSk. As the kth carry signal CRSk is applied to each of the third intermediate node NM30and the fourth intermediate node NM40, leakage current may not occur from the second pull-down unit500-1during the kth horizontal period HPk (seeFIG. 6B). Accordingly, a level of the kth gate signal GSk may be maintained or substantially maintained at a value greater than a reference value.

According to an embodiment of the inventive concept, the first pull-down unit400ofFIG. 9may be replaced with the first pull-down unit400-1shown inFIG. 8.

FIG. 10is a block diagram illustrating a gate driving circuit GDC-1according to an embodiment of the inventive concept.FIG. 11is a circuit diagram of a driving stage SRCk3according to an embodiment of the inventive concept. Hereinafter, the gate driving circuit GDC-1according to the embodiment ofFIG. 10is described with reference toFIGS. 10 and 11. However, detailed descriptions for components that are the same or substantially the same as those described with reference toFIGS. 1 through 7Dare not repeated.

The gate driving circuit GDC-1according the present embodiment includes a plurality of driving stages SRC1to SRCn connected in cascade to each other. The plurality of driving stages SRC1to SRCn are respectively connected to the plurality of gate lines GL1to GLn. The gate driving circuit GDC-1may further include a dummy stage SRC-D connected to a last driving stage SRCn from among the plurality of driving stages SRC1to SRCn. The dummy stage SRC-D may be connected to the dummy gate line GL-D.

Each of the plurality of driving stages SRC1to SRCn includes an output terminal OUT, an input terminal IN, a control terminal CT, a clock terminal CK, a first voltage input terminal V1, and a second voltage input terminal V2. Here, the carry terminal CR is omitted in comparison to the driving stages SRC1to SRCn shown inFIG. 5.

The output terminal OUT of each of the plurality of driving stages SRC1to SRCn is electrically connected to the input terminal IN of the next driving stage of a corresponding driving stage. For example, the input terminal IN of the third driving stage SRC3may receive the gate signal of the second driving stage SRC2that is an immediately previous driving stage. The input terminal IN of the first driving stage SRC1receives the start signal STV.

The control terminal CT of each of the plurality of driving stages SRC1to SRCn is electrically connected to the output terminal OUT of the next driving stage of a corresponding driving stage. The control terminal CT of each of the plurality of driving stages SRC1to SRCn receives the gate signal of the next driving stage of a corresponding driving stage. For example, the control terminal CT of the second driving stage SRC2may receive a gate signal outputted from the output terminal OUT of the third driving stage SRC3that is the immediately next driving stage.

FIG. 11illustrates a kth driving stage SRCk3from among n driving stages SRC1to SRCn shown inFIG. 10. The kth driving stage SRCk3includes an output unit100, a first control unit200, a second control unit300, and a pull-down unit400. In relation to the kth driving stage SRCk3ofFIG. 11, the second pull-down unit500is omitted in comparison to the kth driving stage SRCk shown inFIG. 6A.

Additionally, the second output unit120does not output the kth carry signal CRSk (seeFIG. 6A). The second output unit120outputs a control signal. The second output unit120provides a buffer signal to each of the first intermediate node NM1and the second intermediate node NM2during the kth horizontal period HPk, and provides a switching signal to each of the third and fourth inverter transistors TR3-3and TR3-4.

FIG. 12is a circuit diagram of a driving stage SRCk4according to an embodiment of the inventive concept. According to the embodiment ofFIG. 12, the driving stage SRCk4may include the driving stage SRCk3shown inFIG. 11and the pull-down unit400-1may include a first group of pull-down transistors TR4-11and TR4-12and a second group of pull-down transistors TR4-21and TR4-22as shown in the pull-down unit400-1described with reference toFIG. 8.

As described above, as an output signal is applied to an intermediate node of transistors connected in series between a first node and a discharge voltage input terminal, a voltage of the first node is maintained or substantially maintained at a level greater than a reference value, so that leakage current occurring from transistors connected in series is reduced. Accordingly, the output of an output signal is not delayed.

Furthermore, as an output signal is applied to an intermediate node of transistors connected in series between an output terminal and a discharge voltage input terminal, the output of the output signal may not be delayed, and the output signal may have a high level greater than a reference value.

Although exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments, and that various changes and modifications may be made by one having ordinary skill in the art within the spirit and scope of the present invention as defined in the following claims, and their equivalents.