Semiconductor devices including through vias and methods of fabricating the same

Disclosed are semiconductor devices including through vias and methods of fabricating the same. The methods may include forming a first structure including a metal pattern and a second structure on the first structure. The metal pattern includes an upper surface facing the second structure. The methods may also include etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. After removing the oxidized first etch residue, the upper surface of the metal pattern may include a first portion that includes a recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0062329, filed on May 28, 2019, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present disclosure relates to a semiconductor device including through vias and a method of fabricating the same.

In the electronics industry including devices such as a mobile phone or a laptop computer, there is an increasing demand for electronic devices with light weight, a small form factor, high speed, multifunction, high performance, and high reliability. To meet such a demand, a semiconductor package technology is being researched and developed. In the conventional interconnection technology of two-dimensionally connecting integrated circuits (ICs) using a wire-bonding method, there are several technical disadvantages, such as signal loss in wire, high power consumption, and constraint on design of a device. To overcome these disadvantages, a three-dimensional integrated circuit (3D-IC) package technology of connecting a plurality of stacked semiconductor chips with a vertical interconnection line was proposed. Here, the vertical interconnection line, which is used to vertically connect the semiconductor chips to each other, is called a through via, a through electrode, or a through-silicon-via (TSV). In the TSV-based 3D-IC package technology, it may be possible to place more ICs within a given area and to reduce lengths of wiring lines between circuits. Recently, a variety of research has been conducted to improve reliability and electric characteristics of semiconductor packages that are fabricated using the TSV-based 3D-IC package technology.

SUMMARY

Some embodiments of the inventive concept provide semiconductor devices with improved reliability.

Some embodiments of the inventive concept provide methods of fabricating a semiconductor device with improved reliability.

According to some embodiments of the inventive concept, semiconductor devices may include a first structure including a metal pattern, a second structure on the first structure, and a through via extending through the second structure. The through via may be electrically connected to the metal pattern. The metal pattern includes an upper surface facing the second structure, and the upper surface of the metal pattern includes a recess. The upper surface of the metal pattern includes a first portion that defines the recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.

According to some embodiments of the inventive concept, methods of fabricating a semiconductor device may include forming a first structure including a metal pattern and a second structure on the first structure. The metal pattern includes an upper surface facing the second structure. The methods may also include etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. After removing the oxidized first etch residue, the upper surface of the metal pattern may include a first portion that includes a recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.

According to some embodiments of the inventive concept, methods of fabricating a semiconductor device may include forming a first structure including a metal pattern and a second structure on the first structure, etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. Oxidizing the first etch residue may include forming a metal oxide on the metal pattern. The methods may also include reducing the metal oxide, before or after removing the oxidized first etch residue. Etching the second structure and oxidizing the first etch residue may be performed in-situ in a single process chamber.

According to some embodiments of the inventive concept, methods of fabricating a semiconductor device may include providing a first structure including a metal pattern and a second structure that is on the first structure. The metal pattern may include an upper surface facing the second structure. The methods may also include performing an etch process to form a hole in the second structure. The hole may expose the upper surface of the metal pattern. The methods may further include performing an oxidation process on the first structure and the second structure to oxidize a portion of the metal pattern exposed by the hole, reducing the portion of the metal pattern that is oxidized by performing the oxidation process, and performing a cleaning process on the first structure and the second structure after performing the oxidation process to clean the hole. The etch process and the oxidation process may be performed in-situ, and reducing the portion of the metal pattern may be performed before or after performing the cleaning process.

DETAILED DESCRIPTION

Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

FIGS. 1A to 1Care process flow charts illustrating methods of fabricating a semiconductor device, according to some embodiments of the inventive concept.FIGS. 2A to 2Care sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

Referring toFIGS. 1A and 2A, an upper structure320may be formed on a lower structure300including a copper pattern310. The copper pattern310may be referred to as a metal or conductive pattern. The lower structure300may include an interlayered insulating layer, which extends on (e.g., covers) a semiconductor substrate or interconnection lines formed thereon. The copper pattern310may be electrically connected to at least a portion of the interconnection lines. The upper structure320may include at least one of a passivation layer, an insulating layer, or a semiconductor substrate. The copper pattern310may be located at the uppermost level of the lower structure300. The uppermost level of the lower structure300may be included in a portion that is closest to the upper structure320. It will be understood that “an element A covers an element B” (or similar language) means that the element A is on the element B but does not necessarily mean that the element A covers the element B entirely.

Thereafter, a wafer or substrate, which includes the lower structure300, the copper pattern310, and the upper structure320, may be loaded in an etching chamber. An etching process may be performed to etch the upper structure320, and as a result, a via hole320hmay be formed to expose the copper pattern310(in first step S10). In some embodiments, since a plasma density of an etching gas is high at an upper portion of the via hole320h, the upper portion of the via hole320hmay be formed to be relatively wider than an intermediate portion of the via hole320has illustrated inFIG. 2A. Further, in some embodiments, at a lower portion of the via hole320h, ions of particles constituting an etching gas may recoil from a surface of the copper pattern310and collide with a lower sidewall of the via hole320h. Thus, the lower portion of the via hole320hmay be formed to be relatively wider than the intermediate portion of the via hole320has illustrated inFIG. 2A. Etch residues330may be left on an inner sidewall of the via hole320h. The etch residues330may include, for example, a polymeric material.

Referring toFIGS. 1A and 2B, the etch residues330on the inner sidewall of the via hole320hmay be oxidized (in second step S20). The second step S20may be performed by an oxidation process. The second step S20may be performed in-situ in the etching chamber, after performing the first step S10. During the second step S20, oxygen may be supplied into the etching chamber. The second step S20may be referred to as an ashing process. As a result of the second step S20, the etch residues330may be converted into oxidized etch residues330a. At this time, a top surface of the copper pattern310, which is exposed through a bottom of the via hole320h, may be partially oxidized to form a copper oxide310a. A portion of the copper oxide310amay be formed by eroding an upper portion of the copper pattern310. In some embodiments, the portion of the copper oxide310amay be formed by oxidizing an upper portion of the copper pattern310. If the second step S20is not performed in an in-situ manner, the structure shown inFIG. 2A, in which the copper pattern310is not covered by another layer and thus is exposed, is transferred to another chamber, fabrication facilities may be contaminated by copper. According to some embodiments of the inventive concept, the second step S20may be performed in an in-situ manner, and thus copper contamination may not occur. It will be understood that “two processes/steps being performed in-situ” (or similar language) means that the two processes are performed in a single process chamber or apparatus without transferring an object on which the two processes are performed (e.g., the structure shown inFIG. 2A) to outside of the single process chamber or apparatus.

Referring toFIGS. 1A and 2C, the oxidized etch residues330amay be removed (in third step S30). The third step S30may be performed by a cleaning process. The copper oxide310amay also be removed during the third step S30. As a result of the removal of the copper oxide310a, a recess region R1may be formed in the top surface of the copper pattern310. The third step S30may be performed using, for example, a cleaning agent, which does not etch copper. In some embodiments, the third step S30may be performed using a cleaning agent, in which aqueous ammonia (NH4OH) and sulfuric acid (H2SO4) are not contained. For example, the cleaning agent in the third step S30may include diluted HF (DHF), in which hydrofluoric acid (HF) and water are contained.

Thereafter, a cleaning process may be performed to clean a surface of the copper pattern310exposed through the bottom of the via hole320h. In some embodiments, this cleaning process may be performed using a cleaning solution containing, for example, aqueous ammonia or sulfuric acid. In some embodiments, although not shown, a via plug may be formed in the via hole320h.

In some embodiments, as provided inFIG. 1B, the fabricating methods may further include reducing copper oxide (in fourth step S40) after the third step S30and before the step of forming the via plug. The fourth step S40may be performed when, during the third step S30, the copper oxide310ais incompletely removed and remains. In some embodiments, the fourth step S40may include supplying hydrogen to produce hydrogen plasma and treating (e.g., reducing) the copper oxide310awith the hydrogen plasma. The fourth step S40may be referred to as an “active plasma treatment step” or “hydrogen plasma treatment step”. Due to the fourth step S40, it may be possible to reduce all of the copper oxide310a, which may be left after performing the previous step (e.g., the third step S30), to copper. Thus, the copper oxide310aon the copper pattern310may disappear and be removed.

In some embodiments, as provided inFIGS. 1C and 2B, the fourth step S40may be performed between the second step S20and the third step S30. In other words, the copper oxide310a, which is produced in the step of oxidizing the etch residue on the inner sidewall of the via hole320h(in the second step S20), may be reduced to copper (in the fourth step S40), and then, the oxidized etch residues330amay be removed (in the third step S30). In this case, the recess region R1on the copper pattern310shown inFIG. 2Cmay not be formed.

It may be difficult to remove the etch residues330, which remain on the inner sidewall of the via hole320h, using a copper cleaning agent, and the etch residues330may weaken an adhesion strength between the via plug and a peripheral structure and may cause a failure in electric reliability of semiconductor devices. The fabricating methods according to some embodiments of the inventive concept may make it possible to remove (e.g., completely remove) the etch residues330and to improve electric reliability of semiconductor devices.

Next, some embodiments, in which the inventive concept is applied to a process of forming a through via, will be described.

FIG. 3is a process flow chart illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept.FIGS. 4A to 4Gare sectional views illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. In some embodiments, the method of fabricating the semiconductor device may be sequentially performed as illustrated inFIGS. 4A to 4G.

Referring toFIGS. 3 and 4A, a first structure100may be prepared. The first structure100may include a first semiconductor substrate1, first transistors5disposed on the first semiconductor substrate1, a first interlayered insulating layer10that may have a multi-layered structure and may extend on (e.g., may cover) the first transistors5, a first interconnection line12disposed in the first interlayered insulating layer10, and a first metal pattern14electrically connected to the first interconnection line12. Although a single first interconnection line12is shown inFIG. 4A, multiple first interconnection lines12may be provided in the first interlayered insulating layer10. The first metal pattern14may be disposed at the top portion of the first structure100and may be exposed to the outside. The first metal pattern14may be formed of or include, for example, a precious metal, such as gold or copper. The first metal pattern14may be referred to as a precious metal pattern. In some embodiments, the first metal pattern14may be formed of or include, for example, at least one of aluminum, tungsten, tin, or lead. The first metal pattern14may be positioned at the topmost level of the first interlayered insulating layer10. The first metal pattern14may be positioned in the first interlayered insulating layer10and may be covered with a portion of the first interlayered insulating layer10.

A second structure200may be attached (e.g., bonded) to the first structure100. In some embodiments, the first metal pattern14may be exposed before the second structure200is attached to the first structure100. The second structure200may include a second semiconductor substrate22and a second interlayered insulating layer20. For example, to attach (e.g., bond) the second structure200to the first structure100, a plasma treatment process may be performed on a surface of at least one of the first interlayered insulating layer10and the second interlayered insulating layer20. Thereafter, the second interlayered insulating layer20may be placed on the first interlayered insulating layer10to be in contact with the first interlayered insulating layer10, and then, a thermo-compression process may be performed to attach (e.g., bond) them to each other. In some embodiments, although not shown, a transistor or an interconnection line may be formed on the second semiconductor substrate22.

The second structure200may be etched in an etching chamber to form a via hole26exposing the first metal pattern14(in first step S11). The via hole26may include an upper via hole26u, a lower via hole26b, and an intermediate via hole26mtherebetween. The upper via hole26umay be exposed to a high density of etching plasma, and thus, the upper via hole26umay be formed to be wider than the intermediate via hole26m. The lower via hole26bmay be additionally etched by ions of etching gas particles, which recoil from a surface of the first metal pattern14exposed through the bottom of the via hole26and collide with an inner sidewall of the via hole26, and thus, may be formed to be wider than the intermediate via hole26m. First etch residues330may be produced by the etching process. The first etch residues330may be mainly formed on the inner sidewalls of the upper and lower via holes26uand26b, which are laterally recessed.

Referring toFIGS. 3 and 4B, the first etch residue330on the inner sidewall of the via hole26may be oxidized (in second step S12). The second step S12may be performed by an oxidation process. The second step S12may be performed in-situ in the etching chamber, after performing the first step S11. During the second step S12, oxygen may be supplied into the etching chamber. The second step S12may be referred to as an ashing process. As a result of the second step S12, the first etch residues330may be converted into oxidized first etch residues330a, which are formed by oxidizing the first etch residues330. Here, a top surface of the first metal pattern14, which is exposed through the bottom of the via hole26, may also be partly oxidized to form a first metal oxide14a. In the case where the first metal pattern14includes copper, the first metal oxide14amay be copper oxide. In the second step S12, the surface of the second semiconductor substrate22may also be oxidized to form a first substrate oxide22a.

Referring toFIGS. 3 and 4C, the oxidized first etch residues330amay be removed (in third step S13). The third step S13may be performed by a cleaning process. The first metal oxide14aand the first substrate oxide22amay also be removed during the third step S13. As a result of the removal of the first metal oxide14a, a first recess region R1may be formed in the top surface of the first metal pattern14. In some embodiments, the third step S13may be performed using a cleaning agent, which does not etch copper. In some embodiments, the third step S13may be performed using a cleaning agent, in which aqueous ammonia (NH4OH) and sulfuric acid (H2SO4) are not contained. For example, the cleaning agent in the third step S13may include diluted HF (DHF), in which hydrofluoric acid (HF) and water are contained.

Referring toFIGS. 3 and 4D, a via insulating layer28may be formed on (e.g., formed to cover) the inner sidewall of the via hole26(in fourth step S14). To do this, in some embodiments, the via insulating layer28may be conformally formed on the structure ofFIG. 4C, and then, in an etching chamber, an anisotropic etching process may be performed on the via insulating layer28to form the via insulating layer28extending on only the sidewall of the via hole26. Thus, the top surface of the first metal pattern14may be exposed through the bottom of the via hole26as the via insulating layer28is not provided on a portion of the top surface of the first metal pattern14. In some embodiments, the via insulating layer28may have a uniform thickness along the inner sidewall of the via hole26as illustrated inFIG. 4D. A lower portion of the via insulating layer28may protrude laterally and may cover a portion of the top surface of the first metal pattern14as illustrated inFIG. 4D. As a result of the anisotropic etching process, second etch residues331may be formed on the via insulating layer28that extends on the inner sidewall of the via hole26. The via insulating layer28may be formed of or include at least one of, for example, silicon oxide, silicon nitride, or silicon oxynitride.

Referring toFIGS. 3 and 4E, the second etch residues331on the inner sidewall of the via hole26may be oxidized (in fifth step, S15). The fifth step S15may be performed by an oxidation process. The fifth step S15may be performed in-situ in the etching chamber, after performing the fourth step S14. During the fifth step S15, oxygen may be supplied into the etching chamber. The fifth step S15may be referred to as an ashing process. As a result of the fifth step S15, the second etch residues331may be converted into oxidized second etch residues331a, which are formed by oxidizing the second etch residues331. Here, a top surface of the first metal pattern14, which is exposed through the bottom of the via hole26, may also be partly oxidized to form a second metal oxide14b. In the case where the first metal pattern14includes copper, the second metal oxide14bmay be copper oxide. In the fifth step S15, the surface of the second semiconductor substrate22may also be oxidized to form a second substrate oxide22b.

Referring toFIGS. 3 and 4F, the oxidized second etch residues331amay be removed (in sixth step S16). The sixth step S16may be performed by a cleaning process. The second metal oxide14band the second substrate oxide22bmay also be removed during the sixth step S16. As a result of the removal of the second metal oxide14b, a second recess region R2may be formed in the top surface of the first metal pattern14. The second recess region R2may be deeper than the first recess region R1. In some embodiments, the sixth step S16may be performed using a cleaning agent, which does not etch copper. In some embodiments, the sixth step S16may be performed using a cleaning agent, in which aqueous ammonia (NH4OH) and sulfuric acid (H2SO4) are not contained. For example, the cleaning agent in the sixth step S16may include diluted HF (DHF), in which hydrofluoric acid (HF) and water are contained.

Referring toFIGS. 3 and 4G, the surface of the first metal pattern14may be cleaned (in seventh step S17). This cleaning process may be performed using a cleaning solution containing, for example, aqueous ammonia or sulfuric acid. A diffusion barrier layer30may be conformally formed to extend on (e.g., cover) the side and bottom surfaces of the via hole26, and a conductive layer may be formed to fill the via hole26. A chemical mechanical polishing (CMP) process or an etch-back process may be performed to remove the diffusion barrier layer30and the conductive layer on the second semiconductor substrate22and to remain the diffusion barrier layer30in the via hole26, and as a result, a through via TSV may be formed (in eighth step S18). The through via TSV may be formed of or include, for example, at least one of tungsten, aluminum, or copper. The diffusion barrier layer30may be formed of or include, for example, a metal nitride layer (e.g., a titanium nitride layer, a tantalum nitride layer, or a tungsten nitride layer). Next, a second metal pattern34may be formed to be in contact with the through via TSV, and a passivation layer36may be formed on the second semiconductor substrate22to extend on (e.g., cover) the second metal pattern34. The second metal pattern34may be formed of or include, for example, aluminum or tungsten. The passivation layer36may be formed of or include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride. As a result, a semiconductor device500aaccording to some embodiments of the inventive concept may be formed.

Although not shown, the step of reducing the copper oxide (in S40ofFIG. 1B or 1C) or the active plasma treatment step may be performed between the third and fourth steps S13and S14ofFIG. 3and/or between the second and third steps S12and S13ofFIG. 3to reduce the first metal oxide14a. In some embodiments, the step of reducing the copper oxide (in S40ofFIG. 1B or 1C) or the active plasma treatment step may be performed between the sixth and seventh steps S16and S17ofFIG. 3and/or between the fifth and sixth steps S15and S16ofFIG. 3to reduce the second metal oxide14b. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.

A structure of a semiconductor device, which is fabricated through the afore-described process, will be described in more detail below.FIGS. 5A and 5Bare enlarged sectional views illustrating a portion of a semiconductor device (e.g., a portion ‘P1’ ofFIG. 4G), according to some embodiments of the inventive concept.

Referring toFIGS. 4G and 5A, the semiconductor device500aaccording to some embodiments of the inventive concept may include a first structure100including a first metal pattern14and a second structure200extending on (e.g., covering) the first structure100. InFIG. 4G, the first metal pattern14is illustrated to be a single pattern, but in some embodiments, the first metal pattern14may be composed of a plurality of sub metal patterns spaced apart from each other. In some embodiments, the first metal pattern14may be formed of or include copper. A through via TSV may penetrate the second structure200and may be electrically connected to the first metal pattern14. The top surface of the first metal pattern14may be provided to have a first recess region R1and a second recess region R2. The second recess region R2may be placed at a center region of a bottom of the first recess region R1. The through via TSV may include an intermediate portion32m, a first lower portion32b1placed below the intermediate portion32m, and a second lower portion32b2placed below the first lower portion32b1. The second lower portion32b2may be positioned between the first lower portion32b1and the first metal pattern14. A sidewall of a lower portion of the first lower portion32b1may protrude in a lateral direction toward the second interlayered insulating layer20beyond a sidewall of the second lower portion32b2. A bottom surface of the first lower portion32b1may not be veiled by the second lower portion32b2and may be laterally exposed by the second lower portion32b2. The first lower portion32b1may have a first width W1at a level adjacent to the intermediate portion32mand may have a second width W2at a level adjacent to the second lower portion32b2. The first width W1may be smaller than the second width W2. A lower portion of a via insulating layer28may be interposed between the first metal pattern14and a diffusion barrier layer30.

Referring toFIG. 5B, the first metal pattern14may have a first surface roughness at the bottoms of the first and second recess regions R1and R2and a second surface roughness on a top surface14uof the first metal pattern14, and here, the first surface roughness may be greater than the second surface roughness. The first surface roughness may be higher than the second surface roughness because of at least one of the ashing processes S12and S15and the removal processes S13and S16, which are described with reference toFIG. 3. Except for this difference, the structure ofFIG. 5Bmay be substantially the same as that ofFIG. 5A. In some embodiments, portions of the first metal pattern14that define the first and second recess regions R1and R2may have surfaces that are rougher than the top surface14uof the first metal pattern14contacting the second interlayered insulating layer20as illustrated inFIG. 5B.

The semiconductor device500amay be a part of a semiconductor package. In other words, the first structure100may be a part of a lower semiconductor chip. The second structure200may be a part of an upper semiconductor chip. The semiconductor device500amay be a semiconductor package, in which the lower semiconductor chip and the upper semiconductor chip is connected to each other by the through via TSV. In the semiconductor device500a, the etch residues330and331may be totally removed, and thus, it may be possible to improve an adhesion strength between the through via TSV and a peripheral structure and to improve the reliability of the semiconductor device.

FIG. 6is a sectional view illustrating a semiconductor device according to some embodiments of the inventive concept.

Referring toFIG. 6, a semiconductor device500baccording to some embodiments of the inventive concept may include a second structure200aand a first structure100a, which is disposed on the second structure200a. The second structure200amay include a semiconductor substrate1, a device isolation layer3, a transistor5, and a first interlayered insulating layer10a. The second structure200amay further include a first capping layer24aextending on (e.g., covering) a bottom surface of the semiconductor substrate1.

The first structure100amay include conductive patterns14and12ato12d, second to fourth interlayered insulating layers10bto10d, and an upper passivation layer13. The conductive patterns14and12ato12dmay include a first metal pattern14, a second conductive pattern12a, a third conductive pattern12b, a fourth conductive pattern12c, and a fifth conductive pattern12d. The first metal pattern14and the second conductive pattern12amay be placed at the same height and may be spaced apart from each other. The second conductive pattern12amay be electrically connected to the transistor5.

A conductive pad16may be disposed on the fifth conductive pattern12d. An upper conductive pillar17may be disposed on the conductive pad16. An upper conductive bump18may be disposed on the upper conductive pillar17.

A through via TSV may penetrate the second structure200aand may be in contact with the first metal pattern14. In some embodiments, the through via TSV may have the same or similar shape as that described with reference toFIGS. 4G, 5A, and 5B. The through via TSV may be provided in a via hole26. An inner sidewall of the via hole26may be covered with a via insulating layer28. A diffusion barrier layer30may be interposed between the via insulating layer28and the through via TSV.

A redistribution pattern35may be provided below the first capping layer24a. The redistribution pattern35may be in contact with the through via TSV. The first capping layer24amay be covered with a second capping layer37. A portion of the redistribution pattern35may be in contact with a lower conductive pillar38. The lower conductive pillar38may be provided to penetrate the second capping layer37and may protrude toward the outside. A lower conductive bump39may be provided below the lower conductive pillar38.

The semiconductor device500bofFIG. 6may be formed by the following process. First, a device isolation layer3may be formed in a semiconductor substrate1. Transistors5may be formed on the semiconductor substrate1. A first interlayered insulating layer10amay be formed to extend on (e.g., cover) the semiconductor substrate1. A first metal pattern14and a second conductive pattern12amay be formed on the first interlayered insulating layer10a. A second interlayered insulating layer10b, a third conductive pattern12b, a third interlayered insulating layer10c, a fourth conductive pattern12c, a fourth interlayered insulating layer10d, and a fifth conductive pattern12dmay be sequentially formed on the first metal pattern14and the second conductive pattern12a. An upper passivation layer13may be formed on the fifth conductive pattern12dand may be patterned to expose the fifth conductive pattern12d. A conductive pad16may be formed on the upper passivation layer13to be in contact with the fifth conductive pattern12d. An upper conductive pillar17and an upper conductive bump18may be formed on the conductive pad16.

Thereafter, a first capping layer24amay be formed on a bottom surface of the semiconductor substrate1. The first capping layer24aand the second structure200amay be sequentially and anisotropically etched to form a via hole26exposing the first metal pattern14. Next, a through via TSV may be formed using the method described with reference toFIG. 3. A redistribution pattern35may be formed below the first capping layer24ato be in contact with the through via TSV. A second capping layer37may be formed below the first capping layer24ato cover the redistribution pattern35. Thereafter, a lower conductive pillar38and a lower conductive bump39may be formed.

In fabrication methods of a semiconductor device with a through via according to some embodiments of the inventive concept, an etch residue may be effectively removed, and thus, it may be possible to improve reliability of the fabrication method. In addition, according to some embodiments of the inventive concept, it may be possible to provide a semiconductor device with improved reliability.

The functions/acts of flowchart blocks herein may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Moreover, the functionality of a given block of the flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. Finally, other blocks may be added/inserted between the blocks that are illustrated, and/or blocks/operations may be omitted without departing from the scope of the present inventive concept.

While example embodiments of the inventive concept have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations may be made therein without departing from the scope of the attached claims.