VCO having voltage-to-current converter and PLL using same

The voltage-controlled oscillator in a phase-locked loop comprises a voltage-current converter (62) and a current frequency converter (34). The voltage-current converter (62) comprises a voltage differential-current converter (64), a current-current converter (66) and a current adder-subtracter (68). In the voltage differential-current converter (64), only the voltage fluctuation or difference .DELTA.V.sub.CN with respect to one-half a power supply voltage V.sub.DD /2, and not the absolute value of a control voltage V.sub.CN, undergoes current conversion as a control current I.sub.CN. Therefore, the center frequency of the oscillation frequency is not a factor of control voltage V.sub.CN and is controlled only by an offset voltage V.sub.B2. Accordingly, the center frequency can be independently set by changing offset voltage V.sub.B2. This is particularly significant in zone bit recording, which requires a wide frequency band.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention generally relates to phase-locked loops (PLL) used 
for zone bit recording in hard disk systems, for example, and more 
particularly to improvement of the voltage-controlled oscillator (VCO) 
portion of the phase-locked loop. 
2. Related Technical Art 
Currently, phase-locked loops widely used in magnetic disk devices and 
other types of data separators comprise a first phase-locked loop 
operating in synchronization with a data pulse and a second phase-locked 
loop operating in synchronization with a reference clock, as disclosed in 
Japanese Laid-Open Patent Publication 59-28209, which was configured to be 
locked in at a high speed or quickly regardless of whether the data 
transfer rate changed. This type of phase-locked loop had a configuration 
as shown in FIG. 4. That is, a first phase-locked loop 10 used a phase 
comparator (PC) 12 to compare the phases of a data pulse string S.sub.IN 
and an oscillator output V.sub.1, and outputs a phase difference detection 
signal, a charge pump 14 that provides current to be charged and 
discharged to a loop filter 16, acting as a low-pass filter (LPF), in a 
subsequent stage based on the phase difference detection signal, and a 
voltage-controlled oscillator (VCO1) 18 in which an oscillation frequency 
f.sub.OS1 was controlled by a control voltage V.sub.F1, output by loop 
filter 16. A second phase-locked loop 20 used a phase comparator (PC) 22 
to compare the phases of a reference clock CLK and an oscillator output 
V.sub.2 and output a phase detection signal. A charge pump 24 that 
provides the current to be charged and discharged to the loop filter 26, 
acting as a low-pass filter (LPF), in a subsequent stage based on the 
second phase detection signal, and a voltage-controlled oscillator (VCO2) 
28 in which an oscillation frequency f.sub.OS2 was controlled in responce 
to a control voltage V.sub.F2, output by loop filter 16, were also used. 
The voltage-controlled oscillators 18 and 28 are each circuits with 
characteristic constants equal to each other, and each has a control input 
terminal a and an offset voltage (reference voltage) terminal b. Output 
V.sub.F1 of loop filter 16 and output V.sub.F2 of loop filter 26 of second 
phase-locked loop 20 are impressed on control input terminal a and offset 
voltage (reference voltage) terminal b, respectively, of 
voltage-controlled oscillator 18 of first phase-locked loop 10. An 
intermediate voltage V.sub.DD /2 (DC voltage) of a power source voltage 
V.sub.DD and output V.sub.F2 of loop filter 26 are impressed on control 
input terminal a and offset voltage terminal b, respectively, of 
voltage-controlled oscillator 28 of second phase-locked loop 20. 
Voltage-controlled oscillators 18 and 28 each use, as shown in FIG. 5, a 
voltage-current converter (V/I) 32 and a current frequency converter (I/F) 
34. Voltage-current converter 32 comprises a parallel current path made 
using a MOS transistor Tr.sub.1 which is current-controlled by the voltage 
impressed on control input terminal a and a MOS transistor Tr.sub.2 which 
is current-controlled by the voltage impressed on offset voltage terminal 
b, a load MOS transistor Tr.sub.3 connected in series with this parallel 
current path, an output transistor Tr.sub.4, which acts as a current 
mirror circuit and uses load MOS transistor Tr.sub.3 as its input 
transistor, and a load MOS transistor Tr.sub.5 connected in series to 
transistor Tr.sub.4. Current frequency converter (I/F) 34 is a commonly 
used ring oscillator having three stages of inverters designated here as 
INV.sub.1 -INV.sub.3. 
In only the first phase-locked loop 10, locking occurs when input of a data 
pulse string starts, and a considerable amount of time is required until 
control voltage V.sub.F1, output by loop filter 16, reaches approximately 
V.sub.DD /2, but by adding a reference clock CLK to second phase-locked 
loop 20 in advance to preset it to a locked condition and supplying output 
V.sub.F2 of loop filter 26 to offset voltage terminal b of 
voltage-controlled oscillator 18 in first phase-locked loop 10, first 
phase-locked loop 10 is locked in at high speed regardless of whether the 
data transfer rate changes. 
However, phase-locked loops having the above configuration present the 
following problems. 
(1) If control voltage V.sub.F1, output by loop filter 16 in first 
phase-locked loop 10, is V.sub.DD /2 (locked condition of first 
phase-locked loop 10), the added current (combined current) I of the 
current (control current) I.sub.1 controlled by control voltage V.sub.F1 
and flowing to transistor Tr.sub.1, and the current (offset current) 
I.sub.2 controlled by offset voltage V.sub.F2 and flowing to transistor 
Tr.sub.2 are generated, and a current proportioned to added current I is 
supplied to current frequency converter 34. That is, an oscillation 
frequency f.sub.OS1 of voltage-controlled oscillator 18 is determined by 
the sum of control current I.sub.1 and offset current I.sub.2. Since 
control voltage V.sub.F1 oscillates up and down with one-half the power 
source voltage V.sub.DD as a reference, the center frequency is determined 
by the sum of control current I.sub.1, as determined by V.sub.DD /2, and 
offset current I.sub.2, even when there is no phase difference (locked 
condition). Therefore, the band of the center frequency expands very much 
even when the offset voltage is changed. This is due to the fact that even 
when the offset current is narrowed down in order to lower the center 
frequency, control current I.sub.1, as determined by V.sub.DD /2 in a 
locked condition, is already flowing. 
In zone bit recording in hard disk systems, etc., a data pulse string 
S.sub.IN is generated at data transfer rates of four zones (f.sub.1 =8 
MHz, f.sub.2 =10 MHz, f.sub.3 =12 MHz, f.sub.4 =14 MHz) and the data 
transfer rate is changed by switching among these four rates. Phase-locked 
loops such as that described above cannot be applied to systems requiring 
a wide range of data transfer rates such as this. This is due to the fact 
that the band width of the center frequency is too narrow, and it is not a 
control system that can freely vary the center frequency. Therefore, a 
phase-locked loop that can follow a wide range of data transfer rates for 
a data pulse string has been desired. 
(2) Generally, when the loop filter is a lag-lead filter comprising a 
series circuit made up of a resistance R and a capacitor C, the following 
two equations are extremely important as equations that describe the basic 
characteristics of the phase-locked loop. 
EQU .omega..sub.n =(K.sub.v .multidot.K.sub.c /C).sup.1/2 ( 1) 
EQU .xi.=CR.omega..sub.n /2 (2) 
where, .omega..sub.n is the natural frequency (characteristic frequency), 
.xi. is the damping coefficient (damping factor), K.sub.v is a voltage 
frequency conversion coefficient of the voltage-controlled oscillator, and 
K.sub.c is a conversion coefficient including the phase comparator and the 
charge pump. When a phase-locked loop is applied to a data separator 
circuit of a magnetic storage device, etc., it is necessary to change the 
natural frequency .omega..sub.n in proportion to the data transfer rate 
when the data transfer rate changes. The damping coefficient .xi., on the 
other hand, must remain a fixed value regardless of the data transfer 
rate. This is important from the standpoint of the phase step response and 
peak shift margin characteristic of the phase-locked loop. Therefore, when 
the data transfer rate is low (when the center frequency is low), the 
voltage frequency conversion coefficient K.sub.v of the voltage-controlled 
oscillator 18 must be lowered, and when the data transfer rate is high 
(when the center frequency is high), the voltage frequency conversion 
coefficient K.sub.v must be raised. However, in the voltage-controlled 
oscillators 18 and 28 of the above phase-locked loop, the voltage 
frequency conversion coefficient K.sub.v is fixed due to the physical 
dimensional ratio of transistor Tr.sub.1 for the control current and 
transistor Tr.sub.2 for the offset current, and, therefore, the voltage 
frequency conversion coefficient K.sub.v cannot be linked to the data 
transfer rate. 
(3) Since the above phase-locked loop is locked into high speed when input 
of the data pulse string starts, a configuration is employed that adds a 
second phase-locked loop 20, whereby, if control input voltage V.sub.F1 of 
voltage-controlled oscillator 18 of first phase-locked loop 10 is equal to 
control input voltage V.sub.DD /2 of voltage-controlled oscillator 28 of 
second phase-locked loop 20, the oscillation frequencies become equal to 
each other. 
In zone bit recording, the frequency of the reference clock CLK input to 
phase comparator 22 of second phase-locked loop 20 must be changed 
according to the corresponding data transfer rate, in which case, the 
oscillation frequency of voltage-controlled oscillator 28 is synchronized 
to the frequency of reference clock CLK, and output voltage V.sub.F2 of 
loop filter 26, i.e., value of the offset input voltage of 
voltage-controlled oscillator 18, becomes different from previous zones. 
However, as shown in FIG. 6, offset input voltage V.sub.F2 has a waveform 
that superposes an AC voltage component (pulse) V.sub.C corresponding to 
the charge-discharge period on the DC voltage component V.sub.D 
corresponding to an integrating action of the loop filter, and, therefore, 
DC voltage component V.sub.D cannot be freely changed without restriction 
over the entire range (0-V.sub.DD) of the power source voltage. This is 
because since AC voltage component (pulse) V.sub.C generated by the 
charging and discharging of charge pump 24 corresponds to the phase 
difference detection signal, when DC voltage component V.sub.D approaches 
V.sub.DD or V.sub.SS (ground potential), which are far removed from 
V.sub.DD /2, the AC voltage component (pulse) V.sub.C is clipped at a top 
or bottom limit and the control information for phase locking is 
corrupted. Therefore, the area of change for DC component V.sub.D of the 
output of loop filter 26 is limited to a neighborhood range extending 
above and below the reference V.sub.DD /2, and for this reason it is 
impossible to accommodate a wide range of data transfer rates. 
Furthermore, the output of loop filter 26 is not only used to accommodate 
differing data transfer rates, it is also supplied to offset input b of 
voltage-controlled oscillator 18 to compensate for fluctuations in the 
power source voltage and the ambient temperature, and to automatically 
correct for error factors such as production deviations. Therefore, it is 
necessary to allow for a margin in the variable range to automatically 
correct the output of loop filter 26, but since the variable range of DC 
voltage component V.sub.D is limited to the neighborhood of V.sub.DD /2, 
temperature compensation and correction of errors due to production 
deviations, etc., are not sufficient. 
In view of these problems, the invention is intended to offer a 
voltage-controlled oscillator and phase-locked loop capable of locking the 
oscillation frequency by changing the reference clock to accommodate large 
changes in the data transfer rate. 
SUMMARY OF THE INVENTION 
The invention comprises a voltage-current conversion element that generates 
an output current corresponding to the level of the input voltage and a 
current frequency conversion element that generates an oscillation 
frequency output corresponding to the level of the converted current, 
wherein the voltage-current conversion element comprises a voltage 
differential-current conversion element that uses the input voltage as a 
first input voltage and converts it to a current corresponding to the 
voltage difference between the input voltage and a reference voltage, and 
a current adder-subtracter element that generates a second current 
corresponding to a second input voltage and generates the converted 
current by adding or subtracting the first current based on the current 
generated by the voltage differential-current conversion element and the 
second current. Using this configuration, since a current corresponding to 
fluctuations in the first input voltage is generated, the center frequency 
does not become a factor of the first input voltage and is controlled only 
by the second input voltage. Therefore, the center frequency can be set 
independently by changing the second input voltage. This is particularly 
significant in zone bit recording, which requires a wide frequency band. 
Further, the circuit voltage-frequency characteristics can be made linear, 
thus making it easy to match design levels and actual operating levels. 
Though it depends on the circuit design of the voltage-current conversion 
element, instead of disposing the current frequency conversion element 
directly in series with the voltage differential-current conversion 
element, a current-current conversion element that generates a first 
current proportional to the current generated by the voltage 
differential-current conversion element may be disposed between the 
voltage differential-current conversion element and the current frequency 
conversion element. 
In addition to the above configurations, a configuration may be employed 
that provides an integrating element which compares the first input 
voltage with the reference voltage, integrates the difference, and that 
supplies the output of the integrating element as the second input 
voltage. In this case, the second input voltage does not saturate, and, 
therefore, a phase-locked loop can be realized capable of following a wide 
frequency range. 
The above voltage-controlled oscillator is suitable for application as a 
voltage-controlled oscillator in a phase-locked loop having a first 
phase-locked loop operating in synchronization with the data pulse string 
and a second phase-locked loop operating in synchronization with the 
reference clock. In this case, it is desirable to provide an integrating 
element in the second phase-locked loop that compares the first input 
voltage with the reference voltage and integrates the difference.

PREFERRED EMBODIMENTS FOR IMPLEMENTING THE INVENTION 
Embodiments of the invention are explained below based on the attached 
figures. 
First Embodiment 
FIG. 1 is a circuit diagram showing a phase-locked loop constructed and 
operating according to a first embodiment of the invention. This 
phase-locked loop comprises, as in the prior art, a first phase-locked 
loop 40 operating in synchronization with a data pulse string S.sub.IN and 
a second phase-locked loop 50 operating in synchronization with a 
reference clock CLK. 
The first phase-locked loop 40 uses a phase comparator (PC) 12, which 
compares the phases of data pulse string S.sub.IN and an oscillation 
output V.sub.1 and outputs a phase difference detection signal, a charge 
pump 14, to provide current to be charged and discharged to a loop filter 
(LPF) 16, acting as a low-pass filter, in the next stage based on the 
detection signal, loop filter 16 being formed by a capacitor C and a 
switch SW.sub.1, for switching between serial connections of resistances 
R.sub.1 and R.sub.2 to capacitor C based on a zone switching signal Z. A 
voltage-follower buffer 42 receives the output voltage of loop filter 16 
as input and outputs a voltage equal to it, and a voltage-controlled 
oscillator (VCO1) 60, which is controlled by the oscillation frequency 
f.sub.OS1 based on a control voltage V.sub.B1 output from buffer 42 are 
also used. 
The second phase-locked loop 50 comprises a phase comparator (PC) 22, which 
compares the phases of the reference clock CLK and an oscillation output 
V.sub.2 and outputs a phase difference detection signal, a charge pump 24, 
which provides the current to be charged and discharged to loop filter 
(LPF) 26, acting as a low-pass filter, in the next stage based on the 
detection signal, the commonly used loop filter 26 (LPF), being a series 
circuit being formed by a capacitor and resistance, a voltage-follower 
buffer 52, which receives the output voltage of loop filter 26 as an input 
and outputs a voltage equal to it, and a voltage-controlled oscillator 
(VCO2) 70, which is controlled by oscillation frequency f.sub.OS1 based on 
an intermediate voltage 1/V.sub.DD of the power source voltage V.sub.DD. 
Voltage-controlled oscillators 60 and 70 are circuits with characteristic 
constants equal to each other, and each has a control input terminal a and 
an offset voltage (reference voltage) terminal b. A buffer output V.sub.B1 
is impressed on control input terminal a and a buffer output V.sub.B2 in 
second phase-locked loop 50 is impressed on offset voltage (reference 
voltage) terminal b of voltage-controlled oscillator 60 in first 
phase-locked loop 40. The intermediate voltage V.sub.DD /2 (DC voltage) of 
power source voltage V.sub.DD is impressed on control input terminal a and 
buffer output V.sub.B2 is impressed on offset voltage terminal b of 
voltage-controlled oscillator 70 of second phase-locked loop 50. Buffer 52 
in second locked loop 50 can be omitted because the input of 
voltage-controlled oscillator 70 receiving loop filter 26 output is high 
impedance. 
This phase-locked loop differs from the prior art in the configuration of 
voltage-controlled oscillators 60 and 70. Voltage-controlled oscillators 
60 and 70 have a similar configuration except for resistances r.sub.1 and 
r.sub.2 and a switch SW.sub.2. The configuration of only 
voltage-controlled oscillator 60 is explained here by referring to FIG. 2. 
Voltage-controlled oscillator 60 comprises a voltage-current converter 
(V/I) 62 and a current frequency converter (I/F) 34. Current frequency 
converter 34 is a commonly used ring oscillator, as in the prior art, and 
as described below, has three inverted stages here designated INV.sub.1 
-INV.sub.3. 
Voltage-current converter 62 comprises a voltage differential-current 
converter 64, a current-current converter 66 and a current 
adder-subtracter 68. Voltage differential-current converter 64 provides a 
current proportional to the voltage difference between buffer output 
voltage V.sub.B1 and one-half the voltage of power source voltage 
V.sub.DD. Converte 64 comprises an operational amplifier (OP) having a 
noninverting input terminal that receives buffer output voltage V.sub.B1 
via resistance r (switched resistance r.sub.1 or r.sub.2) and an inverting 
input terminal connected to and receiving a direct current that is 
one-half (compared voltage) power source voltage V.sub.DD, and an 
inverting circuit 64a that receives the output of operational amplifier OP 
as an input and feeds its output back to the noninverting input terminal 
of the operational amplifier OP. Inverting circuit 64a comprises a CMOS 
inverted INV, a load MOS transistor F.sub.2 for a p-type MOS transistor 
F.sub.1 of the CMOS inverted INV, and a load MOS transistor F.sub.4 for an 
n-type MOS transistor F.sub.3 of the CMOS inverted INV. Current-current 
converter 66 receives converted current from voltage differential-current 
converter 64, and is a series circuit comprising a p-type MOS transistor 
F.sub.5 dimensionally similar to the load MOS transistor F.sub.2 and forms 
a current mirror, and an n-type MOS transistor F.sub.6 dimensionally 
similar to the load MOS transistor F.sub.4 and also forming a current 
mirror. Current adder-subtracter 68 is disposed between an output point P 
of current-current converter 66 and the power source voltage (ground 
potential), and is a series circuit comprising an offset control 
transistor F.sub.7 current-controlled by offset voltage V.sub.B2 impressed 
on offset control terminal b and a load MOS transistor F.sub.8 disposed 
between output point P and the power source voltage (V.sub.DD potential). 
Current frequency converter 34 comprises a transistor Tr.sub.4 which 
constitutes a current mirror with transistor F.sub.8 of current 
adder-subtracter 68, a load MOS transistor Tr.sub.5 connected in series 
with transistor Tr.sub.4, a ring oscillator 34a having three inverters 
INV.sub.1 -INV.sub.3 connected in a ring, a set of transistors Tr.sub.6 
-Tr.sub.8 which constitute a parallel current mirror together with 
transistor F.sub.8 and supply the prescribed charging current to each of 
the inverters INV.sub.1 -INV.sub.3, and a set of transistors Tr.sub.9 
-Tr.sub.11 which constitute a current mirror with transistor F.sub.8 and 
transfer the prescribed discharging current from each of the inverters 
INV.sub.1 -INV.sub.3. 
In a phase-locked loop having the above configuration, a buffer output 
voltage V.sub.CN equal to output voltage V.sub.B1 of loop filter 16 is 
supplied to control terminal a, but since the output of inverting circuit 
64 in the next stage is fed back to the noninverting input terminal of 
operational amplifier OP, the operational amplifier constitutes a 
negative-feedback circuit. Therefore, operational amplifier OP operates to 
make the noninverted input voltage of operational amplifier OP equal to 
the inverted input voltage (V.sub.DD /2) by means of an imaginary short 
circuit. Here, assuming the control current flowing through resistance r 
is I.sub.CN, then: 
EQU I.sub.CN =(V.sub.CN -V.sub.DD /2)/r (1) 
Since the control voltage V.sub.CN fluctuates between positive and negative 
based on V.sub.DD /2 as a reference, then V.sub.CN can be expressed as: 
EQU V.sub.CN =V.sub.DD /2.+-..vertline..DELTA.V.sub.CN .vertline.(2) 
where, .DELTA.V.sub.CN is the voltage fluctuation. When equation (2) is 
substituted into equation (1), then: 
EQU I.sub.CN =.+-..vertline..DELTA.V.sub.CN .vertline./r (3) 
That is, only the amount of fluctuation or difference .DELTA.V.sub.CN with 
respect to V.sub.DD /2, not the absolute value of the control voltage 
V.sub.CN, undergoes current conversion as control current I.sub.CN in 
voltage differential-current converter 64. Since the input impedance of 
operational amplifier OP is extremely high, control current I.sub.CN 
returns to the power supply via a feedback loop and inverting circuit 64a. 
When control voltage V.sub.CN is greater than V.sub.DD /2 by 
.DELTA.V.sub.CN, the current flowing to n-type MOS transistor F.sub.3 in 
inverting circuit 64a increases, and control current I.sub.CN flows from 
control terminal a to ground via input resistor r, the feedback loop, and 
transistor F.sub.3. In this case, the mirror current flows to transistor 
F.sub.6. When control voltage V.sub.CN is less than V.sub.DD /2 by 
.DELTA.V.sub.CN, the current flowing to p-type MOS transistor F.sub.1 in 
inverting circuit 64a increases, and control current I.sub.CN flows from 
the power source voltage V.sub.DD to control terminal a via transistor 
F.sub.1, the feedback loop, and input resistor r. In this case, the mirror 
current flows to transistor F.sub.5. Here, assuming the current strength 
(dimension) of transistors F.sub.5 and F.sub.6 is k times that of 
transistors F.sub.2 and F.sub.4, an output current I.sub.CNT flowing to 
output point P in current-current converter 66 is expressed by the 
relationship: 
EQU I.sub.CNT =k.multidot.I.sub.CN =.+-.k.vertline..DELTA.V.sub.CN 
.vertline./r(4) 
where, k is the current-current conversion coefficient. 
Converted current I.sub.CNT is input to current adder-subtracter 68 in the 
next stage. When phase locking occurs and converted current I.sub.CNT is 
zero (when control voltage V.sub.CN =V.sub.DD /2), current addition from 
current-current converter 66 to offset control transistor F.sub.7 or 
current withdrawal from load MOS transistor F.sub.8 toward current-current 
converter 66 does not occur, and, therefore, the current flowing to load 
MOS transistor F.sub.8 and the current flowing to offset control 
transistor F.sub.7 are equal to each other. The level of this current is 
determined by the level of offset voltage V.sub.B2. That is, the 
intermediate frequency of oscillation output V.sub.1 is determined by the 
level of offset voltage V.sub.B2. 
Next, when a phase difference occurs in the phase-locked loop, a control 
current I.sub.CN like that described above is generated. In this case, the 
current flowing to load MOS transistor F.sub.8 fluctuates between positive 
and negative by the amount of current I.sub.CNT, which is proportional to 
control current I.sub.CN, using current I.sub.OF, which flows to offset 
control transistor F.sub.7, as a reference. That is, when the control 
voltage is greater than V.sub.DD /2 by a factor of .DELTA.V.sub.CN, a 
current level .vertline.I.sub.CNT .vertline. is withdrawn toward 
current-current converter 66, thus causing a current I flowing to load MOS 
transistor F.sub.8 to increase by the amount of current level 
.vertline.I.sub.CNT .vertline.. When the control voltage is less than 
V.sub.DD /2 by a factor of .DELTA.V.sub.CNo, however, current level 
.vertline.I.sub.CNT .vertline. is supplied toward current-current 
converter 66, thus causing current I flowing to load MOS transistor 
F.sub.8 to decrease by the amount of current level .vertline.I.sub.CNT 
.vertline.. Here, assuming the offset current flowing to offset control 
transistor F.sub.7 is I.sub.OF, then the converted current I is given by 
the relationship: 
EQU I=I.sub.OF .+-.k.vertline..DELTA.V.sub.CN .vertline./r (5) 
Of the converted currents, offset current I.sub.OF is determined by offset 
voltage V.sub.B2 and the fluctuation current is determined by fluctuation 
.DELTA.V.sub.CN of control voltage V.sub.CN. 
Transistor Tr.sub.4 of current frequency converter 34 constitutes a current 
mirror with load MOS transistor F.sub.8, and a mirror current I.sub.M is 
proportional to current I. The proportional constant is determined by the 
dimensional ratio of load MOS transistor F.sub.8 and transistor Tr.sub.4. 
Current frequency converter 34 is configured based on a commonly used ring 
oscillator, and, therefore, the oscillation frequency is proportional to 
mirror current I.sub.M. Assuming "m" is the proportional constant and "f" 
is the oscillation frequency, then according to equation (5), the 
oscillation frequency f is expressed as: 
EQU f=n.multidot.m(I.sub.OF .+-.k.vertline..DELTA.V.sub.CN .vertline./r)(6) 
where, n is the current frequency proportional constant. 
As can be seen from equation (6), since the dimensional shape of each 
transistor is fixed, offset current I.sub.OF (offset voltage V.sub.B2) 
need only be changed when changing the center frequency (f.sub.0 
=n.m.I.sub.OF) even if k and m remain constant. Further, using the center 
frequency as a reference, the frequency is changed between positive and 
negative by the amount of fluctuation .DELTA.V.sub.CN of control voltage 
V.sub.CN and not the control voltage V.sub.CN itself. Therefore, the 
voltage frequency conversion coefficient K.sub.V for the amount of 
fluctuation .DELTA.V.sub.CN of control voltage V.sub.CN is expressed by 
the relationship: 
EQU K.sub.V =n.multidot.mk/r (7) 
Only input resistance r need be changed when changing voltage frequency 
conversion coefficient K.sub.V. In this embodiment, switched resistors 
r.sub.1 and r.sub.2 were provided for data transfer rates for two zones. 
However, r.sub.1 is less than r.sub.2. It is necessary to make the natural 
frequency .omega..sub.n large when the data transfer rate increases, but 
as can be seen from equation (1), only voltage frequency conversion 
coefficient K.sub.V need be made larger in this case, and therefore, as 
can be seen from equation (7), switch SW.sub.2 is changed from the 
resistance r.sub.2 side to the resistance r.sub.1 side by zone switching 
signal Z in order to lower the value of resistance r. Further, should the 
data transfer rate change, the value of resistance R in loop filter 16 is 
adjusted since it is necessary to maintain damping coefficient .xi. 
constant. That is, when the data transfer rate increases, as can be seen 
from equation (2), the value of resistance R is dropped. Here, assuming 
that R.sub.1 is less than R.sub.2, then switch SW.sub.1 is changed from 
the resistance R.sub.2 side to the resistance R.sub.1 side by zone 
switching signal Z. 
As is made clear in equation (7), when resistance r is fixed, voltage 
frequency conversion coefficient K.sub.V is constant. This means that the 
voltage-frequency characteristic is linear. In voltage-controlled 
oscillators of the prior art, however, the voltage-current converter had a 
nonlinear characteristic (square-law curve), and the voltage frequency 
conversion characteristic would fluctuate when the offset voltage was 
changed to accommodate production deviations. Therefore, errors often 
occurred between design and operating values and the actual shift in 
phase-locking characteristics was large. However, since voltage frequency 
conversion characteristic K.sub.V is fixed in the above embodiment, the 
actual shift can be made small. 
In systems in which data pulse strings S.sub.IN are generated at data 
transfer rates in three zones, four zones, or more, it is only necessary 
that the number of resistances in loop filter 16 and the number of input 
resistances in operational amplifier OP be made to conform to the 
different data transfer rates. Loop filter 16 (FIG. 1) in this embodiment 
requires resistances, but as shown in FIG. 6 of Japanese Laid-Open Patent 
Publication 3-68115, it can be configured with only switches and 
capacitors, or an active element having an equivalent electrical function 
can be employed. 
In voltage-current converter 62 of the above voltage-controlled oscillator 
60, conversion current I.sub.CN corresponding to fluctuation 
.DELTA.V.sub.CN in control voltage V.sub.CN is generated, and control 
voltage V.sub.CN is not a function of center frequency f.sub.0 and is only 
controlled by offset voltage V.sub.B2. Therefore, center frequency f.sub.0 
can be set independently by changing offset voltage V.sub.B2. This is 
particularly significant in zone bit recording requiring a wide frequency 
band. 
Furthermore, it is necessary to link the value of voltage frequency 
conversion coefficient K.sub.V to changes in the data transfer rate, but 
multiple external resistances r.sub.1 and r.sub.2 are provided as the 
switching means for this value, and resistances r.sub.1 and r.sub.2 are 
selected based on the zone switching signal Z. Therefore, it is also 
possible to independently set the voltage frequency conversion coefficient 
K.sub.V. 
It is also necessary to maintain damping coefficient .xi. at the phase step 
response or peak shift margin characteristic point even when the data 
transfer rate changes, but since a means is provided for variably 
controlling the time constant of loop filter 16 based on zone switching 
signal Z, the phase-locking characteristic is not adversely affected. 
The phase-locked loop of the above embodiment was configured with a CMOS 
integrated circuit, but bipolar transistors or other active elements can 
also be employed. The current frequency converter was configured with a 
commonly used ring oscillator, but other circuit configurations may also 
be employed. 
Second Embodiment 
FIG. 3 is a circuit diagram showing a phase-locked loop for a second 
embodiment of the invention. In this figure, the same parts as illustrated 
in FIG. 1 are designated by the same numbers and their explanation is 
omitted here. Differences in phase-locked loop 50 from the first 
embodiment include the addition of an integrating circuit 80 that 
integrates the output V.sub.B2 of buffer 52 in second phase-locked loop 
50, a polarity converter 82 that changes the polarity of the integrated 
output, and supplying the output of polarity converter 82 to the gates of 
offset control transistors F.sub.7 in the current adders 68 of the first 
and second phase-locked loops 40 and 50. 
Integrating circuit 80 comprises an operational amplifier OP.sub.0 having a 
noninverting input terminal connected to the reference voltage (V.sub.DD 
/2), an input resistance R.sub.0 that introduces the output of buffer 52 
to the inverting input terminal of operational amplifier OP.sub.0, and a 
feedback capacitor C.sub.0 disposed between the inverting input terminal 
and the output terminal of the operational amplifier OP.sub.0. Polarity 
converter 82 is formed as a series circuit comprising a p-type MOS 
transistor F.sub.9 and an n-type MOS transistor F.sub.10, and with the 
gate and drain of the transistor F.sub.10 connected together. 
In considering the polarity converting action of polarity converter 82, 
offset voltage V.sub.OF based on the output of integrating circuit 80, 
which receives output voltage V.sub.B2 of buffer 52 as an input voltage, 
is proportional to the integrated value of the voltage difference between 
input voltage V.sub.B2 and reference voltage V.sub.DD /2, using reference 
voltage V.sub.DD /2 as a baseline. The proportional constant is given by 
the ratio 1/C.sub.0 R.sub.0. When output voltage V.sub.B2 of buffer 52 is 
larger than reference voltage V.sub.DD /2, a value obtained by adding the 
integrated value (average value) of the voltage difference to V.sub.DD /2 
becomes the offset voltage, and, therefore, the current that flows to 
offset transistor F.sub.7 is controlled so that it also becomes large. 
Further, when output voltage V.sub.B2 of buffer 52 is smaller than 
reference voltage V.sub.DD /2, a value obtained by subtracting the 
integrated value (average value) of the voltage difference from V.sub.DD 
/2 becomes the offset voltage, and, therefore, the current that flows to 
offset transistor F.sub.7 is controlled so that it also becomes small. As 
in the first embodiment, current I flowing to transistor F.sub.8 is the 
sum of offset current I.sub.OF flowing to transistor F.sub.7 and the 
converted current .+-.k.vertline..DELTA.V.sub.CN .vertline./r flowing to 
output point P. Current frequency converter 34 also oscillates at a 
frequency proportional to current I. When the average level of output 
voltage V.sub.B2 of buffer 52 is larger than reference voltage V.sub.DD 
/2, i.e., when the phase of oscillation frequency f.sub.OS2 is delayed 
behind the phase of reference clock CLK, the offset current of transistor 
F.sub.7 becomes large, and as a result, the phase of the output of current 
frequency converter 34 is controlled so that it advances, thus, causing 
the average level of output voltage V.sub.B2 to become smaller. When the 
average level of output voltage V.sub.B2 of buffer 52 is smaller than 
reference voltage V.sub.DD /2, i.e., when the phase of oscillation 
frequency f.sub.OS2 is advanced past the phase of reference clock CLK, the 
offset current of transistor F.sub.7 becomes small, and, as a result, the 
phase of the output of current frequency converter 34 is controlled so 
that it is delayed, thus, causing the average level of output voltage 
V.sub.B2 to become larger. In this manner, the average level of output 
voltage V.sub.B2 of buffer 52 is continually controlled so that it equals 
reference voltage V.sub.DD /2. Therefore, since the output of the loop 
filter having an AC component is not saturated and the offset voltage 
impressed on offset terminal b can be varied linearly, a phase-locked loop 
capable of following a wide frequency range is realized. Accordingly, this 
is significant in application to phase-locked loops of hard disk devices 
that utilize a wide range of data transfer rates.