Single-stage switched AC/DC converters are provided with a PFC (power factor correction) lead enhanced by inclusion of a saturable reactor and/or by connecting the PFC lead to an intermediate tap in a primary winding of the customary isolation transformer located in the DC/DC conversion part of the converter. An important resulting improvement is reduction in the voltage stress on the energy-storage (or "bulk") capacitor. Included are various circuit arrangements of resetting the saturable inductor, for designer or user selection.

TECHNICAL FIELD 
This invention relates to AC/DC power conversion, and concerns improved 
power factor correction (PFC) in single-stage converters. 
BACKGROUND OF THE INVENTION 
Development of soft-switching power supplies began strongly in the decade 
of the 1980's and has continued meanwhile. Single-stage consolidation 
including PFC correction began mainly in the 1990's. Many resulting 
designs have appeared in patents, and others have been made the subject of 
publication in technical journals. Yet significant trade-offs are inherent 
in known designs, such as voltage stress upon the customary energy storage 
("bulk") capacitor as power factor approaches the desired value of unity. 
Such a trade-off is a common problem in such designs, including my own 
contributions, as well as those of other contributors to this art. 
Representative examples appear in consolidated or single-stage AC/DC 
converters patented by such noted designers as the following: 
Fraidlin, Slack, and Wadlington in U.S. Pat. No. 5,115,182 (1992) for 
Single Conversion Power Factor Correction using SEPIC Converter, providing 
a design with unity power factor but with low-frequency ripple in the 
output and with slow transient response; and 
Teramoto, Sekine, and Saito in U.S. Pat. No. 5,301,095 (1994), for High 
Power Factor AC/DC Converter, a PFC corrective design with a sole 
high-frequency capacitor but wherein the primary diode undergoes hard 
switching unsuited to high-frequency operation, and with input and load 
ranges narrow without extensive frequency modulation; and 
Tsai, Poon, Ho, and Lee in U.S. Pat. No. 5,652,700 (1997), for Low Cost 
AC-to-DC converter Having Input Current with Reduced Harmonics, a 
single-stage PFC AC/DC converter with multiple primary windings on an 
isolation transformer (a primary in the rectified positive lead) in the 
converters in the first dozen drawing sheets--but not in the featured 
final (13th) sheet or in any of the claimed circuitry; their energy 
storage or "bulk" capacitor is so voltage-stressed that a 450 V AC rating 
is needed for a universal (90 to 264 VAC) input range to obtain even an 
0.8 power factor, and subject to a pulsating input current, with high 
switching AC ripple requiring optimal EMI filtration, and its primary 
diode undergoing hard switching; and 
Brkovic & Cuk, in U.S. Pat. No. 5,642,267 (1997), for Single-Stage, Unity 
Power Factor Switching Converter with Voltage Bidirectional Switch and 
Fast Output Regulation, a single-stage PFC AC/DC Cuk converter with a 
saturable inductor ("magnetic amplifier") as a bidirectional switch to 
improve the input current waveform, although capable of providing perfect 
power factor, having its input current operating in deep discontinuous 
mode, requiring a large EMI filter, with low efficiency owing to high 
switch-current stress, plus a costly and complicated controller including 
multipliers and dividers; the bulk capacitor voltage stress, although 
tightly regulated over the entire line and load range, has to be 
significantly greater than the maximum peak rectified line voltage (above 
450 V for universal input). 
Notable examples of contributions to technical (but not patent) literature 
in this general field have included the following: 
Madigan, Erickson, and Ismail, Integrated High Quality 
Rectifier-Regulators, PESC '92 Record, about BIBRED (and BIFRED) designs 
having very good power factor and regulation but relatively poor 
efficiency and excessive voltage stress on the bulk capacitor; 
Redl, Balogh, and Sokal, A New Family of Single-Stage Power-Factor 
Correctors with Fast Regulation of the Output Voltage, PESC '94 Record, 
teaching power factor correction with a sole inductor, but imposing high 
switching stresses because of deep discontinuous conduction operating mode 
and requiring a large EMI filter; and 
Huber and Jovanovic, Single-Stage, Single-Switch Isolated Power Supply 
Technique with Input-Current Shaping and Fast Output-Voltage Regulation 
for Universal Input-Voltage-Range Operations, IEEE APEC 1997 Proceedings, 
describing a converter reasonably capable of 0.9 power factor with a 450 V 
capacitor but necessitating a complicated power transformer with at least 
three primary windings, depending heavily upon leakage inductance, very 
resistant to adequate control. 
A U.S. patent to issue (in 1998) upon my application Ser. No. 08/657,615 
for Consolidated Soft-Switching AC/DC Converters discloses a family of 
converters able to provide good power factor, good efficiency, and also 
continuous input current while maintaining reasonably low energy-storage 
capacitor voltage stress, but also subject to such a trade-off between 
bulk capacitor voltage stress and power factor, whereby the higher the 
power factor, the greater the voltage stress. 
Accordingly, my present effort is to improve further upon the design of 
single-stage AC/DC converters, especially in that regard. 
SUMMARY OF THE INVENTION 
A primary object of the present invention is to limit the voltage stress 
imposed upon the customary bulk capacitor of single-stage AC/DC converters 
while also attaining good power factor correction; 
Another object of this invention is to use a saturable reactor to limit the 
voltage stress upon the bulk capacitor of a converter; 
A further object is to enable a choice of several ways to reset such a 
saturable reactor subjected to high-frequency switching; 
Yet another object of this invention is to provide a family of circuit 
designs by which the foregoing objectives are attained; and 
A still further object of the invention is to accomplish the various 
objects both economically as well as effectively. 
In general, the objects of this invention are attained by means of improved 
content of PFC leads and accompanying circuitry in such switched AC/DC 
converters, by connecting such PFC lead to a tap on a primary winding of 
the isolation transformer of a component DC/DC converter, and by including 
in the PFC lead a saturable inductor and coupling it to a pre-existing 
inductor as on a ferromagnetic core, or by including a so-called 
"mag-amp"--wherein a saturable inductor and its control winding are 
prewound on a common ferromagnetic core. 
More particularly, such circuitry, operating in accordance with the methods 
of this invention, safeguards the bulk capacitor from excessive peak 
voltage. Several circuitry arrangements are described for resetting a 
saturable inductor, whether by coupling it with a pre-existing inductive 
winding, or utilizing a mag-amp combination. A couple types of component 
DC/DC converters are illustrated also. 
Other objects of this invention, together with methods and means for 
attaining the various objects, will become apparent from the following 
description and the accompanying diagrams of more than one embodiment, 
presented by way of example rather than limitation. 
Saturable inductors or Mag-Amps are known as useful in the DC output 
circuitry of various converters, shown by (U.S.) patentees: 
Jitaru, in U.S. Pat. No. 5,126,931 (1992) for Fixed Frequency Single Ended 
Converter Switching at Zero Voltage; Farrington, Jovanovich, and Lee in 
U.S. Pat. No. 5,325,283 (1994) for Novel Zero-Voltage-Switching Family of 
Isolated Converters; and also Vinciarelli, in U.S. Pat. No. 5,432,431 
(1995) for Boost Switching Power Conversion Using Saturable Inductors. 
The present inventor also has participated as co-inventor with Fred C. Lee 
in such output-oriented use of a saturable inductor, in U.S. Pat. No. 
5,262,930 (1993) for Zero-Voltage Transition PWM Converters; U.S. Pat. No. 
5,418,704 (1995) for Zero-Voltage-Transition Pulse-Width-Modulated 
Converters; and U.S. Pat. No. 5,442,540 (1995) for Soft-Switching PWM 
Converters. 
Notably, only one of the foregoing documents (Brkovic & Cuk) discloses a 
saturable inductor in the input to a DC/DC converter section of an AC/DC 
converter, but its excessively complex requirements preclude it from 
effectively meeting the requirements of many users.

DESCRIPTION OF THE INVENTION 
FIG. 1 shows, in schematic circuit diagram form, a predecessor single-stage 
AC/DC converter 11 comprising diode rectifier DR having an AC input at the 
left, with rectified positive lead P and negative (or neutral) lead N to 
the right, bridged by bulk (energy storage) capacitor Cb. Both leads 
terminate in a component DC/DC Converter (dotted outline) enclosing 
isolation transformer Tr. For simplicity this view omits any secondary 
winding and output circuitry, which may take any of many conventional 
forms. Electrical load Ro is shown bridging a pair of leads rightward from 
the dotted outline. 
High-frequency switch S (externally controlled) is connected between lead N 
and the low end of a primary winding divided by a tap into a first part 
with N.sub.P1 turns and a second part with N.sub.P2 turns. The positive 
lead contains filter inductor Lf and steering diode D1 on its way to the 
top end of the primary winding as is customary. 
The foregoing components are conventional for AC/DC converters lacking a 
PFC (power factor correction) lead. However, FIG. 1 also includes such a 
lead, starting from the junction of inductor Lf and diode D1 in the 
positive lead. This PFC lead contains inductor L1, then series diode D2, 
and connects to a tap on the primary winding. 
FIG. 2 shows, in similar schematic form, a first embodiment 12 of the 
present invention, differing from FIG. 1 solely by including saturable 
inductor Ls (and adjacent stylized hysteresis loop symbol) ahead of L1 in 
the PFC lead. The purpose of the saturable inductor, in whatever form, is 
considered further below. 
FIG. 3 shows, in similar schematic form, variant embodiment 13 differing 
from the previous embodiment by interchanging the order of the inductors 
in the PFC lead. Whereas inductor L1 followed Ls in FIG. 2, here Ls is 
preceded by redesignated inductor L1'--sharing a common ferromagnetic 
core, designated by line segments paralleling the respective inductors and 
joined at a right angle. This magnetic coupling of the inductors enables 
energy stored in L1' to transfer to Lf when switch S is turned OFF, and 
thereby enables the forward type of DC/DC converter to operate without a 
separate reset winding on the transformer--such as is shown in some 
subsequent views. 
FIG. 4 shows variant single-stage AC/DC converter 14 embodiment of this 
invention, like that in FIG. 3 except that its component DC/DC converter 
is of flyback type, which operates satisfactorily. 
FIG. 5 shows another embodiment 15 of this invention, differing from the 
embodiment of FIG. 2 by addition of a control winding Lc to Ls on a common 
ferromagnetic core--surrounded by a dotted outline. Lc is in a closed loop 
with variable-current source controlled by the output from operational 
amplifier IC1 having comparative inputs: positive lead voltage on Cb, and 
an external reference voltage Vref. 
FIG. 6 shows schematically embodiment 16, like that of FIG. 5 except that 
the component DC/DC converter is of flyback type. Thus, no further 
description of it is needed here. 
FIG. 7 similarly shows embodiment 17, like that of FIG. 5 but with the 
component DC/DC converter shown as of forward type, and with the 
transformer including another primary winding having Np3 turns. This view 
adds informative designation of currents in given circuit elements, by the 
letter I (with a matching subscript), and designation of voltages by the 
letter V (with matching subscripts). 
FIG. 8 is a graphical representation (18) of selected currents and voltages 
over a complete high-frequency cycle of operation of the FIG. 7 
embodiment, indicated at times: t0, t1, t2, t3, t4, and then t0' (the 
start of the next cycle). 
Shown from top in this graphical view are these voltage cycles: 
V.sub.S --gate control input to MOSFET high-frequency switch S; 
V.sub.ds --drain-to-source voltage of switch S; 
V.sub.A --applied at tap point A on transformer primary winding; and 
V.sub.Ls --across saturable inductor Ls. 
Shown underneath the above voltages are these current cycles: 
I.sub.Lf --through filter inductor Lf; and 
I.sub.L1 --through PFC inductor L1. 
A cycle of operation is described time segment by time segment: 
Just before starting time t0, switch S is OFF, and both Lf and L1 have no 
current flowing therethrough. Mag-Amp Ls has been reset. 
[t0-t1] At t0, switch S is turned ON, and V.sub.ds drops to zero. V.sub.A 
at the primary winding tap becomes (N.sub.P2 /N.sub.P)/V.sub.Cb. 
Throughout this time period, Ls is unsaturated, and thus acting as a 
high-impedance device (much like an open circuit). The voltage across Ls 
is equal to V.sub.IN -(N.sub.P2 /N.sub.P)V.sub.Cb. Voltages across Lf and 
L1 approximate zero. Accordingly, currents I.sub.Lf and I.sub.L1 remain 
substantially zero. As noted below, the duration of this first time period 
depends upon how long (as in volt-seconds) mag-amp action precludes Ls 
from becoming saturated--or how much reset was provided to Ls in the S OFF 
period. This time period ends and the next begins when Ls becomes 
saturated. 
[t1-t2] Ls saturation reduces its inductance to nearly zero. Both currents 
I.sub.Lf and I.sub.L1 ramp up at a rate of dI.sub.Lf /dt=I.sub.L1 /dt, 
equal to [V.sub.IN -V.sub.Cb (N.sub.P2 /N.sub.P)/(Lf+L1). Steering diode 
D1 is reverse-biased and non-conducting during this time period. The peak 
value for both these currents is reached at the end of the period (S 
switches OFF): I.sub.Lf.sup.pk =I.sub.L1.sup.pk =(DT.sub.S 
-t.sub.B)[V.sub.IN -V.sub.Cb (N.sub.P2 /N.sub.P)]/(Lf+L1), where D is the 
duty cycle of switch S, whereas T.sub.S is the switching period, and 
.DELTA.t.sub.B is the blocking time of the mag-amp (before Ls becomes 
saturated). Of course, for a given duty cycle D, the longer the Ls 
blocking time is, the lower the peak current through Lf and L1 will 
become. 
[t2-t3] Switch S is turned OFF at t2, so the voltage across S rises quickly 
to 1+V.sub.Cb (N.sub.P /N.sub.P3) (where N.sub.P3 is the number of turns 
on the transformer (added) reset primary winding), whereupon V.sub.A, the 
voltage at A, the primary tap, equals V.sub.Cb [1+(N.sub.P1 /N.sub.P3)]. 
As a result both I.sub.Lf and I.sub.L1 decrease. Depending on Lf and L1 
inductance values, as well as the instantaneous line voltage, the changing 
rates of I.sub.Lf and I.sub.L1 may or may not be identical during this 
time period. 
If the condition (V.sub.Cb -V.sub.IN)/Lf .gtoreq.(N.sub.P1 /N.sub.P3) 
(V.sub.Cb /L1) is satisfied, both currents I.sub.Lf and I.sub.L1 will 
decay to zero at identical rates: 
EQU dI.sub.Lf /dt=dI.sub.L1 /dt=[V.sub.Cb +(N.sub.P1 /N.sub.P3)V.sub.Cb 
-V.sub.IN ]/(Lf+L1). 
In this special case, diode D1 remains non-conducting throughout the entire 
switching cycle, and both I.sub.Lf and I.sub.L1 decay to zero at the same 
rate--and, of course, then reach zero at the same time (t3). 
But if the condition (V.sub.Cb -V.sub.IN)/Lf.gtoreq.(N.sub.P1 /N.sub.P3) 
(V.sub.Cb /L1) is not met, then I.sub.Lf will decrease faster than 
I.sub.L1, in accord with the following: 
EQU dI.sub.Lf /dt=(V.sub.Cb -V.sub.IN)/Lf and dI.sub.L1 /dt=(N.sub.P1 
/N.sub.P3) (V.sub.Cb /L1). 
The current difference between I.sub.Lf and I.sub.L1 flows into 
energy-storage capacitor Cb through diode D1, and I.sub.L1 decays to zero 
before I.sub.Lf. 
[t3-t4] This is a distinct operating stage only if the last equation is not 
satisfied. After I.sub.L1 decays to zero at time t3, PFC diode D2 becomes 
reverse-biased, and I.sub.Lf continues to decrease at the rate in the 
immediately preceding equation, until reaching zero. During this time 
period, Ls begins to reset and becomes unsaturated. 
Mag-amp resetting can be controlled in a number of ways, and FIG. 7 shows 
resetting by applying a current source Ic to control winding Lc. Precisely 
when the reset waveform will appear can vary within the time period t3-t0' 
but the maximum reset voltage applied to Ls will be limited to (N.sub.P1 
/N.sub.P3)V.sub.Cb (otherwise D2 would start to conduct again). The impact 
Ls has on the operation or performance of the converter is determined 
essentially by the volt-seconds applied to Ls when I.sub.LS is zero (i.e., 
within time period t3-t0'). The total reset volt-seconds applied to Ls 
will determine how many volt-seconds Ls can block conduction, or how long 
.DELTA.B will be when S is next turned ON in the next ensuing switching 
cycle. 
[t4-t0] Both I.sub.Lf and IP.sub.L1 remain at zero during this time period. 
Note in FIG. 8 the implicit assumption that the forward transformer will 
complete reset (when V.sub.ds voltage steps down) within this time period. 
In a real circuit, the forward transformer could complete reset before 
I.sub.Lf reaches zero, whereupon the I.sub.Lf waveform will appear a bit 
different than as shown there, but the principle of operation remains 
fundamentally the same. As already noted, time t0', S is turned ON again, 
and the cycle is repeated. 
FIG. 9 shows a typical graph (19) of V.sub.Cb vs. Io output/load current 
for the FIGS. 6-8 converter with and, alternatively, without saturable 
inductor Ls when operating over a North American input voltage range 
(90-132 VAC). Curve A corresponds to the circuit without using Ls. For a 
given line voltage, V.sub.Cb increases as Io decreases. For such voltage 
range, typical maximum V.sub.Cb, assuming (again) high line voltage and 
light load, is between 220 and 250 V, if the converter is designed to meet 
the IEC 1000-3-2 input harmonic requirement, which requires a power factor 
of about 0.8 or more. Needed would be a 250 V or 300 V capacitor (Cb), and 
a 500 V or 600 V MOSFET as the high-frequency power switch. 
Alternatively, Curve B corresponds to operating the converter with a 
saturable inductor added according to the present invention. For the same 
90-132 VAC input range, V.sub.ref can be set at about 186 V, which is 
close to the maximum peak voltage. When the load current is heavy, 
V.sub.Cb is below V.sub.ref, and op-amp IC1 commands the current source Ic 
to remain at zero, whereupon Ls stays saturated over the entire switching 
cycle and behaves like a very small inductor (Ls residu the same as in the 
absence of Ls. V.sub.Cb increases as Io decreases, and the curve of 
V.sub.Cb vs. Io essentially repeats Curve A. 
As the load current decreases to a critical level, Io.sup.crit (which is 
line-voltage-dependent so that the higher the RMS line voltage, the lower 
the relative Io.sup.crit), V.sub.Cb reaches its threshold voltage, 
V.sub.ref. Op-amp IC1 starts to generate an output for Ic to increase, and 
Ls is provided a degree of reset to reduce the input current and suppress 
V.sub.Cb. As Io continues to decrease, Ic increases and becomes able to 
provide more reset to Ls. As long as the IC1 control loop has a high 
enough DC gain, the maximum V.sub.Cb will be clamped to a value very close 
to V.sub.ref. 
With the maximum V.sub.Cb reduced to about 186 V, a 200 V capacitor as 
V.sub.Cb, and a 400 V MOSFET (with significantly lower ON-resistance than 
a 500 V or 600 V one) as the power switch, improving the efficiency of the 
converter and reducing its cost, as compared to a converter without the 
saturable reactor. 
FIG. 10 shows schematically embodiment 20, like that of FIG. 7 but lacking 
a separate inductor following Ls in the PFC lead. Reset winding (NP.sub.3 
becomes optional due to lack of the separate inductor. Although the design 
flexibility is somewhat reduced, compared to the converter in FIG. 7, this 
FIG. 10 circuit saves an inductor. For universal (90-264 VAC) input range, 
the bulk capacitor can expect to see a maximum voltage of about 430-450 V 
without saturable inductor Ls, which is reducible to about 380 V by 
addition of Ls. 
As already noted, reset of Ls can be provided in numerous ways. FIGS. 11 
and 12 show respective forward converter embodiments 21 and 22 of this 
invention with modified reset circuitry, based (in each instance) on a few 
low-cost components forming a reset module variously connected in the 
respective views. The reset module features a transistor Q1, having a gate 
resistor R1 preceded by a zener diode D.sub.Z, connected to a source of 
activation threshold voltage, and connecting via its emitter to a 
dissimilar voltage, and via its collector to the saturable inductor via a 
control diode Dc. 
In FIG. 11, the PFC winding includes saturable inductor Ls in mag-amp 
configuration with control winding Lc. inductor L1, and diode D2. External 
control voltage Vc is provided through inductor Lc' to one end of the 
control winding, whose other end connects through an added resistor R2 to 
the control diode of the module. The module's emitter is tied to the 
negative lead, and its base via the zener diode to the positive lead, 
setting a threshold voltage (similar to Vref in FIG. 9). At low line and 
heavy load, V.sub.Cb is below zener diode voltage V.sub.Dz ; Q1 remains 
OFF, and Ls is not reset. V.sub.Cb increases as line voltage increases, or 
load current decreases, until it becomes high enough to overcome the 
D.sub.z threshold voltage to activate Q1. Then control winding Lc receives 
reset current, and Ls is reset during the power switch S OFF period. 
Proper selection of R1 and R2 enables maximum V.sub.Cb to be clamped to a 
value close to V.sub.Dz. 
Operation of FIG. 11 converter 21 was verified experimentally by a circuit 
with a 90-132 VAC input and 10 V regulated output. The load current can 
vary between 0 and 6.5 A. Part numbers/parameters were as follows: 
S--IRF840; Lf--18 uH; L1--30 uH, Cb--150 uF; D1, D2--BYV26A; DR1, 
DR2--16CTQ100; Lo--65 uH, Co--390 uF; Q1--2N22222A; Lc--2 mH; Dz--180 V; 
R1--5.1 kohm; R2--360 ohm. Ls is implemented on a Toshiba "MS" series 
amorphous saturable core, MS 21.times.14.times.4.5 W, with 42 turns for 
the main winding and 16 turns for the control winding. The transformer is 
implemented on a TDK PC40-LP32/13 core and has 15 turns for N.sub.P1, 40 
turns for N.sub.P3, and 11 turns for the N.sub.S winding. The switching 
frequency is 100 kHz. The converter was tested first without Ls. At high 
line (132 VAC) and light load, the measured maximum Cb stress was about 
230 V. After adding Ls and its associated control circuitry, the measured 
maximum Cb stress was reduced to about 183, which is slightly lower than 
the maximum peak voltage (186 V) because of component parasitics (such as 
the forward voltage drop of the input bridge rectifier diodes). In both 
cases, the power factor at nominal line (110 VAC) and maximum load is 
about 0.8, and the input harmonic currents are below IEC 1000-3-2 limits. 
The foregoing experimental results agree well with theory, and are more 
important than my theoretical views, as the latter could be erroneous, and 
are unnecessary for understanding and successfully practicing the 
invention as described in several embodiments here. 
In FIG. 12, the PFC lead from the positive lead to primary winding tap A 
contains diode D2, inductor L1, and saturable inductor Ls. Here the module 
emitter is tied to the positive lead, its control diode Dc connects from 
the junction of L1 and Ls, and its zener diode is connected to diode D4, 
their junction being separated from the negative lead by capacitor C1, and 
D4 connects to the junction of the reset primary winding with diode D3 
from the negative lead. Thus, diode D4 and capacitor C1 detect the voltage 
across diode D3: [(1+N.sub.P3 /N.sub.P1 +N.sub.P2)]V.sub.Cb when S is 
turned ON. Selection of threshold voltage of zener diode Dz at (N.sub.P3 
/N.sub.P1 +N.sub.P2)]V.sub.Cb will keep Q1 OFF when V.sub.Cb is less than 
V.sub.ref, and will be activated to suppress Cb voltage when V.sub.Cb 
reaches V.sub.ref and Dz breaks down. When S is turned OFF, the voltage at 
tap point A equals [1+(N.sub.P1 /N.sub.P3)]V.sub.Cb, which is higher than 
the voltage (V.sub.Cb) at the emitter of Q1. Therefore, depending upon how 
strongly Q1 is turned ON when Dz breaks down, a reset voltage will be 
applied to Ls during the S switch OFF period. When Q1 is fully ON, Ls can 
receive a maximum reset voltage of (N.sub.P1 /N.sub.P3)V.sub.Cb. In 
comparison with the reset circuitry of FIG. 11, the reset circuitry of 
FIG. 12 saves a second winding but requires a transistor with a higher 
voltage rating. Both reset embodiments are simply effective. 
As most such converters necessitate design trade-offs between maximum bulk 
capacitor and power factor, the transformer primary PFC tap and a 
saturable inductor is a substantial advance because it enables capacitor 
stress reduction at good power factor. 
Preferred embodiments and variants have been suggested for this invention. 
Such concepts and circuitry are not only useful for single-stage AC/DC 
converters with PFC as illustrated and described here but can be extended 
to other DC/DC topologies than flyback and forward, including such as 
SEPIC and Cuk types, for example. 
Other modifications may be made, as by adding, combining, deleting, or 
subdividing compositions, parts, or steps, while retaining all or some of 
the advantages and benefits of the present invention--which itself is 
defined in the following claims.