Capacitance memories operated with intermittently-energized integrated circuits

Capacitance memories operated with intermittently-energized monolithic integrated circuits tend to lose information during periods between the spaced intervals the integrated-circuits are energized. This tendency, attributable to sneak conduction paths in the un-energized integrated circuit, is forestalled by inserting the channel of a field-effect transistor in series with the memory capacitance, which channel is rendered conductive when only the energizing potential is supplied to the integrated circuit.

The present invention concerns capacitance memories operated together with 
intermittently energized monolithic integrated circuits--e.g., those 
receiving energizing potentials directly from a-c power mains during 
alternate half-cycles of a-c line potential. 
Examples of this type of circuit are sample-and-hold circuits, d-c 
restoration circuits, integrators over intervals relatively long compared 
to the duration of an a-c line potential cycle, and various other analog 
memories. A problem which arises is that, in the intervening periods 
between the spaced intervals during which energizing potential is applied 
to the monolithic integrated circuit, sneak paths are presented which 
permit leakage of charge to or from the memory capacitor. 
The present invention contemplates serial connection of the memory 
capacitor and an analog switch included within the integrated circuit. 
This switch is conductive during the spaced intervals when energizing 
potential is supplied to the integrated circuit, permitting charging or 
discharging of the memory capacitor by the rest of the integrated circuit, 
and is non-conductive during the intervening periods between the aforesaid 
spaced intervals, forestalling change in the quantity of charge stored in 
the memory capacitor. The present inventor has found that an appropriate 
device for constructing an analog switch of the sort desired, when using a 
P-substrate monolithic integrated circuit, comprises a doubly-isolated 
N-channel enhancement-mode conductor-insulator-semiconductor (e.g., 
metal-oxide semiconductor) transistor having its gate biased positively 
during those spaced intervals energizing potential is supplied to the 
integrated circuit.

In FIG. 1, monolithic integrated circuit 10 constructed on a chip is 
arranged together with other elements for detecting the presence of ground 
faults on either of line conductors 11 and 12 or neutral faults on neutral 
conductor 13 in a three-wire grounded-neutral balanced-single-phase a.c. 
(e.g., 60 Hz) power distribution system. Integrated circuit 10 is arranged 
to be line-operated, energizing potential being applied every half cycle 
of a-c line voltage between its terminals 101 and 102. To this end, diode 
14 provides half-wave rectified current to the off-chip voltage-clipping 
network comprising series-pass resistor 15 and shunt-clipper avalanche 
diode 16. The resulting clipped half-wave rectified a-c line potential 
V.sub.102 at terminal 102 (e.g., of 26 v peak amplitude) is further 
clipped by a further on-chip voltage-clipping network comprising 
series-pass resistive element 103 and shunt-clipper avalanche diode 104. 
Diode 104 has a lower avalanche breakdown voltage than that of diode 16 
(e.g., 16 v as compared to 26 v); and the waveform of the doubly clipped 
half-wave rectified line voltage approaches a square wave. 
This doubly clipped half-wave rectified line voltage V.sub.104 across diode 
104 is used as an energizing potential for: a 5 kHz oscillator 105, which 
may be a relaxation oscillator; buffer amplifier 106; keyed amplifier 107, 
used as a synchronous detector at power line frequency; and amplifiers 108 
and 109, used as threshold detectors. Threshold detector 108 supplies 
output signal to terminal 110 when the potential applied to the input 
terminals of detectors 108 and 109 exceeds a negative threshold potential; 
threshold detector 109 supplies an output signal to terminal 110 when this 
potential exceeds a positive threshold level. 
The energizing potential V.sub.104 is also applied to a further on-chip 
voltage-clipping network comprising a series-pass resistive element 111 
and shunt-clipper avalanche diode 112. Diode 112 has an avalanche 
breakdown voltage V.sub.112 that is even lower than that of diode 104 
(e.g., 7 v). So, a substantially square-wave reference potential V.sub.113 
thus appears at terminal 113 of integrated circuit 10. Memory capacitor 2 
has one of its ends connected to terminal 113 and the other to terminal 
114 of integrated circuit 10. Capacitor 2 is used to store information 
provided at point 115 by synchronous detection processes involving keyed 
amplifier 107, which amplifies at such times energizing potential is 
applied to it and so synchronously detects signals at power line 
frequency, and P-channel field-effect transistor 116 operated as a 
transmission gate, which, by application of oscillations to its gate 
electrode from oscillator 105, is periodically rendered conductive and so 
synchronously detects 5 kHz signals. 
In accordance with the present invention, capacitor 2 is not continuously 
connected to point 115, but only at such times as energizing potential is 
available to the rest of the integrated circuit. The analog switch that 
controls the connection of capacitor 2 to point 115 is N-channel field 
effect transistor 117. When V.sub.102 is substantially zero-valued during 
alternate half cycles of power line frequency, insufficient voltage 
obtains at terminal 102 to cause avalanche conduction in diode 118. 
Therefore, resistive element 119 holds the gate electrode of N-channel FET 
117 at ground potential. This prevents forward biasing of the gate 
electrode of this enhancement-mode device 117 with respect to its channel, 
causing the channel of FET 117 to be non-conductive and disconnect point 
115 from capacitor 2. 
When V.sub.102 is of sufficient amplitude to cause avalanche breakdown of 
diode 118, positive potential is applied to the gate electrode of FET 117. 
The breakdown potential V.sub.118 of diode 118 is designed to be of a 
value (e.g., 11) such that the gate potential responsive to V.sub.102 
applied to FET 117 will be sufficient to cause conduction of FET 117 only 
when V.sub.102 exceeds V.sub.104 by an appreciable amount. This is 
arranged by making V.sub.118 greater than the peak value of V.sub.104 
minus both the peak value of V.sub.113 and the threshold voltage of FET 
117. This assures that FET 117 will connect capacitor 102 to point 115 
only at such times as energizing potential V.sub.104 is applied to: 
oscillator 105; amplifiers 106, 107; and voltage comparators 108, 109. 
Oscillations from oscillator 105 are amplified in buffer amplifier 106, 
which supplies the amplified oscillations to terminal 120 for coupling to 
the neutral conductor 13 via transformer 17. Conductors 11, 12 and 13 
thread a core 19 to serve as primaries of a differential current 
transformer 20, the core 19 of which is wrapped by a secondary winding 21. 
In the absence of a ground fault in neutral conductor 13 on the load side 
of transformer 20, no 5 kHz current components will flow in conductor 13 
and there will be no 5 kHz current induced in winding 21. 
When a ground fault is present on neutral conductor 13 on the load side of 
transformer 20, amplified 5 kHz oscillation current will be induced in 
that portion of conductor 13 threading core 19, inducing 5 kHz currents in 
winding 21. These 5 kHz currents, which occur during the alternate 
half-cycles of the a-c line power in which energizing potential is applied 
to oscillator 105 and amplifier 107, are amplified by amplifier 107 and 
are synchronously switched by FET 116 to cause the accumulation of charge 
on capacitor 2 when it is connected to point 115 by FET 117. This causes a 
potential to be developed across capacitor 2, which potential is applied 
to the input circuits of the threshold detectors 108 and 109, and will be 
of sufficient amplitude and correct polarity to exceed the threshold 
potential required to cause one of the threshold detectors 108, 109 to 
supply output signal to terminal 110. 
Absent a ground fault in one of the line conductors 11 and 12, the power 
line currents flowing to and from the load are substantially equal, so 
there is no substantial current of power line frequency (e.g., 60 Hz) 
induced in winding 21. When a ground fault occurs on either of line 
conductors 11 and 12, the instantaneous currents flowing to and from the 
load will not be equal and so a current at power line frequency will be 
induced in winding 21. This current synchronously switched by keyed 
amplifier 107 and subsequently chopped at a 5 kHz rate by FET 116 will 
cause accumulation of charge on capacitor 2 when it is connected to point 
115 by FET 117. This causes a potential to be developed across capacitor 2 
which potential is applied to the input circuits of the threshold 
detectors 108 and 109 and will be of sufficient amplitude and correct 
polarity to exceed the threshold potential required to cause one of the 
threshold detectors 108, 109 to supply output signal to terminal 110. 
The appearance of output signal on terminal 110 is, then, indicative of the 
presence of a ground-fault on one of the conductors 11, 12, 13. This 
output signal may be used for actuating a ground-fault indicator (not 
shown). Alternatively, this output signal may be used for actuating a 
relay switch (not shown) connected to open the conductors 11, 12 and 13 
and forestall delivery of current through them, thus implementing a 
ground-fault interrupter apparatus. 
FIG. 2 shows portions of the parasitic circuit that could exist in the FIG. 
1 circuit during the times V.sub.104 is zero-valued if the connection of 
terminal 114 to point 115 were a direct connection rather than through an 
appropriate analog switch such as FET 117. When the capacitor has been 
charged sufficiently to cause potential at terminal 114 to exceed that at 
terminal 113 by about two junction offset potentials, a discharge path 
exists. The N-material isolation tub 201 for FET 116, which normally is 
reversed biased with respect to P substrate 202, no longer is, so the 
parasitic PNP transistor existing between substrate 202, isolation tub 
201, and P region 203 becomes conductive to couple connection 115 to 
substrate 202, which is grounded. This applies the potential across 
capacitor 2 to avalanche diode 112 so as to forward bias it into 
conduction and a loop is thus completed which can discharge capacitor 2. 
One can forestall this particular mode of discharge by connecting a 
blocking diode in back-to-back connection with a diode between terminal 
113 and the ground connection 204, but other undesired paths for discharge 
obtain. For example, there is a loop for discharge through the parasitic 
transistor just described, capacitor 2, and bleeder resistors 111 and 103 
to the zero-valued V.sub.102. There can be discharge paths completed 
through the isolation tubs holding diodes 205, 206, 207, 208 which may be 
used together with transistors 209 and 210 for establishing threshold 
potentials in voltage comparators 108 and 109. A discharge path can be 
completed through the parasitic PNP associated with NPN transistor 209 
when its collector potential applied via lead 211 falls to ground 
potential. The fall of the potential on the gate electrode 212 of FET 116 
towards ground potential will render its channel conductive and provides 
means for completing a sneak path for charge through keyed amplifier 107 
if it be of a type presenting a path from its output terminal to ground 
when not supplied energizing potential. 
As pointed out above, these paths for discharge of capacitor 2 can be 
interrupted by inserting the controlled conduction path of an analog 
switch in series with capacitor 2, which controlled conduction path is 
conductive only when energizing potential V.sub.104 is at peak value. An 
enhancement mode N-channel conductor-insulator-semiconductor field-effect 
transistor 117 shown in plan and profile in FIGS. 3 and 4, respectively, 
is particularly advantageous for use as the analog switch, the controlled 
conduction path of which is to be serially connected with the memory 
capacitor 2. This device is constructed within a region 302 of P-material, 
located at an exposed surface of an N-material isolation tub 301. 
Isolation tub 301 is located on the same P-material substrate 202 as the 
other elements in the monolithic integrated circuit. Regions 303 and 304 
of N+ material defining the ends of the channel of transistor 117, are 
ohmically contacted by metallization 305 and 306 that connects one of 
these ends to terminal 114 and the other to point 115 (see FIG. 1). The 
remainder of the channel is formed by electrostatic induction, between end 
regions 303 and 304 in that portion of region 302 immediately below its 
interface with the dielectric layer 307, responsive to potential applied 
to the gate electrode structure 308. 
A P+ -material guard ring 309 is diffused into the periphery of the 
P-material region 302 and contacted by metallization 306. Substrate 202 is 
ohmically contacted at a point not shown and connected to a potential 
lower than that at which any other portion of the integrated circuit is 
normally operated. A region 310 of N+-material shown only in plan view in 
FIG. 3 is diffused into N-material isolation tub 301, so the tub can be 
ohmically contacted by metallization 311 which is connected to a potential 
that reverse-biases the junction between region 301 and substrate 202 and 
the junction between regions 301 and 302--e.g., ground as shown in FIG. 1. 
The following features are of interest in the enhancement-type N-channel 
field-effect transistor 117 shown in FIGS. 3 and 4. When the potential on 
the gate electrode structure 308 falls to ground, the channel induced by 
electrostatic induction no longer exists and so transistor 117 is no 
longer conductive between regions 303 and 304. Control potential for 
application to gate electrode structure 308 can be simply derived from the 
energizing potential itself by simple voltage translation methods. There 
is no need for signal inversion, as would be the case if the analog switch 
were provided by the controlled-conduction channel of a p-channel 
field-effect transistor formed within an N-material isolation tub. An 
undesired sneak path through which capacitor 2 will discharge will be 
established only if positive potential on the one of N-material regions 
303 and 304 connected to point 115 exceeds the avalanche breakdown 
potential of the semiconductor junction between that region and the 
P-material region 302 in which it is located. The reverse potential 
required to cause such avalanche breakdown is quite large, usually being 
in excess of 5.5 volts--e.g., eight volts for processing used by RCA 
Corporation.