Integrated circuit pin sharing method and apparatus for diverse memory devices by multiplexing subsets of pins in accordance with operation modes

The present invention, generally speaking, provides for pin sharing between two or more disparate memory devices, a dynamic memory device such as a CD ROM drive or the like and a static memory device such as a ROM integrated circuit. In accordance with one embodiment of the invention, a common set of pins of an integrated circuit are used to interface to a plurality of different information storage device including both a dynamic storage device and static storage device by, in a first mode, using a first subset of the common set of pins to carry data information for one of the devices and, in a second mode, using the first subset of pins to carry address information for another one of the devices. In accordance with another embodiment of the invention, an integrated circuit includes a set of I/O pins, a multiplexer coupled to the set of I/O pins, and multiple device controllers coupled to the multiplexer, including both a dynamic storage device controller and a static storage device controller. Control circuitry is provided for, in a first mode, coupling a first one the device controllers through the multiplexer to the set of I/O pins and for, in a second mode, coupling a second one of the device controllers through the multiplexer to the set of I/O pins.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to integrated circuits and pin count 
reduction. 
2. State of the Art 
As the integration density of integrated circuits increases, designs have 
increasingly become pin-count limited. That is, the features to be 
included in the chip are limited by the number of I/O pins of the final 
chip package. Furthermore, the cost of the chip package in proportion to 
the total cost of the typical integrated circuit continues to increase. In 
many instances, the cost of the final integrated circuit is dominated by 
the cost of the package. For high-volume integrated circuits, a relatively 
small savings per part in the cost of the package can result in a 
substantial overall cost savings. Hence, design efforts to reduce pin 
count so as to allow a lower-cost package to be used instead of a 
higher-cost package are of considerable importance. 
Consumer electronics devices are high volume and very cost-sensitive. An 
example of one such device is a game player. A game player may have 
diverse memory devices such as a boot ROM (Read Only Memory) and a CD ROM 
drive, DVD drive, or the like. A system controller for such a device must 
interface to both types of memory devices. CD ROM drives and the like are 
typically IDE (Integrated Device Electronics) devices conforming to the 
IDE standard. Whereas ROMs typically reside on the same printed circuit 
board as the system controller, IDE drives are connected to the printed 
circuit board using a cable. Pin sharing between the memory devices is 
problematic in that if the devices are connected to the same pins, the ROM 
will have insufficient drive strength to drive the pins. 
Furthermore, the pin requirements of the devices are substantially 
different. An IDE device has a wide data bus (e.g., 16 bits) and a narrow 
address bus (e.g., 3 bits). A ROM, on the other hand, has a narrow data 
bus (e.g, 8 bits) and a wide address bus (e.g., 16 bits). The disparate 
nature of these memory devices therefore renders pin sharing extremely 
difficult. 
SUMMARY OF THE INVENTION 
The present invention, generally speaking, provides for pin sharing between 
two or more disparate memory devices, a dynamic memory device such as a CD 
ROM drive or the like and a static memory device such as a ROM integrated 
circuit. In accordance with one embodiment of the invention, a common set 
of pins of an integrated circuit are used to interface to a plurality of 
different information storage device including both a dynamic storage 
device and static storage device by, in a first mode, using a first subset 
of the common set of pins to carry data information for one of the devices 
and, in a second mode, using the first subset of pins to carry address 
information for another one of the devices. In accordance with another 
embodiment of the invention, an integrated circuit includes a set of I/O 
pins, a multiplexer coupled to the set of I/O pins, and multiple device 
controllers coupled to the multiplexer, including both a dynamic storage 
device controller and a static storage device controller. Control 
circuitry is provided for, in a first mode, coupling a first one the 
device controllers through the multiplexer to the set of I/O pins and for, 
in a second mode, coupling a second one of the device controllers through 
the multiplexer to the set of I/O pins.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring now to FIG. 1, there is shown a block diagram of an exemplary 
system controller in which the present invention may be used. The system 
controller is realized in the form of an integrated circuit having a pin 
interface with a number of I/O pins. Different subsets (103, 105, 107, 
109) of logically related pins are indicated. In the exemplary embodiment, 
the system controller interfaces to an IDE device 110 and a ROM 120, and 
may also interface to an optional modem 130. Normally, because of the 
disparate nature of the IDE device and the ROM, interfacing to the ROM 
would increase the required pin count of the part by about 40 pins more 
than would be required without the ROM, thereby necessitating an expensive 
package. Using the teachings of the present invention, the number of pins 
required by the ROM may be reduced to only 14, thereby allowing a 
relatively inexpensive package to be used. 
Referring still to FIG. 1, a subset of pins 101 includes separate chip 
select pins for each of the external devices, including a ROM chip select 
(ROMCS#), a modem chip select (EXTCS#) and two IDE chip selects (CS0# and 
CS1#). The chip selects are produced by an address decoder 111 coupled to 
a target address portion of the I-PCI bus 140. The I-PCI bus provides for 
high data throughput within the system controller chip. The I-PCI bus 140 
is an internal bus that is similar to the industry standard PCI bus, but 
has been modified (in this example) for use internal to a complex 
integrated circuit. The decoder 111 also selects configuration registers 
113 of the system controller chip for reading and writing. By writing 
appropriate information in to the configuration registers, different modes 
may be selected including a modem mode, a ROM mode, a standard IDE mode 
(IDE STD) that uses DMA and a non-DMA IDE mode (IDE TF) to allow access to 
the test file registers within the IDE drive. 
A subset of pins 107 (16 pins in the illustrated embodiment) provides data 
information to the IDE device 110 in IDE mode and provides address 
information to the ROM 120 in ROM mode. In FIG. 1, the data busses of the 
external devices are represented at the upper edges of the corresponding 
blocks, and data busses of the external devices are represented at the 
lower edges of the corresponding blocks. A subset of pins 109 provides 
data information from the ROM 120 in ROM mode and to and from the modem 
130 in modem mode. Finally, a subset of pins 103 provides address 
information to each of the respective devices (110, 120, 130) in their 
respective modes. This address information is provided through a 
multiplexer 115 and may come from either address bits [5:0] of the PCI bus 
or address bits [7:2] of the PCI bus depending on the mode selected by 
block 113. 
The subset of pins 107 performs three functions: 1) ROM address output; 2) 
IDE data output; and 3) IDE data input. For function number 1, the ROM 
chip select is asserted, a multiplexer 117 is controlled to select address 
bits [21:6], and the pins are driven as outputs. For function number 2, 
the appropriate IDE chip select is asserted, the multiplexer 117 is 
controlled to select PCI data input pins PCI.sub.-- I[15:0], and the pins 
are driven as outputs. For function number 3, the appropriate IDE chip 
select is asserted and the pins are driven as inputs to the chip. Data 
from the IDE device, IDEI[15:0] is input to both of two parallel data 
paths, a DMA data path 150 and a non-DMA data path 160. 
In ROM mode and modem mode, the DMA data path 150 converts byte data to 
word data (elements 121, 123, 125) under control of a B2W state machine 
127 and then converts the resulting word data to longword data (element 
131) under control of a W2L 133 state machine. In IDE mode, the DMA data 
path converts word data to longword data. In both modes, longword data is 
queued within a FIFO 135 for output to the PCI bus and is also input to 
the non-DMA data path 160. The FIFO/OMA paths are used to transfer data 
from the IDE drive direct to memory. The non-DMA path is intended 
primarily for code and data fetches from the ROM. These accesses are not 
always sequential and cannot always be performed by DMA. This circuit does 
support DMA movement of ROM data or single word access of IDE data, but 
this is not normal access. 
The non-DMA data path 160 selects (through multiplexer 161) word data from 
the IDE device 110, the configuration registers 113, or a long word (32 
bits) the DMA data path 150 or selects byte data from the modem 130. This 
allows the host system to access each device appropriately. 
The subset of pins 109 also performs three functions: 1) data input from 
the ROM 120; 2) data input from the modem 130; and 3) data output to the 
modem 130. For function number 1, the ROM chip select is asserted and the 
pins are driven as inputs. For function number 2, the modem chip select is 
asserted and the pins are driven as inputs. For function number 3, the 
modem chip select is asserted and the pins are driven as outputs. 
Referring to FIG. 2, the pin assignments described generally in relation to 
FIG. 1 are shown in greater detail. A pin multiplexer 201 receives address 
bits A[21:0] and data bits D[15:0] from the PCI bus of FIG. 1. The pin 
multiplexer 201 includes multiplexers 115 and 117 in FIG. 1, together with 
additional logic not shown in FIG. 1. Control of the pin multiplexer 201 
is performed by arbitration logic 203. The arbitration logic 203 receives 
request signals from multiple device controllers including, in the present 
example, an IDE controller 210, a ROM controller 220 and a modem 
controller 230. The IDE controller 210 may perform target accesses or 
initiator accesses in accordance with the PCI specification. The ROM and 
modem controllers (220, 230) may perform target accesses only. 
The arbitration logic 201 ensures that conflict between the devices in 
relation to the shared pins is avoided. If only a ROM and IDE device are 
present, the arbitration logic 201 may operate such that the shared pins 
are initially reserved for use of the ROM 120 during boot and thereafter 
are reserved for use of the IDE device 110. Alternatively, both the ROM 
120 and the IDE device 110 may continue to operate following boot, with 
the arbitration logic 201 determining which device controller and which 
corresponding device are given control of the shared pins at any given 
time. 
The respective device controllers (210, 220, 230) each generate chip select 
signals for the respective devices and read/write signals for the 
respective devices. The chip select signals connect directly to dedicated 
pins. The read/write signals, like the address and data signals, are 
multiplexed and are therefore input to the pin multiplexer 201. The IDE 
controller 210 generates a number of additional control signals as shown 
in FIG. 2. For convenience, the actual connection of these control signals 
to the IDE controller 210 is not shown. 
The subsets of pins identified in FIG. 1 are identified by the same 
reference numerals in FIG. 2. The manner in which the ROM, IDE and modem 
interfaces are multiplexed onto common pins may be represented in tabular 
form as follows: 
TABLE 1 
__________________________________________________________________________ 
IDE IO 
IDE DMA 
ROM Modem 
Pin Name function 
function 
function 
function 
__________________________________________________________________________ 
IDE.sub.-- D[15:0]/RA[20:5] 
Data [15:0] 
Data [15:0] 
A[20:5] 
None 
IDE.sub.-- CS0# 
Select for 
N/A, (high) 
N/A, (high) 
N/A, (high) 
task file, 
`IO` data 
IDE.sub.-- CS1# 
Select for 
N/A, (high) 
N/A, (high) 
N/A, (high) 
alt file, 
register 
IDE.sub.-- A[2:0]/RA[4:0] 
IDE A[2:0] 
N/A, (xs) 
A[4:0] A[4:0] 
IDE.sub.-- IOR# 
IOR# IOR# IOR# IOR# 
IDE.sub.-- IOW# 
IOW# IOW# WR# IOW# 
IDE.sub.-- DRQ 
N/A DACK# N/A N/A 
IDE.sub.-- DACK# 
IDEIRQ 
N/A N/A N/A 
IDEIRQ N/A N/A N/A N/A 
ROMCS# N/A N/A ROMCS N/A 
RA[22:21] N/A N/A A[22:21] 
N/A 
RD[7:0] N/A N/A D[7:0] D[7:0] 
EXT.sub.-- CS# 
N/A N/A N/A CS# 
EXT.sub.-- INT# 
N/A N/A N/A INTRQ# 
__________________________________________________________________________ 
It will be appreciated by those of ordinary skill in the art that the 
invention can be embodied in other specific forms without departing from 
the spirit or essential character thereof. The presently disclosed 
embodiments are therefore considered in all respects to be illustrative 
and not restrictive. The scope of the invention is indicated by the 
appended claims rather than the foregoing description, and all changes 
which come within the meaning and range of equivalents thereof are 
intended to be embraced therein.