Integrated circuit with metal layer having carbon nanotubes and methods of making same

A method of fabricating an integrated circuit comprises forming or providing a solution containing carbon nanotubes and forming a metal layer utilizing the solution.

FIELD OF THE INVENTION

The present invention relates in general to the field of integrated circuits and, in particular, to their fabrication.

BACKGROUND OF INVENTION

Metal layers in integrate circuits are utilized to electrically interconnect various devices fabricated on a substrate. Resistance of the materials utilized in the metal layers affect the speed with which signals can propagate between these devices. To improve the propagation of signals, copper has taken over as the primary metal in use in high speed design applications.

Nevertheless, even with increase conductivity of copper, vis-á-vis aluminum, speed issues with copper interconnect exist. For example, as copper conductor features continue to decrease in size, the conductivity resistance associated with the copper conductors increases causing a decrease in speed of signals on these size decreased signal traces. Another problem that affects the propagation of signals is an increase in the electromigration resistance. As conductor feature sizes continue to decrease copper electromigration resistance is limited by such things as surface diffusion and voids.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Carbon nanotubes, depending on their configuration, may exhibit various electrical properties. For example, in one configuration, carbon nanotubes may act as semiconductors. In another configuration, carbon nanotubes act as conductors. Specifically, single wall carbon nanotubes in an arm chair configuration exhibit a number of metallic characteristics.

Among these metallic characteristics, a number of properties are of particular interest with respect to their possible use as part of a metal layer. Single wall, arm chair carbon nanotubes have been shown to have high electrical and thermal conductivity, e.g. higher than copper. Composite single wall carbon nanotube and copper material have also been shown to have higher electrical conductivity than copper. In addition, single wall carbon nanotubes have high electromigration resistance. Composite single wall carbon nanotube and copper materials have also been shown to have higher electromigration resistance than copper.

Disclosed herein are methods of fabricating integrated circuit having conduction layer with potentially higher electrical and thermal conductivity and/or higher electromigration resistance than the prior art. These methods include electro- and electroless plating of metals, electrophoresis and spin on. While the discussion below is focused around the metallization in a dual damascene process, it will be appreciated that the disclosed method can be utilized to provide conductive material application in other integrated circuit processes.

FIG. 1illustrates a cross sectional view of a portion of an integrated circuit having a dual damascene feature, in accordance with one embodiment. The integrated circuit includes a substrate110. Active components of a circuit are formed on substrate110. Further, one or more layers of metal are formed to provide for interconnect between the active components. An oxide layer120is fabricated on an etch stop layer125. The oxide layer120comprises two layers; one used as a via layer130and one as a trench layer140. One of several methods may be utilized to create the trenches145and vias135. In the via-first method, both layers130140may be etched creating vias135. Next, the trench layer140only may be etched creating trenches145for the layer of interconnect. A barrier layer150may be placed on the oxide to separate the metallization layer from the oxide layer to prevent interaction between the two layers. A seed layer160is then placed on the barrier layer150. A metal layer170is then placed on the seed layer160. As discussed in more detail below, the metal layer170comprises carbon nanotubes. For each of the above processes, a chemical mechanical process may be utilized to planarize the surface of the particular layer.

FIG. 2shows a flowchart illustrating a method for creating portions of an integrated circuit design, in accordance with one embodiment. Illustrated is a method for forming an interconnect utilizing co-electroplating to form a metal layer with carbon nanotubes. As illustrated, a substrate with active components is first formed210. Next, deposition of a dielectric layer, to facilitate formation of interconnects to interconnect the active components, is performed. Further, formation of dual damascene features in the dielectric layer, by using e.g. operations of lithography and etching, is performed220.

Next, a barrier layer and a seed layer are deposited230. The barrier layer may comprise a material such as tantalum, tantalum nitride, tantalum silicon nitride, titanium nitride, titanium silicon nitride, tungsten nitride, tungsten silicon nitride, cobalt tungsten phosphide or other materials of the like. The barrier layer may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or plating. In various embodiments, the seed layer is deposited on the barrier layer. This seed layer may comprise a material such as copper or its alloys. Examples of these include CuAl, CuSn, Culn, CuCd or other materials of the like. The seed layer may be deposited utilizing PVD, CVD or plating.

Next, metals containing carbon nanotubes are electroplated to the seed layer240. In various embodiments, the carbon nanotubes are single wall, arm chair carbon nanotubes, and the electroplating process is a Co-electroplating process. In various embodiments, the electroplating is performed utilizing solutions containing metal ions such as Cu, Ag, Au, Al, Sn, In, Ni, Co, Fe, Cd, Cr, Ru, Rh, Re, Sb, Bi, Pt, Zn, Pd, Mn, Ir, Os, Mo, W, their alloys or other materials of the like. The solution may also contain one or more support electrolyte such as sulfuric acid, sulfonic acid, potassium hydroxide and the like. In particular, the solution further contains (single wall, arm chair) carbon nanotubes suspensions. Carbon nanotubes may be suspended in solvents such as water, ethanol, methanol, ethyleneglycol, and so forth. Suspension can be effectuated by e.g. sonication.

Carbon nanotubes can be also made soluble by their functionalization. For example, the carbon nanotubes may be treated with H2SO4 or HNO3 to create a COOH functional group. This may be followed by treatment with S(O)Cl2/H2N—R—SH to create a C(O)N(H)—R—SH functional group. This may be further treated with a reducing agent such as H2PtCl6 to create carbon nanotubes covered with platinum particles. In an alternative embodiment, the solution additionally comprises complexing agents such as ethylenediaminetetra-acetic acid (EDTA), tartrate, citric acid or other materials of the like. Suitable (single wall, arm chair) carbon nanotube suspensions include, but are not limited to, those available from various vendors such as Carbon Nanotechnologies Inc., of Houston Tex.

After the metal layer is fabricated, chemical mechanical polish (CMP) or electropolish may be utilized to remove excess materials250. Further, a passivation or stop etch layer may be optionally deposited on top of the metallization layer260. In one embodiment, the passivation/etch stop layer may comprise SiN, SiC, electroless cobalt, or other materials of the like.

As needed, the procedures220-260may be repeated to add additional interconnects.

FIG. 3shows a flowchart illustrating a method for creating portions of an integrated circuit design, in accordance with another embodiment. Illustrated is a method for forming an interconnect utilizing electroless plating to deposit a metal layer with carbon nanotubes. As previously, a substrate with active components is formed310. The substrate may then be planerized utilized CMP. Then, deposition of a dielectric layer to facilitate formation of interconnects to interconnect the active components may be performed. Further, dual damascene features may be formed in the dielectric layer by using e.g. operations of lithography and etching320.

As with the previous embodiment, barrier and seed layers may then be deposited330. The barrier layer may comprise a material such as tantalum, tantalum nitride, tantalum silicon nitride, titanium nitride, titanium silicon nitride, tungsten nitride, tungsten silicon nitride, cobalt tungsten phosphide, or other materials of the like. The barrier layer may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or plating.

The seed layer is deposited on the barrier layer. The seed layer may comprise a material made of catalytic material for electroless deposition. Examples of these include copper, cobalt, nickel, gold, platinum, rhodium, ruthenium, silver, palladium, iron, and the like. The seed layer may be deposited utilizing PVD, CVD or plating.

Metals containing carbon nanotubes are electrolessly plated to the seed layer to produce an interconnect layer340. In various embodiments, the carbon nanotubes comprise single wall, arm chair carbon nanotubes, and the electroless plating process comprises a co-electroless plating process. The electroless plating is performed utilizing solutions containing metal ions such as Cu, Ag, Au, Al, Sn, In, Ni, Co, Fe, Cd, Cr, Ru, Rh, Re, Sb, Bi, Pt, Zn, Pd, Mn, Ir, Os, Mo, W, their alloys and the like. The solution may also contain reducing agents, complexing agents and carbon nanotubes suspensions. As discussed previously, various techniques may be utilized to produce the carbon nanotubes suspensions. Reducing agents may comprise compounds such as hyphophosphite, amino-borane, formaldehyde, glyoxylic acid, hydrazine, redox pairs such as Ti3+/Ti4+, Fe2+/Fe3+, or other materials of the like. Complexing agents may comprise compounds such as EDTA, tartrate, citric acid, or other materials of the like.

As previously stated, after the metal layer has been laid down, chemical mechanical polish (CMP) or electropolish may be utilized to remove excess materials350. Deposition of a passivation/etch stop layer may be optionally made on top of the metal layer360. The passivation/etch stop layer may comprise SiN, SiC, electroless cobalt, or other materials of the like. As needed, the procedures discussed above may be repeated to add additional interconnects.

FIG. 4shows a flowchart illustrating a method for creating portions of an integrated circuit design, in accordance with yet another embodiment. Illustrated is a method for forming an interconnect utilizing electrophoresis to deposit a metal layer with carbon nanotubes. As with the previous embodiments, a substrate with active components is formed410. Deposition of a dielectric layer to facilitate formation of interconnects to interconnect the active components is performed. Further, dual damascene features are formed in the dielectric layer by using e.g. operations of lithography and etching420.

As with the previous embodiments, a barrier layer and seed layer are deposited430. The barrier layer may comprise a material such as tantalum, tantalum nitride, tantalum silicon nitride, titanium nitride, titanium silicon nitride, tungsten nitride, tungsten silicon nitride, cobalt tungsten phosphide or other materials of the like. The barrier layer may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or plating.

The seed layer is deposited on the barrier layer. Examples of seed materials include copper, cobalt, nickel, gold, platinum, rhodium, ruthenium, silver, palladium, iron and the like. The seed layer may be deposited utilizing PVD, CVD or plating.

Next, electrophoresis of metal particles utilizing solutions comprising metals particles such as Cu, Ag, Au, Al, Sn, In, Ni, Co, Fe, Cd, Cr, Ru, Rh, Re, Sb, Bi, Pt, Zn, Pd, Mn, Ir, Os, Mo, W, their allows or other materials of the like, including carbon nanotubes, is performed440. In various embodiments, the metal particles are 10 to 50 nanometers. In various embodiments, carbon nanotubes are single wall, arm chair carbon nanotubes. The solution may also comprise ligands making the metal particles and the carbon nanotubes charged. The solution may further comprise support electrolyte such as H2O, ethyleneglycol or other materials of the like. An example of such suitable solutions include, but are not limited to, those provided by ALD Nanosolutions, Inc.

After the electrophoresis of the metal particles containing carbon nanotubes, an annealing process may be applied450. This process is performed to melt the metal particles containing the carbon nanotubes. The process may be performed at a range of temperatures (e.g. 200 to 500 degree C.) for a period from 1 to 200 minutes.

As with the previous embodiments, a CMP or electropolish may be performed to remove excess material460. A passiviation/etch stop layer may optionally be deposited on top of the metal layer470. The above process may be repeated for additional interconnects.

FIG. 5shows a flowchart illustrating a method for creating portions of an integrated circuit design, in accordance with another embodiment. Illustrated is a method for forming an interconnect, utilizing spin-on to deposit a metal layer with carbon nanotubes. As with the previous embodiments, a substrate with active components is formed510. Deposition of a dielectric layer to facilitate formation of interconnects to interconnect the active components may be performed. Further, dual damascene features are formed in the dielectric layer by using e.g. operations of lithography and etching520.

As with the previous embodiments, a barrier layer and a seed layer are deposited530. The barrier layer may comprise a material such as tantalum, tantalum nitride, tantalum silicon nitride, titanium nitride, titanium silicon nitride, tungsten nitride, tungsten silicon nitride, cobalt tungsten phosphide or other materials of the like. The barrier layer may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or plating.

Similarly, as with several previous embodiments, the seed layer is deposited on the barrier layer. The seed layer may comprise a material made of catalytic material for electroless deposition. Examples of these include copper, cobalt, nickel, gold, platinum, rhodium, ruthenium, silver, palladium, iron and the like. The seed layer may be deposited utilizing PVD, CVD or plating.

Spin on of metal particles utilizing solutions comprising metals particles such as Cu, Ag, Au, Al, Sn, In, Ni, Co, Fe, Cd, Cr, Ru, Rh, Re, Sb, Bi, Pt, Zn, Pd, Mn, Ir, Os, Mo, W, their alloys or other materials of the like, including carbon nanotubes, is performed540. In various embodiments, the metal particles are 10 to 50 nanometers in size. In various embodiments, the carbon nanotubes are single wall, arm chair carbon nanotubes. In various embodiments, spin on may be performed at substrate rotation speed of about 20-100 rpm for about 1-5 min at room temperature. An example of such suitable solutions include, but are not limited to, those provided by NSI Corp. The solution may also comprise ligands and carbon nanotubes charged. The solution may further comprise support electrolyte such as H2O, ethyleneglycol or other materials of the like.

After the spin-on of the metal particles containing carbon nanotubes, an annealing process may be applied550. This process is performed to melt the metal particles containing the carbon nanotubes. The process may be performed at a range of temperatures (e.g. 200 to 500 degree C.) for a period from 1 to 200 minutes.

As with the previous embodiments, a CMP or electropolish may be performed to remove excess materials560. A passiviation/etch stop layer may be optionally deposited on top of the interconnect lines570. The above process may be repeated for additional interconnects.

Discussed above are methods of fabricating materials which has the potential of exhibiting high electrical and thermal conductivity and/or high electromigration resistance. The resulting metal structures containing (single wall, arm chair) carbon nanotubes dispersed therein to contribute to the increase of, among other things, electrical conductivity.

FIG. 6illustrates is a block diagram of a system600including at least one component with metal layers containing carbon nanotubes. As shown, the system600includes a processor610and temporary memory620, such as SDRAM and DRAM, on high-speed bus605. High-speed bus is connected through bus bridge630to input/output (I/O) bus615. I/O bus615connects permanent memory640, such as flash devices and fixed disk device, networking interface660and I/O devices650to each other and bus bridge630.

At least one of the components, e.g. processor610, temporary memory620, and so forth, is formed having e.g. interconnect, with metal layers having carbon nanotubes. More over, in various embodiments, the carbon nanotubes are single wall, arm chair, carbon nanotubes. In various embodiments, the metal layers with the carbon nanotubes are formed using one of the earlier described processes.

In various embodiments, system600may be a hand held computing device, a mobile phone, a digital camera, a tablet computer, a laptop computer, a desktop computer, a set-top box, a CD player, a DVD player, or a server.