Examples described herein relate to an apparatus including at least one memory and at least one processor communicatively coupled to the at least one memory, the at least one processor to: allocate a scheduler to an egress port and based on unavailability of an egress port, allocate the scheduler to a second egress port to cause any packet allocated to a transmit queue associated with the scheduler to be transmitted using the second egress port. In some examples, a system receives a packet at a port on a network interface, associates a port group with the packet, determines a receive queue for the packet, and copies the packet to the determined receive queue. The port group can be adjusted to remove the port or to add a second port.

An input/output (I/O) device such as a network interface card (NIC) may couple to a computing platform or host device deployed in server-network edge where the server domain ends and an external network domain begins. A solution to implement switch logic or circuitry at a NIC in these types of environments is through use of a set of lookup tables. The lookup tables may identify a portion of data such as a packet header and then actions may be defined in the lookup table based on the packet header. One or more lookup tables can be assigned for use per port.

DETAILED DESCRIPTION

Link aggregation can include combining or aggregating multiple network connections in parallel. A link aggregation group (LAG) can combine a several physical ports together to make a single data path to provide traffic load sharing among the member ports of the group. See, for example, Link Aggregation Control Protocol (LACP) in IEEE 802.3ad and IEEE 802.1AX-2008. For virtual machines (VMs), implementation of link aggregation can involve a virtual function (VF) being used per port and a teaming driver on top of these VFs in each VM. However, changes in each VM may be needed to support link aggregation, and each VM is to be configured with the underlying network architecture. On the transmit side, in order to avoid the need to expose a VF per port to VMs, a network interface-based implementation for link aggregation may be used. However, in a network interface-based (or hardware-based) solution for link aggregation, a packet could be direct memory access (DMA) copied into the network interface, the network interface calculating a hash and, based on the hash, selecting a port to send the packet. If the selected port was temporarily congested, the network interface will provide deep buffers to hold the packet until the port becomes uncongested.

When implementing single root input/output virtualization (SR-IOV) or Intel® Scalable I/O Virtualization (S-IOV) based virtualization of networking devices, various embodiments separate link aggregation from being performed by a VM, so that a single virtual function (VF) can be used for packet-port assignments, no matter which link is used. Various embodiments manage physical port selection in a way that does not affect the tenant owned VM or involve a VM managing physical port selection. Various embodiments provide for software (e.g., OS or VM) selecting a transmit queue. Various embodiments provide a transmit queue-to-scheduler mapping and scheduler to port mapping, and a scheduler allows or causes packet copying (e.g., direct memory access (DMA)) to the network interface if a mapped port has credits and is not congested. In some cases, for transmit operations, a network interface need not provide larger buffers for storing packets in the event of port congestion or perform load distribution among ports, although the network interface can include any of such features.

In various embodiments, one or more of the following features are provided: forwarding of traffic from multiple ports using a single forwarding table; scheduling of traffic from the host to multiple ports using a load balancing by tying a transmit queue to a scheduler and tying a scheduler to a port; ability to fail over traffic from one port to another when a port fails by migrating a transmit queue to another scheduler or a scheduler to another port; and ability to send control packets to a specific port such as alive packets of Link Aggregation Control Protocol (LACP) packets.

In various embodiments, a transmit queue can reference data traffic that is sent from any port without the VM being involved in such queue-to-port association. To load balance traffic among transmit ports, a PF driver can reallocate a transmit queue from using one port to another port by associating the transmit queue with another transmit scheduler. If control packets are to be transmitted from a particular port, control packets can be assigned to a transmit queue that is tied to using the particular port. Various embodiments provide load balancing based on host load balancing methods such as load balancing or reallocation of transmit queue-to-scheduler or scheduler-to-node.

Various embodiments provide coordination between the physical function (PF) drivers of different ports so that a single PF driver remains active and can control scheduling of transmission from the ports whereas the other PF/PFs becomes dormant. Some embodiments provide for a single PF to manage packet transmission scheduling for ports of the network interface. A network interface LAG can be either setup dynamically with software coordination and triggered by software tools or a static bond of a LAG can be used.

Description turns to example manners of allocating receive queues for received packets.FIG.1illustrates an example system. System100may include a host device101coupled to input/output (I/O) device140. System100can be used at least to receive data from network160using I/O device140. I/O device140can include capability of one or more of: a network interface controller, network interface card, smart network interface, fabric interface, interface to an interconnect or bus, and so forth. In some examples, I/O device140includes a switch manager142. As described in more detail later, switch manager142can assign a switch identification (SwitchID or switchID) or port group identifier to data received at I/O device140. For these examples, the data may be received at a port (e.g., port130-1to port130-4) from among various ports depicted inFIG.1. The assigned switch identifications may then be used as part of a lookup table to determine one or more actions for processing the data at I/O device140(e.g., receive queue assignment, forwarding, cryptographic/security processing, etc.).

I/O device140may be coupled to host device101through various virtual station interfaces (VSIs)111D,112D,113A,114B,115C,116D,117E and118x(‘x’ indicates association with a yet to be established data channel) included in virtual switches (V.S.)141,143,146,147,148, and149. The various VSIs included with these virtual switches may be separately arranged to couple to virtual machines (VMs)111-118as shown inFIG.1and may enable data (e.g., in the form of data packets or data frames) to be received from or sent/transmitted to VMs111-118. A VSI can include or refer to a port in a virtual switch. A VSI can refer to or include a VF or an emulated interface used by a virtual machine manager (VMM).

For these examples, VMs111-118may be configured or arranged to be implemented using computing resources maintained at host device101. Any number of virtual switches may be associated with any number of VSIs to communicatively couple to any number of VMs and/or virtual machine managers (hypervisors). Note that reference to a VM can refer to any virtualized execution environment. A virtualized execution environment can include at least a virtual machine, process containers, machine containers, or application processes. A virtual machine (VM) can be software that runs an operating system and one or more applications. A VM can be defined by specification, configuration files, virtual disk file, non-volatile random access memory (NVRAM) setting file, and the log file and is backed by the physical resources of a host computing platform. A VM can be an OS or application environment that is installed on software, which imitates dedicated hardware. The end user has the same experience on a virtual machine as they would have on dedicated hardware. Specialized software, called a hypervisor, emulates the PC client or server's CPU, memory, hard disk, network and other hardware resources completely, enabling virtual machines to share the resources. The hypervisor can emulate multiple virtual hardware platforms that are isolated from each other, allowing virtual machines to run Linux® and Windows® Server operating systems on the same underlying physical host.

A container can be a software package of applications, configurations and dependencies so the applications run reliably on one computing environment to another. Containers can share an operating system installed on the server platform and run as isolated processes. A container can be a software package that contains everything the software needs to run such as system tools, libraries, and settings. Containers are not installed like traditional software programs, which allows them to be isolated from the other software and the operating system itself. Isolation can include access of memory by a particular container but not another container. The isolated nature of containers provides several benefits. First, the software in a container will run the same in different environments. For example, a container that includes PHP and MySQL can run identically on both a Linux computer and a Windows machine. Second, containers provide added security since the software will not affect the host operating system. While an installed application may alter system settings and modify resources, such as the Windows registry, a container can only modify settings within the container.

According to some examples, as shown inFIG.1, a logical port (L-port)141-D is shown as included in virtual switch141. L-port141-D may serve as a logical port capable of being coupled to a data channel D. As mentioned more below, data channel D may be arranged to route data between VM111and VM112. The routing of the data, for example, may be through respective VSIs111and112.

Communication links150-1to150-4may couple network elements included in network(s)160to host device101via respective ports130-1to130-4. In some examples, ports130-1to130-4may represent a physical connector or port via which data (e.g., in the form of data packets or frames) may be received at or sent/transmitted from I/O device140. I/O device140is also shown as including a port extender144. According to some examples, as shown inFIG.1, port extender144may include E-port144-1C and E-port144-2D. For these examples, port extender144may enable physical port103-2to be extended to at least two extender/logical ports to route data to/from virtual switches146and147via E-port144-1C and E-port144-2D.

According to some examples, I/O device140may be configured to operate in accordance with or implement at least some aspects of a proposed IEEE standard (including progenies and variants) having the title of IEEE Standard for Local and metropolitan area networks: Virtual Bridged Local Area Networks: Bridge Port Extension”, IEEE Std 802.1BR-2012, July 2012 (hereinafter “IEEE 802.1BR”). For these examples, I/O device140may also be configured to operate in compliance with or implement at least some aspects of IEEE 802.1Qbg-2012 (including progenies and variants). As part of the implementation of IEEE 802.1Qbg or IEEE 802.1BR, various data channels may be established for routing data either locally between virtual machines on host device101or globally to network elements located at network(s)160.

In some examples, various established data channels are identified as data channels A-E. For these examples, the various VSIs coupled to VMs111to116are associated with data channels A, B, C, D or E with the exception of VSI118xcoupled to virtual machine118. VSI118x, in some examples, may represent a VSI yet to be associated with an established data channel. As mentioned more below, data routed through VSI118xmay include control information used to eventually establish a data channel with VSI118xor administer a data channel. For these instances, a default identification or tag for this control data may be locally generated or originated at I/O device140and then used to assign a switch identification to the data.

According to some examples, data channels may be used to either route data between VMs located at host device101or to route data to between VMs and network elements located at network(s)160. For these example, identification information for the data routed via these data channels may include a tag described in IEEE 802.1Qbg or IEEE 802.1BR. The tag may be a Service tag (S-tag) or a Bridge Port Extension tag (E-tag). In some examples, the S-tag or E-tag may be identification information to indicate that data having one of these tags may be associated with a given channel. These tags may be globally generated or originated from elements remote to I/O device140such as network elements at network(s)160.

In some examples, switch manager142may include logic and/or features arranged to receive data at I/O device140. The data may be associated with a VSI and may have identification information (e.g., an S-tag or E-tag) to indicate an association with channel A. As shown inFIG.1, a VSI coupled to or associated with channel A may be VSI113A. For these examples, VSI113A may be arranged or configurable to couple to VM113and also arranged to route data from VM113through virtual switch143. According to some examples, since the data is routed via a data channel coupled to network(s)160, the data may be considered as being received at the physical port130-1coupled to channel A.

Switch manager142may include logic and/or features arranged or configured to assign a switch identification number to the data based on the identifier assigned to port130-1, identification information for the data (e.g., tag information), and the originator of at least a portion of the identification information. The switch identification information may then be used by logic and/or features of switch manager142as part of a lookup table to determine one or more actions for processing the data at I/O device140.

In some other examples, data having identification information to indicate an association to channel A may be received at I/O device140via port130-1. The data received through port130-1may then be routed via channel A to virtual switch143. As mentioned previously, VSI113A may couple to VM113. For these examples, VSI113A may be arranged to cause the data to be sent or transmitted to VM113. For these other examples, switch manager142may include logic and/or features arranged or configured to assign a switch identification number to the data based on an identifier assigned to the I/O device140receiving port (port130-1), identification information for the data, and the originator of at least a portion of the identification information. The switch identification information may then be used by logic and/or features of switch manager142as part of a lookup table to determine one or more actions for processing the data at I/O device140.

In some examples, data may be received at a port included in I/O device140that may be routed between VMs111and112via data channel D at virtual switch141. Data received at L-port141-1D through VSI111D from VM111may have a destination of VM112. For these examples, identification information for the data received at port141-1D may include a data channel identification number originated at I/O device140(e.g., at virtual switch141). The data channel D identification number may be similar to the format of an S-tag or E-tag. Switch manager142may include logic and/or features arranged or configured to assign a switch identification number to the data based on an identifier assigned to the port141-1D, the locally generated channel D identification number, and an indication that the originator of at least a portion of the identification information was at I/O device140. The switch identification information may then be used by logic and/or features of switch manager142as part of a lookup table to determine one or more actions for processing the data at the I/O device140. In some examples, a single lookup table can be used for a receive port to switchID (port group) association and another table can be used for switchID to receive queue association.

In some examples, virtual switch141may be configured to operate in accordance with IEEE 802.1Qbg and function as a Virtual Ethernet Bridge (VEB).

In some examples, communication links150-1to150-4may communicatively couple I/O device140to network(s)160via ports130-1to130-4, respectively. Communication links150-1to150-4may include various types of wired, wireless or optical communication mediums. For these examples, communication links150-1to150-4may be operated in accordance with one or more applicable communication or networking standards in any version. The communication or networking standards may include, but are not limited to, IEEE 802.1Qbg or IEEE 802.1BR.

FIG.2Adepicts an example system for processing received packets. Network interface250includes one or more ports (e.g., ports252-0to252-1) that can be used to process receive packets from a network medium (e.g., network160), fabric medium or other wired or wireless medium. Other numbers of ports can be supported. According to some embodiments, a table254can be used for multiple physical ports to associate a switchID, LAG, or port group of a packet with port. Table254can be a single copy accessible to interface250for all ports instead of every port having its own lookup table to identify a switchID, LAG or port group of a received packet. However, in some examples, any port (or group of ports) can have any associated table to identify a switchID, LAG or port group of a received packet.

In some examples, a Switch ID represents a port group number of a port group. Table254can be used to merge multiple network ports to a single switching context to allow for usage of a single table for forwarding decisions from multiple ports. Using a single routing table, table254can use a mapping of one or more ports to a Switch ID. For example, Switch ID allocation and lookup described in U.S. Pat. No. 9,280,367 can be used to associate a port with a port group. U.S. Pat. No. 9,280,367 is incorporated by reference in its entirety. In some examples, table254can be used to associate one or more ports with a Switch ID. For example, packets received on port252-0can be assigned a Switch ID=0 whereas packets received on port252-1can be assigned a Switch ID=1.

For example, table254can be associated with 1, 2, 4, 8 or more ports. In this example, one or more ports can be associated with a SwitchID or port group number.

PortSwitchID0011213043. . .. . .74
In this example, ports 0 and 3 are associated with SwitchID of 0; ports 1 and 2 are associated with SwitchID of 1; port 4 is associated with SwitchID of 3; and port 7 is associated with SwitchID of 4.

For example, an administrator can tie one or more ports to a Switch ID using a PF driver214. PF driver214can allocate physical ports to a Switch ID and cause an update of table254. Tying or association of one or more ports to a Switch ID can occur to provide traffic load balancing among ports or receive (Rx) queues (e.g., hashing across all receive queues to evenly balance received traffic across receive (Rx) queues). PF driver214can program the switch tables partially or in totality and can program rules to direct packet traffic to an Rx queue. PF driver214can expose (e.g., permitting configuration or use of) a network interface to an OS or a VM.

For received data plane and control plane packets, table254can be used to identify a port group identifier (e.g., Switch ID or switch identification) for a packet based on a port through which the packet was received. A data plane, which is also referred to as forwarding plane or user plane, carries data packet traffic such as application data. In a network element (e.g., a hardware switch or a hardware router), the data plane is the part of the architecture that decides what actions to perform on received packets at an ingress interface. A control plane and control plane packets control signaling traffic and routing of a network element. Control plane traffic can include flow control traffic, rate limiting requests, alive packets of Link Aggregation Control Protocol (LACP) packets, and so forth.

Instead of, or in addition to, a received packet's physical port number and packet's media access control (MAC) address being used to identify a receive queue associated with a virtualized execution environment that is to process a received packet, a port group number (e.g., Switch ID) and media access control (MAC) address of the received packet can be used to determine a virtualized execution environment that is to process a received packet. For control plane and data plane packets, unified lookup table256can associate a virtualized execution environment with a MAC address and switchID.

For example, a format of table256can be as follows.

For received control packets, a received port number can be provided for use of table258to differentiate control packets per physical port. Using control packet mapping table258, a received control plane packet can be identified using special rules (e.g., EtherType=LACP) and forwarded using the receive port of the received control plane packet as part of a lookup rule to a specific receive queue per PF. In some examples, for control plane packets, a received port number is used to associate received traffic with a PF driver. The control packet can be copied using a direct memory access (DMA) engine from interface250to a buffer associated with the PF driver. For example, a format of table258can be as follows.

PortRx Queuenumberidentifier000. . .. . .711
Any number of ports or receive queues can be used.

In host200, kernel212can be part of a host operating system stored in memory204or a cache and executed by one or more of processors202. PF driver214and bonding driver216can be invoked or called by kernel212. In some examples, bonding driver216takes multiple physical ports and exposes multiple ports as a single physical port to a networking stack. Control interface218-0and control interface218-1can include or access a queue to receive control packets routed by control packet mapping table258through switch260.

Rx queue210can receive packets routed by table256through switch260. Virtualized execution environments206can run an operating system, applications, and VF driver208. By use of VF driver208, virtualized execution environments206can access content of Rx queue210.

Processors202can be an execution core or computational engine that is capable of executing instructions. A core can have access to its own cache and read only memory (ROM), or multiple cores can share a cache or ROM. Cores can be homogeneous and/or heterogeneous devices. Any type of inter-processor communication techniques can be used, such as but not limited to messaging, inter-processor interrupts (IPI), inter-processor communications, and so forth. Cores can be connected in any type of manner, such as but not limited to, bus, ring, or mesh. Processors202may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.), including the instruction(s) described herein. Memory204can be any volatile or non-volatile memory.

Some embodiments of the system support and use either or both of SR-IOV or S-IOV. A SR-IOV extension enables multiple virtualized execution environments (e.g., system images) to share PCIe hardware resources under a single-node system (e.g., single root complex). SR-IOV is compatible at least with specifications available from Peripheral Component Interconnect Special Interest Group (PCI SIG) including specifications such as Single Root I/O Virtualization and Sharing specification Revision 1.1 (2010) and variations thereof and updates thereto. A SR-IOV device provides a bus device function (BDF) identifier for a virtual function within a PCIe hierarchy; a unique memory address space for a virtual function (VF) within a PCIe hierarchy; a unique error logging and escalation scheme; a unique MSI/MSI-X capability for each VF within a PCIe hierarchy; and power-management capabilities for each VF within a PCIe hierarchy. In addition, SR-IOV provides the capability to discover and configure virtualization capabilities which include a number of VFs that the PCIe device will associate with a device and the type of base address register (BAR) mechanism supported by the VFs.

FIG.2Bdepicts an allocation of control and data packet queues. In some examples, control packet queues and data packet queues can be allocated for a port. For example, ports270-0to270-2can receive packets and tables272can be used to associate a receive queue with a received packet. For example, techniques described earlier to associate a receive queue with a receive port or port group identifier can be used. A packet descriptor can be completed and stored in a receive queue that indicates a receive port number and characteristics of a packet. In the queues, a descriptor that references a received packet storage location and header fields can be stored. A descriptor can include memory location or index identifying where received packet bytes stored, length of the packet, and so forth. For example, the descriptor can be processed by a driver or operating system to provide access to data in a received packet to an application. In some examples, control packet queue274-0and data packet queue276-0can be allocated for a port270-0; control packet queue274-1and data packet queue276-1can be allocated for a port270-1; and control packet queue274-2and data packet queue276-2can be allocated for a port270-2.

FIG.2Cdepicts an example of a control packet queue and data packet queue allocated per group of ports. In some examples, control packet queue280and data packet queue282can be allocated for descriptors associated with received packets through ports270-0to270-2. Tables272can be configured to associate a control or receive queue with a received packet according to embodiments described herein.

Description next turns to an example manner to select a port for a packet transmission.FIG.3depicts a simplified block diagram of examples of packet scheduler configurations. Note that host302and interface350can use any of the hardware and/or software elements described herein. Virtualized execution environment (VEE304-0to304-2) running an application (not shown) can have content (e.g., data) available for transmission. If VEEs (or CPUs that run the VEEs) have statistically similar network utilization, then distributing the traffic from the different CPUs (or cores) to different ports evenly (e.g., using a hash calculation) can provide load balancing of port usage. As the traffic of a VEE (or CPU) is assigned to a specific Tx queue, the traffic of different queues can be distributed to different ports. According to some embodiments, load balancing or other allocations of packets for transmission through a port can occur by allocation of host schedulers to TX queues and/or host schedulers to particular port schedulers.

In this example, VEEs304-0to304-2can have associated transmit queues. VF drivers308-0to308-2can provide for transfer of packet data for transmission from transmit queues of respective VEE304-0to304-2. Host schedulers312-0,312-1,314-0, and314-1can select packets for transmission from transmit (TX) queues306-0to306-6and control packet queues310-0to310-1. In some examples, host schedulers312-0,312-1,314-0, and314-1can execute in an operating system (OS) kernel or in user space. Note that a Tx queue and control packet queue can store descriptors that are associated with packets that are to be transmitted. In this particular example configuration, schedulers312-0and312-1and control packet queue310-0provide available packets to scheduler314-0. Scheduler312-0selects available packets from Tx queues306-0and306-1whereas scheduler312-1selects available packets from Tx queues306-2and306-3. Tx queues306-4to306-6and control packet queue310-1provide available packets to scheduler314-1.

For example, a PF driver320can apply an equal weighting scheme (e.g., hash) to select a port for transmission for a packet. Use of a hash can provide for load balancing of use of ports354-0or port354-1. For the sake of illustration, merely two ports are shown, but other numbers of physical ports can be used. A hash calculation can be available in an operating system (OS) or available to a VEE.

PF driver320can load balance use of ports354-0and354-1by associating a tier or arrangement of host schedulers with port schedulers352-0and352-1. According to some embodiments, assignment of a Tx queue to a transmit port can be achieved by one or more PF drivers320tying a Tx queue to a host scheduler and tying a host scheduler to a port scheduler associated with a transmit (egress) port. To dissociate port assignment away from VEEs, PF driver320can tie one or more Tx queues of a VEE to a host scheduler. A host scheduler node can decide which Tx queue to schedule to a port for transmission based on bandwidth available at a port. The scheduler node can fetch a descriptor from a Tx queue and cause the associated data to be copied to interface350. Note the concept of queue described here can be either a stateless LAN queue, an RDMA queue set, an NVMe-oF queue, or any other type of traffic queue.

When a port is unavailable (e.g., fails, is congested, or it not to be used), PF driver320can redirect some or all the Tx queues associated with the unavailable port to another port node associated with an active port(s). In case of port failure, all host schedulers move to a port scheduler associated with other active port(s). In case of congestion, a part of the host schedulers (and associated Tx queue(s)) can move to a port scheduler node associated with other active port(s). Port failure or unavailability can be detected by a teaming driver in some examples. Port failure can occur for example if alive loopback packets are not received (no response).

PF driver320can manage Tx queue to scheduler node association using a table stored in memory. In some examples, a table can identify associations between a host scheduler, transmit queues, port schedulers and port.

In some examples, control plane traffic can be allocated to queues310-0and310-1designated as control queues. In some examples, transmitted control plane traffic does not fail over to another port as control traffic is port specific. If a port fails, Tx control traffic on that port is stopped. PF driver320can tie control packets to an egress port by use of a control packet queue310-0and310-1, which in some examples is not migrated to another port scheduler. But in some embodiments, data plane traffic can be failed, migrated, or moved to another port.

When SR-IOV are used, PF driver320can provide connectivity between interface350and host302. A VEE can request PF driver320for queue creation. In interface350, PF driver320can program context and queue, size of queue, type of descriptors, location of data to be transmitted in memory.

For example, in this configuration, host schedulers314-0and314-1can identify prospective packets for transmission (e.g., using descriptors) to respective port schedulers352-0and352-1. Port schedulers352-0and352-1can schedule packet transmission through respective ports354-0and354-1. In other configurations, multiple host schedulers can be associated with a particular port scheduler.

According to some embodiments, a VEE does not manage or track what port data traffic is sent through. PF driver320, a firmware/virtual machine manager (VMM) or OS can perform Tx queue migration without the VEE intervening. In some examples, network interface350does not provide load balancing of traffic through ports or migration of packets from a congested port to a non-congested port, although network interface350can perform such feature. One or more Tx queues associated with a host scheduler node can be associated with another host scheduler node and a host scheduler node can schedule transmission using another port scheduler. To provide load balancing or in the event of port failure or congestion, a host scheduler node can be associated with another port. Accordingly, a queue or scheduler node can be migrated to use another port without a VEE or its application managing the migration or without providing notification of the migration. For migration or movement of a Tx queue to another port, the PF driver320updates context to indicate a Tx queue is moved to another host scheduler node or port scheduler node. PF driver320can determine which host scheduler node is permitted to use a particular egress port. In some examples, multiple PF drivers are used, where a port has an associated PF driver whereby PF #0 can manage port354-0whereas PF driver #1 manage port354-1.

A queue pause and resume feature can be used when moving a queue or scheduler tree to another port or moving a queue to another scheduler tree. When a Tx queue is moved to another scheduler, PF driver320informs a VEE associated with a Tx queue to pause posting to a particular Tx queue while the Tx queue is moved to another scheduler node. After the Tx queue is moved to another scheduler node, PF driver320allows the VEE to resume populating the moved Tx queue. In some cases, for a queue migration, network interface350performs outstanding requests and quiesces a Tx queue (does not transmit packets received as a movement or migration occurs) until the Tx queue is tied to another port so that a VEE is uninvolved with queue migration.

If interface350has flexibility to expose a single PF driver by making some network interface device configuration changes in non-volatile memory (NVM) and there is no need for a dynamic Tx queue aggregation or disaggregation using multiple PF drivers, a single PF driver can access information about the different scheduler trees or nodes associated with each port and the link information for each port (e.g., from firmware). PF driver320can migrate Tx queues among scheduler nodes to manage packet transmit load on one or more ports.

Dynamic link aggregation can occur to form association between ports and a port group or modify (e.g., add or remove) ports that are part of a port group. In a case where a dynamic link aggregation is to be used or where interface350does not support exposing a single PCIe device or single PF driver across all egress ports, various handoff embodiments can be used. Any PF driver can trigger link aggregation and cause other PF driver(s) to go dormant in terms of exposing (e.g., permitting configuration or use of) a network interface into the OS or a VEE, and the PF driver that triggered link aggregation become the sole or main PF driver. A channel between PF drivers using the kernel or mailboxes in interface350to handoff configuration information between PF drivers. The PF driver that acts as the main can configure a single switch for interface350and access function information regarding a scheduler tree, link information and so forth of the other PF driver(s) about the port(s) that the other PF driver(s) were connected to. In case of a port becoming unavailable (e.g., congested, failed, and so forth), the main PF driver accesses port information and can reprogram the per Tx queue to scheduler node association with a Tx queues Disable/Enable since the main PF driver controls that mapping. A main PF can configure Tx queues associated with separate scheduler nodes tied to separate ports to be associated with the same scheduler node and the same port. The main PF can also choose to expose control interfaces per port into the OS and direct just certain traffic to the control interfaces using special rules (e.g., EtherType is LACP) and the port-to-interface association.

Note that in some examples, port schedulers are not used and host schedulers are associated directly with ports. In other examples, host schedulers are not used and transmit queue are associated with port schedulers, which are associated directly with ports.

Next description turns to an example of a transmit queue migration to another host scheduler.FIG.4Adepicts an example where transmit queue406-0is associated with host scheduler410-0and transmit queue406-1is associated with host scheduler410-1. Host scheduler410-0is associated with port scheduler452-0whereas host scheduler410-1is associated with port scheduler452-1. Port scheduler452-0schedules packet transmission from port454-0whereas port scheduler452-1schedules packet transmission from port454-1. In this example sequence, port454-0becomes congested or fails.

FIG.4Bdepicts an example of migration of a TX queue406-0from a scheduler410-0to a scheduler410-1for scheduling using port scheduler452-1through port454-1. TX queue406-0was formerly associated with scheduler410-0and PF driver #1 associates TX queue406-0with scheduler410-1for example because of a failure or congestion of port454-0. Scheduler410-1is tied to transmit through port454-1through scheduler452-1and packets associated with TX queue406-0and TX queue406-1transmit using port454-1. In some examples, changing to use of another port (e.g., port454-1) can occur separate, independent, or without management or request by VEE402. VEE402can continue to request packet transmission from TX queue406-0without requesting or requiring use of a particular port.

FIG.4Cdepicts an example of migration of a host scheduler410-0to port scheduler452-1. In this example, instead of migrating transmit queue406-0to scheduler410-1, scheduler410-0(through which packets associated with transmit queue406-0are made available for transmission) is associated with port scheduler452-1. PF driver #1 can associate scheduler410-1with scheduler452-1. Accordingly, port scheduler452-1can schedule packets for transmission from TX queues406-0and406-1from port454-1.

FIG.5depicts a process that can be used to determine a receive queue for received packets at an interface. At502, a port group can be associated with a received packet. For example, a look-up table of switchIDs can be used to find a port group identifier associated with an ingress port on which a packet was received. In some examples, the port group associated with the port group identifier includes one or more ports and the port group is adjustable to include or remove any port. At504, a determination can be made of a virtualized execution environment (VEE) to process a received data packet based on a received packet's media access control (MAC) address and port group identifier. For example, a look-up-table can be used to find a VEE associated with a switchID and MAC address. At506, a determination can be made for a control plane queue for control plane packets. For example, the control plane packets can be allocated to a queue associated with an ingress port.

At508, the received data packet can be allocated for processing by a receive queue of the determined VEE. For example, a receive packet buffer can receive a copy of the data packet allocated to the VEE using a direct memory access (DMA) copy operation. At510, a received control plane packet can be copied to a determined control plane queue.

FIG.6depicts an example process to allocate a transmit queue to an output port. At602, a scheduler is associated with an egress port. For example, a PF driver can associate the scheduler with a transmit port. At604, a transmit queue can be associated with a scheduler. For example, a PF driver can associate the transmit queue with a host scheduler. The transmit queue can be used by a virtualized execution environment to store descriptors associated with packets available for transmission. At606, a determination is made as to whether an egress port is to be deallocated. For example, a transmit port can be deallocated if it fails or is congested. In addition, or alternatively,606can include a determination of whether queue should be disassociated from a port scheduler node. If the egress port is to be deallocated or a queue should be disassociated from a port scheduler node,608can follow. If the egress port is not to be deallocated or a queue is not to be disassociated from a port scheduler node,610can follow.

At608, any transmit queue associated with a deallocated egress port can be assigned to another scheduler for allocation to another egress port. For example, a PF driver can assign the transmit queue associated with a deallocated egress port to another port scheduler where the another port scheduler is associated with an active egress port. The active egress port can be selected based on having available transmit bandwidth. In some examples, assigning a queue to another port can involve a network interface transmitting packets associated with the queue before the queue is to be migrated but not fetching packets added to the queue while the queue is migrated. In some examples, assigning a queue to another port can involve halting allowing a virtualized execution environment to allocate packets for transmission to the transmit queue until after the allocation to the another transmit port completes. Note that in some examples, re-assigning a transmit queue to another port scheduler can involve associating a host scheduler associated with the transmit queue to another port scheduler.

Action610can follow608. At610, the port scheduler can scheduler packets for transmission from its active egress port.

Note that in other examples, merely one scheduler layer is used and migration of a transmit queue to another port involves migrating the transmit queue to another scheduler.

FIG.7depicts a system. The system can use embodiments described herein to schedule packets for transmission or identify a receive queue for a received packet. System700includes processor710, which provides processing, operation management, and execution of instructions for system700. Processor710can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware to provide processing for system700, or a combination of processors. Processor710controls the overall operation of system700, and can be or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.

In one example, system700includes interface712coupled to processor710, which can represent a higher speed interface or a high throughput interface for system components that needs higher bandwidth connections, such as memory subsystem720or graphics interface components740, or accelerators742. Interface712represents an interface circuit, which can be a standalone component or integrated onto a processor die. Where present, graphics interface740interfaces to graphics components for providing a visual display to a user of system700. In one example, graphics interface740can drive a high definition (HD) display that provides an output to a user. High definition can refer to a display having a pixel density of approximately 100 PPI (pixels per inch) or greater and can include formats such as full HD (e.g., 1080p), retina displays, 4K (ultra-high definition or UHD), or others. In one example, the display can include a touchscreen display. In one example, graphics interface740generates a display based on data stored in memory730or based on operations executed by processor710or both. In one example, graphics interface740generates a display based on data stored in memory730or based on operations executed by processor710or both.

Memory subsystem720represents the main memory of system700and provides storage for code to be executed by processor710, or data values to be used in executing a routine. Memory subsystem720can include one or more memory devices730such as read-only memory (ROM), flash memory, one or more varieties of random access memory (RAM) such as DRAM, or other memory devices, or a combination of such devices. Memory730stores and hosts, among other things, operating system (OS)732to provide a software platform for execution of instructions in system700. Additionally, applications734can execute on the software platform of OS732from memory730. Applications734represent programs that have their own operational logic to perform execution of one or more functions. Processes736represent agents or routines that provide auxiliary functions to OS732or one or more applications734or a combination. OS732, applications734, and processes736provide software logic to provide functions for system700. In one example, memory subsystem720includes memory controller722, which is a memory controller to generate and issue commands to memory730. It will be understood that memory controller722could be a physical part of processor710or a physical part of interface712. For example, memory controller722can be an integrated memory controller, integrated onto a circuit with processor710.

In one example, system700includes interface714, which can be coupled to interface712. In one example, interface714represents an interface circuit, which can include standalone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, couple to interface714. Network interface750provides system700the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface750can include an Ethernet adapter, wireless interconnection components, cellular network interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces. Network interface750can transmit data to a device that is in the same data center or rack or a remote device, which can include sending data stored in memory. Network interface750can receive data from a remote device, which can include storing received data into memory. Various embodiments can be used in connection with network interface750, processor710, and memory subsystem720. Various embodiments of network interface750use embodiments described herein to receive or transmit timing related signals and provide protection against circuit damage from misconfigured port use while providing acceptable propagation delay.

In one example, system700includes one or more input/output (I/O) interface(s)760. I/O interface760can include one or more interface components through which a user interacts with system700(e.g., audio, alphanumeric, tactile/touch, or other interfacing). Peripheral interface770can include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to system700. A dependent connection is one where system700provides the software platform or hardware platform or both on which operation executes, and with which a user interacts.

In one example, system700includes storage subsystem780to store data in a nonvolatile manner. In one example, in certain system implementations, at least certain components of storage780can overlap with components of memory subsystem720. Storage subsystem780includes storage device(s)784, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, or optical based disks, or a combination. Storage784holds code or instructions and data786in a persistent state (i.e., the value is retained despite interruption of power to system700). Storage784can be generically considered to be a “memory,” although memory730is typically the executing or operating memory to provide instructions to processor710. Whereas storage784is nonvolatile, memory730can include volatile memory (i.e., the value or state of the data is indeterminate if power is interrupted to system700). In one example, storage subsystem780includes controller782to interface with storage784. In one example controller782is a physical part of interface714or processor710or can include circuits or logic in both processor710and interface714.

FIG.8depicts an environment800includes multiple computing racks802, each including a Top of Rack (ToR) switch804, a pod manager806, and a plurality of pooled system drawers. Generally, the pooled system drawers may include pooled compute drawers and pooled storage drawers. Optionally, the pooled system drawers may also include pooled memory drawers and pooled Input/Output (I/O) drawers. In the illustrated embodiment the pooled system drawers include an Intel® Xeon® processor pooled computer drawer808, and Intel® ATOM™ processor pooled compute drawer810, a pooled storage drawer812, a pooled memory drawer814, and a pooled I/O drawer816. Each of the pooled system drawers is connected to ToR switch804via a high-speed link818, such as a 40 Gigabit/second (Gb/s) or 100 Gb/s Ethernet link or a 100+ Gb/s Silicon Photonics (SiPh) optical link. In one embodiment high-speed link818comprises an 800 Gb/s SiPh optical link.

Multiple of the computing racks802may be interconnected via their ToR switches804(e.g., to a pod-level switch or data center switch), as illustrated by connections to a network820. In some embodiments, groups of computing racks802are managed as separate pods via pod manager(s)806. In one embodiment, a single pod manager is used to manage all of the racks in the pod. Alternatively, distributed pod managers may be used for pod management operations.

Environment800further includes a management interface822that is used to manage various aspects of the environment. This includes managing rack configuration, with corresponding parameters stored as rack configuration data824.

In an example, environment800can be implemented using interconnected compute sleds of processors, memories, storages, network interfaces, and other components.

FIG.9depicts a network interface that can use embodiments or be used by embodiments. The network interface can use embodiments described herein in connection with various embodiments for receive queue selection and packet transmit scheduling. Network interface900can include transceiver902, processors904, transmit queue906, receive queue908, memory910, and bus interface912, and DMA engine926. Transceiver902can be capable of receiving and transmitting packets in conformance with the applicable protocols such as Ethernet as described in IEEE 802.3, although other protocols may be used. Transceiver902can receive and transmit packets from and to a network via a network medium (not depicted). Transceiver902can include physical layer (PHY) circuitry914and media access control (MAC) circuitry916. PHY circuitry914can include encoding and decoding circuitry (not shown) to encode and decode data packets according to applicable physical layer specifications or standards. MAC circuitry916can be configured to assemble data to be transmitted into packets, that include destination and source addresses along with network control information and error detection hash values. MAC circuitry916can be configured to process MAC headers of received packets by verifying data integrity, removing preambles and padding, and providing packet content for processing by higher layers.

Processors904can be any a combination of a: processor, core, graphics processing unit (GPU), field programmable gate array (FPGA), application specific integrated circuit (ASIC), or other programmable hardware device that allow programming of network interface900. For example, processors904can provide for allocation or deallocation of intermediate queues. For example, a “smart network interface” can provide packet processing capabilities in the network interface using processors904.

Packet allocator924can provide distribution of received packets for processing by multiple CPUs or cores using timeslot allocation described herein or RSS. When packet allocator924uses RSS, packet allocator924can calculate a hash or make another determination based on contents of a received packet to determine which CPU or core is to process a packet.

Interrupt coalesce922can perform interrupt moderation whereby network interface interrupt coalesce922waits for multiple packets to arrive, or for a time-out to expire, before generating an interrupt to host system to process received packet(s). Receive Segment Coalescing (RSC) can be performed by network interface900whereby portions of incoming packets are combined into segments of a packet. Network interface900provides this coalesced packet to an application.

Direct memory access (DMA) engine926can copy a packet header, packet payload, and/or descriptor directly from host memory to the network interface or vice versa, instead of copying the packet to an intermediate buffer at the host and then using another copy operation from the intermediate buffer to the destination buffer.

Memory910can be any type of volatile or non-volatile memory device and can store any queue or instructions used to program network interface900. Transmit queue906can include data or references to data for transmission by network interface. Receive queue908can include data or references to data that was received by network interface from a network. Descriptor queues920can include descriptors that reference data or packets in transmit queue906or receive queue908. Bus interface912can provide an interface with host device (not depicted). For example, bus interface912can be compatible with peripheral connect Peripheral Component Interconnect (PCI), PCI Express, PCI-x, Serial ATA (SATA), and/or Universal Serial Bus (USB) compatible interface (although other interconnection standards may be used).

FIG.10depicts an example switch. Various embodiments can be used in or with the switch ofFIG.10to provide receive queues or packet transmit scheduling. Switch1004can route packets or frames of any format or in accordance with any specification from any port1002-0to1002-X to any of ports1006-0to1006-Y (or vice versa). Any of ports1002-0to1002-X can be connected to a network of one or more interconnected devices. Similarly, any of ports1006-0to1006-X can be connected to a network of one or more interconnected devices. Switch1004can decide which port to transfer packets or frames to using a table that maps packet characteristics with an associated output port. For example, match-action tables can be used whereby a hash of a portion of a packet is used as an index to find an entry. In addition, switch1004can perform packet replication for forwarding of a packet or frame to multiple ports and queuing of packets or frames prior to transfer to an output port. Some embodiments implement hash-lookup in P4 programing language, which is a programming language designed to allow programming of packet forwarding in data-planes. In contrast to general purpose language such as C or python, P4 is domain-specific language with a number of constructs optimized around network data forwarding.

In some examples, network interface and other embodiments described herein can be used in connection with a base station (e.g., 3G, 4G, 5G and so forth), macro base station (e.g., 5G networks), picostation (e.g., an IEEE 802.11 compatible access point), nanostation (e.g., for Point-to-MultiPoint (PtMP) applications), on-premises data centers, off-premises data centers, edge network elements, fog network elements, and/or hybrid data centers (e.g., data center that use virtualization, cloud and software-defined networking to deliver application workloads across physical data centers and distributed multi-cloud environments).

Some examples include: a method of receiving a packet from a port on a network interface; determining a receive queue for the packet based at least on a port group associated with the packet, wherein the port group is associated with one or more ports; and copying the packet to the determined receive queue. Any method can include: adjusting the port group to add a second port; receiving a second packet at the second port on the network interface; determining that the second packet is associated with the port group; and copying the second packet to the receive queue. Any method can include: receiving a control packet from a first port; associating the first port with a physical function driver; and copying the control packet to a control packet receive queue associated with the physical function driver. Any method can include: identifying the first port as receiving the control packet in a descriptor; receiving a second control packet on a second port; identifying the second port as receiving the second control packet in a second descriptor; and copying the second control packet to the control packet receive queue.

Some examples include at least one non-transitory computer-readable medium, comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to: allocate a transmit queue to a first scheduler; allocate the first scheduler to a first port; and in response to identification of the first port as not available, allocate the first scheduler to a second port. In some examples, the instructions comprise part of a physical function driver. In some examples, selection of the second port is based on the second port having spare transmit bandwidth. In some examples, a virtualized execution environment is to allocate a packet to the transmit queue. In some examples, identification of the first port as not available comprises the first port has failed or is congested. In some examples, allocation the first scheduler to a second port occurs independent from a virtual machine managing the allocation.

Some examples include a system comprising: a network interface; at least one memory; and at least one processor communicatively coupled to the network interface and the at least one memory, the at least one processor to: modify an egress port associated with a transmit queue independent of a virtualized execution environment that provides packets to the transmit queue and assign a received packet to a destination queue based at least in part on a port group identifier, wherein the port group identifier is associated with one or more ports. In some examples, modify the egress port, the at least one processor is to assign a scheduler associated with the transmit queue to another egress port. In some examples, at least one processor is to execute a driver to allocate the scheduler to another egress port.

Example 1 includes an apparatus comprising: at least one processor to: execute a physical function (PF) driver to change an egress port used by a virtualized execution environment to transmit packets toward another egress port; and permit the virtualized execution environment to request packet transmissions during change of egress port toward the another egress port.

Example 2 includes any example, wherein to change the egress port, the PF driver is to associate transmit packets with the another egress port.

Example 3 includes any example, wherein to change the egress port, the PF driver is to based on unavailability of the egress port, allocate a transmit packet scheduler to the another egress port to cause one or more packets allocated to a transmit queue associated with the transmit packet scheduler to be transmitted using the another egress port.

Example 4 includes any example, wherein any transmit packet associated with the transmit queue before the change to the another egress port is permitted to transmit but a packet added to the transmit queue during the change to the another egress port is not permitted to transmit until completion of the change to the another egress port.

Example 5 includes any example, wherein the unavailability of the egress port comprises the egress port has failed or is congested.

Example 6 includes any example, and includes based on unavailability of the egress port, drop one or more control packets to be sent through the egress port.

Example 7 includes any example, wherein said processor is to execute a virtualized execution environment that is to allocate at least one packet to a transmit queue and wherein during change of egress port to the another egress port to cause one or more packet allocated to the transmit queue to be transmitted using the another egress port is to occur independent from port change by the virtualized execution environment.

Example 8 includes any example, wherein the PF driver is to allocate transmit packets to a scheduler that is allocated to the another egress port.

Example 9 includes any example, and includes one or more of: a network interface, rack, compute sled, host computer, or data center.

Example 10 includes any example, and includes a method comprising: changing an egress port used by a virtualized execution environment to transmit packets toward another egress port independent of the virtualized execution environment requesting to change to use the another egress port, wherein a physical function (PF) driver changes the egress port toward the another egress port.

Example 11 includes any example, wherein changing an egress port comprises associating one or more packets to be transmitted with the another egress port.

Example 12 includes any example, wherein changing an egress port comprises associating a transmit packet scheduler toward the another egress port and comprising: transmitting one or more packet allocated to a transmit queue associated with the transmit packet scheduler using the another egress port.

Example 13 includes any example, wherein changing an egress port used by a virtualized execution environment to transmit packets toward the another egress port is based on unavailability of the egress port.

Example 14 includes any example, wherein the unavailability of the egress port comprises the egress port has failed or is congested.

Example 15 includes any example, and includes: based on unavailability of the egress port, dropping one or more control packets to be sent through the egress port.

Example 16 includes any example, and includes at least one non-transitory computer-readable medium, comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to: execute a physical function (PF) driver that is to change from an egress port to transmit one or more packets for a virtualized execution environment toward another egress port to transmit one or more packets independent of the virtualized execution environment requesting to change to use another egress port to transmit packets.

Example 17 includes any example, and includes instructions stored thereon, that if executed by at least one processor, cause the at least one processor to: select the another egress port based on the another egress port having spare transmit bandwidth.

Example 18 includes any example, wherein the PF driver is to change from the egress port to the another egress port based on the egress port having failed or being congested.

Example 19 includes any example, wherein the change from an egress port to the another egress port occurs while the virtualized execution environment continues to request packet transmission.

Example 20 includes any example, and includes instructions stored thereon, that if executed by at least one processor, cause the at least one processor to: allocate a transmit packet scheduler to the another egress port to cause one or more packet allocated to a transmit queue associated with the transmit packet scheduler to be transmitted using the another egress port.