A quadrature bandpass-sampling radio frequency (RF) receiver is provided. The receiver bandpass-samples and quantizes an RF signal to provide an in-phase bi-level digital signal based on an in-phase clock and a quadrature bi-level digital signal based on a quadrature clock. The in-phase clock frequency and the quadrature clock frequency are equal to the RF signal carrier frequency. The quadrature clock is ninety degree out of phase with respect to the in-phase clock.

FIELD OF THE INVENTION

The present invention relates in general to analog-to-digital conversion in communication systems. More specifically, the invention relates to analog-to-digital demodulation of a signal at radio frequencies in a communication system using bandpass sampling and delta-sigma modulation.

BACKGROUND OF THE INVENTION

Wireless systems are becoming a fundamental mode of telecommunication in modern society. In order for wireless systems to continue to penetrate into the telecommunications market, the cost of providing the service must continue to decrease and the convenience of using the service should continue to increase. In response to increasing market demand, radio standards around the world have been proliferated based upon digital modulation schemes. Consequently, it is often advantageous to have a receiver that is capable of communication using more than one of these standardized techniques. In order to do so, it is necessary to have a receiver that is capable of receiving signals that have been modulated according to several different modulation techniques.

Existing receivers are implemented using double conversion (or heterodyne) receiver architectures. A double conversion receiver architecture is characterized in that a received radio-frequency (RF) signal is converted to an intermediate frequency (IF) signal, which is subsequently converted to baseband. In addition, gain control is also typically applied at the IF. However, double conversion receivers have the disadvantage of utilizing a great number of analog circuit components, thus, increasing the cost, size, and power consumption of the receiver.

A direct conversion receiver, also sometimes called a zero-IF receiver, provides an alternative to the traditional double down conversion architecture. This is particularly attractive for the use in wireless systems, especially in handsets, since direct conversion receivers lend themselves more easily to monolithic integration than heterodyne architectures. Also, direct conversion exhibits immunity to the problem of image since there is no IF.

However, there exist design issues associated with the direct conversion architecture. The most serious problem is a direct current (DC) offset in the baseband, which appears in the middle of the down-converted signal spectrum, and may be larger than the signal itself. This phenomenon is caused by local oscillator leakage and self-mixing. Furthermore, mismatch between the in-phase (I) component and the quadrature (Q) component, occurring in the quadrature down-conversion, can lead to corrupted signal constellation, thereby increasing the number of bits in error, due to the differences which may occur in the I and Q signal amplitudes and phases.

Advancement in semiconductor process technologies allows usage of oversampling bandpass delta-sigma analog-to-digital conversion in the RF frequencies, which is a new promising low-cost and reliable technique to digitize RF signals. The delta-sigma converter comprises a bandpass filter, which consists of a series of resonators in cascade, an analog-to-digital converter (A/D), that generates the converted digital output signal, and a digital-to-analog converter (D/A) that produces a plurality of analog signals converted from the digital output signal to be feed back to the resonator inputs. The first error signal is produced by the difference between the input RF signal and the first feedback signal from the D/A. A first resonator in the filter stage amplifies the first error signal to produce a more refined error signal, which is subtracted from a second feedback signal from the D/A. The sequence is repeated down the resonator stages. The output error signal from the last resonator in the bandpass filter is then sampled by the A/D. The digitized signal is converted to a feedback signal via the D/A. In order to achieve feedback stability, the sampling frequency of the A/D must be at least four times the RF signal frequency, and the digital output reproduces the high-frequency waveform of the input RF signal.

Nevertheless, oversampling an RF signal is not quite practical given the current advancement in process technologies, where the sampling clock rate may exceed tens of gigahertz. The inherent clock jitter in the sampling clock to the A/D, due to thermal agitation at the molecule level that generates phase noise in clock oscillators, severely limits the analog-to-digital conversion resolution. Also, pre-processing of the digitized RF signal requires an impractically high clock rate in the tens of gigahertz range.

SUMMARY OF THE INVENTION

The invention features a circuit for demodulating an RF signal to baseband comprising: a single-bit analog-to-digital (A/D) demodulator, having an input conversion bandwidth, configured to receive an RF signal, having an RF carrier frequency, quantize the RF signal based on the in-phase sampling clock to generate an in-phase digital signal, and quantize the RF signal based on the quadrature sampling clock to generate a quadrature digital signal; a sampling clock generator configured to generate an in-phase sampling clock, having an in-phase sampling clock frequency, and a quadrature sampling clock, having a quadrature sampling clock frequency; wherein the RF carrier frequency being between 0.5 GHz to 6 GHz, the input conversion bandwidth being more than 5 MHz and less than 100 MHz, the center frequency of the input conversion bandwidth being equal to the RF carrier frequency, both the in-phase sampling clock frequency and the quadrature sampling clock frequency being equal to the RF carrier frequency, the quadrature sampling clock being ninety degree out of phase with respect to the in-phase sampling clock, and both in-phase digital signal and the quadrature digital signal being bi-level digital signals.

The single-bit A/D demodulator further comprises: first through (K-1)thsummers, the ithsummer being configured to receive the ithin-phase analog signal, the ithquadrature analog signal and the (i+1)thamplified error signal, generate an itherror signal, ithbeing from first through (K−1)th; a Kthsummer configured to receive an input RF signal and the Kthin-phase and quadrature analog signals, generate a Ktherror signal; first through Kthresonators, the ithresonator being configured to receive the itherror signal, generate an ithamplified error signal, ithbeing from first through Kth; a first quantizer configured to receive the first amplified error signal based on the in-phase sampling clock, and generate an in-phase digital signal; a second quantizer configured to receive the first amplified error signal based on the quadrature sampling clock, and generate a quadrature digital signal; first through Kthin-phase digital multipliers configured to multiply the in-phase digital signal with the in-phase sampling clock to generate first through Kthup-converted in-phase signals; first through Kthquadrature digital multipliers configured to multiply the quadrature digital signal with the quadrature sampling clock to generate first through Kthup-converted quadrature signals; first through Kthin-phase D/A converters configured to receive the first through Kthup-converted in-phase signals, and generate first through Kthin-phase analog signals; first through Kthquadrature D/A converters configured to receive the first through Kthup-converted quadrature signals, and generate first through Kthquadrature analog signals; wherein first through Kthin-phase and quadrature D/A converters being single-bit converters, and wherein K is between 2 and 4.

The invention also features a method for demodulating an RF signal to baseband comprising: receiving an RF signal, having an RF carrier frequency; quantizing the RF signal based on the in-phase sampling clock to generate an in-phase digital signal, and based on the quadrature sampling clock to generate a quadrature digital signal, the quantizing being restricted to an input conversion bandwidth; generating an in-phase sampling clock, having an in-phase sampling clock frequency; generating a quadrature sampling clock, having a quadrature sampling clock frequency; wherein the RF carrier frequency being between 0.5 GHz to 6 GHz, the input conversion bandwidth being more than 5 MHz and less than 100 MHz, the center frequency of the input conversion bandwidth being equal to the RF carrier frequency, both the in-phase sampling clock frequency and the quadrature sampling clock frequency being equal to the RF carrier frequency, the quadrature sampling clock being ninety degree out of phase with respect to the in-phase sampling clock, and both in-phase digital signal and the quadrature digital signal being bi-level digital signals.

The quantizing of the RF signal further comprises combining first through (K−1)thin-phase analog signals, first through (K−1)thquadrature analog signals and second through Kthamplified error signals to generate first through (K-1)therror signals, respectively; combining the Kthin-phase and quadrature analog signals to generate a Ktherror signal; amplifying first through Ktherror signals to generate first through Kthamplified error signals; quantizing the first amplified error signal based on the in-phase sampling clock to generate an in-phase digital signal, and based on the quadrature sampling clock to generate a quadrature digital signal; generating first through Kthup-converted in-phase signals based on first through Kthmultiplications of the in-phase digital signal with the in-phase sampling clock; generating first through Kthup-converted quadrature signals based on first through Kthmultiplications of the quadrature digital signal with the quadrature sampling clock; D/A converting first through Kthup-converted in-phase signals to generate first through Kthin-phase analog signals; D/A converting first through Kthup-converted quadrature signals to generate first through Kthquadrature analog signals; wherein D/A converting being a single-bit conversion; and wherein K is between 2 and 4.

DETAILED DESCRIPTION

In overview, the present disclosure concerns electronic devices or units, some of which are referred to as communication units, such as cellular phone or two-way radios and the like, typically having a capability for rapidly handling data, such as can be associated with a communication system such as an Enterprise Network, a cellular Radio Access Network, or the like. More particularly, various inventive concepts and principles are embodied in circuits, and methods therein for receiving signals in connection with a communication unit.

It is further understood that the use of relational terms such as first and second, and the like, if any, are used solely to distinguish one from another entity, item, or action without necessarily requiring or implying any actual such relationship or order between such entities, items or actions. It is noted that some embodiments may include a plurality of processes or steps, which can be performed in any order, unless expressly and necessarily limited to a particular order; i.e., processes or steps that are not so limited may be performed in any order.

Much of the inventive functionality and many of the inventive principles when implemented, are best supported with in integrated circuits (ICs), such as a digital signal processor or application specific ICs. It is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating ICs with minimal experimentation. Therefore, in the interest of brevity and minimization of any risk of obscuring the principles and concepts according to the present invention, further discussion of such ICs, if any, will be limited to the essentials with respect to the principles and concepts used by the exemplary embodiments.

Referring now toFIG. 1A, frequency diagrams103,105, and107illustrate quadrature down conversion of an RF signal to the baseband frequency based on the bandpass-sampling theory. A communication transmitter is employed to modulate the information to a carrier frequency, fC, and transmit the RF signal over the air. For example, conventional cellular phone carrier frequencies are currently set at either 900 MHz or 1800 MHz. In quadrature modulation, two independent data streams, A(t) and B(t), are modulated by cos(wct) and sin(wct), respectively. The combined A(t) cos(wct)−B(t) sin(wct) is then transmitted over the air. In the frequency domain, the transmitted information109in the frequency diagram103can be seen centered at the carrier frequency, fc, where the width of the shaped object corresponds to the bandwidth of the transmitted information. Note that the transmitted object is mirrored to the negative frequencies along the zero-frequency axis.

Referring now toFIG. 1B, the timing diagram111illustrating a sinusoidal waveform131at the RF carrier frequency is provided. The in-phase, A(t), and quadrature, B(t) signals which carry the communicating information modulate slowly the amplitude and/or the phase of the sinusoidal waveform131, depending on the modulation scheme employed in the communication system. In a quadrature bandpass-sampling receiver, the sampling rate is set equal to the RF carrier frequency, fC, and only two respective sampled data points for every period of the RF carrier are captured, as shown in the timing diagram111. The first sequence of sampled data points I1, I2, . . . , INcorresponds to the in-phase (I) sequence while the second sequence of sampled data points Q1, Q2, . . . , QNcorresponds to the quadrature (Q) sequence. Note that the time duration in between two adjacent sampled points of each sequence is always,

1fC,
the RF carrier period, and the time duration between a Q sampled point and an adjacent I sampled point is always,

14⁢fC,
or one quarter of the RF carrier period.

Bandpass sampling the sinusoidal waveform131removes the high frequency RF waveform and captures only the slowly-varying amplitude and/or phase of the communicating information that were modulated to the RF carrier frequency. By virtue of the bandpass sampling theory, the in-phase and quadrature modulated signals are down-converted to baseband, or dc, as illustrated in the frequency diagram105ofFIG. 1A. The sampled I and Q sequences can be recombined, according to I±jQ (where j denotes the imaginary complex number notation), to re-construct the transmitted A(t) and B(t) signals as in the frequency diagram107.

However, conventional technologies currently can not provide a sample/hold or an A/D converter that can sample an RF signal in the gigahertz frequencies and produce a demodulated signal with a resolution higher than 9 bits—a resolution that is far below wireless standard requirements for RF receivers. In the following disclosed embodiments, a novel bandpass sampling technique is provided and discussed to illustrate high-resolution quantization and demodulation of RF signals.

Referring now toFIG. 2, a schematic diagram illustrating a quadrature bandpass sampling receiver201is discussed. The quadrature bandpass sampling receiver201comprises a sampling clock generator205, and a single-bit A/D demodulator203. The sampling clock generator205generates an in-phase sampling clock (I-CLK) and a quadrature sampling clock (Q-CLK). The in-phase sampling clock frequency and the quadrature sampling clock frequency are set equal to the carrier frequency of the input RF signal. The quadrature sampling clock Q-CLK is 90-degree out-of-phase with respect to the in-phase sampling clock I-CLK. The RF signal, whose center frequency is located between 0.5 GHz and 6 GHz, is bandpass-sampled and demodulated by the single-bit A/D demodulator203based on I-CLK to produce a digital I-OUT signal, and based on Q-CLK to produce a digital Q-OUT signal.

Both digital I-OUT and Q-OUT signals are bi-level signals, having only one bit of resolution. However, because the I-OUT and Q-OUT signals are clocked at a sampling rate equal to the RF signal carrier frequency, and the transmitted baseband signals A(t) and B(t) have bandwidths of only a few or tens of megahertz, it is possible to use the oversampling technique to noise-shape the quantization noise in the I-OUT and Q-OUT signals. This oversampling technique is often used in delta-sigma modulators, in which the quantization noise is pushed out to the high frequency range, leaving the signal band near dc having very low level of quantization noise.

Referring now toFIG. 3, a schematic diagram301illustrating an exemplary quadrature bandpass sampling delta-sigma analog-to-digital demodulator (QBS-ADD) will be discussed and described. The QBS-ADD architecture301represents the single-bit A/D demodulator203inFIG. 2and comprises a first through Nthresonators connected in cascade, including a first resonator317, an (N−1)thresonator315and an Nthresonator313; a first quantizer319and a second quantizer321; a first through Nthsummers, including a first summer307, an (N−1)thsummer305and an Nthsummer303; a plurality of single-bit digital-to-analog converters (D/A)335,336,345,346,355,356; and a plurality of digital multipliers331,332,341,342,351, and352.

In general, the QBS-ADD301architecture is a multi-stage feedback architecture, in which the feedback tap points are provided by the pair D/As (355,356), (345,346) and (335,336). The resonators313,315and317form a high-gain composite bandpass filter which provides bandpass filtering and amplification of the error signals produced by the summers303,305, and307, respectively. The Nthsummer303subtracts the feedback information from the D/As355and356from the RF signal to produce an Ntherror signal, which is bandpass filtered and amplified by the Nthresonator313. Next, the (N−1)thsummer305subtracts the feedback information from the D/As345and346from the amplified Ntherror signal at the output of the Nthresonator313to produce an (N−1)therror signal. The (N−1)therror signal is then bandpass filtered and amplified by the (N−1)thresonator315. The process continues until the first error signal being bandpass filtered and amplified by the first resonator317.

The single-bit quantizers319and321provide bandpass sampling and down-conversion of the RF signal to baseband. The first quantizer319and the second quantizer321are clocked by the in-phase sampling clock, I-CLK, and the quadrature sampling clock, Q-CLK, respectively. The first quantizer319generates the bi-level digital output, I-OUT, which contains the in-phase component down-converted to baseband. The second quantizer321generates the bi-level digital output, Q-OUT, which contains the quadrature component down-converted to baseband.

Because the RF signal is demodulated to baseband by the quantizers319and321, by virtue of the bandpass sampling theory, it is fundamentally necessary to up-convert the demodulated signals, I-OUT and Q-OUT, as feedback signals to fulfill the feedback requirement—i.e. the feedback signals must be modulated by the same frequency as the input RF signal so that the correct error signals can be generated at the summers303,305and307. This requirement dictates inclusion of the feedback multipliers331,341,351to up-convert the Q-OUT signal using Q-CLK, and the feedback multipliers332,342and352to up-convert the I-OUT signal using I-CLK to the RF signal carrier frequency. Since I-CLK, Q-CLK, I-OUT, and Q-OUT are all bi-level signals, the multipliers331,332,341,342,351, and352are single-bit multiplication. Consequently, only single-bit D/As335,336,345,346,355, and356are needed.

The addition of the single-bit feedback multipliers331,341,351,332,342, and352in the feedback path set apart a novel QBS-ADD301that allows bandpass-sampling at the RF frequency, which is fundamentally different from the conventional delta-sigma A/Ds, as the later requires sampling clocks at least four times higher than the RF signal frequency.

Each resonator can be constructed from an inductor, L, and a capacitor, C, both of which form a resonance at

1LC.
Each resonator is required to have a high quality factor (Q-factor) to produce the high gain required for signal amplification. All the resonators313,315, and317resonant frequencies are set close to each other to form a bandpass filter with the passband centered about the RF signal carrier frequency. The spacings between resonant frequencies are about 5 MHz to 10 MHz. The order of a bandpass delta-sigma modulator relates to the number of resonators, or more exactly the number of Ls and Cs. For example, a second-order bandpass delta-sigma modulator comprises one LC resonator, or one L and one C; whereas an eighth-order modulator comprises four LC resonators. High-order bandpass delta-sigma modulators are characterized by excessive phase shifts in the bandpass filter, and therefore, are difficult to stabilize due to their feedback characteristic. Nevertheless, fourth-order to eighth-order modulators can be stabilized easily and are adequate to achieve high-resolution A/D quantization to meet various current wireless standard requirements.

InFIG. 4, the frequency diagrams401and403illustrate the down-conversion of the RF signal and the spectrum profile of the QBS-ADD301outputs, after I/Q recombination. In the frequency diagram401, the concepts of input conversion bandwidth of the QBS-ADD301is illustrated. The input conversion bandwidth, ΔBW, is defined as the frequency range within which an RF signal can be demodulated to baseband and effectively quantized to yield high-resolution in-phase and quadrature baseband signals. The input RF signal409is centered at the RF carrier frequency, fc(note that the negative frequency component is not shown in the frequency diagram401for clarity purpose). The center frequency of ΔBW is also equal to fc. Therefore, for the RF signal409to be effectively quantized and demodulated, its total bandwidth, defined as the frequency width of the element409, must be smaller than ΔBW. After down conversion to baseband, the complex (I−jQ) recombination of the in-phase (I) component I-OUT and the quadrature (Q) component Q-OUT produces the baseband signal407. The pass-band bandwidth of the composite bandpass filter formed by the resonators313,315and317determines the input conversion bandwidth ΔBW of the QBS-ADD301, which is usually set between 5 MHz to 100 MHz.

Unlike other conventional RF receivers where the in-phase and quadrature demodulated signals are digitized by a pair of high-resolution A/Ds at a low sampling rate, the QBS-ADD301is a delta-sigma type converter, which produces a stream of bi-level digital I-OUT and Q-OUT signals clocked at a sample rate equal to the RF signal carrier frequency. The frequency diagram403illustrates a typical spectrum profile of the combined I−jQ (where j is the imaginary complex number) from the I-OUT and Q-OUT signals. Even though I-OUT and Q-OUT exhibit noise-like characteristics, the noise-shaping property of oversampling delta-sigma modulators pushes the quantization noise to higher frequencies and leaves the signal band at baseband, between

-Δ⁢⁢BW2⁢⁢and⁢⁢Δ⁢⁢BW2,
with a minimum amount of quantization noise. It is seen then that the frequency band from

-Δ⁢⁢BW2⁢⁢to⁢⁢Δ⁢⁢BW2,
within which the quantization noise is minimized, defines the input conversion bandwidth of the QBS-ADD301; i.e. if the RF signal band falls within the input conversion bandwidth of the QBS-ADD301, then the RF signal can be demodulated and effectively quantized to the highest resolution.

It should be noted that the term communication unit may be used herein to denote a wired device, for example a high speed modem, an xDSL type modem, a fiber optic transmission device, and the like, and a wireless device, and typically a wireless device that may be used with a public network, for example in accordance with a service agreement, or within a private network such as an enterprise network or an ad hoc network. Examples of such communication devices include a cellular handset or device, television apparatus, personal digital assistants, personal assignment pads, and personal computers equipped for wireless operation, and the like, or equivalents thereof, provided such devices are arranged and constructed for operation in connection with wired or wireless communication.

The communication units of particular interest are those providing or facilitating voice communications services or data or messaging services normally referred to as ultra wideband networks, cellular wide area networks (WANs), such as conventional two way systems and devices, various cellular phone systems including analog and digital cellular, CDMA (code division multiple access) and variants thereof, GSM (Global System for Mobile Communications), GPRS (General Packet Radio System), 2.5G and 3G systems such as UMTS (Universal Mobile Telecommunication Service) systems, Internet Protocol (IP) Wireless Wide Area Networks like 802.16, 802.20 or Flarion, integrated digital enhanced networks, LTE (Long Term Evolution) networks, and variants or evolutions thereof.

Furthermore, the wireless communication devices of interest may have short range wireless communications capability normally referred to as WLAN (wireless local area network) capabilities, such as IEEE 802.11, Bluetooth, WPAN (wireless personal area network) or Hyper-Lan and the like using, for example, CDMA, frequency hopping, OFDM (orthogonal frequency division multiplexing) or TDMA (Time Division Multiple Access) access technologies and one or more of various networking protocols, such as TCP/IP (Transmission Control Protocol/Internet Protocol), UDP/UP (Universal Datagram Protocol/Universal Protocol), IPX/SPX (Inter-Packet Exchange/Sequential Packet Exchange), Net BIOS (Network Basic Input Output System) or other protocol structures. Alternatively the wireless communication devices of interest may be connected to a LAN using protocols such as TCP/IP, UDP/UP, IPX/SPX, or Net BIOS via a hardwired interface such as a cable and/or a connector.