A production process for protecting the surface of compound semiconductor wafers includes providing a multi-wafer epitaxial production system with a transfer and load module, a III-V growth chamber and an insulator chamber. The wafer is placed in the transfer and load module and the pressure is reduced to .ltoreq.10.sup.-10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer. The wafer is then moved through the transfer and load module to the insulator chamber and an insulating cap layer is formed by thermally evaporating gallium oxide molecules from an effusion cell using an evaporation source in an oxide crucible, which oxide crucible does not form an eutectic alloy with the evaporation source

FIELD OF THE INVENTION 
The present invention pertains to III-V wafer production and more 
specifically to surface protection of III-V structures. 
BACKGROUND OF THE INVENTION 
Prior art III-V epitaxial wafer production employs a semiconductor layer to 
complete the epitaxial structure. Various semiconducting top layers are 
being used, for example GaAs, In.sub.1-x Ga.sub.x As, Al.sub.1-x Ga.sub.x 
As, InGaAsP, etc., depending on the specific device/circuit application 
and semiconductor substrate. The use of semiconducting top layers in prior 
art epitaxial wafer production results in uncontrollable and detrimental 
electrical and chemical surface properties. Electronic and optoelectronic 
device/circuit processing is complicated and device/circuit performance is 
affected. The degree of complication and degradation is subject to the 
particular device/circuit processing and application. For example, the 
fabrication and performance of unipolar transistor devices/circuits is 
hampered by plasma exposure, Fermi level pinning, and instability of the 
gate-source and gate-drain regions. The fabrication of functional and 
stable MOSFET devices has been impossible. 
Uncontrollable and detrimental electrical and surface properties are caused 
by chemical surface reactions resulting in the formation of native oxides 
and dangling bonds. In turn, the surface is rendered thermodynamically 
unstable and exhibits a pinned Fermi level. Specifically, the high GaAs 
surface reactivity induces Fermi level pinning and surface instability 
after surface exposure as small as 10.sup.3 Langmuirs (1 
Langmuir=10.sup.-6 Torr). Surface preparation techniques conducted after 
exposure to air (sulfur, selenium, etc.) have proven to be inefficient and 
unstable. 
Prior art, for instance, M. Passlack et al., Appl. Phys. Lett., vol 68, 
1099 (1996), Appl. Phys. Lett., vol. 68, 3605 (1996), and Appl. Phys. 
Lett., vol 69, 302, (1996), U.S. Pat. No. 5,451,548, entitled "Electron 
beam Deposition of gallium oxide thin films using a single purity crystal 
layer", issued Sep. 19, 1995, and U.S. Pat. No. 5,550,089, entitled 
"Gallium Oxide Coatings for Optoelectronic Devices Using Electron Beam 
Evaporation of a High Purity Single Crystal Gd.sub.3 Ga.sub.5 O.sub.12 
Source", issued Aug. 27, 1996, reported that thermodynamically stable, 
III-V surfaces (interfaces) with low interface state density can be 
fabricated when a specific insulating cap layer is deposited in-situ on 
GaAs based semiconductor epitaxial layers using e-beam evaporation of 
Gd.sub.3 Ga.sub.5 O.sub.12 while maintaining ultra-high vacuum (UHV). For 
GaAs, pivotal aspects include an extremely low GaAs surface exposure to 
impurities (&lt;10-100 Langmuirs) and the preservation of GaAs bulk and 
surface stoichiometry, the complete exclusion of GaAs surface oxidation, 
and the requirements of a specific atomic structure associated with the 
interfacial atoms of GaAs and the deposited molecules. However, the 
process described in the prior art is not manufacturable since it is 
plagued by dc instability and poor reliability. 
Accordingly, it would be highly advantageous to provide new methods of 
manufacturing which overcome these problems. 
It is a purpose of the present invention to provide a new and improved 
III-V epitaxial wafer production process. 
It is another purpose of the present invention to provide a new and 
improved III-V epitaxial wafer with improved stability and reliability. 
It is still another purpose of the present invention to provide a new and 
improved III-V wafer which is relatively easy to fabricate and use. 
SUMMARY OF THE INVENTION 
The above problems and others are at least partially solved and the above 
purposes and others are realized in a method of protecting the surface of 
a compound semiconductor wafer structure including the steps of providing 
a compound semiconductor wafer structure with a surface and forming an 
insulating cap layer on the surface of the wafer structure by thermally 
evaporating insulating material onto the wafer structure. 
In a specific semiconductor production process, a multi-wafer epitaxial 
production system is provided including a transfer and load module with a 
III-V growth chamber attached and an insulator chamber attached. A 
compound semiconductor wafer with a surface is placed in the transfer and 
load module and the pressure in the multi-wafer production system is 
reduced to .ltoreq.10.sup.-10 Torr. The compound semiconductor wafer is 
moved to the III-V growth chamber and layers of compound semiconductor 
material are epitaxially grown on the surface of the compound 
semiconductor wafer. The compound semiconductor wafer is then moved to the 
transfer and load module and then to the insulator chamber, without 
removing it from the multi-wafer production system, and an insulating cap 
layer is formed by thermally evaporating material onto the layer of 
compound semiconductor material.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring specifically to FIG. 1, a prior art III-V compound semiconductor 
wafer 10 is illustrated. Wafer 10 includes a substrate with one or more 
layers of III-V material epitaxially formed on the upper surface thereof. 
For purposes of this disclosure the substrate and any epitaxial layers 
formed thereon will be referred to simply as a compound semiconductor 
wafer structure, which in FIG. 1 is designated 12. Compound semiconductor 
wafer structure 12 has a top layer 13 with an upper surface 14. Any 
exposure of compound semiconductor wafer structure 12 or top layer 13 to 
ambient conditions (air, processing environments, etc.) results in a layer 
15 of native oxide being formed on the surface. Generally, layer 15 is 
very thin, approximately 10 A thick. The interface between top layer 13 
and native oxide layer 15 is thermodynamically unstable and Fermi level 
pinned. 
A compound semiconductor wafer structure 20 formed in accordance with the 
present invention is illustrated in FIG. 2. Compound semiconductor wafer 
structure 20 generally includes a substrate with one or more layers of 
III-V material epitaxially formed on the upper surface thereof, hereafter 
designated 22. Compound semiconductor wafer structure 20 has a top layer 
23 with an upper surface 24. It will of course be understood that in some 
specific applications (or on some portions of compound semiconductor wafer 
structure 20) there may be no epitaxial layers present on the substrate 
and upper surface 24 may simply be the upper surface of the substrate. An 
insulating cap layer 25 is thermally evaporated onto surface 24 of 
compound semiconductor wafer structure 20. 
Turning now to FIG. 3, a multi-wafer epitaxial production system 30 is 
illustrated, which is utilized in fabricating compound semiconductor wafer 
structure 20 of FIG. 2 in accordance with the present invention. System 30 
includes a transfer and load module 33, a III-V growth chamber 35 attached 
to transfer and load module 33, and an insulator chamber 38 attached to 
transfer and load module 33. Each of chambers 35 and 38 are attached to 
transfer and load module 33 so that wafers, chips, etc. can be processed 
in each chamber without removing the wafers, chips, etc. from system 30. 
Therefore, once a wafer is introduced into system 30 and a vacuum is 
drawn, the wafer is not subjected to the environment until the process is 
completed. 
Thus, as an example of a process of protecting the surface of a compound 
semiconductor wafer structure in accordance with the present invention, a 
compound semiconductor wafer is placed in transfer and load module 33 and 
the pressure in multi-wafer production system 30 is reduced to 
.ltoreq.10.sup.-10 Torr. The wafer is then moved to III-V growth chamber 
35 and one or more layers of compound semiconductor material are 
epitaxially grown on the surface to produce a compound semiconductor wafer 
structure (e.g. compound semiconductor wafer structure 20). After the 
growth of top layer 23, compound semiconductor wafer structure 20 is moved 
to transfer and load module 33 and then to insulator chamber 38. In 
insulator chamber 38, insulating cap layer 25 is formed on surface 24 of 
compound semiconductor wafer structure 20 by thermally evaporating 
insulating material onto wafer structure 20. 
In a preferred embodiment of the process, insulating cap layer 25 is 
thermally evaporated onto surface 24 of wafer structure 20 by thermally 
evaporating gallium oxide molecules from an effusion cell using an 
evaporation source in an oxide crucible. The evaporation source is 
selected from one of polycrystalline Ga.sub.2 O.sub.3 having a melting 
point m.sub.po, single-crystal Ga.sub.2 O.sub.3 having a melting point 
m.sub.po, or a polycrystalline or single-crystal material containing a 
Ga.sub.2 O.sub.3 component having a melting point m.sub.po. The oxide 
crucible containing the evaporation source is selected from either an 
oxide crucible with a melting point m.sub.p &gt;m.sub.po, which oxide 
crucible does not exhibit a eutectic alloy with the evaporation source, or 
an oxide crucible having a eutectic temperature with the evaporation 
source, which eutectic temperature is higher than the evaporation 
temperature of the source. Further, the oxide crucible is preferably 
formed of material having a relatively high bandgap, i.e. generally 
.gtoreq.4 eV. 
In a specific example, the oxide crucible is formed from one of the 
following materials: BeO (mp=2507.degree. C.), ZrO.sub.2 (mp=2710.degree. 
C.), HfO.sub.2 (mp=2774.degree. C.), La.sub.2 O.sub.3 (mp=2305.degree. 
C.), A.sub.2 O.sub.3 (mp=2050.degree. C.), or ThO.sub.2 (mp=3390.degree. 
C.). Using one of the above materials for the oxide crucible, the 
evaporation source is polycrystalline or single-crystal Ga.sub.2 O.sub.3 
or a polycrystalline or single-crystal material containing a Ga.sub.2 
O.sub.3 component (m.sub.po =1725.degree. C.). In another specific 
example, the oxide crucible is formed from one of the following materials: 
ZrO.sub.2 (mp=2710.degree. C.), HfO.sub.2 (mp=2774.degree. C.), La.sub.2 
O.sub.3 (mp=2305.degree. C.), Al.sub.2 O.sub.3 (mp=2050.degree. C.), or 
ThO.sub.2 (mp=3390.degree. C.) and the evaporation source includes one of 
Gd.sub.3 Ga.sub.5 O.sub.12 (m.sub.po =1700.degree. C.) and MgGa.sub.2 
O.sub.4 (m.sub.po =1700.degree. C.). 
Thus, compound semiconductor wafer structure 20 is protected from exposure 
to ambient conditions until insulating cap layer 25 is in place. Because 
insulating cap layer 25 is formed in system 30 of FIG. 3, the structure or 
epitaxial layers are never subjected to ambient conditions and the 
interface between the substrate or epitaxial layers and insulating cap 
layer 25 is thermodynamically stable with excellent electrical properties. 
In the specific example of a compound semiconductor wafer structure with a 
GaAs surface and a layer of oxide deposited thereon, the GaAs-Ga.sub.2 
O.sub.3 interface exhibits monolayer abruptness and the oxide has a 
surface roughness (rms) .ltoreq.2.5 .ANG.. Also, it has been found that 
there is excellent uniformity of interface state density over a fabricated 
wafer. The interface state density is in general comparable or better than 
prior art densities (10.sup.10 cm.sup.-2 eV.sup.-1). Further, in the 
specific example in which Gd.sub.3 Ga.sub.5 O.sub.12 is used as an 
evaporation source, it has been found that Ga.sub.2 O.sub.3 films include 
Gd levels below the detection limit of Selective Ion Mass Spectroscopy 
(SIMS), as illustrated by the graphical representation of FIG. 4. 
The thermally evaporated insulating layer on the wafer structure of the 
disclosed process replaces the exposed semiconductor surface of prior art 
epitaxial products and the buried epitaxial semiconductor surface is 
electrically and chemically stable and exhibits excellent electrical 
properties. Thus, the improved compound semiconductor wafer structure 
fabricated in accordance with the novel surface protection process has the 
following advantages: excellent electrical and chemical properties, 
passivation and protection of the semiconductor epilayer structure and 
devices/circuits formed therein; stability of the excellent electronic and 
chemical surface properties of the semiconductor epilayer structure and 
devices/circuits formed therein; simplification of device/circuit 
processing; improved reproducibility and reliability of devices/circuits; 
and essential parts of the semiconductor surface are not exposed during 
processing, preserving electronic passivation. 
These improvements essentially solve or overcome the problems of the prior 
art, such as dc instability and poor reliability, and therefore provide a 
highly manufacturable process. 
While we have shown and described specific embodiments of the present 
invention, further modifications and improvements will occur to those 
skilled in the art. We desire it to be understood, therefore, that this 
invention is not limited to the particular forms shown and we intend in 
the appended claims to cover all modifications that do not depart from the 
spirit and scope of this invention.