Efficient implementation of a multiplier/accumulator with load

This invention is multiply-accumulate circuit supporting a load of the accumulator. During multiply-accumulate operation a partial product generator forms partial produces from the product inputs. An adder tree sums the partial product and the accumulator value. The sum is stored back in the accumulator overwriting the prior value. During load operation an input gate forces one of the product inputs to all 0's. Thus the partial product generator generates partial products corresponding to a zero product. The adder tree adds this zero product to the external load value. The sum, which corresponds to the external load value is stored back in the accumulator overwriting the prior value. A multiplexer at the side input of the adder tree selects the accumulator value for normal operation or the external load value for load operation.

TECHNICAL FIELD OF THE INVENTION

The technical field of this invention is multiply-accumulators.

BACKGROUND OF THE INVENTION

A digital signal processor (DSP) instruction set typically include multiply-accumulate instructions which execute in dedicated hardware. This multiply-accumulate hardware implements the function:
Acc<=Acc+(X*Y).

As defined above the multiply-accumulate instruction forms the product of two operands X and Y and adds their product to the value stored in an accumulator. The sum is stored in the accumulator overwriting the previous value.

It is desirable to have load or move instructions having this accumulation register (Acc) as a destination. Implementing this function typically employs a multiplexer between data from the multiply-accumulate result and the load/move data. The prior art places this multiplexer just before the Acc register. This places the multiplexer on the most critical path. This critical path is the data flow from the X/Y source registers, through the multiply and add operations to the Acc register.

The multiplexer placement creates a problem. By being in the critical path, the multiplexer slows operation of the multiply-accumulate function. The prior art placement of the multiplexer causes all operations to slow, even ordinary multiply-accumulation. This limits the clock rate that can be employed potentially slowing all data processor operation.

SUMMARY OF THE INVENTION

This invention is directed to a multiply-accumulate circuit supporting a load of an accumulator. During multiply-accumulate operation, a partial product generator forms partial produces from the product inputs. An adder tree sums the partial product and the accumulator value. The sum is stored back in the accumulator overwriting the prior value.

During load operation an input gate forces one of the product inputs to all 0's. Thus the partial product generator generates partial products corresponding to a zero product. The adder tree adds this zero product to the external load value. The sum, which corresponds to the external load value is stored back in the accumulator overwriting the prior value.

A multiplexer at the side input of the adder tree selects the accumulator value for normal operation or the external load value for load operation. This placement of the multiplexer is out of the critical path during normal operation. Thus this circuit may operate faster than the prior art that includes the multiplexer between the adder tree and the accumulator.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1illustrates a multiply-accumulator100having a load accumulator operation according to the prior art. Multiply-accumulator100includes input register101which receives and stores a first input operand X. Multiply-accumulator100includes input register102which receives and stores a second input operand Y. The sources of X and Y could be data from registers in a register file, data recalled from memory or external inputs. The sources of X and Y are not relevant to this invention.

In accordance with the prior art the multiply-accumulate operation is performed in hardware by the combination of partial product generator103and adder tree104. The data stored in input register101and input register102are supplied to respective inputs of partial product generator103. Partial product generator103generates a set of partial products from the inputs X and Y. Adder tree104sums these partial products with the proper shifts to form the product. Adder tree104also receives the current data stored in accumulator106. Adder tree104adds the current data from accumulator106to the product data by summing the accumulator data with the partial products.

The accumulated product output of adder tree104supplies one input of multiplexer105. A second input of multiplexer105receives external source data. This external source data is used to initialize or load accumulator106. The control input to multiplexer105determines the data selected. During ordinary multiply-accumulate operations, multiplexer105selects data from adder tree104for storage in accumulator106. During load operations, multiplexer105selects data from the external source for storage in accumulator106. The selected output of multiplexer105is stored in accumulator106overwriting any prior data.

The placement of multiplexer105illustrated inFIG. 1creates a problem. Multiplexer105introduces additional gate delay in the critical path. Note that every operation of multiply-accumulator100involves the gate delay of multiplexer105. Multiply-accumulator100must be clocked at a lower frequency to accommodate this additional gate delay relative to a non-load multiply-accumulator. This limits the clock rate that can be employed potentially slowing all data processor operation.

FIG. 2illustrates multiply-accumulator200according to this invention. During multiply-accumulate operation multiply-accumulator200operates in the same manner as multiply-accumulator100. Multiply-accumulator200includes input register201which receives and stores a first input operand X and input register203which receives and stores a second input operand Y. The data stored in input register201and input register203are supplied to respective inputs of partial product generator204. Adder tree205sums the partial products with the proper shifts to form the product. Adder tree205also receives the current data stored in accumulator206(via multiplexer207further described below). Adder tree205adds the current data from accumulator206to the product data by summing the accumulator data with the partial products. The output of adder tree201is stored in accumulator206overwriting any prior data.

A load operation employs AND gate202and multiplexer207. AND gate202includes the same structure for each bit of the second operand Y. A first input of AND gate202receives the operand Yi. A second inverting input of AND gate202receives a control signal ZERO. During normal (multiply-accumulate) operation control signal ZERO is all 0's. Due to the inverting action of the inverting input, all bits Yiare passed unchanged to be stored in input register203. During load operation control signal ZERO is all 1's. Thus all bits of operand Y are blocked and the output of AND gate202is all 0's. This zero input is stored in input register203and then passed to partial product generator204. The resulting partial products resolve all 0's. This all zero set of partial products is supplied to adder tree204.

Multiplexer207selects the second input to adder tree205as specified by the control input. During multiply-accumulate operation multiplexer207selects the current contents of accumulator206. During load operation multiplexer207selects the external data source. Because the output of partial product generator204is always zero due to AND gate202zeroing one of its inputs during load operations, the sum of adder tree205is the external data. Adder tree205supplies this external data to accumulator206for storage.

This invention puts the multiplexer in the path from the accumulator register to the adder. This path is less critical than the path from the X/Y registers. The data from accumulator206can be fed into adder tree205at a later point than the partial products from partial product generator204. AND gate202forces the partial products to zero, so that adder tree205passes the external data to accumulator register206. This removes the multiplexer gate delay from the critical path in the multiplier-accumulator. Accordingly, the DSP is permitted to operate at a higher clock frequency.

FIG. 3illustrates an alternative embodiment of this invention. InFIG. 3AND gate303is disposed between input register302and partial product generator204rather than between the source of Y and input register203as illustrated inFIG. 2. The circuit ofFIG. 3operates as previously described. This circuit passed either operand Y or all 0's to the corresponding input of partial product generator204.

Those skilled in the art would realize that the AND gate need not be in the second operand path. This circuit would operate equally well with the AND gate in either operand path. Those skilled in the art would realize the recited inverting input to the AND gate depends upon the sense of the control signal ZERO. It is feasible to employ a non-inverting input to the AND gate if control signal ZERO was all 1's for multiply-accumulate operation and all 0's for load operation.