MANUFACTURING METHOD FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor element includes forming a mask on a front surface of a substrate, the mask having an opening to expose the front surface; growing a first semiconductor layer by epitaxially growing a semiconductor along the mask, starting from the front surface exposed through the opening, and growing a second semiconductor layer on a surface of the first semiconductor layer located opposite to the substrate in a layering direction, and providing an electrode on a surface of the second semiconductor layer located opposite to the surface of the first semiconductor layer in the layering direction. A width from an end portion of the surface to the electrode is smaller than a width of the mask.

BACKGROUND

1. Technical Field

The present disclosure relates to a manufacturing method for a semiconductor element, a semiconductor element, and a semiconductor device.

2. Description of the Related Art

A Schottky barrier diode (SBD) made by an epitaxial lateral overgrowth (ELO) method using a free-standing GaN substrate is described in JP 6070422 B.

SUMMARY

In one aspect, a method of manufacturing a semiconductor element includes forming a mask on a front surface of a substrate, the mask having an opening to expose the front surface, growing a first semiconductor layer by epitaxially growing a semiconductor along the mask, starting from the front surface exposed through the opening, and growing a second semiconductor layer on a surface of the first semiconductor layer located opposite to the substrate in a layering direction, and providing an electrode on a surface of the second semiconductor layer located opposite to the surface of the first semiconductor layer in the layering direction. A width from an end portion of the surface to the electrode is smaller than a width of the mask.

In one aspect, a semiconductor element is manufactured by the method of manufacturing a semiconductor element, and the mask is interposed between the substrate and the first semiconductor layer inside the semiconductor element.

In one aspect, a semiconductor device includes a semiconductor element manufactured by the method of manufacturing a semiconductor element.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An SBD manufactured using a free-standing GaN substrate may have crystal defects in various directions in a voltage resistant end portion of a surface on which an anode electrode is provided. When the crystal defects occur on the surface along a direction of an electric field in the voltage resistant end portion, an impurity level that serves as a source of leakage occurs even when the surface is covered with an insulating film. Thus, the crystal defects that occur along the direction of the electric field serve as paths for leakage current. This reduces the voltage resistance of the SBD.

A manufacturing method for a semiconductor element1, the semiconductor element1, and a semiconductor device2, according to the embodiment will be described below. The semiconductor element1is a power semiconductor used in switching circuits of power converters such as inverters and converters.

EMBODIMENT

Manufacturing Method

FIG.1is a cross-sectional schematic view for describing the semiconductor element according to the embodiment.FIG.2is a cross-sectional schematic view for describing the manufacturing method for the semiconductor element and the semiconductor element according to the embodiment.FIG.3is a plan schematic view for describing the semiconductor element according to the embodiment.FIG.4is a schematic view for describing the semiconductor elements and the semiconductor device according to the embodiment.

As illustrated inFIG.1toFIG.3, in the semiconductor element1manufactured by the manufacturing method according to the embodiment, a semiconductor layer31is formed on a substrate11. In the semiconductor layer31, a GaN layer (first semiconductor layer)32, which is an n+ type semiconductor layer, and a GaN layer (second semiconductor layer)33, which is an n-type semiconductor layer, are layered in order from the substrate11side. Inside the semiconductor element1, a mask21is interposed between the substrate11and the GaN layer32. As illustrated inFIG.4, the semiconductor device2includes the semiconductor elements1manufactured in this manner.

The manufacturing method for the semiconductor element1will be described with reference toFIGS.1,2, and5.FIG.5is a flowchart for describing the manufacturing method for the semiconductor element according to the embodiment. The manufacturing method for the semiconductor element1is performed in accordance with steps illustrated inFIG.5.

The substrate11illustrated inFIGS.1and2is n+ type free-standing GaN. The doping amount of n-type impurities is controlled so that the substrate11has an electron carrier concentration of equal to or higher than 1018 cm−3.

A back surface11bon the opposite side to a front surface11aof a GaN layer, which is a surface layer of the substrate11, may be supported by a substrate other than the GaN substrate, such as a silicon substrate (not illustrated). The substrate that supports the back surface11bof the GaN layer, which is the surface layer of the substrate11, may be, for example, a sapphire substrate or a silicon carbide (SiC) substrate.

First, the mask21made of SiO2is formed on the front surface11aof the GaN layer, which is the surface layer of the substrate11, illustrated inFIG.2(step ST11) (first step). More specifically, the mask21having an opening22is provided on the front surface11aof the substrate11.

The mask21may contain an element that serves as a donor in the semiconductor layer31. Examples of a material of the mask21may include metals such as W and Ti, nitrides such as SiN and AIN, and oxides such as Al2O3and Ga2O3. The mask21may be amorphous. The mask21includes the opening22.

A portion of the front surface11aof the substrate11corresponding to the opening22is exposed through the opening22of the mask21. The mask21may cover the front surface11aat both ends of the substrate11. The mask21may cover the entire side surface or back surface of the substrate11. The mask21may cover the entirety excluding the opening22, of the surfaces that may come into contact with a raw material gas used in a vapor growth method, which will be described below.

A width w1of the mask21in a lateral direction orthogonal to a layering direction is, for example, 10 μm or more. The thickness of the mask21in the layering direction is, for example, 100 nm.

As illustrated inFIG.2, the GaN layer is formed as the semiconductor layer31from the front surface11aof the substrate11exposed through the opening22using the ELO technique described above (step ST12) (second step). More specifically, using the ELO technique, an epitaxial apparatus (not illustrated) epitaxially grows GaN along the mask21from the front surface11aof the substrate11exposed through the opening22to epitaxially grow an n+ type GaN layer32with a high impurity concentration.

The GaN layer32grows, from the front surface11aexposed through the opening22, longitudinally above the opening22in the layering direction, and laterally outside the opening22. A surface32aof the GaN layer32becomes substantially flat. The GaN layer32is auto-doped with impurities from the constituent material of the mask21during crystal growth. When the impurity is silicon (Si), the GaN layer32is a highly doped n+ semiconductor layer. The doping amount of n-type impurities is controlled so that the GaN layer32has an electron carrier concentration equal to or higher than 1018 cm−3. When the doping amount is insufficient in auto-doping, an impurity (for example, Si) may be doped during epitaxial growth. The thickness of the GaN layer32in the layering direction is, for example, 10 μm or more.

In order to obtain a desired impurity concentration profile, the GaN layer33with a low impurity concentration is formed so as to cover the GaN layer32(step ST13) (third step). More specifically, the n− type GaN layer33with a low impurity concentration is formed from the surface32aof the GaN layer32.

The GaN layer33is grown from the surface32aof the GaN layer32by selecting conditions in which longitudinal growth is dominant over lateral growth. A surface33aof the GaN layer33becomes substantially flat. The surface33aof the GaN layer33is located on the opposite side to the substrate11in the layering direction and is a surface on which an upper surface electrode is provided. The GaN layer33is an n− semiconductor layer. The doping amount of n-type impurities is controlled so that the GaN layer33has an electron carrier concentration lower than 1017cm−3. During the epitaxial growth, the GaN layer33is not in contact with the mask21and is covered with the GaN layer32, so that the auto-doping is reduced. The GaN layer32covers a large portion of the mask21, so that the auto-doping of the GaN layer33is also reduced. The thickness of the GaN layers33in the layering direction is, for example, 5 μm or more for an element with a breakdown voltage of 600 V.

As described above, as illustrated inFIGS.1and2, a semiconductor is epitaxially grown along the mask21from the front surface11aexposed through the opening22to produce the semiconductor element1including the semiconductor layer31. The semiconductor layer31is formed on the substrate11. The GaN layer32, which is an n+ type semiconductor layer, and the GaN layer33, which is an n− type semiconductor layer, are epitaxially grown from the front surface of the substrate11in the layering direction.

As illustrated inFIG.3, the semiconductor element1has a hexagonal shape when viewed from above in the layering direction. This is because the growth direction of the crystal in epitaxial growth is determined. In the semiconductor layer31of the semiconductor element1, crystals grow longitudinally above the opening22in the layering direction, and laterally on the outside of the opening22. As a result, the crystal defects on the surface33aof the GaN layer33of the semiconductor element1extend longitudinally in the center portion, and extend laterally on the outside of the center portion.

A manufacturing method for the semiconductor device2including the semiconductor element1will be described with reference toFIG.1andFIG.6.FIG.6is a flowchart for describing a manufacturing method for the semiconductor device according to the embodiment. The manufacturing method for the semiconductor device2is performed in accordance with steps illustrated inFIG.6after the semiconductor element1is manufactured in accordance with steps illustrated inFIG.5. Step ST21to step ST22are performed after performing step ST11to step ST13.

Back surface electrodes61are formed on the back surface11bof the substrate11on the opposite side to the semiconductor layer31(step ST21). More specifically, the back surface electrodes61are formed on the back surface11bof the substrate11by, for example, sputtering.

The back surface electrodes61are obtained by, for example, performing Ti/Ni/Au plating on an Al layer. Note that the back surface electrodes61may be formed after a Schottky electrode41, which will be described below, is formed. In the manufacturing method including a step of increasing a temperature, for example, by performing step ST21last, the influence on the back surface electrodes61can be avoided.

The Schottky electrode41, which is a metal layer (barrier metal), is formed on the surface33aof the GaN layer33of the semiconductor layer31(step ST22). Thus, a Schottky junction is provided between the GaN layer33and the Schottky electrode41.

The Schottky electrode41is made of, for example, Ni, Al, or Pd. The Schottky electrode41is located on the opposite side to the substrate11in the layering direction. The Schottky electrode41is provided in the center portion of the surface33aof the GaN layer33. A width w2from an end portion of the surface33aof the GaN layer33to the Schottky electrode41(width of the voltage resistant end portion) is smaller than the width w1of the mask21. On the surface33aof the GaN layer33, an area from the end portion of the surface33ato the Schottky electrode41is referred to as a voltage resistant end portion.

In the above-described manner, the semiconductor element1is manufactured. The manufactured semiconductor element1can be used as, for example, an SBD having a Schottky junction. Inside the manufactured semiconductor element1, the mask21is interposed between the substrate11and the GaN layer32.

The manufacturing processes described above may be performed concurrently so as to simultaneously manufacture a plurality of semiconductor elements1. In this case, the mask21is formed with a plurality of openings22in a striped pattern. By making one semiconductor element1correspond to one opening22, the plurality of semiconductor elements1can be simultaneously made.

When the mask has a striped pattern, each crystal has a hexagonal shape with two long sides as illustrated inFIG.4.

The semiconductor elements1manufactured simultaneously may be separated into individual pieces and used in the semiconductor devices2, respectively. When the capacity needs to be increased, for example, while the substrate11and the back surface electrodes61are shared by the plurality of semiconductor elements1, the plurality of semiconductor elements1may be mounted for use in the semiconductor device2, as illustrated inFIG.4. Specifically, as illustrated inFIG.4, the back surface electrodes61that are shared are each die-bonded to a corresponding one of the electrode pads201on a mounting substrate200, and individual Schottky electrode41(not illustrated) are connected to another electrode pad202by bonding wires52. By mounting the mounting substrate200in this manner, a plurality of diodes can be connected in parallel to increase the capacity and be used. At this time, the plurality of semiconductor elements1are manufactured so as to be aligned and disposed in a certain direction. In the layering direction view, the semiconductor elements1each have a shape elongated in a substantially orthogonal direction with respect to a direction in which the semiconductor elements1are aligned. Aligning the semiconductor elements1having such a shape in this manner can increase a junction area of the diode. The semiconductor elements1manufactured in this manner are available for a variety of semiconductor devices2according to applications.

As described above, in the present embodiment, the mask21is interposed between the substrate11and the GaN layer32inside the semiconductor element1. In the present embodiment, the width w2from the end portion of the surface33aof the GaN layer33to the Schottky metal film41is smaller than the width w1of the mask21. In the present embodiment, crystals grow longitudinally above the opening22in the layering direction, and laterally on the outside of the opening22. In the present embodiment, the direction of crystal defects in the voltage resistant end portion is the lateral direction. As a result, according to the present embodiment, the occurrence of crystal defects along the direction of the electric field, which may serve as paths for leakage current of the semiconductor element1, can be reduced in the voltage resistant end portion. In the present embodiment, the voltage resistance of the SBD can be improved.

In the present embodiment, the width w1of the mask21is, for example, 10 μm or more. In this variation, the width w2(<w1) of the voltage resistant end portion can be narrowed. According to the present embodiment, the ratio of the conductive area of the semiconductor element1can be increased. In the present embodiment, the semiconductor element1can be reduced in size, thereby reducing costs.

First Variation

A description is given of a first variation of the embodiment usingFIGS.7and8.FIG.7is a cross-sectional schematic view for describing an example of a semiconductor element according to the first variation of the embodiment.FIG.8is a flowchart for describing a manufacturing method for a semiconductor device according to the first variation of the embodiment. As illustrated inFIG.7, the semiconductor element1according to the first variation has a mesa structure and a field plate structure. The semiconductor device2includes such a semiconductor element1. Note that inFIG.7, a step is drawn larger for description. The same applies to the following figures.

A manufacturing method for the semiconductor device2including the semiconductor element1will be described. Steps ST11to ST13are performed in a manner the same as or similar to that in the embodiment. In other words, the semiconductor element1is manufactured in a manner the same as or similar to that in the embodiment. Step ST21is performed in a manner the same as or similar to that in the embodiment. That is, after performing steps ST11to ST21in the embodiment, steps ST22to ST25are performed.

Part of the GaN layer33is dry-etched (step ST22). More specifically, part of the surface33aof the GaN layer33is dry-etched. Specifically, a periphery of the GaN layer33is dry-etched. An end portion of the surface33aof the GaN layer33has a mesa structure. In other words, a periphery of the remaining GaN layer33has a mesa step33s. The periphery of the GaN layer33has a surface33cat a position closer to the GaN layer32than the surface33a, in other words, at a position one step lower.

The Schottky metal film41that forms a Schottky junction with the GaN layer33is formed on the exposed surface33aside (step ST23). The Schottky metal film41covers the exposed surface33aof the GaN layer33. Thus, the Schottky junction is provided between the GaN layer33and the Schottky metal film41.

An insulating film42, which is an insulating layer, is formed (step ST24). The insulating film42covers the exposed GaN layer33and a periphery of the Schottky metal film41. The insulating film42includes a wall portion421covering the periphery of the Schottky metal film41, a wall portion422covering a side surface33bof the GaN layer33, and a wall portion423covering the surface33cof the GaN layer33. The wall portion421has an opening that exposes the Schottky metal film41in the center portion. The wall portion422extends downward in the layering direction from an outer end portion of the wall portion421. The wall portion423extends outward from a lower end portion of the wall portion422in the layering direction.

An upper surface electrode metal film43is formed on the Schottky metal film41and on the insulating film42(step ST25). The upper surface electrode metal film43forms a so-called field plate on the insulating film42. An outer end portion of the wall portion423of the insulating film42is not covered with the upper surface electrode metal film43.

Step ST21, which is a step of forming the back surface electrode, may be performed after step ST25when the annealing temperature of the back surface electrode does not affect the Schottky metal film41, the insulating film42, and the upper surface electrode metal film43.

In the above-described manner, the semiconductor element1having the mesa structure and the field plate structure is manufactured. Having the field plate can reduce the electric field applied to the end portion of the upper surface electrode, resulting in a device with high breakdown voltage. The field plate may be separated from the upper electrode.

In this variation, the electric field applied to the end portion of the upper surface electrode can be reduced by having the mesa step33s. In this variation, the electric field applied to the end portion of the upper surface electrode can be reduced by having the field plate. Thus, according to this variation, the semiconductor element1with a high maximum peak current can be manufactured. According to this variation, the semiconductor element1with improved voltage resistance can be manufactured.

In this variation, the crystal direction in the voltage resistant end portion is the lateral direction, and the occurrence of crystal defects on the surface along the electric field direction, which may serve as paths for leakage current in the semiconductor element1, can be reduced. Thus, in this variation, the height of the mesa step33sin the layering direction can be reduced. In this variation, the width w2of the voltage resistant end portion can be narrowed. These allow the ratio of the conductive area of the semiconductor element1to be increased in this variation. According to this variation, the semiconductor element1can be smaller, thereby reducing costs.

Second Variation A description is given of a second variation of the embodiment usingFIG.9.FIG.9is a cross-sectional schematic view for describing a semiconductor element according to the second variation of the embodiment. The semiconductor element1according to the second variation has a mesa structure, a field plate structure, and a trench structure.

A manufacturing method for the semiconductor device2including the semiconductor element1will be described. Step ST11to step ST13are performed in a manner the same as or similar to that in the embodiment. In other words, the semiconductor element1is manufactured in a manner the same as or similar to that in the embodiment. Step ST21is performed in a manner the same as or similar to that in the embodiment. That is, after performing steps ST11to ST21in the embodiment, steps ST22to ST25are performed. In the following, steps different from those in the first variation will be described.

In step ST22, the mesa step33sand a trench structure33tare formed in the GaN layer33by dry etching. More specifically, a periphery of the remaining GaN layer33has the mesa step33s. The trench structure33thaving a groove shape is formed inside the periphery of the remaining GaN layer33. In the GaN layer33, part of the surface33aremains except for the area where the mesa step33sor the trench structure33tis formed.

In step ST23, the Schottky metal film41is formed on the surface33aremaining inside the mesa step33s.

In step ST24, the insulating film42is formed to cover the exposed surface of the GaN layer33that is not covered with the Schottky metal film41.

In step ST25, the upper surface electrode metal film43is formed on the Schottky metal film41and on the insulating film42.

In the above-described manner, the semiconductor element1having the mesa structure, the field plate structure, and the trench structure is manufactured.

In this variation, the electric field applied to the center portion of the upper surface electrode can be reduced by having the trench structure. According to this variation, the semiconductor element1with higher voltage resistance can be manufactured.

Third Variation A description is given of a third variation of the embodiment usingFIG.10.FIG.10is a cross-sectional schematic view for describing a semiconductor element according to the third variation of the embodiment. The semiconductor element1according to the third variation has a mesa structure, a field plate structure, and a JBS structure. According to the third variation, in the semiconductor layer31of the semiconductor element1, the GaN layer (first semiconductor layer)32, which is an n+ type semiconductor layer, the GaN layer (second semiconductor layer)33, which is an n− type semiconductor layer, and a GaN layer (third semiconductor layer)34, which is a p+ type semiconductor layer, are layered in order from the substrate11.

A manufacturing method for the semiconductor device2including the semiconductor element1will be described. In the third variation, after performing step ST11to step ST13, step ST14(not shown) is performed.

In order to obtain a desired higher impurity concentration profile, the p+ type GaN layer34with a high impurity concentration is formed to cover the GaN layer33(step ST14).

The doping amount of p-type impurities is controlled so that the GaN layer34has a hole carrier concentration of equal to or higher than 1018 cm−3. The surface of the GaN layer34becomes substantially flat. The thickness of the GaN layer34in the layering direction is, for example, 20 nm or more.

Steps ST21and ST25are performed in a manner the same as or similar to that in the second variation.

In step ST22, part of the GaN layer34and part of the GaN layer33are dry-etched to form the mesa step33sand the trench structure33t.

In step ST23, the Schottky metal film41is formed on the GaN layer34and the GaN layer33, which are exposed inside the mesa step33sand outside the GaN layer34and the GaN layer33left in the center. In other words, the Schottky metal film41is disposed except for the center portion and the end portion when viewed in the layering direction.

In step ST24, the insulating film42is formed to cover the exposed surface of the GaN layer33that is not covered with the Schottky metal film41.

In the above-described manner, the semiconductor element1having the mesa structure, the field plate structure, and the JBS structure is manufactured. Note that the semiconductor element1having the JBS structure is not limited thereto. For example, the semiconductor element1may be a Schottky barrier diode.

In this variation, the electric field applied to the center portion of the upper surface electrode can be reduced by having the JBS structure. According to this variation, the semiconductor element1with higher voltage resistance can be manufactured. In this variation, the leakage current can be reduced.

The embodiment disclosed by the present application can be modified without departing from the main point or the scope of the present invention. The embodiment and variations thereof disclosed in the present application can be combined as appropriate.

Embodiments have been described in order to fully and clearly disclose the technology according to the appended claims. However, the appended claims are not to be limited to the embodiments described above and may be configured to embody all variations and alternative configurations that those skilled in the art may make within the underlying matter set forth herein.