Scheduling multiple processes with varying delay sensitivity

Scheduling multiple processes with varying delay sensitivity is disclosed herein. In one example, a processor device iteratively executes a processing workload that includes a fixed-execution-time process and an adjustable-execution-time process. During each iteration of the processing workload, the processor device first determines, for that iteration, a maximum cycle time interval during which both the fixed-execution-time process and an adjustable-execution-time process will execute. The processor device further determines a maximum execution time interval for the adjustable-execution-time process, based on the maximum cycle time interval and a fixed execution time interval for the fixed-execution-time process. The processor device then modifies an adjustable execution time interval for adjustable-execution-time process in the current iteration of the processing workload based on the maximum execution time interval.

BACKGROUND

Some processing workloads executed by processor devices are performed iteratively (often tens, hundreds, or thousands of times per second). A processing workload may include processes that have varying delay sensitivity. For instance, a first process of the processing workload may have a fixed execution time and a second process may have an adjustable execution time, both of which are to be accomplished within a maximum cycle time interval for the iteration.

SUMMARY

The examples disclosed herein relate to scheduling multiple processes with varying delay sensitivity. In some embodiments, a processor device of a computing device iteratively performs a processing workload that includes a first process that is performed within a fixed execution time interval and a second process that is performed within an adjustable execution time interval. Each iteration of the processing workload is performed within a maximum cycle time interval, and thus a sum of the fixed execution time interval and the adjustable execution time interval is less than or equal to the maximum cycle time interval. During each iteration of the processing workload, the processor device determines the maximum cycle time interval for the iteration (based on, e.g., a predefined time interval, a time interval defined by a rate of an external process, and/or a time interval defined by a desired quality of results, as non-limiting examples). The processor device next determines a maximum execution time interval for the second process based on the maximum cycle time interval and the fixed execution time interval. For instance, the maximum execution time interval may be calculated as a difference between the maximum cycle time interval and the amount of time taken to execute the first process, a difference between the maximum cycle time interval and a moving average of first process execution times, a difference between the maximum cycle time interval and a configured execution time of the first process, or a difference between the maximum cycle time interval and a predicted execution time of the first process generated by a machine learning (ML) model, as non-limiting examples.

The processor device then modifies the adjustable execution time interval for the second process based on the maximum execution time interval (e.g., to ensure that the second process is performed within the maximum execution time interval for the second process). For instance, the adjustable execution time interval may be modified by selecting one of a plurality of different algorithms for performing functionality of the second process and/or by selecting one of a plurality of different parameters for the second process, as non-limiting examples. In this manner, the processor device can maximize the efficient use of the available time for executing the second process while abiding by the constraints imposed by the maximum cycle time interval of the processing workload and the fixed execution time interval of the first process.

In another example, a method is provided. The method comprises iteratively performing, by a processor device of a computing device, a processing workload, wherein each iteration of the processing workload is performed within a maximum cycle time interval, the processing workload comprises a first process and a second process, the first process is performed within a fixed execution time interval, and the second process is performed within an adjustable execution time interval. The method further comprises, during each iteration of the processing workload, determining, for the iteration, the maximum cycle time interval for the iteration. The method also comprises determining, for the iteration, a maximum execution time interval for the second process based on the maximum cycle time interval and the fixed execution time interval. The method additionally comprises modifying, for the iteration, the adjustable execution time interval for the second process based on the maximum execution time interval.

In another example, a computing device is provided. The computing device comprise a system memory and a processor device coupled to the system memory. The processor device is to iteratively perform a processing workload, wherein each iteration of the processing workload is performed within a maximum cycle time interval, the processing workload comprises a first process and a second process, the first process is performed within a fixed execution time interval, and the second process is performed within an adjustable execution time interval. The processor device is further to, during each iteration of the processing workload, determine, for the iteration, the maximum cycle time interval for the iteration. The processor device is also to determine, for the iteration, a maximum execution time interval for the second process based on the maximum cycle time interval and the fixed execution time interval. The processor device is additionally to modify, for the iteration, the adjustable execution time interval for the second process based on the maximum execution time interval.

In another example, a computer program product is provided. The computer program product is stored on a non-transitory computer-readable storage medium, and includes computer-executable instructions to cause a processor device to iteratively perform a processing workload, wherein each iteration of the processing workload is performed within a maximum cycle time interval, the processing workload comprises a first process and a second process, the first process is performed within a fixed execution time interval, and the second process is performed within an adjustable execution time interval. The computer-executable instructions further cause the processor device to, during each iteration of the processing workload, determine, for the iteration, the maximum cycle time interval for the iteration. The computer-executable instructions also cause the processor device to determine, for the iteration, a maximum execution time interval for the second process based on the maximum cycle time interval and the fixed execution time interval. The computer-executable instructions additionally cause the processor device to modify, for the iteration, the adjustable execution time interval for the second process based on the maximum execution time interval.

DETAILED DESCRIPTION

As noted above, some processing workloads executed by processor devices are performed iteratively (often tens, hundreds, or thousands of times per second). A processing workload may include processes that have varying delay sensitivity (e.g., a first process of the processing workload may have a fixed execution time and a second process may have an adjustable execution time, both of which are to be accomplished within a maximum cycle time interval for the iteration). For example, a client-server game may involve a continual processing workload loop. During each iteration of the processing workload, a game server performs a first process for receiving and processing input messages, analyzing interactions of virtual objects in the game based on the input messages, and outputting messages to the client game applications based on the interactions. The game server may also perform a second process for updating a simulation model of the game environment during each iteration of the processing workload. The second process may have an adjustable execution time, such that the frequency of updates to the simulation model, the detail with which the simulation model is rendered, and/or other factors may be adjusted to modify the execution time of the second process.

Other applications may also include iterative processing of workloads involving both fixed-execution-time processes and adjustable-execution-time processes. Such applications may include, as non-limiting examples, performing 5G virtual Radio Access Network (vRAN) processing for network efficiency, analyzing sensor and image data for manufacturing quality control, improving artificial intelligence (Al) and machine learning (ML) models based on live feedback, selecting failsafe defaults in safety-related applications, and performing video/audio transcoding for streaming applications.

Because the maximum cycle time interval of a processing workload may be inconstant (e.g., may be affected by external factors and/or by a desired quality of results, as non-limiting factors), a processor device may need to ensure that the first process and the second process are both able to execute within the maximum cycle time interval available for a given iteration of the processing workload. Accordingly, examples disclosed herein relate to scheduling multiple processes with varying delay sensitivity. In some embodiments, a processor device of a computing device iteratively performs a processing workload that includes a first process that is performed within a fixed execution time interval and a second process that is performed within an adjustable execution time interval. It is to be understood that, as used herein, the term “fixed execution time” refers to an execution time that remains relatively constant (e.g., within a given range that can be predetermined) across multiple iterations of the processing workload, but that may vary iteration to iteration. Each iteration of the processing workload is performed within a maximum cycle time interval, and thus a sum of the fixed execution time interval and the adjustable execution time interval is less than or equal to the maximum cycle time interval.

During each iteration of the processing workload, the processor device determines the maximum cycle time interval for the iteration (based on, e.g., a predefined time interval, a time interval defined by a rate of an external process, and/or a time interval defined by a desired quality of results, as non-limiting examples). The processor device next determines a maximum execution time interval for the second process based on the maximum cycle time interval and the fixed execution time interval. For instance, the maximum execution time interval may be calculated as a difference between the maximum cycle time interval and the amount of time taken to execute the first process, a difference between the maximum cycle time interval and a moving average of first process execution times, a difference between the maximum cycle time interval and a configured execution time of the first process, or a difference between the maximum cycle time interval and a predicted execution time of the first process generated by an ML model, as non-limiting examples.

The processor device then modifies the adjustable execution time interval for the second process based on the maximum execution time interval (e.g., to ensure that the second process is performed within the maximum execution time interval for the second process). For instance, the adjustable execution time interval may be modified by selecting one of a plurality of different algorithms for performing functionality of the second process and/or by selecting one of a plurality of different parameters for the second process, as non-limiting examples. In this manner, the processor device can maximize the efficient use of the available time for executing the second process while abiding by the constraints imposed by the maximum cycle time interval of the processing workload and the fixed execution time interval of the first process.

In some examples, the processor device may determine that a current execution of the second process will not complete during the adjustable execution time interval for the second process. The processor device thus may provide an intermediate result (e.g., a most recent complete result of the second process from a previous iteration of the processing workload, or a partial result of the second process from a current iteration of the processing workload, as non-limiting examples) as a result of the second process. The processor device may then persist an internal state of the second process to enable continued execution of the second process during a next iteration of the processing workload.

To illustrate a computing device on which examples may be practiced,FIG.1is provided. InFIG.1, a computing device10includes a processor device12communicatively coupled to a system memory14. The computing device10ofFIG.1and the constituent elements thereof may encompass any one of known digital logic elements, semiconductor circuits, processing cores, and/or memory structures, among other elements, or combinations thereof. Examples described herein are not restricted to any particular arrangement of elements, and it is to be understood that some embodiments of the computing device10may include more or fewer elements than illustrated inFIG.1. For example, the processor device12may further include one or more functional units, instruction caches, unified caches, memory controllers, interconnect buses, and/or additional memory devices, caches, and/or controller circuits, which are omitted fromFIG.1for the sake of clarity.

The processor device12ofFIG.1iteratively executes a processing workload16that includes a fixed-execution-time process18(referred to herein as a “first process18”) and an adjustable-execution-time process20(referred to herein as a “second process20”). Each iteration of the processing workload16is associated with a maximum cycle time interval22during which the iteration is executed, and which may vary between iterations of the processing workload16. Additionally, the first process18is associated with a fixed execution time interval24, while the second process20is associated with an adjustable execution time interval26. Because both the first process18and the second process20are executed within each iteration of the processing workload16, the sum of the fixed execution time interval24and the adjustable execution time interval26must be less than or equal to the maximum cycle time interval22. However, because the fixed execution time interval24remains relatively constant, the processor device12may need to modify the adjustable execution time interval26to ensure that each iteration of the processing workload16can be completed during the maximum cycle time interval22.

Accordingly, during each iteration of the processing workload16, the processor device12first determines, for that iteration, the maximum cycle time interval22. For example, the maximum cycle time interval22may be determined based on a predefined time interval, e.g., that is hardcoded or configured by a user or an automatic process. According to some examples, the maximum cycle time interval22may be determined based on a time interval that is defined by a rate of an external process, such as a network round-trip time, production line manufacturing speed, and the like, as non-limiting examples. Some examples may provide that the maximum cycle time interval22may be determined based on a desired quality of results, e.g., where the maximum cycle time interval22is longer for higher quality of results and shorter for lower quality of results.

The processor device12further determines a maximum execution time interval28for the second process20, based on the maximum cycle time interval22and the fixed execution time interval24. In some examples, the processor device12, during a given iteration of the processing workload16, may start a timer (“TIMER A”)30when execution of the first process18begins, and may stop the timer30when execution of the first process18ends. The processor device12thus may determine an amount of time taken to execute the first process18, and may calculate the maximum execution time interval28as a difference between the maximum cycle time interval22and the amount of time taken to execute the first process18. Some examples may provide that the timer30is used to update a moving average32of first process execution times. In such examples, the processor device12may calculate the maximum execution time interval28as a difference between the maximum cycle time interval22and the moving average32. The moving average32in some examples may comprise a weighted moving average that assigns more weight to recent execution times for the first process18. According to some examples, the maximum execution time interval28may be calculated as a difference between the maximum cycle time interval22and a configured execution time34of the first process, or as a difference between the maximum cycle time interval22and a predicted execution time36of the first process generated by an ML model38.

Once the maximum execution time interval28for the second process20is determined, the processor device12modifies the adjustable execution time interval26for the current iteration of the processing workload16based on the maximum execution time interval28. In particular, the processor device12in some examples may modify the adjustable execution time interval26to ensure that the second process20is performed within the maximum execution time interval28for the second process (which in turn ensures that both the first process18and the second process20are executed within the maximum cycle time interval22). In some examples, the processor device12may start a timer (“TIMER B”)40during a given iteration of the processing workload16when execution of the second process20begins, and may stop the timer40when execution of the second process20ends. In this manner, the processor device12may use the timer40to determine and record an amount of time taken to execute the second process20(i.e., the recorded execution time42). In a subsequent iteration, the processor device12may modify the adjustable execution time interval26for the second process20based on the recorded execution time42taken to execute the second process20in a previous iteration of the processing workload16.

The processor device12according to some examples may also modify the adjustable execution time interval26for the second process20by, e.g., selecting one of a plurality of different algorithms for performing functionality of the second process20, and/or by selecting one of a plurality of different parameters for the second process20. For instance, if more time is available in the maximum execution time interval28, the processor device12may select an algorithm and/or a parameter for the second process20that provides more precise or higher quality results at a cost of longer execution time. Conversely, if less time is available in the maximum execution time interval28, the processor device12may select an algorithm and/or a parameter for the second process20that provides less precise or lower quality results, but in less time.

In some examples, the processor device12may determine that a current execution of the second process20will not complete during the adjustable execution time interval26for the second process20. This may occur, for example, due to an unpredicted variation in execution time of the second process20. Some such examples may provide that the processor device12may provide a most recent complete result44of the second process20(e.g., from a previous iteration of the processing workload16), or may provide a partial result46of the second process20. The processor device12may then persist an internal state48of the second process20for continued execution during a next iteration of the processing workload16.

It is to be understood that, while the processing workload16ofFIG.1is shown as comprising a single fixed-execution-time process18and a single adjustable-execution-time process20, the operations described above with respect toFIG.1are equally applicable to embodiments in which a processing workload includes multiple fixed-execution-time processes and/or multiple adjustable-execution-time processes. In such embodiments, the maximum cycle time interval would be determined as a sum of the fixed execution time interval(s) for the multiple fixed-execution-time process(es) and the adjustable execution time interval(s) for the multiple adjustable-execution-time process(es). Likewise, the maximum execution time interval for the adjustable-execution-time process(es) would be calculated based on the maximum cycle time interval and the fixed execution time interval(s) for the multiple fixed-execution-time process(es). In embodiments with multiple adjustable-execution-time processes, the processor device12could independently modify the adjustable execution time interval for each of the adjustable-execution-time processes to ensure that all of the adjustable-execution-time processes are able to execute within the maximum execution time interval.

FIG.2illustrates execution of an exemplary processing workload50(corresponding to the processing workload16ofFIG.1) according to one example. InFIG.2, a flow52represents operations for executing an exemplary fixed-execution-time process (such as the first process18of FIG.1), and therefore the time required to execute the flow52corresponds to the fixed execution time interval24ofFIG.1. Likewise, a flow54ofFIG.2represents operations for executing an exemplary adjustable-execution-time process (such as the second process20ofFIG.1), and thus the time required to execute the flow54corresponds to the adjustable execution time interval26ofFIG.1. Execution of the flow52and the flow54occurs within a maximum cycle time interval for the processing workload50.

Operations in the example ofFIG.2begin in the flow52, with the processor device12starting a timer A (such as the timer30ofFIG.1) (block56). The processor device12then begins execution of the fixed-execution-time process (block58). The operations of block58may include any operations required to be performed as part of the fixed-execution-time process prior to beginning execution of the adjustable-execution-time process of flow54. Subsequently, the processor device12computes the maximum executable time interval for the adjustable-execution-time process (corresponding to the maximum execution time interval28for the second process20ofFIG.1) (block60). The processor device12then pauses timer A (block62), and begins execution of the adjustable-execution-time process (block64). Operations then resume at block66of the flow54.

In the flow54, the processor device12first modifies the adjustable execution time interval for the adjustable-execution-time process (e.g., to ensure that the operations of the flow54are completed within the maximum executable time interval calculated at block60) (block66). The processor device12then starts a timer B (such as the timer40ofFIG.1) (block68), and executes the operations constituting the adjustable-execution-time process (block70). When the operations of block70are complete, the processor device12stops the timer B (block72), and records and resets the timer B (block74). As discussed above, recording the timer B may enable the processor device12to track execution times of the adjustable-execution-time process over multiple iterations, and subsequently use the tracked execution times to modify the adjustable execution time interval during future iterations of the processing workload50.

The processor device12then determines whether the time limit imposed by the maximum executable time interval calculated at block60of the flow52has been reached (block76). If not, operations continue at block68. However, if the processor device12determines at decision block76that the time limit imposed by the maximum executable time interval has been reached, execution of the adjustable-execution-time process ends (block78), and execution of the fixed-execution-time process resumes at block80of the flow52.

Returning to the flow52, the processor device12resumes the timer A (block80). The processor device12then provides the result of the current iteration of the processing workflow50(block82). The processor device12stops the timer A (block84), and records and resets the timer A (block86). As noted above, recording the timer A may enable the processor device12to track and average execution times of the fixed-execution-time process over multiple iterations, which may allow the maximum execution time interval for the adjustable-execution-time process to be more precisely calculated. If time remains within the maximum cycle time interval for the processing workload50, the processor device12enters a sleep mode (block88). A next iteration90of the processing workload50then begins again, with operations resuming at block56of the flow52.

FIGS.3A-3Cprovide a flowchart92illustrating exemplary operations for scheduling multiple processes with varying delay sensitivity, according to one example. For the sake of clarity, elements ofFIG.1are referenced in describingFIGS.3A-3C. InFIG.3A, operations begin with the processor device12of the computing device10iteratively performing the processing workload16, wherein each iteration of the processing workload16is performed within the maximum cycle time interval22, the processing workload16comprises the first process18and the second process20, the first process18is performed within the fixed execution time interval24, and the second process20is performed within the adjustable execution time interval26(block94).

Next, during each iteration of the processing workload16, the processor device12performs a series of operations (block96). The processor device12determines, for the iteration, the maximum cycle time interval22for the iteration (block98). In some examples, operations of block98for determining the maximum cycle time interval22may include determining the maximum cycle time interval22for the iteration based on one or more of a predefined time interval; a time interval defined by a rate of an external process; and a time interval defined by a desired quality of results (block100). In some examples, the processor device12may also determine an amount of time taken to execute the first process18(block102). The processor device12may then update the moving average32of first process execution times with the amount of time taken to execute the first process18(block104). Operations then continue at block106ofFIG.3B.

Referring now toFIG.3B, the processor device12continues performing operations during each iteration of the processing workload16(block96). The processor device12determines, for the iteration, a maximum execution time interval28for the second process20based on the maximum cycle time interval22and the fixed execution time interval24(block106). In some examples, the maximum execution time interval28for the second process20may comprise a difference between the maximum cycle time interval22and the amount of time taken to execute the first process18(block108). Some examples may provide that the maximum execution time interval28for the second process20comprises a difference between the maximum cycle time interval22and the moving average32of first process execution times (block110). The moving average32of first process execution times may comprise, e.g., a weighted moving average. According to some examples, the maximum execution time interval28for the second process20comprises a difference between the maximum cycle time interval22and the configured execution time34of the first process18(block112). In some examples, the maximum execution time interval28for the second process20comprises a difference between the maximum cycle time interval22and the predicted execution time36of the first process18generated by the ML model38(block114). Operations then continue at block116ofFIG.3C.

Turning now toFIG.3C, the processor device12continues performing operations during each iteration of the processing workload16(block96). The processor device12modifies, for the iteration, the adjustable execution time interval26for the second process20based on the maximum execution time interval28(block116). Exemplary operations for modifying the adjustable execution time interval26for the second process20are discussed in greater detail below with respect toFIG.4.

In some examples, the processor device12may determine that a current execution of the second process20will not complete during the adjustable execution time interval26for the second process20(block118). In response, the processor device12may provide one of a most recent complete result44of the second process20and a partial result46of the second process20(block120). The processor device12may also persist an internal state48of the second process20for continued execution during a next iteration of the processing workload16(block122).

To illustrate exemplary operations for modifying an adjustable execution time interval for an adjustable-execution-time process according to one example,FIG.4provides a flowchart124. Elements ofFIG.1are referenced in describingFIG.4for the sake of clarity. It is to be understood that the operations illustrated inFIG.4may correspond to the operations for modifying the adjustable execution time interval26described in block116ofFIG.3C. Thus, in some examples, the processor device12may modify the adjustable execution time interval26for the second process20such that the second process20is performed within the maximum execution time interval28for the second process20(block126). Some examples may provide that the operations of block126for modifying the adjustable execution time interval26for the second process20such that the second process20is performed within the maximum execution time interval28for the second process20may include the processor device12first determining an amount of time taken to execute the second process20(block128). The processor device12in such examples next records the amount of time taken to execute the second process20(i.e., as the recorded execution time42) (block130). The processor device12then modifies the adjustable execution time interval26for the second process20based on the recorded execution time42taken to execute the second process20in a previous iteration of the processing workload16(block132). In some examples, the operations of block126for modifying the adjustable execution time interval26for the second process20such that the second process20is performed within the maximum execution time interval28for the second process20include the processor device12selecting one or more of one of a plurality of different algorithms for performing functionality of the second process20, and one of a plurality of different parameters for the second process20(block134).

FIG.5is a simpler block diagram of the computing device10ofFIG.1for scheduling multiple processes with varying delay sensitivity, according to one example. InFIG.5, a computing device136includes a processor device138communicatively coupled to a system memory140. The processor device138ofFIG.5iteratively executes a processing workload142that includes a fixed-execution-time process144(referred to herein as a “first process144”) and an adjustable-execution-time process146(referred to herein as a “second process146”). Each iteration of the processing workload142is associated with a maximum cycle time interval148during which the iteration is executed, and which may vary between iterations of the processing workload142. Additionally, the first process144is associated with a fixed execution time interval150, while the second process146is associated with an adjustable execution time interval152.

During each iteration of the processing workload142, the processor device138first determines, for that iteration, the maximum cycle time interval148. The processor device138further determines a maximum execution time interval154for the second process146, based on the maximum cycle time interval148and the fixed execution time interval150. Once the maximum execution time interval154for the second process146is determined, the processor device138modifies the adjustable execution time interval152for the current iteration of the processing workload142based on the maximum execution time interval154.

FIG.6provides a flowchart156illustrating a simplified method for scheduling multiple processes with varying delay sensitivity on the computing device136ofFIG.5, according to one example. Elements ofFIG.5are referenced in describingFIG.6for the sake of clarity. Operations inFIG.6begin with the processor device138of the computing device136iteratively performing the processing workload142, wherein each iteration of the processing workload142is performed within a maximum cycle time interval148, the processing workload142comprises the first process144and the second process146, the first process144is performed within the fixed execution time interval150, and the second process146is performed within the adjustable execution time interval152(block158). The processor device138then performs a series of operations during each iteration of the processing workload142(block160). The processor device138determines, for the iteration, the maximum cycle time interval148for the processing workload142(block162). The processor device138next determines, for the iteration, a maximum execution time interval154for the second process146based on the maximum cycle time interval148and the fixed execution time interval150(block164). The processor device138then modifies, for the iteration, the adjustable execution time interval152for the second process146based on the maximum execution time interval154(block166).

FIG.7is a block diagram of a computing device168, such as the computing device10ofFIG.1or the computing device136ofFIG.5, suitable for implementing examples according to one example. The computing device168may comprise any computing or electronic device capable of including firmware, hardware, and/or executing software instructions to implement the functionality described herein, such as a computer server, a desktop computing device, a laptop computing device, a smartphone, a computing tablet, or the like. The computing device168includes a processor device170, a system memory172, and a system bus174. The system bus174provides an interface for system components including, but not limited to, the system memory172and the processor device170. The processor device170can be any commercially available or proprietary processor.

The system bus174may be any of several types of bus structures that may further interconnect to a memory bus (with or without a memory controller), a peripheral bus, and/or a local bus using any of a variety of commercially available bus architectures. The system memory172may include non-volatile memory176(e.g., read-only memory (ROM), erasable programmable ROM (EPROM), electrically EPROM (EEPROM), etc.), and volatile memory178(e.g., random access memory (RAM)). A basic input/output system (BIOS)180may be stored in the non-volatile memory176and can include the basic routines that help to transfer information among elements within the computing device168. The volatile memory178may also include a high-speed RAM, such as static RAM, for caching data.

A number of modules can be stored in the storage device182and in the volatile memory178, including an operating system184and one or more program modules186which may implement the functionality described herein in whole or in part. It is to be appreciated that the examples can be implemented with various commercially available operating systems184or combinations of operating systems184. All or a portion of the examples may be implemented as a computer program product stored on a transitory or non-transitory computer-usable or computer-readable storage medium, such as the storage device182, which includes complex programming instructions, such as complex computer-readable program code, to cause the processor device170to carry out the steps described herein. Thus, the computer-readable program code can comprise software instructions for implementing the functionality of the examples described herein when executed on the processor device170. The processor device170may serve as a controller, or control system, for the computing device168that is to implement the functionality described herein.

An operator may also be able to enter one or more configuration commands through a keyboard (not illustrated), a pointing device such as a mouse (not illustrated), or a touch-sensitive surface such as a display device (not illustrated). Such input devices may be connected to the processor device170through an input device interface188that is coupled to the system bus174but can be connected by other interfaces, such as a parallel port, an Institute of Electrical and Electronic Engineers (IEEE) 13170 serial port, a Universal Serial Bus (USB) port, an infrared (IR) interface, and the like.

The computing device168may also include a communications interface190suitable for communicating with a network as appropriate or desired. The computing device168may also include a video port192to interface with a display device to provide information to a user. Individuals will recognize improvements and modifications to the preferred examples of the disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.