Process for recess-free planarization of shallow trench isolation

An improved and new process for fabricating planarized isolation trenches, wherein sharp corners at the top periphery of the trench are eliminated and erosion of insulating material at the edges of isolation trenches is suppressed, has been developed. The process uses a two layer mask to etch the isolation trench, followed by an isotropic etch to recess the first layer of the mask. An oxide liner is formed in the trench and across the exposed edge of the trench resulting in rounding the corners of the trench. Then, a second isotropic etch is used to recess the edge of the second mask layer, so that its opening now is beyond the edge of the trench. An oxide layer is conformally deposited over all exposed surfaces and fills the trench. After CMP to planarize the oxide layer, the remaining oxide fills the trench and, also, extends a small distance beyond the edge of the trench and serves to protect edge of the trench during subsequent etching.

BACKGROUND OF THE INVENTION 
(1) Field of the Invention 
This invention relates to a method of fabrication used to form isolation 
regions in semiconductor devices and particularly to a method to form 
shallow trenches for isolation regions in semiconductor devices and more 
specifically to a method to form shallow trench isolation (STI). 
(2) Description of Related Art 
As semiconductor integrated circuits progress toward greater 
micro-miniaturation active devices are packed into ever smaller areas and 
electrical isolation between active devices becomes an extremely important 
issue. Shallow trenches filled with insulating material have proven to be 
most desirable for isolating active devices. However, the trench isolation 
process still suffers from a problem of sub-threshold "double-hump" in I-V 
characteristics caused by sharp corners at the top periphery of the 
isolation trench. In addition, trench isolation processes also suffer from 
a problem of eroded insulating material at trench edges after conventional 
shallow trench isolation processing. This erosion of insulating material 
produces "divots" at the edges of the trench and, also, worsens the 
abnormal device characteristics, such as the "double hump" in I-V curves, 
and, additionally makes subsequent gate etching more difficult. Therefore, 
a challenge in the industry is to provide a means of formation of 
planarized isolation trenches having rounded corners at the top periphery 
of the trenches and without the formation of "divots" at the edges of the 
trenches. 
Numerous improvements to methods of forming planarized isolation trenches 
have been invented. For example, U.S. Pat. No. 5,578,518 entitled "Method 
of Manufacturing a Trench Isolation Having Round Corners" granted Nov. 26, 
1996 to Hidetoshi Koike et al describes a method of forming shallow trench 
isolation which produces rounded corners on the STI. 
Also, U.S. Pat. No. 5,258,332 entitled "Method of Manufacturing 
Semiconductor Devices Including Rounding of Corner Portions by Etching" 
granted Nov. 2, 1993 to Keiji Horioka et al shows methods of forming 
rounded STI corners using plasma etching in gas mixtures including 
fluorine and oxygen. 
U.S. Pat. No. 5,674,775 entitled "Isolation Trench With a Rounded Top Edge 
Using an Etch Buffer Layer" granted Oct. 7, 1997 to Chin-Hsiung Ho et al 
shows a method of forming STI with rounded corners using a sacrificial 
spacer during etching of the trench. 
U.S. Pat. No. 5,433,794 entitled "Spacers Used To Form Isolation Trenches 
With Improved Corners" granted Jul. 18, 1995 to Pierre C. Fazan et al 
describes a method of forming trench isolation in which the isolating 
material extends over the peripheral edge of the trench, thereby creating 
a small rounded cap over the trench. 
U.S. Pat. No. 4,876,217 entitled "Method of Forming Semiconductor Structure 
Isolation Regions" granted Oct. 24, 1989 to Peter J. Zdebel describes a 
method of forming dielectric isolation regions in a semiconductor 
substrate, whereby a trench is etched in the semiconductor substrate, the 
trench is lined with a first dielectric layer, then filled with a second 
dielectric layer, followed by masking and removal of the second dielectric 
layer outside the trench region. 
U.S. Pat. No. 5,190,889 entitled "Method of Forming Trench Isolation 
Structure With Germanium Silicate Filling" granted Mar. 2, 1993 to Stephen 
S. Poon et al describes a method of forming rounded trenches. The method 
uses a barrier layer liner in the trench and a germanium silicate filling 
material. 
U.S. Pat. No. 4,994,406 entitled "Method of Fabricating Semiconductor 
Devices Having Deep and Shallow Isolation Structures" granted Feb. 19, 
1991 to Barbara Vasquez shows a method of forming isolation structures in 
semiconductor substrates whereby both deep trench isolation elements and 
shallow dielectric isolation elements may be fabricated at variable 
widths. 
The present invention is directed to a novel method of fabricating 
planarized isolation trenches, wherein sharp corners at the top periphery 
of the trench are eliminated and erosion of insulating material at the 
edges of isolation trenches is suppressed, 
SUMMARY OF THE INVENTION 
It is a general object of the present invention to provide an improved 
method of forming planarized isolation trenches for use in semiconductor 
integrated circuits. 
A more specific object of the present invention is to provide an improved 
method of forming planarized isolation trenches for use in semiconductor 
integrated circuits, wherein sharp corners at the top periphery of the 
trench are eliminated. 
Another object of the present invention is to provide an improved method of 
forming planarized isolation trenches for use in semiconductor integrated 
circuits, wherein erosion of insulating material at the edges of isolation 
trenches is suppressed. 
In accordance with the present invention, the above and other objectives 
are realized by using a method of forming a trench isolation region in a 
surface of a semiconductor substrate for the purpose of isolating active 
device areas, the method comprising the steps of: providing the 
semiconductor substrate containing active devices; forming a first oxide 
layer on the surface of the semiconductor substrate; forming a silicon 
nitride layer on the first oxide layer; removing portions of the silicon 
nitride layer and the first oxide layer to form an opening in the silicon 
nitride layer and the first oxide layer to expose a selected portion of 
the surface of the semiconductor substrate; etching the semiconductor 
substrate through the opening to form a trench in the semiconductor 
substrate; subjecting the first oxide layer to side etching through the 
openings to form a recess in the first oxide layer and, also, forming an 
exposed edge of the semiconductor substrate at the boundary with the 
trench; forming a second oxide layer over all exposed silicon surfaces 
including the inside of the trench and exposed edge of the semiconductor 
substrate at the boundary with the trench; subjecting the silicon nitride 
layer to isotropic etching which decreases the thickness of the silicon 
nitride layer and recesses the edge of the silicon nitride layer at the 
opening in the silicon nitride layer; forming a third oxide layer over all 
exposed surfaces, filling the trench in the semiconductor substrate with 
the third oxide layer; removing by CMP the third oxide layer, stopping in 
the silicon nitride layer, to leave a portion of the third oxide layer 
only in the trench, and to form a substantially planar surface between the 
remaining silicon nitride layer and the remaining third oxide layer; 
removing by etching the remaining silicon nitride layer; and removing the 
remaining first oxide layer on the surface of the semiconductor substrate, 
thereby forming a planarized oxide filled trench.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The new and improved method of forming planarized isolation trenches for 
use in semiconductor integrated circuits will now be described in detail. 
Referring to FIGS. 1A-1H, semiconductor substrate 10 contains active 
devices (not shown). Semiconductor substrate 10 is preferably single 
crystal silicon, but may be any semiconductor material, such as silicon or 
germanium or silicon or gallium arsenide used in the fabrication of 
integrated circuits. Layer 11 comprises silicon oxide having a thickness 
between about 50 and 500 Angstroms. Layer 12 comprises silicon nitride 
having a thickness between about 1000 and 3000 Angstroms. Layers 11 and 12 
are patterned with a window 13 defining the region where the isolation 
trench is to be formed. 
FIG. 1A shows trench 14 etched into semiconductor substrate 10. Next, as 
shown in FIG. 1B, silicon oxide layer 11 is subjected to side etching 
through the opening in layers 12 and 11. An isotropic etch such as 
buffered or dilute hydrofluoric acid in H.sub.2 O is used. This etch has 
high selectivity for etching silicon oxide preferentially over silicon 
nitride. Typically the etch rate ratio for silicon oxide to silicon 
nitride is between about 20 and 500. This etch, also, has a high 
selectivity for etching silicon oxide preferentially over silicon. 
Typically the etch rate ratio for silicon oxide to silicon is between 
about 20 and 1000. The side etching of silicon oxide layer 11 undercuts 
silicon nitride layer 12 forming a recess 16 in silicon oxide layer 11. 
The recess 16 extends beyond the edge of the etched trench for a distance 
between about 30 and 300 Angstroms. During the side etching of silicon 
oxide layer 11 slight rounding of the top corner of the trench etched into 
the silicon substrate occurs. 
Referring to FIG. 1C, a second oxide layer 17 is formed over all exposed 
silicon surfaces including the inside of the trench and exposed edge of 
the semiconductor substrate at the boundary with the trench. Formation of 
second oxide layer 17 produces an oxide liner within the etched trench and 
across the top corner (now rounded) of the trench. The second oxide layer 
17 abuts the first oxide layer 11, as shown in FIG. 1C. The second oxide 
layer 17 is formed by thermal oxidation in an oxygen-steam ambient, at a 
temperature between about 800.degree. and 1000.degree. C., to a thickness 
between about 50 and 500 Angstroms. The corner of the trench is rounded 
during the formation of the second oxide layer 17 because of the faster 
oxidation rate at the corner, so-called two dimensional effect, when 
oxidation occurs at the recess 16 and at the trench 14. 
Referring to FIG. 1D, an isotropic etch which selectively etches silicon 
nitride preferentially to silicon oxide is used to recess the edge of the 
opening in the silicon nitride layer 12. An isotropic etch such as hot 
phosphoric acid is used. Typically the etch rate ratio for silicon nitride 
to silicon oxide is between about 20 and 100. It is desirable that the 
edge of the opening in silicon nitride layer 12 be recessed between about 
200 and 600 Angstroms. At the same time the thickness of silicon nitride 
layer 12 is reduced by between about 200 and 600 Angstroms, as shown in 
FIG. 1D. 
Now referring to FIG. 1E, third oxide layer 18 is formed over all exposed 
surfaces, filling the trench in the semiconductor substrate. Third oxide 
layer 18 may be silicon oxide deposited conformally by LPCVD (Low Pressure 
Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor 
Deposition) processes to a thickness between about 2000 and 10,000 
Angstroms. 
Next, CMP (Chemical Mechanical Polishing) is used to planarize and remove 
the third oxide layer, stopping in the silicon nitride layer, to leave a 
portion of the third oxide layer only in the trench, and to form a 
substantially planar surface between the remaining silicon nitride layer 
and the remaining third oxide layer, as shown in FIG. 1F. After CMP the 
remaining third oxide fills the trench and, also, extends a distance of 
between about 200 and 600 Angstroms beyond the edge of the trench, as 
shown in FIG. 1F. This extension will serve to protect edge of the trench 
during subsequent etching. 
Referring to FIGS. 1G and 1H, the remaining silicon nitride layer is 
removed by etching in a hot phosphoric acid solution, followed by etching 
of the first oxide layer 11 in a buffered or dilute hydrofluoric acid 
solution in H.sub.2 O. During etching to remove oxide layer 11 the edges 
of the trench are protected by the third oxide layer 18 remaining in the 
trench and extending beyond the edge of the trench for a distance between 
about 200 and 600 Angstroms. 
While the invention has been particularly shown and described with 
reference to the preferred embodiments thereof, it will be understood by 
those skilled in the art that various changes in form and details may be 
made without departing from the spirit and scope of the invention.