A photographic device typically employing a CCD element as a shutter is arranged to have an improved display system. The display system displays the picture number per unit time and the image information storage time by using different display conditions so as to avoid confusion as to what is being displayed. The device enables the photographing picture number per unit time to be taken as a multiple series of 2, such as 60, 30, 15, 8, 4, 2 1 . . . , pictures/second in order to make the numerical series of the photographing picture number common with that for the storage time of the image information so that the image information storage time and the photographing picture number per unit time can be displayed with a common display means.

BACKGROUND OF THE INVENTION: 
1. Field of the Invention: 
The present invention relates to a display system of an image recording 
device. 
2. Description of the Prior Art: 
Along with the recent advance in IC technology the solid image pick-up 
device, such as the CCD, has been progressively developed and made use of 
with the VTR and so on. 
Because this kind of solid image pick-up device can store the image 
information for a predetermined time, transfer the stored charge 
information to an analog shift register via the charge transfer means and 
output it time serially, it is possible to use the charge transfer means 
as the shutter to control the storage time, namely the stored charge 
amount of the image information when the brightness of the object is 
comparatively low. 
Consequently, by repeatedly carrying out storage, reading out and recording 
of the image information with a predetermined timing, it is possible to 
carry out continuous photography in the same way as with a power winder in 
an ordinary camera. 
Furthermore, in this case the photography frame number per unit time can 
optionally be set. 
However, it is difficult to indicate clearly to the operator the frame 
number per unit time if the frame number can be changed in several steps. 
For example, although it is possible to display the above frame number with 
a 7 segment display device in the view finder, the frame number is 
displayed together with other data such as storage time. Accordingly, a 
plural number of the display devices are needed and it is difficult and 
inconvenient to judge what is displayed. 
It is an object of the present invention to provide an improved image 
pick-up device free from the above inconvenience. 
It is another object of the present invention to provide a simplified 
display system. 
It is another object of the present invention to provide a series of the 
continuous photographing picture number per unit time in order to attain a 
simplified display system. 
It is a further object of the present invention to provide a simplified 
display system which is easy to observe, in accordance with various 
photographing modes. 
SUMMARY OF THE INVENTION: 
In order to fulfill the above objects, an embodiment of the present 
invention is so constructed that the photographing picture number per unit 
time can also be displayed with the display means for image information 
storage time in such a manner that the display device is remarkably 
simplified. 
Furthermore, the embodiment is so constructed that image information 
storage time and the photographing picture number are displayed with 
different display conditions in order to avoid confusion, making it 
remarkably easy to observe and to judge what is displayed. 
For example, by making one display with continuous lighting and the other 
with flickering, both can be effectively confirmed even if two kinds of 
displays are simultaneous. 
Furthermore, in accordance with the embodiment of the present invention the 
photographing picture number per unit time is taken as a multiple series 
of 2 such as 60, 30, 15, 8, 4, 2, 1 . . . pictures/second in order to make 
the numerical series of the photographing picture number common with that 
for the storage time of the image information, so that the image 
information storage time and the photographing picture number per unit 
time can be displayed with a common display means.

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS: 
FIG. 1 shows an embodiment of the circuit of the present invention. In the 
drawing, the reference characters LMK identify a light measuring circuit 
in which the photo current produced in a photoelectric transducing element 
SP is logarithmically compressed by a logarithmic compressing element LD 
via a light measuring high input impedance operational amplifier MP, the 
reference characters IFS identify an information input circuit such as the 
diaphragm and an exposure calculating amplifier OPA calculates the light 
measurement information and the set information. From the output of the 
exposure calculating amplifier OPA the storage time information of the 
image is delivered to be A-D converted by an A-D converter AD1. A pulse 
generating circuit OSC produces timing pulses .phi.1 and .phi.2, as shown 
in FIG. 3. The timing pulse .phi.1 is applied to the S-terminal of the A-D 
converter AD1, which starts the A-D conversion in synchronization with the 
rising of the timing pulse .phi.1. As is shown in FIG. 3, the A-D 
conversion is terminated in one pulse and with the termination the output 
level at the E-terminal becomes high. Reference characters LT1 identify a 
latch circuit, having input terminals Q0, Q1, Q2, Q3 respectively 
connected to the output terminals Q0, Q1, Q2, Q3 of the A-D converter AD1. 
An AND gate AN1 applies the latch signal to the latch circuit LT1, whereby 
one input of the AND gate AN1 is connected to the E-terminal which 
delivers the A-D conversion termination pulse of the A-D converter AD1 so 
as to receive the output of the converter AD1 while the output level of 
the AN1 is high and latch it while the level is low. Furthermore, 
reference characters AN2-AN9 and OR1-OR4 identify AND gates and OR gates. 
The output terminals Q3, Q2, Q1, Q0 of the latch circuit LT1 are 
respectively connected to the AND gates AN2-AN5, while the output 
terminals Q3, Q2, Q1, Q0 of an encoder ECD are respectively connected to 
the AND gates AN6-AN9. 
This encoder ECD encodes the number of the pictures picked up per unit time 
set at the pick-up frame speed setting means STD as the image number 
designating means. 
The AND gates AN2-AN5 and gates AN6-AN9 are respectively connected to the 
OR gates OR1-OR4. Reference characters DCD identify a decoder, to whose 
input the terminals Q3, Q2, Q1, Q0 and the OR gates OR1, OR2, OR3, OR4 are 
respectively connected and whose output terminals D0, D1-D13 are grounded 
via light emitting diodes DE0, DE1-DE13. The light emitting diodes DE0, 
DE1-DE13 display the storage time or the pick-up frame speed during 
continuous photography. A photography mode change over switch SW is in the 
continuous photography mode at the side of C and in the single photography 
mode at the side of S, being applied with the voltage Vcc respectively via 
the resistances, R1, R2. 
A frequency divider DIV divides the frequency of the output .phi.1 of the 
pulse generating circuit OSC for making light emitting elements LE0-LE13 
flicker via the AND gates AN6-AN9 in the continuous photography mode to 
display clearly the pick-up frame speed and the shutter time differently. 
Reference characters SM identify a solid image pick-up element, reference 
characters PUK identify a pulse control circuit and reference characters 
RCK identify a conventional recording system circuit, whereby they 
constitute the image recording device. The terminals Q0, Q1, Q2, Q3 of the 
PULSE CONTROL CIRCUIT PUK are respectively connected to the terminals Q0, 
Q1, Q2, Q3 of the encoder ECD, whereby when the mode change over switch SW 
is set at the side of C, a low level signal is applied to the CK terminal 
of the pulse control circuit PUK so that the control pulse for 
photographing at the frequency on the basis of the pick-up frame speed set 
at the pick-up frame speed setting means STD is respectively produced and 
delivered to the recording system circuit RCK. 
FIG. 2 shows an embodiment of the display in the view finder of the image 
pick-up device. 
Reference characters SH identify a scale plate, on which the multiple 
series of 2 for example 2000 (.apprxeq.2.sup.11), 1000 
(.apprxeq.2.sup.10), 500 (.apprxeq.2.sup.9), 250 (.apprxeq.2.sup.8), 125 
(.apprxeq.2.sup.7), 60 (.apprxeq.2.sup.6), 30 (.apprxeq.2.sup.5), 15 
(.apprxeq.2.sup.4), 8 (.apprxeq.2.sup.3), 4 (.apprxeq.w.sup.2), 2 
(.apprxeq.2.sup.1), 1 (.apprxeq.2.sup.0), 1/2 (.apprxeq.2.sup.-1), 1/4 
(.apprxeq.2.sup.-2) are scaled. They are considered as frame speed (F/S), 
while their reciprocal numbers correspond to storage time (TV). 
Hereby, even if the storage time TV is not considered as the reciprocal 
numbers of the scale values, it is possible to make the values correspond 
to the scale value when for example 2000-1/2000 are scaled. However, this 
means too many scale values, which is inconvenient. In accordance with the 
present invention the scale values are 2.sup.n (n: positive or negative 
integer), so that a symmetry is constituted with reference to 1 
eliminating part of the scale. This effect can be obtained not only from 
2.sup.n but also from m.sup.n (m: constant). 
As described above, in accordance with the present invention the series of 
values of the storage time TV are common with that of the value of the 
frame speed F/S so that the display can be remarkably simple. 
Reference characters FA identify a view finder. For example, when the 
photography mode change over switch SW is set in the single photography 
mode at the side of S, the output of the exposure calculating circuit OPA 
delivers the storage time TV of 1/250 sec., the AND gates AN2-AN5 open, 
while AN6-AN9 close so that the light emitting element LE10 flickers in 
synchronization with .phi.2 and the storage time TV is displayed, as shown 
in FIG. 2. 
On the other hand, when the photography mode change over switch SW is set 
in the continuous photography mode at the side of C, the AND gates AN6-AN9 
open, while AN2-AN5 close so that the storage time TV disappears, whereby 
the light emitting element LE4 flickers at a frequency, for example, 1/4 
as high as that of the clock .phi.1 displaying the pick-up frame speed set 
at the pick-up frame speed F/S setting means STD, for example, 4 frames 
per second, as shown in FIG. 2. 
FIG. 3 is a timing chart of the important part of the circuit shown in FIG. 
1. The image information stored during the time between t0-t1, in the 
solid image pick-up device SM is transferred to the analog shift register 
via a conventional change transfer means during the time between t1-t2, 
and time is serially read out and recorded during the time between t2-t3, 
while new image information is stored. 
Then, the picture information stored in the solid image pick-up device SM 
during the time between t2-t3 is transferred to the analog shift register 
via the charge transfer means during the time between t3-t4 and the time 
is serially read out and recorded, while new image information is stored. 
Thus, the above operation is repeated. 
Display SM1 shows that 60 frames of the information are recorded per 
second, a display SM2 shows that 30 frames are recorded per second and a 
display SM3 shows that 15 frames are recorded per second. 
Furthermore, although in continuous photography of the present embodiment 
the storage time is not displayed, it is possible to display both the 
storage time TV and the frame speed F/S. Because the flickering frequency 
of the shutter time is different from that of the photographing frame 
speed F/S, it is possible to tell one from the other. 
Furthermore, it goes without saying that either one can be displayed with 
flickering. 
As described above, in accordance with the present invention the 
photographing frame speed F/S at the time of continuous photography can be 
characteristically displayed easily and rationally in the view finder. 
Hereby, it goes without saying that the storage time TV can be manually 
set. 
Furthermore, because in accordance with the present invention the storage 
time TV is selected from the numerical series of 2.sup.n, it is suited for 
the APEX calculation and the calculating circuit can be constituted 
easily.