Digital to analog converter and display incorporating the same

A digital to analog converter is provided. The digital to analog converter comprises a digital data input, a decoder, a re-queuing circuit and a plurality of current cells. The digital data input receives a digital input data. The decoder decodes the digital input data and generates a decoded data. The re-queuing circuit changes a bit sequence of decoded data and outputs a re-queued data. Each current cell comprises a current source and an internal logic gate. The internal logic gate determines whether the current source outputs the current according to the re-queued data.

This application claims the benefit of Taiwan application Serial No. 93,116,403, filed Jun. 8, 2004, the subject matter of which is incorporated herein by reference.

BACKGROUND

The invention relates in general to a digital to analog converter, and more particularly to a current-driven thermometer code digital to analog converter.

Organic light emitting diode (OLED) displays are among currently prevailing flat panel displays. Since the brightness of an OLED is proportional to the current conducted thereby, variations of current level have great impact on uniformity of an OLED display, and improvement of a current-driving structure increases display uniformity. Thus, the quality of a current-driven digital to analog converter is critical to current output and display quality.

A thermometer code digital to analog converter is current driven and has advantages such as fast response and accurate current output. The operational duration of current sources in a conventional structure, however, differ.

FIGS. 1A˜1Dare illustrations of current outputs of a 4-bit thermometer code digital to analog converter. The digital input data ofFIGS. 1A˜1Dare (0000), (0001), (1000) and (1111), respectively. The shadowed current sources are turned on to output current. FromFIGS. 1A˜1D, it is found that a current source101is always on except in the case where the digital input data is (0000). To the contrary, a current source116is always off except in the case where the digital input data is (1111). In a conventional structure of a current driver, a thin film transistor in the current cell101is often influenced by current stress. This results in device degradation and thermometer code digital to analog converter malfunctions.

FIG. 2Ashows a conventional 6-bit thermometer code digital to analog converter. The thermometer code digital to analog converter includes digital data input B1˜B6, a column decoder202, a row decoder204and a current cell array206. The digital data input B1˜B6represent the least significant bit (LSB) to the most significant bit (MSB) of the 6-bit digital input data, respectively. The column decoder202decodes the bits B1˜B3and outputs signals C1˜C7. The column decoder204decodes the bits B4˜B6and outputs signals R2˜R8. R1is a fixed high voltage level while C8and R9are fixed at a low voltage level. The current cell array206includes 64 current cells A(1,1)˜A(8,8). Each of the current cells A(1,1)˜A(8,8) includes a current mirror CMR and a logic gate LG, as shown inFIG. 2B. The logic gate LG receives one of the signals C1˜C8, represented by C_N, and two of the signals R1˜R9, represented by R_N and R_N+1, and afterward outputs a logic signal to control ON/OFF of the current mirror CMR.

Take a 6-bit digital input data (011110) as an example. Operation of the current cell array206is shown inFIG. 2A. Thirty ones of the current cells, shadowed in the figure, are turned on, while others do not output current. From the explanation ofFIG. 1, the current cell A(1,1) is the most one often turned on. In other words, the current cell A(1,1) is often influenced by a current stress. This results in degradation of device characteristics and an abnormal current output.

SUMMARY

Embodiments of the invention provide a thermometer code digital to analog converter. The operational duration of each current cell in the digital to analog converter is substantially equivalent. The lifetime of thin film devices can be longer and which are less affected by a current stress.

A digital to analog converter according to one embodiment of the invention includes a digital data input, a column decoder, a row decoder, a re-queuing circuit and a plurality of current cells. The digital data input receives digital input data. The decoder decodes the digital input data and generates decoded data. The re-queuing circuit changes sequence of bits of the decoded data and outputs re-queued data. Each current cell includes a current source and an internal logic gate. The internal logic gate determines whether the current source outputs the current according to the re-queued data.

A display, which may be an OLED display, according to another embodiment of the invention includes a pixel array, a scan driver and a data driver. The scan driver sequentially turns on a row of the pixels in the pixel array. The data driver includes a digital to analog converter. The digital to analog converter includes a digital data input, a column decoder, a row decoder, a re-queuing circuit and a plurality of current cells. The digital data input receives column or row digital input data. The column or row decoder decodes the column or row digital input data and generates column or row decoded data. The column or row re-queuing circuit changes sequence of bits in the column or row decoded data and outputs column or row re-queued data. Each current cell includes a current source and an internal logic gate. The internal logic gate determines whether the current source outputs the current according to the column or row re-queued data.

The invention provides a digital to analog converter. The vertical start pulse STV and horizontal start pulse STH of an OLED display are utilized to create a switch signal. The output data generated from the column decoder and the row decoder are re-queued according to the switch signal. Operating duration of each current cell in the digital to analog converter is thus substantially equivalent and circuit lifetime is longer. Output accuracy and reliability are both achieved by using the digital to analog converter according to embodiments of the invention.

DETAILED DESCRIPTION

FIG. 3Ashows a schematic diagram of a digital to analog converter according to an embodiment of the invention. The digital to analog converter includes digital data input B1˜B6, a column decoder302, a row decoder304and a current cell array306, a switch signal generator308, a row re-queuing circuit310, a column re-queuing circuit311, a first logic gate312, a second logic gate313and a switch module314. The digital data input B1˜B6represents the least significant bit (LSB) to the most significant bit (MSB) of the 6-bit input data, respectively. The column decoder302decodes the bits B1˜B3, so-called column digital input data, and outputs signals C1˜C7, so-called column decoded data. The row decoder304decodes the bits B4˜B6, so-called row digital input data, and outputs signals R2˜R8, so-called row decoded data. InFIG. 3A, R1is a fixed high voltage level, while C8and R9are fixed at a low voltage level represented by ground.

The switch signal generator receives an input signal STX, which can be STV or STH. STV is a vertical start pulse and STH is a horizontal start pulse. Output signals of the switch signal generator308are complementary signals Bi_dir and XBi_dir. The row re-queuing circuit310and column re-queuing circuit311are controlled by the signal Bi_dir. The main function of the re-queuing circuits is to re-queue the signals C1˜C8and R1˜R9according to the signal Bi_dir and output C1′˜C8′, so-called column re-queued decoded data, and R1′˜R7′, so-called row re-queued decoded data. More specifically, the row re-queuing circuit310and column re-queuing circuit311are bi-directional circuits, which reverse the output sequence of signals C1˜C8and R1˜R9according to the signal Bi_dir. The switch module314includes switches SW-1˜SW-8, controlled by the signals Bi_dir and XBi_dir, respectively. Each of the switches SW-2˜SW-7switches two of the signals R1′˜R7′ and provides the switched signals to the internal logic gates in the current cells in row2to row7according to the signal Bi_dir. Similarly, the switch SW-1switches the signal R1′ and an output signal of a first logic gate312and provides the switched signals to the internal logic gates in the current cells in row1according to the signal Bi_dir. The switch SW-8switches the signal R7′ and an output signal of a second logic gate313and provides the switched signals to the internal logic gates in the current cells in row8according to the signal Bi_dir. Alternatively, the switch module314is connected to the column re-queuing circuit311and the current cell array. The first logic gate312receives the signal Bi_dir and outputs a signal to the switch SW-1. The first logic gate313also receives the signal Bi_dir and outputs another signal to the switch SW-8. The current cell array includes 64 unit current cells A(1,1)˜A(8,8). Each of the current cells A(1,1)˜A(8,8) includes a current mirror CMR and an internal logic gate LG, as shown inFIG. 3B. The internal logic gate LG receives two switched signals provided by one of the switches and one of the output signals C1′˜C8′ provided by the column re-queuing circuit311and outputs a logic signal to control ON/OFF of the current mirror CMR. Note that the input of the digital to analog converter provided by embodiments of the invention is not limited to a 6-bit signal. In addition, the current cells are not necessarily arranged in an array.

FIG. 4Ashows output waveform simulation of each signal. V(STH) stands for a voltage of the horizontal start pulse. V(BI_DIR) represents a voltage of the signal Bi_dir generated by the switch signal generator. V(B1)˜V(B6) are voltages of the 6-bit digital input data. V(C_1)˜V(C_7) and V(R_1)˜V(R_7) are voltage of the re-queued decoded data generated by the column re-queuing circuit310and the row re-queuing circuit311respectively. In different periods, defined by the horizontal start pulses, the switching sequences of the re-queued decoded data are different. The resulting analog current output is shown inFIG. 4B. In the period A, V(BI_DIR) is a high voltage level and the turn-on sequence of the current cells in the current cell array is represented by an solid arrow. In the period B, V(BI_DIR) is a low voltage level and the turn-on sequence of the current cells in the current cell array is represented by a dashed arrow. Thus, the operational duration of each current cell in the digital to analog converter is substantially equivalent. The thin film devices are less affected by the current stress and a lifetime of the circuit is longer.

A display according to another embodiment of the invention is shown inFIG. 5. The display500includes a pixel array510, a scan driver520and a data driver530. More specifically, the display500may be an OLED display. The scan driver520sequentially turns on a row of pixels in the pixel array510. The data driver530includes a digital to analog converter540. The digital to analog converter, the same as the one shown inFIGS. 3A and 3B, includes a digital data input, a column decoder, a row decoder, a re-queuing circuit and a plurality of current cells. The digital data input receives a digital input data. The decoder decodes the digital input data and generates a decoded data. The re-queuing circuit changes sequence of bits in the decoded data and outputs re-queued data. Each current cell includes a current source and an internal logic gate. The logic gate determines whether the current source outputs the current according to the re-queued data.

Embodiments of the invention provide a digital to analog converter. The vertical start pulse STV and horizontal start pulse STH of the OLED display are utilized to create a switch signal. The output data of the column decoder and the row decoder are re-queued according to the switch signal. The operational duration of each current cell in the digital to analog converter is thus substantially equivalent and circuit lifetime is longer. Output accuracy and reliability are both achieved by using the digital to analog converter according to embodiments of the invention.