Image sensor module having build-in package cavity and the method of the same

The present invention provides an image sensor module having build-in package cavity and the Method of the same. An image sensor module structure comprising a substrate with a package receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate, and a package having a die with a micro lens disposed within the package receiving cavity. A dielectric layer is formed on the package and the substrate, a re-distribution conductive layer (RDL) is formed on the dielectric layer, wherein the RDL is coupled to the die and the conductive traces and the dielectric layer has an opening to expose the micro lens. A lens holder is attached on the substrate and the lens holder has a lens attached an upper portion of the lens holder. A filter is attached between the lens and the micro lens. The structure further comprises a passive device on the upper surface of the substrate within the lens holder.

FIELD OF THE INVENTION

This invention relates to a structure of image sensor, and more particularly to an image sensor module having build-in package cavity and the method of the same.

DESCRIPTION OF THE PRIOR ART

Digital video cameras are under development to facilitate as home appliances. Due to the quick development of the semiconductor technology, the application of the image sensor is widely used for digital still camera or movie camera. Consumers' demand has been directed to light weight, multi-function and high resolution. To meet such demand, technical levels of manufacturing camera have been improved. CCD or CMOS chip is popular device for these camera to capture image and die-bonded by means of a conductive adhesive. Typically, an electrode pad of the CCD or CMOS is wire-bonded by means of a metal wire. The wire bonding limits the size of the sensor module. The device is formed by traditional resin packaging method.

A commonly used conventional image sensor device has an array of photodiodes formed on the surface of the wafer substrate. The methods of forming such photo arrays are well known to those having ordinary skill in the art. Typically, the wafer substrate is mounted to a flat support structure and electrically connected to a plurality of electrical contacts. The substrate is electrically connected to bond pads of the support structure using wires. The structure is then enclosed in a package with a light transmissive surface that allows light to impinge on the array of photodiodes. In order to produce a flat image with relatively little distortion or little chromatic aberration requires the implementation of multiple lenses which are arranged to generate a flat optical plane. This can require many expensive optical elements.

Further, in the field of semiconductor devices, the device density is increased and the device dimension is reduced, continuously. The demand for the packaging or interconnecting techniques in such high density devices is also increased to fit the situation mentioned above.

Conventionally, in the flip-chip attachment method, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out by using a solder composite material through a solder mask for producing a desired pattern of solder bumps. The function of chip package includes power distribution, signal distribution, heat dissipation, protection and support . . . and so on. As a semiconductor become more complicated, the traditional package technique, for example lead frame package, flex package, rigid package technique, can't meet the demand of producing smaller chip with high density elements on the chip. Because conventional package technologies have to divide a dice on a wafer into respective dies and then package the die respectively, therefore, these techniques are time consuming for manufacturing process. Since the chip package technique is highly influenced by the development of integrated circuits, therefore, as the size of electronics has become demanding, so does the package technique. For the reasons mentioned above, the trend of package technique is toward ball grid array (BGA), flip chip (FC-BGA), chip scale package (CSP), Wafer level package (WLP) today. “Wafer level package” is to be understood as meaning that the entire packaging and all the interconnections on the wafer as well as other processing steps are carried out before the singulation (dicing) into chips (dies). Generally, after completion of all assembling processes or packaging processes, individual semiconductor packages are separated from a wafer having a plurality of semiconductor dies. The wafer level package has extremely small dimensions combined with extremely good electrical properties.

WLP technique is an advanced packaging technology, by which the die are manufactured and tested on the wafer, and then singulated by dicing for assembly in a surface-mount line. Because the wafer level package technique utilizes the whole wafer as one object, not utilizing a single chip or die, therefore, before performing a scribing process, packaging and testing has been accomplished; furthermore, WLP is such an advanced technique so that the process of wire bonding, die mount and under-fill can be omitted. By utilizing WLP technique, the cost and manufacturing time can be reduced, and the resulting structure of WLP can be equal to the die; therefore, this technique can meet the demands of miniaturization of electronic devices.

Therefore, the present invention provides an image sensor module to reduce the package size and cost.

SUMMARY OF THE INVENTION

The object of the present invention is to provide an image sensor module to link to MB without “connector” for BGA/LGA type.

The object of the present invention is to provide an image sensor module with PCB having cavities for super thin module application and small foot print (form factor), simple process for CIS module.

The further object of the present invention is to provide an image sensor module which is re-workable by de-soldering.

The present invention provides a method for forming an image sensor module package comprising: providing a substrate with a package receiving cavity formed within an upper surface of the substrate and a conductive trace formed therein, wherein the substrate having contact metal formed thereon; picking and attaching a package into the cavity; wherein the package including a die with micro lens area attached on the base of the package, and filling a first material surrounding the die and keeping the same level with die; cleaning die surface and pads; forming a dielectric layer over the base and die, then to open the I/O pads and micro lens area of the die; forming a RDL on the die and the base to form the fan-out structure; Next, attaching a stencil printing solder paste on the substrate; picking and placing passive components on the substrate by picking and placing tool; soldering the passive components on the substrate by an IR reflow; also forming a solder bridge (bump) on the RDL and the substrate to couple with the trace and the die through the contact metal; and mounting a lens holder on the substrate.

The present invention also provides an image sensor module structure comprising: a substrate with a package receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate, wherein the substrate having a contact metal formed thereon; a package having a die with a micro lens placed on the base of the package; a first material fill into the surrounding of die and keeping the same plane with die; a dielectric layer formed on the die and the base, wherein the dielectric layer has an opening to expose the micro lens; a re-distribution conductive layer (RDL) formed on the dielectric layer, wherein the first RDL is coupled to the die and the conductive traces; a protection dielectric layer formed over the RDL, and having an opening to expose the micro lens; a solder bridge (bump) formed on the protection dielectric layer and the substrate to communicate with the trace through the contact metal; a lens holder attached on the substrate, the lens holder having a lens attached an upper portion of the lens holder.

It should be noted that an opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for CMOS Image Sensor (CIS). A transparent cover with coating IR filter is optionally formed over the micron lens area for protection.

The image sensor chips has been coated the protection layer (film) on the micro lens area; the protection layer (film) with the properties of water repellent and oil repellent that can away the particle contamination on the micro lens area; the thickness of protection layer (film) preferably around 0.1 um to 0.3 um and the reflection index close to air reflection index 1. The process can be executed by SOG (spin on glass) skill and it can be processed either in silicon wafer form or panel wafer form (preferably in silicon wafer form to avoid the particle contamination during further process). The materials of protection layer can be SiO2, Al2O3or Fluoro-polymer etc.

The dielectric layer includes an elastic dielectric layer, silicone dielectric based material, BCB or PI. The silicone dielectric based material comprises siloxane polymers (SINR), Dow Corning WL5000 series. Alternatively, the dielectric layer comprises a photosensitive layer. The RDL communicates to the terminal pads downwardly the contacting via through holes structure.

The material of the substrate includes organic epoxy type FR4, FR5, BT, PCB (print circuit board), alloy or metal. Alternatively, the substrate could be glass, ceramic or silicon.

The material of the base includes organic epoxy type FR4, FR5, BT, PCB (print circuit board), alloy or metal. The alloy includes Alloy42 (42% Ni-58% Fe) or Kovar (29% Ni-17% Co-54% Fe). Alternatively, the base could be glass, ceramic or silicon.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The following embodiments and drawings thereof are described and illustrated in the specification that are meant to be exemplary and illustrative, not limiting in scope. One skilled in the relevant art will identify that the invention may be practiced without one or more of the specific details, not limiting in scope.

Referenced throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment and included in at least one embodiment of the present invention. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The present invention discloses a structure of an image sensor module utilizing a substrate having predetermined cavity formed into the substrate. A photosensitive material is coated over the die and the base. Preferably, the material of the photosensitive material is formed of elastic material. The image sensor module comprising PCB mother board with cavity for Image Sensor chip and using solder paste to join with the wires between contact pads of Image sensor package and contact pads of PCB mother board. The module with super thin structure is less than 400 um. The image sensor chips can be processed by WLP to form the protection layer on micro lens and using the build up layers to form the RDL on the panel form substrate. The protection layer on micro lens may prevent the chip from particle contamination and it has water/oil repellent and the thickness of the layer is less than 0.5 um. The lens holder with IR cart can be fixed on the PCB mother board (on top the micro lens area). The high yield and high quality process can be achieved by the present invention.

FIG. 1depicts a cross-sectional view of the image sensor module in accordance with one embodiment of the present invention. As shown in theFIG. 2, the package structure formed within a substrate100includes a die104attached on a base101of the package, a first material101ais filling into surrounding the die104, and forming build up layers formed on the package. Pluralities of conductive traces106are created within the substrate100for electrical communication, and they connect a flexible circuit126for output, alternatively, solder bumps140are formed on the substrate100to output. A lens holder110is formed over the substrate100for supporting the lens and protection, additionally, holder guide pins with the through-hole formed on substrate100. Lens112is attached on the upper portion of the lens holder110. A filter114is located within the lens holder110, between the lens112and the micro lens116formed on the die104. The filter114can be omitted if it is combined with lens112together. The micro lens116includes a protection layer (film)118formed thereon. It should be noted that the passive device136may be formed on the substrate100and outside the lens holder110.

FIG. 2depicts the partially detailed cross-sectional view of the package structure of image sensor module shown inFIG. 1in accordance with an embodiment of the present invention. The die104is attached on the base101of the package200and fixed by an adhesion (die attached) material120a, and the first material101afilling into the surround area of the die104. As known, the contact pads (Bonding pads)122are formed on the die104. A photosensitive layer or dielectric layer124is formed over the die104and the first material101a. Pluralities of openings are formed within the dielectric layer124through the lithography process or exposure and development procedure. The pluralities of openings are aligned to the contact pads or I/O pads122, respectively. The RDL (re-distribution layer)128, also referred to as metal trace, is formed on the dielectric layer124by removing selected portions of metal layer formed over the layer, wherein the RDL128keeps electrically connecting with the die104through the I/O pads122, electrically connecting solder bumps140with the RDL128and trace106to output. A part of the material of the RDL will re-fills into the openings in the dielectric layer124, thereby forming contact via metal over the bonding pad122. A protection layer132is formed to cover the RDL128.

It should be noted that an opening130is formed within the dielectric layer (protection layer)132and the dielectric layer124to expose the micro lens116of the die104for CMOS Image Sensor (CIS). A protection layer118can be formed over the micro lens116on the micro lens area. The opening130is typically formed by photolithography process as well known to the skilled person in the art. In one case, the lower portion of the opening130can be opened during the formation of via opening. The upper portion of the opening130is formed after the deposition of the protection layer132. Alternatively, the whole opening130is formed after the formation of the protection layer132by lithography. The image sensor chips has been coated the protection layer (film)118on the micro lens area; the protection layer (film)118with the properties of water repellent and oil repellent that can away the particle contamination on the micro lens area. The thickness of protection layer (film)118is preferably around 0.1 um to 0.3 um and the reflection index close to the air reflection index 1. The process can be executed by SOG (spin on glass) skill and it can be processed either in silicon wafer form or panel wafer form (preferably in silicon wafer form to avoid the particle contamination during further process). The materials of protection layer can be SiO2, Al2O3or Fluoro-polymer etc. Finally, a transparent cover134with coating IR filter is optionally formed over the micron lens116for protection. The transparent cover114is composed of glass, quartz, etc.

FIG. 3shows the partially detailed cross sectional view of the cavity area138during reflowing of solder bumps140in accordance with an embodiment. From the illustration, contact metal pads142are formed on the substrate100and contact metal pad on RDL128is formed on the die104. The die104may communicate to the traces106within the PCB via the RDL128and the bonding pad122. It is to form the same level between the RDL128and the contact metal pad142once the package200(die104) is attached on the cavity102, and then apply stencil printing solder paste that covers both RDL128and contact metal pad142. The gap between the die104and cavity sidewall is about 100 um so that the solder paste can be joined together (bridge) to connect the contact metal pads142and the RDL during IR reflowing process.

An alternative embodiment can be seen inFIGS. 4A and 4B, most of the structures are similar toFIG. 1, therefore, the detailed description is omitted. Passive devices402may be formed within the lens holder110by SMT (surface mounting technology), and omitting flexible circuit126is omitted by solder balls404for fan out. This is to integrate the image sensor module and passive components in whole and to gain the number of output pin and minify the volume of image sensor module, alternatively, the solder bumps140also are used for outputting, therefore, the structure having two paths to output. The structure is for BGA (Ball Grid Array) type image sensor module.

Alternately,FIG. 5depicts a cross-sectional view of a structure of image sensor module according to the present invention. Pluralities of conductive traces106are created within the substrate100for electrical communication. Terminal Pads508are located on the bottom surface of the substrate100and connected with the traces106so that the image sensor module can be directly mount on the board. Alternatively, the solder bumps140also are used for outputting, therefore, the structure having two paths to output. The aforementioned structure constructs LGA type image sensor module.

Preferably, the material of the substrate100is organic substrate likes CCL, FR4, FR5, BT (Bismaleimide triazine), PCB with defined cavity or Alloy42 with pre etching circuit. The organic substrate with high Glass transition temperature (Tg) are epoxy type FR5 or BT (Bismaleimide triazine) type substrate. The Alloy42 is composed of 42% Ni and 58% Fe. Kovar can be used also, and it is composed of 29% Ni, 17% Co, 54% Fe. The glass, ceramic, silicon can be used as the substrate due to lower CTE. The dimension of the depth of the cavity102could be larger than the thickness of the die104. It could be deeper as well.

The base101could be round type such as wafer type, the diameter could be 200, 300 mm or higher. It could be employed for rectangular type such as panel form. The substrate100is formed with cavities102and built in circuit106.

In one embodiment of the present invention, the dielectric layer124is preferably an elastic dielectric material which is made by silicone dielectric materials comprising siloxane polymers (SINR), silicon oxide, silicon nitride, Dow Corning WL5000 series and composites thereof. In another embodiment, the dielectric layer is made by a material comprising benzocyclobutene (BCB), epoxy, polyimides (PI) or resin. Preferably, it is a photosensitive layer for simple process. In one embodiment of the present invention, the elastic dielectric layer is a kind of material with CTE larger than 100 (ppm/° C.), elongation rate about 40 percent (preferably 30 percent-50 percent), and the hardness of the material is between plastic and rubber. The thickness of the elastic dielectric layer124depends on the stress accumulated in the RDL/dielectric layer interface during temperature cycling test.

In one embodiment of the invention, the material of the RDL comprises Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy; the thickness of the RDL is between 2 um_and—15 um. The Ti/Cu alloy is formed by sputtering technique also as seed metal layers, and the Cu/Au or CU/Ni/Au alloy is formed by electroplating; exploiting the electro-plating process to form the RDL can make the RDL thick enough to withstand CTE mismatching during temperature cycling. The bonding pads122can be Al or Cu or combination thereof. In case of the structure of FO-WLP utilizes SINR as the elastic dielectric layer and Cu as the RDL metal. According to the stress analysis not shown here, the stress accumulated in the RDL/dielectric layer interface is reduced.

As shown inFIG. 2-5, the RDL metal fans out of the die104and communicates downwardly toward the terminal pads508or solder balls404under the structure, alternatively, to communicate upwardly toward the solder bumps140over the structure. It is different from the prior art technology which stacks layers over the die, thereby increasing the thickness of the package. However, it violates the rule to reduce the die package thickness. On the contrary, the terminal pads are located on the surface that is opposite to the die pads side. The communication traces106are penetrates through the substrate100. Therefore, the thickness of the die package is apparently shrinkage. The package of the present invention will be thinner than the prior art. Further, the substrate is pre-prepared before package. The cavity102and the traces106are pre-determined as well. Thus, the throughput will be improved than ever.

The method of present invention comprises: providing the PCB (FR5/BT) with CIS package cavity. Then, the next step is to pick the CIS package (from blue tape flame) and attach the CIS package into the cavity. Then, the attached material is cured. Build up layers (RDL) process is performed to form the RDL in the package (pre-formed). Then, the stencil printing solder paste on substrate (cover both contact pads), subsequently, and pick and place the passive components on the PCB by picking and placing tool. Afterward, IR reflow is used to solder joining with contact pads of the image sensor module and contact pads of PCB, passive components, and the solder bumps formed on upper surface of the substrate with the trace, followed by flux cleaning the PCB. Next is to mount the lens holder and fix the holder on the PCB, followed by module testing.

The advantages of the present invention are:Module is linking with MB (mother board) without “connector” for BGA/LGA typeSMT process is used to mount CIS module on MB for BGA/LGA typeBuild up layers process is used for CIS packagePCB with cavities for super thin moduleSmall foot print (form factor)Simple process for CIS moduleSolder join terminal pins are standard format (for LGA/BGA type)Module re-workable by de-soldering from MBHighest yield during manufacturing in module/system assemblyProtection layer is on the micro lens to prevent particle contaminationLowest cost substrate (PCB-FR4 or FR5/BT type)High yield due to build up layers process