Semiconductor device and memory system

According to one embodiment, in a semiconductor device, the first pull-up circuit is connected to a third node and to a fourth node. The third node is a node between a drain of the first transistor with a first conductivity type and a source of the second transistor with the first conductivity type. The fourth node is a node between a drain of the third transistor with the first conductivity type, and a source of the fourth transistor with the first conductivity type and a source of the fifth transistor with the first conductivity type. The first pull-down circuit is connected to a fifth node and to a sixth node. The fifth node is a node between a drain of the first transistor with a second conductivity type and a source of the second transistor with the second conductivity type. The sixth node is a node between a drain of the third transistor with the second conductivity type and a source of the fourth transistor with the second conductivity type and a source of the fifth transistor with the second conductivity type.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-141627, filed on Jul. 27, 2018; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and a memory system.

BACKGROUND

A semiconductor device used for an interface of semiconductor memory externally receives a reference differential clock, adjusts the reference differential clock to generate an internal differential clock, and supplies the internal differential clock to the semiconductor memory. The semiconductor memory can latch data with the internal differential clock. At this time, it is desirable to properly generate the internal differential clock.

DETAILED DESCRIPTION

In general, according to one embodiment, there is provided a semiconductor device including a first input circuit, a first latch circuit, a first pull-up circuit, and a first pull-down circuit. In the first input circuit, a second transistor with a first conductivity type and a second transistor with a second conductivity type are arranged between a first transistor with the first conductivity type and a first transistor with the second conductivity type. The second transistor with the first conductivity type and the second transistor with the second conductivity type have gates commonly connected to a second input node. The first transistor with the first conductivity type and the first transistor with the second conductivity type have gates commonly connected to a first input node. In the first latch circuit, a connection of a fourth transistor with the first conductivity type and a fourth transistor with the second conductivity type and a connection of a fifth transistor with the first conductivity type and a fifth transistor with the second conductivity type are arranged in parallel between a third transistor with the first conductivity type and a third transistor with the second conductivity type. The fourth transistor with the first conductivity type and the fourth transistor with the second conductivity type have gates commonly connected to the first input node and have drains commonly connected to a first node. The fifth transistor with the first conductivity type and the fifth transistor with the second conductivity type have gates commonly connected to the second input node and have drains commonly connected to the first node. The third transistor with the first conductivity type and the third transistor with the second conductivity type have gates commonly connected to a second node connected to the first node on an output side of the first input circuit via a first inverter. The first pull-up circuit is connected to a third node and to fourth node. The third node is a node between a drain of the first transistor with the first conductivity type and a source of the second transistor with the first conductivity type in the first input circuit. The fourth node is a node between a drain of the third transistor with the first conductivity type, and a source of the fourth transistor with the first conductivity type and a source of the fifth transistor with the first conductivity type in the first latch circuit. The first pull-down circuit is connected to a fifth node and to a sixth node. The fifth node is a node between a drain of the first transistor with the second conductivity type and a source of the second transistor with the second conductivity type in the first input circuit. The sixth node is a node between a drain of the third transistor with the second conductivity type and a source of the fourth transistor with the second conductivity type and a source of the fifth transistor with the second conductivity type in the first latch circuit.

Exemplary embodiments of a semiconductor device will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

First Embodiment

A semiconductor device according to a first embodiment can be used for a high-speed interface of a semiconductor memory. The semiconductor device is configured according to standards such as DDR, DDR2, DDR3, low power double-data-rate (LPDDR), LPDDR2, and open NAND flash interface (ONFI) in consideration of high-speed data transfer. According to the standards such as DDR, data fetch at double edges of rising and falling of a clock can realize double transfer speed (double data rate) as compared with data fetch at only rising or falling of a clock.

The semiconductor device receives a reference differential clock from an outside, adjusts the reference differential clock to generate an internal differential clock, and supplies the internal differential clock to the semiconductor memory. The semiconductor memory may be a nonvolatile memory such as a NAND-type flash memory or a volatile memory such as a synchronous dynamic random access memory (SCRAM).

In the semiconductor device and/or the semiconductor memory, an operation such as data latch is performed in synchronization with a cross point of the internal differential clock. Since an allowable duty cycle distortion (DCD) range becomes narrower as a frequency of the differential clock used for this operation increaser, suppression of DCD is desired.

The semiconductor device may be configured using a duty cycle corrector (DCC) in order to perform duty correction to suppress the DCD of the differential clock. In this case, not only circuit scale and power consumption become large but also a warm-up cycle for training before operation is provided, and it becomes difficult to satisfy a demand of operating from the first clock of the standard.

Meanwhile, the semiconductor device may be configured using a cross point correction circuit in order to correct the cross point of the differential clock to an appropriate level (for example, an intermediate level between an Logical low level and an Logical high level). The cross point correction circuit applies, to the differential clocks, correction to generate a clock shifted at timing when logic levels of a clock corresponding to one of the differential clocks and of a clock obtained by logically inverting the other differential clock become uniform, to set the cross point to an appropriate level (for example, near the intermediate level). With the correction, if the cross points of the differential clocks can be arranged at substantially temporally equal intervals, correction of DCD without the warm up cycle is conceivable.

However, in the cross point correction circuit, a delay occurs at edge timing of a first differential clock and a first cross point deviates from the appropriate level and an eye pattern becomes small in some cases. That is, there is a possibility that erroneous data values may be latched in the semiconductor device and/or the semiconductor memory due to insufficient setup time and hold time in the data latch with respect to the first differential clock.

This is believed to be due to the fact that an intermediate node in the cross point correction circuit becomes in a floating state and a period in which a potential of the intermediate node becomes unstable exists. For example, if a state in which no clock is input continues, the intermediate node tends to float, and the potential can become an intermediate potential between the Logical high level and the Logical low level due to a leakage current. When a clock is input in this state, an internal state changes between a time when the first clock is received and a time when the second clock is received, and thus response speeds have a difference. There is a possibility that this difference causes jitter and presses a high-speed operation margin.

Therefore, in the first embodiment, pull-up circuits capable of pulling up an intermediate node on a power supply side and pull-down circuit capable of pulling down an intermediate node on a ground side are provided, thereby to properly generate a first differential clock in a cross point correction circuit of a semiconductor device.

Specifically, a semiconductor device1can be configured as illustrated inFIG. 1.FIG. 1is a circuit diagram illustrating a configuration of the semiconductor device1. The semiconductor device1includes a receiver10, a phase splitter20, a cross point correction circuit30, and a cross point correction circuit40.

The semiconductor device1receives reference differential clocks (φCK and φBCK) from an outside (for example, a host or a signal processing circuit). The reference differential clocks include a reference non-inverted clock φCK and a reference inverted clock φBCK. Correspondingly, the receiver10and the phase splitter20are each configured with differential input and output. The cross point correction circuit30and the cross point correction circuit40constitute a differential pair. The cross point correction circuit30is a non-inverting-side cross point correction circuit, and the cross point correction circuit40is an inverting-side cross point correction circuit.

The receiver10is arranged on an input side of the phase splitter20. The receiver10includes a non-inverting-side receiver11and an inverting-side receiver12. The receiver11receives the reference non-inverted clock φCK, generates a non-inverted clock φCK_1, and supplies the non-inverted clock φCK_1to the phase splitter20. The receiver12receives the reference inverted clock φBCK, generates an inverted clock φBCK_1, and supplies the inverted clock φBCK_1to the phase splitter20.

For example, as illustrated inFIG. 2, the receiver10receives the differential clocks (φCK and φBCK) each having a duty ratio of approximately 50% and a cross point close at near an appropriate level (for example, an intermediate level).FIG. 2is a waveform diagram illustrating an operation of the semiconductor device. Meanwhile, in the non-inverted clock φCK_1and the inverted clock φBCK_1output from the receiver10, the duty ratios deviate from 50%, respectively, and the cross point can deviate from the appropriate level due to asymmetry of characteristics between the non-inverting-side receiver11and the inverting-side receiver12.

The phase splitter20illustrated inFIG. 1is arranged between the receiver10, and the cross point correction circuit30and the cross point correction circuit40. The phase splitter20has a non-inverting-side phase splitter21and an inverting-side phase splitter22.

The non-inverting-side phase splitter21receives the non-inverted clock φCK_1via a node21i, and generates and outputs a clock φCKc, which is obtained by logically inverting the non-inverted clock φCK_1, and a clock φCKt corresponding to the non-inverted clock φCK_1.

The phase splitter21includes, for example, a chain circuit21aand a chain circuit21b. The chain circuit21ahas a configuration in which an inverter IV21, an inverter IV25, and an inverter IV26are sequentially connected in series in a chain manner, and one end of a capacitive element C is connected to a line L connecting the inverter IV25and the inverter IV26. The other end of the capacitive element C can be connected to a ground potential. As a result, the chain circuit21apasses the non-inverted clock φCK_1through the inverters IV21, IV25and IV26of the odd number stage to generate and output the clock φCKc. The chain circuit21bhas a configuration in which the inverter IV21, an inverter IV22, an inverter IV23, and an inverter IV24are sequentially connected in series in a chain manner. As a result, the chain circuit21bpasses the non-inverted clock φCK_1through the inverters IV21to IV44of the even number stage to generate and output the clock φCKt.

The inverting-side phase splitter22receives the inverted clock φBCK_1via the node21i, and generates and outputs a clock φBCKc, which is obtained by logically inverting the inverted clock φBCK_1, and a clock φBCKt corresponding to the inverted clock φBCK_1. The internal configuration of the inverting-side phase splitter22is similar to the internal configuration of the non-inverting-side phase splitter21.

The phase splitter20supplies the clock φCKt from a node21o2to the cross point correction circuit30and the clock φBCKc from a node22o1to the cross point correction circuit30.

For example, as illustrated inFIG. 2, in a case where the duty ratios of the non-inverted clock φCK_1and the inverted clock φBCK_1deviate from 50%, respectively, the duty ratios of the clock φCKt and the clock φBCKc can deviate from 50%, respectively.

The cross point correction circuit30illustrated inFIG. 1generates a clock φCKout shifted at timing when logic levels of the clock φCKt corresponding to the non-inverted clock φCK_1and of the clock φBCKc obtained by logically inverting the inverted clock φBCK_1become uniform. The clock φCKt is a clock corresponding to the clock φCK, and the clock φBCKc is a clock corresponding to the clock φBCK. Accordingly, the cross point correction circuit30equivalently applies correction to the differential clocks (the pair of clocks φCK and φBCK) so that the cross point becomes the appropriate level (for example, near the intermediate level).

The cross point correction circuit30is arranged on an output side of the phase splitter20. The cross point correction circuit30includes an input circuit31, a latch circuit32, a pull-up circuit33, a pull-down circuit34, and a control circuit35. The input circuit31is arranged on a phase splitter20side in the cross point correction circuit30. The latch circuit32is arranged on an output side of the input circuit31. The pull-up circuit33and the pull-down circuit34are arranged between the input circuit31and the latch circuit32. The control circuit35is arranged on input sides of the pull-up circuit33and the pull-down circuit34.

The input circuit31has a MOS transistor and an NMOS transistor NM2arranged between a PMOS transistor PM1and an NMOS transistor NM1.

The PMOS transistor PM1and the NMOS transistor NM2have gates commonly connected to an input node IN1. The PMOS transistor PM1has a source connected to a power supply potential and a drain connected to a node N3. The NMOS transistor NM1has a source connected to the ground potential and a drain connected to a node N5.

The PMOS transistor PM2and the NMOS transistor NM2have gates commonly connected to an input node IN2. The PMOS transistor PM2has a source connected to the node N3and a drain connected to a node N13. The NMOS transistor NM2has a source connected to the node N5and a drain connected to the node N13. The node N13constitutes an output node of the input circuit31.

With the configuration, the input circuit31outputs, according to the fact that a logic level of the clock φCKt and a logic level of the clock φBCKc have become uniform, a logic level obtained by inverting the uniform logic level to the node N13.

The latch circuit32has a PMOS transistor PM4and an NMOS transistor NM4, and a PMOS transistor PM5and an NMOS transistor NM5arranged in parallel between a PMOS transistor PM3and an NMOS transistor NM3.

The PMOS transistor PM3and the NMOS transistor NM3have gates commonly connected to a node N2. A node N1on the output side of the input circuit31is connected to the node N2via an inverter IV31. The node N1is connected to node N13. The PMOS transistor PM3has a source connected to the power supply potential and a drain connected to a node N4. The NMOS transistor NM3has a source connected to the ground potential and a drain connected to a node N6.

The PMOS transistor PM4and the NMOS transistor NM4have gates commonly connected to the input node IN1and drains commonly connected to the node N1via a node N15. The PMOS transistor PM4has a source connected to the node N4. The NMOS transistor NM4has a source connected to the node N6.

The PMOS transistor PM5and the NMOS transistor NM5have gates commonly connected to the input node IN2and drains commonly connected to the node N1via the node N15. The PMOS transistor PM5has a source connected to the node N4. The NMOS transistor NM5has a source connected to the node N6.

The node N2is connected to an output node ON1via inverters IV32and IV33. The output node ON1functions as a non-inverting-side output node of the semiconductor device1.

With the configuration, the latch circuit32outputs the logic level output from the input circuit31during a period in which the logic level of the clock φCKt and the logic level of the clock φBCKc are uniform, and holds and outputs the logic level that has been output immediately before, during a period in which the logic level of the clock φCKt and the logic level of the clock φBCKc are different.

The pull-up circuit33is connected to the node N3and the node N4. The pull-up circuit33can pull up the node N3and the node N4. The pull-up circuit33includes a pull-up switch PU1and a pull-up switch PU2.

The pull-up switch PU1is electrically inserted between the power supply potential and the node N3. The pull-up switch PU1pulls up the node N3in response to a control signal φPU12received from the control circuit35. The pull-up switch PU1includes a PMOS transistor PM11. The PMOS transistor PM11has a gate connected to the control circuit35, a source connected to the power supply potential, and a drain connected to the node N3.

The pull-up switch PU2pulls up the node N4in response to the control signal φPU12received from the control circuit35. The pull-up switch PU2is electrically inserted between the power supply potential and the node N4. The pull-up switch PU2includes a PMOS transistor PM12. The PMOS transistor PM12has a hate connected to the control circuit35, a source connected to the power supply potential, and a drain connected to the node N4.

The pull-down circuit34is connected to the node N5and the node N6. The pull-down circuit34can pull down the node N5and the node N6. The pull-down circuit34includes a pull-down switch PD1and a pull-down switch PD2.

The pull-down switch PD1pulls down the node N5in response to a control signal φPD12received from the control circuit35. The pull-down switch PD1is electrically inserted between the ground potential and the node N5. The pull-down switch PD1includes an NMOS transistor NM11. The NMOS transistor NM11has a gate connected to the control circuit35, a source connected to the ground potential, and a drain connected to the node N5.

The pull-down switch PD2pulls down the node N6in response to the control signal φPD12received from the control circuit35. The pull-down switch PD2is electrically inserted between the ground potential and the node N6. The pull-down switch PD2has an NMOS transistor NM12. The NMOS transistor NM12has a gate connected to the control circuit35, a source connected to the ground potential, and a drain connected to the node N6.

In the cross point correction circuit30, the input circuit31receives the clock φCKt and the clock φBCKc, and at timing when the logic level of the clock φCKt and the logic level of the clock φBCKc have become uniform, the input circuit31outputs a signal obtained by inverting the logic level.

The control circuit35receives the clock φCKt and the clock φBCKc, and controls the pull-up circuit33and the pull-down circuit34according to the logic levels of the clock φCKt and the clock φBCKc. The control circuit35generates and supplies the control signal φPU12to the pull-up switches PU1and PU2and generates and supplies the control signal φPD12to the pull-down switches PD1and PD2in response to the clock φCKt and the clock φBCKc. The control circuit35has a NAND circuit NAND1and a NOR circuit NOR1.

The NAND circuit NAND1performs NAND operation of the clock φCKt and the clock φBCKc to generate the control signal φPU12, and supplies the control signal φPU12to the pull-up switches PU1and PU2. The control signal φPU12is a low active signal. The NAND circuit NAND1maintains the control signal φPU12at an Logical low level (active level) during a period in which both the clock φCKt and the clock φBCKc are at an Logical high level (nonactive level), and maintains the control signal φPU12at the Logical high level during a period in which at least one of the clock φCKt and the clock φBCKc is at the Logical low level.

The NOR circuit NOR1generates and supplies the control signal φPD12to the pull-down switches PD1and PD2in response to the clock φCKt and the clock φBCKc. The control signal φPD12is a high active signal. The NOR circuit NOR1maintains the control signal φPD12at the Logical high level (active level) during a period in which both the clock φCKt and the clock φBCKc are at the Logical low level (nonactive level), and maintains the control signal φPD12at the Logical low level during a period in which at least one of the clock φCKt and the clock φBCKc is at the Logical high level.

That is, the control circuit35can turn on/off the pull-up operation of the pull-up circuit33and turns on/off the pull-down operation of the pull-down circuit34according to the clock φCKt and the clock φBCKc, and can realize the pull-up operation and the pull-down operation while preventing a through current in the input circuit31and/or the latch circuit32.

For example, as illustrated inFIG. 2, the control signal φPU12becomes at the Logical low level (active level) and both the pull-up switches PU1and PU2are turned on in response to the fact that the output of the input circuit31becomes at the Logical low level at the timing when both the clock φCKt and the clock φBCKc become at the Logical high level. As a result, since the node N3and the node N4are pulled up, the waveform of the clock φCKout can be steeply raised and output from the output node ON1.

The cross point correction circuit40illustrated inFIG. 1generates a clock φBCKout shifted at timing when logic levels of the clock φCKc corresponding to the non-inverted clock φCK_1and of the clock φBCKt obtained by logically inverting the inverted clock φBCK_1become uniform. The clock φCKc is a clock corresponding to the clock φCK, and the clock φBCKt is a clock corresponding to the clock φBCK. Accordingly, the cross point correction circuit40equivalently applies correction to the differential clocks (the pair of clocks φCK and φBCK) so that the cross point becomes the appropriate level (for example, near the intermediate level).

The cross point correction circuit40is arranged on the output side of the phase splitter20. The cross point correction circuit40includes an input circuit41, a latch circuit42, a pull-up circuit43, a pull-down circuit44, and a control circuit45. The input circuit41is arranged on the phase splitter20side in the cross point correction circuit40. The latch circuit42is arranged on an output side of the input circuit41. The pull-up circuit43and the pull-down circuit44are arranged between the input circuit41and the latch circuit42. The control circuit45is arranged on input sides of the pull-up circuit43and the pull-down circuit44.

The PMOS transistor PM6and the NMOS transistor NM6have gates commonly connected to an input node IN3. The PMOS transistor PM6has a source connected to the power supply potential and a drain connected to a node N9. The NMOS transistor NM6has a source connected to the ground potential and a drain connected to a node N11.

The PMOS transistor PM7and the NMOS transistor NM7have gates commonly connected to an input node IN4. The PMOS transistor PM7has a source connected to the node N9and a drain connected to a node N14. The NMOS transistor NM7has a source connected to the node1411and a drain connected to the node N14. The node N14constitutes an output node of the input circuit41.

With the configuration, the input circuit41outputs, according to the fact that a logic level of the clock φCKc and a logic level of the clock φBCKt have become uniform, a logic level obtained by inverting the uniform logic level to the node N14.

The latch circuit42has a PMOS transistor PM9and an NMOS transistor NM9, and a PMOS transistor PM10and an NMOS transistor NM10arranged in parallel between a PMOS transistor PM8and an NMOS transistor NM8.

The PMOS transistor PM8and the NMOS transistor NM8have gates commonly connected to a node N8. A node N7on the output side of the input circuit41is connected to the node N8via an inverter IV41. The node N7is connected to the node N14. The PMOS transistor PMT has a source connected to the power supply potential and a drain connected to a node N10. The NMOS transistor NM has a source connected to the ground potential and a drain connected to a node N12.

The PMOS transistor PM9and the NMOS transistor NM9have gates commonly connected to the input node IN3and drains commonly connected to the node N7via a node N16. The PMOS transistor PM9has a source connected to the node N10. The NMOS transistor NM9has a source connected to the node N12.

The PMOS transistor PM10and the NMOS transistor NM10have gates commonly connected to the input node IN4and drains commonly connected to the node N7via the node N16. The PMOS transistor PM10has a source connected to the node N10. The NMOS transistor NM10has a source connected to the node N12.

The node N8is connected to an output node ON2via inverters IV42and IV43. The output node ON2functions as an inverting-side output node of the semiconductor device1.

With the configuration, the latch circuit42outputs the logic level output from the input circuit41during a period in which the logic level of the clock φKc and the logic level of the clock φBCKt are uniform, and holds and outputs the logic level that has been output immediately before, during a period in which the logic level of the clock φCKc and the logic level of the clock φBCKt are different.

The pull-up circuit43is connected to the node N9and the node N10. The pull-up circuit43can pull up the node N9and the node N10. The pull-up circuit43includes a pull-up switch PU3and a pull-up switch PU4.

The pull-up switch PU3is electrically inserted between the power supply potential and the node N9. The pull-up switch PU3pulls up the node N9in response to a control signal φPU34received from the control circuit45. The pull-up switch PU3includes a PMOS transistor PM13. The PMOS transistor PM13has a gate connected to the control circuit45, a source connected to the power supply potential, and a drain connected to the node N9.

The pull-up switch PU4pulls up the node N10in response to the control signal φPU34received from the control circuit45. The pull-up switch PU4is electrically inserted between the power supply potential and the node N10. The pull-up switch PU4includes a PMOS transistor PM14. The PMOS transistor PM14has a gate connected to the control circuit45, a source connected to the power supply potential, and a drain connected to the node N10.

The pull-down circuit44is connected to the node N11and the node N12. The pull-down circuit44can pull down the node N11and the node N12. The pull-down circuit44includes a pull-down switch PD3and a pull-down switch PD4.

The pull-down switch Phi pulls down the node N11in response to a control signal φPD34received from the control circuit45. The pull-down switch PD3is electrically inserted between the ground potential and the node N11. The pull-down switch PD3includes an NMOS transistor NM13. The NMOS transistor NM13has a gate connected to the control circuit45, a source connected to the ground potential, and a drain connected to the node N11.

The pull-down switch PD4pulls down the node N12in response to a control signal φPD34received from the control circuit45. The pull-down switch PD4is electrically inserted between the ground potential and the node N12. The pull-down switch PD4includes an NMOS transistor NM14. The NMOS transistor NM14has a gate connected to the control circuit45, a source connected to the ground potential, and a drain connected to the node N12.

In the cross point correction circuit40, the input circuit41receives the clock φCKc and the clock φBCKt, and at timing when the logic level of the clock φCKc and the logic level of the clock φBCKt have become uniform, the input circuit41outputs a signal obtained by inverting the logic level.

The control circuit45receives the clock φCKc and the clock φBCKt, and controls the pull-up circuit43and the pull-down circuit44according to the logic levels of the clock φCKc and the clock φBCKt. The control circuit45generates and supplies the control signal φPU34to the pull-up switches PU3and PU4and generates and supplies the control signal φPD34to the pull-down switches PD3and PD4in response to the clock φCKc and the clock φBCKt. The control circuit45has a NAND circuit NAND2and a NOR circuit NOR2.

The NAND circuit NAND2performs NAND operation of the clock φCKc and the clock φBCKt to generate the control signal φPD34, and supplies the control signal φPU34to the pull-up switches PU3and PU4. The control signal φPU34is a low active signal. The NAND circuit NAND2maintains the control signal φPD34at the Logical low level (active level) during a period in which both the clock φCKc and the clock φBCKt are at the Logical high level (nonactive level), and maintains the control signal φPU34at the Logical high level during a period in which at least one of the clock φCKc and the clock φBCKt is at the Logical low level.

The NOR circuit NOR2generates and supplies the control signal φPD34to the pull-down switches PD3and PD4in response to the clock φCKc and the clock φBCKt. The control signal φPD34is a high active signal. The NOR circuit NOR2maintains the control signal φPD34at the Logical high level (active level) during a period in which both the clock φCKc and the clock φBCKt are at the Logical low level (nonactive level), and maintains the control signal φPD34at the Logical low level during a period in which at least one of the clock φBCKc and the clock φBCKt is at the Logical high level.

That is, the control circuit45can turn on/off the pull-up operation of the pull-up circuit43and turns on/off the pull-down operation of the pull-down circuit44according to the clock φCKc and the clock φBCKt, and can realize the pull-up operation and the pull-down operation while preventing a through current in the input circuit41and/or the latch circuit42.

For example, as illustrated inFIG. 2, the control signal φPD34becomes at the Logical high level (active level) and both the pull-up switches PD3and PD4are turned on in response to the fact that the output of the input circuit41becomes at the Logical high level at the timing when both the clock φCKc and the clock φBCKt become at the Logical low level. As a result, since the node N9and the node N10are pulled up, the waveform of the clock φBCKout can be steeply raised and output from the output node ON2.

That is, the waveform of the clock φCKout can be steeply raised by the cross point correction circuit30in response to the clock φCkt and the clock φBCKc, and the waveform of the clock φBCKout can be steeply raised by the cross point correction circuit40in response to the clock φCKc and the clock φBCKt. Therefore, a delay in edge timing of the first differential clock can be suppressed. As a result, the cross point of the first differential clock can be brought close to the vicinity of the appropriate level (for example, the intermediate level between the Logical high level and the Logical low level), and a large eye pattern can be secured.

As described above, in the first embodiment, the pull-up circuits33and43capable of pulling up the intermediate node on the power supply side and the pull-down circuits34and44capable of pulling down the intermediate node on the ground side are provided in the cross point correction circuits30and40of the semiconductor device1. As a result, DCD can be suppressed for the first differential clock and the first differential clock can be appropriately generated.

Second Embodiment

Next, a semiconductor device201according to a second embodiment will be described. Hereinafter, portions different from the first embodiment will be mainly described.

As illustrated in the first embodiment, when the deviation between the edge timing of the non-inverting-side clock and the edge timing of the inverting-side clock falls within a predetermined range (for example, within a range equal to or less than a half cycle of the reference differential clock), the cross point of the differential clocks can be brought close to the vicinity of the appropriate level by the cross point correction circuit30and the cross point correction circuit40.

However, if the deviation between the edge timing of the non-inverting-side clock and the edge timing of the inverting-side clock falls outside the predetermined range, it becomes difficult to bring the cross point of the differential clocks close to the vicinity of the appropriate level.

Therefore, in the second embodiment, second-stage cross point correction by the comparison circuit is added to first-stage cross point correction by a cross point correction circuit, thereby to enable appropriate cross point correction in a case where deviation in edge timing between a non-inverting-side clock and an inverting-side clock.

Specifically, as illustrated inFIG. 3, the semiconductor device201includes a cross point correction circuit230and a cross point correction circuit240instead of the cross point correction circuit30and the cross point correction circuit40(seeFIG. 1), and further includes a comparison circuit250.FIG. 3is a diagram illustrating a configuration of the semiconductor device201.

The cross point correction circuit230is different from the cross point correction circuit30in not including the pull-up circuit33, the pull-down circuit34, and the control circuit35illustrated inFIG. 1. A non-inverting-side clock output from the cross point correction circuit230will be referred to as φCKout_pre.

The cross point correction circuit240is different from the cross point correction circuit40in not including the pull-up circuit43, the pull-down circuit44, and the control circuit45illustrated inFIG. 1. An inverting-side clock output from the cross point correction circuit240will be referred to as φBCKout_pre.

The comparison circuit250is arranged on an output side of the cross point correction circuit230and on an output side of the cross point correction circuit240. The comparison circuit250includes an input node250a, an input node250b, an output node250c, and an output node250d. The input node250ais connected to an output node ON1of the cross point correction circuit230. The input node250bis connected to an output node ON2of the cross point correction circuit240. The output node250cfunctions as a non-inverting-side output node of the semiconductor device201. The output node250dfunctions as an inverting-side output node of the semiconductor device201.

The comparison circuit250receives the clock φCKout_pre from the cross point correction circuit230and receives the clock φBCKout_pre from the cross point correction circuit240. The comparison circuit250compares the clock φCKout_pre with the clock φBCKout_pre and outputs a clock φCkout and a clock φBCKout with corrected cross points of the clock φCkout_pre and the clock φBCKout_pre, as a comparison result.

The comparison circuit250includes a comparator CP. As the comparator CP, a differential amplifier configured to prevent application of feedback between input and output (so as to perform a comparator operation) can be used. The comparator CP is electrically inserted between the input node250aand the input node250b, and the output node250cand the output node250d. The comparator CP has a non-inverting input terminal (+) electrically connected to the output node ON1of the cross point correction circuit230via the input node250a, an inverting input terminal (−) electrically connected to the output node ON2of the cross point correction circuit240via the input node250b, a non-inverting output terminal (+) electrically connected to the output node250c, and an inverting output terminal (−) electrically connected to the output node250d.

The comparator CP receives the clock φCKout_pre from the cross point correction circuit230and receives the clock φBCKout_pre from the cross point correction circuit240. The comparator CP compares the clock φCKout_pre with the clock φBCKout_pre, outputs an Logical high level as a non-inversion comparison result (clock φCKout) and outputs an Logical low level as an inversion comparison result (clock φBCKout) when the level of the clock φCKout_pre is higher than the level of the clock φBCKout_pre. The comparator CP outputs the Logical low level as the non-inversion comparison result (clock φCKout) and outputs the Logical high level as the non-inversion comparison result (clock φBCKout) when the level of the clock φCKout_pre is lower than the level of the clock φCKout_pre. As a result, the comparator CP outputs the clock φCKout and the clock φBCKout with the corrected cross points of the clock φCkout_pre and the clock φBCKout_pre.

For example, in a case where asymmetry of characteristics and the like between a non-inverting-side receiver11and an inverting-side receiver12are large, deviation in edge timing of waveforms of a non-inverted clock φCK_1and an inverted clock φBCK_1may fall outside a predetermined range (for example, a range equal to or less than a half cycle of reference differential clocks φCK and φBCK), as illustrated by the solid line and the broken line inFIG. 4. In this case, the cross points of the clock φCKout_pre and the clock φBCKout_pre are likely to deviate from an appropriate level (for example, an intermediate level between the Logical high level and the Logical low level) as illustrated by the solid line and the broken line inFIG. 4. At this time, the comparator CP outputs the Logical high level as the clock φCKout and the Logical low level as the clock φBCKout when the level of the clock φCKout_pre is higher than the level of the clock φBCKout_pre, and outputs the Logical low level as the clock φCKout and the Logical high level as the clock φBCKout when the level of the clock φCKout_pre is lower than the level of the clock φBCKout_pre. As a result, the comparator CP can generate the clock φCKout and the clock φBCKout with the cross points at the appropriate level (for example, at the intermediate level).

As described above, in the second embodiment, the second-stage cross point correction by the comparison circuit250is added to the first-stage cross point correction by the cross point correction circuits230and240in the semiconductor device201. As a result, the cross point correction can be appropriately performed in the case where the deviation in the edge timing between the non-inverting-side clock and the inverting-side clock is large.

Note that, as illustrated inFIG. 5, measures to reduce power consumption in a semiconductor device201imay be added. In the semiconductor device201i, a comparison circuit250imay be configured using a plurality of inverters having a “back to hack” configuration in place of the comparator CP (differential amplifier) illustrated inFIG. 3.FIG. 5is a circuit diagram illustrating the configuration of the semiconductor device201iaccording to a modification of the second embodiment.

The comparison circuit250iincludes a plurality of inverters IV3, IV4, IV5, and IV6. The inverter IV4has an input node electrically connected to the output node ON2of the cross point correction circuit240via input node250band an output node electrically connected to a line L2. The line L2is arranged on an output side of the inverter IV4. The line L2electrically connects the output node of the inverter IV4and the output node250cof the comparison circuit250i. The clock φCKout can be output from the comparison circuit250ito the output node250c.

The inverter IV3has an input node electrically connected to the output node ON1of the cross point correction circuit230via the input node250aand an output node electrically connected to a line L1. The line L1is arranged on an output side of the inverter IV3. The line L1electrically connects the output node of the inverter IV3and the output node250dof comparison circuit250i. The clock φBCKout can be output from the comparison circuit250ito the output node250d.

The inverter IV5is electrically inserted with a first polarity between the line L1and the line L2. The first polarity can be a polarity with which the input node of the inverter IV5is electrically connected to the line L1and the output node of the inverter IV5is electrically connected to the line L2, for example.

The inverter IV6electrically inserted with a second polarity between the line L1and the line L2. The second polarity is a polarity opposite to the first polarity, and can be a polarity with which the output node of the inverter IV6is electrically connected to the line L1and the input node of the inverter IV6is electrically connected to the line L2, for example.

As described above, in the semiconductor device201i, the comparison circuit250iis configured using the plurality of inverters having the “back to back” configuration. Accordingly, a configuration having relatively large power consumption (for example, a current source in a differential amplifier) can be omitted, and the power consumption of the semiconductor device201ican be easily reduced.

Alternatively, as illustrated inFIG. 6, measures to enhance accuracy of adjustment of a duty ratio in a semiconductor device201jmay be added. In the semiconductor device201j, a comparison circuit250jmay be configured using a plurality of inverters having a “back to back” configuration in two stages in place of the comparator CP (differential amplifier) illustrated inFIG. 3.FIG. 6is a circuit diagram illustrating a configuration of the semiconductor device201jaccording to another modification of the second embodiment.

The comparison circuit250jfurther includes a plurality of inverters IV7, IV8, IV9, and IV10for the comparison circuit250i(seeFIG. 5). The inverter IV7has an input node electrically connected to the output node of the inverter IV3via the line L1and an output node electrically connected to a line L3. The line L3is arranged on an output side of the inverter IV7. The line L3electrically connects the output node of the inverter IV7and an output node250djof the comparison circuit250j. The clock φCKout can be output from the comparison circuit250jto the output node250dj.

The inverter IV8has an input node electrically connected to the output node of the inverter IV4via the line L2and an output node electrically connected to a line L4. The line L4is arranged on an output side of the inverter IV8. The line L4electrically connects the output node of the inverter IV8and an output node250cjof the comparison circuit250j. The clock φBCKout can be output from the comparison circuit250jto the output node250cj.

The inverter IV9is electrically inserted with a first polarity between the line L3and the line L4. The first polarity can be a polarity with which the input node of the inverter IV9is electrically connected to the line L3and the output node of the inverter IV9is electrically connected to the line L4, for example.

The inverter IV10is electrically inserted with a second polarity between the line L3and the line L4. The second polarity is a polarity opposite to the first polarity, and can be a polarity with which the output node of the inverter IV10is electrically connected to the line L3and the input node of the inverter IV10is electrically connected to the line L4, for example.

As described above, in the semiconductor device201j, the comparison circuit250jis configured using the plurality of inverters that realize the “back to back” configuration in two stages. With the configuration, the accuracy of the comparison operation in the comparison circuit250jcan be improved. Therefore, the cross points of the clock φCKout and the clock φBCKout after generation can be easily brought close to the vicinity of the appropriate level (for example, the intermediate level), and the cross points of the differential clocks can be corrected with high accuracy.

Third Embodiment

Next, a semiconductor device301according to a third embodiment will be described. Hereinafter, portions different from the first and second embodiments will be mainly described.

In the third embodiment, the measure in the first embodiment and the measure in the second embodiment are combined.

Specifically, the semiconductor device301further includes a comparison circuit250(seeFIG. 3) in addition to a receiver10, a phase splitter20, a cross point correction circuit30, and a cross point correction circuit40(seeFIG. 1), as illustrated inFIG. 7.FIG. 7is a diagram illustrating a configuration of the semiconductor device301.

A non-inverting-side clock output from the cross point correction circuit30will be referred to as φCKout_pre. An inverting-side clock output from the cross point correction circuit40will be referred to as φBCKout_pre. The comparison circuit250is arranged on an output side of the cross point correction circuit30and on an output side of the cross point correction circuit40. The input node250ais connected to an output node ON1of the cross point correction circuit30. The input node250bis connected to an output node ON2of the cross point correction circuit40.

The comparison circuit250receives the clock φCKout_pre from the cross point correction circuit30and receives the clock φBCKout_pre from the cross point correction circuit40. The comparison circuit250compares the clock φCKout_pre with the clock φBCKout_pre and outputs a clock φCKout and a clock φBCKout with corrected cross points of the clock φCKout_pre and the clock φBCKout_pre, as a comparison result. Details of the comparison circuit.250are similar to those of the second embodiment.

As described above, in the third embodiment, pull-up circuits33and43capable of pulling up an intermediate node on a power supply side and pull-down circuits34and44capable of pulling down an intermediate node on a ground side are provided in the cross point correction circuits30and40of the semiconductor device301. As a result, DCD can be suppressed for the first differential clock and the first differential clock can be appropriately generated.

Further, in the third embodiment, the second-stage cross point correction by the comparison circuit250is added to the first-stage cross point correction by the cross point correction circuits30and40in the semiconductor device301. As a result, the cross point correction can be appropriately performed in the case where the deviation in the edge timing between the non-inverting-side clock and the inverting-side clock is large.

Note that, as illustrated inFIG. 8, measures to reduce power consumption in a semiconductor device301imay be added. In the semiconductor device301i, a comparison circuit250imay be configured using a plurality of inverters having the “back to back” configuration illustrated inFIG. 5in place of the comparator CP (differential amplifier) illustrated inFIG. 3.FIG. 8is a circuit diagram illustrating a configuration of the semiconductor device301iaccording to a modification of the third embodiment. For details of the comparison circuit250i, the description given with reference toFIG. 5can be applied.

Alternatively, as illustrated inFIG. 9, measures to improve accuracy of adjustment of a duty ratio in the semiconductor device301jmay be added. In the semiconductor device301j, a comparison circuit250jmay be configured using a plurality of inverters having the “back to back” configuration illustrated inFIG. 6in two stages in place of the comparator CF (differential amplifier) illustrated inFIG. 3.FIG. 9is a circuit diagram illustrating a configuration of the semiconductor device301jaccording to another modification of the third embodiment. For details of the comparison circuit250j, the description given with reference toFIG. 6can be applied.

Next, a memory system100to which the semiconductor devices according to the first to third embodiments and the modifications are applied will be described with reference toFIG. 10.FIG. 10is a diagram illustrating a configuration of a memory system to which the semiconductor devices according to the first to third embodiments and the modifications are applied.

A memory system100can be connected to a host200and can function as an external storage medium of the host200. The host200is, for example, a personal computer, and the memory system100is, for example, an SSD, The memory system100includes a controller110and a semiconductor memory120. The controller110is a circuit as hardware, and includes a host interface circuit (host I/F)111, a signal processing circuit112, and a memory interface circuit (memory I/F)113.

For example, the host I/F111includes a semiconductor device1a. The semiconductor device1acan be applied to any of the semiconductor devices according to the first to third embodiments and the modifications. The host I/F111receives a predetermined signal from the host200. The host I/F111generates reference differential clocks φCK and φBCK from the predetermined signal and transfers tree reference differential clocks to the semiconductor device1a. The semiconductor device1areceives the reference differential clocks φCK and φBCK, generates internal differential clocks φCKout and φBCKout, using the reference clocks φCK and φBCK, and supplies the internal differential clocks φCKout and φBCKout to the signal processing circuit112. As a result, the internal differential clocks φCKout and φBCKout can be appropriately used in the signal processing circuit112, the memory I/F113, or the semiconductor memory120.

The memory I/F113includes a semiconductor device1b. The semiconductor device1bcan be applied to any of the semiconductor devices according to the first to third embodiments and the modifications. The memory I/F113receives a predetermined signal from the signal processing circuit112. The memory I/F113generates the reference differential clocks φCK and φBCK from the predetermined signal and transfers the reference differential clocks φCK and φBCK to the semiconductor device1b. The semiconductor device1breceives the reference differential clocks φCK and φBCK, generates the internal differential clocks φCKout and φBCKout, using the reference differential clocks φCK and φBCK, and uses or supplies the internal differential clocks φCKout and φBCKout to the semiconductor memory120. As a result, the internal differential clocks φCKout and φBCKout can be appropriately used in the memory I/F113or the semiconductor memory120.

The semiconductor memory120includes a semiconductor device1c. The semiconductor device1ccan be applied to any of the semiconductor devices according to the first to third embodiments and the modifications. The memory I/F113receives a predetermined signal from the signal processing circuit112. The memory I/F113generates the reference differential clocks φCK and φBCK from the predetermined signal and supplies the reference differential clocks φCK and φBCK to the semiconductor memory120. The semiconductor memory120transfers the supplied reference differential clocks φCK and φBCK to the semiconductor device1c. The semiconductor device1creceives the reference differential clocks φCK and φBCK, generates the internal differential clocks φCKout and φBCKout, using the reference differential clocks φCK and φBCK, and uses or supplies the internal differential clocks φCKout and φCKout to another circuit of the semiconductor memory120. As a result, the internal differential clocks φCKout and φBCKout can be appropriately used in the semiconductor memory120.