SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a field oxide layer formed on a substrate, a gate insulating layer formed on a surface portion of the substrate adjacent to one side of the field oxide layer, a gate electrode formed on the gate insulating layer and a portion of the field oxide layer, a source region formed in a surface portion of the substrate adjacent to one side of the gate electrode, and a drain region formed in a surface portion of the substrate adjacent to another side of the field oxide layer. A surface portion of the substrate on which the field oxide layer is formed is convex upward.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Korean Patent Application No. 10-2023-0001936, filed on Jan. 5, 2023, and all the benefits accruing therefrom under 35 U.S.C. § 119, the contents of which are incorporated by reference in their entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and a method of manufacturing the same. More specifically, the present disclosure relates to a high voltage semiconductor device such as a Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) device and a method of manufacturing the same.

BACKGROUND

Semiconductor devices such as LDMOS devices may be used in application circuits such as power switching circuits. The LDMOS device may include a gate electrode formed on a substrate, a source region and a drain region formed in surface portions of the substrate adjacent to the gate electrode, and a field oxide layer formed on a surface portion of the substrate between the gate electrode and the drain region. The field oxide layer may be used to increase the breakdown voltage of the LDMOS device.

In addition, the LDMOS device may include a drift region formed in the substrate, and the field oxide layer and the drain region may be formed on the drift region. For example, the field oxide layer may be formed through a Local Oxidation of Silicon (LOCOS) process. In such case, because the moving distance of electrons through the drift region under the field oxide layer may be increased, and thus, the on-resistance of the LDMOS device may be increased.

As another example, a field oxide pattern may be formed by forming a silicon oxide layer on the substrate through a chemical vapor deposition process and patterning the silicon oxide layer through an etching process. In the case of using the field oxide pattern, the moving distance of electrons may be reduced. However, the threshold voltage of the LDMOS device may increase and the current may decrease due to defects generated during the chemical vapor deposition process and the etching process.

SUMMARY

The present disclosure is to solve the above problems and provides a semiconductor device having improved electrical characteristics compared to the prior art and a method of manufacturing the same.

In accordance with an aspect of the present disclosure, a semiconductor device may include a field oxide layer formed on a substrate, a gate insulating layer formed on a surface portion of the substrate adjacent to one side of the field oxide layer, a gate electrode formed on the gate insulating layer and a portion of the field oxide layer, a source region formed in a surface portion of the substrate adjacent to one side of the gate electrode, and a drain region formed in a surface portion of the substrate adjacent to another side of the field oxide layer. Particularly, a surface portion of the substrate on which the field oxide layer is formed may be convex upward.

In accordance with some embodiments of the present disclosure, the field oxide layer may have a width that gradually increases downward.

In accordance with some embodiments of the present disclosure, the semiconductor device may further include a drift region formed in the substrate and a body region formed in the substrate. In such case, the source region may be formed in a surface portion of the body region, and the drain region may be formed in a surface portion of the drift region.

In accordance with some embodiments of the present disclosure, the semiconductor device may further include a body contact region formed in a surface portion of the body region adjacent to one side of the source region.

In accordance with another aspect of the present disclosure, a method of manufacturing a semiconductor device may include forming a field oxide layer on a substrate, forming a gate insulating layer on a surface portion of the substrate adjacent to one side of the field oxide layer, forming a gate electrode on the gate insulating layer and a portion of the field oxide layer, forming a source region in a surface portion of the substrate adjacent to one side of the gate electrode, and forming a drain region in a surface portion of the substrate adjacent to another side of the field oxide layer. Particularly, a surface portion of the substrate on which the field oxide layer is formed may be convex upward while the field oxide layer is formed.

In accordance with some embodiments of the present disclosure, forming the field oxide layer may include forming a silicon layer on the substrate, forming a hard mask pattern on the silicon layer to expose a portion of the silicon layer, performing a first thermal oxidation process to oxidize the exposed portion of the silicon layer so that a preliminary field oxide layer having a bird's beak-shaped side portion is formed, removing the hard mask pattern, etching the silicon layer so that a ring-shaped silicon pattern remains under the side portion of the preliminary field oxide layer, and performing a second thermal oxidation process to oxidize the ring-shaped silicon pattern so that the field oxide layer is formed.

In accordance with some embodiments of the present disclosure, forming the field oxide layer may further include forming a pad oxide layer on the substrate. In such case, the silicon layer may be formed on the pad oxide layer.

In accordance with some embodiments of the present disclosure, forming the field oxide layer may further include removing the pad oxide layer after performing the second thermal oxidation process.

In accordance with some embodiments of the present disclosure, the first thermal oxidation process may be performed until the preliminary field oxide layer is reached on the pad oxide layer.

In accordance with some embodiments of the present disclosure, the method may further include forming a body region and a drift region in the substrate before forming the field oxide layer. In such case, the source region may be formed in a surface portion of the body region, and the drain region may be formed in a surface portion of the drift region.

In accordance with some embodiments of the present disclosure, the method may further include forming a body contact region in a surface portion of the body region adjacent to one side of the source region.

In accordance with still another aspect of the present disclosure, a method of manufacturing a semiconductor device may include forming a silicon layer on a substrate, forming a hard mask pattern on the silicon layer to expose a portion of the silicon layer, performing a first thermal oxidation process to oxidize the exposed portion of the silicon layer so that a preliminary field oxide layer having a bird's beak-shaped side portion is formed, removing the hard mask pattern, performing a first etch-back process so that a ring-shaped silicon pattern remains under the side portion of the preliminary field oxide layer, performing a second thermal oxidation process to oxidize the ring-shaped silicon pattern so that a field oxide layer is formed, performing a second etch-back process until the substrate is exposed, forming a gate insulating layer on a surface portion of the substrate adjacent to one side of the field oxide layer, forming a gate electrode on the gate insulating layer and a portion of the field oxide layer, forming a source region in a surface portion of the substrate adjacent to one side of the gate electrode, and forming a drain region in a surface portion of the substrate adjacent to another side of the field oxide layer.

In accordance with some embodiments of the present disclosure, the method may further include forming a pad oxide layer on the substrate. In such case, the silicon layer may be formed on the pad oxide layer.

In accordance with some embodiments of the present disclosure, the pad oxide layer may be removed by the second etch-back process.

In accordance with some embodiments of the present disclosure, the first thermal oxidation process may be performed until the preliminary field oxide layer is reached on the pad oxide layer.

In accordance with some embodiments of the present disclosure, the method may further include forming a body region and a drift region in the substrate before forming the silicon layer. In such case, the source region may be formed in a surface portion of the body region, and the drain region may be formed in a surface portion of the drift region.

In accordance with some embodiments of the present disclosure, the method may further include forming a body contact region in a surface portion of the body region adjacent to one side of the source region.

In accordance with the embodiments of the present disclosure as described above, the surface portion of the substrate on which the field oxide layer is formed may be convex upward, and thus, the moving distance of electrons moving from the source region to the drain region and the on-resistance of the semiconductor device may be reduced. In addition, the interface between the field oxide layer and the substrate may be spaced upward from the movement path of the electrons. Accordingly, the Hot Carrier Injection (HCI) effect may be reduced, and the threshold voltage of the semiconductor device may be stably maintained in comparison with the prior art using the field oxide pattern.

The above summary of the present disclosure is not intended to describe each illustrated embodiment or every implementation of the present disclosure. The detailed description and claims that follow more particularly exemplify these embodiments.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments described below and is implemented in various other forms. Embodiments below are not provided to fully complete the present disclosure but rather are provided to fully convey the range of the present disclosure to those skilled in the art. In the specification, when one component is referred to as being on or

connected to another component or layer, it can be directly on or connected to the other component or layer, or an intervening component or layer may also be present. Unlike this, it will be understood that when one component is referred to as directly being on or directly connected to another component or layer, it means that no intervening component is present. Also, though terms like a first, a second, and a third are used to describe various regions and layers in various embodiments of the present disclosure, the regions and the layers are not limited to these terms.

Terminologies used below are used to merely describe specific embodiments, but do not limit the present disclosure. Additionally, unless otherwise defined here, all the terms including technical or scientific terms, may have the same meaning that is generally understood by those skilled in the art.

Embodiments of the present disclosure are described with reference to schematic drawings of ideal embodiments. Accordingly, changes in manufacturing methods and/or allowable errors may be expected from the forms of the drawings. Accordingly, embodiments of the present disclosure are not described being limited to the specific forms or areas in the drawings, and include the deviations of the forms. The areas may be entirely schematic, and their forms may not describe or depict accurate forms or structures in any given area, and are not intended to limit the scope of the present disclosure.

FIG.1is a schematic cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present disclosure.

Referring toFIG.1, a semiconductor device100, in accordance with an embodiment of the present disclosure, may be used as an LDMOS device, and may include a field oxide layer130formed on a substrate102, a gate insulating layer140formed on a surface portion of the substrate102adjacent to one side of the field oxide layer130, a gate electrode142formed on the gate insulating layer140and a portion of the field oxide layer130, a source region150formed in a surface portion of the substrate102adjacent to one side of the gate electrode142, and a drain region152formed in a surface portion of the substrate102adjacent to another side of the field oxide layer130, for example, to an opposite side of the field oxide layer130.

A body region106and a drift region108may be formed in the substrate102. The substrate102may have a first conductivity type, and the drift region108may have a second conductivity type. For example, a P-type substrate may be used as the substrate102, and the drift region108may be an N-type impurity diffusion region. The body region106may have the first conductivity type. For example, the body region106may be a P-type impurity diffusion region.

In addition, as shown inFIG.1, the substrate102may include a P-type epitaxial layer104. In such case, the body region106and the drift region108may be formed in the P-type epitaxial layer104. For example, the source region106may be formed by implanting P-type impurities into the P-type epitaxial layer104, and the drift region108may be formed by implanting N-type impurities into the P-type epitaxial layer104. Further, as shown inFIG.1, the drift region108may be laterally spaced apart from the body region106by a predetermined distance.

The source region150may be formed in a surface portion of the body region106adjacent to one side of the gate electrode142, and the drain region152may be formed in a surface portion of the drift region108adjacent to another side of the field oxide layer130. The source region150and the drain region152may have the second conductivity type. For example, high-concentration N-type impurity diffusion regions may be used as the source region150and the drain region152.

A body contact region154may be formed in a surface portion of the body region106adjacent to one side of the source region150. The body contact region154may have the first conductivity type. For example, a high-concentration P-type impurity diffusion region may be used as the body contact region154.

In accordance with an embodiment of the present disclosure, as shown inFIG.1, a surface portion102A (refer toFIG.5) of the substrate102on which the field oxide layer130is formed may be convex upward. That is, a surface portion of the substrate102on which the gate insulating layer140is formed may be lower than the surface portion102A of the substrate102on which the field oxide layer130is formed. Therefore, in comparison with the prior art using a field oxide layer formed through a LOCOS process, the movement distance of electrons moving from the source region150to the drain region152may be reduced, and accordingly, the on-resistance of the semiconductor device100may be reduced.

Further, the interface between the field oxide layer130and the substrate102may be spaced upward from the movement path of the electrons. Accordingly, the HCI effect in which the electrons are trapped in the interface portions between the field oxide layer130and the substrate102may be reduced. As a result, the threshold voltage of the semiconductor device100may be stably maintained in comparison with the prior art using the field oxide pattern.

In addition, as shown inFIG.1, the field oxide layer130may have an outwardly inclined side surface. That is, the field oxide layer130may have a width that gradually increases downward. Accordingly, the concentration of electric field between the gate insulating layer140and the field oxide layer130may be reduced.

FIGS.2to8are schematic cross-sectional views illustrating a method of manufacturing the semiconductor device as shown inFIG.1.

Referring toFIG.2, a body region106and a drift region108may be formed in a substrate102. The substrate102and the body region106may have a first conductivity type, and the drift region108may have a second conductivity type. For example, a P-type substrate may be used as the substrate102and may include a P-type epitaxial layer104as shown inFIG.2. In such case, the body region106and the drift region108may be formed in the P-type epitaxial layer104. For example, the body region106may be a P-type impurity diffusion region formed by an ion implantation process, and the drift region108may be an N-type impurity diffusion region formed by an ion implantation process. Further, the drift region108may be laterally spaced apart from the source region106by a predetermined distance.

A pad oxide layer110may be formed on the substrate102. For example, the pad oxide layer110may be formed through a thermal oxidation process to reduce defects at an interface with the substrate102. A silicon layer112may be formed on the pad oxide layer110. For example, a polysilicon layer or an amorphous silicon layer may be formed on the pad oxide layer110through a chemical vapor deposition process.

A hard mask pattern114having an opening116exposing a portion of the silicon layer112may be formed on the silicon layer112. The hard mask pattern114may be made of silicon nitride, and the opening116may be formed above the drift region108. For example, the hard mask pattern114may be formed by forming a silicon nitride layer on the silicon layer112and then patterning the silicon nitride layer.

Referring toFIG.3, a first thermal oxidation process may be performed to oxidize the portion of the silicon layer112exposed by the hard mask pattern114. A preliminary field oxide layer120including a side portion122having a bird's beak shape may be formed on the pad oxide layer110by the first thermal oxidation process. In such case, the first thermal oxidation process may be performed until the preliminary field oxide layer120is reached on the pad oxide layer110.

Referring toFIG.4, after forming the preliminary field oxide layer120, the hard mask pattern114may be removed. For example, the hard mask pattern114may be removed through a wet etching process.

Then, the silicon layer112may be etched so that a ring-shaped silicon pattern124remains under the side portion122of the preliminary field oxide layer120. For example, a first etch-back process may be performed, whereby the ring-shaped silicon pattern124may remain under the side portion122of the bird's beak shape.

Referring toFIG.5, a second thermal oxidation process may be performed to form a field oxide layer130on the substrate102. The ring-shaped silicon pattern124may be oxidized by the second thermal oxidation process. In particular, a thickness of the pad oxide layer110may be increased, except for a portion on which the preliminary field oxide layer120is formed. As a result, a field oxide layer130including the preliminary field oxide layer120, a portion of the pad oxide layer110under the preliminary field oxide layer120, and an oxide portion formed from the ring-shaped silicon pattern124may be formed on the substrate102.

In particular, as shown inFIG.5, the thickness of the pad oxide layer110may be increased by the second thermal oxidation process, and accordingly, a surface portion (a portion indicated by a dotted line)102A of the substrate102on which the field oxide layer130is formed may relatively protrude upward. In addition, as the ring-shaped silicon pattern124is oxidized, the field oxide layer130may have a width gradually increasing downward and a side surface inclined outward.

Referring toFIG.6, after forming the field oxide layer130, a second etch-back process may be performed until the substrate102is exposed, thereby removing the pad oxide layer110. At this time, a surface portion of the field oxide layer130may be removed by the second etch-back process, and thereby a thickness of the field oxide layer130may be reduced by the thickness of the pad oxide layer110.

Referring toFIG.7, a gate insulating layer140may be formed on a surface portion of the substrate102adjacent to one side of the field oxide layer130. For example, a thermal oxidation process may be performed after removing the pad oxide layer110, thereby forming a silicon oxide layer on the substrate102.

Subsequently, a gate electrode142may be formed on the gate insulating layer140and a portion of the field oxide layer130. For example, the gate electrode142may be formed above a portion of the body region106, a portion of the drift region108, and a portion of the P-type epitaxial layer104between the body region106and the drift region108as shown inFIG.7. For example, the gate electrode142may be formed by forming an impurity-doped polysilicon layer on the field oxide layer130and the silicon oxide layer, and then patterning the impurity-doped polysilicon layer. In such case, a portion of the silicon oxide layer formed between the gate electrode142and the substrate102may function as the gate insulating layer140.

Referring toFIG.8, a source region150may be formed in a surface portion of the substrate102adjacent to one side of the gate electrode142, and a drain region152may be formed in a surface portion of the substrate102adjacent to another side of the field oxide layer130. For example, the source region150and the drain region152may be high-concentration N-type impurity diffusion regions and may be simultaneously formed by an ion implantation process. Specifically, the source region150may be formed in a surface portion of the body region106adjacent to the gate electrode142, and the drain region152may be formed in a surface portion of the drift region108adjacent to the field oxide layer130.

Further, a body contact region154may be formed in a surface portion of the body region106adjacent to one side of the source region150, and a gate spacer may be formed on side surfaces of the gate electrode142. For example, the body contact region154may be a high-concentration P-type impurity diffusion region and may be formed by an ion implantation process.

In accordance with the embodiments of the present disclosure as described above, the surface portion102A of the substrate102on which the field oxide layer130is formed may be convex upward, and thus, the moving distance of electrons moving from the source region150to the drain region152and the on-resistance of the semiconductor device100may be reduced. In addition, the interface between the field oxide layer130and the substrate102may be spaced upward from the movement path of the electrons. Accordingly, the HCI effect may be reduced, and the threshold voltage of the semiconductor device100may be stably maintained in comparison with the prior art using the field oxide pattern.

Although the example embodiments of the present disclosure have been described with reference to the specific embodiments, they are not limited thereto. Therefore, it will be readily understood by those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the present disclosure defined by the appended claims.