Wiring board, semiconductor device and semiconductor element

On a semiconductor element loading face, wiring patterns are drawn out from those formed in the vicinity of the edge of the semiconductor element of the loading pads formed to correspond to the electrode terminals of the semiconductor element, and connected to via pads formed in the vicinity of the edge of the semiconductor element loading face; area pads constructed of the loading pads corresponding to the electrode terminals formed in the central region of the semiconductor element and its vicinity are electrically connected to external connecting terminal pads formed in the central region on the other side of the wiring board and its vicinity, through the nearest area pad vias encircled by the external connecting terminal pads and passing through the wiring board and the wiring patterns; and a plurality of the loading pads constituting the area pads commonly use one of the area pad vias.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. §119 from Japanese Patent Application No. 2008-299052 filed on Nov. 25, 2008.

BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates to a wiring board, a semiconductor device and a semiconductor element, and more particularly to a wiring board on which a semiconductor element with electrode terminals on the entire face of the one side thereof is loaded, a semiconductor device with the semiconductor element loaded on the wiring board, and a semiconductor element loaded on the wiring board.

2. Related Art

On the one side of a wiring board100with a conventional semiconductor element102loaded thereon as shown inFIG. 12A, formed is a semiconductor element loading face having a wider area than that of the semiconductor element102to be loaded. On the semiconductor element loading face, pads104,104, . . . are formed which are to be connected with electrode terminals formed in the vicinity of the edge of the semiconductor element102.

From these pads104,104, . . . , wiring patterns108are drawn out to via pads106formed in the vicinity of the edge of the semiconductor element loading face outside the semiconductor element102to be loaded, respectively.

In contrast to such a semiconductor element loading face, on the backside of the wiring board100, as shown inFIG. 12B, external connecting pads114,114, . . . are arranged in a lattice pattern. The via pads106,106, . . . are connected to pads110through vias passing through the wiring board100and further connected to the corresponding external connecting pads114through wiring patterns112.

Meanwhile, in recent years, with development of high performance and miniaturization, the electrode terminals of the semiconductor element has been formed with high density. Namely, as shown inFIG. 10, electrode terminals202,202, have become formed on the entire face of the one side of the semiconductor element200.

In the wiring board on which a semiconductor element200is to be loaded, as shown inFIG. 10, on the semiconductor element loading face, the loading pads corresponding to the electrode terminals202,202, . . . of the semiconductor element200must be formed, and the wiring patterns108must be also drawn from the loading pads to the via pads106formed in the vicinity of the edge of the wiring board, respectively.

However, the pitch between the loading pads corresponding to the electrode terminals202,202, of the semiconductor element200is so narrow that the number of the wiring patterns capable of being formed between the loading pads is limited. As a result, with the wiring board being formed of multiple layers, the wiring patterns which cannot be formed must be drawn to the via pads106.

The following Patent Reference 1 discloses a semiconductor device in which the semiconductor element200with the electrode terminals202,202, . . . formed on the entire surface of the one side is loaded on the board with the wiring board being not formed of multiple layers.

FIG. 11shows such a semiconductor device. In the semiconductor device shown inFIG. 11, the electrode terminals202,202, . . . of the semiconductor element200are electrically connected with the corresponding external connecting terminals206,206formed on a board204through soldering bumps208, respectively.

In the semiconductor device shown inFIG. 11, without routing the wiring patterns on the board, the electrode terminals202,202, . . . of the semiconductor element200are electrically connected with the corresponding external connecting terminals206, respectively.

In the semiconductor device shown inFIG. 11, however, the external connecting terminals206of the board204are formed immediately below the electrode terminals202of the semiconductor element200so that the pitch between the electrode terminals202,202, . . . of the semiconductor element200is equal to that between the external connecting terminals206,206, . . . of the board204. Owing to this fact, the number of the external connecting terminals206capable of being formed at the board204will be limited.

Further, it is required that the pitch between the external connecting terminals206,206, . . . formed on the board204is changed in the relationship with the mounting pads of a mounting board in which the semiconductor device is mounted.

However, it is very difficult to satisfy this requirement in the semiconductor device shown inFIG. 11because the pitch between the electrode terminals202,202, of the semiconductor element200must be first changed.

SUMMARY OF THE INVENTION

In view of the above circumstance, an object of this invention is to provide a wiring board, a semiconductor device and a semiconductor element capable of solving the problem of a conventional semiconductor device in which the number of the external connecting terminals capable of being formed on a wiring board is limited and the pitch between the external connecting terminals is difficult to change; solving the problem of limitation of the number of the external connecting terminals capable of being formed on the wiring board; and easily changing the pitch between the external connecting terminals.

The inventors have investigated in order to solve the above problems, and found out that the number of the wiring patterns formed on the semiconductor element loading face can be minimized and external connecting terminals can be formed on the entire face of the other side of the wiring board by providing, on a semiconductor element loading face formed on the one side of the wiring board and having a wider area than that of the semiconductor element, both of via pads formed in the vicinity of the edge of the semiconductor element loading face, and also areas pads constructed of the loading pads corresponding to electrode terminals formed in the central region of the semiconductor element and its vicinity, the via pads and the area pads being connected with each other from the loading pads corresponding to the electrode terminals formed at the edge of the semiconductor element through wiring patterns; and by electrically connecting each of the area pads to the external connecting terminal pads formed on the other side of the wiring board, respectively through the nearest area pad vias encircled by the external connecting terminal pads and passing through the wiring board and the wiring patterns.

According to a first aspect of this invention, there is provided a wiring board for a semiconductor device in which a semiconductor element with electrode terminals formed on the entire face of one side of the wiring board, wherein on a semiconductor element loading face formed on the one side of the wiring board and having an area wider than an area of the semiconductor element,

the wiring board including:

wiring patterns which are drawn out from loading pads formed in the vicinity of the edge of the semiconductor element in the loading pads formed so as to correspond to the electrode terminals formed on the semiconductor element, respectively and connected to via pads formed in the vicinity of the edge of the semiconductor element loading face;

area pads constructed of the loading pads corresponding to the electrode terminals formed in a central region of the semiconductor element and a vicinity of the central region, which are electrically connected to external connecting terminal pads formed in a lattice pattern in a central region on the other side of the wiring board and a vicinity of the central region so as to correspond to the area pads, respectively through the nearest area pad vias encircled by the external connecting terminal pads formed in a lattice pattern and passing through the wiring board and the wiring patterns; and

a plurality of the loading pads constituting the area pads commonly use one of the area pad vias.

According to a second aspect of this invention, there is provided the wiring board according to the first aspect, wherein

the one end of each the area pad vias is directly connected to each the external connecting terminal pads.

Thereby, the connecting distance between the loading pad and the corresponding external connecting terminal pad can be further shortened.

According to a third aspect of this invention, there is provided the wiring board according to the first or second aspect, wherein

the wiring board is formed of a single insulative layer with top and bottom conductive layers.

According to a forth aspect of this invention, there is provided the wiring board according to any one of the first to third aspects, wherein

the plurality of loading pads constituting the area pads commonly using the one area pad via are power supply pads or grounding pads.

Thereby, the correcting distance between the power supply pad or grounding pad and the corresponding external connecting terminal pad can be shortened to the utmost.

According to a fifth aspect of this invention, there is provided the wiring board according to any one of the first to forth aspects, wherein

the loading pads connected to the via pads through the wiring patterns are signal electrode pads.

Thereby, the power supply pads or grounding pads can be concentrated in the central region of the wiring board and its vicinity.

According to a sixth aspect of this invention, there is provided a semiconductor device, wherein

the semiconductor element is loaded on the semiconductor element loading face of the wiring board according to any one of the first to fifth aspects.

According to a seventh aspect of this invention, there is provided the semiconductor device according to the sixth aspect, wherein

one or both of power supply electrode terminals and grounding electrode terminals are mainly mixedly formed in a central region of the semiconductor element, and

signal electrode terminals are mainly formed at an edge of the semiconductor element.

According to an eighth aspect of this invention, there is provided the semiconductor element loaded on the semiconductor element loading face of the wiring board according to any one of the first to fifth aspects, wherein

one or both of power supply electrode terminals and grounding electrode terminals are mainly mixedly formed in a central region of the semiconductor element, and

signal electrode terminals are mainly formed at an edge of the semiconductor element.

According to a ninth aspect of this invention, there is provided the wiring board according to the first aspect, wherein

the wiring board is formed of a multi layer thereof.

In the wiring board according to this invention, by providing both of the area pads and via pads on the semiconductor element loading face, the semiconductor element with the electrode terminals on the entire face of the one side thereof can be easily loaded thereon. Specifically, the electrode terminals formed at the center region of the semiconductor element and its vicinity can be connected to the loading pads constituting the area pads of the wiring board while the electrode terminals formed in the vicinity of the edge of the semiconductor element can be connected to the loading pads connected to the via pads through the wiring patterns.

The loading pads of these area pads are connected respectively to the corresponding external connecting terminal pads formed on the other side of the wiring board through vias passing through the wiring board. Further, since the via pads are formed in the vicinity of the edge of the wiring board, they may be connected to the external connecting terminal pads formed on the other side of the wiring board through the vias passing through the wiring board, or may be connected to predetermined points of e.g. a mounting board through wire bonding.

In this way, on the entire face of the other side of the wiring board having a wider area than that of the semiconductor element to be loaded, the necessary number of external connecting terminal pads can be formed. Thus, limitation of the number of the external connecting terminals which can be formed on the wiring board can be cancelled and the pitch between the external connecting terminals can be easily charged.

In addition, in this invention, the loading pads constituting the area pads of the wiring board are electrically connected to the external connecting terminal pads formed in a lattice pattern in the central region of the other side of the wiring board and its vicinity through the nearest area pad vias passing through the wiring board encircled by the external connecting terminal pads and the wiring patterns; and further the plurality of loading pads constituting the area pads commonly use one of the area pad vias. Thus, the connecting distance between the loading pads constituting the area pads and the corresponding external connecting terminal pads can be shortened to the utmost so that when the loading pads are used as the power supply pads, changes in a voltage can be prevented.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An example of a semiconductor element to be loaded on a wiring board according to this invention is shown inFIG. 1A. In the semiconductor element10shown inFIG. 1A, electrode terminals12,12, . . . are formed on the entire surface of its one side. Of these electrode terminals12,12, . . . , the electrode terminals12,12formed in the central region encircled by a dotted line and its vicinity are mainly those for power supply and for grounding.

Further, the electrode terminals12, formed in two rows on the edge side of the semiconductor element10(outside the dotted line) are mainly those for signals.

The wiring board20shown inFIG. 1Bon which the above semiconductor element10is loaded is formed of a resin board of a single layer. A semiconductor element loading face is formed on the one side of the wiring board20, and as seen formFIG. 1B, it has a wider area than that of the semiconductor element10. On the semiconductor element loading face, formed are loading pads22corresponding to the electrode terminals12,12, . . . formed on the semiconductor element10, respectively.

Of these loading pads22,22, . . . , the loading pads22,22, . . . formed in the central region encircled by a dotted line and its vicinity are area pads to be connected to the electrode terminals12,12, . . . composed mainly of electrode terminals for power supply and electrode terminals for grounding.

Further, the loading pads22,22, . . . formed in two rows on the edge side of the wiring board20(outside the dotted line) will be connected to the electrode terminals12,12, . . . of mainly those for signals . . . formed in two rows on the edge side of the semiconductor element10.

From the loading pads22,22, . . . formed in two rows on the edge side of the wiring board20, wiring patterns24formed on the one side of the wiring board20are drawn out and connected to via pads26formed in the vicinity of the edge of the wiring board20. The wiring patterns24must be drawn between the loading pads22,22, . . . formed on the outermost side; but usually, there is a gap sufficient to form a single wiring pattern24bet between the loading pads22,22.

Further, as seen fromFIG. 1B, the via pads26,26, . . . are formed at the positions outside the semiconductor element10to be loaded and in the vicinity of the edge of the wiring board20.

As described above, since the via pads26,26, . . . are formed in the vicinity of the edge of the semiconductor element10to be loaded, there is great flexibility in the connection between the via pads26,26, . . . and other pads. For example, the via pads26,26, . . . can be connected through vias passing through the wiring board20to the external connecting pads formed on the other side of the wiring board20. Otherwise, predetermined points of a mounting board for mounting the wiring board20can be connected to the via pads26,26, . . . through wire bonding, respectively.

In the wiring board20shown inFIG. 1B, the loading pads22,22, . . . formed in two rows on the edge side of the wiring board20are connected to the via pads26formed in the vicinity of the edge of the wiring board20. For this reason, on the other side of the wiring board20, over the entire face of the area corresponding to the loading face on which the semiconductor element10is loaded (area encircled by one-dot chain line inFIG. 1B), pads for external connecting terminals (external connecting terminal pads) can be formed which correspond to area pads of the loading pads22,22, . . . formed in the ventral region on the one side of the wiring board20and its vicinity (area encircled by a dotted line). Thus, it is possible to form the necessary number of the external connecting terminal pads for the semiconductor element10to be loaded and easily deal with changes in the pitch between the external connecting terminals.

These external connecting terminal pads, as shown inFIG. 2, are formed in a lattice pattern on the other side of the wiring board20.

Vias30for area pads (area pad vias30), formed in the vicinity of the central region of the area encircled by the external connecting terminal pads28,28. . . formed in a lattice pattern and passing through the wiring board20, are connected to the loading pads22constituting the nearest area pads through the wiring patterns. In the wiring board20shown inFIG. 2, the loading pads22are formed on the one side of the wiring board20so as to correspond to the external connecting terminal pads28formed on the other side of the wiring board20. Further, also at the positions located between the external connecting terminal pads28,28for, the loading pads22are formed.

The state where these loading pads22and the external connecting terminal pads28for are connected with each other is shown inFIGS. 3A to 3C.FIG. 3Ashows the state where the loaning pad22and external connecting terminal pad28are connected to each other in one-to-one correspondence. The loading pad22formed on the one side of the wiring board20so as to correspond to the external connecting terminal pad28formed on the other side of the wiring board20is connected to the one end of the nearest area pad via30through the wiring pattern34formed on the one side of the wiring board20. The area pad via30is a through-hole via whose other end is connected to the external connecting terminal pad28through the wiring pattern34formed on the other side of the wiring board20. The external connecting terminal pad28is covered with an external connecting terminal of a solder ball32.

In this way, the loading pad22constituting the area pad is permitted to shorten the connecting distance to the external connecting terminal pad28to the utmost by the nearest area pad via30.

The loading pads22,22, . . . constituting the area pads are connected to the electrode terminals which are mainly the power supply terminals and grounding terminals of the semiconductor element10. Therefore, as the case may be, both of the adjacent loading pads22,22are the loading pads connected to the power supply terminals or the grounding terminals of the semiconductor element10. In this case, as shown inFIG. 3B, the loading pads22,22can commonly use a single area pad via30. By commonly using the single area pad via30, the number of the area pad vias30and also the number of the external connecting terminal pads28can be reduced.

Further, as shown inFIG. 3C, the loading pads22,22and external connecting terminal pad28,28may commonly use the single area pad via30.

It should be noted that the wiring board20may have three kinds of connecting types ofFIGS. 3A,3B and3C.

When the semiconductor element10shown inFIG. 1Ais loaded on the semiconductor element loading face of the wiring board23shown inFIG. 1Bthereby to obtain the semiconductor device, the power supply electrode terminals or grounding electrode terminals formed in the central region of the semiconductor element10and its vicinity are connected to the loading pads22,22, . . . constituting the area pads of the wiring board20.

The connecting distance between each of the loading pads22,22, . . . of these area pads and the corresponding external connecting terminal pad28, as shown inFIGS. 2 and 3, can be shortened to the utmost. For this reason, in the semiconductor device thus obtained, changes in the voltage supplied from the power supply terminal can be prevented to utmost so that the performance of the semiconductor device can be improved.

The area pad vias30shown inFIGS. 2 and 3are formed in the vicinity of the central region of the area encircled by the external connecting terminal pads28,28, . . . formed in a lattice pattern. However, as shown inFIG. 4, the area pad vias30may be directly connected to the external connecting terminal pads28,28, . . . , respectively. The state where the loading pad22and external connecting terminal pad28, shown inFIG. 4are connected to each other is shown inFIG. 5.FIG. 5Ashows the state where the loading pad22and external connecting terminal pad28are connected to each other in one-to-one correspondence.FIG. 5Bshows the state where the loading pads22,22commonly use the single area pad via30.

The connecting distance between the loading pad22and the corresponding external connecting terminal pad28, shown inFIGS. 4 and 5can be more greatly shortened than that between the loading pad22and the corresponding external connecting terminal pad28, shown inFIGS. 2 and 3.

In the wiring board20shown inFIGS. 2 to 5, the one end of the area pad via30being the through-hole via is hollow at the center. As shown inFIG. 6, each of the loading pads22,22, . . . may be directly connected to the one end of the area pad via30. The state where the loading pad22and external connecting terminal pad28, shown inFIG. 6are connected to each other is shown inFIG. 7.FIG. 7Ashows the state where the loading pad22and external connecting terminal pad28are connected to each other in one-to-one correspondence.FIG. 7Bshows the state where the loading pads22,22commonly use the single external connecting terminal pad28.

In such as a manner that the area pad via30is solid at the center, at both ends of the area pad via30, the loading pad22and external connecting terminal pad28can be easily formed.

As shown inFIG. 7, each of the loading pads22,22, . . . is directly connected to the one end of the area pad via30. In addition, the other end of the area pad via30is connected to each of the external connecting terminal pads28,28, . . . . For this reason, the connecting distance between the loading pad22and external connecting terminal pad28can be shortened to the maximum.

As shown inFIGS. 6 and 7, where it is difficult that the loading pad22and external connecting terminal pad28are formed at both ends of the area pad via30, the external connecting terminal pad28may be connected to the one end of the area pad via30formed in the central region encircled by the external connecting terminal pads28,28, . . . arranged in a lattice pattern as shown inFIG. 8. In this case, it is not necessary to form the loading pad22on the semiconductor element loading face of the wiring board20corresponding to the external connecting terminal pads28,28, . . . . The state where the loading pad22and external connecting terminal pad28, shown inFIG. 8are connected to each other is shown inFIG. 9.FIG. 9Ashows the state where the loading pad22and external connecting terminal pad28are connected to each other in one-to-one correspondence.FIG. 9Bshows the state where the loading pads22,22commonly use the single external connecting terminal pad28.