Techniques to converge and adapt a communication system receiver

A system, apparatus, method and article to converge a communications system receiver are described. The apparatus may include an interference canceller to receive an interference signal and to produce an adaptive signal. The interference canceller is adapted by a first adaptation module. An equalizer is coupled to the interference canceller. The interference canceller is located before the equalizer. The equalizer receives an input signal formed of a sum of a received input signal and the adaptive signal. A slicer is coupled to the equalizer and to the interference canceller. The slicer receives an equalized version of equalizer coefficients and produces a slicer error. The first adaptation module adapts the interference canceller utilizing a convolution of the interference signal with the equalizer coefficients, and multiplying the results by the slicer error. Other embodiments are described and claimed.

BACKGROUND

High speed communication systems capable of higher throughput data rates are emerging. Gigabit Ethernet networks may communicate information at 1 gigabits-per-second (Gbps) or higher over high speed channels. These high speed channels, however, typically realize a corresponding increase in error rates. Techniques such as forward error correction may be used to decrease the error rates. Such techniques, however, may require a communication system to communicate additional overhead in the form of error correcting information. The additional overhead may decrease the effective throughput for a communication system.

A typical physical communication channel, such as an Ethernet cable, for example, introduces inter-symbol interference (ISI) in a received data signal. To minimize the adverse effects of ISI and to improve signal-to-noise ratio (SNR), it is customary to include a filter in the receiver known as an “equalizer.” In some receivers, the entire equalizer may be adaptive. In such cases, however, convergence of the equalizer may be rather slow. In other receivers a fixed equalizer may be used in combination with an adaptive equalizer to provide improved convergence. Even with use of a combination of fixed and adaptive equalizers, however, convergence of the adaptive equalizer may be slower than desirable.

A communications system that includes passing a signal through a channel which introduces ISI and at least one additional interference signal (e.g., an echo signal, transmitted by near-end transmitter device, which has passed through an echo channel) in addition to jitter of the sampling clock at the analog-to-digital (A/D) converter in the receiver, results in a time-variant interference channel. This time-variant interference channel requires the adaptation of an interference canceller. An adaptive interference canceller adaptively filters a noise reference input to maximally match and subtract out noise or interference from a primary input signal (e.g., desired signal plus noise). In order to meet communications system performance requirements, it may be necessary to perform equalization and adaptation in order to reduce the ISI in the system. In addition, it may be necessary to include an interference canceller (e.g., an echo canceller) to cancel the interference described above. The interference canceller may be adapted using one of multiple adaptation processes and/or algorithms. For example, adaptation may be implemented using any of the well-known methods (e.g., least-mean-squares or LMS, recursive least squares or RLS, or Fast RLS).

These methods are well known adaptation algorithm. Briefly, an LMS adaptation algorithm, for example, uses an instantaneous estimate of a gradient vector of a cost function to generate an approximation of the steepest descent algorithm. The instantaneous estimate of the gradient is based on sampled values of a tap-input vector and an error signal. The algorithm iterates over each coefficient in the filter and moves it in the direction of the approximated gradient. The LMS algorithm requires a reference signal that represents the desired filter output. The difference between the reference signal and the actual output of the transversal filter is known as the error signal. An adaptation process employing the LMS algorithm determines a set of filter coefficients that minimize the expected value of a quadratic error signal, i.e., to achieve the least mean squared error (thus the name). As the LMS, RLS, and fast RLS are well known, no further details of these adaptation techniques are necessary for an understanding of the embodiments and examples described and illustrated herein.

DETAILED DESCRIPTION

Various embodiments may be generally directed to techniques to converge a communications receiver. In one embodiment, for example, an apparatus may include an interference canceller to receive an interference signal and to produce an adaptive signal. The interference canceller is adapted by a first adaptation module. An equalizer is coupled to the interference canceller. The interference canceller is located before the equalizer. The equalizer receives an input signal formed of a sum of a received input signal and the adaptive signal. A slicer is coupled to the equalizer and to the interference canceller. The slicer receives an equalized version of the equalizer input signal and produces a slicer error. The first adaptation module adapts the interference canceller utilizing a convolution of the interference signal with the equalizer coefficients, and multiplying the result by the slicer error. Other embodiments are described and claimed. In this manner, the receiver can be adapted to converge using multiple adaptation modules, increase receiver and communication system performance, and reduce power consumption. Other embodiments may be described and claimed.

Various embodiments may comprise one or more elements. An element may comprise any structure arranged to perform certain operations. Each element may be implemented as hardware, software, or any combination thereof, as desired for a given set of design parameters or performance constraints. Although an embodiment may be described with a limited number of elements in a certain topology by way of example, the embodiment may include more or less elements in alternate topologies as desired for a given implementation. It is worthy to note that any reference to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

FIG. 1is a block diagram of a system100provided in accordance to various embodiments. System100may comprise a first network interface102A and a second network interface102B coupled over communication a channel110physical medium. Communication channel110physical medium may comprise a standard cable (not separately shown) such as a Gigabit Ethernet cable, for example. Network interfaces102A, B may comprise respective physical (PHY) units104A, B and respective media access control (MAC) units106A, B. PHY units104A, B are coupled to MAC units106A, B via respective bidirectional links108A, B. Although not separately indicated in the drawing, network interfaces102A, B may comprise transceivers, hybrids, digital signal processors, and other components. In one embodiment, PHY units104A, B may comprise transceivers and hybrids, for example, and MAC units106A, B may be implemented with a digital signal processor. In one embodiment, PHY units104A, B may comprise respective receivers600A, B. Each receiver600A, B may comprise an adaptive digital interference canceller and an equalizer module, for example. Receivers600A, B may be configured such that the adaptive interference cancellers may be adapted in accordance with the various embodiments of adaptation techniques or processes described herein. For, example in one embodiment, adaptive interference canceller adaptively filters a noise reference input to maximally match and subtract out noise or interference from a primary input signal. In various embodiments, network interfaces102A, B may be part of a computer system and may be coupled to a general purpose processor to which other components such as volatile and non-volatile memory devices, mass storage, and input/output devices may be coupled.

Network interfaces102A, B may allow devices coupled thereto to communicate information over a network. In various embodiments, network interfaces102A, B may represent any network interface suitable for use with a number of different Ethernet techniques as defined by the Institute of Electrical and Electronics Engineers (IEEE) 802.3 series of standards. For example, network interfaces102A, B may comprise a structure arranged to operate in accordance with the IEEE 802.3-2005 standard. The IEEE 802.3-2005 standard defines 1000 megabits per second (Mbps) operations (1000BASE-T) using four pair twisted copper Category 5 wire, 10 Gbps operations using fiber cable, and 10 Gbps operations (10GBASE-CX4) using copper twinaxial cable (collectively referred to herein as “Gigabit Ethernet”). More particularly, network interfaces102A, B may have a structure arranged to operate in accordance with the IEEE Standard 802.3-2005 titled “IEEE Standard For Information Technology—Telecommunications and information exchange between systems—Local and metropolitan networks—Specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, Amendment: Ethernet Operation over Electrical Backplanes,” Draft Amendment P802.3ap/Draft 2.1, 2005 (“Backplane Ethernet Specification”). Network interface102A, B, however, is not necessarily limited to the techniques defined by these standards, and network interfaces102A, B may use other techniques and standards as desired for a given implementation. The embodiments are not limited in this context.

Still more particularly, network interfaces102A, B may have a structure arranged to operate in accordance with the IEEE Proposed Standard 802.3an titled “IEEE Standard For Information Technology—Telecommunications and information exchange between systems—Local and metropolitan networks—Specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications: Amendment: Physical Layer and Management Parameters for 10 Gb/s Type 10GBASE-T,” Draft Amendment P802.3an/Draft 3.1, 2005 (“10GBASE-T Specification”). Network interface102A, B, however, is not necessarily limited to the techniques defined by these standards, and network interfaces102A, B may use other techniques and standards as desired for a given implementation. The embodiments are not limited in this context.

As shown inFIG. 1, network interfaces102A, B may include respective MAC units106A, B and PHY units104A, B. In various embodiments, MAC units106A, B and/or PHY units104A, B may be arranged to operate in accordance with one of the Ethernet architectures as previously described, such as the IEEE 802.3-2005 series of standards including the 10GBASE-T and/or Backplane Ethernet Specification. AlthoughFIG. 1illustrates system100with a limited number of elements, it may be appreciated that system100may include more or less elements in different topologies and still fall within the scope of the embodiments. The embodiments are not limited in this context.

In one embodiment, for example, MAC units106A, B and/or PHY units104A, B may be arranged to operate in accordance with the 10GBASE-T and/or the Backplane Ethernet Specification, for example. Backplane Ethernet combines the IEEE 802.3 MAC and MAC Control sublayers with a family of Physical Layers defined to support operation over a modular chassis backplane. Backplane Ethernet supports the IEEE 802.3 MAC operating at 1000 Mbps and/or 10 Gbps. For 1000 Mbps operation, the family of 1000BASE-X PHY signaling systems is extended to include 10000BASE-KX. For 10 Gbps operation, two PHY signaling systems are defined. For operation over four logical lanes, the 10GBASE-X family is extended to include 10GBASE-KX4. For serial operation, the 10GBASE-R family is extended to include 10GBASE-KR (e.g., using various serializer/deserializer or “SERDES” techniques). Backplane Ethernet also specifies an Auto-Negotiation function to enable two devices that share a backplane link segment to automatically select the best mode of operation common to both devices.

It will be appreciated by those skilled in the art that 10GBASE-T is a standard proposed by the IEEE 802 committee to provide 10 Gigabit/second connections over conventional unshielded twisted pair cables. The committee currently working on the standard is IEEE 802.3an, a subgroup of IEEE 802.3. To run multi-gigabit data rates on four-pair copper cabling, however, it may be necessary to employ sophisticated digital signal processing techniques to eliminate the effects of near-end and far-end cross-talk between pairs of cable and to remove the effects of near-end and far-end signal reflections, otherwise known as echoes. Elimination of noise that is external to the cable, such as electro-magnetic interference from outside sources or adjacent cables, is difficult. Cable-to-cable noise, or alien cross-talk, for example, prevents wiring from reliably operating under worst-case 330-foot conditions. Accordingly, to support a suitable cabling system for 10GBASE-T, a new PHY, which interfaces with existing 10G MAC and Gigabit Media Independent Interface (GMII) in the IEEE model, is proposed. The PHY contains the functions to transmit, receive, and manage encoded signals that are recovered from cabling systems. The PHY may be based, for example, on pulse amplitude modulation (PAM) encoding to encode information as a stream of pulses with discrete amplitudes. This is the same modulation technique currently used in 100Base-T and 1000Base-T, but the symbol rates and digital signal processing techniques are enhanced.

With reference to the seven-layer Open System Interconnect (“OSI”) Reference Model developed by the International Standards Organization (“ISO”), MAC units106A, B implement MAC layer operations. The MAC layer is a sublayer of the data link layer. The data link layer is primarily concerned with transforming a raw transmission facility into a communication line free of undetected transmission errors for use by the network layer. The data link layer accomplishes this task by breaking input data into data frames, transmitting the data frames sequentially, and processing acknowledgement frames. The MAC sublayer provides additional functionality concerned with controlling access to broadcast networks (e.g., Ethernet). In the case of Ethernet architecture, for example, the MAC sublayer may implement a CSMA/CD protocol.

In various embodiments, MAC units106A, B are coupled to respective PHY units104A, B via respective bi-directional links108A, B to provide data paths between MAC units106A, B and respective PHY units104A, B. Bi-directional links108A, B are often referred to as a Media Independent Interface (“MII”), an xMII in the case of implementations of 100 Mbps or higher, X attachment unit interface (“XAUI”) in the case of 10 Gbps implementations, or X fiber interface (“XFI”) in the case of dual path 10 Gbps implementations. In one embodiment, for example, bi-directional links108A, B may comprise a 10 Gbps MII (XGMII) when MAC units106A, B and/or PHY units104A, B are implemented for serial operations in accordance with 10GBASE-KR as defined by the Backplane Ethernet Specification. Bi-directional links108A, B may use a 4-octet wide data path, for example, when implemented as an XGMII bi-directional link. In one embodiment, for example, bi-directional links108A, B may comprise a XAUI link where the XGMII from MAC units106A, B is extended through a XGXS sublayer (e.g., XGMII extender sublayer) which provides XGMII on both sides with XAUI used therebetween to extend it. The embodiments are not limited in this context.

In various embodiments, PHY units104A, B implement physical layer operations. The physical layer is primarily concerned with transmitting raw bits over physical medium, e.g., communication channel110physical medium, which may be some form of network. PHY units104A, B are coupled to communication channel110physical medium via respective media dependent interfaces (MDI) units114A, B, for example. Communication channel110physical medium may include various physical communications media, such as an optical fiber, a twisted pair conductor, or the like. In one embodiment, for example, communication channel110physical medium is a four pair twisted conductor, such as copper, conforming to a Category 5, 6, 7 or the like cable. In the four pair twisted conductor embodiment, PHY units104A, B converts digital data received from respective MAC units106A, B (e.g., 1000BASE-X or 10GBASE-X) into analog symbols (e.g., 1000BASE-T or 10GBASE-T) for transmission over communication channel110physical medium. For example, PHY units104A, B may encode the digital data using Manchester encoding or the like. Communication channel110physical medium may operate at any number of bandwidths, including 100 Mbps, 1 Gbps, 10 Gbps, and so forth. PHY units104A, B may be connected or coupled to communication channel110physical medium using any connectors suitable for a given type of communications media, such as an electrical connector, optical connector, and so forth. In one embodiment, for example, PHY units104A, B may be connected or coupled to communication channel110physical medium to support operation over differential, controlled impedance traces on a printed circuit board with two or more connectors and total length up to at least 1 m in accordance with the Backplane Ethernet Specification. The embodiments are not limited in this context.

In various embodiments, PHY units104A, B may further implement operations for various sublayers of the physical layer, including a physical coding sublayer (“PCS”), a physical medium attachment (“PMA”) sublayer, and a physical medium dependent (“PMD”) sublayer. In one embodiment, for example, PHY units104A, B may implement FEC operations for the various sublayers, such as used between the PMA sublayer and PCS sublayer, for example. First and second network interface units102A, B and corresponding components and channel impairments may be described in more detail with reference toFIG. 2.

FIG. 2is a block diagram200of one embodiment of system100shown inFIG. 1. Diagram200of system100illustrates channel impairments such as near-end and far-end echo and near-end crosstalk (NEXT) and far-end crosstalk (FEXT), among other forms or types of communication channel impairments. Communication in system100occurs when signals are transmitted and received between network interfaces102A, B over communication channel110physical medium. Communication channel110physical medium may be adapted for full duplex communication although it is not limited in this context. In one embodiment, communication channel110-1-nphysical media may comprise multiple cables, for example, wherein each cable may comprise, for example, copper twisted wire pairs. In one embodiment n=4 and communication channel110physical medium may comprise four twisted wire pairs110-1-4, for example. In one embodiment, for each parallel communication channel110-1-nphysical medium network interfaces102A,102B may comprise, for example, corresponding PHY units104A-1-n,104B-1-ncoupled to respective MAC units106A-1-n,106B-1-n, over respective bidirectional links108A-1-n,108B-1-n, for example. PHY units104A-1-n,104B-1-nmay comprise transceivers202A-1-n,202B-1-n. Transceivers202A-1-n,202B-1-neach may comprise respective transmitters (T)204A-1-n,204B-1-nand receivers (R)600A-1-n,600B-1-n, which may be coupled to respective communication channels110-1-nphysical media via respective hybrid units212A-1-n,212B-1-n. Concurrent full duplex transmission on all communication channels110-1-nphysical media, however, may lead to channel impairments such as, for example, signal attenuation, echo, crosstalk, among other impairments due to the characteristics of the physical medium.

Although communication across communication channel110-1-nphysical media may be concurrent full duplex, in the following illustrative examples of channel impairments, assume that transmitter204A-1is transmitting information through communication channel110-1physical medium to receiver600B-1and transmitter204A-2is transmitting information through communication channel110-2physical medium to receiver600B-2. Accordingly, in the example illustrated inFIG. 2, echo is a reflection of a transmitted signal back to transmitter204A-1due to impedance mismatch in various points of communication channel110-1physical medium, hybrid units212A-1,212B-1, and MDI units114A-1,114B-1. Echo may manifest itself as a near-end echo interference signal208and a far end echo interference signal210, for example. In the illustrated embodiment, near-end212refers to transmitter204A-1side and far-end214refers to receivers600B-1,600B-2side. The terms near-end212and far-end214are used herein merely to describe a signal from the reference point of a corresponding transmitter and the path of the transmitted signal. Each path of near- and far-end echo interference signals208,210may be considered an echo-channel. Crosstalk is an unwanted signal caused by the interference between adjacent wire pairs in communication channel110-1-nphysical media. In one embodiment, for example, four wire pairs may be used as communication channel110-1-4physical media and any adjacent wire pairs in communication channel100-1-4physical media may be affected by crosstalk, for example. Crosstalk may be characterized as NEXT interference signal216or FEXT interference signal218. NEXT interference signal216is crosstalk that appears at the input of a wire pair at near-end212, e.g., at receiver600A-1input, from transmitter204A-2at near-end212of communication channel110-2physical medium. FEXT interference signal218is crosstalk that appears at the input of a wire pair at near-end212, at receiver600A-1input, from far-end214of communication channel100-2physical medium. Near-end and far-end crosstalk and echo interference signals may be removed by employing techniques described and illustrated herein. For example, near-end and far-end crosstalk and echo interference signals may be removed or substantially eliminated by employing an adaptive interference canceller to adaptively filter the noise reference input to maximally match and subtract out noise or interference from a primary input signal (e.g., desired signal plus noise).

In various embodiments, a signal may be passed between network interfaces102A, B in system100through communication channel110physical medium. Communication channel110physical medium, however, may introduce interference signals such as, for example, ISI and an additional interference signal. The additional interference signal may comprise near-end echo interference signal208, far-end echo interference signal210, NEXT interference signal216, FEXT interference signal218, among other unwanted interference signals that may impair communications in communication channel110physical medium. Near-end echo interference signal208may be defined as an interference signal transmitted by a near-end212device such as transmitter204A-1, which has passed through an echo channel, for example. Although not shown in the illustrated embodiments, receivers600A, B may comprise analog-to-digital (A/D) converters. Accordingly, any clock jitter of the sampling clock at the A/D converter introduced by communication channel110physical medium, or otherwise, may result in a time-variant interference channel. An adaptive interference canceller module may be employed to eliminate or substantially suppress the time-variant interference channel, for example. The various embodiments illustrated and described herein, provide an adaptive interference canceller module as part of receivers600A, B, for example, to adaptively filter the noise reference input to maximally match and subtract out noise or interference from a primary input signal (e.g., desired signal plus noise). Adaptation may be implemented using any of the well-known methods (e.g., LMS, RLS, Fast RLS). Therefore, implementation details of such LMS, RLS, and/or fast RLS adaptation processes or algorithms are not described herein.

To meet increasingly stringent communication system performance requirements, it may be necessary to perform equalization in order to reduce the ISI. In addition, an interference canceller module may be employed to cancel or substantially suppress the interference described above (e.g., an echo canceller, among others).

The following embodiments are described with reference to near-end212network interface102A and receiver600A-1, although the principles may be applied to any of the receivers600A-1-n,600B-1nin system100. Accordingly, when receiver600A-1is first “switched on,” it may be in an initial condition where the equalizers employed to reduce ISI have not yet converged. At this pre-convergence stage, it may be necessary to observe the input to the equalizers in order to cancel near- or far-end echo interference signals208,210in addition to NEXT or FEXT interference signals216,218, among other potential interference signals using an interference canceller module, e.g., a first echo canceller. After the equalizer has converged, the performance of receiver600A-1may be enhanced by turning on an additional interference canceller, e.g., a second echo canceller, that operates at a significantly higher SNR placed at the output of the equalizer (e.g., at the output of a slicer). Such a system may converge, in a combination before and after equalizer interference canceller configuration, with enhanced performance using a single interference cancellation mechanism and an adaptation selection logical switch module. The adaptation logical switch module switches between multiple adaptation processes, techniques, or mechanisms. The adaptation logical switch module provides a smooth transition and seamless reuse of receiver600A-1hardware. Such smooth transition and seamless reuse of receiver600A-1hardware may result in power saving. Throughout this description, an interference canceller module may refer to any interference canceller modules such as, for example, near-end echo or far-end canceller module, a NEXT interference, and/or FEXT canceller module, a FEXT interference canceller module, among others, to cancel near-end and far-end echo interference signals208,210, NEXT interference signals216, and/or FEXT interference signals218. Nevertheless, the embodiments of interference canceller module described and illustrated herein are not limited to an echo or crosstalk interference canceller and may be employed in a variety of interference signal canceling techniques and/or implementation to cancel additional interference signals that may arise in system100, for example.

In interference signal cancellation implementation techniques, there generally is a trade-off between the ability of a system to converge and to suppress interference signals. These tradeoffs are evident, for example, in conventional ISI cancellation schemes where an echo canceller is located either before or after the equalizer. Various embodiments described herein provide techniques to eliminate or substantially, reduce or minimize this trade-off, by achieving both attributes. For example, the various embodiments provide techniques to exploit the benefits of placing the interference canceller module either before or after the equalizer without the detriments of either implementation scheme alone. For example, the various embodiments provide the benefit of both—fast and robust convergence of the various components of the receiver system600A-1(including timing recovery algorithms, equalizers, and interference cancellers) on one hand, and high interference signal suppression on the other, while enabling better system performance from all aspects.

FIG. 3is a diagram of a conventional receiver300. Receiver300comprises a digital echo canceller302and an equalizer304. In the implementation illustrated inFIG. 3, echo canceller302is located before equalizer304. The term “before” is used to indicate that an interference signal318, such as an echo interference signal or crosstalk interference signal, passing through an interference channel (e.g., echo channel) at input311of equalizer304is processed by echo canceller302in time before it is processed by equalizer304. Receiver300comprises a line interface308by which receiver300is coupled to communication channel110physical medium and receives receiver input signal310.

Receiver300also comprises a summer312. Summer312comprises a first input coupled to line interface308and a second input coupled to echo canceller302to receive respective receiver input signal310from line interface308and adaptive signal314provided by echo canceller302as input signals. Summer312is coupled to equalizer304. Summer312operates to sum its input signals, receiver input signal310and adaptive signal314, to produce an output signal316(e.g., equalizer input signal316) as input to equalizer304.

Echo canceller302is coupled to a second input of summer312. Output of summer312also is coupled to echo canceller302. Output of summer312provides equalizer input signal316to echo canceller302as feedback. Echo canceller302also receives echo interference signal318. Adaptation of echo canceller302is performed using echo interference signal318and equalizer input signal316. Echo canceller302cancels echo interference signal318.

Equalizer304is coupled to the output of summer312. Equalizer304may be implemented as a high-pass filter (HPF). Equalizer304may be a finite impulse response (FIR) filter implemented as an adaptive feed forward equalizer (FFE) to receive the equalizer input signal316. Equalizer304may operate in accordance with conventional principles and in combination with other components may operate to equalize equalizer input signal316to reduce or substantially eliminate ISI. Adaptive FFE, for example, may adapt equalizer304characteristics it applies to equalizer input signals316on the basis of echo interference signal318.

Receiver300also comprises a slicer320. Slicer320is coupled to the output of equalizer304. Slicer320may operate in accordance with conventional principles to produce a decision symbol322and a slicer error signal324, as output signals. Decision symbol322may reflect a filtered and/or equalized version of equalizer input signal316and may contain the data to be recovered from receiver input signal310. Slicer error signal324may be an error signal that indicates a deviation of equalizer input signal316from a pre-determined ideal signal profile of received input signal310. Decision symbol322and slicer error signal324may be provided to MAC unit106for further processing.

Although not shown, receiver300also may comprise receiver analog front end electronics coupled to line interface308to receive receiver input signal310via communication channel110physical medium. The receiver analog front end electronics may perform signal conditioning on receiver input signal310in accordance with conventional practices. Receiver300may further comprise an A/D converter coupled to the receiver analog front end electronics to receive the incoming signals. The A/D converter converts incoming signals into a stream of digital samples. Receiver300also may comprise an automatic gain control (AGC) circuit (or block) which is coupled to the A/D converter to receive the stream of digital samples output by the A/D converter. The AGC circuit may operate in accordance with conventional principles and, as a part of its conventional operation, may determine a physical characteristic of communication channel110physical medium such as cable length, for example. Further, equalizer304may be considered to be coupled to line interface308via receiver300analog front end electronics and the A/D converter, for example.

Echo canceller302is located before equalizer304. This configuration provides advantages in that the overall echo channel required to be cancelled at the input of equalizer304does not include equalizer304. As previously discussed equalizer304may be implemented as a HPF to equalize a communication channel110physical medium, which is a low-pass filter (LPF) in nature. This is described below with respect toFIG. 4. Accordingly, locating echo canceller before equalizer304creates an echo channel that is substantially insensitive to clock jitter and to high slopes in the echo channel.

In receiver300, adaptation module326with echo canceller302located before equalizer304uses interference signal318and equalizer input signal316to perform the adaptation of echo canceller302. Equalizer input signal316as an input to adaptation module326, which is also the input signal to equalizer304. Equalizer input signal316is at a very low SNR because it includes a far-end echo signal (e.g., far-end echo signal210), its ISI, and additional interferences (e.g., NEXT, FEXT, among other interference signals), in addition to echo interference signal318it is required to cancel. Accordingly, the echo suppression and/or cancellation capabilities of receiver300utilizing adaptation module326are usually limited.

FIG. 4is a graphical representation of one example of a desired equalizer304response400shape. Equalizer304tap number is indicated along the horizontal axis and amplitude is indicated along the vertical axis. Response400is a typical HPF response curve402of a FFE implemented equalizer304.

FIG. 5is a diagram of a conventional receiver500. Receiver500comprises digital echo canceller302and equalizer304. In the implementation illustrated inFIG. 5, echo canceller302is located after equalizer304. The term “after” is used to indicate that interference signal such as echo interference signal318passing through an echo channel is processed by echo canceller302in time after it is processed by equalizer304.

As shown inFIG. 5, equalizer304is coupled to line interface308and to summer312. Equalizer304receives receiver input signal310from line interface308as a first input. Equalizer304, in accordance with conventional principles, equalizes receiver input signal310to reduce or substantially eliminate ISI and produces an output signal502(e.g., slicer input signal502). Equalizer304is coupled to the first input of summer312and provides adaptive echo interference signal504to the first input of summer312.

Echo canceller302is coupled to the second input of summer312and provides adaptive echo interference signal504to the second input of summer312. Summer312operates to sum its input signals, output signal502from equalizer304and adaptive echo interference signal504, to produce slicer input signal506to slicer320. Slicer320may operate in accordance with conventional principles to produce a decision symbol508and a slicer error signal510, as output signals. Slicer error signal510is provided as feedback to echo canceller302such that the adaptation of echo canceller302may be performed using echo interference signal318and slicer error signal510. Echo canceller302cancels echo interference signal318interference.

In receiver500, adaptation of echo canceller302located after equalizer304utilizes adaptation module512, which provides certain advantages and disadvantages. Conventional methods of adaptation of echo canceller302located after equalizer304, as in receiver500, for example, uses slicer error signal510after it has been processed by equalizer304and slicer320. Processing slicer input signal506through slicer320removes the far-end signal interference after the ISI is removed, and results in a slicer error signal510, which is composed mainly of the interference signals. To echo canceller302slicer error signal510looks like a signal with a high SNR for because it does not include the far-end signal interference, which is removed by slicer320, and is comprised mainly of echo interference signal318. Echo interference signal318may be considered to be a time-invariant signal.

Accordingly, the echo suppression and/or cancellation capabilities of echo canceller302utilizing adaptation module512are usually superior to configurations where, as in receiver500, echo canceller302is located before equalizer304, as illustrated and described with respect to receiver300inFIG. 3. Nevertheless, there are implementation limitations associated with the time-invariant echo channel.

For example, in the implementation of echo suppression employed in receiver500, the overall echo channel required to be cancelled also includes equalizer304. Equalizer304is usually a HPF because it equalizes a physical channel, e.g., communication channel110physical medium, which is a low-pass filter in nature. Therefore, echo channel adaptation with echo canceller302located after equalizer304may be very sensitive to jitter and to high slopes in the echo channel.

Accordingly, in receiver500, the echo suppression and/or cancellation capabilities echo canceller302located after equalizer304and processed in accordance with adaptation module512may be limited by the ability to track the changes in the echo channel, which may be amplified by the HPF in equalizer304.

FIG. 6is a diagram of one embodiment of receiver600. Receiver600may be used in system100. For example, receiver600may be representative of receivers600A-1-n,600B-1-n, that may be used in respective PHY units104A-1-n,104B-1-ncomprising transceivers202A-1-n,202B-1-n. Transceivers202A-1-n,202B-1-neach may comprise respective transmitters (T)204A-1-n,204B-1-nand receivers (R)600A-1-n,600B-1-n, which may be coupled to respective communication channels110-1-nvia respective hybrid units212A-1-n,212B-1-n. In one embodiment, receivers (R)600A-1-n,600B-1-nmay be implemented in accordance with the techniques described with reference toFIG. 6and receiver600. Receiver600comprises interference canceller610and equalizer304. In one embodiment, interference canceller610may be a digital interference canceller, for example. In the illustrated embodiment, interference canceller610is located before equalizer304. Receiver600comprises line interface308by which receiver600is coupled to communication channel110physical medium. Receiver600receives receiver input signal310from communication channel110physical medium via line interface308.

Receiver600comprises summer312. Summer312comprises a first input coupled to line interface308and a second input coupled to interference canceller610to receive respective receiver input signal310from line interface308and adaptive signal602from interference canceller610as input signals. Summer312is coupled to equalizer304via input311. Summer312operates to sum its input signals, receiver input signal310and adaptive signal602, to produce output signal604(e.g., equalizer input signal604) as input to equalizer304.

Interference canceller610is coupled to a second input of summer312. Output of summer312also is coupled to interference canceller610to provide equalizer input signal604to interference canceller610as feedback. Interference canceller610also receives interference signal618. In one embodiment, interference signal618may be a near-end or far-echo interference signal, a NEXT or FEXT interference signal, among other types of interference signals.

Equalizer304is coupled to the output of summer312. Equalizer304may be implemented as a HPF. Equalizer304may be a FIR equalizer implemented as an adaptive FFE to receive equalizer input signal604. Equalizer304contains multiple equalizer coefficients. It will be appreciated, however, that the embodiments may be expanded to other forms or types of equalizers. Equalizer304may operate in accordance with conventional principles and in combination with other components to equalize equalizer input signal604utilizing equalizer coefficients to reduce or substantially eliminate ISI. Adaptive FFE, for example, may adapt equalizer304characteristics to equalizer input signals604on the basis of interference signal618.

Receiver300also comprises slicer320. Slicer320is coupled to the output of equalizer304. Slicer320may operate in accordance with conventional principles to produce a decision symbol606and a slicer error signal608, as output signals. Decision symbol606may reflect a filtered and/or equalized version of equalizer input signal604and may contain the data to be recovered from receiver input signal310. Slicer error signal608may be an error signal that indicates a deviation of equalizer input signal604from a pre-determined ideal signal profile of receiver input signal310. Decision symbol606and slicer error signal608may be provided to MAC unit106, for example. Slicer error signal608also may be provided to interference canceller610. Adaptation of interference canceller610is performed using adaptation module612using interference signal618, the equalizer coefficients, and slicer error signal608. In one embodiment, adaptation module612utilizes the convolution of interference signal618with the equalizer coefficients and multiplies the result by slicer error signal608to perform the adaptation of interference canceller610. In addition, based on the convergence status of equalizer304, adaptation of interference canceller610may be performed using interference signal618multiplied by equalizer input signal604. Interference canceller610cancels interference signal618. In one embodiment, adaptation module612provides a sufficiently high SNR at slicer320when equalizer304(e.g., FFE) has substantially converged.

In the adaptation techniques and echo canceller302/equalizer304configurations described with reference to receivers300,500, placing echo interference canceller302before or after equalizer304results in a performance margin budget that is utilized by echo interference canceller302performance. Because conventional receivers300,500traditionally have a relatively large performance margin taking up part of this budget was customary and did not impact performance significantly.

In 10GBASE-T systems (e.g., system100), however, performance requirements are much higher. Therefore, system100margin is much smaller. Accordingly, it may be necessary for each component in system100to have far superior capabilities than in conventional solutions. In this manner, as little as possible of system100performance budget can be utilized in order to meet the more stringent requirements. For example, in one embodiment, the echo cancellation requirements may be approximately 60 dB of echo suppression, compared to approximately 40 dB in conventional systems.

Accordingly, receiver600may be implemented to converge using a first adaptation process initially when slicer320has a low SNR output and then switch to a second adaptation process when the SNR at slicer320output is sufficiently high such that equalizer304converges to a high-performing system. In one embodiment, this may be achieved with maximal reuse of hardware (interference cancellers610) and seamless continuity. The adaptation technique illustrated with reference to receiver600is based on a “smart” adaptation process employing a logical adaptation selection module described below. Although, the embodiments are described as switching or selecting between two adaptation processes, the principles can be extended to a multiple adaptation processes. The embodiments are not limited in this context.

The advantage of having enhanced performance interference cancellation (e.g., near or far end echo, NEXT, FEXT, and other impairment cancellation) in receiver600is a much improved echo suppression capability. In addition, interference signal618cancellation in receiver600provides enhanced overall performance of system100and a much higher operating SNR margin without incurring the penalty of additional hardware. The additional performance margin results in lower power consumption for receiver600, and therefore, for communication system100. As is well known, power is a factor in communication system100including, for example, 10GBASE-T communication systems.

FIG. 7is a diagram700that illustrates one embodiment of the adaptation process of interference canceller610and one embodiment of the convergence method of equalizer304in receiver600.FIG. 7is a block diagram700of receiver600including a first logical block representing adaptation module702and a second logical block representing adaptation module704. As previously discussed, this principle may be extended to multiple adaptation processes, for example. Diagram700logically illustrates the implementation of the selection of respective adaptation modules702,704of interference canceller610based on information from slicer320. For example, in one embodiment, adaptation selection module706may be employed to monitor information708associated with slicer320. In one embodiment, the criteria for switching between adaptation modules702,704may be defined in terms of a threshold, for example. In one embodiment, a criterion for switching between adaptation modules702,704may be a threshold associated with slicer320. For example, in one embodiment, the threshold may be a slicer320output SNR indicating a convergence status of equalizer304. For example, a threshold for switching may be when slicer320SNR indicates that equalizer304has sufficiently converged. Accordingly, in one embodiment, information from slicer320, such as for example, slicer320SNR, may be used to select one of two adaptation modules702,704. In one embodiment, adaptation of interference canceller610may initially begin with adaptation module702when slicer320SNR is low and then, adaptation selection module706may switch to adaptation module704when slicer320SNR reaches or crosses a predetermined SNR threshold. In one embodiment, adaptation module702performs adaptation of interference canceller610using, for example, interference signal618multiplied by equalizer input signal604. Adaptation module704performs adaptation of interference canceller610using, for example, the convolution of interference signal618and the equalizer coefficients, and multiplying the results by slicer error signal608. In one embodiment, adaptation module704performs the adaptation at a higher SNR relative to adaptation module702, after equalizer304convergence. Further, the adaptation transition from adaptation module702to adaptation module704is seamless in the sense that the interference canceller610coefficients remain the same in both adaptations, but are adapted via adaptation module704at a higher SNR relative to adaptation module702.

Although not shown, receiver700also may comprise receiver analog front end electronics coupled to line interface308to receive receiver input signal310via communication channel110physical medium. Receiver700analog front end electronics may perform signal conditioning on receiver input signal310in accordance with conventional practices. Receiver700may further comprise an A/D converter coupled to the receiver analog front end electronics to receive the incoming signals. The A/D converter converts incoming signals into a stream of digital samples. Receiver700also may comprise an AGC circuit (or block) which is coupled to the A/D converter to receive the stream of digital samples output by the A/D converter. The AGC circuit may operate in accordance with conventional principles and, as a part of its conventional operation. Further, equalizer304may be considered to be coupled to line interface308via receiver700analog front end electronics and the A/D converter, for example.

One embodiment of a method for enhanced performance of pre-equalizer adaptive cancellers using smart adaptation may be employed in system100and receivers600,700. The adaptation of interference canceller610may be performed in accordance with the following mathematical description the adaptation processes. One embodiment of the adaptation process may be described for a FIR equalizer304, implemented as a FFE equalizer304. The embodiments, however, can be extended to equalizers in other forms. In addition, the adaptation method according to various embodiments may be implemented with an LMS, RLS, fast RLS, or other similar adaptation algorithms. Various embodiments of the overall interference cancellation techniques may be employed in a similar manner for any equalizer form and adaptation algorithm.

The following variables define the characteristics of the various components described in receivers in the various embodiments. Accordingly:

hFFEdenotes the impulse response of FFE equalizer304.

hECdenotes the impulse response of interference canceller610.

The term “echo” denotes interference signal618fed into interference canceller610.

The term “error” denotes slicer error signal608of slicer320.

The convolution operation may be denoted by *.

The multiplication operation be denoted by ·

The result of passing the echo (e.g., interference signal618) through interference canceller610and FFE equalizer304is:
echo*hEC*hFFE(1)

Equation (1) may be interpreted in the following manner and may be used to describe adaptation module702:
(echo*hEC*hFFE)=(echo*hEC)*hFFE(2)

In operation, interference canceller610attempts to cancel the echo channel present at the input311of equalizer304(similar to hEC). The result is filtered through FFE equalizer304. To adapt the impulse response of interference canceller610, hEC, the conventional approach using, for example, the LMS algorithm is to adapt hECusing the echo (e.g., interference signal618) and echo channel at the input311of equalizer304. Equation (2) may be employed when interference canceller610is located before FFE equalizer304.

Equation (1), and therefore, adaptation module702may be interpreted in the alternative manner as follows:
(echo*hEC*hFFE)=echo*(hECbefore*hFFE)  (3)

Accordingly, interference canceller610is attempting to cancel the echo channel present at the output of equalizer304. Equation (3) is similar to:
hECafter=hECbefore*hFFE(4)

To adapt hECafterusing adaptation module702using the LMS algorithm, hECaftermay be adapted using echo618and slicer error608. This is for the technique of placing interference canceller610after FFE equalizer304.

In one embodiment, with hEC(e.g., interference canceller610) placed before equalizer304:
(echo*hEC*hFFE)=(echo*hFFE)*hEC(5)

Interference canceller610is attempting to cancel the echo channel604present at input311of equalizer304(e.g., similar to hEC), then the result is filtered through the FFE equalizer304. In order to adapt the impulse response of interference canceller610, hEC, embodiments of adaptation module704for enhanced performance of pre-equalizer adaptive cancellers using adaptation selection module706utilizes the convolution of interference signal618and equalizer input signal604represented by echo*hEC, and slicer error608to adapt the LMS algorithm.

It should be noted that the various embodiments of the adaptation and filtration processes described above can be performed either in time or frequency domain, or in common time-frequency domain. The adaptation mechanism that can be used here is not restricted to being only LMS, but may be based on other learning algorithms like RLS, among others.

Operations for the above embodiments may be further described with reference to the following figures and accompanying examples. Some of the figures may include a logic flow. Although such figures presented herein may include a particular logic flow, it can be appreciated that the logic flow merely provides an example of how the general functionality as described herein can be implemented. Further, the given logic flow does not necessarily have to be executed in the order presented unless otherwise indicated. In addition, the given logic flow may be implemented by a hardware element, a software element executed by a processor, or any combination thereof. The embodiments are not limited in this context.

FIG. 8illustrates one embodiment of a logic flow.FIG. 8illustrates a logic flow800. Logic flow800may be representative of the operations executed by one or more embodiments described herein. As shown in logic flow800, interference canceller610receives (802) interference signal618, error signal608, and equalizer input signal604. Adaptation module702adapts (804) interference canceller610utilizing interference signal618and equalizer input signal604. For example, by multiplying interference signal618and equalizer input signal604. Adaptation module704adapts (806) interference canceller610utilizing the convolution of interference signal618with the equalizer coefficients, and multiplying the result by the slicer error. In addition, the adaptation transition from adaptation module702to adaptation module704is seamless in the sense that the interference canceller610coefficients remain the same in both adaptations, but are adapted via adaptation module704at a higher SNR relative to adaptation module702.

Adaptation selection module706receives information associated with a convergence of equalizer304and selects either a first adaptation module702or a second adaptation module704to adapt interference canceller610. Adapting interference canceller610utilizes interference signal618and equalizer input signal604. Adaptation selection module706receives a signal-to-noise ratio (SNR) signal from slicer320. The SNR indicates a convergence status of equalizer304. Summer312sums input signal310and interference canceller output602and produces equalizer input signal604.

Operations for the above embodiments may be further described with reference to the following figures and accompanying examples. Some of the figures may include a logic flow. Although such figures presented herein may include a particular logic flow, it can be appreciated that the logic flow merely provides an example of how the general functionality as described herein can be implemented. Further, the given logic flow does not necessarily have to be executed in the order presented unless otherwise indicated. In addition, the given logic flow may be implemented by a hardware element, a software element executed by a processor, or any combination thereof. The embodiments are not limited in this context.

In various implementations, system100or apparatus600,700may be illustrated and described as comprising several separate functional elements, such as modules and/or blocks. Although certain modules and/or blocks may be described by way of example, it can be appreciated that a greater or lesser number of modules and/or blocks may be used and still fall within the scope of the embodiments. Further, although various embodiments may be described in terms of modules and/or blocks to facilitate description, such modules and/or blocks may be implemented by one or more hardware components (e.g., processors, DSPs, PLDs, FPGAs, ASICs, circuits, registers), software components (e.g., programs, subroutines, logic) and/or combination thereof.

In various embodiments, system100or apparatus600,700may comprise multiple modules connected by one or more communications media. Communications media generally may comprise any medium capable of carrying information signals. For example, communications media may comprise wired communications media, wireless communications media, or a combination of both, as desired for a given implementation. Examples of wired communications media may include a wire, cable, PCB, backplane, semiconductor material, twisted-pair wire, co-axial cable, fiber optics, and so forth. An example of a wireless communications media may include portions of a wireless spectrum, such as the radio-frequency (RF) spectrum. The embodiments are not limited in this context.

The modules may comprise, or be implemented as, one or more systems, sub-systems, devices, components, circuits, logic, programs, or any combination thereof, as desired for a given set of design or performance constraints. For example, the modules may comprise electronic elements fabricated on a substrate. In various implementations, the electronic elements may be fabricated using silicon-based IC processes such as complementary metal oxide semiconductor (CMOS), bipolar, and bipolar CMOS (BiCMOS) processes, for example. The embodiments are not limited in this context.