EMBEDDED PACKAGE STRUCTURE AND PREPARATION METHOD THEREFOR, AND TERMINAL

An embedded package structure, a preparation method therefor and a terminal are described. The embedded package structure includes a first dielectric layer. The first dielectric layer includes a first surface and a second surface. The embedded package structure includes a first device embedded in the first dielectric layer. A thermal conductive layer is attached to a surface of the first device that is exposed on the first surface of the first dielectric layer. A first circuit layer is connected to a surface of the first device that is exposed on the second surface. A second dielectric layer and a third dielectric layer are symmetrically disposed on two sides of the first dielectric layer.

TECHNICAL FIELD

This application relates to the field of communications technologies, and in particular, to an embedded package structure and a preparation method therefor, and a terminal.

BACKGROUND

With development of terminal mobile phone products, architectures and functions constantly increase. A growing quantity of functions are integrated into a mainboard of a mobile phone. However, due to a limitation of an appearance size of the mobile phone, internal space of the mobile phone is limited. Therefore, an embedded package technology for integrating devices from a surface of a substrate to the inside of the substrate has prominent advantages in miniaturization and high performance, and has become an application hotspot of the package technology. As shown inFIG. 1, in an embedded package substrate in a conventional technology, a substrate1is trenched and then a die2is embedded. However, a back surface of the die2is wrapped by resin, affecting heat dissipation of the die2. In addition, when a window opened in an insulation layer of the die2and a distance between pads are relatively small, there is no enough space to lead out metal wires interconnecting the die2and other devices of a terminal mobile phone to which the die2is applied, affecting embedment of the high-density die2with a plurality of pins. The die2is completely embedded into an organic dielectric layer of the substrate1. Because thermal conductivity of a dielectric resin material is relatively low, heat consumption of the die2cannot be effectively dissipated. In addition, an asymmetric structure of the embedded substrate1causes problems in manufacturing and applying the embedded substrate1.

SUMMARY

The application provides an embedded package structure and a preparation method therefor, and a terminal, to improve heat dissipation of a chip and alleviate warpage of a substrate.

In at least one embodiment, an embedded package structure is provided. The embedded package structure includes: a first dielectric layer, where the first dielectric layer includes a first surface and a second surface that are disposed opposite to each other; further includes a first device embedded in the first dielectric layer, where a difference between a thickness of the first device and a thickness of the first dielectric layer is within a predetermined range; a thermal conductive layer, disposed on the first surface, where the thermal conductive layer is in contact with the first device; and further includes a first circuit layer, disposed on the second surface of the first dielectric layer, where the first circuit layer is electrically connected to the first device. An expansion coefficient of the thermal conductive layer is the same as that of the first circuit layer. The substrate further includes a second dielectric layer, covering the thermal conductive layer, where at least one thermal hole connected to the thermal conductive layer is provided in the second dielectric layer; and further includes a third dielectric layer, covering the first circuit layer, where a first via connected to the first circuit layer is provided in the third dielectric layer. Moreover, an expansion coefficient of the second dielectric layer is the same as that of the third dielectric layer. It can be learned from the foregoing description that structures of the thermal conductive layer and the first circuit layer that are prepared by using materials with the same expansion coefficient, and the second dielectric layer and the third dielectric layer that are prepared by using materials with the same expansion coefficient are respectively disposed on two opposite sides of the first dielectric layer, so that the entire embedded package structure forms a quasi-symmetrical structure. When the substrate is deformed by heat, an expansion status of the thermal conductive layer is approximate to that of the first circuit layer, and an expansion status of the second dielectric layer is approximate to that of the third dielectric layer, so that warpage of the embedded package structure is alleviated. Moreover, the disposed thermal conductive layer and first circuit layer facilitate heat dissipation of the first device.

In an embodiment, the first dielectric layer is prepared by using resin doped with no glass fiber, and the second dielectric layer and the third dielectric layer are prepared by using resin doped with glass fiber. Air bubbles generated when the first dielectric layer wraps the first device are reduced.

In an embodiment, the thickness of the first device is equal to that of the first dielectric layer. In this way, two sides of the first device can be in direct contact with the thermal conductive layer and the first circuit layer. In the application, thicknesses being equal means that if a tolerance between two thicknesses is within a range of ±20 microns, the two thicknesses are considered as the same thickness.

In an embodiment, a thickness of the second dielectric layer is equal to that of the third dielectric layer, a second circuit layer is disposed on a surface of the third dielectric layer facing away from the first dielectric layer, and the second circuit layer is electrically connected to the first circuit layer through the first via. The second circuit layer is electrically connected to the first circuit layer through the first via. A third circuit layer is disposed on a surface of the second dielectric layer facing away from the first dielectric layer, and the third circuit layer is electrically connected to the first circuit layer. An expansion coefficient of the second circuit layer is the same as that of the third circuit layer. Warpage of the substrate is alleviated by using the second circuit layer and the third circuit layer that have the same expansion coefficient.

In an embodiment, the first device is a die, and the thermal conductive layer is in direct contact with the die. The die is used, so that the thermal conductive layer can be in direct contact with the die, and a heat dissipation effect is improved compared with that of a packaged chip in a conventional technology.

In an embodiment, an area in which the thermal conductive layer covers the first surface is greater than an area of a surface that is of the first device and that is exposed on the first device, thereby further improving the heat dissipation effect.

In an embodiment, the predetermined range is 0 microns to 50 microns. In an embodiment, the predetermined range may include different thicknesses such as 0 microns, 10 microns, 20 microns, 30 microns, 40 microns, and 50 microns.

In an embodiment, at least one through hole is provided in the first dielectric layer, a conductive pillar is fixed in each through hole, and a second via in one-to-one correspondence with the conductive pillar is provided in the second dielectric layer; a third via in communication with the conductive pillar is provided in the third dielectric layer; and the third circuit layer is connected to the second circuit layer by using the electrically connected second via, conductive pillar, and third via. A conductive connection between circuits is implemented.

In an embodiment, the embedded package structure further includes a second device disposed at the second dielectric layer and a fourth dielectric layer used for embedding the second device, where the second device is electrically connected to the first circuit layer.

In an embodiment, the second device is electrically connected to the third circuit layer by using a metal jumper wire and/or a solder ball, and the third circuit layer is electrically connected to the first circuit layer.

In at least one embodiment, a terminal is provided. The terminal includes a housing and a mainboard disposed in the housing, and further includes an embedded package structure disposed on the mainboard. The embedded package structure includes a first dielectric layer, where the first dielectric layer includes a first surface and a second surface that are disposed opposite to each other; a first device embedded in the first dielectric layer, where a difference between a thickness of the first device and a thickness of the first dielectric layer is within a predetermined range; a thermal conductive layer, disposed on the first surface, where the thermal conductive layer is in contact with the first device; a first circuit layer, disposed on the second surface of the first dielectric layer, where the first circuit layer is electrically connected to the first device; a second dielectric layer, covering the thermal conductive layer, where at least one thermal hole connected to the thermal conductive layer is provided in the second dielectric layer; and a third dielectric layer, covering the first circuit layer, where a first via connected to the first circuit layer is provided in the third dielectric layer. It can be learned from the foregoing description that structures of the thermal conductive layer and the first circuit layer that are prepared by using materials with the same expansion coefficient, and the second dielectric layer and the third dielectric layer that are prepared by using materials with the same expansion coefficient are respectively disposed on two opposite sides of the first dielectric layer, so that the entire embedded package structure forms a quasi-symmetrical structure. When a substrate is deformed by heat, an expansion status of the thermal conductive layer is approximate to that of the first circuit layer, and an expansion status of the second dielectric layer is approximate to that of the third dielectric layer, so that warpage of the embedded package structure is alleviated. Moreover, the disposed thermal conductive layer and first circuit layer facilitate heat dissipation of the first device.

In an embodiment, the first dielectric layer is prepared by using resin doped with no glass fiber, and the second dielectric layer and the third dielectric layer are prepared by using resin doped with glass fiber. Air bubbles generated when the first dielectric layer wraps the first device are reduced.

In an embodiment, the thickness of the first device is equal to that of the first dielectric layer. In this way, two sides of the first device can be in direct contact with the thermal conductive layer and the first circuit layer.

In an embodiment, a thickness of the second dielectric layer is equal to that of the third dielectric layer, a second circuit layer is disposed on a surface of the third dielectric layer facing away from the first dielectric layer, and the second circuit layer is electrically connected to the first circuit layer through the first via. The second circuit layer is electrically connected to the first circuit layer through the first via. A third circuit layer is disposed on a surface of the second dielectric layer facing away from the first dielectric layer, and the third circuit layer is electrically connected to the first circuit layer. An expansion coefficient of the second circuit layer is the same as that of the third circuit layer. Warpage of the substrate is alleviated by using the second circuit layer and the third circuit layer that have the same expansion coefficient.

In an embodiment, the first device is a die, and the thermal conductive layer is in direct contact with the die. The die is used, so that the thermal conductive layer can be in direct contact with the die, and a heat dissipation effect is improved compared with that of a packaged chip in a conventional technology.

In an embodiment, an area in which the thermal conductive layer covers the first surface is greater than an area of a surface of the first device, thereby further improving the heat dissipation effect.

In an embodiment, at least one through hole is provided in the first dielectric layer, a conductive pillar is fixed in each through hole, and a second via in one-to-one correspondence with the conductive pillar is provided in the second dielectric layer; a third via in communication with the conductive pillar is provided in the third dielectric layer; and the third circuit layer is connected to the second circuit layer by using the electrically connected second via, conductive pillar, and third via. A conductive connection between circuits is implemented.

In an embodiment, the embedded package structure further includes a second device disposed at the second dielectric layer, where the second device is electrically connected to the first circuit layer.

In an embodiment, the second device is electrically connected to the third circuit layer by using a metal jumper wire and/or a solder ball, and the third circuit layer is electrically connected to the first circuit layer.

In an embodiment, the embedded package structure further includes a fourth dielectric layer used for embedding the second device, to improve safety of the second device.

In at least one embodiment, a method for preparing an embedded package structure is provided. The method includes the following operations: preparing a first dielectric layer around a first device, the first device being embedded in the prepared first dielectric layer, two opposite surfaces of the first device being respectively exposed on a first surface and a second surface that are opposite to each other of the first dielectric layer, and a difference between a thickness of the first device and a thickness of the first dielectric layer being within a predetermined range; attaching a thermal conductive layer to the first surface, where the thermal conductive layer is in contact with the first device; preparing a second dielectric layer at the thermal conductive layer; preparing at least one thermal hole in the second dielectric layer, where the at least one thermal hole connected to the thermal conductive layer is provided in the second dielectric layer; preparing, on the second surface, a first circuit layer connected to the first device; preparing a third dielectric layer at the first circuit layer; and preparing, in the third dielectric layer, a first via connected to the first circuit layer. An expansion coefficient of the thermal conductive layer is the same as that of the first circuit layer, and an expansion coefficient of the second dielectric layer is the same as that of the third dielectric layer. It can be learned from the foregoing description that structures of the thermal conductive layer and the first circuit layer that are prepared by using materials with the same expansion coefficient, and the second dielectric layer and the third dielectric layer that are prepared by using materials with the same expansion coefficient are respectively disposed on two opposite sides of the first dielectric layer, so that the entire embedded package structure forms a quasi-symmetrical structure. When a substrate is deformed by heat, an expansion status of the thermal conductive layer is approximate to that of the first circuit layer, and an expansion status of the second dielectric layer is approximate to that of the third dielectric layer, so that warpage of the embedded package structure is alleviated. Moreover, the disposed thermal conductive layer and first circuit layer facilitate heat dissipation of the first device.

In an embodiment, the method further includes: preparing a second circuit layer on a surface of the third dielectric layer facing away from the first dielectric layer, where the second circuit layer is electrically connected to the first circuit layer through the first via; preparing a third circuit layer on a surface of the second dielectric layer facing away from the first dielectric layer; and electrically connecting the third circuit layer to the first circuit layer. An expansion coefficient of the second circuit layer is the same as that of the third circuit layer.

In an embodiment, the preparing a first dielectric layer around a first device, the first device being embedded in the prepared first dielectric layer, two opposite surfaces of the first device being respectively exposed on a first surface and a second surface that are opposite to each other of the first dielectric layer is: disposing a copper foil layer on a carrier board; placing the first device at the copper foil layer; forming a dielectric layer at the copper foil layer through injection molding, to wrap the first device; and thinning the dielectric layer to form the first dielectric layer.

In an embodiment, the electrically connecting the third circuit layer to the first circuit layer is:

preparing a conductive pillar at the copper foil layer; wrapping, by the dielectric layer, the conductive pillar when the dielectric layer is formed at the copper foil layer through injection molding; the conductive pillar being exposed when the dielectric layer is thinned to form the first dielectric layer; when the second dielectric layer is prepared, providing a second via electrically connected to the conductive pillar; the second circuit layer being electrically connected to the second via when the second circuit layer is disposed; de-bonding the first dielectric layer from the copper foil layer; preparing a third via when the third dielectric layer is prepared, where the third via is electrically connected to the conductive pillar; and electrically connecting the third circuit layer to the third via when the third circuit layer is prepared.

In an embodiment, an area in which the thermal conductive layer covers the first surface is greater than an area of a surface of the first device.

DESCRIPTION OF EMBODIMENTS

First, an application scenario of an embedded package structure is described. The embedded package structure is applied to a mobile terminal, such as a mobile phone, a tablet computer, or a wearable device (e.g., an electronic watch). As shown inFIG. 2a, using a mobile phone as an example, the mobile terminal includes a housing10and a printed circuit board disposed in the housing10. An embedded package structure20is disposed on the printed circuit board. The printed circuit board may be a mainboard30of the mobile terminal. During a connection, the embedded package structure20is electrically connected to the mainboard30, as shown inFIG. 2aandFIG. 2b. The embedded package structure20is placed on the mainboard30, and may be electrically connected to the mainboard30by using a ball grid array (BGA), as shown inFIG. 2a, or electrically connected to the mainboard30by using land grid array (LGA), as shown inFIG. 2b. A first device is embedded in the embedded package structure20, where the first device may be a chip or a passive device, and the chip may be chips with different functions, for example, a central processing unit (CPU) chip, a radio frequency drive chip, or a chip of another processor. When the passive device is used, the passive device may be a capacitor, an inductor, or a resistor.

To facilitate understanding of the embedded package structure20provided in an embodiment of the application, the following describes a structure of the embedded package structure20with reference to the accompanying drawings. First refer toFIG. 3aandFIG. 3b.FIG. 3ashows a schematic diagram of an overall structure of the embedded package structure20, andFIG. 3bshows a cutaway drawing of the embedded package structure20. It can be learned fromFIG. 3athat, the embedded package structure20is a plate-like structure as a whole. It can be learned with reference to the cutaway drawing along A-A shown inFIG. 3bthat, the embedded package structure20mainly includes two parts: a substrate21and a fourth dielectric layer26respectively. They are separately described below.

First refer toFIG. 4a.FIG. 4ashows a structure of the substrate21. The substrate21has a multi-layered structure in which a plurality of layers are stacked. The multi-layered structure mainly includes three dielectric layers: a first dielectric layer211, a second dielectric layer213a, and a third dielectric layer213b. During a setting, the first dielectric layer211has two opposite surfaces. For ease of description, the two opposite surfaces are respectively named as a first surface and a second surface. When the second dielectric layer213aand the third dielectric layer213bare disposed, the second dielectric layer213acovers the first surface, and the third dielectric layer213bcovers the second surface. In this case, the disposed second dielectric layer213aand third dielectric layer213bare disposed on two sides of the first dielectric layer211in an approximately symmetrical manner.

When the first dielectric layer211is disposed, a first device22is embedded in the first dielectric layer211. As shown inFIG. 4a, when the first dielectric layer211is disposed, the first device22is embedded in the first dielectric layer211. During production, the first device22is placed on a carrier board, and the first dielectric layer211is directly formed on the carrier board through injection molding. The first dielectric layer211formed during injection molding wraps the first device22, and then a thinning process is used, to make two surfaces of the first device22respectively exposed on the first surface and the second surface of the first device22. When the first dielectric layer211is prepared, the first dielectric layer211is prepared by using pure resin, in which no material that increases a strength such as glass fiber is doped. Because the pure resin has good fluidity, the formed first dielectric layer211can well surround the first device22, and reduce generation of air bubbles or gaps, so that the first dielectric layer211can be well attached to the first device22. It should be understood that,FIG. 4ashows a schematic structural diagram in which one first device22is embedded in the first dielectric layer211. However, in an embodiment of the application, a quantity of first devices22embedded in the first dielectric layer211is not limited to one, or may be two or three. As shown inFIG. 4b, two first devices22are embedded in the first dielectric layer211. However, regardless of the quantity of the first devices22embedded in the first dielectric layer211, a manner of connecting the first device22to another structural layer is the same. Therefore, the following provides description by using an example in which one first device22is embedded in the first dielectric layer211.

Still refer toFIG. 4a. It can be learned from the foregoing description that, the two opposite surfaces of the first device22embedded in the first dielectric layer211are respectively exposed on the first surface and the second surface of the first dielectric layer211. In addition, a difference between a thickness of the first device22and a thickness of the first dielectric layer211is within a predetermined range, which is 0 microns to 50 microns. That is, the difference between the thickness of the first device22and the thickness of the first dielectric layer211is a difference such as 0 microns, 10 microns, 20 microns, 30 microns, 40 microns, 50 microns, or another different difference. For example, the thickness of the first dielectric layer211is greater than that of the first device22, or the thickness of the first dielectric layer211is equal to that of the first device22. That the thickness of the first dielectric layer211is equal to that of the first device22means that the thickness of the first dielectric layer211is the same as that of the first device22within a tolerance range. The tolerance range is ±20 microns.

For ease of description, two surfaces of a die that are exposed on the first surface and the second surface are respectively named as a third surface and a fourth surface. Using a placement direction of the substrate21shown inFIG. 4aas a reference direction, the first surface is an upper surface of the first dielectric layer211, the second surface is a lower surface of the first dielectric layer211, the fourth surface is an upper surface of the first device22, and the third surface is a lower surface of the first device22. A pin is disposed on the third surface. As shown inFIG. 4a, when the first device22is embedded in the first dielectric layer211, the fourth surface of the first device22is exposed on the first surface of the first dielectric layer211, and the third surface of the first device22is exposed on the second surface of the first dielectric layer211. A distance between the fourth surface and the first surface is less than or equal to 50 microns. For example, the fourth surface is higher than or lower than the first surface by different distances such as 0 microns, 10 microns, 20 microns, and 50 microns. However, it should be understood that when the first device22is a device that has no heat dissipation requirement, the fourth surface of the first device22may not be exposed on the first surface of the first dielectric layer211.

In addition to the foregoing dielectric layers, the embedded package structure20further includes a first metal layer212aand a second metal layer212b, where the first metal layer212aand the second metal layer212bare respectively arranged on two opposite sides of the first device22. Still refer toFIG. 4a. When the first metal layer212aand the second metal layer212bare disposed, the first metal layer212acovers the first surface of the first dielectric layer211and is located between the first dielectric layer211and the second dielectric layer213a. Still refer toFIG. 4a. When the first metal layer212ais disposed, a metal layer is coated on the first surface of the first dielectric layer211through sputtering or by using another process, and the coated first metal layer212acovers the exposed fourth surface of the first device22. Then, the first metal layer212ais etched to form different patterns, but the first metal layer212aafter etching includes at least a thermal conductive layer2122covering the fourth surface of the first device22. The first metal layer212aincludes two electrically isolated parts: a conductive layer2121and the thermal conductive layer2122. The thermal conductive layer2122is in contact with the first device22. During preparation, metal is directly sputtered onto the first device22. When the first device22is a chip, the first device22uses a die. In this case, the thermal conductive layer2122is in direct contact with the die. During heat dissipation of the die, generated heat is directly transferred to the thermal conductive layer2122. Compared with a packaged chip used as an embedded chip in a conventional technology, the packaged chip in the conventional technology includes a circuit layer and a package layer for packaging the circuit layer. When a heat dissipation structure is disposed, a thermal conductive layer is laid at the package layer of the packaged chip and is not in direct contact with the chip, thereby increasing heat transfer paths. However, in an embodiment, the thermal conductive layer is in direct contact with the die, to improve a heat dissipation effect. In addition, in an embodiment of the application, an area of the thermal conductive layer2122is greater than that of a surface of the first device22. That is, the area of the thermal conductive layer2122is greater than that of the fourth surface of the first device22, thereby further improving the heat dissipation effect of the first device22.

When the second dielectric layer213ais prepared, the second dielectric layer213ais directly prepared at the first metal layer212a, and the prepared second dielectric layer213ahas a particular strength. The second dielectric layer213ais prepared by using a resin material doped with glass fiber, provided that a ratio of the glass fiber to resin is a common ratio in the conventional technology. It needs to be ensured that the second dielectric layer213ahas a particular supporting strength.

Still refer toFIG. 4a. When the second dielectric layer213ais prepared, a plurality of thermal holes27dare provided in the second dielectric layer213a. After the second dielectric layer213ais formed, the plurality of thermal holes27dare formed in the second dielectric layer213athrough etching or by using another process. A vertical projection of each thermal hole27don the first surface is located at the thermal conductive layer2122, and each thermal hole27dis enabled to communicate with the thermal conductive layer2122, so that heat absorbed by the thermal conductive layer2122is transferred by using the thermal hole27d. In addition, locations and an arrangement manner of the thermal holes27dmay be determined based on requirements and are not limited to the manner shown inFIG. 4a.

Still refer toFIG. 4a. When the second metal layer212bis disposed, the second metal layer212bis a first circuit layer. During setting, a metal layer is first formed on the second surface of the first dielectric layer211through sputtering or by using another process, and then a required circuit pattern is formed through etching. In addition, when the second metal layer212bis disposed, the second metal layer212bis electrically connected to the first device22. As shown inFIG. 4a, there is a protective film layer on the third surface of the first device22, and the protective film layer has a window. The pin of the first device22is exposed outside the window of the protective film layer. When the second metal layer212bis sputtered on the second surface, conductive metal fills the window of the protective film layer and is electrically connected to the pin of the first device22, to implement an electrical connection between the first device22and the second metal layer212b. However, when the window is opened in the protective layer, due to limitation of a process level, the opened window has a diameter of approximately 40 μm, resulting in a relatively large size of a connection between the second metal layer212band the pin. Therefore, when the connection between the second metal layer212band the first device22needs to be relatively small, the manner shown inFIG. 4amay be used: A photosensitive resin layer221may be preset outside the protective film layer of the first device22, and the photosensitive resin layer221is directly connected to a region opposite to the pin of the first device22. This may be understood as opening a window in the protective film layer, then preparing the photosensitive resin layer221at the protective film layer, and filling the disposed photosensitive resin layer221into the window for a direct connection to the pin. When the second metal layer212bneeds to be connected to the pin, a window with a diameter less than 5 μm to 10 μm may be opened in the photosensitive resin layer221by using a process for preparing a wafer (e.g., the wafer that is a source material of the first device22) when the first device22is produced. Therefore, an aperture of the connection between the second metal layer212band the pin is reduced, so that pins of the first device22can be disposed more densely, thereby facilitating miniaturization of the entire first device22. Certainly, the foregoing description is provided by using an example in which the window is a circle. However, the window opened in an embodiment of the application is not limited to a circle, but may also have different sizes such as a square and an oval.

Still refer to the structure inFIG. 4a. When the second metal layer212bis disposed, the second metal layer212bis located between the first dielectric layer211and the third dielectric layer213b. After the second metal layer212bis prepared, the third dielectric layer213bmay be directly prepared at the second metal layer212b, and the prepared third dielectric layer213bcovers the second metal layer212b. A material of the third dielectric layer213bis the same as that of the second dielectric layer213a. The third dielectric layer213bis also prepared by using a resin material doped with glass fiber. In addition, when the second dielectric layer213aand the third dielectric layer213bare disposed, a thickness of the second dielectric layer213ais approximately the same or completely the same as that of the third dielectric layer213b. In addition, first vias27afor connecting to the second metal layer212bare provided in the third dielectric layer213b. As shown inFIG. 4a, there are a plurality of connecting ends2123at the second metal layer212b, and one first via27ais correspondingly provided in each of the connecting ends2123. One end of the first via27ais electrically connected to the connecting end2123at the second metal layer212b, and the other end is configured to connect to another circuit, so that the second metal layer212bis connected to the another circuit. When the first vias27aare provided, positions of the first vias27aare set based on positions of the connecting ends2123at the second metal layer212b. When the first vias27aare formed, through holes are provided in the second dielectric layer213athrough etching or in another known manner, and then metal layers are evaporated on side walls of the through holes. The metal layers are one-to-one electrically connected to the connecting ends2123of the second metal layer212b.

It can be learned from the foregoing description that the placement direction of the embedded package structure20shown inFIG. 4ais used as the reference direction. In a vertical direction, metal layers (e.g., the first metal layer212aand the second metal layer212b) are first respectively disposed on upper and lower sides of the first dielectric layer211, and then two dielectric layers (e.g., the second dielectric layer213aand the third dielectric layer213b) are correspondingly disposed respectively. When the two metal layers are disposed, the two metal layers use a same material, such as copper, silver, or another conductive metal. For example, the two metal layers both use a copper material. A copper doping ratio of the first metal layer212ais the same as or approximate to that of the second metal layer212b, where the copper doping ratio is a ratio of a metal covered area to a total area of a surface to which metal is sputtered. Therefore, when the copper doping ratio of the first metal layer212ais approximately equal to that of the second metal layer212b, expansion coefficients of the first metal layer212aand the second metal layer212blocated on the two sides of the first dielectric layer211are the same. For the disposed second dielectric layer213aand third dielectric layer213b, because the second dielectric layer213aand the third dielectric layer213buse the same material and also have the approximately same thicknesses, expansion coefficients of the two disposed dielectric layers are also approximately the same. It can be learned from the foregoing description that, approximate structures are symmetrically disposed on the two sides (e.g., up and down directions) of the first dielectric layer211, to form a quasi-symmetrical structure (e.g., the first metal layer212ais quasi-symmetrical with the second metal layer212b, and the second dielectric layer213ais quasi-symmetrical with the third dielectric layer213b), so that expansion coefficients of the structures located on the two sides of the first dielectric layer211are approximate to each other. Therefore, when the embedded package structure20is used, deformations of the structures on the two sides of the first dielectric layer211are approximately equal, so that warpage of the embedded package structure20can be effectively limited, and a use effect of the substrate21is improved. The foregoing quasi-symmetry refers to a case in which positions of the two structures are symmetrical, and a difference between the two structures is not large. Using the first metal layer212aand the second metal layer212bas an example, when the copper doping ratio of the first metal layer212ais approximately equal to that of the second metal layer212b, it is considered that the first metal layer212aand the second metal layer212bare disposed on the two sides of the first dielectric layer211in a quasi-symmetric manner.

Still refer toFIG. 4a. In addition to the foregoing quasi-symmetrical structures, another quasi-symmetrical structure is further disposed in the embedded package structure20. For example, the embedded package structure20further includes a third metal layer214band a fourth metal layer214a. The third metal layer214bis disposed on a surface of the third dielectric layer213bfacing away from the first dielectric layer211, and the fourth metal layer214ais disposed on a surface of the second dielectric layer213afacing away from the first dielectric layer211. When the third metal layer214band the fourth metal layer214aare disposed, the third metal layer214band the fourth metal layer214aare both circuit layers. The third metal layer214bis a second circuit layer, and the fourth metal layer214ais a third circuit layer. First, when the third metal layer214bis prepared, a metal layer is formed on the surface of the third dielectric layer213bfacing away from the first dielectric layer211through sputtering or by using another known process, and then the third metal layer214bis formed through etching or laser cutting. As shown inFIG. 4a, when the third metal layer214bis formed, the third metal layer214bis electrically connected to the second metal layer212b. When an electrical connection is implemented, the third metal layer214bhas connecting ends2141configured to connect to the second metal layer212b, and the connecting ends2141are one-to-one connected to the first vias27a. It can be learned fromFIG. 4athat, the second metal layer212band the third metal layer214bare respectively located on two ends of the first vias27a, and the second metal layer212band the third metal layer214bare electrically connected to each other by using the provided first vias27a. In addition, two ends of each first via27aare respectively connected to the connecting end2123of the second metal layer212band the connecting end2141of the third metal layer214b, so that the first metal layer212ais conductively connected to the third metal layer214b.

For the fourth metal layer214a, as shown inFIG. 4a, the fourth metal layer214ais disposed on the surface of the second dielectric layer213afacing away from the first dielectric layer211. When the fourth metal layer214ais prepared, a metal layer is formed on the surface of the second dielectric layer213afacing away from the first dielectric layer211through sputtering or by using another known process, then the third circuit layer is formed through etching or laser cutting, and the formed fourth metal layer214ais also used as a heat dissipation structure of the first device22. As shown inFIG. 4a, when the fourth metal layer214ais disposed, the fourth metal layer214acovers the thermal holes27d. Heat dissipated from the top of the first device22is transferred to the thermal holes27dby using the thermal conductive layer2122. Then, the heat is transferred to the fourth metal layer214aby using the thermal holes27d, so that the heat dissipated from the top of the first device22can be dissipated by using the first metal layer212aand the fourth metal layer214a, thereby improving the heat dissipation effect.

Still refer toFIG. 3b. It can be learned fromFIG. 3bthat when the third metal layer214band the fourth metal layer214aare disposed, the third metal layer214band the fourth metal layer214aare respectively arranged on the two sides of the first dielectric layer211, and the third metal layer214band the fourth metal layer214aare both circuit layers. However, when the third metal layer214band the fourth metal layer214aare disposed, a manner of disposing the third metal layer214band the fourth metal layer214ais similar to that of disposing the first metal layer212aand the second metal layer212b. That is, a copper doping ratio of the third metal layer214bis approximate to that of the fourth metal layer214a, so that the third metal layer214band the fourth metal layer214aare disposed on the two sides of the first dielectric layer211in a quasi-symmetrical manner. Therefore, the disposed third metal layer214band fourth metal layer214ado not cause warpage of the embedded package structure20.

In addition, when the third metal layer214band the fourth metal layer214aare disposed, the third metal layer214band the fourth metal layer214aare respectively the second circuit layer and the third circuit layer, and the disposed third metal layer214bis electrically connected to the second metal layer212b. When the fourth metal layer214ais disposed, based on requirements, the fourth metal layer214amay be separately electrically connected to the third metal layer214band the second metal layer212b, or may be electrically connected to only the third metal layer214b, or may be electrically connected to only the second metal layer212b, or the like. As shown inFIG. 4a, the fourth metal layer214ais separately electrically connected to the third metal layer214band the second metal layer212b. First, a connection between the fourth metal layer214aand the second metal layer212bis described. As shown inFIG. 4a, when the fourth metal layer214ais electrically connected to the second metal layer212b, because the fourth metal layer214aand the second metal layer212bare respectively arranged on two sides of the first device22and are not adjacent to each other, during disposal, a structure running through the first dielectric layer211and the second dielectric layer213aneeds to be disposed to connect the second metal layer212bto the fourth metal layer214a. The foregoing structure includes a conductive pillar23embedded in the first dielectric layer211and a second via27cprovided in the second dielectric layer213a, where the second via27cis electrically connected to the conductive pillar23. Still refer toFIG. 4a. In an embodiment, at least one through hole is provided in the first dielectric layer211(the through hole is not marked in the figure because the through hole overlaps the conductive pillar23), and a conductive pillar23is fixed in each through hole. However, during formation of the foregoing structure, when the first dielectric layer211is prepared, the first device22and the conductive pillar23are first placed at preset positions, and then the first dielectric layer211is formed through injection molding of resin. After injection molding, the conductive pillar23is embedded in the first dielectric layer211. Two surfaces of the conductive pillar23are respectively exposed on the first surface and the second surface of the first dielectric layer211. It can be learned from the foregoing description that after the first dielectric layer211is prepared, the first metal layer212aneeds to be prepared on the first surface and the second metal layer212bneeds to be prepared on the second surface. When the first metal layer212aand the second metal layer212bare prepared, the first metal layer212aand the second metal layer212bare respectively electrically connected to the two exposed surfaces of the conductive pillar23. When the second metal layer212bis formed through etching or by using another process, the conductive pillar23is directly electrically connected to the second metal layer212b. When the first metal layer212ais etched, in addition to the thermal conductive layer2122, the first metal layer212aalso forms the conductive layer2121connected to the conductive pillar23. When the second dielectric layer213acontinues to be prepared, after the second dielectric layer213ais formed, a hole is provided in the second dielectric layer213a, so that the conductive layer2121is exposed, and then a metal layer is coated in the hole to form the second via27c. The second via27cis electrically connected to the conductive pillar23by using the conductive layer2121. When the fourth metal layer214ais formed on the surface of the second dielectric layer213afacing away from the first dielectric layer211, the fourth metal layer214ais electrically connected to the second via27c. In this case, the fourth metal layer214ais electrically connected to the second metal layer212bby using the second via27cand the conductive pillar23. It should be understood that, when the second via27cand the conductive pillar23are disposed, different quantities of second vias27cand conductive pillars23may be disposed based on requirements. As shown inFIG. 4a, there are two conductive pillars23, butFIG. 4ais only an example. In an embodiment of the application, different quantities of conductive pillars23, for example, three, one, five, or six conductive pillars23, may be disposed based on requirements, provided that it is ensured that the fourth metal layer214acan be connected to the second metal layer212b.

Still referring toFIG. 4a. When the fourth metal layer214ais electrically connected to the second circuit layer, when the fourth metal layer214ais electrically connected to the third metal layer214b, the foregoing structure of the second via27cand the conductive pillar23is also used. However, because the third dielectric layer213bis further disposed between the conductive pillar23and the third metal layer214b, a third via27bis provided in the disposed third dielectric layer213b, to connect the conductive pillar23to the third metal layer214b. For a manner of providing the third via27b, refer to the foregoing manner of providing the second via27c. In addition, the third via27bis also electrically connected to the conductive pillar23. In this case, when the fourth metal layer214ais electrically connected to the third metal layer214b, the second via27c, the conductive pillar23, and the third via27bare used.

Still refer toFIG. 4a. In the entire substrate21, outermost layers are the third metal layer214band the fourth metal layer214a. In addition, to protect the third metal layer214band the fourth metal layer214a, protective layers are respectively covered on the third metal layer214band the fourth metal layer214a. The protective layer may be a solder mask layer, or different layers with a protective function such as a plastic package layer or a resin layer. However, to ensure that the substrate21can be electrically connected to another component, a window is opened in the disposed protective layer. For ease of understanding, the following separately provides description.

First, for the second circuit layer, for ease of description, the protective layer covering the third metal layer214bis named as a first protective layer215b. When the first protective layer215bis disposed, a protective layer is formed at the second circuit layer through injection molding or evaporation, and the formed first protective layer215bhas a plurality of first windows2152. The first windows2152correspond to the connecting ends2141of the third metal layer214b. In this case, the third metal layer214bhas first connecting ends exposed on the first windows2152. The disposed first connecting ends may be configured to connect to another circuit. As shown inFIG. 5a, the first windows2152formed in this case may provide an electrical connection between the embedded package structure20and the mainboard by using a land grid array (LGA). In addition to the foregoing manner, another manner may also be used. As shown inFIG. 5b, in this case, the substrate21further includes a first protective layer215bcovering the third metal layer214b, the first protective layer215bhas a plurality of first windows, and solder balls28connected to the second circuit layer are disposed at the first windows. The solder balls28can provide an electrical connection between the substrate21and the mainboard by using a ball grid array28(BGA). Refer to bothFIG. 2aandFIG. 2b. During a connection, the substrate21is electrically connected to the mainboard30by using the LGA or the BGA.

In addition, the third metal layer214band the second metal layer212bmay also be used as a heat dissipation channel of the first device22in addition to being used for the electrical connection. When heat dissipation of the first device22is provided by using the mainboard30, it can be learned fromFIG. 4athat, when heat is transferred, the heat generated by the first device22is transferred to the second metal layer212b, and then transferred to the third metal layer214bby using the second metal layer212b, and then transferred to the mainboard. In addition, it can be learned from the foregoing description that, when the second metal layer212bis disposed, the second metal layer212bis directly attached to the first device22, and there is a relatively large contact area between the second metal layer212band the first device22. Therefore, the heat generated by the first device22can be quickly transferred to the second metal layer212b, and transferred to the third metal layer214bby using the second metal layer212b. The heat generated by the first device22is transferred by using the two metal layers, to facilitate heat dissipation of the first device22. In addition, for the first device22, a chip with relatively high power consumption, such as a radio frequency drive chip, may be used. When a chip with relatively high radio frequency is used, if the chip is embedded in the first dielectric layer211, compared with a state in which the chip is disposed on a surface of the substrate21facing away from the mainboard30, when the mainboard30is used as a heat dissipation path, the embedding setting manner enables the chip to be closer to the mainboard30, thereby reducing a length of the chip heat dissipation path, and facilitating heat dissipation of the chip. In addition, by embedding the chip in the first medium, an area of the surface of the substrate21facing away from the mainboard30that is occupied by the chip can be reduced, thereby helping dispose more devices.

Still refer to the structure shown inFIG. 4a. For the fourth metal layer214a, a protective layer covering the fourth metal layer214ais further included. The protective layer is named as a second protective layer215a. The second protective layer215ahas a plurality of second windows2151. The third circuit has second connecting ends exposed on the second windows2151. A structure of the second protective layer215ais approximately the same as that of the first protective layer215b. Therefore, reference may be made to the foregoing description about the first protective layer215b. Also refer to the structure shown inFIG. 2b. Another device, for example, a second device25or another passive device24, may be disposed on the surface of the substrate21, and the second device25and the passive device24are connected to the first circuit layer. InFIG. 2b, one second device25and one passive device24are disposed. The passive device24may be a passive device24, such as an inductor, a capacitor, or a resistor, used for functions such as filtering. The second device25is a radio frequency device, such as a power amplifier or a filter, that provides interconnection by using an Au wire bonding process or a flip-chip bonding process. In addition, the embedded package structure20further includes the fourth dielectric layer26disposed at the second dielectric layer213aand covering the second device25and the passive device24. The fourth dielectric layer26is used as a package layer, and a material of the fourth dielectric layer26may be resin. When the second device25and the passive device24are packaged, liquid resin is poured onto the second device25and the passive device24, and after cooling, the second device25and the passive device24are embedded in the fourth dielectric layer26. When the second device25and the passive device24need to be shielded, a shielding cover (not shown in the figure) may further be covered at the fourth dielectric layer26. The shielding cover is made of a metal material and is electrically connected to a ground cable of any circuit layer in the substrate21, to shield the second device25and the passive device24.

Still refer toFIG. 5a. When heat dissipation is performed by using the top, a heat-sink device may be disposed at the fourth dielectric layer26(the heat-sink device is not shown inFIG. 5a), to perform heat dissipation on the entire embedded package structure. In this case, the heat generated by the embedded first device22may be transferred to the thermal holes27dby using the first metal layer212a, and then transferred to the fourth metal layer214aby using the thermal holes27d. In this way, the heat dissipated from the top of the first device22can be dissipated to the surface of the substrate21by using the thermal conductive layer2122and the fourth metal layer214a, and heat dissipation is performed by using the heat-sink device.

Also refer toFIG. 6. During a connection, when connections between devices in the substrate21and connections between devices outside the substrate21are implemented, another device on the mainboard30receives a signal. The signal is transmitted into the third metal layer214bby using interconnected pads between the embedded package structure20and the mainboard30. The signal is, for example, input shown inFIG. 6. After the signal enters the substrate21, the signal is transmitted to the second metal layer212bby using the first vias27a, and then the signal is transmitted by using the second metal layer212bto the first device22for processing. The processed signal passes through an output terminal of the first device22to the second metal layer212b, and then is transmitted into the passive device24by using the conductive pillar23, the conductive layer2121, the second via27c, the fourth metal layer214a, and a pad and a solder for soldering the passive device24. After filtering, denoising, and other processing are performed on the signal, the signal is transmitted from the passive device24by using the fourth metal layer214ato a power amplifier (e.g., the second device25) for signal enhancement. Finally, the signal (output) is transmitted onto the mainboard by using a metal jumper wire251, the fourth metal layer214a, the second via27c, the conductive layer2121, the conductive pillar23, the second metal layer212b, the first vias27a, the third metal layer214b, and the pads. Processing of the entire signal is implemented. In an embodiment, reference may be made to a path shown by a solid line with an arrow inFIG. 6, where the path is a path of the signal in the embedded package structure20.

To facilitate understanding of the embedded package structure provided in an embodiment of the application, an embodiment of the application further provides a method for preparing a package substrate21. The method includes:

preparing a first dielectric layer211around a first device22, the first device22being embedded in the prepared first dielectric layer211, two opposite surfaces of the first device22being respectively exposed on a first surface and a second surface that are opposite to each other of the first dielectric layer211, and a difference between a thickness of the first device22and a thickness of the first dielectric layer211being within a predetermined range;

attaching a thermal conductive layer2122to the first surface, where the thermal conductive layer is in contact with the first device;

preparing a second dielectric layer213aat the thermal conductive layer2122;

preparing at least one thermal hole27din the second dielectric layer213a, where the at least one thermal hole27dis connected to the thermal conductive layer;

preparing, on a surface of the first device22that is exposed on the second surface, a first circuit layer connected to the first device22;

preparing a third dielectric layer213bat the first circuit layer; and

preparing, in the third dielectric layer213b, a first via27aconnected to the first circuit layer.

An expansion coefficient of the thermal conductive layer2122is the same as that of the first circuit layer, and an expansion coefficient of the second dielectric layer is the same as that of the third dielectric layer.

In addition to the foregoing operations, the method further includes: preparing a second circuit layer on a surface of the third dielectric layer213bfacing away from the first dielectric layer211, where the second circuit layer is electrically connected to the first circuit layer through the first via27a;

preparing a third circuit layer on a surface of the second dielectric layer213afacing away from the first dielectric layer211; and

electrically connecting the third circuit layer to the first circuit layer.

An expansion coefficient of the second circuit layer is the same as that of the third circuit layer.

In addition, the method further includes: the preparing a first dielectric layer211around a first device22, the first device22being embedded in the prepared first dielectric layer211, two opposite surfaces of the first device22being respectively exposed on a first surface and a second surface that are opposite to each other of the first dielectric layer211is: disposing a copper foil layer on a carrier board; placing the first device22at the copper foil layer; forming a dielectric layer at the copper foil layer through injection molding, to wrap the first device22; and thinning the dielectric layer to form the first dielectric layer211.

The electrically connecting the third circuit layer to the first circuit layer is:

preparing a conductive pillar23at the copper foil layer;

wrapping, by the dielectric layer, the conductive pillar23when the dielectric layer is formed through injection molding;

the conductive pillar23being exposed when the dielectric layer is thinned to form the first dielectric layer211;

when the second dielectric layer213ais prepared, providing a second via electrically connected to the conductive pillar23;

the second circuit layer being electrically connected to the second via when the second circuit layer is disposed;

de-bonding the first dielectric layer211from the copper foil layer;

preparing a third via when the third dielectric layer213bis prepared, where the third via is electrically connected to the conductive pillar23; and

electrically connecting the third circuit layer to the third via when the third circuit layer is prepared.

For ease of understanding of the foregoing method operations, the following describes the method operations in detail with reference to accompanying drawings.

Operation 1: Form the conductive pillar23on the carrier board40.

In an embodiment, as shown inFIG. 7, the conductive pillar23is processed and manufactured at the copper foil layer50of the debondable carrier board40based on a thickness of the first device. The conductive pillar23is required to have a thickness same as that of the first device. The following detailed operations are included: process operations such as pretreatment before film pasting, film pasting, exposure, development, pattern plating, acid washing, and stripping for forming the conductive pillar23. The foregoing manufacturing processes are all common processes in a conventional technology. Therefore, details are not described herein.

Operation 2: Perform surface mounting on the first device22.

In an embodiment, as shown inFIG. 8, a front surface (e.g., the third surface222) that is of the first device22and on which a window is pre-opened and a surface-mount adhesive film is pre-manufactured is mounted downwardly to the copper foil of the carrier board40. Moreover, the surface-mount process requires relatively high precision to ensure alignment process precision required by lines that need to be interconnected.

Operation 3: Perform plastic packaging or embedded lamination.

In an embodiment, as shown inFIG. 9, the first device22and the conductive pillar23may be completely embedded by using resin (e.g., doped with no glass fiber) in a manner of plastic packaging or a manner of vacuum lamination process.

In an embodiment, as shown inFIG. 10, a process manner such as mechanical thinning, plasma thinning, or laser thinning, or a hybrid process manner is used to clean the resin on a surface of the conductive pillar23and a back surface (e.g., the fourth surface223) of the first device22, to expose the conductive pillar23and the fourth surface223of the first device22. A thinned resin layer is the first dielectric layer211.

Operation 5: Manufacture inner-layer lines, to form a first metal layer212a.

In an embodiment, as shown inFIG. 11, an adhesion layer and a metal thin film are first processed in manners such as PVD and evaporation in a plane (e.g., the first surface2111) in which the first dielectric layer211is thinned, and then the detailed process procedures such as pretreatment before film pasting, film pasting, exposure, development, pattern plating, acid washing, and stripping are repeated, to manufacture a line layer on the back surface of the first device22, to form the first metal layer212a. In addition, the first metal layer212aincludes a conductive layer2121connected to the conductive pillar23and the thermal conductive layer2122for performing heat dissipation for the first device22.

Operation 6: Prepare the second dielectric layer213athrough lamination.

In an embodiment, as shown inFIG. 12, the second dielectric layer213ais manufactured on a back metal layer through high-temperature or vacuum lamination, and the manufactured second dielectric layer213auses resin doped with glass fiber.

In an embodiment, as shown inFIG. 13andFIG. 14, the structure formed above is directly separated from the carrier board40by using debondability of the copper foil layer50on the carrier board40. As shown inFIG. 14, the substrate21in which the first device22is embedded is formed after de-bonding.

In an embodiment, as shown inFIG. 14andFIG. 15, the copper foil layer50adhered to the third surface222of the first device22is removed by using an etching process, to expose the first dielectric layer211and the first device22.

Operation 9: Remove the surface-mount adhesive film.

In an embodiment, as shown inFIG. 16, the surface-mount adhesive film pre-manufactured on the front surface of the first device22is removed by using a chemical liquid wet process, and residual adhesive is removed by using a plasma cleaning device to expose a pin2221of the first device22.

Operation 10: Prepare a second metal layer212b, and form the first circuit layer.

In an embodiment, as shown inFIG. 17, an adhesion layer and a metal thin film are processed in manners such as physical vapor deposition (PVD) and evaporation on the window in the front surface of the first device22and resin on the surface of the first device22, to form the second metal layer212b, and then the detailed process procedures such as pretreatment before film pasting, film pasting, exposure, development, pattern plating, acid washing, and stripping are repeated, to manufacture an interconnected line layer on the front surface of the first device, to form the first circuit layer.

Operation 11: Perform lamination to prepare the third dielectric layer213b.

In an embodiment, as shown inFIG. 18, a layer of dielectric layer resin (e.g., the third dielectric layer213b) with a thickness same as that of the second dielectric layer213ais manufactured at the second metal layer212bby using a high-temperature or vacuum lamination process method, to form a symmetrical structure.

Operation 12: Manufacture laser blind holes and outer-layer lines.

In an embodiment, as shown inFIG. 19, vias are processed in a laser drilling manner on pads corresponding to the inner-layer lines, and after the vias (e.g., a first via27a, a second via27c, a third via27b, and a thermal hole27d) are manufactured, as shown inFIG. 20, the detailed process procedures such as pretreatment before film pasting, film pasting, exposure, development, pattern plating, acid washing, and stripping are repeated to manufacture the outer-layer lines, e.g., a third metal layer214band a fourth metal layer214a.

Operation 13: Perform solder masking and surface metal processing.

In an embodiment, as shown inFIG. 21, a solder mask layer is manufactured on the outer-layer lines by using a vacuum lamination process method, to form a first protective layer215band a second protective layer215a, and windows are opened at positions at which pins are correspondingly led out, to form pads interconnected with the outside, and a metal layer or an organic thin film layer is manufactured on the pads, to prevent oxidation of outer-layer copper pads and exposed lines.

It can be learned from the foregoing operations that the embedded package structure prepared and formed by using the foregoing method alleviates warpage of the substrate in a quasi-symmetrical manner, and heat dissipation of the first device22is facilitated by using the plurality of disposed metal layers.

As shown inFIG. 2a, an embodiment of the application further provides a terminal. The terminal may be a common terminal such as a mobile phone or a tablet computer. The terminal includes the foregoing embedded package structure. The embedded package structure alleviates warpage of the substrate in a quasi-symmetrical manner, and heat dissipation of the first device is facilitated by using the plurality of disposed metal layers.

The foregoing descriptions are merely embodiments of the application, but are not intended to limit the protection scope of the application. Any variation or replacement readily figured out by one of ordinary skill in the art within the technical scope disclosed in the application shall fall within the protection scope of the application. Therefore, the protection scope of the application shall be subject to the protection scope of the claims.