Printed circuit board having outer power planes

A multi-layer printed circuit board (PCB) routes signal traces on internal signal layer(s) and includes power planes on the two outermost layers. The outer layers are maintained at the same non-ground voltage level, and are electrically connected by a series of vias that circumscribe signal traces on the internal layer(s). With a preferred maximum spacing of one-tenth the wavelength of electromagnetic energy generated by the signal traces, the vias, together with the outer power planes, contain electromagnetic energy within the PCB. One or more of the outer planes may include a second power plane area maintained at a different voltage. The two power plane areas are connected by decoupling capacitors, located proximate underlying signal traces that traverse the two power plane areas.

BACKGROUND OF THE INVENTION

The present invention relates generally to the field of electronics and in particular to a printed circuit board having power planes on the outermost layers.

The use of multi-layer printed circuit boards (PCB) is well known in the electronic arts. As circuit components simultaneously shrink in size, increase in complexity, and operate at higher frequencies, the resulting increased density, complexity and issues of electromagnetic compatibility have driven the need for printed circuit boards to provide an increasing number of layers with which to route electrical signals and power supply voltages to all components. A multi-layer PCB provides a plurality of electrically conductive layers separated by insulating dielectric layers. The conductive layers may comprise contiguous plane areas, or alternatively may comprise a complex pattern of point-to-point signal traces. The signal traces are arranged to provide the connectivity required among all of the components on the PCB, employing well known routing strategies, such as for example, primarily north-south traces on one layer, and primarily east-west traces on another layer. Both signal traces and power plane voltages may be propagated to other layers by vias, electrically conductive holes through one or more dielectric layers and possibly one or more conductive layers. Signal traces and power plane areas are routed away from vias passing through conductive layers that are not to be electrically connected at that level, as is well known in the art.

A typical “stack,” or arrangement of layers, for early multi-layer PCBs was to locate ground and/or power planes on internal conductive layers, and route signal traces on the outer PCB layers. This facilitated the interconnection of components with signal traces, requiring a minimum number of vias. As PCBs were populated with more complex components, such as microprocessors and Application Specific Integrated Circuits (ASIC), which often require multiple power supply voltage levels, additional internal power plane layers were added to the PCB stack.

With increasing operating frequency of many electrical circuits, the Electromagnetic Compatibility (EMC) of the PCB became a concern, as signal traces radiate electromagnetic energy at high frequencies, potentially causing interference with other electronic circuits. It was discovered that the use of contiguous power planes covering a significant area often improved signal quality and EMC performance. This is due to several factors, including the overall reduction of the loop area between the signal traces and their return signal paths, and the inherent decoupling provided by the distributed inter-plane capacitance. For example, a common stack for a 6-conductive-layer PCB is Signal-Power-Signal-Signal-Ground-Signal (often referred to as S-P-S-S-G-S). In this stack, the high-speed signals are routed on the two middle, or innermost, signal layers, between the power and ground plane layers. In this configuration, provided that the power plane is well decoupled to the ground plane, the power and ground planes together attenuate the electromagnetic fields radiated by those traces on the internal layers shielded by the power planes.

In circuits where most or all of the signal traces carry high frequency signals, it is known to “bury” all signal traces on internal conductive layers, and locate dedicated ground planes on the outer two PCB layers. Both the top and bottom conductive planes are formed in as large and contiguous an area as possible, both are connected to the ground reference voltage of the power supply, and the outer planes are interconnected to each other vertically through the use of vias generously located throughout the plane area. Positive power supply voltage levels may be distributed to components on one or more internal power plane layers, or alternatively as signal traces on one or more signal trace layers. On the outer layers, short traces from each component pin route the associated signal from each pin to a via, which connects to a signal trace located on an interior layer. To allow this routing, the area immediately adjacent the pins at each component position is clear of the ground plane, which fills the remainder of the outer layer with a contiguous ground plane. This PCB stack has been known to reduce electromagnetic emissions from the PCB by as much as 10 dB.

Although the use of outer ground planes provides a significant improvement in EMC performance of a PCB, there remain some situations where this implementation is not feasible or desirable. One example is the use of a component wherein the housing or a portion of the housing is maintained during operation at a voltage level other than ground, such as for example the collimator of a laser diode, or the tab of a TO-220 semiconductor package. In such cases, providing a ground plane on the outer layer would require that a large area of the ground plane be excluded from the vicinity of the relevant component. Signal traces routed to this component would no longer have the ground plane in close proximity, resulting in greater emissions. Alternatively, if the outer ground plane were placed closer to the part to reduce emissions, there is an increased risk of a short circuit between the component housing and ground.

It is desirable, therefore, to provide positive or negative voltage level power planes—rather than a ground plane—as the outermost layers in a multi-layer PCB stack. U.S. Pat. No. 6,288,906 discloses a printed circuit board having power plane layers at the outermost layer positions. The outer power planes of the '906 patent, however, are connected to different positive supply voltages. As described above, it is known that generously interconnecting the two outer ground plane layers by vias increases the EMC performance of the PCB. The direct connection of outer power planes by vias is impossible when the planes are maintained at different voltages.

SUMMARY OF THE INVENTION

The present invention relates to a multi-layer printed circuit board having power planes on the outermost layers. Conductive planes on the outer layers are maintained at the same voltage. The power planes are electrically connected by a series of vias circumscribing at least some of the signal traces on internal signal layers. By placing the vias with a maximum spacing of one-tenth the wavelength of the highest frequency of electromagnetic energy generated by the signal traces, radiation of the electromagnetic energy is reduced.

One of the outer power planes may include a conductive plane portion maintained at a different voltage, such as signal ground. The two conductive planes are connected by decoupling capacitors. The decoupling capacitors are preferably located proximate signal traces crossing the two conductive plane areas.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a multi-layer Printed Circuit Board (PCB) having non-ground voltage level power planes at the outermost layers. The outer power planes are maintained at the same voltage level, which may be a positive or negative voltage level with respect to the reference voltage, or signal ground, of the circuit. For simplicity and clarity of expression, the invention is described herein with positive voltage level outer power planes. A multi-layer PCB according to the present invention is depicted inFIG. 1, indicated generally by the numeral10. The PCB10includes an internal, conductive signal layer12, comprising a plurality of signal traces18. The signal traces18may be formed by lithography, etching, printing, plating, or other methods as known in the art. The PCB may include only the single signal trace layer12, or alternatively, as depicted inFIG. 1, may additionally include a second signal layer14, comprising signal traces20. The PCB10may, in general, comprise any number of internal signal layers12,14, although only two such layers are depicted inFIG. 1for simplicity. The signal traces18,20in the signal layers12,14may be oriented orthogonally, as well known in the art. The signal layers12,14are separated by an insulating dielectric layer16. Signal traces18,20may be connected where necessary or desired by vias (not shown) through dielectric layer16.

Overlying the uppermost signal layer12is another dielectric layer22, and overlying the dielectric layer22is a positive voltage level power plane layer24. Positive voltage level power plane layer24comprises a positive voltage level power plane23and a ground voltage level power plane40, separated by a gap42. The purpose and function of the ground voltage level power plane40is explained below.

Similarly, underlying the lowermost signal layer14is another dielectric layer25. Underlying dielectric layer25is a positive voltage level power plane layer29, comprising positive voltage level power plane27. Although not depicted inFIG. 1, the positive voltage level power plane layer29may additionally include one or more power or ground voltage level power plane areas.

According to the present invention, positive voltage level power planes23and27are maintained at the same positive power supply voltage level whenever power is applied to the PCB10. Electronic components, preferably surface-mount components, may be mounted on positive voltage level power plane layer24,29, or both. The PCB10of the present invention finds particular utility in applications wherein components to be mounted to layers24and/or29include a housing with a significant surface area that is at a positive voltage level when the component is in operation. One example of such a component is the collimator of an anode stem laser diode commonly utilized in laser printers, copiers, fax machines, and the like. The collimator housing is maintained at the laser diode's Vccvoltage level, which is typically +5V DC. As another example, a variety of semiconductor devices are packaged in the industry standard TO-220 package, which includes a tab maintained at a positive voltage level in operation.

FIG. 2depicts a plan view of a PCB10according to the present invention, with positive voltage level power plane layer24as the uppermost layer. Two components,26and28, are mounted on the positive voltage level power plane23. Component26represents a laser diode collimator, as discussed above. The collimator26is mounted directly to the positive voltage level power plane23, forming electrical connectivity therewith (other connections to collimator26not shown). Component28is a representative integrated circuit, which may comprise any of a broad variety of electronic components. The positive power supply voltage input pin30of component28is connected by a short signal trace directly to the positive voltage level power plane23. Other I/O pins of the component28are connected by short signal traces32to vias34, which connect to signal traces18,20on internal signal trace layers12,14(or alternatively, connect to other internal power plane or ground plane layers). A “keep-out” region36is formed on either side of the component28position, to provide space for the short signal traces32and vias34necessary to route signals to the component28. Note that the central region of component28, i.e., the surface below the component28when it is mounted on the PCB10, is filled with contiguous positive voltage level power plane23. This maximizes the surface area of the positive voltage level power plane23, and hence maximizes its effectiveness in suppressing electromagnetic emissions.

The placement of positive voltage level power planes24,29at the outermost layers of a printed circuit board10improves EMC performance of the PCB10by suppressing the emission of electromagnetic energy from the upper and lower surface. According to the present invention, additional suppression and shielding of electromagnetic energy from the edges of PBC10is obtained through the use of vias34connecting both positive voltage level power planes23,27, and circumscribing at least high-frequency signal traces18,20. As depicted inFIG. 2, a “fence” of vias34extends around the periphery of the positive voltage level power plane23, thus shielding all signal traces18,20routed on internal signal trace layers12,14within the fenced-in region. While this configuration is generally preferred for maximum electromagnetic shielding, the via34fence need not be provided at the periphery of the positive voltage level power plane23. Alternatively, a via34fence may be constructed around only that portion of the PCB10containing high-frequency signal traces18,20. Additional vias34, generously located throughout the area of positive voltage level power plane23, ensure uniformity of voltage levels between power planes23and27, thus enhancing electromagnetic shielding.

In order to provide sufficient attenuation, the spacing of the vias34must be controlled. As is well known in the art, the larger the gap between the conductors shielding electromagnetic energy, the more efficient a radiator is created. For sufficient attenuation, the gap between vias34is preferably no greater than one-half of a wavelength of the electromagnetic energy within the dielectric of PCB10, at the maximum frequency of signal traces18,20. More preferably, the maximum gap between vias34is no greater than one-tenth of a wavelength. In calculating the wavelength, the effects of the material forming dielectric layers22,25must be considered. The wavelength (in meters) of an electromagnetic wave in a homogeneous, non-magnetic medium is given by:λ=1/μ0⁢ɛ0⁢ɛrf≈300ɛr⁢f

Where λ is the wavelength in meters, ∈ris the relative dielectric constant of the PCB10dielectric and f is the frequency in MHz. Assuming a maximum spacing of one-tenth wavelength, the vias34comprising the fence should have a spacing l (in mills) no greater thanl=1.1811×103ɛr⁢f

In many applications, it is necessary or desirable to connect one PCB10to another, or to other electrical devices, through cables. This is typically accomplished by providing a cable connector on the PCB10, such as the connector44depicted inFIG. 2. One or more pins of the connector44are typically dedicated to ground and used to terminate the conductors tied to ground on both PCBs10. In many cases, one of these connector44ground pins is also used to terminate the shield of the cable used to interconnect the PCBs10. In this case, it is desirable to maintain a section of the uppermost layer at the signal ground voltage level, to minimize the risk of a short circuit between the cable shield and the connector44or the PCB10.FIG. 2depicts a ground voltage level power plane40formed on the uppermost surface of the PCB10(i.e., as part of the positive voltage level power plane layer24), adjacent to but separate from the positive voltage level power plane23, forming a gap42therebetween. The width of the gap42is sufficient to minimize the risk of a short circuit, given production tolerances and similar considerations. Note that while the power plane area40is presented by way of example as being maintained at a ground voltage level, the present invention is not so limited. In general, the power plane area40may be maintained at any voltage level distinct from the positive voltage level power plane23, as necessary or desired.

Whenever multiple power planes23,40are co-located on the outer surface of PCB10, it is important that the different planes23,40be interconnected using a sufficient number of decoupling capacitors46, to avoid voltage spikes, ringing, and the like on signal traces18,20. According to the present invention, these decoupling capacitors46, spanning the gap42, are located proximate signal traces38crossing the gap42. The placement of decoupling capacitors46adjacent such signal traces38allow high-frequency currents flowing in the power plane areas23,40to return immediately adjacent to the signals38.

In another embodiment of the present invention, with particular utility in the case where currents in components26or28are sufficient to cause EMC problems, additional shielding is achieved by positioning a conductive shield (not shown) over the component26,28, and electrically connecting the shield to the positive voltage level power plane23. The connection may be made using surface mount, pin-through-hole, gasketing techniques, or the like, as known in the art. Preferably, the spacing of the connections between the shield and the positive voltage level power plane23is the same as or less than the spacing between “fence” vias34, as discussed above.

As used herein, the terms “upper,” “lower,” “over,” “under,” and the like, and derivations thereof, are used for convenience to distinguish one side of the PCB10of the present invention from the other, with reference to the orientations depicted inFIGS. 1 and 2. In general, which side of the PCB10of the present invention is considered the “top” or “bottom” in any given implementation is irrelevant.

Although the present invention has been described herein with respect to particular features, aspects and embodiments thereof, it will be apparent that numerous variations, modifications, and other embodiments are possible within the broad scope of the present invention, and accordingly, all variations, modifications and embodiments are to be regarded as being within the scope of the invention. The present embodiments are therefore to be construed in all aspects as illustrative and not restrictive and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.