SEMICONDUCTOR DEVICE AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

Provided are a semiconductor device and a semiconductor apparatus including the same, the semiconductor device including: a first electrode; a second electrode apart from the first electrode; a dielectric structure provided between the first electrode and the second electrode and including a dielectric layer including a metal oxide represented by MxOy; and a leakage current reducing layer including a metal oxide represented by Lay′M′y′Oz′.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0111205, filed on Aug. 23, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The disclosure relates to a semiconductor device and a semiconductor apparatus including the same.

2. Description of the Related Art

As electronic devices are down-scaled, the available space to be occupied by electronic components, such as semiconductor devices, in electronic devices has also been reduced. Accordingly, along with the reduction in size of an electronic component and/or semiconductor device, such as a capacitor, a reduction in thickness of a dielectric layer of the capacitor is also required. However, in this case, a large leakage current may occur through the dielectric layer of the capacitor, thereby making it difficult to drive the electronic component and/or semiconductor device.

SUMMARY

Provided are electronic components having a low leakage current and high capacitance, and semiconductor apparatuses including the same.

According to an aspect of an embodiment, an electronic component includes: a first electrode; a second electrode apart from the first electrode; and a dielectric structure between the first electrode and the second electrode, the dielectric structure including a dielectric layer including a metal oxide represented by MxOy, where M is at least one of Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu, and a leakage current reducing layer including a metal oxide represented by Lax′M′y′Oz′, where M′ is at least one of Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu).

The dielectric layer may include first and second dielectric layers, and the leakage current reducing layer may be between the first dielectric layer and the second dielectric layer.

The leakage current reducing layer may be between the first electrode and the dielectric layer.

The leakage current reducing layer may be between the second electrode and the dielectric layer.

A thickness of the leakage current reducing layer may be 0.1 Å or more and 4.5 Å or less.

A total thickness of the dielectric structure may be 50 Å or less.

The dielectric layer may have a single-layer structure or a multi-layer structure in which different materials are stacked.

The first and second electrodes may each independently include a metal, a metal nitride, a metal oxide, or a combination thereof.

One of the first and second electrodes may include a semiconductor material.

According to an aspect of another embodiment, a semiconductor apparatus includes: a field effect transistor; and a capacitor electrically connected to the field effect transistor. The capacitor includes a first electrode; a second electrode apart from the first electrode; a dielectric structure between the first electrode and the second electrode, the dielectric structure including a dielectric layer including a metal oxide represented by MxOy, where M is at least one of Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu, and a leakage current reducing layer including a metal oxide represented by Lax′M′y′Oz′, where M′ is at least one of Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu.

The field effect transistor may include a channel layer between a source and a drain; a dielectric layer on the channel layer; and a gate electrode on the dielectric layer.

The dielectric layer may include first and second dielectric layers, and the leakage current reducing layer may be between the first dielectric layer and the second dielectric layer.

The leakage current reducing layer may be between the dielectric layer and at least one of the first electrode or the second electrode.

A thickness of the leakage current reducing layer may be 0.1 Å or more and 4.5 Å or less.

A total thickness of the dielectric structure may be 50 Å or less.

The first and second electrodes may each independently include a metal, a metal nitride, a metal oxide, or a combination thereof.

According to an aspect of another embodiment, an electronic device includes the above-described semiconductor apparatus.

DETAILED DESCRIPTION

Reference will now be made in detail to some embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In the drawings, the sizes of constituent elements may be exaggerated for clarity. The embodiments described below are only examples, and thus, it should be understood that the embodiments may be modified in various forms. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the example embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

Hereinafter, an expression such as “above” or “on” may include not only the meaning of “immediately on/under/to the left/to the right in a contact manner”, but also the meaning of “on/under/to the left/to the right in a non-contact manner”. Additionally, device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, it will be understood that when a unit is referred to as “comprising” another element, it does not preclude the possibility that one or more other elements may exist or may be added.

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing tolerance (e.g., ±10%) around the stated numerical value. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes.

It will be understood that, although the terms “first,” “second,” “third”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to differentiate an element from another element, and the order and type of the elements are not limited thereto. Unless explicitly stated or contradicted to the order of operations constituting the method, these operations may be performed in an appropriate order and are not necessarily limited to the order described. In addition, the terms “-er”, “-or”, and “module” described in the specification mean units for processing at least one function and/or operation and can be implemented by hardware components, software components, and/or combinations thereof. For example, the processing units may include and/or be included in, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), and programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.

The connecting lines, or connectors shown in the various figures presented are intended to represent example functional relationships and/or physical or logical couplings between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may be present in a practical device.

The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate the inventive concepts, and does not pose a limitation on the scope of the inventive concepts unless otherwise claimed.

According to an aspect, an electronic component having a small leakage current and high capacitance may be provided.

FIG.1is a cross-sectional view illustrating an electronic100according to some example embodiments. The electronic component100shown inFIG.1may be semiconductor device and/or a capacitor.

Referring toFIG.1, first and second electrodes111and112are provided to be apart from each other, and first and second dielectric layers121and122are provided on the first and second electrodes111and112, respectively. For example, the first electrode111, the first dielectric121, the second dielectric122, and the second electrode may be sequentially stacked. In addition, a leakage current reducing layer130is provided between the first and second dielectric layers121and122.

The first electrode111, which may be referred to as a lower electrode, may be arranged on a substrate (not shown). The substrate may be a portion of a structure supporting the electronic component100(e.g., a capacitor) and/or a portion of a device connected to the electronic component100. The substrate may include a pattern of semiconductor material, a pattern of insulating material, and/or a pattern of conductive material. The substrate may include, for example, a substrate11′, a gate stack12, an interlayer insulating layer15, a contact structure20′, and/or a bit line structure13inFIGS.8and9to be described later below.

The substrate may include, for example, a semiconductor material such as at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), and/or the like, and/or the substrate may include, for example, an insulating material such as at least one of silicon oxide, silicon nitride, silicon oxynitride, and/or the like.

The second electrode112, which may be referred to as an upper electrode, may be arranged to face the first electrode111while being apart from each other. The first and second electrodes111and112may each independently include a conductive (and/or semiconductive) material, such as at least one of a metal, a metal nitride, a metal oxide, or a combination thereof. For example, the first and second electrodes111and112may each independently include a metal (such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), platinum (Pt), and/or the like), a conductive metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), cobalt nitride (CoN), tungsten nitride (WN), and/or the like), and/or a conductive metal oxide (such as platinum oxide (PtO), iridium oxide (IrO2), ruthenium oxide (RuO2), strontium ruthenium oxide (SrRuO3), barium strontium ruthenium oxide ((Ba,Sr)RuO3), calcium ruthenium oxide (CaRuO3), lanthanum strontium cobalt oxide ((La,Sr)CoO3), and/or the like).

For example, the first and second electrodes111and112may each independently include a metal nitride represented by MeMe′N, where Me is a metal element, Me′ is an element different from Me, and N is nitrogen. This metal nitride may include MN metal nitride doped with element M′.

The first and second electrodes111and112may each independently include a single material layer and/or have a structure in which a plurality of material layers are stacked. For example, the first and/or second electrodes111and112may be a single layer of titanium nitride (TiN) and/or of niobium nitride (NbN). Alternatively, the first and/or second electrodes111and112may have a structure in which at least a first electrode layer including titanium nitride (TiN) and a second electrode layer including niobium nitride (NbN) are stacked.

A first dielectric layer121is provided on a surface (e.g., an upper surface) of the first electrode111, and a second dielectric layer122is provided on a surface (e.g., a lower surface) of the second electrode112. The first and second dielectric layers121and122may include a dielectric material having paraelectric properties. For example, the first and second dielectric layers121and122may include a dielectric material having a dielectric constant of about 20 or more and/or 70 or less.

In some example embodiments, each of the first and second dielectric layers121and122may include a metal oxide represented by MxOy(x and y are natural numbers), wherein O is oxygen and M may be one metal element selected from Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb and/or Lu. The first and/or the second dielectric layers121and122may include dopants. The first and second dielectric layers121and122may include, but are not limited to, the same metal oxide. For example, the first and second dielectric layers121and122may include the same and/or different metal oxides. The first and second dielectric layers121and122may each independently have a single-layer structure including a single material layer or a multi-layer structure in which a plurality of material layers are stacked. The first and second dielectric layers may have the same and/or different thicknesses.

The leakage current reducing layer130may be provided between the first and second dielectric layers121and122. The leakage current reducing layer130may reduce a leakage current flowing inside the electronic component100(e.g., a capacitor). In some example embodiments, the leakage current reducing layer130may include a metal oxide represented by Lax′M′y′Oz′(x′, y′, z′ are natural numbers). M′ may be one metal element selected from Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb and/or Lu. Such metal oxides may have paraelectric properties. The M in first and/or second dielectric121and122and the M′ in the leakage current reducing layer130may be the same and/or different metal elements.

The leakage current reducing layer130may have a thickness of about 0.1 Å or more and/or 4.5 Å or less. A total thickness of the first and second dielectric layers121and122and the leakage current reducing layer130may be about 50 Å or less. In some example embodiments, the total thickness of the first and second dielectric layers121and122and the leakage current reducing layer130may be about 40 Å or more and/or 50 Å or less. However, the disclosure is not limited thereto.

In the electronic component100(e.g., a capacitor) according to some example embodiments, by providing the leakage current reducing layer130including a metal oxide represented by LaxMyOzbetween the first and second dielectric layers121and122, the capacitance may be increased, and a leakage current value may be decreased.

In the above description, a case in which the electronic component100is a capacitor having a metal-insulator-metal (MIM) structure in which both the first and second electrodes121and122include a conductive material has been described. However, the present embodiment is not limited thereto. For example, the electronic component100may be/or include a semiconductor device such as a capacitor having a metal-insulator-semiconductor (MIS) structure in which one of the first and second electrodes includes a conductive material and the other includes a semiconductor material.

FIGS.2and3show characteristics of a conventional electronic component including an AlxZryOzleakage current reducing layer and an electronic component according to some example embodiments including a LaxZryOzleakage current reducing layer. InFIGS.2and3, a capacitor having a MIM structure is used as the electronic component.

FIG.2is a view illustrating comparison results of capacitance measurements of the conventional electronic component including an AlxZryOzleakage current reducing layer and the electronic component, according to some example embodiments, including a LaxZryOzleakage current reducing layer. Referring toFIG.2, it can be seen that the capacitance of the electronic component according to the example embodiments is improved by about 10% compared to the conventional electronic component.

FIG.3is a view illustrating comparison results of measurement of leakage current values of a conventional electronic component including an AlxZryOzleakage current reducing layer and an electronic component, according to some example embodiments, including a LaxZryOzleakage current reducing layer. Referring toFIG.3, it can be seen that in the electronic component according to the example embodiments, a leakage current is reduced by about two times at a voltage of 1 V compared to the conventional electronic component.

FIG.4is a cross-sectional view illustrating an electronic component200according to some example embodiments. Hereinafter, different content from the above-described example embodiments will be mainly described.

Referring toFIG.4, the electronic component200includes the first and second electrodes111and112apart from each other, a dielectric layer220provided between the first and second electrodes111and112, and a leakage current reducing layer230provided between the first electrode111and the dielectric layer220. Because the first and second electrodes111and112have been described above, a description thereof will not be given herein.

The dielectric layer220is similar to the first and second dielectric layers121and122inFIG.1described above. For example, the dielectric layer220may include a metal oxide represented by MxOy(x and y are natural numbers). M may be one metal element selected from Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb and/or Lu. The dielectric layer220may have a single-layer structure including a single material layer or a multi-layer structure in which a plurality of material layers are stacked.

The leakage current reducing layer230may be provided between the first electrode111and the dielectric layer220. The leakage current reducing layer230may include a metal oxide represented by Lax′M′yOz′. M′ may be one metal element selected from Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb and/or Lu. Such metal oxides may have paraelectric properties.

The leakage current reducing layer230may have a thickness of about 0.1 Å or more and 4.5 Å or less. A total thickness of the dielectric layer220and the leakage current reducing layer230may be about 50 Å or less. For example, the total thickness of the dielectric layer220and the leakage current reducing layer230may be about 40 Å or more and/or 50 Å or less. However, the disclosure is not limited thereto. In the electronic component200, as in the above-described embodiment, the capacitance may be increased, and a leakage current value may be decreased.

FIG.5is a cross-sectional view illustrating an electronic component300according to some example embodiments.

Referring toFIG.5, the electronic component300includes the first and second electrodes112and112apart from each other, a dielectric layer320provided between the first and second electrodes111and112, and a leakage current reducing layer330provided between the second electrode112and the dielectric layer320. Because the first and second electrodes111and112, the dielectric layer320, and the leakage current reducing layer330may be substantially similar to the first and second electrodes111and112, the dielectric layer220, the leakage current reducing layer230, as described above, a description thereof will not be given herein.

According to another aspect, a semiconductor apparatus may be provided. The semiconductor apparatus may have a form in which a field effect transistor and a capacitor are electrically connected to each other, and the capacitor may be at least one of the aforementioned electronic component device100,200, or300. The semiconductor apparatus may have a memory characteristic, and may be, for example, DRAM. However, this is merely an example, the semiconductor apparatus is not limited thereto.

FIG.6is a view of a semiconductor apparatus D1according to an example embodiment.

Referring toFIG.6, the semiconductor apparatus D1may include a field effect transistor10and a capacitor400electrically connected to each other by the contact20. The field effect transistor10may include a substrate11including a channel11cand a gate electrode12barranged to face the channel11c. A dielectric layer12amay be provided between the substrate11and the gate electrode12b.

The substrate11may include a semiconductor material. The substrate11may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and/or indium phosphide (InP), and may be used after being modified into various forms such as silicon on insulator (SOI).

The substrate11may include a source11a, a drain11b, and a channel11celectrically connected to the source11aand the drain11b. The source11amay be electrically connected to or in contact with one side of the channel11c, and the drain11bmay be electrically connected to or in contact with the other side of the channel11c. For example, the channel11cmay be defined as a substrate area between the source11aand the drain11bin the substrate11.

The source11a, the drain11b, and/or the channel11cmay be each independently formed by implanting impurities into different areas of the substrate11, and in this case, the source11a, the channel11c, and the drain11bmay include a substrate material as a base material.

The source11aand the drain11bmay be formed of and/or include a conductive material. Each of the source11aand the drain11bmay include, for example, a metal, a metal compound, and/or a conductive polymer. The conductive material may be, for example, an electrode and/or electrode contact.

The channel11cmay be implemented as a material layer (thin film) (not shown) separate from the substrate11. In this case, for example, the channel11cmay include an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) material, a quantum dot, and/or an organic semiconductor, as well as a semiconductor material such as Si, Ge, SiGe, III-V, and/or the like. For example, the oxide semiconductor may include InGaZnO and/or the like, the2D material may include transition metal dichalcogenide (TMD) and/or graphene, and the quantum dot may include a colloidal quantum dot (QD), a nanocrystal structure, and/or the like.

The gate electrode12bmay be arranged on the substrate11to face the channel11cwhile being apart from the substrate11. The gate electrode12bmay have, for example, conductivity of 1 Mohm/square or less. The gate electrode12bmay include a conductive material such as a metal, metal nitride, metal carbide, and/or polysilicon. For example, the metal may include aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and/or tantalum (Ta), and the metal nitride film may include a titanium nitride film (TiN film), and/or a tantalum nitride film (TaN film). The metal carbide may be a metal carbide doped with (or containing) aluminum and/or silicon, and may include TiAlC, TaAlC, TiSiC, and/or TaSiC as some specific examples.

The gate electrode12bmay have a structure in which a plurality of materials are stacked. For example, the gate electrode12bmay be and/or include a stacked structure of a metal nitride layer/metal layer such as TiN/AI, and/or a stacked structure of a metal nitride layer/metal carbide layer/metal layer such as TiN/TiAlC/W. The gate electrode12bmay include a TiN and/or Mo, and the above example may be used in variously modified forms.

A gate insulating layer12amay be further provided between the substrate11and the gate electrode12b. The gate insulating layer12amay include a paraelectric material or a high-k dielectric material. The gate insulating layer12amay include a material having a dielectric constant of about 20 to 70. For example, the gate insulating layer12amay include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, and/or the like, and/or a2D insulator such as hexagonal boron nitride (h-BN).

The capacitor400may be at least one of the electronic component100,200, and/or300according to the above-described embodiments.FIG.6shows an example case in which the capacitor400has the structure of the semiconductor device100shown inFIG.1. In this case, first and second dielectric layers421and422are provided between first and second electrodes411and412, and a leakage current reducing layer430including a metal oxide represented by Lax′M′yOz′is provided between the first and second dielectric layers421and422. However, this is only an example, and the capacitor400may have, as described above, the structure of the semiconductor devices200and/or300shown inFIG.4orFIG.5. Because the capacitor400has been described above, a detailed description thereof will not be given herein.

The field effect transistor10and the capacitor400may be electrically connected to each other by the contact20. For example, one of the first and second electrodes411and412of the capacitor400and one of the source and drain11aand11bof the field effect transistor10may be electrically connected to each other by the contact20. The contact20may include a conductive material, for example, tungsten, copper, aluminum, polysilicon, and/or the like. The arrangement of the capacitor400and the field effect transistor10may vary. For example, the capacitor400may be arranged on the substrate11or may be embedded in the substrate11.

FIG.7is a view of a semiconductor apparatus D10according to some example embodiments. The semiconductor apparatus D10shown inFIG.7has a structure in which a plurality of capacitors500and a plurality of field effect transistors are repeatedly arranged.

Referring toFIG.7, the semiconductor apparatus D10may include a field effect transistor having the substrate11′ including a source11a, a drain11b, a channel11c, and the gate stack12, the contact structure20′ arranged on the substrate11′ so as not to overlap the gate stack12, and a capacitor500arranged on the contact structure20′, and may further include the bit line structure13electrically connecting the plurality of field effect transistors.

FIG.7illustrates an example of the semiconductor apparatus D10in which both contact structures20′ and the capacitors500are repeatedly arranged in X and Y directions, but the semiconductor apparatus D10may be not limited thereto. For example, the contact structures20′ may be arranged in the X direction and the Y direction, and the capacitors500may be arranged in a hexagonal shape such as a honeycomb structure.

FIG.8is a cross-sectional view of the semiconductor apparatus D10taken along line A-A′ ofFIG.7.

Referring toFIG.8, the substrate11′ may have a shallow trench isolation (STI) structure including a device isolation layer14. The substrate11′ may be the same and/or substantially similar to the above-described substrate11. The device isolation layer14may be a single layer formed of one type of insulating layer, or a multilayer formed of a combination of two or more types of insulating layers. The device isolation layer14may include a device isolation trench14T in the substrate11′, and the device isolation trench14T may be filled with an insulating material. The insulating material may include, but is not limited to, fluoride silicate glass (FSG), undoped silicate glass (USG), boro-phospho-silicate glass (BPSG), phospho-silicate glass (PSG), flowable oxide (FOX), plasma enhanced tetra-ethyl-ortho-silicate (PE-TEOS), tonen silazene (TOSZ), and/or the like.

The substrate11′ may further include an active area AC defined by the device isolation layer14and a gate line trench12T that is parallel to an upper surface of the substrate11′ and is arranged to extend in the X direction. The active area AC may have a relatively long island shape having a short axis and a long axis. The long axis of the active area AC may be arranged in a K direction parallel to the upper surface of the substrate11′ as exemplarily illustrated inFIG.7. The gate line trench12T may be arranged to cross the active area AC at a certain depth from the upper surface of the substrate11′ or may be arranged in the active area AC. The gate line trench12T may also be arranged inside the device isolation trench14T, and the gate line trench12T inside the device isolation trench14T may have a lower bottom surface than the gate line trench12T of the active area AC.

A first source/drain11′aband a second source/drain11″abmay be arranged in an upper portion of the active area AC located at both sides of the gate line trench12T. The first source/drain11′aband/or the second source/drain11″abmay be the same and/or substantially similar to the above described source11aand/or drain11b.

The gate stack12may be arranged inside the gate line trench12T. For example, the gate stack12may include the gate insulating layer12a, the gate electrode12b, and/or a gate capping layer12csequentially arranged in the gate line trench12T. The gate insulating layer12aand the gate electrode12bmay refer to the above description, and the gate capping layer12cmay include silicon oxide, silicon oxynitride, and/or silicon nitride. The gate capping layer12cmay be arranged on the gate electrode12bto fill the remaining portion of the gate line trench12T.

The bit line structure13may be arranged on the first source/drain11′ab. The bit line structure13may be arranged to be parallel to the upper surface of the substrate11′ and extend in the Y direction. The bit line structure13is electrically connected to the first source/drain11′ab, and may include a bit line contact13a, a bit line13b, and a bit line capping layer13csequentially stacked on the substrate11′. For example, the bit line contact13amay include polysilicon, the bit line13bmay include a metal material, and the bit line capping layer13cmay include an insulating material such as silicon nitride or silicon oxynitride. InFIG.8, a case in which the bit line contact13ahas a bottom surface at the same level as the upper surface of the substrate11′ is exemplarily shown. However, the bit line contact13amay extend from the upper surface of the substrate11′ to the inside of a recess (not shown) formed to a certain depth, so that the bottom surface of the bit line contact13amay be lower than the upper surface of the substrate11′.

The bit line structure13may further include a bit line intermediate layer (not shown) between the bit line contact13aand the bit line13b. The bit line intermediate layer may include a metal silicide such as tungsten silicide, and/or a metal nitride such as tungsten nitride. In addition, a bit line spacer (not shown) may be further formed on a sidewall of the bit line structure13. The bit line spacer may have a single-layer structure or a multi-layer structure, and may include an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride. In addition, the bit line spacer may further include an air space (not shown).

The contact structure20′ may be arranged on the second source/drain11″ab. The contact structure20′ and the bit line structure13may be arranged on different sources/drains on the substrate11′. The contact structure20′ may have a structure in which a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) are sequentially stacked on the second source/drain11″ab. In addition, the contact structure20′ may further include a barrier layer (not shown) surrounding a side surface and a bottom surface of the upper contact pattern. For example, the lower contact pattern may include polysilicon, the upper contact pattern may include a metal material, and the barrier layer may include a conductive metal nitride.

The capacitor500may be electrically connected to the contact structure20′ and arranged on the substrate11′. The capacitor500may be one of the electronic components100,200, and/or300, and/or the capacitor400, according to the above-described embodiments.FIG.8shows an example case in which the capacitor500has the structure of the semiconductor device100shown inFIG.1.

For example, the capacitor500may include a first electrode511electrically connected to the contact structure20′, a second electrode512provided to be apart from the first electrode511, first and second dielectric layers521and522provided between the first and second electrodes511and512, a leakage current reducing layer530including a metal oxide represented by Lax′M′yOz′provided between the first and second dielectric layers521and522. However, this is only an example, and the capacitor may have the structure of the semiconductor devices200and300shown inFIG.4orFIG.5.

The interlayer insulating layer15may be further arranged between the capacitor500and the substrate11′. The interlayer insulating layer15may be arranged in a space between the capacitor500and the substrate11′ in which other structures are not arranged. For example, the interlayer insulating layer15may be arranged to cover wiring and/or electrode structures such as the bit line structure13on the substrate11′, the contact structure20′, and the gate stack12. For example, the interlayer insulating layer15may surround a wall of the contact structure20′. The interlayer insulating layer15may include a first interlayer insulating layer15asurrounding the bit line contact13aand a second interlayer insulating layer15bcovering side surfaces and/or upper surface of the bit line13band the bit line capping layer13c.

The first electrode511of the capacitor500may be arranged on the interlayer insulating layer15, specifically, on the second interlayer insulating layer15b. In addition, when a plurality of capacitors500are arranged, bottom surfaces of a plurality of first electrodes511may be separated by an etch stop layer16. For example, the etch stop layer16may include an opening16T, and a bottom surface of a first electrode100of the capacitor500may be arranged in the opening16T.

The first electrode511may have a cylinder shape with a closed bottom and/or a cup shape, as shown inFIG.8, and/or, in another example, as in a capacitor500′ illustrated inFIG.9, the first electrode511may have a pillar shape such as a cylinder, a square pillar, and/or a polygonal pillar extending in a vertical direction (Z direction). The capacitor500may further include a support portion (not shown) for preventing (e.g., mitigating the potential for) the first electrode511from being tilted and/or collapsed, and the support portion may be arranged on a sidewall of the first electrode511.

The above-described semiconductor apparatus D10may be manufactured with reference to a conventional method known in the art. For example, the semiconductor apparatus D10may be manufactured by including operations of i) to xvi) below.

i) Forming the device isolation trench14T in the substrate11′, and forming the device isolation layer14in the device isolation trench14T (Defining the active area AC of a substrate102by the device isolation layer14and/or the device isolation trench14T),

ii) Filling the inside of the isolation trench14T with an insulating material,

iii) Implanting impurity ions into the substrate11′ to form the first source/drain11′aband the second source/drain11″abin an upper area of the active area AC,

iv) Forming the gate line trench12T in the substrate11′,

v) Forming the gate insulating layer12a, the gate electrode12b, and the gate capping layer12cinside the gate line trench12T,

vi) Forming the first interlayer insulating layer15aon the substrate11′, and forming an opening (not shown) exposing an upper surface of the first source/drain11′ab,

vii) Forming the bit line structure13electrically connected to the first source/drain11′abon the opening of vi),

viii) Forming the second interlayer insulating layer15bcovering an upper surface and a side surface of the bit line structure13,

ix) Forming an opening (not shown) in the first and second interlayer insulating layers15aand15bto expose an upper surface of the second source/drain11″ab,

x) Forming the contact structure20′ electrically connected to the second source/drain11″abon the opening of ix),

x i) Forming the etch stop layer16and a mold layer (not shown) on the second interlayer insulating layer15band the contact structure20′,

x ii) Forming an opening (not shown) in the etch stop layer16and the mold layer (not shown) to expose an upper surface of the contact structure20′,

x iii) Forming the first electrode511to cover an inner wall (to cover bottom and side surfaces) of the opening of x ii),

x iv) Removing the mold layer (not shown),

x v) Forming the first dielectric layer521, a leakage current reducing layer530, and the second dielectric layer522on the first electrode511, and

x vi) Forming the second electrode512on the second dielectric layer522.

The type and/or order of each operation described above is not limited, and may be appropriately adjusted, and some may be omitted and/or added. In addition, a deposition process, a patterning process, an etching process, etc. known in the art may be used to form the components in each operation. For example, an etch-back process may be applied when forming an electrode. In operation v), the gate electrode12bmay be formed by forming a conductive layer on the gate insulating layer12aand then removing an upper portion of the conductive layer by a certain height through an etch-back process. In addition, in operation x iii), the first electrode511may also be manufactured in a structure including a plurality of first electrodes511by forming an electrode to cover all of an upper surface of the mold layer and the bottom and side surfaces of the opening and then removing a portion of the electrode on the upper surface of the mold layer by an etch-back process. As another example, a planarization process may be applied. For example, in operation v), the gate capping layer12cmay be formed by filling the remaining portion of the gate line trench12T with an insulating material and then planarizing the insulating material until the upper surface of the substrate11′ is exposed.

According to another aspect, the above-described electronic component100,200, and/or300and/or the semiconductor apparatuses D1and/or D10may be applied to various electronic devices. For example, the above-described electronic component100,200, and/or300and/or the semiconductor apparatuses D1and/or D10may be applied as logic devices or memory devices in various electronic devices. For example, the electronic component100,200, and/or300and the semiconductor apparatuses D1and D10may be used for arithmetic operations, program execution, and temporary data retention in electronic devices such as mobile devices, computers, laptops, sensors, network devices, or neuromorphic devices. A semiconductor device and a semiconductor apparatus according to embodiments may be useful for electronic devices in which the amount of data transmission is large and data transmission is continuously performed.

FIGS.10and11are conceptual diagrams schematically illustrating a device architecture applicable to an electronic device according to some example embodiments.

Referring toFIG.10, a device architecture1000may include a memory unit1010, an arithmetic logic unit (ALU)1020, and a control unit1030. The memory unit1010, the ALU1020, and the control unit1030may be electrically connected to each other. For example, the device architecture1000may be implemented as a single chip including the memory unit1010, the ALU1020, and the control unit1030. In more detail, the memory unit1010, the ALU1020, and the control unit1030may be interconnected by a metal line in an on-chip to directly communicate with each other. The memory unit1010, the ALU1020, and the control unit1030may be integrated monolithically on one substrate to configure one chip. An input/output device2000may be connected to the device architecture1000. In addition, the memory unit1010may include both a main memory and a cache memory. This device architecture1000may be an on-chip memory processing unit. The memory unit1010, the ALU1020, and/or the control unit1030may each independently include the aforementioned semiconductor device.

Referring toFIG.11, a cache memory1510, an ALU1520, and a control unit1530may constitute a central processing unit (CPU)1500, and the cache memory1510may be formed of static random access memory (SRAM). Separately from the CPU1500, a main memory1600and an auxiliary storage1700may be provided. The main memory1600may be dynamic random access memory (DRAM) and may include the aforementioned semiconductor device. In some cases, the device architecture may be implemented in a form in which computing unit devices and memory unit devices are adjacent to each other in a single chip without distinction of sub-units.

According to the above example embodiments, by providing a leakage current reducing layer including Lax′M′yOz′metal oxide in a dielectric layer, electronic component capable of increasing capacitance while reducing a leakage current may be realized. Such an electronic component may be applied to a semiconductor apparatus such as DRAM, and an electronic device such as a mobile device, a computer, a laptop, a sensor, a network device, and a neuromorphic device. Although some example embodiments have been described above, this is merely examples, and various modifications are possible therefrom by one of ordinary skill in the art.