Pre-decoder for dual power memory

A pre-decoder for providing a pulse signal to a dual power rail word line driver is provided. The pre-decoder includes a clock generator, an address latch and decoder, a level shifter and a processing unit. The clock generator generates a first signal according to a clock, wherein the first signal is powered by a first supply voltage. The address latch and decoder decodes an address to obtain a second signal according to the first signal. The level shifter generates a third signal according to the first signal, wherein the third signal is powered by a second supply voltage higher than the first supply voltage. The processing unit generates the pulse signal according to the second signal and the third signal, wherein the pulse signal is powered by the second supply voltage.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 61/638,233 filed Apr. 25, 2012, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a dual power memory, and more particularly to a pre-decoder of a dual power memory

2. Description of the Related Art

Since process technologies have been scaled down, such as deep sub-micron process technologies, the layout area of a system on chip (SOC) has greatly been decreased. However, memory device reliability (e.g. static random access memory (SRAM)) for SOCs with greatly decreased sizes is poor due to low supply voltages, threshold voltage mismatch caused by process variations and so on. For example, a threshold voltage mismatch of a memory device is about 35 mV/sigma for the 65 nm process. Moreover, such threshold voltage mismatch of a memory device is hard to estimate or simulate by a SPICE corner model, such as an SS (slow PMOS, slow NMOS), TT (typical PMOS, typical NMOS), FF (fast PMOS, fast NMOS), SF, or FS model.

In general, a 10 Mbit memory or greater, is common in an SOC. If a memory device of the SOC is operated with low supply voltage, read/write failure occurs due to threshold voltage mismatch among the memory cells. Furthermore, defect density of read/write failure is increased when supply voltage is decreased.

FIG. 1shows a schematic diagram of an SRAM110, wherein the SRAM110is implemented in an integrated circuit100. The integrated circuit100further comprises a random logic120which is powered by a supply voltage VDD. The SRAM110comprises a memory array111with a plurality of memory cells, a level shifter112, a word line (WL) decoder113for decoding the address signals to obtain the predecode signals, a control unit114for controlling the read/write operations, and an input/output (I/O) unit115for receiving and transmitting data between the SRAM110and the random logic120. Note that there could be an address, clock, and read/write control signals running between the control unit114and the random logic120. In order to avoid read/write failure for the SRAM110, the memory array111is powered by a supply voltage CVDD which is higher than the supply voltage VDD. The level shifter112is disposed between the word line decoder113and the memory array111, which is used to change the voltage levels of signals generated by the word line decoder113from the supply voltage VDD level to the supply voltage CVDD level, so as to drive the memory array111.

FIG. 2shows a word line driver array200with a plurality of dual power rail drivers, wherein the word line driver array200is coupled between a word line decoder202powered by the supply voltage VDD and a memory array204powered by the supply voltage CVDD. The word line decoder202provides a pulse signal XPC indicating that one section of the SRAM corresponding to the address signals has been selected. The word line decoder202further provides a plurality of predecode signals (ex. predecode[0], predecode[1], predecode[2] etc.) to the word line driver array200according to the address signals ADD. Each dual power rail driver of the word line driver array200generates a word line signal according to the corresponding predecode signal and the pulse signal XPC. For example, when the pulse signal XPC is asserted, the driver210generates a word line signal WL[0] according to the predecode signal predecode[0], the driver220generates a word line signal WL[1] according to the predecode signal predecode[1], the driver230generates a word line signal WL[2] according to the predecode signal predecode[2] and so on. In the word line driver array200, each word line driver has a level shifter, such as a level shifter212of the driver210, a level shifter222of the driver220or a level shifter232of the driver230, wherein each level shifter is disposed in data transmission path. Therefore, layout area and extra gate-delay in the critical timing path are increased, thus slowing access of the memory array.

FIG. 3shows another word line driver array300with a plurality of dual power rail drivers, wherein the word line driver array300is coupled between a word line decoder302powered by the supply voltage VDD and a memory array304powered by the supply voltage CVDD. Compared with the word line driver array200ofFIG. 2, no level shifter exists in the data transmission path for each word line driver in the word line driver array300, thereby the layout area of the word line driver array300is smaller than that of the word line driver array200ofFIG. 2. However, a level shifter306disposed in the pulse signal transmission path is used to change the voltage levels of a pulse signal XPC generated by the word line decoder302from the supply voltage VDD level to the supply voltage CVDD level. Therefore, an extra gate-delay in the critical timing path is increased, thus slowing access of the memory array.

FIG. 4shows a schematic diagram illustrating a conventional single power rail pre-decoder400. The pre-decoder400can be implemented in the word line decoder202ofFIG. 2. The pre-decoder400comprises an address latch and decoder410, a clock generator420, a NAND gate430and an inverter440. The clock generator420generates a pulse signal WLP according to a clock CLK, and provides the pulse signal WLP to the address latch and decoder410and the NAND gate430. The address latch and decoder410generates a decoded signal PRC according to an address ADD and the pulse signal WLP. The NAND gate430generates a signal XPCB according to the decoded signal PRC and the pulse signal WLP. The inverter440inverts the signal XPCB to obtain a signal XPC. The signal XPC is a pulse signal indicating that one section of a memory array corresponding to the address ADD has been selected.

FIG. 5shows a waveform illustrating the ideal timing considerations of a memory array. A setup time T_setup is the minimum amount of time that the address ADD should be held steady before a rising edge of the clock CLK, so that the address ADD is reliably sampled by the clock CLK. An access time T_access is the time that it takes a memory array to deliver the data DO in response to the address ADD. Therefore, according to the setup time T_setup and the access time T_access, a minimum clock period T_clock is given by the following equation:
T_clock=T_setup+T_access.

FIG. 6shows a schematic diagram illustrating a conventional dual power rail pre-decoder500. The pre-decoder500can be implemented in the word line decoder302ofFIG. 3. Compared with the pre-decoder400ofFIG. 4, the pre-decoder500further comprises a level shifter510, wherein the level shifter510receives the signal XPC powered by the supply voltage VDD to provide a signal XPC_LS which is powered by the supply voltage CVDD. Therefore, an extra gate-delay T_level_shifter is increased for the access time T_access, thereby the clock period T_clock is also increased. The increased clock period T_clock is given by the following equation:

Therefore, it is desired to insert a level shifter in a critical timing path without affecting the clock period T_clock.

BRIEF SUMMARY OF THE INVENTION

A memory device and a pre-decoder thereof are provided. An embodiment of a pre-decoder for providing a pulse signal to a dual power rail word line driver is provided. The pre-decoder comprises: a clock generator, generating a first signal according to a clock, wherein the first signal is powered by a first supply voltage; an address latch and decoder, decoding an address to obtain a second signal according to the first signal; a level shifter, generating a third signal according to the first signal, wherein the third signal is powered by a second supply voltage higher than the first supply voltage; and a processing unit, generating the pulse signal according to the second signal and the third signal, wherein the pulse signal is powered by the second supply voltage.

Furthermore, an embodiment of a memory device is provided. The memory device comprises: a memory array; a word line decoder, decoding an address to obtain a plurality of predecode signals; a plurality of dual power rail word line drivers, each driving a word line of the memory array according to the individual predecode signal; a common transistor, having a gate for receiving a pulse signal, a first terminal coupled to a ground and a second terminal coupled to the dual power rail word line drivers; and a pre-decoder, providing the pulse signal according to the address and a clock. The pre-decoder comprises: a clock generator, generating a first signal according to the clock, wherein the first signal is powered by a first supply voltage; an address latch and decoder, decoding the address to obtain a second signal according to the first signal; a level shifter, generating a third signal according to the first signal, wherein the third signal is powered by a second supply voltage higher than the first supply voltage; and a processing unit, generating the pulse signal according to the second signal and the third signal, wherein the pulse signal is powered by the second supply voltage.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 7shows a dual power memory device600according to an embodiment of the invention. The memory device600is implemented in a system on chip (SOC). The memory device600comprises a plurality of dual power rail word line drivers6100-610n, a common NMOS transistor N2, a word line (WL) decoder620and a memory array640, wherein the dual power rail word line drivers6100-610nshare the same NMOS transistor N2. According to the address ADD and clock CLK, the word line decoder620provides a plurality of predecode signals predecode[0]-predecode[n] to the dual power rail word line drivers6100-610n, respectively and the Word line decoder620may use a pre-decoder630to provide a pulse signal XPC_LS to a gate of the common NMOS transistor N2, wherein the predecode signals predecode[0]-predecode[n] are powered by a supply voltage VDD and the pulse signal XPC_LS is power by a supply voltage CVDD higher than the supply voltage VDD. Each of the dual power rail word line drivers6100-610nreceives an individual predecode signal from the word line decoder620and provides an individual word line signal to drive the corresponding word line of the memory array640. Taking the dual power rail word line driver6100as an example, the dual power rail word line driver6100receives a predecode signal predecode[0] from the word line decoder620and provides a word line signal WL[0] to drive the corresponding word line of the memory array640. Furthermore, each of the dual power rail word line drivers6100-610ncomprises an inverter612, a signal buffering unit614, an NMOS transistor N1and a PMOS transistor P1. The signal buffering unit614is coupled between the corresponding word line and a node618, wherein the signal buffering unit614comprises a PMOS transistor P2and an inverter616. The signal buffering unit614could be a latch, half latch, buffer, or any component capable of buffering or driving signal. The PMOS transistor P2is coupled between the supply voltage CVDD and the node618, and has a gate coupled to the corresponding word line. The inverter420is coupled between the corresponding word line and the node618, which is powered by the supply voltage CVDD. In the embodiment, the signal buffering unit614is used as an example for description, and does not limit the invention. The PMOS transistor P1is coupled between the supply voltage CVDD and the node618, wherein the PMOS transistor P1has a gate for receiving the pulse signal XPC_LS. The pulse signal XPC_LS is a global pulse signal for a word line decoding operation. Due to that the pulse signal WLP_LS being powered by the supply voltage CVDD, the PMOS transistor P1can be completely turned off by the pulse signal XPC_LS. The NMOS transistor N1is coupled between the node618and the common NMOS transistor N2, and has a gate coupled to the inverter612. The inverter612receives the corresponding predecode signal from the Word line decoder620and controls the NMOS transistor N1to turn on or off according to a signal opposite to the corresponding predecode signal, wherein the inverter612is powered by the supply voltage VDD. The common NMOS transistor N2is coupled between the NMOS transistors N1and a ground GND, and has a gate for receiving the pulse signal XPC_LS. In one embodiment, the pre-decoder630may be implemented in the other circuits on the outside of the word line decoder620.

FIG. 8shows a pre-decoder700according to an embodiment of the invention. The pre-decoder700comprises an address latch and decoder710, a clock generator720, a level shifter730and a processing unit740. The address latch and decoder710generates a decoded signal PRC according to an address ADD and a pulse signal WLP. The clock generator720generates the pulse signal WLP according to a clock CLK, and provides the pulse signal WLP to the address latch and decoder710and the level shifter730. The level shifter730received the pulse signal WLP powered by the supply voltage VDD to provide a pulse signal WLP_LS powered by the supply voltage CVDD. The processing unit740comprises a signal buffering unit750, a pull-up unit780and a pull-down unit790, wherein the processing unit740generates the pulse signal XPC_LS according to the decoded signal PRC from the address latch and decoder710and the pulse signal WLP_LS from the level shifter730. In the embodiment, the processing unit740functions as an AND logic. The signal buffering unit750is coupled between a node760and the gate of the common NMOS transistor N2ofFIG. 7. The signal buffering unit750comprises an inverter770, wherein the inverter770is powered by the supply voltage CVDD. In one embodiment, the signal buffering unit750further comprises a PMOS transistor P4, wherein the PMOS transistor P4is coupled between the supply voltage CVDD and the node760and has a gate coupled to an output of the inverter770. The pull-up unit780comprises a PMOS transistor P3coupled between the supply voltage CVDD and the node760, wherein the PMOS transistor P3has a gate for receiving the pulse signal WLP_LS. Due to that the pulse signal WLP_LS being powered by the supply voltage CVDD, the PMOS transistor P3can be completely turned off by the pulse signal WLP_LS. The pull-down unit790is coupled between the node760and the ground GND, which comprises two NMOS transistor N3and N4connected in series. The NMOS transistor N3is coupled between the node760and the NMOS transistor N4, and has a gate for receiving the decoded signal PRC from the address latch and decoder710. The NMOS transistor N4is coupled between the NMOS transistor N3and the ground GND, and has a gate for receiving the pulse signal WLP_LS. In this embodiment, the level shifter730is disposed on a critical timing path, thus decreasing a setup time T_setup and increasing an access time T_access. Therefore, a minimum clock period T_clock is obtained without timing impact, as shown in the following equation:

FIG. 9shows a clock generator800according to an embodiment of the invention. The clock generator800may provide a variable pulse signal WLP to the level shifter730and the address latch and decoder710ofFIG. 8, to finely tune the access time T_access and the setup time T_setup. The clock generator800comprises a control unit810for delaying timing of the pulse signal WLP and an adjustment unit820for adjusting a duty cycle of the pulse signal WLP. The control unit810comprises two switches830and840, a delay unit860and an inverter850. The switch830is controlled by a select signal SEL, and the switch840is controlled by a select signal SELB complementary to the select signal SEL. Therefore, the switch830is turned on when the switch840is turned off, and switch830is turned off when the switch840is turned on. The inverter850generates the select signal SELB according to the select signal SEL. The delay unit860is coupled between the switch830and the switch840, wherein the delay unit860comprises two inverters862and864connected in series. In one embodiment, the delay unit860may be a level shifter, a delay cell or a buffer cell. Furthermore, the adjustment unit820receives an internal clock signal CLKin provided by the control unit810to generate a pulse signal WLP, wherein the pulse signal WLP and the clock signal CLKin may have differential duty cycles.FIG. 10shows a waveform diagram illustrating the signals of the clock generator800ofFIG. 9. Referring toFIG. 9andFIG. 10together, if the switch830is turned on and the switch840is turned off, the clock CLK may directly serve as the internal clock signal CLKin, and the adjustment unit820may provide the pulse signal WLP according to the internal clock signal CLKin, wherein the pulse signal WLP has a duty cycle appropriate for memory access. If the switch840is turned on and the switch830is turned off, the clock CLK may be delayed to obtain the internal clock signal CLKin, and the adjustment unit820may provide the pulse signal WLP according to the delayed internal clock signal CLKin. Similarly, the pulse signal WLP corresponding to the delayed internal clock signal CLKin has a duty cycle appropriate for memory access.