Circuits And Methods For Memory Built-In-Self-Tests

An integrated circuit includes memory circuits, a selector circuit, a bus coupled to the selector circuit, and a controller circuit. The controller circuit provides test signals from the controller circuit through the bus to the selector circuit for transmission to the memory circuits during a memory built-in-self-test mode. Each of the memory circuits can include a comparator circuit configurable to compare a read data bit read from one of the memory circuits to an expected data bit in the test signals to generate a sticky error bit during the memory built-in-self-test mode.

BACKGROUND

Configurable integrated circuits (ICs) can be configured by users to implement desired custom logic functions. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom circuit design. When the design process is complete, the computer-aided design tools generate an image containing configuration data bits. The configuration data bits are then loaded into configuration memory elements that configure configurable logic circuits in the integrated circuit to perform the functions of the custom circuit design.

DETAILED DESCRIPTION

In a system-on-chip (SoC), hardened memory built-in-self-test (MBIST) controllers are used to test memory blocks. To achieve at-speed testing, one MBIST controller using one or a few memory macros is usually implemented. MBIST area is costly when there are many memory macros in the SoC.

In a field programmable gate array (FPGA), memory blocks are scattered around the integrated circuit (IC) die. As an example, a large FPGA IC can have thousands of memory blocks. Multiple MBIST controllers may be used to test an FPGA memory array.

For functional safety (FUSA) automotive requirements that require memory arrays in an FPGA to be tested during power on, a custom configurable MBIST controller is built in a custom circuit design for the FPGA. However, using a configurable MBIST controller is time consuming. Also, it is difficult to meet at-speed frequency testing requirements using a configurable MBIST controller. In addition, a configurable MBIST controller consumes resources on an FPGA for both manufacturing tests and the custom circuit design.

According to some examples disclosed herein, techniques are provided for using a single memory built-in-self-test (MBIST) controller circuit to test many memory circuits in an integrated circuit (IC) concurrently. According to these examples, an IC includes an MBIST controller circuit that generates MBIST signals during an MBIST mode. The MBIST signals are sent through a high-speed pipelined network-on-chip (NOC) bus for transmission to the memory circuits in the IC when the MBIST mode is enabled. The MBIST mode is enabled by test control signals. Comparators and storage circuitry in the memory circuits generate and capture sticky error bits during the MIBIST mode and shift out the sticky error bits to output pads of the IC. The NOC can also be used to transmit configuration bits (i.e., configuration data bits) to configurable logic circuits and/or to the memory circuits in the IC during a configuration mode of the IC. Using the NOC for transmission of both configuration bits and MBIST signals reduces circuit area usage and cost in the IC.

The techniques disclosed herein can reduce manufacturing test development efforts and provide at-speed frequency testing of memory circuits in an IC. In addition, the techniques disclosed herein can reduce design effort for an MBIST controller used to test memory circuits during power up of the IC. Also, the techniques disclosed herein can reduce circuit resources used for an MBIST controller and can make more resources in an IC available for other uses.

Throughout the specification, and in the claims, the terms “connected” and “connection” mean a direct electrical connection between the circuits that are connected, without any intermediary devices. The terms “coupled” and “coupling” mean either a direct electrical connection between circuits or an indirect electrical connection through one or more passive or active intermediary devices that allows the transfer of information between circuits. The term “circuit” may mean one or more passive and/or active electrical components that are arranged to cooperate with one another to provide a desired function.

This disclosure discusses integrated circuit devices, including configurable (programmable) integrated circuits, such as field programmable gate arrays (FPGAs) and programmable logic devices. As discussed herein, an integrated circuit (IC) can include hard logic and/or soft logic. The circuits in an integrated circuit device (e.g., in a configurable IC) that are configurable by an end user are referred to as “soft logic.” “Hard logic” generally refers to circuits in an integrated circuit device that have substantially less configurable features than soft logic or no configurable features.

FIG.1is a diagram that illustrates an example of a portion of an integrated circuit (IC)100that can test memory circuits in the IC using a memory built-in-self-test (MBIST) controller circuit and a network-on-chip (NOC) bus. Integrated circuit (IC)100includes sectors101of configurable logic and memory circuits, a network-on-chip (NOC) bus105, and a local sector manager (LSM) control circuit102(also referred to herein as control circuit102).

Four sectors101A,101B,101C, and101D are shown inFIG.1merely as an example. According to various examples, IC100can include any number of sectors101. Each of the sectors101in IC100includes a selector (SL) circuit120, memory circuits111, pipeline register circuits112, and memory busses113coupled as shown in Figure (FIG.1. Each of the memory circuits111can, for example, include a memory array having rows and columns of memory cells. The control circuit102includes a multiplexer circuit103and a memory built-in-self-test (MBIST) controller circuit104.

IC100can be any type of integrated circuit, such as a configurable IC (e.g., a field programmable gate array (FPGA) or programmable logic device), a microprocessor IC, a graphics processing unit IC, a memory IC, an application specific IC, a transceiver IC, etc. In the examples described below, IC100is a configurable IC, such as an FPGA or programmable logic device (PLD).

According to the example in which IC100is a configurable IC, control circuit102can be used for controlling configuration bits in a configuration mode of the IC100. In the configuration mode of the IC100, multiplexer circuit103is configured by select signal MBEN to transmit configuration bits CONF to NOC bus105. NOC bus105transmits the configuration bits CONF from multiplexer circuit103to the selector circuits120in the sectors101A,101B,101C,101D, etc. The selector circuits120then transmit the configuration bits (e.g., decoded configuration bits) to the memory circuits111and the configurable logic circuits (not shown inFIG.1) in the respective sectors101. The memory circuits111and the configurable logic circuits are then configured by the configuration bits.

After the configuration mode of IC100is completed, IC100enters a memory built-in-self-test (MBIST) mode. In the MBIST mode, the MBIST controller circuit104is enabled (e.g., by Joint Test Action Group (JTAG) signals) to generate MBIST signals MBS. Also, during the MBIST mode, the state of the select signal MBEN is changed to cause the multiplexer circuit103to transmit the MBIST signals MBS to the NOC bus105. The NOC bus105transmits the MBIST signals MBS from multiplexer circuit103to the selector circuits120in the sectors101A,101B,101C,101D, etc. The selector circuits120then transmit the MBIST signals MBS through busses113and through the pipeline register circuits112to the memory circuits111in the respective sectors101. Thus, the NOC bus105and the busses113are overridden by the MBIST signals MBS during the MBIST mode. The MBIST signals MBS can be transmitted through busses113and pipeline register circuits112to every memory circuit111in a sector. By using the NOC bus105for transmitting both configuration bits and the MBIST signals, additional routing paths are not needed in IC100to transmit the MBIST signals to the memory circuits111, which reduces IC die area and reduces the complexity of signal routing.

FIG.2is a diagram that illustrates further details of circuits in a sector101and the control circuit102in IC100.FIG.2illustrates examples of circuits that can be in each of the sectors101A,101B,101C,101D, etc. in IC100. As shown inFIG.2, each sector101can include memory circuits111, pipeline register circuits112, memory busses113, configurable logic (CL) circuits114, and multiplexer (MUX) circuits115that are coupled as shown inFIG.2. The selector circuit120includes a decoder circuit121, two multiplexer circuits122and123, and a Joint Test Action Group (JTAG) Test Access Port (TAP) controller circuit124. InFIG.2, the control circuit102also includes a JTAG TAP controller circuit106that generates and receives JTAG signals.

In the configuration mode of the IC100, multiplexer circuit103is configured to transmit configuration bits through NOC bus105to the decoder circuit121in selector circuit120. The decoder circuit121decodes the configuration bits to generate decoded configuration bits DCF. In configuration mode, the multiplexer circuits122-123are configured to provide the decoded configuration bits DCF through busses113(and other routing) to the memory circuits111and the configurable logic circuits114on each side of the selector circuit120. The memory circuits111and the configurable logic circuits114are then configured by the decoded configuration bits.

In IC100, JTAG signals from JTAG pads (i.e., external terminals of the IC) are routed to every sector101in IC100. The JTAG signals can include, for example, Test Clock (TCK), Test Mode Select (TMS), Test Data In (TDI), and Test Data Out (TDO). The JTAG signals are then daisy chained from one sector101to another sector101. Within a sector101, the JTAG TAP controller circuit124generates internal Joint Test Action Group (IJTAG) signals IJS using the JTAG signals.

The IJTAG signals IJS set the MBIST mode. For example, the IJTAG signals IJS can configure multiplexer circuit103to transmit the MBIST signals MBS from MBIST controller circuit104to NOC bus105during the MBIST mode. Also, the IJTAG signals IJS can configure the multiplexer circuits122-123to transmit the MBIST signals MBS from NOC bus105to memory circuits111through busses113during MBIST mode.

The IJTAG signals IJS are transmitted from the JTAG TAP controller circuit124to every memory circuit111in the sector101through the multiplexer circuits115during the MBIST mode. In addition, IJTAG signals IJS can be transmitted from the memory circuits111through multiplexer circuits115to the JTAG TAP controller circuit124in MBIST mode. For example, the IJTAG signals IJS can carry out sticky error bits from comparator circuits in each memory circuit111through JTAG TAP controller circuit124to the JTAG pads to perform a pass/fail determination for a memory test of each memory circuit111.

FIG.3is a diagram that illustrates examples of a memory core circuit301and comparator circuits302that can be in each of the memory circuits111in the sectors101of integrated circuit (IC)100. In the example ofFIG.3, memory core circuit301and comparator circuits302are in every memory circuit111in IC100. The memory core circuit301can, for example, include a memory array of memory storage cells.

During MBIST mode, MBIST signals, including signals MWDATA (including write data), MWE (write enable), MRE (read enable), MADR (address signals), MCLK (MBIST clock signal), JTSI (JTAG input signals), and BCLK (built-in-self-test clock signal) from bus113are provided to memory core circuit301. The MBIST signals MWDATA, MWE, MRE, MADR, MCLK, JTSI, and BCLK overwrite the functional signals in memory core circuit301to perform read and write operations to the memory array in memory core circuit301when the MBIST mode is enabled by the IJTAG signals. The signals JTSI are transmitted through a bus via multiplexer circuits115to memory circuit111during the MBIST mode. The write data indicated by signals MWDATA is written to the memory array in memory core circuit301during a write operation. During a read operation in MBIST mode, the memory core circuit301reads the write data that was written during the write operation and outputs this data as read data in signals MRDATA.

The memory core circuit301outputs JTAG signals JTOS1and the signals MRDATA that indicate the read data read from memory core circuit301during the read operation. Comparator circuits302compare the read data indicated by signals MRDATA with expected data indicated by signals MEXD to generate sticky error bits in response to an MBIST comparator enable signal MCEN. The expected data indicated by signals MEXD is generated by MBIST controller circuit104. The sticky error bits generated by comparator circuits302may indicate mismatch errors between the read data indicated by signals MRDATA and the expected data indicated by signals MEXD.

The sticky error bits are output by the comparator circuits302as IJTAG signals JTOS2. The sticky error bits can be shifted out through multiplexer circuits115and JTAG TAP controller circuit124to the JTAG output pads to determine whether a memory test of the memory circuit111has passed or failed. In some examples, all of the memory circuits111receive MBIST signals concurrently. Also, the MBIST mode can be enabled independently in each memory circuit111, so that all of the memory circuits111or a subgroup of the memory circuits111can be selected for testing. For custom circuit designs in an FPGA, this feature provides an option to test all of the memory circuits111or only selected memory circuits111that are used in the custom circuit design to be tested.

FIG.4is a diagram that illustrates details of examples of circuits that can be in each of the memory circuits111to enable a memory built-in-self-test (MBIST) during MBIST mode. In the example ofFIG.4, each memory circuit111includes 6 multiplexer circuits401-406, 4 D flip-flop circuits411-414, and a comparator circuit420that are coupled as shown inFIG.4. IJTAG signals IJCK (clock signal), IJTDI (data in), IJCDR (capture data register), IJUDR (update data register), and IJSDR (shift data register) are provided to the memory circuit111as shown inFIG.4. In addition, signals MRDATA, MCEN, MEXD, and BCLK are provided to comparator circuit420.

In order to enable the MBIST mode, control signal IJSDR is set to a digital value of 1 and control signal IJUDR is set to a digital value of 0 to shift a digital 1 bit from data in signal IJTDI through multiplexer402to flip-flop circuit411. Then, control signal IJSDR is set to a digital value of 0 and control signal IJUDR is set to a digital value of 1 to shift to shift the digital 1 bit from flip-flop circuit411through multiplexer circuit403to flip-flop circuit412in output signal BISTON. When signal BISTON is a digital 1, the IC100operates in the MBIST mode, and the multiplexer circuits103and122-123are configured to transmit the MBIST signals through NOC bus105and busses113to memory circuits111.

The comparator circuit420compares one of the read data bits indicated by signals MRDATA with a corresponding expected data bit indicated by signals MEXD when the comparator circuit420is enabled by enable signal MCEN to generate a sticky error bit SKEB at an output. The comparator circuit420can also include a storage circuit that captures the sticky error bit SKEB at the output in response to clock signal BCLK. The comparator circuit420causes the sticky error bit SKEB to indicate whether the read data bit indicated by signals MRDATA matches the corresponding expected data bit indicated by signals MEXD. The comparator circuit420causes the sticky error bit SKEB to indicate any mismatch between the expected data bit and the read data bit from the memory core circuit301during a built-in-self-test.

The sticky error bit SKEB is provided to the 0 input of multiplexer circuit406as shown inFIG.4. The sticky error bit SKEB can be shifted from comparator circuit420through the flip-flop circuits413-414to a JTAG output pad as is now described. In order to shift out the sticky error bit SKEB, control signals IJCDR, IJUDR, and IJSDR are set to digital values of 1, 0, and 0, respectively, to shift the sticky error bit SKEB from comparator circuit420through multiplexer406, flip-flop circuit414, multiplexer circuit404, multiplexer circuit405, and flip-flop circuit413as data output signal IJTDO. Thus, the sticky error bit SKEB is captured and shifted out through flip-flop circuits414and413as data output signal IJTDO (e.g., part of signals IJS), while the flip-flop circuits411and413are configured as a shift register. Subsequently, the sticky error bit SKEB is then directly shifted out to the JTAG output pad (TDO).

The process of testing memory circuits111in IC100can be summarized as follows. Through JTAG, the MBIST mode is enabled in the targeted memory circuits111to be tested. The MBIST mode is enabled in the selector circuits120for the sectors101in which the targeted memory circuits111reside. The MBIST mode is also enabled in MBIST controller circuit104. Then, a wait period begins for the MBIST testing time. After the MBIST tests have been performed in the targeted memory circuits111, an MBIST done status signal in MBIST controller circuit104is scanned out to confirm the MBIST tests are completed. Then, the sticky error bits generated by the targeted memory circuits111are shifted out through JTAG. The targeted memory circuits111are daisy chained to form a shift register, and the IJTAG sticky error bits are shifted out to the JTAG output pads. By calculating the shift out bit position, the pass/fail status of each targeted memory circuit111can be determined.

FIG.5illustrates an example of a configurable logic integrated circuit (IC)500that can include, for example, the circuitry disclosed herein with respect to any, some, or all ofFIGS.1,2,3, and/or4. As shown inFIG.5, the configurable logic integrated circuit (IC)500includes a two-dimensional array of configurable functional circuit blocks, including configurable logic array blocks (LABs)510and other functional circuit blocks, such as random access memory (RAM) blocks530and digital signal processing (DSP) blocks520. Functional blocks such as LABs510can include smaller programmable logic circuits (e.g., logic elements, logic blocks, or adaptive logic modules) that receive input signals and perform custom functions on the input signals to produce output signals. The configurable functional circuit blocks shown inFIG.5can, for example, be configured to perform the functions of any of the circuitry disclosed herein with respect toFIGS.1-4. For example, memory circuits111can be RAM blocks530.

In addition, programmable logic IC500can have input/output elements (IOEs)502for driving signals off of programmable logic IC500and for receiving signals from other devices. Input/output elements502can include parallel input/output circuitry, serial data transceiver circuitry, differential receiver and transmitter circuitry, or other circuitry used to connect one integrated circuit to another integrated circuit. As shown, input/output elements502can be located around the periphery of the chip. If desired, the programmable logic IC500can have input/output elements502arranged in different ways. For example, input/output elements502can form one or more columns, rows, or islands of input/output elements that may be located anywhere on the programmable logic IC500.

The programmable logic IC500can also include programmable interconnect circuitry in the form of vertical routing channels540(i.e., interconnects formed along a vertical axis of programmable logic IC500) and horizontal routing channels550(i.e., interconnects formed along a horizontal axis of programmable logic IC500), each routing channel including at least one conductor to route at least one signal.

Note that other routing topologies, besides the topology of the interconnect circuitry depicted inFIG.5, may be used. For example, the routing topology can include wires that travel diagonally or that travel horizontally and vertically along different parts of their extent as well as wires that are perpendicular to the device plane in the case of three dimensional integrated circuits. The driver of a wire can be located at a different point than one end of a wire.

Furthermore, it should be understood that embodiments disclosed herein with respect toFIGS.1-4can be implemented in any integrated circuit or electronic system. If desired, the functional blocks of such an integrated circuit can be arranged in more levels or layers in which multiple functional blocks are interconnected to form still larger blocks. Other device arrangements can use functional blocks that are not arranged in rows and columns.

Programmable logic IC500can contain programmable memory elements. Memory elements can be loaded with configuration data using input/output elements (IOEs)502. Once loaded, the memory elements each provide a corresponding static control signal that controls the operation of an associated configurable functional block (e.g., LABs510, DSP blocks520, RAM blocks530, or input/output elements502).

In a typical scenario, the outputs of the loaded memory elements are applied to the gates of metal-oxide-semiconductor field-effect transistors (MOSFETs) in a functional block to turn certain transistors on or off and thereby configure the logic in the functional block including the routing paths. Programmable logic circuit elements that can be controlled in this way include multiplexers (e.g., multiplexers used for forming routing paths in interconnect circuits), look-up tables, logic arrays, AND, OR, XOR, NAND, and NOR logic gates, pass gates, etc.

The programmable memory elements can be organized in a configuration memory array having rows and columns. A data register that spans across all columns and an address register that spans across all rows can receive configuration data. The configuration data can be shifted onto the data register. When the appropriate address register is asserted, the data register writes the configuration data to the configuration memory bits of the row that was designated by the address register.

In certain embodiments, programmable logic IC500can include configuration memory that is organized in sectors, whereby a sector can include the configuration RAM bits that specify the functions and/or interconnections of the subcomponents and wires in or crossing that sector. Each sector can include separate data and address registers.

The configurable logic IC ofFIG.5is merely one example of an IC that can be used with embodiments disclosed herein. The embodiments disclosed herein can be used with any suitable integrated circuit or system. For example, the embodiments disclosed herein can be used with numerous types of devices such as processor integrated circuits, central processing units, memory integrated circuits, graphics processing unit integrated circuits, application specific standard products (ASSPs), application specific integrated circuits (ASICs), and programmable logic integrated circuits. Examples of programmable logic integrated circuits include programmable arrays logic (PALs), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), just to name a few.

The integrated circuits disclosed in one or more embodiments herein can be part of a data processing system that includes one or more of the following components: a processor; memory; input/output circuitry; and peripheral devices. The data processing system can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application. The integrated circuits can be used to perform a variety of different logic functions.

In general, software and data for performing any of the functions disclosed herein can be stored in non-transitory computer readable storage media. Non-transitory computer readable storage media is tangible computer readable storage media that stores data and software for access at a later time, as opposed to media that only transmits propagating electrical signals (e.g., wires). The software code may sometimes be referred to as software, data, program instructions, instructions, or code. The non-transitory computer readable storage media can, for example, include computer memory chips, non-volatile memory such as non-volatile random-access memory (NVRAM), one or more hard drives (e.g., magnetic drives or solid state drives), one or more removable flash drives or other removable media, compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs (BDs), other optical media, and floppy diskettes, tapes, or any other suitable memory or storage device(s).

FIG.6Aillustrates a block diagram of a system10that can be used to implement a circuit design to be programmed into a programmable logic device19using design software. A designer can implement circuit design functionality on an integrated circuit, such as a reconfigurable programmable logic device19(e.g., a field programmable gate array (FPGA)). The designer can implement the circuit design to be programmed onto the programmable logic device19using design software14. The design software14can use a compiler16to generate a low-level circuit-design program (bitstream)18, sometimes known as a program object file and/or configuration program, that programs the programmable logic device19. Thus, the compiler16can provide machine-readable instructions representative of the circuit design to the programmable logic device19. For example, the programmable logic device19can receive one or more programs (bitstreams)18that describe the hardware implementations that should be stored in the programmable logic device19. A program (bitstream)18can be programmed into the programmable logic device19as a configuration program20. The configuration program20can, in some cases, represent an accelerator function to perform for machine learning, video processing, voice recognition, image recognition, or other highly specialized task.

In some implementations, a programmable logic device can be any integrated circuit device that includes a programmable logic device with two separate integrated circuit die where at least some of the programmable logic fabric is separated from at least some of the fabric support circuitry that operates the programmable logic fabric. One example of such a programmable logic device is shown inFIG.6B, but many others can be used, and it should be understood that this disclosure is intended to encompass any suitable programmable logic device where programmable logic fabric and fabric support circuitry are at least partially separated on different integrated circuit die.

FIG.6Bis a diagram that depicts an example of the programmable logic device19that includes three fabric die22and two base die24that are connected to one another via microbumps26. In the example ofFIG.6B, at least some of the programmable logic fabric of the programmable logic device19is in the three fabric die22, and at least some of the fabric support circuitry that operates the programmable logic fabric is in the two base die24. For example, some of the circuitry of configurable IC500shown inFIG.5(e.g., LABs510, DSP520, and RAM530) can be located in the fabric die22and some of the circuitry of IC500(e.g., input/output elements502) can be located in the base die24.

Although the fabric die22and base die24appear in a one-to-one relationship or a two-to-one relationship inFIG.6B, other relationships can be used. For example, a single base die24can attach to several fabric die22, or several base die24can attach to a single fabric die22, or several base die24can attach to several fabric die22(e.g., in an interleaved pattern). Peripheral circuitry28can be attached to, embedded within, and/or disposed on top of the base die24, and heat spreaders30can be used to reduce an accumulation of heat on the programmable logic device19. The heat spreaders30can appear above, as pictured, and/or below the package (e.g., as a double-sided heat sink). The base die24can attach to a package substrate32via conductive bumps34. In the example ofFIG.6B, two pairs of fabric die22and base die24are shown communicatively connected to one another via an interconnect bridge36(e.g., an embedded multi-die interconnect bridge (EMIB)) and microbumps38at bridge interfaces39in base die24.

In combination, the fabric die22and the base die24can operate in combination as a programmable logic device19such as a field programmable gate array (FPGA). It should be understood that an FPGA can, for example, represent the type of circuitry, and/or a logical arrangement, of a programmable logic device when both the fabric die22and the base die24operate in combination. Moreover, an FPGA is discussed herein for the purposes of this example, though it should be understood that any suitable type of programmable logic device can be used.

FIG.7is a block diagram illustrating a computing system700configured to implement one or more aspects of the embodiments described herein. The computing system700includes a processing subsystem70having one or more processor(s)74, a system memory72, and a programmable logic device19communicating via an interconnection path that can include a memory hub71. The memory hub71can be a separate component within a chipset component or can be integrated within the one or more processor(s)74. The memory hub71couples with an input/output (I/O) subsystem50via a communication link76. The I/O subsystem50includes an input/output (I/O) hub51that can enable the computing system700to receive input from one or more input device(s)62. Additionally, the I/O hub51can enable a display controller, which can be included in the one or more processor(s)74, to provide outputs to one or more display device(s)61. In one embodiment, the one or more display device(s)61coupled with the I/O hub51can include a local, internal, or embedded display device.

In one embodiment, the processing subsystem70includes one or more parallel processor(s)75coupled to memory hub71via a bus or other communication link73. The communication link73can use one of any number of standards based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor specific communications interface or communications fabric. In one embodiment, the one or more parallel processor(s)75form a computationally focused parallel or vector processing system that can include a large number of processing cores and/or processing clusters, such as a many integrated core (MIC) processor. In one embodiment, the one or more parallel processor(s)75form a graphics processing subsystem that can output pixels to one of the one or more display device(s)61coupled via the I/O Hub51. The one or more parallel processor(s)75can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s)63.

Within the I/O subsystem50, a system storage unit56can connect to the I/O hub51to provide a storage mechanism for the computing system700. An I/O switch52can be used to provide an interface mechanism to enable connections between the I/O hub51and other components, such as a network adapter54and/or a wireless network adapter53that can be integrated into the platform, and various other devices that can be added via one or more add-in device(s)55. The network adapter54can be an Ethernet adapter or another wired network adapter. The wireless network adapter53can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.

The computing system700can include other components not shown inFIG.7, including other port connections, optical storage drives, video capture devices, and the like, that can also be connected to the I/O hub51. Communication paths interconnecting the various components inFIG.7can be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or any other bus or point-to-point communication interfaces and/or protocol(s), such as the NV-Link high-speed interconnect, or interconnect protocols known in the art.

In one embodiment, the one or more parallel processor(s)75incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In another embodiment, the one or more parallel processor(s)75incorporate circuitry optimized for general purpose processing, while preserving the underlying computational architecture. In yet another embodiment, components of the computing system700can be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processor(s)75, memory hub71, processor(s)74, and I/O hub51can be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system700can be integrated into a single package to form a system in package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system700can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

The computing system700shown herein is illustrative. Other variations and modifications are also possible. The connection topology, including the number and arrangement of bridges, the number of processor(s)74, and the number of parallel processor(s)75, can be modified as desired. For instance, in some embodiments, system memory72is connected to the processor(s)74directly rather than through a bridge, while other devices communicate with system memory72via the memory hub71and the processor(s)74. In other alternative topologies, the parallel processor(s)75are connected to the I/O hub51or directly to one of the one or more processor(s)74, rather than to the memory hub71. In other embodiments, the I/O hub51and memory hub71can be integrated into a single chip. Some embodiments can include two or more sets of processor(s)74attached via multiple sockets, which can couple with two or more instances of the parallel processor(s)75.

Some of the particular components shown herein are optional and may not be included in all implementations of the computing system700. For example, any number of add-in cards or peripherals can be supported, or some components can be eliminated. Furthermore, some architectures can use different terminology for components similar to those illustrated inFIG.7. For example, the memory hub71can be referred to as a Northbridge in some architectures, while the I/O hub51can be referred to as a Southbridge.

Additional examples are now described. Example 1 is an integrated circuit comprising: memory circuits; a selector circuit; a first bus coupled to the selector circuit; and a controller circuit to provide test signals from the controller circuit through the first bus to the selector circuit for transmission to the memory circuits during a memory built-in-self-test mode.

In Example 2, the integrated circuit of Example 1, wherein each of the memory circuits comprises a comparator circuit configurable to compare a read data bit read from one of the memory circuits to an expected data bit in the test signals to generate a sticky error bit during the memory built-in-self-test mode.

In Example 3, the integrated circuit of Example 2, wherein each of the memory circuits further comprises flip-flop circuits that are configurable to shift the sticky error bit to the selector circuit during the memory built-in-self-test mode.

In Example 4, the integrated circuit of any one of Examples 1-3, wherein the selector circuit comprises a test access port circuit configurable to receive and store test output bits generated by the memory circuits during the memory built-in-self-test mode.

In Example 5, the integrated circuit of any one of Examples 1-4, wherein the selector circuit comprises a first multiplexer circuit configurable to provide a first subset of the test signals through a second bus to a first subset of the memory circuits, and wherein the selector circuit further comprises a second multiplexer circuit configurable to provide a second subset of the test signals through a third bus to a second subset of the memory circuits.

In Example 6, the integrated circuit of any one of Examples 1-5 further comprising: multiplexer circuits configurable to provide control signals from the selector circuit to the memory circuits to perform built-in-self-tests during the memory built-in-self-test mode and to provide output signals generated by the memory circuits during the built-in-self-tests to the selector circuit.

In Example 7, the integrated circuit of any one of Examples 1-6, wherein each of the memory circuits comprises flip-flop circuits that are configurable to shift and store a bit used to enable a built-in-self-test of at least one of the memory circuits during the memory built-in-self-test mode.

In Example 8, the integrated circuit of any one of Examples 1-7, wherein the controller circuit provides write data to the memory circuits through the first bus and the selector circuit, and wherein the memory circuits store the write data as stored data, generate read data by reading the stored data, and compare the read data to expected data to generate sticky error bits during built-in-self-tests performed in the memory built-in-self-test mode.

In Example 9, the integrated circuit of any one of Examples 1-8, further comprising: a multiplexer circuit configurable to provide configuration bits through the first bus to the selector circuit for transmission to the memory circuits during a configuration mode of the integrated circuit.

Example 10 is a method for testing memory circuits in an integrated circuit, the method comprising: providing test signals from a controller circuit through a first bus to a first multiplexer circuit; configuring the first multiplexer circuit to provide the test signals from the first bus through a second bus to the memory circuits; and performing built-in-self-tests of the memory circuits using the test signals.

In Example 11, the method of Example 10, wherein performing the built-in-self-tests of the memory circuits further comprises comparing read data from the memory circuits to expected data to generate sticky error bits using comparator circuits in the memory circuits.

In Example 12, the method of any one of Examples 10-11 further comprising: generating test output bits in the memory circuits using the test signals; and shifting the test output bits to a control circuit through shift register circuits in the memory circuits and through second multiplexer circuits.

In Example 13, the method of any one of Examples 10-12, wherein performing the built-in-self-tests of the memory circuits further comprises storing write data indicated by the test signals in the memory circuits as stored data, accessing the stored data as read data, and comparing the read data to expected data to generate output test bits.

In Example 14, the method of any one of Examples 10-13 further comprising: configuring second multiplexer circuits to provide control signals from a test access port control circuit to the memory circuits to perform the built-in-self-tests and to provide test output bits generated by the memory circuits during the built-in-self-tests to the test access port control circuit.

In Example 15, the method of any one of Examples 10-14 further comprising: configuring a second multiplexer circuit to provide additional test signals from the first bus to additional memory circuits through a third bus; and performing additional built-in-self-tests of the additional memory circuits using the additional test signals.

In Example 16, the method of any one of Examples 10-15, wherein performing the built-in-self-tests of the memory circuits further comprises performing the built-in-self-tests using internal Joint Test Action Group signals generated by a control circuit.

Example 17 is a circuit system comprising: memory circuits; a first multiplexer circuit; first and second busses; and a memory controller circuit, wherein the first multiplexer circuit is configurable to provide test bits that are received from the memory controller circuit through the first bus to the memory circuits through the second bus for performing built-in-self-tests of the memory circuits.

In Example 18, the circuit system of Example 17, wherein each of the memory circuits comprises a comparator circuit that compares a read data bit to an expected data bit to generate a sticky error bit during the built-in-self-tests.

In Example 19, the circuit system of any one of Examples 17-18, wherein the test bits comprise write data, and wherein the memory circuits store the write data as stored data, generate read data from the stored data, and compare the read data to expected data to generate sticky error bits during the built-in-self-tests.

In Example 20, the circuit system of any one of Examples 17-19 further comprising: second multiplexer circuits configurable to provide control signals from a control circuit to the memory circuits to perform the built-in-self-tests and to provide output bits generated by the memory circuits to the control circuit in response to the control signals during the built-in-self-tests.

The foregoing description of the exemplary embodiments has been presented for the purpose of illustration. The foregoing description is not intended to be exhaustive or to be limiting to the examples disclosed herein. The foregoing is merely illustrative of the principles of this disclosure and various modifications can be made by those skilled in the art. The foregoing embodiments may be implemented individually or in any combination.