Fabrication method of power semiconductor structure with reduced gate impedance

A fabrication method of a power semiconductor structure with reduced gate impedance is provided. Firstly, a polysilicon gate is formed in a substrate. Then, dopants are implanted into the substrate with the substrate being partially shielded by the polysilicon gate. Afterward, an isolation layer is formed to cover the polysilicon gate. Thereafter, a thermal drive-in process is carried out to form at least a body surrounding the polysilicon gate. Then, the isolation layer is removed to expose the polysilicon gate. Afterward, a metal layer is deposited on the dielectric layer and the polysilicon gate, and a self-aligned silicide layer is formed on the polysilicon gate by using a thermal process.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

This invention relates to a fabrication method of a power semiconductor structure, and more particularly relates to a fabrication method of a power semiconductor with reduced gate impedance.

(2) Description of the Prior Art

Energy conservation is an important issue nowadays. The trend of energy conservation encourages the settlement of strict energy efficiency standards, which brings a severe challenge for the developers of power converters. To meet this challenge, the new power device, such as the power MOSFET, plays an important role and has been widely applied to various power converters.

FIGS. 1A to 1Care schematic cross-section views showing the fabrication method of a typical trenched power semiconductor structure. An N-type trenched power MOSFET is described below for example. As shown inFIG. 1A, firstly, an N-type silicon substrate110is provided, and then a mask (not shown) is utilized to define the location of gate trenches120in the silicon substrate110. The gate trenches120are then formed in the N-type silicon substrate110by dry etching. Thereafter, a gate oxide layer130,132is formed on the exposed surfaces of the N-type silicon substrate110.

Next, a polysilicon layer is deposited over the N-type silicon substrate110to fill the gate trenches120. Then, the portion of the polysilicon layer on the upper surface of the N-type silicon substrate120is removed by etching back to leave a plurality of polysilicon gates140located in the gate trenches120. Thereafter, as shown inFIG. 1B, a blanket ion implantation is carried out to implant P-type dopants in the N-type silicon substrate110to form a doped region150. Then, as shown inFIG. 1C, the implanted P-type dopants are driven in the silicon substrate110by annealing so as to form a P-body150′ in the N-type silicon substrate110.

When scaling down the cell dimension of MOSFETs for a higher integration, the resistance of the polysilicon gate140is increased due to a narrower and shallower gate trench120. The switching speed of the transistor would be badly influenced by the increased gate resistance and a greater switching loss is resulted.

The resistance of polysilicon material can be quite high, which is usually greater than 1 mΩ-cm, in respective with the metal material. In order to reduce the resistance of the polysilicon gate140, a typical method is to form low resistance silicide on the polysilicon gate140.

As to the fabrication process of typical self-aligned silicide (salicide), the timing of the fabrication step of the silicide layer should be postponed until the ion implantation steps and the thermal drive-in steps are finished, such that the unwanted diffusion of metal ions under high temperature to result in pollution can be prevented and the thickness of the silicide layer can be well-controlled. However, as shown inFIGS. 1B and 1C, the drive-in step is usually performed in oxygen ambient, which may result in the formation of the oxide layer on the surface of the polysilicon gate140. In addition, the oxide layer134formed on the polysilicon gate140with high density dopants is always thicker than the oxide layer132′ on the surface of the silicon substrate120.

The oxide layers134,132′ may hinder the formation of silicide. Thus, as shown inFIG. 1C, to form self-aligned silicide (salicide), the oxide layer134on the polysilicon gate140should be removed but the oxide layer132′ should be kept on the silicon substrate110. However, as mentioned above, because the thickness of the oxide layer134on the polysilicon gate140is greater than the oxide layer132′ on the silicon substrate110, it is difficult to selectively remove the oxide layer134on the polysilicon gate140but leave the oxide layer132′ on the silicon substrate110merely by etching.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a fabrication method of a power semiconductor structure capable of forming the self-aligned silicide (salicide) layer on the polysilicon gate for reducing gate impedance of the power semiconductor structure.

A fabrication method of a power semiconductor structure with reduced gate impedance is provided in accordance with an embodiment of the present invention. Firstly, a polysilicon gate is formed in a substrate. The polysilicon gate may be a trenched polysilicon gate or a planar one. Then, dopants are implanted into the substrate with the substrate being partially shielded by the polysilicon gate. Afterward, an isolation layer is formed to cover the polysilicon gate. Thereafter, a thermal drive-in process is carried out to form at least a body surrounding the polysilicon gate. Then, the isolation layer is removed to expose the polysilicon gate. Afterward, a metal layer is deposited on the dielectric layer and the polysilicon gate, and a self-aligned silicide (salicide) layer is formed on the polysilicon gate by using a thermal process.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The main feature of the present invention is to deposit a silicon nitride layer previous to the thermal drive-in process, so as to make sure a clear upper surface on the polysilicon gate without oxide layer thereon is maintained after the following body drive-in and source drive-in steps. Thereby, the silicon oxide layer on the silicon substrate can be utilized as a mask for the formation of self-aligned silicide (salicide) layer on the polysilicon gate for reducing gate resistance. It is well understood that the idea of the present invention can be applied to both the trenched polysilicon gate and the planar one. Since the planar one is simpler in structure than the trenched one, the fabrication method of the trenched power polysilicon structure is described below for a better understanding of the present invention.

FIGS. 2A to 2Fare schematic cross-section views showing a fabrication method of a trenched power semiconductor structure with reduced gate impedance in accordance with a first embodiment of the present invention. As shown inFIG. 2A, a gate trench220is firstly formed in a silicon substrate210. Then, a dielectric layer230,232is formed on exposed surfaces of the silicon substrate210, which includes the inner surface of the gate trench220and the upper surface of the silicon substrate210. The dielectric layer230,232may be formed of silicon oxide, silicon nitride, or other adequate dielectric materials. Thereafter, a polysilicon gate240is formed in the gate trench220. Then, a doped region250is formed by implanting dopants of first conductive type into the silicon substrate210with the silicon substrate being partially shielded by the polysilicon gate240.

Next, as shown inFIG. 2B, an isolation layer260is conformally formed on the silicon substrate210and the polysilicon gate240. The isolation layer260is functioned to isolate the polysilicon gate240from the environmental gas, for example, oxygen. As a preferred embodiment, the isolation layer260may be formed of silicon nitride.

Next, as shown inFIG. 2C, a thermal drive-in step is carried out focusing on the implanted first conductive type dopants in the doped region250indicated by the dashed line. As indicated by the arrow, the dopants within the doped region250are chiefly diffused downward to compose a body250′ surrounding the polysilicon gate240.

Next, as shown inFIG. 2D, a source implantation step is carried out for implanting dopants of second conductive type through the dielectric layer232and the isolation layer260into the body250′. Thereafter, another thermal drive-in step is performed to form the source region270at the surface region of the silicon substrate210.

Next, as shown inFIG. 2E, the isolation layer260is removed to expose the dielectric layer232on the upper surface of the silicon substrate210and the upper surface of the polysilicon gate240. Then, a metal layer280is deposited on the dielectric layer232and the polysilicon gate240. After the deposition of the metal layer280, an annealing process, such as the rapid thermal annealing (RTA) process, is performed to have the metal layer280reacting with the polysilicon gate240so as to form the self-aligned silicide (salicide) layer285at the interface between the polysilicon gate240and the metal layer280. Thereafter, the unwanted portion of the metal layer280, the unreacted portion for example, is removed. The following fabrication steps, such as the step of forming the source contact window, are not the patentable feature of the present invention and are well known for people in the art, and thus are not described here.

In the fabrication method of traditional trenched power semiconductor structure, the silicon oxide layer134on the polysilicon gate140to retard the formation of silicide would be unpreventable due to the existence of the ion implantation step and the adjacent thermal drive-in step. In addition, because the thickness of the silicon oxide layer134on the polysilicon gate140is always greater than the silicon oxide layer132′ on the silicon substrate110, it is difficult to selectively remove the silicon oxide layer134merely by etching to leave the silicon oxide layer132′ on the silicon substrate110as the mask for forming the self-aligned silicide (salicide) layer.

In contrast, as shown inFIG. 2B, in accordance with the present embodiment, the isolation layer260deposited on the polysilicon gate240just after the ion implantation step is capable of preventing the formation of silicon oxide on the polysilicon gate240in the following thermal drive-in step. Thus, as shown inFIG. 2E, after the formation of the body250′ and the source region270, the dielectric layer232on the silicon substrate210can be used as the mask for forming the self-aligned silicide layer285on the polysilicon gate240.

FIGS. 3A to 3Care schematic cross-section views showing a fabrication method of a trenched power semiconductor structure in accordance with a second embodiment of the present invention. Referring toFIG. 3C, in contrast with the first embodiment of the present invention, which has the isolation layer260formed right after the first conductive type dopants being implanted into the substrate210, the present embodiment applies another ion implantation step for implanting second conductive type dopants into the substrate210before the formation of the isolation layer. According the present embodiment, a deeper first doped region350and a shallower second doped region370are formed in the substrate210after the two ion implantation steps, wherein the first doped region350is of the first conductive type and the second doped region370is of the second conductive type.

Next, as shown inFIG. 3B, an isolation layer260is comformally deposited on the silicon substrate210and the polysilicon gate240. Then, as shown inFIG. 3C, a thermal drive-in step is performed focusing on both the dopants in the first doped region350and the second doped region370. As indicated by the arrow, the dopants within the first doped region350are diffused downward to form the body350′ surrounding the polysilicon gate240, and the dopants within the second doped region370are diffused downward to form the source region370′ at the source region of the silicon substrate210.

FIGS. 4A to 4Care schematic cross-section views showing a fabrication method of a trenched power semiconductor structure in accordance with a third embodiment of the present invention. The fabrication step ofFIG. 4Ais next to the fabrication step as shown inFIG. 2C. As shown inFIG. 4A, after the formation of the body450surrounding the polysilicon gate240, dopants of second conductive type are implanted into the body450through the dielectric layer232and the isolation layer260so as to form a doped region470within the body450.

Next, as shown inFIG. 4B, the isolation layer260is removed to expose the dielectric layer232on the silicon substrate210and the upper surface of the polysilicon gate240. Then a metal layer280is deposited on the dielectric layer232and the polysilicon gate240. Afterward, as shown inFIG. 2F, an annealing process, such as the rapid thermal annealing (RTA) step, is carried out to have the metal layer280reacting with the polysilicon gate240so as to form the self-aligned silicide (salicide) layer285on the polysilicon gate240. Meanwhile, the dopants within the doped region470are diffused downward to form the source region470′. Thereafter, the unwanted portion of the metal layer280is removed. The following fabrication steps, such as the step of forming the source contact window, are not the patentable feature of the present invention, and thus are not described here.

FIGS. 5A and 5Bare schematic cross-section views showing a trenched power semiconductor structure with reduced gate impedance in accordance with a fourth embodiment of the present invention. The fabrication ofFIG. 5Ais next to the fabrication as shown inFIG. 2A. As shown inFIG. 5A, an isolation layer560is deposited on the silicon substrate210and the polysilicon gate240right after the ion implantation step for implanting first conductive type dopants into the substrate210to form the doped region250. It is noted that, the thickness of the isolation layer560in accordance with the present embodiment is greater than that of the isolation layer260in the first embodiment of the present invention, and the gate trench220is filled with the isolation layer560.

Next, as shown inFIG. 5B, the unwanted portion of the isolation layer560, which is also the portion outside the gate trench220, is removed by using etching back process so as to leave the portion562within the gate trench220and to have the dielectric layer232on the silicon substrate210exposed. To facilitate the etching back process, the dielectric layer232may be formed of silicon oxide and the isolation layer560may be formed of silicon nitride for the object of selectively removing the isolation layer560. It is understood by persons skilled in the art that the composing materials of the dielectric layer232and the isolation layer560are not so restricted. Various dielectric materials suitable for the etching back process as indicated above can be applied in the present embodiment.

Next, as shown inFIG. 5C, a thermal drive-in step is performed focusing on the first conductive type dopants within the doped region250as indicated by the dashed line. After the thermal drive-in step, a body250′ is formed in the substrate210surrounding the polysilicon gate240. Thereafter, as shown inFIG. 5D, dopants of second conductive type are implanted into the body250′ through the thin dielectric layer232, and then another thermal drive-in step is performed to form the source region270in the silicon substrate210. The following steps of the present embodiment are similar to that of the first embodiment, and thus are not repeated here.

In conclusion, the fabrication method provided in the present invention features the step of depositing the isolation layer260on the polysilicon gate240to isolate the polysilicon gate240from the environment ambient before the drive-in process, thus, the formation of silicon oxide layers on the polysilicon gate240during the drive-in process can be prevented. In addition, after the following steps of forming the body250′ and the source region270, the remained dielectric layer232on the upper surface of the silicon substrate210can be utilized as the mask for forming the self-aligned silicide (salicide) layer285on the polysilicon gate240. Thus, the fabrication method provided in the present invention is capable to simplify the process for forming the self-aligned silicide, which is helpful for reducing gate impedance of power transistors.