Vertical Transistors Occupying Reduced Chip Area and the Methods Forming the Same

A method includes forming a vertical transistor, and the method includes forming a vertical semiconductor bar over a substrate, forming a gate dielectric and a gate electrode encircling the vertical semiconductor bar, forming a first source/drain region over a top surface of the vertical semiconductor bar, removing the substrate to reveal a bottom surface of the vertical semiconductor bar; and forming a second source/drain region contacting the bottom surface of the vertical semiconductor bar. The method further includes forming a backside power line, with the backside power line being on a bottom side of the vertical semiconductor bar. The backside power line is connected to the second source/drain region.

BACKGROUND

Transistors are key components of modern integrated circuits. To satisfy the requirements of increasingly faster switching speed, the drive currents of transistors need to be increasingly higher. At the same time, the gate lengths of transistors are constantly being scaled down. Scaling down the gate lengths leads to undesirable effects known as “short-channel effects,” with which the control of current flow by the gates is compromised. Among the short-channel effects are the drain-induced barrier lowering (DIBL) and the degradation of sub-threshold slope, both of which result in the degradation in the performance of transistors.

The use of multi-gate transistor architecture may help the relief of short-channel effects by improving electrostatic control of the gate on the channel. Fin field-effect transistors (FinFET) were thus developed. To further increase the control of the channels, and to reduce the short-channel effects, transistors having vertical gate-all-around structures were also developed, wherein the respective transistors are also referred to as Vertical Gate All Around (VGAA) transistors. In a VGAA transistor, a gate dielectric and a gate electrode fully encircle a channel region. This configuration delivers a good control of the channel, and the short-channel effects are reduced.

DETAILED DESCRIPTION

A circuit formed of vertical transistors and the methods of forming the same are provided. The vertical transistors may be vertical Gate-All-Around (GAA) transistors. In accordance with some embodiments, vertical GAA transistors are formed, and both of VDD and VSS power lines are formed on the front side and the backside of the vertical transistors. Accordingly, the chip areas occupied by the vertical transistors are reduced. Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

FIGS.1through17illustrate the cross-sectional views of intermediate stages in the formation of an inverter comprising double-side powered vertical transistors in accordance with some embodiments of the present disclosure. The corresponding processes are also reflected schematically in the process flow shown inFIG.22.

FIG.1illustrates a perspective view of an initial structure. The initial structure includes wafer10, which further includes substrate20. Substrate20may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. Substrate20may be doped with a p-type or an n-type impurity, or may be undoped.

In accordance with some embodiments, epitaxy layer22is deposited on substrate20through an epitaxy process. Epitaxy layer22may be formed of or comprise silicon, silicon germanium, or the like. During the epitaxy process, an in-situ doping process may be performed to dope an n-type dopant or a p-type dopant. The n-type dopant may comprise phosphorous, arsenic, antimony, or the like. The p-type dopant may comprise boron, indium, or the like. The n-type or p-type dopant concentration is selected so that the resulting epitaxy layer22may act as a well region of some of the respective vertical transistors. For example, the dopant concentration may be less than 1018 cm−3, such as in the range between about 1015cm−3and about 1018 cm−3. In the illustrative example, a p-type dopant is in-situ doped, so that epitaxy layer22is of p-type.

Next, an implantation mask such as photoresist24is formed and patterned, exposing a portion of epitaxy layer22. Implantation process26is then performed to implant the exposed portion of epitaxy layer22, so that the conductivity type of the implanted portion is inverted. For example, when epitaxy layer22is of p-type, the implanted portion is converted to n-type, and is denoted as portion22N. Conversely, when epitaxy layer22is of n-type, the implanted portion is converted to p-type.

Next, referring toFIG.2, a patterning process is performed through an etching process, so that the remaining epitaxy layer22includes portions22P and22N, respectively, which are of p-type and n-type, respectively. The respective process is illustrated as process202in the process flow200as shown inFIG.22.FIG.18Aillustrates a top view of portions22N and22P as an example. In accordance with some embodiments, as shown inFIG.18A, portions22P and22N are elongated strips to increase channel length. In accordance with other embodiments, portions22P and22N may have other shapes such as rectangular or circular top-view shapes. For example, each of portions22P and22N may include a plurality of small discrete portions that are separated from each other, and the discrete portions may be arranged with a periodic pattern such as an array.

In accordance with some embodiments, the patterning is stopped on the top surface of substrate20. In accordance with other embodiments, a top surface portion of substrate20is also patterned and recessed, and the resulting recessed top surfaces of substrate20are illustrated using dashed lines. Throughout the description, portions22P and22N are alternatively referred to as vertical semiconductor bars22P and22N.

Referring toFIG.3, gate dielectric layer28is formed. The respective process is illustrated as process204in the process flow200as shown inFIG.22. In accordance with some embodiments, gate dielectric layer28includes an Interfacial Layer (IL) in contact with vertical semiconductor bars22P and22N, and a high-k dielectric layer over the IL. In accordance with some embodiments, the IL is formed of or comprise silicon oxide, which may be formed through a deposition process, and/or an oxidation process. In the oxidation process, a surface layer of each of vertical semiconductor bars22N and22P is oxidized to form an oxide. The high-k dielectric layer may be formed of or comprise hafnium oxide, zirconium oxide, aluminum oxide, lanthnum oxide, or the like. The high-k dielectric layer (and possibly the IL also) may be formed as being a conformal layer(s), for example, deposited using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or the like.

FIG.3also illustrates the formation of gate electrode30N. The respective process is illustrated as process206in the process flow200as shown inFIG.22. In accordance with some embodiments, the formation of gate electrode30N includes depositing one or a plurality of conductive layers sequentially, and then patterning the plurality of conductive layers. The deposited layers may include an n-type work function layer (when the respective underlying vertical semiconductor bar is of p-type). In addition, the deposited layers may also include adhesion layers, capping layers (such as TiN layers), and/or the like. In accordance with some embodiments, the n-type work function layer may comprise titanium aluminum (TiAl), TiAlN, or the like. After the deposition, an etching process(es) may be performed to pattern the deposited layers, leaving gate electrode30N.

FIG.4illustrates the formation of gate electrode30P. The respective process is illustrated as process208in the process flow200as shown inFIG.22. In accordance with some embodiments, the formation of gate electrode30P also includes depositing one or a plurality of layers sequentially, and then patterning the plurality of layers. The deposited layers may include a p-type work function layer, and possibly adhesion layers, capping layers (such as TiN layers), and/or the like. In accordance with some embodiments, the p-type work function layer may comprise a TiN layer and possibly a TaN layer. After the deposition, an etching process(es) may be performed to pattern the deposited layers, leaving gate electrode30P.

In accordance with some embodiments, the portion of the p-type work function layer overlapping n-type gate electrode30N may be removed, resulting in the structure shown inFIG.4. In accordance with alternatively embodiments, the portion30P′ of the p-type work function layer overlapping n-type work function layer30N may remain, as shown by dashed lines inFIG.4.

In accordance with some embodiments, gate dielectric layer28is patterned, and some horizontal portions of gate dielectric layer28are removed. The remaining portions of gate dielectric layer28surrounding vertical semiconductor bars22N and22P are referred to as gate dielectrics28N and28P, respectively. In accordance with alternative embodiments, gate dielectric layer28is not patterned, and remain as being a blanket layer. The horizontal portions of gate dielectric layer28may then be removed in the subsequent backside grinding process, as shown inFIG.13.

FIG.5illustrates the formation of gate pad32, which is used for landing a gate contact plug. The respective process is illustrated as process210in the process flow200as shown inFIG.22. The formation of gate pad32may also include depositing a metal layer such as a copper layer, an aluminum layer, a tungsten layer, or the like, and patterning the metal layer. In accordance with some embodiments, gate pad32is in contact with gate electrode30N and30P, and electrically connects gate electrode30N to gate electrode30P.

FIG.6illustrates the formation of dielectric layer34to embed vertical semiconductor bars22P and22N, gate dielectrics28N and28P, gate electrodes30N and30P, and gate pad32therein. The respective process is illustrated as process212in the process flow200as shown inFIG.22. Dielectric layer34may be a homogeneous dielectric layer, or may include a Contact Etch Stop Layer (CESL, which is conformal) and an Inter-Layer Dielectric (ILD). The CESL may be formed of silicon oxide, silicon nitride, silicon carbo-nitride, or the like, and may be formed using CVD, ALD, or the like. The ILD may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD. ALD, or another deposition method. The ILD may be formed of an oxygen-containing dielectric material, which may be a silicon-oxide based material such as silicon oxide, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), or the like.

Next, a planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process may be performed to remove some portions of dielectric layer34, gate dielectrics28N and28P, and gate electrodes30N and30P, with the removed portions being higher than vertical semiconductor bars22P and22N. Accordingly, the top surfaces of vertical semiconductor bars22P and22N are revealed.

FIG.7illustrates the formation of epitaxy layers36N and36P, which form the front-side source/drain regions of the resulting vertical transistors, and may have single crystalline structures. The respective process is illustrated as process214in the process flow200as shown inFIG.22. Throughout the description, source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context. Epitaxy layers36N and36P are formed through selective epitaxy processes, so that they are selectively grown from the top surfaces of vertical semiconductor bars22P and22N, respectively, but not from dielectric materials and metals. Epitaxy layers36N and36P may be heavily doped (for example, through in-situ doping during the epitaxy), so that epitaxy layers36N and36P are N+ layer and P+ layer, respectively. For example, the doping concentration of epitaxy layers36N and36P may be in the range between about 5E20/cm3and about 5E22/cm3. Epitaxy layers36N and36P are selective grown in separate epitaxy processes, with dielectric hard masks (not shown) being used to mask the regions in which the epitaxy is not intended.

Since the epitaxy process is selective, and epitaxy layers36N and36P are not grown from dielectric layers and metal layers, epitaxy layers36N and36P are self-aligned to the underlying vertical semiconductor bars22P and22N, respectively.

FIG.7also illustrates a silicidation process for forming silicide layers38N and38P. The respective process is also illustrated as process214in the process flow200as shown inFIG.22. The formation process may include depositing a metal layer such as a nickel layer, a cobalt layer, or the like, performing an annealing process(es) to react the metal layer with a surface portion of each of epitaxy layers36N and36P, so that silicide layers38N and38P are formed. After the silicidation process, unreacted portions of the metal layer are removed through etching, leaving silicide layers38N and38P. Although not shown, silicide layers38N and38P may extend to the sidewalls of the remaining epitaxy layers36N and36P, respectively. Since the silicidation process is also selective, silicide layers38N and38P are self-aligned to the underlying epitaxy layers36N and36P, respectively.

ILD40is also formed. In accordance with some embodiments, the formation of ILD40may comprise depositing a dielectric layer, and performing a CMP process, until the top surfaces of silicide layers38N and38P are exposed. In accordance with alternative embodiments, ILD40is formed first, followed by patterning ILD40to reveal vertical semiconductor bars22P and22N. The selective epitaxy processes are then performed to form epitaxy layers36N and36P, followed by a silicidation process to form silicide layers38N and38P.

ILD40may be a homogeneous dielectric layer formed of a homogeneous dielectric material such as silicon oxide, PSG, BSG, BPSG, or the like. Alternatively, ILD40may comprise a conformal CESL, and a ILD over the CESL.

FIG.8illustrates the formation of ILD42. Front-side source/drain contact plugs44are also formed. The respective process is illustrated as process216in the process flow200as shown inFIG.22. There may be an etch stop layer (not shown) formed before the formation of ILD42. In accordance with some embodiments, the formation of ILD42and source/drain contact plugs44includes depositing ILD42. patterning ILD42to form source/drain contact openings and to reveal silicide layers38N and38P, filling the source/drain contact openings with metallic-containing materials/layers, and performing a planarization process. Each of source/drain contact plugs44may comprise an adhesion layer such as a TiN layer, and a metal region (such as a tungsten region, a cobalt region, or the like) over the adhesion layer.

In accordance with alternative embodiments, instead of forming silicide layers38N and38P before the formation of ILD42, ILD42may be formed first. Silicide layers38N and38P and source/drain contact plugs44are formed after the formation and the patterning of ILD42to reveal epitaxy layers36N and36P. Accordingly, the edges of source/drain contact plugs44are vertically aligned to the edges of the respective underlying silicide layers38N and38P. The edges of silicide layers38N and38P, however, may be laterally recessed from the respective edges of epitaxy layers36N and36P.

FIG.9illustrates the formation of dielectric layer46, vias48, and gate contact plugs50. There may also be an etch stop layer (not shown) formed before the formation of dielectric layer46. In accordance with some embodiments, the formation of dielectric layer46and vias48includes depositing dielectric layer46, patterning dielectric layer46to form via openings and to reveal source/drain contact plugs44, filling the vias openings with metallic-containing materials/layers, and performing a planarization process. Dielectric layer46may comprise a carbon-containing low-k dielectric material. Each of vias48may comprise a diffusion barrier (such as a TiN layer), and a copper-containing region over the diffusion barrier.

Gate contact plug50is also formed. The respective process is illustrated as process218in the process flow200as shown inFIG.22. The formation process may include etching dielectric layers46and ILDs42,40, and34to form a gate contact opening, and then filling the gate contact opening with a metal-containing material. Gate contact plug50may comprise an adhesion layer such as a TiN layer, and a metal region (such as a tungsten region, a cobalt region, or the like) over the adhesion layer.

FIG.10illustrates the formation of dielectric layer54and metal lines56. There may also be an etch stop layer (not shown) formed before the formation of dielectric layer54. Dielectric layer54may comprise a carbon-containing low-k dielectric material. Metal lines56may include power lines56(VDD) and56(VSS) and signal lines56(S). Metal lines56may be collectively referred to as metal layer MO. The formation process and the materials of dielectric layer54and metal lines56may comprise a damascene process, and may be essentially the same as that of dielectric layer46and metal vias48, respectively.

FIG.11illustrates the formation of dielectric layers58and62and vias60. Vias60are collectively referred to as vias Via0. Dielectric layers58and62may comprise a carbon-containing low-k dielectric material(s). The formation process and the materials of dielectric layers58and62and vias60may be essentially the same as that of dielectric layer54and metal lines56, respectively.

Metal lines64is also formed. Metal lines64are collectively referred to as metal layer M1. The respective process is illustrated as process222in the process flow200as shown inFIG.22. In accordance with some embodiments, a metal line64electrically connects two vias60A, which are further electrically connected to the source/drain regions of two vertical transistors in the inverter. Via60B is also illustrated as being dashed since via60B is in a different plane than illustrated, and is not connected to the illustrated metal line64. Furthermore, vias60and metal lines64may be formed through two single damascene processes or a dual damascene process.

FIG.12illustrates the formation of more dielectric layers, metal vias, metal lines, and the like. In accordance with some embodiments, a surface dielectric layer66and bond pads68are also formed as top surface features of wafer10. In accordance with alternative embodiments, solder regions may be formed as the top surface features of wafer10.

FIGS.13-17illustrate the formation of backside structures on the backside of vertical semiconductor bars22P and22N. A backside grinding process is first performed to remove substrate20and to reveal vertical semiconductor bars22N and22P. The resulting structure is shown inFIG.13. The respective process is illustrated as process224in the process flow200as shown inFIG.22. A carrier (such as a glass carrier, not shown) may be attached to the front side of wafer10before the backside grinding process is performed. As a result of the backside grinding process, the back surfaces of vertical semiconductor bars22P and22N are revealed.

In accordance with some embodiments, the horizontal portions of gate dielectrics28N and28P remain after the backside grinding process. In accordance with alternative embodiments, the horizontal portions of gate dielectrics28N and28P are also removed by the backside grinding process. For example, dashed lines70illustrate the possible levels of the backside surfaces of vertical semiconductor bars22P and22N in accordance with alternative embodiments.

FIG.14illustrates the formation of dielectric layer72, epitaxy regions74N and74P, and silicide layers76N and76P. The respective process is illustrated as process226in the process flow200as shown inFIG.22. The materials, structures, and formation processes may be essentially the same as that of ILD40, epitaxy regions36N and36P, and silicide layers38N and38P, respectively. The details are thus not repeated herein.

FIG.15illustrates the formation of dielectric layer78. Contact plugs80are also formed. The respective process is illustrated as process228in the process flow200as shown inFIG.22. The materials, structures, and formation processes may be essentially the same as that of dielectric layer46and vias48, respectively. The details are thus not repeated herein. Contact plugs80may be routed laterally, so that some portions of contact plugs80are overlapped by power lines56(VDD) and56(VSS).

FIG.16illustrates the formation of dielectric layers82and vias84. Deep vias90are then formed to penetrate a plurality of dielectric layers, and to connect to power lines56(VDD) and56(VSS). Deep vias90are illustrated as being dashed since they are formed in a plane other than the illustrated plane, and are not in contact with source/drain contact plugs80and vias84.

Next, dielectric layer86and backside power lines88(including VDD line88(VDD) and VSS line88(VSS)) are formed. There may be, or may not be, some signal lines formed in dielectric layer86. The respective process is illustrated as process230in the process flow200as shown inFIG.22. VDD line88(VDD) and VSS line88(VSS) are connected to front-side power lines56(VDD) and56(VSS), respectively, through deep vias90. Accordingly, power is conducted from the front-side power lines56(VDD) and56(VSS) to backside power lines88(VDD) and88(VSS), respectively.

Dielectric layers82and86may comprise a carbon-containing low-k dielectric material, silicon oxide, or a non-low-k dielectric material such as silicon nitride, silicon carbide, or the like. The formation process and the materials of dielectric layers82and86, vias84and backside power lines88may be essentially the same as that of dielectric layers58and62, vias60, and metal line64respectively. Furthermore, vias84and backside power lines88may be formed through single damascene processes or a dual damascene process.

Referring toFIG.17, passivation layer92is formed to protect backside power lines88. The respective process is illustrated as process232in the process flow200as shown inFIG.22. Passivation layer92may be formed of a non-low-k and dense dielectric material such as silicon oxide, silicon nitride, un-doped silicate glass, and/or the like, or combinations thereof. Passivation layer92may be a blanket layer with no openings and no conductive features therein. Furthermore, there may be no conductive features formed penetrating through passivation layer92to connect to backside power lines88(VDD) and88(VSS) and signal lines.

In a subsequent process, wafer10is singulated, for example, through a sawing process, so that identical device dies10′ are separated from each other. The respective process is illustrated as process234in the process flow200as shown inFIG.22. Device die10′ includes vertical transistors100N and100P, each having a source region, a channel region, and a drain region aligned to a vertical line. Vertical transistors100N and100P are interconnected to form inverter102. Vertical semiconductor bars22P and22N form the channel regions of vertical transistors100N and100P, respectively.

Epitaxy region36N and74N form the drain region (D) and the source region (S), respectively, of the n-type vertical transistor100N. Epitaxy region36P and74P form the drain region and the source region, respectively, of the p-type vertical transistor100P. The source region of the vertical transistor100N is connected to the backside power line88(VDD). The source region of the vertical transistor100P is connected to the backside power line88(VSS). It is appreciated that although in the illustrated example, backside power lines88(VDD) and88(VSS) are connected to the source regions of the vertical transistors, the backside power lines may also be connected to drain regions in other circuits.

In accordance with some embodiments, as shown inFIG.17, the connection to gate pad32is achieved from the front side of vertical transistors100N and100P through gate contact plug50. In accordance with alternative embodiments, the connection to the gate electrodes of transistors may be performed from the backside of the vertical transistors. For example,FIG.17illustrates backside gate contact plug108, which is connected to metal line106. Metal line106may be connected to VDD, VSS, or may be a signal line. Front-side gate contact plugs and back-side contact plugs may be used in the same device die to achieve more flexible routing.

FIGS.18A,18B, and18Cillustrate the top views obtained at three levels of the structure shown inFIG.17. The cross-section shown inFIG.17include the combination of the features shown in cross-sections17-17inFIGS.18A,18B, and18C.FIG.18Aillustrates a top view obtained at cross-section18A-18A inFIG.17. In accordance with some embodiments, vertical transistors100N and100P are connected to form inverter cell (a standard cell). The boundaries of inverter cell104are illustrated. Backside power lines88(VDD) and88(VSS) extend from the left boundary to the right boundary of inverter cell104, and are parallel to each other. Power lines88(VDD) and88(VSS) also extend to the top boundary and the bottom boundary, respectively, of inverter cell104. Vertical semiconductor bars22N and22P and backside contact plugs80are also illustrated to show the relative positions of these illustrated features, and are illustrated as being dashed since these features are not in the illustrated plane.

FIG.18Billustrates a top view obtained at cross-section18B-18B inFIG.17. In the illustrated plane, gate dielectric28P and gate electrode30P encircle vertical semiconductor bar22N, and gate dielectric28N and gate electrode30N encircle vertical semiconductor bar22P. Accordingly, the respective vertical transistors100N and100P are also vertical GAA transistors.

FIG.18Cillustrates a top view obtained at cross-section18C-18C inFIG.17. In the illustrated plane, front side power lines56(VDD) and56(VSS) extend from the left boundary to the right boundary of inverter cell104, and are parallel to each other. Power lines56(VDD) and56(VSS) also extend to the top boundary and the bottom boundary, respectively, of inverter cell104. Furthermore, signal metal lines64(including64G and64D) have lengthwise directions perpendicular to the lengthwise direction of power lines56(VDD) and64(VSS). Metal line64G is connected to the gates of vertical transistors100N and100P through via60B, and is connected to the input of the inverter cell104. Metal line64D is connected to two vias60A, and is connected to the drains of the vertical transistors. Metal line64D is also connected to vias48, and may act as the output of inverter cell104. As shown inFIG.18C, it is possible to shift the via60B slightly left, and vias60A slightly right, so that they are not electrically shorted to each other.

By conducting the front side power lines64(VDD) and64(VSS) to the respective backside power lines88(VDD) and88(VSS), and connecting the lower source/drain regions to the backside power lines88(VDD) and88(VSS), the device cells formed using the vertical transistors may be smaller than if the power lines are only on the font side of the vertical transistors. For example, referring toFIG.18B, if there are no backside power lines, deep vias may have to be formed at positions110inFIG.18Bin order to provide VDD and VSS to the source regions of the vertical transistors. Also, since the drain regions are directly over the vertical semiconductor bars22N and22P, the interconnection of the drain regions cannot be achieved using a straight metal line directly interconnecting the drain regions since the straight metal line will be shorted with the gate. Accordingly, the interconnection of the drain regions has to run sideway to the left or right (as schematically illustrated by dashed line112). The respective inverter cell104thus will occupy more chip area. For example, the front-side powered inverters may occur 35 percent more chip area than double-side powered inverters.

The double-side powered inverters may be stored as a standard cell in a cell library. Also, other standard cells formed of vertical transistors may also occupy smaller chip areas than the respective front-side powered standard cells. Accordingly, these standard cells may also be laid out using double-side powered cells and stored in cell library. For example,FIGS.19A,19B, and19Cschematically illustrate a lower level, a middle level, and an upper level of a NAND cell122, wherein the top views are obtained from the same levels as that ofFIGS.18A,18B, and18C, respectively.FIGS.20A,20B, and20Cschematically illustrate a lower level, a middle level, and an upper level of a NOR cell124.FIGS.21A,21B, and21Cschematically illustrate a lower level, a middle level, and an upper level of an AND-OR-Invert (AOI) cell126. The details of these cells may be realized from the disclosure of the inverter cell104, and are not discussed in detail herein.

With the design of the front-side and back-side power lines, the standard cells may be placed next to each other to form functional circuits. Accordingly, the front-side power lines of the neighboring cells are joined to each other to form long power lines, and the back-side power lines of the neighboring cells are joined to each other to form long power lines. Furthermore, in both of the front side and the backside, VDD lines and VSS lines may be allocated alternatingly.

The embodiments of the present disclosure have some advantageous features. By conducting front-side power lines to the backside of vertical transistors, and supplying power to the lower source/drain regions of the vertical transistors from the backside power lines, the chip area of the resulting circuit is reduced. The design and the layout of the circuits are also more flexible.

In accordance with some embodiments of the present disclosure, a method includes forming a first vertical transistor comprising forming a first vertical semiconductor bar over a substrate; forming a first gate dielectric and a first gate electrode encircling the first vertical semiconductor bar; forming a first source/drain region over a top surface of the first vertical semiconductor bar; removing the substrate to reveal a bottom surface of the first vertical semiconductor bar; and forming a second source/drain region contacting the bottom surface of the first vertical semiconductor bar; and forming a first backside power line, wherein the first backside power line is on a bottom side of the first vertical semiconductor bar, and wherein the first backside power line is connected to the second source/drain region.

In an embodiment, the method further comprises forming a first front-side power line over the first source/drain region; and forming a first deep via connecting the first front-side power line to the first backside power line. In an embodiment, the first deep via comprises opposing surfaces in physical contact with the first front-side power line and the first backside power line. In an embodiment, the first front-side power line and the first backside power line have lengthwise directions parallel to each other. In an embodiment, the method further comprises forming a source/drain contact plug electrically connecting to the second source/drain region, wherein the source/drain contact plug comprises a portion overlapping a portion of the first front-side power line.

In an embodiment, the first front-side power line and the first backside power line are VDD lines, and the method further comprises forming a second front-side power line parallel to, and in a same metal layer as, the first front-side power line, wherein the second front-side power line is a VSS line; and forming a second backside power line parallel to, and in a same metal layer as, the second front-side power line; and forming a second deep via between, and physically contacting both of, the second front-side power line and the second backside power line.

In an embodiment, the method further comprises forming a second vertical transistor comprising forming second vertical semiconductor bar over the substrate; forming a second gate dielectric and a second gate electrode encircling the second vertical semiconductor bar; forming a third source/drain region over a top surface of the second vertical semiconductor bar; and after the substrate is removed, forming a fourth source/drain region contacting a bottom surface of the second vertical semiconductor bar.

In an embodiment, the method further comprises forming a gate pad connecting the first gate electrode to the second gate electrode; and forming a vertical contact plug over and contacting the gate pad. In an embodiment, the forming the first source/drain region and the forming the second source/drain region comprise selective epitaxy processes. In an embodiment, the method further comprises depositing a passivation layer underlying and contacting the first backside power line.

In accordance with some embodiments of the present disclosure, a structure comprises a first vertical transistor comprising first vertical semiconductor bar; a first gate dielectric and a first gate electrode encircling the first vertical semiconductor bar; a first source/drain region over a top surface of the first vertical semiconductor bar; a second source/drain region contacting a bottom surface of the first vertical semiconductor bar; a first front-side power line overlying the first vertical transistor; and a first backside power line electrically connected to the first front-side power line, wherein the first backside power line is underlying the first vertical semiconductor bar, and wherein the first backside power line is connected to the second source/drain region.

In an embodiment, the structure further comprises a second vertical transistor comprising a second gate electrode electrically connecting to the first gate electrode. The structure further comprises a second front-side power line over the first vertical transistor and parallel to the first front-side power line; and a second backside power line electrically connected to, and overlapped by the second front-side power line, wherein the first backside power line is a VDD line, and the second backside power line is a VSS line. In an embodiment, the first vertical transistor and the second vertical transistor form an inverter.

In an embodiment, the structure a deep via between, and in contact with both of, the first front-side power line and the first backside power line. In an embodiment, the first source/drain region and the second source/drain region comprise epitaxy semiconductor regions. In an embodiment, the first front-side power line and the first backside power line are elongated, and comprise lengthwise directions parallel to each other. In an embodiment, the structure a blanket passivation layer on a backside of the first vertical transistor and contacting the first backside power line, wherein the blanket passivation layer is free from conductive features penetrating through.

In accordance with some embodiments of the present disclosure, a structure comprises a first vertical transistor comprising a first vertical channel; and a first gate electrode encircling the first vertical channel; a second vertical transistor comprising a second vertical channel; and a second gate electrode encircling the second vertical channel; a gate pad connecting the first gate electrode to the second gate electrode; a gate contact plug over and contacting the gate pad; a front-side VDD power line and a front-side VSS power line over the first vertical transistor; and a backside VDD power line and a backside VSS power line underlying the first vertical transistor, wherein the backside VDD power line is overlapped by, and is electrically connected to, the front-side VDD power line, and the backside VSS power line is overlapped by, and is electrically connected to the front-side VSS power line.

In an embodiment, the first vertical transistor comprises an upper source/drain region over the first vertical channel; and a lower source/drain region under the first vertical channel, wherein the lower source/drain region is connected to one of the backside VDD power line and the backside VSS power line. In an embodiment, the first vertical transistor and the second vertical transistor are interconnected as an inverter.