Pulse time detector, a controller for a switched mode power supply, and a switched mode power supply including such a controller

An apparatus for monitoring the pulse time of switches within a DC to DC power supply, comprising a timing circuit responsive to a switching confirmation signal to commence timing and to monitor for control signals being sent to the switch and to indicate whether elapsed period between the switching confirmation signal and the control signal is too long or too short.

FIELD OF THE INVENTION

The present invention relates to a pulse time detector for monitoring pulse times in a switched mode power supply, to a controller for a switched mode power supply including such a detector, and to a switched mode power supply controlled by the controller.

BACKGROUND OF THE INVENTION

It is well known that DC to DC converters can be made to step down, that is BUCK, or step up, that is BOOST, a DC input voltage to a different DC output voltage. The DC to DC converter may comprise an inductor in association with two or more transistors such that the current in the inductor can be built up such that energy is stored in it by virtue of its magnetic field, and then that energy can be discharged from the inductor in order to charge a storage capacitor at the output of the DC to DC converter.

Where a DC to DC converter operates with, for example, a battery as the input voltage source then the battery voltage may change as the battery discharges. Thus a converter may initially be required to BUCK the input voltage, but as the battery discharges it may move into a BOOST mode. It follows that at some time the input voltage may be close to the output voltage. This regime can be difficult to control.

It should be noted that such inductor based DC to DC converters inherently require a ripple current to occur in the inductor otherwise the converter loses its ability to regulate its output voltage in response to changes of load current. It becomes important to be able to control this ripple.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention there is provided an apparatus for monitoring a pulse time of one or more switches within a DC to DC power supply mode, comprising a timing circuit responsive to a switching confirmation signal to commence timing and to monitor for control signals being sent to the one or more switches and to indicate whether an elapsed period between the switching confirmation signal and the control signal is too long or too short.

It is thus possible to commerce the timing of all time periods from a single event. This avoids the build-up of excessive cumulative delays due to “guard periods” where one timing period is triggered by the expiration of a preceding period. This has a significant benefit. The uncertainty in device performance, eg. propagation delays and switching or decision times in components resulting from process variations during manufacture and/or changes in temperature and/or voltage supply, mean that it is common to build a “guard time” into time windows to account for the difference between the fastest and the slowest device of a batch of devices, or of devices that fall with an acceptable device specification. By triggering time windows in sequence, where the commencement of one window depends on the completion of a previous window, then the guard times become summed and consequently the aggregated guard time becomes unnecessarily long. For a device working in a cyclical manner, the unnecessarily long guard time reduces the operating frequency (or if you prefer lengthens the cycle time) beyond that necessary for satisfactory operation of the device.

The limit on operating frequency that the summed guard times impose may limit device performance.

According to a second aspect of the invention there is provided a controller for a DC to DC converter including an apparatus for monitoring pulse time according to the first aspect of the invention.

Preferably the controller is arranged to cause an offset to be generated and applied to signals or comparators in signal paths used to control first and second switches of the DC to DC converter. The first switch controls current flow from an input to a first node of the inductor, and the second switch controls current flow between the second node of the inductor and a common conductor, which acts as a local ground.

According to a third aspect of the present invention there is provided a method of monitoring pulse times of at least one switch within a DC to DC power supply, comprising the steps of:a) monitoring for receipt of a switching confirmation signal which confirms that a switch has reached a desired switching state;b) starting at least one timer in response to the switching confirmation signal;c) monitoring for receipt of a control signal to revert the switch from the desired state;d) comparing an elapsed time as measured by the timer with threshold values and indicating whether the time period from the switching confirmation signal to receipt of the control signal was too long or too short.

Advantageously the DC to DC power supply has first and second switches, the first switch in series between an input node and a first terminal of the inductor and the second switch located between a second terminal of the inductor and a local ground, and the method is responsive to control signals for each of the first and second switches.

DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

A DC to DC voltage converter operable to increase, i.e. BOOST, an input voltage Vinor to reduce, i.e. BUCK, an input voltage Vinis shown inFIG. 1.

The converter comprises an input node2which is connected to a first terminal4of an inductor6via a first electrically controlled switch51. A second switch S2extends between a second terminal8of the inductor6and ground (which may be a “local ground”). A third electrically controlled switch S3extends between the first terminal4of the inductor6and ground. A fourth switch S4extends between the second terminal8of the inductor6and an output node10. A filtering capacitor12is connected between the output node10and ground. The switches S3and S4provide commutation paths and act as active rectifiers. They can be replaced by diodes if desired, and it is advantageous to have diodes placed in parallel with S3and S4.

Only one “ground” is shown but sometimes a designer may choose to implement several “grounds” by virtue of using different conductors to provide the grounds. This allows one ground to be used for switching currents, for example as flow through S2and S3, whilst other grounds are used for quieter lines, such as control signals, so as to reduce cross talk resulting from variations in the ground voltage due to current flow in the conductors acting as a ground.

The switches are driven by a controller20which provides control signals to the switches.

The basic operation of the converter circuit is well known, but will be briefly described for completeness.

Buck Converter Mode

In this mode Vinis greater than Vout. The controller acts to generate a desired output voltage Voutfrom the input voltage Vin. This can be achieved by selectively controlling the states of switches S1and S3. In this mode S2is kept permanently open (high impedance) and S4is kept closed (low impedance).

Switches S1and S3are driven in anti-phase. This ensures that both switches are not simultaneously conducting which would cause the input voltage Vinto short circuit to ground.

In a first phase, which can be regarded as a magnetisation phase, S1is closed and S3is open. Therefore the voltage across the coil, Vcoil, is
Vcoil=Vin−VoutEquation 1
and the rate of change of current, and more particularly of current build up is given from

This current flows for a first time period t1as shown inFIG. 2, towards the output node10where some of the current is supplied to a load and some of the current charges the capacitor12such that a small increase occurs in the voltage Voutacross the capacitor.

The controller20monitors the output voltage Voutand a regulation loop within the controller causes switch S1to open and switch S3to close.

This causes the voltage across the inductor to become
Vcoil=0−Vout=−VoutEquation 3

Consequently the rate of change of current flow in the inductor6becomes

Thus, in a second period the current flow in the coil6starts to decrease, as shown in period t2. Meanwhile current is being drawn from the load so the voltage Voutmay fall a little. This process, which can be regarded as a switching cycle or a control cycle, is repeated by the controller, typically at a repetition rate of 500,000 to 3,000,000 times per second. These values are for illustration only and are not limits. This provides very fine control of the input voltage and the voltage ripple thereon.

It can be seen inFIG. 2that the instantaneous current varies around an average value Iavewhich represents the average current being drawn by the load—and assumed for simplicity to be constant over the two switching cycles shown inFIG. 2.

Boost Mode

When it is desired to make Voutgreater than Vin, then the circuit can be operated in a BOOST mode.

In this mode switch S1is left closed (low impedance) and S3is left open (high impedance). Switches S2and S4are operated in anti-phase.

During a magnetisation phase S4is opened and S2is closed. Therefore the voltage across the coil is given by
Vcoil=Vin−0=VinEquation 5
and consequently the rate of change of current in the coil is given by

ⅆIⅆt=VinLEquation⁢⁢6
so the current builds relatively rapidly. After a time period t3, shown inFIG. 3, the controller20opens switch S2and simultaneously closes switch S4.

Current from the coil now flows towards the load and into the output capacitor12, thereby charging it, as the magnetic flux around the coil collapses.

During this phase the voltage across the coil is

This can be considered as a demagnetisation phase, and is designated t4inFIG. 3.

Without going into rigorous analysis, it can be shown that if a duty cycle D represents the proportion of the time that switch S1is conducting then, for the BUCK converter
Vout=Vin·DEquation 9

If the duty cycle represents the proportion of time that the switch S2is conducting, then for the BOOST converter

These BUCK and BOOST converters work very well when the difference between Vinand Voutis relatively large.

The operation of the controller20can be quite simple if the converter is always going to be in BUCK mode or always going to be in BOOST mode.

A controller operable in both BUCK and BOOST mode is shown inFIG. 4. Such a controller comprises voltage error amplifier30which receives the output voltage (optionally via a resistive attenuator not shown) at one input of the amplifier with a reference voltage supplied to the other input of the amplifier. In this example the reference voltage is provided to the non-inverting input, but the person skilled in the art could design equivalent circuits where this was not the case. The amplifier30forms an output Vea which is a function of the difference between the output voltage and the reference voltage, as modified by a gain G1of the amplifier30.

The output of the amplifier30is supplied to an input of a comparator34in a circuit which can be regarded as a BUCK circuit of the converter. A further input of the comparator is often provided with a signal which, in this example, is from a current sensing circuit that senses the current in the inductor coil. This could be done by, for example a hall effect sensor, but is often performed by measuring the voltage dropped across an ohmic impedance in series with the inductor coil, or by measuring the voltage dropped across transistor S1. However, in this example the coil current is not directly measured but is instead estimated by a coil current emulator60which is the subject of a co-pending patent application and will be described later. The output of the comparator34is provided to a reset input of a set-reset latch38.

An output of the set-reset latch38forms the “S1-drive” signal used to control S1to cause current to be built in the inductor.

A clock signal (i.e. a periodic signal) from a clock circuit (not shown, but known to the person skilled in the art) initiates the start of each control cycle within the controller20. The clock circuit generates a short pulse “clkbuck” at periodic intervals and which is provided to the reset input of the set-reset latch38. This causes the signal “S1-drive” to be removed, and hence the transistor switch S1becomes non-conducting.

The estimated or sensed coil current is compared with the voltage error signal Vea by comparator34, and once the current (as converted to a voltage VITC) becomes less than Vea then the comparator output is asserted, and this sets the set-reset latch causing the “S1-drive” signal to asserted, and coil in the inductor to increase.

It can be seen that this circuit as described so far is operable as a BUCK converter.

A BOOST section is also provided. It can be seen that the boost section has a second comparator134analogous to comparator34. The second comparator receives the output VITCrepresenting the instantaneous current in the inductor6at one input thereof, and a version of the error voltage Veap, subject to possible offsetting at another input thereof. An output of the comparator134is provided to a reset terminal of a set-reset latch138. An output of the latch is used to drive the second switch S2and S4as the compliment of the drive to S2. The set terminal of the latch138receives a BOOST clock signal, “clkboost”. Thus the occurrence of the clkboost signal causes latch138to be set thereby giving rise to a signal S2-drive to close switch S2. Once the inductor current (as represented by VITC) exceeds Veap the comparator resets latch138thereby inhibiting S2-drive.

clkbuck and clkboost have the same frequency as each other.

The switch control signals can be used to directly drive the switches directly if only S1and S2are present. However when switches S3and S4(ofFIG. 1) are also provided then as shown here the switch control signals from the latches38and138are used as inputs to a switch control state machine62that controls the electronic switches. The state machine may set one or more flags, as represented by output64, to indicate the state of each of the switches S1and S4.

However, and as noted before, the operation of the converter can become compromised when the difference between Voutand Vinstarts to fall.

This can be seen because each converter relies on there being a change in the current flowing through the coil during the control cycle. But if Vinand Voutare nearly equal then the rate of increase of current in the magnetisation phase of, for example, the BUCK converter

ⅆIⅆt=(Vin-Vout)LEquation⁢⁢11
and the rate of decrease in the demagnetisation phase of the BOOST converter

ⅆIⅆt=Vout-VinLEquation⁢⁢12
both tend to zero.

A way to overcome the problem of Vinbeing similar to Voutis to deliberately induce a current ripple. This is done in a “buck-boost” window where switches S1and S2are made conducing in each control cycle.

In such a regime each control cycle has several phases.

FIG. 5shows the switching events in a converter operating in a BUCK-BOOST mode as the input voltage drops from 3.6 V to 3.3 V and then to 3 V, whilst Voutis 3.3 V.

It can be seen that each of the cycles has a slow current change region50ato50c. Here switch S3is not conducting, S1is conducting, switch S4is conducting and S2is not conducting. Thus the voltage across the inductor is Vin-Vout. Consequently at50athe current builds slowly, at50bthere is no change in current and at50cthe current actually reduces slowly.

Each cycle also has a period52of fast current build when S1and S2are both conducting, and S3and S4are off. Once the current has built to a sufficient level as determined by the controller20then, S2is opened again (made non-conducting) giving rise to slow current change in regions54ato54c.

Finally a discharge phase occurs when S1is off and S2is off, so S3and S4are on, as indicated by region56.

Because the controller20is responsive to the coil current and the output voltage, then the duration for which S1is off and for which S2is on varies. Thus when Vinis greater than Voutthe time for which switch S2is on is short (and ultimately is zero for pure BUCK operation). As Vintransitions from a bit above Voutto a bit less than Voutit can be observed that the off time for S1decreases and the on time for S2increases.

If the input voltage falls further then switch S1becomes permanently on and we enter pure BOOST operation.

It should be noted that were a BUCK-BOOST controller includes two separate control paths (i.e. a BUCK section and a BOOST section) that can operate concurrently for a given range of input voltage, Vin, then the paths can have their overlap of operation varied by introducing an offset between the paths. The offset can be introduced in any suitable form, i.e. a voltage, a current, a time offset between clock pulses or a digital offset. The present invention can be applied to any control system which varies relative performance of each channel via a varying offset.

However it is necessary to control the relative timing and duration that the switches are on if excessive currents are not to flow in the inductor or regulation is not to be lost. Control strategies divide into

1) voltage mode control

2) current mode control

An example of current mode control is given in U.S. Ser. No. 12/001,700. Here a measurement of the coil current is made. The peak coil current is measured and converted to a sensing voltage Vcur. This is then compared with the voltage error signal. This approach removes one of the 0 Hz poles which would occur in the control loop is a voltage mode control is adapted.

However measuring the current is not trivial. Often the inductor current IL is extracted by measuring the voltage dropped across the first switch S1, which is typically a FET.

This requires the FET to be conducting, and any voltage bounce/ripple to have died away. This typically requires a measurement guard time to be introduced.

Thus, current measurement problems are introduced, but control loop stability is improved.

There are however, further undesirable real world component effects that need to be accounted for, and which can introduce time delays into the control loop, and hence further compromise operation1) the comparators do not switch instantly, and may exhibit significant delays.2) The time to turn the switches on and off varies with temperature and can run into 10's of nanoseconds.

Returning toFIG. 4, an emulator60may take the place of a current sensor. The emulator receives as its input a signal LX1representing the voltage at the first node of the inductor. The signal LX1can, as shown, be measured at the first node of the inductor, or it can be inferred from knowledge of the supply voltage Vinand knowledge of the state of the first switch S1(from the state machine62) associated with the first node of the inductor and which, in conjunction with switch S3, controls whether the first node of the inductor is connected to Vin(e.g. the first voltage) or to ground (the reference voltage). Indeed, if the supply voltage is quite stable then the emulator60could be solely responsive to the switch control state machine62.

The emulator60, by forming an idealised estimate of the instantaneous current in the inductor, removes the noise associated with trying to form an instantaneous measurement.

The emulator60can also change the transfer function of the control loop.

The emulator can be fabricated in many ways, and can be fabricated so as to work in the analog domain or the digital domain—for example as on up/down counter.

The emulator60comprises a current source which generates a current Ichargeproportional to the input voltage Vin
Icharge=Gs·Vin
where Gsrepresents a transconductance term.

The current Ichargeis selectively supplied to a capacitor82when the signal LX indicates that switch S1has closed.

When S1is closed, the rate of current charge in the inductor is

The current source80models the term

VinL.
To model the term

-VoutL
a current sink84is provided to pass a current Idischargewhere
Idischarge=Gs·Vout

The current flow to the current sink is controlled by a switch responsive to LX2(and optionally LX1, as shown inFIG. 4).

Also, as shown inFIG. 4, it is desirable to constrain the voltage across the capacitor to ensure it always takes sensible values. To this end, a leakage path via resistor100to a voltage source102is provided, so as to urge the voltage across the capacitor82towards the voltage of the voltage source102. This compensates for drift that may occur in the scaling of the current source and sink or as a result of errors in measuring Vinor Vout.

The arrangement ofFIG. 4also includes a variable offset generator180responsive to an offset control circuit182. In this embodiment the offset generator180is inserted in the signal path to the inverting input of comparator134. The skilled person will appreciate that an equivalent offset could be applied in the signal path to the non-inverting input or that current steering within the comparator (which typically has a long tail pair) could be implemented to introduce a bias into the long tail pair so as to give a controllable offset in the comparator's response. Alternatively, as disclosed in U.S. Ser. No. 12/001,700 an offset can be introduced into the signal paths to both comparators.

Other controller configurations are possible.FIG. 6, which is taken from U.S. Ser. No. 12/001,700 shows a circuit where signal path between the amplifier30and the comparators34and134is interrupted by an offset amplifier that produces two versions of Vea labelled VCABUCK and VCABOOST which are centred about Vea and separated by a voltage ΔV generated by a voltage generator202, which is responsive to an offset control circuit, like item182ofFIG. 4.

It also shows a current measuring circuit, designated112whose operation is known by the person skilled in the art.

This offset provided by offset generator180or202is used to correct for the effects of delay in the comparator switching times (which may be asymmetric) and the delay in FET turn on time and FET turn off times. These again may be asymmetric in that one is faster than the other.

Returning toFIG. 4, we might expect that asserting “clkboost” would immediately cause S2to conduct. However, real logic gates exhibit a signal propagation delay. Similar delays occur between “clkbuck” being asserted, thereby instructing switch S1to be opened. Propagation delays in excess of 20 ns are typical.

Also, as shown inFIG. 4it can be seen that the size of the offset produced by the offset generator180controls the difference between the values of Vea and Veap and hence the overlap range for which both controllers are active to create a buck-boost window. One suitable algorithm for controlling the overlap is disclosed in U.S. Ser. No. 12/001,700 which is incorporated herein by reference (and more specifically page 12 line 12 to page 19 line 18, and associated drawings) and which discloses a scheme for controlling the length of the transistor switching times when operating in the BUCK-BOOST regime, and indeed it also functions correctly outside of the BUCK-BOOST window.

U.S. Ser. No. 12/001,700 teaches that in order to compensate for the delays that can occur between asserting a control signal for a transistor to switch on or off, and the transistor actually switching on or off, then it is necessary to measure the times for which the transistors are actually conducting. This can be achieved simply by measuring the voltage at the node4, so as to determine whether S1is conducting, or at the node8so as to determine whether S2is conducting. If S1is not conducting and current flow in the inductor is from node4to node8which corresponds to the “Forward” flow. then the voltage at node4is either zero volts, when S3is an active rectifier or −0.7 volts when a fly-back diode is used. However if the current flow in the inductor is in reverse (which could happen if the load current drops to a very low value or if the load has a reactive component) then the voltage at node4could rise above Vin, until such time as a normally reverse biased diode (not shown) in parallel with S1starts conducting. Similarly the voltage at node8for forward current flow is either zero volts when S2is conducting or Voutwhen it is not. For reverse current flow conditions node8is at Voutif S4is conducting, zero volts if S2is conducting or −0.7 V if S2and S4are briefly both off and the flyback diode around S2switches on. Therefore the times for which the transistors are conducting and not conducting can be easily determined. We are generally interested in when switch S1goes non-conducting, which is determined by the voltage at node4going low, and also the time for which S2is conducting, which is shown by a voltage at node8going low.

The times for which the voltages should be low are known to the controller, and the time is for which the voltages actually go low can be compared to transition windows. The transition window is made up of two parts, which in FIG. 10 of U.S. Ser. No. 12/001,700 10 are designated by two distinct shadings. The first part of a transition window indicates a time mask which measures whether the duration for which the corresponding node is at the expected voltage is too short. The second time mask marks the time range in which a switching transition is expected to occur. To put this in context, consider a first pulse which corresponds to transistor S1switching off. The first mask time is initiated at the time the switching signal is sent to the transistor S1and results in a transition occurring at node4. It then times out the first period and a check is made to see whether the transistor S1has switched during that period, as represented by a further transition at node4. The second period202is then commenced which indicates a period in which the transistor switching is expected. At the end of that period if a switching has not occurred, as shown by a change in voltage at node4, then it is known that the pulse exceeds its desired duration. Steps can then be made to change the duration of the pulse. Based on these measurements the pulse width can be varied. Similar measurements are taken for the pulses at the second terminal of the inductor. The controller varies the individual pulse durations using a relatively simple control strategy in which:i) For each one of the time periods, the durations of the pulses are measured.ii) If both the pulses are too short (which includes one or other of them not existing at all) then the duration of the pulses are increased.iii) If both pulses exist, but one of them exceeds the desired duration, then the duration of the pulses are decreased.

For all other conditions, such as both pulses the correct size, one pulse the correct size and the other too short or one pulse greater than the correct size and the other missing, then no alteration to the pulse lengths are made.

The pulse lengths can be varied by changing the value of ΔV generated by the voltage generator202or180.

The technique works well.

As noted before, in practice a state machine is used to control the switches to make sure that S1and S3cannot be on at the same time. This does however give rise to a minimum duration below which the switch cannot transition. This duration set by the state machine or by the reaction time of the transistor switches is often in the range of 6 to 30 ns, and typically around 15 ns.

This means that if the control strategy seeks to reduce the switch on or off time below 15 ns, the switches will not respond more quickly and hence control is impaired. Under such circumstances the switching time of the complimentary pulse in the control strategy needs to be adjusted instead.

The time mask to detect the “too short” period needs to exceed the minimum switching period with a suitable margin of error. In practice this means that the first period corresponding to the pulse being too short needs to be at least 32 ns. If we then account for process and temperature variations this means that the mask time typically ranges between 32 and 50 ns. The other mask period is typically between 50 and 90 ns.

The duration of these windows limit the maximum switching frequency of the regulator. If, in use, the controller sees minimum switching durations of LX1and LX2of 80 ns (resulting from guard periods) or so then this is reasonable for a controller switching at 2.5 MHz (so 400 ns per cycle). However for a controller operating at 6 MHZ (so the control period has a cycle time of 160 ns) then this corresponds to the sum of the mask periods used as part of the control strategy and hence the by pass time for which the rapid current build is actually enabled would be almost zero, leading to poor efficiency and poor regulation.

The algorithm described in the earlier application works well, but the mechanism for determining in the pulses for fast charge (LX2=0, slope=+Vin/L, LX2=node8) and fast discharge (LX1=0, slope=−Vout/L, LX1=node4) are too long or too short can be improved for use at higher repetition rates.

An embodiment of the invention changes the way in which the too short, OK and too long times are calculated.

Firstly, rather that setting the “too short” time to start when a voltage transition occurs at node4or8, as appropriate, instead the state machine is adapted to assert a signal when for example switch S2has received a switch on signal at its gate and has started conducting, and this signal from the state machine, which can be regarded as a “switching confirmation signal” that is used to set the commencement of the “too short” mask period. The signal from the state machine may additionally or alternatively set the commencement of the “too long” mask period. This has an advantage in that the LX1and LX2signals (from nodes4and8) no longer need to be measured, but instead every timing measurement can be derived from the control signals provided by the state machine.

As a consequence the “too short” mask period can be reduced in duration as it no longer has to include the various propagation delays from the time “clkbuck” is asserted to the time the switch can reasonably be expected to start conducting. Similarly the too long period no longer needs to include an uncertainty carried over from the guard periods inserted into the “too short” period. As a consequence the duration of the too short mask can be reduced to around 10 ns or so, and the too long mask can set up a few 10's of nanoseconds after the end of the too short mask has finished.

FIG. 7shows exemplary timing diagrams relating to the control of the second switch S2.

The clkboost signal sets the Set-reset latch and hence causes a signal to switch transistor S2on to be asserted. The state machine that controls S2and S4sets up the necessary delays to avoid a short circuit and asserts a flag when S2is on. Concurrent with, or substantially concurrent with, setting of this flag, the “too short” mask is asserted and the “too long” mask timer is started. The “too short” mask can be considered as extending from time m1to m2as measured from the switching confirmation signal which here is “flag S2=ON”. The too long mask extends from a time m3after the switching confirmation signal, optionally to a limit time m4.

The stop signal, which acts as a control signal, is asserted by the comparator134(FIG. 4) when the voltage at its input reaches an appropriate level. We can see that there are broadly three cases to consider:1) Too short: When the “stop” signal has its rising edge during the mask too short period230, or even earlier, such as before the S2on flag is set, then we know that the control algorithm is trying to switch the transistor off when hardly any ON time has elapsed. This gives rise to only a very small current ripple and hence very poor regulation.2) Too long: When the stop signal has it rising edge long (in relative terms) after the S2on flag was asserted and during the “too long” mask period240then this indicates that the controller has plenty of margin to reduce the duration of the ON state of S2. Too long an ON time may give rise to excessive switching losses.3) Not too long or to short: Here the On time is within an acceptable range of values.

A similar approach can be applied to S1, as shown inFIG. 8. Here, the clkbuck signal is applied to the reset input of the set-reset gate that is in the signal path to switch S1. Thus the clock launches a switch off sequence for S1. The state machine can either ser a flag when S1is off, or as shown here, set a flag when S3switches on. Setting of this flag initiates “too short” and “too long” masks. From here the operation is as described earlier.

Consequently the control strategy can be used in which:1) For each one of the time periods, the durations of the pulses are measured.2) If both the pulses are too short (which includes one or other of them not existing at all) then the duration of the pulses are increased.3) If both pulses exist, but one of them exceeds the desired duration, then the duration of the pulses are decreased,4) For all other conditions, such as both pulses the correct size, one pulse the correct size and the other too short or one pulse greater than the correct size and the other missing, then no alteration to the pulse lengths are made

This regime allows the guard times used in U.S. Ser. No. 12/001,700 to be reduced and hence the controller can be used at higher switching speeds. The control algorithm described in that patent can be used, and the durations of the switching pulses can be adjusted by varying the offset voltage.

This revised control scheme can also be used in other switching controllers. By not having to include ground times because of propagation delays or measure the times a much faster response can be achieved, and the “too short” time can be reduced.

The apparatus for monitoring pulse times can be used with any BUCK-BOOST controller independent of whether the control loop implements voltage mode control or current mode control.