Method and system for diagnosing a semiconductor wafer

Methods and systems for diagnosing semiconductor wafer are provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image includes a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.

BACKGROUND

In semiconductor technology, the wafers, each having multiple chips, are produced by a plurality of processes/stages in a wafer fabrication facility (FAB). Each process/stage can introduce one or more defects into the semiconductor wafers, which leads to quality and reliability issues, failures, and yield losses. To improve manufacturing technologies and enhance wafer quality, reliability, and yield, the semiconductor wafers are measured, tested, monitored and diagnosed at each process/stage. In order to obtain accurate results, alignment is important in a measured, tested, monitored and diagnosed semiconductor wafer.

DETAILED DESCRIPTION

In integrated circuit (IC) design, a variety of functions are integrated into one chip, and an application specific integrated circuit (ASIC) or system on a chip (SOC) cell based design is often used. In this approach, a library of known functions is provided, and after the functional design of the device is specified by choosing and connecting these standard functions, and proper operation of the resulting circuit is verified using electronic design automation (EDA) tools, the library elements are mapped on to predefined layout cells, which contain prefigured elements such as transistors. The cells are chosen with the particular semiconductor process features and parameters in mind and create a process parameterized physical representation of the design. The design flow continues from that point by performing placement and routing of the local and global connections needed to form the completed design using the standard cells.

After design rule checks, design rule verification, timing analysis, critical path analysis, static and dynamic power analysis, and final modifications to the design, a tape out process is performed to produce photomask generation data. This photomask generation (PG) data is then used to create the optical masks used to fabricate the semiconductor device in a photolithographic process at a wafer fabrication facility (FAB). In the tape out process, the database file of the IC is converted into a Graphic Database System (GDS) file (e.g. a GDS file or a GDSII file). The GDS file is then used to make various layers of masks for integrated circuit manufacturing. Specifically, the GDS file became the industry's standard format for transfer of IC layout data between design tools of different vendors.

At present, a golden wafer is selected from a lot of wafers, and the golden wafer is used as a template wafer to measure, test, monitor or diagnose the other wafers in the lot of wafers. For example, a reference image is captured from the golden wafer, and the reference image includes information regarding contour and contrast of the golden wafer. The reference image is used to perform alignment and measurement for the other wafers, so as to verify these wafers. If a verification result is normal, the subsequent process/stage is performed for the verified wafer.

FIG. 1shows a simplified flowchart of a method100for diagnosing a semiconductor wafer, in accordance with some embodiments of the disclosure. It should be noted that additional processes may be provided before, during, and/or after the method100ofFIG. 1, and that some processes may only be briefly described herein. Furthermore, the method100ofFIG. 1can be performed at one or more process/stage for the semiconductor wafer.

Referring toFIG. 1, a target image is obtained according to a graphic data system (GDS) information of a specific layout of an integrated circuit (IC) (S110ofFIG. 1), and the IC will be implemented in a semiconductor wafer. In reality, as will be appreciated by persons skilled in the art, processing circuitry is utilized in the implementation of the invention, and the target image is represented by (or embodied in) an electrical signal. Thus, when it is said that the target image is obtained, it will be understood that an electrical signal embodying the target image is obtained via circuitry. The target image is a template for diagnosing the semiconductor wafer in a specific process/stage. In some embodiments, each process/stage has its own target image. Moreover, the specific layout is a fractional layout of the IC. The fractional layout includes a multi-layer structure of the IC. In some embodiments, the target image includes information regarding a pattern contour corresponding to the specific layout in the semiconductor wafer. For example, the target image includes a first contour, and the first contour has a first pattern corresponding to the specific layout.

FIG. 2shows a schematic view of a target image210in one example. InFIG. 2, the target image210includes a first contour220having a first pattern corresponding to a specific layout. By performing image processing according to the GDS information, the first contour220is clear in the target image210, and no contrast component is shown in the target image210.

Because the first contour220in the target image210is clear and obvious, a high quality alignment image is provided according to the GDS information. For example, due to distortion of the golden wafer, a scanning electron microscope (SEM) controls the alignment weight of the contour and the contrast to obtain the reference image, such as a first weight (e.g. 30% contour+70% contrast) being modified to a second weight (e.g. 100% contour+0% contrast).

The SEM can scan a focused electron beam over a surface of the golden wafer to create the reference image. The electrons in the beam interact with the sample, producing various signals that can be used to obtain information about the surface topography and composition.

In some embodiments, various algorithms can be used to perform image processing in the first contour of the target image. Thus, the first contour of the target image will be closer to the actual situation for alignment. For example, the degree of smoothing can be modified for a line profile created from the first contour of the target image.

Referring back toFIG. 1, after obtaining the target image, an image-based alignment is performed, so as to capture a raw image from the semiconductor wafer according to the first contour of the target image (S120ofFIG. 1). For example, according to the information of target image (e.g. the contour and the related coordinates), the SEM can scan the beam across a selected area corresponding to the related coordinates, and the generated signals are recorded and thereby the raw image is formed pixel by pixel. Valuable information about morphology, surface topology and composition can be obtained in the raw image. The SEM microscopes achieving resolutions below 1 nm are available now.

In some embodiments, when the image-based alignment is performed, a second contour on the semiconductor wafer is compared with the first contour of the target image. When a second pattern of the second contour is identical to the first pattern of the first contour, the raw image having the second contour is captured from the semiconductor wafer.

After obtaining the raw image, the semiconductor wafer is diagnosed by measuring the obtained raw image, and then a diagnostic result of the semiconductor wafer is obtained (S130ofFIG. 1). In some embodiments, the diagnostic result indicates whether a feature is normal for each layer in the semiconductor wafer. If the diagnostic result is normal, the next process/stage is performed for the semiconductor wafer. Conversely, if the diagnostic result is abnormal, the current process/stage is suspended for checking.

If a SEM supports a measurement function, the SEM is capable of directly measuring the dimensions of the features in the semiconductor wafer, such as a critical dimension (CD), the widths and lengths of the metals, polys, active areas (ODs) and vias in the semiconductor wafer. For example, the SEM can capture an image according to the reference image corresponding to the golden wafer. Next, the SEM can measure the dimensions of the features in the semiconductor wafer by assigning cursors in the captured image. For example, a measuring feature is searched based on the recognition of the reference image, and the box cursors are automatically and regularly positioned in a measurement box, so as to perform auto measurement. Furthermore, the positions of the box cursors are determined according to the captured image.

FIG. 3shows a schematic illustrating a measurement box300and a plurality of measurement cursors automatically and regularly positioned by a SEM that supports a measurement function. InFIG. 3, two layers are observed in the measurement box300, with a first layer310being disposed on a second layer320. The measurement cursors include a plurality of pairs of cursors, and each pair of cursors is formed by a left cursor330L and a right cursor330R. Due to interference induced by the contrast in the measurement box300, the measurement cursors330L and330R will be positioned inaccurately, e.g. the measurement cursors labeled as340.

FIG. 4shows a simplified flowchart of a method400for analyzing a raw image from a semiconductor wafer according to GDS information (e.g. S130ofFIG. 1), in accordance with some embodiments of the disclosure. It should be noted that additional processes may be provided before, during, and/or after the method400ofFIG. 4, and that some processes may only be briefly described herein. Furthermore, the method400ofFIG. 4can be performed in one or more process/stage for the semiconductor wafer.

As mentioned above, the raw image is captured when an image-based alignment is performed according to the GDS information of the semiconductor wafer. After obtaining the raw image, a measurement box is assigned in the raw image according to the GDS information (S410ofFIG. 4). In some embodiments, for the semiconductor wafer, there are various features to be verified in the pattern of layout, and the raw image can includes more than one feature. According to the predetermined coordinates of the features, the measurement box is assigned in the raw image, so as to measure the features. A portion of the second pattern of the raw image can be viewed via the measurement box. In some embodiments, the raw image is zoomed in to assign the measurement box.

When the measurement box is assigned, a plurality of indicators is arranged/positioned in the second pattern of the raw image within the measurement box according to the GDS information (S420ofFIG. 4). Specifically, the number of indicators and positions of the indicators are determined according to the GDS information. In some embodiments, the indicators are the box cursors. Furthermore, the number of box cursors is less than the number of box cursors automatically and regularly positioned by the SEM that supports the measurement function. Fewer indicators are positioned in the measurement box, thereby reducing the interference of the measurement. Specifically, no additional indicator is positioned in the measurement box.

In some embodiments, the indicators are divided into a plurality of indicator pairs, and each indicator pair is arranged to measure a feature in the measurement box. For example, the feature to be measured in the raw image is a critical dimension (CD) of the semiconductor wafer, a width or a length of a feature of the second pattern (e.g. the width/length of conductive line), or a distance between the two features of the second pattern (e.g. the space between two conductive lines, or active area).

When the indicators are arranged in the measurement box according to the GDS information, a distance between the two indicators is measured in the measurement box (S430ofFIG. 4), so as to obtain a dimension of a portion of the second pattern in the raw image. In some embodiments, the distance between the two indicators is the CD of the semiconductor wafer, a width or a length of a feature of the second pattern in the raw image, or a distance between the two features of the second pattern in the raw image. Due to the interference induced by the large number of indicators being decreased, the distance between the two indicators can be accurately measured. Thus, measurement error is decreased.

When the distances between the indicators in the measurement box are measured completely, a diagnostic result is provided according to the measured distances (S440ofFIG. 4). In some embodiments, the diagnostic result of the raw image indicates whether the measured values are normal in the measurement box. If the diagnostic result is normal, the features are normal in the current process/stage for the semiconductor wafer, and the next process/stage may be performed. Conversely, if the diagnostic result is abnormal, the current process/stage is suspended for checking the semiconductor wafer.

FIG. 5Ashows a schematic view of a measurement box500in one example. The measurement box500is obtained from a raw image captured from a semiconductor wafer.FIG. 5Bshows a schematic view of GDS information of the semiconductor wafer, and the GDS information is used to capture the raw image comprising the measurement box500ofFIG. 5Afrom the semiconductor wafer. In some embodiments, the raw image is captured by an image capturing mechanism (e.g. SEM) according to the GDS information of the semiconductor wafer.

A single-layer structure is shown in the measurement box500ofFIG. 5A. In some embodiments, the single-layer structure is a portion of the second pattern in the raw image. The single-layer structure includes a plurality of conductive lines510. The conductive lines510can be polysilicon lines or metal lines, for example.

The GDS information of the single-layer structure ofFIG. 5Ais shown inFIG. 5B. In some embodiments, the GDS information includes a plurality of conductive lines530and a plurality of cut lines540. For integrated circuit layouts, the conductive lines530are cut with a cut pattern formed by the cut lines540, such as a cut poly (CPO) pattern.

The conductive lines530in the GDS information represent electrically conductive lines to be formed in a physical integrated circuit over a substrate of the semiconductor wafer. The conductive lines530can include polysilicon or other electrically conductive material such as metal in a metal layer. The cut lines540represent cut sections or patterning area where the conductive lines530are removed for electrical connections/disconnections according to the integrated circuit design in the current stage.

InFIG. 5A, the conductive lines510are divided into two groups: short lines and long lines. The short lines are parallel to the long lines, and the long lines are parallel with each other. According to the GDS information ofFIG. 5B, the short lines510in the same horizontal line are formed by arranging the cut line540in the middle of the corresponding conductive line530. Furthermore, the long line510is formed by arranging two cut lines540on the both sides of the corresponding conductive line530, respectively.

If a dimension of the conductive line530cut in the middle by the cut line540is to be measured, a first sign (e.g.550L-1to550L-6) is assigned to a left side of the conductive line530, and a second sign (e.g.550R-1to550R-6) is assigned to a right side of the conductive line530. According to the first and second signs of the GDS information, the indicators can be accurately arranged in the measurement box, so as to obtain the actual dimension in the semiconductor wafer.

In the measurement box500ofFIG. 5A, a half of the short lines are located at the left side of the measurement box500, and a plurality of indicators520L_1to520L-6are arranged at the left side of the half of the short lines according to the first signs550L-1to550L-6ofFIG. 5B. Furthermore, the other half of the short lines are located at the right side of the measurement box500, and a plurality of indicators520R_1to520R-6are arranged at the right side of the half of the short lines according to the second signs550R-1to550R-6in the GDS information ofFIG. 5B.

For example, in the measurement box500ofFIG. 5A, the indicator520L_1is arranged according to the first sign550L_1ofFIG. 5B, and the indicator520R_1is arranged according to the second sign550R_1ofFIG. 5B. The indicator520L_5is arranged according to the first sign550L_5ofFIG. 5B, and the indicator520R_5is arranged according to the second sign550R_5ofFIG. 5B.

In some embodiments, the indicators520L_1to520L-6and520R_1to520R-6are box cursors in the measurement box500ofFIG. 5A. After arranging the indicators520L_1to520L-6and the indicators520R_1to520R-6, the distances between the indicators520L_1to520L-6and the indicators520R_1to520R-6are measured.

By using the GDS information to assign the indicators in the measurement box, the number of indicators and positions of the indicators can be controlled in advance. Thus, the interference caused by the large number of indicators can be decreased. No additional indicator is positioned in the measurement box. Furthermore, by using the GDS information to distinguish the features, contours and patterns in the raw image, the interference induced by the contrast in the raw image also can be decreased.

FIG. 6Ashows a schematic view of a measurement box600in another example. The measurement box600is obtained from a raw image captured from a semiconductor wafer.FIG. 6Bshows a schematic view of GDS information of the semiconductor wafer, and the GDS information is used to captured the raw image comprising the measurement box600ofFIG. 6Afrom the semiconductor wafer. In some embodiments, the raw image is captured by an image capturing mechanism (e.g. SEM) according to the GDS information of the semiconductor wafer.

A multi-layer structure is shown in the measurement box600ofFIG. 6A. In some embodiments, the multi-layer structure is a portion of the second pattern in the raw image. The multi-layer structure includes a first layer having a plurality of conductive lines610, and a second layer having a plurality of conductive lines620. The first layer is disposed on the second layer, and a cross-layer structure is formed. The conductive lines610and620can be polysilicon lines and/or metal lines, for example.

The GDS information of the first layer ofFIG. 6Ais shown inFIG. 6B. In some embodiments, the GDS information includes a plurality of conductive lines650and a plurality of cut lines660. For integrated circuit layouts, the conductive lines650are cut with a cut pattern formed by the cut lines660.

The conductive lines650in the GDS information represent electrically conductive lines to be formed in a physical integrated circuit over a substrate of the semiconductor wafer. The conductive lines650can include polysilicon or other electrically conductive material such as metal in a metal layer. The cut lines660represent cut sections or patterning area where the conductive lines650are removed for electrical connections/disconnections according to the integrated circuit design in the current stage.

InFIG. 6A, the conductive lines610are divided into two groups: outer lines and inner lines. The inner lines are parallel to each other, and the inner lines are surrounded by the outer lines. According to the GDS information ofFIG. 6B, the outer lines are formed by arranging the cut line660in the middle of the corresponding conductive line650. Furthermore, the inner lines are formed by arranging two cut lines650on both sides of the corresponding conductive lines650, respectively.

According to the GDS information ofFIG. 6B, a first sign (e.g.670L-1to670L-7) is assigned at the left side of the conductive lines650, and a second sign (e.g.670R-1to670R-7) is assigned at the right side of the conductive lines650. According to the first and second signs of the GDS information, the indicators can be accurately arranged in the measurement box, so as to obtain the actual dimensions in the semiconductor wafer.

In the measurement box600ofFIG. 6A, a portion of conductive lines610form a first pattern (labeled as610A). The first pattern of conductive lines610is located at the left side of the measurement box600, and a plurality of indicators630L_1to630L-7are arranged at the edge of the first pattern according to the first signs670L_1to670L-7in the GDS information ofFIG. 6B.

In the measurement box600ofFIG. 6A, a portion of conductive lines610form a second pattern (labeled as610B), and the second pattern is opposite from the first pattern. The second pattern of conductive lines610is located at the right side of the measurement box600, and a plurality of indicators630R_1to630R-7are arranged at the edge of the second pattern according to the second signs670R_1to670R-7in the GDS information ofFIG. 6B.

For example, in the measurement box600ofFIG. 6A, the indicator630L_1is arranged according to the first sign670L_1ofFIG. 6B, and the indicator630R_1is arranged according to the second sign670R_1ofFIG. 6B. The indicator630L_4is arranged according to the first sign670L_4ofFIG. 6B, and the indicator630R_4is arranged according to the second sign670R_4ofFIG. 6B.

In some embodiments, the indicators630L_1to630L-7and the indicators630R_1to630R-7are box cursors in the measurement box600ofFIG. 6A. After arranging the indicators630L_1to630L-7and the indicators630R_1to630R-7, the distances between the indicators630L_1to630L-7and the indicators630R_1to630R-7are measured.

FIG. 7shows a simplified diagram of a system700for diagnosing a semiconductor wafer, in accordance with some embodiments of the disclosure. The system700includes a processing device (e.g., circuitry)710, a determining device (e.g., circuitry)720, and an electron microscope730.

A plurality of IC will be implemented in the semiconductor wafer740via various processes/stages at a wafer fabrication facility. When each process/stage is performed, the semiconductor wafer740will be verified and diagnosed via the system700.

The semiconductor wafer740to be diagnosed is loaded in the electron microscope730. In some embodiments, the electron microscope730can be an image capturing mechanism, and the image capturing mechanism is capable of capturing a raw image from the semiconductor wafer740.

In some embodiments, the system700further includes an interface device750, and a database760.

The processing device710can obtain a graphic database system file GDS of the IC to be implemented in the semiconductor wafer740. In some embodiments, the file GDS is obtained from the database760. In some embodiments, the file GDS is obtained from a remote server.

Furthermore, the processing device710can further obtain a user input Din from the interface device750. In some embodiments, the user input Din includes information regarding coordinates and patterns in the layout of the IC.

In the system700, the processing device710can obtain GDS information in the file GDS. In response to the information of the user input Din, the processing device710can clip the GDS information to provide a target image IMGt, thereby providing increased flexibility based on improvement in handling customized requirements. In some embodiments, the target image IMGt includes a first contour having a first pattern corresponding to a specific layout of the IC, and the specific layout includes a multi-layer structure. In some embodiments, the processing device710can provide the clipped GDS information GDSc corresponding to the target image IMGt. In some embodiments, the clipped GDS information GDSc includes the information (e.g. the first and second signs) regarding the indicators to be assigned in a measurement box.

In some embodiments, the file GDS includes layout information about each layer of the IC of the semiconductor wafer740. The processing device710can provide the target images IMGt for the corresponding layer of the semiconductor wafer740.

The target images IMGt include little layout information, thus it is difficult to effectively and sufficiently gather information from the target images IMGt. Therefore, information regarding circuit design and circuit layout of the IC can be kept secret.

In some embodiments, the processing device710can provide the target images IMGt to the electron microscope730via the determining device720. In some embodiments, the processing device710can directly provide the target images IMGt to electron microscope730without passing through the determining device720.

According to the first contour of the target images IMGt, the electron microscope730can perform image-based alignment to capture a raw image IMGr from the loaded semiconductor wafer740. As mentioned above, the raw image IMGr includes a second contour in the semiconductor wafer740, and the second contour matches the first contour of the target images IMGt.

In some embodiments, the contours of the semiconductor wafer are compared with the first contour of the target images IMGt. If a second pattern of the second contour is identical to the first pattern of the first contour, the raw image IMGr having the second contour is captured from the semiconductor wafer740.

After capturing the raw image IMGr, the electron microscope730outputs the raw image IMGr to the determining device720. Compared with a SEM supporting measurement function in an on-line manner, the determining device720is capable of provide an off-line measurement for the semiconductor wafer740.

After obtaining the raw image IMGr, the determining device720can assign a measurement box in the raw image IMGr. The determining device720can arrange the indicators in the measurement box according to the clipped GDS information GDSc, as mentioned above.

After the indicators are positioned, the determining device720can measure the distances between the indicators, and the dimensions of a portion of the second pattern are obtained. In some embodiments, the dimension of the portion of the second pattern is a critical dimension of the semiconductor wafer, a width or a length of a first feature of the second pattern (e.g. the width/length of conductive line), or a distance between the first feature and a second feature of the second pattern (e.g. the space between two conductive lines, or active area).

According to the measured dimensions, the determining device720can provide a diagnostic result Result_Out. In some embodiments, the diagnostic result Result_Out indicates whether the dimension of the portion of the second pattern is normal.

If the diagnostic result Result_Out is normal, the features of the semiconductor wafer740are normal in the current process/stage for the semiconductor wafer. In response to the diagnostic result Result_Out, the electron microscope730may unload the semiconductor wafer740to perform subsequent processes/stages. Conversely, if the diagnostic result Result_Out is abnormal, i.e. measure failure, the current process/stage is suspended for checking the semiconductor wafer740.

Embodiments for diagnosing a semiconductor wafer are provided. A target image is obtained according to GDS information of the semiconductor wafer. An image-based alignment is performed according to the target image, and a raw image is captured. The raw image includes a second contour corresponding to a first contour of the target image. The raw image is measured in an off-line manner. A measurement box is assigned in the raw image according to the GDS information. A plurality of indicators is arranged in the features within the measurement box. A diagnostic result is provided according to the dimensions of the features for the semiconductor wafer. The dimension of the feature can be a critical dimension of the semiconductor wafer, a width or a length of the feature (e.g. the width/length of conductive line), or a distance from the feature to the other feature (e.g. the space between two conductive lines, or active area).

By using the GDS information to perform alignment and measurement for the semiconductor chip, a high quality image with good contrast is used as a reference image to capture the raw image from the semiconductor chip. Thus, failure rate is decreased for alignment, and tooling time of the image capturing mechanism can be decreased. Furthermore, measurement is accurate by assigning the indicators in the measurement box according to the GDS information. Thus, process capability index (CPK) is stable, and manufacturing cost (e.g. manpower and tooling time) is decreased.

In some embodiments, a method for diagnosing a semiconductor wafer is provided. A target image is obtained according to graphic data system (GDS) information of a specific layout in the semiconductor wafer, wherein the target image comprises a first contour having a first pattern corresponding to the specific layout. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to the first contour. The semiconductor wafer is analyzed by measuring the raw image, so as to provide a diagnostic result.

In some embodiments, a method for diagnosing a semiconductor wafer is provided. Image-based alignment is performed to capture a raw image from the semiconductor wafer according to graphic data system (GDS) information of a specific layout in the semiconductor wafer. A measurement box is assigned in the raw image. At least one pair of indicators is arranged in the measurement box of the raw image. A distance between the indicators is measured. The semiconductor wafer is analyzed according to the measured distance, so as to provide a diagnostic result.

In some embodiments, a system for diagnosing a semiconductor wafer is provided. The system includes a processing device, an electron microscope, and a determining device. The processing device provides a target image according to graphic data system (GDS) information of a specific layout in the semiconductor wafer. The electron microscope receives the target image, and performs image-based alignment to provide a raw image. The raw image is captured from the semiconductor wafer according to the target image. The determining device receives the raw image from the electron microscope. The determining device assigns a measurement box in the raw image according to the input information. The determining device provides a diagnostic result according to the measurement box.

Various functional components or blocks have been described herein. As will be appreciated by persons skilled in the art, the functional blocks will preferably be implemented through circuits (either dedicated circuits, or general purpose circuits, which operate under the control of one or more processors and coded instructions), which will typically comprise transistors that are configured in such a way as to control the operation of the circuitry in accordance with the functions and operations described herein. As will be further appreciated, the specific structure or interconnections of the transistors will typically be determined by a compiler, such as a register transfer language (RTL) compiler. RTL compilers operate upon scripts that closely resemble assembly language code, to compile the script into a form that is used for the layout or fabrication of the ultimate circuitry. Indeed, RTL is well known for it role and use in the facilitation of the design process of electronic and digital systems.