Power efficient amplifier

In one embodiment, an amplifier to drive a load in response to an input voltage signal, the amplifier including a first amplifier to drive the load, a second amplifier, and a control sub-circuit to put the second amplifier into an active mode to drive the load when the output voltage of the first amplifier falls outside a voltage window, and to put the second amplifier into an inactive mode when the output voltage of the first amplifier falls within the voltage window. An embodiment also includes a switch to de-couple a capacitive impedance from the load after the second amplifier is put into its active mode, and to couple the capacitive impedance to the load when the output voltage of the first amplifier falls within the voltage window. Other embodiments are described and claimed.

FIELD

The present invention relates to electronic amplifiers, and more particularly, to efficient electronic power amplifiers with applications to, but not limited to, audio amplification.

BACKGROUND

Linear amplifiers have been used for many years in amplification systems. They have numerous advantages over switch mode amplifiers, such as lower noise, lower distortion, lower EMI (Electro-Magnetic Interference), lower component count, and lower cost. However, linear amplifiers in general have lower power efficiency than switch mode amplifiers. The relatively low power efficiency of linear amplifiers may shorten battery run-times of battery-powered consumer electronic devices. In spite of the lower efficiency, currently linear amplifiers are more widely used in portable electronic devices than switch mode amplifiers because of the above-mentioned advantages.

A typical application of a linear amplifier is an audio amplifier for a consumer electronic device. In such applications, the audio amplifier amplifies a baseband signal, representing audio content, in order to drive a transducer, such as a speaker or headphone, to generate an acoustic signal. Various amplifier circuits have been used. FIG.1illustrates an audio amplifier employing two linear amplifiers to drive load102in response to input signal Vin(t). In this example, input signal Vin(t) is a baseband signal audio with a zero time-average. That is, its DC (Direct Current) component is zero, so that the time average of Vin(t) over long time periods is essentially zero. (The audio information is represented by the variations of Vin(t) about zero, or ground.) Load102may be, for example, a speaker or headphone. The circuit ofFIG. 1is sometimes referred to as an H-bridge amplifier due to its resemblance of the letter “H”.

InFIG. 1, input signal Vin(t) is provided to the inverting input port (or terminal) of amplifier110, also called the negative input port (or terminal). (In other embodiments, Vin(t) may be provided to the non-inverting input port.) Amplifier110may be, for example, an OPAMP (Operational Amplifier). The combination of amplifier110and resistors R1and R2comprises linear amplifier112, where resistors R1and R2set the gain of linear amplifier112. Denoting the output voltage of linear amplifier112as Vo1(t), the gain of linear amplifier112is defined as δVo1(t)/δVin(t), the partial derivative of the voltage Vo1(t) with respect to the voltage Vin(t). This gain is often referred to as the AC (Alternating Current) gain. The gain of linear amplifier112is well known and is given as −R1/R2, where now R1and R2in this expression represent the resistances of resistors R1and R2, respectively. (For ease of notation, in these letters patent a symbol used to denote a resistor in a drawing also represents its resistance value when used in an expression. That is, if a resistor is designated in a drawing by the symbol R, then its resistance value will also be indicated by the same symbol R.)

InFIG. 1, the combination of amplifier120and resistors R3and R4comprise linear amplifier114. Resistors R3and R4are usually chosen to be equal in value. With this choice, the output voltage Vo2(t) of linear amplifier114is the negative of Vo1(t), i.e., Vo2(t)=−Vo1(t). Because of this, it is often said that the H-bridge amplifier has a differential output, and is driving its load in a differential mode. The load voltage is the voltage difference (Vo1(t)−Vo2(t)) applied to load102, and the overall gain, Gn, for the H-bridge amplifier ofFIG. 1is Gn=δ(Vo1(t)−Vo2(t))/δVin(t)=2*δVo1(t)/δVin(t)=−2*R2/R1. Note that inFIG. 1, Vps is the positive power supply voltage and −Vps is the negative power supply voltage.

FIG. 2ais another example of an audio amplifier, but employing only one linear amplifier204, comprising amplifier202and resistors R1and R2. (For simplicity, we will re-use symbols for resistors in various drawings. This is not meant to imply that resistors in different drawings labeled with the same symbol necessarily have the same resistance. It will be clear from context with drawing is being referred to, and therefore there should be no cause for confusion.) The gain of linear amplifier204is given by −R2/R1, and because only one linear amplifier is employed, this gain is also the overall gain for the circuit.

Yet another amplifier circuit is shown inFIG. 2b, again employing only one linear amplifier210, comprising amplifier212and resistors R1and R2. However, unlike the circuits ofFIGS. 1 and 2a, only one power supply voltage, denoted as Vps, is needed. Accordingly, the input signal Vin(t) inFIG. 2bshould have its time-average equal to Vps/2, and a bias voltage Vps/2 is applied to the non-inverting input port of amplifier212. (Although the input signal voltage inFIG. 2bhas a different time-average than that shown inFIGS. 1 and 2a, for notational convenience the same symbol, Vin(t), is used. This should be no cause for confusion.) To prevent wasted static power due to this Vps/2 average value, capacitor215is employed in series with load214. Capacitor215is often referred to as a coupling capacitor.

The output voltage, Vo(t), of amplifier210is given by Vo(t)=G[Vin(t)−Vps/2]+Vps/2, where the gain G is G=−R2/R1. Capacitor215will have a time-average voltage difference of Vps/2, so that the load voltage applied to load214is Vload(t)=Vo(t)−Vps/2=G[Vin(t)−Vps/2]. (Under ideal conditions, if capacitor215had unlimited capacitance, the voltage drop across it would be constant, equal to Vps/2. The larger the capacitance, the less its voltage drop varies with time.)

In comparingFIGS. 2aand2b, we see that the circuit ofFIG. 2bhas the advantage of requiring only one power supply voltage, but at the expense of requiring a capacitor. Capacitor215in series with load214is essentially a simple high-pass filter, and will filter out the low frequency components of the output voltage. Accordingly, in audio applications, capacitor215may limit audio fidelity in the bass region of the output audio signal unless it is large enough to pass the low frequencies of interest. But too large of a capacitor may not be suitable for a small, portable electronic device.

The circuits ofFIGS. 2aand2bhave the same power efficiency, assuming that capacitor215is large enough to pass most of the desired audio signal. Note that to have the same peak output power as that of the circuit inFIG. 2a, the value for the power supply voltage Vps inFIG. 2bshould be two times the value of the power supply voltage used inFIG. 2a. For the remaining discussion in this Background, we assume this relationship for the values of power supply voltage Vps used in the circuits ofFIGS. 2aand2b.

In general, a linear amplifier is linear over some range of its input voltage. As the output voltage of a linear amplifier approaches a supply rail (e.g., one of the power supply rails Vps or -Vps for the circuit ofFIG. 1orFIG. 2a, or the power supply rail Vps or ground for the circuit ofFIG. 2b), the linear amplifier may saturate. For example, a simplified model for a linear amplifier requiring the two power supply voltages Vps and −Vps, such as that used in the H-bridge amplifier ofFIG. 1or used in the amplifier ofFIG. 2a, is illustrated inFIG. 17a, where Vout(t) is the output voltage, Vin(t) is the input voltage, Vsat is a saturation voltage in the range 0<Vsat<Vps, and where we assume that the gain is negative. The functional relation, generalized to either a negative or positive gain G, may be written as: Vout(t)=GVin(t) for |Vin(t)|≦Vsat/|G|; Vout(t)=G*Vsat/|G| for Vin(t)>Vsat/|G|; and Vout(t)=−G*Vsat/|G| for Vin(t)≦−Vsat/|G|.

As another example of saturation, a simplified model for a linear amplifier requiring only one power supply voltage Vps, such as that used in the circuit ofFIG. 2b, is illustrated inFIG. 17b, where the saturation voltage is in the range 0<Vsat<Vps/2, and where again we assume that G is negative. The functional relation, generalized to either a negative or positive gain G, is: Vout(t)=G[Vin(t)−Vps/2]+Vps/2 for |Vin(t)−Vps/2|≦Vsat/|G|; Vout(t)=G*Vsat/|G|+Vps/2 for Vin(t)−Vps/2>Vsat/|G|; and Vout(t)=−G*Vsat/|G| for Vin(t)−Vps (Vsat depends upon the power supply voltage, so that if the power supply voltage for the circuit ofFIG. 2bis twice that ofFIG. 2ain order for the two circuits to provide the same peak output power, then ideally the saturation voltage for each circuit will have the same value.)

With the above simple model in mind, for a single-amplifier circuit, such as the circuit ofFIG. 2aorFIG. 2b, the magnitude of the voltage drop across the load, the load voltage, does not exceed Vsat. (Remember, we are assuming that the value of the supply voltage used forFIG. 2bis twice that used inFIG. 2a, so that the numerical values for their saturation voltages are the same, which we denote simply as Vsat.) However, for the H-bridge amplifier ofFIG. 1, the magnitude of the load voltage can go up 2Vsat. As a result, the H-bridge amplifier is capable of delivering a peak power to its load four times that of the single-amplifier circuit ofFIG. 2aorFIG. 2b. However, two amplifiers need to be powered in the H-bridge amplifier, resulting in twice the power dissipation as for a single-amplifier circuit. (Here, “power dissipation” is the power consumed by an amplifier; it is not the power delivered to the load.)

It would be advantageous for a linear power amplifier to drive a load at a higher peak power than that of a linear single-amplifier power amplifier, and yet have the power efficiency of a linear single-amplifier power amplifier.

DESCRIPTION OF EMBODIMENTS

FIG. 3ais a high level abstraction of some embodiments of the present invention. Amplifiers302aand304aare linear amplifiers. Switch306ahas two states. When in a first state, load308ais connected to capacitor310abut not to amplifier304a; and when in a second state, load308ais connected to amplifier304abut not to capacitor310a. Controller314asets the state of switch306a, and is connected to output port316aof amplifier302a. Network (or sub-circuit)318acouples input port320aof amplifier302a, output port316aof amplifier302a, and the capacitor310ato input port322aof amplifier304a. In practice, network318amay be realized as a resistor network.

Two power rails,326aand328a, are at power supply voltages Vps and !Vps, respectively. These voltages are with respect to ground potential, provided by ground rail330a, which may be taken as zero volts. Power supply voltages Vps and !Vps are provided to linear amplifiers302aand304a. Also, ground potential is provided as well to these amplifiers, and is shown as being applied to one of their input ports. (All voltages are with respect to ground voltage, which is taken as zero.) Input voltage Vin(t) is provided at input port320a. We do not indicate whether it is applied to an inverting input port or a non-inverting input port, because in some embodiments, Vin(t) may be applied to the inverting input port, and for others, Vin(t) may be applied to the non-inverting input port. The output voltage of linear amplifier302aor amplifier304ais assumed, for simplicity of discussion, to be zero if the voltage difference between their input ports Vin(t) is zero, but this is not a requirement. Vin(t) is assumed to have a zero time-average, so that its DC component is zero. The time-average voltage drop across capacitor310ais zero. Accordingly, capacitor310amay not be needed, so that for some embodiments, node324ais grounded.

FIG. 3bis another high level abstraction of some embodiments of the present invention. As inFIG. 3a, amplifiers302band304bare linear amplifiers. Switch306bhas two states. When in a first state, load308bis connected to capacitor310bbut not to amplifier304b; and when in a second state, load308bis connected to amplifier304bbut not to capacitor310b. Controller314bsets the state of switch306b, and is connected to output port316bof amplifier302b. Network (or sub-circuit)318bcouples input port320bof amplifier302b, output port316bof amplifier302b, and the capacitor310bto input port322bof amplifier304b. In practice, network318bmay be realized as a resistor network.

Note that forFIG. 3b, supply voltage Vps is provided by power rail326aand ground potential is provided by ground rail330a, which again may be taken as zero volts, but supply voltage !Vps is not provided for the embodiments represented byFIG. 3. Accordingly, input voltage Vin(t) has a time-average equal to Vps/2. For simplicity of discussion, it is also assumed that the amplifiers inFIG. 3have an output voltage Vps/2 in response to a zero differential input voltage, but this is not a requirement.

As discussed with respect to the prior art amplifiers, capacitor310bhas a time-average voltage drop of Vps/2. If node324bwere to be grounded, the time-average of the voltage drop across load308bwould ideally be Vps/2, which would cause wasted static power dissipation in load308b. By employing capacitor310b, the time-average voltage drop across load308bis ideally zero.

Circuits employing the embodiments represented byFIGS. 3aand3bmay comprise discrete components, or one or more integrated circuits. Furthermore, not all embodiments need comprise all of the elements or functional blocks indicated inFIGS. 3aand3b. For example, inFIG. 3a, elements332aand334aindicate output ports (e.g., connectors, terminals, solder pads, etc.) to which load308amay be connected. Load308amay be a transducer for generating acoustic energy in response to an electrical input signal, such as a speaker or a headphone. Load308amay be the input port of another amplifier system. Similar statements regarding elements332b,334b, and308binFIG. 3balso apply.

As an example, a circuit may be built and sold without a load, where the intended load is a headphone that is to be connected to a headphone jack, or perhaps a speaker that is to be connected to some type of connector or where its terminals are to be soldered to pads. Other embodiments may not have discrete connectors to which a load is connected, but may include an integrated load.

In the claims, we will refer to ports, connectors, pads, etc., for coupling a load, e.g., elements332a,334a,332b, and334b, as load ports. In describing the embodiments in more detail below, these load ports are not explicitly drawn in the accompanying drawings, but they may be included in these embodiments as described with respect toFIGS. 3aand3b. It should also be appreciated that reference to a “port”, whether a load port, input port, or output port, may physically comprise an interconnect, or a portion thereof, and may be used interchangeable with the term “node” or “terminal”.

Before describing in more detail various embodiments of the present invention, it is useful to consider the high level abstractions represented byFIGS. 3aand3b, and to describe in an approximate way their operation. First, considerFIG. 3a. When amplifier302ais operating linearly, its output voltage Vo1(t) is Vo1(t)=G*Vin(t), where G is its gain. During linear operation, switch306ais set to its first state so that load308ais connected to capacitor310abut not to amplifier304a. If capacitor310awere ideal, its voltage drop would be zero so that node324ais held at ground. (For those embodiments without a coupling capacitor, node324ais grounded.) Consequently, during linear operation, the load voltage, Vload, provided to load308ais Vload=G*Vin(t). Network318ais such that during linear operation, the output voltage Vo2(t) of amplifier304ais zero, the same as node324a.

When amplifier302agoes into saturation, its output voltage is either Vsat or −Vsat, where 0<ξVsatξ<ξVpsξ. Assume for this discussion that it is at Vsat. (For saturation at −Vsat, discussion of the circuit operation is the same as that for the Vsat case, and need not be repeated.) During saturation, controller314asets switch306ato its second state so as to connect load308ato the output of amplifier304a. Network318ais such that during saturation, the output voltage Vo2(t) of amplifier304ais −G*Vin(t)+Vsat. Consequently, the load voltage Vload provided to load308a, the difference in output voltages between amplifiers302aand304a, is Vload=Vsat+G*Vin(t)−Vsat=G*Vin(t), which is the desired result. That is, amplifiers302aand amplifier304atogether provide an undistorted amplified version of Vin(t) even if amplifier302ais saturating.

When amplifier302ais operating linearly, only amplifier302ais working to drive load308a, but when amplifier302ais saturating, amplifier304ais switched in to drive load308a. Consequently, it is expected that embodiments represented byFIG. 3aare more power efficient than two-amplifier systems such as that ofFIG. 1, and yet achieve a higher fidelity than single-amplifier systems such as that ofFIG. 2aor2b.

Consider nowFIG. 3b. When amplifier302bis operating linearly, its output voltage Vo1(t) is Vo1(t)=G*(Vin(t)−Vps/2)+Vps/2, where G is its gain. During linear operation, switch306bis set to its first state so that load308bis connected to capacitor310bbut not to amplifier304b. If capacitor310bwere ideal, its voltage drop would be Vps/2, so that node324bis at Vps/2. Consequently, during linear operation, the load voltage Vload provided to load308bis Vload=G*(Vin(t)−Vps/2). Network318bis such that during linear operation, the output voltage Vo2(t) of amplifier304bis Vps/2, the same as node324b.

When amplifier302bgoes into saturation, its output voltage is either Vsat+Vps/2 or −Vsat+Vps/2, where −Vps/2<Vsat<Vps/2. Assume that saturation is at Vsat+Vps/2. (Discussion for the other saturation case is the same and need not be repeated.) During saturation, controller314bsets switch306bto its second state so as to connect load308bto the output of amplifier304b. Network318bis such that during saturation, the output voltage Vo2(t) of amplifier304bis Vo2(t)=−G*(Vin(t)−Vps/2)+Vsat+Vps/2. Consequently, the load voltage Vload provided to load308b, the difference in output voltages between amplifiers302band304b, is Vload=Vsat+Vps/2+G*(Vin(t)−Vps/2)−Vsat−Vps/2), which is the desired result. That is, amplifiers302band amplifier304btogether provide an undistorted amplified version of Vin(t) even if amplifier302bis saturating.

When amplifier302bis operating linearly, only amplifier302bis working to drive load308b, but when amplifier302bis saturating, amplifier304bis switched in to drive load308b. Consequently, just as forFIG. 3a, it is expected that embodiments represented byFIG. 3bare more power efficient than two-amplifier systems such as that ofFIG. 1, and yet achieve a higher fidelity than single-amplifier systems such as that ofFIG. 2aor2b.

It should be noted that the above description for the operation of circuits represented byFIG. 3aandFIG. 3bis only approximate, and is not meant to precisely describe the operation of actual embodiments of the invention. This is because for a linear amplifier, the demarcation between linear and non-linear (saturating) operation may not be precisely defined or precisely known.

For example, as discussed in the Background section, a simplified functional relationship between output voltage and input voltage for a linear amplifier may be illustrated as shown inFIGS. 17aand17b. ForFIG. 17a, linear operation may be specified as those input voltages Vin(t) within the interval [−Vsat/G, Vsat/G], or equivalently, as those output voltages Vout(t) within the interval [−Vsat, Vsat]. ForFIG. 17b, linear operation may be specified as those input voltages Vin(t) within the interval [−Vsat/G+Vps/2, Vsat/G+Vps/2], or equivalently, as those output voltages Vout(t) within the interval [−Vsat+Vps/2, Vsat+Vps/2].

In more realistic models, however, there will be a range of input and output voltages for which there is a substantially linear relationship between output voltage and input voltage, a range of input and output voltages for which there is a non-zero AC gain but for where the relationship between the output voltage and the input voltage is not substantially linear, and a range of input voltage for which the output voltage saturates so that the AC gain is substantially zero. For ease of description, an amplifier may be referred to as being in pre-saturation when its range of input and output voltage is such that there is a non-zero AC gain but for where the relationship between the output voltage and the input voltage is not substantially linear.

In practice, for embodiments represented byFIG. 3a, controller314amay be coupled to amplifier302asuch that amplifier304ais switched in to drive load308awhile amplifier302ais still operating linearly, but before it enters pre-saturation. A similar statement may apply to the respective components inFIG. 3b.

Furthermore, amplifier304a(or304b) does not precisely replicate the negative of that portion of the output voltage signal that amplifier302a(or304b) would have provided if amplifier302a(or302b) wasn't saturating. It should be understood that the above approximate description for the operation of circuits represented byFIG. 3aandFIG. 3bwas given merely to motivate and to provide an intuitive understanding regarding the embodiments. With this in mind, we now describe in more detail the embodiments.

Referring now toFIG. 4, supply voltages Vps and −Vps are provided, and input voltage Vin(t) has a time-average equal to ground, taken as 0 volts. Output voltage Vo1(t) of linear amplifier410is provided to comparators450and460. Comparators450and460are powered by a power supply voltage Vcps, which may or may not be equal to Vps, the positive power supply for linear amplifiers410and420. Threshold voltages Vth1and Vth2at nodes403and405, respectively, are set by resistors R8, R9, and R10such that Vth1is almost equal to Vps and Vth2is almost equal to −Vps. For example, we may set Vth1=0.95*Vps and Vth2=−0.95*Vps. For some embodiments, the condition Vth2<Vo1(t)<Vth1is indicative of the condition that amplifier410is operating linearly. That is, these threshold voltages may be set so that Vth2<Vo1(t)<Vth1is indicative of amplifier410operating linearly but not yet in pre-saturation.

Referring now to electronic switch406, pin1is the common terminal, and pin2is the digital control input terminal. When digital control input pin2is at logic LOW, pin3is connected to the common terminal, pin1, via switch406. When digital control input pin2is at logic HIGH, pin4is connected to the common terminal, pin1, via switch406. Logic OR gate470outputs to pin2a logic HIGH signal upon detecting any of its input voltages, Vcm1(t) or Vcm2(t), at logic HIGH; and outputs to pin2a logic LOW signal otherwise. In practice, logic OR gate470is powered at an appropriate power supply voltage, such as Vcps, Vps, or at another voltage.

Resistors R1and R2set the voltage gain for amplifier410, denoted by G1, as:

G⁢⁢1=∂Vo⁢⁢1⁢(t)∂Vin⁢⁢(t)=-R⁢⁢2R⁢⁢1.(1)
The gain G1has a negative value because the input signal Vin(t) is fed to the inverting input port of amplifier410. Note that for amplifier410operating rail-to-rail, not only are the differential voltages related by Vo1(t)=G1*Vo1(t), but also we have Vo1(t)=G1*Vin(t).

Resistors R3and R4set the voltage gain for the amplifier420, denoted by G2, as:

G⁢⁢2=∂Vo⁢⁢2⁢(t)∂Vinp⁢⁢2⁢(t)=1+R⁢⁢4R⁢⁢3.(2)
Again, we also have Vo2(t)=G1*Vin(t).

We now define several more gains. These definitions will be useful when considering conditions, to be discussed later, under which amplifier420provides the appropriate voltage signal to “restore” the clipped output voltage of amplifier410when saturating. To this end, define the gains

G⁢⁢3=∂Vinp⁢⁢2⁢(t)∂Vin⁢⁢(t),(3)G⁢⁢4=∂Vinp⁢⁢2⁢(t)∂Vo⁢⁢1⁢(t),⁢and(4)G⁢⁢5=∂Vinp⁢⁢2⁢(t)∂Vcp⁢⁢1⁢(t).(5)
These gains are given by:

Resistors R1, R2, R3, R4, R5, R6, and R7may be chosen to satisfy the following three conditions:

Condition (1): When amplifier410is operating linearly, the variation in the voltage Vinp2(t) (the input voltage to amplifier420) due to a variation in Vin(t) cancels the variation in the voltage Vinp2(t) due to a variation in Vo1(t). By variation, we mean a small variation or differential, and will use the symbolδ6. That is, for some arbitrary variable V, δV denotes a small variation or differential in the variable V. Note that when amplifier410is operating linearly, we have δVo1(t)=[G1]δVin(t). With this notation, condition (1) may be restated as: δVinp2(t)=[δVinp2(t)/δVin(t)]δVin(t)+[δVinp2(t)/δVo1(t)]δVo1(t)=0, where because amplifier410is assumed to be operating linearly, the differentials in Vin(t) and Vo1(t) are related by δVo1(t)=[G1]δVin(t).

Condition (2): The voltage gain, G6, defined as G6=δVo2(t)/δVcp1(t), is set to 1. That is,

Condition (3): The voltage gain G7defined as

G⁢⁢7=∂Vo⁢⁢2⁢(t)∂Vin⁢⁢(t),(11)
is set equal to −G1. That is,
G7=−G1.  (12)
Writing

G⁢⁢7=∂Vo⁢⁢2⁢(t)∂Vin⁢⁢(t)=∂Vo⁢⁢2⁢(t)∂Vinp⁢⁢2⁢(t)*∂Vinp⁢⁢2⁢(t)∂Vin⁢⁢(t)=G⁢⁢2*G⁢⁢3,(13)
one obtains the condition

To understand the significance of these conditions, for simplicity we assume for the moment that capacitor C1is ideal so that δVcp1(t)=0 and amplifier410is perfectly linear until some time instant T1, after which it saturates by outputting a constant voltage Vsat. Under these simplifying assumptions, condition1ensures that when amplifier410is operating linearly, the differential (or small variation) in the output voltage of amplifier420is zero. That is, amplifier410provides a constant output voltage independent of Vin(t). This constant is easily seen to be zero because at Vin(t)=0, the output voltage of amplifier410is Vo1(t)=0, so that Vo2(t)=0. Thus, when switch406connects the output port of amplifier420to load408at time instant T1, the output voltage provided to load408by amplifier420is initially zero.

After time T1with amplifier410now operating in saturation, we have Vo1(t)=Vsat. But condition 3 ensures that the differential in the output voltage provided by amplifier420to load408is −G1*δVin(t). Because condition 1 ensured that the output voltage of amplifier420was initially zero at time instant T1, conditions 1 and 3 together ensure that the output voltage of amplifier420after time instant T1is Vo2(t)=−G1*Vin(t)+Vsat. Consequently, the load voltage Vload(t), defined as the difference between the output voltages of amplifiers410and420, is given by Vload(t)=Vo1(t)−Vo2(t)=Vsat+G1*Vin(t)−Vsat=G1*Vin(t), which is the desired result. Loosely stated, during saturation, amplifier420restores that part of the load voltage that amplifier410would have provided if it wasn't saturating.

Furthermore, note that amplifier420is not saturating because it need only provide the output voltage −G1*Vin(t)+Vsat, i.e., the “clipped” portion, which in practice will not be close to Vps or −Vps.

Of course, the above simplifying assumptions regarding the ideal nature of amplifier420in which it goes abruptly into saturation at some time instant TI, and where it is perfectly linear before time T1and outputs a constant saturation voltage after T1, are only met approximately in practice. Hence, the description of the embodiments regarding how amplifier420restores the clipped portion of the output of amplifier410is meant to provide understanding of the embodiments, and is not meant to provide an exact description of embodiments or their operation.

Finally, the significance of condition 2 is that when amplifier410is not saturated, the output voltage Vo2(t) of amplifier420follows (approximately) the voltage on capacitor C1, and consequently, when switch406changes its state so that pin1connects to pin4instead of pin3, the voltage provided to load408does not abruptly change, so that there will not be a “glitch” generated by the switching action.

To satisfy the above three conditions, the following procedure may be followed. First, determine the gain for amplifier410according to the system needs so that R1and R2may be determined. It is important to notice that, in theory, these two resistors may have almost any value, as long as their ratio determines the desired gain. In practice, these resistor values may range from hundreds of Ohms to hundreds of Kilo Ohms, depending on the type of circuit used to realize the amplifier. One design rule to consider when choosing the resistance values is that, in general, the lower the resistance, the lower the noise, and the lower the error voltages caused by the input bias currents of the amplifier. However, the lower the resistance, the higher the power loss consumed by the resistors. Therefore, it is often found in practice that these resistor values are in the tens of kilo Ohms.

Secondly, to meet the requirement listed in Condition 1 above, note that the variation in the voltage Vinp2(t), δVinp2(t), due to a variation in the voltage Vin(t), δVin(t), is:

δ⁢⁢Vinp⁢⁢2⁢(t)=δ⁢⁢Vin⁢⁢(t)*G⁢⁢3=δ⁢⁢Vin⁢⁢(t)R⁢⁢5*(1R⁢⁢6+1R⁢⁢7)+1,(15)
and the variation in the voltage Vinp2(t), δVinp2(t), due to a variation in the voltage Vo1(t), δVo1(t), is:

δ⁢⁢Vinp⁢⁢2⁢(t)=δ⁢⁢Vo⁢⁢1⁢(t)*G⁢⁢4=δ⁢⁢Vo⁢⁢1⁢(t)R⁢⁢6*(1R⁢⁢5+1R⁢⁢7)+1.(16)
From eq. (1), when amplifier410is operating linearly, we have

δ⁢⁢Vo⁢⁢1⁢(t)=G⁢⁢1*δ⁢⁢Vin⁡(t)=-R⁢⁢2R⁢⁢1⁢δ⁢⁢Vin⁡(t),
and combining with eq. (16), one obtains

δ⁢⁢Vo⁢⁢1⁢(t)*G⁢⁢4=-R⁢⁢2R⁢⁢1⁢δ⁢⁢Vin⁡(t)R⁢⁢6*(1R⁢⁢5+1R⁢⁢7)+1.(17)
Making the absolute values of eq. (15) and eq. (17) the same, but having opposite polarity, one obtains

Thirdly, meet the requirement listed in Condition 2 above by using eq. (10):

Finally, derive an equation to meet the requirement listed in Condition 3 above. From eq. (13),

We summarize the above procedure for satisfying the above three conditions: Determine R1and R2by eq. (1) according to the system needs, where

R⁢⁢6R⁢⁢5=R⁢⁢2R⁢⁢1.
(Note that one of the two resistors, R5or R6, may be set, in theory, to any value, as long as the ratio determines the desired gain. In practice, the resistor values are often chosen to be in the range of hundreds of Ohms to hundreds of Kilo Ohms.) Determine R7by eq. (21):
R7=R6.
Determine the ratio of R4and R3by eq. (22):

We illustrate the above by a numerical example. Various waveforms will also be provided for this numerical example. (All resistances are in Ohms.) Set G1=−2 by setting

R⁢⁢2=20⁢K,⁢andR⁢⁢1=-R⁢⁢2G⁢⁢2=10⁢K.
Set R5=10K, so that

FIG. 5provides various simulated waveforms for the above resistor values. (The waveforms were generated based on the assumption that amplifiers410and420have rail-to-rail output capability. In practice, this capability is not necessary.) Resistors R8, R9, and R10were chosen so that Vth1=0.95*Vps and Vth2=−0.95*Vps. The horizontal axis for the plots is time, and the vertical axis for the plots is voltage. Various instances of time are labeled and will be referred when describing the waveforms.

The waveform for input voltage Vin(t) is as shown in plot501ofFIG. 5. Roughly speaking, it changes from a small triangle waveform to a medium triangle waveform, and then to a larger triangle waveform to illustrate the behavior of the amplifier at different input levels. Plot502shows the output signal waveform, Vo1(t), for amplifier410. It can be seen that during the time periods of0to t4, t5to t9, t10to t14, t17to t21, and t24to t26, amplifier410exhibits a gain of −2 without saturation. During the time periods of t3to t6and t13to t18, output voltage Vo1(t) exceeds the threshold voltage of comparator450, Vth1, so that comparator450provides a HIGH logic signal to OR gate470. Thus, the output voltage of logic gate470, Vcsw(t) (seeFIG. 4), comprises pulses as shown in plot503during time periods t3to t6and t13to t18. In similar fashion, during the time periods t8to t11and t20to t25, output voltage Vo1(t) goes below the threshold voltage of comparator460, Vth2, and comparator460provides a logic HIGH signal to OR gate470. Consequently, voltage signal Vcsw(t) comprises pulses as shown in plot503during in the time periods t8to t11and t20to t25.

Amplifier420output voltage, Vo2(t), is shown in plot504. It can be seen that during the time periods of t4to t5, t9to t10, t14to t17, and t21to t24, the waveform for Vo2(t) exhibits clipping because amplifier410is saturating. (During the time periods of0to t4, t5to t9, t10to t14, t17to t21, and t24to t26, amplifier420is not working because of condition 1 as described above is satisfied.) As output voltage Vcsw(t) of logic gate470goes HIGH, switch406is switched to connect the output port of amplifier420to load408. For simplicity of generating the waveforms, we assume switch406is ideal, so that there is no significant voltage drop between its input and output, that is, Vo3(t)=Vo2(t) (seeFIG. 4). The potential difference provided across load408, denoted as Vload(t) in plot505, is Vload(t)=Vo1(t)−Vo3(t)=Vo1(t)−Vo2(t), and is shown in plot505.

In this simulation, plot505shows that load408is driven by an undistorted load voltage Vload(t) waveforms during the time periods of0to t15, t16to t22, and t23to t26, which are amplified and inverted waveforms of input signal Vin(t), even though amplifier410is saturating during the time periods of t4to t5, t9to t10, t14to t17, and t21to t24. In a sense, the circuit ofFIG. 4amplifies its input signal in the same way as done by a conventional linear H bridge amplifier system as represented byFIG. 1. For comparison, simulated waveforms for a typical amplifier as represented byFIG. 1are shown inFIG. 6. InFIG. 6, plot601is input signal Vin(t), plot602is output signal Vo2(t) of the amplifier120, plot603is output signal Vo1(t) of amplifier110, and plot604is the load voltage, denoted as Vload(t), across load102, where Vload(t)=Vo1(t)−Vo2(t).

During the time periods of t15to t16and t22to t23, amplifier420is saturated due to its input signal voltage, Vinp2(t), having too large an amplitude. Note that during these same time periods, it is seen from the plots inFIG. 6that the load voltage applied to load102ofFIG. 1is also clipped. Consequently, for this simulation, the amplifier system ofFIG. 4generates the same output waveforms as those generated by the conventional system ofFIG. 1.

It is instructive to compare the power usage of the prior art amplifier ofFIG. 1to the amplifier ofFIG. 4, where the same input voltage signal is applied to both to generate the same output load voltage signal. In order for the two amplifiers to generate the same output load voltage signal from the same input voltage signal, the conventional linear H bridge amplifier ofFIG. 1has its resistor values (in Ohms) set as follows:
R1=10K, R2=10K, R3=10K, and R4=10K.

Various simulated waveforms for the H bridge amplifier ofFIG. 1are shown inFIG. 7. Plot701is the load voltage across load102. It is the same plot as604ofFIG. 6, and is reproduced inFIG. 7for convenience. Plot702shows the positive power supply current for amplifier110, denoted as Ip1(t), and also the negative power supply current for amplifier120, denoted as In2(t). Plot703shows the positive power supply current for amplifier120, denoted as Ip2(t), and also the negative power supply current for amplifier110, denoted as In1(t). Plot704shows the total power supply current provided to the amplifiers, denoted as Ic(t), where I(t)=Ip1(t)+In1(t)+Ip2(t)+In2(t), which is proportional to the total power consumption of the amplifier circuit. (The “c” in “Ic(t)” is chosen as a mnemonic to mean the “conventional” circuit ofFIG. 1.)

Various simulated waveforms for the embodiment ofFIG. 4are shown inFIG. 8, where the input voltage and the resistors have the same values as used for the simulated waveforms presented inFIG. 5. For convenience, plots502,503, and504inFIG. 5are shown again inFIG. 8as plots802,803, and804, respectively. For convenience, the same notation used for the supply currents indicated inFIG. 7are also used for the supply currents indicated inFIG. 8, where now inFIG. 8, Ip1(t) shown in plot805is the positive power supply current for amplifier410, In1(t) shown in plot806is the negative power supply current for amplifier410, Ip2(t) shown in plot807is the positive power supply current for amplifier420, and In2(t) shown in plot808is the negative power supply current for amplifier420. There should be no cause for confusion because it will be clear from context the set of supply currents being referred to.

InFIG. 8, during the time periods 0to t3, t6to t8, t11to t13, t18to t20, and t25to t26, amplifier410draws supply current as shown in plot805for Ip1(t) and in plot806for In1(t), but amplifier420does not draw any supply current as shown in plot807for Ip2(t) and in plot808for In2(t). Define the total supply current of the embodiment ofFIG. 4as I(t)=Ip1(t)+In1(t)+Ip2(t)+In2(t), where now Ip1(t), In1(t), Ip2(t), and In2(t) refer to the respective currents inFIG. 8. This current is shown in plot809inFIG. 8. To compare the total current of the conventional circuit ofFIG. 1to the embodiment ofFIG. 4, we have also drawn in plot809, as a dotted line, the current Ic(t) from the circuit ofFIG. 1. From plot809, it can be seen that during the periods0to t3, t6to t8, t11to t13, t18to t20, and t25to t26, I(t)=0.5*Ic(t). That is, during these timer periods, the circuit for the embodiment ofFIG. 4consumes only half of the total supply current as the conventional circuit ofFIG. 2. During the time periods t3to t6, t8to t11, t13to t18, and t20to t25, I(t)=Ic(t), so that the embodiment ofFIG. 4consumes the same supply current as the circuit ofFIG. 1.

The plots inFIG. 8may be interpreted to mean that when amplifier410is not saturated (e.g., when the input signal's amplitude is not too large), the embodiment ofFIG. 4cuts the total power consumption by one-half when compared to the prior art circuit ofFIG. 1. In practice, many signals, especially audio signals, have low amplitudes most of the time. Consequently, it is believed that for the embodiment ofFIG. 4, when used to amplifier audio signals, there may be as much as an almost 50% savings in power consumed when compared to the prior art circuit ofFIG. 1. Some real measurements have shown that for amplifying audio signals, the embodiment ofFIG. 4achieves a 50% power saving when the speaker volume is set low, and a 30% to 40% power savings when the speaker volume is set high, when compared with the conventional circuit ofFIG. 1. For battery-powered systems, such as cell phones, MP3 players, portable DVD players, etc., this saving in power consumption may be significant.

Another embodiment is shown inFIG. 9. Note that the circuit ofFIG. 9may be obtained by modifying the embodiment ofFIG. 4in which capacitor C1and resistor R7ofFIG. 4are eliminated, and where pin3of switch406inFIG. 4is grounded. For the circuit ofFIG. 9, the input signal Vin(t) has a zero time-average. For some embodiments, the resistor values indicated inFIG. 9may be chosen to establish the following two conditions.

Condition (1): When the amplifier910is operating linearly, i.e., not saturated and not in pre-saturation, the variation in the voltage Vinp2(t) due to a variation in the voltage Vin(t) cancels the variation in the voltage Vinp2(t) due to a variation in the voltage Vo1(t). As for the embodiment inFIG. 4, this condition ensures that the output voltage of amplifier920is zero when amplifier910is operating linearly, i.e., when amplifier910is not saturated. Thus, load908receives the same signal when switch906is set in its “lower” position so that load908is connected to ground via pin1and pin3, as when it is first connected to amplifier920due to amplifier910entering saturation.

Condition (2): When amplifier910is saturated, voltage gain G7, defined as

G⁢⁢7=∂Vo⁢⁢2⁢(t)∂Vin⁡(t),(311)
is set equal in magnitude but opposite in polarity to gain G1, which was defined by eq. (1). That is,

⁢G⁢⁢7=-G⁢⁢1.⁢⁢⁢Writing⁢⁢G⁢⁢7⁢⁢has⁢⁢G⁢⁢7=∂Vo⁢⁢2⁢(t)∂Vin⁡(t)=∂Vo⁢⁢2⁢(t)∂Vinp⁢⁢2⁢(t)*∂Vinp⁢⁢2⁢(t)∂Vin⁡(t)=(1+R⁢⁢4R⁢⁢3)*1R⁢⁢5R⁢⁢6+1,(312)
one obtains from G7=−G1the relation

(1+R⁢⁢4R⁢⁢3)*1R⁢⁢5R⁢⁢6+1=R⁢⁢2R⁢⁢1.(313)
As discussed with respect to the embodiment ofFIG. 4, conditions1and2ensure (approximately) that when amplifier910is saturated and switch940is switched to its “upper” position (common terminal pin1is connected to pin4), load908will receive from amplifier920that signal which has been clipped away by amplifier910due to its saturation.

With the above conditions in mind, the following is a procedure for determining the values of the resistors indicated inFIG. 9.

First, determine the gain for amplifier910according to the system needs so that R1and R2may be determined, where

G⁢⁢1=∂Vo⁢⁢1⁢(t)∂Vin⁡(t)=-R⁢⁢2R⁢⁢1.(314)
Note that in theory these two resistors may have almost any values, as long as their ratio determines the desired gain. In practice, these resistor values range from the hundreds of Ohms to the hundreds of kilo Ohms, depending on the amplifier being used. A basic design rule to follow is that the lower the resistance, the lower the noise, and consequently the lower the error voltages caused by any bias currents. However, the lower the resistance, the higher the power consumed by the resistors. Accordingly, it is often found in practice that these resistor values are in the tens of kilo Ohms.

Second, derive an equation to meet the requirement listed in Condition 1 above as follows: The differential in the voltage Vinp2(t) due to a differential in the voltage Vin(t) is:

δ⁢⁢Vinp⁢⁢2⁢(t)=δ⁢⁢Vin⁡(t)R⁢⁢5R⁢⁢6+1.(315)
The differential in the voltage Vinp2(t) due to a differential in the voltage Vo1(t) is

δ⁢⁢Vinp⁢⁢2⁢(t)=δ⁢⁢Vo⁢⁢1⁢(t)R⁢6R⁢⁢5+1.(316)
From eq. (1), with amplifier910assumed to be operating linearly, we have

δ⁢⁢Vo⁢⁢1⁢(t)=G⁢⁢1*δ⁢⁢Vin⁡(t)=-R⁢⁢2R⁢⁢1⁢δ⁢⁢Vin⁡(t),
and combining this with eq. (316) gives

δ⁢⁢Vo⁢⁢1⁢(t)R⁢6R⁢⁢5+1=-R⁢⁢2R⁢⁢1⁢δ⁢⁢Vin⁡(t)R⁢6R⁢⁢5+1.(317)
Requiring the values of eqs. (315) and (317) to be the same in magnitude but opposite in polarity gives the following relationships

Finally, derive an equation to meet condition (2) above as follows. From eq. (313),

We may summarize the above description regarding the determination of a set of resistor values as follows. First, determine R1and R2by eq. (314) according to

The above procedure may be illustrated by the following numerical example, where all resistances are in Ohms. Set G1=−2 by choosing for R2and R1the values,

R⁢⁢2=20⁢⁢K,⁢andR⁢⁢1=-R⁢⁢2G⁢⁢2=10⁢⁢K.
Next, set R5=10K, so that R6is given by

We now consider illustrative waveforms to describe the operation of the circuit inFIG. 9using the above values for the resistances. (We assume that amplifiers910and920have rail-to-rail output capability for the illustrative waveforms. In practice, non-rail-to-rail output amplifiers may be employed.)

When the input signal, Vin(t), has its waveform as shown in plot501inFIG. 5, all the other waveforms for the circuit ofFIG. 9will be the same as those for the circuit ofFIG. 4. That is, waveforms in plots502to505and plots802to809also apply to the circuit ofFIG. 9. Consequently, the same discussion regarding the simulated waveforms for the circuit ofFIG. 4also applies to that ofFIG. 9. Consequently, the power savings for the circuit ofFIG. 9will be the same as for the circuit ofFIG. 4.

It is well know that a signal waveform having sharp “turning corners” in the time domain contains relatively very high frequency components. For example, the signal waveform in plot502for Vo1(t) at the time instances t4, t5, t9, t10, t14, t17, t21, and t24, and the signal wayeform in plot504for Vo2(t) at the time instances t15, t16, t22, and t23, exhibit such sharp turns in the time domain. In practice, these sharp turns are caused by saturation of the output stages of the amplifiers. When such waveforms travel through unshielded wires, EMI (Electro-Magnetic Interference) may be emitted.

In typical applications where the circuit inFIG. 4orFIG. 9is used to amplify audio signals, the two voltage signals Vo1(t) and Vo2(t) represent the amplifier output voltages applied to the speakers via unshielded speaker wires. As a result, EMI may result. To mitigate the EMI, the embodiment ofFIG. 10may be employed. The circuit ofFIG. 10is identical in structure to that ofFIG. 9, except for the four diodes D1, D2, D5, and D6, and the four Zener diodes D3, D4, D7, and D8.

Devices D1, D2, D3, and D4form a diode array connected across feedback resistor R2, and devices D5, D6, D7, and D8form another diode array connected across feedback resistor R4. The I-V (current-voltage) characteristic of a typical diode array is shown inFIG. 11a, where the definitions for the diode array current, Izd, and voltage, Vzd, are inferred from the diode array ofFIG. 11b. The same procedure for choosing resistance values for the circuit ofFIG. 9may also be applied to the circuit ofFIG. 10, and simulated waveforms may be illustrated as done for the circuit ofFIG. 9. Accordingly, because of the similarity in circuit topology betweenFIGS. 9 and 10, a detailed discussion for choosing the resistances need not be given. Simulated waveforms are shown inFIG. 12. Input voltage signal Vin(t) is shown in plot1201ofFIG. 12, which is the same as that used for the previously described input voltage signals. As described with respect to the previous embodiments, plot1202shows the voltage Vo1(t), plot1203shows the voltage Vcsw(t), plot1204shows the voltage Vo2(t), and plot1205shows the voltage Vload(t) applied to load1006. As seen fromFIG. 12, the previously sharp corners caused by the saturations of the amplifiers, in this case amplifier910and920, are smoothed out. As a result, it is expected that the EMI is reduced.

Because the diode arrays shunt feedback resistors R2and R4, there is a reduction in the amplifier gains when the amplifier outputs are approaching their saturation voltages. Therefore, the diode array threshold voltage, Vzdth, as shown inFIG. 11a, should be slightly higher than the threshold voltage, Vth1, for comparator1050. (We have assumed that the threshold voltages for comparators1050and1060satisfy |Vth1|=|Vth2|.)

There are numerous other methods to mitigate EMI, such reducing the gain of an amplifier when its output stage is approaching the power supply rails, resulting in a smoothing of the “saturation corners” of the waveforms. Using the diode arrays as shown inFIG. 10is merely one method.

The previous embodiments described so far make use of two power supply voltages, denoted as Vps and −Vps, and are such that the input voltage signal, denoted as Vin(t), has a zero time-average. That is, the time-average of Vin(t) is at ground. However, embodiments may be realized in which only one power supply voltage, simply denoted as Vps, is needed. For such embodiments, the input voltage signal, again denoted by Vin(t), has a time-average equal to Vps/2. Such embodiments should make use of a capacitor so as not to consume unwanted static power, where the capacitor couples the load to ground when only one amplifier is driving the load. For example, such an embodiment is shown inFIG. 13.

Comparing the circuit ofFIG. 13to that ofFIG. 9, it is seen that they have similar structures. However, amplifiers1310and1320require only one power supply to provide a voltage, Vps. Also, resistor R10is now grounded instead of being connected to a negative power supply voltage as inFIG. 9. The input voltage signal Vin(t) indicated inFIG. 13now has its time-average equal to Vps/2. Accordingly, the non-inverting port of amplifier1310and resistor R3are biased at Vps/2. Resistors R8, R9, and R10are chosen so that Vps>Vth1>Vth2>0. In practice, Vth1is close to Vps and Vth2is close to 0 (ground). For example, Vth1may be set to 0.9 Vps volts and Vth2may be set to 0.1 Vps volts.

The bias voltage Vps/2 may be generated in numerous ways. For example. For example,FIG. 14ashows a circuit using a resistor divider comprising resistors R11and R12, where the resistance values of R11and R12are chosen to be much smaller than that of R3, and are chosen small enough so that any bias current drawn by the non-inverting input of amplifier1310does not cause too much of a voltage change in the Vps/2 node1420.FIG. 14bis a modification of the circuit inFIG. 14ain which OPAMP1410is configured as a buffer. As a result, this implementation does not necessarily require low resistances for R11and R12. The circuit inFIG. 14amay be more frequently used in PCB (Printed Circuit Board) form designs, but the circuit inFIG. 14bmay be more suitable, and can easily be implemented in IC (Integrated Circuit) form designs.

The operation of the circuit and choice for the method for choosing resistance values R1, R2, R3, R4, R5, R6, and R7are similar to that ofFIG. 4, and consequently a detailed description is not needed to practice the disclosed embodiments.

The choice for the capacitance of C1should be such that it provides a low impedance to ground for the frequency range of interest. For example, for audio applications, if it is desirable to have good fidelity in the lower frequency ranges, then the capacitance for capacitor C1in the embodiment ofFIG. 13may be chosen as large as is practical. But for small, portable devices, such as audio amplifiers in battery-powered consumer devices, too large of a capacitor would make the device unwieldy and not marketable. Switched-capacitor circuits may be employed so that a relatively low effective impedance is provided for good fidelity, but where the actual capacitances are relatively small.

An embodiment in which a switched-capacitor is employed to increase the effective capacitance is illustrated inFIG. 15a. Node A inFIG. 15ais to be identified with node A inFIG. 13, and capacitor C1inFIG. 15ais to be identified with capacitor C1inFIG. 13, so that box1501indicates the other components ofFIG. 13. Switches1502,1504,1506, and1508switch capacitors C2and C3in parallel with capacitor C1. These switches are controlled by switch logic signal s(t).

A typical waveform representing s(t) is given inFIG. 15b, indicating a period of T seconds and a duty cycle of 50%. Each switch toggles between its two states depending upon whether s(t) is a logic LOW or a logic HIGH. The switches are configured so that when switches1502and1506are in their “lower” positions, switches1504and1508are in their “upper” positions, and conversely, when switches1502and1506are in their upper positions, switches1504and1508are in their lower positions. In this way, for any given switching period, for one-half of the switching period capacitor C2is connected from node A to the power supply rail at voltage Vps and capacitor C3is connected from node A to ground; and for the other half of the switching period capacitor C2is connected from node A to ground and capacitor C3is connected from node A to the power supply rail.

The above description of the switched-capacitor circuit may be visualized by referring toFIGS. 16aand16b.FIG. 16ashows the circuit connections when switches1502and1506are in their lower positions, and when switches1504and1508are in their upper positions. We will refer toFIG. 16aas the first switch state.FIG. 16bshows the circuit connections when switches1502and1506are in their upper positions, and when switches1504and1508are in their lower positions. We will refer toFIG. 16bas the second switch state. InFIGS. 16aand16b, the terminals of capacitors C2and C3have been labeled with a “U” or a “L” to show how the terminals are connected. A “U” terminal is an “upper” terminal when viewing the corresponding capacitor symbol inFIG. 15a. Similarly, a “L” terminal is a “lower” terminal when viewing the corresponding capacitor symbol inFIG. 15a.

Referring now toFIG. 13, if C1were an ideal capacitor with unlimited capacitance and if the input voltage Vin(t) had a time-average equal to Vps/2, then under ideal conditions the time-average of the node voltage at node A would be held at Vps/2. Consequently, in practice, it is desirable for the switched-capacitor circuit to try holding the time-average voltage at node A at Vps/2. By considering the two states inFIGS. 16aand16b, we see how the switched-capacitor circuit inFIG. 15atries to achieve this goal. For example, assume that initially all capacitors are charged to have a potential difference of Vps/2. Suppose the circuit were in the first switch state ofFIG. 16a. If the voltage at node A were to suddenly start to rise above Vps/2, then capacitors C1and C2would receive excess charge (i.e., will charge up to a voltage difference greater than Vps/2) and C3would lose charge (i.e., be discharged to a voltage difference less than Vps/2). Then when the switched-capacitor circuit enters the second switch state ofFIG. 16b, capacitors C1and C2dump some of their charge to capacitor C3, thus restoring to some degree their initial states of having equal potential differences of Vps/2. In this way, the switched-capacitor circuit tries to maintain a time-average voltage of Vps/2 on capacitor C1. A similar argument may be made for the case in which the voltage at node A suddenly starts to fall below Vps/2.

In this way, the switched-circuit emulates a relatively low effective impedance that is significantly lower than the impedance of the sum of the actual physical capacitances of capacitors C2and C3. The capacitances of capacitors C2and C3may, but need not, be chosen to be equal to each other. Furthermore, from the symmetry of their roles, it is seen that the switched-capacitor circuit inFIG. 15amay be modified in which switches1504and1508, and capacitor C3, are removed. Also, the duty cycle for s(t) need not be 50%.

In practice, the one-sided spectral power density for Vin(t) is limited to some finite frequency range, say in the range0to B Hertz. The switching frequency of s(t) should be chosen high enough so that it is significantly higher than the high end of this range of frequencies. For example, the switching frequency may be chosen to be 10 KHz when audio signals are to be amplified.

Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below. For example, the embodiments ofFIG. 4orFIG. 13may be modified to include the diode arrays ofFIG. 11, where one diode array is connected in parallel with resistor R2and another is connected in parallel with resistor R4.

As another example, the amplifier circuits described above may share the same capacitor C1. That is, referring toFIG. 13, this circuit, excluding capacitor C1, may be replicated to drive another load, such as a speaker belonging to a pair of headphones. The resulting circuit is then two separate amplifiers, each with a different input signal, such as the left and right channels of a stereophonic audio signal, where each amplifier drives a separate speaker and both amplifiers shares the capacitor C1. For such an embodiment, the switching-capacitor circuit inFIG. 15amay also be added so as to connect to node A.

As another example, referring toFIG. 3a, output port312aof amplifier304amay be coupled directly to load port334a, instead of via switch306a, in which case controller314acontrols amplifier304aso that it does not drive load308awhen switch306ais in its first state but drives load308awhen switch306ais in its second state.

For example, referring toFIG. 18, amplifier1804has its output port coupled directly to load1808(perhaps via a load port) instead of coupled to a switch. Controller1814controls amplifier1804so that amplifier1804is not driving load1808when switch1806is coupling load1808to capacitor1810, but amplifier1804is controlled to drive load1808when switch1806is not coupling load1808to capacitor1810.

Controller1814may control amplifier1804in various ways, and such methods are well knows to those skilled in the art of amplifiers. For example, a bias current for amplifier1804may be adjusted so that amplifier1804is put into an active mode to drive load1808when the bias current is at some nominal level, and where amplifier1804is put into an inactive mode when the bias current is at zero, or close to zero.

Observe that inFIG. 18, controller1814is shown coupled to amplifier1802in a general way, rather than coupled directly to its output port. That is, for some embodiments, controller1814may monitor a measurable quantity other than the output voltage of amplifier1802. For example, the input voltage Vin(t) may be monitored, or internal voltages or currents within amplifier1802may be monitored.

More generally, controller1814monitors one or more quantities, and a logic signal is outputted in response to the one or more quantities so that amplifier1804is either driving load1808or not driving load1808. That is, a binary decision is made based upon one or more monitored quantities. Such a binary decision may be described by first introducing some notation.

Let x1(t), x2(t), . . . , xn(t) denote n measurable quantities upon which a binary decision is made. The ordered set (x1(t), x2(t), . . . , xn(t)) may be thought of as a point in n-dimensional real space. (The n-dimensional real space is usually denoted as |n.) During circuit operation, each of these quantities will have some range, so that the point (x1(t), x2(t), xn(t)) defines a region in n-dimensional real space as each quantity is allowed to vary over its range of values. This region will be referred to as the operating region of amplifier1802. Let R denote a region that is a proper subset of the operating region. (That is, R is not the entire operating region.). Let D denote a decision, e.g., the decision D is that amplifier1804is not driving load1808. Let D# denote the logical complement of D. (For example, D# is the decision that amplifier1804is driving load1808.) With this notation in mind, a memoryless decision function may be represented as follows: At time t, choose decision D if (x1(t), x2(t), . . . , xn(t)) lies in the region R, otherwise, choose decision D#. Embodiments of the present invention are not necessarily limited to memoryless decisions.

For a specific example of the above discussion regarding a general decision function, referring toFIG. 18, suppose decision D is the state for which amplifier1804is not driving load1808and switch1806is coupling load1808to capacitor1810. The measured quantity may be Vin(t), and the region R may be the interval [Vps/2−Vth, Vps/2+Vth] where 0<Vth<Vps/2. In practice, the region R may not necessarily be the entire region for which amplifier1802is operating linearly. The conditions under which amplifier1802is operating linearly may not be precisely known, and may vary from die to die due to process variation. Accordingly, a conservative approach may be taken in which the region R is a proper subset of the region for which amplifier1802is linear. In other words, that portion of the operating region outside of the region R may represent quantities x1(t), x2(t), . . . , xn(t) for which amplifier1802is linear, is in pre-saturation, or is in saturation. In practice, to save power, the region R may be chosen to include most of the region for which amplifier1802is operating linearly.

More generally, from the above description of some of the embodiments, it is seen that various quantities of a first amplifier are measured or monitored, thereby defining an operating region. When the various monitored quantities are in a region R, where R is a proper subset of the operating region, a second amplifier is controlled so as to not drive the load. This may be accomplished by disconnecting the output port of the second amplifier from the load by way of a switch, or by putting the second amplifier in a mode in which little power is consumed and for which it does not drive the load. When the various monitored quantities are not in the region R, the second amplifier is controlled so as to drive the load.

It should be appreciated that when the second amplifier is put into an inactive mode in which it does not drive the load, the second amplifier may consume some power, and a relatively small amount of power may nevertheless be delivered to the load. However, the second amplifier does not drive the load in the sense that any power delivered to the load by the second amplifier is negligible compared to what it is capable of delivering to the load. Accordingly, in the claims, stating that the second amplifier does not appreciably drive the load is meant to reflect the situation where any power delivered to the load by the second amplifier is negligible compared to the power that it is capable of delivering to the load.

Another embodiment is illustrated inFIG. 19. Amplifier1902drives load1904, and amplifier1906is connected to load1904so as to drive load1904when active, and to not appreciably drive load1904when inactive. A bias current to amplifier1906is controlled by transistor Q1. When the output voltage of amplifier1902is inside the voltage window defined by Vth1and Vth2, that is, when the output voltage Vo1(t) is such that Vth2<Vo1(t)<Vth1, then the combination of logic gate1916drives transistor Q1OFF, so that amplifier1906is starved of bias current and is put into an inactive mode. When the output voltage Vo1(t) falls outside the window defined by Vth2and Vth1, then logic gate1916drives transistor Q1ON, so that bias current is provided to amplifier1906so that it is now actively driving load1904.

In the embodiment ofFIG. 19, module1920, denoted as a charge-pump, may be switched-capacitor circuit theFIG. 15a, so as to provide a low impedance to load1904when switching transistors Q3and Q4are ON.

Note that transistors Q4and Q3serve as the switch for connecting capacitor C4to load1904. The gate of the switch (transistors Q4and Q3) is controlled by NOR gate1914, where one side of the switch is connected to the inverting input port of comparator1918and the other side is connected to the non-inverting input port of comparator1918. When the output voltage of amplifier1902goes outside the voltage window [Vth1, Vth2], capacitor C4is not immediately switched out. However, with the arrangement of comparator1918with logic gates1908,1910,1912, and1914, as amplifier1906is powered-up into its active mode, the current through the switch will decrease. As this current decreases, the magnitude of the voltage drop across the switch will decrease, and when it decreases to a small enough value, comparator1918will trip, causing logic gate1914to turn OFF transistors Q4and Q3. Comparator1918may have a threshold that is substantially zero, as shown inFIG. 19, or a small value close to zero.

In this way, when amplifier1906is powered-up into its active mode, there is a delay before capacitor C4is disconnected from load1904. Other embodiments may employ a module to implement a delay between activating amplifier1906and switching out the capacitive load. This procedure is illustrated in the flow diagram ofFIG. 20. In module2002, the output voltage of the (first) amplifier driving the load is monitored. If it falls outside the voltage window, then module2004puts the second amplifier into an active mode. A delay is introduced by module2006, after which the capacitive load is switched out in module2008. Module2010again monitors the output voltage of the first amplifier, and if it falls within the voltage window, then in module2012the second amplifier is deactivated and the capacitive load is switched to the load, and control is brought back to module2002.

The flow diagram ofFIG. 20is a conceptual way to describe the actions of a circuit. The modules inFIG. 20may represent various sub-circuits, and a sub-circuit may provide the functions of more than one module.

Throughout the description of the embodiments, equalities, or the like, were used in various equations or in various descriptions. For example, a gain may have been set to equal one, or a voltage at one node may have been set to equal a voltage at another node, or the variations in a node voltage due to variations in a first voltage were set to cancel the variations in the node voltage due to variations in a second voltage. Of course, these equalities, or the like, are in practice not satisfied exactly, and should therefore be interpreted as “designed for” equalities, or the like. That is, one of ordinary skill in the art may design various working embodiments to satisfy various conditions, but these conditions can only be met within the tolerances of the technology available to the practitioner. Accordingly, in the following claims, the word “substantially” is used to reflect this fact. For example, a claim may recite that one resistance is substantially equal to another resistance, or that one voltage is substantially equal to another voltage. It is to be understood that “substantially” is a term of art, and is meant to convey the principle discussed above that equalities, or the like, cannot be met with exactness, but only within the tolerances of the technology available to a practitioner.

Furthermore, it is to be understood in these letters patent that the meaning of “A is connected to B”, where A or B may be, for example, a node or device terminal or port, is that A and B are connected to each other so that the voltage potentials of A and B are substantially equal to each other. For example, A and B may be connected by way of an interconnect, transmission line, etc. In integrated circuit technology, the “interconnect” may be exceedingly short, comparable to the device dimension itself. For example, the gates of two transistors may be connected to each other by polysilicon or copper interconnect that is comparable to the gate length of the transistors. As another example, A and B may be connected to each other by a switch, such as a transmission gate, so that their respective voltage potentials are substantially equal to each other when the switch is ON.

It is also to be understood that the meaning of “A is coupled to B” is that either A and B are connected to each other as described above, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B. This device or circuit may include active or passive circuit elements. For example, A may be connected to a circuit element, which in turn is connected to B.

Various logical relationships may be claimed. As customary in logic, “A only if B” means “if A is true, then B is true”; “A if B” means “if B is true, then A is true”; and “A if and only if B” means “if A is true, then B is true; and if B is true, then A is true.”

It is also to be understood that various circuit blocks, such as current mirrors, amplifiers, etc., may include switches so as to be switched in or out of a larger circuit, and yet such circuit blocks may still be considered connected to the larger circuit because the various switches may be considered as included in the circuit block.