POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICE

In an RFC diode, a semiconductor substrate includes an n− drift layer, an n buffer layer, and a diffusion layer provided between and in contact with the n buffer layer and a second metal layer. The diffusion layer includes an n+ cathode layer provided in contact with the n buffer layer and the second metal layer in a diode region. The n+ cathode layer includes a first n+ cathode layer in contact with the second metal layer and a second n+ cathode layer provided between the first n+ cathode layer and the n buffer layer in contact with the n buffer layer. Crystal defect density of the first n+ cathode layer is higher than crystal defect density of another diffusion layer.

FIELD OF THE INVENTION

The present disclosure relates to a power semiconductor device.

DESCRIPTION OF THE BACKGROUND ART

Japanese Patent Application Laid-Open No. 2017-201644 discloses a power diode having two n buffer layers. Between the two n buffer layers, a low carrier lifetime control layer is provided in an n buffer layer in contact with a high concentration n+ layer on the cathode side. By the above, tail current is suppressed during recovery operation of the power diode, that is, reverse recovery switching operation, and as a result, recovery loss is reduced.

The power diode of Japanese Patent Application Laid-Open No. 2017-201644 basically has two n buffer layers having different carrier lifetimes. For this reason, the power diode of Japanese Patent Application Laid-Open No. 2017-201644 can shift a trade-off characteristic between on-voltage and switching loss, which are performance indexes of a power semiconductor device, to the high-speed side without using a carrier lifetime control method. Here, the carrier lifetime control method is, for example, control using a charged particle system of an electron beam, proton, or helium, or a heavy metal system of platinum.

However, there has been a problem that voltage holding capability when a reverse bias is applied to a main junction, which is an action of an n buffer layer, is deteriorated, and voltage interrupting capability, which is basic performance of a power semiconductor, such as reduction of off-loss due to reduction of leakage current during voltage holding, is deteriorated.

Further, there has been a problem that it is difficult to realize high-temperature operation which is a trend in power semiconductor devices due to increase in leakage current during voltage holding.

SUMMARY

An object of a technique of the present disclosure is to shift a trade-off characteristic between on-voltage and switching loss to the high-speed side regardless of a carrier lifetime control method in a power semiconductor device, and to realize low off-loss and high temperature operation.

The power semiconductor device of the present disclosure includes a semiconductor substrate, a first metal layer, and a second metal layer.

The semiconductor substrate has a first main surface and a second main surface facing each other.

The first metal layer is provided on the first main surface of the semiconductor substrate.

The second metal layer is provided on the second main surface of the semiconductor substrate.

The semiconductor substrate includes a drift layer of a first conductivity type, a buffer layer of the first conductivity type, and a diffusion layer.

The buffer layer is provided between the drift layer and the second main surface.

The diffusion layer is provided between and in contact with the buffer layer and the second metal layer.

A partial region in plan view of the power semiconductor device is a diode region that operates as a diode.

The diffusion layer includes a cathode layer of a first conductivity type.

The cathode layer is provided in contact with the buffer layer and the second metal layer in at least a part of the diode region.

The cathode layer includes a first cathode layer and a second cathode layer.

The first cathode layer has one impurity concentration peak point and is in contact with the second metal layer.

The second cathode layer has one impurity concentration peak point and is provided between the first cathode layer and the buffer layer so as to be in contact with the buffer layer.

Crystal defect density of the first cathode layer is higher than crystal defect density of another diffusion layer.

In the power semiconductor device of the present disclosure, the crystal defect density of the first cathode layer is higher than crystal defect density of another diffusion layer.

Therefore, it is possible to shift a trade-off characteristic between on-voltage and switching loss to the high-speed side regardless of a carrier lifetime control method, and to realize low off-loss and high temperature operation.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a preferred embodiment will be described with reference to the attached drawings. Note that the drawings are schematically illustrated, and a mutual relationship between sizes and positions of images illustrated in different drawings is not necessarily accurately described, and can be appropriately changed. Further, in description shown below, similar constituent elements are illustrated with the same reference numerals. This similarly applies to their names and functions. Therefore, there is a case where detailed description of them is omitted.

Further, in description below, terms meaning specific positions and directions such as “upper”, “lower”, “side”, “bottom”, “front”, or “back” may be used, but these terms are used for convenience to facilitate understanding of content of a preferred embodiment, and do not limit directions in actual implementation.

Further, in description below, regarding a conductivity type of a semiconductor, a first conductivity type is an n-type and the second conductivity type is a p-type, but the conductivity types may be opposite.

Further, regarding a conductivity type of a semiconductor, n− represents that n− type impurity concentration is smaller than n, and n+ represents that n-type impurity concentration is larger than n. Similarly, p− represents that p-type impurity concentration is smaller than p, and p+ represents that p-type impurity concentration larger than p.

A. First Preferred Embodiment

FIG.1schematically illustrates a planar structure of a vertical power semiconductor device. As illustrated in the diagram, a plurality of active cell regions R1are formed in a central portion, a surface gate wiring portion R12is provided between two of the active cell regions R1, and a gate pad portion R11is further provided in a partial region.

An intermediate region R2is formed surrounding the active cell region R1, the gate pad portion R11, and the front gate wiring portion R12, and a termination region R3is provided further surrounding a periphery of the intermediate region R2.

The active cell region R1described above is an element formation region that ensures basic performance of the power semiconductor device. Then, a peripheral region including the intermediate region R2and the termination region R3is provided for maintaining withstand voltage including reliability. Among them, the intermediate region R2is a region in which the active cell region R1and the termination region R3are joined to each other, which guarantees breakdown resistance during dynamic operation of the power semiconductor and supports original performance of a semiconductor element in the active cell region R1. Further, the termination region R3guarantees withstand voltage retention in a static state, stability and reliability of a withstand voltage characteristic, suppresses failure in breakdown resistance during dynamic operation, and supports original performance of the active cell region R1.

However, in a case where the power semiconductor device is a diode, the surface gate wiring portion R12and the gate pad portion R11do not need to be provided.

FIGS.2and3illustrate a cross-sectional configuration of a Relaxed Field of Cathode (RFC) diode, which is an example of the power semiconductor device, taken along line A1-A1′ inFIG.1.FIG.2is a cross-sectional view of a conventional RFC diode1000, andFIG.3is a cross-sectional view of an RFC diode1001according to a first preferred embodiment. In the diagrams, the conventional RFC diode1000may be referred to as Con. RFC diode, and the RFC diode1001according to the first preferred embodiment may be referred to as New RFC diode1.

First, the conventional RFC diode1000will be described. The RFC diode1000includes a semiconductor substrate20, a first metal layer5, and a second metal layer11. The semiconductor substrate20includes a first main surface21which is an upper main surface inFIGS.2and3, and a second main surface22facing the first main surface21. The first metal layer5is provided on the first main surface21of the semiconductor substrate20, and the second metal layer11is provided on the second main surface22of the semiconductor substrate20.

The semiconductor substrate20includes a p anode layer6, an n− drift layer7, an n buffer layer8, an n+ cathode layer9, and a p cathode layer10. The p anode layer6is provided between the n− drift layer7and the first main surface21. A surface of the p anode layer6constitutes the first main surface21of the semiconductor substrate20. The n buffer layer8is provided between the n− drift layer7and the second main surface22. The n+ cathode layer9and the p cathode layer10are provided between the n buffer layer8and the second main surface22. Surfaces of the n+ cathode layer9and the p cathode layer10constitute the second main surface22of the semiconductor substrate20and are in contact with the second metal layer11.

A pin diode region31is constituted by a vertical region including the n+ cathode layer9, that is, the n+ cathode layer9and the n buffer layer8, the n− drift layer7, and the p anode layer6above the n+ cathode layer9. Further, a pnp transistor region32is constituted by a vertical region including the p cathode layer10, that is, the p cathode layer and the n buffer layer8, the n− drift layer7, and the p anode layer6above the p cathode layer. As described above, the RFC diode1000has a configuration in which the pin diode region31and the pnp transistor region32are alternately arranged in plan view.

The n− drift layer7is formed using a Si wafer having impurity concentration Cn−of 1.0×1012atoms/cm3or more and 1.0×1015atoms/cm3or less. That is, the semiconductor substrate20is a Si substrate. Device thickness tdevice, which is thickness of the semiconductor substrate20, is 40 μm or more and 700 μm or less.

The p anode layer6has impurity concentration of 1.0×1016atoms/cm3or more on a surface in contact with the first metal layer5, that is, on the first main surface21, peak impurity concentration of 2.0×1016atoms/cm3or more and 1.0×1018atoms/cm3or less, and a depth of 2.0 μm or more and 10.0 μm or less.

In the n buffer layer8, peak impurity concentration Cnb, pis 1.0×1015atoms/cm3or more and 5.0×1016atoms/cm3or less, and the depth Xj, nbis 1.2 μm or more and 50 μm or less.

Next, the RFC diode1001according to the first preferred embodiment will be described. The RFC diode1001is different from the conventional RFC diode1000in that the RFC diode1001includes an n+ cathode layer90instead of the n+ cathode layer9and a p cathode layer100instead of the p cathode layer10. In the RFC diode1001, the n+ cathode layer90has a two-layer structure including a first n+ cathode layer91and a second n+ cathode layer92, and the p cathode layer100has a two-layer structure including a first p cathode layer101and a second p cathode layer102. Note that the first p cathode layer101is also referred to as a first diffusion layer, and the second p cathode layer102is also referred to as a second diffusion layer.

Hereinafter, the first n+ cathode layer91may be referred to as a first cathode layer, and its conductivity type may be denoted as n+1 in the diagram. Further, the second n+ cathode layer92may be referred to as a second cathode layer, and its conductivity type may be denoted as n+2 in the diagram. A conductivity type of the first p cathode layer101may be referred to as p1. A conductivity type of the second p cathode layer102may be referred to as p2.

The first n+ cathode layer91and the first p cathode layer101are in contact with the second metal layer11. The second n+ cathode layer92and the second p cathode layer102are in contact with the n buffer layer8. Lower surfaces of the first n+ cathode layer91and the first p cathode layer101inFIG.3constitute the second main surface22of the semiconductor substrate20.

The first n+ cathode layer91has impurity concentration of 1.0×1018atoms/cm3or more and 1.0×1020atoms/cm3or less on a surface in contact with the second metal layer11, that is, on the second main surface22, and has a depth of 0.1 μm or more and 0.2 μm or less.

The second n+ cathode layer92has peak impurity concentration of 1.0×1017atoms/cm3or more and 1.0×1019atoms/cm3or less and a depth of 0.3 μm or more and 0.5 μm or less.

The first p cathode layer101has impurity concentration of 1.0×1017atoms/cm3or more and 1.0×1019atoms/cm3or less on a surface in contact with the second metal layer11, that is, on the second main surface22, and has a depth of 0.1 μm or more and 0.2 μm or less.

The second p cathode layer102has peak impurity concentration of 1.0×1016atoms/cm3or more and 1.0×1018atoms/cm3or less and a depth of 0.3 μm or more and 0.5 μm or less.

In the present preferred embodiment, the n+ cathode layer90is composed of two layers of the first n+ cathode layer91and the second n+ cathode layer92, and the p cathode layer100is composed of two layers of the first p cathode layer101and the second p cathode layer102. A purpose of each layer is as described below.

The first n+ cathode layer91and the first p cathode layer101are diffusion layers for improving contact property with the second metal layer11. Crystal defect density of the first n+ cathode layer91is higher than crystal defect density of the second n+ cathode layer92, the first p cathode layer101, and the n buffer layer8. The second n+ cathode layer92and the second p cathode layer102are diffusion layers for controlling performance of the RFC diode1001and ensuring normal on-operation.

An impurity profile and a depth of the diffusion layer may be determined by a range (RP) at the time of ion implantation from a characteristic of an annealing technique at the time of formation of the diffusion layer. Here, the range is defined as a depth from second main surface22to a position of peak concentration of each diffusion layer. Therefore, a range at the time of ion implantation when the first n+ cathode layer91, the second n+ cathode layer92, the first p cathode layer101, and the second p cathode layer102are formed is determined by Equation (1) below so that the layers do not interfere with each other.

Here, Rn+1, Rn+2, Rp1, and Rp2represent ranges (m) of the first n+ cathode layer91, the second n+ cathode layer92, the first p cathode layer101, and the second p cathode layer102, respectively.

FIG.4illustrates impurity concentration in a diffusion layer of the RFC diode1001along lines B-B′ and C-C′ ofFIG.3. InFIG.4, the horizontal axis represents a depth (μm) from the second main surface22of the semiconductor substrate20, and the vertical axis represents impurity concentration (atoms/cm3). InFIG.4, a solid line indicates impurity concentration along line B-B′, and a broken line indicates impurity concentration along line C-C′.

Hereinafter, performance of the RFC diode1001according to the first preferred embodiment will be described.FIG.5illustrates PL spectra when the n+ cathode layer9and the p cathode layer10in the conventional RFC diode1000and the first n+ cathode layer91, the second n+ cathode layer92, the first p cathode layer101, and the second p cathode layer102in the RFC diode1001according to the first preferred embodiment are analyzed by a photoluminescence (PL) method. The PL method is an analysis method of irradiating a semiconductor with light and observing light emitted when electrons and holes are recombined via a defect level. The horizontal axis ofFIG.5represents photon energy (eV), and the vertical axis ofFIG.5represents PL intensity normalized by intensity of a band edge.

An analysis condition of the PL method is as described below. A He—Ne laser with a wavelength of 633 nm is used. Temperature is 30 K. Output of a laser beam with which a sample surface is irradiated is set to 4.5 mW. A diameter of the laser beam is 1.3 μm. Intensity of the laser beam on the sample surface is 0.339 MW/cm2.

FIG.5shows that there are two peaks in PL intensity in the 1 n+ cathode layer91. A first peak is due to a trap A with photon energy of 0.969 eV, and a second peak is due to a trap B with photon energy of 1.018 eV. The traps A and B are energy levels derived from CiCs (G-center) and W-center, respectively. The trap A is also referred to as a first lattice defect, and the trap B is also referred to as a second lattice defect.

As described above, there are two traps in the first n+ cathode layer91. The second n+ cathode layer92is formed by a process described in a fourth preferred embodiment described later. The traps A and B, which are crystal defects in the first n+ cathode layer91, are formed by reacting with impurities in Si such as oxygen, carbon, or hydrogen by steps below.

Step A: Ion implantation is performed on the second main surface22of the semiconductor substrate20to form a lattice defect such as an interstitial Si pair (Isi) and a vacancy (V).

Step B: The lattice defect formed in Step A is diffused and self-aggregation occurs, and V2and an interstitial Si pair (Isj: W-center) are formed.

Step C: At the same time as Step B, a substitution reaction of a carbon atom (Cs) present at a lattice position and an interstitial Si pair (Isi) occurs to form an interstitial carbon (Ci).

Step D: Diffusion of the interstitial carbon (Ci) and the lattice defect (vacancy (V)) causes a reaction of the substitutional carbon (Cs) and the interstitial Si pair (Isi) with impurities (oxygen, carbon, and hydrogen) in Si at room temperature, and an impurity defect (composite defect: CiCs) is generated.

Step E: Crystallinity is restored by annealing treatment, but some interstitial Si pairs (Isi: W-center) and impurity defects (composite defects: CiCs) remain.

Here, the subscript i represents interstitial, and the subscript s represents substitutional.

As described above, a crystal defect exists in the first n+ cathode layer91. The fact that diode performance of RFC diode1001is improved and thermally stable performance is obtained by the crystal defect will be described below by diode performance of the 1200 V class.

FIG.6illustrates a trade-off characteristic between on-voltage VFand switching loss ERECfor each of the conventional RFC diode1000and the RFC diode1001according to the first preferred embodiment. In the trade-off characteristic of the RFC diode1001, a relationship between a dose amount of the first n+ cathode layer91and a dose amount of the second n+ cathode layer92is shown as a parameter. The trade-off characteristic of the RFC diode1000is a result of control by lifetime control using an electron beam which is a charged particle. Con. RFC diode1in the diagram is the RFC diode1000without lifetime control by electron beam irradiation. Both Con. RFC diode2and Con. RFC diode3are the RFC diodes1000for which lifetime control by electron beam irradiation is performed, but an amount of irradiation at the time of electron beam irradiation is larger in Con. RFC diode3than in Con. RFC diode2.

In the RFC diode1001, each layer is formed by a process described in the fourth preferred embodiment such that a relationship between a dose amount of the first n+ cathode layer91and a dose amount of the second n+ cathode layer92satisfies Equation (2) below, so that contact property between the first n+ cathode layer91and the second metal layer11is improved, and stable electron injection from the first n+ cathode layer91is realized when the RFC diode1001is in an on state.

Here, Dn+1represents the number of atoms (atoms/cm2) per unit area of the first n+ cathode layer91, and Dn+2represents the number of atoms (atoms/cm2) per unit area of the second n+ cathode layer92. The number of atoms per unit area (atoms/cm2) is a value obtained by integrating the number of atoms per unit volume (atoms/cm3) in a region of a diffusion layer in a depth direction. The number of atoms per unit volume (atoms/cm3) is an analysis value by secondary ion mass spectrometry (SIMS).

Further, in order for the RFC diode1001to perform normal on operation, the first n+ cathode layer91and the second p cathode layer102need to satisfy Equation (3) below with respect to a dose amount. A trade-off characteristic of the RFC diode1001illustrated inFIG.6is a result in a cathode structure that satisfies Equation (3). As described above, according to the RFC diode1001, the high-speed side of a curve of a trade-off characteristic realized by the conventional RFC diode1000by lifetime control using an electron beam can be realized without the lifetime control.

FIG.7illustrates an output characteristic of the RFC diode1001at 298 K. In the RFC diode1001, from a relationship between a characteristic cathode structure illustrated inFIG.3and a process illustrated in the fourth preferred embodiment, it is necessary to invert the first p cathode layer101and the second p cathode layer102to n layers to form the first n+ cathode layer91and the second n+ cathode layer92. For this reason, in order for the RFC diode1001to normally perform on operation, the first n+ cathode layer91and the second p cathode layer102need to satisfy Equation (3) below with respect to a dose amount. By the above, as illustrated inFIG.7, normal on operation is guaranteed without generation of a snap-back characteristic.

Here, Dn+2represents the number of atoms (atoms/cm2) per unit area of the second n+ cathode layer92, and Dp2represents the number of atoms (atoms/cm2) per unit area of the second p cathode layer102.

Next, diode performance of the RFC diode1001satisfying Equations (2) and (3) will be described.

FIG.8illustrates an output characteristic of the conventional RFC diode1000and the RFC diode1001according to the first preferred embodiment. InFIG.8and diagrams that follow, the RFC diode1000without lifetime control by an electron beam is denoted as Con. RFC diode1, and the RFC diode1000with lifetime control by an electron beam is denoted as Con. RFC diode2or Con. RFC diode3.

FIG.8shows that the RFC diode1001has lower current density at a cross-point where an output characteristic at 298 K and an output characteristic at 423 K cross each other than that of the conventional RFC diode1000.

FIG.9illustrates operation temperature dependency of the on-voltage VFof the conventional RFC diode1000and the RFC diode1001according to the first preferred embodiment. The RFC diode1001has positive operation temperature dependency of the on-voltage VFas compared with the conventional RFC diode1000. The conventional RFC diode1000without lifetime control by an electron beam is denoted as Con. RFC diode1inFIG.9. In the conventional RFC diode1000without lifetime control by an electron beam, operation temperature dependency of the on-voltage VFis negative. As shown by Con. RFC diode3, when lifetime control by an electron beam is performed on the conventional RFC diode1000, operation temperature dependency of the on-voltage VFchanges, but behavior is limited by temperature dependency of an impurity defect generated by the electron beam. Here, a main impurity defect generated by the electron beam is a composite defect CiOior C-center having photon energy of 0.789 eV.

Since a power semiconductor device such as an RFC diode is finally mounted on a power module and incorporated into an inverter system, parallel operation needs to be guaranteed. In order to minimize a temperature difference between chips when a large number of chips perform parallel operation, current density of the cross-point is desirably low and operation temperature dependency of the on-voltage VFis desirably positive. When operation temperature dependency of the on-voltage VFis negative during parallel operation of a large number of chips, a phenomenon of breakdown due to current concentration in a specific chip is likely to be induced. However, when operation temperature dependency of the on-voltage VFis positive as in the RFC diode1001, breakdown due to current concentration in a specific chip is suppressed, and normal parallel operation can be guaranteed. That is, the characteristic of the RFC diode1001illustrated inFIGS.8and9is effective from the viewpoint of normal operation of a power module.

FIG.10illustrates a leakage characteristic when a reverse bias is applied to a main junction of the conventional RFC diode1000and the RFC diode1001according to the first preferred embodiment. InFIG.10, the horizontal axis represents the reverse voltage VR(V), and the vertical axis represents leakage current density JR(A/cm2).

In the conventional RFC diode1000, lifetime control using an electron beam is performed in order to control performance to the high-speed side on a trade-off curve inFIG.6. At that time, since an impurity defect (composite defect) is formed inside a device by the electron beam, leakage current caused by the defect increases. As a result, loss (off-loss: JR×VR) when the device holds voltage increases, and a problem occurs in terms of thermal design of a power module or a problem occurs in high-temperature operation.

On the other hand, although the RFC diode1001according to the first preferred embodiment includes the first n+ cathode layer91having high crystal defect density in order to control performance to the high-speed side on a trade-off curve, there is no impurity defect (composite defect) caused by an electron beam in the n− drift layer7and the n buffer layer8in which a depletion layer extends from a main junction for voltage holding when a reverse bias is applied to the main junction. Therefore, as illustrated inFIG.10, leakage current of the RFC diode1001is equivalent to leakage current of the conventional RFC diode1000in which lifetime control by an electron beam is not performed. That is, the RFC diode1001according to the first preferred embodiment has leakage current smaller than that of the conventional RFC diode1000while achieving high-speed operation, and is effective in terms of high-temperature operation and thermal stability.

FIG.11illustrates waveforms of the conventional RFC diode1000and the RFC diode1001according to the first preferred embodiment during recovery operation in a small current mode.

FIG.12is a diagram illustrating a relationship between the snap-off voltage Vsnap-offand power supply voltage VCCfor the conventional RFC diode1000and the RFC diode1001according to the first preferred embodiment. The snap-off voltage Vsnap-offis a maximum value of anode-cathode voltage VAKduring recovery operation. Recovery operation of a diode is excellent in terms of the breakdown tolerance of a diode when the snap-off voltage Vsnap-offis small and the power supply voltage VCCdependency of the snap-off voltage Vsnap-offis insensitive. Further, by setting the snap-off voltage Vsnap-offto rated withstand voltage or less, the snap-off voltage Vsnap-offcan be controlled to the rated withstand voltage or less, and it is possible to suppress diode breakdown caused by voltage instantaneously rising to the rated withstand voltage or more during recovery operation. In the present preferred embodiment, rating of the RFC diode1001is 1200 V.

Since this performance is remarkably exhibited in a sample without lifetime control by an electron beam, the conventional RFC diode1000compared inFIGS.11and12does not have lifetime control by an electron beam. These diagrams show that the RFC diode1001is superior to the conventional RFC diode1000in terms of breakdown resistance.

FIG.13illustrates changes in the on-voltage VFduring continuous energization test for the conventional RFC diode1000and the RFC diode1001according to the first preferred embodiment. In the conventional RFC diode1000(Con. RFC diode3) in which lifetime control by an electron beam is performed, an impurity defect (composite defect) generated by the electron beam is recovered by self-heating during energization of the diode, and the on-voltage VFdecreases during the continuous energization test. On the other hand, in the RFC diode1001according to the first preferred embodiment, in addition to the fact that lifetime control by an electron beam is not performed, the traps A and B, which are crystal defects in the first n+ cathode layer91, are thermally stable traps and do not change due to self-heating during energization of the diode. Therefore, the on-voltage VFdoes not decrease during the continuous energization test, and diode performance does not change with time.

As described above, the RFC diode1001according to the first preferred embodiment utilizes the traps A and B, which are crystal defects in the first n+ cathode layer91, to control a trade-off characteristic between the on-voltage VFand the switching loss ERECto the high-speed side regardless of a conventional lifetime control method, and also to achieve low off-loss, improved breakdown resistance, and thermal stability.

The performance of the RFC diode1001can be realized not only in a case where a Si wafer manufactured by a floating zone (FZ) method is used for the semiconductor substrate20but also in a case where a Si wafer manufactured by a magnetic applied Czochralski (MCZ) method having higher oxygen concentration and carbon concentration in a Si material is used. A Si wafer manufactured by the MCZ method has oxygen concentration of about 1.0×1017atoms/cm3or more and 7.0×1017atoms/cm3or less, and carbon concentration of about 1.0×1014atoms/cm3or more and 5.0×1015atoms/cm3or less. This is because a main crystal defect that controls diode performance in the RFC diode1001is not an impurity defect but an interstitial Si pair that is not formed by reaction with residual oxygen and residual carbon in Si.

The RFC diode1001, which is the power semiconductor device according to the first preferred embodiment, includes the semiconductor substrate20having the first main surface21and the second main surface22facing each other, the first metal layer5provided on the first main surface21of the semiconductor substrate20, and the second metal layer11provided on the second main surface22of the semiconductor substrate20. The semiconductor substrate20includes the n− drift layer7which is a drift layer of a first conductivity type, then buffer layer8provided between the n− drift layer7and the second main surface22, and a diffusion layer provided between the n buffer layer8and the second metal layer11so as to be in contact with the n buffer layer8and the second metal layer11. In the RFC diode1001, a partial region in plan view is the pin diode region31operating as a diode. In the RFC diode1001, a diffusion layer includes the n+ cathode layer90provided in contact with the n buffer layer8and the second metal layer11in at least a part of the pin diode region31. The n+ cathode layer90includes the first n+ cathode layer91which is a first cathode layer having one impurity concentration peak point and in contact with the second metal layer11, and the second n+ cathode layer92having one impurity concentration peak point and provided between the first n+ cathode layer91and the n buffer layer8so as to be in contact with the n buffer layer8. Crystal defect density of the first n+cathode layer91is higher than crystal defect density of another diffusion layer. Therefore, according to the RFC diode1001, a trade-off characteristic between the on-voltage VFand the switching loss ERECis controlled to the high-speed side regardless of a conventional lifetime control method, and low off-loss, improvement in breakdown resistance, and thermal stability are realized.

B. Second Preferred Embodiment

FIG.14illustrates a cross-sectional configuration of an RFC diode1002according to a second preferred embodiment taken along line A1-A1′ inFIG.1. In a diagram below, the RFC diode1002according to the second preferred embodiment may be referred to as a New RFC diode2. The RFC diode1002has a structure in which the first p cathode layer101is removed from the RFC diode1001according to the first preferred embodiment. In other words, in the RFC diode1002, the p cathode layer100is the second p cathode layer102. A structure of the RFC diode1002not specifically mentioned below is similar to that of the RFC diode1001according to the first preferred embodiment.

The n− drift layer7in the RFC diode1002is formed using a Si wafer having the impurity concentration Cn−of 1.0×1012atoms/cm3or more and 1.0×1015atoms/cm3or less.

FIG.15illustrates impurity concentration in a diffusion layer of the RFC diode1002along lines B-B′ and C-C′ inFIG.14. InFIG.15, the horizontal axis represents a depth (μm) from the second main surface22of the semiconductor substrate20, and the vertical axis represents impurity concentration (atoms/cm3). InFIG.15, a solid line indicates impurity concentration along line B-B′, and a broken line indicates impurity concentration along line C-C′.

A parameter of each diffusion layer constituting the RFC diode1002are as described below.

The p anode layer6, the n buffer layer8, the first n+ cathode layer91, and the second n+ cathode layer92are the same as those in the first preferred embodiment.

The second p cathode layer102has impurity concentration of 1.0×1017atoms/cm3or more and 1.0×1019atoms/cm3or less on a surface in contact with the second metal layer11, that is, on the second main surface22, and has a depth of 0.3 μm or more and 0.5 μm or less.

A relationship between a dose amount of the first n+ cathode layer91and a dose amount of the second n+ cathode layer92satisfies Equation (2).

FIG.16illustrates a relationship between Vsnap-offand the power supply voltage VCCduring the recovery operation in the small current mode of the RFC diode1001according to the first preferred embodiment and the RFC diode1002according to the second embodiment.

As can be seen fromFIG.16, in the RFC diode1002, similarly to the RFC diode1001according to the first preferred embodiment, performance in terms of breakdown resistance is guaranteed.

Further, since the RFC diode1002includes the same n+ cathode layer90as the RFC diode1001according to the first preferred embodiment, similarly to the RFC diode1001, the trade-off characteristic between the on-voltage VFand the switching loss ERECis controlled to the high-speed side regardless of a conventional lifetime control method, and low off-loss and thermal stability are realized.

In the RFC diode1002according to the second preferred embodiment, the p cathode layer100is the second p cathode layer102. That is, in the RFC diode1002, the p cathode layer100which is a diffusion layer of a second conductivity type has one impurity concentration peak point. Even in such a configuration, the RFC diode1002controls the trade-off characteristic between the on-voltage VFand the switching loss ERECto the high-speed side regardless of a conventional lifetime control method by the characteristic first n+ cathode layer91, and realizes low off-loss, improvement in breakdown resistance, and thermal stability.

C. Third Preferred Embodiment

FIG.17illustrates a cross-sectional configuration of an RFC diode1003according to a third preferred embodiment taken along line A1-A1′ inFIG.1. In a diagram below, the RFC diode1003according to the third preferred embodiment may be referred to as a New RFC diode3. The RFC diode1003is different from the RFC diode1001according to the first preferred embodiment in including an n buffer layer80instead of the n buffer layer8. The n buffer layer80has a two-layer structure including a first n buffer layer81and a second n buffer layer82. A structure of the RFC diode1003not specifically mentioned below is similar to that of the RFC diode1001according to the first preferred embodiment.

The n− drift layer7in the RFC diode1003is formed using a Si wafer having the impurity concentration Cn−of 1.0×1012atoms/cm3or more and 1.0×1015atoms/cm3or less.

FIG.18illustrates impurity concentration in a diffusion layer of the RFC diode1003along lines B-B′ and C-C′ inFIG.17. InFIG.18, the horizontal axis represents a depth (μm) from the second main surface22of the semiconductor substrate20, and the vertical axis represents impurity concentration (atoms/cm3). InFIG.18, a solid line indicates impurity concentration along line B-B′, and a broken line indicates impurity concentration along line C-C′.

The p anode layer6is similar to that of the first preferred embodiment.

In the first n buffer layer81, peak impurity concentration Cnb1, pis 1.0×1015atoms/cm3or more and 5.0×1016atoms/cm3or less, and the depth Xj, nb1is 1.2 μm or more and 50 μm or less.

The second n buffer layer82has a depth Xj, nb2of Xj, nb1+20 μm. Further, peak impurity concentration Cnb2, pof the second n buffer layer82is 0.01 times or less peak impurity concentration Cnb1, pof the first n buffer layer81. By the above, occurrence of a snap-back characteristic in the on state as illustrated inFIG.7is suppressed, and normal on operation of a diode is guaranteed.

FIG.19illustrates PL spectra when the first n buffer layer81and the second n buffer layer82of the RFC diode1003are analyzed by the PL method. The horizontal axis ofFIG.19represents photon energy (eV), and the vertical axis ofFIG.19represents PL intensity normalized by intensity of a band edge.

An analysis condition of the PL method inFIG.19is similar to the analysis condition of the PL method inFIG.5. It can be seen fromFIG.19that there are two peaks in the PL intensity in the second n buffer layer82. A first peak is due to the trap B with photon energy of 1.018 eV, and a second peak is due to a trap C with photon energy of 1.039 eV. The traps B and C are energy levels derived from W-center and X-center, which are interstitial Si pairs.

FIG.20illustrates a relationship between PL intensity and annealing temperature in the traps B and C in the second n buffer layer82. Annealing is performed in nitrogen atmosphere for 120 minutes. A technique of the present preferred embodiment mainly focuses on device performance control of a power diode by the trap B. FromFIG.20, it can be seen that annealing temperature for the trap B to be a main trap in the second n buffer layer is 370° C. or less.

FIG.21illustrates a trade-off characteristic between on-voltage VFand switching loss ERECfor each of the conventional RFC diode1000and the RFC diode1003according to the third preferred embodiment. Withstand voltage of the RFC diode having a characteristic illustrated inFIG.21is 4.5 kV.

By controlling a condition at the time of ion implantation when the second n buffer layer82is formed so that the peak impurity concentration Cnb2, pof the second n buffer layer82satisfies Cnb2, p≤0.01×Cnb1, pwith the peak impurity concentration Cnb1, pof the first n buffer layer81, it is possible to realize the high-speed side of the curve of the trade-off characteristic realized by the conventional RFC diode1000by the lifetime control using an electron beam without adversely affecting other device performance of the diode.

Further, since the RFC diode1003according to the third preferred embodiment controls power diode performance by utilizing an interstitial Si pair without the lifetime control, similarly to the first preferred embodiment, low off-loss, improvement in breakdown resistance, and thermal stability are realized.

In the RFC diode1003according to the third embodiment, the n buffer layer80includes the first n buffer layer81which is a first buffer layer having one impurity concentration peak point and in contact with a diffusion layer, and the second n buffer layer82which is a second buffer layer having one impurity concentration peak point and in contact with the n− drift layer7. Then, a crystal defect in the second n buffer layer82is the trap B which is a second lattice defect and the trap C which is a third lattice defect detected by a photoluminescence method. Therefore, according to the RFC diode1003, a trade-off characteristic between the on-voltage VFand the switching loss ERECis controlled to the high-speed side regardless of a conventional lifetime control method, and low off-loss, improvement in breakdown resistance, and thermal stability are realized.

D. Fourth Preferred Embodiment

In the present preferred embodiment, a method for manufacturing the RFC diode1001according to the first preferred embodiment will be described.FIGS.22to30are cross-sectional views illustrating the method for manufacturing the RFC diode1001.FIGS.29and30illustrate a detailed process for forming a back side structure of the RFC diode1001.

A characteristic of the method for manufacturing the RFC diode1001is as described below. First, after ion implantation for forming the first p cathode layer101and the second p cathode layer102, ion implantation for forming the first n+ cathode layer91and the second n+ cathode layer92and annealing are present. Further, there is no lifetime control process. Further, the second metal layer11is for a two-layer diffusion layer structure.

Hereinafter, the method for manufacturing the RFC diode1001will be described with reference toFIGS.22to30.FIG.22illustrates the active cell region R1, and the intermediate region R2and the termination region R3formed so as to surround the active cell region R1. First, the semiconductor substrate20on which only the n− drift layer7is formed is prepared. Then, a plurality of p layers52are selectively formed on a surface of the n− drift layer7in the intermediate region R2and the termination region R3. The p layer52is formed by performing ion implantation using an oxide film62formed in advance as a mask and then performing annealing processing on the semiconductor substrate20. Note that an oxide film68at the time of formation of the oxide film62also formed on the second main surface22of the semiconductor substrate20.

Next, as illustrated inFIG.23, ion implantation and annealing processing are performed on a surface of the n− drift layer7in the active cell region R1to form the p anode layer6.

Subsequently, as illustrated inFIG.24, an n+ layer56is formed in an end portion of the termination region R3on the first main surface21side of the semiconductor substrate20. Next, a TEOS layer63is formed on an upper surface of the semiconductor substrate. After the above, processing of removing the oxide film68to expose the second main surface22of the semiconductor substrate20is performed. Then, a doped polysilicon layer65doped with an impurity is formed so as to be in contact with the n− drift layer7exposed on the second main surface22of the semiconductor substrate20. The impurity of the doped polysilicon layer65is, for example, an atom that diffuses into Si and can form an n+ layer, such as phosphorus, arsenic, or antimony. The doped polysilicon layer65is a film doped with high-concentration impurities of 1×1019atoms/cm3or more, and has film thickness of 500 nm or more. At this time, a doped polysilicon layer64is also formed on the first main surface21of the semiconductor substrate20.

Next, the semiconductor substrate20is thermally annealed at 900° C. or more and 1000° C. or less in nitrogen atmosphere. Further, by setting heating temperature to 600° C. or more and 700° C. or less at an optional temperature decreasing speed in the nitrogen atmosphere and performing low-temperature thermal annealing, as illustrated inFIG.25, impurities in the doped polysilicon layer65are diffused to the second main surface22side of the n− drift layer7, and a gettering layer55having a crystal defect and an impurity is formed on the second main surface22side of the n− drift layer7. After the above, an annealing process is performed to capture a metal impurity, a contaminating atom, and damage of the n− drift layer7by the gettering layer55. By the above, carrier lifetime of the n− drift layer7decreased during the wafer process to that point is recovered, and a value equal to or more than it determined by Equation (4) is realized. The present process can also be employed in an IGBT or a reverse conductivity (RC)-IGBT in addition to an RFC diode.

Here, tN−represents thickness (m) of the n− drift layer7. τtrepresents carrier lifetime (sec) in the n− drift layer7in which influence of carrier lifetime on on-voltage is eliminated.

On-voltage of the RFC diode1001depends on carrier lifetime of the n− drift layer7. Equation (4) represents carrier lifetime τt(s) that minimizes dependency of on-voltage of the RFC diode1001on carrier lifetime of the n− drift layer7. If the carrier lifetime τtrepresented by Equation (4) can be realized, influence of carrier lifetime on switching loss can be minimized, and it is effective for reducing off-loss or suppressing thermal runaway.

After the above, as illustrated inFIG.26, the doped polysilicon layer64formed on the first main surface21side of the semiconductor substrate20is selectively removed using liquid of hydrofluoric acid or mixed acid (for example, mixed solution of hydrofluoric acid/nitric acid/acetic acid).

Next, as illustrated inFIG.27, a contact hole for exposing the p layer52, the p anode layer6, and the n+ layer56is formed on the first main surface21of the semiconductor substrate20. That is, the TEOS layer63is processed as illustrated inFIG.27. After the above, an aluminum wiring5A to which Si is added to about 1% or more and 3% or less is formed by a sputtering method. The aluminum wiring5A corresponds to the first metal layer5in.FIG.3.

Subsequently, as illustrated inFIG.28, passivation films46and47are formed on the first main surface21side of the semiconductor substrate20.

After the above, as illustrated inFIG.29, a surface protective film23is formed on the first main surface21side of the semiconductor substrate20. Then, the gettering layer55and the doped polysilicon layer65formed on the second main surface22of the semiconductor substrate20are removed by polishing or etching. Through this removal process, thickness tD of the semiconductor substrate20corresponds to a withstand voltage class of the semiconductor device.

Then, as illustrated inFIG.30, the n buffer layer8is formed on the lower surface side of the n− drift layer7. After the above, the first p cathode layer101and the second p cathode layer102are formed on a lower surface of the n buffer layer8. Subsequently, in the active cell region R1, a conductivity type of a part of the first p cathode layer101and the second p cathode layer102is inverted to form the first n+ cathode layer91and the second n+ cathode layer92. The n buffer layer8, the first p cathode layer101, the second p cathode layer102, the first n+ cathode layer91, and the second n+ cathode layer92are diffusion layers formed by ion implantation and annealing.

Note that, when a diffusion layer is formed, the aluminum wiring5A and the passivation films46and47are present on the first main surface21side of the semiconductor substrate20. For this reason, annealing for forming a diffusion layer is performed using a laser having a temperature gradient in a device depth direction so that the first main surface21side of the semiconductor substrate20has temperature lower than a melting point 660° C. of aluminum used for the aluminum wiring5A, and having a wavelength at which heat is not transmitted to the first main surface21side.

FIG.31is a flowchart illustrating a manufacturing process inFIGS.29and30.

First, in Step S101, the surface protective film23is formed on the first main surface21side of the semiconductor substrate20. Next, in Steps S102and S103, the gettering layer55and the doped polysilicon layer65formed on the second main surface22of the semiconductor substrate20are removed by polishing and etching. Through this removal process, the thickness tD of the semiconductor substrate20corresponds to a withstand voltage class of the semiconductor device.

Next, in Step S104, ion implantation for forming the n buffer layer8is performed. This ion implantation is also referred to as first ion implantation. Next, in Step S105, annealing for activating an ion implanted in Step S104is performed. The annealing in Step S105is also referred to as first annealing.

After the above, in Step S106, ion implantation for forming the second p cathode layer102is performed. This ion implantation is also referred to as second ion implantation.

Next, in Step S107, ion implantation for forming the first p cathode layer101is performed. This ion implantation is also referred to as third ion implantation. Acceleration energy in the second ion implantation and the third ion implantation is determined so that a range satisfies Equation (1). By the above, the first p cathode layer101and the second p cathode layer102are formed so as not to interfere with each other.

Next, in Step S108, a mask for partially forming the first n+ cathode layer91and the second n+ cathode layer92is formed in the active cell region R1by a photomechanical process.

After the above, in Step S109, ion implantation for forming the second n+ cathode layer92is performed. This ion implantation is also referred to as fourth ion implantation.

Subsequently, in Step S110, ion implantation for forming the first n+ cathode layer91is performed. This ion implantation is also referred to as fifth ion implantation. Acceleration energy in the fourth ion implantation and the fifth ion implantation is determined so that a range satisfies Equation (1). By the above, the first n+ cathode layer91and the second n+ cathode layer92are formed so as not to interfere with each other.

Next, in Step S111, a resist for the photomechanical process is removed.

After the above, in Step S112, annealing for activating the ions implanted in Steps S106, S107, S109, and S110is performed. By this annealing, the first p cathode layer101, the second p cathode layer102, the first n+ cathode layer91, and the second n+ cathode layer92are formed. The annealing in Step S112is also referred to as second annealing. The first annealing and the second annealing are performed by laser annealing or in a diffusion furnace at a low temperature equal to or less than a metal melting point of the first metal layer5. A characteristic of the annealing employed here is to reproduce an impurity profile during ion implantation even after activation after annealing.

After the above, in Step S113, the surface protective film23is removed. Next, in Step S114, the second main surface22is applied with light etching.

After the above, in Step S115, the second metal layer11is formed on the second main surface22by a sputtering method. The second metal layer11is a laminated film including a plurality of metal films, and is, for example, a laminated film of metal in contact with Si, Ti, Ni, and Au. By using a monosilicide layer of AlSi, NISi, or the like to which Si is added by about 1% or more and about 3% or less as a metal layer in contact with Si, an effect of the cathode layer characteristic of the RFC diode1001is guaranteed.

Next, annealing at 350° C. is performed in Step S116to form an alloy layer or a silicide layer at an interface between the first p cathode layer101and the second metal layer11and between the first n+ cathode layer91and the second metal layer11. The annealing in Step S116is also referred to as third annealing.

According to the method for manufacturing RFC diode1001described in the fourth preferred embodiment, the first metal layer5and the surface protective film23are formed on the first main surface21of the semiconductor substrate20having the n− drift layer7, thickness of the semiconductor substrate20is controlled to desired thickness after formation of the surface protective film23, first ion implantation and first annealing for forming the n buffer layer8on the second main surface22of the semiconductor substrate are performed after thickness control of the semiconductor substrate20, second ion implantation for forming the second p cathode layer102that is a second diffusion layer of a second conductivity type on the second main surface22of the semiconductor substrate is performed after the first annealing, and third ion implantation for forming the first p cathode layer101that is a first diffusion layer of a second conductivity type on the second main surface of the semiconductor substrate20is performed with acceleration energy smaller than that of the second ion implantation after the second ion implantation, fourth ion implantation for forming the second n+ cathode layer92, which is a second cathode layer of a first conductivity type on the second main surface22of the semiconductor substrate20after the third ion implantation, fifth ion implantation for forming the first n+ cathode layer91, which is a first cathode layer of a first conductivity type, on the second main surface22of the semiconductor substrate20is performed with acceleration energy smaller than that of the fourth ion implantation after the fourth ion implantation, second annealing for activating ions implanted by the second, third, fourth, and fifth ion implantation is performed after the fifth ion implantation so that the second p cathode layer102, the first p cathode layer101, the second cathode layer92, and the first n+ cathode layer91, the second metal layer11is formed on the second main surface22of the semiconductor substrate20after the second annealing, and third annealing is performed at 350° C. in nitrogen atmosphere after formation of the second metal layer11. By the above, the first p cathode layer101and the second p cathode layer102, and the first n+ cathode layer91and the first n+ cathode layer92having different roles can be formed so as to satisfy relationships of Equations (1), (2), and (3), and the trade-off characteristic between the on-voltage VFand the switching loss ERECis controlled to the high-speed side regardless of a conventional life time control method, and reduction of off-loss, improvement in breakdown resistance, and thermal stability are realized.

E. Fifth Preferred Embodiment

In a fifth preferred embodiment, a method for manufacturing the RFC diode1003according to the third preferred embodiment will be described.FIG.32is a flowchart illustrating a process of and after the forming process of the surface protective film23in the method for manufacturing the RFC diode1003.

Steps S101to103inFIG.32are similar to those inFIG.31. After Step S103, ions for forming the first n buffer layer81are implanted in Step S104A. This ion implantation is also referred to as first ion implantation.

After Step S104A, annealing for activating the ions implanted in Step S104A is performed in Step S105A. This annealing is also referred to as first annealing. The first n buffer layer81is formed by the first annealing. The first annealing for forming the first n buffer layer81needs to be higher in temperature than fourth annealing for forming the second n buffer layer82described later.

After Step S105A, in Step S105B, ion implantation for forming the second n buffer layer82is performed. This ion implantation is also referred to as second ion implantation.

Steps S106to S113after Step S105B is similar to those inFIG.31. Note that ion implantation for forming the second p cathode layer102in Step S106is referred to as third ion implantation. Further, ion implantation for forming the first p cathode layer101in Step S107is referred to as fourth ion implantation. Further, ion implantation for forming the second n+ cathode layer92in Step S109is referred to as fifth ion implantation. Further, ion implantation for forming the first n+ cathode layer91in Step S110is referred to as sixth ion implantation.

The second annealing in Step S112forms the second n buffer layer82, the second p cathode layer102, the first p cathode layer101, the second n+ cathode layer92, and the first n+ cathode layer91. In the present process, formation order of the first n buffer layer81and the second n buffer layer82is important. Further, setting of acceleration energy is important in ion implantation for forming the second n buffer layer82.

After Step S113, the fourth annealing is performed in Step S113A. According toFIG.20, annealing temperature in the fourth annealing process for setting the trap B as a main trap is higher than third annealing temperature and 370° C. or lower. By the fourth annealing, in the second n buffer layer82, the trap B that is an interstitial Si pair is controlled to be a main trap.

Steps S114to S116after Step S113A is similar to those inFIG.31. By the above, the RFC diode1003according to the third preferred embodiment is manufactured.

As an ion species for forming the first n buffer layer81, phosphorus, arsenic, selenium, sulfur, or a proton (H+) is used. A proton or helium is used as an ion species for forming the second n buffer layer82. A proton or helium can be introduced into Si by an irradiation technique using a cyclotron other than ion implantation.

In a case where a proton is used as an ion species for forming the first n buffer layer81, when a proton is introduced into Si, a vacancy (v) generated at the time of introduction reacts with an impurity in Si to form a composite defect. Since the composite defect contains hydrogen, the composite defect serves as an electron supply source. Donor concentration increases due to increase in composite defect density by annealing, and donor concentration increases due to a mechanism that promotes a thermal donor conversion phenomenon caused by ion implantation/irradiation process. As a result, an n layer converted to a donor having impurity concentration higher than that of the n− drift layer7is formed as the first n buffer layer81, which contributes to operation of a device.

On the other hand, composite defects formed when a proton is introduced into Si include a defect serving as a lifetime killer that reduces lifetime of a carrier. When a proton is used as an ion species for forming the first n buffer layer81, the first annealing for forming the first n buffer layer81needs to be performed at higher temperature (375° C. or more and 425° C. or less, nitrogen atmosphere, 90 minutes or more) than the fourth annealing for forming the second n buffer layer82in consideration of removal of a defect that serves as a lifetime killer and stability of a profile in the first n buffer layer81.

According to the method for manufacturing the RFC diode1003described in the fifth preferred embodiment, the first metal layer5and the surface protective film23are formed on the first main surface21of the semiconductor substrate20having the n− drift layer7, thickness of the semiconductor substrate20is controlled to desired thickness after formation of the surface protective film23, first ion implantation and first annealing for forming the first n buffer layer81on the second main surface22of the semiconductor substrate20are performed after control of thickness of the semiconductor substrate20, second ion implantation for forming the second n buffer layer82on the second main surface22of the semiconductor substrate20is performed after the first annealing, third ion implantation for forming the second p cathode layer102on the second main surface22of the semiconductor substrate20is performed after the second ion implantation, fourth ion implantation for forming the first p cathode layer101on the second main surface22of the semiconductor substrate20is performed with acceleration energy smaller than that of the third ion implantation after the third ion implantation, fifth ion implantation for forming the second n+ cathode layer92on the second main surface22of the semiconductor substrate is performed after the fourth ion implantation, sixth ion implantation for forming the first n+ cathode layer91on the second main surface22of the semiconductor substrate20is performed with acceleration energy smaller than that of the fifth ion implantation after the fifth ion implantation, second annealing for activating ions implanted by the second, third, fourth, fifth, and sixth ion implantation is performed after the sixth ion implantation so that the second n buffer layer82, the second p cathode layer102, the first p cathode layer101, the second n+ cathode layer92, and the first n+ cathode layer91are formed, third annealing is performed in nitrogen atmosphere, the second metal layer11is formed on the second main surface22of the semiconductor substrate20after the third annealing, and fourth annealing is performed at 350° C. in nitrogen atmosphere after the second metal layer11is formed. By the above, since the first n buffer layer81and the second n buffer layer82in which the trap B of an interstitial Si pair is a main trap component are formed, the trade-off characteristic between the on-voltage VFand the switching loss ERECis controlled to the high-speed side regardless of a conventional lifetime control method, and reduction of off-loss, improvement of breakdown resistance, and thermal stability are realized.

F. Sixth Preferred Embodiment

FIGS.33and34illustrate a cross-sectional configuration of a pin diode, which is an example of the power semiconductor device, taken along line A1-A1′ inFIG.1.FIG.33is a cross-sectional view of a conventional pin diode1010, andFIG.34is a cross-sectional view of a pin diode1011according to a sixth preferred embodiment. In the diagrams, the conventional pin diode1010may be referred to as Con. pin diode, and the pin diode1011according to the sixth preferred embodiment may be referred to as New pin diode1.

The conventional pin diode1010illustrated inFIG.33is similar to a left-half configuration including the pin diode region31of the conventional RFC diode1000illustrated inFIG.2. The pin diode1011of the sixth preferred embodiment illustrated inFIG.34has a similar configuration to a left-half including the pin diode region31of the RFC diode1001according to the first preferred embodiment illustrated inFIG.3. A parameter of each layer of the pin diodes1010and1011, which are not specifically mentioned below, are similar to those in the RFC diodes1000and1001.

The n− drift layer7is formed using a Si wafer having impurity concentration Cn−of 1.0×1012atoms/cm3or more and 1.0×1015atoms/cm3or less.

The p anode layer6, the n buffer layer8, the first n+ cathode layer91, and the second n+ cathode layer92are the same as those in the first preferred embodiment.

FIG.35is a cross-sectional view of a pin diode1012according to a variation of the sixth preferred embodiment taken along line A1-A1∝ ofFIG.1; Compared with the pin diode1011, the pin diode1012includes a third n+ cathode layer93instead of the first n+ cathode layer91. In the third n+ cathode layer93, there are the traps A and B that can be detected by the PL method described inFIG.5.

FIG.36illustrates a trade-off characteristic between the on-voltage VFand the switching loss ERECfor the conventional pin diode1010and the pin diodes1011and1012according to the sixth preferred embodiment and the variation of the sixth preferred embodiment. A trade-off characteristic controlled by an electron beam is illustrated for the conventional pin diode1010.

FromFIG.36, it can be seen that the pin diodes1011and1012according to the sixth preferred embodiment and the variation of the sixth preferred embodiment realize the high-speed side of a trade-off characteristic similar to that of the conventional pin diode1010controlled by an electron beam. This is because the pin diodes1011and1012according to the sixth preferred embodiment and the variation of the sixth preferred embodiment include the first n+ cathode layer91or the third n+ cathode layer93having the trap B similarly to the RFC diode1001according to the first preferred embodiment.

Hereinafter, a portion of the method for manufacturing the pin diode1011different from the method for manufacturing the RFC diode1001according to the first preferred embodiment will be described.FIG.37is a flowchart illustrating a process of and after a forming process of the surface protective film23in the method for manufacturing the pin diode1011. The flowchart ofFIG.37is obtained by deleting Steps S106to S108and Step S111relating to formation of the first p cathode layer101and the second p cathode layer102and the photomechanical process in the flowchart relating to the method for manufacturing the RFC diode1001illustrated inFIG.31.

Since the pin diode1011according to the sixth preferred embodiment includes the first n+ cathode layer91and the second n+ cathode layer92similar to those of the RFC diode1001according to the first preferred embodiment, the trade-off characteristic between the on-voltage VFand the switching loss ERECis controlled to the high-speed side regardless of a conventional lifetime control method, and low off-loss, improved breakdown resistance, and thermal stability are realized.

The pin diode1012according to the variation of the sixth preferred embodiment also includes the third n+ cathode layer93having the traps A and B similarly to the second n+ cathode layer92instead of the second n+ cathode layer92, and thus has a similar effect to the pin diode1011.

As described above, even in the case of the pin diode, it is possible to suppress influence of an impurity defect due to the Si material.

G. Seventh Preferred Embodiment

FIG.38is a cross-sectional view of an RC-IGBT1021, which is the power semiconductor device according to a seventh preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1021has a cathode structure similar to that of the RC-IGBT1001according to the first preferred embodiment.

As illustrated inFIG.38, the RC-IGBT1021includes the semiconductor substrate20, the first metal layer5, and the second metal layer11. The semiconductor substrate20has the first main surface21and the second main surface22facing each other. The first metal layer5is formed on the first main surface21of the semiconductor substrate20, and the second metal layer11is formed on the second main surface22of the semiconductor substrate20.

Further, the RC-IGBT1021is divided into an IGBT region33that operates as an IGBT in plan view and a diode region34that operates as a diode.

The semiconductor substrate20includes the n− drift layer7, an n layer26, a p base layer6A, an n+ emitter layer24, and a p+ layer25. The n layer26is formed on the first main surface21side of the n− drift layer7. The p base layer6A is formed on the first main surface21side of the n layer26. The n+ emitter layer24is formed on the first main surface21side of the p base layer6A in the IGBT region33. The p+ layer25is formed on the first main surface21side of the p base layer6A in the diode region34.

In the IGBT region33, a trench41penetrating the n+ emitter layer24, the p base layer6A, and the n layer26from the first main surface21of the semiconductor substrate is formed. A gate electrode43is embedded in the trench41via a gate insulating film42. An interlayer insulating film29for insulating the gate electrode43from the first metal layer5is formed on the gate electrode43.

In the diode region34, a trench44penetrating the p+ layer25, the p base layer6A, and the n layer26from the first main surface21of the semiconductor substrate20is formed. A dummy gate electrode45is embedded in the trench44via the gate insulating film42. Unlike the trench41, an internal electrode of the trench44serves as the dummy gate electrode45because the internal electrode is in contact with the emitter electrode5and has the same potential.

Furthermore, the semiconductor substrate20includes the n buffer layer8, the n+ cathode layer90, and a p collector layer100A. The n buffer layer8is formed on the second main surface22side of the n− drift layer7.

The n+ cathode layer90is formed in the diode region34and has a two-layer structure including the first n+ cathode layer91and the second n+ cathode layer92. The second n+ cathode layer92is formed between the n buffer layer8and the second main surface22so as to be in contact with the n buffer layer8. The first n+ cathode layer91is formed between and in contact with the second n+ cathode layer92and the second metal layer11. A lower surface of the first n+ cathode layer91constitutes the second main surface of the semiconductor substrate20.

The p collector layer100A is formed in the IGBT region33and has a two-layer structure including a first p collector layer101A and a second p collector layer102A. The second p collector layer102A is formed between the n buffer layer8and the second main surface22so as to be in contact with the n buffer layer8. The first p collector layer101A is formed between and in contact with the second p collector layer102A and the second metal layer11. A lower surface of the first p collector layer101A constitutes the second main surface of the semiconductor substrate20.

A parameter of each layer of the RC-IGBT1021, which is not particularly mentioned below, is similar to the parameter of each corresponding layer in the first preferred embodiment. The n− drift layer7, the n buffer layer8, the first n+ cathode layer91, and the second n+ cathode layer92are similar to those in the first preferred embodiment.

Peak impurity concentration of the p base layer6A is 1.0×1016atoms/cm3or more and 1.0×1018atoms/cm3or less. A joining depth of the p base layer6A is more than that of the n+ emitter layer24and less than that of the n layer26.

Peak impurity concentration of the n layer26is 1.0×1015atoms/cm3or more and 1.0×1017atoms/cm3or less. A joining depth of the n layer26is set to be more than that of the p base layer6A by about 0.5 μm or more and 1.0 μm or less.

Peak impurity concentration of the n+ emitter layer24is 1.0×1018atoms/cm3or more and 1.0×1021atoms/cm3or less. A joining depth of the n+ emitter layer24is 0.2 μm or more and 1.0 μm or less.

Impurity concentration on a surface of the p+ layer25in contact with the first metal layer5, that is, the first main surface21is 1.0×1018atoms/cm3or more and 1.0×1021atoms/cm3or less. A joining depth of the p+ layer25is equal to or more than the joining depth of the n+ emitter layer24.

A depth of the trenches41and44, that is, a trench depth Dtrenchis more than that of the n layer26.

The first p collector layer101A has impurity concentration of 1.0×1017atoms/cm3or more and 1.0×1018atoms/cm3or less on a surface in contact with the second metal layer11, that is, on the second main surface22, and has a depth of 0.1 μm or more and 0.2 μm or less.

The second p collector layer102A has peak impurity concentration of 1.0×1016atoms/cm3or more and 1.0×1020atoms/cm3or less and depth of 0.3 μm or more and 0.5 μm or less.

Here, the first n+ cathode layer91and the second n+ cathode layer92, and the first p collector layer101A and the second p collector layer102A satisfy relationships of Equations (1), (2), and (3). However, in Equation (1), Rp1is read as a range (m) of the first p collector layer101A, and Rp2is read as a range (m) of the second p collector layer102A. Further, in Equation (3), Dp2is read as the number of atoms (atoms/cm2) per unit area of the second p collector layer102A.

FIG.39is a cross-sectional view of an RC-IGBT1022, which is the power semiconductor device according to a first variation of the seventh preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1022is different from the RC-IGBT1021of the seventh preferred embodiment only in that the p cathode layer100is provided in a part of the diode region34. That is, in the RC-IGBT1022, the p cathode layer100which is a diffusion layer of a second conductivity type is provided in contact with the n buffer layer8and the second metal layer11even in a part of the diode region34. In the RC-IGBT1022, the p cathode layer100has a two-layer structure including the first p cathode layer101and the second p cathode layer102.

The second p cathode layer102is formed between the n buffer layer8and the second main surface22so as to be in contact with the n buffer layer8. The first p cathode layer101is formed between and in contact with the second p cathode layer102and the second metal layer11. A lower surface of the first p cathode layer101constitutes the second main surface of the semiconductor substrate20.

Parameters such as impurity concentration and a depth of the first p cathode layer101and the second p cathode layer102in the diode region34are similar to those of the first p collector layer101A and the second p collector layer102A in the IGBT region33.

FIG.40is a cross-sectional view of an RC-IGBT1023, which is the power semiconductor device according to a second variation of the seventh preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1023is different from the RC-IGBT1022according to the first variation of the seventh preferred embodiment only in that the p collector layer100A is composed of one layer of the second p collector layer102A in the IGBT region33, and the p cathode layer100is composed of one layer of the second p cathode layer102in the diode region34.

In the second p collector layer102A and the second p cathode layer102in the RC-IGBT1023, impurity concentration on the second main surface22is 1.0×1017atoms/cm3or more and 1.0×1019atoms/cm3or less, and a depth is 0.3 μm or more and 0.5 μm or less.

In the RC-IGBTs1021,1022, and1023according to the seventh preferred embodiment and the first and second variations of the seventh preferred embodiment, similarly to the method for manufacturing the RFC diode1001described in the fourth preferred embodiment, a collector structure in the IGBT region33and a cathode structure in the diode region34are configured to satisfy relationships of Equations (1), (2), and (3). Therefore, also, in the RC-IGBTs1021,1022, and1023, the trade-off characteristic between the on-voltage VFand the switching loss ERECis controlled to the high-speed side regardless of a conventional lifetime control method, and low off-loss, improvement in breakdown resistance, and thermal stability are realized.

H. Eighth Preferred Embodiment

FIG.41is a cross-sectional view of an RC-IGBT1024, which is the power semiconductor device according to an eighth preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1024is different from the RC-IGBT1021according to the seventh preferred embodiment only in that the p+ layer25is not provided in the diode region34. That is, in the RC-IGBT1024, the p base layer6A is in contact with the first metal layer5in the diode region34.

Each diffusion layer and a trench of the RC-IGBT1024are set so as to have parameters below.

For the p base layer6A in the IGBT region33, parameters are as described below. Peak impurity concentration is 1.0×1016atoms/cm3or more and 1.0×1018atoms/cm3or less. A joining depth is more than that of the n+ emitter layer24and less than that of the n layer26.

For the p base layer6A in the diode region34, parameters are as described below. Impurity concentration on a surface of the p base layer6A in contact with the first metal layer5, that is, the first main surface21is 1.0×1016atoms/cm3or more. Peak impurity concentration is 2.0×1016atoms/cm3or more and 1.0×1018atoms/cm3or less. A joining depth is more than that of the n+ emitter layer24and less than that of the n layer26.

Other than the above, parameters regarding the n layer26, the n+ emitter layer24, the trench depth, the n buffer layer8, the first n+ cathode layer91, the second n+ cathode layer92, the first p collector layer101A, and the second p collector layer102A are similar to those in the seventh preferred embodiment.

FIG.42is a cross-sectional view of an RC-IGBT1025, which is the power semiconductor device according to a first variation of the eighth preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1025is different from the RC-IGBT1021of the seventh preferred embodiment only in that the p cathode layer100is provided in a part of the diode region34. In the RC-IGBT1022, the p cathode layer100has a two-layer structure including the first p cathode layer101and the second p cathode layer102.

The second p cathode layer102is formed between the n buffer layer8and the second main surface22so as to be in contact with the n buffer layer8. The first p cathode layer101is formed between and in contact with the second p cathode layer102and the second metal layer11. A lower surface of the first p cathode layer101constitutes the second main surface of the semiconductor substrate20.

Parameters such as impurity concentration and a depth of the first p cathode layer101and the second p cathode layer102in the diode region34are similar to those of the first p collector layer101A and the second p collector layer102A in the IGBT region33.

FIG.43is a cross-sectional view of an RC-IGBT1026, which is the power semiconductor device according to a second variation of the eighth preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1026is different from the RC-IGBT1025according to the first variation of the eighth preferred embodiment only in that the p collector layer100A is composed of one layer of the second p collector layer102A in the IGBT region33, and the p cathode layer100is composed of one layer of the second p cathode layer102in the diode region34.

In the second p collector layer102A and the second p cathode layer102in the RC-IGBT1026, surface impurity concentration on the second main surface22is 1.0×1017atoms/cm3or more and 1.0×1019atoms/cm3or less, and a depth is 0.3 μm or more and 0.5 or less.

In the RC-IGBTs1024,1025, and1026according to the eighth preferred embodiment and the first and second variations of the eighth preferred embodiment, similarly to the method for manufacturing the RFC diode1001described in the fourth preferred embodiment, a collector structure in the IGBT region33and a cathode structure in the diode region34are configured to satisfy relationships of Equations (1), (2), and (3). Therefore, also in the RC-IGBTs1024,1025, and1026, the trade-off characteristic between the on-voltage VFand the switching loss ERECcan be controlled to the high-speed side regardless of a conventional lifetime control method, and low off-loss, improvement in breakdown resistance, and thermal stability can be realized.

Further, since the p+ layer25is not provided, the diode region34of the RC-IGBTs1024,1025, and1026can achieve the same performance as the pin diode region31of the RFC diode1001according to the first preferred embodiment illustrated inFIG.3and the pin diode1011according to the sixth preferred embodiment illustrated inFIG.34.

I. Ninth Preferred Embodiment

FIG.44is a cross-sectional view of an RC-IGBT1027, which is the power semiconductor device according to a ninth preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1027is different from the RC-IGBT1021of the seventh preferred embodiment only in that the n buffer layer80has a two-layer structure of the first n buffer layer81and the second n buffer layer82as in the RFC diode1003according to the third embodiment.

Parameters of the first n buffer layer81and the second n buffer layer82are similar to those in the RFC diode1003according to the third preferred embodiment.

FIG.45is a cross-sectional view of an RC-IGBT1028, which is the power semiconductor device according to a first variation of the ninth preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1028is different from the RC-IGBT1027of the ninth preferred embodiment only in that the p cathode layer100is provided in a part of the diode region34. In the RC-IGBT1028, the p cathode layer100has a two-layer structure including the first p cathode layer101and the second p cathode layer102.

The second p cathode layer102is formed between the n buffer layer8and the second main surface22so as to be in contact with the n buffer layer8. The first p cathode layer101is formed between and in contact with the second p cathode layer102and the second metal layer11. A lower surface of the first p cathode layer101constitutes the second main surface of the semiconductor substrate20.

Parameters such as impurity concentration and a depth of the first p cathode layer101and the second p cathode layer102in the diode region34are similar to those of the first p collector layer101A and the second p collector layer102A in the IGBT region33.

FIG.46is a cross-sectional view of an RC-IGBT1029, which is the power semiconductor device according to a second variation of the ninth preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1029is different from the RC-IGBT1028according to the first variation of the ninth preferred embodiment only in that the p collector layer100A is composed of one layer of the second p collector layer102A in the IGBT region33, and the p cathode layer100is composed of one layer of the second p cathode layer102in the diode region34.

In the second p collector layer102A and the second p cathode layer102in the RC-IGBT1029, surface impurity concentration on the second main surface22is 1.0×1017atoms/cm3or more and 1.0×1019atoms/cm3or less, and a depth is 0.3 μm or more and 0.5 μm or less.

The RC-IGBTs1027,1028, and1029according to the ninth preferred embodiment and the first and second variations of the ninth preferred embodiment include the first n buffer layer81and the second n buffer layer82similar to the RFC diode1003according to the third preferred embodiment. In the second n buffer layer82, the trap B by an interstitial Si pair is a main trap component. Therefore, according to the RC-IGBTs1027,1028, and1029, as similar to the RFC diode1003, a trade-off characteristic between the on-voltage VFand the switching loss ERECis controlled to the high-speed side regardless of a conventional lifetime control method, and low off-loss, improvement in breakdown resistance, and thermal stability are realized.

FIG.47is a cross-sectional view of an RC-IGBT1030, which is the power semiconductor device according to a tenth preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1030is different from the RC-IGBT1027according to the ninth preferred embodiment only in that the p+ layer25is not provided in the diode region34. That is, in the RC-IGBT1030, the p base layer6A is in contact with the first metal layer5in the diode region34.

Parameters regarding each diffusion layer and a trench of the RC-IGBT1030are as described below. The p base layer6A in the IGBT region33and the diode region34is similar to that of the eighth preferred embodiment. The n layer26, the n+ emitter layer24, the trench depth Dtrench, the first n buffer layer81, the second n buffer layer82, the first n+ cathode layer91, the second n+ cathode layer92, the first p collector layer101A, and the second p collector layer102A are similar to those in the ninth preferred embodiment.

FIG.48is a cross-sectional view of an RC-IGBT1031, which is the power semiconductor device according to a first variation of the tenth preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1031is different from the RC-IGBT1030of the tenth preferred embodiment only in that the p cathode layer100is provided in a part of the diode region34. In the RC-IGBT1030, the p cathode layer100has a two-layer structure including the first p cathode layer101and the second p cathode layer102.

The second p cathode layer102is formed between the n buffer layer8and the second main surface22so as to be in contact with the n buffer layer8. The first p cathode layer101is formed between and in contact with the second p cathode layer102and the second metal layer11. A lower surface of the first p cathode layer101constitutes the second main surface of the semiconductor substrate20.

Parameters such as impurity concentration and a depth of the first p cathode layer101and the second p cathode layer102in the diode region34are similar to those of the first p collector layer101A and the second p collector layer102A in the IGBT region33.

FIG.49is a cross-sectional view of an RC-IGBT1032, which is the power semiconductor device according to a second variation of the tenth preferred embodiment, taken along line A-A′ ofFIG.1. The RC-IGBT1032is different from the RC-IGBT1031according to the first variation of the tenth preferred embodiment only in that the p collector layer100A is composed of one layer of the second p collector layer102A in the IGBT region33, and the p cathode layer100is composed of one layer of the second p cathode layer102in the diode region34.

In the second p collector layer102A and the second p cathode layer102in the RC-IGBT1031, impurity concentration on the second main surface22is 1.0×1017atoms/cm3or more and 1.0×1019atoms/cm3or less, and a depth is 0.3 μm or more and 0.5 μm or less.

The RC-IGBTs1030,1031, and1032according to the tenth preferred embodiment and the first and second variations of the tenth preferred embodiment include the first n buffer layer81and the second n buffer layer82similar to the RFC diode1003according to the third preferred embodiment. In the second n buffer layer82, the trap B by an interstitial Si pair is a main trap component. Therefore, according to the RC-IGBTs1027,1028, and1029, as similar to the RFC diode1003, a trade-off characteristic between the on-voltage VFand the switching loss ERECis controlled to the high-speed side regardless of a conventional lifetime control method, and low off-loss, improvement in breakdown resistance, and thermal stability are realized.

Further, since the p+ layer25is not provided, the diode region34of the RC-IGBTs1030,1031, and1032can achieve the same performance as the pin diode region31of the RFC diode1001according to the first preferred embodiment illustrated inFIG.3and the pin diode1011according to the sixth preferred embodiment illustrated inFIG.34.

FIG.50is a cross-sectional view of an IGBT1033, which is the power semiconductor device according to an eleventh preferred embodiment, taken along line A-A′ ofFIG.1. The IGBT1033has a trench gate structure.

The IGBT1033is similar in configuration to the IGBT region33of the RC-IGBT1027according to the ninth preferred embodiment.

The n− drift layer7in the IGBT1033is similar to the n− drift layer7in the RC-IGBT1027according to the ninth preferred embodiment.

In the IGBT1033, a part of the gate electrode43in the trench41has the same potential as the first metal layer5which is the emitter potential. By the above, saturation current density of the IGBT is suppressed. Further, by controlling a capacitance characteristic, oscillation in a no-load short-circuit state is suppressed. As a result, short circuit tolerance is improved, and lower ON voltage is realized by improving carrier concentration on the emitter side.

The p base layer6A, the n layer26, the n+ emitter layer24, the p+ layer25, the first n buffer layer81, the second n buffer layer82, the first p collector layer101A, the second p collector layer102A, and the trench depth Dtrenchin the IGBT1033are similar to those in the RC-IGBT1027according to the ninth preferred embodiment.

The IGBT1033, which is the power semiconductor device according to the eleventh preferred embodiment, includes the semiconductor substrate20having the first main surface21and the second main surface22facing each other, the first metal layer5provided on the first main surface21of the semiconductor substrate20, and the second metal layer11provided on the second main surface22of the semiconductor substrate20. The semiconductor substrate20includes the n− drift layer7which is a drift layer of a first conductivity type, the n buffer layer8which is a buffer layer of a first conductivity type provided between the n− drift layer7and the second main surface22, and the p collector layer100A which is a collector layer of a second conductivity type provided between the n buffer layer8and the second main surface22. The n buffer layer8includes the first n buffer layer81which is a first buffer layer in contact with the second metal layer11and the second n buffer layer82which is a second buffer layer in contact with the n− drift layer7. A crystal defect in the second n buffer layer82is the trap B which is a second lattice defect and the trap C which is a third lattice defect detected by a photoluminescence method. As described above, the IGBT1033includes the first n buffer layer81and the second n buffer layer82similar to the RFC diode1003according to the third preferred embodiment. In the second n buffer layer82, the trap B by an interstitial Si pair is a main trap component. Therefore, according to the IGBT1033, as similar to the RFC diode1003, a trade-off characteristic between the on-voltage VFand the switching loss ERECis controlled to the high-speed side regardless of a conventional lifetime control method, and low off-loss, improvement in breakdown resistance, and thermal stability are realized.

Note that, preferred embodiments can be freely combined with each other, and each preferred embodiment can be appropriately modified or omitted.

While the disclosure has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised.