Dynamic In-Situ Adaptation of Data Interface

This application is directed to adapting an electronic device in a data communication channel. The electronic device includes a sequence of modulation circuits, and each modulation circuit has one or more adjustable configurations. The sequence of modulation circuits obtains an input data signal and processes the input data signal to generate an output data signal including a first data sample. The electronic device determines a first residual error of the first data sample and adjusts a first adjustable configuration of a first modulation circuit based on the first residual error. A second adjustable configuration of a second modulation circuit is further adjusted based on the first adjustable configuration. In some implementations, the electronic device determines a first configuration error of the first adjustable configuration based on the first residual error, and adjusts the second adjustable configuration based on the first configuration error.

TECHNICAL FIELD

The disclosed implementations relate generally to data transmission technology including, but not limited to, methods, systems, and devices for dynamically adapting modulation circuits of data interfaces in situ for different configurable settings in a high-speed data communication channel.

BACKGROUND

Many electronic devices are physically coupled to each other and communicate with each other using data links and interfaces that comply with high-speed serial computer expansion bus standards (e.g., Peripheral Component Interconnect (PCI) Express). These bus standards allow application of retimers and redrivers to extend a channel reach at a high data speed. A redriver is an analog extension device designed to boost portions of a signal to counteract attenuation caused by signal propagation over a physical interconnect of a corresponding data link. A retimer is a mixed-signal device that is standard-aware and has an ability to fully recover the data, extract the embedded clock, and retransmit a fresh copy of the data using a clean clock. Compared with the redriver, the retimer actively participates in applying the bus standard to implement negotiation, timeouts, bit manipulation, jitter resetting, signal equalization, skew correction, and many other functions. Multiple equalizers are oftentimes applied concurrently in the retimer, and however, can easily interfere with each other and lead to instability and non-convergence. Due to different principles of operation, different equalizers demonstrate different loop bandwidths and rates of convergence. Operating conditions also create additional constraints on an equalizer adaptation process. For example, certain data communication protocols require link training to be completed within a time period that is insufficiently long and limits a convergence rate of an adaptive equalizer. Additionally, configurability is often required for these equalizers due to different reasons (e.g., power saving). It would be beneficial to apply highly configurable and robust equalization mechanisms in a high speed data link or interface having a plethora of operating conditions.

SUMMARY

This application is directed to methods, electronic systems, electronic devices, electronic circuits, data links, data ports, and data interfaces that dynamically adapt modulation circuits of data interfaces in situ for different configurable settings in a high-speed data communication channel. High speed communication integrated circuits (ICs) in today's world are becoming increasingly more complex due to high data rates required by applications such as high resolution displays and high speed data transfer. Different types of equalizers have been developed to address various signal integrity issues that appear as data rates grow. A major source of data-dependent noise called inter-symbol interference (ISI) arises when data is transmitted across a transmission line, and leads to low signal-to-noise ratio (SNR) and high bit error rate (BER) unless adequate equalization is used. Example electronic devices applied for signal equalization include, but are not limited to, continuous-time linear equalizer (CTLE), decision feedback equalizer (DFE), and feed-forward equalizer (FFE). These equalizers are applied jointly with a variable gain amplifier (VGA) to improve the SNR. As such, settings of the CTLE, DFE, FFE and VGA are adjusted concurrently, dynamically, iteratively, and in situ according to different operating conditions (e.g., data rates, protocol standards, cable types, ambient temperatures).

In one aspect, a method is implemented at an electronic device for adapting a data communication channel. The method includes obtaining an input data signal by the electronic device including a sequence of modulation circuits. Each of the modulation circuits has one or more adjustable configurations. The method further includes processing the input data signal by the sequence of modulation circuits to generate an output data signal including a first data sample. The method further includes determining a first residual error of the first data sample, adjusting a first adjustable configuration of a first modulation circuit based on the first residual error, and adjusting a second adjustable configuration of a second modulation circuit based on the first adjustable configuration. In some implementations, the first adjustable configuration of the first modulation circuit and the second adjustable configuration of the second modulation circuit are adjusted dynamically, jointly, or iteratively.

In some implementations, adjusting the second adjustable configuration further includes determining a first configuration error of the first adjustable configuration. The second adjustable configuration is adjusted based on the first configuration error of the first adjustable configuration. Further, in some implementations, the method further includes applying a first scale factor to the first residual error and a second scale factor to the first configuration error and adjusting the first scale factor and the second scale factor to adjust the first adjustable configuration of the first modulation circuit and the second adjustable configuration of the second modulation circuit jointly or iteratively.

In another aspect, a non-transitory computer-readable storage medium stores one or more programs to be executed by one or more processors. The one or more programs include instructions for implementing any of the above methods for adapting an electronic device in a data interface or a data communication channel.

In yet another aspect, an electronic device includes a sequence of modulation circuits each of which has one or more adjustable configurations, an adaptive equalizer controller coupled to the sequence of modulation circuits, and memory storing one or more programs configured for execution by the adaptive equalizer controller and the sequence of modulation circuits. The one or more programs include instructions for implementing any of the above methods for adapting a data interface or a data communication channel.

In yet another aspect, an electronic device includes a sequence of modulation circuits and an adaptive equalizer controller. The sequence of modulation circuits is configured to obtain an input data signal and process the input data signal to generate an output data signal including a first data sample. Each modulation circuit has one or more adjustable configurations. The adaptive equalizer controller is coupled to the sequence of modulation circuits, and configured for determining a first residual error of the first data sample, adjusting a first adjustable configuration of a first modulation circuit based on the first residual error, and adjusting a second adjustable configuration of a second modulation circuit based on the first adjustable configuration.

These illustrative implementations are mentioned not to limit or define the disclosure, but to provide examples to aid understanding thereof. Additional implementations are discussed in the Detailed Description, and further description is provided there.

DESCRIPTION OF IMPLEMENTATIONS

FIG.1is a block diagram of an example electronic system100in which a first electronic device102is electrically coupled to a second electronic device104via a data link106, in accordance with some implementations. The first electronic device102and second electronic device104are configured to exchange data via the data link106. In an example, the first electronic device102includes a video source, and the second electronic device104includes a display device. The display device has a screen configured to display visual content provided by the first electronic device102via the data link106. In another example not shown, the first electronic device102includes a desktop computer, and the second electronic device104includes a mobile phone that exchanges data with the desktop computer via the data link106. Examples of the electronic devices102and104include, but are not limited to, a desktop computer, a laptop computer, a tablet computer, a video player, a camera device, a gameplayer device, or other formats of electronic devices which are configured to provide data or receive data. Video data, audio data, text, program data, control data, configuration data, or any other data are transmitted between the first and second electronic devices102and104via the data link106.

The data link106includes two connectors108at two of its ends. The two connectors108are configured to connect the data link106to respective connectors108of the first electronic device102and second electronic device104. For example, the connector108is a DisplayPort connector having a digital display interface developed by a consortium of personal computer and chip manufacturers and standardized by the Video Electronics Standards Association (VESA). The DisplayPort connector is configured to connect the data link106to the first electronic device102and carry video, audio, and control data according to a data communication protocol. In another example, the connector108is a universal serial bus (USB) connector, e.g., configured to connect a computer to a peripheral device. Exemplary types of the USB connector include, but are not limited to, USB-A, USB-B, USB-C. USB Micro-A, USB Micro-B, USB Mini-B, USB 3.0A, USB 3.0B, USB 3.0 Micro B, and USB Micro-AB. Further, a data communication protocol of USB4 is applied to communicate data using a USB-C connector, thereby providing a throughput of up to 40 Gbps, power delivery of up to 100 W, support for 4K and 5K displays, and backward compatibility with USB 3.2 and USB 2.

In some implementations, the connector108includes a bidirectional channel for communicating a stream of data between the first and second electronic device102and104. The bidirectional channel of the connector108includes two data lanes and a pair of differential pins110coupled to the two data lanes. The pair of differential pins110are configured to receive a differential input signal from the first electronic device102or the second electronic device104, and the differential input signal carries a serial data command or serial content data (e.g., video or audio data) that are communicated via the two data lanes of the connector108. As such, the two data lanes and pair of differential pins110of the connector108are configured to facilitate bidirectional communication between the first electronic device102and the second electronic device104. The bidirectional channel is a data channel or an auxiliary channel. Specifically, the auxiliary channel of the connector108is used for communication of additional serial data beyond video and audio data, such as consumer electronics control (CEC) commands. In some implementations, the pair of differential pins110is coupled to a dedicated set of twisted-pair wires configured to carry two input signals of the differential input signal.

Each connector108of the data link106is configured to be coupled to a respective connector108of the first electronic device102and a respective connector108of the second electronic device104. Each connector108of the data link106is bidirectional, so is each respective connector108of the electronic devices102and104. When the connector108of the data link106is coupled to the first or second electronic device102or104, the pair of differential pins110of the connector108of the data link106are physically and electrically coupled to a pair of differential pins110of the connector108of the first or second electronic device102or104. The pair of differential pins110of the connector108of the first or second electronic device102or104is configured to receive data from, or transmit data to, the differential pins110of the connector108of the data link106.

FIG.2is an example PCI Express electronic system100in which a first electronic device or component102is electrically coupled to a second electronic device or component104via a data link106, in accordance with some implementations. In an example, the first electronic device102includes a central processing unit (CPU) of a personal computer, and the second electronic device104is a peripheral component of the personal computer, such as a graphics card, a hard drive, a solid state drive, a Wi-Fi communication module, or an Ethernet card. The data link106includes a connection port for receiving from the second electronic device104. The connection port is optionally formed on a mother board of the personal computer. The data link106complies with PCI Express (i.e., PCIe), which is a high-speed serial computer expansion bus standard, and provides an interface to communicate data packets between the first and second electronic devices102and104in compliance with the PCI Express. The data link106is a serial data bus including one or more data transmission channels225. Each channel225includes two wire sets for transmitting and receiving data packets, thereby supporting full-duplex communication between the first and second electronic devices102and104. In some examples, the data link106has 1, 4, 8, or 16 channels225coupled in a single data port of the data link106. For each lane, the two wire sets correspond to a downstream data direction140or an upstream data direction150defined with respect to the first electronic device102. Optionally, each wire set includes two wires for carrying a pair of differential signals.

In some implementations, the first electronic device102includes or is coupled to a root complex device206that is further coupled to the data link106. The root complex device206is configured to generate requests for transactions including a series of one or more packet transmissions on behalf of the first electronic device102. Examples of the transactions include, but are not limited to, Memory Read, Memory Read Lock, IO Read, IO Write, Configuration Read, Configuration Write, and Message. In some implementations, the first electronic device102is coupled to one or more additional electronic devices besides the second electronic device104. The data link106includes one or more switch devices to couple the root complex device206of the first electronic device102to multiple endpoints including the second electronic device104and additional electronic devices not shown inFIG.1.

PCI Express is established based on a layered model including an application layer208, a transaction layer210, a data link layer212, and a physical layer214. As the top layer, the application layer208is implemented in software programs, such as Ethernet, NVMe, SOP, AHCI, and SATA. In the transaction layer210, each transaction of a series of packet transmissions is implemented as requests and responses separated by time. For example, a memory-related transaction is translated to device configuration and control data transferred to or from the second electronic device104(e.g., a memory device). Data packets associated with each transaction are managed by data flows on the data link layer212. The physical layer214of PCI Express controls link training and electrical (analog) signaling, and includes a logical block116and an electrical block118. The logic block116defines ordered data sets in training states (e.g., TS1and TS2), and the electrical block118defines eye diagram characteristics and analog waveforms. Each layer of the layered model includes first specifications for a transmitting end where a root complex device206is coupled and second specifications for a receiving end where a peripheral component (i.e., the second electronic device104) is coupled.

As high frequency signals are transmitted within the channels225of the data link106, these signals are distorted and spread over sequential symbols and result in inter symbol interferences (ISI) and bit errors at the receiving end of the second electronic device104. These ISI and bit errors can be suppressed by a feed-forward equalizer (FFE)340(FIG.3A) that is coupled serially on a path of the data link106and configured with equalization settings using an equalization procedure. In an example, the FFE340includes a finite impulse response (FIR) filter. The equalization procedure is implemented when a high speed data transfer rate needs to be initialized, when an equalization request is issued from the application layer208, or when a BER exceeds a data error tolerance. In some implementations, initiation and termination of the equalization procedure are detected on the physical layer214based on data packets transferred over the data link106.

FIG.3Ais a block diagram of an example electronic system100in which a first electronic device or component102is electrically coupled to a second electronic device or component104via a data link106, in accordance with some implementations, andFIG.3Bis a block diagram of an example data link106including a plurality of modulation circuits350, in accordance with some implementations. In an example, the first electronic device102includes a central processing unit (CPU) of a personal computer, and the second electronic device104is a peripheral component of the personal computer, such as a graphics card, a hard drive, a solid state drive, a Wi-Fi communication module, or an Ethernet card. The data link106includes a connection port for receiving data from the second electronic device104. The connection port is optionally formed on a mother board of the personal computer. In some implementations, the data link106complies with a high-speed serial computer expansion bus standard (e.g., PCI Express (PCIe), USB 4) and provides an interface to communicate data packets between the first and second electronic devices102and104in compliance with the bus standard. The data link106is a serial data bus including one or more data channels225. In some implementations, each data channel225includes two wire sets330A and330B (also called two data lanes) for transmitting and receiving data packets, respectively, thereby supporting full-duplex communication between the first and second electronic devices102and104. In some examples, the data link106has 1, 4, 8, or 16 channels coupled in a single data port of the data link106. For each data channel225, the two wire sets330A and330B correspond to a downstream data direction140and an upstream data direction150defined with respect to the first electronic device102, respectively. Optionally, each wire set330A or330B includes two respective wires332and334for carrying a pair of differential signals.

In some implementations, the first electronic device102includes or is coupled to a root complex device (not shown) that is further coupled to the data link106. The root complex device is configured to generate requests for transactions including a series of one or more packet transmissions on behalf of the first electronic device102. Examples of the transactions include, but are not limited to, Memory Read, Memory Read Lock, Input Output (IO) Read, IO Write, Configuration Read, Configuration Write, and Message. In some implementations, the first electronic device102is coupled to one or more additional electronic devices besides the second electronic device104. The data link106includes one or more switch devices to couple the root complex device of the first electronic device102to multiple endpoints including the second electronic device104and additional electronic devices not shown inFIGS.1and2.

A data transmission protocol (e.g., PCI Express, USB4 v2.0, DisplayPort 2.1) is established based on a layered model including an application layer208, a transaction layer210, a data link layer212, and a physical layer214. As the top layer, the application layer208is implemented in software programs, such as Ethernet, NVMe, SOP, AHCI, and SATA. In the transaction layer210, each transaction of a series of packet transmissions is implemented as requests and responses separated by time. For example, a memory-related transaction is translated to device configuration and control data transferred to or from the second electronic device104(e.g., a memory device). Data packets associated with each transaction are managed by data flows on the data link layer212. The physical layer214controls link training and electrical (analog) signaling, and includes a logical block and an electrical block. The logic block216defines ordered data sets in training states, and the electrical block218defines eye diagram characteristics and analog waveforms. Each layer of the layered model includes first specifications for a transmitting side where a root complex device is coupled and second specifications for a receiving side where a peripheral component (i.e., the second electronic device104) is coupled.

As signals are transmitted within the wire sets330of each data channel225of the data link106, the signals are distorted and spread over sequential symbols and result in inter symbol interferences (ISI) and bit errors at the receiving side of the second electronic device104. In some implementations, these ISI and bit errors can be suppressed by an FFE340that is coupled serially on a path of the data link106and configured with equalization settings using an equalization procedure. For example, an equalization procedure is implemented when a high speed data transfer rate needs to be initialized, when an equalization request is issued from the application layer, or when a BER exceeds a data error tolerance.

The electronic system100includes a serializer and deserializer (SERDES) system corresponding to the data link106. The SERDES system of the data link106includes a serializer306, a transmitter308, the data channel225, a receiver318, and a deserializer316. The serializer306converts parallel data received from the first electronic device102to serial data. The transmitter308sends the serial data to the data channel225. The receiver318processes the serial data and send the processed serial data to the deserializer316, which converts the serial data back to the parallel data for the second electronic device104. On a transmitting side, a phase lock loop310generates a transmitter clock signal312based on a reference clock signal324, and the transmitter clock signal312is applied to control serialization of the data to be transmitted by the data channel225of the data link106.

On a receiving side, a clock data recovery (CDR) circuit322is used to recover a receiver clock signal326from the serial data received via the data channel225and compensate for a variation of signal amplitudes caused by a loss and other factors in this data channel225. In some implementations, the CDR circuit322further includes a sampler and a clock recovery circuit. In some implementations, the CDR circuit322is implemented based on one of: a phase-locked loop (PLL), a delay-locked loop (DLL), and a phase interpolator (PI). In some implementations, the CDR circuit322satisfies a BER requirement corresponding to a jitter tolerance. Additionally, the CDR circuit322complies with a communication interface standard (e.g., PCIe, USB4), is functional with spread spectrum clocking (SSC), and satisfies an electromagnetic interference (EMI) requirement. Under some circumstances, the CDR circuit322is configured to be applied in two or more data interfaces having different data rates and signal modulation schemes. The CDR circuit322is configurable, e.g., by offering a pull-in frequency range that is greater than a pull-in frequency range threshold and a jitter tolerance that is better than a jitter tolerance threshold. In some implementations, the CDR circuit322is optimized in both of the pull-in frequency range and jitter tolerance.

The receiver clock signal326generated by the CDR322is used with the receiver318and deserializer316to condition the serial data received via the data channel106and regenerate the parallel data from the serial data. During this process, the receiver318is configured to reduce signal distortion, data spreading over sequential symbols, inter symbol interference (ISI), and resulting bit errors of the serial data on the receiving side of the second electronic device104. The receiver318is configured to generate an output data signal including the stream of data bits302in an input data signal of the receiver318. In some implementations, the receiver318includes a signal conditioning front end applying one or more modulation circuits350to compensate for a loss from the data channel225. Referring toFIG.3B, in some implementations, the receiver318includes one or more of: a continuous time linear equalizer (CTLE)336, a variable gain amplifier (VGA)338, a feed-forward equalizer (FFE)340B, and a decision feedback equalizer (DFE)342. The CTLE336is configured to selectively attenuate low frequency signal components, amplify signal components around the Nyquist frequency, and remove higher frequency signal components to generate filtered serial data. Stated another way, in some implementations, the CTLE336includes an analog filter designed to equalize the signal loss in certain frequencies. The VGA338has a variable gain. The DFE342is configured to further amplify the filtered serial data, and recover one or more data bits at each clock switching edge or during each clock cycle. The one or more recovered data bits form data packets. In some implementations, the FFE340B includes an FIR filter having a plurality of equalization settings (e.g., FIR coefficients), and is applied to improve signal quality of the data packets via digital signal conditioning (e.g., via high frequency filtering in a digital domain). In some implementations, feed forward equalization is optionally implemented by a transmitter-side FFE340A, a receiver-side FFE340B, both. The FFE340A is configured to pre-distort the signal to compensate for the lossy data channel225. In some implementations, a subset or all of the modulation circuits350is applied, and an order of the modulation circuits350is optionally identical to or distinct from that shown inFIG.3B. As such, the receiver IC304receives an input data signal314carrying a stream of data bits302according to a reference clock frequency (e.g., a reference clock signal324inFIG.3A), and outputs an output data signal304including a stream of recovered data bits304that is consistent with the stream of data bits302, thereby reliably keeping the stream of data bits302in the input data signal314.

In some implementations of this application, in-situ adaptation is implemented on different modulation circuits350of an electronic device (e.g., a second electronic device104inFIG.1). The electronic device includes a sequence of modulation circuits350, and each modulation circuit has one or more adjustable configurations. The electronic device obtains an input data signal314. The sequence of modulation circuits350processes the input data signal314and generates an equalized data signal344including a first data sample. The electronic device determines a first residual error of the first data sample, and adjusts a first adjustable configuration of a first modulation circuit (e.g., CTLE336) based on the first residual error. A second adjustable configuration of a second modulation circuit (e.g., VGA338) is further adjusted based on the first adjustable configuration. In some implementations, a single receiver integrated circuit (IC) includes the sequence of modulation circuits350and is configured to operate with different data rates, ambient temperatures, protocols, cables, and operating environments. Each modulation circuit350of the receiver IC is highly programmable and adaptive to offer different equalizer strengths and configurations in support of highly variable operating conditions. Particularly, in-situ and real-time adaptations of the modulation circuits350are implemented dynamically, jointly, and iteratively without interfering with each other. As the operating conditions (e.g., ambient temperature) change in real time during operation, in-situ and real-time adaptation of the receiver IC makes the data communication link106transmit data reliably and adjustably in response to variations of the operating conditions.

FIG.4is a block diagram of an in-situ equalization system400of a data link106, in accordance with some implementations. The in-situ equalization system400includes an adaptive equalizer controller402and one or more modulation circuits350. The one or more modulation circuits350include one or more of: a transmitter-side FFE340A, a CTLE336, a VGA338, a receiver-side FFE340B, and a DFE342. The one or more modulation circuits350form a sequence of modulation circuits350. The modulation circuits350of a receiver318receive an input data signal314transmitted by a wire set330A and carrying a stream of data bits302and generate an equalized data signal344, reducing the ISI caused by channel losses in a stream of recovered data bits304of the equalized data signal344. The adaptive equalizer controller402is coupled to each of the one or more modulation circuits350and configured to control adaptation of the one or more modulation circuits350(e.g., concurrent adaptation of two or more modulation circuits350). In some implementations, the transmitter308includes the FFE340A, which is on a transmitter side distinct from a receiver side where the CTLE336, VGA, FFE340B, and DFE342are located. The adaptive equalizer controller402is coupled to the FFE340of the transmitter308via a separate side-channel or full-duplex backchannel.

In some implementations, a slicer404is coupled to the one or more modulation circuits350. The slicer404receives the equalized data signal344and compares the equalized data signal344with one or more reference voltages to generate an output data signal406including the stream of recovered data bits304. The output data signal406is provided to the adaptive equalizer controller402as an error feedback408. In some implementations, the ISI caused by the wire set330is pre-compensated by the FFE340A on a transmitter side. In some implementations, the ISI caused by the wire set330is reduced and partially compensated by the modulation circuits350on a receiver side. The output data signal406(also called error feedback408) is sampled according to a receiver clock signal326, and each sample of the output data signal406corresponds to a respective ISI cursor. After transmitter-side pre-compensation and/or receiver-side compensation, the error feedback408includes a residual error at each sample (i.e., at each ISI cursor), and each sample deviates from a voltage level of a corresponding data bit by the residual error. In some implementations, the error feedback408includes a sign of the residual error for each ISI cursor.

The adaptive equalizer controller402includes one or more adaptation logics410and a residual error logic (REL)420. The one or more adaptation logics410includes one or more of: a FFE adaptation logic440A, a CTLE adaptation logic436, a VGA adaptation logic438, a FFE adaptation logic440B, and a DFE adaptation logic442. In some implementations, each of a subset of the adaptation logics410is coupled to the REL420and a respective one of the modulation circuits350. For example, the FFE adaptation logic440A is coupled to the FFE340A; the CTLE adaptation logic436is coupled to the CTLE336; the VGA adaptation logic438is coupled to the VGA338; the FFE adaptation logic440B is coupled to the FFE340B; and the DFE adaptation logic442is coupled to the DFE342. For each of a subset of modulation circuit350, the REL420determines a respective residual error412and provides the respective residual error412to the respective adaptation logic410, which further adjusts an adjustable configuration of the respective modulation circuit350based on the residual error412.

In some implementations, an adaptation logic410is configured to receive a respective residual error412, adjust a respective adjustable configuration based on the respective residual error412, and generates an equalizer control signal414to tune the respective adjustable configuration of a respective modulation circuit350. In some implementations, the CTLE336includes a continuous time filter including an resistor capacitor (RC) network. The adjustable configuration of the CTLE336includes a plurality of resistance values (e.g., R0, R1, R2) and a plurality of capacitance values (e.g., CP0, CP1) of the RC network. In some implementations, the adjustable configuration of the VGA338includes a gain GSthat is adjusted continuously or selected from a number of predefined gains. In some implementations, the adjustable configuration of the FFE440A or440B corresponds to a plurality of FIR coefficients C−r, . . . . C0, . . . , and C+s(e.g., where r is equal to 2, and s is equal to 1). In some implementations, the adjustable configuration of the DFE442corresponds to a plurality of DFE coefficients h0, . . . , and hd. Additionally, in some implementations, for each modulation circuit350, the adjustable configuration identifies a preset of adjustable coefficients in a corresponding preset table including a respective number of discrete adjustable settings. For example, the adjustable configuration of the CTLE336is selected from a preset table including a predefined number of discrete configuration settings of capacitors and resistors of the RC network. Higher a preset on the preset table, the stronger compensation provided by the CTLE336.

In some implementations, the adaptive equalizer controller402includes a concurrent adaptive controller430coupled to the adaptation logics410. The concurrent adaptive controller430is configured to control coupling among the adaptation logics410, such that a first adjustable configuration of a first modulation circuit350A is determined by a first adaptation logic410A (FIG.5) based on a residual error412and provided to both the first modulation circuit350A and a second adaptation logic410B (FIG.5). The first modulation circuit350A processes the input data signal314based on the first adjustable configuration506A (FIG.5), and the second adaptation logic410B determines a second adjustable configuration506B for the second modulation circuit350B based on the first adjustable configuration506A. For example, the concurrent adaptive controller430provides control signals to couple the DFE adaptation logic442to the VGA adaptation logic438. A DFE coefficient h0is determined by the DFE adaptation logic442based on a corresponding residual error412of a current sample and provided to both the DFE342and the VGA adaptation logic438. The DFE342is updated to adopt the DFE coefficient h0and process the input data signal314. The VGA adaptation logic438determines the gain value GSfor the VGA338based on the DFE coefficient h0.

FIG.5is a flow diagram of a process of determining adjustable configurations506of modulation circuits350of a data link106, in accordance with some implementations. A residual error logic420is coupled to a slicer404and one or more adaptation logics410including one or more of: a FFE adaptation logic440A, a CTLE adaptation logic436, a VGA adaptation logic438, a FFE adaptation logic440B, and a DFE adaptation logic442(FIG.4). The FFE adaptation logic440A, CTLE adaptation logic436, VGA adaptation logic438, FFE adaptation logic440B, and DFE adaptation logic442further couple the REL to the FFE340A, CTLE336, VGA338, FFE340B, and DFE342, respectively. The residual error logic420is configured to receive an output data signal406including the stream of recovered data bits304, obtain a plurality of data samples502, and determine one or more residual errors412. For example, the REL420obtains the output data signal406including a first data sample502A and/or a second data sample502B, and generates the residual errors412including a first residual error412A of the first data sample502A and/or a second residual error412B of the second data sample502B. The second data sample502B precedes or follows the first data sample502A. Each of the modulation circuits350updates its own respective adjustable configuration506based on associated residual error(s)412, an adjustable configuration of a different modulation circuit350, or a combination thereof.

In some implementations, a first adaptation logic410A is configured to obtain one or more residual errors412from the residual error logic420, update a first adjustable configuration506A of a first modulation circuit350A based on the obtained residual errors412, and optionally determine a first configuration error512A of the first adjustable configuration506A. Alternatively, in some implementations, a second adaptation logic410B is configured to obtain configuration information of one or more distinct modulation circuit (e.g., the adjustable configuration506A or a configuration error512A of the first modulation circuit350A), and update an associated adjustable configuration506B of a second modulation circuit based on the obtained configuration information of the distinct modulation circuit. Additionally and alternatively, in some implementations, the second adaptation logics410B is configured to obtain both a residual error412A or412B and configuration information of distinct modulation circuit (e.g., the adjustable configuration506A or configuration error512A of the first modulation circuit350A), and update an associated adjustable configuration506B of a respective modulation circuit350based on both the residual error412and the configuration information.

More specifically, in some implementations, the REL420includes a first adaptation logic410A and a second adaptation logic410B. An output data signal406includes a first data sample502A. The residual error logic420determines a first residual error412A of the first data sample502A. The first adaptation logic410A obtains the first residual error412A, and adjusts a first adjustable configuration506A of a first modulation circuit350A based on the first residual error412A. The second adaptation logic410B adjusts a second adjustable configuration506B of a second modulation circuit350B based on the first adjustable configuration506A. By these means, the second adjustable configuration506B is not adjusted based directly on data samples502or associated residual errors412of the output data signal406, and is adjusted by providing an accumulative adjustment effect dynamically, jointly, or iteratively with the first adjustable configuration506A, thereby expediting an adaptation process of the modulation circuit350.

In some implementations, the modulation circuit350A or350B determines a first configuration error512A corresponding to the first adjustable configuration506A, and the second adjustable configuration506B is adjusted based on the first configuration error512A. In some implementations, adjustments of the first and second adjustable configurations506A and506B are weighted differently, as the configurations506A and506B are adjusted jointly. The first adaptation logic410A applies a first scale factor k1to the first residual error412A, and the second adaptation logic410B applies a second scale factor k2to the first configuration error512A, while the first adjustable configuration506A of the first modulation circuit350A and the second adjustable configuration506B of the second modulation circuit350B are adjusted jointly and iteratively.

In some implementations, a third adaptation logic410C is configured to adjust a third adjustable configuration506C of a third modulation circuit350C based on the second adjustable configuration506B. Further, in some implementations, the adaptation logic410B or410C determines a second configuration error512B corresponding to the second adjustable configuration506B, and the third adjustable configuration506C is adjusted based on the second configuration error512B. In some implementations, adjustments of the first, second, and third adjustable configurations506A,506B, and506C are weighted differently, as the configurations506A,506B, and506C are adjusted jointly. For example, scale factors k1, k2, and k3are applied to the first residual error412A, the first configuration error512A, the second configuration512B, respectively. By these means, the first, second, and third configurations506A,506B, and506C of different modulation circuits350are adjusted dynamically, jointly, and iteratively to provide an accumulative effect on suppressing ISI, enhancing SNR, and reducing BER of the output data signal406, thereby expediting an adaptation process of the modulation circuit350.

In some implementations, the second adaptation logic410B obtains a second residual error412B of a second data sample502B of the output data signal406. The second data sample502B is distinct from the first data sample502A. The second adaptation logic410B adjusts the second adjustable configuration506B based on the first adjustable configuration506A and one or more of: the first data sample502A, the first residual error412A, the second data sample502B, and the second residual error412B of the output data signal406. Optionally, the second data sample502B-1precedes the first data sample502A of a current ISI cursor and corresponds to a prior ISI cursor temporally preceding the current ISI cursor. Optionally, the second data sample502B-2follows the first data sample502A of a current ISI cursor and corresponds to a post ISI cursor temporally following the current ISI cursor.

In some implementations, the second adaptation logic410B adjusts the second adjustable configuration506B based on the first adjustable configuration506A and one or more of: the first data sample502A and the first residual error412A of the output data signal406. In some implementations, a fourth adjustable configuration506D of a fourth modulation circuit350D is adjusted based on the output data signal406(e.g., a data sample502, a residual error412). The second adaptation logic410B adjusts the second adjustable configuration506B based on both the first adjustable configuration506A and the fourth adjustable configuration506D, e.g., in a weighted manner. Additionally, in an example, a fourth adjustable configuration506D has a fourth configuration error, and the second adjustable configuration506B is determined based on the first and fourth configuration errors, e.g., in the weighted manner. In some implementations, the second adaptation logic410B adjusts the second adjustable configuration506B based on the first adjustable configuration506A and one or more of: the second data sample502B and the first residual error412A of the output data signal406. In some implementations, the second adaptation logic410B adjusts the second adjustable configuration506B based on the first adjustable configuration506A, the first data sample502A, the second data sample502B, and the fourth adjustable configuration506D.

In some implementations, the sequence of modulation circuits350includes a CTLE336, a VGA338, a FFE340(e.g.,340A,340B), and a DFE342(FIG.4). The CTLE336has an adjustable CTLE preset CTLESidentifying one of a plurality of predefined sets of resistances of resistors and capacitances of resistors of the CTLE336. The VGA338has an adjustable gain GS. The FFE340has an adjustable FFE preset of FFE coefficients C−r, . . . . C0, . . . and CS. The DFE342has an adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. Referring toFIG.5, in some implementations (514), the first modulation circuit350A includes the DFE342, and the first adjustable configuration506A includes a subset of the adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The second modulation circuit350B includes one of the FFE340, CTLE336, and the VGA338. The second adjustable configuration506B includes a corresponding subset of the FFE preset of FFE coefficients C−r, . . . . C0, . . . and Cs, the CTLE preset CTLES, and the adjustable gain GS. In some implementations, the subset of the FFE preset of FFE coefficients C−r, . . . . C0, . . . and Csis further applied to determine the CTLE preset CTLES, or vice versa.

Conversely, in some implementations (516), the second modulation circuit350B includes the DFE342, and the second adjustable configuration506B includes a subset of the adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The first modulation circuit350A includes one of the FFE340, CTLE336, and the VGA338, and the first adjustable configuration506A includes a corresponding subset of the FFE preset of FFE coefficients C−r, . . . . C0, . . . , and Cs, the CTLE preset CTLES, and the adjustable gain GS. In some implementations, the adjustable DFE preset of DFE coefficients h0, h1, . . . and hd, which is adjusted based on the FFE preset, is further applied to determine the CTLE preset CTLES. In some implementations, the adjustable DFE preset of DFE coefficients h0, h1, . . . and hd, which is adjusted based on the CTLE preset CTLES, is further applied to determine the FFE preset. In some implementations, the DFE coefficients h0, which is adjusted based on the adjustable gain GS, is further applied to determine the CTLE preset CTLESor the FFE coefficient C0.

In some implementations, the second modulation circuit350B includes the DFE342, and the second adjustable configuration506B includes a subset of the adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The first modulation circuit350A includes two or more of the FFE340, CTLE336, and the VGA338, and the first adjustable configuration506A includes a combination of two or more selected configurations of the FFE preset of FFE coefficients C−r, . . . . C0, . . . and Cs, the CTLE preset CTLES, and the adjustable gain GS. For example, an average or a weighted combination of the two or more selected configurations is applied to determine the second adjustable configuration506B.

In some implementations, the first modulation circuit350A includes the DFE342, and the first adjustable configuration includes a DFE coefficients h0. The second modulation circuit350B includes the VGA338, and the second adjustable configuration506B includes the adjustable gain GS. The DFE coefficients h0and adjustable gain GSare adjusted jointly to suppress a first residual error412A of a first data sample502A associated with a current ISI cursor.

In some implementations, the first modulation circuit350A includes the DFE342, and the first adjustable configuration506A includes a subset of the adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The second modulation circuit350B includes the FFE340, and the second adjustable configuration506B includes a first subset of the FFE preset of FFE coefficients C0, . . . and Cs. Further, in some implementations, the second adaptation logic410B obtains a sequence of successive residual errors412B that immediately precedes the first residual error412A. The sequence of successive residual errors412B corresponds to a sequence of successive data samples502B-1that immediately precedes the first data sample502A. A second subset of the FFE preset of FFE coefficients C−r, . . . , and C−1is adjusted based on the sequence of successive residual errors412B and the first data sample502A.

In some implementations, the first modulation circuit350A includes the DFE342, and the first adjustable configuration506A includes a subset of the adjustable DFE preset of DFE coefficients h1, . . . and hd. The second modulation circuit350B includes one of the CTLE336, and the second adjustable configuration506B includes the CTLE preset CTLES.

In some implementations, the sequence of modulation circuits350includes a DFE342having an adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The output data signal406includes a sequence of successive data samples502that starts with the first data sample502A followed by one or more data samples502B-2, and every two successive data samples502are delayed from each other by a unity delay. The first adaptation logic410A adjusts an i-th DFE coefficients hibased on an (i+1)-th data sample of the sequence of successive data samples502and the first residual error412A, where i is an integer equal to or greater than 0. In an example, the first adaptation logic410A adjusts the DFE coefficient h0based on the first data sample502A and the first residual error412A. In another example, the first adaptation logic410A adjusts the DFE coefficient h2based on the residual sample502B-2(FIG.5) and the first residual error412A.

FIG.6Aillustrates an effect of inter-symbol interference (ISI)600on data transmission in a pulse amplitude modulation (PAM) scheme, in accordance with some implementations. In some implementations, a data bit302is transmitted by an ideal data channel225having no loss. The data bit302corresponds to a single-bit response (SBR)602including a single pulse. A data bit of “1” or “0” corresponds to a rectangular pulse having an amplitude above or below a common mode level, respectively. A series of data bits has a data pattern 011100 and corresponds to a series of SBRs604that are superimposed to one another to form an ideal data signal606. The ideal data signal606includes a train of pulses alternating between two volage levels VDD and VSS. The two voltage voltages VDD and VSS are above and below the common mode level VCM and represent the data bits of “1” and “0”, respectively. Each pulse of the ideal data signal606has a respective pulse width that is determined by a number of identical data bits in the respective pulse. Each pulse of the ideal data signal302has a rising edge and a falling edge, and both the rising and falling edges are substantially sharp (e.g., have edge rates that are greater than a threshold rate).

In some implementations, the data channel225has a loss caused by ISI, and a data bit302corresponds to a single-bit response (SBR)612including a single pulse (e.g., a cosine squared pulse, a Gaussian pulse), which is not a rectangular pulse. A data bit of “1” or “0” corresponds to a non-rectangular pulse (e.g., a cosine squared pulse) having an amplitude above or below the common mode level, respectively. A series of data bits having the data pattern 011100 corresponds to a series of SBRs614that are superimposed to one another to form a data signal616inFIG.6(e.g., corresponding to an input data signal314or an equalized data signal344inFIG.3B). The data signal616includes a train of pulses alternating between two peak volage levels. The two peak voltage voltages are above and below a common mode level VCM, and correspond to the data bits of “1” and “0”, respectively. Each pulse of the ideal data signal606has a respective pulse width (e.g., w1, w2, and w3) that is determined by a number of identical data bits in the respective pulse. Each pulse of the ideal data signal302has a rising edge and a falling edge. Both the rising and falling edges are degraded by ISI600, and therefore, are not substantially sharp (e.g., have edge rates that are less than the threshold rate). In some implementations, if the data signal616is sampled before equalization, the stream of data bits recovered from the data signal616may include a number of bit errors that is beyond a bit error tolerance of the data communication channel225.

FIG.6Bis a temporal diagram of a data signal616(e.g., an output data signal406inFIG.4) including a plurality of samples502, in accordance with some implementations. The data signal616includes a stream of data bits that are coded onto the data signal616according to a reference frequency of a reference clock signal324on a transmitter side. When the data signal616is sampled at the reference frequency, the effect of ISI600is quantified based on measurement of samples502of the data signal314. In some implementations, the output data signal406is sampled at the reference frequency of the reference clock signal324, i.e., at every unit interval. Each sample502is denoted as h[x], where x is a variable tap index. In some implementations, a current sample502C (i.e., h[0]) corresponds to an index value equal to 0. Negatively indexed values correspond to precursor samples512P (e.g., h[−1], h[−2]), which reflects an effect of precursor ISI. The precursor ISI degrades signal quality of the data bits302transmitted over the data channel225before the current sample502C. Positively indexed values correspond to postcursor samples512Q (e.g., h[1], h[2] . . . h[8]), which reflects an effect of postcursor ISI. The postcursor ISI degrades signal quality of the data bits302transmitted over the data communication channel225after the current sample502C. The current sample502A (h[0]) is not impacted by ISI, contains actual information of a current data bit302, and is referred to as a main cursor. In some implementations, an adaptive equalizer controller402reduces the effect of ISI600by reducing or suppressing precursor and postcursor ISI and/or by amplifying a magnitude of the current sample (i.e., the main cursor), thereby enhancing BER of an associated data link106.

FIG.7Ais a temporal diagram of example data signals700that are processed and outputted by a CTLE336, in accordance with some implementations. The CTLE336is a continuous time filter configured to at least partially compensate for a channel loss caused by the data channel225to which the CTLE335is coupled. The CTLE336includes an RC network. Adjustable configuration506of the CTLE336includes a plurality of resistance values (e.g., R0, R1, R2) and a plurality of capacitance values (e.g., CP0, CP1) of the RC network. In some implementations, the adjustable configuration506of the CTLE336identifies a preset of adjustable coefficients in a corresponding preset table including a respective number of discrete adjustable settings. For example, the adjustable configuration of the CTLE336is selected from a preset table including a predefined number of discrete configuration settings of the RC network. Higher a preset on the preset table, the stronger compensation provided by the CTLE336, and the lower ISI observed on a corresponding data signal700.

In this example, the data signals700include a first data signal700A and a second data signal700B. The main cursors (i.e., the current samples512(h[0])) are normalized on the data signals700. The first data signal700A corresponds to a first CTLE preset506-1and includes postcursor samples502Q1(e.g., h[1] and h[2]). The second data signal700B corresponds to a second CTLE preset506-2and includes postcursor samples502Q2(e.g., h′[1] and h′[2]). The first CTLE preset506-1is lower than the second CTLE preset506-2. Each postcursor sample502Q2is smaller than a respective postcursor sample502Q1, and the CTLE336provides stronger ISI compensation in the second data signal700B compared with the first data signal700A.

A preferred CTLE preset is identified in accordance with a determination that ISI cursors are substantially near zero (i.e., that all precursor samples502P and post-cursor samples502Q are substantially equal to VSS or within a predefined threshold range of VSS). Referring toFIG.7A, a third data signal700C located between the data signals700A and700B appears to provide the preferred CTLE preset506-3. In contrast, the first data signal700A corresponds to an under-compensation condition in which the postcursor samples502Q1are above VSS, and the second data signal700B corresponds to an over-compensation condition in which the postcursor samples502Q1are below VSS (e.g., goes beyond the predefined threshold range of VSS). The low voltage level VSS corresponds to a data bit of “0”. In some implementations, the low voltage level VSS is a ground level.

In some implementations, an adaptive CTLE loop is formed to provide the equalizer control signal414that controls the CTLE336. Referring toFIG.4, samples502of the output data signal406are collected to determine associated residual errors412. In accordance with a determination that the residual errors of the postcursor samples502Q are positive, the CTLE preset is incremented. Conversely, in accordance with a determination that the residual errors412of the postcursor samples502Q are negative, the CTLE preset is decremented. The CTLE preset is iteratively adjusted based on the residual errors of the postcursor samples502Q until the preferred CTLE preset is identified (i.e., until the residual errors of the postcursor samples502Q fall within the predefined threshold range of VSS). In some implementations, the residual errors of the postcursor samples502Q vary monotonically with respect to the CTLE preset, i.e. higher preset in the preset table corresponds to lower postcursor sample values. In some implementations, the CTLE adaptation logic436includes a decoding table. The CTLE adaptation logic436obtains the preferred CTLE preset, and determines filter control signals for resistors and capacitors of the RC network of the CTLE336to select a subset of the resistors and capacitors. The filter control signals tune the pole/zero locations of the CTLE336.

FIG.7Bis a temporal diagram of an data signal740that is processed and outputted by a VGA338, in accordance with some implementations. The VGA338is a modulation circuit350used with other equalization circuit, and is not an equalizer by itself. In some implementations, the VGA338is used jointly with the CTLE336to enhance signal integrity. From a different perspective, the VGA338is a continuous time filter configured to provide a flat gain across a VGA frequency band. The VGA338enhances an overall amplitude of the data signal740, such that an SNR of a data signal406generated by the slicer404(FIG.4) is improved (i.e., a signal amplitude of the data signal406increases, while noise from the slicer404stays constant). Adjustable configuration of the VGA338includes a gain value GSthat is adjusted continuously or selected from a number of predefined gains (also called VGA gain presets). As VGA gain preset increases, the amplitude of the data signal740increases. In some implementations, the VGA gain preset is high, such that the data signal740begins to clip and distortion occurs. A preferred VGA gain preset maximizes a peak of the data signal740without causing distortion.

In some implementations, a residual error412is identified for the main cursor h[0] (i.e., a current sample502C) of the data signal740by comparing the current sample502C with a pre-programmed target value of h[0]. A VGA preset update logic (not shown) applies the residual error412identified for the main cursor h[0] to update the adjustable configuration of the VGA338including the gain value G. In accordance with a determination that the residual error412is less than 0 (i.e., the current sample502C is lower than the targe value of h[0]), the VGA gain preset is incremented. Conversely, in accordance with a determination that the residual error412is greater than 0 (i.e., the current sample502C is greater than the targe value of h[0]), the VGA gain preset is decremented. A preferred gain value or a preferred VGA gain preset is determined in accordance with a determination that the residual error412of the main cursor h[0] is within a predefined threshold range of 0 or in accordance with a determination that the current sample502A is substantially close to the pre-programmed target value of h[0] (i.e., within a predefined threshold range of the pre-programmed target value of h[0]).

Additionally, in some implementations, a DFE342is a commonly used equalization technique that uses a set of coefficients C−r, . . . , C0, . . . , and C+sto estimate the ISI at sampling period spaced intervals. These coefficients are multiplied with the sign of previously received bits and then subtracted from the incoming data, thus removing some of the ISI seen at the slicer404and improving the BER. In some implementations, a data signal is summed with a series of DFE weights that are multiplied with the sign of delayed data decisions. A DFE coefficient update logic is configured for updating the coefficients by comparing the sign of the residual error measured by the slicer404with the sign of the data decisions. A common way to implement the DFE adaptation logic442is to use a sign-sign least-mean-square (SSLMS) algorithm, which is an efficient form of stochastic gradient descent (SGD) algorithm. The adaptive logic operates by finding the sign of the residual error of each postcursor ISI tap (i.e., each postcursor sample512Q inFIG.6B). In some implementations, the residual error includes a combination of a data sample and an error sign, and is denoted as e[0]*d[n], where e[0] is the sign (“+” or “−”) of a residual error412measured at a current sampling interval and corresponding to a current sample502C, d[n] is a digital value (“1” or “0”, which is represented as “+” or “−”) of a data decision measured at the previous n-th interval, and n is a positive integer. If the resulting residual error e[0]*d[n] is positive, the estimated DFE coefficient hnshould be incremented, and conversely, if e[0]*d[n] is negative, then estimated DFE coefficient hnshould be decremented. This procedure is then repeated for the current sample512C and postcursor samples502Q (i.e. h[0], h[1], h[2], . . . ). Precursor samples502P (i.e. h[−1], h[−2]) cannot be corrected by the DFE342.

In some implementations, an FFE340includes a transversal FIR filter that is optionally implemented on a transmitter side, a receiver side, or both. The FFE340convolves a data signal and reduces the effect of ISI on the data signal. In some implementations, the FEE complexity of the transmitter-side FFE340A is lower compared to a receiver-side FFE340B. Adaptation of the FFEs340A and340B are similarly implemented, except that, in some implementations, the transmitter-side FFE340A is coupled to a side channel that allows the equalizer control signal414to be returned to the receiver-side FFE340B. Adjustable configuration of the FFE340A or340B corresponds to a plurality of FIR coefficients C−r, . . . , C0, . . . , and C+s. In some implementations, the adjustable configuration of the FFE340identifies a preset of adjustable FIR coefficients in a corresponding preset table including a respective number of discrete adjustable settings.

In some implementations, the FFE340includes a series of unit delays and gain cells, and is configured to sum intermediate waveforms to produce a data signal. Weights or gains (e.g., FFE coefficients) of delayed signals are adjusted, such that the data signal reaching the slicer404exhibits minimal amount of ISI. A collection of weights (e.g., FFE coefficients) is controlled by a FFE coefficient update logic. The plurality of FIR coefficients C−r. . . , C0, . . . , and C+sare sent back from the FFE adaptation logic440B to the FFE340. It is noted that the FFE340equalizes current samples512C (h[0]), precursor samples512P (e.g. h[−1], h[−2]), and postcursor samples512Q (e.g. h[1], h[2]). For example, error signals for FFE precursor adaptation include combinations of a current sample502C with different residual errors e[n]*d[0], where n represents the n-th precursor coefficient. In an example, e[2]*d[0] is used to adapt the FIR coefficient C−2based on a current sample502C (“1” or “0”) and a residual error of a precursor sample502P (e.g., represented by a sign of the residual error of the precursor sample502P (“+” or “−”). In accordance with a determination that the current sample502C is equal to “1” (also represented as “+”) and the residual error of the precursor sample502P (e[2]) is equal to “+”, the FIR coefficient C−2is decreased. In accordance with a determination that the current sample502C is equal to “0” (also represented as “−”) and the residual error of the precursor sample502P (e[2]) is equal to “+”, the FIR coefficient C−2is increased.

FIG.8is a block diagram of another example in-situ equalization system400of a data link106including an adaptive equalizer controller402having a residual error logic420, in accordance with some implementations. A data link106(FIG.3A) includes a transmitter308and a receiver318. The receiver318is configured to generate an equalized data signal344(FIG.3B) including a stream of data bits302in an input data signal314of the receiver318. In some implementations, the data link106includes one or more modulation circuits350to compensate for a loss from the data communication channel225. The one or more modulation circuit350includes one or more of: the CTLE336, VGA338, FFE(s)340, and DFE342. A slicer404is coupled to the one or more modulation circuits350. The slicer404receives the equalized data signal344and samples the equalized data signal344to generate an output data signal406including a plurality of samples. The output data signal406is provided to the adaptive equalizer controller402, which adapts adjustable configuration of a subset or all of the one or more modulation circuit350having one or more adjustable configurations concurrently (e.g., simultaneously, in real time).

In some implementations, the output data signal406is sampled according to a sampling rate (e.g., related to a clock frequency of a receiver clock signal326), and each sample of the output data signal406corresponds to a respective ISI cursor. After transmitter-side pre-compensation and/or receiver-side compensation, the output data signal406includes a residual error at each sample, and the respective sample deviates from a predefined voltage level of a corresponding data bit by the residual error. In some implementations, the data signal406includes a current sample502C, one or more postcursor samples502Q, and one or more precursor samples502P, and each sample502corresponds to a residual error412. Further, in some implementations, the slicer404compares each sample502with a common mode voltage to determine a corresponding data bit406aas “1” or “0” (also as “+” or “−”). Each sample502is further compared with the predefined voltage level VDD or VSS of the corresponding data bit to determine a corresponding error sign406b(e.g., “+”, “−”). Each sample502corresponds to a respective residual error412that is determined based on a combination of the data bit406aand the error sign406b. Stated another way, in some implementations, each residual error412is determined by the residual error logic420based on respective sampling and residual references (e.g., the common mode voltage, the predefined voltage levels VDD and VSS).

The adaptive equalizer controller402includes a residual error logic420that is coupled to a slicer404and one or more adaptation logics410. The adaptation logic(s)410include one or more of: a FFE adaptation logic440A, a CTLE adaptation logic436, a VGA adaptation logic438, a FFE adaptation logic440B, and a DFE adaptation logic442(FIG.4). The residual error logic420is configured to receive a plurality of data samples502and a plurality of residual errors412of the output data signal406including the stream of recovered data bits304. The plurality of data samples502includes samples d[0], d[1], . . . , and d[k], which equal to “1” or “0” (also represented as “+” or “−”), and the plurality of residual errors412includes samples e[m], e[m−1], . . . , and e[0], where k and m are two distinct positive integers. In some implementations, each of the plurality of residual errors412includes a sign of the respective residual error, and an adaptation logic410adjusts a corresponding adjustable configuration based on the sign of the respective residual error (e.g., “+” or “−”) and a data sample value (e.g., d[0], which is equal to “0” or “1” (also represented as “+” or “−”)).

In some implementations, the plurality of samples502includes a current sample, m precursor samples, and k postcursor samples, and the residual error logic420generates a total number (e.g., m+k+1) of residual errors412. Adjustable configuration of a first modulation circuit350A (e.g., DFE342, FFE340, CTLE336) is adjusted based on the residual errors412. For example, for each of DFE, FFE, and CTLE adaptation logics442,440, or436, a respective residual error412is provided to the respective adaptation logic442,440, or436to adjust the corresponding adjustable configuration of the first modulation circuit350A. In some implementations, the adjusted adjustable configuration of the first modulation circuit350A (e.g., DFE342) is provided to a distinct adaptation logic440,436, or438to adjust adjustable configuration of a second modulation circuit350B (e.g., FFE340, CTLE336, or VGA338). Further, in some implementations, for the second modulation circuit350B (e.g., FFE340, CTLE336, or VGA338), the adjusted adjustable configuration of the first modulation circuit350A (e.g., DFE342) is provided jointly with a respective residual error412to the distinct adaptation logic440,436, or438to adjust the adjustable configuration of the second modulation circuit350B.

In some implementations, the DFE adaptation logic442updates the DFE coefficients h0-hdbased on the residual errors412. The DFE342has a number of (d) DFE taps, and the DFE adaptation logic442outputs a DFE control signal802corresponding to the updated DFE coefficients h0-hd. The DFE control signal802is applied to control the DFE342according to the updated DFE coefficient h0-hd. In some situations, the DFE control signal802is further provided to one or more of: the FFE adaptation logic440, the CTLE adaptation logic436, and the VGA adaptation logic438. Further, in some implementations, the FFE adaptation logic440updates each of the FIR coefficients C−r, . . . , C0, . . . , and C+sbased on the residual errors412, the DFE control signal802, or both. The FFE340corresponds to a current sample502C, r precursor samples502P and s postcursor samples, where r and s are positive integers. The FFE adaptation logic440output an FFE control signal804corresponding to the FIR coefficients C−r, . . . . C0, . . . , and C+s. The FFE control signal804is applied to control the FFE340according to the updated FIR coefficients C−r, . . . C0, . . . , and C+s. In an example, the FFE control signal804is further provided to the CTLE adaptation logic436. In some implementations, the CTLE adaptation logic436updates the CTLE preset selection806based on a subset or all of the residual errors412, the DFE control signal802, and the FFE control signal804. In some implementations, the VGA adaptation logic438updates the VGA preset selection808based on the DFE control signal802defining the DFE coefficient h0.

In some implementations, the adaptive equalizer controller402includes a concurrent adaptation controller (CAC)430. The CAC430provides programmable parameters (e.g., enable signals, adaptation update rate control) for adaptation logics410of the adaptive equalizer controller402in accordance with different applications or environments. In accordance with the programmable parameters, the adaptation logics410are arranged to facilitate adjusting an adjustable configuration of an adaptation logic (e.g., the second adjustable configuration506B) based on an adjustable configuration of a distinct adaptation logic (e.g., the first adjustable configuration506A).

FIG.9is a block diagram of a residual error logic420coupled to a slicer404, in accordance with some implementations. The residual error logic420includes combinational logics and is configured to determine a plurality of residual errors412. The residual error logic420receives a data signal406A and an error signal406B from the slicer404. The slicer generates the data signal406A and error signal406B by comparing the equalized data signal344provided by a sequence of modulation circuits350with a common mode voltage and a respective voltage level corresponding to a data bit (e.g., “1” or “0”, “+” or “−”). Each of the data signal406A and error signal406B is delayed by k delay units and m delay units to provide a series of delayed data signals D[0]-D[k] and a series delayed error signals E[0]-E[m], respectively. The series of delayed data signals D[0]-D[k] and the series delayed error signals E[0]-E[m] are combined (e.g., using XOR logic904) to generate a plurality of residual errors412. The plurality of residual errors412are provided to one or more of: the DFE adaptation logic442, the FFE adaptation logic440, and the CTLE adaptation logic436.

FIG.10is a block diagram of an example adaptive equalizer controller402, in accordance with some implementations. The adaptive equalizer controller402includes a residual error logic420, a concurrent adaptation controller430, and a plurality of adaptation logics410including a DFE adaptation logic442, a VGA adaptation logic438, an FFE adaptation logic440, and a CTLE adaptation logic436. The DFE342corresponding to the DFE adaptation logic442has d ISI taps, where d is a positive integer. The residual error logic420generates a plurality of residual errors412. Each of a subset of residual errors412is a combination of an error signal406b(E[0]) and a respective delayed data signal406a(D[i]), and represented by E[0]D[i], where i is equal to 0, 1 . . . , and d. The concurrent adaptation controller430provides programmable enable (e.g., a plurality of DFE enable signals enableDFE) and gai settings (e.g., a plurality of gain value μDFE). The gain settings control a rate of adaptation. The higher each gain value μi,DFE, the faster an adaptation rate of a corresponding DFE coefficient hidespite a higher noise level. In some implementations, each DFE enable signal enablei,DFEcontrols a respective switch, e.g., enables a connection if the DFE enable signal is “1” and disables the connection if the DFE enable signal is “0”.

In some implementations, the DFE adaptation logic442is controlled by the plurality of DFE enable signals enableDFEto generate a plurality of DFE coefficients h0-hd. Specifically, in some implementations, for each DFE coefficient hi, the DFE adaptation logic442is controlled by a respective DFE enable signals enable; DFE to multiple (1002) a respective residual error signal E[0]D[i] with a respective gain value μi,DFEand accumulate a corresponding product by a delayed sum1004to generate a respective DFE coefficient hi, where i is equal to 0, 1, . . . , and d. The DFE coefficients h0-hdform a DFE coefficient array802.

Further, in some implementations, the FFE adaptation logic440is coupled to the concurrent adaptation controller430and the DFE adaptation logic442. The FFE adaptation logic440receives the DFE coefficients h0-hdand updates the FIR coefficients Cj, where s≥j≥−r. For postcursor taps (e.g., C1, C2) corresponding to postcursor samples502Q, the residual error E[0]D[i] is multiplexed with the DFE coefficient hito enforce orthogonality. In some implementations, the DFE coefficient hiis already adapted based on E[0]D[i], and the corresponding FFE coefficient Ciis adjusted based on the DFE coefficient hi, e.g., using a configuration error of the DFE coefficient hi.

In some implementations, the VGA adaptation logic438is coupled to the concurrent adaptation controller430and the DFE adaptation logic442. The VGA adaptation logic438receives the DFE coefficient h0and updates the VGA preset select808. Both the DFE coefficient h0and the VGA preset select808corresponding to the current sample502C. In some implementations, the DFE coefficient h0is already adapted based on E[0]D[0], and the corresponding VGA preset select808is adjusted based on the DFE coefficient h0, e.g., using a configuration error of the DFE coefficient h0.

FIG.11is a flow diagram of an example method1100for adapting an electronic device in a data channel, in accordance with some implementations. For convenience, the method1100is described as being implemented by the electronic device. The electronic device obtains (1102) an input data signal by the electronic device including a sequence of modulation circuits350, and each modulation circuit350has (1104) one or more adjustable configurations506. The electronic device processes (1106) the input data signal by the sequence of modulation circuits350to generate an output data signal (e.g., an output data signal406) including a first data sample502A, and determines (1108) a first residual error412A of the first data sample502A. The electronic device adjusts (1110) a first adjustable configuration506A of a first modulation circuit350A based on the first residual error412A, and adjusts (1112) a second adjustable configuration506B of a second modulation circuit350B based on the first adjustable configuration506A.

In some implementations, the electronic device adjusts the second adjustable configuration506B by determining (1114) a first configuration error512A of the first adjustable configuration506A. The second adjustable configuration506B is adjusted based on the first configuration error512A of the first adjustable configuration506A. Further, in some implementations, the electronic device applies (1116) a first scale factor to the first residual error412A and a second scale factor to the first configuration error512A and adjusts (1118) the first adjustable configuration506A of the first modulation circuit350A and the second adjustable configuration506B of the second modulation circuit350B jointly or iteratively based on the first and second scale factors.

In some implementations, the electronic device determines a second residual error412B of a second data sample502B of the output data signal. The second data sample502B is distinct from the first data sample502A. The second adjustable configuration506B is adjusted based on the first adjustable configuration506A and one or more of: the first data sample502A, the first residual error412A, the second data sample502B, and the second residual error412B of the output data signal. The second data sample502B is optionally precedes or follows the first data sample502A.

In some implementations, the second adjustable configuration506B is adjusted based on the first adjustable configuration506A and one or more of: the first data sample502A and the first residual error412A of the output data signal.

In some implementations, the electronic device adjusts a third adjustable configuration506C of a third modulation circuit350C based on the second adjustable configuration506B.

In some implementations, the electronic device adjusts a fourth adjustable configuration506D of a fourth modulation circuit350D based on the output data signal. The second adjustable configuration506B of the second modulation circuit350B is adjusted based on both the first adjustable configuration506A and the fourth adjustable configuration506D.

In some implementations, the first adjustable configuration506A of the first modulation circuit350A and the second adjustable configuration506B of the second modulation circuit350B are adjusted dynamically, jointly, or iteratively.

In some implementations, the sequence of modulation circuits350includes a continuous time linear equalizer (CTLE)336, a variable gain amplifier (VGA)338, a feed-forward equalizer (FFE)340, and a decision feedback equalizer (DFE)342. The CTLE336has an adjustable CTLE preset CTLESidentifying one of a plurality of predefined sets of resistances of resistors and capacitances of resistors of the CTLE336. The VGA338has an adjustable gain GS. The FFE340has an adjustable FFE preset of FFE coefficients C−r, . . . . C0, . . . and Cs. The DFE342has an adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. Further, in some implementations, the first modulation circuit350A includes (1120) the DFE342, and the first adjustable configuration506A includes a subset of the adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The second modulation circuit350B includes (1122) one of the FFE340, CTLE336, and the VGA338. The second adjustable configuration506B includes (1124) a corresponding subset of the FFE preset of FFE coefficients C−r, . . . . C0, . . . and Cs, the CTLE preset CTLES, and the adjustable gain GS. Alternatively, in some implementations, the second modulation circuit350B includes the DFE342, and the second adjustable configuration506B includes a subset of the adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The first modulation circuit350A includes one of the FFE340, CTLE336, and the VGA338, and the first adjustable configuration506A includes a corresponding subset of the FFE preset of FFE coefficients C−r, . . . . C0, . . . and Cs, the CTLE preset CTLES, and the adjustable gain GS. Alternatively, in some implementations, the second modulation circuit350B includes the DFE342, and the second adjustable configuration506B includes a subset of the adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The first modulation circuit350A includes two or more of the FFE340, CTLE336, and the VGA338, and the first adjustable configuration506A includes a combination of two or more of the FFE preset of FFE coefficients C−r, . . . . C0, . . . and Cs, the CTLE preset CTLES, and the adjustable gain GS.

In some implementations, the sequence of modulation circuits350includes a DFE342and a VGA338, the VGA338having an adjustable gain GS. The DFE342has an adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The first modulation circuit350A includes the DFE342, and the first adjustable configuration506A includes a DFE coefficients h0. The second modulation circuit350B includes the VGA338, and the second adjustable configuration506B includes the adjustable gain GS.

In some implementations, the sequence of modulation circuits350includes an FFE340and a DFE342, the FFE340having an adjustable FFE preset of FFE coefficients C−r, . . . . C0, . . . and Cs. The DFE342has an adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The first modulation circuit350A includes the DFE342, and the first adjustable configuration506A includes a subset of the adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The second modulation circuit350B includes the FFE340, and the second adjustable configuration506B includes a first subset of the FFE preset of FFE coefficients C0, . . . and Cs. Further, in some implementations, the electronic device obtains a sequence of successive residual errors that immediately precedes the first residual error. The sequence of successive residual errors corresponds to a sequence of successive data samples that immediately precedes the first data sample. The electronic device adjusts a second subset of the FFE preset of FFE coefficients C−r, . . . , and C−1based on the sequence of successive residual errors and the first data sample.

In some implementations, the sequence of modulation circuits350includes a CTLE336and a DFE342, the CTLE336having an adjustable CTLE preset CTLES, the DFE342having an adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The first modulation circuit350A includes the DFE342, and the first adjustable configuration506A includes a subset of the adjustable DFE preset of DFE coefficients h1, . . . and hd. The second modulation circuit350B includes one of the CTLE336, and the second adjustable configuration506B includes the CTLE preset CTLES.

In some implementations, the sequence of modulation circuits350includes a DFE342having an adjustable DFE preset of DFE coefficients h0, h1, . . . and hd. The output data signal includes a sequence of successive data samples that starts with the first data sample, and every two successive data samples are delayed from each other by a unity delay. The electronic device adjusts the first adjustable configuration506A of the first modulation circuit350A further by adjusting an i-th DFE coefficients hibased on an (i+1)-th data sample of the sequence of successive data samples and the first residual error, where i is an integer equal to or greater than 0.

In some implementations, the first residual error412A of the first data sample502A includes a sign (e.g., “+” and “−”) of the first residual error412A, and the first adjustable configuration506A of the first modulation circuit350A is determined based on the sign of the first residual error412A and a value (e.g., “1” and “0”, which are represented as “+” or “−”) of a second data sample502B. The second data sample502B is optionally identical to or distinct from the first data sample502A. In an example, a DFE coefficient h1of the DFE342is adjusted based on the sign of a residual error of a postcursor sample502Q (h[1]) and a value (e.g., “1” and “0”, “+” or “−”) of the current sample502C.

It should be understood that the particular order in which the operations inFIG.11has been described are merely exemplary and are not intended to indicate that the described order is the only order in which the operations could be performed. One of ordinary skill in the art would recognize various ways to controlling clock data recovery for a data communication channel. Additionally, it should be noted that details of other processes and structures described above with respect toFIGS.1-10are also applicable in an analogous manner to method1100described above with respect toFIG.11. For brevity, these details are not repeated here.

In some implementations, method1100is, optionally, governed by instructions that are stored in a non-transitory computer readable storage medium and that are executed by one or more processors of the electronic device. Each of the operations shown inFIG.11may correspond to instructions stored in a computer memory or non-transitory computer readable storage medium. The computer readable storage medium may include a magnetic or optical disk storage device, solid state storage devices such as Flash memory, or other non-volatile memory device or devices. The instructions stored on the computer readable storage medium may include one or more of: source code, assembly language code, object code, or other instruction format that is interpreted by one or more processors. Some operations in method1100may be combined and/or the order of some operations may be changed.

It will also be understood that, although the terms first, second, etc. are, in some instances, used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first electronic device can be termed a second electronic device, and, similarly, a second electronic device can be termed a first electronic device, without departing from the scope of the various described implementations. The first electronic device and the second electronic device are both electronic device, but they are not the same electronic device.

The above description, for purpose of explanation, has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The implementations were chosen in order to best explain the principles underlying the claims and their practical applications, to thereby enable others skilled in the art to best use the implementations with various modifications as are suited to the particular uses contemplated.