INTERCALATED METAL/DIELECTRIC STRUCTURE FOR NONVOLATILE MEMORY DEVICES

Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

BACKGROUND

Many modern day electronic devices contain electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data when it is powered, while non-volatile memory is able to store data when power is removed. There are many different types of non-volatile memory that fall within the present disclosure, including Programmable Metallization Cell (PMC) Random Access Memory (RAM) (also referred to in some contexts as Conductive Bridge RAM (CBRAM)), Phase Change RAM (PCRAM), oxide based RAM (OxRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), etc. RRAM in particular is one promising candidate for a next generation non-volatile memory technology. RRAM has a simple structure, consumes a small cell area, has a low switching voltage and fast switching times, and is compatible with CMOS fabrication processes.

DETAILED DESCRIPTION

Resistive random access memory (RRAM) devices generally comprise a data storage dielectric layer, such as a high-κ dielectric layer or silicon dioxide layer, arranged between upper and lower conductive electrodes disposed within a back-end-of-the-line (BEOL) metallization stack. RRAM devices are configured to operate based upon a process of reversible switching between resistive states. This reversible switching is enabled by selectively forming (or breaking) a conductive filament through data storage dielectric layer. For example, a first bias condition can be applied over the upper and lower conductive electrodes to selectively form a conductive filament extending through the data storage dielectric layer, thereby putting the RRAM device in a low-resistance state. When a second voltage is applied, the conductive filament is removed and/or broken, thereby electrically isolating the upper and lower electrodes and putting the RRAM device in a high-resistance state. Thus, RRAM device can be switched between a first (e.g., low) resistance state, a second (e.g., high) resistance state, depending on the bias condition applied to the RRAM device.

Some aspects of the present disclosure lie in the appreciation that the data storage dielectric layer in typical RRAM devices is somewhat “thick” to provide adequate isolation between the upper and lower electrodes. This thickness of the data storage dielectric layer causes the conductive filament to take a long time to form, which causes slow performance. In some embodiments, a single “thin” film of data storage dielectric can separate the upper and lower electrodes from one another. However such a single thin film may be susceptible to reliability issues, such as voltage breakdown, particularly over a large number of read and write operations. Therefore, in some embodiments of the present disclosure, an intercalated metal/dielectric structure, which is made up of a number of thin data storage dielectric layers that alternate with a number of metal layers, is sandwiched between the upper electrode and the lower electrode. Because each data storage dielectric layer is “thin”, each is able to form a conductive filament there through in a relatively short period of time. Consequently, this intercalated metal/dielectric structure provides better reliability, and at the same time provides higher performance (e.g., faster write operations when forming conductive filaments) than other approaches. Further, it will be appreciated that although the present disclosure is set forth in the context of RRAM, that the intercalated metal/dielectric structure may also be utilized in other types of non-volatile memory, including Programmable Metallization Cell (PMC) Random Access Memory (RAM), Phase Change RAM (PCRAM), oxide based RAM (OxRAM), and Magnetic RAM (MRAM) for example.

FIGS.1A-1Billustrate a cross-sectional view of some embodiments of an integrated circuit100including resistive random access memory (RRAM) device having an intercalated metal/dielectric structure. The integrated circuit100includes a semiconductor substrate102with a back-end-of-line (BEOL) interconnect structure104disposed over the semiconductor substrate102. The BEOL interconnect structure104includes a number of metal layers that are arranged within a data storage dielectric structure106. For example, the illustrated metal layers include a lower metal line108and an upper metal line110, with an RRAM device112arranged between the lower metal line108and the upper metal line110. The RRAM device112includes a bottom electrode114which can be in direct contact with the lower metal line108, and an upper electrode116which can be in direct contact with the upper metal line110. Alternatively, a lower via and/or other structures (not shown) can couple the bottom electrode114to the lower metal line108, and/or an upper via and/or other structures (not shown) can couple the upper electrode116to the upper metal line110.

An intercalated metal/dielectric structure118is sandwiched between the bottom electrode114and the upper electrode116. The intercalated metal/dielectric structure118is made up of a number of thin dielectric layers that are stacked in alternating fashion with a number of metal layers. For example,FIGS.1A-1B's embodiment illustrates an intercalated metal/dielectric structure118comprising a lower dielectric layer120over the bottom electrode114, an upper dielectric layer122over the lower dielectric layer, and a first metal layer124separating the upper dielectric layer122from the lower dielectric layer120. AlthoughFIGS.1A-1Billustrate two dielectric layers (e.g.,120,122) separated from one another by a single metal layer (e.g.,124), any number of metal layers with intervening dielectric layers can be disposed between the bottom electrode and the upper electrode.

In some embodiments, the upper dielectric layer122and/or lower dielectric layer120comprise a high-κ dielectric material, such as a hafnium-based oxide (e.g., HfO2), a zirconium-based oxide (e.g., ZrO2), and/or a titanium-based oxide (e.g., TiO2). The high-κ dielectric material has a dielectric constant, K, that is greater than that of silicon dioxide; and thus the high-κ dielectric material has a dielectric constant of greater than about 3.9. In other embodiments, the upper dielectric layer122and/or lower dielectric layer120comprise silicon dioxide. In some embodiments, the first metal layer124comprises a conductive metal, such as copper, aluminum, tungsten, and/or alloys of these metals including ternary chalcogenides. The upper electrode116and the bottom electrode114comprise a metal, such as tantalum, tantalum nitride, titanium, or titanium nitride, for example.

In some embodiments, the overall thickness of the intercalated metal/dielectric structure118is less than 50 nm. Further, a ratio of tmetal:tdielectriccan be tuned during manufacturing; where tmetalis the total thickness of the sum of all the metal layers between the uppermost surface of the bottom electrode and the bottommost surface of the upper electrode, and where tdielectricis the total thickness of the sum of all the dielectric layers between the uppermost surface of the bottom electrode and the bottommost surface of the upper electrode. In some embodiments, tmetal:tdielectriccan range from approximately 1:10 to approximately 2:1.

In some embodiments, the dielectric layers of the intercalated dielectric/metal structure have different thicknesses from one another (though they can also be equal to one another); and the metal layers of the intercalated structure have different thicknesses from one another (though they can also be equal to one another). Further, the thicknesses of the dielectric layers are often different from the thicknesses of the metal layers. In some embodiments, the metal layers have individual thicknesses ranging from 1 nm to 50 nm, and the dielectric layers have individual thicknesses ranging from 0.5 nm to 5 nm. In some cases, each dielectric layer has a thickness that is less than or equal to 10 nm (or even less than or equal to 5 nm), as thicknesses greater than 10 nm may thwart or impair filament formation. In some cases, the metal layers can be made of copper alloys and have individual thicknesses that vary between 15 nm to 30 nm, which provides for good tradeoffs between manufacturing costs and quality. If higher quality and/or thinner metal layers are desired, atomic layer deposition (ALD) or other deposition techniques could be used.

Once manufacturing of the device is complete, a firing (or forming) voltage (Vff) can be applied to the cell to form the filament for the first time. After the filament is initially formed, then SET and RESET biases are used thereafter to write first and second data states to the cell (e.g., “1” and “0”). For example, the firing voltage can include a voltage of +10 V applied to the top electrode while a voltage of 0 V is applied to the bottom electrode for a time ranging from 10 ns to 1 μs, thereby causing the filament to initially form.

A first bias condition—a so-called SET bias—can be applied across the bottom electrode114and upper electrode116to put the RRAM device into a low-resistance state, wherein conductive filaments are formed to extend through the upper and lower dielectric layers as shown inFIG.1A. Thus, inFIG.1A, a lower conductive filament126extends from the bottom electrode114through the lower dielectric layer120and to the first metal layer124, and an upper conductive filament128extends from the first metal layer124through the upper dielectric layer122and to the upper electrode116. For example, in some embodiments, the first bias condition can be—for instance, top electrode (TE) at +10 V, bottom electrode (BE) at 0 V applied for a time of 10 ns.

When a second bias condition—a so-called RESET bias—is applied across the bottom electrode114and upper electrode116, at least a portion of the lower conductive filament (126inFIG.1A) and/or upper conductive filament (e.g.,128inFIG.1A) is removed or broken, such that the lower dielectric layer120and/or upper dielectric layer122fully separate bottom electrode114and the upper electrode116from one another, thereby putting the RRAM device in a high-resistance state such as shown inFIG.1Bfor example. Thus, inFIG.1B, at least a portion of the lower conductive filament is removed or broken so the lower dielectric layer120fully separates the bottom electrode114from the first metal layer124, and at least a portion of the upper conductive filament is removed or broken so the upper dielectric layer122fully separates the first metal layer124from the upper electrode116. For example, in some embodiments, the second bias condition can be—for instance, TE at 0 V, BE at +5 V applied for a time of 20 ns. Thus, by switching between the first bias condition and second bias condition, the RRAM device can be repeatedly and reliably switched between the low-resistance state (FIG.1A) and the high-resistance state (FIG.1B), for example, to act as a selector in a cross-bar memory array or to store data in an RRAM cell.

Compared to embodiments with only a single dielectric layer between the bottom electrode114and upper electrode116, having multiple dielectric layers (e.g., the lower dielectric layer120and upper dielectric layer122) provides shorter conductive filaments which are formed more quickly and at reduced voltages, allowing for faster switching times from the high-resistance state to the low-resistance state. Shorter conducting paths can also improve reliability.

FIGS.2A-2BthroughFIGS.4A-4Bshow various non-limiting examples of additional ways in which the intercalated metal/dielectric structure118can be implemented. Compared toFIGS.1A-1B, which illustrated a (single) first metal layer124disposed between a lower dielectric layer120and an upper dielectric layer122,FIGS.2A-2B through4A-4Bshow additional metal layer(s) and/or dielectric layer(s).

Turning now toFIGS.2A-2B, one can see some embodiments of an RRAM device200wherein the intercalated metal/dielectric structure118includes an upper dielectric layer122and a lower dielectric layer120. A first metal layer124is disposed between the upper dielectric layer122and the lower dielectric layer120. A second metal layer130is disposed over the upper dielectric layer122. The second metal layer130separates the upper dielectric layer12from the upper electrode116.FIG.2Aillustrates the RRAM device200in a high resistance state, whileFIG.2Billustrates the RRAM device200in a low-resistance state where conductive filaments131a,131bare present.

FIGS.3A-3Bshow an alternate embodiment of an RRAM device300wherein the intercalated metal/dielectric structure118again includes an upper dielectric layer122and a lower dielectric layer120. A first metal layer124is disposed between the upper dielectric layer122and the lower dielectric layer120. A second metal layer132is disposed over the bottom electrode114. The second metal layer132separates the bottom electrode114from the lower dielectric layer120.FIG.3Aillustrates the RRAM device300in a high resistance state, whileFIG.3Billustrates the RRAM device300in a low-resistance state where conductive filaments133a,133bare present.

FIGS.4A-4Bshow an alternate embodiment of an RRAM device400wherein the intercalated metal/dielectric structure118again includes an upper dielectric layer122and a lower dielectric layer120. A first metal layer124is again disposed between the upper dielectric layer122and the lower dielectric layer120. In this embodiment, a second metal layer134is disposed over the bottom electrode114. The second metal layer134separates the bottom electrode114from the lower dielectric layer120. A third metal layer136is disposed over the upper dielectric layer122. The third metal layer136separates the upper dielectric layer122from the upper electrode116.FIG.4Aillustrates the RRAM device400in a high resistance state, whileFIG.4Billustrates the RRAM device400in a low-resistance state where conductive filaments135a,135bare present.

Thus, as can be appreciated, the intercalated metal/dielectric structure118can take various forms depending on the implementation. AlthoughFIGS.1A-1B through4A-4Bshow some examples with two dielectric layers (e.g., an upper dielectric layer122and a lower dielectric layer120) and one, two, or three metal layers; in general, the intercalated metal/dielectric structure118can have any number of dielectric layers and any number of metal layers, which are stacked in alternating fashion with one another. Typically, the overall thickness of the intercalated metal/dielectric structure118is sufficiently thin that the RRAM device112can reside within a height corresponding to nearest neighboring metal lines. For example, in some embodiments, a height of the RRAM device can reside within a height measured from a lower metal line108(e.g., metal 3 line) and an upper metal line110(e.g., a metal 4 line). In some embodiments, the overall thickness of the intercalated metal/dielectric structure118is less than 50 nm. Further, a ratio of tmetal:tdielectriccan be tuned during manufacturing; where tmetalis the total thickness of the sum of all the metal layers between the uppermost surface of the bottom electrode and the bottommost surface of the upper electrode, and where tdielectricis the total thickness of the sum of all the dielectric layers between the uppermost surface of the bottom electrode and the bottommost surface of the upper electrode. In some embodiments, tmetal:tdielectriccan range from approximately 1:10 to approximately 2:1.

In some embodiments, the dielectric layers of the intercalated dielectric/metal structure have different thicknesses from one another; and the metal layers of the intercalated structure have different thicknesses from one another. Further, the thicknesses of the dielectric layers are often different from the thicknesses of the metal layers. In some embodiments, the metal layers have individual thicknesses ranging from 1 nm to 50 nm, and the dielectric layers have individual thicknesses ranging from 0.5 nm to 5 nm. In some cases, each dielectric layer has a thickness that is less than or equal to 10 nm (or even less than or equal to 5 nm), as thicknesses greater than 10 nm may thwart or impair filament formation. In some cases, the metal layers can be made of copper alloys and have individual thicknesses that vary between 15 nm to 30 nm, which provides for good tradeoffs between manufacturing costs and quality. If higher quality and/or thinner metal layers are desired, atomic layer deposition (ALD) or other deposition techniques could be used.

Although there is no limit to the number of metal layers and dielectric layers disposed between the bottom electrode and the upper electrode, in some cases it is advantageous to keep a maximum number of metal/dielectric periods to less than or equal to five (e.g., meaning five dielectric layers and five metal layers are arranged in alternating fashion between the bottom electrode and the upper electrode), because that maintains the speed of filament formation to levels similar to conventional approaches using a single (e.g., “thick”) dielectic layer.

In some embodiments, the upper dielectric layer122and lower dielectric layer120comprise a high-κ dielectric layer, such as a hafnium-based oxide (e.g., HfO2), a zirconium-based oxide (e.g., ZrO2), and/or a titanium-based oxide (e.g., TiO2). The high-κ dielectric layer has a dielectric constant, κ, of greater than that of silicon dioxide; and thus a high-κ dielectric layer has a dielectric constant of greater than 3.9. In some embodiments, the first metal layer (e.g.,124), the second metal layer (e.g.,130,132,134), and the third metal layer (e.g.,136) comprise a conductive metal, such as copper, aluminum, tungsten, and/or alloys of these metals including ternary chalcogenides. The upper electrode116and the bottom electrode114comprise a metal, such as tantalum, tantalum nitride, titanium, or titanium nitride, for example.

FIG.5Aillustrates a perspective view of some additional embodiments of an integrated chip including an array500of memory cells502arranged in rows and columns in a cross-bar configuration. The memory cells502are arranged in columns and rows, and for convenience, only some of the memory cells have been labeled502. Each memory cell502can be generally cylindrical-, conical-, frustrum-conical-, pyramidal-, frustrum-pyramidal-, pillar-, cube-, or prism-shaped, and can extend between a wordline (WL) and corresponding bitline (BL). The bit lines (BL) extend laterally along corresponding columns of the array and electrically couple with memory cells in the corresponding columns, whereas word lines (WL) extend laterally along corresponding rows of the array and electrically couple with memory cells in the corresponding rows. For clarity, the bit lines are respectively labeled BL1, BL2, . . . , and BLN, where the subscripts identify corresponding columns and N is an integer variable representing a column in the memory array. Similarly, for clarity, the word lines are respectively labeled WL1, WL2, and WLM, where the subscripts identify corresponding rows and M is an integer variable representing a row in the memory array.

By appropriately biasing a bit line and a word line, the memory cell at the cross point of the bit line and the word line may be selected and read from or written to. In some embodiments, the bias conditions have different polarities depending upon whether writing a first data state to a memory cell or a second data state to a memory cell. Further, the selectors of an unselected row have a sufficiently high resistance to prevent read and/or write disturbance to unselected memory cells sharing a bit line or a source line with the selected memory cell.

FIGS.5B-5Dshow various embodiments of memory cells502that include one or more RRAM devices which can be included inFIG.5A's architecture. As can be seen fromFIG.5B, for example, each memory cell502can include a bottom electrode114, a selector element505over the bottom electrode, an upper electrode116over the selector element505, a memory element504over the upper electrode116, and a top electrode506over the memory element504. The memory element504stores at least one bit of information, while the selector element505has a resistance that controls whether the memory element coupled to the selector element is written to and/or read to. The selector element505can include the intercalated metal/dielectric structure118previously described inFIGS.1-4, for example. Alternatively, as illustrated inFIG.5C, the selector element505can again include the intercalated metal/dielectric structure118and be formed over the memory element504. In some embodiments, the memory element504can also be implemented by using the intercalated metal/dielectric structure118. Thus,FIG.5Dshows an example where the memory element504and the selector element505each include an intercalated metal/dielectric structure118. Thus, in some embodiments, an RRAM device ofFIGS.1A-1B through4A-4Bcan be used as the selector element, which exhibits a reduced threshold voltage compared to other approaches. In other embodiments, an RRAM device ofFIGS.1A-1B through4A-4Bcan be used as the memory element to store one or more bits of data. The resistance of the memory element can be read to determine whether the memory cell is in the high-resistance state corresponding to a first logical value (e.g., a logical “0”, such as inFIG.1A) or whether the memory cell is in the low-resistance state corresponding to a second logical value (e.g., a logical “1”, such as inFIG.1B).

FIG.6illustrates a cross-sectional view of some additional embodiments of an integrated chip600that includes a semiconductor substrate602. The integrated chip comprises a memory region604, such as memory array500, and a logic region606arranged around an outer periphery of the memory region.

Transistors605and/or other active devices are arranged in or over the substrate. Each transistor includes a source/drain regions608that are separated by a channel region610. A gate electrode612overlies each channel region, and is separated from the channel region610by a gate dielectric614. Isolation structures616(e.g., shallow trench isolation structures) may be arranged in the semiconductor substrate602to provide isolation between neighboring transistor devices.

A back-end-of-line (BEOL) interconnect structure618is disposed over the semiconductor substrate602, and operably couples the transistors to one another. The BEOL interconnect structure618includes a dielectric structure with a plurality of conductive features disposed within the dielectric structure. The dielectric structure may comprise a plurality of stacked inter-level dielectric (ILD) layers620a-620f. In various embodiments, the plurality of ILD layers620a-620fmay comprise one or more dielectric materials, such as a low-k dielectric material or an ultra-low-k (ULK) dielectric material, for example. In some embodiments, the one or more dielectric materials may comprise SiO2, SiCO, a fluorosilicate glass, a phosphate glass (e.g., borophosphate silicate glass), etc. In some embodiments, etch stop layers (ESLs)622a-622emay be disposed between adjacent ones of the ILD layers620a-620f. For example, a first ESL622ais disposed between a first ILD layer620aand a second ILD layer620b, a second ESL622bis disposed between the second ILD layer620band a third ILD layer620c, etc. In various embodiments, the ESLs622a-622emay comprise a nitride, silicon carbide, carbon-doped oxide, or other similar materials.

A first conductive contact624aand a second conductive contact624bare arranged within the first ILD layer620a. The first conductive contact624ais electrically connected to a source/drain region of a transistor device in the memory region604, and the second conductive contact624bis electrically connected to source/drain region of a transistor device in the logic region606. In various embodiments, the first conductive contact624aand the second conductive contact624bmay be connected to a source region, a drain region, or a gate electrode of a transistor in the memory region or logic region. In some embodiments, the first conductive contact624aand the second conductive contact624bmay comprise tungsten, for example.

Alternating layers of metal interconnect wires626a-626eand metal vias628a-628dare disposed over the first conductive contact624aand the second conductive contact624b. The metal interconnect wires626a-626eand metal vias628a-628dcomprise a conductive material. In some embodiments, the metal interconnect wires626a-626eand metal vias628a-628dcomprise a conductive core630and a liner layer632that separates the conductive core from surrounding ILD layers. In some embodiments, the liner layer may comprise titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). In some embodiments, the conductive core may comprise copper and/or aluminum, for example.

A memory cell502, such as an RRAM device discussed inFIGS.1-5, is arranged between metal interconnect wire626cand an upper metal interconnect wire626ein the memory region604. Thus, in some embodiments, the memory cell502in the memory region604has an overall height that is sufficient to fit between nearest neighboring metal lines in the logic region606.

FIGS.7-13illustrate some embodiments of cross-sectional views700-1300showing a method of forming an IC comprising an RRAM device. Although the cross-sectional-views shown inFIGS.7-13are described with reference to a method of forming an RRAM device, it will be appreciated that the structures shown in the figures are not limited to the method of formation but rather may stand alone separate of the method.

As illustrated in cross-sectional view700ofFIG.7, a bottom electrode114is formed within a dielectric layer106over a semiconductor substrate102. In various embodiments, the semiconductor substrate102may comprise a semiconductor body (e.g., monocrystalline silicon, SiGe, silicon-on-insulator (SOI)) such as a semiconductor wafer and/or one or more die on a wafer, as well as any other type of metal layer, device, semiconductor and/or epitaxial layers, etc., associated therewith. The dielectric layer106is selectively etched to define a plurality of cavities within the dielectric layer106. The plurality of cavities are filled with a first conductive material to establish the bottom electrode114. In various embodiments, the first conductive material may comprise copper, tungsten, and/or aluminum, for example. In some embodiments, the first conductive material may be deposited by way of a plating process (e.g., an electro plating process, an electro-less plating process). In other embodiments, the first conductive material may be deposited using a vapor deposition technique (e.g., CVD, PVD, ALD, PE-ALD, etc.). In some embodiments, one or more liner layers (not shown) may be deposited within the plurality of cavities prior to filling the plurality of cavities with the first conductive material.

As illustrated in cross-sectional view800ofFIG.8, an intercalated metal/dielectric structure118is formed over the dielectric layer106. In some embodiments, intercalated metal/dielectric structure118may be formed by forming a lower dielectric layer120over the bottom electrode, a first metal layer124over the lower dielectric layer120, an upper dielectric layer122over the first metal layer124, and a second metal layer130over the upper dielectric layer122. An upper electrode layer116can then be formed over the second metal layer130. Other configurations can also be formed, for example, to establish the structures previously described inFIGS.1-5, for example.

In various embodiments, the bottom electrode114, the lower dielectric layer120, upper dielectric layer122, and the upper electrode116may be deposited using vapor deposition techniques (e.g., CVD, PVD, ALD, PE-ALD, etc.). In various embodiments the first and/or second metal layer are made of a metal, and are formed by sputtering, electroplating, electroless plating, or a vapor deposition technique, for example. In various embodiments, the bottom electrode114and the upper electrode116may comprise a metal nitride or a metal. For example, in some embodiments, the bottom electrode114and/or the upper electrode116may comprise a conductive material such as platinum (Pt), aluminum-copper (AlCu), titanium nitride (TiN), gold (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and/or copper (Cu), for example. In various embodiments, the lower dielectric layer120and upper dielectric layer122may comprise nickel oxide (NiO), titanium oxide (TiO), hafnium oxide (HfO), zirconium oxide (ZrO), zinc oxide (ZnO), tungsten oxide (WO3), aluminum oxide (Al2O3), tantalum oxide (TaO), molybdenum oxide (MoO), and/or copper oxide (CuO), for example. In various embodiments, the first metal layer124and/or second metal layer130comprise a conductive metal, such as copper, aluminum, tungsten, and/or alloys of these metals including ternary chalcogenides.

As illustrated in cross-sectional view900ofFIG.9, a memory element504and a top electrode layer506are formed over the intercalated metal/dielectric structure118(ofFIG.8). In some embodiments, the memory element504is a non-volatile memory (NVM) device, such as an RRAM device including one or more chalcogenide-based dielectric layers sandwiched between a pair of electrodes, but in other embodiments the memory element can take other forms, such as a phase-change memory element, or a metal-insulator-metal capacitor, for example. In some embodiments, the top electrode layer506and/or the upper electrode layer116may comprise a conductive material such as platinum (Pt), aluminum-copper (AlCu), titanium nitride (TiN), gold (Au), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and/or copper (Cu), for example. A hardmask902, such as a nitride hardmask or oxynitride hardmask, can be formed over the top electrode506.

As illustrated in cross-sectional view1000ofFIG.10, the intercalated metal/dielectric structure118(ofFIG.7) is patterned to define a patterned device structure. The patterned device structure comprises a bottom electrode114, a RRAM device112arranged over the bottom electrode114, and a top electrode506arranged over the RRAM device112. The RRAM device112can be generally cylindrical-, conical-, frustrum-conical-, pyramidal-, frustrum-pyramidal-, pillar-, cube-, or prism-shaped, and can extend between a wordline (WL) and corresponding bitline (BL).

As illustrated in cross-sectional view1100ofFIG.11, a dielectric liner1102may be formed over the on opposing sides of the patterned device structure. In some embodiments, sidewall spacers may be formed by etching back the dielectric liner1102, such that the dielectric liner is removed from horizontal surfaces, leaving the sidewall spacers along opposing sides of the patterned device structure. In various embodiments, the dielectric liner1102may comprise silicon nitride, a silicon dioxide (SiO2), silicon oxy-nitride (e.g., SiON), or a similar material.

As illustrated in cross-sectional view1200ofFIG.12, a second ILD layer104bis formed over the patterned device structure. The second ILD layer104bmay be formed by a vapor deposition technique (e.g., CVD, PVD, ALD, PE-ALD, etc.), spin on technique, or other technique.

As illustrated in cross-sectional view1300ofFIG.13, the second ILD layer104bis selectively etched to define a second plurality of cavities within the second ILD layer104b. In some embodiments, the second ILD layer104bmay be patterned by selectively exposing the second ILD layer104bto an etchant in areas not covered by a masking layer. The cavities are then filled with metal to establish a via1302coupled to the top electrode506, and an upper metal line1304over the via.

FIG.14illustrates a flow diagram of some embodiments of a method1400of forming an IC comprising an RRAM device having an upper electrode contacting an interconnect wire.

At1402, a lower interconnect structure is formed within a first inter-level dielectric (ILD) layer over a substrate. In various embodiments, the lower interconnect structure may comprise a bottom electrode, an interconnect contact, an interconnect via, or an interconnect wire.FIG.7illustrates some embodiments of a cross-sectional view700corresponding to act1402.

At1404, an intercalated metal/dielectric structure118is formed over the lower interconnect structure. The intercalated metal/dielectric structure comprises a lower dielectric layer, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer. An upper electrode can be formed over the intercalated metal/dielectric structure.FIG.8illustrates some embodiments of cross-sectional views800corresponding to act1404.

At1406, a memory element is formed over the upper electrode, and a top electrode is formed over the memory element.FIG.9illustrates some embodiments of a cross-sectional view900corresponding to act1406.

At1408, top electrode, memory element, upper electrode, and intercalated metal/dielectric structure are patterned.FIG.10illustrates some embodiments of a cross-sectional view1000corresponding to act1408.

At1410, a dielectric liner may be formed over and on opposing sides of the patterned structure of1408.FIG.11illustrates some embodiments of a cross-sectional view1100corresponding to act1410.

At1412, a second ILD layer is formed over dielectric liner.FIG.12illustrates some embodiments of a cross-sectional view1200corresponding to act1412.

At1414, an interconnect via is formed through the second ILD layer, and an upper metal line is formed over the interconnect via.FIG.13illustrates some embodiments of a cross-sectional view1300corresponding to act1414.

Thus, some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

Other embodiments relate to an integrated chip, comprising: a lower conductive interconnect structure surrounded by a first inter-level dielectric (ILD) layer and arranged over a substrate; a bottom electrode disposed over the lower interconnect structure; a top electrode disposed over the bottom electrode, the top electrode residing below the upper interconnect structure; and a plurality of metal layers and a plurality of dielectric layers stacked in alternating fashion over one another and sandwiched between the top and bottom electrode. Still other embodiments relate to a method. In the method, a lower interconnect structure is formed within a first inter-level dielectric (ILD) layer over a substrate. An intercalated metal/dielectric structure is formed over the lower interconnect structure. The intercalated metal/dielectric structure comprises a lower dielectric layer over the lower interconnect structure, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer. An upper electrode is formed over the intercalated metal/dielectric structure.