Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric

Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.

FIELD OF THE INVENTION

The present invention relates to nanoscale channel-based field effect transistor (FET) devices, such as nanowire FET devices, and more particularly, to techniques for defining a damascene gate in nanowire FET devices that surrounds the nanowire channel by replacing a patterned dielectric with a gate conductor material.

BACKGROUND OF THE INVENTION

The definition of a gate line over non-planar surfaces, and in particular forming a surrounding gate around a cylindrical surface, such as a nanowire channel, is challenging. In this regard, the gate definition process has several important requirements. First, the gate should have the same length (i.e., distance between source and drain regions) as it wraps around the cylindrical channel surface. To achieve uniform gate length, the gate needs to be patterned having straight sidewalls. For example, if the gate sidewalls are sloped then the top surface of the cylindrical channel would be covered by a shorter portion of the gate material as compared with the coverage of the bottom surface of the cylindrical channel. See, for example, S. Bangsaruntip et al., “High Performance and Highly Uniform Gate-All-Around Silicon Nanowire MOSFETs with Wire Size Dependent Scaling,” IEDM, Baltimore, Md. (2009) (hereinafter “Bansaruntip”) (FIG. 6(b) illustrates a gate with sloped sidewalls). Second, any gate conductor material outside of the channel region (including underneath the nanowire channels) has to be removed. This requirement is difficult to achieve with conventionally employed directional etching methods such as reactive ion etching (RIE) since the nanowires mask the etching of the gate conductor material underneath the nanowires. Third, the integrity of the nanowires outside of the gate region needs to be preserved during the patterning of the gate.

With regard to the third requirement, suspended nanowires are typically needed to fabricate a surrounding gate. The nanowires can be suspended, for example, by undercutting an insulator (such as a buried oxide (BOX)) below the nanowires. The gate material has to be deposited under the nanowires in order to obtain a surrounding gate. This suggests that to form a gate line one needs to etch past the nanowire and continue etching until the BOX is reached. Thus, during gate definition the etching has to continue even after gate dielectric on top of the nanowires is exposed (to clear the gate material around the nanowires) which can lead to severance of the nanowires due to a finite etch rate of the gate dielectric. Additionally, the gate dielectric is typically made very thin. As a result if the gate dielectric is removed, the nanowire body will be exposed and will also etch. If the etching is stopped once the gate dielectric is exposed, the definition of the gate line all around the nanowire would not be completed. By comparison, with a planar device the etching process can be stopped once the gate conductor material is cleared from the planar surfaces outside of the gate region since the definition of the gate line is complete at this point.

Current gate etching processes produce non-uniform gate lines over the nanowire surfaces, and can lead to severance of small diameter nanowires. Maintaining the integrity of the nanowires during RIE is even more challenging when the gate line is formed over a stacked (multi-layer) nanowire array. The top nanowires are exposed to continuous bombardment of ions until the bottom nanowires in the stack are cleared from the gate conductor material.

Therefore, techniques for forming a gate line with straight sidewalls, while maintaining the integrity of nanowires outside the gate line region, would be desirable.

SUMMARY OF THE INVENTION

The present invention provides techniques for defining a damascene gate in nanowire field-effect transistor (FET) devices that surrounds the nanowire channel by replacing a patterned dielectric with a gate conductor material. In one aspect of the invention, a method of fabricating a FET device is provided. The method includes the following steps. A silicon-on-insulator (SOI) wafer is provided having a SOI layer over a buried oxide (BOX). A plurality of nanowires and pads are patterned in the SOI layer with the pads attached at opposite ends of the nanowires in a ladder-like configuration. The BOX is recessed under the nanowires. At least one dummy gate comprising a patternable dielectric is formed over the recessed BOX and surrounding a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the at least one dummy gate comprise a channel region of the FET and wherein the pads and portions of the nanowires extending out from the at least one dummy gate comprise source and drain regions of the FET. A chemical mechanical polishing (CMP) stop layer is deposited over the at least one dummy gate and over the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the at least one dummy gate. The at least one dummy gate is at least partially removed so as to release the nanowires in the channel region. The at least one dummy gate is replaced with a gate conductor material.

In another aspect of the invention, another method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A stack of alternating layers of silicon germanium and silicon is deposited on the SOI layer. A plurality of fins and pads are patterned in the stack and the SOI layer with the pads attached at opposite ends of the fins in a ladder-like configuration. Portions of the silicon germanium layers from the fins are removed to form a plurality of nanowires in the SOI layer and in each of the silicon layers in the stack. The BOX is recessed under the nanowires. At least one dummy gate comprising a patternable dielectric is formed over the recessed BOX and surrounding a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the at least one dummy gate comprise a channel region of the FET and wherein the pads and portions of the nanowires extending out from the at least one dummy gate comprise source and drain regions of the FET. A CMP stop layer is deposited over the at least one dummy gate and over the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the at least one dummy gate. The at least one dummy gate is at least partially removed so as to release the nanowires in the channel region. The at least one dummy gate is replaced with a gate conductor material.

In yet another aspect of the invention, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX; a plurality of nanowires and pads patterned in the SOI layer with the pads attached at opposite ends of the nanowires in a ladder-like configuration, wherein the BOX is recessed under the nanowires; at least one gate over the recessed BOX and surrounding a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the at least one gate comprise a channel region of the FET and wherein the pads and portions of the nanowires extending out from the at least one gate comprise source and drain regions of the FET; a CMP stop layer over the source and drain regions; and a planarized dielectric film over the CMP stop layer.

In still yet another aspect of the invention, another FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX; a stack of alternating layers of silicon germanium and silicon on the SOI layer; a plurality of nanowires and pads patterned in the SOI layer and in each of the silicon layers in the stack, wherein the BOX is recessed under the nanowires; at least one gate over the recessed BOX and surrounding a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the at least one gate comprise a channel region of the FET and wherein the pads and portions of the nanowires extending out from the at least one gate comprise source and drain regions of the FET; a CMP stop layer over the source and drain regions; and a planarized dielectric film over the CMP stop layer.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Provided herein are techniques for forming a surrounding gate for a nanoscale channel-based field-effect transistor (FET), such as a nanowire FET, that do not use reactive ion etching (RIE) to define the gate structure. In particular, a sacrificial patternable dielectric combined with a damascene-based process is used to form the gate line therefore avoiding the problems described above.FIG. 1Ais a cross-sectional diagram illustrating a starting structure for the process that includes one or more nanowires104formed in a silicon-on-insulator (SOI) wafer. A SOI wafer typically includes a SOI layer over a buried oxide (BOX) and a substrate adjacent to a side of the BOX opposite the SOI layer. In the exemplary embodiment shown illustrated inFIG. 1A, a plurality of nanowires104with pads103attached at opposite ends thereof (seeFIG. 1B, described below) have been etched into the SOI layer, e.g., using conventional lithography and RIE processes. A BOX102(e.g., made up of silicon dioxide (SiO2)) and a substrate101are present beneath nanowires104/pads103.

Nanowires104are then suspended or released from BOX102by etching to recess BOX102under nanowires104. The result is a recessed BOX105over which nanowires104form a suspended bridge between SOI pads103. The recessing of BOX102can be achieved with a diluted hydrofluoric (DHF) etching. The lateral component of this etching undercuts BOX102under nanowires104. Alternatively, the suspension of nanowires104may be obtained during an annealing process used to reshape nanowires104(see below). The recessed BOX105is not limited to the region under nanowires104. The BOX around the pads is also recessed as shown inFIG. 1A. Only under regions covered by SOI the BOX will not recess (with the exception of the lateral etch that forms a SOI overhang). Accordingly, the oxide visible from a top-down view (see for exampleFIG. 1B, described below) is recessed BOX. For ease and clarity of depiction, however, in the following figures the image is cropped to an area surrounding the nanowires and pads.

While SOI substrates provide an easy path to define and suspend nanowires104, it is possible to obtain suspended nanowires using other substrates. By way of example only, a silicon germanium (SiGe)/Si film stack epitaxially grown on a bulk Si wafer (not shown) can also be patterned to form nanowires. The SiGe layer can be used as a sacrificial layer (analogous to BOX102) which is undercut to suspend the nanowires. The implementation of this alternate embodiment would be apparent to one of skill in the art. Additionally, stacked (multi-layer) nanowires can be obtained by epitaxially growing alternating layers of SiGe and Si over a bulk Si wafer or a SOI wafer as will be described in detail below.

FIG. 1Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 1A. As shown inFIG. 1B, nanowires104and pads103have a ladder-like configuration, i.e., with the nanowires connecting the pads much like rungs of a ladder. At this point in the process, each of the nanowires104has a rectangular cross-section that is set by the nanowire width w and the SOI layer thickness t (seeFIG. 1A).

FIG. 2Ais a cross-sectional diagram illustrating nanowires104having been reshaped to form reshaped nanowires108. Here, the reshaping refers to a smoothing of the surfaces of nanowires104to thereby change their respective cross-sections to be more cylindrical, and to a thinning of the nanowires (as shown inFIG. 2A) by moving Si from the nanowire bodies to the SOI pads (now referred to herein after the reshaping process as SOI pads103A). As an example, reshaped nanowires108may be formed by an annealing process during which the SOI wafer is contacted with an inert gas at a temperature, pressure and for a duration that is sufficient to cause Si to migrate from the nanowires to the SOI pads. Here, the term “inert gas” refers to a gas that does not react with Si and can include, but is not limited to, hydrogen (H2), xenon (Xe) and/or helium (He), and potentially others.

While in the exemplary embodiment shown release of the nanowires from the BOX has been achieved by undercutting the BOX using an etch, release of the nanowires from the BOX may also be achieved through the reshaping process. Namely, by giving the nanowires a more cylindrical cross-section, contact area between the nanowires and BOX is minimized. If the nanowires are also thinned then release from the BOX would be achieved.

FIG. 2Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 2A. Using the example wherein the wafer is annealed in H2gas, shortly before H2annealing, native oxide is etched off from the surfaces of nanowires104and SOI pads103. The annealing in H2smoothes the nanowire sidewalls and reshapes the nanowire cross-section from a rectangular cross-section to a more cylindrical cross-section. The H2anneal may also thin the nanowire bodies by re-distributing Si to the SOI pads.

According to an exemplary embodiment, the H2annealing may be performed with a gas pressure of from about 30 torr to about 1,000 ton, at a temperature of from about 600 degrees Celsius (° C.) to about 1,100° C. and for a duration of from about one minute to about 120 minutes. In general, the rate of Si re-distribution increases with temperature and decreases with an increase in pressure. For a discussion of the nanowire reshaping and thinning process see, for example, U.S. patent application Ser. No. 12/365,623 filed by Bangsaruntip et al., entitled “Maskless Process for Suspending and Thinning Nanowires,” the contents of which are incorporated by reference herein.

A dummy gate(s) is then formed over the recessed BOX and surrounding the nanowires. The dummy gate formation process begins by first depositing a patternable dielectric.FIG. 3Ais a cross-sectional diagram illustrating a patternable dielectric, such as hydrogen silsesquioxane (HSQ) film109, having been blanket deposited over the wafer using a spin-coating process. HSQ film109can be tailored to have a thickness HSQthicknessof from about three nanometers (nm) to about 300 nm.FIG. 3Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 3A. Other suitable patternable dielectrics, such as methyl-silsesquioxane (MSQ) may be used in the same manner. See, for example, Kuroki et al., “Characterization of Photosensitive Low-k Films Using Electron-Beam Lithography,” Electrochem. Soc., 152, G281 (2005), DOI:10.1149/1.1867632 and Kuroki et al., “Photosensitive Porous Low-K Interlayer Dielectric Film,” Proc. SPIE 5592, 170 (2005), DOI:10.1117/12.570753, the contents of each of which are incorporated by reference herein.

HSQ film109is then patterned to form a dummy gate.FIG. 4Ais a cross-sectional diagram illustrating HSQ film109having been patterned to form HSQ dummy gate110over recessed BOX105and surrounding reshaped nanowires108. HSQ film109(the patternable dielectric) can be patterned to form dummy gate110using, for example, electron-beam (e-beam) lithography or optical lithography. The unexposed portions of HSQ film109can be removed by a developer. The term “dummy gate” is being used herein since HSQ dummy gate110serves as a sacrificial gate that will be later replaced by a conductive gate material. HSQ dummy gate110masks a channel region of the FET (i.e., the portions of the nanowires surrounded by HSQ dummy gate110), while the exposed (unmasked) regions of nanowires108from which the HSQ was removed (and which extend out from the dummy gate) and pads103A will serve as source and drain regions of the FET.

Once patterned, HSQ dummy gate110is hardened by annealing. According to an exemplary embodiment, the dummy gate is annealed at a temperature of about 900° C. in nitrogen (N2) for a duration of 30 minutes. The hardened HSQ dummy gate has properties similar to thermal silicon dioxide (SiO2) (thermal oxide), with a similar etch rate in diluted hydrofluoric acid (HF). As an example, the etch rate of hardened HSQ is from about 2 nanometers per minute to about 3 nm/min in 100:1 diluted HF (which is the same for thermal SiO2). We further note that the hardening of HSQ can also be achieved by UV-curing and by plasma curing, or by a combination of these methods.FIG. 4Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 4A.

The wafer is then etched in diluted HF to remove any native oxide from the exposed regions of the nanowires, i.e., in the source and drain regions. According to an exemplary embodiment, the etching includes dipping the structure in 100:1 diluted HF (DHF) (the dilution is done with water (H2O)) for 60 seconds. Due to the hardening anneal, the hardened HSQ dummy gate etches very little (i.e., only about two nanometers (nm) of material is removed from the exposed surfaces of the hardened HSQ dummy gate) during this etch. Thus, the HSQ dummy gate110remains intact during this HF dip. If not hardened, the etch rate of spin-coated HSQ in HF is many times faster than that of thermal oxide.

Next, a selective growth of epitaxial Si, Ge or SiGe is performed in the source and drain regions to thicken (or even merge) portions of the nanowires extending out from the dummy gate. Specifically,FIG. 5Ais a cross-sectional diagram illustrating an epitaxial layer120having been selectively grown on reshaped nanowires108and SOI pads103A.FIG. 5Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 5A. As shown inFIGS. 5A and 5B, epitaxial layer120forms only over the exposed regions of Si nanowires108and SOI pads103A (including areas of the nanowires108and SOI pads103A exposed by recessed buried oxide105) due to growth selectivity on Si surfaces.

The epitaxial process used to form epitaxial layer120can merge the nanowires into a continuous block of Si, Ge or SiGe. Epitaxial layer120can be grown (formed) from a Si or Ge precursor in combination with an epitaxial growth method, such as ultra-high vacuum chemical vapor deposition (UHV-CVD), rapid thermal chemical vapor deposition (RT-CVD) and atomic layer deposition (ALD). Typical Si precursors for example include, but are not limited to, dichlorosilane (SiH2Cl2), silicon tetrachloride (SiCl4), a mixture of silane (SiH4) and hydrochloric acid (HCl). Growth of SiGe is obtained by co-flowing a Si precursor and a Ge precursor, such as SiCl4with germane (GeH4). A typical Ge precursor includes, but is not limited to, GeH4. The growth is selective in the sense that deposition of Si, Ge or SiGe takes place only over Si surfaces, but not over dielectric surfaces such as oxides and silicon-nitrides. While selective Si epitaxy typically requires growth temperatures of about 800° C., maintaining selectivity when using lower growth temperatures is possible by adding Ge to the epitaxial layer. With pure Ge growth, the growth temperature can be as low as 300° C. Low temperature growth of SiGe is useful in the case of very thin nanowires as a way to circumvent agglomeration. Agglomeration, which is undesirable, means that the nanowire breaks into balls wherein each ball is formed by collecting the Si material from a segment of the nanowire.

Self-aligned ion-implantation is then used to dope the source and drain regions. The process of self-aligned ion implantation is known to those of skill in the art and thus is not described further herein. For n-type doping, phosphorus (P) and/or arsenic (As) may be used as dopants, and for p-type doping, boron (B) and/or indium (In) may be used as dopants. Rapid thermal annealing (RTA) is used to activate the dopants and anneal out any implant damage. Doping of the source and drain regions may also be obtained by in-situ doping during the epitaxy of epitaxial layer120. When in-situ doping is used, a boron source such as diborane (B2H6) is added to the gas mixture to obtain p-type doping, while phosphine (PH3) is used to obtain n-type doping.

Nitride spacers are then formed on each sidewall of the dummy gate.FIG. 6Ais a cross-sectional diagram illustrating spacers121having been formed on the sidewalls of the HSQ dummy gate110. According to an exemplary embodiment, spacers121are formed by blanket depositing a silicon nitride (Si3N4) film over the wafer and etching by RIE to clear the Si3N4from all planer surfaces. Due to the directional etching, Si3N4will in this example remain under the portions of nanowires108extending outside HSQ dummy gate110(seeFIG. 6A).FIG. 6Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 6A.

A self-aligned silicide, germanide or germanosilicide (if epitaxial layer120includes Si, Ge or SiGe, respectively, see description ofFIG. 5A, above) is then formed over the source and drain regions.FIG. 7Ais a cross-sectional diagram illustrating a self-aligned silicide, germanide or germanosilicide122having been formed over the source and drain regions. More specifically, at least one metal, such as nickel (Ni), platinum (Pt), cobalt (Co) and/or titanium (Ti), is blanket deposited over the wafer. The assembly is annealed to allow the metal to react with the exposed Si, Ge or SiGe over the source and drain regions. The metal over non-Si, -Ge or -SiGe surfaces (e.g., the metal over spacers121and HSQ dummy gate110) remains unreacted. A selective etch is then used to remove the unreacted metal, leaving silicide, germanide or germanosilicide122over the source and drain surfaces.

As an example, in the case where Ni is used as the silicide forming metal, the lower resistivity silicide phase is nickel-silicon (NiSi). The NiSi phase forms at an annealing temperature of about 420° C., and the etch chemistry used to remove the unreacted metal is hydrogen peroxide:sulfuric acid (H2O2:H2SO4) 10:1 at 65° C. for 10 minutes. When epitaxial layer120also contains Ge (as in Si1-xGexor pure Ge) a germanosilicide or germanide alloy forms.

A planarizing film is then formed over the dummy gate and the source and drain regions. The planarizing film is used to planarize, i.e., to reduce the surface topography. SeeFIG. 7A. According to an exemplary embodiment, a chemical mechanical polishing (CMP) stop layer130(e.g., a silicon nitride (Si3N4) layer) is first deposited over the structure, i.e., over HSQ dummy gate110, spacers121and silicide, germanide or germanosilicide122. A thick dielectric film132is then deposited over CMP stop layer130. The dielectric film has to be thick enough to allow planarization by CMP. According to an exemplary embodiment, dielectric film132is made up of an oxide material and is from about 50 nm to about 300 nm thick.FIG. 7Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 7A.

Dielectric film132is then planarized.FIG. 8Ais a cross-sectional diagram illustrating the device after CMP has been used to planarize dielectric film132, resulting in a planarized dielectric film132A. As shown inFIG. 8A, this step also serves to expose a top of HSQ dummy gate110. It is notable that CMP stop layer130(which is not easily polished) allows the polishing pad to “land” on top of HSQ dummy gate110, with little material being removed from the stop layer by the CMP. After the CMP step, the exposed portion of CMP stop layer130topping HSQ dummy gate110is removed by a selective etch step, or by an additional CMP step with a different slurry that polishes CMP stop layer130.FIG. 8Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 8A.

The dummy gate is then removed.FIG. 9Ais a cross-sectional diagram illustrating the device after HSQ dummy gate110has been selectively etched out. The removal of HSQ dummy gate110forms a trench140and exposes the channel region portion of nanowires108.FIG. 9Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 9A. As can be seen fromFIG. 9B, nanowires are exposed in the channel region by the dummy gate removal. The etching (removal) of HSQ dummy gate110can be done using DHF (e.g., DHF 100:1) which is selective to nanowires108and spacer121. Etching with DHF will also remove some of the planarized dielectric film132A if oxide was used for planarization (i.e., if the dielectric film is made up of an oxide material), which will lead to the formation of an undesirable topography. This issue can be overcome as will be described in conjunction with the description ofFIGS. 16A-Band17A-B, below.

A replacement gate is then formed in place of the dummy gate.FIG. 10Ais a cross-sectional diagram illustrating a replacement gate150having been formed in place of the removed HSQ dummy gate110. First, however, a conventional deposition process with a suitable gate dielectric material is used to form gate dielectric151around the nanowires. By way of example only, gate dielectric151can be a thermal oxide or a high-k dielectric such as hafnium oxide (HfO2). A gate conductor material(s) (such as a suitable gate metal, or a combination of a metal gate capped with doped poly-Si) can be deposited over the structure filling trench140, thus forming replacement gate150. Any excess gate conductor material outside of trench140can be removed by CMP.

As a result of the present fabrication process, replacement gate150is formed having substantially straight sidewalls. The term “straight,” as used in the context of the gate herein refers to the vertical aspect of the sidewalls. Perfectly straight sidewalls would be perfectly vertical. InFIG. 10A, the straight sidewalls of replacement gate150are emphasized using dotted lines. By having straight sidewalls, the replacement gate defines substantially the same channel length in each of the nanowires. Channel length is defined as the distance between the source and the drain. Therefore, the top and bottom of the present gate structure have substantially the same length. This advantage is especially evident in the stacked nanowire configurations described below. Gate length and channel length are correlated as channel length, also the distance between the source and drain regions, is defined by the gate length. For illustrative purposes, by comparison, the gate shown in FIG. 6b of Bansaruntip (see above) has sloped sidewalls. As was described above, if the gate sidewalls are sloped (i.e., the gate length at the top of the gate is less than the gate length at the bottom of the gate) then the top surface of the nanowires would be covered by a shorter portion of the gate material as compared with the coverage of the bottom surface of the nanowires.

Accordingly, the term ‘substantially straight sidewalls’ can be quantified based on variation, if any, in the channel length as defined by the gate on any nanowire. For example, with perfectly straight/perfectly vertical sidewalls, there would be no variation in channel length within a given nanowire (i.e., from top-to-bottom as described above) or from one nanowire to another (e.g., in the stacked configuration). Within the context of the present teachings, the sidewalls of the gate are considered to be substantially straight if any resulting variation in the channel length within a given nanowire (i.e., from top-to-bottom as described above) or from one nanowire to another is less than 5 percent (%).FIG. 10Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 10A.

It is notable that full removal of HSQ dummy gate110is not needed as long as nanowires108are released (suspended). Suspending the channel region of nanowires108is needed to form a surrounding gate FET. Substantial over etch of HSQ dummy gate110is not desirable either as the etching will remove portions of BOX102. Since the etching is isotropic, extreme over-etching can lead to shorting of two adjacent gates formed on the same nanowire as will be shown in the examples discussed in reference toFIGS. 11A-Band12A-B, described below. With the formation of the replacement gate, the FET is now complete. Advantageously, since a dummy gate/replacement gate scheme is used with the present techniques, the integrity of the nanowires is preserved during the gate formation process.

Embodiments are also presented herein where multiple gates are formed on the same nanowires. For example,FIG. 11Ais a cross-sectional diagram illustrating a device having two dummy gates. The process flow used to form the structure shown inFIG. 11Ais the same as in the case of the single-gate discussed above, except here two dummy gates are formed. Accordingly, the structure shown inFIG. 11Aincludes a substrate1101, a BOX1102with recessed oxide1105, reshaped nanowires1108and SOI pads1103A (post nanowire reshaping) and HSQ dummy gates1110. HSQ dummy gates1110can be patterned (e-beam lithography or optical lithography) and hardened (annealed) in the same manner as described above. As with the single gate embodiment above, the patterning of the dummy gates defines the various regions of the device. Namely, the portions of reshaped nanowires surrounded by the HSQ dummy gates will serve as a channel region of the device, while the portions of reshaped nanowires extending out from the HSQ dummy gates and the SOI pads will serve as source and drain regions of the device.FIG. 11Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 11A.

Following the same process flow for the single-gate embodiment described above, spacers1121are formed on the sidewalls of the HSQ dummy gates, self-aligned silicide, germanide or germanosilicide1122is formed over the source and drain regions, a CMP stop layer1130is deposited over the structure, a thick dielectric film is deposited over the CMP stop layer and planarized to form planarized dielectric film1132A, the HSQ dummy gates are removed, a gate dielectric1151is formed around the nanowires in the channel region and the HSQ dummy gates are replaced with replacement gates1150. The details concerning each of these processes were presented above, and are incorporated by reference herein.

One notable point in this particular embodiment is that while in the case of the single gate full removal of the HSQ dummy gate is optional so long as the nanowires are released (see above), here full removal of the HSQ dummy gate may be undesirable.FIG. 12Ais a cross-sectional diagram illustrating replacement gates1150having been formed in place of HSQ dummy gates1110. As shown inFIG. 12A, HSQ dummy gates1110are not fully etched, i.e., HSQ dummy gates1110are partially etched, to avoid exposure of BOX1102. Over-etching of the HSQ dummy gates may lead to lateral (sideways) etching of BOX1102, which could in turn lead to a short of the two adjacent gates. The HSQ is therefore etched enough to release or suspend nanowires1108, with bottom portions1142of HSQ dummy gates1110left intact.

As a result of the present fabrication process, replacement gates1150are formed having substantially straight sidewalls (see, for example,FIG. 12A). As described above, by having straight sidewalls the replacement gates define substantially the same channel length in each of the nanowires.FIG. 12Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 12A.

The present techniques can also be applied to the case of stacked nanowires. Stacked nanowires are used to achieve higher circuit density. In this example, to begin the process, fins and pads made up of alternating layers of SiGe and Si are formed on a SOI wafer.FIG. 13Ais a three-dimensional diagram illustrating a starting structure for the stacked nanowire configuration. As shown inFIG. 13A, the SOI wafer includes a substrate1301, a BOX1302and a SOI layer1303. Alternating layers of SiGe and Si are epitaxially deposited over SOI layer1303. An SOI wafer is being used merely as an example since the alternating SiGe and Si layers could also be formed, e.g., on a bulk Si wafer. In the current example, SiGe layer1304is epitaxially grown over SOI layer1303, then Si layer1305is epitaxially grown over SiGe layer1304, then a second SiGe layer1306is epitaxially grown over Si layer1305and finally a second Si layer1307is epitaxially grown over SiGe layer1306. The growth of the stack of SiGe/Si layers1304to1307can be done in one growth step by alternating the flow of precursors used during deposition. For example, to grow the Si layers, a precursor such as SiH4is used, while for the growth of SiGe a mixture of SiH4and GeH4is used.

FIG. 13Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 13A. In the exemplary embodiment shown illustrated inFIGS. 13A and 13B, a plurality of fins1308with pads1309attached at opposite ends thereof have been etched into the stack of layers1303to1307, e.g., using conventional lithography and RIE processes. As shown inFIG. 13B, the fins1308and pads1309have a ladder-like configuration, i.e., with the fins connecting the pads much like rungs of a ladder.

The portions of the SiGe layers in the fins are then removed leaving the portions of the Si layers in the fins to form suspended nanowires. In other words, after etching and removal of the SiGe from the fins each Si layer in the stack (including the SOI layer) has a ladder-like pad-nanowire configuration patterned therein like that shown, for example, inFIG. 13B. Vertically, the pad-nanowire “ladders” are separated from one another by the SiGe remaining in the “pad” areas.FIG. 14Ais a cross-sectional diagram illustrating selective etching of SiGe having been used to form a stack of suspended nanowires1310. As an example, hot gaseous HCL etching can be used to etch SiGe. The etching is followed by an inert gas annealing (such as H2annealing) to reshape and smooth nanowires1310(as was described in detail above). Similar to the case of a single-layer of nanowires, BOX1302can be recessed using DHF, resulting in recessed BOX1311. Alternatively, a wet etch of 1 HF:2 H2O2:3 CH3COOH (hydrofluoric acid, hydrogen peroxide and acetic acid) can be used to selectively etch SiGe with respect to Si.FIG. 14Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 14A.FIG. 15Ais a cross-sectional diagram illustrating an HSQ dummy gate1512having been formed surrounding the stack of nanowires. HSQ dummy gate1512can be patterned (e-beam lithography or optical lithography) and hardened (annealed) in the same manner as described above. As with the embodiments above, the patterning of the dummy gate defines the various regions of the device. Namely, the portions of reshaped nanowires1310surrounded by the HSQ dummy gate will serve as a channel region of the device, while the portions of reshaped nanowires1310extending out from the HSQ dummy gate and the pads will serve as source and drain regions of the device. In this configuration, the pads in the layers together form collective source and drain regions.FIG. 15Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 15A.

The rest of the process flow remains the same as in the embodiments presented above. Namely, spacers1521are formed on the sidewalls of the HSQ dummy gate, self-aligned silicide, germanide or germanosilicide1522is formed over the epitaxially thickened source and drain regions, a CMP stop layer1530is deposited over the structure, a thick dielectric film is deposited over the CMP stop layer and planarized (to form planarized dielectric film1532A), the HSQ dummy gate is removed, a gate dielectric1551is formed around the nanowires and the HSQ dummy gate is replaced with replacement gate1550. The details concerning each of these processes were presented above, and are incorporated by reference herein.FIG. 15Cis a cross-sectional diagram illustrating the completed device.

As highlighted above, full removal of the HSQ dummy gate is optional so long as the nanowires are released (see above). Thus, as shown inFIG. 15CHSQ dummy gate1512is not fully etched to expose BOX1302. This is done to prevent over-etching of the HSQ dummy gate. The HSQ is therefore etched enough to release or suspend the nanowires, with a bottom portion1520of the HSQ dummy gate left intact.

As a result of the present fabrication process, replacement gate1550is formed having substantially straight sidewalls. As described above, by having straight sidewalls, the replacement gate defines substantially the same channel length in each of the nanowires. Therefore, the top and bottom of the present gate structure have substantially the same length. This advantage is especially evident with regard to this example involving stacked nanowires. Specifically, if the sidewalls of the gate were sloped, like in conventional devices, then the channel length (defined by the gate length, see above) at the top of the stack would be significantly shorter than the channel length at the bottom of the stack, which is very disadvantageous.

In this embodiment, as with all of the other embodiments described herein, the replacement gate underlaps the pads. Specifically, the replacement gate surrounds each of the nanowires but does not extend over (does not overlap) the pads. Accordingly, as highlighted above, the portions of the nanowires surrounded by the replacement gate will serve as a channel region of the device, while the portions of the nanowires extending out from the replacement gate and the pads will serve as source and drain regions of the device.

The device may be considered complete at this point. However, as was explained above, the etching of the HSQ dummy gate by DHF may also lead to the etching of planarized dielectric1532A when the dielectric is an oxide. This result is disadvantageous. Therefore, in the particular embodiment shown inFIG. 15C, a second CMP stop layer1534is optionally formed on top of planarized dielectric1532A. Corresponding source contact1524, gate contact1526and drain contact1528are also formed. This aspect of the present techniques used to counteract the effects of the dielectric etching during dummy gate removal is described in further detail below.FIG. 15Dis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 15C.

As was explained in reference toFIG. 9A, and elsewhere above, the etching to remove the dummy gate by DHF may also lead to the etching of the planarized dielectric when the dielectric is an oxide. To overcome this issue a second CMP stop layer (e.g. formed of Si3N4) is used. See, for example,FIG. 16A.FIG. 16Ais a cross-sectional diagram illustrating a device, formed according to the present techniques, having an optional second CMP stop layer. Up to the formation of the second CMP stop layer, the process flow remains the same as with the single-gate, single nanowire layer embodiment presented above. Namely, a plurality of nanowires with pads attached at opposite ends thereof are etched into an SOI layer over a BOX1602and a substrate1601. The nanowires are suspended or released from BOX1602and then reshaped, to form reshaped nanowires1610and SOI pads1603A. An HSQ dummy gate is formed around the nanowires. Spacers1621are formed on the sidewalls of the HSQ dummy gate. Self-aligned silicide, germanide or germanosilicide1622is formed over the epitaxially thickened source and drain regions. A CMP stop layer1630is deposited over the structure, a thick dielectric film is deposited over the CMP stop layer and planarized to form planarized dielectric film1632A. The details concerning each of these processes were presented above, and are incorporated by reference herein.

With this embodiment, however, after planarization of the dielectric film, a second CMP stop layer1670is blanket deposited over the structure. Second CMP stop layer1670is patterned to expose a top portion of the HSQ dummy gate. The HSQ dummy gate is etched out, a gate dielectric1651is formed and the HSQ dummy gate is replaced with replacement gate1650. The details concerning formation of the gate dielectric and replacing the HSQ dummy gate with a replacement gate were presented above, and are incorporated by reference herein. A second CMP step is used to remove excess gate conductor deposited over the second CMP stop layer1670. The structure following the second CMP step is shown inFIG. 16A.

As a result of the present fabrication process, replacement gate1650is formed having substantially straight sidewalls. As described above, by having straight sidewalls, the replacement gate defines substantially the same channel length in each of the nanowires. Therefore, the top and bottom of the present gate structure have substantially the same length.FIG. 16Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 16A.

Source and drain contacts are then formed. A gate contact may also be formed. For example,FIG. 17Ais a cross-sectional diagram illustrating contacts having been formed to the gate and source and drain regions, respectively. The source and drain contacts are formed by etching a trench (also known as via) through second CMP stop layer1670, dielectric film1632A and CMP stop layer1630and then filling the trenches with metal such as tungsten to form conductive vias1702and1704. The metal forms a contact to the silicide, germanide or germanosilicide1622. Metal lines1774and1776may then be patterned to contact the top portion of the metal in the vias that are connecting to the source and the drain. Since the top portion of the gate is exposed there is no need for a via to access the gate. Accordingly, a metal line1772is patterned to contact the gate.FIG. 17Bis a diagram illustrating another perspective, i.e., a top-down view, of the structure ofFIG. 17A.