Semiconductor device

According to one embodiment, a semiconductor device includes a first differential amplifier and a second differential amplifier. The first differential amplifier charges the first output terminal with a second voltage different from a first voltage. The first differential amplifier uses a first clock signal, stopping the charging at the first output terminal, receives first complementary data of the first voltage at the rising edge of a second clock signal, and outputs the first complementary data at the second voltage. The second differential amplifier charges the second output terminal with the second voltage. The second differential amplifier uses a third clock signal, stopping the charging at the second output terminal, receives second complementary data of the first voltage at the rising edge of a fourth clock signal, and outputs the second complementary data at the second voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Applications No. 2013-058940, filed Mar. 21, 2013; and No. 2013-059026, filed Mar. 21, 2013, the entire contents of all of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device able to operate at high speeds, more particularly to a data output circuit for use in the semiconductor device.

BACKGROUND

In a semiconductor device such as a dynamic RAM or a NAND flash memory, it is desired that the clock signal should have a duty ratio of 50% in order to output data at high speed, i.e., double data rate (DDR) in accordance with the clock signal. If the duty ratio deviates from 50%, a sufficient margin can hardly be acquired, and the data cannot be correctly output easily.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device includes a first differential amplifier and a second differential amplifier. The first differential amplifier charges the first output terminal with a second voltage different from a first voltage. The first differential amplifier uses a first clock signal, stopping the charging at the first output terminal, receives first complementary data of the first voltage at the rising edge of a second clock signal, and outputs the first complementary data at the second voltage from the first output terminal. The second differential amplifier charges the second output terminal with the second voltage. The second differential amplifier uses a third clock signal, stopping the charging at the second output terminal, receives second complementary data of the first voltage at the falling edge of a fourth clock signal, and outputs the second complementary data at the second voltage from the second output terminal.

In most data output circuits configured to output data at DDR (i.e., high speed), complementary clock signals REOLATe and REOLATo that determine the timing of outputting data are supplied via a phase splitter to a clocked inverter circuit. The phase splitter adds a phase shift to the complementary clock signals REOLATe and REOLATo. Since the complementary clock signals REOLATe and REOLATo are independent of each other, a phase difference between them, if any resulting from, for example, line delay cannot be corrected. Further, since the clocked inverter circuit receives the output data, high data is output at one through rate, and low data is output at another through rate. Still further, the data output from the clocked inverter circuit is supplied to an output driver transistor through a level shifter, the level shifter changes or skews the duty ratio of the data, inevitably degrading the characteristic of the data output circuit.

First Embodiment

FIG. 1shows a data output circuit according to a first embodiment, which is configured to output data at DDR.

The data output circuit comprises a first differential amplifier11, a second differential amplifier12, a third differential amplifier13, a fourth differential amplifier14, a level converter15, a multiplexer16, and a fifth differential amplifier17.

The third differential amplifier13and the fourth differential amplifier14receives a clock signal REOLATe and a clock signal REOLATo, respectively, as complementary signals. Clock signals REOLATe and REOLATo are signals of a first voltage, such as VDD-level signals.

The third differential amplifier13generates a clock signal from clock signals REOLATe and REOLATo. The clock signal is supplied, as a VDD-level clock signal clked, to the first differential amplifier11through inverter circuits21,22and23.

The fourth differential amplifier14generates a clock signal from clock signals REOLATe and REOLATo. This clock signal is supplied, as a VDD-level clock signal clkod, to the second differential amplifier12through inverter circuits24,25and26.

Clock signal clked and clock signal clkod are signals complementary to each other.

The output terminals of inverter circuits21and24are connected to the level converter15. The level converter15converts a VDD-level clock signal to a clock signal of second voltage, for example, VCCQ level different from VDD level. That is, VCCQ level is may be higher than the VDD level in one case, or may be lower than the VDD level in another case.

The level converter15comprises a plurality of P-channel MOS transistors (hereinafter called “PMOS transistors”) P1to P6and a plurality of N-channel MOS transistors (hereinafter called “NMOS transistors”) N1and N2. The current paths of PMOS transistors P1and P2are connected, at one end, to two nodes, respectively, to which power-supply voltage VCCQ is applied.

The other end of the current path of PMOS transistor P1is grounded by PMOS transistors P3and P4connected in parallel and by an NMOS transistor N1. The gates of PMOS transistor P1and NMOS transistor N1are connected to the output terminal of inverter circuit24.

The other end of the current path of PMOS transistor P2is grounded by PMOS transistors P5and P6connected in parallel and by an NMOS transistor N2. The gates of PMOS transistor P2and NMOS transistor N2are connected to the output terminal of inverter circuit21.

The gates of PMOS transistor P3and t P5receive a signal Φ. The signal Φ is at 0 V if the power-supply voltage VCCQ is, for example, 1.8 V and is 3.3 V if the power-supply voltage VCCQ is 3.3 V.

The gate of PMOS transistor P6is connected to the connection node of PMOS transistors P3and P4. From the connection node, a VCCQ-level clock signal clkeq is output and supplied to the first differential amplifier11.

The gate of PMOS transistor P4is connected to NMOS transistor N2and to the connection node of PMOS transistors P5and P6. From this connection node, a VCCQ-level clock signal clkoq is output. The VCCQ-level clock signal clkoq is supplied to the second differential amplifier12.

The VCCQ-level clock signal clkeq and the VCCQ-level clock signal clkoq are signals complementary to each other.

The first differential amplifier11and the second differential amplifier12are identical in configuration. Therefore, the configuration of only the first differential amplifier11will be described. The components of the second differential amplifier12, which are identical to those of the first differential amplifier11, will be designated by the same reference numbers.

The current path of PMOS transistor P11is connected, at one end, to a node to which the power-supply voltage VCCQ is applied. The other end of the current path of PMOS transistor P11is grounded by NMOS transistors N11, N12and N15.

The current path of PMOS transistor P12is connected, at one end, to a node to which the power-supply voltage VCCQ is applied. The other end of the current path of PMOS transistor P12is grounded by NMOS transistors N13, N14and N15.

Data DTe and data BDTe which are complementary to each other are supplied to the gates of NMOS transistors N12and N14, respectively.

The current paths of PMOS transistors P13and P14connected in parallel to each other are connected, at one end, to the node to which the power-supply voltage VCCQ is applied. The other ends of PMOS transistors P13and P14are connected by PMOS transistor P15to the gate of PMOS transistor P11and the gate of NMOS transistor N11.

The current paths of PMOS transistors P16and P17connected in parallel are connected, at one end, to a node to which the power-supply voltage VCCQ is applied.

PMOS transistors P16and P17are connected, at the other end, by PMOS transistor P18, respectively to the gate of PMOS transistor P12and the gate of NMOS transistor N13.

PMOS transistors P19and P20are connected in series between the gate of PMOS transistor P12and the gate of PMOS transistor P11. PMOS transistor P21is connected between the connection node of PMOS transistors P19and P20and the gate of PMOS transistor11.

The connection node of PMOS transistor P12and NMOS transistor N13is output terminal OUTe of the first differential amplifier11. The connection node is connected to the gate of PMOS transistor P11and to the gate of NMOS transistor N11.

The connection node of PMOS transistor P11and NMOS transistor N11is the inverting output terminal BOUTe of the first differential amplifier11. This connection node is connected to the gate of PMOS transistor P12and to the gate of NMOS transistor N13.

A signal Φ is supplied to the gates of PMOS transistors P13, P16and P21.

A clock signal clkeq output from the level converter15is supplied to the gates of PMOS transistors P14, P17and P20.

A clock signal clked is supplied to the gate of NMOS transistor N15and to the gates of PMOS transistors P15, P18and P19.

In the second differential amplifier12, clock signal clkoq is supplied to the gates of PMOS transistors P14, P17and P20. Clock signal clkod is supplied to the gate of NMOS transistor N15and to the gates of PMOS transistors P15, P18and P19. Data DTo is supplied to the gate of NMOS transistor N14. Data BDTo is supplied to the gate of NMOS transistor N12.

The connection node of PMOS transistor P11and NMOS transistor N11is output terminal OUTo of the second differential amplifier12. The connection node is connected to the gate of PMOS transistor12and to the gate of NMOS transistor N13.

The connection node PMOS transistor P12and NMOS transistor N13is the inverting output terminal BOUTo of the second differential amplifier12. This connection node is connected to the gate of PMOS transistor11and to the gate of NMOS transistor N11.

The multiplexer16comprises a plurality of inverter circuits I1to I4, PMOS transistors P31to P34configuring a transfer gate, NMOS transistors N21to N24, and a latch circuit LT.

PMOS transistors P31and P32connected in parallel, and NMOS transistors N21and N22connected in parallel are connected in series between ground and a node to which the power-supply voltage VCCQ is applied. Further, PMOS transistors P33and P34connected in parallel, and NMOS transistors N23and N24are connected in parallel are connected in series between ground and the node to which the power-supply voltage VCCQ is applied.

Output node OUTe of the first differential amplifier is connected to the gate of PMOS transistor P32, and also to the gate of NMOS transistor N24by inverter circuit I1.

Output node BOUTe of the first differential amplifier is connected to the gate of PMOS transistor P33, and also to the gate of NMOS transistor N21by inverter circuit I2.

Output node BOUTo of the second differential amplifier is connected to the gate of PMOS transistor P31, and also to the gate of NMOS transistor N23by inverter circuit I3.

Output node OUTo of the second differential amplifier is connected to the gate of PMOS transistor P34, and also to the gate of NMOS transistor N22by inverter circuit I4.

The connection node of PMOS transistors P33and P34and NMOS transistors N23and N24is first output terminal A of the multiplexer16. The connection node of PMOS transistors P31and P32and NMOS transistors N21and N22is second output terminal B of the multiplexer16. Latch circuit LT is connected between the first output terminal A and the second output terminal B.

Output terminals A and B of the multiplexer16are connected to the two input terminals of the differential amplifier17. The two output terminals of the differential amplifier17are connected to a PMOS drive transistor (not shown) and an NMOS driver transistor (not shown), respectively.

How the first differential amplifier11, second differential amplifier12and multiplexer16operate in the configuration described above will be explained with reference toFIG. 2.

The first differential amplifier11outputs data DTe and BDTe (even-numbered data) in accordance with clock signals clkeq and clked. The second differential amplifier12outputs data DTo and BDTo (odd-numbered data) in accordance with clock signals clkoq and clkod.

Clock signals clkeq and clkoq are complementary to each other. Clock signals clked and clkod are complementary to each other. Clock signals clkeq and clked are of the same phase, and clock signal clked is delayed a little with respect to clock signal clkeq. Clock signals clkoq and clkod are of the same phase, and clock signal clkod is delayed a little with respect to clock signal clkoq.

As shown inFIG. 2, clock signals clkeq and clked are low at time t1. Therefore, PMOS transistors P14, P15, P17, P18, P19and20are on in the first differential amplifier11. Since NMOS transistor N15is off, NMOS transistors N11to N14are off. As a result, output node OUTe is charged to the VCCQ level via PMOS transistors P13and P15, and output node BOUTe is charged to the VCCQ level via PMOS transistors P17and P18.

At this point, clock signals clkoq and clkod are high. PMOS transistors P14, P15, P17, P18, P19and P20are off and NMOS transistor N15is on, in the second differential amplifier12. PMOS transistors P11and P12and NMOS transistors N11, N12, N13and N14are driven by data signals DTo and BDTo that are complementary to each other. If data DTo and BDTo are high and low, respectively, PMOS transistor P11and NMOS transistors N13and N14will be on, whereas PMOS transistor P12and NMOS transistors N11and N12will be off. In this case, output terminals OUTo and BOUTo of the second differential amplifier12are high (VCCQ) and low (VSS), respectively.

Thereafter, at time t2, clock signal clkeq goes high. Then, PMOS transistors P14, P15, P17, P18, P19and P20are turned off in the first differential amplifier11, stopping the charging at both output node OUTe and BOUTe.

At this point, clock signal clkoq is low. PMOS transistors P14, P15, P17, P18, P19and P20are turned on in the second differential amplifier12, starting the charging at both output nodes OUTo and BOUTo.

Next, at time t3, clock signal clked goes high. NMOS transistor N15is turned on in the first differential amplifier11. At this point, data DTe is low, and data BDTe is high. NMOS transistor N12is therefore turned off, and NMOS transistor N14is turned on. Output terminal OUTe is therefore electrically discharged via NMOS transistors N13, N14and N15, and is made low. As output terminal OUTe is made low, PMOS transistor P11is turned on. Output terminal OUTe therefore is kept high.

At time t3, output terminals OUTo and BOUTo of the second differential amplifier12are held charged (high).

In the multiplexer16, output terminal OUTe of the first differential amplifier11is low, output terminal BOUTe thereof is high, and output terminals OUTo and BOUTo of the second differential amplifier12are both high. Therefore, PMOS transistor P31is off, PMOS transistor P32is on, and NMOS transistors N21and N22are off. PMOS transistors P33and P34are off, NMOS transistor N23is off, and NMOS transistor N24is on. As a result, NMOS transistor N24makes output terminal A of the multiplexer16low, and PMOS transistor P32makes output terminal B of the multiplexer16high. This state is held by the latch circuit LT. That is, the latch circuit LT holds the even-numbered data “e1.”

The data output from output terminals A and B of the multiplexer16is supplied to the differential amplifier17. The differential amplifier17outputs a signal, which is supplied to a PMOS drive transistor (not shown) and a NMOS drive transistor (not shown).

Next, at time t4, clock signal clkoq goes high. PMOS transistors P14, P15, P17, P18, P19and P20of the second differential amplifier12are therefore turned off, stopping the charging at output nodes OUTo and BOUTo.

At this point, clock signal clkeq goes low. PMOS transistors P14, P15, P17, P18, P19and P20of the first differential amplifier11are therefore turned on, starting the charging at output nodes OUTe and BOUTe.

Then, at time t5, clock signal clkod goes high.

NMOS transistor N15of the second differential amplifier12is therefore turned on. At this point, data DTo is low, and data BDTo is high. Therefore, NMOS transistor N14is turned off and NMOS transistor N12is turned on. Output terminal BOUTo of the second differential amplifier12therefore stays high, and the charge is released from output terminal OUTo via NMOS transistors N11, N12and N15. Output terminal OUTo is thereby made low. At time t5, output terminals OUTe and BOUTe of the first differential amplifier11are held in a charged state (high).

In the multiplexer16, PMOS transistors P31, P32and P33are off and PMOS transistor P34is on, because output terminals OUTo of the second differential amplifier12is low, and output terminal BOUTo is high, whereas output terminals OUTe and BOUTe of the first differential amplifier11are high. Further, NMOS transistors N21, N23and N24are off, and NMOS transistor N22is on in the multiplexer16. Hence, output terminal A of the multiplexer16is made high by PMOS transistor P34, and output terminal B of the multiplexer16is made low by NMOS transistor N22. The latch circuit LT holds this state, holding odd-numbered data “o1.”

The data output from output terminals A and B of the multiplexer16is supplied to the differential amplifier17, which outputs a signal. This signal is supplied to the PMOS drive transistor (not shown) and to the NMOS drive transistor (not shown).

Advantages of the First Embodiment

In the first embodiment, the first differential amplifier11receives even-numbered complementary data DTe and BDTe at the rising edge of clock signal clked, and the second differential amplifier12receives odd-numbered complementary data DTo and BDTo at the rising edge of clock signal clkod. Thus, the first and second differential amplifiers11and12receive the even-numbered complementary data and the odd-numbered complementary data, respectively on the rising edges of clock signals clked and clkod. This can suppress not only the phase difference between the complementary data items, but also the phase difference between the even-numbered data and the odd-numbered data.

That is, if a data item is received at the rising edge of a clock signal and another data item is received at the falling edge of the clock signal, the rising edge and falling edge of the clock signal will be received by an NMOS transistor and a PMOS transistor, respectively. In this case, these data items may likely have a phase difference because the NMOS transistor and the PMOS transistor differ in current-driven ability.

By contrast, in this embodiment, clock signals clkeq, clked, clkoq and clkod are supplied to NMOS transistors of the first and second differential amplifiers11and12. Hence, the NMOS transistors have the same current-driven ability (namely, a very small difference in current-driven ability). Therefore, a phase difference can hardly exist between the even-numbered data and the odd-numbered data.

In this embodiment, the first differential amplifier11receives the complementary data DTe and BDTe, and the second differential amplifier12receives the complementary data DTo and BDTo. The duty ratio of the output data can therefore be approximated to 50%. As seem fromFIG. 3, an output circuit of ordinary type, for example, may acquire data at the intermediate level of the data signal. If so, the duty ratio of the data will not be 50% if the signal rises and falls with a delay, as indicated by lines T1and T2inFIG. 3. In this embodiment, the data is acquired at the rising edges of the complementary clock signals if the first and second differential amplifiers11and12receive the complementary data. Therefore, the duty ratio of the output data can approach 50% as indicated by line T3inFIG. 3, even if the signal rises and falls with some delay. A sufficient margin can therefore be ensured in high-speed operation.

Further, in the first and second differential amplifiers11and12, output terminals OUTe and BOUTe and output terminals OUTo and BOUTo are charged to VCCQ higher than VDD while clock signals clkeq and clkoq stay low. When clock signals clkeq and clkoq go high, the charging at output terminals OUTe and BOUTe and output terminals OUTo and BOUTo is stopped. At the rising edges of clock signals clked and clkod, the first and second differential amplifiers11and12receive VDD-level data DTe, BDTe, DTo, and BDTo, and output VCCQ-level data. Thus, the first and second differential amplifiers11and12have the function of a level shifter. This avoids such a phase difference between the complementary data items, as will occur if level shifters are used. If a level shifter except the differential amplifier is used, a phase difference between the complementary data items will occur.

Still further, clock signals REOLATe and REOLATo are supplied to the third differential amplifier13, and also to the fourth differential amplifier14. Therefore, the third and fourth differential amplifiers13and14can cancel the phase difference between clock signals REOLATe and REOLATo.

Second Embodiment

FIG. 4shows the second embodiment. InFIG. 4, the components identical to those of the first embodiment are designated by the same reference numbers.

In the first embodiment described above, data is output from, for example, the first differential amplifier11, output terminals OUTe and BOUTe of the first differential amplifier11are then electrically charged, and the data is output from the second differential amplifier12. Due to, for example, the changes in manufacturing conditions, however, it may take much time to charge output terminals OUTe and BOUTe. In this case, the charging output terminals OUTe and BOUTe of the first differential amplifier11may interfere with the data outputting from the second differential amplifier12. Some margin is required between the completion of charging and the outputting of complementary data.

In view of this, the time between the completion of charging and the outputting of the complementary data is shortened in the second embodiment, thereby to output data at a speed higher than otherwise.

The second embodiment differs from the first embodiment in the configuration of the multiplexer16.

The current path of PMOS transistor P41is connected, at one end, to a node to which the power-supply voltage VCCQ is applied. To the gate of PMOS transistor P41, a clock signal clkod is supplied. The other end of PMOS transistor P41is connected to one end of the series circuit composed of PMOS transistor P42and NMOS transistor N41, and also to one end of the series circuit composed of PMOS transistor P43and NMOS transistor N42. The other end of the series circuit composed of PMOS transistor P42and NMOS transistor N41, and the other end of the series circuit composed of PMOS transistor P43and NMOS transistor N42are grounded by NMOS transistor N43. To the gate of NMOS transistor N43, a clock signal clked is supplied.

The current path of PMOS transistor P44is connected, at one end, to the node to which the power-supply voltage VCCQ is applied. To the gate of PMOS transistor P44, a clock signal clked is supplied. The other end of PMOS transistor P44is connected to one end of the series circuit composed of PMOS transistor P45and NMOS transistor N44, and also to one end of the series circuit composed of PMOS transistor P46and NMOS transistor N45. The other end of the series circuit composed of PMOS transistor P45and NMOS transistor N44, and the other end of the series circuit composed of PMOS transistor P46and NMOS transistor N45are grounded by NMOS transistor N46. To the gate of NMOS transistor N46, a clock signal clkod is supplied.

The gate of PMOS transistor P42is connected to output terminal OUTe of the first differential amplifier11. The gate of PMOS transistor43is connected to output terminal BOUTe of the first differential amplifier11. The gate of PMOS transistor P45is connected to output terminal BOUTo of the second differential amplifier12. The gate of PMOS transistor46is connected to output terminal OUTo of the second differential amplifier12.

The gate of NMOS transistor N41is connected by an inverter circuit I12to output terminal BOUTe of the first differential amplifier11. The gate of NMOS transistor N42is connected by an inverter circuit I11to output terminal OUTe of the first differential amplifier11. The gate of NMOS transistor N44is connected by an inverter circuit I14to output terminal BOUTo of the second differential amplifier12. The gate of NMOS transistor N45is connected by an inverter circuit I13to output terminal OUTo of the second differential amplifier12.

The latch circuit LT is connected, at one end, to the connection node of PMOS transistor P43and NMOS transistor N42, and also to the connection node of PMOS transistor P46and NMOS transistor N45. The other end of the latch circuit LT is connected to the connection node of PMOS transistor P42and NMOS transistor N41, and also to the connection node of PMOS transistor P45and NMOS transistor N44.

The first output terminal A and second output terminal B of the multiplexer16are connected to two input terminals of a differential amplifier17. The two output terminals of the differential amplifier17are connected to a PMOS drive transistor (not shown) and an NMOS transistor (not shown), respectively.

How the configuration described above operates will be explained below.

In the multiplexer16, clock signal clkod goes high and clock signal clked goes low, to receive odd-numbered complementary data from, for example, the second differential amplifier12. As a result, PMOS transistor P41and NMOS transistor N43are turned off, whereas PMOS transistor P44and NMOS transistor N46are turned on. Therefore, Outputs terminals OUTe and BOUTe of the first differential amplifier11are not selected, and the latch circuit LT latches the odd-numbered complementary data output from output terminals OUTo and BOUTo of the second differential amplifier12.

To output the even-numbered complementary data from, for example, the first differential amplifier11, clock signal clkod goes low, and clock signal clked goes high. Therefore, PMOS transistor P44and NMOS transistor N46are turned off, whereas PMOS transistor P41and NMOS transistor N43are turned on. Hence, output terminals OUTo and BOUTo of the second differential amplifier12are not selected, the latch circuit LT latches the even-numbered complementary data output from output terminals OUTe and BOUTe of the first differential amplifier11.

In the second embodiment, the multiplexer16does not select output terminal OUTo or BOUTo of the second differential amplifier12, in accordance with clock signals clked and clkod, in order to output data from the first differential amplifier11, and do not select output terminal OUTe or BOUTe of the first differential amplifier11in order to output data from the second differential amplifier12. This can prevent the data output from the multiplexer16from being interfered due to a delay of charging, even if the charging time differs between the first and second differential amplifiers11and12. Hence, the shift of the duty ratio can be more suppressed than otherwise, and no margin need be set between the completion of charging and the outputting of data. Thus, the data can be output at high speed.

Third Embodiment

(Third and Fourth Differential Amplifiers13and14)

The third and fourth differential amplifiers13and14used in the first and second embodiments are differential amplifiers in which the through current is controlled. The third and fourth differential amplifiers13and14are identical in configuration. Therefore, the configuration of only the third differential amplifier13will be described with reference toFIG. 5. As parenthesized inFIG. 5, the signals REOLATe and REOLATo input to the fourth differential14are other way around with respect to the third differential amplifier13.

As shown inFIG. 5, the third differential amplifier13comprises first and second current-mirror amplifiers CDA1and CDA2. The first and second current-mirror amplifiers CDA1and CDA2are configured by current-mirror type differential amplifiers. The third differential amplifier13has PMOS transistors P101to P105, NMOS transistors N101to N105, inverter circuits I101and1103, and constant current sources CI1and CI2.

In the first current-mirror amplifier CDA1, the current paths of PMOS transistors P101and P102configuring a current mirror are connected, at one end, to a node to which the power-supply voltage VDD is applied. The gates of PMOS transistors P101and P102are connected to the other end of the current path of PMOS transistor P101. The current paths of PMOS transistors P101and P102are connected, at the other end, to one end of the current path of NMOS transistor N101and the one end of the current path of NMOS transistor N102, respectively. The current paths of NMOS transistors N101and N102are connected, at the other end, to ground by NMOS transistor N103and constant current source CI1.

The first input signal (for example, clock signal REOLATe) is supplied to the gate (inverting input terminal BIN) of NMOS transistor N101through inverter circuit I101. The second input signal (for example, clock signal REOLATo) is supplied to the gate (inverting input terminal IN) of NMOS transistor N102through inverter circuit I103.

The first input signal is supplied also to the gate of NMOS transistor N103.

In the second current-mirror amplifier CDA2, constant current source CI2is connected, at one end, to a node to which the power-supply voltage VDD is applied, and at the other end, to one end of the current path of PMOS transistor P103. The other end of PMOS transistor P103is connected to one end of the current path of PMOS transistor P104and also to one end of the current path of PMOS transistor P105. The current paths of PMOS transistors P104and P105are connected, at the other end, to the NNOS transistors N104and N105that configure a current mirror circuit, more precisely to one end of the current path of the NNOS transistor N104and one end of the current path of NMOS transistor N105, respectively. The gates of NMOS transistors N104and N105are connected to one end of the current path of NMOS transistor N104. The current paths of NMOS transistors N104and N105are connected, at the other end, to ground.

The first input signal (for example, clock signal REOLATe) is supplied to the gate of PMOS transistor P103.

The gate of PMOS transistor P104is connected to the inverting input terminal BIN. The gate of PMOS transistor P105is connected to the input terminal IN.

The connection node of PMOS transistor P102and NNOS transistor N102, and the connection node of PMOS transistor P105and NMOS transistor N105are connected to output terminal OUT.

In the third differential amplifier13so configured as described above, the first and second current-mirror amplifiers CDA1and CDA2operate as the first and second input signals REOLATe and REOLATo transition between high and low or low and high. The first and second current-mirror amplifiers CDA1and CDA2stop operating when the first and second input signals REOLATe and REOLATo finish rising or falling.

As shown inFIG. 6A, at time t1, the first input signal REOLATe goes low and the second input signal REOLATo may go high. Then, NMOS transistor N103of the first current-mirror amplifier CDA1is turned off. As a result, the first constant current source CI1becomes inoperative, and PMOS transistor P103of the second current-mirror amplifier CDA2is turned on. The second constant current source CI2therefore becomes operative. PMOS transistor P105is thereby turned on, and output terminal OUT goes high. At this point, the inverting input terminal BIN stays high, and PMOS transistor P104is off. The connection node of PMOS transistor P104and NMOS transistor N104, which is connected to the gates of NMOS transistors N104and N105, is therefore held at a potential equal to the threshold voltage of NMOS transistor N104. NMOS transistors N104and105are therefore turned off, preventing a through current from flowing also in the second current-mirror amplifier CDA2.

At time t2, the first input signal REOLATe may go high and the second input signal REOLATo may go low. Then, NMOS transistor N103of the first current-mirror amplifier CDA1is turned on. Therefore, the first constant current source CI1become operative, and PMOS transistor P103of the second current-mirror amplifier CDA2is thereby turned off. The second constant current source CI2therefore becomes inoperative. At this point, the inverting input terminal BIN stays low and the non-inverting input terminal IN stays high. NMOS transistor N101is turned off, NMOS transistor N102is turned on, and PMOS transistor P105is turned on. As a result, output terminal OUT is made low. The inverting input terminal BIN stays low at this point, and NMOS transistor N101is off. Therefore, PMOS transistor P101and the connection node of PMOS transistor P101and NMOS transistor N101, which is connected to the gate of PMOS transistor P102are held at a potential lower than the power-supply voltage VDD by the threshold voltage of PMOS transistor P101. PMOS transistors P101and P102are therefore turned off, preventing a through current from flowing also in the first current-mirror amplifier CDA1.

As shown inFIG. 6B, the rising and falling edges of the first input signal REOLATe may shift with respect to those of the second input signal REOLATo. Even in this case, the output potential of the first current-mirror amplifier CDA1or second current-mirror amplifier CDA2is determined when the first and second input signals REOLATe and REOLATo become identical in terms of level.

Therefore, through current flows in the first and second current-mirror amplifiers CDA1and CDA2when a potential difference is made between the first and second input signals REOLATe and REOLATo while the first and second input signals REOLATe and REOLATo are changing in terms of level. Thus, any through current is prevented from flowing in the normal state (i.e., high-impedance state).

According to the third embodiment, the first and second current-mirror amplifiers CDA1and CDA2have, each an NMOS transistor N103and a PMOS transistor P103connected in series to the first and second constant current sources CI1and CI2, respectively, and NMOS transistor N103and PMOS transistor P103are controlled by the first input signal REOLATe. Therefore, the first and second constant current sources CI1and CI2start operating at the same time when the first input signal REOLATe transitions between low and high or high and low, and one of the first and second constant current sources CI1and CI2is stopped when the first input signal REOLATe goes high or goes low. The other of the first and second constant current sources CI1and CI2can indeed be operative. However, no tail currents flow in the other constant current source, because NMOS transistors N101and N102or PMOS transistors P104and P105, configuring a differential pair, are turned off. Hence, the third differential amplifier13consumes current when the first input signal REOLATe goes high or low. The current consumption can therefore be achieved in the normal operating state. Thus, a through current flows in the first and second current-mirror amplifiers CDA1and CDA2when the first and second input signals REOLATe and REOLATo change in level, and no through currents flow in the normal state (i.e., high-impedance state).

Fourth Embodiment

FIG. 7shows a fourth embodiment. InFIG. 7, the components identical to those of the third embodiment are designated. Only the components different from those of the third embodiment will be explained below.

As shown inFIG. 7, an NMOS transistor N106is connected in parallel to an NMOS transistor N103. PMOS transistor P103is connected in parallel to a PMOS transistor P106. An inverter circuit I102is connected to output terminal OUT. The signal output from inverter circuit I102is supplied to the gate of an NMOS transistor N106and to the gate of PMOS transistor P106.

In the fourth embodiment, the output signal is fed back to NMOS transistor N106and PMOS transistor P106. Therefore, NMOS transistors N103and N106can enhance the current-driven ability of the first constant current source CI1when the first input signal REOLATe goes high. This can improve the balance when the output signal transitions between low and high or high and low.

Further, an NMOS transistor N103and PMOS transistors P106can enhance the current-driven ability of the second constant current source CI2when the first input signal REOLATe goes low. This can improve the balance when the output signal transitions between low and high or high and low.

Hence, the speed balance can be improved as the output signal transitions between high and low or low and high.

Fifth Embodiment

FIG. 8shows is a circuit diagram showing an example of the fifth differential amplifier17. This fifth differential amplifier17is a modification of the third and fourth differential amplifiers13and14. The fifth differential amplifier17differs from the differential amplifier ofFIG. 7, in that its current-driven ability is variable and that it is applied to an off-chip driver (OCD) circuit. InFIG. 8, the components identical to those shown inFIG. 7are designated by the same reference numbers. Only the components different from those shown inFIG. 7will be explained below.

The OCD shown inFIG. 8comprises first to fourth current-mirror amplifiers CDA1to CDA4. The third and fourth current-mirror amplifiers CDA3and CDA4are identical to the first and second current-mirror amplifiers CDA1and CDA2, except for the control signals used. Therefore, only the first and second current-mirror amplifiers CDA1and CDA2will be described as for configuration, and the third and fourth current-mirror amplifiers CDA3and CDA4will be described, as for only the components different from those of the first and second current-mirror amplifiers CDA1and CDA2.

The circuit ofFIG. 8differs from that ofFIG. 7, in that the first and second current-mirror amplifiers CDA1and CDA2have three constant current sources each, and that these constant current sources can be selected by using a switch.

In the first current-mirror amplifier CDA1, NMOS transistor N111, constant current source CI11, a series circuit composed of NMOS transistor N112and constant current source CI12, and a series circuit composed of NMOS transistor N113and constant current source CI13are connected between ground, on one hand, and NMOS transistors N103and N106, on the other.

A control signal ByPn is supplied to the gate of NMOS transistor N111. A control signal SWPn1is supplied to the gate of NMOS transistor N112. A control signal SWPn2is supplied to the gate of NMOS transistor N113.

In the second current-mirror amplifier CDA2, PMOS transistor P111, constant current source CI21, a series circuit composed of constant current source CI22and PMOS transistor P112, and a series circuit composed of constant current source CI23and PMOS transistor P113are connected between the node to the node applied with the power-supply voltage VDD, on one hand, and PMOS transistors P103and P105, on the other.

A control signal ByPp is supplied to the gate of PMOS transistor P111. A control signal SWPp1is supplied to the gate of PMOS transistor P112. A control signal SWPp2is supplied to the gate of PMOS transistor P113.

The third and fourth current-mirror amplifiers CDA3and CDA4which are configured by current-mirror type differential amplifies, differ from the first and second current-mirror amplifiers CDA1and CDA2, in terms of control signals used.

That is, in the third current-mirror amplifier CDA3, control signal ByNn is supplied to the gate of NMOS transistor N111, control signal SWNn1is supplied to the gate of NMOS transistor N112, and control signal SWNn2is supplied to the gate of NMOS transistor N113.

In the fourth current-mirror amplifier CDA4, control signal ByNp is supplied to the gate of PMOS transistor P111, control signal SWNp1is supplied to the gate of NMOS transistor P112, and control signal SWNp2is supplied to the gate of PMOS transistor P113.

The first input signal B and the second input signal A are complementary to each other. The first input signal B is supplied via an inverter circuit I113to the first to fourth current-mirror amplifiers CDA1to CDA4. The second input signal A is supplied via inverter circuits I111and I112to the first to fourth current-mirror amplifiers CDA1to CDA4. Between inverter circuit I111and inverter circuit I112, the gates of NMOS transistor N115and PMOS transistor P115are connected. NMOS transistor N115and PMOS transistor P115configure a MOS capacitor. The MOS capacitor delays the second input signal A by the same time the first input signal B is delayed.

The signals output from the first and second current-mirror amplifiers CAD1and CAD2are supplied via an inverter circuit I114to PMOS drive transistors (not shown). The signals output from the third and fourth current-mirror amplifiers CAD3and CAD4are supplied via inverter circuit I114to NMOS drive transistors (not shown).

While the first to fourth current-mirror amplifiers CDA1to CDA4are operating, NMOS transistor N111and PMOS transistor P111are set to off state by control signals ByPn, ByPp, ByNn and ByNp. Constant current source CI11and constant current source CI21are therefore operated.

In this state, the circuit ofFIG. 8outputs signals OUT_P and OUT_N generated by inverting the input signal A.

Control signals SWPn1, SWPn2, SWPp1and SWPp2, SWNn1, SWNn2, SWNp1and SWNp2may be controlled independently of each other, in response to commands. Then, the first to fourth current-mirror amplifiers CDA1to CDA4are independently adjusted, in terms of current driven ability. Output signal OUT_P and output signal OUT_N can therefore be adjusted independently in terms of rising and falling and high-impedance period. Hence, the duty ratio of output signal OUT_P and that of output signal OUT_N can be adjusted.

Each embodiment described above can, of course, be applied not only to NAND flash memories and DRAM-data output circuits, but also to any other semiconductor device that should operate at high speed.

Like the first and fourth embodiments, the fifth embodiment can shut a tail current while the input signal stays in normal state, thereby to reduce the current consumption.

Moreover, in the fifth embodiment, control signals SWPn1, SWPn2, SWPp1and SWPp2, SWNn1, SWNn2, SWNp1and SWNp2can control the number of constant current sources (CI11to CI13and CI21to CI23) driven, thereby to adjust the total current-driven ability of the first to fourth current-mirror amplifiers CDA1to CDA4. The rising and falling and high-impedance period of output signal OUT_P and those of output signal OUT_N can therefore be adjusted, ultimately to adjust the duty ratios of output signals OUT_P and OUT_N.

Further, the duty ratio can be set nearly to 50% in the fifth embodiment. A sufficient effective-data time for which to latch data can therefore be acquired. If the fifth embodiment is applied to a DDR-data output circuit, the circuit can reliably operate at high speed.

In the third and fourth embodiments, the first and second constant current sources CI1and CI2may be adjusted in current-driven ability by control signals as in the fifth embodiment.