SEMICONDUCTOR PACKAGE

A semiconductor package includes: a first semiconductor chip including a first pad on a first substrate, and a first insulating layer at least partially surrounding the first pad; and a second semiconductor chip including a second pad below a second substrate and contacting the first pad, and a second insulating layer at least partially surrounding the second pad and contacting the first insulating layer. The first pad includes a first surface contacting the second pad and a second surface opposite the first surface, and an inclined side surface between the first surface and the second surface. The inclined side surface includes a first side surface and a second side surface, facing each other and inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively. Each of the first and second obtuse angles is about 100° to about 130°.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based on and claims priority to Korean Patent Application No. 10-2022-0117648, filed on Sep. 19, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

Embodiments of the present disclosure relate to a semiconductor package.

As demand for high capacity, thinness, and miniaturization of electronic products increases, various types of semiconductor packages are being developed. Recently, as a method for integrating more components (e.g., semiconductor chips) into a package structure, a direct bonding technology for bonding semiconductor chips without an adhesive film (e.g., a non-conductive film (NCF)) or a connection bump (e.g., a solder ball) has been developed.

SUMMARY

An aspect of the present disclosure is to provide a semiconductor package having improved reliability.

According to an aspect of the present disclosure, a semiconductor package includes: a first semiconductor chip including a first substrate, a first pad on the first substrate, and a first insulating layer at least partially surrounding the first pad on the first substrate; and a second semiconductor chip on the first semiconductor chip, and including a second substrate, a second pad below the second substrate and contacting the first pad, and a second insulating layer at least partially surrounding the second pad and contacting the first insulating layer, wherein the first pad includes a first surface contacting the second pad and a second surface opposite the first surface, and an inclined side surface between the first surface and the second surface, wherein the inclined side surface includes a first side surface and a second side surface, facing each other and inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively, and wherein each of the first and second obtuse angles is about 100° to about 130°.

According to an aspect of the present disclosure, a semiconductor package includes: a first semiconductor chip including a first substrate, a first pad on the first substrate, and a first insulating layer at least partially surrounding the first pad on the first substrate; and a second semiconductor chip on the first semiconductor chip, and including a second substrate, a second pad below the second substrate and contacting the first pad, and a second insulating layer at least partially surrounding the second pad and contacting the first insulating layer, wherein the first pad includes a first surface contacting the second pad, a second surface opposite the first surface, and a first side surface between the first surface and the second surface and inclined with respect to the second surface at a first obtuse angle, and the second pad includes a third surface contacting the first pad, a fourth surface opposite the third surface, and a second side surface between the third surface and the fourth surface and inclined with respect to the fourth surface at a second obtuse angle, wherein each of the first and second obtuse angles is about 100° to about 130°.

According to an aspect of the present disclosure, a semiconductor package includes: a first semiconductor chip including a first substrate, a first pad on the first substrate, a first insulating layer at least partially surrounding the first pad on the first substrate, an insulating protective layer between the first substrate and the first insulating layer, a through-electrode extending through the first substrate and the insulating protective layer and connected to the first pad, and a buffer film on the insulating protective layer and spaced apart from the through-electrode; and a second semiconductor chip on the first semiconductor chip, and including a second substrate, a second pad below the second substrate and contacting the first pad, and a second insulating layer at least partially surrounding the second pad and contacting the first insulating layer, wherein the first pad includes a first surface contacting the second pad and a second surface opposite the first surface; and an inclined side surface between the first surface and the second surface, wherein the first pad has a first side surface and an opposite second side surface inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively, and wherein each of the first and second obtuse angles is about 100° to about 130°.

DETAILED DESCRIPTION

FIG.1Ais a cross-sectional view illustrating a semiconductor package according to an embodiment, andFIG.1Bis a partially enlarged view illustrating portion ‘A’ ofFIG.1A.

Referring toFIG.1A, a semiconductor package10according to an embodiment may include a plurality of semiconductor chips, for example, a first semiconductor chip100and a second semiconductor chip200, stacked in a vertical direction (a Z-axis direction). In the first semiconductor chip100and the second semiconductor chip200, an upper surface of the first semiconductor chip100and a lower surface of the second semiconductor chip200may be directly joined and bonded (which, for example, may be referred to as hybrid bonding, direct bonding, or the like) without a connection member such as a metal bump or the like. A first insulating layer151and first upper pads152, which provide the upper surface of the first semiconductor chip100, may be joined and bonded to a second insulating layer231and second lower pads232, which provide the lower surface of the second semiconductor chip200, respectively. The first semiconductor chip100may be electrically connected to the second semiconductor chip200by bonding pad structures BP in which the first upper pads152and the second lower pads232are joined.

The present disclosure may prevent occurrence of defects of the first upper pads152and the second lower pads232, in a process of forming the first upper pads152and the second lower pads232, by adjusting angles formed between a first surface152uand first and second side surfaces152aand152bin each of the first upper pads152, and/or angles formed between a fourth surface2321and third and four side surfaces232aand232bin each of the second lower pads232. Through this, a semiconductor package10with improved reliability may be provided.

For example, at least a portion of the first insulating layer151may be located on a side surface of the first upper pad152, and at least a portion of the second insulating layer231may be located on a side surface of the second lower pad232. In this case, the at least portion of the first insulating layer151may be in contact with the at least portion of the second insulating layer231. Therefore, the side surface of the first upper pad152and the side surface of the second lower pad232may be entirely covered or surrounded with the first and second insulating layers151and231. In this case, to distinguish positions of components in the first semiconductor chip100or the second semiconductor chip200, the “first insulating layer” and the “second insulating layer” may be referred to as a “first upper insulating layer” or “first rear insulating layer,” and a “second lower insulating layer” or “second front insulating layer,” respectively. Also, the “first upper pad” and the “second lower pad” may be referred to as a “first pad” or “first rear pad,” and a “second pad” or “second front pad,” respectively.

Hereinafter, components in the first semiconductor chip100and the second semiconductor chip200will be described in detail with reference toFIG.1Btogether withFIG.1A.

The first semiconductor chip100may include a first substrate110, a first circuit layer120, a first through-electrode140, a first insulating layer151, and a first upper pad152. The first semiconductor chip100may have a flat upper surface provided by an upper surface of the first insulating layer151and an upper surface of the first upper pads152. For example, the upper surface of the first insulating layer151and the upper surface of the first upper pads152exposed from the first insulating layer151may be substantially coplanar.

The first substrate110may be a semiconductor wafer substrate having a front surface FR and a rear surface BA, opposing each other. For example, the first substrate110may be a semiconductor wafer including a semiconductor element such as silicon or germanium, or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The front surface FR may be an active surface having an active region doped with impurities, and the rear surface BA may be an inactive surface opposite to the front surface FR. An insulating protective layer113electrically insulating the first upper pad152and the first substrate110may be disposed on the rear surface BA of the first substrate110. For example, the insulating protective layer113may include silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or silicon carbonitride (SiCN). A buffer film114such as a polishing stop layer or a barrier may be disposed on an upper surface of the insulating protective layer113. For example, the buffer film114may include silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.

The first circuit layer120may be disposed on the front surface FR of the first substrate110, and may include a first interconnection structure connected to the active region, and a first interlayer insulating layer surrounding the first interconnection structure. A first lower pad132electrically connected to an interconnection structure may be disposed below the first circuit layer120. The first lower pad132may be a pad structure electrically connected to an interconnection structure. A connection bump136may be disposed below the first lower pad132. The connection bump136may be a conductive bump structure including, for example, a solder ball, a copper (Cu) post, or the like. The first circuit layer120may have the same or a structure similar to that of a second circuit layer220illustrated inFIG.1B. Therefore, the first interconnection structure and the first interlayer insulating layer can be understood as having characteristics similar to those of a second interconnection structure225and a second interlayer insulating layer221in the second circuit layer220, to be described below. In addition, referring to the modified example ofFIG.4, structures of a first interconnection structure (125′ inFIG.4) and a first interlayer insulating layer (121′ inFIG.4) in the first circuit layer120can be easily understood.

The first through-electrode140may pass or extend through the first substrate110and the insulating protective layer113, to electrically connect the first upper pad152and the first lower pad132. The first through-electrode140may include a via plug145and a side barrier layer141surrounding a side surface of the via plug145. The via plug145may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu), and may be formed by a plating process, a PVD process, or a CVD process. The side barrier layer141may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and may be formed by a plating process, a PVD process, or a CVD process. A side insulating layer including an insulating material (e.g., a high aspect ratio process (HARP) oxide) such as silicon oxide, silicon nitride, silicon oxynitride, or the like may be formed between the side barrier layer141and the first substrate110.

The first insulating layer151may be disposed on the rear surface BA of the first substrate110. The first insulating layer151may include an insulating material that may be joined and bonded to the second insulating layer231below the second semiconductor chip200. For example, the first insulating layer151may include silicon oxide (SiO) or silicon carbonitride (SiCN). For example, at least a portion of the first insulating layer151may be joined to the second insulating layer231, to form a bonding surface BS for joining and bonding the first semiconductor chip100and the second semiconductor chip200.

The first upper pad152may be disposed on the rear surface BA of the first substrate110, and may include a first barrier layer153and a first conductive layer155. At least a portion of the first upper pad152may be joined to the second lower pad232of the second semiconductor chip200, to physically and electrically connect the first semiconductor chip100and the second semiconductor chip200. A bonding pad structure BP and a bonding surface BS may be formed. The first barrier layer153may conformally extend between the first conductive layer155and the first insulating layer151, and may be formed to surround a periphery of the first conductive layer155. The first conductive layer155and the first barrier layer153may include a conductive material. For example, the first conductive layer155may include at least one of copper (Cu), nickel (Ni), gold (Au), or silver (Ag), and the first barrier layer153may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).

As illustrated inFIG.1B, in a cross-section perpendicular to the upper surface of the first substrate110, the first upper pad152may include a second surface1521of the first upper pad152disposed below the first upper pad152, and side surfaces152aand152binclined at first and second obtuse angles α1 and α2 with respect to the second surface1521of the first upper pad152, respectively. The side surfaces152aand152bmay include a first side surface152ainclined at a first obtuse angle αl with respect to the second surface1521of the first upper pad152, and a second side surface152binclined at a second obtuse angle α2 with respect to the second surface1521of the first upper pad152. The first side surface152aand the second side surface152bmay face each other or be opposite each other. Each of the first and second obtuse angles α1 and α2 may have magnitudes in a range of about 100° to about 130° or 100° to 130°. The first upper pad152may include a first surface152uof the first upper pad152disposed on the first upper pad152, and a second surface1521of the first upper pad152facing or opposite the first surface152uof the first upper pad152in a vertical direction (z), perpendicular to the upper surface of the first substrate110. In a cross-section perpendicular to the upper surface of the first substrate110, the first upper pad152may have side surfaces152aand152binclined at first and second acute angles (31and (32with respect to the first surface152uof the first upper pad152, respectively. Each of the first and second acute angles (31and (32may have magnitudes in a range of about 50° to about 80° or 50° to 80°. The first upper pad152may have a trapezoidal shape in which a horizontal width of the first surface152uof the first upper pad152in a first direction (x) is wider than a horizontal width of the second surface1521of the first upper pad152in the first direction (x).

When each of the angles between the second surface1521and the first and second side surfaces152aand152bin each of the first upper pads152and/or each of the angles between the fourth surface2321and the third and fourth side surfaces232aand232bin each of the second lower pads232is less than about 100°, in a process of forming the first upper pad152and the second lower pad232, ion concentration may occur in a portion in which the second surface1521of the first upper pad152meets the first and second side surfaces152aand152b, causing fine cracks to occur. In order to solve the above problems, according to the present disclosure, each of the angles between the second surface1521and the first and second side surfaces152aand152bin each of the first upper pads152and/or each of the angles between the fourth surface2321and the third and fourth side surfaces232aand232bin each of the second lower pads232may be set to be about 100° or more.

When each of the angles between the second surface1521and the first and second side surfaces152aand152bin each of the first upper pads152and/or each of the angles between the fourth surface2321and the third and fourth side surfaces232aand232bin each of the second lower pads232exceeds about 130°, a center portion may be concave in a process of forming the first upper pad152and the second lower pad232. Therefore, in the process of bonding the first upper pad152and the second lower pad232, a void may occur between the first surface152uof the first upper pad152and the third surface232uof the second lower pad232. Therefore, according to the present disclosure, each of the angles between the second surface1521and the first and second side surfaces152aand152bin each of the first upper pads152and/or each of the angles between the fourth surface2321and the third and fourth side surfaces232aand232bin each of the second lower pads232may be set to be about 130° or less.

According to an embodiment, magnitudes of the first and second obtuse angles α1 and α2 may be different from each other, but are not limited thereto.

The second semiconductor chip200may be disposed on the first semiconductor chip100, and may include a second substrate210, a second circuit layer220, a second insulating layer231, and a second lower pad232. The second semiconductor chip200may have a flat lower surface provided by a lower surface of the second insulating layer231and a lower surface of the second lower pad232. For example, the lower surface of the second insulating layer231and the lower surface of the second lower pads232exposed from the second insulating layer231may be substantially coplanar. Since the first semiconductor chip100and the second semiconductor chip200may have substantially the same or similar structures, the same or similar components may be denoted by the same or similar reference numerals, and hereinafter, the same components may be repeated. For example, it can be understood that the second substrate210has substantially the same characteristics as the first substrate110described above.

The second circuit layer220may be disposed on a front surface or an active surface of the second substrate210, and may include a second interconnection structure225connected to an active region and a second interlayer insulating layer221surrounding the second interconnection structure225.

The second interlayer insulating layer221may be or include a flowable oxide (FOX), a tonen silazen (TOSZ), an undoped silica glass (USG), a borosilica glass (BSG), a phosphosilaca glass (PSG), a borophosphosilica glass (BPSG), a plasma enhanced tetra ethyl ortho silicate (PETEOS), a fluoride silicate glass (FSG), a high density plasma (HDP) oxide, a plasma enhanced oxide (PEOX), a flowable CVD (FCVD) oxide, or a combination thereof. At least a portion of the second interlayer insulating layer221surrounding the second interconnection structure225may be formed of a low dielectric layer. The second interlayer insulating layer221may be formed using a chemical vapor deposition (CVD) process, a flowable-CVD process, or a spin coating process.

The second interconnection structure225may be formed, for example, as a multilayer structure including an interconnection pattern and a via, formed of aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be disposed between the interconnection pattern or/and via and the second interlayer insulating layer221. Individual components215constituting an integrated circuit may be disposed on the front surface of the second substrate210. In this case, the second interconnection structure225may be electrically connected to the individual components215through an interconnection portion213(e.g., a contact plug). The individual components215may include an FET such as a planar FET, a FinFET, or the like, a flash memory, a memory element such as a DRAM, an SRAM, an EEPROM, a PRAM, an MRAM, an FeRAM, an RRAM, or the like, a logic element such as AND, OR, NOT, or the like, various active and/or passive elements such as a system LSI, a CIS, and an MEMS.

The second insulating layer231may be disposed below the second substrate210or the second circuit layer220. The second insulating layer231may include an insulating material that may be joined and bonded to the first insulating layer151of the first semiconductor chip100. For example, the second insulating layer231may include silicon oxide (SiO) or silicon carbonitride (SiCN). For example, at least a portion of the second insulating layer231may be joined to the first insulating layer151, to form a bonding surface BS for joining and bonding the first semiconductor chip100and the second semiconductor chip200. In addition, the second insulating layer231may be formed to surround a plurality of second lower pads232arranged on a lower surface thereof. In this case, the second insulating layer231may be referred to as a second lower insulating layer231.

The second lower pad232may be disposed below the second substrate210, and may include a second barrier layer233and a second conductive layer235. At least a portion of the second lower pad232may be joined to the first upper pad152of the first semiconductor chip100, to physically and electrically connect the first semiconductor chip100and the second semiconductor chip200. A bonding pad structure BP and a bonding surface BS may be formed. The second barrier layer233and the second conductive layer235may be formed of the same or similar structures and materials as the first barrier layer153and the first conductive layer155described above.

As illustrated inFIG.1B, the first upper pad152may include a first surface152ucontacting the second lower pad232, a second surface1521opposite to the first surface152u, and inclined side surfaces152aand152blocated between the first surface152uand the second surface1521. The second lower pad232may include a third surface232ucontacting the first upper pad152, a fourth surface2321opposite to the third surface232u, and inclined side surfaces232aand232blocated between the third surface232uand the fourth surface2321. In a cross-section perpendicular to the upper surface of the first substrate110, the second lower pad232may include a third side surface232ainclined at a third obtuse angle γ1with respect to the fourth surface2321, and a fourth side surface232binclined at a fourth obtuse angle γ2with respect to the fourth surface2321. The third side surface232aand the fourth side surface232bmay face each other or be opposite each other. Each of the third obtuse angle γ1and the fourth obtuse angle γ2may have magnitudes in a range of about 100° to about 130° or 100° to 130°.

The second lower pad232may include a fourth surface2321in which the second lower pad232and the second insulating layer231are in contact with each other, and a third surface232ufacing or opposite the fourth surface2321in a vertical direction (z), perpendicular to the upper surface of the first substrate110, and may have third and fourth side surfaces232aand232binclined at third and fourth acute angles M and62with respect to the third surface232u, respectively. Each of the third and fourth acute angles M and62may have magnitudes in a range of about 50° to about 80° or 50° to 80°.

According to an embodiment, magnitudes of the third and fourth obtuse angles γ1 and γ2 may be different from each other, but are not limited thereto.

According to an embodiment, magnitudes of the first and second obtuse angles α1 and α2 may be different from magnitudes of the third and fourth obtuse angles γ1 and γ2, but are not limited thereto.

According to an embodiment, a thickness of the first upper pad152in the vertical direction (z), perpendicular to the upper surface of the first substrate110may be less or thinner than a thickness of the second lower pad232in the vertical direction (z), but is not limited thereto.

FIG.2is a partially enlarged view illustrating a modified example of a semiconductor package according to an embodiment.

Referring toFIG.2, a semiconductor package10aof a modified example may have a heterojunction structure in which different materials are joined on a joining interface between a first upper insulating layer151and a second lower insulating layer231. For example, the second lower insulating layer231may include a lower insulating film231bdirectly contacting the first upper insulating layer151, and an upper insulating film231adisposed on the lower insulating film231b. To improve adhesion between the first upper insulating layer151and the second lower insulating layer231, the lower insulating film231bmay include an insulating material, different from an insulating material of the first upper insulating layer151. For example, the first upper insulating layer151may include silicon oxide (SiO), and the lower insulating film231bof the second lower insulating layer231may include silicon carbonitride (SiCN).

FIG.3is a partially enlarged view illustrating a modified example of a semiconductor package according to an embodiment.

Referring toFIG.3, a semiconductor package10bof a modified example may include grooves g1and g2formed in a bonding pad structure BP. For example, a first upper pad152may include a first conductive layer155and a first barrier layer153surrounding a side surface of the first conductive layer155, and a second lower pad232may include a second conductive layer235contacting at least a portion of the first conductive layer155, and a second barrier layer233surrounding a side surface of the second conductive layer235, the first conductive layer155may have a first groove g1exposing at least a portion of the first barrier layer153, and the second conductive layer235may have a second groove g2exposing at least a portion of the second barrier layer233. For example, at least a portion of an inner wall of the first barrier layer153and at least a portion of an inner wall of the second barrier layer233may be exposed or spaced apart from the first conductive layer155and the second conductive layer235by the first groove g1and the second groove g2, respectively. An outer wall of the first barrier layer153and an outer wall of the second barrier layer233may be covered by a first upper insulating layer151and a second lower insulating layer231, respectively. The first groove g1and the second groove g2may be more stably bonded to the first upper pad152and the second lower pad232, fixed by a bonding surface BS by securing an expansion space of the first conductive layer155and an expansion space of the second conductive layer235during joining and bonding processes of the first upper pad152and the second lower pad232, respectively.

FIG.4is a partially enlarged view illustrating a modified example of a semiconductor package according to an embodiment.

Referring toFIG.4, in a semiconductor package10cof a modified example, a second semiconductor chip200may be stacked on a first circuit layer120of a first semiconductor chip100. For example, the first semiconductor chip100and the second semiconductor chip200may be arranged such that a first front surface FR1 (e.g., of a first substrate110) and a second front surface FR2 (e.g., of a second substrate210) face each other. A first circuit layer120, a first front insulating layer131, and a first front pad132may be arranged on the first front surface FR1 of the first semiconductor chip100, and a second circuit layer220, a second front insulating layer231, and a second front pad232may be arranged on the second front surface FR2 of the second semiconductor chip200. A thickness of the first front pad132in the vertical direction (z), perpendicular to an upper surface of a first substrate110, may be substantially equal to a thickness of the second front pad232in the vertical direction (z). Also, the first front pad132and the second front pad232may be symmetrical with respect to a bonding surface BS on which the first front pad132and the second front pad232are in contact with each other. The first circuit layer120may include a first interconnection structure125electrically connected to individual components115through an interconnection portion, and a first interlayer insulating layer121surrounding the first interconnection structure125. Since the first circuit layer120has substantially the same characteristics as the above-described second circuit layer220, overlapping descriptions will be omitted in the interest of brevity. A first insulating layer151(or a first upper insulating film or layer) and a first upper pad152may be disposed on opposite sides of a first front insulating layer131and a first front pad132, respectively. In addition, it can be understood that the second front insulating layer231and the second front pad232are the same as the above-described second lower insulating layer231and the above-described second lower pad232, respectively. For example, the present modified example may have the same or similar characteristics to those described with reference toFIGS.1A to3, except that the first semiconductor chip100ofFIG.1Ais vertically inverted and joined to the second semiconductor chip200.

FIG.5is a cross-sectional view illustrating a semiconductor package10A according to an embodiment.

Referring toFIG.5, since a semiconductor package10A according to an embodiment has the same or similar features to those described with reference toFIGS.1A to4, except that the semiconductor package10A includes a plurality of second semiconductor chips200A,200B,200C, and200D stacked in the vertical direction (the Z-axis direction) on a first semiconductor chip100and a molding member160, duplicate descriptions may be omitted in the interest of brevity.

Between the plurality of second semiconductor chips200A,200B,200C, and200D, a joining interface on which a second rear insulating layer251and a second front insulating layer231are joined, and a joining interface on which a second rear pad252and a second front pad232are joined may be formed. The plurality of second semiconductor chips200A,200B,200C, and200D may be electrically connected to each other by an upper bonding pad structure BPb in which a second rear pad252and a second front pad232are joined and bonded. Among the plurality of second semiconductor chips200A,200B,200C, and200D, a lowermost second semiconductor chip200A may be electrically connected to the first semiconductor chip100by a lower bonding pad structure BPa in which a second front pad232is joined and bonded to a first rear pad152of the first semiconductor chip100.

The second plurality of semiconductor chips200A,200B,200C, and200D may include the same or similar features to those described with reference toFIGS.1A to4, except for further including a second through-electrode240for forming mutual electrical connection paths. It may have the same or similar structure as the semiconductor chip200. An uppermost second semiconductor chip200D may not include the second through-electrode240, and may have a relatively large thickness. According to an embodiment, more or fewer semiconductor chips than illustrated in the drawings may be stacked on the first semiconductor chip100. For example, three or less or five or more semiconductor chips may be stacked on the first semiconductor chip100.

For example, the first semiconductor chip100may be a buffer chip or a control chip including a plurality of logic devices and/or a plurality of memory devices. The first semiconductor chip100may transmit a signal from the plurality of second semiconductor chips200A,200B,200C, and200D, stacked thereon, to the outside, and may also transmit a signal and power from the outside to the plurality of second semiconductor chips200A,200B,200C, and200D. The plurality of second semiconductor chips200A,200B,200C, and200D may be memory chips including volatile memory devices such as a DRAM or an SRAM or non-volatile memory devices such as a PRAM, an MRAM, an FeRAM, and an RRAM. In this case, the semiconductor package10A of the present embodiment may be used as a high bandwidth memory (HBM) product, an electro data processing (EDP) product, or the like.

The molding member160may be disposed on the first semiconductor chip100, and may seal at least a portion of each of the plurality of second semiconductor chips200A,200B,200C, and200D. The molding member160may be formed to expose an upper surface of the uppermost second semiconductor chip200D. According to embodiments, the molding member160may be formed to cover the upper surface of the uppermost second semiconductor chip200D. The molding member160may include, for example, an epoxy mold compound (EMC), but a material of the molding member160is not particularly limited.

FIG.6Ais a plan view illustrating a semiconductor package10B according to an embodiment, andFIG.6Bis a cross-sectional view ofFIG.6A, taken along line I-I′.

Referring toFIGS.6A and6B, a semiconductor package10B according to an embodiment may include a package substrate600, an interposer substrate700, and at least one package structure PS. In addition, the semiconductor package10B may further include a logic chip (or a processor chip)800disposed adjacent to the package structure PS on the interposer substrate700. Although the package structure PS is illustrated to form the semiconductor package10A illustrated inFIG.5, but is not limited thereto, and may have the same or similar characteristics as the semiconductor packages10,10a,10b, and10c, described with reference toFIGS.1A to4.

The package substrate600may be a support substrate on which the interposer substrate700, the logic chip800, and the package structure PS are mounted, and may be a substrate for a semiconductor package including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring board, and the like. The package substrate600may include a lower pad612disposed at or on a lower surface of a body, an upper pad611disposed at or on an upper surface of the body, and an interconnection circuit613electrically connecting the lower pad612and the upper pad611. The body of the package substrate600may include a material, depending on a type of substrate. For example, when the package substrate600is a printed circuit board, the package substrate600may have a configuration in which an interconnection layer is additionally stacked on one surface or both surfaces of a body copper-clad laminate or a copper-clad laminate. The lower and upper pads612and611and the interconnection circuit613may form an electrical path connecting lower and upper surfaces of the package substrate600. An external connection bump620connected to the lower pad612may be disposed on the lower surface of the package substrate600. The external connection bump620may include, for example, a solder ball.

The interposer substrate700may include a substrate701, a lower protective layer703, a lower pad705, an interconnection structure710, a conductive bump720, and a through-via730. The package structure PS and the processor chip800may be stacked on the package substrate600via the interposer substrate700. The interposer substrate700may electrically connect the package structure PS and the processor chip800to each other.

The substrate701may be formed as, for example, any one of a silicon substrate, an organic substrate, a plastic substrate, and a glass substrate. When the substrate701is a silicon substrate, the interposer substrate700may be referred to as a silicon interposer. When the substrate701is an organic substrate, the interposer substrate700may be referred to as a panel interposer.

The lower protective layer703may be disposed on a lower surface of the substrate701, and the lower pad705may be disposed on the lower protective layer703. The lower pad705may be connected to the through-via730. The package structure PS and the processor chip800may be electrically connected to the package substrate600through conductive bumps720disposed on the lower pad705.

The interconnect structure710may be disposed on an upper surface of the substrate701, and may include an interlayer insulating layer711and a single layer interconnection structure or multilayer interconnection structure712. When the interconnection structure710has a multilayer interconnection structure, interconnection patterns of different layers may be connected to each other through a contact via. An upper pad704connected to the interconnection structure712may be disposed on the interconnection structure710. The package structure PS and the processor chip800may be connected to the upper pad704through a connection bump136.

The through-via730may extend from the upper surface of the substrate701to the lower surface of the substrate701to pass through the substrate701. For example, the through-via730may extend into the interconnection structure710, to be electrically connected to interconnections of the interconnection structure710. When the substrate701is silicon, the through-via730may be referred to as a through-silicon via (TSV). Depending on embodiments, the interposer substrate700may include only the interconnection structure therein, and may not include the through-via.

The interposer substrate700may be used for the purpose of converting or transmitting an input electrical signal between the package substrate600and the package structure PS or the processor chip800. Therefore, the interposer substrate700may not include elements such as active elements or passive elements. Depending on an embodiment, the interconnection structure710may be disposed below the substrate701.

The conductive bump720may be disposed on a lower surface of the interposer substrate700, and electrically connected to interconnections of the interconnection structure710. The interposer substrate700may be mounted on the package substrate600through the conductive bump720. For example, some of a plurality of the lower pad705used for power or ground may be integrated and connected to the conductive bump720, such that the number of lower pads705may be larger than the number of conductive bumps720.

The processor chip800(or logic chip) may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application specific integrated circuit (ASIC), or the like. Depending on types of integrated circuits included in the processor chip800, the semiconductor package10B may be referred to as a server-side semiconductor package, a mobile-side semiconductor package, or the like. Depending on embodiments, the number of processor chips800and/or package structures PS mounted on the interposer substrate700may be more or less than those illustrated in the drawings.

FIG.7Ais a plan view illustrating a semiconductor package10C according to an embodiment, andFIG.7Bis a cross-sectional view ofFIG.7A, taken along line II-II′.

Referring toFIGS.7A and7B, a semiconductor package10C according to an embodiment may include a plurality of second semiconductor chips200a,200b, and200c, horizontally arranged on a first semiconductor chip100. In the present embodiment, the plurality of second semiconductor chips200a,200b, and200c(also referred to as ‘chiplets’) may include chiplets constituting a multi-chip module (MCM). For example, the second semiconductor chips200a,200b, and200cmay be mounted on the first semiconductor chip100. According to embodiments, the second semiconductor chips200a,200b, and200cmay be electrically connected to each other through a first interconnection structure125of the first semiconductor chip100. A bonding pad structure BP, as described with reference toFIGS.1A to4, may be formed between the first semiconductor chip100and the second semiconductor chips200a,200b, and200c. A first upper pad152and a second lower pad232of the bonding pad structure BP may include first and second side surfaces152aand152brespectively inclined at first and second obtuse angles α1 and α2 with respect to a second surface1521of the first upper pad152, and third and fourth side surfaces232aand232brespectively inclined at third and fourth obtuse angles γ1 and γ2 with respect to a fourth surface2321, respectively (seeFIG.1B). Therefore, defects of the first upper pad152and the second lower pad232may be minimized.

The first semiconductor chip100may include an active interposer functioning as an I/O chip. For example, the first semiconductor chip100may include an I/O device, a DC/DC converter, a sensor, a test circuit, or the like therein. Since the first semiconductor chip100may include elements similar to those of the interposer substrate700illustrated inFIG.6B, duplicate descriptions will be omitted in the interest of brevity. In the drawings, although the first semiconductor chip100is illustrated as forming a silicon interposer substrate, a substrate applicable to the present embodiment is not limited thereto. The first semiconductor chip100may be mounted on the package substrate600.

The second semiconductor chips200a,200b, and200cmay include a CPU, a GPU, an FPGA, or the like. The second semiconductor chips200a,200b, and200cmay be composed of different chips. For example, a first chiplet200amay be a GPU chip, a second chiplet200bmay be a CPU chip, and a third chiplet200cmay be an FPGA chip. According to embodiments, the second semiconductor chips200a,200b, and200cmay be composed of the same type of chips. For example, all of the second semiconductor chips200a,200b, and200cmay include GPU chips. The number of chiplets disposed on the first semiconductor chip100is not particularly limited, and for example, two or less or four or more chiplets may be mounted on the first semiconductor chip100. In this case, the chiplet or the chiplet technology may refer to a semiconductor chip manufactured separately according to a size and a function of a device, or a technology for manufacturing such a semiconductor chip.

FIG.8is a flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment according to a process sequence.

FIG.9illustrates a bonding process between a first structure1and a second structure2, to illustrate a method of manufacturing a semiconductor package according to an embodiment.

In this specification, a first structure1and a second structure2may be referred to as a first semiconductor chip100and a second semiconductor chip200, respectively, a first bonding pad BP1 and a second bonding pad BP2 may be referred to as a first pad152and a second pad232, respectively, a first bonding insulating layer BI1 and a second bonding insulating layer BI2 may be referred to as a first insulating layer151and a second insulating layer231, respectively.

Referring toFIGS.8and9, a first structure1including a first bonding structure BS1 may be formed (51), a second structure2including a second bonding structure BS2 may be formed (S2), and the first structure1and the second structure2may be joined such that the first bonding structure BS1 and the second bonding structure BS2 are in direct contact with each other (S3).

The first bonding structure BS1 may include a first bonding pad BP1 and a first bonding insulating layer BI1 surrounding at least a portion of a side surface of the first bonding pad BP1, and the second bonding structure BS2 may include a second bonding pad BP2 and a second bonding insulating layer BI2 surrounding at least a portion of a side surface of the second bonding pad BP2. The first bonding pad BP1 and the second bonding pad BP2 may be in contact with each other, to be bonded by copper-to-copper bonding. Central axes of the first bonding pad BP1 and the second bonding pad BP2 may be shifted from each other for reasons of processing, but are not limited thereto. The first bonding insulating layer BI1 and the second bonding insulating layer BI2 may be in contact with each other, to be bonded by dielectric-to-dielectric bonding. The first bonding structure BS1 and the second bonding structure BS2 may be electrically connected to a redistribution layer or a through-via disposed on each of the first structure1and the second structure2.

In an embodiment, joining of the first structure1and the second structure2may be die-to-die joining, die-to-wafer joining, or wafer-to-wafer joining. For example, when each of the first structure1and the second structure2is a semiconductor chip, joining of the first structure1and the second structure2may be die-to-die joining. For example, when the first structure1is one of a plurality of semiconductor structures divided into scribe lanes on a semiconductor wafer, and the second structure2is a semiconductor chip disposed on each of the plurality of semiconductor structures, joining of the first structure1and the second structure2may be die-to-wafer joining. For example, when the first structure1and the second structure2are one of a plurality of semiconductor structures divided into scribe lanes in each of the first semiconductor wafer and the second semiconductor wafer, joining of the first structure1and the second structure2may be wafer-to-wafer joining.

Hereinafter, a method for manufacturing the first structure1and the second structure2will be described.

FIGS.10A to10Gare cross-sectional views illustrating a manufacturing process for forming a first pad on a rear surface of a semiconductor chip.FIGS.10A to10Gillustrate a portion of a manufacturing process of the first semiconductor chip100illustrated inFIG.1Aaccording to a process sequence.

Referring toFIG.10A, a first semiconductor wafer WF1 including a first preliminary substrate110pand a plurality of through-electrodes140arranged in the first preliminary substrate110pmay be prepared.

The first semiconductor wafer WF1 may be temporarily supported on a first carrier substrate C1by a joining material layer RL such as glue. The first semiconductor wafer WF1 may include components for a plurality of semiconductor chips (or ‘first semiconductor chips’). Specifically, the first semiconductor wafer WF1 may include a first circuit layer120formed on an active surface of the first preliminary substrate110p, and a plurality of through-electrodes140connected to the interconnection structure of the first circuit layer120. The plurality of through-electrodes140may be formed before or during formation of the first circuit layer120, not to completely penetrate the first preliminary substrate110p. In addition, a connection bump136buried in the joining material layer RL may be disposed below the first semiconductor wafer WF1.

Referring toFIG.10B, a portion of the first preliminary substrate110pmay be removed to form a first substrate110having a rear surface110BS in or through which the plurality of through-electrodes140protrude.

The first substrate110having a desired thickness may be formed by applying a polishing process to an upper surface (an inactive surface) of the first preliminary substrate110p. The polishing process may be performed by a grinding process such as a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof. For example, the through-electrodes140may be sufficiently exposed by performing a grinding process to reduce the first preliminary substrate110pto a certain thickness and applying an etch-back process under appropriate conditions.

Referring toFIG.10C, a preliminary buffer film114pand a preliminary protective layer113pcovering upper ends140T of the through-electrodes140protruding onto or from the rear surface110BS of the first substrate110may be formed. The preliminary protective layer113pmay be silicon oxide, and the preliminary buffer film114pmay be silicon nitride or silicon oxynitride. The preliminary protective layer113pand the preliminary buffer film114pmay be formed using a PVD process or a CVD process. Subsequently, the preliminary protective layer113pand the preliminary buffer film114pmay be planarized (e.g., ground) to expose the through-electrodes140. Through the planarization process, the preliminary protective layer113pand the preliminary buffer film114pmay be removed up to a predetermined line GL. In addition, portions of the upper ends140T of the through-electrodes140may also be removed.

Referring toFIG.10D, the first semiconductor wafer WF1 may have a flat surface FS from which a protective layer113, a buffer film114, and the plurality of through-electrodes140are exposed. As described above, since the upper ends140T of the through-electrodes140may be partially removed by a planarization process, a portion of a via plug145may be exposed through the flat surface FS.

Referring toFIG.10E, a rear insulating layer151including a first etch groove ER1 may be formed on a flat surface (‘FS’ inFIG.10D) of the first semiconductor wafer WF1.

The first etch groove ER1 may be formed by etching at least a portion of a preliminary insulating layer formed on the protective layer113and the buffer film114. The preliminary insulating layer may include, for example, silicon oxide (SiO) and/or silicon carbonitride (SiCN), and may be formed using a PVD or CVD process. The first etch groove ER1 may be formed using an etching process such as, for example, reactive-ion etching (RIE) or the like using a photoresist. In this case, the etching process may be performed to have side surfaces152aand152binclined at first and second obtuse angles α1 and α2 with respect to a second surface1521of a rear pad152, respectively (seeFIG.10G). Each of the first and second obtuse angles α1 and α2 may have magnitudes in a range of about 100° to about 130° or 100° to 130° (seeFIG.10G).

Referring toFIG.10F, a preliminary rear pad152pincluding a first preliminary barrier layer153pand a first preliminary conductive layer155pmay be formed on a surface of the rear insulating layer151and inside the first etch groove ER1.

The first preliminary barrier layer153pmay be conformally formed along the surface of the rear insulating layer151. The first preliminary conductive layer155pmay be formed on the first preliminary barrier layer153p, and may fill an internal space of the first etch groove ER1. The first preliminary barrier layer153pand the first preliminary conductive layer155pmay be formed using a plating process, a PVD process, or a CVD process. For example, the first preliminary barrier layer153pmay include titanium (Ti) or titanium nitride (TiN), and the first preliminary conductive layer155pmay include copper (Cu). A seed layer including the same material as the first preliminary conductive layer155pmay be formed between the first preliminary barrier layer153pand the first preliminary conductive layer155p.

Referring toFIG.10G, a rear pad152including a first barrier layer153and a first conductive layer155may be formed by polishing the first preliminary barrier layer153pand the first preliminary conductive layer155p.

A portion of the first preliminary barrier layer153pand a portion of the first preliminary conductive layer155pmay be removed by a polishing process, and a rear pad152including a first conductive layer155and a first barrier layer153may be formed. The polishing process may be performed using, for example, a CMP process using a first slurry. The first slurry may have polishing selectivity with respect to the first preliminary barrier layer153p, the first preliminary conductive layer155p, and the rear insulating layer151.

FIGS.11A to11Care cross-sectional views illustrating a manufacturing process for forming a second pad on a front surface of a semiconductor chip.FIGS.11A to11Cillustrate a portion of a manufacturing process of the second semiconductor chip200illustrated inFIG.1Aaccording to a process sequence.

Referring toFIG.11A, a front insulating layer231including a second etch groove ER2 may be formed on a second semiconductor wafer WF2.

The second semiconductor wafer WF2 may include a second preliminary substrate210p, a second circuit layer220disposed on a front surface of the second preliminary substrate210p, and a front insulating layer231disposed on the second circuit layer220. The second semiconductor wafer WF2 may be supported and temporarily joined to a second carrier substrate C2. The second etch groove ER2 may be formed by etching at least a portion of a preliminary insulating layer formed on the second circuit layer220. The preliminary insulating layer may include, for example, silicon oxide (SiO) and/or silicon carbonitride (SiCN), and may be formed using a PVD or CVD process. The second etch groove ER2 may be formed using an etching process such as, for example, reactive-ion etching (RIE) using a photoresist. In this case, the etching process may be performed to have a third side surface232ainclined at a third obtuse angle γ1 with respect to a fourth surface2321of a front pad232, and a fourth side surface232binclined at a fourth obtuse angle γ2 with respect to the fourth surface2321of the front pad232(seeFIG.11C). Each of the third obtuse angle γ1 and the fourth obtuse angle γ2 may range from about 100° to about 130° or 100° to 130° (seeFIG.11C).

Referring toFIG.11B, a preliminary front pad232pincluding a second preliminary barrier layer233pand a second preliminary conductive layer235pmay be formed on a surface of the front insulating layer231and inside the second etch groove ER2.

The second preliminary barrier layer233pmay be conformally formed along the surface of the front insulating layer231. The second preliminary conductive layer235pmay be formed on the second preliminary barrier layer233p, and may fill an internal space of the second etch groove ER2. The second preliminary barrier layer233pand the second preliminary conductive layer235pmay be formed using a plating process, a PVD process, or a CVD process. For example, the second preliminary barrier layer233pmay include titanium (Ti) or titanium nitride (TiN), and the second preliminary conductive layer235pmay include copper (Cu). A seed layer including the same material as the second preliminary conductive layer235pmay be formed between the second preliminary barrier layer233pand the second preliminary conductive layer235p.

Referring toFIG.11C, a front pad232including a second barrier layer233and a second conductive layer235may be formed by polishing the second preliminary barrier layer233pand the second preliminary conductive layer235p.

A portion of the second preliminary conductive layer235pand a portion of the second preliminary barrier layer233pmay be removed by a polishing process, and a front pad232including a second conductive layer235and a second barrier layer233may be formed. The polishing process may be performed using, for example, a CMP process using a first slurry. The first slurry may have polishing selectivity with respect to the second preliminary barrier layer233p, the second preliminary conductive layer235p, and the front insulating layer231. Thereafter, a rear surface of the second preliminary substrate210pmay be ground to form a plurality of semiconductor chips200(or ‘second semiconductor chips’) having a desired thickness.

FIG.12is a cross-sectional view illustrating a manufacturing process of the semiconductor package10ofFIG.1A.

Referring toFIG.12, first, a semiconductor wafer WF provided for first semiconductor chips100may be prepared. The semiconductor wafer WF may be formed by the manufacturing processes ofFIGS.10A to10G. The semiconductor wafer WF may include a plurality of rear pads152and a rear insulating layer151surrounding the plurality of rear pads152. The semiconductor wafer WF may be supported on a temporary carrier CW by a joining material layer RL.

Next, a plurality of second semiconductor chips200may be prepared. The plurality of second semiconductor chips200may be formed by the manufacturing processes ofFIGS.11A to11C. The plurality of second semiconductor chips200may include a plurality of front pads232and a front insulating layer231surrounding the plurality of front pads232. The semiconductor wafer WF and the plurality of second semiconductor chips200may not be sequentially prepared, and may be formed by independent manufacturing processes.

Next, the plurality of second semiconductor chips200may be disposed on the semiconductor wafer WF. The plurality of second semiconductor chips200may be disposed on the first semiconductor chips100of the semiconductor wafer WF by using, for example, a pick-and-place device. The plurality of second semiconductor chips200may be aligned with the first semiconductor chips100. Therefore, the plurality of rear pads232may be in contact with the plurality of front pads152, and the rear insulating layer151may be in contact with the front insulating layer231.

Next, a thermal compression process may be performed to bond the rear insulating layer151and the front insulating layer231joined to each other, and to bond the plurality of rear pads152and the plurality of front pads232joined to each other. The thermal compression process may be performed such that the rear insulating layer151and the front insulating layer231may be first bonded, and then the plurality of rear pads152and the plurality of front pads232may be bonded. For example, the thermal compression process may be performed such that the rear insulating layer151and the front insulating layer231are bonded under a thermal atmosphere ranging from about 100° C. to about 200° C., and the plurality of rear pads152and the plurality of front pads232are bonded under a thermal atmosphere ranging from about 200° C. to about 300° C. A temperature of the thermal atmosphere is not limited to the above-described range (about 100° C. to about 300° C.), and may be variously changed.

According to embodiments, a lower surface and a side surface of the first pad may be introduced to have a certain angle, to provide a semiconductor package preventing defects during pad formation and having improved reliability.