SEMICONDUCTOR DEVICE ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME

An embodiment of the present disclosure provides a semiconductor device arrangement. This arrangement includes a substrate, an adhesive structure, and a first semiconductor device. The substrate includes an upper surface. The adhesive structure is located on the upper surface and includes a first concave region. The first semiconductor device includes a lower surface facing toward the adhesive structure and a conductive bump located under the lower surface and in the first concave region. The conductive bump includes a first portion and a second portion. Wherein the lower surface does not contact the adhesive structure, the first portion contacts the first concave region, and the second portion does not contact the first concave region.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device arrangement, and more particularly, to a semiconductor device arrangement with conductive bumps and a method of manufacturing the same.

DESCRIPTION OF BACKGROUND ART

A light-emitting diode (LED) is an optoelectronic semiconductor device that is suitable for diverse lighting and display applications because it has good characteristics, such as low power consumption, low heat generation, long operation life, shock tolerance, a compact size, and swift response.

As the continuous advancements in LED technology, the brightness of an LED die is increasing continuously, and the size of LED die is also gradually being reduced to, e.g., less than 100 μm, 50 μm, or 30 μm. The use of LED dies is no longer limited to general lighting applications or as a backlight source in LCD monitors. To use LED dies directly as the pixels of an LED display could become a trend in next-generation displays.

An LED display is composed of millions or even tens of millions of LED chips. Precisely placing such a large number of LED dies on a display panel requires fast and reliable die transfer technology.

SUMMARY OF THE APPLICATION

According to one embodiment of the present disclosure, a semiconductor device arrangement is provided. This arrangement includes a substrate, an adhesive structure, and a first semiconductor device. The substrate includes an upper surface. The adhesive structure is located on the upper surface and includes a first concave region. The first semiconductor device includes a lower surface facing toward the adhesive structure and a conductive bump located under the lower surface and in the first concave region. The conductive bump includes a first portion and a second portion. Wherein the lower surface does not contact the adhesive structure, the first portion contacts the first concave region, and the second portion does not contact the first concave region.

According to another embodiment of the present disclosure, a method of manufacturing a semiconductor device arrangement is provided. This method includes providing a substrate, an adhesive structure, a first semiconductor device, and a second semiconductor device. Wherein, the substrate includes an upper surface; the adhesive structure is located on the upper surface; and the first semiconductor device and the second semiconductor device are located on the adhesive structure. Providing an energy to the first semiconductor device such that a contact area between the first semiconductor device and the adhesive structure is reduced; providing a transferring structure to simultaneously contact the first semiconductor device and the second semiconductor device; and removing the transferring structure to transfer the first semiconductor device to the transferring structure.

DETAILED DESCRIPTION OF THE APPLICATION

The semiconductor device arrangements and manufacturing methods thereof in accordance with the embodiments of the present disclosure are described in detail in the following description. It should be understood that in the following detailed description, for purposes of explanation, numerous specific details and embodiments are set forth in order to provide a thorough understanding of the present disclosure. The elements and configurations described in the following detailed description are set forth in order to clearly describe the present disclosure. The embodiments are used merely for the purpose of illustration. In addition, the drawings of different embodiments may use like and/or corresponding numerals to denote like and/or corresponding elements in order to clearly describe the present disclosure. However, the use of like and/or corresponding numerals in the drawings of different embodiments does not suggest any correlation between different embodiments.

FIG.1Ais a top view of a semiconductor device arrangement1000in accordance with an embodiment of the present disclosure. The semiconductor device arrangement1000includes a plurality of semiconductor devices1arranged in an array on a substrate10. The semiconductor device1may be a light-emitting diode (LED), laser diode (LD), or a transistor. The semiconductor device arrangement1000may be composed of a single type or various types of semiconductor device1. The substrate10can be a growth substrate of the semiconductor device or can be a temporary carrier (non-growth substrate) to support the semiconductor device. The material of the substrate10includes but is not limited to: germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), sapphire, silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), metal, glass, thermal release tape, UV release tape, chemical release tape, heat resistant tape, blue tape, or tapes with dielectric release layer. Each of the semiconductor devices1has a pair of conductive bumps2a,2bfor electrically or physically connecting to the external circuit (e.g., circuit board, backplane) on the side away from the substrate10. The projected shape of the conductive bump is substantially rectangular in the top view, as shown inFIG.1A.

FIG.1Bis a cross-sectional view taken along line A-A′ ofFIG.1A. The semiconductor device1has a pair of electrodes3a,3bon the side away from the substrate10. The conductive bumps2a,2bare disposed on the electrode3a,3b, respectively. The upper surfaces of the conductive bumps2a,2bare of arc shape and not parallel to the upper surfaces of the electrodes3a,3b.

In one embodiment, the material of the conductive bumps2a,2bis different from the material of the electrodes3a,3b. The material of the electrodes3a,3bincludes gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), alloys thereof, or combinations of the stacking layers thereof. The material of the conductive bumps2a,2bmay include a low melting point metal or a low liquidus melting point alloy, whose melting point or liquidus temperature is lower than 210° C., such as bismuth (Bi), tin (Sn), indium (In), or alloys thereof. In an embodiment, the melting point of the low melting point metal or the liquidus temperature of the low liquidus melting point alloy is lower than 170° C. The material of the low liquidus melting point alloy may be tin-indium alloy or tin-bismuth alloy.

FIG.1Cis a top view of a semiconductor device arrangement1001in accordance with another embodiment of the present disclosure. The semiconductor device arrangement1001includes a plurality of semiconductor devices1arranged in a predetermined pattern on the substrate10. The substrate10has a substantially circular shape. For the material of the substrate10, reference can be made to the aforementioned relevant paragraphs.FIG.1Dis a cross-sectional view taken along line A-A′ ofFIG.1C. A sub-adhesive structure4is between each semiconductor device1and the substrate10. Each of the plurality of semiconductor devices1is temporally fixed on the substrate10by the sub-adhesive structure4. Each of the plurality of semiconductor devices1has a pair of the electrodes3a,3bon the side away from the substrate10. The conductive bumps2a,2bare disposed on the electrodes3a,3b, respectively. The upper surfaces of the conductive bumps2a,2bare of arc shape from the lateral view and not completely parallel to the upper surfaces of the electrodes3a,3b. The sub-adhesive structure4may include polymer, such as polyimide (PI), acrylic resin, epoxide resin (EPO), polybenzoxazole (PBO), polysiloxane, cyclic olefin polymer (COP), or benzocyclobutane (BCB). For the material of the conductive bumps2a,2band the material of the electrodes3a,3b, reference can be made to the aforementioned relevant paragraphs.

As shown inFIG.1D, for each semiconductor device1, an outer side42of the sub-adhesive structure4is substantially coplanar with an outermost side19of the semiconductor device1. The sub-adhesive structure4has a thickness H4, which is about 2-3 μm or 1-10 μm. In other words, the sub-adhesive structure4has a maximum width W5, the semiconductor device1has a maximum width W6, and W5is substantially the same as W6. In another embodiment, for each of the semiconductor devices1, the outer side42is not coplanar with the outermost side19of the semiconductor device1, and the sub-adhesive structure4can be retracted or protruded relative to the outermost side19of the semiconductor device1. That is, the maximum width W5can be less than or more than the maximum width W6.

FIG.1Eis a cross-sectional view of the semiconductor device arrangement1003in accordance with another embodiment of the present disclosure. The semiconductor device arrangement1003includes a plurality of semiconductor devices1arranged in a predetermined pattern on a substrate10. An adhesive structure4′ is between the plurality of semiconductor devices1and the substrate10. The plurality of semiconductor devices1is temporarily fixed on the substrate10by the adhesive structure4′. Each semiconductor device1has a pair of the electrodes3a,3bon the side away from the substrate10. The conductive bumps2a,2bare disposed on the electrodes3a,3b, respectively.

As shown inFIG.1E, the adhesive structure4′ has mesa portions43and continuous portions44. The continuous portions44are uninterrupted and continuously disposed on the substrate10across the areas below the plurality of semiconductor devices1and between two adjacent semiconductor devices1. Each of the mesa portions43is between each of the semiconductor devices1and the continuous portions44, protruding from the continuous portion44and corresponding to one of the plurality of semiconductor devices1. For each of the plurality of semiconductor devices1, the outer side42of the mesa portion43is coplanar with or near the outermost side19of the semiconductor device1. The adhesive portion4has a thickness H4, which is about 2-3 μm. The continuous portion44has a thickness H5, which is more than 0 μm and less than 1 μm. In other words, the mesa portion43has a maximum width W5and the semiconductor device1has a maximum width W6, and the maximum width W5is substantially equal to the maximum width W6. In another embodiment, for each semiconductor device1, the outer side42is not coplanar with the outermost side19of the semiconductor device1, and the mesa portion43can be retracted or protruded relatively to the outermost side19of the semiconductor device1. That is, the maximum width W5may be less than or more than the maximum width W6.

FIG.2Ais a three-dimensional view of a semiconductor device1on a substrate10in accordance with an embodiment of the present disclosure. The maximum side length of the semiconductor device1is not more than 100 μm or 50 μm. For example, the maximum side length of the semiconductor device is about 40 μm and the width thereof is about 20 μm. The conductive bump2aand the conductive bump2bhave different polarities (positive, negative), and the minimal horizontal distance D therebetween is less than 40 μm. For example, the maximum side length of the semiconductor device1is about 40 μm and the distance D thereof is about 15 μm. The conductive bumps2a,2bcover the electrodes thereunder (not shown) completely and have convex arc shapes and tops21a,21b. Referring toFIG.2A, the tops21a,21bare located approximately at the geometric center of the conductive bumps2a,2band/or the electrodes.

FIG.2Bis a cross-sectional view of a semiconductor device1taken along line B-B′ ofFIG.2A. The semiconductor device1is placed on the substrate10, and has a semiconductor stack14, a protective layer15, a first electrode3a, a second electrode3b, a first conductive bump2a, and a second conductive bump2b. The outermost side19of the semiconductor stack14is an inclined plane, which is not perpendicular to an upper surface1051of the substrate10. In one embodiment, the semiconductor device1is an LED die, and the semiconductor stack14includes a first semiconductor layer11, an active layer12, and a second semiconductor layer13. The first semiconductor layer11and the second semiconductor layer13can respectively provide electrons and holes so that the electrons and holes can recombine in the active layer12to emit light. The first semiconductor layer11, the active layer12and the second semiconductor layer13may include III-V semiconductor material, such as AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, wherein 0≤x, y≤1; (x+y)≤1. Depending on the material of the active layer12, the LED die can emit a red light with a peak wavelength in a range of 610 nm and 650 nm, a green light with a peak wavelength in a range of 530 nm and 570 nm, a cyan light with a peak wavelength in a range of 500 nm and 485 nm, a blue light with a peak between 450 nm and 485 nm, a violet light with a peak wavelength in a range of 400 nm and 450 nm, or an ultraviolet light with a peak wavelength in a range of 280 nm and 400 nm. The maximum thickness of the semiconductor stack14is about equal to or less than 10 μm. In an embodiment, the lower surface17of the first semiconductor layer11is a rough surface and in contact with the substrate10. In other words, the upper surface of the substrate10is in contact with the lower surface17of the first semiconductor layer11. In another embodiment, the lower surface17of the first semiconductor layer11is a substantially flat surface (not shown). In another embodiment, the substrate10is a growth substrate for epitaxial growth of the semiconductor stack14and can be a patterned sapphire substrate (PSS) so the upper surface of the substrate10facing the semiconductor stack14is a rough surface (not shown). In an embodiment, the semiconductor device1includes a carrier (not shown) under the semiconductor stack14to support the semiconductor stack14, and the carrier may be an epitaxial growth substrate of the semiconductor stack14or not an epitaxial growth substrate. For the material of the carrier, reference can be made to the aforementioned relevant paragraphs of the substrate10, but the selection of materials should conform to the theoretical and practical feasibility.

As shown inFIG.2B, the semiconductor stack14has a mesa16which is formed by removing a portion of the active layer12and the second semiconductor layer13to expose the first semiconductor layer11. The protective layer15covers the upper surface of the second semiconductor layer13, sidewalls of the first semiconductor layer11, sidewalls of the active layer12, sidewalls of the second semiconductor layer13, and the upper surface of the first semiconductor layer11in the mesa16. The protective layer15can contact the substrate10. In another embodiment, the protective layer15is not in contact with the substrate10. The protective layer15has a first opening5ain the mesa16to expose portions of the first semiconductor stack11. The protective layer15has a second opening5bon the second semiconductor layer13to expose portions of the second semiconductor layer13. The first electrode3ais in the mesa16with a portion formed on the protective layer15and covering the protective layer15. The first electrode3ahas a first recess6aformed in the first opening5aand is electrically connected to the first semiconductor layer11. The first electrode3ahas a stepped shape in the area of the mesa16. The second electrode3bhas a portion on the protective layer15outside the second opening5band a second recess6bformed in the second opening5bfor being electrically connected to the second semiconductor layer13.

The protective layer15may be a single-layer or multi-layer structure and has a property of electrical insulation. The material of the single-layer structure may include oxide, nitride, or polymer. The oxide may include aluminum oxide (Al2O3), silicon oxide (SiO2), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), or aluminum oxide (AlOx). The nitride may include aluminum nitride (AlN) or silicon nitride (SiNx). The polymer may include polyimide or benzocyclobutane (BCB). The material of the multi-layer structure may include aluminum oxide (Al2O3), silicon oxide (SiO2), titanium oxide (TiO2), niobium pentoxide (Nb2O5), silicon nitride (SiNx), or combinations thereof. The multi-layer structure can also form a distributed Bragg reflector (DBR).

Referring toFIG.2B, a first conductive bump2ais formed over the first electrode3a. The first conductive bump2amay completely or partially fill the first recess6aof the first electrode3a, and the outermost surface22aof the first conductive bump2ahas a macroscopically smooth and convex arc shape. The first conductive bump2ahas a top21a, which is a region having farthest distance between the first conductive bump2aand the substrate10. As shown inFIG.2B, the outermost surface22aof the first conductive bump2adoes not contain any plane parallel to the lowest surface of the first conductive bump2a, and is not parallel to the upper surface of the first electrode3a, either. The lower surface17of the first semiconductor layer11is a rough surface, wherein the roughness of the outermost surface22aof the first conductive bump2ais less than the roughness of the lower surface17of the first semiconductor layer11and is less than the roughness of the upper surface of the first electrode3a.

Referring toFIG.2B, a second conductive bump2bcovers the second electrode3b. The second conductive bump2bmay completely or partially fill the second recess6bof the second electrode3b, and the outermost surface22bof the second conductive bump2bhas a macroscopically smooth and convex arc shape. The second conductive bump2bhas a top21b, which is a region of the second conductive bump2bfarthest away from the substrate10. As shown in theFIG.2B, the outermost surface22bof the second conductive bump2bdoes not contain any plane parallel to the lowest surface of the second conductive bump2b, and is not parallel to the upper surface of the second electrode3b, either. The roughness of the outermost surface22bof the second conductive bump2ais less than the roughness of the lower surface17of the first semiconductor layer11and is less than the roughness of the upper surface of the second electrode3b. In one embodiment, the top21aof the first conductive bump2aand the top21bof the second conductive bump2bare substantially in a same horizontal height, which is beneficial for the device1to be stably affixed on the substrate subsequently. However, in practice, there may be a certain degree of height difference under the tolerance of the fabrication process. Generally, the lowest surface of the first conductive bump2aand the second conductive bump2bare formed conformally on the first electrode3aand the second electrode3b, respectively, whereas their lowest points are not commonly in the same horizontal height. As shown inFIG.2B, a first thickness H1can be obtained by measuring the vertical distance from the top21aof the first conductive bump2ato the uppermost surface151of the protective layer15. The first conductive bump2ahas a first (maximum) width W1, wherein the ratio H1/W1is between 0.1-0.4, or between 0.1-0.25. A second thickness H2can be obtained by measuring the vertical distance from the top21bof the second conductive bump2nto the uppermost surface151of the protective layer15. The second conductive bump2bhas a second (maximum) width W2, wherein the ratio H2/W2is between 0.1-0.4, or between 0.1-0.25. The ratios of H1/W1and H2/W2may be the same or different. The second thickness H2of the second conductive bump2bis between 4-6 μm.

If the first conductive bump2ais more densely filled in the first recess6aof the first electrode3aand/or the second conductive bump2bis more densely filled in the second recess6bof the second electrode3b, the reliability of the physical or electrical connection between the semiconductor device1and the circuit substrate (not shown) can be improved, and the probability of open circuit between the semiconductor device1and the circuit substrate can be reduced. Specifically, if the structure of the semiconductor device1is as shown inFIG.2Bbut does not have the conductive bump2a/2b, when the semiconductor device1is fixed to a circuit substrate by a solder, the solder between the first electrode3aand the circuit substrate (not shown) may sometimes have holes near the first recess6a, and the solder between the second electrode3band the circuit substrate (not shown) also may sometimes have holes near the second recess6b. These holes may decrease the fixing strength between the semiconductor device1and the circuit substrate.

If a thermal treatment step is present during the formation of the conductive bump, under a specific combination of the selected materials of the conductive bump and the electrode, discretely distributed metal particles may be formed within the conductive bump after the thermal treatment step, as shown inFIG.2C.FIG.2Cis a cross-sectional view of a semiconductor device1in accordance with another embodiment of the present disclosure. For the structure shown inFIG.2C, reference can be made toFIG.2Band the aforementioned relevant paragraphs. The first conductive bump2aand the second conductive bump2bhave discretely distributed, irregularly sized and irregularly shaped particles7distributed therein. The material of the particles7is different from the material of the conductive bump2a,2b, but is partially the same as the material of the electrode3a,3b, such as gold, platinum, and alloy thereof. The shape of particles7may be bar shape, polygon, leaf shape, or teardrop shape.

FIGS.2D-2Eare schematic views of a semiconductor device1′ in accordance with another embodiment of the present disclosure. The top21aand top21bare not in the same horizontal height. The top21ais slightly lower than the top21b.FIG.2Eis a cross-sectional view of a semiconductor device1′ taken along line B-B′ ofFIG.2D. The conductive bump2ais above the mesa16. When the volume of the conductive bump2ais similar to that of the conductive bump2b, because a portion of the conductive bump2afills the mesa16, the top21aof the conductive bump2ais slightly lower than the top21bof the conductive bump2b. In an embodiment, the first thickness H1of the first conductive bump2ais 0.4 to 1 μm less than the second thickness H2of the second conductive bump2b.

FIG.3Ais a top view of a semiconductor device1in accordance to an embodiment of the present disclosure.FIG.3Bis a cross-sectional view of a semiconductor device1taken along line C-C′ ofFIG.3A.FIG.3Cis a cross-sectional view of a semiconductor device1taken along line D-D′ ofFIG.3A. The semiconductor device1includes a semiconductor stack14and an electrode3as well as a conductive bump2on the semiconductor stack14. The projected shape of the conductive bump2and the electrode3inFIG.3Ais substantially a rectangle. The outermost surface22of the conductive bump2has a macroscopically smooth and convex arc shape in the cross-sectional view. The outermost surface22is in contact with the upper surface of the electrode3, and a tangent line of the outermost surface22at the contact point forms an angle θ1 with respect to the upper surface of the electrode3. The angle θ1 is about 90° and can be in a range of 70°<θ1<90°. As shown inFIG.3C, the outermost surface22is in contact with the upper surface of the electrode3, and a tangent line of the outermost surface22at the contact point forms an angle θ2 with respect to the upper surface of the electrode3. Angle θ2 is smaller than angle θ1 and can be in a range of 30°<θ2<70°. In other words, as shown inFIG.3A, the cross-sectional shape of the conductive bump2in a direction that is parallel to the side length of the electrode is not equal to a cross-sectional shape of the conductive bump in a direction of a diagonal line D-D′ of the electrode3.

FIG.4Ashows a semiconductor device arrangement2000in accordance with an embodiment of the present disclosure. The semiconductor device arrangement2000includes a plurality of semiconductor devices1and a carrier30. For simplicity, only three of the semiconductor devices1in one dimension are shown inFIG.4A, but the semiconductor device arrangement2000may include m*n numbers of the semiconductor devices1, wherein m, n are positive integers. The semiconductor devices1are disposed on the carrier30in a way that the conductive bumps2facing the carrier30(or called “flip-chip”). The carrier30may support and fix the semiconductor device1. The carrier30includes a carrier plate31and an adhesive structure32, wherein the material of the carrier plate31may be a light-transmitting material that can be transmitted by a light with a specific wavelength emitted by the LED or laser diode (LD), such as glass, sapphire, or polymer material. The adhesive structure32may include a thermal release tape, UV release tape, chemical release tape, heat resistant tape, blue tape, or tapes with dielectric release layer. In another embodiment, the adhesive structure32may also include a polymer, such as a polyimide and benzocyclobutane (BCB). When the semiconductor devices1are arranged on the carrier30in the form of “flip chip”, the smooth and convex outermost surfaces22of the conductive bumps2are in contact with the adhesive structure32. As shown in theFIG.4A, the conductive bumps2may have an embedded portion that is partially embedded in the adhesive structure32. The embedded portion of each of the conductive bumps2has a maximum width W3parallel to the surface of the adhesive structure32, and the conductive bump2has a maximum width W4, wherein W4>W3. Besides, the outermost surface22of each of the conductive bumps2is smooth and arc-shaped, and, in a selected projection direction, the projected area of the portion of each of the conductive bumps2embedded in the adhesion layer (such as the area of the indentation34inFIG.4C) is less than the area of the electrode3and has a lower adhesive force, which is beneficial for the subsequent transferring process for transferring the semiconductor devices1from the carrier30to another location. The transferring process of the semiconductor devices1will be described in the paragraphs below.

FIGS.4B and4Cshow a side view and a top view of a semiconductor device arrangement2000ofFIG.4Aafter removing one semiconductor device1. Referring toFIG.4C, in the top view, the upper surface of the carrier30can define a removal area33(as in dotted line), representing an exposed region on the carrier30after removing a semiconductor device1. An indentation34is included in the removal area33. The indentation34is a region, which is formed by pressing the conductive bump2to the adhesive structure32, and the indentation34has a projected area in the top view. According to the experimental results, when the ratio of the projected area of the indentation34to the projected area of the semiconductor device1is less than 0.2, it is easier to pick up the semiconductor device1from the carrier30and move it to another location.

FIGS.4D and4Erespectively show semiconductor device arrangements3000and3001in accordance with other embodiments of the present disclosure.FIG.4Dshows a semiconductor device arrangement3000, and the semiconductor device arrangement3000includes a plurality of semiconductor devices1and a carrier30. The carrier30includes a carrier plate31and an adhesive structure32. The plurality of semiconductor devices1is disposed on the carrier30in a way that the conductive bumps2facing the carrier30. The conductive bumps2and the electrodes3are completely embedded in the adhesive structure32and are completely wrapped by the adhesive structure32. The adhesive structure32covers the lower surface of the semiconductor device1which is not covered by the electrode3. By being temporarily fixed onto the adhesive structure32, the positions of the semiconductor devices1on the carrier30can be maintained and are not easy to be changed during the subsequent processes.FIG.4Eshows another semiconductor device arrangement3001. The semiconductor device arrangement3001includes a plurality of semiconductor devices1and a carrier30. The carrier30includes a carrier plate31and a plurality of sub-adhesive structures32″ separated from each other, and the horizontal position and width of a sub-adhesive structure32″ are corresponded to a semiconductor device1. As shown inFIG.4E, an aisle35with a width greater than 0 is between two adjacent sub-adhesive structures32″. The plurality of semiconductor devices1is disposed on the carrier30in such a way that the conductive bumps2facing the carrier30. The conductive bumps2and the electrodes3are completely embedded in the sub-adhesive structure32″ and are completely wrapped by the sub-adhesive structure32″. The sub-adhesive structure32″ covers the lower surface of the semiconductor device1which is not covered by the electrode3.

FIGS.5A-5Dshow a procedure for transferring the semiconductor device1by a transferring structure40. As shown inFIG.5A, a plurality of semiconductor devices1is arranged in an array on the carrier30. The plurality of semiconductor devices1is in contact with the adhesive structure32of the carrier30by portions of the surfaces of the conductive bumps2so the plurality of semiconductor device1can be temporarily fixed onto the carrier30. A transferring structure40is provided to transfer the semiconductor device1from the carrier30to another location. The transferring structure40has a plurality of grabbing portions41, and each of the grabbing portions41is corresponded to the position of the semiconductor device1which is ready to be picked up. As shown inFIG.5B, the transferring structure40moves close to the plurality of semiconductor devices1. After the grabbing portions41contacts some of the plurality of semiconductor devices1, the transferring structure40moves upward so that the semiconductor devices1grabbed by the grabbing portions41leave the carrier30. The adhesion between the grabbing portion41and the semiconductor device1is greater than the adhesion between the semiconductor device1and the carrier30. The semiconductor devices1, which are not contacted by the grabbing portions41, stay on the carrier30.

As shown inFIG.5C, the transferring structure40moves to a position above a predetermined place of the target substrate50together with the semiconductor devices1temporarily fixed on the grabbing portions41. At this predetermined place, the semiconductor devices1may directly or indirectly contact the target substrate50, and eventually be placed or fixed on the target substrate50. As shown inFIG.5D, the semiconductor devices1leave the transferring structure40and stay on the target substrate50, while the transferring structure40may move to the same or a different carrier30to grab other semiconductor devices1. The transferred semiconductor devices1are disposed on the substrate50in such a way that the conductive bumps2face the target substrate50. The target substrate50may be a circuit board of a display, a thin-film transistor (TFT) substrate, a substrate having a redistribution layer (RDL), or a sub-mount substrate of a package. In another embodiment, the target substrate50may be a temporary carrier similar to the carrier30. In FIGS.5A-5D, the connection mode of the semiconductor device1and the carrier30is not limited to the form shown inFIG.4A, and may be the forms shown inFIGS.4D and4E.

FIGS.6A-6Care schematic views of a procedure for transferring the semiconductor device1in accordance with another embodiment of the present disclosure.FIG.6Ashows a plurality of semiconductor devices1disposed in an array on the carrier30. Each semiconductor device1is in contact with the adhesive structure32of the carrier30by a portion of the surfaces of the conductive bumps2so the plurality of semiconductor devices1can be temporarily fixed onto the carrier30. Then, the structure ofFIG.6Ais flipped over or the target substrate50is moved, and such that the plurality of semiconductor devices1can be located between the carrier30and the target substrate50wherein the plurality of semiconductor devices1does not contact the target substrate50. For example, as shown inFIG.6B, the semiconductor device1is suspended over the target substrate50. A laser energy L1is provided to irradiate a specific place of the adhesive structure32from the side of the carrier plate31, wherein the specific place corresponds to one of the semiconductor devices1which is ready to be transferred. The laser energy L1may be a single-shot laser or a multi-shots laser. In an embodiment, one of the semiconductor devices1or a specific position of the adhesive structure32may be irradiated by one or more shots of laser during one irradiation process. In another embodiment, multiple places of the semiconductor devices1or of the adhesive structures32may be irradiated by one or more shots of laser, respectively, during one irradiation process. As shown inFIG.6C, the adhesive structure32irradiated by the laser energy L1may reduce the adhesion between the semiconductor device1and the adhesive structure32, or cause the downward movement force of the semiconductor device1to be greater than the adhesion of the adhesive structure32to the semiconductor device1, so that the semiconductor device1drops to the target substrate50from the carrier30. The transferred semiconductor devices1are disposed on the target substrate50with the conductive bumps2being away from the substrate50. In another embodiment, in the step ofFIG.6B, the semiconductor devices1may contact the target substrate50first, and then, be irradiated by the laser energy L1, so that the semiconductor devices1may align to the target substrate50more precisely. After the step ofFIG.6C, a removal step may be optionally applied to the semiconductor devices1to remove the remaining sub-adhesive structure32″ on the semiconductor devices1. The removal step may include a dry etch or a wet etch, and the dry etch may be an oxygen plasma etching process. InFIGS.6A-6C, the connection mode of the semiconductor devices1and the carrier30is not limited to the form shown inFIG.4A, and may also be the form shown inFIGS.4D and4E.

FIGS.7A-7Dare schematic views of a procedure for forming a semiconductor device1in accordance with an embodiment of the present disclosure. As shown inFIG.7A, a plurality of semiconductor units200is disposed on a substrate10. The semiconductor unit200includes a semiconductor stack14, a protective layer15, a first electrode3a, and a second electrode3b. The plurality of semiconductor units200is disposed on the substrate10with the first electrodes3aand the second electrodes3bbeing away from the substrate10. The first electrode3aand the second electrode3bhave recesses respectively. For the structures of the first electrode3aand the second electrode3b, references can be made to the aforementioned relevant paragraphs. Then, for each of the plurality of semiconductor units200, two lumps of glue material80separated from each other are formed over the first electrode3aand the second electrode3b, respectively. The glue material80includes resin81and a plurality of conductive particles82distributed in the resin81. In an embodiment, the glue material80may be formed by printing, coating, spraying, or dispensing. The printing may include aerosol jet printing or ink-jet printing. The material of the resin81includes thermosetting plastics and a soldering flux. The thermosetting plastics may be epoxy, silicone, polymethylmethacrylate (PMMA), or episulfide. The melting point of the conductive particle82is lower than the solid point of the resin81. In an embodiment, the material of the conductive particle82may be gold, silver, or copper. In another embodiment, the material of the conductive particle82may be a low melting point metal or a low liquidus melting point alloy. In an embodiment, the melting point of the low melting point metal or the liquidus temperature of the low liquidus melting point alloy is lower than 210° C. In another embodiment, the melting point of the low melting point metal or the liquidus temperature of the low liquidus melting point alloy is lower than 170° C. The material of the low liquidus melting point alloy may be a tin alloy, such as a tin-indium alloy and tin-bismuth alloy.

As shown inFIG.7B, a laser energy L2is used to irradiate the glue material80or neighboring regions thereof to heat the glue material80. The laser energy L2may include UV laser beam, visible light laser beam, or IR laser beam. In an embodiment, the laser energy L2is an IR pulse mode laser beam with wavelength of 750-2000 nm, spot size of 0.004-0.002 cm2, beam diameter of 100-500 μm, pulse width (duration) of less than 20 ms, frequency of 500-4000 Hz, duty cycle of 1%-10%, laser power of 100 W, and laser energy of 595-850 J/cm2. As shown inFIG.7C, during the heating process, the conductive particles82gather on the first electrode3aand the second electrode3bto form the first conductive bump2aand the second conductive bump2b, wherein the first conductive bump2aand the second conductive bump2bare convex and have arc outer surfaces. A semiconductor unit200with the first conductive bump2aand the second conductive bump2bhere is called a semiconductor device1. In one embodiment, a portion of the resin81moves over the first conductive bump2a, second conductive bump2b, and the region18between the first electrode3aand the second electrode3b. After the heating process, the first conductive bump2aand the second conductive bump2bare cured, and the resin81covering the first conductive bump2aand the second conductive bump2bis also heated but not completely cured, so the resin81is in a liquid or semi-liquid state. Then, as shown inFIG.7D, a cleaning step is performed to remove the uncured resin81so that the first conductive bump2aand the second conductive bump2bare exposed to the external environment for contacting the carrier plate in subsequent transferring process. The cleaning process may be performed with a solvent, and the solvent may include N-methylpyrrolidinone (NMP), methyl ethyl ketone (MEK), acetone (ACE), or isopropyl alcohol.

FIGS.8A-8Dare schematic views of a procedure for forming the semiconductor device1in accordance with another embodiment of the present disclosure. As shown inFIG.8A, a plurality of semiconductor units200′ is disposed over a substrate10. The semiconductor unit200′ includes a semiconductor stack14, a protective layer15, a first electrode3a, and a second electrode3b. The plurality of semiconductor units200′ is disposed over the substrate10with the first electrode3aand the second electrode3bbeing away from the substrate10. The first electrode3aand the second electrode3bhave recesses respectively. For the structures of the first electrode3aand the second electrode3b, references can be made to the aforementioned relevant paragraphs. A first bonding pad23aand a second bonding pad23bare formed respectively on the first electrode3aand the second electrode3bby using a method of electroplating, chemical plating, or evaporation deposition. The upper surface24aof the first bonding pad23aand the upper surface24bof the second bonding pad23bare substantially conformal with the upper surface of the first electrode3aand the second electrode3b(i.e., the profiles of the both are similar). A single lump of the glue materials83is formed over the semiconductor unit200′, first bonding pad23a, and the second bonding pad23bof each of the plurality of semiconductor units200′. The glue material83only includes resin in this example. In another embodiment, the glue material83includes resin and lower concentration conductive particles (compared to the conductive particles ofFIG.7A). In an embodiment, the forming of the glue material80may be printing, coating, spraying, or dispensing. The printing may include aerosol jet printing or ink-jet printing. For the material of the first bonding pad23aand the second bonding pad23b, references can be made to the aforementioned relevant paragraphs of the conductive bump2a,2b. For the material of the resin, reference can be made to the aforementioned relevant paragraphs.

As shown inFIG.8B, the first bonding pad23aand the second bonding pad23bor neighboring regions thereof are irradiated with a laser energy L3to heat the glue materials83, first bonding pad23a, and the second bonding pad23b. The laser energy L3may include UV laser beam, visible light laser beam, or IR laser beam. In an embodiment, the laser energy L3is IR laser beam with the wavelength of 750-2000 nm. As shown inFIG.8C, during the heating process, the first bonding pad23aand the second bonding pad23bare heated to melt in the glue material83and gather on the first electrode3aand the second electrode3b(if the resin includes conductive particles, some or all of the heated conductive particles may also move toward the first electrode3aand the second electrode3b) to form a first conductive bump2aand the second conductive bump2b, wherein the first conductive bump2aand the second conductive bump2bare convex and have arc outer surfaces. A semiconductor unit200′ with the first conductive bump2aand the second conductive bump2bhere is called a semiconductor device1. A portion of the glue material83moves over the first conductive bump2a, the second conductive bump2b, and the region18between the first electrode3aand the second electrode3b. After the heating process, the first conductive bump2aand the second conductive bump2bare cured, and the glue material83(or resin) covering thereon is heated but not completely cured, so the resin81is in a liquid or semi-liquid state. Then, as shown inFIG.8D, a cleaning process is performed to remove the uncured glue material83(or resin) so that the first conductive bump2aand the second conductive bump2bare exposed to external environment for contacting the carrier plate in subsequent transferring process. For the cleaning process, reference can be made to the aforementioned relevant paragraphs ofFIG.7D.

In another embodiment, during the cleaning process ofFIGS.7D and8D, if the glue material between the conductive bumps2aand2bis not cleaned completely and remained on the semiconductor1, the maximum horizontal height of the remaining glue material is better not higher than the conductive bumps2aand2bfor preventing from affecting the subsequent transfer and die-bonding process.

FIG.9Ais a three-dimensional view of a semiconductor device20in accordance with another embodiment of the present disclosure.FIG.9Bis a cross-sectional view taken along the line B-B′ of the semiconductor device20ofFIG.9A. Referring toFIG.9A, the upper side of the semiconductor device20has a first conductive bump2aand a second conductive bump2bseparated from each other. Between the first conductive bump2aand the second conductive bump2b, at least one lump of remaining glue material84is covered on the semiconductor device20. In the top view, two lumps of remaining glue material84have irregular shapes and different areas. Referring toFIG.9B, the semiconductor device20has a semiconductor stack14, a protective layer15, a first electrode3a, a second electrode3b, a first conductive bump2a, and a second conductive bump2b. The outermost side19of the semiconductor stack14is an inclined plane that is not perpendicular to the upper surface1051of the substrate10. The semiconductor stack14includes a first semiconductor layer11, an active layer12, and a second semiconductor layer13. The remaining glue material84is on the protective layer15between the first conductive bump2aand the second conductive bump2b. The uppermost surface of the remaining glue material84is not higher than the maximum horizontal height of the first conductive bump2aand the second conductive bump2b. Since the height of the remaining glue material84is not beyond that of the conductive bump2aand2b, the subsequent transferring and die-bonding process may not be affected.

FIGS.10A-10Eare schematic views of a procedure for transferring the semiconductor device20′ in accordance with another embodiment of the present disclosure. The structure of the semiconductor device20′ can refer to the figures and paragraphs related to the semiconductor devices1,1′, and20, and the structure of the semiconductor device arrangement5001can refer toFIG.4Eand the paragraphs related to the semiconductor device arrangement3001. Wherein the semiconductor device arrangement5001includes a plurality of semiconductor units300arranged on the carrier30in the form of flip. The first bonding pad53aand the second bonding pad53bare respectively arranged below the first electrode3athe second electrode3bof the semiconductor unit300.

InFIG.10A, a plurality of semiconductor units300is disposed on the carrier30in a way that the electrodes3aand3b(bonding pads53aand53b) facing the carrier30. The carrier30includes a carrier plate31with an upper surface and a plurality of sub-adhesive structures32″ separated from each other located on the upper surface thereof, and one sub-adhesive structure32″ is located under one semiconductor unit300. The horizontal position and width of a sub-adhesive structure32″ are corresponded to a semiconductor unit300. An aisle53with a width greater than 0 is between two adjacent sub-adhesive structures32″. The plurality of semiconductor units300is disposed on the carrier30in such a way that the bonding pads53aand53bare facing and embedded in the sub-adhesive structure32″. The carrier30has a roughly square or round shape, and the material can be referred to the aforementioned paragraphs related to the substrate10. In this step, the first bonding pad53aand the second bonding pad53bare located on electrodes3aand3brespectively, and the outer surfaces54aand54bare roughly conformal to the upper surfaces of the first electrode3aand the second electrode3b, that is, the contours of the two are similar. In one embodiment, the outer surface of the sub-adhesive structure32″ is not coplanar with the outermost side of the semiconductor unit300and may be retracted or protruded relative to the outermost side of the semiconductor unit300.

Then, as shown inFIG.10B, a mask5300is arranged above the corresponding position of the semiconductor device arrangement5001. The mask5300includes a translucent substrate5301(e.g., glass, quartz, sapphire) and a light-shielding metal layer5302(e.g., gold, chromium, tungsten) located on it. The light-shading metal layer5302has an opening5305, and the size of the opening corresponds to a semiconductor unit300below or an array region containing a plurality of semiconductor units300(not shown), which can be an array of m′×n′ semiconductor units300, wherein m′ and n′ are positive integers, and m′ and n′ are not 1 at the same time. In this embodiment, since the laser energy L4is irradiated to the semiconductor unit300through the opposite side of the substrate31, a material that the laser energy L4can penetrate is selected as the substrate31.

Then, as shown inFIG.10C, a laser energy L4from the top of the mask5300is passing through the position of the opening5305to irradiate one or a plurality of semiconductor units300below. The semiconductor unit(s)300irradiated by the laser energy L4is formed as semiconductor device(s)20′. More specifically, the laser energy L4is irradiated through the opening5305towards the first bonding pad53aand the second bonding pad53bof the semiconductor unit300or the neighboring regions thereof, and the laser energy L4may be a single-shot laser or a multi-shots laser. In other words, in one embodiment, the semiconductor unit(s)300may be irradiated with one-laser shot or multiple-laser shots during one irradiation process, and the first bonding pad53aand the second bonding pad53birradiated by the laser energy L4will be heated and gathered on the first electrode3aand the second electrode3b, forming the first conductive bump2aand the second conductive bump2bwith the aforementioned convex arc outer surfaces. In this step, the structure with conductive bumps2a,2bis called a semiconductor device20′. The contact area between the conductive bumps2aand2bof the semiconductor device20′ and the underlying sub-adhesive structure32″ is less than that of the bonding pads53aand53bof the semiconductor unit300. Therefore, the semiconductor device20′ is easier to be picked up in the semiconductor device arrangement5001than the semiconductor device300is. A more detailed mechanism will be described in the enlarged views of the followingFIGS.11A-11B.

Then, as shown inFIG.10D, a transferring structure500is provided to move the semiconductor device20′ from the carrier30to another place. In this embodiment, instead of using a protruding grabbing surface, the transferring structure500is a whole piece of an adhesive layer502(e.g., polydimethylsiloxan (PDMS) or adhesive tape with adhesive force), and the adhesive layer502has a grabbing surface501whose size is several times larger than the semiconductor device(s) to be picked-up. The transferring structure) moves close to the semiconductor unit(s)300and the semiconductor device(s)20′, and after the grabbing surface501contacts with the semiconductor unit(s)300and the semiconductor device(s)20′, it moves upwards so that the semiconductor device(s)20′ adhered to the grabbing surface501and leaving the carrier30(sub-adhesive structure32″), while the semiconductor unit300is not picked-up. At this time, the adhesion between the grabbing surface501and the semiconductor unit300is smaller than the adhesion between the semiconductor unit300and the sub-adhesive structure32″. However, the adhesion between the grabbing surface501and the semiconductor device20′ is greater than the adhesion between the semiconductor device20′ and the sub-adhesive structure32″. Therefore, after the transferring structure500leaves the sub-adhesive structure32″ upwardly, the semiconductor unit300below the transferring structure500can still remain on the carrier30, and the semiconductor device20′ can be selectively picked-up and temporarily fixed on the grabbing surface501.

Finally, the transferring structure500is moved to a predetermined position above a target substrate70together with the semiconductor device20′ temporarily fixed on the grabbing surface501. A surface circuit180can be selectively set at this predetermined position, and the transferred semiconductor device20′ may contact or not contact the target substrate70. As shown inFIG.10E, while the semiconductor device20′ is removed from the transferring structure500to the target substrate70, it can be welded (electrically connected) to the surface circuit180below by directly heating and melting the conductive bumps2aand2b.

In one embodiment, according to the optoelectronic characteristic requirements for the semiconductor device20′, the transferring structure500can be repeatedly moved to the same or different carriers30selectively grabbing the semiconductor devices20′ which meet the requirements thereon to the target substrate70. The selective transfer mode may transfer one semiconductor device20′ at a time, or transfer a plurality of semiconductor devices20′ in an array area at a time. The transferred semiconductor devices20′ are electrically connected to the surface circuit180arranged on the target substrate70in the manner described above. The target substrate70may be a circuit board of a display, a thin-film transistor (TFT) substrate, a substrate having a redistribution layer (RDL), or a sub-mount substrate of a package. In another embodiment, the target substrate70may be a temporary carrier similar to the carrier30without surface circuit thereon.

FIGS.11A-11Bare enlarged views of the area P before and after being irradiated by the laser energy L4inFIG.10C. As shown inFIG.11A, the semiconductor unit300includes a semiconductor stack14, a protective layer15, a first electrode3a, and a second electrode3b. The first bonding pad53aand the second bonding pad53bare respectively formed under the first electrode3aand the second electrode3bby electroplating, chemical plating, or evaporation. The outer surface54aof the first bonding pad53aand the outer surface54bof the second bonding pad53bare roughly conformal to the lower surfaces of the first electrode3aand the second electrode3b, that is, the contours of the two are similar. In addition, each of the outer surfaces54a,54bhas a concave portion corresponding to each of the upper electrodes3a,3b, a rougher texture (relative to the lower surfaces of electrodes3a,3b), or both. At this step, the first bonding pad53a, the second bonding pad53b, and the electrodes3aand3bare embedded in the sub-adhesive structure32″ and completely covered by the sub-adhesive structure32″. The sub-adhesive structure32″ is in direct contact with the outer surface15′ of the semiconductor unit300that is not covered by electrodes3aand3b. As shown in the figure, the shapes of the concave regions6a′ and6b′ constituted by the sub-adhesive structure32″ are corresponding to the first bonding pad23aand the second bonding pad23b.

As shown inFIG.11B, after irradiated by the laser energy L4, the first bonding pad53aand the second bonding pad53bare heated and melted in the sub-adhesive structure32″, and gathering under the first electrode3aand the second electrode3bto form a convex first conductive bump2aand a convex second conductive bump2bwith arc outer surfaces. The semiconductor unit300with a first conductive bump2aand a second conductive bump2bis called a semiconductor device20′. In more detail, since the first electrode3aand the second electrode3bare made of metal, when heated and melted, the first bonding pad53aand the second bonding pad53b, which are also made of metal, can aggregate inwardly based on the upper electrodes3aand3bto form conductive bumps2aand2bin order to have lower surface area and lower surface energy, respectively. Conductive bumps2aand2bcan push the sub-adhesive structure32″ and lift the semiconductor device20′ upwardly from the sub-adhesive structure32″. As shown inFIG.11B, the contact area between the conductive bumps2aand2band the sub-adhesive structure32″ is smaller than that of the first bonding pad53aand the second bonding pad53band the sub-adhesive structure32″ shown inFIG.11A, and the outer surface15′ of the semiconductor device20′ and the sub-adhesive structure32″ can be separated by a distance D1. The first conductive bump2ais located under the outer surface15′ of the semiconductor device20′, in the concave region6a, and includes a first portion2a-1in direct contact with the concave portion6aand a second portion2a-2not in direct contact with the concave portion6a. As a result, the adhesion of the semiconductor device20′ to the sub-adhesive structure32″ becomes smaller than that of the semiconductor unit300.

In one embodiment, the sub-adhesive structure32″ is cured after being heated and is in contact with the outer surface54aand54bof the bonding pad53aand53b. Therefore, when the semiconductor device20′ is removed, the inner contours of the corresponding bonding pads53aand53bare still retained in the concave regions6a′ and6b′. In another embodiment, the sub-adhesive structure32″ produces some fluidity when it is heated and melted, therefore, after the semiconductor device20′ is removed, the concave regions6a′ and6b′ become smoother and the roughness thereof decrease, and although the sub-adhesive structure32″ undergoes some deformation, the roughness of the concave regions6a′ and6b′ is still larger than that of the outer surfaces of the conductive bumps2aand2b.

FIGS.12A-12Dare schematic views of a procedure for transferring the semiconductor device20′ in accordance with another embodiment of the present disclosure. As shown inFIG.12A, the semiconductor device arrangement5001includes a plurality of semiconductor units300facing toward and in contact with the adhesive transferring structure500with the backsides thereof. In this embodiment, the transferring structure500includes a supporting layer503and an adhesive layer502(e.g., polydimethylsiloxan (PDMS)). The adhesive layer502includes a grabbing surface501, and the semiconductor units300are in contact with the grabbing surface501. The transferring structure500may optionally be subjected to a pressure toward the carrier30to ensure that the backsides of the semiconductor units300are contact to the grabbing surface501.

Then, as shown inFIG.12B, a mask5300is arranged above the semiconductor device arrangement5001. The mask5300includes a translucent substrate5301(e.g., glass, quartz, sapphire) and a light-shielding metal layer5302(e.g., gold, chromium, tungsten) located on it. The light-shading metal layer5302has an opening5305, and the size of the opening corresponds to a semiconductor unit300below or an array region containing a plurality of semiconductor units300

As shown inFIG.12C, a laser energy L5is provided from the top of the mask5300through the opening5305to one or a plurality of semiconductor units300. The semiconductor units300irradiated by the laser energy L4become semiconductor devices20′.

As shown inFIG.12D, when the carrier30is separated from the transferring structure500, the semiconductor device20′ can be separated from the sub-adhesive structure32″ and transferred to the grabbing surface501. Subsequently, referring toFIG.10E, the semiconductor device20′ is arranged to a predetermined position of the target substrate70by the transferring structure500.

FIGS.13A-13Dare schematic views of a procedure for transferring the semiconductor device20′ in accordance with another embodiment of the present disclosure. In this embodiment, a mask is not required. As shown inFIG.13A, a laser energy L6is applied directly to the surface of all semiconductor units300by scanning.

As shown inFIG.13B, after applying the laser energy L6, all semiconductor units300are formed into semiconductor devices20′, so the adhesion between the semiconductor devices20′ and carrier30(sub-adhesive structure32″) becomes smaller than that between semiconductor units300and carrier30(sub-adhesive structure32″). The structure and manufacturing methods of semiconductor units300and semiconductor devices20′ may be referred toFIGS.11A-11Band related paragraphs.

As shown inFIG.13C, the transferring structure500with a protruding grabbing portion504is used to pick up a specific semiconductor device20′ using an adhesive layer502with a protruding grabbing portion. In an embodiment, a grabbing portion504has a similar projected area with a semiconductor device20′, and a grabbing portion504may pick a semiconductor device20′ up at a time. After the transferring structure500is moved to a specific semiconductor device20′ and the grabbing portion504is in contact with the semiconductor device20′, the transferring structure500is moved upwards so that the semiconductor device20′ is picked up by the grabbing portion504and leaves the carrier30(sub-adhesive structure32″), and the semiconductor device20′ that is not in contact with the grabbing portion504remains on the carrier30(sub-adhesive structure32″). At this time, the adhesion between the grabbing portion504and the semiconductor device20′ is greater than the adhesion between the semiconductor device20′ and the carrier30(sub-adhesive structure32″). Subsequently, as mentioned above, the semiconductor device20′ is placed on a predetermined position of the target substrate (not shown) by the transferring structure500.

FIG.14shows a cross-sectional view of another semiconductor device arrangement6001. As shown inFIG.14, the semiconductor unit400is a vertical light-emitting diode chip. The semiconductor unit400includes a semiconductor stack14, a protective layer15, a first electrode3a, and a second electrode3b. The first bonding pad53ais formed under the first electrode3aby electroplating, chemical plating, or evaporation. The outer surface54aof the first bonding pad53ais roughly conformal with the lower surface of the first electrode3a, that is, the contours of the two are similar. The first electrode3aand the first bonding pad53aare positioned below the semiconductor stack14and are embedded in the sub-adhesive structure32″; The second electrode3bis located above the semiconductor stack14. In other words, the first electrode3a(and the first bonding pad53a) and the second electrode3bare respectively located on opposite sides of the semiconductor stack14. In addition, the upper surface of the semiconductor stack14can be selectively covered with a light-transmitting conductive layer77(e.g., indium-tin oxide) to increase the current diffusion effect on the surface of the semiconductor unit400.

As shown inFIG.14, a plurality of sub-adhesive structures32″ is arranged on the carrier30and separated from each other, and a sub-adhesive structure32″ is located below a semiconductor unit222and has a width substantially equal to that of a semiconductor unit222. There is an aisle63between the adjacent sub-adhesive structures32″ with a distance greater than 0. The method of transferring the semiconductor unit222in the semiconductor device arrangement6001may be referred toFIGS.5A-5D,FIGS.6A-6C,FIGS.10A-10E,FIGS.12A-12D,FIGS.13A-13C, and related paragraphs. Wherein, when a laser energy is applied to the semiconductor unit222, the adhesion between the semiconductor unit222and the carrier30(sub-adhesive structure32″) is reduced by simply converting the first bonding pad53aembedded in the sub-adhesive structure32″ into an arc-shaped conductive bump (not shown).

It should be understood that many of the above embodiments in this disclosure can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described. For example, in the preceding embodiments, the semiconductor unit and semiconductor device may contain a growth substrate or no growth substrate.

Although some embodiments of the present disclosure and their advantages have been described in detail, various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.