Semiconductor device having a ferroelectric TFT and a dummy element

The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 μm to 14 μm). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collisions of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device. More particularly the present invention relates to a semiconductor device including a semiconductor element such as a capacitor and a transistor in which a dielectric with high dielectric constant or a ferroelectric is used.

BACKGROUND OF THE INVENTION

With increases in the packing density of semiconductor memories, a capacitor element with larger capacity is needed. Therefore, a technology to integrate a capacitor element including a dielectric layer with high dielectric constant or a ferroelectric characteristics into a integrated circuit lately has attracted considerable attention.

In order to put a nonvolatile RAM into practice which enables writing and reading with lower operating voltage at higher speed compared to conventional devices, a technology to integrate a capacitor element including a ferroelectric layer has been pursued.

A conventional method for manufacturing a semiconductor device including a dielectric with high dielectric constant or a ferroelectric characteristics (hereinafter, a dielectric with high dielectric) is explained below referring toFIGS. 20A and 20B.

As shown inFIG. 20A, a first metal film202(e.g. a Pt film) is formed on a substrate201with an integrated circuit by sputtering. A dielectric film203with high dielectric constant is formed on the first metal film202by spin coating or chemical vapor deposition (CVD), followed by forming a second metal film204(e.g. a Pt film) on the dielectric film203by sputtering. After a photoresist209is formed on the second metal film204in a predetermined pattern, each film is selectively removed by dry etching to form a capacitor element208composed of first electrode205, a capacitor dielectric layer206and a second electrode207.

However, in such a capacitor element produced by the conventional method, a capacitor dielectric layer with high dielectric constant is degraded in electric characteristics. Such a degradation also is observed in a transistor including a dielectric layer with high dielectric constant.

SUMMARY OF THE INVENTION

Therefore, with the foregoing in mind, it is the object of the present invention to suppress a degradation of a dielectric with high dielectric constant in a semiconductor element.

In order to achieve the above-described object, an embodiment of the semiconductor device of the present invention comprises a substrate, a semiconductor element and a dummy semiconductor element. The semiconductor element includes a first dielectric layer on the substrate and an electrode on the first dielectric layer, and the dummy semiconductor element includes a second dielectric layer on the substrate and a dummy electrode on the second dielectric layer. The dummy semiconductor is located so that a space between the electrode and the dummy electrode is in a predetermined range. The predetermined range is preferably between 0.3 μm and 1.4 μm.

When the semiconductor element is a capacitor element, an embodiment of the semiconductor device of the present invention comprises a substrate, a capacitor element and a dummy capacitor element. The capacitor element includes a bottom electrode on the substrate, a first dielectric layer on the bottom electrode and a top electrode on the first dielectric layer, and the dummy capacitor element includes a dummy bottom electrode on the substrate and a second dielectric layer on the dummy bottom electrode and a dummy top electrode on the second dielectric layer. The dummy capacitor element is located so that a space between the top electrode and the dummy top electrode is in a predetermined range (e.g. 0.3 μm to 14 μm).

Two or more semiconductor elements can be included in the semiconductor device. In such a case, an embodiment of the semiconductor device of the present invention comprises a substrate, at least two capacitor elements, and a dummy capacitor element. Each capacitor element includes a bottom electrode, a first dielectric layer and a top electrode, and the dummy capacitor element includes a dummy bottom electrode, a second dielectric layer and a dummy top electrode as described above. The capacitor elements and the dummy capacitor element are located so that a space between an adjacent pair of electrodes selected from the top electrodes and the dummy top electrode, in which at least one electrode in the pair is one of the top electrodes, is in a predetermined range (e.g. 0.3 μm to 14 μm). The semiconductor device can include two or more dummy semiconductor devices.

Such a semiconductor device of the present invention can be manufactured by a method which comprises forming a dielectric film on a substrate, forming the electrically conductive film on the dielectric film, and etching the electrically conductive film so as to form the electrode. When etching the electrically conductive film, a dummy electrode is formed with the electrode so that a space between the electrode and the dummy electrode is in a predetermined range (e.g. 0.3 μm to 14 μm).

The inventors have succeeded in elucidating the degradation of the dielectric with high dielectric constant in a semiconductor element.

As shown inFIGS. 20A and 20B, the second metal film204is etched until the surface of the dielectric film202appears. As shown inFIG. 21, in the dry etching, etching ions210are partially accumulated on the dielectric film203so that the surface of the dielectric film203holds electrical charges211. In the case of a dielectric with high dielectric constant, the amount of electrical charges211is around 100 times as much as that in the case of silicon oxide or silicon nitride. The amount of electrical charges is proportional to the area of the surface exposed to the etching ions210.

Therefore, the large exposed surface of the dielectric film203with high dielectric constant causes an electrostatic repulsion between the etching ions210and the electrical charges211. As shown inFIG. 21, the repulsion changes the direction of travel212of the etching ions210around the photoresist209. The etching ions210deviate to the dielectric covered with the metal layer207, which will remain as a dielectric layer of a capacitor element. More collision of etching ions210with the dielectric below the edge portion of the metal layer207than usual generates defects in the crystal structure in the dielectric. Thus, a damaged region213, which causes the degradation in the capacitor element, is formed.

According to the present invention, the surface of the dielectric film exposed to the etching ions is limited by the dummy element, which can reduce the electrical charges on the dielectric film. Therefore, the collision with the etching ions proceeding diagonally is suppressed to prevent the semiconductor element from degrading in electrical characteristics.

These and other advantages of the present invention will become apparent those skilled in the art upon reading and understanding the following detailed description.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the semiconductor device of the invention, the space between the electrode and the dummy electrode is preferably in the range of 0.3 μm to 9 μm, more preferably in the range of 0.3 μm to 5 μm.

In the semiconductor device of the invention, the electrode and the dummy electrode are preferably composed of the same electrically conductive material. The electrode and the dummy electrode are preferably formed by etching the same electrically conductive film.

In the semiconductor device of the invention, the first dielectric layer is composed of the material selected from a dielectric material having a dielectric constant of 100 or more and a ferroelectric material.

In the semiconductor device of the invention, the first dielectric layer and the second dielectric layer are composed of the same dielectric material. The first dielectric layer and the second dielectric layer are preferably included in the same dielectric film. The first dielectric layer and the second dielectric layer are preferably formed by etching the same dielectric film.

Some embodiments of the present invention are explained below referring to the drawings.

First embodiment

As shown inFIGS. 1 and 2, in the semiconductor device, a capacitor element16formed on a substrate15is encircled by a dummy capacitor element17. The capacitor element16has a rectangular shape while the dummy capacitor element17has a frame-shape surrounding the capacitor element16entirely. The capacitor element16is composed of a first (bottom) electrode18, a capacitor dielectric layer19and a second (top) electrode20. The dummy capacitor element17is composed of a first dummy (a dummy bottom) electrode21, a dummy capacitor dielectric layer22and a second dummy (a dummy top) electrode23. As shown inFIG. 2, in the capacitor element16and the dummy capacitor element17, the corresponding layers have substantially the same thickness.

A method for manufacturing the semiconductor device is explained below referring toFIGS. 3Ato3D.

As shown inFIG. 3A, a first metal film24is formed on the substrate15including an integrated circuit at a thickness of 50 nm to 400 nm. A dielectric film25with high dielectric constant composed of e.g. SrBixTaxOy is formed on the first metal film24by spin coating or CVD. A second metal film26is formed on the dielectric film25at a thickness of 50 nm to 300 nm. The first and second metal films24and26can be composed of platinum and formed by sputtering. On the second metal film26, first photoresist layers27are formed in a predetermined pattern by photolithography.

Next, as shown inFIG. 3B, the second metal film26is removed selectively by dry etching to form the second electrode20and the second dummy electrode23.

After second photoresist layers28are formed in another predetermined pattern by photolithography as shown inFIG. 3C, the dielectric film25and the first metal film24are removed selectively by dry etching. As a result, a capacitor dielectric layer19, a first electrode18, a dummy capacitor dielectric layer22and a first dummy electrode21are formed as shown in FIG.3D.

Thus, the capacitor element16and the dummy capacitor element17are formed at the same time. In the semiconductor device, the space between the second electrode20and the second dummy electrode23is set in the range of 0.3 μm to 14 μm.

As shown inFIG. 4, in the step of etching the second metal film26to reveal the surface of the dielectric film25, the surface of the dielectric film25surrounding the second electrode20is limited by the second dummy electrode23. As a result, the amount of electrical charges29accumulated on the surface is less than that in the conventional method as shown inFIG. 21so that the electrostatic repulsion to etching ions30is reduced. Thus, the etching ions30can proceed to the dielectric film25without deviating in path. Therefore, the collision of the etching ions traveling diagonally with the dielectric below the second electrode20can be suppressed.

Second embodiment

As shown inFIGS. 5 and 6, in the semiconductor device, capacitor elements32and dummy capacitor elements33are arranged regularly on a substrate31including an integrated circuit. The capacitor elements32are arranged in the inner area of a broken line inFIG. 5while the dummy capacitor elements33are located to surround the capacitor elements32. The capacitor elements32and the dummy capacitor elements33have the same rectangular shape. Each capacitor element32is composed of a first electrode34, a capacitor dielectric layer35and a second electrode36. Each dummy capacitor element33is composed of a first dummy electrode37, a dummy capacitor dielectric layer38and a second dummy electrode39. As shown inFIG. 6, in the capacitor element32and the dummy capacitor element33, the corresponding layers have substantially the same thickness.

The semiconductor device can be produced by the same method as described above except for a pattern of the photoresist layers. The suitable materials for the layers also are the same as the first embodiment.

In the semiconductor device, each second electrode36is surrounded by four electrodes. The four electrode are selected from the other second electrodes36and the dummy electrodes39. The space between the second electrode26and the electrodes adjacent to the second electrode is set in the range of 0.3 μm to 14 μm.

Such an arrangement also can suppress the damage to the capacitor dielectric layer35. In addition, the dummy capacitor elements33can reduce the difference in electrical characteristics among the capacitor elements32, especially the difference between the outer elements and the inner elements.

The dummy capacitor element may have another shape such as a frame-like shape as described in the first embodiment.

Third embodiment

As shown inFIGS. 7 and 8, in the semiconductor device, a capacitor element42formed on a substrate41including an integrated circuit is encircled by a dummy capacitor element43. The capacitor element42composed of a first electrode44, a capacitor dielectric layer45and a second electrode46. The dummy capacitor element43is composed of a first dummy electrode47, a dummy capacitor dielectric layer48and a second dummy electrode49. As shown inFIG. 8, the first electrode44and the first dummy electrode47are included in the same electrically conductive film. The capacitor dielectric layer45and the dummy capacitor layer48also are included in the same dielectric film.

The semiconductor device can be produced by the same method as described above except for a pattern of the photoresist layers. The suitable materials for the layers also are the same as the first embodiment. The space between the second electrode46and the dummy electrode49is set in the range of 0.3 μm to 14 μm.

Such an arrangement also can suppress the damage of the capacitor dielectric layer45.

The semiconductor device described above or in the first embodiment may include two or more capacitor elements.

Fourth embodiment

As shown inFIGS. 9 and 10, in the semiconductor device, capacitor elements52and dummy capacitor elements53are arranged regularly on a substrate51including an integrated circuit. The capacitor elements52are arranged in the inner area of a broken line inFIG. 9while the dummy capacitor elements53are located to surround the capacitor elements52. Each capacitor element52is composed of a first electrode54, a capacitor dielectric layer55and a second electrode56. Each dummy capacitor element53is composed of a first dummy electrode57, a dummy capacitor dielectric layer58and a second dummy electrode59.

As shown inFIGS. 9 and 10, the first electrode54and the first dummy electrode57arranged in a line are included in the same electrically conductive film. The capacitor dielectric layer55and the dummy capacitor layer58in the line also are included in the same dielectric film. In the semiconductor device, lines including the capacitor elements52and the dummy capacitor elements53at both ends are arranged, except for the lines at both ends. The lines at both ends includes only the dummy capacitor elements53.

The semiconductor device can be produced by the same method as described above except for a pattern of the photoresist layers. The suitable materials for the layers also are the same as the first embodiment.

As described in the second embodiment, the space between the second electrode56and the electrodes adjacent to the second electrode56is set in the range of 0.3 μm to 14 μm.

Such an arrangement also can suppress the damage to the capacitor dielectric layer55and reduce the difference in electrical characteristics among the capacitor elements52. In addition, the semiconductor device has less undulations since some of the films remains without etching. Less undulations make wiring to the integrated circuit easier.

In the embodiments as described above, the electrode and the dummy electrode corresponding to the electrode are composed of the same material. The capacitor dielectric element and the dummy dielectric layer also are composed of the same material. The capacitor element is integrated into the circuit in the semiconductor device while the dummy capacitor element is produced not for being integrated into the circuit but for suppressing the collision of the etching ions with the dielectric in the capacitor element. As long as the desired object can be achieved, the shape, the material and the arrangement of the dummy element are not limited.

For example, electrically conductive oxides such as RuO2and IrO2can be used as a material for the electrode as well as various kinds of metal. Dielectric compounds such as BaxSr1-xTiOx, Pb(Zr1-xTix)O3, SrBi2(Ta1-xNbx)2O9, Bi4Ti3O12(0≦x≦1) can be used for the dielectric capacitor layer.

Fifth embodiment

Other semiconductor elements such as transistors also can be used for the semiconductor element of the present invention as well as capacitor elements.

FIG. 11shows an embodiment of a memory cell including a transistor97and a capacitor element98. In such a memory cell, the dummy elements as described above can be used for transmission and capacitor elements.

For example, in the case of a transistor, a gate electrode121on a substrate120corresponds to the top electrode in a capacitor element as shown inFIG. 13. Agate insulating layer (not shown inFIG. 13) corresponding to a capacitor dielectric layer in a capacitor element is formed between the substrate120and the gate electrode121. When forming a transistor, a dummy gate electrode122can suppress the degradation of the transistor as is in the case of a capacitor element. As shown inFIG. 13, a source electrode123and a drain electrode124formed in the substrate120is not necessary below the dummy gate electrode122.

In the memory cell inFIG. 11, a transistor97includes a gate87, a source85, a drain86and a gate insulating layer88composed of a ferroelectric material. The memory cell also has a capacitor element98including a bottom electrode91, a capacitor insulating layer92composed of a ferroelectric material and a top electrode93.

The transistor97and the capacitor element98are connected with other elements by bit lines89,90and95. A field oxide layer82and insulating layers83and84formed on a substrate81prevent unnecessary contacts between the elements.

A memory cell inFIG. 12also has transistors117including gates107, sources105, drains106, gate insulators103and gate insulating layers108composed of a ferroelectric material. On an insulating layer102, there are capacitor elements118including bottom electrodes111, capacitor insulating layers112composed of a ferroelectric material and top electrodes113.

The transistor117and the capacitor element118also are connected with each other and other elements by bit lines109,110and115. Insulating layers102and104prevent unnecessary contacts between the elements. In the memory cells as shown inFIGS. 11 and 12, dummy capacitor elements and/or dummy transistors (dummy gate electrodes) can be used for preventing degradation of the layer composed of the dielectric with high dielectric constant.

The semiconductor device for which the dummy element can be used is not limited to the memory cells as described above.

EXAMPLE

The devices as shown inFIGS. 14to16were produced. In the semiconductor device, capacitor elements61, first dummy capacitor elements62and second dummy capacitor elements63were arranged on a substrate60.

As shown inFIGS. 14 and 15, in the capacitor elements61and the first dummy capacitor elements62, a first electrode64and a first dummy electrode67are included in the same electrically conductive film. A capacitor dielectric layer65and a dummy capacitor dielectric layer68also are included in the same dielectric film. As shown inFIG. 15, the first dummy capacitor elements62are located at the end of the line including the capacitor elements61and the first dummy capacitor elements62.

As shown inFIGS. 14 and 16, only the second dummy capacitor elements63are provided at the line at the end. In the second dummy capacitor elements63, first dummy electrodes71are included in the same electrically conductive film and dummy dielectric capacitor layers72are included in the same dielectric film.

The space α between a second electrode66and a second dummy electrode69in the first dummy capacitor element62was set at 1.5 μm. The space β between the second electrode66and a second dummy electrode73in the second dummy capacitor element63was set at 12.8 μm. The devices were produced by the process as described above. The capacitor dielectric layer was composed of SrBixTaxOy at a thickness of 0.24 μm. The electrodes were composed of Pt.

On the other hand, semiconductor devices were produced in the same way but without the first dummy elements62and the second dummy elements63. Remnant polarization in each device was measured.

As shown inFIG. 17, remnant polarization in the devices with the dummy elements was 13 μC/cm2to 15 μC/cm2. As shown inFIG. 18, remnant polarization in the devices without the dummy elements was 5 μC/cm2to 10 μC/cm2. Thus, the dummy elements can improve and stabilize remnant polarization in the capacitor elements. Therefore, for example, the dummy elements can expand a margin for error in reading data from the device.

The relationship between the space β and the remnant polarization was investigated. As shown inFIG. 19, when the space β was above 14 μm, the remnant polarization sharply dropped (line A). In this case, the size of the second electrodes66and the second dummy electrodes69and73were 5×5 μm. When the size of the electrodes was set at 1.5×1.5 μm, the remnant polarization sharply dropped in the range above 9 μm. When the size of the electrodes was set at 1×1 μm, the remnant polarization sharply dropped in the range above 5 μm. The space β below 0.3 μm makes it difficult to produce the elements. The same results were observed when the space α was changed instead of the space β.