Thermal control apparatus and methodology

Various embodiments of a thermal control methodology and apparatus are disclosed. In one embodiment, an integrated circuit includes one or more thermal sensors, comparison circuitry, and control circuitry. The comparison circuitry is configured to receive temperature readings from the one or more thermal sensors. The control circuitry is configured to reduce a performance level of one or more controlled subsystems responsive to the comparison circuitry determining that at least one temperature reading from the one or more thermal sensors exceeds one of one or more threshold values. A software-based thermal control mechanism may also execute concurrently with the apparatus.

BACKGROUND

1. Field of the Invention

This disclosure is related to electronic systems, and more particularly, to the thermal control of electronic systems.

2. Description of the Related Art

As the number of transistors implemented integrated circuits (ICs) has increased, the management of issues related to temperature has increased in importance. In many ICs, a large number of transistors operating at the same time can produce a significant amount of heat. If left unchecked, the amount of heat generated by the operation of the transistors of an IC may cause erroneous operation or permanent damage.

Temperature sensors are implemented on many different types of ICs. One or more temperature sensors may be place on an IC die and may be used to determine a temperature at a respective location thereon. The temperature sensors may measure and report temperature information to other circuitry, such as one or more registers. In some IC's, such as various types of processors and systems on a chip (SOCs), software may be executed that monitors the registers. If a temperature exceeding a predefined threshold is detected, the software may initiate actions to shut down one or more portions of the IC.

SUMMARY

Various embodiments of a thermal control methodology and apparatus are disclosed. In one embodiment, an integrated circuit includes one or more thermal sensors, comparison circuitry, and control circuitry. The comparison circuitry is configured to receive temperature readings from the one or more thermal sensors. The control circuitry is configured to reduce a performance level of one or more controlled subsystems responsive to the comparison circuitry determining that at least one temperature reading from the one or more thermal sensors exceeds one of one or more threshold values.

In one embodiment, the comparison circuitry and the control circuitry may operate in parallel with a software temperature control routine executed on a processor. Thus, the system may include both hardware and software thermal monitoring and control mechanisms. The hardware mechanism (including, e.g., comparison circuitry) may monitor temperature readings received from the one or more temperature sensors more frequently than the software mechanism. If the hardware mechanism determines that a temperature reading exceeds a temperature threshold, then the hardware mechanism may cause a corresponding reduction to a performance level to at least a corresponding functional unit of the IC. This reduction in the performance level may allow the temperature at the reporting sensor to fall back below the temperature threshold prior to being checked by the software mechanism.

In one embodiment, multiple temperature thresholds may be used. For example, the control circuit may reduce the performance of a controlled subsystem by a first amount responsive to determining that a corresponding temperature value has exceeded a first threshold, or by a second amount responsive to determining that the corresponding temperature value has exceeded a second threshold. The second threshold may be greater than the first threshold. The software mechanism may shut down the controlled subsystem (as well as other portions of the integrated circuit, in some embodiments) if a corresponding temperature reading exceeds the second threshold. In some embodiments, the software mechanism may take no action upon determining that a temperature reading exceeds the first threshold. Thus, the hardware mechanism may be allowed an opportunity to maintain the temperature of various subsystems of the integrated circuit within safe limits without having to perform a complete shutdown. The software mechanism may perform a shutdown of one or more controlled subsystems only after the hardware mechanism is no longer able to maintain respective temperatures within safe limits.

Various types of performance reductions may be performed by the control circuitry in different embodiments of the hardware mechanism. For example, the frequency of a clock signal provided to a controlled subsystem may be reduced responsive to a temperature reading exceeding a threshold in one embodiment. Other types of performance reductions may include operating voltage reductions, bandwidth limitations, re-allocation of a workload to another subsystem (e.g., from one processor core to another) and so forth.

Various units, circuits, or other components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits and/or memory storing program instructions executable to implement the operation. The memory can include volatile memory such as static or dynamic random access memory and/or nonvolatile memory such as optical or magnetic disk storage, flash memory, programmable read-only memories, etc. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, paragraph six interpretation for that unit/circuit/component.

DETAILED DESCRIPTION OF EMBODIMENTS

Turning now toFIG. 1, a block diagram of one embodiment of an integrated circuit (IC) is shown. In the embodiment shown, IC10is a system-on-a-chip (SoC) including processor cores12and14, a graphics unit16, and an on-chip memory18. Memory18in the embodiment shown may be a read-only memory (ROM), a flash memory, a random access memory, or any other suitable memory type. IC10also includes various thermal control mechanisms to monitor and regulate its temperature during operation. In this example, processor cores12and14and graphics unit16each include a temperature sensor11. Each of the temperature sensors11is coupled to trip point circuit13, which is configured to compare temperatures readings received from each of the thermal sensors to one or more threshold values. IC10also includes a thermal control circuit15that is coupled to receive comparison information from trip point circuit13. In this particular embodiment, thermal control circuit15may adjust performance levels of the various functional units (or subsystems) of IC10by changing the frequencies of respectively received clock signals. Embodiments are also possible and contemplated in which thermal control circuit15may perform other control actions to adjust respective performance levels. Such action may include, but are not limited to, voltage adjustments, bandwidth adjustments, workload allocation/re-allocation, and so on.

Trip point circuit13and thermal control circuit15may comprise a hardware-based thermal control mechanism. That is, the hardware-based thermal control mechanism in the embodiment shown is implemented using hardware circuits of IC10. IC10in this embodiment is also configured to implement a software-based thermal control mechanism that may run in parallel with, and complementary to, the hardware-based thermal control mechanism. More particularly, instructions for implementing software-based thermal control mechanism (SWTCM)19are stored in memory18in this embodiment. The instructions of SWTCM19may be accessed by processor core12, which may execute the instructions to carry out a software-based thermal control routine. During execution of instructions of SWTCM19, processor core12may access temperature comparison results from trip point circuit13, and may take thermal control actions based thereupon.

As noted above, trip point circuit13may compare received temperature readings to one or more temperature thresholds. These thresholds may be programmable, or may be hardwired into trip point circuit13. In either case, reporting of the comparison results to thermal control circuit15may be performed at pre-defined intervals. Concurrent with operation of the hardware-based thermal control mechanism, instructions of SWTCM19executed by processor12may access comparison results from trip point circuit13at its own pre-defined intervals. In the embodiment shown, the intervals at which trip point circuit13reports comparison results to thermal control circuit15may be shorter in duration than the intervals at which SWTCM19accesses comparison information from trip point circuit13. Thus, thermal control circuit15may receive updated comparison information more frequently than comparison information is received by instructions of SWTCM19executed by processor core12.

Thermal control circuit15in the embodiment shown is coupled to receive three different clock signals, CPU1Clk, CPU2Clk, and Graphics Clock. Corresponding output clock signals Clk1, Clk2, and Clk3, are provided from thermal control unit15to processor core12, processor core14, and graphics unit16, respectively. The input clock signals may essentially serve as full frequency reference clock signals for their corresponding output clock signals. Thermal control circuit15in this particular embodiment may reduce the performance of any of processor cores12and14and graphics unit16by dividing the input clock signals to produce respective output clock signals at a reduced frequency. In this embodiment, the clock signals may be divided independently of one another such that some units may operate in a reduced performance mode while others may operate in a full (normal) performance mode.

Since the hardware-based thermal control mechanism updates at more frequent intervals than the software-based thermal control mechanism, the hardware-based mechanism may provide finer grain thermal control functionality for IC10. Accordingly, as noted above, the hardware-based thermal control mechanism may perform various types of performance adjustments to IC10responsive to certain comparison results. For example, if a temperature reading exceeds a first temperature threshold, thermal control circuit15may reduce, by a first amount, the performance of a functional unit associated with the reporting temperature sensor11. If the temperature reading exceeds a second temperature threshold, thermal control circuit may reduce, by a second amount, the performance of the functional unit associated with the reporting temperature sensor. Using the example of a clock frequency, thermal control circuit15may reduce the frequency of a corresponding clock signal by a first amount if the first temperature threshold is exceeded, and may reduce the frequency of the corresponding clock signal by a second amount if the second temperature threshold is exceeded. In this particular example, the thermal control action was performed with respect to only the functional unit associated with the reporting temperature sensor. However, embodiments are possible and contemplated wherein performance reductions may be performed to additional functional units responsive to a temperature reading exceeding one of the thresholds. It is further noted that, responsive to a temperature reading falling below one of the threshold values, performance may be restored to values from which they were previously reduced.

The hardware thermal control mechanism may include hysteresis in its operation. Thermal control circuit15may not immediately reduce the performance level of one or more of the functional units responsive to an initial indication of a temperature reading from a particular temperature sensor11exceeding a threshold. Instead, thermal control circuit15may wait for a predetermined time. If, after the predetermined time has elapsed, the temperature reading from the particular temperature sensor11is still above the threshold, thermal control circuit15may perform a thermal control action, such as a reduction of clock frequency to at least the corresponding functional unit. If, on the other hand, the temperature reading from the particular temperature sensor11falls back below the threshold voltage before the predetermined time has elapsed, thermal control circuit15may maintain the performance level of the corresponding functional unit at its current level.

Hysteresis may also be used in boosting performance levels when a temperature falls below a temperature threshold. In the embodiment shown, thermal control unit15may wait another predetermined time to boost the performance of a functional unit after a corresponding temperature reading has fallen below a given threshold. If the predetermined time elapses, and the temperature remains below the threshold, thermal control circuit15may boost the performance of a corresponding functional unit by, e.g., increasing its clock frequency. On the other hand, if the temperature does not remain below the threshold for the duration of the predetermined time, thermal control unit15may maintain the corresponding functional unit at a reduced performance level. It is noted that the predetermined times required for increasing the performance (when a temperature falls below a threshold) and reducing the performance (when a temperature is above the threshold) may be different from one another. Furthermore, these predetermined times may be programmable.

As previously noted, when its corresponding instructions are executed on processor core12, SWTCM19may access temperature comparison results at intervals that are less frequent than the hardware-based thermal control mechanism. Moreover, SWTCM19may take different actions responsive to temperature readings exceeding a threshold. In this particular embodiment, responsive to a temperature reading from a particular temperature sensor11exceeding a maximum temperature threshold, processor core12may execute instructions for SWTCM19to shut down at least the corresponding functional unit. Typically, since the hardware-based thermal control mechanism updates more frequently, it may often times be able to maintain temperatures within prescribed limits. A determination by SWTCM19that a temperature exceeds a maximum threshold may indicate that the hardware-based thermal control mechanism has been unsuccessful in maintaining the temperature within prescribed limits, and thus a shutdown may be performed to prevent potential damage to circuitry of IC10. The extent of the shutdown may vary based on the particular circumstances. For example, if a thermal sensor associated with only one functional unit is reporting a temperature greater than the maximum threshold, then only that functional unit may be shutdown. In another example, if thermal sensors associated with a number of functional units are reporting temperatures exceeding a maximum threshold, the entirety of IC10may be shut down. It is also noted that if processor core12is to be shut down in the embodiment shown, processor core14may assume the role of executing instructions for SWTCM19.

In addition to a maximum temperature threshold, trip point circuit may compare received temperature readings to other threshold values. By implementing additional threshold values that are below the maximum value, the thermal output (and thus the temperature) of IC10and its respective functional units may be maintained within limits while potentially preventing shutdowns by the SWTCM19.

Turning now toFIG. 2, a block diagram of one embodiment of a hardware-based Thermal control apparatus is shown. More particularly,FIG. 2illustrates details for one embodiment of each of trip point circuit13and thermal control circuit15. In this exemplary embodiment, the hardware-based thermal control apparatus is configured to monitor two temperature sensors11based on two different thresholds, for two different functional units (in this case a processor core and a graphics unit). However, embodiments are possible and contemplated (including the embodiment illustrated in FIG.1)in which temperatures reported by more than two temperature sensors11are monitored for more than two functional units. Additionally, while comparisons are made against two different thresholds in this example, comparisons against more than two thresholds are also possible and contemplated for various embodiments. Embodiments configured to monitor only a single temperature sensor11, against only a single temperature threshold, and/or for controlling only a single functional unit are also possible and contemplated.

In the embodiment shown, trip point circuit13includes four separate comparators21A-21D. Each of the comparators is coupled to receive temperature readings from one of the temperature sensors11A or11B. Trip point circuit13also includes threshold registers22and23, which are configured to store first and second temperature threshold values, respectively. In the embodiment shown, the temperature threshold values are programmable. In lieu of registers, other storage devices that may store temperature thresholds may be implemented in other embodiments.

Comparators21A and21C are coupled to threshold register22in the embodiment shown, while comparators21B and21D are coupled to threshold register23. Comparators21A and21B are coupled to receive a temperature readings from temperatures sensor11A, while comparators21C and21D are coupled to receive temperature readings from temperature sensor11B. Comparators21A and21C in the embodiment shown are configure to compare temperature readings to the temperature threshold value stored in threshold register22. Similarly, comparators21B and21D in the embodiment shown are configure to compare temperature readings to the temperature threshold value stored in threshold register23.

OR gate27A in the embodiment shown is coupled to receive comparison results from comparators21B and21D. If a comparison result from either of comparators21B or21D indicates that a correspondingly received temperature reading is above the temperature threshold stored in threshold register23, OR gate27A may output a logic 1. Otherwise, if neither of comparators21B or21D indicates that respectively received temperature readings exceed the temperature threshold stored in threshold register23, OR gate27A may output a logic 0. OR gate27B in the embodiment shown is coupled to receive comparison results from comparators21A and21C. If either of comparators21A or21C indicate that a received temperature reading exceeds the temperature threshold stored in threshold register22, OR gate27B may output a logic 1. If neither of comparators21A or21C indicate that a received temperature reading exceeds the temperature threshold stored in threshold register22, then OR gate27B may output a logic 0.

Counter/selector24A in the embodiment shown is coupled to the output of OR gate27A. Similarly, counter/selector24B is coupled to the output of OR gate27B. Each of the counter/selectors in the embodiment shown may initiate a count responsive to a transition of the output of its respectively coupled OR gate. Additionally, each counter/selector may also generate selection codes used to set a performance level for a given functional unit. Although not explicitly shown inFIG. 2, each counter/selector may also be coupled to receive information from each of comparisons21A-21D in order to determine which of the temperature sensors11A and/or11B are reporting temperatures that are exceeding one of the temperature threshold values. This may in turn allow thermal control circuit15to control the respective performance levels of the correspondingly coupled functional units independently from one another.

In the embodiment shown, counter/selector unit24A is configured to operate based on comparisons of received temperature readings to the temperature threshold stored in threshold register23. Responsive to a change of state of the output of OR gate27A (e.g., due to one or both comparators indicating a temperature reading exceeding the threshold stored in threshold register23), counter/selector24A may initiate a count. The count may continue until either a predefined count value is reached or until the output of OR gate27A changes states again, whichever occurs first. The predefined count value may correspond to a predetermined time. Thus, if the predefined count is reached, counter/selector24A may change an output code in order to cause a change to a performance level of one or more functional units. If the predefined count is not reached before the output of OR gate27A changes state again, then counter/selector24A may maintain its current output code(s), thereby enabling the functional units of IC10to maintain their present performance levels. Counter/selector24B may operate in a similar manner with respect to OR gate27B. Changing performance levels may include reducing a performance level (e.g., by reducing the frequency of a respectively received clock signal) or increasing a performance level (e.g., by increasing the frequency of a respectively received clock signal). Performance level reductions may occur responsive to determining that a temperature reading is exceeding one of the threshold values. Performance level increases may occur responsive to determining that a temperature reading has fallen below a previously exceeded temperature threshold value.

The output codes provided by counter/selectors24A and24B may be received at select inputs by multiplexers31A and31B. In one embodiment, multiplexers31A and31B may be independently controlled. In other embodiments, multiplexers31A and31B may operate in concert with one another. Each of multiplexers31A and31B is coupled to receive divisor values as inputs. The divisor value selected by multiplexer31A may be received by clock divider32A, while the divisor selected by multiplexer31B may be received by clock divider32B. Each of multiplexers31A and31B in the embodiment shown is coupled to receive three divisor inputs: full frequency (i.e. divide by 1), divisor 1, and divisor 2. The latter two divisor may cause a receiving one of dividers32A and32B to divide its respectively received input clock signal to produce an output clock signal having a lower frequency. For example, if divisor 1=2, then when received by divider32A, the Clk1output signal will have a frequency that is one half that of the input clock signal, CPU Clk1.

Thus, thermal control circuit15in this particular example may control the performance level of a processor core and a graphics unit by controlling the frequencies of clock signals provided thereto. Switching from the full frequency to divisor 1 may reduce the frequency of a divided one of the clock signals by a first amount. Switching to divisor 2 may reduce the frequency of the divided clock signal by a second amount. By changing the divisors received by dividers32A and32B, the clock frequencies and corresponding performance levels of the functional units of IC10may be controlled in accordance with received temperature readings. Although performance levels are controlled via clock frequencies in the embodiment shown, it is noted that embodiments that control performance levels using different methods are possible and contemplated. For example, supply voltages, workloads, bandwidths, and other parameters may be altered to control performance in various embodiments. Furthermore, embodiments in which multiple parameters are adjustable to control performance in accordance with received temperature readings are possible and contemplated.

FIGS. 3A and 3Bare timing diagram illustrating hysteresis in the operation of one embodiment of a hardware-based thermal control apparatus. It is noted that these examples are given for only a single threshold and two performance levels, although as noted above, embodiments are possible and contemplated for multiple thresholds with multiple performance levels.

FIG. 3Aillustrates the hysteresis in changing performance levels responsive to temperature readings crossing a temperature threshold. The example shown inFIG. 3Abegins with a received temperature being below a threshold value. At (A), it is determined that the temperature level has exceeded the threshold. For a time T1 thereafter, performance is maintained at its current level. When T1 has elapsed (e.g., as indicated by a counter/selector such as that discussed above in reference toFIG. 2), the temperature remains above the threshold, and the performance of a functional unit is dropped from its normal level to a reduced level.

At (B), the temperature has again fallen below the threshold level. For a time T2 thereafter, the performance level of the functional unit is held at a reduced level. When T2 has elapsed, the temperature remains below the threshold, and thus the performance level of the functional unit is restored to its normal level. It is noted that in this particular embodiment, times T1 and T2 are different. However, embodiments where these values are the same are also possible. Furthermore, these values may be programmable in some embodiments.

InFIG. 3B, the temperature again begins at a level that is below the threshold. At (C), the temperature is determined to be above the threshold. A counter may then begin counting to toll the time. However, in this case, the temperature falls back below the threshold before time T1 has elapsed. Since the threshold is no longer exceeded after T1 has elapsed, the performance level is thus maintained.

By using hysteresis in the hardware-based thermal control mechanism, a balance between thermal control and performance may be achieved. More particularly, adding hysteresis to the operation of the hardware-based thermal control mechanism may be useful in preventing performance level changes for short-lived temperature changes that exceed or fall below a threshold, while allowing sufficient time to determine if a change of performance level is desirable.

FIG. 4is a flow diagram illustrating the combined operation of one embodiment of a hardware-based thermal control mechanism in conjunction with one embodiment of a software-based thermal control mechanism. Method400in the embodiment shown may be performed using various combinations of hardware and software embodiments discussed above, or may be implemented using other embodiments not explicitly discussed herein. The method described herein is directed toward a single temperature sensor. However, as noted above, the method may be performed concurrently for any number of sensors with both the hardware and software-based thermal control mechanisms.

Method400begins with the monitoring of temperature reading received from a temperature sensor on an IC or within a system (block405). The monitoring may be performed concurrently by both a hardware-based thermal control mechanism and a software-based thermal control mechanism. The hardware-based thermal control mechanism may monitor temperatures at intervals of a first length, while the software-based thermal control mechanism may monitor temperatures at intervals of a second length. The hardware-based thermal control mechanism may monitor temperature readings more frequently than the software-based thermal control mechanism.

During the monitoring of the temperature readings from the temperature sensors, comparisons of the temperature reading to a 1sttemperature threshold may be performed. If the temperature reading does not exceed the 1stthreshold (block435, no), then operation of a corresponding functional unit or other controlled subsystem may be maintained at a normal (e.g., full) performance level. If the temperature reading exceeds the 1sttemperature threshold (block410, yes) but does not exceed a 2ndtemperature threshold (block415, no), then the performance of the functional unit may be set to a 1streduced level (block420). In one embodiment, operating a 1streduced level may include reducing a frequency of a clock signal relative to that of the full frequency during the normal operation mode. Other methods of reducing the performance of a functional unit are also possible and contemplated, including those which change two or more operating parameters.

As noted above, monitoring of temperature readings may be performed by both the hardware and software-based thermal control mechanisms. In this embodiment, the software-based thermal control mechanism may ignore comparisons of temperature readings to the 1stthreshold, focusing instead on comparisons of the temperature readings to the 2ndthreshold. The 2ndthreshold in this embodiment is greater than the 1stthreshold. Thus, if a comparison determines that a temperature reading is greater than the 2ndthreshold (block415, yes), the subsequent actions performed depend on whether the comparison information is utilized by the hardware-based thermal control mechanism or the software-based thermal control mechanism. When the hardware-based thermal control mechanism determines that a temperature reading exceeds the 2ndthreshold (block425, HW), the performance of the functional unit may be set to a 2ndreduced level.

If the software-based thermal control mechanism determines that the temperature reading exceeds the 2ndthreshold (block425, SW), then at least the functional unit (if not the IC/system itself) may be shut down (block440). Since the hardware-based thermal control mechanism monitors temperature readings relative to the temperature thresholds more frequently than the software-based thermal control mechanism, a determination of a reading exceeding the 2ndthreshold by the latter may indicate that the hardware mechanism is unable to bring the temperature of the functional unit (or IC/system as a whole) under control. Accordingly, the shutdown may be performed to prevent the possibility of damage to the system. Furthermore, since the hardware-based mechanism monitors temperature readings relative to the temperature thresholds more frequently than the software-based thermal control mechanism, the likelihood that a temperature reading exceeding the 2ndthreshold is reduced, as is the likelihood that such a result will be detected by the software-based mechanism.

When operating at one of the reduced performance levels, the hardware based mechanism may continue monitoring temperature readings relative to the thresholds per block405. When operating at the 2ndreduced performance level, temperature readings detected below the 2ndthreshold may eventually result in the hardware-based mechanism increasing the performance level back to the 1streduced performance level. If subsequent temperature readings indicate that the temperature has fallen below the 1stthreshold, the hardware-based mechanism may further increase the performance level back to the normal performance level. In both reducing and increasing the performance levels, hysteresis may be employed such that performance levels are not reduced or increased due to brief temperature changes that are not otherwise part of a trend of increasing or decreasing temperature. This in turn may allow for more long-term optimization of the performance level based on the overall trend of temperature changes.

Turning next toFIG. 5, a block diagram of one embodiment of a system150is shown. In the illustrated embodiment, the system150includes at least one instance of an IC5(e.g., that implements processor10ofFIG. 1) coupled to one or more peripherals154and an external memory158. A power supply156is also provided which supplies the supply voltages to the IC10as well as one or more supply voltages to the memory158and/or the peripherals154. In some embodiments, more than one instance of the IC10may be included (and more than one external memory158may be included as well).

The peripherals154may include any desired circuitry, depending on the type of system150. For example, in one embodiment, the system150may be a mobile device (e.g. personal digital assistant (PDA), smart phone, etc.) and the peripherals154may include devices for various types of wireless communication, such as wifi, Bluetooth, cellular, global positioning system, etc. The peripherals154may also include additional storage, including RAM storage, solid-state storage, or disk storage. The peripherals154may include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc. In other embodiments, the system150may be any type of computing system (e.g. desktop personal computer, laptop, workstation, net top etc.).

The external memory158may include any type of memory. For example, the external memory158may be SRAM, dynamic RAM (DRAM) such as synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, LPDDR1, LPDDR2, etc.) SDRAM, RAMBUS DRAM, etc. The external memory158may include one or more memory modules to which the memory devices are mounted, such as single inline memory modules (SIMMs), dual inline memory modules (DIMM5), etc.