ADAPTIVE INTEGRITY SCAN RATES IN A MEMORY SUB-SYSTEM BASED ON BLOCK HEALTH METRICS

A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event and, responsive to the occurrence of the data integrity check trigger event, identifies a memory die of a plurality of memory dies. The processing device further associates each segment of the identified memory die with a respective group of a plurality of groups, each group representing one or more of a plurality of error mechanisms, and determines one or more respective adaptive scan frequencies for the identified memory die based on statistics of the segments associated with each respective group.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to adaptive integrity scan rates in a memory sub-system based on block health metrics.

BACKGROUND

DETAILED DESCRIPTION

A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. For example, NAND memory, such as 3D flash NAND memory, offers storage in the form of compact, high density configurations. A non-volatile memory device is a package of one or more dice, each including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values.

A memory device can be made up of bits arranged in a two-dimensional or a three-dimensional grid. Memory cells are formed onto a silicon wafer in an array of columns (also hereinafter referred to as bitlines) and rows (also hereinafter referred to as wordlines). A wordline can refer to one or more rows of memory cells of a memory device that are used with one or more bitlines to generate the address of each of the memory cells. The intersection of a bitline and wordline constitutes the address of the memory cell. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a wordline group, a wordline, or individual memory cells. One or more blocks can be grouped together to form separate partitions (e.g., planes) of the memory device in order to allow concurrent operations to take place on each plane.

One example of a memory sub-system is a solid-state drive (SSD) that includes one or more non-volatile memory devices and a memory sub-system controller to manage the non-volatile memory devices. A given segment of one of those memory devices (e.g., a block) can be characterized based on the programming state of the memory cells associated with wordlines contained within the segment. When data is written to a memory cell of the segment for storage, the memory cell can deteriorate. Accordingly, each memory cell of the segment can handle a finite number of write operations performed before the memory cell is no longer able to reliably store data. The error rate associated with data stored at the data block can increase due to a number of factors, including read disturb, slow charge loss, the passage of time, change in temperature, etc. Therefore, at certain intervals, the memory sub-system can perform a data integrity check (also referred to herein as a “scan”) to verify that the data stored at a segment does not include any errors. During the data integrity check, one or more reliability statistics are determined for data stored at the block. One example of a reliability statistic is raw bit error rate (RBER). The RBER corresponds to a number of bit errors per unit of time that the data stored at the block experiences. The data integrity check can take the form of a read disturb scan, triggered by a threshold number of read operations having been performed, or a media scan, triggered by the expiration of a threshold period of time.

If the data integrity check indicates that the reliability statistic for a block (or other segment) exceeds a threshold value, indicating a high error rate associated with data stored at the block, then the data stored at the block can be relocated to a new block of the memory sub-system (also referred to herein as “folding”). The folding of the data stored at the block to the other block can include writing the data to the other block to refresh the data stored by the memory sub-system. Many memory sub-systems have a set scan frequency at which the data integrity check is performed for each block or other segment of the memory device. This scan frequency is typically the same for all blocks in the memory device and is fixed for the entire lifetime of the memory sub-system. Other memory sub-systems modulate the scan frequency over time based on workload (i.e., the number of operations performed on the block) and/or environmental conditions (e.g., time, temperature). Memory sub-systems do not currently account for differences in error mechanisms experienced by different blocks when modulating the scan frequency. For example, by virtue of differing access patterns, certain blocks may be more susceptible to read disturb errors, and thus should have a read disturb scan performed more frequently, while other blocks may be more susceptible to latent read disturb or data retention errors, and thus should have a media scan performed more frequently. Since conventional techniques do not consider the susceptibility to different error mechanisms, the corresponding scan frequencies are often sub-optimal. For example, the data integrity checks may be performed too often (i.e., overscanning) for some blocks and not often enough (i.e., underscanning) for other blocks. Performing such data integrity checks too frequently (i.e., more often than necessary) can hurt system performance, as well as increase the power consumption of the memory sub-system. System bandwidth and other resources are also tied up for extended periods of time, preventing the use of those resources for other functionality. Performing such data integrity checks too infrequently can lead to potential permanent data loss and decreased quality of service and memory sub-system performance.

Aspects of the present disclosure address the above and other deficiencies by utilizing adaptive integrity scan rates in a memory sub-system based on block health metrics. In one embodiment, the memory sub-system controller can adaptively adjust the scan frequency at which a data integrity check is performed for different memory devices (e.g., memory dies) in the memory sub-system. For example, in response to a triggering event, the memory sub-system controller can classify at least a sub-set of the blocks (or other segments) of a memory device into respective groups representing different error mechanisms based on how those blocks have been used over time. In one embodiment, the groups represent blocks that are specifically susceptible to the read disturb, latent read disturb, and data retention error mechanisms. In other embodiments, some other number of groups representing different error mechanisms can be used. Once the blocks are assigned to respective groups, the memory sub-system controller can determine associated statistics (e.g., error counts or error rates) for the blocks in each group. Using the determined statistics for representative blocks from each group (e.g., the best and/or worst performing blocks), the memory sub-system controller can determine a corresponding scan frequency. For example, using the statistics from the blocks in the read disturb group, the memory sub-system controller can determine an optimal read count threshold at which to trigger a read disturb scan on the memory device. Similarly, using the statistics from the blocks in the latent read disturb and/or data retention groups, the memory sub-system controller can determine an optimal time threshold at which to trigger a media scan on the memory device. The memory sub-system controller than can thus perform a subsequent data integrity check for that memory die according to the adaptively determined scan frequency value(s). The same process can be performed separately for each memory die, or group of memory dies, in the memory sub-system.

Advantages of the approach described herein includes, but is not limited to, improved performance in the memory sub-system. For example, the data integrity checks help to avoid data corruption and the need for error correction operations, but adaptively determining the scan frequency ensures that overscanning and underscanning are not performed, thereby saving system resources. In addition, by determining a separate scan frequency for each memory die, the memory sub-system controller can account for die-to-die variations and improve reliability over the entire lifetime of the memory sub-system.

FIG.1illustrates an example computing system100that includes a memory sub-system110in accordance with some embodiments of the present disclosure. The memory sub-system110can include media, such as one or more volatile memory devices (e.g., memory device140), one or more non-volatile memory devices (e.g., one or more memory device(s)130), or a combination of such.

In some embodiments, the memory device(s)130include local media controllers135that operate in conjunction with memory sub-system controller115to execute operations on one or more memory cells of the memory device(s)130. An external controller (e.g., memory sub-system controller115) can externally manage the memory device130(e.g., perform media management operations on the memory device(s)130). In some embodiments, a memory device130is a managed memory device, which is a raw memory device (e.g., memory array104) having control logic (e.g., local controller135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. Memory device(s)130, for example, can each represent a single die having some control logic (e.g., local media controller135) embodied thereon. In some embodiments, one or more components of memory sub-system110can be omitted.

In one embodiment, the memory sub-system110includes an adaptive scan component113that can determine adaptive scan frequencies for respective memory dies (e.g., memory device130) in memory sub-system110based on statistics of groups of segments that experience different types of error mechanisms. In one embodiment, adaptive scan component113detects an occurrence of a data integrity check trigger event in the memory sub-system110, and in response, identifies a memory die of a plurality of memory dies in the memory sub-system110. The data integrity check trigger event can include at least one of an expiration of a threshold period of time since a previous data integrity check or an occurrence of a threshold number of program-erase cycles in the memory sub-system110since the previous data integrity check. Adaptive scan component113can further associate each segment of the identified memory die with a respective group of a plurality of groups. Each group can represent one or more of a plurality of error mechanisms, such as read disturb, latent read disturb, data retention, etc. Adaptive scan component113can further determine an adaptive scan frequency for the identified memory die based on statistics of the segments associated with each respective group. When the adaptive scan frequency has been reached, adaptive scan component113can perform a data integrity check to determine a reliability statistic (e.g., RBER) for a segment (e.g., a block) of the identified memory die, and determine whether the reliability statistic satisfies a folding criterion (e.g., is greater than a threshold value). Responsive to determining that the reliability statistic satisfies the folding criterion, adaptive scan component113can perform a folding operation on the segment of the identified memory die. Further details with regards to the operations of adaptive scan component113are described below.

FIG.2Ais a flow diagram of an example method of determining adaptive scan frequencies for memory dies in a memory sub-system in accordance with some embodiments of the present disclosure. The method200can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method200is performed by adaptive scan component113ofFIG.1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation205, the processing logic (e.g., adaptive scan component113) detects an occurrence of a data integrity check trigger event. Depending on the embodiment, the data integrity check trigger event comprises at least one of an expiration of a threshold period of time since a previous data integrity check or an occurrence of a threshold number of program-erase cycles in the memory sub-system since the previous data integrity check.

At operation210, responsive to the occurrence of the data integrity check trigger event, the processing logic identifies a memory die of a plurality of memory dies. In one embodiment, memory sub-system110includes a plurality of memory dies. For example, memory device130can be representative of one memory die. A given memory die can be identified using any number of different approaches. For example, adaptive scan component113can identify the first die in a sequence (e.g., arranged by die number), or can identify the memory die randomly or pseudo-randomly.

At operation215, the processing logic associates each segment of the identified memory die with a respective group of a plurality of groups, each group representing one or more of a plurality of error mechanisms. In one embodiment, there can be groups of segments (e.g., blocks) representing the read disturb mechanism, the latent read disturb mechanism, the data retention mechanism, and additional and/or different error mechanisms. In one embodiment, adaptive scan component113can associate each segment with a respective group based on a workload experienced by each segment. That workload can include a read count or read rate (i.e., number of read operations within a given period of time) of the segment and a time since the segment was programmed (i.e., a block age). For example, adaptive scan component113can determine the read count/read rate and time since program for each segment, compare those values to established thresholds, and associate each segment with a respective group accordingly.

FIG.2Bis a diagram illustrating the grouping of segments of a memory die according to error mechanisms in accordance with some embodiments of the present disclosure. The graph250illustrates a number of groups defined according to read count/read rate and time since program. For example, segments can be plotted according to the time since program on the x-axis of graph250with the time values divided into BIN0-BIN7. The range of time represented by each bin can vary depending on the implementation and may or may not be consistent for all bins. In general, BIN0 represents the lowest time since program, while BIN7 represents the highest time since program. In addition, the segments can be plotted according to the read count and/or read rate on the y-axis of graph250with the read values divided into bins logarithmically. In one embodiment, a data retention group252can include any segments with a relatively low read count (e.g., 1-10) and any time since program. Data retention errors occur in a memory device to the passage of time and/or changes in environmental conditions (e.g., temperature) which cause the level of charge stored at each memory cell to change, potentially resulting in read errors. Thus, data retention is likely to occur even if the read count is relatively low. A latent read disturb group254can include any segments with a higher read count (e.g., 100-1000) and any time since program. Latent read disturb is caused by a lingering voltage on a memory cell left after a read operation. If read commands are issued with delay in between a first read command and a second read command, the latent read disturb stress component per read is increased, thus a comparatively larger amount of latent read disturb accumulates. Thus, latent read disturb is likely to occur when the read count is slightly higher, but not excessively high. A read disturb group256can include any segments with an even higher read count (e.g., 10,000-100,000+) and a relatively low time since program (e.g., BIN0-BIN2). Read disturb is the result of continually reading from one memory cell without intervening erase operations, causing other nearby memory cells to change over time (e.g., become programmed). If too many read operations are performed on a memory cell, data stored at adjacent memory cells of the segment can become corrupted or incorrectly stored at the memory cell. Thus, read disturb is likely to occur when the read count is high, but the time since program is relatively low. A backup retention group258can include any segments with the higher read count and a relatively high time since program (e.g., BIN3-BIN7). In other embodiments, the delineations between groups in either read count or time since program can be variable or otherwise configured depending on the specific implementation.

Referring again toFIG.2A, at operation220, the processing logic determines one or more respective adaptive scan frequencies for the identified memory die based on statistics of the segments associated with each respective group. In one embodiment, adaptive scan component113can use reliability statistics (e.g., read error rate) of certain representative segments in a given group or groups to determine a corresponding adaptive scan frequency for the identified memory die. For example, statistics of segments associated with the read disturb group256can be used to determine a scan frequency for a read disturb scan performed on the memory die. Similarly, statistics of segments associated with the data retention group252can be used to determine a scan frequency for a media scan performed on the memory die. In one embodiment, statistics of segments associated with multiple different groups can be used to determine a scan frequency. For example, statistics of segments associated with data retention group252and latent read disturb group254can be used to determine the scan frequency for the media scan performed on the memory die. Additional details pertaining to how adaptive scan frequencies are determined are described below with respect toFIG.3.

At operation225, the processing logic determines whether there are additional memory dies among the plurality of memory dies. If so, the processing logic returns to operation210to identify a subsequent memory die and repeats operations215and220for each remaining die in order to determine respective adaptive scan frequencies for the each of the plurality of memory dies. If not, the processing logic returns to operation205and waits for a subsequent occurrence of a data integrity check trigger event.

FIG.3is a flow diagram of an example method of determining adaptive scan frequencies on a memory die in accordance with some embodiments of the present disclosure. The method300can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method300is performed by adaptive scan component113ofFIG.1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation305, the processing logic performs a read operation on each segment of the memory die associated with a given group to determine respective associated reliability statistics. In one embodiment, adaptive scan component113applies a read voltage to one or more wordlines of the identified memory die to read a raw code word (i.e., a series of a fixed number of bits) from the memory die. Adaptive scan component113can apply the code word to an error correcting code (ECC) decoder to generate a decoded code word and compare the decoded code word to the raw code word. Adaptive scan component113can count a number of flipped bits between the decoded code word and the raw code word, with a ratio of the number of flipped bits to the total number of bits in the code word representing the reliability statistic (e.g., the raw bit error rate (RBER)). Scan determining component113can repeat this process for additional code words until the entire memory die has been scanned.

At operation310, the processing logic can identify representative segments in each group of the plurality of groups. In one embodiment, adaptive scan component113can identify the best and/or worst performing segments as the representative segments. For example, the best performing segments can be one or more segments having the lowest RBER within each group, while the worst performing segments can be one or more segments having the highest RBER within each group.

At operation320, the processing logic can determine a respective adaptive scan frequency based on the respective reliability statistics associated with the one or more representative segments (e.g., the segments with the highest RBER). In one embodiment, adaptive scan component113reads an entry of a plurality of entries in a data structure, wherein the entry is associated with the respective reliability statistics and comprises an indication of the adaptive scan frequency. For example, adaptive scan component113could maintain a lookup table (LUT) or other data structure in local memory119of memory sub-system controller115, or elsewhere in memory sub-system110, that includes the plurality of entries. Each entry can be associated with a specific reliability statistic or a range of reliability statistics, and can include corresponding respective adaptive scan frequencies. The adaptive scan frequencies can be defined using a period of time since a previous scan, a number of PECs since a previous scan, or some other metric. In one embodiment, the respective adaptive scan frequencies for different reliability statistics are determined via experimentation performed before or during manufacture of the memory sub-system110. In one embodiment, there can be different data structures, or the values in the entries of one data structure can vary, to account for different points in the lifetime of the memory sub-system110. For example, there could be one data structure having certain adaptive scan frequencies for the memory dies when the total program-erase cycle (PEC) count in the memory sub-system110is below a certain threshold, and another data structure having different adaptive scan frequencies for the memory dies when the total program-erase cycle (PEC) count in the memory sub-system110is above the threshold.

At operation405, the processing logic (e.g., adaptive scan component113) determines whether the adaptive scan frequency for the identified memory die has been reached. As determined in operation220ofFIG.2A, each memory die can have a separate respective adaptive scan frequency for either or both of a read disturb scan or a media scan. For example, if the adaptive scan frequency is defined as a certain period of time since a previous data integrity check (i.e., a media scan), adaptive scan component113can maintain a timer set to an initial value according to the adaptive scan frequency. When the timer expires, adaptive scan component113can determine that the adaptive scan frequency has been reached. If the adaptive scan frequency is defined as a number of read operations since a previous data integrity check (i.e., a read disturb scan), adaptive scan component113can maintain a counter that is incremented each time a read operation occurs on the memory die. When the counter reaches a configurable threshold value, adaptive scan component113can determine that the adaptive scan frequency has been reached.

In response to determining that the adaptive scan frequency for the identified memory die has been reached, at operation410, the processing logic performs a data integrity check to determine a reliability statistic for a segment of the identified memory die. In one embodiment, adaptive scan component113applies the default read voltage level to one or more wordlines of the identified memory die to read a raw code word (i.e., a series of a fixed number of bits) from the segment (e.g., a block) of the memory die. Adaptive scan component113can apply the code word to an error correcting code (ECC) decoder to generate a decoded code word and compare the decoded code word to the raw code word. Adaptive scan component113can count a number of flipped bits between the decoded code word and the raw code word, with a ratio of the number of flipped bits to the total number of bits in the code word representing the reliability statistic (e.g., the raw bit error rate (RBER)). Scan determining component113can repeat this process for additional code words until the entire memory die has been scanned.

At operation415, the process logic determines whether the reliability statistic satisfies a folding criterion (e.g., meets or exceeds a folding threshold). In one embodiment, adaptive scan component113compares the reliability statistic to the folding threshold. Responsive to determining that the reliability statistic satisfies the folding criterion, at operation420, the processing logic performs a folding operation on the segment of the identified memory die. In one embodiment, adaptive scan component113relocates data stored at that segment to another segment on the same or a different memory die. In one embodiment, adaptive scan component113reads data stored in the corresponding block (i.e., the block for which the error rate meets or exceeds the folding threshold) writes that data to another block. Once the data has been written to the other block, the data stored in the initial block is erased and the initial block is available to be programmed with new data. Depending on the embodiment, the data is relocated to another block of the same plane of the same memory die, to another plane on the same memory die, or to a different memory die of the memory sub-system110.