Method for fabricating a semiconductor device having stress/strain and protrusion

A semiconductor device includes a silicon substrate having a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate on the side of the gate electrode, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material, a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall.

FIELD

An aspect of the embodiments discussed herein is directed to a method of manufacturing a semiconductor device including a film for providing increased channel stress of a field-effect transistor.

BACKGROUND

A technique has been known in which the crystals of the channel region of a semiconductor device including a field-effect transistor are distorted to increase the carrier mobility. For example, a method has been proposed for forming a stress film covering the field-effect transistor so that a predetermined stress may be produced in the channel region.

The field-effect transistor has a structure having side walls that electrically separate the gate electrode from the source and drain regions when the gate electrode, the source region and the drain region are formed. The side walls are formed on the side surfaces of the gate electrode and at both ends of the channel region.

A side wall having a small width may increase the stress produced in the channel region by the stress film, and may increase the carrier mobility accordingly. However, the side wall having a small width may not maintain sufficient insulation between the gate electrode and the source region or between the gate electrode and the drain region.

For example, Japanese Laid-open Patent Publication No. 2005-057301 discusses that grooves are formed so as to extend to the portions under the side walls from the surfaces of the source and drain regions formed at both sides of the side walls, and are filled with a stress film. By forming grooves near the channel region, the distance between the stress film and the channel region may be reduced independent of the width of the side wall.

SUMMARY

According to an aspect of an embodiment, a semiconductor device includes a silicon substrate including a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material, a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall.

DESCRIPTION OF EMBODIMENTS

As described previously, the side wall in the structure discussed in Patent Document 1 is however made of silicon oxide (SiO2). Silicon oxide (SiO2) has a lower Young's modulus than silicon (Si) forming the substrate of the field-effect transistor. Consequently, stress produced by the stress film is absorbed by the deflection of the side wall. The stress produced by the stress film may not be efficiently transmitted to the channel region.

A first embodiment and a second embodiment will now be described. However, the present technique is not limited to the embodiments.

FIGS. 1 to 6are detailed representations of the structure of an n-type MIS transistor10according to a first embodiment and a method of manufacturing the n-type MIS transistor10. In the MIS transistor and the method of manufacturing the MIS transistor according the first embodiment, a second side wall14bhaving a higher Young's modulus than the p-type silicon (Si) substrate11is formed at both ends of the channel region. By forming the second side wall14bat both ends of the channel region, the uniaxial stress in the channel region may be increased.

FIG. 1illustrates the structure of the n-type MIS transistor10of the first embodiment.FIG. 1Ais a plan view of the n-type MIS transistor10.FIG. 1Bis a sectional view taken along line X-X′ inFIG. 1A.

InFIG. 1A, reference numeral11adenotes a protrusion;13denotes a gate electrode;14adenotes a first side wall;14bdenotes a second side wall;18denotes a pocket region;19denotes an extension region;21adenotes a deep source region;21bdenotes a deep drain region;40denotes an active region; and50denotes an element isolation region. The n-type MIS transistor10is an example of the semiconductor device.

As illustrated inFIG. 1A, the element isolation region50is formed around the n-type MIS transistor10. The active region40is a rectangular region defined by the element isolation region50. The gate electrode13extends across the center of the active region40. The first side wall14aand the second side wall14bare formed around the gate electrode13. The pocket regions18and the extension regions19are formed to predetermined widths along the gate electrode13in the active region40. The gate electrode13is formed over the protrusion11a. The deep source region21aand the deep drain region21bare formed in the entire active region40except the gate electrode13, pocket regions18and extension regions19.

InFIG. 1B, reference numeral11denotes a p-type silicon (Si) substrate;11adenotes the protrusion;12denotes a gate insulating layer;13denotes the gate electrode;14adenotes the first side wall;14bdenotes the second side wall;15denotes a silicide layer;16adenotes a stress film;18denotes the pocket region;19denotes the extension region;21adenotes the deep source region; and21bdenotes the deep drain region. InFIG. 1B, the same parts as those inFIG. 1Aare designated by the same reference numerals.

The protrusion11ais formed on the p-type silicon (Si) substrate11. The protrusion11ahas an upper surface and a side surface. Preferably, the side surface of the protrusion11ais inclined from the direction perpendicular to the major surface of the p-type silicon (Si) substrate11. Preferably, the inclination of the side surface of the protrusion11ais 30 to 60 degrees. The protrusion11ahas a height of about 10 nm to 20 nm.

The gate insulating layer12is formed on the protrusion11aof the p-type silicon (Si) substrate11. The gate insulating layer12has a thickness of, for example, about 1 nm to 2 nm.

The gate electrode13is formed to a height of, for example, about 100 nm on the gate insulating layer12. Polysilicon (Si) may be used for the gate electrode13.

The source region25aand the drain region25bare provided in the protrusion11aof the p-type silicon (Si) substrate11. The extension regions19are part of the source region25aand the drain region25b. Preferably, the extension regions19are formed to a width of, for example, 40 nm to 60 nm respectively from one edge and the opposite edge of the p-type silicon (Si) substrate11in the region where the gate insulating layer12is disposed, and to a depth of at most 20 nm to 60 nm from the surface of the p-type silicon (Si) substrate. The width of the extension regions19depends on the widths of the below-described first side wall14aand second side wall14bon the p-type silicon (Si) substrate11. The extension region19prevents the depletion layer from spreading in the channel region, and prevents the below-described short channel effect from occurring between the deep source region21aand the deep drain region21b. The channel region of the n-type MIS transistor10refers to a region formed in the p-type silicon (Si) substrate11under the gate insulating layer12, that is, in the protrusion11a, during operation of the n-type MIS transistor10.

The pocket regions18are formed so as to come in contact respectively with one edge and the opposite edge of the p-type silicon (Si) substrate11in the region where the gate insulating layer12is disposed and so as to cover the peripheries of the extension regions19. The pocket regions18and the extensions region19are partially provided in the protrusion11aof the p-type silicon (Si) substrate11. The pocket region18is intended to suppress the punch through effect between the source region25aand the drain region25b. Preferably, the maximum depth of the pocket region18is, for example, 30 nm to 80 nm.

The deep source region21aand the deep drain region21bare formed with a predetermined interval so as to come in contact respectively with the ends of the p-type silicon (Si) substrate11in the regions under the first side walls14a. Preferably, the maximum depth of the deep source region21aand the deep drain region21bis, for example, 50 nm to 200 nm.

The silicide layer15is formed on the surfaces of the gate electrode13, the deep source region21aand the deep drain region21b. Preferably, the silicide layer15is formed to a thickness of, for example, 20 nm to 70 nm. It is not however necessary to provide the silicide layer15in the present embodiment.

The first side walls14aare formed on the side surfaces of the gate electrode13and the side surface of the protrusion11a, and on the p-type silicon (Si) substrate11. The first side wall14amay be made of silicon oxide (SiO2), which is an insulating material having a lower Young's modulus than the p-type silicon (Si) substrate11. Preferably, the silicon oxide (SiO2) has an insulating strength of 10×107(V/cm) or more. The first side walls14amay be provided only on the side surface of the protrusion11a.

The second side walls14bare formed on the surfaces of the first side walls14a. Preferably, the bottoms of the second side walls14bare located lower than the upper surface of the protrusion11a. The second side wall14bis made of silicon nitride (SiN) having a higher Young's modulus than the p-type silicon (Si) substrate11.

Preferably, the thickness of the second side wall14bis about four times as large as the thickness of the first side wall14a. In the first embodiment, the Young's modulus of silicon oxide (SiO2) is 65 [GPa] while the Young's modulus of silicon nitride (SiN) is 200 to 300 [GPa]. Hence, the Young's modulus of silicon oxide (SiO2) is about ¼ of the Young's modulus of silicon nitride (SiN). If the thickness of the silicon oxide (SiO2) is reduced to ¼ of the thickness of the silicon nitride (SiN), the stress produced by the stress film16adescribed later is absorbed by the deflection of the first side walls14a. Consequently, the problem occurs that the stress produced by the stress film16ais not efficiently transmitted to the channel region. The Young's modulus of silicon nitride (SiN) is varied depending on the forming conditions.

The stress film16ais formed over the entire surface of the p-type silicon (Si) substrate11so as to cover the surfaces of the gate electrode13, the first side walls14a, the second side walls14b, the silicide layer15, the deep source region21aand the deep drain region21b. The stress film16ahas a thickness of, for example, about 70 nm to 90 nm.

FIGS. 2 to 4illustrate a method for manufacturing the n-type MIS transistor10according to the first embodiment.

FIG. 2Aillustrates the process operation of forming the gate insulating layer12and the gate electrode13.

The gate insulating layer12is formed on the p-type silicon (Si) substrate11. For the gate insulating layer12, a silicon oxynitride (SiON) layer is formed by CVD, or combination of thermal oxidation and thermal nitridation. The p-type silicon (Si) substrate11contains, for example, 1.0×1016cm−3of a p-type conductive impurity.

The gate electrode13is formed on the gate insulating layer12. The gate electrode13is formed by depositing a polycrystalline silicon (Si) layer (not illustrated) to a thickness of about 100 nm on the gate insulating layer12by CVD or the like and patterning the polycrystalline silicon (Si) layer into an electrode shape by photolithography and anisotropic etching.

FIG. 2Billustrates the process operation of forming the pocket regions18, the source region25aand the drain region25b. A first ion implantation is performed on the source region25aand the drain region25b.

A pair of pocket regions18is formed by oblique ion implantation of a p-type conductive impurity to the pocket regions18of the p-type silicon (Si) substrate11, using the gate electrode13as a mask. Preferably, the oblique ion implantation is performed at an angle of 45° with the normal to the substrate, as indicated by arrows18a. Boron (B) may be used as the p-type conductive impurity. The oblique ion implantation is performed under the conditions of an accelerated energy of 10 keV and a dose of 1×1013/cm2.

The extension regions19are part of the source region25aand the drain region25b. A pair of extension regions19is formed by the first ion implantation to the extension regions19of the p-type silicon (Si) substrate11, using the gate electrode13as a mask. For example, arsenic (As) may be used as an n-type conductive impurity. The ion implantation is performed, for example, under the conditions of an accelerated energy of 5 keV and a dose of 1×1014/cm2.

FIG. 2Cillustrates the process operation of forming the protrusion11a.

The protrusion11ais formed with part of the gate insulating layer12and gate electrode13left on the p-type silicon (Si) substrate11. The protrusion11ais formed by anisotropically etching the silicon oxynitride (SiON) layer on the p-type silicon (Si) substrate11using the gate electrode13as a mask, and subsequently anisotropically etching the p-type silicon (Si) substrate11using the gate electrode13as a mask again. The silicon oxynitride (SiON) layer may be removed by etching in the operation illustrated inFIG. 2A. The anisotropic etching forming the protrusion11ais performed under conditions where the side surface of the protrusion11amay be tapered. For etching of the silicon oxynitride (SiON) layer and the p-type silicon (Si) substrate11, for example, CHF3/Ar/O2gas containing a fluorocarbon gas CHF3or CF4/Ar/O2gas containing a fluorocarbon gas CF4is used.

Preferably, the inclination of the side surface of the protrusion11ais 30 to 60 degrees. If the inclination of the protrusion11ais less than 30 degrees, the extension regions19formed in the protrusion11aare reduced. Consequently, the leakage current is increased in the channel region. If the inclination of the side surface of the protrusion11ais larger than 60 degrees, the stress from the stress film16amay not efficiently be transmitted to the protrusion11athrough the second side walls14b. Consequently, it becomes difficult to increase the driving current of the n-type MIS transistor10. The inclination of the side surface of the protrusion11ais adjusted by varying the bias voltage and the concentration of the fluorocarbon gas used for the anisotropic etching.

The extension regions19, which are part of the source region25aand drain region25b, are thus formed in the protrusion11aof the p-type silicon (Si) substrate11. The protrusion11ahas a height of about 10 nm to 20 nm. In this operation, the top of the polycrystalline silicon gate electrode13is also etched to reduce the height.

FIG. 2Dillustrates the process operation of forming a silicon oxide (SiO2) layer14cintended for the first side walls14a. The silicon oxide (SiO2) layer14cis a first insulating layer.

As illustrated inFIG. 2D, the insulating silicon oxide (SiO2) layer14cis formed to a thickness of about 5 nm to 10 nm by, for example, CVD so as to cover the side surface of the protrusion11aand the gate electrode13. Specifically, the silicon oxide (SiO2) layer14cmay be formed by low pressure CVD reacting at a substrate temperature of 600° C. using, for example, tetraethoxysilane (TEOS) and O2as source gases. In this operation, the surface of the silicon oxide (SiO2) layer14copposing the p-type silicon (Si) substrate11becomes lower than the upper surface of the protrusion11a.

FIG. 3Aillustrates the process operation of forming a silicon nitride (SiN) layer14dintended for the second side walls14b. The silicon nitride (SiN) layer14dis a second insulating layer. As illustrated inFIG. 3A, the silicon nitride (SiN) layer14dhaving a higher Young's modulus than the p-type silicon (Si) substrate11is formed to a thickness of 35 nm to 45 nm by, for example, CVD so as to cover the protrusion11a, the gate electrode13and the silicon oxide (SiO2) layer14c. Specifically, the silicon nitride (SiN) layer14dmay be formed by low pressure CVD reacting at a substrate temperature of about 600° C. using dichlorosilane (SiCl2H2) and ammonia (NH3) as source gases.

As an alternative to dichlorosilane (SiCl2H2), silane (SiH4), bis(tert-butylamino silane) (BTBAS) or the like may be used as a silicon (Si) source gas for the silicon nitride (SiN) layer14d.

FIG. 3Billustrates the process operation of forming the first side walls14aand the second side walls14b.

As illustrated inFIG. 3B, the first side walls14aand the second side walls14bare formed by anisotropically etching the silicon nitride (SiN) layer14dand subsequently the silicon oxide (SiO2) layer14cover the entire surface of the p-type silicon (Si) substrate11. For etching the silicon nitride (SiN) layer14d, for example, CHF3/Ar/O2gas containing a fluorocarbon gas CHF3may be used. For etching the silicon oxide (SiO2) layer14c, C4F8/Ar/O2gas containing a fluorocarbon gas C4F8may be used.

The first side walls14aare thus formed of an insulating material on the side surface of the protrusion11aand on the p-type silicon (Si) substrate11. The second side walls14bare formed of a material having a higher Young's modulus than the silicon (Si) substrate on the surfaces of first side walls14a.

In the present embodiment, the first side walls14aand the second side walls14bare formed by depositing the silicon oxide (SiO2) layer14cand the silicon nitride (SiN) layer14din that order, and then anisotropically etching the entire surface. Alternatively, the first side walls14amay first be formed by depositing a silicon oxide (SiO2) layer14cand anisotropically etching the silicon oxide (SiO2) layer14c, and subsequently the second side walls14bmay be formed by depositing a silicon nitride (SiN) layer14dand anisotropically etching the silicon nitride (SiN) layer14d. This manufacturing method allows the first side walls14ato be formed only on the side surfaces of the gate electrode13and the side surface of the protrusion11a.

FIG. 3Cillustrates the process operation of forming the deep source region21aand the deep drain region21b. A second ion implantation is performed on the deep source region21aand the deep drain region21b.

As illustrated inFIG. 3C, the deep source region21aand the deep drain region21bare formed by the second ion implantation of an n-type conductive impurity to the deep source region21aand the deep drain region21bon the p-type silicon (Si) substrate11using the gate electrode13, the first side walls14aand the second side walls14bas a mask. For example, arsenic (As) may be used as an n-type conductive impurity. The ion implantation is performed, for example, under the conditions of an accelerated energy of 30 keV and a dose of 1×1015/cm2.

Then, the ion-implanted impurity may be activated by annealing at 1000° C. for about 10 seconds.

FIG. 3Dillustrates the process operation of forming the silicide layer15.

As illustrated inFIG. 3D, a metal for forming the silicide layer15is deposited on the surfaces of the gate electrode13, the deep source region21aand the deep drain region21b. In the present embodiment, the metal for forming the silicide is, for example, cobalt (Co). The deposition of cobalt (Co) on the surfaces of the gate electrode13, the deep source region21aand the deep drain region21bis performed by sputtering using, for example, a cobalt (Co) target with a DC bias of about 250 W applied. Preferably, cobalt (Co) is deposited to a thickness of, for example, about 3 nm to 8 nm. The primary siliciding reaction of cobalt (Co) at the surfaces of the gate electrode13, the deep source region21aand the deep drain region21bmay be performed by low-temperature annealing, for example, at about 500° C. for 30 seconds in a nitrogen (N2) atmosphere. Then, the unreacted cobalt (Co) layer is removed with, for example, a mixture of ammonium hydrogen peroxide (NH3.H2O2) and persulfuric acid (H2SO5). Subsequently, a secondary siliciding at the surfaces of the gate electrode13and the p-type silicon (Si) substrate11may be performed by high-temperature annealing at, for example, about 700° C. for about 30 seconds in a nitrogen (N2) atmosphere. The silicide layer15is thus formed on the surfaces of the gate electrode13, the deep source region21aand the deep drain region21b. The metal for forming the silicide layer15may be nickel (Ni).

FIG. 4illustrates the process operation of forming the stress film16a.

The stress film16ais formed over the gate electrode13, the first side walls14aand the second side wall14b. Specifically, the stress film16ais formed over the entire surface of the p-type silicon (Si) substrate11so as to cover the surfaces of the gate electrode13, the first side walls14a, the second side walls14b, the silicide layer15, the deep source region21aand the deep drain region21b. Preferably, the stress film16ais made of, for example, silicon nitride (SiN). Preferably, the stress film16ais formed by, for example, plasma CVD. The stress film16ais formed to a thickness of, for example, about 70 nm to 90 nm. For forming the silicon nitride (SiN) layer intended for the stress film16a, a SiN forming gas (for example, NH3and SiH4) is used. Then, hydrogen (H) is removed from the silicon nitride (SiN) layer being the stress film16aby UV curing. Thus, the stress film16amay be formed so that the silicon nitride (SiN) layer shrinks and exhibits the property of applying a tensile stress to the channel region.

The n-type MIS transistor10is thus completed through further operations including the operations of forming an insulating interlayer (not illustrated), forming a contact hole (not illustrated) using the stress film16aas an etching stopper, and forming conductor lines (not illustrated).

The above embodiment has described a MIS transistor using an n-type MIS transistor10. The MIS transistor, however, may be a p-type MIS transistor. In such a case, the conductivity type of the above n-type MIS transistor10is reversed for a p-type MIS transistor.

The present embodiment is not limited to the structure, conditions and the like described in the present embodiment. Various modifications may be made in the embodiment.

FIG. 5is a table illustrating the orientation of the stress and distortion applied to the channel region of an n-type MIS transistor, suitable to increase the driving current of the n-type MIS transistor, and the orientation of the stress and distortion applied to the channel region of a p-type MIS transistor, suitable to increase the driving current of the p-type MIS transistor.

InFIG. 5, the Direction column is denoted by1; the NMOS field, by2; the PMOS field, by3, the mark column, by4; the Tension field, by5; and the Compression field, by6.

The Direction column1is filled with the direction of the stress and distortion produced by a stress. The stress and distortion are produced in the longitudinal direction (X direction: direction connecting the source region and the drain region).

The NMOS column2is filled with the orientation of the stress applying a distortion suitable to increase the driving current of an n-type MIS transistor.

It is illustrated that tension is suitable for the distortion in the longitudinal direction.

The Tension5represents that when a distortion is applied by a tensile force in the longitudinal direction (X direction: direction connecting the source region and the drain region), the driving current is increased.

The PMOS column3is filled with the orientation of the stress applying a distortion suitable to increase the driving current of a p-type MIS transistor.

The orientation of the longitudinal direction is compression6. This means that a distortion produced by compression is suitable to increase the driving current.

In the present embodiment, it is a necessary condition for increasing the driving current of the MIS transistor that the longitudinal direction (X direction: direction connecting the source region and the drain region) coincides with the <110> direction of the silicon (Si) semiconductor substrate.

The band structure of a silicon (Si) crystal is changed by applying a distortion, thereby increasing the effective mobility of conductive carriers in the inversion layer of a MIS transistor. By increasing the effective mobility of the conductive carriers, the driving current of the MIS transistor is increased. In contrast, if the distortion is applied to the band structure in a reverse direction, the effective mobility of the conductive carriers is reduced.

For the orientations of stress applying distortion suitable to increase the driving current of a MIS transistor, illustrated in the NMOS column2and the PMOS column3, a non-patent document: S. E. Thompson et al.,IEEE Trans. Elec. Dev, pp. 1790-1797, November 2004 was consulted.

The mark column4illustrates that the distortion in the longitudinal direction (X direction: direction connecting the source region and the drain region) is represented by Exx.

FIG. 5illustrates that Exx in the orientation of tension5illustrated in the NMOS column2contributes to the carrier mobility in the channel region. Also, it is illustrated that Exx in the orientation of compression illustrated in the PMOS column3contributes to the carrier mobility in the channel region.

FIG. 6is a representation illustrating the improvement of the stress and distortion in the channel region of the n-type MIS transistor10according to the first embodiment.

FIG. 6Aillustrates an n-type MIS transistor10′. Arrows22ain the figure indicate the orientation of the stress σxx and distortion Exx produced in the X direction (direction connecting the source region and the drain region) in the channel region. The orientation in which distortion Exx is produced corresponds to that of distortion Exx illustrated inFIG. 5. The gate electrode13has a width of 40 nm and a height of 100 nm. The first side wall14ahas a width of 10 nm, and the second side wall14bhas a width of 30 nm. The stress film16aover the n-type MIS transistor10′ has a thickness of 80 nm. The stress film16ais a film applying a tensile stress, that is, a silicon nitride (SiN) film having a tensile stress.

FIG. 6Billustrates an n-type MIS transistor10. Arrows22bin the figure indicate the orientation of the stress σxx and distortion Exx produced in the X direction (direction connecting the source region and the drain region) in the channel region. The orientation in which distortion Exx is produced corresponds to that of distortion Exx illustrated inFIG. 5. The difference between the n-type MIS transistor10′ illustrated inFIG. 6Aand the n-type MIS transistor10illustrated inFIG. 6Bis that the n-type MIS transistor10has a protrusion11aof 15 nm in height.

FIG. 6Cillustrates the results of simulations for stress σxx and distortion Exx produced in the vicinity of the channel region in the structures of the n-type MIS transistor10′ and the n-type MIS transistor10. InFIG. 6C, the vertical axis represents the stress σxx in the X direction. The distortion Exx is obtained by dividing the length of elongation by the original length, and is dimensionless. The lateral axis ofFIG. 6Crepresents the position in the range of −10 nm to 10 nm, wherein the interface between the p-type silicon (Si) substrate11and the gate insulating layer12is defined as the origin point, and the lower side from the gate insulating layer12is positive and the height direction of the gate electrode13is negative.

In the simulations for obtaining the above-described stress and distortion, the Young's moduli of the silicon oxide (SiO2) of the first side wall14a, the silicon (Si) of the p-type silicon (Si) substrate11, the silicon nitride (SiN) of the second side wall14bare set so as to be increased in that order. Specifically, the Young's modulus of silicon oxide (SiO2) is set at 65 [GPa]; the Young's modulus of silicon (Si) is set at 130 GPa; and the Young's modulus of silicon nitride (SiN) is set at 200 GPa.

InFIG. 6C, the black rhombic data30asurrounded by a dashed line represents a value of stress σxx in the n-type MIS transistor10′, and the black rhombic data30bsurrounded by a solid line represent values of stress σxx in the n-type MIS transistor10. In this figure, the black rhombic data30asurrounded by the dashed line represents a value of stress σxx along the z axis at the interface between the p-type silicon (Si) substrate11and the gate insulating layer12. The black rhombic data30bsurrounded by the solid line represent values of stresses σxx at positions respectively 1 nm and 6 nm lower than the origin point of the interface between the p-type silicon (Si) substrate11and the gate insulating layer12.

FIG. 6Ccompares the black rhombic data30asurrounded by the dashed line and the black rhombic data30bsurrounded by the solid line. In the black rhombic data30asurrounded by the dashed line, the stress σxx in the n-type MIS transistor10′ at the interfaced between the p-type silicon (Si) substrate11and the gate insulating layer12was 0.28. In the black rhombic data30bsurrounded by the solid line, the stresses σxx in the n-type MIS transistor10were 0.34 and 0.38 respectively.

FIG. 6Dis a graph illustrating distortions, or σxx, in the longitudinal direction (X direction: direction connecting the source region and the drain region) obtained by simulations using the n-type MIS transistor10′ and the n-type MIS transistor10. InFIG. 6D, the black circular data30csurrounded by a dashed line represents the distortion Exx in the n-type MIS transistor10′, and the black circular data30dsurrounded by a solid line represent the distortion Exx in the n-type MIS transistor10. In this figure, the black circular data30csurrounded by the dashed line represents the value of distortion Exx along the z axis at the interface between the p-type silicon (Si) substrate11and the gate insulating layer12. The black circular data30dsurrounded by the solid line represent the values of distortions Exx at positions respectively 1 nm and 6 nm lower than the origin point of the interface between the p-type silicon (Si) substrate11and the gate insulating layer12.

FIG. 6Dcompares the black circular data30csurrounded by the dashed line and the black circular data30dsurrounded by the solid line. While the distortion Exx of the black circular data30csurrounded by the dashed line is 0.0025 at the interface between the p-type silicon (Si) substrate11and the gate insulating layer12in the n-type MIS transistor10′, the distortions Exx of the black circular data30dsurrounded by the solid line are 0.0030 and 0.0034 respectively in the n-type MIS transistor10.

FIGS. 6C and 6Dillustrate that the positive stress σxx (uniaxial stress) and distortion Exx in the X direction (direction connecting the source region and the drain region) in the n-type MIS transistor10are higher than those in the n-type MIS transistor10′.

The stress σxx and distortion Exx pulling the channel region in the X direction are produced in the channel region through the second side walls14bwhen the stress film16ashrinks in the manufacturing process of the n-type MIS transistor10. It may be thought that since the n-type MIS transistor10includes the second side walls14bof silicon nitride (SiN) at both ends of the channel region, the uniaxial stress and distortion in the X direction produced in the channel region are more increased than those in the n-type MIS transistor10′. Since the distortion Exx contributes to the increase of the carrier mobility in the channel region, as illustrated inFIG. 5, the carrier mobility in the channel region of the n-type MIS transistor10may be increased.

In the MIS transistor and the method of manufacturing the MIS transistor, according to the first embodiment, a second side wall having a higher Young's modulus than the silicon (Si) substrate is formed at both ends of the channel region. By forming the second side wall at both ends of the channel region, the uniaxial stress in the channel region may be increased.

In the MIS transistor and the method of manufacturing the MIS transistor, according to the present embodiment, the first side wall is formed of silicon oxide (SiO2), which is an insulating material. Since the first side wall is made of silicon oxide (SiO2), the withstand voltage between the gate electrode and the source region and between the gate electrode and the drain region may be kept high.

FIGS. 7 to 11are representations of the structure of an n-type MIS transistor20according to a second embodiment and a method of manufacturing the n-type MIS transistor20. In the MIS transistor20and the method of manufacturing the MIS transistor20, according to the second embodiment, the protrusion11bof the MIS transistor20has a lower height than that of the MIS transistor10of the first embodiment. In addition, the first insulating layer14cis formed lower than the height of the protrusion11bby anisotropic etching. By reducing the height of the protrusion11b, the extension regions19of the protrusion11bmay be increased. Since the extension regions19may be increased, the leakage current in the channel region may be reduced.

FIG. 7illustrates the structure of the n-type MIS transistor20according to the second embodiment.FIG. 7Ais a plan view of the n-type MIS transistor20.FIG. 7Bis a sectional view taken along line X-X′ inFIG. 7A. InFIG. 7, the same members as in the first embodiment are designated by the same reference numerals and the same description of these members will be omitted.

InFIG. 7A, reference numeral11bdenotes the protrusion;13denotes a gate electrode;14adenotes a first side wall;14bdenotes a second side wall;18denotes a pocket region;19denotes an extension region;21adenotes a deep source region;21bdenotes a deep drain region;40denotes an active region; and50denotes an element isolation region. The n-type MIS transistor20is an example of the semiconductor device.

As illustrated inFIG. 7A, the element isolation region50is formed around the n-type MIS transistor20. The active region40is a rectangular region defined by the element isolation region50. The gate electrode13extends across the center of the active region40. The first side wall14aand the second side wall14bare formed around the gate electrode13. The pocket regions18and the extension regions19are formed to predetermined widths along the gate electrode13in the active region40. The gate electrode13is formed over the protrusion11b. The deep source region21aand the deep drain region21bare formed in the entire active region40except the gate electrode13, the pocket regions18and the extension regions19.

InFIG. 7B, reference numeral11denotes a p-type silicon (Si) substrate;11bdenotes the protrusion;12denotes a gate insulating layer;13denotes the gate electrode;14adenotes the first side wall;14bdenotes the second side wall;15denotes a silicide layer;16adenotes a stress film;18denotes the pocket region;19denotes the extension region;21adenotes the deep source region; and21bdenotes the deep drain region. InFIG. 7B, the same parts as those inFIG. 7Aare designated by the same reference numerals.

The protrusion11bis formed on the p-type silicon (Si) substrate11. Preferably, the side surface of the protrusion11bis tapered. The protrusion11bhas a height of 6 nm to 10 nm.

The gate insulating layer12is formed on the protrusion11bof the p-type silicon (Si) substrate11. The gate insulating layer12has a thickness of, for example, about 1 nm to 2 nm.

The gate electrode13is formed to a height of, for example, about 100 nm on the gate insulating layer12. Polysilicon (Si) may be used for the gate electrode13.

The source region25aand the drain region25bare provided in the protrusion11bof the p-type silicon (Si) substrate11. The extension regions19are part of the source region25aand the drain region25b. Preferably, the extension regions19are formed to a width of, for example, 40 nm to 60 nm respectively from one edge and the opposite edge of the p-type silicon (Si) substrate11in the region where the gate insulating layer12is disposed, and to a depth of at most 20 nm to 60 nm from the surface of the p-type silicon (Si) substrate11.

The pocket regions18are formed so as to come in contact respectively with one edge and the opposite edge of the p-type silicon (Si) substrate11in the region where the gate insulating layer12is disposed and so as to cover the peripheries of the extension regions19. The pocket regions18and the extensions region19are partially provided in the protrusion11bof the p-type silicon (Si) substrate11. Preferably, the maximum depth of the pocket region18is, for example, 30 nm to 80 nm.

The deep source region21aand the deep drain region21bare formed with a predetermined interval so as to come in contact respectively with the ends of the p-type silicon (Si) substrate11in the regions under the first side walls14a′. Preferably, the maximum depth of the deep source region21aand the deep drain region21bis, for example, 50 nm to 200 nm.

The silicide layer15is formed on the surfaces of the gate electrode13, the deep source region21aand the deep drain region21b. Preferably, the silicide layer15is formed to a thickness of, for example, 20 nm to 70 nm. It is not however necessary to provide the silicide layer15in the present embodiment.

The first side walls14a′ are formed on the side surfaces of the gate electrode13and the side surface of the protrusion11b, and on the p-type silicon (Si) substrate11. The first side wall14a′ may be made of silicon oxide (SiO2), which is an insulating material having a lower Young's modulus than the p-type silicon (Si) substrate11. The thickness of the first side walls14a′ from the surface of the p-type silicon (Si) substrate11other than the protrusion11bis 3 nm or less.

The second side walls14bare formed on the surfaces of the first side walls14a′. Preferably, the bottoms of the second side walls14bare located lower than the upper surface of the protrusion11b. The second side wall14bmay be made of silicon nitride (SiN) having a higher Young's modulus than the p-type silicon (Si) substrate11. The first side wall in the present embodiment corresponds to the first side wall14ain the first embodiment. Accordingly, it is preferable that the thickness of the second side wall14bis about four times as large as the thickness of the first side wall14a′.

The stress film16ais formed over the entire surface of the p-type silicon (Si) substrate11so as to cover the surfaces of the gate electrode13, the first side walls14a′, the second side walls14b, the silicide layer15, the deep source region21aand the deep drain region21b. The stress film16ahas a thickness of, for example, about 70 nm to 90 nm.

FIGS. 8 to 10illustrate a method for manufacturing the n-type MIS transistor20according to the second embodiment. InFIGS. 8 to 10, the same members as those described inFIGS. 2 to 4in the first embodiment are designated by the same reference numerals and the same description of these members will be omitted.

FIG. 8Aillustrates the process operation of forming the gate insulating layer12and the gate electrode13in the same manner as the technique illustrated inFIG. 2Ain the first embodiment.

FIG. 8Billustrates the process operation of forming the pocket regions18, the source region25aand the drain region25b. A first ion implantation is performed on the source region25aand the drain region25b.

The pair of pocket regions18is formed in the same manner as the technique illustrated inFIG. 2Bin the first embodiment.

The extension regions19are part of the source region25aand the drain region25b. The pair of extension regions19is formed by the first ion implantation to the extension regions19of the p-type silicon (Si) substrate11, using the gate electrode13as a mask. For example, arsenic (As) may be used as an n-type conductive impurity. The first ion implantation is performed, for example, under conditions of an accelerated energy of 5 keV and a dose of 1×1014/cm2.

FIG. 8Cillustrates the process operation of forming the protrusion11b.

The protrusion11bis formed with part of the gate insulating layer12and gate electrode13left on the p-type silicon (Si) substrate11. The protrusion11bis formed by anisotropically etching the silicon oxynitride (SiON) layer on the p-type silicon (Si) substrate11using the gate electrode13as a mask, and subsequently performing anisotropic etching using the gate electrode13as a mask again. The anisotropic etching forming the protrusion11bis performed under conditions where the side surface of the protrusion11amay be tapered. For etching of the silicon oxynitride (SiON) layer and the p-type silicon (Si) substrate11, for example, CHF3/Ar/O2gas containing a fluorocarbon gas CHF3or CF4/Ar/O2gas containing a fluorocarbon gas CF4is used. Preferably, the inclination of the tapered surface of the protrusion11bis 30 to 60 degrees.

The extension regions19, which are part of the source region25aand drain region25b, are thus formed in the protrusion11bof the p-type silicon (Si) substrate11. The protrusion11bhas a height of about 6 nm to 10 nm. In this operation, the top of the polycrystalline silicon gate electrode13is also etched to reduce the height.

The MIS transistor20of the present embodiment has a lower protrusion11bthan the MIS transistor10of the first embodiment. By reducing the height of the protrusion11b, the extension regions19of the protrusion11bmay be more increased than those in the MIS transistor10of the first embodiment. Since the extension regions19of the protrusion11bmay be formed larger, the leakage current in the channel region may be reduced.

FIG. 8Dillustrates the process operation of forming a silicon oxide (SiO2) layer14cintended for the first side walls14a′ in the same manner as the technique illustrated inFIG. 2Din the first embodiment. The silicon oxide (SiO2) layer14cis a first insulating layer.

FIG. 9Aillustrates the process operation of anisotropically etching the silicon oxide (SiO2) layer14c.

As illustrated inFIG. 9A, the operation of anisotropically etching the silicon oxide (SiO2) layer14cis intended to reduce the thickness of the silicon oxide (SiO2) layer14cto a level lower than the upper surface of the protrusion11bof the p-type silicon (Si) substrate11. Preferably, the thickness of silicon oxide (SiO2) layer14con the surface of the p-type silicon (Si) substrate11is 3 nm or less. The anisotropic etching of the silicon oxide (SiO2) layer14cis performed by RIE. The anisotropic etching of the silicon oxide (SiO2) layer14cuses C4F8/Ar/O2gas containing a fluorocarbon gas C4F8.

FIG. 9Billustrates the process operation of forming a silicon nitride (SiN) layer14dintended for the second side walls14bin the same manner as the technique illustrated inFIG. 3Ain the first embodiment. The silicon nitride (SiN) layer14dis a second insulating layer.

FIG. 9Cillustrates the process operation of forming the first side walls14a′ and the second side walls14bin the same manner as the technique illustrated inFIG. 3Bin the first embodiment. The first side walls14a′ are thus formed of an insulating material on the side surface of the protrusion11band on the p-type silicon (Si) substrate11. The second side walls14bare formed of a material having a higher Young's modulus than the silicon (Si) substrate on the surfaces of first side walls14a′.

FIG. 9Dillustrates the process operation of forming the deep source region21aand the deep drain region21bin the same manner as the technique illustrated inFIG. 3Cin the first embodiment. A second ion implantation is performed on the deep source region21aand the deep drain region21b.

Then, the ion-implanted impurity may be activated by annealing at 1000° C. for about 10 seconds.

FIG. 10Aillustrates the process operation of forming a silicide layer15in the same manner as the technique illustrated inFIG. 3Din the first embodiment.

FIG. 10Billustrates the process operation of forming a stress film16in the same manner as the technique illustrated inFIG. 4Ain the first embodiment.

The n-type MIS transistor20is thus completed through further operations including the operations of forming an insulating interlayer (not illustrated), forming a contact hole (not illustrated) using the stress film16aas an etching stopper, and forming conductor lines (not illustrated).

The above embodiment has described a MIS transistor using an n-type MIS transistor20. The MIS transistor, however, may be a p-type MIS transistor. In such a case, the conductivity type of the above n-type MIS transistor20is reversed for a p-type MIS transistor.

The embodiment is not limited to the structure, conditions and the like described in the present embodiment. Various modifications may be made in the embodiment.

FIG. 11is a representation illustrating the improvement of the stress and distortion in the channel region of the n-type MIS transistor20according to the second embodiment.

FIG. 11Aillustrates again the n-type MIS transistor10′ illustrated inFIG. 6Ain the first embodiment. Arrows22ain the figure indicate the orientation of the stress σxx and distortion Exx produced in the X direction (direction connecting the source region and the drain region) in the channel region.

FIG. 11Billustrates an n-type MIS transistor20. Arrows22cin the figure indicate the orientation of the stress σxx and distortion Exx produced in the X direction (direction connecting the source region and the drain region) in the channel region. The orientation in which distortion Exx is produced corresponds to that of distortion Exx illustrated inFIG. 5. The difference between the n-type MIS transistor10′ illustrated inFIG. 11Aand the n-type MIS transistor20illustrated inFIG. 11Bis that the n-type MIS transistor20has the protrusion11bof 8 nm in height, and that the thickness of the first side walls14a′ on the surface of the p-type silicon (Si) substrate11is 3 nm or less.

FIG. 11Cillustrates the results of simulations for stress σxx and distortion Exx produced in the vicinity of the channel region in the structures of the n-type MIS transistor10′ and the n-type MIS transistor20. InFIG. 11C, the vertical axis represents the stress σxx in the X direction. The stress σxx is obtained by dividing the length of elongation by the original length, and is dimensionless. The lateral axis ofFIG. 11Crepresents the position in the range of −10 nm to 10 nm, wherein the interface between the p-type silicon (Si) substrate11and the gate insulating layer12is defined as the origin point, and the lower side from the gate insulating layer12is positive and the height direction of the gate electrode13is negative.

In the simulations for obtaining the above-described stress and distortion, the Young's moduli of the silicon oxide (SiO2) of the first side wall14a, the silicon (Si) of the p-type silicon (Si) substrate11, the silicon nitride (SiN) of the second side wall14bare set so as to be increased in that order. Specifically, the Young's modulus of silicon oxide (SiO2) is set at 65 GPa; the Young's modulus of silicon (Si) is set at 130 GPa; and the Young's modulus of silicon nitride (SiN) is set at 200 GPa.

InFIG. 11C, the black square data30asurrounded by a dashed line represents a value of stress σxx in the n-type MIS transistor10′, and the black square data30esurrounded by a solid line represent a value of stress σxx in the n-type MIS transistor20. In this figure, the black square data30asurrounded by the dashed line represents a value of stress σxx along the z axis at the interface between the p-type silicon (Si) substrate11and the gate insulating layer12. The black square data30esurrounded by the solid line represents a value of stress σxx at a position 2 nm lower than the origin point of the interface between the p-type silicon (Si) substrate11and the gate insulating layer12.

FIG. 11Ccompares the black square data30asurrounded by the dashed line and the black square data30esurrounded by the solid line. In the black square data30asurrounded by the dashed line, the stress σxx in the n-type MIS transistor10′ at the interfaced between the p-type silicon (Si) substrate11and the gate insulating layer12was 0.28. In the black square data30esurrounded by the solid line, the stress σxx in the n-type MIS transistor20was 0.31.

FIG. 11Dis a graph illustrating distortions, or Exx, in the longitudinal direction (X direction: direction connecting the source region and the drain region) obtained by simulations using the n-type MIS transistor10′ and the n-type MIS transistor20. InFIG. 11D, the black triangular data30csurrounded by a dashed line represents the distortion Exx in the n-type MIS transistor10′, and the black triangular data30fsurrounded by a solid line represents the distortion Exx in the n-type MIS transistor20. In this figure, the black triangular data30csurrounded by the dashed line represents the value of distortion Exx along the z axis at the interface between the p-type silicon (Si) substrate11and the gate insulating layer12. The black triangular data30fsurrounded by the solid line represents the value of distortion Exx at a position 2 nm lower than the origin point of the interface between the p-type silicon (Si) substrate11and the gate insulating layer12.

FIG. 11Dcompares the black triangular data30csurrounded by the dashed line and the black triangular data30fsurrounded by the solid line. While the distortion Exx of the black triangular data30csurrounded by the dashed line is 0.0025 at the interface between the p-type silicon (Si) substrate11and the gate insulating layer12in the n-type MIS transistor10′, the distortion Exx of the black triangular data30dsurrounded by the solid line is 0.0027 in the n-type MIS transistor20.

FIGS. 11C and 11Dillustrate that the positive stress σxx (uniaxial stress) and distortion Exx in the X direction (direction connecting the source region and the drain region) in the n-type MIS transistor20are higher than those in the n-type MIS transistor10′.

The stress σxx and distortion Exx pulling the channel region in the X direction are produced through the second side walls14bwhen the stress film16ashrinks in the manufacturing process of the n-type MIS transistor20. It may be thought that since the n-type MIS transistor20includes the second side wall14bof silicon nitride (SiN) at both ends of the channel region, the uniaxial stress and distortion in the X direction produced in the channel region are more increased than those in the n-type MIS transistor10′. Since the distortion Exx contributes to the increase of the carrier mobility in the channel region, as illustrated inFIG. 5, the carrier mobility in the channel region of the n-type MIS transistor20may be increased.

In the MIS transistor and the method of manufacturing the MIS transistor, according to the second embodiment, the protrusion11bof the MIS transistor has a lower height than that of the MIS transistor of the first embodiment. In addition, the first insulating layer14cis formed lower than the height of the protrusion11bby anisotropic etching. By reducing the height of the protrusion11b, the extension regions19of the protrusion11bmay be more increased than those in the MIS transistor10of the first embodiment. Since the extension regions19of the protrusion11bmay be increased, the leakage current in the channel region may be reduced.

In the semiconductor device and the method of manufacturing the semiconductor device, according to the present embodiment, a second side wall having a higher Young's modulus than the silicon (Si) substrate is formed at both ends of the channel region. By forming the second side wall at both ends of the channel region, the uniaxial stress in the channel region may be increased.