Integrated circuit with a hibernate mode and method therefor

An integrated circuit (100) includes a firewall input terminal, a first circuit (110, 120, 170, 172), and a second circuit (220). The firewall input terminal is for receiving a firewall input signal. The first circuit (110, 120, 170, 172) is coupled to a first power supply voltage terminal (203) and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal (210), to the firewall input terminal (214), and to the first circuit (110, 120, 170, 172). When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.

FIELD OF THE DISCLOSURE

The invention relates generally to data processors, and more particularly to data processors with low power modes.

BACKGROUND

Low power consumption is an important requirement in the design of data processing systems. For example many applications such as cell phones, personal digital assistants, and the like are powered by a battery. In order to avoid frequent battery changes or the need to connect the battery to a charger, it is desirable that all integrated circuits consume a minimum amount of power. Modern digital integrated circuit fabrication techniques use complementary metal oxide semiconductor (CMOS) transistors that facilitate low power consumption. CMOS logic circuits only consume significant amounts of power when they are switching and integrated circuits built using CMOS technology, or significant portions thereof, may be designed to operate statically, allowing the power to be reduced during periods of inactivity.

Early power reduction techniques were hardware based. For example in an electronic hand held calculator, the user would enable the arithmetic circuitry by depressing a key. The arithmetic circuitry would input the operands and perform the calculation before shutting down.

However these techniques proved to be inadequate for microprocessors which might, for example, perform periodic functions independent of any user input. U.S. Pat. No. 4,758,945 invented by James J. Remedi discloses two software-based techniques for power reduction. The first technique, known as WAIT mode, causes the clock signals to be interrupted between the oscillator and the data processing system in response to a WAIT instruction. WAIT mode takes advantage of the fact that clock signals provided to a static CMOS microprocessor can be interrupted without the microprocessor losing its state. The second technique is known as STOP mode. In STOP mode, not only are the microprocessor's clock signals interrupted, but the oscillator itself is also disabled. Thus even the power consumed by the oscillator circuit is saved. However exit from STOP mode requires a wake-up delay for the clock signals from the oscillator to stabilize before being driven to the microprocessor and STOP mode cannot be used in situations that require fast response to external events. In either WAIT mode or STOP mode, it is possible to continue to supply clock signals to an internal timer, known as a watchdog timer, to periodically wake up the microprocessor.

In MOS integrated circuits that have been placed in STOP mode, the only power consumed is due to leakage currents. In many battery-powered applications it is desirable to reduce power consumption further by eliminating even these leakage currents. However if operational power were removed from the chip, the watchdog timer would be unable to periodically reawaken the chip, and an external wakeup mechanism would be required. Furthermore such external wakeup mechanism requires additional components and adds to system cost. Thus there is a need for a new mode capable of reducing power consumption even further without increasing system cost.

BRIEF SUMMARY

Thus in one form the present invention provides an integrated circuit including a firewall input terminal and first and second circuits. The firewall input terminal is adapted for receiving a firewall input signal. The first circuit is coupled to a first power supply voltage terminal and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal, to the firewall input terminal, and to the first circuit. When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.

In another form the present invention provides an integrated circuit comprising first and second power supply voltage terminals, a firewall input terminal, and first and second circuits. The firewall input terminal receives a firewall input signal. The firewall input signal is active to indicate that a voltage on the first power supply voltage terminal is not valid while a voltage on the second power supply voltage terminal is valid. The first circuit is coupled to the first power supply voltage terminal and has a control output. The second circuit is coupled to the second power supply voltage terminal and has a first control input coupled to the control output of the first circuit and a second control input for receiving the firewall input signal. The control output affects the operation of the second circuit selectively in response to the firewall input signal.

In yet another form the present invention provides a timing comprising a firewall input terminal, a control input terminal, an output terminal, and a firewall circuit. The firewall input terminal receives a firewall input signal. The control input terminal receives a control signal. The output terminal provides a first output signal. The firewall circuit has a first input terminal coupled to the firewall input terminal, a second input terminal for receiving the control signal, and an output terminal for providing a firewalled control signal. When the firewall input signal is active, the firewalled control signal is inactive regardless of a state of the control signal. When the firewall input signal is inactive, a state of the firewalled control signal is determined by the control signal. When active the firewalled control signal affects an operation of the timer.

In still another form the present invention provides a method for operating an integrated circuit. Operational power for a first internal circuit is received via a first power supply voltage terminal. Operational power for a second internal circuit is received via a second power supply voltage terminal. A firewall input signal is received at a firewall input terminal. When active, the firewall input signal indicates that a voltage on the first power supply voltage terminal is not valid while a voltage on the second power supply voltage terminal is valid. The second internal circuit is firewalled from the first internal circuit in response to an activation of the firewall input signal.

In yet another form the present invention provides a method for operating a computer system. Operational power is provided to a first internal circuit of an integrated circuit via a first power supply voltage terminal. Operational power is provided to a second internal circuit of an integrated circuit via a second power supply voltage terminal. A firewall signal is activated. A voltage on the first power supply voltage terminal is removed after activating the firewall signal while keeping operational power on the second power supply voltage terminal valid.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

FIG. 1illustrates in block diagram form a data processing system100according to the present invention. All the devices of data processing system100shown inFIG. 1are combined into a single integrated circuit and thus data processing system100is referred to as a system on chip (SOC). Data processing system100includes generally a central processing unit (CPU) core110, a system bus120, a security engine130, a system bus controller140, a set of bus masters150, a set of bus slaves160, a bus bridge170, a peripheral bus172, and a set of peripherals180.

CPU core110is a conventional CPU that is able to fetch instructions and data via system bus120and execute the instructions so fetched. In the illustrated embodiment CPU core110is a high performance CPU optimized for data intensive applications that executes reduced instruction set computer (RISC) instructions. To support high performance operation for complex SOC tasks it includes separate instruction and data caches and has a five-stage pipeline. However it should be apparent that CPU core110may be any type of CPU capable of running application software such as RISC, complex instruction set computer (CISC), digital signal processor (DSP), etc.

System bus120is a high-speed bus having a control bus portion, a 36-bit address bus portion, and a 32-bit data bus portion. System bus120is the coherency point within system100. A bus master marks a system bus transaction as either coherent or non-coherent. Transactions that are marked as coherent are then snooped by all caching masters, such as the data cache in CPU core110. Transactions that are marked as non-coherent are not snooped. CPU core110is a coherent caching master, whereas the alternate bus masters in set150can be programmed for coherent or non-coherent operation. For example the data cache in CPU core110snoops transactions on system bus120. If a read transaction hits in the data cache, then it provides the data to system bus120. If a write transaction hits in the data cache then the data cache array is updated with the new data. If an alternate bus master initiates a coherent cycle, then it is not necessary to write back and invalidate lines in the data cache in CPU core110that hit in the alternate bus master's memory buffers. If an alternate bus master is configured for non-coherent operation, however, then software must ensure that data in its memory buffers has not been stored in the data cache to prevent the data buffer from containing old, stale data.

Security engine130has data encryption and decryption capabilities for such tasks as the encryption and decryption of Internet packets for secure transmission. It includes a two-channel DMA controller that is able to request and gain access to system bus120via a system bus interface. Security engine130processes data in a packet controller block, and is assisted by a hardware random number generator. It also generates interrupts through a dedicated interrupt provided to interrupt controller188, described further below.

System bus controller140is a logic circuit adapted to receive requests for bus ownership and grant them in an ordered fashion. One bus master is CPU core110, which has an output for providing a request signal labeled “REQ” and an input for receiving a grant signal labeled “GNT”. A set of four alternative bus masters from set150each also output a corresponding request signal REQ and receive a corresponding grant signal GNT. System bus controller140arbitrates for use of system bus120using a least recently used/fair arbitration scheme. This scheme prevents two or more masters from consuming the entire system bus bandwidth, while permitting low latency access to system bus120for masters that request the bus infrequently, such as peripherals.

System Bus Masters

System bus120conducts address, data, and control signals as determined by bus masters that have ownership of it. These bus masters include CPU core110and set of bus masters150. As shown inFIG. 1set150includes four bus masters including a direct memory access (DMA) controller151, two Ethernet media access controllers (MACs)152and153, and a universal serial bus (USB) host154.

DMA controller151has a bidirectional connection to system bus120, an output for providing a request signal REQ, and an input for receiving a grant signal GNT. DMA controller151has eight channels. Each channel is capable of transferring data between memory and peripherals or between memory and a memory mapped first-in, first-out (FIFO) buffer through SRAM controller161, and using a general-purpose input/output pin as a request line. The channel characteristics are programmable via system bus120. Software running on CPU core110initializes DMA controller151and programs its channels with the appropriate starting address, ending address, and length. In addition each channel has programmable modes of operation including identification of the peripheral device involved in the transfer, byte order (big Endian or little Endian), transfer direction, transfer size, data width, whether coherency is marked on the system bus, interrupt enable, and channel halted status.

Each of Ethernet MACs152and153performs the media access control function of layer2of the open systems interconnect (OSI) reference model specified in section 4 of American National Standards Institute/Institute of Electrical and Electronics Engineers (ANSI/IEEE) standard 802.3, commonly referred to as “Ethernet”. Ethernet MACs152and153are bidirectionally connected to respective external physical layer (layer1) devices using the Media Independent Interface (MII) described in the IEEE 802.3u standard. The logical link control portion of layer2and higher layers of the OSI stack may be performed by software running on CPU core110. In order to perform the overhead tasks associated with frame construction, Ethernet MACs152and153include a dedicated DMA engine to access system bus120so that DMA controller151is not required. Note that since Ethernet MACs152and153actually share a common DMA engine, this DMA engine only outputs a single REQ output and receives a single GNT input instead of the two shown inFIG. 1.

USB host154is a device conforming to the Universal Serial Bus Specification that implements a communication architecture and interface to allow for the connection of multiple peripherals through a single port while also providing digital telephony capabilities. A USB is used to connect a USB device with a USB host. For example, a USB may connect a microcontroller (i.e., USB device) to a computer system (i.e., USB host). Each USB device is composed of a collection of independently operating endpoints. An endpoint, which is the ultimate consumer or provider of data, is a uniquely identifiable portion of a USB device that is the terminus of a communication flow between the USB host and the USB device. USB host154conforms to the Open HCI Interface specification, revision 1.0, as well as being compliant with revision 1.1 of the USB specification. It provides two root hub ports, port0and port1, and provides four external interface pins corresponding to the positive and negative signals of each of port0and port1. USB Host154is programmed from the system bus, and has a host enable control register that determines whether the reset done status is to be polled, which clocks to be enabled, whether the USB controller is enabled or held in reset, whether coherency is marked on the system bus, and byte order (big Endian or little Endian).

System Bus Slaves

Data processing system100also includes a set of bus slaves160bidirectionally connected to system bus120. Set of bus slaves160includes a static random access memory (SRAM) controller161, a double data rate/single data rate (DDR/SDR) memory controller162, an enhanced joint test action group (EJTAG) controller163, and a personal computer interconnect (PCI) interface164.

SRAM controller161provides a general-purpose interface to SRAM and a variety of external peripherals and memory devices. It includes four programmable regions, each providing an external device chip select signal when accessed from system bus120. Each of the four static bus chip selects may be programmed to support many different device types, including SRAM, NOR and NAND flash memory, read-only memory (ROM), personal computer memory card interface association (PCMCIA) compliant devices, and other kinds of input/output (I/O) peripherals. SRAM controller161provides three registers that are programmable from system bus120to define the memory location and characteristics of each of four regions, including a configuration register, a timing parameters register, and an address region control register.

DDR/SDR controller162provides a glueless interface for systems using either DDR or SDR synchronous dynamic random access memory (SDRAM). It supports three programmable regions having corresponding chip select output signals. Each region has a mode configuration register, an address configuration and enable register, and a write data register, and each region is programmable for operation with either DDR or SDR SDRAM devices. When a region has been programmed to DDR mode, DDR/SDR controller162supports DDR200, DDR266, DDR333, and DDR400timing as specified in JEDEC Standard JESD79C with fourteen address bits and two differential clock output pairs. When a region has been programmed to DDR mode, it supports fourteen address bits with two clock outputs. In either more DDR/SDR controller162supports three ranks of SDRAM devices. Each rank can be either one 32-bit SDRAM device or two 16-bit SDRAM devices. Each device can contain either two or four banks. DDR/SDR controller162also includes an 8-entry open bank address tag with a least-recently-used (LRU) replacement algorithm, and supports stride transfers initiated by DMA controller151.

EJTAG (Enhanced Joint Test Action Group) controller163implements a modified version of the JTAG test interface (specified in IEEE 1149.1) described in the EJTAG 2.5 specification published by MIPS Computer, Inc. EJTAG controller163supports the extended instructions SDBBP and DERET, debug exceptions, extended CP0 registers known as DEBUG, DEPC, and DESAVE, the EJTAG memory range from 0xFF200000 through 0xFF3FFFFF, processor bus breakpoints (EJTAG 2.0), memory overlay (EJTAG 2.0, and an EJTAG test access port per IEEE 1149.1. EJTAG controller163also supports an implementation-specific feature by providing instruction and data breakpoints through the watch exception.

PCI Interface controller164is compatible with version 2.2 of the PCI Interface standard. It bridges transactions between system bus120and an external PCI bus operating at either 33 MHz or 66 MHz. PCI interface controller164provides a glueless interface to up to four external PCI devices. It has several flexible modes of operation. For example, it can execute processor-initiated master transactions to the PCI bus as well as accept external PCI target transactions to local memory.

Peripheral Bus Devices

Peripheral device set180includes several lower bandwidth peripherals connected to peripheral bus172and accessible from system bus120through bus bridge170. Bus bridge170appears as a bus slave to system bus120. The peripherals in set180include a real-time clock (RTC) and time-of-year (TOY) timer181, a power management controller182, four programmable serial controllers (PSCs)183, a set of three universal asynchronous receiver-transmitters (UARTs)185, an I2S bus controller186, a set of 43 general purpose I/O pins187, an interrupt control block188, and a USB device controller189. The basic function of each of these blocks is described in TABLE I:

TABLE IBlockDescriptionRTC AND TOYReal time clock and time-of-year clock. The RTC181uses a counter to function as a conventional realtime clock. The TOY clock is designed to operateas a continuously running clock. In hibernate mode,the TOY clock continues to operate and is firewalledfrom the rest of the chip.POWER MGMTPower management controller. This block provides182multiple power saving options that can be chosendepending on whether power conservation or systemresponsiveness is most critical.PSCs 183Synchronous serial interfaces. These two ports aredesigned to provide a simple connection to externalserial devices, with one port supporting thesynchronous serial interface (SSI) protocol and theother supporting a subset of the serial peripheralinterface (SPI) protocol.UARTs 185Universal asynchronous receiver/transmitters. Thesethree channels provide serial links for devices suchas keyboards and are similar to the personalcomputer industry standard 16550 UART.GPIO 187General-purpose I/O ports. These ports areprogrammed using a data register and a datadirection register and the pin functions are sharedwith other devices.INTERRUPTInterrupt controllers. Each of two interruptCONTROL 188controllers supports 32 interrupt sources andgenerates interrupt signals that are input toCPU core 110.USB-DEVICE 189Universal serial bus device controller, supportingendpoints 0, 2, 3, 4, and 5.

Each of these blocks has a set of registers associated with their particular operation. In general they also have an associated base address register that defines the starting address of their register block. The devices' registers are accessed from system bus120and the devices themselves transfer data over system bus120through bus bridge170.

Power Management

According to the present invention data processing system100has circuitry within multiple power supply voltage domains. In a new mode known as the “hibernate” mode, power may be removed from all the power supply voltage domains except one. In the illustrated embodiment this power supply voltage domain includes a time-of-year (TOY) clock circuit that maintains a real-time clock. Maintaining the TOY clock while powering down the rest of the chip is especially useful for battery-powered applications such as personal digital assistants (PDAs), smart cellular telephones, hand held Internet appliances, and the like.

During hibernate mode data processing system100erects a “firewall” between the TOY clock and the rest of the chip. As used herein “firewall” means a circuit that is interposed in some way between two other circuits to keep one from affecting the other, in a manner analogous to that of a fireproof wall erected to prevent the spread of fire from one room to the next. In the illustrated embodiment during hibernate mode a firewall circuit is responsive to the receipt of a special firewall input signal, labeled “FWTOY”, to keep internal circuitry which is powered down from affecting the TOY clock, which continues to receive power and operate during hibernate mode.

Reference is now made toFIG. 2, which illustrates a portion200of data processing system100including a TOY clock220that forms a portion of RTC and TOY block181. Portion200includes several integrated circuit terminals201-204and210-216in the form of bonding pads suitable for connection to integrated circuit package terminals by known techniques such as wire bonding or bumping. Note thatFIG. 2is a functional diagram and is not meant to imply any spatial relationship on the periphery of the integrated circuit die between the various terminals.

Terminals201-204form power supply voltage terminals for internal circuitry. Power supply terminals201-203receive positive power supply voltages labeled “VDDX”, “VDDY”, and “VDDI”, respectively, and power supply terminal204receives a ground power supply voltage labeled “VSS”. A power supply for most input/output circuitry in an I/O power supply voltage domain is formed between VDDX and VSS. A power supply for the input/output circuitry associated with DDR/SDRAM controller162in a DDR/SDRAM I/O power supply voltage domain is formed between VDDY and VSS. A power supply for internal circuitry in an internal circuitry power supply voltage domain is formed between VDDI and VSS. These power supply voltages can assume optimal levels appropriate to their domains. For example it is desirable to operate VDDI at a relatively low voltage, for example 1.2 volts, to minimize power consumption. However the I/O power supplies need higher voltages, for example 3.3 volts, to allow integrated circuit100to interface properly with external components. Note that circuit blocks include levels shifters for exchanging signals between voltage domains, which helps avoid crowbar currents.

The remaining terminals210-216are associated with TOY clock220and include a power supply terminal210for receiving a positive power supply voltage labeled “XPWR32”, an input/output terminal211for conducting a general purpose input/output signal labeled “GPIO[1]” which in one mode provides an input to TOY clock220, an input terminal212for receiving a crystal input signal labeled “XTI32”, an output terminal213for providing a crystal output signal labeled “XTO32”, an input terminal214for receiving theFWTOYinput signal, an output terminal215for providing a control signal labeled “WAKE”, and a power supply terminal216for receiving a ground power supply voltage labeled “XAGND32”. A power supply for the circuitry associated with TOY clock220and a crystal oscillator, known as the 32.768 kHz oscillator supply voltage domain, is formed between XPWR32and XAGND32. XPWR32is preferably relatively high, for example about 3.3 volts, to ensure proper operation of a crystal oscillator, described below.

TOY clock220includes an oscillator222having a control input terminal for receiving a control signal labeled “EO”, a crystal input terminal connected to terminal212, a crystal output terminal connected to terminal213, and a clock output terminal. The recommended external crystal has a fundamental frequency of 32.768 kHz, which is the well-known color burst frequency. A multiplexer224has a first input terminal labeled “1” connected to terminal211, a second input terminal labeled “0” connected to the output terminal of oscillator222, a control input terminal for receiving a signal labeled “BP”, and an output terminal. TOY clock220uses multiplexer224to select between one of two possible clock sources based on control signal BP, namely an externally supplied clock received on the GPIO[1] signal pin, terminal211, or the crystal controlled signal received from the output terminal of oscillator222.

A divider226has an input terminal connected to the output terminal of multiplexer224, a preset input terminal for receiving a 16-bit value labeled “TRIM”, and an output terminal. Divider226divides the clock signal selected by multiplexer226by a programmable amount equal to the TRIM bits plus one to provide a divided clock signal to the output terminal thereof.

Counter228has an input terminal connected to the output terminal of divider226, a preset input terminal for receiving a 32-bit value labeled “COUNT”, and an output terminal. Counter228counts the number of pulses at the output of divider226to provide a count value to the output terminal thereof.

TOY clock220also includes three match circuits232,234, and236. Each match circuit has an input connected to the output terminal of counter228, and an output terminal that provides an interrupt output signal when the output of counter228matches a programmable match value set in a corresponding match register. Additional features of match circuits232,234and236are not explicitly illustrated inFIG. 2. For example each match circuit includes a data input terminal that receives its programmable match value, and a write enable terminal that receives a corresponding write enable signal. The programmable match value is received from a data portion of peripheral bus172in a manner that will be described more fully below. The write enable signal is active when an access is made to a memory-mapped location corresponding to the particular match register. The outputs of counter228and of each match register are provided to corresponding inputs of interrupt controller188ofFIG. 1. Thus the occurrence of a particular count value can trigger an interrupt and CPU core110can take an appropriate action after receiving the interrupt.

TOY clock220also includes a set of registers useful for controlling the operation thereof.FIG. 2illustrates three exemplary registers useful in understanding the present invention including a control register242labeled “sys_cntrctrl”, a trim register244labeled “sys_toytrim”, and a count register246labeled “sys_toywrite”. Control register242has a data input terminal connected to a 32-bit DATA bus that forms a portion of peripheral bus172ofFIG. 1, a write enable input terminal, a first output terminal connected to the control input terminal of buffer224for providing the EO bit, and a second output terminal connected to the control input terminal of multiplexer226for providing the BP bit. Control register242is operable to store a control register value therein when the signal at its write control input terminal is active. It also includes additional control bits, not shown inFIG. 2, that control other aspects of TOY clock220. Trim register244has a data input terminal connected to the 32-bit data bus, a write control input terminal, and an output terminal connected to the trim input terminal of divider228for providing a 16-bit value labeled “TRIM”. Trim register244is operable to store a divider value therein when the signal at its control input terminal is active. Count register246has a data input terminal connected to the 32-bit data bus, a write control input terminal, and an output terminal connected to the count input terminal of counter230for providing a 32-bit value labeled “COUNT”. Count register246is operable to store an initial counter value therein when the signal at its control input terminal is active.

In order to implement the firewall mechanism TOY clock220includes a firewall circuit250. Firewall circuit250includes AND gates251-255. Each AND gate has a first input terminal connected to input terminal214for receiving the firewall signalFWTOYtherefrom. AND gate251has a second input terminal for receiving a first control signal from a control bus, and an output terminal connected to the control input terminal of register242. AND gate252has a second input terminal for receiving a second control signal from the control bus, and an output terminal connected to the control input terminal of register244. AND gate253has a second input terminal for receiving a third control signal from the control bus, and an output terminal connected to the control input terminal of register246. AND gate254has a second input terminal for receiving an input signal labeled “RESET”, and an output terminal for providing a signal labeled “TOY RESET”. AND gate255is representative of thirty-two AND gates each having a first input terminal connected to input terminal214for receiving the firewall signal therefrom, a second input terminal connected to a corresponding bit of a 32-bit DATA bus portion of peripheral bus172, and an output terminal for providing the internal DATA value.

Firewall circuit250uses three mechanisms to place a “firewall” between circuitry in the XPWR23domain and all other circuits. The first firewall mechanism prevents select signals on the CONTOL portion of peripheral bus172, which may have indeterminate values during hibernate mode, from spuriously selecting any of registers242,244, and246. Each of registers242,244, and246is a memory-mapped register that is selected when an address conducted on peripheral bus172matches its corresponding address in the memory map. During normal operation CPU core110can update any one of these registers by outputting a corresponding address on system bus120. Bus bridge170recognizes that the access is within a range of addresses associated with peripheral bus172and drives the system address signals onto peripheral bus172. Decoder circuitry not shown inFIGS. 1 and 2compares the address conducted on peripheral bus172to the base addresses of each of registers242,244, and246and outputs a select signal on a CONTROL bus portion of peripheral bus172to select the corresponding register. AND gates251,252, and253gate off the select signal during hibernate mode. Thus the first firewall mechanism preserves the control registers from being spuriously selected resulting in their contents being overwritten.

The second firewall mechanism firewalls the TOY RESET signal. TOY RESET is provided to most circuit blocks in TOY clock220to return them to appropriate initial states. However during hibernate mode TOY clock220continues to operate uninterrupted. AND gate254prevents indeterminate values on the RESET signal of peripheral bus172from resulting in the activation of TOY RESET. Thus the second firewall mechanism prevents TOY clock220from being spuriously reset during hibernate mode.

The third firewall mechanism firewalls the DATA bus. During hibernate mode the signals on the DATA bus portion of peripheral bus172assume indeterminate levels. These signals may actually assume an intermediate logic state at a voltage between a logic low voltage and a logic high voltage. Normally CMOS logic circuits only consume power when the input signals transition through intermediate logic states. However if an input signal remains at the intermediate logic state during hibernate mode then a logic circuit to which it is connected in TOY clock220would experience a virtual short. This virtual short would cause a relatively high leakage current and defeat the extremely low power consumption otherwise provided during hibernate mode. Thus the third firewall mechanism prevents unnecessary power consumption during hibernate mode caused by indeterminate levels on input signals.

Thus firewall circuit250builds a firewall between circuits in the XPWR32domain and circuits in all other power domains. Firewall circuit250uses these three exemplary mechanisms to ensure continued safe operation during hibernate mode.

Note that in other embodiments other firewall mechanisms may be used. Note also that registers242,244, and246are merely exemplary and TOY clock220includes additional registers that are firewalled in a similar manner during hibernate mode. For example each of match circuits232,234, and236include corresponding match registers that are memory-mapped and can be written to during normal operation. Thus firewall circuit250includes further circuitry to cause spurious values from being written to these match registers. Firewall circuit250may also be implemented using other logic circuitry besides the AND gates shown inFIG. 2. For example, the same function could be accomplished using NOR gates with negative logic, transmission gates with pulldown elements, etc. In addition other circuits or types of circuits may be placed inside the firewall. For example in the illustrated embodiment the RTC portion of RTC and TOY block181and POWER MANAGEMENT block182are also in the XPWR32domain and are placed within the firewall.

TOY clock220also includes a mechanism for externally waking up data processing system100from hibernate mode. Since TOY clock220is still operational in hibernate mode, it advantageously provides an open-drain output signal, theWAKEsignal, to indicate that the output of228has reached the value programmed into MATCH2 register236. Thereafter external power control circuitry not shown inFIG. 2can wake up system100by restoring power to the other power supply voltage domains. Thus for example an external power controller chip could be designed that would generate different desired voltage levels for each of the power supply voltage domains, disable each of these domains appropriately in each low power state of operation, and respond to theWAKEsignal to restore data processing system100to normal operation mode.

Accordingly note that in the illustrated embodiment data processing system100is capable of operating in any of the power states shown in TABLE II below:

Two registers not illustrated inFIG. 2are important in the operation of TOY clock220during hibernate mode. The first register, known as the “sys_wakesrc” register, is useful to system operation upon waking up from hibernate mode. Activating RESET, powering up, or waking up from hibernate mode all cause CPU core110to start fetching instructions from an initial address known as a boot vector. The sys_wakesrc register includes status bits that allow software to distinguish between hibernate wakeup and normal reset or power up, and to take appropriate action. For example if the system is powering up, TOY clock220should be initialized. However if the system is waking up from hibernate mode, TOY clock220does not need to be initialized. The second register is known as the “sys_wakemsk” register, and includes a bit to determine whether theWAKEsignal is activated in response to a match in MATCH2 register236. It also includes a bit to determine whether the system can be awakened from the SLEEP state in response to a match in MATCH2 register236, and bits to determine whether any of a group of general purpose I/O bits can cause a wakeup from the SLEEP state. Both the sys_wakesrc and the sys_wakemsk registers are firewalled in the same manner as registers242,244, and246during hibernate mode.

FIG. 3illustrates a timing diagram300of signals associated with data processing system100entering hibernate mode. In timing diagram300the vertical axis represents voltage and the horizontal axis represents time. Timing diagram300illustrates VDDX in a waveform302, a VDDX validation signal labeled “VDDXOK” in a waveform304, and firewall signalFWTOYwaveform306. At a time to data processing system100enters hibernate mode in response to the activation of the firewall signalFWTOY.FWTOYmust be asserted at least a minimum setup time310before the removal of VDDX and at least a minimum setup time312before the inactivation of VDDXOK at time t1. OnceFWTOYasserts, the operation of TOY clock220is protected and the de-assertion of VDDXOK does not affect it. VDDXOK may then de-assert at any time or even become indeterminate for a length of time, provided that it resolves to a logic low value at least a minimum setup time314before its subsequent activation at time t3.

WhileFIG. 3shows the minimum timing relationships required for entry into and exit from hibernate mode, other system configurations are possible. For example it is possible to not use hibernate in a so-called “never hibernate” system by tying both XPWR32andFWTOYto VDDX. Thus XPWR32ramps with VDDX andFWTOYis seen as de-asserted when VDDXOK rises, and time periods312and316are zero. However in a so-called “always hibernate” system,FWTOYis tied to VDDXOK. VDDXOK is de-asserted before VDDX drops and remains de-asserted until VDDX rises, ensuring that the minimum timing requirements forFWTOYare met. In the “always hibernate” system every activation of VDDXOK causes a hibernate wakeup. XPWR32is tied to a supply, such as a battery, which is always valid even during hibernate.

Note that the integrated circuit100could be part of a larger computer system that includes both integrated circuit100and a power controller chip. This power controller chip would not only generate the power supply voltages in each of the available power supply voltage domains but also control the transition between low power states. Such a power supply controller chip would activate VDDXOK andFWTOYappropriately to enter hibernate mode, and would awaken from hibernate mode using theWAKEsignal. Such a system includes substantial flexibility in minimizing power consumption while using the integrated TOY clock220. Thus the design of the power controller chip can be greatly simplified.