INTEGRATED CIRCUIT DEVICES AND METHODS OF FORMING THE SAME

Integrated circuit devices may include a substrate including a word line trench extending longitudinally in a first horizontal direction, a gate dielectric film extending along an inner surface of the word line trench, a word line in a lower portion of the word line trench on the gate dielectric film and extending longitudinally in the first horizontal direction, and an insulating capping pattern in an upper portion of the word line trench on the word line and extending longitudinally in the first horizontal direction. The word line may include a work-function control conductive plug including a conductive metal nitride that include a metal dopant, and the work-function control conductive plug includes a top surface in contact with a bottom surface of the insulating capping pattern, a sidewall in contact with the gate dielectric film, and a bottom surface in contact with a monolithic layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0178693, filed on Dec. 19, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The inventive concept relates to an integrated circuit (IC) device, and more particularly, to an IC device including a buried word line.

As the integration density of IC devices including a plurality of word lines of a buried channel array transistor (BCAT) formed in a substrate increases, a pitch between the plurality of word lines has decreased, and a gate induced drain leakage (GIDL) current has increased. Thus, refresh characteristics of the IC devices may be adversely affected. Accordingly, to reduce/inhibit the occurrence of a GIDL current and precisely control a threshold voltage of a gate electrode, a gate electrode including heterogeneous materials having different work functions has been developed.

SUMMARY

The inventive concept provides an integrated circuit (IC) device, which may reduce or inhibit the occurrence of a leakage current while reducing a resistance of a word line, and have improved electrical characteristics, such as refresh characteristics.

According to an aspect of the inventive concept, there is provided an IC device including a substrate including a word line trench, the word line trench extending longitudinally in a first lateral direction, a gate dielectric film extending along (e.g., covering) an inner surface of the word line trench, a word line in (e.g., filling) a lower portion of the word line trench on the gate dielectric film, the word line extending longitudinally in the first lateral direction, and an insulating capping pattern in (e.g., filling) an upper portion of the word line trench on the word line, the insulating capping pattern extending longitudinally in the first lateral direction, wherein the word line includes a work-function control conductive plug including a conductive metal nitride including a metal dopant, and the work-function control conductive plug includes a top surface in contact with a bottom surface of the insulating capping pattern, a sidewall in contact with the gate dielectric film, and a bottom surface in contact with a single layer (e.g., a monolithic layer). In some embodiments, the conductive metal nitride may be formed by doping the conductive metal nitride with the metal dopant.

According to other aspect of the inventive concept, there is provided an IC device including a substrate including a plurality of active regions and a word line trench, the plurality of active regions being defined by a device isolation film, and the word line trench extending longitudinally in a first lateral direction across the plurality of active regions, a gate dielectric film in contact with the plurality of active regions and the device isolation film inside the word line trench, a word line in (e.g., filling) a lower portion of the word line trench on the gate dielectric film, the word line extending longitudinally in the first lateral direction, an insulating capping pattern in (e.g., filling) an upper portion of the word line trench on the word line, the insulating capping pattern extending longitudinally in the first lateral direction; and a pair of source/drain regions on respective sides of the word line in one of the plurality of active regions, wherein the word line includes a work-function control conductive plug including a conductive metal nitride that includes a metal dopant, the work-function control conductive plug including a gate top surface in contact with the insulating capping pattern and a pair of upper sidewalls in contact with the gate dielectric film, the pair of upper sidewalls facing the pair of source/drain regions, respectively, and the work-function control conductive plug filling the word line trench in a second lateral direction without being cut off between the pair of upper sidewalls, wherein the second lateral direction is perpendicular to the first lateral direction, and a first conductive plug including an undoped conductive metal nitride, the first conductive plug including a first top surface in contact with a bottom surface of the work-function control conductive plug and a pair of first sidewalls in contact with the gate dielectric film, and the first conductive plug filling the word line trench in the second lateral direction without being cut off between the pair of first sidewalls. In some embodiments, the conductive metal nitride may be formed by doping the conductive metal nitride with the metal dopant. In some embodiments, the work-function control conductive plug extends continuously in the second horizontal lateral direction between the pair of upper sidewalls, and the first conductive plug extends continuously in the second lateral direction between the pair of first sidewalls.

According to other aspect of the inventive concept, there is provided an IC device including a substrate including a word line trench, the word line trench extending longitudinally in a first lateral direction, a gate dielectric film extending along (e.g., covering) an inner surface of the word line trench, a word line in (e.g., filling) a lower portion of the word line trench on the gate dielectric film, the word line extending longitudinally in the first lateral direction, and an insulating capping pattern in (e.g., filling) an upper portion of the word line trench on the word line, the insulating capping pattern extending longitudinally in the first lateral direction, wherein the word line includes a titanium nitride (TiN) plug that includes a lanthanum (La) as a dopant and includes a gate top surface in contact with the insulating capping pattern and a pair of upper sidewalls in contact with the gate dielectric film, the TiN plug filling the word line trench in a second lateral direction without being cut off between the pair of upper sidewalls, wherein the second lateral direction is perpendicular to the first lateral direction, and an undoped TiN plug having a first top surface in contact with a bottom surface of the TiN plug and a pair of first sidewalls in contact with the gate dielectric film, the undoped TiN plug filling the word line trench in the second lateral direction without being cut off between the pair of first sidewalls, wherein, one of the pair of upper sidewalls and one of the pair of first sidewalls are on the same plane extend along one planar surface without a step adjacent to an interface between the TiN plug and the undoped TiN plug. In some embodiments, the TiN plug is formed by doping the TiN plug with the La dopant. In some embodiments, TiN plug extending continuously in the second lateral horizontal direction between the pair of upper sidewalls, and the undoped TiN plug extending continuously in the second lateral horizontal direction between the pair of first sidewalls. In some embodiments, the one of the pair of upper sidewalls and the one of the pair of first sidewalls may be on the same plane without a step adjacent to the interface between the La-doped TiN plug and the undoped TiN plug.

DETAILED DESCRIPTION

Hereinafter, example embodiments of the present inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements in the drawings, and repeated descriptions thereof are omitted.

FIG.1is a layout diagram of a memory cell array region of an integrated circuit (IC) device100according to some embodiments of the present inventive concept. Although not shown inFIG.1, the IC device100may include various components in addition to those shown inFIG.1.

Referring toFIG.1, the IC device100may include a plurality of active regions AC, which extend longitudinally in an oblique direction with respect to each of a first lateral direction (also referred to as a first horizontal direction and, for example, X direction) and a second lateral direction (also referred to as a second horizontal direction and, for example, Y direction) on an X-Y plane. A plurality of word lines WL may intersect the plurality of active regions AC and extend longitudinally in the first lateral direction (e.g., X direction). Each of the plurality of word lines WL may have a substantially constant width in the second lateral direction along the first lateral direction (e.g., X direction).

On the plurality of word lines WL, a plurality of bit lines BL may extend parallel to each other longitudinally in the second lateral direction (e.g., Y direction). The plurality of bit lines BL may be connected to the plurality of active regions AC through the direct contacts DC.

A plurality of buried contacts BC may be between two adjacent ones of the plurality of bit lines BL. A plurality of conductive landing pads LP may be on the plurality of buried contacts BC, respectively. The plurality of buried contacts BC and the plurality of conductive landing pads LP may connect a lower electrode of a capacitor formed on the plurality of bit lines BL to the active region AC. At least a portion of each of the plurality of conductive landing pads LP may overlap the buried contact BC.

FIGS.2A to2Dare cross-sectional views of the IC device100according to some embodiments of the present inventive concept.FIG.2Ais a cross-sectional view taken along a line X1-X1′ ofFIG.1.FIG.2Bis a cross-sectional view taken along a line X2-X2′ ofFIG.1.FIG.2Cis a cross-sectional view taken along a line Y1-Y1′ ofFIG.1.FIG.2Dis an enlarged cross-sectional view of a portion “EX1” ofFIG.2C. Although not shown inFIGS.2A to2D, the IC device100may include various components in addition to those shown inFIGS.2A to2D.

Referring toFIGS.2A to2D, the IC device100may include a substrate102in which a device isolation trench104T is formed. The device isolation trench104T may be filled by a device isolation film104. A plurality of active regions AC may be defined by the device isolation trench104T and the device isolation film104in the substrate102.

The device isolation film104may surround the plurality of active regions AC on the substrate102. The device isolation film104may include, for example, a silicon oxide film, a silicon nitride film, or a combination thereof. A vertical level of a bottom surface of the device isolation trench104T or a depth of the device isolation trench104T may vary according to a width of the device isolation trench104T in a lateral direction (e.g., the first lateral direction or the second lateral direction). As the width of the device isolation trench104T in the lateral direction increases, the vertical level of the bottom surface of the device isolation trench104T may be farther from a main surface102M of the substrate102. As used herein, the term “vertical level” refers to a distance from the main surface102M of the substrate102in a vertical direction (e.g., Z direction or −Z direction).

The substrate102may include, for example, silicon (e.g., single crystalline silicon, polycrystalline silicon, or amorphous silicon). In some other embodiments, the substrate102may include at least one selected from germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, the substrate102may include a conductive region, for example, a doped well or a doped structure.

A plurality of word line trenches WT may be formed in the substrate102and extend parallel to each other in the first lateral direction (e.g., X direction). Each of the plurality of word line trenches WT may have a line shape, which intersects with the plurality of active regions AC and the device isolation film104and extends longitudinally in the first lateral direction (e.g., X direction). The inside of each of the plurality of word line trenches WT may be filled by a gate dielectric film120, the word line WL, and the insulating capping pattern128.

As shown inFIG.2A, each of the plurality of word line trenches WT includes first portions of a bottom surfaces on the plurality of active regions AC, which may be at a higher vertical level than second portions of the bottom surface on the device isolation film104. Accordingly, a bottom profile of each of the plurality of word line trenches WT may have a concavo-convex shape, and a bottom surface of the word line WL may have a concavo-convex shape corresponding to the bottom profile of the word line trench WT. A plurality of fin areas AF may be formed in the plurality of active regions AC. The plurality of fin areas AF may protrude upward in the vertical direction (e.g., Z direction) toward the word line WL under the word line WL to correspond to the bottom profile of the word line trench WT.

As shown inFIGS.2A and2C, the plurality of word line trenches WT may include a first trench portion T1A and a second trench portion T1B. The first trench portion TIA may be in the substrate102and have a lowermost surface at a first vertical level LV1. The second trench portion T1B may be in the device isolation film104and have a lowermost surface at a second vertical level LV2. The second vertical level LV2may be lower than the first vertical level LV1.

The gate dielectric film120may conformally cover an inner surface of the word line trench WT to contact the plurality of active regions AC and the device isolation film104. The gate dielectric film120may include, for example, a silicon oxide film (e.g., a SiO2film). The gate dielectric film120may have a thickness of, for example, about 10 nm to about 30 nm, without being limited thereto.

Each of the plurality of word lines WL may fill a lower space (also referred to as a lower portion), which is a first portion of the word line trench WT, on the gate dielectric film120and extend longitudinally in the first lateral direction (e.g., X direction). Each of the insulating capping pattern128may fill an upper space (also referred to as an upper portion), which is a second portion of the word line trench WT, on a corresponding one of the plurality of word lines WL and extend longitudinally in the first lateral direction (e.g., X direction). The first portion and the second portion of the word line trench WT are different portions.

As shown inFIGS.2A,2C, and2D, each of the plurality of word lines WL may include a first conductive plug122A and a work-function control conductive plug122B, which overlap each other in the vertical direction (e.g., Z direction). In the vertical direction (e.g., Z direction), the work-function control conductive plug122B may be between the first conductive plug122A and the insulating capping pattern128. The first conductive plug122A may be spaced apart from the insulating capping pattern128in the vertical direction (e.g., Z direction) with the work-function control conductive plug122B therebetween. A top surface of the work-function control conductive plug122B may be in contact with a bottom surface of the insulating capping pattern128, and a bottom surface of the work-function control conductive plug122B may be in contact with a top surface of the first conductive plug122A. As used herein, the top surface of the work-function control conductive plug122B may be referred to as a gate top surface, and the top surface of the first conductive plug122A may be referred to as a first top surface. As used herein, “an element A vertically overlapping an element B” (or similar language) means that at least one vertical line can be drawn that intersects both elements A and B. As used herein, “a bottom surface” refers to a surface facing the substrate102, and “a top surface” refers to a surface opposite the lower surface. The top surface may also be referred to as an upper surface, and the bottom surface may also be referred to as a lower surface.

In some embodiments, in each of the plurality of word lines WL, the first conductive plug122A may include, for example, an undoped conductive metal nitride. For instance, the first conductive plug122A may include, for example, an undoped titanium nitride (TiN) plug. As used herein, “an undoped element or layer” refers to an element or layer that does not include and thus is devoid of dopants intentionally added thereto. For example, an undoped element/layer of the first conductive plug122A may not include a metal dopant (e.g., lanthanum (La)) included in the work-function control conductive plug122B. In some embodiments, an undoped element/layer of the first conductive plug122A may be devoid of a metal dopant (e.g., lanthanum (La)) included in the work-function control conductive plug122B.

The first conductive plug122A may include a pair of sidewalls SW1, which are opposite to each other and are spaced apart from each other in the second lateral direction (e.g., Y direction) and are each in contact with the gate dielectric film120. The first conductive plug122A may have a structure that fills the word line trench WT between the pair of sidewalls SW1without being cut off in the second lateral direction (e.g., Y direction). In some embodiments, the first conductive plug122A may contact the pair of sidewalls SW1and may extend continuously between the pair of sidewalls SW1in the second lateral direction (e.g., Y direction), as illustrated inFIG.2D. As used herein, the sidewalls SW1of the first conductive plug122A may be referred to as first sidewalls. Among surfaces of the first conductive plug122A, surfaces other than a top surface contacting the bottom surface of the insulating capping pattern128may be in contact with the gate dielectric film120.

In some embodiments, in each of the plurality of word lines WL, the work-function control conductive plug122B may include a conductive metal nitride including a metal dopant. The conductive metal nitride may be doped with the metal dopant. For example, the work-function control conductive plug122B may include a TiN plug including lanthanum (La) as a dopant. A layer including a dopant may be formed by doping the layer with the dopant.

The work-function control conductive plug122B may have a pair of sidewalls SW0, which are opposite to each other and are spaced apart from each other in the second lateral direction (e.g., Y direction) and are each in contact with the gate dielectric film120. The work-function control conductive plug122B may have a structure that fills the word line trench WT between the pair of sidewalls SW0without being cut off in the second lateral direction (e.g., Y direction). In some embodiments, the work-function control conductive plug122B may contact the pair of sidewalls SW0and may extend continuously between the pair of sidewalls SW0in the second lateral direction (e.g., Y direction), as illustrated inFIG.2D. As used herein, the sidewalls SW0of the work-function control conductive plug122B may be referred to as upper sidewalls or upper portions of sidewalls.

In the IC device100shown inFIGS.2A to2D, the first conductive plug122A may be surrounded by (e.g., be contacted by) only the work-function control conductive plug122B and the gate dielectric film120. Stated differently, the work-function control conductive plug122B and the gate dielectric film120completely enclose the first conductive plug122A when viewed in cross-section. As shown inFIGS.2A and2C, a length of portions of the first conductive plug122A, which vertically overlap the plurality of active regions AC in the vertical direction (e.g., Z direction), may be shorter than a length of portions of the first conductive plug122A, which vertically overlap the device isolation film104in the vertical direction (e.g., Z direction). The top surface of the first conductive plug122A may extend planar without a step in the first lateral direction (e.g., X direction), and a bottom surface of the first conductive plug122A may extend in a concavo-convex shape in the first lateral direction (e.g., X direction).

A bottom surface of the work-function control conductive plug122B may be in contact with a single layer. As used herein, the single layer may refer to a single film or a single pattern entirely including (i.e., consisting of) one type of material and may be also referred to as a monolithic layer that includes only a single material. In the IC device100shown inFIGS.2A to2D, the bottom surface of the work-function control conductive plug122B may be in contact with only the first conductive plug122A including a conductive metal nitride film.

The sidewall SW1of the first conductive plug122A and the sidewall SW0of the work-function control conductive plug122B may extend along a single planar surface without a step in a portion adjacent to an interface between the first conductive plug122A and the work-function control conductive plug122B. Stated differently, the sidewall SW1of the first conductive plug122A and the sidewall SW0of the work-function control conductive plug122B may include respective portions adjacent to the interface between the first conductive plug122A and the work-function control conductive plug122B, and those portions are on the same plane as illustrated inFIG.2D. As shown inFIGS.2C and2D, the sidewall SW1of the first conductive plug122A and the sidewall SW0of the work-function control conductive plug122B may include a portion extending in a straight line passing through the interface between the first conductive plug122A and the work-function control conductive plug122B.

AlthoughFIGS.2A,2B, and2Cillustrate an example in which a length of the work-function control conductive plug122B in the vertical direction (e.g., Z direction) is less than a length of the first conductive plug122A in the vertical direction (e.g., Z direction) in one word line WL, the inventive concept is not limited thereto. For example, in one word line WL, the length of the work-function control conductive plug122B may be equal to or greater than the length of the first conductive plug122A in the vertical direction (e.g., Z direction). In one word line WL, the length of each of the first conductive plug122A and the work-function control conductive plug122B in the vertical direction (e.g., Z direction) may be variously adjusted as needed.

The insulating capping pattern128may fill the remaining space of the word line trench WT on the word line WL. In some embodiments, the insulating capping pattern128may include, for example, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or a combination thereof. In some embodiments, the insulating capping pattern128may include a silicon nitride film. In some other embodiments, the insulating capping pattern128may include, for example, a silicon oxide film and a silicon nitride film. The silicon oxide film may cover the top surface of the work-function control conductive plug122B and at least a portion of a surface of the gate dielectric film120. The silicon nitride film may fill an upper space of the word line trench WT on the silicon oxide film.

In the plurality of active regions AC, a plurality of source/drain regions SD may be on both sides of the plurality of word lines WL. Each of the plurality of source/drain regions SD may include an impurity region including impurity ions implanted into the substrate102. The sidewalls SW0of the work-function control conductive plug122B may respectively face a pair of source/drain regions SD, which are on both sides of the gate dielectric film120in the second lateral direction (e.g., Y direction).

In each of the plurality of word lines WL included in the IC device100, the first conductive plug122A may include, for example, an undoped TiN film, and the work-function control conductive plug122B may include, for example, a TiN film including lanthanum (La) as a dopant. In some embodiments, lanthanum (La) may be included at a content of, for example, about 0.01 atomic percent (at %) to about 10 at % in the work-function control conductive plug122B, without being limited thereto. A work function of the work-function control conductive plug122B may be lower than a work function of the first conductive plug122A. In some embodiments, the work function of the work-function control conductive plug122B may be lower than the work function of the first conductive plug122A by about 300 mV to about 500 mV, for example, about 400 mV to about 450 mV. Thus, each of the plurality of word lines WL may have a dual work function structure.

More specifically, when the first conductive plug122A includes an undoped TiN film and the work-function control conductive plug122B includes a TiN film including lanthanum (La) as a dopant, La atoms may be distributed in the TiN film in the work-function control conductive plug122B, and thus, a chemical bonding structure of the TiN film including the La atoms as a dopant may have a different structure from that of the undoped TiN film. Accordingly, a work function of the TiN film including the La atoms as a dopant may be different from a work function of the undoped TiN film. The work function of the TiN film including the La atoms as a dopant may be lower than the work function of the undoped TiN film. As a content ratio of La atoms in the TiN film including the La atoms as a dopant increases, the work function of the TiN film including the La atoms as a dopant may be further smaller.

As used herein, each of the work function of the work-function control conductive plug122B and the work function of the first conductive plug122A may refer to an effective work function. The effective work function may refer to a work function modified by the influence of a bonding interface between each of the work-function control conductive plug122B and the first conductive plug122A and a silicon oxide film in a structure in which each of the work-function control conductive plug122B and the first conductive plug122A is in contact with the silicon oxide film.

Each of the plurality of word lines WL may have a structure in which the work function of the work-function control conductive plug122B is lower than the work function of the first conductive plug122A, and thus, each of the plurality of word lines WL may have a dual work function structure. In addition, because the work-function control conductive plug122B having a relatively low work function is on the first conductive plug122A having a relatively high work function, the work-function control conductive plug122B having the relatively low work function may be more adjacent to the source/drain region SD than the first conductive plug122A. Accordingly, the word line WL may have a structure in which, as compared to the first conductive plug122A, the work-function control conductive plug122B has a greater area overlapping the source/drain region SD including an impurity region in a lateral direction (e.g., the first horizonal direction or the second horizontal direction). Therefore, a gate induced drain leakage (GIDL) current may decrease or may be prevented from increasing in the IC device100, and a reduction in data retention time may decrease or may be prevented, thereby improving refresh characteristics.

Furthermore, in each of the plurality of word lines WL included in the IC device100, the work-function control conductive plug122B having the relatively low work function may not have the liner structure located only in the local region adjacent to the gate dielectric film120in the second lateral direction (e.g., Y direction) but a plug structure extending over the entire width of the word line WL in the second lateral direction (e.g., Y direction). Thus, a volume occupied by the work-function control conductive plug122B having the relatively low work function in the work line WL may be increased. Therefore, in the IC device100, refresh characteristics may be further improved compared to a case in which the work-function control conductive plug122B has a liner structure located only in a local region adjacent to the gate dielectric film120.

Moreover, in each of the plurality of word lines WL included in the IC device100, because the first conductive plug122A has a relatively low resistivity and a relatively high work function, a resistance of the word line WL may be reduced, and a threshold voltage targeted by a transistor may be precisely controlled. Accordingly, the IC device100may ensure stable electrical characteristics.

In addition, each of the plurality of word lines WL included in the IC device100may include only a metal-containing structure and may not include a material (e.g., polysilicon) having a relatively high resistance. Therefore, a volume occupied by a metal in each of the plurality of word lines WL may be increased, and thus, resistances of the plurality of word lines WL may be reduced.

As shown inFIGS.2A to2C, the main surface102M of the substrate102, the device isolation film104, and the insulating capping pattern128may be covered by a buffer insulating film130. The buffer insulating film130may include, for example, an oxide film, a nitride film, or a combination thereof. As shown inFIG.2B, a plurality of direct contacts DC may be respectively on partial regions of the plurality of active regions AC. As shown inFIGS.2A and2B, a plurality of bit lines BL may extend longitudinally in the second lateral direction (e.g., Y direction) on the buffer insulating film130and the plurality of direct contacts DC. The plurality of bit lines BL may be covered by a plurality of insulating capping patterns138.

A plurality of conductive plugs140P and a plurality of insulating fences142may be alternately arranged one-by-one in a line in the second lateral direction (e.g., Y direction) between a pair of bit lines BL, which are adjacent to each other from among the plurality of bit lines BL. The plurality of insulating fences142may fill a plurality of recesses128R formed in the top surface of the insulating capping pattern128and may be respectively arranged one-by-one between the plurality of conductive plugs140P. In the second lateral direction (e.g., Y direction), both sidewalls of the plurality of conductive plugs140P may be respectively covered by the plurality of insulating fences142. The plurality of conductive plugs140P, which are arranged in a line in the second lateral direction (e.g., Y direction), may be insulated from each other by the plurality of insulating fences142. The plurality of conductive plugs140P may constitute the plurality of buried contacts BC shown inFIG.1.

Each of the plurality of bit lines BL may be connected to the active region AC through the direct contact DC. One direct contact DC and a pair of conductive plugs140P, which face each other with the one direct contact DC therebetween, may be connected to respectively different active regions AC, from among the plurality of active regions AC. In some embodiments, the direct contact DC may include, for example, silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or a combination thereof. For example, the direct contact DC may include an epitaxial silicon layer.

Each of the plurality of bit lines BL may include a lower conductive layer132, a middle conductive layer134, and an upper conductive layer136, which are sequentially formed on the substrate102. A top surface of the lower conductive layer132may extend coplanar with a top surface of the direct contact DC.FIGS.2A and2Billustrate an example in which each of the plurality of bit lines BL has a triple structure including the lower conductive layer132, the middle conductive layer134, and the upper conductive layer136, but the inventive concept is not limited thereto. For example, each of the plurality of bit lines BL may be formed as a single layer, a double layer, or a stacked structure of four or more layers. In some embodiments, the lower conductive layer132may include, for example, conductive polysilicon. Each of the middle conductive layer134and the upper conductive layer136may include, for example, titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten (W), tungsten silicide, or a combination thereof. For example, the middle conductive layer134may include TiN and/or TiSiN, and the upper conductive layer136may include W. The insulating capping pattern138may include a silicon nitride film.

Each of the plurality of conductive plugs140P may have a pillar shape that extends in the vertical direction (e.g., Z direction) along a space between the plurality of bit lines BL on the substrate102. A bottom surface of each of the plurality of conductive plugs140P may be in contact with the active region AC. A portion of each of the plurality of conductive plugs140P may be at a lower level than the main surface102M of the substrate102. The plurality of conductive plugs140P may include, for example, doped polysilicon, metal, conductive metal nitride, or a combination thereof.

Each of the plurality of insulating fences142may have a pillar shape extending in the vertical direction (e.g., Z direction) between two adjacent ones of the plurality of bit lines BL. The plurality of insulating fences142may include, for example, a silicon nitride film.

Both sidewalls of the plurality of bit lines BL, the plurality of insulating capping patterns138, and the plurality of direct contacts DC may be respectively covered by a plurality of insulating spacers146. The plurality of insulating spacers146may extend longitudinally parallel to the plurality of bit lines BL in the second lateral direction (e.g., Y direction) on the both sidewalls of the plurality of bit lines BL. The plurality of insulating spacers146may include, for example, an oxide film, a nitride film, air spacers, or a combination thereof. As used herein, the term “air” may refer to space including the atmosphere or other gases that may be in the atmosphere or during a manufacturing process.

Each of the plurality of conductive plugs140P may be spaced apart from the bit line BL in the first lateral direction (e.g., X direction) with the insulating spacer146therebetween. Each of the plurality of insulating fences142may be spaced apart from the bit line BL with the insulating spacer146therebetween in the first lateral direction (e.g., X direction).

A metal silicide film172and a conductive landing pad LP may be sequentially formed on the conductive plug140P. The metal silicide film172and the conductive landing pad LP may vertically overlap the conductive plug140P. Each of a plurality of metal silicide films172may be between the conductive plug140P and the conductive landing pad LP and be spaced apart from the bit line BL with the insulating spacer146therebetween. The metal silicide film172may include, for example, cobalt silicide, nickel silicide, or manganese silicide.

Each of a plurality of conductive landing pads LP may be connected to the conductive plug140P through the metal silicide film172. The plurality of conductive landing pads LP may extend from respective spaces between the plurality of insulating capping patterns138to respective upper spaces of the plurality of insulating capping patterns138to vertically overlap portions of the plurality of bit lines BL. Each of the plurality of conductive landing pads LP may include a conductive barrier film174and a conductive layer176. The conductive barrier film174may include, for example, titanium (Ti), titanium nitride (TiN), or a combination thereof. The conductive layer176may include, for example, a metal, a metal nitride, conductive polysilicon, or a combination thereof. For example, the conductive layer176may include tungsten (W).

The plurality of conductive landing pads LP may have a plurality of island-type pattern shapes in a view from above. The plurality of conductive landing pads LP may be electrically insulated from each other by an insulating film180filling insulating spaces180S, which are around the plurality of conductive landing pads LP. The insulating film180may include, for example, a silicon nitride film, a silicon oxide film, or a combination thereof.

In the IC device100shown inFIGS.2A to2D, each of the plurality of word lines WL may include only a metal-containing structure including the first conductive plug122A and the work-function control conductive plug122B and be configured to provide a dual work function. Accordingly, resistances of the plurality of word lines WL may be reduced, and an increase in GIDL current and a reduction in data retention time may decrease or may be prevented in the IC device100. Thus, refresh characteristics may be improved, and stable electrical characteristics may be ensured.

FIG.3is a cross-sectional view of an IC device200A according to some embodiments of the present inventive concept.FIG.3illustrates an enlarged cross-sectional configuration of a portion corresponding to region “EX1” ofFIG.2Cin the IC device200A. InFIG.3, the same reference numerals are used to denote the same elements as inFIGS.2A to2D, and repeated descriptions thereof are omitted.

Referring toFIG.3, the IC device200A may have the substantially same configuration as the IC device100described with reference toFIGS.1and2A to2D. However, the IC device200A may include a word line WL2A instead of a word line WL.

The word line WL2A may fill a lower space (also referred to as a lower portion), which is a portion of the word line trench WT, on the gate dielectric film120and extend longitudinally in a first lateral direction (e.g., X direction). The word line WL2A may include a work-function control conductive plug222B, a first conductive plug222A, and a second conductive plug234, which overlap each other in a vertical direction (e.g., Z direction). The second conductive plug234may be farther from the work-function control conductive plug222B than the first conductive plug222A.

The first conductive plug222A and the second conductive plug234may include different materials from each other. The first conductive plug222A may include, for example, an undoped conductive metal nitride, and the second conductive plug234may include a single metal. The work-function control conductive plug222B may include, for example, a conductive metal nitride including a metal dopant. In some embodiments, a work function of the metal included in the second conductive plug234may be higher than a work function of the conductive metal nitride included in the first conductive plug222A.

The first conductive plug222A and the work-function control conductive plug222B may substantially have the same configurations as the first conductive plug122A and the work-function control conductive plug122B, respectively, which have been described with reference toFIGS.2A,2C, and2D. However, the first conductive plug222A may be between the second conductive plug234and the work-function control conductive plug222B in the vertical direction (e.g., Z direction), and a bottom surface of the first conductive plug222A may be spaced apart from the gate dielectric film120in the vertical direction (e.g., Z direction) with the second conductive plug234therebetween. The bottom surface of the first conductive plug222A may be in contact with a single layer. The bottom surface of the first conductive plug222A may be in contact with a top surface of the second conductive plug234including a single metal. As used herein, “a single metal” may refer to a single metal layer or a monolithic metal layer including only one metallic material.

The work-function control conductive plug222B, the first conductive plug222A, and the second conductive plug234may be at different vertical distances from each other from the main surface102M of the substrate102. In the vertical direction (e.g., Z direction), a shortest distance from the main surface102M of the substrate102to the first conductive plug222A may be greater than a shortest distance from the main surface102M of the substrate102to the work-function control conductive plug222B, and a shortest distance from the main surface102M of the substrate102to the second conductive plug234may be greater than the shortest distance from the main surface102M of the substrate102to the first conductive plug222A. In a lateral direction (e.g., the first lateral direction (e.g., X direction) and a second lateral direction (e.g., Y direction)), the work-function control conductive plug222B, the first conductive plug222A, and the second conductive plug234may be arranged so as not to face each other.

The second conductive plug234may be spaced apart from the insulating capping pattern128in the vertical direction (e.g., Z direction) with the first conductive plug222A and the work-function control conductive plug222B therebetween. The second conductive plug234may be spaced apart from the work-function control conductive plug222B in the vertical direction (e.g., Z direction) with the first conductive plug222A therebetween.

The second conductive plug234may have a top surface in contact with the bottom surface of the first conductive plug222A. The second conductive plug234may have a pair of sidewalls SW22, which are opposite to each other and are spaced apart from each other in the second lateral direction (e.g., Y direction) and are each in contact with the gate dielectric film120. The second conductive plug234may have a structure that fills the word line trench WT between the pair of sidewalls SW22without being cut off in the second lateral direction (e.g., Y direction). In some embodiments, the second conductive plug234may contact the pair of sidewalls SW22and may extend continuously between the pair of sidewalls SW22in the second lateral direction (e.g., Y direction), as illustrated inFIG.3. As used herein, the top surface of the second conductive plug234may be referred to as a second top surface, and a sidewall of the second conductive plug234may be referred to as a second sidewall.

From among surfaces of the second conductive plug234, surfaces other than the top surface in contact with the bottom surface of the first conductive plug222A may be in contact with the gate dielectric film120. A bottom surface of the second conductive plug234may extend in a concavo-convex shape in the first lateral direction (e.g., X direction). In some embodiments, the second conductive plug234may include, for example, a molybdenum (Mo) plug.

In the IC device200A, a sidewall SW20of the work-function control conductive plug222B, a sidewall SW21of the first conductive plug222A, and the sidewall SW22of the second conductive plug234may extend along one planar surface without a step in each of a portion adjacent to an interface between the work-function control conductive plug222B and the first conductive plug222A and a portion adjacent to an interface between the first conductive plug222A and the second conductive plug234. In the word line WL2A, a length of each of the work-function control conductive plug222B, the first conductive plug222A, and the second conductive plug234in the vertical direction (e.g., Z direction) is not limited to that shown inFIG.3but may be variously adjusted as needed.

In some embodiments, the work-function control conductive plug222B may include, for example, TiN including lanthanum (La) as a dopant, the first conductive plug222A may include, for example, undoped TiN, and the second conductive plug234may include, for example, molybdenum (Mo). Molybdenum (Mo) may provide a higher work function than TiN. Because the word line WL2A includes the second conductive plug234including molybdenum (Mo), a resistance of the word line WL2A may be reduced, a threshold voltage targeted by a transistor may be precisely controlled, and the IC device200A may ensure stable electrical characteristics.

FIG.4is a cross-sectional view of an IC device200B according to some embodiments of the present inventive concept.FIG.4illustrates an enlarged cross-sectional configuration of a portion corresponding to region “EX1” ofFIG.2Cin the IC device200B. InFIG.4, the same reference numerals are used to denote the same elements as inFIGS.2A to2D and3, and repeated descriptions thereof are omitted.

Referring toFIG.4, the IC device200B may have the substantially same configuration as the IC device200A described with reference toFIG.3. However, the IC device200B may include a word line WL2B instead of the word line WL2A.

The word line WL2B may fill a lower space (also referred to as a lower portion), which is a portion of the word line trench WT, on the gate dielectric film120and extend longitudinally in a first lateral direction (e.g., X direction). The word line WL2B may include a work-function control conductive plug222B, a first conductive plug222A, a second conductive plug234B, and a third conductive plug236, which overlap each other in a vertical direction (e.g., Z direction).

In the IC device200B, the work-function control conductive plug222B, the first conductive plug222A, the second conductive plug234, and the third conductive plug236may be at different vertical distances from each other from a main surface102M of the substrate102. The first conductive plug222A, the second conductive plug234, and the third conductive plug236may be spaced apart from the insulating capping pattern128in the vertical direction (e.g., Z direction) with the work-function control conductive plug222B therebetween. The first conductive plug222A, the second conductive plug234, and the third conductive plug236may be at different vertical distances from each other from the insulating capping pattern128. In the vertical direction (e.g., Z direction), a shortest distance from the insulating capping pattern128to the second conductive plug234may be greater than a shortest distance from the insulating capping pattern128to the first conductive plug222A, and a shortest distance from the insulating capping pattern128to the third conductive plug236may be greater than the shortest distance from the insulating capping pattern128to the second conductive plug234. In a lateral direction (e.g., the first lateral direction (e.g., X direction) and a second lateral direction (e.g., Y direction)), the work-function control conductive plug222B, the first conductive plug222A, the second conductive plug234, and the third conductive plug236may be arranged so as not to face each other.

The first conductive plug222A and the work-function control conductive plug222B may have the same configurations as described with reference toFIG.3. The second conductive plug234B may have the substantially same configuration as the second conductive plug234described with reference toFIG.3. However, the first conductive plug222A may be between the second conductive plug234B and the work-function control conductive plug222B in the vertical direction (e.g., Z direction), and the first conductive plug222A may be spaced apart from the gate dielectric film120in the vertical direction (e.g., Z direction) with the second conductive plug234B and the third conductive plug236therebetween. The first conductive plug222A and the third conductive plug236may be spaced apart from each other in the vertical direction (e.g., Z direction) with the second conductive plug234B therebetween.

The second conductive plug234B may have a top surface in contact with the bottom surface of the first conductive plug222A and a bottom surface in contact with a top surface of the third conductive plug236. The bottom surface of the second conductive plug234B may be spaced apart from the gate dielectric film120in the vertical direction (e.g., Z direction) with the third conductive plug236therebetween. The bottom surface of the second conductive plug234B may be in contact with a single layer. The bottom surface of the second conductive plug234B may be in contact with the top surface of the third conductive plug236including a conductive metal nitride.

Each of the first conductive plug222A and the third conductive plug236may include, for example, an undoped conductive metal nitride. In some embodiments, the first conductive plug222A may include the same material as the third conductive plug236. In some embodiments, each of the first conductive plug222A and the third conductive plug236may include, for example, an undoped TiN plug.

The third conductive plug236may be spaced apart from the first conductive plug222A in the vertical direction (e.g., Z direction) with the second conductive plug234B therebetween, and the top surface of the third conductive plug236may be in contact with the bottom surface of the second conductive plug234B. The third conductive plug236may have a pair of sidewalls SW23, which are opposite to each other and are spaced apart from each other in the second lateral direction (e.g., Y direction) and are each in contact with the gate dielectric film120. The third conductive plug236may have a structure that fills the word line trench WT between the pair of sidewalls SW23without being cut off in the second lateral direction (e.g., Y direction). In some embodiments, the third conductive plug236may contact the pair of sidewalls SW23and may extend continuously between the pair of sidewalls SW23in the second lateral direction (e.g., Y direction), as illustrated inFIG.4As used herein, the top surface of the third conductive plug236may be referred to as a third top surface. From among surfaces of the third conductive plug236, surfaces other than the top surface in contact with the bottom surface of the second conductive plug234B may be in contact with the gate dielectric film120. A bottom surface of the third conductive plug236may extend in a concavo-convex shape in the first lateral direction (e.g., X direction).

In the IC device200B, a sidewall SW20of the work-function control conductive plug222B, a sidewall SW21of the first conductive plug222A, a sidewall SW22B of the second conductive plug234B, and the sidewall SW23of the third conductive plug236may extend along one planar surface without a step in each of a portion adjacent to an interface between the work-function control conductive plug222B and the first conductive plug222A, a portion adjacent to an interface between the first conductive plug222A and the second conductive plug234B, and a portion adjacent to an interface between the second conductive plug234B and the third conductive plug236. In the word line WL2B, a length of each of the work-function control conductive plug222B, the first conductive plug222A, the second conductive plug234B, and the third conductive plug236in the vertical direction (e.g., Z direction) is not limited to that shown inFIG.4and may be variously adjusted as needed.

In some embodiments, the work-function control conductive plug222B may include, for example, TiN including lanthanum (La) as a dopant, each of the first conductive plug222A and the third conductive plug236may include, for example, undoped TiN, and the second conductive plug234may include, for example, molybdenum (Mo). Molybdenum (Mo) may provide a higher work function than TiN. The word line WL2B may include the second conductive plug234including molybdenum (Mo) and the first conductive plug222A and the third conductive plug236, which are spaced apart from each other in the vertical direction (e.g., Z direction) with the second conductive plug234therebetween. Accordingly, a resistance of the word line WL2B may be reduced, a threshold voltage targeted by a transistor may be precisely controlled, and the IC device200B may ensure stable electrical characteristics.

FIG.5is a cross-sectional view of an IC device300according to some embodiments of the present inventive concept.FIG.5illustrates an enlarged cross-sectional configuration of a portion corresponding to region “EX1” ofFIG.2Cin the IC device300. InFIG.5, the same reference numerals are used to denote the same elements as inFIGS.2A to2D, and repeated descriptions thereof are omitted.

Referring toFIG.5, the IC device300may have the substantially same configuration as the IC device100described with reference toFIGS.1and2A to2D. The IC device300may have the same plan layout configuration as shown inFIG.1. However, the IC device300may include a gate dielectric film320, a word line WL3, and an insulating capping pattern128, which fill a word line trench WT.

The word line WL3may fill a lower space (also referred to as a lower portion), which is a portion of the word line trench WT, on the gate dielectric film320and extend longitudinally in a first lateral direction (e.g., X direction). The word line WL3may include only a work-function control conductive plug322. The work-function control conductive plug322may have a top surface in contact with a bottom surface of the insulating capping pattern128. From among surfaces of the work-function control conductive plug322, surfaces other than the top surface in contact with the bottom surface of the insulating capping pattern128may be in contact with the gate dielectric film320. In a second lateral direction (e.g., Y direction), a width of the work-function control conductive plug322may be less than a width of the insulating capping pattern128.

The work-function control conductive plug322may have a pair of sidewalls SW3, which are opposite to each other and are spaced apart from each other in the second lateral direction (e.g., Y direction) and are each in contact with the gate dielectric film320. The work-function control conductive plug322may have a structure that fills the word line trench WT between the pair of sidewalls SW23without being cut off in the second lateral direction (e.g., Y direction). In some embodiments, the work-function control conductive plug322may contact the pair of sidewalls SW23and may extend continuously between the pair of sidewalls SW23in the second lateral direction (e.g., Y direction), as illustrated inFIG.5. In some embodiments, the work-function control conductive plug322may include a TiN plug including lanthanum (La) as a dopant.

The gate dielectric film320may include a first portion320A in contact with the sidewall SW3of the work-function control conductive plug322and a second portion320B in contact with the insulating capping pattern128. In the second lateral direction (e.g., Y direction), a thickness TH1of the first portion320A of the gate dielectric film320may be greater than a thickness TH2of the second portion320B of the gate dielectric film320. In some embodiments, the first portion320A of the gate dielectric film320may include, for example, a combination of at least one selected from a titanium oxide film and a titanium lanthanum oxide film and a silicon oxide film, and the second portion320B of the gate dielectric film320may include, for example, a silicon oxide film. In the first portion320A of the gate dielectric film320, at least one selected from the titanium oxide film and the titanium lanthanum oxide film may be between the silicon oxide film and the work-function control conductive plug322.

FIG.6Ais a layout diagram of an IC device400according to some embodiments of the present inventive concept, andFIG.6Bis a cross-sectional view taken along lines X1-X1′ and Y1-Y1′ ofFIG.6A.

Referring toFIGS.6A and6B, the IC device400may include a substrate410, a plurality of first conductive lines420, a channel layer430, a gate electrode440, a gate insulating layer450, and a capacitor structure480. The IC device400may include a memory device including a vertical channel transistor (VCT). The VCT may refer to having a structure in which a channel length of the channel layer430extends in a vertical direction from the substrate410.

A lower insulating layer412may be on the substrate410, and the plurality of first conductive lines420may be spaced apart from each other in the first lateral direction (e.g., X direction) on the lower insulating layer412and extend longitudinally in a second lateral direction (e.g., Y direction). On the lower insulating layer412, a plurality of first insulating patterns422may fill spaces between the plurality of first conductive lines420. The plurality of first insulating patterns422may extend longitudinally in the second lateral direction (e.g., Y direction), and top surfaces of the plurality of first insulating patterns422may be at the same vertical level as top surfaces of the plurality of first conductive lines420. Each of the plurality of first conductive lines420may function as a bit line of the IC device400.

In some embodiments, the plurality of first conductive lines420may include, for example, doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the plurality of first conductive lines420may include doped polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), niobium nitride (NbN), titanium aluminide (TiAl), titanium aluminum nitride (TiAIN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tantalum silicon nitride (TaSiN), ruthenium titanium nitride (RuTiN), nickel silicide (NiSi), cobalt silicide (CoSi), iridium oxide (IrOx), ruthenium oxide (RuOx), or a combination thereof, without being limited thereto. Each of the plurality of first conductive lines420may include a single layer or a multilayered structure of the materials described above. In some embodiments, the plurality of first conductive lines420may include a two-dimensional (2D) semiconductor material. The 2D semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

Channel layers430may be arranged in a matrix form on the plurality of first conductive lines420and be spaced apart from each other in the first lateral direction (e.g., X direction) and the second lateral direction (e.g., Y direction). The channel layer430may have a first width in the first lateral direction (e.g., X direction) and a first height in the vertical direction (e.g., Z direction), and the first height may be greater than the first width. For example, the first height may be about twice to about 10 times the first width, without being limited thereto. A bottom portion of the channel layer430may function as a first source/drain region, an upper portion of the channel layer430may function as a second source/drain region, and a portion of the channel layer430between the first and second source/drain regions may function as a channel region.

In some embodiments, the channel layer430may include an oxide semiconductor. For example, the oxide semiconductor may include indium gallium zinc oxide (InGaZnO), indium gallium silicon oxide (InGaSiO), indium tin zinc oxide (InSnZnO), indium zinc oxide (InZnO), zinc oxide (ZnO), zinc tin oxide (ZnSnO), zinc oxynitride (ZnON), zirconium zinc tin oxide (ZrZnSnO), tin oxide (SnO), hafnium indium zinc oxide (HfInZnO), gallium zinc tin oxide (GaZnSnO), aluminum zinc tin oxide (AlZnSnO), YbGaZnO, InGaO, or a combination thereof. As used herein, the indication of each of materials listed above refers to a material including elements included therein, without referring to a chemical formula representing a stoichiometric relationship. The channel layer430may include a single layer or a multilayered structure of the oxide semiconductor. In some embodiments, the channel layer430may have a bandgap that is higher than the bandgap energy of silicon. For example, the channel layer430may have a bandgap energy of about 1.5 eV to about 5.6 eV. For example, the channel layer430may have an optimum channel performance when the channel layer430has a bandgap energy of about 2.0 eV to about 4.0 eV. For example, the channel layer430may be polycrystalline or amorphous, without being limited thereto. In some embodiments, the channel layer430may include a 2D semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

The gate electrode440may extend in the first lateral direction (e.g., X direction) on both sidewalls of the channel layer430. The gate electrode440may include a first sub-gate electrode440P1facing a first sidewall of the channel layer430and a second sub-gate electrode440P2facing a second sidewall that is opposite to the first sidewall of the channel layer430. Because one channel layer430is between the first sub-gate electrode440P1and the second sub-gate electrode440P2, the IC device400may have a dual-gate transistor structure. However, the inventive concept is not limited thereto. The second sub-gate electrode440P2may be omitted, and only the first sub-gate electrode440P1facing the first sidewall of the channel layer430may be formed to implement a single-gate transistor structure.

In some embodiments, similar to the word line WL described with reference toFIGS.2A to2D, the gate electrode440may include a work-function control conductive plug and a first conductive plug, which are sequentially stacked on the gate insulating layer450, the work-function control conductive plug may include, for example, TiN including lanthanum (La) as a dopant, and the first conductive plug may include undoped TiN.

In some other embodiments, similar to the word line WL2A described with reference toFIG.3, the gate electrode440may include a work-function control conductive plug, a first conductive plug, and a second conductive plug, which are sequentially stacked on the gate insulating layer450, the work-function control conductive plug may include, for example, TiN including lanthanum (La) as a dopant, the first conductive plug may include, for example, undoped TiN, and the second conductive plug may include, for example, molybdenum (Mo).

In still some other embodiments, similar to the word line WL2B described with reference toFIG.4, the gate electrode440may include a work-function control conductive plug, a first conductive plug, a second conductive plug, and a third conductive plug, which are sequentially stacked on the gate insulating layer450, the work-function control conductive plug may include, for example, TiN including lanthanum (La) as a dopant, each of the first conductive plug and the third conductive plug may include, for example, undoped TiN, and the second conductive plug may include, for example, molybdenum (Mo).

In yet some other embodiments, similar to the word line WL3described with reference toFIG.5, the gate electrode440may include a work-function control conductive plug stacked on the gate insulating layer450, and the work-function control conductive plug may include, for example, TiN including lanthanum (La) as a dopant.

The gate insulating layer450may surround a sidewall of the channel layer430and be between the channel layer430and the gate electrode440. For example, as shown inFIG.6B, the entire sidewall of the channel layer430may be surrounded by the gate insulating layer450, and a portion of a sidewall of the gate electrode440may be in contact with the gate insulating layer450. In some other embodiments, the gate insulating layer450may extend in the first lateral direction (e.g., X direction), which is a direction in which the gate electrode440extends longitudinally. From among sidewalls of the channel layer430, only two sidewalls facing the gate electrode440may be in contact with the gate insulating layer450.

In some embodiments, the gate insulating layer450may include, for example, a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high-k dielectric film may include, for example, a metal oxide or a metal oxynitride. For example, the high-k dielectric film that may be used as the gate insulating layer450may include HfO2, HfSiO, HfSiON, HfTaO, HfTIO, HfZrO, ZrO2, Al2O3, or a combination thereof, without being limited thereto.

A plurality of second insulating patterns432may extend in the second lateral direction (e.g., Y direction) on the plurality of first insulating patterns422, and the channel layer430may be between two adjacent ones of the plurality of second insulating patterns432. In addition, between two adjacent second insulating patterns432, a first buried layer434and a second buried layer436may be in a space between two adjacent channel layers430. The first buried layer434may be in a bottom portion of a space between the two adjacent channel layers430, and the second buried layer436may be formed to fill the remaining portion of the space between the two adjacent channel layers430on the first buried layer434. A top surface of the second buried layer436may be at the same level as a top surface of the channel layer430, and the second buried layer436may cover a top surface of the gate electrode440. In some other embodiments, the plurality of second insulating patterns432may include a material layer that is continuous with the plurality of first insulating patterns422. In some embodiments, the second buried layer436may include a material layer that is continuous with the first buried layer434.

A capacitor contact460may be on the channel layer430. The capacitor contact460may vertically overlap the channel layer430. Capacitor contacts460may be arranged in a matrix form and be spaced apart from each other in the first lateral direction (e.g., X direction) and the second lateral direction (e.g., Y direction). The capacitor contact460may include, for example, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAIN, TiSi, TİSİN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO, RuO, or a combination thereof, without being limited thereto. An upper insulating layer462may surround sidewalls of the capacitor contact460on the plurality of second insulating patterns432and the second buried layer436.

An etching stop film470may be on the upper insulating layer462, and a capacitor structure480may be on the etching stop film470. The capacitor structure480may include a lower electrode482, a capacitor dielectric layer484, and an upper electrode486.

The lower electrode482may pass through the etching stop film470and be electrically connected to a top surface of the capacitor contact460. The lower electrode482may be formed as a pillar type extending in the vertical direction (e.g., Z direction), without being limited thereto. In some embodiments, the lower electrode482may vertically overlap the capacitor contact460. Lower electrodes482may be arranged in a matrix form and be spaced apart from each other in the first lateral direction (e.g., X direction) and the second lateral direction (e.g., Y direction). In some other embodiments, a landing pad (not shown) may be further located between the capacitor contact460and the lower electrode482, and thus, the lower electrode482may be arranged in a hexagonal shape.

FIG.7Ais a layout diagram of an IC device400A according to some embodiments of the present inventive concept, andFIG.7Bis a perspective view of the IC device400A shown inFIG.7A.

Referring toFIGS.7A and7B, the IC device400A may include a substrate410A, a plurality of first conductive lines420A, a channel structure430A, a contact gate electrode440A, a plurality of second conductive lines442A, and a capacitor structure480. The IC device400A may include a memory device including a VCT.

A plurality of active regions AC may be formed in the substrate410A and defined by a first device isolation film412A and a second device isolation film414A. The channel structure430A may be in each of the active regions AC. The channel structure430A may include a first active pillar430A1and a second active pillar430A2, which extend in a vertical direction, and a connection430L, which is connected to the bottom of the first active pillar430A1and the bottom of the second active pillar430A2. A first source/drain region SD1may be in the connection430L, a second source/drain region SD2may be in an upper portion of each of the first and second active pillars430A1and430A2. Each of the first active pillar430A1and the second active pillar430A2may constitute an independent unit memory cell.

The plurality of first conductive lines420A may extend longitudinally in a direction intersecting with each of the plurality of active regions AC. For example, the plurality of first conductive lines420A may extend longitudinally in a second lateral direction (e.g., Y direction). From among the plurality of first conductive lines420A, one first conductive line420A may be on the connection430L between the first active pillar430A1and the second active pillar430A2and be located on the first source/drain region SD1. Another first conductive line420A, which is adjacent to the one first conductive line420A, may be between two channel structures430A. From among the plurality of first conductive lines420A, one first conductive line420A may function as a common bit line included in two unit memory cells that include the first active pillar430A1and the second active pillar430A2, which are on both sides of the one first conductive line420A.

One contact gate electrode440A may be between two channel structures430A, which are adjacent to each other in the second lateral direction (e.g., Y direction). For instance, the contact gate electrode440A may be between the first active pillar430A1of one channel structure430A and the second active pillar430A2of another channel structure430A adjacent thereto. One contact gate electrode440may be shared between the first active pillar430A1and the second active pillar430A2on both sidewalls thereof. A gate insulating layer450A may be between the contact gate electrode440A and the first active pillar430A1and between the contact gate electrode440A and the second active pillar430A2. The plurality of second conductive lines442A may extend in a first lateral direction (e.g., X direction) on a top surface of the contact gate electrode440A. Each of the plurality of second conductive lines442A may function as a word line of the IC device400A.

In some embodiments, similar to the word line WL described with reference toFIGS.2A to2D, the contact gate electrode440A may include a work-function control conductive plug and a first conductive plug, which are sequentially stacked on the gate insulating layer450A, the work-function control conductive plug may include, for example, TiN including lanthanum (La) as a dopant, and the first conductive plug may include undoped TiN.

In some other embodiments, similar to the word line WL2A described with reference toFIG.3, the contact gate electrode440A may include a work-function control conductive plug, a first conductive plug, and a second conductive plug, which are sequentially stacked on the gate insulating layer450A, the work-function control conductive plug may include, for example, TiN including lanthanum (La) as a dopant, the first conductive plug may include, for example, undoped TiN, and the second conductive plug may include, for example, molybdenum (Mo).

In still some other embodiments, similar to the word line WL2B described with reference toFIG.4, the contact gate electrode440A may include a work-function control conductive plug, a first conductive plug, a second conductive plug, and a third conductive plug, which are sequentially stacked on the gate insulating layer450A, the work-function control conductive plug may include, for example, TiN including lanthanum (La) as a dopant, each of the first conductive plug and the third conductive plug may include, for example, undoped TiN, and the second conductive plug may include, for example, molybdenum (Mo).

In yet some other embodiments, similar to the word line WL3described with reference toFIG.5, the contact gate electrode440A may include a work-function control conductive plug stacked on the gate insulating layer450A, and the work-function control conductive plug may include, for example, TiN including lanthanum (La) as a dopant.

A capacitor contact460A may be on the channel structure430A. The capacitor contact460A may be on the second source/drain region SD2, and the capacitor structure480may be on the capacitor contact460A.

FIGS.8A through16Bare cross-sectional views illustrating a method of manufacturing an IC device, according to some embodiments of the present inventive concept. In some embodiments, processes may be sequentially performed as illustrated inFIGS.8A through16B.FIGS.8A,9A,10A,11A,12A,13A,14A,15A and16Aare cross-sectional views taken along line X1-X1′ ofFIG.1, andFIGS.8B,9B,10B,11B,12B,13B,14B,15B and16Bare cross-sectional views taken along line Y1-Y1′ ofFIG.1. An example method of manufacturing the IC device100shown inFIGS.1and2A to2Dis described with reference toFIGS.8A to16B.

Referring toFIGS.8A and8B, a mask pattern M1may be formed on a main surface102M of a substrate102, and the substrate102may be etched by using the mask pattern M1as an etch mask, and thus, a device isolation trench104T may be formed in the substrate102. A plurality of active regions AC may be defined by the device isolation trench104T in the substrate102. The mask pattern M1may include, for example, a hard mask including an oxide film, polysilicon, or a combination thereof.

Referring toFIGS.9A and9B, the mask pattern M1may be removed from the resultant structure ofFIGS.8A and8B. Thereafter, an insulating film P104may be formed to fill the device isolation trench104T and cover a main surface102M of the substrate102, and an ion implantation process for forming a plurality of source/drain regions SD in the substrate102may be performed. A portion of the insulating film P104, which fills the device isolation trench104T, may serve as a device isolation film104. A portion of the insulating film P104, which covers the main surface102M of the substrate102, may protect the main surface102M of the substrate102during the ion implantation process for forming the plurality of source/drain regions SD or subsequent processes (e.g., an etching process).

Referring toFIGS.10A and10B, a mask pattern M2may be formed on the resultant structure ofFIGS.9A and9B, and a portion of the insulating film P104and a portion of the substrate102may be etched by using the mask pattern M2as an etch mask. Thus, a plurality of word line trenches WT extending longitudinally in a first lateral direction (e.g., X direction) may be formed to intersect with the plurality of active regions AC and the device isolation film104. Each of the plurality of word line trenches WT may include a first trench portion TIA and a second trench portion T1B. The first trench portion TIA may have a bottom surface exposing the substrate102at a first vertical level LV1. The second trench portion T1B may have a bottom surface exposing the device isolation film104at a second vertical level LV2. Here, the second vertical level LV2may be lower than the first vertical level LV1. The mask pattern M2may include, for example, an oxide film, an amorphous carbon layer (ACL), a silicon oxynitride (SiON) film, or a combination thereof.

To form the plurality of word line trenches WT, a first etching process and a second etching process may be sequentially performed on the main surface102M of the substrate102. The first etching process may include etching the substrate102and the device isolation film104under a condition that the substrate102and the device isolation film104are etched at substantially the same etch rate. The second etching process may include etching the substrate102and the device isolation film104under a condition that an etch rate of the device isolation film104is etched at a higher etch rate than the substrate102. As a result, the second vertical level LV2of the bottom surface of the second trench portion T1B exposing the device isolation film104may be lower than first vertical level LV1of the bottom surface of the first trench portion TA exposing the substrate102. The first trench portion TIA and the second trench portion T1B may have substantially the same width or substantially similar widths in the second lateral direction (e.g., Y direction).

The plurality of active regions AC may include a plurality of fin areas AF, which protrude upward in the vertical direction (e.g., Z direction) from the second vertical level LV2to the first vertical level LV1inside the plurality of word line trenches WT, respectively.

Referring toFIGS.11A and11B, a gate dielectric film120may be formed on the resultant structure ofFIGS.10A and10B. The gate dielectric film120may be formed to conformally cover an inner wall of each of the plurality of word line trenches WT. The gate dielectric film120may include, for example, a silicon oxide film.

The gate dielectric film120may be formed by using, for example, an atomic layer deposition (ALD) process. In some embodiments, the process of forming the gate dielectric film120may be performed in a plasma atmosphere by using O2gas and inert gas. In some other embodiments, the process of forming the gate dielectric film120may be performed in a plasma atmosphere by using O2gas, inert gas, and H2gas. In still some other embodiments, during the formation of the gate dielectric film120, an in-situ steam generation (ISSG) process using vapor or a combination of H2gas and O2gas may be performed.

Referring toFIGS.12A and12B, a plurality of conductive metal nitride films122may be formed on the gate dielectric film120to fill portions (e.g., lower spaces) of the plurality of word line trenches WT, respectively. The plurality of conductive metal nitride films122may include, for example, TiN.

In some embodiments, to form the plurality of conductive metal nitride films122, a conductive metal nitride may be deposited to such a sufficient thickness as to fill the plurality of word line trenches WT on the resultant structure ofFIGS.11A and11B. Thereafter, a portion of the conductive metal nitride may be etched back, and thus, the conductive metal nitride film122may be left in the lower space of each of the plurality of word line trenches WT. After the plurality of conductive metal nitride films122are formed, an upper space of each of the plurality of word line trenches WT may be emptied.

Referring toFIGS.13A and13B, a protective liner192may be formed to cover the gate dielectric film120, which is exposed on the conductive metal nitride film122inside each of the plurality of word line trenches WT.

The protective liner192may be formed to conformally cover not only a surface of the gate dielectric film120but also a top surface of the conductive metal nitride film122. The protective liner192may protect the gate dielectric film120from being damaged during a subsequent process of forming a work-function control conductive plug122B. In some embodiments, the protective liner192may include, for example, a TiN film, a silicon oxide film, a silicon nitride film, or a combination thereof.

In some embodiments, to form the protective liner192, a protective film may be formed to conformally cover exposed surfaces in the resultant structure ofFIGS.12A and12B. Thereafter, a portion of the protective film may be removed, and thus, the protective liner192may remain inside each of the plurality of word line trenches WT. After the protective liner192is formed, a space may remain on the protective liner192inside each of the plurality of word line trenches WT.

Referring toFIGS.14A and14B, while the gate dielectric film120is being covered by the protective liner192on the conductive metal nitride film122, a metal oxide film194may be formed on the protective liner192.

To form the metal oxide film194, a metal oxide may be blanket-deposited on the resultant structure ofFIGS.13A and13B. Thereafter, a portion of the metal oxide may be removed, and thus, the metal oxide film194may remain over the conductive metal nitride film122inside each of the plurality of word line trenches WT. The metal oxide film194may be spaced apart from Each the conductive metal nitride film122and the gate dielectric film120with the protective liner192therebetween. The metal oxide film194may include, for example, a lanthanum oxide film.

Thereafter, the resultant structure including the metal oxide film194may be annealed, and thus, metal atoms may diffuse from the metal oxide film194into the conductive metal nitride film122. As a result, an upper portion of the conductive metal nitride film122may be converted into a work-function control conductive plug122B. The work-function control conductive plug122B may include a conductive metal nitride including a metal dopant. For example, the work-function control conductive plug122B may include TiN including lanthanum (La) as a dopant. After the work-function control conductive plug122B is formed, the remaining portion of the conductive metal nitride film122may be left as a first conductive plug122A. The first conductive plug122A may include, for example, undoped TiN.

The annealing process may be performed at a temperature of, for example, about 400° C. to about 950° C., without being limited thereto. In some other embodiments, the annealing process may be omitted. In this case, metal atoms may diffuse from the metal oxide film194into the conductive metal nitride film122due to a process atmosphere during or after the formation of the metal oxide film194without an additional annealing process, and thus, the work-function control conductive plug122B may be obtained. Because the gate dielectric film120is covered by the protective liner192on the conductive metal nitride film122, there may be no concern that the gate dielectric film120is adversely affected by metal atoms diffused from the metal oxide film194during the formation of the work-function control conductive plug122B.

Referring toFIGS.15A and15B, the metal oxide film194and the protective liner192may be removed from the resultant structure ofFIGS.14A and14Bin which the work-function control conductive plug122B is formed, and thus, a top surface of the work-function control conductive plug122B and the gate dielectric film120may be exposed.

In some embodiments, the metal oxide film194and the protective liner192may be completely removed from the resultant structure ofFIGS.14A and14B. As a result, inside the word line trench WT, the entire region of the top surface of the work-function control conductive plug122B and the surface of the dielectric film120at a higher vertical level than the top surface of the work-function control conductive plug122B, and residue of the protective liner192may not remain on each of the top surface of the work-function control conductive plug122B and the surface of the gate dielectric film120.

In some other embodiments, differently from that illustrated inFIGS.15A and15B, although the metal oxide film194is completely removed from the resultant structure ofFIGS.14A and14B, a portion of the protective liner192may remain. In this case, the residue of the protective liner192remaining on at least one of the top surface of the work-function control conductive plug122B and the surface of the gate dielectric film120may constitute a portion of an insulating capping pattern (refer to128inFIGS.16A and16B) that is formed in a subsequent process.

Referring toFIGS.16A and16B, in the resultant structure ofFIGS.15A and15B, the insulating capping pattern128may be formed to fill the upper space of each of the plurality of word line trenches WT. Thereafter, films formed on the substrate102may be removed to expose the main surface102M of the substrate102.

In some embodiments, to form the insulating capping pattern128, the upper space of each of the plurality of word line trenches WT may be filled by a silicon nitride film. As in the resultant structure ofFIGS.15A and15B, when the metal oxide film194and the protective liner192are completely removed and the residue of the protective liner192does not remain on each of the top surface of the work-function control conductive plug122B and the surface of the gate dielectric film120, the insulating capping pattern128may include, for example, a silicon nitride film.

In some other embodiments, differently from those illustrated inFIGS.15A and15B, after the processes described with reference toFIGS.15A and15Bare performed, when the residue of the protective liner192remains on at least one of the top surface of the work-function control conductive plug122B and the surface of the gate dielectric film120inside the word line trench WT, the upper space of each of the plurality of word line trenches WT may be filled by a silicon nitride film to form the insulating capping pattern128. Thus, the insulating capping pattern128including the residue of the protective liner192and the silicon nitride film may be obtained. When the protective liner192includes a silicon oxide film, the insulating capping pattern128may include a silicon oxide film and a silicon nitride film. The silicon oxide film may cover at least a portion of the top surface of the work-function control conductive plug122B and the top surface of the gate dielectric film120. The silicon nitride film may fill the upper space of the word line trench WT on the silicon oxide film.

Although the processes described with reference toFIGS.12A to16Bpertain to a case in which a process of forming a plurality of word lines WL is performed in a state in which the mask pattern M2remains on the substrate102, when necessary, a subsequent process may be performed after the mask pattern M2is removed in any one of the processes described with reference toFIGS.12A to16B.

Afterwards, a buffer insulating film130, a plurality of direct contacts DC, a plurality of bit lines BL, a plurality of insulating spacers146, an insulating fence142, a plurality of conductive plugs140P, a metal silicide film172, a conductive landing pad LP, and an insulating film180may be formed on the substrate102, and thus, the IC device100having the configuration shown inFIGS.2A to2Dmay be manufactured.

FIGS.17A and17Bare cross-sectional views illustrating a method of manufacturing an IC device according to some embodiments of the present inventive concept.FIG.17Aillustrates a cross-sectional configuration of portions corresponding to a cross-section taken along line X1-X1′ ofFIG.1.FIG.17Billustrates a cross-sectional configuration of portions corresponding to a cross-section taken along line Y1-Y1′ ofFIG.1. Another example method of manufacturing the IC device100shown inFIGS.1and2A to2Dis described with reference toFIGS.17A and17B.

Referring toFIGS.17A and17B, the processes described with reference toFIGS.8A to12Bmay be performed. Thereafter, a metal oxide film194A covering a top surface of a conductive metal nitride film122may be formed inside each of the plurality of word line trenches WT. To form the metal oxide film194A, a metal oxide may be blanket-deposited on the resultant structure ofFIGS.13A and13B. Thereafter, a portion of the metal oxide may be removed, and thus, the metal oxide film194A may remain over the conductive metal nitride film122inside each of the plurality of word line trenches WT. The metal oxide film194A may be formed to contact the top surface of the conductive metal nitride film122. The metal oxide film194A may include a lanthanum oxide film.

Afterwards, a protective liner196may be formed to cover a top surface of the metal oxide film194A. The protective liner196may include, for example, TiN, a silicon oxide film, a silicon nitride film, or a combination thereof.

In some embodiments, to form the protective liner196, a protective film may be formed to conformally cover exposed surfaces in the resultant structure including the metal oxide film194A. Thereafter, a portion of the protective film may be removed, and thus, the protective liner196may remain inside each of the plurality of word line trenches WT. After the protective liner196is formed, a space may remain on the protective liner196inside each of the plurality of word line trenches WT. The protective liner196may reduce or prevent outgassing of conductive elements included in the work-function control conductive plug122B after a work-function control conductive plug122B is formed in a subsequent process.

The resultant structure including the protective liner196may be annealed in a similar manner to that described with reference toFIGS.14A and14B, and thus, metal atoms may diffuse from the metal oxide film194A into the conductive metal nitride film122. As a result, the work-function control conductive plug122B may be obtained from an upper portion of the conductive metal nitride film122. After the work-function control conductive plug122B is formed, the remaining portion of the conductive metal nitride film122may be left as the first conductive plug122A. The annealing process may be omitted. In this case, metal atoms may diffuse from the metal oxide film194A into the conductive metal nitride film122due to a process atmosphere during or after the formation of the metal oxide film194A and the protective liner196without an additional annealing process, and thus, the work-function control conductive plug122B may be obtained.

Thereafter, the metal oxide film194A and the protective liner196remaining on the resultant structure including the work-function control conductive plug122B may be removed in a similar manner to that described with reference toFIGS.15A and15B, and the processes described with reference toFIGS.16A and16Bmay be performed. Thus, the IC device100having the configuration illustrated inFIGS.2A to2Dmay be manufactured.

The processes described with reference toFIGS.8A to12Bmay be performed to manufacture the IC device200A described with reference toFIG.3. However, before the process of forming the plurality of conductive metal nitride films122is performed in the processes described with reference toFIGS.12A and12B, a second conductive plug234may be formed on a portion of the gate dielectric film120, which is adjacent to a bottom surface of each of the plurality of word line trenches WT. The second conductive plug234may include a single metal. In some embodiments, the second conductive plug234may include, for example, molybdenum (Mo).

In some embodiments, to form the second conductive plug234, a Mo film may be formed on the gate dielectric film120in the resultant structure ofFIGS.11A and11B, and a portion of the Mo film may be removed. Thus, the second conductive plug234may remain on the portion of the gate dielectric film120, which is adjacent to the bottom surface of the word line trench WT.

Thereafter, processes similar to those described with reference toFIGS.13A to16Bor processes similar to those described with reference toFIGS.17A and17Bmay be performed on the resultant structure including the second conductive plug234, and thus, the IC device200A shown inFIG.3may be manufactured.

The processes described with reference toFIGS.8A to16Bmay be performed to manufacture the IC device200B described with reference toFIG.4. However, before the process of forming the plurality of conductive metal nitride films122is performed in the process described with reference toFIGS.12A and12B, a third conductive plug236and a second conductive plug234B may be sequentially formed on a portion of the gate dielectric film120, which is adjacent to the bottom surface of each of the plurality of word line trenches WT. The third conductive plug236may include, for example, an undoped conductive metal nitride, and the second conductive plug234B may include a single metal. For example, the third conductive plug236may include, for example, undoped TiN, and the second conductive plug234B may include, for example, molybdenum (Mo).

In some embodiments, to form the third conductive plug236, a TiN film may be formed on the gate dielectric film120in the resultant structure ofFIGS.11A and11B, and a portion of the TiN film may be removed. Thus, the third conductive plug236may remain on the portion of the gate dielectric film120, which is adjacent to the word line trench WT.

In some embodiments, to form the second conductive plug234B, a Mo film may be formed on the resultant structure including the third conductive plug236, and a portion of the Mo film may be removed. Thus, the second conductive plug234B may remain on the third conductive plug236inside the word line trench WT.

Thereafter, processes similar to those described with reference toFIGS.13A to16Bor processes similar to those described with reference toFIGS.17A and17Bmay be performed on the resultant structure including the second conductive plug234B, and thus, the IC device200B shown inFIG.4may be manufactured.

FIGS.18A and18Bare cross-sectional views illustrating a method of manufacturing an IC device, according to some embodiments of the present inventive concept.FIG.18Aillustrates a cross-sectional configuration of portions corresponding to a cross-section taken along line X1-X1′ ofFIG.1.FIG.18Billustrates a cross-sectional configuration of portions corresponding to a cross-section taken along line Y1-Y1′ ofFIG.1. An example method of manufacturing the IC device300shown inFIG.5is described with reference toFIGS.18A and18B.

Referring toFIGS.18A and18B, processes up to forming a gate dielectric film120may be performed as described with reference toFIGS.8A to11B. Thereafter, as described with reference toFIGS.12A and12B, a process of forming a plurality of conductive metal nitride films122may be performed. However, in the present embodiment, a metal oxide film394may be further formed between the gate dielectric film120and the conductive metal nitride film122inside each of the plurality of word line trenches WT. In some embodiments, the metal oxide film394may include, for example, a lanthanum oxide film.

As shown inFIGS.18A and18B, to form a structure in which the metal oxide film394and the conductive metal nitride film122are sequentially stacked on the gate dielectric film120inside each of the plurality of word line trenches WT, initially, a lanthanum oxide film may be formed by using, for example, an ALD process to conformally cover exposed surfaces in the resultant structure ofFIGS.11A and11B. Next, a TiN film may be formed to fill remaining spaces on the lanthanum oxide film inside the plurality of word line trenches WT. Thereafter, a portion of each of the TiN film and the lanthanum oxide film may be removed to obtain the resultant structure shown inFIGS.18A and18B.

Afterwards, the obtained resultant structure may be annealed in a similar manner to that described with reference toFIGS.14A and14B, and thus, metal atoms may diffuse from the metal oxide film394into the conductive metal nitride film122. As a result, as shown inFIG.5, the work-function control conductive plug322including a conductive metal nitride including a metal dopant as a dopant may be obtained from the conductive metal nitride film122.

After the metal atoms diffuse from the metal oxide film394into the conductive metal nitride film122, oxygen atoms remaining in the metal oxide film394may be converted into a form of an oxide (e.g., titanium oxide, lanthanum oxide, and/or silicon oxide). Portions of the gate dielectric film120in contact with the metal oxide film394may increase in thickness due to the oxide. As a result, a gate dielectric film320including a first portion320A having a relatively thick thickness may be obtained as described above with reference toFIG.5. A portion of the gate dielectric film120at a higher vertical level than the metal oxide film394may be maintained at a relatively thin original thickness. The portion of the gate dielectric film120may remain as the second portion320B of the gate dielectric film320shown inFIG.5.

As shown inFIGS.18A and18B, the above-described embodiment pertains to an example in which the structure in which the metal oxide film394and the conductive metal nitride film122are sequentially stacked on the gate dielectric film120inside each of the plurality of word line trenches WT may be first formed, and the metal atoms may diffuse from the metal oxide film394into the conductive metal nitride film122by using an annealing process, but the inventive concept is not limited thereto. For example, the annealing process may be omitted, and metal atoms may diffuse from the metal oxide film394into the conductive metal nitride film122during the formation of the metal oxide film394and the conductive metal nitride film122.

In some other embodiments, differently from that described above, a lanthanum oxide film may be formed to conformally cover exposed surfaces in the resultant structure ofFIGS.11A and11B, and a TiN film may be formed to fill remaining spaces of the plurality of word line trenches WT on the lanthanum oxide film. Thereafter, an annealing process may be performed as needed, and thus, metal atoms may diffuse from the metal oxide film394into the conductive metal nitride film122. Subsequently, a portion of the obtained resultant structure may be removed to form the work-function control conductive plug322shown inFIG.5. In this case, a gate dielectric film having a substantially constant width in the second lateral direction (e.g., Y direction) may be obtained in the vertical direction (e.g., Z direction) instead of the gate dielectric film320shown inFIG.5.

Although example methods of manufacturing the IC devices100,200A,200B, and300shown inFIGS.1to5have been described with reference toFIGS.8A to18B, the inventive concept is not limited thereto. It will be understood that IC devices having various structures may be manufactured by applying various modifications and changes to the IC devices100,200A.200B, and300shown inFIGS.1to5within the scope of the inventive concept.

As used herein, an element or region that is “covering” or “surrounding” or “filling” another element or region may completely or partially cover or surround or fill the other element or region.

Although terms (e.g., first, second or third) may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and, similarly a second element may be referred to as a first element without departing from the teachings of the disclosure.

While the inventive concept has been shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims. The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the present inventive concept. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.