METHOD FOR MANUFACTURING TRENCH MOSFET

A method for manufacturing a trench MOSFET includes: forming a trench extending from an upper surface of an epitaxial layer of a first dopant type into the epitaxial layer; forming a gate dielectric layer and a gate conductor located in the trench; forming a body region of a second dopant type located in the epitaxial layer, where the body region is adjacent to the trench; forming a source region of the first dopant type located in the body region; forming a first dielectric layer on the source region and the gate dielectric layer; forming a contact hole extending through the first dielectric layer and the source region and extending into the body region; forming a spacer on a side wall of the contact hole; forming a body contact region of the second dopant type through the contact hole; and forming a conductive channel filling the contact hole.

TECHNICAL FIELD

This application relates to the technical field of semiconductors, and in particular, to a method for manufacturing a trench metal oxide semiconductor field effect transistor (MOSFET).

BACKGROUND

A trench metal oxide semiconductor field effect transistor (MOSFET) device is widely used in the field of power electronics due to advantages such as a high input impedance, a small driving current, a fast switching speed, and high temperature characteristics.

In a general trench MOSFET device, an on resistance of the device is reduced by continuously reducing a size of the device, and the reduction of the size of the device leads to a corresponding decrease in a size of a body region. Therefore, a contact region formed in the body region laterally intrudes into a trench region adjacent to the trench, and the performance of the device is affected.

SUMMARY

The present application provides a method for manufacturing a trench MOSFET. A contact hole is formed before a contact region is formed, and a spacer is formed in the contact hole. The spacer of a side wall of the contact hole can prevent the contact region from laterally invading a trench region, thereby ensuring the reliability of performance of a device.

The present application provides a method for manufacturing a trench MOSFET, including:forming a trench extending from an upper surface of an epitaxial layer of a first dopant type into the epitaxial layer;forming a gate dielectric layer and a gate conductor located in the trench, where the gate dielectric layer covers an inner surface of the trench and isolates the gate conductor from the epitaxial layer;forming a body region of a second dopant type located in the epitaxial layer, where the body region is adjacent to the trench;forming a source region of the first dopant type located in the body region;forming a first dielectric layer on the source region and the gate dielectric layer;forming a contact hole extending through the first dielectric layer and the source region and extending into the body region;forming a spacer on a side wall of the contact hole;forming a body contact region of the second dopant type through the contact hole; andforming a conductive channel filling the contact hole.

DETAILED DESCRIPTION

In each of the following accompanying drawings, same elements are represented by using similar reference numerals. For clarity, each part in the accompanying drawings is not drawn to scale. In addition, certain known parts may not be shown. For brevity, a semiconductor structure obtained after a plurality of steps may be described in a figure.

In describing the structure of a device, when a layer or a region is located “above” or “over” another layer or another region, it may mean that the layer or the region is directly located above another layer or another region, or other layers or regions are further included between the layer or the region and another layer or another region. In addition, if the device is turned over, the layer or the region is located “below” or “under” the another layer or the another region.

For describing the situation of being directly above the another layer or the another region, expressions of “directly above . . . ” or “above and adjacent to . . . ” are to be used herein.

Unless otherwise specified below, each part of the semiconductor device may be made of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN), group IV-IV semiconductors such as silicon carbide (SiC), group II-VI compound semiconductors such as cadmium sulfide (CdS) and cadmium telluride (CdTe), and group IV semiconductors such as silicon (Si) and germanium (Ge). A gate conductor may be formed by various materials that can conduct electricity, for example, a metal layer, a doped polysilicon layer, or a laminated gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, for example, TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and a combination of various conductive materials. A gate dielectric may be made of SiO2or a material having a dielectric constant greater than SiO2, including, for example, an oxide, a nitride, a nitrogen oxide, silicate, aluminate, and titanate. Moreover, the gate dielectric may be formed not only by the material known to those skilled in the art, but also by the material developed for the gate dielectric in the future.

FIG.1shows a sectional view of a trench MOSFET according to one or more embodiments of the present application. In the present application, a first dopant type is one of an N type or a P type, and a second dopant type is the other of the N type and the P type. An N-type semiconductor layer may be formed by implanting an N-type dopant, such as P and As, into a semiconductor layer. A P-type semiconductor layer may be formed by doping a P-type dopant, such as B, into the semiconductor layer.

A trench MOSFET100includes a substrate101and an epitaxial layer111located on the substrate101. The substrate101, as a drain region of the trench MOSFET100, has the first dopant type, which, in one or more embodiments, is heavy N-type dopant. The epitaxial layer111is located on a first surface of the substrate101, and the epitaxial layer111is lightly doped relative to the substrate101.

The trench MOSFET100includes: a trench112located in the epitaxial layer111, a gate dielectric layer113and a gate conductor115located inside the trench112; and a body region116located in the epitaxial layer111and adjacent to the trench112, where the body region116is of the second dopant type. The trench112extends from an upper surface of the epitaxial layer111into the epitaxial layer111, and ends in the epitaxial layer111. The gate dielectric layer113covers a bottom and a side wall of the trench112, and the gate conductor115is located in a cavity formed by the gate dielectric layer113around the trench112and is isolated from the epitaxial layer111by the gate dielectric layer113.

The trench MOSFET100further includes: a source region119of the first dopant type formed in the body region116; a contact region118of the second dopant type formed in the body region116; a dielectric layer117formed on the source region119and the gate conductor115; and a conductive channel120formed immediately adjacent to the source region119, which penetrates the dielectric layer117and the source region119to reach the contact region118. The dielectric layer117may be an oxide layer having a certain thickness, for example, silicon oxide.

The trench MOSFET100further includes a drain electrode121and a source electrode122. The drain electrode121is located on a second surface of the substrate101and is electrically connected to the substrate101. The source electrode122is located on the dielectric layer117and is connected to the contact region118through the conductive channel120. The second surface of the substrate101is opposite to the first surface of the substrate101.

FIG.2AtoFIG.2Kshow sectional views of stages of a method for manufacturing a trench MOSFET device according to one or more embodiments of the present application. The method for manufacturing a trench MOSFET device provided in one or more embodiments of the present application is described below with reference toFIG.2AtoFIG.2G.

As shown inFIG.2A, an epitaxial layer111is formed on a substrate101, and a trench112is formed in the epitaxial layer111.

In the step, the epitaxial layer111is formed on a first surface of the substrate101, and the substrate101serves as a drain region of the device and has a first dopant type. In one or more embodiments, a material of the substrate101may be an N-type monocrystalline silicon substrate.

A patterned first mask PR1is formed on an upper surface of the epitaxial layer111, and the trench112is formed in the epitaxial layer111through the first mask PR1.

In the step, for example, a first mask PR1is formed by using a deposition process, the patterned first mask PR1is formed by photolithography, and the epitaxial layer111is then etched through the patterned first mask PR1to form the trench112in the epitaxial layer111. In one or more embodiments, the etching may be dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching. In one or more embodiments, the first mask PR1may be a photoresist mask, and the first mask PR1is removed after the trench112is formed.

As shown inFIG.2B, a gate dielectric layer113and a polysilicon layer1151are successively formed in the trench112.

In one or more embodiments, the gate dielectric layer113is formed inside the trench112and on the upper surface of the epitaxial layer111by thermal oxidation or chemical vapor deposition (CVD). That is to say, the gate dielectric layer113covers a bottom and a side wall of the trench112and the upper surface of the epitaxial layer111. In one or more embodiments, the gate dielectric layer113may be composed of an oxide or a nitride, for example, silicon oxide or silicon nitride. The thermal oxidation includes hydrothermal oxidation (HTO) or selective reactive oxidation (SRO). The CVD includes low pressure CVD (LPCVD) or sub-atmospheric CVD (SACVD).

The polysilicon layer1151is formed inside the trench112and on the surface of the gate dielectric layer113on the epitaxial layer111through the low pressure CVD. The gate dielectric layer113isolates the polysilicon layer1151from the epitaxial layer111.

As shown inFIG.2C, the polysilicon layer1151is etched back to form a gate conductor115.

In the step, the back etching is performed to remove a part of the polysilicon layer1151located on the epitaxial layer111, so that an upper end of the polysilicon layer1151ends at an opening of the trench112, and an upper surface of the polysilicon layer1151is flush with the upper surface of the epitaxial layer111to form the gate conductor115.

In other embodiments, a chemical-mechanical planarization process may further be used for removing the part of the polysilicon layer1151located on the epitaxial layer111, so that the upper end of the polysilicon layer1151ends at the opening of the trench112, and the upper surface of the polysilicon layer1151is flush with the upper surface of the epitaxial layer111to form the gate conductor115. In this case, the gate dielectric layer113located on the epitaxial layer111is also removed. After the forming the gate conductor115, the method further includes growing an oxide layer on the surface of the epitaxial layer111as a barrier layer in a subsequent process of forming a body region116and a source region119.

As shown inFIG.2D, the body region116and the source region119are formed in a region of the epitaxial layer111adjacent to the trench112.

The body region116is of the second dopant type, where the second dopant type is opposite to the first dopant type. The photoresist mask is used to define a region of the body region116, and a first ion implantation is performed in the region defined by the photoresist mask to form the body region116in the epitaxial layer111close to the trench112. After the body region116is formed, the photoresist mask is removed. The photoresist mask is used to define a region of the source region119, and a second ion implantation is performed in the region defined by the photoresist mask to form the source region119of the first dopant type in the body region116. By controlling parameters for the ion implantation, for example, the implantation energy and dosage, a desired depth and a desired doping concentration may be obtained. A depth of the body region116does not exceed an extending depth of the gate conductor115in the trench112. The body region116and the source region119are respectively adjacent to the trench112, and are isolated from the gate conductor115by the gate dielectric layer113.

As shown inFIG.2E, a first dielectric layer1171is formed on the source region119and on the gate dielectric layer113.

In the step, the first dielectric layer1171located on the source region119is formed through the deposition process, and the chemical-mechanical planarization is further performed to obtain a flat surface. The first dielectric layer1171covers top surfaces of the source region119and the gate conductor115.

A part of the gate dielectric layer113located on the upper surface of the epitaxial layer111may or may not be removed by etching after the source region119is formed, and is conformal with the first dielectric layer1171and located on the source region119. The first dielectric layer1171is, for example, an oxide layer.

As shown inFIG.2F, a contact hole123extending through the first dielectric layer1171and the source region119to the inside of the body region116is formed.

In the step, for example, a second mask PR2is formed on the first dielectric layer1171by using a deposition process, a patterned second mask PR2is formed by photolithography, and then the source region119and the body region116are etched through the patterned second mask PR2to form the contact hole123. The contact hole123extends from the upper surface of the first dielectric layer1171toward the substrate101, extends through the first dielectric layer1171and the source region119, and stops inside the body region116. In one or more embodiments, the etching may be dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching. In one or more embodiments, the second mask PR2may be a photoresist mask, and the second mask PR2is removed after the contact hole123is formed.

As shown inFIG.2G, a second dielectric layer1172is formed.

In the step, the second dielectric layer1172is formed by using the deposition process. The second dielectric layer1172covers a surface of the first dielectric layer1171and a bottom and a side wall of the contact hole123. In one or more embodiments, the second dielectric layer1172adopts, for example, the same oxide layer as the first dielectric layer1171.

As shown inFIG.2H, the second dielectric layer1172is etched to form a spacer1231in the contact hole123.

In the step, the second dielectric layer1172is etched through the etching process. By controlling the parameters for etching, for example, etching energy, an etching angle, and an etching time, at least part of the second dielectric layer1172covering the side wall of the contact hole123is retained when the etching of the second dielectric layer1172covering the bottom of the contact hole123is completed during the etching of the second dielectric layer1172to form the spacer1231. In addition, the spacer1231has an inclined side wall. An end of the spacer1231close to the bottom of the contact hole123is thicker than an end of the spacer1231close to an opening of the contact hole123, and the thickness of the side wall gradually decreases. An inclined side wall is presented in a direction from the bottom toward the opening of the contact hole123.

When the etching of the second dielectric layer1172covering the bottom of the contact hole123is completed, the second dielectric layer1172on the surface of the first dielectric layer1171outside the contact hole123and a part of the first dielectric layer1171are removed, and the rest of the first dielectric layer1171is used as a dielectric layer117. Alternatively, the second dielectric layer1172on the surface of the first dielectric layer1171outside the contact hole123is partially retained and used as the dielectric layer117together with the first dielectric layer1171.

As shown inFIG.2I, a contact region118of the second dopant type is formed in the body region116.

In the step, a single ion implantation is performed on the body region116through the contact hole123to form the contact region118of the second dopant type in the body region116, as shown inFIG.2I(upper). During the ion implantation, the spacer1231located on the side wall of the contact hole123blocks lateral implantation of ions, so that the implanted ions mainly extend in a depth direction perpendicular to the contact hole123to prevent the formed contact region118from laterally intruding into a trench region S adjacent to the trench112.

In one or more embodiments, the contact hole123is first formed, and then the spacer1231is formed on the side wall of the contact hole123, so as to block lateral extension of the implanted ions, and prevent the formed contact region118from laterally intruding into the trench region S adjacent to the trench112, thereby ensuring the reliability of the performance of the device. In addition, the lateral intrusion of the contact region118is controlled, so that a size of the body region116is further reduced, thereby further reduce a size of the whole device or increase a density of the device per unit area.

Further, in one or more embodiments, since the contact hole123extends into the body region116, the ions can be directly implanted into the body region116during the formation of the contact region118by performing the ion implantation through the contact hole123. Compared with the ion implantation performed from the upper surface of the source region119, one or more embodiments disclosed herein provide a method that shortens the time of the ion implantation.

As shown inFIG.2I(lower), in one or more embodiments, a plurality of ion implantations may be further performed on the body region116through the contact hole123, to form the contact region118of the second dopant type in the body region116. When the plurality of ion implantations are performed on the body region116through the contact hole123, a desired depth and a desired doping concentration for each ion implantation may be obtained by controlling the parameters for the each ion implantation, for example, the implantation energy and dosage. In one or more embodiments, the implantation energy for the plurality of ion implantations may be successively decreased. For example, three ion implantations are performed on the body region116through the contact hole123. The implantation energy for the first ion implantation is the highest, the implantation energy for the second ion implantation is the second highest, and the implantation energy for the third ion implantation is the lowest.

A parasitic resistance formed by the N-type substrate101, the P-type body region116, and the N-type source region119limits the UIS performance of the device. In general, depths of the contact hole123and the conductive channel120are usually increased to reduce the parasitic resistance between the P-type body region116and the N-type source region119. However, it is difficult to perform deep-hole etching, and a hole is easily formed in the conductive channel120in a process that a metal is deposited in the deep hole to form the conductive channel120, which affects the conductivity and reliability of the device. In one or more embodiments, the plurality of ion implantations may be performed to further increase a depth of the contact region118in a longitudinal direction while ensuring that the contact region118does not invade into the trench S region, thereby reducing the parasitic resistance of the N-type substrate101, the P-type body region116, and the N-type source region119, and improving the UIS capability of the device. Compared with the reduction of the parasitic resistance of the N-type substrate101, the P-type body region116, and the N-type source region119by increasing the depth of the contact hole123, one or more embodiments disclosed herein provides a method that can simplify the manufacturing process flow of the device, and the formed device has higher reliability.

As shown inFIG.2J, the spacer1231is removed.

In the step, for example, the spacer1231is removed by wet etching.

As shown inFIG.2K, the conductive channel120is formed.

In the step, a metal layer is formed by using the deposition process. The metal layer covers the dielectric layer and fills the contact hole123, and contacts the contact region118. Then the metal layer on the dielectric layer117is removed through back etching or the chemical-mechanical planarization, so that the metal layer only fills the contact hole123to form the conductive channel120. The conductive channel120extends to the contact region118.

A source electrode122is formed on the dielectric layer117by using the deposition process, the photolithography process, and the etching process. The source electrode122is connected to the contact region118through the conductive channel120, and a drain electrode121is formed on the second surface of the substrate101by using the deposition process, as shown inFIG.1.

In the present application, the source electrode122, the gate conductor115, and the drain electrode121may be made of a conductive material. In one or more embodiments, the conductive material may be a metallic material such as an aluminum alloy or copper.

FIG.3AtoFIG.3Oshow sectional views of stages of a method for manufacturing a trench MOSFET device according to one or more embodiments of the present application. The method for manufacturing a trench MOSFET device provided in the embodiments of the present application is described below with reference toFIG.2AtoFIG.2G.

The steps shown inFIG.3AtoFIG.3Gare the same as the steps shown inFIG.2AtoFIG.2G, and the details are not described herein again.

As shown inFIG.3H, the second dielectric layer1172located at the bottom of the contact hole123is removed to form the first spacer1231.

In the step, the second dielectric layer1172is etched by using the dry etching process. By controlling the parameters for the etching, for example, etching energy, an etching angle, and an etching time, the second dielectric layer1172covering the side wall of the contact hole123is retained when the etching of the second dielectric layer1172covering the bottom of the contact hole123is completed during the etching of the second dielectric layer1172to form the first spacer1231.

As shown inFIG.3I, the first ion implantation is performed on the body region116.

In the step, the first ion implantation is performed with the first ion implantation energy through the contact hole123having the first spacer1231, and a first contact region118aof the second dopant type is formed in the body region116. During the first ion implantation, the first spacer1231located on the side wall of the contact hole123blocks lateral implantation of ions, so that the implanted ions mainly extend in a depth direction perpendicular to the contact hole.

As shown inFIG.3J, the first spacer1231is thinned to form a second spacer1232.

In the step, for example, a part of the first spacer1231is removed by wet etching, the first spacer1231is thinned, and the rest of the part of the first spacer1231forms the second spacer1232. That is to say, the thickness of the second spacer1232is less than the thickness of the first spacer1231to form a larger ion implantation window.

As shown inFIG.3K, the second ion implantation is performed on the body region116.

The second ion implantation is performed with the second ion implantation energy through the contact hole123having the second spacer1232, and a second contact region118bof the second dopant type is formed in the body region116. During the second ion implantation, the second spacer1232located on the side wall of the contact hole123blocks the lateral implantation of the ions. Since the thickness of the second spacer1232is less than the thickness of the first spacer1231, a lateral size of the formed second contact region118bis greater than a lateral size of the first contact region118a.

As shown inFIG.3L, the second spacer1232is thinned to form a third spacer1233.

In the step, for example, a part of the second spacer1232is removed by wet etching, the second spacer1232is thinned, and the rest of the part of the second spacer1232forms the third spacer1233. That is to say, the thickness of the third spacer1233is less than the thickness of the second spacer1232to form a larger ion implantation window. The third spacer1233has an inclined side wall. An end of the third spacer1233close to the bottom of the contact hole123is thicker than an end of the third spacer1233close to the opening of the contact hole123. That is to say, the thickness of the side wall gradually decreases, and an inclined side wall is presented in a direction from the bottom of the contact hole123toward the opening of the contact hole123.

As shown inFIG.3M, the third ion implantation is performed on the body region116.

The third ion implantation is performed with the third implantation energy through the contact hole123having the third spacer1233, and a contact region118is formed in the body region116. During the third ion implantation, the third spacer1233located on the side wall of the contact hole123blocks the lateral implantation of the ions.

Lateral diffusions of a dopant implanted with the first ion implantation energy, a dopant implanted with the second ion implantation energy, and a dopant implanted with the third ion implantation energy vary with distances between the implanted depth and the bottom surface of the contact hole123. In one or more embodiments, the dopant implanted during the first ion implantation is at a distance from the bottom surface of the contact hole123greater than the dopant implanted during the second ion implantation, and the dopant implanted during the second ion implantation is at a distance from the bottom surface of the contact hole123greater than the dopant implanted during the third implantation. The first ion implantation energy is greater than the second ion implantation energy, and the second ion implantation energy is greater than the third ion implantation energy. Since the lateral diffusions size at different implantation depths differ, the contact region has a more uniform lateral size by forming spacers and ion implantation windows of different sizes and by performing a plurality of ion implantations through ion implantation windows of different sizes.

As shown inFIG.3N, the third spacer1233is removed.

In the step, for example, the third spacer1233is removed by wet etching.

As shown inFIG.3O, a conductive channel120is formed.

In the step, a metal layer is formed by using the deposition process. The metal layer covers the dielectric layer and fills the contact hole123, and contacts the contact region118. Then the metal layer on the dielectric layer117is removed through back etching or the chemical-mechanical planarization, so that the metal layer only fills the contact hole123to form the conductive channel120. The conductive channel120extends to the contact region118.

A source electrode122is formed on the dielectric layer117by using the deposition process, the photolithography process, and the etching process. The source electrode122is connected to the contact region118through the conductive channel120, and a drain electrode121is formed on the second surface of the substrate101by using the deposition process, as shown inFIG.1.

In the present application, the source electrode122, the gate conductor115, and the drain electrode121may be made of a conductive material. In one or more embodiments, the conductive material may be a metallic material such as an aluminum alloy or copper.

As described above according to the embodiments of the present application, all details of these embodiments are not described in detail and do not limit the present application to being only the specific embodiments. These embodiments are selected and specifically described in this specification to better explain the principles and practical application of the present application, so that those skilled in the art can make good use of and modifications based on the present application.