Ovonic threshold switch (OTS) driver/selector uses unselect bias to pre-charge memory chip circuit and reduces unacceptable false selects

The present disclosure generally relates to non-volatile memory arrays and memory devices in which a leakage current through an OTS is utilized to pre-charge a circuit of a memory chip. By running an additional wire on each side of a tile which is orthogonal to, above, or below the X and Y select wires, a high value resistance material, such as an OTS, may be deposited at the intersection. The OTS allows the word line or bit line to be selected without pulling excessive leakage to the select wire from the bias voltage, such as V/2. A thickness of the OTS is adjusted such that the Vt of the OTS is greater than V/2, with margin, and the OTS does not turn on when the OTS is selected. A resistance is created between the V/2 wire and the word line select wire or the bit line select wire.

BACKGROUND OF THE DISCLOSURE

Field of the Disclosure

Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly to non-volatile memory and pre-charging a memory chip circuit.

Description of the Related Art

As electronic memories approach limits beyond which they will no longer be able to produce the density, cost, or performance improvements necessary, a host of memory technologies are being investigated as potential replacements for conventional silicon complementary metal oxide semiconductor (CMOS) integrated circuit memories.

Among the memory technologies being investigated are a number of bi-directional memory technologies: memories that exploit a directional characteristic of the material used to program or read a memory device. Conventional memory devices typically associate one of two memory states with the presence or absence of charge, or with a high or low voltage. In such conventional memories, memory states are associated with uni-directional characteristics; charge is either present or not (e.g., DRAM, FLASH) or a node is held at a high or low voltage (e.g., SRAM). There is no sense of “direction” to such storage mechanisms. In contrast, bi-directional memories employ some directional aspect of their memory material to store binary information. For example, one memory state may be written by forcing a current through a bi-directional memory device in one direction or applying a voltage of one polarity, and another memory state may be written by forcing a current through the same device in the opposite direction or applying a voltage of the opposite polarity. The programmed memory states may then be sensed by, for example, applying to the memory device either a voltage to measure current related to memory state, or forcing a current through and measuring a voltage related to memory state.

Bi-directional memory types include resistive random access memories and magneto-resistive random access memories (both referred to as RRAM), programmable metallization cells, Pnictide phase change memories, polymer memories, ferro-electric random access memories (FeRAM), ionic memory devices and metal nano-particle memory cells.

A RRAM cell may be programmed, respectively, to high resistance and low resistance values by applying electric pulses of opposite polarities to a cell. The cell's high and low resistance values are employed to represent two different memory states.

4 F2memory cells are typically built between the intersection of orthogonal first metal and second metal wires running through the memory tile plane in the X-Y directions to select the memory cell. Generally, the width of a cell is 2 F in each direction. Each wire can terminate at the edge and be driven from the far edge, thus increasing the available space for the driver to 4 F. However, the available space remains tight, thus making it difficult to fit a drive transistor therein. As such, little room exists for an interconnect or extra transistors connected to each word line (or bit line in the other direction). Additionally, the gate of the transistor is either on or off, as driven by a decoder. As the select transistor is 1 of N, where N may be 2000 wires in a typical NVM memory (on pitch), when the wire is not selected it is floating and may drift away from the unselect level.

To avoid current leakage in NVM, the word lines and bit lines are provided with half of the voltage of the system (rather than ground or high-impedance). Further, word lines and bit lines can be pre-charged before any operation by a voltage through a high resistance.

In arrays, such as those larger than 1K×1K memory cells, with drivers disposed on each of the four sides, it often becomes difficult to add a transistor or resistor connecting each line to respective unselect bias, such as to V/2. Absent this “keep alive” bias, it is difficult to keep each word line biased at the unselect level, such as V/2. Further, with a transistor connected to the line, the line may drift to the voltage of leakage through the transistor connected thereto. With the deselect level on the drain at zero volts, the word line will inevitably leak away to its voltage, which causes unacceptable false selects. The gate of the select transistor can be controlled by a CMOS NAND decoder, such that the gate is selected high 1/N along the side of the memory tile. Additional space does not exist to add another drive transistor or high value resistor. Furthermore, cycling back to the lines periodically to refresh wastes power and machine cycles.

Therefore, what is needed in the art is an improved memory device. More specifically, what is needed in the art is an ovonic threshold switch (OTS) keep alive for non-volatile memory array select lines, where the OTS is used to pre-charge the memory chip circuit.

SUMMARY OF THE DISCLOSURE

The present disclosure generally relates to non-volatile memory arrays and memory devices in which a leakage current through an ovonic threshold switch (OTS) is utilized to pre-charge a circuit of a memory chip. By running an additional wire on each side of a tile which is orthogonal to, above, or below the X and Y select wires, a high value resistance material, such as an OTS, may be deposited at the intersection. The OTS allows the word line or bit line to be selected without pulling excessive leakage to the select wire from the bias voltage, such as V/2. A thickness of the OTS is adjusted such that the Vtof the OTS is greater than V/2, with margin, and the OTS does not turn on when the OTS is selected. A resistance is created between the V/2 wire and the word line select wire or the bit line select wire. This technique can be applied to bias other signals to other voltages.

In one embodiment, a memory device is disclosed. The memory device includes a word line, a bit line disposed perpendicular to the word line, and a memory element disposed between the word line and the bit line. The memory device also includes a select element coupled to the memory element and a connecting element. The select element is disposed adjacent the word line and the connecting element is disposed between the word line and a voltage source.

In another embodiment, a memory device is disclosed. The memory device includes a word line, a bit line disposed perpendicular to the word line, and a memory element disposed between the word line and the bit line. The memory device also includes a select element coupled to the memory element and a connecting element. The select element is disposed adjacent the bit line and the connecting element is disposed between the bit line and a voltage source.

In another embodiment, a memory array is disclosed. The memory array includes a word line, a bit line disposed perpendicular to the word line, at least one memory device, and at least one connecting element disposed between one of the word line or the bit line and a fixed voltage. The at least one memory device includes a memory element disposed between the word line and the bit line, and a select element coupled to the memory element. The select element is disposed adjacent the word line.

DETAILED DESCRIPTION

The present disclosure generally relates to non-volatile memory arrays and memory devices in which a leakage current through an OTS is utilized to pre-charge a circuit of a memory chip. By running an additional wire on each side of a tile which is orthogonal to, above or below, the X and Y select wires, a high value resistance material, such as an OTS, may be deposited at the intersection therein. The OTS allows the word line or bit line to be selected without pulling excessive leakage to the select wire from the bias voltage, such as V/2. A thickness of the OTS is adjusted such that the Vtof the OTS is greater than V/2, with margin, and the OTS does not turn on when the OTS is selected. A resistance is created between the V/2 wire and the word line select wire or the bit line select wire. This technique can be applied to bias other signals to other voltages.

FIGS. 1A and 1Bare schematic illustrations of a memory device100. The memory device100has word line102having a first longitudinal axis102A and a bit line104having a second longitudinal axis104A perpendicular to the word line102.

The memory device100further includes a memory cell106disposed between the word line102and the bit line104. In some embodiments, the memory cell106is coupled to the word line102and/or the bit line104. The memory cell106includes a memory element108and a select element110. The memory element108is disposed between the word line102and the bit line104. In some embodiments, the memory element108is coupled to the word line102or the bit line104. Furthermore, in certain embodiments, the memory element108is a resistive random access memory (RRAM) device. In other embodiments, the memory element108may be a phase change memory (PCM) device. The select element110is coupled to the memory element108. Furthermore, the select element110is disposed adjacent the bit line104. In certain embodiments, the select element110may contact the bit line104. The select element110is selected from the group consisting of an ovonic threshold switch (OTS), a doped chalcogenide alloy, a thin film silicon, a metal-metal oxide switch, or a Field Assisted Superlinear Threshold selector (FAST). Furthermore, in some embodiments, the memory element108is in series with the select element110. It is contemplated, however, that in some embodiments the select element110may be disposed adjacent the word line102and/or contact the word line102.

The memory device100also includes a connecting element112. The connecting element112is disposed between the word line102and a voltage source114. In some embodiments, the connecting element112comprises an undoped or lightly doped polysilicon material. In some embodiments, the connecting element112comprises a second memory element116and a second select element118. The second select element118of the connecting element112may include one of an ovonic threshold switch (OTS), a doped chalcogenide alloy, a thin film silicon, a metal-metal oxide switch, or a FAST. The second memory element116of the connecting element112comprises a RRAM material and/or device. In other embodiments, the second memory element116of the connecting element112may comprise a PCM material and/or device. In some embodiments, the connecting element112may include only the select element118with a thickness equal to approximately the height of memory cell106. In some embodiments, memory element116may be replaced with a select element118.

As shown inFIGS. 1A and 1B, the connecting element112is coupled to the word line102. In some embodiments, the connecting element112may also be coupled to a wire120. Wire120may be substantially similar to the word line102and/or the bit line104ofFIGS. 1A and 1B. However, rather than being a memory wire like word line102or bit line104, wire120may be tied to a voltage, such as V/2, where V is the higher write voltage applied across the memory array word line(s)102and/or bit line(s)104. Wire120may be similar to a column line under a word line, or a word line over a column line. Array lines may be extended to be over or under the wire120.

The select element110of the memory cell106and the second select element118of the connecting element112may be formed at the same level and/or at the same time using a single masking step. It is contemplated, however, that in some embodiments, the select element110and the second select element118may be formed at different levels, at different times, and/or utilizing different or distinct mask steps. As such, the memory element108and the select element110of the memory cell106may flip or swap locations between the respective word line102and bit line104. Also, the second memory element116and the second select element118of the connecting element112may flip or swap locations between the respective word line102or bit line104and the corresponding wire120. Additionally, in some embodiments, the second memory element116and the second select element118of the connect element112may be made of the same material, and/or one of the second memory element116or the second select element118may be extended to displace the other entirely.

FIGS. 2A and 2Bare schematic illustrations of a memory device200. The memory device200has bit line202having a first longitudinal axis202A and a word line204having a second longitudinal axis204A perpendicular to the bit line202.

The memory device200further includes a memory cell206disposed between the bit line202and the word line204. In some embodiments, the memory cell206is coupled to the bit line202and/or the word line204. The memory cell206includes a memory element208and a select element210. The memory element208is disposed between the bit line202and the word line204. In some embodiments, the memory element208is coupled to the bit line202or the word line204. Furthermore, in certain embodiments, the memory element208is a resistive random access memory (RRAM) device. In other embodiments, the memory element208may be a phase change memory (PCM) device, a magneto resistive (MRAM) device or Memristor device, without limitation. The select element210is coupled to the memory element208. Furthermore, the select element210is disposed adjacent the word line204. In certain embodiments, the select element210may contact the word line204. The select element210is selected from the group consisting of an ovonic threshold switch (OTS), a doped chalcogenide alloy, a thin film silicon, a metal-metal oxide switch, or a FAST. Furthermore, in some embodiments, the memory element208is in series with the select element210. It is contemplated, however, that in some embodiments the select element210may be disposed adjacent the bit line202and/or contact the bit line202.

The memory device200also includes a connecting element212. The connecting element212is disposed between the bit line202and a voltage source214. In some embodiments, the connecting element212comprises an undoped polysilicon material. In some embodiments, the connecting element212comprises a second memory element216and a second select element218. The second select element218of the connecting element212may include one of an ovonic threshold switch (OTS), a doped chalcogenide alloy, a thin film silicon, a metal-metal oxide switch, or a FAST. The second memory element216of the connecting element212comprises a RRAM material and/or device. In other embodiments, the second memory element216of the connecting element212may comprise a PCM material and/or device. In some embodiments, the select element218may be extended and/or displace the memory element216, or, in other embodiments, the memory element216may be replaced by another select element218via the use of mask, deposit techniques, and/or etch techniques familiar to those skilled in the art.

As shown inFIGS. 2A and 2B, the connecting element212is coupled to the bit line202. In some embodiments, the connecting element212may also be coupled to a wire220. Wire220may be built substantially similar to the bit line202and/or the word line204ofFIGS. 2A and 2B. However, rather than being a memory wire like bit line202or word line204, wire220may be tied to a voltage, such as V/2. Wire220may be similar to a column line under a word line, or a word line over a column line. Array lines may be extended to be over or under the wire220. V may be the max voltage applied across the array word lines and bit lines on a given chip for that cycle and may vary between write and read cycles, being greater for write cycles.

The select element210of the memory cell206and the second select element218of the connecting element212may be formed at the same level and/or at the same time using a single masking step. It is contemplated, however, that in some embodiments, the select element210and the second select element218may be formed at different levels, at different times, and/or utilizing different or distinct mask steps. As such, the memory element208and the select element210of the memory cell206may flip or swap locations between the respective bit line202and word line204. Also, the second memory element216and the second select element218of the connecting element212may flip or swap locations between the respective bit line202or word line204and the corresponding wire220. In some embodiments, the select element218may displace the memory element216.

FIG. 3Aillustrates a memory array300, according to one embodiment. The memory array300is comprised of a plurality of bottom interconnect lines302, a plurality of top interconnect lines304disposed perpendicular to the plurality of bottom interconnect lines302, and a plurality of memory cells306disposed in between the plurality of bottom interconnect lines302and the plurality of top interconnect lines304. According to one example, inFIGS. 1A and 1Ba memory device100is shown, and includes a first interconnect line, such as word line102, a second interconnect line, such as bit line104, and a memory cell106disposed between the word line102and the bit line104. Furthermore, according to another example, inFIGS. 2A and 2Ba memory device200is shown and includes a first interconnect line, such as bit line202, a second interconnect line, such as word line204, and a memory cell206disposed between the bit line202and the word line204. Although not shown, it is to be understood that the first plurality of bottom interconnect lines302substantially similar to the either of the word lines and/or the bit lines ofFIG. 1A, 1B, 2A, or2B. As such, the first interconnect line302may be a word line or a bit line, while the second interconnect line304may be a bit line or a word line, respectively, depending on the selection of the first interconnect line302. The first interconnect line302and the second interconnect line304may not be the same type of line. To illustrates, the first interconnect line302may be a word line and the second interconnect line302may be a bit line, or the first interconnect line302may be a bit line and the second interconnect line302may be a word line.

Each memory device306ofFIG. 3Amay include a memory element and a select element. The memory element is disposed between the first interconnect line302and the second interconnect line304. The select element is coupled to the memory element. In some embodiments, the select element is disposed adjacent either the first interconnect line302or the second interconnect line304.

Memory array300further includes at least one connecting element308. Each connecting element308is disposed between one of the first interconnect line302or the second interconnect line304and a fixed voltage310. In some embodiments, the fixed voltage310may be V/2.

In some embodiments, the connecting element308comprises an undoped polysilicon material. In some embodiments, the connecting element308comprises a second memory element and a second select element. The second switch element of the connecting element308may include one of an ovonic threshold switch (OTS), a doped chalcogenide alloy, a thin film silicon, a metal-metal oxide switch, or a FAST. The second memory element of the connecting element308may comprise a RRAM material and/or device. In other embodiments, the second memory element of the connecting element308may comprise a PCM material and/or device, MRAM, and/or Memristor, without limitation.

As shown inFIG. 3A, the connecting element308is coupled to the first interconnect line302and/or the second interconnect line304. In some embodiments, the connecting element308may also be coupled to a wire320. Wire320may be built substantially similar to the first interconnect line302and/or the second interconnect line304. However, rather than being a memory wire like the first interconnect line302and/or the second interconnect line304, wire320may be tied to a voltage, such as V/2. Wire320may be similar to a column line under a word line, or a word line over a column line. Array lines may be extended to be over or under the wire320.

FIG. 3Bschematically illustrates a first embodiment of a memory array400. Memory array400is substantially similar to memory array300ofFIG. 3A. As shown inFIG. 3B, the first interconnect line302B is a bit line, and the second interconnect line304B is a word line. At least one memory cell306B is disposed between each bit line and word line. Each memory device306B includes a memory element330B and a select element332B. The memory element330B is in series with the select element332B. The memory element330B is disposed between the bit line and the word line. The select element332B is coupled to the memory element330B. Further, the select element332B is disposed adjacent the word line. The select element332B is an ovonic threshold switch (OTS), a doped chalcogenide alloy, a thin film silicon, a metal-metal oxide switch, or a FAST.

The memory array400ofFIG. 3Balso includes the least one connecting element308B. Each connecting element308B is disposed between each bit line (first interconnecting line302B) and a fixed voltage310B. In some embodiments, the fixed voltage310B may be V/2.

In some embodiments, the connecting element308B comprises an undoped polysilicon material. In some embodiments, the connecting element308B comprises a second memory element312B and a second select element314B. The second select element314B of the connecting element308B may include one of an OTS, a doped chalcogenide alloy, a thin film silicon, a metal-metal oxide switch, or a FAST. The second memory element312B of the connecting element308B may comprise a RRAM material and/or device. In other embodiments, the second memory element312B of the connecting element308B may comprise a PCM material and/or device.

As shown inFIG. 3B, the connecting element308B is coupled to each bit line (first interconnecting line302B) of the memory array400B. As further shown, the connecting element308B is also coupled to wire320B. Wire320B is substantially similar to the bit line (first interconnecting line302B). However, rather than being a memory wire like the bit line (first interconnecting line302B), wire320B is tied to a voltage310B, such as V/2.

FIG. 3Cschematically illustrates a first embodiment of a memory array500. Memory array500is substantially similar to memory array300ofFIG. 3A. As shown inFIG. 3C, the first interconnect line302C is a word line, and the second interconnect line304C is a bit line. At least one memory device306C is disposed between each word line and bit line. Each memory device306C includes a memory element330C and a select element332C. The memory element330C is in series with the select element332C. The memory element330C is disposed between the word line and the bit line. The select element332C is coupled to the memory element330C. Further, the select element332C is disposed adjacent the bit line. The select element332C is an OTS, a doped chalcogenide alloy, a thin film silicon, a metal-metal oxide switch, or a FAST.

The memory array500ofFIG. 3Calso includes the least one connecting element308C. Each connecting element308C is disposed between each word line (first interconnecting line302C) and a fixed voltage310C. In some embodiments, the fixed voltage310C may be V/2.

In some embodiments, the connecting element308C comprises an undoped polysilicon material. In some embodiments, the connecting element308C comprises a second memory element312C and a second select element314C. The second select element314C of the connecting element308C may include one of an OTS, a doped chalcogenide alloy, a thin film silicon, a metal-metal oxide switch, or a FAST. The second memory element312C of the connecting element308C may comprise a RRAM material and/or device. In other embodiments, the second memory element312C of the connecting element308C may comprise a PCM material and/or device.

As shown inFIG. 3C, the connecting element308C is coupled to each word line (first interconnecting line302C) of the memory array500. As further shown, the connecting element308C is also coupled to wire320C. Wire320C is substantially similar to the word line (first interconnecting line302C). However, rather than being a memory wire like the word line (first interconnecting line302C), wire320C is tied to a voltage310C, such as V/2.

FIG. 4is a schematic circuit diagram600of a row decoder for an ovonic threshold switch keep alive system. As shown, wire602is operatively connected to under and/or above to a word line or a bit line604A,604B. In certain embodiments, the word line604A may be an X select wire and the bit line604B may be a Y select wire. It is contemplated, however, that in certain embodiments, the bit line604B may be the X select wire, and the word line may be the Y select wire. The wire602may be substantially similar to the wire120ofFIG. 1, the wire220ofFIG. 2AorFIG. 2B, or the wire320ofFIG. 3AorFIG. 3B. A high value resistance material608is disposed at the intersection606of the word line604A and the bit line604B. In some embodiments, the high value resistance material608includes an undoped semiconductor material or an ovonic threshold switch (OTS), either of which have a high resistance which allows the word line or the bit line to be selected without pulling excessive leakage to the select wire from the bias voltage, such as V/2.

The fabrication of the row decoder device for an ovonic threshold switch keep alive system may include providing a mask to define a region between the metal wires (for example, the word line604A, the bit line604B, and/or the wire602), in which is deposited the high value resistance material608(for example, the OTS). In some embodiments, the OTS may be deposited with electrodes to encapsulate the OTS. The OTS may have a thickness adjusted such that a Vtof the OTS is greater than V/2 with a margin so that the OTS does not turn on when the OTS is selected. As such, a resistance is created between the V/2 wire610and the any of the word line select wire, or between the V/2 wire610and the bit line select wire (in the Y-direction), as similarly done for the word line selected wire.

Benefits of the present disclosure include avoidance of the need to individually refresh the word lines and bit lines upon power up and after an unselect. By providing an additional wire down each side of the tile which are orthogonal to, above or below the X and Y select wires, a material may be deposited at the intersection using a mask to define a region in which a high value resistance material is deposited. A first end of the wire is connected to the unselect bias voltage, such as V/2 where V is the write voltage applied across the array X and Y select wires. As such, the floating wires are maintained at the unselect voltage V/2 and driven there automatically upon power up.

Additional benefits include that in a non-volatile memory array, leakage current through a non-conducting OTS is used to pre-charge a circuit of the memory chip. Specifically, the OTS is utilized to pre-charge the word lines and the bit lines. The pre-charge voltage may be half of the operating voltage. The connecting element “keep-alive” can also be applied to other signals on a chip by placement between the signal and appropriate voltage, which may be a DC or voltage that varies.

In summation, non-volatile memory arrays and memory devices in which a leakage current through an OTS is utilized to pre-charge a circuit of a memory chip is disclosed. By running an additional wire on each side of a tile which is orthogonal to, above, or below the X and Y select wires, a high value resistance material, such as an OTS, may be deposited at the intersection. The OTS allows the word line or bit line to be selected without pulling excessive leakage to the select wire from the bias voltage, such as V/2. A thickness of the OTS is adjusted such that the Vtof the OTS is greater than V/2, with margin, and the OTS does not turn on when the OTS is selected. A resistance is created between the V/2 wire and the word line select wire or the bit line select wire. The resistance can replace a transistor which can connect the wire to the voltage when the wire is not selected or during inactive portions of the memory cycle.