Capacitive load driving circuit and droplet ejection apparatus

A capacitive load driving circuit includes: a phase lead compensator, advancing a phase of an output signal of a filter; a series compensator, determining an error between a driving signal and an output signal of the phase lead compensator; a stabilization compensator, performing a derivative action on an output signal of the filter; a voltage comparison unit, comparing a differential voltage between a signal output from the series compensator and a signal output from the stabilization compensator, with a voltage of a predetermined triangular waveform, and outputting a pulse width modulation signal; a voltage amplification unit, amplifying the voltage of the pulse width modulation signal output, and supplying the amplified pulse width modulation signal to the input terminal of the filter; and plural capacitive loads each connected in parallel to the capacitor. A droplet ejection apparatus includes the capacitive load driving circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC 119 from Japanese Patent Application No. 2007-327613 filed Dec. 19, 2007.

BACKGROUND

1. Technical Field

The present invention relates to a capacitive load driving circuit and a droplet ejection apparatus.

2. Related Art

Conventionally, a drive circuit of an ink jet head ejects ink droplets from nozzles provided respectively to piezoelectric elements provided in a piezoelectric head by supplying an analog driving signal to the piezoelectric elements provided. Since the piezoelectric elements are capacitive elements, electrostatic capacity, which is a load, of the piezoelectric head increases as the number of piezoelectric elements driven simultaneously increases. Thus, there is a problem that a waveform of a driving signal input into the piezoelectric element is weakened such that a stable operation cannot be realized.

SUMMARY

A first aspect of the invention is a capacitive load driving circuit including: a filter having an inductor, one end of which is connected to an input terminal and another end of which is connected to an output terminal, and a capacitor having a fixed electrostatic capacity, and one electrode of which is connected to the output terminal, and another electrode of which is grounded; a plurality of capacitive loads, each of which is connected in parallel to the capacitor and any one of the capacitive loads is driven; a phase lead compensator that advances a phase of an output signal of the filter; a series compensator that determines an error between a driving signal and an output signal of the phase lead compensator and outputs a signal on which a proportional integral operation has been performed; a stabilization compensator that is configured independently of the series compensator and outputs a signal obtained by performing a derivative action on an output signal of the filter; a voltage comparison unit that compares a differential voltage between a signal output from the series compensator and a signal output from the stabilization compensator and a voltage of predetermined triangular waves and outputs a pulse width modulation signal; and a voltage amplification unit that amplifies the voltage of the pulse width modulation signal output from the voltage comparison unit and supplies the amplified pulse width modulation signal to the input terminal of the filter.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of the present invention will be described in detail below with reference to drawings.

First Exemplary Embodiment

FIG. 1is a block diagram showing the configuration of an ink jet printer according to a first exemplary embodiment of the invention. The ink jet printer has a piezoelectric head10for ejecting ink, a control unit20for controlling ejection of ink, and a drive circuit30for driving the piezoelectric head10based on control of the control unit20.

The piezoelectric head10has an ejection element group in which ejection elements, each of which includes n (n is a natural number) piezoelectric elements111to11n, are accumulated, n transmission gates121to12n, each of which is connected to the respective piezoelectric element111to11nin series to be turned on or turned off, and a piezo-selection circuit13for controlling on or off of the transmission gates121to12nto select any one of the piezoelectric elements111to11n.

Subscripts (1 to n) of numerals are used to distinguish each piezoelectric element or transmission gate and are omitted when there is no need for distinction.

FIG. 2is a diagram showing the configuration of an ejection element. The piezoelectric head10is produced by integrating about 100 to 1000 of the ejection elements shown inFIG. 2. When a voltage changing over time is applied to the piezoelectric element11in each ejection element, a diaphragm11avibrates in accordance with fluctuations of the piezoelectric element11and the volume of a pressure chamber11bfilled with liquid ink changes before droplets are thereby ejected from a nozzle11c.

The control unit20has a driving signal generation circuit21for generating a driving signal, an image memory22for storing image data, a control memory23for storing control data, and a CPU24for performing overall control.

The CPU24uses the control data stored in the control memory23to cause the driving signal generation circuit21to generate a predetermined driving signal. The CPU24also controls the piezo-selection circuit13of the piezoelectric head10to suitably select an ejection element based on the image data stored in the image memory22so that the transmission gate12corresponding to the ejection element is turned on.

The drive circuit30provides, for example, a driving signal shown inFIG. 3to the piezoelectric head10. The frequency band of the driving signal broadens with increasing ejection frequencies and reaches several hundred kHz in the example shown inFIG. 3.

A driving signal V1, which is a fixed multiple times voltage of the driving signal shown inFIG. 3, is input into the drive circuit30. More specifically, if the voltage amplification factor (the ratio of an input voltage V1of the drive circuit to a filter voltage V2) of the drive circuit30is 20, while the maximum value of the driving signal shown inFIG. 3is 29 [V], that of the input voltage V1is 1.45 [V].

Here, the piezoelectric element11in the piezoelectric head10is capacitive. Thus, the drive circuit30drives the piezoelectric head10, which is a load whose electrostatic capacity changes in accordance with the number of dots to be driven.

Incidentally, the piezoelectric elements111to11nare connected in parallel to a fixed-capacity capacitor C0constituting a filter34shown inFIG. 5later. Therefore, frequency characteristics of the filter34are determined by an inductor L, the capacitor C0, and electrostatic capacity Cpwhose capacity changes depending on the number of piezoelectric elements111to11nto be driven.

If for example, the electrostatic capacity of one piezoelectric element11is 400 [pF], the electrostatic capacity Cpviewed from the drive circuit30when an image of 250 dots is formed is 0.1 [μF]. Here, filter frequency characteristics when L=2.2 [μF], C0=0.2 [μF], and Cp=0.1, 0.3, 0.5 [μF] are as shown inFIG. 4.

Configuration of the Drive Circuit30:

FIG. 5is a circuit diagram showing the configuration of the drive circuit30.FIG. 6is a diagram showing transfer functions of each of circuits constituting the drive circuit30.

The drive circuit30has a switching voltage amplifier circuit33, the filter34, a stabilization compensator35for stabilizing a control target, a first phase lead compensator36for making phase lead compensation to prevent oscillations during feedback, a second phase lead compensator37connected in series to the first phase lead compensator36, and a series compensator38.

Switching Voltage Amplifier Circuit33

The switching voltage amplifier circuit33has a comparator IC1, a gate drive circuit GD, and a first transistor TR1and a second transistor TR2constituted by, for example, MOSFET.

A non-inversion input terminal of the comparator IC1is connected to an output terminal of an operational amplifier IC4via a resistor R21. Triangular waves are input into an inversion input terminal of the comparator IC1. An output terminal of the comparator IC1is connected to an input terminal of the gate drive circuit GD. A first output terminal of the gate drive circuit GD is connected to a gate of the first transistor TR1and a second output terminal thereof is connected to a gate of the second transistor TR2.

A high-voltage source is applied to a drain of the first transistor TR1. A source of the first transistor TR1is connected to a drain of the second transistor TR2. A source of the second transistor TR2is grounded. Then, the source of the first transistor TR1(the drain of the second transistor TR2) becomes an output terminal of the switching voltage amplifier circuit33. An output terminal of the switching voltage amplifier circuit33is connected to the piezoelectric head10via the filter34.

The comparator IC1compares an amplitude of a preset triangular wave and that of an analog signal V5output from the operational amplifier IC4. The comparator IC1outputs a pulse signal of logic ‘0’ if the amplitude of the triangular wave is larger and outputs a pulse signal of logic ‘1’ if the amplitude of V5is larger. Therefore, the comparator IC1is a pulse width modulation circuit whose cycle Ts is the same as that of the triangular wave and that outputs a pulse signal in proportion to the amplitude of an input analog signal and of the ratio (duty ratio) of a time TONof logic ‘1’ to a time TS-TONof logic ‘0’. The amplitude of the output signal is generally 3 to 5 [V].

The gate drive circuit GD amplifies the amplitude of a pulse signal output from the comparator IC1to a voltage at which the transistors TR1and TR2are operable. Then, if the pulse signal from the comparator IC1is logic ‘1’, the gate drive circuit GD outputs a voltage that turns on the transistor TR1and also a voltage that turns off the transistor TR2. If the pulse signal from the comparator IC1is logic ‘0’, the gate drive circuit GD outputs a voltage that turns off the transistor TR1and also a voltage that turns on the transistor TR2.

The transistors TR1and TR2complementarily perform a switching operation in accordance with a pulse signal output from the gate drive circuit GD. An output voltage 6 V of the switching voltage amplifier circuit33is similar to a pulse signal shown inFIG. 7. The output voltage 6 V is equal to a supply voltage VDD if a voltage drop due to channel resistance is excluded.

Here, the maximum voltage that can be input into the switching voltage amplifier circuit33is a maximum voltage VTof the triangular wave and the maximum output voltage is the supply voltage VDD. Therefore, the voltage amplification factor K0of the switching voltage amplifier circuit33is given by Equation 1:
K0=VDD/VT(1)

The filter34has the inductor L, one terminal of which is connected to the output terminal of the switching voltage amplifier circuit33and the other terminal of which becomes a filter output terminal and the capacitor C0, one electrode of which is connected to the filter output terminal and the other electrode of which is grounded.

A capacity C of a capacitor is the sum of the fixed capacity C0and the electrostatic capacity Cpthat changes depending on the number of dots to be printed. A resonance frequency f0of a filter is given by Equation 2 and an angular frequency ω0is given by Equation 3:

A transfer function F(s) from input V6to output V2of the filter34is given by Equation 4:

where s is a Laplace variable and a relation with a frequency f is defined by Equation 5:
s=j2πf, j=√{square root over (−1)}  (5)

As shown inFIG. 6, a transfer function from input V5of the switching voltage amplifier circuit33to the output V2of the filter34is defined as P(s). P(s) is expressed by Equation 6, which is a product of Equation 1 and Equation 4. Equation 6 is called a control target.

An output terminal of the filter34is connected to the stabilization compensator35and the first phase lead compensator36.

The stabilization compensator35has an operational amplifier IC2. An inversion input terminal of the operational amplifier IC2is connected to an output side of the filter34via a resistor R11and a capacitor C11connected in series and also to the output side of the stabilization compensator35via a resistor R12. A non-inversion input terminal of the operational amplifier IC2is grounded.

Since the real part of a solution of a characteristic equation of (Equation 6) is 0, the control target P(s) is unstable. Thus, the control target P(s) will be stabilized.

Negative feedback from V2to V6inFIG. 6is a stabilization compensator K2(s) and the control target P(s) is stabilized in the invention by causing the stabilization compensator K2(s) to have derivative characteristics. If TD0is a time constant, the transfer function of K2(s) is given by Equation 7 and that of a closed loop system consisting of P(s) and K2(s) is given by Equation 8:

FIG. 8is a diagram exemplifying frequency characteristics of the transfer function Q(s) from V3to V2. According toFIG. 8, it is evident that resonance is suppressed compared withFIG. 4.

In a circuit configuration shown inFIG. 5, derivative characteristics based on Equation 7 can in principle be imparted. However, in reality, the gain in a high-frequency region increases to lead to vulnerability to noise and thus, as shown in Equation 9 below, a configuration using inexact differential was adopted:

K2⁡(s)=sC11⁢R111+sC11⁢R11(9)
Phase Lead Compensator

The first phase lead compensator36has a capacitor C31and a resistor R31connected in parallel and a resistor R32. One end of a parallel circuit consisting of the capacitor C31and the resistor R31is connected to the output terminal of the filter34. The other end is an output terminal of the first phase lead compensator36and is grounded via the resistor R32.

A transfer function K11(s) of the first phase lead compensator36is given by Equation 10:

G0gives a DC voltage amplification factor of the whole drive circuit30from the input V1to the output V2. Since the voltage amplification factor is set to be 20 (26 [dB]) from what has been described above, G0=20.

The second phase lead compensator37is connected to the output side of the first phase lead compensator36in series and has an operational amplifier IC3. A non-inversion input terminal of the operational amplifier IC3is grounded via the resistor R32. An inversion input terminal of the operational amplifier IC3is connected to an output terminal of the operational amplifier IC3via a resistor R42and also is grounded via a capacitor C and a resistor R connected in series. Then, the output terminal of the operational amplifier IC3is connected to the series compensator38via a resistor R51.

A transfer function K12(s) of the second phase lead compensator37is given by Equation 13:

The operational amplifier IC3also has a function to act as a buffer between the first and second phase lead compensators36and37and the subsequent series compensator38by receiving a high input impedance signal from the first phase lead compensator36and converting the received signal into a low impedance signal.

A phase lead compensator constituted by the first and second phase lead compensators36and37described above has characteristics shown below.

FIG. 9is a diagram showing phase characteristics of the stabilized control target Q(s). Since there is almost no phase margin (a margin of phase delay with respect to −180 degrees) near 1 [MHz] when the load is 0.5 [μF], there is a possibility of oscillation if feedback is received as it is.

Since Q(s) is a second-order lag system, second-order phase lead compensation K1(s) obtained by cascade-connecting first-order phase lead compensation is used in the exemplary embodiment.

If the output of the phase lead compensation K1(s) is V8, phase voltage characteristics from V3to V8are like those shown inFIG. 10. In comparison withFIG. 9,FIG. 10shows an improvement of the phase margin by 60 [deg] when the load capacity is 0.5 [μF]. Accordingly, negative feedback can be received with stability with respect to load fluctuations.

The series compensator38has the operational amplifier IC4. An inversion input terminal of the operational amplifier IC4is connected to the output terminal of the operational amplifier IC4via a resistor R52and a capacitor C51connected in series. The driving signal V1generated by the driving signal generation circuit21is input into a non-inversion input terminal of the operational amplifier IC4. The output terminal of the operational amplifier IC4is connected to the non-inversion input terminal of the comparator IC1via the resistor R21.

The series compensator38determines an error between the driving signal V1and the signal V8whose phase is advanced from that of the output V2of the filter34and performs an operation to amplify the error and that to integrate the error.

Particularly the latter performs an operation in such a way that a drive circuit becomes a 1-type servo control system. That is, if the input signal V1is DC due to an integral action, the steady-state deviation of the output signal V2becomes 0 with respect to a target value. Voltage characteristics of the signals V1and V8and output V3are given by Equation 16:
V3=A(s)(V1−V8)  (16)
where A(s) satisfies Equations 17 to 19:

The resistor R21and a resistor R22shown inFIG. 5add the output V3of the series compensator38and output V4of the stabilization compensator35. The added signal V5is input into the non-inversion input terminal of the comparator IC1. Since the stabilization compensator35performs an inversion operation due to Equation 9, the relationship among V3, V4and V5is given by Equation 20 when it is assumed that R21=R22.

When the driving signal V1is supplied to the drive circuit30configured as described above, the series compensator38compares the driving signal V1and the output signal V2for which phase lead compensation has been made and outputs the signal V3set to a level in accordance with an error thereof. The switching voltage amplifier circuit33compares the triangular wave and the signal V3to perform pulse width modulation and voltage amplification. An output signal of the switching voltage amplifier circuit33is supplied to the piezoelectric head10via the filter34.

Here, the control target, that is, the transfer function P(s) from the signal V5of the switching voltage amplifier circuit33to the output V2of the filter34is represented by (Equation 6), as described above. (Equation 6) has no first-order term concerning s in the denominator and has resonance characteristics and thus, lacks stability.

Therefore, the stabilization compensator35provides the first-order term concerning s to the denominator of the transfer function P(s) of the control target (corresponding to (Equation 7)) by providing derivative characteristics and configures a closed loop (corresponding to (Equation 8)) to stabilize the control target.

However, in phase characteristics of the transfer function Q(s) of the control target stabilized by the stabilization compensator35, there is almost no phase margin (a margin of phase delay with respect to −180 degrees) near 1 [MHz] when the load is 0.5 [μF]. Thus, there is a possibility of oscillation if feedback is received as it is.

In consideration of the fact that Q(s) is a second-order lag system, the first and second phase lead compensators36and37make second-order phase lead compensation for the output V2. Thus, negative feedback is received with stability even if the load fluctuates.

FIG. 11is a diagram exemplifying drive characteristics of the drive circuit30. Even if the load capacity fluctuates between 0.1 and 0.5 [μF], the output (the voltage of the piezoelectric element11) of the filter34with respect to the target value remains almost the same, showing excellent low-sensitivity characteristics.

Second Exemplary Embodiment

Next, a second exemplary embodiment of the invention will be described. The same reference numerals are attached to the same circuits as those in the first exemplary embodiment and different aspects will be mainly described.

Excellent output of the filter34was obtained with respect to the target value inFIG. 11, but as is evident in characteristics near 20 [μsec], transitive-tracking properties of the target value is somewhat insufficient. Thus, an ink jet printer according to the second exemplary embodiment has, in addition to the low-sensitivity characteristics, a drive circuit30A whose transitive-tracking properties have been improved.

FIG. 12is a circuit diagram showing the configuration of the drive circuit30A.FIG. 13is a diagram showing transfer functions of each of circuits constituting the drive circuit30A.

The drive circuit30A has, in addition to the configuration shown inFIG. 5, a feed forward compensator39for making feed forward compensation to the input V5of the switching voltage amplifier circuit33from the input V1.

Feed Forward Compensator39

The feed forward compensator39has an operational amplifier IC5, resistors R61, R62and R63, and a capacitor C61. An inversion input terminal of the operational amplifier IC5is connected to the non-inversion input terminal of the operational amplifier IC4via the resistor R61. The resistor R61is connected in parallel to the resistor R63and the capacitor C61connected in series. A non-inversion input terminal of the operational amplifier IC5is grounded. An output terminal of the operational amplifier IC5is connected to the inversion input terminal of the operational amplifier IC5via the resistor R62and also to the inversion input terminal of the operational amplifier IC2.

A transfer function G(s) of the drive circuit30A from the input V1to the output V2of the filter34is given by Equation 21 below:

The first term in Equation 21 is transfer characteristic itself when there is no feed forward (FIG. 6) and a response to a target value is shown inFIG. 4. The second term shows an effect of a feed forward compensator D(s) and the response to the target value may be improved if D(s) has a high-frequency emphasis property.

Assume that the transfer characteristic from the input V1to the output V9of the feed forward compensator39is given by (Equation 22). However, Q(s) changes depending on load capacity and thus, Q(s) at maximum load (Cp=0.5 [μF]) is assumed.

FIG. 14is a diagram exemplifying frequency characteristics of the feed forward compensator D(s). The feed forward compensator D(s) has a high-frequency emphasis property. However, this property is complex and is thus approximated by a simple first-order high-frequency emphasis property for actually configuring a circuit.

FIG. 12shows an example using the operational amplifier IC5. Here, a transfer characteristic from the input V1to the output V9is given by Equation 23:

Equation 23 shows an inversion operation. Here, the stabilization compensator Q(s) inFIG. 12also shows an inversion operation and thus, the number of operational amplifiers is saved by inverting V9before addition by the operational amplifier IC2.

FIG. 15is a diagram exemplifying drive characteristics of the drive circuit30A. The output (the voltage of the operational amplifier11) of the filter34hardly changes even if the load capacity fluctuates between 0.1 and 0.5 [μF], showing excellent low-sensitivity characteristics. Further, while insufficient tracking of the target value is observed near 20 [μsec] inFIG. 11, insufficient tracking is improved inFIG. 15.

While the present invention has been illustrated and described with respect to some specific exemplary embodiments thereof, it should be understood that the present invention is by no means limited thereto and encompasses all changes and modifications which will become possible without departing from the spirit and scope of the invention.