RECEIVER SYSTEM AND METHOD FOR RECEIVER TESTING

A receiver system which may be implemented in an integrated circuit device and suitable for use in automotive radar systems such as collision avoidance systems, includes self test circuitry whereby a local oscillator test signal is generated by an on-board frequency multiplier and mixed in a down-conversion mixer with an RF test signal. The RF test signal is generated on the device by up-conversion of an externally generated low-frequency test signal with the local oscillator test signal. Baseband components may also be checked using test signals of suitable frequency divided down from the local oscillator test signal by a programmable frequency divider. This self test arrangement obviates any need for applying externally generated RF test signals to the IC device.

FIELD OF THE INVENTION

This invention relates to a receiver system and a method for receiver testing and has particular, though not exclusive, applicability to radar receivers for vehicles.

BACKGROUND OF THE INVENTION

Millimetre wave radio frequency (RF) systems are finding increasing application in active safety systems for vehicles such as adaptive cruise control and collision warning systems. An increasing demand for such systems has led to a corresponding interest in integrating these RF systems on silicon and/or compound semiconductor-based integrated circuits rather than using discrete components. Silicon integration provides the possibility of manufacturing larger volumes of such systems at lower cost compared with discrete component systems or system based on compound semiconductors. Millimetre wave frequencies are generally defined to be between around 30-300 GHz with 77 GHz being a typical operating frequency for an automotive radar system. A typical radar receiver generally comprises a heterodyne or homodyne receiver for down-converting the received high-frequency (RF) signal to an intermediate frequency (IF) by mixing the high-frequency signal with a locally-generated local oscillator (LO) signal. Down conversion (to frequencies of typically less than 100 MHz,) has the benefit that the signal at the intermediate frequency (or baseband) can be processed more easily.

Testing of millimetre wave systems however is difficult and expensive. Particularly in the case of systems operating at over 10 GHz, precision test fixtures and equipment have to be used which require maintenance and calibration. One known testing procedure mentioned in WO 2010007473 involves applying high-frequency probe signals to the receiver on the die to be tested and measuring the receivers response. This method is not very reliable as the high-frequency probe signals can be very sensitive to the characteristics of the transmission lines employed. An alternative known testing procedure is described in US 20120126821 which comprises a method of testing an RF integrated circuit incorporating an on-chip test circuit. High frequency test signals (greater than 10 GHz) are generated during a test mode using a voltage controlled oscillator (VCO) which is included in the on-chip test circuit. However, VCO's tend to be unstable. Reliability is a critical factor in automotive systems where a failure rate close to 0 ppm is required.

SUMMARY OF THE INVENTION

The present invention provides a receiver system, a method for testing a receiver system, a radar system and a vehicle as described in the accompanying claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now toFIG. 1an example of a receiver system is indicated at100and may comprise an integrated circuit101. The receiver system may include RF circuitry, baseband circuitry and a built in test circuitry. The receiver system in some embodiments may comprise a multichannel receiver system. In some embodiments, the integrated circuit101may comprise a package which may take any variety of forms such as for example, a plastic dual in-line package, ceramic dual in-line package, chip-scale package, lead-frame package or a ball grid array.

In some embodiments, the integrated circuit101may be implemented as a monolithic microwave integrated circuit (MMIC). In some embodiments, the integrated circuit may be fabricated using compound semiconductors, CMOS- or SiGe-BiCMOS technologies.

The integrated circuit101may be arranged to interface with a serial peripheral interface bus (SPI) which is asynchronous serial datalink operating in accordance with known techniques.

The integrated circuit101may be provided with an RF port102, a local oscillator (LO) port103and intermediate frequency (IF) port104and a test signal port105. The integrated circuit101may further comprise a down-conversion mixer106for mixing an RF signal received from an external source via the RF port102on line107with a local oscillator signal on line108down to a baseband signal on line109. In the case where the receiver system is configured as a multichannel receiver, more than one down-conversion mixers may be provided. The down-conversion mixer may comprise any type of active or passive mixing or modulation circuitry such as for example, Gilbert type mixers, resistive mixers or diode mixers.

The output of the down-conversion mixer on line109may be connected to a baseband module110whose output on line111may be connected to the IF port104. The baseband module110may comprise a first peak voltage detector112, a high pass filter113, an amplifier114, and a second peak voltage detector115. The first peak detector112may be used to measure the output voltage directly after down-conversion and also to guarantee functionality of the RF-path up to the IF signal of the down-converter106. The second peak detector115may then be used to measure and track functionality of the baseband chain components comprising the high pass filter113, and the amplifier114. The signal on line111may be taken via the IF port104to external circuitry for further processing.

In some embodiments, a local oscillator input line116may link the local oscillator port103with a frequency doubler117whose output may be fed to the LO input of the down-conversion mixer106on line108through a power detector118. In the case of a multichannel receiver system, the output of the frequency doubler117may be passed through a power splitter119and thence a series of “N” power detectors prior to application to the LO inputs of a series of down-conversion mixers. The frequency doubler117may comprise any conventional circuitry for performing this function which may employ for example, phase locked loop techniques or non-linear circuits and filters.

The power detector118may comprise any conventional power detection circuitry or can be identical to the peak detector design used for the peak voltage detectors112and115comprising the baseband circuitry110. Using the power detector118, the input power level at the LO port of the down-converter106can be measured.

The test signal input port105may be operably coupled to a switch120. An output of the switch may be operably coupled on line121to an input of an up-conversion mixer122. The up-conversion mixer may be arranged to mix a signal on line121with a local oscillator signal on line108to produce an up converted signal online123. The up-conversion mixer122may, for example, be a single-sideband mixer. As an alternative, a double sideband mixer may be used. In the latter case, a bandpass filter may be provided for filtering out any unwanted sideband. A second output of the switch120on line124may be operably coupled to an input of the baseband module110. The switch may be implemented using bipolar transistors or MOS transistors or other appropriate device. The switch120may be controlled by dedicated signals via a SPI. In one example these may be dedicated analogue control signals generated externally to the integrated circuit101. A first coupler124may be provided for coupling a signal on the output of the up-conversion mixer122to the RF input line107of the down-conversion mixer106. The first coupler124may comprise any type of conventional coupling device such as a directional coupler, for example. Preferably, the coupler124is one having extremely low losses so that noise performance of the integrated circuit101is not degraded.

A SPI clock125provides a reference signal to a frequency multiplier module126. An SPI clock may run typically within the range 1-100 MHz. In one embodiment, the frequency multiplier module126comprises a phase locked loop (PLL) configured as a frequency multiplier in accordance with conventional techniques. In an alternative embodiment, the frequency multiplier module106comprises a multiplied ring oscillator.

An output on line127from the frequency multiplier module126may be coupled into the local oscillator signal line116by means of a second coupler128. A third coupler129may be provided for coupling the output of the frequency multiplier module126to a programmable frequency divider/multiplier module130. The second and third couplers128,129may each comprise any type of conventional coupling or power splitting device such as a directional coupler, rat race coupler, magic tee coupler. In the example where the frequency multiplier module126comprises a multiplied ring oscillator, an output thereof may be operably coupled to the programmable frequency divider/multiplier130on line131. An output of the programmable frequency divider/multiplier on line132may, by the action of the switch120, be operably coupled via line124to an input of the baseband module110.

The receiver system100comprising the integrated circuit101is therefore provided with a built-in test circuitry which only requires, in one embodiment, the application of a comparatively low (5-10 MHz) externally-generated low frequency test signal at the test signal input port105. In a manner to be described in more detail below, the low frequency test input may be up-converted (to 77 GHz in one example) to provide an RF test signal for enabling the complete RF path to be characterised and tracked. Local oscillator test signals (of 76 GHz in one typical example or 38 GHz in another example\) may be generated on-board utilising the SPI clock125and frequency multiplier module126. In addition to providing a LO test signal to the down-conversion mixer106, the local oscillator test signals may be used in the up-conversion mixer122to up-convert the low frequency test signal to produce an RF test signal. Further, baseband circuitry may be tested using the low frequency test signal applied via the test signal input port105or by switching in output signals of various frequencies from the programmable frequency divider/multiplier module130. Signals of different frequencies may be useful for testing filter stages of the baseband module110for example. On-board couplers124,128permit the coupling of the on-board generated test signals into the receiver RF and LO paths.

Reference will now be made toFIG. 2where there is shown a schematic block diagram illustrating how the receiver system100ofFIG. 1may be implemented in a radar system of a vehicle. A vehicle200is fitted with a radar system201which, in one example, supports a collision warning system for the vehicle. Typically, in a collision warning system, electromagnetic waves of 77 GHz which are transmitted by the radar system may be reflected from objects ahead, to the side or to the rear of the vehicle200. Reflected signals which are received by the radar system may be used to detect objects in the vicinity of the vehicle and to trigger a warning of an imminent collision. In some examples, a frequency modulated continuous-wave signal is transmitted whose reflected signal from a target permits the radar system to determine range and range rate of the target. The vehicle-mounted radar system201is shown in schematic form inFIG. 2and may comprise a radar front end module203which may be operably coupled to a microcontroller unit MCU204. The radar front end module203and the MCU204may be powered by the vehicle's battery on line205. The MCU204may be connected on an output line206to the vehicle's CAN bus. The radar front end module203may comprise a transmitter207and a receiver system208such as that described with reference toFIG. 1, for example. A local oscillator module209may be connected to both the transmitter module203and the receiver system208. The receiver system208may include the RF circuitry, test circuitry and baseband circuitry as described above with reference toFIG. 1. The receiver system208also comprises at least one RF input port210, a local oscillator port211an IF port212and a test signal input port213. In some examples, the receiver system208may be a multichannel receiver system which receives input RF signals from one or more antennas209,214. An array of antennas is useful, for example, for determining of an angle of arrival of a received radar signal by comparing phase differences between signals at the antennas thereby enabling computation of an angular position of a target. The MCU204may provide power and control signals to the radar front end module203. The MCU204may also be arranged to supply a low frequency test signal of between 5-10 MHz to the test signal input port213of the receiver system208. The MCU204may program one of its pulse width modulated (PWM) outputs to provide the required test signal with predetermined amplitude, frequency and phase.

Referring back toFIG. 1, operation of a receiver system in a target detection mode will now be described. A 77 GHz signal is received at the RF port102and a local oscillator signal is received at local oscillator port103. In this example, there is no test signal applied to the test signal input port105and the programmable frequency divider/multiplier130and the frequency multiplier module126may be disabled. The local oscillator signal may be set at 76 GHz (in which case the frequency doubler117may also be disabled) and applied to the local oscillator input of the down-conversion mixer106along with the received RF signal on line107. Alternatively, the local oscillator signal may be set at 38 GHz and doubled by the frequency doubler117so that a 76 GHz appears at the local oscillator input of the down-conversion mixer106. The down-conversion mixer106, as is conventional, produces a down-converted intermediate frequency signal typically in the range from DC to 200 MHz on line109which is applied to the baseband module110. The baseband module110may operate as follows. The high pass filter113may be used to typically suppress the DC signal and the flicker noise of the down-converted signal. By this, the filter113prevents the following gain stage provided by the amplifier114from compression and DC-level offset issues. The amplifier114may be typically designed a variable gain amplifier (VGA) whose gain may be programmable via the SPI125interface. Depending on the input signal level at the RF port102, the baseband gain may be adjusted via the amplifier114to optimize the signal level at the IF port104for any following analog to digital conversion.

The resulting (analogue) baseband signal on line111may be fed from the IF port104to an external module for further processing. The further processing may include signal amplitude measurement using an analog to digital converter. The typical frequency range of the signals appearing at the IF port104is from DC up to 10 MHz.

A self-test mode of operation of a receiver system will now be described with reference toFIGS. 1 and 2and toFIG. 3which is a simplified flowchart of a method for testing a receiver. A method300for testing the RF path of a receiver commences at301where the frequency multiplier126and programmable frequency divider/multiplier130are enabled. An enabling and programming signal may be provided by the MCU104. At302, a 38 GHz signal is generated in the frequency multiplier126and coupled by way of the second coupler128to the local oscillator input line116. At303, the 38 GHz signal is multiplied in the frequency doubler117to produce a 76 GHz local oscillator test signal on line108. At304, the up-conversion mixer122is enabled and a 10 MHz test signal is applied to the test signal input port105and the switch120is adjusted so that the 10 MHz test signal is applied to an input of the up-conversion mixer122. At305, the 76 GHz local oscillator test signal and 10 MHz test signal are mixed in the up-conversion mixer so that the 10 MHz test signal is up-converted into the RF domain to produce an RF test signal of 76 GHz+10 MHz or 76 GHz-10 MHz, for example. At306the RF test signal is coupled by way of the first coupler124to the RF input of the down-conversion mixer106. At307, the RF test signal is mixed with the local oscillator test signal in the down-conversion mixer106to produce on line109a baseband signal. Using a homodyne receiver architecture and with a test signal at 10 MHz, the down-conversion mixer generates a baseband signal which is identical to the test signal e.g. 10 MHz. The signal subsequently appearing at the IF port104may be analysed externally in order to check the operation of the RF and baseband circuitry of the receiver system.

Operation of the baseband circuitry, particularly filters and amplifiers may be checked by operating the switch120, at308, so that the low-frequency test signal is diverted away from the up-conversion mixer122and to any interface in the of the baseband chain, for example, module110instead. Low-frequency voltage swing measurements may then be made (at309) at any interface between the components comprising the baseband module110and at the IF port104. Measurements made at the outputs of the various baseband module components may be done by way of suitable connections or probes (not shown). As an example, signals to be measured can be taken from pads conveniently located and be converted by analogue to digital converters or read by the SPI. If any adjustments are found to be necessary as a result of the measurement and monitoring processes, a control and adjustment loop may be provided externally to the receiver. Such a loop may be implemented in a microcontroller.

An alternative method of testing baseband components at various different frequencies may be carried out by employing the frequency multiplier126and programmable frequency divider/multiplier130. At310output signals from the frequency multiplier126may be coupled by way of the third coupler129to the programmable frequency divider/multiplier130which may be programmed to produce low-frequency test signals of predetermined frequencies for application to the baseband components. In some examples, the frequency range of the test signals is typically the same as the operating frequencies of the receiver IF signals.

In an alternative arrangement, the direct link131between the frequency multiplier126and the programmable frequency divider/multiplier130may be employed to transfer a signal of an appropriate frequency, taken from an intermediate stage of the frequency multiplication chain of the frequency multiplier126to the programmable frequency divider/multiplier130.

The above method has the advantage of being able to monitor an integrated circuit receiver's functionality and performance under simulated operational conditions, that is, with a local oscillator applied. No high-frequency signals (greater than between 5-10 MHz) are required to be input to the receiver during a test procedure. All high-frequency signals are generated in the receiver itself using frequency multiplication and up conversion techniques. The above method or any part of it may be carried out on a receiver during production test or even during normal operation of the receiver. Normally, the up conversion mixer122is disabled. However, it is possible to enable the up-conversion mixer during normal operation and detect this (known) test signal at the IF port104for example.

In one embodiment, the frequency multiplier126ofFIG. 1may comprise a non-linear circuit400(seeFIG. 4) for generating harmonics of a reference frequency. InFIG. 4, a reference frequency may be a clock signal401provided by a serial peripheral interface (SPI).The frequency multiplier circuit400may comprise a plurality of cascaded multiplier, filter and gain stages402and may be based on harmonic multiplication factors, N (where N may be typically 2 or 3). Undesired frequencies may be filtered out or at least suppressed to produce a signal at a desired frequency on line403.

In another embodiment, the frequency multiplier126ofFIG. 1may comprise a phase locked loop (seeFIG. 5). In this example, a clock signal on line501, supplied via a serial peripheral interface (SPI)502, may act as a reference frequency for a phase detector503and may be applied to one input thereof. A programmable frequency divider504may comprise a part of a feedback loop between a second input of the phase detector503and a voltage controlled oscillator (VCO)505. A low pass filter506may be operably coupled between an output of the phase detector503and an input of the VCO505. The programmable frequency divider (which may be controlled by a signal on the SPI502) acts to make the frequency of the output signal from the PLL500on line507a multiple of the reference frequency (that is, the SPI clock). One or more amplifier stages508,509may be added to the output of the VCO505.

The invention may also be implemented in a computer program for running on a computer system, at least including code portions for performing steps of a method according to the invention when run on a programmable apparatus, such as a computer system or enabling a programmable apparatus to perform functions of a device or system according to the invention.

As an example, a tangible computer program product may be provided having executable code stored therein to perform a method for testing a receiver, the method comprising, generating in the receiver a local oscillator test signal using a frequency multiplier and coupling the local oscillator test signal to a first input of a down-conversion mixer receiving a test signal at an input port of the receiver, up-converting the received test signal with the local oscillator test signal in an up-conversion mixer to produce an RF test signal, coupling the RF test signal to a second input of the down-conversion mixer, and mixing the RF test and local oscillator test signals in the down-conversion mixer to produce a baseband signal at an output port of the receiver.

The computer program may be stored internally on computer readable storage medium or transmitted to the computer system via a computer readable transmission medium. All or some of the computer program may be provided on computer readable media permanently, removably or remotely coupled to an information processing system. The computer readable media may include, for example and without limitation, any number of the following: magnetic storage media including disk and tape storage media; optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memories; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, etc.; and data transmission media including computer networks, point-to-point telecommunication equipment, and carrier wave transmission media, just to name a few.

Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. For example, the components comprising the baseband module110as illustrated inFIG. 1comprise the basic typical building blocks used in baseband circuitry. Other configurations of baseband circuitry are possible and need not necessarily be limited to the particular choice and arrangement of components illustrated, that is, peak voltage detectors, a filter and an amplifier. Further, the SPI clock125may be replaced with some other suitable clock generator

Also for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. Further, the entire functionality of the modules shown inFIG. 1may be implemented in an integrated circuit That is to say that a receiver system may be implemented in an integrated circuit. Such an integrated circuit may be a package containing one or more dies. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner. For example an integrated circuit device may comprise one or more dies in a single package with electronic components provided on the dies that form the modules and which are connectable to other components outside the package through suitable connections such as pins of the package and bondwires between the pins and the dies.