MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a magnetic memory device may include forming a bottom electrode layer on a substrate; forming a block structure on the bottom electrode layer; performing a first deposition process on the bottom electrode layer to form a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer on the bottom electrode layer; performing a second deposition process on the free magnetic layer to form a capping layer on the free magnetic layer; and performing an etching process after forming a hard mask on the capping layer to form magnetic tunnel junction patterns. The first deposition process may include irradiating a first beam toward the substrate. The second deposition process may include irradiating a second beam toward the substrate. The second beam may have a greater angle than the first beam with respect to a normal line perpendicular to an upper surface of the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0013755, filed on Feb. 1, 2023, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The present disclosure relates to a magnetic memory device including a magnetic tunnel junction and a method of manufacturing the same.

In general, a magnetic memory device may include a magnetic tunnel junction (MTJ) pattern. The magnetic tunnel junction pattern may include two magnetic layers and an insulating layer interposed therebetween. Resistance of the magnetic tunnel junction pattern varies depending on magnetization directions of the magnetic layers. For example, the magnetic tunnel junction pattern may have a high resistance value when magnetization directions of the magnetic layers are anti-parallel to each other and the magnetic tunnel junction pattern may have a low resistance value when magnetization directions of the magnetic layers are parallel to each other. Data may be stored into and/or read out from the magnetic tunnel junction pattern by using a difference between these resistance values.

Highly integrated and/or low-power magnetic memory devices have been increasingly demanded with the development of an electronic industry. Thus, research is being conducted to satisfy these demands.

SUMMARY

The present disclosure relates to a magnetic memory device with improved manufacturing process efficiency and/or a method of manufacturing the same.

A method of manufacturing a magnetic memory device according to some embodiments of the present disclosure may include forming a bottom electrode layer on a substrate; forming a block structure on the bottom electrode layer; performing a first deposition process on the bottom electrode layer to form a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer on the bottom electrode layer; performing a second deposition process on the free magnetic layer to form a capping layer on the free magnetic layer; and performing an etching process after forming a hard mask on the capping layer to form magnetic tunnel junction patterns. The first deposition process may include irradiating a first beam toward the substrate and the first beam may form a first angle with a normal line perpendicular to an upper surface of the substrate. The second deposition process may include irradiating a second beam toward the substrate and the second beam may form a second angle with the normal line. The second angle may be greater than the first angle.

A method of manufacturing a magnetic memory device according to some embodiments of the present disclosure may include providing a substrate including a block structure; performing a first deposition process including irradiating a first beam on the substrate to form a first deposition layer; and performing a second deposition process including irradiating a second beam on the first deposition layer to form a second deposition layer. The first beam may form a first angle with respect to a normal line perpendicular to an upper surface of the substrate. The second beam may form a second angle with respect to the normal line. The second angle may be greater than the first angle.

A method of manufacturing a magnetic memory device according to some embodiments of the present disclosure may include forming a lower interlayer insulating layer including lower wirings on a substrate, the substrate including a first region, a second region, and a third region neighboring in a first direction parallel to the substrate; forming a first interlayer insulating layer including lower contact plugs on the lower interlayer insulating layer; forming a bottom electrode layer on the lower interlayer insulating layer; forming a block structure on the bottom electrode layer, the block structure being formed on the third region of the substrate; performing a first deposition process on the bottom electrode layer, the first deposition process including irradiating a first beam having a first angle with a normal line perpendicular to an upper surface of the substrate, the first deposition process including forming a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer; performing a second deposition process on the free magnetic layer, the second deposition process including irradiating a second beam having a second angle with the normal line, the second deposition process forming a capping layer; performing a planarization process after forming a hard mask on the capping layer; performing an etching process on the hard mask to form magnetic tunnel junction patterns; and forming an upper wiring on the magnetic tunnel junction patterns. The second angle may be greater than the first angle. A thickness of the capping layer on the first region of the substrate may be greater than a thickness of the capping layer on the second region of the substrate.

DETAILED DESCRIPTION

Hereinafter, the present disclosure will be described in detail by describing embodiments of the present disclosure with reference to the accompanying drawings.

FIG.1is a circuit diagram illustrating a unit memory cell of a magnetic memory device according to some embodiments of the present disclosure.

Referring toFIG.1, a unit memory cell MC may include a memory element ME and a selection element SE. The memory element ME and the selection element SE may be electrically connected to each other in series. The memory element ME may be connected between a bit line BL and the selection element SE. The selection element SE may be connected between the memory element ME and a source line SCL and be controlled by a word line WL. The selection element SE may include, for example, a bipolar transistor or a MOS field effect transistor.

The memory element ME may include a magnetic tunnel junction (MTJ), and the magnetic tunnel junction MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBR between the first and second magnetic patterns MP1and MP2. One of the first and second magnetic patterns MP1and MP2may be a pinned magnetic pattern whose magnetization direction is fixed in a single direction regardless of an external magnetic field under ordinary use environment. The other of the first and second magnetic patterns MP1and MP2may be a free magnetic pattern whose magnetization direction is changed due to an external magnetic field between two stable magnetization directions. The magnetic tunnel junction pattern MTJ may have an electrical resistance whose value is much greater in case that the magnetization directions of the pinned and free magnetic patterns are anti-parallel to each other than in case that the magnetization directions of the pinned and free magnetic patterns are parallel to each other. That is, the electrical resistance of the magnetic tunnel junction pattern MTJ may be controlled by changing the magnetization direction of the free magnetic pattern. Therefore, the memory element ME may use the difference in electrical resistance, depending on the magnetization directions of the pinned and free magnetic patterns, as a mechanism that may cause the unit memory cell MC to store data therein.

FIG.2is a cross-sectional view of a magnetic memory device according to some embodiments of the present disclosure.

Referring toFIG.2, a first insulating interlayer110may be disposed on a substrate100, and lower contact plugs115may be disposed in the first insulating interlayer110. The substrate100may be a semiconductor substrate including silicon, silicon on insulator (SOI), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), or the like. The first interlayer insulating layer110may include, for example, oxide, nitride, and/or oxynitride.

Each of the lower contact plugs115may pass through and/or penetrate the first interlayer dielectric layer110and may electrically connect with the substrate100. A selection element (see SE ofFIG.1) may be disposed in the substrate100, and the selection element may be, for example, a field effect transistor. Each of the lower contact plugs115may be electrically coupled to one terminal (e.g., a source/drain terminal) of a corresponding one of the selection elements. The lower contact plug115may include at least one of doped semiconductor materials (e.g., doped silicon), metals (e.g., tungsten, titanium, and/or tantalum), metal-semiconductor compounds (e.g., metal silicide), and conductive metal nitride (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride).

Bottom electrodes BE may be respectively disposed on the lower contact plugs115. A first magnetic tunnel junction pattern MTJ1and a first top electrode TE1may be disposed on a first bottom electrode BE among the bottom electrodes, and a second magnetic tunnel junction pattern MTJ2and a second top electrode TE2may be disposed on a second bottom electrode BE among the bottom electrodes BE. The first bottom electrode BE, the first magnetic tunnel junction pattern MTJ1, and the first top electrode TE1may be sequentially stacked in a first direction D1 perpendicular to an upper surface100U of the substrate100. The second bottom electrode BE, the second magnetic tunnel junction pattern MTJ2, and the second top electrode TE2may be sequentially stacked in the first direction D1. The first magnetic tunnel junction pattern MTJ1and the second magnetic tunnel junction pattern MTJ2may be spaced apart from each other in a second direction D2 parallel to the upper surface100U of the substrate100. The first magnetic tunnel junction pattern MTJ1may be disposed between the first bottom electrode BE and the first top electrode TE1, and the second magnetic tunnel junction pattern MTJ2may be disposed between the second bottom electrode BE and the second top electrode TE2. The bottom electrodes BE may be electrically connected to the lower contact plugs115, respectively. The bottom electrodes BE may include, for example, conductive metal nitride (e.g., titanium nitride or tantalum nitride). The top electrode TE may include at least one of a metal (e.g., Ta, W, Ru, Ir, etc.) and a conductive metal nitride (e.g., TiN).

The first magnetic tunnel junction pattern MTJ1may include a pinned magnetic pattern130, a free magnetic pattern140, and a tunnel barrier pattern TBR between the pinned magnetic pattern130and the free magnetic pattern140. According to some embodiments, the pinned magnetic pattern130may be disposed between the first bottom electrode BE and the tunnel barrier pattern TBR, and the free magnetic pattern140may be disposed between the first top electrode TE1and the tunnel barrier pattern TBR. The first magnetic tunnel junction pattern MTJ1may further include a seed pattern120between the first bottom electrode BE and the pinned magnetic pattern130, a first capping pattern150A between the first top electrode TE1and the free magnetic pattern140, and a first upper capping pattern160A between the first capping pattern150A and the first top electrode TE1.

The seed pattern120may include a material that helps crystal growth of the pinned magnetic pattern130. The seed pattern120may include, for example, at least one of chromium (Cr), iridium (Ir), and ruthenium (Ru).

The pinned magnetic pattern130may have a magnetization direction130MD fixed in one direction. The magnetization direction130MD of the pinned magnetic pattern130may be perpendicular to an interface between the tunnel barrier pattern TBR and the free magnetic pattern140. The pinned magnetic pattern130may include a magnetic element. The pinned magnetic pattern130may include at least one of iron (Fe), cobalt (Co), and nickel (Ni). For example, the pinned magnetic pattern130may include at least one of an intrinsic perpendicular magnetic material and an extrinsic perpendicular magnetic material. The intrinsic perpendicular magnetic material may include a material having perpendicular magnetization characteristics even when there is no external factor. The intrinsic perpendicular magnetic material may include at least one of i) a perpendicular magnetic material (e.g., CoFeTb, CoFeGd, CoFeDy), ii) a perpendicular magnetic material having an L10structure, iii) CoPt having a hexagonal close packed lattice structure, and iv) a vertical magnetic structure. The perpendicular magnetic material having the L10structure may include at least one of L10structure FePt, L10structure FePd, L10structure CoPd, or L10structure CoPt. The perpendicular magnetic structure may include magnetic layers and non-magnetic layers that are alternately and repeatedly stacked. For example, the perpendicular magnetic structure may include at least one of (Co/Pt)n, (CoFe/Pt)n, (CoFe/Pd)n, (Co/Pd)n, (Co/Ni)n, (CoNi/Pt)n, (CoCr/Pt)n, or (CoCr/Pd)n (“n” is the number of stacking). The extrinsic perpendicular magnetic material may include a material having intrinsic horizontal magnetization characteristics and perpendicular magnetization characteristics due to an external factor. For example, the extrinsic perpendicular magnetic material may have the perpendicular magnetization characteristic due to magnetic anisotropy induced by junction of the pinned magnetic pattern130and the tunnel barrier pattern TBR. The extrinsic perpendicular magnetic material may include, for example, CoFeB. The pinned magnetic pattern130may include a Co-based Heusler alloy.

The tunnel barrier pattern TBR may include a metal oxide layer. The tunnel barrier pattern TBR may include at least one of, for example, a magnesium (Mg) oxide layer, a titanium (Ti) oxide layer, an aluminum (Al) oxide layer, a magnesium-zinc (Mg—Zn) oxide layer, or a magnesium-boron (Mg—B) oxide layer.

The free magnetic pattern140may have a magnetization direction140MD changeable parallel to or anti-parallel to the magnetization direction130MD of the pinned magnetic pattern130. The magnetization direction140MD of the free magnetic pattern140may be perpendicular to an interface between the tunnel barrier pattern TBR and the free magnetic pattern140.

The free magnetic pattern140may include a magnetic element. The first free magnetic pattern142may include at least one of iron (Fe), cobalt (Co), and nickel (Ni). For example, the free magnetic pattern140may include cobalt-iron (CoFe). As another example, the free magnetic pattern140may include at least one of the perpendicular magnetic material (e.g., CoFeTb, CoFeGd, CoFeDy), the perpendicular magnetic material having the L10structure, the CoPt having the hexagonal close packed lattice structure, and the vertical magnetic structure. The free magnetic pattern140may include a magnetic material having perpendicular magnetization characteristics due to magnetic anisotropy induced by junction of the free magnetic pattern140and the tunnel barrier pattern TBR. For example, the free magnetic pattern140may include cobalt-iron-boron (CoFeB). The free magnetic pattern140may include a Co-based Heusler alloy.

The first capping pattern150A may be disposed between the free magnetic pattern140and the first upper capping pattern160A. The first capping pattern150A may be used to enhance vertical anisotropy of the free magnetic pattern140. The first capping pattern150A may include a first non-magnetic metal. The first capping pattern150A may further include oxygen. For example, the first nonmagnetic metal may include tantalum (Ta).

The first upper capping pattern160A may include a second non-magnetic metal. The second non-magnetic metal may be different from the first non-magnetic metal. For example, the second non-magnetic metal may include at least one of molybdenum (Mo), tungsten (W), chromium (Cr), rhenium (Re), and manganese (Mn). According to some embodiments, the first upper capping pattern160A may further include oxygen. In this case, the first upper capping pattern160A may include an oxide of the second nonmagnetic metal.

The second magnetic tunnel junction pattern MTJ2may include a pinned magnetic pattern130, a free magnetic pattern140, and a tunnel barrier pattern TBR between the pinned magnetic pattern130and the free magnetic pattern140. The second magnetic tunnel junction pattern MTJ2may further include a seed pattern120between the second bottom electrode BE and the pinned magnetic pattern130, a second capping pattern150B between the second top electrode TE2and the free magnetic pattern140, and a second upper capping pattern160B between the second capping pattern150B and the second top electrode TE2. A thickness T1of the first capping pattern150A may be greater than a thickness T2of the second capping pattern150B.

In the first and second magnetic tunnel junction patterns MTJ1and MTJ2, the first capping pattern150A and the second capping pattern150B that are in contact with the free magnetic pattern140may have different thicknesses. Accordingly, characteristics of the first magnetic tunnel junction pattern MTJ1and the second magnetic tunnel junction pattern MTJ2may be different.

A second interlayer insulating layer180may be disposed on the first interlayer insulating layer110, and may cover side surfaces of the bottom electrodes BE, first and second magnetic tunnel junction patterns MTJ1and MTJ2, and first and second top electrodes TE1and TE2. The second interlayer insulating layer180may include, for example, oxide, nitride, and/or oxynitride.

An upper wiring200may be disposed on the second interlayer insulating layer180and may be connected to the first and second top electrodes TE1and TE2. The upper wiring200may be connected to the first and second magnetic tunnel junction patterns MTJ1and MTJ2through the first and second top electrodes TE1and TE2, and may function as a bit line (BL ofFIG.1). The upper wiring200may include at least one of a metal (e.g., copper) and a conductive metal nitride.

FIG.3is a plan view of a magnetic memory device according to some embodiments of the present disclosure, andFIG.4is a cross-sectional view taken along line I-I′ ofFIG.3. For simplicity of description, descriptions overlapping those of the magnetic memory device described with reference toFIGS.1and2will be omitted.

Referring toFIGS.3and4, lower wirings102and lower contacts104may be disposed on a substrate100. The lower wirings102may be spaced apart from an upper surface100U of the substrate100in a first direction D1 perpendicular to the upper surface100U of the substrate100. The lower contacts104may be disposed between the substrate100and the lower wirings102, and each of the lower wirings102may be electrically connected to the substrate100through a corresponding one of the lower contacts104. The lower wirings102and the lower contacts104may include metal (e.g., copper).

Select elements (SE inFIG.1) may be disposed in the substrate100. The selection elements may be, for example, field effect transistors. Each of the lower wirings102may be electrically connected to a terminal (e.g., a source/drain terminal) of a corresponding one of the selection elements through a corresponding lower contact104.

A lower interlayer insulating layer106may be disposed on the substrate100and may cover the lower wirings102and the lower contacts104. Upper surfaces of uppermost lower wirings102among the lower wirings102may be coplanar with an upper surface of the lower interlayer insulating layer106. The upper surfaces of the uppermost lower wirings102may be positioned at substantially the same height as the upper surface of the lower interlayer insulating layer106. In this specification, a height means a distance measured in the first direction D1 from the upper surface100U of the substrate100. The lower interlayer insulating layer106may include, for example, oxide, nitride, and/or oxynitride.

A first interlayer insulating layer110may be disposed on the lower interlayer insulating layer106and may cover the upper surfaces of the uppermost lower wirings102.

A plurality of lower contact plugs115may be disposed in the first interlayer insulating layer110. The plurality of lower contact plugs115may be spaced apart from each other in a second direction D2 and a third direction D3 parallel to the upper surface110U of the substrate100and crossing the second direction D2. Each of the plurality of lower contact plugs115may pass through the first interlayer insulating layer110and be connected to a corresponding lower wiring102among the lower wirings102. Each of the plurality of lower contact plugs115may be electrically connected to a corresponding one terminal (e.g., a source/drain terminal) of the selection elements through the corresponding lower wiring102.

A plurality of data storage patterns DS may be disposed on the first interlayer insulating layer110and may be spaced apart from each other in the second direction D2 and the third direction D3. The plurality of data storage patterns DS may be respectively disposed on the plurality of lower contact plugs115and may be respectively connected to the plurality of lower contact plugs115.

The plurality of data storage patterns DS may include a first data storage pattern DS1and a second data storage pattern DS2. The first data storage pattern DS1may include a first bottom electrode BE, a first magnetic tunnel junction pattern MTJ1, and a first top electrode TE1sequentially stacked on a corresponding lower contact plug115. The second data storage pattern DS2may include a second bottom electrode BE, a second magnetic tunnel junction pattern MTJ2, and a second top electrode TE2sequentially stacked on a corresponding lower contact plug115. The first bottom electrode BE, the first magnetic tunnel junction pattern MTJ1, and the first top electrode TE1may be substantially the same as the first bottom electrode BE, the first magnetic tunnel junction pattern MTJ1, and the first top electrode TE1described with reference toFIG.2. The second bottom electrode BE, the second magnetic tunnel junction pattern MTJ2, and the second top electrode TE2may substantially the same as the second bottom electrode BE, the second magnetic tunnel junction pattern MTJ2, and the second top electrode TE2described with reference toFIG.2.

According to some embodiments, an upper surface of the first interlayer insulating layer110may be recessed toward the substrate100between the plurality of data storage patterns DS. A protective insulating layer170may surround each side surface of the plurality of data storage patterns DS. The protective insulating layer170may cover side surfaces of the bottom electrode BE, first and second magnetic tunnel junction patterns MTJ1and MTJ2, and first and second top electrodes TE1and TE2, and may surround the side surfaces of the bottom electrode BE, first and second magnetic tunnel junction patterns MTJ1and MTJ2, and first and second top electrodes TE1and TE2when viewed in a plan view. The protective insulating layer170may extend from each side surface of the plurality of data storage patterns DS onto a recessed upper surface110RU of the first interlayer insulating layer110. The protective insulating layer170may conformally cover the recessed upper surface110RU of the first interlayer insulating layer110. The protective insulating layer170may include nitride (e.g., silicon nitride).

A second interlayer insulating layer180may be disposed on the first interlayer insulating layer110and may cover the plurality of data storage patterns DS. The protective insulating layer170may be interposed between each side surface of the plurality of data storage patterns DS and the second interlayer insulating layer180, and may extend between the recessed upper surface110RU of the first interlayer insulating layer110and the second interlayer insulating layer180.

A plurality of upper wirings200may be disposed on the second interlayer insulating layer180. The plurality of upper wirings200may extend in the second direction D2 and may be spaced apart from each other in the third direction D3. Each of the plurality of upper wirings200may be connected to data storage patterns DS spaced apart from each other in the second direction D2 among the plurality of data storage patterns DS.

FIGS.5,6, and8to13are views illustrating a method of manufacturing a magnetic memory device according to some embodiments of the present disclosure, and are cross-sectional views corresponding to line I-I′ ofFIG.3.FIGS.7A and7Bare schematic diagrams for illustrating a method of manufacturing a magnetic memory device according to some embodiments of the present disclosure. For simplicity of description, descriptions overlapping those of the magnetic memory device described with reference toFIGS.1to4will be omitted.

Referring toFIG.5, a substrate100may be provided. Selection elements (SE inFIG.1) may be formed in the substrate100, and lower wirings102and lower contacts104may be formed on the substrate100. Each of the lower wirings102may be electrically connected to one terminal (e.g., a source/drain terminal) of a corresponding one of the selection elements through a corresponding one of the lower contacts104. The substrate100may include a first region R1, a second region R2, and a third region R3neighboring in a second direction D2. The second region R2may be disposed between the first region R1and the third region R3. The lower wirings102and the lower contacts104may be formed on the first region R1and the second region R2of the substrate100. A lower interlayer insulating layer106may be formed on the substrate100to cover the lower wirings102and the lower contacts104. Upper surfaces of uppermost lower wirings102among the lower wirings102may be coplanar with an upper surface of the lower interlayer insulating layer106.

A first interlayer insulating layer110may be formed on the lower interlayer insulating layer106, and a plurality of lower contact plugs115may be formed in the first interlayer insulating layer110. Each of the plurality of lower contact plugs115may pass through the first interlayer insulating layer110and be connected to a corresponding lower wiring102among the lower wirings102. Forming the plurality of lower contact plugs115may include, for example, forming lower contact holes penetrating the first interlayer insulating layer110, forming a lower contact layer filling the lower contact holes on the first interlayer insulating layer110, and planarizing the lower contact layer until an upper surface of the first interlayer insulating layer110is exposed.

A bottom electrode layer BEL may be formed on the first interlayer insulating layer110. For example, the bottom electrode layer BEL may be formed through sputtering, chemical vapor deposition, or atomic layer deposition.

Referring toFIG.6, an etch stop layer SL may be formed on the bottom electrode layer BEL. The etch stop layer SL may cover an upper surface of the bottom electrode layer BEL. A block structure300may be formed on the etch stop layer SL. The block structure300may be formed on the third region R3of the substrate100. The block structure300may have a shape of a wall or a pillar extending in the first direction D1. For example, the block structure300may include silicon oxide.

Prior to describing a manufacturing method to be described later, a schematic diagram for helping understanding of the deposition process will be first described. Referring toFIGS.7A and7B, a deposition target10maybe provided. The deposition target10may include a first part P1, a second part P2, and a third part P3adjacent to each other. The second part P2may be disposed between the first part P1and the third part P3. A deposition impediment20maybe provided on the third part P3of the deposition target10.

A first beam B1may be irradiated onto the deposition target10to form a first angle A1with respect to a normal line perpendicular to an upper surface of the deposition target10. Due to the deposition impediment20, the first beam B1may be directly irradiated more on the first part P1and the second part P2than on the third part P3of the deposition target10. Therefore, when the first beam B1is irradiated, an irradiated material may be deposited more concentrated on the first part P1and the second part P2than on the third part P3of the deposition target10.

A second beam B2may be irradiated onto the deposition target10to form a second angle A2with respect to the normal line. In this case, the second angle A2may be greater than the first angle A1. Due to the interference of the deposition impediment20, the second beam B2may be irradiated more on the first part P1than the second part P2and the third part P3of the deposition target10. Therefore, when the second beam B2is irradiated, the irradiated material may be deposited more on the first part P1than to the third part P3and the second part P2of the deposition target10. The irradiation angle of the beam to the deposition target10maybe adjusted to have different thicknesses for each part.

As the first angle A1and the second angle A2are smaller, deposition may be performed in a wider area, and as the first angle A1and the second angle A2are larger, the deposition is performed in a narrower area. The deposition area may be adjusted by adjusting the irradiation angle and a height of the deposition impediment20.

Referring toFIG.8, the etch stop layer SL may be etched to form an etch stop pattern310. The etch stop pattern310may be formed between the block structure300and the bottom electrode layer BEL. The etch stop pattern310may expose the bottom electrode layer BEL in a portion where the block structure300is not formed. A first deposition process may be performed on the bottom electrode layer BEL. The first deposition process may include irradiating a first beam B1. The first beam B1may form a first angle A1with respect to a normal line perpendicular to the upper surface100U of the substrate100. Due to the interference of the block structure300, the first beam B1may be irradiated more on the first region R1and the second region R2than on the third region R3of the substrate.

Referring toFIG.9, a first deposition layer DL1may be formed by the first deposition process. The first deposition layer DL1may include a seed layer120L, a pinned magnetic layer130L, a tunnel barrier layer TBRL, and a free magnetic layer140L sequentially stacked on the bottom electrode layer BEL. The first deposition process may include sequentially depositing the seed layer120L, the pinned magnetic layer130L, the tunnel barrier layer TBRL, and the free magnetic layer140L. The first deposition layer DL1may be formed by, for example, sputtering, chemical vapor deposition, or atomic layer deposition. A thickness H1of the first deposition layer DL1at the first region R1and the second region R2of the substrate100may be greater than a thickness H2of the first deposition layer DL1at the third region R3.

A second deposition process may be performed on the first deposition layer DL1. The second deposition process may include irradiating a second beam B2. The second beam B2may form a second angle A2with respect to a normal line perpendicular to the upper surface100U of the substrate100. The second angle A2may be greater than the first angle A1. The second angle may be 30° to 60°. Due to the interference of the block structure300, the second beam B2may be irradiated more on the first region R1than on the second region R2and the third region R3of the substrate.

Referring toFIG.10, a second deposition layer DL2may be formed by the second deposition process. A thickness H3of the second deposition layer DL2at the first region R1of the substrate100may be greater than a thickness H4of the second deposition layer DL2at the second region R2and the third region R3. The second deposition layer DL2may be formed by, for example, sputtering, chemical vapor deposition, or atomic layer deposition.

The second deposition layer DL2may include a capping layer150L on the first deposition layer DL1. The capping layer150L may include a first capping layer150AL at the first region R1of the substrate and a second capping layer150BL at the second region R2of the substrate. A thickness T1of the first capping layer150AL may be greater than a thickness T2of the second capping layer150BL.

The second deposition layer DL2may further include an upper capping layer160L. The upper capping layer160L may include a first upper capping layer160AL at the first region R1of the substrate and a second upper capping layer160BL at the second region R2of the substrate. An upper surface300U of the block structure300may be higher than an uppermost surface160U of the second deposition layer DL2.

Referring toFIG.11, hard masks175may be formed on the second deposition layer DL2. The hard masks175may define regions where magnetic tunnel junction patterns to be described later are to be formed. After forming the hard masks175, a planarization process may be performed. Accordingly, upper surfaces of the hard masks175on the first region R1of the substrate and the hard masks175on the second region R2may be positioned at the same height. The hard masks175may include at least one of a metal (e.g., Ta, W, Ru, Ir, etc.) and a conductive metal nitride (e.g., TiN).

Referring toFIG.12, the second deposition layer DL2, the first deposition layer DL1, and the bottom electrode layer BEL may be sequentially etched using the hard masks175as an etching mask. Accordingly, a first magnetic tunnel junction pattern MTJ1, a second magnetic tunnel junction pattern MTJ2, and bottom electrodes BE may be formed on the first interlayer insulating layer110. The bottom electrodes BE may be respectively connected to the lower contact plugs115, and the first and second magnetic tunnel junction patterns MTJ1and MTJ2may be respectively formed on the bottom electrodes BE.

Etching the first deposition layer DL1and the second deposition layer DL2may include sequentially etching the upper capping layer160L, the capping layer150L, the free magnetic layer140L, the tunnel barrier layer TBRL, the pinned magnetic layer130L, and the seed layer120L using the hard masks175as an etch mask. Accordingly, the first magnetic tunnel junction pattern MTJ1may include a seed pattern120, a pinned magnetic pattern130, a tunnel barrier pattern TBR, a free magnetic pattern140, a first capping pattern150A, and a first upper capping pattern160A sequentially stacked on the first bottom electrode BE among the bottom electrodes BE. The second magnetic tunnel junction pattern MTJ2may include a seed pattern120, a pinned magnetic pattern130, a tunnel barrier pattern TBR, a free magnetic pattern140, a second capping pattern150B, and a second upper capping pattern160B sequentially stacked on the second bottom electrode BE among the bottom electrodes BE.

The etching process of etching the first deposition layer DL1, the second deposition layer DL2, and the bottom electrode layer BEL may be, for example, an ion beam etching process using an ion beam. The ion beam may include inert ions. An upper surface of the first interlayer insulating layer110may be recessed at both sides of the magnetic tunnel junction pattern MTJ by the ion beam etching process. Accordingly, the first interlayer insulating layer110may have a upper surface110RU recessed at both sides of the magnetic tunnel junction pattern MTJ.

After the ion beam etching process, remaining portions of each of the hard masks175may remain on the first and second magnetic tunnel junction patterns MTJ1and MTJ2. The remaining portions of the hard masks175may function as first and second top electrodes TE1and TE2. Hereinafter, the remaining portions of the hard masks175may be referred to as first and second top electrodes TE1and TE2. The first top electrode TE1, the first magnetic tunnel junction pattern MTJ1, and the first bottom electrode BE may constitute a first data storage pattern DS1. The second top electrode TE2, the second magnetic tunnel junction pattern MTJ2, and the second bottom electrode BE may constitute a second data storage pattern DS2.

By the etching process, the block structure300and the etch stop pattern310may be removed from the substrate100. After the block structure300and the etch stop pattern310are removed, the first interlayer insulating layer110may be exposed.

Referring toFIG.13, a protective insulating layer170may be formed on the first interlayer insulating layer110to cover the first and second data storage patterns DS1and DS2. The protective insulating layer170may be formed to conformally cover upper and side surfaces of the first and second data storage patterns DS1and DS2, and may extend along the recessed insulating layer110RU of the first interlayer insulating layer110. A second interlayer insulating layer180may be formed on the protective insulating layer170to cover the first and second data storage patterns DS1and DS2.

Referring back toFIG.4, portions of the second interlayer insulating layer180and the protective insulating layer170may be removed, and an upper surface of the top electrode TE of the data storage pattern DS may be exposed. An upper wiring200may be formed on the second interlayer insulating layer180and may cover the exposed upper surface of the top electrode TE. The upper wiring200may be electrically connected to the top electrode TE.

According to embodiments of inventive concepts of the present disclosure, the first capping pattern150A and the second capping pattern150B having different thicknesses may be manufactured through a single deposition process. That is, the first and second magnetic tunnel junction patterns MTJ1and MTJ2having different characteristics may be manufactured in a single process. A thickness difference between the first capping pattern150A and the second capping pattern150B may be adjusted using the height of the block structure300and the irradiation angle of the second beam B2. Accordingly, it is possible to provide a magnetic memory device with improved efficiency and a method of manufacturing the same.

FIGS.14and15are plan views of magnetic memory devices according to some embodiments of the present disclosure. For simplicity of explanation, descriptions overlapping those of the magnetic memory device described with reference toFIGS.5to13will be omitted.

Referring toFIG.14, a plurality of block structures300may be formed on the substrate100. Each of the plurality of block structures300may have a wall shape extending in one direction parallel to the upper surface of the substrate100. The plurality of block structures300may be horizontally spaced apart from each other. The magnetic tunnel junction patterns MTJ may be formed between the plurality of block structures300.

Referring toFIG.15, a plurality of block structures300may be formed on the substrate100. Each of the plurality of block structures300may have a pillar shape extending in a direction perpendicular to the upper surface of the substrate100. The plurality of block structures300may be horizontally spaced apart from each other. The magnetic tunnel junction patterns MTJ may be formed between the plurality of block structures300. The magnetic tunnel junction patterns MTJ may be disposed between three adjacent block structures300.

FIG.16is a cross-sectional view of a magnetic memory device according to some embodiments of the present disclosure. For simplicity of description, descriptions overlapping those of the magnetic memory device described with reference toFIGS.1to13will be omitted.

Referring toFIGS.12and16, a magnetic memory device according to some embodiments may include a block structure300and an etch stop pattern310. During the etching process described with reference toFIG.12, at least a portion of the block structure300may remain instead of being removed. In this case, the etch stop pattern310may be interposed between the remainder of the block structure300and the first interlayer insulating layer110. The protective insulating layer170may further cover the remainder of the block structure300and side surfaces of the etch stop pattern310. An upper surface of the remainder of the block structure300may be in contact with the upper wiring200.

According to embodiments of inventive concepts of the present disclosure, the first capping pattern and the second capping pattern having different thicknesses may be manufactured in one deposition process. That is, the first and second magnetic tunnel junction patterns having different characteristics may be manufactured in a single process. The thickness difference between the first capping pattern and the second capping pattern may be adjusted using the height of the block structure and the irradiation angle of the beam used in the deposition process. Accordingly, it is possible to provide the magnetic memory device with the improved manufacturing process efficiency and the method of manufacturing the same.

While embodiments are described above, a person skilled in the art may understand that many modifications and variations are made without departing from the spirit and scope of the present disclosure defined in the following claims. Accordingly, example embodiments of the present disclosure should be considered in all respects as illustrative and not restrictive, with the spirit and scope of the present disclosure being indicated by the appended claims.