SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a semiconductor element, a first wiring member electrically connected to a first main electrode on a first surface of the semiconductor element, a second wiring member electrically connected to a second main electrode on a second surface of the semiconductor element, a signal terminal connected to a signal pad on the second surface through a bonding wire. The second wiring member includes an insulating base material, a front surface metal body on a front surface of the insulating base material adjacent to the semiconductor element, and a back surface metal body on a back surface. An end portion of the front surface metal body is located between an end portion of a bonding target to which the front surface metal body is bonded and an end portion of the semiconductor element in an arrangement direction of the semiconductor element and the signal terminal.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and a method for manufacturing the same.

BACKGROUND

For example, JP 2020-64907 A discloses a semiconductor device that includes a semiconductor chip having main electrodes on opposite surfaces thereof, a first heat sink, a second heat sink, and a signal terminal. A drain electrode is provided on one surface of the semiconductor chip, and a source electrode and a signal pad are provided on a back surface of the semiconductor chip. The first heat sink is electrically connected to the drain electrode, and the second heat sink is electrically connected to the source electrode. The signal terminal is connected to the signal pad via a bonding wire. The disclosure of JP 2020-64907 A is incorporated herein by reference as an explanation of technical elements in the present disclosure.

SUMMARY

The present disclosure describes a semiconductor device and a method for manufacturing the semiconductor device. A semiconductor device according to an aspect includes a semiconductor element, a first wiring member electrically connected to a first main electrode on a first surface of the semiconductor element, a second wiring member electrically connected to a second main electrode on a second surface of the semiconductor element, a signal terminal connected to a signal pad on the second surface through a bonding wire. The second wiring member includes an insulating base material, a front surface metal body on a front surface of the insulating base material adjacent to the semiconductor element, and a back surface metal body on a back surface of the insulating base material. An end portion of the front surface metal body is located between an end portion of a bonding target to which the front surface metal body is bonded and an end portion of the semiconductor element in an arrangement direction of the semiconductor element and the signal terminal.

DETAILED DESCRIPTION

In a semiconductor device having a double-sided heat dissipation structure, which is for example represented by JP2020-64907 A, a terminal (conductive spacer) may be disposed between a source electrode and a second heat sink in order to avoid contact between a bonding wire and the second heat sink, that is, in order to secure the height of the bonding wire. The thicker the terminal is, the farther the facing surfaces of a first heat sink and the second heat sink are away from each other, and the effect of magnetic flux cancellation by the currents flowing in opposite directions, that is, the effect of inductance reduction is likely to be reduced. It may also increase thermal resistance.

In addition, it is conceivable that a portion of the second heat sink closer to the signal terminal than the terminal is cut out to avoid contact between the bonding wire and the second heat sink and to bring the facing surfaces of the first heat sink and the second heat sink close to each other. However, heat diffusion from the semiconductor element to the second heat sink is inhibited by the cutout. In such a configuration, it is difficult to reduce the dead space. From the above-described viewpoint or from other viewpoints not mentioned, further improvement is required for the semiconductor device.

The present disclosure provides a semiconductor device capable of reducing thermal resistance while reducing inductance, and a method for manufacturing the semiconductor device.

According to an aspect of the present disclosure, a semiconductor device includes: a semiconductor element having a first surface and a second surface opposite to the first surface in a thickness direction, and including a first main electrode disposed on the first surface, a second main electrode disposed on the second surface, and a signal pad disposed at a position different from the second main electrode on the second surface; a first wiring member electrically connected to the first main electrode; a second wiring member electrically connected to the second main electrode; a signal terminal; and a bonding wire electrically connecting the signal pad and the signal terminal. In the semiconductor device, the second wiring member is a substrate having an insulating base material, a front surface metal body, and a back surface metal body. The front surface metal body is disposed on a front surface of the insulating base material adjacent to the semiconductor element and is electrically connected to the second main electrode. The back surface metal body is disposed on a back surface of the insulating base material. An end portion of the front surface metal body is located between an end portion of a bonding target to which the front surface metal body is bonded and an end portion of the semiconductor element in an arrangement direction of the semiconductor element and the signal terminal.

In such a semiconductor device, the substrate is used as the second wiring member. By patterning the front surface metal body of the substrate, the end portion of the front surface metal body is located between the end portion of the bonding target and the end portion of the semiconductor element in the arrangement direction. Since the end portion of the front surface metal body is located more to inside than the end portion of the semiconductor element in this manner, it is possible to avoid contact between the front surface metal body and the bonding wire and to bring the facing surfaces of the front surface metal body of the second wiring member and a conductive portion of the first wiring member close to each other. As a result, the effect of magnetic flux cancellation is enhanced, and inductance can be reduced. In addition, since the heat transfer path from the semiconductor element to the front surface metal body of the second wiring member is shortened, the thermal resistance can be reduced.

Further, since the end portion of the front surface metal body is located more to outside than the end portion of the bonding target, the heat of the semiconductor element can be diffused outside the bonding target through the front surface metal body. As such, the thermal resistance can be reduced. As a result, it is possible to reduce the thermal resistance while reducing the inductance.

According to an aspect of the present disclosure, a method for manufacturing a semiconductor device includes: electrically connecting a first main electrode disposed on a first surface of a semiconductor element and a first wiring member to each other; connecting a signal pad that is disposed on a second surface of the semiconductor element opposite to the first surface in a thickness direction to a signal terminal through a bonding wire; and, after the connecting of the signal pad and the signal terminal through the bonding wire, electrically connecting a second main electrode disposed at a position different from the signal pad on the second surface of the semiconductor element and a second wiring member to each other. In the electrically connecting of the second main electrode and the second wiring member, a substrate having an insulating base material, a front surface metal body and a back surface metal body is used. In the substrate, the front surface metal body is disposed on a front surface of the insulating base material adjacent to the semiconductor element, and electrically connected to the second main electrode; the back surface metal body is disposed on a back surface of the insulating base material; and the front surface metal body is patterned such that an end portion of the front surface metal body is located between an end portion of a bonding target to which the front surface metal body is bonded and an end portion of the semiconductor element in an arrangement direction of the semiconductor element and the signal terminal. In the electrically connecting of the second main electrode and the second wiring member, the second main electrode and the second wiring member are electrically connected to each other while an exposed portion of the insulating base material exposed from the front surface metal body is brought into contact with the bonding wire.

In such a method, the substrate is used as the second wiring member. The front surface metal body of the substrate is patterned such that the end portion of the front surface metal body is located between the end portion of the bonding target and the end portion of the semiconductor element in the arrangement direction. Since the end portion of the front surface metal body is located more to inside than the end portion of the semiconductor element, contact between the front surface metal body and the bonding wire can be avoided. Also, the facing surfaces of the front surface metal body of the second wiring member and a conductive portion of the first wiring member can be brought close to each other. As a result, the effect of magnetic flux cancellation is enhanced, and the inductance can be reduced. In addition, since the heat transfer path from the semiconductor element to the front surface metal body of the second wiring member is shortened, the thermal resistance can be reduced. By electrically connecting the second main electrode and the second wiring member in a state where the exposed portion of the insulating base material exposed from the front surface metal body is in contact with the bonding wire, the facing surfaces are brought closer to each other, and the effects of reducing the inductance and reducing the thermal resistance can be enhanced.

Further, since the end portion of the front surface metal body is located more to outside than the end portion of the bonding target, the heat of the semiconductor element can be diffused outside the end portion of the bonding target through the front surface metal body. As such, the thermal resistance can be reduced. As a result, it is possible to reduce the thermal resistance while reducing the inductance.

The disclosed aspects in this specification adopt different technical solutions from each other in order to achieve their respective objectives. Objects, features, and advantages disclosed in this specification will become apparent by referring to the following detailed descriptions and accompanying drawings.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The same or corresponding elements are designated with the same reference numerals throughout the embodiments, and descriptions thereof will not be repeated. When only part of the configurations is described in each embodiment, the configurations of the other preceding embodiments can be applied to the other parts of the configurations. A combination of configurations is not limited to the combination of the configurations explicitly described in the description of each embodiment. Configurations of a plurality of embodiments can be combined in part even if not explicitly described as long as there is no problem in the combination.

A semiconductor device of the present embodiment is applicable to, for example, a power conversion device of a movable object having a rotary electric machine as a drive source. The movable object is, for example, an electric vehicle such as an electrical vehicle (EV), a hybrid vehicle (HV), or a plug-in hybrid vehicle (PHV), a flying object such as a drone, a ship, a construction machine, or an agricultural machine. Hereinafter, an example in which the semiconductor device is applied to a vehicle will be described.

First Embodiment

First, a schematic configuration of a drive system of a vehicle will be described with reference toFIG.1.

As shown inFIG.1, a vehicle drive system1is provided with a direct current (DC) power supply2, a motor generator3, and an electric power conversion device4.

The DC power supply2is a direct-current voltage source including a chargeable/dischargeable secondary battery. Examples of the secondary battery include a lithium ion battery and a nickel hydride battery. The motor generator3is a three-phase alternating current (AC) type rotary electric machine. The motor generator3functions as a drive source for traveling the vehicle, that is, an electric motor. The motor generator3functions as a generator during regeneration. The electric power conversion device4performs electric power conversion between the DC power supply2and the motor generator3.

Next, a circuit configuration of the electric power conversion device4will be described with reference toFIG.1. The electric power conversion device4includes a power conversion circuit. The electric power conversion device4of the present embodiment includes a smoothing capacitor5and an inverter6that is a power conversion circuit.

The smoothing capacitor5mainly smoothes the DC voltage supplied from the DC power supply2. The smoothing capacitor5is connected to a P line7which is a power supply line on a high potential side and an N line8which is a power supply line on a low potential side. The P line7is connected to a positive electrode of the DC power supply2, and the N line8is connected to a negative electrode of the DC power supply2. The positive electrode of the smoothing capacitor5is connected to the P line7between the DC power supply2and the inverter6. The negative electrode of the smoothing capacitor5is connected to the N line8between the DC power supply2and the inverter6. The smoothing capacitor5is connected to the DC power supply2in parallel. The P line7and the N line8may be referred to as power supply lines7and8.

The inverter6corresponds to a DC-AC converter circuit. The inverter6converts the DC voltage into a three-phase AC voltage according to the switching control by a control circuit (not shown) and outputs the three-phase AC voltage to the motor generator3. Thereby, the motor generator3is driven to generate a predetermined torque. At the time of regenerative braking of the vehicle, the inverter6converts the three-phase AC voltage generated by the motor generator3by receiving the rotational force from wheels into a DC voltage according to the switching control by the control circuit, and outputs the DC voltage to the P line. In this way, the inverter6performs bidirectional power conversion between the DC power supply2and the motor generator3.

The inverter6includes upper-lower arm circuits9for three phases. The upper-lower arm circuit9may be referred to as a leg. The upper-lower arm circuit9includes an upper arm9H and a lower arm9L. The upper arm9H and the lower arm9L are connected in series between the P line7and the N line8, and the upper arm9H is adjacent to the P line7. A connection point between the upper arm9H and the lower arm9L is connected to a winding3aof a corresponding phase of the motor generator3via an output line10. The inverter6has six arms. Each arm is configured to include a switching element. At least a part of each of the P line7, the N line8, and the output line10is configured by a conductive member such as a bus bar.

In the present embodiment, a switching element constituting each arm is provided by an n-channel MOSFET11. The number of switching elements constituting each arm is not particularly limited. The number thereof may be one or more. The MOSFET is an abbreviation of a metal oxide semiconductor field effect transistor.

In the present embodiment, each arm has two MOSFETs11, as an example. The two MOSFETs11constituting one arm are connected in parallel. In the upper arm9H, the drains of the two MOSFETs11connected in parallel are connected to the P line7. In the lower arm9L, the sources of the two MOSFETs11connected in parallel are connected to the N line8. The sources of the two MOSFETs11connected in parallel in the upper arm9H and the drains of the two MOSFETs11connected in parallel in the lower arm9L are connected to each other. The two MOSFETs11connected in parallel are turned on and off at the same timing by a common gate drive signal (drive voltage).

A freewheeling diode12is connected in antiparallel to each of the MOSFETs11. The diode12may be a parasitic diode (body diode) of the MOSFET11or may be a diode provided separately from the parasitic diode. The anode of the diode12is connected to the source of the corresponding MOSFET11, and the cathode of the diode12is connected to the drain of the corresponding MOSFET11. The upper-lower arm circuit9for one phase is provided by one semiconductor device20. Details of the semiconductor device20will be described later.

The electric power conversion device4may further include a converter as a power conversion circuit. The converter is a DC-DC converter circuit for converting the DC voltage to a DC voltage with different value. The converter is disposed between the DC power supply2and the smoothing capacitor5. The converter includes, for example, a reactor and the upper-lower arm circuit9described above. The converter having such a configuration can boost and suppress the voltage. The electric power conversion device4may further include a filter capacitor for removing power supply noise from the DC power supply2. The filter capacitor is provided between the DC power supply2and the converter.

The electric power conversion device4may include a drive circuit for the switching elements constituting the inverter6or the like. The drive circuit supplies a drive voltage to the gate of the MOSFET11of the corresponding arm based on the drive command of the control circuit. The drive circuit drives the corresponding MOSFET11, that is, turns on and off the corresponding MOSFET11by applying the drive voltage. The drive circuit may be referred to as a driver.

The electric power conversion device4may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET11and outputs the drive command to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a host ECU (not shown) or signals detected by various sensors. ECU is an abbreviation of an electronic control unit.

Examples of the various sensors include a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding3aof each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator3. The voltage sensor detects the voltage across the smoothing capacitor5. The control circuit includes, for example, a processor and a memory. The control circuit outputs, for example, a PWM signal as the drive command. PWM is an abbreviation of pulse width modulation.

Next, the semiconductor device will be described with reference toFIGS.2to10.FIG.2is a perspective view of the semiconductor device20.FIG.3is a plan view of the semiconductor device when viewed along a direction Z1inFIG.2.FIG.3is a transparent view showing the internal structure. A region covered with the sealing body30is indicated by a broken line.FIG.4is a cross-sectional view taken along a line IV-IV inFIG.3.FIG.5is a cross-sectional view taken along a line V-V inFIG.3.FIG.6is a cross-sectional view taken along a line VI-VI inFIG.3.FIG.7is a cross-sectional view taken along a line VII-VII inFIG.3.FIG.8is a plan view of a substrate50on which a semiconductor element40is mounted.FIG.8is the view in which a sealing body30and a substrate60are removed fromFIG.3.FIG.9is a plan view showing a circuit pattern of a front surface metal body52on the substrate50.FIG.10is a plan view showing a circuit pattern of a front surface metal body62on the substrate60.

Hereinafter, a thickness direction of the semiconductor element40(semiconductor substrate) is referred to as a Z direction. An arrangement direction in which multiple semiconductor elements40are arranged side by side is referred to as an X direction. The arrangement direction is orthogonal to the Z direction. In the present embodiment, the X direction is the arrangement direction of the semiconductor elements40that are connected in parallel. A direction orthogonal to both the Z direction and the X direction is referred to as a Y direction. Unless otherwise specified, a shape when viewed in the Z direction, that is, a shape along an XY plane defined by the X direction and Y direction is referred to as a planar shape. A plan view when viewed in the Z direction may be simply referred to as a plan view.

As shown inFIGS.2to10, the semiconductor device20constitutes one upper-lower arm circuit9as described above, that is, the upper-lower arm circuit9for one phase. The semiconductor device20includes a sealing body30, a semiconductor element40, substrates50and60, a conductive spacer70, an arm connection portion80, and an external connection terminal90. The semiconductor device20may be referred to as a semiconductor module, a power card, or the like.

The sealing body30seals a part of other elements constituting the semiconductor device20. A remaining part of the other elements is exposed to the outside of the sealing body30. The sealing body30is made of, for example, a resin. An example of the resin is an epoxy resin. The sealing body30is made of a resin and molded by, for example, a transfer molding method. Such a sealing body30may be referred to as a sealing resin body, a mold resin, a resin molded body, or the like. The sealing body30may be formed using gel, for example. The gel is filled (disposed), for example, in a facing region between the pair of substrates50and60.

As shown inFIGS.2to4, the sealing body30has a substantially rectangular shape as the planar shape. The sealing body30has a first surface30aand a second surface30bwhich is a back surface opposite to the first surface30ain the Z direction, as surfaces forming a contour. The first surface30aand the second surface30bare, for example, flat surfaces. In addition, the sealing body30has side surfaces30c,30d,30e, and30f, as surfaces connecting the first surface30aand the second surface30b. The side surface30cis a surface from which the power supply terminal91and the signal terminal93H of the external connection terminals90protrude. The side surface30dis a surface opposite to the side surface30cin the Y direction. The side surface30dis a surface from which the output terminal92and the signal terminal93L protrude. The side surfaces30eand30fare surfaces from which the external connection terminals90do not protrude. The side surface30eis a surface opposite to the side surface30fin the X direction.

The semiconductor element40is formed by forming a switching element on a semiconductor substrate made of silicon (Si), a wide bandgap semiconductor having a wider bandgap than silicon, or the like. Examples of the wide bandgap semiconductor include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3) and diamond. The semiconductor element40may be referred to as a power element, a semiconductor chip, or the like.

The semiconductor element40of the present embodiment is configured by forming the above-described n-channel MOSFET11in a semiconductor substrate made of SiC. The MOSFET11has a vertical structure so that a main current flows in the thickness direction of the semiconductor element40(semiconductor substrate), that is, in the Z direction. The semiconductor element40has main electrodes of switching elements on both surfaces in the Z direction, which is the thickness direction of the semiconductor element40. Specifically, the semiconductor element40has, as the main electrodes, a drain electrode40D on a first surface, and a source electrode40S on a second surface which is a back surface opposite to the first surface in the Z direction. The main current flows between the drain electrode40D and the source electrode40S.

In a case where the diode12is a parasitic diode, the source electrode40S also serves as an anode electrode, and the drain electrode40D also serves as a cathode electrode. The diode12may be formed on a chip separate from the MOSFET11. The drain electrode40D is a main electrode on the high potential side, and the source electrode40S is a main electrode on the low potential side.

The semiconductor element40has substantially a rectangular shape as the planar shape. For example, the semiconductor element40has a square shape, as the planar shape. As shown inFIGS.3and8, the semiconductor element40has a pad40P, which serves as a signal electrode, on the second surface. The pad40P is formed at a position different from the source electrode40S on the second surface. The pad40P includes at least a gate pad. The semiconductor element40of the present embodiment has four pads40P. As shown inFIG.8, the pads40P include a gate pad GP, a Kelvin source pad KSP, an anode pad AP, and a cathode pad KP.

The gate pad GP is a pad40P for applying a drive voltage to the gate electrode of the MOSFET11. That is, the gate pad GP is a gate electrode pad40P that controls a main current flowing between the drain electrode40D and the source electrode40S, which are main electrodes. The Kelvin source pad KSP is a pad40P for detecting the source potential of the MOSFET11, that is, the potential of the source electrode40S. The anode pad AP is a pad40P for detecting an anode potential of a temperature sensitive diode (not shown) included in the semiconductor element40. The cathode pad KP is a pad40P for detecting the cathode potential of the temperature sensitive diode.

Among the pads40P, the gate pad GP, the anode pad AP, and the cathode pad KP are electrically separated from the source electrode40S. The Kelvin source pad KSP is electrically connected to the source electrode40S. In the present embodiment, the gate pad GP, the Kelvin source pad KSP, the anode pad AP, and the cathode pad KP are arranged in this order in the X direction.

The source electrode40S and the pad40P are exposed from a protective film (not shown) that is formed on the second surface of the semiconductor substrate. The drain electrode40D is formed on a substantially entire region on the first surface. The source electrode40S is formed on a part of the second surface of the semiconductor element40. In the plan view, the drain electrode40D has a larger area than the source electrode40S. The drain electrode40D corresponds to a first main electrode, and the source electrode40S corresponds to a second main electrode.

The semiconductor device20includes a plurality of semiconductor elements40having the above-described configuration. The plurality of semiconductor elements40include a semiconductor element40H constituting the upper arm9H and a semiconductor element40L constituting the lower arm9L. The semiconductor element40H will also be referred to as an upper arm element, and the semiconductor element40L will also be referred to as a lower arm element. The semiconductor element40of the present embodiment includes two semiconductor elements40H and two semiconductor elements40L.

The semiconductor element40H includes a semiconductor element41H as a first element and a semiconductor element42H as a second element. The two semiconductor elements40H (41H,42H) are arranged in the X direction. The two semiconductor elements40H, which are arranged in the X direction, have a common structure. The two semiconductor elements40H having the common structure are arranged in the X direction and oriented in the same direction. The two semiconductor elements40H are connected in parallel to each other.

The semiconductor element40L includes a semiconductor element41L as a first element and a semiconductor element42L as a second element. The two semiconductor elements40L (41L and42L) are arranged in the X direction. The two semiconductor elements40L, which are arranged in the X direction, have a common structure. The two semiconductor elements40L having the common structure are arranged in the X direction and oriented in the same direction. The two semiconductor elements40L are connected in parallel to each other.

In the present embodiment, all the semiconductor elements40have a common structure. The arrangement of the semiconductor elements41H and42H and the arrangement of the semiconductor elements41L and42L have two-fold symmetry around an axis along the Z direction. The semiconductor element40H and the semiconductor element40L are arranged in the Y direction. The semiconductor device20includes two rows of the semiconductor elements40H and the semiconductor elements40L along the Y direction.

The semiconductor elements40are disposed at substantially the same position in the Z direction. The drain electrode40D of each semiconductor element40faces the substrate50. The source electrode40S of each semiconductor element40faces the substrate60.

The substrates50and60are disposed so as to sandwich the plurality of semiconductor elements40therebetween in the Z direction. The substrates50and60are disposed such that at least portions thereof face each other in the Z direction. The substrates50and60encompass all of the plurality of semiconductor elements40(40H and40L) in the plan view.

The substrate50is disposed on the drain electrode40D side with respect to the semiconductor element40. The substrate60is disposed on the source electrode40S side with respect to the semiconductor element40. The substrate50is electrically connected to the drain electrode40D as described later, and provides a wiring function. Similarly, the substrate60is electrically connected to the source electrode40S and provides a wiring function. Therefore, the substrates50and60may be referred to as wiring members, wiring substrates, or the like. The substrate50may be referred to as a drain substrate, and the substrate60may be referred to as a source substrate. The substrates50and60provide a heat dissipation function of dissipating heat generated by the semiconductor element40. Therefore, the substrates50and60may be referred to as heat dissipation members. The substrate50corresponds to a first wiring member. The substrate60is a second wiring member electrically connected to the second main electrode.

The substrate50has a facing surface50afacing the semiconductor element40and a back surface50bopposite to the facing surface50a. The substrate50includes an insulating base material51, a front surface metal body52, and a back surface metal body53. The substrate60has a facing surface60afacing the semiconductor element40and a back surface60bopposite to the facing surface60a. The substrate60includes an insulating base material61, a front surface metal body62, and a back surface metal body63. Hereinafter, the front surface metal bodies52and62and the back surface metal bodies53and63may be simply referred to as metal bodies52,53,62, and63. The substrate50is a substrate in which the insulating base material51and the metal bodies52and53are stacked. The substrate60is a substrate in which the insulating base material61and the metal bodies62and63are stacked.

The insulating base material51electrically separates the front surface metal body52and the back surface metal body53from each other. Similarly, the insulating base material61electrically separates the front surface metal body62and the back surface metal body63from each other. The base materials51and61may be referred to as insulating layers. The material of the insulating base materials51and61is a resin or a ceramic of an inorganic material. As the resin, for example, an epoxy-based resin or a polyimide-based resin can be used. As the ceramic, for example, Al2O3(alumina), Si3N4(silicon nitride), or the like can be used. When the insulating base materials51and61are resin, the substrates50and60may be referred to as metal-resin substrates. When the insulating base materials51and61are ceramic, the substrates50and60may be referred to as metal-ceramic substrates.

In the case of the insulating base materials51and61using a resin material, an inorganic filler may be contained in the resin material in order to improve heat dissipation property, insulation property, and the like. The linear expansion coefficient may be adjusted by adding a filler. As the filler, for example, Al2O3, SiO2(silicon dioxide), AlN (aluminum nitride), BN (boron nitride), or the like can be used. The insulating base materials51and61may contain only one type of filler or may contain a plurality of types of fillers.

In the case of the insulating base materials51and61using the resin-based material, the thickness of each of the insulating base materials51and61, that is, the length in the Z direction is preferably about 50 μm to 300 μm in consideration of the heat dissipation property or the insulation property. In the case of the insulating base materials51and61using a ceramic material, the thickness of each of the insulating base materials51and61is preferably about 200 μm to 500 μm. In the Z direction, the front surfaces of the insulating base materials51and61are inner surfaces, that is, surfaces on the semiconductor element40side, and the back surfaces of the insulating base materials51and61opposite to the front surfaces in the Z direction are outer surfaces. The insulating base materials51and61may have a common (same) material configuration or may be different from each other. In the present embodiment, the resin-based insulating base materials51and61are employed, and the material configuration is common. The linear expansion coefficients of the insulating base materials51and61are adjusted to substantially the same value as that of the sealing body30by adding a filler to the resin. By adding the filler to the resin, the linear expansion coefficients of the insulating base materials51and61and the sealing body30are close to the linear expansion coefficient of the metal (Cu) constituting the metal bodies52,53,62, and63.

The metal bodies52,53,62,63are provided, for example, as metal plates or metal foils. The metal bodies52,53,62, and63are made of a metal having good electrical conductivity and thermal conductivity, such as Cu or Al. The thickness of each of the metal bodies52,53,62, and63is, for example, about 0.1 mm to 3 mm. The front surface metal body52is disposed on the front surface of the insulating base material51in the Z direction. The back surface metal body53is disposed on the back surface of the insulating base material51. Similarly, the front surface metal body62is disposed on the front surface of the insulating base material61in the Z direction. The back surface metal body63is disposed on the back surface of the insulating base material61.

The thickness relationship between the front surface metal bodies52and62and the back surface metal bodies53and63is not particularly limited. The thickness of the front surface metal body52may be larger than that of the back surface metal body53or may be substantially equal to that of the back surface metal body53. The thickness of the front surface metal body52may be smaller than that of the back surface metal body53. Similarly, the thickness of the front surface metal body62may be larger than that of the back surface metal body63or may be substantially equal to that of the back surface metal body63. The thickness of the front surface metal body62may be smaller than that of the back surface metal body63. The relationship between the thicknesses of the front surface metal bodies52and62is not particularly limited, and the relationship between the thicknesses of the back surface metal bodies53and63is not particularly limited.

The front surface metal bodies52and62are patterned. The front surface metal bodies52and62provide wirings, that is, a circuit. Therefore, the front surface metal bodies52and62may be each referred to as a circuit pattern, a wiring layer, a circuit conductor, or the like. The front surface metal bodies52and62may each include a plating film such as a Ni-based plating film or an Au plating film on the metal surface. The pattern of the front surface metal bodies52and62may be referred to as a circuit pattern. The surface of the front surface metal body52and a non-arrangement region of the front surface of the insulating base material51on which the front surface metal body52is not arranged form the facing surface50aof the substrate50. Similarly, the surface of the front surface metal body62and a non-arrangement region of the front surface of the insulating base material61on which the front surface metal body62is not arranged form the facing surface60aof the substrate60.

For example, the substrates50and60may be formed by preparing the front surface metal bodies52and62patterned into a predetermined shape by press working, etching, or the like, and bringing the front surface metal bodies52and62into close contact with the stacked bodies of the two-layer structures of the insulating base materials51and61and the back surface metal bodies53and63, respectively. After forming the stacked bodies having a three-layer structure of the front surface metal bodies52and62, the insulating base materials51and61, and the back surface metal bodies53and63, the front surface metal bodies52and62may be patterned by cutting or etching.

As shown inFIGS.8and9, the front surface metal body52includes a P wiring54and a relay wiring55. The P wiring54and the relay wiring55are electrically separated by a predetermined interval (gap). The gap is filled with the sealing body30. As surfaces on the semiconductor element40side in the Z direction, the P wiring54has a facing surface54a, and the relay wiring55has a facing surface55a. The facing surfaces54aand55aprovide the facing surface50adescribed above.

The P wiring54is connected to a P terminal91P described later and the drain electrode40D of the semiconductor element40H. The P wiring54electrically connects the P terminal91P and the drain electrode40D of the semiconductor element40H to each other. The P wiring54electrically connects the drain electrode40D of the semiconductor element41H and the drain electrode40D of the semiconductor element42H to each other.

The relay wiring55is connected to the drain electrode40D of the semiconductor element40L, the arm connection portion80, and the output terminal92. The relay wiring55electrically connects the arm connection portion80and the drain electrode40D of the semiconductor element40L to each other. The relay wiring55electrically connects the source electrode40S of the semiconductor element40H and the drain electrode40D of the semiconductor element40L to the output terminal92. The relay wiring55electrically connects the drain electrode40D of the semiconductor element41L and the drain electrode40D of the semiconductor element42L to each other.

The P wiring54and the relay wiring55are arranged side by side in the Y direction. In the Y direction, the P wiring54is disposed on the power supply terminal91side, and the relay wiring55is disposed on the output terminal92side. The P wiring54is disposed on the side surface30cside of the sealing body30, and the relay wiring55is disposed on the side surface30dside.

The P wiring54has a notch540. The notch540is opened in one of four sides of a substantially rectangular shape in the plan view having the X direction as a longitudinal direction. The notch540is provided substantially at the center in the X direction on the side facing the side surface30c. The P wiring54has a base portion541and a pair of extension portions542. The base portion541and the pair of extension portions542define the notch540. The P wiring54has a substantially U shape (recessed shape) in the plan view.

The base portion541is a portion closer to the relay wiring55than the notch540and the extension portions542in the Y direction, and has a substantially rectangular shape in the plan view. The base portion541overlaps the semiconductor element40H in the plan view. That is, the two semiconductor elements40H (41H,42H) are disposed on the base portion541. The drain electrode40D of each of the semiconductor elements40H is connected to the base portion541.

The two extension portions542extend from the base portion541in the same direction, specifically, in the Y direction toward the side surface30cof the sealing body30. One of the extension portions542is connected to the vicinity of one end of the base portion541in the X direction, and the other of the extension portions542is connected to the vicinity of the other end of the base portion541in the X direction. The end portions of the U-shape of the P wiring54, that is, the end portions of the two extension portions542opposite to the base portion541are both located at substantially the same position in the Y direction. The pair of extension portions542interpose the notch540in the X direction. The length of the base portion541in the Y direction is longer than the depth of the notch540and the extension portions542.

The relay wiring55also has a notch550. The notch550is opened in one of four sides of the substantially rectangular shape in the plan view. The notch550is provided substantially at the center in the X direction on the side facing the side surface30d. That is, in the front surface metal body52, the notch540is provided in one end portion in the Y direction, and the notch550is provided in the other end portion.

The relay wiring55includes a base portion551and a pair of extension portions552. The base portion551and the pair of extension portions552define the notch550. The relay wiring55has a substantially U shape (recessed shape) in the plan view. The base portion551is a portion closer to the P wiring54than the notch550and the extension portions552in the Y direction, and has a substantially rectangular shape in the plan view. The base portion551overlaps the semiconductor element40L in the plan view. That is, the two semiconductor elements40L (41L,42L) are disposed on the base portion551. The drain electrode40D of each of the semiconductor elements40L is connected to the base portion551.

The two extension portions552extend from the base portion551in the same direction, specifically, in the Y direction toward the side surface30dof the sealing body30. One of the extension portions552is connected to the vicinity of one end of the base portion551in the X direction, and the other of the extension portions552is connected to the vicinity of the other end of the base portion551. The end portions of the U-shape of the relay wiring55, that is, the end portions of the two extension portions552opposite to the base portion551are both located at substantially the same position in the Y direction. The pair of extension portions552interpose the notch550in the X direction. The length of the base portion551in the Y direction is longer than the depth of the notch550and the extension portions552.

As shown inFIGS.3and10, the front surface metal body62includes an N wiring64and a relay wiring65. The N wiring64and the relay wiring65are electrically separated by a predetermined interval (gap). The gap is filled with the sealing body30. As surfaces on the semiconductor element40side in the Z direction, the N wiring64has a facing surface64a, and the relay wiring65has a facing surface65a. The facing surfaces64aand65aform the facing surface60adescribed above.

The N wiring64is connected to an N terminal91N described later and the source electrode40S of the semiconductor element40L. The N wiring64electrically connects the N terminal91N and the source electrode40S of the semiconductor element40L. The N wiring64electrically connects the source electrode40S of the semiconductor element41L and the source electrode40S of the semiconductor element42L. The N wiring64may be referred to as a negative electrode wiring, a low potential power supply wiring, or the like.

The relay wiring65is connected to the source electrode40S of the semiconductor element40H and the arm connection portion80. The relay wiring65electrically connects the source electrode40S of the semiconductor element40H and the arm connection portion80to each other. The relay wiring65electrically connects the source electrode40S of the semiconductor element41H and the source electrode40S of the semiconductor element42H to each other.

The N wiring64also has a notch640. The notch640is opened in one of four sides of the substantially rectangular shape in the plan view. The notch640is provided substantially at the center in the X direction on the side facing the side surface30c. The N wiring64has a base portion641and a pair of extension portions642. The base portion641and the pair of extension portions642define the notch640. The N wiring64has a substantially U shape (recessed shape) in the plan view.

The base portion641is a portion closer to the side surface30dthan the notch640and the extension portion642in the Y direction. The base portion641has a substantially rectangular shape in the plan view having the longitudinal direction along the X direction. The base portion641is arranged side by side with the relay wiring65in the Y direction. The base portion641overlaps the relay wiring55in the plan view. The source electrode40S of each of the semiconductor elements40L is connected to the base portion641.

The two extension portions642extend from the base portion641in the same direction, specifically, in the Y direction toward the side surface30cof the sealing body30. One of the extension portions642is connected to the vicinity of one end of the base portion641in the X direction, and the other of the extension portions642is connected to the vicinity of the other end of the base portion641. The end portions of the U-shape of the N wiring64, that is, the end portions of the two extension portions642opposite to the base portion641are located at substantially the same position in the Y direction.

The pair of extension portions642form both ends of the front surface metal body62in the X direction. The pair of extension portions642are disposed near the ends of the substrate60. In the plan view, a part of each of the pair of extension portions642overlaps the P wiring54. In the Y direction, the extension portions642are longer than the base portion641.

As described above, the relay wiring65is arranged side by side with the N wiring64, specifically, the base portion641in the Y direction. In the Y direction, the relay wiring65is disposed at a position close to the side surface30cof the sealing body30, and the base portion641is disposed at a position close to the side surface30d. The relay wiring65is disposed between the pair of extension portions642in the X direction. The relay wiring65is interposed between the pair of extension portions642. The relay wiring65is disposed in the notch640. The relay wiring65is disposed with a predetermined interval (gap) from the N wiring64. In the plan view, a part of the relay wiring65overlaps the P wiring54, and another part of the relay wiring65overlaps the relay wiring55. The source electrode40S of each of the semiconductor elements40H is connected to the relay wiring65. Details of the arrangement of the front surface metal body62(the N wiring64and the relay wiring65) will be described later.

The back surface metal bodies53and63are electrically separated from the circuit including the semiconductor element40and the front surface metal bodies52and62by the insulating base materials51and61. The back surface metal bodies53and63may be referred to as metal base substrates. The heat generated by the semiconductor element40is transmitted to the back surface metal bodies53and63via the front surface metal bodies52and62and the insulating base materials51and61. The back surface metal bodies53and63each provide a heat dissipation function.

The back surface metal bodies53and63of the present embodiment each have a substantially rectangular shape as the planar shape. The back surface metal bodies53and63are so-called solid conductors disposed on substantially the entire back surfaces of the insulating base materials51and61. As described above, since the linear expansion coefficients of the insulating base materials51and61are adjusted by the addition of the filler, the warpage can be suppressed even when the pattern is changed between the front and back sides. Of course, the back surface metal bodies53and63may be patterned so as to coincide with the front surface metal bodies52and62in the plan view.

The back surface metal bodies53and63of the present embodiment are disposed on substantially the entire back surfaces of the corresponding insulating base materials51and61. In order to further enhance the heat dissipation effect, at least one of the back surface metal bodies53and63may be exposed from the sealing body30. In the present embodiment, the back surface metal body53is exposed from the first surface30aof the sealing body30, and the back surface metal body63is exposed from the second surface30bof the sealing body30. The exposed surface of the back surface metal body53is substantially flush with the first surface30a. The exposed surface of the back surface metal body63is substantially flush with the second surface30b. The back surface metal bodies53and63form the back surfaces50band60bof the substrates50and60.

The conductive spacer70provides a spacer function of securing a predetermined interval between the semiconductor element40and the substrate60. The conductive spacer70secures the height for a wire electrically connecting the corresponding signal terminal93to the pad40P of the semiconductor element40. The conductive spacer70is located in the middle of an electric conduction and heat conduction path between the source electrode40S of the semiconductor element40and the substrate60, and provides a wiring function and a heat dissipation function. The conductive spacer70contains a metal material having good electrical conductivity and thermal conductivity, such as copper (Cu). The conductive spacer70may include a plating film on its surface.

The conductive spacer70may be referred to as a terminal, a terminal block, a metal block body, or the like. The semiconductor device20includes the same number of conductive spacers70as the semiconductor elements40. Specifically, the semiconductor device20includes four conductive spacers70. The conductive spacers70are individually connected to the semiconductor elements40. The conductive spacer70is a columnar body having a size substantially equal to or slightly smaller than that of the source electrode40S in the plan view.

The arm connection portion80electrically connects the relay wirings55and65. That is, the arm connection portion80electrically connects the upper arm9H and the lower arm9L. The arm connection portion80is provided between the semiconductor element40H and the semiconductor element40L in the Y direction. The arm connection portion80is provided in an overlapping region between the relay wiring55and the relay wiring65in the plan view. The arm connection portion80of the present embodiment includes a joint portion81and a bonding material103described later.

The joint portion81is a metal columnar body provided separately from the front surface metal bodies52and62. Such a joint portion81may be referred to as a joint terminal. In the Z direction, the bonding material103is interposed between one of the end portions of the joint portion81and the relay wiring55, and the bonding material103is interposed between the other one of the end portions of the joint portion81and the relay wiring65.

Alternatively, the joint portion81may be integrally connected to at least one of the front surface metal body52or the front surface metal body62. That is, the joint portion81may be provided integrally with the front surface metal bodies52and62as a part of the substrates50and60. For example, the joint portion81is provided as a protrusion of the front surface metal body62(relay wiring65). The arm connection portion80may not include the joint portion81. That is, the arm connection portion80may include only the bonding material103.

The external connection terminal90is a terminal for electrically connecting the semiconductor device20to an external device. The external connection terminal90is formed using a metal material having good conductivity such as copper. The external connection terminal90is, for example, a plate member. The external connection terminal90may be referred to as a lead. The external connection terminal90includes a power supply terminal91, an output terminal92, and a signal terminal93. The power supply terminal91includes a P terminal91P and an N terminal91N. The P terminal91P, the N terminal91N, and the output terminal92are main terminals electrically connected to the main electrode of the semiconductor element40. The signal terminal93includes a signal terminal93H on the upper arm9H side and a signal terminal93L on the lower arm9L side.

The power supply terminal91is an external connection terminal90electrically connected to the power supply lines7and8described above. The P terminal91P is electrically connected to the positive electrode terminal of the smoothing capacitor5. The P terminal91P may be referred to as a positive electrode terminal, a high potential power supply terminal, or the like. The P terminal91P is connected to the P wiring54of the front surface metal body52. That is, the P terminal91P is connected to the drain electrode40D of the semiconductor element40H constituting the upper arm9H.

The P terminal91P is connected to the vicinity of one end of the P wiring54in the Y direction. The P terminal91P extends in the Y direction from a connection portion (bonding portion) with the P wiring54, and protrudes to the outside of the sealing body30from the vicinity of the center of the side surface30cin the Z direction. The semiconductor device20of the present embodiment includes two P terminals91P. As shown inFIG.8, one of the P terminals91P is connected to one of the pair of extension portions542, and the other one of the P terminals91P is connected to the other one of the pair of extension portions542. The P terminal91P is disposed at a position close to the notch540, that is, on the inner side in each of the extension portions542so as to be adjacent to the N terminal91N in the plan view. The two P terminals91P are arranged side by side in the X direction. The two P terminals91P are disposed at substantially the same position in the Z direction.

The N terminal91N is electrically connected to the negative electrode terminal of the smoothing capacitor5. The N terminal91N may be referred to as a negative electrode terminal, a low potential power supply terminal, or the like. The N terminal91N is connected to the N wiring64of the front surface metal body62. That is, the N terminal91N is connected to the source electrode40S of the semiconductor element40L constituting the lower arm9L.

The N terminal91N is connected to the vicinity of one end of the N wiring64in the Y direction. The N terminal91N extends in the Y direction from the bonding portion with the N wiring64, and protrudes to the outside of the sealing body30from the vicinity of the center of the side surface30cin the Z direction. The semiconductor device20includes two N terminals91N. One of the N terminals91N is connected to one of the pair of extension portions642, and the other one of the N terminals91N is connected to the other one of the pair of extension portions642. The two N terminals91N are arranged side by side in the X direction. The two N terminals91N are disposed at substantially the same position in the Z direction.

The two N terminals91N are disposed on the outer side of the two P terminals91P in the X direction. In the plan view, one of the N terminals91N is disposed close to one of the P terminals91P, and the other one of the N terminals91N is disposed close to the other one of the P terminals91P. Side surfaces of the N terminal91N and the P terminal91P adjacent to each other in the X direction face each other at a part including a portion protruding from the sealing body30.

The output terminal92is electrically connected to the winding3a(stator coil) of the corresponding phase of the motor generator3. The output terminal92may be referred to as an O terminal, an AC terminal, or the like. As shown inFIGS.3and8, the output terminal92is connected to the relay wiring55of the front surface metal body52of the substrate50. That is, the output terminal92is connected to a connection point between the upper arm9H and the lower arm9L.

The output terminal92is connected to the vicinity of one end of the relay wiring55in the Y direction. The output terminal92extends in the Y direction from the bonding portion with the relay wiring55, and protrudes to the outside of the sealing body30from the vicinity of the center in the Z direction on the side surface30d. The semiconductor device20includes two output terminals92. One of the output terminals92is connected to one of the pair of extension portions552, and the other of the output terminals92is connected to the other one of the pair of extension portions552. The two output terminals92are arranged side by side in the X direction. The two output terminals92are disposed at substantially the same position in the Z direction.

The signal terminals93are electrically connected to a circuit board (not shown) including a drive circuit. The signal terminal93H is electrically connected to the pad40P of the semiconductor element40H via the bonding wire110. The number of the signal terminals93H is not particularly limited. The signal terminal93H includes at least a terminal for applying a drive voltage to at least the gate electrode of the semiconductor element40H. The semiconductor device20of the present embodiment includes two signal terminals93H. The signal terminals93H are disposed at a position overlapping the notch540of the P wiring54in the plan view. In the signal terminal93H, a bonding portion with the bonding wire110faces not the front surface metal body52but the insulating base material51. The two signal terminals93H are arranged side by side in the X direction.

The signal terminal93H extends in the Y direction from the bonding portion with the bonding wire110, and protrudes to the outside of the sealing body30from the vicinity of the center of the side surface30cin the Z direction. At least a part of the protruding portion of the signal terminal93H extends in the same direction as the power supply terminal91. The signal terminal93H is disposed between the two P terminals91P in the X direction. That is, the external connection terminals90protruding from the side surface30care arranged in the order of the N terminal91N, the P terminal91P, the two signal terminals93H, the P terminal91P, and the N terminal91N in the X direction.

The signal terminals93H include a gate terminal93G and a Kelvin source terminal93KS. The two signal terminals93H are arranged in the order of the gate terminal93G and the Kelvin source terminal93KS in the direction from the semiconductor element42H toward the semiconductor element41H. The gate terminal93G is connected to the gate pad GP of each semiconductor element40H via a bonding wire110. The Kelvin source terminal93KS is connected to the Kelvin source pad KSP of each semiconductor element40H via a bonding wire110.

The signal terminal93L is electrically connected to the pad40P of the semiconductor element40L via the bonding wire110. The signal terminal93L includes at least a terminal for applying a drive voltage to the gate electrode of the semiconductor element40L. The semiconductor device20of the present embodiment includes four signal terminals93L. The signal terminals93L are disposed at a position overlapping the notch550of the relay wiring55in the plan view. In the signal terminal93L, the bonding portion with the bonding wire110faces not the front surface metal body52but the insulating base material51. The four signal terminals93L are arranged side by side in the X direction.

The signal terminal93L extends in the Y direction from the bonding portion with the bonding wire110, and protrudes to the outside of the sealing body30from the vicinity of the center in the Z direction on the side surface30d. At least a part of the protruding portion of the signal terminal93L extends in the same direction as the output terminal92. The signal terminals93L are disposed between the two output terminals92in the X direction. That is, the external connection terminals90protruding from the side surface30dare arranged in the order of the output terminal92, the four signal terminals93L, and the output terminal92in the X direction. The four signal terminals93L are arranged in a space defined between the output terminals92.

The signal terminals93L include a gate terminal93G, a Kelvin source terminal93KS, an anode terminal93A, and a cathode terminal93K. The four signal terminals93L are arranged in the order of the gate terminal93G, the Kelvin source terminal93KS, the anode terminal93A, and the cathode terminal93K in the direction from the semiconductor element42L toward the semiconductor element41L. The arrangement of the four signal terminals93L corresponds to the arrangement of the pads40P of the semiconductor element41L.

The gate terminal93G is connected to the gate pad GP of each semiconductor element40L via a bonding wire110. The Kelvin source terminal93KS is connected to the Kelvin source pad KSP of each semiconductor element40L via a bonding wire110. The anode terminal93A is connected to the anode pad AP of the semiconductor element41L via a bonding wire110. The cathode terminal93K is connected to the cathode pad KP of the semiconductor element41L via a bonding wire110.

As described above, the semiconductor device20includes the two signal terminals93H and the four signal terminals93L as the signal terminals93. The signal terminals93H are disposed so that the semiconductor element40is interposed between the signal terminals93H and the signal terminals93L in the Y direction. The two signal terminals93H are arranged side by side in the X direction together with the four power supply terminals91(91P and91N). The four signal terminals93L are arranged side by side in the X direction together with the two output terminals92. In order to suppress an increase in the size in the X direction, the semiconductor device20has two signal terminals93H and four signal terminals93L. Thus, the number of external connection terminals90is six on each of the side surface30cside and the side surface30dside.

In the configuration in which the plurality of semiconductor elements40are thermally connected to each other, it is also possible to guarantee the overheated state of the plurality of semiconductor elements40by using only the temperature sensitive diodes of some of the semiconductor elements40. Therefore, only some of the plurality of semiconductor elements40may be connected to the anode terminal93A and the cathode terminal93K. In this case, the number of signal terminals93can be reduced. However, if the temperature sensitive diodes that are not connected to the anode terminal93A and the cathode terminal93K are set in a so-called floating state in which the temperature sensitive diodes float in potential, there is a concern that a defect may occur in the semiconductor element40.

In the present embodiment, the Kelvin source terminal93KS, which is the signal terminal93H, is connected to the anode pad AP of each semiconductor element40H via the bonding wire110in order to suppress the temperature sensitive diode from being in the floating state in terms of potential. Alternatively, the Kelvin source terminal93KS may be connected to the cathode pad KP of each semiconductor element40H. Similarly, the Kelvin source terminal93KS, which is the signal terminal93L, is connected to the anode pad AP of the semiconductor element42L via the bonding wire110. Alternatively, the Kelvin source terminal93KS may be connected to the cathode pad KP of the semiconductor element42L.

The drain electrode40D of the semiconductor element40is bonded to the front surface metal body52via the bonding material100. The source electrode40S of the semiconductor element40is bonded to the conductive spacer70via the bonding material101. The conductive spacer70is bonded to the front surface metal body62via the bonding material102. The joint portion81is bonded to the front surface metal bodies52and62via the bonding material103. Among the external connection terminals90, the P terminal91P, the N terminal91N, and the output terminal92, which are main terminals, are bonded to the front surface metal bodies52and62via the bonding material104.

The bonding materials100to104have electrical conductivity. For example, solder can be adopted as the bonding materials100to104. An example of the solder is a multi-component lead-free solder containing Cu, Ni, and the like in addition to Sn. Instead of the solder, a sintered bonding member such as sintered silver may be used.

The P terminal91P, the N terminal91N, and the output terminal92may be directly bonded to the corresponding front surface metal bodies52and62without the bonding material104. The P terminal91P, the N terminal91N, and the output terminal92may be directly bonded to the front surface metal bodies52and62by, for example, ultrasonic bonding, friction stir welding, laser welding, or the like. When the joint portion81is provided separately from the substrates50and60, the joint portion81may be directly bonded to the front surface metal bodies52and62.

As described above, in the semiconductor device20, the plurality of semiconductor elements40constituting the upper-lower arm circuit9for one phase are sealed by the sealing body30. The sealing body30integrally seals (covers) the plurality of semiconductor elements40, a part of the substrate50, a part of the substrate60, the plurality of conductive spacers70, the arm connection portion80, and a part of each external connection terminal90. The sealing body30seals the insulating base materials51and61and the front surface metal bodies52and62in the substrates50and60.

The semiconductor element40is disposed between the substrates50and60in the Z direction. The semiconductor element40is interposed between the substrates50and60arranged to face each other. Accordingly, the heat of the semiconductor element40can be dissipated to both sides in the Z direction. The semiconductor device20has a double-sided heat dissipation structure. The back surface50bof the substrate50is substantially flush with the first surface30aof the sealing body30. The back surface60bof the substrate60is substantially flush with the second surface30bof the sealing body30. Since the back surfaces50band60bare exposed surfaces, heat dissipation can be improved.

The two semiconductor elements40H (41H and42H) arranged side by side in the X direction are connected in parallel to each other by the front surface metal bodies52and62, the conductive spacers70, and the bonding materials100to102. The two semiconductor elements40L (41L and42L) arranged side by side in the X direction are connected in parallel to each other by the surface metal bodies52and62, the conductive spacers70, and the bonding materials100to102.

<Arrangement of Front Surface Metal Body>

Next, the arrangement (pattern) of the front surface metal body62will be described with reference toFIGS.3,6,10, and11.FIG.11is an enlarged view of a region XI inFIG.6. The front surface metal body62of the present embodiment is patterned so as to have a predetermined positional relationship with a part of other elements constituting the semiconductor device20.

First, the N wiring64of the front surface metal body62will be described. As shown inFIGS.3,6, and11, the semiconductor element40L and the signal terminal93L, which are electrically connected to each other via the bonding wire110, are arranged in the Y direction. In the Y direction, an end portion64eof the N wiring64is located between an end portion70e1of the conductive spacer70as the bonding target to which the N wiring64is bonded and an end portion40Le of the semiconductor element40L. Each of the end portions40Le,64e, and70e1described above is an end portion on the signal terminal93L side in the Y direction. In the configuration including the conductive spacer70, the bonding target of the N wiring64is the conductive spacer70bonded via the bonding material102. The bonding target may be referred to as a connection target.

The end portion64eof the N wiring64is located between the end portion70e1of the conductive spacer70connected to the semiconductor element41L and the end portion40Le of the semiconductor element41L. Similarly, the end portion64eof the N wiring64is located between the end portion70e1of the conductive spacer70connected to the semiconductor element42L and the end portion40Le of the semiconductor element42L.

The end portion64eof the N wiring64may be at a position closer to the end portion70e1of the conductive spacer70than the end portion61e1of the insulating base material61in the Y direction, or may be at a position substantially coincide with the position of the end portion61e1in the Y direction. The end portion61e1is an end portion on the signal terminal93L side in the Y direction. The end portion64eof the present embodiment is closer to the end70e1than the end61e1. That is, the N wiring64is cut out. As shown inFIGS.6,10, and11, the insulating base material61has an exposed portion61a1exposed from the front surface metal body62. A top portion110tof the bonding wire110connected to the signal terminal93L faces the exposed portion61a1in the Z direction. The top portion110tis closer to the insulating base material61than the facing surface64aof the N wiring64in the Z direction. The top portion110tis located between the end portion40Le and the end portion61e1in the Y direction.

InFIG.11, the position of the end portion64eof the N wiring64in the Y direction is indicated by P1, the position of the end portion40Le of the semiconductor element40L is indicated by P2, and the position of the end portion70e1of the conductive spacer70is indicated by P3. The position P1of the end portion64eis between the position P2of the end portion40Le and the position P3of the end portion70e1.

The relay wiring65also has the same configuration as the N wiring64. As shown inFIGS.3and6, the semiconductor element40H and the signal terminal93H, which are electrically connected to each other via the bonding wire110, are arranged in the Y direction. In the Y direction, the end portion65eof the relay wiring65is located between the end portion70e2of the conductive spacer70as the bonding target to which the relay wiring65is bonded and the end portion40He of the semiconductor element40H. Each of the end portions40He,65e, and70e2described above is an end on the signal terminal93H side in the Y direction. In the configuration including the conductive spacer70, the bonding target of the relay wiring65is the conductive spacer70bonded via the bonding material102.

The end portion65eof the relay wiring65is located between the end portion70e2of the conductive spacer70connected to the semiconductor element41H and the end portion40He of the semiconductor element41H. Similarly, the end portion65eof the relay wiring65is located between the end portion70e2of the conductive spacer70connected to the semiconductor element42H and the end portion40He of the semiconductor element42H.

The end portion65eof the relay wiring65may be located closer to the end portion70e2of the conductive spacer70than the end portion61e2of the insulating base material61in the Y direction, or may be located at a position substantially coincide with the position of the end portion61e2in the Y direction. The end portion61e2is an end portion on the signal terminal93H side in the Y direction. The end portion65eof the present embodiment is closer to the end portion70e2than the end portion61e2. That is, the relay wiring65is cut out. As shown inFIGS.6and10, the insulating base material61has an exposed portion61a2exposed from the front surface metal body62. The top portion110tof the bonding wire110connected to the signal terminal93H faces the exposed portion61a2in the Z direction. The top portion110tis closer to the insulating base material61than the facing surface65aof the relay wiring65in the Z direction. The top portion110tis located between the end portion40He and the end portion61e2in the Y direction.

Summary of First Embodiment

In the present embodiment, the substrate60is used as the second wiring member electrically connected to the source electrode40S, which is the second main electrode. The end portion64eof the N wiring64is located between the end portion70e1of the conductive spacer70, which is the bonding target of the N wiring64, and the end portion40Le of the semiconductor element40L by the patterning of the front surface metal body62of the substrate60. The end portion65eof the relay wiring65is located between the end portion70e2of the conductive spacer70, which is the bonding target of the relay wiring65, and the end portion40He of the semiconductor element40H.

In this manner, the end portions64eand65eof the front surface metal body62are located more to inside than the corresponding end portions40Le and40He of the semiconductor element40. As a result, contact between the front surface metal body62and the bonding wire110can be avoided, and the facing surfaces of the front surface metal body62of the substrate60and the front surface metal body52of the substrate50can be brought close to each other. For example, as shown inFIG.11, the facing surface55aof the relay wiring55and the facing surface64aof the N wiring64can be brought close to each other. That is, it is possible to shorten a facing surface distance D1, which is a distance between the facing surfaces55aand64ain the Z direction.

The broken-line arrows shown inFIG.11indicate the flow of current. As described above, since the facing surfaces55aand64aare close to each other, the effect of magnetic flux cancellation by the currents flowing in opposite directions to each other is enhanced, and thus the inductance can be reduced. In addition, since the heat transfer path from the semiconductor element40to the front surface metal body62is shortened, the thermal resistance can be reduced.

In addition to the facing surfaces55aand64a, the facing surface54aof the P wiring54and the facing surface64aof the N wiring64can be brought close to each other. The facing surface54aof the P wiring54and the facing surface65aof the relay wiring65can be brought close to each other. The facing surface55aof the relay wiring55and the facing surface65aof the relay wiring65can be brought close to each other. Therefore, the inductance can be reduced. Further, it is possible to reduce the thermal resistance.

The heat spreads ideally at an angle of 45 degrees due to the presence of the heat transfer member. In the present embodiment, the end portions64eand65eof the front surface metal body62are located more to outside than the end portions70e1and70e2of the conductive spacer70as the bonding target of the front surface metal body62. The heat of the semiconductor element40can be diffused to the outside of the conductive spacer70(bonding target) in the plan view through the front surface metal body62. That is, in the present embodiment, the heat of the semiconductor element40is diffused in an ideal or nearly ideal state as indicated by the broken-line arrow inFIG.11. Therefore, it is possible to reduce the thermal resistance. As described above, according to the semiconductor device20of the present embodiment, it is possible to reduce the thermal resistance while reducing the inductance.

In the present embodiment, the arrangement of the front surface metal body62described above is adopted in the configuration including the conductive spacer70. Thus, the facing surfaces of the surface metal bodies52and62can be brought close to each other, that is, the thickness T1of the conductive spacer70can be reduced. Since the conductive spacer70is thin, the thermal resistance can be reduced.

In the present embodiment, the top portion110tof the bonding wire110connected to the signal terminal93L faces the exposed portion61a1of the insulating base material61in the Z direction. The top portion110tof the bonding wire110connected to the signal terminal93H faces the exposed portion61a2of the insulating base material61in the Z direction. In other words, the insulating base material61(and the back surface metal body63) is disposed up to the position outside of the end portions64eand65eof the front surface metal body62. Accordingly, when heat is transferred from the front surface metal body62to the insulating base material61and the back surface metal body63, the heat is also diffused to the outside of the front surface metal body62in the plan view. Therefore, the thermal resistance can be further reduced.

Modification

As shown inFIG.12, the end portion64eof the N wiring64, which is the front surface metal body62, may be located between the end portion40Pe of the pad40P of the semiconductor element40L on the source electrode40S side and the end portion40Le of the semiconductor element40L.FIG.12corresponds toFIG.11. InFIG.12, the position of the end portion40Pe is indicated by P4. The position P1of the end portion64eis between the position P2of the end portion40Le and the position P4of the end portion40Pe. According to this, heat is easily diffused to the outside of the conductive spacer70(bonding target) in the plan view, and the thermal resistance can be further reduced.

The same applies to the end portion65eof the relay wiring65. Although not illustrated, the end portion65eof the relay wiring65may be located between the end portion of the pad40P of the semiconductor element40H on the source electrode40S side and the end portion40He of the semiconductor element40H.

Although an example in which the semiconductor device20includes the conductive spacer70has been described, the present disclosure is not limited thereto. A configuration may be adopted in which the conductive spacer70is not interposed between the semiconductor element40and the front surface metal body62, and the front surface metal body62is bonded to the source electrode40S via a bonding material. In this case, the metal body as the bonding target to which the front surface metal body62is bonded is the source electrode40S.

As shown inFIG.13, the front surface metal body62may be thicker than the back surface metal body63.FIG.13corresponds toFIG.11. The thicker the front surface metal body62is, the shorter the distance D2between the opposing surfaces can be. As a result, the effect of magnetic flux cancellation is enhanced, and the inductance can be further reduced. When the thickness of the front surface metal body62is increased, the conductive spacer70can be easily removed as shown inFIG.13. InFIG.13, the front surface metal body62is bonded to the source electrode40S via the bonding material102A. Of course, in the configuration including the conductive spacer70, the front surface metal body62may be thicker than the back surface metal body63.

As shown inFIG.13, the end portion64eof the N wiring64is located between the end portion40Se1of the source electrode40S, which is the bonding target, and the end portion40Le of the semiconductor element40L. The end portion40Se1is an end portion on the signal terminal93L side in the Y direction. InFIG.13, the position of the end portion40Se1is indicated by P5. The position P1of the end portion64eis between the position P2of the end portion40Le and the position P5of the end portion40Se1. The end portion65eof the relay wiring65is located between the end portion40Se2(seeFIG.3) of the source electrode40S as the bonding target and the end portion40He of the semiconductor element40H. With such an arrangement, even in the configuration in which the bonding target is the source electrode40S, the same effect as that of the configuration in which the bonding target is the conductive spacer70can be achieved.

The end portions64eand65eof the front surface metal body62are not limited to the examples described above. For example, as shown inFIG.14, the front surface metal body62may be formed with notches620and621, and the above-described end portions64eand65emay be each provided by at least a part of side portions defining the corresponding notch620and621. InFIG.14, as an example, the bottom sides of the notches620and621are the end portions64eand65e.

The notch620is locally provided at an end portion of the N wiring64on the signal terminal93L side so as to avoid contact with the bonding wire110connected to the signal terminal93L. The notch621is locally provided at an end portion of the relay wiring65on the signal terminal93H side so as to avoid contact with the bonding wire110connected to the signal terminal93H. In this manner, the front surface metal body62may have a locally notched shape. According to this, it is possible to reduce the thermal resistance as compared with a shape in which the end portion is uniformly cut out.

The arrangement of the pads40P is not limited to the example described above. For example, as shown inFIG.15, the pads40P may be provided so as to be biased to the periphery of one of four corners of the semiconductor element40having a substantially rectangular planar shape. In the two semiconductor elements40L having a common structure and arranged side by side in the X direction, the semiconductor element42L is arranged to be rotated by 90 degrees with respect to the arrangement of the semiconductor element41L. In the two semiconductor elements40H having a common structure and arranged side by side in the X direction, the semiconductor element42H is arranged so as to be rotated by 90 degrees with respect to the arrangement of the semiconductor element41H. Each of the source electrode40S and the conductive spacer70has a shape in which one of four corner portions of a substantially rectangular shape in the plan view is cut out so as to avoid the pads40P.

InFIG.15, in the arrangement of the pads40P described above, notches622and623are formed in the front surface metal body62, and the end portions64eand65edescribed above are each provided by at least a part of side portions defining the corresponding notch622and623. The notch622is locally provided at the end portion of the N wiring64on the signal terminal93L side so that the end portion64esatisfies the above-described positional relationship while avoiding contact between the N wiring64and the bonding wire110connected to the signal terminal93L. The notch623is locally provided at the end portion of the relay wiring65on the signal terminal93H side so that the end portion65esatisfies the above-described positional relationship while avoiding contact between the relay wiring65and the bonding wire110connected to the signal terminal93H. In this way, by forming the front surface metal body62in the shape in which the front surface metal body62is locally cut out, even when the pads40P are arranged unevenly, it is possible to reduce the thermal resistance while reducing the inductance.

Second Embodiment

The present embodiment is a modification of the preceding embodiment as a basic configuration and may incorporate description of the preceding embodiment. In the preceding embodiment, the bonding wire110is provided so as not to be in contact with the insulating base material61. Alternatively, the bonding wire110may be provided so as to be in contact with the insulating base material61.

FIG.16is a cross-sectional view showing an example of the semiconductor device20according to the present embodiment.FIG.16corresponds toFIG.11. In the semiconductor device20shown inFIG.16, the bonding wire110is in contact with the insulating base material61. The bonding wire110has a contact portion110cthat is a portion in contact with the insulating base material61. The bonding wire110is pressed against the insulating base material61and deformed. By this deformation, the contact portion110cextends substantially parallel to the surface of the insulating base material61, for example. The bonding wire110connected to the signal terminal93L is in contact with the exposed portion61a1of the insulating base material61. Although not shown, the bonding wire110connected to the signal terminal93H is in contact with the exposed portion61a2of the insulating base material61.

The semiconductor device20does not include the conductive spacer70. The front surface metal body62of the substrate60is bonded to the source electrode40S, which is the bonding target, via the bonding material102A. The N wiring64is bonded to the source electrode40S of the semiconductor element40L. Although not shown, the relay wiring65is bonded to the source electrode40S of the semiconductor element40H.

The other configurations are the same as the configurations described in the preceding embodiment. For example, the end portion64eof the N wiring64is located between the end portion40Se1of the source electrode40S, which is the bonding target, and the end portion40Le of the semiconductor element40L. Although not shown, the end portion65eof the relay wiring65is located between the end portion40Se2of the source electrode40S, which is the bonding target, and the end portion40He of the semiconductor element40H.

FIG.17is a cross-sectional view showing an example of a method for manufacturing the semiconductor device20shown inFIG.16.FIG.17corresponds toFIG.16.FIG.17shows a process of electrically connecting the semiconductor element40and the substrate60.

First, each element constituting the semiconductor device20is prepared. In the present embodiment, the substrate60in which the front surface metal body62is patterned so that the end portions64eand65esatisfy the above-described positional relationship is prepared.

Next, a first connection step is performed. In this step, the semiconductor element40is disposed on the front surface metal body52of the substrate50such that the drain electrode40D faces the front surface metal body52. Then, the drain electrode40D and the front surface metal body52are electrically connected to each other. In the present embodiment, the drain electrode40D and the front surface metal body52are bonded by the bonding material100. In the first connection step, the joint portion81and the front surface metal body52are bonded by the bonding material103. The P terminal91P and the output terminal92are bonded to the front surface metal body52by the bonding material104.

Next, a wire bonding step is performed. In this step, the pads40P of the semiconductor element40and the signal terminals93are bonded via the bonding wires110. Specifically, the signal terminal93L and the corresponding pad40P of the semiconductor element40L are connected via the bonding wire110. The signal terminal93H and the corresponding pad40P of the semiconductor element40H are connected via the bonding wire110.

Next, a second connection step is performed. In this step, the source electrode40S of the semiconductor element40and the substrate60as the second wiring member are electrically connected to each other. In the present embodiment, the source electrode40S and the front surface metal body62are bonded via the bonding material102A. At this time, the substrate50to which the semiconductor element40is connected and the substrate60are relatively displaced in directions in which the facing surfaces of the surface metal bodies52and62approach each other.

Due to this displacement, the exposed portions61a1and61a2of the insulating base material61exposed from the front surface metal body62come into contact with the top portion110tof the bonding wire110. As shown inFIG.17, the exposed portion61a1of the insulating base material61is in contact with the bonding wire110connected to the signal terminal93L. The exposed portion61a2of the insulating base material61is in contact with the bonding wire110connected to the signal terminal93H.

Then, from the contact state, the facing surfaces of the surface metal bodies52and62, for example, the facing surfaces55aand64ashown inFIG.17are further displaced in the approaching directions. The bonding wire110is pressed and deformed by the insulating base material61(substrate60), and the height of the bonding wire110becomes lower than that at the time of wire bonding. In this deformed state, the source electrode40S and the front surface metal body62are bonded to each other. In the second connection step, the joint portion81and the front surface metal body62are bonded to each other via the bonding material103. The N terminal91N and the front surface metal body62are bonded via the bonding material104.

Next, a molding step of the sealing body30is performed. For example, the sealing body30is molded by the above-described transfer molding method. After the molding, for example, cutting is performed. The sealing body30is cut together with parts of the back surface metal bodies53and63of the substrates50and60. Thus, the back surfaces50band60bare exposed from the sealing body30. The back surface50bis substantially flush with the first surface30aof the sealing body30, and the back surface60bis substantially flush with the second surface30b. Note that the sealing body30may be molded in a state in which the back surfaces50band60bare pressed against the cavity wall surface of the molding die and brought into close contact therewith. In this case, when the sealing body30is molded, the back surfaces50band60bare exposed from the sealing body30. Therefore, cutting after the molding is unnecessary.

Next, unnecessary portions such as tie bars are removed from the lead frame. In this way, the semiconductor device20described above can be obtained.

Summary of Second Embodiment

The positions of the end portions64eand65eof the front surface metal body62in the present embodiment are the same as those in the preceding embodiment. Therefore, the same effects as those of the configurations described in the preceding embodiment can be achieved. That is, it is possible to reduce the thermal resistance while reducing the inductance.

In the present embodiment, as described above, the insulating base material61of the substrate60is pressed against the bonding wire110when the source electrode40S and the front surface metal body62are bonded. The bonding wire110is pressed and deformed by the insulating base material61(substrate60), and the height of the bonding wire110becomes lower than that at the time of wire bonding. With the configuration in which the bonding wires110are in contact with the exposed portions61a1and60a2of the insulating base material61, the distance D1between the facing surfaces can be further shortened. Thereby, it may be possible to reduce the inductance. In addition, the thermal resistance can be further reduced. In addition, a configuration in which the conductive spacer70is excluded can be easily obtained. For example, the conductive spacer70can be easily removed without increasing the thickness of the front surface metal body62as shown inFIG.13.

Further, since the bonding wires110are held between the signal terminals93, the pads40P, and the insulating base material61, it is possible to suppress the occurrence of wire sweep at the time of molding the sealing body30.

FIG.18shows the results of the electromagnetic field simulation. The vertical axis represents inductance in arbitrary units (a.u.). RE1and RE2indicate the results of the reference examples, and PE1and PE2indicate the results of the configuration examples (the present examples) equivalent to the present embodiment. Unlike the present examples, the reference examples include a conductive spacer. In the present example, since the conductive spacer is not provided, the distance between the facing surfaces of the front surface metal bodies is reduced by the thickness of the conductive spacer. In RE1and PE1, the insulating base materials51and61were made of nitride-based ceramic. In RE2and PE2, the insulating base materials51and61were made of resin.

As shown inFIG.18, according to the present examples (PE1, PE2), it is apparent that the inductance can be reduced by about 20%, as compared with the reference examples (RE1, RE2), in any cases of using either ceramic or resin.

Even if the bonding wire110is in contact with the exposed portions61a1and61a2of the insulating base material61in the second connection step described above, the bonding wire110may be slightly separated from the exposed portion61a1or61a2in a step subsequent to the second connection step, for example, a molding step. Therefore, as shown inFIG.19, the semiconductor device20may have a slight gap having a distance D2of 0.1 mm or less between the bonding wire110and the exposed portion61a1or61a2of the insulating base material61. Since the distance D1between the facing surfaces is determined in the second connection step, the same effect as that of the configuration shown inFIG.16can be obtained.

Modification

The above-described manufacturing method may be applied to a configuration including the conductive spacer70. That is, in the configuration including the conductive spacer70, the bonding wire110may be brought into contact with the exposed portion61a1or61a2of the insulating base material61, or may have a slight gap of 0.1 mm or less. The thickness of the conductive spacer70can be reduced.

The configuration described in the present embodiment can be combined with any configuration of the first embodiment and the modification.

The example in which the end portions64eand65eof the front surface metal body62are located between the end portions40Se1and40Se2of the source electrode40S and the end portions40Le and40He of the semiconductor element40has been described, but the present disclosure is not limited thereto. For example, as shown inFIG.20, the position P1of the end portion64eof the N wiring64may be located more to inside than the position P5of the end portion40Se1of the source electrode40S as the bonding target. The end portion40Se1is located between the end portions40Le and64ein the Y direction. As described above, according to the present embodiment, when the source electrode40S (second main electrode) and the substrate60(second wiring member) are electrically connected, the bonding wire110is pressed by the insulating base material61of the substrate50. As a result, the distance D1between the opposing surfaces can be shortened. Therefore, even if the end portions64eand65eof the front surface metal body62do not have the above-described positional relationship, the inductance and the thermal resistance can be effectively reduced.

Third Embodiment

The present embodiment is a modification of the preceding embodiments as a basic configuration and may incorporate description of the preceding embodiments. In the preceding embodiments, the semiconductor device20includes two semiconductor elements40H and two semiconductor elements40L, and in which the semiconductor elements40H are arranged in the X direction, the semiconductor elements40L are arranged in the X direction, and the semiconductor element40H and the semiconductor element40L are arranged in the Y direction. In addition, the P terminal91P, the N terminal91N, and the signal terminal93H protrude from one of the side surfaces of the sealing body30in the Y direction, and the output terminal92and the signal terminal93L protrude from the opposite side surface.

However, the number and arrangement of the semiconductor elements40, the arrangement of the external connection terminals90, and the like are not limited to the example described above. For example, each arm may be constituted by one semiconductor element40instead of the plurality of semiconductor elements40. Instead of the configuration in which the signal terminals93H and93L are arranged so as to interpose the semiconductor element40therebetween, the signal terminal93H and the signal terminal93L may be arranged side by side.

FIGS.21to24show a semiconductor device20of the present embodiment.FIG.21is a perspective view of the semiconductor device20.FIG.22is a plan view ofFIG.21viewed along the direction Z2.FIG.22is a transparent view showing the internal structure.FIG.23is a cross-sectional view taken along a line XXIII-XXIII inFIG.22.FIG.24is a cross-sectional view taken along a line XXIV-XXIV inFIG.22.

The semiconductor device20of the present embodiment constitutes one upper-lower arm circuit9, that is, the upper-lower arm circuit9for one phase, as in the preceding embodiment. The semiconductor device20includes elements similar to those of the configuration described in the preceding embodiment (seeFIGS.2to11). The semiconductor device20includes a sealing body30, a semiconductor element40, substrates50and60, a conductive spacer70, an arm connection portion80, and an external connection terminal90. Hereinafter, portions different from the configurations described in the preceding embodiment will be mainly described.

The sealing body30seals a part of other elements constituting the semiconductor device20as in the preceding embodiment. As shown inFIG.21, the sealing body30has a substantially rectangular shape as the planar shape. The sealing body30has a first surface30aand a second surface30bin the Z direction. Side surfaces connecting the first surface30aand the second surface30binclude two side surfaces30gand30hfrom which the external connection terminals90protrude. The side surface30his a surface opposite to the side surface30gin the Y direction.

The semiconductor element40includes one semiconductor element40H constituting the upper arm9H and one semiconductor element40L constituting the lower arm9L. The semiconductor device20includes two semiconductor elements40. The configurations of the semiconductor elements40H and40L are common to each other. As shown inFIG.22, the semiconductor elements40H and40L are arranged in the X direction. The semiconductor elements40are disposed at substantially the same position in the Z direction. The drain electrode40D of each of the semiconductor elements40faces the substrate50. The source electrode40S of each of the semiconductor elements40faces the substrate60.

The substrates50and60are disposed so as to interpose the plurality of semiconductor elements40in the Z direction. The substrates50and60are disposed such that at least portions thereof face each other in the Z direction. The substrates50and60encompass all of the plurality of semiconductor elements40(40H and40L) in the plan view.

Similar to the preceding embodiment, the substrate50includes an insulating base material51, a front surface metal body52, and a back surface metal body53. The substrate60includes an insulating base material61, a front surface metal body62, and a back surface metal body63. The front surface metal body52includes a P wiring54and a relay wiring55. The P wiring54and the relay wiring55are electrically separated by a predetermined interval (gap).

The P wiring54is connected to the P terminal91P and the drain electrode40D of the semiconductor element40H. The P wiring54electrically connects the P terminal91P and the drain electrode40D of the semiconductor element40H. The P wiring54has a substantially rectangular planar shape defining the longitudinal direction in the Y direction. The relay wiring55is connected to the drain electrode40D of the semiconductor element40L, the arm connection portion80, and the output terminal92. The relay wiring55has a substantially rectangular planar shape.

The P wiring54and the relay wiring55are arranged side by side in the X direction. The semiconductor element40L is mounted on one end side of the relay wiring55in the X direction, specifically, on a side far from the P wiring54. The joint portion81constituting the arm connection portion80is mounted on the other end side of the relay wiring55in the X direction, specifically, on the side close to the P wiring54. The P terminal91P is connected to the vicinity of one end of the P wiring54in the Y direction. The output terminal92is connected to the vicinity of one end of the relay wiring55in the Y direction. The P terminal91P and the output terminal92are disposed on the same side of the semiconductor element40in the Y direction.

The front surface metal body62includes an N wiring64and a relay wiring65. The N wiring64and the relay wiring65are electrically separated by a predetermined interval (gap). The N wiring64is connected to the N terminal91N and the source electrode40S of the semiconductor element40L. The relay wiring65is connected to the source electrode40S of the semiconductor element40H and the arm connection portion80.

The N wiring64has a base portion643and an extension portion644. The N wiring64has substantially an L-shape as the planar shape. The base portion643has substantially a rectangular shape as the planar shape. The base portion643encompasses a part of the semiconductor element40L in the plan view. The base portion643encompasses the source electrode40S of the semiconductor element40L. The extension portion644connects to one side of the base portion643having substantially the rectangular shape in the plan view. The extension portion644extends from a side of the base portion643facing the relay wiring65toward the base portion653in the X direction.

In the N wiring64(base portion643), an end portion64ewhich is a side on the signal terminal93L side is located between the end portion40Le of the semiconductor element40L and the end portion70eof the conductive spacer70as the bonding target in the Y direction.

The relay wiring65includes a base portion653and an extension portion654. The relay wiring65has substantially an L-shape as the planar shape. The base portion653has substantially a rectangular shape as the planar shape. The base portion653encompasses a part of the semiconductor element40H in the plan view. The base portion653encompasses the source electrode40S of the semiconductor element40L. The extension portion654connects to one side of the base portion653having substantially the rectangular shape as the planar shape The extension portion654extends from a side of the base portion653facing the N wiring64toward the base portion643in the X direction. At least a part of the extension portion654overlaps the relay wiring55in the plan view.

In the relay wiring65, an end portion65e, which is a side on the signal terminal93H side, is located between the end portion40He of the semiconductor element40H and the end portion70eof the conductive spacer70as the bonding target in the Y direction.

The N wiring64and the relay wiring65are arranged side by side in the X direction. The base portion643and the base portion653are arranged in the X direction. The source electrode40S of the semiconductor element40L is electrically connected to the base portion643. The source electrode40S of the semiconductor element40H is electrically connected to the base portion653. The extension portion644and the extension portion654are arranged in the Y direction. The N terminal91N is connected to the extension portion644. The joint portion81is connected to the extension portion654.

The conductive spacer70is interposed between the source electrode40S of the semiconductor element40and the substrate60. The conductive spacers70are individually connected to the source electrodes40S of the semiconductor elements40.

The arm connection portion80electrically connects the relay wiring55and the relay wiring65. The arm connection portion80is provided between the semiconductor element40H and the semiconductor element40L in the X direction. The arm connection portion80is provided in an overlapping region between the relay wiring55and the relay wiring65(extension portion654) in the plan view. The arm connection portion80of the present embodiment is configured to include the joint portion81and the bonding material103as in the preceding embodiment. The joint portion81is a metal columnar body. In the Z direction, the bonding material103is interposed between one of the end portions of the joint portion81and the relay wiring55, and the bonding material103is interposed between the other one of the end portions of the joint portion81and the relay wiring65. Alternatively, the joint portion81may integrally connect to at least one of the front surface metal bodies52and62. The arm connection portion80may not include the joint portion81.

The external connection terminal90includes a power supply terminal91, an output terminal92, and a signal terminal93. The power supply terminal91includes a P terminal91P and an N terminal91N. Hereinafter, the P terminal91P, the N terminal91N, and the output terminal92may be referred to as main terminals91P,91N, and92. The signal terminal93includes a signal terminal93H on the upper arm9H side and a signal terminal93L on the lower arm9L side.

The P terminal91P is connected to the vicinity of one end of the P wiring54in the Y direction. The P terminal91P extends outward in the Y direction from the connection portion with the P wiring54. A portion of the P terminal91P is covered with the sealing body30, and the remaining portion protrudes from the sealing body30. The P terminal91P protrudes to the outside of the sealing body30from the vicinity of the center of the side surface30gin the Z direction.

The N terminal91N is connected to the vicinity of one end of the N wiring64in the Y direction. The N terminal91N extends outward in the Y direction from the connection portion with the N wire64. A part of the N terminal91N is covered with the sealing body30, and the remaining part protrudes from the sealing body30. The N terminal91N protrudes to the outside of the sealing body30from the vicinity of the center of the side surface30gin the Z direction.

The output terminal92is connected to the vicinity of one end of the relay wiring55in the Y direction. The output terminal92extends outward in the Y direction from the connection portion with the relay wiring55. A portion of the output terminal92is covered with the sealing body30, and the remaining portion protrudes from the sealing body30. The output terminal92protrudes to the outside of the sealing body30from the vicinity of the center of the side surface30gin the Z direction.

The three main terminals91P,91N, and92are arranged side by side in the X direction. The main terminals91P,91N, and92are arranged in the order of the P terminal91P, the N terminal91N, and the output terminal92in the X direction. Side surfaces of the P terminal91P and the N terminal91N, which are the power supply terminals91, face each other at a part including portions protruding from the sealing body30.

The signal terminal93is electrically connected to the pad40P of the corresponding semiconductor element40via the bonding wire110. The signal terminal93H is connected to the pad40P of the semiconductor element40H via a bonding wire110. The signal terminal93L is connected to the pad40P of the semiconductor element40L via a bonding wire110. The signal terminal93extends outward in the Y direction and protrudes to the outside of the sealing body30from the vicinity of the center of the side surface30hin the Z direction. The signal terminal93is extended on the side opposite to the main terminals91P,91N, and92in the Y direction. The semiconductor element40is disposed between the main terminals91P,91N, and92and the signal terminal93in the Y direction.

The semiconductor device20includes two guide frames94. One of the guide frames94connects to the P terminal91P. The other guide frame94connects to the output terminal92. These guide frames94are portions that connect an outer peripheral frame holding the signal terminals93and the main terminals91P and92in a state before unnecessary portions of the lead frame are removed. A part of the guide frame94connecting to the P terminal91P is connected to the P wiring54. A part of the guide frame94connecting to the output terminal92is connected to the relay wiring55. The guide frame94can have the same connection structure (bonding structure) as the main terminals91P,91N, and92.

As described above, in the semiconductor device20of the present embodiment, the plurality of semiconductor elements40constituting the upper-lower arm circuit9for one phase are sealed by the sealing body30. The sealing body30integrally seals the plurality of semiconductor elements40, a part of the substrate50, a part of the substrate60, the plurality of conductive spacers70, the arm connection portion80, and a part of each of the external connection terminals90. The sealing body30seals the insulating base materials51and61and the front surface metal bodies52and62of the substrates50and60.

The semiconductor element40is disposed between the substrates50and60in the Z direction. The semiconductor element40is interposed between the substrates50and60arranged to face each other. Accordingly, the heat of the semiconductor element40can be dissipated to both sides in the Z direction. The semiconductor device20has a double-sided heat dissipation structure. The back surface50bof the substrate50is substantially flush with the first surface30aof the sealing body30. The back surface60bof the substrate60is substantially flush with the second surface30bof the sealing body30. Since the back surfaces50band60bare exposed surfaces, heat dissipation can be improved.

Summary of Third Embodiment

The positions of the end portions64eand65eof the front surface metal body62in the present embodiment are the same as those in the preceding embodiments. Therefore, the same effects as those of the configurations described in the preceding embodiments can be achieved. That is, it is possible to reduce the thermal resistance while reducing the inductance.

The configuration described in the present embodiment can be combined with any configuration of the first embodiment, the second embodiment, and the modification. For example, in the present embodiment, notches620and621may be provided in the front surface metal body62, as shown inFIG.14, The pads40P may be provided so as to be biased to one of the corners of the rectangle, and the notches622and623may be provided in the front surface metal body62, as shown inFIG.15. The bonding wires110may be brought into contact with the exposed portions61a1and61a2of the front surface metal body62, as shown inFIG.16. The conductive spacer70may be omitted.

Other Embodiments

The present disclosure in the specification, the drawings and the like is not limited to the embodiments exemplified hereinabove. The disclosure encompasses the illustrated embodiments and modifications by those skilled in the art based thereon. For example, the present disclosure is not limited to the combinations of components and/or elements shown in the embodiments. The present disclosure may be implemented in various combinations thereof. The present disclosure may have additional parts that may be added to the embodiments. The present disclosure encompasses modifications in which components and/or elements are omitted from the embodiments. The present disclosure encompasses the replacement or combination of components and/or elements between one embodiment and another. The technical scopes disclosed in the present disclosure are not limited to the description of the embodiments. The several technical scopes disclosed are indicated by the description of the claims, and should be further understood to include meanings equivalent to the description of the claims and all modifications within the scope.

The disclosure in the specification, drawings and the like is not limited by the description of the claims. The disclosure in the specification, the drawings, and the like encompasses the technical ideas described in the claims, and further extends to a wider variety of technical ideas than those in the claims. Hence, various technical ideas can be extracted from the disclosure of the specification, the drawings, and the like without being bound by the description of the claims.

When an element or layer is referred to as being “on,” “coupled,” “connected,” or “combined,” it may be directly on, coupled to, connected to, or combined with the other element or layer, or further, intervening elements or layers may be present. In contrast, when an element is described as “directly disposed on,” “directly coupled to,” “directly connected to”, or “directly combined with” another element or another layer, there are no intervening elements or layers present. Other terms used to describe the relationships between elements (for example, “between” vs. “directly between”, and “adjacent” vs. “directly adjacent”) should be interpreted similarly. As used herein, the term “and/or” includes any combination and all combinations relating to one or more of the related listed items. For example, the term A and/or B includes only A, only B, or both A and B.

Spatially relative terms such as “inner,” “outer,” “back,” “below,” “low,” “above,” and “high” are utilized herein to facilitate description of one element or feature's relationship to another element (s) or feature (s) as illustrated. Spatial relative terms can be intended to include different orientations of a device in use or operation, in addition to the orientations illustrated in the drawings. For example, when a device in a drawing is turned over, elements described as “below” or “directly below” other elements or features are oriented “above” the other elements or features. Therefore, the term “below” can include both above and below. The device may be oriented in the other direction (rotated 90 degrees or in any other direction) and the spatially relative terms used herein are interpreted accordingly.

The vehicle drive system1is not limited to the configurations of the embodiments described above. Although the example in which the vehicle drive system1includes one motor generator3has been described, the present disclosure is not limited thereto. A plurality of motor generators may be provided. Although the example in which the electric power conversion device4includes the inverter6as a power conversion circuit has been described, the present disclosure is not limited thereto. For example, the electric power conversion device4may include a plurality of inverters. The electric power conversion device4may include at least one inverter and a converter. The electric power conversion device4may include only the converter.

The example in which the semiconductor element40includes the MOSFET11as a switching element has been described, but the present disclosure is not limited thereto. For example, an IGBT may be employed. IGBT is an abbreviation of Insulated Gate Bipolar Transistor.

Although the substrate50is exemplified as the wiring member connected to the drain electrode40D, the wiring member is not limited thereto. In the configuration in which the wiring member is not limited to the substrate50, a metal plate (lead frame) may be adopted instead of the substrate50. In the case of the wiring member made of the metal plate, a first metal plate to which the drain electrode40D of the semiconductor element40H is connected and a second metal plate to which the drain electrode40D of the semiconductor element40L is connected are disposed on the drain electrode40D side.

The example in which one semiconductor device20constitutes the upper-lower arm circuit9(two arms) for one phase has been described, but the present disclosure is not limited thereto. For example, the present disclosure can be applied to a semiconductor device in which one semiconductor device20constitutes one arm. The number of arms configured by one semiconductor device20is not particularly limited.