Integrated circuit and related audio amplifier

An integrated circuit includes a die that includes a circuit configured to generate a PWM signal in response to a first clock signal, and a first set of pads configured to provide amplified PWM signals to external filters. An amplifier stage is configured to provide the amplified PWM signals. The die includes two pads configured to be coupled to an external inductor, and a second set of pads configured to provide regulated voltages. An electronic converter circuit is configured to generate the regulated voltages to supply the amplifier stage. The electronic converter circuit includes a control circuit configured to drive electronic switches in response to a second clock signal to regulate the regulated voltages to a respective target value. The die includes a control block to synchronize the switching activity of the electronic switches with the switching activity of the amplifier stage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Italian Patent Application No. 102018000002466, filed on Feb. 7, 2018, which application is hereby incorporated herein by reference.

TECHNICAL FIELD

The present invention relates generally to an electronic system and method, and, in particular embodiments, to an integrated circuit and related audio amplifier.

BACKGROUND

FIG. 1shows a typical audio system. In the example considered, the system comprises an audio signal generator10, such as a radio, CD or MP3 player, generating an analog audio signal AS to be sent to at least one speaker SPK.

In the example considered, an audio amplifier20is connected between the audio signal generator10and the speaker SPK, which is configured to generate an amplified audio signal AAS by amplifying the analog audio signal AS provided by the audio signal generator10.

For example,FIG. 2shows a possible implementation of a so-called class-D audio amplifier20. Specifically, in the example considered, the audio amplifier20comprises a waveform generator202generating a periodic triangular waveform signal TS, having typically a frequency between 250 kHz and 2.5 MHz. The triangular waveform signal TS is sent together with the audio signal AS to a comparator204, which compares the audio signal AS with the triangular waveform signal TS thereby generating a square wave signal DS, whose duty-cycle varies as a function of the amplitude of the audio signal AS. The square wave signal DS is then amplified by an amplifier stage206, thereby generating an amplified square wave signal ADS.

For example,FIG. 3shows an example of the amplifier stage206, which comprises a half-bridge comprising two electronic switches SW1and SW2, such as (n-channel) Field Effect Transistors (FET), connected in series between two terminals210and212adapted to receive a DC supply voltage Vbat, such as a voltage provided by a battery. Usually, the (negative) terminal212represent a ground GND. In the example considered, the control terminals of the switches SW1and SW2(e.g., the gate terminals of respective transistors) are driven as a function of the digital signal DS. For example, in the example considered are shown two driver circuits2062and2064for the electronic switches SW1and SW2, and a control circuit2060configured to generate the control signals for the driver circuits2062and2064as a function of the digital signal DS. Substantially, the amplifier206is configured to convert the amplitude of the digital signal DS to the value of the voltage received at the terminals210and212, which generally is greater than the voltage of the digital signal DS. For example, the level of the signal DS may be 3 VDC and the voltage Vbatmay be 12 VDC. Accordingly, the square wave signal ADS at the intermediate point between the two switches SW1and SW2corresponds to an amplified version of the signal DS.

Finally, the amplified square wave signal ADS is sent to a low-pass or bandpass filter208, which removes at least the high-frequency spectrum from the amplified signal square wave signal ADS, thereby generating an amplified audio signal AAS, which is proportional to the original audio signal AS.

For example,FIG. 4shows an example a LC filter208. Generally, the filter stage208comprises two input terminals for receiving the signal ADS provided by the amplifier stage206, e.g., the input terminals are connected the intermediate point of the half-bridge and the ground GND shown inFIG. 3. Moreover, the filter stage208comprises two output terminals for connection to the speaker SPK. Specifically, in the example considered, the first input terminal is connected to the first output terminal via an inductor L, and the second input terminal and the second output terminal are short circuited to ground GND. Finally, a capacitance C is connected in parallel with the output, i.e., between the output terminals. Substantially similar (active or passive) low-pass or bandpass filters208are provided in most audio amplifier circuits and/or may be integrated also within the speaker SPK.

Accordingly, a class-D amplifier is based on the fact that the switching frequency of the amplifier20is significantly higher than the usual audio band (between 20 Hz and 20 kHz) and accordingly the high switching frequency may be filtered with the filter stage208, thereby reconstructing the profile of the original audio signal AS.

In the context of digital audio data, the signal generator10may comprise an analog-to-digital converter (ADC) for generating the signal AS or the signal generator10may provide directly the digital signal DS. Accordingly, the blocks202and204are purely optional.

Generally, the audio system may also use a plurality of speakers SPK, such as two or four, with respective audio amplifiers20using different signals AS/DS.

Those of skill in the art will appreciate that the audio system usually comprises also one or more electronic converters30configured to generate the regulated supply voltages for the various blocks of the audio system, such as the supply voltage for the audio signal generator10and possibly the blocks202and204in order to generate the digital/binary signal DS, the supply signals for the control circuit2060and the driver circuits2062and2064, etc.

For example, usually the converter30comprises a DC/DC converter, such as a converter configured to convert the voltage Vbatinto a lower supply voltage, such as a voltage between 1.5 and 3.3 VDC, e.g., 1.8 VDC, used by the digital circuits of the audio system and/or the low power analog processing circuits. Similarly, additional regulated voltages may be generated for the driver circuits2062and2064, such as 4.5 VDC for the driver circuit2064.

In case of a car radio, the design of the various components of the audio system may be challenging, because of the large variations of voltage Vbatof the automotive battery. For example, during crank and dump, a typical battery voltage of 14.4V may sharply (in less than 2 ms) drop down to 4-5V or rise up to 40V. For a proper operation, the electronic converter30should thus be able to control the supply voltages of the audio system for all battery conditions.

SUMMARY

Various embodiments relate to integrated circuits for implementing an audio amplifier, such as a class-D audio amplifier.

In various embodiments, the die of the integrated circuit comprises a circuit configured to generate at least one PWM signal, an amplifier stage, an electronic converter circuit, and a control block.

Specifically, in various embodiments, the circuit is configured to generate the at least one PWM signal in response to at least one first clock signal. For example, the circuit may comprise for each of the at least one PWM signal, a respective terminal for receiving an analog audio signal, a triangular waveform generator configured to generate a triangular waveform signal in response to a respective first clock signal, and a comparator configured to generate the respective PWM signal by comparing the analog audio signal with the triangular waveform signal. Generally, the circuit may also comprise a signal generator configured to generate the analog audio signal or directly the at least one PWM signal. Similarly, the die may comprise a pad and a communication interface configured to receive digital audio data, and a processing circuit configured to convert the digital audio data into the analog audio signal or directly the at least one PWM signal.

In various embodiments, the amplifier stage has associated a first set of pads of the die, where each pad of the first set of pads is configured to provide a respective amplified PWM signal to an external low-pass or band-pass filter. Accordingly, the amplifier stage is configured to receive at input the at least one PWM signal and provide at output the amplified PWM signals.

For example, in various embodiments, the amplifier stage comprises for each pad of the first set of pads a half-bridge, respective drive circuits and a control circuit. Specifically, each half-bridge comprises a high-side switch and a low-side switch, where the intermediate point between the high-side switch and the low-side switch is connected to the respective pad of the first set of pads. A high-side driver circuit and a low-side driver circuit are used to drive the high-side switch and the low-side switch, respectively. The control circuit is configured to generate the control signals for the high-side driver circuit and the low-side driver circuit as a function of the at least one PWM signal.

In various embodiments, the electronic converter circuit has associated two power supply pads configured to be connected to a supply voltage, two inductor pads configured to be connected to an external inductor and a second set of pads, where each pad of the second set of pads is configured to provide a respective regulated voltage, where each pad of the second set of pads is arranged to be connected to a respective external capacitor. Accordingly, the electronic converter circuit is configured to generate the regulated voltages in order to supply the driver circuits and the control circuit of the amplifier stage.

For example, in various embodiments, the electronic converter circuit comprises a respective output terminal for each of the regulated voltages, where each of the output terminals of the electronic converter circuit is connected to a respective pad of the second set of pads. A first set of electronic switches is configured to selectively couple the two inductor pads to the two power supply pads for controlling the current flowing through the external inductor. A second set of electronic switches is arranged to sequentially couple the two inductor pads to the output terminals, thereby charging the external capacitors with the current flowing through the external inductor. Accordingly, a control circuit may drive the first set of electronic switches and the second set of electronic switches in response to a second clock signal in order to regulate each of the regulated voltages to a respective requested value.

For example, a first of the regulated voltages may be referred to the negative pad of the two power supply pads, whereby the respective pad of the second set of pads is arranged to be connected via the respective external capacitor to the negative pad of the two power supply pads, which represent a ground. The die of the integrated circuit may however also comprise a further pad, where the electronic converter circuit is configured to generate a further voltage at the further pad, where a second of the regulated voltages is referred to the further voltage, whereby the respective pad of the second set of pads is configured to be connected via the respective external capacitor to the further pad. Accordingly, the second voltage may be a voltage having a fixed or variable offset with respect to ground. For example, as will be described in the following, this may be useful when the half-bridge is connected between the two power supply pads, which may receive a variably supply voltage. In this case, the electronic converter circuit may regulate the further voltage to a value determined as a function of the value of the supply voltage connected to the two power supply pads. For example, this second regulated voltage may be used to supply the control circuit of the amplifier stage.

For example, for generating the second voltage referred to the further pad, the first set of electronic switches may comprise a first electronic switch connected between the positive power supply pad and the first inductor pad, and a second electronic switch connected between the second inductor pad and the negative power supply pad. The second set of electronic switches may comprise a third electronic switch connected between the second inductor pad and the pad of the second set of pads associated with the second of the regulated voltages, and a fourth electronic switch connected between the first inductor pad and the further pad. In this case, the control circuit of the electronic converter circuit may monitor the voltage between the pad of the second set of pads associated with the second of the regulated voltages and the further pad. During a charge phase, the control circuit may close the first and the second electronic switch, thereby increasing the current flowing through the external inductor.

Conversely, during a discharge phase, the control circuit may close the third and the fourth electronic switch, whereby the current flowing through the external inductor charges the external capacitor connected between the pad of the second set of pads associated with the second of the regulated voltages and the further pad, thereby increasing the respective voltage. Accordingly, the control circuit may regulate the duration of the charge phase and/or the discharge phase, such that the voltage corresponds to a requested value.

In various embodiments, the control block comprises an oscillator circuit configured to generate the at least one first clock signal and the second clock signal, whereby the switching activity of the first set of electronic switches and the second set of electronic switches is synchronized with the switching activity of the half-bridges of the amplifier stage. For example, the oscillator circuit may comprise an integrated oscillator and/or a Phase-Locked Loop. For example, the oscillator circuit may generate the at least one first clock signal and the second clock signal with one of the following frequencies:

the frequency of the second clock signal corresponds to the frequency of the at least one first clock signal;

the frequency of the second clock signal corresponds to a multiple of the frequency of the at least one first clock signal; or

the frequency of the at least one first clock signal corresponds to a multiple of the frequency of the second clock signal.

In various embodiments, the circuit is configured to generate each of the at least one PWM signal in response to a respective first clock signal, and the oscillator circuit may apply a different phase difference to each of the at least one first clock signal and the second clock signal.

Additionally or alternatively, the control block may implement other functions. For example, the die of the integrated circuit may comprise at least one communication pad and the control block may comprise a communication interface for receiving control commands for controlling the operation of the electronic converter circuit and/or the amplifier stage; and/or transmitting information concerning the status of the electronic converter circuit and/or the amplifier stage.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

In the followingFIGS. 5 to 23parts, elements or components which have already been described with reference toFIGS. 1 to 4are denoted by the same references previously used in such Figures. The description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description.

As mentioned before, various embodiments of the present application relate to an electronic converter30a, such as an electronic converter30afor an audio system (see also the description ofFIGS. 1 to 4).

FIG. 5shows the general architecture of an embodiment of the electronic converter30a. Generally, the electronic converter30acomprises two input terminals300and302for connection to a DC supply voltage Vbat, where the negative terminal302represent a ground GND. For example, the terminals300and302may be connected to a battery BAT, such as the battery of a vehicle, such as a car.

In the embodiment considered, the electronic converter30acomprises at least two output terminals304and306for providing a regulated voltage Vfloat, which may e.g., be used to power one or more digital/analog circuits, such as the signal generator10, and/or the blocks202,206and/or the control circuit2060described in with respect toFIG. 2.

Specifically, in various embodiments, the voltage at the terminal304is not connected directly to ground GND, i.e., the voltage Vfloat−between the (negative) terminal304and ground GND is not zero. However, the electronic converter30ais configured to generate a regulated and substantially constant voltage Vfloatbetween the terminals304and306, such as 1.8 VDC.

Specifically, in various applications it may be desirable that the voltage Vfloatis referred to a reference voltage Vref, which is smaller than the voltage Vbat, i.e.:
0<Vref<Vbat

Specifically, in various embodiments, the converter30agenerates a voltage Vfloat+between the positive terminal306and ground GND, which corresponds to:
Vfloat+=Vref+Vfloat/2.
and a voltage Vfloat−between the negative terminal304and ground GND which corresponds to:
Vfloat−=Vref−Vfloat/2
whereby the voltage between the (positive) terminal306and the (negative) terminal304corresponds to Vfloat.

For example, in various embodiments, the reference voltage Vrefis variable and set to 50% of the supply voltage Vbat(or generally Vref=x*Vbat, with 0<x<1). For example, the reference voltage Vrefmay be provided by an additional voltage regulator or a voltage divider.

Generally, such a floating voltage Vfloatmay be useful in many applications.

For example, in the case of an audio system, such a floating voltage Vfloatmay be used by the analog circuits, in particular by the circuit2060, in order to improve the quality of the audio signal, in particular with respect to the signal/noise ratio. For example, this simplifies the implementation of unity-gain amplifier (as described, e.g., in documents Maxim, “APPLICATION NOTE 3977—Class-D Amplifiers: Fundamentals of Operation and Recent Developments”, Jan. 31, 2007, available at https://www.maximintegrated.com/en/app-notes/index.mvp/id/3977, or U.S. Pat. No. 8,558,618 B2, which are incorporated herein by reference), because the voltage gain of the amplifier stage206is unitary. Similarly, also the digital circuits may work with the floating voltage Vfloatin order to simplify the interface between the digital and analog circuits.

For example,FIG. 6shows exemplary waveform for the supply voltage Vbat, the reference voltage Vrefand the voltages Vfloat+and Vfloat−(referred to ground GND).

As mentioned before, in case the converter30ais powered via a vehicle battery BAT, the variation of the supply voltage Vbatmay be fast (<2 ms). In various embodiments, the converter30ashould thus be able to generate voltages Vfloat+and Vfloat−following such voltage variations. For example, this implies that the capacitances associated with the terminals304and306with respect to ground GND should be small.

In various embodiments (see, e.g.,FIG. 5), the electronic converter30amay also comprise one or more additional output terminals, such as terminals308and310, for providing one or more additional supply voltages, such as voltages V1and V2, which, e.g., may be used to power the driver circuits2062and2064arranged to drive the switches of a half-bridge. Generally, only a single terminal may be required for these voltages V1and V2, insofar as these voltages may be referred to ground GND.

Accordingly, in various embodiments, the converter30areceives at input a variable input voltage Vbatand provides at output one or more voltages, which generally may be smaller or greater than the input voltage Vbat. Thus, generally, a plurality of electronic converters may be used, where each electronic converter is configured to generate a respective one of the voltages Vfloat+, Vfloat−, V1and V2.

ConverselyFIG. 7shows an embodiment of an electronic converter30aconfigured to generate a plurality of the voltages Vfloat+, Vfloat−, V1and V2.

Specifically, in the embodiment considered, a so called Single-Inductor Multiple-Output (SIMO) architecture is used. As the term implies, in this case, the electronic converter30acomprises a single inductor L.

Specifically, in the embodiment considered, the electronic converter30acomprise a half-bridge comprising two electronic switches Sh and Sl, such as (e.g., n-channel) FETs, connected (e.g., directly) in series between the terminals300and302arranged to receive the supply voltage Vbat, i.e., the terminals300and302may be connected (directly or via a cable) to the battery BAT.

In the embodiment considered, a first terminal of the inductor L is connected (e.g., directly) to the intermediate point between the switches Sl and Sh. The second terminal of the inductor L is connected (e.g., directly) via a further electronic switch Sbb to the negative terminal302. Moreover, the second terminal of the inductor L is also connected (e.g., directly) via a respective switch, such as a (e.g., n-channel) FET, to each of the output terminals of the electronic converter30a, i.e., the terminals304,306and the optional terminals308and/or310For example, in the embodiment considered, the electronic converter30acomprises:

an electronic switch S− connected (e.g., directly) between the second terminal of the inductor L and the terminal304providing the voltage Vfloat−;

an electronic switch S+ connected (e.g., directly) between the second terminal of the inductor L and the terminal306providing the voltage Vfloat+;

optionally an electronic switch S1connected (e.g., directly) between the second terminal of the inductor L and the terminal306providing the voltage V1; and

optionally an electronic switch S2connected (e.g., directly) between the second terminal of the inductor L and the terminal308providing the voltage V2.

In various embodiments, each of the switches S−, S+, S1and S2may ensure that current may flow from the second inductor terminal towards the respective output terminal. For this purpose, each of the switches may be:

a bidirectional switch, e.g., by using two field effect transistors connected in opposite direction in series, e.g., in case of n-channel FET the drain of a first FET may be connected to the second inductor terminal, the drain of a second FET may be connected to the respective output terminal, and the source terminals of the two FETs may be connected together; or

an unidirectional switch, e.g., by connecting a diode in series with a FET.

Moreover, as will be described in the following, the electronic switch associated with the output terminal304,306, etc., providing the highest output voltage (e.g., switch S2associated with the terminal310providing the voltage V2to the driver circuit2062), may also be implemented with a diode.

In the embodiment considered, a respective capacitor C+, C−, C1and C2is associated with each of the output terminals. Specifically, in the embodiment considered, each terminal304,306,308and310is connected (e.g., directly) via the respective capacitor C+, C−, C1or C2to ground GND.

As shown inFIG. 8, the electronic converter30acomprises also a control circuit32configured to generate drive signals DRVh, DRVl, DRVbb, DRV−, DRV+, DRV1and DRV2configured to drive the switches Sh, Sl, Sbb, S−, S+, S1and S2, respectively, as a function of the output voltages Vfloat−, Vfloat+, V1and V2, and the respective requested output voltages (not shown inFIG. 8).

Generally, by driving the switches in an appropriate manner, the converter30amay be operated as buck (step-down), boost (step-up) or buck-boost converter.

For example, at the example ofFIGS. 9A, 9B and 10will be described a possible operation of the control circuit32. Specifically,FIGS. 9A and 9Bshow two exemplary switching states of the converter ofFIG. 7andFIG. 10shows a possible waveform of the current ILflowing through the inductor L.

In the embodiment considered, the control circuit32closes at an instant t0and for a charge time Tchargethe switches Sh and Sbb and maintains opened the other switches (seeFIG. 9A). Accordingly, during this phase the inductor L is connected to the supply voltage Vbatand the current ILincrease substantially linearly.

At the end of the charge interval Tcharge, i.e., at an instant t1, the control circuit32opened the switches Sh and Sbb, and closes the switch Sl and one of the output switches S+, S−, S1or S2associated with the outputs, such as the switch S− (seeFIG. 9B). Accordingly, during a following time interval T−the inductor current ILflows to the output304and the voltage Vfloat−increase, while the current ILdecrease substantially linearly.

At an instant t2, e.g., when the voltage Vfloat−has reached the requested value, the control circuit32opened the previously closed output switch, e.g., the switch S−, and closes a next output switch, such as the switch S+. Accordingly, during a following time interval T+the inductor current ILflows to the output306and the voltage Vfloat+increase, while the current ILdecrease substantially linearly.

At an instant t3, e.g., when the voltage Vfloat+has reached the requested value, the control circuit32opened the previously closed output switch, e.g., the switch S+, and closes a next output switch, such as the switch S1. Accordingly, during a following time interval T1the inductor current ILflows to the output308and the voltage V1increase, while the current ILdecrease substantially linearly.

At an instant t4, e.g., when the voltage V1has reached the requested value, the control circuit32opened the previously closed output switch, e.g., the switch S1, and closes a next output switch, such as the switch S2. Accordingly, during a following time interval T2the inductor current ILflows to the output310and the voltage V2increase, while the current ILdecrease substantially linearly.

At an instant t5, e.g., when the voltage V2has reached the requested value, the control circuit32opened the previously closed output switch, e.g., the switch S2.

Generally, the sequence of the various discharge phases T+, T−, T1, and T2may also be different, and the converter may use more or less phases in order to provide more or less output voltages.

The control circuit32may start a new cycle Tchargeat a fixed frequency or immediately with the instant t5. The former being usually referred to as Pulse Width Modulation (PWM) mode, while the latter is usually called quasi resonant mode.

Specifically, in various embodiments, apart from regulating the durations of the various discharge phases, the control circuit32also regulates the duration of the charge phase Tchargein order to ensure that sufficient energy is stored in the inductor L in order to reach the requested output voltages. For example, the control circuit32may use for this purpose the voltage at the output terminal corresponding to the last discharge phase, e.g., the voltage V2terminal310.

For example, the control circuit32may increase the duration of the charge phase Tchargewhen:

the inductor current ILreaches zero and the voltage is smaller than the requested value, or

a new switching cycle starts with fixed frequency and the voltage is smaller than the requested value.

Similarly, the control circuit32may decrease the duration of the charge phase Tchargewhen:

the voltage reaches the requested value and the inductor current ILis greater than zero, or in a complementary manner the inductor current ILreaches zero and the voltage is greater than the requested value, or

a new switching cycle starts with fixed frequency and the voltage is greater than the requested value.

Thus, in the embodiment considered, the control circuit32may use a fixed reference values for the voltages V1and V2, thereby providing substantially constant voltages V1and V2. Conversely, the control circuit32may use variable reference values for the voltages Vfloat+and Vfloat−determined as a function of the voltage Vbat, thereby providing variable voltages Vfloat+and Vfloat−, where the voltage Vfloatbetween the terminals304and306is substantially constant (as described in the foregoing).

Generally, instead of using a single charge phase Tcharge, the converter may use also a plurality of charge phases, e.g., a respective charge phase for each discharge phase. For example, in this case, the electronic converter30amay be operated as a buck-boost converter, where a plurality of outputs is regulated sequentially. Accordingly, in the embodiment considered, the electronic converter30ais used in a time-sharing mode, where the switches Sh, Sl and Sbb and the inductor L are sequentially used to provide power to one of the output capacitors (by closing one of the switches S−, S+, S1or S2).

Again, as mentioned in the foregoing, the electronic converter30acould also generate only the voltages Vfloat+and Vfloat−. Moreover, based on the values of the supply voltage Vbatand the requested output voltages, the control circuit32may operate the switches in order to implement other converter topologies, which control the current flowing through the inductor L, such as:

a buck converter, where the switch Sbb remains opened, and the control circuit32closes alternatively the switches Sh and Sl, e.g., in order to generate a voltage V1being smaller than the supply voltage Vbat.

a boost converter, where the switch Sh remains closed and the switch Sl remains opened, and the control circuit32closes alternatively the switch Sbb and e.g., the switch S2in order to generate a voltage V2being greater than the supply voltage Vbat.

In various embodiments, due to the fact that the voltages Vfloat+and Vfloat−are between the minimum and the maximum value of the supply voltage Vbat, the control circuit32operates at least for these voltages the converter30aas buck-boost converter as described in the foregoing.

While the solution described in the foregoing is a valid solution in order to generate constant or almost constant output voltage, e.g., the voltages V1and V2, the solution may present some drawbacks for the generation of variable voltages, such as the voltages Vfloat+and Vfloat−. For example, as mentioned in the foregoing, the supply voltage Vbatand thus the reference voltage Vrefmay vary fast (<2 ms). Thus, the electronic converter30ashould be able to provide also voltages Vfloat+and Vfloat−, which are able to follow these variations. However, the architecture shown inFIG. 7requires the tank/output capacitors C+ and C−, which are charged by the current IL. Moreover, the converter is operated sequentially with the time-sharing technique. Thus, the output capacitors may not be too small. For example, the capacitances of the capacitors C1and C2may be between 5 e 100 uF, e.g., approximately 10 uF. Thus, in order to follow variations having a frequency being greater than 100 Hz, large charge or discharge currents would be required, which would render the system less efficient.

Moreover, the voltages Vfloat+and Vfloat−are regulated independently, thereby using two separate control loops. These loops have to ensure a sufficient precision in order to obtain the requested voltage Vfloat.

FIG. 11shows thus a second embodiment of the electronic converter30a. Specifically, in the embodiment considered, the electronic switch S− associated with the terminal304providing the voltage Vfloat−is not connected anymore to the second terminal of the inductor L, but to the first terminal of the inductor L, i.e., the intermediate point between the switches Sh and Sl of the half-bridge. Moreover, a single capacitor Cf is connected between the terminals304and306. In some embodiments, the capacitors C+ and C− are thus omitted.

FIG. 13shows again a possible waveform of the current ILflowing through the inductor L, andFIGS. 14A, 14B and 14Cshow various switching stages of the converter30a.

Specifically, the control circuit32closes again at an instant t0and for a charge time Tchargethe switches Sh and Sbb and maintains opened the other switches (seeFIG. 14A). Accordingly, during this phase the current ILincreases substantially linearly. At an instant t1, the control circuit32opens thus the switches Sh and Sbb and the charge phase ends.

During the following discharge phases, the energy stored in the inductor L is then provided to the output terminals. Specifically, during one of the discharge phases T+/−, e.g., the first discharge phase, the control circuit32drives the control terminal of the switches S+ and S− in order to close these switches, e.g., at the instant t1(seeFIG. 14B). Accordingly, in this embodiment, the switches S+ and S− are closed during the same phase. As shown inFIG. 12, the control circuit32may thus generate (in addition to the drive signals DRVh, DRVl, DRVbb, DRV1and DRV2configured to drive the switches Sh, Sl, Sbb, S1and S2, respectively) a common drive signal DRVf, which drives simultaneously the switches S+ and S−. Moreover, as shown inFIG. 12, in the embodiment considered, the control circuit32receives at input directly the voltage difference Vfloat.

Specifically, when both switches S+ and S− are closed, the inductor current ILwill flow from the terminal304to the terminal306, thereby charging the capacitor Cf. Thus, the voltage Vfloat−will decrease and the voltage Vfloat−will increase, whereby the Vfloatbetween the terminals304and306will increase. Thus, in the embodiment considered, the current ILdecrease substantially linearly and the control circuit32may switch off the switches S+ and S− at an instant t3directly when the voltage Vfloatreaches the requested constant value. Generally, in case unidirectional switches are used for the switches S+ and S−, these switches should support the mentioned current flow direction, i.e., the switch S− should be configured to permit a current flow from the terminal304towards the first terminal of the inductor L (as a function of the respective drive signal DRV−/DRVf) and the switch S+ should be configured to permit a current flow from the second terminal of the inductor L towards the terminal306(as a function of the respective drive signal DRV+/DRVf).

Thus, at the instant t3, the control circuit32opened the previously closed output switches S+ and S−, and closes the switch Sl and one of the other output switches, such as the switch S1(seeFIG. 14C). Accordingly, as in the previous embodiment, during a following time interval T1the inductor current ILflows now from ground GND (via the switches Sl an S1) to the output308and the voltage V1increase, while the current ILdecrease substantially linearly.

At an instant t4, e.g., when the voltage V1has reached the requested value, the control circuit32opened the previously closed output switch, e.g., the switch S1, and closes a next output switch, such as the switch S2. Accordingly, during a following time interval T2the inductor current ILflows to the output310and the voltage V2increase, while the current ILdecrease substantially linearly.

At an instant t5, e.g., when the voltage V2has reached the requested value, the control circuit32opened the previously closed output switch, e.g., the switch S2.

Again, the sequence of the various discharge phases T+/−, T1, and T2may also be different, and the converter may use more or less phases in order to provide more or less output voltages. Moreover, also in this case, a plurality of charge phase may be used, such as a respective charge phase for each discharge phase.

Thus, in the embodiment considered, during one of the discharge phases, both switches S+ and S− are closed (while the other switches Sh, Sl, Sbb, S1and S2are opened). Thus, in the embodiment considered, the inductor current ILcharges the capacitor Cf and the control circuit may directly regulate the output voltage Vfloat.

Again, considering the voltage levels at the inductor L, the switch Sl and/or the switch connected to the output terminal providing the highest output voltage (e.g., the switch S2) may also be implemented with a diode, and the control unit302may thus not generate the respective drive signals, e.g., the drive signal DRVl for the switch Sl and the drive signal DRV2for the switch S2.

In the embodiment shown inFIGS. 11 and 12, the control circuit32regulates only the voltage difference between the terminals304and306, i.e., the voltage Vfloat. However, the control circuit32does not regulate the offset of the voltages Vfloat+and Vfloat−with respect to ground GND.

Generally, the control circuit32could thus also regulate the voltages Vfloat+and Vfloat−with respect to ground GND. For example, in an embodiment, the control circuit32could close both switches S+ and S− until either the voltage Vfloat+or the voltage Vfloat−reaches the requested reference value (Vref+/−Vfloat/2), and then either:

when the voltage Vfloat+has reached the requested voltage (Vref+Vfloat/2), continue to discharge the terminal302towards ground GND (e.g., by closing the switch Sbb) or towards one of the other output terminals (e.g., via the switch S1or S2); or

when the voltage Vfloat−has reached the requested voltage (Vref−Vfloat/2), continue to charge the terminal304from ground GND e.g., by opening the switch S− and closing the switch Sl.

Unfortunately, this control is rather complex and instead of using a single capacitor Cf, two capacitors C+ and C− would again be required. Substantially, in this case, the voltages Vfloat+and Vfloat−would have to be regulated again individually, with the associated complexity to obtain the requested variable values.

FIG. 15shows an embodiment, which permits a simplified control of voltage offset of the voltages Vfloat+and Vfloat−. Specifically, in the embodiment considered, the control circuit32regulates the duration of the interval T+/−in order to obtain the requested voltage difference Vfloat(as described with respect toFIGS. 11-14), however, the control circuit32does not regulate the voltage Vfloat+and Vfloat−with respect to ground GND. Conversely, the offset of these voltages Vfloat+and Vfloat−is imposed separately by coupling the terminals302and304to the reference voltage Vref, representing a common mode for the terminals302and304.

In various embodiments (seeFIG. 16), the converter30amay thus comprise a circuit34configured to generate the voltage Vrefat a node/terminal312as a function of the voltage Vbat. For example, in various embodiments, the circuit34comprises a resistive voltage divider comprising two resistors Rref1and Rref2connected (e.g., directly) between the terminals300and302. Accordingly, in the embodiment considered, the voltage Vrefat the intermediate point between the two resistors Rref1and Rref2(representing the node/terminal312in the embodiment considered) will be proportional to the supply voltage Vbatbased on the values of the resistors Rref1and Rref2. For example, in various embodiments, the resistors Rref1and Rref2have substantially the same value. Generally, the circuit34may also comprise more complex circuits for implementing a reference voltage generator, possibly comprising also amplifier stages (such as one or more operation amplifiers and/or current mirrors) in order to ensure a stable output voltage Vreffor different load conditions at the node/terminal312.

In the embodiments considered, the terminals304and306are coupled to the voltage Vrefvia respective resistors Rcm1and Rcm2, i.e., a resistor Rcm1is connected (e.g., directly) between the terminal306and the terminal312providing the voltage Vref(e.g., the intermediate point between the resistors Rref1and Rref2) and a resistor Rcm2is connected (e.g., directly) between the terminal304and the terminal312. In order to obtain the voltages Vref+/−Vfloat/2 the resistors Rcm1and Rcm2should have the same value. However, generally the resistors could also have different values, e.g., when a different scaling with respect to the ground GND is requested.

For example, assuming a switching frequency of 2 MHz, the inductance of the inductor L may be 10 μH, the capacitance of the capacitor Cf may be 10 μF, the resistances of the resistors Rcm1and Rcm2may be 10 kΩ and the resistances of the resistors Rref1and Rref2may be 10 kΩ. Accordingly, typically the inductor L, the capacitor Cf and the resistors Rcm1, Rcm2, Rref1and Rref2have values in the micro-henry (μH)/micro-farad (μF)/kilo-ohm (kΩ) range, respectively.

The inventors have observed that the solution described with respect toFIGS. 15 and 16is a valid solution, in particular when no high precision of the offsets Vfloat+and Vfloat−with respect to the ground GND is required. From a practical point of view, the circuit will however comprise also parasitic capacitance, such as capacitances associated with the first and second terminal of the inductor L.

For example, this is shown inFIG. 17, where parasitic currents Ipar1and Ipar2are flowing through the switches S+ and S−, respectively. Specifically, these parasitic currents Ipar1and Ipar2do not flow through the inductor L but towards the positive supply voltage Vbatand/or ground GND. The inventors have observed that (based on the implementation of the switches S+ and S−) usually these parasitic current Ipar1and Ipar2flow only during a brief interval at the instant t1when the switches S+ and S− are closed, i.e., the duration of the current pulses is significantly smaller than the duration of the interval T+/−. In principle, these parasitic currents Ipar1and Ipar2would not represent any particular issue, when their amplitude would be the same. However, in case the values are different, a current (Ipar1−Ipar2) will also flow towards the node312providing the reference voltage Vref. For example, in case the reference voltage Vrefis provided by a voltage divider (seeFIG. 16), this current will vary the reference voltage Vreffrom the requested value.

FIG. 18shows thus a modified embodiment that is capable of inhibiting or at least reducing this current flow towards the node312. Specifically, in the embodiment considered, the electronic converter30acomprises (in addition to the components described with respect toFIG. 15) at least one of:

a capacitor Cf1connected (e.g., directly) between the terminal306and the terminal300providing the supply voltage Vbat; and

In various embodiments, taking into account typical values for the parasitic current Ipar1and Ipar2the capacitors Cf1and Cf2may have a capacitance being significantly smaller than the capacitance of the capacitor Cf, such as less than 5%, preferably between 0.1% and 2%, preferably approximately 1%. For example, in various embodiments, the capacitance of the capacitors Cf1and Cf2is between 10 and 100 nF (nano-farad). In various embodiments, the capacitors Cf1and Cf2may have the same capacitance.

Accordingly, in the embodiment considered, the parasitic currents Ipar1and Ipar2will also flow. However, the current pulse (Ipar1−Ipar2) will not flow (or will flow less) towards the node312but through the low impedance path provided by the capacitor Cf1and/or the capacitor Cf2(and also the capacitor Cf).

Generally, the capacitors Cf1and/or Cf2may be connected to any reference voltage having a low impedance towards ground GND (as it is the case for the supply voltage Vbat). For example, the capacitors Cf1may also be connected to the terminal302(instead of the terminal300) and/or the capacitors Cf2may also be connected to the terminal300(instead of the terminal302).

FIG. 19shows a second embodiment for obtaining the voltage offsets Vfloat+and Vfloat−with respect to ground GND. Specifically, the embodiment is based on the circuit shown inFIG. 11and comprises in addition two further circuits:

a first clamp circuit36connected (e.g., directly) to the terminal306; and

a second clamp circuit38connected (e.g., directly) to the terminal308.

Specifically, in the embodiment considered, the first clamp circuit36is configured to selectively permit a current flow towards the terminal306until the voltage corresponds to an upper voltage threshold VH.

For example, as shown inFIG. 20, the clamp circuit36may comprise a transistor362, such as a n-channel FET, such as an NMOS, connected (e.g., directly) between the terminal300providing the supply voltage Vbatand the terminal306.

In the embodiment considered, the gate terminal of the transistor362is driven by an operational amplifier364. Specifically, in the embodiment considered, the operational amplifier364receives at the non-inverting/positive input terminal the upper voltage threshold VHand at the inverting/negative input terminal the voltage at the terminal306.

Accordingly, the circuit36will drive the transistor362thereby permitting a current flow (from the supply voltage Vbat) towards the terminal306, until the voltage at the terminal306reaches or is greater than the voltage VH.

Conversely, in the embodiment considered, the second clamp circuit38is configured to selectively permit a current flow from the terminal304until the voltage corresponds to a lower voltage threshold VL.

For example, as shown inFIG. 21, the clamp circuit38may comprise a transistor382, such as a p-channel FET, such as a PMOS, connected (e.g., directly) between the terminal304and the terminal302(ground GND).

In the embodiment considered, the gate terminal of the transistor382is driven by an operational amplifier384. Specifically, in the embodiment considered, the operational amplifier receives at the non-inverting/positive input terminal the lower voltage threshold VLand at the inverting/negative input terminal the voltage at the terminal304.

Accordingly, the circuit38will drive the transistor382thereby permitting a current flow from the terminal304(towards ground GND), until the voltage at the terminal304reaches or is smaller than the voltage VL.

In various embodiments, the clamp circuits36and38are not used to directly impose the voltages Vref+/−Vfloat/2, but the clamp circuits set only approximately the voltages at the nodes304and306with respect to ground GND.

Specifically, in various embodiments, the upper and the lower threshold correspond to:
VH=Vref+Vfloat/2−Δ
VL=Vref−Vfloat/2+Δ

Accordingly, without any switching activity of the switches Sh, Sl, Sbb, the clamp circuits36and38would set the following voltages (via the coupling of the capacitor Cf):
Vfloat+=Vref+Vfloat/2−Δ
Vfloat−=Vref−Vfloat/2+Δ
and the voltage difference VDiffbetween the terminals306and304would be:
VDiff+=Vfloat−2Δ

For example, in various embodiments, the value of Δ is selected between 5 and 20% of the value of Vfloat, e.g., Δ=0.1 Vfloat. For example, Δ may be between 150 and 180 mV for Vfloat=1.8 V.

Accordingly, once the control unit32drives the switches of the converter30a, the control unit32will also regulate the voltage difference VDiffuntil the value corresponds to the requested value Vfloat.

When the supply voltage Vbatremains constant, the clamp circuits36and38do not intervene during this regulation of the voltage difference VDiff. Conversely, the clamp circuits34and36may absorb the current peaks generated by the parasitic current mentioned before and/or may intervene when the supply voltage Vbatvaries.

FIG. 22shows in this respect a possible embodiment of the control circuit32. Specifically, in the embodiment considered, the voltages Vfloat+and Vfloat−are provided to a differential amplifier320, e.g., based on an operation amplifier. The output of the differential amplifier320is connected to an error amplifier324, such as a PI (Proportional-Integral) or PID (Proportional-Integral-Derivative) regulator, configured to generate an error signal as a function of the voltage difference and a reference signal REF. In the embodiment considered a scaling circuit and/or a current-voltage conversion circuit322, such as a voltage divider comprising two resistors, may be connected between the differential amplifier320and the error amplifier324.

In the embodiment considered, the optional voltages V1and V2may be provided similarly to respective error amplifiers332and336. While also in this case may be used scaling circuits330and334, usually no differential amplifiers are required, because the voltages V1and V2are referred to ground GND.

The error signals at the output of the error amplifiers324,332and336are provided to a driver circuit326. Specifically, in the embodiment considered, the driver circuit326is configured to manage the charge phase and the various discharge phases by generating the drive signals for the switches Sh, Sl, Sbb, S+, S− S1and S2. Generally, the drive signal DRVl for the switch Sl and the drive signal DRV2for the switch S2are purely optional, because these switches may also be implemented with diodes.

For example, in various embodiments, the driver circuit326may be a Pulse-Width-Modulation (PWM) driver circuit. For this reason, the driver circuit326may have associated an oscillator328configured to generate an oscillator signal having a fixed frequency, i.e., a fixed switching period TSW.

For example, once the oscillator signal indicates the start of a new switching cycle (corresponding essential to the instant t0ofFIG. 13), the driver circuit326sets the drive signals DRVh and DRVbb for closing the switches Sh and Sbb. At the instant t1, i.e., after the duration Tcharge, the driver circuit326sets the drive signals DRVh and DRVbb for opening the switches Sh and Sbb. Accordingly, in the embodiment considered, these drive signals DRVh and DRVbb are PWM signals, which are set:

to a first logic level (e.g., high) for a switch-on duration corresponding to the duration Tcharge; and

to a second logic level (e.g., low) for a switch-off duration corresponding to TSW−Tcharge.

In the embodiment considered, the driver circuit326sets then (e.g., at the instant t1) the drive signal DRVf for closing the switches S+ and S−. At the instant t3, i.e., after the duration T+/−, the driver circuit326sets the drive signal DRVf for opening the switches S+ and S−. Accordingly, in the embodiment considered, the drive signal DRVf is a PWM signal, which is set:

to a first logic level (e.g., high) for a switch-on duration corresponding to the duration T+/−; and

to a second logic level (e.g., low) for a switch-off duration corresponding to TSW−T+/−.

In the embodiment considered, the driver circuit326sets then (e.g., at the instant t3) the drive signal DRV1for closing the switch S1(and possibly the drive signal DRVl for closing the switch Sl). At the instant t4, i.e., after the duration T1, the driver circuit326sets the drive signal DRV1for opening the switch S1. Accordingly, in the embodiment considered, the drive signal DRV1is a PWM signal, which is set:

to a first logic level (e.g., high) for a switch-on duration corresponding to the duration T1; and

to a second logic level (e.g., low) for a switch-off duration corresponding to TSW−T1.

Generally, the driver circuit326may then generate the drive signal DRV2for the switch S2. Conversely, in the embodiment considered the switch S2is implemented with a diode. Accordingly, when the switches S+, S− and S1are opened, the current ILwill flow through the diode S2towards the terminal310until the current ILreaches zero or the switching duration TSWhas finished.

Specifically, in the embodiment considered, the driver circuit326is configured to vary the switch-on durations T+/−and T1of the drive signals DRVf and DRV1as a function of the error signals provided by the error amplifiers324and332, respectively. Specifically, in the embodiment considered, the error amplifiers324and332will vary these durations (via the respective error signals) until the voltages Vfloatand V1correspond to the respective requested values.

Conversely, in the embodiment considered, the driver circuit326is configured to vary the switch-on duration Tchargeof the drive signals DRVh and DRVbb as a function of the error signal provided by the error amplifiers336. Specifically, in the embodiment considered, the error amplifier336will vary the duration (via the respective error signal), thereby varying the maximum current IL, until the voltages V2correspond to the respective requested values. Additionally, the driver circuit326may vary the switch-on duration Tchargealso as a function of the error signals provided by the other error amplifiers, e.g., the amplifiers324and332, which may be useful in order to perform a (predictive) control in case of short load variations of the outputs. For example, such an arrangement is useful when the error amplifiers324,332and336have (in addition to an integral component) a proportional and/or derivative component.

Accordingly, in various embodiments, the control unit32is configured to manage the following phases which are repeated periodically:

a charge phase Tcharge, where the control circuit32closes the switches Sh and Sbb for storing energy in the inductor L;

a (last) discharge phase, where the energy stored in the inductor L is transferred to an output; and

one or more optional intermediate discharge phases between the charge phase and the last discharge phase, where the energy stored in the inductor L is transferred to one or more respective other outputs.

Generally, the discharge phase T+/−may be the last discharge phase or an intermediate discharge phase.

Specifically, in various embodiments, the control unit is configured to stop an intermediate phase when the respective output voltage reaches the requested value. Conversely, the last discharge phase is used to control the duration of the charge phase Tcharge.

For example, by using a PWM modulation with constant switching cycle TSW, the control unit32may:

increase the duration of the charge phase Tcharge(while maintaining the total duration TSW) when, at the end of the last discharge phase, the respective output voltage is smaller than the requested value; and

decrease the duration of the charge phase Tcharge(while maintaining the total duration TSW) when, at the end of the last discharge phase, the respective output voltage is greater than the requested value.

Generally, the duration of the last discharge phase may also be constant. Thus, the control unit32may:

increase the duration of the charge phase Tchargewhen, at the end of the last discharge phase, the respective output voltage is smaller than the requested value; and

decrease the duration of the charge phase Tchargewhen, at the end of the last discharge phase, the respective output voltage is greater than the requested value.

Most of the components of the electronic converters30adescribed in the foregoing may also be integrated in an integrated circuit. For example,FIG. 23shows an embodiment, where such integrated circuit may comprise:

two pins/pads300and302for connection to the supply voltage Vbat;

the optional switch S1;

the optional switch/diode S2;

the control circuit32; and

the optional clamp circuits36and38.

In various embodiments, the integrated circuit does not comprise large inductors, capacitors and resistors, such as the inductor L, the capacitor Cf, and the capacitors C1and C2, i.e., these components are external with respect to the integrated circuit. Conversely, small capacitors, such as the capacitors Cf1and Cf2, and the various resistors described may be external or internal.

For example, in the embodiment considered, the integrated circuit comprises:

two pins/pads400and402for connection to an external inductor L;

a pin/pad308for connection to an external capacitor C1(being optional insofar as the voltage V1is optional);

a pin/pad310for connection to an external capacitor C2(being optional insofar as the voltage V2is optional); and

at least two pins/pads for connection to the capacitor Cf.

Generally, the capacitor Cf may be connected directly to two pads/pins304and306. Conversely,FIG. 23shows an embodiment where four pins/pads304,306,404and406are used. Specifically, the pins/pads404and406are connected directly to the switches S− and S+, respectively. Conversely, the pins/pads304and306provide the voltages Vfloat−and Vfloat+. Accordingly, in the embodiment considered, a first terminal of an external capacitor Cf may be connected to the pins/pads304and404, thereby connecting the pin/pad304externally to the pin/pad404, and a second terminal of the external capacitor Cf may be connected to the pins/pads306and406, thereby connecting the pin/pad306externally to the pin/pad406.

Specifically, this embodiment has the advantage that the parasitic inductances Lbond1, Lbond2, Lbond3and Lbond4of the bonding of the pins304,306,404and404implement with the capacitor Cf an improved filter stage for current peaks.

Generally, the various embodiments may also be combined. For example, inFIG. 23, the integrated circuit comprises also the clamp circuits38and36which are connected internally to the pins/pads306and304.

Moreover, in the embodiment considered, the electronic converter comprises the capacitors Cf1and Cf2, which are connected externally to the pins/pads304/404and306/406, respectively.

Similarly, the electronic converter could also comprise the coupling resistors Rcm1and Rcm2, which may be connected externally in parallel to the capacitor Cf or internally between the pins/pads304/306or404/406.

Accordingly, the various embodiments described with respect toFIGS. 11 to 23have the following advantages:

only a single phase T+/−is requested in order to regulate the output voltage Vfloat;

accordingly, only a single control loop may be required, because only a single drive signal DRVf may be used;

a single output capacitor Cf is required for providing the output voltage Vfloat; accordingly, except for the parasitic currents and the optional filter capacitors Cf1and CF2, the current used to charge the output capacitor does not flow towards ground GND;

the offset voltages Vfloat+and Vfloat−may be regulated faster, because the capacitances of the respective terminals towards the supply voltage Vbatand ground GND are small.

Moreover, as described in the foregoing, the same electronic converter30amay be used to generate in addition to the voltage Vfloatalso one or more additional voltages V1and V2. In case these voltages are absent, the respective switches S1and S2, and also the switch/diode Sl may be omitted.

Thus, in various embodiments, the electronic converter30acomprises two input terminals300and302configured to receive a supply voltage Vbatand two output terminals304and306configured to provide a regulated voltage Vfloat.

In various embodiments, the electronic converter30acomprises an inductor L comprising a first and a second terminal. A first electronic switch Sh is connected between the first input terminal300and the first terminal of the inductor L. A second electronic switch Sbb is connected between the second terminal of the inductor L and the second input terminal302.

In various embodiments, the electronic converter30acomprises moreover a third electronic switch S+ connected between the second terminal of the inductor L and the first output terminal306and a fourth electronic switch S− is connected between the first terminal of the inductor L and the second output terminal304. A capacitor Cf is connected between the first output terminal306and the second output terminal304.

In various embodiments, a control circuit32monitors the voltage between the two output terminals304and306. During a charge phase Tcharge, the control circuit32closes the first electronic switch Sh and the second electronic switch Sbb, thereby increasing the current ILflowing through the inductor L. During a discharge phase T+/−, the control circuit32closes the third electronic switch S+ and the fourth electronic switch S−, whereby the current ILflowing through the inductor L charges the capacitor Cf, thereby increasing the voltage between the two output terminals.

In various embodiments, the control circuit32regulates the duration of the charge phase Tchargeand/or the discharge phase T+/−, such that the voltage between the two output terminals304and306corresponds to a requested value Vfloat. For example, the control circuit32may determine whether, at the end of the discharge phase T+/−, the voltage between the two output terminals304and306is greater than the requested value Vfloat. When, at the end of the discharge phase T+/−, the voltage between the two output terminals304and306is smaller than the requested value Vfloat, the control circuit32may increase the duration of the charge phase Tcharge. Conversely, when, at the end of the discharge phase T+/−, the voltage between the two output terminals304and306is greater than the requested value Vfloat, the control circuit32may decrease the duration of the charge phase Tcharge.

Generally, the electronic converter30amay also comprise one or more further outputs. For example, in various embodiments, the electronic converter comprises a further output terminal308(and/or310) configured to provide a further regulated voltage V1(V2), where the further regulated voltage is referred to the second input terminal302, which represents a ground. A further capacitor C1(C2) is connected between the further output terminal308(310) and the second input terminal302, where a further electronic switch S1(S2) is connected between the second terminal of the inductor L and the further output terminal. In this case, the converter30acomprises also a fifth electronic switch Sl connected between the first terminal of the inductor L and the second input terminal302. Generally, the fifth electronic switch Sl and/or the further electronic switch S2may be implemented with diodes.

In this case, the control circuit32may thus also regulate the further output voltage V1(and/or V2). For example, during a further discharge phase T1(T2), the control circuit32may close the fifth electronic switch Sl and the further electronic switch S1(S2), whereby the current ILflowing through the inductor L charges now the further capacitor C1(C2), thereby increasing the voltage between the further output terminal308(310) and the second input terminal (302). Similarly, the control circuit32may regulate the duration of the charge phase Tchargeand/or the further discharge phase T1(T2), such that the voltage between the further output terminal and the second input terminal corresponds to a further requested value V1(V2).

For example, in various embodiments, the control circuit32is configured for repeating periodically the charge phase, the discharge phase and the further discharge phase, where one of the discharge phases corresponds to a last discharge phase and the other of the discharge phases corresponds to an intermediate discharge phase between the charge phase and the last discharge phase. In this case, the control circuit32may stop the intermediate discharge phase when the respective voltage being increased during the intermediate discharge phase reaches the respective requested value. Moreover, the control circuit may increase the duration of the charge phase when, at the end of the last discharge phase, the respective voltage being increased during the last discharge phase is smaller than the respective requested value, and decrease the duration of the charge phase when, at the end of the last discharge phase, the respective voltage being increased during the last discharge phase is greater than the respective requested value.

Generally, the electronic converter30amay also control the offset of the voltage between the two output terminals304and306with respect to the second input terminal302, i.e., with respect to ground.

For example, in various embodiments, the electronic converter30acomprises a reference voltage generator34, such as a voltage divider, configured to generate a reference voltage Vrefbeing preferably proportional to the supply voltage Vbat. In this case, a first resistor Rref1may be connected between the first output terminal300and the reference voltage Vref, and a second resistor Rref2may be connected between the second output terminal302and the reference voltage Vref.

In various embodiments, the electronic converter30amay also be configured to filter parasitic current spikes. For this purpose, the electronic converter30amay comprise a first capacitor Cf1connected between the first output terminal306, and the first input terminal300or the second input terminal302. Additionally or alternatively, the electronic converter30amay comprise a second capacitor Cf2connected between the second output terminal304, and the first input terminal300or the second input terminal302.

Generally, in addition or as alternative to the coupling to the reference voltage Vref, the converter30amay also comprise clamp circuits36and/or38for limiting the voltage offset of the two output terminals with respect to the second input terminal, i.e., with respect to ground. Specifically, the electronic converter30amay comprise a first clamp circuit36configured to selectively permit a current flow towards the first output terminal, until the voltage between the first output terminal and the second input terminal reaches or is greater than an upper voltage. The electronic converter may comprise also a second clamp circuit38configured to selectively permit a current flow from the second output terminal, until the voltage between the second output terminal and the second input terminal reaches or is smaller than a lower voltage.

Generally, both the electronic converter30and the audio amplifier20may be integrated in the same integrated circuit. Generally, similar to what has been describe with respect toFIG. 23, larger inductors and capacitors may be connected externally to the integrated circuit.

For example,FIG. 24shows an integrated circuit IC comprising the components in order to implement a class-D audio amplifier20with the respective electronic converter30configured to generate the supply voltages for the audio amplifier20.

Generally, the term integrated circuit does not imply that the die is mounted within a package, but e.g., the die could also be mounted directly on a printed-circuit-board (PCB). Thus, the term pad is used to identify the pad of the die of the integrated circuit and the term pin identifies the pin or lead of an optional external package of the integrated circuit. Thus, when using the term “pad/pin” this indicates that the die has a pad and in case an external package is used, also the package has a corresponding pin, which is connected to the respective pad of the die, e.g., via wire bonding.

As described with respect toFIGS. 1 to 4, when using analog audio signals AS, a class-D audio amplifier20comprises a circuit for generating a PWM signal DS, where the duty cycle of the signal DS is proportional to the amplitude of the analog audio signal AS. For example, as described with respect toFIG. 2, a triangular waveform generator202and a comparator204may be used for this purpose. Generally, these blocks are purely optional, because the audio amplifier20may also receive directly the PWM signal DS, or other data identifying the signal DS, such as digital audio data.

Accordingly, in the embodiment considered, the integrated circuit IC comprises a pad/pin500for receiving an audio signal AS or DS. Generally, this pad/pin is purely optional, because the integrated circuit IC could also comprise directly an audio signal generator10.

A class-D audio amplifier comprises also an amplifier stage206, comprising a half-bridge SW1, SW2which is driven as a function of the PWM signal DS, i.e., the amplifier stage206generates an amplified PWM signal ADS. Moreover, a class-D audio amplifier comprises a low-pass or band-pass filter stage208(seeFIG. 4), such as a LC filter stage, which is configured to remove the frequency of the PWM signal.

Due to the fact, that the filter stage208comprises usually large inductors and/or capacitors, the filter stage208is preferably external to the integrated circuit IC.

Accordingly, in the embodiment considered, the integrated circuit IC comprises for each audio channel a respective pad/pin502configured to be connected via a respective filter stage208to one or more speakers30. For example, in the embodiment considered, are shown three pads/pins5021,5022and5023adapted to be connected to three filter stages2081,2082and2083. When using plural channels, the integrated circuit IC may also comprise a plurality of pins/pads500for receiving a plurality of respective audio signals.

In various embodiments, the number of channels (i.e., the number of amplified PWM signals ADS) may also be different from the number of the initial audio signals, e.g., the number of the analog audio signals AS. For example, in various embodiments, the audio signal AS may be a stereo signal having two channels (such as left and right), while the audio amplifier20may be configured to generate four amplified audio signals ADS for four speakers (such as front-left, front-right, rear-left, rear-right). For this purpose, the audio amplifier20may also perform a mixing operation.

Thus, in various embodiment, the die of the integrated circuit IC comprises a circuit for generating at least one PWM signal DS, such as the blocks202and204, or the signal generator10, or the pad(s)500which could also be used to directly receive the signal(s) DS. The die comprises also a set of pads502corresponding to the number of channels of the audio amplifier20, where each pad502is configured to provide a respective amplified PWM signal ADS. Specifically, each of these pads502is arranged to be connected to a respective external low-pass or band-pass filter208. Moreover, the die comprises an amplifier stage206configured to receive at input the at least one PWM signal DS and provide at output the amplified PWM signals ADS. Specifically, the amplifier stage206comprises for each pad502a half-bridge (comprising the high-side and low-side switches SW1and SW2), where the intermediate point between the switches of the half-bridge is connected to a respective pad502. With each half-bridge is associated a high-side driver circuit2062for driving the respective high-side switch SW1and a low-side driver circuit2064for driving the respective low-side switch SW2, and a control circuit2060configured to generate the control signals for the high-side driver circuit2062and the low-side driver circuit2064as a function of the at least one PWM signal DS.

As described with respect toFIG. 3, the audio amplifier20uses a plurality of supply voltages, such as a voltage V2for the high-side driver2062and a voltage V1the low-side driver2064. Preferably, the audio amplifier uses also a further supply voltage Vfloat, which supplies the analog and/or digital processing parts of the audio amplifier20, such as the block2060and the optional blocks202and204.

Specifically, as described in the foregoing, the supply voltage Vfloathas preferably an offset with respect to ground, in order to place the voltage Vfloatmore or less at the center of the supply voltage used to supply the half-bridge of the amplifier stage206, thereby simplifying the implementation of a unitary gain amplification. Thus, in case the half-bridge SW1/SW2is powered via a variable voltage, such as a battery voltage Vbat, also the offset of the supply voltage Vfloatwith respect to ground should be variable, while the supply voltage Vfloatitself should remain constant. Conversely, when the half-bridge SW1/SW2is powered via a regulated supply voltage, such as the voltage V2, also the offset of the voltage Vfloatwith respect to ground may be constant.

Accordingly, generally, the integrated circuit IC comprises two pads/pins300and302for receiving a supply voltage Vbatand the electronic converter30is configured to generate a plurality of regulated voltages, which may have a fixed or variable offset with respect to ground. For example, in the embodiment considered, the electronic converter30generates two regulated voltages V1and V2, which are referred to ground. Moreover, in the embodiment considered, the electronic converter30generates two voltages Vfloat+and Vfloat−, where the electronic converter regulates the voltage Vfloat=Vfloat+−Vfloat−, and possibly also the voltages Vfloat+and Vfloat−with respect to ground. However, generally, also the voltage Vfloatcould be referred to ground, i.e., Vfloat−=0, and accordingly the voltage Vfloat−is purely optional.

Based on the characteristics of the output voltages generated by the electronic converter30, the electronic converter30may have one of the previous described architectures, such as those described with respect to the converter30a. For example, when using a voltage Vfloat+being referred to ground or having a fixed offset, also the converter shown inFIG. 7may be used. Moreover, based on the characteristics of the supply voltage Vbatthe electronic converter30/30amay be operated as boost, buck or buck-boost converter. For this reason, as described in the foregoing, one or more of the switches Sh, Sl and Sbb may be omitted or replaced with a diode.

In fact, based on the specific application, the electronic converter30may be a SIMO converter comprising:

a plurality of output terminals306,308,310(optionally the terminal304) configured to provide a respective voltage to the audio amplifier20, where a respective capacitor C+, C1, C2(and optionally C−) is connected to each output terminal;

a single inductor L;

one or more electronic switches Sh, Sl, Sbb for controlling the current flowing through the inductor L;

one or more electronic switches S+, S1, S2(and optionally S−) for forwarding the current flowing through the indicator L to a respective output terminal, thereby charging the capacitor associated with the respective output terminal; and

a control circuit32configured to drive the electronic switches in order to regulate the voltages at the output terminals.

In the embodiment considered, the integrated circuit IC comprises thus the electronic switches of the electronic converter30and the control circuit32, while the inductor L and the output capacitors are connected externally to the integrated circuit IC.

For example, in the embodiment considered, the integrated circuit IC comprises two pads/pins400and402for connection to the inductor L, and one or more pads/pins306,308and310(and optionally304) for connection to the capacitors. Specifically, in various embodiments, the die of the integrated circuit IC comprises:

two power supply pads300and302configured to be connected to a supply voltage Vbat;

two pads400,402configured to be connected to an external inductor L; and

a set of pads306,308and310, where each of these pads is configured to provide a respective regulated voltage Vfloat, V1, V1, where each of these pads is arranged to be connected to a respective external capacitor C+/Cf, C1and C2.

Moreover, in various embodiments, the die comprises an electronic converter circuit configured to generate the regulated voltages Vfloat, V1and V2, which are used to supply (at least) the high-side driver circuit2062, the low-side driver circuit2064and the control circuit2060of the amplifier stage206. Specifically, in the embodiment considered, the electronic converter circuit comprises a respective output terminal for each of the regulated voltages Vfloat, V1and V2, where each of these output terminals is connected to a respective pad306,308,310. The electronic converter circuit comprises also a first set of electronic switches Sh, Sl and Sbb configured to selectively couple the pads400and402(for the external inductor L) to the power supply pads300and302for controlling the current flowing through the external inductor L. Moreover, the electronic converter circuit comprises a second set of electronic switches S+, S1and S2configured to sequentially couple the pads400and402to the output terminals, thereby charging the external capacitors C+/Cf, C1and C2with the current flowing through the external inductor L. Accordingly, the control circuit32of the electronic converter circuit may drive the electronic switches Sh, Sl, Sbb, S+, S1and S2in order to regulate each of the regulated voltages Vfloat, V1and V2to a respective requested value.

In various embodiments, the integrated circuit IC comprises also a common control block40. Generally, the control block40may be implemented with any suitable analog or mixed analog/digital circuit. In various embodiments, the common control block40may be powered via one of the voltages generated by the electronic converter30, such as the floating voltage Vfloator the voltage V1, or possibly an externally provided regulated voltage.

For example, in various embodiments, the control block40is configured to control and/or monitor the operation of the electronic converter30(including the control circuit32) and the audio amplifier20.

For example, in various embodiments, the integrated circuit IC comprises one or more pads/pins504for exchanging status and/or control data. Specifically, these one or more pads/pins504are connected to the control block40for transmitting control commands to the control block40and/or for receiving status information from to the control block40. For example, the one or more pads/pins504may be connected to a communication interface42of the control block40, such as a serial communication interfaces, such as a Universal Asynchronous Receiver-Transmitter (UART), Inter Integrated Circuit (I2C) or Serial Peripheral Interface (SPI) communication interface.

For example, the interface42may be used to generate control signals CTR1for setting one or more parameters of the electronic converter30, such as output voltage values, number of active outputs, PWM switching frequency, and/or control signals CTR2for setting one or more parameters of the audio amplifier20, such as the gain of the various channels. Similarly, the interface42may be used to provide one or more status information of the electronic converter30, such as possible error states (e.g., derived from an incorrect or missing connection of the inductor L or the output capacitors; or a malfunction of an electronic switch of the converter), the value of the supply voltage Vbatand/or the output voltages, and/or the audio amplifier20, such as whether a short circuit or an open load condition has been detected at the outputs502.

Generally, the control block40may exchange the status and/or control information with the electronic converter30and the audio amplifier20via any suitable communication, including also bus systems, such as a shared bus. However, in various embodiments, also two separate bus systems may be used for the communication with the electronic converter30and the audio amplifier20, respectively. Generally, also the electronic converter30may exchange data with the audio amplifier20, such as signals referring to the temperatures of the amplifier's power transistors SW1/Sw2, output current level and/or output voltage, supply voltage and so on.

As shown inFIG. 25, in various embodiments, the common control block40may comprise a communication interface44for receiving digital audio data, such as an Integrated Interchip Sound (I2S) interface, where the interface44is connected to one or more further pads/pins506of the integrated circuit IC. In this case, the common control block42comprises a processing circuit (e.g., included in the interface44) for converting the digital audio data into an analog audio signal AS or a pulse width modulated signal DS. In this case, the pads/pins500may thus be omitted. However, the pads/pins500may be provided also in addition to the pads/pins506and, e.g., the control interface42may be used to select the source for the audio data (i.e., either the pads/pins500or the pads/pins506) to be used by the audio amplifier20.

In various embodiments, the common control block40may generate also one or more reference signals for the electronic converter30and/or the audio amplifier20, such as the signal REF for the control circuit32shown inFIG. 22.

Moreover, as mentioned before the electronic converter30, in particular the control circuit32may use a clock signal for generating the various drive signals for the electronic switches of the electronic converter30with a constant switching cycle period.

Accordingly, as shown inFIG. 26, in various embodiments the respective oscillator328shown inFIG. 22may form part of this common control block40. Generally, instead of using a complete oscillator, such as a ring oscillator or an integrated crystal oscillator, the oscillator circuit236may also comprise a circuit to be interfaced via a pad/pin508with an external oscillator, such as an external crystal oscillator, or directly with an external clock signal. For example, when receiving an external clock signal, e.g., together with digital sound data provide to the interface506, the oscillator circuit326may comprise a Phase-Locked Loop (PLL), e.g., in order to generate the internal clock signals having a frequency being a multiple of the frequency of the externally received clock signal.

For example, the oscillator circuit328may generate a first clock signal CLK1, which is used by the control circuit32for generating the drive signals for the electronic switches. Similarly, the same oscillator circuit328may generate a second clock signal CLK2, which may be used by the audio amplifier, e.g., by the triangular waveform generator202.

Accordingly, the frequency of the PWM signal DS (and thus the switching frequency of the half-bridges SW1/SW2of the various channels of the audio amplifier20) may be synchronized with the switching activity of the electronic converter30. Generally, such a synchronization may be achieved by generating clock signals CLK1and CLK2, where:

the frequency of the clock signal CLK1corresponds to the frequency of the clock signal CLK2;

the frequency of the clock signal CLK1corresponds to a multiple of the frequency of the clock signal CLK2; or

the frequency of the clock signal CLK2corresponds to a multiple of the frequency of the clock signal CLK1.

Thus, in various embodiments, the control circuit32of the electronic converter circuit drives the electronic switches Sh, Sl, Sbb, S+, S1and S2in response to the clock signal CLK1and the PWM signal(s) DS are generated in response to the clock signal CLK2. Moreover, in various embodiments, the die of the integrated circuit IC comprises a control block40comprising an oscillator circuit328configured to generate the clock signals CLK1and CLK2, whereby the switching activity of the electronic switches Sh, Sl, Sbb, S+, S1and S2is synchronized with the switching activity of the half-bridges of the amplifier stage206.

For example,FIG. 27Ashows an embodiment, where the frequency of the clock signal CLK1is half the frequency of the clock signals CLK2. Moreover,FIG. 27Ashows that each channel of the audio amplifier20may operate with a respective clock signal CLK2. For example, inFIG. 27Aare shown two clock signals CLK21and CLK22. Preferably this clock signals CLK21and CLK22have the same frequency.

Accordingly, the synchronization permits to reduce or even avoid a negative effect of the switching activity of the electronic converter30on the amplified audio signals AAS. Specifically, by using synchronized clock signals, the frequency f1of the clock signal CLK1and the frequency f2of the clock signal CLK2have usually a difference Δ, which is greater than 20 kHz, i.e.:
|f1−f2|≥20 kHz.

Conversely, when the signals are not synchronized, it is likely that the amplified audio signal AAS may comprise harmonics of the clock signal CLK1, which may influence negatively the signal to noise ratio.

Moreover, in order to reduce electromagnetic interference (EMI), in various embodiments, the oscillator circuit328may also be configured to generate clock signals, where the frequencies f1and f2are not constant, but may vary over time, while still maintaining the clock signals synchronized.

However, the inventors have observed that the driving as shown inFIG. 27Amay still generate undesired effects in the amplified audio signal AAS, in particular for low amplitude audio signals. Specifically, the switching of the channels of the electronic converter30and/or the audio amplifier20may cause a variation of the supply voltage of the half-bridge SW1/SW2and/or one or more of the voltages provided by the electronic converter30. Accordingly, generally, a mutual influence exists between the switching of the electronic converter30and the various channels of the audio amplifier20. However, while the clock signals CLK1and CLK2ideally switch at the same instant, indeed the various channels and the electronic converter will switch at slightly different instances due to intrinsic jitter of the clock signals, whereby the various channels of the audio amplifier20may indeed switch with substantially different voltage levels during consecutive switching cycles.

The inventors have observed that this mutual influence may be reduced by ensuring that, while the clock signals CLK1and CLK2are synchronized, these clock signals do not switch at the same instant. Accordingly, as shown inFIG. 27B, in various embodiments, a phase shift is introduced in the clock signals by the oscillator circuit328, where preferably a different phase difference is used for each clock signal.

Accordingly, in the embodiment considered, the components for implementing both a SIMO converter30and a class-D audio amplifier20are implemented in a single integrated circuit IC. Specifically, only some external inductors and capacitors have to be connected to the integrated circuit IC and a single supply voltage Vbathas to be provided at the pads/pins300/302of the integrated circuit IC in order to render the audio amplifier20operative. The integration of the various blocks in a common integrated circuit IC permits also to adapt the operation of the system in real time to different operation conditions, such as to variations of the supply voltage Vbus, the operation temperature of the system, the load connected to the output terminals502, whether the audio amplifier indeed is used to amplify audio signals or is switched off, etc.

FIG. 28shows a detailed view in case the integrated circuit IC comprises also a package. Specifically, in the embodiment considered, the pads304,306,308and310of the die are connected to respective pins304′,306′,308′ and310′ of the integrated circuit package via a respective wire bonding. For example, inFIG. 28are shown in addition to the inductances Lbond1and Lbond2associated with the wiring of the pads304and306also inductances L1and L2for the pads308and310. For example, typically such a wire bonding has an inductance between 1 and 10 nH, e.g., between 3 and 4 nH. In case the electronic converter30uses high switching frequencies, also high voltage pulses may be generated at these parasitic inductances, which thus may influence the performance of the system.

In line with the description ofFIG. 23, this problem may be avoided or at least reduced, by interrupting the connection between the electronic converter30and the audio amplifier20, and by using two wire bondings.

For example,FIG. 29shows that at least one output terminal of the electronic converter30, such as the terminal for the voltage V1, is not connected directly to the audio amplifier20within the die of the integrated circuit IC. Specifically, the output terminal of the electronic converter30is connected to a first pad308aof the die. Conversely, the respective input of the audio amplifier20configured to receive the voltage V1is connected to a second pad308bof the die, i.e., the connection of the output terminal of the electronic converter30to the respective input terminal of the audio amplifier20is interrupted within the die of the integrated circuit IC.

In the embodiment shown inFIG. 29, the pads308aand308bare then connected via respective bondings to a common pin308′, i.e., the respective capacitor C1has to be connected only to a single pin308′.

Conversely, in the embodiment shown inFIG. 30, the pads308aand308bare the connected via respective bondings to two separate pins308′aand308′b, i.e., the respective capacitor C1has to be connected to both pins308′aand308′b, thereby short circuiting externally the pins308′aand308′b. In various embodiments, one or more pins of the IC may also be placed between the pins308′aand308′b, thereby further reducing the mutual inductance between the bondings of these pins. Generally, the external connection between the pins308′aand308′bmay also be implemented with other means, such as traces on the printed circuit board.

Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.