Apparatuses and methods for duty cycle adjustments

Apparatuses and methods have been disclosed. One such apparatus includes a plurality of gates coupled together in series. A first pull-down circuit can be coupled to a node between two adjacent gates of the plurality of gates and controlled responsive to a first control signal. A second pull-down circuit can be coupled to an output of one of the gates and controlled responsive to a second control signal. A duty cycle of a signal provided by the plurality of gates can be increased responsive to the first control signal and can be decreased responsive to the second control signal. The plurality of gates and the first and second pull-down circuits can make up a duty cycle adjuster circuit that can adjust the duty cycle of the signal by adjusting only a single type of edges of the signal.

BACKGROUND

Apparatuses such as electronic devices can have a clock circuit that can generate a clock signal to synchronize at least certain circuits within the electronic device. Certain electronic devices (e.g., memory devices) that employ these clock circuits can be manufactured to meet certain timing standards. Thus, a memory device that includes a clock circuit can generate a clock signal to meet a particular timing standard in order to be compatible with other electronic devices that interact with the memory device.

A signal might be generated with relatively small timing inaccuracies and/or a clock path of a circuit can introduce timing inaccuracies into the signal. These timing inaccuracies can be corrected by a duty cycle adjuster circuit (e.g., a duty cycle correction circuit) that can adjust the duty cycle of a clock signal. However, a problem with conventional duty cycle adjuster circuits is that they adjust falling edges of the clock signal to increase duty cycle, but then have to adjust rising edges of the clock signal to decrease the duty cycle. Also, when the rising edges of the clock signal are adjusted, it can impact timing and jitter performance by introducing accuracy mismatches and increasing power and lock time budgets.

FIGS. 1A and 1Billustrate typical prior art duty cycle adjuster circuits.FIG. 1Ashows a schematic diagram of a circuit that can increase the duty cycle of a clock signal as shown by adjusting (e.g., skewing) the falling edges of the clock signal. A low signal on a first inverter101is inverted to a high signal that is inverted back to a low signal at the output of the circuit by a second inverter102. However, the CLK OUT low signal is delayed by the gate delays resulting from the two inverters101,102. Thus, the resulting high signal at the node110between the inverters101,102during that delay can enable the n-channel metal-oxide semiconductor (NMOS) transistors103,104when their control gates are properly biased. A control signal on the first transistor103can then enable that transistor103and the resulting delayed high signal from the CLK OUT can enable the second transistor104such that the node between the two inverters is pulled down. This resulting low signal is inverted to a high signal at CLK OUT, thus adjusting the falling edges of the output clock CLK OUT.

FIG. 1Bshows a circuit that can decrease the duty cycle of a clock signal as shown by adjusting the rising edges of the clock signal. The first two inverters121,122provide (e.g., produce, generate, output, etc.) a substantially similar signal at the middle node127as the input clock CLK IN except delayed by two gate delays from the inverters121,122. A third inverter123provides an inverted clock signal that is delayed by yet another gate delay caused by the third inverter123. These delays provide a high signal at the middle node127at substantially the same time that the control gates of NMOS transistors125,126are biased with enable voltages from a control signal and the delayed signal from the third inverter123. When these transistors125,126turn on, they pull down the middle node127when normally that node would be going high, thus adjusting the rising edges of the output clock CLK OUT. However, such an adjustment of the duty cycle using the rising edges can introduce timing problems with certain standards and jitter performance problems.

There are general needs to adjust a signal duty cycle to deal with timing and jitter performance problems.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure.

The following embodiments include duty cycle adjuster circuits that can adjust the duty cycle of an output signal by adjusting only a single type of edges (e.g., just the falling edges or just the rising edges) of the output signal. For example, whether the duty cycle is to be increased or decreased, only a single type of edges (e.g., either the falling edges or the rising edges, but not both) of the signal is adjusted or vice versa.

FIG. 2illustrates a schematic diagram of an embodiment of a duty cycle adjuster circuit. This circuit includes a plurality of series coupled gates201-204(e.g., inverters). At an INF node, a first pair of transistors200(e.g., NMOS) are coupled together in series between the INF node and a reference voltage node (e.g., circuit ground). The collector of a first transistor205of the first pair of transistors200is coupled to the INF node, the collector of a second transistor206is coupled to the drain of the first transistor205, and the drain of the second transistor206is coupled to the reference voltage node. In another embodiment, the first transistor205and the second transistor206can swap locations.

At the output CLK OUT, a second pair of transistors220(e.g., NMOS) are coupled together in series between the CLK OUT output and the reference voltage node. The collector of a first transistor207of the second pair of transistors220is coupled to the CLK OUT output, the collector of a second transistor208is coupled to the drain of the first transistor207, and the drain of the second transistor208is coupled to the reference voltage node. The first and second pairs of transistors200,220can act as pull-down circuits.

The circuit can receive an input signal CLK IN, provide an output signal CLK OUT, and be responsive to a bias increase control signal BIASINC and a bias decrease control signal BIASDEC. The BIASINC signal is coupled to a control gate of and enables/disables the first transistor205of the first pair of transistors200. The BIASDEC signal is coupled to a control gate of and enables/disables the first transistor207of the second pair of transistors220.

The BIASINC and BIASDEC control signals are shown in the embodiments ofFIGS. 2 and 5as being analog voltage signals coupled to the control gates of their respective transistors. However, another embodiment can incorporate digital, multiple bit bias increase and decrease control signals as shown inFIG. 8and described subsequently.

In the embodiment ofFIG. 2, the BIASINC and BIASDEC signals are both active high. A high signal level can be any voltage that is at least at the threshold voltage of the respective transistor in order to enable the transistor such that it conducts. A low signal level can be any voltage that is less than the threshold voltage of the respective transistors such that the transistor is disabled and does not conduct. Thus, when it is desired to increase the duty cycle of the output signal, the BIASINC signal can be increased to a high level while the BIASDEC signal is at a low level. When it is desired to decrease the duty cycle, the BIASINC signal can be at a low level while the BIASDEC signal can be increased to a high level. Other embodiments can use both active low BIASINC and BIASDEC signals or a combination of active high and active low signals.

The control gate of the second transistor206of the first pair of transistors200is coupled to a CNTL node between two of the inverters202,203. The control gate of the second transistor208of the second pair of transistors220is coupled to the INF node.

FIG. 3illustrates an embodiment of a timing diagram for a duty cycle increase operation of the circuit ofFIG. 2. The timing diagram shows only a single pulse for purposes of clarity. However, one skilled in the art would realize that the circuit ofFIG. 2would work the same with a signal comprising a plurality of pulses.

Referring to bothFIG. 2andFIG. 3, the CLK IN pulse is shown going from a low level to a high level into the first gate201. The output of the first gate201is the INF node that is shown going to a low level. The low-going INF signal is delayed from the CLK IN signal by one gate delay.

The INF signal is input to the second gate202that can then invert it and generate the CNTL signal at the CNTL node. This signal is delayed from the CLK IN signal by two gate delays and is used to control the second transistor206. When the CNTL signal reaches a threshold voltage for the second transistor206, the second transistor206can turn on and conduct when both the first transistor205is turned on and when the INF signal reaches a collector voltage high enough above the reference. Thus, when the BIASINC signal is high, the INF signal is high, and the CNTL signal is high, the INF node can be pulled down.FIG. 3shows the time301on the CNTL signal where, due to the gate delays, the CNTL signal and the INF signal would be high substantially simultaneously. The time300where the INF signal is pulled low is shown matching up with the time301of the CNTL signal.

The delay of the rising edge of the INF signal going high at area300can cause the CLK OUT signal to be delayed as well. This has the effect of moving the falling edge of CLK OUT by a particular time represented by ΔT′. The delay of the rising edge of the INF signal can be controlled by the BIASINC signal.

As shown inFIG. 2, ΔT′ can be determined by the quantity of gates (e.g., gate delay) between the INF node and the output of the circuit. Thus, in order to change the amount ΔT′ by which the CLK OUT signal can be adjusted, the quantity of gates between the INF node and the output of the circuit can be changed. Increasing the quantity of gates can increase ΔT′ and decreasing the quantity of gates can decrease ΔT′.

During the duty cycle increase operation, the second pair of transistors220are turned off since BIASDEC is at a low level. Thus, this circuit220has no affect on the CLK OUT signal at this time.

The above described embodiment assumes a digital implementation of the embodiment ofFIG. 2. In other words, when the BIASINC signal is a logical high state (e.g., at threshold voltage of transistor205), the transistor205is turned on. However,FIG. 2can also operate in an analog implementation. In such an embodiment, the voltage level of the BIASINC signal above the threshold voltage of transistor205can determine the amount of adjustment of the duty cycle. Thus, increasing the voltage level of the BIASINC signal will increase ΔT′. For example, if the threshold level of transistor205is 0.5V, any voltage level for BIASINC that is above 0.5V will increase ΔT′.

Additionally, the strength of the pull down of the first pair of transistors200can affect the duty cycle change. The inverter201includes an internal pull up resistor (not shown). The ratio of the pull down, effected by the first pair of transistors200, to the pull up of the internal pull up resistor of inverter201can adjust the duty cycle. For example, increasing the BIASINC voltage level can increase the pull down strength and, thus, increase ΔT′.

FIG. 4illustrates a timing diagram of an embodiment of a duty cycle decrease operation of the circuit ofFIG. 2. The timing diagram shows only a single pulse for purposes of clarity. However, one skilled in the art would realize that the circuit ofFIG. 2would work the same with a signal comprising a plurality of pulses.

Referring to bothFIG. 2andFIG. 4, the CLK IN pulse is shown going from a low level to a high level into the first gate201. The output of the first gate201is the INF node that is shown going to a low level. The low-going INF signal is delayed from the CLK IN signal by one gate delay. ΔT is the maximum duty cycle increase amount. The duty cycle increase is controlled by the strength ratio of pull down220

The INF signal is input to the second gate202that can then invert it and generate the CNTL signal at the CNTL node. The INF signal can also be used to control the second transistor208of the second pair of transistors220. When the INF signal reaches a threshold voltage for the second transistor208, the second transistor208can turn on and conduct when both the first transistor207of the pair of transistors220is turned on and when the CLK OUT signal reaches a collector voltage high enough above the reference. Thus, when the BIASDEC signal is high, the INF signal is high, and the CLK OUT signal is high, the CLK OUT output node can be pulled down by the second pair of transistors220at a time ΔT prior to when the CLK OUT signal would normally go low.FIG. 4shows the point401on the CLK OUT signal where, due to the gate delays, the CLK OUT signal and the INF signal would be high substantially simultaneously.

As in the duty cycle increase embodiment above, the time period ΔT′ that the duty cycle can be decreased can be determined by the quantity of gates (e.g., gate delay) between the INF node and the output of the circuit. Thus, in order to change the amount ΔT′ by which the CLK OUT signal can be adjusted, the quantity of gates between the INF node and the output of the circuit can be changed. Increasing the quantity of gates can increase ΔT′ and decreasing the quantity of gates can decrease ΔT′.

During the duty cycle decrease operation, the first pair of transistors200are turned off since BIASINC is at a low level. Thus, this circuit200has no affect on the CLK OUT signal at this time.

The above described embodiment inFIG. 4assumes a digital implementation of the embodiment ofFIG. 2. In other words, when the BIASDEC signal is a logical high state (e.g., at threshold voltage of transistor207), the transistor207is turned on. However,FIG. 2can also operate in an analog implementation. In such an embodiment, the voltage level of the BIASDEC signal above the threshold voltage of transistor207can determine the amount of adjustment of the duty cycle. Thus, increasing the voltage level of the BIASDEC signal will decrease ΔT′. For example, if the threshold level of transistor207is 0.5V, any voltage level for BIASDEC that is above 0.5V will decrease ΔT′.

Additionally, the strength of the pull down of the second pair of transistors220can affect the duty cycle change. The inverter204includes an internal pull up resistor (not shown). The ratio of the pull down, effected by the second pair of transistors220, to the pull up of the internal pull up resistor of inverter204can adjust the duty cycle. For example, increasing the BIASDEC voltage level can increase the pull down strength and, thus, decrease ΔT′.

FIG. 5illustrates another embodiment of a duty cycle adjuster circuit. This embodiment enables a range of time for the duty cycle adjustment. This range can be illustrated inFIG. 5as a time period between ΔT1and ΔT2. The ΔT1and ΔT2times can be the same or different. As seen in the circuit ofFIG. 5, ΔT1can be adjusted by the quantity of gates (e.g., gate delay) between the input node CLK IN and a CF node. Similarly, ΔT2can be adjusted by the quantity of gates between the output node CLK OUT and an INF node. ΔT1+ΔT2indicates a maximum range of duty cycle change amount.

The circuit ofFIG. 5comprises a plurality of gates501-504(e.g., inverters) coupled in series. At an INF node, a first pair of transistors500(e.g., NMOS) are coupled together in series between the INF node and a reference voltage node (e.g., circuit ground). The collector of a first transistor510of the first pair of transistors500is coupled to the INF node, the collector of a second transistor511is coupled to the drain of the first transistor510, and the drain of the second transistor511is coupled to the reference voltage.

At the output CLK OUT, a second pair of transistors520(e.g., NMOS) are coupled together in series between the CLK OUT output and the reference voltage node. The collector of a first transistor512of the second pair of transistors520is coupled to the CLK OUT output, the collector of a second transistor513is coupled to the drain of the first transistor512, and the drain of the second transistor513is coupled to the reference voltage node.

At a CF node, a third pair of transistors530(e.g., PMOS) are coupled between the CF node and a voltage source node (e.g., supply voltage node). The collector of a first transistor514of the third pair of transistors530is coupled to the voltage source node, the collector of a second transistor515is coupled to the drain of the first transistor514, and the drain of the second transistor515is coupled to the CF node. The first and second pairs of transistors500,520can act as pull-down circuits while the third pair of transistors530can act as a pull-up circuit.

The circuit can receive an input signal CLK IN, provide an output signal CLK OUT, and be responsive to a bias increase control signal BIASINC, and a bias decrease control signal BIASDEC. The BIASINC signal is coupled to a control gate of and enables/disables the first transistor510of the first pair of transistors500and the first transistor of the third pair of transistors530. The BIASDEC signal is coupled to a control gate of and enables/disables the first transistor512of the second pair of transistors520.

In a digital implementation of the embodiment ofFIG. 5, the BIASINC and BIASDEC signals are both active high. A high signal level can be any voltage that is at least at the threshold voltage of the respective transistor in order to enable the transistor such that it conducts. A low signal level can be any voltage that is less than the threshold voltage of the respective transistors such that the transistor is disabled and does not conduct. Thus, when it is desired to increase the duty cycle of the output signal, the BIASINC signal can be increased to a high level while the BIASDEC signal is at a low level. When it is desired to decrease the duty cycle, the BIASINC signal can be at a low level while the BIASDEC signal can be increased to a high level. Other embodiments can use active low BIASINC and BIASDEC signals or a combination of active high and active low signals.

The control gate of the second transistor511of the first pair of transistors500is coupled to a CNTL node between two of the gates502,503. The control gate of the second transistor513of the second pair of transistors520is coupled to the INF node. The control gate of the second transistor514of the third pair of transistors530is coupled to the input CLK IN. Using the types of transistors illustrated inFIG. 5, each of the second transistors511,513of the first and second pairs of transistors500,520can be enabled by a high signal while the second transistor514of the third pair of transistors530can be enabled by a low signal.

In an analog implementation of the embodiment ofFIG. 5, the voltage level of the BIASINC signal above the threshold voltage of transistor510can determine the amount of adjustment of the duty cycle. Thus, increasing the voltage level of the BIASINC signal will increase ΔT′. For example, if the threshold level of transistor510is 0.5V, any voltage level for BIASINC that is above 0.5V will increase ΔT′.

Additionally, the strength of the pull down of the first pair of transistors500can affect the duty cycle change. The inverter501includes an internal pull up resistor (not shown). The ratio of the pull down, effected by the first pair of transistors500, to the pull up of the internal pull up resistor can adjust the duty cycle. For example, increasing the BIASINC voltage level above the transistor510threshold level can increase the pull down strength and, thus, increase ΔT′.

Similarly, in an analog implementation of the embodiment ofFIG. 5, the voltage level of the BIASDEC signal above the threshold voltage of transistor512can determine the amount of adjustment of the duty cycle. Thus, increasing the voltage level of the BIASDEC signal will decrease ΔT′. For example, if the threshold level of transistor512is 0.5V, any voltage level for BIASINC that is above 0.5V will decrease ΔT′.

Additionally, the strength of the pull down of the second pair of transistors520can affect the duty cycle change. The inverter504includes an internal pull up resistor (not shown). The ratio of the pull down, effected by the second pair of transistors520, to the pull up of the internal pull up resistor can adjust the duty cycle. For example, increasing the BIASDEC voltage level above the transistor512threshold level can increase the pull down strength and, thus, decrease ΔT′.

FIG. 6illustrates an embodiment of a timing diagram for a duty cycle increase operation of the circuit ofFIG. 5. The timing diagram shows only a single pulse for purposes of clarity. However, one skilled in the art would realize that the circuit ofFIG. 5would work the same with a signal comprising a plurality of pulses.

Referring to bothFIG. 5andFIG. 6, the CLK IN pulse is shown going from a low level to a high level into the first gate501. The output of the first gate501is the INF node that is shown going to a low level. The low-going INF signal is delayed from the CLK IN signal by one gate delay.

The INF signal is input to the second gate502that can then invert it and generate the CNTL signal at the CNTL node. This signal is delayed from the CLK IN signal by two gate delays and is used to control the second transistor511. When the CNTL signal reaches a threshold voltage for that transistor511, the transistor511can turn on and conduct when both the first transistor510is turned on and when the INF signal reaches a collector voltage high enough above the reference. Thus, when the BIASINC signal is high, the INF signal is high, and the CNTL signal is high, the INF node can be pulled down.FIG. 6shows the time601on the CNTL signal where, due to the gate delays, the CNTL signal and the INF signal would be high substantially simultaneously. The time600where the INF signal is pulled low is shown matching up with the time601of the CNTL signal.

The delay of the INF signal going high at point600can cause the CLK OUT signal to be delayed as well. This has the effect of moving the falling edge of CLK OUT by a particular time represented by ΔT′.

During the duty cycle increase operation, the second pair of transistors520and the third pair of transistors530are turned off since BIASDEC is at a low level such that the first transistor512is turned off and BIASINC is at a high level such that the first transistor515is turned off (the PMOS transistor515is enabled with an active low signal). Thus, the second520and third pairs of transistors520,530have no affect on the CLK OUT signal during this operation.

FIG. 7illustrates an embodiment of a timing diagram for a duty cycle decrease operation of the circuit ofFIG. 5. The timing diagram shows only a single pulse for purposes of clarity. However, one skilled in the art would realize that the circuit ofFIG. 5would work the same with a signal comprising a plurality of pulses.

Referring to bothFIG. 5andFIG. 7, the CLK IN pulse is shown going from a low level to a high level into the first gate501. The output of the first gate501is the INF node that is shown going to a low level. The low-going INF signal is delayed from the CLK IN signal by one gate delay.

The INF signal is input to the second gate502that can then invert it and generate the CNTL signal at the CNTL node. The INF signal can also be used to control the second transistor513of the second pair of transistors520. When the INF signal reaches a threshold voltage for that transistor513, the transistor513can turn on and conduct when both the first transistor512of the pair of transistors520is turned on and when the CLK OUT signal reaches a collector voltage high enough above the reference. This has the effect of pulling the output down at a time ΔT2from when it normally would go low. Additionally, since the BIASINC signal is low during this operation, the third pair transistors530can conduct when both the CLK IN signal are low and the CF node goes low. This has the effect of pulling the CF node high at a time ΔT1prior to when the CF node would normally go high. Thus, the duty cycle can be adjusted in the range approximately between ΔT1and ΔT2. The range700when these signals are true is indicated inFIG. 7.

In the embodiment ofFIG. 5, since the quantity of gates that determine ΔT1is equal to the quantity of gates that determine ΔT2, ΔT1=ΔT2. By increasing the quantity of gates between the INF node and the output, ΔT2can be increased. By increasing the quantity of gates between the input and the CF node, ΔT1can be increased. In order to keep proper signal level for each node when increasing and decreasing the quantity of gates, the INF node can be located after a first odd number of gates, the CNTL node can be located after first even number of gates, the CF node can be located after a second odd number of gates, and the CLK OUT output can be located after a second even number of gates where the second odd number of gates is greater than first odd number of gates and the second even number of gates is greater than the first even number of gates.

FIG. 8illustrates an embodiment of any of the first or second transistor pairs200,202,500,502ofFIG. 2or5. As discussed previously, the circuits of those figures used an analog voltage signal to enable/disable the first transistors205,207,510,512in the pair of transistors200,202,500,502. The embodiment ofFIG. 8can use a multiple bit, digital control signal to control the duty cycle adjuster circuits.

The embodiment ofFIG. 8comprises a plurality of transistors800-803connected in parallel that together act as the first transistors of the above circuits. The control gates of each transistor800-803can be coupled to a different enable signal. Thus, a four bit control word comprising BIAS0, BIAS1, BIAS2, BIAS3can be used to control the circuit (assuming the second transistor810is enabled as described previously). The active state of each enable signal can be determined by the type of transistor (e.g., NMOS, PMOS) used as each of the parallel coupled transistors800-803.

For example, a1111control word provided to the circuit illustrated inFIG. 8would enable all of the transistors800-803if the transistors were NMOS transistors that can be enabled with an active high signal. If the second and fourth transistors801,803were replaced with PMOS transistors, however, a0000control word would enable all of the transistors800-803.

In an analog implementation of the embodiment ofFIG. 8, the voltage level of the BIAS0-BIAS3signals above the threshold voltage of their respective transistors800-803can determine the amount of adjustment of the duty cycle. Thus, increasing the voltage level of the BIAS0-BIAS3signals will increase ΔT′. For example, if the threshold level of transistor800is 0.5V, any voltage level for BIAS0that is above 0.5V will increase ΔT′.

Additionally, the strength of the pull down of any one of the plurality of transistors800-803can affect the duty cycle change. The ratio of the pull down, effected by the plurality of transistors800-803, to the pull up of an internal pull up resistor of any gate coupled to the INF node can adjust the duty cycle. For example, increasing the BIAS0voltage level above the transistor800threshold level can increase the pull down strength and, thus, increase ΔT′.

The above embodiments illustrate the transistors as being NMOS transistors. Other embodiments can use PMOS transistors.

Accordingly, the quantity and types of transistors shown inFIG. 8are for purposes of illustration only. The quantities and types of transistors can determine the control word content and size.

As used herein, an apparatus may refer to, for example, circuitry, an integrated circuit die, a memory device, a memory array, or a system including such a circuit, die, device or array.

CONCLUSION

One or more embodiments of the duty cycle adjuster circuit can adjust a single type of edges of a signal in order to both increase and decrease a duty cycle. This can result in better jitter performance and output data eye window in a system by eliminating a duty cycle variable on a jitter source due to a rising edge timing being adjusted. The present embodiments can also provide energy efficiency advantages over the prior art by saving power on digital locked loop control logic by providing a more predictable locking time.