SEMICONDUCTOR PACKAGE

A semiconductor package comprises: a first package substrate; a semiconductor device mounted on a first surface of the first package substrate and connected to the first package substrate; a plurality of connection pads on a second surface of the first package substrate; a plurality of external connection terminals respectively disposed on one or more connection pads of the plurality of connection pads; a plurality of passive elements mounted on one or more connection pads of the plurality of connection pads in which the plurality of external connection terminals are not disposed; and a floating structure disposed between at least one passive element from the plurality of passive elements and at least one external connection terminal from the plurality of external connection terminals, spaced apart from the at least one passive element and the at least one external connection terminal, and disposed on the second surface of the first package substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0039248, filed on Mar. 24, 2023, and Korean Patent Application No. 10-2023-0071014, filed on Jun. 1, 2023 in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

BACKGROUND

The embodiments relate to a semiconductor package.

2. Background of Related Art

In a semiconductor package, a land side capacitor (LSC) may be provided on the opposite side of a package substrate on which a semiconductor chip is mounted. A semiconductor package including a LSC may be mounted on a substrate. The semiconductor package may be mounted on the substrate, and an underfill layer may be interposed between the semiconductor package and the substrate. However, when a semiconductor chip mounted inside the semiconductor package is performing an operation and a temperature of the semiconductor package rises, a bulky underfill layer located near the LSC without solder balls thermally expands. Due to the thermal expansion of the underfill layer, cracks may occur in solder balls positioned around the LSC.

SUMMARY

The problem to be solved by the embodiments of the present disclosure is to provide a semiconductor package with improved reliability.

The problem to be solved by the embodiments of the present disclosure is not limited to the above-mentioned problems, and other problems not mentioned are clearly understood by those skilled in the art from the following description.

According to one or more embodiments, a semiconductor package comprises: a first package substrate; a semiconductor device mounted on a first surface of the first package substrate and electrically connected to the first package substrate; a plurality of connection pads on a second surface of the first package substrate; a plurality of external connection terminals respectively disposed on one or more connection pads of the plurality of connection pads; a plurality of passive elements mounted on one or more connection pads of the plurality of connection pads in which the plurality of external connection terminals are not disposed; and a floating structure disposed between at least one passive element from the plurality of passive elements and at least one external connection terminal from the plurality of external connection terminals, spaced apart from the at least one passive element and the at least one external connection terminal, and disposed on the second surface of the first package substrate, where the floating structure is insulated.

According to one or more embodiments, a semiconductor package comprises: a first redistribution structure; a semiconductor device mounted on first surface of the first redistribution structure and electrically connected to the first redistribution structure; a plurality of connection pads on a second surface of the first redistribution structure; a plurality of external connection terminals respectively disposed on at least one or more connection pads of the plurality of connection pads; and a plurality of passive elements mounted on one or more connection pads of the plurality of connection pads in which the plurality of external connection terminals are not disposed; an external substrate on which the first redistribution structure is mounted, and being electrically connected to at least one external connection terminal from the plurality of external connection terminals; a floating structure provided on the second surface of the first redistribution structure in a non-connection terminal area; and an underfill layer provided between the external substrate and the first redistribution structure, wherein the floating structure is insulated, and wherein the non-connection terminal area is defined as an area between the external substrate and the first redistribution structure where the plurality of external connection terminals are not disposed and the plurality passive elements are included.

According to one or more embodiments, a semiconductor package comprises: a first redistribution structure; a first semiconductor device mounted on a first surface of the first redistribution structure, electrically connected to the first redistribution structure, and including an application processor (AP); a plurality of connection pads on a second surface of the first redistribution structure; a plurality of external connection terminals respectively disposed on one or more connection pads of the plurality of connection pads; and a plurality of passive elements mounted on one or more connection pads of the plurality of connection pads in which the plurality of external connection terminals are not disposed; a floating structure disposed between at least one passive element from the plurality of passive elements and at least one external connection terminal from the plurality of external connection terminals, spaced apart from the at least one passive element and the at least one external connection terminal, and disposed on a second surface of the first redistribution structure; an external substrate on which the first redistribution structure is mounted and electrically connected to the external connection terminal; an underfill layer provided between the external substrate and the first redistribution structure; an encapsulant surrounding the first semiconductor device, on the first surface of the first redistribution structure; a second redistribution structure disposed on the encapsulant; a conductive post penetrating the encapsulant and electrically connecting the second redistribution structure and the first redistribution structure to each other; and a second semiconductor device mounted on a surface of the second redistribution structure and including a memory device, wherein the floating structure is insulated, wherein an adhesive layer is interposed between the floating structure and the second surface of the first redistribution structure so that the floating structure is attached by the adhesive layer, wherein the floating structure is between the first redistribution structure and the external substrate, in an overlapping region overlapping a shape of the first semiconductor device in a vertical direction, and the vertical direction is a direction perpendicular to the first and second surfaces of the first redistribution structure, and the floating structure is made of a material including silicon or polymer.

DETAILED DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and descriptions already given for them are omitted.

A layer may be described as having an upper surface and a lower surface. As understood by one of ordinary skill in the art, the surfaces of a layer may also be described as first and second surfaces, where a first surface may be one of the upper surface and the lower surface of the layer, and the second surface may be the other of the upper surface and the lower surface of the layer.

FIG.1is a plan view illustrating a semiconductor package1A according to one or more embodiments.FIG.2is a cross-sectional view taken along line AA′ of the semiconductor package ofFIG.1according to one or more embodiments.FIG.3is a cross-sectional view taken along the same line AA′ as that ofFIG.2in the semiconductor package according to one or more embodiments.FIG.4is an enlarged view of a portion B of the cross-sectional view of the semiconductor package ofFIG.2according to one or more embodiments.FIG.5is an enlarged view of the portion B as shown inFIG.4in a cross-section of a semiconductor package1A according to one or more embodiments.

Referring toFIGS.1to5, the semiconductor package1A may include a first redistribution structure100and an internal semiconductor device200mounted on the first redistribution structure100. A semiconductor package1B (FIG.3) according to one or more embodiments may include a first redistribution structure100and the internal semiconductor device200mounted on the first redistribution structure100, and may further include a plurality of conductive posts310disposed around the internal semiconductor device200and spaced apart from the internal semiconductor device200, a second redistribution structure400disposed on the internal semiconductor device200, and an upper semiconductor device500mounted on the second redistribution structure400. Because most of the description of the semiconductor package1A, which is one or more embodiments, is included in the description of the semiconductor package1B, most of the description of the semiconductor package1A may be replaced by a description of the semiconductor package1B.

The semiconductor package1B may be a fan-out semiconductor package in which a horizontal width and a horizontal area of the first redistribution structure100are larger than those of the internal semiconductor device200. In one or more examples, the term horizontal refers to an X-Y plane, the first horizontal direction refers to an X-axis direction, and the second horizontal direction refers to a Y-axis direction. In some embodiments, the semiconductor package1B may be a fan-out wafer level package (FOWLP) or a fan-out panel level package (FOPLP). A semiconductor package1G, which is one or more embodiments in the case of a panel level package, is described below with reference toFIG.9.

In some embodiments, the first redistribution structure100may be formed by a redistribution process. In one or more examples, the first redistribution structure100may be referred to as a first package substrate. The first package substrate includes a printed circuit board (PCB) substrate. A case in which the first package substrate is the PCB substrate is described below with reference toFIG.10.

The first redistribution structure100may include a redistribution insulating layer110and a plurality of redistribution patterns120. The redistribution insulating layer110may cover the plurality of redistribution patterns120. In some embodiments, the first redistribution structure100may include a plurality of stacked redistribution insulating layers110. The redistribution insulating layer110may be formed of, for example, photo imageable dielectric (PID) or photosensitive polyimide (PSPI).

The plurality of redistribution patterns120may include a plurality of redistribution line patterns121and a plurality of redistribution via patterns122. The plurality of redistribution patterns120may be, for example, a metal, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru) or an alloy of the metal, but is not limited thereto.

As illustrated inFIG.2, the plurality of redistribution line patterns121may be disposed on at least one of upper and lower surfaces of the redistribution insulating layer110. For example, when the first redistribution structure100includes a plurality of stacked redistribution insulating layers110, the plurality of redistribution line patterns121may be disposed between an upper surface of the uppermost redistribution insulating layer110, a lower surface of the lowermost redistribution insulating layer110, and adjacent redistribution insulating layers110. As illustrated inFIG.2, the plurality of redistribution line patterns121extend in the Y direction, and the plurality of redistribution via patterns122extend in the X direction.

The plurality of redistribution via patterns122may pass through the redistribution insulating layer110and be connected to some of the plurality of redistribution line patterns121. In some embodiments, the plurality of redistribution via patterns122may have a tapered shape extending from an upper side of a first redistribution layer to a lower side of a second redistribution layer with a larger horizontal width. In the tapered shape of the plurality of redistribution via patterns122, the direction in which the horizontal width of the tapered shape increases may vary depending on the process of the structure, or may vary depending on the process of the first redistribution structure100. As understood by one of ordinary skill in the art, the embodiments of the present disclosure are not limited by the shape of the plurality of redistribution via patterns122.

In some embodiments, one or more of the plurality of redistribution line patterns121may be formed together with one or more of the plurality of redistribution via patterns122to form an integral body. For example, the redistribution line pattern121and the redistribution via pattern122contacting the lower surface of the redistribution line pattern121may be formed together to form an integral body.

Among the plurality of redistribution patterns120, one or more of the redistribution patterns120disposed adjacent to the lower surface of the first redistribution structure100may be referred to as a plurality of first lower surface connection pads130B and one or more of the redistribution patterns120disposed adjacent to the upper surface of the first redistribution structure100may be referred to as a plurality of first upper surface connection pads130U. For example, the plurality of first lower surface connection pads130B may be one or more of the plurality of redistribution line patterns121disposed adjacent to the lower surface of the first redistribution structure100, and the plurality of upper surface connection pads130U may be one or more of the plurality of redistribution line patterns121disposed adjacent to the upper surface of the first redistribution structure100. Accordingly, each redistribution pattern120may be one of an upper surface connection pad130U or a lower surface connection pad130B.

A plurality of external connection terminals140may be respectively attached to the plurality of first lower surface connection pads130B. The plurality of external connection terminals140may connect the semiconductor package1B to an external substrate600. The external substrate600may be a printed circuit board (PCB) substrate on which other semiconductor devices are mounted. A plurality of external substrate pads610disposed on the upper surface of the external substrate600may be electrically connected to the plurality of first lower surface connection pads130B disposed on the lower surface of the first redistribution structure100through the plurality of external connection terminals140. In some embodiments, the plurality of external connection terminals140may be solder bumps or solder balls. In one or more examples, a plurality of chip connecting members242may be attached to one or more of the plurality of first upper surface connection pads130U, and a plurality of conductive posts310may be disposed to other one or more of the plurality of first upper surface connection pads130U.

The plurality of upper surface connection pads130U may be disposed on an upper surface of the redistribution insulating layer110. For example, when the first redistribution structure100includes a plurality of stacked redistribution insulating layers110, the plurality of upper surface connection pads130U may be disposed on the upper surface of the uppermost redistribution insulating layer110.

As illustrated inFIG.3, at least one internal semiconductor device200may be mounted on the first redistribution structure100. For example, a single internal semiconductor device200or a plurality of internal semiconductor devices200may be mounted on the first redistribution structure100. The internal semiconductor device200may include a semiconductor substrate210having an active surface210F and an inactive surface facing each other, a front end of line layer (FEOL)220formed on the active surface210F of the semiconductor substrate210, a back end of line (BEOL) layer230provided under the FEOL layer220, and a plurality of chip pads241disposed on a first surface of the internal semiconductor device200. For example, the internal semiconductor device200may have a thickness of about 150 μm or more in a vertical direction.

In one or more examples, the first and second surfaces of the internal semiconductor device200face each other, and the second surface of the internal semiconductor device200refers to the inactive surface310B of the semiconductor substrate210. An active surface210F of the semiconductor substrate210may be adjacent to the first surface of the internal semiconductor device200. Therefore, the FEOL layer220and the BEOL layer230corresponding to the semiconductor element layers may be thicker than the actual semiconductor device300.

In some embodiments, the internal semiconductor device200may have a face down arrangement with the first surface facing the first redistribution structure100and may be mounted on an upper surface of the first redistribution structure100. In this case, the first surface of the internal semiconductor device200may be referred to as a lower surface of the internal semiconductor device200, and the second surface of the internal semiconductor device200may be referred to as an upper surface of the internal semiconductor device200.

A plurality of chip connection members242may be between the plurality of chip pads241of the internal semiconductor device200and one or more of the plurality of first upper surface connection pads130U of the first redistribution structure100. For example, each of the plurality of chip connecting members242may be a solder ball or a micro bump. The internal semiconductor device200and the redistribution pattern120of the first redistribution structure100may be electrically connected to each other through a plurality of chip connection members242. The plurality of chip connection members242may include an under bump metal (UBM) layer disposed on the plurality of chip pads and a conductive connection member covering the UBM layer. The plurality of chip connecting members242may be formed of, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Tin), gold (Au), or solder, but are not limited thereto.

The semiconductor substrate210may include, for example, a semiconductor material, such as silicon (Si) or germanium (Ge). In one or more examples, the semiconductor substrate210may include compound semiconductor materials, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate210may include a well doped with impurities, which may operate as a conductive region. The semiconductor substrate210may have various device isolation structures, such as a shallow trench isolation (STI) structure.

A semiconductor device including a plurality of individual devices of various types may be formed on the active surface of the semiconductor substrate210. The plurality of individual devices may be electrically connected to the conductive region of the semiconductor substrate210. The semiconductor device may further include a conductive line or a conductive plug electrically connecting the plurality of individual devices to the conductive region of the semiconductor substrate210. In addition, each of the plurality of individual elements may be electrically separated from other neighboring individual elements by an insulating film.

In some embodiments, the internal semiconductor device200may include a logic device. For example, the internal semiconductor device200may be a central processing unit chip, a graphics processing unit chip, or an application processor (AP). In other embodiments, when the semiconductor package1includes a plurality of internal semiconductor devices200, one of the plurality of internal semiconductor devices200may be a central processing unit chip, a graphics processing unit chip, or an application processor chip, and another one of the internal semiconductor devices200may be a memory semiconductor chip including a memory device. As understood by one of ordinary skill in the art, in one or more examples, the semiconductor package1may include only internal semiconductor devices200that are processors, or only internal semiconductor devices200that are memory chips.

The memory device may be a non-volatile memory device, such as a flash memory, a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In some embodiments, the memory device may be a volatile memory device, such as dynamic random access memory (DRAM) or static random access memory (SRAM).

In one or more examples, the internal semiconductor device200may be a semiconductor device in which a plurality of semiconductor chips are vertically stacked. The plurality of semiconductor chips may be stacked semiconductor chips including through-silicon vias (TSVs).

An encapsulant320may cover the internal semiconductor device200and a plurality of conductive posts310(FIG.3) on the upper surface of the first redistribution structure100. The encapsulant320may fill a space between the first redistribution structure100and the second redistribution structure400to be described below. For example, the encapsulant320may have a thickness of about 150 μm to about 500 μm. For example, the encapsulant320may be a molding member including an epoxy mold compound (EMC). The encapsulant320may further include a filler. In the semiconductor package1A, according to one or more embodiments, as shown inFIG.1, a vertical level of the upper surface of the encapsulant320may be the same as a vertical level of the upper surface of the internal semiconductor device200. In one or more examples, the vertical level of the upper surface of the encapsulant320may be higher than the vertical level of the upper surface of the internal semiconductor device200.

In some embodiments, a first underfill layer250surrounding the plurality of chip connection members242may be between the internal semiconductor device200and the first redistribution structure100. In some embodiments, the first underfill layer250may fill a space between the internal semiconductor device200and the first redistribution structure100and may cover a lower portion of a side surface of the internal semiconductor device200. The first underfill layer250may be formed by, for example, a capillary underfill process and made of an epoxy resin.

In some embodiments, the side surface of the first redistribution structure100, the side surface of the encapsulant320, and the side surface of the second redistribution structure400may be aligned with each other in the vertical direction to form a coplanar surface.

The plurality of conductive posts310may penetrate the encapsulant320and electrically connect the first redistribution structure100to the second redistribution structure400. The plurality of conductive posts310may be spaced apart from the internal semiconductor device200in a horizontal direction and provided between the first redistribution structure100and the second redistribution structure400. For example, the plurality of conductive posts310may be spaced apart from the internal semiconductor device300in a horizontal direction and may be disposed outside the internal semiconductor device200on the upper surface of the first redistribution structure100. In one or more examples, the second redistribution structure400may be referred to as a second package substrate.

In one or more examples, the plurality of conductive posts310may be between a plurality of first upper surface connection pads130U and a plurality of second lower surface connection pads to be described below. The plurality of second lower surface connection pads may be provided on the lower surface of the second redistribution structure. Bottom surfaces of the plurality of conductive posts410may contact the plurality of upper surface connection pads130U on the upper surface of the first redistribution structure100to be electrically connected to the plurality of redistribution patterns120by, and upper surfaces of the plurality of conductive posts310may contact the plurality of second lower surface connection pads of the second redistribution structure400to be electrically connected to the plurality of redistribution patterns420.

In one or more examples, similar to the first redistribution structure100, the second redistribution structure400may include a redistribution insulating layer and a plurality of redistribution patterns420. The redistribution insulating layer may cover the plurality of redistribution patterns420. InFIG.2, the configuration of the second redistribution structure400is substantially the same as that of the first redistribution structure100. Therefore, the description already given for the second redistribution structure400may be omitted.

Referring toFIG.3, the upper semiconductor device500may be mounted on the second upper surface connection pad located on the upper surface of the second redistribution structure400. The upper semiconductor device500may be a semiconductor package including a semiconductor chip. Accordingly, the semiconductor package1B according to one or more embodiments may have a package-on-package (POP) structure.

A plurality of connection members542may be interposed between the plurality of connection pads541provided under the upper semiconductor device500and the plurality of secondary upper surface connection pads provided on the upper surface of the second redistribution structure400. For example, each of the plurality of connection members542may be a solder ball or a micro bump. The plurality of connecting members542may be formed of, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Tin), gold (Au), or solder, but are not limited thereto.

In some embodiments, a second underfill layer550surrounding the plurality of connection members542may be between the upper semiconductor device500and the second redistribution structure400. The second underfill layer550may fill a space between the upper semiconductor device500and the second redistribution structure400and may cover a lower portion of a side surface of the upper semiconductor device500. The second underfill layer550may be formed by, for example, a capillary underfill process and made of an epoxy resin.

The semiconductor chip included in the upper semiconductor device500may be a semiconductor chip including a non-volatile memory device, such as a flash memory, a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In some embodiments, the memory device may be a semiconductor chip including a volatile memory device, such as dynamic random access memory (DRAM) or static random access memory (SRAM).

The semiconductor chip included in the upper semiconductor device500may be a central processing unit chip, a graphics processing unit chip, or an application processor chip. In other embodiments, when the upper semiconductor device500includes a plurality of semiconductor chips, one of the plurality of semiconductor chips may be a central processing unit chip, a graphics processing unit chip, or an application processor chip, and another one of the plurality of semiconductor chips may be a memory semiconductor chip including a memory device.

Because the upper semiconductor device500is electrically connected to the second upper surface connection pad, the conductive posts410and the first redistribution structure100, the upper semiconductor device500may be electrically connected to the internal semiconductor device200. In addition, the upper semiconductor device500may exchange electrical signals with external devices through the plurality of external connection terminals140and the external substrate pad610.

Passive elements150may be provided on a first lower surface connection pad130B on the lower surface of the first redistribution structure100. The passive element150may be any one of a capacitor, an inductor, and a resistor. For example, a first passive element150A (FIG.1), a second passive element150B (FIG.1), and a third passive element150C (FIG.5) may be provided on the first lower surface connection pad130B disposed on the lower surface of the first redistribution structure100. The first passive element150A, the second passive element150B, and the third passive element150C may be any one of a capacitor, an inductor, and a resistor.

On the lower surface of the first redistribution structure100, a first external connection terminal140may be spaced apart from the passive elements around the passive elements. For example, as shown inFIG.1, the first passive element150A may be spaced apart from the adjacent external connection terminal140by a certain distance. Similarly, the second passive element150B and the third passive element150C may be spaced apart from the adjacent external connection terminal140by a certain distance. For example, an area where the external connection terminal140is not provided exists around the first passive element150A, the second passive element150B, and the third passive element150C.

As inFIG.1, an area adjacent to the first passive element150A and not provided with the external connection terminal140may be referred to as a first non-connection terminal area NB1. An area adjacent to the second passive element150B and not provided with the external connection terminal140may be referred to as a second non-connection terminal area NB2. An area adjacent to the third passive element150C and not provided with the external connection terminal140may be referred to as a third non-connection terminal area NB3. The first non-connection terminal area NB1, the second non-connection terminal area NB2, and the third non-connection terminal area NB3may be referred to as a first no-solder ball area, a first no-solder ball area, and a third no-solder ball area, respectively.

In the semiconductor package1B according to one or more embodiments, a floating structure may be provided in a non-connection terminal area. As one or more embodiments, a first floating structure161may be provided in the first non-connection terminal area NB1. A second floating structure162may be provided in the second non-connection terminal area NB2. A floating structure may not be provided in the third non-connection terminal area NB3. In one or more examples, the first floating structure161to the ninth floating structure169(FIG.8) may be collectively referred to as a floating structure160. In addition, in one or more examples, the first passive element150A to the third passive element150C may be collectively referred to as the passive element150.

The first floating structure161may be between the first passive element150A and the adjacent external connection terminal140. The first passive element150A may have a shape extending in a first horizontal direction (X-axis direction). The second passive element150B may have a shape extending in the first horizontal direction (X-axis direction). The third passive element150C may have a shape extending in a second horizontal direction (Y-axis direction). For example, as illustrated inFIGS.1and5, an element having a shape extending in the X-axis direction refers to the element having a length in the X-axis direction that is longer than a length of the element in the Y-axis direction. Similarly, an element having a shape extending in the Y-axis direction refers to the having a length in the Y-axis direction that is longer than a length of the element in the X-axis direction.

As one or more embodiments, the first floating structure161may have a shape extending in a first horizontal direction (X-axis direction). In other words, the first floating structure161may have a shape extending in the first horizontal direction (X-axis direction) similarly to the first horizontal direction (X-axis direction), which is the direction in which the first passive element150A extends. In one or more examples, the longitudinal direction of a specific element refers to an extension direction of the specific element. For example, the longitudinal direction of the first passive element150ais a first horizontal direction (X-axis direction), the longitudinal direction of the first floating structure161is a first horizontal direction, and the longitudinal direction of the third passive element150C is the second horizontal direction (Y-axis direction).

In one or more examples, the overlapping area OLA may refer to a boundary of a shape in which the internal semiconductor device200overlaps the lower surface of the first redistribution structure100in a vertical direction (Z-axis direction) perpendicular to a horizontal plane (X-Y plane). For example, in the semiconductor package1B, according to one or more embodiments, the overlapping area OLA may be formed in a rectangular shape on the lower surface of the first redistribution structure100. As one or more embodiments, the first floating structure161and the second floating structure162may be provided on the lower surface of the first redistribution structure100in the overlapping area OLA.

A third underfill layer620may be between the first redistribution structure100and the external substrate600. The third underfill layer620may be formed by, for example, a capillary underfill process and made of an epoxy resin. The first passive element150A, the second passive element150B, the third passive element150C, the plurality of external connection terminals140, the first floating structure161, and the second floating structure162may be surrounded by a third underfill layer620.

In some embodiments, the floating structure may be insulated. For example, the first floating structure161and the second floating structure162may be insulated. In addition, the floating structure may be made of a material including a polymer or silicon. For example, the first floating structure161and the second floating structure162may be made of a material including polymer or silicon. Insulation and constituent materials may be applied to all floating structures In one or more examples, not just the first floating structure161and the second floating structure162. Therefore, the description already given for this is omitted below.

The first floating structure161may be disposed parallel to the first passive element150A. In one or more examples, two components that are parallel to each other may refer to the longitudinal directions of each component being parallel to each other. In addition, the second floating structure162may be disposed parallel to the second passive element150B.

The first horizontal length of the first floating structure161may be substantially the same as the first horizontal length of the first passive element150A. On the other hand, the first horizontal length of the second floating structure162may be longer than the first horizontal length of the second passive element150B.

As one or more embodiments, the first floating structure161may be provided between the first passive element150A and the external connection terminal141, and the second floating structure162may be provided between the second passive element150B and the external connection terminal141. At the same time, the first floating structure161and the second floating structure162may be disposed between the first passive element150A and the second passive element150B.

As one or more embodiments, as shown inFIG.1, the first passive element150A and the first floating structure161may be parallel in the first horizontal direction (X-axis direction). At the same time, the second floating structure162may be parallel to the first floating structure161in the first horizontal direction (X-axis direction).

In one or more examples, similar to the third non-connection terminal area NB3, even if the third passive element150C is disposed, a floating structure may not be provided in the third non-connection terminal area NB3when another passive element is not disposed adjacent thereto. In one or more examples, the first and second non-connection terminal areas NB1and NB2, the floating structure may not be disposed in the third non-connection terminal area NB3having a relatively small horizontal area. For example, a person skilled in the art may decide whether or not to place a floating structure as needed.

As illustrated inFIG.4, the floating structure160may be attached to the lower surface of the first redistribution structure100through an adhesive layer. In one or more embodiments, the first floating structure161may be positioned on the lower surface of the first redistribution structure100by an adhesive layer161A. After the first passive element150A is mounted on the lower surface of the first redistribution structure100or before the first passive element150A is mounted on the lower surface of the first redistribution structure100, the first floating structure161may be disposed on a lower surface of the first redistribution structure100.

As shown inFIG.5, in the semiconductor package1C according to one or more embodiments, the floating structure160may be attached to the lower surface of the first redistribution structure100through connection terminals such as solder balls. As one or more embodiments, the first floating structure163may be positioned on the lower surface of the first redistribution structure100through a floating connection terminal163B. The floating connection terminal163B may be a solder ball. Alternatively, the first floating structure163may be disposed by bonding to the dummy pad163A provided in the process of forming the first redistribution structure100through the floating connection terminal163B. In this case, the first floating structure163may be disposed together in the process of mounting the first passive element150A.

Referring toFIGS.4and5, a vertical level difference between the lower surface of the first redistribution structure100and the external substrate600may be referred to as a first height H1, a vertical level difference between the lower surface of the first passive element150A and the lower surface of the first redistribution structure100may be referred to as a second height H2, and a vertical level difference between the lower surface of the first floating structure161and the lower surface of the first redistribution structure100may be referred to as a third height H3.

The first height H1is the distance between the lower surface of the first redistribution structure100and the upper surface of the external substrate600, and is equal to the thickness of the third underfill layer620between the first redistribution structure100and the external substrate600in the vertical direction.

The second height H2may be less than the first height H1. The third height H3may be less than the first height H1. The third height H3may be less than, equal to, or larger than the second height H2. The third height H3may be greater than the second height H2and less than the first height H1. Due to the range of the third height H3, the distance between the lower surface of the first redistribution structure100and the external substrate600is short, preventing excessive proximity. By limiting the distance between the lower surface of the first redistribution structure100and the external substrate600to a predetermined distance or more, the third underfill layer620may be more smoothly interposed between the lower surface of the first redistribution structure100and the external substrate600. Such a height range may be applied not only to the first floating structure161but also to other floating structures.

Referring toFIGS.4and5, the first passive element150A and the first floating structure161may be spaced apart from each other by a first distance D1. The first distance D1may be about 50 μm or more. A separation distance between the first passive element150A and the first floating structure161may be greater than or equal to the first distance D1so that the third underfill layer620is smoothly interposed between the first passive element150A and the first floating structure161.

In some embodiments, in a semiconductor package including a passive element and an external connection terminal140disposed around the passive element, and the third underfill layer620surrounding the passive element and the external connection terminal140, the passive element may be horizontally spaced apart from the external connection terminal140with the third underfill layer620therebetween. When the passive element is disposed in the overlapping area OLA, heat generated from the internal semiconductor device200may be transferred to the third underfill layer620through the first redistribution structure100. In the area of the non-connection terminal provided with the passive element, the volume of the material constituting the underfill layer is relatively greater than the area where the connection terminal is provided. In one or more examples, the underfill layer may have a greater coefficient of thermal expansion (CTE) than CTE of the substrate and the redistribution structure located nearby. Due to this, when the temperature of the semiconductor package is generally raised due to heat generation of the semiconductor chip, the underfill layer may experience greater thermal expansion than the surrounding structure. Due to the relatively great thermal expansion of the underfill layer, defects such as cracks may occur in the external connection terminal140electrically connecting the redistribution structure to the external substrate, and thus the reliability of the semiconductor package may deteriorate.

In the semiconductor package1B according to the embodiment, a floating structure made of a material including may be between the first redistribution structure100and the external substrate600, where the silicon or the polymer has a relatively less coefficient of thermal expansion than epoxy mold compound (EMC), which is a material constituting the underfill layer.

By disposing a floating structure having a less coefficient of thermal expansion than the material constituting the underfill layer between the first redistribution structure100and the external substrate600, when the overall temperature of the semiconductor package rises due to heat generation of the semiconductor chip, thermal expansion generated in the underfill layer may be reduced compared to a case where the floating structure is not present. In addition, because the floating structure is provided in the non-connection terminal area, the volume of the third underfill layer620in the non-connection terminal area may be reduced. For example, even if the temperature of the semiconductor package is increased, thermal expansion of the underfill is reduced, thereby advantageously preventing or reducing defects that may occur in the external connection terminal140covered by the underfill. Accordingly, reliability of the semiconductor package1B may be improved through the semiconductor package1B according to one or more embodiments.

As shown inFIG.1, the first non-connection terminal area NB1including the first passive element and the second non-connection terminal area NB2including the second passive element may be positioned with the external connection terminal140therebetween. The volume of the underfill in the first non-connection terminal area NB1and the second non-connection terminal area NB2is greater than that of the area where the connection terminals are disposed. In addition, because the first non-connection terminal area NB1and the second non-connection terminal area NB2are located in the overlapping area OLA, the temperature of the underfill in the first and second non-connection terminal areas NB1and NB2may be more easily raised. Therefore, the external connection terminal140provided between the first non-connection terminal area NB1and the second non-connection terminal area NB2may have a defect such as a crack of the external connection terminal140provided between the first non-connection terminal area NB1and the second non-connection terminal area NB2due to thermal expansion of the underfill on both sides.

As shown inFIG.3, in the semiconductor package1B according to the embodiment, the first floating structure161may be provided between the first passive element150A and the external connection terminal141, and the second floating structure162may be provided between the second passive element150B and the external connection terminal141, so as to prevent or reduce defects in the external connection terminal140provided between the first second and second non-connection terminal area NB1and NB2. The first floating structure161and the second floating structure162may be disposed between the first passive element150A and the second passive element150B. Based on this configuration, thermal expansion due to temperature rise occurring in the first and second non-connection terminal areas NB1and NB2may be reduced.

Accordingly, through the semiconductor package1B according to one or more embodiments, reliability of the semiconductor package1B may be improved by preventing or reducing defects that may occur in the external connection terminal140provided between the first and second non-connection terminal areas NB1and NB2.

FIG.6is a plan view illustrating a semiconductor package1D according to one or more embodiments.

Referring toFIG.6, on one side of the passive element150, a floating structure may be located spaced apart from the passive element150, and the floating structure may be spaced apart from the passive element150on the other side opposite to the place where the floating structure is disposed. For example, the passive element150may be provided between the two floating structures. For example, as shown inFIG.6, a fourth floating structure164may include a left fourth floating structure164L and a right fourth floating structure164R. The right fourth floating structure164R closer to the center of the lower surface of the first redistribution structure100may be referred to as an inner fourth floating structure. In addition, the right fourth floating structure164R closer to the center of the lower surface of the structure100may be referred to as an inner fourth floating structure.

In one or more examples, a fifth floating structure165may include a left fifth floating structure165L and a right fifth floating structure165R. In the fifth floating structure165, a right fifth floating structure165R located farther from the center of the lower surface of the first redistribution structure100may be referred to as an outer fifth floating structure. In addition, a left fifth floating structure165L closer to the center of the lower surface of the first redistribution structure100may be referred to as an inner fifth floating structure. This naming method may also be applied to a seventh floating structure167to a ninth floating structure169to be described below, and the description already given thereto is omitted.

As shown inFIG.6, on the lower surface of the first redistribution structure100, the right fourth floating structure164R disposed between the first passive element150A and the second passive element150B may have a greater width in the second horizontal direction (Y-axis direction) than the left fourth floating structure164L. Similarly, the left fifth floating structure165L disposed between the first passive element150A and the second passive element150B may have a greater width in the second horizontal direction (Y-axis direction) than the right fifth floating structure164R.

In the semiconductor package1D, according to one or more embodiments, the floating structure disposed between the first passive element150A and the second passive element150B may have a greater volume than floating structures not disposed between the first passive element150A and the second passive element150B, so as to prevent or reduce defects in the external connection terminal140provided between the first non-connection terminal area NB1and the second non-connection terminal area NB2. Thermal expansion due to temperature rise generated in the underfill layer in the first and second non-connection terminal areas NB1and NB2may be reduced through the floating structure having a greater volume.

Accordingly, through the semiconductor package1D, according to one or more embodiments, reliability of the semiconductor package ID may be improved by preventing or reducing defects that may occur in the external connection terminal140provided between the first and second non-connection terminal areas NB1and NB2.

FIG.7is a plan view illustrating a semiconductor package1E according to one or more embodiments.

Referring toFIG.7, a floating structure surrounding the periphery of a passive element150may be provided. For example, as inFIG.7, a sixth floating structure166surrounding a first passive element150A may be provided on the lower surface of a first redistribution structure100. On the X-Y plane, which is the lower surface of the first redistribution structure100, the sixth floating structure166may have a frame-like shape in which the first passive element150A is disposed in the center so that the floating structure may be positioned between external connection terminals140disposed around the first passive element150A.

The sixth floating structure166in the semiconductor package1E, according to one or more embodiments, may significantly and advantageously reduce the volume of an underfill layer interposed in the first non-connection terminal area NB1. Accordingly, reliability of the semiconductor package1E may be improved by preventing or reducing defects that may occur in the external connection terminal140through the semiconductor package1E according to one or more embodiments.

In one or more examples, for a seventh floating structure167including a left seventh floating structure167L and a right seventh floating structure167R, the length of the left seventh floating structure167L may be different from that of the right seventh floating structure167R.

FIG.8is a plan view illustrating a semiconductor package1F according to one or more embodiments.

Referring toFIG.8, like the sixth floating structure166having the frame-like shape described above around the passive element150, a floating structure surrounding the passive element150and divided into two may be provided. For example, as shown inFIG.8, an ‘L-shaped’ floating structure may be symmetrically disposed around the first passive element150A, and an eighth floating structure158may be provided to surround the circumference of the first passive element150A.

In one or more examples, the first, second, third, fourth, and seventh floating structures161,162,163,164, and167, respectively, the floating structure may be disposed in an orientation that is not parallel to the passive element150. For example, as shown in FIG.8, a ninth floating structure169including a front ninth floating structure169F and a rear ninth floating structure169B may be disposed in an orientation that is not parallel to the second passive element150B. A longitudinal direction of the second passive element150B may be the first horizontal direction (X-axis direction), and a longitudinal direction of the ninth floating structure169disposed in the second non-connection terminal area NB2where the second passive element150B is located may be a second horizontal direction (Y-axis direction).

FIG.9is a cross-sectional view illustrating a semiconductor package1G according to one or more embodiments The description already given of the embodiments of the present disclosure may be omitted.

Referring toFIG.9, the semiconductor package1G according to the embodiment may be a panel level package (PLP). In more detail, the semiconductor package1G according to one or more embodiments may be a fan-out panel level package (FOPLP).

A substrate base350may be positioned on a portion of the upper surface of a first redistribution structure100. The substrate base350may be formed of an insulating material. For example, the substrate base350may include at least one material selected from flame retardant 4 (FR-4), tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimide triazine (BT), thermount, cyanate ester, phenolic resin, epoxy resin, polyimide, and liquid crystal polymer.

In one or more examples, a conductive connection structure340extending through the substrate base350from the lower surface to the upper surface of the substrate base350may be included. The conductive connection structure340may be electrically connected to a lower redistribution pattern120of the lower redistribution structure100. The conductive connection structure340may be electrically connected to a chip pad223of the internal semiconductor device200and/or an external connection terminal290through the lower redistribution pattern120. The conductive connection structure340may include a plurality of conductive layers341extending in a horizontal direction (e.g., an X direction and/or a Y direction) and a plurality of conductive via patterns343extending in a vertical direction (e.g., a Z direction). The conductive connection structure340may be made of copper, nickel, stainless steel, or beryllium copper.

The plurality of conductive layers341may be arranged spaced apart from each other at different vertical levels within the substrate base350. The plurality of conductive layers341may extend on at least one of upper and lower surfaces of each of the plurality of layers constituting the substrate base350. The plurality of conductive via patterns343may pass through at least a portion of the substrate base350and extend in a vertical direction (e.g., a Z direction), and may electrically connect the plurality of conductive layers341positioned at different vertical levels.

The semiconductor package1G may include the second redistribution structure400disposed on the encapsulant320. Among the descriptions of the second redistribution structure400, a description already given in the first redistribution structure100may be omitted. A plurality of upper redistribution via patterns360extend downward from the upper surface and may extend through the encapsulant320. In some embodiments, each of the plurality of upper redistribution via patterns360may have a tapered shape in which a horizontal width narrows and extends in a direction from an upper side to a lower side thereof. At least one of the plurality of upper redistribution via patterns360may be connected to the conductive connection structure340. The upper redistribution pattern243may be electrically connected to the lower redistribution pattern120through the conductive connection structure340.

FIG.10is a cross-sectional view illustrating a semiconductor package1H according to one or more embodiments. The description already given of the embodiments of the present disclosure may be omitted.

The semiconductor package1H according to one or more embodiments may include a printed circuit board as a first package substrate100A. The first package substrate100A may include insulating layers170, a top passivation layer191, and a bottom passivation layer192, and a wiring structure180. A case in which the first package substrate100A of the semiconductor package1H according to the embodiment has a multilayer structure including insulating layers170is described as an example. However, the embodiments are not limited to this configuration, and the first package substrate100A may have a single-layer structure. The wiring structure180may include wiring patterns181and connection vias182. The first package substrate100A may be a support substrate for manufacturing a semiconductor package by mounting a semiconductor chip thereon. Lower surface pad patterns180B may be disposed on the first package substrate100A.

The insulating layers170may include a plurality of insulating layers stacked in a vertical direction Z, for example, three insulating layers including a first insulating layer, a second insulating layer, and a third insulating layer. The insulating layers170may cover the wiring patterns181and the connection vias182. The insulating layers170may include an insulating resin. The insulating resin may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with inorganic fillers or/and glass fiber (glass cloth or glass fabric) in these resins, for example, prepreg, ajinomoto build-up film (ABF), FR-4, and bismaleimide triazine (BT). The insulating layers170may include a photosensitive resin, such as photoimageable dielectric (PID) resin. In this case, the insulating layers170may be formed thinner, and the wiring patterns181and the connection vias182may be formed more minutely. Depending on the process, the boundary between the insulating layers170of different levels may be unclear.

The top passivation layer191and the bottom passivation layer192may be provided as layers to protect the semiconductor package from external physical or chemical damage. The top passivation layer191and the bottom passivation layer192may protect the first package substrate100A. The bottom passivation layer192may be disposed to cover, for example, bottom surface of lowermost layer of the plurality of insulating layers170in a lower region of the first package substrate100A. The top passivation layer191may be disposed to cover the top surface of the uppermost layer of the plurality of insulating layers170. The top passivation layer191and the bottom passivation layer192may include an insulating resin and an inorganic filler, but may not include glass fibers. For example, the top passivation layer191and the bottom passivation layer192may include ABF, but are not limited thereto, and may include a photosensitive insulating material (PID) or insulating polymer, for example, photosensitive polyimide (PSPI).

An opening may be formed in a portion of the bottom passivation layer192to expose at least a portion of the lower surface pad patterns180B, respectively. A plurality of external connection terminals140such as solder balls may be respectively connected to the lower surface pad patterns180B exposed through the opening. The lower surface pad patterns180B may include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or a metal material including an alloy thereof. Similar to the lower surface pad patterns180B, an opening may be formed in a portion of the top passivation layer191to expose at least a portion of an upper surface pad patterns180U.

While the embodiments of the present disclosure have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.