SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

A semiconductor structure includes a circuit substrate, at least one semiconductor package, at least one semiconductor device, and a ring structure. The at least one semiconductor package is disposed on the circuit substrate, and the semiconductor package includes a plurality of integrated circuit structures. The at least one semiconductor device, disposed on the circuit substrate and aside the semiconductor package. The ring structure is disposed on the circuit board. The ring structure includes at least one opening pattern corresponding to the semiconductor device.

BACKGROUND

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components, such as transistors, diodes, resistors, capacitors, etc. For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of integrated circuit structures has emerged.

DETAILED DESCRIPTION

The disclosure relates to a semiconductor device and its forming method. In some embodiments, a semiconductor device includes semiconductor package(s) and semiconductor device(s) around the semiconductor package(s), which are laterally disposed and electrically connected to a circuit substrate. In some embodiments, a ring structure is disposed on the circuit substrate to encircle the semiconductor device(s). The ring structure of the disclosure has an overhang portion across the semiconductor device(s), and the overhang portion has opening pattern(s) corresponding to the underlying semiconductor device(s). In some embodiments, by including such ring structure with opening pattern(s), the warpage of the 3DIC semiconductor structure may be effectively controlled without contacting the underlying semiconductor device(s), thus enhancing yield and reliability of the semiconductor device.

FIG.1toFIG.4are cross-sectional views of a method of forming a semiconductor structure in accordance with some embodiments. It is understood that the disclosure is not limited by the method described below. Additional operations can be provided before, during, and/or after the method and some of the operations described below can be replaced or eliminated, for additional embodiments of the methods.

Referring toFIG.1, a circuit substrate100is provided. In some embodiments, the circuit substrate100includes a core layer and two build-up layers on opposite sides of the core layer. In some embodiments, the core layer includes prepreg, polyimide, photo image dielectric (PID), Ajinomoto buildup film (ABF), the like, or a combination thereof. However, the disclosure is not limited thereto, and other dielectric materials may also be used. In some embodiments, each of build-up layer includes dielectric layers, such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), prepreg, Ajinomoto buildup film (ABF), silicon nitride, silicon oxide, the like, or a combination thereof. The material of the core layer may be different from the material of the build-up layers. In some embodiments, the circuit substrate100includes wiring patterns102that penetrate through the core layer and the build-up layers for providing electrical routing between different components. The wiring patterns102include lines, vias, pads and/or connectors. The wiring patterns102include Cu, Al, Ti, Ta, W, Ru, Co, Ni, the like, or a combination thereof. In some embodiments, the circuit substrate100has first pads104,105at a first side S1and second pads106at a second side S2opposite to the first side S1. The first pads104,105and the second pads106are configured to connect to bumps and/or components. In some embodiments, first and second mask layers are formed on the first side S1and the second side S2, respectively. The first and second mask layers may include materials having a chemical composition of silica, barium sulfate and epoxy resin, and/or the like. The first and second mask layers may cover portions of the first and second pads104,105and106while expose portions of the first and second pads104,105and106for bumps and/or components. In some embodiments, the first pads104,105of the circuit substrate100at the first side S1are electrically connected at least one semiconductor package and/or semiconductor device, and the second pads106of the circuit substrate100at the second side S2are electrically connected to bumps108. The bumps108are referred to as “ball grid array (BGA) balls” in some examples. The circuit substrate100is referred to as a “board substrate” or “printed circuit board (PCB)” in some examples. In other embodiments, the core layer of circuit substrate100may be omitted as needed, and such circuit substrate100is referred to as a “coreless circuit substrate”.

Referring toFIG.2, at least one semiconductor package200is provided and bonded to the first side S1of the circuit substrate100. In some embodiments, the semiconductor package200includes an interposer201and multiple integrated circuit structures TD11, TD12and TD3disposed on the interposer201. In some embodiments, the semiconductor package200is referred to as a “chip-on-wafer (CoW) module” in some embodiments.

The interposer201is configured to provide electrical connection between components. In some embodiments, the interposer201is a silicon-free substrate including wring layers202embedded by polymer layers. The wring layers202include metal lines and/or metal vias. In some embodiments, each wring layer202includes Cu, Al, Ti, Ta, W, Ru, Co, Ni, the like, or a combination thereof. In some embodiments, a seed layer and/or a barrier layer may be disposed between each wiring layer202and the adjacent polymer layer. The seed layer may include Ti/Cu. The barrier layer may include Ta, TaN, Ti, TiN, CoW or a combination thereof. In some embodiments, each polymer layer includes an organic material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), the like, or a combination thereof. The interposer201may be referred to an “organic interposer” in some examples. The polymer layers of the interposer201may be replaced by dielectric layers or insulating layers as needed. In some embodiments, the interposer201is a silicon-containing substrate, and further includes through silicon vias penetrating through the silicon substrate and electrically connected to the wring layers202.

In some embodiments, the interposer substrate201is a passive interposer, which is used to convey a lack of a functional device or integrated circuit device. Such passive interposer is referred to as a “device-free interposer” in some examples.

In other embodiments, the interposer substrate201is an active interposer that contains at least one functional device or integrated circuit device embedded in the polymer layers and electrically connected to the wiring layers202. Such active interposer is referred to as a “device-containing interposer” in some examples.

In some embodiments, the interposer201has a first side S3and a second side S4opposite to the first side S3. In some embodiments, the interposer201is bonded to the first pads104of the circuit substrate100through bumps204at the second side S4thereof. The bumps204are referred to as “controlled collapse chip connection (C4) bumps” in some examples.

The integrated circuit structures TD11, TD12and TD13are arranged side by side, disposed over and bonded to the first side S3of the interposer201. In some embodiments, the integrated circuit structures TD11and TD13are periphery integrated circuit structures around the central integrated circuit structures TD12. In some embodiments, the integrated circuit structures TD11, TD12and TD13are electrically connected to the interposer201through bumps B11, B12and B13, respectively. The bumps B11, B12and B13are referred to as “micro bumps” in some examples.

Each of the integrated circuit structures TD11, TD12and TD13may be a single die or a die stack including multiple dies. The adjacent dies in the die stack may be vertically stacked through a solder joint or a hybrid bonding including a metal-to-metal bonding and a dielectric-to-dielectric bonding. In some embodiments, each of the integrated circuit structures TD11, TD12and TD13includes an integrated active device, such as a logic device, a memory device, a MOSFET device, a CMOS device, a BJT device, a system on chip (SoC), the like, or a combination thereof. In some embodiments, at least one of the integrated circuit structures TD11, TD12and TD13may be a dummy chip. Herein, a dummy die indicates a non-operating die, a die configured for non-use, a die without devices therein or a die configured to electrically couple together two other components, strengthen the package structure, and/or improve the heat dissipation.

In some embodiments, the integrated circuit structures TD11, TD12and TD13may have the same or different sizes and/or functions upon the design requirements. The semiconductor package200is referred to as a “homogeneous package” when the integrated circuit structures TD11, TD12and TD13have the same function. The semiconductor package200is referred to as a “heterogeneous package” when the integrated circuit structures TD11, TD12and TD13have different functions.

In some embodiments, the semiconductor package200further includes an underfill layer UF1between the integrated circuit structures TD11, TD12, TD13and the interposer201and around the bumps B11, bumps B12and B13, and an underfill layer UF2between the interposer201and the circuit substrate100around the bumps204. In some embodiments, the semiconductor package200further includes an encapsulation layer E over the interposer201and around the integrated circuit structures TD11, TD12and TD13. In some embodiments, the top surface of the encapsulation layer E is flushed with the top surfaces of the integrated circuit structures TD11, TD12and TD13.

Referring toFIG.3, multiple semiconductor devices300are formed aside the semiconductor package200. In some embodiments, the semiconductor device300includes an integrated passive device, such as a resistor, a capacitor, an inductor, a resonator, a regulator, a filter, the like, or a combination thereof. In some embodiments, the semiconductor device300includes an integrated active device, such as a logic device, a memory device, a MOSFET device, a CMOS device, a BJT device, a system on chip (SoC), the like, or a combination thereof. In some embodiments, the semiconductor device300is referred to as an “integrated circuit chiplet” or “surface mount device (SMD)” in some embodiments. In some embodiments, the semiconductor device300is bonded to the first pads105of the circuit substrate100through bumps302. The bumps302are referred to as “controlled collapse chip connection (C4) bumps” in some examples. An underfill layer UF3may be formed between the semiconductor device300and the circuit substrate100around the bumps302.

The height H2of the semiconductor device300is higher than the height H1of the semiconductor package200, counting from the first surface S1of the circuit substrate100. From another point of view, the top surface of the semiconductor device300is higher than the top surfaces of the integrated circuit structures TD11, TD12and TD13by a non-zero distance.

Referring toFIG.4, a ring structure400is bonded to the circuit substrate100through an adhesive layer AL. In some embodiments, the ring structure400has an annular shape (e.g., square-ring shape) encircling the semiconductor device300. The ring structure400may be placed on the circuit substrate100in correspondence of the adhesive layer AL, and bonded to the circuit substrate100by curing (or pre-curing) the adhesive layer AL, for example. In some embodiments, the ring structure400includes any suitable material, such as metal, metallic alloy, or the like. For example, the ring structure400may include stainless steel, copper tungsten, aluminum, the like, or a combination thereof.

In some embodiments, the ring structure400includes a main portion MP (or called “base portion” in some examples) contacting the adhesive layer AL and an extending portion EP (or called “overhang portion” in some examples) protruding from the main portion MP towards the semiconductor device300. Specifically, the extending portion EP of the ring structure400may have an inverted-U shape, with at least one opening pattern OP corresponding to the underlying semiconductor device300on the circuit substrate100. In some embodiments, each opening pattern OP has substantially vertical sidewalls. However, the disclosure is not limited thereto. In other embodiments, each opening pattern OP may be a narrow-top and wide-bottom opening having inclined sidewalls. For example, each opening pattern OP may have a trapezoidal shape in a cross-sectional view. The main portion MP and the extending portion EP may be integrally formed as a single piece. In some embodiments, the opening patterns OP of the extending portion EP of the ring structure400are patterned by a laser drilling process. In other embodiments, the opening patterns OP of the extending portion EP of the ring structure400are patterned by an etching process. Since the height H2of the semiconductor device300is higher than the height H1of the semiconductor package200, the conventional ring structure may contact the underlying components when package warpage occurs. However, in the disclosure, by including a ring structure with opening patterns, the warpage of the 3DIC semiconductor structure may be effectively controlled without contacting the underlying semiconductor devices, thus enhancing yield and reliability of the semiconductor device. Upon the formation of the ring structure, a semiconductor structure10of the disclosure is thus completed.

FIG.5is a simplified top view of a semiconductor structure in accordance with some embodiments, in which few elements such as semiconductor packages and integrated circuit structures, and ring structure are shown for simplicity and clarity of illustration. In some embodiments,FIG.4is the cross-sectional view taken along the line I-I′ ofFIG.5.

As shown inFIG.5, from a top view, multiple semiconductor packages200and multiple semiconductor devices300are disposed on a circuit board, and the semiconductor devices300are disposed around the semiconductor packages200. In some embodiments, the semiconductor devices300are disposed at opposite sides of the semiconductor packages200. However, the disclosure is not limited thereto. In other embodiments, the semiconductor devices300are disposed at four sides of the semiconductor packages200. The ring structure400has multiple openings OP for providing spaces for the underlying semiconductor devices300, so as to prevent undesired contact and damage between the semiconductor devices300and the ring structure400.

More specifically, as shown inFIG.4, each opening pattern OP is defined by three parts EP1, EP2and EP3of the extending portion EP of the ring structure400. The part EP1is disposed between and in contact with the parts EP2and EP3, and the part EP2is connected to the main portion MP. In some embodiments, the thickness TH1of the part EP1is thinner than the thickness TH2of the part EP2or the thickness TH3of the part EP3. In some embodiments, the thickness TH2of the part EP2is substantially the same as the thickness TH3of the part EP3, as shown inFIG.4. Specifically, the extension part EP of the ring structure400inFIG.4have two different thicknesses. However, the disclosure is not limited thereto. In other embodiments, the thickness TH2of the part EP2may be different from the thickness TH3of the part EP3.

In the extending portion EP of the ring structure400, the thinner part EP1is configured to provide enough space for the underlying semiconductor device300, while thicker parts EP2and EP1are configured to strength the package structure and prevent package warpage. In some embodiments, the thickness of the main portion MP of the ring is between about 0.5 mm and 10 mm, the ratio of the thickness TH2(or TH3) to the thickness TH1is between about 0.5 and 1.0, and the ratio of the thickness TH1to the thickness TH2(or TH3) is between about 0.7 and 1.0. Other ratios may be possible, as long as the ring structure400is separated from the underlying semiconductor device300or the adjacent semiconductor package by a non-zero distance.

For example, the distance W0from the part EP3of the ring structure400to the semiconductor package200is between about 1 mm and 5 mm. That is, the ring structure400is separated from the semiconductor package200by a distance W0(e.g., 1-5 mm). For example, the distance W1from the semiconductor device300to the semiconductor package is between 3 mm and 10 mm. For example, the distance W2from the part EP2of the ring structure400to the semiconductor device300is greater than about 0.1 mm, the distance W3from the part EP3of the ring structure400to the semiconductor device300is greater than about 0.1 mm. For example, the distance W4from the main portion MP of the ring structure400to the semiconductor device300is greater than about 1 mm. Other distances may be possible, as long as the ring structure400is laterally or vertically separated from the underlying semiconductor device300or the adjacent semiconductor package200by a non-zero distance.

For example, the gap distance G1from the part EP1of the ring structure400to the semiconductor device300is greater than about 200 μm. For example, the gap distance G2from the part EP2of the ring structure400to the semiconductor device300is between 0 μm and 200 μm. For example, the gap distance G3from the part EP3of the ring structure400to the semiconductor package300is greater than 200 μm. Other gap distances may be possible, as long as the ring structure400is separated from the underlying semiconductor device300or the adjacent semiconductor package by a non-zero distance.

Besides, as shown inFIG.4, the width OPW of the opening pattern OP of the ring structure400is greater than the width SDW of the underlying semiconductor device300by a non-zero distance, such as greater than about 0.2 mm or more. From a top view, the ring structure400of the disclosure is separated from or non-overlapped with the semiconductor package200, as shown inFIG.5.

FIG.6is a cross-sectional view of a semiconductor structure in accordance with some embodiments. The semiconductor structure11ofFIG.6is similar to the semiconductor structure10ofFIG.4, so the difference is described below, and the similarity is not iterated herein.

One difference between the semiconductor structure11and the semiconductor structure10lies in that, in the semiconductor structure11, a buffer layer402is further attached to the ring structure400so as to provide more protection for the underlying semiconductor device300. Specifically, after forming opening patterns OP in the extension portion EP of the ring structure400and before mounting the ring structure400on the circuit substrate100, a buffer layer402is formed on the bottom surface BS of the extension portion EP. In some embodiments, the buffer layer402includes a dielectric material, a soft material or an elastic material, such as rubber, polymer (e.g., epoxy) or tape (e.g., die attach film), or the like. The hardness of the buffer layer402is less than the hardness of the ring structure. In some embodiments, the thickness of the buffer layer402ranges from about 10 μm to 60 μm. In some embodiments, the buffer layer402is formed on a portion of the bottom surface BS of the extension portion EP (i.e., the bottom surface of the part EP1), as shown inFIG.6. However, the disclosure is not limited thereto. In other embodiments, the buffer layer402may be formed on the entire bottom surface BS of the extension portion EP. Another difference between the semiconductor structure11and the semiconductor structure10lies in that, in the semiconductor structure11, the thickness TH3of the part EP3is different from (e.g., greater than) the thickness TH2of the part EP2. Specifically, the extension part EP of the ring structure400inFIG.6have three different thicknesses.

FIG.7is a cross-sectional view of a semiconductor structure in accordance with some embodiments.FIG.8is a simplified top view of a semiconductor structure in accordance with some embodiments. In some embodiments,FIG.7is the cross-sectional view taken along the line I-I′ ofFIG.8.

The semiconductor structure12ofFIG.7is similar to the semiconductor structure10ofFIG.4, so the difference is described below, and the similarity is not iterated herein. One difference between the semiconductor structure12and the semiconductor structure10lies in that, in the semiconductor structure12, a buffer layer402is further attached to the ring structure400so as to provide more protection for the underlying semiconductor device300. In some embodiments, the buffer layer402is formed not only on the entire bottom surface BS of the extension portion EP but also on the sidewall of the main portion MP, as shown inFIG.7. In some embodiments, the sidewall of the buffer layer402may be protruded from the sidewall of the adhesion layer AL, as shown inFIG.7. In other embodiments, the sidewall of the buffer layer402may be flushed with the sidewall of the adhesion layer AL. Another difference between the semiconductor structure12and the semiconductor structure10lies in that, in the semiconductor structure12, the extension part EP of the ring structure400laterally extends across not only the semiconductor device300but also a portion of the semiconductor package200. Specifically, from a top view, the ring structure400is partially overlapped with the semiconductor package200, as shown inFIG.8.

FIG.9is a cross-sectional view of a semiconductor structure in accordance with some embodiments.FIG.10is a simplified top view of a semiconductor structure in accordance with some embodiments. In some embodiments,FIG.9is the cross-sectional view taken along the line I-I′ ofFIG.10.

The semiconductor structure13ofFIG.9is similar to the semiconductor structure10ofFIG.4, so the difference is described below, and the similarity is not iterated herein. One difference between the semiconductor structure13and the semiconductor structure10lies in that, in the semiconductor structure13, the thickness of the part EP1of the extension portion EP is continuously varied from one end adjacent to the part EP2to another end adjacent to the part EP3. Specifically, in the semiconductor structure13, each opening pattern OP of the ring structure400has a dome shape in a cross-sectional view (as shown inFIG.9), and has a circular shape in a top view (as shown inFIG.10). In some embodiments, from a top view, the ring structure400of the semiconductor structure13is separated from the semiconductor package200, as shown inFIG.10. However, the disclosure is not limited thereto. In some embodiments, from a top view, the ring structure400of the semiconductor structure13may be partially overlapped with the semiconductor package200.

FIG.11is a cross-sectional view of a semiconductor structure in accordance with some embodiments. The semiconductor structure14ofFIG.11is similar to the semiconductor structure13ofFIG.9, so the difference is described below, and the similarity is not iterated herein. The difference between the semiconductor structure14and the semiconductor structure13lies in that, in the semiconductor structure14, a buffer layer402is further attached to the ring structure400so as to provide more protection for the underlying semiconductor device300. Specifically, after forming opening patterns OP in the extension portion EP of the ring structure400and before mounting the ring structure400on the circuit substrate, a buffer layer402is formed on the bottom surface BS of the extension portion EP. In some embodiments, the buffer layer402includes a dielectric material, a soft material or an elastic material, such as rubber, polymer (e.g., epoxy) or tape (e.g., die attach film), or the like. The hardness of the buffer layer402is less than the hardness of the ring structure. In some embodiments, the thickness of the buffer layer402ranges from about 10 μm to 60 μm. In some embodiments, the buffer layer402may be formed not only on the entire bottom surface BS of the extension portion EP but also on the sidewall of the main portion MP, as shown inFIG.11.

FIG.12is a cross-sectional view of a semiconductor structure in accordance with some embodiments.FIG.13is a simplified top view of a semiconductor structure in accordance with some embodiments. In some embodiments,FIG.13is the cross-sectional view taken along the line I-I′ ofFIG.12.

The semiconductor structure15ofFIG.12is similar to the semiconductor structure10ofFIG.4, so the difference is described below, and the similarity is not iterated herein. One difference between the semiconductor structure15and the semiconductor structure10lies in that, in the semiconductor structure15, each opening pattern OP corresponds to multiple semiconductor devices (e.g., semiconductor devices300and301). The number of the semiconductor devices is not limited by the present disclosure. For example, each opening pattern OP may correspond to two or more semiconductor devices.

In some embodiments, each of the semiconductor devices300and301includes an integrated passive device, such as a resistor, a capacitor, an inductor, a resonator, a regulator, a filter, the like, or a combination thereof. In some embodiments, each of the semiconductor devices300and301includes an integrated active device, such as a logic device, a memory device, a MOSFET device, a CMOS device, a BJT device, a system on chip (SoC), the like, or a combination thereof. The semiconductor devices300and301may have the same or different functions, sizes, heights and/or widths. In some embodiments, the semiconductor device300is bonded to the first pads105of the circuit substrate100through bumps302, and the semiconductor device301is bonded to the first pads105of the circuit substrate100through bumps303. An underfill layer UF3may be formed between the circuit substrate100and each of the semiconductor devices300and301and around the bumps302and303.

In some embodiments, each of the height H2of the semiconductor device300and the height H3of the semiconductor device301is higher than the height H1of the semiconductor package200, counting from the first surface S1of the circuit substrate100. From another point of view, the top surfaces of the semiconductor devices300and301are higher than the top surfaces of the integrated circuit structures TD11, TD12and TD13by a non-zero distance. However, the disclosure is not limited thereto. In other embodiments, the height of at least one of multiple semiconductor devices may be higher than the height H1of the semiconductor package200, while the height of at least one of multiple semiconductor devices may be lower than the height H1of the semiconductor package200.

Another difference between the semiconductor structure15and the semiconductor structure10lies in that, in the semiconductor structure15, the extension part EP of the ring structure400laterally extends across not only the semiconductor devices300and301but also a portion of the semiconductor package200. Specifically, from a top view, the ring structure400is partially overlapped with the semiconductor package200, as shown inFIG.13.

The width OPW of the opening pattern OP of the ring structure is greater than the total width SDW of the underlying semiconductor devices300and301by a non-zero distance, such as greater than about 0.2 mm or more. Besides, the gap distance G11between the part EP1of the ring structure400to the semiconductor device300is greater than about 200 μm, and the gap distance G12between the part EP1of the ring structure400to the semiconductor device301is greater than about 200 μm.

FIG.14is a cross-sectional view of a semiconductor structure in accordance with some embodiments. The difference between the semiconductor structure16and the semiconductor structure15lies in that, in the semiconductor structure16, a buffer layer402is further attached to the ring structure400so as to provide more protection for the underlying semiconductor devices300and301. In some embodiments, the buffer layer402is formed not only on the entire bottom surface BS of the extension portion EP but also on the sidewall of the main portion MP, as shown inFIG.14.

FIG.15is a cross-sectional view of a semiconductor structure in accordance with some embodiments. The difference between the semiconductor structure17and the semiconductor structure14lies in that, in the semiconductor structure17, a part EP2is omitted from the extension part EP of the ring structure. As shown inFIG.15, each opening pattern OP is defined by the main portion MP, and parts EP1, EP3of the extending portion EP of the ring structure400. The part EP1is disposed between and in contact with the main portion MP and the part EP3. Specifically, the extension part EP of the ring structure400inFIG.15have two different thicknesses.

FIG.16is a cross-sectional view of a semiconductor structure in accordance with some embodiments. The difference between the semiconductor structure18and the semiconductor structure17lies in that, in the semiconductor structure18, a buffer layer402is further attached to the ring structure400so as to provide more protection for the underlying semiconductor devices300and301. In some embodiments, the buffer layer402is formed not only on the entire bottom surface BS of the extension portion EP but also on the sidewall of the main portion MP, as shown inFIG.16.

The semiconductor structures of the disclosure are illustrated below with reference toFIG.4toFIG.16.

According to some embodiments of the disclosure, a semiconductor structure10/11/12/13/14/15/16/17/18includes a circuit substrate100, at least one semiconductor package200, at least one semiconductor device300, and a ring structure400. The at least one semiconductor package200is disposed on the circuit substrate100, and the semiconductor package200includes a plurality of integrated circuit structures TD11, TD12and TD13. The integrated circuit structures TD11, TD12and TD13may be laterally arranged and/or vertically stacked upon the process requirements. The at least one semiconductor device300is disposed on the circuit substrate100and aside the semiconductor package200. The ring structure400is disposed on the circuit board100and surround multiple semiconductor device300. The ring structure400includes at least one opening pattern OP corresponding to the semiconductor device300.

In some embodiments, a top surface of the semiconductor device300is higher than a top surface of the semiconductor package200. In some embodiments, a width OPW of the opening pattern OP is greater than a width SDW of the semiconductor device300.

In some embodiments, the at least one semiconductor device15/16/17/18includes two semiconductor devices300and301, and each opening pattern OP corresponds to the two semiconductor devices300and301, as show inFIG.12toFIG.16.

In some embodiments, the semiconductor structure11/12/14/16/18further includes a buffer layer402disposed on a surface of the opening pattern OP. The buffer layer402may be attached to a portion of the bottom surface or an entire bottom surface of the extension part EP of the ring structure400. The buffer layer402may further continuously extend along the sidewall of the base portion MP of the ring structure400. In some embodiments, the buffer layer402is separated from the semiconductor device300and/or the semiconductor package200by a non-zero distance.

In some embodiments, from a top view or a cross-sectional view, the ring structure400is separated from the semiconductor package200by a non-zero distance, as shown inFIG.4.FIG.5,FIG.6,FIG.9,FIG.10andFIG.11.

In some embodiments, from a top view or a cross-sectional view, the ring structure400is partially overlapped with the semiconductor package200, as shown inFIG.7,FIG.8,FIG.12,FIG.13,FIG.14,FIG.15andFIG.16.

In some embodiments, the semiconductor package10/11/12/13/14/15/16/17/18further includes an interposer201disposed between the integrated circuit structures TD11, TD12, TD13and the circuit substrate100; and an encapsulation layer E disposed over the interposer201and encapsulating the integrated circuit structures TD11, TD12, TD13. In some embodiments, the interposer201is optional and may be omitted as needed.

According to some embodiments of the disclosure, a semiconductor structure10/11/12/13/14/15/16/17/18includes a circuit substrate100, a plurality of integrated circuit structures TD11, TD12, TD13, an encapsulating layer E, at least one semiconductor device300and a ring structure400. The integrated circuit structures TD11, TD12, TD13are laterally disposed on and electrically connected to the circuit substrate100. The encapsulating layer E encapsulates the integrated circuit structures TD11, TD12, TD13. The at least one semiconductor device300is disposed on the circuit substrate100and separated from the encapsulating layer E. The ring structure400is disposed on the circuit substrate100. The ring structure400includes a base portion MP and an overhang portion EP laterally extending across the at least one semiconductor device300with respect to the base portion MP, wherein the overhang portion EP has at least two different thicknesses. From another point of view, the bottom surface BS (e.g., the surface facing the semiconductor device300) of the overhang portion EP of the ring structure400is uneven and stepped. Such ring structure400is called a “stepped ring structure” in some examples.

In some embodiments, a top surface of the semiconductor device300is higher than a top surface of the integrated circuit structures TD11, TD12, TD13.

In some embodiments, the overhang portion EP of the ring structure400has a first part P1with a first thickness and a second part P2/P3with a second thickness, the second thickness is greater than the first thickness, and the first part P1corresponds to the at least one semiconductor device300.

In some embodiments, from a top view or a cross-sectional view, the second part P3of the ring structure400is spaced apart from the at least one semiconductor device300or the integrated circuit structures TD11, TD12, TD13, as shown inFIG.4.FIG.5.FIG.6,FIG.9,FIG.10andFIG.11.

In some embodiments, from a top view or a cross-sectional view, the second part P2of the ring structure400is spaced apart from the at least one semiconductor device300but overlapped with at least one of the integrated circuit structures TD11, TD12, TD13, as shown inFIG.7,FIG.8,FIG.12,FIG.13,FIG.14,FIG.15andFIG.16. In some embodiments, the overhang portion EP of the ring structure400further extends over a portion of the encapsulation layer E.

In some embodiments, the overhang portion EP has a continuously varied thickness, as shown inFIG.9andFIG.11.

In some embodiments, the semiconductor structure further includes a buffer layer402disposed on a bottom surface BS of the overhang portion EP and a sidewall of the base portion MP of the ring structure400, as shown inFIG.7,FIG.11,FIG.14andFIG.16.

At act502, at least one semiconductor package is bonded to a circuit board.FIG.1,FIG.2,FIG.4toFIG.16illustrate different views corresponding to some embodiments of act502.

At act504, a plurality of semiconductor devices are bonded to the circuit substrate and around the semiconductor package.FIG.3toFIG.16illustrate different views corresponding to some embodiments of act504.

At act506, a ring structure is mounted on the circuit board, wherein the ring structure includes a plurality of opening patterns corresponding to the plurality of semiconductor devices.FIG.4toFIG.16illustrate different views corresponding to some embodiments of act506.

In some embodiments, the method further includes, before mounting the ring structure on the circuit board, forming a buffer layer on surfaces of the opening patterns of the ring structure, as shown inFIG.6,FIG.7.FIG.11,FIG.14andFIG.16.

In some embodiments, from a top view or a cross-sectional view, the ring structure is separated from the semiconductor package by a non-zero distance, as shown inFIG.4.FIG.5,FIG.6,FIG.9,FIG.10andFIG.11.

In some embodiments, from a top view or a cross-sectional view, the ring structure is partially overlapped with the semiconductor package, as shown inFIG.7,FIG.8,FIG.12,FIG.13,FIG.14,FIG.15andFIG.16.

In view of the above, in the disclosure, a semiconductor device includes semiconductor package(s) and semiconductor device(s) around the semiconductor package(s), which are laterally disposed and electrically connected to a circuit substrate. In some embodiments, a ring structure is disposed on the circuit substrate to encircle the semiconductor device(s). The ring structure of the disclosure has an overhang portion across the semiconductor device(s), and the overhang portion has opening pattern(s) corresponding to the underlying semiconductor device(s). In some embodiments, by including such ring structure with opening pattern(s), the warpage of the 3DIC semiconductor structure may be effectively controlled without contacting the underlying semiconductor device(s), thus enhancing yield and reliability of the semiconductor device.

According to some embodiments of the disclosure, a semiconductor structure includes a circuit substrate, at least one semiconductor package, at least one semiconductor device, and a ring structure. The at least one semiconductor package is disposed on the circuit substrate, and the semiconductor package includes a plurality of integrated circuit structures. The at least one semiconductor device, disposed on the circuit substrate and aside the semiconductor package. The ring structure is disposed on the circuit board. The ring structure includes at least one opening pattern corresponding to the semiconductor device.

According to some embodiments of the disclosure, a semiconductor structure includes a circuit substrate, a plurality of integrated circuit structures, an encapsulating layer, at least one semiconductor device and a ring structure. The integrated circuit structures are laterally disposed on the circuit substrate. The encapsulating layer encapsulates the integrated circuit structures. The at least one semiconductor device is disposed on the circuit substrate and separated from the encapsulating layer. The ring structure is disposed on the circuit substrate. The ring structure includes a base portion and an overhang portion laterally extending across the at least one semiconductor device with respect to the base portion, wherein the overhang portion has at least two different thicknesses.

According to some embodiments of the disclosure, a method of forming a semiconductor structure includes: bonding at least one semiconductor package to a circuit board; bonding a plurality of semiconductor devices to the circuit substrate and around the semiconductor package; and mounting a ring structure on the circuit board, wherein the ring structure includes a plurality of opening patterns corresponding to the plurality of semiconductor devices.