Switching power supply device and method for controlling switching power supply device

By an NMOS (22) being switched on or off, a direct-current voltage E0 is charged in a capacitor (24), and a DC/DC converting circuit (30) charges a direct-current output voltage V0 to be supplied to a load L in a capacitor (34). A load state detection circuit (40) determines whether the load L is in a lightly loaded state or in a non-lightly loaded state, and outputs a signal (S40) as a determination signal. When the load state detection circuit (40) outputs a signal (S41) of “L” as a signal representing that it is a lightly loaded state, a time period setting circuit (41) outputs a signal (S41) of “L” after a preset time period elapses. A PFC on/off switching circuit (42) is supplied with the signal (S41) of “L”, and outputs a control signal (S25) of “L” to a power factor improvement circuit (20). Accordingly, in the case where the load L enters a lightly loaded state, the operation of the power factor improvement circuit (20) is stopped when the preset time elapses.

TECHNICAL FIELD

The present invention relates to a switching power supply device mounted with a power factor improvement circuit.

BACKGROUND ART

FIG. 11is a circuit diagram showing a conventional switching power supply device.

This switching power supply device has a power factor improvement circuit provided at the output side of a full-wave rectifying circuit2connected to an alternating-current power supply1, and a DC/DC converting circuit provided at the output side of the power factor improvement circuit. As the switching power supply device being provided with the power factor improvement circuit, the capacitance of an input electrolysis capacitor of the DC/DC converting circuit can be small-sized.

The power factor improvement circuit comprises a coil3, an N-channel MOSFET (hereinafter referred to as NMOS)4, a diode5, a capacitor6, and a PFC section control circuit7.

In the power factor improvement circuit, the NMOS4is switched on or off in accordance with a control signal output from the PFC section control circuit7thereby repeatedly flowing a switching current through the coil3. The switching current is in proportion to the instant value of a pulsating voltage generated by the full-wave rectifying circuit2. The coil3stores energy therein by letting the switching current flow therethrough, and the stored energy is changed into a direct-current voltage through the diode5and charged into the capacitor6.

The DC/DC converting circuit comprises a transformer8, an NMOS9, a diode10, a capacitor11, a DC/DC section control circuit12, and an output voltage detection circuit13.

The DC/DC section control circuit12is a circuit that controls switching on or off of the NMOS9, and the output terminal of the DC/DC section control circuit12is connected to the gate of the NMOS9. The output voltage detection circuit13is a circuit that detects the voltage charged in the capacitor111and supplies it to the DC/DC section control circuit12.

This switching power supply device is further equipped with a load state detection circuit14and a PFC on/off switching circuit15. The load state detection circuit14is connected to the DC/DC section control circuit12. The PFC on/off switching circuit15is disposed between the load state detection circuit14and the PFC section control circuit7of the power factor improvement circuit. The PFC on/off switching circuit15actuates or stops the PFC section control circuit7.

In this switching power supply device, the NMOS4is switched on or off in accordance with a control signal generated by the PFC section control circuit7. When the NMOS4is switched on, a switching current flows through the coil3and stores energy therein. In a time period in which the NMOS4is switched off, the stored energy is supplied to the capacitor6via the diode5thereby charging the capacitor6. The capacitor6is charged with a voltage E0which is higher than the alternating-current voltage generated by the alternating-current power supply1.

On the other hand, the NMOS9is switched on or off in accordance with a control signal supplied from the DC/DC section control circuit12to the gate of the NMOS9. When the NMOS9is switched on, a switching current flows from the capacitor6to a primary winding8aof the transformer8and stores energy therein. When the NMOS9is switched off, the stored energy is charged into the capacitor11via the diode10. The capacitor11is charged with a direct-current voltage V0to be supplied to a load16.

The output voltage detection circuit13detects the level of the direct-current voltage V0, and supplies a voltage signal indicating the level of the direct-current voltage V0to the DC/DC section control circuit12. The DC/DC section control circuit12generates a control signal for setting the timing at which the NMOS9is switched on or off based on the voltage signal supplied from the output voltage detection circuit13. The NMOS9is switched on or off in accordance with this control signal. The load state detection circuit14outputs a detection result indicating whether the loaded state of the load16is lightly loaded or heavily loaded, based on the duty ratio of this control signal.

When the detection result indicates a heavily loaded state, the PFC on/off switching circuit15controls the PFC section control circuit7to generate a control signal, so that the switching operation will be continued and the resultant energy will be charged into the capacitor6.

To the contrary, when the detection result indicates a lightly loaded state, the PFC on/off switching circuit15controls the control signal from the PFC section control circuit7to be fixed at a low level (“L”) so that the switching operation will be stopped. Due to this, the energy generated by the switching current ceases to be charged into the capacitor6. When the operation of the power factor improvement circuit stops, the power to be consumed drops accordingly. In this state, the DC/DC converting circuit only operates.

As known from the above, a switching power supply device mounted with a conventional power factor improvement circuit includes a device for stopping the operation of the power factor improvement circuit based on the state of the load (see, for example, Unexamined Japanese Patent Application KOKAI Publication No. H8-111975).

As described above, since a conventional switching power supply device has its power factor improvement circuit stop operating when the load16is light, it can realize low power consumption. However, since a predetermined startup time is required, after the power factor improvement circuit starts operating, for the output voltage from the power factor improvement circuit to reach a predetermined voltage, trouble is caused if the lightly loaded state and the heavily loaded state are repeated alternately. The trouble will now be explained with reference toFIG. 12.

FIG. 12is a timing chart for explaining the problem of a conventional switching power supply device.

If the electricity requirements of the load16are large and the load16is heavy, a load current I0that flows through the load16increases. If the electricity requirements of the load16are small and the load16is light, the load current I0flowing through the load16decreases and the voltage V0charged in the capacitor11fluctuates. The DC/DC section control circuit12generates such a control signal as to make the voltage detected by the output voltage detection circuit13constant, thereby setting the timing at which the NMOS9is switched on or off.

For example, if the load16decreases to under a predetermined value at a time t1, the duty ratio of the control signal is changed. The load state detection circuit14detects the state of the load16from the duty ratio, and generates, for example, a signal S14having a low level (hereinafter referred to as “L”) in a time period in which the load16is light. In the time period in which the signal S14of “L” is generated, the control signal to be supplied from the PFC section control circuit7to the NMOS4is controlled at “L” by the PFC on/off switching circuit15thereby the power factor improvement circuit is stopped. In other words, the switching of the NMOS4is stopped.

As the power factor improvement circuit being stopped, the voltage E0charged in the capacitor6lowers. If the power factor improvement circuit remains stopped, the charging voltage E0of the capacitor6becomes almost the effective value E1of the pulsating voltage generated by the full-wave rectifying circuit2.

Even when the load16gets heavy again at a time t2and the power factor improvement circuit starts operating, a predetermined startup time is required before the output voltage of the power factor improvement circuit reaches a predetermined voltage. Since during this time the load of the switching power supply device is heavy, the charging voltage E0of the capacitor6sharply decreases from the time t2. Afterwards, the charging voltage E0moderately increases from the time t3.

If the load16again becomes light at the time t4before the charging voltage E0of the capacitor6increases to the full, the operation of the power factor improvement circuit stops and the charging voltage E0of the capacitor6starts decreasing from this time.

As described above, if the state where the load16is light and the state where it is heavy appear alternately, there occur time periods t12to t13, t15to t16, and t17to t18during which the charging voltage E0of the capacitor6largely decreases. Assuming a voltage value E2[V] as the minimum voltage required for the DC/DC converting circuit to maintain its output voltage V0constant, the charging voltage E0of the capacitor6falls below the charging voltage value E2[V] in the time periods t12to t13, t15to t16, and t17to t18, and the output voltage of the DC/DC converting circuit therefore lowers (dips).

DISCLOSURE OF INVENTION

It is an object of the present invention to provide a switching power supply device capable of maintaining the output voltage even when the load fluctuates, and a method for controlling a switching power supply device.

To achieve the above object, a power supply device according to a first aspect of the present invention is characterized by comprising:

a charging section (20,50) which is actuated to charge a charging element (24,54);

a direct-current voltage generation section (30,60) which generates a second direct-current voltage based on a first direct-current voltage of the charging element (24,54), and applies the generated second direct-current voltage to a load (L); and

an operation control section (40,41,42,70,71,72,80,90,100) which actuates the charging section (20,50), determines whether a state of the load (L) to which the direct-current voltage generation section (30,60) applies the second direct-current voltage is a lightly loaded state or not, and in a case where determining that the load (L) enters a lightly loaded state, controls the charging section (20,50) to stop operation of charging the charging element (24,54) when a preset time period elapses after it determines that the load (L) enters the lightly loaded state.

A method for controlling a power supply device according to a second aspect of the present invention is a method for controlling a power supply device comprising a charging section (20,50) which is actuated to charge a charging element (24,54), and a direct-current voltage generation section (30,60) which generates a second direct-current voltage based on a first direct-current voltage of the charging element (24,54) and applies the generated second direct-current voltage to a load (L), characterized by comprising:

a step of determining whether the load (L) is in a lightly loaded state or not; and

a step of, in a case where it is determined that the load (L) enters a lightly loaded state, controlling the charging section (20,50) to stop operation, when the preset time period elapses.

BEST MODE FOR CARRYING OUT THE INVENTION

FIRST EMBODIMENT

A switching power supply device according to a first embodiment of the present invention comprises a power factor improvement circuit20, a DC/DC converting circuit30, a load state detection circuit40, a time period setting circuit41, and a PFC on/off switching circuit42as shown inFIG. 1, and supplies a direct-current voltage V0to a load L.

A full-wave rectifying circuit2rectifies an alternating-current voltage generated by an alternating-current power supply1and applies a pulsating voltage to the power factor improvement circuit20.

The power factor improvement circuit20is a circuit which is connected to the output end of the full-wave rectifying circuit2and improves the power factor by controlling the switching current to follow the pulsating voltage. The power factor improvement circuit20is a non-insulated type one, and comprises a coil21, an NMOS22, a diode23, a capacitor24, and a PFC section control circuit25.

One end of the coil21is connected to the positive electrode of the full-wave rectifying circuit2, and the other end of the coil21is connected to the drain of the NMOS22serving as the switching element and to the anode of the diode23. The source of the NMOS22is connected to the negative electrode of the full-wave rectifying circuit2. The cathode of the diode23is connected to one electrode of the capacitor24serving as a charging element. The other electrode of the capacitor24is connected to the negative electrode of the full-wave rectifying circuit2.

The PFC section control circuit25is a circuit for supplying a control signal S25to the NMOS22to control the whole power factor improvement circuit20, and comprises a timing control circuit25aas shown inFIG. 4. The timing control circuit25ais a circuit for generating the control signal S25to be supplied to the NMOS22, and its output terminal is connected to the gate of the NMOS22as shown inFIG. 1. The charging voltage E0of the capacitor24is the output voltage of the power factor improvement circuit20.

The NMOS22is switched on when the level of the control signal S25output from the PFC section control circuit25becomes a high level (hereinafter referred to as “H”), and switched off when the signal level becomes a low level (hereinafter referred to as “L”). When the NMOS22is switched on or off, the power factor improvement circuit20starts operating and charges the capacitor24.

The capacitor24is an input electrolytic capacitor of the DC/DC converting circuit30, and is a charging element that is electrically charged by the power factor improvement circuit20. When the operation of the power factor improvement circuit20is stopped, the charging voltage E0of the capacitor24is charged at around the peak value of the pulsating voltage applied by the full-wave rectifying circuit2. The charging voltage E0of the capacitor24becomes almost the effective value of the pulsating voltage.

When a startup time passes after the power factor improvement circuit20starts operating, it charges the capacitor24with a voltage higher than the alternating-current voltage generated by the alternating-current power supply1. The charging voltage E0of the capacitor24at this time is assumed as voltage E1.

The DC/DC converting circuit30is a circuit for voltage-converting the output voltage E0of the power factor improvement circuit20and applying the converted voltage to the load L. The DC/DC converting circuit30stabilizes the voltage to be supplied to the load L by PWM (Pulse Width Modulation) control. The DC/DC converting circuit comprises a transformer31, an NMOS32, a diode33, a capacitor34, a DC/DC section control circuit35, and an output voltage detection circuit36.

The transformer31includes a primary winding31aand a secondary winding31bwhich are electromagnetically coupled to each other. One end of the primary winding31ais connected to the connection node between the cathode of the diode23and the one electrode of the capacitor24which are in the power factor improvement circuit20.

The drain of the NMOS32is connected to the other end of the primary winding31aof the transformer31. The source of the NMOS32is connected to the other electrode of the capacitor24.

The anode of the diode33is connected to one end of the secondary winding31bof the transformer31. The cathode of the diode33is connected to one electrode of the capacitor34. The other electrode of the capacitor34is earthed together with the other end of the secondary winding31b.

The turn ratio between the primary winding31aand secondary winding31bof the transformer31is set at such a ratio at which the output voltage to be applied to the load L by the DC/DC converting circuit30can be maintained even if the charging voltage E0of the capacitor24becomes the minimum voltage necessary for operation.

The minimum voltage of the charging voltage E0of the capacitor24is determined by the minimum input voltage of the alternating-current voltage of the alternating-current power supply1, the loaded state of the load L, the capacitance of the capacitor24, margin, etc. The minimum voltage is assumed as E2.

The NMOS32is a switching element constituted by an N-channel MOSFET, and the gate of the NMOS32is connected to the output terminal of the DC/DC section control circuit35.

The DC/DC section control circuit35is a circuit for controlling the DC/DC converting circuit30by PWM, and comprises a control signal generation section35aas shown inFIG. 2. The control signal generation section35asets the duty ratio based on the level of a signal output from the output voltage detection circuit36and generates a control signal S35having this duty ratio set therein. With one cycle regarded as a full time period, the duty ratio indicates the ratio of a time period of “H” to the full time period. The DC/DC section control circuit35supplies the control signal S35generated by the control signal generation section35ato the NMOS32. The NMOS32is switched on when the control signal S35output from the DC/DC section control circuit35becomes “H, and switched off when the control signal S35becomes “L”.

The diode33rectifies the voltage induced in the secondary winding31b. The capacitor34smoothes the rectified voltage output from the diode33and generates a direct-current voltage V0. This direct-current voltage V0is the output voltage of the DC/DC converting circuit30and at the same time the output voltage of the switching power supply device. The output voltage detection circuit36is connected to the connection node between the one electrode of the capacitor34and the cathode of the diode33.

The output voltage detection circuit36is constituted by, for example, resistors36aand36bconnected in series as shown inFIG. 2. One end of the resistor36ais connected to the connection node between the one electrode of the capacitor34and the cathode of the diode33, and one end of the resistor36bis earthed to the ground. The connection node between the resistor36aand the resistor36bserves as the output terminal of the output voltage detection circuit36. The output voltage detection circuit36outputs divisional voltages of the direct-current voltage V0which is divided between the resistor36aand the resistor36bto the DC/DC section control circuit35.

The load state detection circuit40, the time period setting circuit41, and the PFC on/off switching circuit42serve for determining whether the state of the load L is a lightly loaded state or not, and when determining that the load L enters a lightly loaded state, stopping the power factor improvement circuit20from the operation of charging the capacitor24when a preset time period elapses since the load L enters the lightly loaded state.

The load state detection circuit40is a circuit that detects the loaded state of the load L based on the duty ratio of the control signal S35, and outputs a determination signal representing whether the load L is in a lightly loaded state or not.

As shown inFIG. 2, the load state detection circuit40is connected to the output terminal of the DC/DC section control circuit35, and acquires the control signal S35generated by the control signal generation section35aof the DC/DC section control circuit35.

The load state detection circuit40comprises a resistor40aand a resistor40bin series, a capacitor40c, a comparator40d, and a reference power supply40c. One end of the resistor40ais connected to the output terminal of the DC/DC section control circuit35, and the other end of the resistor40bis earthed. The connection node between the resistor40aand the resistor40bis connected to one electrode of the capacitor40cand to the input terminal (+) of the comparator40d. The other electrode of the capacitor40cis earthed.

The reference power supply40eis connected to the other input terminal (−) of the comparator40d. The reference voltage of the reference power supply40eis a voltage set in advance for determining whether the load L is in a lightly loaded state or in a non-lightly loaded state.

The comparator40doutputs from its output terminal, a signal S40showing a result of comparing the voltage supplied to its input terminal (+) and the voltage of the reference power supply40esupplied to its input terminal (−).

If the load current of the load L is small, the duty ratio of the control signal S35becomes small and the voltage to be supplied to the input terminal (+) becomes low. If the voltage supplied to the input terminal (+) is lower than the voltage of the reference power supply40e, the comparator40doutputs the signal S40of “L” from the output terminal. The output terminal of the comparator40dacts as the output terminal of the load state detection circuit40, and the load state detection circuit40outputs the signal S40of “L” to the time period setting circuit41as a determination signal representing that a lightly loaded state is entered.

On the contrary, when the current consumed by the load L increases, the duty ratio of the control signal S35becomes large. Accordingly, the voltage to be supplied to the input terminal (+) of the comparator40dincreases. When the voltage supplied to the input terminal (+) becomes higher than the voltage of the reference power supply40e, the comparator40doutputs a signal S40of “H” from the output terminal. The load state detection circuit40outputs the signal S40of “H” to the time period setting circuit41as a determination signal representing that a non-lightly loaded state is entered.

The time period setting circuit41is a circuit that outputs a signal S41of “L” having a timing set therein to represent that a lightly loaded state is entered, when the signal S40of “L” is output from the load state detection circuit40as a determination signal representing that the load L enters a lightly loaded state.

As shown inFIG. 3, the time period setting circuit41comprises an NMOS41a, a capacitor41b, a constant current source41c, and a schmitt trigger circuit41d.

The NMOS41ais an N-channel MOSFET that is switched on to discharge the capacitor41b, and the signal S40is supplied to its gate from the load state detection circuit40. The source of the NMOS41ais earthed. The NMOS41ais switched on when the signal S40of “H” is supplied to the gate from the load state detection circuit40and switched off when the signal S40of “L” is supplied to the gate.

The capacitor41bserves to set the level of a signal to be supplied to the schmitt trigger circuit41d, and the drain of the NMOS41ais connected to one electrode of the capacitor41b. The other electrode of the capacitor41bis earthed.

The constant current source41cserves to charge the capacitor41b, and is connected to the connection node between the one electrode of the capacitor41band the source of the NMOS41a.

The input terminal of the schmitt trigger circuit41dis connected to the one electrode of the capacitor41b. The schmitt trigger circuit41dcompares the voltage Vc of the one electrode of the capacitor41bwith a preset threshold, and outputs an output signal S41based on the comparison result. The schmitt trigger circuit41dholds two thresholds Vth1and Vth2. The threshold Vth1is a threshold to be compared with the voltage Vc when the voltage Vc rises from a lower level. The threshold Vth2is a threshold to be compared with the voltage Vc when the voltage Vc falls from a higher level. When the level of the signal S40changes from “H” to “L” and the voltage Vc gets across the threshold Vth1from a lower level, the schmitt trigger circuit41dhaving an inverter outputs the signal S41of “L”. When the level of the signal S40changes from “L” to “H” and the voltage Vc gets across the threshold Vth2from a higher level, the schmitt trigger circuit41doutputs the signal S41of “H”.

The threshold Vth1is set higher than the threshold Vth2(Vth1>Vth2). With the two thresholds Vth1and Vth2set in this manner, the schmitt trigger circuit41dcomes to have a hysteresis between the voltage Vc to be input thereto and the signal level of the signal S41to be output therefrom, and thus fictions stably without being influenced by noise, etc.

Note that the capacitance of the capacitor41band the current supply ability of the constant current source41care set such that a time T taken from when the NMOS41ais switched off to when the voltage of the one electrode of the capacitor41bgets across the threshold Vth1should be a preset time.

The time T is set based on the startup time which is required from a time when the power factor improvement circuit20starts operating to a time when the charging voltage E0of the capacitor24, i.e., the output voltage of the power factor improvement circuit reaches the voltage E1, and based on the effect of saving power consumption, and is preferably 100 μsec to 10 sec for practical use.

The PFC on/off switching circuit42is a circuit that controls the timing control circuit25ato stop outputting the control signal S25to the NMOS22thereby to stop the operation of the power factor improvement circuit20, when the signal S41of “L” is output from the time period setting circuit41.

The PFC on/off switching circuit42comprises a PMOS42aas shown inFIG. 4. The PMOS42ais a P channel MOSFET, and the signal S41of the time period setting circuit41is input to its gate. The source of the PMOS42ais connected to the output terminal of the PFC section control circuit25, and the drain of the PMOS42ais earthed. The PMOS42ais switched on when the signal S41of “L” is supplied to its gate. When the PMOS42ais switched on, the control signal S25to be output from the PFC section control circuit25becomes “L”, thereby the NMOS22is switched off and the operation of the power factor improvement circuit20is stopped.

Next, the operation of this switching power supply device will be explained.

When supplied with an alternating-current voltage from the alternating-current power supply1, the full wave rectifying circuit2rectifies the supplied alternating-current voltage and applies a pulsating voltage to the power factor improvement circuit20.

When the PMOS42aof the PFC on/off switching circuit42is switched off, the PFC section control circuit25outputs a control signal S25which turns to “H” and “L” alternately and is generated by the timing control circuit25ato the power factor improvement circuit20.

The NMOS22of the power factor improvement circuit20has its gate supplied with the control signal S25, and is switched on or off in accordance with the level of the control signal S25.

When the control signal S25becomes “H”, the NMOS22is switched on, and a switching current flows through the coil21and stores energy therein while the NMOS22is being switched on. When the control signal S25becomes “L”, the NMOS22is switched off, and a current flows through the capacitor24via the diode23in accordance with the energy having been stored during the on period. The capacitor24is charged with this current and smoothes the pulsating voltage applied to the power factor improvement circuit20. The power factor improvement circuit20charges the capacitor24with a higher voltage than the alternating-current voltage generated by the alternating-current power supply1. The charging voltage E0of the capacitor24reaches the voltage E1.

The DC/DC section control circuit35starts operating and supplies the control signal S35of “H” or “L” to the gate of the NMOS32.

When the control signal S35is “H”, the NMOS32is switched on, and a switching current flows through the primary winding31aof the transformer31from the capacitor24while the NMOS22is being switched on thereby storing energy in the primary winding31a.

When the control signal S35is “L”, the NMOS32is switched off. And when the NMOS32is switched off, a current flows through the capacitor34via the secondary winding31band the diode33in accordance with the energy having been stored during the on period. The capacitor34is charged with this current and smoothes the rectified voltage from the diode33. The capacitor34is charged with a direct-current voltage V0to be supplied to the load L.

The output voltage detection circuit36generates voltages proportional to the direct-current voltage V0at the resistors36aand36b, and supplies a signal indicating the level of the direct-current voltage V0to the DC/DC section control circuit35. The DC/DC section control circuit35performs PWM control based on the level of the signal supplied from the output voltage detection circuit36.

That is, if the direct-current voltage V0becomes slightly higher than a preset voltage, the DC/DC section control circuit35slightly reduces the duty ratio of the control signal S35. When the duty ratio of the control signal S35becomes slightly smaller, the direct-current voltage V0becomes lower.

On the other hand, if the direct-current voltage V0becomes slightly lower than the preset voltage, the DC/DC section control circuit35slightly increases the duty ratio of the control signal S35. When the duty ratio of the control signal S35is slightly increased, the direct-current voltage V0increases. In this manner, the direct-current voltage V0is controlled to be the preset voltage, and becomes almost constant.

Along with the increase or decrease of the load current I0flowing through the load L, the load L becomes a lightly loaded state or a non-lightly loaded state. In accordance with this change in the load state, the direct-current voltage V0also slightly changes.

The load state detection circuit40detects the loaded state of the load L based on the duty ratio of the control signal S35generated by the DC/DC section control circuit35.

The resistor40aand resistor40bof the load state detection circuit40divide the level of the control signal S35repeating “H” and “L”. The capacitor40cis charged with a divisional voltage signal resulting from the control signal S35, and smoothes this divisional voltage signal. The load state detection circuit40supplies the signal of the level having been smoothed to the input terminal (+) of the comparator40d.

The comparator40dcompares the level of the signal supplied from the capacitor40cwith the reference voltage supplied from the reference power supply40e.

When a predetermined load current I0flows through the load L from the times t2to t3shown inFIG. 5and the level of the signal from the capacitor40csupplied to the input terminal (+) of the comparator40dbecomes higher than the reference voltage, the comparator40doutputs a signal S40of “H”. The load state detection circuit40outputs this signal S40of “H” to the time period setting circuit41as a determination signal showing that the load L is in a non-lightly loaded state,

If the level of the signal S40supplied to the gate of the NMOS41aof the time period setting circuit41is “H”, the NMOS41ais switched on. When the NMOS41ais switched on, one electrode of the capacitor41bgets earthed, and the charging voltage Vc of the capacitor41bbecomes almost 0. Since the level of the signal to be supplied to the schmitt trigger circuit41dbecomes equal to or lower than the threshold Vth1, the schmitt trigger circuit41dsupplies a signal S41of “H” to the PFC on/off switching circuit42.

The PMOS42aof the PFC on/off switching circuit42is switched off when its gate is supplied with the signal S41of “H”. When the PMOS42ais switched off, the PFC section control circuit25outputs a control signal S25generated by the timing control circuit25ato the power factor improvement circuit20. The power factor improvement circuit20charges the capacitor24with a voltage higher than the alternating-current voltage generated by the alternating-current power supply1, and the charging voltage E0of the capacitor24becomes the voltage E1.

When the time t3comes and the load current I0flowing through the load L decreases, the duty ratio of the control signal S35becomes small. When the duty ratio of the control signal S35becomes small and the level of the signal supplied from the capacitor40cbecomes lower than the reference voltage, the level of the signal S40to be output from the comparator40dchanges from “H” to “L”. The load state detection circuit40outputs the signal S40of “L” to the time period setting circuit41as a signal representing that the load L enters a lightly loaded state.

When the level of the signal S40supplied to the gate of the NMOS41aof the time period setting circuit41changes from “H” to “L”, the NMOS41ahaving been switched on is switched off. When the NMOS41ais switched off, the capacitor41bis charged with the current from the constant current source41cand the charging voltage Vc of the capacitor41bincreases from 0.

Even if the charging voltage Vc of the capacitor41bincreases but if a non-lightly loaded state returns at the time t4which is before the threshold Vth1of the schmitt trigger circuit41dis got across, the load state detection circuit40outputs a signal S40of “H” to the time period setting circuit41. Then, the NMOS41aof the time period setting circuit41is switched on with its gate supplied with the signal S40of “H”, and the capacitor41bis earthed again before the charging voltage Vc of the capacitor41bgets across the threshold th1. Because of this, the schmitt trigger circuit41dcontinuously supplies a signal S41of “H” to the PMOS42aof the PFC on/off switching circuit42.

The PMOS42aremains switched off, and the NMOS22of the power factor improvement circuit20is switched on or off in accordance with the level of the control signal S25output from the PFC section control circuit25. As described above, if the load L enters a lightly loaded state but if the load L is switched to a non-lightly loaded state before the preset time T passes, the power factor improvement circuit20continues to operate as it has been.

When the power factor improvement circuit20continues to operate and the time t9comes at which the load current I0flowing through the load L decreases and the voltage at the input terminal (+) of the comparator40dbecomes lower than the reference voltage, the load state detection circuit40likewise outputs a signal S40of “L” to the time period setting circuit41as a signal representing that the load L enters a lightly loaded state.

The NMOS41aof the time period setting circuit41is switched off and the charging voltage Vc of the capacitor41bincreases from 0. If the time T passes from the time t9and the non-lightly loaded state continues even when the time t10comes, the charging voltage Vc of the capacitor41bgets across the threshold Vth1of the schmitt trigger circuit41d.

When the level of the signal supplied to the shcmitt trigger circuit41dgets across the threshold Vth1, the schmitt trigger circuit41dsupplies a signal S41of “L” to the PFC on/off switching circuit42.

The PMOS42aof the PFC on/off switching circuit42is switched on with its gate supplied with the signal S41of “L”. When the PMOS42ais switched on, the PFC section control circuit25supplies a control signal S25of “L” to the power factor improvement circuit20. The NMOS22of the power factor improvement circuit20is to be kept switched off with its gate supplied with the control signal S25of “L”. That is, the operation of the power factor improvement circuit20stops. When the operation of the power factor improvement circuit20stops, the power to be consumed will be reduced accordingly. Then, the charging voltage E0of the capacitor24decreases.

In a case where the load L turns to be a non-lightly loaded state at the time t11, the power factor improvement circuit29starts operating. In the case where the load L enters the non-lightly loaded state, the charging voltage E0of the capacitor24further decreases because the load of the switching power supply device increases. However, since the charging voltage E0of the capacitor24at the time t10at which the power factor improvement circuit20stops operating is E1, the charging voltage E0does not decrease to equal to or lower than the voltage E2. Accordingly, the DC/DC converting circuit30can maintain the output voltage V0, and thus applies an almost constant output voltage V0to the load L.

Then, the power factor improvement circuit20charges the capacitor24when the startup time passes after the power factor improvement circuit20starts operating, in order to increase the charging voltage E0to the voltage E1.

As explained above, the switching power supply device according to the present embodiment keeps the power factor improvement circuit20, which requires a predetermined time to start up, functioning until the preset time T passes, even if the load L have entered lightly loaded state.

Accordingly, it is possible to prevent the charging voltage E0of the capacitor24from decreasing to equal to or lower than the lowest voltage E2required for keeping the DC/DC converting circuit30functioning, and to maintain the output voltage V0of the DC/DC converting circuit30at the preset voltage. Therefore, it is also possible to prevent the load L from erroneous operation.

SECOND EMBODIMENT

FIG. 6is a block diagram showing a switching power supply device according to the second embodiment of the present invention.

The above-described first embodiment has explained a switching power supply device mounted with a non-insulated power factor improvement circuit20using a coil21, however, various power factor improvement circuits can be mounted. Further, The DC/DC converting circuit30of the switching power supply device of the first embodiment uses the transformer31, but a DC/DC converting circuit using no transformer can be mounted. The switching power supply device according to the present embodiment is mounted with an insulated power factor improvement circuit50and a boosting DC/DC converting circuit60, and comprises a load state detection circuit70, a time period setting circuit71, and a PFC on/off switching circuit72.

The power factor improvement circuit50comprises a transformer51, an NMOS52, a diode53, a capacitor54, and a PFC section control circuit55.

One end of a primary winding of the transformer51is connected to the positive electrode of a full-wave rectifying circuit2which rectifies an alternating-current voltage generated by an alternating-current power supply1. The drain of the NMOS52is connected to the other end of the primary winding. The source of the NMOS52is connected to the negative electrode of the full-wave rectifying circuit2.

The anode of the diode53is connected to one end of a secondary winding of the transformer51, and one electrode of the capacitor54is connected to the cathode of the diode53, The other electrode of the capacitor54is earthed together with the other end of the secondary winding of the transformer51. The output terminal of the PFC section control circuit55is connected to the gate of the NMOS52. The PFC section control circuit55is a circuit same as the PFC section control circuit25of the first embodiment.

The DC/DC converting circuit60comprises a coil61, an NMOS62, a diode63, a capacitor64, a DC/DC section control circuit65, and an output voltage detection circuit66.

One end of the coil61is connected to the connection node between the capacitor54and the diode53which are in the power factor improvement circuit50. The other end of the coil61is connected to the drain of the NMOS62and to the anode of the diode63. The cathode of the diode63is connected to one electrode of the capacitor64. The other electrode of the capacitor64is earthed together with the source of the NMOS62. A load L is connected between both the electrodes of the capacitor64.

The DC/DC section control circuit65is a circuit same as the DC/DC section control circuit35of the first embodiment, and the output terminal of the DC/DC section control circuit65is connected to the gate of the NMOS62. The output voltage detection circuit66is a circuit same as the output voltage detection circuit36, and is connected to the connection node between the one electrode of the capacitor64and the cathode of the diode63. The output terminal of the output voltage detection circuit66is connected to the DC/DC section control circuit65.

The load state detection circuit70, the time period setting circuit71, and the PFC on/off switching circuit72are circuits same as the load state detection circuit40, the time period setting circuit41, and the PFC on/off switching circuit42of the first embodiment respectively, and have the same connections.

The power factor improvement circuit50switches on or off the NMOS52in accordance with a control signal generated by the PFC section control circuit55. When the NMOS52is switched on, a switching current flows through the primary winding of the transformer51. Energy is stored in the transformer51as the switching current flows therethrough, and the stored energy is charged into the capacitor54via the secondary winding of the transformer51and the diode53when the NMOS52is switched off.

The NMOS62of the DC/DC converting circuit60is switched on or off based on the level of a control signal generated by the DC/DC section control circuit65, and a switching current flows through the coil61when the NMOS62is switched on. The energy stored in the coil61as the switching current flows therethrough is stored in the capacitor64via the diode63in a period in which the NMOS62is switched off. The energy stored in the capacitor64appears as a direct-current output voltage V0to be supplied to the load L.

The load state detection circuit70, the time period setting circuit71, and the PFC on/off switching circuit72operate in the same way as the load state detection circuit40, the time period setting circuit41, and the PFC on/off switching circuit42of the first embodiment respectively.

As described above, the switching power supply device of the present embodiment is mounted with the power factor improvement circuit50and DC/DC converting circuit60which are different from the first embodiment, but the load state detection circuit70, the time period setting circuit71, and the PFC on/off switching circuit72operate in the same way as the load state detection circuit40, the time period setting circuit41, and the PFC on/off switching circuit42of the first embodiment respectively. Therefore, fluctuations in the direct-current output voltage V0to be supplied to the load L are suppressed and erroneous operation, etc. of the load L can be prevented likewise the first embodiment.

The present invention is not limited to the above-described embodiments, but can be modified in various manners. The followings are examples of such modifications.

(1) The present invention is not limited to the power factor improvement circuits20and50, but may be a boosting switching power supply circuit different from the power factor improvement circuits20and50or something like a voltage-multiplying rectifying circuit.

(2) The present invention is applicable to a switching power supply device mounted with not only the DC/DC converting circuits30and60, but also various types of DC/DC converting circuit.

(3) The time period setting circuit41ofFIG. 3comprises the schmitt trigger circuit41d, but may comprise a direct-current power supply41eand a comparator41fas shown inFIG. 7instead of the schmitt trigger circuit41d.

FIG. 7is a circuit diagram showing an example of modification of the time period setting circuit41.

In this case, the connection node between one electrode of the capacitor41band the drain of the NMOS41amay be connected to the input terminal (−) of the comparator41fand the direct-current power supply41emay be connected to the Input terminal (+) of the comparator41f. Further, the reference voltage generated by the direct-current power supply41emay be set variable in accordance with the output from the comparator41fso as to have a hysteresis likewise the case where the schmitt trigger circuit41d, which is a schmitt inverter, is provided.

(4) In the first embodiment, the time period setting circuit41having the schmitt trigger circuit is used to provide a hysteresis between the output signal S40of the load state detection circuit40and the output signal S41of the time period setting circuit41and thereby to control executing and stopping of charging in the power factor improvement circuit20to be switched stably. As compared with this, a circuit for providing a hysteresis such as a schmitt trigger circuit or the like may be set in the load state detection circuit40, so that executing and stopping of charging in the power factor improvement circuit20may be switched stably.

(5) The load state detection circuit40determines whether it is a lightly loaded state or a non-lightly loaded state based on the duty ratio of the control signal S35, however, may be so configured as to determine based on the direct-current output voltage V0or may be so configured as to determine based on a returned signal.

(6) The PFC on/off switching circuit42is constituted by the PMOS42awhereby the control signal S25is fixed at “L”. However, the PFC section control circuit25may be so configured as to be made active or inactive by a signal generated by the PFC on/off switching circuit42.

(7) The load state detection circuit40may be changed to the following load state detection circuit80shown inFIG. 8.

FIG. 8is a circuit diagram showing the load state detection circuit80as a modified example of the load state detection circuit40.

This load state detection circuit80comprises an on period comparing circuit BOA and a reference period generating circuit80B.

The on period comparing circuit80A is constituted by a delay flip-flop (hereinafter referred to as D-FF)81. The control signal S35to be supplied from the DC/DC section control circuit35to the gate of the NMOS32is input to the data input terminal D of the D-FF81. The positive phase output terminal Q of the D-FF81is the output terminal of the load state detection circuit80, and the load state detection circuit80outputs a signal S40representing whether the load L is in a lightly loaded state or in a non-lightly loaded state.

The reference period generating circuit80B comprises a first reference period generating circuit82, a second reference period generating circuit83, and a toggle switch circuit84. The first reference period generating circuit82is a circuit which generates a pulse signal P1synchronous with a periodic wave signal generated by an unillustrated internal oscillator or the like and having a width of a first reference period (T1). The second reference period generating circuit83is a circuit which generates a pulse signal P2synchronous with the periodic wave signal and having a width of a second reference period (T2) shorter than the first reference period.

The toggle switch circuit84comprises a two-input AND gate84a, a two-input AND gate84b, and a two-input OR gate84c. One input terminal of the AND gate84ais connected to the output terminal of the first reference period generating circuit82, and the other input terminal of the AND gate84ais connected to the reverse phase output terminal Q bar of the D-FF81. The output terminal of the AND gate84ais connected to one input terminal of the OR gate84c.

One input terminal of the AND gate84bis connected to the output terminal of the second reference period generating circuit83. The other input terminal of the AND gate84bis connected to the positive phase output terminal Q of the D-FF81. The output terminal of the AND gate84bis connected to the other input terminal of the OR gate84c. The output terminal of the OR gate84cis the output terminal of the toggle switch circuit84and is connected to a clock terminal of the D-FF81.

The operation of the load state detection circuit80will be explained.

The first reference period generating circuit82generates a pulse signal P1synchronous with a periodic wave signal generated by the unillustrated oscillator and having a pulse width of T1. The second reference period generating circuit83generates a pulse signal P2having a pulse width of T2shorter than T1synchronously with the periodic wave signal.

The positive phase output terminal Q and reverse phase output terminal Q bar of the D-FP81respectively output signals having mutually complementary logic levels. When the reverse phase output terminal Q bar of the D-FF81is at “H”, the AND gate84aof the toggle switch circuit84permits the pulse signal P1generated by the first reference period generating circuit82to pass therethrough. When the positive phase output terminal Q of the D-FF81is at “HI”, the AND gate84bpermits the pulse signal P2generated by the second reference period generating circuit83to pass therethrough. The OR gate84cobtains the logical sum of the output signals from the AND gates84aand84band supplies it to the clock terminal of the D-FF81. That is, the toggle switch circuit84selects the second reference period generating circuit83when the positive phase output terminal Q of the D-FF81is at “H” and supplies the output signal therefrom to the clock terminal of the D-FF81, and selects the first reference period generating circuit82when the reverse phase output terminal Q bar of the D-FF81is at “H” and supplies the output signal therefrom to the clock terminal of the D-FF81.

When the level of the clock terminal falls, the D-FF81latches the state of the signal level of the control signal S35which the DC/DC section control circuit35supplies to the gate of the NMOS32.

For example, when the reverse phase output terminal Q bar of the D-FF81is at “H”, the toggle switch circuit84selects the first reference period generating circuit82and supplies the pulse signal P1to the clock terminal of the D-FF81. If the control signal S35is at “H” and thus the NMOS32is in the state of being switched on when the pulse signal P1falls, the D-FF81latches “H” and outputs “H” from the positive phase output terminal Q.

If the control signal S35has become “L” before the pulse signal P1falls, the D-FF81latches “L” and outputs “L” from the positive phase output terminal Q. That is, the D-FF81compares the period in which the NMOS32is switched on and the period generated by the first reference period generating circuit82, and shows the result on the signal S40. When the load L is in a lightly loaded state, the signal S40becomes “L”, because the timing at which the NMOS32is switched off comes early. When the load is in a non-lightly loaded state, the signal S40becomes “H” because the timing at which the NMOS32is switched off comes late.

When the positive phase output terminal Q of the D-FF81is at “H”, the toggle switch circuit84selects the second reference period generating circuit83and supplies the pulse signal P2to the clock terminal of the D-FF81. If the control signal S35is at “H” and the NMOS32is switched on when the pulse signal P2falls, the D-FF81latches “H” and the level of the positive phase output terminal Q becomes “H”. If the control signal S35has become “L” before the pulse signal P2falls, the D-FF81latches “L” and outputs the level of the positive phase output terminal Q.

That is, the D-FF81compares the period in which the NMOS32is switched on with the period generated by the second reference period generating circuit83, and outputs a signal S40showing the result. When the load L is in a lightly loaded state, the level of the signal S40becomes “L” because the timing at which the NMOS32is switched off comes early. When the load L is in a non-lightly loaded state, the level of the signal S40becomes “H” because the timing at which the NMOS32is switched off comes late.

As the period (T1) set by the first reference period generating circuit82being set longer than the reference period (T2) set by the second reference period circuit83, the toggle switch circuit84has a hysteresis in selection switching.

(8) The PFC on/off switching circuit42shown inFIG. 4controls the switching operation of the NMOS22serving as the switching element to be stopped, by switching on the PMOS4ain order to get the output terminal of the PFC section control circuit25earthed. According to this manner, an unillustrated control power supply for driving the PFC section control circuit25gets earthed, producing a large loss. In order to prevent such a loss, the following PFC on/off switching circuits90and100which are shown inFIG. 9andFIG. 10may be used.

FIG. 9is a circuit diagram showing a PFC on/off switching circuit90as a modified example of the PFC on/off switching circuit42.

The PFC on/off switching circuit90comprises an inverter91, three NPN transistors92,93, and94, two PNP transistors95and96, and a constant current source97. The signal S41is input to the input terminal of the inverter91from the time period setting circuit41. The output terminal of the inverter91is connected to the base of the transistor92. The emitter of the transistor92is earthed.

The collector of the transistor92, the collector and base of the transistor93, and the base of the transistor94are connected to the constant current source97. The emitters of the transistors93and94are both earthed. The transistors93and94constitute a current mirror circuit.

The collector of the transistor94is connected to the collector and base of the transistor95and to the base of the transistor96. The emitters of the transistors95and96are connected to a power supply in common. The transistors95and96constitute a current mirror circuit. The collector of the transistor96is connected to the input terminal of the PFC section control circuit25to which a drive current Ibaisis input.

In the PFC on/off switching circuit90shown inFIG. 9, when the level of the signal S41supplied from the time period setting circuit41is high, the inverter91outputs “L.” and the transistor92is switched off. In response to this, the base voltages of the transistor93and transistor94increase to switch on the transistor93and transistor94. In other words, the current mirror circuit constituted by the transistors93and94is switched on. As the transistor94being switched on, the base voltages of the transistor95and transistor96decrease thereby to switch on the current mirror circuit constituted by the transistor95and transistor96. Due to this, a drive current Ibiasflows to the PFC section control circuit25via the transistor96. Supplied with the drive current Ibias, the PFC section control circuit25starts operating and generates the control signal S25for switching on or off the NMOS22.

When the level of the signal S41supplied from the time period setting circuit41is low, the inverter91outputs “H” and the transistor92is switched on. By the transistor92being switched on, the base voltages of the transistor93and transistor94decrease to thereby switch off the current mirror circuit constituted by the transistors93and94. By the transistor94being switched off, the base voltages of the transistors95and96constituting a current mirror circuit increase to switch off the transistor96. By the transistor96being switched off, the drive current Ibiasceases to flow to the PFC section control circuit25, stopping the operation of the PFC section control circuit25. That is, the control signal S25for controlling switching on or off of the NMOS22is fixed at “L”, and the NMOS22is stopped from being switched on or off.

Since the PFC on/off switching circuit90shown inFIG. 9controls the NMOS22to be stopped from being switched on or off by prohibiting the drive current Ibiasfor the interior of the PFC section control circuit25from flowing to the PFC section control circuit25, the power to be consumed in the PFC section control circuit25can be greatly suppressed.

FIG. 10is a circuit diagram showing a PFC on/off switching circuit100as another modified example of the PFC on/off switching circuit42.

This PFC on/off switching circuit100comprises a resistor101, an NPN transistor102, a resistor103, and a PNP transistor104. The signal S41is input to one end of the resistor101from the time period setting circuit41. The other end of the resistor101is connected to the base of the transistor102. The emitter of the transistor102is earthed, and the collector of the transistor102is connected to one end of the resistor103. The other end of the resistor103is connected to the base of the transistor104.

The emitter of the transistor104is connected to a power supply, and the collector of the transistor104is connected to the power supply terminal of the PFC section control circuit25. The transistor104serves as a switch for shutting the power to be supplied to the PFC section control circuit25.

When the level of the signal S41output from the time period setting circuit41is high, the transistor102is in the on state and the base voltage of the transistor104is therefore decreased. Accordingly, the transistor104gets in the on state, and power is supplied to the PFC section control circuit25to allow the PFC section control circuit25to operate. Due to this, the NMOS22is switched on or off. When the level of the output signal S41from the time period setting circuit41drops, the transistor102is switched off and the transistor104is switched off. In this state, no power is supplied to the PFC section control circuit25, and therefore the PFC section control circuit25does not operate and the NMOS22is not switched on or off.

In the PFC on/off switching circuit100shown inFIG. 10, the transistor104shuts the power supply for the PFC section control circuit25. Therefore, power loss in the PFC section control circuit25can be suppressed to the lowest level possible.

The present invention is based on Japanese Patent Application No. 2002-373027 filed on Dec. 24, 2002, specification, claims and drawings of which are incorporated herein by reference in its entirety.

INDUSTRIAL APPLICABILITY

The present invention can be applied to industrial fields in which a power supply device is used.