Memory modules including capacity for additional memory

A method and apparatus for repair of a multi-chip module, such as a memory module, are provided where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to single in-line memory modules (SIMMs), dual in-line memory modules (DIMMs), and the like, and, more specifically, to SIMM, DIMM and other memory module boards providing at least one extra die site for attachment of an additional die to replace a defective die or dice thereon.

2. State of the Art

An integrated circuit (IC) typically includes a semiconductor die (die) electrically attached to a lead frame providing physical support for the die and connecting the die to external circuitry, such as a printed circuit board or other conductor-carrying substrate. In such an arrangement, the lead frame and die may be connected by wire bonding the lead fingers of the lead frame to contact or bond pads located on a surface of the die. The die and lead frame are then typically encapsulated within a transfer-molded plastic package, although ceramic and metal packages may also be used, depending on the operating environment and the packaging requirements of the die.

As the demand for memory, in particular random access memory (RAM), surpassed the memory capability of a single die, multi-chip modules (MCMs) were developed, such modules having a number of memory devices attached to a single substrate, such as a printed circuit board. A SIMM is a memory module having multiples of the same basic die, where the semiconductor memory chips are aligned in a row and interconnected to a printed circuit board to, in effect, create a single device with the memory capacity of the combined memory chips. An example of a SIMM, including a plurality of dynamic random access memory devices (DRAMs) used as memory in a computer, is illustrated in U.S. Pat. No. 4,992,850, issued Feb. 12, 1991, to Corbett et al., assigned to the assignee of the present invention. As the demand for additional memory on a single device has increased, other devices, such as dual in-line memory modules (DIMMs), have also been developed. Such devices, while providing the desired memory capability on a single printed circuit board, present unique problems for the manufacturer when one or more of the semiconductor memory chips thereon fail.

It is well known that semiconductor dice have an early failure rate, often referred to in reliability terms as “infant mortality.” Moreover, infant mortality of MCMs is multiplied depending on the number of individual semiconductor dice provided therein. For example, a SIMM composed of ten dice, each die having an individual reliability yield of 95%, would result in a first pass test yield of less than 60%, while a SIMM composed of twenty dice, each die having an individual reliability yield of 95%, would produce a first pass test yield of less than 36%.

When a single packaged die, such as a dual in-line package (DIP), fails, a manufacturer can attempt to repair the device, use the device for some reduced capacity function if the device is only partially defective, or scrap it. When complete failure of a die has not occurred and a portion of the memory is good (e.g., 1, 2, or 3 megabits of a 4-megabit chip), such a device is not typically useful. For MCMs such as a SIMM, where a number of semiconductor dice are attached to a single substrate, however, it may not be possible to use the device for some reduced capacity function and it is surely not desirable to scrap the entire MCM when some, if not most, of the dice attached thereto are not defective. Thus, the manufacturer is left with the somewhat costly process of reworking the MCM, typically by removing the defective chips and replacing them with new ones. Such a procedure is described in U.S. Pat. Nos. 5,239,747 and 5,461,544, where a SIMM having a specialized trace pattern suitable for both burn-in and individual die testing is tested to determine if any of the semiconductor devices mounted thereon are non-functional and, if so, either the defective device is replaced with a device which has been subjected to burn-in, or the entire multi-chip module can be subjected to another burn-in process after the replacement of the defective device. The defective devices, however, are merely replaced by removing the defective device and replacing it with another device either previously subjected to burn-in or not. This rework process can be complicated, time consuming and costly, depending upon the type of device, the type of mounting of the device on the substrate, and the type of substrate used for mounting. For example, plastic-packaged devices are typically physically pulled to disconnect their leads from the module, while so-called “glob topped” (silicone or epoxy gel covering) dice may be removed after cutting through the encapsulant to the wire-bonded die, which is pulled. In addition, since replacing multiple unacceptable dice on a MCM poses physical risks to other MCM dice during the replacement operation, it may be desirable to discard such a MCM rather than attempt rework, particularly where the reliability of the replacement die is not known.

Depending on the extent of testing and/or burn-in procedures employed, a die may typically be classified into varying levels of reliability and quality. For example, a die may meet only minimal quality standards by undergoing standard probe testing or ground testing while still in wafer form, while individual separated or “singulated” dice may be subjected to intelligent burn-in at full-range temperatures with full testing of the die's circuitry. A die that has been so tested is termed a “known good die” (KGD). Examples of methods for the testing and burn-in of an individual die prior to packaging are disclosed in U.S. Pat. Nos. 5,448,165 and 5,475,317.

A cost-effective method for producing known reliable SIMMs, DIMMs, and the like, with larger numbers of chips on a single device is desirable for industry acceptance and use. In an attempt to provide known reliable SIMMs complying with consumer requirements, it would be desirable to fabricate the SIMM completely of KGD. Using only KGD in a SIMM, however, would not currently be cost effective since each KGD has to be subjected to performance and burn-in testing, both of which are costly at this point in time. Typically, however, SIMMs are fabricated from probe-tested dice, and are subsequently burned-in and performance tested. In contrast to the use of all KGD in a SIMM, when using dice with well known production and reliability histories, particularly where the dice being used are known to have a low infant mortality rate, the use of such minimally tested dice to produce a SIMM is usually found to be the most cost effective alternative.

As previously stated, since typical testing and burn-in procedures are generally labor and time intensive, posing significant risks to the dice of a SIMM, in the event that a SIMM contains an unacceptable die, replacement of the unacceptable die with a KGD is preferable. Module rework with a KGD does not typically require the SIMM to be subjected to additional burn-in procedures that can unnecessarily stress the dice. An example of a method and apparatus for the testing and burn-in of an individual die prior to packaging is illustrated in U.S. Pat. No. 5,424,652, issued Jun. 13, 1995, to Hembree et al., assigned to the assignee of the present invention. Such a method and apparatus provide a source of KGD to allow for the rework of an unacceptable die in a MCM with a KGD. In other instances, it is known to test a die in a package for functionality and replace any defective die. Such is illustrated in U.S. Pat. Nos. 5,137,836, 5,378,981, and 5,468,655.

One way in the art to eliminate the need to physically remove defective or unacceptable dice from a SIMM has been to provide additional, redundant spaces on the printed circuit board for attachment of replacement chips. Thus, one additional space has been provided adjacent each memory chip on the board, the additional spaces providing contacts for attachment of a semiconductor chip similar to the one it is replacing. For example, if a 32-megabit SIMM contains eight 4-megabit chips, then eight additional spaces are provided on the SIMM, configured to accept up to eight additional 4-megabit chips, if necessary. Such a configuration, however, results in a memory module that is approximately twice as big as a memory module having no extra spaces.

Therefore, a need exists for the cost-efficient fabrication of SIMMs, DIMMs, and the like, of known performance and reliability requirements that requires a minimal amount of rework when one or more dice attached thereto are found defective.

BRIEF SUMMARY OF THE INVENTION

Accordingly, a memory module, such as a single in-line memory module (SIMM) or dual in-line memory module (IMM), is provided having at least one redundant or auxiliary chip attach location for attachment of a replacement chip. When one or more dice on a memory module are found defective, one or more replacement chips can be attached to the one or more auxiliary chip attach locations with the size of the replacement chips being at least equal to the amount of defective memory. Thus, the defective dice can be replaced without needing to be physically removed. Moreover, by providing auxiliary chip attach locations that can accept different sizes and memory capacities of replacement semiconductor chips, one replacement chip can replace several defective chips on the memory module.

In a preferred embodiment, a SIMM or DIMM board is provided having a plurality of primary chip attach locations and one auxiliary chip attach location. Each of the plurality of primary chip attach locations is similarly configured to accept the same type of semiconductor chip, such as a number of 4-megabit chips. The auxiliary chip attach location, on the other hand, is configured to accept more than one capacity of replacement semiconductor chip. Thus, depending on the amount of defective memory detected on the SIMM, a replacement chip having at least that amount of good memory can be attached to the auxiliary chip attach location. Consequently, the replacement chip may be a 1-megabit chip, if only one (1) megabit of memory is found defective, or a 4-megabit chip, if an entire 4-megabit chip is found to be defective, the configuration of the auxiliary chip attach location being capable of accepting either replacement chip.

In another preferred embodiment, a SIMM or DIMM is provided having two rows of the same type of semiconductor memory chip and a redundant or additional chip attach location for accepting a variety of semiconductor memory chips. The redundant chip attach location is electronically connected in parallel to the rest of the memory chips so that if one or more memory chips are found defective, an auxiliary replacement chip having an amount of memory approximately equal to that found defective can be attached to the additional chip attach location.

Having the capability to easily and cost effectively rework memory modules without the need to remove defective chips or the need to substitute defective chips on a one-to-one basis is highly desirable. The ability to provide auxiliary chip attach locations that can accommodate a plurality of different chip configurations not only makes rework more simple, but allows memory modules with large numbers of chips to be cost effective. For example, in yet another preferred embodiment, a memory module having three rows of similar memory chips is provided with more than one auxiliary chip attach location, each of the auxiliary chip attach locations being capable of receiving more than one type of semiconductor die. Thus, if only one of the many chips provided thereon fails entirely, then one substantially identically configured chip can be attached to any one of the three auxiliary chip attach locations. If more than one memory chip fails or more defective memory is located than can be replaced with a single auxiliary chip, then, if necessary, more than one replacement chip can be attached to any one or more of the three auxiliary chip attach locations.

In yet another preferred embodiment, rather than having all of the auxiliary chip attach locations capable of receiving variously configured chips, at least two auxiliary chip attach locations are each provided with different configurations. Thus, depending on the number of bad memory chips, one or more chips having a combined memory capacity substantially equal to the bad memory can be attached to the auxiliary chip attach locations. For example, on a DIMM with five defective 4-megabit chips found, a replacement 16-megabit chip can be attached to the auxiliary chip attach location configured to receive 16-megabit chips and a replacement 4-megabit chip can be attached to the auxiliary chip attach location configured to receive a 4-megabit chip.

Preferably, the replacement chips are KGD so that the additional burn-in is not required on the memory module. Moreover, the KGD may be partially defective dice or “partials” that are known to be good for a certain capacity of memory (e.g., 3 megabits of a 4-megabit chip). This is particularly attractive, since a high percentage (approaching 50%) for some designs of 16-megabit DRAMS is partially or completely defective, while 5-10% of 4-megabit DRAMS comprise partials. Since partials might otherwise be discarded, beneficial use thereof as replacement chips enhances the effective yield rate for the chips and lowers per-unit memory costs.

Thus, for example, for a SIMM having a design memory capacity of 32 megabits with 7 of the 32 megabits tested defective, a replacement partial 16-megabit chip known to be good for 7 megabits could be attached to an auxiliary location. The defective memory of 7 megabits on the primary chip(s) could then be disabled. Similarly, for a 32-megabit memory module with 7 bad megabits of memory and more than one auxiliary chip attach location, a replacement full 4-megabit KGD and a 3-megabit “partial” KGD could be attached to two of the auxiliary chip attach locations.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 1, a single in-line memory module (SIMM)10, in accordance with the present invention, is illustrated having an elongate substrate12, such as a printed circuit board (PCB) or other substrate known in the art, to which a plurality of semiconductor memory chips14is attached. The chips14are all preferably substantially similar in configuration and memory capacity and are flip-chip bonded to individual chip attach locations of the substrate12as is known in the art. That is, as shown in the example of flip-chip bonding ofFIG. 1A, the chips14are provided with bumped solder balls15on each bond pad17located on the active surface19of the chip14and are superimposed over similarly configured contacts or terminals21on the surface16of the substrate12, at which time the solder balls15are heated and melted or “reflowed” to form a mechanical and electrical connection between the substrate12and each chip14. Other conductive elements, such as a conductive or conductor-filled epoxy, may be employed in lieu of solder. Each chip14may also be wire bonded to the substrate12, as illustrated inFIG. 1B, where, as opposed toFIG. 1A, the chip14is positioned on active surface19and wire bonds23are made between the bond pads17of the chip14and contacts or terminals21on the surface16of the substrate12.

Longitudinally extending along one edge18of the SIMM10, a male socket-type electrical connection20is provided having a plurality of electrical contacts22configured to interface with a SIMM socket as known in the art. Each of the chips14is electrically connected to one or more of the plurality of electrical contacts22through various electrical traces carried in or on the substrate12, as known in the art.

In addition to the standard or primary chip attach locations for the chips14, a redundant or auxiliary chip attach location24is provided on the surface16. The auxiliary chip attach location24is provided with a plurality of contact points or terminals26that can be connected to more than one type of replacement semiconductor chip. As shown inFIG. 1, the auxiliary chip attach location24is provided with an inner array28of contact points or terminals26and an outer array30of contact points or terminals26. As better illustrated in the close-up view ofFIG. 2, the auxiliary chip attach location40includes a plurality of contacts42comprising an inner array44for attachment of a chip of similar configuration to the chips14of FIG.1. An outer array46of contacts42forms the appropriate configuration for attachment of a larger-capacity replacement chip. In the illustrated embodiment, each of the contacts42of the inner array44is connected via a trace48to a corresponding contact42of the outer array46. While, in some instances, such a one-to-one correspondence between the contacts42of the inner and outer arrays44and46may be desirable, such a configuration is not required. The configuration of the outer array46, for example, may depend on the type, size, and configuration of a replacement die to be connected to the outer array46.

Accordingly, if during intelligent burn-in of the SIMM10one of the ten chips14shown inFIG. 1completely fails, then a replacement chip of substantially similar configuration to chips14can be attached to the inner array28to replace the failed chip14. As illustrated inFIG. 3, however, if more than one chip14fails or memory equaling the capacity of more than one chip is proven defective during burn-in, it may be necessary to connect a larger-capacity replacement chip50to the auxiliary chip attach location, one that provides enough memory to replace the combined memory of the failed chips14.

It should be noted that the replacement chip may be attached to the module by a technique different from that used to connect chips14. Thus, the replacement chip may be wire-bonded for ease of attachment, while the chips14were flip-chip attached by solder reflow. The replacement chip may then be separately glob-topped or otherwise protected after wire bonding, the primary chips having been previously underfilled and encapsulated during initial fabrication of the module.

Referring now toFIG. 4, another preferred embodiment of a chip attach location60is illustrated. The single array62of the chip attach location60is comprised of a plurality of elongate contacts64outwardly extending from an inner perimeter66to an outer perimeter68defined by the inner and outer ends70and72of each contact64, respectively. Such a configuration allows attachment of variously sized replacement chips50, so long as the bond pads of the replacement chip50can be bonded to the contacts of the chip attach location60, whether by wire bonding, such as that illustrated inFIG. 1B, by flip-chip bonding, as illustrated inFIG. 1A, or by other methods known in the art.

As illustrated inFIG. 5, a SIMM or dual in-line memory module (DIMM)80including two rows of memory chips84can also benefit from having a redundant chip attach location82for attachment of an additional or replacement chip if any of the chips84provided thereon are found defective. In prior art devices, a SIMM or DIMM80having twenty memory chips84thereon, as illustrated inFIG. 5, would typically not prove to be cost effective without the aforementioned 100% redundancy of auxiliary to primary chip sites. Having a redundant chip attach location82that can accommodate various sizes of replacement memory chips provides an easy, cost effective means of reworking such a device.

Similarly, inFIG. 6, a memory module90having thirty individual memory chips92is made possible by providing at least one auxiliary chip attach location94. Because of the difficulty associated with reworking a device having so many potentially defective chips, manufacturing such a device as memory module90would typically not even be attempted without the exclusive use of pretested known-good-die (KGD). The exclusive use of KGD primary chips would clearly not be cost effective because of the cost associated with testing each chip individually before attaching it to the memory device.

As illustrated inFIG. 6, it may be desirable to provide more than one auxiliary chip attach location94such as auxiliary locations96and98. Such a configuration has added benefits because it provides more flexibility for the type and number of chips that can be attached thereto. For example, if four of the memory chips92are found completely defective, each of the chips92having a design memory capacity of 16 megabits, and another chip92exhibits 3 megabits of defective memory, then a 3-megabit (partial 4-megabit) chip100can be attached to auxiliary location98and a 64-megabit chip102attached to auxiliary location96. Various other combinations could also be devised depending on the KGD on hand and the memory size of those KGD.

As shown inFIG. 7, it is contemplated that more than one auxiliary chip attach location112and114be provided on the memory device110, each of the auxiliary locations112and114capable of accepting a different replacement chip. In this preferred embodiment, the single auxiliary location82, as shown inFIG. 5, has been divided into two auxiliary locations112and114. Accordingly, depending on the number, if any, of defective or bad chips116, various combinations of known-good replacement chips can be selected depending on the size and memory size of those on hand.

It is also contemplated that various other memory modules known in the art, such as the DRAM card120illustrated inFIG. 8, could include at least one auxiliary chip site122for replacement of defective memory of primary chips124. Moreover, those skilled in the art will appreciate that, while not specifically illustrated, other multi-chip modules may also include and benefit from at least one redundant or auxiliary chip attach location.

Finally, as shown inFIG. 9, the multi-chip modules of the various preferred embodiments herein described, such as SIMM10ofFIG. 1, can be incorporated into a memory device130of an electronic system132, such as a computer system, that includes an input device134and an output device136coupled to a processor device138. Of course, the multi-chip module10can alternatively be incorporated into the input device134, the output device136, or the processor device138.

It will be appreciated by those skilled in the art that various methods can be used to achieve the desired memory capability of the memory device, such as use of enabling and/or disabling devices118located on each chip116of FIG.7. The enabling and/or disabling devices118may include fuses, antifuses, and other such devices known in the art that can fully or partially disable the memory capacity of a chip116. Furthermore, a programmable device, such as a so-called “traffic control” EEPROM, as known in the art, may be installed on each module and programmed based on burn-in results to reroute input and output paths and link the new KGD auxiliary chips to the remainder of memory on the module so as to present an interface to the mother board or other higher-level packaging, which is indistinguishable to the host system from a perfect as-fabricated module with 100% good primary or original memory. Such a traffic control EEPROM is illustrated at86in FIG.5.

Those skilled in the art will also appreciate that the number and configuration of auxiliary chip attach locations may vary, depending on the configuration of replacement chips and the needs of the user. Further, while the invention has been described with relation to memory devices, the invention may be practiced on many other multi-chip modules where a single chip attach location having the capability to accept various semiconductor devices could reduce the time and cost associated with rework.

It should be noted that the term “chip,” as used in the specification and appended claims, is intended as exemplary and not limiting, the invention having applicability to any packaged die, bare die, and/or any intermediate product thereof. In addition, while the preferred embodiments were illustrated as being flip-chip bonded to the substrate, the dice, whether replacement or otherwise, may be wire bonded or otherwise electrically attached to the substrate as known in the art.

It will also be appreciated by one of ordinary skill in the art that one or more features of any of the illustrated embodiments may be combined with one or more features from another to form yet another combination within the scope of the invention as described and claimed herein. Thus, while certain representative embodiments and details have been shown for purposes of illustrating the invention, it will be apparent to those skilled in the art that various changes in the invention disclosed herein may be made without departing from the scope of the invention, which is defined in the appended claims.