Wire bond pad system and method

To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

BACKGROUND

The present disclosure generally relates to the field of integrated circuit packaging, and more particularly to systems and methods of forming wire bond pads for packaging Radio Frequency (RF) integrated circuits (ICs).

2. Description of the Related Art

Silicon or other semiconductor wafers are fabricated into integrated circuits (ICs) as is known to one of ordinary skill in the art of IC fabrication. An IC is bonded and electrically connected to a carrier or substrate, which has layers of dielectric and metal traces, and packaged for use. A surface plating material is plated onto the top layer of copper traces to provide electrical connection points between the IC and the substrate, permitting the IC to interface with the outside world. Traditionally, nickel/gold (Ni/Au) has been a standard surface plating material for RFIC products and in certain situations, the RFIC is wire-bonded to the Ni/Au wire-bond pads plated on the surface of the substrate to form the electrical connections of the RFIC with its package. However, increases in gold prices have increased packaging costs associated with the Ni/Au surface plating.

SUMMARY

Systems and methods are disclosed to reduce the cost of RFIC packaging by using a Nickel/Palladium/Gold (Ni/Pd/Au) surface plating material for RFIC products. To decrease the costs, the gold layer in the Ni/Pd/Au surface plating is thinner than the gold layer in Ni/Au surface plating. However, Ni/Pd/Au has a much higher radio frequency sheet resistance than Ni/Au due to thin palladium and gold layers and the ferromagnetic nature of nickel. This contributes to reduced effective current sheet thickness and increased current crowding on the RF signals, and can, in some embodiments, lead to greater RF losses for RF signals traveling through the Ni/Pd/Au plated surfaces than are found on RF signals traveling through the Ni/Au plated surfaces. These losses can impact product performance and yield.

Further systems and methods are disclosed to reduce the RF losses associated with the lower cost Ni/Pd/Au surface plating for RFICs. In some embodiments of design layouts, the RF line/trace surface, edge, and sidewalls in the wire-bonding area are open to the plating process and are therefore plated with the Ni/Pd/Au surface finish. Due to the skin effect and eddy current effect on the RF current traveling through the plated wire-bonding areas, a majority of the RF current is running on the trace edges and side walls of the plated wire-bonding areas. Because a majority of the RF current is running on the trace edges and side walls, plating the trace edges and sidewalls contributes more to RF losses. To reduce the RF losses, some embodiments reconfigure the solder mask to cover the trace edges and sidewalls in the wire-bonding area such that the trace edges and sidewalls are not plated with the Ni/Pd/Au surface finish. The copper trace edges and sidewalls free from the Ni/Pd/Au plating around the wire-bonding areas provide a low resistive path for the RF current around the Ni/Pd/Au wire bond pad and thus, reduce the RF signal loss associated with the Ni/Pd/Au surface plating of the RFIC substrate.

Certain embodiments relate to a method of fabricating a radio frequency integrated circuit (RFIC) module including providing a substrate having at least one copper trace, the copper trace having a wire bonding surface. The method further includes forming a solder mask opening for a wire bonding pad directly over the bonding surface of the copper trace, the wire bonding pad having at least one edge and at least one sidewall. The method further includes forming solder mask directly over the at least one edge and the at least one sidewall of the wire bonding pad, plating the copper trace with a nickel layer, plating the nickel layer with a palladium layer and plating the palladium layer with a gold layer to form a nickel/palladium/gold wire bonding pad. The nickel/palladium/gold wire bonding pad has the at least one edge and the at least one sidewall free from the nickel, palladium, and gold layers.

According to a number of embodiments, the disclosure relates to a wire bonding pad for a radio frequency integrated circuit (RFIC) module. The wire bonding pad includes a nickel layer plated over a wire bonding surface of a copper trace, the copper trace formed on an upper surface of a substrate of an RFIC module. The wire bonding pad further includes a palladium layer plated over the nickel layer and a gold layer plated over the palladium layer. The wire bonding pad having a wire bond area, at least one edge adjacent to the wire bond area, and at least one sidewall adjacent to the at least one edge, the at least one edge and the at least one sidewall free from the nickel layer, the palladium layer, and the gold layer.

In accordance with various embodiments, an apparatus for fabricating a radio frequency integrated circuit (RFIC) module includes means for providing a substrate having at least one copper trace, the copper trace having a wire bonding surface, and means for forming a solder mask opening for a wire bonding pad directly over the bonding surface of the copper trace, the wire bonding pad having at least one edge and at least one sidewall. The apparatus further includes means for forming solder mask directly over the at least one edge and the at least one sidewall of the wire bonding pad, means for plating the copper trace with a nickel layer, means for plating the nickel layer with a palladium layer, and means for plating the palladium layer with a gold layer to form a nickel/palladium/gold wire bonding pad. The nickel/palladium/gold wire bonding pad has the at least one edge and the at least one sidewall free from the nickel, palladium, and gold layers.

DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS

The features of the systems and methods will now be described with reference to the drawings summarized above. Throughout the drawings, reference numbers are re-used to indicate correspondence between referenced elements. The drawings, associated descriptions, and specific implementation are provided to illustrate embodiments of the inventions and not to limit the scope of the disclosure.

Wire bonding is a technique for connecting electrical circuit devices, for example, integrated circuit (IC) die, to the next level of packaging. These circuit devices generally comprise a plurality of small conductive leads/pads that are electrically connected, for example, by ball bonding, wedge bonding, or the like, to wire bond pads on conductors embedded in the device package or substrate. The wire bond pads on the substrate provide the electrical connections between the IC and the substrate, permitting the IC to interface with the outside world. In either type of wire bonding, the wire is attached at both ends using some combination of heat, pressure, and ultrasonic energy to make a weld.

A plurality of copper patterns is formed on a substrate which is electrically connected to the circuit patterns, and a filler, such as a dielectric, is filled between the copper patterns such that an upper surface of the copper pattern is exposed. However, bare copper is not readily solderable or bondable and requires plating with a material that facilitates soldering or bonding. Areas that should not be solderable/bondable are covered with a material to resist plating. In general, solder resist refers to a polymer coating that acts as a mask and prevents the plating material from adhering to the masked copper traces. A surface plating material is plated onto the top layer of exposed copper traces to provide the wire bond pads. In some applications, wire bond pads are suited for wire bonding directly over active circuits to avoid damaging fragile devices and to lower metal resistance for power integrated circuits.

FIG. 1illustrates a portion of an IC module100comprising an IC102, a substrate116, a copper trace104, wire bond pads106a,106b, and bonding wires108, according to an embodiment. The IC is wire bonded to wire bond pads106through wires108. In the illustrated embodiment, wire bond pad106ais a 6-wire wire bond pad and wire bond pad106bis a 3-wire wire bond pad. In other embodiment, other numbers of wires108can be attached to the wire-bond pads106. Wire bond pad106comprises a bond area114, sidewalls110, and edges112.

FIG. 2illustrates a flow chart for an exemplary process200for forming wire bond pads. The process200is described with respect to the embodiment illustrated inFIG. 1. State202begins with a substrate116formed with layers of dielectrics and conductors104, including a trace104on an upper surface of the substrate116, to form circuit paths as is known to one of ordinary skill in the art of semiconductor fabrication.

At State204, the process200applies solder mask to those areas of the IC module100that are to be kept free of plating material, as is known to one of ordinary skill in the art of semiconductor fabrication. A solder mask opening defines the areas to which the plating material will adhere. In some embodiments, the solder mask opening exposes the wire bond area114, the sidewalls110, and the edges112of the wire bond pad106to the plating material. In other embodiments, the trace104and the wire bond area114, the sidewalls110, and the edges112of the wire bond pad106are open to the plating process.

At State206, the exposed areas (free of solder mask) of the copper trace104are plated with the plating material to form the wire bond pads106as is known to one of ordinary skill in the art of semiconductor fabrication.

In an embodiment, the plating material is nickel/gold (Ni/Au). At State206, the nickel layer is plated over the copper trace104and the gold layer is plated over the nickel layer. Examples of plating techniques include, for example, immersion plating deposition, electrolytic plating, electroless plating, and the like.

In an embodiment, the copper trace is between about 5 microns and about 50 microns thick, and preferably approximately 20 microns. The nickel layer in the Ni/Au plating is between about 2.5 microns to about 7.6 microns thick, and more preferably, between about 5 microns to about 7 microns. The gold layer is approximately 0.70+/−0.2 microns thick, and more preferably approximately 0.5+/−0.1 microns.

Traditionally, Ni/Au has been a standard surface plating material for radio frequency integrated circuit (RFIC) products. Radio frequency (RF) is a rate of oscillation in the range of about 30 kHz to about 300 GHz. In an embodiment, the RFIC102is wire-bonded to Ni/Au wire-bond pads106plated on the surface of the substrate116to form the electrical connections of the RFIC102with its package. However, increases in gold prices have increased packaging costs associated with the Ni/Au surface plating.

To reduce packaging costs, a nickel/palladium/gold (Ni/Pd/Au) plating material is used to form wire bond pads for RFICs. In an embodiment, the RFIC102is wire-bonded to Ni/Pd/Au wire-bond pads106plated on the surface of the substrate116to form the electrical connections of the RFIC102with its package. The Ni/Pd/Au plating uses less gold than the Ni/Au plating material, and, as gold prices increase, the Ni/Pd/Au plating is advantageously less costly than the Ni/Au plating material.

FIG. 3illustrates a cross-section of the Ni/Pd/Au wire bond pad106on the surface of the substrate116, according to an embodiment. The Ni/Pd/Au wire bond pad106comprises a nickel layer302, a palladium layer304, and a gold layer306.

Referring toFIGS. 2 and 3, at State206, the nickel layer302is plated over the copper trace104; the palladium layer304is plated over the nickel layer302, and the gold layer306is plated over the palladium layer304. Examples of plating techniques include, for example, immersion plating deposition, electrolytic plating, electroless plating, and the like.

In an embodiment illustrated inFIG. 3, a height HCuof the copper trace104is between about 5 microns and about 50 microns, and preferably 20 microns. A height HNiof the nickel layer302is between about 2.5 microns to about 7.6 microns, and more preferably between about 5 microns to about 7 microns. A height HPdof the palladium layer304is approximately 0.09+/−0.06 microns, and more preferably approximately 0.1+/−0.01 microns. A Height HAuof the gold layer306is approximately 0.10+/−0.05 microns, and more preferably approximately 0.1+/−0.01 microns.

However, the Ni/Pd/Au plated surface, due to the thin palladium and gold layers304,306and the ferromagnetic nature of the nickel layer302, has a higher sheet resistance at radio frequencies than the Ni/Au plated surface. Sheet resistance is applicable to two-dimensional systems where the thin film, such as surface finish plating for semiconductors, for example, is considered to be a two-dimensional entity. It is analogous to resistivity in three-dimensional systems. When the term sheet resistance is used, the current must be flowing along the plane of the sheet, not perpendicular to it.

In the Ni/Au wire bond pad embodiment described above, the sheet resistance of the Ni/Au is approximately 30 mΩ/square at 2 GHz whereas the sheet resistance of the Ni/Pd/Au in the Ni/Pd/Au wire bond pad embodiment described above and illustrated inFIG. 3is approximately 150 mΩ/square at 2 GHz. Consequently, plating the wire bond pads106with the Ni/Pd/Au plating material instead the Ni/Au plating material can, in an embodiment, lead to extra RF losses. In turn, this can impact product performance and yield. In some embodiments, a Ni/Pd/Au plated surface may potentially increase RF loss by approximately 0.1 dB to approximately 0.4 dB, or equivalently impact power efficiency by approximately 1% to approximately 4%.

Further, oscillating signals are subject to skin effect. Skin effect is the tendency of an alternating electrical current to distribute itself within a conductor so that the current density near the surface of the conductor is greater than that at its core. That is, the electric current tends to flow at the skin of the conductor at an average depth called the skin depth. The skin effect causes the effective resistance of the conductor to increase with the frequency of the current because much of the conductor carries little current. Skin effect is due to eddy currents induced by the alternating current. As the frequency of the signal increases, to RF frequencies, for example, the skin depth decreases. In addition, the eddy currents also cause crowding of the alternating RF current at the edges of the conductor. Thus, a major portion of the RF current travels on the edge and sidewalls of the conductor104.

FIG. 4illustrates an enlarged portion of an RFIC module400comprising an RFIC402, a substrate416, a copper trace404, wire bond pads406, and the bonding wires108, according to an embodiment. The RFIC402is wire bonded to the wire bond pads406through the bonding wires108. In the illustrated embodiment, a wire bond pad406ais a 6-wire wire bond pad and a wire bond pad406bis a 3-wire wire bond pad. In other embodiments, other numbers of wires108, such as for example, 1, 2, 3, 4, 5 or more than 6, can be attached to the wire-bond pads406. The wire bond pad406comprises a bond area414, sidewalls410, and edges412.

To reduce RF signal losses, the fabrication process can limit the Ni/Pd/Au wire bond pad406to the bond area414, leaving the sidewalls410and edges412free from the Ni/Pd/Au plating material. The majority of the RF current travels through the unplated edges and side walls surrounding the plated wire bond area414, instead of traveling through the plated edge412and sidewalls410as illustrated inFIGS. 1 and 3. Thus, the RF losses are reduced.

FIG. 5illustrates a flow chart for an exemplary process500for forming Ni/Pd/Au wire bond pads406, according to an embodiment. The process500is described with respect to the embodiment illustrated inFIG. 4. State502begins with the substrate416formed with layers of dielectrics and conductors404, including trace404on an upper surface of the substrate416, to form circuit paths as is known to one of ordinary skill in the art of semiconductor fabrication.

At State503, in an embodiment, the solder mask is reconfigured to cover the edges412and sidewalls410of the wire bond pads406. In another embodiment, the solder mask is reconfigured to cover the trace404, and the edges412and the sidewalls410of the wire bond pads406. The solder mask opening covers the wire bond area414, such that the wire bond area414is open to the plating process, while the edges412and the sidewalls410are not. In an embodiment, the width of the edge412covered by the solder mask should be at least wider than the solder mask opening registration tolerance. In another embodiment, the width of the edge412covered by the solder mask is approximately 10 microns to 200 microns, and preferably 50 microns to 100 microns.

At State504, the process500applies the reconfigured solder mask to the RFIC module400, as is known to one of ordinary skill in the art of semiconductor fabrication.

At State506, the process500plates the RFIC module400with the Ni/Pd/Au plating material to form the wire bond pads406as is known to one of ordinary skill in the art of semiconductor fabrication. Examples of plating techniques include, for example, immersion plating deposition, electrolytic plating, electroless plating, and the like.

FIG. 6illustrates a cross-section of the Ni/Pd/Au wire bond pad406on the surface of the substrate416, according to an embodiment. The Ni/Pd/Au wire bond pad406comprises a nickel layer602, a palladium layer604, and a gold layer606. As illustrated inFIG. 6, the edges412and sidewalls410of the Ni/Pd/Au wire bond pad406are free from the Ni/Pd/Au plating.

Referring toFIGS. 5 and 6, the nickel layer602is plated over the copper trace404; the palladium layer604is plated over the nickel layer602, and the gold layer606is plated over the palladium layer604. Examples of plating techniques include, for example, immersion plating deposition, electrolytic plating, electroless plating, and the like.

In an embodiment illustrated inFIG. 6, a height HCuof the copper trace404is between about 5 microns and about 50 microns, and preferably approximately 20 microns. A height HNiof the nickel layer602is between about 2.5 microns to about 7.6 microns, and more preferably between about 5 microns to about 7 microns. A height HPdof the palladium layer604is approximately 0.09+/−0.06 microns, and more preferably approximately 0.1+/−0.01 microns. A height HAuof the gold layer606is approximately 0.10+/−0.05 microns, and more preferably approximately 0.1+/−0.01 microns.

FIG. 7is a graph700comparing the RF losses for traces with edge/sidewall exposed surfaces and edge/sidewall plated surfaces, according to an embodiment. The graph700shows power loss expressed in decibels (dBs) along the y or vertical axis and frequency expressed in gigahertz (GHz) along the x or horizontal axis. The power loss of the RF signals is calculated as 10 log10[RFpowerout/RFpower in] at frequencies ranging from about 1.40 GHz to about 2.25 GHz.

The graph700comprises lines710,720,730,740, and750, representing the power loss of an RF signal through various traces on an RFIC substrate. Line710indicates an RF power loss of the RF signal through a bare copper trace (no surface finish). At approximately 1.9 GHz, as indicated by point715, the power loss is approximately 0.614 dB.

Line720indicates the power loss of the RF signal through a copper trace comprising a Ni/Au bonding pad having its edges and sidewalls free from plating, while line730indicates the power loss through a copper trace comprising a Ni/Au bonding pad with its edges and sidewalls plated with the Ni/Au plating material. Point725on line720indicates the power loss to be approximately 0.729 dB at approximately 1.9 GHz and point735on line730indicates the power loss to be approximately 0.795 dB at approximately 1.9 GHz.

Line740indicates the power loss of the RF signal through a copper trace comprising a Ni/Pd/Au bonding pad having its edges and sidewalls free from plating, while line750indicates the power loss through a copper trace comprising a Ni/Pd/Au bonding pad with its edges and sidewalls plated with the Ni/Pd/Au plating material. Point745on line740indicates the power loss to be approximately 0.923 dB at approximately 1.9 GHz and point755on line750indicates the power loss to be approximately 1.191 dB at approximately 1.9 GHz.

Referring to the embodiments illustrated inFIG. 7, the bare copper trace (line710) provides the least power loss and the trace comprising the Ni/Pd/Au bonding pad having plated edges and sidewalls (line750) provides the greatest RF power loss. Traces with Ni/Au bonding pads (lines720,730) create less power loss to the RF signal than traces with Ni/Pd/Au bonding pads (lines740,750). Comparing the traces comprising the Ni/Au bonding pad, the trace with exposed edge and sidewalls (line720) creates less power loss than the trace with the plated edge and sidewalls (line730). Similarly, the trace with the Ni/Pd/Au bonding pad with exposed edge and sidewalls (line740) creates less power loss to the RF signal than the trace comprising the Ni/Pd/Au bonding pad with plated edges and sidewalls (line750). As indicated by arrow760, in an embodiment, the RF power loss for the RF signal passing through the Ni/Pd/Au bonding pad that does not have its edges and sidewalls plated with the Ni/Pd/Au plating material is approximately 0.26 dB less than the RF power loss of the RF signal passing through the Ni/Pd/Au bonding pad with Ni/Pd/Au plated edges and sidewalls.

In an embodiment, there is a minimum width for the plated wire bond area414that is exposed to the process500to achieve successful and reliable wire bond connections.FIGS. 4 and 6, described above, illustrate embodiments of the wire bonding pads406that fit within the uniform width of the copper trace404. In other words, the width of the plated wire bond area414and the width of the unplated edges412and sidewalls414do not exceed the uniform width of the trace404in the area of the wire bond pad406and the areas of the trace404adjacent to the wire bond pad406.

FIGS. 8A-8Fillustrate exemplary layouts for wire bonding pads where the minimum width of the plated bond area414and the width of at least one unplated edge412exceed the uniform width of the trace404in the area of the wire bond pad406and the areas of the trace404adjacent to the wire bond pad406. If, in an embodiment, after the edge412of the wire bond pad406is covered with solder mask such that it remains free of plating, the minimum size requirements for the wire bond area414are not met, the width of the trace404can be proportionally increased with minimal edge exposure to meet the size requirements.

FIGS. 8A-8Dillustrate exemplary layouts of wire bond pads406having exposed edges412and sidewalls410surrounding the wire bond pads406. In an embodiment, if, after the edge412of the wire bond pad406is covered with solder mask such that it remains free of plating, the minimum size requirements for the wire bond area414are not met, the width of the trace404can be deformed with minimal edge exposure to meet the wire bonding area414size requirements. In other words, a layout of the wire-bonding area meets or is larger than the minimal dimensions set by the design rule of a substrate technology, and at the same time, minimizes plated edges and side walls of the copper trace comprising the bonding area. Thus, the RF current flows through a minimal distance on the high resistive plated edges and side walls. InFIGS. 8A-8D, the trace404expands in width in the area of the wire bond pad406to accommodate the wire bond area414. Further, the expanded trace404permits the wire bond pad406to maintain covered edges412and side walls410(not illustrated) during the solder mask process, which in turn permits the completed wire bond pad406to maintain exposed edges412and side walls410along all of the perimeter of the wire bond pad406.

FIGS. 8E and 8Fillustrate exemplary layouts where the trace404comprises the wire bond pad406, but circuit layout considerations limit the pad size and prevent the edge412from being covered with solder mask during the masking process. In one embodiment, the trace404deforms with a wire bond pad406to accommodate the wire bond area414. In another embodiment, the trace404deform in the area of the wire bond pad406to accommodate the wire bond area414. InFIG. 8E, the trace404is deformed with one wire bond pad406to accommodate a 3-wire wire bonding area414. InFIG. 8F, the trace404is deformed with two wire bond pads406to accommodate two 2-wire wire bonding areas414. Thus, the deformed trace404permits a minimal length of edges and sidewalls being plated, or in other words, maximizes the length of unplated edges and side walls to reduce RF losses and maintains the required bondable area of the wire bond pad.

To reduce costs, in some embodiments, Ni/Pd/Au instead of Ni/Au is plated onto the surface traces of substrates for RFIC modules to form wire-bond areas. However, Ni/Pd/Au has a higher RF sheet resistance than Ni/Au and this leads to higher RF losses for signals traveling through Ni/Pd/Au wire-bond areas than for signals traveling through Ni/Au wire-bond areas. To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow through low resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

While embodiments have been described with respect to Ni/Pd/Au surface plating, the disclosed systems and methods apply to any high RF loss surface plating, such as, for example, Sn, Pb, other surfaces of ferromagnetic materials, and the like.

Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The words “coupled” or connected”, as generally used herein, refer to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

The teachings of the invention provided herein can be applied to other systems, not necessarily the systems described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.