Methods for selective placement of dislocation arrays

Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation arrays with respect to devices subsequently formed on the layers.

FIELD OF THE INVENTION

This invention relates generally to semiconductor substrates and particularly to semiconductor substrates with strained semiconductor layers.

BACKGROUND

Silicon-germanium (SiGe) virtual substrates are a platform for new generations of very large scale integration (VLSI) devices that exhibit enhanced performance in comparison to devices fabricated on bulk Si substrates. An important component of a SiGe virtual substrate is a layer of SiGe that has been relaxed to its equilibrium lattice constant (i.e., one that is larger than that of Si). This relaxed SiGe layer may be formed directly on a Si substrate (e.g., by wafer bonding or direct epitaxy) or atop a relaxed graded SiGe layer, in which the lattice constant of the SiGe material has been increased gradually over the thickness of the layer. The SiGe virtual substrate can also incorporate buried insulating layers, echoing the structure of a semiconductor-on-insulator (SOI) wafer. In order to fabricate high performance devices on these platforms, thin strained semiconductor layers of Si, Ge, or SiGe are grown on the relaxed SiGe virtual substrates. The resulting biaxial tensile or compressive strain alters carrier mobilities in these layers, enabling the fabrication of high speed and/or low power devices.

Differences in lattice constants of various materials may result in misfit dislocations forming at an interface between the thin strained semiconductor layer, such as strained Si and an underlying layer, such as relaxed SiGe.

Misfit dislocations form when an upper strained semiconductor layer reaches a critical thickness Tcrit. This equilibrium critical thickness is a not a function of temperature, but at reduced temperatures, strained layers may be grown in a metastable state. The metastable thickness of the strained layer may be thicker than Tcrit, but misfit dislocations may not have formed because of the absence of sufficient thermal energy for their formation. The metastable critical thickness of a strained layer is larger than Tcrit, and decreases with increasing temperature. At temperatures commonly used for complementary metal-oxide semiconductor (CMOS) processing, the metastable critical thickness of a typical upper strained semiconductor layer is close to Tcrit. The critical thickness of a strained layer utilized in CMOS devices and processed at elevated temperatures may be therefore considered the equilibrium critical thickness Tcrit.

One may avoid the formation of misfit dislocations in, e.g., CMOS devices by keeping the thickness of the upper strained semiconductor layer much less than Tcrit. This approach, however, places severe constraints on CMOS design rules. In addition, the close proximity of an underlying semiconductor layer containing, for example, SiGe to a top surface of the wafer creates a number of process optimization challenges, such as the definition of source and drain junctions, formation of metal silicides, and fabrication of shallow-trench-isolation (STI) regions. Optimization of these design features is complicated by interaction with, e.g., both Si and Ge.

Alternatively, one may distance misfit dislocations from an upper strained semiconductor layer by, e.g., forming the upper strained semiconductor layer with a thickness much greater than a critical thickness for misfit dislocation formation. Then, however, the misfit dislocations—even though concentrated away from the top surface of the strained layer—may cause problems in devices, such as MOSFETs, fabricated in this layer. Because the density of misfit dislocations increases as layer thickness increases above Tcrit, this solution may create a high density of misfit dislocations at an interface between the strained layer and the underlying layer. Misfit dislocations may act as diffusion pipes, facilitating migration of dopants between sources and drains, thereby promoting leakage. Misfit dislocations may also act as carrier recombination/generation centers in which electrons and holes combine, thereby also promoting leakage. Further, non-uniform distribution of misfit dislocations may introduce spatial variations in strain across the surface of the wafer. Moreover, making the upper strained semiconductor layer too thick may result in the relaxation of the layer, thereby negating the increase in carrier mobility provided by a strained layer.

SUMMARY

Misfit dislocations may create problems in devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs). The misfit dislocations may act as recombination centers in which electrons and holes combine. Further, misfit dislocations may create diffusion pipes for dopants, such as boron or arsenic, leading, e.g., to a short between a source and a drain. In both instances, the misfit dislocations may act as leakage paths, leading to poor device performance, characterized, for example, by high off currents (Ioff).

The present invention facilitates selection of the location of misfit dislocations between semiconductor layers, including at least one strained layer, to improve performance of devices fabricated on these layers. The misfit dislocations may be placed at a depth deep enough not to significantly affect device characteristics. The depth of the misfit dislocations is also shallow enough to avoid significantly relaxing the strained layer, thereby maintaining the carrier mobility enhancement provided by the strained layer. In accordance with the invention, a window is identified in which the thickness of the strained layer is thick enough so that the misfit dislocations are substantially removed from a device channel but thin enough to avoid carrier mobility degradation.

In an aspect, the invention features a method for selecting a placement of misfit dislocations, the method including forming a first layer over a substrate, the first layer having a first equilibrium lattice constant. A second layer is formed over the first layer, the second layer having (i) a second equilibrium lattice constant different from the first equilibrium lattice constant, and (ii) a critical thickness at which a plurality of misfit dislocations form at an interface proximate the second layer. A thickness of the second layer is selected to define a distance between a top surface of the second layer and the misfit dislocations that form at the interface corresponding to the selected placement of misfit dislocations when the thickness is equal to or greater than the critical thickness.

One or more of the following features may be included. The first layer may include a relaxed layer and/or a compressively strained layer and/or germanium. The second layer may include a tensilely strained layer and/or a compressively strained layer and/or silicon. The thickness of the second layer may be selected to reduce carrier recombination. A plurality of dopants may be introduced into a portion of the first layer, with the thickness of the second layer selected to reduce lateral diffusion piping of the dopants along the interface between the first layer and second layers.

At least one of a source and a drain region may be defined by introducing a plurality of dopants into a portion of the second layer, with a bottommost portion of the source or drain region being disposed at a preselected distance from the misfit dislocations at the interface. The preselected distance may be selected so that the source or drain is substantially free of misfit dislocations. The bottommost portion of the source or drain region may be disposed above the interface. The thickness of the second layer may be at least 1000 Å. The at least one of the source and drain regions may include an extension, and the misfit dislocations at the interface may be disposed (i) below the extension and (ii) above the bottommost portion of the source or drain region. The thickness of the second layer may be selected from the range comprising approximately 400 angstroms to 500 angstroms. Defining the source or drain region may include the introduction of the plurality of dopants by a single implantation step. The source and the drain regions cooperate to form a transistor.

A semiconductor layer may be formed over a portion of the second layer, so that at least a portion of the semiconductor layer is disposed over the source or drain region. The semiconductor layer may include at least one of a group II, a group III, a group IV, a group V, a group VI element, and combinations thereof. The thickness of the semiconductor layer may be selected so that the bottommost portion of the source or drain region is disposed above the preselected distance from the interface.

A metal layer may be formed over the semiconductor layer, and the substrate may be heated to form a contact layer including metal-semiconductor alloy, with the contact layer including at least a portion of the semiconductor layer and at least a portion of the metal layer. Forming the contact layer may include consuming substantially all of the semiconductor layer. Forming the contact layer may include consuming at least a portion of the second layer and/or only a portion of the semiconductor layer. The semiconductor layer may have a third equilibrium constant, and the third equilibrium constant may be substantially equal to the first equilibrium constant of the first layer.

In another aspect, the invention features a method for forming a semiconductor structure. The method includes the steps of forming a first layer over a substrate, the first layer having a first equilibrium lattice constant, and forming a second layer over the first layer, the second layer having (i) a second equilibrium lattice constant different from the first equilibrium lattice constant, and (ii) a critical thickness at which a plurality of misfit dislocations form at an interface proximate the second layer. A thickness of the second layer is selected to define a distance between a top surface of the second layer and the misfit dislocations that form at the interface such that a device formed over the second layer has an off current less than approximately 10−8Amperes/micrometer and a strained channel.

In another aspect, the invention features a method for placing misfit dislocations at a desired location within a semiconductor structure. A first layer is formed over a substrate, the first layer including a first material having a first equilibrium lattice constant. A second layer is formed over the first layer, the second layer including a second material having (i) a second equilibrium lattice constant different from the first equilibrium lattice constant, and (ii) a critical thickness at which a plurality of misfit dislocations form at an interface proximate the second layer. The first material, the second material, and a second layer thickness are selected to place the misfit dislocations at the desired location.

In another aspect, the invention features a semiconductor structure having a selected placement of misfit dislocations. The structure includes a first layer disposed over a substrate, the first layer having a first equilibrium lattice constant; and a second layer disposed over the first layer, the second layer having (i) a second equilibrium lattice constant different from the first equilibrium lattice constant, and (ii) a critical thickness at which a plurality of misfit dislocations form at an interface proximate the second layer. A thickness of the second layer is selected to define a distance between a top surface of the second layer and the misfit dislocations that form at the interface corresponding to the selected placement when the thickness is equal to or greater than the critical thickness.

One or more of the following features may be included. The first layer may include a relaxed layer and/or a compressively strained layer and/or germanium. The second layer may include a tensilely strained layer and/or silicon. The thickness of the second layer may be selected to reduce carrier recombination. A plurality of dopants may be disposed in a portion of the first layer, with the thickness of the second layer selected to reduce diffusion piping of the dopants out of the portion of the first layer.

A transistor may be formed over the second layer, the transistor including (i) a gate dielectric disposed over a portion of the second layer, (ii) a gate disposed over the gate dielectric, the gate comprising a conducting material, and (iii) a source and a drain disposed proximate the gate and extending into the second layer. The misfit dislocations may be disposed at a preselected distance from an interface between the gate dielectric and the second layer. The transistor may have an off current of less than 10−8Amperes/micrometer and a strained channel.

At least one of a source and a drain region may be defined in a portion of the second layer and may include a plurality of dopants, with the second layer having a thickness greater than the critical thickness and a bottommost portion of the source or drain region being disposed at a preselected distance from the misfit dislocations at the interface. The first layer may include a relaxed layer and/or a compressively strained layer and/or germanium. The second layer may include a tensilely strained layer and/or a compressively strained layer and/or silicon. The preselected distance may be selected so that the source or drain region is substantially free of misfit dislocations. Substantially all of the bottommost portion of the source or drain region may be substantially equidistant from a topmost portion of the source or drain region disposed in the second layer. At least one source and one drain may be defined in the portion of the second layer, and the source and the drain regions may cooperate to form a transistor.

A contact layer including a metal-semiconductor alloy may be disposed over a portion of the second layer. The contact layer may extend into the portion of the second layer.

A semiconductor layer may be disposed over the portion of the second layer, and a portion of the source or drain region may be disposed in the semiconductor layer. The semiconductor layer may include at least one of a group II, a group III, a group IV, a group V, a group VI element, and combinations thereof. The semiconductor layer may have a third equilibrium lattice constant substantially equal to the first equilibrium lattice constant. A contact layer including a metal-semiconductor alloy may be disposed over the semiconductor layer.

In another aspect, the invention features a semiconductor structure including a first layer disposed over a substrate, the first layer having a first equilibrium lattice constant; and a second layer disposed over the first layer, the second layer having (i) a second equilibrium lattice constant different from the first equilibrium lattice constant, and (ii) a critical thickness at which a plurality of misfit dislocations form at an interface proximate the second layer. A thickness of the second layer is selected to define a distance between a top surface of the second layer and the misfit dislocations that form at the interface such that a device formed over the second layer has an off current less than approximately 10−8Amperes/micrometer and a strained channel.

In another aspect, the invention features a method for selecting a placement of misfit dislocations. A first layer portion is formed over a substrate, the first layer having a first equilibrium lattice constant, and a regrowth layer is formed over the first layer portion, the regrowth layer having a regrowth equilibrium lattice constant different from the first equilibrium lattice constant. A plurality of misfit dislocations may form at an interface between the first layer portion and the regrowth layer. A second layer is formed over the regrowth layer. A thickness of the regrowth layer is selected to define a distance between a top surface of the second layer and the misfit dislocations corresponding to the selected placement of the misfit dislocations.

One or more of the following features may be included. The second layer may be strained. A lattice mismatch between the first equilibrium lattice constant and the regrowth layer may be less than about 0.04%, and the thickness of the regrowth layer may be less than about 450 nanometers (nm). The first layer may include a first germanium content, the regrowth layer may include a second germanium content, and the difference between the first germanium content and the second germanium content is less than about 1%.

A lattice mismatch between the first equilibrium lattice constant and the regrowth layer may be less than about 0.08%, and the thickness of the regrowth layer may be less than about 210 nm. The first layer may include a first germanium content, the regrowth layer may include a second germanium content, and the difference between the first germanium content and the second germanium content may be less than about 2%.

A lattice mismatch between the first equilibrium lattice constant and the regrowth layer may be less than about 0.12%, and the thickness of the regrowth layer may be less than about 130 nm. The first layer may include a first germanium content, the regrowth layer may include a second germanium content, and the difference between the first germanium content and the second germanium content may be less than about 3%.

In another aspect, the invention features a method for suppressing the formation of misfit dislocations. A first layer portion is formed over a substrate, the first layer having a first equilibrium lattice constant and a first composition. A regrowth layer is formed over the first layer portion, the regrowth layer having a regrowth equilibrium lattice constant and a regrowth composition. The formation of misfit dislocations at an interface between the first layer portion and the regrowth layer is suppressed by the selection of the first and regrowth equilibrium lattice constants and the first and regrowth compositions.

One or more of the following features may be included. The regrowth equilibrium lattice constant may be substantially identical to the first equilibrium lattice constant. The regrowth composition may be substantially identical to the first layer portion composition. A second layer may be grown over the regrowth layer. The second layer may be strained.

In another aspect, the invention features a semiconductor structure including a first layer portion disposed over a substrate, the first layer having a first equilibrium lattice constant. A regrowth layer is disposed over the first layer portion, the regrowth layer having a regrowth equilibrium lattice constant different from the first equilibrium lattice constant. A second layer is disposed over the regrowth layer. A plurality of misfit dislocations is disposed at an interface between the first layer portion and the regrowth layer, and the regrowth layer has a thickness selected to define a distance between a top surface of the second layer and the misfit dislocations.

The following feature may be included. The second layer may strained.

In another aspect, the invention features a semiconductor structure including a first layer portion disposed over a substrate, the first layer having a first equilibrium lattice constant, and a regrowth layer disposed over the first layer portion, the regrowth layer having a regrowth equilibrium lattice constant substantially identical to the first equilibrium lattice constant. A density of misfit dislocations disposed at an interface between the first layer portion and the regrowth layer is substantially zero per square centimeter.

One or more of the features may be included. A second layer may be disposed over the regrowth layer. The second layer may be strained.

In another aspect, the invention features a method for selecting a placement of a dislocation array. A substrate having a first equilibrium lattice constant is provided. A first layer is formed over the substrate, the first layer having a second equilibrium lattice constant. A thickness of the first layer is selected to define a distance between a top surface of the first layer and an interface between the first layer and the substrate. A dislocation array is disposed at the interface corresponding to the selected placement of the dislocation array.

One or more of the following features may be included. The first layer may be strained. The first equilibrium lattice constant may be substantially identical to the second equilibrium constant, and a composition of the first layer may be substantially identical to a composition of the substrate. In another aspect, the invention features a method for selecting a placement of a dislocation array. A substrate is provided having a first equilibrium lattice constant. A first layer is formed over the substrate, the first layer having a second equilibrium lattice constant. A thickness of the first layer is selected to define a distance between a top surface of the first layer and an interface between the first layer and the substrate. The misfit dislocations form at the interface and the thickness of the first layer is selected such that a device formed over the first layer has an off current less than 10−8Amperes/micrometer and a strained channel.

In another aspect, the invention features a semiconductor structure including a substrate having a first equilibrium lattice constant; and a first layer disposed over the substrate, the first layer having a second equilibrium lattice constant. A thickness of the first layer is selected to define a distance between a top surface of the first layer and an interface between the first layer and the substrate, a dislocation array is disposed at the interface, and the thickness of the first layer provides (i) an off current less than 10−8Amperes/micrometer and (ii) a strained channel in a device formed over the first layer.

The following feature may be included. A transistor may be formed over the first layer, the transistor including (i) a gate dielectric disposed over a portion of the first layer, (ii) a gate disposed over the gate dielectric, the gate comprising a conducting material, and (iii) a source and a drain disposed proximate the gate and extending into the first layer. The dislocation array may be disposed at a preselected distance from an interface between the gate dielectric and the first layer.

In another aspect, the invention features a semiconductor structure having a selected placement of a dislocation array. The structure includes a substrate having a first equilibrium lattice constant, and a first layer disposed over the substrate, the first layer having a second equilibrium lattice constant. A thickness of the first layer is selected to define a distance between a top surface of the first layer and the dislocation array that forms at the interface corresponding to the selected placement.

The following feature may be included. A transistor may be formed over the first layer, the transistor including (i) a gate dielectric disposed over a portion of the first layer, (ii) a gate disposed over the gate dielectric, the gate comprising a conducting material, and (iii) a source and a drain disposed proximate the gate and extending into the first layer. The dislocation array may be disposed at a preselected distance from an interface between the gate dielectric and the first layer.

DETAILED DESCRIPTION

Referring toFIG. 1, which illustrates an epitaxial wafer100amenable to use with the present invention, a strained layer102and a relaxed layer104are disposed over a substrate106. The ensuing discussion focuses on a strained layer102that is tensilely strained, but it is understood that strained layer102may be tensilely or compressively strained. Strained layer102has a lattice constant other than the equilibrium lattice constant of the material from which it is formed, and it may be tensilely or compressively strained; relaxed layer104has a lattice constant equal to the equilibrium lattice constant of the material from which it is formed. Tensilely strained layer102shares an interface108with relaxed layer104.

Substrate106and relaxed layer104may be formed from various materials systems, including various combinations of group II, group III, group IV, group V, and group VI elements. For example, each of substrate106and relaxed layer104may include a III-V compound. Substrate106may include gallium arsenide (GaAs), and relaxed layer104may include indium gallium arsenide (InGaAs) or aluminum gallium arsenide (AlGaAs). These examples are merely illustrative, and many other material systems are suitable.

In some embodiments, substrate106may include an insulator layer and/or a compositionally graded layer (not shown) above and/or below a semiconductor wafer. The graded layer may include Si and Ge with a grading rate of, for example, 10% Ge per micrometer (μm) of thickness, grown at, for example, at 600-1200° C. See, e.g., U.S. Pat. No. 5,221,413. In an embodiment, relaxed layer104may include Si1-xGexwith a uniform composition, containing, for example, Ge in the range 0.1≦x≦0.9 and having a thickness T1of, e.g., 0.2-2 μm. In an embodiment, T1is 1.5 μm.

Strained layer102may include a semiconductor such as at least one of a group II, a group III, a group IV, a group V, and a group VI element. Strained semiconductor layer102may include, for example, Si, Ge, SiGe, GaAs, indium phosphide (InP), and/or zinc selenide (ZnSe). In some embodiments, strained semiconductor layer102may include approximately 100% Ge, and may be compressively strained. A strained semiconductor layer102comprising 100% Ge may be formed over, e.g., relaxed layer104containing uniform Si1-xGexhaving a Ge content of, for example, 50-90% (i.e., x=0.5-0.9), preferably 70% (i.e., x=0.7).

Relaxed layer104and strained layer102may be formed by epitaxy, such as by atmospheric-pressure CVD (APCVD), low-(or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHVCVD), by molecular beam epitaxy (MBE), or by atomic layer deposition (ALD). Strained layer102containing Si may be formed by CVD with precursors such as silane, disilane, or trisilane. Strained layer102containing Ge may be formed by CVD with precursors such as germane or digermane. The epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. The growth system may also utilize a low-energy plasma to enhance layer growth kinetics.

In an embodiment in which strained layer102contains substantially 100% Si, strained layer102may be formed in a dedicated chamber of a deposition tool that is not exposed to Ge source gases, thereby avoiding cross-contamination and improving the quality of interface108between strained layer102and relaxed layer104. Furthermore, strained layer102may be formed from an isotopically pure silicon precursor(s). Isotopically pure Si has better thermal conductivity than conventional Si. Higher thermal conductivity may help dissipate heat from devices subsequently formed on strained layer102, thereby maintaining the enhanced carrier mobilities provided by strained layer102.

In some embodiments, relaxed layer104and/or strained layer102may be planarized by, e.g., CMP, to improve the quality of subsequent wafer bonding (see discussion below with reference toFIGS. 8-12). Strained layer102may have a low surface roughness, e.g., less than 0.5 nm root mean square (RMS).

Referring toFIG. 2, in an alternative embodiment, a substrate200is a semiconductor, such as silicon. Several layers collectively indicated at202are formed on substrate200. Layers202may be grown, for example, by APCVD, LPCVD, or UHVCVD.

Layers202include a graded layer204disposed over substrate200. Graded layer204may include Si and Ge with a grading rate of, for example, 10% Ge per μm of thickness, and a thickness T3of, for example, 2-9 μm. Graded layer204may be grown, for example, at 600-1200° C. Relaxed layer104is disposed over graded layer204. A virtual substrate206includes relaxed layer104and graded layer204.

A compressively strained layer208including a semiconductor material is disposed over relaxed layer104. In an embodiment, compressively strained layer208includes group IV elements, such as Si1-yGey, with a Ge content (y) higher than the Ge content (x) of relaxed Si1-xGexlayer104. Compressively strained layer208contains, for example, Ge in the range 0.25≦y≦1 and has a thickness T4of, e.g., 10-500 angstroms (Å). In some embodiments, compressively strained layer208has a thickness T4of less than 500 Å. In certain embodiments, T4is less than 200 Å.

Substrate200with layers202typically has a threading dislocation density of 104-105/cm2.

Referring toFIGS. 3aand3b, misfit dislocations may form under the following conditions.FIG. 3ais a schematic cross-sectional view of a local arrangement of atoms in, e.g., a Si thin film layer300on a Si1-xGexlayer310, andFIG. 3bis a three-dimensional view of the layers ofFIG. 3a, with atomic arrangements removed for clarity. The line Z-Z′ is common to both figures. Si layer300has a first equilibrium lattice constant a1, and is disposed over Si1-xGexlayer310having a second equilibrium lattice constant a2. An equilibrium lattice constant is the lattice constant of an unstrained material. Si has an equilibrium lattice constant a1of 5.431 Å and Ge has an equilibrium lattice constant of 5.658 Å, so the lattice mismatch between Si and Ge is approximately 4%. In embodiments with Ge content (x) of layer310greater than zero, therefore, second equilibrium lattice constant a2is greater than first equilibrium lattice constant a1. The mismatch between first and second equilibrium lattice constants a1, a2may result in the formation of a misfit dislocation320at an interface330between Si layer300and Si1-xGexlayer310. Misfit dislocation320has an associated first and second threading dislocation340,350at each of its two ends360,370. In the illustrated embodiment, first and second threading dislocations340,350each extend through Si layer300. In alternative embodiments, one or both of threading dislocations340,350may extend through Si1-xGexlayer310.

Analogously, referring toFIGS. 1 and 2, misfit dislocations may form at interface108between tensilely strained layer102and relaxed layer104as well as at interface210between tensilely strained layer102and compressively strained layer208. In each case, an equilibrium lattice constant of tensilely strained layer102including Si is less than an equilibrium lattice constant of relaxed layer104that includes Ge. This difference in equilibrium lattice constants between the two layers may lead to misfit dislocations forming at interface108or210proximate tensilely strained layer102.

Misfit dislocations may lead to carrier mobility degradation. In some embodiments, thickness T2of tensilely strained layer102may be as much as approximately three times Tcritfor misfit dislocation formation, without substantial carrier mobility degradation due to the misfit dislocations. For example, in an embodiment in which tensilely strained layer102includes strained silicon and is disposed over relaxed layer104including Si1-xGexhaving a Ge content of, for example, 20% Ge (i.e., x=0.2), Tcritmay be approximately 150 Å and T2may be approximately 450 Å without causing significant carrier mobility degradation.

Referring toFIG. 3c, adapted from F. R. N. Nabarro,Theory of Crystal Dislocations(1967) p. 33, incorporated by reference herein, an interface380between an upper first layer382and a bottom second layer384formed from crystalline material directly joined by, e.g., wafer bonding, may also contain screw dislocations, a result of in-plane rotation of the first and second layers382,384with respect to each other.FIG. 3cis a schematic top-view representation of atoms in the two layers382,384, with the upper layer382represented by open circles and the lower layer384represented by closed circles. Atoms from the upper layer382are bonded directly to atoms from the bottom layer across portions of interface380, e.g., in a first and a second coherent region390, as indicated by the perfect overlay of open and closed circles in these regions390. In coherent regions390, a lattice of the upper first layer382registers, i.e., aligns, with a lattice of the bottom second layer384. On the other hand, atoms in upper layer382may misregister with respect to atoms in bottom layers384to form screw dislocations392. Screw dislocations392are separated by a distance h, with the screw dislocations392forming a boundary394normal to interface380between upper and bottom layers382,384.

Referring toFIG. 4, a transistor400is formed on substrate106with tensilely strained layer102disposed over relaxed layer104. In an embodiment, tensilely strained layer102and relaxed layer104include Si and Si1-xGex, respectively, as described above with reference toFIGS. 1 and 2. Transistor400includes a gate dielectric410disposed over a portion412of tensilely strained layer102. Gate dielectric410may include, for example, thermally grown silicon dioxide. Transistor400also includes a gate414disposed over gate dielectric410. Gate414includes a conducting material, such as doped polycrystalline silicon. Transistor400further includes a source416and a drain418(defined, for purposes of illustration, by the interior boundaries). In an embodiment, source416and drain418are formed by the introduction of dopants into tensilely strained layer102and relaxed layer104. Source416has a source extension416aunderlying a first sidewall spacer420, and drain418has a drain extension418aunderlying a second sidewall spacer422. First and second sidewall spacers420,422are positioned proximate gate414, and may be formed from a dielectric material, such as silicon dioxide, silicon nitride, or a combination of both.

A depletion region450is disposed below source416, drain418as well as below gate410in a channel452of transistor400. In a typical CMOS device based on 130 nm technology, a depth d1of the depletion region450below gate dielectric410is approximately 200 Å. Channel452may be strained.

As discussed above, the difference in lattice constants between tensilely strained layer102and relaxed layer104may lead to the formation of misfit dislocations at interface108between tensilely strained layer102and relaxed layer104. By selecting a specific thickness T2of tensilely strained layer102, the placement of misfit dislocations at interface108may be controlled. A distance between misfit dislocations and a top surface424of tensilely strained layer102is thereby deliberately defined. In an embodiment in which a transistor, such as transistor400, is formed on tensilely strained layer102, this distance is equivalent to a distance between misfit dislocations and an interface426between gate dielectric410and tensilely strained layer102.

The positioning of interface108and misfit dislocations may be selected by taking into account the following options described below with reference to embodiments A-E illustrated inFIG. 4. In this discussion, thickness T2denotes a starting thickness of tensilely strained layer102as well as final thickness of tensilely strained layer102in the theoretical case where the thickness T2of tensilely strained layer102does not change during the fabrication of transistor400. Tcritis assumed to be 175 Å for this example, i.e., misfit dislocations start to form when T2≧175 Å.

In embodiment A, thickness T2of tensilely strained layer102is less than Tcrit, e.g., T2<175 Å. Here, no misfit dislocations form at interface108between tensilely strained layer102and relaxed layer104. The leakage that may be caused by misfit dislocations facilitating diffusion piping or acting as recombination-generation centers is thereby avoided. The low thickness T2of tensilely strained layer102, however, may present other device problems due to the close proximity of Ge (included in relaxed layer104) to the top surface424of tensilely strained layer102. Ge, for example, may present a challenge to the formation of metal silicide with low resistivity over source416and drain418. Further, the placement of bottom boundaries416b,418bof source416and drain418, as well as extensions416a,418a, in relaxed layer104containing Ge is an additional parameter to be considered during device design. Moreover, the extension of shallow trench isolation (STI) (not shown) into regions containing Ge requires modification—or complete revision—of processes conventionally used for forming STI in layers containing only Si.

In embodiment B, thickness T2of tensilely strained layer102extends to line B and therefore is slightly greater than Tcrit. Thickness T2is, for example, 190 Å. In this embodiment, misfit dislocations at interface108between tensilely strained layer102and relaxed layer104, therefore, intersect source extension416aand drain extension418a, as well as depletion region450in channel452. Misfit dislocations at interface108may lead to diffusion piping, with dopants from source extension416aand drain extension418adiffusing along misfit dislocations, possibly creating an electrical short between source extension416aand drain extension418a. Diffusion piping is especially likely in embodiment B because of the proximity of source extension416aand drain extension418a. A second effect of misfit dislocations in embodiment B is the possibility of the misfit dislocations acting as recombination-generation centers for carriers in the depletion region450in channel452. This recombination-generation, like diffusion piping, is a current sink and may increase Ioffof transistor400.

In embodiment C, thickness T2of tensilely strained layer102is greater than Tcrit, and is selected so that misfit dislocations in interface108are positioned below source extension416aand drain extension418a, but above bottom boundaries416b,418bof source416and drain418, respectively. T2may be, for example, approximately 400-500 Å. Because the distance between source416and drain418is greater than the distance between source extension416aand418a, the risk of diffusion piping occurring along misfit dislocations is reduced. Further, the number of misfit dislocations acting as recombination-generation centers may also be reduced in comparison to embodiment B because of the smaller depletion region450area intersected by misfit dislocations in embodiment C. Reduction in recombination-generation helps maintain a low Ioff, e.g., less than 10−8Amperes/↑m (A/μm). In some embodiments, Ioffis less than 10−10A/μm. Embodiment C may be, for some applications, the preferred embodiment.

In embodiment D, thickness T2of tensilely strained layer102is even greater than Tcrit, and tensilely strained layer102extends below bottom boundaries416b,418bof source416and drain418. T2is, for example, 1000 Å. This embodiment has the advantage of virtually eliminating the risk of diffusion piping because misfit dislocations do not intersect source416and drain418regions. An additional advantage of embodiment D is that the fabrication of transistor400entirely in tensilely strained layer102eliminates the need for reengineering source416and drain418junction depths and dopant profiles to take into account interaction with, e.g., Ge, in relaxed layer104. Finally, misfit dislocations at interface108are relatively far from surface424of tensilely strained layer102. This distance reduces spatial variation in strain that will occur at surface424and will reduce carrier mobility variation between a plurality of MOSFETs formed in tensilely strained layer102. A possible disadvantage of embodiment D, however, is a greater density of threading dislocations in tensilely strained layer102, induced by its greater thickness T2and greater density of misfit dislocations. Embodiment D may be desirable for certain applications.

In embodiment E, thickness T2of tensilely strained layer102is much greater than Tcrit, and tensilely strained layer102extends significantly below bottom boundaries416b,418bof source416and drain418, as well as below depletion region450. T2is, for example, greater than 2000 Å. Although embodiment E maintains the advantages of embodiment D, it also has a disadvantage. The misfit dislocation density is even greater, with a significant relaxation of tensile strain in tensilely strained layer102and an accompanying reduction in carrier mobilities. Moreover, the threading dislocation density is even greater in this embodiment.

The density of misfit dislocations at interface108depends not only on the thickness T2of tensilely strained layer102, but also on the difference in equilibrium lattice constants of materials forming tensilely strained layer102and an underlying layer, such as relaxed layer104. For example, a large difference in equilibrium lattice constants will result in the formation of misfit dislocations at interface108at a faster rate as thickness T2is increased above Tcritthan in an embodiment with a small difference in equilibrium lattice constants.

Referring also toFIG. 2, transistor400may also be formed on substrate200with layers202including compressively strained layer208disposed below tensilely strained layer102. Similar considerations are taken into account in the determination of optimal misfit dislocation placement as are discussed above with reference to a wafer having tensilely strained layer102disposed directly on relaxed layer104.

Referring toFIG. 5, in an alternative embodiment, the placement of source/drain regions with respect to misfit dislocations may be controlled in part by the formation of raised source and drain regions. For example, a transistor500may have a source region502and a drain region504each having a bottommost portion502a,504athat is disposed at a pre-selected distance d2from a dislocation array510. The dislocation array510is located at interface108between a first layer, such as relaxed layer104(or compressively strained layer208as shown inFIG. 2), having a first equilibrium lattice constant and a second layer, such as tensilely strained layer102, having (i) a second equilibrium lattice constant different from the first equilibrium lattice constant, and (ii) a thickness T2greater than critical thickness Tcritat which a plurality of misfit dislocations form at interface108proximate the second layer102. This embodiment is analogous to embodiment D (seeFIG. 4). Here, however, the placement of the source and drain502,504above the misfit dislocations510in interface108is not achieved by forming tensilely strained layer102with a thickness T2that is much greater than Tcrit, and thereby possibly having a greater density of threading dislocations in tensilely strained layer102. Rather, a semiconductor layer520is formed over the second layer, e.g., tensilely strained layer102, and source and drain regions502,504are effectively disposed both in doped portions of tensilely strained layer102and in semiconductor layer520.

More specifically, source and drain regions502,504may be defined as follows. A gate530, including a gate electrode532and a gate dielectric534, may be defined over tensilely strained layer102by, e.g., photolithography and etching. Gate electrode532may include polycrystalline silicon and gate dielectric534may include silicon dioxide. Source502and drain504, as indicated by boundaries BSand BD, are formed proximate gate530in tensilely strained layer102by, for example, ion implantation. The depths of source502and drain504in tensilely strained layer102are defined so that the bottommost portions502a,504aof source502and drain regions502,504, as bounded by boundaries BSand BD, are a preselected distance d2from interface108. In an embodiment, transistor500is an NMOS transistor, and source and drain regions502,504are formed by the implantation of n-type ions, such as arsenic. In an alternative embodiment, transistor500is a PMOS transistor, and source and drain regions502,504are formed by the implantation of p-type ions, such as boron.

Isolation regions (not shown) separate transistor500from adjacent devices. The isolation regions may be, for example, trenches filled with a dielectric material. A first and a second sidewall spacer536,538are formed proximate gate530. Sidewall spacers536,538are formed of a dielectric, e.g., silicon dioxide, silicon nitride, or a stack of both or other suitable materials.

Subsequently, semiconductor layer520is selectively formed over exposed semiconductor surfaces, such as silicon surfaces, i.e., on top surface540of gate electrode532, a top surface544of source502, and a top surface546of drain504. Semiconductor layer520will not form, however, over dielectric surfaces, such as over sidewall spacers536,538and isolation regions (not shown). In an embodiment, semiconductor layer520is an epitaxial layer. Semiconductor layer520may include a semiconductor material, such as group IV, II-VI, and III-V compounds. In some embodiments, semiconductor layer520may include, for example, silicon. The silicon of semiconductor layer520may be strained to the same extent that underlying tensilely strained layer102, also including silicon, is strained. In some embodiments, semiconductor layer520may have a third equilibrium lattice constant substantially equal to the first equilibrium lattice constant of the first layer, e.g., relaxed layer104. Then, layer520may be formed with an arbitrary thickness without creating new misfit dislocations at any interface. Semiconductor layer520has an initial thickness of, for example, approximately 100-400 Å. Semiconductor layer520has a low resistivity of, e.g., 0.001 ohm-cm that facilitates the formation of low-resistance contacts. To achieve this low resistivity, semiconductor layer520is, e.g., epitaxial silicon doped with, for example, arsenic to a concentration of 1020atoms/cm3. Semiconductor layer520may be doped in situ, during deposition. In alternative embodiments, semiconductor layer520may be doped after deposition by ion implantation or by gas-, plasma- or solid-source diffusion.

A metal layer is formed over transistor500. The metal layer may be formed by, for example, sputter deposition. The metal layer may have an initial thickness of, e.g., 50-200 Å and include a metal such as cobalt, titanium, tungsten, nickel, or platinum. The metal is selected to react with semiconductor layer520to form a low-resistance metal-semiconductor alloy when exposed to heat, as described below. The metal is also selected such that the metal-semiconductor alloy remains stable at temperatures typically required to complete transistor500fabrication, e.g., 400-700° C.

Subsequent to the deposition of the metal layer, a first rapid thermal anneal is performed, e.g., at 550° C. for 60 seconds. This heating step initiates a reaction between the metal layer and semiconductor layer520, forming a high resistivity phase of a metal-semiconductor alloy, e.g., cobalt silicide (CoSi). Portions of the metal layer are removed by a wet etch, such as sulfuric acid and hydrogen peroxide. In an alternative embodiment, the wet etch may be ammonium hydroxide, peroxide, and water. This wet etch removes the portions of the metal layer disposed over dielectric materials, such as over the first and second sidewall spacers536,538and the isolation regions. Portions of the metal layer disposed over semiconductor layer520remain in place after the anneal and wet etch.

Substrate200, including transistor500, may be subjected to a second heat treatment. For example, in an embodiment in which the metal layer includes cobalt, substrate200undergoes a rapid thermal anneal at 800° C. for 60 seconds in a nitrogen ambient. This heating step initiates a reaction in the metal-semiconductor alloy layer that substantially lowers its resistivity, to form a substantially homogeneous contact layer560. Contact layer560includes a metal-semiconductor alloy, e.g., a metal silicide such as a low resistivity phase of cobalt silicide (CoSi2). Contact layer560has a thickness T5of, for example, 400 Å. Contact layer560has a low sheet resistance, e.g., less than about 10 ohm/square, and enables a good quality contact to be made to source and drain regions502,504, as well as to gate530.

During formation, contact layer560consumes a portion of semiconductor layer520. After contact layer560formation, semiconductor layer520has a thickness T6of, e.g., 0-200 Å. The remaining portions of semiconductor layer520disposed over source and drain regions502,504include the same type of dopants as the source and drain regions502,504and, therefore, effectively function as portions of the source and drain regions502,504, respectively. In other words, the source and drain regions502,504may be disposed not only in portions of tensilely strained layer102and but also in portions of semiconductor layer520.

As noted above, the bottommost portions502a,504aof the source and drain regions502,504, bounded by boundaries Bs and BD respectively, are at preselected distance d2from the misfit dislocations510at interface108. In an embodiment, formation of conventional deep source/drain implants, which may result in source/drain regions intersecting substrate regions that contain misfit dislocations, may be avoided by the introduction of appropriate dopants into semiconductor layer520. The presence in semiconductor layer520of a second plurality of dopants of the same conductivity type as the dopants present in source and drain regions502,504results in portions of semiconductor layer520functioning as portions of source and drain regions502,504. In effect, portions of source and drain regions502,504are thereby raised above tensilely strained layer102. The distance d2of source and drain regions502,504above misfit dislocations may be selected by tailoring the thicknesses of semiconductor layer520and contact layer560, wherein increasing the thickness of semiconductor layer520allows the depth of source and drain regions502,504in tensilely strained layer102to be decreased and, in turn, distance d2of the bottommost portions502a,504aof these regions502,504from misfit dislocations to be increased. In summary, distance d2may be selected such that the source and drain regions502,504are substantially free of dislocations, thereby avoiding diffusion piping between these regions and enhancing transistor500performance.

Bottommost portions502a,504aof source and drain regions502,504, bound by boundaries BSand BD, may be substantially flat, such that substantially all of the bottommost portions502a,504ais substantially equidistant from a topmost portion502b,504bof source and drain region502,504, respectively, disposed within the second layer, e.g., tensilely strained layer102. This configuration is achieved by, for example, defining source and drain regions502,504with a single shallow implant, rather than with a conventional process in which both a shallow implant and a deep implant are performed to define source and drain regions.

Referring toFIG. 6as well as toFIG. 5, in some embodiments, formation of the metal-semiconductor alloy contact layer560may include complete consumption of semiconductor layer520, including consumption of misfit dislocations that may form at interface between semiconductor layer520and the second layer, e.g. tensilely strained layer102, if semiconductor layer520is lattice-mismatched with respect to the second layer. In some embodiments, as illustrated, formation of metal-semiconductor alloy may include consuming at least a portion of the second layer, e.g., tensilely strained layer102, including misfit dislocations that may form at the interface between semiconductor layer520and second layer102, thereby eliminating possible diffusion piping and/or current leakage paths induced by misfit dislocations along this interface.

In certain embodiments, relaxed layer104may be planarized prior to growth of strained layer102to eliminate a crosshatched surface roughness induced by graded buffer layer204(see, e.g., U.S. Pat. No. 6,593,641). Alternatively, relaxed layer104may be formed by the growth of a first relaxed layer portion104a, followed by planarization and subsequent growth of a regrowth layer104b, with an interface104cformed between the first relaxed layer portion104aand regrowth layer104b.

The formation of regrowth layer104bon planarized first relaxed layer portion104amay improve the quality of subsequent strained layer102growth by ensuring a clean surface for the growth of strained layer102. Growing on this clean surface may be preferable to growing strained material, e.g., silicon, on a surface that is possibly contaminated by oxygen and carbon from the planarization process. The conditions for epitaxy of the relaxed semiconductor regrowth layer104bon the planarized first relaxed layer portion104amay be chosen to minimize the surface roughness of the resulting structure, including of layers formed over regrowth layer104b.

In some embodiments, misfit dislocations may form at interface104c, e.g., because of slight differences in Ge content of first layer portion104aand regrowth layer104b. These misfit dislocations may adversely affect devices built on layers202. Two approaches may be taken to reduce the effect of misfit dislocations on devices. First, one may attempt to substantially avoid the formation of misfit dislocations at interface104c. The formation of misfit dislocations at interface104cmay be lowered to substantially zero dislocations per square centimeter by, e.g., forming regrowth layer104bwith a lattice constant substantially equal to a lattice constant of first relaxed layer portion104a. This may be achieved by, e.g., forming both first relaxed layer portion104aand regrowth layer104bwith a substantially same composition at substantially identical processing conditions, with an equilibrium lattice constant of first relaxed layer portion104abeing substantially equal to an equilibrium lattice constant of regrowth layer104b. For example, first relaxed layer portion104may be formed from Si1-xGexwith x selected from the range 0 to 1 inclusively, regrowth layer104bmay be formed from Si1-yGeywith y selected from the range 0 to 1 inclusively, and x being approximately equal to y. Alternatively, regrowth layer104bmay have a thickness T7that is less than a critical thickness, i.e., regrowth layer104bmay be strained. The critical thickness Tcritof a SiGe layer mismatched by a Ge fraction x can be estimated by the following formula:
Tcrit=(0.55/x)ln(10Tcrit),
where Tcritis given in nanometers. See, e.g., Houghton,Journal of Applied Physics,15 Aug. 1991, 2136-2151, incorporated by reference herein. For example, if first layer portion104aincludes Si0.80Ge0.20and regrowth layer104bincludes Si0.79Ge0.21or Si0.81Ge0.19, i.e., a difference in Ge content of about 1% and a lattice mismatch of about 0.04%, the critical thickness Tcritof regrowth layer104bmay be greater than 450 nm. Therefore, misfit dislocations at interface104cmay be avoided by keeping thickness T7of regrowth layer104bless than 450 nm, so that regrowth layer104bis strained. In another embodiment, first layer portion104amay include Si0.80Ge0.20and regrowth layer104bmay include Si0.78Ge0.22or Si0.82Ge0.18, i.e., a difference in Ge content of about 2% and a lattice mismatch of about 0.08%. The critical thickness Tcritof regrowth layer104bmay be greater than 210 nm. Therefore, misfit dislocations at interface104cmay be avoided by keeping thickness T7of regrowth layer104bless than 210 nm, so that regrowth layer104bis strained. In yet another embodiment, first layer portion104amay include Si0.80Ge0.20and regrowth layer104bmay include Si0.77Ge0.23or Si0.83Ge0.17, i.e., a difference in Ge content of about 3% and a lattice mismatch of about 0.12%. The critical thickness Tcritof regrowth layer104bmay be greater than 130 nm. Therefore, misfit dislocations at interface104cmay be avoided by keeping thickness T7of regrowth layer104bless than 130 nm, so that regrowth layer104bis strained. The decision regarding the selection of T7to ensure that regrowth layer104bis strained may be based on a historical behavior of a specific reactor in terms of accuracy and repeatability of films with specific Ge content.

In a second approach, the effect of misfit dislocations on devices subsequently built on layers202may be reduced by making the thickness T7of regrowth layer104bsufficiently thick to allow the devices, such as transistors, to be formed in strained layer102and regrowth layer104bentirely above interface104c. For example, in the example given above of first relaxed layer portion104aincluding Si0.79Ge0.21and regrowth layer104bincluding Si0.80Ge0.20, regrowth layer104bmay have a thickness T7that is much greater than the critical thickness of 450 nm, e.g., T7may be 1.5 μm. Assuming the typical device subsequently formed in strained layer102and regrowth layer104bextends less than 3000 Å-5000 Å into layers202, the device will be disposed above interface104cand will be substantially free of misfit dislocations.

Controlling the depth of an interface between two layers to control the placement of dislocations with respect to a device may also be accomplished with strained silicon-on-semiconductor (SSOS) substrates. An SSOS substrate may be formed as follows, as described in U.S. Ser. Nos. 10/456,708, 10/456,103, and 10/264,935, the entire disclosures of each of the three applications being incorporated by reference herein.

Referring toFIG. 8, a cleave plane800may be formed in epitaxial wafer100, such as strained layer102and relaxed layer104disposed over substrate106(seeFIG. 1). Strained layer102may have been formed at a relatively low temperature, e.g., less than 700° C., to facilitate the definition of abrupt interface108between strained layer102and relaxed layer104. This abrupt interface108may enhance the subsequent separation of strained layer102from relaxed layer104, as discussed below with reference toFIG. 9. Abrupt interface108is characterized by the transition of Si or Ge content (in this example) proceeding in at least 1 decade (order of magnitude in atomic concentration) per nanometer of depth into the sample. In an embodiment, this abruptness may be greater than 2 decades per nanometer.

Cleave plane800may be formed, for example, by the implantation of hydrogen ions into relaxed layer104. This implantation is similar to the SMARTCUT process described by, e.g., Bruel et al.,Proceedings1995IEEE International SOI Conference, October 1995, 178-179, incorporated by reference herein. Implantation parameters may include implantation of hydrogen (H2+) to a dose of 2.5-5×1016ions/cm2at an energy of, e.g., 50-100 keV. For example, H2+may be implanted at an energy of 75 keV and a dose of 4×1016ions/cm2through strained layer102into relaxed layer104. In alternative embodiments, it may be favorable to implant at energies less than 50 keV to decrease the depth of cleave plane800and decrease the amount of material subsequently removed during the cleaving process (see discussion below with reference toFIG. 8). In an alternative embodiment, other implanted species, such as H+or He+, may be used with the dose and energy being adjusted accordingly. The implantation may also be performed prior to the formation of strained layer102. Then, the subsequent growth of strained layer102is preferably performed at a temperature low enough to prevent premature cleaving along cleave plane800, i.e., prior to the wafer bonding process. This cleaving temperature is a complex function of the implanted species, implanted dose, and implanted material. Typically, premature cleaving may be avoided by maintaining a growth temperature below approximately 500° C.

Referring toFIG. 9, epitaxial wafer100is bonded to a crystalline handle wafer900. Handle wafer900may include a bulk semiconductor material, such as silicon.

Referring toFIG. 10as well as toFIG. 9, a split is induced at cleave plane800by annealing handle wafer900and epitaxial wafer100after they are bonded together. This split may be induced by an anneal at 300-700° C., e.g., 550° C., inducing hydrogen exfoliation layer transfer (i.e., along cleave plane800) and resulting in the formation of two separate wafers1000,1010. One of these wafers (1000) has a first portion1020of relaxed layer104disposed over strained layer102. Strained layer102is in contact with handle wafer900. The other of these wafers (1010) includes substrate106, and a remaining portion1030of relaxed layer104. In some embodiments, wafer splitting may be induced by mechanical force in addition to or instead of annealing. If necessary, wafer1000with strained layer102may be annealed further at 600-900° C., e.g., at a temperature greater than 800° C., to strengthen the bond between the strained layer102and handle wafer900. In some embodiments, this anneal is limited to an upper temperature of about 900° C. to avoid the destruction of a strained Si/relaxed SiGe heterojunction by diffusion.

Referring toFIG. 11as well as toFIG. 10, relaxed layer portion1020is removed from strained layer102. This removal could be accomplished by, for example, wet or dry etching. In an embodiment, removal of relaxed layer portion1020containing, e.g., SiGe, includes oxidizing the relaxed layer portion1020by wet (steam) oxidation. For example, at temperatures below approximately 800° C., such as temperatures between 600-750° C., wet oxidation will oxidize SiGe much more rapidly then Si, such that the oxidation front will effectively stop when it reaches the strained layer102, in embodiments in which strained layer102includes Si. The difference between wet oxidation rates of SiGe and Si may be even greater at lower temperatures, such as approximately 400° C.-600° C. Good oxidation selectivity is provided by this difference in oxidation rates, i.e., SiGe may be efficiently removed at low temperatures with oxidation stopping when strained layer102is reached. This wet oxidation results in the transformation of SiGe to a thermal insulator1100, e.g., SixGeyOz. The thermal insulator1100resulting from this oxidation is removed in a selective wet or dry etch, e.g., wet hydrofluoric acid. In some embodiments, it may be more economical to oxidize and strip several times, instead rather than just once.

In certain embodiments, wet oxidation may not completely remove the relaxed layer portion1020. Here, a localized rejection of Ge may occur during oxidation, resulting in the presence of a residual Ge-rich SiGe region at the oxidation front, on the order of, for example, several nanometers in lateral extent. A surface clean may be performed to remove this residual Ge. For example, the residual Ge may be removed by a dry oxidation at, e.g., 600° C., after the wet oxidation and strip described above. Another wet clean may be performed in conjunction with—or instead of—the dry oxidation. Examples of possible wet etches for removing residual Ge include a Piranha etch, i.e., a wet etch that is a mixture of sulfuric acid and hydrogen peroxide (H2SO4:H2O2) at a ratio of, for example, 3:1. An HF dip may be performed after the Piranha etch. Alternatively, an RCA SC1 clean may be used to remove the residual Ge. The process of Piranha or RCA SC1 etching and HF removal of resulting oxide may be repeated more than once. In an embodiment, relaxed layer portion including, e.g., SiGe, is removed by etching and annealing under a hydrochloric acid (HCl) ambient.

In the case of a strained Si layer102, the surface Ge concentration of the final strained Si surface is preferably less than about 1×1012atoms/cm2when measured by a technique such as total reflection x-ray fluorescence (TXRF) or the combination of vapor phase decomposition (VPD) with a spectroscopy technique such as graphite furnace atomic absorption spectroscopy (GFAAS) or inductively-coupled plasma mass spectroscopy (ICP-MS). In some embodiments, after cleaving, a planarization step or a wet oxidation step may be performed to remove a portion of the damaged relaxed layer portion1020as well as to increase the smoothness of its surface. A smoother surface may improve the uniformity of subsequent complete removal of a remainder of relaxed layer portion1020by, e.g., wet chemical etching. After removal of relaxed layer portion1020, strained layer102may be planarized. Planarization of strained layer102may be performed by, e.g., CMP; an anneal at a temperature greater than, for example, 800° C., in a hydrogen (H2) or hydrochloric acid (HCl) containing ambient; or cluster ion beam smoothing.

Referring toFIG. 12, after bonding and further processing (as described above), SSOS substrate1200is formed, having strained layer102disposed in contact with semiconductor handle wafer900. The strain of strained layer102is not induced by underlying handle wafer900, and is independent of any lattice mismatch between strained layer102and handle wafer900. In an embodiment, strained layer102and handle wafer900include the same semiconductor material, e.g., silicon. Handle wafer900may have a lattice constant equal to a lattice constant of strained layer102in the absence of strain. Strained layer102may have a strain greater than approximately 10−3. Strained layer102may have been formed by epitaxy, and may have a thickness T2ranging from approximately 20 Å to approximately 1000 Å, with a thickness uniformity of better than approximately ±10%. In an embodiment, strained layer102may have a thickness uniformity of better than approximately ±5%. Strained layer102may have a surface roughness of less than 20 Å.

Referring toFIG. 13as well as toFIG. 12, misfit dislocations may form at an interface1300between bonded strained layer102and handle wafer900. An additional array of screw dislocations may also arise from local incoherency of the crystalline lattices defined by strained layer102and handle wafer900across the bonded interface1300, the result of a slight rotation of strained layer102with respect to handle wafer900during the bonding process. Together, the misfit dislocations and screw dislocations located at interface1300form a dislocation array. By selecting a specific thickness T2of tensilely strained layer102, the distance between this dislocation array and a top surface1310of tensilely strained layer102is thereby deliberately defined. In an embodiment in which a transistor, such as transistor400, is formed on tensilely strained layer102, this distance is equivalent to a distance between the dislocation array and an interface1320between gate dielectric layer410and tensilely strained layer102. The positioning of interface1300and the dislocation array may be selected by taking into account the following options described below with reference to embodiments F-I illustrated inFIG. 13. In this discussion, thickness T2denotes a starting thickness of tensilely strained layer102as well as a final thickness of tensilely strained layer102in the theoretical case where the thickness T2of tensilely strained layer102does not change during the fabrication of transistor400. In embodiment F, thickness T2of tensilely strained layer102extends to line F, so that the dislocation array at interface1300between tensilely strained layer102and handle wafer900intersects source extension416aand drain extension418a, as well as depletion region450in channel452. The dislocation array at interface1300may lead to diffusion piping, with dopants from source extension416aand drain extension418adiffusing along the dislocation array, possibly creating an electrical short between source extension416aand drain extension418a. Diffusion piping is especially likely in embodiment F because of the proximity of source extension416aand drain extension418a. A second effect of the dislocation array in embodiment F is the possibility of the dislocations acting as recombination-generation centers for carriers in the depletion region450in channel452. This recombination-generation, like diffusion piping, is a current sink and may increase Ioffof transistor400.

In embodiment G, thickness T2of tensilely strained layer102is selected so that the dislocation array at interface1300are positioned below source extension416aand drain extension418a, but above bottom boundaries416b,418bof source416and drain418, respectively. T2may be, for example, approximately 400-500 Å. Because the distance between source416and drain418is greater than the distance between source extension416aand418a, the risk of diffusion piping occurring along dislocations is reduced. Further, the number of dislocations acting as recombination-generation centers may also be reduced in comparison to embodiment F because of the smaller depletion region450area intersected by the dislocation array in embodiment G. Reduction in recombination-generation helps maintain a low Ioff, e.g., less than 10−8A/μm. In some embodiments, Ioffis less than 10−10A/μm. Embodiment G may be, for some applications, the preferred embodiment.

In embodiment H, thickness T2of tensilely strained layer102is selected so that tensilely strained layer102extends below bottom boundaries416b,418bof source416and drain418. T2is, for example, 1000 Å. This embodiment has the advantage of virtually eliminating the risk of diffusion piping because dislocations do not intersect source416and drain418regions. Finally, misfit dislocations at interface1300are relatively far from surface1310of tensilely strained layer102. This distance reduces spatial variation in strain that will occur at surface1310and will reduce carrier mobility variation between a plurality of MOSFETs formed in tensilely strained layer102. A possible disadvantage of embodiment H, however, is a greater density of threading dislocations in tensilely strained layer102, induced by its greater thickness T2and greater density of misfit dislocations. Embodiment H may be desirable for certain applications.

In embodiment I, thickness T2of tensilely strained layer102is selected so that tensilely strained layer102extends significantly below bottom boundaries416b,418bof source416and drain418, as well as below depletion region450. T2is, for example, greater than 2000 Å. Although embodiment I maintains the advantages of embodiment H, it also has a disadvantage. The dislocation density is even greater, with a significant relaxation of tensile strain in tensilely strained layer102and an accompanying reduction in carrier mobilities. Moreover, the threading dislocation density is even greater in this embodiment.

In some embodiments, handle wafer900may have a first equilibrium lattice constant, tensilely strained layer102may have a second equilibrium lattice constant that is substantially identical to the first equilibrium lattice constant. Tensilely strained layer102may have a composition that is substantially identical to a composition of the substrate.

The invention may be embodied in other specific forms without departing from the spirit of essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein.