Image display

The present invention provides an image display capable of performing high-precision multi-gradation display while avoiding problems of a subtle noise and increase in a drive frequency. Display signal data of one frame is constructed by a plurality of sub frames of, for example, four sub frames 1/4 to 4/4. The 1/4 frame is set as an address period of an analog signal, the 2/4 frame is set as an analog gradation display period, the 3/4 frame is set as an address period of a digital signal, and the 4/4 frame is set as a digital gradation light emission period. The image display is constructed in such a manner that, in the analog gradation display period, an OLED device in a pixel emits light of time according to an analog signal voltage stored in a storage capacitor in the pixel by an analog drive signal circuit and, in the digital gradation display period, a binary light emitting operation of light emission and non light emission is performed according to a digital signal voltage stored in the storage capacitor by a digital signal driving circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention-relates to an image display capable of performing multi-gradation display and, more particularly, to an image display suitable for high gradation display.

2. Description of the Related Art

Referring toFIGS. 16 to 18, two conventional techniques will be described hereinbelow.

FIG. 16is a configuration diagram of a light emitting device using a first conventional technique (hereinbelow, called first conventional technique). Pixels205each having an organic electro-luminescent (EL) element204as a pixel light emitting material are disposed in a matrix in a display part. The pixels205are connected to external drive circuits via gate lines206, source lines207, power source lines208, and the like. In each pixel205, the source line207is connected to the gate of a power TFT203and one end of a storage capacitor202via a logic TFT (Thin-Film-Transistor)201, and one end of the power TFT203and the other end of the storage capacitor202are commonly connected to the power source line208.

The other end of the power TFT203is connected to a common power source terminal via the organic EL element204. One end of the gate line206is connected to a frame scanning circuit210, and one end of the source line207is connected to an analog signal voltage input circuit209. The logic TFT201and the power TFT203are formed by using polysilicon TFTs on an SiO2substrate.

The operation of the first conventional technique with such a configuration will now be described.

When the logic TFT201in a predetermined pixel row is opened/closed by the frame scanning circuit210via the gate line206, an analog signal voltage supplied from the analog signal voltage input circuit209to the source line207is supplied to the gate of the power TFT203and the storage capacitor202and held for a period of one frame until the next scan writing is performed. The power TFT203supplies an analog signal current according to the analog signal voltage to the organic EL element204. It makes the organic EL element204emit light with brightness corresponding to the analog signal voltage.

The first conventional technique is disclosed in detail in, for example, Japanese Unexamined Patent Application No. 8-241048. Although the term “organic electro-luminescent (EL) element” is used as the light emitting element in the above description of the conventional technique in accordance with the term used in the publication in the conventional technique, in recent years, the light emitting element is often called an OLED (Organic Light Emitting Diode) device. In the specification as well, the latter term will be used hereinbelow.

Referring now toFIGS. 17 and 18, another conventional technique will be described.

FIG. 17is a configuration diagram of a light emitting device using a second conventional technique (hereinbelow, called a second conventional technique). The structure of the second conventional technique is basically similar to the structure described in the first conventional technique except that a digital signal voltage input circuit211is provided in place of the analog signal voltage input circuit209and a sub frame scanning circuit212is provided in place of the frame scanning circuit210. Only the difference in operations due to the structural differences will be described.

Referring toFIG. 18, the operation of the second conventional technique will be described. As shown inFIG. 18, in the conventional technique, one frame period for displaying information of one frame is divided into a plurality of sub frame periods. Further, the sub frame period is constructed by an address period Ts as a period of writing a display signal to each pixel and each of sustain periods T1to Tn (to simplify explanation, n=5 inFIG. 18) for performing display with or without light emission in accordance with a written display signal. In the address periods Ts, the drive voltage of the OLED device is at the off level and light is not emitted. Although the operation of writing a display signal to each pixel in each address period is basically similar to that of the first conventional technique, the display signal is not an analog signal voltage but a digital signal voltage of two values of “high level” and “low level”.

Therefore, light emission of the OLED device in each of the sustain periods T1to T5subsequent to the address periods Ts is also digital light emission of “on” or “off”. As shown inFIG. 18, a time weight of the i-th power of 2 is assigned to each of the sustain periods T1to T5of the sub frames, so that a weight is assigned to each light emission bit. It enables gray scale display according to each of bits of digital data in the second conventional technique.

An advantage of the conventional technique is that since the power TFT203is used as a simple switch, a characteristic variation of the power TFT203such as a threshold voltage is not reflected in brightness at the time of light emission. In the conventional technique, consequently, an image can be displayed with small brightness variation and high picture quality. Such a conventional technique is disclosed in, for example, Japanese Unexamined Patent Application No. 2001-159878.

SUMMARY OF THE INVENTION

By extension of the conventional technique, it is difficult to provide an image display realizing multi-gradation display of six bits, eight bits, or the like required for use in a TV or the like in future as described hereinbelow.

In the first conventional technique shown inFIG. 16, the organic EL element204as a current driven element is driven by the power TFT203. The power TFT203functions as a current output element which receives a voltage. When a threshold voltage Vth of the power TFT203varies, a variation component is added to a signal voltage supplied. Consequently, a fixed brightness deviation occurs in each pixel.

Generally, as compared with a single crystal Si element, a TFT largely varies among elements. Particularly, in the case where a number of TFTs are formed like pixels, it is very difficult to suppress characteristic variations among elements. For example, in the case of a low-temperature polycrystalline silicon TFT, it is known that Vth varies on a volt unit basis. On the other hand, the light emission characteristic of the OLED device is generally sensitive to an input voltage. There is a case that light brightness varies about twice by a difference of the input voltage of 1V. Consequently, such a brightness deviation cannot be allowed in gray scale display. Therefore, in the first conventional technique, it is difficult to realize multi-gradation gray-scale display requiring accurate brightness control.

On the other hand, the second conventional technique described by referring toFIGS. 17 and 18intends to obtain an accurate brightness control by digitally controlling the OLED device of each pixel. However, to carry out such a digital control by using a number of bits for performing multi-gradation gray-scale display, the number of sub frames has to be increased. For example, in the case of 8-bit display, in addition to eight sustain periods T1to T8, eight address periods Ts corresponding to eight sub frames are necessary. Due to this, heavy burden is applied on a sub frame scanning circuit212and, as a result, it causes an increase in power consumption and cost.

In a display panel of a large size to some extent, the limitations of the time constant of the gate line206are seen, so that there is a physical upper limit on the sub frame scanning frequency.

As described above, by the second conventional technique, it is also difficult to increase the number of bits for multi-gradation gray-scale display from the viewpoint of driving.

In short, it is difficult to realize higher precision since the “analog signal” as in the first conventional technique is sensitive to a subtle noise and, on the other hand, since the “digital signal” as in the second conventional technique has to be divided into sub fields, the drive frequency has to be increased, and it becomes difficult to realize higher precision.

An object of the present invention is therefore to provide an image display in which the number of bits for multi-gradation display is increased.

Particularly, an object of the present invention is to provide an image display realizing high-precision multi-gradation display by using both “analog signal” and “digital signal” while avoiding the problem of a subtle noise and the problem of higher drive frequency.

It sounds that both existing “analog” and “digital” signals are simply used. However, the present invention is based on an idea quite different from the conventional idea of simply using both “analog” and “digital” signals. It will be briefly described hereinbelow.

The idea of using both the “digital” and “analog” signals in a conventional electronic circuit is just formation of a “digital circuit” and an “analog circuit” on a single silicon (Si) chip or module.

On the other hand, as long as the inventors herein know, conventional image displays are not based on an idea of realizing higher performance by inputting an “analog signal” to a “digital circuit” or driving an “analog circuit” by a “digital signal” as compared with the case where both of a “digital circuit” and an “analog circuit” are mounted on a single board. The present invention has been achieved by defying common sense and an idea of a different angle, realizing higher-precision and higher-gradation display which is not easily achieved by a single “digital circuit” or “analog circuit”, by allowing both an “analog signal” and a “digital signal” to coexist in a single circuit in consideration of a special boundary condition of a display such that a human visual characteristic senses a similar gray scale in each of digital display and analog display.

An example of representative means of the invention is as follows. According to the invention, there is provided an image display including: a display part constructed by a plurality of pixels; a signal line for writing display signal data on each of the pixels; write pixel selecting means for selecting a pixel to which the display signal data supplied to the signal line is written from the plurality of pixels; and signal data generating means for generating the display signal data, wherein the signal data generating means includes multivalue signal data generating means for generating display signal data having a multivalue level of three or more values, the display signal data constructing one frame is constructed by display signal data of a plurality of sub frames supplied to a group of pixels of the plurality of pixels to be displayed in the same frame period, and the display signal data in at least one of the sub frames in one frame has a multivalue level of at least three values, or a multivalue level of three or larger values.

Preferably, the write pixel selecting means is constructed by a polysilicon TFT.

The display signal data in the sub frame may have a multivalue level of three or more values.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of an image display according to the present invention will be described in detail hereinbelow with reference to the accompanying drawings.

First Embodiment

With reference toFIGS. 1 to 4, a first embodiment of an image display of the invention will be described. First, by referring toFIG. 1, the general configuration of the embodiment will be stated.

FIG. 1is a configuration diagram of an OLED display panel of the first embodiment. Pixels6each having an OLED device4as a pixel light emitting material are arranged in a matrix in a display part. Each pixel6is connected to predetermined peripheral drive circuits via a writing line9, an illuminating line10, a signal line7, a power source line8, and the like. The writing line9and illuminating line10are connected to a pixel selecting circuit11, and the signal line7is connected to an analog signal driving circuit12and a digital signal driving circuit16via a signal input switch13and is further connected to a delta wave input line15via a delta wave input switch14. All of the pixels6, pixel selecting circuit11, analog signal driving circuit12, and digital signal driving circuit16are formed on a glass substrate by using polysilicon TFTs.

In each pixel6, the signal line7is connected to the gate of a drive TFT2via a storage capacitor1, a source terminal of the drive TFT2is connected to the power source line8, and a drain terminal of the drive TFT2is connected to the OLED device4via an illuminating TFT5. A reset TFT3is provided between the gate and drain of the drive TFT2, the gate of the illuminating TFT Sis connected to the illuminating line10and the gate of the reset TFT3is connected to the writing line9. The drive TFT2is constructed as a part of an inverter having the OLED device4as a load, and the reset TFT3can be regarded as a switch for short-circuiting the input/output of the inverter.

Since the methods of fabricating the polysilicon TFT, the OLED device4and the like are similar to those generally reported, their description will not be given here. Regarding the OLED device4, for example, the first and second conventional techniques can be referred to.

As the configuration of the pixel selecting circuit11in the embodiment, generally, the circuit configuration which is known as a shift register is used, and reconstruction is possible within a range of general knowledge. As the analog signal driving circuit12, a general DA (digital-to-analog) converter in a polysilicon TFT panel is used. Alternately, a signal line analog driving circuit in a liquid crystal driver LSI or the like can be used. The digital signal driving circuit16is a parallel buffer circuit for buffering 1-bit input data and outputting the data.

In the embodiment, one frame period is divided into four phases. In practice, one frame is constructed by two sub frames each consisting of two phases. For convenience, the phases are named as the 1/4 frame to the 4/4 frame, and operations in the phases will be sequentially described by referring toFIGS. 2A and 2BandFIGS. 3A and 3B.

FIGS. 2A and 2Bare timing charts showing operations in the 1/4 frame and the 2/4 frame constructing the sub frame in the first half of one frame. In the 1/4 frame period ofFIG. 2A, the writing lines9and the illuminating lines10corresponding to pixel rows are sequentially scanned by the pixel selecting circuit11. For convenience, it is assumed that, in the timing chart, the wave risen state denotes an “on” state and, the wave fallen state denotes an “off” state. At this time, the signal input switch13is on and the delta wave input switch14is off. As the pixel selecting circuit11selects pixel rows A, B, C, . . . , an analog voltage signal is written by the analog signal output circuit12into the selected pixel6via the signal line7. Since it is designed that the analog signal consists of five bits in this case, there are32signal voltage levels. Subscripts A, B, and C of the writing lines9and illuminating lines10correspond to pixel rows in this case and similarly in the following.

In the 2/4 frame period ofFIG. 2B, the writing line9is set to be always off and the illuminating line10is set to be always on by the pixel selecting circuit11. At this time, the signal input switch13is off and the delta wave input switch14is on. Consequently, a delta wave as shown inFIG. 2Bis input from the delta wave input line15to all of pixels via the delta wave input switch14and the signal line7.

A pixel circuit operation of the embodiment in the sub frame will be described in more detail with reference toFIG. 1. A state such that when the reset TFT3and illuminating TFT5are turned on/off in a state where an analog signal voltage is applied to the signal line7, a gate voltage of an inverter constructed by the driving TFT2and the OLED device4becomes a threshold value of inversion of the inverter when the same analog signal voltage is input to the signal line7is stored in the storage capacitor1. This corresponds to writing of the analog signal voltage in the 1/4 frame period. Subsequently, in the 2/4 frame period, when a delta waveform including the written analog signal voltage value is input to the signal line7, the inverter of each pixel operates so that if the voltage on the signal line7is higher than a pre-stored analog signal voltage, a current is not passed to the OLED device4and if the voltage of the signal line7is lower than the pre-stored analog signal voltage, a current is passed to the OLED device4. By the operation, the light emission time of the OLED device is controlled by the written analog signal voltage, and variations in the inversion threshold value of the inverter due to the characteristic variations of the driving TFT2are also canceled.

The sub frame in the latter half will now be described.

FIGS. 3A and 3Bare timing charts showing the operations of the 3/4 frame and the 4/4 frame constructing the sub frame of the latter half. The operation in the3/4frame period inFIG. 3Ais basically the same as that in the 1/4 frame. The difference from the operation in the 1/4 frame in this case is that a voltage output to the signal line7is not the analog voltage from the analog signal voltage output circuit12but is a digital voltage output from the digital signal voltage output circuit16. As the pixel selecting circuit11sequentially selects the pixel rows A, B, C, . . . , a digital voltage signal of one of two values corresponding to “light emission” and “no light emission” is written from the digital signal output circuit16to the selected pixel6via the signal line7.

In the 4/4 frame period ofFIG. 3B, the writing line9is set to be always off and the illuminating line10is set to be always on by the pixel selecting circuit11. At this time, the signal input switch13is off and the delta wave input switch14is on. Consequently, an intermediate voltage of the digital signal voltage as shown inFIG. 3Bis applied from the delta wave input line15to all of pixels via the delta wave input switch14and the signal line7.

In this case, an inverter circuit of each pixel (hereinbelow, called a pixel inverter) operates so that when the intermediate voltage of the signal line7is higher than a pre-written digital signal voltage, a current is not passed to the OLED device4and, when the intermediate voltage is lower than the pre-written digital signal voltage, a current is passed to the OLED device4. By the operation, light emission of each OLED device4is determined by the stored digital signal voltage. Since either the on or off state of the pixel inverter is determined with reliability, an inversion error due to a parasitic effect and the like does not occur, which may occur in the 2/4 frame in which the inversion time of the pixel inverter is controlled. That is, in the 4/4 frame, extremely accurate light emission control can be expected. As a result, in the embodiment, light emission control with precision twice as high as that in the case where driving is made only by analog signal voltages can be realized.

FIG. 4shows the OLED drive sequence.FIG. 4shows an address period Ts, analog and digital gradation display periods, and on/off periods of the OLED driving corresponding to the analog and digital gradation display periods. The frame period is constructed by two sub frames of the first half and the latter half sub frames. The first-half sub frame consists of a 1/4 frame as an analog signal voltage address period and a 2/4 frame as an analog gradation display light emission period. The latter-half sub frame consists of a 3/4 frame as a digital signal voltage address period and a 4/4 frame as a digital gradation display light emission period.

The analog signal voltage is 5-bit data of 6-bit data except for the MSB (Most Significant Bit), and the digital signal voltage indicates MSB data. The gradation display in the analog gradation light emission period is controlled by 32 values by modulating light emission time. The gradation in the digital gradation light emission period is binary display of “light emission” and “non light emission”. The maximum light emission (ON) period of the analog gradation light emission period is equal to the digital gradation light emission period.

The foregoing embodiment can be variously changed without departing from the spirits of the present invention. For example, although a glass substrate is used as the TFT substrate in the embodiment, in place of the TFT substrate, another transparent insulating substrate such as a quartz substrate or a transparent plastic substrate can be used. When it is arranged to emit light of the OLED device4from the top face, an opaque substrate can be also used.

Although only p-channel pixel TFTs are used in the embodiment, by properly changing a drive waveform, n-channel TFTs or CMOS switch can be used. The pixel inverter is not limited to the inverter constructed by the drive TFT2and the OLED device4but, obviously, a configuration of a CMOS inverter or a constant current source circuit using an n-channel TFT as a load can be also employed.

In the description of the embodiment, the number of pixels, the panel size, and the like are not mentioned purposely for the reason that the invention is not limited by such specifications and formats. Although the display signal voltage is set to have 64 grades (6 bits), the higher gradation is also possible and, on the contrary, the gradation precision can be also easily decreased. Specifically, when k bits from the most significant bit (MSB) out of the m bits are used as binary display signal data for 2mgradation display of m bits, (m-k) bits become a signal used for the analog gradation display. In the embodiment, it corresponds to the case where m=6 and k=1. Therefore, it is sufficient to change m and k in accordance with necessary gradation.

In the embodiment, the peripheral driving circuits which are the pixel selecting circuit11, analog signal driving circuit12, and digital signal driving circuit16are constructed by low-temperature polysilicon TFT circuits. It is in the scope of the present invention that the peripheral driving circuits or a part of the circuits are constructed by a single-crystal-LSI (Large Scale Integrated circuit). In addition, the delta wave generating circuit or the like can be also constructed by a low-temperature polysilicon TFT circuit.

In the foregoing embodiment, the OLED device4is used as a light emitting device. Obviously, the invention can be realized by using a general light emitting device made of other inorganic material in place of the OLED device4.

The above-described various modifications and the like can be basically similarly applied to not only the foregoing embodiment but also other embodiments described hereinbelow.

Second Embodiment

A second embodiment of the invention will be described by referring toFIGS. 5 and 6.FIG. 5is a configuration diagram of an OLED display panel of the second embodiment. Pixels25each having an OLED device24as a pixel light emitting material are arranged in a matrix in a display part. Each pixel25is connected to peripheral drive circuits via a gate line26, a signal line27, a power source line28, and the like.

In each pixel25, the signal line27is connected to the gate of a drive TFT23and one end of a storage capacitor22via an input TFT21, and one end of the drive TFT23and the other end of the storage capacitor22are commonly connected to the power source line28. The other end of the drive TFT23is connected to a common power source terminal via the OLED device24. On the other hand, one end of the gate lien26is connected to a gate scanning circuit30, and one end of the signal line27is connected to an analog signal driving circuit29and a digital signal driving circuit31. The input TFT21, drive TFT23, gate scanning circuit30, analog signal driving circuit29, and digital signal driving circuit31are formed by using polysilicon TFTs on a glass substrate.

The operation of the OLED display panel in the embodiment will be described hereinbelow. In the embodiment, one frame is constructed by two sub frames. For easier understanding, the following description will be given by calling the first sub frame a 1/2 frame and calling the second sub frame a 2/2 frame.

In a writing period of the 1/2 frame, the analog signal driving circuit29is activated to output an analog signal voltage and, on the other hand, the digital signal driving circuit31is made inactive and an output impedance becomes extremely high. When the gate scanning circuit30scans the input TFT21in a predetermined pixel row via the gate line26, an analog signal voltage supplied from the analog signal driving circuit29to the signal line27is input to the gate of the driving TFT23and storage capacitor22, and held for one sub frame period until the next scanning operation is performed. During the period, the drive TFT23passes an analog signal current according to the analog signal voltage to the OLED device24, and the OLED device24emits light with analog brightness corresponding to the analog signal voltage. In this case, the analog signal voltage is a signal of 32 grades corresponding to five bits.

In the 2/2 frame writing period, the digital signal driving circuit31is activated to output a digital signal voltage and, on the other hand, the analog signal driving circuit29is made inactive, and an output impedance becomes extremely high. When the gate scanning circuit30scans again the input TFT21in a predetermined pixel row via the gate line26, the digital signal voltage supplied from the digital signal driving circuit31to the signal line27is input to the gate of the drive TFT23and the storage capacitor22and held for one sub frame period until the next scan writing is performed. During the period, the drive TFT23passes the digital signal current according to the digital signal to the OLED device24and the OLED device24emits light or does not emit light in accordance with the digital signal. In this case, the digital signal is an ON or OFF signal corresponding to one bit of the MSB.

In the embodiment as well, the OLED device24at the time of digital driving can be turned on or off with reliability. Thus, a light emission brightness error due to a characteristic variation such as a threshold variation in the drive TFT23, which is concerned at the time of analog driving does not occur. In other words, in the 2/2 frame, extremely accurate light emission control can be expected. As a result, in the embodiment, light emission control with precision twice as high as that in the case of performing driving only by the analog signal voltage driving can be realized.

FIG. 6shows the driving sequence.FIG. 6shows analog and digital gradation display periods corresponding to scanning lines in one frame, and brightness of OLEDs in the first row. The frame period is constructed by two sub frames of the first-half and latter-half sub frames. The first-half sub frame is a 1/2 frame as an analog signal voltage address period, and the latter-half sub frame is a 2/2 frame as a digital signal voltage address period. The analog signal voltage is 5-bit data except for the MSB of 6-bit data, and the digital signal voltage is MSB data. The gradation display in the analog gradation display light emission period is controlled by modulating the light emission brightness. The grade in the digital gradation display light emission period is indicated by binary data of light emission and non light emission. The analog gradation display light emission period is set to have the same length as the digital gradation display light emission period.

Although the brightness variation at the time of analog gradation light emission is larger than that in the first embodiment, the second embodiment has an advantage such that the pixel configuration is simple.

A method of canceling a threshold voltage variation of the drive TFT23by introducing an offset canceling (auto zero) circuit in the analog signal voltage driving period as in the second embodiment is known. Such a method is described in, for example, “Technical digest of SID 98”, pp. 11 to 14 (1998) (called a third conventional technique). By combining the offset canceling technique of the third conventional technique to the second embodiment, multi-gradation display with smaller brightness variation can be realized and display with similar high precision while using a TFT of larger characteristic variation can be also realized.

Third Embodiment

A third embodiment of the present invention will be described with reference toFIGS. 7 and 8.FIG. 7is a configuration diagram of a liquid crystal display panel of the third embodiment. Pixels34each having a liquid crystal capacitor33as an optical characteristic modulation device are arranged in a matrix in a display part. The pixels34are connected to peripheral driving circuits via gate lines36and signal lines35.

In each pixel34, the signal line35is connected to one end of the liquid crystal capacitor33via an input TFT32, and the other end of the liquid crystal capacitor33is connected to a common power source terminal. On the other hand, one end of the gate line36is connected to a gate scanning circuit38, and one end of the signal line35is connected to an analog signal driving circuit37and a digital signal driving circuit39. The input TFT32, gate scanning circuit38, analog signal driving circuit37, and digital signal driving circuit39are formed on a glass substrate by using polysilicon TFTs. In the embodiment, a display panel is constructed in such a manner that a back light is provided on the back face of the glass substrate, and a counter glass substrate on which a counter electrode of the liquid crystal capacitor and a color filter are formed is assembled. The structure is a general one, so that its detailed description will not be given here.

The operation of the third embodiment will be described hereinbelow. In the embodiment, one frame is constructed by three sub frames. For easier understanding, the following description will be given by calling the first sub frame a 1/3 frame, calling the second sub frame a 2/3 frame, and calling the third sub frame a 3/3 frame.

First, in a writing period of the 1/3 frame, the analog signal driving circuit37is activated to output an analog signal voltage and, on the other hand, the digital signal driving circuit39is made inactive and an output impedance becomes extremely high. When the gate scanning circuit38scans the input TFT32in a predetermined pixel row via the gate line36, an analog signal voltage supplied from the analog signal driving circuit37to the signal line35is input to the liquid crystal capacitor33and held for one sub frame period until the next scanning operation is started. During the period, the liquid crystal capacitor33applies an analog signal field corresponding to the written analog signal voltage to a liquid crystal layer, and the liquid crystal layer produces a predetermined optical characteristic modulation effect. In this case, the analog signal voltage is a signal of 16 grades corresponding to four bits.

In the 2/3 frame writing period, the digital signal driving circuit39is activated to output a digital signal voltage and, on the other hand, the analog signal driving circuit37is made inactive,and an output impedance becomes extremely high. When the gate scanning circuit38scans again the input TFT21in a predetermined pixel row via the gate line36, the digital signal voltage supplied from the digital signal driving circuit39to the signal line35is input to the liquid crystal capacitor33and held for one sub frame period until the next scan writing is started. During the period, the liquid crystal capacitor33applies a digital signal field corresponding to the written digital signal voltage to the liquid crystal layer and the liquid crystal layer shows an optical transmission state or a non-transmission state in accordance with the digital signal. In this case, the digital signal is an ON or OFF signal corresponding to one bit of the MSB.

In the writing period of the 3/3 frame as well, the digital signal driving circuit39is activated to output a digital signal voltage and, on the other hand, the analog signal driving circuit37is made inactive so that an output impedance becomes extremely high. When the gate scanning circuit38scans again the input TFT21in a predetermined pixel row via the gate line36, the digital signal voltage supplied from the digital signal driving circuit39to the signal line35is input to the liquid crystal capacitor33and held for one sub frame period until the next scan writing is started. During the period, the liquid crystal capacitor33applies a digital signal field corresponding to the written digital signal voltage to the liquid crystal layer and the liquid crystal layer shows an optical transmission state or a non-transmission state in accordance with the digital signal. In this case, the digital signal is an ON or OFF signal corresponding to the next one bit of the MSB.

In the embodiment as well, the liquid crystal capacitor33in the 2/3 and 3/3 frames of digital driving is selected in the on and off state with reliability, so that a modulation brightness error due to a field through charge in the input TFT32which is concerned at the time of analog driving does not occur. In other words, in the 2/3 and 3/3 frames, extremely accurate light emission control can be expected. As a result, in the embodiment, light emission control with precision four times as high as that in the case of driving is made only by the analog signal voltage can be realized.

FIG. 8shows the driving sequence.FIG. 8shows analog and digital gradation display periods corresponding to scanning line driving in one frame, and illumination of pixels in the first row. The frame period consists of three sub frames. The first sub frame is a 1/3 frame as an analog signal voltage address period, and the following two sub frames are 2/3 and 3/3 frames as a digital signal voltage address period. The analog signal voltage is 4-bit data except for two bits from the MSB out of data of total six bits, and the digital signal voltage is MSB data and 1-bit data next to the MSB.

The gradation display in the analog gradation light emission period is controlled by analog-modulating the optical characteristic of the liquid crystal layer, and the grade in the digital gradation light emission period is indicated by binary data of “light-emission” and “non light emission”. The analog gradation display period of the 1/3 frame is set to have the same length as the digital gradation display period2of the 3/3 frame, which is the half of the digital gradation display period1of the 2/3 frame.

The reason why the digital gradation display period corresponding to the most significant bit is set as the 2/3 frame which is in the middle of the three sub frames with respect to time is as follows. It is known that when the center of gravity of a time base of the light emission (transmission) period fluctuates according to the display grade, a false signal called a false contouring is generated. To lessen the generation, the most significant bit of the longest light emission period is disposed in the center portion of the frame.

In the embodiment, the analog signal consists of four bits and the digital signal consists of two bits. The number of bits can be properly changed according to required specifications. The larger the number of bits of the digital signal is, the higher the gradation precision is. However, increase in the number of sub frames causes increase in a panel drive frequency. Consequently, it is desirable to select the number of bits according to a use. Further, in the case of a liquid crystal panel as in the embodiment, there is generally a problem of speed of response. Increase in the sub frames is limited from the view point of speed of response of the liquid crystal layer.

Obviously, change in the number of bits of a digital signal is not limited to the liquid crystal display panel as in the embodiment but can be also applied to a light emission display panel as described in the foregoing first and second embodiments.

Fourth Embodiment

With reference toFIGS. 9 to 12, a fourth embodiment of the invention will be described. First, by referring toFIG. 9, the general configuration of the fourth embodiment will be stated.

FIG. 9is a configuration diagram of an OLED display panel of the fourth embodiment. Pixels47each having an OLED device44as a pixel light emitting material are arranged in a matrix in a display part. The pixels47are connected to predetermined peripheral drive circuits via writing line50, reset lines52, display lines51, signal lines48, power source lines49, and the like. The writing lines50, reset lines52, and display lines51are connected to a pixel selecting circuit53, and the signal lines48are connected to an analog signal driving circuit54and a digital signal driving circuit55. All of the pixels47, pixel selecting circuit53, analog signal driving circuit54, and digital signal driving circuit55are formed on a glass substrate by using polysilicon TFTS.

In each pixel47, the signal line48is connected to the gate of a drive TFT46via an input TFT41and a storage capacitor42, and a source terminal of the drive TFT46is connected to the input TFT41and one end of a display TFT45. Multiple ends of the display TFT45are connected to the power source line49. The drain terminal of the drive TFT46is connected to an OLED device44. A reset TFT43is provided between the drain terminal and the gate terminal of the drive TFT46, the gate of the input TFT41is connected to the writing line50, the gate of the reset TFT43is connected to the reset line52, and the gate of the display TFT45is connected to the display line51.

The basic role of the analog signal driving circuit54and that of the digital signal driving circuit55are similar to that in the analog signal driving circuit12and that in the digital signal driving circuit16in the first embodiment except that an output is not a signal voltage but is a signal current in the fourth embodiment. Consequently, in a signal output part of each of the analog signal driving circuit54and the digital signal driving circuit55, a TFT connected to a current source is used.

In the embodiment, one frame period is divided into four phases. In practice, one frame is constructed by two sub frames each consisting of two phases. For convenience, the phases are named as the 1/4 frame to the 4/4 frame, and operations in the phases will be sequentially described by referring toFIGS. 10 and 11.

FIG. 10is a timing chart showing operations in the 1/4 frame constructing the sub frame in the first half of one frame. In the 1/4 frame period, the writing lines50and the reset lines52corresponding to pixel rows are sequentially scanned by the pixel selecting circuit53. During the period, the display lines51are off all the time. As the pixel selecting circuit53selects pixel rows A, B, C, . . . , an analog signal current is written by the analog signal output circuit54into the selected pixel47via the signal line48. Since it is designed that the analog signal consists of five bits in this case, there are32signal current levels. Subsequently, in the 2/4 frame period (not shown), when the display lines51are turned on, a light emission power is supplied to each pixel.

A pixel circuit operation in the sub frame will now be described in more detail with reference toFIG. 9. When the input TFT41and the reset TFT43are turned on/off in a state where an analog signal current is applied to the signal line48, the same signal current as that supplied to the signal line48is passed to the OLED device44via the drive TFT46. Since a voltage across the gate and source of the drive TFT46is applied to both ends of the storage capacitor42, at the time point the reset TFT43is turned off, the condition of the voltage across the gate and source is stored in both ends of the storage capacitor42. This is the writing of the analog signal current in the 1/4 frame period.

Subsequently, in the 2/4 frame period, the display line51is turned on and, accordingly, the drive TFT46is turned on again. An amount of current passed to the drive TFT46at this time is determined by the condition of the voltage across the gate and source preliminarily stored in the storage capacitor42, so that it is equal to the analog signal current value input to the pixel in the frame 1/4. Therefore, the drive current of the OLED element44is controlled by the pre-stored analog signal current, and a light emission current amount is simultaneously controlled.

The sub frame in the latter half will now be described.FIG. 11is a timing chart showing the operations of the 3/4 frame constructing the sub frame of the latter half. The operation in the 3/4 frame period is basically the same as that in the 1/4 frame. The difference from the operation in the 1/4 frame in this case is that a current supplied to the signal line48is not an analog current from the analog signal current driving circuit54but is a digital current output from the digital signal driving circuit55. As the pixel selecting circuit53sequentially selects the pixel rows A, B, C, . . . , a digital current signal of one of two values corresponding to “light emission” and “no light emission” is written from the digital signal driving circuit55to the selected pixel47via the signal line48. In the 4/4 frame period (not shown), the display line51is turned on again, thereby supplying the light emission power to each pixel.

FIG. 12shows the drive sequence.FIG. 12shows an address period Ts, analog and digital gradation display periods, and on/off periods of the OLED driving and the display line51corresponding to the analog and digital gradation display periods. The frame period is constructed by two sub frames of the first half and the latter half sub frames. The first-half sub frame consists of a 1/4 frame as an analog signal current address period and a 2/4 frame as an analog gradation display light emission period. The latter-half sub frame consists of a 3/4 frame as a digital signal current address period and a 4/4 frame as a digital gradation display light emission period. The analog signal current is 5-bit data except for the LSB (Least Significant Bit) out of data of total six bits, and the digital signal voltage indicates LSB data. The gradation display in the analog gradation display light emission period is controlled by 32 values by modulating light emission time. The gradation in the digital gradation display light emission period is binary display of “light emission” and “non light emission”. The digital gradation light emission period is a period of1/64of the analog gradation light emission period.

The circuit configuration itself of the pixel47in the embodiment is an already known technique and its details are described in “Technical Digest of International Electron Device Meeting 98”, pp. 875-878 (1998) (hereinbelow, called a fourth conventional technique) and the like. In the case of the fourth conventional technique, the gradation of light emission luminance is controlled only by an analog signal current. The fourth conventional technique has, however, a problem such that when the value of the analog signal current becomes small, a signal current cannot be accurately written into the pixel. When the value of the analog signal current is small, it takes time to charge or discharge parasitic capacitance in a signal line, and an image signal cannot be written at a frame rate at which a moving image can be displayed in reality.

For example, in the case of assuming an OLED panel of about 2 inches, a parasitic capacitance between a writing line and a pixel, which is estimated at least about 4 pF occurs in a signal line in a normal design. When it is assumed that the minimum signal current value is 20 nA and a write voltage is 1V, 200 μsec is necessary to charge/discharge the parasitic capacitance. When the rate is 60 frames per second, the maximum number of pixel rows is only 83.

In contrast, in the embodiment, since the maximum least bit (LSB), that is, the minimum bit is input as the digital current signal, the signal current value is equal to the maximum analog signal current value. Therefore, writing by a substantial minimum signal current value is necessary for the second bit from the LSB, so that the minimum current value is 40 nA in the above example of the numerical values. In the case of the embodiment, therefore, the maximum number of pixel rows can be increased to 166 under the same condition.

Although the digital gradation is applied only to the LSB in the embodiment, by applying the digital gradation to a plurality of bits from the LSB, a display panel of a larger number of pixels, a larger size, or a larger number of grades can be also realized. Specifically, when n bits from the least significant bit (LSB) out of the m bits are used as binary display signal data for 2mgradation display by m bits, (m-n) bits are D/A converted and becomes a signal used for analog gradation display. In the embodiment, it corresponds to the case where m=6 and n=1. Therefore, it is sufficient to change m and n in accordance with necessary gradation. In the case of increasing “n”, attention has to be paid since the number of sub frames also increases.

Fifth Embodiment

With reference toFIGS. 13 and 14, a fifth embodiment of the invention will be described. First, by referring toFIG. 13, the general configuration of the embodiment will be stated.

FIG. 13is a configuration diagram of an OLED display panel of the fifth embodiment. The pixels47each having an OLED device44as a pixel light emitting material are arranged in a matrix in a display part. Each pixel47is connected to predetermined peripheral drive circuits via writing line50, reset line52, display line51, signal line48, power source line49, and the like. The writing lines50, reset lines52, and display lines51are connected to the pixel selecting circuit53, and the signal lines48are connected to a multivalue signal driving circuit60. All of the pixels47, pixel selecting circuit53, and multivalue signal driving circuit60are formed on a glass substrate by using polysilicon TFTS. In each pixel47, the signal line48is connected to the gate of the drive TFT46via the input TFT41and the storage capacitor42, and the source terminal of the drive TFT46is connected to the input TFT41and one end of a display TFT45.

Multiple ends of the display TFT45are connected to the power source line49. The drain terminal of the drive TFT46is connected to the OLED device44. The reset TFT43is provided between the drain terminal and the gate terminal of the drive TFT46, the gate of the input TFT41is connected to the writing line50, the gate of the reset TFT43is connected to the reset line52, and the gate of the display TFT45is connected to the display line51.

The basic role of the multivalue signal driving circuit60is to output signal currents of multiple values, and a TFT connected to a current source is added to a signal output part in a generally known multivalue signal voltage output circuit.

In the embodiment, one frame period is divided into four phases. In practice, one frame is constructed by two sub frames each consisting of two phases. For convenience, the phases are named as the 1/4 frame to the 4/4 frame. Since the operation of the fifth embodiment is similar to that of the fourth embodiment already described by referring toFIGS. 10 and 11except that the levels of a signal current passed to the signal line48are eight grades including 0 in the 1/4 and 3/4 frames, its description will not be repeated.

FIG. 14shows the drive sequence in the fifth embodiment.FIG. 14shows the address period Ts, an upper bits data driving period of a time weight of 8, a lower bits digital data driving period of a time weight of 1, and an on/off period of 8-level data OLED driving and the display line51.

The frame period is constructed by two sub frames of the first half and the latter half sub frames. The first-half sub frame expresses data of upper three bits by light emission brightness of the 8-level OLED device44, and the latter-half sub frame expresses data of lower three bits by light emission brightness of the 8-level OLED device44. The first-half sub frame consists of a 1/4 frame as a multivalue signal current address period of the upper three bits and a 2/4 frame as a multi-grade light emission period of upper three bits. The latter-half sub frame consists of a 3/4 frame as a multivalue signal current address period of lower three bits and a 4/4 frame as a multi-grade light emission period of lower three bits.

In this case, the sub frame of the first half can be regarded as upper-bit display in a 2-bit octal number, and the sub frame of the latter half can be regarded as lower-bit display in the 2-bit octal number. Therefore, in the light emission periods of the 2/4 and 4/4 frames, a time weight of 8 times corresponding to the octal number is assigned.

In the embodiment as well, there are an advantage such that the minimum write current value in the multivalue signal current can be a large value, and an advantage such that a signal current can be accurately written into a pixel. In the case of using only a normal analog signal current, for example, signal current writing of 64 grades is necessary. In contrast, in the fifth embodiment, signal current writing of 8 grades is sufficient.

Although display of 64 grades by a eight-bit octal number is realized in the fifth embodiment, the invention is not limited to the specific values. In other words, a combination of y bits in x notation may be employed. For example, 64 gradations can be realized by employing a three-bit tetral number, 256 gradations can be realized by employing a four-bit-tetral number, and so on.

It is unnecessary to use a combination of y bits in an x notation to display all of grades. For example, by employing a three-bit quainary number for 64-grade display, gamma correction is performed on the 64 grades, or by increasing only brightness of the maximum luminance grade to an extreme value, nonlinear brightness display like so-called peak luminance generation can be also realized.

A signal current level to be used can be changed also by display colors of R, G, and B.

Since the embodiment is based on a concept of x notation digital driving, it may be misled that the embodiment is apart from the concept of using both “analog signal” and “digital signal” as the idea of the invention. Description will be further given on this point. Definition of “digital signal” in the conventional image display is clearly “binary digital signal” and the “digital signal” has only two values of “on” and “off”. In contrast, the invention is based on the concept of using “multivalued analog signal” as well on the same device. That is, “analog signal” defined in the present invention is not always endless continuous gradations but is “multivalued signal” which even includes “digital signal in x notation”. The concept of the embodiment is that “multivalue signal” exists in the concept of a digital signal of a sub frame, so that the embodiment is within the concept of the present invention. It is obvious from the above argument that the concept of displaying only “analog signal” in each of sub frames is included in the present invention.

Sixth Embodiment

With reference toFIG. 15, a sixth embodiment of the invention will be described.FIG. 15is a configuration diagram of an image display terminal (PDA: Personal Digital Assistants)100as the sixth embodiment.

To a wireless interface (I/F)102, compressed image data or the like is input as radio data conformed with the standard of a short-range wireless access system from the outside. An output of the wireless I/F102is connected to a data bus108via an I/O (Input/Output) circuit103. To the data bus108, a microprocessor (MPU)104, a display panel controller106, a frame memory107, and the like are also connected.

Further, an output of the display panel controller106is input to an OLED display panel101. The image display terminal100is further provided with a delta wave generating circuit105and a power supply109. An output of the delta wave generating circuit105is input to the OLED display panel101. Since the OLED display panel101has the same configuration and operation as those in the foregoing first embodiment, its description will not be repeated here.

The operation of the sixth embodiment will be described. First, the wireless I/F102receives compressed image data from the outside in accordance with a command and transfers the image data to the microprocessor104and the frame memory107via the I/O circuit103. The microprocessor104receives a command operation from the user and drives the whole image display terminal100as necessary to decode the compressed image data, perform a signal process, and display information. The image data subjected to the signal process is temporarily stored in the frame memory107.

When the microprocessor104gives an instruction of displaying data, in response to the instruction, the image data is supplied from the frame memory107to the OLED display panel101via the display panel controller106, and the supplied image data is displayed in a real time manner on the OLED display panel101. At this time, the display panel controller106outputs a predetermined timing pulse necessary to simultaneously display images and, synchronously, the delta wave generating circuit105outputs a delta wave shaped pixel drive voltage.

As described in the first embodiment, by using the signals, display data generated from 6-bit image data is displayed in a real time manner on the OLED display panel101. The power supply109which includes a secondary battery supplies power for driving the whole image display terminal100.

According to the embodiment, the image display terminal100capable of performing high-precision multi-gradation display can be provided.

Although the OLED display panel described in the first embodiment is used as an image display device in the sixth embodiment, obviously, various display panels described in the other embodiments of the present invention can be also used.

As obviously understood from the foregoing embodiments, according to the invention, the image display capable of performing high-precision multi-gradation display can be obtained while solving problems of a subtle noise and increase in driving frequency.