Differential charge pump and filter with common-mode voltage control

A charge pump and filter for a phase-lock loop circuit are provided with common-mode voltage control for differential outputs to be used by a voltage-controlled oscillator. The common-mode voltage controller preferably initializes capacitors in the filter to an optimum common-mode voltage in response to a reset signal. Common-mode voltage is controlled using currents that are small compared to currents generated by the charge pump (less than 20 .mu.A).

BACKGROUND OF THE INVENTION
 1. Field of the Invention
 The present invention generally relates to electronic clock circuits, and
 more particularly to an electronic clock for a microprocessor, that uses a
 phase-lock loop (PLL) circuit having an improved charge pump which
 compensates for common-mode voltages at the differential inputs of a
 voltage-controlled oscillator.
 2. Description of the Related Art
 Electronic circuits that provide clock signals are used in a wide
 assortment of devices, and particularly in computer systems.
 Microprocessors and other computer components, such as random access
 memory (RAM), device controllers and adapters, use clock signals to
 synchronize various high-speed operations. These computer clock circuits
 often use a phase-lock loop (PLL) circuit to synchronize (de-skew) an
 internal logic control clock with respect to an external system clock.
 A typical prior art PLL circuit 1 is shown in FIG. 1 and includes a
 phase/frequency detector (PFD) 2, a charge pump 3, a low-pass filter 4,
 and a voltage-controlled oscillator (VCO) 5. Phase/frequency detector 2
 compares two input signals, a reference signal f.sub.ref (from the
 external system clock) and a feedback signal f.sub.fb, and generates phase
 error signals that are a measure of the phase difference between f.sub.ref
 and f.sub.fb. The phase error signals ("UP" and "DOWN") from detector 2
 are used to generate control signals by charge pump 3 which are filtered
 by low-pass filter 4 and fed into the control input of voltage-controlled
 oscillator 5. Voltage-controlled oscillator 5 generates a periodic signal
 with a frequency which is controlled by the filtered phase error signal.
 The output of voltage-controlled oscillator 5 is coupled to the input
 f.sub.fb of phase/frequency detector 2 directly or indirectly through
 other circuit elements such as dividers 6, buffers (not shown) or clock
 distribution networks (not shown), thereby forming a feedback loop. If the
 frequency of the feedback signal is not equal to the frequency of the
 reference signal, the filtered phase error signal causes the frequency of
 voltage-controlled oscillator 5 to shift (upwards or downwards) toward the
 frequency of the reference signal, until voltage-controlled oscillator 5
 finally locks onto the frequency of the reference; following frequency
 acquisition, phase acquisition is achieved in a similar manner. The output
 of voltage-controlled oscillator 5 is then used as the synchronized signal
 (for internal logic control). In cases where the incoming data is a
 self-clocking bit stream, the comparator system is used to extract the
 clock information from the data stream itself.
 PLL's for microprocessors must exhibit high tolerance to electrical noise
 generated by the large number of rapidly switching logic circuits that are
 fabricated on the same die (silicon substrate or microchip). Differential
 circuits (rather than single-ended circuits) are accordingly preferred for
 these applications, but at present they are generally in use for only
 selected portions of the PLL, such as the voltage-controlled oscillator
 signal path (but not the control path of the voltage-controlled
 oscillator). See "A PLL Clock Generator with 5 to 110 MHz of Lock Range
 for Microprocessors," IEEE Journal of Solid-State Circuits, vol. 27, no.
 11, pp. 1599-1607 (November 1992), and "A Wide-Bandwidth Low-Voltage PLL
 for PowerPC.TM. Microprocessors" IEEE Journal of Solid-State Circuits,
 vol. 30, no. 4, pp. 383-391 (April 1995).
 One problem that can arise with differential circuits in a PLL circuit
 relates to common-mode voltage. In a differential circuit, a value is
 based on the relative voltages of two signals, i.e., their difference, and
 not their absolute values. A common-mode voltage is a voltage that is
 applied equally to both signals, whereby the absolute values of the
 voltages are higher, although the difference between the voltages remains
 constant. A circuit element with differential inputs may be designed with
 an n-type field-effect transistor (nfet) source-coupled pair at the input,
 or a p-type field-effect transistor (pfet) source-coupled pair at the
 input. These transistors are sensitive to common-mode voltages that arise
 from the signal source, such as those resulting from excessive noise,
 leakage currents, and nfet or pfet operating characteristics. If the
 common-mode of the signal from the filter moves in such a way that the
 input stage begins to shut off (e.g., a high common-mode voltage for a
 pfet source-coupled pair), then the stability of the circuit can
 deteriorates dramatically and eventually fail to operate. This phenomenon
 is particularly troublesome with high-speed clock circuits, e.g., those
 with speeds greater than a few hundred megahertz.
 One approach to handling such high common-mode voltages in a
 voltage-controlled oscillator would be to provide more sophisticated input
 stages. The resulting bandwidth reduction on the control input would,
 however, render such a voltage-controlled oscillator practically useless
 due to the loss of the required high frequency signal caused by the zero
 frequency in the transfer function. It would, therefore, be desirable and
 advantageous to devise an improved PLL clocking circuit having a
 differential component, such as a voltage-controlled oscillator, in which
 common-mode voltages of the inputs are controlled to alleviate the
 foregoing problems.
 SUMMARY OF THE INVENTION
 It is therefore one object of the present invention to provide an improved
 clock circuit, such as may be used with a microprocessor.
 It is another object of the present invention to provide such a clock
 circuit having a phase-lock loop (PLL) which uses a charge pump and filter
 to supply differential control inputs to a voltage-controlled oscillator.
 It is yet another object of the present invention to provide a clock
 circuit using such a charge pump and filter which controls or compensates
 for common-mode voltages arising at the control inputs.
 The foregoing objects are achieved in a circuit generally comprising charge
 pump means for receiving one or more error signals and generating two
 output control signals, means for filtering the output control signals,
 including capacitor means for storing electrical charge, and means for
 controlling a common-mode voltage at the capacitor means. The means for
 controlling the common-mode voltage can include means for clamping the
 output control signals at high voltages, and further preferably includes
 means for initializing the capacitor means to an optimum common-mode
 voltage in response to a reset signal. The means for controlling the
 common-mode voltage generates currents that are small compared to currents
 generated by the charge pump means (less than 20 .mu.A). A phase-lock loop
 (PLL) can be constructed using this circuit, along with phase/frequency
 detector means for supplying the one or more error signals, and
 voltage-controlled oscillator means for providing a feedback signal to the
 phase/frequency detector means.
 The above as well as additional objectives, features, and advantages of the
 present invention will become apparent in the following detailed written
 description.

DESCRIPTION OF THE PREFERRED EMBODIMENT
 With reference now to the figures, and in particular with reference to FIG.
 2, there is depicted one embodiment 10 of a circuit constructed in
 accordance with the present invention, and adapted for use in a phase-lock
 loop (PLL) circuit. Circuit 10 is generally comprised of a charge pump 12,
 a filter 14, and a common-mode voltage controller 16. In this embodiment,
 circuit 10 is used to create differential input signals V.sub.c and
 V.sub.cb which are fed to a voltage-controlled oscillator (not shown in
 FIG. 2) having a source-coupled pair of p-type metal-oxide semiconducting
 field-effect transistors (pfets). A PLL which uses circuit 10 may include
 additional components such as a phase/frequency detector (not shown in
 FIG. 2), connected in a manner similar to that shown in FIG. 1, wherein
 the outputs of the phase/frequency detector (UP, UPB, DOWN, DOWNB) are
 provided to charge pump 12. A suitable phase/frequency detector is
 described in U.S. patent application Ser. No. 08/888,797. As will become
 apparent to those skilled in the art, circuit 10 is particularly useful in
 a PLL circuit designed for a high-speed computer clock.
 Charge pump 12 includes a pair of n-type metal-oxide semiconducting
 field-effect transistors (nfets) 18 and 20 which are respectively
 connected to the UP and DOWN inputs provided from the phase/frequency
 detector. A pair of pfets 22 and 24 are similarly connected to the
 complementary signals UPB and DOWNB. A first constant current source 26 is
 coupled to three other nfets 28, 30 and 32 to form two current mirrors
 that are respectively connected to nfets 18 and 20. A second constant
 current source 34 is similarly coupled to three other pfets 36, 38 and 40
 to form two current mirrors that are respectively connected to pfets 22
 and 24. The devices are connected as indicated to a power supply V.sub.dd
 or AV.sub.dd (analog voltage V.sub.dd) which, in the depicted embodiment,
 is about 2.5 volts.
 When the DOWN signal is asserted, current is sunk by the drain of nfet 18
 which is further coupled to a first differential output V.sub.c via a
 clamping nfet 42. When the UP signal is asserted, current is sunk by the
 drain of nfet 20, which is further coupled to a second differential output
 V.sub.cb via another clamping nfet 44. Conversely, when the DOWNB signal
 is asserted, current is sourced by the drain of pfet 24 which is connected
 to the drain of nfet 20 and, when the UPB signal is asserted, current is
 sourced by the drain of pfet 22, which is connected to the drain of nfet
 18. Since the DOWNB signal is the inverse of the DOWN signal and DOWNB is
 "active" in the low (zero) state, nfet 18 operates together with pfet 24.
 Similarly, since the UPB signal is the inverse of the UP signal and UPB is
 also "active" in the low (zero) state, nfet 20 operates together with pfet
 22. In this manner, the error signals from the phase/frequency detector
 are used to gate the currents and generate the control output signals,
 which become inputs to the voltage-controlled oscillator. In the
 particular embodiment of circuit 10, charge pump 12 generates control
 signals with currents in the range of 30-90 .mu.A.
 The output control signals V.sub.c and V.sub.cb are conditioned by filter
 14, which includes a first RC filter 46 connected to output V.sub.c, and a
 second RC filter 48 connected to output V.sub.cb. Each RC filter
 preferably includes a plurality of precision resistors which are
 interconnected in such a manner as to allow trimming of the RC filter
 resistance by cutting one or more of the interconnecting leads using a
 tool or laser. Each RC filter also has a capacitive element 50, 52. In
 other words, the currents from nfets 42 and 44 are used charge or
 discharge the filter capacitors as the error signals are asserted, which
 accordingly causes the voltage at the outputs V.sub.c and V.sub.cb to
 increase or decrease.
 Common-mode voltages can arise in charge pump 12 and filter 14 due to
 various reasons, such as leakage currents, excessive noise, and device
 operating characteristics, potentially allowing V.sub.c and V.sub.cb to
 rise above (or fall below) V.sub.dd -V.sub.t over a long period of time.
 The voltages at the capacitor nodes CAP and CAPB are sensed respectively
 by pfets 54 and 56, and represent the average value of the voltages at
 V.sub.c and V.sub.cb. Pfets 54 and 56 generate currents which are
 proportional to V.sub.dd -V.sub.c and V.sub.dd -V.sub.cb, respectively.
 These currents are added using an nfet 58 so that the voltage at the drain
 node of nfet 58 is proportional to the sum of the currents, effectively
 monitoring (inversely) the common-mode voltage of V.sub.c and V.sub.cb.
 The voltage at this node is compared to an external reference voltage
 v.sub.ref using the gain stage comprised of pfets 60, 62 and 68, and nfets
 64 and 66. An external voltage v.sub.p is used to bias pfet 60 in the
 constant-current region. An exemplary value for v.sub.p is 1.5 volts
 although this is somewhat dependent on temperature, the fabrication
 process and the power supply, and can be controlled by monitoring the
 temperature of the circuit.
 As the common-mode voltage (V.sub.c +V.sub.cb) increases, the voltage at
 the drain node of nfet 58 decreases, causing more current to flow through
 pfet 62 and increasing the voltage at the drain node (out) of nfet 64.
 Nfet current sinks 70 and 72 draw currents proportional to the common-mode
 voltage from the filter capacitors 50 and 52. The currents so drawn are
 small compared to the currents sourced or sunk by charge pump 12, and are
 matched so that the common-mode voltage is reduced without
 overcompensating, while the differential voltage is unaffected. The
 currents sunk by nfets 70 and 72 are shown as a function of common-mode
 voltage in FIG. 3 (for V.sub.ref =0.7 volts). Under normal conditions,
 these currents will be less than 5 .mu.A, and are limited to less than 20
 .mu.A (about 18 .mu.A) under worst case common-mode conditions.
 Common-mode voltage controller 16 is initialized in response to assertion
 of the power-on reset signal (complement). That signal is connected to an
 inverter 74 whose output controls two nfets 76 and 78 that are
 respectively connected to the CAP and CAPB nodes. The output of inverter
 74 is also fed to another inverter 80 whose output further controls a pfet
 82 that supplies an initialization reference voltage to nfets 76 and 78
 via a voltage divider comprised of nfets 84 and 86. In this manner, when
 the power-one reset signal (complement) is sent, pfet 82 conducts and a
 voltage V.sub.init is generated. This voltage charges capacitors 50 and 52
 since nfets 76 and 78 are turned on. V.sub.init is preferably the optimum
 common-mode value, approximately equal to (V.sub.dd -V.sub.t)/2 (around
 0.8 volts). Nfets 76 and 78 are preferably low impedance to allow quick
 charging to V.sub.init. This initialization circuit ensures rapid and
 predictable loop acquisition.
 Clamping nfets 42 and 44 provide further protection against high
 common-mode voltages. For low values of V.sub.c and V.sub.cb, nfets 42 and
 44 are conducting, effectively transferring the currents from or to the
 charge pump. Nfets 42 and 44 will conduct until their source voltages
 (V.sub.c and V.sub.cb) are approximately V.sub.dd -V.sub.t where V.sub.t
 is the threshold voltage of the device. Since the bulk-to-source voltage
 (V.sub.bs) is large, the value of V.sub.t is much larger than the V.sub.t
 of a device with a grounded source, and may be as much as two times
 larger. Hence, V.sub.c and V.sub.cb are limited to voltages of less than
 V.sub.dd -0.8, as a first order approximation, and so do not reach higher
 levels which would turn off the voltage-controlled oscillator. Voltage
 clamping with an nfet source-coupled pair input for the voltage-controlled
 oscillator would clamp the output control signals at a low voltage rather
 than a high voltage.
 Although the invention has been described with reference to specific
 embodiments, this description is not meant to be construed in a limiting
 sense. Various modifications of the disclosed embodiment, as well as
 alternative embodiments of the invention, will become apparent to persons
 skilled in the art upon reference to the description of the invention. It
 is therefore contemplated that such modifications can be made without
 departing from the spirit or scope of the present invention as defined in
 the appended claims.