Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same

A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at least one joint-level doped semiconductor portion.

FIELD

The present disclosure relates generally to the field of three-dimensional memory devices and specifically to multi-tier three-dimensional memory devices containing dummy memory cells for providing inter-tier connection and methods of making the same.

BACKGROUND

Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. Some of the challenges for fabricating a multi-tier memory stack structure include formation of memory openings having high aspect ratios and alleviation of effects of misalignment of tier-level memory openings formed in different tier structures. Thus, methods are desired for providing a reliable connection between vertically neighboring memory stack structures.

SUMMARY

According to an aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate; a first memory opening fill structure extending through the first alternating stack and comprising a first memory film and a first vertical semiconductor channel that is laterally surrounded by the first memory film; a joint-level electrically conductive layer overlying the first alternating stack; at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer; a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer; and a second memory opening fill structure extending through the second alternating stack and comprising a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at least one joint-level doped semiconductor portion. The first memory film and the second memory film are vertically spaced from each other by the at least one joint-level doped semiconductor portion.

According to another aspect of the present disclosure, a three-dimensional memory device is provided, which comprises: a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate; a joint-level electrically conductive layer overlying the first alternating stack; a first memory opening fill structure extending through the first alternating stack and the joint-level electrically conductive layer and comprising a first memory film and a first vertical semiconductor channel that is laterally surrounded by the first memory film; a dielectric liner layer including a horizontal portion that overlies the first alternating stack and underlies the joint-level electrically conductive layer, and a cylindrical vertical portion that laterally surrounds an upper portion of the first memory opening fill structure, wherein the joint-level electrically conductive layer is laterally spaced from the first memory opening fill structure by the cylindrical vertical portion of the dielectric liner layer; a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer and the dielectric liner layer; and a second memory opening fill structure comprising a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and extends through the second alternating stack and contacting the first vertical semiconductor channel.

According to yet another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises the steps of: forming a first alternating stack of first insulating layers and first spacer material layers located over a substrate; forming a first memory opening fill structure through the first alternating stack, wherein the first memory opening fill structure comprises a first memory film and a first vertical semiconductor channel that is laterally surrounded by the first memory film; forming at least one joint-level doped semiconductor portion on a top surface of the first vertical semiconductor channel; forming at least one annular dielectric spacer around the at least one joint-level doped semiconductor portion; forming a joint-level spacer material layer over the first alternating stack and around the at least one joint-level doped semiconductor portion; forming a second alternating stack of second insulating layers and second spacer material layers over the joint-level spacer material layer; and forming a second memory opening fill structure through the second alternating stack, wherein the second memory opening fill structure comprises a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and contacts the at least one joint-level doped semiconductor portion. The first and second spacer material layers and the joint-level spacer material layers are formed as, or are replaced with, first and second electrically conductive layers and a joint-level electrically conductive layer, respectively.

According to still another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, which comprises the steps of: forming a first alternating stack of first insulating layers and first spacer material layers over a substrate; forming a joint-level sacrificial planarization layer over the first alternating stack; forming a first memory opening fill structure through the first alternating stack and the joint-level sacrificial planarization layer, wherein the first memory opening fill structure comprises a first memory film and a first vertical semiconductor channel that is laterally surrounded by the first memory film; removing the joint-level sacrificial planarization layer selective to the first memory opening fill structure and the first alternating stack; forming a dielectric liner layer and a joint-level spacer material layer over the first memory opening fill structure and the first alternating stack, wherein the dielectric liner layer includes a horizontal portion that overlies the first alternating stack and underlies the joint-level spacer material layer, and a cylindrical vertical portion that laterally surrounds an upper portion of the first memory opening fill structure, wherein the joint-level spacer material layer is laterally spaced from the first memory opening fill structure by the cylindrical vertical portion of the dielectric liner layer; forming a second alternating stack of second insulating layers and second spacer material layers over the joint-level spacer material layer and the dielectric liner layer; and forming a second memory opening fill structure through the second alternating stack, wherein the second memory opening fill structure comprises a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and contacts the first vertical semiconductor channel. The first and second spacer material layers and the joint-level spacer material layers are formed as, or are replaced with, first and second electrically conductive layers and a joint-level electrically conductive layer, respectively.

DETAILED DESCRIPTION

As discussed above, the present disclosure is directed to multi-tier three-dimensional memory devices employing dummy memory cells for providing inter-tier connection and methods of making the same, the various aspects of which are described below. An embodiment of the disclosure can be employed to form semiconductor devices such as three-dimensional monolithic memory array devices comprising a plurality of NAND memory strings. The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. Elements with the same reference numeral refer to a same element or a similar element, and are presumed to have the same composition unless explicitly noted otherwise.

As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element.

As used herein, a “layer stack” refers to a stack of layers. As used herein, a “line” or a “line structure” refers to a layer that has a predominant direction of extension, i.e., having a direction along which the layer extends the most.

As used herein, an “active region” refers to a source region of a field effect transistor or a drain region of a field effect transistor.

Referring toFIG. 1, a first exemplary structure according to a first embodiment of the present disclosure is illustrated, which can be employed, for example, to fabricate a device structure containing vertical NAND memory devices. The first exemplary structure includes a substrate, which can be a semiconductor substrate (9,10). The substrate can include a substrate semiconductor layer9. The substrate semiconductor layer9maybe a semiconductor wafer or a semiconductor material layer, and can include at least one elemental semiconductor material (e.g., single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a major surface7, which can be, for example, a topmost surface of the substrate semiconductor layer9. The major surface7can be a semiconductor surface. In one embodiment, the major surface7can be a single crystalline semiconductor surface, such as a single crystalline semiconductor surface.

At least one semiconductor device700for a peripheral circuitry can be formed on a portion of the substrate semiconductor layer9. Optionally, a portion of the substrate semiconductor layer9can be vertically recessed to provide a recessed region, and the at least one semiconductor device700may be formed in the recessed region. Alternatively, an additional semiconductor material may be added to the substrate semiconductor layer9outside a region of the at least one semiconductor device700, for example, by selective epitaxy after formation of the at least one semiconductor device.

The at least one semiconductor device can include, for example, field effect transistors. For example, at least one shallow trench isolation structure720can be formed by etching portions of the substrate semiconductor layer9and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer9, and can be subsequently patterned to form at least one gate structure (750,752,754,758), each of which can include a gate dielectric750, a gate electrode (752,754), and a gate cap dielectric758. The gate electrode (752,754) may include a stack of a first gate electrode portion752and a second gate electrode portion754. At least one gate spacer756can be formed around the at least one gate structure (750,752,754,758) by depositing and anisotropically etching a dielectric liner. Active regions730can be formed in upper portions of the substrate semiconductor layer9, for example, by introducing electrical dopants employing the at least one gate structure (750,752,754,758) as masking structures. Additional masks may be employed as needed.

The active region730can include source regions and drain regions of field effect transistors. A first dielectric liner761and a second dielectric liner762can be optionally formed. Each of the first and second dielectric liners (761,762) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atoms. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner761can be a silicon oxide layer, and the second dielectric liner762can be a silicon nitride layer. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device.

A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer770. In one embodiment the planarized top surface of the planarization dielectric layer770can be coplanar with a top surface of the dielectric liners (761,762). Subsequently, the planarization dielectric layer770and the dielectric liners (761,762) can be removed from an area to physically expose a top surface of the substrate semiconductor layer9in regions that do not include the at least one semiconductor device700.

An optional semiconductor material layer10may be formed within, or on top of, the substrate semiconductor layer9by ion implantation of electrical dopants (such as p-type dopants or n-type dopants) and/or by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. The single crystalline semiconductor material of the semiconductor material layer10can be in epitaxial alignment with the single crystalline structure of the substrate semiconductor layer9. Portions of the deposited semiconductor material located above the top surface of the planarization dielectric layer170can be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer10can have a top surface that is coplanar with the top surface of the planarization dielectric layer170.

The region (i.e., area) of the at least one semiconductor device700is herein referred to as a peripheral device region300. The region in which a memory array is subsequently formed is herein referred to as a memory array region100. A contact region200for subsequently forming stepped terraces of electrically conductive layers can be provided between the memory array region100and the peripheral device region300.

A gate dielectric layer12can be formed above the semiconductor material layer10and the planarization dielectric layer170. The gate dielectric layer12can include, for example, a silicon oxide layer and/or a dielectric metal oxide layer (such as an aluminum oxide layer and/or a hafnium oxide layer). The thickness of the gate dielectric layer12can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed.

An alternating stack of first material layers and second material layers is subsequently formed. Each first material layer can include a first material, and each second material layer can include a second material that is different from the first material. The first material layers can be insulating layers, in which case the first material layers are herein referred to as first insulating layers132. The second material layers are herein referred to as first spacer material layers, which provide vertical spacing between the first insulating layers132. The first spacer material layers may be provided as sacrificial material layers that are subsequently replaced with electrically conductive layers. In this case, the first spacer material layers are referred to as first sacrificial material layers142. Alternatively, the first spacer material layers may be provided as electrically conductive layers (such as metal layers). In this case, the first spacer material layers are herein referred to as first electrically conductive layers. While the present disclosure is described employing an embodiment in which the first sacrificial material layers142are employed as the first spacer material layers, embodiments are expressly contemplated herein in which first electrically conductive layers are employed as the first spacer material layers.

In one embodiment, the first material layers and the second material layers can be first insulating layers132and first sacrificial material layers142, respectively. In one embodiment, each first insulating layer132can include a first insulating material, and each first sacrificial material layer142can include a first sacrificial material. The alternating stack formed by the first insulating layers132and the first sacrificial material layers142is herein referred to as a first alternating stack (132,142), or a lower alternating stack (132,142). In this case, the stack can include an alternating plurality of first insulating layers132and first sacrificial material layers142. As used herein, a “sacrificial material” refers to a material that is removed during a subsequent processing step.

The first alternating stack (132,142) can include first insulating layers132composed of the first material, and first sacrificial material layers142composed of the second material, which is different from the first material. The first material of the first insulating layers132can be at least one insulating material. Insulating materials that can be employed for the first insulating layers132include, but are not limited to silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first insulating layers132can be silicon oxide.

The first sacrificial material layers142may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layers142can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the first sacrificial material layers142can be material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium.

In one embodiment, the first insulating layers132can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial material layers. The first material of the first insulating layers132can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the first insulating layers132, tetraethylorthosilicate (TEOS) can be employed as the precursor material for the CVD process. The second material of the first sacrificial material layers142can be formed, for example, CVD or atomic layer deposition (ALD).

The thicknesses of the first insulating layers132and the first sacrificial material layers142can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each first insulating layer132and for each first sacrificial material layer142. The number of repetitions of the pairs of a first insulating layer132and a first sacrificial material layer142can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. In one embodiment, each first sacrificial material layer142in the first alternating stack (132,142) can have a uniform thickness that is substantially invariant within each respective first sacrificial material layer142.

A first-tier insulating cap layer172can be subsequently formed over the second alternating stack (232,242). The first-tier insulating cap layer172includes a dielectric material that is different from the material of the first sacrificial material layers142. The first-tier insulating cap layer172includes a dielectric material that may be the same as, or different from, the material of the first insulating layers132. In one embodiment, the first-tier insulating cap layer172can include silicon oxide. In one embodiment, the thickness of the first-tier insulating cap layer172can be in a range from 20 nm to 100 nm, although lesser and greater thicknesses can also be employed. The first alternating stack (132,142) and the first insulating cap layer172collectively constitutes a first tier structure (132,142,172).

Referring toFIGS. 2A and 2B, the first tier structure (132,142,172) can be patterned to form first stepped surfaces. The first stepped surfaces form a first terrace region, which is located within an area of the contact region200. The contact region200includes a first stepped area in which the first stepped surfaces are formed, and a second stepped area in which additional stepped surfaces are to be subsequently formed in an second tier structure (to be subsequently formed over the first tier structure). The memory array region100is provided adjacent to the contact region200. Memory devices including memory stack structures can be subsequently formed in the memory array region100. The first stepped surfaces can be formed, for example, by forming a mask layer with an opening therein, etching a cavity within the levels of the topmost first sacrificial material layer142and the topmost first insulating layer132, and iteratively expanding the etched area and vertically recessing the cavity by etching each pair of a first insulating layer132and a first sacrificial material layer142located directly underneath the bottom surface of the etched cavity within the etched area. The first-tier insulating cap layer172and the first alternating stack (132,142) are patterned such that each underlying first sacrificial material layer142laterally protrudes farther than any overlying first sacrificial material layer142in the etched region, and each underlying first insulating layer132laterally protrudes farther than any overlying first insulating layer132in the etched region. The contact region can be a contact region of the first alternating stack (132,142). The cavity is herein referred to as a first stepped cavity.

A dielectric material is deposited to fill the first stepped cavity. Excess portions of the dielectric material overlying the topmost surface of the first alternating stack (132,142), are removed for example, by chemical mechanical planarization. The remaining portion of the deposited dielectric material forms a first dielectric material portion, which is herein referred to as a first retro-stepped dielectric material portion165. The first retro-stepped dielectric material portion165is formed on the first stepped surfaces. The first dielectric material portion165is retro-stepped. As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. The first tier structure, which is also referred to as a first stack structure, comprises the first alternating stack (132,142) and the first retro-stepped dielectric material portion165. The first retro-stepped dielectric material portion165is incorporated into the first tier structure (132,142,172,165).

Referring toFIGS. 3A and 3B, first-tier openings (149,119) extending to a top surface of the substrate (9,10) are formed through the first tier structure (132,142,172,165). The first-tier openings (149,119) include first-tier memory openings149that are formed in the memory array region100and first-tier support openings119that are formed in the contact region200. The first-tier memory openings149and the first-tier support openings119can be formed concurrently by a patterning process. To form the first-tier openings (149,119), a lithographic material stack (not shown) including at least a photoresist layer can be formed over the first tier structure (132,142,172,165), and can be lithographically patterned to form openings within the lithographic material stack. The pattern in the lithographic material stack can be transferred through the entirety of the first tier structure (132,142,172,165) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the first tier structure (132,142,172,165) underlying the openings in the patterned lithographic material stack are etched to form the first-tier openings (149,119). In other words, transfer of the pattern in the patterned lithographic material stack through the first tier structure (132,142,172,165) forms the first-tier openings (149,119).

In one embodiment, the chemistry of the anisotropic etch process employed to etch through the materials of the first alternating stack (132,142) can alternate to optimize etching of the first and second materials in the first alternating stack (132,142) while providing a comparable average etch rate for the first dielectric material portion165. The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the first-tier openings (149,119) can be substantially vertical, or can be tapered. Subsequently, the patterned lithographic material stack can be subsequently removed, for example, by ashing. The first-tier memory openings149and the first-tier support openings119can be formed concurrently employing the same set of anisotropic etch processes.

In one embodiment, the substrate (9,10) can be employed as a stopping layer for the anisotropic etch process. In one embodiment, the first-tier openings (149,119) may extend below the top surface of the substrate (9,10) by an overetch. The lateral dimensions (e.g., a diameter) of the first-tier openings (149,119) can be from about 20 nm to 200 nm at an upper portion of each first-tier opening (149,119), and can be about 10 nm to 150 nm at a lower portion of each first-tier opening (149,119).

In one embodiment, the first-tier memory openings149can be formed as an array of openings, which can be a periodic two-dimensional array of openings. The first-tier support openings119can be formed as discrete openings that are mutually separated from one another, and may, or may not, form a periodic two-dimensional array pattern. In one embodiment, the first-tier support openings119may form a plurality of periodic one-dimensional array patterns that are parallel among one another.

FIGS. 4A-4Gillustrate sequential vertical cross-sectional views of a first-tier memory opening149within the first exemplary structure up to the processing step of formation of a first memory stack structure.

Referring toFIG. 4A, a first-tier memory opening149in the first exemplary device structure ofFIGS. 3A and 3Bis illustrated. The first-tier memory opening149extends through the first-tier insulating cap layer172, the first alternating stack (132,142), the gate dielectric layer12, and optionally into an upper portion of the semiconductor material layer10. At this processing step, each first-tier support opening119can extend through the first retro-stepped dielectric material portion165, a subset of layers in the first alternating stack (132,142), the gate dielectric layer12, and optionally through the upper portion of the semiconductor material layer10. The recess depth of the bottom surface of each first-tier memory opening149with respect to the top surface of the semiconductor material layer10can be in a range from 0 nm to 30 nm, although greater recess depths can also be employed. Optionally, the first sacrificial material layers142can be laterally recessed partially to form lateral recesses (not shown), for example, by an isotropic etch.

Referring toFIG. 4B, an optional epitaxial channel portion (e.g., an epitaxial pedestal)11can be formed at the bottom portion of each first-tier memory opening149and each first-tier support openings119, for example, by selective epitaxy. As an optional structure, the epitaxial channel portions11may be formed, or may be omitted. In case the epitaxial channel portions11are not formed, the processing steps ofFIG. 4Bcan be omitted. Each epitaxial channel portion11comprises a single crystalline semiconductor material in epitaxial alignment with the single crystalline semiconductor material of the semiconductor material layer10. In one embodiment, the epitaxial channel portion11can be doped with electrical dopants of the same conductivity type as the semiconductor material layer10. In one embodiment, the top surface of each epitaxial channel portion11can be formed above a horizontal plane including the top surface of a first sacrificial material layer142. In this case, at least one source select gate electrode can be subsequently formed by replacing each first sacrificial material layer142located below the horizontal plane including the top surfaces of the epitaxial channel portions11with a respective conductive material layer. The epitaxial channel portion11can be a portion of a transistor channel that extends between a source region to be subsequently formed in the substrate (9,10) and a drain region to be subsequently formed in an upper portion of the first-tier memory opening149. A first-tier memory cavity149′ is present in the unfilled portion of the first-tier memory opening149above the epitaxial channel portion11. In one embodiment, the epitaxial channel portion11can comprise single crystalline silicon. In one embodiment, the epitaxial channel portion11can have a doping of the first conductivity type, which is the same as the conductivity type of the semiconductor material layer10that the epitaxial channel portion contacts. If a semiconductor material layer10is not present, the epitaxial channel portion11can be formed directly on the substrate semiconductor layer9, which can have a doping of the first conductivity type.

Referring toFIG. 4C, a stack of layers including a first blocking dielectric layer152, a first charge storage layer154, a first tunneling dielectric layer156, and an optional first outer semiconductor channel layer611can be sequentially deposited in the first-tier memory openings149.

The first blocking dielectric layer152can include a single dielectric material layer or a stack of a plurality of dielectric material layers. In one embodiment, the first blocking dielectric layer can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of the at least one metallic element and oxygen, or may consist essentially of the at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the first blocking dielectric layer152can include a dielectric metal oxide having a dielectric constant greater than 7.9, i.e., having a dielectric constant greater than the dielectric constant of silicon nitride.

Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. The dielectric metal oxide layer can subsequently function as a dielectric material portion that blocks leakage of stored electrical charges to control gate electrodes. In one embodiment, the first blocking dielectric layer152includes aluminum oxide. In one embodiment, the first blocking dielectric layer152can include multiple dielectric metal oxide layers having different material compositions.

Alternatively or additionally, the first blocking dielectric layer152can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the first blocking dielectric layer152can include silicon oxide. In this case, the dielectric semiconductor compound of the first blocking dielectric layer152can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. Alternatively, the first blocking dielectric layer152can be omitted, and a backside first blocking dielectric layer can be formed after formation of backside recesses on surfaces of memory films to be subsequently formed.

Subsequently, the first charge storage layer154can be formed. In one embodiment, the first charge storage layer154can be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the first charge storage layer154can include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions (e.g., floating gates), for example, by being formed within lateral recesses into first sacrificial material layers142. In one embodiment, the first charge storage layer154includes a silicon nitride layer. In one embodiment, the first sacrificial material layers142and the first insulating layers132can have vertically coincident sidewalls, and the first charge storage layer154can be formed as a single continuous layer.

In another embodiment, the first sacrificial material layers142can be laterally recessed with respect to the sidewalls of the first insulating layers132, and a combination of a deposition process and an anisotropic etch process can be employed to form the first charge storage layer154as a plurality of memory material portions that are vertically spaced apart. While the present disclosure is described employing an embodiment in which the first charge storage layer154is a single continuous layer, embodiments are expressly contemplated herein in which the first charge storage layer154is replaced with a plurality of memory material portions (which can be charge trapping material portions or electrically isolated conductive material portions) that are vertically spaced apart.

The first charge storage layer154can be formed as a single first charge storage layer of homogeneous composition, or can include a stack of multiple first charge storage layers. The multiple first charge storage layers, if employed, can comprise a plurality of spaced-apart floating gate material layers that contain conductive materials (e.g., metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof) and/or semiconductor materials (e.g., polycrystalline or amorphous semiconductor material including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or additionally, the first charge storage layer154may comprise an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the first charge storage layer154may comprise conductive nanoparticles such as metal nanoparticles, which can be, for example, ruthenium nanoparticles. The first charge storage layer154can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. The thickness of the first charge storage layer154can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

The first tunneling dielectric layer156includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The first tunneling dielectric layer156can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the first tunneling dielectric layer156can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the first tunneling dielectric layer156can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the first tunneling dielectric layer156can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

The optional first outer semiconductor channel layer611includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first outer semiconductor channel layer611includes amorphous silicon or polysilicon. The first outer semiconductor channel layer611can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first outer semiconductor channel layer611can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A first memory cavity149′ is formed in the volume of each first-tier memory opening149that is not filled with the deposited material layers (52,154,156,611).

Referring toFIG. 4D, the optional first outer semiconductor channel layer611, the first tunneling dielectric layer156, the first charge storage layer154, the first blocking dielectric layer152are sequentially anisotropically etched employing at least one anisotropic etch process. The portions of the first outer semiconductor channel layer611, the first tunneling dielectric layer156, the first charge storage layer154, and the first blocking dielectric layer152located above the top surface of the first-tier insulating cap layer172can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the first outer semiconductor channel layer611, the first tunneling dielectric layer156, the first charge storage layer154, and the first blocking dielectric layer152at a bottom of each first memory cavity149′ can be removed to form openings in remaining portions thereof. Each of the first outer semiconductor channel layer611, the first tunneling dielectric layer156, the first charge storage layer154, and the first blocking dielectric layer152can be etched by a respective anisotropic etch process employing a respective etch chemistry, which may, or may not, be the same for the various material layers.

Each remaining portion of the first outer semiconductor channel layer611can have a tubular configuration. The first charge storage layer154can comprise a charge trapping material or a floating gate material. In one embodiment, each first charge storage layer154can include a vertical stack of first charge storage regions that store electrical charges upon programming. In one embodiment, the first charge storage layer154can be a first charge storage layer in which each portion adjacent to the first sacrificial material layers142constitutes a first charge storage region.

A surface of the epitaxial channel portion11(or a surface of the semiconductor material layer10in case the epitaxial channel portions11are not employed) can be physically exposed underneath the opening through the first outer semiconductor channel layer611, the first tunneling dielectric layer156, the first charge storage layer154, and the first blocking dielectric layer152. Optionally, the physically exposed semiconductor surface at the bottom of each first memory cavity149′ can be vertically recessed so that the recessed semiconductor surface underneath the first memory cavity149′ is vertically offset from the topmost surface of the epitaxial channel portion11(or of the semiconductor substrate layer10in case epitaxial channel portions11are not employed) by a recess distance. A first tunneling dielectric layer156is located over the first charge storage layer154. A set of a first blocking dielectric layer152, a first charge storage layer154, and a first tunneling dielectric layer156in a first-tier memory opening149constitutes a memory film150, which includes a plurality of first charge storage regions (as embodied as the first charge storage layer154) that are insulated from surrounding materials by the first blocking dielectric layer152and the first tunneling dielectric layer156. In one embodiment, the first outer semiconductor channel layer611, the first tunneling dielectric layer156, the first charge storage layer154, and the first blocking dielectric layer152can have vertically coincident sidewalls.

Referring toFIG. 4E, a first inner semiconductor channel layer612can be deposited directly on the semiconductor surface of the epitaxial channel portion11or the semiconductor substrate layer10if the epitaxial channel portion11is omitted, and directly on the first outer semiconductor channel layer611. The first inner semiconductor channel layer612includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first inner semiconductor channel layer612includes amorphous silicon or polysilicon. The first inner semiconductor channel layer612can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first inner semiconductor channel layer612can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The first inner semiconductor channel layer612may partially fill the first memory cavity149′ in each memory opening, or may fully fill the cavity in each memory opening.

The materials of the first outer semiconductor channel layer611and the first inner semiconductor channel layer612are collectively referred to as a first semiconductor channel material. In other words, the first semiconductor channel material is a set of all semiconductor material in the first outer semiconductor channel layer611and the first inner semiconductor channel layer612.

Referring toFIG. 4F, in case the first memory cavity149′ in each first-tier memory opening is not completely filled by the first inner semiconductor channel layer612, a first dielectric core layer162L can be deposited in the first memory cavity149′ to fill any remaining portion of the first memory cavity149′ within each first-tier memory opening. The first dielectric core layer162L includes a dielectric material such as silicon oxide or organosilicate glass. The first dielectric core layer162L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG. 4G, the horizontal portion of the first dielectric core layer162L can be removed, for example, by a recess etch from above the top surface of the first-tier insulating cap layer172. Each remaining portion of the first dielectric core layer162L constitutes a dielectric core162. Further, the horizontal portion of the first inner semiconductor channel layer612located above the top surface of the first-tier insulating cap layer172can be removed by a planarization process, which can employ a recess etch or chemical mechanical planarization (CMP). Each remaining portion of the first inner semiconductor channel layer612can be located entirety within a first-tier memory opening149or entirely within a first-tier support opening119.

Each adjoining pair of a first outer semiconductor channel layer611and a first inner semiconductor channel layer612can collectively form a first vertical semiconductor channel61through which electrical current can flow when a vertical NAND device including the first vertical semiconductor channel61is turned on. A first tunneling dielectric layer156is surrounded by a first charge storage layer154, and laterally surrounds a portion of the first vertical semiconductor channel61. Each adjoining set of a first blocking dielectric layer152, a first charge storage layer154, and a first tunneling dielectric layer156collectively constitute a first memory film150, which can store electrical charges with a macroscopic retention time. In some embodiments, a first blocking dielectric layer152may not be present in the first memory film150at this step, and a first blocking dielectric layer may be subsequently formed after formation of backside recesses. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours. Each contiguous set of material portions that fills a first-tier memory opening149constitutes a first memory opening fill structure57, which can include an epitaxial channel portion11, a first memory film150, a first vertical semiconductor channel61, and a first dielectric core162. Thus, each first-tier memory opening149can be filled with an instance of a first memory opening fill structure57. Each first-tier support opening119can be filled with a first-tier support opening fill structure17, which can include an epitaxial channel portion11, a first memory film150, a first vertical semiconductor channel61, and a first dielectric core162.

Referring toFIGS. 5A and 5B, the exemplary structure is illustrated after formation of the first memory opening fill structures57in the first-tier memory openings149and formation of the first-tier support opening fill structures17in the first-tier support openings119. Each layer (such as the first blocking dielectric layer152, the first charge storage layer154, the first tunneling dielectric layer156, the first outer semiconductor channel layer611, and the first inner semiconductor channel layer612) within each first-tier support opening fill structure17can have the same composition and the same thickness as the corresponding layer within a first memory opening fill structure57. The first memory opening fill structures57can be arranged as a plurality of two-dimensional periodic arrays in the memory array region100. Likewise, the first-tier support opening fill structures17can be arranged as a plurality of two-dimensional periodic arrays in the contact region200.

FIGS. 6A-6Hillustrate a region overlying a first memory opening fill structure57of the first exemplary structure during formation of joint-level doped semiconductor portions and joint-level material layers according to the first embodiment of the present disclosure. As used herein, a “joint level” refers to a level at which two structures are adjoined to each other. Specifically, a first memory opening fill structure57can be adjoined to a second memory opening fill structure to be subsequently formed at the joint level, and a first-tier support opening fill structure17can be adjoined to a second support opening fill structure to be subsequently formed at the joint level.

Referring toFIG. 8A, a first joint-level doped semiconductor layer173L is deposited over the first tier structure, which includes the first alternating stack (131,142), the first-tier cap dielectric layer172, the first memory opening fill structures57, and the first support opening fill structures17. The first joint-level doped semiconductor layer173L includes a first doped semiconductor material, which can be, for example, doped amorphous silicon, doped polysilicon, or a doped silicon-germanium alloy. The first doped semiconductor material can be doped with dopants of the first conductivity type, i.e., the same conductivity type as the conductivity type of the semiconductor material layer10. For example, if the semiconductor material layer10is doped with p-type dopants, the first joint-level doped semiconductor layer173L can be doped with p-type dopants. The dopant concentration of the first joint-level doped semiconductor layer173L can be in a range from 1.0×1015/cm3to 1.0×1019/cm3, although lower and higher dopant concentrations can also be employed. The thickness of the first joint-level doped semiconductor layer173L can be in a range from 20 nm to 100 nm, although lesser and greater thicknesses can also be employed. The first joint-level doped semiconductor layer173L can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition) or a non-conformal deposition method (such as plasma enhanced chemical vapor deposition).

Referring toFIG. 6B, a photoresist layer147can be applied over the first joint-level doped semiconductor layer173L and lithographically patterned to cover each of the first memory opening fill structures57and each of the first-tier support opening fill structures17. Physically exposed portions of the first joint-level doped semiconductor layer173L can be removed by an anisotropic etch. Each remaining portion of the first joint-level doped semiconductor layer173L constitutes a first joint-level doped semiconductor portion173. Each first joint-level doped semiconductor portion173covers and protects the underlying first vertical semiconductor channel61from oxidation during a subsequent oxidation process. The photoresist layer can be subsequently removed, for example, by ashing. The width (e.g., diameter) of the doped semiconductor portion173can be smaller than that of the first memory opening149(e.g., 20-25 nm smaller than a 100 nm first memory opening149) but larger than that of the first memory cavity149′ (e.g., about 20 nm larger than a 60 nm first memory cavity149′) to account for misalignment of the layers (e.g., about 10 nm misalignment).

Referring toFIG. 6C, an oxidation process is performed to convert physically exposed surface portions of each first joint-level doped semiconductor portion173into a dielectric oxide material. Each oxidized surface portion of the first joint-level doped semiconductor portions173constitutes a dielectric oxide portion174′, which includes a dielectric oxide of the semiconductor material of the first joint-level doped semiconductor portions173, and may include silicon oxide. Thermal oxidation or plasma oxidation may be employed to form the dielectric oxide portions174′. The thickness of each dielectric oxide portion174′, as measured between an inner sidewall and an outer sidewall, can be in a range from 10 nm to 50 nm, such as 10 to 15 nm, although lesser and greater thicknesses can also be employed. In an alternative embodiment shown in the dashed line inset inFIG. 6C, only the sidewalls of the first joint-level doped semiconductor portions173are oxidized to form a first annular dielectric spacer174. In this alternative embodiment, a mask147, such as the patterned photoresist layer used to etch portions173, is left on the top surface of the etched portions173while leaving the sidewalls of the portions173exposed. The exposed sidewalls of the portions173are then oxidized to form the first annular dielectric spacers174followed by removing the mask147.

Referring toFIG. 6D, a first joint-level spacer material layer175, a joint-level insulating layer176, and a second joint-level spacer material layer177can be sequentially formed. The first joint-level spacer material layer175and the second joint-level spacer material layers177can include the same material as the first spacer material layers in the first alternating stack (132,142). If the first spacer material layers are provided as first sacrificial material layers142, the first joint-level spacer material layer175and the second joint-level spacer material layers177can include the same sacrificial material as the first sacrificial material layers142. If the first spacer material layers are provided as first electrically conductive layers, the first joint-level spacer material layer175and the second joint-level spacer material layers177can include the same conductive material as the first electrically conductive layers (which are formed as the first spacer material layers). The joint-level insulating layer176can include the same insulating material as the first insulating layers132. The first joint-level spacer material layer175, the joint-level insulating layer176, and the second joint-level spacer material layer177are collectively referred to as joint-level material layers180.

The first joint-level spacer material layer175can be formed over the first alternating stack (132,142) and around the first joint-level doped semiconductor portion173. The joint-level insulating layer176is formed over the first joint-level spacer material layer175. The second joint-level spacer material layer177is an additional joint-level spacer material layer that is formed over the joint-level insulating layer176. Thus, the first joint-level spacer material layer175, the joint-level insulating layer176, and the second joint-level spacer material layer177are formed over the first joint-level doped semiconductor portions173and either the dielectric oxide portion174′ or the spacer174(depending on which one is present), as well as over the first alternating stack (132,142).

The thickness of each of the first joint-level spacer material layer175, the joint-level insulating layer176, and the second joint-level spacer material layer177can be in a range from 20 nm to 100 nm, although lesser and greater thicknesses can also be employed. Each of the first joint-level spacer material layer175, the joint-level insulating layer176, and the second joint-level spacer material layer177includes portions that overlie the dielectric oxide portions174′ or the first annular dielectric spacers174, which protrude upward due to the topography caused by the dielectric oxide portions174′ or the first annular dielectric spacers174above each of the first memory opening fill structure57and each of the first-tier support opening fill structure17.

Referring toFIG. 6E, a chemical mechanical planarization (CMP) process can be optionally performed to remove protruding portions of the second joint-level spacer material layer177above each of the first memory opening fill structure57and each of the first-tier support opening fill structure17. In this case, the top surface of the joint-level insulating layer176may, or may not, be physically exposed above each of the first memory opening fill structure57and each of the first-tier support opening fill structure17. The chemical mechanical planarization process is optional, and thus, may be skipped.

Referring toFIG. 6F, a photoresist layer157can be applied over the stack of the first joint-level spacer material layer175, the joint-level insulating layer176, and the second joint-level spacer material layer177, and can be lithographically patterned to form openings over the dielectric oxide portions174′ and the first joint-level doped semiconductor portions173. The lateral dimensions of each opening in the photoresist layer157can be selected such that the outer periphery of each first joint-level doped semiconductor portion173is entirely within the area of an overlying opening in the photoresist layer157. In one embodiment, the outer periphery of each first joint-level doped semiconductor portion173can be laterally offset inward from the periphery of an overlying opening in the photoresist layer157at least by an overlay tolerance between the first memory opening fill structures and second-tier memory openings to be subsequently formed in a second tier structure to be subsequently formed, i.e., at least by the overlay tolerance between the first-tier memory openings149and the second-tier memory openings to be subsequently formed. In one embodiment, the periphery of each opening in the photoresist layer157can be located outside the area of the respective underlying dielectric oxide portion174′ or the first annular dielectric spacers174. In another embodiment shown by the dashed lines, the periphery of each opening in the photoresist layer157can be located even with or inside the area of the respective underlying dielectric oxide portion174′ or the first annular dielectric spacers174.

An anisotropic etch process can be performed to etch the portions of the second joint-level spacer material layer177, the joint-level insulating layer176, and the first joint-level spacer material layer175that are located within the areas of the openings in the photoresist layer157. The photoresist layer157is employed as an etch mask during the anisotropic etch process. The chemistry of the various steps of the anisotropic etch process can be selected to sequentially etch each material of the second joint-level spacer material layer177, the joint-level insulating layer176, and the first joint-level spacer material layer175selective to materials of underlying layers. Thus, the material of the second joint-level spacer material layer177can be etched selected to the material of the joint-level insulating layer176in a first etch step, the material of the joint-level insulating layer176can be etched selective to the material of the first joint-level spacer material layer175in a second etch step, and the material of the first joint-level spacer material layer175can be etched selective to materials of the dielectric oxide portions174′ or the spacers174and the first-tier insulating cap layer172. In one embodiment, the first and second joint-level spacer material layers (175,177) can include silicon nitride, and the joint-level insulating layer176and the first-tier insulating cap layer172can include silicon oxide. Each opening in the memory array region100that is formed through the stack of the second joint-level spacer material layer177, the joint-level insulating layer176, and the first joint-level spacer material layer175is herein referred to as a joint-level memory opening. Each opening in the contact region200that is formed through the stack of the second joint-level spacer material layer177, the joint-level insulating layer176, and the first joint-level spacer material layer175is herein referred to as a joint-level support opening. The joint-level memory openings and the joint-level support openings are herein collectively referred to as joint-level openings.

Subsequently, if the horizontal top portion of the dielectric oxide portions174′ is present then it can be etched. Alternatively, if the spacers174are formed in the step ofFIG. 6C, then the etching step can be omitted. The optional horizontal top portion of the dielectric oxide portions174′ cab be etched selective to the doped semiconductor material of the first joint-level doped semiconductor portions173by a fourth step of the anisotropic etch process. For example, a reactive ion etch step employing a chemistry selected from CF4/O2, CF4/CHF3/Ar, C2F6, C3F8, C4F8/CO, C5F8, and CH2F2can be employed to etch the dielectric semiconductor oxide material of the horizontal top portions of the dielectric oxide portions174′. Each remaining annular portion of the dielectric oxide portions174′ constitutes an annular dielectric spacer, which is herein referred to as a first annular dielectric spacer174. As used herein, an “annular” element refers to an element including a single hole therethrough. Thus, each first annular dielectric spacer174is formed from an oxidized surface portion of the first joint-level doped semiconductor portion173as provided at the processing steps ofFIG. 6B. The photoresist layer157is subsequently removed, for example, by ashing. A recessed region is provided within each volume that is laterally enclosed by sidewalls of the second joint-level spacer material layer177, the joint-level insulating layer176, and the first joint-level spacer material layer175and overlies a respective first joint-level doped semiconductor portion173and a respective first annular dielectric spacer174.

Referring toFIG. 6G, a conformal dielectric material layer including a dielectric material such as silicon oxide and/or a dielectric metal oxide (e.g., aluminum oxide) can be deposited over the top surface of the second joint-level spacer material layer177and inside the recessed regions overlying the first annular dielectric spacers174. The conformal dielectric material layer can be deposited by a conformal deposition process such as low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The conformal dielectric layer can be subsequently anisotropically etched to remove horizontal portions overlying the second joint-level spacer material layer177and the first joint-level doped semiconductor portions173. Each remaining portion of the conformal dielectric material layer inside a respective recessed region constitutes a second annular dielectric spacer178. The composition of the second annular dielectric spacers178may be the same as, or may be different from, the composition of the first annular dielectric spacers174. In one embodiment, the thickness of the conformal dielectric material layer can be selected such that each second annular dielectric spacer178overlaps with an outer periphery of a respective first annular dielectric spacer174located within the same recessed region. In another embodiment, each second annular dielectric spacer178is formed only on the top surface of each respective first annular dielectric spacer174. In one embodiment, the top surfaces of the first-tier insulating cap layer172, the first memory opening fill structures57, and the first-tier support opening fill structures17can be entirely covered by the first joint-level spacer material layer175, the first joint-level doped semiconductor portions173, the first annular dielectric spacers174, and optionally by the second annular dielectric spacers178. In one embodiment, an annular bottom surface of each second annular dielectric spacer178can directly contact a top surface of the first-tier insulating cap layer172. In another embodiment, an annular bottom surface of each second annular dielectric spacer178only contacts the top surface of each respective first annular dielectric spacer174and does not directly contact a top surface of the first-tier insulating cap layer172.

Referring toFIG. 6H, a second joint-level doped semiconductor layer is deposited in the remaining volumes of the recessed regions. The second joint-level doped semiconductor layer includes a second doped semiconductor material, which can be, for example, doped amorphous silicon, doped polysilicon, or a doped silicon-germanium alloy. The second doped semiconductor material can be doped with dopants of the first conductivity type. The second joint-level doped semiconductor layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition) or a non-conformal deposition method (such as plasma enhanced chemical vapor deposition). The entire remaining volume of each recessed region can be filled with the second joint-level doped semiconductor layer.

Excess portions of the second joint-level doped semiconductor layer can be removed from above the horizontal plane including the top surface of the second joint-level spacer material layer177by a planarization process such as chemical mechanical planarization. Each remaining portion of the second joint-level doped semiconductor layer that fills the recessed regions constitutes a second joint-level doped semiconductor portion179. The second joint-level doped semiconductor portions179can include the same doped semiconductor material as, or may include a different doped semiconductor material from, the first joint-level doped semiconductor portions173. The dopant concentration of the second joint-level doped semiconductor portions179can be in a range from 1.0×1015/cm3to 1.0×1019/cm3, although lower and higher dopant concentrations can also be employed.

Within each opening through the stack of the first joint-level spacer material layer175, the joint-level insulating layer176, and the second joint-level spacer material layer177, each of the first joint-level spacer material layer175, the joint-level insulating layer176, and the second joint-level spacer material layer177is laterally spaced from at least one joint-level doped semiconductor portion (173,179) (i.e., from the first and second joint-level doped semiconductor portions (173,179)) by at least one annular dielectric spacer (174,178), (i.e., by the first and/or second annular dielectric spacers (174,178)). Each contiguous combination of a first joint-level doped semiconductor portion173, a second joint-level doped semiconductor portion179, a first annular dielectric spacer174, and a second annular dielectric spacer178that fills a joint-level memory opening is herein referred to as a joint-level memory opening fill structure67.

Referring toFIGS. 7A and 7B, the first exemplary structure is shown at the processing steps ofFIG. 6H. Each joint-level support opening is filled with a respective contiguous combination of a first joint-level doped semiconductor portion173, a second joint-level doped semiconductor portion179, a first annular dielectric spacer174, and a second annular dielectric spacer178, which is herein referred to as a joint-level support opening fill structure27. The joint-level memory opening fill structures57and the joint-level support opening fill structures27are collectively referred to as joint-level fill structures (67,27).

Referring toFIGS. 8A and 8B, a second alternating stack (232,242) of material layers is subsequently formed on the top surface of the joint-level material layers (175,176,177). The second alternating stack (232,242) includes an alternating plurality of third material layers and fourth material layers. Each third material layer can include a third material, and each fourth material layer can include a fourth material that is different from the third material. In one embodiment, the third material can be the same as the first material of the first insulating layer132, and the fourth material can be the same as the second material of the first sacrificial material layers142.

In one embodiment, the third material layers and the fourth material layers can be second insulating layers232and second sacrificial material layers242, respectively. The third material of the second insulating layers232can be at least one insulating material. The fourth material of the second sacrificial material layers242is a sacrificial material that can be removed selective to the third material of the second insulating layers232. The second sacrificial material layers242may comprise an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layers242can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device.

In one embodiment, each second insulating layer232can include a second insulating material, and each second sacrificial material layer242can include a second sacrificial material. In this case, the second alternating stack (232,242) can include an alternating plurality of second insulating layers232and second sacrificial material layers242. The third material of the second insulating layers232can be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layers242can be formed, for example, CVD or atomic layer deposition (ALD).

The third material of the second insulating layers232can be at least one insulating material. Insulating materials that can be employed for the second insulating layers232can be any material that can be employed for the first insulating layers132. The fourth material of the second sacrificial material layers242is a sacrificial material that can be removed selective to the third material of the second insulating layers232. Sacrificial materials that can be employed for the second sacrificial material layers242can be any material that can be employed for the first sacrificial material layers142. In one embodiment, the second insulating material can be the same as the first insulating material, and the second sacrificial material can be the same as the first sacrificial material. For example, the first and second sacrificial material layers (142,242) can include silicon nitride, and the first and second insulating layers (132,232) can include silicon oxide.

The thicknesses of the second insulating layers232and the second sacrificial material layers242can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each second insulating layer232and for each second sacrificial material layer242. The number of repetitions of the pairs of a second insulating layer232and a second sacrificial material layer242can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. In one embodiment, each second sacrificial material layer242in the second alternating stack (232,242) can have a uniform thickness that is substantially invariant within each respective second sacrificial material layer242.

An insulating cap layer70can be subsequently formed over the second alternating stack (232,242). The insulating cap layer70includes a dielectric material that is different from the material of the second sacrificial material layers242. The insulating cap layer70includes a dielectric material that may be the same as, or different from, the material of the second insulating layers232. In one embodiment, the insulating cap layer70can include silicon oxide. The second alternating stack (232,242) and the insulating cap layer70constitute a second tier structure (232,242,70).

Referring toFIGS. 9A and 9B, additional stepped surfaces are formed in the second alternating stack (232,242) and in the joint-level material layers (175,176,177) in the contact region200. The additional stepped surfaces are herein referred to as second stepped surfaces. The second stepped surfaces are formed in a second stepped area, which is adjacent to, and does not overlie, the first stepped area of the first stepped surfaces within the first tier structure (132,142,172,165). The second stepped surfaces can be adjacent to, and do not overlie, the stepped interface between the first alternating stack (132,142) and the first retro-stepped dielectric material portion165.

The second stepped surfaces can be formed, for example, by forming a mask layer with an opening therein, etching a cavity within the levels of the topmost second sacrificial material layer242and the topmost second insulating layer232, and iteratively expanding the etched area and vertically recessing the cavity by etching a pair of a second insulating layer232and a second sacrificial material layer242located directly underneath the bottom surface of the etched cavity within the etched area. The second alternating stack (232,242) is patterned such that each underlying second sacrificial material layer242laterally protrudes farther than any overlying second sacrificial material layer242in the etched region, and each underlying second insulating layer232laterally protrudes farther than any overlying second insulating layer232in the etched region. Likewise, the joint-level material layers (175,176,177) such that each of the joint-level material layers (175,176,177) laterally protrude farther than any layer in the second alternating stack (232,242), and the first joint-level spacer material layer175laterally protrudes farther than the second joint-level spacer material layer177. The etched area includes the area of the contact region200, which includes the contact area for the second alternating stack (232,242) and a contact area for the first alternating stack (132,142).

Thus, the second alternating stack (232,242) is patterned to form the second stepped surfaces thereupon. The cavity formed by removal of portions of the second alternating stack (232,242) is herein referred to as a second stepped cavity. The area of the second stepped cavity includes the area of the first retro-stepped first dielectric material portion165, from which all layers of the second alternating stack (232,242) are removed. The area of the second stepped cavity further includes the area of the second stepped surfaces of the second alternating stack (232,242).

Dielectric material is deposited to fill the second stepped cavity. Excess portions of the dielectric material overlying the topmost surface of the second alternating stack (232,242) are removed, for example, by chemical mechanical planarization. The remaining portion of the deposited dielectric material is retro-stepped, and thus, forms a second dielectric material portion, which is herein referred to as a second retro-stepped dielectric material portion265. The second retro-stepped dielectric material portion265is located on, and over, the second stepped surfaces of the second alternating stack (232,242). The second retro-stepped dielectric material portion265is formed on the second stepped surfaces. The contact region200comprises a region of the first stepped surfaces and a region of the second stepped surfaces. Upon formation of the second retro-stepped dielectric material portion265, the second retro-stepped dielectric material portion265is incorporated into the second tier structure (232,242,70,265), i.e., becomes an element of the second tier structure (232,242,70,265).

The first stepped surfaces and the second stepped surfaces are collectively referred to as “stepped surfaces.” A first portion of the stepped surfaces is the first stepped surfaces located in the first tier structure (132,142,172,165). As second portion of the stepped surfaces is the second stepped surfaces located in the second tier structure (232,242,70,265). The first stepped surfaces and the second stepped surfaces are located within the contact region200.

The region of the stepped surfaces is herein referred to as a terrace region. Each sacrificial material layer (142,242) among the first and second sacrificial material layers (142,242) that is not a bottommost first sacrificial material layer142laterally extends less than any underlying layer among the first and second sacrificial material layers (142,242). The terrace region includes stepped surfaces of the first and second alternating stacks (132,142,232,242) that continuously extend from a bottommost layer within the first alternating stack (132,142) to a topmost layer within the second alternating stack (232,242).

Referring toFIGS. 10A and 10B, second-tier openings (249,219) are formed through the second tier structure (232,242,265,70) to the top surface of the first tier structure (132,142,172,165). The second-tier openings (249,219) include second-tier memory openings249that are formed in the memory array region100and second-tier support openings219that are formed in the contact region200. Each adjoining combination of a first-tier memory opening149, a joint-level memory opening, and a second-tier memory opening249collectively constitutes a memory opening, or an inter-tier memory opening. Each adjoining combination of a first-tier support opening119, a joint-level support opening, and a second-tier support opening (that is formed over a respective joint-level support opening) collectively constitutes a support opening, or an inter-tier support opening.

The second-tier memory openings249are formed through the second tier structure (232,242,70,265) in areas that overlap with the joint-level memory opening fill structures67, i.e., with the joint-level memory openings. Thus, each second-tier memory opening249can be formed on top of a respective joint-level memory opening fill structure67. In one embodiment, the bottom surface of each second-tier memory opening249can be formed within a periphery of a top surface of an underlying joint-level memory opening fill structure67, i.e., can have an areal overlap with the top surface of the underlying joint-level memory opening fill structure67. The second-tier support openings219are formed through the second tier structure (232,242,70,265) such that each second-tier support opening219is formed in an area that overlaps with the area of an underlying joint-level support opening fill structures27. In one embodiment, the same lithographic mask may be employed to pattern the first-tier openings (149,119) and the second-tier openings (249,219).

The second-tier openings (249,219) can be formed by a combination of lithographic patterning and an anisotropic etch. For example, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the second tier structure (232,242,265,70), and can be lithographically patterned to form openings within the lithographic material stack. The pattern in the lithographic material stack can be transferred through the entirety of the second tier structure (232,242,265,70) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the second tier structure (232,242,265,70) underlying the openings in the patterned lithographic material stack are etched to form the second-tier openings (249,219). In other words, transfer of the pattern in the patterned lithographic material stack through the second tier structure (232,242,265,70) forms the second-tier openings (249,219).

In one embodiment, the chemistry of the anisotropic etch process employed to etch through the materials of the second alternating stack (232,242) can alternate to optimize etching of the third and fourth materials in the second alternating stack (232,242) while providing a comparable average etch rate for the second dielectric material portion265. The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the second-tier openings (249,219) can be substantially vertical, or can be tapered.

The lateral dimensions (e.g., a diameter) of the second-tier openings (249,219) can be comparable to the lateral dimensions of the first-tier openings (149,119). For example, the lateral dimensions of the second-tier openings (249,219) can be from about 20 nm to 200 nm at an upper portion of each second-tier opening (249,219), and can be about 10 nm to 150 nm at a lower portion of each second-tier opening (249,219). In one embodiment, the second-tier memory openings249and the first-tier memory openings149can be formed as an array of openings, which can be a periodic two-dimensional array of openings. The second-tier support openings219and the first-tier support openings119can be formed as discrete openings that are mutually separated from one another, and may, or may not, form a periodic two-dimensional array pattern. Subsequently, the patterned lithographic material stack can be subsequently removed, for example, by ashing.

FIGS. 11A-11Fillustrate a region including a stack of a first memory opening fill structure57, a joint-level memory opening fill structure67, and a second-tier memory opening249during formation of a second memory opening fill structure.FIG. 11Aillustrate the region at the processing steps ofFIGS. 10A and 10B, i.e., after formation of the second-tier memory openings249and the second-tier support openings219.

Referring toFIG. 11B, a stack of layers including a second blocking dielectric layer252, a second charge storage layer254, a second tunneling dielectric layer256, and an optional second outer semiconductor channel layer621can be sequentially deposited in the second-tier memory openings249. Each adjoining set of a second blocking dielectric layer252, a second charge storage layer254, and a second tunneling dielectric layer256collectively constitute a second memory film250, which can store electrical charges with a macroscopic retention time.

The second blocking dielectric layer252can include a single dielectric material layer or a stack of a plurality of dielectric material layers. In one embodiment, the second blocking dielectric layer can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of the at least one metallic element and oxygen, or may consist essentially of the at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. Any of the materials that can be employed for the first blocking dielectric layer152can be employed for the second blocking dielectric layer252.

Subsequently, the second charge storage layer254can be formed. In one embodiment, the second charge storage layer254can be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the second charge storage layer254can include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions (e.g., floating gates), for example, by being formed within lateral recesses into second sacrificial material layers242. In one embodiment, the second charge storage layer254includes a silicon nitride layer. In one embodiment, the second sacrificial material layers242and the second insulating layers232can have vertically coincident sidewalls, and the second charge storage layer254can be formed as a single continuous layer.

In another embodiment, the second sacrificial material layers242can be laterally recessed with respect to the sidewalls of the second insulating layers232, and a combination of a deposition process and an anisotropic etch process can be employed to form the second charge storage layer254as a plurality of memory material portions that are vertically spaced apart. While the present disclosure is described employing an embodiment in which the second charge storage layer254is a single continuous layer, embodiments are expressly contemplated herein in which the second charge storage layer254is replaced with a plurality of memory material portions (which can be charge trapping material portions or electrically isolated conductive material portions) that are vertically spaced apart.

The second charge storage layer254can be formed as a single second charge storage layer of homogeneous composition, or can include a stack of multiple second charge storage layers. The multiple second charge storage layers, if employed, can comprise a plurality of spaced-apart floating gate material layers that contain conductive materials (e.g., metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof) and/or semiconductor materials (e.g., polycrystalline or amorphous semiconductor material including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or additionally, the second charge storage layer254may comprise an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the second charge storage layer254may comprise conductive nanoparticles such as metal nanoparticles, which can be, for example, ruthenium nanoparticles. The second charge storage layer254can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. The thickness of the second charge storage layer254can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

The second tunneling dielectric layer256includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The second tunneling dielectric layer256can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the second tunneling dielectric layer256can include a stack of a second silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the second tunneling dielectric layer256can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the second tunneling dielectric layer256can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

The optional second outer semiconductor channel layer621includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second outer semiconductor channel layer621includes amorphous silicon or polysilicon. The second outer semiconductor channel layer621can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second outer semiconductor channel layer621can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. A second memory cavity249′ is formed in the volume of each second-tier memory opening249that is not filled with the deposited material layers (252,254,256,621).

Referring toFIG. 11C, the optional second outer semiconductor channel layer621, the second tunneling dielectric layer256, the second charge storage layer254, the second blocking dielectric layer252are sequentially anisotropically etched employing at least one anisotropic etch process. The portions of the second outer semiconductor channel layer621, the second tunneling dielectric layer256, the second charge storage layer254, and the second blocking dielectric layer252located above the top surface of the second-tier insulating cap layer70can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the second outer semiconductor channel layer621, the second tunneling dielectric layer256, the second charge storage layer254, and the second blocking dielectric layer252at a bottom of each second memory cavity249′ can be removed to form openings in remaining portions thereof. Each of the second outer semiconductor channel layer621, the second tunneling dielectric layer256, the second charge storage layer254, and the second blocking dielectric layer252can be etched by a respective anisotropic etch process employing a respective etch chemistry, which may, or may not, be the same for the various material layers.

Each remaining portion of the second outer semiconductor channel layer621can have a tubular configuration. The second charge storage layer254can comprise a charge trapping material or a floating gate material. In one embodiment, each second charge storage layer254can include a vertical stack of second charge storage regions that store electrical charges upon programming. In one embodiment, the second charge storage layer254can be a second charge storage layer in which each portion adjacent to the second sacrificial material layers242constitutes a second charge storage region.

A surface of an upper portion of the at least one joint-level doped semiconductor portion (i.e., the first and second joint-level doped semiconductor portions (173,179)) can be physically exposed underneath the opening through the second outer semiconductor channel layer621, the second tunneling dielectric layer256, the second charge storage layer254, and the second blocking dielectric layer252. Optionally, the physically exposed semiconductor surface at the bottom of each second memory cavity249′ can be vertically recessed so that the recessed semiconductor surface underneath the second memory cavity249′ is vertically offset from the topmost surface of the second joint-level doped semiconductor portions179by a recess distance.

A second tunneling dielectric layer256is located over the second charge storage layer254. A set of a second blocking dielectric layer252, a second charge storage layer254, and a second tunneling dielectric layer256in a second-tier memory opening249constitutes a memory film250, which includes a plurality of second charge storage regions (as embodied as the second charge storage layer254) that are insulated from surrounding materials by the second blocking dielectric layer252and the second tunneling dielectric layer256. In one embodiment, the second outer semiconductor channel layer621, the second tunneling dielectric layer256, the second charge storage layer254, and the second blocking dielectric layer252can have vertically coincident sidewalls.

Referring toFIG. 11D, a second inner semiconductor channel layer622can be deposited directly on the semiconductor surface of the second joint-level doped semiconductor portion179, and directly on the second outer semiconductor channel layer621. The second inner semiconductor channel layer622includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second inner semiconductor channel layer622includes amorphous silicon or polysilicon. The second inner semiconductor channel layer622can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second inner semiconductor channel layer622can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed. The second inner semiconductor channel layer622may partially fill the second memory cavity249′ in each memory opening, or may fully fill the cavity in each memory opening.

The materials of the second outer semiconductor channel layer621and the second inner semiconductor channel layer622are collectively referred to as a second semiconductor channel material. In other words, the second semiconductor channel material is a set of all semiconductor material in the second outer semiconductor channel layer621and the second inner semiconductor channel layer622.

In case the second memory cavity249′ in each second-tier memory opening is not completely filled by the second inner semiconductor channel layer622, a second dielectric core layer262L can be deposited in the second memory cavity249′ to fill any remaining portion of the second memory cavity249′ within each second-tier memory opening. The second dielectric core layer262L includes a dielectric material such as silicon oxide or organosilicate glass. The second dielectric core layer262L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG. 11E, the horizontal portion of the second dielectric core layer262L can be removed, for example, by a recess etch from above the top surface of the second-tier insulating cap layer70. Each remaining portion of the second dielectric core layer262L constitutes a dielectric core262. Further, the horizontal portion of the second inner semiconductor channel layer622located above the top surface of the second-tier insulating cap layer70can be removed by a planarization process, which can employ a recess etch or chemical mechanical planarization (CMP). Each remaining portion of the second inner semiconductor channel layer622can be located entirety within a second-tier memory opening249or entirely within a second support opening219.

Each adjoining pair of a second outer semiconductor channel layer621and a second inner semiconductor channel layer622can collectively form a second vertical semiconductor channel62through which electrical current can flow when a vertical NAND device including the second vertical semiconductor channel62is turned on. A second tunneling dielectric layer256is surrounded by a second charge storage layer254, and laterally surrounds a portion of the second vertical semiconductor channel62. In some embodiments, a second blocking dielectric layer252may not be present in the second memory film250at this step, and a second blocking dielectric layer may be subsequently formed after formation of backside recesses. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.

Referring toFIG. 11F, the top surface of each second dielectric core262can be recessed below the top surface of the insulating cap layer70, for example, by a recess etch to a depth that is located between the top surface of the insulating cap layer70and the bottom surface of the insulating cap layer70. Drain regions63can be formed by depositing a doped semiconductor material within each recessed region above the second dielectric cores262. The drain regions63can have a doping of a second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the drain regions63can be in a range from 5.0×1019/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material can be removed from above the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP) or a recess etch to form the drain regions63.

Each combination of a first memory film150and a first vertical semiconductor channel61(which is a lower portion of the vertical semiconductor channel) within a first-tier memory opening149constitutes a first-tier memory stack structure (150,61). Each combination of a second memory film250and a second vertical semiconductor channel62(which is an upper portion of the vertical semiconductor channel) within a second-tier memory opening249constitutes a second-tier memory stack structure (250,62). Each contiguous combination of a first vertical semiconductor channel61, a set of at least one joint-level doped semiconductor portions (173,179) (which can include a first joint-level doped semiconductor portion173and a second joint-level doped semiconductor portion179), a second vertical semiconductor channel62constitutes a vertical semiconductor channel (61,173,179,62). Each combination of an epitaxial channel portion11(if present), a first-tier memory stack structure (150,61), a first dielectric core162, a joint-level memory opening fill structure67, a second-tier memory stack structure (250,62), a second dielectric core262, and a drain region63within an inter-tier memory opening is herein referred to as a memory opening fill structure (57,67,77), or an inter-tier memory opening fill structure. Each combination of an epitaxial channel portion11(if present), a first-tier memory stack structure (150,61), a first dielectric core162, a joint-level support opening fill structure27, a second-tier memory stack structure (250,62), a second dielectric core262, and a drain region63within an inter-tier support opening is herein referred to as a support opening fill structure (17,27,37), or an inter-tier support opening fill structure.

FIGS. 12A and 12Billustrate the first exemplary structure after formation of the inter-tier memory opening fill structures (57,67,77) and the inter-tier support opening fill structures (17,27,37), i.e., after the processing steps ofFIG. 11F.

Referring toFIGS. 13A, 13B, and 14A, a contact level dielectric layer80can be formed over the second tier structure (232,242,265,70). The contact level dielectric layer80includes a dielectric material such as silicon oxide, a dielectric metal oxide, and/or organosilicate glass. In one embodiment, the contact level dielectric layer80can be composed primarily of a silicon oxide material. The thickness of the contact level dielectric layer80can be in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

If the spacer material layers (142,242,175,177) are electrically conductive layers, then the subsequent processing steps for replacement of the sacrificial material layers with electrically conductive layers can be omitted.

In case the spacer material layers (142,242,175,177) are sacrificial material layers, a photoresist layer (not shown) can be applied over the contact level dielectric layer80, and is lithographically patterned to form at least one elongated opening in each area in which formation of a backside contact via structure is desired. The pattern in the photoresist layer can be transferred through the contact level dielectric layer80, the second tier structure (232,242,265,70), and the first tier structure (132,142,172,165) employing an anisotropic etch to form the at least one backside trench79, which extends at least to the top surface of the substrate (9,10). In one embodiment, the at least one backside trench79can include a source contact opening in which a source contact via structure can be subsequently formed.

An etchant that selectively etches the second material of the sacrificial material layers (142,242) and the joint-level spacer material layers (175,177) with respect to the materials of the insulating layers (132,232) and the semiconductor material(s) of the substrate (9,10) can be introduced into the at least one backside trench79, for example, employing an etch process. Backside recesses43are formed in volumes from which the sacrificial material layers (142,242) and the joint-level spacer material layers (175,177) are removed. Specifically, first backside recesses are formed in the volumes from which the first sacrificial material layers142are removed, second backside recesses are formed in the volumes from which the second sacrificial material layers242are removed, and joint-level backside recesses are formed in the volumes from which the joint-level spacer material layers (175,177) are removed.

The removal of the second material of the sacrificial material layers (142,242) and the sacrificial materials of the joint-level sacrificial material layers (175,177) can be selective to the materials of the insulating layers (132,232,176,172,70), the materials of the retro-stepped dielectric material portions (165,265), the semiconductor material(s) of the substrate (9,10), and the material of the outermost layer of the memory films50. Each backside recess43can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess43can be greater than the height of the backside recess43. The inter-tier memory openings and the inter-tier support openings are herein referred to as front side openings or front side cavities in contrast with the backside recesses43. In one embodiment, the memory array region100comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate (9,10). In this case, a first subset of the backside recesses43formed by removal of the first and second sacrificial material layers (142,242) can define spaces for receiving a respective word line of the array of monolithic three-dimensional NAND strings, while a second subset of the backside recesses formed by removal of the inter-tier spacer material layers (175,177) can define spaces for receiving a set of at least one channel control electrically conductive layer that controls electrical current through the vertical semiconductor channel (61,173,179,62) without controlling any charge storage elements that are provided in the first and second memory films (150,250).

Each of the plurality of backside recesses43can extend substantially parallel to the top surface of the substrate (9,10). A backside recess43can be vertically bounded by a top surface of an underlying insulating layer (132,232,172, or176) and a bottom surface of an overlying insulating layer (132,232,172,176, or70). In one embodiment, each backside recess43can have a uniform height throughout.

Subsequently, physically exposed surface portions of the optional epitaxial channel portions11and the semiconductor material layer10may be converted into dielectric material portions by thermal conversion and/or plasma conversion of the semiconductor materials into dielectric materials. For example, thermal conversion and/or plasma conversion can be employed to convert a surface portion of each epitaxial channel portion11into a tubular dielectric spacer (shown inFIG. 14A), and to convert each physically exposed surface portion of the semiconductor material layer10into a planar dielectric portion616(shown inFIG. 15B).

Referring toFIGS. 14B, 15A, and 15B, a backside blocking dielectric layer44can be optionally formed. The backside blocking dielectric layer44, if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the backside recesses43. In case the first and second blocking dielectric layers (152,252) are present within each memory opening, the backside blocking dielectric layer44is optional. In case the first and second blocking dielectric layers (152,252) are omitted, the backside blocking dielectric layer44is present

The backside blocking dielectric layer44can be formed in the backside recesses43and on a sidewall of the backside trench79. The backside blocking dielectric layer can be formed directly on horizontal surfaces of the insulating layers (132,232,172,176,170) and physically exposed sidewalls of the first and second blocking dielectric layers (152,252) within the backside recesses43. If the backside blocking dielectric layer44is formed, formation of the tubular dielectric spacers116and the planar dielectric portion616prior to formation of the backside blocking dielectric layer44is optional. In one embodiment, the backside blocking dielectric layer44can be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer44can consist essentially of aluminum oxide. The thickness of the backside blocking dielectric layer44can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be employed.

At least one conducive material can be deposited to form electrically conductive layers (146,246,346). The at least one conductive material can include a metallic liner and a conductive fill material layer. The metallic liner can include a metallic nitride material such as TiN, TaN, WN, an alloy thereof, or a stack thereof. The metallic liner functions as a diffusion barrier layer and an adhesion promotion layer. The metallic liner can be deposited by a conformal deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), and can have a thickness in a range from 1 nm to 6 nm, although lesser and greater thicknesses can also be employed. The conductive fill material layer can be deposited directly on the metallic liner by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The conductive fill material layer includes a conductive material. The conductive material can include at least one elemental metal such as W, Cu, Co, Mo, Ru, Au, and Ag. Additionally or alternatively, the conductive fill material layer (146,246, or346) can include at least one intermetallic metal alloy material. Each intermetallic metal alloy material can include at least two metal elements selected from W, Cu, Co, Mo, Ru, Au, Ag, Pt, Ni, Ti, and Ta. In one embodiment, the conductive fill material layer can consist essentially of W, Co, Mo, or Ru.

Each portion of the at least one conducive material that fills a backside recess43constitutes an electrically conductive layer (146,246, or346). The electrically conductive layers (146,246,346) include first electrically conductive layers146that are formed in the first backside recesses in the first tier structure, second electrically conductive layers246that are formed in the second backside recesses in the second tier structure, and joint-level electrically conductive layers346formed at the joint level, i.e., between the first tier structure and the second tier structure and around each of the joint-level fill structures (67,27). The portion of the at least one conductive material that excludes the electrically conductive layers (146,246,346) constitutes continuous metallic material layer46L. A plurality of electrically conductive layers (146,246,346) can be formed in the plurality of backside recesses43, and the continuous metallic material layer46L can be formed on the sidewalls of each backside trench79and over the contact level dielectric layer80. A backside cavity is present in the portion of each backside trench79that is not filled with the backside blocking dielectric layer and the continuous metallic material layer46L.

While the backside recesses43remain as cavities, i.e., between removal of the sacrificial material layers (142,242,175,177) and formation of the electrically conductive layers (146,246,346) in the backside recesses43, the memory opening fill structures (57,67,77) and the support pillar structures (17,27,37) mechanically support the insulating layers (132,142,172,176,70) and the contact level dielectric layer80. Thus, each first sacrificial material layer142can be replaced with a respective first electrically conductive layer146, each second sacrificial material layer242can be replaced with a respective second electrically conductive layer246, and each joint-level spacer material layer (175,177) can be replaced with a respective joint-level electrically conductive layer346, while the memory opening fill structures (57,67,77) and the support pillar structures (17,27,37) provide structural support to the insulating layers (132,142,172,176,70) and the contact level dielectric layer80.

Referring toFIGS. 16A and 16B, the deposited metallic material of the continuous electrically conductive material layer46L is etched back from the sidewalls of each backside trench79and from above the contact level dielectric layer80, for example, by an isotropic wet etch, an anisotropic dry etch, or a combination thereof. The electrically conductive layers (146,246,346) in the backside recesses are not removed by the etch process. In one embodiment, the sidewalls of each electrically conductive layer (146,246,346) can be vertically coincident after removal of the continuous electrically conductive material layer46L.

Each of the first and second electrically conductive layers (146,246) can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each of the first and second electrically conductive layers (146,246,346) are the control gate electrodes for the vertical memory devices including the first memory film150, the second memory film250, and the vertical semiconductor channel (61,173,179,62). In other words, each of the first and second electrically conductive layers (146,246,346) can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices. In contrast, the joint-level electrically conductive layers346do not control any charge storage, but controls the current flow through the joint-level doped semiconductor portions (173,179).

An insulating material layer can be formed in the at least one backside trench79and over the contact level dielectric layer80by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in a range from 1.5 nm to 60 nm, although lesser and greater thicknesses can also be employed. An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact level dielectric layer80and at the bottom of each backside trench79. Each remaining portion of the insulating material layer constitutes an insulating spacer74. The anisotropic etch can continue to etch through physically exposed portions of the planar dielectric portion, if present, in each backside trench79. Thus, an insulating spacer74is formed in each backside trench79directly on physically exposed sidewalls of the electrically conductive layers (146,246).

A source region60can be formed underneath each backside trench79by implantation of electrical dopants into physically exposed surface portions of the semiconductor material layer10. Each source region60is formed in a surface portion of the substrate (9,10) that underlies a respective opening through the insulating spacer74. Due to the straggle of the implanted dopant atoms during the implantation process and lateral diffusion of the implanted dopant atoms during a subsequent activation anneal process, each source region60can contact a bottom surface of the insulating spacer74. A surface portion of the semiconductor material layer10adjoining a source region60and continuously extending to the epitaxial channel portions11constitutes a horizontal semiconductor channel59, which is a common portion of a plurality of semiconductor channels (59,11,61,173,179,61) that include the vertical semiconductor channels (61,173,179,62) within the memory opening fill structures (57,67,77).

A backside contact via structure76can be formed within each cavity. Each contact via structure76can fill a respective cavity. The backside contact via structures76can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity) of the backside trench79. For example, the at least one conductive material can include a conductive liner (not expressly shown) and a conductive fill material portion (not expressly shown). The conductive liner can include a metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion can include a metal or a metallic alloy. For example, the conductive fill material portion can include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.

The at least one conductive material can be planarized employing the contact level dielectric layer80overlying the alternating stacks (132,146,232,246) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact level dielectric layer80can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches79constitutes a backside contact via structure76. Each backside contact via structure76can be formed directly on a top surface of a source region60. Each backside contact via structure76can contact a respective source region60, and can be laterally surrounded by a respective insulating spacer74.

Referring toFIGS. 17A and 17B, additional contact via structures (88,86) can be formed through the contact level dielectric layer80and through the retro-stepped dielectric material portions (165,265). For example, drain contact via structures88can be formed through the contact level dielectric layer80on each drain region63. Each drain contact via structure88can be formed through the contact level dielectric layer80on each of the drain regions63, while not forming any conductive structure through the contact level dielectric layer80over the doped semiconductor material portions of the dummy drain regions163.

Layer contact via structures86can be formed in the terrace region on the electrically conductive layers (146,246,346) through the contact level dielectric layer80, and through the retro-stepped dielectric material portions (165,265). The layer contact via structures86vertically extend at least through a dielectric material portion (i.e., the second retro-stepped dielectric material portion265) within the second tier structure (232,246,265,70), and contact a respective electrically conductive layer selected from the first and second electrically conductive layers (146,246) and the joint-level electrically conductive layers346. Peripheral gate contact via structures (not shown) and peripheral active region contact via structures (not shown) can be formed through the retro-stepped dielectric material portions (165,265) directly on respective nodes of the peripheral devices700(shown inFIG. 1).

While the present disclosure is described employing an embodiment in which the first and second spacer material layers are formed as first and second sacrificial material layers (142,242), respectively, and the joint-level spacer material layers (175,177) are formed as additional sacrificial material layers, embodiments are expressly contemplated herein in which the first and second spacer material layers are formed as first and second electrically conductive layers (146,246) at the time of formation of the alternating stacks, and the joint-level spacer material layers (175,177) are formed as joint-level electrically conductive layers at the time of formation of the joint-level spacer material layers (175,177). In this case, processing steps employed to replace the sacrificial material layers (142,242,175,177) with the electrically conductive layers (146,246,346) can be omitted.

The first exemplary structure comprises at least one annular dielectric spacer (174,178), which includes a first annular dielectric spacer174and a second annular dielectric spacer178. Further, the first exemplary structure comprises at least one joint-level doped semiconductor portion (173,179), which includes a first joint-level doped semiconductor portion173and a second joint-level doped semiconductor portion179. The first annular dielectric spacer174contacts a top surface of the first memory film150and laterally surrounds the first joint-level doped semiconductor portion173. The second annular dielectric spacer178contacts at least one of a top surface and outer sidewall of the first annular dielectric spacer174and a bottom surface of the second alternating stack (232,246) and laterally surrounds the second joint-level doped semiconductor portion179.

A second exemplary structure can be derived from the first exemplary structure by modifying the joint-level fill structures (67,27) in which the second annular dielectric spacer is formed by oxidation of a semiconductor layer rather than by deposition of a dielectric layer. For example, the first exemplary structure ofFIGS. 5A and 5Bcan be employed to form the second exemplary structure.

Referring toFIG. 18A, a first joint-level doped semiconductor layer173L is deposited over the first tier structure, which includes the first alternating stack (131,142), the first-tier cap dielectric layer172, the first memory opening fill structures57, and the first support opening fill structures17. The first joint-level doped semiconductor layer173L includes a first doped semiconductor material, which may have the same composition and the same thickness as in the first embodiment.

Referring toFIG. 18B, a photoresist layer147can be applied over the first joint-level doped semiconductor layer173L and lithographically patterned to cover each of the first memory opening fill structures57and each of the first-tier support opening fill structures17. Physically exposed portions of the first joint-level doped semiconductor layer173L can be removed by an anisotropic etch. Each remaining portion of the first joint-level doped semiconductor layer173L constitutes a first joint-level doped semiconductor portion173. Each first joint-level doped semiconductor portion173covers and protects the underlying first vertical semiconductor channel61from oxidation during a subsequent oxidation process. In one embodiment, the bottom surface of each first joint-level doped semiconductor portion173can contact an entire top surface of an underlying first memory opening fill structure57. The photoresist layer can be subsequently removed, for example, by ashing.

Referring toFIG. 18C, in one embodiment, an oxidation process is performed to convert physically exposed surface portions of each first joint-level doped semiconductor portion173into a dielectric oxide material. Each oxidized surface portion of the first joint-level doped semiconductor portions173constitutes a dielectric oxide portion, which is herein referred to as a first dielectric oxide portion174′, which includes a dielectric oxide of the semiconductor material of the first joint-level doped semiconductor portions173, and may include silicon oxide. Thermal oxidation or plasma oxidation may be employed to form the first dielectric oxide portions174′. The thickness of each first dielectric oxide portion174′, as measured between an inner sidewall and an outer sidewall, can be in a range from 10 nm to 50 nm, although lesser and greater thicknesses can also be employed. In an alternative embodiment shown in the dashed line inset inFIG. 18C, only the sidewalls of the first joint-level doped semiconductor portions173are oxidized to form a first annular dielectric spacer174. In this alternative embodiment, a mask147, such as the patterned photoresist layer used to etch portions173, is left on the top surface of the etched portions173while leaving the sidewalls of the portions173exposed. The exposed sidewalls of the portions173are then oxidized to form the first annular dielectric spacers174followed by removing the mask147.

Referring toFIG. 18D, a first joint-level spacer material layer175can be deposited over the first dielectric oxide portion174′ or the first annular dielectric spacers174and the first joint-level doped semiconductor portion173. The first joint-level spacer material layer175can include the same material as the first spacer material layers in the first alternating stack (132,142). If the first spacer material layers are provided as first sacrificial material layers142, the first joint-level spacer material layer175can include the same sacrificial material as the first sacrificial material layers142. If the first spacer material layers are provided as first electrically conductive layers, the first joint-level spacer material layer175can include the same conductive material as the first electrically conductive layers (which are formed as the first spacer material layers).

The first joint-level spacer material layer175can be formed over the first alternating stack (132,142) and around the first joint-level doped semiconductor portion173and one of the first dielectric oxide portions174′ or the first annular dielectric spacers174. The thickness of the first joint-level spacer material layer175can be in a range from 20 nm to 100 nm, although lesser and greater thicknesses can also be employed. A chemical mechanical planarization (CMP) process can be performed to remove protruding portions of the first joint-level spacer material layer175and a horizontal top portion of each first dielectric oxide portion174′ from above a horizontal plane including top surfaces of the first joint-level doped semiconductor portions173. Each remaining annular portion of the first dielectric oxide portions174′ (if present) constitutes an annular dielectric spacer, which is herein referred to as a first annular dielectric spacer174. Thus, each first annular dielectric spacer174is formed from an oxidized surface portion of the first joint-level doped semiconductor portion173as provided at the processing steps ofFIG. 18BorFIG. 18C. In one embodiment, the chemical mechanical planarization process can further remove portions of the first annular dielectric spacers174and surface portions of the first joint-level doped semiconductor portions173from above a horizontal plane including the top surface of the first joint-level spacer material layer175. In this case, the top surfaces of the first joint-level spacer material layer175, the first annular dielectric spacers174, and the first joint-level doped semiconductor portions173can be within a same horizontal plane.

Referring toFIG. 18E, a second joint-level doped semiconductor layer is deposited over the first joint-level spacer material layer175. The second joint-level doped semiconductor layer includes a second doped semiconductor material, which may have the same composition as, or have a different composition from, the material of the first joint-level doped semiconductor layer173L. The thickness of the second joint-level doped semiconductor layer may be in a range from 20 nm to 100 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer247can be applied over the second joint-level doped semiconductor layer and lithographically patterned to cover the first annular dielectric spacers174and the first joint-level doped semiconductor portions173. The lithographic mask employed to pattern the photoresist layer at the processing steps ofFIG. 18Bcan be employed again at this step. Physically exposed portions of the second joint-level doped semiconductor layer can be removed by an anisotropic etch. Each remaining portion of the second joint-level doped semiconductor layer constitutes a second joint-level doped semiconductor portion273. Each second joint-level doped semiconductor portion273covers an underlying first joint-level doped semiconductor portion173. The photoresist layer can be subsequently removed, for example, by ashing.

An oxidation process is performed to convert physically exposed surface portions of each second joint-level doped semiconductor portion273into a dielectric oxide material. Each oxidized surface portion of the second joint-level doped semiconductor portions273constitutes a dielectric oxide portion, which is herein referred to as a second dielectric oxide portion274′, which includes a dielectric oxide of the semiconductor material of the second joint-level doped semiconductor portions273, and may include silicon oxide. Thermal oxidation or plasma oxidation may be employed to form the second dielectric oxide portions274′. The thickness of each second dielectric oxide portion274′, as measured between an inner sidewall and an outer sidewall, can be in a range from 10 nm to 50 nm, although lesser and greater thicknesses can also be employed. In an alternative embodiment shown in the dashed line inset inFIG. 18E, only the sidewalls of the second joint-level doped semiconductor portions273are oxidized to form a second annular dielectric spacer274. In this alternative embodiment, a mask247, such as the patterned photoresist layer used to etch portions273, is left on the top surface of the etched portions273while leaving the sidewalls of the portions273exposed. The exposed sidewalls of the portions273are then oxidized to form the second annular dielectric spacers274followed by removing the mask \247.

Referring toFIG. 18F, a joint-level insulating layer176can be deposited over the second dielectric oxide portion274′ o the second annular dielectric spacers274and the second joint-level doped semiconductor portion273. The joint-level insulating layer176can include the same material as the first insulating layers132in the first alternating stack (132,142). The joint-level insulating layer176can be formed over the second joint-level doped semiconductor portions273and around the second joint-level doped semiconductor portion273. The thickness of the joint-level insulating layer176can be in a range from 20 nm to 100 nm, although lesser and greater thicknesses can also be employed. A chemical mechanical planarization (CMP) process can be performed to remove protruding portions of the joint-level insulating layer176and a horizontal top portion of each second dielectric oxide portion274′ or the second annular dielectric spacers274from above a horizontal plane including top surfaces of the second joint-level doped semiconductor portions273. Each remaining annular portion of the second dielectric oxide portions274′ (if present) constitutes an annular dielectric spacer, which is herein referred to as a second annular dielectric spacer274. Thus, each second annular dielectric spacer274is formed from an oxidized surface portion of the second joint-level doped semiconductor portion273as provided at the processing steps ofFIG. 18E. In one embodiment, the chemical mechanical planarization process can further remove portions of the second annular dielectric spacers274and surface portions of the second joint-level doped semiconductor portions273from above a horizontal plane including the top surface of the joint-level insulating layer176. In this case, the top surfaces of the joint-level insulating layer176, the second annular dielectric spacers274, and the second joint-level doped semiconductor portions273can be within a same horizontal plane.

Referring toFIG. 18G, a third joint-level doped semiconductor layer is deposited over the joint-level insulating layer176. The third joint-level doped semiconductor layer includes a third doped semiconductor material, which may have the same composition as, or have a different composition from, the material of the first joint-level doped semiconductor layer173L and/or the material of the second joint-level doped semiconductor layer. The thickness of the third joint-level doped semiconductor layer may be in a range from 20 nm to 100 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer347can be applied over the third joint-level doped semiconductor layer and lithographically patterned to cover the second annular dielectric spacers274and the second joint-level doped semiconductor portions273. The lithographic mask employed to pattern the photoresist layer at the processing steps ofFIG. 18Bcan be employed again at this step. Physically exposed portions of the third joint-level doped semiconductor layer can be removed by an anisotropic etch. Each remaining portion of the third joint-level doped semiconductor layer constitutes a third joint-level doped semiconductor portion373. Each third joint-level doped semiconductor portion373covers an underlying second joint-level doped semiconductor portion273. The photoresist layer can be subsequently removed, for example, by ashing.

An oxidation process is performed to convert physically exposed surface portions of each third joint-level doped semiconductor portion373into a dielectric oxide material. Each oxidized surface portion of the third joint-level doped semiconductor portions373constitutes a dielectric oxide portion, which is herein referred to as a third dielectric oxide portion374′, which includes a dielectric oxide of the semiconductor material of the third joint-level doped semiconductor portions373, and may include silicon oxide. Thermal oxidation or plasma oxidation may be employed to form the third dielectric oxide portions374′. The thickness of each third dielectric oxide portion374′, as measured between an inner sidewall and an outer sidewall, can be in a range from 10 nm to 50 nm, although lesser and greater thicknesses can also be employed. In an alternative embodiment shown in the dashed line inset inFIG. 18G, only the sidewalls of the third joint-level doped semiconductor portions373are oxidized to form a third annular dielectric spacer374. In this alternative embodiment, a mask347, such as the patterned photoresist layer used to etch portions373, is left on the top surface of the etched portions373while leaving the sidewalls of the portions373exposed. The exposed sidewalls of the portions373are then oxidized to form the third annular dielectric spacers374followed by removing the mask347.

Referring toFIG. 18H, a second joint-level spacer material layer177can be deposited over the third dielectric oxide portion374′ or the third annular dielectric spacers374and the third joint-level doped semiconductor portion373. The second joint-level spacer material layer177can include the same material as the first sacrificial material layers142in the first alternating stack (132,142). The second joint-level spacer material layer177can be formed over the third joint-level doped semiconductor portions373and around the third annular dielectric spacers374or portions374′. The thickness of the second joint-level spacer material layer177can be in a range from 20 nm to 100 nm, although lesser and greater thicknesses can also be employed.

A chemical mechanical planarization (CMP) process can be performed to remove protruding portions of the second joint-level spacer material layer177and a horizontal top portion of each third dielectric oxide portion374′ or the third annular dielectric spacers374from above a horizontal plane including top surfaces of the third joint-level doped semiconductor portions373. Each remaining annular portion of the third dielectric oxide portions374′ (if present) constitutes an annular dielectric spacer, which is herein referred to as a third annular dielectric spacer374. Thus, each third annular dielectric spacer374is formed from an oxidized surface portion of the third joint-level doped semiconductor portion373as provided at the processing steps ofFIG. 18G. In one embodiment, the chemical mechanical planarization process can further remove portions of the third annular dielectric spacers374and surface portions of the third joint-level doped semiconductor portions373from above a horizontal plane including the top surface of the second joint-level spacer material layer177. In this case, the top surfaces of the second joint-level spacer material layer177, the third annular dielectric spacers374, and the third joint-level doped semiconductor portions373can be within a same horizontal plane.

Each of the first joint-level spacer material layer175, the joint-level insulating layer176, and the second joint-level spacer material layer177is laterally spaced from the first, second, and third joint-level doped semiconductor portions (173,273,373) by the first, second, and third annular dielectric spacers (174,274,374). Each of the first, second, and third joint-level doped semiconductor portions (173,273,373) is formed by deposition and patterning of a respective doped semiconductor material. Each of the first, second, and third joint-level annular dielectric spacers (174,274,374) is formed by oxidation of a surface portion of a respective one of the first, second, and third joint-level doped semiconductor portions (173,273,373) and an anisotropic etch of the respective one of the first, second, and third joint-level doped semiconductor portions (173,273,373).

Then, the processing steps ofFIGS. 19A-19Fcan be performed in lieu of the processing steps ofFIGS. 11A-11F.

FIG. 19Aillustrate a region of the second exemplary structure at the processing steps ofFIGS. 10A and 10B, i.e., after formation of the second-tier memory openings249and the second-tier support openings219.

Referring toFIG. 19B, a stack of layers including a second blocking dielectric layer252, a second charge storage layer254, a second tunneling dielectric layer256, and an optional second outer semiconductor channel layer621can be sequentially deposited in the second-tier memory openings249employing the processing steps ofFIG. 11B.

Referring toFIG. 19C, the optional second outer semiconductor channel layer621, the second tunneling dielectric layer256, the second charge storage layer254, the second blocking dielectric layer252are sequentially anisotropically etched employing at least one anisotropic etch process, which can be the same as the anisotropic etch process ofFIG. 11C.

Referring toFIG. 19D, a second inner semiconductor channel layer622can be deposited directly on the semiconductor surface of the second joint-level doped semiconductor portion273, and directly on the second outer semiconductor channel layer621. In case the second memory cavity249′ in each second-tier memory opening is not completely filled by the second inner semiconductor channel layer622, a second dielectric core layer262L can be deposited in the second memory cavity249′ to fill any remaining portion of the second memory cavity249′ within each second-tier memory opening. The processing steps ofFIG. 11Dmay be employed.

Referring toFIG. 19E, the horizontal portion of the second dielectric core layer262L can be removed, for example, by a recess etch from above the top surface of the second-tier insulating cap layer70, for example, employing the processing steps ofFIG. 11E. Each adjoining pair of a second outer semiconductor channel layer621and a second inner semiconductor channel layer622can collectively form a second vertical semiconductor channel62through which electrical current can flow when a vertical NAND device including the second vertical semiconductor channel62is turned on.

Referring toFIG. 19F, the top surface of each second dielectric core262can be recessed below the top surface of the insulating cap layer70, for example, by a recess etch to a depth that is located between the top surface of the insulating cap layer70and the bottom surface of the insulating cap layer70. Drain regions63can be formed by depositing a doped semiconductor material within each recessed region above the second dielectric cores262employing the processing steps ofFIG. 11F.

Each combination of a first memory film150and a first vertical semiconductor channel61(which is a lower portion of the vertical semiconductor channel) within a first-tier memory opening149constitutes a first-tier memory stack structure (150,61). Each combination of a second memory film250and a second vertical semiconductor channel62(which is an upper portion of the vertical semiconductor channel) within a second-tier memory opening249constitutes a second-tier memory stack structure (250,62). Each contiguous combination of a first vertical semiconductor channel61, a set of at least one joint-level doped semiconductor portions (173,273,373) (which can include a first joint-level doped semiconductor portion173, a second joint-level doped semiconductor portion273, and a third joint-level doped semiconductor portion373), a second vertical semiconductor channel62constitutes a vertical semiconductor channel (61,173,273,373,62). Each combination of an epitaxial channel portion11(if present), a first-tier memory stack structure (150,61), a first dielectric core162, a joint-level memory opening fill structure67, a second-tier memory stack structure (250,62), a second dielectric core262, and a drain region63within an inter-tier memory opening is herein referred to as a memory opening fill structure (57,67,77), or an inter-tier memory opening fill structure. Each combination of an epitaxial channel portion11(if present), a first-tier memory stack structure (150,61), a first dielectric core162, a joint-level support opening fill structure27, a second-tier memory stack structure (250,62), a second dielectric core262, and a drain region63within an inter-tier support opening is herein referred to as a support opening fill structure (17,27,37), or an inter-tier support opening fill structure.

A third exemplary structure can be derived from the first exemplary structure by modifying the joint-level fill structures (67,27) to include only one joint-level doped semiconductor portion173. For example, the first exemplary structure ofFIGS. 5A and 5Bcan be employed to form the third exemplary structure.

Referring toFIG. 20A, a joint-level doped semiconductor layer173L is deposited over the first tier structure, which includes the first alternating stack (131,142), the first-tier cap dielectric layer172, the first memory opening fill structures57, and the first support opening fill structures17. The joint-level doped semiconductor layer173L of the third exemplary structure can include the same material as the first joint-level doped semiconductor layer173L of the first exemplary structure. Thus, the joint-level doped semiconductor layer173L can include a doped semiconductor material. The thickness of the joint-level doped semiconductor layer173L of the third exemplary structure can be greater than the thickness of the first joint-level doped semiconductor layer173L of the first exemplary structure. For example, the thickness of the joint-level doped semiconductor layer173L can be in a range from 60 nm to 100 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG. 20B, a photoresist layer147can be applied over the joint-level doped semiconductor layer173L and lithographically patterned to cover each of the first memory opening fill structures57and each of the first-tier support opening fill structures17. Physically exposed portions of the joint-level doped semiconductor layer173L can be removed by an anisotropic etch. Each remaining portion of the joint-level doped semiconductor layer173L constitutes a joint-level doped semiconductor portion173. Each joint-level doped semiconductor portion173covers and protects the underlying first vertical semiconductor channel61from oxidation during a subsequent oxidation process. In one embodiment, the bottom surface of each joint-level doped semiconductor portion173can contact an entire top surface of an underlying first memory opening fill structure57. The photoresist layer can be subsequently removed, for example, by ashing.

Referring toFIG. 20C, in one embodiment, an oxidation process is performed to convert physically exposed surface portions of each joint-level doped semiconductor portion173into a dielectric oxide material. Each oxidized surface portion of the joint-level doped semiconductor portions173constitutes a dielectric oxide portion174′, which includes a dielectric oxide of the semiconductor material of the joint-level doped semiconductor portions173, and may include silicon oxide. Thermal oxidation or plasma oxidation may be employed to form the dielectric oxide portions174′. The thickness of each dielectric oxide portion174′, as measured between an inner sidewall and an outer sidewall, can be in a range from 10 nm to 50 nm, although lesser and greater thicknesses can also be employed. In an alternative embodiment shown in the dashed line inset inFIG. 20C, only the sidewalls of the joint-level doped semiconductor portions173are oxidized to form a first annular dielectric spacer174. In this alternative embodiment, a mask147, such as the patterned photoresist layer used to etch portions173, is left on the top surface of the etched portions173while leaving the sidewalls of the portions173exposed. The exposed sidewalls of the portions173are then oxidized to form the annular dielectric spacers174followed by removing the mask147.

Referring toFIG. 20D, a joint-level spacer material layer175can be deposited over the dielectric oxide portion174′ or the annular dielectric spacer174and the joint-level doped semiconductor portion173. The joint-level spacer material layer175can include the same material as the first spacer material layers in the first alternating stack (132,142). If the first spacer material layers are provided as first sacrificial material layers142, the joint-level spacer material layer175can include the same sacrificial material as the first sacrificial material layers142. If the first spacer material layers are provided as first electrically conductive layers, the joint-level spacer material layer175can include the same conductive material as the first electrically conductive layers (which are formed as the first spacer material layers).

The joint-level spacer material layer175can be formed over the first alternating stack (132,142) and around the joint-level doped semiconductor portion173and at least one of spacer174or portion174′. The thickness of the joint-level spacer material layer175can be in a range from 60 nm to 300 nm, although lesser and greater thicknesses can also be employed. A chemical mechanical planarization (CMP) process can be performed to remove protruding portions of the joint-level spacer material layer175and a horizontal top portion of each dielectric oxide portion174′ from above a horizontal plane including top surfaces of the joint-level doped semiconductor portions173. Each remaining annular portion of the dielectric oxide portions174′ (if present) constitutes an annular dielectric spacer174. Thus, each annular dielectric spacer174is formed from an oxidized surface portion of the joint-level doped semiconductor portion173as provided at the processing steps ofFIG. 20BorFIG. 20C. In one embodiment, the chemical mechanical planarization process can further remove portions of the annular dielectric spacers174and surface portions of the joint-level doped semiconductor portions173from above a horizontal plane including the top surface of the joint-level spacer material layer175. In this case, the top surfaces of the joint-level spacer material layer175, the annular dielectric spacers174, and the joint-level doped semiconductor portions173can be within a same horizontal plane.

The joint-level spacer material layer175is laterally spaced from the joint-level doped semiconductor portion173by the annular dielectric spacer174. The joint-level doped semiconductor portion173is formed by deposition and patterning of a doped semiconductor material. The joint-level annular dielectric spacers174is formed by oxidation of a surface portion of a joint-level doped semiconductor portion173and an anisotropic etch of the joint-level doped semiconductor portion173. Each contiguous combination of a joint-level doped semiconductor portion173and a joint-level annular dielectric spacer overlying a first memory opening fill structure57constitutes a joint-level memory opening fill structure67. Each contiguous combination of a joint-level doped semiconductor portion173and a joint-level annular dielectric spacer overlying a first support opening fill structure17constitutes a joint-level support opening fill structure27.

Then, the processing steps ofFIGS. 21A-21Fcan be performed in lieu of the processing steps ofFIGS. 11A-11F.

FIG. 21Aillustrate a region of the second exemplary structure at the processing steps ofFIGS. 10A and 10B, i.e., after formation of the second-tier memory openings249and the second-tier support openings219.

Referring toFIG. 21B, a stack of layers including a second blocking dielectric layer252, a second charge storage layer254, a second tunneling dielectric layer256, and an optional second outer semiconductor channel layer621can be sequentially deposited in the second-tier memory openings249employing the processing steps ofFIG. 11B.

Referring toFIG. 21C, the optional second outer semiconductor channel layer621, the second tunneling dielectric layer256, the second charge storage layer254, the second blocking dielectric layer252are sequentially anisotropically etched employing at least one anisotropic etch process, which can be the same as the anisotropic etch process ofFIG. 11C.

Referring toFIG. 21D, a second inner semiconductor channel layer622can be deposited directly on the semiconductor surface of the second joint-level doped semiconductor portion179, and directly on the second outer semiconductor channel layer621. In case the second memory cavity249′ in each second-tier memory opening is not completely filled by the second inner semiconductor channel layer622, a second dielectric core layer262L can be deposited in the second memory cavity249′ to fill any remaining portion of the second memory cavity249′ within each second-tier memory opening. The processing steps ofFIG. 11Dmay be employed.

Referring toFIG. 21E, the horizontal portion of the second dielectric core layer262L can be removed, for example, by a recess etch from above the top surface of the second-tier insulating cap layer70, for example, employing the processing steps ofFIG. 11E. Each adjoining pair of a second outer semiconductor channel layer621and a second inner semiconductor channel layer622can collectively form a second vertical semiconductor channel62through which electrical current can flow when a vertical NAND device including the second vertical semiconductor channel62is turned on.

Referring toFIG. 21F, the top surface of each second dielectric core262can be recessed below the top surface of the insulating cap layer70, for example, by a recess etch to a depth that is located between the top surface of the insulating cap layer70and the bottom surface of the insulating cap layer70. Drain regions63can be formed by depositing a doped semiconductor material within each recessed region above the second dielectric cores262employing the processing steps ofFIG. 11F.

Each combination of a first memory film150and a first vertical semiconductor channel61(which is a lower portion of the vertical semiconductor channel) within a first-tier memory opening149constitutes a first-tier memory stack structure (150,61). Each combination of a second memory film250and a second vertical semiconductor channel62(which is an upper portion of the vertical semiconductor channel) within a second-tier memory opening249constitutes a second-tier memory stack structure (250,62). Each contiguous combination of a first vertical semiconductor channel61, a set of at least one joint-level doped semiconductor portions173(which can include a joint-level doped semiconductor portion173only in this embodiment), a second vertical semiconductor channel62constitutes a vertical semiconductor channel (61,173,62). In the third embodiment, the at least one joint-level doped semiconductor portion consists of a single joint-level doped semiconductor portion173contacting a top surface of the first memory film150and a bottom surface of the second memory film250. The at least one annular dielectric spacer consists of a single annular dielectric spacer174that contacts an entirety of an outer sidewall of the single joint-level doped semiconductor portion173.

Each combination of an epitaxial channel portion11(if present), a first-tier memory stack structure (150,61), a first dielectric core162, a joint-level memory opening fill structure67, a second-tier memory stack structure (250,62), a second dielectric core262, and a drain region63within an inter-tier memory opening is herein referred to as a memory opening fill structure (57,67,77), or an inter-tier memory opening fill structure. Each combination of an epitaxial channel portion11(if present), a first-tier memory stack structure (150,61), a first dielectric core162, a joint-level support opening fill structure27, a second-tier memory stack structure (250,62), a second dielectric core262, and a drain region63within an inter-tier support opening is herein referred to as a support opening fill structure (17,27,37), or an inter-tier support opening fill structure.

Referring toFIG. 22A, an alternate embodiment of the third exemplary structure after formation of the second memory opening fill structures77, which is derived from the third exemplary structure by reducing the thicknesses of each joint-level doped semiconductor portions173, each single annular dielectric spacer174, and the joint-level spacer material layer175, for example, to a range from 20 nm to 150 nm, although lesser and greater thicknesses can also be employed.

Referring toFIG. 22B, the alternate embodiment of the third exemplary structure is shown after formation of the electrically conductive layers (146,246,346).

Each of the first, second, and third exemplary structures can comprise a three-dimensional memory device. The three-dimensional memory device can comprise: a first alternating stack (132,146) of first insulating layers132and first electrically conductive layers146located over a substrate (9,10); a first memory stack structure (150,61) extending through the first alternating stack (132,146) and comprising a first memory film150and a first vertical semiconductor channel61that is laterally surrounded by the first memory film150; a joint-level electrically conductive layer376(which may be a bottommost one in case multiple joint-level electrically conductive layers376are present) overlying the first alternating stack (132,146); at least one joint-level doped semiconductor portion {(173,179), (173,273,373), or173} contacting a top surface of the first vertical semiconductor channel61and located within, and electrically isolated from, the joint-level electrically conductive layer346; a second alternating stack (232,246) of second insulating layers232and second electrically conductive layers246located over the joint-level electrically conductive layer376; a second memory stack structure (250,62) extending through the second alternating stack (232,246) and comprising a second memory film250and a second vertical semiconductor channel62that is laterally surrounded by the second memory film250and vertically extends into the at least one joint-level doped semiconductor portion {(173,179), (173,273,373), or173}. The first memory film150and the second memory film250are vertically spaced from each other by the at least one joint-level doped semiconductor portion {(173,179), (173,273,373), or173}. While the present disclosure is described employing an embodiment in which the first-tier insulating cap layer172is provided above the initial first alternating stack (132,142), embodiments are expressly contemplated herein in which a first-tier insulating cap layer172is not provided and a topmost layer of a first tier structure as initially formed is a topmost first sacrificial material layer142. In this case, a joint-level insulating layer can be formed directly on the topmost first sacrificial material layer prior to forming the joint-level electrically conductive layer376(which may be a bottommost one in case multiple joint-level electrically conductive layers376are present). The joint-level electrically conductive layer376overlies the first alternating stack (132,146) with the joint-level insulating layer as an intermediate layer between the first alternating stack (132,146) and the joint-level electrically conductive layer376.

In one embodiment, the three-dimensional memory device further comprises at least one annular dielectric spacer {(174,178), (174,274,374), or174} laterally surrounding the at least one joint-level doped semiconductor portion {(173,179), (173,273,373), or173}, and laterally surrounded by the joint-level electrically conductive layer346. In some embodiments, the three-dimensional memory device can further comprise: a joint-level insulating layer (176or275) overlying the joint-level electrically conductive layer346; an additional joint-level electrically conductive layer346overlying the joint-level insulating layer (176or275) and underlying the second alternating stack (232,246) as illustrated in the first and second embodiments. The joint-level insulating layer (176or275) and the additional joint-level electrically conductive layer346are laterally spaced from the at the one joint-level doped semiconductor portion {(173,179), (173,273,373), or173} by the at least one annular dielectric spacer {(174,178), (174,274,374), or174}.

In each of the first, second, and third exemplary structures, a bottommost surface of the at least one joint-level doped semiconductor portion {(173,179), (173,273,373), or173} contacts a top surface of the first vertical semiconductor channel61and a top surface of the first memory film150. The first vertical semiconductor channel61is shown inFIGS. 6B-6F, 11A-11F, 14A-14B and 18A-22B. A topmost surface of the at least one joint-level doped semiconductor portion {(173,179), (173,273,373), or173} contacts a bottom surface of the second memory film250; a recessed surface of the at least one joint-level doped semiconductor portion {(173,179), (173,273,373), or173} contacts a bottommost surface of the second vertical semiconductor channel62; and the at least one annular dielectric spacer {(174,178), (174,274,374), or174} has a greater lateral extent (i.e., a maximum lateral dimension) than the first memory film and the second memory film.

Referring toFIGS. 23A and 23B, a fourth exemplary structure according to a fourth embodiment of the present disclosure can be derived from the first exemplary structure ofFIGS. 2A and 2Bby forming a joint-level sacrificial planarization layer480over the top surface of the first-tier insulating cap layer172. The joint-level sacrificial planarization layer480includes a sacrificial material that can be removed selective to the materials of the first-tier insulating cap layer172and the first retro-stepped dielectric material portion165. For example, the first-tier insulating cap layer172and the first retro-stepped dielectric material portion165can comprise silicon oxide, and the joint-level sacrificial planarization layer480can include a sacrificial material such as amorphous silicon, polysilicon, a silicon-germanium alloy, a non-organic polymer (such as a silicon-based polymer), or silicon nitride. In one embodiment, the joint-level sacrificial planarization layer480can include polysilicon. The thickness of the joint-level sacrificial planarization layer480can be in a range from 30 nm to 600 nm, although lesser and greater thicknesses can also be employed. The joint-level sacrificial planarization layer480can be deposited by a conformal or non-conformal deposition method.

Referring toFIGS. 24A and 24B, the processing steps ofFIGS. 3A and 3Bcan be performed to form first-tier memory openings149and first-tier support openings119with appropriate modification to the anisotropic etch process. Specifically, the etch process employed at the processing steps ofFIGS. 3A and 3Bcan be employed with a modification that inserts an additional etch step for etching the material of the joint-level sacrificial planarization layer480before etching the materials of the first-tier cap insulating layer172and the first alternating stack (132,142). The first-tier memory openings149are formed through the joint-level sacrificial planarization layer480and the first tier structure (132,142,172,165) in the memory array region100, and the first-tier support openings119are formed through the joint-level sacrificial planarization layer480and the first tier structure (132,142,172,165) in the contact region200.

FIGS. 25A-25Jillustrate sequential vertical cross-sectional views of a first-tier memory opening149and its vicinity within the fourth exemplary structure up to the processing step of formation of a joint-level spacer material layer484.

Referring toFIG. 25A, a first-tier memory opening149in the fourth exemplary device structure ofFIGS. 24A and 24Bis illustrated. The first-tier memory opening149extends through the joint-level sacrificial planarization layer480, the first-tier insulating cap layer172, the first alternating stack (132,142), the gate dielectric layer12, and optionally into an upper portion of the semiconductor material layer10. At this processing step, each first-tier support opening119can extend through the joint-level sacrificial planarization layer480, the first retro-stepped dielectric material portion165, a subset of layers in the first alternating stack (132,142), the gate dielectric layer12, and optionally through the upper portion of the semiconductor material layer10. The recess depth of the bottom surface of each first-tier memory opening149with respect to the top surface of the semiconductor material layer10can be in a range from 0 nm to 30 nm, although greater recess depths can also be employed. Optionally, the first sacrificial material layers142can be laterally recessed partially to form lateral recesses (not shown), for example, by an isotropic etch.

Referring toFIG. 25B, an optional epitaxial channel portion (e.g., an epitaxial pedestal)11can be formed at the bottom portion of each first-tier memory opening149and each first-tier support openings119, for example, by selective epitaxy. The processing steps ofFIG. 4Bmay be employed. The epitaxial channel portion11is optional structure, and may be omitted.

Referring toFIG. 25C, a stack of layers including a first blocking dielectric layer152, a first charge storage layer154, a first tunneling dielectric layer156, and an optional first outer semiconductor channel layer611can be sequentially deposited in the first-tier memory openings149. Each of the first blocking dielectric layer152, the first charge storage layer154, the first tunneling dielectric layer156, and the optional first outer semiconductor channel layer611may be the same as in the first embodiment.

Referring toFIG. 25D, the optional first outer semiconductor channel layer611, the first tunneling dielectric layer156, the first charge storage layer154, the first blocking dielectric layer152are sequentially anisotropically etched employing at least one anisotropic etch process. The processing steps ofFIG. 4Dmay be employed. The portions of the first outer semiconductor channel layer611, the first tunneling dielectric layer156, the first charge storage layer154, and the first blocking dielectric layer152located above the top surface of the first-tier insulating cap layer172can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the first outer semiconductor channel layer611, the first tunneling dielectric layer156, the first charge storage layer154, and the first blocking dielectric layer152at a bottom of each first memory cavity149′ can be removed to form openings in remaining portions thereof.

Referring toFIG. 25E, a first inner semiconductor channel layer612can be deposited directly on the semiconductor surface of the epitaxial channel portion11or the semiconductor substrate layer10if the epitaxial channel portion11is omitted, and directly on the first outer semiconductor channel layer611. The processing steps ofFIG. 4Emay be employed. The materials of the first outer semiconductor channel layer611and the first inner semiconductor channel layer612are collectively referred to as a first semiconductor channel material. In other words, the first semiconductor channel material is a set of all semiconductor material in the first outer semiconductor channel layer611and the first inner semiconductor channel layer612.

Referring toFIG. 25F, in case the first memory cavity149′ in each first-tier memory opening is not completely filled by the first inner semiconductor channel layer612, a first dielectric core layer162L can be deposited in the first memory cavity149′ to fill any remaining portion of the first memory cavity149′ within each first-tier memory opening. The first dielectric core layer162L includes a dielectric material such as silicon oxide or organosilicate glass. The first dielectric core layer162L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG. 25G, the horizontal portion of the first dielectric core layer162L can be removed, for example, by a recess etch from above the top surface of the joint-level sacrificial planarization layer480. Each remaining portion of the first dielectric core layer162L constitutes a dielectric core162. Further, the horizontal portion of the first inner semiconductor channel layer612located above the top surface of the first-tier insulating cap layer172can be removed by a planarization process, which can employ a recess etch or chemical mechanical planarization (CMP). Each remaining portion of the first inner semiconductor channel layer612can be located entirety within a first-tier memory opening149or entirely within a first-tier support opening119.

Each adjoining pair of a first outer semiconductor channel layer611and a first inner semiconductor channel layer612can collectively form a first vertical semiconductor channel61through which electrical current can flow when a vertical NAND device including the first vertical semiconductor channel61is turned on. A first tunneling dielectric layer156is surrounded by a first charge storage layer154, and laterally surrounds a portion of the first vertical semiconductor channel61. Each adjoining set of a first blocking dielectric layer152, a first charge storage layer154, and a first tunneling dielectric layer156collectively constitute a first memory film150, which can store electrical charges with a macroscopic retention time. In some embodiments, a first blocking dielectric layer152may not be present in the first memory film150at this step, and a first blocking dielectric layer may be subsequently formed after formation of backside recesses. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.

Each contiguous set of material portions that fills a first-tier memory opening149constitutes a first memory opening fill structure57, which can include an epitaxial channel portion11, a first memory film150, a first vertical semiconductor channel61, and a first dielectric core162. Thus, each first-tier memory opening149can be filled with an instance of a first memory opening fill structure57. Each first-tier support opening119can be filled with a first-tier support opening fill structure17, which can include an epitaxial channel portion11, a first memory film150, a first vertical semiconductor channel61, and a first dielectric core162.

Referring toFIG. 25H, a photoresist layer47can be applied over the joint-level sacrificial planarization layer480, the first-tier memory opening fill structures57that are formed in the first-tier memory openings149, and first-tier support opening fill structures that are formed in the first-tier support openings119. The photoresist layer47can be patterned to form to form isolated portions of the photoresist layer47that covers each of the first-tier memory opening fill structures57and first-tier support opening fill structures, while physically exposing the top surface of the joint-level sacrificial planarization layer480. In one embodiment, each portion of the joint-level sacrificial planarization layer480that is laterally spaced from the first-tier memory opening fill structures57and first-tier support opening fill structures by more than the thickness of the joint-level sacrificial planarization layer480can be physically exposed, i.e., not covered by the patterned portions of the photoresist layer47.

An etch process can be performed to remove the joint-level sacrificial planarization layer480selective to the materials of the first-tier cap insulating layer172, the first retro-stepped dielectric material portion165, and the outermost layer of the first memory film150(i.e., the first blocking dielectric layer152). For example, if the joint-level sacrificial planarization layer480includes polysilicon, a wet etch process employing a KOH solution can be employed to etch the joint-level sacrificial planarization layer480. The photoresist layer47can be subsequently removed, for example, by ashing.

Referring toFIG. 25I, a dielectric liner layer482can be deposited. The dielectric liner482includes a material that is different form the material of the first sacrificial material layer142. The material of the dielectric liner layer482may be the same as the material of the first insulating layers132. For example, the dielectric liner layer482can include silicon oxide. The dielectric liner layer482can be formed by conformally depositing a dielectric liner material on a top surface of each first memory stack structure (150,61), on an upper portion of a sidewall of each first memory stack structure (150,61), and over a topmost layer in the first alternating stack (132,142). In other words, the dielectric liner layer482can be deposited by a conformal deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the dielectric liner layer482can be in a range from 6 nm to 100 nm, such as from 12 nm to 50 nm, although lesser and greater thicknesses can also be employed. The thickness of the dielectric liner layer482can be in a range from 2% to 40% of the thickness of the joint-level sacrificial planarization layer480, although lesser and greater percentages can also be employed.

Referring toFIG. 25J, a spacer material can be deposited over the dielectric liner material of the dielectric liner layer482. The spacer material can be the same material as the material of the first spacer material layers in the first alternating stack (132,142). If the first spacer material layers are the first sacrificial material layers142, the deposited spacer material can be the same as the sacrificial material of the first sacrificial material layers142. For example, if the first sacrificial material layers142include silicon nitride, the deposited spacer material can include silicon nitride. If the first spacer material layers are first electrically conductive layers, the deposited spacer material can include a conductive material such as a metal and/or a conductive metallic alloy. While the present disclosure is described employing an embodiment in which the first spacer material layers are first sacrificial material layers142, embodiments are expressly contemplated herein in which the first spacer material layers are first electrically conductive layers.

Portions of the spacer material and the dielectric liner material can be removed from above a horizontal plane including the top surface of the first memory stack structures (150,61) by a planarization process such as chemical mechanical planarization. The remaining portion of the deposited and planarized spacer material constitutes a joint-level spacer material layer484. Horizontal portions of the dielectric liner layer482overlying the first memory-opening fill structures57can be removed during the planarization process. The dielectric liner layer482includes the remaining portion of the dielectric liner material after the planarization process. The remaining portion of the spacer material constitutes a joint-level spacer material layer484.

Thus, a combination of the dielectric liner layer482and the joint-level spacer material layer484is formed over the first memory stack structures (150,61) and the first alternating stack (132,142). The dielectric liner layer482includes a horizontal portion that overlies the first alternating stack (132,142) and underlies the joint-level spacer material layer484. The dielectric liner layer482further includes cylindrical vertical portions, each of which laterally surrounds an upper portion of a respective first memory stack structure (150,61). As used herein, a “cylindrical” element refers to an element having an inner sidewall that is parallel to an outer sidewall and having a uniform thickness between the inner sidewall and the outer sidewall. The joint-level spacer material layer484is laterally spaced from the first memory stack structures (150,61) by the cylindrical vertical portion of the dielectric liner layer482.

Referring toFIGS. 26A and 26B, the fourth exemplary structure is illustrated after formation of the first memory opening fill structures57in the first-tier memory openings149and formation of the first-tier support opening fill structures17in the first-tier support openings119. Each layer (such as the first blocking dielectric layer152, the first charge storage layer154, the first tunneling dielectric layer156, the first outer semiconductor channel layer611, and the first inner semiconductor channel layer612) within each first-tier support opening fill structure17can have the same composition and the same thickness as the corresponding layer within a first memory opening fill structure57. The first memory opening fill structures57can be arranged as a plurality of two-dimensional periodic arrays in the memory array region100. Likewise, the first-tier support opening fill structures17can be arranged as a plurality of two-dimensional periodic arrays in the contact region200.

Referring toFIGS. 27A and 27B, the processing steps ofFIGS. 8A, 8B, 9A, and 9Bcan be performed to form a second alternating stack (232,242) of second insulating layers232and second sacrificial material layers242, second stepped surfaces, and a second retro-stepped dielectric material portion265.

Referring toFIGS. 28A and 28B, the processing steps ofFIGS. 10A and 10Bcan be performed to form second memory openings249over the first memory-opening fill structures57and to form second support openings219over the first support opening fill structure17.

Subsequently, the processing steps ofFIGS. 29A-29Fcan be performed to form second memory opening fill structures in the second-tier memory openings and to form second support opening fill structures in the second-tier support openings.

FIG. 29Aillustrate a region of the second exemplary structure at the processing steps ofFIGS. 28A and 28B, i.e., after formation of the second-tier memory openings249and the second-tier support openings219.

Referring toFIG. 29B, a stack of layers including a second blocking dielectric layer252, a second charge storage layer254, a second tunneling dielectric layer256, and an optional second outer semiconductor channel layer621can be sequentially deposited in the second-tier memory openings249employing the processing steps ofFIG. 11B. The second memory film250is formed directly on a top surface of the first memory film150.

Referring toFIG. 29C, the optional second outer semiconductor channel layer621, the second tunneling dielectric layer256, the second charge storage layer254, the second blocking dielectric layer252are sequentially anisotropically etched employing at least one anisotropic etch process, which can be the same as the anisotropic etch process ofFIG. 11C. After formed an opening in the horizontal portion of the second memory film250at the bottom of each second-tier memory opening249, and the first vertical semiconductor channel61can be optionally vertically recessed.

Referring toFIG. 29D, a second inner semiconductor channel layer622can be deposited directly on the semiconductor surface of the first vertical semiconductor channel61, and directly on the second outer semiconductor channel layer621. In case the second memory cavity249′ in each second-tier memory opening is not completely filled by the second inner semiconductor channel layer622, a second dielectric core layer262L can be deposited in the second memory cavity249′ to fill any remaining portion of the second memory cavity249′ within each second-tier memory opening. The processing steps ofFIG. 11Dmay be employed.

Referring toFIG. 29E, the horizontal portion of the second dielectric core layer262L can be removed, for example, by a recess etch from above the top surface of the second-tier insulating cap layer70, for example, employing the processing steps ofFIG. 11E. Each adjoining pair of a second outer semiconductor channel layer621and a second inner semiconductor channel layer622can collectively form a second vertical semiconductor channel62through which electrical current can flow when a vertical NAND device including the second vertical semiconductor channel62is turned on. The second vertical semiconductor channel62can be formed directly on a vertically recessed surface of the first vertical semiconductor channel61.

Referring toFIG. 29F, the top surface of each second dielectric core262can be recessed below the top surface of the insulating cap layer70, for example, by a recess etch to a depth that is located between the top surface of the insulating cap layer70and the bottom surface of the insulating cap layer70. Drain regions63can be formed by depositing a doped semiconductor material within each recessed region above the second dielectric cores262employing the processing steps ofFIG. 11F.

Each combination of a first memory film150and a first vertical semiconductor channel61(which is a lower portion of the vertical semiconductor channel) within a first-tier memory opening149constitutes a first-tier memory stack structure (150,61). Each combination of a second memory film250and a second vertical semiconductor channel62(which is an upper portion of the vertical semiconductor channel) within a second-tier memory opening249constitutes a second-tier memory stack structure (250,62). Each contiguous combination of a first vertical semiconductor channel61and a second vertical semiconductor channel62constitutes a vertical semiconductor channel (61,62). Each combination of an epitaxial channel portion11(if present), a first-tier memory stack structure (150,61), a first dielectric core162, a second-tier memory stack structure (250,62), a second dielectric core262, and a drain region63within an inter-tier memory opening is herein referred to as a memory opening fill structure (57,77), or an inter-tier memory opening fill structure. Each combination of an epitaxial channel portion11(if present), a first-tier memory stack structure (150,61), a first dielectric core162, a second-tier memory stack structure (250,62), a second dielectric core262, and a drain region63within an inter-tier support opening is herein referred to as a support opening fill structure (17,37), or an inter-tier support opening fill structure.

Subsequently, the processing steps ofFIGS. 13A, 13B, 14A, 14B, 15A, and 15Bcan be performed. The joint-level spacer material layer484is removed during removal of the first and second sacrificial material layers (142,242). Removal of the joint-level spacer material layer484and the first and second sacrificial material layers (142,242) is selective to the dielectric liner layer482. Thus, the backside blocking dielectric layer44can be deposited directly on the dielectric liner layer482. After formation of the backside blocking dielectric layer44, a joint-level electrically conducive layer346can be formed in the remaining volume of the backside cavity43that is formed by removal of the joint-level spacer material layer484.FIG. 29Gillustrates the fourth exemplary structure at the processing steps ofFIG. 14B. Subsequently, the processing steps ofFIGS. 17A, 17B, 18A, and18B can be performed.

The fourth exemplary structure comprises a three-dimensional memory device. The three-dimensional memory device comprises: a first alternating stack (132,146) of first insulating layers132and first electrically conductive layers146located over a substrate (91,10); a joint-level electrically conductive layer346overlying the first alternating stack (132,146); a first memory stack structure (150,61) extending through the first alternating stack (132,146) and the joint-level electrically conductive layer346and comprising a first memory film150and a first vertical semiconductor channel61that is laterally surrounded by the first memory film150; a dielectric liner layer482including a horizontal portion that overlies the first alternating stack (132,146) and underlies the joint-level electrically conductive layer346, and a cylindrical vertical portion that laterally surrounds an upper portion of the first memory stack structure (150,61), wherein the joint-level electrically conductive layer346is laterally spaced from the first memory stack structure (150,61) by the cylindrical vertical portion of the dielectric liner layer482; a second alternating stack (232,246) of second insulating layers232and second electrically conductive layers246located over the joint-level electrically conductive layer346and the dielectric liner layer482; and a second memory stack structure77comprising a second memory film250and a second vertical semiconductor channel62that is laterally surrounded by the second memory film250and extends through the second alternating stack (232,246) and contacting the first vertical semiconductor channel61.

In one embodiment, a bottommost surface of the second memory film250contacts a topmost surface of the first memory film150within a horizontal plane including a bottommost surface of the second alternating stack (232,246), and a bottommost surface of the second vertical semiconductor channel62is located below the horizontal plane and physically contacts the first vertical semiconductor channel61.

In one embodiment, an inner sidewall of the dielectric liner layer482contacts an outer sidewall of the first memory film150, an annular top surface of the dielectric liner layer482contacts a bottom surface of the second alternating stack (232,246), and the first memory film150and the second memory film250physically contact each other.

In one embodiment, the three-dimensional memory structure comprises a backside blocking dielectric layer44located between each vertically neighboring pair of an insulating layer selected from the first and second insulating layers (132,232) and an electrically conductive layer selected from the first and second electrically conductive layers (146,246). The backside blocking dielectric layer44contacts outer sidewalls of the first memory film150and the second memory film250, a top surface of the horizontal portion of the annular dielectric spacer, an outer sidewall of the cylindrical vertical portion of the annular dielectric spacer, and a bottommost surface of the second alternating stack.

Referring to each of the exemplary structures of the present disclosure and alternative embodiments thereof, each three-dimensional memory device of the present disclosure can comprise a monolithic three-dimensional NAND memory device. The first and second electrically conductive layers (146,246) can comprise, or can be electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device. However, the at least one joint-level electrically conductive layers346does not comprise, and is not electrically connected to, any word line of the monolithic three-dimensional NAND memory device. Each of the at least one joint-level electrically conductive layers346is only capacitively coupled to the at least one doped semiconductor portion {(173,179), (173,273,373),173} or the first vertical semiconductor channel61, and controls the electrical current through the vertical semiconductor channel of each vertical NAND string.

In one embodiment, a terrace region can be provided, in which each electrically conductive layer (146,246) other than a topmost electrically conductive layer within the first and second alternating stacks (132,146,232,246) laterally extends farther than any overlying electrically conductive layer within the first and second alternating stacks (132,146,232,246). The terrace region includes stepped surfaces of the first and second alternating stacks (132,146,232,246) that continuously extend from a bottommost layer within the first and second alternating stacks (132,146,232,246) to a topmost layer within the first and second alternating stacks (132,146,232,246). Each subset of the first and second support pillar structures (227,155) extends through the stepped surfaces and through a respective retro-stepped dielectric material portion (165or265) that overlies the stepped surfaces.

Each of the word line contact via structures (which is a subset of the layer contact via structures86that contact the first and second electrically conductive layers (146,246)) can contact a respective electrically conductive layer among the first and second electrically conductive layers (146,246) in the terrace region.

Each of the first and second exemplary structures can include a three-dimensional memory device. In one embodiment, the three-dimensional memory device comprises a vertical NAND memory device. The electrically conductive layers46can comprise, or can be electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device. The substrate (9,10) can comprise a silicon substrate. The vertical NAND memory device can comprise an array of monolithic three-dimensional NAND strings over the silicon substrate. At least one memory cell (as embodied as a portion of a memory material layer54at a level of an electrically conductive layer (146,246)) in a first device level of the array of monolithic three-dimensional NAND strings can be located over another memory cell (as embodied as another portion of the memory material layer54at a level of another electrically conductive layer (146,246)) in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate can contain an integrated circuit comprising a driver circuit for the memory device located thereon. The electrically conductive layers46can comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate (9,10), e.g., between a pair of backside trenches79. The plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level. The array of monolithic three-dimensional NAND strings can comprise: a plurality of semiconductor channels (59,11,61,62), wherein at least one end portion60of each of the plurality of semiconductor channels (59,11,61,62) extends substantially perpendicular to a top surface of the substrate (9,10); and a plurality of charge storage elements (as embodied as portions of the memory material layer located at levels of the electrically conductive layers46). Each charge storage element can be located adjacent to a respective one of the plurality of semiconductor channels (59,11,61,62).

Impact of misalignment of memory stack structures in different tier structures can be alleviated by providing a joint-level electrically conductive layer346that functions as a dummy electrode that is not coupled to any charge storage element. The at least one doped semiconductor portion {(173,179), (173,273,373),173} or the dielectric liner layer482provide a robust alignment and connection scheme between each pair of a first memory opening fill structure57and a second memory opening fill structure77. Further, the at least one joint-level electrically conductive layer346provides additional control for the channel current through each vertical semiconductor channel of the vertical NAND strings.

The methods of the present disclosure can be employed in conjunction with other integrations schemes that provide vertical stacking of multiple tier structures, each including an alternating stack of insulating layers and electrically conductive layers. For example, a subset of tier structures within a three-dimensional memory device may employ landing pads that are formed in a topmost insulating layer. In this case, tier-level memory openings can be formed through a respective alternating stack for at least one tier structure, and the top of each tier-level memory openings can be widened to provide landing pad regions. The tier-level memory openings including the widened portions can be filled with a sacrificial material, and an upper tier structure can be formed thereabove. Additional memory openings can be formed through the upper tier structure, and the sacrificial material can be removed to form inter-tier memory openings that extend through multiple tier structures. While misalignment between vertically adjacent openings are typically accumulative, use of the landing pads can be a cost-effective approach for providing multi-tier memory structures. By combining the methods of the present disclosure in combination with such integration schemes that provide vertical stacking through use of landing pads, the advantage of the present disclosure can be further utilized.