Media clock recovery

A system recovers a local media clock from a master media clock based on time-stamped packets received from a transmitter. The packets may include audio, video, or a combination of both, sampled at a rate determined by the master media clock at the transmitter. Timestamps in the packets may be based on values of a remote real-time counter at the transmitter that is synchronized with a local real-time counter at a receiver. The local media clock may be syntonized with the master media clock through the clock periods. The clocks may be synchronized by syntonizing the clocks and adjusting the phase of the local media clocks based on timestamps and a real-time counter.

BACKGROUND OF THE INVENTION

1. Technical Field

This application relates to media streams and, in particular, to the recovery of a media clock from time-stamped packets in media streams.

2. Related Art

Audio/video media streams may be transmitted from a transmitter to a receiver. A clock or counter at the receiver may be synchronized with a clock or counter at the transmitter through a clock synchronization protocol. Examples of clock synchronization protocols include IEEE (Institute of Electrical and Electronics Engineers) 1588:2002 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems, and IEEE 802.1AS Precision Time Protocol (PTP) in IEEE 802.1AS Standard for Local and Metropolitan Area Networks—Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks.

The clock synchronization protocol may include a protocol for exchanging messages between nodes to synchronize the clock at the receiver with the clock at the transmitter or with a clock at some other node. For example, PTP nodes may exchange Ethernet messages that synchronize the PTP nodes to a common time reference by providing clock master selection and negotiation mechanisms, link delay measurement and compensation, and clock rate matching and adjustment mechanisms. PTP provides a Best Master Clock Algorithm (BMCA), which is an algorithm for negotiating which of the clocks in the PTP nodes is to be the master clock. In particular, BMCA describes a negotiation and a signaling mechanism that identifies a grandmaster node. Once the grandmaster node is selected, synchronization may begin automatically between the grandmaster node and the other PTP nodes known as slave nodes. PTP messages transmitted from the grandmaster node, the slave nodes, or both, may include a timestamp value taken from a Real-Time Counter (RTC). The slave nodes may compare a value of the RTC of the slave nodes with a value of the RTC at the grandmaster node. By using link delay measurement and compensation techniques, the slave nodes may synchronize the RTC in each of the slave nodes with the RTC at the grandmaster node. Once the RTCs are synchronized with each other, periodic messages may provide information that enables the PTP rate matching adjustment algorithms. As a result, the PTP nodes may remain synchronized to a common time. However, the clock synchronization protocol does not perform media clock recovery.

SUMMARY

A system may recover a local media clock from a master media clock based on time-stamped packets received from a transmitter. The system may receive a media stream that was sampled at a rate determined by the master media clock at the transmitter. The system may include a frequency synthesizer, a local real-time counter, a period determination module, and a syntonization adjustment module. The frequency synthesizer may generate the local media clock. The local real-time counter may be synchronized with a remote real-time counter in the transmitter using a clock synchronization protocol. The period determination module may determine the period of the local media clock from a change in the local real-time counter over one or more cycles of the local media clock. The period determination module may also determine the period of the master media clock from the differences in timestamps included in the time-stamped packets. The syntonization adjustment module may cause the frequency synthesizer to adjust the frequency of the local media clock to match the frequency of the master media clock based on any difference between the period of the local media clock and the period of the master media clock.

The system may also include a synchronization adjustment module. The synchronization adjustment module may cause the frequency synthesizer to adjust the phase of the local media clock to match the phase of the master media clock. The synchronization adjustment module may determine the phase adjustment from a difference between a timestamp in a time-stamped packet and a value read from the local real-time counter when the synchronization adjustment module reads the timestamp of the time-stamped packet.

DETAILED DESCRIPTION

A transmitter may be a device that transmits data over a network. The transmitter may include one or more elements that transmit a media stream over the network. For example, the transmitter may be a networked DVD (Digital Video Disc) player that transmits an audio/video stream. The receiver may receive and process the media stream transmitted by the transmitter. The receiver may include one or more elements that receive the media stream over the network. For example, the receiver may be a digital signal processor. A Real-Time Counter (RTC) at the transmitter and at the receiver may be controlled by a RTC clock at the transmitter and the receiver, respectively. A clock synchronization protocol may synchronize the RTCs and the RTC clocks. Prior to being transmitted by the transmitter to the receiver, an audio/video media stream may be provided to the transmitter at a rate associated with a master media clock. Because the master media clock and the RTC clock at the transmitter may be different from each other, the characteristics of the master media clock, such as frequency, may be different than the RTC clock. The receiver may provide both the recovered media stream and a local media clock to a consumer component or client of the media stream. The consumer component may read the media stream on an edge of the local media clock. In one example, the consumer component may include an I2S (Integrated Interchip Sound) compliant device that reads a word of sampled data from a set of data lines at a rate determined by a clock on a word clock line. The receiver may generate the local media clock on the word clock line and provide each word of the media stream on the set of data lines in compliance with the I2S standard. The receiver may generate the local media clock such that the local media clock at the receiver is synchronized with the master media clock at the transmitter.

The receiver may recover multiple media clocks. One receiver may receive audio/video media streams from multiple transmitters nearly simultaneously, where each one of the media streams is provided to the transmitters at a rate determined by a different one of the multiple media clocks. Each one of the media clocks may be different from the other media clocks. Each one of the media clocks may have different characteristics than the RTC clocks at the receivers. Alternatively or in addition, one receiver may receive multiple media streams from a single transmitter, where each of the multiple media streams is sampled at a different rate than the others because the multiple media streams are sampled at rates determined by multiple master media clocks. Alternatively or in addition, multiple media streams may be sampled at a single common rate.

A system may generate the local media clock at the receiver from time-stamped packets received from the transmitter. The local media clock may be generated with a frequency synthesizer, such as a Direct Digital Synthesizer (DDS). The period of the master media clock may be determined at the receiver based on a change in a first set of timestamps included in the time-stamped packets. The first set of timestamps may be values of the RTC at the transmitter sampled at a frequency determined by the master media clock. For example, the RTC at the transmitter may be sampled at a frequency equal to the frequency of the master media clock. The timestamps and sampled values of the media stream may be received at the transmitter in the time-stamped packets. The sampled values of the media stream may have been sampled at a rate determined by the master media clock. For example, the sampled values of the media stream may have been sampled at a frequency equal to the frequency of the master media clock. Each of the timestamps in the first set of timestamps may include a value of the RTC sampled as the transmitter prepared to send the packet that includes the timestamp. Each of the packets may include the timestamp and one or more sampled values of the media stream. For example, the transmitter may generate two packets, where each one of the packets includes a timestamp for the audio/video data included in that packet. The period may be calculated at the receiver as a difference between the two timestamps. The RTC at the receiver may be synchronized with the RTC at the transmitter using a clock synchronization protocol, such as PTP.

A second set of timestamps may be read from the RTC at the receiver by sampling the RTC on an edge of the local media clock, such as on a rising edge of the local media clock, a falling edge, or on both. A period of the local media clock may be determined based on a change in the second set of timestamps. The frequency of the local media clock may be adjusted with the frequency synthesizer to limit the difference between the period of the master media clock and the period of the local media clock. In other words, the local media clock may be syntonized with master media clock when the two clocks have the same frequency.

The phase difference between the master media clock and the local media clock may be determined by comparing one or more of the timestamps in the time-stamped packets with one or more corresponding timestamps read from the local RTC. If the master media clock and the local media clock are syntonized, then a difference between a timestamp in one of the packets and a value of the RTC in the receiver may indicate the extent of a phase shift between the master media clock and the local media clock. The difference between the timestamp in the packet and the value of the RTC, when divided by the period of the master media clock, may generate a remainder that indicates the phase difference between the master media clock and the local media clock. If the phase difference is below a threshold value, the clocks may be synchronized. The phase of the local media clock may be adjusted with the frequency synthesizer to limit the phase difference between the master media clock and the local media clock.

FIG. 1illustrates an example of an Audio/Video Packet Management System (AVPM System)100. The AVPM system100includes a MCR (media clock recovery) module102that generates a local media clock104at a receiver106from time-stamped packets108. The MCR module102may be a unitary part of the receiver106, or may be physically separate from, and in communication with, the receiver106. Each one of the time-stamped packets108may include a timestamp110.

InFIG. 1, the receiver106includes a media interface112, a physical media interface114, a local Real-Time Counter (RTC)116, and a header engine118. The media interface112may include the MCR module102. Alternatively, the receiver106may include more, fewer, or different components. For example, the receiver106may not include the physical media interface114.

The AVPM system100may include the receiver106and a transmitter120. The AVPM system100may include more, fewer, or different components. For example, the AVPM system100may only include the receiver106with the local RTC116the MCR module102, or only the local RTC116and the MCR module102without the receiver106. The MCR module102may be any component that generates the local media clock104from the time-stamped packets108and the local RTC116.

The local media clock104may be any periodic signal indicative of a sampling rate of data in a media stream126. For example, the local media clock104may be a square wave, a pulse wave, a sinusoid, or any other suitable periodic wave form. The frequency of the local media clock104may be a multiple or fraction of the sampling rate of the data in the media stream126. In one example, the frequency of the local media clock104may correspond to twice the sampling rate. In a second example, the frequency of the local media clock104may be an eighth of the sampling rate. In a third example, where the media stream126includes NTSC (National Television System Committee) video, the sampling rate may be a pixel clock rate of 27 MHz and the frequency of the local media clock104may be 15.734 kHz, sometimes referred to as the video line rate.

The receiver106may communicate with the transmitter120over a network122. The transmitter120may include a remote Real-Time Counter (RTC)124.

The receiver106may be a circuit, executable instructions retained on a non-transitory media, or combination that receives the time-stamped packets108from the transmitter120. For example, the receiver106may be a circuit, an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). In one example, the receiver106may be a computer, a networking card, an audio digital signal processor, a video signal processor, or other device. The receiver106may be referred to as a listener.

The time-stamped packet108may be a data block that includes a timestamp110. The time-stamped packet108may include at least a portion of the media stream126. Alternatively or in addition, the time-stamped packet108may be a data block without any portion of the media stream126, but that is received by the receiver106along with other packets that include at least a portion of the media stream126. For example, the time-stamped packet108may include an IEEE P1722 packet.

The timestamp110may include a value read from the remote RTC124or a value derived from a value read from the remote RTC124. The timestamp110may be dimensionless. For example, the timestamp110may be a value of an accumulator register included in the remote RTC124. Alternatively, the timestamp110may include a unit of time. In one example, the timestamp110may be a sum of a value read from the remote RTC124and a delay value, where the delay value is indicative of a maximum transmission delay between the transmitter120and any receiver, such as the receiver106.

The media interface112may be a circuit, executable instructions retained on a non-transitory media, or combination thereof that generates the media stream126on a per-media clock domain basis from the time-stamped packets108. A media clock domain may be the sampling rate of data in a stream. The media clock domain may be 44.1 kilohertz, 48 kilohertz, 96 kilohertz, or 192 kilohertz, for example. The media interface112may provide the media stream126and the local media clock104to the physical media interface114. Alternatively or in addition, the media interface112may provide a clock derived from the local media clock104to the physical media interface114. In yet other alternative, the media interface112may provide the media stream126and the local media clock104directly to another component of the receiver106without the physical media interface114.

The physical media interface114may include a physical transport medium that is electrically coupled to the media interface112for transporting the media stream126to a suitable component. Examples of the physical media interface114include an I×S (Time-Division Multiplexing) serial connection, an IEC (International Electrotechnical Commission) 60958 SPDIF interface, an MPEG2/4 (Moving Pictures Expert Group) interface, an interface for H.264 Transport Streams, an interface for Bt.601/656 raw video, an interface available from LINKPORT, which is a registered trademark of Compex, Inc. of Anaheim, Calif., or other tangible data transport components. Driver code in the physical media interface114may read data in the media stream126, directly or indirectly, out of buffer memory in the media interface112. The driver code may transmit the data in the media stream126to devices other than the receiver106and the transmitter120, such as to a personal computer. The physical media interface114may propagate the local media clock104, or a clock signal derived from the local media clock104, to the other devices.

The receiver106may include multiple media interfaces112and multiple corresponding physical media interfaces114. Each of the media interfaces112may include the MCR module102for the media clock domain applicable to that media interface112. Consequently, the receiver106may receive multiple media streams from one or more transmitters120where at least one of the media streams is sampled at a different media clock domain than the other media streams. For example, one of the media streams may be sampled at about 44.1 kilohertz, while another one of the media streams may be sampled at about 192 kilohertz. One of the media interfaces112may provide the media stream126sampled at about 44.1 kilohertz, and a different one of the media interfaces112may provide the media stream126sampled at about 192 kilohertz. The MCR module102in each one of the media interfaces112may generate the local media clock104used by that media interface112. The MCR module102in a first one of the media interfaces112may generate the first local media clock104at about 44.1 kilohertz and the MCR module102in a second one of the media interfaces112may generate the second local media clock104at 192 kilohertz. The media streams may or may not be related. Alternatively or in addition, the single MCR module102may generate the local media clock104for multiple media streams sampled at a common rate.

The local RTC116and the remote RTC124may be a counter that increases or decreases at a rate determined by a clock, such a RTC clock127at the receiver106and a RTC clock128at the transmitter120. For example, the local RTC116and the remote RTC124may be implemented as accumulation registers, digital counters, real-time clock ICs (integrated circuits) or any other suitable devices. A digital counter may be any semiconductor device that counts the number of times a digital event has occurred. The digital event may be a rising or falling edge of the RTC clock127or128, for example. The local RTC116and the remote RTC124may be synchronized using any known clock synchronization protocol.

The header engine118may be a circuit, executable instructions retained on a non-transitory media, or combination thereof that processes the time-stamped packets108received over the network122and extracts packet header information, such as the timestamp110, from the time-stamped packets108. The header engine118may also provide the payload132to other components of the receiver106. The payload132may be a portion of the media stream126that is included in the time-stamped packets108.

The timestamp110may be a presentation time130. The presentation time130may be the time, according to the local RTC116, at which the portion of the media stream126included in the payload132is to be presented to the physical media interface114. In one example, the presentation time130may be the timestamp110included in the time-stamped packet108. In a second example, the presentation time130may be the timestamp110plus a propagation delay value. In a third example, the presentation time130may be any other value derived from the timestamp110in the packet108.

The header engine118may also determine the number of samples of the media stream126between timestamps, which is referred to as SYT_INTERVAL134or ISYT. Each one of the time-stamped packets108may include multiple data blocks in the payload132, where each one of the data blocks corresponds to a sample of the media stream126. Additionally, a single one of the data blocks may include sampled values of more than one media streams, or channels, such as a sampled value of a left audio channel and a sampled value of a right audio channel. Each one of the data blocks may include a sampled value of each one of the media streams. In one example, each one of the time-stamped packets108may include only one timestamp110even though each one of the time-stamped packets108may include multiple samples of the media stream126. Including one timestamp110for multiple samples or data blocks may be more efficient than including one timestamp110for each individual data block or sample. Thus, the SYT_INTERVAL134may be the number of data blocks in the payload132in some examples. In one example, a DBC (data block count) in an AVBTP (Audio/Video Bridging Transport Protocol) header may indicate how often AVBTP presentation timestamps are included in the time-stamped packets108as compared to the number of data blocks in the time-stamped packets108, so the header engine118may set SYT_INTERVAL134to the DBC. In a second example, the SFC (Sampling Frequency Code) field of the FDF (Format Dependent Field) portion of the CIP (Common Isochronous Packet) header may provide the number of samples between timestamps in an IEEE P1722 packet, so the header engine118may set SYT_INTERVAL134to the SFC. In a third example, the SYT_INTERVAL134may be the value “1,” because the timestamp110is included for each data block in the payload132. In a forth example, the SYT_INTERVAL134may not be determined or used.

The transmitter120may be a circuit, executable instructions retained on a non-transitory media, or combination thereof that transmits the time-stamped packets108over the network122. For example, the transmitter120may be a circuit, an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Alternatively, the transmitter120may be a computer, a networking device for a computer, an audio digital signal processor, a video signal processor, or other device. The transmitter120may be referred to as a talker or a speaker.

The network122may be a communications network. For example, the network122may include a local area network (LAN), a wireless local area network (WLAN), a personal area network (PAN), a wide area network (WAN), the Internet, a combination thereof. The network122may support communications protocols that communicate the time-stamped packets108and other packets, such as those used by the clock synchronization protocol.

During operation of the AVPM system100, the transmitter120and the receiver106may communicate with each other using the clock synchronization protocol. Based on the messages exchanged between the transmitter120and the receiver106, the remote RTC124and the local RTC116may be synchronized.

The transmitter120may receive a source media stream136sampled in accordance with a master media clock138. The transmitter120may generate one of the time-stamped packets108by reading a value of the remote RTC124, adding a maximum delay, and storing the sum as the timestamp110in the packet108. The transmitter120may store a portion of the source media stream136in the time-stamped packet108and may transmit the time-stamped packet108over the network122. The transmitter120may repeat the process of reading the value of the remote RTC124, generating the timestamp110, storing the next portion of the source media stream136, and transmitting the next one of the time-stamped packets108over the network122. Through this process, the transmitter120may transmit the source media stream136to the receiver106.

The header engine118may process the time-stamped packets108. The header engine118may extract the timestamp110from each of the time-stamped packets108. The header engine may pass the payload132from the time-stamped packets108to other components of the receiver106, such as the media interface112. The header engine118may provide the timestamp110or a derivation thereof to the media interface112. The header engine118may provide the SYT_INTERVAL134to the media interface112.

The MCR module102in the media interface112may perform media clock recovery by reading values of the local RTC116and processing the timestamp110and the SYT_INTERVAL134to generate the local media clock104. The media interface112may provide the local media clock104and the media stream126to the physical media interface114. Alternatively, the MCR module102may receive the time-stamped packets108or portions thereof, and communicate with the local RTC116through other components.

FIG. 2illustrates the MCR module102that generates the local media clock104. The MCR module102may include a period determination module202, a syntonization calculation module204, a syntonization adjustment module206, a synchronization calculation module208, a synchronization adjustment module210, and a frequency synthesizer212. Other MCR modules102may include more, fewer, or different components.

The syntonization calculation module204determines a period difference218and generates a syntonized flag220. The period difference218may be the difference in the master period214and the local period216. The syntonized flag220may indicate whether the master media clock138is syntonized with the local media clock104.

The syntonization adjustment module206directs the frequency synthesizer212to adjust the frequency of the local media clock104in accordance with a frequency adjustment222. The frequency adjustment222may be a value that the frequency synthesizer212accepts to adjust the frequency of the local media clock104.

The synchronization adjustment module210directs the frequency synthesizer212to adjust the phase of the local media clock104in accordance with a phase adjustment228. The phase adjustment228may be a value that the frequency synthesizer212accepts to adjust the phase of the local media clock104. In one example, the phase adjustment228may be the phase adjust value224. In a second example, the phase adjustment228may be derived from the phase adjust value224, such as where the synchronization adjustment module210accepts frequency adjustments in a different format, such as an output frequency instead of an adjustment to the output frequency.

The frequency synthesizer212generates a range of frequencies to form an output signal, such as the local media clock104, from a fixed time base or oscillator, such as a reference clock230. The frequency synthesizer212may include a DDS (direct digital synthesizer), a Direct Analog Synthesis, a digital PLL (phase-locked loop) synthesizer such as an integer-N synthesizer and a fractional-N synthesizer, or another type of synthesizer. In one example implementation of the frequency synthesizer, the frequency synthesizer212may include a counter that wraps back to zero when saturated. Whenever a) the counter wraps, the level of the local media clock104may be toggled. The rate at which the counter wraps may be adjusted by varying an increment size used to increment the counter. For example, an increment size of 1 wraps much less often than an increment size of 100. Instead of varying the increment size, the value at which the counter wraps back to zero may be varied while maintaining a constant increment size. The counter may be driven by the reference clock230, which controls when the counter increments. The frequency synthesizer212may adjust the phase and frequency of the local media clock104based on input values. The frequency synthesizer212may, for example, execute Taylor Series correction algorithms to bring the spurious free dynamic range (SFDR) to at least 150 decibels and, as a result, minimize output jitter.

The frequency synthesizer212may accept the frequency adjustment222as an input value. In response, the frequency synthesizer212may produce a constant frequency signal, such as the local media clock104, based on the frequency adjustment222. If the frequency synthesizer212is a DDS, the equation for calculating the frequency adjustment222, M, for the DDS may be, for example:
M=2n(Tref/Tout)
where n is the number of bits in an accumulator that holds the frequency adjustment222, Trefis the period of the reference clock230, and Toutis the desired output period. Frequency is the number of occurrences of a repeating event per unit time. The period is the duration of one cycle in a repeating event, so the period is the reciprocal of the frequency. In terms of the frequency of the local media clock104, fout, and the frequency of the reference clock230, frefmay be expressed as
fout=(fref*M)/2n
where n is the number of bits in an accumulator that holds the frequency adjustment222, M. The frequency of the local media clock104, fout, may be expressed as the frequency adjustment222, M, multiplied by the reference frequency, fref, divided by 2n. In one example, if the frequency of the reference clock230is 125 MHz and n is 48, then the frequency resolution of the DDS is 0.000000444 Hz, which is 125 Mhz divided by 2n. Thus, M may be selected so that the frequency of the local media clock104, fout, matches any target frequency.

In addition to the frequency adjustment222, the frequency synthesizer212may accept the phase adjustment228as an input value. The frequency synthesizer212may adjust the phase of the local media clock104based on the phase adjustment228. If the frequency adjustment222is increased, then the frequency synthesizer212may shift the phase of the local media clock104in one direction. In contrast, if the frequency adjustment222is decreased, then the frequency synthesizer212may shift the phase in the other direction.

During operation of the MCR module102, the MCR module102may sequentially receive SYT_INTERVAL134and the timestamp110for each of the time-stamped packets108. The MCR module102may receive SYT_INTERVAL134and the timestamp110from the header engine118. Alternatively, the MCR module102may sequentially receive the timestamp110for each of the time-stamped packets108without receiving SYT_INTERVAL134.

The period determination module202may determine the master period214by comparing the timestamp110with the timestamp110in a previously received time-stamped packet108. The period determination module202may subtract the timestamps110to determine the elapsed time between the packets108as a change in the remote RTC124. If only one sample of the source media stream136is included in each of the time-stamped packets, then the elapsed time between the packets108may be the period214of the master media clock138. If there is one timestamp110and SYT_INTERVAL134samples in each of the time-stamped packets108, then the period214of the master media clock138may be the elapsed time divided by SYT_INTERVAL134. The period determination module202may average the change in timestamps, filter the change in timestamps, or otherwise process the change in timestamps in order to calculate the master period214.

In one example, the frequency of the master media clock138, fS, may be expressed as a function of timestamps:
fS=[(tB−tA)*10−9/SYT_INTERVAL]−1=[SYT_INTERVAL/(tB−tA)]*109
where tAis the timestamp in a first one of the time-stamped packets108and tBis the timestamp in a second one of the time-stamped packets108. For example, the frequency of the master media clock138may be 8/(3A48A25016−3A46175016)*109, which is about 48,003.07 Hz, where SYT_INTERVAL is 8, tBis 3A48A25016nanoseconds, and tAis 3A46175016nanoseconds.

In addition to the master period214, the period determination module202may determine the local period216. The period determination module202may read a local RTC timestamp232from the local RTC116in response to detecting a rising edge of the local media clock104, a falling edge of the local media clock104, or a combination of both. The period determination module202may subtract the sampled local RTC timestamps232to determine the elapsed time between samples as a change in the local RTC116. The period determination module202may average the change in timestamps, filter the change in timestamps, or otherwise process the change in timestamps in order to calculate the period216of the local media clock104over time.

The syntonization calculation module204may receive the master period214and the local period216from the period determination module202. The syntonization calculation module204may determine the period difference218. The period difference218may be the master period214subtracted from the local period216. The syntonization calculation module204may average, filter, or otherwise process the difference between the master period214and the local period216in order to determine the period difference218.

The syntonization calculation module204may determine the syntonized flag220based on the period difference218. If the absolute value of the period difference218is zero or about zero or less than a threshold value, then the syntonized flag220may indicate that the local media clock104is syntonized with the master media clock138. In contrast, if the absolute value of the period difference218is greater than a threshold value, then the syntonized flag220may indicate that the local media clock104is not syntonized with the master media clock138.

If the syntonized flag220indicates that the local and master media clocks104and138are not syntonized, then the syntonization adjustment module206may increment or decrement the frequency adjustment222, M, as described above, so that the frequency of the local media clock104, fout, is closer to the frequency of the master media clock138, fS. The syntonization adjustment module206may communicate the frequency adjustment222to the frequency synthesizer212.

The described process may be repeated until the local and master media clocks104and138are syntonized. The period determination module202may re-calculate the periods214and216, the syntonization calculation module204may set the syntonized flag220accordingly, and the syntonization adjustment module206may re-determine and re-transmit the frequency adjustment222to the frequency synthesizer212, until the syntonized flag220indicates the master and local media clocks104and138are syntonized. The process may be repeated multiple times because of lost packets or other abnormalities causing variations in the determination of the periods214and216. One such abnormality includes round-off errors due to limitations in the accuracy of the timestamp110. The described process may continue even after the local and master media clocks104and138are syntonized

If the syntonized flag220indicates that the local media clocks104and138are syntonized, then the synchronization calculation module208may determine whether the master and local media clocks104and138are synchronized. The synchronization calculation module208may set the synchronized flag226accordingly. The synchronization calculation module208may receive the local period216, the master period214, or both from the period determination module202. When the master and local media clocks104and138are syntonized, then the local period216and the master period214may be the same value: a syntonized period. For example, the syntonized period may be the local period216, the master period214, or derived from both, such as a sum of the local period216and the master period214divided by two.

The timestamp110received in the time-stamped packet108may be the presentation time130. If so, when the receiver106receives the time-stamped packet108, the presentation time130will likely be greater than the local RTC timestamp232read from the local RTC116. In particular, the presentation time130may be many multiples of the syntonized period greater than the local RTC timestamp232. Therefore, the difference between the presentation time130and the local RTC timestamp232may be divided by the syntonized period to determine a phase difference between the master media clock138and the local media clock104. The phase difference may be the remainder of the difference between the presentation time130and the local RTC timestamp232divided by the syntonized period. The synchronization calculation module208may determine the phase adjust value224to be the phase difference. If the phase adjust value224is about zero or a value less than a threshold value, then the synchronization calculation module208may determine that the master and local media clocks104and138are synchronized and set the synchronized flag226accordingly.

If the synchronized flag226indicates that the master and local media clocks104and138are not synchronized, then the synchronization adjustment module210may determine the phase adjustment228from the phase adjust value224received from the synchronization calculation module208. The synchronization adjustment module210may communicate the phase adjustment228to the frequency synthesizer212. In response, the frequency synthesizer212may adjust the phase of the local media clock104. The period determination module202, the syntonization calculation module204, the syntonization adjustment module206, the synchronization calculation module208and the synchronization adjustment modules210may repeat the above described operations until the local and master media clocks104and138are synchronized.

Even after the local and master media clocks104and138are synchronized, the process may continue indefinitely. If the local and master media clocks104and138are synchronized, then no further adjustments are made. Nevertheless, because of inaccuracies, such as clock drift, round-off error, non-exact period matching, and other abnormalities, the local and master media clocks104and138may eventually stray from each other, so continuing the process indefinitely facilitates updating the local media clock104to match the master media clock138to compensate for the inaccuracies.

Due to the feedback nature of the system100, large sweeping adjustments may cause the control system to become unstable. Accordingly, relatively small adjustments may made to bring the local media clock104closer to the desired frequency, which may result in a gradual convergence to the desired frequency. Because a large initial error may cause the system100to take a relatively long time to converge on the desired frequency using relatively small adjustments, a tiered approach may be used. Accordingly, if the initial error is large, then a large coarse adjustment may be made. As the errors get smaller, the adjustment may become smaller.

FIG. 3illustrates an example of the period determination module202. The period determination module202may include a packet timestamp delay302, a packet timestamp adder304, a packet timestamp FIR (finite impulse response) filter306, a local timestamp delay308, a local timestamp adder310, a local timestamp FIR filter312, and a scale adjustment module314. The period determination module202may include more, fewer, or different components. For example, the period determination module202may not include the scale adjustment module314. In yet another example, the period determination module202may not include the packet timestamp FIR filter306and the local timestamp FIR filter312.

The packet timestamp delay302or the local timestamp delay308may include any component that outputs a previous input value. The packet timestamp and the local timestamp delays302and308may delay a fixed amount of time. The packet timestamp and the local timestamp delays302and308may be, for example, a buffer component controlled by a signal, such that on the rising or falling edge of the signal, the buffer reads an input value and outputs an output value equal to the input value read N cycles of the signal ago. The signal for the packet timestamp delay302may be a timestamp valid signal316indicating the period determination module202is to process the timestamp110recently received in the time-stamped packet108. The header engine118may cause the timestamp valid signal316to rise as each one of the time-stamped packets108is processed and to fall between processing of the time-stamped packets108. Alternatively, a different component of the receiver106may generate the timestamp valid signal316. For example, a stream identifier filter may generate the timestamp valid signal316in response to determining that a stream id in the packet108identifies a stream that the receiver106is receiving. The signal for the local timestamp delay308may be the local media clock104. Examples of the delays302and308include a delay element described in HDL (hardware description language) and implemented in a FPGA (field programmable gate array), a semiconductor buffer element, and executable instructions stored in computer-readable storage media.

The packet timestamp adder304or the local timestamp adder310may include any component that outputs a difference between two inputs. The adders304and310may include an adder element described in HDL and implemented in a FPGA, a semiconductor buffer element, and instructions executable by a processor.

The packet timestamp FIR filter306or local timestamp FIR filter312may include hardware and/or software that selectively passes certain elements of a signal while eliminating or compensating others. The FIR filters306and312may be weighted average filters. The FIR filters306and312may average the last N timestamp deltas (change in timestamps) thereby filtering anomalous input timestamp deltas or limiting the effect of anomalous input timestamp deltas. The packet timestamp FIR filter306may be a standard 256-tap filter, and the local timestamp FIR filter312may be a standard 32-tap filter. The packet timestamp FIR filter306and the local timestamp FIR filter312may be of different orders and be a different type of filter. The FIR filters306and312may include a filter element described in HDL and implemented in a FPGA, a semiconductor buffer element, an off-the shelf discrete component, and executable instructions retained in a computer readable media.

The scale adjustment module314may include hardware and/or software that adjust outputs of the FIR filters306and312so that the master period214and the local period216are at the same scale. For example, the scale adjustment module314may compensate for SYT_INTERVAL134being non-zero. The scale adjustment module314may divide the output of the packet timestamp FIR filter306by SYT_INTERVAL134. Alternatively, the scale adjustment module314may multiply the output of the local timestamp FIR filter312by SYT_INTERVAL134. Alternatively or in addition, the scale adjustment module314may adjust for differences in a delay of the packet timestamp delay302and a delay of the local timestamp delay308. If the local timestamp delay308buffers a value for N cycles of the local media clock104, then the scale adjustment module314may divide the output of the local timestamp FIR filter312by N. Alternatively or in addition, the scale adjustment module314may convert between internal number formats for implementation reasons, such as between floating point and fixed scale. The scale adjustment module314may include components described in HDL and implemented in a FPGA, an application specific integrated circuit (ASIC), and executable instructions retained in a computer readable media.

During operation of the period determination module202, the period determination module202may receive the timestamp valid signal316, the timestamps110in the time-stamped packets108, SYT_INTERVAL134, the local RTC timestamps232, and the local media clock104as inputs. The period determination module202may generate the master period214and the local period216from these inputs.

The period determination module202may wait for the timestamp valid signal316to indicate that the timestamp110from the time-stamped packet108may be processed. For example, the packet timestamp delay302and the packet timestamp FIR306may be clocked by the timestamp valid signal316.

In response to the timestamp valid signal316indicating that the timestamp100is valid, the packet timestamp delay302may store the current timestamp110, TS, and output an old timestamp318, TSold, which was previously received as an input to the packet timestamp delay302. The packet timestamp adder304may determine a raw period320, Traw, of the master media clock138by subtracting the old timestamp318, TSoldfrom the current timestamp110, TS. In one example, the raw period320, Traw, may be the master period214multiplied by SYT_INTERVAL134.

In response to the timestamp valid signal316indicating that the timestamp100is valid, the packet timestamp FIR filter306may sum the raw period320with previously generated raw periods and output an average raw period322of the master media clock138. The packet timestamp FIR filter306may be a 256-tap FIR filter with constant coefficients that sums the last 256 raw period values320generated by the packet timestamp adder304. The 256-tap FIR filter may thereby generate a fixed-point average raw period322with eight binary bits of fractional precision. The packet timestamp FIR filter306may be of a different order and be configured differently.

The period determination module202may determine the local period216of the local media clock104in response to detecting a falling edge, a rising edge, or both of the local media clock104. The local timestamp delay308and the local timestamp FIR filter312may be clocked by the local media clock104. The local timestamp delay308may read the current local RTC timestamp232from the local RTC116and output an old RTC timestamp324, RTCold, in response to detecting a falling edge of the local media clock104. The local timestamp adder310may determine a raw period326, Traw, of the local media clock104by subtracting the old RTC timestamp324from the current local RTC timestamp232. Also, in response to detecting the falling edge of the local media clock104, the local timestamp FIR filter312may sum the raw period326with previously generated raw periods to output an average raw period328of the master media clock138. The local timestamp FIR filter312may be a 32-tap FIR filter with constant coefficients. After calculating 32 raw period values, the 32-tap FIR filter may generate the average raw period328of the local media clock104as a fixed-point average with five binary bits of fractional precision. The local timestamp FIR filter312may be of a different order or be configured differently.

The order of the local timestamp FIR filter312may be less than the order of the packet timestamp FIR filter306. For example, the order of the local timestamp FIR filter312may be 32 and the order of the packet timestamp FIR filter306may be 256. The lower order local timestamp FIR filter312may limit the number of raw period values summed. Thus, the local timestamp FIR filter312may respond quickly to adjustments in frequency or phase made by the frequency synthesizer212. As a result, however, some precision may be lost when calculating the local period216as compared with calculating the master period214.

The scale adjustment module314may adjust the average raw period322of the master media clock138and the average raw period328of the local media clock104so that the master period214and the local period216are at the same scale. The scale adjustment module314may divide the average raw period322of the master media clock138by SYT_INTERVAL134to determine at the master period214.

FIG. 4illustrates an example of the syntonization calculation module204and the syntonization adjustment module206. The syntonization calculation module204may include a period adder402, a PID (proportional integral derivative) controller404, an averager component406, and a hysteresis component408. Alternatively, the syntonization calculation module204may include more, fewer, or different components. For example, the syntonization calculation module204may not include the averager component406.

The period adder402may include hardware and/or software that calculates a difference between two inputs. The period adder402may determine a difference410between the master period214and the local period216.

The PID controller404may be a control loop feedback controller. The PID controller may be tuned by, for example, three separate parameters: a proportional value, an integral value, and a derivative value, denoted P, I, and D, respectively. The proportional value may determine the reaction to a current error, the integral value may determine the reaction based on the sum of recent errors, and the derivative value may determine the reaction based on the rate at which the error has been changing. The error may be the difference410between the master period214and the local period216. The weighted sum412of these three values may ultimately be used to adjust the frequency of the local media clock104.

The averager component406may include hardware and/or software that averages an input value. The averager component406may average the weighted sum412generated by the PID controller404. The averager component406may include, for example, an N-order FIR filter414that sums the weighted sums412generated by the PID controller404over N cycles of a clock that controls the averager component406. The clock that controls the averager component406may be the local media clock104. In an alternative example, the clock that controls the average component406may be the timestamp valid signal316. Alternatively, the clock that controls the average component406may be unrelated to the timestamp valid signal316and the local and master media clocks104and138. The N-order FIR filter414may be a 32-tap filter or any other suitable order. The averager component406may also include a division component416that divides the output of the N-order FIR filter414by N in order to calculate the average of the weighted sums412generated by the PID controller404. The average of the weighted sums412generated by the PID controller404may be the period difference218generated by the syntonization calculation module204. Alternatively, the N-order FIR filter414may determine the period difference218without the division component416.

The hysteresis component408may include hardware and/or software that converts a numerical number input into a Boolean output based on hysteresis. If the Boolean output is y and the input is u, then y may be determined as follows: y=false if y=true and u<=ulow; y=true if y=false and u>=uhigh; and y=ypreviousotherwise. The values ulowand uhighare threshold values.

During operation of the syntonization calculation module204, the syntonization calculation module204may determine the period difference218and the syntonized flag220. The period adder402may determine the difference410between the master period214and the local period216. The difference410between the master period214and the local period216represents a measurement of error in the local period216, because the master period214and the local period216are ideally the same when the master media clock138is syntonized with the local media clock104.

The PID controller404may reduce overshoot or other effects of adjusting the frequency of the local media clock104. In particular, the PID controller404may generate the PID values from the difference410between the master period214and the local period216, and determine the weighted sum412of the PID values. The averager component406may determine the period difference218from the weighted sum412of the PID values, further reducing the effect of anomalous differences410between the master period214and the local period216.

The hysteresis component408may receive the period difference218from the averager component406. The hysteresis component408may generate the syntonized flag220from the period difference218.

The syntonization adjustment module206may include a comparator418and an adjustment adder420. Alternatively, the syntonization adjustment module206may include more, fewer, or different components. For example, syntonization adjustment module206may not include the adjustment adder420.

The comparator418may be hardware and/or software that compares two inputs and generates an output to indicate which of the inputs is larger. For example, the comparator418may be an operational amplifier configured as a comparator.

The adjustment adder420may include hardware and/or software that sums two inputs. For example, the adjustment adder420may be an accumulator register.

During operation of the syntonization adjustment module206, the syntonization adjustment module206may receive the period difference218and the syntonized flag220from the syntonization calculation module204, determine the frequency adjustment222, and transmit the frequency adjustment222to the frequency synthesizer212.

If the syntonized flag220indicates that the local media clock104is syntonized with the master media clock138, then the syntonization adjustment module206may not transmit the frequency adjustment222to the frequency synthesizer212. However, if the syntonized flag220indicates that the local media clock104is not syntonized with the master media clock138, then the syntonization adjustment module206may determine and transmit the frequency adjustment222to the frequency synthesizer212.

The comparator418may compare the period difference218with a zero reference or some other threshold value. The comparator418may then output an adjust value422that is either a positive or negative number depending on comparison. The adjust value422may therefore indicate whether the frequency of the local media clock104should increase or decrease, and by how much.

If the frequency adjustment222is a value that indicates at what frequency the frequency synthesizer212should generate the local media clock104, then the adjustment adder420may add the adjust value422to the frequency adjustment222last transmitted to the frequency synthesizer212to obtain the frequency adjustment222. Alternatively, if the frequency adjustment222is a value that indicates how much the frequency of the local media clock104should change, then the syntonization adjustment module206may set the frequency adjustment222to the adjust value422.

FIG. 5illustrates an example of the synchronization calculation module208and the synchronization adjustment module210. The synchronization calculation module208may include a timestamp adder502, a modulo component504, a comparator506, an adjustment direction component508, an adjustment adder510, and a hysteresis component512. Alternatively, the synchronization calculation module208may include more, fewer, or different components.

The timestamp adder502may include hardware and/or software that determines a difference between two inputs and outputs the difference. The timestamp adder502may output a timestamp difference513that is a difference between the timestamp110of the time-stamped packet108and the local RTC timestamp232.

The modulo component504may include hardware and/or software that outputs the remainder of a division of one input value by another input value. The modulo component504may output a phase difference514between the local media clock104and the master media clock138as the remainder of the timestamp difference513divided by the syntonized period518. The syntonized period518may be the master period214or the local period216, which are substantially the same value when the local media clock104is syntonized with the master media clock138.

The comparator506may include hardware and/or software that compares two input values and determines whether one is greater than the other. The comparator506may compare a lock threshold516with the phase difference514between the local media clock104and the master media clock138to determine which is greater than the other. The lock threshold516may be any value less than a period of the local media clock104. For example, the lock threshold516may be the syntonized period518divided by two, or any other suitable value.

The adjustment direction component508may include hardware and/or software that generates a negative value if a Boolean input is true and a positive value if the Boolean input is false. The adjustment direction component508may generate the negative value as an adjustment direction520if the comparator506indicates the phase difference514is less than the lock threshold516, such as half of the syntonized period518, and generate the positive value as the adjustment direction520otherwise. The adjustment direction520may be any value indicating a direction the phase of the local media clock104is to be adjusted. For example, the adjustment direction520may be one or negative one.

The adjustment adder510may include hardware and/or software that sums two input values. The adjustment adder510may update the phase adjustment value224by adding the adjustment direction520or any predetermined constant to the phase adjustment value224. The phase adjustment may not be applied if the modulo component504outputs a zero result. If the modulo component504outputs a zero result, then the local and master media clocks104and138are in phase and no adjustment is needed. If non-zero, an adjustment may be made in a direction that brings the local and master media clocks104and138more in phase with each other. The phase adjust value224may initially be set to zero because no phase adjustment in either direction has occurred.

The hysteresis component512may include hardware and/or software that converts a numerical number input into a Boolean output based on hysteresis. For example, if the Boolean output is y and the input is u, then y may be determined as follows: y=false if y=true and u<=ulow; y=true if y=false and u>=uhigh; and y=ypreviousotherwise. The values ulowand uhighare threshold values. The Boolean output of the hysteresis component512may be the synchronized flag226and the input of the hysteresis component512may be the phase adjust value224.

The synchronization adjustment module210may include a phase adder522. Alternatively, the synchronization adjustment module210may include more, fewer, or different components. For example, the synchronization adjustment module210may include multiple phase adders522, one for each local media clock104.

The phase adder522may include hardware and/or software that sums two input values. The phase adder522may sum the phase adjust value224and the current phase adjustment228and output the phase adjustment228.

During operation of the synchronization calculation module208, the synchronization calculation module208may wait until the syntonized flag220indicates that the local media clock104is syntonized with the master media clock138before determining the synchronized flag226and the phase adjust value224. Alternatively, the synchronization calculation module208may determine the synchronized flag226and the phase adjust value224regardless of whether the syntonized flag220indicates the local media clock104is syntonized with the master media clock138. In one example, the synchronization calculation module208may be clocked by the local media clock, the timestamp valid signal316, or any other suitable signal. In a second example, the synchronization calculation module may be executed by a processor in response to an interrupt.

Due to the clock synchronization protocol, the remote RTC124and the local RTC116may have substantially the same value. If the timestamp110is the presentation time130described above, then the timestamp110in the packet108may be far ahead of the local RTC timestamp232read from the local RTC116when the packet108is processed. The modulo component504may determine the phase difference514as mod(Y−X, T), where Y is the timestamp110in the time-stamped packet108generated based on a value read from the remote RTC124on an edge of the master media clock138; X is the local RTC timestamp232read from the local RTC116on an edge of the local media clock104; T is the syntonized period518; and mod() is the modulo operator. Because the periods of the master and local media clocks138and104have been made the same, the modulo operator may remove any full cycles of the master and local media clocks138and104, so that the modulo operator generates the phase difference514.

The combination of the comparator506and the adjustment direction component508may determine the adjustment direction520. The adjustment direction520may be useful because the process of synchronization may be faster if the phase of the local media clock104is shifted in one direction than the other.

The hysteresis component512may set the synchronized flag226from the phase adjust value224. The synchronization adjustment module210may receive the synchronized flag226and the phase adjust value224from the synchronization calculation module208. The synchronization adjustment module210may receive the syntonized flag220from the syntonization calculation module204or another module.

If the synchronized flag226indicates that the master and local media clocks138and104are not synchronized and the syntonized flag22indicates the clocks are syntonized, then the synchronization adjustment module210may determine the phase adjustment228, and transmit the phase adjustment228to the frequency synthesizer212. The phase adder522may increment the phase adjustment228by the phase adjust value224. Alternatively, the synchronization adjustment module210may transmit the phase adjust value224to the frequency synthesizer212.

FIG. 6illustrates a flow diagram of the operation of an example of the MCR module102. The operation of the MCR module102may include more, fewer, or different operations than illustrated inFIG. 6. The operations may be executed in an order different than is illustrated inFIG. 6.

The period of the master media clock138may be determined from the timestamps110in the time-stamped packets108(602). The period determination module202may determine the master period214by repeatedly determining the difference between each successive one of the timestamps110in the time-stamped packets108.

The period of the local media clock104may be determined by sampling the local RTC116(604). The period determination module202may determine the local period216by repeatedly reading the local RTC timestamp232from the local RTC116on the rising edge of the local media clock104and determining the difference between each successive one of the local RTC timestamps232. Although the period of the master media clock138is determined before the period of the local media clock104in the example illustrated inFIG. 6, the order may be reversed or the periods may be determined at substantially the same time in other examples.

A determination may be made whether the master media clock138and the local media clock104are syntonized (606). The syntonization calculation module204may compare the period difference218between the master period214and the local period216with a threshold value. If the master media clock138and the local media clock104are not syntonized, then the frequency adjustment222may be determined from the period difference218(608). The frequency of the local media clock104may be adjusted accordingly (610). The syntonization adjustment module206may determine the frequency adjustment222and transmit the frequency adjustment222to the frequency synthesizer212. The frequency synthesizer212may adjust the frequency of the local media clock104accordingly. The operation may repeat by returning to the operation where the period of the master media clock138is determined (602). Alternatively or in addition, the operation may delay (612) prior to beginning again.

Alternatively, if the master media clock138and the local media clock104are syntonized, then the phase adjust value224may be determined (614). A determination may be made whether the master media clock138and the local media clock104are synchronized from the phase adjust value224(616). For example, the synchronization calculation module208may determine the phase adjust value224and set the synchronization flag226accordingly.

If the synchronization flag226indicates that the master media clock138and the local media clock104are synchronized, then the operation may end. In one example, the operation may end by beginning again at the operation where the period of the master media clock138is determined from the timestamps110in the time-stamped packets108(602). Alternatively or in addition, the operation may delay prior to beginning again at the operation where the period of the master media clock138is determined from the timestamps110in the time-stamped packets108(602). In a second example, the operation may continue to generate the local media clock104without further modification of the local media clock104.

Alternatively, if the synchronization flag226indicates that the master media clock138and the local media clock104are not synchronized, then the phase adjustment228may be determined (618). The phase of the local media clock104may be adjusted based on the phase adjustment228(620). The synchronization adjustment module210may determine the phase adjustment228and transmit the phase adjustment228to the frequency synthesizer212. The frequency synthesizer212may adjust the phase of the local media clock104accordingly. In one example, the operation may begin again by returning to the operation where the period of the master media clock138is determined from the timestamps110in the time-stamped packets108(602). Alternatively or in addition, the operation may continue by delaying (622) before returning to the operation where the period of the master media clock138is determined from the timestamps110in the time-stamped packets108(602). In a second example, the master and the local clocks138and104may be assumed to still be syntonized, and the operation returns to where the phase adjust value224is determined (614).

FIG. 7illustrates an example of a hardware diagram of the MCR module102. The MCR module102may include a logic circuit702, a processor704, and a memory706. The processor704may be in communication with the logic circuit702and the memory706over a bus708.

Alternatively, the MCR module102may include more, fewer, or different components. For example, the logic circuit702may include the processor704and the memory706. In one example, the entire MCR module102may be included in the logic circuit702. The logic circuit702may be a field programmable gate array (FPGA), the bus708may be a processor local bus (PLB), and the processor704may be a soft core processor, such as MicroBlaze designed for Xilinx FPGAs from Xilinx™, a registered trademark of Xilinx, Inc of San Jose, Calif. The receiver106and the MCR module102may be implemented in the logic circuit702. The MCR module102may be implemented partially or completely in an FPGA, an application-specific integrated circuit (ASIC), a complex programmable logic device (CPLD), or any other discrete physical component. In a second example, the memory706may include all of the components of the MCR module102other than the processor704and the frequency synthesizer212.

The logic circuit702may include any hardware and/or software device, such as an integrated circuit, discrete physical components, or any combination thereof. The logic circuit702may include an FPGA, an application-specific integrated circuit (ASIC), a complex programmable logic device (CPLD), off-the self components, or any combination thereof. The logic circuit702may be a circuit generated from a hardware description language (HDL), such as Verilog HDL. The logic circuit702may include an implementation of the period determination module202, the syntonization calculation module204, the synchronization calculation module208, the frequency synthesizer212, or any other part the MCR module102or the receiver106.

The memory706may be a data storage device or combination of data storage devices. The memory706may include non-volatile and/or volatile memory, such as a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), flash memory, any other type of computer readable media, or any combination thereof. Alternatively or in addition, the memory706may include an optical, magnetic (hard-drive) or any other form of data storage device. The memory706may be included in the logic circuit702.

The processor704may be any hardware component that executes computer readable instructions. For example, the processor704may be a microcontroller, a soft core processor, an ASIC (application-specific integrated circuit), an FPGA (field programmable gate array), a CPLD (complex programmable logic device), a central processing unit of a computing device, a general processor, a digital signal processor, a digital circuit, an analog circuit, or any combination thereof.

The memory706may include computer code. The computer code may include instructions executable with the processor704. The computer code may be written in any computer language now known or later discovered, such as C++, C#, Java, Pascal, Visual Basic, Perl, HyperText Markup Language (HTML), JavaScript, assembly language, and any combination of computer languages. The computer code may include source code and/or compiled code.

The memory706may store program logic that implements the synchronization adjustment module210, the syntonization adjustment module206, or any other part of the MCR module102other than the frequency synthesizer212. For example, the memory706may store program logic that implements the scale adjustment module314in the period determination module202. In one example, the memory706may include program logic that implements the period determination module202, the syntonization calculation module204, and the synchronization calculation module208.

The bus708may be an interface that transfers data between components. The components may include the logic circuit702, the processor704, the memory706, or any other device. The bus708may include a data bus internal to a computing device, a parallel bus, a serial bus, a PLB (Processor Local Bus), or any other tangible medium for transferring data between components.

The AVPM system100, including the MCR module102in particular, may be implemented in many different ways. For example, although some features are shown stored in the computer-readable memory706(e.g., as logic implemented as computer-executable instructions or as data structures in memory), all or part of the AVPM system100or the MCR module102, other than the frequency synthesizer212, may be stored on, distributed across, or read from the memory706or some other machine-readable media. The computer-readable media may include RAM, an optical storage device, a magnetic storage device, a hard disk, a floppy disk, a CD-ROM, a solid state memory device, or any other form of tangible storage device. Alternatively or in addition, all or part of the AVPM system100and the MCR module102may be implemented in the logic circuit702.

The processing capability of the AVPM system100and the MCR module102may be distributed among multiple entity or nodes, such as among multiple processors and memories, optionally including multiple distributed processing systems. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may implemented with different types of data structures such as linked lists, hash tables, or implicit storage mechanisms. Logic, such as programs or circuitry, may be combined or split among multiple programs, distributed across several memories and processors, and may be implemented in a library, such as a shared library (e.g., a dynamic link library (DLL)). The DLL, for example, may store code that calculates the frequency adjustment222. As another example, the DLL may itself provide a portion of the functionality of the AVPM system100, MCR module102, or both. The processor704may be in communication with the memory706and the logic circuit702. The processor704may also be in communication with additional elements, such as a network interface configured to send and receive data over the network122.

The processor704may be one or more devices operable to execute computer executable instructions or computer code embodied in the memory706or in other memory in order to perform the features of the MCR module102, the receiver106, or any combination thereof. The syntonization adjustment module206, when executed by the processor704, may read the period difference218and syntonized flag220from the syntonization calculation module204over the bus708. The syntonization adjustment module206may also transmit the frequency adjustment222to the frequency synthesizer212over the bus708. Alternatively or in addition, the synchronous adjustment module210, when executed by the processor704, may read the synchronized flag226and the phase adjust value224from the synchronization calculation module208over the bus708. The synchronous adjustment module210may also transmit the phase adjustment228to the frequency synthesizer212over the bus708.

Furthermore, although specific components of innovations were described, methods, systems, and articles of manufacture consistent with the innovation may include additional or different components. For example, a processor may be implemented as a microprocessor, microcontroller, application specific integrated circuit (ASIC), discrete logic, or a combination of other type of circuits or logic. Similarly, memories may be DRAM, SRAM, Flash or any other type of memory. Flags, data, tables, entities, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be distributed, or may be logically and physically organized in many different ways. The components, other than the frequency synthesizer212, may be non-transitory computer readable media encoded with computer readable instructions. The components may operate independently or be part of a same program. The components may be resident on separate hardware, such as separate removable circuit boards, or share common hardware, such as a same memory and processor for implementing instructions from the memory. Programs may be parts of a single program, separate programs, or distributed across several memories and processors. For example, the syntonization calculation module204may be separated into multiple components, and the synchronization calculation module208may include the synchronization adjustment module210.

The respective logic, software or instructions for implementing the processes, methods and/or techniques discussed above may be provided on computer-readable media or memories or other tangible media, such as a cache, buffer, RAM, removable media, hard drive, other computer readable storage media, or any other tangible media or any combination thereof. The tangible media include various types of volatile and nonvolatile storage media. The functions, acts or tasks illustrated in the figures or described above may be executed in response to one or more sets of logic or instructions stored in or on computer readable media. The functions, acts or tasks are independent of the particular type of instructions set, storage media, processor or processing strategy, and may be performed by software, hardware, integrated circuits, firmware, micro code and the like, operating alone or in combination. Likewise, processing strategies may include multiprocessing, multitasking, parallel processing and the like. In one example, the instructions are stored on a removable media device for reading by local or remote systems. In other examples, the logic or instructions are stored in a remote location for transfer through a computer network or over telephone lines. In yet other examples, the logic or instructions are stored within a given computer, central processing unit (“CPU”), graphics processing unit (“GPU”), or system.

The term “audio/video” may mean audio, video, or both. Thus, in one example, “audio/video” means only audio. In a second example, “audio/video” means only video. In a third example, “audio/video” means a combination of audio and video.

While various examples of the invention have been described, it will be apparent to those of ordinary skill in the art that many more examples and implementations are possible within the scope of the invention. Accordingly, the invention is not to be restricted except in light of the attached claims and their equivalents.