Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits

Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir. Annealing extends the interfacial oxide layer into the semiconductor substrate at portions of the semiconductor substrate that underlie the oxygen reservoir to form a regrown interfacial region in or on the semiconductor substrate.

TECHNICAL FIELD

The technical field generally relates to methods of scaling a thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming integrated circuits, and integrated circuits. More particularly, the technical field relates to methods of scaling a thickness of an interfacial oxide layer that enables selective regrowth of the interfacial oxide layer.

BACKGROUND

Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel and that is separated from the channel by a gate dielectric structure. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.

As advanced metal-oxide-semiconductor (MOS) technology continues to scale and move into the deep-sub-micron geometry dimensions, scaling of the gate dielectric structure has been widely explored to minimize inversion thickness (Tinv), i.e., thickness of an inversion layer or inversion channel within the gate dielectric structure, while maintaining operability of the MOSFETs. One technique that has been employed to scale Tinvwhile maintaining operability of the MOSFETs is to include one or more high-k dielectric layer in the gate dielectric structure in combination with an interfacial oxide layer such as silicon oxide. The high-k dielectric layer enables Tinvto be scale down to about 14 Å without sacrificing reliability of the FETs. As used herein, high dielectric constant or “high k” means having a dielectric constant greater than about 3.9. However, further scaling of Tinvoften results in poor reliability of the resulting FETs, with leakage current through the gate dielectric structure increasing exponentially with the decrease in the Tinv. Nitridation of the interfacial oxide layer has also been employed in combination with use of the high-k dielectric layer to provide Tinvscaling without sacrificing reliability of N-type FETs. For example, Tinvof the gate dielectric structure can be effectively scaled by another 2 Å through nitridation of the interfacial oxide layer. However, nitridation of the interfacial oxide layer negatively impacts reliability of P-type FETs, where negative bias temperature instability (NBTI) is a function of nitrogen in the gate dielectric structure. Regrowth of the interfacial oxide layer through annealing in an oxygenated environment may reverse the impact of nitridation on reliability of the P-type FETs. However, interfacial oxide layer regrowth also occurs at locations of the N-type FETs, thereby negating the benefits of nitridation on Tinvscaling for the N-type FETs. Further, annealing in the oxygenated environment may also adversely impact dielectric properties of the high-k dielectric layer.

Accordingly, it is desirable to provide methods of scaling thickness of a gate dielectric structure that enables selective regrowth of the interfacial oxide layer at particular locations of the interfacial oxide layer while also minimizing impact on dielectric properties of the high-k dielectric layer. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.

BRIEF SUMMARY

Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided herein. In an embodiment, a method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir. Annealing extends the interfacial oxide layer into the semiconductor substrate at portions of the semiconductor substrate that underlie the oxygen reservoir to form a regrown interfacial region in or on the semiconductor substrate.

In another embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate that includes an N-type field effect transistor well and a P-type field effect transistor well. An interfacial oxide layer is formed within the N-type field effect transistor well and the P-type field effect transistor well. The interfacial oxide layer is nitrided, and a high-k dielectric layer is formed over the interfacial oxide layer after nitriding the interfacial oxide layer. An oxygen reservoir is formed over at least the P-type field effect transistor well. The semiconductor substrate including the oxygen reservoir disposed on the semiconductor substrate is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir. Annealing extends the interfacial oxide layer into the P-type field effect transistor well to form an regrown interfacial region. A gate electrode structure is formed over the N-type field effect transistor well and the P-type field effect transistor well including over the regrown interfacial region.

In another embodiment, an integrated circuit includes a semiconductor substrate that includes an N-type field effect transistor well and a P-type field effect transistor well. An interfacial oxide layer is disposed over the N-type field effect transistor well and the P-type field effect transistor well. A high-k dielectric layer is disposed over the interfacial oxide layer. A regrown interfacial region is formed in the P-type field effect transistor well adjacent to the interfacial oxide layer. The N-type field effect transistor well is free from the regrown interfacial region. A gate electrode structure is disposed over the N-type field effect transistor well and the P-type field effect transistor well including over the regrown interfacial region.

DETAILED DESCRIPTION

Provided herein is a method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, as well as integrated circuits and methods of forming integrated circuits with a scaled gate dielectric structure that overlies the semiconductor substrate. Scaling, as described herein, refers to modification of a thickness of a gate dielectric structure. The gate dielectric structure, as described herein, refers to all layers of dielectric material that are disposed over and/or within the semiconductor substrate and over which a gate electrode structure is to be formed in accordance with conventional MOS fabrication, with the gate dielectric structure being disposed between the semiconductor substrate and the gate electrode structure. In accordance with the methods described herein, an interfacial oxide layer is formed in or on the semiconductor substrate and a high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer where regrowth of interfacial oxide is desired, with a sealant layer formed over the oxygen reservoir. The oxygen reservoir, as referred to herein, is a structure that provides a source of oxygen under annealing conditions. The sealant layer is a structure that effectively inhibits oxygen diffusion thereinto. The interfacial oxide layer is extended into the semiconductor substrate at portions of the semiconductor substrate that underlie the oxygen reservoir by annealing the semiconductor substrate to form a regrown interfacial region in or on the semiconductor substrate, with the regrown interfacial region including an oxide of the semiconductor material in the semiconductor substrate. In particular, the oxygen reservoir provides oxygen that diffuses through the high-k dielectric layer and the interfacial oxide layer to form the regrown interfacial region in areas of the semiconductor substrate that underlie the oxygen reservoir, with the sealant layer inhibiting excessive ambient oxygen from diffusing into the high-k dielectric layer during annealing. As a result, the regrown interfacial region includes an oxide material that is similar in composition to the interfacial oxide layer. In this manner, selective formation of the regrown interfacial region may be achieved in desired areas of the semiconductor substrate while minimizing impact on dielectric properties of the high-k dielectric layer and while also maintaining benefits associated with Tinvscaling through nitridation in other areas of the semiconductor substrate. As such, the regrown interfacial region alleviates reliability concerns that may arise due to excessive Tinvscaling of the interfacial oxide layer and may be selectively formed only in areas of the semiconductor substrate that could give rise to reliability concerns.

Referring toFIG. 1, in accordance with an exemplary embodiment of a method for forming an integrated circuit, a semiconductor substrate10is provided. The semiconductor substrate10includes semiconductor material. As used herein, the phrase “semiconductor material” includes monocrystalline silicon materials, such as relatively pure or lightly impurity-doped monocrystalline silicon materials typically used in the semiconductor industry, as well as polycrystalline silicon materials, and silicon admixed with other elements such as germanium, carbon, and the like. In addition, “semiconductor material” encompasses other materials such as relatively pure and impurity-doped germanium, gallium arsenide, zinc oxide, glass, and the like. In the embodiment shown inFIG. 1, the semiconductor substrate10is a bulk silicon material. It is to be appreciated that, although not shown, additional layers may be present below the semiconductor substrate10in accordance with conventional integrated circuit configurations.

In an embodiment and as shown inFIG. 1, the semiconductor substrate10includes a P-type field effect transistor (FET) well12and an N-type FET well14, in anticipation of forming P-type FETs (PFETs) and N-type FETs (PFETs) in accordance with conventional integrated circuit fabrication. In particular, the semiconductor substrate10is configured for later formation of a complimentary MOS integrated circuit (CMOS IC), which includes both NMOS FETs and PMOS FETs. To form the P-type FET well12and the N-type FET well14, the semiconductor substrate10may be doped with an appropriate dopant, i.e., a conventional p-type or n-type dopant. The methods described herein are particularly suitable when both the P-type FET well12and the N-type FET well14are present in the semiconductor substrate10because Tinvscaling considerations are different for gate dielectric structures over the P-type FET well12and the N-type FET well14, with the methods provided for selective techniques for Tinvscaling to enable separate Tinvscaling for regions of the semiconductor substrate10with the P-type FET well12and the N-type FET well14.

Referring again toFIG. 1, in an embodiment an interfacial oxide layer16is formed in or on the semiconductor substrate10, such as within the N-type FET well14and the P-type FET well12of the semiconductor substrate10. The interfacial oxide layer16, as referred to herein, is an oxide of the semiconductor material of the semiconductor substrate10and is one layer in a gate dielectric structure18that is shown inFIG. 2. The interfacial oxide layer16may be formed through a dedicated technique that is intended to only form the interfacial oxide layer16, or may be passively formed as a result of other processing techniques such as during pre-cleaning or during subsequent formation and thermal treatment of a high-k dielectric layer over the semiconductor substrate10, as described in further detail below. Although conventional techniques for forming the interfacial oxide layer16may be employed, an example of dedicated technique that is suitable for forming the interfacial oxide layer16is wet chemical oxidation through treatment with a mixture of ammonium hydroxide, hydrogen peroxide and water at an ambient temperature of about 21° C. The interfacial oxide layer16helps minimize mobility degradation in the semiconductor substrate10that may otherwise occur due to high-k dielectric material in a subsequently-formed high-k dielectric layer in the gate dielectric structure, as described in further detail below. However, the interfacial oxide layer16is generally thicker than necessary and may be thinned to decrease Tinvof the gate dielectric structure that includes the interfacial oxide layer16and the high-k dielectric layer. Typically, the thickness of the interfacial oxide layer16is from about 13 Å to about 40 Å, although lesser and greater thicknesses are also contemplated herein. In accordance with the methods described herein, even thinner initial thickness of the interfacial oxide layer16, below 10 Å, is possible, with later oxide regrowth selectively employed to thicken the interfacial oxide layer16where desired. Thinning of the interfacial oxide layer16may be conducted through conventional techniques such as wet cleans that leave hydrogen terminated molecules on a surface of the interfacial oxide layer.

In an embodiment, the interfacial oxide layer16is nitrided. Nitriding the interfacial oxide layer16results in introduction of nitrogen into the interfacial oxide layer16to produce oxynitride such as, for example, silicon oxynitride. Because silicon oxynitride has a higher k-value than silicon oxide, further scaling of the interfacial oxide layer16after nitridation by an additional 2 Å (such as down to 11 Å) is possible while maintaining reliability of the NFET that is ultimately formed over the N-type FET well14. However, reliability of the PFET that is ultimately formed over the P-type FET well12is compromised by nitriding and scaling the Tinvof the interfacial oxide layer16. In particular, negative bias temperature instability in the PFET is associated with nitridation of the interfacial oxide layer16, leading to shift in voltage threshold over time. The methods described herein address and alleviate PFET reliability concerns that are associated with nitridation of the interfacial oxide layer16, as described in further detail below. Nitridation may be conducted through conventional techniques such as through rapid thermal annealing (RTA) in an ammonia ambient, or through direct plasma nitridation (DPN).

After optional nitridation and as shown inFIG. 2, a high-k dielectric layer20is formed over the interfacial oxide layer16. In an embodiment, the high-k dielectric layer20is formed directly on the interfacial oxide layer16. The high-k dielectric layer20may be formed through conventional techniques, and may include any material that has a dielectric constant greater than about 3.9. Examples of suitable high-k dielectric materials include, but are not limited to, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, strontium oxide, iridium oxide, aluminum oxide, and the like. Tinvis generally minimized such that the thickness of the high-k dielectric layer20is also minimized while maintaining performance. The high-k dielectric layer20may have a thickness of from about 5 Å to about 30 Å.

In an embodiment and as shown inFIG. 3, an oxygen reservoir22is formed over at least a portion of the high-k dielectric layer20for purposes of providing a source of oxygen that enables later regrowing of the interfacial oxide within the semiconductor substrate10as described in further detail below. In embodiments and as shown inFIG. 3, the oxygen reservoir22is disposed directly upon the high-k dielectric layer20. However, in other embodiments and referring momentarily toFIG. 6, one or more additional layers32,34may be disposed between the oxygen reservoir22and the high-k dielectric layer20as described in further detail below. The oxygen reservoir22may be formed over at least the P-type FET well12, with later regrowth of the interfacial oxide alleviating any reliability concerns associated with the optional nitridation of the interfacial oxide layer16. For example, in an embodiment and as shown inFIG. 3, the oxygen reservoir22is formed over only a portion of the high-k dielectric layer20, such as over the P-type FET well12, with an exposed portion24of the high-k dielectric layer20free from the oxygen reservoir22. The oxygen reservoir22may be formed over only the portion of the high-k dielectric layer20by conventional patterning a blanket-formed layer of material for the oxygen reservoir22in a desired configuration of the oxygen reservoir22. In this embodiment, oxide regrowth within the semiconductor substrate10at the exposed portion24can be minimized or avoided while enabling oxide regrowth in areas of the semiconductor substrate10that underlie the oxygen reservoir22.

Suitable materials for the oxygen reservoir22include any material that provides a source of oxygen under annealing conditions. Additionally, in various embodiments the oxygen reservoir22is removed prior to gate electrode formation and, thus, includes material that may be selectively removed from the high-k dielectric layer20. However, it is to be appreciated that in embodiments, the oxygen reservoir22may remain disposed over the semiconductor substrate10in the final integrated circuit. Various metal nitrides and metal carbides may be suitable materials for the oxygen reservoir22, and the oxygen reservoir22may include at least about 99 weight % or those materials, with oxygen present in the oxygen reservoir22as a result of conventional formation techniques. In particular, CVD, PVD, ALD techniques may be employed to form the oxygen reservoir22from materials such as, but not limited to, titanium nitride, tantalum nitride, tungsten nitride, titanium carbide, tantalum carbide, and/or tungsten carbide. The aforementioned materials experience natural oxidation after deposition or tend to attract oxygen as an impurity during deposition. Further, the aforementioned materials have a propensity to lose oxygen during subsequent annealing and certain materials more readily release oxygen than other of the materials. For instance, tantalum nitride loses oxygen more readily than titanium nitride. In a specific embodiment, the oxygen reservoir22includes titanium nitride. In another specific embodiment, the oxygen reservoir22includes tantalum nitride. Thickness of the oxygen reservoir22may also affect proper function of the oxygen reservoir22as a source of sufficient amounts of oxygen to enable oxide regrowth within the semiconductor substrate10, and the thickness may depend upon particular thicknesses of the high-k dielectric layer20and the interfacial oxide layer16. In a specific embodiment, where thickness of the interfacial oxide layer16is minimized to about 11 Å after nitridation and where the high-k dielectric layer20has a minimized thickness of about 5 Å, an appropriate thickness of the oxygen reservoir22that includes titanium nitride is at least about 2 nm, such as about 10 nm. Because tantalum nitride provides oxygen at a higher rate than titanium nitride, an appropriate thickness of the oxygen reservoir22that includes tantalum nitride is at least about 0.5 nm, such as about 2 nm.

Referring toFIG. 4, a sealant layer36is formed over the oxygen reservoir22for inhibiting excessive ambient oxygen from diffusing into the high-k dielectric layer20during annealing. The sealant layer36enables controllable interfacial oxide regrowth under appropriate annealing conditions while minimizing an unpredictable impact from environmental oxygen during annealing. Examples of suitable materials for the sealant layer36include, but are not limited to, semiconductor or dielectric materials. Examples of suitable semiconductor materials include, but are not limited to amorphous or crystalline silicon. Examples of suitable dielectric materials include, but are not limited to, silicon nitride and silicon oxide. In various embodiments, the sealant layer36is formed from a material that may be selectively removed from a layer that is disposed directly beneath the sealant layer36. Thickness of the sealant layer36may also impact performance of the sealant layer36. For example, the sealant layer36may have a thickness of from about 3 to about 20 nm to enable the sealant layer36to effectively inhibit diffusion of environmental oxygen therethrough an into the oxygen reservoir22during annealing.

In various embodiments and although not shown in the Figures, the sealant layer36may be disposed directly upon the oxygen reservoir22and on the exposed portion24of the high-k metal layer. However, one or more intervening layers38,40may be disposed between the sealant layer36and the oxygen reservoir22and/or between the sealant layer36and the exposed portion24of the high-k dielectric layer20. The one or more intervening layers38,40may be incorporated for various purposes. For example, depending upon the material chosen for the sealant layer36, the material of the sealant layer36may diffuse into, react with, or otherwise affect the dielectric properties of the high-k dielectric layer20. In an embodiment and as shown inFIG. 4, to avoid interaction between the sealant layer36and the exposed portion24of the high-k dielectric layer20, one of the intervening layers38,40is a delamination structure38that is formed over the oxygen reservoir22and over the exposed portion24of the high-k dielectric layer20prior to forming the sealant layer36over the oxygen reservoir22. The delamination structure38provides a physical barrier between the sealant layer36and the exposed portion24of the high-k dielectric layer20and may include any material that may be selectively etched from at least the high-k dielectric layer20and that does not materially degrade the dielectric properties of the high-k dielectric layer20. In an embodiment, the delamination structure38includes a nitride such as titanium nitride. Notably, titanium nitride may be employed to form both the delamination structure38and the oxygen reservoir22, which the distinction being thickness of the respective structures. In this embodiment, the delamination structure38is sufficiently thin to inhibit oxide regrowth in the semiconductor substrate10beneath the exposed portion24of the high-k dielectric layer20while having sufficient thickness to inhibit interaction between the sealant layer36and the high-k dielectric layer20. For example, the delamination structure38may have a thickness of from about 0.5 to less than about 2 nm, especially when titanium nitride is used.

Another type of intervening layer that may be incorporated between the sealant layer36and the oxygen reservoir22and/or between the sealant layer36and the exposed portion24of the high-k dielectric layer20is a leakage inhibiting layer40, which may be formed independent of the delamination structure38. The leakage inhibiting layer40may be formed prior to forming the delamination structure38, with the delamination structure38formed over the leakage inhibiting layer40when both are present. At thin Tinvleakage current through the high-k dielectric layer20and the interfacial oxide layer16may impact device performance especially at the N-type FET well14. By forming the leakage inhibiting layer40over the oxygen reservoir22and over the exposed portion24of the high-k dielectric layer20, selective formation of the leakage inhibiting layer40may be achieved with the leakage inhibiting layer40separated from the portion of the high-k dielectric layer20that underlies the oxygen reservoir22. During annealing, the material from the leakage inhibiting layer40may be driven into the high-k dielectric layer20in the exposed portion24of the high-k dielectric layer20, resulting in a modified high-k dielectric layer42as shown inFIG. 5. Suitable materials for the leakage inhibiting layer40include, but are not limited to, lanthanides such as lanthanum oxide.

After the sealant layer36is in place, the semiconductor substrate10including the oxygen reservoir22and the sealant layer36, among other structures described above, is annealed to diffuse oxygen through the high-k dielectric layer20and the interfacial oxide layer16from the oxygen reservoir22. Annealing, as referred to herein, is any type of treatment at high environmental temperatures (greater than ambient temperature) around the semiconductor substrate10. Annealing is effective to extend the interfacial oxide layer16into the semiconductor substrate10at portions of the interfacial oxide layer16that underlie the oxygen reservoir22to thereby form a regrown interfacial region44in the semiconductor substrate10. For example and as shown inFIG. 4, the interfacial oxide layer16may be extended into the P-type FET well12adjacent to the interfacial oxide layer16to form the regrown interfacial region44, thereby alleviating the impact of nitridation on PFET reliability. In the embodiment shown inFIG. 4, because the oxygen reservoir22is not disposed over the N-type FET well14, the N-type FET well14is free from the regrown interfacial region. The regrown interfacial region44, as referred to herein, is any extension of oxide material into the semiconductor substrate10that forms beneath the oxygen reservoir22and that is not present prior to annealing.

Suitable annealing conditions may be readily determined based upon materials of the oxygen reservoir22and thickness of various layers over the semiconductor substrate10. In embodiments, annealing is conducted through conventional techniques such as, but not limited to, a spiked annealing process, rapid thermal annealing, laser annealing, or in a conventional furnace. Annealing may be conducted with a peak environmental temperature, i.e., temperature of a gaseous environment surrounding the semiconductor substrate10and overlying structures, of at least 700° C. For example, in a specific embodiment for the structure as shown inFIG. 4, the spiked annealing process can be conducted by gradually increasing environmental temperature to a peak temperature in a range of from about 950° C. to about 1000° C. and maintained at the peak temperature for about 5 seconds. However, exact conditions may be dependent upon the desired thickness of the regrown interfacial region44.

After annealing, various layers may be removed from over the semiconductor substrate10. For example, in an embodiment, the sealant layer, the delamination structure, and the oxygen reservoir may be removed after annealing through conventional techniques such as etching. The resulting structure may then be further prepared for FEOL processing, including gate electrode formation, to produce an integrated circuit46including a gate electrode structure48as shown inFIG. 5. In particular, in the embodiment shown inFIG. 5, gate electrode structures48are formed over the N-type FET well14and the P-type FET well12including over the regrown interfacial region44, with a shallow trench isolation (STI) structure56and sidewall spacers58formed in accordance with conventional FEOL processing. Although not shown, source and drain regions as well as other features may be formed in accordance with conventional FEOL processing to complete formation of PFETs and NFETs over the semiconductor substrate10. In other embodiments and although not shown, the delamination layer and the oxygen reservoir may optionally remain disposed over the semiconductor substrate and can be incorporated into the final integrated circuit. However, the sealant layer is generally removed after annealing in all embodiments.

Another embodiment of a method of forming an integrated circuit will now be described with reference toFIG. 6. The semiconductor substrate10is provided and the interfacial oxide layer16and high-k dielectric layer20are formed over the semiconductor substrate10in the same manner as described above. However, in this embodiment and as alluded to above, one or more additional layers32,34are disposed between the oxygen reservoir22and the high-k dielectric layer20and are formed prior to forming the oxygen reservoir22. In particular, in this embodiment, a combination of protecting layers including a first protecting layer32and a second protecting layer34are formed over the high-k dielectric layer20prior to forming the oxygen reservoir22for purposes of protecting the high-k dielectric layer20during removal of the oxygen reservoir22and to minimize interaction between the sealant layer36and the high-k dielectric layer20. In this embodiment, the first protecting layer32may include tantalum nitride and the second protecting layer34may include titanium nitride, which enables the oxygen reservoir22to be effectively removed under circumstances where the protecting layers32,34are to remain over the semiconductor substrate10during formation of the gate electrode structures and where the oxygen reservoir22contains the same material as the second protecting layer34. However, it is to be appreciated that in other embodiments and although not shown, a single protecting layer may be effective to protect the high-k dielectric layer20. Annealing and FEOL processing may proceed in the same manner as described above.

Another embodiment of a method of forming an integrated circuit will now be described with reference toFIGS. 7 and 8. The semiconductor substrate10is provided and the interfacial oxide layer16and high-k dielectric layer20are formed over the semiconductor substrate10in the same manner as described above. However, in this embodiment, an oxygen reservoir722is continuously formed over the P-type FET well12and over N-type FET well14. Also, in this embodiment, the oxygen reservoir722is schematically shown having a lesser thickness than the oxygen reservoir22ofFIGS. 1-6, and such lesser thickness may be appropriate when tantalum nitride is used in the oxygen reservoir722. To avoid oxide regrowth in the N-type FET well14, an oxygen scavenging structure730may be formed over the N-type FET well14prior to continuously forming the oxygen reservoir722over the P-type FET well12and over N-type FET well14. The oxygen scavenging structure730may include any material that readily reacts with oxygen to thereby inhibit diffusion of oxygen from the oxygen reservoir722through the layers that overlie the N-type FET well14. In embodiments, the oxygen scavenging structure730may include materials chosen from titanium nitride, aluminum-containing materials, and other metals that readily react with oxygen. Thickness of the oxygen scavenging structure730is not limited, provided that the oxygen scavenging structure730effectively inhibits oxide regrowth in the semiconductor substrate10at the N-type FET well14. Under circumstances where titanium nitride is used in the oxygen scavenging structure730, the oxygen scavenging structure730may have a thickness of less than 2 nm to avoid the titanium nitride from functioning as an oxygen reservoir itself. Annealing may proceed in the same manner as described above. However, in an embodiment, the oxygen reservoir722and the oxygen scavenging structure730may remain over the high-k dielectric layer20during formation of the gate electrode structure and may be incorporated into the integrated circuit. In an embodiment and as shown inFIG. 8, a gap fill structure750, such as a tungsten layer formed through chemical vapor deposition, may be formed over the oxygen reservoir722and the oxygen scavenging structure730, followed by electrode formation over the gap fill structure750. FEOL processing may then proceed as described above.