Semiconductor device

A RESURF isolation structure surrounds an outer periphery of the high-side circuit region to isolate the high-side circuit region and the low-side circuit region from each other. The RESURF isolation structure includes a high-voltage isolation region, a high-voltage N-ch MOS, and a high-voltage P-ch MOS. The high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS include a plurality of field plates (9,19a,19b,19c). An inner end of the field plate (19c) of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than an inner end of the field plate (19b) of the high-voltage N-ch MOS located closest to the low-side circuit region.

FIELD

The present invention relates to a semiconductor device including a lateral high-voltage device.

BACKGROUND

An HVIC (High Voltage IC) that drives a power chip in a half bridge configuration includes a low-side circuit region, a high-side circuit region, and a level shift circuit for signal transmission between the low side and the high side. Substrate potential is set as the reference voltage in the low-side circuit region, while the high-side circuit region is isolated from the substrate to have a high breakdown voltage. High-voltage isolation of the high-side circuit region from the substrate voltage is achieved by the RESURF effect. In plan view, the outer periphery of the high-side circuit region is surrounded by a RESURF isolation structure (see, for example, PTL 1).

The level shift circuit includes a high-voltage N-ch MOS that transmits signals from the low-side circuit region to the high-side circuit region, and a high-voltage P-ch MOS that transmits signals from the high-side circuit region to the low-side circuit region. The high-voltage N-ch MOS and the high-voltage P-ch MOS have a breakdown voltage equal to that of the RESURF isolation region surrounding the outer periphery of the high-side circuit region (see, for example, NPL 1), and are formed within the same RESURF isolation region surrounding the outer periphery of the high-side circuit region (see, for example, PTL 2 and NPL 2).

CITATION LIST

Patent Literature

Non Patent Literature

SUMMARY

Technical Problem

The high-voltage N-ch MOS maintains the high breakdown voltage by full depletion of an N-type RESURF region. The high-voltage P-ch MOS maintains the high breakdown voltage by full depletion of a P-type diffusion layer on the surface in addition to the N-type RESURF region. Therefore, in both of the high-voltage N-ch MOS and high-voltage P-ch MOS, a transient leakage current flows during a period in which the depletion layer spreads within the high-voltage isolation region, from a time point when a high voltage is applied until full depletion is achieved. A prolonged period of this transient leakage current flow could induce a malfunction of the level shift circuit.

While a long field plate on the low side would accelerate depletion in the high-voltage N-ch MOS and shorten the period of transient leakage current flow, it would inhibit depletion of the P-type diffusion layer of the high-voltage P-ch MOS and prolong the period of transient leakage current flow. This can easily cause the high-voltage P-ch MOS of the level shift circuit to malfunction. On the other hand, a short field plate on the low side would cause the high-voltage N-ch MOS of the level shift circuit to malfunction easily. According to conventional techniques, the high-voltage N-ch MOS and high-voltage P-ch MOS have the same field plate structure, so that it was not possible to shorten the period of leakage current flow in both of the high-voltage N-ch MOS and high-voltage P-ch MOS.

The present invention was made to solve the problem described above and it is an object of the invention to provide a semiconductor device configured to shorten the period of transient leakage current that flows when high voltage is applied in both of a high-voltage N-ch MOS and a high-voltage P-ch MOS, to improve the malfunction tolerance of a level shift circuit.

Solution to Problem

A semiconductor device according to the present invention includes: a high-side circuit region; a low-side circuit region; and a RESURF isolation structure surrounding an outer periphery of the high-side circuit region to isolate the high-side circuit region and the low-side circuit region from each other, wherein the RESURF isolation structure includes a high-voltage isolation region, a high-voltage N-ch MOS, and a high-voltage P-ch MOS, the high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS include a thermal oxide film, and a plurality of field plates provided on the thermal oxide film, an inner end of the field plate of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than an inner end of the field plate of the high-voltage N-ch MOS located closest to the low-side circuit region.

Advantageous Effects of Invention

In the present invention, an inner end of the field plate of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than an inner end of the field plate of the high-voltage N-ch MOS located closest to the low-side circuit region. Thus, the period in which a transient leakage current flows when a high voltage is applied is shortened in both of the high-voltage N-ch MOS and high-voltage P-ch MOS, whereby the malfunction tolerance of the level shift circuit can be improved.

DESCRIPTION OF EMBODIMENTS

A semiconductor device according to the embodiments of the present invention will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.

FIG. 1is a diagram illustrating a semiconductor device according to Embodiment 1 of the present invention. This semiconductor device is an HVIC (High Voltage IC)3that drives power chips1and2in a half bridge configuration. The HVIC3includes a high-side circuit region4that drives the power chip1, a low-side circuit region5that drives the power chip2, and a level shift circuit6that transmits signals between the low-side circuit region5and the high-side circuit region4.

FIG. 2is a diagram illustrating a high-voltage N-ch MOS in the level shift circuit according to Embodiment 1 of the present invention. The signal transmission from the low-side circuit region5to the high-side circuit region4is performed by the high-voltage N-ch MOS7in the level shift circuit6.FIG. 3is a diagram illustrating a high-voltage P-ch MOS in the level shift circuit according to Embodiment 1 of the present invention. The signal transmission from the high-side circuit region4to the low-side circuit region5is performed by the high-voltage P-ch MOS8in the level shift circuit6.

FIG. 4is a plan view illustrating the high-side circuit region of the semiconductor device according to Embodiment 1 of the present invention. For the sake of simplicity, only part of the configuration is shown. A RESURF isolation structure surrounds the outer periphery of the high-side circuit region in plan view to isolate the high-side circuit region and the low-side circuit region from each other. The RESURF isolation structure includes a high-voltage isolation region, a high-voltage N-ch MOS, and a high-voltage P-ch MOS. Substrate potential is set as the reference voltage of the low-side circuit region, while the high-voltage isolation region isolates the high-side circuit region from the substrate potential to have a high breakdown voltage. The high-voltage N-ch MOS and high-voltage P-ch MOS have the same level of breakdown voltage as that of the high-voltage isolation region. A spiral polysilicon portion9surrounds the outer periphery of the high-side circuit region in the RESURF structure.

FIG. 5is a cross-sectional view of the high-voltage isolation region along I-II ofFIG. 4. A P-type epitaxial layer (not shown) is formed on a P-type substrate10, and an N-type diffusion layer11athat is the RESURF region is formed thereon. A P-type diffusion layer12that reaches the P-type substrate10surrounds the high-side circuit region and the N-type diffusion layer11a. A P-type diffusion layer13ais formed on the inner side of one end of the P-type diffusion layer12such as to partly overlap the P-type diffusion layer12. An N+-type buried diffusion layer14ais formed on the inner side of one end of the P-type diffusion layer13asuch as to be in contact with the lower face of the P-type epitaxial layer. An N+-type diffusion layer15ais formed on the surface of the N-type diffusion layer11aat a certain distance from the P-type diffusion layer12. A P+-type diffusion layer16ais formed on a surface portion of the P-type diffusion layer13a. A thermal oxide film17is formed on the upper face of the N-type diffusion layer11abetween the P-type diffusion layer12and the N+-type diffusion layer15a. Polysilicon portions18aand19aare formed at a certain distance from each other such as to cover an inner end portion and an outer end portion of the thermal oxide film17, respectively. An insulating film20is formed such as to cover the surfaces of these components.

Metal wiring layers21and22are formed on the insulating film20. The metal wiring layer21is electrically connected to the N+-type diffusion layer15aand the polysilicon portion18athrough a contact hole. The metal wiring layer22is electrically connected to the P+-type diffusion layer16aand the polysilicon portion19avia a contact hole that extends through the insulating film20.

The polysilicon portion9is formed inside the insulating film20. One end of the polysilicon portion9is electrically connected to the metal wiring layer22while the other end is electrically connected to the metal wiring layer21. The impurity concentration is higher in the order of the N+-type buried diffusion layer14a, the P-type diffusion layer12, the N-type diffusion layer11a, and the P-type substrate10. The N-type diffusion layer11asatisfies the RESURF conditions.

FIG. 6is a cross-sectional view of the high-voltage N-ch MOS along III-IV ofFIG. 4. An N-type diffusion layer11bof the high-voltage N-ch MOS is electrically isolated from the N-type diffusion layer11aof the high-voltage isolation region (the isolation structure is not shown; see, for example, PTL 2 and NPL 2). An N+-type buried diffusion layer14bis also electrically isolated from the N+-type buried diffusion layer14a. A P+-type diffusion layer23is formed on a surface portion of the P-type diffusion layer12. A P-type diffusion layer13bis formed on the surface of the N-type diffusion layer11bbetween the P-type diffusion layer12and the thermal oxide film17. An N+-type diffusion layer15bis formed on the surface of the N-type diffusion layer11bat a certain distance from the P-type diffusion layer12. A P+-type diffusion layer16band an N+-type diffusion layer24are formed on surface portions of the P-type diffusion layer13b.

Polysilicon portions18band19bare formed on the thermal oxide film17at a certain distance from each other such as to cover an inner end portion and an outer end portion of the thermal oxide film17, respectively. The polysilicon portion19bextends also over the P-type diffusion layer13bvia a gate oxide film. The polysilicon portion9is formed on the thermal oxide film17between the polysilicon portions18band19b.

Metal wiring layers25,26,27, and28are formed on the insulating film20. The metal wiring layer25is electrically connected to the N+-type diffusion layer15band the polysilicon portion18bthrough a contact hole. The metal wiring layer26is electrically connected to the polysilicon portion19bthrough a contact hole. The metal wiring layer27is electrically connected to the P+-type diffusion layer16band N+-type diffusion layer24through a contact hole. The metal wiring layer28is electrically connected to the P+-type diffusion layer23via a contact hole that extends through the insulating film20. The metal wiring layer28is also electrically connected to the metal wiring layer22.

FIG. 7is a cross-sectional view of the high-voltage P-ch MOS along V-VI ofFIG. 4. An N-type diffusion layer11cof the high-voltage P-ch MOS is electrically isolated from the N-type diffusion layer11aof the high-voltage isolation region. An N+-type buried diffusion layer14cis also electrically isolated from the N+-type buried diffusion layer14a. A P-type diffusion layer13cis formed on the surface of the N-type diffusion layer11cbetween the P-type diffusion layer12and the thermal oxide film17. A P+-type diffusion layer16cis formed on a surface portion of the P-type diffusion layer13c. A P-type diffusion layer29is formed on the surface of the N-type diffusion layer11csuch as to be in contact with the lower face of the thermal oxide film17. A P+-type diffusion layer30is formed on the surface of the N-type diffusion layer11cat a certain distance from the P-type diffusion layer29. An N+-type diffusion layer15cis formed on one side of the P-type diffusion layer30opposite from the P-type diffusion layer29.

Polysilicon portions18cand19care formed at a certain distance from each other such as to cover an inner end portion and an outer end portion of the thermal oxide film17, respectively. The polysilicon portion18cis formed on the N-type diffusion layer11cbetween the P-type diffusion layer29and the P-type diffusion layer30via a gate oxide film. Metal wiring layers31,32, and33are formed on the insulating film20. The metal wiring layer31is electrically connected to the P+-type diffusion layer30and N+-type diffusion layer15cthrough a contact hole. The metal wiring layer32is electrically connected to the polysilicon portion18cthrough a contact hole. The metal wiring layer33is electrically connected to the P+-type diffusion layer16cand the polysilicon portion19cvia a contact hole that extends through the insulating film20.

The length Ln of the polysilicon portion19bon the thermal oxide film17of the high-voltage N-ch MOS that is the field plate located closest to the low-side circuit region, the length Li of the polysilicon portion19aon the thermal oxide film17of the high-voltage isolation region, and the length Lp of the polysilicon portion19con the thermal oxide film17of the high-voltage P-ch MOS, satisfy the relationship expressed by Formula 1 below.
Ln=Li>Lp  (1)

Thus, the inner end of the polysilicon portion19cthat is the field plate of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than the inner end of the polysilicon portion19bthat is the field plate of the high-voltage N-ch MOS located closest to the low-side circuit region.

The plurality of polysilicon portions9in the high-voltage P-ch MOS are spaced apart at larger intervals than those of the plurality of polysilicon portions9in the high-voltage N-ch MOS and in the high-voltage isolation region. The intervals of the plurality of polysilicon portions9in the high-voltage P-ch MOS need not be constant.

Next, the advantageous effects of this embodiment will be explained in comparison to a comparative example.FIG. 8is a plan view illustrating a high-side circuit region of a semiconductor device according to the comparative example.FIG. 9is a cross-sectional view of a high-voltage isolation region along I-II ofFIG. 8.FIG. 10is a cross-sectional view of a high-voltage N-ch MOS along III-IV ofFIG. 8.FIG. 11is a cross-sectional view of a high-voltage P-ch MOS along V-VI ofFIG. 8. In the comparative example, the high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS all have the same field plate structure (Ln=Li=Lp).

The high-voltage N-ch MOS maintains the high breakdown voltage by full depletion of the N-type diffusion layer11b. The high-voltage P-ch MOS maintains the high breakdown voltage by full depletion of the P-type diffusion layer29on the surface in addition to the N-type diffusion layer11c. Therefore, in both of the high-voltage N-ch MOS and high-voltage P-ch MOS, a transient leakage current flows during a period in which the depletion layer spreads within the high-voltage isolation region, from a time point when a high voltage is applied, until full depletion is achieved. A prolonged period of this transient leakage current flow could induce a malfunction of the level shift circuit6.

FIG. 12andFIG. 13are cross-sectional views for explaining a depletion process of the high-voltage N-ch MOS according to the comparative example. Referring toFIG. 13, the polysilicon portion19bthat is the field plate located closest to the low-side circuit region is longer than that ofFIG. 12, this low-voltage polysilicon portion19bextending out more toward the high-side circuit region. Therefore, when a high voltage and a low voltage are applied to the metal wiring layer25, and the metal wiring layers26,27and28, respectively, the mobility of electrons34in the N-type diffusion layer11btoward the high side is increased. Depletion is thus accelerated, which shortens the period of transient leakage current flow.

FIG. 14andFIG. 15are cross-sectional views for explaining a depletion process of the high-voltage P-ch MOS according to the comparative example. Referring toFIG. 15, the polysilicon portion19cthat is the field plate located closest to the low-side circuit region is longer than that ofFIG. 14, this low-voltage polysilicon portion19cextending out more toward the high-side circuit region. Therefore, when a high voltage and a low voltage are applied to the metal wiring layers31and32, and the metal wiring layers28and33, respectively, the holes35in the P-type diffusion layer29are attracted below the polysilicon portion19c. Depletion of the P-type diffusion layer29is thus inhibited, which prolongs the period of transient leakage current flow.

In contrast, according to this embodiment, the polysilicon portion19bthat is the field plate located closest to the low-side circuit region in the high-voltage N-ch MOS is long and extends out toward the high-side circuit region, so that depletion of the N-type diffusion layer11bis accelerated. On the other hand, the polysilicon portion19cthat is the field plate located closest to the low-side circuit region in the high-voltage P-ch MOS is short and its inner end portion is located closer to the low-side circuit region than that of the high-voltage N-ch MOS, so that depletion of the P-type diffusion layer29is accelerated. Thus, the period in which a transient leakage current flows when a high voltage is applied is shortened in both of the high-voltage N-ch MOS and high-voltage P-ch MOS, whereby the malfunction tolerance of the level shift circuit6can be improved.

FIG. 16is a plan view illustrating a high-side circuit region of a semiconductor device according to Embodiment 2 of the present invention.FIG. 17is a cross-sectional view of a high-voltage isolation region along I-II ofFIG. 16.FIG. 18is a cross-sectional view of a high-voltage N-ch MOS along III-IV ofFIG. 16.FIG. 19is a cross-sectional view of a high-voltage P-ch MOS along V-VI ofFIG. 16.

In this embodiment, the plurality of polysilicon portions9in the high-voltage P-ch MOS and in the high-voltage isolation region are spaced apart at larger intervals than those of the plurality of polysilicon portions9in the high-voltage N-ch MOS. The length Ln of the polysilicon portion19bon the thermal oxide film17of the high-voltage N-ch MOS, the length Li of the polysilicon portion19aon the thermal oxide film17of the high-voltage isolation region, and the length Lp of the polysilicon portion19con the thermal oxide film17of the high-voltage P-ch MOS, satisfy the relationship expressed by Formula 2 below.
Ln>Li=Lp  (2)

In the configuration of this embodiment, too, the inner end of the polysilicon portion19cthat is the field plate of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than the inner end of the polysilicon portion19bthat is the field plate of the high-voltage N-ch MOS located closest to the low-side circuit region. Thus, the same effects as those of Embodiment 1 can be achieved.

FIG. 20is a plan view illustrating a high-side circuit region of a semiconductor device according to Embodiment 3 of the present invention.FIG. 21is a cross-sectional view of a high-voltage isolation region along I-II ofFIG. 20.FIG. 22is a cross-sectional view of a high-voltage N-ch MOS along III-IV ofFIG. 20.FIG. 23is a cross-sectional view of a high-voltage P-ch MOS along V-VI ofFIG. 20.

In this embodiment, intervals of parts of the spiral polysilicon portion9are same in the high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS. The plurality of polysilicon portions9in the high-voltage P-ch MOS are positioned closer to the low-side circuit region than the plurality of polysilicon portions9in the high-voltage N-ch MOS.

In the configuration of this embodiment, too, the inner end of the polysilicon portion19cthat is the field plate of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than the inner end of the polysilicon portion19bthat is the field plate of the high-voltage N-ch MOS located closest to the low-side circuit region. Thus, the same effects as those of Embodiment 1 can be achieved. Moreover, since there is no need to increase the intervals between the plurality of polysilicon portions9of the high-voltage P-ch MOS, deterioration of the stability of breakdown voltage can be minimized.

FIG. 24is a plan view illustrating a high-side circuit region of a semiconductor device according to Embodiment 4 of the present invention.FIG. 25is a cross-sectional view of a high-voltage isolation region along I-II ofFIG. 24.FIG. 26is a cross-sectional view of a high-voltage N-ch MOS along III-IV ofFIG. 24.FIG. 27is a cross-sectional view of a high-voltage P-ch MOS along V-VI ofFIG. 24.

In this embodiment, similarly to Embodiment 1, the polysilicon portion19cthat is the field plate located closest to the low-side circuit region in the high-voltage P-ch MOS is shorter than the polysilicon portion19bthat is the field plate located closest to the low-side circuit region in the high-voltage N-ch MOS. The polysilicon portion19con the thermal oxide film17of the high-voltage P-ch MOS is shifted parallelly toward the polysilicon portion18cso that the distance between them equals to the distance between the polysilicon portions18aand19a, and the distance between the polysilicon portions18band19b. Namely, the distance between the field plate closest to the low-side circuit region and the field plate closest to the high-side circuit region is the same in all of the high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS. The P-type diffusion layer12, the P+-type diffusion layer23, the P+-type diffusion layer16c, the P-type diffusion layer13c, and the metal wiring layer33are also shifted parallelly toward the polysilicon portion18cby the same length as the polysilicon portion19c. The length of the P-type diffusion layer29and the thermal oxide film17is reduced by the length of movement of the polysilicon portion19c.

Thus, the period in which a transient leakage current flows when a high voltage is applied is shortened in both of the high-voltage N-ch MOS and high-voltage P-ch MOS, whereby the malfunction tolerance of the level shift circuit6can be improved.

Moreover, since the distance between the field plate closest to the low-side circuit region and the field plate closest to the high-side circuit region is the same in all of the high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS, the spiral polysilicon portion9can be placed as it is at the same position. Thus the spiral polysilicon portion9can be formed by only straight lines and circular arc patterns so that the layout design is made easy. Also, the space for the low-side region of the high-voltage P-ch MOS can be saved.

FIG. 28is a plan view illustrating a high-side circuit region of a semiconductor device according to Embodiment 5 of the present invention.FIG. 29is a cross-sectional view of a high-voltage isolation region along I-II ofFIG. 28.FIG. 30is a cross-sectional view of a high-voltage N-ch MOS along III-IV ofFIG. 28.FIG. 31is a cross-sectional view of a high-voltage P-ch MOS along V-VI ofFIG. 28.

In this embodiment, a polysilicon portion36and a metal wiring layer37that are capacitively-coupled to each other are formed on a thermal oxide film17instead of the spiral polysilicon portion9of Embodiment 1. In this case, too, the same effects as those of Embodiment 1 can be achieved.

The polysilicon portion36is made of the same layer as the polysilicon portions18a,18b,18c,19a,19b, and19c, while the metal wiring layer37is made of the same layer as the metal wiring layers21,22,25,26,27,28,31,32, and33, so that they can be respectively formed simultaneously. Therefore, as compared to Embodiment 1, the step of forming the polysilicon portion9can be omitted.

The P-type substrate10and the semiconductor layer thereon are not limited to ones formed of silicon, but instead may be formed of a wide-bandgap semiconductor having a bandgap wider than that of silicon. The wide-bandgap semiconductor is, for example, a silicon carbide, a gallium-nitride-based material, or diamond. A power semiconductor device formed of such a wide-bandgap semiconductor has a high voltage resistance and a high allowable current density, and thus can be miniaturized. The use of such a miniaturized semiconductor device enables the miniaturization and high integration of the semiconductor module in which the semiconductor device is incorporated. Further, since the semiconductor device has a high heat resistance, a radiation fin of a heatsink can be miniaturized and a water-cooled part can be air-cooled, which leads to further miniaturization of the semiconductor module. Further, since the semiconductor device has a low power loss and a high efficiency, a highly efficient semiconductor module can be achieved.

REFERENCE SIGNS LIST