Method and system to compensate for scanner system timing variability in a semiconductor wafer fabrication system

A semiconductor wafer fabrication system that includes at least a track system and a scanner system compensates for deviations from nominal periodicity in the scanner system by dynamically introducing time delays when such deviations are detected. Preferably prior art static wait states are also introduced into the wafer recipe to reduce probability of resource conflicts. The resultant semiconductor wafer fabrication system can enjoy enhanced wafer throughput in that synchronization of wafer flow is maintained, despite such deviations.

FIELD OF THE INVENTION

The invention relates generally to semiconductor wafer fabrication systems that comprise a track system and a scanner system, and more specifically to compensating such wafer fabrication systems for deviations from nominal timing in the scanner system.

BACKGROUND OF THE INVENTION

Modern integrated circuits (ICs) are fabricated on semiconductor wafers that are mass produced in fabrication sites. The fabrications sites (or “fabs”) employ various types of automatic equipment that must function to very exacting and carefully controlled operating parameters.FIG. 1depicts some of the process steps or modules found in a generic fab system10. System10may be thought of as a track system20that comprises a variety of production modules, and a scanner (or stepper) system30. Track system20typically operates synchronously under control of a computer system40that, among other tasks, outputs a track system clock signal (TRACK CLOCK). By synchronously it is meant that wafers are moved in the track system20responsive to the track clock signal.

The wafers under production are made available for input to the scanner system30responsive to the track clock signal. However scanner system30receives the wafers and outputs scanner system-completed wafers responsive to its internal scanner system clock (SCANNER CLOCK). Understandably much attention is given in the prior art to trying to synchronize the track clock and the scanner clock to reduce dead-time in moving and processing wafers through the overall fabrication system. But to achieve good synchronization between the track clock and the scanner clock, the timing in the scanner system must exhibit a substantially consistent periodicity. But in practice, exposure procedures within the scanner system can exhibit,a timing deviation from nominal periodicity, which deviation or variability hampers clock synchronization.

Exemplary modules within track system20are shown inFIG. 1. At the upper left region ofFIG. 1, a sequence of wafers are input to system20. A chill plate module50typically is used to stabilize the wafer temperature by about 1° C. to room temperature before the wafers enter a spin coater60where a film of polymer photoresist is placed on the upper surface of the wafer. In some processes, at step60an anti-reflection coating may first be deposited upon the upper wafer surface and the wafer then baked (e.g., module or step70) and then returned to the spin coater60for deposition of photo resist. As modern photolithography seeks to define smaller and smaller feature size using shorter wavelength light, ultraviolet reflectivity becomes a greater problem, and thus the use of anti-reflection layer(s).

Eventually the wafer is passed by a robotic unit140to a bake plate70where the film of photoresist is hardened and excess solvents are driven out of the wafer with heat. A subsequent chill plate process80cools the wafers to a stabilized room temperature. Upon receipt of a track clock signal issued by computer system40, the wafer under process is then sent out of the thus-described portion of track system20and is available for input to the stepper/scanner system30. Stepper/scanner system30will accept the wafer in question responsive to a signal from the scanner clock. Within system30various lithographic techniques may be carried out upon the wafer in question. At module or step90, the wafer is subjected to a post-exposure bake (PEB), using a PEB bake plate, and then to a chill plate100, that returns the wafer to a stabilized ambient room temperature. A developer module stage110typically follows, during which the latent lithographic image that was formed within the stepper/scanner module30is developed in the polymer film on the wafer upper surface. In a positive tone image, the portions of the photoresist exposed to light will become soluble and dissolve away in solution to expose desired regions of the wafer structure. A bake plate step120follows to dry and harden the wafer surface. An etcher module130then follows, and the thus-processed wafer is returned to a chill plate, e.g., module50. Several of the steps or stages shown inFIG. 1may be repeated for the same wafer dozens of time, depending upon the specifics of the processes involved (e.g., the “recipe”. Typically devices shown generically as robotic arms140may be used to mechanically move wafers from one module to another.

In practice the rate at which track system20can send wafers for input to stepper/scanner system30may not coincide with the rate at which stepper/scanner system30is ready to receive (“R2R”) new wafers. Similarly, the time when scanner system30is ready to send (“R2S”) wafers back into track system20may not coincide with the moment at which track system20is ready to receive wafers for further processing. In some prior art systems10, buffers such as150may be included to add time to processing of wafers within system20. One or more buffers or buffer functions may be used in system10to absorb what would otherwise be disturbances to the time flow of wafers. A buffer may be a physical entity, for example a module used as a temporary storage site to hold excess wafers longer than needed for processing at that station, perhaps a dedicated buffer station, or a robotic arm temporarily used as a storage site for wafers.

By way of example, assume that responsive to timing of the track clock signal chill plate80is ready to send wafers into the stepper/scanner system30sooner than the stepper/scanner clock allows system30to be ready. When it is known that stepper/scanner system30is ready to receive wafers, the robotic arm140can load wafers into system30, taking them if necessary from a buffer150.

Understandably having to provide extra robotic arms and/or buffers to try to improve the output timing of track system20is not an optimum solution to the problem of enabling a better timing match between system20and system30. There can be time conflicts within system10between modules competing for access to a given module, and it can be necessary to try to force time matching between wafers sent out of system20, and wafers received into system30, and then wafers exiting system30back into track system20. But providing buffers150and/or additional robotic type mechanisms140to try to smooth out system flow requires additional cost and additional floor space within the fab, and will actually reduce wafer throughput.

One prior art solution to helping resolve resource conflicts within track system20is described in U.S. Pat. No. 6,418,356 (July 2002) to H. Oh, inventor herein. In the '356 patent, conflicts for transportation resources (e.g., robotic mechanism) are resolved by selectively adding “wait” time to modules that can tolerate such wait states without substantially degrading on-wafer production results associated with track system20. Applicant incorporates herein by reference U.S. Pat. No. 6,418,356.

But even if track system resource conflicts can be resolved, deviations from nominal timing in the associated scanner system can degrade overall fabrication system performance. What is needed is a method of compensating for such scanner system timing deviations such that the timing match between the ready to send (R2S) state of the track system and the ready to receive (R2R) state of the stepper/scanner lithographic system is maintained.

The present invention provides such compensation for time deviations in a scanner system.

SUMMARY OF THE PRESENT INVENTION

The present invention operates a semiconductor wafer fabrication system that includes a track system and a scanner system such that deviations from anticipated nominal timing in the scanner system are compensated for. Such time deviations typically arise from variations in scanner system exposure times. The present invention detects such scanner system time deviations and dynamically inserts additional time “delays” into the wafer production system to help compensate therefor, and to thus preserve good synchronization of wafer flow across the track system to scanner system interface.

These dynamically inserted delays are in addition to pre-planned “waits” that are added into the wafer production recipe at non-critical module phases of the process, as disclosed in U.S. Pat. No. 6,418,356. The resultant semiconductor wafer fabrication system can maintain a synchronized wafer flow, and thus achieve improved throughput. Other features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail, in conjunction with their accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 2is a block diagram of a semiconductor wafer production system200that includes a track system20′ and a scanner system30′. Systems20′ and30′ may be the same as systems20and30inFIG. 1, or may include different and/or different numbers of modules and more or less robotic units.

It may be assumed that system200has track system20′ compensation in the form of inserted “wait” times as described in U.S. Pat. No. 6,418,356. However in contrast to what is described in the '356 patent, track system20′ advantageously also has compensation against deviations from nominal scanner system timing, which is to say, deviations from nominal scanner system clock periodicity. Such compensation is in the form of inserted time “delays”.

System200preferably operates under control of computer system210whose computer readable memory stores (or can be loaded with) software220that when executed by the computer CPU implements the above system operation. Computer system210can readily compare actual scanner system30′ clock timing against a nominal clock timing to detect deviations in periodicity from nominal. When such timing deviations are detected, software210upon CPU execution causes the insertion into track system20′ of appropriate time “delays” (as contrasted with the insertion of '356 patent pre-planned “waits”, which are introduced into the wafer production recipe even before system200is turned-on). As described herein, such inserted “delays” improve the match between timing of wafers sent by track system20′ and timing of wafers received by scanner system30′, e.g., wafers sent from chill plate80into scanner system30′, as well as wafers sent from scanner system30′ into post-exposure bake module90in track system20′, in exemplaryFIG. 2.

Track system20′ is shown with four robotic stations: LRP-230(or “LPR”) is a load port robotic unit associated with loading wafers into/out of system200, CTR-230(or “CTR”) is a robotic unit associated with coater module60, SIR-230(or “SIR”) is a robot associated loading wafers into and out of scanner system30′, and DVR-230(or “DVR”), a robot associated generally with developer module110. All four robotic units LRP, CTR, SIR, and DVR preferably have two arms, such as robotic units developed by assignee ASML, Inc. While system200will be described with reference to these four robotic stations, it is understood that the present invention may be practiced with wafer production systems employing fewer or more than four track system robotic stations, or with systems not employing any dual-armed robotic stations.

Table 1 below will now be described with reference to the present invention. In Table 1, rows 11–15 (shown with shading) denote process steps associated with scanner system30′; the remaining process steps are associated with track system20′. Nominally a period of 40.0 seconds is assumed for the wafer recipe given in Table 1, e.g., in the nominal case a new wafer enters the system for processing every 40 seconds.

Referring to Table 1, the first column denotes process steps, and the fifth column denotes the process and overhead (OH) time corresponding to the process step. By way of example, in a chill plate operation (e.g., CP1x), the overhead time refers to the time necessary to open and close the chill plate chamber module, whereas the process time represents the actual duration of a timed-chill within the closed chill plate chamber.

Thus in Table 1, the first column represents modules for the process steps, where LPx denotes load port, CP1x, CP2x, CP3x denote chill plates (e.g., perhaps chill plates50,80,100inFIG. 2), BARCx denotes bottom anti-reflection coating module (e.g., a step carried out by spin coater module60), HP1x, HP2x, HP3x, HP4x denote hot or bake plates (e.g., bake plates70,90,120inFIG. 2), CTx denotes a coater module (e.g., module60inFIG. 2), OEBRX denotes removal of the bead formed on the outer edge of a wafer. IN-PED and OUT-PED denote input and output pedestals within scanner system30′, ALIGN denotes wafer alignment within scanner system30′, EXPOSE refers to wafer exposure within scanner system30, and DISCHARGE refers to a discharge chute within scanner system30′. The five rows of data in Table 1 relating to scanner system30′ are shown with background shading and dark borders; the remaining rows of data represent steps in track system20′.

Columns two and three in Table 1 denote robot assignments in the exemplary embodiment to be described and robotic movements. LPR denotes load port robot (e.g., LPR-230inFIG. 2), CTR denotes coater robot (e.g., CTR-230inFIG. 2), SIR denotes a stepper interface robot (e.g., SIR-230inFIG. 2), WHR and DIR denote a wafer handling robots associated with scanner system30′ (e.g., WHR-240, DHR-240inFIG. 2). In a so-called single movement, a generic robot that must move a wafer from a first process module to a following second process module must first remove the wafer already in the second process module before relocating the first wafer to the second process module. In a swap movement, a two-armed robotic mechanism is used in which the first robot arm can pick up a first wafer from a first module, and a second wafer from a second module, and then use the first arm to position the first wafer in the second module. Where feasible, swap movements are preferred to single movements.

For example, looking left-to-right at row1in Table 1, in a load port process step, a wafer is picked-up by an LPR robotic mechanism (e.g., LPR-230) from the load port LPx and is placed at a following process module, chill plate CP1x (perhaps module50inFIG. 2). Transport time associated with picking-up and placing as shown in column4is 7.0 seconds. At row2, a chill plate process step occurs for which the sum of process and overhead time is 24.0 seconds.

In the last column of row2, a 20 second pre-planned wait time is added to the wafer process and overhead time, as described in U.S. Pat. No. 6,418,356.

The pre-planned wait times shown in the last column of Table 1 are determined and added to the wafer recipe process times before wafer production system200is even turned on. These are times added to non-critical module stages as described in the '356 patent to help resolve resource conflicts within track system20′. These prior art “waits” are to be distinguished from “delays” that are added, as needed, during actual operation of wafer production system200to compensate for deviations from nominal periodicity within scanner system30′, according to the present invention.

After the expiration of the process, overhead and preplanned wait time at process module XP1x, a robotic mechanism CTR-230takes 7.0 seconds to transport the wafer to the next process step, namely BARCx in row3of Table 1.

In row3, a process and overhead time of 44.0 second is used for removal of the bead from the wafer circumferences, with a pre-planned wait of 33.5 seconds appended, according to the '356 patent. It is seen that a wafer swap robotic movement occurs in which 5.5 second transport time is used to move the wafer to the next process step, namely baking the wafer at hot plate HP1x in row4of Table 1.

Jumping down to shaded-rows11–15, which involve process steps and robotic movements inside scanner system30′, an IN-PED step involves robotic mechanism SIR-230placing a wafer on an input pedestal (IN-PED), the wafer having thus entered scanner system30′. As indicated in Table 1, a wafer-handling robot (e.g, WHR-240) is then used to transport the wafer to the aligner stage (ALIGN), see exemplary system200shown inFIG. 2, and Table 1, row12. Transport time is 12.5 seconds with 1.0 second process plus overhead time. Zero planned wait is required. At row12in Table 1, the wafer now undergoes an alignment step that involves 19.30 seconds process plus overhead time, with 25.0 seconds pre-planned. The alignment takes place at a stage that is part of the DIR-240robotic mechanism.

At the expiration of the alignment, overhead, and pre-planned wait time, the wafer in question now undergoes an exposure step that involves simply rotating the DIR-240robot. Movement is such that one arm of the DIR-240robotic unit holding an aligned wafer is rotated or moved into position to expose that wafer, while the other arm is free to move another wafer into the pre-alignment step. Table 1 indicates that the rotation takes 6.5 seconds transport time, while 33.5 seconds are exposure plus overhead time, and zero seconds wait.

In the next row of Table 1, the WHR-240robotic mechanism discharges the wafer from the exposure stage within scanner system30′ in 12.4 seconds with 1.0 seconds process and overhead time, and zero seconds wait. In row15of Table 1 (the last row directed to scanner system30′ per se) the SIR-230robotic mechanism picks the wafer in question from the out pedestal (OUT-PED) associated with scanner system30′. This maneuver takes nominally 9.5 seconds transport time with 1.0 seconds process and overhead time, with zero seconds wait. The wafer has now completed processing within scanner system30′ and re-enters track system20′ as indicated in exemplaryFIG. 2, for example beginning with a post-exposure bake step90(denoted as HP-3x in row16of Table 1).

Referring to Table 1, row16, the wafer at hot plate HP3x undergoes 94.0 seconds of process plus overhead time in baking. DVR robotic mechanism230then picks and transports the wafer to chill plate CP3x in 7 seconds. The wafer then undergoes a chill plate process step, perhaps chill plate100inFIG. 2, denoted CP3x in Table 1. After 64.0 seconds of chill time plus overhead time, robotic mechanism DVR-230requires 5.5 seconds to transport the wafer to the developer module (see Table 1, row18).

As shown inFIG. 2, typically the wafer next undergoes a developer step110, denoted DEVx in Table 1, involving an 89.0 second process plus overhead time. In Table 1 the following step is another chill plate (CP4x), perhaps chill plate50inFIG. 2, after which the wafer exits track system20′ via a load port (denoted LPx in Table 1). It is understood thatFIG. 2and Table 1 are exemplary and indeed every step shown inFIG. 2may not be reflected in Table 1.

FIG. 3comprisesFIG. 3AandFIG. 3B, the latter being a continuation ofFIG. 3A.FIGS. 3A and 3Bgraphically depict twenty-five wafers, denoted in the vertical axis as wafer number1, . . .25, as the wafers undergo processing in system200as a function of elapsed time, shown on the horizontal axis. To reiterate, in the system described in U.S. Pat. No. 6,418,356, incorporated hereby by reference, various “wait” times were added to non-critical processes to avoid conflicts by different wafers for a common system resource, these waits being denoted as “planned waits” in the last column of Table 1. InFIGS. 3A and 3B, such waits are shown as white bars, and are calculated for system200′ inFIG. 2per the '356 patent. The legend of symbols on the right-hand portion ofFIGS. 3A and 3Bidentifies what the various rectangular and square-like symbols inFIGS. 3A and 3Bdenote. Further, various exemplary regions ofFIGS. 3A and 3Bare explicitly called out with identifying indicia at the top portions ofFIGS. 3A and 3B.

FIG. 4, comprisingFIGS. 4A–4F, is a spreadsheet showing the fabrication recipe for the twenty-five wafers in question.FIGS. 3A and 3Bgraphically depict the data calculated and enumerated in detail inFIGS. 4A–4F. As described herein, the various “wait” times shown inFIGS. 4A–4Fand depicted inFIGS. 3A and 3Bas white rectangles are wait times as described in the '356 patent, and are planned “waits” that are added to non-critical module stages to reduce problems associated with resource conflicts. By contrast, the various inserted “delay” times shown inFIGS. 4A–4Fand depicted as black rectangles inFIGS. 3A and 3Bare time “delays” inserted according to the present invention to compensate for deviations from nominal timing (e.g., variability in scanner clock periodicity) in scanner system30′. These delays are added into system200, depicted inFIG. 2.

InFIG. 4A, column1denotes wafer number (data for 25 wafers being shown in the column), and column2represents deviations (in seconds) from nominal 40.0 second timing or periodicity for scanner system30′, in the example being described. It is these scanner system30′ deviations that are compensated for with inserted “delays”, according to the present invention. The insertion of such “delays” advantageously helps to promote a better timing match between when track system20′ is ready to send a wafer into scanner system30′, and when scanner system30′ is ready to receive such a wafer, as well as when scanner system30′ is ready to provide a wafer for further processing back into track system20′, and when track system20′ is ready to receive such wafer for further processing.

The interplay between Table 1,FIGS. 4A–4F, andFIGS. 3A and 3Bwill now be described. Let us arbitrarily begin with wafer4, which is the fourth wafer from the bottom inFIG. 3A. From the legend on the right portion ofFIG. 3Awe see that wafer4is completing its 49.0 second time in the CTx (coater module), some of the 49.0 seconds being to the left ofFIG. 3A, e.g., not shown. The associated data appears inFIG. 4B, fourth row from top (e.g., data for wafer4), column26, CTx. Immediately after the CTX station, there is a 28.5 wait time, shown inFIG. 3Aas a white bar commencing at about time 640 seconds, and denoted wait6inFIG. 4C, column27, fourth row. Note inFIG. 4C, no insertion delay (as opposed to a “wait”) is required, according to the present invention. Still looking at wafer4inFIG. 3A, after 28.5 seconds of wait time has expired (at approximately 670 seconds along the time axis), the CTR-230robot moves the wafer over a 5.5 second transport time (see Table 1; seeFIG. 4C, row4, column29).

At about time 690 seconds wafer4is positioned on a hot plate HP2x for 94.0 seconds (see Table 1 andFIG. 4C, row4, column30). The end of the 94.0 second hot plate duration is approximately time 765 for wafer4inFIG. 3A. No additional wait, as disclosed in the '356 patent is required, as indicated byFIG. 4C, row4, column31, e.g., wait7is zero seconds.

Next as shown by the small rectangle inFIG. 3Athat follows the relatively long hot plate rectangle symbol, the SIR-230robotic unit takes wafer4for 7.0 seconds, reflecting data inFIG. 4C, at row4, column32. At about time 770 seconds, wafer4begins 64.0 seconds on cold plate CP2x (see Table 1, andFIG. 4C, row4, column33), as indicated by the rectangular bar inFIG. 3Athat extends from about time 770 to about time 834. As shown by the white bar inFIG. 3Athat follows, an intentional wait of 13.5 seconds is inserted (wait8inFIG. 4C, row4, column34), again as determined preferably following the disclosure in the '356 patent.FIG. 4C, row4, column35shows that no delay per the present invention is required, e.g., delay8is zero. Next, as shown by the small rectangle beginning at about time 895 seconds, the wafer is moved by the SIR-230robotic unit for about 5.5 seconds. The corresponding data appears inFIG. 4C, row4, column36, as well as Table 1.

As shown inFIG. 4C, row4, column37, no “delay” is inserted at this time, e.g., delay9–10is zero seconds. At about time 860 an OEBRx process step is carried out for 34.0 seconds, perFIG. 4C, row4, column38. InFIG. 3A, as shown by the small white rectangle, a wait of 5.0 seconds (wait9inFIG. 4C, row4, column39) follows. Immediately following is an inserted “delay” of 1.54 seconds, according to the present invention, denoted delay11inFIG. 4D, row4, column40. This delay is inserted at about time 895 inFIG. 3A. Next follows a robotic movement of wafer4with SIR240that occupies 8.0 seconds (see Table 1, andFIG. 4D, row4, column41). The end of this 8.0 second movement occurs at approximately time 905 seconds inFIG. 3A.

Thus just after about time 960 inFIG. 3Aan intentional delay (delay12inFIG. 4D, row4, column47) of 1.86 seconds is added, according to the present invention. This delay is depicted as a narrow black rectangle inFIG. 3A. Next wafer4is moved by robotic unit DIR-240over a 6.5 second transport time (see Table 1 andFIG. 4D, row4, column48). At about time 970 there is a delay of 2.98 seconds (FIG. 4D, row4, column40). This is the delay in start-up of the exposure step, and it is this deviation or delay in nominal exposure starting time that the present invention compensates for (among other deviations). InFIG. 3A, exposure does not start until about time 975 seconds, and lasts for 33.5 seconds (see EXPOSE,FIG. 4D, row4, column50), exposure shown as a solid rectangle that extends to about time 1008 seconds. No wait state is permitted after exposure (wait12is zero seconds inFIG. 4D, row4, column51).

Over a transport time of 6.5 seconds (see Table 1 andFIG. 4D, row4, column52), robotic unit DIR-240moves wafer4to the discharge station (DISCHRG inFIG. 4E, row4, column53) for 1.0 second. No wait state is inserted (e.g., wait13is zero seconds perFIG. 4E, row4, column54). At about time 1015, robotic unit WHR-240moves wafer4over a 12.4 second transport time (Table 1 andFIG. 4E, row4, column55) to the OUT-PED station in scanner system30′. PerFIG. 4E, row4, column56, wafer4spends 1.0 seconds at this station, and is then moved by robotic unit SIR-230with its 9.5 second transport time to hot plate HP3x, e.g., post-exposure bake module90inFIG. 2. Note fromFIG. 4E, row4, columns57and58, that no wait time and no delay time is inserted (e.g., wait14is zero seconds, and delay17is zero seconds). The 9.5 second SIR-240transport time is reflected in Table 1, andFIG. 4E, row4, column59.

As shown graphically inFIG. 3Aby the hatched rectangle spanning from just before time 1040 through about time 1130, wafer4next remains on hot plate HP3x for 94.0 seconds (see Table 1 andFIG. 4E, row4, column60). No wait state is permitted after the post-exposure bake (e.g.,FIG. 4E, row4, column61shows wait15is zero seconds). Wafer4is immediately picked up by robotic unit DVR-230and transported (with a 7 second transport time) to chill plate CP3x, e.g., module100inFIG. 2, for 64 seconds (see Table 1 andFIG. 4E, row4, column63). This 64 second wafer4cooling step commences inFIG. 3Aat about time 1140 and extends offFIG. 3Ato be terminated at the left edge ofFIG. 3B, just after time 1200 seconds.

The white rectangle inFIG. 3Bextending to about time 1215 seconds represents an inserted wait of 13.5 seconds (wait16,FIG. 4E, row4, column64). Next follows an inserted delay of 5.03 seconds, according to the present invention, denoted delay19inFIG. 4E, row4, column65, and depicted as a dark rectangle inFIG. 3B, ending at about time 1220.

This lengthy development process is shown inFIG. 3Bas the long rectangle extending from about time 1220 to about time 1319 seconds. Looking atFIG. 4F, row4, columns68and69, wafer4is subjected to a 30.0 second wait (wait17) and a 6.77 inserted delay (delay20) before being transported by robotic unit DVR-230. After the robotic transport time of 5.5 seconds (see Table 1 andFIG. 4F, row4, column70), wafer4is presented to a chill plate, e.g., module50(or equivalent) inFIG. 2, for 5.0 seconds (Table 1 andFIG. 4F, row4, column71). Again it is noted thatFIG. 2is generic and not every module depicted is necessarily reflected in the wafer recipe being described.

Wafer4is nearing the completion of processing. PerFIG. 4F, row4, columns72and73, wafer4undergoes a 31.0 second wait (wait18), followed by a 2.45 second inserted delay (delay21). InFIG. 4B, delay21terminates shortly before time 1400 seconds. Wafer4is then transported by robotic unit LPR-230(with 7 second transport time) to load port LPx of track system20′. Wafer4is then pushed out of track system20′ slightly after time 1400 inFIG. 3B.

If we examine the other wafers shown inFIGS. 3A and 3B, it is seen that at approximately every 40.0 seconds one of the twenty-five wafers to be processed enters the system flow. As noted in column2inFIG. 4A, scanner time deviation from a nominal 40.0 second scanner clock period can vary from a nominal about 0 seconds to about 4.14 seconds. When computer system210detects such deviations from nominal scanner system time, an appropriate time delay is inserted into the system flow, as exemplified byFIGS. 4A–4F.

It is the combination of pre-planned “wait states”, as disclosed in the '356 patent, plus dynamically inserted “delays”, according to the present invention, that promotes the desired synchronous wafer flow throughout scanner system30′ and track system20′, notwithstanding deviations in clock periodicity within scanner system30′. For example, at about time 1217 seconds, dynamically inserting delays to the movement of wafers1and4(FIG. 4F, row1, column69andFIG. 4E, row4, column65) enables robotic unit DVR-230to execute pick and placement of wafers1,4, and7in one continuous single-swap-swap motion.

But for the insertion of these delays, according to the present invention, conflicts in the requests for pick and place by wafers1,4, and7would exist. Such conflicts would lead to the loss of synchronization of wafer flow across track system20′ and scanner system30′. ExaminingFIGS. 3A and 3Bvertically along various time instances, it is seen that resource conflicts are avoided as a result of the inserted wait states and time delays, notwithstanding perturbation in scanner periodicity. Determination of delay times, according to the present invention, may be carried out by software220using analytical techniques such as those disclosed in U.S. Pat. No. 6,418,356.

Although the exemplary system described assumed a 40 second period, which is to say a production of 90 wafers per minute, it will be appreciated that a faster throughput can also be implemented, for example at least 130 wafers per minute, and preferably 160 wafers per minute.

Modifications and variations may be made to the disclosed embodiments without departing from the subject and spirit of the invention as defined by the following claims.