Silicon carbide power device with improved robustness and corresponding manufacturing process

An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

BACKGROUND

Technical Field

The present disclosure relates to a silicon carbide (SiC) power device having an improved robustness, in particular in regard to thermomechanical stresses due to thermal cycles; the present disclosure moreover relates to a process for manufacturing the power device.

Description of the Related Art

Integrated electronic devices are known, for example diodes or MOSFETs (Metal-Oxide Semiconductor Field-Effect Transistors) for power-electronic applications, made starting from a silicon carbide substrate.

Such devices are advantageous thanks, at least in part, to the favorable chemico-physical properties of silicon carbide. For instance, silicon carbide generally has a bandgap wider than that of silicon, that is the material commonly used in electronic power devices. Consequently, even with relatively small thicknesses, silicon carbide has a breakdown voltage higher than silicon and can therefore be advantageously used in high-voltage, high-power, and high-temperature applications.

Manufacturing of advanced silicon carbide power devices is, however, affected by some problems due to the dielectric properties of passivation layers used with insulating functions.

On account of the high operating temperature and dielectric rigidity, a polyimide layer (i.e., a polymer of imide monomers) is typically used as passivation and insulation material in current silicon carbide power devices, being for example formed via deposition using spin-coating techniques. Problems of adhesion of this passivation layer to the underlying silicon carbide substrate (or to some other layer of material), in particular after thermal cycles (both during operations of electrical testing and during the effective operating life) currently limit reliability of such power devices.

In particular, due to possible delamination of the passivation layer, caused by thermomechanical stresses after the aforesaid thermal cycles, so-called electrical arching phenomena may occur in reverse biasing, between metal-material regions of the power device, with consequent damage or breakdown of the same power device.

BRIEF SUMMARY

In various embodiments, the present disclosure provides an improved solution for a silicon carbide power device, allowing to overcome the disadvantages highlighted previously associated to known solutions and in particular providing a higher robustness in regard to thermomechanical stresses due to thermal cycles.

According to the present disclosure, a silicon carbide power device and a corresponding manufacturing process are therefore provided.

In one or more embodiments, an electronic power device is provided that includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis transverse to the horizontal plane. The substrate includes an active area, and a non-active edge area surrounding the active area, and a plurality of doped regions extending from the front surface into the substrate in the active area. A dielectric region is disposed over the front surface in at least the edge area. A passivation layer is disposed over the front surface of the substrate, and the passivation layer is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through a thickness of the dielectric region at the edge area and is configured to define a mechanical anchorage for the passivation layer.

In one or more embodiments, a process for manufacturing an electronic power device is provided that includes: forming a dielectric region on a front surface of a substrate of silicon carbide (SiC), at an edge area of the substrate, the substrate having the front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis transverse to said horizontal plane, said substrate including an active area and the edge area, which is not active, a plurality of doped regions extending from the front surface into the substrate in the active area; and forming a passivation layer over the front surface of said substrate, and in contact with said dielectric region in said edge area. The forming the passivation layer includes forming an anchorage region that extends through a thickness of said dielectric region at said edge area and is configured to define a mechanical anchorage for said passivation layer.

DETAILED DESCRIPTION

With initial reference toFIG. 1A, a first embodiment of a process for manufacturing a silicon carbide power device is now disclosed.

The above manufacturing process envisages providing a wafer1comprising a silicon carbide substrate2, having a front surface2aand a rear surface2b, which extend in a horizontal plane xy and are separate from and opposite to one another along a vertical axis z, transverse to the horizontal plane xy.

In the embodiment illustrated, where the power device is, by way of example, a power diode, a rear cathode contact is formed on the rear surface2bof the substrate, constituted by a layer of conductive material3, for example metal material.

Moreover, a plurality of anode wells4, constituted by appropriately doped regions, are formed at the front surface2aof the substrate2, in an active area A′ of the power device. In a known manner, each of the aforesaid anode wells4, which can have a strip-like conformation (in top view, in the horizontal plane xy), represents a cell of the power device.

At the front surface2aof the substrate2, in an edge area A″ of the power device (distinct and separate from the active area A′), an edge anode region5is moreover formed, which is also constituted by an appropriately doped region, having a side extension greater than that of the aforesaid anode wells4(inFIG. 1A, along a first axis x of the aforesaid horizontal plane xy).

In a known manner, the edge area A″ terminates at a scribe line SL, represented by a dashed line, along which dicing of the wafer1will be carried out, for the formation of dies of the power device, once the manufacturing process is completed.

The edge anode region5is arranged externally with respect to the active area A′ and to the anode wells4, for example being shaped like a ring around the active area A′. In a way not shown, the aforesaid edge anode region5may be connected to a ring-shaped implanted region, which is also formed at the front surface2aof the substrate2, at the edge area A″ (having, in a known manner, functions of termination of the electrical field).

As shown in the aforesaidFIG. 1A, a thick dielectric layer8, in particular of TEOS (TetraEthyl OrthoSilicate), is formed by deposition on the substrate2, coating the entire front surface2aof the substrate2; the thick dielectric layer8has a thickness comprised, for example, between 0.5 μm and 2.5 μm.

As illustrated inFIG. 1B, an overlying layer10is formed by deposition on the thick dielectric layer8, for example made of polysilicon or of a different material (for example, silicon nitride), which provides a chemical-etching selectivity relative to the material of the thick dielectric layer8, in the example TEOS; the overlying layer10has a thickness comprised, for example, between 0.2 μm and 1.5 μm.

As illustrated inFIG. 1C, the overlying layer10is defined via photolithographic process, i.e., via formation of a photoresist mask (not illustrated here) and subsequent etching of the material, in the example polysilicon (selectively with respect to the underlying thick dielectric layer8).

In particular, definition of the overlying layer10leads to formation of a first overlying region10aand a second overlying region10b, at the edge area A″, which are spaced apart laterally (in the horizontal plane xy, inFIG. 1Calong the axis x) and define between them an access window12. As will be illustrated hereinafter, these overlying regions10a,10bcan have a ring shape in top view and are arranged around and externally to the active area A′ of the power device.

For instance, the first and second overlying regions10a,10bmay have a same width in the horizontal plane xy (inFIG. 1Calong the axis x), for example a width of 20 μm, and the access window12may have a width (inFIG. 1Calong the axis x; in general, in a direction transverse to a direction of longitudinal extension) comprised between 10 μm and 20 μm.

In particular, the first overlying region10ais located laterally at a distance (in the horizontal plane xy, inFIG. 1Calong the axis x) with respect to the boundary of the active area A′ of the power device, therefore being arranged, in use, in an electrically non-active area of the power device (in other words, an area external to the area involved by the electrical field lines due to operation of the power device).

As illustrated inFIG. 1D, the thick dielectric layer8is then defined, once again by photolithographic process so as to remove it (therefore leaving the front surface2aof the substrate2exposed) in the active area A′ (therefore exposing the anode wells4and, at least in part, the edge anode region5) and moreover along the scribe line SL, leaving a remaining dielectric region8aabove the edge area A″.

In a known way, here not shown, anode electrical-contact regions may then be formed, by surface implants in the aforesaid anode wells4and edge anode region5, in order to improve the corresponding electrical contact properties.

As shown inFIG. 1E, a front conductive layer14, for example a metal layer, is then formed above the front surface2aof the substrate2, in a conformable manner (for example, by a sputtering process).

The front conductive layer14is then defined, as illustrated inFIG. 1F, via photolithographic process, so as to remove it in the edge area A″ and leave a remaining portion thereof, designated by14a, above the active area A′, in particular in direct contact with the front surface2aof the substrate2, the anode wells4, and the edge anode region5, therefore forming an anode electrical contact of the power device.

As illustrated in the aforesaidFIG. 1F, this remaining portion14aextends in part also above the dielectric region8a, at the boundary between the active area A′ and the edge area A″.

The outer end of the aforesaid remaining portion14ais in any case sufficiently far from the first overlying region10a, so that the first overlying region10ais located, as discussed previously, in a non-active area of the power device (for example, in the case where the electrical field lines terminate at a distance of approximately 20 μm from the outer end of the remaining portion14a, the first overlying region10ais arranged at a distance sufficiently higher than 20 μm from the same outer end of the remaining portion14a).

With reference toFIG. 1G, the manufacturing process proceeds with a chemical etching, for example with hydrofluoric acid (HF), of the dielectric region8a, through the access window12defined between the first and second overlying regions10a,10b.

In particular, this etching operation is carried out via photolithographic process, with an etching mask15, represented schematically by a dashed line in the aforesaidFIG. 1G, which coats the entire surface of the wafer1and in particular a major part of the same overlying regions10a,10b, except for the area at the aforesaid access window12. In other words, the etching mask15has an opening15avertically corresponding to the access window12, having slightly larger dimensions, in the horizontal plane xy (inFIG. 1Galong the axis x), than those of the access window12.

During etching, the chemical-etching agent (in the example, HF) therefore penetrates through the access window12through the dielectric region8a, removing the underlying material (etching stops on the front surface2aof the substrate2), without, however, involving the overlying regions10a,10bgiven the characteristics of selectivity of the etching process in regard to the material of the same overlying regions10a,10b.

In particular, given that wet etching is totally isotropic, an anchorage opening16is formed in the dielectric region8a, extending vertically (along the vertical axis z) throughout the thickness of the dielectric region8a, and which horizontally (in the horizontal plane xy, inFIG. 1Galong the axis x, in general in a direction transverse to a direction of longitudinal extension) has a width, designated by W1, that is greater than the corresponding width, designated by W2, of the access window12(for example, satisfying the relation: W1>W2+10 μm; in other words, there is, for example, a difference of at least 5 μm with respect to the overlying opening, i.e., the access window12, on either side along the axis x).

In detail, in the embodiment illustrated, the anchorage opening16is trapezium-shaped in cross-section, and the aforesaid dimension W1has a larger extension, at the major base of the trapezium, facing the access window12, comprised, for example, between 2 μm and 5 μm (in any case depending upon the thickness of the dielectric, the aforesaid wet etching being isotropic).

Basically, following upon etching, a respective end portion of the first and second overlying regions10a,10b, designated by18aand18b, respectively, facing the access window12, is arranged suspended and protruding over the underlying anchorage opening16.

As illustrated inFIG. 1H, a passivation layer20, in particular, of polyimide (other materials, for example photoresist or the like, which in any case have dielectric characteristics, may be used) is then formed above the entire surface of the wafer1(except for the area of the scribe line SL). For instance, the passivation layer is formed using fluid or viscous spin-coating techniques and is subsequently subjected to a curing step.

Following upon its formation, the passivation layer20has, in particular, an anchorage region22, which extends in the anchorage opening16, occupying it entirely, and has: a first portion22a, within the aforesaid anchorage opening16, which assumes a corresponding conformation (in the example, with trapezoidal cross-section); and a second portion22b, within the access window12, having a width smaller than that of the first portion (inFIG. 1H, along the axis x).

In particular, the aforesaid first portion22aof the anchorage region22is located directly underneath, and in direct contact with, the end portions18a,18bof the first and second overlying regions10a,10b, and the aforesaid second portion22bis arranged between the same end portions18a,18b.

The wafer1is then subjected to dicing along the scribe line SL, for formation of a die integrating the power device, here designated by25(in the example, a power diode).

The aforesaid power device25therefore has the passivation layer20, arranged at least over the dielectric region8(of thick dielectric) in the edge area A″, that is appropriately anchored thanks to the presence of the corresponding anchorage region22and the associated mechanical anchorage within the anchorage opening16.

Advantageously, this anchorage region22allows the passivation layer20to remain mechanically anchored, even after thermal cycles (during electrical testing or during effective operation of the power device25), eliminating or in any case markedly reducing the possibility of delamination of the passivation layer20from the underlying material and of consequent electrical-arching phenomena.

FIG. 2is a simplified top view, with parts removed for clarity, of the resulting power device25and of the corresponding die, designated by1′ (having a substantially square conformation in top view).

In the embodiment illustrated, the active area A′ of the power device25has a substantially square conformation in the horizontal plane xy, corresponding to which is a substantially square conformation of the overlying anode electrical contact (constituted by the remaining portion14aof the front conductive layer14). The first and second overlying regions10a,10bhave in this case the conformation of a square ring in the horizontal plane xy and entirely surround the active area A′. The passivation layer20extends above the front surface of the die25′ and has, in particular, the anchorage region22, which also has the shape of a square ring (in top view), being in fact arranged at the access window12defined between the aforesaid first and second overlying regions10a,10b.

In the variant embodiment illustrated inFIG. 3, the first and second overlying regions10a,10bdo not form a complete ring around the active area A′ of the power device25, but are arranged in a distributed manner, only at the corners of the active area A′, externally thereto. Consequently, also the anchorage region22is in this case present in a distributed manner, only at the aforesaid corners, being on the other hand made in a way altogether similar to what has been discussed previously.

FIG. 4shows, once again in cross-sectional view, a further variant of the power device25, where the second overlying region10bhas a width in the horizontal plane xy (inFIG. 4along the axis x, in general in a direction transverse to the direction of longitudinal extension) greater than the corresponding width of the first overlying region10a.

In particular, the aforesaid second overlying region10bhas a further end18b′, opposite to the end18bfacing the access window12, which protrudes from the underlying dielectric region8a. Consequently, the passivation layer20, once formed, has a further anchorage area, designated by22′, arranged directly underneath the aforesaid further end18b′, which therefore contributes to anchoring the passivation layer20with respect to the underlying substrate2and to preventing delamination phenomena due to the thermomechanical stresses.

In an evident manner, also for this embodiment the configurations discussed previously with reference toFIGS. 2 and 3may be envisaged.

A further embodiment of the manufacturing process of the power device is now discussed.

In this case, as shown inFIG. 5A, a first dielectric layer30, in particular of TEOS, is first deposited above the front surface2aof the substrate2(at which the anode wells4and the edge anode region5have previously been formed).

As illustrated inFIG. 5B, this first dielectric layer30is then subjected to a dopant implantation (for example, As, Ar, or some other P type dopant) through an appropriate implant mask31, in a way limited and confined to an external region, at the edge area A″ and in the proximity of the scribe line SL, for formation of a doped portion30′ (the width of which in the horizontal plane xy, along the axis x inFIG. 5B, substantially corresponds to the aforesaid width W1, as will be highlighted hereinafter).

The aforesaid doped portion30′ is arranged at what constitutes, during operation, an electrically non-active area of the power device (in other words, it is arranged in an area external to the area involved by the electrical field lines due to operation of the power device).

Next, as shown inFIG. 5C, a second dielectric layer32, in particular once again of TEOS, is deposited above the first dielectric layer30(and the corresponding doped portion30′), the assembly constituted by the first and second dielectric layers30,32forming a thick dielectric layer, once again designated by8, within which, as has been discussed previously, the aforesaid doped portion30′ is to be incorporated.

In particular, following upon the aforesaid implantation, the doped portion30′ has an etch rate higher than that of the material constituting the second dielectric layer32; for example, the ratio between the etch rate of the doped portion30′ and that of the second dielectric layer32is higher than or equal to two.

As illustrated inFIG. 5D, the thick dielectric layer8is then defined, via photolithographic process, so as to remove it (therefore leaving the front surface2aof the substrate2exposed) in the active area A′ (thus exposing the anode wells4and, at least in part, the edge anode region5) and moreover along the scribe line SL, leaving a remaining dielectric region8aabove the edge area A″ (wherein the aforesaid doped portion30′ is incorporated).

As illustrated inFIG. 5E, the front conductive layer, once again designated by14, for example a metal layer, is then formed, in a conformable manner on the front surface2aof the substrate2(for example, by a sputtering process).

The above front conductive layer14is then defined, as illustrated inFIG. 5F, via photolithographic process, so as to remove it in the edge area A″ and leave a remaining portion thereof, designated once again by14a, in the active area A′, in particular in direct contact with the front surface2aof the substrate2, the anode wells4, and the edge anode region5, thus forming the anode electrical contact of the power device.

As illustrated in the aforesaidFIG. 5F, the remaining portion14aextends in part also on the dielectric region8a, at the boundary between the active area A′ and the edge area A″.

As shown inFIG. 5G, dry etching, for example plasma etching, of the dielectric region8ais then carried out, in an area vertically corresponding to the corresponding doped portion30′.

In particular, etching is carried out through an appropriate etching mask33(represented schematically with dashed lines) so as to dig a vertical trench34throughout the thickness of the dielectric region8a, centrally with respect to the corresponding doped portion30′ (it is noted that the dry etch involves indistinctly the material of the dielectric region8a, irrespective of doping, therefore without distinction as regards the corresponding doped portion30′).

As shown inFIG. 5H, through the same etching mask33, which has therefore not yet been removed, a second etch is carried out, in particular a wet etch, for example with hydrofluoric acid HF.

On account of the different etch rate, the etch penetrates, in the horizontal plane xy, more into the doped portion30′ than it does into the overlying material of the dielectric region8a, thus causing removal (in the example, complete removal) of the same doped portion30′, for formation of what is once again defined as the anchorage opening16and of the access window12, overlying, and in fluidic communication with, the same anchorage opening16, which is in this case also formed in the same dielectric region8a. The anchorage opening16therefore has again, in the horizontal plane xy (inFIG. 5Halong the axis x), a width W1greater than the corresponding width W2of the access window12.

It is noted that, in this embodiment, the end portions, once again designated by18a,18b, facing the access window12and suspended and protruding above the underlying anchorage opening16are the result of etching of the surface portion of the dielectric region8aand are therefore constituted by the material of the same dielectric region8a.

As illustrated inFIG. 5I, the passivation layer20, for example, of polyimide, is then formed above the entire surface of the wafer1(except for the area of the scribe line SL), using spin-coating techniques.

After its formation, the passivation layer20has in particular the anchorage region22, which extends in the anchorage opening16, occupying it entirely, and once again has: the first portion22a, within the same anchorage opening16, having a corresponding conformation; and the second portion22b, within the access window12, having a dimension smaller than that of the first portion22ain the horizontal plane xy (inFIG. 5I, along the axis x).

In particular, the aforesaid first portion22aof the anchorage region22is located directly underneath, and in direct contact with, the end portions18a,18bof the dielectric region8a, and the aforesaid second portion22bis arranged between the same end portions18a,18bof the dielectric region8a.

The wafer1is then subjected to dicing along the scribe line SL, for formation of the die containing the power device, once again designated by25.

Also in this case, advantageously, the anchorage region22enables the passivation layer20to remain anchored and fixed, even following upon thermal cycles and the resulting electromechanical stresses.

FIG. 6is a top view, simplified and with parts removed for clarity, of the resulting power device25and of the corresponding die1′ (having a substantially square conformation in top view).

In the embodiment illustrated, the active area A′ of the power device25has a substantially square conformation in the horizontal plane xy, corresponding to which is a substantially square conformation of the remaining overlying portion14aof the front conductive layer14(which constitutes the anode electrical contact).

The anchorage opening16and the corresponding anchorage region22of the passivation layer20have the conformation of a square ring in the horizontal plane xy itself, entirely surrounding the active area A′.

In the embodiment illustrated inFIG. 7, the aforesaid anchorage opening16and the aforesaid anchorage region22do not form a complete ring around the active area A′ of the power device25, but are arranged in a distributed manner only at the corners of the active area A′, externally thereto.

A further embodiment of the process for manufacturing the power device is now discussed.

In this case, as illustrated inFIG. 8A, a sacrificial region40is first formed above the front surface2aof the substrate2, by deposition via photolithographic process; the sacrificial region40is made of polysilicon or other appropriate material (for example, silicon nitride), which provides a chemical-etching selectivity relative to the dielectric material, for example TEOS, of which the thick dielectric layer8will then be formed.

The sacrificial region40is formed in a manner limited and confined to an external region of the power device, in the edge area A″ and in the proximity of the scribe line SL, therefore being arranged in what constitutes, during operation, an electrically non-active area of the power device (in other words, being arranged in an area external to the area involved by the electrical field lines due to operation of the power device).

The sacrificial region40has, for example, a width of approximately 30 μm (in particular, the width of the sacrificial region40in the horizontal plane xy, along the axis x inFIG. 6A, corresponds substantially to the aforesaid width W1, as will on the other hand be highlighted hereinafter).

Then (FIG. 8B), the thick dielectric layer8, for example, once again of TEOS, is deposited above the front surface2aof the substrate2and in particular on the sacrificial region40, which is therefore incorporated within the same thick dielectric layer8.

As shown inFIG. 8C, the thick dielectric layer8is then defined, via photolithographic process, in a way substantially similar to what has been discussed previously, therefore so as to remove it in the active area A′ and moreover along the scribe line SL, leaving a remaining dielectric region8aabove the edge area A″ (wherein the aforesaid sacrificial region40is incorporated).

As illustrated inFIG. 8D, the manufacturing process proceeds in this case with dry etching, for example plasma etching, of the dielectric region8a, in an area vertically corresponding to the sacrificial region40.

In particular, etching is carried out using an appropriate etching mask42(represented schematically with a dashed line), so as to dig a trench44throughout the thickness of the dielectric region8a, centrally with respect to the aforesaid sacrificial region40.

As illustrated inFIG. 8E, after removal of the etching mask42, a second etch is carried out, in particular a wet etch for selective removal of the remaining sacrificial region40. In particular, the etching agent penetrates into the trench44and moves laterally to remove the aforesaid sacrificial region40so as to form what is once again defined as anchorage opening16in the dielectric region8aand the access window12, overlying, and in fluidic communication with, the same anchorage opening16, which in this case is also formed in the same dielectric region8a(the anchorage opening16once again has in the horizontal plane xy, inFIG. 8Ealong the axis x, a width W1greater than the corresponding width W2of the access window12).

The anchorage opening16has in this case a substantially rectangular shape in cross-section, and the access window has a substantially trapezoidal section (with the minor base facing the aforesaid anchorage opening16).

It is noted that, also in this embodiment, the end portions18a,18b, facing the access window12and suspended and protruding above the underlying anchorage opening16, are the result of etching of the surface portion of the dielectric region8aand are integral with the same dielectric region8a.

As illustrated inFIG. 8F, the front conductive layer, once again designated by14, for example of metal material, is then formed, in a conformable manner on the front surface2aof the substrate2(for example, by a sputtering process); it is noted that in this case, the front conductive layer14also penetrates into the anchorage opening16and the access window12, in the example filling them.

The front conductive layer14is then defined, as illustrated inFIG. 8G, via photolithographic process, so as to remove it in the edge area A″ and leave a remaining portion thereof, designated once again by14a, above the active area A′, in particular in direct contact with the front surface2aof the substrate2, the anode wells4, and the edge anode region5, therefore forming the anode electrical contact of the power device. As illustrated in the aforesaidFIG. 8G, this remaining portion14aextends in part also on the dielectric region8a, at the boundary between the active area A′ and the edge area A″. It is noted that this etching envisages complete removal of the material within the anchorage opening16and the access window12.

As illustrated inFIG. 8H, the passivation layer20, for example of polyimide is then formed above the entire surface of the wafer1(except for the area of the scribe line SL), using spin-coating techniques.

Following upon its formation, the passivation layer20has in particular the anchorage region22, which extends in the anchorage opening16, occupying it entirely, and once again has: the first portion22a, within the same anchorage opening16, having a corresponding conformation (also in this case being rectangular in section); and the second portion22b, within the access window12, having a size smaller than that of the first portion22ain the horizontal plane xy (inFIG. 8H, along the axis x).

In particular, the aforesaid first portion22aof the anchorage region22is located also in this case directly underneath, and in direct contact with, the end portions18a,18bof the dielectric region8a, and the aforesaid second portion22bis arranged between the same end portions18a,18bof the dielectric region8a.

The wafer1is then subjected to dicing along the scribe line SL, for formation of the die integrating the power device, once again designated by25.

Also in this case, advantageously, the anchorage region22enables the passivation layer20to remain anchored in a fixed manner within the anchorage opening16, even following upon thermal cycles and resulting electromechanical stresses.

FIG. 9is a simplified top view, with parts removed for clarity, of the resulting power device25and of the corresponding die1′ (having a substantially square conformation in top view). In the embodiment illustrated, the active area A′ of the power device25has a substantially square conformation in the horizontal plane xy, corresponding to which is a substantially square conformation of the remaining overlying portion14aof the front conductive layer14(which defines the anode electrical contact).

The anchorage opening16and the corresponding anchorage region22of the passivation layer20have the conformation of a square ring in the horizontal plane xy, surrounding the active area A′ entirely.

In the embodiment illustrated inFIG. 10, the aforesaid anchorage opening16and the aforesaid anchorage region22do not form a complete ring around the active area A′ of the power device25, but are arranged in a distributed way only at the corners of the active area A′, externally thereto.

The advantages of the present solution are clear from the foregoing description.

In particular, it is once again underlined that, thanks to the presence of the anchorage region22, the passivation layer20is anchored and fixed in a reliable manner, thus preventing possible delamination thereof, i.e., its partial detachment from the underlying material, on account of thermomechanical stresses due to thermal cycles.

Consequently, the present solution enables maximization of the reliability and robustness of a resulting power device25, in particular with respect to the corresponding edge termination (from which, in use, the aforesaid delamination phenomena start), which is obtained starting from the silicon carbide substrate2.

The manufacturing process, in the embodiments described, is convenient and economically advantageous to implement, including processing steps that are in themselves standard in the semiconductor industry.

Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure.

In particular, it is underlined that the present solution can find advantageous application in any electronic device, in particular for power applications, in which anchorage of a passivation layer to an underlying material is advantageous to prevent phenomena of delamination due, for example, to thermomechanical stresses.

Moreover, it is underlined that the present solution may envisage a desired number of anchorage regions22, obtained in a way altogether corresponding to what has been discussed previously, in particular in the edge area A″ of the power device25.

Provision of a plurality of anchorage regions22may in fact enable a further increase in the anchoring of the passivation layer20and therefore a further increase in the reliability of the resulting power device25.

These anchorage regions22may have any desired arrangement; for example, they may be arranged according to a grid arrangement in the aforesaid edge area A″.

Purely by way of example,FIG. 11shows the cross-section of a power device25(in particular, a power diode, but it is evident that what has been illustrated may be applied for any different electronic device), which has two anchorage regions22in the edge area A″, spaced apart at an appropriate separation distance (inFIG. 11along the axis x).