Scan driver and driving method thereof

A display device includes a plurality of scan lines and a scan driver. The scan driver includes a plurality of stages for transmitting a scan signal having a first voltage to the plurality of scan lines, and each of the stages includes a sequential switching unit, a sequential output unit, a concurrent switching unit, and a concurrent output unit. The concurrent output unit includes a first transistor for transmitting a second control signal to the output terminal according to a first control signal during a concurrent driving period before the scan signal is converted from a first level to a second level according to the second control signal, and a gate voltage of the first transistor is controlled by a voltage that is different from the first voltage according to the first control signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2011-0004076, filed in the Korean Intellectual Property Office on Jan. 14, 2011, the entire contents of which are incorporated herein by reference.

BACKGROUND

The present invention relates to a scan driver and a driving method thereof. More particularly, the present invention relates to a scan driver of a display device.

2. Description of the Related Art

An active display device, such as an organic light emitting diode (OLED) display and a liquid crystal display (LCD), includes a plurality of pixels disposed in a matrix format, defined by a plurality of scan lines extending in a row direction and a plurality of data lines extending in a column direction. A scan driver sequentially applies scan pulses to the plurality of scan lines, and a data driver transmits data signals to the plurality of data lines to write corresponding data to the plurality of pixels for displaying images.

In general, the display device sequentially applies the scan pulses to the plurality of scan lines to sequentially write the data to the pixels included in the pixel lines extending in the row direction to display the images. However, as the size of the display panel of the display device is increased and the driving method becomes complicated, the display device concurrently (e.g., simultaneously) applies a voltage (e.g., a predetermined voltage) to the plurality of scan lines such that all pixels may be concurrently (e.g., simultaneously) initialized or concurrently (e.g., simultaneously) light-emitted or stopped from light emitting, as well as have sequential data writing.

Accordingly, a scan driver capable of executing an operation of a shift register for sequentially applying the scan pulses (hereinafter, sequential switching) and an operation of concurrently (e.g., simultaneously) outputting a voltage (e.g., a predetermined voltage) for turning on/off (hereinafter, concurrent switching) is desired. Particularly, research on a circuit structure that quickly and stably processes conversion between voltages when executing concurrent switching of the scan driver by converting into a high voltage (e.g., a predetermined high voltage) and a low voltage (e.g., a predetermined low voltage) and outputting them is desired.

SUMMARY

Embodiments of the present invention are directed toward a scan driver that is capable of concurrently (e.g., simultaneously) applying a voltage (e.g., a predetermined voltage), as well as having a function of a shift register for sequentially applying scan pulses and quickly and stably processing conversion between the voltages when concurrently (e.g., simultaneously) outputting a predetermined voltage.

According to an embodiment of the present invention, a scan driver includes a plurality of stages being configured to transmit a scan signal to a plurality of scan lines of a display device. Each of the stages includes a sequential switching unit, a sequential output unit, a concurrent switching unit, and a concurrent output unit. The sequential switching unit is configured to receive the scan signal from an output terminal of a previous stage. The sequential output unit is connected to an output terminal of a same stage of the stages. The concurrent output unit is connected to the output terminal. The sequential switching units of the stages are configured to sequentially scan the scan signal having a first voltage in a first period, and the sequential output units of the stages are configured to sequentially output the scan signal having the first voltage. The concurrent switching units of the stages are configured to concurrently output the scan signal having a same voltage in a second period, and the concurrent output units of the stages are configured to concurrently output the scan signal having the same voltage. The concurrent output unit includes a first transistor for transmitting a second control signal to the output terminal according to a first control signal during the second period, and a gate voltage of the first transistor is controlled by a second voltage that is different from the first voltage according to the first control signal before the scan signal is changed from a first level to a second level according to the second control signal.

The concurrent output unit may further include a second transistor connected to a gate of the first transistor, and the concurrent output unit may be configured to be turned on according to the first control signal to transmit a voltage of the second level.

The first transistor may be configured to output a same voltage as the first level or the second level as the scan signal during the second period corresponding to the second control signal when the first transistor is turned on.

The second voltage may be different from the voltage of the second level by a voltage difference of a third voltage.

The third voltage may be a threshold voltage of a second transistor included in the concurrent output unit of the scan driver.

When each of the stages includes PMOS transistors, the voltage of the second level may be a low level voltage and the second voltage may be higher than the low level voltage by the third voltage, and when each of the stages includes NMOS transistors, the voltage of the second level may be a high level voltage and the second voltage may be lower than the high level voltage by the third voltage.

The first control signal may have a gate-off voltage level for turning off transistors included in each of the stages at the first period and a gate-on voltage level for turning on the transistors included in each of the stages at a second period, and the second control signal may have a voltage of the first level or the second level at the second period.

The second period may include a third period and a fourth period, and the concurrent switching unit and the concurrent output unit included in each of the stages may be configured to concurrently output the scan signal of the same voltage as the first level corresponding to the second control signal of the first level during the third period, and to concurrently output the scan signal of the same voltage as the second level corresponding to the second control signal of the second level during the fourth period.

Each of the stages may include first, second, and third clock terminals, and first, second, and third clock signals may be alternately and respectively input to the first, second, and third clock terminals of each of the stages. The first, second, and third clock signals may sequentially have gate-on voltage levels for turning on the transistors included in each of the stages during the first period, and each have a cycle of 3 horizontal cycles and a 1/3 duty ratio.

The sequential switching unit and the sequential output unit of each of the stages may be configured to sequentially scan the scan signal corresponding to the first, second, and third clock signals during the first period, and the sequential output unit may be configured to output a voltage of the second clock terminal as the first voltage of the scan signal during the first period.

Each of the stages may further include a control terminal. A third control signal may be input to the control terminal, and the third control signal may have a gate-on voltage level for turning on the transistors included in each of the stages during the first period.

Each of the stages may include first, second, and third clock terminals. First, second, and third clock signals may be alternately and respectively input to the first, second, and third clock terminals of each of the stages, and the first, second, and third clock signals all may have the gate-off voltage level for turning off the transistors included in each of the stages during the second period.

Each of the stages may further include a control terminal. A third control signal may be input to the control terminal, and the third control signal may have the gate-off voltage level for turning off the transistors included in each of the stages during the second period.

According to an embodiment of the present invention, a scan driver including a plurality of stages is configured to transmit a scan signal to a plurality of scan lines of a display device. Each of the stages includes a first transistor, a second transistor, a third transistor, a fourth transistor, a sequential driver, and a concurrent driver.

The first transistor is connected between a first control terminal supplied with a voltage of a first level or a second level and an output terminal for outputting a scan signal having a voltage according to the voltage of the first control terminal, and the first transistor has a gate connected to a first node. The second transistor is connected between a second control terminal supplied with the voltage of the first level or the second level and the first node, and the second transistor has a gate connected to the second control terminal. The third transistor is connected to a first voltage terminal supplied with a first voltage and the output terminal, and the first transistor has a gate connected to a second node. The fourth transistor is connected between the output terminal and a clock terminal supplied with the voltage of the first level or the second level, and the fourth transistor has a gate connected to a third node. The sequential driver is connected to an input terminal for receiving a scan signal from a previous stage, the first voltage terminal, a second voltage terminal for supplying the second voltage, and the first node to the third node. The sequential driver is configured to operate the third and fourth transistors to sequentially output the scan signal having the second voltage to the output terminals of the plurality of stages during a first period. The concurrent driver is connected to the first voltage terminal, the second control terminal, the second node, and the third node, and the concurrent driver is configured to concurrently turn on the first and second transistors such that the scan signal of a same voltage is concurrently output to the output terminals of the plurality of stages during a second period. Before the scan signal of the same voltage is changed from a first level to a second level according to the voltage of the first control terminal, each of the stages is configured to control the first node voltage to be a third voltage that is different from the second voltage.

The third voltage may be different from the voltage of the second level by a fourth voltage. The fourth voltage may be a threshold voltage of the second transistor.

When each of the stages includes PMOS transistors, the voltage of the second level may be a low level voltage and the third voltage may be higher than the low level voltage by the fourth voltage, and when each of the stages includes NMOS transistors, the voltage of the second level may be a high level voltage and the third voltage may be lower than the high level voltage by the fourth voltage.

The second transistor may be connected between the second voltage terminal for receiving a fifth voltage and the first node, and the gate of the second transistor may be connected to the second control terminal for receiving the voltage of the first level or the second level.

Each of the stages may be configured to receive a first control signal and a second control signal. The first control signal may have a gate-off voltage level for turning off the transistors included in each of the stages during the first period and a gate-on voltage level for turning on the transistors included in each of the stages during the second period. The second control signal may have a voltage of the first level or the second level during the second period.

The second period may include a third period and a fourth period, and the concurrent drivers of the stages may be configured to concurrently output the scan signal as the first level corresponding to the second control signal of the first level during the third period and to concurrently output the scan signal as the second level corresponding to the second control signal of the second level during the fourth period.

The concurrent driver may include a fifth transistor and a sixth transistor. The fifth transistor may be connected between the first voltage terminal and the second node, and the fifth transistor may be configured to be turned on in response to a gate-on voltage supplied to the second control terminal. The sixth transistor may be connected between the first voltage terminal and the third node, and the sixth transistor may be configured to be turned on in response to the gate-on voltage supplied to the second control terminal.

Each of the stages may further include a first capacitor connected between the output terminal and the first node.

The sequential driver may include a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor. The seventh transistor may be connected between the first voltage terminal and the second node, and the seventh transistor may have a gate connected to the input terminal. The eighth transistor may be connected between the first voltage terminal and the third node, and the eighth transistor may have a gate connected to the second node. The ninth transistor may be connected between the input terminal and the third node, and the ninth transistor may have a gate connected to a first clock terminal. The tenth transistor may be connected between the first voltage terminal and the first node, and the tenth transistor may have a gate connected to a second clock terminal or a third control terminal. The eleventh transistor may be connected between the second node and the second voltage terminal, and the eleventh transistor may have a gate connected to a third clock terminal.

First, second, and third clock signals may be alternately and respectively input to the first, second, and third clock terminals. The first, second, and third clock signals may sequentially have a gate-on voltage level for turning on a transistor during the first period, and each may have three horizontal cycles and a 1/3 duty ratio. The first, second, and third clock signals may have a gate-off voltage level for turning off the transistor during the second period.

First, second, and third clock signals may be alternately and respectively input to the first, second, and third clock terminals, and a third control signal may be input to the third control terminal. The signal that is input to the second clock terminal or the third control terminal may have a gate-on voltage level for turning on a transistor during the first period, and the signal that is input to the second clock terminal or the third control terminal may have a gate-off voltage level for turning off the transistor during the second period.

Each of the stages may further include a second capacitor connected between the first voltage terminal and the second node, and a third capacitor may be connected between the output terminal and the third node.

According to an embodiment of the present invention, a method for driving a scan driver of a display device including a plurality of scan lines is provided. In sequential driving, in response to a plurality of clock signals each alternately having a first level and a second level, the method includes sequentially transmitting a scan signal having a voltage corresponding to the second level to the plurality of scan lines. In concurrent driving, the method includes concurrently applying the scan signal having the voltage corresponding to the first level or the second level to the plurality of scan lines according to a second control signal having the voltage corresponding to the first level or the second level, in a state in which the plurality of clock signals are maintained as the first level and the first control signal is maintained as the second level. In the concurrent driving, before the scan signal is changed from the first level to the second level according to the second control signal, a gate voltage of a first transistor for transmitting the second control signal to an output terminal according to the first control signal is controlled at a first voltage that is different from the voltage corresponding to the second level.

The first voltage may be different from the voltage corresponding to the second level by a second voltage. The second voltage may be a threshold voltage of a second transistor connected to a gate of the first transistor.

When the scan driver includes PMOS transistors, the voltage corresponding to the second level may be a low level voltage and the first voltage may be higher than the low level voltage by the second voltage. When the scan driver includes NMOS transistors, the voltage corresponding to the second level may be a high level voltage and the first voltage may be lower than the high level voltage by the second voltage.

In the sequential driving, the method further includes receiving a third control signal having the second level, and in the concurrent driving, the method further includes receiving the third control signal having the first level.

According to exemplary embodiments of the present invention, the scan driver may perform both sequential switching by sequentially applying a scan signal to a plurality of scan lines and concurrent switching by applying a constant voltage to a plurality of scan lines.

According to an exemplary embodiment of the present invention, in the concurrent switching operation of the scan driver, a circuit structure having an output with a fast and stable switching speed between a high voltage and a low voltage may be provided. Accordingly, the scan driver may be applied to a large, high resolution, and high speed panel.

Also, when comparing with a typical circuit configuration of a scan driver, the number of elements and signals that are used may be reduced such that the circuit configuration may be simplified and the layout area may be reduced. Accordingly, a probability of product deterioration may be reduced such that a yield may be improved.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.

FIG. 1is a block diagram of a display device according to an exemplary embodiment of the present invention,FIG. 2andFIG. 8are block diagrams of a scan driver according to exemplary embodiments of the present invention, andFIG. 3is a circuit diagram of one stage of the scan driver shown inFIG. 2.

Referring toFIG. 1, a display device includes a display unit100, a scan driver200, a data driver300, and a signal controller400for controlling them.

In a view of an equivalent circuit diagram, the display unit100includes a plurality of display signal lines S1-Sn and D1-Dm and a plurality of pixels PX connected thereto and arranged in a matrix format. The display unit100may include a lower panel and an upper panel (not shown) facing each other.

The display signal lines S1-Sn and D1-Dm include a plurality of scan lines S1-Sn for transmitting scan signals (referred to as “gate signals”) and a plurality of data lines D1-Dm for transmitting data signals. The scan lines S1-Sn extend in the row direction and are parallel to each other, and the data lines D1-Dm extend in the column direction and are parallel to each other.

The scan driver200is connected with the scan lines S1to Sn, and applies scan signals, formed of a combination of a gate-on voltage and a gate-off voltage, to the scan lines S1to Sn. The gate-on voltage is a voltage that is applied to the gate of a transistor, thereby turning on the transistor, and the gate-off voltage is a voltage that is applied to the gate of the transistor, thereby turning off the transistor.

The data driver300, connected to the data lines D1-Dm, generates the data signals, representing the grayscale of the pixel PX, and applies them to the data lines D1-Dm.

The signal controller400controls the operation of the scan driver200and the data driver300.

On the other hand, the pixel PX includes a transistor (not shown), which has the gate connected to the scan line and the source/drain connected to the data line to transmit the data signal from the data line in response to the gate-on voltage from the scan line, and a light emitting region (not shown) that emits light with a gray level according to the data signal of the transistor. Here, when the display device is the liquid crystal display (LCD), the light emitting region may include a capacitor for storing the data signal and a liquid crystal layer for displaying the gray level according to the data signal stored in the capacitor. Also, when the display device is an organic light emitting display, the light emitting region may include a capacitor for storing the data signal, a driving transistor for transmitting an amount of current according to the data signal that is stored in the capacitor, and an organic light emitting diode (OLED) for emitting light with the gray level according to the current from the driving transistor.

The drivers200,300, and the controller400may be directly mounted on the display unit100as at least one integrated circuit chip type, may be mounted on a flexible printed circuit film (not shown) to be attached to the display unit100as a tape carrier package (TCP), and may be separately mounted on a flexible printed circuit (FPC) (not shown). Alternatively, the drivers200,300, and400may be integrated in the display unit100along with the signal lines S1-Sn and D1-Dm and the transistors. Also, the drivers200,300, and the controller400may be integrated as a single chip, and in one embodiment, at least one among them or at least one circuit element forming them may be positioned outside the single chip.

Referring toFIG. 2, the scan driver200ofFIG. 1includes a plurality of stages ST1-STn, and receives a high voltage VGH, a low voltage VGL, at least one clock signal SCK1, SCK2, and SCK3, at least one control signal, and a scan start signal SSP. The at least one control signal includes a first control signal SS and a second control signal SGCK. The plurality of stages ST1-STn are connected to a plurality of scan lines S1-Sn of the display device, respectively, and output the scan signals scan[1]-scan[n] to the corresponding scan lines S1-Sn.

Each stage, for example the i-th stage STi, includes an input terminal IN, an output terminal OUT, clock terminals CK1, CK2, and CK3, a first control terminal SST, a second control terminal GCK, a high voltage terminal VGHT, and a low voltage terminal VGLT.

The first control signal SS and the second control signal SGCK are respectively input to the first control terminal SST and the second control terminal GCK of the i-th stage STi. The high voltage VGH and the low voltage VGL are respectively applied to the high voltage terminal VGHT and the low voltage terminal VGLT of the i-th stage STi.

The clock signals SCK1, SCK2, and SCK3are alternately and respectively input to the clock terminals CK1, CK2, and CK3, of the plurality of stages ST1-STn. In more detail, in the case that I is 3j−2 (hereinafter, j=1, 2, . . . n/3) in the i-th stage STi, the clock terminals CK1, CK2, and CK3are respectively input with the clock signals SCK1, SCK2, and SCK3, in the case that I is 3j−1, the clock terminals CK1, CK2, and CLK3are respectively input with the clock signals SCK2, SCK3, and SCK1, and in the case that I is3j, the clock terminals CK1, CK2, and CK3are respectively input with the clock signals SCK3, SCK1, and SCK2.

The output terminal OUT of the i-th stage STi outputs the scan signal scan[i], selectively having the gate-on voltage and the gate-off voltage, to the corresponding scan line Si.

The input terminal IN of the i-th stage STi is connected to the output terminal OUT of the previous stage STi−1 such that the input terminal of the i-th stage STi receives the scan signal scan[i−1] of the previous stage STi−1 that is the previous output signal. The output terminal OUT of the i-th stage STi is connected to the input terminal IN of the next stage STi+1 to transmit the scan signal scan[i].

The input terminal IN of the first stage ST1is input with the scan start signal SSP. Also, the output terminal OUT of the final stage STn is connected to the corresponding scan line Sn.

Here, a time for scanning one scan line is referred to as one horizontal cycle 1H. The clock signals SCK1, SCK2, and SCK3each have a cycle of 3H and a duty ratio of 1/3, and the phase difference between two neighboring clock signals is 1H. Therefore, during a period when one of the three clock signals SCK1, SCK2, and SCK3has a low voltage, two clock signals have a high voltage.

During the period when the scan driver200sequentially applies the gate-on voltage to the plurality of scan lines S1-Sn, the first control signal SS may have the gate-off voltage. On the other hand, during the period when the scan driver200concurrently (e.g., simultaneously) applies the gate-on voltage to a plurality of scan lines S1-Sn, the first control signal SS and the second control signal SGCK may have the gate-on voltage, and during the period when the scan driver200concurrently (e.g., simultaneously) applies the gate-off voltage to the plurality of scan lines, the first control signal SS and the second control signal SGCK may have the gate-off voltage.

Referring toFIG. 3, each stage, for example the i-th stage STi, includes a sequential switching unit310, a sequential output unit315, a concurrent switching unit320(e.g., a simultaneous switching unit), and a concurrent output unit325(e.g., a simultaneous output unit). They include PMOS (P-channel metal-oxide semiconductor) transistors M1-M11and capacitors C1, C2, and C3. When using the PMOS transistors, the gate-on voltage is a low voltage and the gate-off voltage is a high voltage. Alternatively, the transistors M1-M11may be formed of an NMOS (N-channel metal-oxide semiconductor), and in this case, the gate-on voltage is the high voltage and the gate-off voltage is the low voltage.

The sequential switching unit310includes transistors M1-M4and M10that are connected to the input terminal IN, the high voltage terminal VGHT, the low voltage terminal VGLT, and the clock terminals CK1, CK2, and CK3.

The input terminal IN is connected to the gate of the transistor M1and the drain of the transistor M2. The node QB is connected to the drain of the transistor M1, the gate of the transistor M3, and the source of the transistor M4. The node QA is connected to the source of the transistor M2and the drain of the transistor M3. The sources of the transistors M1, M3, and M10are connected to the high voltage terminal VGHT, and the drain of the transistor M4is connected to the low voltage terminal VGLT. The gate of the transistor M2is connected to the clock terminal CK1, the gate of the transistor M4is connected to the clock terminal CK3, and the gate of the transistor M10is connected to the clock terminal CK2. The drain of the transistor M10is connected to the node QC.

The sequential output unit315is connected to the output terminal OUT to output the scan signal scan[i] to the corresponding scan line Sn in the sequential switching driving. The sequential output unit315includes transistors M7and M8and capacitors C1and C2, and is connected to the high voltage terminal VGHT, the clock terminal CK2, and the output terminal OUT.

The drain of the transistor M7and the source of the transistor M8are connected to the node QD that is connected with the output terminal OUT. The source of the transistor M7is connected to the high voltage terminal VGHT, and the drain of the transistor M8is connected to the clock terminal CK2. The gate of the transistor M7is connected to the node QB, and the gate of the transistor M8is connected between the node QA. Also, the capacitor C1is connected to the gate and the source of the transistor M7, and the capacitor C2is connected between the gate and the source of the transistor M8. The capacitors C1and C2may include a parasitic capacitance between the gate and the source of the transistors M7and M8formed in the manufacturing process.

The concurrent switching unit320includes transistors M5and M6, and is connected to the first control terminal SST, the high voltage terminal VGHT, and the nodes QA and QB. The gates of the transistors M5and M6are commonly connected to the first control terminal SST, and the sources of the transistors M5and M6are connected to the high voltage terminal VGHT. The drain of the transistor M5is connected to the node QB, and the drain of the transistor M6is connected to the node QA.

The concurrent output unit325is connected to the output terminal OUT to output the scan signal scan[i] to the corresponding scan line Sn in the concurrent switching driving. The concurrent output unit325includes transistors M9and M11and a capacitor C3, and is connected to the first control terminal SST and the second control terminal GCK in addition to the output terminal OUT.

The source of the transistor M9is connected to the node QD to which the output terminal OUT is connected. The gate of the transistor M9and the source of the transistor M11are connected to the node QC, and the drain of the transistor M9is connected to the second control terminal GCK. The drain of the transistor M11is connected to the first control terminal SST, and the gate of the transistor M11is connected to the drain for a diode connection (diode-connecting the transistor M11). Also, the capacitor C3is connected between the node QD to which the source of the transistor M9is connected and the node QC to which the gate of the transistor M9is connected.

Next, an operation of the scan driver according to an exemplary embodiment of the present invention will be described with reference toFIG. 4andFIG. 5.

FIG. 4is a signal timing diagram illustrating a sequential switching mode of a scan driver according to an exemplary embodiment of the present invention, andFIG. 5is a signal timing diagram illustrating a concurrent switching mode of a scan driver according to an exemplary embodiment of the present invention.

InFIG. 4andFIG. 5, for better understanding and ease of description, the high level of the clock signal and the high level of the control signal are the same as the high voltage VGH of the high voltage terminal VGHT, and the low levels of the clock signal and the control signal are the same as the low voltage VGL of the low voltage terminal VGLT. Also, the transistors of each stage STiare PMOS transistors such that it is assumed that the transistor is turned off in response to the high level of the clock signal or the control signal, that is, the high voltage, and the transistor is turned on in response to the low level of the clock signal or the control signal, that is, the low voltage.

Firstly, the shift register function of the scan driver200in sequential switching driving of the scan driver200will be described with reference toFIG. 4.

Referring toFIG. 4, the first control signal SS that is maintained as the high level during a sequential switching driving period is transmitted such that the first control terminal SST has the high voltage VGH. Also, the clock terminal CK2, receiving one of the clock signals SCK1, SCK2, and SCK3that are switched with the low level, has the low voltage VGL such that the transistor M10is turned on. Thus, the transistor M10transmits the high voltage VGH to the node QC. The transistors M5, M6, M9, and M11are in the turn-off state in accordance with the first control terminal SST and the transistor M10during the sequential switching driving period. Accordingly, the concurrent switching unit320and the concurrent output unit325, including the transistors M5, M6, M9, and M11, are not operated such that the output of the scan signal of the sequential switching driving period is not affected. Here, the transistor M9is in the turn-off state such that the waveform of the second control signal SGCK that is transmitted to the second control terminal GCK may be any waveform and is not shown inFIG. 4.

During the sequential switching driving period, the scan start signal SSP, having the low voltage VGL during the period T0that is equal to 1H, is applied such that the scan operation is started. In the period T0, the clock signal SCK1has the low voltage VGL, and the clock signals SCK2and SCK3have the high voltage VGH such that the input terminal IN and the clock terminal CK1receive the low voltage and the clock terminals CK2and CK3receive the high voltage in the first stage ST1. Thus, the transistor M2is turned on such that the voltage at the node QA is decreased to the low voltage, and the transistor M1is turned on such that the voltage at the node QB is increased to the high voltage. Accordingly, the transistor M7is turned off and the transistor M8is turned on. Therefore, the output terminal OUT of the first stage ST1, that is, the voltage of the scan signal scan[1], is maintained as the high voltage of the clock terminal CK2, and the capacitor C2stores the voltage corresponding to the difference between the high voltage and the low voltage that are respectively maintained at the source and the gate of the transistor M8.

Next, during the period T1, the clock signal SCK2has the low voltage and the scan start signal SSP has the high voltage. Thus, in the first stage ST1, the clock terminal CK2receives the low voltage, and the input terminal IN and the clock terminals CK1and CK3receive the high voltage. Accordingly, the transistors M1, M2, and M4are turned off such that the node QA and the node QB enters the floating state. Accordingly, the transistor M7is maintained in the turn-off state, and the node QA is at the low voltage such that the transistor M8is maintained in the turn-on state, and thereby the voltage of the output terminal OUT is decreased to the low voltage by the clock terminal CK2. Here, the voltage of the node QA is decreased to a voltage that is lower than the low voltage VGL by a bootstrap effect due to the capacitor C2such that the transistor M8is completely turned on, and thereby the voltage of the output terminal OUT becomes the low voltage VGL. That is, the first stage ST1outputs the scan signal scan[1] having the low voltage VGL, i.e., the gate-on voltage. As described above, the first stage ST1turns on the transistor M8while maintaining the input at the low voltage that is transmitted through the transistor M2at the period T0through the capacitor C2such that the low voltage of the clock signal SCK2may output as the scan signal scan[1].

The scan signal scan[1] and the clock signal SCK2have the low voltage and the clock signals SCK1and SCK3have the high voltage at the period T1, such that the input terminal IN and the clock terminal CK1are at the low voltage and the clock terminals CK2and CK3are at the high voltage in the second stage ST2. Accordingly, the second stage ST2is operated like the first stage ST1in the period T0such that the scan signal scan[2] having the high voltage, that is, the gate-off voltage, is output to the output terminal OUT.

Next, the clock signal SCK3has the low voltage during the period T2such that the clock terminal CK3receives the low voltage in the first stage ST1, and the input terminal IN and the clock terminals CK1and CK2receive the high voltage. Thus, the transistor M4is turned on such that the node QB is decreased to the low voltage and the transistor M7is turned on. Also, the transistor M3is turned on such that the node QA is increased to the high voltage and the transistor M8is turned off. Accordingly, the first stage ST1outputs the scan signal scan[1] having the high voltage to the output terminal OUT by turning on the transistor M7.

In the period T2, the clock signal SCK3has the low voltage and the scan signal scan[1] and the clock signals SCK1and SCK2have the high voltage, such that the second stage ST2is operated like the first stage ST1in the period T1such that the scan signal scan[2] of the low voltage is output to the output terminal OUT by the clock terminal CK2having the low voltage.

Next, the third stage ST3receives the scan signal scan[2] of the low voltage from the input terminal IN and is operated like the first stage ST1in the period T0by the clock terminal CK1of the low voltage and the clock terminals CK2and CK3of the high voltage to output the scan signal scan[3] of the high voltage.

Then, the clock signal SCK1has the low voltage during the period T3such that the clock terminal CK1receives the low voltage in the first stage ST1, and the input terminal IN and the clock terminals CK2and CK3receive the high voltage. Thus, the transistor M2is turned on such that the node QA maintains the high voltage and the transistor M8maintains the turn-off state. The transistors M1and M4are turned off such that the node QB is in the floated state and the transistor M7maintains the turn-on state. Accordingly, the first stage ST1outputs the scan signal scan[1] of the high voltage to the output terminal OUT. That is, the first stage ST1turns on the transistor M7after the period T2such that the scan signal scan[1] of the high voltage may be output.

The clock signal SCK1has the low voltage and the scan signal scan[1] has the high voltage at the period T3, such that the second stage ST2is operated like the first stage ST1in the period T2to output the scan signal scan[2] of the high voltage. Accordingly, the third stage ST3is operated like the first stage ST1in the period T1with the input terminal IN at the high voltage and the clock terminal CK2at the low voltage such that the scan signal scan[3] of the low voltage is output.

As described above, the clock terminal CK2connected to the transistor M10has the low voltage and the first control terminal SST has the high voltage in the state before the start of the sequential switching driving, and the scan driver200may sequentially output the low voltage, that is, the scan signals scan[1]-scan[n] having the gate-on voltage, to a plurality of scan lines S1-Sn in response to the low voltage waveform of the clock signals SCK1, SCK2, and SCK3.

The sequential switching driving of the scan driver200according to an exemplary embodiment of the present invention is not limited to the exemplary embodiment ofFIG. 4, and may be equally applied to overlapping driving by expanding the number of clock signals to six clock signals and the width of each clock signal to 2H.

Next, a concurrent switching operation of the scan driver200will be described with reference toFIG. 5.

Referring toFIG. 5, the clock signals SCK1, SCK2, and SCK3and the scan start signal SSP have the high voltage during the concurrent switching period. Thus, the transistors M1, M2, M4, and M10are turned off.

In the state that the first control signal SS is maintained as the low voltage, when the second control signal SGCK is changed into the low level, a concurrent-on period Ton is started in the concurrent switching period.

When the first control signal SS is maintained as the low voltage, the first control terminal SST has the low voltage in a plurality of stages ST1-STn such that the transistors M5, M6, and M11are turned on.

Accordingly, the voltages at the nodes QA and QB are increased to the high voltage and the voltage at the node QC is decreased to the low voltage. The transistors M7and M8are turned off by the high voltage at the nodes QA and QB such that the output by the transistors M7and M8is prevented. During the concurrent switching period, the sequential switching driver310and the sequential output unit315of each stage of the scan driver200are not operated.

Here, the transistor M9is turned on by the low voltage at the node QC such that the voltage of the output terminal OUT is decreased to the low voltage at the second control terminal GCK during the concurrent-on period Ton. Here, the voltage of the node QC is decreased to a lower voltage than the low voltage VGL by a bootstrap effect due to the capacitor C3, and the transistor M9is completely and stably turned on such that the voltage of the output terminal OUT becomes the low voltage VGL. The more detailed description of the driving waveforms corresponding to the5A section ofFIG. 5will be given with reference toFIG. 6below.

By this operation, the plurality of stages ST1-STn output the low voltage, that is, the scan signals scan[1]-scan[n] having the gate-on voltage, to a plurality of scan lines S1-Sn, such that the transistors of the pixels PX having the gate connected to the scan lines S1-Sn may all be turned on.

Next, the second control signal SGCK has the high voltage in the state that the first control signal SS still maintains the low voltage in a concurrent-off period Toff in the concurrent switching period.

Thus, in the plurality of stages ST1-STn, the voltage of the output terminal OUT is output as the high voltage of the second control signal SGCK that is transmitted to the second control terminal GCK when the transistors M9and M11are still turned on. Accordingly, the plurality of stages ST1-STn output the high voltage, that is, the scan signals scan[1]-scan[n] having the gate-off voltage, to the plurality of scan lines S1-Sn such that the transistors, having the gate connected to the scan lines S1-Sn, are all turned off.

FIG. 6is a view illustrating the voltage levels of the driving waveforms5A shown inFIG. 5in more detail, and is based on the circuit diagram of the concurrent output unit325of the scan driver200, to stably execute the concurrent on/off driving in the concurrent switching period.

In general, the transistor connected to the output terminal of the scan driver is turned on by the very small voltage Vgs between the gate and the source of the transistor when the output signal (e.g., the scan signal) is changed from the high level to the low level. The reason is that the speed at which the gate voltage is decreased by the voltage of the signal input to the gate terminal of the transistor is similar to the speed at which the source voltage is decreased by the terminal voltage connected to the drain terminal of the transistor. That is, the voltage waveform of the gate terminal of the transistor and the waveform of the output signal of the output terminal connected the source terminal of the transistor are almost concurrently (e.g., simultaneously) changed from the high level to the low level such that the voltage Vgs between the gate and the source of the transistor is not large at the time the capacitor connected between the gate and the source of the transistor starts to bootstrap.

Accordingly, for driving a panel load connected to the output terminal, the transistor is driven by the small voltage Vgs between the gate and the source such that the on resistance gets larger, and a drawback is that the change to the low level from the high level of the scan signal output from the output terminal becomes slow.

To solve this problem, the circuit structure of the concurrent output unit325of the scan driver200, according to an exemplary embodiment of the present invention that was previously explained inFIG. 3, is used, and the driving waveforms of the concurrent (e.g., simultaneous) conversion from the high level to the low level for the scan signal and the output thereof are shown inFIG. 6.

Before the time t0, the voltage of the node QC and the output signals of the plurality of stages ST1-STn, that is, the plurality of scan signals scan[1]-scan[n], maintain the high voltage VGH. The scan signals scan[1]-scan[n] are converted and output from the high voltage to the low voltage VGL during the concurrent-on period Ton, and in more detail, they start to be converted into the low voltage state at the time t2and start to be converted into the high voltage state at the time t4inFIG. 6.

When the first control signal SS is changed from the high voltage to the low voltage and is transmitted to the first control terminal SST at the time t0, the transistor M11is turned on such that the voltage of the node QC starts to be decreased to the low voltage VGL.

Next, when the voltage of the node QC is decreased to the voltage of the level that is higher than the gate node voltage (i.e., the low voltage VGL of the first control signal SS) of the transistor M11at the time t1by the threshold voltage (|Vth (M11)|) of the transistor M11, the transistor M11is turned off such that the voltage of the node QC is almost constantly or substantially maintained. The voltage of the node QC is reduced to the low level and maintained by the transistor M11from the time t0to the time t2such that the transistor M9is turned on, however the second control terminal GCK that is connected to the drain of the transistor M9is in the high voltage state such that the plurality of scan signals scan[1]-scan[n] are still in the high voltage state.

When the second control signal SGCK starts to be changed into the low level at the time t2, the voltage at the second control terminal GCK is decreased to the low voltage and the transistor M9is turned on such that the plurality of scan signals scan[1]-scan[n] are concurrently, (e.g., simultaneously) decreased to the low voltage. Here, the voltage change amount of the scan signals scan[1]-scan[n] is substantially reflected in the voltage change amount of the node QC by the coupling effect of the capacitor C3. Accordingly, in the timing diagram ofFIG. 6, it is shown that the waveforms of the scan signals scan[1]-scan[n] and the waveform of the node QC is substantially the same during the period between the time t2and the time t3.

When the second control signal SGCK and the scan signals scan[1]-scan[n] reach the level of the low voltage VGL at the time t3, the voltage of the node QC becomes “2VGL−VGH+|Vth (M11)|” that is a much lower value than the low voltage VGL. For concurrently (e.g., simultaneously) outputting the scan signals scan[1]-scan[n] of the low voltage VGL to the output terminal OUT, the voltage of the node QC, as the gate voltage of the transistor M9that is connected to the output terminal OUT, is driven sufficiently lower than the low voltage VGL as the source voltage of the transistor M9such that the voltage between the gate and the source of the transistor M9is sufficiently large. That is, the voltage between the gate and the source of the transistor M9at the time t3is the voltage difference ΔV between the low voltage VGL of the scan signals scan[1]-scan[n] and the voltage “2VGL−VGH+|Vth (M11)|” of the node QC, and the voltage difference ΔV is as shown in Equation 1.
ΔV=VGH−VGL−|Vth(M11)|  Equation 1

Accordingly, the voltage difference ΔV is a substantially large value such that the on resistance of the transistor M9is small, and thereby the voltage of the scan signals scan[1]-scan[n] may be quickly changed from the high level to the low level for driving the large panel load by a transistor of a small size.

When the second control signal SGCK is increased to the high voltage from the time t4, the transistor M9is still in the turn-on state such that the voltages of the scan signals scan[1]-scan[n] are increased to the high voltage. That is, the transistor M9passes the waveform of the second control signal SGCK, which is at the high voltage as in the time t0, as the plurality of scan signals scan[1]-scan[n]. Likewise, the change amount that the voltage of the scan signals scan[1]-scan[n] is changed into the high voltage by the capacitor C3is reflected by the voltage change amount of the node QC such that the voltage of the node QC is increased. Next, when the second control signal SGCK becomes the high voltage VGH at the time t5, the plurality of scan signals scan[1]-scan[n] have the high voltage VGH such that the concurrent-off period Toff is started. Although not shown inFIG. 6, when the first control signal SS is changed into the high level and the clock terminal CK2has the low voltage by the clock signal including the low voltage waveform, the voltage of the node QC becomes the high voltage VGH, and then the transistor M9is turned off.

FIG. 7is a circuit diagram of one stage of the scan driver200according to another exemplary embodiment of the present invention.

Referring toFIG. 7, different from the stage STi ofFIG. 3, the gate of the transistor M11is connected to the first control terminal SST in each stage STia, and the drain of the transistor M11is connected to the low voltage terminal VGLT. In the exemplary embodiment ofFIG. 3, when the first control terminal SST receives the low voltage, the transistor M11is turned on such that the voltage of the node QC becomes the low voltage. However, in the exemplary embodiment ofFIG. 7, when the first control terminal SST receives the low voltage, the transistor M11is turned on and the low voltage VGL is applied from the low voltage terminal VGLT, to which the drain of the transistor M11is connected, such that the voltage of the node QC becomes the low voltage. In the exemplary embodiment ofFIG. 7, the driving operation and the driving waveforms of the remaining circuit elements are substantially the same as described above such that the description of the driving operation is omitted.

FIG. 8is a block diagram of a scan driver200aaccording to another exemplary embodiment of the present invention.FIG. 9is a circuit diagram of one stage of the scan driver200ashown inFIG. 8.FIG. 10is a signal timing diagram illustrating the sequential switching driving of the scan driver200ashown inFIG. 8.FIG. 11is a signal timing diagram illustrating the concurrent switching driving of the scan driver200ashown inFIG. 8.

Referring toFIG. 8, the scan driver200aincludes a plurality of stages ST1b-STnb that receive the high voltage VGH, the low voltage VGL, the three clock signals SCK1, SCK2, and SCK3, at least one control signal, and the scan start signal SSP. The clock signals SCK1, SCK2, and SCK3each have a cycle period of 3H and a duty ratio of 1/3, and the phase difference of two neighboring clock signals is 1H, like the exemplary embodiment ofFIG. 2. However, the present invention is not limited to this driving method. For example, six clock signals may be included, and the cycle period of the clock signal may be expanded to 6H such that the phase difference between the clock signals may be driven to be overlapped by 1H.

In the exemplary embodiment ofFIG. 8, the control signal may include the first control signal SS, the second control signal SGCK, and a third control signal SR.

Each stage STib has substantially the same structure as the stage STi shown inFIG. 2. However, each stage STib may include a third control terminal SRT to receive the third control signal SR.

InFIG. 8, the input process in which the clock signals SCK1, SCK2, and SCK3are alternately and respectively input to the clock terminals CK1, CK2, and CK3of the plurality of stages ST1b-STnb is substantially the same as that ofFIG. 2such that the description thereof is omitted.

FIG. 9is a circuit diagram of an i-th stage STib among the plurality of stages ST1b-STnb shown inFIG. 8, and it has a circuitry similar to that ofFIG. 3.

Referring toFIG. 9, each stage, for example the i-th stage STib, includes a sequential switching unit310b, a sequential output unit315b, a concurrent switching unit320b(e.g., a simultaneous switching unit), and a concurrent output unit325b(e.g., a simultaneous output unit).

However, in each stage as illustrated inFIG. 9, the gate of the transistor M10is not connected to the clock terminal CK2, but is connected to the third control terminal SRT.

Accordingly, the transistor M10is turned on/off by the third control signal SR that is received by the third control terminal SRT. That is, in the sequential switching driving of the scan driver200a, the third control signal SR is maintained as the low voltage, and in the concurrent switching driving, the third control signal SR is maintained as the high voltage such that the operation of the scan driver200ais controlled.

The waveform diagram for performing the sequential switching by using the circuit of each stage ofFIG. 9is shown inFIG. 10, and the waveform diagram for performing the concurrent switching is shown inFIG. 11.

The sequential switching driving and the concurrent switching driving according to the exemplary embodiment ofFIG. 10andFIG. 11are substantially the same as shown in the driving method ofFIG. 4andFIG. 5.

However, according to the exemplary embodiment ofFIG. 10, the third control signal SR is maintained as the low level, such that the third control terminal SRT receives the low voltage and the transistor M10is turned on. Thus, the voltage of the node QC is maintained as the high voltage VGH by the transistor M10such that the concurrent output unit325bis not operated during the sequential switching period. In the exemplary embodiment ofFIG. 3andFIG. 4, the clock signals, transmitted to the clock terminal CK2that is connected to the gate of the transistor M10, are refreshed during about 1H period one by one every 3H period to maintain the node QC as the high voltage. However, in the exemplary embodiment ofFIG. 9andFIG. 10, the node QC is always maintained as the high voltage by the third control signal SR such that the sequential switching driving may be more stable.

Here, according to the exemplary embodiment ofFIG. 11, the third control signal SR is maintained as the high level to turn off the transistor M10such that the concurrent switching like the driving method ofFIG. 5is executed.

FIG. 12is an enlarged view of a portion11A in the signal timing diagram shown inFIG. 11, and shows a plurality of scan signals scan[1]-scan[n] that are concurrently (e.g., simultaneously) changed to the low voltage or the high voltage and are output according to the waveform of the second control signal SGCK in the stage in which the third control signal SR is maintained as the high voltage VGH during the concurrent switching period. The detailed description of the driving waveforms ofFIG. 12is substantially the same as that given forFIG. 6such that it is omitted here.

FIG. 13is a circuit diagram of one stage STic of the scan driver200according to another exemplary embodiment of the present invention.

Referring toFIG. 13, the stage STic is similar to the circuit structure of the stage STib ofFIG. 9, but the gate of the transistor M11is connected to the first control terminal SST in each stage STic, and the drain of the transistor M11is connected to the low voltage terminal VGLT. Accordingly, in the exemplary embodiment ofFIG. 9, when the first control terminal SST receives the low voltage, the transistor M11is turned on such that the voltage of the node QC becomes the low voltage. However, in the exemplary embodiment ofFIG. 13, when the first control terminal SST receives the low voltage, the transistor M11is turned on, and the low voltage VGL is applied from the low voltage terminal VGLT to which the drain of the transistor M11is connected such that the same function is executed. The driving waveforms according to the exemplary embodiment ofFIG. 13are substantially the same as those ofFIG. 9.

According to other exemplary embodiments,FIG. 14toFIG. 17are circuit diagrams in which the transistors shown in the exemplary embodiments ofFIG. 3,FIG. 7,FIG. 9, andFIG. 13are changed from PMOS transistors to the NMOS transistors.

The driving method of the sequential switching or the concurrent switching according to the configuration of the circuit diagrams ofFIG. 14toFIG. 17is substantially the same as described above. However, the voltage level of the signals for operating the NMOS transistors are opposite to those for operating the PMOS transistors.