Semiconductor devices having dielectric caps on contacts and related fabrication methods

Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure involves forming a first layer of a first dielectric material overlying a doped region formed in a semiconductor substrate, forming a first conductive contact electrically connected to the doped region within the first layer, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and a gate structure overlying the semiconductor substrate, and forming a second conductive contact electrically connected to the gate structure within the second layer.

TECHNICAL FIELD

Embodiments of the subject matter generally relate to semiconductor devices and to device fabrication methods, and more particularly, relate to devices and to fabrication methods for forming contacts between devices formed on a semiconductor substrate and overlying layers.

BACKGROUND

Transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), are the core building block of the vast majority of semiconductor devices. Some semiconductor devices, such as high performance processor devices, can include millions of transistors. For such devices, decreasing transistors size, and thus increasing transistor density, has traditionally been a high priority in the semiconductor manufacturing industry. As the size and spacing of the transistors decrease, it is more difficult to avoid inadvertent creation of electrical connections between adjacent devices, which, in turn, reduces yield.

BRIEF SUMMARY

A method is provided for fabricating a semiconductor device structure. The semiconductor device includes a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure. The method involves forming a first layer of a first dielectric material overlying the doped region, forming a first conductive contact electrically connected to the doped region within the first layer, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and the gate structure, and forming a second conductive contact electrically connected to the gate structure within the second layer.

In another embodiment, a method of fabricating a semiconductor device structure involves forming a first layer of a first dielectric material overlying a doped region formed in a semiconductor substrate, removing portions of the first layer to form a first voided region overlying the doped region. forming a first conductive contact electrically connected to the doped region in the first voided region, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and a gate structure formed on the semiconductor substrate, removing portions of the second layer overlying the gate structure to form a second voided region exposing the gate structure while leaving the dielectric cap intact, and forming a second conductive contact electrically connected to the gate structure in the second voided region.

In yet another embodiment, an apparatus for a semiconductor device is provided. The semiconductor device structure includes a substrate of a semiconductor material, a gate structure overlying the substrate, a doped region formed in the substrate proximate the gate structure, a first dielectric material overlying the doped region, a first conductive contact electrically connected to the doped region formed in the first dielectric material, and a dielectric cap overlying the first conductive contact.

DETAILED DESCRIPTION

FIGS. 1-10illustrate a semiconductor device structure100and related process steps for fabricating the semiconductor device structure100with conductive electrical contacts to doped source/drain regions formed in a semiconductor substrate. Although the subject matter may be described herein in the context of a MOS semiconductor device, the subject matter is not intended to be limited to MOS semiconductor devices, and may be utilized with other semiconductor devices which are not MOS semiconductor devices. Additionally, although the term “MOS device” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term will be used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or other conductive material) that is positioned over a gate insulator (whether oxide or other insulator) which, in turn, is positioned over a semiconductor substrate. Various steps in the fabrication of MOS semiconductor devices are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details.

Referring now toFIG. 1, the fabrication process begins after front end of line (FEOL) processing steps are performed to fabricate a semiconductor device structure100that includes a plurality of transistor structures104,106,108formed on a substrate of a semiconductive material102, such as monocrystalline silicon or another silicon-comprising material, in a conventional manner. In an exemplary embodiment, the semiconductor material102is doped in a conventional manner to achieve a desired dopant profile for the body regions (or well regions) of the transistor structures104,106,108.

As illustrated inFIG. 1, each transistor structure104,106,108includes a gate structure110,112,114overlying the semiconductor substrate102that functions as a gate electrode for the respective transistor structure104,106,108. The gate structures110,112,114can be created using a conventional gate stack module or any combination of well-known process steps. In practice, each gate structure110,112,114typically includes at least one layer of dielectric material116(e.g., an oxide material, high-k dielectric material, or the like) overlying the semiconductor substrate102, and at least one layer of conductive material118(e.g., a metal material, a polysilicon material, or the like) overlying the dielectric material116. It should be understood that various numbers, combinations and/or arrangements of materials may be utilized for the gate structures in a practical embodiment, and the subject matter described herein is not limited to any particular number, combination, or arrangement of gate material(s) in the gate structure. Additionally, the subject matter is not intended to be limited to any particular number of gate structures.

Each transistor structure104,106,108also includes spaced-apart doped regions120,122,124,126formed in the semiconductor substrate102adjacent to its respective gate structure110,112,114that function as source/drain regions for the respective transistor structures104,106,108. Accordingly, for convenience, but without limitation, the doped regions120,122,124,126are alternately referred to herein as source/drain regions. For example, P-type source/drain regions for PMOS transistor structures may be formed by implanting P-type ions into the semiconductor material102using the gate structures110,112,114as an implantation mask, or alternatively, N-type source/drain regions for NMOS transistor structures may be formed by implanting N-type ions into the semiconductor material102using the gate structures110,112,114as an implantation mask.

It will be appreciated that althoughFIG. 1depicts the source/drain regions as being integrally formed with or otherwise contiguous with source/drain regions of adjacent transistor structures for purposes of illustration, the subject matter is not intended to be limited to any particular arrangement of the source/drain regions. For example, in practice, the transistor structures may be electrically isolated (e.g., by performing shallow trench isolation (STI) or another isolation process) and independently doped in a conventional manner.

Still referring toFIG. 1, in an exemplary embodiment, the fabrication process continues by forming a dielectric material128between neighboring gate structures110,112,114and overlying the doped regions120,122,124,126. In an exemplary embodiment, the dielectric material128is formed by conformably depositing a layer of the dielectric material128, such as silicon dioxide or another oxide material, overlying the gate structures110,112,114and the doped regions120,122,124,126by chemical vapor deposition (CVD) or another deposition process. The thickness of the layer of dielectric material128is chosen such that the dielectric material128completely fills any gaps between the gate structures110,112,114to a minimum height that meets or exceeds the height of the gate structures110,112,114, or in other words, the thickness of the dielectric material128is greater than or equal to the height of the gate structures110,112,114.

After forming the layer of dielectric material128, the fabrication process continues by removing portions of the dielectric material128overlying the gate structures110,112,114to obtain a substantially planar surface130that is aligned with the upper surface of the gate structures110,112,114, resulting in the device structure100illustrated byFIG. 1. In an exemplary embodiment, the fabrication process planarizes the layer of dielectric material128to uniformly remove portions of the dielectric material128across the semiconductor substrate until reaching the conductive gate material118of the gate structures110,112,114. In other words, the fabrication process ceases planarizing the dielectric material128when the upper surfaces of the gate structures110,112,114are exposed. In accordance with one embodiment, chemical-mechanical planarization (CMP) is used to polish the dielectric material128with a chemical slurry for a predetermined amount of time based on the thicknesses of the dielectric material128such that the CMP stops when the upper surfaces of the gate structures110,112,114are exposed. Alternative endpoint detection techniques could also be utilized to determine when to stop the CMP procedure, or alternative planarization techniques may be used to obtain the substantially planar surface130that is aligned with the upper surfaces of the gate structures110,112,114.

Turning now toFIG. 2, in an exemplary embodiment, after forming the dielectric material128between the gate structures110,112,114, the fabrication process continues by forming a layer of dielectric material132overlying the gate structures110,112,114and the dielectric material128. In an exemplary embodiment, the dielectric material132is realized as a hard mask material, such as silicon nitride or the like, that is conformably deposited overlying the planar surface130of the semiconductor device structure100ofFIG. 1. For convenience, but without limitation, the dielectric material132is alternatively referred to herein as a hard mask material. As described in greater detail below in the context ofFIGS. 11-14, in accordance with one or more embodiments, prior to forming the hard mask material132, a dielectric gate capping material is formed on the conductive gate material118. For example, the dielectric gate capping material may be realized as an oxide material formed by oxidizing the conductive gate material118(e.g., by thermal oxidation or chemical oxidation).

Turning now toFIGS. 3-4, after forming the hard mask material132, the fabrication process continues by selectively removing portions of the dielectric material128and hard mask material132overlying the source/drain regions120,122,124,126to create voided regions136,138,140overlying the source/drain regions120,122,124,126and forming conductive contacts142,144,146in the voided regions136,138,140. The source/drain contacts142,144,146are realized as a conductive material148that provides an electrical connection to source/drain regions120,122,124,126, wherein the voided regions136,138,140define the lateral dimensions of the source/drain contacts142,144,146subsequently formed therein. In some embodiments, the voided regions136,138,140also correspond to the pattern, routing and/or intralayer interconnections to be provided by the source/drain contacts142,144,146. In this regard, in addition to providing vertical interconnections to overlying contact layers and/or metal layers, the source/drain contacts142,144,146may also provide lateral intralayer interconnections (alternatively referred to as local interconnects) between source/drain regions of different transistor structures. For convenience, but without limitation, the source/drain contacts142,144,146may alternatively be referred to herein as lower level source/drain contacts.

Referring toFIG. 3, in an exemplary embodiment, the fabrication process forms a layer of masking material, such as a photoresist material, overlying the semiconductor device structure100ofFIG. 2and removes portions of the masking material (e.g., using photolithography or a suitable etchant chemistry) to create an etch mask that defines the pattern for the conductive material148of the lower level source/drain contacts142,144,146. In this regard, portions of the hard mask material132overlying the source/drain regions120,122,124,126that will subsequently be removed to create the voided regions136,138,140are exposed by the etch mask. The portions of the dielectric material128adjacent to the gate structures110,112,114are protected by the masking material to electrically isolate the subsequently formed contacts142,144,146from adjacent gate structures110,112,114. After patterning the masking material, the fabrication process continues by selectively removing exposed portions of the dielectric materials128,132using the patterned masking material as an etch mask. In an exemplary embodiment, the exposed portions of dielectric materials128,132are removed using an anisotropic (or directional) etch process that stops on the semiconductor material102, for example, by plasma-based reactive ion etching (RIE) using an anisotropic etchant chemistry. After removing exposed portions of the dielectric materials128,132to form the voided regions136,138,140, the fabrication process continues by removing any remaining masking material in a conventional manner to obtain the semiconductor device structure100illustrated inFIG. 3.

Referring toFIG. 4, after creating voided regions136,138,140, the fabrication process continues by forming contacts142,144,146in the voided regions136,138,140. In the illustrated embodiment, prior to forming the conductive material148, metal silicide contact regions150,152,154are formed on the exposed upper surfaces of the source/drain regions120,122,124in a conventional manner to facilitate forming electrical connections to the source/drain regions120,122,124. After forming the silicide contact regions150,152,152, the lower level source/drain contacts142,144,146are preferably formed by conformably depositing a layer of conductive material148, such as a tungsten material, by CVD or another deposition process to a thickness chosen such that the conductive material148fills the voided regions136,138,140to a minimum height that meets or exceeds the height of the gate structures110,112,114combined with the thickness of the hard mask material132(e.g., a “flush” fill or overfill). As illustrated, the conductive material148completely fills the voided regions136,138,140and contacts the contact regions150,152,154to provide a conductive electrical connection to the source/drain regions120,122,124,126. Although not illustrated, it should be noted that in some embodiments, a relatively thin layer of a barrier material may be formed in the voided regions136,138,140prior to forming the layer of conductive material148.

After forming the layer of conductive material148, the fabrication process continues by planarizing the semiconductor device structure100to remove portions of the conductive material148overlying the hard mask material132to obtain a substantially planar surface156that is aligned with the upper surface of the hard mask material132, resulting in the semiconductor device structure100ofFIG. 4. In this regard, the conductive material148is uniformly removed across the semiconductor device structure100until reaching hard mask material132, for example, by performing CMP to polish the conductive material148with a chemical slurry and stopping when the upper surfaces of the hard mask material132are exposed, in a similar manner as described above.

Turning now toFIG. 5, in the illustrated embodiment, the fabrication process continues by forming dielectric caps on the lower level source/drain contacts142,144,146. In accordance with one embodiment, a dielectric capping material160is formed on the lower level source/drain contacts142,144,146by oxidizing the exposed surfaces of the conductive material148(e.g., by thermal oxidation or chemical oxidation) to form the oxide capping material160from the upper surface of the lower level source/drain contacts142,144,146. In this regard, oxidizing the conductive material148to grow the oxide capping material160on the exposed surfaces of the conductive material148consumes the exposed conductive material148, such that the upper surfaces of the oxide capping material160are maintained substantially aligned with the upper surfaces of the remaining hard mask material132overlying the gate structures110,112,114after the oxide capping material160is grown. In an exemplary embodiment, the oxide capping material160is grown to a thickness that is greater than or equal to the thickness of the hard mask material132so the underlying conductive material148is not inadvertently exposed during subsequent etch process steps, as described in greater detail below. In other words, after oxidation, the upper surface of the conductive material148(e.g., the interface with the oxide capping material160) is below the upper surface of the conductive gate material118. It should be noted that in alternative embodiments, if the oxidation rate of the conductive material148is not sufficient (or too low) to result in the upper surface of the conductive material148being below the upper surface of the conductive gate material118, the conductive material148may be deposited to a thickness that is less than the height of the conductive gate material118, and a second conductive material having a greater oxidation rate may be deposited overlying the conductive material148prior to the planarization step, wherein the second conductive material is then oxidized to provide the oxide capping material160with a thickness that is greater than or equal to the thickness of the hard mask material132.

Still referring toFIG. 5, in accordance with one or more alternative embodiments, the dielectric capping material160is realized as a hard mask material or another dielectric material formed on the lower level source/drain contacts142,144,146, for example, if oxide material formed by oxidizing the conductive material148does not provide the desired amount of isolation and/or the desired amount of etch selectivity for subsequent process steps. In this regard, after planarizing and oxidizing the conductive material148, oxide material overlying the conductive material148is removed using an anisotropic etchant chemistry that is selective to oxide material without attacking the hard mask material132, such that the hard mask material132overlying the gate structure110remains intact while at least some of (if not all of) the oxide material is removed from the conductive material148. After removing oxide material from the conductive material148, the dielectric caps are formed by conformably depositing the dielectric capping material160, such as a hard mask material or another suitable dielectric material, overlying the hard mask material132and the conductive material148to a thickness that is greater than the difference between the upper surfaces of the hard mask material132and the upper surfaces of the conductive material148to fill any voided regions above the conductive material148to a minimum height that meets or exceeds the hard mask material132on top of the gate structures110,112,114. After forming the layer of dielectric capping material160, the dielectric capping material160is planarized to obtain a substantially planar surface resulting in the semiconductor device structure100ofFIG. 5. Preferably, the dielectric capping material160is different from the hard mask material132to allow the hard mask material132to be selectively etched while the dielectric capping material160remains intact, and vice versa, as described in greater detail below.

Referring now toFIGS. 6-8, after forming the capping material160, the fabrication process continues by forming a contact layer overlying the semiconductor substrate that includes one or more source/drain contacts165,167. The source/drain contacts165,167in the contact layer provide vertical interconnections between the lower level source/drain contacts142,144and a metal interconnect layer (e.g., Metal 1) subsequently formed overlying the substrate. Additionally, the source/drain contacts165,167may provide a lateral intralayer interconnection between lower level source/drain contacts142,144(e.g., on another regions of the semiconductor substrate) and/or subsequently formed gate contacts. For convenience, but without limitation, the source/drain contacts165,167formed in the contact layer may alternatively be referred to herein as upper level source/drain contacts because they are formed in a dielectric layer overlying the dielectric layer(s) that the lower level source/drain contacts142,144,146are formed in.

Referring toFIG. 6, in an exemplary embodiment, the fabrication of the contact layer begins by conformably depositing a layer of a dielectric material162, such as an oxide material, overlying the device structure100ofFIG. 5, resulting in the device structure100illustrated byFIG. 6. For convenience, but without limitation, the dielectric material162may alternatively be referred to herein as an oxide material. After forming the dielectric material162, the fabrication process continues by selectively removing portions of the dielectric material162to create voided regions163,164in the dielectric material162that correspond to the lateral pattern, routing and/or interlayer interconnections to be provided by the upper level source/drain contacts165,167. For example, a layer of a masking material (e.g., a photoresist material or the like) may be formed overlying the dielectric material162, and portions of the masking material may be subsequently removed (e.g., using photolithography or a suitable etchant chemistry) to define the pattern for the upper level source/drain contacts165,167. In an exemplary embodiment, the mask exposes at least a portion of the dielectric material162overlying one or more of the lower level source/drain contacts142,144such that at least a portion of the subsequently formed voided regions163,164overlies or overlaps a lower level source/drain contacts142,144to provide a conduit for the conductive material166of the upper level source/drain contacts165,167to contact the lower level source/drain contacts142,144.

Referring toFIG. 7, after patterning the masking material to create the etch mask, the exposed portions of the dielectric materials160,162are selectively removed using an anisotropic etchant that removes the exposed portions of the dielectric material162until surfaces of the conductive material148of the lower level source/drain contacts142,144are exposed. For example, when the dielectric materials160,162are both oxides, exposed portions of dielectric materials160,162may be removed using an anisotropic etch process, such as plasma-based RIE, with an anisotropic etchant chemistry that is selective to oxide material160,162without attacking the hard mask material132, such that the hard mask material132overlying the gate structure110remains intact. After exposing the conductive material148of the lower level source/drain contacts142,144, any remaining masking material is removed in a conventional manner to obtain the semiconductor device structure100illustrated inFIG. 7. In the illustrated embodiment, exposed portions of dielectric material162overlying the gate structure110between lower level source/drain contacts142,144is also removed, such that the voided region164overlies or overlaps at least a portion of the gate structure110. AlthoughFIG. 7depicts the dielectric material162overlying the contact146as remaining intact, it should be noted that contacts to contact146may be formed within the dielectric material162at another location on the semiconductor substrate.

Referring now toFIG. 8, the fabrication of the upper level source/drain contacts165,167within the layer of dielectric material162continues by forming a conductive material166in the voided regions163,164. In an exemplary embodiment, the conductive material166is formed by conformably depositing a conductive metal material, such as a tungsten material, overlying the semiconductor substrate102to a thickness chosen such that the conductive material166fills the voided regions163,164to a minimum height that meets or exceeds the height of the intralayer dielectric material162. As illustrated inFIG. 8, the conductive material166contacts the previously exposed upper surfaces of the lower level source/drain contacts142,144to provide an electrical interconnection to the underlying source/drain regions120,122via the lower level source/drain contacts142,144. As illustrated, the hard mask material132overlying the gate structure110remains intact and isolates the conductive material166of the source/drain contact167from the gate structure110. After forming the conductive material166, the fabrication process continues by planarizing the conductive material166to uniformly remove portions of the conductive material166across the semiconductor substrate until reaching the dielectric material162to obtain a substantially planar surface168that is aligned with the upper surface of the dielectric material162.

Turning now toFIGS. 9-10, after forming the upper level source/drain contacts165,167, the fabrication process continues by forming one or more conductive gate contacts176that provide vertical interconnections between one or more of the gate structures110,112,114and a metal interconnect layer (e.g., Metal 1) subsequently formed overlying the substrate. Additionally, in the illustrated embodiment ofFIG. 10, the gate contact176also provides lateral interconnections between gate structures112,114.

Referring toFIG. 9, after planarizing the conductive material166, the fabrication process continues by selectively removing portions of the dielectric material162to create one or more voided regions170in the dielectric material162that correspond to the lateral pattern, routing and/or interlayer interconnections to be provided by the gate contacts176. As described above, a layer of a masking material is formed overlying the dielectric material162and portions of the masking material are removed to define the pattern for the gate contacts176. In an exemplary embodiment, the mask exposes at least a portion of the dielectric material162overlying one or more of the gate structures112,114such that at least a portion of the subsequently formed voided region170overlies or overlaps the gate structures112,114to provide a conduit for the conductive material172of the gate contacts176to contact the gate structures112,114. In the illustrated embodiment, the dielectric material162overlying the lower level source/drain contact146between gate structures112,114is also removed, such that the voided region170overlies or overlaps the lower level source/drain contact146to allow the gate contacts176to provide a lateral interconnection spanning across the lower level source/drain contact146. After patterning the masking material to create the etch mask, the exposed portions of the dielectric material162are selectively removed using an anisotropic etchant that removes the exposed portions of the dielectric material162until surfaces of the hard mask material132are exposed. In this regard, the exposed portions of dielectric material162are anisotropically etched using an anisotropic etchant chemistry that is selective to the dielectric material162without attacking the hard mask material132, such that the hard mask material132acts as an etch stop. After exposing the hard mask material132, a second anisotropic etch process is performed to selectively remove the hard mask material132using an anisotropic etchant chemistry that is selective to the hard mask material132without attacking the capping material160, resulting in the semiconductor device structure100illustrated inFIG. 9. It should be noted that in embodiments where a dielectric gate capping material is formed on the conductive gate material118, a third anisotropic etch process may be performed to selectively remove the dielectric gate capping material using an anisotropic etchant chemistry that is preferably selective to dielectric gate capping material to expose the conductive gate material118while at least a portion of the dielectric capping material160remains intact.

Referring now toFIG. 10, the fabrication of the gate contacts176continues by forming a conductive material172in the voided region170. In an exemplary embodiment, the conductive material172is formed by conformably depositing a conductive metal material, such as a tungsten material, overlying the semiconductor substrate102to a thickness chosen such that the conductive material172fills the voided region170to a minimum height that meets or exceeds the height of the intralayer dielectric material162. As illustrated inFIG. 10, the conductive material172contacts the conductive gate material118to provide an electrical interconnection to the gate structures112,114. Additionally, in the illustrated embodiment, the conductive material172provides lateral interconnections between gate structures112,114by spanning over the lower level source/drain contact146while the capping material160overlying the contact146remains intact and provides a dielectric cap that isolates the conductive material172of the gate contact176from the conductive material148of the contact146. After forming the conductive material172, the fabrication process continues by planarizing the conductive material172to uniformly remove portions of the conductive material172across the semiconductor substrate until reaching the dielectric material162to obtain a substantially planar surface174that is aligned with the upper surface of the dielectric material162. After forming the gate contacts, the fabrication process may continue by performing well known back end of line (BEOL) process steps to complete fabrication of the semiconductor device structure100in a conventional manner. For example, the fabrication process may proceed by forming an interlayer dielectric material overlying the planar surface174, forming vias in the interlayer dielectric material, and forming a metal interconnect layer (e.g., Metal 1) overlying the interlayer dielectric material, and repeating these metallization steps until all of the necessary metal interconnect layers have been formed.

It should be noted that althoughFIGS. 7-10illustrate the upper level source/drain contacts165,167and the gate contacts176as being formed using separate deposition process steps, in practice, the upper level source/drain contacts165,167and the gate contacts176may be formed concurrently. For example, after removing exposed portions of the dielectric materials160,162to form voided regions163,164, the fabrication process may continue by removing the etch mask used to form voided regions163,164, forming an etch mask that exposes portions of the dielectric material162overlying gate structures112,114, and removing exposed portions of the dielectric material162to create the one or more voided regions170corresponding to the lateral pattern, routing and/or interlayer interconnections to be provided by the gate contacts176. After forming the voided regions163,164,170, the upper level source/drain contacts165,167and the gate contacts176may then be concurrently formed by conformably depositing a conductive metal material in the voided regions163,164,170and planarizing the conductive material to obtain a substantially planar surface that is aligned with the upper surface of the dielectric material162.

FIGS. 11-14illustrate an alternate embodiment of the fabrication process described above. In the alternate embodiment, prior to forming the layer of hard mask material132, a dielectric gate capping material234is formed on the conductive gate material118. For example, the capping material234may be realized as an oxide material formed by oxidizing the upper surface of the conductive gate material118(e.g., by thermal oxidation or chemical oxidation). After creating voided regions overlying the source/drain regions120,122,124,126as described above in the context ofFIG. 3, lower level source/drain contacts242,244,246are formed in the voided regions by depositing a conductive material248, such as a tungsten material, to a thickness chosen such that the conductive material248partially fills the voided regions to a maximum height that is less than the height of the dielectric material128. As illustrated, the upper surfaces of the conductive material248formed in the voided regions are below the upper surfaces of the dielectric material128. After forming the layer of conductive material248, the conductive material248is planarized to remove the conductive material248overlying the hard mask material132, resulting in the semiconductor device structure200ofFIG. 11.

Turning now toFIG. 12, after planarizing the conductive material248, the alternate fabrication process continues by conformably depositing a dielectric capping material260, such as a hard mask material or another suitable dielectric material, overlying the semiconductor device structure200ofFIG. 11. For convenience, the dielectric capping material260may alternatively be referred to herein as a hard mask material, however, it will be appreciated that other dielectric capping materials may be utilized in a practical embodiment. In an exemplary embodiment, the layer of the hard mask material260is deposited to a thickness that is greater than the difference between the upper surfaces of the hard mask material132and the upper surfaces of the conductive material248. In this manner, the dielectric capping material260fills the remainder of the voided regions above the conductive material248to a minimum height that meets or exceeds the hard mask material132on top of the gate structures110,112,114. After forming the layer of dielectric capping material260, the dielectric capping material260is planarized to obtain a substantially planar surface262, resulting in the semiconductor device structure200ofFIG. 12.

Referring now toFIG. 13, after planarizing the dielectric capping material260, fabrication of the semiconductor device structure200continues by forming upper level source/drain contacts265,267of conductive material166in a similar manner as described above in the context ofFIGS. 6-8. In this regard, in the alternate embodiment of the fabrication process, when the dielectric capping material260and the hard mask material132are realized as the same material, such as a nitride material, and the dielectric material162is an oxide material, the oxide material162may be removed (after forming an etch mask) using an anisotropic etchant chemistry that is selective to the oxide material162without attacking the nitride hard mask material132,260, such that the hard mask material260overlying the lower level source/drain contacts242,244remains intact after etching the overlying dielectric material162. After exposing the hard mask material132,260, a second anisotropic etch process is performed to selectively etch the hard mask material132,260without attacking the dielectric gate capping material234, such that at least a portion of the dielectric gate capping material234remains intact and isolates the conductive gate material118from the conductive material166of the subsequently formed source/drain contact267. After the conductive material248of the lower level source/drain contacts242,244is exposed, the upper level source/drain contacts265,267are formed by depositing and planarizing the conductive material166in a similar manner as described above in the context ofFIG. 8.

Referring now toFIG. 14, after planarizing the conductive material166, fabrication of the semiconductor device structure200continues by forming gate contacts of conductive material172in a similar manner as described above in the context ofFIGS. 9-10. In the alternate embodiment of the fabrication process, after forming the etch mask defining the lateral pattern, routing and/or interlayer interconnections to be provided by the gate contacts, the dielectric material162is anisotropically etched to expose the underlying hard mask material132,260using an anisotropic etchant that is selective to the dielectric material162without attacking the hard mask material132,260, such that the hard mask material132,260acts as an etch stop. After exposing the hard mask material132,260, a second anisotropic etch process is performed to selectively remove the hard mask material132,260using an anisotropic etchant chemistry that is selective to the hard mask material132,260without attacking the dielectric gate capping material234. In this regard, by virtue of the upper surfaces of the conductive material248being below the upper surfaces of the gate structures110,112,114, at least a portion of the hard mask material260overlying the lower level source/drain contact246remains intact after the hard mask material132is removed from the gate structures112,114. After removing the exposed hard mask material132from the gate structures112,114, a third anisotropic etch process is performed to selectively remove the gate capping material234and expose the conductive gate material118using an anisotropic etchant chemistry that is selective to the gate capping material234without attacking the remaining hard mask material260overlying the lower level source/drain contact246. After the conductive gate material118is exposed, the gate contact276is formed by conformably depositing and planarizing the conductive material172in a similar manner as described above in the context ofFIG. 10. As illustrated inFIG. 14, the remaining hard mask material260on the lower level source/drain contact246remains intact as a dielectric cap that isolates the conductive material248of the lower level source/drain contact246from the conductive material172of the gate contact276when the conductive material172spans across the lower level source/drain contact246to provide lateral interconnections between gate structures112,114.

FIG. 15illustrates a cross-sectional view of another embodiment of a semiconductor device structure300that may be fabricated in accordance with the processes described herein. The illustrated semiconductor device structure300includes an isolation region302, such as an oxide material or another dielectric material, formed in the semiconductor substrate material102in a conventional manner (e.g., STI or another isolation process) to isolate doped regions (or diffusion regions) of the semiconductor material102having transistor structures formed thereon. In the illustrated embodiment, the lower level source/drain contacts142,144,146extend laterally across the isolation region302to provide lateral intralayer interconnections between source/drain regions of transistor structures formed on diffusion regions isolated by the isolation region302. In the illustrated embodiment, gate contacts304,306are formed in the dielectric material162overlying the isolation region302to provide vertical interconnections between the gate structures110,112,114and a metal interconnect layer (e.g., Metal 1) subsequently formed overlying the substrate, with gate contact306also providing a lateral interconnection between gate structures112,114. As illustrated, the dielectric capping material160on the lower level source/drain contacts142,144,146overlying the isolation region302isolates the lower level source/drain contacts142,144,146from the gate contacts304,306, thereby allowing the lower level source/drain contacts142,144,146to provide intralayer interconnections between the source/drain regions of different transistor structures formed on different diffusion regions with a reduced risk of inadvertent electrical connections (or shorts) being created between the gate contacts304,306and the lower level source/drain contacts142,144,146. For the embodiment illustrated inFIG. 15, upper level source/drain contacts between the lower level source/drain contacts142,144,146and an overlying metal interconnect layer (e.g., Metal 1) may be formed overlying the diffusion regions as described above in the context ofFIGS. 1-14.

To briefly summarize, one advantage of the fabrication processes described herein is that dielectric caps are formed on the lower level source/drain contacts, thereby preventing inadvertent electrical connections between lower level source/drain contacts and neighboring gate contacts as device geometries are reduced. As a result, the lower level source/drain contacts may be utilized to provide intralayer interconnections between the source/drain regions of different transistor structures with a reduced risk of inadvertent electrical connections (or shorts) being created between adjacent and/or overlying gate contacts and the lower level source/drain contacts.

While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. For example, although the subject matter may be described herein in the context of conformal deposition and anisotropic etch processes, practical embodiments of the fabrication processes described herein may utilize other types of deposition and etch processes (e.g., a non-conformal deposition in lieu of a conformal deposition or an isotropic etchant in lieu of an anisotropic etchant). In this regard, it will be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.