Storage device and operating method thereof

A storage device includes a nonvolatile memory; a controller configured to control a write operation of the nonvolatile memory according to a write request received from a host and transmit a response to the write request to the host; and write buffers configured to store write data received with the write request. The controller is further configured to: set a response transmission delay time based on an available size of the write buffers, a minimum response transmission delay time, and a maximum response transmission delay time, transmit the response to the write request to the host after the response transmission delay time passes, and dynamically adjust, as the available size of the write buffers changes, the response transmission delay time within a range from the minimum response transmission delay time to the maximum response transmission delay time.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2019-0106404, filed on Aug. 29, 2019, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to an electronic device, and more particularly, to a storage device and an operating method thereof.

2. Related Art

Recently, a paradigm for a computer environment has transitioned to ubiquitous computing which enables a computer system to be used anytime and anywhere. Therefore, the use of portable electronic devices such as cellular phones, digital cameras, and notebook computers is rapidly increasing. Such portable electronic devices generally use a data storage device using a memory apparatus. The data storage device is used to store data used in the portable electronic devices.

A data storage device using the memory apparatus is advantageous in that stability and durability are superior due to the absence of a mechanical driving unit, information access speed is very fast, and power consumption is small. Examples of data storage devices having such advantages include a universal serial bus (USB) memory apparatus, a memory card having various interfaces, a universal flash storage (UFS) device, and a solid state drive.

SUMMARY

A storage device capable of dynamically adjusting a response transmission delay to a host and an operating method thereof are described herein.

In an embodiment, a storage device includes a nonvolatile memory; a controller configured to control an operation of a write operation of the nonvolatile memory according to a write request received from a host and transmit a response to the write request to the host; and write buffers configured to store write data received with the write request. The controller is further configured to: set a response transmission delay time based on an available size of the write buffers, a minimum response transmission delay time, and a maximum response transmission delay time, transmit the response to the write request to the host after the response transmission delay time passes, and dynamically adjust, as the available size of the write buffers changes, the response transmission delay time within a range from the minimum response transmission delay time to the maximum response transmission delay time.

In an embodiment, an operating method of a storage device includes: receiving, by the controller, a write request and write data from a host; acquiring, by the controller from the write buffers, buffer usage information including an available size of the write buffers; setting, by the controller, a response transmission delay time based on the available size of the write buffers, a minimum response transmission delay time, and a maximum response transmission delay time; transmitting, by the controller, a response to the write request to the host after the set response transmission delay time passes; and dynamically adjusting, by the controller, as the available size of the write buffers changes, the response transmission delay time within a range from the minimum response transmission delay time to the maximum response transmission delay time.

In an embodiment, a controller for controlling a memory device includes: a write buffer configured to buffer write data to be stored in the memory device; a command queue configured to queue a write request corresponding to the write data; a response delay configured to respond to the write request according to an actual response transmission delay time based on a total size of the write buffer, a threshold usage size of the write buffer, a currently available size of the write buffer, and minimum and maximum response transmission delay times; and a processor configured to control the memory device to store therein the write data in response to the write request.

In accordance with the present embodiments, it is possible to dynamically adjust a response transmission delay time within the range from the minimum response transmission delay time determined in advance to the maximum response transmission delay time determined in advance according to the number of available buffers, so that it is possible to substantially prevent a problem that the response transmission delay time is greatly increased at a specific time point. As a consequence, since a deviation of the response transmission delay time is reduced from the viewpoint of the host, the host can determine that the storage device substantially maintains a certain level of performance.

Furthermore, in accordance with the present embodiments, the response transmission delay time is dynamically adjusted, so that it is possible to substantially prevent pending of a host operation due to an insufficient buffer space. Consequently, it is possible to substantially prevent performance degradation in the storage device.

DETAILED DESCRIPTION

Various embodiments of the invention are described below with reference to the accompanying drawings. However, the present invention may be modified or changed in various ways as those in skilled in the art will understand. Thus, the present invention is not limited to the disclosed embodiments. Rather, the present invention may be embodied in many different forms, configurations and arrangements. To that end, reference herein to “an embodiment” or the like is not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s). Similarly, an element referred to in the singular does not preclude more than one such element, unless stated or the context indicates otherwise. Moreover, transition phrases, such as “comprising,” “including,” and the like are used in the open-ended sense. That is, any such phrase does not exclude elements or operations in addition to those stated.

FIG. 1is a diagram illustrating a configuration of a storage device10in accordance with an embodiment.

Referring toFIG. 1, the storage device10may store data that is accessed by a host20such as a cellular phone, an MP3 player, a laptop computer, a desktop computer, a game machine, a television, and/or an in-vehicle infotainment system. The storage device10may also be called a memory system.

The storage device10may be any of various types of storage devices according to an interface protocol electrically connected to the host20. For example, the storage device10may be configured as any of a multimedia card in the form of a solid state drive (SSD), an MMC, an eMMC, an RS-MMC, or a micro-MMC, a secure digital card in the form of an SD, a mini-SD, or a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a storage device in the form of a personal computer memory card international association (PCMCIA) card, a storage device in the form of a peripheral component interconnection (PCI) card, a storage device in the form of a PCI express (PCI-E) card, a compact flash (CF) card, a smart media card, and a memory stick.

The storage device10may be fabricated as any of various types of packages. For example, the storage device10may be fabricated as any of a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level fabricated package (WFP), and a wafer-level stack package (WSP).

The storage device10may include a nonvolatile memory100, a controller200, and one or more buffer memories, identified as buffer memory300inFIG. 1.

The nonvolatile memory100may operate as a data storage medium of the storage device10. The nonvolatile memory100may be configured as any of various types of nonvolatile memories, such as a NAND flash memory apparatus, a NOR flash memory apparatus, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory (MRAM) using a tunneling magneto-resistive (TMR) film, a phase change random access memory (PRAM) using chalcogenide alloys, and/or a resistive random access memory (ReRAM) using a transition metal oxide, according to memory cells.

AlthoughFIG. 1illustrates the nonvolatile memory100as one block, the nonvolatile memory100may include a plurality of memory chips (or dies). The present invention may be applied to the storage device10including a multi-chip nonvolatile memory100.

The nonvolatile memory100may include a memory cell array (not illustrated) having memory cells arranged in the respective intersection regions of bit lines (not illustrated) and word lines (not illustrated). The memory cell array may include memory blocks, each of which s may include multiple pages.

For example, each memory cell of the memory cell array may be a single level cell (SLC) that stores one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a triple level cell (TLC) capable of storing three bits of data, or a quad level cell (QLC) capable of storing four bits of data. Also, the memory cell array may include memory cells having a two-dimensional horizontal structure or memory cells having a three-dimensional vertical structure.

The controller200may control overall operation of the storage device10. The controller200may process a request REQ received from a host20. The controller200may generate control signals for controlling the operation of the nonvolatile memory100in response to the request REQ received from the host20and provide the generated control signals to the nonvolatile memory100.

The controller200may transmit a response RES to the host20in response to the request REQ received from the host20. The host20may transmit a subsequent request REQ to the storage device10after receiving the response RES from the storage device10. Furthermore, the controller200may store data DATA received from the host20in the buffer memory300. Furthermore, the controller200may store data DATA to be provided to the host20in the buffer memory300.

The buffer memory300may be configured to temporarily store data DATA to be transmitted from the host20to the nonvolatile memory100. Furthermore, the buffer memory300may be configured to temporarily store data DATA to be read from the nonvolatile memory100and transmitted to the host20. Furthermore, the buffer memory300may be configured to store map data. The buffer memory300may include a random access memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM); however, the present invention is not limited to any particular type of buffer memory.

Referring toFIG. 2, the controller200may include a processor210, a response delay component (response delay)220, a host interface230, and a memory interface240.

The processor210may control the overall operations of the controller200. The processor210may include a micro control unit (MCU) and/or a central processing unit (CPU). The processor210may process the request REQ transmitted from the host20. In order to process the request REQ received from the host20, the processor210may execute a code type instruction or algorithm loaded in an internal memory (not illustrated), that is, software, and control internal functional blocks and the nonvolatile memory100.

The response delay220may monitor the buffer memories300in real-time to detect the number of currently available buffer memories300(or the available size of one or more buffer memories), and delay the output of a response RES corresponding to the request REQ received from the host20according to the number of currently available buffer memories300or available size thereof). A detailed configuration and operation of the response delay220will be described with reference toFIG. 5andFIG. 6.

The host interface230may serve as an interface between the host20and the storage device10. For example, the host interface230may communicate with the host20using any of standard transmission protocols such as an universal serial bus (USB), an universal flash storage (UFS), a multi-media card (MMC), a parallel advanced technology attachment (PATA), a serial advanced technology attachment (SATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnection (PCI), and/or a PCI express (PCI-E).

The memory interface240may control the nonvolatile memory100under the control of the processor210. The memory interface240may be called a memory controller, a flash control top (FCT) and the like. The memory interface240may provide control signals to the nonvolatile memory100. The control signals may include a command, an address and the like for controlling the nonvolatile memory100. The memory interface240may provide data to the nonvolatile memory100or receive data from the nonvolatile memory100. The memory interface240may be electrically connected to the nonvolatile memory100through a channel CH including one or more signal lines.

Referring toFIG. 3, the controller200may further include an internal memory250, which may store the response delay220. For example, the response delay220illustrated inFIG. 2may be implemented by hardware. Alternatively, the response delay220illustrated inFIG. 3may be implemented by software, or a combination of hardware and software. In an embodiment, the response delay220ofFIG. 3may be a set of source codes configured to monitor the buffer memories300and delay the output of the response RES corresponding to the request REQ received from the host20, according to the number of available buffer memories300.

The internal memory250may include a random access memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). As described above, the internal memory250may store software (firmware) that is executed by the processor210. Furthermore, the internal memory250may store data required for executing the software, for example, meta data. That is, the internal memory250may operate as a working memory of the processor210.

When the nonvolatile memory100is configured as a flash memory apparatus, the processor210may execute software called a flash translation layer (FTL) in order to control operation of the nonvolatile memory100and provide device compatibility to the host20. Through the execution of the flash translation layer (FTL), the host20may recognize and use the storage device10as a general storage such as a hard disk. The flash translation layer (FTL) loaded in the internal memory250may be composed of modules for performing various functions and meta data for executing the modules. The flash translation layer (FTL) may include a read module, a write (or program) module, a map module, a power management module, a wear-leveling module, a bad block management module, a garbage collection module and the like; however, the configuration of the flash translation layer (FTL) is not limited to the aforementioned modules. The response delay220ofFIG. 3may be called a response delay module.

FIG. 1toFIG. 3illustrate an example in which the buffer memory300is disposed externally to the controller200; however, the present invention is not limited to that arrangement; the buffer memory300may be disposed within the controller200.

FIG. 4is a diagram illustrating the buffer memory300.

Referring toFIG. 4, the buffer memory300may include a map buffer310, a read buffer320, a write buffer330and the like.

The map buffer310may store the map data. The map data may include a plurality of logical address to physical address (L2P) entries including logical addresses and physical addresses mapped to the logical addresses. The map data may be stored in a specific region (for example, a system data region) of the nonvolatile memory100, and when the storage device10is powered on, the map data may be read from the specific region and stored in the map buffer310. The map data stored in the map buffer310may be updated by a map module executed by the processor210. Furthermore, when a read request and a read logical address are received from the host20, the processor210translates the read logical address to a corresponding physical address on the basis of the map data stored in the map buffer310, and provides the translated physical address to the nonvolatile memory100through the memory interface240together with a read command.

The read buffer320may store read data read from the nonvolatile memory100. The processor210may transmit the read data stored in the read buffer320to the host20through the host interface230.

The write buffer330may store write data received with a write request from the host20. The processor210may provide the write data stored in the write buffer330to the nonvolatile memory100through the memory interface240together with a write command.

Since the data transmission rate between the host20and the controller200is different than the operation speed (for example, a read operation speed and a write operation speed) of the nonvolatile memory100, the buffer memory300may serve as a buffer for data flow. That is, since the data transmission rate between the host20and the controller200is relatively faster than the operation speed of the nonvolatile memory100, when continuous write request and write data are received from the host20, the nonvolatile memory100is not able to process the write request and write data in real-time. Accordingly, in order to temporarily store such write data until the nonvolatile memory100is ready to receive such data, the buffer memory300, specifically, the write buffer330is used.

When the write request and the write data are received from the host20, the controller200stores the write data in the write buffer330of the buffer memory300and transmits a response to the write request to the host20upon the completion of the storing. The host20transmits the write request and the write data to the controller200, and then waits until the response is received from the controller200.

Even in a situation where the host20needs to transmit subsequent write request and write data to the controller200the host20does not transmit the subsequent write request and write data to the controller200in the absence of response from the controller200. After a response is received from the controller200, the host20transmits the subsequent write request and write data to the controller200. The write data stored in the write buffer330may be deleted from the write buffer330after being stored in the nonvolatile memory100. As described above, since the operation speed of the nonvolatile memory100is relatively slow, the speed at which subsequent write data is stored in the write buffer330may be faster than that at which the write data in the write buffer330is stored in the nonvolatile memory100. As a result, the write buffer330becomes filled with write data, leaving no empty space for additional write data.

When there is no empty space in the write buffer330, the controller200is not able to store any more write data received from the host20in the write buffer330. Therefore, when there is no empty space in the write buffer330, the controller200does not transmit a response to a write request, which has been last received from the host20, to the host20. Accordingly, the host20may wait without transmitting any more write request and write data to the controller200.

Then, when empty space becomes available in the write buffer330, the controller200transmits the response to the last-received write request to the host20, and in response the host20may transmit subsequent write request and write data to the controller200.

As described above, when the write buffer330is full, a write response transmission delay time (write latency) between the host20and the controller200is greatly increased. That is, a response, which is transmitted to the host20immediately after write data is stored in the write buffer330until the write buffer330is full, is transmitted to the host20after a very long time passes when the write buffer330is full.

In the present disclosure, the write response transmission delay time (or more simply response transmission delay time) may indicate a time interval from the time at which the host20has transmitted a write request to the controller200to the time at which the host20has received a response corresponding to the write request from the controller200.

When the write buffer330fills up, which may occur frequently and in a short time, the controller200does not transmit a response to the host20for a long time, which may occur repeatedly. Therefore, the deviation of the response transmission delay time between the host20and the controller200may be large, which may be a factor that degrades the operational performance of the storage device10.

Accordingly, the controller200in accordance with an embodiment may acquire the number of currently available write buffers330by monitoring the write buffers330of the buffer memory300in real-time and adjust the response transmission delay time in real-time according to the number of currently available write buffers330.

The number of currently available write buffers330may represent the number of empty buffers among the write buffers330. In the present disclosure, the number of currently available write buffers330may be indicative of the currently available size in all of the write buffers330. The configuration and operation of adjusting the response transmission delay time in real-time according to the number of available write buffers330is described with reference toFIG. 5toFIG. 10.

FIG. 5is a diagram illustrating an operation of the response delay220in accordance with an embodiment.FIG. 5illustrates only components for explaining the operation of the response delay220in accordance with an embodiment. For clarity, components less related to the operation of the response delay220among the components of the controller200are neither illustrated nor described here.

Referring toFIG. 5, the host interface230may receive a write request WREQ and write data WDATA from the host20(seeFIG. 1) ({circle around (1)}). The host interface230may transmit the write data WDATA to the write buffer330({circle around (2)}). Furthermore, the host interface230may transmit the write request WREQ to the response delay220({circle around (2)}).

The write buffer330may store the write data WDATA received from the host interface230. As the write data WDATA is stored in the write buffer330, the response delay220may generate a response WRES and transmit the response WRES to the host interface230({circle around (3)}). The host interface230may transmit the response WRES received from the response delay220to the host ({circle around (4)}).

The response delay220may transmit a command CMD_BUI requesting buffer usage information to the write buffer330({circle around (5)}). The write buffer330may provide the buffer usage information BUI to the response delay220in response to the received command CMD_BUI ({circle around (6)}). The buffer usage information may include information on the currently available number (or currently available size) of the write buffers330. The response delay220may set a response transmission delay time until the response WRES is transmitted to the host interface230, according to the available number of the write buffers330, and transmit the response WRES to the host interface230after the set response transmission delay time passes.

To this end, the response delay220may include a timer (not illustrated). For example, the response delay220may check the time at which the write request WREQ is received by using the timer, determine whether or not the set response transmission delay time has passed from the reception time of the write request WREQ by using the timer, and then transmit the response WRES to the host interface230. A detailed configuration and operation of the response delay220is described with reference toFIG. 6.

FIG. 6is a diagram illustrating a configuration of the response delay220.

Referring toFIG. 6, the response delay220may include a write buffer monitor221, a response transmission delay time calculator223, and a response generator225.

The write buffer monitor221may monitor the available number of the write buffers330(or available size therein) in real-time and provide a result of the monitoring to the response transmission delay time calculator223. For example, the write buffer monitor221may transmit the command CMD_BUI, requesting the buffer usage information, to the write buffer330in real-time (or periodically), and receive the buffer usage information from the write buffer330. As described above, the buffer usage information may include information on the currently available number (or currently available size) of the write buffers330.

The response transmission delay time calculator223may determine a response transmission delay time (for example, an actual response transmission delay time) by using the buffer usage information provided from the write buffer monitor221, that is, the available number (or available size) of the write buffers330. For example, the response transmission delay time calculator223may calculate (or set) the actual response transmission delay time by using the total number (or total size) of the write buffers330, the threshold usage number (or threshold usage size) of the write buffers330in which response transmission delay to the host20is triggered, a maximum response transmission delay time and a minimum response transmission delay time, which may be determined in advance, and the currently available number (or currently available size) of the write buffers330.

For example, the response transmission delay time calculator223may set the actual response transmission delay time by using the following Equation 1.
tRESD=((Bt−Bu−Ba)*(Dmax−Dmin)/(Bt−Bu))+DminEquation 1

In Equation 1 above, ‘tRESD’ denotes the actual response transmission delay time, ‘Bt’ denotes the total number (or total size) of the write buffers330, ‘Bu’ denotes the threshold usage number of the write buffers330in which response transmission delay is triggered, ‘Ba’ denotes the currently available number of the write buffers330, ‘Dmax’ denotes the maximum response transmission delay time determined in advance, and ‘Dmin’ denotes the minimum response transmission delay time, which may be determined in advance.

In the present embodiment, the maximum response transmission delay time may be determined using a command queue depth (QD) and a target response transmission delay time corresponding to the command queue depth.

Furthermore, the minimum response transmission delay time may be determined using an average response transmission delay time, which may be determined in advance, and the maximum response transmission delay time. In the present embodiment, the minimum response transmission delay time may indicate the time at which response transmission delay is triggered. The average response transmission delay time may be obtained using the total number (or total size) of the write buffers330, the threshold usage number of the write buffers330in which response transmission delay is triggered, and a maximum pending time for a write operation of user data. The maximum pending time may indicate a maximum time during which the write operation of user data is pending for internal operations (for example, garbage collection write, journal update, erase operation and the like) performed in the storage device10. The maximum pending time may be determined through a test such as a simulation.

For example, the response transmission delay time calculator223may obtain the average response transmission delay time, the maximum response transmission delay time, and the minimum response transmission delay time by using the following Equation 2 to Equation 4.
Dav=tPD/(Bt−Bu)  Equation 2
Dmax=Dtg/QDEquation 3
Dmin=Dmax−(2*(Dmax−Dav))  Equation 4

In Equation 2 to Equation 4 above, ‘Dav’ denotes the average response transmission delay time, ‘tPD’ denotes the maximum pending time, ‘Dtg’ denotes the target response transmission delay time, and ‘QD’ denotes the command queue depth.

Among the parameters used in Equation 1 to Equation 4 above, the threshold usage number of the write buffers330in which response transmission delay is triggered, the command queue depth (QD), and the target response transmission delay time are variable parameters. As the threshold usage number of the write buffers330, the command queue depth (QD), and the target response transmission delay time change, the slope of a graph indicating change in the response transmission delay time according to the available number may change.

Furthermore, since only the aforementioned parameters are changed according to a product characteristic or a design change, it is possible to easily tune the response transmission delay time even though the product characteristic or the design is changed.

FIG. 7is a flowchart illustrating a process of determining the maximum response transmission delay time and the minimum response transmission delay time in accordance with an embodiment. In describing such process reference may also be made to one or more ofFIG. 1toFIG. 6.

In step S710, the average response transmission delay time may be determined (or calculated) using the total number (or total size) of the write buffers330, the threshold usage number of the write buffers330in which response transmission delay is triggered, and the maximum pending time. Specifically, the average response transmission delay time may be obtained by dividing the maximum pending time by the difference between the threshold usage number of the write buffers330and the total number of the write buffers330.

In step S720, the maximum response transmission delay time may be determined (or calculated) using the command queue depth (QD) and the target response transmission delay time. Specifically, the maximum response transmission delay time may be obtained by dividing the target response transmission delay time by the command queue depth.

In step S730, the minimum response transmission delay time may be determined (or calculated) using the average response transmission delay time determined in step S710and the maximum response transmission delay time determined in step S720. The minimum response transmission delay time may indicate a time point at which response transmission delay is triggered.

Specifically, the minimum response transmission delay time may be obtained by subtracting a response transmission delay time from the maximum response transmission delay time, where the response transmission delay time corresponds to twice the difference between the average response transmission delay time and the maximum response transmission delay time.

FIG. 8is a flowchart illustrating an operating method of the storage device in accordance with an embodiment. In describing such operating method reference may also be made to one or more ofFIG. 1toFIG. 6.

In step S810, the controller200may receive a write request and write data from the host20.

In step S820, the controller200may store the received write data in the write buffer330of the buffer memory300.

In step S830, the response delay220of the controller200may acquire the buffer usage information on the write buffer330. For example, the response delay220may transmit a command requesting the buffer usage information to the write buffer330, which may provide the buffer usage information to the response delay220in response to the command. As described above, the buffer usage information may include information on the available number (or available size) of the write buffers330.

In step S840, the response delay220may determine whether the available number (or available size) of the write buffers330is greater than or equal to the threshold usage number. When the available number (or available size) of the write buffers330is greater than or equal to the threshold usage number, the process may proceed to step S850. On the other hand, when the available number (or available size) of the write buffers330is less than the threshold usage number, the process may proceed to step S870.

In step S850, the response delay220may determine (or set) the actual response transmission delay time by using the total number (or total size) of the write buffers330, the threshold usage number (or threshold usage size) of the write buffers330in which response transmission delay is triggered, the maximum response transmission delay time and the minimum response transmission delay time, which may be determined in advance, and the available number (or available size) of the write buffers330acquired in step S830.

Specifically, the response delay220may calculate a first value (Btu−Bu−Ba) by a subtraction operation involving the threshold usage number, Buthe available number of the write buffers330(Ba) and the total number of the write buffers330(Bt), calculate a second value by subtracting the minimum response transmission delay time (Dmin) from the maximum response transmission delay time (Dmax), calculate a third value by multiplying the second value by the first value, calculate a fourth value (Bt−Bu) by subtracting the threshold usage number of the write buffers330(Bu) from the total number of the write buffers330(Bt), calculate a result value by dividing the third value by the fourth value, and add the minimum response transmission delay time to the result value, thereby determining the actual response transmission delay time.

In step S860, the controller200may transmit a response to the write request received in step S810to the host20after a time corresponding to the actual response transmission delay time determined in step S850passes.

In step S870, the controller200may transmit a response to the write request received in step S810to the host20immediately after the write data is stored in the write buffer330.

FIG. 9is a graph illustrating a response transmission delay time according to the available number of write buffers in accordance with an embodiment.

Referring toFIG. 9, a horizontal axis denotes the number of the write buffers330and a vertical axis denotes the response transmission delay time. As illustrated inFIG. 9, the time at which response transmission delay is triggered corresponds to the time at which the usage number of the write buffers330reaches the threshold usage number. In such a case, the response transmission delay time corresponds to the minimum response transmission delay time described above. Accordingly, the controller200may transmit a response to the host20without delay until the usage number of the write buffers330reaches the threshold usage number.

Referring toFIG. 9, a difference d1between the maximum response transmission delay time and the average response transmission delay time and a difference d2between the minimum response transmission delay time and the average response transmission delay time may be substantially equal to each other. The response transmission delay time according to the number of the write buffers330may increase linearly from the time at which number of the write buffers330corresponds to the threshold usage number. In such a case, the slope of the graph may change as one or more parameters change. Since these parameters have been described above, they are not described here.

FIG. 10is a graph illustrating an actual response transmission delay time determined according to the available number of the write buffers in accordance with an embodiment. For example, it is assumed that the total number of the write buffers is ‘100’, the threshold usage number of the write buffers is ‘20’, the available number of the write buffers is ‘50’, the maximum response transmission delay time is ‘10 μs’, the average response transmission delay time is ‘6 μs’, and the minimum response transmission delay time is ‘2 μs’.

Referring toFIG. 10, the response delay220may determine the actual response transmission delay time by using the buffer usage information acquired from the write buffer330, that is, the available number ‘50’ and Equation 1 above.

For example, it is assumed that subtracting the sum of the threshold usage number and the available number of the write buffers330from the total number of the write buffers330yields a first value, that subtracting the minimum response transmission delay time from the maximum response transmission delay time yields a second value, and that subtracting the threshold usage number of the write buffers330from the total number of the write buffers330yields a third value.

According to the above assumption, the first value may be ‘30’, the second value may be ‘8’, and the third value may be ‘80’. Dividing the product of the first value and the second value (‘240’) by the third value ‘80’, the result is ‘3’; and adding the minimum response transmission delay time ‘2’ to ‘3’, the actual response transmission delay time tRESDis ‘5’. Accordingly, the response delay220may transmit a response to the host20after a response transmission delay time of ‘5 μs’ passes.

That is, in the present disclosure, it is possible to dynamically adjust the response transmission delay time (that is, the actual response transmission delay time) within a range from a minimum response transmission delay time to a maximum response transmission delay time, either or both of which may be determined in advance, according to the available number of the write buffers330. As described above, the response transmission delay time is dynamically adjusted within a set range, so that it is possible to avoid or substantially limit a significant increase in the response transmission delay time at any time during operation. As a consequence, since the response transmission delay time is reduced and maintained within an acceptable range, the host recognizes that the storage device substantially maintains a certain level of performance and thus can more efficiently interact with the storage device.

FIG. 11illustrates a data processing system including a solid state drive (SSD) in accordance with an embodiment. Referring toFIG. 11, a data processing system2000may include a host apparatus2100and an SSD2200.

The SSD2200may include a controller2210, a buffer memory device2220, nonvolatile memory devices2231to223n, a power supply2240, a signal connector2250, and a power connector2260.

The controller2210may control overall operation of the SSD2220.

The buffer memory device2220may temporarily store data to be stored in the nonvolatile memory devices2231to223n. The buffer memory device2220may temporarily store data read from the nonvolatile memory devices2231to223n. The data temporarily stored in the buffer memory device2220may be transmitted to the host apparatus2100or the nonvolatile memory devices2231to223naccording to control of the controller2210.

The nonvolatile memory devices2231to223nmay be used as a storage medium of the SSD2200. The nonvolatile memory devices2231to223nmay be coupled to the controller2210through a plurality of channels CH1to CHn. One or more nonvolatile memory devices may be coupled to one channel. The nonvolatile memory devices coupled to the same channel may be coupled to the same signal bus and the same data bus.

The power supply2240may provide power PWR input through the power connector2260to the inside of the SSD2200. The power supply2240may include an auxiliary power supply2241. The auxiliary power supply2241may supply the power so that the SSD2200is properly terminated even when sudden power-off occurs. The auxiliary power supply2241may include large capacity capacitors capable of charging the power PWR.

The controller2210may exchange a signal SGL with the host apparatus2100through the signal connector2250. The signal SGL may include a command, an address, data, and the like. The signal connector2250may be configured as any of various types of connectors according to an interfacing method between the host apparatus2100and the SSD2200.

FIG. 12illustrates the controller2210ofFIG. 11. Referring toFIG. 12, the controller2210may include a host interface2211, a control component2212, a random access memory (RAM)2213, an error correction code (ECC) component2214, and a memory interface2215.

The host interface2211may perform interfacing between the host apparatus2100and the SSD2200according to a protocol of the host apparatus2100. For example, the host interface2211may communicate with the host apparatus2100through any of a secure digital protocol, a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, an embedded MMC (eMMC) protocol, a personal computer memory card international association (PCMCIA) protocol, a parallel advanced technology attachment (PATA) protocol, a serial advanced technology attachment (SATA) protocol, a small computer system interface (SCSI) protocol, a serial attached SCSI (SAS) protocol, a peripheral component interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, and a universal flash storage (UFS) protocol. The host interface unit2211may perform a disc emulation function that the host apparatus2100recognizes the SSD2200as a general-purpose data storage apparatus, for example, a hard disc drive HDD.

The control component2212may analyze and process the signal SGL input from the host apparatus2100. The control component2212may control operations of internal functional blocks according to firmware and/or software for driving the SDD2200. The RAM2213may be operated as a working memory for driving the firmware or software.

The ECC component2214may generate parity data for the data to be transferred to the nonvolatile memory devices2231to223n. The generated parity data may be stored in the nonvolatile memory devices2231to223ntogether with the data. The ECC component2214may detect errors in data read from the nonvolatile memory devices2231to223nbased on the parity data. When detected errors are within a correctable range, the ECC component2214may correct the detected errors.

The memory interface2215may provide a control signal such as a command and an address to the nonvolatile memory devices2231to223naccording to control of the control component2212. The memory interface2215may exchange data with the nonvolatile memory devices2231to223naccording to control of the control component2212. For example, the memory interface2215may provide data stored in the buffer memory device2220to the nonvolatile memory devices2231to223nor provide data read from the nonvolatile memory devices2231to223nto the buffer memory device2220.

FIG. 13illustrates a data processing system including a data storage apparatus in accordance with an embodiment. Referring toFIG. 13, a data processing system3000may include a host apparatus3100and a data storage apparatus3200.

The host apparatus3100may be configured in a board form such as a printed circuit board (PCB). Although not shown inFIG. 13, the host apparatus3100may include internal functional blocks configured to perform functions of the host apparatus3100.

The host apparatus3100may include a connection terminal3110such as a socket, a slot, or a connector. The data storage apparatus3200may be mounted on the connection terminal3110.

The data storage apparatus3200may be configured in a board form such as a PCB. The data storage apparatus3200may refer to a memory module or a memory card. The data storage apparatus3200may include a controller3210, a buffer memory device3220, nonvolatile memory devices3231to3232, a power management integrated circuit (PMIC)3240, and a connection terminal3250.

The controller3210may control overall operation of the data storage apparatus3200. The controller3210may be configured the same or substantially the same as the controller2210illustrated inFIG. 12.

The buffer memory device3220may temporarily store data to be stored in the nonvolatile memory devices3231and3232. The buffer memory device3220may temporarily store data read from the nonvolatile memory devices3231and3232. The data temporarily stored in the buffer memory device3220may be transmitted to the host apparatus3100or the nonvolatile memory devices3231and3232according to control of the controller3210.

The nonvolatile memory devices3231and3232may be used as a storage medium of the data storage apparatus3200.

The PMIC3240may provide power input through the connection terminal3250to the inside of the data storage apparatus3200. The PMIC3240may manage the power of the data storage apparatus3200according to control of the controller3210.

The connection terminal3250may be coupled to the connection terminal3110of the host apparatus3100. A signal such as a command, an address, and data and power may be transmitted between the host apparatus3100and the data storage apparatus3200through the connection terminal3250. The connection terminal3250may be configured in various forms according to an interfacing method between the host apparatus3100and the data storage apparatus3200. The connection terminal3250may be arranged on or in any side of the data storage apparatus3200.

FIG. 14illustrates a data processing system including a data storage apparatus in accordance with an embodiment. Referring toFIG. 14, a data processing system4000may include a host apparatus4100and a data storage apparatus4200.

The host apparatus4100may be configured in a board form such as a PCB. Although not shown inFIG. 14, the host apparatus4100may include internal functional blocks configured to perform functions of the host apparatus4100.

The data storage apparatus4200may be configured in a surface mounting packaging form. The data storage apparatus4200may be mounted on the host apparatus4100through a solder ball4250. The data storage apparatus4200may include a controller4210, a buffer memory device4220, and a nonvolatile memory device4230.

The controller4210may control overall operation of the data storage apparatus4200. The controller4210may be configured the same or substantially the same as the controller2210illustrated inFIG. 12.

The buffer memory device4220may temporarily store data to be stored in the nonvolatile memory device4230. The buffer memory device4220may temporarily store data read from the nonvolatile memory device4230. The data temporarily stored in the buffer memory device4220may be transmitted to the host apparatus4100or the nonvolatile memory device4230through control of the controller4210.

The nonvolatile memory device4230may be used as a storage medium of the data storage apparatus4200.

FIG. 15illustrates a network system5000including a data storage apparatus in accordance with an embodiment. Referring toFIG. 15, the network system5000may include a server system5300and a plurality of client systems5410to5430which are coupled through a network5500.

The server system5300may serve data in response to requests of the plurality of client systems5410to5430. For example, the server system5300may store data provided from the plurality of client systems5410to5430. In another example, the server system5300may provide data to the plurality of client systems5410to5430.

The server system5300may include a host apparatus5100and a data storage apparatus5200. The data storage apparatus5200may be configured of the storage device10ofFIG. 1, the SSD2200ofFIG. 11, the data storage apparatus3200ofFIG. 13, or the data storage apparatus4200ofFIG. 14.

FIG. 16illustrates a nonvolatile memory device included in a data storage apparatus in accordance with an embodiment. Referring toFIG. 16, a nonvolatile memory device100may include a memory cell array110, a row decoder120, a column decoder140, a data read/write block130, a voltage generator150, and control logic160.

The memory cell array110may include memory cells MC arranged in regions in which word lines WL1to WLm and bit lines BL1to BLn intersect.

The row decoder120may be coupled to the memory cell array110through the word lines WL1to WLm. The row decoder120may operate through control of the control logic160. The row decoder120may decode an address provided from an external apparatus (not shown). The row decoder120may select and drive the word lines WL1to WLm based on a decoding result. For example, the row decoder120may provide a word line voltage provided from the voltage generator150to the word lines WL1to WLm.

The data read/write block130may be coupled to the memory cell array110through the bit lines BL1to BLn. The data read/write block130may include read/write circuits RW1to RWn corresponding to the bit lines BL1to BLn. The data read/write block130may operate according to control of the control logic160. The data read/write block130may operate as a write driver or a sense amplifier according to an operation mode. For example, the data read/write block130may operate as the write driver configured to store data provided from an external apparatus in the memory cell array110in a write operation. In another example, the data read/write block130may operate as the sense amplifier configured to read data from the memory cell array110in a read operation.

The column decoder140may operate through control of the control logic160. The column decoder140may decode an address provided from an external apparatus (not shown). The column decoder140may couple the read/write circuits RW1to RWn of the data read/write block130corresponding to the bit lines BL1to BLn and data input/output (I/O) lines (or data I/O buffers) based on a decoding result.

The voltage generator150may generate voltages used for an internal operation of the nonvolatile memory device100. The voltages generated through the voltage generator150may be applied to the memory cells of the memory cell array110. For example, a program voltage generated in a program operation may be applied to word lines of memory cells in which the program operation is to be performed. In another example, an erase voltage generated in an erase operation may be applied to well regions of memory cells in which the erase operation is to be performed. In another example, a read voltage generated in a read operation may be applied to word lines of memory cells in which the read operation is to be performed.

The control logic160may control overall operation of the nonvolatile memory device100based on a control signal provided from an external apparatus. For example, the control logic160may control an operation of the nonvolatile memory device100such as a read operation, a write operation, an erase operation of the nonvolatile memory device100.

While various embodiments have been illustrated and described, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the present invention is not limited by or to the disclosed embodiments. Rather, the present invention encompasses all modifications and variations that fall within the scope of the claims including their equivalents.