An exemplary functional input sequential circuit for reducing the setup time of input signals. The functional sequential circuit includes a tri-state inverter having an input signal and two control signals. The transmission circuit receives a control signal from a combinational logic circuit that performs a logical operation on a second input signal and a clock signal. The output of the transmission circuit is coupled to a digital storage element. Further, a control circuit is coupled to the digital storage element in order to force a value on the digital storage element when no input signal is received from the transmission circuit. The control circuit is also controlled by the second input signal and a clock signal.

TECHNICAL FIELD

Embodiments of the disclosure relate to sequential circuits, and more specifically, to high-performance functional-input sequential circuits.

BACKGROUND

Some sequential circuits, such as latches and flip-flops, accept an input that is a logical function of multiple inputs; these sequential circuits are typically called functional-input sequential circuits. The logical function of the input signals can be any function such as an OR, NAND, NOR, or AND operation. Typically, implementation of these logical functions requires a series combination of transistors, which increases the input signals setup time, defined as the minimum amount of time before a clock's active edge by which the data must be stable for it to be latched correctly. Any violation in this minimum required time causes incorrect data capture, known as setup violation.

Further, in networks that include a number of sequential elements in a single clock path, the sequential elements face different insertion delays, and therefore, the clock signal reaches the sequential elements at different times. If the setup time of the signals at the sequential elements is different and further, if the sequential elements have varying insertion delays, data can be incorrectly captured, causing errors. In certain situations, the clock can be skewed to compensate for the insertion delays, but if the sequential elements all belong to the same clock path, skewing the clock becomes cumbersome.

BRIEF SUMMARY

Embodiments of the invention are directed to an exemplary functional-input sequential circuit. The functional-input sequential circuit includes a transmission circuit receiving a first input signal, a first control signal, and a second control signal. The circuit further includes a combinational logic circuit receiving a second input signal and a clock input signal, the combinational logic circuit is operatively coupled to the transmission circuit providing the first control signal to the transmission circuit. The second control signal is derived from the clock or from the first control signal using some combinational logic. The transmission circuit further provides an output to a digital storage element. In addition, a control circuit is coupled to the digital storage element to force a value on the digital storage element depending on a state of the first and second input signals and the clock signal.

DETAILED DESCRIPTION

Overview

The following detailed description is made with reference to the figures. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations of the description that follows.

Typically, in functional-input sequential circuits a logic gate performing a logical function on at least two input signals provides the input to a sequential device. The logical function can be a NAND, NOR, AND, or OR function.FIG. 1illustrates a typical functional-input sequential circuit100, as employed in the art, that includes a dual input NAND gate102or NOR gate104coupled to the input of a digital storage element106, such as a latch or a flip-flop. In order to realize the dual input logical function of the NAND gate102or the NOR gate104, two or more cascaded stages of transistor circuitry is required.FIG. 2depicts the NOR gate104implemented using CMOS transistors, which includes four transistors connected in series and parallel, as also found in the art. Due to the series stacking of the PMOS transistors202and204, the setup time of any input signal increases, which degrades the performance of the typical functional input sequential circuit100. Hence, removing the series stack of transistors can reduce the setup time, thereby increasing the performance of the typical functional input sequential circuit100.

To this end, embodiments of the present invention replace a multiple input logical gate present at the input of a digital storage element with a single-input transmission circuit and a combinational circuit that controls the gating of the single-input transmission circuit. One of the multiple input signals is provided to the single-input transmission circuit, while the other input signals are provided to the combinational logic circuit. In one implementation, the input signals include a critical and one or more non-critical signals. Examples of critical signals are enable signals, data signals, and so on. Examples of non-critical signals can be reset signals, set signals, scan signals, test signals, and so on. The non-critical signals are removed and placed in the combinational logic circuit, while the critical signal is provided directly to the transmission circuit. Typically, the non-critical signals are not used as often as the critical signals; therefore, removing the non-critical signals from the critical path ensures considerable reduction in the setup time of the critical signal.

In another implementation, all the input signals are critical, in which case, one signal is supplied to the single-input transmission circuit, while the other signals are supplied to the combinational logic circuit. In this case, the signal provided to the single-input transmission circuit has a shorter setup time compared to the input signal provided to the combinational logic circuit. It will be understood that the new topology performs the same functionality as a multiple input functional sequential circuit. These and other designs, features, and advantages of the present invention will become apparent with reference to the following detailed description and the drawings.

Embodiments

FIG. 3illustrates a block diagram of an exemplary functional-input sequential circuit300according to an embodiment of the claimed invention. The functional-input sequential circuit300includes a transmission circuit302coupled to a digital storage element304, the transmission circuit302receives a first input signal306, and a first and second control signals. A combinational logic circuit310provides the first control signal308, while the second control signal312can be an inverted clock signal, an inverted first control signal, a clock signal, and so on. Further, a control circuit314controls a digital value of the digital storage element304. A second input signal316and a clock signal318are provided as inputs to the combinational logic circuit310and the control circuit314. The control circuit314forces a high or low value on the digital storage element304depending on the value of the second input signal316, and the clock signal318. Moreover, an output320of the transmission circuit302is provided to the digital storage element304.

In one embodiment, the transmission circuit302is a tri-state inverter receiving an input signal and two control signals. The value of the control signals308and312determine the operation of the tri-state inverter, i.e., the control signals308and312can switch on/off the tri-state inverter. For example, when the control signal308is low and control signal312is high, the output320of the tri-state inverter is the inverted input signal. Alternately, when the control signal308is high and control signal312is low, the output320is disconnected from the rest of the circuit. Thus, the control signals can control the operation of the tri-state inverter. In another embodiment, the transmission circuit302is a simple inverter followed by a pair of transmission gates that provides the same functionality as the tri-state inverter. Other examples of the transmission circuit302include switches, tri-state buffers, and buffers. A suitable transmission circuit is selected based on the application of the functional-input sequential circuit300; for example, in cases where the logical function is an AND or OR operation, the transmission circuit302can be a tri-state buffer or a buffer followed by a transmission gate.

As stated previously, the combinational logic circuit310provides at least one of the control signals, such as the control signal308, to the transmission circuit302. The combinational logic circuit310can perform a certain logical function on input signals based on the type of logic gates used. Further, the same logical function can be achieved by using different logic gates or by changing the order of the logic gates in the circuit. It will be understood that any combination of logic gates can be used to derive a particular logical function. For example, the combinational logic circuit310can realize logical functions such as AND, NAND, NOR, NOT, and so on.

In one implementation, the combinational logic circuit310receives a second input signal316and a clock signal318, and the circuit outputs the control signal308based on a logical function of the input signals. Further, the control signal308controls gating of the transmission circuit302.

The digital storage element304can be a latch or a flip-flop. The following two paragraphs explain the basic concepts related to digital storage elements. A latch is an electronic circuit that has two stable states and thereby stores one bit of information. The output of a latch may depend not only on its current input, but also on its previous inputs, and therefore latches are described as sequential logic circuits. Further, latches are designed to be transparent, i.e., a change in an input signal causes immediate changes in output. Alternatively, additional logic can be combined with a simple transparent latch to make it opaque when another input is not asserted. For example, a clock signal can control the state of the latch. When the clock signal is low, the latch behaves transparently and forwards the input signal to the output. Alternatively, when the clock signal is high, the latch behaves opaquely, and forwards the last input signal value that was stored in the latch.

A flip-flop, like a latch, stores one bit of information and is usually controlled by one or two control signals and/or a clock signal. The output often includes the output signal together with its complement. Unlike latches, flip-flops are not transparent, and they ignore their inputs except at the transition of a dedicated clock signal. Thus, a flip-flop can either change or retain its output signal based upon the values of the input signals at the clock transition. Some flip-flops change their outputs on the rising edge of the clock, others on the falling edge. A commonly used master-slave flip-flop can be made using two latches, one as master and other as slave latch.

The control circuit314, coupled to the digital storage element304, can operate as a pull-up or a pull-down circuit. The pull-up circuit forces a high (one) value on the digital storage element304when the tri-state inverter402is not driving the input of the digital storage element304or when the clock signal318is low. While, the pull-down circuit forces a low (zero) value on the digital storage element304when the tri-state inverter402is not driving its input and also when clock signal318is low, i.e., latch is transparent. For example, if the tri-state inverter402is disabled, the control circuit314can either pull-up or pull-down the value of the digital storage element304depending on the embodiment.

The combinational logic circuit310and the control circuit314aid in producing a value at the output of the digital storage element304, which is a logical function of the first input signal306, the second input signal316, and the clock signal318. Further, these circuits can replace any multiple-input logic function placed before the digital storage element304. For example, these circuits along with the transmission circuit302can replace an OR, an AND, a NOR or a NAND gate. The followingFIGS. 4-10will describe some embodiments of the functional-input sequential circuit300.

In one embodiment, the functional-input sequential circuit300is part of an integrated clock-gating cell (ICG). Usually, the ICG cells gate a clock signal thereby reducing the total power consumed in a circuit. These ICG cells typically include a NOR gate that receives an enable signal and a test signal. The NOR gate is coupled to a latch that receives the NOR gate output and a clock signal and the output of the latch is provided to an AND gate along with the clock signal. The output of the AND gate is a gated clock signal, which can be provided to the rest of the circuit. Most often, ICG cells are inserted after a clock distribution system and before the rest of the circuit. Placing one ICG cell for the entire circuit provides better power reduction and consumes lesser chip space, but on the other hand, affects the enable signal timing.

One embodiment of the present invention includes a high-performance ICG cell that reduces the setup time of the enable signal considerably. This result can be achieved by replacing the ICG's NOR gate with a faster gate. Since the NOR gate includes a series stack of transistors receiving multiple signals including critical and non-critical signals, the setup time of the critical signal or enable signal increases. Thus, replacing the NOR gate (with a logic gate receiving only the critical signal) can reduce the setup time of the enable signal. The two input signals to the NOR gate are the enable signal and the test signal, by removing the test signal from the critical path of the circuit and providing it to control the transmission circuit302, the performance of the ICG cell is enhanced. Further, because the series transistor stack from the input stage is removed, the setup time for zero and one logic of the enable signal are more balanced. In addition, since the transmission circuit302receives only the enable signal as an input, it can be independently sized to reduce area and decrease the setup time.

FIG. 4is a block diagram of an exemplary NOR input latch400that can be used to replace the NOR gate and the latch of the ICG. The exemplary NOR input latch400includes a tri-state inverter402receiving an enable signal404, a latch406receiving the output signal320from the tri-state inverter402, an OR combinational logic circuit408, and a pull-down circuit410. The OR combinational logic circuit408performs a logical OR operation on the clock signal318and a test signal412and provides the control signal308to the tri-state inverter402, while the control signal312is derived from an inverted clock signal414. The pull-down circuit410is coupled to the latch406and it controls the latch's value. When the latch406does not receive an input from the tri-state inverter402and when the clock signal318is low, the pull-down circuit410forces the value of the latch406to a logical zero. Further, the inverted clock signal414and the test signal412control the pull-down circuit410.

The enable signal404is a functional signal that is used in the normal operation of the ICG, while the test signal412is typically used to test the ICG. It will be appreciated however, that the NOR input latch400can be utilized in any circuitry and its application is not restricted to the ICG, also any input signals can be applied to the NOR input latch400, such as data signals, clear signals, reset signals, scan signals, and so on. The implementation of the NOR input latch in an ICG is merely an example to illustrate the operation of the NOR input latch400.

FIG. 5illustrates a circuit diagram500for the exemplary NOR input latch400. Here, the tri-state inverter402comprises PMOS and NMOS transistors. The control signal308drives the PMOS transistor502, which is connected between a power supply504and a second PMOS transistor, while the inverted clock signal414(the second control signal312) drives the NMOS transistor506, which is connected between the ground508and a second NMOS transistor. A logical one to the PMOS transistor502disconnects the circuit from the power supply504, while a logical zero connects the tri-state inverter402to the power supply504. Similarly, a logical one to the NMOS transistor506drives the enable signal404to the ground508, while a logical zero disconnects the circuit from the ground508.

As shown, the logical OR operation of the OR combinational logic circuit408can be realized by inverting the test signal412and the clock signal318at the inverters510and512respectively and providing the inverted signals to a NAND gate514. The output of the NAND gate514is the control signal308, which is provided to the PMOS transistor502.

The latch406can be implemented using any configuration known in the art. For example, the latch depicted inFIG. 5includes a tri-state inverter516in a feedback loop. The control signal308and the inverted clock signal414control the gating of the tri-state inverter516. When the inverted clock signal414is low and the control signal is high, the latch406behaves opaquely and forwards the last stored value. Alternately, when the inverted clock signal414is high, the latch406is transparent, passing the signal at its input to the output.

Further, the pull-down circuit410is implemented using two NMOS transistors518and520, controlled by the inverted clock signal414and the test signal412respectively. Since both the transistors are NMOS and in series, both the inverted clock signal414and the test signal412, must be high in order to enable the pull-down circuit410. Using the inverted clock signal414along with the test signal412ensures that the test signal412does not change the value of the latch406asynchronously.

The operation of the NOR input latch400will be described now with reference to theFIGS. 4 and 5. A typical NOR truth table for the enable and test signals is depicted in table 1, while table 2 depicts the operation of the exemplary NOR input latch400.

Table 2 shows that the NOR function is obtained between the enable signal404the test signal412, for high and low values of the clock signal318. It should be noted that when the clock318is low, the latch406value is allowed to change and for a high clock value, the latch406value remains unchanged and the latch406drives the stored value (as seen in rows 2, 4, 6, and 8 of table 2).

As depicted in table 2, when both the test signal412and the clock signal318are zero (rows 1 and 5 of table 2), the output320follows a simple inversion of the enable signal404. Therefore, when the test signal412is zero and the clock signal318is low, the tri-state inverter402inverts the enable signal404and the output320is provided to the latch406.

When the test signal412is one and the clock signal318is zero (rows 3 and 7 of table 2), the control signals308and312are one, which keeps PMOS502off and turn NMOS506on respectively. If the enable signal404is one, the output320of the tri-state inverter402is pulled down to zero as NMOS506is also on. However, here the pull-down circuit410is also enabled (as the test signal412and the inverted clock signal414are high), which also pulls the output320down (row 7) and the latch406accepts the new value. If the enable signal is zero, the tri-state inverter402is blocked, as the PMOS502is switched off. In this case, the pull-down circuit410pulls the output320down to a logical zero value (row 3).

For the case, when the test signal412and the clock signal318are both one (rows 4 and 8 of table 2), the control signal312, which is the inverted clock signal414, becomes zero. This switches off the NMOS transistor506, thereby gating the enable signal404from entering the latch406. Further, the pull-down circuit410is disabled as the inverted clock signal414is zero and the latch406drives the output.

In another embodiment, a NAND gate can provide an input to the latch406.FIG. 6illustrates a block diagram of an exemplary NAND input latch600that follows this embodiment. The NAND input latch600includes the tri-state inverter402and the latch406. The tri-state inverter402receives the input signal306and provides the output signal320to the latch406. A NOR combinational logic circuit602performs a NOR operation on the clock signal318and the input signal316. Further, a pull-up circuit604is coupled to the latch406and it forces a logic one on the latch406in situations when the output320of the tri-state inverter402is disabled.

FIG. 7illustrates an exemplary circuit diagram700of the NAND input latch600. Four transistors702,704,706, and708form the tri-state inverter402. The transistors can be any known transistors such as CMOS transistors, TTL transistors, and so on. In this diagram, the transistors are depicted as CMOS transistors. The transistors702and704are PMOS, while the transistors706and708are NMOS transistors. The control signal308is provided to the NMOS transistor708, while the clock signal318(which is the control signal312) is provided to the PMOS transistor702.

The NOR combinational logic circuit602can be realised using an inverter710and a NOR gate712. The inverter710inverts the input signal316, and the output of the inverter710along with the clock signal318is provided to the NOR gate712. A NOR operation is performed on the two signals, and the output of the NOR gate is the control signal308. The control signal308along with the clock signal318control the gating of the tri-state inverter402and a second tri-state inverter (tri-state inverter714), present in the latch406. In addition, the pull-up circuit604, which is coupled to the latch406, includes two PMOS transistors that are controlled by the input signal316and the clock signal318. Since the transistors are P-type, both signals should have a logic zero value to enable the pull-up circuit604. It will be understood that an NMOS pull-up circuit can also be utilized, in which case, the input signals can be inverted before they are provided to the pull-up circuit604.

The operation of the NAND input latch600will be described now with reference toFIGS. 6 and 7. Table 3 depicts the truth table for a NAND operation, while table 4 depicts the operation of the exemplary NAND input latch.

TABLE 3Truth table for NANDInputInputOutput316306320001011101110

Table 4 depicts the NAND function obtained between the input signals306and316for high and low clock values. It should be noted that only when the clock signal318is low, the latch value is allowed to change, while, for high clock values the output of the latch406remains unchanged (rows 2, 4, 6, and 8 of table 2) and the pull-up circuit604is not activated as clock signal318is one. In this case, the latch406drives the stored value.

According to table 4, whenever the input signal316is high and the clock318is low (rows 3 and 7 of table 4) the output320is an inversion of the input signal306. In this case, the control signal308is high and it connects the NMOS transistor706to the ground. Further, as the clock signal318controls the PMOS702, the low value of the clock signal318enables the PMOS702and connects it to the power supply. Therefore, when the clock signal318is low and the input signal316is high, both the PMOS and NMOS transistors702and708are switched on and the tri-state inverter402inverts the input signal306normally.

Alternately, whenever the input signal316is zero and the clock318is low (rows 1 and 5 of table 4), the output320is one, irrespective of the input signal306. As the control signal308is low, the NMOS transistor708is disconnected, but the PMOS702is switched on (low clock signal318). In this case, the pull-up circuit604is activated and it pulls the latch406value up regardless of the input signal306value. Note that if the input signal306is low (row 1), the pull-up path in the tri-state inverter402is also enabled, as clock signal318is low, however this does not cause any problem, because both, this pull up of the tri-state inverter402and the pull-up circuit604are trying to drive the output320high.

The latch406behaves transparently and forwards the input to the output when the clock signal318is low, as the tri-state inverter716is disabled. Alternately, when the clock signal318is high, the tri-state inverter716is enabled and the latch406behaves opaquely and forwards the last stored value.

In this manner, the exemplary NAND input latch600ofFIGS. 6-7performs the same operation as a NAND gate placed before a latch and provides a lower setup time for the input signal306as no series stack of transistors is present. Moreover, the sizing of the transistors in the NAND input latch600can be done independently to improve the performance.

In another embodiment, the functional-input sequential circuit300can be used for a functional flip-flop, such as a synchronous reset flip-flop, which can be created using a D flip-flop. In typical D flip-flops, a data signal is provided to an inverter at the input of the flip-flop. Replacing the inverter with a dual-input NAND gate can convert the flip-flop into a synchronous-reset flip-flop. One input of the NAND gate can be a data input, while the second input can be an active low clear/reset signal. However, replacing the inverter at the D flip-flop input with a NAND gate degrades the setup time for the data signal as the NAND gate includes a double NMOS series stack.

The functional-input sequential circuit300can replace the NAND gate flip-flop to improve the performance of the synchronous reset/clear flip-flop.FIG. 8illustrates a block diagram of an exemplary NAND input Flip-flop800, including the tri-state inverter402, a flip-flop802coupled to the tri-state inverter402, the pull-up circuit604coupled to the flip-flop802, and a NAND combinational logic circuit804driving the tri-state inverter402. The clock signal318and an active low clear signal806drive the pull-up circuit604. The NAND combinational logic circuit804performs a logical NAND operation on an active low clear signal806and the inverted clock signal414, producing the control signal308. Further, the control signal312can be derived by inverting the control signal308at inverter808.

In an alternate implementation, an inverter followed by a transmission gate can replace the tri-state inverter402. This in case, the control signals308and312control the transmission gate. In this example, the input signals are the active low clear signal806and a data signal. It will be appreciated that this is merely exemplary and any other input signals can be utilized, such as set signals, reset signals, enable signal, and scan signals.

FIG. 9illustrates the circuit diagram900of the exemplary NAND input flip-flop800diagrammed inFIG. 8. The tri-state inverter402receives an input signal, which can be the data signal902. In addition, the tri-state inverter402receives two control signals, i.e., a first and second control signals. The control signal308is the output of the NAND combinational logic circuit804. The control signal312is nothing but an inversion of the control signal308. The control signal308is supplied to an active low switch, such as a PMOS transistor904that connects the data signal902to the power supply, while the control signal312controls an active high switch, such as an NMOS transistor906that connects the data signal902to the ground.

The flip-flop802, which is a conventional master-slave delay (D) flip-flop, receives the output320of the tri-state inverter402. It will be appreciated that any other type of flip-flop can be utilized, and the D flip-flop used here is merely to illustrate the operation of the NAND input flip-flop800. Additionally, the pull-up circuit604is coupled to the flip-flop802, and the active low clear signal806together with the clock signal318control the pull-up circuit604. If both the signals are low, the pull-up circuit604forces the flip-flop802value high.

In one embodiment, the NAND combinational logic circuit804includes an inverter908and a NAND gate910. The inverter908inverts the clock signal318and the inverted clock signal414is provided to the NAND gate910along with the active low clear signal806. The output of the NAND gate910(control signal308) is provided to the PMOS transistor904. Further, an inverter912inverts the output of the NAND gate910and the inverted output, which is the control signal312is provided to the NMOS transistor906.

The operation of the NAND input flip-flop800will now be described with reference toFIG. 8andFIG. 9. Table 5 depicts a typical NAND truth table, while table 6 depicts the operation of the exemplary NAND input flip-flop800.

TABLE 5Truth table for NANDCLRZDataOutput806902320001011101110

As depicted in table 6, when the active low clear signal806is one, the output320follows the inverted data signal902, however when the active low clear signal806is low, the output320is one irrespective of the data signal902. In order to achieve this output320, the control signals308and312gate the tri-state inverter402.

As depicted in Table 6 andFIG. 9, when the clock signal318is low, and the clear signal806is one (rows 5 and 7 of table 6), the PMOS transistor904and the NMOS transistor906connect the tri-state inverter402to the power supply and the ground (as the control signal308is zero and the control signal312is one). In this situation, the tri-state inverter402operates normally, i.e., it inverts the data signal902and provides the inverted signal to the flip-flop802at the master latch input. Further, when the clock signal318is low, the master latch opens (and it accepts the input from the tri-state inverter402), while the slave latch is closed, and the slave latch drives the output.

When clock signal318is high (rows 2, 4, 6, and 8 of the table 6), the PMOS transistor904and the NMOS transistor906disconnect the tri-state inverter402from the power supply and the ground, thereby disabling the tri-state inverter402. The master latch of the flip-flop802closes and drives the output, while the slave latch opens.

Alternately, when the clear signal806is low and the clock signal318is low (rows 1 and 3 of table 6), the tri-state inverter402is gated as the first control signal is one and the second control signal is zero. Nevertheless, since the clock signal318is low, the master latch becomes active. Further, the low clock signal enables the pull-up circuit604, which forces the value of the master latch high. When the clock signal318makes a transition from low to high, the master latch closes and the slave latch opens, clearing the output. However, when the clock signal318makes a transition from high to low, the pull-up circuit604forces the value of the master latch high, the master latch opens and the slave latch closes. This scenario ensures that the output of the flip-flop802remains unchanged. Therefore, the combination of the tri-state inverter, the NAND combinational logic circuit804, and the pull-up circuit604provide the same result as a NAND gate, however, the set-up time for the data signal902is substantially reduced, because the series stacking of transistors is avoided. This is because the active low clear signal806has been removed from the critical path and placed in the NAND combinational logic circuit804, reducing the set-up time for the data signal902.

FIG. 10depicts an alternate embodiment of the functional flip-flop. The block diagram depicts a NOR input flip-flop1000, it includes the tri-state inverter402that receives the input signal306, the flip-flop802connected to the output of the tri-state inverter402, the pull-down circuit410coupled to the flip-flop802, and an OR combinational logic circuit1002controlling the gating logic of the tri-state inverter402. The OR combinational logic circuit1002performs a logical OR operation on the input signal316and the clock signal318. The output of the OR combinational logic circuit1002(control signal308) and the inverted clock signal414(control signal312) control the tri-state inverter402. Further, the pull-down circuit410that forces the master latch of the flip-flop802to zero logic is controlled by the input signal316and the inverted clock signal414. A high input signal316and a low clock signal318enable the pull-down circuit410.

The operation of the NOR input flip-flop1000is similar to the operation of the NOR input latch400. Further, any input signals can be applied to the NOR input flip-flop1000. For example, a data signal902can be the input signal306, while a reset, set, scan, or a second data signal can be the input signal316. In another embodiment, the NOR input flip-flop1000can function for more than two inputs. A first input can be supplied to the tri-state inverter402, while the other inputs can be supplied to the combinational logic circuit310.

Exemplary Method

FIG. 11is a flowchart of a method1100for performing a logical function on at least one input signal in a functional-input sequential circuit. The method1100will be described with reference to components shown inFIGS. 3-10and the accompanying description, above. The method1100includes steps directed towards performing a logical function such as an OR, NOR, AND, or NAND operation.

At step1102, a first input signal and a second input signal are received. In one implementation, the first input signal306is provided to a transmission circuit, such as the transmission circuit302. Examples of transmission circuits include, but are not limited to, tri-state inverters, inverters followed by transmission gates, buffers followed by transmission gates, and switches. A combinational logic circuit, such as the combinational logic circuit310receives the second input signal316. In one embodiment, the input signal306or the input signal316can include more than one signal. Examples of first and second input signals include, but are not limited to, data signals, test signals, enable signals, scan signals, set signals and reset signals. Further, in another embodiment, one of the first or second input signals can be a non-critical signal.

A combinational logic operation is performed on the input signal316and a clock signal318at step1104to obtain a control signal. In one embodiment, the combinational logic circuit310performs the logical operation. The particular combinational logic operation performed will be dictated by the requirements of the application in question. For example, for a NOR-input sequential circuit the combinational logic circuit310performs a logical OR operation. Examples of other combinational logic operations can include any combinations of NAND, NOR, AND, OR, and NOT operations. The output of the combinational logic circuit310is the control signal308.

At step1106, the first input signal306is controlled by the first control signal308and a second control signal. In one implementation, the second control signal312can be employed to control the first input signal306. The control signal312can vary depending on the application in questions. For example, the control signal312can be the clock signal318, the inverted clock signal414, and the inverted control signal308. In one embodiment, the control signals308and312are provided to the transmission circuit302. Based on the values of the control signals308and312the transmission circuit302can either pass the input signal306or block it. In embodiment, where the transmission circuit302is a tri-state inverter402or an inverter followed by transmission gates, the first input signal306is inverted and the inverted input signal306is provided as the output320of the tri-state inverter402.

At step1108, the output320is received and stored in a digital storage element, such as the digital storage element304. The digital storage element304can be a latch or a flip-flop. The input signals that are allowed to pass at the transmission circuit302reach the digital storage element304. The digital storage element304stores the output signal320for a clock period. In case the clock signal318is low, the digital storage element304behaves transparently and forwards the signal at its input to the output. If the clock signal318is high, the digital storage element304stores the output320until the clock signal318becomes low.

In cases when the input signal306is blocked and when the clock signal318is low, the value of the digital storage element304is controlled at step1110. In one embodiment, a control circuit314, such as a pull-up or a pull-down circuit is employed to control the digital storage element value. In case of a pull-down circuit, such as the pull-down circuit410, the digital storage element304value is pulled down to a logic zero, while in case of a pull-up circuit, such as the pull-up circuit604, the digital storage element304value is pulled up to a logic one. The control circuit314controls the value of the digital storage element304depending on the value of the input signal306, the input signal316, and the clock signal318.

The output of the digital storage element is obtained at step1112. This output is a logical function of the input signals306and316. Therefore, the logical function at the input of a sequential circuit is carried out by separating the two input signals, providing one input signal306to a transmission circuit302and using the second input signal316to obtain a control signal308that controls the operation of the transmission circuit302. Further, the control circuit314helps realize the logical function. For example, instead of employing a NOR gate for a NOR operation, a transmission gate, a combinational logic circuit, and a control circuit are used to obtain the same functionality as a NOR gate. However, the set-up time of the input signal is substantially reduced, as the series-stacking present in a typical NOR gate has been removed, and the input path includes a single signal.