Self-calibrating gain control circuit for low noise amplifier

An amplifier comprises a Low Noise Amplifier (LNA) that amplifies a Radio Frequency (RF) signal that includes a transconductance, a gain and an input stage that receives the RF signal. A bias assembly includes a bias circuit with a bias resistance and generates a bias current for the input stage of the LNA, which is related to the bias resistance. A shunt feedback stage amplifies an output of the input stage, generates an RF output and includes a shunt resistance. Changes in the bias resistance due to changes in conditions are substantially offset by changes in the shunt resistance due to the changes in conditions, which reduces variation of the gain of the LNA based on the changes in conditions.

TECHNICAL FIELD

This invention relates to low noise amplifiers (LNA).

BACKGROUND

One of the key building blocks of a conventional RF transceiver is a Low Noise Amplifier (LNA).FIG. 1shows an implementation of a CMOS LNA high gain path200commonly adopted in conventional RF transceivers. The gain of this amplifier can be expressed as:Av=gm·Q2·Rpwhere gm is the transconductance of the input device, Q is the quality factor of the load inductor and Rpis the parasitic resistance associated with the inductor.

Referring to the equation above, the gain is a strong function of gm of the input transistor, as well as the Q of the inductor of the LNA. gm may vary +/−30-40%, and the Q2Rpterm typically varies +/−10-20% due to process, temperature etc. variation. As a result, the gain of the LNA can easily vary by greater than 6 dB. This gain variation may affect receiver performance significantly in real life applications and hence, the implementation may not be desirable.

SUMMARY

An amplifier comprises a Low Noise Amplifier (LNA) that amplifies a Radio Frequency (RF) signal and that includes a transconductance, a gain and an input stage that receives the RF signal. A bias assembly includes a bias circuit with a bias resistance and generates a bias current for the input stage of the LNA, which is related to the bias resistance. A shunt feedback stage amplifies an output of the input stage, generates an RF output and includes a shunt resistance. Changes in the bias resistance due to changes in conditions are substantially offset by changes in the shunt resistance due to the changes in conditions, which reduces variation of the gain of the LNA based on the changes in conditions.

In other features, the bias resistance and the shunt resistance include the same type of resistors. The conditions include at least one of process, temperature, environmental, and/or power variations. The bias resistance and the shunt resistance include poly resistors.

In other features, an integrated circuit comprises the amplifier. The shunt resistance is arranged on the integrated circuit in close proximity to the bias resistance such that the conditions of the bias resistance substantially mirror the conditions of the shunt resistance.

In other features, the bias circuit further includes a first transistor having a gate, a source and a drain. A second transistor has a gate, a source, and a drain. The gate and drain of the second transistor and the gate of the first transistor communicate. A source of the first transistor communicates with a first end of the bias resistance. The bias circuit further includes a current mirror that communicates with the drains of the first and second transistors and that outputs the bias current. The bias circuit further includes a bias current buffer that communicates with the current mirror and that supplies a buffered current based on the bias current. The current mirror includes a third transistor that has a first size and that communicates with the drain of the first transistor. A fourth transistor has a second size and communicates with the drain of the second transistor. The first size is substantially equal to the second size.

DETAILED DESCRIPTION

FIG. 2shows an aspect of a wireless transceiver210for communicating information. The receive path of the wireless transceiver210may include an amplifier212for amplifying an input signal214. The amplifier212may include a bias assembly218and LNA216constructed in accordance with the principles of the invention. A mixer222may combine the amplified input signal with a Radio Frequency (RF) LO signal224. A filter226and adjustable amplifier223may filter and amplify the combined signal, and mix the generated signal with an Intermediate Frequency (IF) LO signal down to baseband for possibly further amplification and filtering. An analog-to-digital converter (ADC)228may convert the mixed signal to a digital signal for further processing.

In the transmit path, a digital-to-analog converter227may convert a digital signal to an analog signal for transmission by a transmitter225.

FIG. 3shows an aspect of an amplifier230for generating an RF output. The amplifier230is configured to compensate for gain variations that may be caused by process and environmental variations. The amplifier230is suitable for assembly as an integrated circuit fabricated with CMOS techniques. The amplifier230includes a bias assembly232for supplying a bias current, lout, to an LNA234. A bias current buffer236may be connected between the bias assembly232and LNA234to level shift and amplify the bias current.

In one aspect, the LNA234may include an input stage238and a shunt feedback stage240to amplify an RFinsignal242. To compensate for gain changes related to resistive component variations in the shunt feedback stage240, the bias assembly232may be configured to have a resistive variation that is about inversely proportional to the shunt feedback stage resistive variation. The bias assembly232may, for example, include a bias circuit244to generate the bias current as a function of a bias resistor246, where environmental variations of the bias resistor resistance may partially or completely cancel resistance variations of the shunt feedback stage240.

In another aspect, the LNA234may include an input stage238to amplify the RFinsignal242, but not include a shunt feedback stage240. A bias assembly232may include a bias circuit244to generate the bias current as a function of a bias resistor246. The bias resistor246may be either an on-chip resistor or an external resistor. If an on-chip resistor is used, the bias assembly232may also include a calibration circuit248to partially or completely cancel resistance variations of the bias resistor246.

FIG. 4shows an aspect of a bias assembly10for supplying a bias current, lout, to an LNA (not shown). The bias assembly10is suitable for assembly as an integrated circuit fabricated with CMOS techniques. The bias assembly10includes a bias circuit12and a calibration circuit14. The bias circuit12generates the bias current as a function of a bias impedance16. The bias impedance16may be controlled in response to a control signal18from the calibration circuit14to maintain a relatively constant value over variations in operating conditions such as process variations and environmental conditions variations.

Referring toFIG. 5, several configurations of the bias impedance are shown. A hybrid configuration50includes a series string of resistors52and control transistors54that are connected in shunt with one or more of the resistors52. A series configuration60includes a series string of resistors62with control transistors64that are connected in shunt with each resistor62. A shunt configuration70includes groupings of a resistor72connected in series with a control transistor74and the series combinations of resistor-transistor connected in shunt. The resistors in each of the configurations may be made from any suitable material including N+ poly and P+ poly.

Referring toFIG. 4, a bias voltage that may include temperature and process compensation is applied across the bias impedance16to generate the bias current. The bias current is supplied to a current mirror20that may reflect the bias current to a buffer22. The buffer22supplies the bias current to an LNA (not shown) and may be configured as either a P Metal Oxide Semiconductor (PMOS) or an NMOS current mirroring gain buffer. The device characteristics of the buffer22may be varied in relation to the current mirror20to change the amplitude of the bias current supplied by the buffer22. For example, the size of the buffer22may be varied relative to the current mirror to cause a corresponding change in the current supplied.

The calibration circuit14may determine the effect of process and environmental variations on a calibration impedance24such as a poly resistor. The calibration impedance24preferably is constructed from similar material, has a similar configuration, and is located in close proximity to the bias impedance16so that changes in the calibration impedance24may track changes in the bias impedance16. A reference current, Iref,26may be applied to the calibration impedance24to generate a calibration voltage that is compared to a reference voltage, Vref,28. The reference current26may be generated from a fixed voltage such as the reference voltage28and a fixed resistor that maintains a predictable value over process and environmental variations. A comparator30monitors changes in the calibration impedance24relative to the voltage reference28. A latch32may latch the output of the comparator30synchronous to a clock. A calibration control circuit34may delay the latch output to reduce the impact of noise generated at the clock edges. The calibration control circuit34may include control logic and a up/down counter38. A calibration signal, CAL, enables the calibration control circuit34. A clock signal, Clk2, provides a timing reference for the counter38. A decoder40interprets the signal from the calibration control circuit34and in response may control the resistance of the calibration impedance24by enabling or disabling control transistors.

FIG. 6shows an aspect of a bias circuit80for generating an LNA bias current. The bias circuit80may include a PMOS current mirror pair, Q3and Q4, and a pair of NMOS transistors, Q1and Q2,82and84for generating a controlled current, Is, through a resistor, Rs,86. A size ratio, K, of Q1and Q2is selected to provide a desired current amplitude of Is. The following equations show the relation between the transconductance of Q1and Rs, if the currents flowing through Q1and Q2are equal,2⁢Isμ⁢⁢C⁢WL+VTH1=2⁢Isμ⁢⁢C⁡(WL)·K+VTH2+Is·Rs

The pair of PMOS transistors, Q3and Q4,88and90may be selected to have the same size so that the currents flowing through drains of Qland Q2are substantially equal. With equal currents in Q1and Q2, the relationship described by Equation 1 is maintained. A buffer92is preferably the same type of transistor as Q3and Q4,88and90, and may be sized in relation to Q3to vary the amplitude of current, lout flowing from the buffer92. For example, if the buffer92is selected to be three times larger than Q3, then Iout1will be three times larger than Is. A current mirror94including transistors Q6and Q7may be connected to the buffer92to set a bias current, Iout2, of an LNA95. The ratio of the sizes of Q6and Q7may be varied to change the amplitude of Iout2with respect to Iout1.

If the size ratio of Q5and Q3is M and the ratio of Q7and Q6is N, then the bias current Iout2flowing into Q7will be:gm,Q7=2⁢μ⁢⁢C⁡(WL)·Iout2=2⁢MNRs⁢(1-1K)

It can be seen that the transconductance of the LNA input stage is predominately dependent on the resistor value Rs. Rsmay be implemented as an external resistor or an on chip resistor. If Rsis implemented as an on chip resistor, then the resistance value of Rswill vary with process and environmental variations. The variation of the LNA gain to process and environmental changes may be reduced by using any of several techniques including 1) a calibration scheme to reduce the variation of Rswith process and environmental changes, and 2) adding a shunt feedback stage to cancel out the resistor variation.

In one aspect, the LNA95may include an input stage96to amplify an RF input signal, RFin. Recall that the gain of the LNA is:Av=gm·Q2·Rp∝Q2⁢RpRs

Since Rswill be calibrated, the Q2Rp term becomes the dominant contributor of gain variation, varying by about 10%-20%.

In another aspect, the LNA95may also include a shunt feedback stage97connected to the input stage96to further amplify RFin. The gain of this LNA can be expressed as:Av=gm·Rf∝RfRs,
where Rfis the shunt feed back resistor. If Rfis chosen to be the same type of resistor as Rs, a good match can be achieved, leading to improved gain accuracy.

FIG. 7shows an operation for amplifying an RF signal. Starting at block100, a bias voltage may be generated by a two transistor circuit. The bias voltage may be equal to the difference between the Vgsvoltages of the two transistors. At block102, the bias voltage is applied across a bias impedance to generate a bias current. The bias impedance may be controllable and may include one or more poly resistors in combination with switches. The magnitude of the bias current may be a function of the poly resistors and the physical characteristics of the two transistors including size ratio, width, length, and capacitance. At block104, the bias current is mirrored to generate an output current that is a function of the poly resistance.

In one aspect, at block106, a reference current is generated. At block108, the reference current is supplied to a controlled calibration impedance that may include several poly resistors in combination with switches. At block110, the voltage developed across the controlled calibration impedance may be compared to a reference voltage. At block112, the impedance of the controlled calibration impedance may be controlled as a function of the comparison to reduce the difference between the reference voltage and the voltage developed across the controlled calibration impedance. Different ones of the control switches are turned on or off to effect the desired control. At block114, a control signal may be generated to indicate the change in the controlled calibration impedance that cancels the difference between the reference voltage and the voltage developed across the controlled calibration impedance. The control signal may indicate the state of each of the control switches. At block116, the impedance of the controlled bias impedance may be controlled in response to the control signal so that changes in the poly resistance are compensated for by effecting the same changes to the controlled bias impedance that are effected for the controlled calibration impedance. Variations in the resistance of the poly resistors caused by process, environmental conditions, and operating conditions may be compensated for by controlling for the change in resistance of the controlled calibration impedance poly resistors and mirroring that control to the controlled bias impedance poly resistors. By compensating for changes in the resistance of the poly resistors, the transconductance of the LNA may be held constant over process variations and environmental conditions resulting in a relatively constant LNA gain, with the dominant variation resulting from the effective impedance from the inductor tank.

In another aspect, continuing from block104to block118an LNA is biased with the output current. The LNA may include an input stage to receive an RF input signal. At block120, a portion of the amplified RF input signal may be communicated to the input stage using a shunt resistor to provide feedback. Variations in the shunt resistor may be compensated for by variations in the bias impedance to cause the gain of the amplifier to be substantially independent of changes in conditions that affect the values of the resistors.