Display substrate, display apparatus, and method of fabricating display substrate

A display substrate has a display area and a peripheral area. The display substrate includes a base substrate; a first insulating layer on the base substrate and in at least the peripheral area; a plurality of light emitting elements on the base substrate and in the display area; and an encapsulating layer on a side of the plurality of light emitting elements distal to the base substrate to encapsulate the plurality of light emitting elements. The encapsulating layer includes a first inorganic encapsulating sublayer extending from the display area into the peripheral area. The display substrate has a groove extending into the first insulating layer in the peripheral area, forming a first perimeter substantially surrounding the display area. The first inorganic encapsulating sublayer extends into at least a portion of the groove.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a national stage application under 35 U.S.C. § 371 of International Application No. PCT/CN2018/113653, filed Nov. 2, 2018, the contents of which are incorporated by reference in the entirety.

TECHNICAL FIELD

The present invention relates to display technology, more particularly, to a display substrate, a display apparatus, and a method of fabricating a display substrate.

BACKGROUND

Organic light emitting diode (OLED) display apparatuses are self-emissive devices, and do not require backlights. OLED display apparatuses also provide more vivid colors and a larger color gamut as compared to the conventional liquid crystal display (LCD) apparatuses. Further, OLED display apparatuses can be made more flexible, thinner, and lighter than a typical LCD apparatus. An OLED display apparatus typically includes an anode, an organic layer including an organic light emitting layer, and a cathode. OLEDs can be either a bottom-emission type OLED or a top-emission type OLED.

SUMMARY

In one aspect, the present invention provides a display substrate having a display area and a peripheral area, comprising a base substrate; a first insulating layer on the base substrate and in at least the peripheral area; a plurality of light emitting elements on the base substrate and in the display area; and an encapsulating layer on a side of the plurality of light emitting elements distal to the base substrate to encapsulate the plurality of light emitting elements; wherein the encapsulating layer comprises a first inorganic encapsulating sublayer extending from the display area into the peripheral area; the display substrate has a groove extending into the first insulating layer in the peripheral area, forming a first perimeter substantially surrounding the display area; and the first inorganic encapsulating sublayer extends into at least a portion of the groove.

Optionally, the first inorganic encapsulating sublayer extends into the groove substantially around the first perimeter.

Optionally, the encapsulating layer further includes a second inorganic encapsulating sublayer on a side of the first inorganic encapsulating sublayer distal to the base substrate; and the second inorganic encapsulating sublayer extends into at least a portion of the groove.

Optionally, the second inorganic encapsulating sublayer extends into the groove substantially around the first perimeter.

Optionally, the groove has a depth along a direction from the first insulating layer to the base substrate greater than 50 nm.

Optionally, the groove has a width along a direction from the display area to the peripheral area greater than 10 μm.

Optionally, the groove extends into a plurality of insulating layers comprising the first insulating layer.

Optionally, the groove extends into the first insulating layer, a second insulating layer on a side of the first insulating layer distal to the base substrate, and a third insulating layer on a side of the second insulating layer distal to the base substrate; and the third insulating layer is an inter-layer dielectric layer.

Optionally, the display substrate further comprises a crack barrier layer on the base substrate and in the peripheral area.

Optionally, the display substrate has one or more trenches extending into the first insulating layer in the peripheral area, forming one or more second perimeters each of which substantially surrounding the first perimeter; and the crack barrier layer extends into the one or more trenches.

Optionally, the one or more trenches has a depth along a direction from the first insulating layer to the base substrate substantially same as a depth of the groove along the direction from the first insulating layer to the base substrate.

Optionally, the crack barrier layer comprises a first barrier sublayer and a second barrier sublayer on a side of the first barrier sublayer distal to the base substrate; and the first barrier sublayer extends into the one or more trenches.

Optionally, the display substrate further comprises a planarization layer in the display area; and a pixel definition layer defining a plurality of subpixel apertures on a side of the planarization layer distal to the base substrate; wherein the first barrier sublayer and the planarization layer are in a same layer and comprises a same material; and the second barrier sublayer and the pixel definition layer are in a same layer and comprises a same material.

Optionally, the display substrate further comprises a dam layer on a side of the first insulating layer distal to the base substrate; wherein the dam layer forms a third perimeter defining the display area.

Optionally, the dam layer comprises a first dam sublayer on a side of the first insulating layer distal to the base substrate; a second dam sublayer on a side of the first dam sublayer distal to the first insulating layer; and a third dam sublayer on a side of the second dam sublayer distal to the first dam sublayer.

Optionally, the display substrate further comprises a planarization layer in the display area; a pixel definition layer defining a plurality of subpixel apertures on a side of the planarization layer distal to the base substrate; and a spacer layer for spacing apart the display substrate from a counter substrate in a display panel comprising the display substrate; wherein the first dam sublayer and the planarization layer are in a same layer and comprises a same material; the second dam sublayer and the pixel definition layer are in a same layer and comprises a same material; and the third dam sublayer and the spacer layer are in a same layer and comprises a same material.

In another aspect, the present invention provides a display apparatus comprising the display substrate described herein or fabricated by a method described herein; and a counter substrate facing the display substrate.

In another aspect, the present invention provides a method of fabricating a display substrate having a display area and a peripheral area, comprising forming a first insulating layer on a base substrate and in at least the peripheral area; forming a groove extending into the first insulating layer in the peripheral area, the groove forming a first perimeter substantially surrounding the display area; forming a plurality of light emitting elements on the base substrate and in the display area; and forming an encapsulating layer on a side of the plurality of light emitting elements distal to the base substrate to encapsulate the plurality of light emitting elements; wherein forming the encapsulating layer comprises forming a first inorganic encapsulating sublayer extending from the display area into the peripheral area; and the first inorganic encapsulating sublayer is formed so that the first inorganic encapsulating sublayer extends into at least a portion of the groove.

Optionally, the method further comprises forming one or more trenches extending into the first insulating layer in the peripheral area, the one or more trenches forming one or more second perimeters each of which substantially surrounding the first perimeter; and forming a crack barrier layer on the base substrate and in the peripheral area; wherein the crack barrier layer is formed so that the crack barrier layer extends into the one or more trenches.

Optionally, the method further comprises forming a planarization layer in the display area; forming a pixel definition layer defining a plurality of subpixel apertures on a side of the planarization layer distal to the base substrate; forming a spacer layer for spacing apart the display substrate from a counter substrate in a display panel comprising the display substrate; and forming a dam layer on a side of the first insulating layer distal to the base substrate, the dam layer forming a third perimeter defining the display area; wherein forming the crack barrier layer comprises forming a first barrier sublayer and forming a second barrier sublayer on a side of the first barrier sublayer distal to the base substrate; and forming the dam layer comprises forming a first dam sublayer on a side of the first insulating layer distal to the base substrate, forming a second dam sublayer on a side of the first dam sublayer distal to the first insulating layer; and forming a third dam sublayer on a side of the second dam sublayer distal to the first dam sublayer, wherein the first barrier sublayer, the first dam sublayer, and the planarization layer are formed in a same layer in a single patterning process using a same material and a single mask plate; the second barrier sublayer, the second dam sublayer, and the pixel definition layer are formed in a same layer in a single patterning process using a same material and a single mask plate; the third dam sublayer and the spacer layer formed in a same layer in a single patterning process using a same material and a single mask plate; and the groove and the one or more trenches are formed in a single patterning process using a single mask plate.

DETAILED DESCRIPTION

It is discovered in the present disclosure that inorganic encapsulating sublayers of an encapsulating layer in a display substrate is prone to being peeling off an insulating layer of the display substrate, particularly when subject to external force, leading to defects in encapsulation.

Accordingly, the present disclosure provides, inter alia, a display substrate, a display apparatus, and a method of fabricating a display substrate that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides a display substrate having a display area and a peripheral area. In some embodiments, the display substrate includes a base substrate; a first insulating layer on the base substrate and in at least the peripheral area; a plurality of light emitting elements on the base substrate and in the display area; and an encapsulating layer on a side of the plurality of light emitting elements distal to the base substrate to encapsulate the plurality of light emitting elements. Optionally, the encapsulating layer includes a first inorganic encapsulating sublayer extending from the display area into the peripheral area. Optionally, the display substrate has a groove extending into the first insulating layer in the peripheral area, forming a first perimeter substantially surrounding the display area. Optionally, the first inorganic encapsulating sublayer extends into at least a portion of the groove.

As used herein, the term “display area” refers to an area of a display substrate (e.g., an opposing substrate or an array substrate) in a display panel where image is actually displayed. Optionally, the display area may include both a subpixel region and an inter-subpixel region. A subpixel region refers to a light emission region of a subpixel, such as a region corresponding to a pixel electrode in a liquid crystal display or a region corresponding to a light emissive layer in an organic light emitting diode display panel. An inter-subpixel region refers to a region between adjacent subpixel regions, such as a region corresponding to a black matrix in a liquid crystal display or a region corresponding a pixel definition layer in an organic light emitting diode display panel. Optionally, the inter-subpixel region is a region between adjacent subpixel regions in a same pixel. Optionally, the inter-subpixel region is a region between two adjacent subpixel regions from two adjacent pixels.

As used herein the term“peripheral area” refers to an area of a display substrate (e.g., an opposing substrate or an array substrate) in a display panel where various circuits and wires are provided to transmit signals to the display substrate. To increase the transparency of the display apparatus, non-transparent or opaque components of the display apparatus (e.g., battery, printed circuit board, metal frame), can be disposed in the peripheral area rather than in the display areas.

As used herein the term “substantially surrounding” refers to surrounding at least 50% (e.g., at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, and 100%) of a perimeter of an area.

FIG. 1is a schematic diagram illustrating the structure of a display substrate in some embodiments according to the present disclosure.FIG. 3is a plan view of a display substrate in some embodiments according to the present disclosure. Referring toFIG. 1andFIG. 3, the display substrate in some embodiments has a display area DA and a peripheral area PA. The display substrate in some embodiments includes a base substrate10; a first insulating layer21on the base substrate10and in at least the peripheral area PA. InFIG. 1, the first insulating layer21extends from the display area DA into at least a part of the peripheral area PA. The display substrate further optionally includes a plurality of light emitting elements LE on the base substrate10and in the display area DA, and an encapsulating layer on a side of the plurality of light emitting elements LE distal to the base substrate10to encapsulate the plurality of light emitting elements LE. Optionally, and referring toFIG. 1, the encapsulating layer includes a first inorganic encapsulating sublayer41extending from the display area DA into the peripheral area PA.

FIG. 2Ais a schematic diagram illustrating the structure of an encapsulating layer in some embodiments according to the present disclosure. Referring toFIG. 2A, the encapsulating layer in some embodiments may include multiple sublayers, including one or more inorganic encapsulating sublayers and one or more organic encapsulating sublayers for enhanced encapsulation ability to prevent oxygen or moist from entering the display substrate. In one example shown inFIG. 2A, the encapsulating layer40includes a first organic encapsulating sublayer43, a first inorganic encapsulating sublayer41on the first organic encapsulating sublayer43, a second organic encapsulating sublayer44on a side of the first inorganic encapsulating sublayer41distal to the first organic encapsulating sublayer43, and a second inorganic encapsulating sublayer42on a side of the second organic encapsulating sublayer44distal to the first inorganic encapsulating sublayer41.

FIG. 2Bis a schematic diagram illustrating the structure of display substrate in a display area in some embodiments according to the present disclosure. Referring toFIG. 2B, the display substrate in the display area includes a base substrate10, the first insulating layer21on the base substrate10, a planarization layer60on a side of the first insulating layer21distal to the base substrate10, a pixel definition layer70on a side of the planarization layer60distal to the base substrate10and defining a plurality of subpixel apertures, and a spacer layer90on a side of the pixel definition layer70distal to the base substrate10. The spacer layer90is configured to space apart the display substrate from a counter substrate in a display panel having the display substrate. Each of the plurality of light emitting elements LE in some embodiments includes a first electrode80, a light emitting layer81in a respective one of the plurality of subpixel apertures and on a side of the first electrode80distal to the base substrate10, and a second electrode82on a side of the light emitting layer81distal to the first electrode80. The second electrode82may be formed to extend throughout the display area in an open mask process.

Referring toFIG. 1, in some embodiments, the display substrate has a groove G1extending into the first insulating layer21in the peripheral area PA, forming a first perimeter substantially surrounding the display area DA. Optionally, the first inorganic encapsulating sublayer41extends into at least a portion of the groove G1. As used herein, the term “extend into” is used to refer to extending partially through or extending through completely. InFIG. 1, the groove G1only partially extends through the first insulating layer21.

In some embodiments, and referring toFIG. 1andFIG. 3, the first inorganic encapsulating sublayer41extends into the groove G1substantially around the first perimeter. For example, the first inorganic encapsulating sublayer41extends into the groove G1at every part of the first perimeter.

In some embodiments, the first inorganic encapsulating sublayer41extends into the groove G1at some parts of the first perimeter, but is absent in the groove G1at other parts of the first perimeter.

FIG. 4is a schematic diagram illustrating the structure of a display substrate in some embodiments according to the present disclosure. Referring toFIG. 4, the encapsulating layer in some embodiments further includes a second inorganic encapsulating sublayer42on a side of the first inorganic encapsulating sublayer41distal to the base substrate10. Similar to the first inorganic encapsulating sublayer41, the second inorganic encapsulating sublayer42also extends from the display area DA into the peripheral area PA. In the display substrate as shown inFIG. 4, the second inorganic encapsulating sublayer42does not extend into the groove G1.

FIG. 5is a schematic diagram illustrating the structure of a display substrate in some embodiments according to the present disclosure. Referring toFIG. 5, the encapsulating layer in some embodiments further includes a second inorganic encapsulating sublayer42on a side of the first inorganic encapsulating sublayer41distal to the base substrate10. In the display substrate as shown inFIG. 5, not only the first inorganic encapsulating sublayer41extends into at least a portion of the groove G1, but also the second inorganic encapsulating sublayer42extends into at least a portion of the groove G1. InFIG. 5, the groove G1extends through the first insulating layer21.

In some embodiments, the second inorganic encapsulating sublayer42extends into the groove G1substantially around the first perimeter. For example, the second inorganic encapsulating sublayer42extends into the groove G1at every part of the first perimeter.

In some embodiments, the second inorganic encapsulating sublayer42extends into the groove G1at some parts of the first perimeter, but is absent in the groove G1at other parts of the first perimeter.

Referring toFIG. 1, in some embodiments, the groove G1has a depth D along a direction from the first insulating layer21to the base substrate10. Optionally, the depth D is greater than 50 nm, e.g., greater than 100 nm, greater than 200 nm, greater than 300 nm, greater than 400 nm, greater than 500 nm, greater than 600 nm, greater than 700 nm, greater than 800 nm, greater than 900 nm, and greater than 1000 nm. Optionally, the depth D is in a range of approximately 500 nm to approximately 700 nm, e.g., approximately 600 nm.

Referring toFIG. 1, in some embodiments, the groove G1has a width W along a direction from the display area DA to the peripheral area PA. Optionally, the width W is greater than 10 μm, e.g., greater than 20 μm, greater than 30 μm, greater than 40 μm, greater than 50 μm, greater than 60 μm, greater than 70 μm, greater than 80 μm, greater than 90 μm, greater than 100 μm, greater than 150 μm, greater than 200 μm, and greater than 500 μm. Optionally, the width W is in a range of approximately 50 μm to approximately 150 μm, e.g., approximately 100 μm.

Referring toFIGS. 1, 4, and 5, in some embodiments, the display substrate further includes a crack barrier layer50on the base substrate10and in the peripheral area PA. The crack barrier layer50is on a side of the groove G1distal to the display area DA. Optionally, the crack barrier layer50is formed to surround the first perimeter formed by the groove G1.

In some embodiments, the display substrate has one or more trenches T extending into the first insulating layer21in the peripheral area PA, forming one or more second perimeters each of which substantially surrounding the first perimeter. The crack barrier layer50extends into the one or more trenches T. Optionally, the one or more trenches T and the groove G1are formed in a single patterning process (e.g., a same etching process) using a single mask plate. Optionally, the one or more trenches T has a depth along a direction from the first insulating layer21to the base substrate10substantially same as a depth of the groove G1along the direction from the first insulating layer21to the base substrate10. Optionally, the depth of the one or more trenches T is greater than 50 nm, e.g., greater than 100 nm, greater than 200 nm, greater than 300 nm, greater than 400 nm, greater than 500 nm, greater than 600 nm, greater than 700 nm, greater than 800 nm, greater than 900 nm, and greater than 1000 nm. Optionally, the depth of the one or more trenches T is in a range of approximately 500 nm to approximately 700 nm, e.g., approximately 600 nm.

Referring toFIGS. 1, 4, and 5, in some embodiments, the display substrate further includes a dam layer30on a side of the first insulating layer21distal to the base substrate10. The dam layer30forms a third perimeter defining the display area DA, e.g., forming a boundary between the display area DA and the peripheral area PA. The first inorganic encapsulating sublayer41or the second inorganic encapsulating sublayer42climbs over the dam layer30and extends from the display area DA into the peripheral area PA.

In some embodiments, the groove G1extends into a plurality of insulating layers.FIG. 6is a schematic diagram illustrating the structure of a display substrate in some embodiments according to the present disclosure. Referring toFIG. 6, the display substrate includes a first insulating layer21, a second insulating layer22on a side of the first insulating layer21distal to the base substrate10, and a third insulating layer23on a side of the second insulating layer22distal to the base substrate10. The groove G1extends into (e.g., extends completely through) the first insulating layer21, the second insulating layer22, and the third insulating layer23.

In one example, the first insulating layer21is a first gate insulating layer of the display substrate, the second insulating layer22is a second gate insulating layer of the display substrate, and the third insulating layer23is an inter-layer dielectric layer of the display substrate.

Referring toFIG. 6again, in some embodiments, the crack barrier layer includes a first barrier sublayer51and a second barrier sublayer52on a side of the first barrier sublayer51distal to the base substrate10. Optionally, the first barrier sublayer51extends into the one or more trenches T. In some embodiments, the first barrier sublayer51and a planarization layer of the display substrate are in a same layer and are made of a same material. As used herein, the term “same layer” refers to the relationship between the layers simultaneously formed in the same step. In one example, the first barrier sublayer51and the planarization layer are in a same layer when they are formed as a result of one or more steps of a same patterning process performed in a same layer of material. In another example, first barrier sublayer51and the planarization layer can be formed in a same layer by simultaneously performing the step of forming first barrier sublayer51and the step of forming the planarization layer. The term “same layer” does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

In some embodiments, the second barrier sublayer52and a pixel definition layer (see, e.g.,FIG. 2B) of the display substrate are in a same layer and are made of a same material.

Referring toFIG. 6again, in some embodiments, the dam layer includes a first dam sublayer31on a side of the first insulating layer21distal to the base substrate10, a second dam sublayer32on a side of the first dam sublayer31distal to the first insulating layer21, and a third dam sublayer33on a side of the second dam sublayer32distal to the first dam sublayer31. Optionally, the first dam sublayer31and a planarization layer (see, e.g.,FIG. 2B) of the display substrate are in a same layer and are made of a same material. Optionally, the second dam sublayer32and a pixel definition layer (see, e.g.,FIG. 2B) of the display substrate are in a same layer and are made of a same material. Optionally, the third dam sublayer33and a spacer layer (see, e.g.,FIG. 2B) of the display substrate are in a same layer and are made of a same material.

Various appropriate insulating materials and various appropriate fabricating methods may be used to make the crack barrier layer50, the dam layer30, the pixel definition layer70, the planarization layer60, the first insulating layer21, the second insulating layer22, the third insulating layer23, and the spacer layer90. For example, an insulating material may be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of appropriate insulating materials for making the crack barrier layer50, the dam layer30, the pixel definition layer70, the planarization layer60, the first insulating layer21, the second insulating layer22, the third insulating layer23, and the spacer layer90include, but are not limited to, silicon oxide (SiOx), silicon nitride (SiNy, e.g., Si3N4), silicon oxynitride (SiOxNy), various resins, and various organic polymers.

In another aspect, the present disclosure provides a method of fabricating a display substrate having a display area and a peripheral area. In some embodiments, the method includes forming a first insulating layer on the base substrate and in at least the peripheral area; forming a groove extending into the first insulating layer in the peripheral area, the groove forming a first perimeter substantially surrounding the display area; forming a plurality of light emitting elements on the base substrate and in the display area; and forming an encapsulating layer on a side of the plurality of light emitting elements distal to the base substrate to encapsulate the plurality of light emitting elements.

Optionally, the step of forming the encapsulating layer includes forming a first inorganic encapsulating sublayer extending from the display area into the peripheral area. Optionally, the first inorganic encapsulating sublayer is formed so that the first inorganic encapsulating sublayer extends into at least a portion of the groove. Optionally, the first inorganic encapsulating sublayer is formed to extend into the groove substantially around the first perimeter.

Optionally, the step of forming the encapsulating layer further includes forming a second inorganic encapsulating sublayer on a side of the first inorganic encapsulating sublayer distal to the base substrate. Optionally, the second inorganic encapsulating sublayer is formed so that the second inorganic encapsulating sublayer extends into at least a portion of the groove. Optionally, the second inorganic encapsulating sublayer is formed so that the second inorganic encapsulating sublayer extends into the groove substantially around the first perimeter.

Optionally, the groove is formed to have a depth along a direction from the first insulating layer to the base substrate greater than 50 nm. Optionally, the depth is greater than 50 nm, e.g., greater than 100 nm, greater than 200 nm, greater than 300 nm, greater than 400 nm, greater than 500 nm, greater than 600 nm, greater than 700 nm, greater than 800 nm, greater than 900 nm, and greater than 1000 nm. Optionally, the depth is in a range of approximately 500 nm to approximately 700 nm, e.g., approximately 600 nm.

Optionally, the groove is formed to have a width along a direction from the display area to the peripheral area greater than 10 μm. Optionally, the width is greater than 10 μm, e.g., greater than 20 μm, greater than 30 μm, greater than 40 μm, greater than 50 μm, greater than 60 μm, greater than 70 μm, greater than 80 μm, greater than 90 μm, greater than 100 μm, greater than 150 μm, greater than 200 μm, and greater than 500 μm. Optionally, the width is in a range of approximately 50 μm to approximately 150 μm. e.g., approximately 100 μm.

In some embodiments, the method includes forming a plurality of insulating layers on the base substrate, one of which is the first insulating layer. Optionally, the groove is formed to extend into the plurality of insulating layers. In one example, the method includes forming a first insulating layer on the base substrate, forming a second insulating layer on a side of the first insulating layer distal to the base substrate, and forming a third insulating layer on a side of the second insulating layer distal to the base substrate. Optionally, the groove is formed to extend into the first insulating layer, a second insulating layer on a side of the first insulating layer distal to the base substrate, and a third insulating layer on a side of the second insulating layer distal to the base substrate. In one example, the first insulating layer is a first gate insulating layer of the display substrate, the second insulating layer is a second gate insulating layer of the display substrate, and the third insulating layer is an inter-layer dielectric layer of the display substrate.

In some embodiments, the method further includes forming a crack barrier layer on the base substrate and in the peripheral area. In some embodiments, prior to forming the crack barrier layer, the method further includes forming one or more trenches extending into the first insulating layer in the peripheral area. The one or more trenches forms one or more second perimeters each of which substantially surrounding the first perimeter. The crack barrier layer is formed so that the crack barrier layer extends into the one or more trenches. Optionally, the one or more trenches is formed to have a depth along a direction from the first insulating layer to the base substrate substantially same as a depth of the groove along the direction from the first insulating layer to the base substrate. Optionally, the groove and the one or more trenches are formed in a single patterning process using a single mask plate.

In some embodiments, the step of forming the crack barrier layer includes forming a first barrier sublayer and forming a second barrier sublayer on a side of the first barrier sublayer distal to the base substrate. Optionally, the first barrier sublayer is formed to extend into the one or more trenches.

In some embodiments, the method further includes forming a planarization layer in the display area, and forming a pixel definition layer defining a plurality of subpixel apertures on a side of the planarization layer distal to the base substrate. Optionally, the first barrier sublayer and the planarization layer are formed in a same layer in a single patterning process using a same material and a single mask plate. Optionally, the second barrier sublayer and the pixel definition layer are formed in a same layer in a single patterning process using a same material and a single mask plate.

In some embodiments, the method further includes forming a dam layer on a side of the first insulating layer distal to the base substrate. The dam layer forms a third perimeter defining the display area.

In some embodiments, the step of forming the dam layer includes forming a first dam sublayer on a side of the first insulating layer distal to the base substrate, forming a second dam sublayer on a side of the first dam sublayer distal to the first insulating layer; and forming a third dam sublayer on a side of the second dam sublayer distal to the first dam sublayer.

In some embodiments, the method further includes forming a planarization layer in the display area; forming a pixel definition layer defining a plurality of subpixel apertures on a side of the planarization layer distal to the base substrate; and forming a spacer layer for spacing apart the display substrate from a counter substrate in a display panel comprising the display substrate. Optionally, the first dam sublayer and the planarization layer are formed in a same layer in a single patterning process using a same material and a single mask plate. Optionally, the second dam sublayer and the pixel definition layer are formed in a same layer in a single patterning process using a same material and a single mask plate. Optionally, the third dam sublayer and the spacer layer formed in a same layer in a single patterning process using a same material and a single mask plate.

Optionally, the first barrier sublayer, the first dam sublayer, and the planarization layer are formed in a same layer in a single patterning process using a same material and a single mask plate. Optionally, the second barrier sublayer, the second dam sublayer, and the pixel definition layer are formed in a same layer in a single patterning process using a same material and a single mask plate. Optionally, the third dam sublayer and the spacer layer formed in a same layer in a single patterning process using a same material and a single mask plate.

FIGS. 7A to 7Dillustrate a process of fabricating a display substrate in some embodiments according to the present disclosure. Referring toFIG. 7A, a first insulating layer21is formed on the base substrate10, a second insulating layer22is formed on a side of the first insulating layer21distal to the base substrate10, and a third insulating layer23is formed on a side of the second insulating layer22distal to the base substrate10. In one example, the first insulating layer21is a first gate insulating layer of the display substrate, the second insulating layer22is a second gate insulating layer of the display substrate, and the third insulating layer23is an inter-layer dielectric layer of the display substrate. A plurality of light emitting element LE are formed in the display area DA of the display substrate. A dam layer, including a first dam sublayer31on a side of the first insulating layer21distal to the base substrate10, a second dam sublayer32on a side of the first dam sublayer31distal to the first insulating layer21, and a third dam sublayer33on a side of the second dam sublayer32distal to the first dam sublayer31, is formed on a side of the third insulating layer23distal to the base substrate10.

Referring toFIG. 7B, a groove G1and one or more trenches T are formed to extend into the first insulating layer21, the second insulating layer22, and the third insulating layer23.

Referring toFIG. 7C, a first barrier sublayer51is formed in the peripheral area PA and on a side of the groove G1distal to the display area DA. The first barrier sublayer51is formed to extend into the one or more trenches T. Further, a first inorganic encapsulating sublayer41of an encapsulating layer is formed to extend from the display area DA into the peripheral area PA. The first inorganic encapsulating sublayer41is formed to extend into at least a portion of the groove G1.

Referring toFIG. 7D, a second inorganic encapsulating sublayer42is formed on a side of the first inorganic encapsulating sublayer41distal to the base substrate10. The second inorganic encapsulating sublayer42is formed to extend into at least a portion of the groove G1. Further, a second barrier sublayer52is formed on a side of the first barrier sublayer51distal to the base substrate10.

FIGS. 8A to 8Eillustrate a process of fabricating a display substrate in some embodiments according to the present disclosure. Referring toFIG. 8A, a first insulating layer21is formed on the base substrate10, a second insulating layer22is formed on a side of the first insulating layer21distal to the base substrate10, and a third insulating layer23is formed on a side of the second insulating layer22distal to the base substrate10. In one example, the first insulating layer21is a first gate insulating layer of the display substrate, the second insulating layer22is a second gate insulating layer of the display substrate, and the third insulating layer23is an inter-layer dielectric layer of the display substrate.

Referring toFIG. 8B, a groove G1and one or more trenches T are formed to extend into the first insulating layer21, the second insulating layer22, and the third insulating layer23. The groove G1and the one or more trenches T are formed in a single patterning process using a single mask plate.

Referring toFIG. 8C, a planarization layer60is formed on a side of the first insulating layer21distal to the base substrate10, a first dam sublayer31is formed on a side of the first insulating layer21distal to the base substrate10to define the display area DA, and a first barrier sublayer51is formed in the peripheral area PA and on a side of the groove G1distal to the display area DA. The first barrier sublayer51is formed to extend into the one or more trenches T. The first barrier sublayer51, the first dam sublayer31, and the planarization layer60are formed in a same layer in a single patterning process using a same material and a single mask plate. By having the first barrier sublayer51, the first dam sublayer31, and the planarization layer60formed in a single patterning process, the manufacturing process can be significantly simplified.

Referring toFIG. 8D, a second dam sublayer32is formed on a side of the first dam sublayer31distal to the first insulating layer21, a second barrier sublayer52is formed on a side of the first barrier sublayer51distal to the base substrate10, and a pixel definition layer70is formed in the display area DA to define a plurality of subpixel apertures. The second barrier sublayer52, the second dam sublayer32, and the pixel definition layer70are formed in a same layer in a single patterning process using a same material and a single mask plate. By having the second barrier sublayer52, the second dam sublayer32, and the pixel definition layer70formed in a single patterning process, the manufacturing process can be significantly simplified.

Referring toFIG. 8E, a third dam sublayer33is formed on a side of the second dam sublayer32distal to the first dam sublayer31. The third dam sublayer33and a spacer layer may be formed in a same layer in a single patterning process using a same material and a single mask plate. Subsequently, a first inorganic encapsulating sublayer41of an encapsulating layer is formed to extend from the display area DA into the peripheral area PA. The first inorganic encapsulating sublayer41is formed to extend into at least a portion of the groove G1. A second inorganic encapsulating sublayer42is formed on a side of the first inorganic encapsulating sublayer41distal to the base substrate10. The second inorganic encapsulating sublayer42is formed to extend into at least a portion of the groove G1.

In another aspect, the present disclosure provides a display panel including a display substrate described herein and a counter substrate facing the display substrate. In some embodiments, the plurality of light emitting elements are a plurality of organic light emitting diodes, and the display panel is an organic light emitting diode display panel. In some embodiments, the plurality of light emitting elements are a plurality of quantum dots light emitting diodes, and the display panel is a quantum dots light emitting diode display panel. In some embodiments, the plurality of light emitting elements are a plurality of micro light emitting diodes, and the display panel is a micro light emitting diode display panel.

In another aspect, the present disclosure provides a display apparatus including a display panel described herein, and one or more integrated circuits connected to the display substrate.FIG. 9is a schematic diagram illustrating the structure of a display apparatus in some embodiments according to the present disclosure. Referring toFIG. 9, the display apparatus in some embodiments includes a display substrate1and a counter substrate2facing the display substrate1. The display apparatus includes a spacer layer90spacing apart the display substrate1from the counter substrate2. Examples of appropriate display apparatuses include, but are not limited to, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital album, a GPS, etc.