Display device

A display device including a plurality of pixel electrodes arranged in a matrix including rows and columns and a plurality switching elements coupled with the pixel electrodes; a plurality of gate lines coupled with the switching elements and extending in a row direction, at least two gate lines assigned to a row; and a plurality of data lines coupled with the switching elements and extending in a column direction, a data line assigned to at least two columns, wherein each of the pixel electrodes has a first side and a second side that is farther from a data line than the first side, and the switching elements are disposed near the second sides of the pixel electrodes.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to and the benefit of Korean Patent Application No. 10-2004-0072507 filed on Sep. 10, 2004, Korean Patent Application No. 10-2004-0072749 filed on Sep. 10, 2004, and Korean Patent Application No. 10-2004-0072685 filed on Sep. 10, 2004, which are hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display device having an improved structure and driving scheme that simplifies manufacturing processes and reduces cost.

2. Description of Related Art

An active type display device such as an active matrix (AM) liquid crystal display (LCD) and an active matrix organic light emitting display (OLED) includes a plurality of pixels arranged in a matrix and including switching elements and a plurality of signal lines such as gate lines and data lines for transmitting signals to the switching elements. The switching elements of the pixels selectively transmit data signals from the data lines to the pixels in response to gate signals received from the gate lines for displaying images. The pixels of the LCD adjust transmittance of incident light depending on the data signals. The pixels of the OLED adjust luminance of light emission depending on the data signals.

The display device further includes a gate driver for generating and applying the gate signals to the gate lines and a data driver for applying the data signals to the data lines. Each of the gate driver and the data driver generally includes a plurality driving integrated circuit (IC) chips. The number of the IC chips is preferably few to reduce manufacturing cost. In particular, the number of the data driving IC chips is important since the data driving IC chips are much more expensive than the gate driving IC chips.

An LCD includes a pair of panels provided with field generating electrodes and a liquid crystal (LC) layer having dielectric anisotropy, which is disposed between the two panels. The field generating electrodes generally include a plurality of pixel electrodes connected to switching elements such as thin film transistors (TFTs) to be supplied with data voltages and a common electrode covering an entire surface of a panel and supplied with a common voltage. A pair of field generating electrodes that generate the electric field in cooperation with each other and a liquid crystal disposed therebetween form a liquid crystal capacitor.

The LCD applies the voltages to the field generating electrodes to generate an electric field to the liquid crystal layer. The strength of the electric field may be controlled by adjusting the voltage across the liquid crystal capacitor. Since the electric field determines the orientations of liquid crystal molecules and the molecular orientations determine the transmittance of light passing through the liquid crystal layer, the light transmittance is adjusted by controlling the applied voltages, thereby obtaining desired images on the display.

To prevent image deterioration due to long-time application of the unidirectional electric field, etc., polarity of the data voltages with respect to the common voltage is reversed every frame, every row, or every dot.

Among the various inversion types, a dot inversion reversing the data voltage polarity every given number of pixels reduces vertical crosstalk or vertical flickering due to the kickback voltage, thereby improving the image quality. However, the polarity inversion of the data voltages flowing in each data line often requires complicated driving scheme that may cause signal delay. Although the signal delay may be reduced by using a low resistivity metal, it may complicate the manufacturing process and increase the production cost.

On the contrary, a column inversion reverses the voltage polarity every given number of pixel columns. Since the column inversion does not reverse the polarity of the data voltages applied to each data line during one frame, the problems associated with signal delay are remarkably reduced.

However, the column inversion technique is inferior to the dot inversion technique in terms of vertical crosstalk and vertical flickering, etc.

SUMMARY OF THE INVENTION

This invention provides a display device having an arrangement of switching elements of pixels arranged on a substrate thereof that allows for a driving scheme that reduces the number of data driving IC chips while ensuring image quality; thereby simplifying a manufacturing process and reducing cost.

The invention discloses a display device including a plurality of pixels arranged in a matrix, each pixel having a switching element coupled thereto; a plurality of gate lines coupled with the switching elements and extending in a row direction of the matrix, each row including at least two of the gate lines; and a plurality of data lines coupled with the switching elements, each data line extending in a column direction of the matrix, wherein each of the pixel electrodes have a first side and a second side that is farther from a data line than the first side, and the switching elements are arranged near the second sides of the pixel electrodes.

DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The present invention is described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like numerals refer to like elements throughout.

In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numerals refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, the element may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

Liquid crystal displays (LCD) as an example of a display device according to embodiments of the invention are described below with reference to the accompanying drawings.

FIG. 1is a block diagram of an LCD according to an embodiment of the invention.FIG. 2is an equivalent circuit diagram of a pixel of an LCD according to an embodiment of the invention.

Referring toFIG. 1, an LCD includes a LC panel assembly300, a gate driver400and a data driver500that are connected to the panel assembly300, a gray voltage generator800connected to the data driver500, and a signal controller600controlling the above elements.

Referring toFIG. 1, the panel assembly300includes a plurality of display signal lines G1-G2nand D1-Dmand a plurality of pixels PX connected thereto and arranged substantially in a matrix. In a structural view shown inFIG. 2, the panel assembly300includes a lower panel and an upper panel200and a LC layer3arranged therebetween.

The display signal lines G1-G2nand D1-Dmare arranged on the lower panel100and include a plurality of gate lines G1-G2ntransmitting gate signals (also referred to as “scanning signals”), and a plurality of data lines D1-Dmtransmitting data signals. The gate lines G1-G2nextend substantially in a row direction and are substantially parallel to each other, while the data lines D1-Dmextend substantially in a column direction and are substantially parallel to each other.

Referring toFIG. 2, each pixel PX includes a switching element Q connected; e.g., coupled, with a gate line G and a data line D, and a LC capacitor Clc and a storage capacitor Cst that are connected; e.g., coupled, with the switching element Q. The storage capacitor Cst may be omitted as necessary.

The switching element Q including a TFT is provided on the lower panel100and includes three terminals: a control terminal connected; e.g., coupled, with the gate line G; an input terminal connected; e.g., coupled, with the data line D; and an output terminal connected; e.g., coupled, with both the LC capacitor Clc and the storage capacitor Cst.

The LC capacitor Clc includes a pixel electrode190provided on the lower panel100and a common electrode270provided on an upper panel200as two terminals. The LC layer3arranged between the two electrodes190and270operates as dielectric of the LC capacitor Clc. The pixel electrode190is connected; e.g., coupled, with the switching element Q, and the common electrode270is supplied with a common voltage Vcom and covers an entire surface of the upper panel200. It is understood that the common electrode270may be provided on the lower panel100, and at least one of the pixel electrode190and the common electrode270may have a shape of approximately a bar or a stripe.

The storage capacitor Cst is an auxiliary capacitor for the LC capacitor Clc. The storage capacitor Cst includes the pixel electrode190and a separate signal line, which is provided on the lower panel100, overlapping the pixel electrode190via an insulator, and is supplied with a predetermined voltage such as the common voltage Vcom. Alternatively, the storage capacitor Cst includes the pixel electrode190and an adjacent gate line called a previous gate line, which overlaps the pixel electrode190via an insulator.

For a color display, each pixel PX may uniquely represents one of primary colors (i.e., spatial division) or each pixel PX may sequentially represents the primary colors in turn (i.e., temporal division) such that spatial or temporal sum of the primary colors are recognized as a desired color.FIG. 2shows an example of spatial division in that each pixel PX includes a color filter230representing one of the primary colors in an area of the upper panel200facing the pixel electrode190. Alternatively, the color filter230may be provided on or under the pixel electrode190on the lower panel100.

An example of a set of the primary colors includes a red color, a green color, and a blue color. The pixels PX including red, green, and blue color filters are referred to as red, green, and blue pixels, respectively. A representative arrangement of red, green, and blue pixels is a stripe arrangement where each pixel row includes red, green, and blue pixels arranged in turn and each pixel column represents only one color.

One or more polarizers (not shown) are attached to at least one of the panels100and200. In addition, one or more retardation films (not shown) for compensating refractive anisotropy may be arranged between the polarizer(s) and the panel(s).

Referring toFIG. 3, a detailed configuration of an LCD according to an embodiment of the invention is described.

FIG. 3schematically shows a structure of an LCD according to an embodiment of the invention.

Referring toFIG. 3, an LCD includes a panel assembly300, a printed circuit board (PCB)550, and at least one flexible printed circuit (FPC) film510attached to the panel assembly300and the PCB550.

The PCB550is arranged near an upper edge portion of the panel assembly300and mounts or has affixed thereto several circuit elements such as the signal controller600, the gray voltage generator800, etc. The FPC film510mounts a data driving IC540and includes a plurality of output lead lines521connected; e.g., coupled, with output terminals of the data driving IC540and a plurality of input lead lines (not shown) connected; e.g., coupled, with input terminals of the data driving IC540.

The panel assembly300further includes a left dummy line L1and a right dummy line L2extending substantially parallel to the data lines (D1, D2, . . . ) and disposed left to the leftmost data line D1and right to the rightmost data line Dm, respectively. The PCB550further includes bypass lines551aand551band the FPC film510further includes connection lines522a,522b,523aand523b, e.g., two pairs of connection lines.

The right dummy line L2is electrically connected; e.g., coupled, with a lead line521, which is connected; e.g., coupled, with the leftmost data line D1, through the connection line523a, the bypass line551a, and the connection line522a. Similarly, the left dummy line L1is electrically connected; e.g., coupled, with another lead line521, which is connected; e.g., coupled, with the rightmost data line Dm, through the connection line522b, the bypass line551b, and the connection line523b. The connection lines522band523bare connected; e.g., coupled, with the dummy lines L1and L2at contact points C1and the connection lines522aand523aare connected to the lead lines521at contact points C2. The connection lines522a,522b,523aand523bare connected; e.g., coupled, with the bypass lines551aand551bat contact points C3.

Each pair of gate lines G2i−1and G2i(i=1, 2, . . . ) is arranged at the upper and lower sides of a row of pixel electrodes190. Each data line Dj(j=1, 2, 3, . . . ) is arranged between two adjacent columns of the pixel electrodes190. In other words, each data line Dj(j=1, 2, 3, . . . ) is arranged between adjacent pairs of pixel electrodes190. The left dummy line L1is arranged left of the leftmost pixel column and the right dummy line L2is arranged right of the rightmost pixel column.

The pixel electrodes190are connected; e.g., coupled, with the gate lines (G1, G2, . . . ) and the data lines (D1, D2, . . . ) or the dummy lines L1and L2via the switching elements Q that are arranged near the corners of the pixel electrodes190. For example, the connection between the pixel electrodes190and the dummy lines L1and L2may be omitted because the dummy lines L1and L2may be considered as the data lines (D1, D2, . . . ) in relation to the connection relation.

The corner positions of the pixel electrodes190, which are assigned to the respective switching elements Q coupled thereto, vary in rows and columns depending on the connection between the pixel electrode190and the gate lines (G1, G2, . . . ) and the data lines (D1, D2, . . . ). For example, a switching element Q for a pixel electrode190to be connected; e.g., coupled, with an upper gate line G2i−1and a left data line (D1, D2, . . . ) is arranged near the upper left corner of the pixel electrode190, which is the nearest corner from the upper gate line G2i−1and the left data line (D1, D2, . . . ).

A row of pixel electrodes190are alternately connected; e.g., coupled, with a pair of gate lines G2i−1and G2iadjacent thereto and alternately connected; e.g., coupled, with the nearest data line and the next nearest data line. A column of pixel electrodes190are alternately connected; e.g., coupled, with upper gate lines G2i−1and lower gate lines G2iadjacent thereto and alternately connected; e.g., coupled, with the nearest data line and the next nearest data line.

Accordingly, a pair of pixel electrodes190arranged between two adjacent data lines and a pair of gate lines are connected; e.g., coupled, with the same data line but to different gate lines.

The following is a discussion of an arrangement of the switching elements in the pixel matrix and their connection to the respective gate lines and data lines. The pixels in each pixel row have switching element positioned alternately near an upper corner and a lower corner. The pixels in each pixel column have switching elements positioned alternately near an upper corner and a lower corner and also positioned alternately at a left side corner and a right side corner. A pair of gate lines is arranged at the upper and lower sides of each pixel row where the switching elements of the pixels in each pixel row are connected; e.g., coupled, with the gate line positioned nearest the respective switching element. Each data line is arranged between adjacent pairs of pixel columns and connected; e.g., coupled, with switching elements associated with the pairs of pixels. In one embodiment, each pair of pixels having switching elements connected; e.g., coupled, with the same data line is disposed in the same pixel row. In another embodiment, two pixels in each pixel row disposed between two adjacent data lines have switching elements connected; e.g., coupled, with the same data line. Finally, in yet another embodiment, two adjacent pixels in each pixel column have switching elements connected; e.g., coupled, with different data lines.

The above described arrangement reduces the number of the data lines D1, D2, D3, . . . into half of the pixel columns. The arrangement and the connections of the pixel electrodes190with the gate lines and the data lines shown inFIG. 3may also be varied.

An LC panel assembly according to an embodiment of the invention is described below with reference toFIGS. 4,5,6and7.

FIG. 4is a layout view of a lower panel (TFT array panel) according to an embodiment of the invention.FIGS. 5,6and7are sectional views of an LC panel assembly including the lower panel shown inFIG. 4taken along lines V-V′, VI-VI′, and VII-VII′, respectively.

Referring toFIGS. 4,5,6, and7, an LC panel assembly includes a TFT array panel100, a common electrode panel200facing the TFT array panel100, and a liquid crystal layer3interposed between the panels100and200.

Regarding the TFT array panel100, a plurality of pairs of gate lines121aand121band a plurality of storage electrode lines131are formed on an insulating substrate110, such as transparent glass or plastic.

The gate lines121aand121btransmit gate signals and extend substantially in a transverse direction. The pair of gate lines121aand121bare separated from each other and include a plurality of gate electrodes124aand124bextending toward each other, e.g., upward and downward. Each of the gate lines121aand121bfurther includes an end portion129having a sufficiently large area for contact with another layer or an external driving circuit.

A gate driving circuit (not shown) for generating the gate signals may be mounted on a flexible printed circuit (FPC) film (not shown), which may be attached with the substrate110, directly mounted on the substrate110, or integrated onto the substrate110. The gate lines121aand121bmay extend to be connected; e.g., coupled, with a driving circuit that may be integrated with the substrate110.

The storage electrode lines131are supplied with a predetermined voltage, and each of the storage electrode lines131is arranged between two adjacent gate lines121. Each of the storage electrode lines131includes a plurality of sets of storage electrodes133a1,133a2,133b1,133b2,133c1,133c2and133dand a plurality of pairs of storage connections135aand135bconnecting adjacent sets of storage electrodes133a1-133d.

Each set of the storage electrodes133a1-133dsubstantially form a pair of rectangular shapes, each rectangular shape includes a first storage electrode133a1or133a2extending in the transverse direction, a second storage electrode133b1or133b2extending in the transverse direction and arranged opposite the first storage electrode133a1or133a2, a third storage electrode133c1or133c2extending in a longitudinal direction and connecting one ends of the first and the second storage electrodes133a1and133b1or133a2and133b2, and a fourth storage electrode133dextending in the longitudinal direction and connecting the other ends of the first and the second storage electrodes133a1and133b1or133a2and133b2. The pair of rectangular shapes commonly share the fourth storage electrode133dand have substantially a 180-degree rotational symmetry with respect to a center of the fourth storage electrode133d. The first storage electrodes133a1and133a2are curved near where the gate electrodes124aand124bare positioned. However, the storage electrode lines131may have various shapes and arrangements.

The gate lines121aand121band the storage electrode lines131may be made of a metal containing Al or Al alloy, a metal containing Ag or Ag alloy, a metal containing Cu or Cu alloy, a metal containing metal Mo or Mo alloy, Cr, Ta, or Ti. However, the gate lines121aand121bmay have a multi-layered structure that include two conductive films (not shown) having different physical properties. One of the films may be made of a low resistivity metal containing Al, a metal containing Ag, and a metal containing Cu for reducing signal delay or voltage drop.

The other film may be made of material such as a metal containing Cr, Ta, or Ti, which has good physical, chemical, and electrical contact characteristics with other materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the combination of the two films may include a lower Cr film and an upper Al (alloy) film and a lower Al (alloy) film and an upper Mo (alloy) film. However, it is understood that the gate lines121aand121band the storage electrode lines131may be made of various metals or conductors.

The lateral sides of the gate lines121aand121band the storage electrode lines131are inclined relative to a surface of the substrate, and the inclination angle thereof ranges about 30 degrees to about 80 degrees.

A gate insulating layer140, which may be made of silicon nitride (SiNx) or silicon oxide (SiOx), is formed on the gate lines121aand121band the storage electrode lines131.

A plurality of pairs of semiconductor islands154aand154band a plurality of semiconductor islands152are formed on the gate insulating layer140. Each of the semiconductor islands154aand154bis arranged on a gate electrode124aor124band includes extensions covering edges of the gate line121aand121band a storage connection135a. The semiconductor islands152are arranged on the storage connections135band cover edges of the storage connections135b. The semiconductor islands152and154may be made of hydrogenated amorphous silicon (abbreviated to “a-Si”) or polysilicon.

A plurality of pairs of ohmic contact islands163aand165aare formed on the semiconductor islands154a, and a plurality of ohmic contact islands162are formed on the semiconductor islands152. In addition, a plurality of pairs of ohmic contact islands (not shown) are formed on the semiconductor islands154b. The ohmic contacts162,163aand165amay be made of n+ hydrogenated a-Si heavily doped with n type impurity such as phosphorous or they may be made of silicide.

The lateral sides of the islands152,154aand154band the ohmic contacts162,163aand165aare inclined relative to the surface of the substrate110, and the inclination angles thereof are preferably in a range of about 30 degrees to about 80 degrees.

A plurality of data lines171and a plurality of drain electrodes175aand175bare formed on the ohmic contacts162,163aand165aand the gate insulating layer140.

The data lines171transmit data signals and extend substantially in the longitudinal direction to intersect the gate lines121aand121band the storage connections135aand135b. Each data line171includes a plurality of source electrodes173aand173bextending toward the gate electrodes124aand124band curved like a character J. Each of the source electrodes173aextends in an area between adjacent two gate lines121aand121b.

Each of the data lines171further includes an end portion179having a sufficiently large area for contact with another layer or an external driving circuit. A data driving circuit (not shown) for generating the data signals may be mounted on a FPC film (not shown), which may be attached with the substrate110, directly mounted on the substrate110, or integrated with the substrate110. The data lines171may be connected with a driving circuit that may be integrated with the substrate110.

The drain electrodes175aand175bare separated from the data lines171and arranged opposite to the source electrodes173aand173bwith respect to the gate electrodes124aand124b. Each of the drain electrodes175aand175bincludes a relatively wide end portion and a relatively narrow end portion. The wide end portion overlaps a storage electrode133aand the narrow end portion is partly enclosed by a source electrode173aor173b.

A gate electrode124a/124b, a source electrode173a/173b, a drain electrode175a/175b, and a semiconductor island154a/154btogether form a TFT having a channel formed in the semiconductor island154a/154blocated between the source electrode173a/173band the drain electrode175a/175b.

The data lines171and the drain electrodes175aand175bmay be made of a refractory metal such as Cr, Mo, Ta, Ti, or an alloy thereof. However, the data lines171and the drain electrodes175aand175bmay be a multilayered structure that includes a refractory metal film (not shown) and a low resistivity film (not shown). For example, the multi-layered structure may include a double-layered structure that may include a lower Cr/Mo (alloy) film and an upper Al (alloy) film, and a triple-layered structure that may include a lower Mo (alloy) film, an intermediate Al (alloy) film, and an upper Mo (alloy) film. However, the data lines171and the drain electrodes175aand175bmay be made of various metals or conductors.

The data lines171and the drain electrodes175aand175bhave inclined edge profiles relative to the surface of the substrate, and the inclination angles thereof range about 30 degrees to about 80 degrees.

The ohmic contacts162,163aand165aonly arranged between the underlying semiconductor islands152,154aand154band the overlying conductors171,175aand175bthereon and they reduce the contact resistance therebetween. The semiconductor islands152and the extensions of the semiconductor islands154bdisposed on the gate lines121aand121band the storage connections135aand135bare arranged such as to smoother or level the profile of the surface, thereby preventing the disconnection of the data lines171. The semiconductor islands152,154aand154binclude some exposed portions, which are not covered with the data lines171and the drain electrodes175aand175b, such as, for example, portions located between the source electrodes173aand173band the drain electrodes175aand175b.

A passivation layer180may be formed on the data lines171, the drain electrodes175aand175b, and the exposed portions of the semiconductor islands152,154aand154b. The passivation layer180may be made of an inorganic insulator material or an organic insulator material and the passivation layer180may have a substantially level top surface. The inorganic insulator material may include silicon nitride and silicon oxide. The organic insulator material may have a photosensitivity and dielectric constant of less than about 4.0. The passivation layer180may include a lower film containing an inorganic insulator and an upper film containing an organic insulator such that it has the insulating characteristics of the organic insulator while the organic insulator material prevents damage to the exposed portions of the semiconductor islands152,154aand154b.

The passivation layer180has a plurality of contact holes182and185exposing the end portions179of the data lines171and the drain electrodes175aand175b, respectively. The passivation layer180and the gate insulating layer140have a plurality of contact holes181exposing the end portions129of the gate lines121aand121b.

A plurality of pixel electrodes191and a plurality of contact assistants81and82are arranged on the passivation layer180, and may be made of a transparent conductor material such as ITO or IZO or a reflective conductor material such as Ag, Al, Cr, or an alloy thereof.

The pixel electrodes191are physically and electrically connected; e.g., coupled, with the drain electrodes175aand175bvia the contact holes185so that the pixel electrodes191receive data voltages from the drain electrodes175aand175b. The pixel electrodes191that are supplied with the data voltages generate electric fields in cooperation with a common electrode270of the common electrode panel that is supplied with a common voltage, which determine the orientations of liquid crystal molecules (not shown) of the liquid crystal layer3. A pixel electrode191and the common electrode270form a LC capacitor Clc, which stores applied voltages after the TFT is turned off.

A pixel electrode191overlaps the storage electrodes133a1-133d. The pixel electrode191and a drain electrode175aand175bconnected with the pixel electrode191, and the storage electrode line131form a storage capacitor Cst, which increases the voltage storing capacity of the LC capacitor Clc.

The pixel electrodes190cover the wide end portions of the drain electrodes175aand175band have longitudinal edges arranged on the storage electrodes133c1,133c2and133dso that the storage electrodes133c1,133c2and133dblock the interference between the pixel electrodes191and the data lines171and the interference between the pixel electrodes191.

The contact assistants81and82are connected; e.g., coupled, with the end portions129of the gate lines121aand121band the end portions179of the data lines171through the contact holes181and182, respectively. The contact assistants81and82protect the end portions129and179and improve the adhesion between the end portions129and179and external devices.

Below is a description of the common electrode panel200according to an embodiment of the invention.

A light blocking member220, referred to as a black matrix, for preventing or significantly reducing light leakage is arranged on an insulating substrate210. The light blocking member220may include a plurality of openings facing the pixel electrodes191and it may have substantially the same planar like shape as the pixel electrodes191. Alternatively, the light blocking member220may include a plurality of substantially rectilinear portions facing the data lines171and a plurality of widened portions facing the TFTs on the TFT array panel100.

A plurality of color filters230are formed on the substrate210and they are arranged substantially in the areas enclosed or defined by the light blocking member220. The color filters230may extend substantially in the longitudinal direction along the pixel electrodes191. The color filters230may represent one of the primary colors such as red, green and blue colors.

An overcoat250may be formed on the color filters230and the light blocking member220. The overcoat250is preferably made of (organic) insulator and it prevents or substantially prevents the color filters230from being exposed to contaminants and also provides a substantially level surface. The overcoat250may be omitted.

A common electrode270may be formed on the overcoat250. The common electrode270is preferably made of a transparent conductive material such as ITO and IZO.

Alignment layers (not shown) that may be homogeneous may be arranged on inner surfaces of the panels100and200.

Referring again toFIG. 1, the gray voltage generator800generates two sets of a plurality of gray voltages related to the transmittance of the pixels. The gray voltages in one set have a positive polarity with respect to the common voltage Vcom, while the grey voltages in the other set have a negative polarity with respect to the common voltage Vcom.

The gate driver400is connected; e.g., coupled, with the gate lines G1-G2nof the panel assembly300and synthesizes the gate-on voltage Von and the gate-off voltage Voff from an external device to generate gate signals for application to the gate lines G1-G2n.

The data driver500is connected; e.g., coupled, with the data lines D1-Dmof the panel assembly300and transmits data voltages, which are selected from the gray voltages supplied from the gray voltage generator800, to the data lines D1-Dm.

The gate driver400and the data driver500may each include at least one integrated circuit (IC) chip mounted on the panel assembly300or on a flexible printed circuit (FPC) film in a tape carrier package (TCP) type, which are attached to the LC panel assembly300. Alternately, the drivers400and500may be integrated with the panel assembly300along with the display signal lines G1-G2nand D1-Dmand the TFT switching elements Q.

The signal controller600controls the operation of the gate driver400and the gate driver500.

The operation of at least the above-described LCD is described below.

The signal controller600is supplied with input image signals R, G and B and input control signals controlling the display thereof such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, and a data enable signal DE, from a graphics controller (not shown), e.g., externally provided. After generating gate control signals CONT1and data control signals CONT2and processing the image signals R, G and B suitable for the operation of the panel assembly300according to the input control signals and the input image signals R, G and B, the signal controller600transmits the gate control signals CONT1to the gate driver400, and transmits the processed image signals DAT and the data control signals CONT2to the data driver500. The processing of the image signals R, G and B includes the rearrangement of the image data R, G and B according to the pixel arrangement of the panel assembly300.

The gate control signals CONT1include a scanning start signal STV for instructing to start scanning and a clock signal for controlling the output time of the gate-on voltage Von. The gate control signals CONT1may further include an output enable signal OE for defining the duration of the gate-on voltage Von.

The data control signals CONT2include a horizontal synchronization start signal STH for informing the start of data transmission for a group of pixels, a load signal LOAD for instructing to apply the data voltages to the data lines D1-Dm, and a data clock signal HCLK. The data control signal CONT2may further include an inversion signal RVS for reversing the polarity of the data voltages with respect to the common voltage Vcom.

Responding to the data control signals CONT2from the signal controller600, the data driver500receives a packet of the image data DAT for half of a row of pixels from the signal controller600, converts the image data DAT into analog data voltages selected from the gray voltages supplied from the gray voltage generator800, and applies the data voltages to the data lines D1-Dm. It is understood that the packet may contain various amounts of image data DAT.

The gate driver400applies the gate-on voltage Von to the gate line G1-G2nin response to the gate control signals CONT1received from the signal controller600, thereby turning on the switching elements Q connected thereto. The data voltages applied to the data lines D1-Dmare supplied to the pixels through the activated switching elements Q.

The difference between the data voltage and the common voltage Vcom is represented as a voltage across the LC capacitor Clc, which is referred to as a pixel voltage. The LC molecules in the LC capacitor Clc have orientations depending on the magnitude of the pixel voltage, and the molecular orientations determine the polarization of light passing through the LC layer3. The polarizer(s) converts the light polarization into the light transmittance.

By repeating this procedure by a unit of half of a horizontal period, which is denoted by “½H” and is equal to half period of the horizontal synchronization signal Hsync or the data enable signal DE, all gate lines G1-G2nare sequentially supplied with the gate-on voltage Von during a frame, thereby applying the data voltages to all pixels. When the next frame starts after one frame finishes, the inversion control signal RVS applied to the data driver500is controlled such that the polarity of the data voltages is reversed, which is referred to as “frame inversion”.

Other than the frame inversion, the data driver500varies the polarity of the data voltages flowing in each data line during one frame, thereby changing the polarity of the pixel voltages. Since the connections between the pixels and the data lines D1-Dmare complex, as shown inFIG. 3, the polarity inversion pattern generated by the data driver500is different from the polarity inversion of the pixel voltages appearing on the panel assembly300. Hereinafter, the polarity inversion of the data driver500is referred to as “driver inversion” and the polarity inversion of the pixel voltages appearing on the panel assembly300is referred to as “apparent inversion.”

The polarity inversion pattern shown inFIG. 3is a driver inversion of a column inversion and an apparent inversion of 1×2 dot inversion. The driver column inversion indicates that the polarity of the data voltages in each data line is fixed or constant and the polarity of the data voltages in adjacent data lines is opposite. The apparent 1×2 dot inversion indicates that the polarity is inverted every row and every two columns.

The above-described arrangements of the switching elements of the pixels realize a 1×2 dot-type apparent inversion for a given column-type driver inversion. The column-type driver inversion diversifies materials available for the data lines and thus it is easy to find a material that is suitable for simplifying the manufacturing process. In addition, the dot-type apparent inversion disperses the difference in the luminance due to the kickback voltages between the positive-polarity pixel voltages and the negative-polarity pixel voltages to thereby reduce vertical line defect.

Now, an arrangement of pixels in an LCD according to another embodiment of the present invention is described with reference toFIG. 8.

FIG. 8schematically shows an arrangement of pixels in an LCD according to another embodiment of the invention.

Referring toFIG. 8, the arrangement of pixels according to this embodiment is similar to the arrangement of pixels shown inFIG. 3.

In detail, each pair of gate lines G2i−1and G2i(i=1, 2, . . . ) are disposed at the upper side and the lower side of a row of pixel electrodes190. Each data line Dj(j=1, 2, 3, . . . ) is arranged between two adjacent columns of the pixel electrodes190.

In addition, two switching elements Q connected; e.g., coupled, with a pair of pixel electrodes190in a pixel row are arranged between two adjacent data lines Djand Dj+1and are connected to different gate lines G2i−1and G2i. For example, as shown inFIG. 8, a switching element Q arranged near an upper corner of a pixel electrode190is connected; e.g., coupled, with an upper gate line G2i−1, and a switching element Q arranged near a lower corner of a pixel electrode190is connected; e.g., coupled, with the lower gate line G2i.

Each connection connecting the switching elements Q and the data lines is arranged between two adjacent gate lines.

The switching elements Q are arranged further from the data lines in the embodiment shown inFIG. 8than in the embodiment shown inFIG. 3. In detail, each of the switching elements Q is arranged near a longitudinal edge of a pixel electrode190, which is farther one of two longitudinal edges of the pixel electrode190from the data lines.

In summary, the pixels and the switching elements Q are arranged such that the switching elements Q of a pair of adjacent pixels in a row, which are arranged between two adjacent data lines, are connected; e.g., coupled, with a single data line. Further, a pair of adjacent pixels in a column are connected; e.g., coupled, with different data lines, and the switching elements of the pair of adjacent pixels are arranged at opposite sides of the pixel electrodes190in the column direction. In a pixel row, pairs of pixels having the same configuration are repeatedly arranged.

A TFT array panel including the pixel arrangement shown inFIG. 8is described in detail with reference toFIG. 9andFIG. 10.

FIGS. 9 and 10are layout views of TFT array panels according to embodiments of the invention.

Layered structures of the TFT array panels according to the embodiments shown inFIG. 9andFIG. 10are substantially the same as the layered structures shown inFIGS. 5,6, and7, and thus the cross sections of the TFT array panels are omitted for purposes of convenience.

A plurality of gate lines121aand121bincluding gate electrodes124aand124band end portions129, and a plurality of storage electrode lines131including storage electrodes133a1-133dand storage connections135aand135bare arranged on a substrate110, and a gate insulating layer140. A plurality of semiconductor islands152,154aand154b, and a plurality of ohmic contacts162,163a,163b,165aand165bare sequentially arranged thereon. A plurality of data lines171including source electrodes173aand173band end portions179and a plurality of drain electrodes175aand175bare formed on the ohmic contacts162,163a,163b,165aand165band the gate insulating layer140. A passivation layer180is formed thereon. A plurality of contact holes181,182and185are provided at the passivation layer180and the gate insulating layer140. A plurality of pixel electrodes190and a plurality of contact assistants81and82are formed on the passivation layer180.

Each of the TFT array panels shown inFIG. 9andFIG. 10further includes a plurality of semiconductor islands153arranged at intersections of the gate lines121aand121band the data lines171and a plurality of ohmic contacts (not shown) arranged between the semiconductor islands153and the data lines171. The semiconductor islands153smooth or substantially level the profile of the surface, thereby preventing the disconnection of the data lines171.

In addition, each of the source electrodes173aand173bshown inFIG. 10has a shape of a substantially U-like or curved character. The drain electrodes175aand175bextend in a longitudinal direction to intersect upper edges of the gate electrodes124aand124b. Since the upper edges of the gate electrodes124aand124bare substantially parallel to an extension direction of the gate lines121aand121b, the overlapping areas of the drain electrodes175aand175band the gate electrodes124aand124bare substantially uniform when the drain electrodes175aand175bmove in the extension direction of the gate lines121aand121b.

The embodiments shown inFIGS. 8,9, and10have reduced vertical stripes as compared with the embodiment shown inFIGS. 4,5,6, and7, which are described below with reference toFIG. 11andFIG. 12.

FIG. 11is a schematic layout view of the LCD shown inFIGS. 4,5,6, and7, andFIG. 12is a schematic layout view of the LCD shown inFIGS. 8,9, and10. The hatched areas inFIG. 11andFIG. 12are those areas covered by light blocking members.

The distance between two adjacent pixel electrodes190is different between when there is a data line171arranged between the pixel electrodes190and when there is no data line arranged between the pixel electrodes190. An area having a larger width than a width of the data line171is required so that the data line may be arranged between the pixel electrodes190.

Due to the difference in the distance between the pixel electrodes190, the width of the light blocking member depends on whether the data line171is so arranged. For example, for a 15-inch WXGA LCD, the width of a portion of the light blocking member disposed on a data line171may be about 29 microns, while the width of a portion of the light blocking member disposed between the pixel electrodes190without a data line may be about 18 microns.

Referring toFIG. 11, the area of a portion A of the light blocking member covering a data line171is larger than the area of a portion B of the light blocking member without a data line. Accordingly, a pair of pixels arranged between the data line171have an effective display area that is smaller than an effective display area of a pair of pixels that do not have a data line arranged therebetween, thereby causing a longitudinal stripe defect.

However, the LCD shown inFIGS. 8,9, and10arranges the switching elements Q at portions located between the pixel electrodes190that do not include a data line. Therefore, the area of a portion D of the light blocking member includes an area occupied by the switching elements Q as well as an area of a gap between the pixel electrodes190, while the area of a portion C which includes a the data line171does not include an area that is occupied by the switching elements Q. The area occupied by the switching elements Q may compensate for the area increased by interposing the data line171, thereby reducing the difference in the areas between the portions C and D, which decreases the longitudinal stripe defect.

Pixel arrangements according to other embodiments of the invention are described below with reference toFIGS. 13,14and15.

FIGS. 13,14and15schematically show arrangements of pixels in an LCD according to other embodiments of the invention, wherein the arrangement of pixels is similar to the arrangement of pixels shown inFIG. 8.

Each pair of gate lines G2i−1and G2iare arranged at the upper and lower sides of a row of pixel electrodes190. Each data line Djis arranged between two adjacent columns of the pixel electrodes190.

Two switching elements Q connected; e.g., coupled, with a pair of pixel electrodes190in a pixel row and arranged between two adjacent data lines, are connected; e.g., coupled, with different gate lines G2i−1and G2i. For example, as shown inFIG. 13, a switching element Q arranged near an upper corner of a pixel electrode190is connected; e.g., coupled, with an upper gate line G2i−1, and a switching element Q arranged near a lower corner of a pixel electrode190is connected; e.g., coupled, with the lower gate line G2i.

Further, the switching elements Q are arranged near a longitudinal edge of the pixel electrodes190, which is relatively distant from the data lines, and each interconnection connecting the switching elements Q with the data lines is arranged between two adjacent gate lines.

However, the connections between the switching elements Q and the data lines shown inFIGS. 13,14and15are different from the connections shown inFIG. 8, and such configuration is described below.

According to the arrangement shown inFIG. 13, the switching elements Q in each pair of pixels adjacent in the row direction (referred to as “pixel pair” hereinafter) are connected; e.g., coupled, with different data lines. Two adjacent pixels in the column direction are connected; e.g., coupled, with different data lines and have switching elements Q arranged at the opposite positions in the column direction. The switching elements Q of corresponding pixels in two pixel pairs adjacent in the row direction are connected; e.g., coupled, with different sided data lines and are arranged at opposite positions in the column direction. As a result, the pixel arrangement shown inFIG. 13is obtained by repeatedly arranging a 2×4 pixel matrix in the row direction and the column direction.

In the arrangement shown inFIG. 14, the switching elements Q in each pixel pair are connected; e.g., coupled, with a single data line. Two pixels adjacent in the column direction are connected to different data lines and have switching elements Q arranged at the same position. Two pixel pairs adjacent in the row direction have the same configuration. As a result, the pixel arrangement shown inFIG. 14is obtained by repeatedly arranging a 2×2 pixel matrix in the row direction and the column direction.

In the arrangement shown inFIG. 15, the switching elements Q in each pixel pair are connected; e.g., coupled, with a single data line. Two pixels adjacent in the column direction are connected; e.g., coupled, with different data lines and have switching elements Q arranged at the same position. The switching elements Q of corresponding pixels in two pixel pairs adjacent in the row direction are connected; e.g., coupled, with the same sided data lines and arranged at opposite positions in the column direction. As a result, the pixel arrangement shown inFIG. 15is obtained by repeatedly arranging a 2×4 pixel matrix in the row direction and the column direction.

Pixel arrangements according to other embodiments of the invention are described below with reference toFIGS. 16,17and18.

FIGS. 16,17and18schematically show arrangements of pixels in an LCD according to other embodiments of the invention, wherein the arrangement of pixels are similar to the arrangement shown inFIG. 8.

Each pair of gate lines G2i−1and G2iare arranged at the upper side and the lower side of a row of pixel electrodes190. Each data line Djis arranged between two adjacent columns of the pixel electrodes190.

Two switching elements Q in a pixel pair are connected; e.g., coupled, with different gate lines G2i−1and G2i. For example, a switching element Q disposed near an upper corner of a pixel electrode190is connected; e.g., coupled, with an upper gate line G2i−1, and a switching element Q disposed near a lower corner of a pixel electrode190is connected; e.g., coupled, with the lower gate line G2i.

The switching elements Q are arranged near a longitudinal edge of the pixel electrodes190, which is furthest from the data lines, and each interconnection174connecting the switching elements Q and the data lines is arranged between two adjacent gate lines.

The connections between the switching elements Q and the data lines shown inFIGS. 16-18are different from those shown inFIG. 8. Two switching elements Q are connected to a single interconnection174. For example, as shown inFIG. 16, in upper and lower pixel pairs adjacent in the column direction, a lower switching element Q of the upper pixel pair and an upper switching elements Q of the lower pixel pair are connected; e.g., coupled, with a single data line.

In the arrangement shown inFIG. 16, the switching elements Q in each pixel pair are connected; e.g., coupled, with different data lines. Two pixels adjacent in the column direction are connected; e.g., coupled, with different data lines and have switching elements Q arranged at the same position. Two pixel pairs adjacent in the row direction have the same configuration. As a result, the pixel arrangement shown inFIG. 16is obtained by repeatedly arranging a 2×2 pixel matrix in the row direction and the column direction.

In the arrangement shown inFIG. 17, the switching elements Q in each pixel pair are connected; e.g., coupled, with different data lines. Two pixels adjacent in the column direction are connected; e.g., coupled, with different data lines and have switching elements Q arranged at the same position. The switching elements Q of corresponding pixels in two pixel pairs adjacent in the row direction are connected arranged different sided data lines and disposed at opposite positions in the column direction. As a result, the pixel arrangement shown inFIG. 17is obtained by repeatedly arranging a 2×4 pixel matrix in the row direction and the column direction.

In the arrangement shown inFIG. 18, the switching elements Q in each pixel pair are connected; e.g., coupled, with different data lines. Two pixels adjacent in the column direction are connected; e.g., coupled, with a single data line or different data lines and have switching elements Q arranged at the same position or opposite-positions in the column direction. The switching elements Q of corresponding pixels in two pixel pairs adjacent in the row direction are connected; e.g., coupled, with different sided data lines and disposed at opposite positions in the column direction. As a result, the pixel arrangement shown inFIG. 18is obtained by repeatedly arranging a 4×4 pixel matrix in the row direction and the column direction.

The polarity inversion types of data voltages in the LCDs shown inFIGS. 13,14,15,16,17, and18are described below.

The driver inversion in the LCDs shown inFIGS. 13,14,15,16,17, and18is a column inversion.

The above-described arrangements of the switching elements of the pixels realize a 1×2 dot-type apparent inversion for a given column-type driver inversion. The column-type driver inversion enables a variety of materials to be used for the data lines, thereby potentially reducing cost and simplifying the manufacturing process. The dot-type apparent inversion also disperses the difference in the luminance due to the kickback voltages between the positive-polarity pixel voltages and the negative-polarity pixel voltages to reduce vertical line defect.

The above-described structure and driving scheme according to the embodiment of the present invention reduce the number of the data driving IC chips while ensuring image quality.

It is understood that the invention is not limited to the embodiments discussed above and may be employed to other display devices such as OLED device.