Method of selecting operating characteristics of a resistive memory device

In a method of providing an operating characteristic of a resistive memory device, material of an electrode thereof is selected to in turn provide a selected operating characteristic of the device. The material of the electrode may be reacted with material of an insulating layer of the resistive memory device to form a reaction layer, the selected operating characteristic being dependent on the presence of the reaction layer.

BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates generally to memory devices, and more particularly, to selection of operating characteristics of resistive memory devices.

2. Background Art

Recently, resistive memory devices have been developed for use in storage applications in electronic devices. A typical resistive memory device is capable of selectively being placed in a low resistance (“programmed”) state and a high resistance (“erased”) state. The state of the device is read by providing an electrical potential across the device and sensing the level of current through the device. These devices are appropriate for use in a wide variety of electronic devices, such as computers, personal digital assistants, portable media players, digital cameras, cell phones, automobile engine controls and the like. In these various uses, resistive memory devices are subjected to a wide variety of conditions. It would be desirable to tailor operating characteristics of the devices to the particular usage thereof.

Therefore, what is needed is an approach wherein particular operating characteristics of resistive memory devices may be selected.

DISCLOSURE OF THE INVENTION

Broadly stated, a method of providing an operating characteristic of a resistive memory device comprises selecting material of an electrode of the resistive memory device, the selected operating characteristic being dependent on the selected material of the electrode. The material of the electrode may be reacted with material of an insulating layer of the resistive memory device to form a reaction layer, the selected operating characteristic being dependent on the presence of the reaction layer.

The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there are shown and described embodiments of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.

BEST MODE(S) FOR CARRYING OUT THE INVENTION

Reference is now made in detail to specific embodiments of the present invention which illustrate the best mode presently contemplated by the inventors for practicing the invention.

FIG. 1-3illustrate the fabrication of a first embodiment of resistive memory device. Initially, a copper electrode32is provided (FIG. 1). A Cu2O layer34is thermally grown by oxidizing copper of the electrode32, providing a Cu2O insulating layer34on and in contact with the electrode32(FIG. 2). A second electrode36, of Ni or Co, is deposited on and in contact with the insulating layer. The electrode32, insulating layer, and electrode36form a first embodiment of resistive memory device38. The electrode32is connected to the drain of an access MOS transistor40, which has its source connected to ground (shown in schematic form inFIGS. 4-7).

The switching mechanism of the resistive memory device38is explained based on the Space-Charge-Limited-Conduction model. In a solid material with unfilled deep traps, SCLC current is significantly lowered from the trap-free case by a ratio θ, determined by the trap depth (ΔEt) and density (Nt) as θ∝ exp(ΔEt/kT)/Nt. A dramatic resistance reduction occurs when the deep traps are filled at the traps-filled-limit voltage (VTFL) that is determined by the unfilled deep trap density. After that the material is switched from a high-resistance state (“OFF”) into a low-resistance state (“ON”). The ON state retention is determined by the “thermal release time” (detrapping through thermal processes) that is exponentially proportional to ΔEt as τ∝ exp(ΔEt/kT).

FIG. 8is a plot of resistive memory device current vs. electrical potential applied across the memory device38with a Ni electrode36. In order to program the memory device38(FIGS. 4 and 8), an electrical potential is applied across the resistive memory device38from a higher to a lower electrical potential in the direction of from electrode36to electrode32, by applying an electrical potential Vpg1(the “program” electrical potential) to the electrode36. This causes electronic charge carriers in the form of electrons and/or holes to enter the insulating layer34and fill traps in layer34, so that the overall memory device38is switched to a conductive, low-resistance (programmed) state (A). The current through the resistive memory device38is limited to a relatively low level by application of a relatively low voltage Vg1to the gate of the transistor40. Upon removal of such potential the memory device38remains in a conductive or low-resistance state having an on-state resistance indicated at (B), due to the long retention associated with deep trap levels.

In order to erase the resistive memory device38(FIGS. 5 and 8), an electrical potential is applied across the memory device38from a higher to a lower electrical potential in the direction of from electrode36to electrode32, i.e., the same direction as the programming potential, by applying Ver1(the “erase” electrical potential) to the electrode36. The erase potential is substantially lower than the programming potential so as to avoid the possibility of undesirably reprogramming the device38in the erase step. Meanwhile, the voltage Vg2applied to the gate of the transistor40is higher than in the programming step to provide higher current flow though the device38. The high current causes a temperature rise in the device via Joule heating. This causes electronic charge carriers to escape, i.e., leave the traps in the insulating layer34(C), so that the overall memory device38is in a high-resistance (erased) state.

The memory device38may be erased using a second approach (FIGS. 6 and 8). In this approach, the erase electrical potential is applied across the memory device38from higher to lower potential in the direction from the electrode32to the electrode36, i.e., in the direction opposite that as applied in the programming of the device38, by applying Ver1to the electrode32and grounding electrode36. This causes electronic charge carriers to escape the traps in the insulating layer34(D), so that the overall memory device38is in a high-resistance (erased) state.

In the read step of the memory device38in its programmed (low resistance) state or its erased (high resistance) state (FIGS. 7 and 8), an electrical potential Vr(the “read” electrical potential) is applied across the memory device38from a higher to a lower electrical potential in the direction from the electrode36to the electrode32, or vice versa, by applying Vr(the “read” electrical potential) to the electrode36. This electrical potential is less than the electrical potentials applied across the memory device38for programming and erasing. In this situation, with the voltage Vg1applied to the gate of the transistor40as in the programming step, the memory device38will readily conduct current in its programmed state, and will allow only minimal current therethrough in its erased state, indicating the memory device38to be in its programmed state or its erased state.

FIG. 9-12illustrate the fabrication of a second embodiment of resistive memory device. Initially, a copper electrode132is provided (FIG. 9). A Cu2O layer134is thermally grown by oxidizing copper of the electrode132, to provide a Cu2O insulating layer134on and in contact with the electrode132(FIG. 10). A second electrode136, of Ti or Ta, is deposited on and in contact with the insulating layer134. Next, material of the electrode136is reacted with material of the insulating layer134, causing the insulating layer134to be reduced, i.e., to provide oxygen to the formation of a reaction layer137of TiOxor TaOx(as appropriate) between the insulating layer134and the electrode136. This provides the second embodiment of resistive memory device138, with the insulating layer134and reaction layer137between the first and second electrodes132,136.This reaction causes deeper traps to be formed in the overall reaction layer-insulating layer structure than in the previous embodiment (i.e., greater energy is required to remove an electronic charge carrier from a trap in this embodiment than in the previous embodiment). While in the first embodiment minimal reaction may occur between two materials, this would not have a significant effect on the traps of the device. It is to be understood that the present reaction is intended to alter the traps.

FIG. 16is a plot of memory device current vs. electrical potential applied across the resistive memory device138with a Ti electrode136. In order to program the memory device138(FIGS. 13 and 16), an electrical potential is applied across the memory device138from a higher to a lower electrical potential in the direction of from electrode136to electrode132, by applying Vpg2(the “program” electrical potential) to the electrode136. This causes electronic charge carriers in the form of electrons and/or holes to enter the insulating layer134and reaction layer137and fill traps therein, to provide that the overall memory device138is in a conductive, low-resistance (programmed) state (E). The current through the memory device138is limited to a relatively low level by application of a relatively low voltage Vg2to the gate of the transistor140. Upon removal of such potential the memory device138remains in a conductive or low-resistance state having an on-state resistance indicated at (F), due to the long retention associated with deep trap levels.

In order to erase the memory device138(FIGS. 14 and 16), an electrical potential is applied across the memory device138from a higher to a lower electrical potential in the direction of from electrode132to electrode136, i.e., the direction opposite to the direction of the programming potential, by applying Ver2to the electrode132and grounding electrode136. This causes electronic charge carriers to leave the traps in the insulating layer134and in the reaction layer137(G), so that the overall memory device138is in a high-resistance (erased) state.

The read step is similar to that for the first embodiment.

As will be seen, based on the selection of the electrode material, for example Ni vs. Ti, and/or the reaction process, the devices38,138have significantly different operational characteristics. For example, the programming characteristics are different, i.e., programming voltage Vpg1of the first device38is lower than the programming voltage Vpg2of the second device138. Furthermore, the erase characteristics are different, i.e., the erase voltage Ver2of the second device138is lower than the erase voltage Ver1of the first device38. In fact the first device38is substantially symmetrical in behavior and can be erased by applying potential in either direction, while the second device138is substantially non-symmetrical in behavior and can be most effectively erased by applying potential in a direction opposite the programming potential. The on-state resistance curves B, F of the devices38,138are substantially different. And, because of the deep traps in the second embodiment138, (programmed) data retention is improved as compared to the first embodiment38. These different operating characteristics are dependent on selection of material of the electrode (36,136), and/or the reaction of the material of that electrode with the material of the insulating layer134.

Various erase mechanisms of the devices ofFIGS. 3 and 12will now be described.

FIG. 17again illustrates the resistive memory device ofFIG. 3. As described above, with the memory device38in its programmed, low-resistance state, electronic charge carriers are held in traps in the insulating layer34. In order to erase the device38, trapped electronic charge carriers can escape the traps through either a field-assisted process or a thermal de-trapping process, or a combination of these processes. That is, the electronic charge carriers must be taken from trap energy levels to a conduction band/valence band energy level by overcoming trap depth (trap depth=|trap energy level−conduction band/valence band energy level|). At room temperature, without electrical potential applied across the device, the trapped electronic charge carriers are quite stably held by the traps, resulting in the memory device38remaining in its programmed state.

With a sufficient electrical potential applied across the device38in accordance with the above erasing methods, the energy barrier is sufficiently lowered so that the electronic charge carriers are taken from trap energy levels to a Fermi energy level, causing the electronic charge carriers to escape the traps, so that the device38is erased. This mechanism may occur independent of increase in temperature of the device.

In a solid material with unfilled deep-level traps, SCLC current is significantly lowered from the trap-free case by a ratio θ, determined by the trap depth (ΔEt) and density (Nt) as θ∝ exp(ΔEt/kT)/Nt, where k is the Boltzmann constant and T is temperature in K. A dramatic current increase (and resistance reduction) occurs when the deep traps are filled at the traps-filled-limit voltage (VTFL) that is determined by the unfilled deep trap density. After that the material is switched from a high-resistance state (“OFF”) into a low-resistance state (“ON”). Both OFF and ON states are described by SCLC model. Deep traps lower the OFF state current, and the ON state current approaches the trap-free limit conduction as the deep traps get filled. The ON state retention is determined by the “thermal release time” (detrapping through thermal processes) that is exponentially proportional to ΔEt as τ∝ exp(ΔEt/kT). Long retention is expected on materials with the appropriate density of deep level traps.

Thermal de-trapping during the erase operation is achieved by Joule heating caused by the high current through the device38as described above. Thermal de-trapping may also be achieved through increase in ambient temperature, or by a combination of Joule heating and an increase in ambient temperature.

FIG. 18is a graph illustrating resistance of devices vs. temperature for a number of programmed devices38of the type ofFIGS. 3 and 17, with Ni electrode36, illustrating that substantially all of the devices38adopt a high resistance (erased) state at 150° C.

FIG. 19again illustrates the device138ofFIG. 12. As described above, with the memory device138in its programmed, low-resistance state, electronic charge carriers are held in traps in the insulating layer134and reaction layer137. In order to erase the device138, the electronic charge carriers must be taken from trap energy levels to a conduction band/valence band energy level by overcoming trap depth (trap depth=|trap energy level−conduction band/valence band energy level|). The trap depth in this case is greater than in the embodiment ofFIGS. 3 and 17. At room temperature, without electrical potential applied across the device, the trapped electronic charge carriers are quite stably held by the traps, resulting in the memory device138remaining in its programmed state.

With a sufficient electrical potential applied across the device138in accordance with the above erasing methods, the energy barrier is sufficiently lowered so that the electronic charge carriers are taken from trap energy levels to a Fermi energy level, causing the electronic charge carriers to escape the traps, so that the device138is erased. This mechanism may occur independent of increase in temperature of the device.

While again sufficiently high temperature through Joule heating and/or increase in ambient temperature (without electrical potential applied to the device138) will cause the electronic charge carriers to escape the traps, because of the deeper trap energy level, a much higher temperature would be required to erase the programmed device138ofFIGS. 19 and 12. Indeed,FIG. 20illustrate that substantially all of a large number of such devices retain their programmed (low resistance) states even at 250° C. Because of this high thermal stability, the erasing process includes application of electrical potential across the device as described above. This is to be compared to the previous embodiment, wherein erasing can be readily achieved through Joule heating and/or increase in ambient temperature.

Thus, the programming thermal stability of the resistive memory device is dependent on the selection of electrode material (36,136) and/or the reaction of electrode material with material of the insulating layer. As will be seen, the temperature sufficient to erase a programmed resistive memory device is dependent on selection of electrode material and/or the reaction of electrode material with material of the insulating layer.

In each approach, both erase approaches (applied electrical potential and increased temperature) may used at the same time. As will be seen fromFIG. 21(for Ni electrode36), power required to erase programmed devices38decreases with increase in device temperature. Arrows pointing to the right indicate median power, while arrows to the left indicate average power. “0” power indicates devices erased by temperature alone.

FIG. 22illustrates a high density memory device array150which incorporates memory devices38as described above and diodes39. As illustrated inFIG. 22, the memory device array150includes a first plurality152of parallel conductors (bit lines) BL0, BL1, . . . BLn, and a second plurality154of parallel conductors (word lines) WL0, WL1, . . . WLnoverlying and spaced from, orthogonal to, and crossing the first plurality of conductors152. A plurality of memory devices38are included, each in series with a diode39, to form a memory device-diode structure162which connects a bit line with a word line at the intersection thereof, with the diode in a forward direction from the bit line to the word line. Each memory device-diode structure162may be manufactured as a stacked structure, so that efficient manufacturing thereof is achieved.

FIG. 23illustrates a high density memory device array250which incorporates memory devices138and transistors140as described above. As illustrated inFIG. 23, the memory device array250includes a first plurality252of parallel conductors (bit lines) BL0, BL1, . . . BLn, and a second plurality254of parallel conductors (word lines) WL0, WL1, . . . WLnoverlying and spaced from, orthogonal to, and crossing the first plurality of conductors252. A plurality of memory devices138are included, each in series with a transistor140, to form a memory device-transistor structure262which connects a bit line with a word line at the intersection thereof. The transistors140act as select devices for the associated memory devices138. In this embodiment, memory devices38may be used in place of memory devices138.

As will be seen, particular operating characteristics of resistive memory devices may be selected, by selecting electrode material and/or reacting material of an electrode with material of the insulating layer thereof. As examples, the programming, erasing on-state resistance and data retention characteristics can be selected depending on the application.

FIG. 24illustrates a system300utilizing memory devices as described above. As shown therein, the system300includes hand-held devices in the form of cell phones302, which communicate through an intermediate apparatus such as a tower304(shown) and/or a satellite. Signals are provided from one cell phone to the other through the tower304. Such a cell phone302with advantage uses memory devices of the type described above for data storage, for example names, telephone number and other data. One skilled in the art will readily understand the advantage of using such memory devices in other hand-held devices which utilize data storage, such as portable media players, personal digital assistants, digital cameras and the like.

FIG. 25illustrates another system400utilizing memory devices as described above. The system400includes a vehicle402having an engine404controlled by an electronic control unit406. The electronic control unit406with advantage uses memory devices of the type described above for data storage, for example data relating to engine and vehicle operating conditions.

FIG. 26illustrates yet another system500utilizing memory devices as described above. This system500is a computer502which includes an input in the form of a keyboard, and a microprocessor for receiving signals from the keyboard through an interface. The microprocessor also communicates with a CDROM drive, a hard drive, and a floppy drive through interfaces. Output from the microprocessor is provided to a monitor through an interface. Also connected to and communicating with the microprocessor is memory which may take the form of ROM, RAM, flash and/or other forms of memory. The memory with advantage uses memory devices of the type described above for storage of any data which is of use.

The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Other modifications or variations are possible in light of the above teachings.

The embodiments were chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill of the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally and equitably entitled.