Semiconductor storage device with a capacitor using a ferroelectric substance and fabricating method thereof

In a fabricating method of a semiconductor storage device, a ferroelectric film is formed on a lower electrode, and crystallized. Thereafter, a heat treatment is performed in an atmosphere of hydrogen or a mixture of hydrogen and an inert gas to vanish a defect at the interface between the gate insulating film of a MOS transistor and a silicon substrate. Next, an upper electrode is formed on the ferroelectric film.

BACKGROUND OF THE INVENTION
 The present invention relates to a semiconductor storage device and
 fabricating method thereof, and more particularly, to a semiconductor
 storage device and fabricating method thereof provided with a capacitor
 that uses a ferroelectric substance as a dielectric film.
 A prior art non-volatile memory that uses a ferroelectric substance is
 shown in FIG. 3. The prior art ferroelectric memory is constructed of at
 least one switching transistor and at least one ferroelectric capacitor.
 Similar to the CMOS (Complementary Metal Oxide Semiconductor) process of
 the conventional DRAM (Dynamic Random Access Memory), after forming a
 switching transistor in an active region surrounded by an element
 isolation region and forming a lower electrode corresponding to a drive
 line on the element isolation region, a ferroelectric substance is formed.
 The ferroelectric capacitor exhibits a hysteretic behavior of charged
 electrons with respect to an application electric field.
 The ferroelectric film has a spontaneous polarization even though the
 application electric field is removed, and therefore, information (1 or 0)
 is stored depending on the direction of this polarization. Taking
 advantage of this property, a non-volatile memory capable of retaining the
 information when the power supply is turned off can be achieved. For the
 application of the ferroelectric capacitor to a memory, there is
 necessitated about 5 .mu.C/cm.sup.2 charge on the capacitor since positive
 and negative threshold voltages for inverting the polarization are equal
 to each other and a difference between the amount of inverted charges and
 the amount of non-inverted charges is detected by a sensing amplifier of a
 semiconductor memory.
 After forming the ferroelectric capacitor, there are simultaneously
 processed an upper plate electrode, a PZT film and a drive line into
 respective specified shapes. A bit line is electrically connected to one
 source/drain region, while the other source/drain region is electrically
 connected to a plate electrode of the ferroelectric capacitor by way of
 wiring.
 For the ferroelectric substance, there is employed lead zirconate titanate
 (PbZr.sub.x Ti.sub.1-x O.sub.3, referred to as PZT hereinafter), bismuth
 layered compound (SrBi.sub.4 Ti.sub.4 O.sub.15, SrBi.sub.2 Ta.sub.2
 O.sub.9) or the like as a material that satisfies the aforementioned
 characteristics. For the electrode material, there are employed PtRh and
 PtRhO.sub.x that have a good lattice bondability to the PZT film and an
 excellent oxidation resistance or RuO.sub.2, IrO.sub.2 and LaSrCoO that
 are oxides and have the feature of electrical conductivity. After the
 formation of the ferroelectric capacitor, an interlayer insulating film is
 formed and the elements are interconnected by means of metal wiring. For
 the interlayer insulating film, there is employed the raw material of
 silane gas or TEOS (tetraethoxysilane), and a silicon oxide film or a
 silicon nitride film is formed by the CVD (Chemical Vapor Deposition)
 method.
 A memory provided with a transistor as described above is normally
 subjected to a heat treatment within a temperature range of 400 to
 450.degree. C. in an inert gas atmosphere containing hydrogen after the
 completion of the final process of metal wiring or protecting film
 formation. This process is to obtain stable transistor characteristics
 through a reduction in the interface state density of the gate oxide film
 by vanishing a defect at the interface between the gate oxide film of the
 transistor and the substrate with diffused hydrogen.
 A prior art technique as disclosed in the prior art reference of Japanese
 Patent Laid-Open Publication No.
 HEI 7-273297 will be described below with reference to FIG. 3.
 First, an element isolation region 42 is formed on the surface of a
 semiconductor substrate 41, and thereafter, diffusion regions of a source
 43 and a drain 44 and a switching transistor 47 having a gate electrode 46
 to be formed on the substrate 41 via a gate insulating film 45 are formed.
 Next, a BPSG film (Boro-Phospho Silicate Glass film) 48 is formed as an
 interlayer insulating film, and further a titanium adhesion layer 49
 having a film thickness of 20 nm, a Pt lower electrode 51 having a film
 thickness of 200 nm, a ferroelectric film 52 having a film thickness of
 250 nm and a Pt upper electrode 53 having a film thickness of 200 nm are
 successively formed on the BPSG film 48. The lower electrode 51, the
 ferroelectric film 52 and the upper electrode 53 constitute a capacitor
 50.
 Next, a first protecting film 54 made of silicon oxide comprised of SOG
 (spin-on glass) is formed to a film thickness of 200 nm, and a second
 protecting film 55 is formed to a film thickness of 220 nm by application
 heat treatment of a MOD (Metal Organic Decomposition) solution having the
 same composition as that of the material of the ferroelectric thin film 52
 on the first protecting film 54. The second protecting film 55 is baked
 under the same processing conditions as those of the ferroelectric film
 52.
 Further, an interlayer insulating film 56 is formed to a film thickness of
 300 nm on the second protecting film 55 by silane thermal decomposition
 achieved by LPCVD (Low Pressure Chemical Vapor Deposition). Openings 57
 are formed through the first protecting film 54, the second protecting
 film 55, the interlayer insulating film 56 and the BPSG film 48, which are
 corresponding to the source 43 and the drain 44 of the switching
 transistor 47. A source lead wire 58 and a drain lead wire 59 are formed
 through these openings 57. Openings 57, which are corresponding to the
 upper electrode 53 and the lower electrode 51, are also formed through the
 first protecting film 54, the second protecting film 55 and the interlayer
 insulating film 56. The drain lead wire 59 and an upper electrode lead
 wire 60 are electrically connected to each other through these openings
 57.
 After the formation of the capacitor 50, the interlayer insulating film 56
 to be employed between the multilayer wiring lines 60, 59 and 58 made of
 aluminum or the like or the protecting films 54 and 55 to be formed after
 the completion of the wiring lines must be formed at a substrate
 temperature of about 400.degree. C. taking the reaction of the aluminum
 wiring lines 60, 59 and 58 with the silicon substrate 41 and the
 reliability of the aluminum wiring lines 60, 59 and 58 into consideration.
 For this reason, the interlayer insulating film 56 and the protecting
 films 54 and 55 have conventionally been formed of the raw material of
 silane or TEOS (tetraethoxysilane) by the plasma CVD method capable of
 forming the films at low temperature.
 However, the interlayer insulating film 56 formed of silane or TEOS by the
 plasma CVD method contains a large amount of hydrogen. The hydrogen is
 dissociated by heat treatment at a temperature of about 400.degree. C.
 after the formation of the protecting films 54 and 55, diffused into the
 elements and activated by the Pt upper electrode 53 of the ferroelectric
 capacitor 50. When the activated hydrogen reaches an interface of the
 ferroelectric film 52, a reduction effect occurs on the ferroelectric film
 52 side, as a consequence of which oxygen in the film 52 is pulled out to
 destroy the dielectric property. If this phenomenon progresses, then the
 ferroelectric characteristic of the ferroelectric film 52 deteriorates to
 cause an increase in the leak current. Furthermore, the heat treatment is
 performed in an inert gas atmosphere containing hydrogen after the
 formation of the upper electrode 53 in the above prior art, and therefore,
 the deterioration in the ferroelectric characteristic and an increase in
 the leak current occur similarly.
 If a thin film 55 equivalent to the ferroelectric substance in terms of
 composition and crystalline structure is used as a hydrogen interrupting
 protecting film, then the protecting film is hard to be flattened. This
 leads to a problem that a separation from the insulating film on the
 protecting film occurs and a problem that chemical elements constituting
 the protecting film diffuse to exert bad influence on the switching
 transistor or the like.
 SUMMARY OF THE INVENTION
 Accordingly, an object of the present invention is to provide a
 semiconductor storage device and fabricating method thereof capable of
 making compatible stable transistor characteristics with a good capacitor
 ferroelectric characteristic.
 In one aspect of the present invention, a semiconductor storage device
 fabricating method for fabricating a semiconductor storage device provided
 with a capacitor that uses a ferroelectric film as a dielectric film and a
 MOS transistor, comprises the steps of:
 forming the ferroelectric film on a lower electrode of the capacitor;
 performing a first heat treatment in an atmosphere of hydrogen or a mixture
 of hydrogen and an inert gas after crystallizing the ferroelectric film so
 that a defect is vanished at an interface between a gate insulating film
 of the MOS transistor and a semiconductor substrate; and
 forming an upper electrode of the capacitor on the ferroelectric film
 directly or via a contact hole formed through an interlayer insulating
 film after having performed the first heat treatment.
 In another aspect of the present invention, a semiconductor storage device
 has a capacitor, said capacitor comprising:
 a lower electrode;
 a ferroelectric film that is formed on the lower electrode and has an upper
 surface processed by hydrogen; and
 an upper electrode on the ferroelectric film.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
 The present invention will be described in detail below on the basis of the
 embodiments thereof shown in the accompanying drawings.
 FIGS. 1A, 1B, 1C and 1D are process charts for fabricating a semiconductor
 storage device according to an embodiment of the present invention, in
 which are shown a semiconductor substrate 1, a switching transistor 2, an
 element isolation region 3, a first interlayer insulating film 4, a
 polysilicon plug 5, a barrier metal layer 6, a capacitor lower electrode
 7, a ferroelectric film 8, a second interlayer insulating film 9, an upper
 electrode 10, a third interlayer insulating film 11, a metal wiring 12 and
 a surface protecting film 13.
 The process of fabricating a semiconductor storage device according to one
 embodiment of the present invention will be described below.
 First, as shown in FIG. 1A, a MOS transistor that serves as the switching
 transistor 2 and the element isolation region 3 are formed on the silicon
 substrate 1 according to a known transistor fabricating method. An SiOF
 film is formed as the first interlayer insulating film 4 on the silicon
 semiconductor substrate 1, using a BPSG film (Boro-Phospho Silicate Glass
 film) or silicon tetrafluoride (SiF.sub.4) as a raw material.
 Next, as shown in FIG. 1A, a contact hole forming resist pattern (not shown
 in the drawings) is formed through a lithographic process, and thereafter
 a contact hole is opened by the dry etching method. Next, a polysilicon
 film is deposited and doped with phosphorus at a temperature of 800 to
 900.degree. C. Next, the polysilicon film is polished by
 chemico-mechanical polishing, thereby forming the polysilicon plug 5 in
 the contact hole. Next, a Ti film (not shown) is formed to a film
 thickness of 200 .ANG. as an adhesion layer for the lower electrode
 7/barrier metal layer 6.
 Next, as shown in FIG. 1B, a titanium nitride film or a TaSiN film or a
 laminate film of these materials are formed by the sputtering method to a
 thickness of 1000 to 2000 .ANG. as the barrier metal layer 6 between the
 lower electrode 7 and the polysilicon plug 5. A TiN film was used as the
 barrier metal layer 6 in the present embodiment. Next, Pt or a compound
 containing Pt or an oxide electrode of IrO.sub.2, RuO.sub.2, ReO.sub.3 or
 the like or a laminate film of these materials is formed by the sputtering
 method to a film thickness of 500 to 1500 .ANG. as the lower electrode 7.
 A Pt film was used as the lower electrode 7 in the present embodiment.
 Next, as shown in FIG. 1B, a PZT film is formed by the sol-gel method to a
 film thickness of 2000 .ANG. on the lower electrode 7, and the film is
 crystallized into a perovskite structure having a ferroelectric
 characteristic by applying heat by means of a lamp or an electric furnace,
 thereby forming the ferroelectric film 8. The crystallization temperature
 largely varies depending on the ferroelectric material, and a temperature
 of 600 to 700.degree. C. is preferable for the PZT film or PLZT film.
 Next, the ferroelectric film 8, lower electrode 7, barrier metal layer 6,
 and the adhesion layer are patterned. The film 8 is composed of the PZT
 film, lower electrode 7 is composed of Pt, barrier metal layer 6 is
 composed of TiN film, and the adhesion layer is composed of a Ti film.
 Then, the substrate 1 is subjected to a heat treatment within a
 temperature range of 300 to 450.degree. C. in an atmosphere of hydrogen or
 an inert gas containing hydrogen after this patterning. Through these
 processes, a defect at the interface between the Si semiconductor
 substrate 1 and the gate oxide film of the switching transistor 2 is
 vanished by hydrogen.
 By thus performing the heat treatment in the inert gas containing hydrogen
 before forming the upper electrode 10, no deterioration is observed in the
 ferroelectric characteristic as shown in FIG. 2A. If the processing is
 performed in the inert gas containing hydrogen after the formation of the
 upper electrode 10, then the deterioration in the ferroelectric
 characteristic becomes significant as shown in FIG. 2B.
 That is, if the heat treatment is performed in the atmosphere containing
 hydrogen after the formation of the upper electrode 53 as in the prior
 art, then it is presumable that the hydrogen is easily absorbed by the
 upper electrode 53 and reaches the interface of the ferroelectric film 52.
 Then, the upper electrode 53, and in particular, It has a catalytic
 effect, and it is presumable that the hydrogen is activated to cause a
 reducing effect on the ferroelectric film 52 side, consequently pulling
 out oxygen in the ferroelectric film 52. If this phenomenon progresses,
 then the ferroelectric characteristic will deteriorate and a leak current
 will increase. Therefore, in the present embodiment, the heat treatment in
 the hydrogen atmosphere is executed before the formation of the upper
 electrode 10 of the capacitor 18. Therefore, according to this embodiment,
 the defect at the interface between the gate oxide film of the switching
 transistor 2 and the silicon substrate 1 can be vanished by hydrogen
 without deteriorating the ferroelectric characteristic through the heat
 treatment in the gas containing hydrogen. Thereby, the interface state
 density of the gate oxide film can be reduced. Therefore, the excellent
 ferroelectric characteristic of the capacitor 18 can be made compatible
 with the stable characteristics of the transistor 2.
 Next, as shown in FIG. 1C, the second interlayer insulating film 9 is
 formed on the ferroelectric film 8 comprised of a PZT film. This second
 interlayer insulating film 9 is comprised of an SiOF film formed by the
 plasma CVD method within a substrate temperature range of normal
 temperature to 450.degree. C. using SiF.sub.4, O.sub.2 and Ar as raw
 materials. Otherwise, the second interlayer insulating film 9 may be
 comprised of an SiONF film formed within a substrate temperature range of
 normal temperature to 450.degree. C. using SiF.sub.4, N.sub.2, O.sub.2 and
 Ar or N.sub.2 O as raw materials. The insulating film 9 formed by the
 above method uses no hydrogen containing gas as the film forming gas, and
 therefore, no hydrogen (H) exists in the insulating film 9. Therefore, no
 hydrogen dissociation is caused by the heat treatment, consequently
 incurring no deterioration in the ferroelectric characteristic.
 Next, a contact hole for forming the upper electrode 10 is opened. As the
 upper electrode 10, Pt is formed to a thickness of about 1000 .ANG. and
 patterned by a photolithographic process. It is to be noted that the
 material of the upper electrode 10 is not limited to Pt, and it is
 acceptable to employ an oxide conductor used for the lower electrode 7 or
 a laminate electrode of these materials. Also, the upper electrode 10 may
 be been directly formed on the ferroelectric film 8 , not via the contact
 hole formed through the insulating film 9.
 Next, as shown in FIG. 1C, the third interlayer insulating film 11 is
 formed on the upper electrode 10 by a method similar to that of the second
 interlayer insulating film 9. Next, as shown in FIG. 1D, a contact hole is
 opened on a source of the switching transistor 2, and the metal wiring 12
 is formed.
 Then, after the formation of this metal wiring 12, an SiOF film for the
 surface protecting film 13 is formed within a substrate temperature range
 of normal temperature to 450.degree. C., using SiF.sub.4, O.sub.2 and Ar
 as raw materials. Otherwise, an SiNF film for the surface protecting film
 13 is formed within a substrate temperature range of normal temperature to
 450.degree. C., using SiF.sub.4, N.sub.2 and Ar as raw materials.
 Otherwise, an SiONF film for the surface protecting film 13 is formed
 within a substrate temperature range of normal temperature to 450.degree.
 C., using SiF.sub.4, N.sub.2, O.sub.2 and Ar or N.sub.2 O as raw
 materials.
 Furthermore, the surface protecting film 13 may be provided by a silicon
 nitride film formed by the plasma CVD method using SiF.sub.4 and N.sub.2
 as raw materials. For the surface protecting film 13, a nitrided oxidized
 silicon film may be formed using SiF.sub.4 and N.sub.2 O as material
 gases. Furthermore, a laminate film of these films may be used as the
 surface protecting film 13.
 After the formation of the surface protecting film 13, a heat treatment is
 performed within a temperature range of 300 to 450.degree. C. in an
 atmosphere of an inert gas or oxygen or a mixture gas of these gases.
 By this second heat treatment, the damage caused by the plasma introduced
 during the process of opening the contact hole, processing the metal
 wiring and forming the surface protecting film 13 can be recovered. Since
 the heat treatment temperature is set to 300 to 450.degree. C., reaction
 of aluminum with the silicon semiconductor substrate can be suppressed
 when aluminum is used for wiring. Accordingly, reliability of the aluminum
 wiring can be secured. By virtue of the heat treatment performed within
 the temperature range of 300 to 450.degree. C., the hydrogen that has
 vanished the defect at the interface between the gate oxide film of the
 transistor 2 and the substrate 1 is not dissociated. Therefore, the
 characteristics of the transistor can be stabilized.
 Although the PZT film is employed as the ferroelectric film 8 in the
 aforementioned embodiment, the present invention is not limited to this,
 and it is acceptable to employ a bismuth layered compound (SrBi.sub.4
 Ti.sub.4 O.sub.15, SrBi.sub.2 Ta.sub.2 O.sub.9)
 The Invention being thus described, it will be obvious that the invention
 may be varied in many ways. Such variations are not be regarded as a
 departure form the sprit and scope of the Invention, and all such
 modifications as would be obvious to one skilled in the art are Intended
 to be included within the scope of the following claims.