Dual damascene structure and its manufacturing method

The present invention relates to a dual damascene structure and its manufacturing method. The invention uses two implanting step to form two stop layers. It uses the stop layers to perform an anisotropic etching step so as to form a via and trench. Finally, a conductive layer is filled into the via and trench followed by the completion of forming of the dual damascene structure. The invention controls the etching stop. Another advantage of the present invention is that of using the spacer as the trench mask instead of the multi-mask. Therefore, misalignment is prevented in the present invention.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates in general to a semiconductor component and its 
manufacturing method, and more particularly to a multi-level metallization 
and interconnection component and its manufacturing method. 
2. Description of the Related Art 
As the level of integration for integrated circuits increases, the number 
of interconnects necessary for linking up devices increases, too. 
Therefore, design employing two or more metallic layers is gradually 
becoming the norm in the fabrication of integrated circuits. When the 
level of integration is further increased a high production yield and good 
reliability is difficult to get. Damascene processing method is a 
fabrication technique that involves the creation of interconnect lines by 
first etching a trench in a planar dielectric layer, and then filling that 
trench with metal. The method is capable of introducing copper metal which 
is not easily etched into the semiconductor device. Therefore, this method 
is the best choice in the manufacturing industry for sub-quarter micron 
interconnects. 
Conventional damascene processing technique has a number of problems. For 
example, depth of trench lines is hard to control, profile of via sidewall 
is difficult to standardize and the processing window is quite narrow. 
FIG. 1A to FIG. 1D are cross-sectional views showing the manufacturing 
steps of a conventional dual damascene processing method. As shown in FIG. 
1A, an insulator layer 102 is deposited over a semiconductor substrate 
100. Then, a mask is used to define the pattern of the interconnection on 
the insulator layer 102. An etching process is carried out for forming a 
trench 104 in the insulator layer 102. 
Next, referring to FIG. 1B, a thick photoresist layer 106 is formed over 
the insulator layer 102, filling in the trench 104. Defining and etching 
processes are then performed to expose the surface of the insulator layer 
102 in the trench 104 so as to form a first via 108. 
Then, as shown in FIG. 1C, an etching process is performed to remove parts 
of the insulator layer 102 exposed in the first via 108 and to form a 
second via 108', exposing the semiconductor substrate 100. 
Next, the photoresist layer 106 is removed as shown in FIG. 1D so as to 
form a third via 110 with two different of widths. A conductive layer (not 
shown) is formed over the entire structure; thereafter a polishing process 
is performed to remove the conductive layer over the insulator layer 102. 
This completes the forming of the dual damascene structure. 
The method of manufacturing the dual damascene according the conventional 
method described above is not without flaws. After the trench is formed, 
it is necessary to perform a photolithography step for forming the first 
via. And, the width of the first via is smaller than the trench, therefore 
misalignment of the pattern occurres during the defining procedure. 
Furthermore, it is difficult to etch and form the via owing to the larger 
aspect ratio of the second via. 
FIG. 2A to FIG. 2E are cross-sectional views showing the manufacturing 
steps of another conventional dual damascene processing method. As shown 
in FIG. 2A, an insulator layer 202 is deposited over a semiconductor 
substrate 200. Then, a mask is used to define the pattern of the 
interconnection on the insulator layer 202. An etching process is carried 
out to form a trench 204 within the insulator layer 202 and expose the 
surface of the semiconductor substrate 200. 
Next, referring to FIG. 2B, a layer of photoresist 206 is formed over the 
insulator layer 202, filling the via 204. Then, as shown in FIG. 2C, a 
mask is used to define the pattern of the trench 208 within the 
photoresist layer 206, and the undesired photoresist 206 is removed to 
expose parts of the insulator layer 202. The photoresist plug 206' remains 
in the via 204. The width of the trench 208 is larger than the via 204. 
Referring to FIG. 2D, an etching step is then performed on the insulator 
layer 202 so as to form a trench 208' by using the trench pattern 208 
within the photoresist layer 206. 
Next, as shown in FIG. 2E, the photoresist layer 206 and photoresist plug 
206' are removed. A conductive layer (not shown) is formed on the entire 
structure; thereafter a polishing process is performed to remove the 
conductive layer over the insulator layer 202. This completes the forming 
of the dual damascene structure. 
The method described above still has drawbacks. For example, there is no 
etching stop layer within the insulator layer, therefore it may be 
over-etched during the trench etching operation. As the level of 
integration for integrated circuits increases, it is harder and harder to 
remove the photoresist plug within the via. Furthermore, this method also 
uses several photolithographic and etching steps which are accompanied by 
misalignment during the via and trench formation procedures. 
SUMMARY OF THE INVENTION 
It is therefore an object of the invention to provide a dual damascene 
structure and its manufacturing method which uses a nitrogen implantation 
step to form an etch stop layer. The present invention improves the 
controll of the etching stop during the etching process which is used to 
form the trench. In addition, the polysilicon or silicon nitride layer is 
used as masks for reducing misalignment during the step forming of the via 
and trench. 
The invention achieves the above-identified objects by providing a new 
method of forming a dual damascene structure. A dielectric layer is formed 
above a semiconductor substrate. A patterned mask layer is formed on the 
dielectric layer. A first implanting step is performed to implant nitrogen 
gases or ions and a thermal annealing step is then performed so as to form 
a first etching stop layer in the dielectric layer. The first etching stop 
layer has a via opening at the position corresponding to the mask layer. A 
patterned photoresist layer is formed. Then, a spacer is formed on the 
sidewall of the photoresist layer and the spacer layer under the 
photoresist layer remains. A second implanting step is performed to form a 
second etching stop layer on the dielectric layer; the second etching stop 
layer has a trench opening. Thereafter, the spacer layer, spacer, and mask 
layer are removed. Parts of the dielectric layer are removed to form the 
trench and via by using an anisotropic etching step. A conductive layer is 
formed in the trench and via so as to form the dual damascene structure 
coupled to the semiconductor substrate. 
The invention achieves the above-identified objects by providing another 
new method of forming a dual damascene structure. A dielectric layer is 
formed above the semiconductor substrate. A mask layer having an opening 
is formed on the dielectric layer. A spacer is formed on the sidewall of 
the opening. An implanting stop layer is formed in the dielectric layer by 
performing a first implanting step to implant nitrogen ions. The 
implanting stop layer is formed at the position corresponding to the 
opening formed by the spacer. The spacer is removed, and another trench 
opening is formed in the mask layer. A second implanting step is performed 
to form an etching stop layer in the dielectric layer. The etching stop 
layer is formed at the position corresponding to the opening on the mask 
layer. A third implanting step is performed to reduce the 
anti-implantation ability of the implanting stop layer. The implanting 
stop layer is transformed into an incohesive structure or oxide-like 
structure. Then, an anisotropic etching step is performed to form a trench 
and via. The via exposes the semiconductor substrate. Finally, a 
conductive layer is formed in the trench and via. This completes the 
formation of the dual damascene structure.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
FIGS. 3A to 3I are cross-sectional views showing the process steps of one 
preferred embodiment of the method for manufacturing the dual damascene. 
Referring to FIG. 3A, a dielectric layer 302 is formed on a semiconductor 
substrate 300. There are many devices formed on the substrate, but they 
are not shown in order to simplify the figures. The dielectric layer 302, 
for example, is a silicon dioxide or borophosphosilicate glass layer, with 
a thickness of about 20000 .ANG.. A layer of mask 304 is then formed on 
the dielectric layer 302. 
Next, referring to FIG. 3B, a first implanting step I.sub.31 is performed 
to implant reactants, for example, nitrogen gases or ions, into dielectric 
layer 302 by using the mask layer 304. Then, an annealing step at a 
temperature of about 350-450.degree. C. is performed to form a first 
etching stop layer 306, for example, a silicon nitride layer, at a depth 
of about 9000-10000 .ANG.. The range of the annealing temperature is 
controlled so it does not affect the diffusion of the implants. The U.S. 
Pat. No. 5,314,843 discloses an implanting method regarding control of the 
implanting energy to implant reactants into the determined depth with a 
determined concentration. 
Thereafter, referring to FIG. 3C, after the first etching stop layer 306 is 
formed, a layer of spacer 308, for example, titanium nitride or 
polysilicon spacer, is formed, for example, by chemical vapor deposition 
method, over the dielectric layer 302 and the mask layer 304. Then, a 
layer of photoresist 309 is formed over the spacer 308. 
Next, referring to FIG. 3D, parts of the spacer layer 308 and photoresist 
layer 309 are removed until the top surface of the mask layer 304 is 
exposed so as to form a spacer 308' on the sidewall of the mask 304 and to 
leave a spacer 308" under the second photoresist layer 309. The first 
photoresist layer 304, spacer 308', and spacer 308" constitute a trench 
mask. 
As shown in FIG. 3E, a second implanting is performed to implant reactants, 
for example, nitrogen ions, into the dielectric layer 302. Then, an 
annealing step at a temperature of about 350-450.degree. is performed to 
form a second etching stop layer 310, for example, a silicon nitride 
layer, with the depth of about 1000-2000 .ANG. by using the trench mask. 
Referring again to the U.S. Pat. No. 5,314,843, an implanting method is 
disclosed regarding control of the implanting energy to implant reactants 
into the determined depth at a determined concentration. 
Next, referring to FIG. 3F, the trench mask is removed. The first etching 
stop layer 306 and second etching stop layer 310 are formed within the 
dielectric layer 302. The first etching stop layer 306 has an opening 
which is used to form a via, and the second etching stop layer 310 has an 
opening which is used to form a trench. The size of the opening in the 
first etching stop layer 306 corresponds to the mask layer 304, and the 
size of the opening in the second etching stop layer 310 corresponds to 
the size of the opening in the trench mask. Therefore the size of the 
trench is larger than the via. 
Referring to FIG. 3G, parts of the dielectric layer 302 are removed, for 
example, by using an anisotropic etching method and using the first and 
second etching stop layers 306 and 310 as stop layers for protecting the 
underneath dielectric layer 302 from etching. Furthermore, the first and 
second etching layer 306 and 310 have openings; therefore the trench/via 
312 and trench 313 are formed during the etching process. Additionally, 
the substrate is exposed by the via 312. 
Next, referring to FIG. 3H, a conductive layer 314 is formed over the 
structure illustrated in FIG. 3G. The conductive layer 314 is made of 
metal, for example, copper, aluminum, aluminum alloy or aluminum-copper 
alloy. 
Referring to FIG. 3I, the conductive layer 314 over the second etching stop 
layer 310 is removed, for example, by chemical mechanical polishing 
method, so as to form an interconnect structure 314' in the trench/via 312 
and trench 313. This completes the forming of the dual damascene 
structure. 
FIGS. 4A to 4G are cross-sectional views showing the process steps of 
another preferred embodiment of the method for manufacturing the dual 
damascene. 
First, referring to FIG. 4A, a dielectric layer 402 is formed on a 
semiconductor substrate 400. There are many devices formed on the 
substrate, but they are not shown in order to simplify the figures. The 
dielectric layer 402 is, for example, a silicon dioxide or 
borophosphosilicate glass layer, with a thickness of about 20000 .ANG.. A 
layer of mask 404 with an opening is formed on the dielectric layer 402. 
Next, referring to FIG. 4B, a layer of spacer 406, for example, titanium 
nitride or polysilicon, is formed, for example, by using a chemical vapor 
deposition method, over the structure illustrated in FIG. 4A. 
As shown in FIG. 4C, parts of the spacer 406 are removed, for example, by 
using an etching back method, to form a spacer 406' on the sidewall of the 
mask layer 404 in the opening. Then, a first implanting step I.sub.41 is 
performed for implanting reactants, for example, nitrogen ions, into the 
dielectric layer 402 to form a implanting stop layer 408, for example, a 
silicon nitride layer, with a depth of about 1000-2000 .ANG. by using the 
mask layer 404 and spacer 406'. The U.S. Pat. No. 5,314,843 discloses an 
implanting method regarding control of the implanting energy to implant 
reactants into the determined depth at a determined concentration. The 
size of the implanting stop layer 408 is the same as the opening formed in 
the spacer 406' and mask layer 404. 
Next, referring to FIG. 4D, the spacer 406' is removed and then an another 
defining step is performed to form a trench opening in the mask layer 
406'. A second implanting process I.sub.42 is performed to implant 
reactants, for example, nitrogen ions, into the dielectric layer 402. 
Then, an annealing process with a higher temperature is performed to form 
an etching stop layer 410, for example, a silicon nitride layer, with a 
depth of about 9000-10000 .ANG.. Referring again to the U.S. Pat. No. 
5,314,843, it discloses an implanting method regarding control of the 
implanting energy to implant reactants at a determined depth with a 
determined concentration. Because the implanting stop layer 408 and mask 
layer 404 can be used as barrier layers during the second implanting 
process I.sub.42, the etching stop layer 410 is not formed behind the 
implanting stop layer 408 and mask layer 404. 
Then, referring to FIG. 4E, a third implanting step I.sub.43 is performed 
to transform the implanting stop layer 408 into an incohesive structure 
408', for example, by implanting oxygen gases into the implanting stop 
layer 408 without performing the high temperature annealing step, but so 
that a dielectric layer 402-like layer is formed during the high 
temperature annealing step. This third implanting step I.sub.43 destroys 
the crystal of the silicon nitride or reduces the silicon nitride layer 
into the oxide-like structure. It therefore undoes the barrier ability of 
the implanting stop layer 408. 
Thereafter, referring to FIG. 4F, parts of the dielectric layer 402 are 
removed, for example, by using an anisotropic etching method, so as to 
exposes the semiconductor substrate 400 by using the mask layer 404 and 
etching stop layer 410 as barrier layers. Therefore, the dielectric layer 
402 under the mask layer 404 and etching stop layer 410 aren't be removed, 
and finally a trench/via 412 and a trench 413 are formed. 
Next, as shown in FIG. 4G, a conductive layer, for example, a metal layer, 
is formed over the structure as shown in FIG. 4F. The material used for 
the conductive layer can be copper, aluminum, aluminum alloy or 
aluminum-copper alloy. The conductive layer over the mask layer 404 is 
removed, for example, by using a chemical mechanical polishing method, to 
form an interconnection structure 414 in the trench/via 412 and trench 
413. This completes the forming of the dual damascene structure. 
The characteristic of the present invention includes using two implanting 
step to form the two etching stop layer within the dielectric layer. The 
invention does not have difficulty in controlling the etching stop, as 
does the prior art. 
Another characteristic of the present invention is that of providing a dual 
damascene structure and its manufacturing method. The present invention 
uses the spacer as the trench mask, but two mask are used in the prior 
art. The misalignment of the conventional method doesn't occurred in the 
present invention. 
While the invention has been described by way of example and in terms of a 
preferred embodiment, it is to be understood that the invention is not 
limited thereto. To the contrary, it is intended to cover various 
modifications and similar arrangements and procedures, and the scope of 
the appended claims therefore should be accorded the broadest 
interpretation so as to encompass all such modifications and similar 
arrangements and procedures.