Extremal voltage detector with high input impedance

An extremal voltage detector produces an output voltage from an operational amplifier having its non-inverting input terminal connected to a first node and its inverting input terminal connected to a second node. A number of identical metal-oxide-semiconductor field-effect transistors (MOSFETs) controlled by respective input voltages are connected in parallel between the first node and a first power supply terminal. Another identical MOSFET, controlled by the output voltage, is connected between the second node and the first power supply terminal. Alternatively, a plurality of identical MOSFET detection circuits, controlled by the input and output voltages, are connected in parallel between the first power supply node and the first and second nodes. A pair of constant-current circuits conduct equal currents from the first and second nodes to a second power-supply terminal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an extremal voltage detector, more specifically to a maximum voltage detector for detecting the highest of a plurality of input voltages and a minimum voltage detector for detecting the lowest of a plurality of input voltages.

2. Description of the Related Art

FIG. 1is a schematic diagram of a conventional maximum value detector disclosed in Japanese Patent Application Publication No. 2005-5808.

This detector generates an output voltage z equal to the highest among three input voltages x1to x3. The detector comprises npn transistors Q11to Q13receiving input voltages x1to x3at their bases, an npn transistor Q1rthat generates the output voltage z by feedback at its base, a current source Jt for driving npn transistors Q11to Q13and Q1r, and pnp transistors Q21to Q23and Q2rfor feeding identical currents to the turned-on transistors among npn transistors Q11to Q13and Q1r. Transistors Q11to Q13and Q1rare formed so as to have identical VBE-IE (base-emitter voltage vs. emitter current) characteristics.

The detector also has npn transistors Q31to Q33and pnp transistors Q41to Q43that control the base currents of pnp transistors Q21to Q23, current sources J1to J3for driving respective npn transistors Q31to Q33, and an output impedance converter F. The impedance converter F comprises an npn transistor Qa driven by a current source Ja and a pnp transistor Qb driven by another current source Jb.

The emitters of npn transistors Q11to Q13and Q1rare connected in common to current source Jt, and their collectors are connected through respective transistors Q21to Q23and Q2rto a terminal from which they receive a power supply potential VCC. The base of transistor Q1ris connected to the emitter of pnp transistor Qb in the impedance converter F.

Transistors Q31to Q33have their collectors all connected to the power supply potential (VCC), their bases connected to the collectors of respective transistors Q21to Q23, and their emitters connected to respective current sources J1to J3. Transistors Q41to Q43have their bases connected to the emitters of respective transistors Q31to Q33, their emitters connected to the bases of respective transistors Q21to Q23, and their collectors all connected to ground (GND).

The bases of transistors Q21to Q23are connected in common to the base of transistor Q2r, forming a current mirror in which transistors Q21to Q23constitute the input side and transistor Q2rconstitutes the output side.

The operation of this circuit will be described under the assumption that input voltage x1is the highest of the three input voltages x1to x3.

Under this assumption, transistor Q11pulls the emitter voltages of transistors Q11, Q12, Q13, Q1rup to a value V01equal to the difference (x1−VBE1) between input voltage x1and the base-emitter voltage VBE1at which transistor Q11turns on. The base-emitter voltages of transistors Q12, Q13are less than VBE1, so while transistor Q11is turned on, transistors Q12and Q13are turned off. This forces up the base voltages of transistors Q32, Q33. Because transistors Q32, Q33operate as emitter followers, the base voltages of transistors Q42, Q43are likewise pulled up. As a result, transistors Q42, Q43are turned off and do not draw base current from transistors Q21, Q22, Q23, Q2r.

Conversely, the turned-on transistor Q11pulls down the base voltage of emitter-follower transistor Q31, and accordingly lowers the base voltage of transistor Q41. Transistor Q41is thereby turned on and draws base current from transistor Q21, enabling transistor Q21to supply collector current I1to transistor Q11. Transistor Q41also draws base currents from transistors Q22, Q23, and Q2r, but the collector currents I2, I3of transistors Q22, Q23flow to the bases of transistors Q32, Q33, respectively, instead of to transistors Q12, Q13, which are turned off.

The voltage that appears at the base of transistor Q1ris obtained by adding the base-emitter voltage VBE2of transistor Q1rto its emitter voltage V01. Accordingly, the output voltage z can be calculated as follows:
z=V01+VBE2=x1−VBE1+VBE2

Since transistors Q21to Q23and Q2rconstitute a current mirror, transistors Q11and Q1rconduct identical currents. From the identical VBE-IE characteristics of transistors Q11and Q1r, it follows that their base-emitter voltages are equal (VBE1=VBE2). The output voltage z is therefore equal to input voltage x1(z=x1), so that the highest voltage x1among the input voltages x1to x3is output as the output voltage z.

Since this maximum voltage detector is a bipolar transistor circuit, however, it draws input current. In the example above, input current is drawn into the base of transistor Q11. If the voltage source connected to the base of transistor Q11has high output impedance, the flow of input current produces a significant drop in the input voltage, which has been problematic.

If, for example, the voltage source connected to the base of transistor Q11has an output impedance of one hundred kilohms (100 kΩ) and the base current of transistor Q11is one milliampere (1 μA), the resulting voltage drop ΔV is 100 mV (=100 kΩ×1 μA).

Accordingly, this maximum voltage detector is inapplicable to circuits such as liquid crystal driver circuits in which a current drain of several tens on nanoamperes is enough to lead to pixel on-off malfunctions.

SUMMARY OF THE INVENTION

An object of the present invention is to provide maximum and minimum voltage detectors that do not draw input current.

The invention provides an extremal voltage detector comprising metal-oxide-semiconductor field-effect transistor (MOSFET) circuits that receive a plurality of input voltages and generate a single output voltage representing the maximum or minimum of the input voltages, depending on the circuit configuration and the types of MOSFETs employed.

The detector is powered from a first power supply terminal that supplies a first potential and a second power supply terminal that supplies a second potential. One of the two potentials may be a ground potential. The detector has a first node and a second node. A first constant-current circuit conducts a constant current between the first node and the second power supply terminal; a second constant-current circuit conducts an identical constant current between the second node and the second power supply terminal. The output voltage is produced by an operational amplifier having its non-inverting input terminal connected to the first node and its inverting input terminal connected to the second node.

In a first aspect of the invention the detector has a plurality of identical first MOSFETs, connected in parallel between the first power supply terminal and the first node, that receive the input voltages at their gates. A second MOSFET, having the same channel type and electrical characteristics as the first MOSFETs, is connected between the first power supply terminal and the second node, and receives the output voltage at its gate.

This detector detects the maximum input voltage if the first potential is higher than the second potential and the MOSFETs are n-channel (NMOS) transistors. The minimum input voltage is detected if the first potential is lower than the second potential and the MOSFETs are p-channel (PMOS) transistors.

In a second aspect of the invention the detector has a plurality of identical detection circuits connected in parallel between the first power supply terminal and the first and second nodes. Each detection circuit includes four MOSFETs. The first MOSFET has its source connected to the first node and its drain connected to the drain of the second MOSFET, and receives one of the input voltages at its gate. The second and third MOSFETs have their sources connected to the first power supply terminal and form a current mirror, their gates both being connected to the drain of the second MOSFET. The fourth MOSFET has its source connected to the second node and its drain connected to the drain of the third MOSFET, and receives the output voltage at its gate.

This detector detects the maximum input voltage if the first potential is higher than the second potential, the second and third MOSFETs are PMOS transistors, and the first and fourth MOSFETs are NMOS transistors. The minimum input voltage is detected if the first potential is lower than the second potential, the second and third MOSFETs are NMOS transistors, and the first and fourth MOSFETs are PMOS transistors.

In both aspects of the invention, since the input voltage signals are received at the gates of MOSFETs, no input current is drawn, and the maximum or minimum input voltage can be detected accurately even if some of the input signal sources have high output impedance.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters.

First Embodiment

The first embodiment is a maximum voltage detector that detects, for example, the maximum of a plurality of pixel driving voltages to permit automatic adjustment of the luminance or contrast of a liquid crystal display. The maximum voltage detector comprises a plurality of n-channel metal-oxide-semiconductor (NMOS) transistors11,12, . . . ,1n. The gates of NMOS transistors11,12, . . . ,1nreceive, in this example, respective display-pixel driving voltages as input voltages IN1, IN2, . . . , INn.

The drains of NMOS transistors11,12, . . . ,1nare connected to a first power supply terminal that supplies a positive potential VDD. Their sources are connected in common to a first node N1. Node N1is connected through a constant current source2to a second power supply terminal that supplies zero or ground potential (GND); node N1is also connected to the non-inverting input terminal of an operational amplifier (OP)3.

The inverting input terminal of the operational amplifier3is connected to a second node N2, which is connected to the source of an NMOS transistor4. The drain of NMOS transistor4is connected to the VDD terminal, and its gate is connected to the output terminal of the operational amplifier3, from which an output voltage OUT is output. A constant current source5for supplying a constant current to NMOS transistor4is also connected between node N2and the ground terminal.

NMOS transistors11to1nand4are formed so as to have identical threshold voltages VT and identical gate-source voltage vs. drain current (VGS-ID) characteristics. The constant currents I supplied by constant current sources2,5are also mutually equal.

Next, the operation of the circuit inFIG. 2will be described, under the assumption that input voltage IN1is the highest among the input voltages IN1to INn.

The voltage VN1at node N1is then pulled up by NMOS transistor11to a voltage lower than the input voltage IN1by an amount substantially equal to the threshold voltage VT of NMOS transistor11(VN1=IN1=VT). The other NMOS transistors12to1nare turned off because their gate-source voltages (the difference between each of their input voltages IN2to INn and the voltage VN1of node N1) is less than the threshold voltage VT.

Since the output voltage OUT of the operational amplifier3is supplied to the gate of NMOS transistor4, the voltage VN2at node N2is obtained substantially by subtracting the threshold voltage VT of NMOS transistor4from the output voltage OUT (VN2=OUT−VT).

Since nodes N1and N2are connected to the non-inverting and inverting input terminals of the operational amplifier3, respectively, the output voltage OUT is controlled by the operational amplifier3so as to make the voltages VN1, VN2at nodes N1, N2mutually equal. That is, the operational amplifier3performs feedback control so as to produce the following relationship.
IN1−VT=OUT−VT

Accordingly, the relationship OUT=IN1is obtained, which indicates that the highest voltage IN1among the input voltages IN1to INn is output as the output voltage OUT.

As described above, the maximum voltage detector of the first embodiment comprises NMOS transistors that receive the input voltages IN1to INn at their gates and therefore do not draw input current. A resulting advantage is that the maximum voltage can be detected with high accuracy even if the input signal sources have high output impedance.

A maximum voltage detector has been described in the first embodiment, but a minimum voltage detector can also be configured if NMOS transistors11to1nare replaced with PMOS transistors and the constant current sources2,5are disposed on the VDD side of the circuit.

In the first embodiment, if a plurality of input voltages have values substantially equal to the maximum voltage, the constant current I conducted by constant current source2is divided into branch currents flowing through the NMOS transistors receiving these maximum input voltages. The resistive voltage drops in these NMOS transistors are thereby reduced, raising the voltage at the non-inverting input terminal of the operational amplifier and introducing the possibility that the maximum voltage will not be detected accurately. This possible inaccuracy is avoided in the second embodiment, described below.

Second Embodiment

In detection circuit101, NMOS transistor11receives input voltage IN1at its gate, has its source connected to a first node N1, and has its drain connected to a first internal node N3. To this node N3are connected the gates of PMOS transistors12,13and the drain of PMOS transistor12. The sources of PMOS transistors12,13are connected to the VDD terminal. PMOS transistors12,13thus constitute a current mirror. The drain of PMOS transistor13is connected to a second internal node N4, which is connected to the drain of NMOS transistor14. The source of NMOS transistor14is connected to a second node N2, and its gate receives the output voltage (OUT) of the maximum voltage detector from an operational amplifier3.

Similarly, in each of the detection circuits102to10nthat receive input voltages IN2to INn, the sources of the NMOS transistors11,14are connected to respective nodes N1, N2, and the gate of NMOS transistor14receives the output voltage OUT.

The constant current sources2,5are connected between node N1and ground and between node N2and ground, respectively. The non-inverting and inverting input terminals of the operational amplifier3are connected to respective nodes N1, N2. The output terminal of the operational amplifier3outputs the output signal OUT. In each of the detection circuits101to10n, PMOS transistors12,13have the same gate length and width and NMOS transistors11,14also have the same gate length and width. The constant current sources2,5conduct equal currents.

Next, the operation of the circuit inFIG. 3will be described under the assumption that input voltage IN1is the highest among the input voltages IN1to INn.

The source voltage of NMOS transistor11in detection circuit101(voltage VN1at node N1) then becomes lower than the input voltage IN1by substantially the threshold voltage VT of this NMOS transistor11, so the difference between each of the other input voltages IN2to INn and voltage VN1is less than the threshold voltage VT, causing the NMOS transistors11in detection circuits102to10nto turn off.

The voltage VN1at node N1is not precisely equal to the voltage obtained by subtracting the threshold voltage VT from the input voltage IN1. Since NMOS transistor11has an on-resistance R1, if the current flowing through NMOS transistor11(the current supplied by the constant current source2) is denoted I, the voltage VN1is given by the following equation:
VN1=IN1−VT−(R1×I)

The current I flowing through NMOS transistor11also flows through the PMOS transistor12connected in series with NMOS transistor11, and an identical current flows through PMOS transistor13and NMOS transistor14, because PMOS transistors12and13constitute a current mirror. Since the gate of NMOS transistor14receives the output voltage OUT, if the on-resistance of NMOS transistor14is denoted R4, the voltage VN2at node N2is given by the following equation:
VN2=OUT−VT−(R4×I)

Since nodes N1, N2are connected to the non-inverting and inverting input terminals of the operational amplifier3, respectively, the output voltage OUT is controlled by the operational amplifiers3so as to make the voltages VN1, VN2at the nodes N1, N2mutually equal. That is, the operational amplifier3performs feedback control so as to produce the following relationship.
IN1−VT−(R1×I)=OUT−VT−(R4×I)

Since NMOS transistors11,14are identically dimensioned, the condition R1=R4is satisfied. Accordingly, the above equation reduces to OUT=IN1, which implies that the highest voltage IN1among the input voltages IN1to INn is output as the output voltage OUT.

Next, it will assumed that the input voltages IN1, IN2among the input voltages IN1to INn have substantially the same voltage VMAX, which is higher than the other input voltages IN3to INn.

In this case, the two NMOS transistors11in detection circuits101and102are simultaneously turned on, and the current I supplied from constant current source2is divided into two equal branch currents. The voltage VN1at node N1is now given by the following equation:
VN1=VMAX−VT−(R1×I/2)

In both of these detection circuits101,102, a current having the same value (I/2) also flows through the mirroring PMOS transistor13and NMOS transistor14. Therefore, the voltage VN2at node N2is given by the following equation:
VN2=VMAX−VT−R4×(I/2)

Since nodes N1and N2are connected to the non-inverting and inverting input terminals of the operational amplifier3, respectively, the output voltage OUT is controlled by the operational amplifier3so that the voltages VN1, VN2at the respective nodes N1, N2are mutually equal. That is, the operational amplifier3performs feedback control so as to establish the following relationship.
VMAX−VT−(R1×I/2)=OUT−VT−(R4×I/2)

Since R1=R4as noted above, the above equation reduces to OUT=VMAX. This implies that even if a plurality of the input voltages IN1to INn have the maximum voltage VMAX, this voltage VMAX is correctly output as the output voltage OUT.

As described above, the maximum voltage detector of the second embodiment comprises NMOS transistors that receive the input voltages IN1to INn at their gates, so that no input current is drawn and the same advantage as in the first embodiment is obtained.

Further, the maximum voltage detector of the second embodiment has current mirror detection circuits101to10nthat receive the input voltages IN1to INn, each of the detection circuits101to10nincluding an NMOS transistor11that conducts current in response to the input voltage and an NMOS transistor14that conducts a mirrored current. Feedback control brings the voltage VN2at the node N2to which the sources of NMOS transistors14are connected to the same level as the voltage VN1at the node N1to which the sources of NMOS transistors11are connected. An advantage of the second embodiment is that regardless of the number of input voltages having the maximum value, the maximum voltage is detected with high accuracy because the NMOS transistors11,14conduct equal currents in each of the detection circuits10.

A maximum voltage detector has been described in the second embodiment, but a minimum voltage detector can also be obtained by replacing NMOS transistors with PMOS transistors and vice versa and interchanging the power supply and ground potentials.

Those skilled in the art will recognize that further variations are possible within the scope of the invention, which is defined in the appended claims.