Digital adjustment of gain and offset for digital to analog converters

Improved digital to analog converter (DAC) circuitry incorporating the ability to utilize a single DAC to generate either voltage or current outputs, and the ability to digitally adjust the gain and offset. Previous digital to analog circuitry has been limited to a single type of analog output per DAC and to the use of external precision resistors to set the gain and offset for a single DAC, or a group of DACs. By utilizing the same on-chip circuitry to supply both types of outputs, chip area, power consumption and cost is reduced while offering more flexibility to the customer. The ability to digitally adjust the gain and offset for a group of DACs eliminates the cost of external resistors, lowers the board area, and lowers the assembly cost for the end product. In addition, since gain and offset can be adjusted dynamically, maximum flexibility is provided to the customer. Digital adjustment of gain and offset can be used to calibrate for chip and system errors, and can allow more exact adjustment and external precision resistors.

FIELD OF THE INVENTION

The invention relates to the field of integrated circuits and more particularly to the field of digital to analog converter circuitry.

BACKGROUND OF THE INVENTION

Circuits that convert a digital value, such as a sequence of binary digits, to an analog value, such as voltage or current, are known generally as digital to analog converters, or DACs. The output of a DAC can be an analog voltage or an analog current. In a typical DAC, a binary value is written into a register and circuitry converts this value into a voltage or current, which is available as an output from the DAC. It is often desirable that the analog output vary linearly with the digital input, and in this case, the conversion of the binary value into the voltage or current is a function of the gain and offset of the DAC. The voltage output of a linear DAC can be expressed as:
Vout=(Vgain·(DATA/MAX))+Voffset
and the current output of a linear DAC can be expressed as:
Iout=(Igain·(DATA/MAX))+Ioffset
where Vgainis the voltage gain, Voffsetis the voltage offset, Igainis the current gain, Ioffsetis the current offset, DATA is the digital input value and MAX is two raised to the number of bits in the digital input (e.g., 8192 in the case of a 13-bit digital input value). Voltage and current offsets and gains in general are not limited to positive values and can vary arbitrarily.

An existing method for setting the gain and offset of a DAC is to attach external precision resistors to the integrated circuit containing the DAC circuitry. The resistance of the resistors determines the gain and offset. In cases where multiple DACs are incorporated into a single integrated circuit, often the gain and offset for an entire group of DACs is set with a single pair of external resistors. A group of DACs can be of any size, and there can be any number of DACs implemented on a single device. The Edge6420, manufactured by Semtech Corporation, is an example of a device incorporating multiple groups of DACs. The Edge6420 has one group of 20 DACs, four groups of 8 DACs each, and one group of 12 DACs, for a total of 64 DACs. Typically DACs are configured either as voltage output DACs or current output DACs. In the case of the Edge6420, four of the groups consist of voltage output DACs and two of the groups consist of current output DACs.

The use of DACs dedicated to either voltage outputs or current outputs has several disadvantages. First, it decreases the flexibility of the device since the integrated circuit manufacturer fixes the number of current and voltage outputs. Alternatively, if user configuration of either current or voltage mode is desired, it increases the cost and power consumption of the device since two DACs would then be needed for a single output.

The use of external resistors to set the gain and offset for a group of DACs has several disadvantages. First, the customer must change the external resistors to change the gain or offset of a DAC group. This means that either a physical change to the device is needed, or the gain and offset must be fixed and cannot change dynamically. Also, since DACs may have a fairly large range of gains and offsets, a fairly large range of resistances is needed. Additionally, the precision of the gain and offset is limited by the precision of the resistors. Finally, the use of external resistors increases the cost of the end product (due to the cost of the resistors and the cost of additional board space), increases the cost of packaging due to additional pins, increases the cost of assembly, and increases the physical size of the end product.

SUMMARY OF THE INVENTION

The present invention is an improved apparatus for implementing DAC circuitry.

In some embodiments, a single DAC is used to provide either a voltage output or a current output depending on a mode signal.

In other embodiments, two levels of analog to digital converters are used, i.e., a first level of control DACs to digitally adjust the gain or offset and a second level of output DACs to generate the desired output. There may be two control DACs, i.e., one to set the gain of an output DAC and one to set the offset of an output DAC. The output DAC may provide a voltage output or a current output. There may be multiple output DACs forming a group, such that all of the gains and offsets of the output DACs in the group are set by the same control DACs. In the case of control signals from the control DACs that are voltages, they can be wired directly to multiple output DACs. In the case of control signals from the control DACs that are currents, they can be mirrored to create equivalent currents, each of which is wired to a single output DAC.

In some embodiments, a second digital input is provided to the control DACs and the two digital inputs are added together.

DETAILED DESCRIPTION

The present invention is directed to improved analog to digital conversion circuitry incorporating features that increase the flexibility and lower the cost. In particular, the ability to digitally adjust gain and offset is provided, and circuitry to allow a single converter to provide either a voltage output or a current output is provided.

FIG. 1illustrates a prior art voltage output digital to analog converter (DAC) circuitry. CSdac110is a current steering digital to analog converter (CSdac) that accepts digital input180, voltage gain170, voltage offset160and produces a current output on line120, proportional to the binary value present on digital input180. Current output120is coupled to the negative input of voltage amplifier140and to one side of feedback resistor130. The positive input of voltage amplifier140is coupled to ground and the other side of feedback resistor130is coupled to the output of voltage amplifier140. The output of voltage amplifier140is also coupled to the voltage output pad150.

The DAC circuitry inFIG. 1converts the 13-bit binary input value present on digital input180into an analog output voltage on pin150, linearly proportional to the digital input. The current steering DAC110is used to convert the digital input into a current, and voltage amplifier140is used to convert the current into a voltage. The feedback resistor130is ratiometrically matched to resistors internal to CSdac110. Ratiometric matching is a method of laying out on-chip resistors such that the ratio of the resistances is tightly controlled and precisely known, even if the absolute value of resistance is not. By using ratiometric matching, it is possible to develop circuitry with very accurate outputs even when the resistances themselves are not known very accurately. The voltage gain170and voltage offset160inputs to CSdac110are generated by the circuitry illustrated inFIG. 3, discussed below.

FIG. 2illustrates a prior art current output DAC circuitry. CSdac210accepts digital input280, current gain270and produces a current output on line220, proportional to the binary value present on digital input280. Current output220is coupled to the negative input of current amplifier240and to one side of feedback resistor230. The other side of feedback resistor230is coupled to the output of current amplifier240and to another feedback resistor260. The positive input of current amplifier240is coupled to output pad250and to the other side of feedback resistor260.

The DAC circuitry inFIG. 2converts the 13-bit binary input value present on digital input280into an analog output current on pin250, linearly proportional to the digital input. The current steering DAC210is used to convert the digital input into a current, and current amplifier240is used to amplify that current into a current to be supplied external to the device. The feedback resistors230and260are ratiometrically matched to each other as described above. The ratio of feedback resistor230to feedback resistor260determines the current gain from CSdac output220to the current supplied to output pad250. The current gain270input to CSdac210is generated by the circuitry illustrated inFIG. 4, discussed below.

FIG. 3illustrates prior art circuitry in which external resistors are used to set the gain and offset for a group of voltage output DACs. Externally supplied reference voltage Vref305is coupled to the negative input of master amplifier310. Master amplifier310output315is coupled to six-transistor current mirror320, which creates three matching currents. A current mirror utilizes the ability to create on-chip transistors that have matching characteristics, and thus identical source currents for a given gate voltage. One end of current mirror320is coupled to source voltage supply VDD and the three current outputs are coupled to master resistor pad325, voltage gain resistor pad345and to conductor340respectively. Master resistor pad325is also coupled to the positive input of master amplifier310and to one side of external resistor335. The other side of external resistor335is coupled to ground. Voltage gain resistor pad345is also coupled to voltage gain output355and to one side of external resistor350. The other side of external resistor350is coupled to ground. Conductor340is coupled to four-transistor current mirror375, which creates two matching currents. One end of current mirror375is coupled to source voltage supply VSS and the two current outputs are coupled to conductor340and to voltage offset resistor pad365, respectively. Voltage offset resistor pad365is also coupled to voltage offset output370and to one side of external resistor360. The other side of external resistor360is coupled to ground.

The circuitry ofFIG. 3is used to generate two voltages, i.e., voltage gain output355and voltage offset output370. The value of external reference voltage305and external master resistor335control the current flowing through external resistor335, and in turn control the current that is mirrored by current mirror320. The same current flowing through external resistors350and360will create known voltage drops and thereby set the value of voltage gain output355and voltage offset voltage360. Since the voltage offset may be set to a negative value, the current must be mirrored through a second current mirror375and referenced to a negative voltage. Thus the gain and offset are determined by the ratios of the external precision resistors335,350and360. Typically these resistors are 0.1% precision resistors, but other values of precision may be used. In order to adjust the output of the circuitry shown inFIG. 3, the external resistors must be manually modified.

The gain and offset outputs355and370are coupled to a voltage output DAC, such as that shown in FIG.1. In the case that a group of voltage output DACs are all being supported by the circuitry ofFIG. 3, voltage gain output355and voltage offset output370would be coupled to all DACs in the group. In the case that multiple groups of voltage output DACs are present, only a portion of the circuitry shown inFIG. 3need be replicated. Particularly, there need only be a single master amplifier310, master resistor pad325and external master resistor335. Current mirrors320and375would be expanded to incorporate additional current outputs such that one pair of external resistors350and360, and one pair of outputs335and370are present for each group of DACs to be supported.

FIG. 4illustrates prior art circuitry in which an external resistor is used to set the gain for a group of current output DACs. Externally supplied reference voltage Vref405is coupled to the negative input of current gain amplifier410. Current gain amplifier410output415is coupled to four-transistor current mirror420, which creates two matching currents. One end of current mirror420is coupled to source voltage supply VDD and the two current outputs are coupled to current gain resistor pad425and current gain output440, respectively. Current gain resistor pad425is also coupled to the positive input of current gain amplifier410and to one side of external resistor435. The other side of external resistor435is coupled to ground.

The circuitry ofFIG. 4is used to generate a current gain output current440. The value of external reference voltage405and external current gain resistor435control the current flowing through external resistor435, and in turn control the current that is mirrored by current mirror420and supplied to current gain output440. Thus, external precision resistor435determines the gain. In order to adjust the output of the circuitry shown inFIG. 4, the external resistor must be manually modified.

The gain output440is coupled to a current output DAC, such as that shown in FIG.2. In the case that a group of current output DACs is supported by the circuitry ofFIG. 4, a individual current gain output would be needed for each DAC in the group. Current mirror420would be expanded to incorporate additional current outputs, i.e., one for each DAC. In the case that multiple groups of current output DACs are present, all of the circuitry shown inFIG. 4would be replicated for each group.

FIG. 5illustrates an embodiment of the present invention in which a single CSdac is used to generate both voltage and current outputs. CSdac510accepts digital input580, voltage gain input570, voltage offset input560, current gain input575, current offset input565, and mode input505, and generates outputs515and520proportional to the binary value present on digital input580. Output515is coupled to the negative input of voltage amplifier530and to one side of feedback resistor525. The positive input of voltage amplifier530is coupled to ground and the other side of feedback resistor525is coupled to the output of voltage amplifier530. The output of voltage amplifier530is also coupled to voltage output pad535. Output520is coupled to the negative input of current amplifier545and to one side of feedback resistor540. The other side of feedback resistor540is coupled to the output of current amplifier545and to another feedback resistor550. The positive input of current amplifier545is coupled to output pad555and to the other side of feedback resistor550.

The circuitry ofFIG. 5can operate in either a voltage mode or a current mode, as controlled by mode input505. Mode input505may originate from an external pin, by a bit stored in an internal register, or by some other mechanism that generates a control signal. If the voltage mode is selected, the voltage gain input570and voltage offset input560are converted inside CSdac510into a current output515. Output515is then converted by voltage amplifier530to a voltage that is provided on voltage output pad535. If the current mode is selected, the current gain input575and the current offset input565are converted inside CSdac510into a current output520. Output520is then amplified by current amplifier545to provide a current on current output pad555. The four gain and offset inputs570,560,575and565to CSdac510are generated by the circuitry illustrated inFIGS. 6 and 7.

FIG. 6illustrates an embodiment of circuitry that generates the voltage gain and current gain inputs to the circuitry of FIG.5. The group gain is set using a digital input value rather than through the use of external resistors as in the prior art. Digital input660is used by CSdac610to produce a current output615that is linearly proportional to the input value. Current gain input650and voltage gain input655are used to set the gain of CSdac610, depending on mode input665. CSdac output615is coupled to six-transistor current mirror620, which creates three matching currents. One end of current mirror620is coupled to source voltage supply VDD and the three current outputs are coupled to CSdac output615, current gain output630and conductor625, respectively. Conductor625is coupled to four-transistor current mirror635, which creates two matching currents. One end of current mirror635is coupled to source voltage supply VSS and the two current outputs are coupled to conductor625and to voltage gain output640, respectively. Voltage gain output640is also coupled to one side of internal resistor645. The other side of internal resistor645is coupled to ground.

The circuitry ofFIG. 6is used to generate voltage gain output voltage640and current gain output current630. The current input from voltage gain input655, the value of digital input value660and the value of internal resistor645control the voltage output on voltage gain output640. The current input from current gain input650and the value of digital input value660control the current output on current gain output630. The gain inputs655and650are generated by the circuitry illustrated inFIGS. 8 and 9, discussed below.

The voltage and current gain outputs640and630are coupled to a voltage and current output DAC, such as that shown in FIG.5. In the case that a group of voltage and current output DACs are all being supported by the circuitry ofFIG. 6, voltage gain output640would be coupled to all DACs in the group. Additionally, an individual current gain output would be needed for each DAC in the group. Current mirror620would be expanded to incorporate additional current outputs, i.e., one for each DAC. In the case that multiple groups of voltage and current output DACs are present, all of the circuitry shown inFIG. 6would be replicated for each group. Digital input660is illustrated as a 13-bit digital input, but if lower resolution is required for gain adjustment, a smaller size input could be used, thereby reducing power and chip area.

FIG. 7illustrates an embodiment of circuitry that generates the voltage offset and current offset inputs to the circuitry of FIG.5. The offset is set using a digital input value rather than through the use of external resistors as in the prior art. Digital input770is used by CSdac710to produce a current output715that is linearly proportional to the input value. Current offset input760and voltage offset input765are used to set the gain of CSdac710, depending on mode input775. CSdac output715is coupled to six-transistor current mirror720, which creates three matching currents. One end of current mirror720is coupled to source voltage supply VDD and the three current outputs are coupled to CSdac output715, voltage offset output725, and conductor745, respectively. Voltage offset output725is also coupled to one end of internal resistor730. The other end of internal resistor730is coupled to ground. Conductor745is coupled to current offset output750and to conductor755. Conductor755is coupled to four-transistor current mirror740, which creates two matching currents. One end of current mirror740is coupled to source voltage supply VSS and the two current outputs are coupled to conductor755and to master current input735.

The circuitry ofFIG. 7is used to generate voltage offset output voltage725and current gain output current750. The current input from voltage offset input765, the value of digital input value770and the value of internal resistor730control the voltage output on voltage offset output725. The current input from current offset input760, the value of digital input value770, and the current input from master current input735control the current output on current offset output750. The offset inputs765and760and the master current input735are generated by the circuitry illustrated inFIGS. 8 and 9, discussed below.

The voltage and current offset outputs725and750are coupled to a voltage and current output DAC, such as that shown in FIG.5. In the case that a group of voltage and current output DACs are all being supported by the circuitry ofFIG. 7, voltage offset output725would be coupled to all DACs in the group. Additionally, an individual current offset output would be needed for each DAC in the group. Current mirrors720and740would both be expanded to incorporate additional current outputs, i.e., one for each DAC. In the case that multiple groups of voltage and current output DACs are present, all of the circuitry shown inFIG. 7would be replicated for each group. Digital input770is illustrated as a 13-bit digital input, but if lower resolution is required for offset adjustment, a smaller size input could be used, thereby reducing power and chip area.

FIG. 8illustrates an embodiment of circuitry that generates the current gain and current offset inputs to the circuitry ofFIGS. 6 and 7. An external resistor is used to create a master current adjusted to the voltage reference input. Externally supplied reference voltage850is coupled to the negative input of amplifier810. Amplifier810output815is coupled to eight-transistor current mirror820, which creates four matching currents. One end of current mirror820is coupled to source voltage supply VDD and the four current outputs are coupled to master resistor pad840, master current output835, current gain output830and current offset output825, respectively. Master resistor pad840is also coupled to the positive input of amplifier810and to one side of external resistor845. The other side of external resistor845is coupled to ground.

The circuitry ofFIG. 8is used to generate three currents to be used by the circuitry inFIGS. 6 and 7, which is in turn used to control the gain and offset of a group of current output DACs. The external resistor845, preferably a 0.1% precision resistor, and the external voltage850are used to set the ideal current reference for the chip. Mirrored versions of this current are output by the circuitry in FIG.8. In the case that multiple groups of current output DACs are all being supported by the circuitry ofFIG. 8, separate current outputs would be needed for each group. Current mirror820would be expanded to provide three current outputs for each group of DACs.

Since the current gain output current830is created with externally set parameters (i.e. external reference voltage850and external master resistor845), the error from the digital input660ofFIG. 6to the current gain output630is minimized. Similarly, since current offset current825is created the same way, the error from the digital input770ofFIG. 7to the current offset output750is minimized. Master current output835is an accurate negative offset provided to the master current input735of FIG.7. Master current input735is mirrored onto conductor755and is then summed with the current provided on conductor745, which is a current linearly varying with the digital input code770. The summed current, current offset output750, is provided to the current output DACs. The use of a negative master current input735allows the current offset output750to be adjusted both positive and negative to eliminate circuit offset errors.

FIG. 9illustrates an embodiment of circuitry that generates the voltage gain and voltage offset inputs to the circuitry ofFIGS. 6 and 7. An internal resistor is used to create reference currents. Externally supplied reference voltage940is coupled to the negative input of amplifier910. Amplifier910output915is coupled to six-transistor current mirror920, which creates three matching currents. One end of current mirror920is coupled to source voltage supply VDD and the three current outputs are coupled to the positive input of amplifier910, voltage gain output930, and voltage offset output925, respectively. The positive input of amplifier910is also coupled to one end of internal resistor935. The other end of internal resistor935is coupled to ground.

The circuitry ofFIG. 9is used to generate two currents to be used by the circuitry inFIGS. 6 and 7, which is in turn used to control the gain and offset of a group of voltage output DACs. Internal resistor935is ratiometrically matched to internal resistor645in FIG.6and internal resistor730in FIG.7. In the case that multiple groups of voltage output DACs are all being supported by the circuity ofFIG. 9, separate current outputs would be needed for each group. Current mirror920would be expanded to provide two current outputs for each group of DACs.

Since the voltage gain output current930is created with an externally set parameter (i.e., external reference voltage940) and since internal resistor935is ratiometrically matched to internal resistor645onFIG. 6, the error from the digital input value660onFIG. 6to the voltage gain output voltage640is minimized. Similarly, since voltage offset current925is created in the same way, and since internal resistor935is also ratiometrically matched to internal resistor730onFIG. 7, the error from digital input value770onFIG. 7to voltage offset output725is minimized.

FIG. 10illustrates an alternative embodiment of the circuitry shown inFIGS. 6 and 7in which two digital inputs are used to drive the gain adjustment DAC and/or the offset adjustment DAC. Error register1050accepts digital input1060and provides its output to adder1080. Input register1060accepts digital input1070and also provides its output to adder1080. Adder1080adds both of its digital inputs and provides the summed input to CSdac1010. The output of adder1080acts in a similar manner to digital input660on FIG.6and digital input770in FIG.7. Current input1030, voltage input1040and mode input1090are analogous to the three inputs650,655and665inFIGS. 6 and 760,765and775in FIG.7. CSdac output1020is coupled to the remaining circuitry ofFIG. 6or FIG.7.

The use of two registers to drive the group gain or group offset CSdac can be used to make fine adjustments to calibrate for circuit error. Circuit error consists of a chip component as well as a system component and error register1050can be configured to calibrate for either or both. By configuring error register1050with a circuit error adjustment, the ideal digital input code, loaded into register1070, will create an ideal analog gain or offset adjustment. Error register1050can be a dynamically loadable register, a combination of static storage elements, or a combination of the two. In some embodiments, error register1050would be factory calibrated during test by blowing fuses or configuring electrically alterable memory cells. In some embodiments the error register could be invisible to the customer and not loadable by the customer. In other embodiments, a factory calibration would be a default power-up value and the customer could override it by loading a new digital code into error register1050after power-up. There could also be an additional input to adder1080to accommodate both factory and system error adjustments. Providing both types of error adjustments allows maximum flexibility for the customer to calibrate the error out of their system and load the ideal digital input code into register1070.

In alternative embodiments, if both voltage and current mode need not be supported, the circuitry shown inFIG. 5could be used with only one of the two sets of inputs and with no mode input. Additionally, the support circuitry ofFIGS. 6 and 7would need support only one of the two types of outputs, and only one of the circuitry ofFIGS. 8 and 9need be provided.

In some embodiments it may be desirable to have voltage output DACs and current output DACs simultaneously enabled in the same group. In this case, different CSdacs would be used to generate the voltage gain and offset and the current gain and offset. In some embodiments, for a given group of DACs, it may be necessary to support adjustment of only gain and not offset, or only offset and not gain. In this case, the circuitry ofFIGS. 5-9could be simplified to provide only the outputs necessary.

One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purpose of illustration and not of limitation.