Solid-state image pickup device with particular pixel arrangement

In a solid-state image pickup device according to this invention, because a photodiode 2 has a side close to a transfer transistor 3 is longer than an opposite side of the photodiode 2, the transfer transistor 3 can be increased in width. Therefore, it is possible to miniaturize the size of a pixel without causing deterioration in reading property. As a result, this invention can provide the solid-state image pickup device that achieves further miniaturization of pixels by applying an efficient layout of the pixels.

TECHNICAL FIELD

The present invention relates to a solid-state image pickup device, and particularly relates to a solid-state image pickup device in which an amplifier transistor and a reset transistor are shared by a plurality of pixels.

BACKGROUND ART

There have been widely used video cameras and electronic cameras in recent years. These cameras include solid-state image sensors such as CMOS image sensors. The solid-state image sensors each include an imaging block in which a plurality of photoelectric conversion blocks each configured by a photodiode are disposed in a two-dimensional array, and there are formed unit regions (unit pixels) each including the photodiode as a main functional part.

FIG. 12is an explanatory diagram, exemplarily showing the configuration of an imaging block in a conventional CMOS image sensor and an equivalent circuit for one unit pixel. In the CMOS image sensor shown inFIG. 12, each unit pixel100includes a photoelectric conversion block configured by a photodiode102and three MOS transistors103,105, and107each of which converts signal charges into voltage signals to output the voltage signal (see Patent Document 1, for example).

Upon receiving light beams, signal charges (electrons) accumulated in the photodiode102are transferred to a floating diffusion (FD) block104through the electric charge transfer transistor103in accordance with readout pulses that are applied from a readout signal line109to a gate electrode of the electric charge transfer transistor103. The FD block104is connected to a gate electrode of the amplifier transistor105, and a variation in electric potential of the FD block104caused by the signal charges (electrons) is impedance-converted by the amplifier transistor105and is then outputted to a vertical signal line15. The reset transistor107resets the electric potential of the FD block104so as to be equal to the electric potential of a power supply line108in accordance with a vertical reset pulse that is applied from a vertical reset line14to a gate electrode thereof.

The unit pixels100are scanned as follows, one time each in one cycle by a vertical shift register11as well as by a horizontal shift register12. More specifically, when pulses are supplied from the vertical shift register11to one reset line14during a constant period of time in one cycle, the reset transistor107connected to the reset line is turned ON to cause the floating diffusion block104to be set to a high potential and to be selected. When there are selected pixels in a row corresponding to this reset line14by this operation, signals outputted from the respective pixels are transmitted to the corresponding vertical signal lines15. During this constant period of time, horizontal select pulses are sequentially outputted from the horizontal shift register12to respective horizontal select lines17, and signals outputted from the corresponding vertical signal lines15are sequentially extracted to horizontal signal lines18through horizontal select transistors16, respectively. Upon completing the scanning of all the pixels in the same row, vertical select pulses are supplied to the reset line14in the following row so as to scan the respective pixels in this following row in the manner similar to the above. These operations are repeated to scan all the pixels in all the rows one time each during one cycle, and output signals thereof are extracted to the horizontal signal lines18in a time-series manner.

In recent years, there has been growing requirement for reduction in size of a solid-state image sensor for the purpose of adding camera functions to mobile apparatuses such as mobile phones. Such reduction in size of the solid-state image sensor as well as reduction in size of unit pixels for the purpose of increase in the number of pixels lead to reduction in light receiving area in one unit pixel, which deteriorates the properties of the solid-state image sensor such as the quantity of saturation signals and sensitivity.

In order to prevent such deterioration in property, there have been conventionally proposed a method of sharing photodiodes to reduce the number of transistors per unit pixel, as well as breakthroughs by optimization of the sharing method and the like (see Patent Document 2, for example).

However, since these are merely conceptual propositions, it has been difficult to preferably maintain the properties of the solid-state image sensor only by such methods.

PRIOR ART DOCUMENTS

Patent Documents

SUMMARY OF THE INVENTION

Problem to be Solved by the Invention

The present invention has been made in view of the above circumstances, and an object thereof is to provide a solid-state image pickup device that achieves an efficient layout of pixels for further miniaturization of the pixels.

Solutions to the Problem

According to the present invention, there is provided a first solid-state image pickup device including on a semiconductor substrate: a plurality of photodiodes that are disposed in a matrix (i, j) to convert light beams into signal charges and accumulate the signal charges; an electric charge transfer transistor for reading out the signal charges accumulated in the photodiodes; a floating diffusion for converting into electric potentials the signal charges that are photoelectrically converted by the photodiodes and are read out by the electric charge transfer transistor; a reset transistor for resetting the signal charges; and an amplifier transistor for amplifying the read out signal charges, the reset transistor and the amplifier transistor being shared by the plurality of photodiodes, a distance d1between a center of gravity of a region for sensing the light beams in a photodiode (i, j) and a center of gravity of a region for sensing the light beams in a photodiode (i, j+1) being different from a distance d2between a center of gravity of a region for sensing the light beams in a photodiode (i+1, j) and a center of gravity of a region for sensing the light beams in a photodiode (i+1, j+1), and a distance d3between the center of gravity of the region for sensing the light beams in the photodiode (i, j+1) and a center of gravity of a region for sensing the light beams in a photodiode (i, j+2) being equal to the distance d2, wherein each of the photodiodes has a side close to the transfer transistor is longer than a side opposite thereto.

According to the present invention, there is provided a second solid-state image pickup device including on a semiconductor substrate: a plurality of photodiodes that are disposed in a matrix (i, j) to convert light beams into signal charges and accumulate the signal charges; an electric charge transfer transistor for reading out the signal charges accumulated in the photodiodes; a floating diffusion for converting into electric potentials the signal charges that are photoelectrically converted by the photodiodes and are read out by the electric charge transfer transistor; a reset transistor for resetting the signal charges; and an amplifier transistor for amplifying the read out signal charges, the reset transistor and the amplifier transistor being shared by the plurality of photodiodes, a distance d1between a center of gravity of a region for sensing the light beams in a photodiode (i, j) and a center of gravity of a region for sensing the light beams in a photodiode (i, j+1) being different from a distance d2between a center of gravity of a region for sensing the light beams in a photodiode (i+1, j) and a center of gravity of a region for sensing the light beams in a photodiode (i+1, j+1), and a distance d3between a center of gravity of the region for sensing the light beams in the photodiode (i, j+1) and a center of gravity of a region for sensing the light beams in a photodiode (i, j+2) being equal to the distance d2, wherein each of the photodiodes has a side close to the transfer transistor being longer than a side opposite thereto, and each of the photodiodes is axisymmetrical in one of an i direction and a j direction with respect to a center of gravity of an area of the photodiode, and is not axisymmetrical in the remaining direction.

EFFECTS OF THE INVENTION

According to the present invention, there is provided a solid-state image pickup device that has an efficient layout of pixels for achieving further miniaturization of the pixels as well as causes no residual image.

DESCRIPTION OF SYMBOLS

Described in detail below are embodiments of the present invention shown in the drawings.

First Embodiment

FIG. 1is a diagram best illustrating the feature of the first embodiment, schematically showing the configuration of a layout of pixels.

FIG. 1shows unit pixels10of 16 pixels in total arranged to have four pixels in columns i, i+1, i+2, and i+3 in the row direction and four pixels in rows j, j+1, j+2, and j+3 in the column direction, and photodiodes2for performing photoelectric conversion are disposed in the respective pixels. Each of the unit pixels10is defined as a region on a substrate, which includes one photodiode block as a main functional part as well as parts necessary to achieve the function. Each of the photodiodes2is denoted by symbols B, R, Gr, or Gb. More specifically, the photodiode B is provided with a color filter for blue color so as to photoelectrically convert blue color. Similarly, the photodiode R photoelectrically converts red color, and the photodiodes Gr and Gb photoelectrically convert green color. Symbol Gr indicates that a corresponding photodiode is disposed next to a photodiode R, and symbol Gb indicates that a corresponding photodiode is disposed next to a photodiode B.

InFIG. 1, the four photodiodes2share a reset transistor7and an amplifier transistor5. In the column i, transfer transistors3are disposed between the photodiodes2in the row j and the row j+1 to each perform the transfer operation from the corresponding photodiode2to a floating diffusion4a. Further, a reset transistor7is disposed with an element isolation being interposed between the floating diffusion4aand the reset transistor7. In the column i+1, transfer transistors3are disposed between the photodiodes2in the row j+1 and the row j+2 to each perform the transfer operation from the corresponding photodiode2to a floating diffusion4b. Further, an amplifier transistor5is disposed with an element isolation being interposed between the floating diffusion4band the amplifier transistor5.

A group of unit pixels in which the four photodiodes2share the reset transistor7and the amplifier transistor5is referred to as a cell51, which is called as a four-pixel-one-cell because one cell is generally configured by four pixels.

The present embodiment is mainly characterized by the optimization of the layout of the photodiodes2, as well as is characterized in that a side31of a photodiode adjacent to a transfer transistor3is longer than an opposite side32of the photodiode. The effects of the present embodiment will be detailed later.

Described next is a circuit configuration of an image pickup device in which photodiodes are shared in four pixels.FIG. 2is an explanatory diagram exemplarily showing the configuration of an imaging block in a conventional CMOS image sensor in which the amplifier transistor5and the reset transistor7are shared in four pixels, as well as an equivalent circuit for the four shared pixels.

FIG. 12is a circuit diagram in which photodiodes are not shared, and shows a circuit configuration different from that ofFIG. 2only in the following two points (1) and (2): (1) there are provided four photodiodes2; and (2) there are provided four transfer transistors3in shared pixels101.

The basic operations are performed as follows. Upon receiving light beams, signal charges (electrons) accumulated in the photodiode2are transferred to a floating diffusion4through one of the four transfer transistors3in accordance with readout pulses that are applied to a gate electrode of the transfer transistor3. The floating diffusion4is connected to a gate electrode of the amplifier transistor5, and a variation in electric potential of the floating diffusion4caused by the signal charges (electrons) is impedance-converted by the amplifier transistor5and is then outputted to a vertical signal line15. The reset transistor7resets the electric potential of the floating diffusion4so as to be equal to the electric potential of a power supply line8in accordance with a vertical reset pulse that is applied from a vertical reset line14to a gate electrode thereof.

The shared pixels101are scanned by a vertical shift register11and a horizontal shift register12in the following manner. When pulses are applied from the vertical shift register11to the transfer transistors3for the photodiodes2to be read and an electric potential corresponding to the quantity of the electric charges transferred to the floating diffusion4is applied to the gate portion of the amplifier transistor5, output signals of the pixels are transmitted respectively to the vertical signal lines15. Horizontal select pulses are sequentially outputted from the horizontal shift register12to respective horizontal select lines17, and the corresponding output signals are sequentially extracted to horizontal signal lines18. Upon the completion of the series of operations, the operations of reading out the electric charge of the following photodiode are started. The subsequent operations are similarly performed, and upon the completion of the operations of reading out the four photodiodes, the photodiodes in the next row are subsequently read out.

FIG. 3is a diagram conceptually showing the arrangement of pixels as described in Patent Document 2, andFIG. 4is an enlarged diagram showing a portion11ofFIG. 3.

The size of a unit pixel is defined by the distance between a photodiode and a photodiode adjacent thereto, and the pixel size is denoted by an arrow21. The pixel sizes are variously determined in accordance with the trends and applications of the image sensors. The pixels for mobile phones and digital cameras are required to be miniaturized in size, and are generally made to be 2 μm or less. In the arrangement of pixels shown inFIG. 4, the pixel size is equal to a sum of a width22of the photodiode2and a width23of an element isolation between the adjacent photodiodes. The larger photodiode has an area for receiving light beams and thereby to achieve an image sensor of high performance. However, there is a restriction to the width23of an element isolation (such as STI: Shallow Trench Isolation) by the requirement on the pixel size or by the design rule. Accordingly, in a case where a cell has the pixel size21equal to 1.75 μm and the minimum width23of the element isolation defined by the design rule is 0.25 μm, the photodiode has the width22equal to 1.5 μm.

The pixel size also restricts the horizontal width of the floating diffusion4inFIG. 4. A width24of the floating diffusion4corresponds to a width of a channel of the transfer transistor3. If this channel width is reduced, the reading property of the transfer transistor3is deteriorated. Accordingly, this channel width is generally set to approximately 0.5 μm. A width25of the element isolation between the floating diffusion4and the reset transistor7is restricted by the design rule, and is set to 0.25 μm in this case. A width26of the reset transistor region is also restricted by the design rule, and is set to 0.9 μm in this case. A width27of the element isolation for isolating the reset transistor region26and the photodiode2adjacent thereto is also restricted by the design rule, and is set to 0.25 μm in this case. The design rule to be referred to herein corresponds to the CMOS logic 0.13 μm rule. The total sum of the numerical values recited above is equal to 1.9 μm. This design rule allows the miniaturization only down to 1.9 μm. In order to realize the pixel size of 1.75 μm, the channel width of the transfer transistor3needs to be reduced, that is, the width24of the floating diffusion needs to be reduced and thus the reading property thereof should be deteriorated. It is therefore difficult to achieve the pixel size of 1.75 μm in any case.

The present embodiment proposes the optimum layout of the photodiodes, in which the reading property is not deteriorated and the pixel size of 1.75 μm is achieved under the similar design rule.

FIG. 5is a schematic diagram according to the present embodiment. In this diagram, the photodiode is denoted by symbol2, the transfer transistor is denoted by symbol3, the floating diffusion is denoted by symbols4aor4b, the reset transistor is denoted by symbol7, the amplifier transistor is denoted by symbol5, the pixel size is denoted by symbol21, the width of the photodiode is denoted by symbol22, the width of the element isolation between the adjacent photodiodes is denoted by symbol23, the width of the floating diffusion is denoted by symbol24, the width of the element isolation between the floating diffusion and the reset transistor region is denoted by symbol25, the width of the reset transistor region is denoted by symbol26, the width of the element isolation between the reset transistor and the photodiode is denoted by symbol27, and a reduced portion of the photodiode is denoted by symbol28, respectively.

Described next is the relative positions of the respective specific elements. The transfer transistor3is disposed close to the larger width of the photodiode. The floating diffusion4ais disposed between the transfer transistors3adjacent to the upper and lower photodiodes, respectively. InFIG. 5, the sides of the photodiodes2each close to the corresponding transfer transistor are aligned in parallel with each other in the row direction. In this state, similarly to the ordinary layout described with reference toFIG. 4, the sides of the photodiodes2aligned in parallel with each other in the row direction are perpendicular to the sides of the photodiodes2in parallel with each other in the column direction.

While the photodiodes2illustrated inFIG. 4each have a rectangular shape, the photodiodes2illustrated inFIG. 5each have a polygonal shape. As shown inFIG. 5, the reduced portion28of the photodiode is formed by two vertices. This configuration enhances the flexibility in the layout of the width24of the floating diffusion4and the width of the transfer transistor. Therefore, it is possible to realize a cell of 1.75 μm even under the design rule applied to the case shown inFIG. 4.

As described with reference toFIG. 4, the width of 1.9 μm is required from the floating diffusion4to the element isolation27. In the case where the pixel size needs to be equal to 1.75 μm, the difference therebetween of 0.15 μm needs to be reduced by the photodiode formed into the polygonal shape. The length of the reduction can be divided and added to the photodiodes located on the both sides thereof. The length of the reduced portion28of the photodiode is therefore equal to 0.075 μm.

FIG. 1is an overview diagram showing pixels arranged in four rows and in four columns illustrated inFIG. 5. As apparent from this diagram, the photodiode2has the width31close to the transfer transistor3, which is larger than the width32of the opposite side thereof.

FIG. 6shows active regions29in the transfer transistors so as to clarify channel widths30of the transfer transistors shown inFIG. 5. In the case where the active region in the transfer transistor3is formed obliquely, the floating diffusion4can be displaced to achieve the miniaturization of the pixels under the restrictions of the design rule and the reading property.

FIGS. 13 and 14are diagrams each conceptually showing the effects of the layout according to the present embodiment, in which the photodiode, the transfer transistor, and the floating diffusion are denoted by symbols2,3, and4, respectively.

InFIG. 13, a potential deep portion of the photodiode is denoted by symbol33, which is determined by the ion implantation and the heat treatment in the manufacturing process as well as by the layout of pixels.FIG. 13shows an ordinary layout, in which the photodiodes2each have a rectangular shape. In this case, the potential deep portion33of each of the photodiodes is located substantially at the center of gravity of the photodiode2.

FIG. 14shows the layout according to the present embodiment. The potential deep portion33of the photodiode is shifted toward the transfer transistor3in accordance with the layout of pixels. Because the transfer transistor3and the potential deep portion33of the photodiode is close to each other, there is an exerted effect of perfect transfer. There is another exerted effect of the present embodiment that the layout can help such perfect transfer, which is hard to be achieved by the miniaturization of the cells.

Because the length of the reduction is divided and added to the photodiodes located on the both sides thereof, the shape of the photodiodes is made horizontally symmetrical with respect to the center of gravity of the photodiode. Therefore, the efficiency of light beams incident on the photodiode from the right and the efficiency of light beams incident on the photodiode from the left are equal to each other, which is also one of the features of the present embodiment.

Each of the photodiodes is vertically asymmetrical with respect to the center of gravity of the photodiode. However, the photodiodes in an identical color, such as the photodiodes R, B, or G have an identical shape, so as to easily realize correction by signal processing or the like.

As shown inFIG. 7, the CMOS image sensor provided with a select transistor6also exerts the technical effects similar to those exerted in the case where any select transistor is not provided.

Described above is the image sensor in which four photodiodes share the reset transistor and the amplifier transistor. The technical effects similar to those of the present embodiment will be exerted even in an image sensor of the type shown inFIG. 8in which two photodiodes2share the reset transistor7, the amplifier transistor5, and the select transistor6.

Even in a case where the element isolation24or27described with reference toFIG. 4in relation toFIG. 7is replaced with implant isolation achieved by implantation, the technical effects thereof are exerted similarly to those of the present embodiment.

This embodiment of the present invention realizes the pixel size of 1.75 μm or less even under the process rule of 0.13 μM while achieving the satisfactory reading property.

Second Embodiment

A second embodiment of the present invention is described in the following.

FIG. 9is a diagram showing a layout of pixels in a case of reducing the number of vertices of each photodiode in the polygonal shape according to the present embodiment.FIG. 9is conceptually the same asFIG. 5, and is different fromFIG. 5in the shape of the photodiode.

The photodiode is denoted by symbol2, the transfer transistor is denoted by symbol3, the floating diffusion is denoted by symbol4aor4b, the reset transistor is denoted by symbol7, the amplifier transistor is denoted by symbol5, the pixel size is denoted by symbol21, the width of the photodiode is denoted by symbol22, the width of the element isolation between the adjacent photodiodes is denoted by symbol23, the width of the floating diffusion is denoted by symbol24, the width of the element isolation between the floating diffusion and the reset transistor region is denoted by symbol25, the width of the reset transistor region is denoted by symbol26, the width of the element isolation between the reset transistor and the photodiode is denoted by symbol27, and the reduced portion of the photodiode is denoted by symbol28, respectively.

Described next is the relative positions of the respective specific elements. The transfer transistor3is disposed close to the larger width of the photodiode. The floating diffusion4ais disposed between the transfer transistors3adjacent to the upper and lower photodiodes, respectively. InFIG. 9, the sides of the photodiodes2each close to the corresponding transfer transistor3are aligned in parallel with each other in the row direction. In this state, similarly to the ordinary layout described with reference toFIG. 4, the sides of the photodiodes2aligned in parallel with each other in the row direction are perpendicular to the sides of the photodiodes2in parallel with each other in the column direction.

InFIG. 5, the reduced portion28of the photodiode is formed by the two vertices. To the contrary, the reduced portion28of the photodiode shown inFIG. 9is formed only by one vertex. Similarly to the first embodiment, in the second embodiment, in a case where the total sum of the width24of the floating diffusion, the width25of the element isolation between the floating diffusion and the reset transistor region, the width26of the reset transistor region, and the width27of the element isolation between the reset transistor and the photodiode is larger than the pixel size, there is the reduced portion provided to the photodiode in order to realize the pixel size. In this case, the photodiode2shown inFIG. 9has an area larger than that of the photodiode shown inFIG. 6, which is advantageous in view of the saturation property.

As shown inFIG. 10, in a case of applying the design rule under which the reset transistor region7can be cut obliquely, this second embodiment is effectively adopted. More specifically, in a case where the width of the element isolation between the region of the reset transistor7and the photodiode is smaller than the size approved by the design rule, as in such a manner shown inFIG. 10, the active region for disposing the reset transistor or the amplifier transistor has sides respectively in parallel with the adjacent active regions. This configuration achieves the optimum layout with no deterioration in saturation property due to the reduction in size of the photodiode2.

FIG. 11is an overview diagram showing pixels aligned in four rows and in four columns illustrated inFIG. 9. The width31of the photodiode2close to the transfer transistor3is made larger than the width32of the opposite side thereof. This configuration realizes the miniaturization of the pixel size even under the restriction of the design rule.

This embodiment of the present invention realizes the pixel size of 1.75 μm or less even under the process rule of 0.13 μm while achieving the satisfactory reading property.

Industrial Applicability

The solid-state image sensor, the manufacturing method therefor, and the solid-state image pickup device according to the present invention are applied to CMOS image sensors, electronic cameras, and the like, and contribute to reduction in size, increase in the number of pixels, and prevention of deteriorations of the imaging properties such as decrease in saturation signal amount and deterioration in sensibility. Moreover, the solid-state image pickup device according to the present invention may be widely utilized in cameras or camera systems for digital still cameras, mobile cameras, cameras for medical use, vehicle cameras, video cameras, monitoring cameras, security cameras, and the like, which concern high image quality.