CELL BALANCING USING AN EXTERNAL POWER SOURCE

Described examples include a system having a power source having a first output terminal and a second output terminal and a controller. The system also has a selective charger coupled to the controller, the selective charger configured to couple, in response to instructions from the controller, the first output terminal of the power source to a first node that is configured to be coupled to a first terminal of a selected battery cell of two or more serially coupled battery cells, and couple the second output terminal of the power source to a second node configured to be coupled to a second battery terminal of the selected battery cell.

TECHNICAL FIELD

This relates generally to battery technology, and more particularly to recharging batteries.

BACKGROUND

To use rechargeable batteries, such as lithium-ion cells, for high power applications, such as electric vehicles, the cells of the battery array must be at least partially arranged in series. Lithium-based batteries have a voltage of 3 to 4 volts, depending on the chemistry used in the cell. Some applications require hundreds of volts. Thus, many lithium-based battery cells are placed in series to provide the required voltage. However, due to heating, jostling, or other physical or chemical effects, a particular cell in a series of cells may discharge faster or slower than the others. When any cell in the series is depleted, the series can no longer provide power. In addition, recharging must stop when any cell in the series has reached its maximum capacity due, in part, to the dangers of overcharging. Therefore, to maximize charging of a series, and to maximize power extraction from the series, it is desirable to balance the charge on cells within the series.

SUMMARY

In accordance with an example, a system includes a power source having a first output terminal and a second output terminal and a controller. The system also includes a selective charger coupled to the controller, the selective charger configured to couple, in response to instructions from the controller, the first output terminal of the power source to a first node that is configured to be coupled to a first terminal of a selected battery cell of two or more serially coupled battery cells, and couple the second output terminal of the power source to a second node configured to be coupled to a second battery terminal of the selected battery cell.

DETAILED DESCRIPTION

In the drawings, corresponding numerals and symbols generally refer to corresponding parts unless otherwise indicated. The drawings are not necessarily drawn to scale.

FIG.1is a schematic diagram of an example battery pack100. Battery cells102-0through102-N are coupled in series to provide a voltage N times the voltage of a single battery cell. Each battery has two battery terminals. The shading on the batteries indicates the state of charge of that battery. In this example, battery cell102-N-2has become unbalanced with the other battery cells. Specifically, battery cell102-N-2is not fully charged while the other battery cells are fully charged. This means that, as the energy stored in battery pack100is used, battery cell102-N-2will become fully depleted before the other battery cells. One dissipated battery cell may pull the voltage of the battery pack out of its acceptable operating range. Thus, this battery pack must be recharged sooner than necessary.

FIG.2is a schematic circuit diagram of an example selective charging circuit200. Battery cells102-0through102-N are arranged in a serially coupled battery pack. Resistors204-0through204-ncouple the battery nodes between the respective battery cells to cell balancing nodes including battery nodes CB0through CBn, which provide a connection from the battery cells to integrated circuit202. In this example, n is equal to N+1, so for example, if there is one battery cell (N=1), then there will be two resistors (n=1+1). Capacitors206-0through206-N are coupled across battery cells102-0through102-N, respectively, to dissipate any spurious voltage spikes, and thus protect battery cells102-0through102-N. Diodes208-0through208-N are also coupled across battery cells102-0through102-N, respectively, to dissipate any reverse power spikes. Integrated circuit202includes transistors210-0through210-N, which are coupled across battery cells102-0through102-N, respectively, to serve as switches. The gates of transistors210-0through210-N are coupled to cell balancing control212. In this example, transistors210-0through210-N are field effect transistors, but in other examples, one or more of transistors210-0through210-N may be other types of transistors such as bipolar junction transistors.

If at least one battery cell of the battery cells102-0to102-N is overcharged relative to the other battery cells, CB control212can turn on transistors210-0through210-N that are coupled to the overcharged cell(s) to discharge the overcharge through the resistors coupled to the overcharged cells. Processor218(labeled main control unit or MCU inFIG.2) provides instructions to perform this operation through communication interface216and analog front end (AFE) digital control214. In some configurations, processor218is a separate integrated circuit. That is, processor218is formed on a separate substrate from integrated circuit202. In other configurations, cell balancing control212, AFE digital control214, communication interface216, multiplexor controller220, multiplexor222, and multiplexor224may or may not be on one or more separate integrated circuits.

Another balancing method is provided by external power source228. External power source228can be a separate battery pack, power derived from an external charging station, or power derived from one or more other sources. Power converter226is shown inFIG.2coupled to external power source228via transformer227where the input coil provides two isolator input terminals and the output coil provides two isolator output terminals. In this example, transformer227serves as a power isolator. However, this configuration is only an example. Any power conversion system that provides the proper voltage and current for charging one of battery cells102-0through102-N can be used. That is, assume battery cells102-0through102-N each comprise a 3.5 V cell. The voltage provided by power converter226would then provide a voltage that, taking into account voltage drops caused by intervening circuitry, would apply slightly more than 3.5 V to a charging cell. One output terminal from power converter226is coupled to multiplexor222via one of power input terminals225on integrated circuit202. The other output terminal from power converter226is coupled to multiplexor224via the other one of power input terminals225on integrated circuit202. Multiplexor222and multiplexor224are controlled by multiplexor controller220, which is controlled by processor218through communication interface216and AFE digital control214. As an example, assume battery cell102-N-1has a voltage lower than the other battery cells in an example battery pack comprising battery cells102-0,102-N, and102-N-1. To balance battery cell102-N-1, multiplexor222is used to couple one output lead of power converter226to charge battery node CBn-1and multiplexor224is used to couple the other output lead from power converter226to charge battery node CBn-2, thus providing charging energy to bring battery cell102-N-1in balance with the other battery cells in the example battery pack.

FIG.3are schematic circuit diagrams of example multiplexor222and example multiplexor224(FIG.2). VISOPis the positive lead from power converter226. A particular connection from VISOPto the selected cell balancing node of CBn to CB1is made by enabling one of current source308or one of current sources324-nto324-1. P field effect transistor (PFET)302and PFET304provide the coupling to battery node CBn. When current source308is on, the gates of PFET302and PFET304are pulled low and thus PFET302and PFET304are conductive or ON. Thus, current flow from VISOPto battery node CBn. The current through resistor306is limited by current source308, so most of the current goes to the charging battery. In addition, the current through resistor306provides a voltage drop that biases PFET302and PFET304. When current source308is shut off, the gates of PFET302and PFET304are pulled high by VISOPthrough resistor306, thus rendering PFET302and PFET304non-conductive or OFF.

For the selective connections to cell balancing nodes CBn-1through CB1, the respective one of current sources324-n-1through324-1are enabled. The current through current source324-x(where “x” designates one of the 1 through n−1 cell balancing nodes) is mirrored through PFET320-xto PFET322-x. This mirrored current is applied to the gates of N field effect transistor (NFET)328-xand NFET326-x, thus rendering these transistors conductive or ON. The current through resistor330-xis limited by the current through PFET322-x. The current through PFET322-xalso biases NFET328-xand326-x. When current source324-xis turned off, the gates of NFET328-xand NFET326-xare pulled to VISOP, which renders NFET328-xand NFET326-xnon-conductive or OFF.

The corresponding portions of multiplexor224operate in a similar manner. That is, PFET312operates in a similar manner to PFET304. PFET310operates in a similar manner to PFET302. Resistor314operates in a similar manner to resistor306. Current source316operates in a similar manner to current source308. Current source344-n-1through current source344-1operate in a similar manner to current source324-n-1through,324-1, respectively. PFET340-n-1through PFET340-1operate in a similar manner to current PFET320-n-1through PFET320-1, respectively. PFET342-n-1through PFET342-1operate in a similar manner to current PFET322-n-1through PFET322-1, respectively. NFET348-n-1through NFET348-1operate in a similar manner to NFET328-n-1through NFET328-1, respectively. NFET346-n-1through NFET346-1operate in a similar manner to NFET326-n-1through NFET326-1, respectively. Resistor350-n-1through resistor350-1operate in a similar manner to resistor330-n-1through resistor330-1, respectively. Of note, the selective connections coupled to battery node CBnin multiplexor222and battery node CBn-1in multiplexor224do not utilize a mirrored current source because there is not enough voltage headroom in this circuit to allow using a mirrored current source. That is, the voltages on battery node CBnand battery node CBn-1are too close to VPACK+, which is used to drive the connections to the other nodes.

FIG.4is a schematic circuit diagram of voltage monitoring for one cell102-X, where a similar circuit is provided for each of the cells102-0through102-N. Across each cell, an analog to digital converter (ADC)402is coupled between each battery node CBXand its adjacent battery node CBX-1and serve as voltage measuring devices. In another example, one ADC402or a smaller number of ADCs than the number of cells may be used and coupled by a multiplexor to the cell to be measured. The multiplexor can then rotate the coupling to the cells over a time period to measure all of the cells. The output of ADC402is a digital signal representing the voltage across cell102-X. ADC402provides this signal to processor218via communications interface216(FIG.2). The voltage on a cell drops slightly as the cell is discharged. The relationship between the voltage across the cell and the cell's state of charge is a known function. Therefore, processor218(FIG.2) can determine the state of charge of each cell by monitoring the voltage across each cell.

FIG.5is another example charge balancing circuit500. In this example, a voltage isolation circuit is provided for each battery cell102-X. Specifically, external voltage input514-X includes connections to the outside power source (VISOPand VISON) and an Enable input. In this example, transformer516-X isolates driver512-X from external voltage input514-X. External voltage input514-X, transformer516-X and driver512-X condition the power for use to charge the battery cell102-X. This is only one example and other power conditioning circuits can be used.

When external voltage input514-X is enabled, positive bias is applied to the base of transistor502-X through resistor508-X. This makes transistor502-X conductive and power flows through resistor506-x to the positive battery node of battery cell102-X, through transistor502-X, through resistor510-X back to driver512-X or to ground. If too much current is flowing, the voltage drop across resistor510-X forward biases transistor504-X, which pulls some of the bias from the base of transistor502-X. This limits the current through the cell to a selected value to avoid overheating of battery cell102-X and other damaging effects of excessive charging current. Therefore, each battery cell in charge balancing circuit500can be separately charged to provide cell balancing.

Also, in this description, the recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, then X may be a function of Y and any number of other factors.

While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a field effect transistor (“FET”) (such as an n-channel FET (NFET) or a p-channel FET (PFET)), a bipolar junction transistor (BJT—e.g., NPN transistor or PNP transistor), an insulated gate bipolar transistor (IGBT), and/or a junction field effect transistor (JFET) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

References may be made in the claims to a transistor's control input and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

References herein to a FET being “ON” or “enabled” means that the conduction channel of the FET is present and drain current may flow through the FET. References herein to a FET being “OFF” or “disabled” means that the conduction channel is not present so drain current does not flow through the FET. An “OFF” FET, however, may have current flowing through the transistor's body-diode.

Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter or, if the parameter is zero, a reasonable range of values around zero.