POWER MODULE HAVING A MULTI-LEVEL LEAD FRAME

A power module includes: a first substrate comprising a patterned first metallization; a second substrate comprising a patterned second metallization that faces the patterned first metallization; a first plurality of vertical power transistor dies having a drain pad attached to a first part of the patterned first metallization and a source pad electrically connected to a first part of the patterned second metallization; a second plurality of vertical power transistor dies having a drain pad attached to a second part of the patterned first metallization and a source pad electrically connected to a second part of the patterned second metallization; and a multi-level lead frame between the first substrate and the second substrate and attached to each of the first part of the patterned first metallization, the first part of the patterned second metallization, the second part of the patterned first metallization, and the second part of the patterned second metallization.

BACKGROUND

Power modules often have a half bridge configuration with a high-side switch and a low-side switch in the same module. Each switch is typically formed from 1 to 4 (or more) power transistor dies (chips), which results in a total of 2 to 8 (or more) dies per module, sandwiched between two die carrier substrates. In the case of SiC transistor dies for implementing the half bridge switches, SiC technology is more expensive compared to Si technology. However, SiC technology delivers higher voltage operation, wider temperature ranges, and increased switching frequencies when compared to existing Si technology. Thermal optimization is an issue with power modules, especially in the case of a fully populated power module with 8 or more SiC transistor dies. Strong thermal coupling between the SiC dies arises since the distances between the single SiC dies are relatively short. Electrically conductive vias outside the perimeter of the SiC transistor dies are typically used to provide power and signal connections between the die carrier substrates, which results in strong thermal coupling between the die carrier substrates. This means that relatively expensive SiC dies and die carrier substrates are not fully exploited with respect to thermal and electrical performance in conventional power module designs.

Hence, there is a need form an improved power module design with better thermal performance.

SUMMARY

According to an embodiment of a power module, the power module comprises: a first substrate comprising a patterned first metallization; a second substrate comprising a patterned second metallization that faces the patterned first metallization; a first plurality of vertical power transistor dies having a drain pad attached to a first part of the patterned first metallization and a source pad electrically connected to a first part of the patterned second metallization; a second plurality of vertical power transistor dies having a drain pad attached to a second part of the patterned first metallization and a source pad electrically connected to a second part of the patterned second metallization; and a lead frame between the first substrate and the second substrate, wherein the first plurality of vertical power transistor dies and the second plurality of vertical power transistor dies form a half bridge, wherein the lead frame comprises: a first lead attached to the first part of the patterned second metallization and providing a low-side current path to the half bridge; a second lead attached to the second part of the patterned first metallization and providing a high-side current path to the half bridge; and a third lead attached to both the first part of the patterned first metallization and the second part of the patterned second metallization, and providing a phase current path to the half bridge.

According to another embodiment of a power module, the power module comprises: a first substrate comprising a patterned first metallization; a second substrate comprising a patterned second metallization that faces the patterned first metallization; a first plurality of vertical power transistor dies having a drain pad attached to a first part of the patterned first metallization and a source pad electrically connected to a first part of the patterned second metallization; a second plurality of vertical power transistor dies having a drain pad attached to a second part of the patterned first metallization and a source pad electrically connected to a second part of the patterned second metallization; and a multi-level lead frame between the first substrate and the second substrate and attached to each of the first part of the patterned first metallization, the first part of the patterned second metallization, the second part of the patterned first metallization, and the second part of the patterned second metallization.

According to another embodiment of a power module, the power module comprises: a first substrate comprising a patterned first metallization; a second substrate comprising a patterned second metallization that faces the patterned first metallization; a first plurality of vertical power transistor dies forming a low-side switch of a half bridge and having a drain pad attached to a first part of the patterned first metallization and a source pad electrically connected to a first part of the patterned second metallization; a second plurality of vertical power transistor dies forming a high-side switch of the half bridge and having a drain pad attached to a second part of the patterned first metallization and a source pad electrically connected to a second part of the patterned second metallization; and a multi-level lead frame attached to both the patterned first metallization and the patterned second metallization and providing a low-side current path, a high-side current path, and a phase current path to the half bridge.

DETAILED DESCRIPTION

The embodiments described herein provide a power module design having a multi-level lead frame that attaches to both die carrier substrates included in the power module. The multi-level lead frame eliminates the need for electrically conductive vias that provide power and signal connections between the die carrier substrates. Instead, the multi-level lead frame provides the power and signal connections to both die carrier substrates. The space gained by omitting the electrically conductive vias can be used, e.g. to increase the distance between the power transistor dies included in the module, accommodate additional dies, improve the electrical (e.g., higher output current capacity) and thermal performance, simplify the assembly process, reduce module cost, etc. The power module design supports double-sided cooling where the main heat dissipation of one group of power transistor dies is through one side of the power module via one die carrier substrate and the main heat dissipation another group of vertical power transistor dies is through the opposite side of the module via the other die carrier substrate. The power module design may support single-side cooling instead of double-sided cooling.

Described next, with reference to the figures, are exemplary embodiments of the power module design and corresponding methods of production. Any of the power module embodiments described herein may be used interchangeably unless otherwise expressly stated.

FIG.1Aillustrates a plan view of an embodiment of a power module100.FIG.1Billustrates a side view of the power module100.FIGS.1C and1Dillustrate different disassembled views of the power module100. The power module100may form part of a power electronics circuit for use in various power applications such as in a DC/AC inverter, a DC/DC converter, an AC/DC converter, a DC/AC converter, an AC/AC converter, a multi-phase inverter, an H-bridge, DC motor drive, etc.

The power module100includes a first (die carrier) substrate102having a patterned first metallization104and a second (die carrier) substrate106vertically aligned with the first substrate102. The second substrate106has a patterned second metallization108that faces the patterned first metallization104of the first substrate102.FIGS.1C and1Dshow the first and second substrates102,106, respectively, with the second substrate106being flipped inFIG.1Dso that the patterned second metallization108which faces the first die carrier substrate102is visible. Both substrates102,106may have a patterned or un-patterned metallization110,112at the respective opposite side of each substrate102,106, e.g., as shown inFIGS.1A and1Bto provide double-sided cooling. One of these non-facing substrate metallizations110,112may be covered by a mold body114such that the power module100instead provides single-sided cooling.

The substrate metallizations104,108that face one another are patterned to ensure proper routing of electrical connections for implementing a power electronics device included in the power module100. Exemplary electrical connections are described in more detail later in the context of a half bridge. However, a half bridge is just one example of a power electronics device that may be included in the power module100. The substrate metallizations104,108that face one another may be patterned differently than what is illustrated in the figures, to facilitate electrical connections for any type of power electronics device included in the power module100.

The first substrate102may be a direct bonded copper (DBC) substrate, an active metal brazed (AMB) substrate, or an insulated metal (IMS) substrate, where in each case an insulating body116such as a ceramic separates the metallized sides104,110of the first substrate102from one another. The second substrate106may be a DBC substrate, an AMB substrate, or an IMS substrate, where in each case an insulating body118such as a ceramic separates the metallized sides108,112of the second substrate106from one another. The insulating body116of the second substrate106instead may be omitted such that the second substrate106includes just a patterned metallization108, e.g., such as a lead frame. The first and second substrates102,106may be the same substrate type or different substrate types. The first substrate102and the second substrate106may have identical areas or different areas. InFIGS.1C and1D, the first and second substrates102,106are shown side-by-side before the second substrate106is flipped from right to left and aligned vertically with the first substrate102.

The power module100also includes first vertical power transistor dies120and second vertical power transistor dies122. The power transistor dies120,122are ‘vertical’ dies in that the primary current flow path is between the front and back sides of each die120,122. The drain terminal is typically disposed at the die backside, with gate and source terminals (and optionally one or more sense terminals) at the die frontside. Additional types of semiconductor dies may be included in the power module100, such as power diode dies, logic dies, controller dies, gate driver dies, etc. In one embodiment, the first vertical power transistor dies120are SiC power MOSFET (metal-oxide-semiconductor field-effect transistor) dies and the second vertical power transistor dies122are also SiC power MOSFET dies. The first and second vertical power transistor dies120,122instead may be Si power MOSFET dies, HEMT (high-electron mobility transistor) dies, IGBT (insulated-gate bipolar transistor) dies, JFET (junction filed-effect transistor) dies, etc.

The first vertical power transistor dies120included in the power module100may have a drain pad (out of view) attached to a first part124of the patterned first metallization104of the first substrate102. At the opposite side, the first vertical power transistor dies120have a source pad126electrically connected to a first part128of the patterned second metallization108of the second substrate106via electrically conductive first spacers130. The first spacers130may be attached to the source pad126of the first vertical power transistor dies120by a first attach material such as solder, diffusion solder, glue, adhesive, etc. The first spacers130may be attached to the first part128of the patterned second metallization108of the second substrate106by a second attach material such as solder, diffusion solder, glue, adhesive, etc. The first and second attach materials may comprise the same material or different materials.

The second vertical power transistor dies122included in the power module100may have a drain pad (out of view) attached to a second part132of the patterned first metallization104of the first substrate102. At the opposite side, the second vertical power transistor dies122may have a source pad134electrically connected to a second part136of the patterned second metallization108of the second substrate106via electrically conductive second spacers138. The second spacers138may be attached to the source pad134of the second vertical power transistor dies122by a first attach material such as solder, diffusion solder, glue, adhesive, etc. The second spacers138may be attached to the second part136of the patterned second metallization108of the second substrate106by a second attach material such as solder, diffusion solder, glue, adhesive, etc. The first and second attach materials may comprise the same material or different materials.

The die spacers130,138may comprise, e.g., AlSiC which is an aluminum matrix with silicon carbide particles and where AlSiC exhibits very poor solder wetting. Other thermally and electrically conductive materials may be used for the spacers130,130, e.g., such as Cu, Al, etc.

The power module100also includes a multi-level lead frame140between the first and second substrates102,106. The multi-level lead frame140is attached to both the patterned first metallization104of the first substrate102and the patterned second metallization108of the second substrate106. As explained above, the first vertical power transistor dies120and the second vertical power transistor dies122may form a half bridge. For example, as schematically illustrated inFIG.2, the first vertical power transistor dies120may be electrically coupled in parallel to form a low-side switch device200of the half bridge and the second vertical power transistor dies122may be electrically coupled in parallel to form a high-side switch device202of the half bridge. The low-side and high-side switch devices200,202are schematically illustrated inFIG.2as a power MOSFET with a freewheeling diode, as an example.

In the half bridge example, the multi-level lead frame140, which is attached to both the patterned first metallization104of the first substrate102and the patterned second metallization108of the second substrate106, provides a low-side current path (DC−), a high-side current path (DC+), and a phase current path (AC) to the half bridge. The multi-level lead frame140may also provide a gate signal path (G1) for the gate pad142of each first vertical power transistor die120and a gate signal path (G2) for the gate pad144of each second vertical power transistor die122. The multi-level lead frame140may further provide a source sense path (S1) for the first vertical power transistor dies120, a source sense path (S2) for the second vertical power transistor dies122, and a drain sense path (D2) for the second vertical power transistor dies122.

Continuing with the half bridge example, the multi-level lead frame140may include a first lead146attached to the first part128of the patterned second metallization108of the second substrate106for providing the low-side current path (DC−) to the half bridge. The multi-level lead frame140may also include a second lead148attached to the second part132of the patterned first metallization104of the first substrate102for providing the high-side current path (DC+) to the half bridge. The multi-level lead frame140may further include a third lead150attached to both the first part124of the patterned first metallization104of the first substrate102and the second part136of the patterned second metallization108of the second substrate106for providing the phase current path (AC) to the half bridge.

InFIG.1C, the first vertical power transistor dies120are flanked on one side by a first subset122aof the second vertical power transistor dies122and flanked on the opposite side by a second subset122bof the second vertical power transistor dies122. According to this embodiment, the drain of each vertical power transistor die122in the first subset122ais attached to a first segment132aof the second part132of the patterned first metallization104of the first substrate102and the drain of each vertical power transistor die122in the second subset122bis attached to a second segment132bof the second part132of the patterned first metallization104of the first substrate102. The first part124of the patterned first metallization104of the first substrate102is laterally interposed between the first segment132aand the second segment132bof the second part132of the patterned first metallization104of the first substrate102.

The second lead148of the multi-level lead frame140is attached to the first segment132aof the second part132of the patterned first metallization104of the first substrate102. In this example, the multi-level lead frame140further includes a fourth lead152attached to the second segment132bof the second part132of the patterned first metallization104of the first substrate102. The second lead148of the multi-level lead frame140provides the high-side current path (DC+) to the first subset122aof the second vertical power transistor dies122and the fourth lead152of the multi-level lead frame140provides the high-side current path (DC+) to the second subset122bof the second vertical power transistor dies122.

As shown inFIGS.1C and1D, the first lead146of the multi-level lead frame140may be attached to the first part128of the patterned second metallization108of the second substrate106by solder154. The second lead148and the fourth lead152of the multi-level lead frame140may be attached to the second part132of the patterned first metallization104of the first substrate102by solder156. The third lead150of the multi-level lead frame140may be attached to both the first part124of the patterned first metallization104of the first substrate102and the second part136of the patterned second metallization108of the second substrate106by solder158.

The multi-level lead frame140may include additional leads. For example, a first gate lead160of the multi-level lead frame140may be attached to a third part162of the patterned first metallization104of the first substrate102, e.g., by solder164to provide the gate signal path (G1) for the gate pad142of each first vertical power transistor die120. A second gate lead166of the multi-level lead frame140may be attached to a fourth part168of the patterned first metallization104of the first substrate102, e.g., by solder170to provide the gate signal path (G2) for the gate pad144of each second vertical power transistor die122. The gate pad142of each first vertical power transistor die120is electrically connected to the third part162of the patterned first metallization104of the first substrate102, e.g., by one or more bond wires172. The gate pad144of each second vertical power transistor die122is electrically connected to the fourth part168of the patterned first metallization104of the first substrate102, e.g., by one or more bond wires174.

A first sense lead176of the multi-level lead frame140may be attached to the second part132of the patterned first metallization104of the first substrate102, e.g., by solder178to provide the source sense path (S1) for the first vertical power transistor dies120. A second sense lead180of the multi-level lead frame140may be attached to the first part128of the patterned second metallization108of the second substrate105, e.g., by solder182to provide the source sense path (S2) for the second vertical power transistor dies122. Two additional leads184,186of the multi-level lead frame140may be attached to respective additional parts188,190of the patterned first metallization104of the first substrate102, e.g., by solder192to electrically contact opposite terminals of a thermal sensor194such as an NTC (negative temperature coefficient) thermistor.

FIG.3illustrates a side perspective view of the first substrate102. As shown inFIG.3, the proximal (attached) end of some leads148,152,160,166,176,184,186of the multi-level lead frame140are at a first (lower) level and attached to the patterned first metallization104of the first substrate102. The proximal end of other the leads146,180of the multi-level lead frame140are at a second (upper) level and attached to the patterned second metallization108of the second substrate106which is not shown inFIG.3.

In one embodiment, the proximal (substrate attachment) end of the lead150of the multi-level lead frame140that provides the phase current path (AC) is a split end. The split end has a first part300at the lower level and attached to the first part124of the patterned first metallization104of the first substrate102. The split end also has a second part302at the upper level and attached to the second part136of the patterned second metallization108of the second substrate106. A gap304is present in the split end, between the first (lower) part300and the second (upper) part302of the phase current path lead150. The distal (external) end of the leads146,148,150,152,160,166,176,180,184,186are not embedded in the mold body114, e.g., as shown onFIGS.1A and1B, to provide points of external electrical contact to the power module100.

FIGS.4A and4Bshow a plan view of the first (FIG.4A) and second (FIG.4B) substrates102,106included in the power module100. According to this embodiment, the first segment132aand the second segment132bof the second part132of the patterned first metallization104of the first substrate102are interconnected by an additional part400of the patterned first metallization104. InFIG.4B, the dashed rectangles indicate where the die spacers130,138contact the patterned second metallization108of the second substrate106.

InFIGS.1A through4B, the only spacers include in the power module100are die spacers130,138for electrically connecting the source pads126,134of the vertical power transistor dies120,122to the patterned second metallization108of the second substrate106. The module configuration shown inFIGS.1A through4Bwith reduced spacer usage lowers loop inductance, yielding lower stray inductance. Additional chip area also becomes available by omitting via spacers. Further, the module outline (pin-out, mold body, etc.) is unaffected. More generally, the space gained by omitting via spacers can be used, e.g. to increase the distance between the power transistor dies120,122included in the power module100, accommodate additional dies, improve the electrical (e.g., higher output current capacity) and thermal performance of the power module100, simplify the module assembly process, reduce module cost, etc.

FIG.5Aillustrates the same view asFIG.1C, but schematically shows the low-side (LS) and high-side (HS) half bridge switch devices200,202formed by the first vertical power transistor dies120and the second vertical power transistor dies122, respectively, superimposed on the first substrate102.FIG.5Bis similar toFIG.5A, but with the high-side current path (+) and the phase current path (˜) superimposed on the first substrate102.FIG.5Cis similar to FIG.5B, but with the low-side current path (−) and the phase current path (˜) superimposed on the second substrate106.

Each ofFIGS.6A,7A,8A,9A and10Aschematically shows different configurations for the low-side (LS) and high-side (HS) switch devices200,202formed by the first vertical power transistor dies120and the second vertical power transistor dies122, respectively. Each ofFIGS.6B,7B,8B,9B and10Bschematically shows corresponding different configurations for the high-side current path (+) and the phase current path (˜) related to the first substrate102. Each ofFIGS.60,7C,8C,9C and10Cschematically shows corresponding different configurations for the low-side current path (−) and the phase current path (˜) related to the second substrate106. The patterned first metallization104of the first substrate102and the patterned second metallization108of the second substrate106can be designed/patterned accordingly to accommodate the different switch device and current path configurations shown inFIGS.6A-6C,7A-7C,8A-8C,9A-9C and10A-10C. More generally, the substrate metallizations104,108that face one another may be patterned to accommodate any desired layout for the first and second vertical power transistor dies120,122included in the power module100.

The upper part ofFIG.11Aillustrates a top perspective view of the multi-level lead frame140included in the power module100and the lower part ofFIG.11Aillustrates a corresponding side view of the multi-level lead frame140, before separation of the leads146,148,150,152,160,166,176,180,184,186from a frame1100of the multi-level lead frame140. The frame1100enables easier handling of the multi-level lead frame140by automatic assembly equipment. Features of the multi-level lead frame140such as the leads146,148,150,152,160,166,176,180,184,186may be formed by stamping, punching, etching, etc. The multi-level lead frame140may be formed and processed as a single unit or may be one of a plurality of leaf frame units that are interconnected and processed in parallel. The thickness of the multi-level lead frame140may range, e.g., from 0.1 mm to 1 mm or thicker.

The upper part ofFIG.11Billustrates a top perspective view of the multi-level lead frame140included in the power module100and the lower part ofFIG.11Billustrates a corresponding side view of the multi-level lead frame140, after separation of the leads146,148,150,152,160,166,176,180,184,186from the frame1100. The separation may be performed by stamping, punching, etching, etc. The distal ends of the leads146,148,150,152,160,166,176,180,184,186are bent in the z direction inFIG.11B, to yield respective final lead configurations used in the power module100.

As shown inFIGS.11A and11B, the substrate attachment end of some leads148,152,160,166,176,184,186of the multi-level lead frame140are at a first (lower) level ‘L1’ which corresponds to the patterned first metallization104of the first substrate102. The substrate attachment end of other leads146,180of the multi-level lead frame140are bent in the z direction so as to be positioned at a second (upper) level ‘L2’ which corresponds to the patterned second metallization108of the second substrate106. The lead150of the multi-level lead frame140that provides the phase current path (AC) has a split substrate attachment end inFIGS.11A and11B. The split end of the phase current path lead150includes a first part300at the lower level L1for attachment to the patterned first metallization104of the first substrate102and a second part302at the upper level L2for attachment to the patterned second metallization108of the second substrate106.

The difference between the first and second levels L1, L2corresponds to the vertical (z direction) space or gap between the patterned first metallization104of the first substrate102and the patterned first metallization104of the first substrate102. The magnitude of the vertical space or gap corresponds to the height (thickness) of the vertical power transistor dies102,122plus the height (thickness) of the die spacers130,138. The height (thickness) of the die spacers130,138may be chosen to ensure adequate clearance for the gate bond wires172,174.

FIG.12illustrates a partial cross-sectional view of the power module100. An outline of the mold body114is shown inFIG.12, so that the internal module components are visible. InFIG.12, the proximal (substrate attachment) end of the lead150of the multi-level lead frame140that provides the phase current path (AC) has a split configuration to enable attachment of the phase current path lead150to both the patterned first metallization104of the first substrate102and the patterned second metallization108of the second substrate106. The split end of the phase current path lead150has a first part300at the lower level L1that is attached to the first part124of the patterned first metallization104of the first substrate102and a second part302at the upper level L2that is attached to the second part136of the patterned second metallization108of the second substrate106. The second part302of the split end of the phase current path lead150has a transition zone1200that is bent at an angle a such as 30° with a range of −15°/+60° to accommodate the height transition from the lower level L1that corresponds to the patterned first metallization104of the first substrate102to the upper level L2that corresponds to the patterned second metallization108of the second substrate106.

FIG.13illustrates a partial cross-sectional view of the power module100, according to another embodiment. An outline of the mold body114is shown inFIG.13, so that the internal module components are visible. InFIG.13, the proximal (substrate attachment) end of the lead150of the multi-level lead frame140that provides the phase current path (AC) has a bent end1300to enable attachment of the phase current path lead150to both the patterned first metallization104of the first substrate102and the patterned second metallization108of the second substrate106. The bent end1300of the phase current path lead150has a first part1302at the first (lower) level L1and attached to the first part124of the patterned first metallization104of the first substrate102. The bent end1300of the phase current path lead150also has a second part1304that transitions to the second (upper) level L2and is attached to the second part128of the patterned second metallization108of the second substrate106.

FIG.14illustrates a partial cross-sectional view of the power module100, according to another embodiment. An outline of the mold body114is shown inFIG.14, so that the internal module components are visible. InFIG.14, the proximal (substrate attachment) end1400of the lead150of the multi-level lead frame140that provides the phase current path (AC) has an increased thickness (T2>T1) compared to a part1402of the lead150joining the proximal end1400. A first (lower) side1404of the proximal end1400is attached to the first part124of the patterned first metallization104of the first substrate102and a second (upper) side1406of the proximal end1400opposite the first side1404is attached to the second part128of the patterned second metallization108of the second substrate106. In one embodiment, the proximal end1400of the phase current path lead150includes a stack of two or more metallic layers, with a lowermost metallic layer1408being attached to the first part124of the patterned first metallization104of the first substrate102and an uppermost metallic layer1410being attached to the second part128of the patterned second metallization108of the second substrate106.

The metallic layers1408,1410of the stack may be formed by joining different lead frames by an electrically conductive joining material1412such as solder, welding, sintering, gluing, mechanical fixing (e.g., screw, clamp, rivet, etc.), etc. The separate lead frames may be connected inside or outside of the mold body114.

Example 1. A power module, comprising: a first substrate comprising a patterned first metallization; a second substrate comprising a patterned second metallization that faces the patterned first metallization; a first plurality of vertical power transistor dies having a drain pad attached to a first part of the patterned first metallization and a source pad electrically connected to a first part of the patterned second metallization; a second plurality of vertical power transistor dies having a drain pad attached to a second part of the patterned first metallization and a source pad electrically connected to a second part of the patterned second metallization; and a lead frame between the first substrate and the second substrate, wherein the first plurality of vertical power transistor dies and the second plurality of vertical power transistor dies form a half bridge, wherein the lead frame comprises: a first lead attached to the first part of the patterned second metallization and providing a low-side current path to the half bridge; a second lead attached to the second part of the patterned first metallization and providing a high-side current path to the half bridge; and a third lead attached to both the first part of the patterned first metallization and the second part of the patterned second metallization, and providing a phase current path to the half bridge.

Example 2. The power module of example 1, wherein: the drain of each vertical power transistor die in a first subset of the second plurality of vertical power transistor dies is attached to a first segment of the second part of the patterned first metallization and the drain of each vertical power transistor die in a second subset of the second plurality of vertical power transistor dies is attached to a second segment of the second part of the patterned first metallization; the first part of the patterned first metallization is laterally interposed between the first segment and the second segment of the second part of the patterned first metallization; the second lead is attached to the first segment of the second part of the patterned first metallization; the lead frame further comprises a fourth lead attached to the second segment of the second part of the patterned first metallization; the second lead provides the high-side current path to the first subset of the second plurality of vertical power transistor dies; and the fourth lead provides the high-side current path to the second subset of the second plurality of vertical power transistor dies.

Example 3. The power module of example 2, wherein the first plurality of vertical power transistor dies is flanked on a first side by the first subset of the second plurality of vertical power transistor dies, and wherein the first plurality of vertical power transistor dies is flanked on a second side opposite the first side by the second subset of the second plurality of vertical power transistor dies.

Example 4. The power module of example 2 or 3, wherein the first segment and the second segment of the second part of the patterned first metallization are interconnected by an additional part of the patterned first metallization.

Example 5. The power module of any of examples 1 through 4, wherein the third lead has a split end with a first part of the split end attached to the first part of the patterned first metallization and a second part of the split end attached to the second part of the patterned second metallization.

Example 6. The power module of any of examples 1 through 4, wherein the third lead has a bent end with a first part of the bent end at a first level and attached to the first part of the patterned first metallization and a second part of the bent end at a second level different than the first level and attached to the second part of the patterned second metallization.

Example 7. The power module of any of examples 1 through 4, wherein a proximal end of the third lead has an increased thickness compared to a part of the third lead joining the proximal end, and wherein a first side of the proximal end is attached to the first part of the patterned first metallization and a second side of the proximal end opposite the first side is attached to the second part of the patterned second metallization.

Example 8. The power module of example 7, wherein the proximal end of the third lead comprises a stack of two or more metallic layers, wherein a lowermost one of the two or more metallic layers is attached to the first part of the patterned first metallization and an uppermost one of the two or more metallic layers is attached to the second part of the patterned second metallization.

Example 9. The power module of any of examples 1 through 8, wherein the first lead is attached to the first part of the patterned second metallization by solder, wherein the second lead is attached to the second part of the patterned first metallization by solder, and wherein the third lead is attached to both the first part of the patterned first metallization and the second part of the patterned second metallization by solder.

Example 10. The power module of any of examples 1 through 9, wherein the lead frame further comprises a first gate lead attached to a third part of the patterned first metallization and a second gate lead attached to a fourth part of the patterned first metallization, wherein a gate pad of the first plurality of vertical power transistor dies is electrically connected to the third part of the patterned first metallization, and wherein a gate pad of the second plurality of vertical power transistor dies is electrically connected to the fourth part of the patterned first metallization.

Example 11. The power module of any of examples 1 through 10, wherein the lead frame further comprises a first sense lead attached to the second part of the patterned first metallization and a second sense lead attached to the first part of the patterned second metallization.

Example 12. A power module, comprising: a first substrate comprising a patterned first metallization; a second substrate comprising a patterned second metallization that faces the patterned first metallization; a first plurality of vertical power transistor dies having a drain pad attached to a first part of the patterned first metallization and a source pad electrically connected to a first part of the patterned second metallization; a second plurality of vertical power transistor dies having a drain pad attached to a second part of the patterned first metallization and a source pad electrically connected to a second part of the patterned second metallization; and a multi-level lead frame between the first substrate and the second substrate and attached to each of the first part of the patterned first metallization, the first part of the patterned second metallization, the second part of the patterned first metallization, and the second part of the patterned second metallization.

Example 13. A power module, comprising: a first substrate comprising a patterned first metallization; a second substrate comprising a patterned second metallization that faces the patterned first metallization; a first plurality of vertical power transistor dies forming a low-side switch of a half bridge and having a drain pad attached to a first part of the patterned first metallization and a source pad electrically connected to a first part of the patterned second metallization; a second plurality of vertical power transistor dies forming a high-side switch of the half bridge and having a drain pad attached to a second part of the patterned first metallization and a source pad electrically connected to a second part of the patterned second metallization; and a multi-level lead frame attached to both the patterned first metallization and the patterned second metallization and providing a low-side current path, a high-side current path, and a phase current path to the half bridge.