Semiconductor device having an amorphous silicon-germanium gate electrode

A silicon germanium layer is deposited over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, an upper silicon layer in an amorphous state is deposited on the silicon germanium layer. Thereafter, a gate electrode is formed by patterning the silicon germanium layer and the upper silicon layer.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device including a gate electrode and a method for fabricating the device.

Recently, as semiconductor devices have been downsized drastically and as the number of devices integrated on a chip has been increasing steeply, dual-gate CMOSFETs (complementary metal-oxide semiconductor field-effect transistors) have been used more and more widely.

Hereinafter, a p-channel MOSFET included in a known dual-gate CMOS device will be described as a typical known semiconductor device with reference to FIG.11.

As shown inFIG. 11, a gate electrode3of polysilicon is formed over a semiconductor substrate1of silicon with a gate insulating film2interposed between them. Normally, the gate electrode3is doped with a dopant, e.g., boron (B), by an ion implantation technique. The boron ions are implanted into a polysilicon film, of which the gate electrode3will be made, at an energy low enough to form a boron concentration profile in the gate electrode3with one of its peaks located near the upper surface thereof and to prevent the boron atoms from penetrating through the gate insulating film2into the semiconductor substrate1.

In this case, if the polysilicon film to be the gate electrode3is annealed after having been doped with boron, the boron atoms in the polysilicon film diffuse toward the semiconductor substrate1. Any inappropriate condition for the annealing process causes the boron atoms in the polysilicon film to permeate through the gate insulating film2in the semiconductor substrate1. Then, the dopant concentration in the semiconductor substrate1changes to degrade the device characteristics. Also, where a metal layer is deposited on the polysilicon film to form a poly-metal gate electrode and then a silicon nitride film to be a hard mask is deposited on the metal layer and annealed or where a silicon nitride film to be a sidewall is deposited on the gate electrode3and annealed, the permeation of the boron atoms into the semiconductor substrate1is observed noticeably.

To suppress the boron atoms from permeating the semiconductor substrate1, various measures have been taken; a silicon oxynitride film that can suppress the boron atom permeation to a certain degree is adopted as the gate insulating film2.

However, even if the silicon oxynitride film is used as the gate insulating film2, the boron atom permeation is not completely suppressible. Particularly, where the silicon oxynitride film is extremely thin (less than 3 nm, for example) to catch up with performance enhancement of devices, the silicon oxynitride film can suppress the boron atom permeation just slightly to say the least.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to prevent a dopant introduced into a gate electrode from permeating a semiconductor substrate.

To achieve this object, a first inventive semiconductor device includes a gate electrode that has been formed over a semiconductor substrate with a gate insulating film interposed between the gate electrode and the substrate. The gate electrode includes: a silicon germanium layer; and an upper silicon layer that has been formed on the silicon germanium layer.

In the first inventive device, a gate electrode includes: a silicon germanium layer; and an upper silicon layer that has been formed on the silicon germanium layer. Thus, in doping the gate electrode with a dopant such as boron, the dopant can be introduced by an ion implantation process into the silicon germanium layer through the upper silicon layer. So, the dopant can be implanted sufficiently shallow while the penetration of the dopant into a semiconductor substrate, which is usually caused by a channeling phenomenon, is suppressible. Accordingly, it is possible to prevent the dopant, with which the gate electrode has been doped, from permeating the semiconductor substrate even if the gate electrode is subsequently subjected to an annealing process, for example. As a result, any variation in device characteristics, which might result from a change in dopant concentration in the semiconductor substrate, is suppressible.

Also, in the first inventive device, the bandgap of the silicon germanium layer for the gate electrode may be changed by controlling a germanium concentration in the silicon germanium layer. And the threshold voltage controllability of the gate electrode can be improved by changing the bandgap. In that case, the gate electrode does not have to be doped with any dopant. As a result, any variation in device characteristics, which might result from the permeation of a dopant from the gate electrode into the semiconductor substrate, is suppressible with more certainty.

Further, in the first inventive device, since the silicon germanium layer is covered with the upper silicon layer, cross contamination (contamination of the semiconductor substrate or a reactor), caused by germanium atoms released from the silicon germanium layer, is also suppressible. Accordingly, a process for forming a gate electrode out of silicon layers can be utilized.

In one embodiment of the present invention, the gate electrode may further include a lower silicon layer under the silicon germanium layer.

In such an embodiment, the lower silicon layer with a surface morphology better than that of the silicon germanium layer exists under the silicon germanium layer for the gate electrode. Thus, the breakdown strength of the gate insulating film can be improved compared to a situation where the silicon germanium layer and the gate insulating film are in direct contact with each other.

In another embodiment, the gate electrode may further include a metal layer on the upper silicon layer, and a silicon nitride film may have been formed over the gate electrode.

Then, the gate electrode is implementable as a poly-metal gate electrode. And even though the silicon nitride film has been formed over the gate electrode, any dopant existing in the gate electrode hardly permeates the semiconductor substrate.

In this particular embodiment, an insulating layer preferably exists between the gate electrode and the silicon nitride film.

In that case, the dopant, existing in the gate electrode, even less likely permeates the semiconductor substrate when the insulating layer is made of silicon dioxide, for example.

A second inventive semiconductor device includes a gate electrode that has been formed over a semiconductor substrate with a gate insulating film interposed between the gate electrode and the substrate. The gate electrode includes a silicon germanium layer that has been deposited in an amorphous state.

In the second inventive device, a gate electrode includes a silicon germanium layer that has been deposited in an amorphous state. Thus, in doping the gate electrode with a dopant such as boron, the dopant can be introduced by an ion implantation process into the silicon germanium layer in the amorphous state. So, the dopant can be implanted sufficiently shallow while the penetration of the dopant into a semiconductor substrate, which is usually caused by a channeling phenomenon, is suppressible. Accordingly, it is possible to prevent the dopant, with which the gate electrode has been doped, from permeating the semiconductor substrate even if the gate electrode is subsequently subjected to an annealing process, for example. As a result, any variation in device characteristics, which might result from a change in dopant concentration in the semiconductor substrate, is suppressible.

Also, in the second inventive device, the bandgap of the silicon germanium layer for the gate electrode may be changed by controlling a germanium concentration in the silicon germanium layer. And the threshold voltage controllability of the gate electrode can be improved by changing the bandgap. In that case, the gate electrode does not have to be doped with any dopant. As a result, any variation in device characteristics, which might result from the permeation of a dopant from the gate electrode into the semiconductor substrate, is suppressible with more certainty.

Further, in the second inventive device, the silicon germanium layer in the amorphous state for the gate electrode has a better surface morphology than a silicon germanium layer in a polycrystalline state. Accordingly, the silicon germanium layer has a good surface morphology near the interface with the gate insulating film. Thus, the breakdown strength of the gate insulating film improves.

Furthermore, in the second inventive device, the gate electrode may be made of the silicon germanium layer alone. For that reason, the process steps of forming the gate electrode can be simplified as compared to forming a gate electrode with a multilayer structure, and the gate electrode can also have its thickness reduced to e.g., 100 nm or less.

In one embodiment of the present invention, the gate electrode may further include a metal layer on the silicon germanium layer, and a silicon nitride film may have been formed over the gate electrode.

In such an embodiment, the gate electrode is implementable as a poly-metal gate electrode. And even though the silicon nitride film has been formed over the gate electrode, any dopant existing in the gate electrode hardly permeates the semiconductor substrate.

In this particular embodiment, an insulating layer preferably exists between the gate electrode and the silicon nitride film.

In that case, the dopant, existing in the gate electrode, even less likely permeates the semiconductor substrate when the insulating layer is made of silicon dioxide, for example.

In one embodiment of the first or second inventive device, a germanium concentration in a part of the silicon germanium layer near a lower surface thereof is preferably lower than a germanium concentration in the other part of the silicon germanium layer.

In such an embodiment, it is possible to prevent the gate insulating film from decreasing its breakdown strength or changing its characteristics while suppressing decrease in the threshold voltage controllability of the gate electrode.

In another embodiment of the first or second inventive device, the silicon germanium layer may contain boron or phosphorus.

Then, the threshold voltage controllability of the gate electrode can be improved. Also, where the silicon germanium layer contains boron, the boron atoms existing in the silicon germanium layer are activated at a higher rate than in a normal polysilicon film. Thus the boron atoms will even less likely permeate the semiconductor substrate.

In another embodiment of the first or second inventive device, a silicon nitride film may have been formed over the gate electrode with an insulating layer interposed between the gate electrode and the silicon nitride film.

Then, even though the silicon nitride film has been formed over the gate electrode, any dopant existing in the gate electrode hardly permeates the semiconductor substrate.

In another embodiment of the first or second inventive device, the gate electrode may be used as a gate electrode for at least one of two MOS transistors in a dual-gate MOS device.

Then, it is possible to prevent a dopant introduced into a p+or n+gate electrode for one of the two MOS transistors in the dual-gate CMOS device from permeating the semiconductor substrate. Thus, any variation in the characteristics of the dual-gate CMOS device, which might result from a change in dopant concentration in the semiconductor substrate, is suppressible. Also, the bandgap of the silicon germanium layer of the p+or n+gate electrode may be changed by controlling a germanium concentration in the silicon germanium layer. And the threshold voltage controllability of the p+or n+gate electrode can be improved by changing the bandgap. In that case, the p+or n+gate electrode does not have to be doped with any dopant. That is to say, just by controlling the germanium concentration in the silicon germanium layer of the p+or n+gate electrode, it is possible to form a dual-gate CMOS device easily while preventing the penetration or permeation of any dopant into the semiconductor substrate.

A first inventive method for fabricating a semiconductor device includes the step of a) depositing a silicon germanium layer over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. The method further includes the step of b) depositing an upper silicon layer in an amorphous state on the silicon germanium layer. And the method further includes the step of c) forming a gate electrode by patterning the silicon germanium layer and the upper silicon layer.

According to the first inventive method, a silicon germanium layer and an upper silicon layer in an amorphous state are deposited in this order over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, a gate electrode is formed by patterning the silicon germanium layer and the upper silicon layer. Thus, in doping the gate electrode with a dopant such as boron, the dopant can be introduced by an ion implantation process into the silicon germanium layer through the upper silicon layer in the amorphous state. So, the dopant can be implanted sufficiently shallow while the penetration of the dopant into the semiconductor substrate, which is usually caused by a channeling phenomenon, is suppressible. Accordingly, it is possible to prevent the dopant, with which the gate electrode has been doped, from permeating the semiconductor substrate even if the gate electrode is subsequently subjected to an annealing process, for example. As a result, any variation in device characteristics, which might result from a change in dopant concentration in the semiconductor substrate, is suppressible.

Also, according to the first inventive method, the bandgap of the silicon germanium layer for the gate electrode may be changed by controlling a germanium concentration in the silicon germanium layer. And the threshold voltage controllability of the gate electrode can be improved by changing the bandgap. In that case, the gate electrode does not have to be doped with any dopant. As a result, any variation in device characteristics, which might result from the permeation of a dopant from the gate electrode into the semiconductor substrate, is suppressible with more certainty.

Further, according to the first inventive method, since the silicon germanium layer is covered with the upper silicon layer, cross contamination, caused by germanium atoms released from the silicon germanium layer, is also suppressible. Accordingly, a process for forming a gate electrode out of silicon layers can be utilized.

In one embodiment of the present invention, the first method may further include the step of depositing a lower silicon layer on the gate insulating film before the step a) is performed, and the step c) may include patterning the lower silicon layer.

In such an embodiment, the lower silicon layer with a surface morphology better than that of the silicon germanium layer exists under the silicon germanium layer for the gate electrode. Thus, the breakdown strength of the gate insulating film can be improved compared to a situation where the silicon germanium layer and the gate insulating film are in direct contact with each other.

In another embodiment, the first method may further include the step of d) depositing a metal layer and a silicon nitride film in this order on the upper silicon layer between the steps b) and c), and the step c) may include patterning the silicon nitride film and then patterning the metal layer by using the patterned silicon nitride film as a mask.

Then, the gate electrode is implementable as a poly-metal gate electrode. And even though the silicon nitride film has been formed over the gate electrode, any dopant existing in the gate electrode hardly permeates the semiconductor substrate.

In this particular embodiment, the step d) preferably includes depositing an insulating layer between the metal layer and the silicon nitride film.

In that case, the dopant, existing in the gate electrode, even less likely permeates the semiconductor substrate when the insulating layer is made of silicon dioxide, for example.

A second inventive method for fabricating a semiconductor device includes the step of a) depositing a silicon germanium layer in an amorphous state over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. The method further includes the step of b) forming a gate electrode by patterning the silicon germanium layer.

According to the second inventive method, a silicon germanium layer in an amorphous state is deposited over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, a gate electrode is formed by patterning the silicon germanium layer. Thus, in doping the gate electrode with a dopant such as boron, the dopant can be introduced by an ion implantation process into the silicon germanium layer in the amorphous state. So, the dopant can be implanted sufficiently shallow while the penetration of the dopant into the semiconductor substrate, which is usually caused by a channeling phenomenon, is suppressible. Accordingly, it is possible to prevent the dopant, with which the gate electrode has been doped, from permeating the semiconductor substrate even if the gate electrode is subsequently subjected to an annealing process, for example. As a result, any variation in device characteristics, which might result from a change in dopant concentration in the semiconductor substrate, is suppressible.

Also, according to the second inventive method, the bandgap of the silicon germanium layer for the gate electrode may be changed by controlling a germanium concentration in the silicon germanium layer. And the threshold voltage controllability of the gate electrode can be improved by changing the bandgap. In that case, the gate electrode does not have to be doped with any dopant. As a result, any variation in device characteristics, which might result from the permeation of a dopant from the gate electrode into the semiconductor substrate, is suppressible with more certainty.

Further, according to the second inventive method, the silicon germanium layer in the amorphous state for the gate electrode has a better surface morphology than a silicon germanium layer in a polycrystalline state. Accordingly, the silicon germanium layer has a good surface morphology near the interface with the gate insulating film. Thus, the breakdown strength of the gate insulating film improves.

Furthermore, according to the second inventive method, the gate electrode may be made of the silicon germanium layer alone. Thus, the process steps of forming the gate electrode can be simplified as compared to forming a gate electrode with a multilayer structure, and the gate electrode can also have its thickness reduced to e.g., 100 nm or less.

In one embodiment of the present invention, the second method may further include the step of c) depositing a metal layer and a silicon nitride film in this order on the silicon germanium layer between the steps a) and b). And the step b) may include patterning the silicon nitride film and then patterning the metal layer by using the patterned silicon nitride film as a mask.

In such an embodiment, the gate electrode is implementable as a poly-metal gate electrode. And even though the silicon nitride film has been formed over the gate electrode, any dopant existing in the gate electrode hardly permeates the semiconductor substrate.

In this particular embodiment, the step c) preferably includes depositing an insulating layer between the metal layer and the silicon nitride film.

In that case, the dopant, existing in the gate electrode, even less likely permeates the semiconductor substrate when the insulating layer is made of silicon dioxide, for example.

In one embodiment of the first or second inventive method, the step a) may include: supplying a first source gas containing silicon and a second source gas containing germanium; and changing a mixture ratio of the first and second source gases with time, thereby setting a germanium concentration in a part of the silicon germanium layer near a lower surface thereof lower than a germanium concentration in the other part of the silicon germanium layer.

In such an embodiment, it is possible to prevent the gate insulating film from decreasing its breakdown strength or changing its characteristics while suppressing decrease in the threshold voltage controllability of the gate electrode.

In another embodiment of the first or second inventive method, the silicon germanium layer may contain boron or phosphorus.

Then, the threshold voltage controllability of the gate electrode can be improved. Also, where the silicon germanium layer contains boron, the boron atoms existing in the silicon germanium layer are activated at a higher rate than in a normal polysilicon film. Thus the boron atoms will even less likely permeate the semiconductor substrate.

In another embodiment, the first or second inventive method may further include the step of implanting boron or phosphorus ions into the silicon germanium layer.

Then, the silicon germanium layer can be doped with boron or phosphorus with certainty.

In an alternative embodiment of the first or second inventive method, the step a) may include supplying a gas containing silicon, a gas containing germanium and a gas containing boron or phosphorus, thereby depositing the silicon germanium layer containing boron or phosphorus.

Then, the silicon germanium layer can also be doped with boron or phosphorus with certainty. In addition, the silicon germanium layer can be doped with boron or phosphorus without performing an ion implantation process thereon. So, the penetration of the boron or phosphorus atoms into the semiconductor substrate, which is usually caused by a channeling phenomenon, does not arise. That is to say, no boron or phosphorus atoms permeate the semiconductor substrate even when an annealing process is carried out after that on the boron or phosphorus ions implanted.

In another embodiment, the first or second inventive method may further include the step of depositing a silicon nitride film over the gate electrode with an insulating layer interposed between the gate electrode and the silicon nitride film.

Then, even though the silicon nitride film has been formed over the gate electrode, any dopant existing in the gate electrode hardly permeates the semiconductor substrate.

In another embodiment of the first or second inventive method, the gate electrode may be used as a gate electrode for at least one of two MOS transistors in a dual-gate MOS device.

Then, it is possible to prevent a dopant introduced into a p+or n+gate electrode for one of the two MOS transistors in the dual-gate CMOS device from permeating the semiconductor substrate. Thus, any variation in the characteristics of the dual-gate CMOS device, which might result from a change in dopant concentration in the semiconductor substrate, is suppressible. Also, the bandgap of the silicon germanium layer of the p+or n+gate electrode may be changed by controlling a germanium concentration in the silicon germanium layer. And the threshold voltage controllability of the p+or n+gate electrode can be improved by changing the bandgap. In that case, the p+or n+gate electrode does not have to be doped with any dopant. That is to say, just by controlling the germanium concentration in the silicon germanium layer of the p+or n+gate electrode, it is possible to form a dual-gate CMOS device easily while preventing the penetration or permeation of any dopant into the semiconductor substrate.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a semiconductor device and a method for fabricating the device in accordance with a first embodiment of the present invention will be described with reference to the accompanying drawings.

FIGS. 1A through 1Dare cross-sectional views corresponding to respective process steps for fabricating a semiconductor device in accordance with the first embodiment.

First, as shown inFIG. 1A, a gate insulating film12is deposited to a thickness of about 3 nm, for example, on a silicon substrate11of a conductivity type.

Next, as shown inFIG. 1B, a silicon germanium layer13(which will be herein called an “SiGe layer”) is deposited to a thickness of 100 nm, for example, on the gate insulating film12by an LPCVD (low-pressure chemical vapor deposition) process. In this process, a source gas containing silicon (which will be herein called as an “Si source gas”) and a source gas containing germanium (which will be herein called a “Ge source gas”) are supplied at a temperature of about 600° C. or less.

In this case, SiH4(mono silane) or Si2H6(disilane) gas, for example, may be used as the Si source gas. GeH4gas, for example, may be used as the Ge source gas. In this process step, the Ge concentration (which will be herein represented by mass percentage) in the SiGe layer13is controllable by changing the mixture ratio of the Si and Ge source gases. For example, the SiGe layer13can have a Ge concentration of about 50% by supplying the SiH4and GeH4gases at a flow rate ratio of one to five.

Next, as shown inFIG. 1C, a silicon layer14(which will be herein called an “Si layer”) in an amorphous state is deposited to a thickness of 40 nm, for example, on the SiGe layer13by an LPCVD process with an Si source gas supplied at a temperature of about 500° C. In this process step, the Si layer14may be deposited continuously in the chamber where the SiGe layer13has been deposited by changing the source gases, for example. Or the SiGe and Si layers13and14may be deposited in mutually different chambers either successively or as completely independent process steps.

Then, as shown inFIG. 1C, boron ions are implanted into the SiGe layer13at an acceleration voltage of 5 keV and at a dose of 1×1015/cm2.

Next, as shown inFIG. 1D, the Si layer14, SiGe layer13and gate insulating film12are sequentially etched by using a mask pattern (not shown), which covers part of the substrate where a gate electrode will be formed, thereby forming a gate electrode15consisting of the SiGe and Si layers13and14over the silicon substrate11with the gate insulating film12interposed between them.

In the first embodiment, after the Si layer14was formed and until boron ions have been implanted into the SiGe layer13, no process steps requiring annealing are carried out to keep the Si layer14amorphous. Thus it is possible to prevent the boron atoms, existing in the SiGe layer13, from penetrating into the silicon substrate11or the boron ions from being implanted too deep. After the boron ions have been implanted into the SiGe layer13, however, the Si layer14will be polycrystalline in the end because the Si layer14will be annealed in the process step of depositing an interlevel dielectric film on the gate electrode15, for example.

As described above, according to the first embodiment, an SiGe layer13and then an Si layer14in an amorphous state are deposited in this order over a silicon substrate11with a gate insulating film12interposed between the SiGe layer13and the silicon substrate11. Then, boron ions are implanted into the SiGe layer13. Thereafter, the SiGe and Si layers13and14are patterned to form a gate electrode15. Thus, the boron ions are implanted into the SiGe layer13through the Si layer14in the amorphous state; the boron ions can be implanted sufficiently shallow while the penetration of the boron atoms into the silicon substrate11, which is usually caused by a channeling phenomenon, is suppressible. Accordingly, it is possible to prevent the boron atoms, with which the SiGe layer13for the gate electrode15has been doped, from permeating the silicon substrate11even if the SiGe layer13is subsequently annealed, for example. As a result, any variation in device characteristics, which might result from a change in dopant concentration in the silicon substrate11, is suppressible.

FIG. 2illustrates how the flatband voltage (which will be herein called “vfb”) of the gate electrode15changes with the thickness of the SiGe layer13. The data shown inFIG. 2was obtained where the thickness of the gate insulating film12was about 3 nm, the Ge concentration in the SiGe layer13was about 20% and the boron ions were implanted at an acceleration voltage of about 5 keV. InFIG. 2, the solid circles connected with solid lines, the solid squares connected with one-dot chains, and the open triangles connected with dashed lines show how Vfb changed where the thickness of the Si layer14was 20, 30 and 40 nm, respectively.

As shown inFIG. 2, as for an Si layer14with a thickness of 20 nm, if the SiGe layer had a thickness of 75, 100 and 125 nm, Vfb was 0.598, 0.217 and 0.079 V, respectively. As for an Si layer14with a thickness of 30 nm, if the SiGe layer had a thickness of 50, 75 and 125 nm, Vfb was 0.683, 0.282 and 0.062 V, respectively. As for an Si layer14with a thickness of 40 nm, if the SiGe layer had a thickness of 50, 75, 100 and 125 nm, Vfb was 0.201, 0.121, 0.074 and 0.054 V, respectively. The lower the flatband voltage Vfb, the smaller the quantity of boron atoms permeating. Thus where the SiGe layer13has a thickness of about 80 nm, the permeation of the boron atoms into the silicon substrate11is sufficiently suppressible by setting the thickness of the Si layer14at about 30 nm or more.

Further, according to the first embodiment, the SiGe layer13for the gate electrode15is doped with the boron ions, so the threshold voltage (which will be herein called “Vt”) controllability of the gate electrode15improves.

Also, according to the first embodiment, the boron atoms in the SiGe layer13are activated at a higher rate than in a normal polysilicon film. Thus the boron atoms will much less likely permeate the silicon substrate11.

Furthermore, according to the first embodiment, since the SiGe layer13is covered with the Si layer14, cross contamination, caused by the Ge atoms released from the SiGe layer13, is also suppressible. Accordingly, a process for forming a gate electrode out of Si layers (which will be herein called an “Si process”) can be utilized.

In addition, although boron ions are implanted into the SiGe layer13in the first embodiment, phosphorus (P) ions may also be implanted instead (e.g., at an acceleration voltage of 10 keV and at a dose of 5×1015/cm2). Or boron and phosphorus ions may be both implanted at a time. Also, instead of doping the SiGe layer13with boron or phosphorus by an ion implantation process after the SiGe layer13has been deposited, the SiGe layer13containing boron or phosphorous may be deposited by supplying not only Si and Ge source gases but also a gas containing boron or phosphorus (B2H6gas, for example) during the deposition process thereof. Or the SiGe layer13may also be doped with boron or phosphorus by thermally diffusing phosphine (PH3), for example, after the SiGe layer13has been deposited.

Also, in the first embodiment, the process step of doping the SiGe layer13with boron, for example, may be omitted. Specifically, the bandgap of the SiGe layer13for the gate electrode15can be changed by controlling the Ge concentration in the SiGe layer13. Accordingly, the Vt controllability of the gate electrode15can be improved without doping the SiGe layer13with boron, for example. As a result, even in applying this embodiment to forming a dual-gate CMOS device, there is no concern about the permeation of any dopant, e.g., boron. Further, in that case, the Si layer14does not have to be deposited in an amorphous state, nor does the Si layer14have to be kept amorphous until a dopant such as boron has been introduced.

Further, in the first embodiment, the SiGe layer13may also be deposited in an amorphous state by an LPCVD process where Si and Ge source gases are supplied at a temperature of about 500° C. or less. Then, the boron atoms will even less likely permeate the silicon substrate11.

Modified Example of Embodiment 1

Hereinafter, a semiconductor device and a method for fabricating the device in accordance with a modified example of the first embodiment will be described with reference to the accompanying drawings.

The method of this modified example differs from that of the first embodiment in that the Ge concentration in the SiGe layer13is changed in the depth direction by changing the mixture ratio of Si and Ge source gases with time in the process step of depositing the SiGe layer13(see FIG.1B).

Specifically, the SiGe layer13may have a Ge concentration of about 10%, for example, near the lower surface thereof (i.e., part of the SiGe layer13, close to the interface with the gate insulating film12) by setting the ratio of the Ge source gas very low or to zero for a while after the SiGe layer13started to grow. On the other hand, the SiGe layer13may have a Ge concentration of about 70%, for example, near the upper surface thereof by increasing the ratio of the Ge source gas as the SiGe layer13grows thicker.

In this process, since the Ge concentration is much lower, the surface morphology of the SiGe layer13improves, thus the interface between the gate insulating film12and the SiGe layer13has almost no unevenness. In other words, no too dense electric fields are distributed around the interface. Accordingly, it is possible to prevent the breakdown strength of the gate insulating film12from decreasing. Also, the gate insulating film12is not exposed to the Ge source gas with a high concentration for sometime after the SiGe layer13started to grow. Thus, variation in characteristics of the gate insulating film12is avoidable. Further, the overall Ge concentration in the SiGe layer13for the gate electrode15does not decrease, nor does the Vt controllability of the gate electrode15for that reason.

Where the Ge source gas is supplied at various ratios increasing along with the growth of the SiGe layer13, the Ge source gas ratio may be increased either continuously or discontinuously to change the Ge concentration in the SiGe layer13continuously or discontinuously in the depth direction as shown inFIG. 3Aor3B.

According to the modified example of the first embodiment, the following effects are attainable in addition to the effects of the first embodiment.

Specifically, in this modified example, the SiGe layer13can have a lower Ge concentration near the lower surface thereof as compared to the other part thereof by changing the mixture ratio of Si and Ge source gases with time in the process step of depositing the SiGe layer13. For this reason, it is possible to prevent the gate insulating film12from decreasing its breakdown strength or changing its characteristics while suppressing decrease in the Vt controllability of the gate electrode15.

Hereinafter, a semiconductor device and a method for fabricating the device in accordance with a second embodiment of the present invention will be described with reference to the accompanying drawings.

FIGS. 4A through 4Dare cross-sectional views corresponding to respective process steps for fabricating a semiconductor device in accordance with the second embodiment.

First, as shown inFIG. 4A, a gate insulating film22is deposited to a thickness of about 3 nm, for example, on a silicon substrate21of a conductivity type. Then, a lower silicon layer23(which will be herein called a “lower Si layer”) in an amorphous state is deposited to a thickness of 10 nm, for example, on the gate insulating film22by an LPCVD process with an Si source gas such as SiH4gas supplied at a temperature of about 500° C.

Next, as shown inFIG. 4B, an SiGe layer24is deposited to a thickness of 100 nm, for example, on the lower Si layer23by an LPCVD process with Si and Ge source gases supplied at a temperature of about 600° C. or less. In this process step, the Ge concentration in the SiGe layer24is controllable by changing the mixture ratio of the Si and Ge source gases.

Next, as shown inFIG. 4C, an upper silicon layer25(which will be herein called an “upper Si layer”) in an amorphous state is deposited to a thickness of 40 nm, for example, on the SiGe layer24by an LPCVD process with an Si source gas supplied at a temperature of about 500° C.

It should be noted that the lower or upper Si layer23or25may be deposited continuously in the chamber where the SiGe layer24will be or has been deposited, respectively, by changing the source gases, for example or the lower or upper Si layer23or25and the SiGe layer24may be deposited in mutually different chambers either successively or as completely independent process steps.

Then, as shown inFIG. 4C, boron ions are implanted into the SiGe layer24at an acceleration voltage of 5 keV and at a dose of 1×1015/cm2.

Next, as shown inFIG. 4D, the upper Si layer25, SiGe layer24, lower Si layer23and gate insulating film22are sequentially etched by using a mask pattern (not shown), which covers part of the substrate where a gate electrode will be formed, thereby forming a gate electrode26consisting of the lower Si, SiGe and upper Si layers23,24and25over the silicon substrate21with the gate insulating film22interposed between them.

In the second embodiment, after the upper Si layer25was formed and until boron ions have been implanted into the SiGe layer24, no process steps requiring annealing are carried out to keep the upper Si layer25amorphous. Thus it is possible to prevent the boron atoms, existing in the SiGe layer24, from penetrating into the silicon substrate21or the boron ions from being implanted too deep. After the boron ions have been implanted into the SiGe layer24, however, the upper Si layer25will be polycrystalline in the end because the upper Si layer25will be annealed in the process step of depositing an interlevel dielectric film on the gate electrode26, for example.

As described above, according to the second embodiment, a lower Si layer23in an amorphous state, SiGe layer24and upper Si layer25in an amorphous state are deposited in this order over a silicon substrate21with a gate insulating film22interposed between the lower Si layer23and the silicon substrate21. Then, boron ions are implanted into the SiGe layer24. Thereafter, the lower Si, SiGe and upper Si layers23,24and25are patterned to form a gate electrode26. Thus, the boron ions are implanted into the SiGe layer24through the upper Si layer25in the amorphous state; the boron ions can be implanted sufficiently shallow while the penetration of the boron atoms into the silicon substrate21, which is usually caused by a channeling phenomenon, is suppressible. Accordingly, it is possible to prevent the boron atoms, with which the SiGe layer24for the gate electrode26has been doped, from permeating the silicon substrate21even if the SiGe layer24is subjected to an annealing process, for example, after that. As a result, any variation in device characteristics, which might result from a change in dopant concentration in the silicon substrate21, is suppressible. Also, the lower Si layer23with a surface morphology better than that of the SiGe layer24exists under the SiGe layer24of the gate electrode26. Thus, the breakdown strength of the gate insulating film22(which will be herein called an “insulating film breakdown strength”) can be kept high enough. Specifically, where the gate insulating film22and the SiGe layer24are in direct contact with each other, the interface between the gate insulating film22and the SiGe layer24has unevenness. For this reason, electric field is distributed too densely around the interface, which results in decrease in the insulating film breakdown strength. In contrast, the second embodiment can suppress such an unwanted phenomenon.

Further, according to the second embodiment, the SiGe layer24for the gate electrode26is doped with boron, so the Vt controllability of the gate electrode26improves.

Also, according to the second embodiment, the boron atoms in the SiGe layer24are activated at a higher rate than in abnormal polysilicon film. Thus the boron atoms will much less likely permeate the silicon substrate21.

Furthermore, according to the second embodiment, since the SiGe layer24is covered with the upper Si layer25, cross contamination, caused by the Ge atoms released from the SiGe layer24, is also suppressible. Accordingly, an Si process can be utilized.

Although boron ions are implanted into the SiGe layer24in the second embodiment, phosphorus ions may also be implanted instead (e.g., at an acceleration voltage of 10 keV and at a dose of 5×1015/cm2). Or boron and phosphorus ions may be both implanted at a time. Also, instead of doping the SiGe layer24with boron or phosphorus, for example, by an ion implantation process after the SiGe layer24has been deposited, the SiGe layer24containing boron or phosphorus, for example, may be deposited by supplying not only Si and Ge source gases but also a gas containing boron or phosphorus, for example, (e.g., B2H6gas) during the deposition process thereof. Or the SiGe layer24may also be doped with boron or phosphorus, for example, by thermally diffusing PH3, for example, after the SiGe layer24has been deposited.

Also, in the second embodiment, the process step of doping the SiGe layer24with boron, for example, may be omitted. Specifically, the bandgap of the SiGe layer24for the gate electrode26can be changed by controlling the Ge concentration in the SiGe layer24. Accordingly, the Vt controllability of the gate electrode26can be improved without doping the SiGe layer24with boron, for example. As a result, even in applying this embodiment to forming a dual-gate CMOS device, there is no concern about the permeation of any dopant, e.g., boron. Further, in that case, the upper Si layer25does not have to be deposited in an amorphous state, nor does the upper Si layer25have to be kept amorphous until a dopant such as boron has been introduced.

Further, in the second embodiment, the SiGe layer24may also be deposited in an amorphous state by an LPCVD process where Si and Ge source gases are supplied at a temperature of about 500° C. or less. Then, the boron atoms will even less likely permeate the silicon substrate21.

Also, in the second embodiment, the SiGe layer24may have a lower Ge concentration near the lower surface thereof as compared to the other part thereof by changing the mixture ratio of Si and Ge source gases with time in the process step of depositing the SiGe layer24. Then, it is possible to prevent the gate insulating film22from decreasing its breakdown strength or changing its characteristics while suppressing decrease in the Vt controllability of the gate electrode26.

Modified Example of Embodiment 2

Hereinafter, a semiconductor device and a method for fabricating the device in accordance with a modified example of the second embodiment will be described with reference to the accompanying drawings.

The method of this modified example differs from that of the second embodiment in the following respect. Specifically, in the second embodiment, boron is introduced into the SiGe layer24by an ion implantation process after the SiGe layer24has been deposited. In this modified example, on the other hand, boron is introduced into the SiGe layer24during the deposition process thereof by supplying not only Si and Ge source gases but also a gas containing boron (which will be herein called a “B source gas”) such as B2H6gas.

FIGS. 5A through 5Dare cross-sectional views corresponding to respective process steps for fabricating a semiconductor device in accordance with this modified example.

First, as shown inFIG. 5A, a gate insulating film22is deposited to a thickness of about 3 nm, for example, on a silicon substrate21of a conductivity type as in the process step shown inFIG. 4Afor the second embodiment. Then, a lower Si layer23in an amorphous state is deposited to a thickness of 10 nm, for example, on the gate insulating film22by an LPCVD process with an Si source gas such as SiH4gas supplied at a temperature of about 500° C.

Next, as shown inFIG. 5B, an SiGe layer24containing boron is deposited to a thickness of 100 nm, for example, on the lower Si layer23by an LPCVD process with Si, Ge and B source gases supplied at a temperature of about 600° C. or less. In this process step, the Ge concentration in the SiGe layer24is controllable by changing the mixture ratio of the Si and Ge source gases.

Then, as shown inFIG. 5C, an upper Si layer25in an amorphous state is deposited to a thickness of 40 nm, for example, on the SiGe layer24by an LPCVD process with an Si source gas supplied at a temperature of about 500° C. as in the second embodiment.

Subsequently, as in the second embodiment, the upper Si layer25, SiGe layer24, lower Si layer23and gate insulating film22are sequentially etched by using a mask pattern (not shown), which covers part of the substrate where a gate electrode will be formed, thereby forming a gate electrode26consisting of the lower Si, SiGe and upper Si layers23,24and25over the silicon substrate21with the gate insulating film22interposed between them as shown in FIG.5D.

According to the modified example of the second embodiment, the following effects are attainable in addition to the effects of the second embodiment.

Specifically, in this modified example, not only Si and Ge source gases but also a B source gas are supplied to deposit the SiGe layer24containing boron. Thus, the SiGe layer24can be doped with boron without performing an ion implantation process thereon. So, the penetration of the boron atoms into the silicon substrate21, which is usually caused by a channeling phenomenon, does not arise. That is to say, no boron atoms permeate the silicon substrate21even when an annealing process is carried out after that on the boron ions implanted.

Although not only Si and Ge source gases but also a B source gas are supplied to deposit the SiGe layer24containing boron in this modified example, a gas containing phosphorous such as PH3gas may be supplied along with the Si and Ge source gases to deposit an SiGe layer containing phosphorous instead. Or not just the Si and Ge source gases but a gas containing both boron and phosphorous may be supplied to deposit an SiGe layer containing boron and phosphorous.

Hereinafter, a semiconductor device and a method for fabricating the device in accordance with a third embodiment of the present invention will be described with reference to the accompanying drawings.

FIGS. 6A through 6Care cross-sectional views corresponding to respective process steps for fabricating a semiconductor device in accordance with the third embodiment.

First, as shown inFIG. 6A, a gate insulating film32is deposited to a thickness of about 3 nm, for example, on a silicon substrate31of a conductivity type.

Next, as shown inFIG. 6B, an SiGe layer33in an amorphous state is deposited to a thickness of about 100 nm, for example, on the gate insulating film32by an LPCVD process with Si and Ge source gases supplied at a temperature of about 500° C. or less. In this process step, the Ge concentration in the SiGe layer33is controllable by changing the mixture ratio of the Si and Ge source gases. Then, boron ions are implanted into the SiGe layer33at an acceleration voltage of 5 keV and at a dose of 1×1015/cm2.

Subsequently, the SiGe layer33and the gate insulating film32are sequentially etched by using a mask pattern (not shown), which covers part of the substrate where a gate electrode will be formed, thereby forming a gate electrode34out of the SiGe layer33over the silicon substrate31with the gate insulating film32interposed between them as shown in FIG.6C.

In the third embodiment, after the SiGe layer33was formed and until boron ions have been implanted into the SiGe layer33, no process steps requiring annealing are carried out to keep the SiGe layer33amorphous. Thus it is possible to prevent the boron atoms, existing in the SiGe layer33, from penetrating into the silicon substrate31or the boron ions from being implanted too deep. After the boron ions have been implanted into the SiGe layer33, however, the SiGe layer33will be polycrystalline in the end because the SiGe layer33will be annealed in the process step of depositing an interlevel dielectric film on the gate electrode34, for example.

As described above, according to the third embodiment, an SiGe layer33in an amorphous state is deposited over a silicon substrate31with a gate insulating film32interposed between them. Then, boron ions are implanted into the SiGe layer33. Thereafter, the SiGe layer33is patterned to form a gate electrode34. Thus, the boron ions are implanted into the SiGe layer33in the amorphous state; the boron ions can be implanted sufficiently shallow while the penetration of the boron atoms into the silicon substrate31, which is usually caused by a channeling phenomenon, is suppressible. Accordingly, it is possible to prevent the boron atoms, with which the SiGe layer33for the gate electrode34has been doped, from permeating into the silicon substrate31even if the SiGe layer33is subsequently annealed, for example. As a result, any variation in device characteristics, which might result from a change in dopant concentration in the silicon substrate31, is suppressible. Also, the SiGe layer33in the amorphous state has a better surface morphology than an SiGe layer33in a polycrystalline state. Accordingly, the SiGe layer33has a good surface morphology near the interface with the gate insulating film32. Thus, the breakdown strength of the gate insulating film32improves. Further, the gate electrode34is made of the SiGe layer33alone. Thus, the process steps of forming the gate electrode34can be simplified as compared to forming a gate electrode with a multilayer structure, and the gate electrode34can also have its thickness reduced to e.g., 100 nm or less.

Further, according to the third embodiment, the SiGe layer33for the gate electrode34is doped with boron, so the Vt controllability of the gate electrode34improves.

Also, according to the third embodiment, the boron atoms in the SiGe layer33are activated at a higher rate than in a normal polysilicon film. Thus the boron atoms will even less likely permeate the silicon substrate31.

Although boron ions are implanted into the SiGe layer33in the third embodiment, phosphorus ions may also be implanted instead (e.g., at an acceleration voltage of 10 keV and at a dose of 5×1015/cm2). Or boron and phosphorus ions may be both implanted at a time. Also, instead of doping the SiGe layer33with boron or phosphorus, for example, by an ion implantation process after the SiGe layer33has been deposited, the SiGe layer33containing boron or phosphorous, for example, may be deposited by supplying not only Si and Ge source gases but also a gas containing boron or phosphorus, for example, (e.g., B2H6gas) during the deposition process thereof. Or the SiGe layer33may also be doped with boron or phosphorus, for example, by thermally diffusing PH3, for example, after the SiGe layer33has been deposited.

Also, in the third embodiment, the process step of doping the SiGe layer33with boron, for example, may be omitted. Specifically, the bandgap of the SiGe layer33for the gate electrode34can be changed by controlling the Ge concentration in the SiGe layer33. Accordingly, the Vt controllability of the gate electrode34can be improved without doping the SiGe layer33with boron, for example. As a result, even in applying this embodiment to forming a dual-gate CMOS device, there is no concern about the permeation of any dopant, e.g., boron. Further, in that case, the SiGe layer33does not have to be deposited in an amorphous state, nor does the SiGe layer33have to be kept amorphous until a dopant such as boron has been introduced.

Also, in the third embodiment, the SiGe layer33may have a lower Ge concentration near the lower surface thereof as compared to the other part thereof by changing the mixture ratio of Si and Ge source gases with time in the process step of depositing the SiGe layer33. Then, it is possible to prevent the gate insulating film32from decreasing its breakdown strength or changing its characteristics while suppressing decrease in the Vt controllability of the gate electrode34.

Also, in the third embodiment, an upper silicon layer may be formed on the SiGe layer33for the gate electrode34and a lower silicon layer may be formed under the SiGe layer33for the gate electrode34.

Modified Example of Embodiment 3

Hereinafter, a semiconductor device and a method for fabricating the device in accordance with a modified example of the third embodiment will be described with reference to the accompanying drawings.

Unlike the third embodiment, the method of this modified example further includes the step of depositing a silicon nitride film over a gate electrode34after the gate electrode34has been formed.

FIGS. 7A through 7Eare cross-sectional views corresponding to respective process steps for fabricating a semiconductor device in accordance with this modified example.

First, as shown inFIG. 7A, a gate insulating film32is deposited to a thickness of about 3 nm, for example, on a silicon substrate31of a conductivity type as in the process step shown inFIG. 6Afor the third embodiment.

Then, as shown inFIG. 7B, an SiGe layer33in an amorphous state is deposited to a thickness of about 100 nm, for example, on the gate insulating film32by an LPCVD process with Si and Ge source gases supplied at a temperature of about 500° C. or less as in the process step shown inFIG. 6Bfor the third embodiment. In this process step, the Ge concentration in the SiGe layer33is controllable by changing the mixture ratio of the Si and Ge source gases. Specifically, in this modified example, the Ge concentration in the SiGe layer33is set to about 20%. Then, boron ions are implanted into the SiGe layer33at an acceleration voltage of 5 keV and at a dose of 1×1015/cm2.

Next, as in the third embodiment, the SiGe layer33and the gate insulating film32are sequentially etched by using a mask pattern (not shown), which covers part of the substrate where a gate electrode will be formed, thereby forming a gate electrode34out of the SiGe layer33over the silicon substrate31with the gate insulating film32interposed between them as shown in FIG.7C. Then, the silicon substrate31is doped with a dopant by performing an ion implantation process, for example, using the gate electrode34as a mask, thereby forming a doped layer35to be source/drain regions.

Subsequently, as shown inFIG. 7D, a silicon dioxide film36is deposited to a thickness of about 50 nm, for example, over the silicon substrate31as well as over the gate electrode34. Then, as shown inFIG. 7E, a silicon nitride film37is deposited to a thickness of about 100 nm, for example, over the silicon dioxide film36.

Next, although not shown, an interlevel dielectric film is deposited over the silicon nitride film37. Then contacts are formed through the silicon dioxide film36, silicon nitride film37and interlevel dielectric film to connect interconnects, which will be formed on the interlevel dielectric film, to the doped layer35. In this case, the silicon nitride film37acts as an etch stopper in the process step of etching the interlevel dielectric film to form contact holes.

According to the modified example of the third embodiment, the following effects are attainable in addition to the effects of the third embodiment.

Normally, if a gate electrode doped with boron is formed, a silicon nitride film is deposited over the gate electrode and then the substrate is annealed (e.g., by an annealing process required to deposit an interlevel dielectric film), the boron atoms existing in the gate electrode permeate the semiconductor substrate more noticeably as compared to a situation where the annealing is carried out without depositing the silicon nitride film.

In contrast, according to this modified example, boron ions are implanted into the SiGe layer33in the amorphous state; the boron ions can be implanted sufficiently shallow while the penetration of the boron atoms into the silicon substrate31, which is usually caused by a channeling phenomenon, is suppressible. Accordingly, even if the silicon nitride film37is deposited over the gate electrode34made of the SiGe layer33, the boron atoms existing in the gate electrode34will not permeate the silicon substrate31during the subsequent annealing process.

In this modified example, the silicon nitride film37is used as a stopper in etching the interlevel dielectric film deposited on the silicon nitride film37. Alternatively, a sidewall may be formed out of the silicon nitride film37on the side faces of the gate electrode34. Specifically, in the process step shown inFIG. 7E, the silicon nitride film37is deposited over the gate electrode34with the silicon dioxide film36interposed between them. Then, as shown inFIG. 8, the silicon nitride film37may be etched back to form a sidewall37A out of the silicon nitride film37on the side faces of the gate electrode34with the silicon dioxide film36interposed between them. Then, an MOS transistor having an LDD (lightly doped drain) structure can be formed.

Also, in this modified example, the ion implantation process step for doping the SiGe layer33with boron and the ion implantation process step for forming the doped layer35are carried out separately. Alternatively, these process steps may be carried out at a time after the gate electrode34has been formed.

Hereinafter, a semiconductor device and a method for fabricating the device in accordance with a fourth embodiment of the present invention will be described with reference to the accompanying drawings.

FIGS. 9A through 9Eare cross-sectional views corresponding to respective process steps for fabricating a semi-conductor device in accordance with the fourth embodiment.

First, as shown inFIG. 9A, a gate insulating film42is deposited to a thickness of about 3 nm, for example, on a silicon substrate41of a conductivity type.

Next, as shown inFIG. 9B, an SiGe layer43in an amorphous state is deposited to a thickness of about 100 nm, for example, on the gate insulating film42by an LPCVD process with Si and Ge source gases supplied at a temperature of about 500° C. or less. In this process step, the Ge concentration in the SiGe layer43is controllable by changing the mixture ratio of the Si and Ge source gases. Specifically, in the fourth embodiment, the Ge concentration in the SiGe layer43is set to about 20%. Then, boron ions are implanted into the SiGe layer43at an acceleration voltage of 5 keV and at a dose of 1×1015/cm2.

Subsequently, as shown inFIG. 9C, a metal layer44of tungsten, for example, is deposited to a thickness of about 50 nm, for example, on the SiGe layer43. Then, as shown inFIG. 9D, a silicon dioxide film45and a silicon nitride film46are deposited in this order to respective thicknesses of about 50 nm and about 100 nm, for example, on the metal layer44.

Next, the silicon nitride film46and the silicon dioxide film45are sequentially etched by using a resist pattern (not shown), which covers part of the substrate where a gate electrode will be formed. Then, the metal layer44, SiGe layer43and gate insulating film42are sequentially etched by using the patterned silicon nitride and silicon dioxide films46and45as a hard mask, thereby forming a poly-metal gate electrode47consisting of the SiGe and metal layers43and44over the silicon substrate41with the gate insulating film42interposed between them as shown in FIG.9E.

In the fourth embodiment, after the SiGe layer43was formed and until boron ions have been implanted into the SiGe layer43, no process steps requiring annealing are carried out to keep the SiGe layer43amorphous. Thus it is possible to prevent the boron atoms, existing in the SiGe layer43, from penetrating into the silicon substrate41or the boron ions from being implanted too deep. After the boron ions have been implanted into the SiGe layer43, however, the SiGe layer43will be polycrystalline in the end because the SiGe layer43will be annealed in the process step of depositing an interlevel dielectric film over the poly-metal gate electrode47, for example.

As described above, according to the forth embodiment, an SiGe layer43in an amorphous state is deposited over a silicon substrate41with a gate insulating film42interposed between them. Then, after boron ions are implanted into the SiGe layer43, a metal layer44is deposited on the SiGe layer43. Thereafter, the SiGe and metal layers43and44are patterned to form a poly-metal gate electrode47. Thus, the boron ions are implanted into the SiGe layer43in the amorphous state; the boron ions can be implanted sufficiently shallow while the penetration of the boron atoms into the silicon substrate41, which is usually caused by a channeling phenomenon, is suppressible. Accordingly, it is possible to prevent the boron atoms, with which the SiGe layer43for the poly-metal gate electrode47has been doped, from permeating the silicon substrate41even if the SiGe layer43is subsequently annealed, for example. As a result, any variation in device characteristics, which might result from a change in dopant concentration in the silicon substrate41, is suppressible. Also, the SiGe layer43in the amorphous state has a better surface morphology than an SiGe layer43in a polycrystalline state. Accordingly, the SiGe layer43has a good surface morphology near the interface with the gate insulating film42. Thus, the breakdown strength of the gate insulating film42improves.

Further, according to the fourth embodiment, the SiGe layer43for the poly-metal gate electrode47is doped with boron, so the Vt controllability of the poly-metal gate electrode47improves.

Also, according to the forth embodiment, the boron atoms existing in the SiGe layer43are activated at a higher rate than in a normal polysilicon film. Thus the boron atoms will even less likely permeate the silicon substrate41.

Suppose a film is deposited as a material for a gate electrode and doped with boron and then a silicon nitride film is deposited on the film and annealed (e.g., an annealing process required to deposit an interlevel dielectric film after the gate electrode has been formed). In that case, the boron atoms existing in the material film of the gate electrode normally permeate a semiconductor substrate more noticeably as compared to a situation where the annealing is carried out without depositing the silicon nitride film.

In contrast, according to the forth embodiment, boron ions are implanted into the SiGe layer43in an amorphous state; the boron ions can be implanted sufficiently shallow while the penetration of the boron atoms into the silicon substrate41, which is usually caused by a channeling phenomenon, is suppressible. Accordingly, even though the silicon nitride film46is deposited on the poly-metal gate electrode47including the SiGe layer43, the boron atoms existing in the SiGe layer43will not permeate the silicon substrate41during the subsequent annealing process.

Also, according to the forth embodiment, the silicon nitride film46is deposited over the poly-metal gate electrode47including the SiGe layer43with the silicon dioxide film45interposed between them. Thus, the boron atoms, existing in the SiGe layer43, hardly permeate the silicon substrate41even if the SiGe layer43is annealed after that.

Although boron ions are implanted into the SiGe layer43in the forth embodiment, phosphorus ions may also be implanted instead (e.g., at an acceleration voltage of 10 keV and at a dose of 5×1015/cm2). Or boron and phosphorus ions may be both implanted at a time. Also, instead of doping the SiGe layer43with boron or phosphorus, for example, by an ion implantation process after the SiGe layer43has been deposited, the SiGe layer43containing boron or phosphorous, for example, may be deposited by supplying not only Si and Ge source gases but also a gas containing boron or phosphorus, for example, (e.g., B2H6gas) during the deposition process thereof. Or the SiGe layer43may also be doped with boron or phosphorus, for example, by thermally diffusing PH3, for example, after the SiGe layer43has been deposited.

Also, in the forth embodiment, the process step of doping the SiGe layer43with boron, for example, may be omitted. Specifically, the bandgap of the SiGe layer43for the poly-metal gate electrode47can be changed by controlling the Ge concentration in the SiGe layer43. Accordingly, the Vt controllability of the poly-metal gate electrode47can be improved without doping the SiGe layer43with boron, for example. As a result, even in applying this embodiment to forming a dual-gate CMOS device, there is no concern about the permeation of any dopant, e.g., boron. Further, in that case, the SiGe layer43does not have to be deposited in an amorphous state, nor does the SiGe layer43have to be kept amorphous until a dopant such as boron has been introduced.

Also, in the forth embodiment, the SiGe layer43may have a lower Ge concentration near the lower surface thereof as compared to the other part thereof by changing the mixture ratio of Si and Ge source gases with time in the process step of depositing the SiGe layer43. Then, it is possible to prevent the gate insulating film42from decreasing its breakdown strength or changing its characteristics while suppressing decrease in the Vt controllability of the poly-metal gate electrode47.

Also, in the forth embodiment, an upper silicon layer may be formed between the SiGe and metal layers43and44for the poly-metal gate electrode47and a lower silicon layer may be formed under the SiGe layer43for the poly-metal gate electrode47.

Further, in the forth embodiment, the silicon dioxide film45(with a thickness of about 50 nm, for example) and the silicon nitride film46(with a thickness of about 100 nm, for example) are deposited on the metal layer44. Optionally, only the silicon nitride film46(with a thickness of about 150 nm, for example) may be deposited on the metal layer44.

Hereinafter, a semiconductor device and a method for fabricating the device in accordance with a fifth embodiment of the present invention will be described with reference to the accompanying drawings.

This embodiment relates to a method for forming a dual-gate CMOS device by one of the semiconductor device fabricating methods of the first through forth embodiments.

FIGS. 10A and 10Bare cross-sectional views corresponding to respective process steps for fabricating a semiconductor device in accordance with the fifth embodiment.

First, as shown inFIG. 10A, an n-type semiconductor region51aand a p-type semiconductor region51bare defined in the surface of a silicon substrate51. The n- and p-type semiconductor regions51aand51bare electrically isolated from each other by an isolation52.

Then, as shown inFIG. 10B, a p+gate electrode54ais formed over the n-type semiconductor region51aand an n+gate electrode54bis formed over the p-type semiconductor region51b, in accordance with one of the methods of the first through forth embodiments. A gate insulating film53is interposed between the p+gate electrode54aand the n-type semiconductor region51aand between the n+gate electrode54band the p-type semiconductor region51b. The p+gate electrode54aincludes an SiGe layer doped with a p-type dopant such as boron. The n+gate electrode54bincludes an SiGe layer doped with an n-type dopant such as phosphorous.

Subsequently, although not shown, a p-type doped layer is formed as p-type source/drain regions in the n-type semiconductor region51aand an n-type doped layer is formed as n-type source/drain regions in the p-type semiconductor region51b, thereby forming a dual-gate CMOS device in which p- and n-channel MOSFETs are disposed side by side.

In forming a dual-gate CMOS device, boron atoms introduced into a p+gate electrode for a p-channel MOSFET in the dual-gate CMOS device are apt to permeate a semiconductor substrate.

In contrast, according to the fifth embodiment, the p+gate electrode54afor the p-channel MOSFET of the dual-gate CMOS device is formed by one of the methods of the first through fourth embodiments. Thus, a dopant such as boron, with which the p+gate electrode54ahas been doped, hardly permeates the silicon substrate51. Accordingly, any variation in device characteristics, which might result from a change in dopant concentration in the silicon substrate51, is suppressible.

Likewise, according to the fifth embodiment, the n+gate electrode54bfor the n-channel MOSFET of the dual-gate CMOS device is also formed by one of the methods of the first through fourth embodiments. Thus, a dopant such as phosphorous, with which the n+gate electrode54bhas been doped, hardly permeates the silicon substrate51, either. Accordingly, any variation in device characteristics, which might result from a change in dopant concentration in the silicon substrate51, is also suppressible.

It should be noted that the process step of doping the SiGe layer of the p+gate electrode54awith boron, for example, may be omitted in the fifth embodiment. Specifically, the bandgap of the SiGe layer can be changed by controlling the Ge concentration in the SiGe layer. Accordingly, the Vt controllability of the p+gate electrode54acan be improved without doping the SiGe layer with boron, for example. Similarly, in the fifth embodiment, the process step of doping the SiGe layer of the n+gate electrode54bwith phosphorus, for example, may also be omitted. That is to say, according to the fifth embodiment, the p+or n+gate electrode54aor54bdoes not have to be doped with a dopant. Thus, just by controlling the Ge concentration in the SiGe layer for the p+or n+gate electrode54aor54b, it is possible to form a dual-gate CMOS device easily while preventing the penetration or permeation of the dopant into the silicon substrate51.

In the fifth embodiment, the p+and n+gate electrodes54aand54bare both formed by one of the methods of the first through fourth embodiments. Alternatively, either the p+or n+gate electrode54aor54bmay be formed by one of the methods of the first through fourth embodiments.