Device almost last embedded device structure and method of manufacturing thereof

An electronics package is disclosed that comprises a multilayer interconnect structure including a plurality of insulating substrate layers each having a plurality of microvias formed therein, a plurality of conductive wiring layers positioned on the plurality of insulating substrate layers, and a plurality of conductive microvias in the plurality of microvias to, wherein a bottom wiring layer includes a plurality of first terminal pads that are positioned on a bottom surface of the multilayer interconnect structure. The electronics package also comprises an electrical component coupled to the bottom surface of the multilayer interconnect structure, the electrical component including first I/O pads aligned with the first terminal pads and second I/O pads aligned to regions of the multilayer interconnect structure without first terminal pads. The electronics package further comprises a plurality of conductive through vias extending through the multilayer interconnect structure and electrically connected to the plurality of second I/O pads.

BACKGROUND OF THE INVENTION

Embodiments of the invention relate generally to semiconductor device packages or electronics packages and to a device-almost last method of manufacturing thereof. An embedded device module with a complex semiconductor device or chip (with hundreds or thousands of I/O terminals) is embedded under a prefabricated multilayer interconnect structure, with the semiconductor device attached to the prefabricated multilayer interconnect structure after it is tested thereby avoiding committing the semiconductor device to an interconnect structure with a potential defect. Two different types of interconnects are used to connect the device to the interconnect structure—a high density, moderate performance connection for signal pads and a high performance, moderate density connection for high performance controls, power, and ground pads. Minimal interconnect processing is performed after the semiconductor device is attached, thereby increasing yield and lowering costs while attaining the high electrical performance inherent with an embedded device structure.

State of the art electronics packaging covers a wide range of methods, structures, and approaches from wire bond modules to flip chip modules and to embedded device/chip modules. Wire bonded modules are a mature packaging approach that is low cost but has poor electrical performance and has limited input/output (I/O) capability. These modules use wires bonded to device pads to connect the top I/O pads of semiconductor devices to an interconnect structure such as a multilayered organic or ceramic substrate with multiple dielectric and patterned metal layers. An exemplary construction of a prior art wire bond electronics package10is illustrated inFIG. 1with two semiconductor devices11mounted onto a multilayer substrate13using die attach material15on topside17. Wire bonds21connect die pads23located on the active surface25of semiconductor devices11to conductive pads27on the topside17of multilayer substrate13. Molding resin29encapsulates semiconductor devices11, wire bonds21, and exposed portions of multilayer substrate13. Multilayer substrate13has backside terminals31that are connected to conductive pads27by through holes33. Multilayer substrate13may have multiple dielectric layers35, multiple buried conductive layers37, and multiple layer to layer vias39. Wire bonds have inherently high inductance and series resistance, current crowding on the bond pads, and can cause microcracking within the semiconductor devices11near bonding sites. They are limited to I/O pads in one to three rows of die pads23located on the perimeter edges of the devices11and typically are limited to a few hundred I/Os.

Prior art flip chip modules use an array of terminal pads dispersed over the full surface of the semiconductor device to interconnect the device I/Os to a package or substrate. The device I/O pads can be in a fully populated array of pads or in a partially depopulated array of pads. Solder bumps are formed on each pad forming an array of solder spheres that are used to flip attach the device onto a package base, substrate, or board that has a matching array of pads. Although the pitch of the solder pads is larger than the pitch of wire bond pads, the array pads utilize the whole device surface and can contain 5× to 20× more pads than a wire bonded device. The solder bumps have larger cross-sections than wire bonds (>20×) and have a much shorter electrical path (>10×) than wire bonds and therefore have higher current carrying capability (>5×) and higher frequency capability (5×). A general construction of a prior art flip chip electronic package40is illustrated inFIG. 2with two semiconductor devices11attached to multilayer substrate13. Flip chip solder bumps41are applied to conductive pads27on multilayer substrate13and coupled to die pads23. Molding resin29encapsulates the semiconductor devices11. While flip chip modules such as that illustrated inFIG. 2provide some advantages over wire bond technology, solder has poor electrical conductivity and is susceptible to both solder fatigue and electro-migration failures and the flipped chip has a very poor thermal cooling pathway.

Embedded device or chip modules and Fan-Out Wafer Level Packages (WLPs) are packaging approaches that address the limitations of wire bond and flip chip packages by eliminating wire bonds and solder bumps and replacing them with direct metallization contacts. Embedded device modules and Fan-Out WLPs are moving into the mainstream of microelectronics packaging for low and mid-complexity semiconductor devices, with these approaches being driven by the latest portable electronics devices, such as smart phones, as each new generation of smart phones puts more function into a smaller space with the requirement that the electronics consume less power. Embedded device modules combine multiple electronic devices, such as semiconductor devices or chips, capacitors, resistors and/or inductors in a common package using an interconnect structure that overlies the components and provides direct metallurgical interconnect to component terminals that minimizes interconnect parasitics. Combining multiple electronic devices in the same embedded device module with its lower parasitics provides higher electrical performance, faster operation, and lower power dissipation, while reducing the function's footprint saving board space. Fan-Out WLPs fan out the semiconductor device I/O terminals from the restricted area of the device surface to a larger footprint by fabricating an overlay interconnect structure on the surface of the semiconductor device that extends over an off-device molded region. This allows device I/O pitch to be relaxed to a larger I/O terminal pitch that facilitates attachment to a printed circuit board (PCB). The larger pitch reduces PCB complexity and lowers its costs and increases its yields. It also increases assembly yields, further lowering costs. Fan-Out WLPs can be used as stand-alone surface mounted devices or they can include feed throughs that enable incorporation into Package-on-Package (POP) assembly.

A general construction of a prior art embedded device electronic package50is illustrated inFIG. 3with two semiconductor devices11attached to multilayer overlay insulating substrate structure51. Multilayer overlay insulating substrate structure51has multiple insulating substrate layers53and multiple wiring layers55. Structure51also includes lower overlay insulating substrate layer57with first microvia connections59extending through lower overlay insulating substrate layer57to die pads23of semiconductor devices11and connect them to buried wiring layer61. An upper overlay insulating substrate layer63with second microvia connections65extends through the upper overlay insulating substrate layer63to buried wiring layer61and connecting to topside wiring layer67. Molding resin29encapsulates the semiconductor devices11. The multilayer overlay insulating substrate structure51with its direct metallization to die pads23through first microvia connections59eliminate 90% of the interconnect parasitics associated with wire bonded modules and flip chip modules. Most importantly, interconnect structure defects such as wiring shorts and opens and high resistance or open microvia would cause the scrapping of good semiconductor device that are attached to a die site that had an interconnect defect.

A general construction of a prior art Fan-Out Wafer Level Package (WLP)70is depicted inFIG. 4with one semiconductor device11molded into resin material29. An overlay insulating substrate structure54lies over the active surface25of the semiconductor device11and the top surface73of resin material29. Generally, the process of forming the Fan-Out WLP70starts with embedding semiconductor device11in resin material29with top surface73of resin material29generally level with active surface25of semiconductor device11. This processing takes place in large circular or rectangular panels in a multi-up configuration. Following this encapsulation, a first overlay insulating substrate layer57is applied over the active surface25of semiconductor device11and the top surface73of resin material29. First microvias75are formed through the first overlay insulating substrate layer57to die pads23and optionally, to feed through conductors77that may be embedded in the resin material29. First wiring layer61is applied to the first overlay insulating substrate layer57and into first microvias75and forming first microvia connections59to die pads23and optionally, to feed through conductors77. Second overlay insulating substrate layer63is applied to first overlay insulating substrate layer57and first wiring layer61. Second microvias79are formed in the second overlay insulating substrate layer63to portions of first wiring layer61. Top side wiring layer67is applied to the second overlay insulating substrate layer63and into second microvias79and forming second microvia connections65to exposed portions of first wiring layer61. Additional overlay insulating substrate layers and wiring layers can be applied for as needed for more complex, higher I/O pad count devices. Optionally, the molding resin29can be back ground to planarize and/or thin the module.

Fan-Out WLP70, with its direct metallization to die pads23through first microvia connections59eliminate 90% of the interconnect parasitics associated with wire bonded fan-out modules and flip chip fan-out modules. The main disadvantages of the Fan-Out WLP is that interconnect defects that cause the Fan-Out WLP overlay structure to be defective, such as for example interconnect shorts or opens or via opens, causes the costly complex semiconductor device to be scrapped along with the interconnect structure, increasing the effective cost of the packaging process.

Despite the advantages of an embedded device module or Fan-Out WLP construction, these construction techniques are more complex, less mature, and higher cost than wire bond and flip chip approaches. One major disadvantage of the embedded device module construction versus the wire bond or flip chip modules is that defects in the overlay interconnect structure can lead to the loss of a complex and costly semiconductor device since the device is committed to the module prior to the fabrication of the build-up interconnect structure. Prior art approaches to address the yield issues associated with embedded device module construction have had limited effects and/or are not applicable to high performance semiconductor devices with high I/O count and high power and ground current requirements.

Accordingly, it would be desirable to provide an electronics packaging technology that permits construction of a high performance, high I/O count microelectronics package, with high interconnect performance and high interconnect and assembly yield.

BRIEF DESCRIPTION OF THE INVENTION

In accordance with one aspect of the invention, an electronics package comprises a multilayer interconnect structure including a plurality of insulating substrate layers, a plurality of conductive wiring layers positioned on the plurality of insulating substrate layers, with each of the plurality of insulating substrate layers having one or more of the plurality of conductive wiring layers positioned thereon, and a plurality of conductive microvias extending through the plurality of insulating substrate layers to electrically connect the plurality of conductive wiring layers, wherein a bottom wiring layer of the plurality of conductive wiring layers includes a plurality of first terminal pads that are positioned on a bottom surface of the multilayer interconnect structure. The electronics package also comprises an electrical component coupled to the bottom surface of the multilayer interconnect structure, the electrical component including a plurality of first input/output (I/O) pads aligned with the plurality of first terminal pads and a plurality of second I/O pads aligned to regions of the multilayer interconnect structure without first terminal pads. The electronics package further comprises a plurality of conductive through vias extending through the multilayer interconnect structure and electrically connected to the plurality of second I/O pads.

In accordance with another aspect of the invention, a method of manufacturing an electronics package includes providing a pre-fabricated multilayer interconnect structure comprising a top surface and a bottom surface, with the multilayer interconnect structure including a plurality of insulating substrate layers each having a plurality of microvias formed therein and a plurality of conductor layers positioned on the plurality of insulating substrate layers and in the plurality of microvias, the plurality of conductor layers comprising a plurality of first terminal pads positioned on the bottom surface of the multilayer interconnect structure. The method also includes coupling an active surface of a semiconductor device to the bottom surface of the multilayer interconnect structure such that a plurality of semiconductor device first input/output (I/O) pads on the active surface are aligned to the plurality of first terminal pads, forming a plurality of through vias that extend from the top surface of the multilayer interconnect structure down to a plurality of semiconductor device second I/O pads on the active surface of the semiconductor device, and forming conductive through vias in the plurality of through vias that contact the plurality of semiconductor device second I/O pads.

In accordance with yet another aspect of the invention, an electronics package comprises a multilayer interconnect structure including a plurality of insulating substrate layers each comprising a plurality of microvias formed therein, a plurality of conductive wiring layers positioned on the plurality of insulating substrate layers such that each of the plurality of insulating substrate layers has one or more conductive wiring layers positioned thereon, and a plurality of conductive microvias in the plurality of microvias to electrically connect the plurality of conductive wiring layers, wherein the plurality of conductive wiring layers and the plurality of conductive microvias are positioned in a perimeter region of the multilayer interconnect structure that surrounds a center region of the multilayer interconnect structure. The electronics package also comprises a semiconductor device attached to a bottom surface of the multilayer interconnect structure, the semiconductor device comprising a plurality of first input/output (I/O) pads aligned with the perimeter region and a plurality of second I/O pads aligned with the center region. The electronics package further comprises a plurality of conductive through vias extending through the multilayer interconnect structure in the center region and electrically connected to the plurality of second I/O pads.

In accordance with still another aspect of the invention, a reconfigured semiconductor device includes a semiconductor device having a plurality of device I/O pads on an active surface thereof, the plurality of device I/O pads comprising first device I/O pads and second device I/O pads. The reconfigured semiconductor device also includes a first redistribution layer on the active surface, the first redistribution layer comprising a first insulating substrate layer, a first plurality of vias formed through the first insulating substrate layer to the plurality of device I/O pads, and a first wiring layer overlying the first insulating substrate layer and extending into the plurality of vias down onto portions of the plurality of device I/O pads, the first wiring layer comprising a plurality of first contact pads connected to the plurality of device I/O pads. The reconfigured semiconductor device further includes an upper redistribution layer overlying the first redistribution layer and comprising an upper insulating substrate layer, a plurality of vias formed through the upper insulating substrate layer to a plurality of contact pads on a wiring layer below the upper insulating substrate layer that comprises the first wiring layer or an additional wiring layer between the first redistribution layer and the upper redistribution layer, and an upper wiring layer overlying the upper insulating substrate layer and extending into the plurality of vias and onto portions of the plurality contact pads on the wiring layer below the upper insulating substrate layer, the upper wiring layer comprising a plurality of upper contact pads connected to a plurality of contact pads on the wiring layer below the upper insulating substrate layer. The upper contact pads comprise first reconfigured device I/O pads and second reconfigured device I/O pads, with each of a plurality of the first reconfigured device I/O pads electrically connected to a single respective first device I/O pad and each of a plurality of the second reconfigured device I/O pads electrically connected to at least two respective second device I/O pads.

In accordance with still another aspect of the invention, an electronics package includes a multilayer interconnect structure comprising a plurality of insulating substrate layers each having a plurality of microvias formed therein and a plurality of conductor layers positioned on the plurality of insulating substrate layers and in the plurality of microvias, wherein the plurality of conductor layers comprises buried conductive via connections embedded in the multilayer interconnect structure. The electronics package also includes an electrical component attached to the multilayer interconnect structure and aligned with the buried conductive via connections, the electrical component comprising a plurality of input/output (I/O) pads. The electronics package further includes a plurality of conductive through vias extending through the multilayer interconnect structure and forming a direct electrical and physical connection with at least a portion of the plurality of I/O pads, wherein the buried conductive via connections are in physical contact with one or more of the plurality of conductive through vias.

In accordance with still another aspect of the invention, an electronics package includes a multilayer interconnect structure comprising a plurality of insulating substrate layers and a plurality of conductor layers positioned on the plurality of insulating substrate layers and extending through a plurality of microvias formed therein. The electronics package also includes an electrical component comprising a plurality of input/output (I/O) pads electrically coupled to the plurality of conductor layers and a plurality of conductive through vias extending through a least two insulating substrate layers of the plurality of insulating substrate layers and electrically connected to at least a portion of the plurality of I/O pads. The plurality of conductor layers further includes a first conductor layer including a ground plane buried in the multilayer interconnect structure, the ground plane forming a direct electrical and physical connection with a respective conductive through via that is electrically connected to a ground I/O pad of the plurality of I/O pads, and includes a second conductor layer including a power plane buried in the multilayer interconnect structure, the power plane forming a direct electrical and physical connection with a respective conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.

In accordance with still another aspect of the invention, an electronics package includes a multilayer interconnect structure comprising a plurality of insulating substrate layers and a plurality of conductor layers positioned on the plurality of insulating substrate layers and extending through a plurality of microvias formed therein. The electronics package also includes an electrical component comprising a plurality of input/output (I/O) pads electrically coupled to the plurality of conductor layers and a plurality of conductive through vias extending through at least two insulating substrate layers of the plurality of insulating substrate layers and electrically connected to at least a portion of the plurality of I/O pads. The plurality of conductor layers includes a first conductor layer comprising a partial ground plane buried in the multilayer interconnect structure and forming a direct electrical and physical connection with a respective conductive through via that is electrically connected to a ground I/O pad of the plurality of I/O pads and a partial power plane buried in the multilayer interconnect structure and forming a direct electrical and physical connection with a respective conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.

In accordance with still another aspect of the invention, a method of manufacturing an electronics package includes providing a multilayer interconnect structure comprising a plurality of insulating substrate layers each having a plurality of microvias formed therein and a plurality of conductor layers positioned on the plurality of insulating substrate layers and in the plurality of microvias, at least one of the plurality of conductor layers including at least one buried conductive via aperture embedded in the multilayer interconnect structure. The method also includes attaching an active surface of an electrical component to the interconnect structure, forming at least one shoot through via that extends through the at least one buried conductive via aperture down to at least one I/O pad of a plurality of I/O pads on the active surface of the electrical component, and forming a conductive through via in each of the at least one shoot through vias that physically contacts a respective buried conductive via aperture to form at least one buried conductive via connection and that physically contacts a respective I/O pad of the plurality of I/O pads.

In accordance with still another aspect of the invention, an electronics package includes a plurality of insulating substrate layers each having a plurality of microvias formed therein, a plurality of conductor layers positioned on the plurality of insulating substrate layers and in the plurality of microvias, and a plurality of conductive through vias extending through at least two of the plurality of insulating substrate layers. The plurality of conductor layers comprises includes a first conductor layer including a ground plane buried in the electronics package, the ground plane forming a direct electrical and physical connection with a first conductive through via of the plurality of conductive through vias and a second conductor layer including a power plane buried in the electronics package, the power plane forming a direct electrical and physical connection with a second conductive through via of the plurality of conductive through vias.

These and other advantages and features will be more readily understood from the following detailed description of preferred embodiments of the invention that is provided in connection with the accompanying drawings.

DETAILED DESCRIPTION

Embodiments of the present invention provide packaging structures with a complex semiconductor device (i.e., “chip”) embedded within a molded substrate with a complex interconnect structure overlying and electrically connected to the active surface of the device and that is done with a high yielding process. Specifically, a complex semiconductor device that was been directly attached and electrically interconnected to a multilayer interconnect structure with minimal interconnect processing occurring after the complex semiconductor device is attached to the multilayer interconnect structure. Other embodiments of this invention provide methods for fabricating an embedded device/chip module with a complex semiconductor device that is attached to a pre-fabricated and fully tested multilayer interconnect structure with minimized number of processing steps performed after the complex semiconductor device is attached to the multilayer interconnect structure.

As used herein, the term “complex semiconductor device” refers to a semiconductor die or chip that performs specific functions, such as a microprocessor, a controller, a graphics processor, or an applications processor, as non-limiting examples. These complex semiconductor devices are characterized by high gate count (generally 10's or 100's of millions of gates), high clock rates (1 Gigahertz or more) and high I/O count (100's to 1000's or more). Typically, these complex semiconductor devices contain control lines, address busses, data busses, and clock signals, as well as power and ground pads. On these complex semiconductor devices, generally 50% to 80% or more of their I/O's are power or ground pads in order to minimize the parasitic resistances and reduce voltage drops in the power and ground connections.

Referring now toFIG. 5, a multilayer interconnect structure100is illustrated to facilitate understanding of the construction thereof, according to embodiment of the invention. Multilayer interconnect structure100is constructed of a plurality of insulating substrate layers101,103,105and a plurality of conductor layers102,104,106that provide electrical connections through the insulating substrate layers101,103,105and electrical connections to the multilayer interconnect structure100. The plurality of conductor layers102,104,106are comprised of a plurality of wiring layers109,111,113,115(or “traces”) and a plurality of conductive microvias117,119,121. In the illustrated embodiment, multilayer interconnect structure100is composed of three insulating substrate layers101,103,105(i.e., core layer101, upper layer103, and lower layer105), four conductive wiring layers109,111,113,115(i.e., first patterned wiring layer109, second patterned wiring layer111, upper patterned wiring layer113, and bottom patterned wiring layer115), and three sets of conductive microvias117,119,121. Alternative embodiments of multilayer interconnect structure100may have more or less wiring layers, insulating layers, and conductive microvias than illustrated inFIG. 5based on the complexity of the circuit function being implemented.

According to various embodiments, insulating substrate layers101,103,105may be provided in the form of insulating films or dielectric substrates, such as for example a Kapton® laminate flex, an organic film, or substrate comprising polyimide, epoxy, BT resin, although other suitable materials may also be employed, such as Ultem®, polytetrafluoroethylene (PTFE), or another polymer film, such as a liquid crystal polymer (LCP) or a polyimide substrate, or inorganic substrates such as Si, SiC, AlN, ceramic, or glass, as non-limiting examples. Alternatively, each of insulating substrate layers101,103,105may be provided as an organic film provided with an adhesive layer, a self-bonding film, such as, for example, an epoxy-fiber glass pre-preg, or a liquid dispensed dielectric that is cured in place.

The wiring layers109,111,113,115and/or conductive microvias117,119,121may be composed of one or more electrically conductive materials. In an exemplary embodiment, the wiring layers and conductive vias may be composed of a barrier or adhesion layer, a seed layer, and a relatively thick layer of bulk material that is plated atop the seed and barrier layers achieving the desired conductor layer thickness. In alternative embodiments, the barrier layer and/or the seed layer may be omitted from the wiring layers. The barrier layer, when used, is applied to the respective insulating substrate layer101,103,105prior to application of the seed layer and bulk material. The barrier layer may include titanium or chromium, as non-limiting examples. When used, seed metal layer may be an electrically conductive material such as copper, as one non-limiting example. The layer of bulk material is plated up to achieve the desired thickness of the wiring layers109,111,113,115, with the bulk material portion of each wiring layer including at least one electrically conductive material such as copper, aluminum, gold, silver, nickel, other standard wiring material, or combinations thereof as nonlimiting examples. However, other electrically conducting materials or a combination of metal and a filling agent may be used in other embodiments. In some embodiments the barrier layer may have a thickness in the approximate range of 0.1 to 0.4 microns, the seed metal layer may have a thickness in the approximate range of 1 to 3 microns and the bulk layer may have a thickness in the approximate range of 10 to 100 microns, with it being recognized that other materials at other thicknesses can be used based on design requirements. Alternatively, wiring layers109,111,113,115may be formed of an electrically conductive polymer or formed using inks that contain conductive metal particles.

As depicted inFIG. 5, upper wiring layer113contains upper terminal pads123that are positioned in pre-determined locations to facilitate electrical connections to an additional interconnect layer or layers (not shown) that might be added after a complex semiconductor device (not shown) is attached to multilayer interconnect structure100. Bottom wiring layer115contains a plurality first lower terminal pads125and optionally contains a plurality of second lower terminal pads127, with the first lower terminal pads125and the second lower terminal pads127being provided in a perimeter region128of multilayer interconnect structure100. First lower terminal pads125are positioned to interconnect to signal I/O pads of complex semiconductor device (not shown) that would be attached to multilayer interconnect structure100in assembling a complex microelectronic package or module, as will be explained in greater detail later on. Optional second lower terminal pads127(shown in phantom) are positioned to interconnect to lower I/O structures, such as pins, through molding vias, or a substrate structure that could be incorporated into a complex microelectronic package or module. As will be explained in greater detail below, second lower terminal pads127are formed/positioned on multilayer interconnect structure100so as to be external to or outside of a footprint of the complex semiconductor device that is to be joined to the multilayer interconnect structure100.

As further depicted inFIG. 5, a center region129of multilayer interconnect structure100does not have wiring features or upper terminal pads123and does not have any first lower terminal pads125or second lower terminal pads127. Center region129is preferably reserved for the formation of vias that would connect to I/O pads of a complex semiconductor device after it is attached to multilayer interconnect structure100. Depending upon the design requirements of a specific complex microelectronic package and the specific I/O pad configuration of a complex semiconductor device, interconnect wiring and layer-to-layer microvias could be incorporated within the center region129providing additional circuit functionality. It should be noted that many if not most complex semiconductor devices such as microprocessors, ASICs, and application processors are designed for flip chip attach and have all of their digital I/O pads located in the perimeter region of the chip and reserve the central region of the chip for power and ground I/O pads to facilitate escape routing in the mating substrate.

According to embodiments of the invention, multilayer interconnect structure100can be fabricated by any standard industry process used to fabricate a multilayer flex circuit. Preferably, multilayer interconnect structure100is fabricated by applying a conductor layer104onto/adjacent to the topside of core insulating substrate layer101. The conductor layer104can be a thin composite seed layer such as, for example, titanium:copper with a thickness of 0.5 to 5 microns, and preferably 1-2 microns. Alternatively, the conductor layer104can be a metal foil bonded to the core insulating substrate layer101. Microvias117are formed through the core insulating substrate layer101exposing portions of the conductor layer104by laser ablation, chemical etch, or plasma etch, for example. Depending on the current carrying requirements of the circuit, microvias117may have a diameter of about 5 to 100 microns, preferably 10 to 25 microns. Microvias117may have diameter outside of this stated range in some embodiments based on alternative design specifications. Conductor layer104is also applied onto/adjacent to the bottom surface of the core insulating substrate layer101, into the microvias117and on exposed portions of the first conductor layer. The conductor layer104is then patterned to form the first patterned wiring layer109and the second patterned wiring layer111, such as by semi-additive, additive, or subtractive processes, for example.

In fabricating multilayer interconnect structure100, the upper insulating substrate layer103and lower insulating substrate layer105are then formed on either side of core insulating substrate layer101. Upper conductive microvias119are formed through upper insulating substrate layer103and lower conductive microvias121are formed through lower insulating substrate layer105in a similar way as the conductive microvias117in core insulating substrate layer101and are formed to portions of first patterned wiring layer109and second patterned wiring layer111, respectively. Conductor layers102,106are then applied onto/adjacent to the upper surface and lower surface, respectively, of upper insulating substrate layer103and lower insulating substrate layer105and into microvias119and121, respectively. The conductor layers102,106have a thickness of about 2 to 50 microns, preferably 5 to 20 microns, based upon the electrical requirements of the circuit. However, the thickness of the conductor layers102,106may fall outside of this range in alternative embodiments. The conductor layers102,106are then patterned to form the upper patterned wiring layer113and the lower patterned wiring layer115, respectively, such as by semi-additive, additive, or subtractive processes, for example. In yet other embodiments, either or both of upper patterned wiring layer113and the lower patterned wiring layer115are formed using a deposition technique such as inkjet printing, screen printing, or dispensing, as non-limiting examples.

Upon completion of such a fabrication process (or a similar fabrication process), a multilayer interconnect structure100may thus be provided as a pre-fabricated interconnect structure that does not require any additional via formation, metallization, etc. The pre-fabricated multilayer interconnect structure100may be fully tested to ensure proper operability/functionality, so as to prevent committing of a semiconductor device to an interconnect structure with a potential defect. Although the multilayer interconnect structure100depicted inFIG. 5contains the die site for only one electrical component, it should be recognized that multilayer interconnect structure100would be formed as a structure containing multiple die sites such as in the form of a large panel containing 10's or 100's of die sites.

Referring now toFIGS. 6-12, a preferred method of forming an embedded electronic module181(FIG. 12) is illustrated according to one embodiment of the invention. As described below, the embedded electronic module181contains a multilayer interconnect structure100overlying a complex semiconductor device131—with microvia-less electrical connections provided to a plurality of signal I/O pads on the complex semiconductor device131and with conductive vias provided that form electrical connections to a plurality of power, ground, and control I/O pads on the complex semiconductor device131. As indicated above, the multilayer interconnect structure100may be provided as a pre-fabricated and pre-tested interconnect structure, so as to avoid committing a high cost complex semiconductor device131to a potentially faulty interconnect structure.

FIG. 6depicts the multilayer interconnect structure100ofFIG. 5after an electrical component131, hereafter referred to as “complex semiconductor device131,” is attached to the outer surface of lower patterned wiring layer115and the bottom side of the lower insulating substrate layer105using an electrically non-conductive component attach material133, thereby forming a first intermediate structure135. According to various embodiments, component attach material133is an electrically insulating material that is applied to surrounding components of the multilayer interconnect structure by spin coating, spray coating, meniscus coating, printing, or in film form. Component attach material133may be a polymeric material (e.g., epoxy, silicone, liquid crystal polymer, or a ceramic, silica, or metal filled polymer) or other organic material as non-limiting examples. In some embodiments, component attach material133is provided on lower insulating layer105in either an uncured or partial cured (i.e., B-stage) form. Alternatively, component attach material133may be applied to the complex semiconductor device131prior to coupling component attach material133to lower insulating layer105.

The complex semiconductor device131has a plurality of perimeter I/O device signal pads137, center I/O device control pads139, center I/O device power pads141, and center I/O device ground pads143. Although complex semiconductor device131is depicted inFIGS. 6-12(and inFIGS. 13-22) as having a small number of I/O pads137,139,141,143, it should be understood that complex semiconductor device131would have hundreds or thousands of I/O pads. The simplified version of complex semiconductor device131is depicted here to better understand the structure of these preferred embodiments. Perimeter I/O device signal pads137are in positions opposite to first lower terminal pads125of multilayer interconnect structure100.

FIG. 7depicts the first intermediate structure135ofFIG. 6after exposed surfaces of complex semiconductor device131and exposed regions of component attach material133are encapsulated with molding resin or encapsulant145, thereby forming a second intermediate structure147. According to an embodiment, molding resin145is an organic resin containing fillers to reduce its Thermal Coefficient of Expansion, which is less than 40 PPM/C or less than 30 PPM/C. Alternatively, molding resin145may be a polymer such as, for example, an epoxy material, a pre-preg material, an inorganic material, a composite dielectric material, or any other electrically insulating organic or inorganic material. Optionally, the outer surface149of molding resin145can be background to expose the back surface151of complex semiconductor device131and, if desired, back grounding can continue into semiconductor device131, thinning it along with thinning the molding resin145. However, with or without backgrinding being performed, molding resin145encapsulates at least a portion of the semiconductor device131, with the sides of the semiconductor device131being fully encapsulated in the molding resin145.

FIG. 8depicts the second intermediate structure147ofFIG. 7after a topside insulating substrate layer153is applied to topside surface155of multilayer interconnect structure100, thereby forming a third intermediate structure157. Topside insulating substrate layer153may be provided in the form of insulating films or dielectric substrates, such as for example a Kapton® laminate flex, an organic film, or substrate comprising polyimide, epoxy, BT resin, although other suitable materials may also be employed, such as Ultem®, polytetrafluoroethylene (PTFE), or another polymer film, such as a liquid crystal polymer (LCP) or a polyimide substrate, or inorganic substrates such as Si, SiC, AlN, ceramic, or glass, as non-limiting examples. Alternatively, topside insulating substrate layer153may be provided as an organic film provided with an adhesive layer, a self-bonding film, such as, for example, an epoxy-fiber glass pre-preg, or a liquid dispensed dielectric that is cured in place.

FIG. 9depicts the third intermediate structure157ofFIG. 8after microvias159are formed in topside insulating substrate layer153to portions of upper patterned wiring layer113and after through vias161are formed through topside insulating substrate layer153, upper insulating substrate layer103, core insulating substrate layer101, lower insulating substrate layer105, and component attach material133, and down to center I/O device control pads139, center I/O device power pads141, and center I/O device ground pads143, thereby forming a fourth intermediate structure163. Microvias159and through vias161can be formed, for example, by laser ablation, chemical etch, or plasma etch.

FIG. 10depicts the fourth intermediate structure163ofFIG. 9after conductive material is applied to microvias159, through vias161, and the outer surface of topside insulating substrate layer153to form conductive microvias165, conductive through vias167, and a patterned wiring layer169(which can alternately be referred to as module contact pads169or topside terminal pads169), thereby forming a fifth intermediate structure171. Conductive material is applied and patterned on topside insulating substrate layer153(to form the wiring layer169), into microvias153and down onto exposed portions of upper patterned wiring layers113, and into through vias163and down onto center I/O device control pads139, center I/O device power pads141, and center I/O device ground pads143of complex semiconductor device131. In an exemplary embodiment, the conductive material may be composed of a barrier or adhesion layer, a seed layer, and a relatively thick layer of bulk material that is plated atop the seed and barrier layers achieving the desired wiring layer thickness. In alternative embodiments, the barrier layer and/or the seed layer may be omitted from the wiring layer. The barrier layer, when used, is applied to the topside insulating substrate layer153prior to application of the seed layer and bulk material. The barrier layer may include titanium or chromium, as non-limiting examples. When used, seed metal layer may be an electrically conductive material such as copper, as one non-limiting example. The layer of bulk material is plated up to achieve the desired thickness of the wiring layer169, with the bulk material portion of each wiring layer including at least one electrically conductive material such as copper, aluminum, gold, silver, nickel, other standard wiring material, or combinations thereof as nonlimiting examples. However, other electrically conducting materials or a combination of metal and a filling agent may be used in other embodiments. In some embodiments the barrier layer may have a thickness in the approximate range of 0.1 to 0.4 microns, the seed metal layer may have a thickness in the approximate range of 1 to 3 microns and the bulk layer may have a thickness in the approximate range of 10 to 100 microns, with it being recognized that other materials at other thicknesses can be used based on design requirements. Alternatively, wiring layer169may be formed of an electrically conductive polymer or formed using inks that contain conductive metal particles.

The conductive material may be applied by one or more of sputtering, evaporation, electroless plating, electroplating, and pulsed plating. The conductive material can then be patterned to form wiring layer169, such as by semi-additive, additive, or subtractive processes, for example. In yet other embodiments, patterned wiring layer169is formed using a deposition technique such as inkjet printing, screen printing, or dispensing, as non-limiting examples.

FIG. 11depicts the fifth intermediate structure171ofFIG. 10after a topside solder mask173is applied to the outer surface of topside insulating substrate layer153and patterned wiring layer169and after topside solder mask173is patterned to form solder mask openings175to selected portions of the wiring layer169, thereby forming a sixth intermediate structure177. Topside solder mask173is preferably an organic resin that is photo-definable and is patterned by exposing the resin to UV light through a mask or through a direct write UV beam.

FIG. 12depicts the sixth intermediate structure177ofFIG. 11after package level inputs/outputs (I/Os)179(such as solder spheres as illustrated inFIG. 12) are disposed onto solder mask openings175on exposed portions of patterned wiring layer169, thereby forming a first embedded electronics module181, according to an embodiment of the invention. It is noted thatFIG. 12also depicts an optional feature of this embodiment, where multiple package level I/Os179are attached to the same interconnected portions of patterned wiring layer169that are tied to I/O device power pads141and tied to I/O device ground pads143, thereby further improving electrical performance by reducing interconnect resistance.

The resulting first embedded electronics module181shown inFIG. 12includes electrical connections between complex semiconductor device131and multilayer interconnect structure100that are a combination of capacitive coupling and conductive coupling connections. A plurality of signal I/Os of complex semiconductor device131represented by perimeter I/O device signal pads137are connected by capacitive coupling to first lower terminal pads125. A plurality of control I/Os of complex semiconductor device131represented by center I/O device control pads139are electrically connected to multilayer interconnect structure100by conductive through vias167. A plurality of power and ground I/Os of complex semiconductor device131represented by center I/O device power pads141and center I/O device ground pads143, respectively, are electrically connected to multilayer interconnect structure100by conductive through vias167.

With regard to the capacitive coupling formed between first lower terminal pads125125and I/O device signal pads137, the capacitive coupling is achieved due to a small amount of electrically non-conductive component attach material133that is present between first lower terminal pads125and I/O device signal pads137that prevents a direct metallic connection therebetween. For example, a thin layer of component attach material133that is approximately 0.5-1.0 micrometers in thickness may be present between first lower terminal pads125and I/O device signal pads137. With regard to the conductive coupling formed between conductive through vias167and I/O device control pads139, I/O device power pads141, and center I/O device ground pads143, the conductive through vias167are constructed as robust conductive vias of increased dimensions and capable of conducting higher current levels as compared to micro vias117,119,121, which is especially desirable for connection to I/O device power pads141and center I/O device ground pads143. Thus, in preferred embodiments, the cross-sectional area of conductive through vias167is at least twice as large as the cross-sectional area of microvias117,119,121, with the cross-sectional areas measured at the midpoints of the conductive through vias167and microvias117,119,121. In an alternative embodiment, the cross-sectional area of conductive through vias167is at least four times as large as the cross-sectional area of microvias117,119,121. In yet another alternative embodiment, the cross-sectional area of conductive through vias167is at least ten times as large as the cross-sectional area of microvias117,119,121.

Referring now toFIGS. 13-15, a preferred method of forming an embedded electronic module is illustrated according to another embodiment of the invention, with the embedded electronic module containing through molding conductive vias191(FIGS. 14 and 15) along with the multilayer interconnect structure100overlying complex semiconductor device131.

FIG. 13depicts the fifth intermediate structure171ofFIG. 10where, instead of next forming the sixth intermediate structure177illustrated inFIG. 11, the fabrication process continues by forming optional through molding openings183from the bottom side185of molding resin145, through component attach material133, and to second lower terminal pads127, thereby forming a seventh intermediate structure187. Through molding openings183can be formed by laser ablation, plasma etch, or chemical etch, for example. As previously indicated, second lower terminal pads127are positioned on multilayer interconnect structure100so as to be external to or outside of a footprint of the semiconductor device131, and thus semiconductor device131does not interfere with formation of through molding openings183.

FIG. 14depicts the seventh intermediate structure187ofFIG. 13after conductive material189is disposed into through molding openings183. The conductive material189electrically contacts second lower terminal pads127and forms through molding conductive vias191, thereby forming an eighth intermediate structure193. Through molding conductive vias191provide electrical connections from multilayer interconnect structure100to the bottom side185of the molding resin145to facilitate vertical connection of the embedded electronic module181.

FIG. 15depicts the eighth intermediate structure193ofFIG. 14after solder mask173is applied to the outer surface of topside insulating substrate layer153and patterned wiring layer169and is patterned to form solder mask openings175to selected portions of the patterned wiring layer169, after solder spheres179are disposed onto solder mask openings175on exposed portions of patterned wiring layer169, and after package level inputs/outputs (I/Os)195(e.g., solder balls) are disposed on a bottom surface197of through molding conductive vias191, thereby forming a second embedded electronics module199.

As depicted inFIG. 16, the combination of through molding conductive vias191and solder balls195facilitate the stacking of a second electronics module201on top of or under second embedded electronics module199ofFIG. 15, thereby forming a package-on-package (PoP) assembly. Second electronics module201is a packaged microelectronics component with topside terminal pads203that are arranged in a perimeter configuration to mirror the bottom surface197of through molding conductive vias191. Solder balls195electrically connect the bottom surface197of through molding conductive vias191to the topside terminal pads203of second electronics module201, forming a first embedded electronics PoP assembly205.

FIG. 17depicts another preferred embodiment of the invention where a third embedded electronics module209identical to that of the first embedded electronics module181ofFIG. 12is provided, except that the third embedded electronics module209has its device I/O pads137,139,141,143electrically connected to the multilayer interconnect structure100by a combination of anisotropic conductive adhesive (ACA) and direct metallization. The ACA207provides high electrically conductivity in the vertical direction210and high electrical isolation in the lateral direction212. In this embodiment, component attach material133(FIG. 12) is replaced with ACA207, which is composed of an organic resin that includes electrically conductive filler particles208therein. According to an exemplary embodiment, the electrically conductive filler particles208are in the form of vertically orientated electrically conductive elements, such as carbon nanotubes for example. The density and orientation of the electrically conductive filler particles208is such that, when the ACA207is cured, the electrically conductive filler particles208will provide an electrical path through the organic resin in a vertical direction. The ASA207thus electrically connects perimeter I/O device signal pads137to first lower terminal pads125of multiplayer interconnect structure100without providing an electrical short between adjacent perimeter I/O device signal pads137. Center I/O device control, power, and ground pads139,141,143of complex semiconductor device131are connected to multiplayer interconnect structure100by electrically conductive through vias167as depicted in first embedded electronic module181inFIG. 12, forming the third embedded electronics module209.

Because ASA207provides a direct electrical path from I/O device signal pads137to the multilayer interconnect100, all device signal I/O, control I/O, power I/O, and ground I/O pads137,139,141,143could be interconnected to terminal pads125,127on the multilayer interconnect structure100and eliminate the need for conductive through vias167to connect to power, ground, and control pads139,141,143of the complex semiconductor device131. However, it is well known that power and ground pads141,143on high-end semiconductors such as complex semiconductor devices131have high current requirements and that they need very low resistivity interconnects from the substrate to the device pads. Indeed, some signal I/O and control I/O, such as a clock signal, may also require low resistivity connections. Typically, signal I/O for data busses and address busses (covering most device signal I/O) have lower current requirements and can be connected with higher resistivity connections. Although each complex semiconductor device131has differing design requirements, the highest performance structure of this embodiment is to utilize the ACA207to connect to low current I/O device signal pads137and conductive through vias167for all power, ground, and higher current controls I/O pads141,143,139, as depicted inFIG. 17.

Although not depicted inFIG. 17, it is recognized that through molding conductive vias191and solder balls195as depicted inFIG. 15can be added to the third embedded electronics module209to form an embedded electronics module that facilitates vertical connection of an electronics module thereto. That is, the addition of through molding conductive vias191and solder balls195to the third embedded electronics module209provides for attachment of a second electronics module to its bottom surface197(as depicted inFIG. 16) to form an embedded electronics PoP assembly.

Referring now toFIG. 18, another preferred embodiment of the invention is depicted. InFIG. 18, a fourth embedded electronics module215is illustrated where device I/O pads137,139,141,143are electrically connected to the multilayer interconnect structure100by a combination of compression bonding connections and direct metallization using conductive through vias. During curing of non-conductive component attach material133that bonds complex semiconductor device131to the lower surface of multilayer interconnect structure100, the adhesive133shrinks and is squeezed from a gap (such as gap217inFIG. 17) between perimeter I/O device signal pads137and first lower terminal pads125, allowing the perimeter I/O device signal pads137and first lower terminal pads125to make physical contact and electrically interconnect. First lower terminal pads125and second lower terminal pads127are formed with a thick metallization layer, such as for example 20 to 40 microns, to facilitate this process. This results in perimeter I/O device signal pads137and first lower terminal pads125being electrically bonded to each other by compression bonding. Center I/O device control, power, and ground pads139,141,143of complex semiconductor device131are connected to multiplayer interconnect structure100by electrically conductive through vias167as depicted in first embedded electronic module181inFIG. 12, forming fourth embedded electronics module215. Because thicker first lower terminal pads125are in physical contact with perimeter device I/O signal pads137, all device signal and control I/O pads137can be interconnected in perimeter device I/O pads, and the conductive through vias167only need to connect to center I/O device power and ground pads141,143, simplifying the fabrication process. Although not depicted, through molding conductive vias191and solder balls195as depicted inFIG. 15can be added to fourth embedded electronics module215to form an embedded electronics module that facilitates vertical connection of an electronics module thereto. That is, the addition of through molding conductive vias191and solder balls195to the fourth embedded electronics module215provides for attachment of a second electronics module to its bottom surface197(as depicted inFIG. 16) to form an embedded electronics PoP assembly.

Referring now toFIGS. 19-22, another preferred embodiment of the invention is depicted. InFIGS. 19-22, build-up of a fifth embedded electronics module is illustrated that has perimeter I/O device signal pads137of complex semiconductor device131connected to first lower terminal pads125of the multilayer interconnect structure100via a localized conductive adhesive or solder. Referring first toFIG. 19, the multiplayer interconnect structure100ofFIG. 5is depicted after non-conductive component attach material133is applied to the bottom surface of multiplayer interconnect structure100, with portions of first lower terminal pads125being free of component attach material133, thereby forming ninth intermediate structure223. According to embodiments of the invention, component attach material133can be applied, for example, by screen printing or stencil printing just to the bottom side of the lower insulating substrate layer105or can be applied over the outer surface of lower patterned wiring layer115and the bottom side of the lower insulating substrate layer105(e.g., such as by spin coating, spray coating, or meniscus coating) and then patterned by, for example, laser ablation or by photopatterning with UV light exposure.

FIG. 20depicts the ninth intermediate structure223ofFIG. 19after a conductive adhesive227has been applied to exposed portions of first lower terminal pads125, thereby forming a tenth intermediate structure225. Conductive adhesive227can be applied for example by screen printing, stencil printing, or ink jetting.FIG. 21depicts the tenth intermediate structure225ofFIG. 20after complex semiconductor device131is bonded to the bottom surface of multilayer interconnect structure100, thereby forming an eleventh intermediate structure229. Perimeter I/O device signal pads137of complex semiconductor device131are electrically connected to first lower terminal pads125of the multilayer interconnect structure100by the localized conductive adhesive227. While the use of conductive adhesive227is described above, it is recognized that an alternative embodiment could alternatively use solder paste instead of conductive adhesive—with the solder paste being applied to exposed portions of first lower terminal pads125to electrically connect the perimeter I/O device signal pads137to first lower terminal pads125, thereby forming tenth intermediate structure225.

FIG. 22depicts the eleventh intermediate structure229ofFIG. 21after molding resin145is applied to its lower surface, thereby encapsulating complex semiconductor device131. As illustrated, conductive through vias167are formed down through multilayer interconnect structure100and component attach material133to electrically connect to center I/O device control, power and ground pads139,141,143. Topside solder spheres179are mounted onto the topside of multilayer interconnect structure100, thereby forming fifth embedded electronics module231. In this embodiment, all I/O device pads137,139,141,143of the complex semiconductor device131are electrically connected to conductive features of multilayer interconnect structure100. Although not depicted, through molding conductive vias191and solder balls195as depicted inFIG. 15, can be added to fifth embedded electronics module231to form an embedded electronics module that facilitates vertical connection of an electronics module thereto. That is, the addition of through molding conductive vias191and solder balls195to the fifth embedded electronics module231provides for attachment of a second electronics module to its bottom surface197(as depicted inFIG. 16) to form an embedded electronics PoP assembly.

Referring now toFIGS. 23A-23H, wafer level processing of a semiconductor wafer300containing a plurality of complex semiconductor devices131is depicted that targets redistributing the device I/O pads to facilitate incorporating these devices into the various embodiments of the invention described in the preceding paragraphs and illustrated inFIGS. 5-22, according to another preferred embodiment of this invention. AlthoughFIGS. 23A-23Hdepict a cross-section of a device with twelve (12) I/O pads across its surface, and having a total of 144 I/O pads in a full 12×12 area array configuration, it is recognized that a typical complex semiconductor device would have hundreds or thousands of I/O pads. Thus, it is to be understood that the complex semiconductor device(s) depicted inFIGS. 23A-23Hwith fewer I/O pads is for purposes of clarity and facilitating better understanding of the invention.

Referring first toFIG. 23A, a simplified version of a portion of a complex semiconductor wafer300containing multiple complex semiconductor die sites301is provided, withFIG. 23Adepicting one die site301. The die site301includes a plurality of device I/O pads303comprising multiple signal pads305located in the perimeter region and one signal pad305located in the central region, and at least one control pad307, multiple power pads309, and multiple ground pads311all located in the central region. Although typical complex semiconductor dies have most of their signal I/O pads305located on the die perimeter region, complex semiconductor dies can have one or more signal I/O pads305located in the central region of the die.

FIG. 23Bdepicts the complex semiconductor wafer300ofFIG. 23Aafter a first on-wafer insulating substrate layer313is dispensed on the wafer top surface. The on-wafer insulating substrate layer313may be comprised of an organic resin, polyimide, epoxy, or liquid crystal polymer and may be applied by spin coating, spray coating, or meniscus coating, for example. According to embodiments, the first on-wafer insulating substrate layer313may have a thickness of 1 to 20 microns and preferably of 2 to 10 microns.FIG. 23Cdepicts the complex semiconductor wafer300ofFIG. 23Bafter microvias315are formed through first on-wafer insulating substrate layer313to a plurality of device I/O pads303. The microvias315may be formed by a photo-patterning of the first on-wafer insulating substrate layer313, with the insulating substrate layer being patterned by UV light exposure or laser ablation, for example.FIG. 23Ddepicts the complex semiconductor wafer300ofFIG. 23Cafter a conductive material is dispensed on the outer surface of first on-wafer insulating substrate layer313and into microvias315and onto exposed portions of a plurality of device I/O pads303and subsequently patterned, so as to form a conductive interconnect layer317(i.e., “patterned conductive layer317”) on the outer surface of on-wafer insulating substrate layer313and conductive microvias319. The conductive material may be applied by one or more of electroless plating, sputtering, evaporation and electroplating or by one of subtractive patterning and semi-additive patterning.

FIG. 23Edepicts the complex semiconductor wafer300ofFIG. 23Dafter a second on-wafer insulating substrate layer321is dispensed on the top surface of the first on-wafer insulating substrate layer313and on patterned conductive layer317. According to embodiments, the second on-wafer insulating substrate layer321may have a thickness of 1 to 20 microns and preferably of 2 to 10 microns.FIG. 23Fdepicts the complex semiconductor wafer300ofFIG. 23Eafter second microvias323are formed through second insulating substrate layer321to a plurality of locations on patterned conductive layer317.FIG. 23Gdepicts the complex semiconductor wafer300ofFIG. 23Fafter a conductive material is dispensed on the outer surface of second on-wafer insulating substrate layer321and into second microvias323and onto exposed portions of a plurality of locations on patterned conductive layer317and subsequently patterned to form second conductive microvias325and redistributed I/O pads327, with the redistributed I/O pads327including reconfigured device I/O signal pads329, reconfigured device I/O power pads331, reconfigured device I/O ground pads333, and at least one reconfigured device I/O control pad335. A reconfigured complex semiconductor die site337is thereby formed.FIG. 23Hdepicts the reconfigured complex semiconductor die site337ofFIG. 23Gafter it is singulated from complex semiconductor wafer300forming reconfigured complex semiconductor chip339.

According to one embodiment, the number of reconfigured device I/O signal pads329may thus be approximately equal to the number of device I/O signal pads305and the number of reconfigured device I/O power pads331and reconfigured device I/O ground pads333may be less than or equal to half of the number of device I/O power pads309and device I/O ground pads311. As depicted inFIGS. 23A-23H, device I/O signal pads305are redistributed to perimeter regions of the reconfigured complex semiconductor device331, with each device I/O signal pad305routed to a corresponding reconfigured device I/O signal pad329. Multiple device I/O power pads309are redistributed to a center portion of reconfigured complex semiconductor device339, with multiple device I/O power pads309routed to common reconfigured device I/O power pads331to form a conductive plate region—i.e., each reconfigured device I/O power pad331is electrically connected to at least two device I/O power pads309. The reconfigured device I/O power pads331are preferably larger than the device I/O pads303and larger than the reconfigured device I/O signal pads329. Multiple device I/O ground pads311are redistributed to a center portion of reconfigured complex semiconductor device339, with multiple device I/O ground pads311routed to common reconfigured device I/O ground pads333to form a conductive plate region—i.e., each reconfigured device I/O ground pad333is electrically connected to at least two device I/O ground pads311. The reconfigured device I/O ground pads333are preferably larger than the device I/O pads303and larger than the reconfigured device I/O signal pads329. At least one device I/O control pad is307redistributed to a center portion of reconfigured complex semiconductor device339, with each device I/O control pad307routed to a corresponding reconfigured device I/O control pad335. The at least one reconfigured device I/O control pad335is preferably larger than the device I/O pads303and larger than the reconfigured device I/O signal pads329. According to one embodiment, a size of the reconfigured device I/O power pads331, reconfigured device I/O ground pads333, and reconfigured device I/O control pad335is twice the size of the reconfigured device I/O signal pads329. The reconfigured complex semiconductor device339ofFIG. 23Hcan be used to replace complex semiconductor device131depicted inFIGS. 6-18, 21, and22.

Referring now toFIG. 24, a multilayer interconnect structure400is depicted that is similar to multilayer interconnect structure100depicted inFIG. 5, with multilayer interconnect structure400representing another embodiment of the invention. Similar to multilayer interconnect structure100, multilayer interconnect structure400includes three insulating substrate layers401,403,405(i.e., core layer401, upper layer403, and lower layer405), four patterned wiring layers409,411,413,415(i.e., first patterned wiring layer409, second patterned wiring layer411, upper patterned wiring layer413, and bottom patterned wiring layer415), and three sets of insulating substrate layer conductive microvias417,419,421, although it is recognized that multilayer interconnect structure400may have fewer interconnect layers or more interconnect layers as determined by the complexity of the circuit function being implemented. Upper wiring layer413contains upper terminal pads423that are positioned in pre-determined locations for additional interconnect layer(s) that might be added after a complex semiconductor device (not shown) is attached to multilayer interconnect structure400. Bottom wiring layer415contains a plurality of first lower terminal pads425and optionally contains a plurality of second lower terminal pads427. First lower terminal pads425are positioned to interconnect to signal I/O pads of the complex semiconductor device that would be attached to multilayer interconnect structure400in assembling a complex microelectronic package or module. Optional second lower terminal pads427are positioned to interconnect to lower I/O structures such as pins, through molding vias, or a substrate structure that could be incorporated into a complex microelectronic package or module.

As shown inFIG. 24, multilayer interconnect structure400differs from multilayer interconnect structure100(FIG. 5) in that multilayer interconnect structure400includes conductive features in the center region429of multilayer interconnect structure400. In the embodiment ofFIG. 24, patterned conductor layers409and411define buried conductive via connections409aand411athat are used to assist in the formation of through vias461depicted later inFIG. 26. According to an exemplary embodiment, conductive via connections409aand411aare in the form of cover pads or intra-layer via connections that include an aperture formed therein in order to provide for the formation of through vias (i.e., “shoot-through vias”) that assist in via formation accuracy, speed, and yield. In another embodiment, patterned conductor layers409and411may define buried conductive power and ground planes409b,411b(seeFIGS. 32A-32E), respectively, in the interconnect structure400. The power and ground planes may be formed of copper foil or another similar metallic conductor. For example, as previously described, a conductor layer may be formed that is composed of a barrier or adhesion layer, a seed layer, and a layer of bulk material that is plated atop the seed and barrier layers achieving the desired conductor layer thickness, as previously described. The barrier layer may include titanium or chromium, while the seed metal layer may include copper and the layer of bulk material may include at least one electrically conductive material such as copper, aluminum, gold, silver, nickel, or combinations thereof. Other electrically conducting materials or a combination of metal and a filling agent may be used in other embodiments, such as an electrically conductive polymer or inks that contain conductive metal particles. The buried conductive power and ground planes may be structured to cover most of the surface/plane of interconnect structure400on which they are formed, or may over overly desired sections/portions of the surface/plane of interconnect structure400on which they are formed (i.e., “partial” power and ground planes). The power and ground planes may be formed as mostly continuous features/layers or as segmented features divided into different areas that are isolated from one another. The ground plane is connected to a power supply ground terminal (not shown) and serves as a return path for current from different circuits/components (i.e., complex semiconductor device) packaged with the interconnect structure in an embedded electronics module. The power plane is the counterpart to the ground plane and behaves as an AC signal ground plane while providing DC power to the circuits/components (i.e., complex semiconductor device) packaged with the interconnect structure in an embedded electronics module. Additionally, each of the ground and power planes may serve to provide electromagnetic interference (EMI) shielding to the semiconductor device431.

Referring now toFIGS. 25-27, build-up steps for forming an embedded electronics module are illustrated where a complex semiconductor device is attached and electrically connected to multilayer interconnect structure400. Referring first toFIG. 25, the multilayer interconnect structure400ofFIG. 24is depicted after a complex semiconductor device431is bonded to the lower surface of multilayer interconnect structure400via component attach material433and after exposed surfaces of complex semiconductor device431and exposed regions of component attach material433are encapsulated with molding resin445, thereby forming a twelfth intermediate structure460. Complex semiconductor device431is placed on the bottom surface of multilayer interconnect structure400, with the complex semiconductor device431perimeter I/O device signal pads437aligned to first lower terminal pads425of multilayer interconnect structure400. In addition, center I/O device power pads441and center I/O device ground pads443are aligned to conductive via connections409aand411a.

FIG. 26and depicts twelfth intermediate structure460ofFIG. 25after microvias459are formed in topside insulating substrate layer453to portions of upper patterned wiring layer413and through vias461,461a,461bare formed through topside insulating substrate layer453, upper insulating substrate layer403, core insulating substrate layer401, lower insulating substrate layer405and component attach material433to center I/O device control pads439, center I/O device power pads441, and center I/O device ground pads443, thereby forming thirteenth intermediate structure470. Through vias461aare formed through openings475in patterned conductor layer411and through vias461bare formed through openings473in patterned conductor layer409to more precisely control the location of through vias461a,461b.

FIG. 27depicts thirteenth intermediate structure470ofFIG. 26after conductive material is applied to microvias459, through vias461,461a,461band the outer surface of topside insulating substrate layer453, so as to form solid conductive microvias465, conductive through vias467,467a,467band patterned conductor or wiring layer469, thereby forming fourteenth intermediate structure480. Respective conductive through vias467b,467amake electrical contact with patterned conductor layer409and patterned conductor layer411, thereby providing direct electrical connection with power and ground buried conductive planes provided by conductor layers409and411.

FIG. 28is similar toFIG. 27and represents yet another embodiment of the invention. It depicts thirteenth intermediate structure470ofFIG. 26after conductive material is applied to microvias459, to the side walls of through vias461,461a,461band to the outer surface of topside insulating substrate layer453, so as to form conductive microvias465, conformal conductive through vias471,471a,471band patterned wiring layer469, thereby forming fifteenth intermediate structure490. Fifteenth intermediate structure490has lower current carrying capability due to its conformal conductive through vias471,471a,471bfor power and ground connections versus the solid conductive through vias467,467a,467band would be limited to lower power dissipation devices. The conformal conductive through vias471,471a,471brequire less plating to form and would have greater mechanical flexibility.

FIG. 29is similar toFIG. 27and depicts a sixteenth intermediate structure500that has conductive via connections409aand411areplaced by conductive via connections415athat are on the lower patterned conductor layer415. Solid conductive vias473are formed through openings in conductive via connections415a.

FIG. 30is similar toFIG. 27and depicts a seventeenth intermediate structure510that has solid conductive through vias467areplaced with solid conductive through vias475which each connect to a plurality of center I/O device power pads441or center I/O device ground pads443. The solid conductive through vias475in seventeenth intermediate structure510provide further reductions in the interconnection resistance on the electrical connections to power pads441and ground pads443. Additionally, solid conductive through vias475in seventeenth intermediate structure510also provide improved thermal spreading and an improved thermal cooling path that can minimize junction temperature with the complex semiconductor device431.

While the intermediate structures ofFIGS. 27-30are illustrated with the perimeter I/O device signal pads437of semiconductor device431being capacitively coupled to first lower terminal pads425of multilayer interconnect structure400due to a thin layer of electrically non-conductive component attach material433that is present therebetween, it is recognized that first lower terminal pads425can be electrically coupled I/O device signal pads437via other means, according to additional embodiments of the invention. That is, first lower terminal pads425can be electrically coupled I/O device signal pads437via use of an anisotropic conductive adhesive for adhesive433(seeFIG. 17), via compression bonding between the pads425and pads437(seeFIG. 18), or via use of a localized conductive adhesive or solder applied between pads425and pads437in openings formed in non-conductive component attach material433(seeFIG. 22).

Additionally, intermediate structures ofFIGS. 27-30can be further processed to add additional features such as: the addition of through molding conductive vias191as depicted inFIG. 14, after package level inputs/outputs (I/Os)195(e.g., solder balls) disposed on a bottom surface197of through molding conductive vias191as depicted inFIG. 15, and stacking of a second electronics module201on top of or under the intermediate structures as depicted inFIG. 16.

Referring now toFIGS. 31A-31D, detailed views of portions of the multilayer interconnect structure400are shown prior to and after formation of vias and conductive vias therein as depicted inFIGS. 25-28, according to embodiments of the invention.FIG. 31Ashows a portion of the twelfth intermediate structure460ofFIG. 25in greater detail. Second patterned wiring layer411is shown as including an aperture477formed therethrough to provide for via formation through the conductive feature411a.FIG. 31Bdepicts the through vias461aofFIG. 26in greater detail. As shown, through vias461aare formed to have a stepped configuration, with the aperture477in conductive feature411aresulting in a narrower via being formed below conductive feature411aand down to the I/O pad441on complex semiconductor device431upon formation thereof via a (laser) ablation technique.FIG. 31Cshows the solid conductive vias467aofFIG. 27in greater detail, with it being seen therein that solid conductive vias467ahave a stepped configuration following that of through vias461a.FIG. 31Dshows the conformal through vias471aofFIG. 28in greater detail, with it being seen therein that conformal through vias471ahave a stepped configuration following that of through vias461a. The stepped through vias461a, solid conductive vias467a, and conformal through vias471adepicted inFIG. 31have two key advantages. First, they form a direct electrical connection of the power and ground to interconnect wiring or power/ground planes within multilayer interconnect structure400—providing a higher performing interconnect structure. Second, they provide more precise vias that connect to center I/O device power pads441and center I/O device ground pads443of the complex semiconductor device431, improving yields.

Referring now toFIGS. 32A-32E, cross-sections and conductor layers of fourteenth intermediate structure480ofFIG. 27are depicted according to an embodiment where buried patterned conductor layers409and411are formed/patterned to provide a ground plane and power plane in fourteenth intermediate structure480.

FIG. 32Adepicts a top view of patterned conductor layer411in intermediate structure480. Patterned conductor layer411is formed to include a double row of conductive microvias421and cover pads411a, as well as solid conductive through vias467btied to I/O device power pads441and solid conductive through vias467atied to I/O device ground pads443of complex semiconductor device431(FIG. 27). Patterned conductor layer411is further formed to include a ground plane411bcovering most of the surface of the interconnect structure400, with keep-out regions412(i.e., regions free of conductive material) formed to isolate conductive microvias421and conductive through vias467btied to I/O device power pads441. The ground plane411bis coupled to solid conductive via467athat is tied to I/O device ground pads443. For purposes of forming solid conductive via467a, apertures477are formed through ground plane411b, with the solid conductive via467aformed therethrough, as best seen inFIG. 27.

FIG. 32Bdepicts a top view of patterned conductor layer409in intermediate structure480. Patterned conductor layer409is formed to include a double row of conductive microvias417and cover pads409a, as well as solid conductive through vias467btied to I/O device power pads441and solid conductive through vias467atied to I/O device ground pads443of complex semiconductor device431(FIG. 27). Patterned conductor layer409is further formed to include a power plane409bcovering most of the surface of the interconnect structure400, with keep-out regions410(i.e., regions free of conductive material) formed to isolate conductive microvias417and conductive through vias467atied to I/O device ground pads443. The power plane409bis coupled to solid conductive via467bthat is tied to I/O device power pads441. For purposes of forming solid conductive via467b, apertures477are formed through power plane409b, with the solid conductive vias467bformed therethrough, as best seen inFIG. 27.

FIG. 32Cdepicts a top view of patterned conductor layer423in intermediate structure480. Patterned conductor layer423is formed to include a double row of conductive microvias419and cover pads423a(i.e., upper terminal pads), as well as routing traces423bthat tie to selected cover pads423in order to redistribute the pads to pre-determined locations for providing I/O connections to the module added after a complex semiconductor device431(FIG. 27) is attached to multilayer interconnect structure400. Conductive through vias467(not shown),467a,467bare electrically isolated from cover pads423, as patterned conductor layer423is patterned so as to be mostly free of conductive material (i.e., a majority of insulating substrate layer403is left unmetallized, as opposed to patterned conductor layers409,411that include power plane409band ground plane411b, respectively, that cover most of the surface of the interconnect structure400).

Referring now toFIGS. 32D and 32E, cross-sectional views taken along line b-b′ and line a-a′ ofFIGS. 32A-Care shown, respectively. As first shown inFIG. 32D, the intermediate structure480is cut through the upper row of conductive microvias417,419,421and cover pads409a,411a,423a. For patterned conductor layers409,411, the conductive microvias417,421are isolated from ground plane411band power plane509bby way of keep-out regions410,412. As shown inFIG. 32E, the intermediate structure480is cut through the solid conductive vias467a,467b. For patterned conductor layer409, the solid conductive via467aextending down to I/O device ground pad(s)443is electrically isolated from power plane409bby keep-out regions410, while the solid conductive via467bextending down to I/O device power pad(s)441is electrically coupled to power plane409b. For patterned conductor layer411, the solid conductive via467bextending down to I/O device power pad(s)441is electrically isolated from ground plane411bby keep-out regions412, while the solid conductive via467aextending down to I/O device ground pad(s)443is electrically coupled to ground plane411b.

Referring now toFIG. 33, a conductor layer409,411included in multilayer interconnect structure400is depicted according to another embodiment where one of patterned buried conductor layers409,411is formed as a split plane that defines buried partial power and ground planes, with layer409being illustrated inFIG. 33. The conductive layer409is patterned to form a split plane where half of the plane is a power plane and half is a ground plane—with a partial power plane409cseparated from a partial ground plane409dby a non-conductive area414. The power plane portion409cof the split plane is in contact with conductive through via467b, which in turn extends down to I/O device power pads441. The ground plane portion409dof the split plane is in contact with conductive through via467a, which in turn extends down to I/O device ground pads443. The patterning of conductive layer409to form a split plane including partial power plane409cand partial ground plane409dbeneficially improves yield in fabricating the interconnect structure400(FIG. 24) by saving a whole layer of processing, and it additionally provides robust electrical performance. WhileFIG. 33shows buried conductor layer409as being patterned to include only a single partial power plane409cand partial ground plane409d, it is recognized that buried conductor layer409may be patterned to define multiple distinct partial power planes409cand partial ground planes409delectrically isolated from one another and electrically coupled to respective I/O device power pads441and I/O device ground pads443, according to another embodiment.

With regard to the buried conductive via connections interconnect structure400included in conductor layers409and411, it is recognized that such buried conductive via connections could be included in other electronics packages used in a die almost last fabrication process.FIG. 34illustrates another electronics package600that includes such buried conductive via connections, with the electronics package including a semiconductor device602and a multilayer interconnect structure606. The multilayer interconnect structure606is composed of multiple insulating substrate layers616, and multiple conductive wiring layers618, with microvia connections620connecting between adjacent wiring layers. The multiple insulating substrate layers616includes an insulating substrate604to which the active surface610of semiconductor device602is bonded by a component attach material614such as an adhesive, for example. A cavity622is formed in the multilayer interconnect structure606forming a window frame around semiconductor device602. Resin material624fills cavity666encapsulating semiconductor device602.

As shown inFIG. 34, a first buried conductive feature or connection626is formed on a top surface of insulating substrate604. Microvias628are formed through insulating substrate604to selected areas of buried conductive feature or connection626. A second buried conductive feature or connection630is formed on a bottom/outer surface of insulating substrate604, with an outer insulating layer634being applied on the bottom/outer surface of insulating layer604and on second buried conductive feature or connection630.

Buried conductive via connections626,630may be used to optimize the location of through vias636that are formed through insulating substrate604, outer insulating layer634, and adhesive614. According to one embodiment, conductive via connections626,630are in the form of cover pads or intra-layer via connections that include an aperture formed therein in order to provide for the formation of through vias (i.e., “shoot-through vias”) that aid in via formation accuracy, speed and yield. Additionally, conductive via connections626,630may define buried conductive power and ground planes, respectively, in the interconnect structure606. The power and ground planes may be formed of copper foil or another similar conductor, for example, and are structured to cover most of the surface/plane of interconnect structure606on which they are formed. The power and ground planes may be formed as mostly continuous features/layers or as segmented features divided into different areas that are isolated from one another. Additionally, outer vias635and outer wiring layer637may be formed on/through outer insulating layer634to electrically connect to selected areas of second buried conductive via connections630, selected areas of first buried conductive via connections626, and/or conductive wiring layers618.

Beneficially, embodiments of the invention thus provide an embedded device module with a complex semiconductor device or other electrical component embedded under a prefabricated multilayer interconnect structure, with the semiconductor device attached to the prefabricated multilayer interconnect structure after it is tested, thereby avoiding committing the semiconductor device to an interconnect structure with a potential defect. Two different types of interconnects are used to connect the device to the interconnect structure—a high density, moderate performance connection for signal pads and a high performance, moderate density connection for high performance controls, power, and ground pads—thereby requiring minimal interconnect processing after the semiconductor device is attached. An embedded device module with increased yield and lowered costs is thus achieved, while with the module attaining the high electrical performance inherent with an embedded device structure.

Therefore, according to one embodiment of the invention, an electronics package comprises a multilayer interconnect structure including a plurality of insulating substrate layers, a plurality of conductive wiring layers positioned on the plurality of insulating substrate layers, with each of the plurality of insulating substrate layers having one or more of the plurality of conductive wiring layers positioned thereon, and a plurality of conductive microvias extending through the plurality of insulating substrate layers to electrically connect the plurality of conductive wiring layers, wherein a bottom wiring layer of the plurality of conductive wiring layers includes a plurality of first terminal pads that are positioned on a bottom surface of the multilayer interconnect structure. The electronics package also comprises an electrical component coupled to the bottom surface of the multilayer interconnect structure, the electrical component including a plurality of first input/output (I/O) pads aligned with the plurality of first terminal pads and a plurality of second I/O pads aligned to regions of the multilayer interconnect structure without first terminal pads. The electronics package further comprises a plurality of conductive through vias extending through the multilayer interconnect structure and electrically connected to the plurality of second I/O pads.

According to another embodiment of the invention, a method of manufacturing an electronics package includes providing a pre-fabricated multilayer interconnect structure comprising a top surface and a bottom surface, with the multilayer interconnect structure including a plurality of insulating substrate layers each having a plurality of microvias formed therein and a plurality of conductor layers positioned on the plurality of insulating substrate layers and in the plurality of microvias, the plurality of conductor layers comprising a plurality of first terminal pads positioned on the bottom surface of the multilayer interconnect structure. The method also includes coupling an active surface of a semiconductor device to the bottom surface of the multilayer interconnect structure such that a plurality of semiconductor device first input/output (I/O) pads on the active surface are aligned to the plurality of first terminal pads, forming a plurality of through vias that extend from the top surface of the multilayer interconnect structure down to a plurality of semiconductor device second I/O pads on the active surface of the semiconductor device, and forming conductive through vias in the plurality of through vias that contact the plurality of semiconductor device second I/O pads.

According to yet another embodiment of the invention, an electronics package comprises a multilayer interconnect structure including a plurality of insulating substrate layers each comprising a plurality of microvias formed therein, a plurality of conductive wiring layers positioned on the plurality of insulating substrate layers such that each of the plurality of insulating substrate layers has one or more conductive wiring layers positioned thereon, and a plurality of conductive microvias in the plurality of microvias to electrically connect the plurality of conductive wiring layers, wherein the plurality of conductive wiring layers and the plurality of conductive microvias are positioned in a perimeter region of the multilayer interconnect structure that surrounds a center region of the multilayer interconnect structure. The electronics package also comprises a semiconductor device attached to a bottom surface of the multilayer interconnect structure, the semiconductor device comprising a plurality of first input/output (I/O) pads aligned with the perimeter region and a plurality of second I/O pads aligned with the center region. The electronics package further comprises a plurality of conductive through vias extending through the multilayer interconnect structure in the center region and electrically connected to the plurality of second I/O pads.

According to still another embodiment of the invention, a reconfigured semiconductor device includes a semiconductor device having a plurality of device I/O pads on an active surface thereof, the plurality of device I/O pads comprising first device I/O pads and second device I/O pads. The reconfigured semiconductor device also includes a first redistribution layer on the active surface, the first redistribution layer comprising a first insulating substrate layer, a first plurality of vias formed through the first insulating substrate layer to the plurality of device I/O pads, and a first wiring layer overlying the first insulating substrate layer and extending into the plurality of vias down onto portions of the plurality of device I/O pads, the first wiring layer comprising a plurality of first contact pads connected to the plurality of device I/O pads. The reconfigured semiconductor device further includes an upper redistribution layer overlying the first redistribution layer and comprising an upper insulating substrate layer, a plurality of vias formed through the upper insulating substrate layer to a plurality of contact pads on a wiring layer below the upper insulating substrate layer that comprises the first wiring layer or an additional wiring layer between the first redistribution layer and the upper redistribution layer, and an upper wiring layer overlying the upper insulating substrate layer and extending into the plurality of vias and onto portions of the plurality contact pads on the wiring layer below the upper insulating substrate layer, the upper wiring layer comprising a plurality of upper contact pads connected to a plurality of contact pads on the wiring layer below the upper insulating substrate layer. The upper contact pads comprise first reconfigured device I/O pads and second reconfigured device I/O pads, with each of a plurality of the first reconfigured device I/O pads electrically connected to a single respective first device I/O pad and each of a plurality of the second reconfigured device I/O pads electrically connected to at least two respective second device I/O pads.

According to still another embodiment of the invention, an electronics package includes a multilayer interconnect structure comprising a plurality of insulating substrate layers each having a plurality of microvias formed therein and a plurality of conductor layers positioned on the plurality of insulating substrate layers and in the plurality of microvias, wherein the plurality of conductor layers comprises buried conductive via connections embedded in the multilayer interconnect structure. The electronics package also includes an electrical component attached to the multilayer interconnect structure and aligned with the buried conductive via connections, the electrical component comprising a plurality of input/output (I/O) pads. The electronics package further includes a plurality of conductive through vias extending through the multilayer interconnect structure and forming a direct electrical and physical connection with at least a portion of the plurality of I/O pads, wherein the buried conductive via connections are in physical contact with one or more of the plurality of conductive through vias.

According to still another embodiment of the invention, an electronics package includes a multilayer interconnect structure comprising a plurality of insulating substrate layers and a plurality of conductor layers positioned on the plurality of insulating substrate layers and extending through a plurality of microvias formed therein. The electronics package also includes an electrical component comprising a plurality of input/output (I/O) pads electrically coupled to the plurality of conductor layers and a plurality of conductive through vias extending through a least two insulating substrate layers of the plurality of insulating substrate layers and electrically connected to at least a portion of the plurality of I/O pads. The plurality of conductor layers further includes a first conductor layer including a ground plane buried in the multilayer interconnect structure, the ground plane forming a direct electrical and physical connection with a respective conductive through via that is electrically connected to a ground I/O pad of the plurality of I/O pads, and includes a second conductor layer including a power plane buried in the multilayer interconnect structure, the power plane forming a direct electrical and physical connection with a respective conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.

According to still another embodiment of the invention, an electronics package includes a multilayer interconnect structure comprising a plurality of insulating substrate layers and a plurality of conductor layers positioned on the plurality of insulating substrate layers and extending through a plurality of microvias formed therein. The electronics package also includes an electrical component comprising a plurality of input/output (I/O) pads electrically coupled to the plurality of conductor layers and a plurality of conductive through vias extending through at least two insulating substrate layers of the plurality of insulating substrate layers and electrically connected to at least a portion of the plurality of I/O pads. The plurality of conductor layers includes a first conductor layer comprising a partial ground plane buried in the multilayer interconnect structure and forming a direct electrical and physical connection with a respective conductive through via that is electrically connected to a ground I/O pad of the plurality of I/O pads and a partial power plane buried in the multilayer interconnect structure and forming a direct electrical and physical connection with a respective conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.

According to still another embodiment of the invention, a method of manufacturing an electronics package includes providing a multilayer interconnect structure comprising a plurality of insulating substrate layers each having a plurality of microvias formed therein and a plurality of conductor layers positioned on the plurality of insulating substrate layers and in the plurality of microvias, at least one of the plurality of conductor layers including at least one buried conductive via aperture embedded in the multilayer interconnect structure. The method also includes attaching an active surface of an electrical component to the interconnect structure, forming at least one shoot through via that extends through the at least one buried conductive via aperture down to at least one I/O pad of a plurality of I/O pads on the active surface of the electrical component, and forming a conductive through via in each of the at least one shoot through vias that physically contacts a respective buried conductive via aperture to form at least one buried conductive via connection and that physically contacts a respective I/O pad of the plurality of I/O pads.

According to still another embodiment of the invention, an electronics package includes a plurality of insulating substrate layers each having a plurality of microvias formed therein, a plurality of conductor layers positioned on the plurality of insulating substrate layers and in the plurality of microvias, and a plurality of conductive through vias extending through at least two of the plurality of insulating substrate layers. The plurality of conductor layers comprises includes a first conductor layer including a ground plane buried in the electronics package, the ground plane forming a direct electrical and physical connection with a first conductive through via of the plurality of conductive through vias and a second conductor layer including a power plane buried in the electronics package, the power plane forming a direct electrical and physical connection with a second conductive through via of the plurality of conductive through vias.

Embodiments of the present invention have been described in terms of the preferred embodiment, and it is recognized that equivalents, alternatives, and modifications, aside from those expressly stated, are possible and within the scope of the appending claims.