Lateral high-voltage semiconductor devices with majorities of both types for conduction

This invention provides a lateral high-voltage semiconductor device, which is a three-terminal one with two types of carriers for conduction and consists of a highest voltage region and a lowest voltage region referring to the substrate and a surface voltage-sustaining region between the highest voltage region and the lowest voltage region. The highest voltage region and the lowest region have an outer control terminal and an inner control terminal respectively, where one terminal is for controlling the flow of majorities of one conductivity type and another for controlling the flow of majorities of the other conductivity type. The potential of the inner control terminal is regulated by the voltage applied to the outer control terminal. The figure presented schematically shows a device by using an n-MOSFET to control the flow of electrons and a pnp bipolar transistor to control the flow of holes, and the potential of the base region of the pnp transistor is regulated by the voltage applied to the gate electrode of the n-MOSFET.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Chinese Patent Application No. 200910131196.7, filed Apr. 7, 2009, the entire contents of which are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a technique of semiconductor devices, and specifically to lateral high-voltage semiconductor devices.

BACKGROUND OF THE INVENTION

It is well-known that the breakdown voltage, the on-resistance and the reliability are the most important issues of power devices.

During turning-on and turning-off of lateral high-voltage power devices, there is a transient stage with high voltage and large current. When a unipolar lateral power device operating in this stage, the carriers introduced by the large-current density produce a significant deviation of distribution of electric flux density of the lateral device from that case of without carriers, making the electric field of a local place be enhanced and therefore the impact ionization coefficients increased, resulting a local avalanche breakdown. The SOA (Safe Operating Area) of the device is then reduced by such a local avalanche breakdown, and the reliability of the device is also decreased.

To diminish such an effect, a conventional measure is using a small current density in the turn-on stage. However, such a method is at an expense of the performance of the device. Also, a perfect elimination of the deviation of electric flux density distribution of surface is impossible.

REFERENCES

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The detail of the present invention and the examples of the application of the present invention will be demonstrated hereinafter. In all of the following figures, the same number means the same component or element.

FIG. 1is a schematic cross-sectional view of an n-LDMOS by using the basic voltage-sustaining structure of Ref. [3]. The n-LDMOS uses electrons as majority carriers for conduction. In this figure, D stands for the drain electrode, S stands for the source electrode and G stands for the gate electrode of the n-LDMOS. The shaded area120stands for the gate oxide or gate insulator. D is connected to n+-drain region200, and S is connected both to n+-source region111and source-body p-region106through p+-region110. The surface voltage-sustaining region consists of p-region101, n-region102, p-region103and a part of p-region106. Note that the connection between S and p-region103may not be an outer one. Instead of that, p-region103can be connected directly to p-region106at certain part of the interdigitated layout, e.g. at the finger edge(s) or finger end(s), or even no connection with the p-region103still being fully depleted under the condition of the device sustaining a high voltage. Thus, the meaning of the connection is only to present that the potential of the rightmost part of p-region103is nearly the same as the potential of p-region106. Such connections in the following figures are considered as the same meaning stated above.

According to the Ref. [3], when the electric flux density of net ionized acceptor of the surface voltage-sustaining region decreases according to the increasing of the surface distance from the edge of source-body region to the drain region, the device can sustain the largest reverse-biased voltage within a shortest surface distance. Here, the value of the electric flux density of net ionized acceptor means a result of the number of the ionized acceptor of the p-regions minus the number of the ionized donor of the n-region within a not too large area in the surface divided by the area itself. Note that a not too large area means an area having a dimension much smaller than the depletion width, Wpp, of a one-sided abrupt parallel plane junction formed by the same substrate under the breakdown voltage. However, the dimension of the area can be larger than the thickness of the surface voltage-sustaining region.

Assume that D0is the density of net ionized acceptor of the depleted layer in a one-sided abrupt parallel plane junction formed by the same n-substrate100under its breakdown voltage. Then, in the case of the surface voltage-sustaining region is not a parallel plane one, e.g. is shown as inFIG. 1, in order to sustain the voltage close to the breakdown voltage of the parallel plane junction made by the same substrate in a small lateral dimension, one of the practical methods is that: the dose (the density of ionized impurities) of p-region101is 2D0at the right end, and then gradually decreases according to the lateral distance, and eventually becomes a value of D0at the left end of the region; the doses of n-region102and p-region103are constant, and the values of them are 2D0and D0, respectively. Thereupon, the density of net ionized acceptor in the surface voltage-sustaining region in such an n-LDMOS meets the demand of sustaining a largest breakdown voltage. Besides, the dose in n-region102can be very large, making the on-resistance of the device being very small.

FIG. 2shows the simulation result of ID˜VDcharacteristics of the n-LDMOS designed by using the method mentioned above and done by using TMA-MEDICI. The breakdown voltage is 800V. Here, the voltage VGSvaries from 1V to 6V and the voltage VDSvaries from 0V to 800V. It can be seen fromFIG. 2that when the VGSis 6V and VDSis increased about to 300V, the order of magnitude of the current density achieves to about 1·10−4A/μm, there appears an “upward curling” of the curve shown as909. Such phenomenon does not exist in a normal VDMOSFET in the saturation region. The deviation of the current versus voltage behaviour from a normal VDMOSFET is caused by impact ionization. Due to that when the density of current is large enough, the influence on the electric flux density of surface voltage-sustaining region caused by the electron charges introduced by the current can not be neglected. Thus, the negative flux density introduced by the large electron current counteracts part of the positive flux density in n-region102, so the ideal electric field distribution is changed to be not an ideal one. Consequently, the electric field at some location becomes larger, which can lead to considerable impact ionization. Although such impact ionization does not caused avalanche breakdown, it produces the phenomenon of “upward curling”. That is undesirable because it may influence the reliability of the device. Therefore, such phenomenon should be avoided as much as possible. Note that such phenomenon happens not only in the devices formed by using the technique of VLD as the surface voltage-sustaining region, but also in the devices using other techniques, e.g. using the technique of RESURF or JTE.

A method to remove such phenomenon is to limit the current density. Assume that when the net density of negative charges introduced by the electron current equals to tenth of D0. If the length of the surface voltage-sustaining is 100 μm, and the value of VDSis 100V, the electric field is about 1·104V/cm. Under such an electric field, the velocity of electron is saturated, having a value of 7·106cm/s. If the value of D0is 2·1012cm−2, then the corresponding allowable maximum current density, jmax, is 2·10−5A/μm.

Although a limiting of the maximum value of current density can be used to avoid the “upward curling” of ID˜VDSshown inFIG. 1, it is desired to have larger current density so that the area of chip can be saved for a large current capability. In order to get this purpose, the present invention proposes a method to implement a three-terminal lateral power device by simultaneously introducing equal amount of two types of carriers. Here, when the value of the density of electron current reaches a certain value, the electric flux of electron introduced by the electron current can be entirely offset by the electric flux of introduced holes, so the influence on the distribution of electric flux density of device caused by carriers can be eliminated. It then can not only avoid the phenomenon of “upward curling”, but also have a larger maximum current density for the reason that another type of carriers for conduction reduces the on-state voltage drop of the device at the same current density.

Since the saturated velocity of hole is about half of that of electron, the introduced hole current density required is only half of the introduced electron current density.

FIG. 3shows, a three-terminal lateral power device using two types of carriers for conduction. The figure shown on the right is its equivalent circuit. Here, the holes are introduced by a pnp bipolar transistor, and the electrons are introduced by the n-LDMOS. The electrode D is connected to both the n+-drain region201of n-LDMOS and p+-emitter region202of the pnp bipolar transistor. Electrode S is connected to both n+-source region111of n-LDMOS and source-body p-region106of n-LDMOS through p+-region110. Control terminal G is the gate electrode of n-LDMOS. The shaded area120stands for the gate oxide or gate insulator. n-region104and p-region103are the base region and collector region respectively. The surface voltage-sustaining region of the device is constructed by p-region101, n-region102, p-region103, a part of n-region104and a part of p-region106. When a voltage applied across the control terminal G with respect to source-body region of n-LDMOS is larger than the threshold voltage of the n-LDMOS, an electron current flow from n+-region201to source region of n-LDMOS through n-region104. The portion of n-region104shown in this figure can be equivalent to a series resistor R for electron current. Thus, from the equivalent circuit of the right portion of this figure, there is a voltage drop across104when there is an electron current, which makes the emitter junction of pnp have a forward biased voltage. When the value of this voltage reaches above 0.6V (refer to the silicon transistor), holes is injected to n-region104from p+-region202, and then swept into p-region103, a hole current is thus formed. It is obviously that such device is equivalent to a kind of anode-shorted IGBT.

It is worthy to note that when the device inFIG. 3is implemented, all the holes coming from p+-region202must be ensured to flow through p-region103, but not through p-region101. If the holes flow through p-region101, the electric flux density of the surface voltage-sustaining region can be superficially still satisfied the demand of optimum distribution. However, not all of the electric flux density of the holes flowing through p-region101is offset by that of the electrons flowing through n-region102, a portion of electric flux density of holes flowing through p-region101are neutralized by that of ionized acceptors in101, which results a diminish of the dose of101. Now, since the ionized acceptor in the depleted region in101acts to form a barrier of electrons to obstruct them flow from102into n−-region100, the barrier height would be reduced or even disappeared once there are a large number of holes in101. Such a flow of electrons will cause a deviation of the electric flux density of surface voltage-sustaining region from the optimum distribution, and results the phenomenon of “upward curling” again.

The resistor R in the circuit of the right portion ofFIG. 3can be realized in other way instead of that shown in the left portion ofFIG. 3. The paths of electron current in104can have different structure.FIG. 4is a top view of an example for another form of the resistor. It can be seen from this figure that when the electron current flows from201to the surface voltage-sustaining region through104, a forward biased voltage drop across202and104would be generated, so the hole current can be introduced. Not to mention, the resistor can even be replaced by an active resistance formed by a device.

FIG. 5shows the output characteristic curves of the device ofFIG. 3, simulated by using TMA-MEDICI package. It should be pointed out that although the parameters of the simulated device are not optimized, the phenomenon of “upward curling” is drastically be diminished in comparison with the curves inFIG. 2. Moreover, the current density in the linearity region has been increased significantly.

The structure shown inFIG. 3can also be used to implement high (low)-side device.FIG. 6shows a high-side device with two types of carriers for conduction by using the basic structure shown inFIG. 3and a low-side surface voltage-sustaining region. The surface voltage-sustaining region of the high-side device is constructed by n-region116, p-region117, the portion of p-region115starting from a place under the right side of204to the left edge of118and the portion of n-region108starting from a place under the right side of204to the left edge of116; and the low-side surface voltage-sustaining region has a same structure as that of the surface voltage-sustaining region inFIG. 3. Electrode SHis connected both to n+-source region113of n-LDMOS and source-body p-region118of n-LDMOS through p+-region112, and it is also connected to the terminal having the largest negative voltage. The n+-region203is the drain region of n-LDMOS and connected to the floating voltage terminal (TUB). The electrode GHof the control terminal stands for the gate electrode of the n-LDMOS. The shaded area121stands for the gate oxide or gate insulator. n-region108, p-region117and p+-region204are base region, collector region and emitter region of the pnp bipolar transistor, respectively. When the voltage drop across SHand DHis very large, i.e., the high-side device is turned off and the low-side device is turned on,204and117will be punched through, then there could be a large current. In order to avoid such a punch-through, the n-region108needs a high dose of doping and a large length and/or narrow width to generate certain voltage drop. The figure shown on the right is the equivalent circuit of the high-side device.

The deficiency of the device inFIG. 3is that: to make the pnp-transistor conduct, a voltage drop of 0.6˜0.8V across201and the portion of104underneath202is paid, and this increases the entire conduction voltage drop. Besides, the current density of injected minority carriers by the bipolar transistor is not proportional to the voltage drop across the junction, so it is difficult to keep the ratio of electron current density to hole current density be a certain ideal value. The present invention also proposes a method to replace the bipolar transistor mentioned above by using a p-MOSFET with a lower conduction voltage drop.

FIG. 7shows another three-terminal lateral power device with two types of carriers for conduction by using p-MOSFET to introduce hole current. Such device consists of two parts shown asFIG. 7(a) andFIG. 7(b) respectively.FIG. 7(a) shows a p-MOSFET implemented by using the basic voltage-sustaining structure in Ref. [3], andFIG. 7(b) shows an n-MOSFET to supply gate voltage for the p-MOSFET shown inFIG. 7(a). These two parts are implemented in neighboring surface regions, and the equivalent circuit of them is shown in right part ofFIG. 7. In this figure, D stands for the source electrode of p-MOSFET inFIG. 7(a) as well as the drain electrode of n-MOSFET inFIG. 7(b). S stands for the drain electrode of p-MOSFET inFIG. 7(a) as well as the source electrode of n-MOSFET inFIG. 7(b). G stands for the gate electrode of n-MOSFET inFIG. 7(b). It should be noted that the gate electrode GPis not an outer electrode but is directly connected by an inner connection to the n+-region300inFIG. 7(b) or to the output terminal of a built-in circuit where300is connected to an input terminal of the built-in circuit. In other words, the device shown inFIG. 7is still a three-terminal one.

When the voltage applied across G and the source-body region is larger than the threshold voltage of the n-MOSFET inFIG. 7(b), a current of electrons flow from n+-region200into the source region of n-MOSFET through n-region109, which acts as a resistor. When the electron current flows through such equivalent resistor, the value of the voltage of300is a negative one with respect to the largest voltage of electrode D. As300is connected to GPinFIG. 7(a), the value of the voltage of GPis a certain negative one with respect to the voltage of D. When such negative value is lower than the threshold voltage of the p-MOSFET, an inversion layer will be formed in the surface of104, and such inversion layer produces a channel for the hole current flowing from p+-region202to p-region103. To obtain such negative voltage for GPin a short distance, the dose in109inFIG. 7(b) should be smaller than that in104inFIG. 7(a). When the voltage applied to GPis appropriate, the p-MOSFET inFIG. 7(a) will introduce an hole current, while the n-MOSFET inFIG. 7(b) will introduce an electron current. Thus, a lateral three-terminal power device with two types of carriers for conduction can be implemented. And a compensation of the electric fluxes by two carriers of opposite signs in a not too large area can be achieved and the surface electric flux satisfying the optimum distribution can be realized.

FIG. 8shows another method for introducing a hole current by using a p-MOSFET, where the device also consists of two parts, which are shown asFIG. 8(a) andFIG. 8(b) respectively. The part shown inFIG. 8(a) includes a p-MOSFET and an n-MOSFET, wherein the voltage-sustaining region of n-MOSFET is implemented by using the basic voltage-sustaining structure in Ref. [3]; the part shown inFIG. 8(b) is the same as that inFIG. 7(b); the two parts shown inFIG. 8(a) andFIG. 8(b) are implemented in neighboring surface regions and the figure on the right is the equivalent circuit. Here, D stands for the source electrode of p-MOSFET inFIG. 8(a) as well as the both drain electrodes of n-MOSFETs inFIG. 8(a) andFIG. 8(b); S stands for the both source electrodes of n-MOSFETs inFIG. 8(a) andFIG. 8(b); G stands for the both gate electrodes of n-MOSFETs inFIG. 8(a) andFIG. 8(b); p-region103is the drain region of p-MOSFET inFIG. 8(a). Note that the gate electrode Gpof p-MOSFET inFIG. 8(b) is not an outer electrode, but is directly connected by an inner connection to the n+-region300inFIG. 8(b) or to the output terminal of a built-in circuit when300is connected to an input terminal of the built-in circuit. Thus, the device shown inFIG. 8is still a three-terminal device. Similar to the device shown inFIG. 7, when the voltage applied to G satisfies certain condition, the p-MOSFET will introduce a hole current. In comparison to the device shown inFIG. 7, the n-MOSFET inFIG. 8(a) can introduce a flow of electrons as well. Thus, the device shown inFIG. 8has a smaller specific on-resistance than that ofFIG. 7.

The purpose of the devices inFIG. 7andFIG. 8is to control the introduced holes not by any outer terminal. The method to combine such kind of device with the unipolar device shown as inFIG. 1(three terminals are connected correspondingly) also can make a lateral three-terminal power device with two types of carriers for conduction. In fact, the methods shown inFIG. 7,FIG. 8, and evenFIG. 3are only a part of the examples of the present invention, and there are other various methods to introduce holes. Similarly, the methods to introduce electrons are also various, and the methods mentioned above are only a part of the examples of the present invention. Moreover, there are many methods to introduce both hole current and electron current in a device while maintain a compensation of hole density and electron density within a not too large area.

FIG. 9schematically shows a top view of a device formed by integrating the devices mentioned above altogether. Here, the regions901,902,903,904stand for the devices shown inFIG. 1,FIG. 8(a),FIG. 7(b) (orFIG. 8(b)) andFIG. 7(a), respectively. The dashed line means isolation regions between two neighbouring devices. The density of electrons introduced by901,902and903is equal to the density of holes introduced by902and904within a not too large area. Obviously, such methods can be used to implement either high-side devices and/or low-side devices, and this is not to be repeated hereinafter.

Since the resistance109inFIG. 7(b) should be very large for supplying gate voltage to p-MOSFET, the current may flow into other adjacent region with lower resistance along the direction perpendicular to the paper, it then in turn makes the gate voltage being not enough to operating the p-MOSFET properly. Therefore, when the device shown inFIG. 7(a) and the one shown inFIG. 7(b) are implemented together in neighbouring surface regions, there must be an isolation region to isolate the electron current. This is also true for the device shown inFIG. 8.

FIG. 10shows a bird's eye view of using an isolation technique to implement the two devices shown inFIG. 8. There is an isolation region602between the devices ofFIG. 8(a) marked as603and ofFIG. 8(b) marked as601. Electrode S is connected through p+-region110to the source-body p-region106, thereby connected with p-region101. The n-region107can have a certain value of doping concentration, which is directly connected to substrate n-region100. The upper left portion shows the equivalent circuit of this figure.

FIG. 11schematically shows a cross-sectional view along the dash-line inFIG. 10. It can be seen from this figure that the isolation region602consists of an n-region107surrounded by p-region106and two sides of n-region102. To obtain the effect in Ref. [2-5], when602,601and603are fully depleted, the average value of flux density of602should between those of601and of603.

However, the isolation technique shown inFIG. 11brings out a restriction of the hole current and the electron current to flow in each separated device. Thus one kind of devices have excessive hole current and other kind of devices have excessive electron current. Especially, when the device ofFIG. 7(a) is in conduction state, it has only hole current, whereas the device inFIG. 7(b) has only electron current. Therefore, the introduced carriers distribute not uniformly in the combined structure, and the densities of introduced electrons and holes are different in different local region. This causes the surface electric flux density not satisfying said optimum distribution in Ref. [3]. Although this problem can be solved by making the width of each device to be very small, so that the surface electric flux in a small region can still satisfy said optimum distribution, the penalty is the density of isolation regions being increased.

FIG. 12shows another isolation method. In this figure,604stands for the isolation region between two devices. In contrast toFIG. 12, p-region103in different devices is connected each to other. With such a method, the device which originally has no hole current, e.g. the device shown inFIG. 7(b), now it has a flow of holes through p-region103. So the total hole current would distribute evenly in the whole region of the integrated device and the surface electric flux in a small region can satisfy said optimum distribution.

FIG. 13shows another isolation method similar toFIG. 12. In this figure, p-region101at the bottom and p-region103at the top of all devices are connected throughout the whole device. This method can make devices more compact. In this figure,605stands for isolation region. When the p-region106is fully depleted, it can obstruct the electron current flowing through the depletion region and thus plays a role of isolation.

It is obvious that for isolation region, instead of using p-n junction, dielectric isolation can also be used.FIG. 14shows a method by using a dielectric region for isolation to the structure shown inFIG. 11. Here,400stands for trenches filled with dielectric. Such method can avoid the disadvantage of increasing area caused by the lateral diffusion in the p-n junction isolation. Evidently, such a method has the same problem as stated aboutFIG. 11, that is, the surface electric flux in local region can not satisfy said optimum distribution.

FIG. 15andFIG. 16show the structures by using dielectric isolation to replace the p-n junction isolation inFIG. 12andFIG. 13, respectively. To compare with the structure shown inFIG. 14, the effective surface electric flux can satisfy the optimum distribution in a not too large area by modification of p-type region103. In addition, the technique of using dielectric can eliminate the leakage current between two neighboring device.

Naturally, the technique of SIS (silicon-insulator-silicon) can also be used for isolation, such as shown inFIG. 17. Here,500stands for the insulator layer. As the insulator layer has a higher critical electric field than that of silicon, a local strong electric field does not cause significant impact ionization, so the device has a better performance.

Despite all of the examples illustrated above are about that the control terminal directly controls the electron current and a hole current is simultaneously introduced due to the electron current, it is obvious that there are other kinds of devices with a control terminal to control the hole current and thereby an electron current is introduced.

FIG. 18shows a p-MOSFET only having holes for conduction. The voltage-sustaining region of the device consists of p-region701, n-region702, p-region703and a portion of n-region704as well as a portion of p-region706. Here S stands for the source electrode of p-region, connected both to p+-region802and source-body n-region704through n+-region801; p+-region712is the drain region of the p-MOSFET; G stands for the gate electrode, and the shaded area721stands for the gate oxide or gate insulator. The right portion of this figure shows the equivalent circuit of the device.

FIG. 19shows a three terminal device by using an npn transistor to introduce a flow of electrons initiated by a flow of holes produced by a p-MOSFET. The principle of the device is similar with the one shown inFIG. 3. Here, n+-region713, p-region709and n-region702are emitter region, base region and collector region of the npn transistor, respectively. The portion of p-region709with hole current flowing can be equivalent to a series resistor R shown in the figure. When there is a hole current flowing through the equivalent resistor, a voltage drop is developed across it, which makes the npn transistor conduct, and an electron current is formed. The figure on the right shows the equivalent circuit.

FIG. 20shows another three-terminal lateral power device with two types of carriers for conduction by using an n-MOSFET to introduce electron current. Such device consists of two parts, which are shown asFIG. 20(a) andFIG. 20(b), respectively.FIG. 20(a) shows an n-MOSFET implemented by using the basic voltage-sustaining structure inFIG. 18, andFIG. 20(b) shows a p-MOSFET to supply gate voltage for the n-MOSFET shown inFIG. 20(a). When the voltage applied to G respected to the source-body region of the p-MOSFET is a certain negative value, there is a hole current flowing from p+-region731into the drain region712of p-MOSFET through p-region736, which serves as a resistor. When the hole current flows through such a resistor, the voltage across the resistor is a positive one with respect to the electrode D, which has the lowest potential. The electrode Gnshown inFIG. 20(a) is connected to p+-region731. And when the voltage value of Gnwith respect to p-region706reaches a certain positive one, then an inversion layer is formed in the surface of706, making n-MOSFET conduct. Note that the structure shown inFIG. 20is again a three-terminal device by using the gate electrode of p-MOSFET as the control terminal and the gate electrode of n-MOSFET has an inner connection. The figure on the right portion shows an equivalent circuit of combination of the two parts.

FIG. 21shows another method to implement a lateral three-terminal device with two types of carriers for conduction by using n-MOSFET to introduce a flow of electrons. Here, the structure shown inFIG. 21(b) is the same with that inFIG. 20(b). As distinct from the device inFIG. 20(a), the device inFIG. 21(a) can introduce a flow of electrons as well. Thus, compared to the device inFIG. 20, the device inFIG. 21can have a smaller specific on-resistance. The figure on the right shows an equivalent circuit.

Similar toFIG. 7andFIG. 8, isolation regions must be set between the devices shown inFIG. 20(a) andFIG. 20(b) and between the devices shown inFIG. 21(a) andFIG. 21(b). Such isolation regions are used to obstruct the hole currents in the direction perpendicular to the paper. Apparently, the isolation method shown inFIG. 11can be used for this propose, with the same problem that the surface electric flux distribution deviates from the optimum one due to the existence of local excessive holes.

FIG. 22shows a method of isolation with connection of n-region702throughout all of the devices. By such method, the devices, e.g. shown inFIG. 20(b) orFIG. 21(b), which originally would have no electron for conduction, now turn out to have a flow of electrons introduced by other devices, so the surface electric flux distribution in every local region of the combination device can satisfy said optimum distribution. In this figure,611stands for the voltage-sustaining region of a device,613stands for the voltage-sustaining region of another device, and612stands for the isolation region between them. In the isolation method shown inFIG. 12,107is set between the two p-region106. Similarly, a p-region can be set in the middle of702to connect to p-region701. Here, such a p-region does not need to contact with p-region703, and even does not extend from701to the top. Certainly, the part of702between the two p-region can be replaced by a trench of dielectric, as shown inFIG. 23, wherein600stands for the dielectric isolation region.

A high-voltage CMOS can be realized by integrating the device of this invention utilizing the gate electrode of the p-MOSFET in it as the outer control terminal and the device of this invention utilizing the gate electrode of the n-MOSFET in it as the outer control terminal. This is shown inFIG. 24. Here, the largest negative voltage is applied to the electrode Dpand the smallest one is applied to the electrode Dp; the gate electrodes Gnand Gpare connected together as the input terminal of the CMOS and the electrodes Spand Snare connected together as the output terminal of the CMOS. The figure on the right shows the equivalent circuit of the CMOS.

Although the impurity profile in the above mentioned voltage-sustaining region is set as Ref. [4], it is evident that the methods of the present invention can be used in such cases as: the multilayer surface voltage-sustaining region by using the technique of RESURF or by using the technique of JTE with impurity profile made by two-sections with different values and other multilayer surface voltage-sustaining regions with other kinds of impurity profile.

Some examples of the present invention have been illustrated above. It should be understood that various other examples of application, which should be included in the scope of the present invention as defined in the claims, will be apparent to those skilled in the art.

Although the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. The object of choosing and describing the examples of the application of the present invention is for better explanation of the theory and practical applications. Apparently, the examples chosen above are for those skilled in the art to understand the present invention and thus be able to design various applications with various modifications for special utilizations.