THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

A thin film transistor includes a substrate, a gate, a gate insulating layer, a semiconductor layer, a first conductive layer, a covering layer and a sidewall protection layer. The gate is disposed on the substrate, the gate insulating layer is disposed on the gate, and the semiconductor layer is disposed on the gate insulating layer. The first conductive layer is disposed on the semiconductor layer, and the first conductive layer includes copper. The covering layer is disposed on an upper surface of the first conductive layer, and the covering layer includes copper nitride. The sidewall protection layer is disposed on a side surface of the first conductive layer, and the sidewall protection layer includes copper nitride.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin film transistor and a manufacturing method thereof, and more particularly to a thin film transistor and a manufacturing method thereof using copper as a material of conductive lines or electrodes.

2. Description of the Prior Art

In large-size display panels, copper is used as the material of conductive lines or electrodes in order to enhance the carrier mobility of thin film transistors. However, the oxidation or diffusion of copper may cause the electrical characteristics of thin film transistors unstable, which leads to poor display quality of the display panel.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is that when copper is used as the material of the conductive lines or electrodes of the thin film transistors in the display panel, the oxidation or diffusion of copper causes the electrical characteristics of the thin film transistors to be unstable.

To solve the above technical problem, the present invention provides a manufacturing method of a thin film transistor which includes following steps: providing a substrate; forming a gate on the substrate; forming a gate insulating layer on the gate; forming a semiconductor layer on the gate insulating layer; forming a source/drain conductive layer on the gate insulating layer and the semiconductor layer, the source/drain conductive layer includes a first conductive layer and a covering layer, the covering layer is disposed on an upper surface of the first conductive layer, the first conductive layer includes copper, and the covering layer includes copper nitride; and performing a patterning process to form a trench in the source/drain conductive layer, and the trench penetrates through the source/drain conductive layer.

To solve the above technical problem, the present invention also provides a method for manufacturing a thin film transistor which includes following steps: providing a substrate; forming a gate on the substrate; forming a gate insulating layer on the gate; forming a semiconductor layer on the gate insulating layer; forming a source/drain conductive layer on the gate insulating layer and the semiconductor layer, the source/drain conductive layer includes a first conductive layer, and the first conductive layer includes copper; performing a patterning process to form a trench in the source/drain conductive layer, and the trench penetrates through the source/drain conductive layer; and performing a nitridation treatment, the nitridation treatment forms a covering layer on an upper surface of the first conductive layer, the covering layer includes copper nitride, and the nitridation treatment is performed after the patterning process is performed.

To solve the above technical problem, the present invention provides a thin film transistor which includes a substrate, a gate, a gate insulation layer, a semiconductor layer, a drain and a source, and each of the drain and the source includes a first conductive layer and a covering layer. The gate is disposed on the substrate, the gate insulating layer is disposed on the gate, and the semiconductor layer is disposed on the gate insulating layer. The first conductive layer is disposed on the semiconductor layer and the gate insulating layer, and the first conductive layer includes copper. The covering layer is disposed on an upper surface of the first conductive layer, and the covering layer includes copper nitride.

In the thin film transistor and the manufacturing method thereof of the present invention, the copper nitride layer is formed above, below or on the side surface of the copper layer of the source and drain as the covering layer, the barrier layer or the sidewall protection layer, which can mitigate the oxidation and diffusion of copper and further improve the electrical characteristics of the thin film transistor. Using the copper nitride layer as the covering layer or barrier layer can prevent the edge of the covering layer or barrier layer from forming the chamfer due to etching and reduce the holes or cracks in the thin film transistor, thereby improving the reliability of the thin film transistor.

DETAILED DESCRIPTION

To provide a better understanding of the present invention to those skilled in this field, preferred embodiments will be detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings to elaborate on the contents and effects to be achieved. It should be noted that the drawings are simplified schematics, and therefore show only the components and combinations associated with the present invention, so as to provide a clearer description of the basic architecture or method of implementation. The components would be complex in reality. In addition, for ease of explanation, the components shown in the drawings may not represent their actual number, shape, and dimensions; details can be adjusted according to design requirements.

A direction DR1and a direction DR2are shown in the following drawings. The direction DR2may be perpendicular to a surface100F of a substrate100, the direction DR1may be parallel to the surface100F of the substrate100, and the direction DR2may be perpendicular to the direction DR1. The spatial relationship of structures can be described according to the directions DR1and DR2in the following drawings.

Referring toFIG.1toFIG.9,FIG.1toFIG.8are schematic cross-sectional diagrams illustrating a manufacturing method of a thin film transistor according to a first embodiment of the present invention, andFIG.9is a flowchart of the manufacturing method of the thin film transistor according to the present invention. The manufacturing method of the thin film transistor of this embodiment includes following steps. As shown inFIG.1andFIG.9, a step S100is first performed to provide the substrate100. The substrate100may be a rigid substrate such as a glass substrate, a plastic substrate, a quartz substrate or a sapphire substrate, but the material of the rigid substrate is not limited thereto. The substrate100may also be a flexible substrate such as polyimide (PI) substrate or polyethylene terephthalate (PET) substrate, but the material of the flexible substrate is not limited thereto.

Next, a step S102is performed to form a gate102on the substrate100. For example, a conductive layer may be formed on the surface100F of the substrate100, and a photolithography-etching process may be performed on the conductive layer to form the gate102, but not limited thereto. In this disclosure, the photolithography-etching process may for example include forming a photoresist on a material layer (such as the above-mentioned conductive layer), exposing the photoresist by a light source through a mask, developing the photoresist to pattern the photoresist, and etching the material layer with the patterned photoresist as a mask to pattern the material layer (for example, patterning the conductive layer to form the gate102). The gate102may include conductive materials, such as metal, but not limited thereto.

Next, a step S104is performed to form a gate insulating layer104on the gate102. For example, the gate insulating layer104may be disposed on the gate102and the surface100F of the substrate100, but not limited thereto. In some embodiments, the gate insulating layer104may include an insulating layer106and an insulating layer108. The insulating layer106may be disposed on the gate102and the surface100F of the substrate100, the insulating layer108may be disposed on the insulating layer106, and the insulating layer106may be disposed between the substrate100and the insulating layer108, but not limited thereto. In some embodiments, the gate insulating layer104may include only one insulating layer.

The insulating layer106or the insulating layer108may include inorganic insulating materials, such as silicon oxide, silicon nitride or a combination of the above, but not limited thereto. For example, the insulating layer108includes silicon oxide and the insulating layer106includes silicon nitride. Other layers or devices may be disposed between the gate insulating layer104and the substrate100or between the gate102and the substrate100.

Next, a step S106is performed to form a semiconductor layer110on the gate insulating layer104. For example, a semiconductor material layer may be formed on the gate insulating layer104(such as the insulating layer108) first, and the photolithography-etching process may be performed on the semiconductor material layer to form the semiconductor layer110, but not limited thereto. In the present invention, the semiconductor layer110may include metal oxide semiconductor, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) or a combination of the above, but the material of the metal oxide semiconductor is not limited thereto.

Next, as shown inFIG.2,FIG.3andFIG.9, a step S108is performed to form a source/drain conductive layer112on the gate insulating layer104and the semiconductor layer110. As shown inFIG.2, a conductive layer116can be formed on the gate insulating layer104and the semiconductor layer110, and the conductive layer116includes molybdenum, but not limited thereto. The conductive layer116may include other suitable metals or alloys. Then, a conductive layer114can be formed on the conductive layer116, and the conductive layer114includes copper. In this disclosure, the conductive layer114may be referred to as the first conductive layer114and the conductive layer116may be referred to as the second conductive layer116. The conductive layer114and the conductive layer116can be formed by a physical vapor deposition process, but not limited thereto.

In some embodiments, the conductive layer114and the conductive layer116can be formed by the same physical vapor deposition apparatus, and a copper target and a molybdenum target can be provided in the same chamber to respectively form the conductive layer114and the conductive layer116, but not limited thereto. In some embodiments, the conductive layer114and the conductive layer116can be formed by the same physical vapor deposition apparatus, but the conductive layer114and the conductive layer116can be formed in different chambers. In some embodiments, the conductive layer114and the conductive layer116can be formed by different physical vapor deposition apparatus.

As shown inFIG.3, a covering layer118is formed on the conductive layer114, and the covering layer118includes copper nitride. In this embodiment, the source/drain conductive layer112includes the conductive layer116, the conductive layer114and the covering layer118. In some embodiments, a reactive physical vapor deposition process can be performed to form the covering layer118on an upper surface114F of the conductive layer114, but not limited thereto.

For example, as shown inFIG.2andFIG.4, after the structure inFIG.2is formed, the process of forming the covering layer118on the upper surface114F of the conductive layer114ofFIG.2by the reactive physical vapor deposition process120may include following steps. A copper target122is provided, the copper target122can be electrically connected to the cathode of a power supply device124, and the anode of the power supply device124can be grounded. Nitrogen (such as nitrogen gas) is provided and can be used as a reaction gas to form copper nitride on the copper target122. As shown inFIG.4, nitrogen ions N+or N+2can react with the surface layer on the surface of the copper target122to form a copper nitride film126. Argon (such as argon gas) is provided and can be used as sputtering gas to bombard the copper nitride (such as the copper nitride film126) on the copper target122with argon ions Art Therefore, the copper nitride CuNxis deposited on the upper surface114F of the conductive layer114, and the covering layer118can be formed on the upper surface114F of the conductive layer114.

The reactive physical vapor deposition process120can be performed in the physical vapor deposition apparatus. In some embodiments, the reactive physical vapor deposition process120and the step of forming the conductive layer114can be performed in the same physical vapor deposition apparatus and in the same chamber having the copper target, but not limited thereto. For example, after the conductive layer114is formed in the physical vapor deposition apparatus, the covering layer118is formed on the upper surface114F of the conductive layer114by the reactive physical vapor deposition process120in the same vacuum condition. Therefore, the manufacturing time and cost can be saved.

Next, as shown inFIG.5andFIG.9, a step S110is performed to perform a patterning process128on the source/drain conductive layer112to pattern the conductive layers114and116and the covering layer118to respectively form the conductive layers114P and116P and the covering layer118P. The patterning process128forms a trench130in the source/drain conductive layer112. The trench130penetrates through the source/drain conductive layer112(i.e., penetrating through the conductive layers114and116and the covering layer118), and the trench130exposes a side surface114S of the conductive layer114P, a side surface116S of the conductive layer116P, a side surface118S of the covering layer118P and a portion of an upper surface110F of the semiconductor layer110.

The patterning process128may include the photolithography-etching process. For example, a patterned photoresist132may be formed on the source/drain conductive layer112(i.e., formed on the covering layer118) by the photolithography process of the patterning process128. The patterned photoresist132may have an opening, and the opening corresponds to the location where the trench130is formed. The trench130may be formed by the etching process of the patterning process128, and the trench130may penetrate through the conductive layers114and116and the covering layer118and may expose a portion of the upper surface110F of the semiconductor layer110. The patterned photoresist132can be removed after the patterning process128. In this disclosure, the conductive layers114and116and the covering layer118have yet been etched can also be respectively referred to as the conductive material layers114and116and the covering material layer118.

Next, the advantages of the covering layer118including copper nitride in this embodiment will be explained. For example, if the covering layer118includes molybdenum, the edge of the covering layer118P adjacent to the trench130may form a chamfer after the etching process for forming the trench130is performed since the etching rates of molybdenum and copper are different. Therefore, when an insulating layer142is formed in the subsequent step S116(referring toFIG.8andFIG.9), holes or cracks are easily formed in the insulating layer142in the trench130since the chamfer of the edge of the covering layer118P may be not completely filled in with the insulating layer142, thereby decreasing reliability of the thin film transistor. However, when the covering layer118includes copper nitride, the chamfer can be prevented from forming on the edge of the covering layer118P adjacent to the trench130after the etching process for forming the trench130is performed since the etching rates of copper nitride and copper are relatively close, thereby improving the reliability of the thin film transistor.

Next, as shown inFIG.6andFIG.9, a step S112is performed to perform a nitridation treatment134. The nitridation treatment134forms a sidewall protection layer136on the side surface114S of the conductive layer114P and a sidewall protection layer138on the side surface116S of the conductive layer116P. In this disclosure, the sidewall protection layer136may be referred to as the first sidewall protection layer, and the sidewall protection layer138may be referred to as the second sidewall protection layer. The sidewall protection layer136includes copper nitride and the sidewall protection layer138includes molybdenum nitride, but the material of the sidewall protection layer138is not limited thereto. After the step S112is performed, the fabrication of the drain DE and the source SE of the thin film transistor may be completed. The drain DE and the source SE are opposite to each other and a gap GP is located between the drain DE and the source SE, and each of the drain DE and the source SE can include the conductive layers114P,116P, the covering layer118P and the sidewall protection layers136,138.

The nitridation treatment134can be performed in a chemical vapor deposition apparatus, and the nitridation treatment134can include providing argon (such as argon gas) first and providing nitrogen (such as nitrogen gas) next to form the sidewall protection layer136and the sidewall protection layer138in a plasma environment. The temperature of the plasma environment may be less than 220° C., but not limited thereto. Argon can be provided first to remove pollutants on the side surface114S of the conductive layer114P and the side surface116S of the conductive layer116P and activate the bonding on the side surface114S and the side surface116S. Next, nitrogen is provided, and dissociated nitrogen ions react with copper on the side surface114S of the conductive layer114P to form copper nitride (i.e., the sidewall protection layer136), and the dissociated nitrogen ions react with molybdenum on the side surface116S of the conductive layer116P to form molybdenum nitride (i.e., the sidewall protection layer138).

Next, as shown inFIG.7andFIG.9, a step S114is performed to perform an oxygen-containing repairing treatment140. Since the upper surface110F of the semiconductor layer110may be damaged in the etching process of the patterning process128used to form the trench130(referring toFIG.5), the oxygen-containing repairing treatment140can be performed to repair defects in the semiconductor layer110. In the oxygen-containing repairing treatment140, an oxygen-containing gas may be provided for repairing the semiconductor layer110. The oxygen-containing gas may include oxygen or nitrous oxide, but not limited thereto. In addition, the oxygen-containing repairing treatment140can be performed in the chemical vapor deposition apparatus. Therefore, the steps of nitridation treatment134and the oxygen-containing repairing treatment140can be sequentially performed in the same chemical vapor deposition apparatus for saving the manufacturing time and cost.

Since the oxygen-containing repairing treatment140is performed after the nitridation treatment134is performed (i.e., after the sidewall protection layer136and the sidewall protection layer138is formed), the covering layer118P and the sidewall protection layer136have been respectively formed on the upper surface114F and the side surface114S of the conductive layer114P, and the sidewall protection layer138has been formed on the side surface116S of the conductive layer116P when the oxygen-containing repairing treatment140is performed. The covering layer118P and the sidewall protection layer136can be used as an oxidation prevention layer of the conductive layer114P, and the sidewall protection layer138can be used as the oxidation prevention layer of the conductive layer116P, and oxygen molecules can be prevented from reacting with the conductive layers114P and116P. Therefore, the oxidation of copper in the conductive layer114P and the oxidation of molybdenum in the conductive layer116P in the oxygen-containing repairing treatment140can be mitigated, thereby improving the electrical characteristics of the thin film transistor.

Next, as shown inFIG.8andFIG.9, a step S116is performed to form an insulating layer142. The insulating layer142is disposed on the drain DE, the source SE and the semiconductor layer110and in the gap GP between the drain DE and the source SE. The insulating layer142is disposed in the gap GP and covers the semiconductor layer110including metal oxide semiconductor, thus the insulating layer142may include an insulating material including oxygen, but not limited thereto. The material of the insulating layer142may for example include silicon oxide, aluminum oxide or titanium oxide, but not limited thereto.

Although the insulating layer142including oxygen is disposed on the drain DE and the source SE and in the gap GP between the drain DE and the source SE, the covering layer118P and the sidewall protection layer136can be used as the oxidation prevention layer of the conductive layer114P to mitigate the oxidation of copper in the conductive layer114P. Similarly, the sidewall protection layer138can be used as the oxidation prevention layer of the conductive layer116P to mitigate the oxidation of molybdenum in the conductive layer116P. The covering layer118P and the sidewall protection layer136can also mitigate the diffusion of copper in the conductive layer114P. Therefore, the electrical characteristics of the thin film transistor can be improved.

In addition, the insulating layer142can be formed in the chemical vapor deposition apparatus. Therefore, the step of nitridation treatment134, the step of oxygen-containing repairing treatment140and the step of forming the insulating layer142can be sequentially performed in the same chemical vapor deposition apparatus, thereby saving the manufacturing time and cost.

In this embodiment, the manufacturing method of the thin film transistor includes the nitridation treatment134, and the nitridation treatment134is performed after the patterning process128is performed. The nitridation treatment134can form the sidewall protection layer136including copper nitride on the side surface114S of the conductive layer114P including copper. In addition, the nitridation treatment134is performed before the oxygen-containing repairing treatment140and the step of forming oxygen-containing insulating layer142is performed, the sidewall protection layer136can prevent the oxygen in the oxygen-containing repairing treatment140and the oxygen in the insulating layer142from entering the conductive layer114P from the side surface114S of the conductive layer114P, and the oxidation of copper can be mitigated.

Specifically, in this embodiment, the covering layer118P and the sidewall protection layer136including copper nitride are used as the oxidation prevention layer of the conductive layer114P and respectively formed on the upper surface114F and the side surface114S of the conductive layer114P including copper, so as to prevent the upper surface114F and the side surface114S of the conductive layer114P from reacting with oxygen, thereby mitigating the oxidation of copper in the conductive layer114P and further improving the electrical characteristics of the thin film transistor.

As shown inFIG.8, a thin film transistor10of this embodiment can include the substrate100, the gate102, the gate insulating layer104, the semiconductor layer110, the conductive layer114P, the covering layer118P, the sidewall protection layer136and the insulating layer142. The gate102is disposed on the substrate100, the gate insulating layer104is disposed on the gate102, and the semiconductor layer110is disposed on the gate insulating layer104. The conductive layer114P is disposed on the semiconductor layer110and the gate insulating layer104, and the conductive layer114P includes copper. The covering layer118P is disposed on the upper surface114F of the conductive layer114P, and the covering layer118P includes copper nitride. The sidewall protection layer136is disposed on the side surface114S of the conductive layer114P, and the sidewall protection layer136includes copper nitride.

The thin film transistor10further includes the conductive layer116P disposed between the conductive layer114P and the semiconductor layer110and between the conductive layer114P and the gate insulating layer104, and the conductive layer116P includes molybdenum. The conductive layer116P can be used as a barrier layer of the conductive layer114P to mitigate the diffusion of copper in the conductive layer114P. The thin film transistor10further includes the sidewall protection layer138disposed on the side surface116S of the conductive layer116P, and the sidewall protection layer138includes molybdenum nitride.

In some embodiments, one of the drain DE and the source SE includes the conductive layer116P, the conductive layer114P, the covering layer118P, the sidewall protection layer136and the sidewall protection layer138disposed on one side of the semiconductor layer110, and the other one of the drain DE and the source SE includes another conductive layer116P, another conductive layer114P, another covering layer118P, another sidewall protection layer136and another sidewall protection layer138disposed on the other side of the semiconductor layer110, and the drain DE and the source SE respectively couple to one side of the semiconductor layer110and the other side of the semiconductor layer110

The gap GP is disposed between the drain DE and the source SE, the sidewall protection layer136is disposed between the conductive layer114P and the gap GP in the direction DR1, and the sidewall protection layer138is disposed between the conductive layer116P and the gap GP in the direction DR1.

The thin film transistor10further includes the insulating layer142disposed on a portion of the upper surface110F of the semiconductor layer110and the covering layer118P and filled in the gap GP between the drain DE and the source SE. The sidewall protection layer136is disposed between the conductive layer114P and the insulating layer142in the direction DR1, and the sidewall protection layer138is disposed between the conductive layer116P and the insulating layer142in the direction DR1.

The thin film transistor and the manufacturing method thereof of the present invention are not limited to the aforementioned embodiments. The following will continue to disclose other embodiments of the present invention. However, in order to simplify the description and highlight the differences between the embodiments, the same reference numerals are used to denote the same elements hereinafter, and the repeated portions will not be described again.

Referring toFIG.10toFIG.13,FIG.10toFIG.13are schematic cross-sectional diagrams of a manufacturing method of a thin film transistor according to a second embodiment of the present invention, and the flowchart of the manufacturing method of the thin film transistor according to the second embodiment can also refer toFIG.9. As shown inFIG.9, the steps S100, S102, S104and S106can be performed, and the schematic cross-sectional diagrams corresponding to the steps S100, S102, S104and S106of this embodiment can refer toFIG.1.

Next, as shown inFIG.10andFIG.9, the step S108is performed to form a source/drain conductive layer112A on the gate insulating layer104and the semiconductor layer110, and the source/drain conductive layer112A includes the conductive layer114and the conductive layer116. Comparing to the source/drain conductive layer112including the conductive layers114and116and the covering layer118in the first embodiment, the source/drain conductive layer112A in this embodiment does not include the covering layer118.

Next, as shown inFIG.11andFIG.9, the step S110is performed, and the patterning process128is performed on the source/drain conductive layer112A to pattern the conductive layers114and116to respectively form the conductive layers114P and116P. The patterning process128forms the trench130A in the source/drain conductive layer112A, and the trench130A penetrates through the source/drain conductive layer112A (i.e., penetrating through the conductive layers114and116).

In this embodiment, the patterning process128may include the photolithography-etching process. For example, the patterned photoresist132can be formed on the source/drain conductive layer112A (i.e., formed on the conductive layer114) by the photolithography process of the patterning process128. The patterned photoresist132may have an opening corresponding to the location where the trench130A is formed. The trench130A may be formed by the etching process of the patterning process128. The trench130A penetrates through the conductive layers114and116of the source/drain conductive layer112A, and the trench130A exposes the side surface114S of the conductive layer114P, the side surface116S of the conductive layer116P and a portion of the upper surface110F of the semiconductor layer110. The patterned photoresist132can be removed after the patterning process128.

Next, as shown inFIG.12andFIG.9, the step S112is performed to perform the nitridation treatment134. The nitridation treatment134can simultaneously form the covering layer118P on the upper surface114F of the conductive layer114P and the sidewall protection layer136on the side surface114S of the conductive layer114P, and each of the covering layer118P and the sidewall protection layer136includes copper nitride. Similar to the first embodiment, the nitridation treatment134can be performed in the chemical vapor deposition apparatus, and the nitridation treatment134includes providing argon first and providing nitrogen next in the plasma environment to form the covering layer118P and the sidewall protection layer136.

In the first embodiment, the process of forming the covering layer118on the upper surface114F of the conductive layer114is performed before the patterning process128, and the patterning process128patterns the covering layer118to form the covering layer118P. However, in this embodiment, the process of forming the covering layer118on the upper surface114F of the conductive layer114before the patterning process128is not required, the covering layer118P can be formed on the upper surface114F of the conductive layer114P and the sidewall protection layer136can be formed on the side surface114S of the conductive layer114P simultaneously by the nitridation treatment134. Therefore, the manufacturing time and cost can further be saved in this embodiment comparing to the first embodiment.

In addition, the sidewall protection layer138can also be formed on the side surface116S of the conductive layer116P in the nitridation treatment134, and the sidewall protection layer138includes molybdenum nitride, but the material of the sidewall protection layer138is not limited thereto. After the nitridation treatment134is performed, the fabrication of the drain DE and the source SE of the thin film transistor may be completed. The drain DE and the source SE are opposite to each other and the gap GP is located between the drain DE and the source SE, and each of the drain DE and the source SE can include the conductive layers114P,116P, the covering layer118P, and the sidewall protection layers136,138.

In the nitridation treatment134, argon may be provided first to remove the pollutants on the upper surface114F and side surface114S of the conductive layer114P and the side surface116S of the conductive layer116P and activate the bonding on the upper surface114F, the side surface114S and the side surface116S. Next, nitrogen is provided, and the dissociated nitrogen ions react with copper on the upper surface114F and the side surface114S of the conductive layer114P to form copper nitride (i.e., the covering layer118P and the sidewall protection layer136), and the dissociated nitrogen ions react with molybdenum on the side surface116S of the conductive layer116P to form molybdenum nitride (i.e., the sidewall protection layer138).

Next, as shown inFIG.9, the step S114is performed to perform the oxygen-containing repairing treatment140. The schematic cross-sectional diagram corresponding to the step S114of this embodiment can refer toFIG.7of the first embodiment.

Next, as shown inFIG.13andFIG.9, the step S116is performed to form the insulating layer142. The insulating layer142is disposed on the drain DE, the source SE and the semiconductor layer110and in the gap GP between the drain DE and the source SE.

Referring toFIG.14toFIG.17,FIG.14toFIG.17are schematic cross-sectional diagrams of a manufacturing method of a thin film transistor according to a first variant embodiment of the first embodiment of the present invention, and the flowchart of the manufacturing method of the thin film transistor of the first variation of the first embodiment can also refer toFIG.9.

As shown inFIG.9, the steps S100, S102, S104, S106and S108are performed, the schematic cross-sectional diagrams corresponding to the steps S100, S102, S104and S106of this embodiment can refer toFIG.1, and the schematic cross-sectional diagrams corresponding to the step S108of this embodiment can refer toFIG.2andFIG.3. The difference between this variant embodiment and the first embodiment is that the conductive layer116in the first embodiment includes molybdenum but the conductive layer116in this variant embodiment includes copper nitride.

As shown inFIG.14, the step inFIG.14can be performed after the step inFIG.1. In this variant embodiment, the copper nitride film can be formed on the gate insulating layer104and the semiconductor layer110by the reactive physical vapor deposition process120, and the copper nitride film is used as the conductive layer116. The details of the reactive physical vapor deposition process120have been introduced in the first embodiment, and will not be described again.

Next, as shown inFIG.15, the conductive layer114can be formed by a physical vapor deposition process144. For example, the supply of nitrogen is stopped and the supply of argon is continued after the conductive layer116is formed, the copper target122is bombarded with argon ions Art, and copper Cu is deposited on the conductive layer116to form the conductive layer114. The method of forming the conductive layer116and the conductive layer114in this variant embodiment is not limited to the example inFIG.14andFIG.15. In addition, the method of forming the covering layer118in this variant embodiment can refer to the first embodiment, and will not be described again.

Next, as shown inFIG.9, the step S110is performed to perform the patterning process128on the source/drain conductive layer112to pattern the conductive layers114and116and the covering layer118to respectively form the conductive layers114P and116P and the covering layer118P. The schematic cross-sectional diagram corresponding to the step S110of this embodiment can refer toFIG.5.

Next, as shown inFIG.16andFIG.9, the step S112is performed to perform the nitridation treatment134. The nitridation process134can form the sidewall protection layer136on the side surface114S of the conductive layer114P, and the sidewall protection layer136includes copper nitride. After the nitridation treatment134is performed, the fabrication of a drain DE_A and a source SE_A of the thin film transistor may be completed. The drain DE_A and the source SE_A are opposite to each other and a gap GP_A is located between the drain DE_A and the source SE_A, and each of the drain DE_A and the source SE_A can include the conductive layers114P,116P, the covering layer118P and the sidewall protection layer136.

Next, as shown inFIG.9, the steps S114and S116are sequentially performed, that is, the oxygen-containing repairing treatment140and the step of forming the insulating layer142in the steps S114and S116are sequentially performed to form a thin film transistor10_A inFIG.17. As shown inFIG.17, in this embodiment, each of the conductive layer116P and the covering layer118P includes copper nitride, the conductive layer114P includes copper, and the sidewall protection layer136on the side surface114S of the conductive layer114P includes copper nitride. In addition, the insulating layer142is disposed on the drain DE_A, the source SE_A (seeFIG.16for DE_A and SE_A) and the semiconductor layer110and in the gap GP_A between the drain DE_A and the source SE_A.

Since the conductive layer116P is disposed between the conductive layer114P and the semiconductor layer110, and the conductive layer116P includes copper nitride, the conductive layer116P can be used as the barrier layer to mitigate the phenomenon that copper in the conductive layer114P diffuses to the semiconductor layer110, thereby improving the electrical characteristics of the thin film transistor.

Next, the manufacturing method of the thin film transistor of the first variant embodiment of the second embodiment of the present invention will be described, and the flowchart of the manufacturing method of the thin film transistor of the first variant embodiment of the second embodiment can also refer toFIG.9.

As shown inFIG.9, the steps S100, S102, S104, S106and S108are performed, the schematic cross-sectional diagrams corresponding to the steps S100, S102, S104and S106of this embodiment can refer toFIG.1, and the schematic cross-sectional diagram corresponding to the step S108of this embodiment can refer toFIG.10. The difference between this variant embodiment and the second embodiment is that the conductive layer116in the second embodiment includes molybdenum but the conductive layer116in this variant embodiment includes copper nitride.

Next, the step S110shown inFIG.9is performed, and the schematic cross-sectional diagram of the step S110in this variant embodiment can refer toFIG.11. The patterning process128is performed on the source/drain conductive layer112A to pattern the conductive layers114and116to respectively form the conductive layers114P and116P.

Next, as shown inFIG.9, the step S112is performed to perform the nitridation treatment134. The schematic cross-sectional diagram of the step S112of this variant embodiment can refer toFIG.16. The nitridation treatment134can form the covering layer118P on the upper surface114F of the conductive layer114P and the sidewall protection layer136on the side surface114S of the conductive layer114P simultaneously, and each of the covering layer118P and the sidewall protection layer136includes copper nitride. After the nitridation treatment134is performed, the fabrication of the drain DE_A and the source SE_A of the thin film transistor may be completed. The drain DE_A and the source SE_A are opposite to each other and the gap GP_A is located between the drain DE_A and the source SE_A, and each of the drain DE_A and the source SE_A can include the conductive layers114P,116P, the covering layer118P and the sidewall protection layer136.

Next, as shown inFIG.9, the steps S114and S116are sequentially performed, that is, the oxygen-containing repairing treatment140and the step of forming the insulating layer142in the steps S114and S116are sequentially performed to form the thin film transistor10_A inFIG.17.

Referring toFIG.18toFIG.21,FIG.18toFIG.21are schematic cross-sectional diagrams of a manufacturing method of a thin film transistor according to a second variant embodiment of the first embodiment of the present invention, and the flowchart of the manufacturing method of the thin film transistor of the second variant embodiment of the first embodiment can also refer toFIG.9. Different from the first embodiment, a conductive layer146is disposed between the conductive layer116and the conductive layer114in this embodiment, and the conductive layer146includes copper nitride. In this disclosure, the conductive layer146may be referred to as the third conductive layer.

As shown inFIG.9, the steps S100, S102, S104, S106and S108are performed, the schematic cross-sectional diagrams corresponding to the steps S100, S102, S104and S106of this embodiment can refer toFIG.1.

Next, as shown inFIG.18andFIG.9, the step S108is performed to form the source/drain conductive layer112B on the gate insulating layer104and the semiconductor layer110. The source/drain conductive layer112B includes the covering layer118, the conductive layer114, the conductive layer146and the conductive layer116. The conductive layer146is disposed between the conductive layer114and the conductive layer116, and the conductive layer146includes copper nitride. For example, the conductive layer146can be formed on the conductive layer116by the reactive physical vapor deposition process120, but not limited thereto. The conductive layer116includes molybdenum, but not limited thereto. The conductive layer116may include other suitable metals or alloys.

Next, as shown inFIG.19andFIG.9, the step S110is performed to perform the patterning process128on the source/drain conductive layer112B to pattern the conductive layers114,146and116and the covering layer118to respectively form the conductive layers114P,146P and116P and the covering layer118P. In this disclosure, the conductive layers114,146and116and the covering layer118have yet been etched can respectively be referred to as the conductive material layers114,146and116and the covering material layer118. The patterning process128forms a trench130B in the source/drain conductive layer112B. The trench130B penetrates through the source/drain conductive layer112B (i.e., penetrating through the conductive layers114,146, and116and the covering layer118), and the trench130B exposes the side surface116S of the conductive layer116P, the side surface146S of the conductive layer146P, the side surface114sof the conductive layer114P, the side surface118S of the covering layer118P and a portion of the upper surface110F of the semiconductor layer110.

Next, as shown inFIG.20andFIG.9, the step S112is performed to perform the nitridation treatment134. The nitridation treatment134can form the sidewall protection layer136on the side surface114S of the conductive layer114P and the sidewall protection layer138on side surface116S of conductive layer116P. The sidewall protection layer136includes copper nitride and the sidewall protection layer138includes molybdenum nitride, but the material of the sidewall protection layer138is not limited thereto. After the nitridation treatment134is performed, the fabrication of the drain DE_B and the source SE_B of the thin film transistor may be completed. The drain DE_B and the source SE_B are opposite to each other and a gap GP_B is located between the drain DE_B and the source SE_B, and each of the drain DE_B and the source SE_B can include the conductive layers114P,116P,146P, the covering layer118P and the sidewall protection layers136,138.

Next, as shown inFIG.9, the steps S114and S116are sequentially performed, that is, the oxygen-containing repairing treatment140and the step of forming the insulating layer142in the steps S114and S116are sequentially performed to form a thin film transistor10_B inFIG.21. As shown inFIG.21, the insulating layer142is disposed on the drain DE_B, the source SE_B and the semiconductor layer110and in the gap GP_B between the drain DE_B and the source SE_B.

In this embodiment, the conductive layer146P is disposed between the conductive layer116P and the conductive layer114P, and the conductive layer116P and the conductive layer146P can be used as double barrier layers to mitigate the phenomenon that copper in the conductive layer114P diffuses to the semiconductor layer110, thereby improving the electrical characteristics of the thin film transistor.

Referring toFIG.22toFIG.24,FIG.22toFIG.24are schematic cross-sectional diagrams of a manufacturing method of a thin film transistor according to a second variant embodiment of the second embodiment of the present invention, and the flowchart of the manufacturing method of the thin film transistor in the second variant embodiment of the second embodiment can also refer toFIG.9. Different from the second embodiment, the conductive layer146is disposed between the conductive layer116and the conductive layer114in this embodiment, and the conductive layer146includes copper nitride.

As shown inFIG.9, the steps S100, S102, S104and S106are performed, the schematic cross-sectional diagrams corresponding to the steps S100, S102, S104and S106of this embodiment can refer toFIG.1.

Next, as shown inFIG.22andFIG.9, the step S108is performed to form a source/drain conductive layer112C on the gate insulating layer104and the semiconductor layer110. The source/drain conductive layer112C includes the conductive layer114, the conductive layer146and the conductive layer116, the conductive layer146is disposed between the conductive layer114and the conductive layer116, and the conductive layer146includes copper nitride. The conductive layer116includes molybdenum, but not limited thereto. The conductive layer116may include other suitable metals or alloys.

Next, as shown inFIG.23andFIG.9, the step S110is performed to perform the patterning process128on the source/drain conductive layer112C to pattern the conductive layers114,146and116to respectively form the conductive layers114P,146P and116P. The patterning process128forms a trench130C in the source/drain conductive layer112C. The trench130C penetrates through the source/drain conductive layer112C (i.e., penetrating through the conductive layers114,146and116), and the trench130C exposes the side surface114S of the conductive layer114P, the side surface116S of the conductive layer116P, the side surface146S of the conductive layer146P and a portion of the upper surface110F of the semiconductor layer110F.

Next, as shown inFIG.24andFIG.9, the step S112is performed to perform the nitridation treatment134. The nitridation treatment134may form the covering layer118P on the upper surface114F of the conductive layer114P, and the sidewall protection layers136and138respectively on the side surface114S of the conductive layer114P and the side surface116S of the conductive layer116P. Each of the covering layer118and the sidewall protection layer136includes copper nitride, and the sidewall protection layer138includes molybdenum nitride, but the material of the sidewall protection layer138is not limited thereto. After the nitridation treatment134is performed, the fabrication of the drain DE_B and the source SE_B of the thin film transistor may be completed. The drain DE_B and the source SE_B are opposite to each other and the gap GP_B is located between the drain DE_B and the source SE_B, and each of the drain DE_B and the source SEB can include the conductive layers114P,116P,146P, the covering layer118P and the sidewall protection layers136,138.

Next, as shown inFIG.9, the steps S114and S116are sequentially performed, that is, the oxygen-containing repairing treatment140and the step of forming the insulating layer142in the steps S114and S116are sequentially performed to form the thin film transistor10_B inFIG.21.

In summary, in the thin film transistor and the manufacturing method thereof of the present invention, the copper nitride layer is formed above, below or on the side surface of the copper layer of the source and drain as the covering layer, the barrier layer or the sidewall protection layer, which can mitigate the oxidation and diffusion of copper and further improve the electrical characteristics of the thin film transistor. Using the copper nitride layer as the covering layer can prevent the edge of the covering layer from forming the chamfer due to etching and reduce the holes or cracks in the thin film transistor, thereby improving the reliability of the thin film transistor.