Semiconductor structure with airgap

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

FIELD OF THE INVENTION

The invention relates to semiconductor structures and, more particularly, to a field effect transistor (FET) with an underlying airgap and methods of manufacture.

BACKGROUND

RF switches are significantly easier to make on silicon on insulator (SOI) substrates than on bulk substrates because all junctions are bounded by oxide (STI laterally and the buried oxide below) which eliminates the problem of dropping large voltages across well to substrate junctions. SOI also has low junction capacitances which reduces loading on RF signals. However, it is often advantageous to integrate an RF switch into a bulk process. This can be done with a triple well and very high resistivity substrates, but is a challenge as the RF voltages still must be dropped across a junction, and the large depletion layers in high resistivity substrates add substantial area to the layout.

SUMMARY

In an aspect of the invention, a method comprises forming an amorphous layer at a predetermined depth of a substrate. The method further comprises forming an airgap in the substrate under the amorphous layer. The method further comprises forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

In an aspect of the invention, a method comprises forming at least one deep trench structure in a bulk substrate, on sides of an active region. The method further comprises forming sidewall structures on sidewalls of the at least one deep trench structure, which acts as an etch stop layer. The method further comprises forming a lateral undercut in the bulk substrate starting at a bottom of the at least one deep trench structure. The method further comprises filling the at least one deep trench structure with material to form an airgap from the lateral undercut in the bulk substrate under the active region.

In an aspect of the invention, a structure comprises: an amorphous layer under an active region of a substrate; an airgap in the substrate under the amorphous layer; and a completely isolated transistor in the active region, above the amorphous layer and the airgap and surrounded by shallow trench isolation regions.

DETAILED DESCRIPTION

The invention relates to semiconductor structures and, more particularly, to a field effect transistor (FET) with an underlying airgap and methods of manufacture. In more specific embodiments, the present invention is directed to an RF switch FET manufactured in bulk technology with an airgap underneath its transistor channel. In embodiments, the present invention provides a completely isolated, e.g., oxide isolated, switch FET integrated onto the bulk process.

In embodiments, the FET is a bulk CMOS transistor with an underlying airgap. The location of the airgap, e.g., top of the airgap, is determined by an etch barrier directly under and in contact with the transistor channel and source and drain regions. In embodiments, the etch barrier layer is an amorphous layer formed by an ion implantation process. In further embodiments, the location of the sides and/or the bottom of the airgap can be determined by the etch barrier layer. The airgap, on the other hand, can be formed by NH4OH wet etch of silicon, where the etch access to the silicon is from a top surface opening. In alternative embodiments, the etch access to the silicon is from the bottom of a deep trench which has sidewall spacers, and the airgap is formed by XeF2dry etch of silicon.

Advantageously, the structures of the present invention fully isolate the FET so that there is no junction which connects the transistor to the substrate. The FET of the present invention is also integrated into standard bulk silicon processing without disturbing adjacent elements. Additionally, the present invention eliminates the problem of dropping large voltages across well to substrate junctions in bulk technologies, as well as the problem of large depletion layers in high resistivity substrates which add substantial area to the layout.

The FET of the present invention can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the level translator of the present invention have been adopted from integrated circuit (IC) technology. For example, the structures of the present invention are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the level translator of the present invention uses basic building blocks, including: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.

FIGS. 1-4show respective structures and fabrication processes according to aspects of the present invention. More specifically, inFIG. 1, the structure10includes a BULK substrate10. In embodiments, the BULK substrate12is a silicon substrate which can be approximately 350 microns in thickness; although other dimensions are also contemplated by the present invention. A barrier layer14is formed on the substrate12. In embodiments, the barrier layer14can be a Silicon Nitride material, which is deposited using conventional deposition processes, e.g., chemical vapor deposition (CVD) process. Shallow trench isolation (STI) structures16are formed in the substrate12, through the barrier layer14.

In embodiments, the STI structures16can be formed from oxide, and fabricated using conventional photolithography, etching, deposition and polishing processes. For example, in embodiments, a photoresist can be formed on the barrier layer14, which is exposed to energy (e.g., light) in order to form a pattern. Through conventional etching processes, e.g., reactive ion etching (RIE), a corresponding pattern (vias) is formed in the substrate12and barrier layer14. The photoresist is then removed using conventional processes, e.g., oxygen ashing processes. An oxide or other insulator material is then deposited within the opening(s) and any residual material is removed from the surface of the barrier layer14using, e.g., a chemical mechanical process (CMP).

Still referring toFIG. 1, a photoresist18is formed on the barrier layer14and the STI structures16. The photoresist18is patterned to form an opening18abetween adjacent STI structure(s)16′. An ion implant process (as representatively shown by the arrows inFIG. 1) is then performed to create an amorphous layer20at a certain depth of the silicon layer12, abutting the STI structure(s)16′. The amorphous layer20is formed below the channel, e.g., active region, of transistors which will be formed in later fabrication processes. In embodiments, the implant process can be Ar or Ge or other species, e.g., Boron, which will form an amorphous layer20from the single crystalline substrate12, e.g., silicon substrate.

In embodiments, the amorphous layer20is bounded by the STI structure(s)16′ and has a depth of about 500 Å to about 2000 Å; although other depths are contemplated by the present invention as determined by the energy level of the ion implantation process. It should be understood by those of skill in the art that the depth of the amorphous layer20may be a function of the transistor, e.g., in order to provide sufficient space for a transistor channel, and based on the energy level of the ion implantation process. A typical amorphising dose for Ar or Ge will be about 2×1013to 1×1015ions per square cm. On the other hand, the dosage of the ion implantation process will determine the quality of the amorphous layer20. Both the dosage and energy level can be selected using known look-up tables.

InFIG. 2, a trench22aand undercut region22bis formed on sides of the STI structure(s)16′ and underneath amorphous layer20, respectively. In embodiments, the undercut portion22bextends laterally below an active region of the yet to be formed transistor, and is of such a depth as to provide sufficient spacing to form an airgap under such transistor, e.g., about 0.5 microns to about 10 microns. As shown inFIG. 2, in an alternative or optional embodiment, an amorphous layer20acan be provided under the undercut region22bby performing a second, higher energy ion implantation process that the formation of the amorphous layer20. In embodiments, the amorphous layer20ais an optional structure which can be formed prior to or after the amorphous layer20.

To form the trench22aand undercut region22b, a photoresist24is formed on the barrier layer14and the STI structures16(16′). The photoresist24is patterned to form an opening24a. A reactive ion etch process is then performed to remove the silicon nitride later and the silicon material, thereby forming the trench22aand undercut region22b. In embodiments, the undercut region22bis formed under an active region, e.g., channel, of a yet to be formed transistor. In embodiments, the wet etch process uses a chemistry which is selective to silicon, e.g., which will not attack the oxide material of the STI structure or the amorphous layer20(or amorphous layer20a, in optional embodiments). For example, the wet etch process can be performed using NH4OH. In this way, the amorphous layer20and oxide of the STI structures will act as an etch-stop layer. In addition, the photoresist24will protect the top portion of the wafer, e.g., nitride layer14.

InFIG. 3, the photoresist is removed and the structure is subjected to an oxidation process to form a passivated surface26. In embodiments, the passivated surface26is an oxidized surface of the substrate12, e.g., surface of the undercut region22b, and of the opposing amorphous layer20.

In preferred embodiments, the passivated surface26is formed by a growth process using an annealing process. For example, the structure ofFIG. 3can be subjected to a high temperature anneal process at about 800° C. to about 900° C. In alternate embodiments, the structure ofFIG. 3can be subjected to a rapid thermal anneal process to form the passivated surface26.

InFIG. 4, the trench22ais closed to form an airgap30. In embodiments, the trench is closed by the deposition of a material28, e.g., polysilicon material. After deposition of the material28, any residual material on the surface of the structure can be removed by a CMP process. A conventional transistor (FET)32is then formed over the airgap30using conventional deposition, lithography, etching and source/drain formation (diffusion regions on sides of a channel) processes, already known to those of skill in the art. In this way, the transistor32is completely isolated, e.g., oxide isolated, from portions (undoped portions) of the substrate by the STI structures and passivated surface26, with an underlying airgap. The location of the airgap30is directly under and in contact with the transistor channel and source and drain regions (diffusion regions), shown representatively at reference numeral34. The diffusion regions34are thus electrically isolated from the silicon substrate12.

In alternative embodiments, additional implants can be performed at multiple energies to set a perimeter of amorphous material which will limit the extent of the undercut etch outside of trenches22a.

FIGS. 5-12show respective structures and fabrication processes according to additional aspects of the present invention. InFIG. 5, the structure10′ includes a pad oxide layer50formed on the substrate12. In embodiments, the pad oxide layer50can have a thickness of about 80 Å; although other dimensions are also contemplated by the present invention. A pad nitride layer52is formed on the pad oxide layer50, which can have a thickness of about 1700 Å; although other dimensions are also contemplated by the present invention. An oxide hard mask54is formed on the pad nitride layer52, which can have a thickness of about 4500 Å; although other dimensions are also contemplated by the present invention. In embodiments, the layers50,52,54can be other materials, any of which are formed using conventional deposition processes, e.g., CVD, followed by a planarization process, as appropriate, e.g., CMP, as should be understood by those of skill in the art.

InFIG. 6, a photoresist56is formed on the oxide hard mask54, which is patterned by exposure to energy (e.g., light). Opening(s)58are then formed in the layers52,54,56, through the pattern, using conventional etching processes, e.g., RIE.

Thereafter, with an appropriate chemistry, deep trenches60are formed in the substrate12, as shown inFIG. 7. In embodiments, the deep trenches60can be about 5000 Å to about 25000 Å in depth; although other depths are also contemplated by the present invention. For example, the depth of the deep trenches60are provided deep enough to isolate a channel layer (formed in the substrate) of a transistor.

In the case of using the deep trenches60, continuing withFIG. 8, the resist is removed and sidewall structure(s)62are formed in the trenches60. In embodiments, the sidewall structure(s)62can be an oxide material. More specifically, in embodiments, the sidewall structure(s)62can be formed by an oxide deposition followed by a TEOS (Tetraethyl Orthosilicate) deposition process. In alternative embodiments, the sidewall structure(s)62can be formed using eDRAM collar deposition processes. In embodiments, the wall thickness of the sidewall structure(s)62is dependent on the dimensions of the deep trench60; that is, the wall thickness of the sidewall structure(s)62should not pinch off the deep trench60. The oxide process can be followed by an annealing process.

As shown inFIG. 9, the material of the sidewall structure(s)62at the bottom of the deep trench60is removed by an etching process. In embodiments, this etching process will also remove the sidewall material from a top surface of the structure, e.g., layer54. In embodiments, the etching process is an anisotropic etching process, in order to remove the material on horizontal surfaces, leaving the sidewalls on the vertical portions on the deep trench(es).

InFIG. 10, an etching or venting process is performed to form a lateral undercut64, removing material under an active region, e.g., channel of a transistor. In embodiments, the etching process is a XeF chemistry.

InFIG. 11, the trench60is closed to form an airgap66. In embodiments, the trench is closed by the deposition of a material68, e.g., polysilicon material. After deposition of the material68, any residual material on the surface of the structure can be removed by a CMP process. A conventional transistor (FET)32is then formed over the airgap66using conventional deposition, lithography, etching and source/drain formation processes, already known to those of skill in the art. In this way, the transistor32is completely isolated.

FIG. 12shows a top view ofFIG. 11. As shown in this view, the filled trenches, e.g., material66, surround the transistor32such that the transistor32is completely isolated, with an underlying airgap. The location of the airgap30is directly under and in contact with the transistor channel and source and drain regions.