Biasing circuit providing bias voltages based transistor threshold voltages

This application is directed to a bias circuit. The bias circuit includes a biasing voltage reference circuit including at least a first transistor. The biasing voltage reference circuit is configured to output a first voltage that depends on a threshold voltage of the first transistor. The bias circuit also includes a differential input circuit coupled to the biasing voltage reference circuit and having two differential inputs. The differential input circuit is configured to receive the first voltage and a reference voltage and generate a second voltage based on a difference between the first voltage and the reference voltage. The bias circuit further includes a buffer circuit coupled to the differential input circuit. The buffer circuit is configured to receive the second voltage and generate a bias voltage based on the second voltage. The bias voltage depends on the threshold voltage of the first transistor.

TECHNICAL FIELD

This application relates generally to electronic circuit including, but not limited to, methods, systems, and devices for providing a biasing current using one or more transistors.

BACKGROUND

Compound semiconductor integrated circuits are difficult to bias without using external electronic components. Limited transistor devices are available on a compound semiconductor integrated circuit to make on-chip bias circuits, and resulting bias circuits oftentimes have large performance variation and/or large power consumption. Due to these constraints, customers normally build off-chip biasing circuits (e.g., based on bias resistor ladders) for the compound semiconductor integrated circuits. These biasing circuits are oftentimes implemented using discrete electronic components that incur a higher cost and are difficult to operate. As device integration becomes standard, customers are less willing to design and apply these off-chip hybrid biasing circuits. There is a need for integrated biasing circuit solutions that are efficient in cost and easy to operate, reduces power consumption, and enhances performance variation.

SUMMARY

Various implementations of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, after considering this disclosure, and particularly after considering the section entitled “Detailed Description” one will understand how the aspects of some implementations are used to self-bias a circuit. The self-biasing circuit uses depletion mode field effect transistors (FETs) to generate an output voltage. Specifically, the biasing circuit provides a threshold reference via a first transistor, and operates as a current source having an offset from a first transistor saturation current IDSS1. An intermediate voltage VAand a reference voltage Vrefare fed into a differential pair including at least two transistors. The reference voltage Vrefis optionally generated via a voltage divider that is any combination of FET, diode, and/or resistors and configured to enable process variation compensation of one or more predetermined elements. An intermediate output VB of the differential pair is fed into a buffer and scaled through a resistor divider to generate a bias voltage Vout. In some embodiments, the bias voltage Voutis correlated with and tracks a threshold voltage of the transistor devices applied in the biasing circuit. When the bias voltage Voutis applied to bias a gate of a circuit transistor, a drain current of the circuit transistor is substantially independent of the threshold voltage.

In one aspect, a bias circuit includes a biasing voltage reference circuit including at least a first transistor. The biasing voltage reference circuit is configured to output a first voltage that depends on a threshold voltage of the first transistor. The bias circuit also includes a differential input circuit coupled to the biasing voltage reference circuit and having two differential inputs. The differential input circuit is configured to receive the first voltage and a reference voltage. The differential input circuit is further configured to generate a second voltage based on a difference between the first voltage and the reference voltage. The bias circuit further includes a buffer circuit coupled to the differential input circuit. The buffer circuit configured to receive the second voltage and generate a bias voltage based on the second voltage. The bias voltage depends on the threshold voltage of the first transistor. In some embodiments, the bias circuit includes only depletion mode field effect transistors (FET), and the first transistor is one of the depletion mode FETs.

In some embodiments, the bias circuit further includes a drive transistor coupled to the buffer circuit. The drive transistor is configured to receive the bias voltage at a gate of the drive transistor and generate a drive current that flows through a drain and a source of the drive transistor. The drive transistor has a threshold voltage that is equal to the threshold voltage of the first transistor. In some embodiments, the bias circuit does not include a current mirror. In some embodiments, the drive current varies less than 5% when the threshold voltage drifts from a nominal threshold value by 0.3V. In some embodiments, the drive current is substantially constant, independently of a drift of the threshold voltage of the first transistor (or any transistor) from a nominal threshold value.

In some embodiments, the biasing voltage reference circuit further includes a plurality of biasing resistors that are arranged in series with each other and with the first transistor. The plurality of biasing resistors has a first end coupled to one of the biasing resistors, a first biasing node coupled between two biasing resistors, and a second biasing node coupled to another two biasing resistors. The biasing voltage reference circuit is biased by itself (and without being coupled to an external reference voltage). A source of the first transistor is coupled to a first end of the plurality of biasing resistors, a gate of the first transistor is coupled to the first biasing node, the first voltage is coupled to the second biasing node. In some embodiments, each of the plurality of biasing resistors includes a self-biased biasing transistor. A drain and a gate of the self-biased biasing transistor are coupled to each other to form a corresponding biasing resistor. Alternatively, in some embodiments, each of the plurality of biasing resistors is a diode.

In some embodiments, the bias circuit further includes a high power rail powered by a high supply voltage and a low power rail powered by a low supply voltage. Each of the biasing voltage reference circuit, differential input amplifier circuit, and buffer circuit is biased between the high power rail and the low power rail, and the high and low supply voltages are held substantially constant, independently of a drift of the threshold voltage of the first transistor (or any other transistor) from a nominal threshold value.

In some embodiments, the reference voltage is independent of a drift of the threshold voltage of the first transistor from a nominal threshold value, and the bias circuit further includes a resistor divider including a plurality of reference resistors arranged in series and configured to generate the reference voltage. In some embodiments, the threshold voltage of the first transistor has a nominal threshold value, and the reference voltage generated by the resistor divider is configured to be equal to the first voltage that is generated when the threshold voltage of the first transistor has no drift from the nominal threshold value. In some embodiments, each of the plurality of reference resistors includes a self-biased reference transistor, a drain and a gate of the self-biased reference transistor being coupled to each other to form a corresponding reference resistor. Alternatively, in some embodiments, each of the plurality of reference resistors is a diode.

In some embodiments, the buffer circuit further includes a buffer transistor having a gate configured to receive the second voltage, a plurality of output resistors that are coupled in series with each other and at a source of the buffer transistor, and an output interface coupled between two output resistors in the plurality of output resistors. The output interface is configured to output the bias voltage. In some embodiments, a drift of the threshold voltage of the first transistor from a nominal threshold value is amplified in the second voltage, and (ratios of) resistances of the plurality of output resistors are configured to scale the bias voltage from a source voltage of the source of the buffer transistor, thereby compensating the amplified drift of the threshold voltage in the second voltage and a drift of a threshold voltage of the buffer transistor from the nominal threshold value. In some embodiments, each of the plurality of output resistors includes a self-biased output transistor, a drain and a gate of the self-biased output transistor being coupled to each other to form a corresponding output resistor. Alternatively, in some embodiments, each of the plurality of reference resistors is a diode.

In some embodiments, the bias circuit is coupled to a drive transistor, the drive transistor configured to receive the bias voltage at a gate of the drive transistor and generate a drive current that flows through a drain and a source of the drive transistor, independently of a drift of the threshold voltage of the first transistor from a nominal threshold value. In some embodiments, the bias circuit is integrated with the drive transistor on a substrate of a semiconductor chip.

In some embodiments, the bias circuit is coupled to a drive transistor. The drive transistor is configured to receive the bias voltage at a gate of the drive transistor and generate a drive current that flows through a drain and a source of the drive transistor. In some embodiments, the bias circuit and the drive transistor are located on two substrates of two distinct semiconductor chips.

In some embodiments, the biasing voltage reference circuit, differential input amplifier, and buffer are formed based on silicon. In some embodiments, the biasing voltage reference circuit, differential input amplifier, and buffer circuit are formed based on III-V compound semiconductors (e.g., GaAs, GaN).

In another aspect, some implementations include a method of manufacturing a bias circuit. The method includes providing a biasing voltage reference circuit including at least a first transistor. The biasing voltage reference circuit is configured to output a first voltage that depends on a threshold voltage of the first transistor. The method further includes providing a differential input circuit coupled to the biasing voltage reference circuit and having two differential inputs. The differential input circuit is configured to receive the first voltage and a reference voltage and generate a second voltage based on a difference between the first voltage and the reference voltage. The method further includes providing a buffer circuit coupled to the differential input circuit. The buffer circuit configured to receive the second voltage and generate a bias voltage based on the second voltage. The bias voltage depends on the threshold voltage of the first transistor. In some embodiments, the bias circuit is manufactured in accordance with any of the above-mentioned embodiments.

In another aspect, a method of generating a bias voltage is performed at a bias circuit. The bias circuit includes biasing voltage reference circuit having at least a first transistor, a differential input circuit coupled to the biasing voltage reference circuit and having two differential inputs, and a buffer circuit coupled to the differential input circuit. The method includes outputting, by the biasing voltage reference circuit, a first voltage that depends on a threshold voltage of the first transistor. The method further includes, receiving, by the differential input circuit, the first voltage and a reference voltage, and generating a second voltage based on a difference between the first voltage and the reference voltage. The method further includes receiving, by the buffer circuit, the second voltage, and generating, by the buffer circuit, a bias voltage based on the second voltage. The bias voltage depends on the threshold voltage of the first transistor.

In some embodiments, the bias circuit further includes a drive transistor coupled to the buffer circuit and the method further includes receiving, by the drive transistor, the bias voltage at a gate of the drive transistor and generating a drive current that flows through a drain and a source of the drive transistor. The drive transistor has a threshold voltage that is equal to the threshold voltage of the first transistor.

In some embodiments, the bias circuit further includes a resistor divider including a plurality of reference resistors arranged in series, and the reference voltage is independent of a drift of the threshold voltage of the first transistor from a nominal threshold value. The method further includes generating, by the resistor divider, the reference voltage. In some embodiment, the threshold voltage of the first transistor has a nominal threshold value and the reference voltage generated by the resistor divider is configured to be equal to the first voltage that is generated when the threshold voltage of the first transistor has no drift from the nominal threshold value.

In some embodiments, the bias circuit further includes a buffer transistor having a gate, a plurality of output resistors that are coupled in series with each other and at a source of the buffer transistor, and an output interface coupled between two output resistors in the plurality of output resistors. The method further includes receiving, by the buffer transistor, the second voltage and outputting, by the output interface, the bias voltage. In some embodiments, a drift of the threshold voltage of the first transistor from a nominal threshold value is amplified in the second voltage, and resistances of the plurality of output resistors are configured to scale the bias voltage from a source voltage of the source of the buffer transistor, thereby compensating the amplified drift of the threshold voltage in the second voltage and a drift of a threshold voltage of the buffer transistor from the nominal threshold value.

In some embodiments, the bias circuit is coupled to a drive transistor. The bias circuit is integrated with the drive transistor on a substrate of a semiconductor chip. The method further includes receiving, by the drive transistor, the bias voltage at a gate of the drive transistor and generating, by the drive transistor, a drive current that flows through a drain and a source of the drive transistor, independently of a drift of the threshold voltage of the first transistor from a nominal threshold value.

In some embodiments, the bias circuit is coupled to a drive transistor, and the bias circuit and the drive transistor are located on two substrates of two distinct semiconductor chips. The method further includes receiving, by the drive transistor, the bias voltage at a gate of the drive transistor, and generating, by the drive transistor, a drive current that flows through a drain and a source of the drive transistor.

Other implementations and advantages may be apparent to those skilled in the art in light of the descriptions and drawings in this specification.

DESCRIPTION OF EMBODIMENTS

Numerous details are described herein in order to provide a thorough understanding of the example embodiments illustrated in the accompanying drawings. However, some embodiments may be practiced without many of the specific details, and the scope of the claims is only limited by those features and aspects specifically recited in the claims. Furthermore, well-known processes, components, and materials have not been described in exhaustive detail so as not to unnecessarily obscure pertinent aspects of the embodiments described herein.

FIG.1is a circuit diagram of a bias circuit100in accordance with some embodiments. In some embodiments, the bias circuit100includes a biasing voltage reference circuit110including at least a first transistor112(Q1), a differential input circuit120coupled to the biasing voltage reference circuit110and having two differential inputs (e.g., Vrefand VA), and a buffer circuit130coupled to the differential input circuit120. In some embodiments, the bias circuit100includes a resistor divider140including a plurality of reference resistors142arranged in series and configured to generate a reference voltage Vref. The biasing voltage reference circuit110is configured to output a first voltage VA that depends on a threshold voltage of the first transistor112(Q1). The differential input circuit120is configured to receive the first voltage and a reference voltage and generate a second voltage VB based on a difference between the first voltage VA and the reference voltage Vref. The buffer circuit130is configured to receive the second voltage VB and generate a bias voltage Voutbased on the second voltage VB. The bias voltage Voutdepends on the threshold voltage of the first transistor112(Q1). In some embodiments, the bias circuit100does not include a current mirror. The biasing voltage reference circuit110, the differential input circuit120, the biasing voltage reference circuit110, and the resistor divider140are configured such that the bias voltage Voutis correlated with and tracks a threshold voltage of the transistors (e.g., transistors Q1-Q3) applied in the bias circuit100.

Each individual chip of the bias circuit100is manufactured from a microfabrication process. Each type of transistors (e.g., depletion mode N-type transistors) has a threshold voltage. The threshold voltage has a nominal threshold value and may varies in a threshold value range containing the nominal threshold value when each transistor of the respective type is manufactured from different processing batches, different wafers of a batch, and/or at different locations of a certain wafer. For example, the depletion model N-type transistor manufactured from a GaAs-based microfabrication process has the nominal threshold value of −1.0 V, and the corresponding threshold value may vary up to a high corner threshold voltage of −0.7 V and a low corner threshold voltage of −1.3 V. For each individual bias circuit100, a corresponding threshold voltage drifts with temperature. If temperature is stable, the threshold voltage of the bias circuit100is fixed, and has a drift with respect to the nominal threshold voltage value of the same type of transistors manufactured from the same type of microfabrication process.

Specifically, in some embodiments, each bias circuit100is located at a fixed position of a wafer processed using a known microfabrication process, and each transistor of the bias circuit100has a threshold voltage that has a drift with respect to the nominal threshold voltage. The drift of this threshold voltage varies with a temperature of the bias circuit100, and is optionally distinct from that of another bias circuit100. In the bias circuit100, the first voltage VA outputted by the biasing voltage reference110changes with the threshold voltage of the first transistor112(Q1). In some embodiments, in the context of the biasing voltage reference circuit110, the first voltage VA depends on the threshold voltage of the first transistor112(Q1), and the first voltage VA scales or amplifies a drift of the threshold voltage of the first transistor112(Q1) from the nominal threshold value. In some embodiments, in the context of the buffer circuit130, the bias voltage Voutdepends on the threshold voltage of the first transistor Q1, and the bias voltage Voutchanges with the threshold voltage without scaling.

In some embodiments, the bias circuit100includes a high power rail (e.g., “VDD”) powered by a high supply voltage (e.g., VDD) and a low power rail powered by a low supply voltage (e.g., “VSS”). In some embodiments, each of the biasing voltage reference circuit110, differential input circuit120, and buffer circuit130is biased between the high power rail and the low power rail. The high and low supply voltages are held substantially constant, independently of a drift of the threshold voltage of the first transistor112(Q1) (or any transistor) from a nominal threshold value.

In some embodiments, the biasing voltage reference circuit110, differential input circuit120, and buffer circuit130are formed based on silicon. In some embodiments, the biasing voltage reference circuit110, differential input circuit120, and buffer circuit130are formed based on III-V compound semiconductors (e.g., GaN, GaAs). The bias circuit is part of Monolithic Microwave ICs (MMICs). In some embodiments, the bias circuit100includes only depletion mode field effect transistors (FET), and the first transistor112(Q1) is one of the depletion mode FETs.

In some embodiments, the biasing voltage reference circuit110further includes a plurality of biasing resistors114that are arranged in series with each other and with the first transistor112(Q1). The plurality of biasing resistors114have a first end coupled to one of the biasing resistors, a first biasing node115coupled between two biasing resistors and a second biasing node117coupled to another two biasing resistors. For example, the first biasing node115is coupled between second and third biasing resistors114band114c, and the second biasing node117is coupled between first and second biasing resistors114aand114b. In some embodiments, the biasing voltage reference circuit110is biased by itself without using an external reference voltage to bias itself. A source of the first transistor112(Q1) is coupled to the first end of the plurality of biasing resistors114(e.g., first biasing resistor114a), a gate of the first transistor112(Q1) coupled to the first biasing node115, and the first voltage VA is coupled to the second biasing node117. In some embodiments, each of the plurality of biasing resistors114includes a self-biased biasing transistor. A drain and a gate of the self-biased biasing transistor are coupled to each other to form a corresponding biasing resistor. Alternatively, in some embodiments, each of the plurality of biasing resistors114is a diode.

A voltage gain (Av1) of the first transistor112(Q1) is determined by the following equation:
Av1=gm1Rds1(1)
where gm1is a transconductance of the first transistor112(Q1), and Rds1is an on resistance of the first transistor112(Q1) (i.e., an internal resistance when the first transistor112(Q1) is in a fully conducting state). Further, the first voltage (VA) is determined by the following equation:

VA=(R2+R3)⁢VDDRds⁢1-Av⁢1⁢R3+(1+Av⁢1)⁢(R1+R2+R3)(2)
where R1, R2, and R3are resistances of the plurality of biasing resistors114, Rds1is the on resistance of the first transistor112(Q1), Av1is the voltage gain of the first transistor112(Q1), and VDD is the high power rail voltage.

As descried above, the resistor divider140is configured to generate a reference voltage Vref. In some embodiments, the reference voltage is independent of a drift of the threshold voltage of the first transistor112(Q1) from a nominal threshold value. Different chips having different bias circuit100have different threshold voltages, and however, the reference voltages Vrefused by the different bias circuits100are substantially identical when the high and low power rail voltages are fixed. In some embodiments, the threshold voltage of the first transistor112(Q1) has a nominal threshold value and the reference voltage Vrefgenerated by the resistor divider140is configured to be equal to the first voltage VA that is generated when the threshold voltage of the first transistor112(Q1) has no drift from the nominal threshold value. In some embodiments, each of the plurality of reference resistors142includes a self-biased reference transistor, a drain and a gate of the self-biased reference transistor being coupled to each other to form a corresponding reference resistor142. Alternatively, in some embodiments, each of the plurality of reference resistors142is a diode.

In some embodiments, the differential input circuit120includes a plurality of differential transistors122(e.g., first and second differential transistors122aand122b(Q2 and Q3)). In some embodiment, a first differential transistor122a(Q2) is configured to receive at a gate the reference voltage Vref, and a second differential transistor122b(Q3) is configured to receive at a gate the first voltage VA. In some embodiment, the differential input circuit120includes a plurality of collector resistors (e.g., first and second collector resistors124aand124b). In some embodiments, a first collector resistor124ais coupled to a drain of the first differential transistor122aand a second collector resistor124bis coupled to a drain of the second differential transistor122b.

A voltage gain (Av2) of the first differential transistor122a(Q2) is determined by the following equation:
Av2=gm2Rds2(3)
where gm2is a transconductance of a first differential transistor122a(Q2), and Rds2is an on resistance of the second differential transistor122b(Q2). A voltage gain (Av3) of the second differential transistor124bis determined by the following equation:
Av3=gm3Rds3(4)
where gm3is a transconductance of the second differential transistor122b(Q3), and Rds3is the resistance between the drain and the source of the second differential transistor122b. In some embodiments, the first and second differential transistors122(Q2 and Q3) are identical to each other, and the first and second collector resistors124aand124bare identical to each other.

An output resistance (RO) of the differential input circuit120is determined by the following equation:
Ro=R11+Rds3(5)
where R11is a second collector resistor124b, and Rds3is the on resistance of the second differential transistor122b(Q3).

A resistance across (Rx) the differential input circuit120is determined by the following equation:
Rx=R10+R12(6)
where R10is a first resistor coupled between the high power rail voltage and the first and second differential resistors124, and R12is a second resistor coupled between the low power rail voltage and the sources of the first and second differential transistors122aand122b(Q2 and Q3).

A current Ixfor the differential input circuit120passes through the second collector resistor124b(R11) and is determined by the following equation:

where Rois the output resistor and Rxis a sum of the first and second resistors R10and R12. A differential current Idiffof the differential input circuit120is determined by the following equation:

Idiff=2⁢Ro⁢Ix+Av⁢2(Vref-VA)Ro(8)
where ROis the output resistance, Av2is the voltage gain of the first differential transistor122a(Q2), Vrefis the reference voltage, and VAis the first voltage.

The second voltage (VB) is determined by the following equation:
VB=Rds3Ix−Av3[VA−(IdiffR12+VSS)]IdiffR12+VSS(9)
where Rds3is the on resistance of the second differential transistor122b(Q3), Av3is the voltage gain of the second differential transistor122b(Q3), VAis the first voltage, R12is the second resistor, and VSSis the low power rail voltage.

In some embodiments, the buffer circuit130includes a buffer transistor132(Q4) having a gate configured to receive the second voltage, a plurality of output resistors134that are coupled in series with each other and at a source of the buffer transistor132(Q4), and an output interface136coupled between two output resistors (e.g., first and second output resistors134aand134b) in the plurality of output resistors134. The output interface136is configured to output the bias voltage Vout. In some embodiments, a drift of the threshold voltage of the first transistor112(Q1) from a nominal threshold value is amplified in the second voltage VB. The second voltage VB drops by a threshold voltage at a source of the buffer transistor132(Q4), and therefore, the amplified drift of the threshold voltage is reduced by the threshold voltage at the source of the buffer transistor132(Q4). A ratio of resistances of the plurality of output resistors134further scales a source voltage of the source of the buffer transistor132(Q4), thereby compensating the amplified drift of the threshold voltage in the second voltage and a drift of a threshold voltage of the buffer transistor132(Q4) from the nominal threshold value. In some embodiments, each of the plurality of output resistors134includes a self-biased output transistor, a drain and a gate of the self-biased output transistor being coupled to each other to form a corresponding output resistor. Alternatively, in some embodiments, each of the plurality of output resistors134is a diode.

A voltage gain (Av4) of the buffer transistor132(Q4) is determined by the following equation:
Av4=gm4Rds4(10)
where gm4is a transconductance of the buffer transistor132(Q4), and Rds4is an on resistance of the buffer transistor132(Q4).

Further, the bias voltage (Vout) is determined by the following equation:

Vout=R5⁢VDD-(1+Av⁢4)⁢VSS+Av⁢4⁢VBRds⁢4+(1+Av⁢4)⁢(R4+R5)+VSS(11)
where R4and R5are resistors of the plurality of output resistors134, Rds4is the on resistance of the buffer transistor132(Q4), Av4is a voltage gain of the buffer transistor132(Q4), VBis the second voltage, VSS is the low power rail voltage, and VDD is the high power rail voltage.

In some embodiments, the bias circuit100is coupled to a drive transistor150(Q5). The drive transistor150(Q5) is configured to receive the bias voltage Voutat a drive transistor gate and generate a drive current that flows through a drive transistor drain and a drive transistor source, independently of a drift of the threshold voltage of the first transistor112(Q1) from a nominal threshold value. Stated another way, two distinct bias circuits100correspond to two distinct threshold voltages of the transistors Q1-Q4, and two drive currents passing drains of the drive transistors150(Q5) of the two distinct bias circuits100are substantially constant and independent of the two distinct threshold voltages, when the same high power rail voltages and the same low power rail voltages are applied to power the two distinct bias circuits100. In some embodiments, the bias circuit100is integrated with the drive transistor150(Q5) on a substrate of a semiconductor chip. Alternatively, in some embodiments, the drive transistor150(Q5) configured to receive the bias voltage at the drive transistor gate and generate a drive current that flows through the drive transistor drain and the drive transistor source, and the bias circuit100and the drive transistor150(Q5) are located on two substrates of two distinct semiconductor chips.

In some embodiments, the low supply voltage VSS is biased at a negative voltage level, and a source of the drive transistor150(Q5) is grounded. Alternatively, in some embodiments not shown inFIG.1, the low supply voltage VSS is biased at a ground voltage level, and a source of the drive transistor150(Q5) is biased at a positive voltage level.

In some embodiments, the drive transistor150is coupled to the buffer circuit130and configured to receive the bias voltage Voutat the drive transistor gate and generate a drive current that flows through the drive transistor drain and the drive transistor source. The drive transistor150(Q5) has a threshold voltage that is equal to the threshold voltage of the first transistor112(Q1). In some embodiments, the drive current varies less than 5% when the threshold voltage drifts from a nominal threshold value by 0.3V. In some embodiments, the drive current is substantially constant, independently of a drift of the threshold voltage of the first transistor112(Q1) (or any transistor Q2-Q5) from a nominal threshold value.

FIG.2is a plot200illustrating example performance improvement provided by a bias circuit100, in accordance with some embodiments. The bias circuit100applies a plurality of transistors (e.g., Q1-Q4) having the same transistor types. A size of each transistor is configured to give desirable circuit performance. Each transistor has a respective threshold voltage that drifts from a nominal threshold voltage value as a result of a processing variation. For example, the nominal threshold voltage value corresponding to a process nominal condition is −1.0 V. The plurality of transistors of the bias circuit100, if processed differently or located differently on a wafer, have a threshold voltages drift caused by a process condition drifting between 65-135% of the process nominal condition. For example, the threshold voltage of the transistors drifts between −0.83 V and −1.18 V. Plot200has a Y-axis representing a drive current (IDD) of a drive transistor150and an X-axis representing a threshold voltage in a threshold value range. As shown in plot200incorporation of the bias circuit100results in substantially constant current biasing (represented by Compensated line220). In some embodiments, a drive current is regarded as a substantially constant current, if the drive current varies less than a threshold percentage (e.g., 5%) across the threshold value range. Alternatively, without the use of the bias circuit100, the current biasing steadily increases (represented by Uncompensated line210) beyond 80 mA.

FIG.3is a flowchart of a method of providing a bias circuit, in accordance with some embodiments. The bias circuit is provided in accordance with one or more of the features described above in reference toFIG.1. The method300includes providing (302) a biasing voltage reference circuit110including at least a first transistor (e.g., a first transistor112(Q1) inFIG.1). The biasing voltage reference circuit110is configured to output a first voltage VAthat depends on a threshold voltage of the first transistor. In some embodiments, the method300includes providing (304) a resistor divider140including a plurality of reference resistors142arranged in series and configured to generate a reference voltage Vref.

The method300includes providing (306) a differential input circuit120coupled to the biasing voltage reference circuit110and having two differential inputs. The differential input circuit120is configured to receive the first voltage VA and the reference voltage Vrefand generate a second voltage VB based on a difference between the first voltage VA and the reference voltage Vref.

In some embodiments, the method300includes providing (308) a buffer circuit130coupled to the differential input circuit120. The buffer circuit130is configured to receive the second voltage VB and generate a bias voltage Voutbased on the second voltage VB, the bias voltage Voutdepending on the threshold voltage of the first transistor. In some embodiments, the method300includes providing (310) a drive transistor150. The drive transistor150is configured to receive the bias voltage Voutat a gate of the drive transistor150and generate a drive current that flows through a drain and a source of the drive transistor150. In some embodiments, the bias circuit100is (312) integrated with the drive transistor150on a substrate of a semiconductor chip. Alternatively, in some embodiments, the bias circuit100(including circuits110,120,130, and140) and the drive transistor150are (314) located on two substrates of two distinct semiconductor chips.

FIG.4is a flowchart of a method400implemented at a bias circuit, in accordance with some embodiments. In some embodiments, the method400is performed at a bias circuit100including biasing voltage reference circuit110including at least a first transistor, a differential input circuit120coupled to the biasing voltage reference circuit110and having two differential inputs, and a buffer circuit130coupled to the differential input circuit120. In some embodiments, the bias circuit100includes a resistor divider140and/or a drive transistor150. Additional information on the bias circuit100and its one or more components is provided above in reference toFIG.1. Method400includes outputting (402), by the biasing voltage reference circuit110, a first voltage VA that depends on a threshold voltage of the first transistor112(Q1). In some embodiments, the method400includes generating (404), by the resistor divider140, a reference voltage Vref. The method400includes receiving (406), by the differential input circuit120, the first voltage VA and reference voltage Vrefand generate a second voltage VB based on a difference between the first voltage VA and the reference voltage Vref.

The method400further includes receiving (408), by the buffer circuit130, the second voltage VB and generating a bias voltage Voutbased on the second voltage VB. The bias voltage VB depends on the threshold voltage of the first transistor112(Q1). In some embodiments, the method400includes receiving (410), by the drive transistor150, the bias voltage Voutat a gate of the drive transistor150(Q5) and generating a drive current that flows through a drain and a source of the drive transistor150(Q5). The drive transistor150(Q5) having a threshold voltage that is equal to the threshold voltage of the first transistor112(Q1). In some embodiments shown inFIG.1, the low supply voltage VSS is biased at a negative voltage level, and a source of the drive transistor150(Q5) is grounded.

In some embodiments of this application, the bias circuit100is manufactured as an electronic component by itself or integrated on the same substrate with electronic circuit that are biased (e.g., the drive transistor150(Q5)). No or few external active or pass electronic components are applied to enable operation and integration of the bias circuit100, thereby reducing packaging parastics and conserving power consumptions. The bias voltage Voutoptionally depends on a threshold voltage of the transistors (e.g., Q1-Q5). When the bias voltage Voutis applied to bias the drive transistor150(Q5), a drive current provided by the drive transistor150(Q5) is substantially constant and independent of any drift of the threshold voltage of the transistors. The bias voltage Voutis proportional to the threshold voltage and tracks any drift of the threshold voltage of the transistors applied in the bias circuit100. By these means, the bias circuit100provides an integrated biasing solution that is efficient in cost and easy to operate, reduces power consumption, and enhances performance variation.

It should be understood that the particular order in which the operations inFIGS.3and4have been described are merely exemplary and are not intended to indicate that the described order is the only order in which the operations could be performed. One of ordinary skill in the art would recognize various ways to reorder the operations described herein. Additionally, it should be noted that details of processes described herein with respect to methods300and400(e.g.,FIGS.3and4) are also applicable in an exchangeable manner. For brevity, these details are not repeated.

The above description has been provided with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to be limiting to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles disclosed and their practical applications, to thereby enable others to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated.

Clause 1. A method, comprising:at a bias circuit including biasing voltage reference circuit including at least a first transistor, a differential input circuit coupled to the biasing voltage reference circuit and having two differential inputs, and a buffer circuit coupled to the differential input circuit:outputting, by the biasing voltage reference circuit, a first voltage that depends on a threshold voltage of the first transistor;receiving, by the differential input circuit, the first voltage and a reference voltage;generating, by the differential input circuit, a second voltage based on a difference between the first voltage and the reference voltagereceiving, by the buffer circuit, the second voltage; andgenerating, by the buffer circuit, a bias voltage based on the second voltage, wherein the bias voltage depends on the threshold voltage of the first transistor.

Clause 2. The method of clause 1, wherein the bias circuit further includes a drive transistor coupled to the buffer circuit, the method further comprising:receiving, by the drive transistor, the bias voltage at a gate of the drive transistor; andgenerating, by the drive transistor, a drive current that flows through a drain and a source of the drive transistor;wherein the drive transistor has a threshold voltage that is equal to the threshold voltage of the first transistor.

Clause 3. The method of clause 1, wherein the bias circuit further includes a resistor divider including a plurality of reference resistors arranged in series and the reference voltage is independent of a drift of the threshold voltage of the first transistor from a nominal threshold value, the method further comprising:generating, by the resistor divider, the reference voltage.

Clause 4. The method of clause 3 wherein:the threshold voltage of the first transistor has a nominal threshold value; andthe reference voltage generated by the resistor divider is configured to be equal to the first voltage that is generated when the threshold voltage of the first transistor has no drift from the nominal threshold value.

Clause 5. The method of clause 1, wherein the bias circuit further includes a buffer transistor having a gate, a plurality of output resistors that are coupled in series with each other and at a source of the buffer transistor, and an output interface coupled between two output resistors in the plurality of output resistors, the method further comprising:receiving, by the buffer transistor, the second voltage; andoutputting, by the output interface, the bias voltage.

Clause 6. The method of clause 5, wherein a drift of the threshold voltage of the first transistor from a nominal threshold value is amplified in the second voltage, and resistances of the plurality of output resistors are configured to scale the bias voltage from a source voltage of the source of the buffer transistor, thereby compensating the amplified drift of the threshold voltage in the second voltage and a drift of a threshold voltage of the buffer transistor from the nominal threshold value.

Clause 7. The method of clause 1, wherein the bias circuit is coupled to a drive transistor, the bias circuit being integrated with the drive transistor on a substrate of a semiconductor chip, the method further comprising:receiving, by the drive transistor, the bias voltage at a gate of the drive transistor; andgenerating, by the drive transistor, a drive current that flows through a drain and a source of the drive transistor, independently of a drift of the threshold voltage of the first transistor from a nominal threshold value.

Clause 8. The method of clause 1, wherein the bias circuit is coupled to a drive transistor, the bias circuit and the drive transistor being located on two substrates of two distinct semiconductor chips, the method further comprising:receiving, by the drive transistor, the bias voltage at a gate of the drive transistor; andgenerating, by the drive transistor, a drive current that flows through a drain and a source of the drive transistor.