Printed wiring board and method for manufacturing the same

A printed wiring board includes an insulating layer, a conductor layer formed on the insulating layer and including first and second pads, a solder resist layer formed on the insulating layer, covering the conductor layer and exposing the first and second pads to form the second pad having diameter smaller than diameter of the first pad, a first bump formed on the first pad and including first base and top plating layers such that the first base layer has embedded portion in the resist layer and exposed portion and having diameter substantially equal to or smaller than diameter of the embedded portion, and a second bump formed on the second pad and including second base and top plating layers such that the second base layer has embedded portion in the resist layer and exposed portion and having diameter substantially equal to or smaller than diameter of the embedded portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2019-157653, filed Aug. 30, 2019, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a printed wiring board having plating bumps and a method for manufacturing the printed wiring board.

Description of Background Art

In Japanese Patent Application Laid-Open Publication No. 2019-54111, in a printed wiring board, bumps of different sizes are respectively formed on conductor pads in openings of different sizes formed in a solder resist layer on a base insulating layer, the bumps being each formed by forming a base plating layer formed of Cu as a metal post and forming a top plating layer formed of Sn on the base plating layer. The entire contents of this publication are incorporated herein by reference.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and including a first conductor pad and a second conductor pad, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer formed on the base insulating layer and exposing the first and second conductor pads to form the second conductor pad having a diameter smaller than a diameter of the first conductor pad, a first bump formed on the first conductor pad and including a first base plating layer and a first top plating layer formed on the first base plating layer such that the first base plating layer has an embedded portion embedded in the solder resist layer and an exposed portion exposed from the solder resist layer and having a diameter substantially equal to or smaller than a diameter of the embedded portion, and a second bump formed on the second conductor pad and including a second base plating layer and a second top plating layer formed on the second base plating layer such that the second bump has a diameter smaller than a diameter of the first bump and that the second base plating layer has an embedded portion embedded in the solder resist layer and an exposed portion exposed from the solder resist layer and having a diameter substantially equal to or smaller than a diameter of the embedded portion.

According to another aspect of the present invention, a method for manufacturing a printed wiring board includes forming a conductor layer including a first conductor pad and a second conductor pad on a base insulating layer on a base insulating layer, forming a dry film resist layer on the base insulating layer such that the dry film resist layer is covering the conductor layer formed on the base insulating layer, forming a first opening exposing the first conductor pad and a second opening having a smaller diameter than a diameter of the first opening and exposing the second conductor pad, applying first metal plating such that a first base plating layer is formed on the first conductor pad in the first opening and that a second base plating layer is formed on the second conductor pad in the second opening, applying second metal plating such that a first top plating layer is formed on the first base plating layer in the first opening to form a first bump post including the first base plating layer and the first top plating layer and that a second top plating layer is formed on the second base plating layer in the second opening to form a second bump post including the second base plating layer and the second top plating layer, removing the dry film resist layer from the base insulating layer on which the first bump post is formed on the first conductor pad of the conductor layer and the second bump post is formed on the second conductor pad of the conductor layer, forming a solder resist layer on the base insulating layer such that the solder resist layer covers the first bump post formed on the first conductor pad of the conductor layer and the second bump post formed on the second conductor pad of the conductor layer, and thinning the solder resist layer over an entire surface of the solder resist layer such that the first top plating layer of the first bump post and the second top plating layer of the second bump post are positioned outside the solder resist layer.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1illustrates an enlarged view of a portion of a printed wiring board10according to an embodiment of the present invention. The printed wiring board10may be a substrate with a core formed by alternately laminating conductor layers and resin insulating layers on one side or both sides of a core substrate (not illustrated in the drawings), the conductor layers each having a predetermined circuit pattern. In the case where the conductor layers are formed on both sides of the core substrate, conductor layers opposing each other via the core substrate may be connected to each other via through-hole conductors (not illustrated in the drawings). Alternatively, the printed wiring board10may be a coreless substrate obtained by alternately laminating conductor layers and resin insulating layers on a support plate (not illustrated in the drawings) instead of a core substrate, and then removing the support plate. In any case, as illustrated inFIG. 1, the printed wiring board10includes at least a base insulating layer12which is positioned outermost among the resin insulating layers, a conductor layer14which is formed on the base insulating layer12and has a predetermined circuit pattern, and a solder resist layer16which is formed on the base insulating layer12and the conductor layer14. Other multiple conductor layers and multiple resin insulating layers are often alternately provided below the base insulating layer12, but are omitted in the drawings. However, it is also possible that the printed wiring board10is formed of one insulating layer (the base insulating layer12) and one conductor layer (the conductor layer14).

A first conductor pad (14a) is set at a center portion of the conductor layer14where a large-diameter bump is to be formed. A cylindrical first base plating layer24is formed on the first conductor pad (14a), and a first top plating layer28is formed on the first base plating layer24. A first bump post41is formed by the first base plating layer24and the first top plating layer28.

A second conductor pad (14b) having a smaller diameter than the first conductor pad (14a) is set at a center portion of the conductor layer14where a small-diameter bump is to be formed. A cylindrical second base plating layer30having a smaller diameter than the first base plating layer24is formed on the second conductor pad (14b), and a second top plating layer32is formed on the second base plating layer30. A second bump post42is formed by the second base plating layer30and the second top plating layer32.

As illustrated inFIG. 1, a solder resist layer16is provided on the base insulating layer12, between outer peripheral portions of the conductor layer14, and between the first bump post41and the second bump post42and further on them. By a reflow treatment, head portions of the first top plating layer28and the second top plating layer32are melted and shaped into substantially hemispherical shapes. As a result, a printed wiring board10having a large-diameter first bump20and a small-diameter second bump22is formed.

Details of the parts of the printed wiring board illustrated inFIG. 1described above are as follows.

The base insulating layer12can be formed of, for example, a resin composition or the like containing an inorganic filler such as silica or alumina and an epoxy resin. The conductor layer14is formed of a conductive metal, for example, a metal containing copper as a main component.

An underlayer may be formed on each of the first and second conductor pads (14a,14b). As the underlayer, a nickel layer formed on a surface of each of the first and second conductor pads (14a,14b), a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer can be exemplified. In addition, a nickel layer and a gold layer formed on the nickel layer can be exemplified.

The printed wiring board10according to the embodiment of the present invention has the first bump20and the second bump22which has a smaller diameter than the first bump20. The first bump20can be used for connecting to a power source or a ground line.

The second bump22having a smaller diameter than the first bump20can be used for connecting to a signal line.

An intermediate layer containing, for example, nickel as a main component can be provided between the first base plating layer24and the first top plating layer28which form the first bump20and between the second base plating layer30and the second top plating layer32which form the second bump22.

The first base plating layer24and the second base plating layer30are each formed of a conductive metal, preferably a metal containing copper as a main component. The first base plating layer24and the second base plating layer30are preferably each formed to a height exceeding a surface of the solder resist layer16(a surface on an opposite side with respect to the base insulating layer12).

The first top plating layer28and the second top plating layer32are each formed of a metal which has a lower melting point than the first base plating layer24and the second base plating layer30and which is melted by a reflow treatment and is shaped into a substantially hemispherical shape as illustrated inFIG. 1, for example, a metal containing tin as a main component.

In the above-described printed wiring board according to the embodiment of the present invention, the first bump20has an embedded portion (20a) embedded in the solder resist layer16and an exposed portion (20b) exposed from the solder resist layer16(in the example ofFIG. 1, the embedded portion (20a) and a portion of the exposed portion (20b) are in the first base plating layer24), and a diameter of the embedded portion (20a) and a diameter of the exposed portion (20b) are substantially the same. Further, the second bump22has an embedded portion (22a) embedded in the solder resist layer16and an exposed portion (22b) exposed from the solder resist layer16(in the example ofFIG. 1, the embedded portion (22a) and a portion of the exposed portion (22b) are in the second base plating layer30), and a diameter of the embedded portion (22a) and a diameter of the exposed portion (22b) are substantially the same.

Therefore, according to the above-described printed wiring board in the embodiment of the present invention, since the embedded portion (20a) and the exposed portion (20b) of the first bump20have substantially the same diameter and the embedded portion (22a) and the exposed portion (22b) of the second bump22have substantially the same diameter, first bumps and second bumps can be formed at high densities. Further, according to a method for manufacturing a printed wiring board according to an embodiment of the present invention to be described later, as compared to a case of where an opening is sequentially formed for each bump using laser, it is not necessary to form an opening in a solder resist for each bump, and thus, productivity is improved.

In the following, a method for manufacturing the printed wiring board10illustrated inFIG. 1is described with reference toFIGS. 2A-2G.

First, as illustrated inFIG. 2A, the conductor layer14having a predetermined circuit pattern is formed on the base insulating layer12, and a dry film resist layer51is formed on the conductor layer14and the base insulating layer12, and, in a state in which a mask is formed at a position where openings of the dry film resist layer51can be formed, for example, by UV exposure, a first opening (16a) on the first conductor pad (14a) of the conductor layer14where a large-diameter bump is to be formed and a second opening (16b) on the second conductor pad (14b) of the conductor layer14where a small-diameter bump is to be formed are formed in the dry film resist layer51. An aspect ratio of the first opening (16a), that is, a ratio of a depth to a diameter at a bottom thereof can be set to 0.5 or less. An aspect ratio of the second opening (16b), that is, a ratio of a depth to a diameter at a bottom thereof can be set to 0.6 or more.

Next, as illustrated inFIG. 2B, an electrolytic copper plating treatment is performed in the first opening (16a) and the second opening (16b) of the dry film resist layer51, and the first base plating layer24and the second base plating layer30each formed of copper are respectively formed on the first conductor pad (14a) and the second conductor pad (14b). When it is not possible for the first base plating layer24and the second base plating layer30to have predetermined heights by performing a plating process once, the plating process is repeated two or more times.

As illustrated inFIG. 2C, an electrolytic Ni plating treatment and an electrolytic Sn plating treatment are performed with respect to the first base plating layer24and the second base plating layer30in the first opening (16a) and the second opening (16b), and the first top plating layer28and the second top plating layer32each formed of Sn are respectively formed on the first base plating layer24and the second base plating layer30via an intermediate layer26formed of Ni.

As illustrated inFIG. 2D, the dry film resist layer51is removed. As a result, the first bump post41including the first base plating layer24, the intermediate layer26and the first top plating layer28is formed on the first conductor pad (14a), and the second bump post42including the second base plating layer30, the intermediate layer26and the second top plating layer32is formed on the second conductor pad (14b).

As illustrated inFIG. 2E, the solder resist layer16is formed on the base insulating layer12, between outer peripheral portions of the conductor layer14, and between the first bump post41and the second bump post42and further on them.

As illustrated inFIG. 2F, a plasma treatment is performed on the solder resist layer16to thin the solder resist layer16over an entire surface thereof. As a result, the first top plating layer28and an upper portion of the first base plating layer24of the first bump post41, and, the second top plating layer32and an upper portion of the second base plating layer30of the second bump post42, are positioned on an outer side of an upper surface of the solder resist layer16. After that, the first top plating layer28and the second top plating layer32are subjected to a reflow treatment, and the printed wiring board10as illustrate inFIG. 1having the first bump20and the second bump22each having a hemispherical head can be obtained.

The plasma treatment described above can be performed using CF4or CF4+O2. Further, after the solder resist layer16is thinned over the entire surface thereof, residues left by the plasma treatment can be removed by a wet blast treatment.

According to the above-described method for manufacturing the printed wiring board, the openings are not formed using laser, and the first bump post41and the second bump post42are formed by plating in the openings formed by exposure in the dry film resist layer. Therefore, of the first bump20, the embedded portion (20a) embedded in the solder resist layer16and the exposed portion (20b) exposed from the solder resist layer16(in the example ofFIG. 1, the embedded portion (20a) and a portion of the exposed portion (20b) are in the first base plating layer24) have substantially the same diameter. Further, the second bump22has an embedded portion (22a) embedded in the solder resist layer16and an exposed portion (22b) exposed from the solder resist layer16(in the example ofFIG. 1, the embedded portion (22a) and a portion of the exposed portion (22b) are in the second base plating layer30), and a diameter of the embedded portion (22a) and a diameter of the exposed portion (22b) are substantially the same. As a result, a printed wiring board according to an embodiment of the present invention can be obtained.

In Japanese Patent Application Laid-Open Publication No. 2019-54111, in each of the base plating layers forming the metal posts of different sizes, a diameter of an exposed portion formed to be exposed to an outer side of the solder resist layer is larger than a diameter of an embedded portion formed to be embedded inside an opening. Therefore, there is a problem that it is difficult to form the metal posts at a high density.

A printed wiring board according to an embodiment of the present invention includes: a base insulating layer; a conductor layer that is formed on the base insulating layer and includes a first conductor pad and a second conductor pad, the second conductor pad having a smaller diameter than the first conductor pad; a solder resist layer formed on the base insulating layer and on the conductor layer; a first bump formed on the first conductor pad; and a second bump formed on the second conductor pad, the second bump having a smaller diameter than the first bump. The first bump has a first base plating layer and a first top plating layer formed on the first base plating layer. The second bump has a second base plating layer and a second top plating layer formed on the second base plating layer. The first base plating layer in the first bump has an embedded portion embedded in the solder resist layer and an exposed portion exposed from the solder resist layer, and a diameter of the embedded portion and a diameter of the exposed portion are substantially the same. The second base plating layer in the second bump has an embedded portion embedded in the solder resist layer and an exposed portion exposed from the solder resist layer, and a diameter of the embedded portion and a diameter of the exposed portion are substantially the same.

A method for manufacturing a printed wiring board according to an embodiment of the present invention includes: forming a base insulating layer; forming a conductor layer on the base insulating layer; forming a dry film resist layer on the base insulating layer and on the conductor layer; simultaneously forming, in the dry film resist layer by exposure, a first opening exposing a portion of the conductor layer as a first conductor pad and a second opening exposing another portion of the conductor layer as a second conductor pad, the second opening having a smaller diameter than the first opening; by performing first metal plating in the first opening and the second opening, forming a first base plating layer on the conductor layer in the first opening and forming a second base plating layer on the conductor layer in the second opening; by performing second metal plating in the first opening and the second opening, forming a first top plating layer on the first base plating layer in the first opening to form a first bump post, and forming a second top plating layer on the second base plating layer in the second opening to form a second bump post; removing the dry film resist layer; forming a solder resist layer on the base insulating layer and on the first bump post and the second bump post; and thinning the solder resist layer over an entire surface thereof by performing a plasma treatment such that the first top plating layer of the first bump post and the second top plating layer of the second bump post are positioned on an outer side of the solder resist layer.