Method for fabricating semiconductor lighting chip

A method for fabricating a semiconductor lighting chip includes steps of: providing a substrate; forming a first etching layer on the substrate; forming a connecting layer on the first etching layer; forming a second etching layer on the connecting layer; forming a lighting structure on the second etching layer; and etching the first etching layer, the connecting layer, the second etching layer and the lighting structure, wherein an etching rate of the first etching layer and the second etching layer is lager than that of the connecting layer and the lighting structure, thereby to form the connecting layer and the lighting structure each with an inverted frustum-shaped structure.

1. TECHNICAL FIELD

The disclosure generally relates to a method for fabricating a semiconductor lighting chip.

2. DESCRIPTION OF RELATED ART

In recent years, due to excellent light quality and high luminous efficiency, light emitting diodes (LEDs) have increasingly been used as substitutes for incandescent bulbs, compact fluorescent lamps and fluorescent tubes as light sources of illumination devices.

The LED generally includes a lighting chip, which includes an n-type semiconductor layer, an active layer and a p-type semiconductor layer sequentially formed on a substrate. When a voltage is applied between the n-type semiconductor layer and the p-type semiconductor layer, hole-electron recombination will happen at the active layer, and energy is released in the form of light.

In order to improve luminescent efficiency of the lighting chip, the lighting chip is etched to form an inverted frustum-shaped structure, in which a width of the lighting chip gradually decreases from an upper surface to a bottom surface thereof. Therefore, more light will travel to the external environment through inclined sidewalls of the lighting chip. However, the conventional etching of the lighting chip is time consuming.

Therefore, a method for fabricating a semiconductor lighting chip is desired to overcome the above described shortcoming.

DETAILED DESCRIPTION

An embodiment of a method for fabricating a semiconductor lighting chip will now be described in detail below and with reference to the drawings.

Referring toFIGS. 1-2, a substrate10is firstly provided. Material of the substrate10can be selected from a group consisting of Si, SiC, GaN and sapphire. In this embodiment, the substrate10is made of sapphire.

A first etching layer20is formed on an upper surface of the substrate10by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or hydride vapor phase epitaxy (HYPE). In this embodiment, the first etching layer20is a low temperature buffer layer made of GaN or AlN, and has a thickness about 20 nm.

After that, a connecting layer30is formed on an upper surface of the first etching layer20. In this embodiment, the connecting layer30is a non-doping GaN layer, which has a thickness about 1 μm.

A second etching layer40is then formed on an upper surface of the connecting layer30. In this embodiment, the second etching layer40is a super lattice layer consisting of a number of GaN layers42and a number of AlN layers44alternating with each other. A thickness of each GaN layer42is about 40 nm, and a thickness of each AlN layer44is about 20 nm. In this embodiment, the second etching layer40includes ten GaN layers42and ten AlN layers44; therefore, a total thickness of the second etching layer40is about 0.6 μm.

A lighting structure50is then formed on an upper surface of the second etching layer40. The lighting structure50includes a first semiconductor layer52, an active layer54and a second semiconductor layer56sequentially formed on the second etching layer40. In this embodiment, the first semiconductor layer52is an n-type GaN layer, which has a thickness of about 3 μm. The active layer54is a multiple quantum well (MQW) GaN layer, which has a thickness of about 145 nm. The second semiconductor layer is a p-type semiconductor layer, which has a thickness of about 0.1 μm.

Referring also toFIGS. 3-5, the first etching layer20, the connecting layer30, the second latching layer40, and the lighting structure50are then etched by KOH solution at a temperature of 90° C. for 5-10 minutes. Because the AlN layer is easier to etch than the GaN layer, the etching of the first etching layer20and the second etching layer40by the KOH solution is faster than that of the connecting layer30. Therefore, the first etching layer20and the second etching layer40are firstly etched, clearances are formed between the bottom surface of the connecting layer30and the upper surface of the substrate10, and clearances are also formed between the bottom surface of the lighting structure50and the upper surface of the connecting layer30. Therefore, the bottom surfaces of the lighting structure50and the connecting layer30are exposed to the external environment. The KOH solution will etch the lighting structure50and the connecting layer30from the plane (000-1), thereby forming inclined sidewalls of the lighting structure50and the connecting layer30with an inclined angle relative to a horizontal plane (i.e., a plane parallel to the upper surface of the substrate10) between 57 degrees and 62 degrees.

In addition, during etching the AlN layers44, etching of the AlN layers44by the KOH solution is faster than that of the GaN layers42, whereby the KOH solution will etch the AlN layers44and form clearances440at two lateral sides of the AlN layers44, therefore exposing lateral edges of the GaN layers42. Generally, the plane (000-1) of GaN structure has a relatively high surface energy, after the lateral edges of the GaN layers42are exposed to the external environment, the KOH solution will etch the GaN layers42from the bottom surfaces of the lateral edges and sidewalls of the GaN layers42at the same time. Therefore, planes (10-1-1) and (11-2-2) are remained after etching, and an included angle between each of the sidewalls of the GaN layers42and a horizontal plane extending from the corresponding bottom surface is in a range from 57 degrees to 62 degrees.

Referring toFIG. 5, after the etching of the lighting structure50, a transparent conductive layer60is formed on an upper surface of the second semiconductor layer56. A right portion of the lighting structure50is etched away to expose a partial surface of the first semiconductor layer52. A first electrode70and a second electrode72are then formed on the transparent conductive layer60and the first semiconductor layer52, respectively. The transparent conductive layer60can be made of indium-tin oxide or Ni/Au alloy to achieve uniform current distribution in the second semiconductor layer56.

Because the first etching layer20is formed between the connecting layer30and the substrate10, and the second etching layer40is formed between the lighting structure50and the connecting layer30, peripheral portions of the first etching layer20and the second etching layer40can be firstly etched to expose the bottom surfaces of the connecting layer30and the lighting structure50which will be simultaneously etched after the etching of the first etching layer20and the second etching layer40. Time consumed by the etching process is reduced due to the simultaneous etching of the bottom surfaces of the connecting layer30and the lighting structure50. For example, if the lighting chip is etched only at the bottom of the connecting layer30, it needs a time of t2to form a sidewall with a predetermined inclined angle. If the lighting chip is etched simultaneously from the bottom surfaces of the connecting layer30and the lighting structure50, it needs a time t1to form a side wall with the predetermined inclined angle. Obviously, t1is less than t2. Generally, the etching time of the lighting chip is adjustable by controlling the position of the second etching layer40. Specifically, as the smaller the distance between the second etching layer40and the active layer54is, the less time for etching the lighting chip is needed. Therefore, this method can flexibly control the manufacture period of the lighting chip.

In addition, the second etching layer40is a super lattice layer, which can effectively prevent dislocation defects80from extending from the connecting layer30to the active layer54, therefore improving luminescent efficiency of the lighting chip. In the conventional technology, because of the lattice mismatch between the connecting layer30and the substrate10, the dislocation defects80will be formed in the connecting layer30made of GaN. The dislocation defects80will extend to the active layer54in subsequent epitaxial process, which reduces the hole-electron recombination happening in the active layer54. In this embodiment, when a supper lattice layer is formed between the connecting layer30and the lighting structure50, the stress in the supper lattice layer will make the dislocation defects80change their original direction. Therefore, fewer dislocation defects80can extend to the lighting structure50and the luminescent efficiency of the lighting chip is improved.

In addition, by etching, the lighting structure50forms an inverted frustum-shaped structure in which a width of the lighting structure50gradually decreases from the upper surface to the bottom surface thereof. Similarly, the connecting layer30forms an inverted frustum-shaped structure in which a width of the lighting structure50gradually decreases from the upper surface to the bottom surface thereof. The inverted frustum-shaped structures of the connecting layer30and the lighting structure50can reflect the lighting from the active layer, therefore improving luminescent efficiency of the lighting chip.