Magnetic tunnel junction ternary content addressable memory

A Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) employing six transistors and exhibiting reduced standby leakage and improved area-efficiency. In the proposed TCAM, data can be written to the MJT devices by conventional current induced magnetization techniques and by controlling the source line, thereby eliminating the need for external writing circuitry.

BACKGROUND OF THE INVENTION

Field of the Invention

This invention relates to content addressable memories. More specifically, the invention provides a magnetic tunnel junction (MTJ) based ternary content addressable memory (TCAM).

Brief Description of the Prior Art

Magnetic Tunnel Junction (MTJ) is a spintronic device which stores data in the form of spin of an electron, unlike a static Complementary Metal-Oxide-Semiconductor (CMOS) memory cell, which stores data in the form of electric potential. An MJT device consists of three layers—a layer of magnetic oxide sandwiched between two layers of magnetic material. Data is stored in the form of magnetization in the two magnetic material layers. A logic ‘0’ is stored when the two magnetic layers are magnetized in the same direction and a logic ‘1’ is stored when the two magnetic layers are magnetized in the opposite direction.FIG. 1Aillustrates an MTJ device configuration in parallel and antiparallel states.

Pinned Layer (PL) magnetization exhibits a fixed magnetization, whereas Free Layer (FL) magnetization can be polarized parallel or anti-parallel with respect to the PL. In this context, it should be noted that the resistance of MTJ is high when PL and FL are in antiparallel configuration, whereas the resistance of MJT is low when PL an FL are parallel to each other. The value written to the MTJ depends on the direction and the strength of the charge current. The minimum current required to flip the state of the MTJ is called the critical current.FIG. 1Billustrates the directions charge current to write ‘1’ and ‘0’ to an MTJ device.

Tunnel Magneto Resistance (TMR) is the ratio of electrical resistances of the MTJ structure in parallel and antiparallel polarization states of FL relative to PL magnetization. If RHis the MTJ resistance in an antiparallel state and RLis the MTJ resistance in a parallel state, the TMR is defined as

Content Addressable Memory (CAM) is widely used in pattern matching, internet data processing, packet forwarding, for tag bits storage in a processor cache, for associative memory and in many other fields where searching a specific pattern of data is a major operation. The special functionality of the content search in CAM requires a comparison circuitry integrated with the memory cell. The required comparator, in addition to the memory element itself, adds area and power overhead in CAMs.

CAMs can be divided into two categories depending on the number of states that can be stored in the memory cell, namely: binary CAM (BCAM) and ternary CAM (TCAM). BCAM stores a binary bit, namely ‘0’ and ‘1’, whereas TCAM can store three possible values, namely ‘1’, ‘0’, and ‘don't care’ (X). CAMs can be further categorized into two topologies, namely NOR and NAND type (seeFIGS. 1C-1D). The stored bits are compared with the data on the search line (SL) and its complement (\SL) by XOR operation with the transistor network M1, M2, M3, and M4. To store data in a TCAM cell having a NOR-type architecture, data bit and the complement are stored in two SRAM cells.

The ‘don't care’ bit can be realized by storing ‘1’ in both SRAM cells, i.e., D=\D=1. In the case of a match, both SL-D and \SL-\D paths are disconnected, and the match line remains precharged. In the case of miss, either of the SL-D or \SL-\D connect ML to ground, which discharges the precharged ML.

In a NAND-type architecture, TCAM cells are connected in series. Data bit D and \D are derived from a single SRAM cell, unlike two SRAM cells in a NOR-type TCAM. The stored bit is masked by using a mask bit (M) in a parallel SRAM cell.

In case of match, the precharged ML is connected to ground by series TCAM cells of the word by turning the NMOS transistor M1‘ON’. Storing the mask bit as ‘1’ enables transistor M2, despite match or miss, which implements ‘don't care’ functionality. CMOS TCAM uses two SRAM cells, thereby doubling the area overhead, compared to conventional SRAM cells.

However, conventional CAMs suffer from area, power, and speed limitations. As it pertains to TCAM, the need to store and match a ‘don't care’ matching state requires two storage bits, which further worsens the area overhead. CMOS CAM is power hungry due to power consumed in match line (ML), search line, and leakage of the bit cell. In nanometer technologies, leakage power constitutes a major portion of the total power consumed in CAM memory. Non-volatile technologies, which are more area efficient than status random-access memory (SRAM) and can provide zero leakage, are attractive in such a scenario. However, continued improvement of TCAM is needed.

Accordingly, what is needed is improved area efficiency and non-volatility using MTJ-based TCAM for on-chip CAM applications. However, in view of the art considered as a whole at the time the present invention was made, it was not obvious to those of ordinary skill in the field of this invention how the shortcomings of the prior art could be overcome.

SUMMARY OF THE INVENTION

In accordance with the present invention, a Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) employing six transistors and exhibiting reduced standby leakage and improved area-efficiency is provided. In the proposed TCAM, data can be written to the MJT devices by conventional current induced magnetization techniques and by controlling the source line, thereby eliminating the need for external writing circuitry.

In one embodiment of the invention, a Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) cell is provided comprising, a first Magnetic Tunnel Junction (MTJ) device having a first node coupled to a search line, a second MTJ device having a first node coupled between to a complement search line, a first match line discharge transistor having a gate coupled to a second node of the first MTJ device and a second match line discharge transistor having a gate coupled to a second node of the second MTJ device. The TCAM cell further includes, a first word line selection transistor having a drain coupled to the gate of the first match line discharge transistor and the second node of the first MTJ device, a second word line selection transistor having a drain coupled to the gate of the second match line discharge transistor and to the second node of the second MTJ device, a write access transistor having a drain coupled to a source of the first word line selection transistor and to the source of the second word line selection transistor and a search enable transistor having a drain coupled to a source of the first word line selection transistor and to the source of the second word line selection transistor.

In a particular embodiment, the first MTJ device and the second MJT device include, a first magnetic layer having a pined magnetization direction, a second magnetic layer having a free magnetization direction and a magnetic oxide disposed between the first magnetic layer and the second magnetic layer. In the MJT devices, a logic state of a bit stored in the TCAM cell is represented by the relative resistance of the first MJT device and the second MJT device.

In the TCAM cell of the present invention, the threshold voltage of the first match line discharge transistor and the threshold voltage of the second match line discharge transistor are greater than a voltage at the second node of the first MJT device and a voltage at the second node of the second MJT device during a match condition. In addition, the threshold voltage of the first match line discharge transistor or the threshold voltage of the second match line discharge transistor is less than a voltage at the second node of the first MJT device and a voltage at the second node of the second MJT device during a mismatch condition.

In a particular embodiment of the TCAM cell, the write access transistor is sized to provide a drain current that is greater than a critical write current of the first MJT device and the second MJT device during a write operation.

In an additional embodiment of the TCAM cell, a low resistance value of the first MJT device and the second MJT device and a size of the search enable transistor are selected to provide a search current that is below a critical current of the first MJT device and the second MJT device and in addition, a high resistance value of the first MJT device and the second MJT device is determined by the Tunnel Magneto Resistance (TMR) of the TCAM cell.

In accordance with an additional embodiment of the present invention, a Ternary Content Addressable Memory (TCAM) device, comprising a plurality of TCAM cells in accordance with the TCAM cell of the present invention is provided.

In an additional embodiment, a method for operating a Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) cell is provided, which includes precharging a match line of the TCAM cell to positive voltage supply level, wherein the match line is coupled to a drain of a first match line discharge transistor and to a drain of a second match line transistor, and wherein a gate of the first match line discharge transistor is coupled to a second node of a first MJT device and a gate of the second match line discharge transistor is coupled to a second node of a second MJT device. The method of operating the TCAM cell further includes, providing a ground voltage supply level to a gate of a write access transistor and to a source line coupled to a source of the write access transistor and providing a positive voltage supply level to a gate of search enable transistor and to a gate of a first word line selection transistor and a gate of a second word line selection transistor, wherein a source of the search enable transistor is coupled to the source line and a drain of the search enable transistor is coupled to a source of the first match line discharge transistor and to a source of the second match line discharge transistor. The method further includes providing search data on a search line and on a complement search line to be compared against data stored in the first MJT device and in the second MJT device, where a first node of the first MJT device is coupled to the search line and a first node of the second MJT device is coupled to the complement search line and turning the first match line discharge transistor and the second match line discharge transistor OFF to maintain a charge on the precharged match line if the search data matches the data stored in the first MJT device and in the second MJT device, or turning the first match line discharge transistor and the second match line discharge transistor ON to discharge the precharged match line.

In a particular embodiment, the method of operating the TCAM further includes, writing the data stored in the first MJT device and in the second MJT device, prior to precharging the match line. Writing the data further includes, providing a ground voltage supply level to the gate of the search enable transistor to disable the search enable transistor, providing a positive voltage supply level to the gate of the write access transistor, wherein a drain of the write access transistor is coupled to a source of the first wordline selection transistor and to a source of the second wordline selection transistor and providing a positive voltage supply level to a first word line coupled to the gate of the first wordline selection transistor or to a second word line coupled to the gate of the second wordline selection transistor for a selected word and controlling the search line to write stored data in the first MJT device and in the second MJT device provided by the search line and the complement search line.

In a particular embodiment for writing a logic “1”, the method includes, providing a positive voltage supply level to the gate of the first wordline selection transistor and providing a ground voltage supply level to the gate of the second wordline selection transistor, providing a positive voltage supply level to the source line. The method of writing a logic “1” further includes, providing a ground voltage supply level to the search line to provide a write current to write an antiparallel state to the first MTJ device in the first cycle and providing a ground voltage supply level to the gate of the first wordline selection transistor, providing a positive voltage supply level to the gate of the second wordline selection transistor and providing a write current to write a parallel state to the second MTJ device, in a second cycle.

In an additional embodiment for writing a logic “0”, the method includes, providing a positive voltage supply level to the gate of the first wordline selection transistor and providing a ground voltage supply level to the gate of the second wordline selection transistor, providing a positive voltage supply level to the source line and to the complement search line. The method for writing a logic “0’ further includes, providing a ground voltage supply level to the search line to provide a write current from the search line to write a parallel state to the first MTJ device in a first cycle and providing a ground voltage supply level to the gate of the first wordline selection transistor, providing a positive voltage supply level to the gate of the second wordline selection transistor, providing a ground voltage supply level to the source line to providing a write current to write an antiparallel state to the second MTJ device, in a second cycle.

In a particular embodiment for writing logic “X”, the method includes, providing a positive voltage supply level to the gate of the first wordline selection transistor and to the gate of the second wordline selection transistor, providing a positive voltage supply level to the source line, and providing a ground voltage supply level to the search line and to the complement search line to provide a write current from the search line to write an antiparallel state to the first MTJ device and to write an antiparallel state to the second MTJ device, in the same cycle.

Accordingly, the TCAM cell and method of operation of the TCAM cell, in accordance with various embodiments of the present invention provides improved area efficiency and non-volatility using MTJ-based TCAM for on-chip CAM applications. These and other important objects, advantages, and features of the invention will become clear as this disclosure proceeds.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to a non-volatile NOR type TCAM cell using MTJ devices. The TCAM employs only 6 transistors and 2 MTJ devices, instead of 16 transistors, as is commonly known in the current state of the art for CMOS TCAM devices.

With reference toFIG. 2, a Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) cell200, in accordance with an embodiment of the present invention includes, a first Magnetic Tunnel Junction (MTJ) device205having a first node coupled to a search line200and a second MTJ device210having a first node coupled between to a complement search line225. The TCAM cell further includes, a first match line discharge transistor230having a gate coupled to a second node of the first MTJ device205and a second match line discharge transistor235having a gate coupled to a second node of the second MTJ device210. The TCAM cell additionally includes, a first word line selection transistor265having a drain coupled to the gate of the first match line discharge transistor230and the second node of the first MTJ device205and a second word line selection transistor270having a drain coupled to the gate of the second match line discharge transistor235and to the second node of the second MTJ device210. The TCAM cell further includes a write access transistor245having a drain coupled to a source of the first word line selection transistor265and to the source of the second word line selection transistor270and a search enable transistor240having a drain coupled to a source of the first word line selection transistor265and to the source of the second word line selection transistor270. As shown inFIG. 2, the first match line discharge transistor230further includes a drain coupled to a match line215and a source coupled to a source line260and wherein the second match line discharge transistor235further includes a drain coupled to the match line215and a source coupled to the source line260. In addition, a gate of the first word line selection transistor265is coupled to a first word line275and a gate of the second word line selection transistor270is coupled to a second word line277.

In order to enable writing to the first MJT device205and the second MJT device210, a gate of the write access transistor245is coupled to a write signal255and a source of the write access transistor is coupled to the source line260. In order to enable searching of the first MJT device205and the second MJT device210, a gate of the search enable transistor240is coupled to a search enable signal250and a source of the search enable transistor240is coupled to the source line260.

In operation of the TCAM cell200illustrated inFIG. 2, the two (2) MTJ devices205,210store data D and complement data \D, respectively. Match line discharge transistors M1230and M2235form a match line (ML) discharge network to discharge a precharged match line215, depending upon the result of a data comparison with the search lines SL220and \SL225. During a search, transistors M3265and M5240and M4270and M5240, along with the MTJs205,210, form a voltage divider network in which the drain voltages of M3265and M4270drive the gates of discharge transistors M1230and M2235, respectively.

The TCAM cell of the present invention is designed in such a way that during a match condition, the voltage of node X1at the gate of discharge transistor M1230and the voltage of node X2at the gate of discharge transistor M2235are below the threshold voltage of M1230and M2235, and as such, the match line (ML)215remains precharged. However, during a mismatch condition, the voltage of X1rises above the threshold of M1230or the voltage of X2rises above the threshold voltage of M2235, thus discharging the match line215.

Transistor M3265and M4270are the wordline (WL1and WL2) selection transistors, and transistor M6245is the write access transistor that turns ON only during a write (WR) operation. Transistor M6245can be sized larger to allow sufficient write current. Transistor M5240is driven by Search Enable (SE) signal250and is sized to limit the MTJ205,210current to provide a read disturb free search operation. The ‘don't care’ bit can be stored in the cell by storing ‘1’ in both D and \D bits. The search bit can be masked by driving SL=\SL=0 on the search lines220,225. The Source Line (SrL)260is used for two purposes, namely (1) write operation when the SrL260is connected to 0 or Vdddepending on the write data to the MTJs205,210; and (2) search operation when SrL260is driven to 0 to allow voltage division.

In the TCAM cell of the present invention, two match cases exist, namely (1) (D, \D)=(SL, \SL)=(1, 0); and (2) (D, \D)=(SL, \SL)=(0, 1). Since both cases are substantially similar, only the first case is explained herein. For (D, \S)=(1, 0), the left side MTJ205is in high resistance (RH) state whereas the right side MTJ210is in low resistance (RL) state. Since (SL, \SL)=(1, 0), the voltage at node X1is

VX⁢⁢1=Vsl*rRH+r=VM
and the voltage at node X2is 0. In this expression, r is the lumped ON resistance of transistors M3265and M5240, and Vstis SL voltage. To keep transistor M1230OFF during match, VX1should be lower than Vth0(i.e., the threshold voltage of M1230and M2235).

VX⁢⁢2=V\⁢sl*rRL+r=VMM
where V\slis \SL voltage. To keep transistor M2235ON during mismatch, VHshould be higher than Vth0. Similar analysis applies to the 2ndcase as well.

From the above equations VMM>VMfor the two cases as RH>RL. For the design to function properly (i.e., discharge ML during a mismatch condition at a higher speed compared to that of a match condition), RH, RL, and r should be selected such that VM<Vth0<VMM. The following analytical equations can be used to quantify the design parameters.

IMM and IM are the currents drawn from SL and \SL in case of mismatch and match, respectively, and Δ1, Δ2are the offset voltages with respect to Vth0. Subtracting Eqs. (1) and (2) and using RH=RL*(1+TMR), the following is obtained:

As such, the TCAM cell in accordance with the present invention an be optimized using three primary approaches: (1) maximizing the difference between mismatch and match voltages i.e., (Δ1+Δ2); (2) maximizing the absolute values of offsets from Vth0, i.e., |Δ1| and |Δ2| to keep M1/M2strongly ON or OFF as needed during mismatch and match, respectively, and (3) lowering the search current below critical write current of MTJ.

From Eq. (4), it can be concluded that higher TMR, higher RH, and higher r can be employed to enhance (Δ1+Δ2). Although higher r and RLis also good for maximizing Δ1, it minimizes Δ2. A lower Δ2can turn ON M1/M2during match, degrading the sense margin.FIG. 3illustrates a Vgsmargin diagram illustrating the best and worst VMand VMMwith respect to Vth0.

The voltages VMM1, VMM3, VM1and VM3provide poor sense margin compared to VMM2and VM2, even with the same magnitude of Δ1+Δ2. The ideal margin is obtained when RH=∞ and RL=0, which gives VMM=Vddand VM=0. However, a lower RLcould be detrimental for read disturb due to the resulting high search current conditions. High values of RHand RLensure low search line currents. This, in combination with high TMR can provide better Vgsmargin, i.e., (Δ1+Δ2) with low search power consumption.

In the TCAM of the present invention200, the search lines SL220and \SL225are used to write data to the MTJ devices205,210. Table 1 summarizes the states of the control signals in the write operation. Writing ‘1’ and ‘0’ requires two cycles to write to the two MTJs205,210while ‘X’ can be written in a single cycle. During a write the ML precharge is disabled to avoid power consumption from the ML215. This is achieved by pulling the ‘precharge’ signal high. NMOS transistor M6245is turned ON during write by WR signal255. Note that M6245is sized to provide a drain current greater than the critical write current of the MTJ devices205,210. The search enable signal SE250is pulled to ground which disables transistor M5240. The WLxis turned ON only for the selected word so that the unselected cells are unaffected. The source line SrL260is controlled appropriately to write a ‘1’ or ‘0’.

FIG. 4Aillustrates the equivalent circuit of the TCAM cell during write to /D bit. The transistors are replaced with equivalent ON resistances. Resistors r3, r4and, r6are equivalent resistors of M3265, M4270and M6245, respectively. The writing operation is described below. In the first cycle, writing to D bit is enabled by pulling WL1275to Vddand path to \D is disabled by pulling WL2277to ground. In the second cycle of write operation, writing to \D bit is enabled by pulling WL2277to Vddand D bit path is disabled by pulling WL1275to ground.

1. Writing ‘1’: In the first cycle, SrL260is pulled high and SL220line is pulled to ground. The write current flows from SL220writing antiparallel state to the first MTJ device205storing bit D. There is no current through the other MTJ device210as the WL2277control signal is at zero potential. In the second cycle the SrL260is held high, SL220is pulled to Vddand \SL225is pulled low which programs the second MTJ device210, storing \D to parallel state. There is no current through the other MTJ205as SL220and SrL260are both high.

2. Writing ‘0’: In the first cycle, the SrL260and \SL225are pulled high and the SL220line is pulled low. The first cycle writes parallel magnetization state to MTJ storing D bit. In the second cycle, the SrL260is pulled low while retaining the states of SL220and \SL225at 0 and \Vdd, respectively, which programs the \D bit to antiparallel state.

3. Writing ‘X’: The ‘X’ state can be stored by writing logic 1 to both D and \D. Both the word lines WL1275and WL2277are pulled high. The SrL260is pulled to Vddand the search lines SL220and \SL225are pulled to ground. The current flows through both the MTJ devices205,210storing antiparallel states to D and \D.

In the TCAM cell of the present invention, search is a single cycle operation. The ML215is precharged to Vddand WR255is pulled to ground. The SrL260is pulled to ground throughout the search operation. Next, SE250, WL1275and WL2277are pulled high to enable the conducting path through M5240, M3265and M4270(Table 1). Either VMMor VMvoltage is developed depending on the match or mismatch, respectively, at the gate of M1230or M2235. The search line SL220is pulled to Vdd and complement search line \SL225is pulled low to search a logic ‘1’. Similarly, SL220is pulled low an, \SL225is pulled to Vdd to search for logic ‘0’. Both SL220and \SL225are pulled low to search ‘X’. Circuit operation in match and mismatch cases are discussed below.FIG. 4Bshows the equivalent circuit during search operation.

It should be noted that VX2is less than VX1and appears due to the potential across r5which results in a current though RLeven when \SL=0. The transistors M3265and M5250are sized such that VX1<Vth0. So M1230and M2235are turned OFF and the ML215remains precharged. The other match case i.e., (D, \D)=(SL, \SL)=(0, 1) is similar.

Vd1(mismatch)>Vth0>Vdh(match). Under these conditions both M1230and M2235are turned ON to discharge the precharged ML215which provides better sense margin.

FIG. 5illustrates the ML215voltages during search operation for the TCAM cell of varied word sizes, namely 1, 16, 128 and 256-bit for match and mismatch. Predictive 22 nm model is used for simulations. The waveforms correspond to the worst case sense margin (i.e., single miss in the whole word). The rate of discharge of ML line215in match case increases with the word size due to the increased number of cells leaking the ML current through weakly driven M1230and M2235. This in turn limits the sense margin for larger word sizes.

The low MTJ resistance and sizing of the sense enable transistor M5240are chosen to keep the search current below the critical current while providing a sufficient Vgsto drive M1230and M2235in order to differentiate the miss and match cases. The high MTJ resistance is determined by the Tunnel Magneto Resistance (TMR).

The write access transistor M6255is sized to provide greater than critical current to the MTJ during write operation. A range of RL(5 k to 9 k) was simulated with fixed TMR of 100%. The trend is shown in theFIG. 6A, for a 16-bit word. It can be observed from the plot that high resistance values with smaller NMOS widths provide good sense margin (close to Vdd/2) with lower MTJ current from the search line. Based on this, RL=8 kΩ is selected for the current design. The MTJ current during mismatch is also plotted. It should be noted that mismatch current is always greater than the match current, and thus it was considered for estimating the worst case read disturb during search operation.

Width of the NMOS devices M3265, M4270and M5240are important parameters to ensure low search current and reduce the power dissipated from the search lines. The plot in theFIG. 6Ashows the distribution of MTJ current for various widths of the NMOS device M5240with different RLvalues. Smaller width of NMOS devices offers higher resistance, reduces search current (good for lower read disturb and power) and also improves the sense margin. However, minimum sized transistor can be susceptible to manufacturing process variations.

In an exemplary embodiment, a width of 50 nm was selected for M5240for the low search current and process variation tolerance, respectively. It can be observed from the plot inFIG. 6Athat miss case current is highly dependent upon the width of the M5NMOS device240and remains almost the same for different RLvalues. In this embodiment, high RLis selected to keep the TMR within practical limits, 100%-150%. To determine the optimal size of transistors M3265and M4270, the size was swept and the sense margin and sense current was observed for 50 nm M5240width, as illustrated inFIG. 6B. It is evident from the plot ofFIG. 6Bthat the sense margin increases sharply from 50 nm up to 200 nm. After 200 nm, improvement in the sense margin saturates. Also, the search current increases by approximately 10× with increase in the width by 25 nm. Thus, in an exemplary embodiment, the width of M3365and M4270was selected to be 200 nm.

FIG. 7illustrates the trend of match current and sense margin versus width of NMOS M5240for different TMR values. The RLof MTJ is fixed to 8 K for this analysis and TMR and RHare selected for low match case search current and higher sense margin. It can be seen that higher TMR ensures better sense margin and low MTJ match current with fixed RL. It can be seen from the plot ofFIG. 7that the NMOS width does not affect the MTJ current compared to that in the miss case because of the fact that the MTJ high resistance RHdominates the effective NMOS resistance of M3365, M4270and M5240. This also results in low drain voltage at M3365and M4270compared to that in the mismatch case. So, the width of the NMOS devices is selected based on the mismatch current drawn from the SL, while the TMR is chosen to satisfy the match case conditions. It can be noted that the sense margin benefit of a TMR greater than 125% saturates. Hence, TMR=125% has been used and provides less than 45 μA of match current with a sense margin close to 500 mV.

Resistance of an MTJ device is shown to depend upon oxide thickness and surface area of free layer. Therefore by tuning these parameters it is possible to obtain an MTJ device resistance of RL=8 kΩ. Similarly, it has been experimentally shown that TMR could be improved up to 236%. This can be used during design time to ensure TMR=125% for proper functioning of the current TCAM cells.

To simulate the results of the exemplary TCAM cell of the present invention, TMR=125% was used with RL=8 kΩ, 50 nm M5transistor240and 200 nm M3365and M4270transistors. MTJ models were selected with 29 nm×22 nm×3 nm free layer dimension and 0.876 nm oxide (MgO) thickness for design simulations. Word size of 16, 32, 64, 128 and 256-bit was simulated to analyze the design with respect to process, temperature and voltage variations.

The worst case sense margin, sense delay (for 50 mV sense margin development) and the Power Delay Product (PDP) per bit search from 10° C. to 90° C. are shown inFIGS. 8A-8Cfor different word sizes. A single bit mismatch is considered for sense margin and sense delay as it is the worst case condition. The sense delay increases proportionally as the word size due to increment in ML interconnect capacitance. As the temperature increases, the rate of ML215discharge increases due to lowering of threshold voltage of the discharge transistors M1230and M2235.

Sense margin decreases with temperature due to ML215discharge through subthreshold leakage current of discharge transistors in the match case. Therefore, the sense delay (for 50 mV sense margin) increases as the temperature increases. The PDP is proportional to the change in sense delay while the operating voltage and the search line current are similar across different temperatures. FromFIGS. 8A-8C, a reliable sense margin of greater than 50 mV across the range of temperature till 256-bit word size was obtained.

In this exemplary embodiment, the operating voltage is varied from 0.7V to 1.2V to observe the sensitivity of sense margin, sense delay and PDP per bit search, as illustrated inFIGS. 9A-9C. A 50 mV sense development time is used to measure the sense delay. Below 0.7V the sense margin of 256-bit CAM word is less than 50 mV. Sense margin and sense delay are sensitive to Vdddue to lowering of gate voltage of M1230and M2235, while their threshold voltages remain fixed. At lower voltages the M1230and M2235transistors fail to turn ON, or weakly conduct, even during mismatch, thereby degrading the sense margin (especially for wider words). Sense delay for a 256-bit TCAM word varies from 124 ps at 1.2V to 2.098 ns at of 0.7V (sense delay is plotted in log 10 scale). The increase in the sense delay results in a sharp increase in the PDP, at 0.7V.

For process variation analysis of the exemplary embodiment, fast-fast (FF), slow-slow (SS), and typical-typical (TT) corners were considered. The process variation was modeled by lumping the variation in channel length, oxide thickness, flat band conditions, etc., into threshold voltage of the transistor. The SS (FF) is simulated by adding (subtracting) 150 mV from nominal threshold voltage. The worst case sense margin is plotted for different supply voltages at TT, SS and FF corners, as shown inFIGS. 10A-10C. It can be observed that the embodiment of the TCAM cell can provide a reliable sense margin of above 50 mV at all corners till 0.75V for 128-bit words or less. The poor sense margin at lower voltages is linked with poor Vgsacross M1230and M2235that keeps the ML215precharged, even in mismatch conditions.

The 256-bit word fails to provide adequate sense margin in FF corner at 1V. This is primarily due to poor Δ2when Vth0moves down coupled with leakage from the match bits, as shown inFIG. 4. Thus, bit match and mismatch bits leak, thereby degrading the sense margin. As such, threshold voltage modulation and search enable (SE) voltage boosting or underdrive was shown to improve sense margin for 256-bit word simulations.

In order to solve the poor sense margin, Vth0, Δ1and Δ2were modulated by exploring threshold voltage modulation of transistor M1230and M2235(to tune Vth0) and SE250voltage modulation (to tune Δ1and Δ2).FIG. 11Aillustrated the results at 1V for the three PV corners for 256-bit word at different SE signal voltages, and 0 mV, 50 mV and 100 mV higher Vth. Change in the gate drive of M3265and M4270changes their ON resistance and results in corresponding change in Δ1and Δ2. It can be noted that an optimum choice of SE can improve the sense margin. Moreover, repositioning of Vth0can improve the sense margin even further.FIG. 11Billustrates the sense margin across three PV corners with Vthimplants at 850 mV supply voltage. It can be noted that Vthmodulation can improve the worst case sense margin significantly (FF and SS in this case) even though the sense margin in TT corner is degraded. The improvement results from decreased match case current through M1230and M2235at SS and the reverse effect in miss case at FF. At the same time lower SE increases the resistance of M3/M4which in turn increases Δ2. As expected, the sense margin in FF with Vthimplant is comparable to TT corner without implant. With 100 mV Vthimplant the design can provide a reliable sense margin of above 40 mV in all the PV corners, even without SE modulation. A 150 mV SE under-drive can improve the sense margin at TT to more than 120 mV and a 250 mV SE under-drive can improve the sense margin at FF to more than 50 mV.

TCAM cell currently known in the art consist of 16 transistors while the TCAM cell in accordance with the present invention, includes only 6 NMOS transistors and 2 MTJ devices, which results in a device that is 127% more area-efficient.

For power comparison, the CMOS TCAM in the prior art was implemented and simulated using 22 nm predictive model. The leakage power of the TCAM cell of the present invention is zero while SRAM TCAM consumes a considerable amount of standby power. In the mostly OFF applications, such as “Internet of Things” and smartphone, the TCAM cell of the present invention could be quite beneficial compared to CMOS CAM. While the search power consumption of the TCAM cell of the present invention is higher compared to CMOS TCAM currently known in the art, due to the search line current (—51 uA in case of a mismatch at IV) drawn to generate a secondary voltage at the drain terminals of M3265and M4270, which enables the discharge transistors of ML215. The search line current can be reduced further by selecting MTJ devices with high RLand high TMR. The power consumption during search operation of ‘1’ and ‘0’ bits at 0.8V in MTJ device based TCAM is observed to be up to 80% higher in the worst case (successful search of ‘1’) compared to NOR type CMOS TCAM currently known in the art. Table 2 summarizes the power consumption during search operation of ‘1’, ‘0’ and ‘X’ bits at 1V and 0.8V.

A spintronic TCAM was disclosed herein and can be seen to be promising for zero standby leakage and area-efficiency, thus improving the functioning of the CAM and overall computing system. Detailed analysis was conducted in the presence of process, voltage, and temperature variations for a wide range of word sizes. As such, it is shown that, the TCAM cell design can operate with reliable sense margin up to 128-bit word size till 0.7V. Threshold voltage modulation and search enable underdrive were also discussed herein to improve sense margin for 256-bit word. The TCAM cell of the present invention is 127% area-efficient compared to conventional CMOS TCAM and 33-50% area efficient compared to other spintronic CAMs.