Correcting data reading device in a digital convergence correcting device

A digital convergence correcting device effecting convergence correction by using convergence correcting data stored in a memory which includes an address fixing device which, in the case where convergence correcting data are insufficient, reads out in succession the correcting data corresponding to the last horizontal scanning line for the portion lacking in the data so that the correcting data are used repeatedly, and which, in the case where convergence correcting data are excessive, only necessary convergence correcting data are used.

BACKGROUND OF THE INVENTION 
This invention relates to a device for correcting the convergence of an 
electron beam in a color television receiver and in particular to a 
digital convergence correcting device used in the case where a high 
precision convergence correction is required. 
A prior art digital convergence correcting device is disclosed in 
JP-B-56-40355. According to the invention disclosed in this publication, 
convergence correcting waveforms (correcting data) are stored in a memory 
and the correcting data corresponding to the position of the scanning line 
are read out from the memory to correct the convergence. This prior art 
example is shown in FIG. 11. 
In FIG. 11 convergence correcting waveforms corresponding to the position 
of the scanning line on the image screen are stored as correcting data in 
a memory 1. These correcting data stored in the memory 1 are read out in 
synchronism with the scanning of the image screen and supplied to a D/A 
converter 2. The correcting data are converted into analog signal in the 
D/A converter 2. Thus, a continuous analog correcting waveform signal is 
outputted through a low pass filter (LPF) 3. Further, the output signal of 
this LPF is inputted to a convergence yoke 5 through a voltage-current 
converting amplifier 4. 
The prior art digital convergence correcting device is used only in there 
industrial color television receivers, etc., for which a high precision 
correction was required. For this reason the prior art convergence 
correcting device was is used in a color television receiver whose input 
signal is standardized. Consequently, heretofore no attention has been 
paid to the convergence correction for television signals produced at 
special reproduction, etc. in VTRs, video disc devices for home use, etc., 
different from those that are standardized. 
For example, for high speed reverse direction picture searches in VTR's, 
the number of scanning lines on the image screen constituting one field 
increases. The correcting data stored in the memory 1 are formed on the 
basis of a standard signal for which the number of scanning lines is 
predetermined. For this reason, in the prior art convergence correcting 
device it is not possible to effect the convergence correction 
corresponding to the increase in the number of scanning lines for high 
speed reverse direction picture search. As the result, misconvergence 
takes place in the lower part of the image and image quality is 
significantly deteriorated. 
Hereinbelow, the reason why the number of scanning lines on the image 
screen constituting one field increases for high speed reverse direction 
picture searches in VTRs, for home use will be explained, referring to 
FIGS. 12(a), 12(b), 13(a) and 13(b). 
FIG. 12(a) is a scheme for explaining video tracks 11 for the image signal 
recorded on a video tape 10 for a VTR. In the figure, for normal 
reproduction a video head 12 scans the tape as indicated by an arrow 13 to 
reproduce the image signal recorded on the video track 11. Information 
corresponding to one field is recorded in the video track 11. Denoting the 
displacement velocity of the video tape 10 at this time by v.sub.t and the 
peripheral velocity of the cylinder (not shown in the figure) around which 
the tape is wound, by v.sub.cl the velocity of the video head 12 with 
respect to the tape can be represented by the vector sum of v.sub.t and 
v.sub.cl. 
Next, the state in which the video tape is scanned in the reverse direction 
is indicated in FIG. 13(a). The video head 12 scans the tape, as indicated 
by arrow 14, and reproduces the image signal on the video track 11 along 
an oblique direction. The velocity of the video tape 10 at this time is 
represented by -v.sub.t. 
Accordingly, in the state indicated in FIG. 13(a), the velocity of the 
video tape 10 --v.sub.t, the peripheral velocity of the cylinder v.sub.c2 
and the velocity of the video head 12 with respect to the tape v.sub.r 
have a vectorial relationship as indicated in FIG. 13(b). 
In this case, the scanning length in FIG. 13(a) is longer than in FIG. 
13(b) and the number of scanning lines in one field increases. 
In the above, for the description purpose of simplifying explanation, it 
was assumed that the image is reproduced with the same speed in the 
reverse direction. The above explanation is valid also for a high speed 
reverse direction picture search. Consequently, with increasing of the 
speed of the picture search in the reverse direction, the number of 
scanning lines in one field increases. In a usual VTR the number of 
scanning lines can increase by about 20 lines. That is, the number of 
scanning lines in one field can be greater than 260. 
It is a matter of course that the number of scanning lines in one field 
decreases for a forward direction picture search, contrarily with respect 
to that in the reverse direction. 
For this reason, in the case where correcting data for the digital 
convergence correction corresponding to the number of scanning lines for 
the standard image signal are stored in the memory, the state in which 
correcting data are insufficient or excessive can take place. 
As described above, the prior art industrial digital convergence correcting 
device has a problem as follows: the convergence correction is impossible 
for the image signals whose number of scanning lines is increased or 
decreased for special reproduction in VTRs, etc., which gives rise to the 
problem that misconvergence takes place in the part of the image screen 
corresponding to the increase or decrease in the number of scanning lines 
and the image quantity is deteriorated. 
SUMMARY OF THE INVENTION 
The object of this invention is to provide a digital convergence correcting 
device which prevents that misconvergence (deterioration in the image 
quality) which takes place in any part of the whole image screen, even in 
the case where the convergence is corrected for signals whose number of 
scanning lines is increased or decreased. 
A digital convergence correcting device according to this invention is 
characterized in that it comprises address signal generating means for 
supplying read out address signals to a memory in which convergence 
correcting data are stored, and after having reached the last address 
signal, it is supplied in succession to the memory. When the vertical 
scanning of the image screen is terminated, the address signal generating 
means is reset. 
According to this invention in the case where an image signal whose number 
of scanning lines is greater than that of the standard image signal is 
displayed on the image screen for the part corresponding to the increased 
number of scanning lines, the correcting data corresponding to the 
position of the scanning line just prior thereto (the last scanning line 
of the standard image signal) are used repeatedly to prevent 
misconvergence in the part of the image screen described above. 
On the contrary, in the case where an image signal whose number of scanning 
lines is smaller than that of the standard image signal is displayed on 
the image screen, the operation for reading out the correcting data is 
reset by the vertical blanking signal so that only the correcting data 
corresponding to the necessary scanning lines are used. 
As described above, according to this invention, convergence correction is 
possible even if the number of scanning lines varies.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 is a block diagram illustrating an embodiment of this invention, in 
which reference numeral 1 is a memory in which convergence correcting data 
are stored; 7 is a line address counter; 8 is a row address counter; 50 is 
an input terminal for video signals; 51 is a synchronization pulse 
separating circuit; 52 and 53 are waveforming circuits; 54 is a 
multiplying circuit; and 55 is a judging circuit. 
FIG. 2 is a front view of an image screen of a television receiver. In the 
figure the position in the horizontal direction is represented by x and 
the position in the vertical direction by y. The correcting data in the 
horizontal direction and those in the vertical direction corresponding to 
coordinates (x, y) of scanning lines l1, l2, l3, . . . , ln in the 
horizontal direction are stored in the memory 1 in FIG. 1. 
For a color television receiver, correction data are necessary for 3 sorts 
of signals red, green and blue, but here, for the sake of simplifying 
explanation, only the horizontal direction correcting data for green will 
be explained. 
In FIG. 1, access positions for the data stored in the memory 1 are set by 
line and row address signals. That is, the access positions for the data 
stored in the memory 1 are set by the line address signal coming from the 
line address counter 7 and the row address signal coming from the row 
address counter 8. The addresses of the scanning lines l1, l2, l3, . . . , 
ln on the image screen correspond to line addresses. Consequently the line 
address counter 7 generates line address signals by counting pulses H 
having the same repetition frequency as the horizontal synchronization 
signal. Further, the row address corresponds to the position x on the 
scanning line. Consequently, the row address counter 8 generates row 
address signals by counting reference clock pulses C having a 
predetermined clock frequency and it is reset by the pulses H described 
above. 
Now various sorts of pulses for controlling the line address counter 7 and 
the row address counter 8 will be described. 
The video signal is inputted in the terminal 50 and the horizontal 
synchronization signal and the vertical synchronization signal contained 
in the video signal are separated from each other in the synchronization 
pulse separating circuit 51. The separated horizontal synchronization 
signal is waveformed in the waveforming circuit 52 and inputted in the 
input clock terminal IN of the line address counter 7. At the same time 
the horizontal synchronization signal is inputted in the reset terminal R 
of the row address counter 8 (pulse H). 
Further, the separated horizontal synchronization signal is multiplied in 
the multiplying circuit 54 so as to be transformed into a clock signal 
having a predetermined pulse frequency. This clock signal is inputted in 
the input clock terminal CK of the row address counter 8 as clock C. That 
is, the row address counter 8 counts the clock C and it is reset by the 
pulse H. 
The line address counter 7 counts the pulse H. The vertical synchronization 
signal is waveformed by the waveforming circuit 53 and outputted as a 
pulse V, which is inputted to the reset terminal R. The line address 
counter 7 is reset by this pulse V. Further, when the count number of the 
line address counter 7 has reached the line corresponding to the position 
of the last scanning line of the data stored in the memory 1, the judging 
circuit 55 judges it; the count is stopped at this point of time; and an 
instruction to hold the count value at this time is supplied to the line 
address counter. 
The greater the number of the correcting data corresponding to the 
coordinates (x, y) is, the higher the precision is. However it is 
desirable to form the correcting data, as follows, on the basis of the 
device necessary for forming them, the time of adjustment and the capacity 
of the memory. 
At first the image screen 6 is divided into a lattice shape, as indicated 
in FIG. 3, and the correcting data are determined for every intersection 
(X, Y) in the lattice. Then the correcting data are set for an arbitrary 
position in the coordinates (x, y) by effecting an interpolation operation 
using the correcting data set for every intersection (X, Y). The position 
in the ordinate y is determined often, corresponding to the position of 
the horizontal scanning line and ten and several points in the abscissa x 
are chosen for every horizontal scanning line in the horizontal direction. 
Therefore, the region where positions in the coordinates (x, y) are chosen 
is in accordance with the effective image screen of the television 
receiver, but the number of points which are actually chosen is determined 
depending on the capacity of the memory and the power of correction. 
FIG. 4(a) shows the waveform of the signal around the vertical flyback 
period (20H), FIG. 4(b) indicates the vertical synchronization pulse, and 
FIG. 4(c) indicates the pulse V, which is the vertical blanking pulse 
formed from the vertical synchronization pulse. 
As indicated in FIG. 4(a), the number of the effective scanning lines is 
about 242.5 obtained by subtracting the synchronization from the number of 
scanning lines in one field, which is 262.5. 
For the memory for storing the correcting data, apart from the fact that it 
has a required capacity, it is desirable that the address assignment can 
be effected in a simple manner. In this embodiment a memory for general 
use for 256 lines is used. 
From the above explanation it can be understood that the correcting data 
are stored in 243 lines in the memory for 256 lines. 
Consequently, when the line address counter is reset by the falling edge of 
the pulse V, which is the vertical blanking pulse, the data of 242.5 lines 
are read out. 
Next the operation of this embodiment will be explained more in detail. 
FIG. 5 is a circuit diagram indicating a concrete example of the line 
address counter 7 and the judging circuit 55 in FIG. 1. 
Here important points in the operation of the circuit indicated in FIG. 5 
are as follows. 
(1) The line address counter 7 counts the pulse H, which is the horizontal 
synchronization pulse, and it is reset by the pulse V, which is the 
vertical blanking pulse, to load the initial value therein. 
(2) When the maximum count number, i.e. 243, is read out, that value, i.e. 
243, is held, as it is. 
In FIG. 5, A, B, C, D, E, F, G and H in the counter 7 are set at the 
initial value 0. Output signals Q.sub.0, Q.sub.l, Q.sub.2, Q.sub.3, 
Q.sub.4, Q.sub.5, .sub.Q6 and Q.sub.7 are counter output signals. These 
counter output signals are inputted to the memory and line addresses are 
assigned. A NAND gate 15 outputs a signal "Low", when the output of the 
counter 7 is 243. The T input terminal is the input terminal for the pulse 
H and it is valid, only when a signal "High"is inputted in the P input 
terminal. 
When the number of pulses H inputted in the T input terminal is 243, the 
potential at the P input terminal becomes "Low" and the counting operation 
is stopped. After that, the pulse V, which is the vertical blanking pulse, 
is inputted in the "Load" input terminal. The counter 7 is reset by the 
pulse V, which is the vertical blanking pulse, and thereafter it begins to 
count pulses, starting from the initial value 0. 
It is a matter of course that, in the case where the number of scanning 
lines is below 243 such as for a high speed picture search, the counter 7 
is reset by the pulse V, which is the vertical blanking pulse, before the 
count number reaches 243. 
Another concrete example of the line address counter 7 and the judging 
circuit 55 is shown in FIG. 6. The difference between the concrete example 
indicated in FIG. 6 and that indicated in FIG. 5 is that the maximum value 
of the count number is 256 in the former (the maximum value of the count 
number is 243 in the latter). At the maximum count value 256 a signal 
"High" is outputted from the C output terminal of the counter 7. This 
signal "High" is converted into a signal "Low"by an inverter 20, which 
signal "Low" is inputted in the P input terminal. After that the counter 7 
is reset by the pulse V, which is the vertical blanking pulse inputted to 
the input terminal "Load", and begins counting from 0. The example 
indicated in FIG. 6 is one in which the memory is used efficiently, 
because the usual memory corresponds to 256 lines. That is, in this 
concrete example, the correcting data are set corresponding to y in the 
coordinates (x, y), which is 256, explained referring to FIG. 3. 
In the example indicated in FIG. 6, for high speed reverse direction 
picture search, the correcting data of the 256-th line is used repeatedly. 
The other operation of the embodiment indicated in FIG. 6 is identical to 
that in the embodiment indicated in FIG. 5. 
FIG. 7 is a block diagram illustrating still another embodiment of this 
invention. The blocks having functions identical to those of the 
constituting parts of the embodiment indicated in FIG. 1 are denoted by 
identical reference numerals. 
The difference from the embodiment indicated in FIG. 1 is that the line 
address counter 7 and the row address counter 8 are operated by pulses 
based on the horizontal and the vertical synchronization signals inputted 
in the block 57, which represents a deflecting circuit. 
The horizontal synchronization signal separated by the synchronization 
pulse separating circuit 51 passes through an automatic frequency control 
(AFC) 56 to be inputted to the block 57 representing a deflecting circuit, 
and at the same time it is inputted to the waveforming circuit 52. The 
output signal of the waveforming circuit 52 is inputted to the row address 
counter 8 as the reset pulse and to the row address counter 8 as the input 
clock C through the multiplying circuit 54. 
The AFC 56 and the multiplying circuit 54 are usually composed of a phase 
locked loop (PLL). Consequently, the S/N of the horizontal synchronization 
signal inputted to the multiplying circuit 54 is improved by the AFC 56 
and thus it is possible for the design of the multiplying circuit 54 to 
provide emphasis in the capture range rather than in the S/N 
characteristics. 
The multiplying circuit 54, in which a PLL is used, consists of a phase 
comparator (PC) 100, a voltage controlled oscillator (VCO) 101, a 
frequency divider (1/n) 102, etc. Generally the central frequency of the 
voltage controlled oscillator 101 is used after having being well 
adjusted. However, as described above, by widening the capture range the 
adjustment is made unnecessary, which brings about a cost merit. 
Further the pulse V for the reset inputted in the line address counter 7 is 
a signal obtained by waveforming the clock signal synchronized with the 
vertical synchronization signal inputted to the deflection circuit block 
57 by means of the waveforming circuit 58. 
As can be understood from the above explanation, the operation of the line 
address counter 7 and the row address counter 8 is in synchronism with the 
deflection circuit block 57. Consequently, even in the case where the 
operation of the deflection circuit block 57 is disturbed by external 
disturbance, etc., since the operation of the digital convergence is 
disturbed in synchronism therewith, an advantage is obtained that 
deterioration in the image quality is reduced. 
FIG. 8 illustrates still another embodiment of this invention. The 
difference thereof from the embodiment indicated in FIG. 7 consists in the 
connecting structure among the multiplying circuit 54, the waveforming 
circuit 58 and the inverter 203. 
The multiplying circuit 54 generates the input clock C inputted to the row 
address counter 8, which clock C is in synchronism in phase with the 
horizontal synchronization signal. In the embodiment indicated in FIG. 8, 
the multiplying circuit 54 is composed of an NAND gate 200, a resistor 201 
and a capacitor 202. FIG. 9 shows waveforms of signals in various parts of 
the embodiment indicated in FIG. 8. 
A clock signal H, which is in synchronism in phase with the horizontal 
synchronization signal, as indicated in FIG. 9 (a), is outputted from the 
output terminal of the waveforming circuit 58. This signal H is inputted 
to the NAND gate 200. When this clock signal H is high, the multiplying 
circuit 54 constitutes an oscillating circuit, together with the resistor 
201 and the capacitor 202. When the clock signal is low, the multiplying 
circuit 54 does not oscillate. 
Consequently, the clock signal C, which is in synchronism with the clock 
signal H, is outputted from the multiplying circuit 54, as indicated in 
FIG. 9(b). 
Further, the inverter 203 is used for forming the pulse H. According to 
this embodiment, the multiplying circuit 54 can be realized with a 
construction simpler than that of the multiplying circuit 54 indicated in 
FIG. 7. 
FIG. 10 illustrates still another embodiment of this invention. The 
difference of between the embodiment indicated in FIG. 10 from that 
indicated in FIG. 1 consists in that the horizontal synchronization signal 
is used only once within one field. Apart therefrom, the pulse H having 
the same period as the horizontal synchronization signal is generated by 
counting the clock signal C. 
In FIG. 10, reference numeral 61 indicates an extracting circuit taking out 
one of horizontal synchronization signals separated in the synchronization 
pulse separating circuit 51 by using the pulse V, which is in synchronism 
with the vertical synchronization signal. The counter 62 is started by the 
horizontal synchronization signal taken out by the extracting circuit 61. 
The counter 62 counts the clock signal C and generates one pulse H for 
every period of the horizontal synchronization signal to supply the pulse 
H to the line address counter 7 and the row address counter 8. 
The clock signal C is generated by the multiplying circuit 54 and the 
waveforming circuit 60 on the basis of the horizontal synchronization 
signal separated by the synchronization pulse separating circuit 57. 
The advantage of this embodiment consists in that it is not influenced by 
jitter in the horizontal synchronization signal. For example, in the case 
where a clock signal C supplied by another system is used, the delay time 
in the waveforming circuit cannot be specified. From this point of view 
this embodiment is advantageous. 
In the above embodiments examples in which the correcting data in the 
243-th or 256-th line are used as the last line for the convergence 
correcting data inputted in the memory at the adjustment are shown. 
However, these are not necessary conditions. Rather this invention can be 
applied to any system, in which the number of scanning lines differs 
therefrom, such as system television, SECAM system television, 
non-interlace double scanning line television, etc. 
The important point of this invention consists in that the correcting data 
corresponding to the position of the last scanning line stored at the 
adjustment are used repeatedly so that the data originally deficient are 
complemented. The stored correcting data are obtained by an operation 
based on the values at the intersections (X, Y) in the lattice and the 
region of the value of y can be arbitrarily set. 
Further, although, in the above explanation, the scanning lines and the 
lines in the memory correspond to each other, it is a matter of course 
that the scanning lines may correspond to the rows therein. In addition, 
although the vertical blanking pulse was used in the above as the reset 
pulse for the line address counter, this invention can be realized with a 
pulse synchronized in phase with the vertical synchronization pulse 
instead of the vertical blanking pulse. 
Furthermore, although there were shown in the above the embodiments in 
which this invention was applied to a color television, it is a matter of 
course that this invention can be applied to the digital convergence 
correcting device in a projection type color video projecting device.