Multi-ported memory cell

A multi-port semiconductor memory device is provided with current limiting transistor devices interposed between the memory cell and the bit line transfer gates for multiple bit line pairs. Where each bit line pair represents a memory port that is connected to the memory cell during read and write operations, the current limiting transistor devices effectively reduce the current flow from non-writing bit lines, thereby improving memory writability. In addition, the current limiting transistor devices effectively reduce the current flow to non-reading bit lines, thereby improving memory stability.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to the field of digital electronic circuits, specifically, semiconductor memory devices adapted for use with computer systems. In one aspect, the present invention relates to a semiconductor memory device which has a multi-port function.

2. Description of the Related Art

Generally, a multi-port memory is a memory device having a number of ports for reading and writing and corresponding address and control ports, such that multiple locations in the memory can be simultaneously accessed. A plurality of word lines and a plurality of bit lines are connected to each memory cell of the multi-port memory. Multi-port memories may be used in a variety of applications, such as a cache memory which functions as a memory common to the CPUs incorporated in a multi-CPU system, or as an image memory in which the same address must be accessed at the same time.

With multi-port memories, some ports are dedicated to reading or writing. Alternatively, some of the ports may be used for both reading and writing, though not simultaneously on the same read/write port. With multi-port memories, multiple read and write operations can be performed in a clock cycle. Indeed, a read/write port can be used for both reading and writing when one access is performed in the first half cycle and another access is performed in the second half cycle.

FIG. 1is a circuit diagram showing a conventional 3-port memory device. InFIG. 1, the first memory node1of a memory cell10, which comprises, for example, a static memory, is connected to a bit line BLa by a transfer gate14which is made of an MOS transistor. The gate of the transfer gate14is coupled to a word line WLa. The second memory node2of the memory cell10is connected to a bit line /BLa by a transfer gate12which is made of a MOS transistor. The gate of the transfer gate12is connected to a word line WLa. The first memory node1of the memory cell10is also connected to a bit line BLb by a transfer gate18which is made of a MOS transistor. The gate of the transfer gate18is coupled to a word line WLb. The second memory node2of the memory cell10is connected to a bit line /BLb by a transfer gate16which is made of a MOS transistor. The gate of the transfer gate16is coupled to a word line WLb. Further, the first memory node1of the memory cell10is connected to a bit line BLc by a transfer gate22which is made of a MOS transistor. The gate of the transfer gate22is coupled to a word line WLc. The second memory node2of the memory cell10is connected to a bit line /BLc by a transfer gate20which is made of a MOS transistor. The gate of the transfer gate20is coupled to a word line WLc. As shown, data read from the memory cell10may be output directly on a bit line (e.g., BLa), but the data in memory cell10may also be inverted by an inverter device (not drawn) before being connected to an output port by an access gate (e.g., transistor14).

Bit-line load circuits24,26,28are provided between the bit lines (e.g., load circuit24is coupled between bit line BLa and bit line /BLa) for maintaining the potentials of these bit lines at a power-supply potential. Each bit-line load circuit comprises two gate-coupled MOS transistors, each of which has its current path connected, at one end, to a power-supply VDD and, at the other end, to a bit line. Each bit-line load circuit is controlled by a control signal from a bit line control circuit40that is provided to the gates of the MOS transistors in the bit-line load circuits24,26,28.

The memory cell10stores data values opposite to each other. For example, the memory cell may be implemented as a pair of cross-coupled inverters connected in parallel between first and second memory nodes. Stored data values stored are transferred to the bit lines BLa and /BLa through the transfer gates14and12, in accordance with the potential of the word line WLa. The data values opposite to each other and stored in the memory cell10are also transferred to the bit lines BLb and /BLb through the transfer gates18and16, in accordance with the potential of the word line WLb. Further, the data values opposite to each other and stored in the memory cell10are also transferred to the bit lines BLc and /BLc through the transfer gates22and20, in accordance with the potential of the word line WLc.

Each port in the memory is identified with respect to the input/output bit line pairs that are used to transfer data into and out of the memory cell. For example, in the three-port memory configuration depicted inFIG. 1, the input/output path using the bit lines BLa and /BLa can be referred to as a first port, the input/output path using the bit lines BLb and /BLb can be referred to as a second port, and the input/output path using the bit lines BLc and /BLc can be referred to as a third port.

As the port number M increases for a multi-port memory, it becomes increasingly difficult to have both stability and writability for the multi-ported cell when non-writing wordlines are activated. For example, where cross-coupled inverters are used for the memory cell, the operation window gets very marginal with conventional three-port memory cells, and can disappear entirely with conventional four-port memory cells. This is because required beta-ratio (which is ratio of the memory cell latch size divided by the access pass-gate size) for cell stability virtually gets M times smaller when not writing.

The diminishing operation margin for cell stability is illustrated inFIGS. 2 and 3, which characterize the stability of the memory cell with the input/output characteristic curves for each inverter of a cross-coupled inverter memory cell in a 3-port memory (FIG. 2) and 4-port memory (FIG. 3). In accordance with conventional techniques for assessing the input/output characteristics of a memory cell,FIG. 2shows two inverter transfer curves for first and second memory cell inverters. Waveform50represents the transfer characteristic (during data reading) for a first inverter in the cross-coupled inverter memory cell (rotated 180 degrees about a diagonal axis) and waveform60represents the transfer characteristic for a second inverter in the cross-coupled inverter memory cell. The outer intersection points52,56represent stable points in the circuit operation, but point54represents a meta-stable point that is not really stable. As the spread62,64between the curves50,60increases, the stability of the memory device increases, but as the spread62,64decreases, the stability of the memory device decreases.

The stability essentially disappears for a 4-port memory, as illustrated inFIG. 3, which shows inverter transfer waveform70(rotated 180 degrees about a diagonal axis) for the first inverter in the cross-coupled inverter memory cell and waveform80for the second inverter in the cross-coupled inverter memory cell. As shown inFIG. 3, there is essentially no stability for the 4-port memory device because there is no spread between the waveforms.

Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.

SUMMARY OF THE INVENTION

In accordance with the present invention, normally-ON transistors are coupled between wordline pass-gates and the cell latch. By acting as a current limiter, these additional transistors act as current limiter to improve the beta-ratio and enhance operation margin for both cell stability and writability.

In accordance with another embodiment of the present invention, a multi-port semiconductor memory device is provided. The memory device includes a plurality of memory cells, each having a first and second memory node. In a selected embodiment, the memory cell is a pair of inverters cross-coupled in parallel between the first and second memory nodes. A current limiting device is coupled to each memory node. In a selected embodiment, each current limiting device is an MOS transistor or an insulated-gate transistor having a current path connected between a memory node and a transfer or access device. The gate of the current limiting device may be connected to a power supply voltage or otherwise controlled by a control signal to limit the amount of current that passes to and from the memory cell during data read and write operations. A plurality of transfer devices are coupled to each current limiting device. Each transfer device has a current path coupled between a bit line and the current limiting device to which it is coupled. With this coupling, data passes between the bit line and the memory node via the current limiting device under control of a word line signal that is applied to the transfer device. In a selected embodiment, each transfer device is a pair of insulated-gate transistors, each of which is coupled between a current limiting device and a bit line under control of a word line signal. Each transfer device may also include a second, third and fourth pair of insulated-gate transistors, each of which is connected between a current limiting device and a bit line. Additional pairs of insulated-gate transistors may also be included in the transfer device for transferring the stored data values from the memory cell to multiple bit line pairs (or in the reverse direction) in accordance with the additional word line signals.

DETAILED DESCRIPTION

In addition to providing a memory design that is stable (in terms of retaining the data content stored in the memory cell), there is a competing and potentially conflicting need for writability that must be balanced in the memory design. For example, memory stability is promoted by having smaller transfer or access gate sizes and larger NMOS gate sizes in the memory cell inverters. The ratio of these sizes is referred to as the beta-ratio, which is bigger for more stable memory designs, meaning that the NMOS driver gate in the memory cell inverters is larger and the transfer gate is smaller. However, with multi-port memories, the effective increase in the transfer gate size (because of the additional transfer gates for the additional ports) reduces the beta-ratio, meaning that the cell stability is diminished. Thus, to obtain stable memory cell operation, there is minimum beta-ratio value required for memory cell stability.

At the same time, cell writability is improved with weaker NMOS driver gates and larger transfer gates. In other words, writability is improved with a smaller beta-ratio. This is shown by an analysis of the input/output characteristic curves depicted inFIG. 4which uses the waveforms for each inverter of a cross-coupled inverter memory cell when performing write operations to the memory cell to characterize the writability of the memory cell. As depicted, waveform90represents the transfer characteristic (during data writing) for a first inverter in the cross-coupled inverter memory cell (rotated 180 degrees about a diagonal axis) and waveform92represents the transfer characteristic for a second inverter in the cross-coupled inverter memory cell. With memory devices, there should by only one intersection point between the two waveforms, which is a stable point94(in other words, this is the write converging point) for write operations.

The smaller the beta-ratio, the greater the spread98between waveforms90,92. Conversely, as the beta-ratio increases, there is less separation between waveforms90,92. If the spread98reduces sufficiently or disappears, then there will be multiple intersection points between waveforms90,92, resulting in multiple stability points. Thus, if the beta-ratio is too large, the spread98between the inverter curves90,92decreases so that there are multiple stability points for the inverters during writing, which is not desirable. Thus, there is maximum beta-ratio value required for memory cell writability.

Where multiple bit line pairs are connected to a memory cell in addition to the bit line pair that is reading or writing to the cell (such as when precharged bit lines are coupled to the memory cell in addition to the data-charged bit line pair that is reading or writing to the cell), excessive current flow from the bit lines impedes the memory cell performance. For example, during write operations, the activated transfer gates for the non-writing bit lines impede discharge of the bit line that is being used to write to the memory cell. As a result, as more ports and transfer gates are added, the minimum beta-ratio value required for stable read operations increases, and at the same time, the maximum beta-ratio value required for acceptable writability decreases.

In accordance with the present invention, current flow to the memory cell is limited by current limiting devices positioned between the memory cell and the transfer gates that are used for writing to the memory cell. By including a current limiting device at each memory cell node, the operational window between the minimum and maximum beta-ratio values is effectively increased.

FIG. 5shows a circuit diagram of a multi-ported memory configuration in accordance with the present invention implemented in a 3-port memory. A memory cell100, for example, a static memory, comprises, for example, a pair of cross coupled inverters104,102connected in parallel between two memory latch nodes106,108. With such memory cell configurations, when the word line (e.g., word line140) for a particular port (e.g., the input/output path using the bit lines134and135) is activated to write to the memory cell100, the non-writing wordlines (e.g., word lines142,144) can also be activated, in which case the bits lines for the second port (e.g., the input/output path using the bit lines132and133) and third port (e.g., the input/output path using the bit lines130and131) are precharged. (As will be appreciated, multiple bit lines and wordlines are shown in the figures as dual lines that are bundled together in the end, even though they are not electrically tied together.)

To improve the stability and writability of such memory cell configurations, the first memory latch node106is connected to the first memory node110by a first current limiting transistor120, which as depicted inFIG. 5is an MOS transistor with its gate connected to a reference or power supply voltage to turn the transistor120“on.” In similar fashion, second memory latch node108is connected to the second memory node112by a second current limiting transistor122, which as depicted inFIG. 5is an MOS transistor with its gate connected to a reference or power supply voltage to turn the transistor122“on.” Through the current limiting transistors120,122, data stored in the memory cell100is connected to the bit lines130–135by transfer or pass gates124–129.

In particular, opposing data values are stored in a memory cell100. One of the data values stored in the memory cell100is output to bit line134via a first current limiting transistor120and a transfer gate128in accordance with the potential of a word line140. The inverted data value stored in the memory cell100is output to a bit line135through second current limiting transistor122and a transfer gate129in accordance with the potential of a word line140. In accordance with the potential of a word line142, the data stored in the memory cell100is output to a bit line132through first current limiting transistor120and a transfer gate126in accordance with the potential of a word line142, and the data inverted with respect to this data is transferred from the memory cell100to a bit line133through second current limiting transistor122and a transfer gate127. Finally, in accordance with the potential of a word line144, the data stored in the memory cell100is output to a bit line130through first current limiting transistor120and a transfer gate124in accordance with the potential of a word line144and the data inverted with respect to this data is transferred from the memory cell100to a bit line131through second current limiting transistor122and a transfer gate125.

In the embodiment of the present invention where the gates of the current limiting transistors are connected to a reference or power supply voltage, the current limiting transistors act as currently limiters during the multi-port read and write operations to the memory cell100. By providing normally-ON transistors120,122, the memory cell current is limited to the current flow permitted by the activated transistors120,122, thereby improving the beta-ratio by making it more consistent and enhancing the operation margin for both cell stability and writability.

In accordance with an alternate embodiment, the gates of the current limiting transistors120,122may be selectively activated under control of gate control signals. By turning current limiting transistors120,122off when read or write operations to the memory cell100are not required, improved isolation of the memory cell100is provided.

In connection with the bit line precharging described above, the circuit configuration depicted inFIG. 5depicts a bit-line load circuit180for holding the potentials of the bit lines that are not used for writing data at power-supply potential VDD. As described more fully in U.S. Pat. No. 5,287,323 (which is hereby incorporated by reference as if fully set forth herein), the bit-line load circuit includes, for each bit line pair, a pair of gate coupled MOS transistor, each of which has its current paths connected, at one end, to the bit lines and, at the other end, to the power-supply potential VDD. Under control of a write-enable and/or read-enable signal and/or address signal, the commonly coupled gates of the MOS transistor pair is activated to pull the bit lines to the power supply voltage.

FIG. 6shows a circuit diagram of a multi-ported memory configuration in accordance with the present invention implemented in a 4-port memory. A memory cell200is provided consisting of a pair of cross coupled inverters204,202connected in parallel between two memory nodes206,208.

With such memory cell configurations, when the word line (e.g., word line240) for a first port (e.g., the input/output path using the bit lines236and237) is activated to read or write to the memory cell200, the non-writing/reading wordlines (e.g., word lines242,244,246) can also be activated, in which case the bits lines for the second port (e.g., the input/output path using the bit lines234and235), third port (e.g., the input/output path using the bit lines232and233) and fourth port (e.g., the input/output path using the bit lines230and231) are precharged.

To mitigate the effects of the additional current from the other connected ports, a pair of normally-ON transistors are inserted between wordline pass gates and the memory cell. These additional transistors act as current limiters to enhance the beta-ratio operating margins, thereby improving both cell stability and writability. In particular, the first memory latch node206is connected to the first memory node210by a first current limiting transistor220, which as depicted inFIG. 6is an MOS transistor with its gate connected to a reference or power supply voltage to turn the transistor220“on.” In similar fashion, second memory latch node208is connected to the second memory node212by a second current limiting transistor222, which as depicted inFIG. 6is an MOS transistor with its gate connected to a reference or power supply voltage to turn the transistor222“on.” Through the current limiting transistors220,222, data stored in the memory cell200is connected to the bit lines230–237by transfer or pass gates254–261.

As described herein, the gates of the current limiting transistors220,222may be selectively activated under control of gate control signals221,223. In this way, the current limiting function can be selectively controlled. It will be appreciated that the current limiting control function can be implemented in any of the multi-port embodiments of the present invention, regardless of the number of ports.

In particular, opposing data values are stored in a memory cell200. One of the data values stored in the memory cell200is output to bit line236via a first current limiting transistor220and a transfer gate260in accordance with the potential of a word line240. The inverted data value stored in the memory cell200is output to a bit line237through second current limiting transistor222and a transfer gate261in accordance with the potential of a word line240. In accordance with the potential of a word line242, the data stored in the memory cell200is output to a bit line234through first current limiting transistor220and a transfer gate258, and the data inverted with respect to this data is transferred from the memory cell200to a bit line235through second current limiting transistor222and a transfer gate259. In accordance with the potential of a word line244, the data stored in the memory cell200is output to a bit line232through first current limiting transistor220and a transfer gate256, and the data inverted with respect to this data is transferred from the memory cell200to a bit line233through second current limiting transistor222and a transfer gate257. Finally, in accordance with the potential of a word line246, the data stored in the memory cell200is output to a bit line230through first current limiting transistor220and a transfer gate254, and the data inverted with respect to this data is transferred from the memory cell200to a bit line231through second current limiting transistor222and a transfer gate255.

FIGS. 7aand7bare charts illustrating the stability and writability a multi-ported memory configuration in accordance with the present invention. The inverter waveforms shown inFIG. 7aprovide a representative characterization of the memory cell stability for a multi-port memory device according to the present invention, while the waveforms shown inFIG. 7bprovide a representative characterization of the memory cell writability for a multi-port memory device according to the present invention. The depicted waveforms are provided for illustrative purposes, and are not intended to provide a quantitatively precise representation of the operation of the multi-port memory of the present invention.

As shown inFIG. 7a, the waveform270represents the response curve for a first memory cell inverter (e.g., inverter104inFIG. 5) in a multi-port memory of the present invention, where the voltage readings are taken between an A node (node106) and a B node (node108). Waveform272represents the response curve for a second memory cell inverter (e.g., inverter102inFIG. 5) as rotated about a diagonal axis in a multi-port memory of the present invention, where the voltage readings are taken between an X node (node106) and a Y node (node108). The response curves shown inFIG. 7ashow a stable memory with two stable points271,273, and with good spread275,276between the curves270,272. As a result, even if there is some shift in the waveforms due to process variation or noise etc., there is plenty of margin in the design to maintain stable memory circuit operation.

FIG. 7bshows that the memory circuit design of the present invention also has good writability. In particular the figure represents a case for writing “0” to node106(and thus writing “1” to node108). The waveform280represents the response curve for a first memory cell inverter (e.g., inverter104inFIG. 5) in a multi-port memory of the present invention, where the voltage readings are taken between an A node (node106) and a B node (node108). Waveform282represents the response curve for a second memory cell inverter (e.g., inverter102inFIG. 5) as rotated about a diagonal axis in a multi-port memory of the present invention, where the voltage readings are taken between an X node (node106) and a Y node (node108). The response curves shown inFIG. 7bdepict a memory with good writability, having a single stable point281, which represents node108having a voltage of “1” and node106having a voltage of “0.” In addition, the spread285between the curves280,282promotes writability of the multi-port memory.

As has been described in detail, the semiconductor memory device according to this invention, which is of multi-port type, can perform data-writing and data-reading with improved reliability and stability and at high speed and can, therefore, be greatly useful as a cache memory, an image memory, or the like. The first and second embodiments, described above, are a 3-port memory and a 4-port memory, respectively. Nonetheless, the number of ports is not limited to these, and the present invention can be applied to a memory having multiple ports. The more ports a multi-port memory has, the more difficult it is to have circuit stability and acceptable operational margin. In view of this, the present invention, if used, is advantageous.

While the system and method of the present invention has been described in connection with the preferred embodiment, it is not intended to limit the invention to the particular form set forth, but on the contrary, is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims so that those skilled in the art should understand that they can make various changes, substitutions and alterations without departing from the spirit and scope of the invention in its broadest form.