Metal and via definition scheme

A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer.

BACKGROUND

DETAILED DESCRIPTION

ICs are commonly formed by a sequence of material layers, some of which are patterned by a photolithography process. It is important that the patterned layers properly align or overlay with adjacent layers. Proper alignment and overlay becomes more difficult in light of the decreasing geometry sizes of modern ICs. In addition, the surface topography of an underlying substrate, such as a semiconductor wafer, impacts the lithography imaging quality and further degrades the overlay tolerance between adjacent material layers. Furthermore, lithography processes are a significant contributor to the overall cost of manufacturing, including processing time and the cost of masks (also referred to as photomasks) used in the process. In some fabrication process, two different masks are used to define metal lines and vias with two separate exposure processes. More efficient and cost effective methods to define the metal layer and via layer are desirable.

FIG. 1Ais a top view of an exemplary integrated circuit of the metal and via definition scheme at a metal pattern definition stage according to some embodiments. InFIG. 1A, a dielectric layer108and a photoresist layer110for defining metal pattern are shown.

The space between the photoresist layer110strips has a width w1 in an opening113that would not have a via directly underneath and a maximum width w2 in an opening111that would have a via to be formed directly underneath. The w1 ranges from about 40 nm to about 50 nm and the w2 ranges from about 60 nm to about 70 nm in some embodiments. The w2 is greater than the w1 from about 10% to about 50% in some embodiments. The opening111directly above the via to be formed with the maximum width w2 has a curved shape, such as a part of an oval or circular shape in some embodiments. However, other profile shapes are possible.

FIG. 1Bis a cross section of the exemplary integrated circuit structure inFIG. 1Aaccording to some embodiments.FIG. 1Billustrates the cross section along the cutline A-A′ inFIG. 1A. InFIG. 1B, a substrate102, dielectric layers104and108, an etch stop layer106, and a photoresist layer110for defining metal pattern are shown.

The substrate102comprises silicon, silicon dioxide, aluminum oxide, sapphire, germanium, gallium arsenide (GaAs), an alloy of silicon and germanium, indium phosphide (InP), silicon on insulator (SOI), or any other suitable material in some embodiments. The substrate102may also be made of or include some other suitable elementary semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Alternatively, the substrate102may include a non-semiconductor material such as a glass substrate for thin-film-transistor liquid crystal display (TFT-LCD) devices, or fused quartz or calcium fluoride for a photomask (mask).

In some embodiments, the substrate102includes one or more material layers (e.g., insulating, conductive, semi-conductive, etc.) formed thereon. The substrate102may include various doped regions, dielectric features, and multilevel interconnects. The substrate102may further include additional features or layers with various devices and functional features. Active and passive devices, such as transistors, capacitors, resistors, and the like, may be formed on the substrate102. In some embodiments, the substrate102includes various doped features for various microelectronic components, such as a complementary metal-oxide-semiconductor field-effect transistor (CMOSFET), an imaging sensor, and a memory cell.

The dielectric layers104and108may comprise low-k dielectric material, SiO2, or other dielectric material. In some embodiments, each of the dielectric layers104and108has a thickness ranging from about 30 nm to about 100 nm. In some embodiments, low-k dielectric material (dielectric) has a dielectric constant less than about 3.5. In some embodiments, low-k dielectrics may also include a class of dielectrics referred to as extremely low-k (ELK) dielectrics, which have a dielectric constant less than about 2.5. For example, the extremely low-k dielectrics may be used as interlayer dielectrics (ILDs) for sub-micron technology (e.g., for 65 nm node, 45 nm node, or beyond technology). In addition, the extremely low-k dielectrics may be porous. In some embodiments, low-k dielectrics include oxygen, silicon, nitrogen, and the like. The exemplary ELK materials include carbon-containing materials, organo-silicate glass, porogen-containing materials, and the like. The dielectric layers104and108including low-k dielectrics may be deposited using spin-on or a CVD method such as Plasma Enhanced CVD (PECVD), Low Pressure CVD (LPCVD), or Atomic Layer CVD (ALCVD).

The etch stop layer106comprises tetraethyl orthosilicate (TEOS), SiO, SiC, SiN, SiOC, SiON, SiCN, AlOXNY, or any other suitable material in some embodiments. The etch stop layer106has a thickness ranging from about 2 nm to about 10 nm in some embodiments. The etch stop layer106can be formed over the dielectric layer104by PECVD or a physical vapor deposition (PVD) in some embodiments.

The photoresist layer110is defined (patterned) by a photolithography exposure using a mask. The photoresist layer110has a thickness ranging from about 70 nm to about 100 nm in some embodiments. In some embodiments, the opening113has an aspect ratio (i.e., height/width) ranging from about 1.4 to about 2.5 and the opening111has an aspect ratio ranging from about 1 to about 1.6. However, the aspect ratio of the openings113and111could be higher or lower in some embodiments.

FIG. 2Ais the top view andFIG. 2Bis the cross section of the exemplary integrated circuit structure inFIGS. 1A and 1Bafter a spacer layer112is deposited according to some embodiments. The spacer layer112is made of dielectric material, such as SiN. Also, any other suitable material can be used. The spacer layer112, such as SiN, has a thickness ranging from about 20 nm to about 30 nm in some embodiments. The spacer layer112has a different etching characteristics from dielectric layer108and the etch stop layer106, thus enabling a selective etching in some embodiments.

The spacer layer112is deposited by atomic layer deposition (ALD), CVD, or PECVD in some embodiments. The shape of the spacer layer112is generally conformal to the photoresist layer110and capable of gap filling the opening113in some embodiments. The spacer layer112is a dummy layer and would be removed later. The spacer layer112has a width w4 on the sidewall and a thickness t1 on the bottom of the opening114that range from about 20 nm to about 30 nm. The opening113is filled (or sealed) by the spacer layer112. On the other hand, the opening111is partially filled to form a new opening114below the top surface of the photoresist110. The opening114with a width w3 is formed on the top of the planned via area (e.g. the via hole120inFIG. 7). The opening114results from the photoresist layer110spacing of w2 that is greater than w1 by about 10%-about 50% in some embodiments.

FIG. 3Ais the top view andFIG. 3Bis the cross section of the exemplary integrated circuit structure inFIGS. 2A and 2Bafter the spacer layer112is etched to form the opening116with a spacing width w5 from the previous opening114. The opening116is between the photoresist110strips and exposes the top surface of the dielectric layer108. The width w5 is substantially close to the via width to be formed in the via hole120inFIG. 7according to some embodiments.

A wet etching process is used for this operation in some embodiments. For example, the spacer layer112can be etched by hot H3PO4solution (with the temperature ranging from about 80° C. to about 200° C.) from the top of the planned via region and extend into the opening114to reach the top surface of the dielectric layer108inFIG. 2Bto closely match the planned via width. In one example, for a H3PO4solution with about 85% concentration at about 165° C., the SiN etching rate is about 3 nm/min, and the etching depth can be controlled by etching time. The width w5 ranges from about 30 nm to about 50 nm in some embodiments. This operation is optional since the width w3 of the opening114inFIG. 2Bcould be suitable for the planned via width in some other embodiments.

FIG. 4Ais the top view andFIG. 4Bis the cross section of the exemplary integrated circuit structure inFIGS. 3A and 3Bafter the dielectric layer108is etched to form the opening118that has a width w5′ that matches the via width to be formed in the via hole120as shown inFIG. 7according to some embodiments. The spacer layer112has a different etching selectivity from the dielectric layer108, and functions as a self-aligning mask. The width w5′ may be slightly different from the width w5 inFIG. 3Bdue to the additional etching. A dry etching process or any other suitable etching method is used for this step in some embodiments. For example, dry etching (plasma etching) using C2F6, CF4, and/or oxygen as etchants can be performed to etch the dielectric layer108. The dry etching stops at the etch stop layer106.

The etch stop layer106can be etched by dry etching (plasma etching) using CxFy, N2, and/or O2as etchants. Other suitable etching process can be used. In some embodiments, the dielectric layer108and the etch stop layer106are etched in one operation. Afterwards, the spacer layer112is removed.

FIG. 5Ais the top view andFIG. 5Bis the cross section of the exemplary integrated circuit structure inFIGS. 4A and 4Bafter the spacer layer112is removed according to some embodiments. A wet etching process is used for this operation in some embodiments, but dry etching can be used in other embodiments. For example, the spacer layer112can be removed by a hot H3PO4solution with the temperature ranging from about 80° C. to about 200° C. Afterwards, the dielectric layers104and108are etched to form the metal trench122and the via hole120inFIGS. 6A and 6B.

FIG. 6Ais the top view andFIG. 6Bis the cross section of the exemplary integrated circuit structure inFIGS. 5A and 5Bafter the dielectric layers104and108are etched to form the metal trench122and the via hole120according to some embodiments. A dry etching process or any other suitable etching method can be used for this operation. For example, dry etching (plasma etching) using C2F6, CF4, and/or oxygen as etchants can be performed to etch the dielectric layers104and108. Any other suitable etching process can be also used.

As described above, the via hole120can be defined by the use of the photoresist layer110using the metal trench pattern. This mechanism completes the metal and via definition by the same mask with a photolithography exposure of the photoresist layer110and using the spacer layer112, compared to two exposures for a conventional dual damascene process. Two mask patterns used for the conventional process for forming metal lines and vias can be reduced to one mask to reduce costs. Using multiple masks incurs overlay errors and increase patterning variations. Reducing the patterning masks to one reduces overlay errors and improves patterning accuracy. Also, the process is simpler and more suited for manufacturing with reduced complexity.

FIG. 7is the cross section of the exemplary integrated circuit structure inFIGS. 6A and 6Bafter the photoresist layer110is removed according to some embodiments. The photoresist layer110can be removed by any one of a dry etching process, such as plasma ashing (O2ash process), or other suitable methods.

FIG. 8is the cross section of the integrated circuit structure inFIG. 7after a barrier layer124and a gap filling metal layer126are formed. In some embodiments, copper (Cu) is used as the conductive material to fill the trench121and122and the via hole120. In some embodiments, the barrier layer124, such as Ta, TaN, TiN, or any combination thereof, is formed on the trench121and122and the via hole120before filling in the trenches with the conductive material. The barrier layer124is deposited by a proper technique, such as ALD, PVD, or CVD. The barrier layer124may function as a diffusion barrier and adhesive layer for integrity of the interconnect structure.

Afterwards, the metal trench121and122, and the via hole120are filled with metal, such as Cu, to form metal lines and a via, respectively. For example, Cu can be deposited using an electrochemical plating process. In some embodiments, a Cu seed layer is formed by PVD with a thickness ranging from about 2 nm to about 10 nm in the metal trench122and the via hole120prior to filling the metal trench122and the via hole120. In some embodiments, a planarizing process such as a chemical mechanical polishing is performed after filling the metal trench122and the via hole120to remove excess conductive materials (e.g., a top part of the metal filled over the metal trenches121and122).

By using the mechanism described above, a via of an interconnect structure can be defined by the use of a spacer layer according to the overlying metal trench pattern. This mechanism completes the via definition by a photolithography exposure of the photoresist using the mask of the metal trench pattern, and narrowing of the width of the opening of the metal trench pattern using the spacer layer. In comparison, a conventional dual damascene process requires two photomasks. Thus, two mask patterns used for the conventional process can be reduced to one mask, which reduces cost, overlay errors, and process complexity.

According to some embodiments, a method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer.

According to some embodiments, a method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is deposited over the photoresist layer and the first dielectric layer. The spacer layer is etched to form a first opening with the via width wherein the first opening is disposed directly above a via location. The first dielectric layer is etched to form a second opening with a width matching the via width at the via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer.

According to some embodiments, a method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer. The etch stop layer is disposed over a second dielectric layer. The first dielectric layer and the second dielectric layer comprise SiO2 or low-k dielectric material. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has a first opening that has a via width. The first opening is disposed directly above a via location. The spacer layer comprises SiN. The first dielectric layer is etched to form a second opening matching the via width at the via location. The spacer layer is removed after etching the first dielectric layer. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer. The photoresist layer is removed.

The above method embodiment shows exemplary steps, but they are not necessarily required to be performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiment of the disclosure. Embodiments that combine different claims and/or different embodiments are within the scope of the disclosure and will be apparent to those skilled in the art after reviewing this disclosure.