Nonvolatile memory device having self reprogramming function

A nonvolatile memory device having a self reprogramming function is provided. The nonvolatile memory device includes a memory cell, a first transistor, a second transistor, and a latch circuit. The memory cell is for data storage. The first transistor receives a reading control signal at a gate. And a first source/drain is electrically coupled to the memory cell. The second transistor receives a reset control signal at a gate. A source/drain is electrically coupled to a second source/drain of the first transistor, and a second source/drain of the second transistor is grounded. In addition, the electrical characteristics of the second transistor are opposite to that of the first transistor. The latch circuit includes a latch input terminal and a latch output terminal. In which, the latch input terminal is electrically coupled to the second source/drain of the first transistor and the first source/drain of the second transistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile memory, and more particularly, to a nonvolatile memory having a reprogramming function.

2. Description of the Related Art

FIG. 1schematically shows a flow chart illustrating a conventional method for fabricating a nonvolatile memory. Referring toFIG. 1, a plurality of steps are required for fabricating a nonvolatile memory. First, in step S101, the fabrication process is performed. Then, in step S103, a test process is performed on the nonvolatile memory. When the test result is indicated that the nonvolatile memory is good (i.e. “good” as indicated in step S103), a packaging process is performed in step S11. Otherwise, if it is found that a defect exists in the nonvolatile memory during the fabrication process of S101(i.e. “fail” as indicated in step S103), an E-fuse technique is performed to repair the nonvolatile memory during step S105. In step S107, the fabrication process is performed. Then in step S109, the testing process is performed on the repaired nonvolatile memory. If the repaired nonvolatile memory is made to be a good product (i.e. “good” as indicated in step S109), the packaging process is performed in step S111. However, if there is still some defects in the repaired nonvolatile memory (i.e. “fail” as indicated in step S103), the nonvolatile memory is scrapped.

Referring toFIG. 1, after the packaging process is completed on the nonvolatile memory, a program code is recorded into the memory in step S113, and a final testing is performed in step S115. Then, in step S117, it is determined whether the memory has passed the final testing of step S115. If the memory has passed the final testing in step S115(i.e. “yes” as indicated in step S117), a final testing is directly performed on the memory in step S121. Otherwise, if the memory does not pass the final testing in step S115(i.e. “no” as indicated in step S117), the E-fuse technique is performed to repair the nonvolatile memory in step S119. Then the final testing is performed again on the memory in step S121. Afterwards, in step S123, it is determined whether the memory has passed the final testing in step S121. If the memory does not pass the final testing in step S121(i.e. “no” as indicated in step S123), the memory is scrapped. Otherwise, if the memory has passed the final test of step S121(i.e. “yes” as indicated in step S123), the memory is ready for shipment.

In general, the final testing in the steps S115or S121mentioned above may include a temperature test, that is to test the operation of the memory under different temperature environments. In such cases, various thermal intensities having different temperatures are applied on the memory. However, the charges inside the memory are easily lost under exposure to elevated temperatures. And the program code could be messed up if the memory is used for an extended period of time under such elevated temperature conditions. Accordingly, a nonvolatile memory having a self-refreshing function is disclosed in U.S. Pat. No. 5,347,486.

The technique disclosed in U.S. Pat. No. 5,347,486 is suitable for larger capacity memory devices. Since its circuit structure is more complicated, it is not as suitable for application in the smaller sized circuit. However, micro circuit is widely used in different applications such as the RFID (radio frequency identification) circuit where the memory device disclosed in U.S. Pat. No. 5,347,486 is not as suitable.

SUMMARY OF THE INVENTION

Therefore, it is an object of the present invention to provide a nonvolatile memory having a self reprogramming function. The nonvolatile memory is able to resolve the problem of data losses in the memory under high temperature testing, and also is suitable for the application in micro circuit.

The present invention provides a nonvolatile memory having a self reprogramming function. The nonvolatile memory includes a memory cell for storing data, a sense amplifier, a writing amplifier, and a latch circuit. The sense amplifier is used for reading the state of the memory cell in response to a reading control signal, and to output the read state to the latch circuit. The writing amplifier is to determine whether to program the memory cell in response to a writing control signal. In addition, the latch circuit has a latch input terminal and a latch output terminal. Furthermore, the latch input terminal is electrically coupled to the sense amplifier and the writing amplifier.

In an embodiment of the present invention, the sense amplifier includes a first PMOS transistor and a first NMOS transistor. In which, a reading control signal is received by a gate of the first PMOS transistor. And a first source/drain and a second source/drain of the first PMOS transistor are electrically coupled to the memory cell and to the latch input terminal of the latch circuit, respectively. In addition, a reset control signal is received by a gate of the first NMOS transistor. A first source/drain of the first NMOS transistor is electrically coupled to the second source/drain of the first PMOS transistor. In addition, a second source/drain of the first NMOS transistor is grounded.

Moreover, the sense amplifier further includes a second NMOS transistor. In which, a loading control signal is received by a gate of the second NMOS transistor, a first source/drain of the second NMOS transistor is electrically coupled to the latch input terminal of the latch circuit, and a writing data is received by a second source/drain of the second NMOS transistor.

Furthermore, the latch circuit includes a first inverter and a second inverter. In which, an input terminal and an output terminal of the first inverter are electrically coupled to the latch input terminal and the latch output terminal of the latch circuit, respectively. An input terminal and an output terminal of the second inverter are electrically coupled to the output terminal and the input terminal of the first inverter, respectively.

In an embodiment of the present invention, the writing amplifier includes a third NMOS transistor and a fourth NMOS transistor. In which, a writing control signal is received by a gate of the third NMOS transistor, a first source/drain of the third NMOS transistor is electrically coupled to the memory cell, and a second source/drain of the third NMOS transistor is electrically coupled to a first source/drain of the fourth NMOS transistor. In addition, a gate of the fourth NMOS transistor is electrically coupled to the latch input terminal of the latch circuit. In addition, the first source/drain and a second source/drain of the fourth NMOS transistor are electrically coupled to the second source/drain of the third NMOS transistor and are grounded, respectively.

When the testing process is performed on the nonvolatile memory provided by the present invention under the elevated temperature conditions, the state of the memory cell is latched in the latch circuit by enabling the reading control signal. After the testing process performed on the memory is completed, the writing amplifier determines whether to program the memory cell according to the state latched in the latch circuit. Accordingly, the present invention is able to avoid the data loss under the high temperature testing conditions. Moreover, since each memory cell in the present invention is disposed with a latch circuit, the present invention is able to provide the self-reprogramming function without using complicated circuit structure. As a result, the present invention is suitable for application in the smaller sized circuit.

DESCRIPTION OF THE EMBODIMENTS

Reference shall now be made in detail to the present embodiments of the invention, in which examples are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and in the description to refer to the same or like parts. In addition, the types of the transistor described hereinafter such as the NMOS transistor, the PMOS transistor, and the PMOS memory device are all embodiments of the present invention. However, other types of transistors or memory devices can also be used by one of ordinary skills in the art according to the actual physical requirements without departing from the main spirit of the invention.

FIG. 2is a block diagram of a configuration of a nonvolatile memory having a self-reprogramming function, according to an embodiment of the present invention. Referring toFIG. 2, the memory circuit200provided by the present invention at least includes a memory cell210. In addition, the memory cell210is electrically coupled to a sense amplifier220and a writing amplifier230. The sense amplifier220is electrically coupled to the latch circuit240via a latch input terminal Q, and the latch circuit240is electrically coupled to the writing amplifier230via the latch input terminal Q.

In other embodiments of the present invention, the sense amplifier200further includes a loading switch260. In which, a writing data WR_data is transmitted by the loading switch260to the latch input terminal of the latch circuit240in response to a loading control signal LD.

FIG. 3is a circuit diagram of a nonvolatile memory having a self-reprogramming function according to an embodiment of the present invention. Referring toFIG. 3, the memory cell210further includes a PMOS memory device216. In which, a first gate of the PMOS memory device216is electrically coupled to a word line212, a first source/drain of the PMOS memory device216is electrically coupled to a bit line214and a DC bias VDD, and a second source/drain of the PMOS memory device216is electrically coupled to the sense amplifier220. In addition, the threshold voltage of the PMOS memory device216is determined by applying the high voltage/current to write into the electric charge.

In the present embodiment, the sense amplifier220mainly includes a PMOS transistor222and an NMOS transistor224. In which, a first source/drain of the PMOS transistor222is electrically coupled to the memory cell210, a reading control signal RDB is received by a gate of the PMOS transistor222, and a second source/drain of the PMOS transistor222is electrically coupled to the NMOS transistor224and the latch input terminal Q of the latch circuit240. A reset control signal RE is received by a gate of the NMOS transistor224, a first source/drain of the NMOS transistor224is electrically coupled to the second source/drain of the PMOS transistor222, and a second source/drain of the NMOS transistor224is grounded.

Referring toFIG. 3, the writing amplifier230further includes the NMOS transistors226and228. In which, a writing control signal WR is received by a gate of the NMOS transistor226, and a first source/drain and a second source/drain of the NMOS transistor226are electrically coupled to the first source/drain of the PMOS transistor222and to a first source/drain of the NMOS transistor228, respectively. In addition, the first source/drain and a gate of the NMOS transistor228are electrically coupled to the second source/drain of the NMOS transistor226and to the latch input terminal Q of the latch circuit240, respectively. And a second source/drain of the NMOS transistor228is grounded.

Moreover, in the present embodiment, the latch circuit240may be embodied by using two inverters. The output terminals of the two inverters are electrically coupled to their respective input terminals. In the present embodiment, the latch circuit240includes an inverter242. In which, an input terminal and an output terminal of the inverter242are electrically coupled to the latch input terminal Q and to a latch output terminal QB of the latch circuit240, respectively.

Furthermore, the latch circuit240further includes a PMOS transistor244and an NMOS transistor246. In which, a first source/drain of the PMOS transistor244is electrically coupled to a DC bias, a gate of the PMOS transistor244is electrically coupled to the output terminal of the inverter242, and a second source/drain of the PMOS transistor244is electrically coupled to a first source/drain of the NMOS transistor246. In addition, a gate of the NMOS transistor246is electrically coupled to the output terminal of the inverter242. And a second source/drain of the NMOS transistor246is grounded.

In the present embodiment, the loading switch260includes an NMOS transistor262. In which, a first source/drain of the NMOS transistor262is electrically coupled to the latch input terminal Q, a loading control signal LD is received by a gate of the NMOS transistor262, and the writing data WR_data is received by a second source/drain of the NMOS transistor262.

FIG. 4is a timing diagram of the control signals inFIG. 2, according to an embodiment of the present invention. Referring toFIGS. 2,3, and4, it is assumed that when a final testing, such as the high temperature test, is performed on the memory200of the present invention, a pulse of the reset control signal RE is generated at the time point t1, which turns on the NMOS transistor224. Meanwhile, the latch input terminal Q of the latch circuit240is pulled down to a ground level.

Then, at the time point t2, the reset control signal RE is disabled. Furthermore, the reading control signal RDB is transited from the high potential to the low potential, which turns off the NMOS transistor224and turns on the PMOS transistor222. As a result, the state of the memory cell210is latched on the latch input terminal Q of the latch circuit240.

Then, at the time point t4, the reset control signal RDB is transited from the low potential to the high potential, which turns off the PMOS transistor222again. Meanwhile, the data stored in the memory cell210had been latched on the output terminal QB of the latch circuit240.

In addition, since the gate of the NMOS transistor228is electrically coupled to the latch input terminal Q of the latch circuit240, the NMOS transistor228is turned on when the latch input terminal Q is on the high potential, and the NMOS transistor228is turned off when the latch input terminal Q is on the low potential.

It is assumed that the memory200has passed the final testing before the time point t5, thus the writing control signal WR is enabled at the time point t5. Meanwhile, the NMOS transistor226is turned on. Here, whether the NMOS transistor228is turned on or off is determined by the voltage level on the latch input terminal Q. Assuming that the state of the memory cell210previously latched on the latch input terminal Q is on a programming state, which indicates the voltage level on the latch input terminal Q to be on a high level state, meanwhile, the NMOS transistor228is turned on and a programming current is generated to program the PMOS memory device216.

On the other hand, when the state of the memory cell210previously latched on the latch input terminal Q is in an erase state, which indicates the voltage level on the latch input terminal Q to be on a low level state, meanwhile, the NMOS transistor228is turned off and the programming current is not generated. In the aforementioned case, the memory cell210is maintained in the erase state.

FIG. 5is a timing diagram of the signals for programming the memory cell. Referring toFIGS. 3 and 5, the loading control signal LD is enabled first at the time point t6when it is desired to program the memory cell210, which turns on the NMOS transistor262.

Then, at the time point t7, the data is transmitted to the latch input terminal Q of the latch circuit240via the NMOS transistor262, such that the voltage level on the latch input terminal Q is pulled up to the high level state. Meanwhile, since the voltage level on the latch input terminal Q is at the high level state, the NMOS transistor228is turned on. Then at the time point t8, the writing control signal WR is enabled, which turns on the NMOS transistor226. In case the NMOS transistors226and228are both turned on, a programming current is generated by the writing amplifier230to program the memory cell210.

In summary, the present invention has at least the following advantages:

1. since the data stored in the memory cell in the latch circuit before the temperature test is able to be temporarily latched, the present invention is able to avoid the data losses during the high temperature test; and

2. since each memory cell is disposed with a latch circuit, the present invention is suitable for the smaller sized memory devices and for disposing in micro circuit.