Outer code protection for solid state memory devices

Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.

SUMMARY

Various embodiments of the present invention are generally directed to providing outer code word protection for solid state memory devices, such as non-volatile (NVM) memory devices. The outer code words provide protection for data blocks of memory device. In some configurations the memory device comprises a memory chip that includes multiple die. In some configurations, the memory device comprises multiple chips and each chip includes multiple die. The outer code words described herein may span multiple blocks, may span multiple die and/or may span multiple chips to providing data protection for blocks, die, and chips, respectively.

Some embodiments involve a solid state memory device that is arranged in multiple data blocks, each block comprising an array of memory cells arranged in a plurality of pages. Encoder circuitry is configured to encode data into inner code words and symbol-based outer code words. Modulator circuitry is configured to store the inner code words and the symbol-based outer code words in the memory cells of the multiple blocks. The modulator circuitry is configured to store one or more inner code words in each page of each block and to store one or more symbols of each outer code word in at least one page of each block.

For example, in some configurations, the modulator circuitry is configured to store only one outer code word symbol in one page of each of the multiple blocks. In some configurations, the symbols of the outer code word overlap the inner code words and the modulator circuitry is configured to store a plurality of outer code word symbols in one page of each of the multiple blocks.

The pages of each block may be arranged in multiple planes, with at least one symbol of each outer codeword stored in each page of the multiple planes. For example, in some configurations, the pages of each data block may be arranged in an even plane and an odd plane. The modulator circuitry is configured to store at least one symbol of each outer codeword in an even plane page of each block and at least one symbol of each outer codeword in an odd plane page of the block.

The encoder circuitry can be configured to encode the data into the outer code words using a Reed-Solomon code having dmin greater than or equal to 2.

In some configurations, the memory cells are multiple level memory cells capable of storing x bits, where x>1. In these configurations, the pages of the memory cell array may be denoted physical pages and each of the physical pages comprises a logical page for each of the x bits.

The memory device may further include demodulator circuitry configured to read the memory cells of the memory device and decoder circuitry configured to decode the inner code words and the outer code words and to correct errors in the inner code words and the outer code words. In some implementations, the decoder circuitry is configured to iterate between correcting the outer code words and correcting the inner code words.

Some embodiments involve a method of operating a solid state non-volatile memory device. The device includes multiple data blocks, each block comprising an array of memory cells arranged in a plurality of pages. Data is encoded into inner code words and outer code words and the inner code words and outer code words are stored in the solid state memory device. Each page of each block stores at least one inner code word. One or more pages of each block stores one or more symbols of each outer code word. The inner code words and the outer code words are read from the memory device. Errors in the data are corrected using the inner code words and the outer code words. An error corrected output is provided from the corrected data.

In some implementations, the memory device includes multiple memory chips and each of the multiple blocks is arranged respectively on one of the multiple chips.

Storing the inner code words and the outer code words in the memory device may involve storing a plurality of outer code word symbols in one page of each of the multiple blocks.

In some configurations, the pages of each block are arranged in multiple planes, and storing the inner code words and the outer code words in the memory device comprises storing at least one symbol of each outer codeword in each page of the multiple planes. Storing the inner code words and the outer code words in the memory device may involve storing only one outer code word symbol in one page of each of the multiple blocks.

In some implementations, the symbols of the outer code words are interleaved in each page.

Correcting errors in the data using the inner code words and the outer code words can involve iterating between correcting the outer code words and correcting the inner code words.

These and other features and aspects which characterize various embodiments of the present invention can be understood in view of the following detailed discussion and the accompanying drawings.

DETAILED DESCRIPTION

Error correction in solid state memory devices, including non-volatile memory (NVM) devices, becomes more important as the technology moves to smaller dimensions and to memory cells capable of storing multiple bits. Error correction using concatenated coding allows multiple codes to be used for enhanced error correction. Code concatenation reduces the complexity of the error correction process because it allows multiple, simpler error correction coding (ECC) to be implemented rather than a single more complex ECC. The use of concatenated inner and outer codes enhances error correction performance, allowing data to be more quickly recovered using less error protection when compared to approaches using an inner code alone. Outer codes can be arranged to protect particular logical and/or physical memory entities. For example, outer code words that span multiple blocks can be used to protect against block failures. A symbol-based outer code word that spans multiple blocks includes multiple symbols and a symbol of the outer code word is stored in each of the multiple blocks. Similarly, outer codes that span multiple die can be used to protect against die failures; outer codes that span multiple chips can be used to protect against chip failures.

FIG. 1is a block diagram illustrating a system configured to implement a concatenated coding scheme for a solid state memory device120. The memory device120comprises a number of memory cells; each memory cell can store one or more bits of data. Incoming data is encoded using both an inner encoder115and an outer encoder110. The inner encoder115encodes the data into inner code words and inner parity data. The outer encoder110encodes the data into outer coder words and outer parity data. A modulator117receives the encoded data and generates signals required to store the encoded data in the cells of the memory device120.

When the stored data is accessed from the memory device, voltage sense circuitry130senses the voltage levels present on the cells of the memory device120. The demodulator132converts the stored voltage levels to an encoded binary signal. The inner decoder134corrects errors in the data using the inner parity data generated by the inner encoder115. The outer decoder136corrects errors in the data using the outer parity data generated by the outer encoder110.

A typical NVM device includes an array of memory cells, each memory cell comprising a floating gate transistor. The memory cells in an array can be grouped into larger units, such as blocks, physical pages, and logical pages. An exemplary block size includes 64 physical pages of memory cells with 16,384 (16K) memory cells per physical page. Other block or page sizes can be used.FIG. 2Aillustrates a memory cell array200arranged in K blocks201. The memory cell array includes the 16K memory cells fabricated on a single semiconductor die.

FIG. 2Billustrates one block201of a memory cell array. The memory cell array comprises M×N memory cells per block201, the memory cells (floating gate transistors)202are arranged M rows of physical pages203and in columns of N NAND strings. Each physical page203is associated with a word line WL0-WLM-1. When a particular word line is energized, the N memory cells of the physical page103associated with that particular word line are accessible on bit lines BL0-BLN-1. In alternate embodiments, the memory cells of the solid state NVM may be arranged in a NOR array or in other array types, for example.

The exemplary memory array201may include memory cells that are capable of storing one bit per cell, or may include memory cells capable of storing two or more bits per memory cell. In general, the ability to program memory cells to a number of voltages, q, where q can represent any of 2cmemory states, allows c bits to be stored in each memory cell. In multi-level memory storage devices, c is greater than or equal to 2. For example, the memory cells may be programmable to four voltage levels and thus can store two bits of information per cell.

FIG. 3illustrates a block301of memory cells302that are capable of storing two bits of information denoted the most significant bit (MSB) and the least significant bit (LSB). Although this example involves multi-level memory cells that store two bits per memory cell, in general, multi-level memory cells may store three, four bits, five bits or even more bits per memory cell.

When multi-level memory cells are used to form the memory array, each physical page303associated with a word line can be subdivided into multiple logical pages320,321, as illustrated inFIG. 3. One logical page320,321for each type of bit may be stored in the memory cells302of the physical page303. Memory cell arrays that subdivide one physical page into multiple logical pages corresponding to the number of bits stored in multi-level memory cell are referred to herein as having multi-page architecture. In the exemplary memory storage array block301illustrated inFIG. 3, each physical page303associated with a word line WL1-WLM-1is subdivided into two logical pages320,321. A first logical page320includes the LSBs of the memory cells302of the physical page303. The second logical page321includes the MSBs of the memory cells302of the physical page303. The logical pages320,321associated with a physical page303are capable of being accessed (programmed or read) independently of each other. The LSBs stored in the memory cells of the physical page are accessed using a first logical page address and the MSBs stored in the memory cells of the physical page are accessed using a second logical page address.

In some implementations, the memory cell array can be arranged so that a word line is associated with multiple physical pages and each physical page is further subdivided into multiple logical pages according to the number of bits stored by each memory cell.

To increase storage capacity, some memory ICs are packaged to include multiple memory chips, each memory chip having multiple memory die per memory chip, each die having multiple memory blocks per memory die.FIG. 4illustrates an IC memory400that includes V memory chips, depicted inFIG. 4as Chips0through Chip V-1. Each memory chip includes J die, depicted inFIG. 4as Die0through Die J-1. Each die includes K blocks of memory cells, depicted inFIG. 4as Block0through Block K-1. Block0of Die0, Chip0is illustrated in detail showing the multiple memory cells per block, the memory cells of each block, are arranged in M physical pages.

An arrangement of inner and outer codes is illustrated inFIGS. 5A and 5B.FIG. 5Aillustrates memory cells of a die (in this example, Die0) arranged in multiple blocks (Block0through Block K-1). In this example, inner code words are stored in the Othpage of each of Blocks0through Block K-2. Each of the inner code words includes data bits and inner code parity bits. The outer code is stored in Page0of Block K-1of Die0. The outer code bits are formed by performing an exclusive OR (XOR) of a bit from each block. For example, outer code bit b0K-1=b00⊕b01⊕b02⊕b03. . . b0K-2; outer code bit b1K-1=b10⊕b11⊕b12⊕b13. . . b1K-2, etc., where the subscript indicates the block. The outer code parity bit indicates an error in an odd number (such as one) of the inner code bits that are XORed to form the outer code parity bit. Any single inner code word failure can be recovered using all the other inner code words.

The diagram ofFIG. 5Billustrates outer code parity that is calculated by XORing a bit from each die in an IC memory package. In this example, inner code words are stored in the 0thpage of the 0thblock of Die0through Die J-J. Page0of Block0of Die J-1contains the result of XORing the inner code word bits. Outer code parity bit b0J-1=b00⊕b01⊕b02⊕b03. . . b0J-2; outer code parity bit b1J-1=b10⊕b11⊕b12⊕b13. . . b1J-2, etc., where the subscript indicates the die. Again, in this example, any single inner code word failure can be recovered using all of the inner code words.

In some implementations, each block and/or each die is arranged in an even plane and an odd plane. Pages of the even plane may have corresponding pages in the odd plane which can be concurrently accessible. An arrangement of inner code words and outer code words for blocks or dies having multiple planes is illustrated inFIG. 6. In this scenario, each of the even plane pages602,604,606store an inner code word with inner parity bits. Each of the outer plane pages601,603,605store an inner code word with inner parity bits. The outer parity for the even plane is formed by XORing a bit from each of the even plane inner code words. The outer parity for the odd plane is formed by XORing a bit from each of the odd plane code words as illustrated inFIG. 6. For even and odd planes of a die, a die failure would invalidate both planes within a die, but since each plane is covered separately, the data can still be recovered. However, this approach may not be as robust in protecting against random inner code failures. For example, when there are two inner code failures, half of the inner code failures can be corrected if the two failures are on different planes.

One approach to improving the robustness of error correction to cover multiple inner code failures is to cover both planes with a single code having the capability to correct two errors when the error locations are known. This may be accomplished, for example, by considering the known error locations as erasures. Instead of the XOR, or single bit parity with minimum distance, dmin, of 2, a code with dmin of 3 is required, for example, a Hamming code. The overhead for using a code with dmin=3, however, is significant. For example, two plane coverage for 16 die would require a 32 bit outer code word with 6 parity bits.

An implementation that improves error correction robustness involves the use of a symbol-based outer code that spans the blocks and/or spans the die and/or spans the chips of the memory IC. Various arrangements of the outer code word are possible to provide protection against data errors. For example, in an implementation that provides protection on the block level, the symbol-based outer code word may span multiple blocks wherein each block spanned by the outer code word is arranged on a particular die of a particular chip. Outer code words that span multiple blocks, wherein the blocks spanned are arranged on different die of the same chip provide protection on the die level. Outer code words that span multiple blocks, wherein the blocks spanned are arranged on different chips provide protection on the chip level.

FIG. 7Aillustrates symbol-based outer code words that span multiple blocks (Block0through Block K-1). In this example, the multiple blocks are arranged on the 0thdie of the 0thchip, although it will be appreciated that, in the case of a memory IC with multiple die and multiple chips, the K blocks may be arranged on any of the die of any of the chips in the memory IC. InFIG. 7A, the arrangement of outer code words0through4and inner code words0through K-1is illustrated for page0of each block. Although only the arrangement of the inner code words and the outer code words for page0is shown, inner code words and outer code words for pages1through N-1may be arranged similarly to page0.

Each inner code words0through K-1include data and inner code parity bits. The last two inner code words (inner code words K-2and K-1) are the parity symbols for the outer code words. In this implementation, two blocks of outer code parity symbols would be used.

FIG. 7Billustrates a symbol-based outer code that spans multiple die of a memory chip. In this example, the outer code words span Die0through Die J-1of Chip0. Chips1through V-1may include similarly arranged outer code words.FIG. 7Billustrates outer code words0through4and inner code words0through J-1for page0of each of the J die. Although only the arrangement of the inner code words and the outer code words for page0is shown, inner code words and outer code words for pages1through N-1may be arranged similarly to page0. Each inner code word0through J-1includes data and inner code parity bits. The last two inner code words (inner code word J-2and J-1) are the parity symbols for outer code words. In this implementation, die J-2and J-1store the outer code parity symbols.

FIG. 7Cillustrates a symbol-based outer code that spans multiple chips of a memory IC. In this example, the outer code words span Chip0through Chip V-1.FIG. 7Cillustrates outer code words0through4and inner code words0through J-1for Page0of Die0. Die1through Die J-1may be similarly arranged. The outer code parity symbols for each outer code word are designated OP0and OP1. Furthermore, although only the arrangement of the inner code words and the outer code words for page0is shown, inner code words and outer code words for pages1through N-1may be arranged similarly to page0. Each inner code word0through V-1includes data and inner code parity bits. The last two inner code words (inner code word V-2and V-1) are the parity symbols for outer code words. In this implementation, Chips V-2and V-1store the outer code parity symbols.

In some configurations, the outer code words are constructed so that the outer code word parity symbols are intermixed with the data symbols within a page. In this arrangement, the outer code word symbols are not segregated into pages that only store data and pages that only store parity. An implementation in which parity symbols are intermixed with data symbols within a page is illustrated inFIG. 7D.FIG. 7Dshows the 0thpages of die0through die11in which outer code words0through4encode the 0thpages. Additional pages on each die may be similarly arranged. The outer code word parity symbols are intermixed with the data symbols on each page. The arrangement illustrated inFIG. 7Dcan be contrasted with that ofFIG. 7Bwhere the outer code data and parity symbols are not intermixed. InFIG. 7B, two pages (the 0thpages of die J-2and die J-1) store all parity symbols (OPS0, OPS1) of the outer code words. Intermixing data and parity may be used for outer code words that span various memory entities, e.g., chips, blocks, etc., and may be used for bit and/or symbol based outer code words, including the exemplary arrangements described herein.

In some implementations, the multiple planes of a chip, die or block are spanned by the symbol-based outer code words.FIG. 8illustrates an arrangement of symbol-based outer code words spanning multiple die having multiple planes. It will be appreciated that a similar arrangement of symbol-based outer code words may be used to span multiple data blocks having multiple planes or multiple memory chips having multiple planes.FIG. 8depicts a memory IC having J die, wherein each die is divided into an even plane and an odd plane. Each even plane page stores inner code words800,802,804,806,808,810,812,814and each odd plane page stores inner code words801,803,805,807,809,811,813. The inner code words include data and parity. Thus, page0of the even plane of Die0stores an inner code word800and page zero of the odd plane of Die0stores an inner code word801. Page one of the even plane of Die1stores an inner code word802and page one of the odd plane of Die1stores an inner code word803, and so forth. For example, there may be G outer code words that span the even plane pages of the J die and there G outer code words that span the odd plane pages of the J die. The even plane outer code words include pages812,814of outer parity symbols OPS0and OPS1, which are stored in the even plane of die J-2and J-1. The odd plane outer code words include pages813,815of outer parity symbols OPS0and OPS1which are stored in and the odd plane of die J-2and J-1.

In some implementations, the outer code words can span both planes of the blocks, die, or chips as illustrated inFIGS. 9A9B, and9C, respectively. Note thatFIG. 8illustrates the outer code words that span one plane of multiple die. In contrast to the scenario ofFIG. 8,FIGS. 9A,9B and9C illustrate outer code words that span multiple planes of multiple blocks, die or chips, respectively.FIG. 9Aillustrates outer code words0-4that span the even and odd planes of Blocks0through K-1. Symbol S0of outer code word0is stored in inner code word0of the even plane of Block0and symbol S1of outer code word0is stored in inner code word1of the odd plane of Block0; symbol S2of outer code word0is stored in inner code word2of the even plane of Block1and symbol S3of outer code word0is stored in inner code word3of the odd plane of Block1, and so forth. The outer parity symbols OPS0and OPS1are stored in inner code word2K-2of the even plane of Block K-1and in inner code word2K-1of the odd plane of Block K-1, respectively.

FIG. 9Billustrates outer code words that span the even and odd planes of Die0-Die J-1. Symbol S0of outer code word0is stored in inner code word0of the even plane of Die0, symbol S1of outer code word0is stored in inner code word1of the odd plane of Die0, symbol S2of outer code word0is stored in inner code word2of the even plane of Die1, and symbol S3of outer code word0is stored in inner code word3of the odd plane of Die1, and so forth. The outer parity symbols OPS0and OPS1are stored in inner code word2J-2of the even plane of Die J-1and in inner code word2J-1of the odd plane of Die J-1, respectively.

FIG. 9Cillustrates a configuration that includes outer code words that span the even and odd planes of Die0of Chip0-Chip V-1.FIG. 9Conly shows the arrangement for Die0of Chips0through V-1, y those skilled in the art will understand that a similar arrangement may be implemented for each die of Chips0through V-1.

The use of a Reed-Solomon outer code with dmin greater than or equal to 2 allows for the correction of errors without knowing the location of the errors. For example, with two planes per block (or two planes per die) and two parity symbols per outer code word, all single symbol errors within one outer code word can be recovered if no two errors occur in the same code word.

At higher bit error rates, the probability of having two or more errors in the same outer code word may be significant. In these situations, extending multiple symbols of the outer code words along an inner code word may be helpful. An arrangement that includes multiple outer code word symbols extending along an inner code word for outer code words that span multiple planes of multiple blocks is illustrated inFIG. 10A.FIG. 10Aillustrates two outer code words having symbols that extend along inner code words, although it is to be understood that additional outer code words and/or inner code words may be used. Each of the outer code words has12symbols that extend along three inner code words. As illustrated inFIG. 10A, symbols S0, S1, S2, S3of outer code words0and1extend along inner code word0of the even plane of block0; symbols S4, S5, S6, S7of outer code words0and1along inner codeword1of the odd plane of block0, and symbols S8, S9, S10, S11of outer code words0and1extend along inner code word2of the even plane of block1, etc. The odd and even planes of block JK-1store the outer code word parity symbols.FIGS. 10B and 10Cillustrates similar arrangements, except that the outer code words span multiple die (FIG. 10B) or multiple chips (FIG. 10C), rather than multiple blocks as illustrated inFIG. 10A.

The systems and methods described herein involving the use of concatenated inner and outer codes provide the capability to continue data recovery even when some of the outer code words are not correctable. Corrected data from the outer code words that are correctable can be used to recover some of the inner code words that originally failed. Correcting a fraction of the bits in error at a time, in many cases, will be sufficient to gradually reduce the number errors by repeated iterations until all the errors are corrected. This approach enhances error correction because only some of the outer code words need to be corrected in the first iteration.

An error recovery process that includes iterating between correcting the outer code words and correcting the inner code words is illustrated by the flow diagram ofFIG. 11. Error recovery begins1110, followed by a determination that one or more inner code words are correctable1120. If some or all of the inner code words are correctable, then the inner code words are corrected1140. If additional error correction is possible1150, then the outer code words are corrected1130followed by correction of the inner code words1140. The error correction process ends1160when no additional error correction is possible or when the maximum number of iterations occur or upon process time out.

An error recovery process that uses correction of the outer code words to facilitate correction of the inner code words is further illustrated inFIGS. 12A-12C.FIG. 12Ashows an example of data that is not recoverable without iterations between correcting the outer code words and correcting the inner code word. In the example illustrated inFIG. 12A, each inner code can correct eight errors, and each outer code can correct eight errors. Each shaded rectangle inFIGS. 12A-12Cindicates an error1200. Inner code words0-2have errors that are not correctable using the inner code words because each of these inner code words has more than eight errors and are therefore not correctable. Outer code words0and3also have more than eight errors and are not correctable. However outer code words1and2have fewer than eight errors and are correctable. Correcting outer code words1and2and then using these corrections to facilitate correcting the inner code words is beneficial, as illustrated inFIG. 12B. After outer code words1and2are corrected, on the second inner code words correction iteration, inner code words0and1can now be corrected, as shown inFIG. 12C. The remaining errors illustrated inFIG. 12Care correctable because, although inner code word2includes more than eight errors, outer code words0and three contain less than eight errors and are therefore correctable.

In some practical applications, it is desirable and less expensive to use smaller code words and to protect each page of the memory with multiple inner code words and outer code words. An arrangement using multiple concatenated codes in this manner is illustrated inFIG. 13.FIG. 13illustrates page0of even and odd planes of a block, die, or chip. Additional pages, e.g., pages1through M-1, of the block, die or chip may be arranged similarly, although for illustration purposes only page0is shown inFIG. 13. In various configurations, the outer code words may span the even and odd planes of multiple chips, multiple die or multiple blocks.

In this example, there are two inner code words1305,1315per page, although more inner code words per page are possible Inner code word01305and an Inner code word11315each include data bits1301and inner code parity bits (IP)1302. Outer code words0through3may be symbol-based as depicted inFIG. 13. Each outer code word has U symbols, denoted S0through SU-1. Symbols S0through SU-3are outer code data symbols and symbols SU-2and SU-1are outer code parity symbols. Outer code word0and Outer code word1each span the 0thinner code words1305of the 0thpages for the odd and even planes of each chip, die, or block. Outer code word2and outer code word3each span the 1stinner code words1315of the 0thpage of each chip, die or block. Note that the inner and outer code words of additional pages, (e.g., pages1through M-1) which are not shown inFIG. 13, may be similarly arranged.

Another implementation is illustrated inFIG. 14. This implementation spreads each outer code word over all of the inner code words of a page so that each inner code failure impacts a smaller portion of the outer code word. In various configurations, the outer code words may span the even and odd planes of multiple chips, multiple die or multiple blocks. For example,FIG. 14illustrates symbol-based outer code words that span both inner code words of a page of even and odd planes of each chip, die or block. Using this arrangement, each inner code word of a page is protected by each outer code word.FIG. 14illustrates the arrangement of inner code words and outer code words for page0of even and odd pages of a block, die or chip. In this example, although only the 0thpage of each chip, die, or block is shown, additional pages, e.g., pages1through M-1may be arranged similarly.

The example ofFIG. 14includes two inner code words1405,1415per page, although more inner code words per page may be used. Each inner code word1405,1415includes data bits1401,1411and parity bits1402,1412. Outer code words0through3may be symbol-based, each having U symbols as shown inFIG. 14. For example, inFIG. 14, each outer code word0through3spans both the 0thinner code word1405and the 1stinner code word1415of each page0of the even and odd planes of the chip, die or block. For each outer code word0through3, outer code symbols S0through SU-5are outer code data symbols and outer code symbols SU-4through SU-1are outer code parity symbols. As illustrated inFIG. 14, symbol S0of outer code word0is arranged in inner code word01405, symbol S1of outer code word0is arranged in inner code word11415, symbol S2of outer code word0is arranged in inner code word01405, symbol S3is arranged in inner code word11415, and so forth.

FIG. 15shows an alternate approach which involves interleaving the outer code words within a page. In various configurations, the outer code words may span the even and odd planes of multiple chips, multiple die or multiple blocks. The example ofFIG. 15illustrates one inner code word per page, although a greater number of inner code words per page may be used. Each inner code word1501includes data bits1511and parity1512. The outer code words may be symbol-based, each outer code word comprising U symbols. In this example, the outer code words span the 0thpages of even and odd planes of a chip, a die or a block. The symbols of the outer code words are interleaved within each of the 0thpages. For example, the symbols S0and S1of each outer code word are interleaved in page0of the even plane of the 0thchip, die or block; the symbols S2and S3of each outer code word are interleaved in page0of the odd plane of the 0thchip die or block; the symbols S4and S5of each outer code word are interleaved in page0of the even plane of the 1stchip, die, or block, and so forth.

When multiple inner code words are used per page, the number of outer code words covering the inner code words need not be exactly equal.FIG. 16illustrates one configuration that includes an unequal number of outer code words for each inner code word of a page, although other implementations of unequal outer code word coverage are possible. InFIG. 16each page is encoded by two inner code words. The first group of inner code words is covered by five outer code words (outer code words0through4) and the second group of inner code words is covered by three outer code words (outer code words5through7.