System and method for pre-charged linear phase-frequency detector

A method for comparing phases of two signals including placing a first output node in a floating state, detecting a first edge of a first signal on a first input node after placing the first output node in the floating state, coupling the first edge of the first signal to the first output node and resetting the first output node to the floating state after coupling the first edge of the first signal to the first output node. A system for comparing phases of two signals can also be included.

BACKGROUND

The present invention relates generally to phase-locked loop (PLL) circuits, and more particularly, to methods and systems for detecting the phase-frequency in a PLL circuit.

Phase-Frequency detectors are commonly used in phase-locked loop (PLL) circuits. PLL's are often used as part of input/output (I/O) portions microprocessors and in clock signal generating circuits.FIG. 1Ais a schematic diagram of a typical PLL circuit100used in frequency synthesis. The PLL includes a phase-frequency detector (PFD)102, a charge-pump104, a loop filter106, a voltage-controlled oscillator (VCO)108and a frequency divider110. The function of each of these components is described as follows.

The PFD102detects a phase difference between the edges of a reference clock122and a second signal (e.g., a feedback clock)124. The PFD102produces two output signals: a pump-up signal132and a pump-down signal134. The width of the pump-up signal132and pump-down signal134is proportional to a detected phase difference between the reference clock122and the feedback clock124. A PFD102can also be used in any other circuit where the phases of two signals are compared to produce one or more output signals proportional to the phase difference of the input signals.

The charge-pump104responds to the pump-up signal132and pump-down signal134output by the PFD102to deliver a net amount of charge to the loop filter106proportional to the phase difference between the reference clock122and the feedback clock124. The loop filter106converts the current136delivered by the charge-pump104into a loop filter voltage142. The loop filter voltage142is then applied to the VCO108to adjust or tune the frequency of the VCO clock output signal152. The VCO108varies its frequency of oscillation in response to the loop filter voltage142. The VCO108typically uses a transfer function in Hertz/Volt to produce a VCO clock output signal152with a frequency corresponding to the loop filter voltage142.

The frequency divider110divides the frequency of VCO clock output signal152by a selected division ratio (N). The resulting frequency of the signal124output by the frequency divider110is 1/N of the frequency of the VCO output signal152. If the PLL100is locked on a selected frequency of the VCO clock output signal152, the frequency of feedback clock124is equal to that of the reference clock122. The phase of the feedback clock124is also coincidental with the phase of the reference clock122. It can also be said that the PLL100multiplies the frequency of the reference clock122by a factor of N.

Unfortunately VCOs typically produce a significant portion of jitter. Jitter is defined as slight shifts in phase of the VCO clock output signal152. The frequency of operation of microprocessors is ever increasing over time. By way of example, some I/O circuits have 4 Gbps cycle rates and in the future will be 8 Gbps and even faster. This requires clocks of higher and higher frequencies or clocks cycles of corresponding shorter periods. The amount of jitter that the microprocessor can tolerate in the shorter duration clocks is smaller for shorter clock periods. Acceptable jitter is normally specified in unit intervals or UI that is a fraction of the clock period. Restated, even if the jitter specification is unchanged (i.e., the same UI) the absolute amount of time allotted for jitter will be actually be reduced for clocks with shorter periods. Therefore there is a need for systems and methods for reducing jitter in the VCO clock output signal152.

SUMMARY

Broadly speaking, the present invention fills these needs by providing systems and methods for reducing clock jitter. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, computer readable media, or a device. Several inventive embodiments of the present invention are described below.

One embodiment provides a method for comparing phases of two signals including placing a first output node in a floating state, detecting a first edge of a first signal on a first input node after placing the first output node in the floating state, coupling the first edge of the first signal to the first output node and resetting the first output node to the floating state after coupling the first edge of the first signal to the first output node.

The floating state of the first output node can include deactivating a current source connected to the first output node and deactivating a current sink connected to the first output node. The current sink can be deactivating at the same time or before the current source is deactivating.

Resetting the first output node to the floating state after coupling the first edge of the first signal to the first output node can include resetting the first output node to the floating state after a sufficient time delay for the first output node to achieve a voltage corresponding to the first edge of the first signal.

The method can also include placing a second output node in a floating state, detecting a first edge of a second signal on a second input node after placing the second output node in the floating state, coupling the first edge of the second signal to the second output node and resetting the second output node to the floating state after coupling the first edge of the second signal to the second output node.

Resetting the first output node to the floating state after coupling the first edge of the first signal to the first output node and resetting the second output node to the floating state after coupling the first edge of the second signal to the second output node can include resetting the first output node and the second output node to the floating state after a sufficient time delay for the first output node and the second output node to achieve an equal signal level. The first output node and the second output node can achieve an equal signal level for a time duration substantially equal to a phase difference between the first input signal and the second input signal.

The first signal can be a reference signal and the second signal can be a feedback signal. The second signal can be a feedback signal from a voltage controlled oscillator.

Another embodiment provides a circuit for comparing phases of two signals. The circuit includes a first input circuit including a first input node, a first output node coupled to the first input node through a first input semiconductor switch, a current source coupled to the first output node through a first source semiconductor switch, and a current sink coupled in series with the first input semiconductor switch through a first sink semiconductor switch. The circuit also includes a first reset circuit having a first input coupled to the first output node and an output coupled to the first sink semiconductor switch and a second reset circuit having an input coupled to the first output node and the second reset circuit includes an output coupled to the to the first source semiconductor switch, the first reset circuit and the second reset circuit capable of placing the first output node in a floating state.

The first reset circuit can be capable of deactivating the first source semiconductor switch, wherein the first sink semiconductor switch is deactivated at substantially the same time or before the first source semiconductor switch is deactivated. The input of the second reset circuit can be coupled to the output of the first reset circuit.

The circuit can also include a second input circuit including a second input node, a second output node coupled to the second input node through a second input semiconductor switch, the current source coupled to the second output node through a second source semiconductor switch and the current sink coupled in series with the second input semiconductor switch through a second sink semiconductor switch.

The first reset circuit can include a second input coupled to the second output node and a second output of the first reset switch is coupled to the second sink semiconductor switch and wherein the output of the second reset circuit is coupled to the to the second source semiconductor switch, the first reset circuit and the second reset circuit capable of placing the second output node in a floating state.

The first reset circuit can include a second input coupled to the second output node and the output of the first reset switch is coupled to the second sink semiconductor switch and wherein the output of the second reset circuit is coupled to the to the second source semiconductor switch, the first reset circuit and the second reset circuit capable of placing the second output node in a floating state.

The first reset circuit can include a second input coupled to the second output node and the output of the first reset circuit is coupled to the second sink semiconductor switch, the second reset circuit capable of deactivating the second sink semiconductor switch and wherein the output of the second reset circuit output is coupled to the second source semiconductor switch, the second reset circuit capable of deactivating the second source semiconductor switch, wherein the first sink semiconductor switch and the second sink semiconductor switch are deactivated at substantially the same time or before the first source semiconductor switch and the second source semiconductor switch are deactivated.

The first signal can be a reference signal and the second signal can be a feedback signal. The second signal can be a feedback signal from a voltage controlled oscillator. The first reset circuit can be capable of deactivating the first source semiconductor switch, wherein the first sink semiconductor switch is deactivated at substantially the same time or before the first source semiconductor switch is deactivated.

Yet another embodiment provides a circuit for comparing phases of two signals. The circuit includes a first input circuit including a first input node, a first output node coupled to the first input node through a first input semiconductor switch, a current source coupled to the first output node through a first source semiconductor switch and a current sink coupled in series with the first input semiconductor switch through a first sink semiconductor switch. The circuit also includes a second input circuit including a second input node a second output node coupled to the second input node through a second input semiconductor switch, the current source coupled to the second output node through a second source semiconductor switch and the current sink coupled in series with the second input semiconductor switch through a second sink semiconductor switch. The circuit also includes a first reset circuit having a first input coupled to the first output node and an output coupled to the first sink semiconductor switch and a second reset circuit having an input coupled to the first output node and the second reset circuit includes an output coupled to the to the first source semiconductor switch, the first reset circuit and the second reset circuit capable of placing the first output node in a floating state, wherein the first reset circuit includes a second input coupled to the second output node and the output of the first reset circuit is coupled to the second sink semiconductor switch, the second reset circuit capable of deactivating the second sink semiconductor switch and wherein the output of the second reset circuit output is coupled to the second source semiconductor switch, the second reset circuit capable of deactivating the second source semiconductor switch, wherein the first sink semiconductor switch and the second sink semiconductor switch are deactivated at substantially the same time or before the first source semiconductor switch and the second source semiconductor switch are deactivated.

DETAILED DESCRIPTION

Several exemplary embodiments for systems and methods for reducing clock jitter will now be described. It will be apparent to those skilled in the art that the present invention may be practiced without some or all of the specific details set forth herein.

One embodiment uses a higher frequency reference clock122′ to reduce jitter in the VCO clock output signal152. The higher frequency of the reference clock122′ is limited only by the highest frequency that the PLL circuit can tolerate. In addition to reducing jitter, the higher frequency reference clock122′ also provides a higher frequency refresh rate of the PLL, improved noise filtering and a simpler frequency divider.

The PLL will have a higher frequency refresh rate because the PLL will be refreshed or updated at the same higher frequency of the reference clock122′. As a result, the corrections are applied to the PLL circuit more often.

The noise filtering is improved because the PLL acts as a low-pass filter to filter out phase noise and the jitter resulting therefrom that may be a result of the reference clock122. Therefore, for a given bandwidth, the noise produced by a higher frequency reference clock122′ will be better filtered by the low-pass filter action of the PLL.

The frequency divider110can be simpler because the PLL100performs a simpler frequency multiplication with a higher frequency reference clock122′. More specifically, once the PLL100is locked on a frequency, the frequency of the VCO clock152is N times the frequency of the reference clock122′, where N is the division ratio of the divider110. Therefore, for a selected output frequency of the VCO clock152the division ratio N of the divider110will be smaller for a higher frequency reference clock122′ than for a typical frequency reference clock122. By way of example if a desired output frequency of the VCO clock152is 10 GHz, and the reference clock122is 1 GHz, then N must be equal to 10 to achieve the output frequency of 10 GHz. Alternatively, if the higher frequency reference clock122′ is 5 GHz, then N must only be equal to 2 to achieve the output frequency of 10 GHz. A lower division ratio (N) requires a simpler frequency divider110than a higher division ratio. The simpler frequency divider110can require fewer components. Therefore, the simpler frequency divider110can be smaller, more reliable and consume less power.

Noise injected at the VCO causes phase shifts in the VCO clock output152. A loop with a higher bandwidth will correct for such phase shifts more quickly than a loop with smaller bandwidth. Filtering is achieved for the same bandwidth but if the amount of filtering was already acceptable for the lower frequency reference clock122then by increasing the frequency of the reference clock to the higher frequency reference clock122′ the frequency of the noise injection caused by the reference clock also increases, therefore the loop bandwidth can be increased without compromising the filtering action on the injection while at the same time making the loop more agile to clean VCO noise. As a result, the overall causes of jitter within the VCO are reduced. Further bandwidth increase is possible given the fact that phase degradation in the loop caused by the delay through the divider is smaller for a given bandwidth, due to the smaller division ratio. As a result, the same phase margin could be achieved at a higher bandwidth.

FIGS. 1B and 1Care schematic diagrams of two of the most common topologies of linear PFDs102′ and102″ that can be used to perform the function of the PFD102. The PFD102′ inFIG. 1Bis based on nand gates160A-160J and inverters161A-161F with reset168. The PFD102″ inFIG. 1Cis based on D flip-flops170A and170B, inverter172, nand gate174, with reset168′.

FIGS. 1D and 1Eare graphical representations of the corresponding waveforms for the reference clock122leading the feedback clock124in a PFD. The rising edge of the reference clock122initiates the pump-up output132and the rising edge of the feedback clock124initiates the rising edge of the pump-down output134. The reset signal180A (and/or reset_not signal180B) are initiated at a time delay after both the reference clock122and the feedback clock124are high. The reset signal (and/or reset_not signal180B) reset the pump-up output132and the pump-down output134. Referring now toFIG. 1D, if the rising edge of the reference clock122leads the rising edge of the feedback clock124, then the pulse width of the pump up signal132is wider than the pulse width of the pump down signal134resulting in a net pump-up shown as the I-out signal136. Referring now toFIG. 1E, if the rising edge of the feedback clock124leads the rising edge of the reference clock122, then the pulse width of the pump down signal134is wider than the pulse width of the pump up signal132resulting in a net pump-down shown as the I-out signal136. If the rising edge of the feedback clock124and the rising edge of the reference clock122occur simultaneously, then the pulse width of the pump down signal134is the same as the pulse width of the pump up signal132resulting in a zero net pump-up or pump-down (i.e., I-out signal136=0).

Referring now toFIGS. 1A,1D and1E, the I-out signal136is produced by the charge-pump104in response to the pump up signal132and the pump down signal134. More specifically, the pump up signal132causes the current to be sourced by the current source135A. The current provided by the current source135A is applied to the loop filter106, if the current sink135B is not sinking the current (i.e., current sink135B is disabled because pump-down signal134is not applied to the current sink135B). The current provided by the current source135A is applied to the current sink135B when the pump-down signal134is applied to the current sink135B. Similarly, the current sink135B sinks current from the loop filter106, unless the current source135A is enabled (i.e., when pump up signal132enables the current source135A. Sourcing current to or sinking current from the loop filter106increases or decreases the voltage on the VCO108, which correspondingly varies the frequency of the VCO.

FIG. 2is a schematic diagram of an improved PFD200, in accordance with an embodiment of the present invention. One of the limits imposed on the maximum frequency of the reference clock122′ is the circuit structure and operation of the typical PFD102shown inFIG. 1Aabove. The improved PFD200provides a maximum frequency of operation that is substantially higher than the frequency of operation of the traditional PFD102. The improved PFD200enables the use of the higher frequency reference clock122′. The improved PFD200is pre-charged to enable the use of the higher frequency reference clock122′. The pre-charged PFD200has a fast response time.FIGS. 3A-Care schematic diagrams of PFDs200′,200″ and200′″ in accordance with additional embodiments of the present invention.

The pre-charged PFDs200-200′″ are faster because the nodes u1, u2, d1and d2are pre-charged. When the nodes u1, u2, d1and d2are pulled-down or pulled-up (depending on their respective polarity and type of device e.g., PMOS/NMOS), a respective input transistor will drive each of the nodes in the respective pulled-up or pulled-down state. Before the state of each of the nodes u1, u2, d1and d2can be changed, the respective input transistor must first be disabled. If the respective input transistor is not first disabled, then the input transistor will initially fight switching the state of the respective nodes. As a result, if driven too fast, an excess (or bleeding) current can be produced in a transitional state of the input as in traditional CMOS logic. This bleeding current can cause jitter in the VCO clock output signal152.

By way of example, in a typical inverter including a PMOS transistor and a NMOS transistor, both PMOS and NMOS transistors conduct when the input passes through a middle value. When both the PMOS and NMOS transistors conduct, a current spikes results due to the current passing from supply to ground during that time.

Referring again to the pre-charged PFDs200-200′″, to reduce the fighting the changing of the states of the nodes u1, u2, d1and d2, each one of the respective input transistors are disabled before the state of the nodes are switched. As a result, the nodes u1, u2, d1and d2are temporarily placed in a floating state before trying to switch their respective states. The nodes u1, u2, d1and d2can temporarily store their last set value in their respective parasitic capacitance until their respective input transistors instruct them to change their state.

FIG. 4is a flowchart of the method operations400performed by the PFDs200-200′″, in accordance with an embodiment of the present invention.FIGS. 5A and 5Bare graphical representations of the corresponding waveforms compared to time for the reference clock122leading the feedback clock124in a PFD200-200′″, in accordance with various embodiments of the present invention.FIG. 5Aillustrates the states of the various nod in the PFD200-200′″ in a pump-up condition.FIG. 5Billustrates the states of the various nodes in the PFD200-200′″ in a pump-down condition. Referring now toFIGS. 2,4and5A, the rising edge of the reference clock122′ leads the rising edge of the feedback clock124. Starting with the reset signal210A in a low state, which disables (stops conducting) current sinking semiconductor switch NMOS202B and thereby allowing an easy pull-up of first input node ul by input semiconductor switch PMOS202A. Since the reset signal210A is in a low state, then reset_not210B is in a high state, which disables PMOS202G and thereby allowing first output node u2to float because the current source semiconductor switch PMOS202G no longer couples the applied current source201A to the first output node u2. The rising edge of the reference clock122′ enables (e.g., starts conducting) current sinking semiconductor switch NMOS202H, which pulls first output node u2low. The rising edge of the reference clock122′ also enables current sinking semiconductor switch NMOS202C and disables input semiconductor switch PMOS202A. First output node u2is low because current sinking semiconductor switches NMOS202H and NMOS202J are sinking any current available at first output node u2to ground (e.g., series coupled current sinking semiconductor switches NMOS202H and NMOS202J are a current sink for first output node u2by coupling first output node u2to ground201B). An inverter208A inverts the low state of the first output node u2to produce a high pump-up signal132.

Starting with the reset signal210A in a low state, which disables current sinking semiconductor switch NMOS202E and thereby allowing an easy pull-up of second input node d1by input semiconductor switch PMOS202D. Since the reset signal210A is in a low state, then reset_not210B is in a high state, which disables current source semiconductor switch PMOS202K causing the applied current source201A to no longer be coupled across current source semiconductor switch PMOS202K to the second output node d2and thereby allowing the second output node d2to float. The rising edge of the feedback clock124enables current sinking semiconductor switch NMOS202L, which pulls the second node d2low. The rising edge of the feedback clock124also enables current sinking semiconductor switch NMOS202F and disables input semiconductor switch PMOS202D. The second node d2is low because current sinking semiconductor switches NMOS202L and NMOS202M are sinking any current available at the second output node d2by coupling output node d2to ground201B. An inverter208B inverts the low state of the second output node d2to produce a high pump-down signal134.

In an operation405ofFIG. 4, a first output node (e.g., node u2or d2) is placed in a floating state. Node u2can be placed in a floating state by disabling the current sinking through NMOS202H and/or NMOS202J. Similarly, node d2can be placed in a floating state by disabling the current sinking through NMOS202L and/or NMOS202M.

Referring again toFIGS. 2 and 5A, the NOR gate206produces a reset signal210A. The inverter204inverts the reset signal210A to produce a reset_not signal210B. The reset signal210A is high only when both of output nodes u2and d2are low. Conversely, the reset_not signal210B is low only when both of output nodes u2and d2are low. When both of output nodes u2and d2are low (e.g., when a high pump-up signal132and a high pump-down signal134are being produced), the reset signal210A is high and enables current sinking semiconductor switches NMOS202B and NMOS202E. As a result, current sinking semiconductor switches NMOS202B and NMOS202C sink the current to input node u1by coupling input node u1to ground201B and current source semiconductor switches NMOS202E and NMOS202F sink the current to input node d1by coupling input node d1to ground201B. As a result input nodes u1and d1are driven low. When input nodes u1and d1are driven low, then current sinking semiconductor switches NMOS202J and202M, respectively are disabled which decouples ground201B to output nodes u2and d2causing output nodes u2and d2, respectively to begin to float.

A short time delay after the reset signal210A goes high, the reset_not signal210B goes low. The low reset_not signal210B enables current source semiconductor switches PMOS202G and PMOS202K. Enabling current source semiconductor switches PMOS202G and PMOS202K couples current source201A to the output nodes u2and d2and drives respective output nodes u2and d2to a high state. Since the output nodes u2and d2were floating before the current source semiconductor switches PMOS202G and PMOS202K were enabled, then the current source semiconductor switches PMOS202G and PMOS202K were required to provide less current to drive the respective output nodes u2and d2to the high state. When the output nodes u2and d2are at a high state, the respective pump-up signal132and pump-down signal134go to a low state.

As the output nodes u2and d2are at a high state and the next incoming rising edges of the reference clock122′ and the feedback clock124are due, it would be beneficial to have the output nodes u2and d2in a floating state before the rising edges of the reference clock122′ and the feedback clock124arrive at the inputs.

As the output nodes u2and d2are at a high state, the reset signal210A switches to a low state, which disables current sinking semiconductor switches NMOS202B and NMOS202E. When current sinking semiconductor switches NMOS202B and NMOS202E are disabled, then nodes u1and d1are left floating waiting to be pulled up when the reference clock122′ and the feedback clock124go to a low state. Input nodes u1and d1are pulled high in preparation for when the reference clock122′ and the feedback clock124go to a high state. The reset signal210A switching to a low state also causes the reset_not signal210B to switch to a high state. The reset_not signal210B high state disables current source semiconductor switches PMOS202G and PMOS202K causing output nodes u2and d2to float.

Referring again toFIG. 4, in an operation410, a first edge of the first signal is detected on a first input node at a time after the first output node is placed in the floating state. As described above, the output nodes u2and d2are placed in a floating state shortly after causing the respective pump-up signal132and pump-down signal134to go to a low state.

In an operation415, the first edge of the first signal is coupled to the first output node as described above. In an operation420, the first output node is reset to the floating state after the first edge of the first signal is coupled to the first output node.

FIGS. 5A and 5Bare graphical representation of the waveforms of the pre-charged PFDs200-200′″ ofFIG. 4, in accordance with an embodiment of the present invention.FIGS. 5A and 5Billustrate the cases where, (a) reset210A and reset-not210B occur during reference clock122′ high and (b) reset210A and reset_not210B occur when reference clock122′ is low. The time when the pump-up signal132and the pump-down signal134overlap (t_ovrLap) is equal to the sum of the several propagation delays as follows,
t_ovrLap=tpd—I3+tpd—I4+tpd—P2u
t_ovrLap=tpd—I3+tpd—I4+tpd—P2d

where tpd_*=propagation delay of * instance or device.

For the proposed PFD to operate properly two conditions must be met,

Condition 1 will ensure that output nodes u2and d2are fully discharged by the rising of the respective reference clock122′ and feedback clock124before input nodes u1and d1are discharged by the rising of reset signal210A. The last output node, either u2or d2, that was the last to go to a low state will trigger the reset signal210A to go to a high state.

Condition 2 will ensure that output nodes u1and d1are fully discharged by the reset signal210A going high before PMOS202G and PMOS202K, respectively, are commanded to pull-up by the reset_not signal210B going to a low state. Otherwise if the respective reference clock122′ and/or the feedback clock124is high NMOS202J and NMOS202M will fight with PMOS202G and PMOS202K, respectively, attempting to pull-up the output nodes u2and d2at the same time. This conflict would slow down the charging of the output nodes u2and d2and produce a spike of current flowing through the PMOS202G to the NMOS202H and NMOS202J to ground and PMOS202K through NMOS202L and NMOS202M to ground.

The proposed pre-charged PFD200-200′″ has a maximum frequency of operation which is substantially higher than that of existing topologies such as those inFIG. 1A. The higher frequency capability will enable the use of a higher frequency reference clock122′. While not described in detail, the operation of the PFDs200′,200″ and200′″ shown inFIGS. 3A-3C, respectively, operate in a similar manner to that described above for PFD200. Specifically, the output nodes of PFDs200′,200″ and200′″ are allowed to float before being switching states so that they output nodes can switch states more easily, more quickly and more power efficiently.

It should be understood that while NMOS and PMOS devices are described above, NMOS devices and PMOS are merely exemplary devices and that any type of switching circuit device or semiconductor switching device including transistors and other switching devices can be used interchangeably to perform the same functions with respective relatively minor adjustments to voltage polarity and circuit structure.

It will be further appreciated that the instructions represented by the operations in the aboveFIG. 5are not required to be performed in the order illustrated, and that all the processing represented by the operations may not be necessary to practice the invention. Further, the processes described in any of the above figures can also be implemented in software stored in any one of or combinations of the RAM, the ROM, or the hard disk drive.