Semiconductor memory device and method of fabricating the same

A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

BACKGROUND

Embodiments of the present disclosure are directed to a semiconductor memory device and a method of fabricating the same, and in particular, to a semiconductor memory device that includes buried gate lines and a method of fabricating the same.

Due to their small-sized, multifunctional, or low-cost characteristics, semiconductor devices are important elements in the electronic industry. Semiconductor devices can be classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that include both memory and logic elements.

Due to increasing demand for high speed low-power electronic devices, semiconductor devices require a fast operating speed or a low operating voltage. To satisfy this demand, a semiconductor device needs a high integration density, that is, more elements per area. However, an increase in the integration density can lead to a decrease in the reliability of the semiconductor device.

In a dual work function metal gate structure, a tungsten electrode is provided at a lower level, and an n-doped poly-silicon is provided at an upper level. In this structure, owing to a subsequent thermal treatment process, intermixing between the two materials can occur. To prevent this intermixing, a barrier layer having a low resistance property is used.

In a conventional technology, a SiO2-based material is used as the barrier layer. If such a SiO2-based barrier layer has a thickness of 10 Å or more, it can act as an insulating layer, which can lead to a deterioration of the electric characteristics of the semiconductor device. In some cases, the barrier layer is formed by directly depositing a TiN-based metal layer and removing a sidewall portion thereof. However, in these cases, it is challenging to control dispersion errors while depositing and removing the metal layer. Moreover, during the deposition process, metal contamination can occur in a sidewall portion of a gate oxide.

SUMMARY

Some embodiments of the inventive concept can provide a semiconductor memory device that is configured to reduce gate-induced-drain-leakage (GIDL) current, and a method of fabricating the same.

Some embodiments of the inventive concept can provide a semiconductor memory device having good reliability, and a method of fabricating the same.

According to exemplary embodiments of the inventive concept, a method of fabricating a semiconductor memory device include etching a substrate to form a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower region of the trench, oxidizing a top surface of the first gate electrode to form a preliminary barrier layer, nitrifying the preliminary barrier layer to form a barrier layer, and forming a second gate electrode on the barrier layer that fills an upper region of the trench.

According to exemplary embodiments of the inventive concept, a semiconductor memory device includes a semiconductor substrate that includes a trench, a gate insulating layer disposed in the trench that covers bottom and inner side surfaces of the trench, a first gate electrode disposed in a lower region of the trench, the first gate electrode including a first metal, a second gate electrode disposed in the trench and on the first gate electrode, and a barrier layer provided between the first and second gate electrodes, the barrier layer including an oxynitride of the first metal. A work-function of the second gate electrode is lower than a work-function of the first gate electrode.

According to exemplary embodiments of the inventive concept, a semiconductor memory device includes a substrate that includes active regions surrounded by a device isolation layer, the active regions extending in a first direction, gate lines buried in trenches formed in an upper portion of the substrate, where the gate lines cross the active regions in a second direction that crosses the first direction and divide the active regions into first and second doped regions, and a bit line disposed on the gate lines that extends in a third direction that crosses both of the first and second directions. Each of the gate lines includes a first gate electrode disposed in a lower region of the trench, where a top surface of the first gate electrode includes oxygen and nitrogen atoms, and a second gate electrode disposed on the first gate electrode.

It should be noted that these drawings are not to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment. The use of similar or identical reference numbers in the various drawings may indicate the presence of a similar or identical element or feature.

DETAILED DESCRIPTION

Exemplary embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown.

FIG. 1is a plan view of a semiconductor memory device according to some embodiments of the inventive concept.FIGS. 2A and 2Bare sectional views taken along lines I-I′ and II-II′, respectively, ofFIG. 1, that illustrate a semiconductor memory device according to some embodiments of the inventive concept.FIGS. 3 to 6are sectional views, which are taken along line I-I′ ofFIG. 1and illustrate a semiconductor memory device according to some embodiments of the inventive concept.

In the present specification, a first direction D1, a second direction D2, and a third direction D3, which are defined on the same plane, will be used to scribe directional aspects of an element. The first direction D1and the second direction D2are perpendicular to each other, and the third direction D3is not parallel to either of the first or second directions D1and D2.FIG. 2Ashows a cross section taken in the third direction D3, andFIG. 2Bshows a cross section taken in the second direction D2.

According to some embodiments, referring toFIGS. 1, 2A, and 2B, a device isolation layer110is provided in a substrate100to define active regions ACT. The substrate100includes a semiconductor substrate. For example, the semiconductor substrate may be or include a silicon wafer, a germanium wafer, or a silicon-germanium wafer. When viewed in a plan view, each of the active regions ACT has a bar-like shape that extends in the third direction D3.

According to some embodiments, gate lines GL are provided in the substrate100to cross the active regions ACT, when viewed in a plan view. The gate lines GL can be used as word lines. The gate lines GL extend in the second direction D2and are arranged in the first direction D1. The gate lines GL are buried in the substrate100. For example, the gate lines GL can be provided in trenches120of the substrate100. The trenches120extend to cross the active regions ACT.

According to some embodiments, each of the gate lines GL includes a first gate electrode220, a barrier layer230, and a second gate electrode240. The first gate electrode220is provided in the trench120. The first gate electrode220partially fills the trench120. The first gate electrode220fills a lower region of the trench120. The first gate electrode220is formed of or includes at least one metal such as tungsten (W), titanium (Ti), or tantalum (Ta).

According to some embodiments, the second gate electrode240is disposed on the first gate electrode220to fill a portion of the trench120. When viewed in a plan view, the second gate electrode240overlaps the first gate electrode220. For example, each of the first and second gate electrodes220and240extends in the second direction D2. The second gate electrode240covers a top surface of the first gate electrode220. A top surface of the second gate electrode240is positioned at a level below that of a top surface of the substrate100. A work-function of the second gate electrode240is lower than that of the first gate electrode220. The second gate electrode240is formed of or includes polysilicon that is doped with n-type impurities.FIG. 2Aillustrates an example in which the second gate electrode240has a flat top surface, but the inventive concept is not limited thereto. As shown inFIG. 3, the top surface240aof the second gate electrode240may have an inwardly recessed shape (i.e., a shape recessed toward the first gate electrode220). For example, the top surface240aof the second gate electrode240may be formed to have a “V”-shaped section. In certain embodiments, the top surface240aof the second gate electrode240may be formed to have a “U”-shaped section.

According to some embodiments, the barrier layer230is disposed between the first and second gate electrodes220and240. Owing to the barrier layer230, the first and second gate electrodes220and240are not be in contact with each other or are spaced apart from each other. The barrier layer230can prevent silicon atoms in the second gate electrode240from diffusing into the first gate electrode220, and thus can prevent a metal silicide layer from being formed in the first gate electrode220. In addition, the barrier layer230can prevent n-type impurities, such as phosphorus (P), in the second gate electrode240from diffusing into the first gate electrode220, and thus can prevent undesired materials, such as tungsten phosphide (WP2), from forming in the first gate electrode220. The barrier layer230is a thin film. For example, the barrier layer230has a thickness ranging from about 1 Å to about 50 Å. If the thickness of the barrier layer230is less than 1 Å, silicon atoms in the second gate electrode240can diffuse through the barrier layer230and into the first gate electrode220. If the thickness of the barrier layer230is greater than 50 Å, an electrical resistance between the first and second gate electrodes220and240can increase, which can deteriorate electric characteristics of the gate lines GL. The barrier layer230is formed of or includes a metal oxynitride of a metallic element such as tungsten (W), titanium (Ti), or tantalum (Ta). Here, the metallic element of the first gate electrode220is the same as that in the metal oxynitride of the barrier layer230. For example, the first gate electrode220can be formed of or includes tungsten (W), and the barrier layer230is formed of or includes tungsten oxynitride.

In certain embodiments, the barrier layer230is formed of or includes metal nitrides of a metal such as tungsten (W), titanium (Ti), or tantalum (Ta). Here, the metallic element of the first gate electrode220is the same as that in the metal nitride of the barrier layer230. For example, the first gate electrode220can be formed of tungsten (W), and the barrier layer230is formed of tungsten nitride.

In some embodiments, a work function adjusting layer225may be interposed between the first gate electrode220and the barrier layer230. As shown inFIG. 4, the work function adjusting layer225may be provided to adjust a work function of the gate lines GL. As an example, the work function adjusting layer225may have a work function lower than that of the first gate electrode220. The work function adjusting layer225may have a thickness, which is adjusted in consideration of a work function required for the gate lines GL, or may be doped with a work function adjusting element (e.g., lanthanum (La) or hafnium (Hf)) in consideration of a work function required for the gate lines GL. The work function adjusting layer225may be formed of or include at least one of binary metal nitrides (e.g., titanium nitride (TiN) and tantalum nitride (TaN)), ternary metal nitrides (e.g., titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium silicon nitride (TiSiN), and tantalum silicon nitride (TaSiN)), or metal oxynitrides obtained by oxidizing them.

According to some embodiments, a gate insulating layer210is interposed between the gate lines GL and the active regions ACT and between the gate lines GL and the device isolation layer110. The gate insulating layer210is formed of or includes at least one of an oxide, a nitride, or an oxynitride. However, the material of the gate insulating layer210is not limited thereto, and the gate insulating layer210may include various other insulating materials. Here, a nitrogen concentration of a second portion214of the gate insulating layer210adjacent to the second gate electrode240is greater than a nitrogen concentration of a first portion212of the gate insulating layer210adjacent to the first gate electrode220. For example, the concentration of N+ ions in the second portion214is greater than that in the first portion212. The N+ ions in the second portion214can reduce leakage current through the gate insulating layer210, which can improve the reliability of a semiconductor memory device.

In some embodiments, referring now toFIG. 3, a liner layer260is interposed between the second gate electrode240and the gate insulating layer210. As shown inFIG. 5, the liner layer260covers an inner side surface of the gate insulating layer210and a top surface of the second gate electrode240. The liner layer260extends into a space between the gate insulating layer210and the second gate electrode240. The liner layer260is formed of or includes metal nitride. For example, the liner layer260can be formed of or includes titanium nitride. Hereinafter, a semiconductor memory device in which the liner layer260is not provided will be described.

According to some embodiments, referring back toFIGS. 1, 2A, and 2B, first capping layers250may be provided on the gate lines GL. The first capping layers250are disposed to fill the remaining spaces of the trenches120. A top surface of the first capping layers250is positioned at the same level as the top surface of the substrate100. The first capping layers250are formed of or include at least one of silicon oxide, silicon nitride, or silicon oxynitride. Both side surfaces of each of the first capping layers250are next to the active regions ACT and the device isolation layer110. The gate insulating layers210is interposed between the first capping layers250and the active regions ACT and functions as a buffer layer that reduces stress between the active regions ACT and the first capping layers250. In certain embodiments, the gate insulating layers210do not be extended into gaps between the active regions ACT and the first capping layers250or between the device isolation layer110and the first capping layers250. For example, the uppermost portions of the gate insulating layers210are in contact with side surfaces of the first capping layers250.

According to some embodiments, a first doped region SD1and a second doped region SD2are provided in two of the active regions ACT adjacent to both sides surfaces of the gate lines GL. The first and second doped regions SD1and SD2are formed below the top surface of the substrate100or in the substrate100. The first and second doped regions SD1and SD2have a conductivity type different from that of the substrate100. For example, when the substrate100is p-type, the first and second doped regions SD1and SD2are n-type. The first and second doped regions SD1and SD2can be used as a source or drain region.

According to some embodiments, a first pad310and a second pad320are disposed on the substrate100, and in some embodiments, the first pad310and the second pad320are connected to the first doped region SD1and the second doped region SD2, respectively. The first pad310and the second pad320are formed of or include at least one conductive material, such as doped poly silicon or a metal.

According to some embodiments, a first interlayer insulating layer400is disposed on the first and second pads310and320. The first interlayer insulating layer400is formed of or includes at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

According to some embodiments, bit lines BL are disposed on the first interlayer insulating layer400. The bit lines BL are disposed on the first interlayer insulating layer400and in a second interlayer insulating layer540. The second interlayer insulating layer540is formed of or includes a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. Each of the bit lines BL is connected to the first pad310through a first contact510, which penetrates the first interlayer insulating layer400. The bit lines BL and the first contact510are formed of or include at least one conductive material, such as doped silicon or a metal.

According to some embodiments, second capping layers520are disposed on the bit lines BL, and insulating spacers530are provided that cover side surfaces of the bit lines BL. The second capping layers520and the insulating spacers530are formed of or include at least one of silicon nitride, silicon oxide, or silicon oxynitride.

According to some embodiments, a second contact610is disposed on the substrate100. The second contact610penetrates the first and second interlayer insulating layers400and540and is connected to the second pad320. The second contact610is formed of or includes at least one conductive material, such as doped silicon or a metal.

According to some embodiments, a data storage element connected to the second contact610is disposed on the second interlayer insulating layer540. For example, the data storage element is or includes a capacitor CA that includes a first electrode620, a second electrode640, and a dielectric layer630interposed between the first electrode620and the second electrode640. The first electrode620is shaped like a cylinder with closed bottom. The second electrode640covers the first electrode620. The first electrode620and the second electrode640are formed of or include at least one of doped silicon, a metal, or a metal compound.

According to some embodiments, a supporting layer700is disposed between the second electrode640and the second interlayer insulating layer540. The supporting layer700is disposed on an outer sidewall of the first electrode620, thereby preventing the first electrode620from leaning or falling. The supporting layer700is formed of or includes an insulating material.

For convenience in illustration,FIG. 2Aillustrates an example in which lower portions of the gate lines GL have a rectangular shape, but the inventive concept is not limited thereto. For example, as shown inFIG. 6, a lower region of the trench120may have a “U”-shaped section, and thus, the gate line GL filling the trench120may have a rounded lower portion. In certain embodiments, the gate lines GL may be provided at different depths, according to their positions. As an example, to reduce a length of a channel region that is formed in the active region ACT between the first and second doped regions SD1and SD2, the gate lines GL on the active regions ACT may be formed at a relatively high level. For example, the bottom portions of the gate lines GL in the device isolation layer110may be lower than those on the active regions ACT.

In a semiconductor memory device according to some embodiments of the inventive concept, each of the gate lines GL includes the first gate electrode220, which is located at a low level and has a high work-function, and the second gate electrode240, which is located at a high level and has a low work-function. The second gate electrode240can reduce leakage current, such as gate-induced-drain-leakage (GIDL) current, which can occur in the doped regions SD1or SD2by the gate lines GL.

In addition, according to some embodiments, the barrier layer230can prevent silicon atoms or n-type impurities in the second gate electrode240from diffusing into the first gate electrode220and can prevent a metal silicide or a metal nitride from forming in the first gate electrode220. Accordingly, electric characteristics of the gate lines GL can be improved.

Furthermore, according to some embodiments, the N+ ions in the second portion214of the gate insulating layer210contribute to reducing leakage current into the gate insulating layer210, which can improve reliability of a semiconductor memory device.

FIGS. 7A and 7Bare sectional views that illustrate a semiconductor memory device according to some embodiments of the inventive concept and correspond to a section taken along line I-I′ ofFIG. 1.

According to some embodiments, referring toFIGS. 1, 2B, and 7A, a width W2of the second gate electrode240is greater than a width W1of the first gate electrode220. When measured in a direction normal to a side surface of the trench120, a thickness T1of the first portion212of the gate insulating layer210is greater than a thickness T2of the second portion214of the gate insulating layer210. In detail, when compared with an inner sidewall of the first portion212, an inner sidewall of the second portion214is recessed out toward the sidewall of the trench120. Since the second portion214adjacent to the second gate electrode240is thinner than the first portion212of the gate insulating layer210, a strong electric field can be generated between the second gate electrode240and the doped regions SD1and SD2. Accordingly, electric characteristics between the second gate electrode240and the doped regions SD1and SD2can be improved. The thickness T2of the second portion214is about 40% to 70% of the thickness T1of the first portion212. For example, the thickness T2of the second portion214is about 50% of the thickness T1of the first portion212. If the thickness T2of the second portion214is less than about 40% of the thickness T1of the first portion212, leakage current, such as GIDL current, which is produced in the doped regions SD1and SD2from the second gate electrode240through the gate insulating layer210can increase. If thickness T2of the second portion214is more than about 70% of the thickness T1of the first portion212, a strong electric field is not generated between the second gate electrode240and the doped regions SD1and SD2.

In addition, according to some embodiments, a nitrogen concentration of the second portion214of the gate insulating layer210is greater than that of the first portion212of the gate insulating layer210. For example, the second portion214can have a high N+ ion concentration. The N+ ions in the second portion214reduce leakage current into the gate insulating layer210, which can improve the reliability of a semiconductor memory device.

According to some embodiments, a width of a lower region of the trench120in which the first gate electrode220is disposed is less than a width of an upper region of the trench120in which the second gate electrode240is disposed. The second gate electrode240has a width W2that is greater than a width W1of the first gate electrode220.

In some embodiments, the gate insulating layer210includes the second portion214that is thinner than the first portion212and contains the N+ ions. Accordingly, a strong electric field can be generated between the second gate electrode240and the doped regions SD1and SD2, and owing to the N+ ions in the second portion214, leakage current into the gate insulating layer210can be reduced. In other words, according to some embodiments of the inventive concept, the electric characteristics and reliability of a semiconductor memory device can be improved.

FIG. 7Aillustrates an example, in which the side surface of the second gate electrode240is perpendicular to the top surface of the substrate100. However, the side surface of the second gate electrode240may be at an angle, unlike that shown inFIG. 7A. Referring to FIG.7B, according to an embodiment, a width of the second gate electrode240is greater than the width W2of the first gate electrode220and increases with increasing distance from the substrate100. In detail, an inner side surface214aof the second portion214of the gate insulating layer210is inclined at an angle relative to an inner side surface of the first portion212. Here, the thickness T2of the second portion214decreases with increasing distance from the substrate100. The lowermost portion of the second portion214has the thickest portion of the second portion214, whose thickness is equal to or less than the thickness T1of the first portion212. The uppermost portion of the second portion214is the thinnest portion of the second portion214, whose thickness is greater than 30% of the thickness T1of the first portion212.

According to an embodiment, the width W2of the second gate electrode240increases with increasing distance from the substrate100. A width of the lowermost portion of the second gate electrode240is equal to or greater than the width W1of the first gate electrode220, and a width of the uppermost portion of the second gate electrode240is greater than the width W1of the first gate electrode220.

According to an embodiment, due to the afore-described shape of the gate insulating layer210, a width of the capping layer250increases with increasing distance from the substrate100. The width of the lowermost portion of the capping layer250is equal to the width of the uppermost portion of the second gate electrode240, and the width of the uppermost portion of the capping layer250is greater than the width of the second gate electrode240.

FIG. 7Cis a sectional view that illustrates a semiconductor memory device according to some embodiments of the inventive concept and corresponds to a section taken along line I-I′ ofFIG. 1.

Referring toFIGS. 1, 2, and 7C, according to an embodiment, the gate insulating layer210includes a first sub-insulating layer211. For example, when measured in the direction normal to the side surface of the trench120, the second portion214of the gate insulating layer210is thinner than the first portion212of the gate insulating layer210. The first sub-insulating layer211is provided on an inner side surface of the second portion214. The first sub-insulating layer211is provided in the trench120and covers the inner side surface of the second portion214. In addition, the first sub-insulating layer211encloses the second gate electrode240and the capping layer250. In other words, the first sub-insulating layer211is interposed between the second gate electrode240and the second portion214and between the capping layer250and the second portion214. Here, an inner side surface of the first sub-insulating layer211is coplanar with the inner side surface of the first portion212of the gate insulating layer210. The first sub-insulating layer211is formed of or includes the same material, such as silicon oxide, as the gate insulating layer210. Alternatively, the first sub-insulating layer211is formed of or includes an oxynitride compound, which contains oxygen, nitrogen, and an element, such as silicon (Si), included in the gate insulating layer210. For example, the first sub-insulating layer211is formed of or includes silicon oxynitride (SiON). In certain embodiments, the first sub-insulating layer211further includes an impurity, such as helium (He), hydrogen (H), nitrogen (N), or oxygen (O). A nitrogen concentration of the first sub-insulating layer211is higher than a nitrogen concentration of the first portion212and a nitrogen concentration of the second portion214. High-concentration nitrogen ions, i.e., N+, in the first sub-insulating layer211can reduce a leakage current passing through the gate insulating layer210and the first sub-insulating layer211, and thus, the reliability of the semiconductor memory device can be improved.

Furthermore, according to an embodiment, the first sub-insulating layer211has a better crystal quality than the second portion214of the gate insulating layer210. For example, the number of crystal defects in the first sub-insulating layer211is less than the number of crystal defects in the second portion214. Here, the number of crystal defects refers to the number of crystal defects per unit area. A leakage current from the gate line GL can flow through the crystal defects in the gate insulating layer210, and thus, fewer crystal defects in the first sub-insulating layer211reduces the leakage current from the gate line GL.

FIG. 7Dis a sectional view that illustrates a semiconductor memory device according to some embodiments of the inventive concept and corresponds to a section taken along line I-I′ ofFIG. 1.

Referring toFIGS. 1, 2, and 7D, according to an embodiment, the width W2of the second gate electrode240is greater than the width W of the first gate electrode220, and a width W3of the capping layer250is greater than the width W2of the second gate electrode240. The gate insulating layer210has the first portion212adjacent to the first gate electrode220, the second portion214adjacent to the second gate electrode240, and a third portion216adjacent to the capping layer250. When measured in the direction normal to the side surface of the trench120, the thickness T1of the first portion212of the gate insulating layer210is greater than the thickness T2of the second portion214of the gate insulating layer210, and the thickness T2of the second portion214is greater than a thickness T3of the third portion216. In detail, an inner sidewall of the second portion214is recessed from an inner sidewall of the first portion212toward the outside of the trench120, and an inner sidewall of the third portion216is recessed from the inner sidewall of the second portion214toward the outside of the trench120. The thickness T2of the second portion214is about 70% to 95% of the thickness T1of the first portion212. The thickness T3of the third portion216is about 40% to 70% of the thickness T1of the first portion212.

According to an embodiment, a width of an intermediate region of the trench120, in which the second gate electrode240is disposed, is greater than a width of a lower region of the trench120, in which the first gate electrode220is disposed, and is less than a width of an upper region of the trench120, in which the capping layer250is disposed. The width W2of the second gate electrode240is greater than the width W1of the first gate electrode220and is less than the width W3of the capping layer250.

According to an embodiment, since the second portion214adjacent to the second gate electrode240and the third portion216adjacent to the capping layer250are thinner than the first portion212of the gate insulating layer210, a strong electric field can be generated between the second gate electrode240and the doped regions SD1and SD2. Accordingly, electric characteristics between the second gate electrode240and the doped regions SD1and SD2can be improved.

FIG. 7Eis a sectional view that illustrates a semiconductor memory device according to some embodiments of the inventive concept and corresponds to a section taken along line I-I′ ofFIG. 1.

Referring toFIGS. 1, 2, and 7E, according to an embodiment, the gate insulating layer210includes the first sub-insulating layer211and a second sub-insulating layer213. For example, when measured in the direction normal to the side surface of the trench120, the second portion214of the gate insulating layer210is thinner than the first portion212of the gate insulating layer210, and the third portion216of the gate insulating layer210is thinner than the second portion214of the gate insulating layer210.

According to an embodiment, the first sub-insulating layer211is provided on the inner side surface of the second portion214. The first sub-insulating layer211is provided in the trench120and covers the inner side surface of the second portion214. In addition, the first sub-insulating layer211encloses the second gate electrode240. That is, the first sub-insulating layer211is interposed between the second gate electrode240and the second portion214of the gate insulating layer210. The inner side surface of the first sub-insulating layer211is coplanar with the inner side surface of the first portion212of the gate insulating layer210.

According to an embodiment, the second sub-insulating layer213is provided on an inner side surface of the third portion216. The second sub-insulating layer213is provided in the trench120and covers the inner side surface of the third portion216. In addition, the second sub-insulating layer213encloses the capping layer250. That is, the second sub-insulating layer213is interposed between the capping layer250and the third portion216of the gate insulating layer210. An inner side surface of the second sub-insulating layer213is coplanar with the inner side surface of the first portion212of the gate insulating layer210and the inner side surface of the first sub-insulating layer211.

According to an embodiment, the first sub-insulating layer211and the second sub-insulating layer213are formed of or include an oxynitride compound, which contains oxygen, nitrogen, and an element, such as silicon (Si), included in the gate insulating layer210. For example, the first sub-insulating layer211and the second sub-insulating layer213are formed of or include silicon oxynitride (SiON). In certain embodiments, the first sub-insulating layer211and the second sub-insulating layer213further include an impurity, such as helium (He), hydrogen (H), nitrogen (N), or oxygen (O). A nitrogen concentration of the first sub-insulating layer211is higher than a nitrogen concentration of the second portion214, and a nitrogen concentration of the second sub-insulating layer213is higher than a nitrogen concentration of the third portion216. High-concentration nitrogen ions, i.e., N+, in the first and second sub-insulating layers211and213reduce a leakage current passing through the first and second sub-insulating layers211and213, and thus, the reliability of the semiconductor memory device can be improved.

FIGS. 8A to 14Aare sectional views taken along line I-I′ ofFIG. 1that illustrate a method of fabricating a semiconductor memory device according to some embodiments of the inventive.FIGS. 8B to 14Bare sectional views taken along line II-II′ ofFIG. 1that illustrate a method of fabricating a semiconductor memory device according to some embodiments of the inventive.FIGS. 10C to 12Care enlarged views of portions ‘A’, i.e., a portion of a surface of a first gate electrode, ofFIGS. 10A to 12A.FIG. 13Cis a sectional view illustrating a process of forming a second gate electrode.

According to some embodiments, referring toFIGS. 1, 8A, and 8B, the device isolation layer110is formed in the substrate100that define the active regions ACT. The device isolation layer110includes at least one of a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. The device isolation layer110includes a portion that extends into the substrate100.

According to some embodiments, the second doped regions SD2is formed in the active regions ACT of the substrate100. The second doped regions SD2is formed by an ion implantation process. The second doped region SD2is doped with n-type impurities.

According to some embodiments, referring toFIGS. 1, 9A, and 9B, the trenches120are formed in an upper portion of the substrate100. For example, forming the trenches120includes forming mask patterns M on the substrate100and then etching the substrate100and the device isolation layer110using the mask patterns M as an etch mask. Each of the trenches120is formed to have a line shape extending in the second direction D2. The device isolation layer110and the active regions ACT are exposed through the trenches120. The mask patterns M are removed after the etching process. InFIG. 9A, the trench120is illustrated to have a rectangular section, but the inventive concept is not limited thereto. In the case where the substrate100is etched to form the trench120, a center region of a bottom surface of the trench120may be more easily etched, compared with an edge region, as shown inFIG. 7. Thus, the trench120may be formed to have a bottom surface whose center region is recessed, and a bottom region of the trench120may have a “U”-shaped section. Hereinafter, for convenience in description, the inventive concept will be described with reference to the trench120ofFIG. 9A.

According to some embodiments, referring toFIGS. 1, 10A, and 10B, an insulating layer215is formed on the substrate100and in the trenches120. The insulating layer215may be formed by, for example, a thermal oxidation process, an atomic layer deposition (ALD) process, or a chemical vapor deposition (CVD) process. The insulating layer215is formed to cover the top surface of the substrate100and side and bottom surfaces of the trenches120. The insulating layer215is formed of or includes silicon oxide.

Next, according to some embodiments, the gate lines GL are formed in the trenches120. Each of the gate lines GL includes the first gate electrode220, the barrier layer230, and the second gate electrode240.

According to some embodiments, the first gate electrode220is formed in a lower region of each of the trenches120that are coated with the insulating layer215. For example, a conductive material is deposited on the substrate100. The conductive material is formed to fill the trenches120. The deposition of the conductive material may be, for example, a CVD process. The conductive material includes a metallic material, such as tungsten (W), titanium (Ti), or tantalum (Ta). Thereafter, the deposited conductive material is etched to form the first gate electrode220. The etching process is performed until the first gate electrode220has a desired thickness.

According to some embodiments, referring toFIG. 10C, the first gate electrode220has a polycrystalline structure. The first gate electrode220includes a plurality of grains, and in this case, the first gate electrode220has an uneven top surface, owing to the presence of the grains. For example, the top surface of the first gate electrode220includes a protruding portion P1and an indented portion P2that is lower than the protruding portion P1. The indented portion P2is connected to crystalline defects, such as a grain boundary between the grains, of the first gate electrode220.

Thereafter, as previously described with reference toFIG. 4, the work function adjusting layer225may be formed on the first gate electrode220. For example, a work function adjusting material may be deposited on the substrate100. Here, the work function adjusting material may be formed to fill the trench120. The work function adjusting material may include metal nitrides, such as titanium nitride (TiN) and tantalum nitride (TaN). Next, the deposited work function adjusting material may be etched to form the work function adjusting layer225. In the case where the work function adjusting layer225is formed on the first gate electrode220, the work function adjusting layer225may be formed to have grains, and thus, the work function adjusting layer225may have an uneven top surface, whose shape is determined depending on shapes of the grains. In certain embodiments, a process of forming the work function adjusting layer225may be omitted. The description that follows will refer to an example of the gate lines GL ofFIG. 10Awithout the work function adjusting layer225.

According to some embodiments, referring toFIGS. 1, 11A, and 11B, a preliminary barrier layer235is formed on the first gate electrode220. In detail, a surface treatment process is performed on the top surface of the first gate electrode220. The surface treatment process is an oxidation process. An upper portion of the first gate electrode220is oxidized by the surface treatment process to form the preliminary barrier layer235.

According to some embodiments, referring toFIG. 11C, owing to the uneven top surface of the first gate electrode220, an oxidation thickness of the upper portion of the first gate electrode220is not uniform. For example, the protruding portion P1is easily oxidized, because it has a relatively large exposed area. By contrast, the indented portion P2is not easily oxidized, because it has a relatively small exposed area. Accordingly, the preliminary barrier layer235on the indented portion P2is thinner than the preliminary barrier layer235on the protruding portion P1.

According to some embodiments, referring toFIGS. 1, 12A, and 12B, the barrier layer230is formed on the first gate electrode220. In detail, a surface treatment process is performed on the preliminary barrier layer235. The surface treatment process is a nitrification process. As a result of the surface treatment process, the preliminary barrier layer235is nitrified to form the barrier layer230. An upper portion of the first gate electrode220is partially nitrified during the surface treatment process. Here, the nitrified upper portion of the first gate electrode220constitutes a portion of the barrier layer230.

According to some embodiments, referring toFIG. 12C, the barrier layer230is formed to have a uniform thickness. For example, the nitrification of the preliminary barrier layer235is easily performed on both of the protruding and indented portions P1and P2. As an example, nitrogen atoms easily infiltrate into a grain boundary of the first gate electrode220. Here, the preliminary barrier layer235on the indented portion P2is more effectively nitrified, because it is thinner than that on the protruding portion P1. Accordingly, during nitrification of the preliminary barrier layer235on the protruding portion P1, an upper portion of the first gate electrode220is partially nitrified, and in this case, the barrier layer230is composed of the nitrified portions of the preliminary barrier layer235and the first gate electrode220. In other words, the barrier layer230on the indented portion P2is thickened, and in this case, the barrier layer230has a uniform thickness on the protruding portion P1and the indented portion P2.

In some embodiments, the surface treatment process is performed on a portion of the insulating layer215. For example, an exposed fifth portion219of the insulating layer215that is positioned above the first gate electrode220and the barrier layer230is nitrified during the surface treatment process. Accordingly, the fifth portion219has a N+ ion concentration that is higher than that of a fourth portion217adjacent to the first gate electrode220.

According to some embodiments, referring toFIGS. 1, 13A, and 13B, the second gate electrode240is formed on the barrier layer230. For example, a poly-silicon layer is deposited on the substrate100and the insulating layer215. The poly-silicon layer is formed to fill the trenches120. The poly-silicon layer may be formed by, for example, a CVD process. Thereafter, the deposited poly-silicon layer is etched and doped with n- or p-type impurities to form the second gate electrode240. An amount of impurities, which are doped in the poly silicon layer, may be adjusted in consideration of a work function required for the second gate electrode240. The etching process is performed until the second gate electrode240has a desired thickness. In certain embodiments, the deposited poly silicon layer may be doped with n- or p-type impurities, and then, the poly silicon layer may be etched-back to form the second gate electrode240.

According to some embodiments of the inventive concept, it may be possible to form the barrier layer230having a uniform thickness. In the case where the barrier layer230has a non-uniform thickness, n- or p-type impurities may be diffused into the first gate electrode220through a thin portion of the barrier layer230. By contrast, in some embodiments, during a process of forming the second gate electrode240, n- or p-type impurities may not be diffused into the first gate electrode220. Thus, it may be possible to dope the second gate electrode240with a large amount of n- or p-type impurities, for the work function adjustment, without deterioration or damage of the first gate electrode220. In other words, according to some embodiments of the inventive concept, it may be possible to adjust the work function of the gate lines GL within a relatively large range. This may allow the gate lines GL to have a desired work function that can meet technical requirements for a semiconductor memory device.

In the case where the second gate electrode240including poly silicon is doped with a large amount of impurities, the second gate electrode240may have a reduced strength. In this case, the top surface240aof the second gate electrode240may be recessed, as shown inFIG. 13C, or a center region of the top surface240aof the second gate electrode240may be over-etched during a subsequent etch-back process to be performed after the doping process. As a result, the second gate electrode240may be formed to have a top surface whose section is shaped like a letter “V” or “U”. Hereinafter, the inventive concept will be described in more detail with reference to the second gate electrode240ofFIG. 13A.

As a result of the afore-described process, the gate lines GL are formed in the trenches120. Each gate line GL includes the first gate electrode220, the barrier layer230, and the second gate electrode240.

According to some embodiments, referring toFIGS. 1, 14A, and 14B, the first capping layers250are formed in the trenches120. For example, forming the first capping layers250includes forming a capping layer on the substrate100and performing a planarization process on the capping layer. During the formation of the first capping layers250, at least a portion of the insulating layer215is removed from the top surface of the substrate100. As a result, the gate insulating layer210is formed between the gate lines GL and the active regions ACT or between the gate lines G. and the device isolation layer110. In the case where, as shown inFIG. 13C, the top surface of the second gate electrode240of the gate line GL has a “V”- or “U”-shaped section, a bottom portion of the first capping layer250may have a shape corresponding to the top surface of the second gate electrode240. The first capping layers250are formed of or include at least one of silicon nitride, silicon oxide, or silicon oxynitride. As a result of the etching process, top surfaces of the device isolation layer110and the active regions ACT are exposed.

According to some embodiments, an ion implantation process is performed on the substrate100to form the first doped region SD1in a region of the substrate100between two adjacent gate lines GL. The first doped region SD1has the same conductivity type, such as n-type, as that of the second doped region SD2. The first doped region SD1is formed to be deeper than the second doped region SD2.

In certain embodiments, the liner layer260is formed before forming the second gate electrode240. The liner layer260may be formed by, for example, a CVD process. The liner layer260is formed to conformally cover the insulating layer215. The liner layer260is formed of or includes at least one metallic material or metal nitride material. For example, the liner layer260includes at least one of titanium (Ti), tungsten (W), or nitrides thereof. If the liner layer260is formed, a semiconductor memory device fabricated by a subsequent process has the same structure as that shown inFIG. 5. Hereinafter, embodiments of the inventive concept will be described with reference to an example in which no liner layer260is formed.

According to some embodiments, referring back toFIGS. 1, 2A, and 2B, a conductive layer is formed on the substrate100and is patterned to form the first pad310and the second pad320. The first pad310is connected to the first doped region SD1, and the second pad320is connected to the second doped region SD2. The first pad310and the second pad320are formed of or include at least one of a doped poly-crystalline silicon layer, a doped single-crystalline silicon layer, or a metal layer.

According to some embodiments, the first interlayer insulating layer400is formed on the first and second pads310and320. The first interlayer insulating layer400may be formed by, for example, a CVD process. A portion of the first interlayer insulating layer400is patterned to form contact holes. A conductive material is formed on the first interlayer insulating layer400to fill the contact holes, and then, a capping layer is formed on the conductive material. The capping layer and the conductive material are patterned to form first contacts510in the contact holes, the bit lines BL, and the second capping layers520on the bit lines BL. An insulating spacer layer is conformally deposited on the first interlayer insulating layer400and is anisotropically etched to form insulating spacers530that cover side surfaces of the bit lines BL.

According to some embodiments, the second interlayer insulating layer540is formed on the first interlayer insulating layer400, and then, a planarization process is performed to expose top surfaces of the second capping layers520. Thereafter, the second contact610are formed that penetrate the second interlayer insulating layer540and the first interlayer insulating layer400to be connected to the second pad320. The supporting layer700is formed on the second interlayer insulating layer540. The supporting layer700may be formed by, for example, a CVD process. The first electrodes620are formed that penetrate the supporting layer700, and each of the first electrodes620is connected to the second contact610. The dielectric layer630, which conformally covers the first electrodes620, and the second electrode640, which covers the first electrodes620, are formed that constitute the capacitor CA. A semiconductor memory device according to some embodiments of the inventive concept can be fabricated by the afore-described method.

According to some embodiments, if the barrier layer230does not have a uniform thickness, silicon or n-type impurities can diffuse into the first gate electrode220through a thin portion of the barrier layer230, and electric resistance between the first and second gate electrodes220and240increases at a thick portion of the barrier layer230. By contrast, in a method of fabricating a semiconductor memory device according to some embodiments of the inventive concept, the barrier layer230is formed to have a substantially uniform thickness. Thus, dispersion errors in a process of forming the barrier layer230can be reduced. Furthermore, not only can barrier characteristics of the barrier layer230be improved, but also electric characteristics between the first and second gate electrodes220and240.

FIGS. 15A and 17Aare sectional views taken along line I-I′ ofFIG. 1that illustrate a method of fabricating a semiconductor memory device according to some embodiments of the inventive concept.FIGS. 15B and 17Bare sectional views taken along line II-II′ ofFIG. 1that illustrate a method of fabricating a semiconductor memory device according to some embodiments of the inventive concept.

According to some embodiments, referring toFIGS. 1, 15A, and 15B, the second gate electrode240is formed to be wider than the first gate electrode220. For example, an etching process is performed on the structure ofFIGS. 12A and 12B. As a result of the etching process, the insulating layer215is partially removed. For example, the etching process is performed on the fifth portion219of the insulating layer215, which is located above the first gate electrode220and the barrier layer230. Accordingly, when measured in a direction perpendicular to the side surface of the trench120, the fourth portion217of the insulating layer215is thicker than the fifth portion219of the insulating layer215. An upper width of the trench120measured at a level above the first gate electrode220is greater than a lower width of the trench120at a level of the first gate electrode220.

According to an embodiment, a portion of the insulating layer215removed by the etching process has a worse crystal quality than the remaining portion, such as the fourth and fifth portions217and219, of the insulating layer215. For example, a portion of the insulating layer215may be damaged during the process of forming the first gate electrode220described with reference toFIGS. 10A and 10B. In detail, a conductive material is deposited on the insulating layer215to fill the trench120, and then, the conductive material is etched to form the first gate electrode220. The etching process is performed until the first gate electrode220has a desired thickness, and in this case, a portion of the insulating layer215, which is located above the top surface of the first gate electrode220, may be damaged by the etching process. Accordingly, many crystal defects may be created in the portion of the insulating layer215. The crystal defects can lead to an undesired current flow. For example, in the final structure of the semiconductor memory device, the crystal defects can serve as a current path of a leakage current leaked from the gate line GL.

According to some embodiments, the portion of the insulating layer215having the bad crystal quality is removed, and thus, a portion of the insulating layer215that serves as a current path of a leakage current is removed. Accordingly, the gate insulating layer210with reduced crystal defects is formed, and the leakage current from the gate line GL is reduced.

According to some embodiments, referring toFIGS. 1, 16A, and 16B, the second gate electrode240is formed on the barrier layer230. For example, forming the second gate electrode240includes depositing a poly-silicon layer on the barrier layer230and doping the poly-silicon layer with n-type impurities. The second gate electrode240in an upper region of the trench120is wider than the first gate electrode220in a lower region of the trench120.

Thereafter, according to some embodiments, a process previously described with reference toFIGS. 14A, 14B, 2A, and 2Bis performed on the structure ofFIGS. 16A and 16Bto form a semiconductor memory device ofFIG. 7A.

FIGS. 15A and 15Billustrate an example, in which the side surface of the second gate electrode240is formed to be perpendicular to the top surface of the substrate100. However, embodiments of the inventive concept are not limited to this example, and in other embodiments, the side surface of the second gate electrode240is formed at an angle to the top surface of the substrate100, unlike that shown inFIGS. 15A and 15B.

According to some embodiments, referring toFIGS. 1, 17A, and 17B, the second gate electrode240is wider than the first gate electrode220. For example, an etching process is performed on the structure ofFIGS. 12A and 12B. As a result of the etching process, the insulating layer215is partially removed. For example, the etching process is performed on the fifth portion219of the insulating layer215, which is located above the first gate electrode220and the barrier layer230. Here, due to process variations or errors in the etching process, an exposed portion of the insulating layer215, which is located above the first gate electrode220, may be non-uniformly etched, and thus, there may be a spatial variation in the etching depth. The etching depth refers to a depth in a direction from an inner side surface of the insulating layer215that faces the trench120toward the outside of the trench120. For example, the etching depth of the portion of the insulating layer215decreases with decreasing distance from the bottom surface of the trench120. This can result from the etching solution used in the etching process not completely reaching a bottom region of the trench120or from other causes. Accordingly, an inner side surface of the fifth portion219of the insulating layer215is formed to be inclined at an angle to a top surface of the barrier layer230. A thickness of the fifth portion219of the insulating layer215decreases with increasing distance from the substrate100.

Thereafter, according to an embodiment, the process previously described with reference toFIGS. 13A, 13B, 14A, 14B, 2A, and 2Bis performed on the structure ofFIGS. 17A and 17Bto form the semiconductor memory device ofFIG. 7B.

FIGS. 18A and 19Aare sectional views taken along line I-I′ ofFIG. 1that illustrate a method of fabricating a semiconductor memory device according to some embodiments of the inventive concept.FIGS. 18B and 19Bare sectional views taken along line II-II′ ofFIG. 1that illustrate a method of fabricating a semiconductor memory device according to some embodiments of the inventive concept.

Referring toFIGS. 1, 18A, and 18B, according to an embodiment, the first sub-insulating layer211is formed on the insulating layer215. The first sub-insulating layer211is formed on an inner side surface of the fifth portion219of the insulating layer215.

According to an embodiment, the first sub-insulating layer211is formed by a deposition process. For example, one of a thermal oxidation process, an atomic layer deposition (ALD) process, or a chemical vapor deposition (CVD) process may be performed on the structure ofFIGS. 12A and 12Bto form the first sub-insulating layer211. The first sub-insulating layer211covers the top surface of the barrier layer230and the inner side surface of the fifth portion219of the insulating layer215, and then, an anisotropic etching process on the first sub-insulating layer211is performed to remove a portion of the first sub-insulating layer211located on the barrier layer230. The first sub-insulating layer211is formed of or includes an oxynitride compound, which contains oxygen, nitrogen, and an element, such as silicon (Si), included in the insulating layer215. For example, the first sub-insulating layer211is formed of or includes silicon oxynitride (SiON).

In certain embodiments, the first sub-insulating layer211is formed by a curing process. For example, in the structure ofFIGS. 12A and 12B, the curing process is performed on an exposed portion of the insulating layer215located above the barrier layer230to form the first sub-insulating layer211. Here, the exposed portion of the insulating layer215on which the curing process is performed has a worse crystal quality than the remaining portion of the insulating layer215. For example, the exposed portion of the insulating layer215may be damaged during the process of forming the first gate electrode220described with reference toFIGS. 10A and 10B. In this case, the exposed portion of the insulating layer215located above the top surface of the first gate electrode220may be damaged by an etching process, which is performed to form the first gate electrode220. Accordingly, many crystal defects may be created in the damaged portion of the insulating layer215. The curing process includes injecting a curing element into the exposed portion of the insulating layer215. Here, the curing element may be an element in a material that constitutes the insulating layer215. As an example, when the insulating layer215includes silicon oxide, the curing element is oxygen (O). The curing element may include one of various elements, such as helium (He), hydrogen (H), nitrogen (N), or oxygen (O), depending on the materials that constitute the insulating layer215. One of O3HF, helium, hydrogen, nitrogen, oxygen, ozone, or hydroxide gases may be used as a reaction gas in the curing process. As a result of the curing process, crystal defects in the damaged portion of the insulating layer215are cured. For example, the curing element may be injected into the crystal defects of the insulating layer215to improve the crystal quality of the insulating layer215. The portion of the insulating layer215on which the curing process is performed constitutes the first sub-insulating layer211.

Referring toFIGS. 19A and 19B, according to an embodiment, the second gate electrode240is formed on the barrier layer230. For example, a poly-silicon layer is deposited on the substrate100and the insulating layer215. The poly-silicon layer fills the trenches120. The poly-silicon layer may be formed by, for example, a CVD process. Thereafter, the deposited poly-silicon layer is etched and doped with n- or p-type impurities to form the second gate electrode240. The etching process is performed until the second gate electrode240has a desired thickness.

Thereafter, according to an embodiment, the first capping layers250are formed in the trench120. For example, the formation of the first capping layers250includes forming a capping layer on the substrate100and performing a planarization process on the capping layer. Here, a portion of the first sub-insulating layer211and a portion of the insulating layer215that cover the top surface of the substrate100are removed together, after forming the first capping layer250. This process may be the same as or similar to the process described with reference toFIGS. 14A and 148.

Thereafter, according to some embodiments, the process previously described with reference toFIGS. 14A, 14B, 2A, and 2Bis performed on the structure ofFIGS. 19A and 19Bto form the semiconductor memory device ofFIG. 7C.

FIGS. 20A and 20Bare sectional views that illustrate a method of fabricating a semiconductor memory device according to some embodiments of the inventive concept. In detail,FIG. 20Acorresponds to a sectional view taken line I-I′ ofFIG. 1, andFIG. 20Bcorresponds to a sectional view taken line II-II′ ofFIG. 1.

Referring toFIGS. 1, 20A, and 20B, according to an embodiment, the capping layer250is formed to be wider than the second gate electrode240. An etching process is performed on the structure ofFIGS. 16A and 16B. As a result of the etching process, the insulating layer215is partially removed. For example, the etching process is performed on a sixth portion218of the insulating layer215located above the second gate electrode240. Accordingly, when measured in the direction perpendicular to the side surface of the trench120, the fifth portion219of the insulating layer215is thicker than the sixth portion218of the insulating layer215. A width of an upper region of the trench120, which is located above the first gate electrode220, is greater than a width of a lower region of the trench120, in which the first gate electrode220is disposed, and is greater than a width of an intermediate region of the trench120, in which the second gate electrode240is disposed.

According to an embodiment, a portion of the insulating layer215removed by the etching process may have a worse crystal quality than the remaining portion, such as the fourth to sixth portions217,219, and218, of the insulating layer215. For example, a portion of the insulating layer215may be damaged during the process of forming the second gate electrode240described with reference toFIGS. 13A and 13B. In detail, a second gate electrode material, such as poly silicon, etc., is deposited on the barrier layer230to fill the trench120, and an etching process is performed on the second gate electrode material to form the second gate electrode240. The etching process is performed until the second gate electrode240has a desired thickness, and in this case, a portion of the insulating layer215located above the top surface of the first gate electrode220may be damaged by the etching process. Accordingly, many crystal defects may be created in the damaged portion of the insulating layer215. The crystal defects can lead to an undesired current flow. For example, in the final structure of the semiconductor memory device, the crystal defects can serve as a current path of a leakage current leaked from the gate line GL.

According to some embodiments, the bad crystal quality portion of the insulating layer215is removed, and thus, a portion of the insulating layer215that serves as a current path of a leakage current is removed. Accordingly, the gate insulating layer210with reduced crystal defects can be formed, and a leakage current from the gate line GL can be reduced.

Thereafter, according to some embodiments, the process previously described with reference toFIGS. 14A, 14B, 2A, and 2Bis performed on the structure ofFIGS. 20A and 201Bto form the semiconductor memory device ofFIG. 7D.

FIGS. 21A and 21Bare sectional views that illustrate a method of fabricating a semiconductor memory device according to some embodiments of the inventive concept. In detail,FIG. 21Acorresponds to a sectional view taken line I-I′ ofFIG. 1, andFIG. 21Bcorresponds to a sectional view taken line II-II′ ofFIG. 1.

According to an embodiment, the second sub-insulating layer213is formed on the insulating layer215. The second sub-insulating layer213is formed on an inner side surface of the sixth portion218of the insulating layer215.

Referring toFIGS. 1, 21A, and 21B, according to an embodiment, the first sub-insulating layer211is formed by a deposition process. For example, the process described with reference toFIGS. 20A and 20Bis performed on the structure ofFIGS. 19A and 19Bto form the capping layer250, which is wider than the second gate electrode240. For example, an etching process is performed to remove a portion of the insulating layer215. For example, the etching process is performed on the sixth portion218of the insulating layer215located above the second gate electrode240. Accordingly, when measured in the direction perpendicular to the side surface of the trench120, the fifth portion219of the insulating layer215is thicker than the sixth portion218of the insulating layer215.

According to an embodiment, one of a thermal oxidation process, an atomic layer deposition (ALD) process, or a chemical vapor deposition (CVD) process may be performed on the insulating layer215to form the second sub-insulating layer213. The second sub-insulating layer213is formed to cover the top surface of the second gate electrode240and the inner side surface of the sixth portion218of the insulating layer215, and then, an anisotropic etching process on the second sub-insulating layer213is performed to remove a portion of the second sub-insulating layer213located on the second gate electrode240. The second sub-insulating layer213is formed of or includes an oxynitride compound, which contains oxygen, nitrogen, and an element, such as silicon (Si), included in the insulating layer215. For example, the second sub-insulating layer213is formed of or includes silicon oxynitride (SiON).

In certain embodiments, the second sub-insulating layer213is formed by a curing process. For example, in the structure ofFIGS. 19A and 19B, the curing process is performed on an exposed portion of the insulating layer215located above the second gate electrode240to form the second sub-insulating layer213. Here, the exposed portion of the insulating layer215on which the curing process is performed has a worse crystal quality than the remaining portion of the insulating layer215. For example, the exposed portion of the insulating layer215may be damaged during the process of forming the second gate electrode240described with reference toFIGS. 13A and 13B. In this case, the exposed portion of the insulating layer215located above the top surface of the second gate electrode240may be damaged by the etching process performed to form the second gate electrode240. Accordingly, many crystal defects may be created in the damaged portion of the insulating layer215. The curing process includes injecting a curing element into the exposed portion of the insulating layer215. Here, the curing element is an element in a material that constitutes the insulating layer215. As an example, when the insulating layer215includes silicon oxide, the curing element is oxygen (O). The curing element may include one of various elements, such as helium (He), hydrogen (H), nitrogen (N), or oxygen (O), depending on the material that constitutes the insulating layer215. One of O3HF, helium, hydrogen, nitrogen, oxygen, ozone, or hydroxide gases may be used as a reaction gas in the curing process. As a result of the curing process, the crystal defects in the damaged portion of the insulating layer215can be cured. For example, the curing element is injected in the crystal defect of the insulating layer215to improve the crystal quality of the insulating layer215. The portion of the insulating layer215on which the curing process is performed constitutes the second sub-insulating layer213.

Thereafter, according to some embodiments, the process previously described with reference toFIGS. 14A, 14B, 2A, and 2Bis performed on the structure ofFIGS. 21A and 21Bto form the semiconductor memory device ofFIG. 7E.

According to some embodiments of the inventive concept, a semiconductor memory device may be configured such that leakage current in a doped region, such as gate-induced-drain-leakage (GIDL) current, is suppressed.

In addition, according to some embodiments of the inventive concept, a barrier layer is provided to prevent silicon or n-type impurities in a second gate electrode from diffusing into a first gate electrode and thereby to prevent a metal silicide layer or a metal nitride layer from forming. Accordingly, electric characteristics of gate lines can be improved.

Furthermore, according to some embodiments of the inventive concept, leakage current into the gate insulating layer can be reduced, which can improve the reliability of a semiconductor memory device.

In a method of fabricating a semiconductor memory device according to some embodiments of the inventive concept, the barrier layer can be formed to have a substantially uniform thickness. Accordingly, dispersion errors in a process of forming the barrier layer can be reduced, which can improve not only barrier characteristics of the barrier layer but also electric characteristics between the first and second gate electrodes.