Semiconductor device and method of forming through-silicon-via with sacrificial layer

A semiconductor device can be formed by first providing a semiconductor wafer, and forming a conductive via into the semiconductor wafer. A portion of the semiconductor wafer can be removed so that the conductive via extends above a surface of the semiconductor wafer. A first insulating layer can be formed over the surface of the semiconductor wafer and the conductive via, followed by a second insulating layer, the second insulating layer having a different material composition than the first insulating layer. Portions of the insulating layers can be removed to expose the conductive via.

TECHNICAL FIELD

The present disclosure relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming TSV with sacrificial material.

BACKGROUND

Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly can refer to both a single semiconductor device and multiple semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

A conventional semiconductor wafer may contain conductive through silicon vias (TSV). A plurality of vias is formed through the semiconductor wafer. The vias are filled with conductive material to form the conductive TSV. A portion of the back surface of the semiconductor wafer is removed by chemical mechanical polishing (CMP) to expose a portion of the side surface of the conductive TSV. CMP is an expensive manufacturing process. Alternatively, a portion of the back surface of the semiconductor wafer is removed by a photolithographic etching process with a1xstepper to expose a portion of the side surface of the conductive TSV. The1xstepper typically cannot provide sufficient overlay margin for the photolithographic and etching process.

SUMMARY

System and methods of forming TSV in semiconductor devices using sacrificial materials are disclosed. In one embodiment, a method includes: (a) providing a semiconductor wafer; (b) forming a conductive via into the semiconductor wafer; (c) removing a portion of the semiconductor wafer so the conductive via extends above a surface of the semiconductor wafer; (d) forming a first insulating layer over the surface of the semiconductor wafer and the conductive via; (e) forming a second insulating layer over the first insulating layer, the second insulating layer having a different material composition than the first insulating layer; and (f) removing a portion of the second insulating layer and a portion of the first insulating layer to expose the conductive via.

In one embodiment, the forming step (e) includes conformally forming the second insulating layer over the first insulating layer. In another embodiment, the forming step (e) includes non-conformally forming the second insulating layer over the first insulating layer. In one embodiment, the removing step (f) includes complete removal of the second insulating layer.

In one embodiment, the first insulating layer includes silicon nitride and the second insulating layer includes at least one of silicon oxide, silicon dioxide, silicon oxynitride and silicon carbon nitride. In another embodiment, the first insulating layer includes at least one of silicon oxide and silicon dioxide, and the second insulating layer includes at least one of silicon nitride, silicon oxynitride and silicon carbon nitride. In some embodiments, the thickness of the second insulating layer is in the range of from about 0.5 micron to about 5 microns.

In one embodiment, a method of forming TSV in semiconductor devices using sacrificial materials includes: (a) providing a semiconductor wafer; (b) forming a conductive via into the semiconductor wafer with a portion of the conductive via extending above a surface of the semiconductor wafer; (c) forming a plurality of insulating layers over the surface of the semiconductor wafer and the conductive via; and (d) removing a portion of the plurality of insulating layers to expose the conductive via.

In one embodiment, the forming step (c) includes: forming a first insulating layer over the surface of the semiconductor wafer and the conductive via; and forming a second insulating layer over the first insulating layer, the second insulating layer having a different material composition than the first insulating layer.

In another embodiment, the removing step (d) includes: removing a portion of the second insulating layer; and removing a portion of the first insulating layer, the two removing steps capable of exposing the conductive via.

In one embodiment, the first insulating layer includes silicon nitride and the second insulating layer includes at least one of silicon oxide, silicon dioxide, silicon oxynitride and silicon carbon nitride. In another embodiment, the first insulating layer includes at least one of silicon oxide and silicon dioxide, and the second insulating layer includes at least one of silicon nitride, silicon oxynitride and silicon carbon nitride. In some embodiments, the thickness of the second insulating layer is in the range of from about 0.5 micron to about 5 microns.

In one embodiment, the second insulating layer is conformally formed over the first insulating layer. In another embodiment, the second insulating layer is non-conformally formed over the first insulating layer.

In one embodiment, a method of forming TSV in semiconductor devices using sacrificial materials includes: (a) providing a semiconductor wafer; (b) forming a conductive via into the semiconductor wafer; (c) removing a portion of the semiconductor wafer so the conductive via extends above a surface of the semiconductor wafer; (d) forming a first insulating layer over the surface of the semiconductor wafer and the conductive via, the first insulating layer being silicon nitride; (e) forming a second insulating layer over the first insulating layer, the second insulating layer being at least one of silicon oxide, silicon dioxide, silicon oxynitride and silicon carbon nitride; and (f) removing a portion of the second insulating layer and a portion of the first insulating layer to expose the conductive via.

In one embodiment, the forming step (e) includes conformally forming the second insulating layer over the first insulating layer. In another embodiment, the forming step (e) includes non-conformally forming the second insulating layer over the first insulating layer. In yet another embodiment, the removing step (f) includes complete removal of the second insulating layer. In some embodiments, the thickness of the second insulating layer is in the range of from about 0.5 micron to about 5 microns.

Other variations, embodiments and features of the present disclosure will become evident from the following detailed description, drawings and claims.

DETAILED DESCRIPTION OF THE DISCLOSURE

It will be appreciated by those of ordinary skill in the art that the embodiments disclosed herein can be embodied in other specific forms without departing from the spirit or essential character thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive.

The present disclosure is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the disclosure is described in terms of the best mode for achieving the disclosure's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. In one embodiment, the portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. In another embodiment, the portion of the photoresist pattern not subjected to light, i.e., the negative photoresist, is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

Patterning is the basic operation by which portions of the top layers on the semiconductor wafer surface are removed. Portions of the semiconductor wafer can be removed using photolithography, photomasking, masking, oxide or metal removal, photography and stenciling, and microlithography. Photolithography includes forming a pattern in reticles or a photomask and transferring the pattern into the surface layers of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of the semiconductor wafer in a two-step process. First, the pattern on the reticle or masks is transferred into a layer of photoresist. Photoresist is a light-sensitive material that undergoes changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist occurs as either negative-acting photoresist or positive-acting photoresist. Second, the photoresist layer is transferred into the wafer surface. The transfer occurs when etching removes the portion of the top layers of semiconductor wafer not covered by the photoresist. The chemistry of photoresists is such that the photoresist remains substantially intact and resists removal by chemical etching solutions while the portion of the top layers of the semiconductor wafer not covered by the photoresist is removed. The process of forming, exposing, and removing the photoresist, as well as the process of removing a portion of the semiconductor wafer can be modified according to the particular resist used and the desired results.

In negative-acting photoresists, photoresist is exposed to light and is changed from a soluble condition to an insoluble condition in a process known as polymerization. In polymerization, unpolymerized material is exposed to a light or energy source and polymers form a cross-linked material that is etch-resistant. In most negative resists, the polymers are polyisopremes. Removing the soluble portions (i.e. the portions not exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the opaque pattern on the reticle. A mask whose pattern exists in the opaque regions is called a clear-field mask.

In positive-acting photoresists, photoresist is exposed to light and is changed from relatively nonsoluble condition to much more soluble condition in a process known as photosolubilization. In photosolubilization, the relatively insoluble resist is exposed to the proper light energy and is converted to a more soluble state. The photosolubilized part of the resist can be removed by a solvent in the development process. The basic positive photoresist polymer is the phenol-formaldehyde polymer, also called the phenol-formaldehyde novolak resin. Removing the soluble portions (i.e. the portions exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the transparent pattern on the reticle. A mask whose pattern exists in the transparent regions is called a dark-field mask.

After removal of the top portion of the semiconductor wafer not covered by the photoresist, the remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

FIG. 1illustrates electronic device50having a chip carrier substrate or printed circuit board (PCB)52with a plurality of semiconductor packages mounted on its surface. Electronic device50can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. The different types of semiconductor packages are shown inFIG. 1for purposes of illustration.

Electronic device50can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device50can be a subcomponent of a larger system. For example, electronic device50can be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, electronic device50can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

For the purpose of illustration, several types of first level packaging, including bond wire package56and flipchip58, are shown on PCB52. Additionally, several types of second level packaging, including ball grid array (BGA)60, bump chip carrier (BCC)62, dual in-line package (DIP)64, land grid array (LGA)66, multi-chip module (MCM)68, quad flat non-leaded package (QFN)70, and quad flat package72, are shown mounted on PCB52. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB52. In some embodiments, electronic device50includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

FIGS. 2a-2cshow exemplary semiconductor packages.FIG. 2aillustrates further detail of DIP64mounted on PCB52. Semiconductor die74includes an active region containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and are electrically interconnected according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of semiconductor die74. Contact pads76are one or more layers of conductive material, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and are electrically connected to the circuit elements formed within semiconductor die74. During assembly of DIP64, semiconductor die74is mounted to an intermediate carrier78using a gold-silicon eutectic layer or adhesive material such as thermal epoxy or epoxy resin. The package body includes an insulative packaging material such as polymer or ceramic. Conductor leads80and bond wires82provide electrical interconnect between semiconductor die74and PCB52. Encapsulant84is deposited over the package for environmental protection by preventing moisture and particles from entering the package and contaminating semiconductor die74or bond wires82.

FIG. 2billustrates further detail of BCC62mounted on PCB52. Semiconductor die88is mounted over carrier90using an underfill or epoxy-resin adhesive material92. Bond wires94provide first level packaging interconnect between contact pads96and98. Molding compound or encapsulant100is deposited over semiconductor die88and bond wires94to provide physical support and electrical isolation for the device. Contact pads102are formed over a surface of PCB52using a suitable metal deposition process such as electrolytic plating or electroless plating to prevent oxidation. Contact pads102are electrically connected to one or more conductive signal traces54in PCB52. Bumps104are formed between contact pads98of BCC62and contact pads102of PCB52.

InFIG. 2c, semiconductor die58is mounted face down to intermediate carrier106with a flipchip style first level packaging. Active region108of semiconductor die58contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within active region108. Semiconductor die58is electrically and mechanically connected to carrier106through bumps110.

BGA60is electrically and mechanically connected to PCB52with a BGA style second level packaging using bumps112. Semiconductor die58is electrically connected to conductive signal traces54in PCB52through bumps110, signal lines114, and bumps112. A molding compound or encapsulant116is deposited over semiconductor die58and carrier106to provide physical support and electrical isolation for the device. The flipchip semiconductor device provides a short electrical conduction path from the active devices on semiconductor die58to conduction tracks on PCB52in order to reduce signal propagation distance, lower capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die58can be mechanically and electrically connected directly to PCB52using flipchip style first level packaging without intermediate carrier106.

FIGS. 3a-3millustrate, in relation toFIGS. 1 and 2a-2c, a process of forming conductive TSV through a semiconductor wafer using sacrificial layer, end point detection (EPD), and chemical mechanical polishing (CMP) process.FIG. 3ashows a semiconductor wafer120with a base substrate material122, such as silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components124is formed on wafer120separated by a non-active, inter-die wafer area or saw street126as described above. Saw street126provides cutting areas to singulate semiconductor wafer120into individual semiconductor die124.

FIG. 3bshows a cross-sectional view of a portion of semiconductor wafer120. Each semiconductor die124has a back surface128and active surface130containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface130to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die124may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing.

InFIG. 3c, a plurality of blind vias133is formed into active surface130and partially but not completely through semiconductor wafer120using mechanical drilling, laser drilling, or deep reactive ion etching (DRIE).

An electrically conductive layer136is formed over insulating layer134within vias133using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer136can be one or more layers of Ni, tantalum nitride (TaN), nickel vanadium (NiV), platinum (Pt), palladium (Pd), chromium copper (CrCu), or other suitable barrier material.

InFIG. 3e, blind vias133are filled with Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), poly-silicon, or other suitable electrically conductive material using electrolytic plating, electroless plating process, or other suitable metal deposition process to form z-direction conductive TSV138lined with insulating layer134and conductive layer136and embedded within semiconductor wafer120. In one embodiment, conductive layer136operates as a barrier layer to inhibit diffusion of conductive TSV138, e.g. Cu, into insulating layer134and base substrate material122. Conductive TSV138are electrically connected to the circuits on active surface130. A portion of active surface130of semiconductor die124is optionally removed by grinder140or CMP to planarize the surface and expose conductive TSV138.

InFIG. 3f, an electrically conductive bump material is deposited over conductive TSV138using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive TSV138using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps142. In some applications, bumps142are reflowed a second time to improve electrical contact to conductive TSV138. An optional under bump metallization (UBM) layer can be disposed between bumps142and conductive TSV138. Bumps142can also be compression bonded to conductive TSV138. Bumps142represent one type of interconnect structure that can be formed over conductive TSV138. The interconnect structure can also use stud bump, micro bump, or other electrical interconnect.

FIG. 3gshows a temporary substrate or carrier144containing sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. An interface layer or double-sided tape146is formed over carrier144as a temporary adhesive bonding film, etch-stop layer, or thermal release layer. Semiconductor wafer120is inverted, positioned over, and mounted to interface layer146over carrier144with active surface130and bumps142oriented toward the carrier.FIG. 3hshows semiconductor wafer120mounted to interface layer146over carrier144.

Semiconductor wafer120and carrier144are placed in a chase mold. A mold underfill (MUF) material148in a liquid state is injected into the chase mold between semiconductor wafer120and carrier144. MUF material148can be an encapsulant, molding compound, or polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. MUF material148is cured.FIG. 3ishows MUF material148disposed between semiconductor wafer120and carrier144.

InFIG. 3j, a portion of back surface128is removed by a combination of backgrinding, CMP, and/or etching processes to expose conductive TSV138above surface150of semiconductor wafer120. Conductive TSV138remains lined with insulating layer134and conductive layer136and extending above surface150of semiconductor wafer120.

An electrically conductive layer151is formed over insulating layer134, conductive layer136, and conductive TSV138using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer151can be one or more layers of titanium tungsten (TiW), titanium copper (TiCu), titanium tungsten copper (TiWCu), tantalum nitrogen copper (TaNCu), or other suitable material. In one embodiment, conductive layer151operates as a seed layer for electrical interconnect to external devices. Conductive layer151can be formed prior to etching surface128to extend conductive TSV138above surface150.

InFIG. 3l, another insulating layer162can be conformally applied over the previous insulating or dielectric layer152. In another embodiment, the insulating layer162can also be non-conformally applied over the insulating or dielectric layer152. The insulating layer162can be formed using the same material and in the same manner as that of the insulating or dielectric layer152. In addition to covering the dielectric layer152, the insulating layer162can also cover the surface150of the semiconductor wafer120, insulating layer134, and conductive layer151. In some instances, the insulating layer162can follow the contour of the dielectric layer152, the surface150of the semiconductor wafer120, the insulating layer134, and the conductive layer151.

InFIG. 3m, portions of the dielectric layer152as well as the insulating layer162can be removed via a chemical mechanical polishing (CMP) process similar to that described above. In these instances, the CMP process can remove portions of the insulating layer162, the entire insulating layer162, portions of the dielectric layer152, or combinations or variations thereof. Because both the dielectric layer152and the insulating layer162are shielding or passivation layers, they need not be completely removed. In operation, CMP is able to planarize the contoured or convoluted surface and expose the conductive TSV138by removing, chemically and mechanically, portions of the two layers152,162. In other embodiments, other etching or removal processes may be incorporated. The planarization and removal of the contoured layers152,162subsequently allows additional processing steps to be carried out to the conductive TSV138and the rest of the semiconductor wafer120, including without limitation additional stacking of interconnects or integrating additional semiconductor devices (not shown).

FIGS. 4a-4dis a process flow of forming a conductive TSV using a sacrificial layer according to another embodiment of the present disclosure. TSV technology can offer high connectivity and low parasitic between semiconductor devices via 3D integration, as the demand for higher performance, small size, and higher density of electronic devices continue to drive the development of such integration where different functional devices are merged into a single package. One of the challenges of TSV processing is to reveal the conductive via (e.g., copper via) at post TSV process and chemical mechanical polishing (CMP) is one of the removal processes for doing so. Challenges with CMP include the difficulty of detecting end point (e.g., when to stop etching or polishing) when there is little discerning difference in the passivation layers/materials. Under-polishing can render unopen TSV and uneven TSV surface, while over-polishing can cause too little passivation layer to remain resulting in leakage issues.

In one embodiment, the present disclosure provides a method of providing clear EPD for CMP by adding a sacrificial layer that is able to deliver signal differences during CMP. The processing steps as shown inFIGS. 4a-4dis one example of a package that is ready for backside grinding and CMP processes.

A method of making the semiconductor device starts by providing a semiconductor wafer404as shown inFIG. 4a. The semiconductor wafer404can be a silicon wafer coupled to a carrier402using an underfill material406similar to the process described above. A plurality of TSV or conductive vias410(e.g., copper vias) can be formed into the semiconductor wafer404, each conductive via410having a corresponding conductive bump408(e.g., solder or copper bump). An insulating layer412such as liner oxide can be formed about each conductive via410. As can be appreciated by one skilled in the art, all of these steps can be carried out using processes and technologies described above, the components having the same or similar material properties.

FIG. 4bshows the package ofFIG. 4awith a portion of the semiconductor wafer404removed so the conductive vias410extends above a surface of the semiconductor wafer404(e.g., protruding copper vias). Removal of portions of the semiconductor wafer404can be accomplished by suitable silicon etching processes as understood by one skilled in the art. A first dielectric or insulating layer414can be formed over the surface of the semiconductor wafer404and the conductive vias410, the dielectric or insulating layer414being formed via suitable coating or deposition processes, among others. In this instance, the dielectric or first insulating layer414is able to completely cover the conductive vias410and any portion that extends above the surface of the semiconductor wafer404. Similarly, the dielectric or first insulating layer414is able to completely cover the surface of the semiconductor wafer404.

FIG. 4cshows the package ofFIG. 4bwith a second dielectric or insulating layer416being formed over the first dielectric or insulating layer414, the second dielectric or insulating layer416having a different material composition than the first dielectric or insulating layer414. In one embodiment, the thickness of the second dielectric or insulating layer416can be in the range of from about 0.5 micron to about 5 microns. In some embodiments, the thickness of the second dielectric or insulating layer416can be less than 0.5 micron or greater than 5 microns. In other embodiments, the thickness of the second dielectric or insulating layer416can be about 1 micron, or about 1.5 microns, or about 2 microns, or about 2.5 microns, or about 3 microns, or about 3.5 microns, or about 4 microns, or about 4.5 microns.

The thickness of the second dielectric or insulating layer416can be modified as necessary depending on the amount of protrusion of the conductive vias410. For example, the second dielectric or insulating layer416can be greater than 5 microns if the amount of protrusion of the conductive vias410is large, while little to minimal protrusion of the conductive vias410may mean that the second dielectric or insulating layer416can be 0.5 micron or less. The greater the amount of protrusion the better process margin there can be for this backside via or conductive via410removal process. The addition of the second insulating layer416also means that higher protruding conductive vias410can be supported with reduced breakage concerns.

In one embodiment, the second insulating layer416can be conformally formed over the first insulating layer414. Conformal coating can be defined as coverage that conforms to virtually any shape including crevices, points, sharp edges, and flat, exposed surfaces. In another embodiment, the second insulating layer416need not be conformally formed over the first insulating layer414. Examples of the different types of coverage or coating will be better illustrated in subsequent figures.

FIG. 4dshows the package ofFIG. 4cwhere portions of the second insulating layer416as well as portions of the first insulating layer414have been removed to expose the conductive vias410. In this embodiment, the removal step includes the complete removal of the second insulating layer416. Similar to above, the removal step can be accomplished via a CMP process. In operation, the second insulating layer416is similar to that of a sacrificial layer where this layer and its material composition is sacrificed to facilitate EPD of the CMP process. The CMP process is able to planarize or remove any amount of protrusion of the conductive vias410such that the upper surface of the package is substantially planar or flat across the entire width of the semiconductor wafer404.

In one embodiment, the first insulating layer414includes silicon nitride while the second insulating layer416includes at least one of silicon oxide, silicon dioxide, silicon oxynitride and silicon carbon nitride. In an alternative embodiment, the first insulating layer414includes at least one of silicon oxide and silicon dioxide, while the second insulating layer416includes at least one of silicon nitride, silicon oxynitride and silicon carbon nitride.

CMP end point detection (EPD) techniques can be via optical detection or motor current (e.g. torque) detection, or combination of both. For optical detection, laser or monochromatic light intensity or reflectance changes when different material is emitted. For example, silicon oxide may have one reflectance value while silicon nitride many have another reflectance value. Different dielectric or insulating materials would have different values. In the alternative, optical detection may utilize multi-wavelength white spectrum light, which changes according to layer thickness. For motor current detection, the current of the motor can change due to the motor load as the CMP process encounters a different material. In other words, different materials (e.g., silicon oxide, silicon nitride) may polish at different rates and require different amount of current depending on the motor load. It will be appreciated by one skilled in the art that other end point detection (EPD) methods for CMP process may be utilized in combination with the current disclosure.

In general, the idea is that different materials have different optical properties and can be chemically and/or mechanically polished at different rates (e.g., different motor speed, current due to material properties). The combination of the two dielectric or insulating layers414,416, allows for the change in optical and/or material properties to be detected by CMP EPD techniques. In doing so, it allows for better and more accurate process control. In short, the two dielectric or insulating layers414,416should have different material properties. For example, if the second insulating layer416(e.g., sacrificial layer) is oxide, then the first insulating layer414(e.g., passivation layer) should be nitride, or vice versa. The distinctive material changes (e.g., going from oxide to nitride or vice versa) with a CMP process as the insulating layers414,416are slowly removed allow for improved end point detection (EPD) and facilitate the protrusion removal process. In other words, the upper insulating layer416can function as a sacrificial layer, while the lower insulating layer414can function as an etch stop layer. The CMP EPD process can recognize the change in material and realize that portions of the wafer have been removed and that most of the upper layer is gone and the machine has now reached the lower layer. The resulting wafer is one that can be substantially planar and ready for subsequent processing steps.

FIGS. 5a-5care cross-sectional views of the packages inFIGS. 4b-4d. InFIG. 5a, conformal coverage of the first insulating layer414can be formed over and around the conductive via410, the liner oxide412, as well as the surface of the semiconductor wafer404. InFIG. 5b, the second insulating layer416is applied over the first insulating layer414. In this example, the second insulating layer416is conformally covering the first insulating layer414. The second insulating layer416is also conformally covering the conductive via410, the liner oxide412, as well as the surface of the semiconductor wafer404. InFIG. 5c, the second insulating layer416has been completed removed by the CMP process as well as portions of the first insulating layer414leaving a substantially planar upper surface of the conductive via410surrounded by liner oxide412on the semiconductor wafer404passivated with the first insulating layer414.

FIGS. 6a-6bare cross-sectional views of alternative embodiments ofFIGS. 5b-5c. As discussed above, the second insulating layer416can be conformally coated over the first insulating layer414. InFIG. 6a, the second insulating layer416is non-conformally coated over the first insulating layer414. As shown, certain areas of the first insulating layer414about the conductive via410are not covered by the second insulating layer416. Regardless of the conformity of the second insulating layer416with respect to the first insulating layer414, during the CMP process a substantially planar surface can be achieved as shown inFIG. 6bfor the same reasons as discussed above.

In one embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a conductive via into the semiconductor wafer with a portion of the conductive via extending above a surface of the semiconductor wafer, forming a plurality of insulating layers over the surface of the semiconductor wafer and the conductive via, and removing a portion of the plurality of insulating layers to expose the conductive via.

In one embodiment, the above forming step includes forming a first insulating layer over the surface of the semiconductor wafer and the conductive via, followed by forming a second insulating layer over the first insulating layer, the second insulating layer having a different material composition than the first insulating layer.

In one embodiment, the above removing step includes removing a portion of the second insulating layer, followed by removing a portion of the first insulating layer, the two removing steps capable of exposing the conductive via.

Like above, the first insulating layer includes silicon nitride while the second insulating layer includes at least one of silicon oxide, silicon dioxide, silicon oxynitride and silicon carbon nitride. In an alternative embodiment, the first insulating layer includes at least one of silicon oxide and silicon dioxide, while the second insulating layer includes at least one of silicon nitride, silicon oxynitride and silicon carbon nitride.

The thickness of the second insulating layer is in the range of from about 0.5 micron to about 5 microns. In one example, the second insulating layer can be conformally formed over the first insulating layer. In another example, the second insulating layer can be non-conformally formed over the first insulating layer.

In one embodiment, a method of making a semiconductor device includes the processing steps similar to those above: (a) providing a semiconductor wafer; (b) forming a conductive via into the semiconductor wafer; (c) removing a portion of the semiconductor wafer so the conductive via extends above a surface of the semiconductor wafer; (d) forming a first insulating layer over the surface of the semiconductor wafer and the conductive via, the first insulating layer being silicon nitride; (e) forming a second insulating layer over the first insulating layer, the second insulating layer being at least one of silicon oxide, silicon dioxide, silicon oxynitride and silicon carbon nitride; and (f) removing a portion of the second insulating layer and a portion of the first insulating layer to expose the conductive via.

In one embodiment, the forming step (e) includes conformally forming the second insulating layer over the first insulating layer. In another embodiment, the forming step (e) includes non-conformally forming the second insulating layer over the first insulating layer. In yet another embodiment, the removing step (f) includes complete removal of the second insulating layer.

In some embodiments, the thickness of the second insulating layer is in the range of from about 0.5 micron to about 5 microns

Although the current description has been described in detail with reference to several embodiments, additional variations and modifications exist within the scope and spirit of the disclosure.