Phase changing on-chip thermal heat sink

A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

FIELD OF THE INVENTION

The invention relates to integrated circuit devices and, more particularly, to methods and systems for dissipating heat in semiconductor devices.

BACKGROUND

Heat can be removed from a device (e.g., transistor, power amplifier, etc.) in an integrated circuit chip using either the substrate itself down to a heat sink, or using wiring that is formed over the device as a heat path for transferring heat away from the device and out of the top of the chip. Such wiring, however, typically has a primary purpose of carrying electric current within the chip and is not primarily optimized for heat transfer. The electric current generates its own heat within the wiring through resistive heating, and the combination of resistive heating and heat transfer from devices can degrade the reliability and the current handling capacity of the wiring.

According to Moore's law of scaling, both the current density and the circuit density increase with each generation. In combination with exotic substrates with limited thermal conductivity such as GaAs or silicon-on-insulator (SOI), the thermal budget limitations in a chip are becoming more and more severe. Circuits or subcircuits typically use the full power budget for only a limited amount of time, often for fractions of milliseconds. With current technology, the power and temperature budget need to account for the heat generated during these periods.

Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove, particularly of a temporal nature.

SUMMARY

In a first aspect of the invention, there is a method of manufacturing an integrated circuit chip. The method includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink comprises a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

In another aspect of the invention, there is a method of manufacturing an integrated circuit chip. The method includes forming a heat sink in a substrate by: forming a trench in the substrate; forming a liner on surfaces of the trench; forming a phase change material on the liner and in the trench, wherein the phase change material has a melting point temperature that is less than an upper limit of a design operating temperature of the chip; and forming a cap on the phase change material and in the trench. The method also includes thinning a backside of the substrate to expose a portion of the liner. The method further includes forming a device on a front side of the substrate proximate the heat sink.

In another aspect of the invention, a semiconductor structure includes a device on a substrate of an integrated circuit chip, and a heat sink proximate to the device. The heat sink comprises a core composed of a phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

In another aspect of the invention, a semiconductor structure includes: a substrate; a buried insulator layer on the substrate; a semiconductor layer on the buried insulator layer; an isolation region in the semiconductor layer; and a resistor on the isolation region. The resistor is composed of a phase change material that is configured to be in a liquid phase during operation of the resistor.

In another aspect of the invention, a design structure tangibly embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises the structures of the present invention. In further embodiments, a hardware description language (HDL) design structure encoded on a machine-readable data storage medium comprises elements that when processed in a computer-aided design system generates a machine-executable representation of an on-chip heat sink comprising a phase change material, which comprises the structures of the present invention. In still further embodiments, a method in a computer-aided design system is provided for generating a functional design model of the on-chip heat sink comprising a phase change material. The method comprises generating a functional representation of the structural elements of the on-chip heat sink comprising a phase change material.

DETAILED DESCRIPTION

The invention relates to integrated circuit devices and, more particularly, to methods and systems for dissipating heat in semiconductor devices. According to aspects of the invention, a heat sink comprising a phase change material is formed in a cavity in one or more layers of an integrated circuit chip. In embodiments, the phase change material has a melting point temperature that is less than an upper limit of a design operating temperature of the chip. The heat sink comprising the phase change material may be thermally linked to an external heat sink that is arranged on an outer surface of the chip. In this manner, implementations of the invention provide an efficient mechanism for preventing temperature spikes that can be very damaging to the components of the chip.

Aspects of the invention may be used, for example, with a sub-circuit that uses its full power for a short duration, e.g., a power amplifier in a wireless communication system may have a full power transmission window of a few microseconds. Implementations of the invention smooth out the peaks of the localized chip temperature due to such short duration events, and this permits an external heat sink to the dimensioned less aggressively and manufactured less expensively. In an additional application, the phase change material heat sink may be used in it melted state as a precision resistor, relying on the fact that melted metal has no grains which eliminates a cause of resistor variability.

FIGS. 1-19show processing steps and structures in accordance with aspects of the invention. In particular,FIG. 1shows a cross section of a portion of a semiconductor structure5comprising a substrate15, a device25formed on the substrate15, a plurality of insulator layers35formed over the device25and the substrate15, and a plurality of electrically conductive elements45formed in the insulator layers35. The substrate15, device25, insulator layers35, and conductive elements45may be composed of conventional semiconductor materials and may be formed using conventional semiconductor fabrication processes.

The substrate15may comprise any suitable substrate, such as a silicon-on-insulator (SOI) substrate (e.g., including a substrate, a buried insulator layer, and a semiconductor layer) or bulk material substrate (e.g., including doped regions typically referred to as wells). The substrate15may be composed of any suitable material including, but not limited to, Si, SiGe, SiGeC, SiC, GE alloys, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors.

The device25may comprise any desired type of integrated circuit device including, but not limited to, a metal oxide semiconductor field effect transistor (MOSFET), a heterojunction bipolar transistor (HBT), etc. The device25may be a power device, for example, a power amplifier, a power diode, part of a processor core, etc., which generates a significant amount of heat during operation. The device25may be formed on a top surface of the substrate15and may extend partially into the substrate15. Any number of devices25may be present in the structure5.

The insulator layers35may comprise any desired number of layers of electrically insulating material (e.g., dielectric material), such as silicon dioxide (SiO2), tetraethylorthosilicate (TEOS), borophosphosilicate glass (BPSG), hydrogen silsesquioxane (HSQ), etc. Such layers are commonly referred to as interlevel dielectric (ILD) layers, wiring levels, etc. A lowermost one of the insulator layers35has a vertical thickness sufficient to cover (e.g., encapsulate) the device25, while subsequent ones of the insulator layers35may have any desired thickness ranging, for example, from about 0.2 μm for the lower layers to about 4-6 μm for the upper layers.

The plurality of electrically conductive elements45may comprise, for example, contacts, wires, vias, and/or interconnects, etc., and are structured to provide an electrically conductive pathway to a portion of the device25. The electrically conductive elements45may be composed of any suitable material (e.g., copper, etc.) and may be formed using conventional techniques (e.g., forming trenches in the insulator layers35and filling the trenches with conductive material, etc.).

As depicted inFIG. 2, a trench55(e.g., cavity) is formed in at least one layer of the insulator layers35. The trench55may be formed using photolithographic masking and etching. For example, a photomask may provided by forming a layer of photoresist material on the uppermost one of the insulator layers35, exposing the photoresist material to a pattern of light, and developing the exposed photoresist material. An etching process, such as one or more reactive ion etch (RIE) processes, may then be used to form the trench55extending from the top surface of the uppermost one of the insulator layers35downward toward the device25by removing material not covered by the photomask. After etching, the photomask may be removed using a conventional ashing or stripping process.

Still referring toFIG. 2, the trench55may extend into only a single one of the insulator layers35, or alternatively may extend into more than one of the insulator layers35. In accordance with aspects of the invention, the trench55is located at a distance “d” from the device25that is: (i) sufficiently small to ensure efficient thermal coupling between the device25and a heat sink material later formed in the trench55, and (ii) sufficiently large to avoid inducing parasitic capacitance between the device25and the heat sink material later formed in the trench55. In this manner, the resultant heat sink is formed proximate to the device25. In embodiments, the distance “d” is in the range of about 5 μm to about 10 μm, although the invention is not limited to this distance and smaller distances may be used when parasitic capacitance can be avoided. In embodiments, the trench55has a vertical depth (e.g., thickness) in a range of about 1 μm to about 5 μm, and an area (e.g., in plan view) in a range of about 10 μm to about 100 μm. The invention is not limited to these dimensions, however, and any suitable size trench55may be used within the scope of the invention. In additional embodiments, the trench55vertically overlaps the device25(e.g., a single vertical line intersects both the trench55and the device25.)

As depicted inFIG. 3, a liner65is formed on the exposed surfaces of the trench55, e.g., contacting the material of one or more of the insulator layers35. The liner65may be formed using conventional semiconductor processes and may comprise any suitable diffusion barrier material. In embodiments, the liner65is formed using a conformal deposition process, such as chemical vapor deposition (CVD), and is composed of a diffusion barrier material such as titanium nitride (TiN), silicon nitride (SiN), etc. The liner65may be formed to any desired thickness sufficient to provide a sufficient diffusion barrier for the phase change material that will be contained in the remainder of the trench55. For example, the liner65may have a thickness in a range of about 4 nm to 40 nm, although other thicknesses may be used within the scope of the invention.

In embodiments, when the liner65is composed of an electrical insulator material (e.g., SiN, etc.), the trench55may be formed to extend to one or more of the electrically conductive elements45, such that a portion of the liner65is formed directly on the one or more of the electrically conductive elements45(e.g., an emitter contact of the device25), e.g., as depicted by the dashed lines inFIG. 3. In other embodiments, the liner65may be composed of an electrical conductive material, which permits the heat sink to be part of a wiring network that is electrically connected to a device or sub-circuit.

As depicted inFIG. 4, a core75is formed in the trench55on the liner65. In accordance with aspects of the invention, the core75comprises a phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. In a non-limiting example, the upper limit of a design operating temperature of the chip may be about 105° C., and the phase change material may be configured to have a melting point in a range between about 50° C. and about 100° C.

In embodiments, the core75is composed of an alloy comprising gallium (Ga) and at least one of indium (In), zinc (Zn), tin (Sn), gold (Au), and copper (Cu). The ratio of the constituent elements of the alloy forming the core75may be adjusted to achieve a desired melting point for the core75. The core75may be formed, for example, by a CVD process that deposits a film of the alloy (e.g., InGa) in the trench using a temperature controlled chamber that maintains the structure5at a temperature that is sufficiently low (e.g., cool) to maintain the deposited alloy in a solid state. The core75may also be formed, for example, by plural CVD processes in which layers of the individual constituents of the alloy (e.g., In and Ga) are alternately formed within the trench55. The core75may also be formed, for example, using an electrodeposition process that utilizes a gallium electroplating bath with alloying elements added directly to the bath.

Still referring toFIG. 4, the deposition of the core75may result in the formation of excess material on the upper surface of the uppermost one of the insulator layers35. The excess material (e.g., alloy) is removed using a planarization process. Any suitable planarization process may be used, such as an endpoint etch or chemical mechanical polish (CMP).

As depicted inFIG. 5, the core75is recessed to form a trench85. The trench85may be formed using any suitable technique, such as a timed etch of the core75material, e.g., using an RIE process that removes the material of the core75but avoids removing material of the insulator layers35and liner65.

As shown inFIG. 6, a cap95is formed in the trench85on the upper surface of the core75. In embodiments, the cap85is composed of the same material as the liner65. The cap95may be formed using any desired fabrication technique, such as CVD. A planarization process, e.g., CMP, may be performed after forming the cap95.

In accordance with aspects of the invention, the core75encapsulated by the liner65and cap95constitutes an on-chip heat sink100comprising a reservoir of phase change material that provides enhanced heat dissipation for the device25. Heat generated by the device25(e.g., when the device25receives a power surge) is absorbed by the on-chip heat sink100and causes the temperature of the core75to increase toward the melting point of the core75. As the core75begins to melt (e.g., change from a solid phase to a liquid phase), the heat of formation temporarily absorbs energy and keeps the core75temperature close to the melting point until substantially all the core75is melted. While melting from a solid to a liquid, the core75remains at substantially a same temperature while it continues to absorb heat from the device25(e.g., as latent heat). Melting the core75absorbs about 125 to 300 times the amount of energy required to increase a same volume of silicon one degree Celsius. For example, heating 1000 μm3of silicon requires about 1.6 nJ (nano-Joule), whereas melting 1000 μm3of InGa requires about 210-470 nJ. In this manner, implementations of the invention keep the device25relatively cool at least until the core75is fully melted.

As depicted inFIG. 7, an external heat sink105may be thermally connected to the on-chip heat sink100. The external heat sink105may comprise any conventional heat sink apparatus that is formed or connected externally to the chip. For example, the external heat sink105may comprise a metal layer deposited and patterned on the outer surface of the uppermost one of the insulator layers35. As another example, the external heat sink105may comprise a pre-formed metal structure that is connected to the uppermost one of the insulator layers35, e.g., via a thermal interface material. The external heat sink105promotes heat transfer away from the on-chip heat sink100, thus permitting the core75to cool and solidify when the device25temporarily stops generating heat (e.g., between power surges of the device25).

As depicted inFIG. 8, at least one insulator layer115may be formed over the uppermost one of the insulator layers35and the on-chip heat sink100in the structure ofFIG. 6. For example, the uppermost one of the insulator layers35in which the trench55was formed may comprise an intermediate wiring level, and the at least one insulator layer115may comprise a last wiring level. The at least one insulator layer115may be composed of the same material as the insulator layers35.

FIG. 9shows adding an external heat sink105to the structure ofFIG. 8. In embodiments, the external heat sink105is formed on or connected to the uppermost surface of the at least one insulator layer115(e.g., in a manner similar to that described with respect toFIG. 7). Prior to adding the external heat sink105, at least one thermal link125may be formed in the at least one insulator layer115and in contact with the heat sink100. In embodiments, the at least one thermal link125comprises a wire or via that is formed by etching a trench in the at least one insulator layer115and forming a thermally conductive material (e.g., metal) in the trench (e.g., via CVD).

FIGS. 10-15illustrate an implementation of the invention in which an on-chip heat sink is formed in a substrate a rather than in insulator layers above the substrate. In accordance with aspects of the invention, the heat sink a may be formed in a substrate as a through-silicon-via (also referred to as a through-wafer-via). For example, as shown inFIG. 10, a trench155may be formed in the substrate15. As described herein, the substrate15may be an SOI substrate or a bulk silicon substrate, and the trench155may be formed using photolithographic masking and etching techniques. As shown inFIG. 11, a liner165may be formed on the surfaces of the trench155. The liner165may be similar to liner65. As shown inFIG. 12, a core175may formed in the remainder of the trench155on the liner165. The core175may be similar to core75. As shown inFIG. 13, the core175may be recessed and a cap195may be formed on the core175to form the on-chip heat sink100′. The cap195may be similar to cap95.

As shown inFIG. 14, a backside197of the substrate may be thinned (e.g., using a grinding process) until a portion of the liner165is exposed at the backside197, such that the combination of the core175and liner165constitutes a through-silicon-via200that extends completely through the substrate15. As shown inFIG. 15, the device25, insulating layers35, and electrically conductive elements45may be formed at the front side of the substrate15(e.g., opposite the backside197) and over the on-chip heat sink100′

In accordance with aspects of the invention, the on-chip heat sink100′ may thus be implemented earlier in the fabrication process as a through-silicon-via. The heat sink100′ may undergo a phase change (e.g., melt) while absorbing heat from the device25(e.g., similar to heat sink100), and may dissipate the heat through the substrate15or an external heat sink that is thermally linked to the heat sink100′, e.g., at the backside197.

FIGS. 16-19illustrate an implementation of the invention in which a precision resistor is composed of a phase change material. Specifically,FIG. 16shows an exemplary SOI wafer210employed as an intermediate structure in implementations of the invention. The SOI wafer210has a semiconductor substrate215, which is typically a silicon substrate, a buried insulator layer220formed on the substrate215, and a semiconductor layer225, which is typically a silicon layer, formed on the buried insulator layer220. The constituent materials of the SOI wafer210may be selected based on the desired end use application of the semiconductor device. For example, the substrate215may be composed of any suitable material including, but not limited to, Si, SiGe, SiGeC, SiC, GE alloys, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. The buried insulator layer220may be composed of oxide, such as SiO2, and may be referred to as a buried oxide (BOX) layer220. Moreover, although the SOI wafer is referred to as “silicon on insulator,” the semiconductor layer225is not limited to silicon. Instead, the semiconductor layer225may be comprised of various semiconductor materials, such as, for example, Si, SiGe, SiC, SiGeC, etc.

As shown inFIG. 17, a shallow trench isolation (STI) structure230is formed in the wafer210, and a resistor235is formed on the STI230. The STI230may be a conventional shallow trench isolation structure formed using conventional semiconductor fabrication processes and materials. For example, the STI230may be formed by arranging a photoresist material on the semiconductor layer225, exposing and developing the photoresist, etching an STI trench in the semiconductor layer225through the patterned photoresist (e.g., using an RIE process), stripping the photoresist, filling the trench with an STI material (e.g., SiO2), and planarizing the top surface of the structure (e.g., via CMP). The STI230locally replaces a portion of the semiconductor layer225.

In accordance with aspects of the invention, the resistor235is composed of material that has a melting point that causes the resistor235to be in a liquid phase at normal operating temperatures of the chip. For example, similar to core75described herein, the resistor235may be composed of an alloy of Ga and one of and at least one of indium (In), zinc (Zn), tin (Sn), gold (Au), and copper (Cu), in which the ratio of the constituent materials of the alloy is adjusted to achieve a desired melting point for the resistor235. In embodiments, the ratio of the constituent materials of the alloy is adjusted to cause the resistor to have a melting point in a range of about 40° C. to about 80° C., although the invention is not limited to these values and any suitable melting point may be used. The material of the resistor235may be formed using conventional techniques, e.g., CVD, electrodeposition, etc. For example, the material of the resistor235may be deposited in a conformal blanket deposition and then patterned to a final shape. As another example, a patterned lift-off mask may first be formed, the material of the resistor235formed in an opening of the lift-off mask, and the lift-off mask removed leaving the resistor235.

One source of variability in resistive metal films is the grain size of the solid metal. A liquid metal film, however, has no grains. Therefore, by using a resistor235that is in a liquid phase at normal (e.g., design) operating temperatures of the chip, implementations of the invention eliminate the unwanted variation associated with grain size.

As shown inFIG. 18, a dielectric layer270is formed over the resistor235, portions of the semiconductor layer225, and STI230. The dielectric layer270may be formed using conventional semiconductor fabrication processes and materials. For example, the dielectric layer270may comprise one or more layers of oxide, nitride, oxynitride, or other dielectric materials that are formed using, e.g., CVD. In embodiments, the dielectric layer270comprises a thin oxide film270aformed on the resistor235and portions of the semiconductor layer225and STI230, a nitride layer270bdeposited on the oxide film270a, and an upper layer270c(e.g., comprising SiO2, BPSG, TESO, HSQ, etc.) deposited on the nitride layer270b. The oxide film270amay have a thickness of about 3 nm, the nitride layer270bmay have a thickness of about 20-30 nm, and the upper layer270cmay have a thickness of about 1-6 μm, although the invention is not limited to these dimensions and any suitable thicknesses may be employed within the scope of the invention.

As shown inFIG. 19, resistor contacts295are formed in the dielectric layer270and in contact with the upper surface of the resistor235. The resistor contacts295may be composed of any suitable electrical conducting material and may be formed using conventional semiconductor processing techniques. For example, the resistor contacts295may be formed by masking and etching the dielectric layer270to form contact holes in the dielectric layer270, and depositing metal (e.g., copper or aluminum) in the contact holes (e.g., via CVD).

Design process910employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure920together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure990.