Three dimensional integrated circuit package

This invention discloses a three-dimensional, high density package for integrated circuits for which integrated circuits are placed onto substrate layers and then stacked together. Techniques for interconnecting the layers to one another and for connecting the layers to external circuitry are also disclosed. Techniques for cooling the stack with heat sinks or fluid flow are also disclosed.

FIELD OF THE INVENTION 
This invention relates to the improved packaging of multiple electronic 
circuit devices More particularly, this invention describes a three 
dimensional structure, which when implemented as described offers the 
capability for packaging, interconnecting and cooling a large number of 
integrated circuits in an extremely dense and easily manufactured unit. 
BACKGROUND OF THE INVENTION 
In the field of electronics it has been a continual goal of engineers to 
reduce the size of systems. The majority of system size reduction has been 
achieved through utilization of integrated circuit technology. A primary 
aim of these technologies has been to reduce transistor size and integrate 
increasingly dense circuitry and functionality within a single integrated 
circuit. 
In order to connect integrated circuits to operational electronic systems, 
some means must be available for transferring signals and power into and 
out of the integrated circuit. Typically, each chip is placed into its own 
chip package. Wires are then connected between bond pads on the chip and 
pins on the package. Several such packages (DIPs, SIPs, LCC, PGA, etc.) 
are then assembled onto various media (ceramic, epoxy, metallized layers, 
etc.) to perform useful functions. For purposes of this description define 
"chip" to mean a completed integrated circuit die prior to the formation 
of any physical or electrical connection thereto. The "major surface" of 
the chip is defined to be that surface on which the integrated electronics 
have been disposed. The "back surface" of the chip shall be that surface 
opposite the major surface. 
Packaging technology has essentially allowed for the placement of a chip 
into a protective environment which allows for the interconnection of the 
chip to external circuitry. The integrated circuit is then electrically 
connected (bonded) to external connectors. Historically integrated circuit 
packages have been cylindrical cans with wire pins housing small chips. 
Subsequently Dual-In-Line packages (DIPs) made of plastic or ceramic with 
two parallel rows of pins became the industry standard. Due to increased 
lead count (pin) requirements Pin Grid Array (PGA) packages, which have a 
matrix of pins extending from the bottom of the package, and Leadless Chip 
Carrier (LCC) packages, which have an array of external connector lands 
around the package edge, have been developed. 
Typical integrated circuit packages contain only one integrated circuit. 
The package "footprint" is many times the area of the integrated circuit. 
To satisfy the requirements for increasing the density of electronic 
circuitry within a system, attempts have been made to employ 
three-dimensional stacking of integrated circuits. Such three-dimensional 
techniques attempt to overcome the difficulties which face the designer of 
hybrid circuits. A hybrid circuit typically consists of a two dimensional 
structure made up of a large insulated substrate, usually ceramic, onto 
which are connected in lateral orientation, two or more chips, packaged 
chips and/or other electronic components. These techniques are well known 
in the art, but their effectiveness at significantly increasing circuit 
density is somewhat limited. 
A technique proposed in Carson, et al., U.S. Pat. No. 4,551,629 involves 
the three dimensional stacking of chips. While this stack of chips has a 
higher packaging density than any of the previously described techniques 
there are severe manufacturing, thermal and testing difficulties which 
make this technique difficult and expensive to implement. These 
difficulties relate to the complexity of the stacking process together 
with the processing problems associated with attempting to form external 
connections to the semiconductor stack. The package cannot easily be made 
hermetic. Special chips must be designed and configured for use with this 
technique. Further, complex wafer processing techniques must be applied to 
the edges of the stack prior to external connection. Because of this 
additional processing the circuits cannot be tested at each step of the 
processing causing extensive manufacturing yield loss. A severe limitation 
is imposed by the requirement that all of the stacked devices must have 
the equal dimensions. 
It is an object of this invention to provide a high density packaging 
technology for chips. 
It is another object of this invention to use this packaging technology to 
provide a variety of high density packages for chips useful for a variety 
of applications. 
It is another object of this invention to have the manufacturing steps for 
forming high density packages use industry standard packaging techniques. 
Still another object of this invention is to provide high density 
integrated circuit packages which are suitable for use with standard 
commercial chips of various dimensions. 
Yet another object of this invention is to provide efficient and convenient 
means for cooling such high density chip packages. 
A further object of this invention is to provide an efficient means for the 
interconnection of the chips in such a high density package. 
An additional object of this invention is to provide a structure which is 
easy to test both during and subsequent to manufacturing. 
SUMMARY OF THE INVENTION 
This invention is for an improved package and packaging technology for 
chips from which circuit modules are formed which are significantly denser 
and easier to manufacture than previously existing techniques allowed. The 
techniques of this invention are applicable for use with any form of 
commercially available chip. Standard commercially available chips may be 
used without any modification or special manufacturing steps. 
In accordance with the present invention, at least one chip is mounted on 
each of a plurality of substrates, commonly ceramic, each of which has 
electronically conducting traces for carrying electronic signals. The 
chips connect electrically to the traces by means such as wire bonds, flip 
chip bonding, or TAB bonding. At least certain of the traces extend to 
edges of the substrate for the purpose of making electrical connections 
from the chip(s) on the substrate to external circuitry. Other traces may 
extend from one edge of the substrate to another edge to allow the 
pass-through of an external signal. Other traces may extend between 
multiple chips on these single substrates which contains more than one 
chip. Pins which extend from the edge of the substrate are connected to 
the pattern of traces on each layer. A substrate may contain multiple 
layers of traces for the distribution of signals, power or ground voltages 
and currents. 
Two or more substrates are connected together, one on top of the other, to 
form a dense stack of electronic circuitry. Between each layer, a window 
frame spacer, commonly ceramic, surrounds and protects the chips. Define 
"layer" to consist of a substrate, traces, chips, and external 
connections. 
Side interconnection plates (SIP) electrically connect between layers. A 
SIP is a substrate, commonly ceramic, on which appropriately placed 
conducting traces are formed. The SIP is coupled to receive signals from 
and supply signals to the external connectors of each layer (pins). At 
least one trace on a SIP may be so configured as to connect to each layer 
within the stack such as for a bus signal, ground or power supply. 
Through the use of layer pass-throughs and SIPs, signals may be routed 
anywhere around or within the stack. SIPs may have multiple layers of 
traces. 
Three basic configurations are described for making external connection 
from the stack. A first device uses an external side interconnection plate 
(ESIP). An ESIP is similar to a SIP except that the ESIP is larger than 
the side of the stack to which it connects and certain traces on the ESIP 
extend beyond the edges of the stack and terminate in lands (bond pads) of 
sufficient size to receive a wire bond. 
A module subassembly consists of a stack, SIP(s) and ESIP and is mounted 
within a package base. Package pins for external connection to the 
completed device penetrate and terminate within the package base. Using 
standard integrated circuit wire bonding techniques, the ESIP bond pads 
are bonded to the package pins. A cap covers the stack, SIP and ESIP 
assembly to protect the stack from mechanical damage and to provide an 
hermetic seal. 
A second configuration used for making external connections from the stack 
connects the stack to a base plate out of which extends an array of pins, 
similar to a standard pin grid array (PGA) single chip package. Conductive 
traces are formed on a substrate, usually ceramic, forming the base. The 
base may contain multiple layers of traces as required by the specific 
application being implemented. Pins penetrate the layer and are 
electrically coupled to the traces. The traces extend to those edges which 
correspond to the edges of the stack to be coupled to SIPs. SIPs connect 
to the base as if the base was simply another layer in the stack. 
A third configuration connects the stack to a second PGA-like base. In this 
configuration the connectors on the edges of each layer connect to the PGA 
base plate as if it were a SIP. Vias and traces connect the connectors on 
the edges of each layer to the pins on the bottom of the PGA package. If 
the connectors on the edges of the layers are pins then the PGA package 
pins will only reside around the periphery of the base plate. Using such 
pin connections allows the added advantage of inspectibility of the 
connections from the stack to the base plate. Further, with this 
configuration the base plate may be larger than the surface of the stack 
to which it attaches allowing for additional pins. 
Due to the high circuit density, certain applications may require that 
means be provided for cooling the stack. A first such means for the 
ESIP-type module includes attaching a heat sink to the outside of the 
package base. A second means includes interspersing heat sink members at 
predetermined intervals within the stack. A third means includes 
interspersing liquid cooling layers at predetermined intervals within the 
stack. These and other features and advantages of the present invention 
will become more apparent upon a perusal of the following detailed 
description taken in conjunction with the accompanying drawings wherein 
similar characters of reference refer to similar items in each of the 
several views.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
Many of the techniques disclosed in this detailed description of the 
invention are exemplary only and it should be clear to one skilled in the 
art that alternate techniques may be employed in practicing this 
invention. Further, other techniques which are peripheral to the invention 
and well known in the art, such as how to attach an integrated circuit to 
a ceramic substrate, are not disclosed so as to prevent obscuring the 
invention in unnecessary detail. 
As shown in FIG. 1, metal traces 24 are disposed on a rectangular substrate 
22 through normal photo lithographic, thin film and/or thick film 
techniques. The substrate may be formed of any material suitable for 
electronic packaging including but not limited to ceramic (Aluminum 
Oxide), polyimide, epoxy-glass, Beryllium Oxide, Aluminum Nitride, or 
Silicon. Figure la shows traces 24 as dotted lines indicating that they 
are either on the under side of substrate 22 or internal or both. These 
traces are defined in such a manner as to have proper orientation in order 
to be electrically coupled to receive signals from preselected chips 32. 
Certain traces 24 terminate along the edge of substrate 22. Connector pins 
26 are connected (usually brazed) onto the edge of substrate 22 and are 
coupled to receive electronic signals from traces 24. In the alternative, 
traces 24 may end in depressions 36 for solder reflow bonding. Other 
traces 24 may extend from one edge of substrate 22 to another edge to 
simply pass-through a signal which is external to the substrate 22. For 
those substrates 22 with more than one chip 32 still other traces 24 may 
couple those chips 32 to one another. Yet other traces 24 may form 
integral capacitors on substrate 22 to decouple noise from chips 32. 
Chips 32 are connected to substrate 22 and are electrically coupled to 
traces 24 through standard bonding techniques such as by flip chip bonds 
28 or wire bonds 30. Where traces 24 and chips 32 are on opposite faces of 
substrate 22 as shown in FIG. 1, electrical coupling between chips 32 and 
traces 24 must occur through vias 34. For certain applications which 
require increased density chips 32 may be mounted on either face of 
substrate 22 with coupling between such chips 32 occurring through vias 
34. Depending upon the number of pins 26 necessary for electrical 
interconnection as required by the particular application those external 
connections may be positioned along any or all edges of substrate 22. Two 
or more substrates 22 are joined together to form a stack. Spacer 38 or 
40, a frame structure, is placed between successive substrates 22 to 
protect chip(s) 32. Spacer 38 will be thicker for those applications 
having chips 32 on either face of substrate 22 than for those applications 
having chips 32 on only one face of substrate 22. The notch 42 in spacer 
38 is used to mechanically hold a heat sink in place as described below. 
Spacer 38 or 40 may be formed separately or be fabricated integrally with 
each substrate 22. FIG. 1d shows the assembly of substrate 22 and spacer 
38. 
In FIGS. 2a, 2b and 2c a completed layer of the alternate embodiment is 
shown to include substrate 22, traces 24, pins 26, bonds 28 or 30, vias 34 
(where needed) and spacer 38 or 40. Preferred layer 46 results if spacer 
38 or 40 is connected to the opposite side of substrate 22 as chips 32 as 
shown in FIG. 1. 
Alternate layer 47 results if spacer 38 or 40 surrounds chips 32 on 
substrate 22 as shown in FIG. 2. 
FIG. 3 shows a plurality of layers 46 joined together to form stack 44. To 
further simplify this disclosure only layer 46 is described. Layer 47 may 
be substituted for layer 46. In other words stack 44 could also be formed 
of a plurality of layers 47. Stack 44 is characterized by extremely dense 
electronic circuitry. In order to simplify this disclosure only pins 26 
and holes 54 are described for connecting each layer to external 
circuitry. It is obvious to one skilled in the art that depressions 36 and 
bump bonds 56 may be substituted for pins 36 and holes 54. 
The layers 46 in this embodiment and those alternate embodiments described 
below are joined together using conventional integrated circuit packaging 
techniques. The layers 46 may be joined using indium solder, solder 
preform, epoxy glass or other adhesives known in the art. In this manner 
the stack made of the layers 46 forms an integral sealed module. The 
coupling between layers 46 may be used to form an hermetic seal protecting 
the chips 32. 
Electrical connection is made to each layer 46 of stack 44 through pins 26. 
Electrical interconnection between layers 46 of stack 44 is conducted 
through a Side Interconnect Plate (SIP) 50. SIP 50 is a substrate, usually 
ceramic, of the same dimensions as the surface of stack 44 to which it 
attaches. Traces 52 are disposed on the surface of SIP 50. SIP 50 may have 
multiple layers of traces depending upon the application for which stack 
44 is configured. At appropriate places on SIP 50 and coupled to traces 52 
are holes 54 as necessary to couple to pins 26. Traces 52 and 
through-holes 54 may be configured by the designer as necessary for a 
particular application. One trace 52 may connect to multiple layers 46. 
One trace 52 may be connected to several pins 26 which performs an 
identical function for each of several chips 32. Thus, for specific 
applications, data buses, power supplies or ground signal for stack 44 may 
be formed by the appropriate placement of traces 52, traces 24 and pins 
26. 
In FIG. 3, the top layer 46 in stack 44 connects to end cap 48, usually 
ceramic. End cap 48 protects chips 32 in the top layer 46 of stack 44. All 
other chips 32 within stack 44 are protected by the layer 46 immediately 
above. If stack 44 is formed of layers 46, end cap 48 must also have a 
spacer 38 or 40. If stack 44 is formed of layers 47, end cap 48 need only 
e a rectangular parallelpiped of the same dimensions as substrate 22. 
The preferred embodiment of the invention is shown in FIG. 4 and FIG. 5. As 
shown in FIG. 4, heat sink members 72 or 74 are positioned within the 
stack between layers 46 or 47. Either spacer 38 or 40 may be used with 
heat sinks 72 or 74. Where spacer 38 is wider than heat sink 72 or 74, the 
spacer 38 has notch 42 to accommodate the heat sink. The heat sink member 
72 which is used between layers 46, where spacer 38 or 40 surround the 
back side of substrate 22 and thus protects chips 32 of the next layer has 
a "U" shaped bend in order to avoid interfering with chips 32. The heat 
sink member 74 which is used between layers 47, where spacer 38 or 40 
surrounds chips 32 on substrate 22 is a straight member. Heat sink member 
72 or 74 are relatively thin within the bounds of stack 44. In those 
situations where notch 42 is included in spacer 38 or 40 the heat sink may 
be of a similar dimension as notch 42 thereby adding no additional 
thickness to the stack. External to the boundaries of stack 44 heat sink 
member 72 or 74 may have their dimensions increased in order to improve 
heat dissipation. Where chips 32 have been flip chip bonded to substrate 
22, a thermally conducting bond 76, commonly eutectic, may be formed 
between the back surface of chip 32 and heat sink 72 or 74 for more 
efficient heat dissipation. In those situations where wire bonds 30 are 
employed to connect chips 32 to substrate 22 a metal slug 31 may be 
embedded in the substrate 22 in the appropriate locations which are 
underneath the chips 32 which are wire bonded 30 to substrate 22 for more 
efficient heat dissipation. The metal slug 31 contacts the back surface of 
chips 32 and the heat sink 72 or 74. Heat is conducted away from the chips 
32 via slug 31 and into heat sink 72 or 74. 
Heat sink members 72 or 74 are typically made of metal or other heat 
conductive material which typically also conducts electrical signals. In 
order to avoid the possibility of electrical shorts where wire bonds are 
used, the surface of the heat sink 72 or 74 which faces the wire bonds is 
electrically insulated, commonly porcelainized; i.e. one surface of the 
heat sink is coated with porcelain or other nonconductive material. 
To simplify the disclosure, only layer 46 and heat sink 72 will be 
discussed. Layer 47 and heat sink 74 may be substituted for layer 46 and 
heat sink 72. As shown in FIG. 5 two or more layers 46 and heat sinks 72 
are joined together to form stack 78. Heat sinks 72 need only be 
interspersed between layers 46 as is necessary to keep the temperature of 
stack 78 within the specific bounds. For those layers 46 without heat sink 
72 spacer 40 not 38 must be used. End cap 48 protects the chip at an the 
end of stack 78 which has no layer 46 covering it. SIPs 50 form 
interconnections between layers 46 of stack 78 in the preferred 
embodiment. 
Stack 78 connects to base plate array 80 for external electrical 
connection. An array of pins 82 penetrate ceramic substrate 86. Traces 84 
are disposed on substrate 86 and are electrically coupled to appropriate 
pins 82 as required by the application. Certain of traces 84 extend to the 
edge of base array 80. Pins 90 are connected to the side of base array 80 
for interconnection to SIP 50. Ceramic cover plate 88 connects to 
substrate 86 and covers traces 84. SIPs 50 connect to base array 80 simply 
as if it were another layer 46. 
FIG. 6 shows another method for connecting stack 44 or stack 78 to a PGA 
base plate. Base plate 81 comprises a substrate 87 from which extend pins 
83 and through which penetrate holes 91. Formed on substrate 87 and 
electrically coupled to pins 83 and holes 91 are traces 85. A secondary 
substrate or spacer 89 may be attached to substrate to cover, insulate and 
protect traces 85. Connector pins 26 of stack 44 or stack 78 penetrate and 
are electrically coupled to holes 91. The connection between pins 26 and 
these holes 91 may be inspected visually or otherwise for high reliability 
and quality applications. 
FIG. 7 shows a first alternate embodiment of the invention used for those 
applications which do not require the heat removal efficiency of the 
preferred embodiment. The subassembly of FIG. 7 including stack 44, end 
cap 48, SIP 50 and external side interconnect plate ESIP 58 is mounted 
within package base 62. ESIP 58 is similar to SIP 50 in that it is a 
ceramic substrate, with traces 52 and holes 54 placed to couple to pins 
26. However, ESIP 58 has dimensions sufficiently larger than the surface 
of stack 44 to which it attaches to allow for bond pads 60. Thus, after 
connection and coupling of stack 44 to ESIP 58, external signals may be 
coupled to stack 44 through standard wire bonding techniques to bond pads 
60. The ESIP 58 is mounted into package base 62. Penetrating through the 
walls of the cavity of base 62 are package pins 64. After insertion of the 
subassembly into package 62, wire bonds 70 connect pins 64 to bond pads 
60. Package cap 66 covers and protects stack 44, SIP 50, ESIP 58 and wire 
bonds 60. Where needed for heat dissipation heat sink 68 is attached to 
the outside of base 62. 
FIG. 8 shows a modification of the preferred embodiment described above in 
relation to FIG. 5. In this embodiment the major components are similar to 
those shown in the drawing of FIG. 5 and similar components are numbered 
similarly. 
The circuit layer 45 of the application shown in FIG. 8 includes a heat 
sink 74, four integrated circuit chips 32, a plurality of pins 26, and a 
frame 160 having internal traces 24. The frame 160 is mounted onto the 
heatsink in the location shown by the dotted lines 156. The chips 32 are 
mounted onto the heat sink 74 in predetermined locations 154 as shown. In 
this manner the chips 32 are surrounded by the frame 160 on the heatsink 
74. 
The frame 160 (FIG. 8A) is formed from overframe 150, protector frame 152 
and traces 24 using conventional techniques. The traces 24 for carrying 
electronic signals to and from the chips 32 are previously formed on the 
surface of the protector frame 152. The overframe 150 is mounted on top of 
the protector frame 152. The protector frame 152 and the overframe are 
formed with holes therethrough corresponding to the chips 32 as shown. The 
holes in the overframe 152 are generally larger than the holes in the 
protector frame 150. In this way the traces 24 and the upper surface of 
the protector frame 152 are exposed within the holes in the overframe 150. 
The traces 24 are thereby available for wire bonding. Generally, the 
protector frame 152, the overframe 150 and their respective traces 24 are 
preformed in the green state of ceramic. The frames are then co-fired to 
form the frame 160 into a single unit having internal traces prior to 
assembly within the stack 78. The frame 160 may be formed from several 
frame layers such as 150 and 152 to form a multilayer interconnection 
system of traces 24. 
The overframe 150 is formed of a smaller outer dimension than the protector 
frame 152. The notch 158 is formed by placing the two frames 150 and 152 
together. The notch 158 is used to mechanically support the pins 26 
thereby improving the mechanical strength of the coupling of the pin 26 to 
the layer 45. 
If the heatsink 74 is electrically conductive then the electrical potential 
of the substrate of the chip 32 using conventional chip mounting 
techniques may be controlled by the heatsink 74. In such an application it 
is preferred to electrically couple each heatsink 74 in the stack 78 to 
one another and to a predetermined electrical potential. Alternatively, 
the heatsink may be formed of or coated with an electrically inert 
material. In such an application the electrical potential of the substrate 
may be controlled by conventional techniques such as an on-chip back-bias 
generator. If the heatsink is formed of Beryllium Oxide then it will be 
both electrically inert and thermally active. 
FIG. 9 shows a second alternate embodiment necessary for those applications 
which require more dissipation of heat than can occur in the preferred 
embodiment. Layer 46 is identical to that disclosed in the preferred and 
first alternate embodiment. Selectively interspersed between layers 46 are 
fluid cooling layers 92. Cooling layer 92 is composed of substrate 94 and 
cap 102 which are the same dimensions as layer 46. Inlet channel 96 and 
outlet channel 98 are etched into substrate 94. Inlet 96 and outlet 98 
extend from the edge of opposite sides and run parallel to the other pair 
of opposite edges of substrate 94. Inlet 96 and outlet 98 do not extend 
completely across substrate 94, but terminate within the boundaries of 
substrate 94. Etched between inlet 96 and outlet 98 are a plurality of 
parallel microchannels 100. The microchannels, with a typical dimension of 
800 microns, are of a sufficiently small size to reduce turbulent flow in 
liquids flowing through the microchannel 100. Cap 102 connects to 
substrate 94 in order to seal inlet channel 96, outlet channel 98 and 
microchannels 100. 
Forcing a liquid into inlet 96 fills that channel before being forced 
through microchannels 100. Liquid flowing through channels 100 will absorb 
heat and remove it from the electronic circuitry on layers 46. Cooling 
layers 92 need only be interspersed between such layers 46 as is necessary 
for cooling the specific application. 
SIPs 104 are formed also to function as a fluid conduits to cooling layers 
92. SIP 104 comprises a substrate 110 on which are formed traces 111 which 
are coupled to holes 116. Holes 116 are coupled to receive signals from 
pins 26 of layer 46. These elements perform the same functions as on SIP 
50. Supply channel 106 is incorporated into substrate 110 along one edge 
from one extreme edge of substrate 110, but positioned so as to avoid 
interference with traces 114. In certain materials such channels may be 
formed by etching. Cover 112 are joined to substrate 110 to seal channel 
106. Holes 120 are formed through cover 12 to allow electrical coupling to 
traces 114 by pins 26 and to allow fluid in channels 106 to reach inlets 
96 or outlets 98. Nipples 108 are connected to certain holes 120 and cover 
112 to mechanically couple SIP 104 to stack 118 for fluid flow. A second 
SIP 104 is connected to another side of stack so that outlets 98 are 
connected to nipples 108 for removal of cooling fluid. In certain 
circumstances, these cooling channels may be integral with substrate 46 in 
FIG. 1a. 
An example for forming a 1/4 MByte static RAM module is disclosed. The 
chips selected for this example are 64K by 1 SRAMs; e.g. the Integrated 
Device Technology IDT #7187. In order to achieve 1/4 MByte of memory, 
thirty-two chips are required. One design can be built having eight layers 
with four devices per layer. Each substrate is 25 mils thick. Each spacer 
is 35 mils thick. Each heat sing is designed to be of proper dimensions to 
fit within the notch formed in each spacer. A pin grid array base is 40 
mils thick. The end cap may be formed to be 20 mils thick. The stack is 
thus 540 mils tall for substrate material, spacers, end cap and base plate 
plus 10.times.0.6 mils associated with interlayer adhesive. The entire 
stack is thus only 600 mils tall. 
Each die is 138 mils by 369 mils. The spacing between each die is 100 mils. 
The spacing between the die and the edge of the layer is 50 mils. The die 
are arranged as shown in FIG. 12. Thus, the minimal layer size is 1250 
mils by 1000 mils. The base plate will be the same size as any of the 
layers. This is the footprint required for the completed assembly for 
attachment to an external circuit. However, because of the heat sink 
overhang, each layer further requires 180 mils on each of the two opposite 
edges of the stack creating an overall footprint for a 1/4 MByte memory of 
1.6 inches by 1.1 inches, i.e. a total of 1.8 square inches. Conventional 
packaging of the same number of chips would require 18 square inches. 
FIGS. 10 and 11 show the trace pattern for each of the SIPs necessary for 
appropriate interconnection between each of the layers and to the pin grid 
array base plate. FIG. 12 shows the trace pattern necessary for a single 
layer to connect each of the four die to each other and to each SIP on a 
given layer. The completed package conforms to industry standards with 
respect to pin spacings and dimensions. 
Another embodiment of an improved stacked package will now be described in 
conjunction with FIGS. 13-16, whereby the SIPs (Side Interconnect Plates) 
are brought "inboard" to the package stack. 
Referring to FIG. 13, the interconnect pins are brought inboard as shown. 
The pins run through each layer (L-1 to L-4). The pins are soldered into 
the grooves (G). Connections are made between (or among) the layers by 
making connections (D) to the pins (G). In FIG. 13, chip (24) is connected 
to chip (6) on layer (4) but not to chip (18) on layer L-3, where burning 
is required. All bussed chips are connected to the appropriate pin (G) by 
internal planes (D). Similarly, Vcc and Vss voltages are brought into the 
package. The heat sinks are not connected to any pin except the ground pin 
of the package. Any signal which is required at a pin (G) must first be 
brought to plane (F) by means of vias (V). 
The chips are bonded to the heat sinks by thermally conducting and 
electrically isolating epoxy glue. The heat sinks are soldered to the 
bottom face of the Printed Circuit Board (FR-4) which is a metallic 
(copper) plane. 
FIG. 14 shows an exploded perspective view of the improved embodiment of 
FIG. 13. 
FIG. 15 shows a larger cross-sectional view of the preferred embodiment of 
FIG. 13 of the present invention. 
FIG. 16 depicts a plan view of one layer of the preferred embodiment of 
FIG. 15. 
The layers of FIG. 14 may be of different sizes. 
As can be seen, the side interconnect plate (SIP) "function" of other 
embodiments is brought inboard to the preferred embodiment shown in FIGS. 
13-16. 
The SIP function only permits interconnection of the circuit configuration 
on the sides while the embodiment shown in FIGS. 13-16 can provide 
interconnection on all four sides (a linear vs. area interconnection). 
The pins of FIG. 14 do not contact the layers (the insulating plate or 
layer of FIG. 13 is distinguished from the chip carrier of FIG. 14). 
The chip carrier of FIG. 14 may be made up of many layers. The pins make 
electrical connection to the chip carrier but not to the heat sinks. 
A layer select signal as applied to the circuit package of FIG. 14 could 
allow selection of a particular layer independently (the data/address 
signals are applied to all layers in parallel). 
Another aspect of the present invention of FIGS. 13-16 provides that each 
layer can be tested independently so that the defective chip can be 
removed by desoldering an insulating layer, removing the defective chip, 
replacing it and stacking the configuration according to the embodiment 
shown in FIGS. 13-16. 
The packages of FIGS. 13-16 have the following advantages: 
(1) It is mechanically very rigid due to the pin structure. 
(2) The thermal capacity is excellent due to the fact that the heat sinks 
can extend along all four sides of the package. 
(3) Its electrical characteristics are very good because there is a ground 
plane around each signal pin, and in close proximity to it. 
(4) Manufacturing is simpler because the pins act as self-aligning tools. 
(5) For packages which require many pins, several rows of slots (S) can be 
put around the periphery of the package. In addition, a full PGA (Pin Grid 
Array) can be fabricated by placing an array of pins on each layer. 
(6) The interlayer pins form the package pins, thereby reducing the need to 
have a separate "pin layer." 
(7) Testing is accomplished by assembling the stack layer by layer and 
testing each layer in turn. The layer selects are activated with the 
appropriate address and data information. Reads and Writes are performed 
until the layer has been verified. Then the next layer is added and its 
layer select is activated. An examination of the output data is made to 
see if data integrity exists during read/write operations. 
(8) This structure can be implemented in multilayer even denser packaging 
and higher thermal and environmental protection. In addition, it is 
hermetic. 
A modification to this structure of FIGS. 13-16 allows for the removal and 
replacement of the integrated circuits (ICs). This is accomplished by the 
insertion of a metallic chip carrier (CC) at the base of each chip (CC). 
This CC is anodized on one side. The anodization is covered by nickel. 
This combination allows the chip to be electrically isolated from the heat 
sink while providing an excellent thermal path to the heat sink. The chip 
is epoxied to the anodized face of the CC. The other face is soldered to 
the heat sink. 
The advantage of this approach is that it allows the CC to be de-soldered 
from the heat sink in the event that the chip is found to be defective 
during testing of the layers. 
The bonding pads (K) associated with each chip (20, 24) are large enough to 
allow multiple bonds to be made. Hence, on chip replacement there is 
sufficient "clean" surface to allow adequate bonding to be made. 
Each printed circuit board (or ALN, Al.sub.2 O.sub.3) layer (C) has lips 
(J) which allow top sealing covers (H) to be attached in order to 
hermetically isolate the chips after the functional testing of the layer. 
In certain configurations, the cavity (M) is divided into two cavities (one 
per chip) in such a way that (B) provides additional support for (H). This 
is to provide mechanical support for those layer packages which may 
contain in excess of 16 ICs per layer. 
An additional advantage of "inboard" pins is that it reduces the weight of 
the package (SIPs excluded). 
A unique three-dimensional, high density package and packaging technology 
for integrated circuits is disclosed Which is easily and inexpensively 
manufactured. Industry standard packaging techniques may by used in 
manufacturing such a module. Commercially available integrated circuits 
may be packaged in such a module without any modifications to the chips.