Extended write modes for non-volatile static random access memory architectures having word level switches

Disclosed herein is a method of performing a non-volatile write to a memory containing a plurality of volatile memory cells grouped into words, with each volatile memory cell having at least one non-volatile memory cell associated therewith. The method includes steps of a) receiving a non-volatile write instruction including at least one address and at least one data word to be written to that at least one address, b) writing the at least one data word to the volatile memory cells of a word at the at least one address, and c) writing data from the volatile memory cells written to during step b) to the non-volatile memory cells associated to those volatile memory cells by individually addressing those non-volatile memory cells for non-volatile writing, but not writing data from other volatile memory cells to their associated non-volatile memory cells because those non-volatile memory cells are not addressed.

TECHNICAL FIELD

This disclosure is directed to the field of non-volatile static random access memory (NVSRAM) architectures that have word level switches permitting non-volatile write (store) operations on individual words, and in particular, extended non-volatile write modes for such NVSRAM architectures.

BACKGROUND

There are two main types of memory devices used in computers today, namely “non-volatile” and “volatile” memory devices. The name “non-volatile” comes from the fact that non-volatile memory devices maintain the data stored therein, even when power is removed or temporarily lost. It follows that the name “volatile” comes from the fact that volatile memory devices do not maintain the data stored therein when the power is removed or temporarily lost.

Common non-volatile memory devices include read only memory (ROM) devices, EPROM (erasable programmable ROM) devices, EEPROM (electrically erasable programmable ROM) devices, and flash RAM devices. Common volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM) devices. Volatile memory devices are widely used for temporary data storage, such as during data manipulation, since writing data into or reading data out of these devices can be performed quickly and easily. However, a disadvantage of these volatile memory devices is that they require the constant application of power, and in the case of DRAM a data refresh signal, to maintain data stored in the memory cells. Once power supplied to the device is interrupted, the data stored in the volatile memory cells is lost.

Non-volatile memory devices suffer from an endurance problem caused by repeated cycling of program and erase operations, as well as slower access speeds than volatile memory devices. SRAM devices have a fast data access speed and a long lifetime, and are therefore suitable for use in a computer system. However, since SRAM is a volatile memory device, the stored data stored will be lost if power is interrupted. Therefore, there was a recognized need to back up information stored in SRAM memories with non-volatile memory, in the event of power failure.

Consequently, non-volatile static random access memory (NVSRAM) has been developed, which pairs each SRAM cell with two EEPROM cells so as to produce a device capable of quickly storing the contents of the SRAM cell in the event of power loss and then retrieving of those contents when power is restored. Each EEPROM cell is comprised of a floating gate transistor that has a charge placed on its floating gate to modify the voltage threshold VT of that floating gate transistor, and this charge indicates the state of the binary data retained in that EEPROM cell.

Both EEPROM and NVSRAM memories suffer notable drawbacks. With EEPROM, while the minimal granularity of a store operation is one byte, the maximal granularity of a store operation is one page, which is one row—this means that only a single word line may be written to at once. Therefore, to store more than a row's worth of data into an EEPROM, a store must be performed sequentially on each row until the data to be written is complete. Since a store operation on an EEPROM may only store data to a single same page (row), storing a quantity of data in excess of one page (row) to an EEPROM requires multiple such operations, is time consuming, and consumes excessive power.

One advantage of NVSRAM is that it can store the contents of all of its SRAM cells to their respective EEPROM cells in parallel, making store operations of large amounts of data a quick operation. However, this is also a considerable drawback in that a conventional NVSRAM is only arranged to store the contents of all of its SRAM cells to their respective EEPROM cells in parallel, and if a store to fewer than all EEPROM cells is desired, it cannot be performed. The reasons for this are shown inFIG. 1, which it can be seen that every NVSRAM cell10receives the same power source line PS and same control gate line CGL, both of which are manipulated when performing store operations to the EEPROM cells. In addition, each row of NVSRAM cells10receives a respective wordline WL for that row.

Since it is desirable not only for there to be NVSRAM cells capable of performing a store operation on less than all of their EEPROM cells, but for such capability to have opcodes supporting the operations it makes possible, further development of NVSRAm technology is needed.

SUMMARY

Disclosed herein is a method of performing a non-volatile write to a memory containing a plurality of volatile memory cells grouped into words, with each volatile memory cell having at least one non-volatile memory cell associated therewith. The method includes steps of: a) receiving a non-volatile write instruction, the non-volatile write instruction including at least one address and at least one data word to be written to that at least one address; b) writing the at least one data word to the volatile memory cells of a word at the at least one address; and c) at specified time, writing data from the volatile memory cells written to during step b) to the non-volatile memory cells associated to those volatile memory cells by individually addressing those non-volatile memory cells for non-volatile writing, but not writing data from other volatile memory cells to their associated non-volatile memory cells because those non-volatile memory cells are not addressed.

The specified time may or may not be when chip deselection of the memory occurs.

The at least one address may include a starting address. The at least one data word may be a plurality of data words. Step b) may include: b1) writing a first data word of the plurality of data words to the volatile memory cells of the word at the starting address; b2) incrementing the starting address to produce a next address; b3) writing a next data word of the plurality of data words to the volatile memory cells of the word at the next address; b4) if the plurality of data words contains another data word that was not yet written, increment the next address and returning to step b3); and b5) if the plurality of data words does not contain another data word that was not yet written, proceeding to step c).

The specified time may or may not be when chip deselection of the memory occurs.

The at least one address may be a plurality of addresses. The at least one data word may be a plurality of data words. Step b) may include: b1) writing a first data word of the plurality of data words to the volatile memory cells of a word at a first of the plurality of addresses; b2) writing a next data word of the plurality of data words to the volatile memory cells of a word at a next of the plurality of addresses; b3) if the next of the plurality of addresses is a last address of the plurality of addresses, proceeding to step c); and b4) if the next of the plurality of addresses is not a last address of the plurality of addresses, returning to step b2).

The specified time may or may not be when chip deselection of the memory occurs.

Also disclosed herein is an electronic device including a memory array comprising a plurality of volatile memory cells grouped into words and at least one non-volatile memory cell associated with each volatile memory cell, and a plurality of word level switches, each word level switch being associated with one word and permitting writing of data to non-volatile memory cells associated with volatile memory cells of that word. The electronic device may also include control circuitry configured to perform steps of: a) receiving a non-volatile write instruction, the non-volatile write instruction including at least one address and at least one data word to be written to that at least one address; b) writing the at least one data word to the volatile memory cells of a word at the at least one address; and c) at specified time, writing data from the volatile memory cells written to during step b) to the non-volatile memory cells associated to those volatile memory cells by individually addressing those non-volatile memory cells for non-volatile writing, but not writing data from other volatile memory cells to their associated non-volatile memory cells because those non-volatile memory cells are not addressed.

The specified time may or may not be when chip deselection of the memory array occurs.

The at least one address may be a plurality of addresses. The at least one data word may be a plurality of data words. Step b) may include: b1) writing a first data word of the plurality of data words to the volatile memory cells of a word at a first of the plurality of addresses; b2) writing a next data word of the plurality of data words to the volatile memory cells of a word at a next of the plurality of addresses; b3) if the next of the plurality of addresses is a last address of the plurality of addresses, proceeding to step c); and b4) if the next of the plurality of addresses is not a last address of the plurality of addresses, returning to step b2).

The specified time may or may not be when chip deselection of the memory array occurs.

Also disclosed herein is a method of operating a non-volatile static random access memory (NVSRAM) including: a) receiving a non-volatile write instruction, the non-volatile write instruction including at least one address and at least one data word to be written to that at least one address; b) writing the at least one data word to volatile memory cells of a word at the at least one address; and c) writing data from the volatile memory cells written to during step b) to the non-volatile memory cells associated to those volatile memory cells by individually addressing those non-volatile memory cells for non-volatile writing.

The at least one address may include a starting address. The at least one data word may include a plurality of data words. Step b) may include: b1) writing a first data word of the plurality of data words to the volatile memory cells of the word at the starting address; b2) incrementing the starting address to produce a next address; b3) writing a next data word of the plurality of data words to the volatile memory cells of the word at the next address; b4) if the plurality of data words contains another data word that was not yet written, increment the next address and returning to step b3); and b5) if the plurality of data words does not contain another data word that was not yet written, proceeding to step c).

The at least one address may be a plurality of addresses. The at least one data word may be a plurality of data words. Step b) may include: b1) writing a first data word of the plurality of data words to the volatile memory cells of a word at a first of the plurality of addresses; b2) writing a next data word of the plurality of data words to the volatile memory cells of a word at a next of the plurality of addresses; b3) if the next of the plurality of addresses is a last address of the plurality of addresses, proceeding to step c); and b4) if the next of the plurality of addresses is not a last address of the plurality of addresses, returning to step b2).

DETAILED DESCRIPTION

The following disclosure enables a person skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

Reference is first made toFIG. 2A, showing a NVSRAM array99comprised of multiple NVSRAM cells10and word level switches11, with the NVSRAM cells10being arranged into words90, and with one word level switch11located adjacent each word90. The words90are arranged into columns122, and the word level switches11are arranged into columns124as well. The word level switches11generate individual word level control signals, such as a power signal on a power source line PS, a control gate signal on a control gate line CGL, and a word level word signal on a word level word line WWL.

Understand that it is these word level switches11that permit each word of the NVSRAM array99to be individually addressed during non-volatile operations, yet be backward compatible with standard NVSRAM volatile and non-volatile operations if desired.

A NVSRAM memory104is further described with additional reference toFIG. 2B. The NVSRAM memory104includes the NVSRAM array99, which itself includes multiple columns122, with each column being comprised of words90of NVSRAM cells10. Each word90is divided into its constituent NVSRAM cells10. Adjacent each column122of NVSRAM words90is a column124of word level switches11. A row decoder108and column decoder110receive instructions from control logic116and decode addresses within the NVSRAM array99accordingly. A write HV generator112and sense amplifiers118respectively operate during write and read cycles to effectuate writes of data to, and reads of data from, the NVSRAM array99. The control logic116may receive commands or opcodes (e.g. read, write, reload, store, extended page write, bulk write, and delayed write) via a SPI bus interface114, and may generate its commands to the row decoder108and column decoder110based thereupon.

An example word90utilizing the NVSRAM cells10taught above is now described with reference toFIG. 2C. Word switch circuitry11has inputs coupled to the NW, WL, SRWL, ERWL, RL, EES, VDD, VPLUS, VMINUS, ERASEC, PROGC, RSTW, READ, and SETW lines, and provides output to the PS, CGL, and WWL lines. Any number of NVSRAM cells94. . .9nare coupled to the word switch circuitry11and to their respective bitlines BL0. . . BLn. The word switch circuitry11performs the functions as will be described below so as to facilitate read, write, reload, and store operations performed on and by the NVSRAM cells94. . .9non a word by word basis.

Additional reference now is madeFIG. 2Dshowing the design of the NVSRAM cells10. The NVSRAM cells10are 10T (ten transistor). Each NVSRAM cell10includes a 6T (six transistor) SRAM cell12formed from first and second cross coupled inverters14and16forming a latch that stores a data bit, with pass gate transistors MN3and MN4providing access to the stored data bit. First and second EEPROM strings17and18serve to back up the stored data bit if power loss is anticipated or expected, and then the data bit can be retrieved once power is restored.

The first inverter14is formed from PMOS transistor MP1and NMOS transistor MN1. Transistor MP1has its source coupled to the power supply line PS and its body coupled to the n-well line NW. Transistor MN1has its drain coupled to the drain of transistor MP1, its source coupled to the NS line, and its gate coupled to the gate of transistor MP1.

The second inverter16is formed from PMOS transistor MP2and NMOS transistor MN2. Transistor MP2has its source coupled to the power supply line PS and its body coupled to the n-well line NW. Transistor MN2has its drain coupled to the drain of transistor MP2, its source coupled to the NS line, and its gate coupled to the gate of transistor MP2. The gates of transistors MP2and MN2are coupled to the drains of transistors MP1and MN1, and the gates of transistors MP1and MN1are coupled to the drains of transistors MP2and MN2.

Pass gate NMOS transistor MN3has its drain coupled to node N1(at the drains of transistors MP1and MN1), its source coupled to the bit line BL, and its gate coupled to the word level word line WWL. Pass gate NMOS transistor MN4has its drain coupled to node N2(at the drains of transistors MP2and MN2), its source coupled to the complementary bit line BLC, and its gate coupled to word line WL.

The first EEPROM string17is comprised of NMOS transistor MN5in series with floating gate transistor EE1. The transistor MN5has its drain coupled to node N1and a gate coupled to the reload line RL. The floating gate transistor EE1has its drain coupled to the source of transistor MN5, its source coupled to the EEPROM source line EES, and its gate coupled to the control gate line CGL.

The second EEPROM string18is comprised of NMOS transistor MN6in series with floating gate transistor EE2. The transistor MN6has its drain coupled to node N2and its gate coupled to the reload line RL, and a source. The floating gate transistor EE2has its drain coupled to the source of transistor MN6and its source coupled to the EEPROM source line EES.

Operation of this circuit for operations on the SRAM cell12need not be described herein as it proceeds as is standard for SRAM cells. Operations performed on the EEPROM strings17and18for storing non-volatile data are now described.

The storing of non-volatile data into the EEPROM cells (floating gate transistors EE1and EE2) is accomplished by performing an erase operation followed by a program operation.

The erase operation operates as follows. The EES, NS, WWL and RL lines are set to a logic low, isolating the floating gate transistors EE1and EE2from the SRAM12. The n-well line NW and power supply line PS are set to VDD. The CGL line is then pulsed with a high voltage, for example 14V, erasing the contents of the floating gate transistors EE1and EE2, putting them into an off state.

The program operation operates as follows. The EES, NS, WL, and RL lines are set to a logic low, while the n-well line NW is set to VDD and the power supply line PS is set to 5V. The CGL line is pulsed with −9V so that a cell storing a one sees 5-(−9)=14V and a cell storing a zero sees 0-(−9)=9V, while the RL line is then set to a logic high to connect the floating gate transistors EE1and EE2to the SRAM12. The inverter14or16that is holding a logic high passes the logic high to the floating gate transistor EE1or EE2connected thereto, and the inverter14or16that is holding a logic zero passes the logic low to the floating gate transistor EE1or EE2connected thereto. While a 14V difference between N1or N2and CGL is sufficient to program an EEPROM cell, 9V has a negligible effect and is insufficient to program an EEPROM cell. Therefore, the floating gate transistor EE1or EE2receiving a logic one is programmed, while the floating gate transistor EE1or EE2receiving a logic zero is not programmed. Thus, the data from the SRAM cell12is stored as non-volatile data.

The reloading of non-volatile data into the SRAM cell12upon power-up is as follows. The EEPROM source line EES and NS line are placed at a logic low, as is the word line WL. The CGL line is placed at a reference voltage Vref, typically around 0.5V to 1V. The n-well line NW and RL line are placed at VDD. The power supply line PS then ramps up. The RL line being at VDD turns on transistors MN5and MN6, coupling the EEPROM cells (floating gate transistors EE1and EE2) to nodes N1and N2. The floating gate transistors EE1and EE2will be at different states, with one being “programmed” and containing the bit of stored data and the other being “erased”. The floating gate transistor EE1or EE2that is programmed will draw more current than the one that is erased, which unbalances the cross coupled inverters14and16, resulting in a flipping of the states of the inverters14and16to match that of the floating gate transistors EE1and EE2, thereby reloading the SRAM cell12with the stored non-volatile data bit.

Understand that in prior art applications, the PS, CGL, and WL lines are global to a NVSRAM array, such that when a program operation is performed, it is performed globally to all NVSRAM cells of that NVSRAM array. The word level switches11disclosed herein permit store operations (non-volatile write operations) to be performed on the NVSRAM array99on a word by word basis, such that the granularity of a store operation is one word90. Keeping this functionality in mind, new or updated opcodes have been devised which combine the operation of a write to the SRAM cells12of a word of NVSRAM cells10with a store operation of the data from those SRAM cells12(once written) to the EEPROM cells17-18of those NVSRAM cells10.

As will be described, the word level switches11include a control gate latch30which provides the control gate signal to the control gate line CGL,

The control gate latch30is now described with reference toFIG. 2E. The control gate latch30includes cross coupled inverters32and34. The inverter32includes PMOS transistor MP31and NMOS transistor MN31. The transistor MP31has its source and body coupled to the VPLUS line and its drain coupled to node N31. The transistor MN31has its drain coupled to node N31and its source coupled to the VMINUS line. The gates of transistors MP31and MN31are coupled to node N32. The inverter34includes PMOS transistor MP32and NMOS transistor MN32. The transistor MP32has its source and body coupled to the VPLUS line and its drain coupled to node N32. The transistor MN32has its drain coupled to node N32and its source coupled to the VMINUS line. The gates of transistors MP32and MN32are coupled to node N31.

NMOS transistor MN33has its drain coupled to node N31and its gate coupled to the program line PROGC. NMOS transistor MN34has its drain coupled to the source of transistor MN33, its source coupled to ground, and its gate coupled to the PSN line. NMOS transistor MN35has its drain coupled to node N31and its gate coupled to the erase line ERASEC. NMOS transistor MN36has its drain coupled to the source of transistor MN35, its source coupled to ground, and its gate coupled to the power supply line PS. NMOS transistor MN37has its drain coupled to node N32, its source coupled to ground, and its gate coupled to the read line READ. The PROGC and PSN signals being at a logic high, or the ERASEC and PS signals being at a logic high, serves to set the control gate latch30. The READ signal serves to reset the latch. Note that the control gate line signal CGL is generated at node N32.

The power source latch40is now described with reference toFIG. 2F. The power source latch40includes cross coupled inverters42and44, as well as an inverter46coupled in series with the output of inverter44. Inverter42is comprised of PMOS transistor MP41and NMOS transistor MN41. The transistor MP41has its source and body coupled to VDD and its drain coupled to node N41. The transistor MN41has its drain coupled to node N41and its source coupled to ground. The gates of transistors MP41and MN41are coupled to node N42. The inverter44includes PMOS transistor MP42and NMOS transistor MN42. The transistor MP42has its source and body coupled to VDD and its drain coupled to node N42. The transistor MN42has its drain coupled to node N42and its source coupled to ground. The gates of transistors MP42and MN42are coupled to node N41.

NMOS transistor MN43has its drain coupled to node N42and its gate coupled to the SETW line. NMOS transistor MN44has its drain coupled to the source of transistor MN43, its source coupled to ground, and its gate coupled to the word line WL. NMOS transistor MN45has its drain coupled to node N41, its source coupled to ground, and its gate coupled to the RSTW line. Note that the power supply line PS is produced at node N43and its inverse PSN is produced at node N42. The RSTW signal being at a logic high sets the latch formed from inverters42and44(and therefore resets the power source latch40), while the SETW and WL lines being high resets the latch formed from inverters42and44(and therefore sets the power source latch).

Inverter46is comprised of PMOS transistor MP43and NMOS transistor MN46. PMOS transistor MP43has its source and body coupled to VDD and its drain coupled to node N43. NMOS transistor MN46has its drain coupled to node N43and its source coupled to ground. The gates of transistors MP43and MN46are coupled to node N42.

The control circuitry150is now described with reference toFIG. 2G. The control circuitry150includes NOR gates156and inverter152. Inverter152has an input coupled to the word line WL. NOR gate156has inputs coupled to the WRITEN line and to the output of inverter152. The word level word line WWL signal is produced at the output of NOR gate156.

An alternate design for word switch circuitry11′ is now described with reference toFIGS. 2H-2I. The word switch circuitry11′ is comprised of the control gate latch30(FIG. 2E), power source latch170, and control circuitry180.

The power source latch170includes cross coupled inverters174and176forming a latch. The inverter174includes PMOS transistor MP71and NMOS transistor MN71. The transistor MP71has its source and body coupled to VDD and its drain coupled to node N71. The transistor MN71has its drain coupled to the drain of transistor MP71and its source coupled to ground. The gates of transistors MP71and MN71are coupled to node N72. The inverter176includes PMOS transistor MP72and NMOS transistor MN72. The transistor MP72has its source and body coupled to VDD and its drain coupled to node N72. The transistor MN72has its drain coupled to node N72and its source coupled to ground. The gates of transistors MP72and MN72are coupled to node N71. NMOS transistor MN73has its drain coupled to node N72, its source coupled to ground, and its gate coupled to the word level word line WWL. NMOS transistor MN74has its drain coupled to node N71, its source coupled to ground, and its gate coupled to the RSTW line. The word level word line WWL being at a logic high resets the latch formed from inverters174and176and thus sets the power source latch170, while RSTW being at a logic high sets the latch formed from inverters174and176and thus resets the power source latch170. Note that the inverse of the power source signal PSN is produced at node N72.

The power source latch170circuitry also includes inverter178having its input coupled to node N72to thereby produce the power source signal PS at its output. Inverter178includes PMOS transistor MP73and NMOS transistor MN75. Transistor MP73has its source and body coupled to VDD and its gate coupled to node N72. Transistor MN75has its source coupled to ground, and its gate coupled to node N72. The drains of transistors MP73and MN75are coupled to node N73. Note that the power source signal PS is produced at node N73.

The control circuitry180includes NAND gate182and inverter184. The NAND gate182has inputs coupled to the word line WL and the SETW line, and provides its output to inverter184. A WWLN signal is produced at the output of the NAND gate182, and the WWL signal is produced at the output of the inverter184.

An extended page write opcode or operation is now described with additional reference to flowchart50ofFIG. 3. The extended page write operation is characterized by its ability to write to any size memory page, up to and including a page the size of the entire NVSRAM array99.

The extended page write operation begins at Block51by sending an extended page write opcode to the control logic116, or by sending of signals generated by an external device (such as a microprocessor) based upon the extended page write opcode to the control logic116(Block52). The opcode is sent together with a starting address (Block53), which is a given number of bytes in length. As an example, for a NVSRAM memory104comprised of a 512 k NVSRAM array99, the starting address would be two bytes, meaning that there would be 16 address bits. The opcode is also sent with, following the starting address, data bytes to be written (Block54). The control logic116operates the NVSRAM cells10and their word level switch11corresponding to the starting address to write a number of data bytes corresponding to the word length to the SRAM cells12of the word90at that address (Block54).

If the last data byte written at the received address is the last data byte sent with the extended page write opcode (Block55), then at the next chip deselection, the data that was written into the SRAM cells12of the NVSRAM words90that were addressed during execution of the extended page write opcode are stored into the EEPROM cells of those NVSRAM words90(Block59), and execution of the extended page write opcode is completed (Block60). If the last data byte written to the addressed NVSRAM word90was not the last data byte sent (Block55), and if the address that data byte was written to is not the last address in the NVSRAM array99(Block56), then the address is incremented by one (Block57), and the control logic116sends the next received data byte to be written to the next addressed NVSRAM word90(back to Block54), and this repetition of Blocks54,55,56, and57proceeds until the last byte sent with the opcode has been written. At this point, at the next chip deselection, the data that was written into the SRAM cells12of the NVSRAM words90that were addressed during execution of the extended page write opcode are stored into the EEPROM cells of those NVSRAM words90(Block59), and execution of the extended page write opcode is completed (Block60). Note that if at any point, if the address the most recent byte was written into is the last address in the memory (Block56), and further bytes remain to be written, then the address is reset to the first address in the memory (Block58), and Block54is returned to, with operation proceeding accordingly from there.

A bulk write opcode or operation is now described with additional reference to flowchart70ofFIG. 4. The bulk write operation is characterized by its ability to write to non-sequential addresses.

The bulk write operation begins at Block71by sending a bulk write opcode to the control logic116, or by sending of signals generated by an external device (such as a microprocessor) based upon the bulk write opcode to the control logic116(Block72). The opcode is sent together with a first address (Block73), which is a given number of bytes in length. The opcode is also sent with, following the first address, data bytes to be written to the word90at that first address (Block74). The control logic116operates the NVSRAM cells10and their word level switch11corresponding to the starting first to write the received data bytes to the SRAM cells12at the starting address (Block74).

If the address just written to was the last address sent (Block75), then at the next chip deselection, the data that was written into the SRAM cells12of the NVSRAM words90that were addressed during execution of the bulk write opcode are stored into the EEPROM cells of those NVSRAM words90(Block78), and execution of the extended page write opcode is completed (Block79)

If the address just written to was not the last address sent with the opcode, then the bulk write operation proceeds to send a next address (Block76), and then send the bytes intended for that address and writes the bytes to the SRAM cells12of the NVSRAM word90at that address (Block77). Note again that this address at Block76need not be sequential with the first address (or preceding address), and indeed, may be any address of the NVSRAM array99. Then, Block75is returned to in order to determine whether the address just written to was the last address sent with the opcode. If the address written to was the last address sent with the bulk write opcode, then at the next chip deselection, the data that was written into the SRAM cells12of the NVSRAM words90that were addressed during execution of the bulk write opcode are stored into the EEPROM cells of those NVSRAM words90(Block78), and execution of the extended page write opcode is completed (Block79).

A delayed write opcode is now described with additional reference to flowchart80ofFIG. 5. The delayed write operation begins at Block81by sending a delayed write opcode to the control logic116, or by sending of control signals generated by an external device (such as a microprocessor) based upon the delayed write opcode to the control logic116. Then, an extended page write operation or a bulk write operation is executed (Block82), however the final store operation that stores the data that was written to the SRAM cells12of the NVSRAM words90that were addressed during execution of the extended page write or bulk write is not performed at chip deselection. Instead, the final store operation is performed at a later specified time (Block83), which may be, for example, immediately following the write to SRAM instead of waiting for chip deselection, or at any other desired time.

Understand that for full backward compatibility, the control logic116or external device sending control signals to the control logic116is also fully capable of executing the traditional, prior art NVSRAM operations of read, write, load, and store. Note that when a traditional prior art NVSRAM write operation is performed, the contents of all SRAM cells in the entire NVSRAM array are stored in their respective EEPROM cells upon chip deselection; with the extended page write and bulk write operations disclosed herein, only those SRAM cells that were actually written to by the command have their contents stored in their respective EEPROM cells upon chip deselection. Also, with the delayed write operations disclosed herein, only those SRAM cells that were actually written to by the command or opcode have their contents stored in their respective EEPROM cells at the later specified time. This helps increase longevity and robustness of the NVSRAM memory104, as unselected NVSRAM cells10and words90are not stressed.

Also note that through the use of the word level switches11enabling individual word level access, traditional EEPROM store and load operations may be executed if desired. A traditional EEPROM store is a particular case of bulk page write executed by not incrementing the row address when the address to be written reaches the end of the row (corresponding to the first address sent), and instead having the address roll over to the beginning of the row.