Predicting timing violations

For predicting timing violations, a prediction module predicts a timing violation for a first instruction in a semiconductor device in response to use by the first instruction of a specified sensitized path. The prediction module further mitigates the predicted timing violation.

FIELD

The subject matter disclosed herein relates to timing violations and more particularly relates to predicting timing violations.

BACKGROUND

Semiconductor circuits may occasionally have timing violations, particularly when there are temperature or voltage stresses.

BRIEF SUMMARY OF THE INVENTION

A method is disclosed for predicting timing violations, a prediction module predicts a timing violation for a first instruction in a semiconductor device in response to use by the first instruction of a specified sensitized path. A violation history table may store the specified sensitized path. The prediction module further mitigates the predicted timing violation. A semiconductor device and an apparatus are also disclosed that perform the functions of the method.

DETAILED DESCRIPTION OF THE INVENTION

Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment, but mean “one or more but not all embodiments” unless expressly specified otherwise. The terms “including,” “comprising,” “having,” and variations thereof mean “including but not limited to” unless expressly specified otherwise. An enumerated listing of items does not imply that any or all of the items are mutually exclusive or mutually inclusive, unless expressly specified otherwise. The terms “a,” “an,” and “the” also refer to “one or more” unless expressly specified otherwise. In addition, “optional”, “optionally”, or “or” refer, for example, to instances in which subsequently described circumstance may or may not occur, and include instances in which the circumstance occurs and instances in which the circumstance does not occur.

The computer readable medium may also be a computer readable signal medium. A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electrical, electro-magnetic, magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport computer readable program code for use by or in connection with an instruction execution system, apparatus, or device. Computer readable program code embodied on a computer readable signal medium may be transmitted using any appropriate medium, including but not limited to wireline, optical fiber, Radio Frequency (RF), or the like, or any suitable combination of the foregoing

The computer program product may be shared, simultaneously serving multiple customers in a flexible, automated fashion. The computer program product may be standardized, requiring little customization and scalable, providing capacity on demand in a pay-as-you-go model.

Aspects of the embodiments are described below with reference to schematic flowchart diagrams or schematic block diagrams of methods, apparatuses, systems, and computer program products according to embodiments of the invention. It will be understood that each block of the schematic flowchart diagrams or schematic block diagrams, and combinations of blocks in the schematic flowchart diagrams or schematic block diagrams, can be implemented by computer readable program code. The computer readable program code may be provided to a processor of a general purpose computer, special purpose computer, sequencer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the schematic flowchart diagrams or schematic block diagrams block or blocks.

Although various arrow types and line types may be employed in the flowchart or block diagrams, they are understood not to limit the scope of the corresponding embodiments. Indeed, some arrows or other connectors may be used to indicate only the logical flow of the depicted embodiment. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted embodiment. It will also be noted that each block of the block diagrams or flowchart diagrams, and combinations of blocks in the block diagrams or flowchart diagrams, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer readable program code.

FIG. 1is a schematic block diagram illustrating one embodiment of a semiconductor device100. The semiconductor device100includes a functional unit105, registers110, an input/output115, a violation history table120, a branch history register125, a voltage sensor130, a prediction module135, a temperature sensor140, and a functional unit state register145.

In one embodiment, the semiconductor device100is a processor. Alternatively, the semiconductor device100may be a graphics accelerator, a memory controller, or the like.

The functional unit105, registers110, input/output115, violation history table120, branch history register125, voltage sensor130, prediction module135, temperature sensor140, and functional unit state register145may each comprise semiconductor gates, signal lines, resistors, capacitors, power lines, common lines, and the like. The semiconductor gates, signal lines, resistors, capacitors, power lines, common lines and other elements may be organized as into functional nodes. One or more nodes arranged in a path may perform a function. In one embodiment, if the nodes do not complete the function within a specified number of instruction cycles, the timing for the semiconductor device100is violated. Violations of timing are referred to herein as timing violations.

The functional unit105may be a structural component in a pipelined architecture, including but not limited to, an arithmetic logic unit (ALU), an instruction scheduler, a load address generator, a memory address generator, and forward check logic. The functional unit105may perform operations on data in the registers110. Alternatively, the functional unit105may perform operations on addresses, data sets, and the like. In one embodiment, the functional unit105performs operations in response to the instructions. In a certain embodiment, at least one instruction is a static instruction.

The input/output115may store data to and read data from the registers110. The violation history table120may store one or more sensitized paths associated with a timing violation. Each sensitized path may comprise one or more nodes. Alternatively, the violation history table120may store instructions, combinations of instructions, combinations of instructions and inputs, combinations of instructions and results, or combinations of instructions, inputs, and results associated with one or more sensitized paths. For example, a set of first instructions, as well as inputs, or results for the set of first instructions may be stored for a sensitized path that is susceptible to a timing violation. The results may be branch results, conditional results, operation results, or the like. The inputs may include operands, addresses, and the like.

The branch history register125may store a history of recent states within the functional unit105. For example, the branch history register125may record the last ten instructions executed by the functional unit105, along with inputs and results for the instructions.

The voltage sensor130may measure voltages within or associated with the semiconductor device100. In one embodiment, the voltage sensor130measures a supply voltage for the semiconductor device100. The voltage sensor130may assert a voltage sensor signal if a voltage falls below a voltage threshold.

The temperature sensor140may measure temperatures within or associated with the semiconductor device100. In one embodiment, the temperature sensor140asserts a temperature sensor signal if the temperature exceeds a temperature threshold.

In order to increase the performance of the semiconductor device100, the timing of signals for paths of the semiconductor device100may have tight tolerances. As a result, when some instructions are executed in combination with other recent instructions, inputs, or results along with an elevated temperature or reduced voltage, timing violations may occur. The embodiments described herein predict timing violations before the timing violations occur so that the timing violations may be mitigated. In one embodiment, the prediction module135predicts the timing violations.

FIG. 2is a schematic block diagram illustrating one embodiment of nodes and paths280. A plurality of nodes285is depicted. Results from a first node285amay be communicated to second node285band a third node285c, with results from the second node communicated to the third node285cand results from the third node285ccommunicated to a fourth node285d. The nodes285may collectively complete an operation or function when a last node285such as the fourth node285dcompletes that node's portion of the operation. The nodes285from the initial first node285ato the last node285form a path290. A path290may have a typical or worst case time interval for completing operations. Paths290with typical or worst case time intervals that are substantially similarly to an instruction cycle may be sensitized paths290.

FIG. 3is a schematic block diagram illustrating one embodiment of a computer200and architectural simulation205. The computer200may execute the architectural simulation205.

The computer200may include a processor and memory. The memory may be a computer readable storage medium. The memory may comprise semiconductor storage devices, hard disk drives, optical storage devices, micromechanical storage devices, holographic storage devices, or combinations thereof. The memory may store program code that is executed by the processor to perform the architectural simulation205.

The architectural simulation205may be a simulation of the semiconductor device100. The architectural simulation205may be employed to identify nodes285and paths290of the semiconductor device100that are employed for an instruction or combination of instructions. The architectural simulation205may simulate propagation delays along signal lines, switching times for gates, transistors, and other circuit elements, reflections, crosstalk, and the like of the nodes285and paths290.

The architectural simulation205may determine the time required for each path290to complete a function for an instruction or instructions. In one embodiment, the architectural simulation205is used to identify sensitized paths290in the semiconductor device100for one or more instructions as will be described hereafter.

FIG. 4is a schematic block diagram illustrating one embodiment of a logic analyzer and semiconductor device system125. The logic analyzer210may be used to capture states of a semiconductor device100. In one embodiment, the logic analyzer210is used to determine frequencies of states, related instructions, and the like as will be discussed hereafter. For example, the logic analyzer210may capture a plurality of instructions executed by the semiconductor device100while executing program code.

FIG. 5is a schematic flowchart diagram illustrating one embodiment of a violation history table generation method501. The method501may generate the violation history table120. The method501may be performed by elements of a semiconductor device100, the architectural simulation205, the logic analyzer210, or combinations thereof.

The method501starts, and in one embodiment the method501identifies506an instruction set for the semiconductor device100. In one embodiment, the instruction set may be the most frequently used instructions from one or more programs. The programs may include but are not limited to benchmark programs, target programs for the semiconductor device100, and programs designed specifically to stress the semiconductor device100.

For example, the program may be the SPEC CPU2006 benchmark as defined by the Standard Performance Evaluation Corporation. Alternatively, the program may be a custom program that will be executed by the semiconductor device100.

The method501may further identify506the instruction set using the architectural simulator. The architectural simulator205may record all instructions or combinations of instructions that are executed. In addition, the architectural simulator205may record inputs or results.

Alternatively, the one or more programs may be executed by the semiconductor device100and the logic analyzer210may record the instructions that are executed. In a certain embodiment, a device that is analogous to the semiconductor device100may execute the programs and the logic analyzer210may record the instructions that are executed. The logic analyzer210may also record inputs or results.

The most frequently executed instructions or combinations of instructions executed by the functional unit105may be identified506as the instruction set. For example, the 100 most frequently executed combinations of instructions may be selected as the instruction set. Alternatively, the 10,000 most frequently executed combinations of instructions may be selected as the instruction set. In a certain embodiment, the instruction set includes all possible instructions.

The method501may further identify508inputs or results that are likely to increase the completion time on paths290of the functional unit105. The inputs or results may generate signals that increase crosstalk in a path290, increase current consumption in the path290, increase reflections in the path290, or combinations thereof.

The method501may further identify510sensitized paths290for the instruction set. The sensitized paths290may be within a specified timing threshold of exceeding timing tolerances. The timing threshold may be in the range of 0-5% of an instruction cycle. For example, for a timing threshold of 3%, a path290may be identified as a sensitized path290if the timing for the path290is with 2% of the timing for the instruction cycle.

The method501may identify510paths290that complete an operation or function within the timing threshold of an instruction cycle as sensitized paths290. The operation or function may be in response to instructions, operands, data values, and combinations thereof. In one embodiment, the architectural simulation205may be employed to identify510the sensitized paths. For example, the architectural simulation205may be programmed to identify all paths290for the instruction set that where timing exceeds the timing threshold. Alternatively, the logic analyzer210may be employed to identify504the sensitized paths.

For example, for an instruction cycle of 1,000,000 picoseconds (ps), a path may be identified as a sensitized path290for an instruction if the time for the path290to complete the instruction is within the timing threshold of 1,000,000 ps. In one embodiment, sensitized paths satisfy Equation 1, where T is the time interval for the path290, IC is the length of an instruction cycle, and PT is the timing threshold.
(|IC−T|/IC)>PTEquation 1

In one embodiment, the timing threshold PT is between 0-3% of the total available time for the instruction cycle IC. Alternatively, the timing threshold PT is between 0-8% of the total available time for the instruction cycle IC.

The method501may further generate512the violation history table120. The violation history table120may include all instructions or combinations of instructions, inputs, or results using sensitized paths290such that the sensitized paths are within the timing threshold of the total available time for the instruction cycle.

FIG. 6is a schematic block diagram illustrating one embodiment of a violation history table120. The violation history table120is the violation history table120ofFIG. 1. In the depicted embodiment, the violation history table120includes a plurality of entries230. Each entry230may include one or more instructions235that employ the sensitized paths290.

The instructions235may be a series of instructions. Alternatively, the instructions235may be a set of instructions that may occur in any order.

In one embodiment, each entry230may also include inputs240. In one embodiment, the inputs240must be present for the instructions235to be included in the violation history table120. Alternatively, if the inputs240are present, the likelihood of predicting a timing violation is increased while the inputs240are not required for the instructions235to be included in the violation history table120.

Each entry230may also include results245. The results245may indicate results of the branch instruction, an address generation, a computational result, or combinations thereof. In one embodiment, the results245must be present for the instructions235to be included in the violation history table120. Alternatively, the results245need not be present. However, the likelihood of predicting a timing violation may be increased if the results245are present.

FIG. 7is a schematic block diagram illustrating one embodiment of a branch history register125. The branch history register125may be the branch history register125ofFIG. 1. In the depicted embodiment, the branch history register125includes one or more instructions255. The instructions255may be one or more instructions in an instruction pipeline. The instructions255may be compared with the instructions235of the violation history table120to determine if an instruction or combination of instructions employ a sensitized path290and is likely to cause a timing violation.

In one embodiment, the branch history register125also includes inputs260. The inputs260may be inputs for the instructions255. In a certain embodiment, the branch history register125includes results265. The results265may indicate results of the branch instruction, an address generation, a computational result, or combinations thereof.

FIG. 8is a schematic flow chart diagram illustrating one embodiment of a timing violation prediction method500. The method500may predict future timing violations. The method500may be performed by elements of the semiconductor device100including but not limited to the violation history table120, the branch history registers125, the voltage sensor130, the prediction module135, the temperature sensor140, or the functional unit state register145.

The method500starts, and in one embodiment, the prediction module135determines534a state. The state may be for the semiconductor device100. Alternatively, the state may be for the functional unit105. In one embodiment, the prediction module135latches signals from the functional unit135or semiconductor device100in the branch history register125to determine534the state.

The prediction module135may further determine536if the sensitized paths290are used by a first instruction. In one embodiment, the sensitized paths290are used if the state of the branch history register125matches one or more entries230in the violation history table120. For example, the sensitized paths290are used if the instructions255of the branch history register125match the instructions235in a specified entry230of the violation history table120.

In one embodiment, the inputs260of the branch history table125are also evaluated in determining536if the sensitized paths290are used. For example, the sensitized paths290may be used if the instructions255of the branch history register125match the instructions235in a specified first entry230aof the violation history table120and if one or more inputs260of the branch history table125match one or more inputs240of the specified first entry230aof the violation history table120.

In addition, the results265of the branch history table125may be evaluated in determining536if the sensitized paths290are used. For example, the sensitized paths290may be used if the instructions255and one or more results265of the branch history register125match the instructions235and one or more results245in a specified first entry230aof the violation history table120.

If the sensitized paths290are not used, the prediction module135may continue to determine534the state. If the sensitized paths are used, the temperature sensor140may measure538a temperature within the semiconductor device100, surrounding devices, or combinations thereof. The temperature sensor140may be located within the semiconductor device100. In addition, the temperature sensor140may set a register value, assert a signal line, or combinations thereof when the temperature exceeds a temperature threshold.

In a certain embodiment, the temperature sensor140may be located outside of the semiconductor device100. The temperature sensor140may assert a signal to a contact of the semiconductor device100when the temperature exceeds the temperature threshold.

In addition, the voltage sensor130may measure540one or more voltages within or associated with the semiconductor device100. In one embodiment, the voltage sensor130measures540a supply voltage for the semiconductor device100. The voltage sensor130may set a register value, assert a signal line, or combinations thereof when the supply voltage falls below a voltage threshold.

In an alternate embodiment, the voltage sensor130is located outside of the semiconductor device100. The voltage sensor130may assert a signal to a contact of the semiconductor device100when the supply voltage falls below the voltage threshold.

The prediction module135may predict542a timing violation. In one embodiment, the prediction module135predicts542the timing violation if the sensitized paths290are used. Alternatively, the prediction module135predicts542the timing violation if the sensitized paths are used and an environmental condition is met. The environmental condition may be met if the temperature exceeds the temperature threshold. In an alternate embodiment, the environmental condition is met if a voltage such as the supply voltage falls below the voltage threshold.

If the prediction module135does not predict542the timing violation, the prediction module135may continue to determine534the state. If the prediction module135predicts542the timing violation, the prediction module135may mitigate544the timing violation and continue to determine534the state.

In one embodiment, the prediction module135mitigates544the timing violation associated with the first instruction by adding at least one instruction cycle for the first instruction as will be described hereafter. In an alternate embodiment, the prediction module135mitigates544the timing violation by inserting a stall into one or more instruction pipelines during the execution of the first instruction associated with timing violation. For example, the prediction module135may delay all instructions from completing for one instruction cycle while the first instruction executes.

Alternatively, the prediction module135may mitigate544the timing violation with time borrowing. For example, buffers may be added to a clock signal for one or more latches for the outcome of the first instruction so that the outcome is latched later, mitigating the timing violation.

Alternatively, the prediction module135may mitigate544the timing violation by identifying the first instruction associated with the timing violation. The prediction module135may set a bit to indicate the predicted timing failure for the first instruction. The functional unit state register145may track whether the functional unit105can receive the first instruction. The functional unit state register145may prevent the functional unit105from completing the first instruction for an instruction cycle in response to the first instruction being identified as having a predicted timing failure.

In one embodiment, the prediction module135may mitigate544the timing violation by delaying a tag broadcast for an instruction pipeline for at least one instruction cycle in response to predicting the timing failure. Tags may be used to synchronize one or more instruction pipelines. Delaying a tag broadcast may delay the completion of the first instruction410aassociated with the predicted timing violation.

In a certain embodiment, the prediction module135mitigates544the timing violation by scheduling the first instruction associated with the timing violation earlier. For example, the prediction module135may schedule the first instruction to start earlier in the instruction pipeline relative to other instructions.

By predicting timing violations, the method500may anticipate and mitigate the timing violations, eliminating the need for a time-consuming error recovery. Thus average instruction cycles for the semiconductor device100may be shortened as potential timing violations are predicted and mitigated.

FIGS. 9A-Care schematic block diagrams illustrating one embodiment of mitigating a predicted timing violation. Instruction pipelines400are shown. Although for simplicity two instruction pipelines400are depicted, any number of instruction pipelines400may be employed. The instruction pipelines400may be embodied in the functional unit105.

Each instruction pipelines400includes one or more instructions410organized an execution order. The instruction pipelines400are depicted as divided by instruction cycles415. One of skill in the art will recognize that the instruction pipelines400need not be divided by instruction cycle415. Instructions410may require one or more instruction cycles415to execute. The instruction pipelines400include program counters420. The program counters420indicate the instruction410that is currently completing. Portions of instructions410may be executed throughout the instruction pipeline400.

InFIG. 9A, the first instruction410ais identified as having a predicted timing violation. The predicted timing violation will be mitigated as will be shown hereafter. InFIG. 9B, the timing violation is mitigated by adding one instruction cycle for the first instruction410a. Thus when the first instruction410aexecutes has shown inFIG. 9C, the first instruction410awill have an additional instruction cycle415to complete rather than the one instruction cycle415as originally scheduled inFIG. 9A. In certain embodiments, two or more instruction cycles415may be added to the first instruction410ato mitigate the predicted timing violation.

FIG. 10is a schematic block diagram illustrating one alternate embodiment of mitigating a predicted timing violation. The first instruction410aassociated with the timing violation ofFIG. 9Ais shown being executed. In order to mitigate the timing violation, at least a first instruction pipeline400ais stalled so the first instruction410ahas additional time to complete. The instruction pipelines400may be stalled by pausing an instruction clock. In a certain embodiment, only one instruction pipeline400such as the first instruction pipeline400ais stalled. Instruction pipeline400may be stalled for one or more instruction cycles415. Alternatively, the instruction pipeline400may be stalled for a portion of an instruction cycle415.