Communications apparatus for encoding and decoding multiplexed optical signal

A fiber optic multiplexing controller for transmitting a separate original electrical signal to each of a plurality of signal receiving devices. Each separate original electrical signal originates from one or a plurality of signal sending units. A transmit section of the controller includes an encoder for encoding the separate original electrical signals into a single multiplexed electrical signal. The transmit section further includes a fiber optic transmitter for converting the multiplexed electrical signal to an optical signal. Thereafter, the optical signal is transmitted via fiber optics to a receive section of another identical controller. This receive section includes an optical receiver, provided for the purpose of receiving the transmitted optical signal and converting it to a multiplexed electrical signal. The multiplexed signal, whether electrical or optical, is made up of discrete portions. Each portion of the signal is devoted to a predetermined one of the separate original electrical signals. The receive section further includes a decoder for decoding or de-multiplexing the received multiplexed electrical signal into a corresponding number of received electrical signals, one for each of the receiving devices, and for forwarding the signals via drive circuits provided to communicate with the devices.

BACKGROUND OF THE INVENTION 
This invention relates to controllers or interfaces between signal sending 
units and signal receiving devices, and in particular to controllers 
employing multiplexed fiber optic transmission of the necessary signals, 
and the accompanying conversions and multiplexing from original electrical 
signals to optical signals and back to electrical signals. 
Certain types of equipment employ electrical devices, such as motors and 
solenoids, which perform various functions and which are selectively 
energizable by means such as relays. These relays are often controlled by 
digital control signals provided over electrically conducting wires, 
either from an electronic computer or from some other type of signal 
generating control, such as a human operator. In addition, these devices 
experience conditions which require monitoring and possibly response by 
the computer or the operator, in effect evidencing a need to transmit data 
back to the computer or the operator. 
For example, certain types of commercial and military aircraft of advanced 
design employ relay-controlled electrical load devices, such as motors 
located in various separated parts of the aircraft, which are energizable 
in response to switches operated by a pilot. In addition, such devices are 
commonly energizable according to commands, generally low power digital 
electrical signals, from a control computer, which may be remotely 
situated in the cockpit. In turn, these devices may experience 
over-current conditions, or for some other reason be forced to trip to an 
open state, and the operator or computer need to be informed of these 
conditions so as to enable a responsive action. Further, the operator or 
computer even needs to be aware of the state of the contacts, that is, 
whether they are open or closed. Hence control signals need to flow both 
from and to the operator or computer. In the past, these control signals 
have been transmitted via individual wires, usually at least one pair of 
wires for each of the devices to be controlled. However, this arrangement 
of at least a separate pair of wires for each device to be controlled had 
the undesirable effect of adding a substantial amount of weight to the 
aircraft for each controlled device, in addition to the problems of 
control cable routing and mounting competition for the wiring space within 
an aircraft. 
This invention relates to improvements to the devices set forth above and 
to solutions to the problems raised thereby. 
SUMMARY OF THE INVENTION 
The invention includes a fiber optic communications system for 
communicating signals between two sets of components within the system. 
The system includes a multiplexing controller for transmitting a separate 
original electrical signal to each of a plurality of devices, positioned 
in each of a control element and a data management element. Fiber optics 
provide data transmission at much lower weight and volume for a given 
volume of data transferred. In the present invention, each separate 
original electrical signal to be transmitted to a receiving device 
originates from one or a plurality of signal sending units. That is, the 
invention can be applied whether the signal is a control signal 
originating with the computer or operator referred to above, or is 
indicative of a trip condition or of the status of the contacts 
themselves, that is, whether they are open or closed, in one or more of 
the relays or other remote devices. The fiber optic multiplexing 
controller has a transmit section that includes encoding means for 
receiving and encoding the separate original electrical signals into a 
single multiplexed signal. The multiplexed signal is made up of discrete 
portions, each devoted to a predetermined one of the original signals. The 
transmit section further includes optical transmission means for receiving 
the multiplexed electrical signal and converting it to an optical signal. 
Thereafter the optical signal is transmitted via fiber optic cables to a 
receive section of another similar controller located remote from the 
first controller. The receive section includes an optical reception means, 
which receives the transmitted optical signal and converts it to a 
multiplexed electrical signal again comprising discrete portions, again 
each of those portions being devoted to a predetermined one of the 
separate original electrical signals. The receive section further includes 
decoding means for decoding the received multiplexed electrical signal 
into a corresponding number of received electrical signals, one for each 
of the receiving devices. Each of the received electrical signals 
corresponds to one of the separate original electrical signals. Finally, a 
plurality of output drive circuits is provided, one for each of the 
receiving devices, for receiving the now de-multiplexed electrical control 
signals and communicating them to the receiving devices. 
The encoding means includes synchronization means for generating a 
synchronization channel and combining it with the original electrical 
signals into the single, multiplexed electrical signal. This 
synchronization channel is arranged first in order of channels transmitted 
within the multiplexed electrical signal. Both the transmit section and 
the receive section include clock means so as to be able to use that 
synchronization channel to ensure that the proper separate original 
electrical signal finally arrives at the intended receiving device. 
Generally, the original electrical signals are in digital form, that is, 
each assumes either an "on" state or an "off" state. Likewise, the devices 
to be controlled require signals controlling them to be in digital form, 
assuming either an "on" state and an "off" state. Hence the optical 
transmission means includes means for converting the "on" states of the 
original electrical signals, as occurring in the multiplexed electrical 
signal from the encoding means, to a period of a predetermined switching 
frequency in the optical signal, and for converting the "off" states of 
the original electrical signals, as occurring in the multiplexed 
electrical signal, to a period of a predetermined but much lower frequency 
in the optical signal. The term "frequency" used here indicates the 
turning on and off of an LED a number of times per second. Hence, when the 
original electrical signal is "on", the LED is turned on and off very 
quickly, whereas when the original electrical signal is "off", the LED is 
turned on and off relatively very slowly. To finish out the process on the 
receive end, the optical reception means includes means for converting the 
periods of high and low frequency to a multiplexed electrical signal as 
needed by the decoding means for decoding into electrical control signals 
to effect control of the devices. 
It is thus an object of the invention to provide a fiber optic multiplexing 
controller for interfacing between one or more signal sending units, such 
as a control computer or a bank of switches, and a number of devices to be 
controlled, such as relays or remote control circuit breakers.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
Referring now to FIG. 1, there is shown a control system 10 for controlling 
a plurality of load devices L1, L2, . . . Ln, such as load control relays 
or remote control circuit breakers. The invention is especially well 
adapted for use in aircraft control systems, but could also find equally 
suitable application in other control systems, such as on a factory floor. 
The control system 10 includes a CPU or other control element 12 connected 
to a data management element 14 via a pair of fiber optic links 16 and 18. 
One of the fiber optic links, link 16, carries control signals to the data 
management element 14. The data management element 14 in turn is connected 
to each of the load devices L1, L2, . . . Ln by a control link 20 for 
transmitting control signals to the load devices, that is, open and close 
signals, and by feedback links 22 and 24 to transmit information about the 
condition of the devices back to the data management element 14. In the 
embodiment shown in FIG. 1, for instance, feedback link 22 transmits a 
signal as to whether the particular device is open or closed, while link 
24 transmits a signal that the particular device is in a trip condition. 
This feedback information is then carried back to the control element 12 
via fiber optic link 18. 
As indicated by reference to FIG. 1, the preferred embodiment of the 
present invention contemplates two communications apparatuses 32, one 
being positioned in the control element 12 and a second being located in 
the data management element 14, each having a transmit section 26 as shown 
in FIG. 2 FIG. 3 shows an entire communications apparatus 32, having both 
a transmit section 26 and a receive section 28, as generally required to 
handle communications in both directions, that is, of control signals from 
the control element 12 to the devices L1, L2, . . . Ln, and of feedback or 
condition signals in the reverse direction. 
TRANSMIT SECTION 
As indicated in FIG. 2, each transmit section 26 is connected to receive 
signals from a signal sending unit 36, whether that signal sending unit be 
control element 12 or one of the load devices L1, L2, . . . Ln. Each of 
the signals is predetermined to be related to one of the load devices L1, 
L2, . . . Ln, whether an open or close signal from the control element 12 
or a trip or open/close indication from the load devices L1, L2, . . . Ln. 
The transmit section 26 includes an input conditioning circuit 34 for 
receiving and conditioning all of the signals to be transmitted. The 
conditioning performed here includes switch de-bouncing since the circuit 
is designed to be connectable to a control console consisting of switches 
operated by a human operator or pilot, besides being capable of being 
connected to a control computer. In addition, there may likely occur some 
bounce in the load devices L1, L2, . . . Ln on trip or opening and closing 
of the contacts. Further, the conditioning includes general noise 
reduction and filtering. 
From the input conditioning circuit 34, the now-conditioned signals 
continue to a latch circuit 38, which latches the signals in the state 
they are in at the time that the signal is assembled as will be described 
below. That is, latch circuit 38 prevents the state of each signal from 
changing during the period of transmission, since to allow any such change 
of state would corrupt the transmission signal. From there, the 
now-latched signals are passed to an encode circuit 40, where several 
signals relating to the several devices are combined into a serial data 
word, that is, the signals are multiplexed together into a multiplexed 
electrical signal for later transmission. 
The output of the encode circuit 40, that is, the multiplexed electrical 
signal, is sent to a combinational logic and transmitter circuit 42, which 
drives an optical transmitter 44 in converting the multiplexed electrical 
signal to a multiplexed optical signal for transmission via the fiber 
optic link 30. 
Each of the above elements within the transmit section 26 is synchronized 
with each other by connection to a system clock 46. The importance of 
synchronization and the system clock 46 will be set forth in more detail 
subsequently herein. 
RECEIVE SECTION 
As indicated, the optical signal referred to above is transmitted via the 
fiber optic link 30 to the receive section 28 located in the opposite 
communications apparatus 32, as shown in FIGS. 1 and 2. The fiber optic 
link 30 is connected to an optical receiver 48, wherein the multiplexed 
optical signal is converted into a multiplexed electrical signal. From the 
optical receiver 48, the multiplexed electrical signal is sent to a signal 
conditioning circuit 50, mainly for the purpose of conditioning the logic 
signal from the optical receiver 48, and making the signal a more perfect 
square wave. Generally, elimination of noise at this point will not be 
necessary because of the clean and noise-free nature of fiber optic 
transmission. 
The conditioned signal then proceeds to a decode circuit 52, which decodes 
the multiplexed electrical signal into signals relating to each of the 
load devices L1, L2, . . . Ln, and passes the signals on to a number of 
output drive circuits 54 that is the same as the number of receiving 
devices. Each relevant signal is thus communicated to the appropriate 
receiving device 56. 
Similar to the transmit section 26, the receive section 28 includes a 
system clock 58 for synchronizing the signal conditioning circuit 50 and 
the decode circuit 52 properly with the signal. 
DETAIL OF COMMUNICATIONS APATUS 
The details of the preferred embodiment of the communications apparatus 32 
explained generally above and shown in FIG. 2 are shown in FIGS. 3A, 3B, 
3C and 3D, which show a single circuit including one transmit section 26 
and one receive section 28, both connected to a single system clock 59 for 
synchronizing the various parts within the particular sections. This 
embodiment would most advantageously be applied to the data management 
element 14 shown in FIG. 1, because it shows a number of discrete inputs 
and a number of discrete outputs. Where there are preferred or required to 
be any differences between the communications apparatus 32 applied to the 
data management element 14 and the apparatus applied to the control 
element 12, those will be stated. 
Referring now to FIGS. 3A, 3B, 3C and 3D, the signal sending unit 36 
comprises a bank of switches 60. While FIG. 3A shows these switches 60 as 
physical switches, they may alternatively be any type of switch means 
including switches of a semiconductor type. Generally each switch shown 
corresponds to an open/close indication or a trip indication from one of 
the load devices L1, L2, . . . Ln. Further, while there are shown a total 
of 16 such switches 60, it will become apparent subsequently herein why 
not all of these inputs are practically usable. 
Assuming that the apparatus 32 is installed in the data management element 
14, shown in FIG. 1, the switches 60 represent inputs from the devices L1, 
L2, . . . Ln, as stated above. If the apparatus 32 were installed in the 
control element 12, the switches 60 could represent either a bank of 
switches to be operated by a human operator, such as a pilot, or a number 
of signal lines from a control computer. 
As indicated above, an input conditioning circuit 34 is connected to the 
signal sending unit 36. In FIG. 3A, the input conditioning circuit 34 
comprises integrated circuits U1, U4 and U7, which in this embodiment are 
MC14490 chips. These are provided for de-bouncing the input signals, since 
bounce in the switches 60 could cause substantial false indications in the 
apparatus. Further, these integrated circuits perform a noise elimination 
function, which would be applicable even if the signal sending unit were 
not a bank of switches, but rather a source of logic signals such as a 
computer. Three MC14490 chips are provided since each such chip is capable 
of handling six signal lines, and there are a total of 16 such signal 
lines from the signal sending unit 36 to be conditioned. 
As further indicated above, the signals are then passed to a latch circuit 
38. Again, the purpose of the latch circuit 38 is to prevent the state of 
any signal from changing during the period of transmission. In FIG. 3A, 
latch circuit is shown to include two integrated circuits U2 and U5. These 
ICs are preferred to be 74LS273 chips, since they are low cost, low power, 
widely available latching circuits. Two such chips are required because 
each is capable of handling eight signal lines, and there are a total of 
16 such signal lines from the conditioning circuit 34 to be latched. 
From the latch circuit 38, the signals are sent to the encode circuit 40 
for combining the signals into a serial data word, that is, multiplexing 
the signals together into a multiplexed electrical signal for later 
transmission. As shown in FIG. 3B, the encode circuit 40 includes two 
encoding integrated circuits U3 and U6. These ICs are preferred to be 
counter chips such as 74LS151 chips. These chips have the capability of 
encoding 8 signals, received on inputs I0 through I7, into one, resulting 
in the use of two such chips in this circuit. Notice that each chip has 
eight signal inputs I0 through I7 and only one signal output Z, due to its 
encoding function. Notice also, though, that U3 has only seven signal 
lines leading from U2 into it. In the embodiment shown in FIGS. 3A and 3B, 
the first signal from U2 is not encoded with the others, since the first 
bit always sent is a synchronization pulse or bit. In the present 
embodiment this first output signal from U2 is held aside as a spare at 61 
(FIG. 3B). The first input I0 into U3 is then tied high. With this input 
tied high, the first bit of data ultimately transmitted by the optical 
transmitter 44 is always a certain predetermined state, in this case 
because of the logic the first bit transmitted will be a low signal, so 
that the receive section can synchronize on that bit. This effect is 
similar to a start bit in RS-232 communications. 
Assuming 16 total communication channels, this synchronization pulse takes 
up the first of these channels, leaving a maximum of 15 communication 
channels for actual data. Assuming that there are two channels required 
for each load device L1, L2, . . . Ln, that is, trip and open/close, this 
allows for reporting back to the control element 12 with he status of up 
to seven such load devices over a single fiber optic link 30 (FIG. 2). 
Within the combinational logic and transmitter circuit 42, the output 
signals from the two encode chips U3 and U6 are both sent to a logic chip 
U8, wherein NAND gates 62, 64 and 66 arbitrate the order of signals sent, 
based on signals sent from the system clock 59 via a divider chip U11 
(FIG. 3A). As shown in FIG. 3A, the system clock 59 includes a timer 
portion 59a and an integrated circuit U28. Chip U28 is preferably a 
divider chip such as a 74LS197. Timer portion 59a includes generally 
conventionally arranged elements of a clock timer, including a crystal 
oscillator CA1 and RC networks 68 and 70 connected with inverters 72, 74 
and 76. The signal from this clock timer portion 59a is divided into 
various proportional parts by U28. The Q3 output divides the timer ticks 
by 16, while the Q0 output divides the timer ticks by 2. The Q3 output, 
which divides the clock input by 16, is used as a clock input to 
integrated circuit U11, which as also preferably a divider chip such as 
the 74LS197. Chip U11 has divider outputs Q0, Q1 and Q2, which are 
successively further divided timer outputs, dividing the clock input by 2, 
4 and 8 respectively. These outputs control the inputs S0, S1 and S2 
respectively of encoder chips U3 and U6, thus enabling the encoder chips 
to encode the data input to them into a single output line. Chip U11 
further has a divider output Q3 which divides the clock input by 16. This 
output Q3 of chip U11 is used by NAND gates 62, 64 and 66 to determine 
that the output Z of encoder chip U3 is taken first, and thereafter the 
output Z of encoder chip U6, in controlling the diode D1. Thus it is 
ensured that the signals from the first seven switches 60 are first sent, 
followed by the signals from the last eight switches 60. 
From logic chip U8, the output of the NAND gates 62 and 64 are sent to a 
driver chip U9, which includes a NAND gate 78, connected so as to drive a 
transistor Q1. The transistor Q1 acts as a drain, draining current from 
the voltage source V1 when energized and, when not energized, allowing the 
current to flow through the light emitting diode D1 so as to send a light 
signal outward via fiber optic link 18 (FIG. 1) to a similar 
communications apparatus 32 at the control element 12. The Q0 output of 
divider chip U28 divides its clock input by 2, and is the frequency used 
by NAND gates 62, 64 and 78 to flash the diode D1 when it is on. 
The shape of an example signal being transmitted is shown in FIG. 4. In 
that figure, a "low" value, or a wave including a frequency as shown in 
the figure, corresponds to a logical "1", whereas a "high" value, that is, 
one that has no frequency within itself, corresponds to a logical "0". As 
indicated in that figure, the first "1" signal 80 constitutes the 
synchronization pulse. Thereafter, each "1" signal 82, 84 and 86 indicates 
the presence of a condition to be tested for in one of the load devices 
L1, L2, . . . Ln, and which load device is indicating the condition. That 
is, which channel has a "1" value signifies which device and which 
condition within that device is indicated. In that figure, bits 3, 6 and 9 
have a frequency and thus indicate that the devices corresponding to those 
bits are present. The line 87 indicates a very short pulse to signify the 
beginning of the reset period, during which all inputs 60 are again sensed 
in preparation for the next transmission period. 
The signal transmitted by the diode D1, via fiber optic link 30 (FIG. 2), 
is received in a receive section similar to the receive section 28 shown 
in FIGS. 3C and 3D, although located in the control element 12. Since the 
actual receive section 28 shown in FIGS. 3C and 3D is configured to be 
located in the data management element 14, it will be described with 
respect to that environment, as connected to the load devices L1, L2, . . 
. Ln, with any necessary differences between that environment and the 
environment of the control element 12 stated specifically. 
A signal similar to that referred to above, except carrying control signals 
to the load devices L1, L2, . . . Ln, is received via the fiber optic link 
30 (FIG. 2) at the light sensitive transistor 88, referring now to FIGS. 
3C and 3D, and there converted from an optical signal to an electrical 
signal. From the light sensitive transistor 88, the electrical signal is 
passed to a signal conditioning circuit 50, embodied here by a pair of 
buffers 90, provided for the purpose of conditioning the signal from the 
transistor 88 into a clean logic signal. Although one buffer 90 would be 
sufficient to accomplish the conditioning function, two such buffers are 
supplied here because each such buffer has the effect of inverting the 
signal, but it is desired to have a non-inverted signal after the 
conditioning. Therefore the first buffer inverts the signal, and the 
second one inverts it again, thereby restoring it to its original sign. 
From there, the signal is sent to the decode circuit 52, which first 
comprises integrated circuits U10 and U22. Chip U10 is preferably a 
74LS123, while chip U22 is preferably a 74LS194. These are included for 
the purpose of determining whether the particular portion of the signal 
presently being received from the buffers 90 is a frequency or a low 
signal. That is, chips U10 and U22 examine the frequency being received 
and determine whether it is a relatively faster frequency, being flashed 
quickly by the output Q0 of divider chip U28, indicating that the 
particular relevant switch 60 is closed, or whether it is a relatively 
slower frequency, indicating that it is not being flashed, signifying that 
the particular relevant switch 60 is open. 
Decode circuit 52 further includes decoder integrated circuits U15, U18 and 
U19. Similar to chips U11 and U28, chip U15 is preferably a 74LS197 
divider chip, while U18 and U19 are preferably 74LS259 chips, which take 
basically one input and break it up into its eight relevant parts. Similar 
to the encode circuit the detail of which is set forth above, chip U15 
receives clock pulses from chip U28 and divides them based on which output 
is taken. The four outputs Q0, Q1, Q2 and Q3 divides the pulses input by 
2, 4, 8 and 16 respectively. The Q0, Q1 and Q2 outputs drive the A0, Al 
and A2 inputs of each of the chips U18 and U19, with the actual chip 
selected to transmit by the Q3 output of U15. 
Thus, again employing pulses from the system clock 59, these decoder chips 
U18 and U19 determine which part of the mutliplexed signal applies to the 
each of the load devices L1, L2, . . . Ln. The now de-multiplexed signal 
is sent along to the proper receiving device 56 via output drive circuits 
54. In the case shown in FIGS. 3C and 3D, since the outputs are directed 
to load devices L1, L2, . . . Ln, the output drive circuits include op 
amps as shown. 
If the receiving device 56 were a device such as control element 12, some 
conventional type of buffer and latch arrangement would be appropriate, to 
allow the control element to read the presented information in its own 
time. 
While the apparatus hereinbefore described is effectively adapted to 
fulfill the aforesaid objects, it is to be understood that the invention 
is not intended to be limited to the particular preferred embodiments of 
fiber optic multiplexing communications apparatus herein set forth. 
Rather, it is to be taken as including all reasonable equivalents without 
departing from the scope of the appended claims.