Thin film transistor, thin film transistor array panel, and display device

A thin film transistor is provided, which includes: a gate electrode (124); a gate insulating layer (140) formed on the gate electrode; a semiconductor layer (154) formed on the gate insulating layer and disposed opposite the gate electrode; a source electrode (173) and a drain electrode (175) that are formed at least in part on the semiconductor layer and face each other, a passivation layer (180) formed on the source electrode, the drain electrode, and a portion of the semiconductor layer that is not covered with the source electrode and the drain electrode; and a shielding electrode (196) formed on the passivation layer and disposed on a region between the source electrode and the drain electrode.

TECHNICAL FIELD

The present invention relates to a thin filmtransistor, a thin film transistor array panel, and a display device.

BACKGROUND ART

A flat panel display such as a liquid crystal display (LCD) and an organic light emitting display (OLED) includes a display panel, drivers for driving the display panel, and a controller for controlling the drivers.

A display panel for an LCD or an OLED generally includes a plurality of pixel electrodes arranged in a matrix and a common electrode covering an entire surface of the display panel and supplied with a common voltage. Between the pixel electrodes and the common electrode, an LCD further includes a liquid crystal (LC) layer having dielectric anisotropy, while an OLED includes a plurality of organic light emitting members.

The display panel further includes a plurality of switching elements such as thin film transistors (TFTs), and a plurality of gate lines and data lines. The gate lines transmit gate signals, each having a gate-on voltage for turning on the switching elements and a gate-off voltage for turning off the switching elements, and the data lines transmit data signals.

The drivers of the display device include a gate driver generating the gate signals and applying the gate signals to the gate lines and a data driver generating the data signals and applying the data signals to the data lines. The gate driver and the data driver may include a plurality of driving integrated circuit (IC) chips mounted on the display panel or on flexible printed circuit (FPC) films, which in turn are attached to the display panel.

In addition, the drivers, particularly the gate driver is often integrated on the display panel along with the switching elements for increasing an effective display area, decreasing the size of the flame, and reducing the manufacturing cost. At this time, the gate driver includes a plurality of TFTs.

Hereinafter, the TFTs connected to the pixel electrodes are referred to as pixel TFTs, while the TFTs of the gate driver are referred to as driver TFTs. Each of the TFTs has a gate electrode, a source electrode, and a drain electrode.

DISCLOSURE OF INVENTION

Technical Problem

In the meantime, the TFTs disposed under the common electrode are affected by the common voltages applied to the common electrode.

The threshold voltage (Vt) of a TFT is represented as:
Vt=Vt0+γ(√{square root over (2φf+Vcs)}−√{square root over (2φf)})  (1)

Here, Vcs=Vcom—Vs (where Vcom is a common voltage and Vs is a voltage of the source electrode of the TFT), Vt0 indicates the threshold voltage when Vcs=0, v is a manufacturing process parameter, and φf is a physical parameter constant.

As shown in Equation (1), the threshold voltage (Vt) depends on Vcs and thus on the common voltage (Vcom).

In particular, when the common voltage (Vcom) becomes high to increase the threshold voltage (Vt), a driving voltage applied to the gate electrode of the TFT for turning on the TFT is increased and thus the currents in a turn-on state of the TFT are decreased, thereby decreasing the operational efficiency of the TFT.

In addition, a parasitic capacitor generated between the common electrode and the gate electrode decreases an output voltage of the TFT. For example, when the TFT is a driver TFT disposed at an output terminal of the gate driver, the output voltage corresponds to a gate-on voltage for turning on pixel TFTs and the decreased magnitude of the gate-on voltage may not turn on the pixel TFTs.

Furthermore, the driver TFT is much larger than the pixel TFT such that the driver TFT has a channel width equal to 7,000-10,000 microns. Therefore, the parasitic capacitance between the common electrode and the gate electrode becomes very large. For an example of a low-voltage driving LC, the parasitic capacitance (Cgs) between the gate electrode and the source electrode and the parasitic capacitance (Cgc) between the gate electrode and the common electrode have a relation,
Cgs:Cgc=4.6:1.  (2)

Relation (2) shows that the parasitic capacitance (Cgc) between the gate electrode and the common electrode is very large to have an effect on the operation of the TFT.

The present invention is provided for solve the problems of the conventional art.

Technical Solution

A thin film transistor is provided, which includes: a gate electrode; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer and disposed opposite the gate electrode; a source electrode and a drain electrode that are formed at least in part on the semiconductor layer and face each other; a passivation layer formed on the source electrode, the drain electrode, and a portion of the semiconductor layer that is not covered with the source electrode and the drain electrode; and a shielding electrode formed on the passivation layer and disposed on a region between the source electrode and the drain electrode.

The shielding electrode may be electrically isolated.

Alternatively, the shielding electrode may be supplied with a predetermined voltage and the predetermined voltage supplied to the shielding electrode may be equal to or lower than a ground voltage or may be a negative voltage.

The shielding electrode may include IZO or ITO and may have a shape of horseshoes.

The passivation layer may include organic insulator.

A thin film transistor array panel is provided, which includes: a gate line and a data lie; a first thin film transistor including a control electrode, an input electrode, an output electrode, and a channel portion disposed between the input electrode and the output electrode and generating a gate signal to be applied to the gate line; a second thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode, and a channel portion disposed between the source electrode and the drain electrode and transmitting a data signal from the data line in response to the gate signal from the gate line; a pixel electrode connected to the drain electrode to receive the data signal; and a first shielding electrode disposed on the channel portion of the first thin film transistor.

The first shielding electrode may be electrically isolated.

The first shielding electrode may be supplied with a predetermined voltage. The predetermined voltage supplied to the first shielding electrode may be equal to or lower than a ground voltage, may be a negative voltage, or may have a magnitude for turning off the second thin film transistor.

The first shielding electrode may include the same layer as the pixel electrode.

The thin film transistor array panel may further include a second shielding electrode disposed on the channel portions of the second thin film transistor and including the same layer as the pixel electrode.

The thin film transistor array panel may further include an insulating layer disposed between the first and the second thin film transistors and the first and the second shielding electrodes.

The insulating layer may include organic material.

A display device is provided, which includes: a gate line and a data line; a first thin film transistor including a channel portion and generating a gate signal to be applied to the gate line; a second thin film transistor transmitting a data signal from the data line in response to the gate signal from the gate line; a pixel electrode connected to the second thin film transistor to receive the data signal; a shielding electrode disposed on the channel portion of the first thin film transistor; and a common electrode facing the pixel electrode.

The shielding electrode may face the common electrode.

The shielding electrode may be supplied with a predetermined voltage lower than a voltage applied to the common electrode and the predetermined voltage supplied to the shielding electrode may have a magnitude for turning off the second thin film transistor.

The shielding electrode may include the same layer as the pixel electrode.

The display device may further include a dielectric layer disposed between the shielding electrode and the Common electrode and the dielectric layer may include a liquid crystal layer.

Advantageous Effects

The shielding electrodes block the effect of a common voltage applied to the Common electrode on the channels of the TFTs to prevent the deterioration of the threshold voltage of the TFTs. In addition, the application of the predetermined voltage such as a gate-off voltage lower than a common voltage to the shielding electrodes reduces a driving voltage of the TFTs and advances the switching time of the TFTs, thereby increasing the efficiency of input voltages supplied to the TFTs and the efficiency of the operation of the TFTs.

Furthermore, the employment of the shielding electrode does not increase the manufacturing cost or do not complicate the manufacturing process since the shielding electrodes are formed along with the pixel electrodes.

BEST MODE FOR CARRYING OUT THE INVENTION

In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numerals refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being on another element, it can be directly on the other element or intervening elements may also be present In contrast, when an element is referred to as being directly on another element, there are no intervening elements present

Then, TFTs, TFT array panels, and display devices according to embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1is a block diagram of a display device according to an embodiment of the present invention, andFIG. 2is an equivalent circuit diagram of a pixel of an LCD illustrated as an example of a display device according to an embodiment of the present invention.

Referring toFIG. 1, a display device according to an embodiment includes a display panel unit300, a gate driver400and a data driver500that are connected to the panel unit300, a gray signal generator800connected to the data driver500, and a signal controller600controlling the above elements.

Referring toFIG. 1, the panel unit300includes a plurality of display signal lines Gl-Gnand Dl-Dmand a plurality of pixels PX connected thereto and arranged substantially in a matrix to form a display area DA. Referring toFIG. 2, a panel unit300for an LCD includes lower and upper panels100and200and a LC layer3interposed therebetween. A panel unit300for an organic light emitting display (OLED) may include a single panel.

The display signal lines Gl-Gnand Dl-Dminclude a plurality of gate lines Gl-Gntransmitting gate signals (also referred to as scanning signals), and a plurality of data lines Dl-Dmtransmitting data signals. The gate lines Gl-Gmextend substantially in a row direction and substantially parallel to each other, while the data lines Dl-Dmextend substantially in a column direction and substantially parallel to each other.

Each pixel PX includes at least a switching element (not shown) such as a TFT and at least a capacitor (not shown).

Referring toFIG. 2, each pixel PX of the LCD includes a switching element Q connected to the signal lines Gl-Gnand Dl-Dm, and a LC capacitor CLCand a storage capacitor CSTthat are connected to the switching element Q. The display signal lines G1-Gnand Dl-Dmare disposed on the lower panel100and the storage capacitor CSTmay be omitted if unnecessary.

The switching element Q including a TFT is provided on the lower panel100and has three terminals: a control terminal connected to one of the gate lines Gl-Gn; an input terminal connected to one of the data lines Dl-Dm; and an output terminal connected to both the LC capacitor CLCand the storage capacitor CST.

The LC capacitor CLCincludes a pixel electrode190provided on the lower panel100and a common electrode270provided on the upper panel200as two terminals. The LC layer3disposed between the two electrodes190and270functions as dielectric of the LC capacitor CLC. The pixel electrode190is connected to the switching element Q, and the common electrode270is supplied with a common voltage Vcom and covers an entire surface of the upper panel200. UnlikeFIG. 2, the common electrode270may be provided on the lower panel100, and both electrodes190and270may have shapes of bars or stripes.

The storage capacitor CSTis an auxiliary capacitor for the LC capacitor CLC. The storage capacitor CSTincludes the pixel electrode190and a separate signal line, which is provided on the lower panel100, overlaps the pixel electrode190via an insulator, and is supplied with a predetermined voltage such as the common voltage Vcom. Alternatively, the storage capacitor CSTincludes the pixel electrode190and an adjacent gate line called a previous gate line, which overlaps the pixel electrode190via an insulator.

For color display, each pixel PX uniquely represents one of primary colors (i.e., spatial division) or each pixel PX sequentially represents the primary colors in turn (i.e., temporal division) such that spatial or temporal sum of the primary colors are recognized as a desired color. An example of a set of the primary colors includes red, green, and blue colors.FIG. 2shows an example of the spatial division that each pixel PX includes a odor filter230representing one of the primary colors in an area of the upper panel200facing the pixel electrode190. Alternatively, the color filter230is provided on or under the pixel electrode190on the lower panel100.

One or more polarizers (not shown) are attached to at least one of the panels100and200.

Each pixel PX for the OLED may include a switching transistor (not shown) connected to the display signal lines Gl-Gnand Dl-Dm, a driving transistor (not shown) and a storage capacitor (not shown) connected thereto, and a light emitting diode (not shown) connected to the driving transistor. The light emitting diode includes a pixel electrode (not shown), a common electrode (not shown), and a light emitting member (not shown) interposed therebetween.

Referring toFIG. 1again, the gray signal generator800generates a plurality of gray signals related to the transmittance of the pixels PX. For an LCD, the gray signal generator800generates two sets of a plurality of gray voltages. The gray voltages in one set have a positive polarity with respect to the common voltage Vcom, while those in the other set have a negative polarity with respect to the common voltage Vcom.

The gate driver400is connected to the gate lines Gl-Gnof the panel unit300and generates gate signals for application to the gate lines Gl-Gnhaving two levels equal to a gate-on voltage Von and a gate-off voltage Voff, respectively. The gate driver400is integrated on the panel unit300and includes a plurality of driving circuits (not shown). Each of the driving circuits is connected to one of the gate lines Gl-Gnand includes a plurality of, for example, about fourteen thin film transistors. However, the gate driver400may include a plurality of integrated circuit (IC) chips (not shown) mounted on the panel unit300or mounted on flexible printed circuit (FPC) films (not shown) that are attached to the panel unit300.

The data driver500is connected to the data lines Dl-Dmof the panel unit300and applies data voltages, which are selected from the gray voltages supplied from the gray signal generator800, to the data lines Dl-Dm. The data driver500may be also integrated on the panel unit300, or mounted on the panel unit300or on FPC films (not shown) that are attached to the panel unit300in forms of IC chips.

The drivers400and500or the FPC films mounting the drivers400and500are disposed on a peripheral area of the panel unit300, which is located around the display area DA.

The signal controller600controls the gate driver400and the data driver500and it may be mounted on a printed circuit board (PCB).

Now, an LCD according to an embodiment of the present invention is described in detail with reference toFIGS. 3-7as well asFIGS. 1 and 2.

FIG. 3is a schematic layout view of a TFT in a gate driver according to an embodiment of the present invention,FIG. 4is an expanded layout view of a portion of the TFT shown inFIG. 3, andFIG. 5is a sectional view of the TFT shown inFIG. 4taken along the line V-V′.FIG. 6is a layout view of a portion of a TFT array panel for an LCD andFIG. 7is a sectional view of the TFT array panel shown inFIG. 6taken along the line VII-VII′.

Referring toFIGS. 3-7, an LCD according to this embodiment includes a lower panel100and an upper panel200spaced apart from each other with a gap, and a LC layer3filled in the gap.

First, the upper panel200is described in detail.

A light blocking member220also referred to as a black matrix is formed on an insulating substrate210such as transparent glass. The light blocking member220has a plurality of open areas in a display area DA (shown inFIG. 1), while it has no open area in a peripheral area. A plurality of color filters230that may represent primary colors such as red, green and blue colors are formed on the substrate210and partly on the light blocking member220and they may be disposed only in the display area DA but not in the peripheral area. An overcoat250, a common electrode270, and an alignment layer21preferably made of polyimide are formed in sequence on the Color filters230and the light blocking member220.

In an exemplary LCD, the thickness of the LC layer3or the length of the gap between the panels100and200is equal to about 3.7 microns, and the thickness of the color filters230preferably ranges from about 1.5 microns to about 1.6 microns.

Description of the lower panel100follows.

A plurality of gate lines121for transmitting gate signals and a plurality of control signal lines126are formed on an insulating substrate110. Each gate line121extends substantially in a transverse direction and a plurality of portions of each gate line121form a plurality of gate electrodes124. Each gate line121includes a plurality of projections127protruding downward.

Each control signal line126includes a control electrode124ahaving an increased area. The control electrode124ahas an opening124bbisecting the control electrode124ainto upper and lower halves.

The gate lines121and the control signal lines126are preferably made of Al containing metal such as Al and Al alloy, Ag containing metal such as Ag and Ag alloy, Cu containing metal such as Cu and Cu alloy, Mo containing metal such as Mo and Mo alloy, Cr, Ta, or Ti. However, the gate lines121and the control signal lines126may have a multi-layered structure including two films having different physical characteristics. One of the films is preferably made of low resistivity metal including Al containing metal, Ag containing metal, or Cu containing metal for reducing signal delay or voltage drop in the gate lines121. On the other hand, the other of the films is preferably made of material such as Mo containing metal, Cr, Ta, Ti, and alloys thereat which has good physical, chemical, and electrical contact characteristics with other materials such as indium tin oxide (ITO) and indium zinc oxide (IZO). Examples of the films are a Cr lower film and an Al upper film and an Al lower film and a Mo upper film.

The lateral sides of the gate lines121are inclined relative to a surface of the substrate110, and the inclination angle thereof ranges about 30-80 degrees.

A gate insulating layer140preferably made of silicon nitride (SiNx) is formed on the gate lines121and the control signal lines126.

A plurality of semiconductor islands154and155preferably made of hydrogenated amorphous silicon (abbreviated to a-Si) or polysilicon are formed on the gate insulating layer140. The semiconductor islands154and155are disposed opposite the gate electrodes124and the control electrodes124a, respectively.

A plurality of pairs of ohmic contact islands163and165and other pairs of ohmic contact islands163aand165apreferably made of silicide or n+ hydrogenated a-Si heavily doped with n type impurity are formed on the semiconductor islands154and155, respectively.

The lateral sides of the semiconductor islands154and155and the ohmic contacts163and165are inclined relative to a surface of the substrate110, and the inclination angles thereof are preferably in a range of about 30-80 degrees.

A plurality of data lines171, a plurality of input signal lines171a, a plurality of drain electrodes175, a plurality of output signal lines176, and a plurality of storage capacitor conductors177are formed on the ohmic Contacts163,165,163aand165aand the gate insulating layer140.

The data lines171for transmitting data voltages extend substantially in the longitudinal direction and intersect the gate lines121. Each data line171includes A plurality of branches projecting toward the drain electrodes175to form a plurality of source electrodes173and an end portion179having a larger area for contact with another layer or an external device. Each pair of the source electrodes173and the drain electrodes175are separated from each other and opposite each other with respect to a gate electrode124.

Each of the input signal lines171aincludes a longitudinal portion extending substantially in the longitudinal direction, a plurality of, for example, three main branches extending from the longitudinal portion substantially in the transverse direction to form input connections172, and a plurality of secondary branches extending from the main branches172to a control electrode124ain the longitudinal direction like a comb to form input electrodes173a. A middle one of the main branches172overlaps an opening124bof the Control electrode124a.

Each of the output signal lines176includes an output terminal connected to one of the gate lines121and having a large area, a plurality of, for example, two main branches extending from the output terminal substantially in the transverse direction to form output connections178, which are interposed between the input connections172, and a plurality of secondary branches extending from the main branches178to the control electrodes124ain the longitudinal direction like a comb to form output electrodes175a.

The input electrodes173aand the output electrodes175aare alternately arranged in the transverse direction.

A gate electrode124, a source electrode173, and a drain electrode175along with a semiconductor island154form a switching TFT having a channel formed in the semi-conductor island154disposed between the source electrode173and the drain electrode175. Likewise, a control electrode124a, a set of input electrodes173a, and a set of output electrodes175aalong with a (pair of) semiconductor island155form a driver TFT having a channel formed in the semiconductor island155disposed between the input electrode173aand the output electrode175a. The channel of the driver TFT has a shape of horseshoes.

The storage capacitor conductors177overlap the projections127of the gate lines121.

The data lines171, the input signal lines171a, the drain electrodes175, the output signal lines176, and the storage capacitor conductors177are preferably made of refractory metal such as Mo, Cr, Ti, Ta and alloys thereof However, they may also have a multi-layered structure including a low resistivity film and a good contact film. For example, the data lines171, etc., may include triple films including a middle film of Al or Al alloy and upper and lower films of Mo or Mo alloy.

The data lines171, the drain electrodes175, and the storage capacitor conductors177also have tapered lateral sides relative to the surface of the substrate110, and the inclination angles thereof range about 30-80 degrees.

The ohmic contacts163,165,163aand165aare interposed only between the underlying semiconductor islands154and155and overlying layers including the data lines171, the drain electrodes175, and the input and the output signal lines171aand176and reduce the contact resistance therebetween.

A passivation layer180is formed on the data lines171, the drain electrodes175, the input and the output signal lines171aand176, the storage electrode capacitors177, and exposed portions of the semiconductor islands154, which are not covered with the data lines171, etc. The passivation layer180is preferably made of photo-sensitive organic material having a good flatness characteristic, low dielectric insulating material such as a-Si:C:O and a-Si:O:F formed by plasma-enhanced chemical vapor deposition (PECVD), or inorganic material such as silicon nitride and silicon oxide. The passivation layer180may have a double-layered structure including a lower inorganic film and an upper organic film.

The passivation layer180has a plurality of contact holes182,185and187exposing the end portions179of the data lines171, the drain electrodes175, and the storage Inductors177, respectively.

A plurality of pixel electrodes190, a plurality of shielding members196and196a, and a plurality of contact assistants82, which are preferably made of transparent Inductive material such as ITO or IZO, are formed on the passivation layer180.

The pixel electrodes190are physically and electrically connected to the drain elect rodes175through the contact holes185and to the storage capacitor conductors177through the contact holes187such that the pixel electrodes190receive the data voltages from the drain electrodes175and transmit the received data voltages to the storage capacitor conductors177.

The pixel electrodes190supplied with the data voltages generate electric fields in cooperation with the common electrode270on the upper panel200, which determine liquid crystal molecules in the liquid crystal layer3.

As described above with reference toFIG. 2, a pixel electrode190and the common electrode270form a liquid crystal capacitor CLC, which stores applied voltages after turn-off of the TFT. The storage capacitor CSTfor enhancing the voltage storing capacity is implemented by overlapping the pixel electrode190with a previous gate line121. The capacitances of the storage capacitors, i.e., the storage capacitances are increased by providing the projections127at the gate lines121for increasing overlapping areas and by providing the storage capacitor conductors177, which are connected to the pixel electrodes190and overlap the projections127, under the passivation layer180for decreasing the distance between the terminals.

The pixel electrodes190overlap the gate lines121and the data lines171to increase aperture ratio but it is optional.

The shielding electrodes196and196aare disposed on the channel portions of the switching TFTs or the driver TFTs, respectively, which are disposed on a region between the source electrodes173and the drain electrodes175or a region between the input electrodes173aand the output electrodes175a. The shielding electrodes196ahave shapes of horseshoe having several curves, while the shielding electrodes196are rectangular. The shielding electrodes196amay be supplied with a predetermined voltage lower than the common voltage Vcom from another signal line (not shown) and the predetermined voltage includes the gates voltage Voff and a ground voltage. However, the shielding electrodes196aand196may be electrically isolated.

The contact assistants82are connected to the exposed end portions179of the data lines171through the contact holes182, respectively. The contact assistants82protect the exposed end portions179and complement the adhesion between the end portions179and external devices.

The pixel electrodes190are made of transparent conductive polymer. For a reflective LCD, the pixel electrodes190are made of opaque reflective metal. In these cases, the contact assistants82may be made of material such as ITO or IZO different from the pixel electrodes190.

An alignment layer11preferably made of polyimide is coated on the pixel electrodes190, the shielding electrodes196and196a, and portions of the passivation layer180that are not covered with the pixel electrodes190and the shielding electrodes196and196a.

Now, the operation of the above-described LCD will be described in detail.

The signal controller600is supplied with input image signals R, G and B and input control signals controlling the display thereof such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, and a data enable signal DE, from an external graphics controller (not shown). After generating gate control signals CONT1and data control signals CONT2and processing the input image signals R, G and B suitable for the operation of the panel unit300on the basis of the input control signals and the input image signals R, G and B, the signal controller600transmits the gate control signals CONT1to the gate driver400, and the processed image signals DAT and the data control signals CONT2to the data driver500.

The gate control signals CONT1include a scanning start signal STV for instructing to start scanning and at least a clock signal for controlling the output time of the gate-on voltage Von. For example, the at least a clock signal includes a pair of clock signals having 180-degree phase difference or three or more clock signals having uniform phase differences. The gate control signals CONT1may further include an output enable signal OE for defining the duration if the gate-on voltage Von.

The data control signals CONT2include a horizontal synchronization start signal STH for informing of transmission if the image data DAT, a load signal LOAD for instructing to apply the data voltages to the data lines Dl-Dm, a inversion control signal RVS for reversing the polarity of the data voltages (with respect to the common voltage Vcom), and a data clock signal HCLK.

The data driver500receives a packet of the image data DAT for a pixel row from the signal controller600and converts the image data DAT into analog data signals selected from the gray signals supplied from the gray signal generator800in response to the data control signals CONT2from the signal controller600. Thereafter, the data driver500applies the data signals to the data lines Dl-Dm.

Responsive to the gate control signals CONT1from the signal controller600, the gate driver400applies the gate-on voltage Von to the gate line Gl-Gn, thereby turning on the switching elements Q connected thereto.

The driver TFT shown inFIGS. 3-5is disposed at an output terminal of the gate driver400. The output terminal of the output signal line176of the driver TFT is connected to one of the gate lines Gl-Gnand applies the gate signal including the gate-on voltage to the gate line Gl-Gn. The input signal line171aof the driver TFT is supplied with a clock signal and the controls signal126is supplied with a driving signal from an external device. Accordingly, the driver TFT outputs the clock signal, which is applied to the input electrode173athrough the input signal lines171a, through the output electrode175aand the output terminal when the driving signal applied to the control electrode124athrough the control signal line126has an appropriate level. A high level voltage of the clock signal is output as the gate-on voltage Von with a voltage drop by the driver TFT. A low level voltage of the clock signal may be equal to the gate-off voltage Voff that may be applied to the shielding electrodes196a. Alternatively, the shielding electrodes196amay be supplied with the gate-off voltage Voff supplied through a separate signal path.

Then, the data signals applied to the data lines Dl-Dmare supplied to the pixels PX through the activated switching elements Q.

In the LCD shown inFIGS. 2-7, the difference between a voltage of a data signal, i.e., the data voltage and the common voltage Vcom is represented as a voltage across the LC capacitor CLC, i.e., a pixel voltage. The LC molecules310in the LC capacitor CLChave orientations depending on the magnitude of the pixel voltage, and the molecular orientations determine the polarization of light passing through the LC layer3. The polarizer(s)11and21converts the light polarization into the light transmittance.

By repeating this procedure by a unit of the horizontal period (which is indicated by 1H and equal to one period of the horizontal synchronization signal Hsync and the data enable signal DE), all gate lines Gl-Gnare sequentially supplied with the gate-on voltage Von during a frame, thereby applying the data voltages to all pixels PX.

In the LCD shown inFIGS. 2-7, when the next frame starts after finishing one frame, the inversion control signal RVS applied to the data driver500is controlled such that the polarity of the data voltages is reversed (which is called frame inversion). The inversion control signal RVS may be also controlled such that the polarity of the data voltages flowing in a data line in one frame are reversed (for example, line inversion and dot inversion), or the polarity of the data voltages in one packet are reversed (for example, column inversion and dot inversion).

At this time, the shielding electrodes196and196ablock the effect of the common voltage Vcom applied to the common electrode270on the channels of the TFTs having the electrodes124,173,175,124a,173aand175aand the semiconductors154and155to prevent the deterioration of the threshold voltage of the TFTs. In addition, the application of the predetermined voltage such as the gate-off voltage Voff lower than the common voltage Vcom to the shielding electrodes196and196areduces a driving voltage of the TFTs and advances the switching time of the TFTs, thereby increasing the efficiency of input voltages supplied to the TFTs and the efficiency of the operation of the TFTs.

Furthermore, the employment of the shielding electrode196and196ado not increase the manufacturing cost or do not complicate the manufacturing process since the shielding electrodes196and196aare formed along with the pixel electrodes190.

The advantages of the shielding electrodes are described in detail in an indirect way that the common voltage applied to the common electrode is varied or the common electrode is removed with reference toFIGS. 8-14.

Referring toFIGS. 8-10, the variations of orientations of LC molecules and equipotential lines in a LC layer depending on the magnitude of a common voltage applied to a common electrode in LCDs are described in detail.

FIGS. 8 and 9show orientations of LC molecules and equipotential lines in a LC layer under the application of a common voltages of +3.3V and −1.0V to a common electrode, respectively, andFIG. 10show orientations of LC molecules and equipotential lines in the LC layer without a common electrode. The voltages of a gate electrode (or a control electrode) G, a source electrode (or an input electrode) S, and a drain electrode (or an output electrode) D of a TFT were 25V, 25V, and 14V, respectively. The LC layer has positive anisotropy.

As shown inFIGS. 8 and 9, a higher common voltage makes greater effects on the voltages of the source electrode S and the drain electrode D such that the equipotential lines become more horizontal. However, the equipotential lines, which determine the orientations of the LC molecules, are determined only by the voltages of the drain electrode D and the source electrode S when there is no common electrode as shown inFIG. 10.

Accordingly, it is apparent that the operational efficiency of the TFT becomes better as the magnitude of the common voltage becomes smaller since a decreased magnitude of the common voltage reduces the threshold voltage of the TFT as described above.

Referring toFIGS. 11-14, the variation of gate signals outputted from a gate driver of an LCD depending on the common voltage.

FIGS. 11 and 12illustrate waveforms of a gate signal under the application of a common voltage equal to +3.3V with and without a LC layer, respectively, andFIGS. 13 and 14illustrate waveforms of a gate signal under the application of a common voltage equal to −1.0V with and without a LC layer, respectively. InFIGS. 11-14, reference characters Vg and VCKdenote the gate signal and a clock signal used for generating the gate signal and having a high level voltage equal to +23.6V.

In presence of the LC layer, the high level voltage (i.e., the gate-on voltage Von) of the gate signal Vg under the common voltage of +3.3V as shown inFIG. 11is equal to about +14.6V, which is lower than the high level voltage of the clock signal VCKby about 9.0V. On the contrary, the gate-on voltage Von of the gate signal Vg under the common voltage of −1.0V as shown inFIG. 13is equal to about +20.6V, which is lower than the high level voltage of the clock signal VCKby only about 3.0V. Accordingly, it is understood that the operational efficiency of the TFT is improved as the common voltage becomes lower since a lower common voltage makes less effects on the LC layer and the electrodes to reduce the voltage drop of the gate signal from the gate driver.

In the absence of the LC layer, the gate-on voltages Von of the gate signal Vg under the common voltage of +3.3V and −1.0V shown inFIGS. 12 and 14are equal to about +20.6V and +20.8V, respectively, which are almost equal to each other. This means that the common voltage does not significantly affect the operation of the TFT.

The above-described results indicate that the shielding electrodes supplied with a voltage lower than the common voltage improves the operational efficiency of the TFTs, particularly when a dielectric material such as a LC layer is disposed between the common electrode and the TFT.

The above descriptions may be adapted to other flat panel display devices such as OLED.

Although preferred embodiments of the present invention have been described in detail hereinabove, it should be clearly understood that many variations and/or modifications of the basic inventive concepts herein taught which may appear to those skilled in the present art will still fill within the spirit and scope of the present invention, as defined in the appended claims.