Processor and control method for processor

A processor includes a programmable logic circuit provided with a plurality of processing units. The programmable logic circuit is capable of reconfiguring a first logic circuit corresponding to first circuit configuration information according to a first process and a second logic circuit corresponding to second circuit configuration information according to a second process. Each of the first and second logic circuits includes an information holding unit. A first control circuit stores the second circuit configuration information in the information holding unit of the first logic circuit and generates an execution control signal for executing the first process. A second control circuit obtains the second circuit configuration information from the information holding unit of the first logic circuit in response to completion of the first process and controls the programmable logic circuit so as to reconfigure the second logic circuit corresponding to the second circuit configuration information.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2013-036080, filed on Feb. 26, 2013, the entire contents of which are incorporated herein by reference.

FIELD

This disclosure relates to a processor and a control method for a processor.

BACKGROUND

Japanese Laid-Open Patent Publication No. 2001-68993 describes an example of a semiconductor device including a programmable logic circuit. The logic circuit includes a plurality of calculation units and couples the calculation units in accordance with configuration information supplied from a control circuit (e.g., CPU) provided in the semiconductor device. When a logic structure corresponding to the configuration information is configured in the logic circuit, the logic circuit outputs a completion flag. The control circuit responds to the completion flag and instructs the logic circuit to perform calculation. Then, the logic circuit performs the processing based on the instruction and outputs a completion flag upon completion of the processing. In response to the completion flag, the control circuit sets the subsequent configuration information in the logic circuit. In such a manner, the subsequent configuration information is set every time the logic circuit completes the processing.

The control circuit sets configuration information in response to a completion flag indicating the completion of processing in the logic circuit. Thus, when the programmable logic circuit performs a plurality of processes, the subsequent configuration information is not set in each logic circuit until all of the processes are completed. The delay in setting the configuration information in each logic circuit may lead to an increase in processing time.

SUMMARY

One aspect of this disclosure is a processor. The processor includes a programmable logic circuit that includes a plurality of processing units and is configured to selectively use the processing units to reconfigure a logic circuit. The programmable logic circuit is capable of performing a first process, followed by a second process which relates to the first process. The programmable logic circuit is further capable of reconfiguring a first logic circuit, which corresponds to first circuit configuration information according to the first process, and a second logic circuit, which corresponds to second circuit configuration information according to the second process, each of the first and second logic circuits including an information holding unit. The processor further includes a first control circuit that is configured to generate an execution control signal for executing the first process. The first control circuit is further configured to store the second circuit configuration information in the information holding unit of the first logic circuit. The processor further includes a second control circuit that is configured to obtain the second circuit configuration information from the information holding unit of the first logic circuit in response to completion of the first process and control the programmable logic circuit so as to reconfigure the second logic circuit corresponding to the second circuit configuration information.

DESCRIPTION OF THE EMBODIMENTS

Referring to the accompanying drawings, one embodiment will now be described below. As illustrated inFIG. 1, a processor10includes a reconfiguration control circuit11, a programmable logic circuit12, a central processing unit (hereinafter, CPU)13, and a memory interface (a memory I/F inFIG. 1)14, which are coupled by a bus15so as to communicate with one another.

The memory interface14is coupled to a memory100. The memory100is, for example, a dynamic random access memory (DRAM). The reconfiguration control circuit11, the programmable logic circuit12, and the CPU13access the memory100via the bus15and the memory interface14.

The CPU13includes a memory13a. The memory13ais a nonvolatile memory and stores program data performed by the CPU13. The CPU13stores reconfiguration information corresponding to a process to be performed by the programmable logic circuit12in the memory100and the programmable logic circuit12. The CPU13is one example of a first control circuit.

The reconfiguration control circuit11controls reconfiguration of the programmable logic circuit12. The reconfiguration control circuit11may read reconfiguration information from the memory100and set the reconfiguration information in the programmable logic circuit12. Further, the reconfiguration control circuit11may read reconfiguration information from the programmable logic circuit12and set the reconfiguration information in the programmable logic circuit12. The reconfiguration control circuit11is one example of a second control circuit.

The programmable logic circuit12configures a logic circuit according to the reconfiguration information. The programmable logic circuit12is capable of configuring a plurality of logic circuits. Further, the programmable logic circuit12is capable of reconfiguring, during operation of one logic circuit, a plurality of other logic circuits. The logic circuits may include a calculation circuit. The programmable logic circuit12includes an information holding unit12athat holds the reconfiguration information. Although not illustrated inFIG. 1, the programmable logic circuit12includes a plurality of processing units. The programmable logic circuit12configures a logic circuit by coupling some of the processing units in accordance with the reconfiguration information.

The reconfiguration information includes circuit configuration information and an operation parameter. For example, the circuit configuration information includes unit information, which indicates processing units used to configure a logic circuit, and coupling information, which indicates how the processing units, as well as the processing units and an external circuit, are coupled. The operation parameter includes an initial value and set information that are provided for the logic circuit. The set information includes, for example, a value indicating configuration of data (e.g., the number of bits) used for a process performed by each processing unit, the amount of data generated in each processing unit, and the like.

The CPU13sets the circuit configuration information in the program area102of the memory100and in the information holding unit12aof the programmable logic circuit12. Further, the CPU13sets the operation parameter used in the programmable logic circuit12in the program area102of the memory100.

The reconfiguration control circuit11reads the circuit configuration information and the operation parameter from the program area102of the memory100in accordance with a command provided by the CPU13. Then, the control circuit11sets the circuit configuration information and the operation parameter in the programmable logic circuit12. The programmable logic circuit12configures a logic circuit corresponding to the circuit configuration information. The configured logic circuit processes data read from the data area101of the memory100(i.e., read data) based on the operation parameter and stores the processed data (i.e., write data) in the data area101. When the processing completes, the logic circuit (programmable processing circuit12) outputs a process completion flag.

In response to the process completion flag output from the programmable logic circuit12, the reconfiguration control circuit11reads the circuit configuration information from the information holding unit12aof the programmable logic circuit12and also reads the operation parameter from the program area102of the memory100. Then, the reconfiguration control circuit11sets the circuit configuration information and the operation parameter in the programmable logic circuit12. The programmable logic circuit12configures a logic circuit corresponding to the circuit configuration information. Based on the operation parameter, the configured logic circuit processes data (i.e., read data) read from the data area101of the memory100and stores the processed data (write data) into the data area101.

FIG. 2illustrates an example of the programmable logic circuit12, as well as transmission and reception of various signals among the reconfiguration control circuit11, the programmable logic circuit12, the CPU13, and the memory100. InFIG. 2, the memory interface14and the bus15illustrated inFIG. 1are omitted.

The programmable logic circuit12includes a plurality of (twenty four inFIG. 2) processing units E01to E24and a coupling unit NU. The processing units E01to E20are, for example, calculation units. The processing units E21to E24are, for example, output interface units. In the following description, the processing units E01to E20may be referred to as “calculation units E01to E20”, and the processing units E21to E24may be referred to as “output interface units E21to E24”.

The coupling unit NU couples some of the processing units in accordance with the circuit configuration information. Further, according to the circuit configuration information, the coupling unit NU couples some of the processing units to the bus15illustrated inFIG. 1. For example, as illustrated inFIG. 5, the coupling unit NU couples the processing units E01, E05, E09, E14, E19, and E22in accordance with first circuit configuration information. In addition, the coupling unit NU couples the processing units E01and E22to the bus15in accordance with first circuit configuration information.

Further, for example, in accordance with second circuit configuration information, the coupling unit NU couples the processing units E02, E10, E13, and E21and also couples the processing units E02and E21to the bus15. Further, for example, in accordance with third circuit configuration information, the coupling unit NU couples the processing units E03, E06, E11, E15, and E23and also couples the processing units E03and E23to the bus15.

The processing unit E21includes an information holding unit RR1. Similarly, the processing units E22to E24include information holding units RR2to RR4, respectively. Each of the information holding units RR1to RR4is an example of the information holding unit12aillustrated inFIG. 1.

In order to output data from the programmable logic circuit12, each logic circuit reconfigured in the programmable logic circuit12includes at least one output interface unit and, in the present embodiment, at least one of the processing units E21to E24.

The program area102of the memory100includes memory areas111to114corresponding to the processing units E21to E24that include the information holding units RR1to RR4, respectively. The CPU13stores circuit configuration information CI1for the first process performed in the programmable logic circuit12in memory areas111to114. Further, the CPU13stores operation parameters EP1and EP2for processes performed by the respective logic circuits including the processing units E21to E24in the memory areas111to114.

Further, the CPU13stores circuit configuration information CI2for the subsequent process performed by the respective logic circuits including the processing units E21to E24in the information holding units RR1to RR4of the processing units E21to E24.

The CPU13supplies the reconfiguration control circuit11with a reconfiguration control signal EC1. In response to the reconfiguration control signal EC1, the reconfiguration control circuit11performs a reconfiguration process for performing the first process in the programmable logic circuit12. In the reconfiguration process, the reconfiguration control circuit11reads the circuit configuration information CI1from each of the memory areas111to114and supplies the programmable logic circuit12with the circuit configuration information CI1. The programmable logic circuit12reconfigures each logic circuit in accordance with the corresponding circuit configuration information CI1.

Next, the reconfiguration control circuit11reads the operation parameter EP1for the first process from each of the memory areas111to114and supplies the programmable logic circuit12with the operation parameter EP1. Then, the programmable logic circuit12sets the corresponding operation parameter EP1into each of the processing units E21to E24.

Upon completing the reconfiguration process to the programmable logic circuit12, the reconfiguration control circuit11outputs a completion flag EFa. In response to the completion flag EFa from the reconfiguration control circuit11, the CPU13supplies the programmable logic circuit12with an execution control signal EX1.

In response to the execution control signal EX1, the programmable logic circuit12activates each logic circuit configured. Each logic circuit reads data from the data area101of the memory100in accordance with the corresponding operation parameter EP1and performs a given process (for example, calculation process) based on the read data. Then, each of the processing units E21to E24in the respective logic circuits stores the processed data in the memory100in accordance with the corresponding operation parameter EP1.

The processing units E21to E24output completion flags EFb1to EFb4when processes in the respective logic circuits are completed. By receiving the completion flags EFb1to EFb4, the reconfiguration control circuit11determines that the respective logic circuits have completed their respective processes. When the respective logic circuits complete the processes, the reconfiguration control circuit11reads the circuit configuration information CI2for the subsequent process from the information holding units RR1to RR4of the processing units E21to E24. Further, the reconfiguration control circuit11reads the operation parameter EP2for the subsequent process from each of the memory areas111to114. Then, the reconfiguration control circuit11supplies the programmable logic circuit12with the circuit configuration information CI2read from each of the information holding units RR1to RR4and the operation parameter EP2read from each of the memory areas111to114. Then, the programmable logic circuit12reconfigures each logic circuit in accordance with the corresponding circuit configuration information C12and sets the corresponding operation parameter EP2in each of the processing units E21to E24.

Then, the reconfiguration control circuit11supplies the programmable logic circuit12with an execution control signal EX2. In response to the execution control signal EX2, the programmable logic circuit12activates each logic circuit configured. Each logic circuit reads data from the data area101of the memory100in accordance with the corresponding operation parameter EP2and performs a given process (for example, calculation process) based on the read data. Then, each of the processing units E21to E24in the respective logic circuits stores the processed data in the memory100in accordance with the corresponding operation parameter EP2.

As described above, the completion flags EFb1to EFb4are output from the processing units E21to E24when the respective logic circuits complete their respective processes. In response to the completion flags EFb1to EFb4, the reconfiguration control circuit11reads the circuit configuration information C12for the subsequent process from the processing units E21to E24. Further, in response to the completion flags EFb1to Efb4, the reconfiguration control circuit11reads the operation parameter EP2from the memory areas111to114respectively corresponding to the processing units E21to E24. Then, the reconfiguration control circuit11supplies the programmable logic circuit12with the circuit configuration information CI2and the operation parameter EP2and reconfigures the programmable logical circuit12.

Accordingly, even when one of the logic circuits reconfigured in the programmable logic circuit12is performing the process, the reconfiguration control circuit11reconfigures a new logic circuit and allows the new logic circuit to perform the subsequent process. Therefore, in comparison to the case where a new logic circuit for the subsequent process is reconfigured after all logic circuits reconfigured in the programmable logic circuit12complete their respective processes, the processing units in the programmable logic circuit12may be used effectively. This may reduce waiting time in processes performed successively and shorten the total processing time in the programmable logic circuit12.

FIG. 3illustrates an example of the reconfiguration control circuit11and the processing units E21to E24(output interface units E21to E24). The output interface units E21to E24are identical to one another. Therefore, the structure of the output interface unit E21will now be explained, and parts of the explanations of the output interface units E22to E24are omitted. Further, inFIG. 3, components included in the output interface units E22to E24, as well as the memory interface14and bus15illustrated inFIG. 1, are omitted.

The output interface unit E21includes first to third registers31to33, a data control unit34, and an interface control unit35. The first and second registers31and32store the operation parameters of the output interface unit E21. For example, the operation parameter stored in the first register31indicates an output size OS, and the operation parameter stored in the second register32indicates an output address OA. The output size OS corresponds to the amount of data transferred to the memory100in each transfer process. The output address OA specifies an area where data is written. The third register33stores the circuit configuration information CI2. Each of the first to third registers31to33is an example of the information holding unit RR1illustrated inFIG. 2. Although not illustrated, each of the output interface units E22to E24also includes first to third registers31to33. Each of the registers31to33of the output interface unit E22is an example of the information holding unit RR2. Each of the registers31to33of the output interface unit E23is an example of the information holding unit RR3. Each of the registers31to33of the output interface unit E24is an example of the information holding unit RR4.

The data control unit34is supplied with data SD1output from a processing unit coupled to the output interface unit E21. The data control unit34monitors the amount of output data SD1and supplies the interface control unit35with a control signal indicating arrival of the initial data. When the amount of output data SD1reaches the output size OS, the data control unit34supplies the interface control unit35with a control signal indicating completion of the process.

Based on the control signal supplied from the data control unit34, the output size OS stored in the first register31, and the output address OA stored in the second register32, the interface control unit35transfers output data D0held in the data control unit34to the memory100. Consequently, the output data D0is stored in the data area101of the memory100specified by the output address OA.

Upon transfer of the output data D0to the memory100, the interface control unit35outputs a completion flag EFb1. Similarly, upon transfer of output data D1to D3according to the output data SD2to SD4to the memory100, the respective interface control units of the output interface units E22to E24output completion flags EFb2to EFb4, respectively.

The reconfiguration circuit11includes a circuit reconfiguration control unit21, an output selection unit22, an information selection unit23, and an address control unit24. Based on the completion flags EFb1to EFb4, the address control unit24determines addresses for accessing the memory areas111to114corresponding to the output interface units E21to E24. The output interface unit used in each of processes performed in the programmable logic circuit12and the order of the processes are determined beforehand. For example, a pointer is shifted according to the process performed in the programmable logic circuit12and an address is determined based on the pointer and the completion flags EFb1to EFb4. Then, the address control unit24supplies the determined address to the memory100. Based on the address supplied by the address control unit24, the memory100reads the operation parameter EP2from the corresponding one of the memory areas111to114.

The information selection unit23reads circuit configuration information from the respective third registers33of the output interface units E21to E24based on the completion flags EFb1to EFb4. For example, the information selection unit23reads circuit configuration information CI21from the third register33of the output interface unit E21based on the completion flag EFb1. Similarly, based on the completion flags EFb2to EFb4, the information selection unit23reads circuit configuration informations CI22to CI24, respectively from the respective third registers33of the output interface units E22to E24. Then, the information selection unit23supplies the circuit reconfiguration control unit21with the circuit configuration information. InFIG. 3, “CI2” indicates one of the circuit configuration information CI21to CI24. Similarly, “EP2” indicates one of the operation parameters EP21to EP24.

The circuit configuration control unit21supplies the output selection unit22with the circuit configuration information CI2and the operation parameter EP2. The output selection unit22supplies the programmable logic circuit12with the circuit configuration information CI2. The programmable logic circuit12configures a logic circuit corresponding to the circuit configuration information CI2. Further, the output selection unit22sets the operation parameter EP2in a processing unit of a logic circuit to be configured next based on the circuit configuration information CI2.

For example, the logic circuit to be configured next based on the circuit configuration information CI2includes the output interface unit E21. In this case, the output selection unit22sets an operation parameter EP21in each of the first and second registers31and32of the output interface unit E21. Similarly, in the case where the logic circuit to be configured next includes the output interface unit E22, the output selection unit22sets an operation parameter EP22in each of the first and second registers31and32of the output interface unit E22. Similarly, in the case where the logic circuit to be configured next includes the output interface unit E23or E24, the output selection unit22sets an operation parameter EP23in each of the first and second registers31and32of the output interface unit E23.

Thus, based on the circuit configuration information CI2and the operation parameter EP2, the reconfiguration control circuit11controls reconfiguration of the logic circuit that performs the subsequence process. The circuit configuration information CI2includes information (unit numbers) for specifying processing units included in the logic circuit to be reconfigured. The reconfiguration control circuit11supplies the programmable logic circuit12with the circuit configuration information CI2. Further, the reconfiguration control circuit11sets the operation parameter EP2in the processing unit included in the logic circuit reconfigured in the programmable logic circuit12.

Next, the flow of reconfiguration processing in the programmable logic circuit12will now be described. As illustrated inFIG. 8, in step201, the CPU13sets the circuit configuration information and the operation parameter in the programmable logic circuit12and the memory100. Then, the CPU13outputs the reconfiguration control signal EC1.

Next, in step202, the reconfiguration control circuit11reconfigures the programmable logic circuit12in response to the reconfiguration control signal EC1and outputs the completion flag EFa. In response to the completion flag EFa, the CPU13outputs the execution control signal EX1to activate the programmable logic circuit12.

Next, in step203, the reconfiguration control circuit11determines whether or not to receive the completion flags EFb1to EFb4. When none of the completion flags EFb1to EFb4is output, the reconfiguration control circuit11repeats step203. When any of the completion flags EFb1to EFb4is output, the reconfiguration control circuit11executes step204.

In step204, the reconfiguration control circuit11identifies the unit number of the output interface unit that has output the completion flag and executes steps205ato205din accordance with the identified unit number. For example, when the output interface unit E21has output the completion flag EFb1, the reconfiguration control circuit11executes step205a. Similarly, when the output interface units E22to E24has output the completion flags EFb2to EFb4, the reconfiguration control circuit11executes steps205bto205drespectively.

In step205a, the reconfiguration control circuit11reconfigures the programmable logic circuit12based on the circuit configuration information CI21read from the register33of the processing unit E21(output interface unit E21) and the operation parameter EP21read from the memory area111in accordance with the completion flag EFb1. Then, the reconfiguration control circuit11activates the logic circuit reconfigured in the programmable logic circuit12.

In step205b, the reconfiguration control circuit11reconfigures the programmable logic circuit12based on the circuit configuration information CI22read from the register33of the processing unit E22(output interface unit E22) and the operation parameter EP22read from the memory area112in accordance with the completion flag EFb2. Then, the reconfiguration control circuit11activates the logic circuit reconfigured in the programmable logic circuit12.

In step205c, the reconfiguration control circuit11reconfigures the programmable logic circuit12based on the circuit configuration information CI23read from the register33of the processing unit E23(output interface unit E23) and the operation parameter EP23read from the memory area113in accordance with the completion flag EFb3. Then, the reconfiguration control circuit11activates the logic circuit reconfigured in the programmable logic circuit12.

In step205d, the reconfiguration control circuit11reconfigures the programmable logic circuit12based on the circuit configuration information CI24read from the register33of the processing unit E24(output interface unit E24) and the operation parameter EP24read from the memory area114in accordance with the completion flag EFb4. Then, the reconfiguration control circuit11activates the logic circuit reconfigured in the programmable logic circuit12.

Next, in step206, the reconfiguration control circuit11determines whether or not all the logic circuits reconfigured have completed their respective processes, that is, whether or not the logic circuits have output the respective completion flags. When there are any logic circuits that have not completed their processes, the reconfiguration control circuit11executes step203again. When all the logic circuits complete their processes, the reconfiguration process inFIG. 8ends.

Next, an example of the processing performed in the programmable logic circuit12will now be described. As illustrated inFIG. 4A, a process A0includes a process A1, a process A2, and a process A3. For example, in the process A1, the programmable logic circuit12reads data from the data area101of the memory100illustrated inFIG. 1, processes the data, and stores the processed data into the data area101. In the process A2, the programmable logic circuit12reads the data stored in the data area101by the process A1, processes the data, and stores the processed data into the data area101. In the process A3, the programmable logic circuit12reads the data stored in the data area101by the process A2, processes the data, and stores the processed data into the data area101. Thus, in the process A0, the process A1is first processed, the process A2is next processed, and the process A3is lastly processed.

As illustrated inFIG. 4B, a process B0includes a process B1and a process B2. For example, in the process B1, the programmable logic circuit12reads data from the data area101of the memory100illustrated inFIG. 1, processes the data, and stores the processed data into the data area101. In the process B2, the programmable logic circuit12reads the data stored in the data area101by the process B1, processes the data, and stores the processed data into the data area101. Thus, in the process B0, the process B1is first processed, and then, the process B2is processed.

As illustrated inFIG. 4C, a process C0includes a process C1. For example, in the process C1, the programmable logic circuit12reads data from the data area101of the memory100illustrated inFIG. 1, processes the data, and stores the processed data into the data area101.

The process A0(processes A1to A3), the process B0(processes B1and B2), and the process C0(process C1) are each calculation process. In the following description, the process A0(processes A1to A3), the process B0(processes B1and B2), and the process C0(process C1) may be referred to as calculation A0(A1to A3), calculation B0(B1, B2), and calculation C0(C1), respectively.

Next, an example of logic circuits configured in the programmable logic circuit12in accordance with the reconfiguration information will now be described. Here, logic circuits that perform the processes illustrated inFIGS. 4A to 4Cwill now be described.

As illustrated inFIG. 5, the logic circuit that performs the process A1illustrated inFIG. 4Ais configured from, for example, the processing units E02, E10, E13, and E21. The reconfiguration information (circuit configuration information) corresponding to the process A1includes the unit numbers of the processing units E02, E10, E13, and E21and the coupling information for coupling these processing units. The processing unit E02is supplied with data DIa1used in the process A1. The processing unit E21outputs data DOa1as the result of the process A1.

As illustrated inFIG. 5, the logic circuit that performs the process B1illustrated inFIG. 4Bis configured from, for examples, the processing units E01, E05, E09, E14, E19, and E22. The reconfiguration information (circuit configuration information) corresponding to the process B1includes the unit numbers of the processing units E01, E05, E09, E14, E19, and E22and the coupling information for coupling these processing units. The processing unit E01is supplied with data DIb1used in the process B1. The processing unit E22outputs data DOb1as the result of the process B1.

As illustrated inFIG. 5, the logic circuit that performs the process C1illustrated inFIG. 4Cis configured from, for examples, the processing units E03, E06, E11, E15, and E23. The reconfiguration information (circuit configuration information) corresponding to the process C1includes the unit numbers of the processing units E03, E06, E11, E15, and E23and the coupling information for coupling these processing units. The processing unit E03is supplied with data DIc1used in the process C1. The processing unit E23outputs data DOc1as the result of the process C1.

As illustrated inFIG. 6, the logic circuit that performs the process A2illustrated inFIG. 4Ais configured from, for example, the processing units E02, E08, E10, E13, and E21. The reconfiguration information (circuit configuration information) corresponding to the process A2includes the unit numbers of the processing units E02, E08, E10, E13, and E21and the coupling information for coupling these processing units. The processing unit E02is supplied with data DIa2used in the process A2. The processing unit E21outputs data DOa2as the result of the process A2.

As illustrated inFIG. 6, the logic circuit that performs the process B2illustrated inFIG. 4Bis configured from, for examples, the processing units E01, E09, E14, E20, and E22. The reconfiguration information (circuit configuration information) corresponding to the process B2includes the unit numbers of the processing units E01, E09, E14, E20, and E22and the coupling information for coupling these processing units. The processing unit E01is supplied with data DIb2used in the process B2. The processing unit E22outputs data DOb2as the result of the process B2.

As illustrated inFIG. 7, the logic circuit that performs the process A3illustrated inFIG. 4Ais configured from, for examples, the processing units E03, E07, E12, E19, and E23. The reconfiguration information (circuit configuration information) corresponding to the process A3includes the unit numbers of the processing units E03, E07, E12, E19, and E23and the coupling information for coupling these processing units. The processing unit E03is supplied with data DIa3used in the process A3. The processing unit E23outputs data DOa3as the result of the process A3.

Next, an example of the processing performed in step201(setting of the circuit configuration information and the operation parameters) illustrated inFIG. 8will now be described. Step201includes steps221to223illustrated inFIG. 9.

In step221, the CPU13sets the reconfiguration information corresponding to the process A0illustrated inFIG. 4A. First in step221a, the CPU13sets the circuit configuration information and the operation parameter for the calculation A1in the memory100. The CPU13sets the circuit configuration information for the calculation A2in the register33of the output interface unit E21used in the logic circuit that performs the calculation A1. Next, in step221b, the CPU13sets the operation parameter for the calculation A2in the memory100. Further, the CPU13sets the circuit configuration information for the calculation A3in the register33of the output interface unit E21used in the logic circuit that performs the calculation A1. Next, in step221c, the CPU13sets the operation parameter for the calculation A3in the memory100. Further, the CPU13sets “No process to be performed next” as the circuit configuration information in the register33of the output interface unit E23 used in the logic circuit that performs the calculation A3.

Next, in step222, the CPU13sets the reconfiguration information corresponding to the process B0illustrated inFIG. 4B. First in step222a, the CPU13sets the circuit configuration information and the operation parameter for the calculation B1in the memory100. Further, the CPU13sets the circuit configuration information for the calculation B2in the register33of the output interface unit E22used in the logic circuit that performs the calculation B1. Next, in step222b, the CPU13sets the operation parameter for the calculation B2in the memory100. Further, the CPU13sets “No process to be performed next” as the circuit configuration information in the register33of the output interface unit E22 used in the logic circuit that performs the calculation B2.

Next, in step223, the CPU13sets the reconfiguration information corresponding to the process C0illustrated inFIG. 4C. That is, in step223a, the CPU13sets the circuit configuration information and the operation parameter for the calculation C1in the memory100. Further, the CPU13sets “No process to be performed next” as the circuit configuration information in the register33of the output interface unit E23used in the logic circuit that performs the calculation C1.

Next, examples of the processes performed in steps205ato205dillustrated inFIG. 8will now be described. The processes in steps205ato205dare identical to one another. Here, the process in step205awill now be explained.

Step205aillustrated inFIG. 8includes steps231to237illustrated inFIG. 10. In step231, the reconfiguration control circuit11obtains, from the register33of the output interface unit E21, the circuit configuration information for a logic circuit to be configured next. In step232, the reconfiguration control circuit11determines whether or not the circuit configuration information indicates “No process to be performed next”. When the circuit configuration information indicates “No process to be performed next”, the process in step205aends. When the circuit configuration information does not indicate “No process to be performed next” (i.e., the subsequent process is present), the reconfiguration control circuit11proceeds to step233.

In step233, the reconfiguration control circuit11sets the circuit configuration information in the programmable logic circuit12. Thus, a new logic circuit is configured.

Next, in step234, the reconfiguration control circuit11obtains the operation parameter from the memory area111illustrated inFIG. 3. Then, in step235, the reconfiguration control circuit11sets the operation parameter in each of the registers31and32of the output interface unit of the logic circuit configured in step233.

Next, in step236, the reconfiguration control circuit11stores the circuit configuration information for a logic circuit to be configured next in the register33of the output interface unit of the logic circuit configured in step233.

For example, the processes performed by the programmable logic circuit12are performed by a plurality of logic circuits which are configured in sequence through the reconfiguration processes performed an n (1≦n) times. In this case, for example in step233, the logic circuit is configured through the m-th (1≦m<n) reconfiguration process. In step236, the circuit configuration information used in and after the (m+1)th reconfiguration process is stored in the register33of the logic circuit (output interface unit) configured through the m-th reconfiguration process.

Next, in step237, the reconfiguration control circuit11instructs the logic circuit (processing units) configured in step233to perform processes.

Next, the operation of the processor10will now be described.

As illustrated inFIG. 11A, the CPU13outputs the reconfiguration control signal EC1. In response to the reconfiguration control signal EC1, the reconfiguration control circuit11sets the reconfiguration information for the processes A1, B1, and C1in the programmable logic circuit12. The programmable logic circuit12configures a logic circuit corresponding to the reconfiguration information according to the process A1, a logic circuit corresponding to the reconfiguration information according to the process B1, and a logic circuit corresponding to the reconfiguration information according to the process C1. Subsequently, the CPU13outputs the execution control signal EX1. The three logic circuits configured in the programmable logic circuit12perform the respective processes, A1, B1, and C1.

First, when the process A1completes, the reconfiguration control circuit11sets the reconfiguration information according to the subsequent process A2in the programmable logic circuit12. The programmable logic circuit12newly configures a logic circuit corresponding to the reconfiguration information according to the process A2. Then, the reconfiguration control circuit11outputs the execution control signal EX2. The logic circuit newly configured in the programmable logic circuit12performs the process A2in response to the execution control signal EX2.

Here, when the process A1completes, the processes B1and C1are being performed. That is, even when the processes B1and C1are being performed, the logic circuit for the subsequent process A2is configured and the process A2is initiated.

Next, when the process B1completes, the reconfiguration control circuit11sets the reconfiguration information according to the subsequent process B2in the programmable logic circuit12. The programmable logic circuit12newly configures a logic circuit corresponding to the configuration information according to the process B2. Then, the reconfiguration control circuit11outputs the execution control signal EX2. The logic control circuit newly configured in the programmable logic circuit12performs the process B2in response to the execution control signal EX2. Here, when the process B1completes, the process C1is being performed. Thus, even when the process C1is being performed, the logic circuit for the subsequent process B2is configured. Further, even when the logic circuit for the process B2is being configured, the process A2is initiated.

Next, when the process C1completes, the reconfiguration control circuit11determines that there is no process to be processed subsequently to the process C1, and completes processes relating to the process C0.

Next, when the process A2completes, the reconfiguration control circuit11sets the reconfiguration information according to the subsequent process A3in the programmable logic circuit12. The programmable logic circuit12newly configures a logic circuit corresponding to the reconfiguration information according to the process A3. Then, the reconfiguration control circuit11outputs the execution control signal EX2. The logic circuit newly configured in the programmable logic circuit12performs the process A3in response to the execution control signal EX2.

Next, a comparative example will now be described. In the comparative example, a CPU manages setting of the reconfiguration information relating to a plurality of processes. In the following description, components identical to those in the embodiment described above are labelled with the same names and symbols.

As illustrated inFIG. 11B, a CPU13outputs a reconfiguration control signal EC1. In response to the reconfiguration control signal EC1, a reconfiguration control circuit11sets the reconfiguration information according to processes A1, B1, and C1in the programmable logic circuit12. The programmable logic circuit12configures a logic circuit corresponding to the reconfiguration information according to the process A1, a logic circuit corresponding to the reconfiguration information according to the process B1, and a logic circuit corresponding to the reconfiguration information according to the process C1. Subsequently, the CPU13outputs an execution control signal EX1. The three logic circuits configured in the programmable logic circuit12perform their respective processes, A1, B1, and C1.

First, the process A1completes, then the process B1completes, and lastly the process C1completes. When the process C1completes, all the processes in the programmable logic circuit12complete. Then, the CPU13outputs the reconfiguration control signal EC1, and the reconfiguration control circuit11sets the reconfiguration information according to the subsequent processes A2and B2in the programmable logic circuit12. The programmable logic circuit12configures a logic circuit corresponding to the reconfiguration information according to the process A2, and a logic circuit corresponding to the reconfiguration information according to the process B2. Then, the CPU13outputs the execution control signal EX1. The two logic circuits configured in the programmable logic circuit12perform the respective processes A2and B2.

Thereafter, the process A2completes first. Then, the process B2completes. When the process B2completes, the CPU13outputs the reconfiguration control single EC1, and the reconfiguration control circuit11sets reconfiguration information according to the subsequent process A3in the programmable logic circuit12. The programmable logic circuit12configures a logic circuit corresponding to the reconfiguration information according to the process A3. Then, the CPU13outputs the execution control signal EX1. The logic circuit configured in the programmable logic circuit12performs the process A3. Next, when the process A3completes, all the processes are completed.

As described above, in the present embodiment illustrated inFIG. 11A, the times required to perform the process A0(processes A1to A3) and the process B0(processes B1and B2) are shortened in comparison to those in the comparative example illustrated inFIG. 11B. Accordingly, in the processor10according to the present embodiment, processing time may be shortened than that in the comparative example.

The present embodiment has the advantages described below.

(1) The programmable logic circuit12includes a plurality of processing units E01to E24. Each of the processing units E01to E20is, for example, a calculation unit. Each of the processing units E21to E24is an output interface unit. The processing units E21to E24include information holding units RR1to RR4, respectively.

The CPU13stores the circuit configuration information CI1according to the first process and the operation parameters EP1and EP2for performing the first process in the program area102of the memory100. Further, the CPU13stores the circuit configuration information CI2according to the second process and the circuit configuration information according to the subsequent processes in the respective information holding units RR1to RR4of the processing units E21to E24used for the first process. Upon receiving the completion flags EFb1to EFb4from the programmable logic circuit12, the reconfiguration control circuit11determines that the processing units E21to E24have completed their processes. When the processing units E21to E24complete their processes, the reconfiguration control circuit11obtains the circuit configuration information CI2from the information holding units RR1to RR4of the processing units E21to E24. Then, the reconfiguration control circuit11sets the circuit configuration information CI2in the programmable logic circuit12.

According to this structure, for example, when the process A1completes, the reconfiguration control circuit11reads the circuit configuration information CI2according to the subsequent process A2even while the processes B1and C1being performed, and controls the programmable logic circuit12so as to reconfigure a logic circuit corresponding to the circuit configuration information CI2. Thus, without waiting for completion of the processes B1and C1, the subsequent process A2may be initiated. Accordingly, processing time may be shortened.

(2) The processing units E21to E24among the processing units E01to E24serve as the output interface units E21to E24which output processed data. The output interface units E21to E24include the information holding units RR1to RR4, respectively, for holding the circuit configuration information. In this structure, the circuit configuration information is stored in the information holding unit (output interface unit) of a logic circuit reconfigured in the programmable logic circuit12. Accordingly, upon completion of the first process in the logic circuit, the reconfiguration control circuit11may easily obtain the circuit configuration information for the subsequent process.

It should be apparent to those skilled in the art that the above embodiment may be embodied in many other specific forms without departing from the scope of the invention. Particularly, it should be understood that the above embodiment may be embodied in the following forms.

In the embodiment described above, data used in the processes A0to C0performed in the programmable logic circuit12are read from the memory100, but they may be supplied from an external device.

In the embodiment described above, the programmable logic circuit12stores processed data in the memory100, but may store them in an external device.

In the embodiment described above, the programmable logic circuit12may repeat the same process more than once. For example, inFIG. 11A, after the process A1has been performed more than once, the process A2may be performed.

In the example illustrated inFIG. 11A, the programmable logic circuit12first performs the processes A1, B1, and C1. However, the timing with which processes are initiated may be changed if required. For example, where three processes A, B, and C are performed, the process A may be performed first, and followed by the processes A and B in response to the completion of the process A. Further, in response to the completion of the processes A and B, the processes A to C may be performed. In this way, a pipeline process may be achieved.

In the embodiment described above, the information holding units (registers33) for holding the circuit configuration information are included in the output interface units E21to E24, but may be included in other processing units E01to E20.