Method of manufacturing a semiconductor wafer having an SOI configuration

The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to methods of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration and, more particularly, to preparing SOI semiconductor starting wafers at the beginning of front-end-of-line (FEOL) processing in very-large-scale-integration (VLSI).

2. Description of the Related Art

In the ongoing task to comply with constraints imposed by Moore's Law, FDSOI (“fully depleted silicon-on-insulator”) seems to be a promising candidate for next generation technologies in the fabrication of semiconductor devices at technology nodes of 22 nm and beyond. Currently, FDSOI is considered as a promising candidate for solving, with comparatively less process complexity, scaling, leakage and variability issues to further shrink CMOS technology beyond 28 nm and, particularly, beyond 22 nm.

In detail, FDSOI is considered as offering the following benefits: the electrostatic control of transistor devices in FDSOI technology acts as a performance booster and enables lower VDD; random dopant fluctuation is reduced in FDSOI technology, therefore decreasing the variability of the threshold voltage of transistor devices; and transistor devices fabricated in accordance with FDSOI technology show low leakage and a good control of short channel effects when compared to conventional bulk technology.

The range of FDSOI technology covers a wide range of applications from high performance, lower power systems on chip to ultralow power applications. This range covers a great variety of markets, such as mobile internet devices (Smartphones, tablets, notebooks, etc.), imaging (digital cameras, camcorders, etc.), mobile multimedia, home multimedia (TV, Blueray, etc.), automotive infotainment and so on.

Aside from FDSOI allowing the combination of high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques, fabrication processes as employed in FDSOI techniques are comparatively simple and actually represent a low risk evolution of conventional planar bulk CMOS techniques when compared to multidimensional semiconductor devices, such as FinFETs.

In SOI techniques, a special kind of substrate is used, the substrate being formed by a semiconductor layer, such as a top silicon layer or a layer of germanium or silicon germanium, formed on a buried oxide (BOX) layer, which is in turn formed on a semiconductor substrate. For example, in case of an N-type SOI device, a P-type semiconductor film is sandwiched between a gate stack and the BOX layer.

Furthermore, in SOI techniques, one distinguishes between two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI devices. Both types differ in that the thickness of the semiconductor layer in FDSOI is sufficiently small such that it is fully depleted, while the semiconductor layer in PDSOI is of greater thickness relative to FDSOI such that the semiconductor layer in PDSOI is not fully depleted. Typically, the thickness of the top silicon layer in known starting wafers for FDSOI technology processes is typically in a range from about 10-25 nm and according starting wafers enable the fabrication of planar fully depleted transistors with less than 10 nm of silicon under the gate.

Current requirements on the uniformity of the thickness of the top silicon layer are set to lie within a few angstroms in order to comply with demands on reliability and performance in manufactured integrated circuits. According to a current requirement, the6sigma range is required to be less than 0.1 nm, wherein sigma (also represented by the Greek letter sigma a or the Latin letter s) denotes the standard deviation which is a term in statistics and represents a measure that is used to quantify the amount of variation or dispersion of a set of data values. For example, a low standard deviation indicates that data points tend to be close to the mean (also called the expected value) of the set, while a high standard deviation indicates that data points are spread out over a wider range of values. Generally, the standard deviation of a random variable, statistical population, data set, or probability distribution is the square root of its variance. A useful property of the standard deviation is that, unlike the variance, it is expressed in the same units as the data. The term “six sigma range” therefore denotes the range within six standard deviations from the mean and current requirements in VLSI FDSOI set an upper bound such that deviations from the mean within the range of six standard deviations from the mean are less than 0.1 nm. As, according to Chebyshev's inequality, more than 97% of measured data are to lie within the range of six standard deviations, it may be understood that current requirements demand uniformity of the thickness of the top silicon layer to a very high degree because the deviation from the mean is basically allowed to be less than 0.1 nm.

Starting from a provided SOI starting wafer, an FDSOI wafer may be prepared by oxidizing the top silicon layer, typically having a thickness at about 12 nm, and removing the oxide such that a top silicon layer of reduced thickness, typically in the range from about 5-30 nm, is obtained.

With regard toFIGS. 1aand 1b, measurements of the thickness of the top silicon layer in FDSOI starting wafers were taken.

FIG. 1ashows thickness values taken across a starting wafer by measurement and/or statistical evaluation prior to a reduction of the thickness of the silicon layer of starting wafers, that is, the starting wafer is not an FDSOI starting wafer but an SOI starting wafer where the top silicon layer has a thickness of about 120 angstroms. As illustrated inFIG. 1a, the thickness profile taken across the starting wafer shows a strongly varying thickness at 120 angstroms in a range of about ±5 angstroms around the mean.

RegardingFIG. 1b, thickness values taken across the starting wafer are shown after a first process of oxidizing an upper surface region of the top silicon layer and prior to a removal of the oxide in attempts to reduce the thickness of the top silicon layer to thickness values of the top silicon layer. As shown herein, the thickness profile shows strong variability around a mean of 80 angstroms thickness in the range of about ±3 angstroms around the mean.

With regard toFIGS. 1cand 1d, a variability of a thickness across measured starting wafers is illustrated by means of schematic contour plots in top views on wafer surfaces.

FIG. 1cschematically shows a contour line plot indicating a thickness profile of the top silicon layer of a first measured starting wafer10awithin a measuring area11aon the basis of measurement points12a(the depicted amount of measurement points is only for illustrative purposes), the contour lines indicating lines of constant thickness.

Similarly,FIG. 1dshows a contour line plot of another measured starting wafer10bmeasured within a measuring area11bon the basis of measuring points12b(the depicted amount of measurement points is only for illustrative purposes), the contour lines indicating lines of constant thickness.

The measured starting wafers10aand10bshow a non-uniformity in the thickness profile around a mean thickness of 12 nm in the range of about ±0.3 nm.

In view of the above discussion, there is a need in the art to provide a method of processing a semiconductor starting wafer to provide a processed starting wafer complying with required uniformity constraints of a few angstroms, e.g., currently a 6 sigma range of less than about 0.1 nm.

SUMMARY OF THE DISCLOSURE

In accordance with a first aspect of the present invention, a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration is provided. In accordance with illustrative embodiments herein, the method includes providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate, and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

In accordance with a second aspect of the present invention, a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration is provided. In accordance with some illustrative embodiments herein, the method includes providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate, and a buried insulating material layer formed between the semiconductor layer and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, determining a thickness profile of each of the semiconductor layer and the oxide surface region, determining a target thickness of the semiconductor layer, thinning the oxide surface region in a dry etching process, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region in a wet etching process, wherein the semiconductor layer having the target thickness is exposed.

DETAILED DESCRIPTION

In general, a wafer, also called a slice or substrate, is a thin slice of semiconductor material, such as a crystalline silicon, used in electronics for the fabrication of integrated circuits, for example. The wafer serves as the substrate for microelectronic devices built in and over the wafer and undergoes many microfabrication process steps, such as doping or ion implantation, etching, deposition of various materials, and photolithographic patterning, after which the individual microcircuits are separated (dicing) and packaged in the end.

In wafer fabrication, a procedure composed of many repeated sequential processes to produce complete electrical or photonic circuits is performed. Examples of such processes may include, without limitation, production of radio frequency (RF) amplifiers, LEDs, optical computer components and CPUs for computers. Wafer fabrication is used to build components with the necessary electrical structures.

The main process may begin with electrical engineers designing the circuit and defining its functions, and specifying the signals, inputs, outputs and voltages needed. These electrical circuit specifications are entered into electrical circuit design software, such as SPICE, and then imported into circuit layout programs, which are similar to ones used for computer aided design. This is necessary for the layers to be defined for photomask production. The resolution of the circuits increases rapidly with each step in design, as the scale of the circuits at the start of the design process is already being measured in fractions of micrometers. Each step thus increases circuit density for a given area.

Generally, wafers start out as blank and pure starting wafers, on which circuits are built in layers in clean rooms. Processes used for building circuits on wafers comprise a vast plurality of different steps of great complexity which are often repeated many hundreds of times, depending on the desired circuit and its connections.

New processes to accomplish each of these steps with better resolution and in improved ways emerge every year, with the result of constantly changing technology in the wafer fabrication industry. New technologies result in denser packing of minuscule surface features such as transistors and micro-electro-mechanical systems (MEMS). This increased density continues the trend often cited as Moore's Law.

In various aspects of the present disclosure, a semiconductor starting wafer is prepared prior to any front-end-of-line (FEOL) processing employed for forming semiconductor device structures in and on the semiconductor starting wafer. The prepared semiconductor starting wafer may be prepared such that semiconductor device structures may be subsequently fabricated by using advanced technologies, i.e., technologies applied to approach technology nodes smaller than 100 nm, for example, smaller than 50 nm or smaller than 35 nm, e.g., at 22 nm or below. The person skilled in the art will appreciate that, according to the present disclosure, ground rules smaller or equal to 45 nm, e.g., at 22 nm or below, may be imposed. The person skilled in the art will appreciate that the prepared semiconductor starting wafer may be employed in the fabrication of semiconductor device structures having a minimal length dimension and/or width dimension smaller than 100 nm, for example, smaller than 50 nm or smaller than 35 nm or smaller than 22 nm. For example, the prepared semiconductor starting wafer may be employed in 45 nm technologies or below, e.g., 22 nm or even below.

In accordance with the present disclosure, FDSOI substrates have a thin semiconductor layer disposed on a buried insulating material layer, which in turn is formed on a base substrate. In accordance with some illustrative embodiments herein, the semiconductor layer may comprise one of silicon, silicon germanium and the like. The buried insulating material layer may comprise an insulating material, e.g., silicon oxide or silicon nitride. The base substrate may be a material that may be used as a substrate in the art, e.g., silicon, silicon germanium and the like. The person skilled in the art will appreciate that, in accordance with FDSOI substrates, the semiconductor layer may have a thickness of 30 nm or less, e.g., about 20 nm or less (e.g., in a range from about 10-20 nm), while the buried insulating material layer may have a thickness of about 145 nm or, in accordance with advanced techniques, the buried insulating material layer may have a thickness in a range from about 10-30 nm. For example, in some illustrative embodiments of the present disclosure, the semiconductor layer may have a desired thickness, or target thickness, in a range from about 2-10 nm.

With regard toFIGS. 2a-2e, some illustrative embodiments of a process of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration will be described in greater detail. The schematic illustration inFIGS. 2a-2eis not to scale and is only presented for the sake of describing some illustrative embodiments of the present disclosure in a non-limiting way.

FIG. 2aschematically illustrates a semiconductor starting wafer100that may be provided at the beginning of wafer processing, e.g., prior to the formation of gate structures during front-end-of-line (FEOL) processing. In accordance with illustrative embodiments of the present disclosure, the provided semiconductor starting wafer100has a base substrate101, a buried insulating material layer103, and a semiconductor layer105disposed on each other, wherein the buried insulating material layer103is interposed or sandwiched between the base substrate101and the semiconductor layer105. As indicated in the cross-sectional view ofFIG. 2a, an upper surface of the semiconductor layer105has a thickness variability, that is, the thickness of the semiconductor layer105varies by the amount as indicated by the double arrow109in addition to a minimal thickness t (corresponds inFIG. 2ato a thickness of the semiconductor layer105from an interface between 105 and 103 to the broken line107; in the following the thickness t is accordingly understood) with regard to a broken line107.

In accordance with some illustrative examples, the double arrow109may indicate a variability in the thickness of the semiconductor layer105, e.g., greater than 1 nm, and may be on the order of several nanometers.

In accordance with some illustrative embodiments of the present disclosure, the base substrate101may be a semiconductor base substrate as employed in SOI techniques, such as a silicon base substrate, germanium base substrate and the like. For example, the base substrate101may comprise monocrystalline silicon having a plane orientation of (100).

In accordance with some illustrative embodiments of the present disclosure, the semiconductor layer105may be, for example, P-type monocrystalline silicon having a plane orientation of (100), a crystal orientation (110) or (100) parallel to an orientation flat or notch.

In accordance with some illustrative embodiments, the semiconductor layer105may have an initial thickness of about 30 nm or less, e.g., in the range of about 10-20 nm. The person skilled in the art will appreciate that, in according illustrative embodiments, the starting wafer100may have an FDSOI configuration.

In accordance with some illustrative embodiments of the present disclosure, the buried insulating material layer103may be formed of a silicon oxide film having a thickness of 10 nm or less. This does not pose any limitation to the present disclosure and the buried insulating material layer103may be formed by silicon nitride instead.

FIG. 2bschematically illustrates the semiconductor starting wafer100at a more advanced stage during processing, when an oxidization process110is performed and an oxide surface region111is formed on the semiconductor layer105by oxidizing an upper surface region of the semiconductor layer105. In accordance with some illustrative examples of the present disclosure, the oxidization process110may comprise exposing the semiconductor starting wafer100to the oxidization process110in a furnace for thermally treating semiconductor wafers such that a thermal oxidization may be performed, or by performing a rapid thermal oxidization process. In still some other alternatives, the oxidization process110may include an oxidization process at low temperatures, such as plasma oxidization. However, this does not pose any limitation to the present disclosure.

In accordance with some illustrative embodiments of the present disclosure, the oxide surface region111may have a thickness in a range from about 2-10 nm, e.g., the oxide surface region111may have a thickness in a range from about 2-7 nm or in a range from about 2-5 nm or in a range from about 4-9 nm or in a range from about 4-7 nm.

In accordance with some illustrative embodiments of the present disclosure, the oxidization process110may be adjusted to oxidize the semiconductor layer105such that an amount of 5-20% of the thickness t of the semiconductor layer105is oxidized. For example, an amount of 10-20% of the thickness t of the semiconductor layer105may be oxidized.

FIG. 2cschematically illustrates the semiconductor starting wafer100at a more advanced stage during processing, at which a thinning of the oxide surface region111inFIG. 2bis performed, resulting in a thinned oxide surface region111′.

In accordance with some illustrative embodiments of the present disclosure, the thinning of the oxide surface region111inFIG. 2bmay comprise an ion beam induced etching112of the oxide surface region111inFIG. 2b. In accordance with some illustrative examples herein, the ion beam induced etching112may comprise scanning an ion beam over the semiconductor starting wafer100in a halocarbon environment. The person skilled in the art will appreciate that, during scanning of an ion beam over the semiconductor starting wafer100, an intensity of the scanning ion beam may be varied for locally thinning the oxide surface region111in a desired manner. In accordance with some special illustrative examples herein, the ion beam induced etching112may be configured to locally etch the oxide surface region111in a way such that a greater amount of material of the oxide surface region111is removed at positions on the surface of the semiconductor starting wafer100having a thicker semiconductor layer105and showing a greater variation109with respect to the broken line107inFIG. 2a.

In accordance with some illustrative alternative embodiments of the present disclosure, the thinning of the oxide surface region111inFIG. 2bmay comprise a local laser etching112of the oxide surface region111inFIG. 2b. In accordance with some illustrative examples herein, the local laser etching112may comprise scanning a laser beam, e.g., a focused laser beam, over the semiconductor starting wafer100in a halocarbon environment. The person skilled in the art will appreciate that, during scanning of a laser beam over the semiconductor starting wafer100, an intensity of the scanning laser beam may be varied for locally thinning the oxide surface region111in a desired manner. In accordance with some special illustrative examples herein, the local laser etching112may be configured to locally etch the oxide surface region111in a way such that a greater amount of material of the oxide surface region111is removed at positions on the surface of the semiconductor starting wafer100having a thicker semiconductor layer105and showing a greater variation109with respect to the broken line107inFIG. 2a.

FIG. 2dschematically illustrates the semiconductor starting wafer100at a more advanced stage during fabrication, particularly when the semiconductor starting wafer100is exposed to an oxidization process114. The oxidization process114is configured such that the thinned oxide surface region111′ is increased by the oxidization process114into the semiconductor layer105by forming a further oxide region111aand decreasing a thickness of the semiconductor layer105such that a semiconductor layer105′ of a decreased thickness relative to the semiconductor layer105inFIG. 2ais obtained.

In accordance with some illustrative embodiments of the present disclosure, during the oxidization process114, a thickness of the resulting oxide surface region (which is formed by the thinned oxide surface region111′ and the further oxide region111a) is locally increased in that a thickness of the thinned oxide surface region111′ is locally increased in dependence on a thickness of the thinned oxide surface region111′. For example, the oxide surface region111′ grows locally faster or slower in dependence on the local thickness of the oxide surface region111′. That is, with smaller thickness, the oxide surface region111′ grows faster and, with greater thickness, the oxide surface region111′ grows slower. The person skilled in the art will appreciate that a depth of the oxide surface region111′,111areaching into the semiconductor layer105′ becomes more even when compared to the variability of the thickness of the semiconductor layer105as denoted by double arrow109inFIG. 2a. In other words, the semiconductor layer105′ has a more uniform thickness when compared with the semiconductor layer105inFIG. 2a.

In accordance with some illustrative examples of the present disclosure, a variability of the semiconductor layer105′ relative to the variability of the thickness of the semiconductor layer105(as indicated by double arrow109inFIG. 2a) is reduced by at least 50%, e.g., by at least 70%.

In accordance with some illustrative embodiments of the present disclosure, the oxidization process114may comprise a thermal oxidization using a furnace or a rapid thermal oxidation process. Alternatively, without limitation, an oxidization process at low temperatures may be performed, such as plasma oxidation.

After a complete reading of the present disclosure, the person skilled in the art will appreciate that the boundary line separating the further oxide surface region111aand the semiconductor layer105′ may not be as smooth as the illustration inFIG. 2dshows. The illustration inFIG. 2dis only schematic and not limiting in this regard. The person skilled in the art will appreciate that the semiconductor layer105′ may have a varying thickness, however, the variability of the thickness of the semiconductor layer105′ being small as compared to the variability as illustrated by reference numeral109inFIG. 2a, particularly, the semiconductor layer105′ may have a thickness complying with any required uniformity.

FIG. 2eschematically illustrates the semiconductor starting wafer100at a more advanced stage during fabrication, after the oxide surface region111′,111ais removed and the semiconductor layer105′ is exposed, particularly, an upper surface105′uof the semiconductor layer105′ is exposed.

In accordance with some illustrative embodiments of the present disclosure, the oxide surface region111′,111amay be removed by an etching process (not illustrated), using DHF or CERTAS.

In accordance with some illustrative embodiments of the present disclosure, the oxidization process110inFIG. 2b, the thinning process112as illustrated inFIG. 2c, and the oxidization process114as illustrated inFIG. 2dmay be configured such that a target thickness of the semiconductor layer105′ may be reached. The target thickness of the semiconductor layer105′ may be set to at most about 30 nm.

In accordance with some illustrative embodiments, the target thickness may be set in the range from about 1-10 nm, such as in a range from about 5-10 nm (e.g., at about 6 nm), when processing a starting wafer being provided in accordance with FDSOI technologies. This does not pose any limitation to the present disclosure and the person skilled in the art will appreciate that, upon selecting an appropriate target thickness, semiconductor starting wafers100in accordance with other SOI technologies may be provided, e.g., PDSOI technologies.

In accordance with some illustrative embodiments of the present disclosure, a thickness profile of the semiconductor starting wafer100at the stage as illustrated inFIG. 2emay be performed.

In accordance with some illustrative embodiments of the present disclosure, based on the determined thickness profile of the semiconductor starting wafer100as illustrated inFIG. 2e, the process as described above with regard toFIGS. 2a-2emay be repeated in case that a desired thickness profile is not reached to a desired degree of accuracy. The person skilled in the art will appreciate, after a complete reading of the present disclosure, that the process as illustrated with regard toFIGS. 2a-2dmay be an iterative process, e.g., may be repeated at least one time for obtaining a desired thickness profile of the semiconductor layer105′.

In accordance with some illustrative embodiments of the present disclosure, the semiconductor starting wafer100may be subjected to FEOL processing for forming semiconductor devices, e.g., transistor devices and the like, in the semiconductor layer105′ and on the semiconductor layer105′.

In accordance with some illustrative embodiments of the present disclosure, a thickness profile of the semiconductor starting wafer100may be obtained by performing an ellipsometer thickness measurement. Herein, a fit between measurement points may be performed in accordance with known fitting procedures in accordance with known curve fitting methods in order to obtain best or optimized fits to a series of data points.

With regard to ellipsometer thickness measurements, the person skilled in the art will appreciate that ellipsometry is an optical technique for investigating the dielectric properties (complex, refractive, index or dielectric function) of thin films by measuring the change of polarization upon reflection or transmission of incident radiation in a known polarization state interacting with a material structure of interest (reflective, absorbed, scattered, transmitted) and measuring the change in the polarization of the incident radiation to the interacted radiation. As the measurement signal obtained in ellipsometry depends on the thickness of the material structure of interest, among other material properties, ellipsometry represents a contact-free determination of the thickness of a material structure of interest. For example, an ellipsometry experiment may be set up by a light source emitting a radiation of a predefined state (e.g., radiation prepared in a known state by a polarizer, commentator and the like), and a detector for detecting light reflected by a sample, the detector being configured to detect the change in the state of the incident radiation on the sample. After data acquisition and computation of the data in accordance with known evaluation methods, the acquired data is analyzed and the thickness of layers of the sample may be obtained. Accordingly, a thickness profile of the oxide surface region111and the semiconductor layer105inFIG. 2a, as well as a thickness profile of the semiconductor layer105′ inFIG. 2e, may be obtained.

With regard toFIG. 3, an illustrative process flow of a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration in accordance with some illustrative embodiments of the present disclosure will be described.

In accordance with some illustrative embodiments of the present disclosure, a semiconductor starting wafer may be provided at step310. The semiconductor starting wafer may be configured as discussed above with regard toFIG. 2a, the semiconductor starting wafer having an SOI configuration and, thus, comprising a base substrate, a semiconductor layer, and a buried insulating material layer interposed between the base substrate and the semiconductor layer.

At step330, the semiconductor starting wafer may be exposed to a first oxidization process, wherein an oxide surface region may be formed by oxidizing an upper surface region of the semiconductor layer. In accordance with some explicit examples, the first oxidization process may correspond to the oxidization process110as described above and the oxide surface region may correspond to the oxide surface region111as described above.

At step350, the oxide surface region may be thinned, e.g., in a dry etching process. In accordance with some illustrative examples herein, the thinning of the oxide surface region may be performed in accordance with the explanations given above with regard toFIG. 2c.

At step370, the semiconductor starting wafer may be exposed to a second oxidization process, wherein a thickness of the oxide surface region is locally increased. In accordance with some illustrative examples herein, the second oxidization process may correspond to the oxidization process112as described above with regard toFIG. 2d.

At step390, the oxide surface region may be removed, e.g., in a wet etching process, wherein the semiconductor layer having a preset target thickness is exposed. In accordance with some illustrative examples herein, the removal of the oxide surface region may be performed by using an agent for etching an oxide material, e.g., DHF or CERTAS.

With regard toFIG. 4, an illustrative process flow of a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration in accordance with some illustrative embodiments of the present disclosure will be described.

In accordance with some illustrative embodiments of the present disclosure, a semiconductor starting wafer may be provided at step410. The semiconductor starting wafer may be configured as discussed above with regard toFIG. 2a, the semiconductor starting wafer having an SOI configuration and, thus, comprising a base substrate, a semiconductor layer, and a buried insulating material layer interposed between the base substrate and the semiconductor layer.

At step430, the semiconductor starting wafer may be exposed to a first oxidization process, wherein an oxide surface region may be formed by oxidizing an upper surface region of the semiconductor layer. In accordance with some explicit examples, the first oxidization process may correspond to the oxidization process110as described above and the oxide surface region may correspond to the oxide surface region111as described above.

At step440, a thickness profile of each of the semiconductor layer and the oxide surface region may be determined. In accordance with some illustrative embodiments herein, the thickness profile may be determined in accordance with ellipsometry measurements as explained above.

At step445, a target thickness of the semiconductor layer may be determined. In accordance with some special illustrative examples herein, the target thickness may be determined on the basis of data relating to the thickness profiles of the semiconductor layer and the oxide surface region and/or data relating to at least one process performed during the processing of the semiconductor starting wafer, e.g., the first oxidization process, and at least one subsequent process to be described below. For example, the data may be based on feedforward modeling.

At step450, the oxide surface region may be thinned in a dry etching process. In accordance with some illustrative examples herein, the thinning of the oxide surface region may be performed in accordance with the explanations given above with regard toFIG. 2c.

At step470, the semiconductor starting wafer may be exposed to a second oxidization process, wherein a thickness of the oxide surface region is locally increased. In accordance with some illustrative examples herein, the second oxidization process may correspond to the oxidization process112as described above with regard toFIG. 2d.

At step490, the oxide surface region may be removed in a wet etching process, wherein the semiconductor layer having the target thickness is exposed. In accordance with some illustrative examples herein, the removal of the oxide surface region may be performed by using an agent for etching an oxide material, e.g., DHF or CERTAS.

After a complete reading of the present disclosure, the person skilled in the art will appreciate that a material quantity of the oxide surface region removed during the dry etch process as described above with regard to step350and/or450, or the thinning process as described above with regard toFIG. 2c, may depend on a local thickness of the semiconductor layer such that the removed material quantity of the oxide surface region increases with increasing local thickness of the semiconductor layer and decreases with decreasing local thickness of the semiconductor layer. Accordingly, the process for removing a material quantity of the oxide surface region during a thinning process of the oxide surface region may be controlled such that the removed material quantity locally correlates with a thickness of the semiconductor layer.

After a complete reading of the present disclosure, the person skilled in the art will appreciate that the oxide surface region may be locally increased during the second oxidization process as described with regard to step370and/or470above, or as described with regard toFIG. 2dabove, such that a uniformity of the thickness of the semiconductor layer is increased.

After a complete reading of the present disclosure, the person skilled in the art will appreciate that the second oxidization process as described above with regard to step370and/or470, or the oxidization process114as described with regard toFIG. 2dabove, may comprise an endpoint determination provided by feedforward model data or pre-calculated time data. For example, the endpoint determination may depend on the target thickness as described above with regard to step445.

After a complete reading of the present disclosure, the person skilled in the art will appreciate that at least some illustrative embodiments of the present disclosure as described above show a planarization of a semiconductor layer of a semiconductor starting wafer provided with an SOI configuration, where an upper surface of the semiconductor layer is oxidized such that an oxide is formed on the semiconductor layer, the oxide is locally thinned depending on a thickness profile of the semiconductor layer, and a further oxidization is performed prior to removing the oxide. Accordingly, semiconductor starting wafers having a semiconductor layer of a variability complying with advanced requirements on the variability as imposed by very large scale integration techniques and beyond may be obtained.

After a complete reading of the present disclosure, the person skilled in the art will appreciate that the semiconductor starting wafer as manufactured in accordance with at least some illustrative embodiments of the present disclosure may comply with any uniformity requirements on a thickness of the semiconductor layer of the manufactured starting wafer, e.g., by appropriately adjusting and tuning at least one process performed during the manufacturing, e.g., at least one of first oxidization processes, second oxidization processes, thinning processes, etching processes, and the like.

After a complete reading of the present disclosure, the person skilled in the art will appreciate that, in FDSOI technologies, starting wafers may be manufactured, the starting wafers having semiconductor layers (i.e., top semiconductor layers) with a deviation from a target thickness, e.g., an illustrative target thickness of less than about 10 nm (such as in a range from about 5-10 nm, e.g., at about 6 nm), being in a range of 1 angstroms (0.1 nm) or low single digit angstroms (e.g., around about 5 angstroms). In accordance with some illustrative examples, a thickness of an oxide surface region formed in a first oxidation process may vary locally between 2-10 nm.