Nonvolatile semiconductor memory device and method for manufacturing same

According to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of first semiconductor regions; a plurality of control gate electrodes; a charge storage layer; a first insulating film provided between the charge storage layer and first semiconductor regions; a second insulating film provided between the charge storage layer and control gate electrodes; and an element isolation region provided between the plurality of first semiconductor regions, and the element isolation region being in contact with the first insulating film and a first portion of the charge storage layer on the first insulating film side. Each of the plurality of control gate electrodes is in contact with a second portion other than the first portion of the charge storage layer. The charge storage layer includes a silicon-containing layer in contact with the first insulating film and a silicide-containing layer provided on the silicon-containing layer.

FIELD

Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a method for manufacturing same.

BACKGROUND

In a nonvolatile semiconductor memory device typified by a NAND flash memory, while miniaturization is progressing, the element isolation region is configured to have a prescribed depth to ensure the electrical insulation between elements.

However, with the progress of miniaturization, the width of the floating gate becomes narrower. Hence, there is a problem that depletion of the upper portion of the floating gate is likely to occur and the stability of writing and the stability of reading are not sufficient. Thus, a nonvolatile semiconductor memory device is desired that is good in the stability of writing and the stability of reading even when miniaturization progresses.

DETAILED DESCRIPTION

In general, according to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of first semiconductor regions extending in a first direction, and the plurality of first semiconductor regions being arranged in a direction crossing the first direction; a plurality of control gate electrodes provided on an upper side of the plurality of first semiconductor regions, the plurality of control gate electrodes extending in a second direction different from the first direction, and the plurality of control gate electrodes being arranged in a direction crossing the second direction; a charge storage layer provided in a position, and each of the plurality of first semiconductor regions and each of the plurality of control gate electrodes cross in the position; a first insulating film provided between the charge storage layer and each of the plurality of first semiconductor regions; a second insulating film provided between the charge storage layer and each of the plurality of control gate electrodes; and an element isolation region provided between adjacent ones of the plurality of first semiconductor regions, and the element isolation region being in contact with the first insulating film and a first portion of the charge storage layer on the first insulating film side.

Each of the plurality of control gate electrodes is in contact with a second portion other than the first portion of the charge storage layer via the second insulating film. The charge storage layer includes a silicon-containing layer in contact with the first insulating film and a silicide-containing layer provided on the silicon-containing layer.

Hereinbelow, embodiments are described with reference to the drawings. In the following description, identical components are marked with the same reference numerals, and a description of components once described is omitted as appropriate.

First Embodiment

FIG. 1is a schematic plan view showing a nonvolatile semiconductor memory device according to a first embodiment.

FIG. 2Ais a schematic cross-sectional view showing the nonvolatile semiconductor memory device in the position of line A-A′ ofFIG. 1, andFIG. 2Bis a schematic cross-sectional view showing the nonvolatile semiconductor memory device in the position of line B-B′ ofFIG. 1. InFIG. 2AandFIG. 2B, the positive direction of the Z axis is set upward and the negative direction is set downward.

FIG. 3is an enlarged schematic cross-sectional view of a charge storage layer and the surroundings of the charge storage layer ofFIG. 2A.

As shown inFIG. 1, a nonvolatile semiconductor memory device1includes a plurality of semiconductor regions11(first semiconductor regions) and a plurality of control gate electrodes60.

Each of the plurality of semiconductor regions11extends in the Y direction (a first direction). The plurality of semiconductor regions11are arranged in a direction (e.g. the X direction) crossing the Y direction. The conductivity type of the plurality of semiconductor regions11is, for example, the p type.

Each of the plurality of control gate electrodes60is provided on the upper side of the plurality of semiconductor regions11. Each of the plurality of control gate electrodes60extends in the X direction (a second direction) different from the Y direction. The plurality of control gate electrodes60are arranged in a direction (e.g. the Y direction) crossing the X direction.

The plurality of control gate electrodes60are provided on the upper side of the plurality of semiconductor regions11. In the nonvolatile semiconductor memory device1, each of the plurality of semiconductor regions11and each of the plurality of control gate electrodes60cross.

A transistor is disposed in the position where each of the plurality of semiconductor regions11and each of the plurality of control gate electrodes60cross. The transistor is described later. The transistors are arranged two-dimensionally in the X direction and the Y direction. Each transistor functions as a memory cell of the nonvolatile semiconductor memory device1.

As shown inFIG. 2AandFIG. 2B, the nonvolatile semiconductor memory device1includes the semiconductor region11, the control gate electrode60, a charge storage layer30, a gate insulating film20(a first insulating film), an IPD (inter poly dielectric) film40(a second insulating film), an element isolation region50, a semiconductor region10, and an insulating layer70. The conductivity type of the semiconductor region10is the n type. The charge storage layer30may be referred to as a floating gate layer30. The control gate electrode60may be referred to as a word line60. The IPD film40may be referred to as a charge block film40. The semiconductor region10and the semiconductor region11are collectively referred to as a semiconductor layer12.

In the nonvolatile semiconductor memory device1, the semiconductor region11, the gate insulating film20, the charge storage layer30, the IPD film40, and the control gate electrode60constitute a transistor. The transistor is provided in the position where the semiconductor region11and the control gate electrode60cross.

Each of the plurality of semiconductor regions11forms part of a NAND string. Each of the plurality of semiconductor regions11is separated by the element isolation region50. Each of the plurality of semiconductor regions11is defined by the element isolation region50in the semiconductor layer12. Each of the plurality of semiconductor regions11functions as an active area of the transistor.

The charge storage layer30is provided in the position where each of the plurality of semiconductor regions11and each of the plurality of control gate electrodes60cross. The charge storage layer30is in a rectangular shape extending in the Z direction in the A-A′ cross section and the B-B′ cross section shown inFIG. 2AandFIG. 2B. Thus, the charge storage layer30has a prismatic shape extending in the Z direction. The charge storage layer30can store a charge that has tunneled from the semiconductor region11via the gate insulating film20.

Here, the charge storage layer30includes a silicon-containing layer31in contact with the gate insulating film20and a silicide-containing layer32provided on the silicon-containing layer31.

The resistivity of the silicide-containing layer32is lower than the resistivity of the silicon-containing layer31. The silicon-containing layer31includes, for example, a polysilicon (poly-Si) layer doped with an impurity element such as boron (B). The silicide-containing layer32includes a layer of a silicide made out of polysilicon doped with an impurity element such as boron (B). As the metal for making a silicide out of polysilicon, for example, at least one metal selected from titanium (Ti), nickel (Ni), cobalt (Co), molybdenum (Mo), and tungsten (W) is given.

The length from the lower end31dof the silicon-containing layer31to the upper end50uof the element isolation region50is the same as the length from the lower end31dof the silicon-containing layer31to the junction30cbetween the silicon-containing layer31and the silicide-containing layer32(corresponding to the thickness of the silicon-containing layer31in the Z direction). For example, the height of the upper end50uof the element isolation region50is the same as the height of the junction30c.

The width of the silicide-containing layer32in a direction (e.g. the X direction) crossing the Y direction is, for example, 5 nm (nanometers) or less.

The gate insulating film20is provided between the charge storage layer30and each of the plurality of semiconductor regions11. The gate insulating film20functions as a tunnel insulating film through which a charge (e.g. electrons) tunnels between the semiconductor region11and the charge storage layer30.

The IPD film40is provided between the charge storage layer30and each of the plurality of control gate electrodes60. The element isolation region50is provided between adjacent ones of the plurality of semiconductor regions11. The IPD film40covers the upper surface30uof the charge storage layer30. The IPD film40further covers part of the side wall32wof the charge storage layer30.

Each of the plurality of control gate electrodes60is in contact with the charge storage layer30via the IPD film40. For example, as shown inFIG. 2A, the control gate electrode60is in contact with, via the IPD film40, a portion of the charge storage layer30other than a portion of the charge storage layer30with which the element isolation region50is in contact. In other words, each of the plurality of control gate electrodes60has an extending portion60ain contact with the charge storage layer30via the IPD film40. Adjacent ones of the plurality of extending portions60asandwiches the charge storage layer30.

That is, the control gate electrode60covers part of the charge storage layer30via the IPD film40. For example, the control gate electrode60covers the upper surface30uand part of the side wall32wof the charge storage layer30via the IPD film40(seeFIG. 2A). The control gate electrode60covers the upper surface30uof the charge storage layer30via the IPD film40(seeFIG. 2B). The control gate electrode60functions as a gate electrode for controlling the transistor.

The element isolation region50is in contact with the gate insulating film20and a portion of the charge storage layer30on the gate insulating film20side. The element isolation region50is further in contact with the semiconductor region10. The insulating layer70is provided between adjacent ones of the plurality of control gate electrodes60. The insulating layer70is in contact with the IPD film40, the charge storage layer30, and the gate insulating film20. For example, as shown inFIG. 2B, the insulating layer70covers the side wall32wof the charge storage layer30.

That is, the upper surface30uand the side wall32wof the charge storage layer30are covered with an insulator including the IPD film40and the insulating layer70. Thereby, the charge stored in the charge storage layer30is prevented from leaking to the control gate electrode60.

The material of the semiconductor region11is silicon doped with boron (B) and/or the like. The material of the semiconductor region10is silicon doped with phosphorus (P), arsenic (As), and/or the like. The gate insulating film20may be a NON film like that shown inFIG. 3in which a silicon nitride film20a, a silicon oxide film20b, and a silicon nitride film20care stacked in this order, or may be a single-layer film of a silicon oxide film or a silicon nitride film. The illustration of the gate insulating film20is only an example, and the gate insulating film20is not limited to this structure.

The material of the element isolation region50and the insulating layer70is, for example, silicon oxide (SiO2). The material of the control gate electrode60is, for example, polysilicon containing a p-type impurity. Alternatively, the material of the control gate electrode60may be a metal such as tungsten, a metal silicide, or the like.

As shown inFIG. 3, the upper end32uand the side wall32wof the silicide-containing layer32are covered by the IPD film40. The IPD film40includes a nitride film40a(a second nitride film) in contact with the silicide-containing layer32, an oxide film40bcovering the nitride film40a, and a nitride film40ccovering the oxide film40b.

The material of the nitride film40ais titanium silicon nitride (SiTIN), titanium nitride (TiN), or the like. The material of the oxide film40bis silicon oxide (SiO2) or the like. The material of the nitride film40cis silicon nitride (SiN) or the like.

In the embodiment, the p type may be taken as a first conductivity type and the n type may be taken as a second conductivity type, or the n type may be taken as the first conductivity type and the p type may be taken as the second conductivity type. As the p-type impurity element, for example, boron (B) is given. As the n-type impurity element, for example, phosphorus (P) and arsenic (As) are given.

The manufacturing process of the nonvolatile semiconductor memory device1will now be described.

The method for forming films and layers described below is, unless otherwise specified, appropriately selected from CVD (chemical vapor deposition), the sputtering method, the ALD (atomic layer deposition) method, the epitaxial method, the spin coating method, etc. The removal of films and layers is appropriately selected from dry etching such as RIE (reactive ion etching), wet etching using a hydrofluoric acid solution, an alkaline solution, or the like, and ashing using an oxygen-containing gas.

FIG. 4AtoFIG. 11Bare schematic views showing the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment.

OfFIG. 4AtoFIG. 11B, the drawings of the numbers including “A” show a cross section corresponding to line A-A′ ofFIG. 1, and the drawings of the numbers including “B” show a plan view.

First, as shown inFIG. 4AandFIG. 4B, a stacked body15is prepared. The stacked body15includes the semiconductor layer12, the gate insulating film20provided on the semiconductor layer12, and the silicon-containing layer31provided on the gate insulating film20. The stacking direction of the stacked body15is the Z direction. Subsequently, a plurality of mask layers90extending in the Y direction and arranged in a direction (e.g. the X direction) crossing the Y direction are formed on the stacked body15.

The patterning of the mask layer90is performed by, for example, photolithography and etching. As the material of the mask layer90, a material having a high processing selectivity to the semiconductor is selected. For example, the material of the mask layer90is silicon oxide (SiO2), silicon nitride (SiN), a resist, a material other than these, or a material in which these materials are stacked.

Next, as shown inFIG. 5AandFIG. 5B, etching is performed on the stacked body15exposed from the plurality of mask layers90. Thereby, a plurality of trenches80extending in the Y direction are formed in the semiconductor layer12. Consequently, the semiconductor region11sandwiched by adjacent ones of the plurality of trenches80is formed. The width of the silicide-containing layer32in the X direction is adjusted to 5 nm or less. The gate insulating film20extending in the Y direction is formed on the semiconductor region11, and the silicon-containing layer31extending in the Y direction is formed on the gate insulating film20.

Next, as shown inFIG. 6AandFIG. 6B, the element isolation region50is formed in each of the plurality of trenches80.

Next, as shown inFIG. 7AandFIG. 7B, the element isolation region50is etched back. Thereby, the element isolation region50in contact with the semiconductor region11, the gate insulating film20, and a portion of the silicon-containing layer31on the gate insulating film20side is formed in each of the plurality of trenches80. After that, the mask layer90is removed. Then, the natural oxide film formed on the surface of the silicon-containing layer31is removed.

Next, the portion exposed from the element isolation region50of the silicon-containing layer31is exposed to a metal element-containing gas35. Then, the silicon-containing layer31is heated.FIG. 8AandFIG. 8Bshow the state after the silicon-containing layer31is exposed to the metal element-containing gas35.

As the metal element-containing gas35, for example, a metal chloride is used. As the metal chloride, for example, titanium tetrachloride (TiCl4) is given. As the metal chloride, also a chloride of at least one metal selected from nickel (Ni), cobalt (Co), molybdenum (Mo), and tungsten (W) may be used. The heating temperature is not less than 500° C. and not more than 600° C.

The metal (e.g. Ti) in the metal chloride selectively reacts more with the silicon-containing layer31than with the element isolation region50. Consequently, part of the silicon-containing layer31is made into a silicide. That is, the charge storage layer30including the silicon-containing layer31and the silicide-containing layer32is formed on the gate insulating film20. In the case where titanium tetrachloride is used, the silicide-containing layer32contains, for example, titanium silicide (TiSi).

Subsequently, after part of the silicon-containing layer31is made into a silicide, the silicon-containing layer that has become a silicide is exposed to a nitrogen-containing gas. Thereby, the surface of the charge storage layer30exposed from the element isolation region50is nitrided (see the nitride film40aofFIG. 3). Then, the oxide film40band the nitride film40care formed. Thereby, the IPD film40including the nitride film40a, the oxide film40b, and the nitride film40cis formed.FIG. 9AandFIG. 9Bshow this state.

As shown inFIG. 9AandFIG. 9B, the portion exposed from the element isolation region50of the charge storage layer30is covered by the IPD film40.

Next, as shown inFIG. 10AandFIG. 10B, a control gate electrode layer60L is formed in each of the plurality of trenches80and on the charge storage layer30via the IPD film40.

Next, as shown inFIG. 11AandFIG. 11B, the control gate electrode layer60L is divided into a plurality of control gate electrodes60. The control gate electrode layer60L is divided by photolithography and etching. After the division, the plurality of control gate electrodes60extend in the X direction, and are arranged in the Y direction. After that, the insulating layer70is formed on the semiconductor region11between adjacent ones of the plurality of control gate electrodes60(seeFIG. 2B). By such a manufacturing process, the nonvolatile semiconductor memory device1is formed.

FIG. 12is a schematic cross-sectional view showing a nonvolatile semiconductor memory device according to a reference example.

In a nonvolatile semiconductor memory device100according to the reference example, the charge storage layer is a single layer. The charge storage layer of the reference example is formed of the silicon-containing layer31.

A case is assumed where, for example, in the nonvolatile semiconductor memory device100, miniaturization has progressed and the width in the X direction of the silicon-containing layer31has become minute (e.g. 5 nm or less).

In this case, for example, when in the time of the writing of data a positive potential is applied to the control gate electrode60and a negative potential (or the ground potential) is applied to the semiconductor region11, depletion is likely to occur in the upper portion31aof the silicon-containing layer31. This is because the silicon-containing layer31is very fine and the electric field is likely to concentrate at the upper end of the silicon-containing layer31.

There are few carriers in the depletion layer. Therefore, in the time of the writing of data, an insulating layer of the thicknesses of the IPD film40and the depletion layer (the upper portion31a) exists on the silicon-containing layer31. In other words, in the time of the writing of data, the substantial thickness of the silicon-containing layer31is the thickness excluding that of the depletion layer (the upper portion31a). That is, a charge cannot be stored in the portion where the depletion layer is formed.

Therefore, in the nonvolatile semiconductor memory device100, the silicon-containing layer31cannot be made to sufficiently function as a charge storage layer, and the stability of data writing is not sufficient. Furthermore, also in the time of data reading, depletion in the upper portion31aof the silicon-containing layer31is likely to occur, and the stability of data reading is not sufficient. For example, a Vth jump phenomenon may occur in which the threshold voltage (Vth) in data reading rises steeply. Thus, it is preferable to suppress the depletion in the upper portion of the charge storage layer.

As a first means for suppressing the depletion in the upper portion of the charge storage layer, there may be a means in which the concentration of the impurity element contained in the charge storage layer is increased. This is because the increase in the impurity element concentration decreases the resistivity of the charge storage layer and suppresses the extension of the depletion layer.

For example, there is a means in which a high concentration impurity element is introduced into the upper portion of the charge storage layer by plasma doping. However, when plasma is used, the very fine charge storage layer is damaged and a good quality charge storage layer is not formed.

As a second means, there may be a means in which the silicon-containing layer31of the stacked body15is replaced with a metal layer (or a silicide layer). That is, it is a means in which a stacked body composed of the semiconductor layer12/the gate insulating film20/a metal layer (or a silicide layer) is prepared before the trench80is formed. By this means, the charge storage layer is made of a metal (or a silicide), and it can be foreseen that the depletion in the upper portion of the charge storage layer will be suppressed.

However, when this means is employed, during forming the trench80, the metal or silicide that is a component of the charge storage layer may go through the trench80to adhere to the semiconductor regions10and11as a residue, and the attached metal or silicide may diffuse into the semiconductor regions10and11. Consequently, the electric conductivity, conductivity type, etc. of the semiconductor regions10and11may be changed to cause a loss to the function as an active area of the semiconductor region11.

In contrast, in the first embodiment, the lower side of the charge storage layer30is formed of the silicon-containing layer31and the upper side of the charge storage layer30is formed of the silicide-containing layer32. The resistivity of the silicide-containing layer32is lower than the resistivity of the silicon-containing layer31. Therefore, in the time of data writing and reading, the depletion in the upper portion of the charge storage layer30is suppressed. Thus, data writing and reading are stabilized.

The formation of the silicide-containing layer32is performed not by plasma doping but by a thermal reaction. Therefore, the charge storage layer30is less likely to be damaged in the process and a good quality charge storage layer is formed. Furthermore, the silicide-containing layer32is a salicide (self aligned silicide) layer formed by exposing the silicon-containing layer31to a reaction gas. Therefore, even when miniaturization progresses by generations, the process of making a silicide follows the miniaturization by generations. Consequently, a charge storage layer with a narrow pitch and a very fine size is formed by generations.

In the first embodiment, the stacked body15before forming the trench80only includes the silicon-containing layer31. Hence, when the trench80is formed, there is no case where a metal or a silicide adheres to the semiconductor regions10and11as a residue. Even if a component of the silicon-containing layer31adheres to the semiconductor regions10and11, there is no problem because the main component of the silicon-containing layer31and the main component of the semiconductor regions10and11are both the same silicon (Si). Thereby, the electric conductivity, conductivity type, etc. of the semiconductor regions10and11are less likely to be changed, and the function as an active area of the semiconductor region11is not lost.

In the nonvolatile semiconductor memory device1, not only is the control gate electrode60in contact with the upper end of the charge storage layer30via the IPD film40, but the control gate electrode60is also in contact with the side wall32wof the charge storage layer30via the IPD film40. Thus, the charge storage state of the charge storage layer30is evenly reflected on the control gate electrode60.

Before the insulating layer70is buried, infrastructure processing for forming the source/drain is performed. The source/drain regions are not shown.

Second Embodiment

FIG. 13is a schematic cross-sectional view showing a nonvolatile semiconductor memory device according to a second embodiment.

FIG. 13is an enlarged schematic cross-sectional view of the charge storage layer and the surroundings of the charge storage layer.

The basic structure of a nonvolatile semiconductor memory device2is the same as the basic structure of the nonvolatile semiconductor memory device1. However, the ratio between the thickness of the silicon-containing layer31and the thickness of the silicide-containing layer32is different from the ratio between the thickness of the silicon-containing layer31and the thickness of the silicide-containing layer32in the nonvolatile semiconductor memory device1.

In the nonvolatile semiconductor memory device2, the length d1 from the lower end31dof the silicon-containing layer31to the junction30cbetween the silicon-containing layer31and the silicide-containing layer32is longer than the length d2 from the junction30cto the upper end32uof the silicide-containing layer32(corresponding to the thickness of the silicide-containing layer32in the Z direction). That is, the thickness in the Z direction of the silicon-containing layer31is thicker than the thickness in the Z direction of the silicide-containing layer32.

For example, the length d2 is not less than 10% and not more than 20% of the length d3 from the lower end of the charge storage layer30(corresponding to the lower end31dof the silicon-containing layer31) to the upper end of the charge storage layer30(the upper end32uof the silicide-containing layer32). That is, the thickness in the Z direction of the silicide-containing layer32is not less than 10% and not more than 20% of the thickness in the Z direction of the charge storage layer30. The length d2 is set to, for example, the thickness in the Z direction of the depletion layer in the reference example.

FIG. 14AandFIG. 14Bare schematic cross-sectional views showing the manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment.

The manufacturing process of the nonvolatile semiconductor memory device2is basically the same as the manufacturing process of the nonvolatile semiconductor memory device1. However, in the manufacturing process of the nonvolatile semiconductor memory device2, the etchback of the element isolation region50is performed at least two times. That is, the etchback of the element isolation region50includes the first etchback processing and the second etchback processing.

For example, the first etchback processing is performed from the state ofFIG. 6AandFIG. 6B. Thereby, the element isolation region50shown inFIG. 14Ais obtained. In this stage, the upper end50uof the element isolation region50is located at a depth of d2 from the upper end31uof the silicon-containing layer31.

The length d2 in the Z direction of the portion of the silicon-containing layer31exposed from the element isolation region50by the first etchback processing is shorter than the length d1 in the Z direction of the portion of the silicon-containing layer31not exposed from the element isolation region50.

For example, the length d2 in the Z direction of the portion of the silicon-containing layer31exposed from the element isolation region50by the first etchback processing is adjusted to not less than 10% and not more than 20% of the length in the Z direction of the silicon-containing layer31.

Subsequently, after the first etchback processing, the portion exposed from the element isolation region50of the silicon-containing layer31is exposed to a metal element-containing gas (e.g. TiCl4). Thereby, a portion of the silicon-containing layer31extending approximately d2 in depth from the upper end31uof the silicon-containing layer31is changed into the silicide-containing layer32.

After that, the second etchback processing is performed on the element isolation region50.FIG. 14Bshows this state. In this stage, the element isolation region50in contact with the semiconductor region11, the gate insulating film20, and a portion of the silicon-containing layer31on the gate insulating film20side is formed. After that, the IPD film40is formed. By such a manufacturing process, the nonvolatile semiconductor memory device2is formed.

In the nonvolatile semiconductor memory device2, since the portion where the depletion layer is formed in the reference example is replaced with the silicide-containing layer32, depletion can be suppressed similarly to the nonvolatile semiconductor memory device1. The nonvolatile semiconductor memory device2exhibits similar effects to the nonvolatile semiconductor memory device1. In addition, the nonvolatile semiconductor memory device2exhibits the following effect.

The resistivity of the silicide-containing layer32is lower than the resistivity of the silicon-containing layer31. Therefore, after data writing, electrons are preferentially stored more in the silicide-containing layer32than in the silicon-containing layer31.

In the nonvolatile semiconductor memory device2, the junction30cbetween the silicon-containing layer31and the silicide-containing layer32is located more on the upper side than in the nonvolatile semiconductor memory device1. In other words, in the nonvolatile semiconductor memory device2, the junction30cis located more on the upper side than in the nonvolatile semiconductor memory device1. The silicide-containing layer32of the nonvolatile semiconductor memory device2is more away from the semiconductor region11than the silicide-containing layer32of the nonvolatile semiconductor memory device1.

Therefore, in the nonvolatile semiconductor memory device2, after data writing, electrons stored in the silicide-containing layer32are less likely to be released to the semiconductor region11. That is, the data retention ability of the nonvolatile semiconductor memory device2is further increased as compared to the data retention ability of the nonvolatile semiconductor memory device1.

Third Embodiment

FIG. 15is a schematic cross-sectional view showing a nonvolatile semiconductor memory device according to a third embodiment.

The basic structure of a nonvolatile semiconductor memory device3is the same as the basic structure of the nonvolatile semiconductor memory device2. However, the charge storage layer30of the nonvolatile semiconductor memory device3includes a nitride film38(a first nitride film). The nitride film (SiN)38is provided on the lower side of the silicide-containing layer32. AlthoughFIG. 15illustrates a state where the silicide-containing layer32and the nitride film38are apart, the nitride film38may be in contact with the silicide-containing layer32.

The nitride film38functions as a barrier film that suppresses the diffusion of the impurity element (e.g. boron) contained in the silicon-containing layer31to the silicide-containing layer32. The thickness of the nitride film38is so adjusted that electrons can pass through the nitride film38. The thickness of the nitride film38is, for example, in the order of atoms.

FIG. 16toFIG. 17Bare schematic cross-sectional views showing the manufacturing process of the nonvolatile semiconductor memory device according to the third embodiment.

First, as shown inFIG. 16, the stacked body15including the silicon-containing layer31including the nitride film38is prepared. In the stacked body15, the silicon-containing layer31is provided on the upper and lower sides of the nitride film38. After that, the processes described inFIG. 5andFIG. 6are performed.

Next, as shown inFIG. 17AandFIG. 17B, the etchback of the element isolation region50is performed at least two times.

For example, the first etchback processing is performed. Thereby, the element isolation region50shown inFIG. 17Ais obtained. In this stage, the upper end50uof the element isolation region50is located at a depth of d2 from the upper end31uof the silicon-containing layer31.

The length d2 in the Z direction of the portion of the silicon-containing layer31exposed from the element isolation region50by the first etchback processing is shorter than the length d1 in the Z direction of the portion of the silicon-containing layer31not exposed from the element isolation region50. The position of the upper end50uof the element isolation region50is adjusted to a position higher than the position of the nitride film38.

Subsequently, after the first etchback processing, the portion exposed from the element isolation region50of the silicon-containing layer31is exposed to a metal element-containing gas (e.g. TiCl4). A portion of the silicon-containing layer31on the upper side of the nitride film38is exposed to the metal element-containing gas. Thereby, a portion of the silicon-containing layer31extending approximately d2 in depth from the upper end31uof the silicon-containing layer31is changed into the silicide-containing layer32.

After that, the second etchback processing is performed on the element isolation region50.FIG. 17Bshows this state. In this stage, the element isolation region50in contact with the semiconductor region11, the gate insulating film20, and a portion of the silicon-containing layer31on the gate insulating film20side is formed. After that, the IPD film40is formed. By such a manufacturing process, the nonvolatile semiconductor memory device3is formed.

Also in the nonvolatile semiconductor memory device3, similar effects to the nonvolatile semiconductor memory device2are exhibited. In addition, the nonvolatile semiconductor memory device3exhibits the following effects.

A case is assumed where, for example, titanium (Ti) is contained in the silicide-containing layer32. In this case, due to the affinity between titanium and boron (B) contained in the silicon-containing layer31, the silicide-containing layer32may absorb boron in the silicon-containing layer31to form titanium boride (TiB) in the silicide-containing layer32. The titanium boride exhibits insulating properties, and the resistivity of the silicide-containing layer32may be increased. Thus, it is preferable to suppress the diffusion of boron from the silicon-containing layer31to the silicide-containing layer32.

In the nonvolatile semiconductor memory device3, the nitride film38functioning as a barrier film is provided on the lower side of the silicide-containing layer32. Therefore, the diffusion of boron from the silicon-containing layer31to the silicide-containing layer32is suppressed by the nitride film38.

In the nonvolatile semiconductor memory device3, by providing the nitride film38, the impurity concentration of the silicon-containing layer31can be increased as compared to the impurity concentration of the silicon-containing layer31of the nonvolatile semiconductor memory devices1and2. This means, to the electrons stored in the silicide-containing layer32, that the barrier at the junction30cbecomes higher. Consequently, electrons stored in the silicide-containing layer32after writing are less likely to diffuse to the semiconductor region11, and the data retention ability is further increased.

Hereinabove, embodiments are described with reference to specific examples. However, the embodiment is not limited to these specific examples. That is, one skilled in the art may appropriately make design modifications to these specific examples, and such modifications also are included in the scope of the embodiment to the extent that the spirit of the embodiment is included. The components of the specific examples described above and the arrangement, material, conditions, shape, size, etc. thereof are not limited to those illustrated but may be appropriately altered.

The term “on” in “a portion A is provided on a portion B” refers to the case where the portion A is provided on the portion B such that the portion A is in contact with the portion B and the case where the portion A is provided above the portion B such that the portion A is not in contact with the portion B.

Furthermore, components of the embodiments described above may be combined within the extent of technical feasibility, and combinations of them also are included in the scope of the embodiment to the extent that the spirit of the embodiment is included. Furthermore, one skilled in the art may arrive at various alterations and modifications within the idea of the embodiment. Such alterations and modifications should be seen as within the scope of the embodiment.