Image pickup apparatus, image pickup system and method for driving image pickup apparatus

A signal based on a pixel signal of a first pixel sampled by a capacitor element is held by a signal holding unit with a switch left turned on.

BACKGROUND OF THE INVENTION

Field of the Invention

The aspect of the embodiments relates to an image pickup apparatus, an image pickup system and a method for driving an image pickup apparatus.

Description of the Related Art

An image pickup apparatus has been known in which a plurality of pixels is arranged over a plurality of rows and a plurality of columns.

In addition, there is an image pickup apparatus which includes a signal holding unit which holds a signal output by a pixel and an AD conversion unit which converts the signal held by the signal holding unit to a digital signal, such as that described in Japanese Patent Laid-Open No. 2008-67358. A switch is provided in an electrical path between the signal holding unit and the pixel. The signal holding unit holds a signal output by the pixel by the switch being brought into a non-conductive state after it has been in a conductive state.

SUMMARY OF THE INVENTION

A first aspect of the embodiments is an image pickup apparatus comprising: a plurality of pixels, each of the pixels being configured to output a pixel signal to a signal line; a capacitor element; a signal holding unit; a switch having one node connected to the signal line and another node connected to the capacitor element and the signal holding unit, wherein the capacitor element samples the pixel signal when the switch is turned on, and holds the pixel signal output when the switch is turned off, the pixel signal of a first pixel among the pixels is output to the signal line, and a signal based on the pixel signal of the first pixel sampled by the capacitor element by turning the switch on is held by the signal holding unit with the switch left turned on. In addition, another aspect of the embodiments is a method for driving an image pickup apparatus, the image pickup apparatus comprising: a plurality of pixels, each of the pixels being configured to output a pixel signal to a signal line; a capacitor element; and a signal holding unit configured to hold a signal based on the pixel signal, in which the capacitor element is capable of sampling the pixel signal and holding the pixel signal, in the method a first pixel among the pixels outputs the pixel signal to the signal line, and in a period during which the capacitor element samples the pixel signal of the first pixel, the signal holding unit holds a signal based on the pixel signal of the first pixel.

DESCRIPTION OF THE EMBODIMENTS

In the image pickup apparatus of Japanese Patent Laid-Open No. 2008-67358, a noise generated by a conduction or non-conduction operation of a switch is superimposed onto a signal output by a pixel. Consequently, a noise included in a signal held by a signal holding unit increases, which can be an issue.

The embodiments described below relate to technology for reducing a noise included in a signal held by a signal holding unit.

Hereinbelow, each embodiment will be described with reference to the drawings.

First Embodiment

FIG. 1illustrates a configuration of an image pickup apparatus of a first embodiment. The image pickup apparatus includes a pixel array1000, an amplifying circuit1100, a sampling and holding unit1200, and an AD conversion unit1300. The image pickup apparatus further includes a current source160, a vertical scanning circuit170, a counter320, and a horizontal scanning circuit360.

The pixel array1000includes pixels150arranged over a plurality of rows and a plurality of columns. Each pixel150includes a photodiode10p, a reset transistor11p, a selection transistor12p, an amplifying transistor13p, and a transfer transistor14p. In the above, p is a number obtained by subtracting 1 from the number of the row where the pixel is located. The photodiode10pis a photoelectric conversion unit which generates charge based on light. The transfer transistor14pand the photodiode10pare connected to an input node of the amplifying transistor13p. A signal READ(n) is input to a gate of the transfer transistor14pfrom the vertical scanning circuit170. What is meant by (n) is that the signal output by the vertical scanning circuit170is input to a pixel150located in the n-th row. One node of the reset transistor11pis connected to the input node of the amplifying transistor13p, and a power supply voltage is input to another node thereof. A signal RES(n) is input to a gate of the reset transistor11pfrom the vertical scanning circuit170. One node of the amplifying transistor13pis connected to the selection transistor12p, and the power supply voltage is input to another node thereof. One node of the selection transistor12pis connected to the amplifying transistor13p, and another node thereof is connected to a vertical signal line165. A signal SEL(n) is input to a gate of the selection transistor12pfrom the vertical scanning circuit170. The vertical signal line165is connected to the current source160and a switch175included in the amplifying circuit1100. When a signal PSEL(n) transitions to High, the selection transistor12pis turned on. Consequently, a current supplied by the current source160is input to the amplifying transistor13pthrough the selection transistor12p. The amplifying transistor13poutputs a pixel signal, which is a signal based on a potential of the input node, to the vertical signal line165through the selection transistor12p. The amplifying transistor13pperforms a source follower operation with the power supply voltage and the current source160. In other words, the power supply voltage, the current source160, and the amplifying transistor13pconstitute a source follower circuit.

The amplifying circuit1100includes the switch175, a capacitor element190, an amplifier180, a capacitor element200, and a switch210. The switch175is controlled by a signal VLON input from a timing generator (not illustrated). The switch210is controlled by a signal ARES input from the timing generator (not illustrated). The amplifier180outputs a signal obtained by amplifying an input signal at a gain represented by “a capacitance value of the capacitor element190/a capacitance value of the capacitor element200” to a switch220included in the sampling and holding unit1200.

The sampling and holding unit1200includes the switch220, a capacitor element230, a buffer240, and a switch250. The switch220is controlled by a signal SH input from the timing generator (not illustrated). The switch250is controlled by a signal TH input from the timing generator (not illustrated). The capacitor element230holds a signal based on a signal output by the pixel150by the switch220being brought into a non-conductive state after it has been in a conductive state. One node of the capacitor element230is connected to the switch220. The one node of the capacitor element230is connected to a first memory330as a signal holding unit through the buffer240, a capacitor element260, a comparator280, and a latch310. A ground voltage as a reference voltage is input to another node of the capacitor element230. The buffer240buffers an input signal and outputs the signal to the capacitor element260included in the AD conversion unit1300. Output of the amplifying circuit1100is represented by “output V_AOUT(m).” What is meant by (m) is that the amplifying circuit1100is an amplifying circuit1100located in the m-th column.

The AD conversion unit1300includes the capacitor element260, a capacitor element270, the comparator280, a switch290, a switch300, the latch310, the first memory330, a switch340, and a second memory350.

One input node of the comparator280is connected to the capacitor element260. Another input node of the comparator280has the capacitor element270. A ramp signal RAMP is input to the capacitor element270from a ramp signal supply unit (not illustrated). Each of the switch290and the switch300is controlled by a signal CRES output from the timing generator (not illustrated). Output V_COUT(m) of the comparator280is input to the latch310. What is meant by (m) is that the signal is output by a comparator280located in the m-th column. When receiving the output V_COUT(m) from the comparator280, the latch310outputs a signal LAT(m) to the first memory330.

The counter320generates a count signal by counting a clock signal. The count signal output by the counter320is input to the first memory330.

The switch340is controlled by a signal MREAD input from the timing generator (not illustrated). When the switch340is turned on, the second memory350holds a signal held by the first memory330.

The horizontal scanning circuit360sequentially scans the second memories350of respective columns, thereby reading, from the second memories350of respective columns, the signal held by the second memory350to an output unit370.

The output unit370outputs the signal output from the second memory350outside the image pickup apparatus.

Next, an operation of a comparative example which uses the configuration of the image pickup apparatus inFIG. 1will be described.

FIG. 2Aillustrates the operation of the comparative example. In the operation illustrated inFIG. 2A, a NAD period and an S-reading period are overlapped. In addition, a SAD period and an N-reading period of the pixel150in the next row are overlapped.

Details of the operation illustrated inFIG. 2Aare illustrated inFIG. 3.

A period from time t0to time t8illustrated inFIG. 3is the N-reading period illustrated inFIG. 2A.

At time t0inFIG. 3, the vertical scanning circuit170makes a signal SEL(1) transition to High. Consequently, a signal is output to the vertical signal line165from the pixel150in the first row.

At time t1inFIG. 3, the vertical scanning circuit170makes a signal RES(1) transition from High to Low. Consequently, the input node of the amplifying transistor13phas a potential after reset. Consequently, the amplifying transistor130of the pixel150in the first row outputs a signal based on the reset potential of the input node to the vertical signal line165. This signal is referred to as an N signal. The N signal is one of pixel signals output by the pixel150, and a noise signal output by the pixel150.

At time t2, which is in a period during which the pixel150outputs the N signal, the timing generator (not illustrated) makes the signal ARES transition from High to Low. Consequently, the N signal is clamped by the capacitor element190.

The amplifying circuit1100outputs an OFFSET signal, which is a signal at an offset level, from time t2. The signal is referred to as an offset signal. The OFFSET signal is a signal based on a noise signal, which is one of pixel signals. Since the timing generator (not illustrated) has made the signal SH transition to High, the capacitor element230samples the OFFSET signal.

Thereafter, at time t3, the timing generator (not illustrated) makes the signal SH transition to Low. Consequently, the capacitor element230holds the OFFSET signal.

The OFFSET signal held by the capacitor element230is input to the buffer240. The buffer240outputs a signal obtained by buffering the OFFSET signal to the comparator280through the capacitor element260.

At that time, the potential of the ramp signal RAMP is set to a ramp start potential.

Thereafter, at time t3to time t4, the ramp signal supply unit offsets the potential of the ramp signal RAMP.

At time t6, the timing generator (not illustrated) changes the signal CRES from High to Low. The capacitor element260clamps the OFFSET signal. In addition, the capacitor element270clamps the offset potential of the ramp signal RAMP.

The N-reading period is a period from when the pixel150starts outputting the N signal to when the ramp signal RAMP starts changing the potential, which will be described later.

Next, the NAD period will be described.

By time t8, the ramp signal supply unit (not illustrated) sets the potential of the ramp signal RAMP to the ramp start potential. The ramp signal supply unit starts changing the potential of the ramp signal RAMP at the time t8.

The counter320starts counting the clock signals in response to the start of the change in the potential of the ramp signal RAMP. In accordance therewith, counting-up of the count signals is started.

The comparator280outputs the signal V_COUT(m) which indicates a result of comparison between potentials of an inverting input node and a non-inverting input node.

When a magnitude relationship between the potentials of the inverting input node and the non-inverting input node of the comparator280is reversed at time t9, a value of the signal V_COUT(m) changes.

When the value of the signal V_COUT(m) changes, the latch310makes the signal LAT(m) transition to High, and then to Low.

The first memory330holds a count signal generated at timing when the signal LAT(m) has transitioned from High to Low. The count signal is a digital signal based on a noise component of the comparator280. The digital signal is referred to as a digital N signal. The digital N signal is a signal mainly including a component of variation between the comparators280in respective columns.

Thereafter, at time t11, the ramp signal supply unit (not illustrated) ends the change in the potential of the ramp signal RAMP. The counter320ends the counting of the clock signals. In accordance therewith, the counting-up of the count signals is ended.

The NAD period is a period from when the change in the potential of the ramp signal RAMP is started to when the change in the potential of the ramp signal RAMP is ended.

Thereafter, the timing generator makes the signal MREAD transition to High. Consequently, the second memory350holds the digital N signal held by the first memory330. Consequently, it becomes possible to load a next count signal into the first memory330.

In the operation in the comparative example inFIG. 2A, at least a part of the NAD period and a part of the S-reading period are overlapped. In an example described below, the entirety of the NAD period and a part of the S-reading period are overlapped.

The S-reading period will be described.

At time t7, the vertical scanning circuit170makes a signal PTX(1) transition to High. Accordingly, charge accumulated by a photodiode100is transferred to the amplifying transistor130. The amplifying transistor130outputs a signal based on the charge accumulated by the photodiode100to the vertical signal line165. This signal includes the N signal. This signal is referred to as an (S+N) signal. The (S+N) signal is one of the pixel signals output by the pixel150. In addition, the (S+N) signal is an optical signal based on charge, output from the pixel150.

At time t13, the timing generator (not illustrated) makes the signal VLON transition to High. The capacitor element190remains clamping the N signal. Therefore, an S signal, obtained by subtracting the N signal from the (S+N) signal is input to an input node of the amplifier180.

The amplifier180outputs a signal based on the S signal. This signal includes a signal obtained by amplifying the S signal and an OFFSET signal of the amplifier180. The signal based on the S signal is referred to as an (amplified S+OFFSET) signal.

At time t13, the timing generator (not illustrated) makes the signal SH transition to High. Consequently, the capacitor element230samples the (amplified S+OFFSET) signal. Thereafter, at time t15, the timing generator (not illustrated) makes the signal SH transition to Low. Consequently, the capacitor element230holds the (amplified S+OFFSET) signal.

The S-reading period is a period from when the pixel150starts outputting the (S+N) signal to when the ramp signal RAMP starts changing the potential, which will be described later.

Next, the SAD period will be described. During this period, the AD conversion unit1300converts the amplified S signal which is a signal based on the S signal to a digital signal.

At time t15, the capacitor element230holds the (amplified S+OFFSET) signal.

The (amplified S+OFFSET) signal held by the capacitor element230is input to the buffer240. The buffer240outputs a signal obtained by buffering the (amplified S+OFFSET) signal to the comparator280through the capacitor element260.

The capacitor element260continues clamping the OFFSET signal clamped in the previous NAD period. Therefore, the amplified S signal, obtained by subtracting the OFFSET signal from the (amplified S+OFFSET) signal, is input to the inverting input node of the comparator280.

In addition, the capacitor element270is clamping the initial potential of the ramp signal RAMP clamped in the previous NAD period.

At time t15, the ramp signal supply unit starts changing the potential of the ramp signal RAMP.

The counter320starts counting the clock signals in response to the start of the change in the potential of the ramp signal RAMP. In accordance therewith, counting-up of the count signals is started.

The comparator280outputs the signal V_COUT(m) which indicates a result of comparison between potentials of the inverting input node and the non-inverting input node.

When a magnitude relationship between the potentials of the inverting input node and the non-inverting input node of the comparator280is reversed at time t16, a value of the signal V_COUT(m) changes.

When the value of the signal V_COUT(m) changes, the latch310makes the signal LAT(m) transition to High, and then to Low at time t17.

The first memory330holds a count signal generated at timing when the signal LAT(m) transitions from High to Low. The count signal is a digital signal based on the amplified S signal. The digital signal is referred to as a digital S signal.

At time t19, the ramp signal supply unit (not illustrated) ends the change in the potential of the ramp signal RAMP.

The SAD period is a period from when the change in the potential of the ramp signal RAMP is started to when the change in the potential of the ramp signal RAMP is ended.

Thereafter, at time t21, the timing generator (not illustrated) makes the signal MREAD transition to High. Consequently, the second memory350holds the digital S signal held by the first memory330. Consequently, it becomes possible to load a next count signal into the first memory330.

Thereafter, the horizontal scanning circuit360sequentially scans the second memories350of respective columns, thereby reading the digital S signals and the digital N signals from the second memories350of respective columns, to the output unit370.

In the operation in the comparative example inFIG. 2A, a part of the SAD period and a part of the N-reading period of the pixel150in the next row are overlapped.

In the operation in the comparative example, driving is performed such that the switch220is turned off in order for the capacitor element230to hold the (amplified S+OFFSET) signal. There is a situation that a switching noise, which is generated by the switch220turned from on to off by the driving, is superimposed on the (amplified S+OFFSET) signal.

FIG. 2Billustrates driving of the embodiment.

A difference from the comparative example inFIG. 2Aresides in that the NAD period and the S-reading period are not overlapped. Another difference therefrom resides in that the SAD period and the N-reading period are not overlapped.

Regarding the N-reading period of the embodiment, driving thereof which is different from that of the N-reading period of the comparative example will be described.

FIG. 4illustrates details of the driving of the embodiment illustrated inFIG. 2B.

In the N-reading period of the comparative example, the capacitor element230holds the OFFSET signal by the timing generator (not illustrated) making the signal SH transition from High to Low. In the embodiment, the timing generator (not illustrated) keeps the signal SH High from time t0. Consequently, the OFFSET signal continues to be input from the amplifier180to the comparator280through the buffer240from when the amplifier180starts outputting the offset signal to when the NAD period ends. During this period, the capacitor element230remains sampling the OFFSET signal. In the period during which the capacitor element230samples the offset signal, the first memory330holds a digital signal based on the OFFSET signal. Other operations are the same as the operations for the N-reading period described for the comparative example.

The operation for the NAD period in the embodiment is the same as the operation for the NAD period in the comparative example.

In the embodiment, the S-reading period starts after the NAD period ends.

Regarding the S-reading period in the embodiment, an operation thereof which is different from that of the S-reading period in the comparative example will be described. In the S-reading period in the comparative example, the capacitor element230holds the (amplified S+OFFSET) signal by the timing generator (not illustrated) making the signal SH transition from High to Low. In the embodiment, the signal SH remains High since time t0. Consequently, the (amplified S+OFFSET) signal continues to be input from the amplifier180to the comparator280through the buffer240from when the amplifier180starts outputting the (amplified S+OFFSET) signal to when the SAD period ends. During this period, the capacitor element230remains sampling the (amplified S+OFFSET) signal. In the period during which the capacitor element230samples the (amplified S+OFFSET) signal, the first memory330holds a digital signal based on the (amplified S+OFFSET) signal. Other operations are the same as the operations for the S-reading period described for the comparative example.

The operation for the SAD period in the embodiment is the same as the operation for the SAD period in the comparative example.

In the embodiment, the N-reading period of the pixel150in the next row starts after the SAD period ends.

In the operation in the embodiment, the switch220is left turned on from the start of the output of the (amplified S+OFFSET) signal to the end of the SAD period. The switch220is used in order for the capacitor element230as a signal holding capacitor to hold a signal. Consequently, the capacitor element230remains sampling the (amplified S+OFFSET) signal. In the period during which the capacitor element230samples the (amplified S+OFFSET) signal based on an S signal of a first pixel, the first memory330holds a digital signal corresponding to an amplified S signal based on the S signal of the first pixel. Consequently, it is less likely to include the noise generated by the switching of the switch220in the (amplified S+OFFSET) signal.

Accordingly, with the image pickup apparatus of the embodiment, it is possible to improve a signal/noise (S/N) ratio of the signal based on the S signal output by the pixel150.

In addition, the switch220is left turned on from the start of the output of the offset signal to the end of the NAD period. The switch220is used in order for the capacitor element230as a signal holding capacitor to hold a signal. Consequently, the capacitor element230remains sampling the OFFSET signal. In the period during which the capacitor element230samples the OFFSET signal based on an N signal of the first pixel, the first memory330holds a digital signal corresponding to an OFFSET signal based on the N signal of the first pixel. Consequently, it is less likely to include the noise generated by the switching of the switch220in the OFFSET signal.

Accordingly, with the image pickup apparatus of the embodiment, it is possible to reduce the noise included in a signal based on the N signal output by the pixel150.

In the embodiment, an example has been described in which the capacitor element260and the capacitor element270perform a clamp operation prior to the NAD period. However, the operation is not essential. The AD conversion unit1300of the embodiment can be configured not to include the capacitor element260and the capacitor element270. In that case, the digital N signal and the digital S signal also include a component of the OFFSET signal of the amplifying circuit1100. Even in that case, the component of the offset signal of the amplifying circuit1100can be subtracted by subtracting the digital N signal from the digital S signal.

In the embodiment, the AD conversion performed by counting time from the start of the change in the potential of the ramp signal to the reversal of the magnitude relationship between the ramp signal and an analog signal has been described. The embodiment is not limited to the AD conversion method, and can be applied to other AD conversion methods such as those of a successive approximation type, a delta-sigma type, and a pipeline type.

In the embodiment, an example has been described in which the amplifying circuit1100is provided in each column. Another example will be described with reference toFIG. 5.

Respective signals illustrated inFIG. 5correspond to the signals illustrated in the timing chart inFIG. 4. In other words, also in the image pickup apparatus inFIG. 5, the signal SH remains High over the N-reading period, the NAD period, the S-reading period, and the SAD period.

The image pickup apparatus inFIG. 5has a configuration obtained by excluding the amplifying circuit1100from the image pickup apparatus illustrated inFIG. 1. Each of the N signal and the (S+N) signal output by the pixel150is output to the sampling and holding unit1200. The buffer240outputs a signal obtained by buffering each of the N signal and the (S+N) signal output from the pixel150to the AD conversion unit1300. The capacitor element260clamps the N signal. Consequently, a signal obtained by subtracting the N signal from the (S+N) signal is input to the inverting input node of the comparator280. The digital N signal has a component mainly including variation in characteristics between the comparators280in respective columns. The digital S signal is a signal based on the S signal.

Also in the example inFIG. 5, other AD conversion methods can be applied. In addition, the capacitor element260and the capacitor element270can be omitted.

In the embodiment, an example has been described in which the image pickup apparatus includes the AD conversion unit1300. There is no limitation to the example.FIG. 7illustrates an image pickup apparatus of another mode. The image pickup apparatus inFIG. 7includes a signal reading unit1500connected to an output node of the sampling and holding unit1200. The signal reading unit1500includes a switch500, a switch501, a capacitor element505, a capacitor element506, a switch510, and a switch511. The switch500and the switch501are controlled by a signal PTS and a signal PTN output from the timing generator (not illustrated). The switch510and the switch511are controlled by a signal CSEL(m) output from the horizontal scanning circuit360. The capacitor element505holds an OFFSET signal output by the buffer240. The capacitor element506holds an (amplified S+OFFSET) signal output by the buffer240.

An output unit380outputs, as output OUT, an amplified S signal obtained by subtracting an (amplified S+OFFSET) signal and an OFFSET signal output from the signal reading unit1500of each column.

The driving of the embodiment can be applied also in the configuration as described above. In other words, the capacitor element505or the capacitor element506as a signal holding unit may hold the signal in the period during which the capacitor element230samples the signal.

Second Embodiment

In the first embodiment, the driving ofFIG. 2Ahas been described as the comparative example. An image pickup apparatus of a second embodiment switches and performs the driving ofFIG. 2Aand the driving ofFIG. 2B.

FIG. 6illustrates the driving of the embodiment.

The image pickup apparatus performs reading for Live View, collectively resets charges of PDs in all rows, accumulates charge, and performs reading for a still image. In Live View, an image is generated which includes several tens of frames per second. One frame in Live View corresponds to one vertical scanning in the image pickup apparatus. The one vertical scanning corresponds to reading of signals from a pixel150in the first row to a pixel150in the last row.

In the reading for Live View, reading of signals is performed at a higher frame rate than that in the reading for a still image. In the reading for Live View, the driving illustrated inFIG. 2Ais performed.

On the other hand, in the reading for a still image, reading of signals with a high S/N ratio is performed. Accordingly, in the reading for a still image, the driving illustrated inFIG. 2Bis performed.

As described above, when high-speed reading is performed in the image pickup apparatus, the driving illustrated inFIG. 2Ais performed. On the other hand, when reading of signals with a high S/N ratio is performed in the image pickup apparatus, the driving illustrated inFIG. 2Bis performed. As described above, the image pickup apparatus of the embodiment has an effect which makes it possible to perform both the high-speed reading and the reading of signals with a high S/N ratio.

Third Embodiment

A third embodiment relates to an image pickup system including the image pickup apparatus of each embodiment described above.

Examples of the image pickup system include a digital still camera, a digital camcorder, and a monitoring camera.FIG. 8illustrates a schematic diagram of a digital still camera to which the image pickup apparatus is applied, as an example of the image pickup system.

The image pickup system illustrated inFIG. 8includes a barrier1501, a lens1502, and a diaphragm1503. The barrier1501is provided for protecting a lens. The lens1502makes the image pickup apparatus1504focus an optical image of an object. The diaphragm1503is provided for making an amount of light passing through the lens1502variable. The lens1502and the diaphragm1503constitute an optical system which concentrates light to the image pickup apparatus1504. In addition, the image pickup system illustrated inFIG. 8includes an output signal processing unit1505which performs a process of an output signal output from the image pickup apparatus1504. The output signal processing unit1505performs an operation to output a signal after performing various kinds of correction and compression as needed.

The image pickup system illustrated inFIG. 8further includes a buffer memory unit1506and an external interface unit1507. The buffer memory unit1506is provided for temporarily storing image data. The external interface unit1507is provided for communicating with an external computer or the like. The image pickup system further includes a recording medium1509capable of connecting thereto and disconnecting therefrom such as a semiconductor memory and a recording medium-controlling interface unit1508. The recording medium1509is provided for recording or reading image data. The recording medium-controlling interface unit1508is provided for performing recording or reading with respect to the recording medium1509. The image pickup system further includes an overall control/calculation unit1510and a timing supply unit1511. The overall control/calculation unit1510controls various calculations and the entire digital still camera. The timing supply unit1511outputs various timing signals to the image pickup apparatus1504and the output signal processing unit1505. Here, the timing signals and the like may be input from outside, and the image pickup system may include at least the image pickup apparatus1504and the output signal processing unit1505which processes an output signal output from the image pickup apparatus1504.

As described above, the image pickup system of the embodiment can perform an image-pickup operation by applying the image pickup apparatus1504.

Each of the embodiments described above is represented only as an exemplary embodiment for implementing the disclosure, and the technical scope of the disclosure should not be restrictively interpreted by the embodiments. In other words, the disclosure can be implemented in various forms without departing from the technical idea or the main feature thereof. In addition, the disclosure can be implemented by combining each of the embodiments described above in various ways.

The aspect of the embodiments makes it possible to reduce a noise of a signal held by a signal holding unit.

This application claims the benefit of Japanese Patent Application No. 2015-241382, filed Dec. 10, 2015, which is hereby incorporated by reference herein in its entirety.