Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed links

Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.

BACKGROUND

Description of the Related Art

Baseline wander is a common issue for any alternating current (AC) coupled serializer/deserializer (SerDes) link. It is noted that baseline wander is sometimes referred to as DC wander. Whenever a long string of 1's or 0's is transmitted on a signal path, the signal has energy in the low frequency part of the spectrum which is not effectively transmitted by the AC coupling capacitor. The rejected part of the signal creates low frequency noise which is especially harmful for multi-level signaling (e.g., pulse amplitude modulation 4-level (PAM4)) because of smaller eye separation. This is also an important issue for cases when the AC capacitor is placed on the semiconductor die as compared to on the circuit board. When the AC capacitor is on the die, it typically cannot be made too large as compared to when it is on the circuit board. The typical solution for baseline wander involves a feedback mechanism, where the effect of baseline wander is estimated and added back to the input as a correction. The feedback involves a finite amount of delay, which means the correction mechanism can never be perfect, leading to a non-zero impairment in the link budget due to baseline wander.

DETAILED DESCRIPTION OF IMPLEMENTATIONS

Various systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed herein. In one implementation, a receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. The combination of the receiver in parallel with the capacitor at the input adds a zero to the overall receiver transfer function and acts as a linear equalizer for low frequency signals. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. In one implementation, the current through the current sources is automatically adjusted by a common mode feedback op-amp. This op-amp has one input as the sensed common mode at the input pads (VCMPAD) and the other input as the desired common mode voltage reference (VCMREF). The current is continuously adjusted to maintain VCMPAD=VCMREFacross process, voltage, and temperature variation. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.

Referring now toFIG.1, a block diagram of one implementation of a generic computer or communication system100including a transmitter105and a receiver110is shown. In one implementation, transmitter105transmits data to receiver110over communication channel115. Communication channel115can include any number of individual connections (i.e., signal paths) between transmitter105and receiver110, with the number of connections varying according to the implementation. Also, the individual connections of communication channel115can support differential and/or single-ended signals. In one implementation, differential signals include two signals that are out of phase and equal in amplitude. For example, one signal of the differential signal may represent a positive signal while the other may represent a negative signal. A single-ended signal is one signal carrying data that transitions between two voltage levels, such as between ground (i.e., 0 Volts) and a supply voltage (i.e., VDD). Throughout this disclosure, many of the circuits are described in terms of supporting differential signals. However, one skilled in the art will understand that these circuits can also be adapted to support single-ended signals. Depending on the implementation, communication channel115is a cable, backplane, one or more metal traces, or other type of communication channel. For example, in one implementation, channel115is one or more metal traces between two chips of a multi-chip module. At the physical layer, the communication between the transmitter105and the receiver device110can be unidirectional or bidirectional according to a given transmission protocol. It is noted that system100can include any number and type of other devices. Additionally, system100can include any number of transmitter-receiver pairs dispersed throughout the system.

Transmitter105and receiver110can be any type of devices depending on the implementation. For example, in one implementation, transmitter105is a processing unit (e.g., central processing unit (CPU), graphics processing unit (GPU)) and receiver110is a memory device. The memory device can be any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of the SDRAMs such as mDDR3, etc., and/or low power versions of the SDRAMs such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static random access memory (SRAM), etc. One or more memory devices can be coupled onto a circuit board to form memory modules such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, the memory devices can be mounted within a system on chip (SoC) or integrated circuit (IC) in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module (MCM) configuration.

In another implementation, transmitter105is an input/output (I/O) fabric and receiver110is a peripheral device. The peripheral devices can include devices for various types of wireless communication, such as Wi-Fi, Bluetooth®, cellular, Global Positioning System (GPS), etc. The peripheral devices can also include additional storage, including random access memory (RAM) storage, solid state storage, or disk storage. The peripheral devices can also include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc. In other implementations, transmitter105and receiver110are other types of devices. It is noted that system100can be any type of system, such as an IC, SoC, MCM, and so on.

Turning now toFIG.2, a block diagram of one implementation of a computing system200is shown. As shown, system200represents chip, circuitry, components, etc., of a desktop computer210, laptop computer220, server230, mobile device240, or otherwise. Other systems, apparatuses, and devices (e.g., game consoles, wearable devices, Internet of things (IoT) devices, peripheral devices) are possible and are contemplated. In the illustrated implementation, the system200includes any number of pairs of transmitters202A-N and receivers203A-N.

Referring now toFIG.3, a block diagram of one implementation of a receiver300is shown. In one implementation, receiver110(ofFIG.1) includes one or more instances of the components of receiver300. Input signal305is received on interface310by receiver circuit315. In one implementation, input signal305is a differential signal and interface310includes two separate physical connections. In another implementation, input signal305is a single-ended signal and interface310includes one physical connection.

In one implementation, receiver circuit315achieves three different goals for input signal305received on interface310before passing the conditioned signal to interface320. In this implementation, receiver circuit315prevents baseline wander (i.e., DC wander), performs DC level shifting, and achieves linear equalization for input signal305. Examples of different ways of implementing receiver circuit315will be provided throughout the remainder of this disclosure. After being coupled to interface320, the output signal from receiver315is provided to receiver front-end325. The receiver front-end325can prepare the signal for being sampled to extract data carried by the signal.

Turning now toFIG.4, a block diagram of one implementation of a receiver circuit400is shown. In one implementation, receiver circuit315includes the components and structure shown for receiver circuit400. In one implementation, a differential input data signal is received by receiver circuit400on channels405A-B. For example, in one implementation the positive signal of the differential signal is received by405A and the negative signal of the differential signal is received by405B. Two current sources410A and410C are coupled to pad405A, with a first leg of current source410A coupled to a voltage supply and a second leg of current source410A coupled to pad405A, and with a first leg of current source410C coupled to pad405A and a second leg of current source410C coupled to ground. Similarly, two current sources430A and430C are coupled to pad405B, with a first leg of current source430A coupled to a voltage supply and a second leg of current source430A coupled to pad405B, and with a first leg of current source430C coupled to pad405B and a second leg of current source430C coupled to ground.

Receiver pad405A is coupled to a first leg of resistor415and a first leg of capacitor420, with resistor415and capacitor420arranged in a parallel fashion. It is noted that receiver pad405A can also be referred to as first differential signal line input405A. It is also noted that the line extending from receiver pad405A can also be referred to as transmission line405A, signal path405A, or signal line405A. A second leg of resistor415and a second leg of capacitor420are coupled to receiver front end signal line input465A. It is noted that the line extending from receiver front end signal line input405A can also be referred to as transmission line465A, signal path465A, or signal line465A. Also, two current sources410B and410D are coupled to signal line input465A, with a first leg of current source410B coupled to a voltage supply and a second leg of current source410B coupled to signal line input465A, and with a first leg of current source410D coupled to signal line input465A and a second leg of current source410D coupled to ground.

Similarly, receiver pad405B is coupled to a first leg of resistor435and a first leg of capacitor440, with resistor435and capacitor440arranged in a parallel fashion. A second leg of resistor435and a second leg of capacitor440are coupled to receiver front end signal line input465B. Also, two current sources430B and430D are coupled to signal line input465B, with a first leg of current source430B coupled to a voltage supply and a second leg of current source430B coupled to signal line input465B, and with a first leg of current source430D coupled to signal line input465B and a second leg of current source430D coupled to ground.

A pair of resistors455and460arranged in a serial fashion are coupled between receiver front end signal line input465A and receiver front end signal line input465B. The midpoint of resistors455and460is coupled to a first input of op-amp450, and a reference voltage is coupled to a second input of op-amp450. The output of op-amp450is coupled to current sources410A-D and430A-D. Op-amp450controls the flow of current through current sources410A-D and430A-D to achieve the proper DC level on signal line inputs465A-B to match what is expected by the subsequent circuit (e.g., receiver front-end circuit).

Receiver circuit400is able to prevent baseline wander, shift a DC level of an input signal, and achieve linear equalization. A typical SerDes link employs the use of a finite impulse response (FIR) filter at the transmitter to attenuate low frequency components of the data signal with respect to high frequency components. This leads to a flatter response at the receiver end of the channel. Additionally, a receiver may use a decision feedback equalizer (DFE) to cancel one or more previously transmitted bits of data. However, these techniques do not provide sufficient attenuation for lower frequency components (lower than 1/20thof the Nyquist frequency). This results in a residual intersymbol interference (ISI) when long strings of 1's or 0's are transmitted through the channel. However, the receiver circuit400presented inFIG.4repurposes the circuit used for avoiding baseline wander to act as a linear equalizer at lower frequencies. This is achieved by the addition of a low frequency zero (e.g., at ˜800 Mhz for 16 GHz Nyquist frequency).

It should be understood that receiver circuit400is merely one example of a receiver circuit for preventing baseline wander, shifting a DC level of an input signal, and achieving linear equalization. In other implementations, other combinations of components and/or other suitable structures of a receiver circuit can be employed. In other words, it should be understood that variations to the arrangements of components shown for receiver circuit400can be employed in other implementations. Two examples of variations are presented for receiver circuit500(ofFIG.5) and receiver circuit700(ofFIG.7) and are described in further detail below.

Referring now toFIG.5, a block diagram of another implementation of a receiver circuit500is shown. Receiver circuit500is a variation on the structure of receiver circuit400shown inFIG.4. In a scenario where the voltage difference between the transmitter and receiver is known and the common mode voltage at the input pads505A-B is lower than the common mode voltage at receiver front end input pads565A-B, two of the current sources can be omitted from the input and output channels. Accordingly, input signal path505A is connected to current source510C which acts as a current sink, and output signal path565A is connected to current source510B which supplies current which flows through resistor515to current source510C. Similarly, input signal path505B is connected to current source530C which acts as a current sink, and output signal path565B is connected to current source530B which supplies current which flows through resistor535to current source530C. The other components of receiver circuit500are similar to receiver circuit400.

Turning now toFIG.6, a block diagram of one implementation of current source circuitry600is shown. In one embodiment, current sources510B and510C (ofFIG.5) are implemented using the components and structure of circuitry600. The signal labeled “Opamp out” refers to the control signal generated by the op-amp (e.g., op-amp550). Also, the signal labeled “Vin,p” corresponds to signal path505A and the signal labeled “Vout,p” corresponds to signal path565A. As shown inFIG.6, P-type transistors605and610are coupled in series between the supply voltage and “Vout,p”. P-type transistors615and620are coupled in series between the supply voltage and the drain of N-type transistor625. The gates of N-type transistor625and N-type transistor630are coupled together, with the source ports of N-type transistors625and630tied to ground, and the drain port of N-type transistor630tied to “Vin,p”. Also, the source ports of P-type transistors635and640are tied to the supply voltage, and the drain ports of P-type transistors635and640are tied to the drain ports of N-type transistors645and650, respectively. The gates of N-type transistors645and650are tied together and to the drain port of N-type transistor650, and the source ports of N-type transistors645and650are tied to ground. The gates of P-type transistors635and610are tied together and labeled as “Vbias,p”. It is noted that the arrangement of transistors shown in circuitry600is merely one possible scheme for implementing current sources510B and510C and current sources530B and530C in accordance with one implementation. In other implementations, other suitable arrangements of circuitry can be used to construct current sources510B and510C and current sources530B and530C.

Turning now toFIG.7, a block diagram of another implementation of a receiver circuit700is shown. Receiver circuit700is a variation on the structure of receiver circuit400shown inFIG.4. In a scenario where the voltage difference between the transmitter and receiver is known and the common mode voltage at the input pads705A-B is higher than the common mode voltage at receiver front end input pads765A-B, two of the current sources can be omitted from the input and output signal paths. Accordingly, input signal path705A is connected to current source710A which supplies current through resistor715to current source710D, and output signal path765A is connected to current source710D which acts as a current sink. Similarly, input signal path705B is connected to current source730A which supplies current through resistor735to current source730D, and output signal path765B is connected to current source730D which acts as a current sink. The other components of receiver circuit700are similar to receiver circuit400.

Turning now toFIG.8, a block diagram of one implementation of current source circuitry800is shown. In one embodiment, current sources710A and710D (ofFIG.7) are implemented using the components and structure of circuitry800. The signal labeled “Vin,p” corresponds to signal path705A and the signal labeled “Vout,p” corresponds to signal path765A. As shown inFIG.8, the source ports of P-type transistors805and810are connected to the supply voltage, with the gates of P-type transistors805and810connected together and to the drain port of P-type transistor805. The drain port of P-type transistor810is coupled to the signal labeled “Vin,p”. The signal labeled “Vout,p” is connected to the drain port of N-type transistor830, with the gate of N-type transistor830connected to the gates of N-type transistors820and825and labeled as “Vbias,n”. The drain port of N-type transistor825is connected to the drain port of P-type transistor805. Current source815is connected in between the supply voltage and the drain port of N-type transistor820. The source ports of N-type transistors820,825, and830are connected to ground. It is noted that the arrangement of transistors shown in circuitry800is merely one possible scheme for implementing current sources710A and710D and current sources730A and730D in accordance with one implementation. In other implementations, other suitable arrangements of circuitry can be used to construct current sources710A and710D and current sources730A and730D.

Referring now toFIG.9, one implementation of a method900for employing a combination scheme for direct current level shifting of signals is shown. For purposes of discussion, the steps in this implementation and those ofFIG.10-12are shown in sequential order. However, it is noted that in various implementations of the described methods, one or more of the elements described are performed concurrently, in a different order than shown, or are omitted entirely. Other additional elements are also performed as desired. Any of the various systems or apparatuses described herein are configured to implement method900(and methods1000-1200).

A first circuit receives an input signal on a first interface (block905). The input signal can be one side (e.g., either positive or negative) of a differential signal or a single-ended signal, depending on the implementation. It is noted that the first interface can also be referred to as a first signal path, a first signal line, a first pad, a first node, or a first transmission line. The input signal passes through a parallel combination of a resistor and capacitor to a second interface (block910). The resistor provides a feed-forward path for low frequency components. A plurality of current sources, coupled to the first and second interfaces, adjust a direct current (DC) level of the first input signal based on a difference between a current mode voltage and a reference voltage (block915). The plurality of first current sources can include four current sources or eight current sources, depending on the implementation. The input signal is provided to a second circuit via the second interface (block920). In one implementation, the second circuit is a receiver front-end circuit. After block920, method900ends.

Turning now toFIG.10, one implementation of a method1000for preventing baseline wander, performing DC level adjustment, and achieving linear equalization is shown. A plurality of current sources of a receiver circuit convert a direct current (DC) level of an input signal on a first interface to a desired reference voltage of an output signal on a second interface (block1005). A feed-forward resistor, in parallel with an alternating current (AC) capacitor, provides a feed-forward resistor path for low frequency signal components so as to prevent baseline wander of the input signal (block1010). Also, the feed-forward resistor in parallel with the AC capacitor performs linear equalization of the input signal so as to attenuate low frequency signal components of the input signal with respect to high frequency signal components (block1015). After block1015, method1000ends. As a result of performing method1000, the input signal is passed from the first interface to the second interface while achieving three goals of preventing baseline wander, adjusting the DC level, and undergoing linear equalization.

Referring now toFIG.11, one implementation of a method1100for receiving and conditioning a differential data signal is shown. A receiver circuit receives a differential input signal on first and second signal paths (block1105). It is noted that the first signal path can be a wire, a trace, or other physical connection medium, and the second signal path can be a wire, a trace, or other physical connection medium separate and distinct from the first channel. One or more first current sources provide (i.e., supply) current to or sink current from the first signal path (block1110). One or more second current sources provide current to or sink current from the second signal path (block1115).

One side of the differential input signal is passed, on the first signal path, through a first parallel arrangement of a resistor and a capacitor to a third signal path (block1120). One or more third current sources provide current to or sink current from the third signal path (block1125). Also, the other side of the differential input signal is passed, on the second signal path, through a second parallel arrangement of a resistor and a capacitor to a fourth signal path (block1130). One or more fourth current sources provide current to or sink current from the fourth signal path (block1135). An amplifier (e.g., op-amp) receives a sensed common mode voltage on a first leg and a reference voltage on a second leg to generate a control signal to drive the first, second, third, and fourth current sources (block1140). An output version of the input differential signal is provided on the third and fourth signal paths to a receiver front-end circuit (block1145). After block1145, method1100ends. By performing method1100, the output version of the differential signal avoids baseline wander, undergoes a DC level shift, and achieves linear equalization.

Turning now toFIG.12, one implementation of a method1200for generating a baseline wander corrected version of an input signal is shown. An apparatus receives an input signal on a first interface (block1205). In one implementation, the input signal is a differential signal. In another implementation, the input signal is a single-ended signal. In a further implementation, the input signal is one signal of a differential signal pair. A circuit connected to the first interface generates an output signal as a baseline wander corrected version of the input signal, where the circuit includes a receiver-capacitor parallel arrangement and one or more current sources connected to either end of the resistor-capacitor parallel arrangement (block1210). A second interface receives the output signal from the circuit and transfers the output signal to a receiver front-end circuit (block1215). After block1215, method1200ends. It is noted that in addition to generated a baseline wander corrected version of the input signal, the circuit can also shift a DC level of the input signal and perform linear equalization at relatively low frequencies.

Turning now toFIG.13, a block diagram illustrating one implementation of a non-transitory computer-readable storage medium1300that stores a circuit representation1305is shown. In one implementation, circuit fabrication system1310processes the circuit representation1305stored on non-transitory computer-readable storage medium1300and fabricates any number of integrated circuits1315A-N based on the circuit representation1305.

Non-transitory computer-readable storage medium1300can include any of various appropriate types of memory devices or storage devices. Medium1300can be an installation medium (e.g., a thumb drive, CD-ROM), a computer system memory or random access memory (e.g., DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM), a non-volatile memory (e.g., a Flash, magnetic media, a hard drive, optical storage), registers, or other types of memory elements. Medium1300can include other types of non-transitory memory as well or any combinations thereof. Medium1300can include two or more memory mediums which reside in different locations (e.g., in different computer systems that are connected over a network).

In various implementations, circuit representation1305is specified using any of various appropriate computer languages, including hardware description languages such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, etc. Circuit representation1305is usable by circuit fabrication system1310to fabricate at least a portion of one or more of integrated circuits1315A-N. The format of circuit representation1305is recognizable by at least one circuit fabrication system1310. In some implementations, circuit representation1305includes one or more cell libraries which specify the synthesis and/or layout of the integrated circuits1315A-N.

Circuit fabrication system1310includes any of various appropriate elements configured to fabricate integrated circuits. This can include, for example, elements for depositing semiconductor materials (e.g., on a wafer, which can include masking), removing materials, altering the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), etc. Circuit fabrication system1310can also perform testing of fabricated circuits for correct operation.

In various implementations, integrated circuits1315A-N operate according to a circuit design specified by circuit representation1305, which can include performing any of the functionality described herein. For example, integrated circuits1315A-N can include any of various elements shown in the circuits illustrated herein and/or multiple instances of the circuit illustrated herein. Furthermore, integrated circuits1315A-N can perform various functions described herein in conjunction with other components. For example, integrated circuits1315A-N can be coupled to voltage supply circuitry that is configured to provide a supply voltage (e.g., as opposed to including a voltage supply itself). Further, the functionality described herein can be performed by multiple connected integrated circuits.

As used herein, a phrase of the form “circuit representation that specifies a design of a circuit . . . ” does not imply that the circuit in question must be fabricated in order for the element to be met. Rather, this phrase indicates that the circuit representation describes a circuit that, upon being fabricated, will be configured to perform the indicated actions or will include the specified components.

It should be emphasized that the above-described implementations are only non-limiting examples of implementations. The implementations are applied for up-scaled, down-scaled, and non-scaled images. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.