Battery protecting circuit, method of controlling the same, and battery pack

A battery pack is disclosed. The battery pack has an analog front end which senses if a failure occurs in a microcontroller, and interrupts charging and discharging of the battery in response to the failure.

BACKGROUND

The disclosed technology relates to a battery protecting circuit, a method of controlling the same, and a battery pack.

2. Description of the Related Technology

With an increase in use of portable electronic devices, such as mobile phones, digital cameras, laptop computers, and the like, batteries for supplying power to operate such portable electronic devices have been developed.

Batteries are often provided as a battery pack including a battery cell and a protection circuit that controls charging and discharging of the battery cell. Batteries may be any of lithium ion (Li-ion) batteries, nickel-cadmium (Ni—Cd) batteries, or the like according to the type of a battery cell. The battery cell may be used as a rechargeable secondary battery.

Some batteries further include microcontrollers or other programmable processors which are used to control the operation of the battery such that the battery operates properly and is protected from excessive currents which can damage or destroy the battery. Batteries may, therefore, be susceptible to failure if the microcontroller malfunctions.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

One inventive aspect is a battery pack, which includes a battery cell, a terminal unit, and a switch configured to selectively connect the battery cell and the terminal unit. The battery pack also includes a microcontroller configured to generate commands, and an analog front end configured to receive the commands from the microcontroller and to control charging and discharging of the battery cell according to the commands. The analog front end includes a status input terminal configured to receive a status signal indicative of a status of the microcontroller, a failure determination processor configured to determine whether the microcontroller has experienced a failure based on the status signal and to generate a failure signal, and a switch controller configured to control the switch according to the failure signal.

Another inventive aspect is a method of controlling a battery pack, where the battery pack includes a battery cell, a terminal unit, and an analog front end in communication with a microcontroller. The method includes the analog front end receiving a status signal indicating a status of the microcontroller, the analog front end determining whether the microcontroller has experienced a failure, and the analog front end generating a control signal to disconnect the battery cell from the terminal unit if the microcontroller has experienced a failure.

DETAILED DESCRIPTION OF CERTAIN INVENTIVE EMBODIMENTS

Certain embodiments are described more fully with reference to the accompanying drawings, in which various inventive aspects and features are shown. In the following description, various features are described, and a detailed description of certain other features are not provided to not obscure the inventive subject matter. Unless otherwise defined, terms used herein have the meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG. 1is a block diagram of a battery pack1according to an embodiment.

Referring toFIG. 1, the battery pack1includes a battery protection circuit100(hereinafter, a ‘protection circuit’) and a battery cell200.

The battery cell200includes at least one bare cell. The battery cell is connected to the protection circuit100. Charging or discharging occurs when an external device is connected to a terminal unit110of the protection circuit100. The battery cell200may be a rechargeable secondary battery.

The protection circuit100controls charging and discharging of the battery cell200, and senses an abnormal condition of the battery cell200to prevent damage to the battery cell200. The protection circuit100includes the terminal unit110, an analog front-end120, a microcontroller or processor130, a status indicator circuit140, a charging/discharging switch150, and a protection device160.

The terminal unit110is connected to a charging device for charging the battery cell200or an external device. The external device may be a load consuming electric energy stored in the battery cell200. The terminal unit110includes a positive terminal111and a negative terminal112. If the charging device is connected to the terminal unit110, charging may occur in the battery pack1. While charging, current flows into the battery pack1via the positive terminal111and flows out of the battery pack1via the negative terminal112. If the external device is connected to the terminal unit110, discharging may occur in the battery pack1. While discharging, current flows out of the battery pack1via the positive terminal111and flows into the battery pack1via the negative terminal.

The analog front-end120controls charging and discharging of the battery cell200. The analog front-end120senses a charge/discharge status of the battery cell200, such as an internal current flow status of the battery pack1, the temperature of the battery pack1, and the like. The analog front-end120transmits the sensed data as sensed data Sdata to the microcontroller130. Although inFIG. 1the sensed data Sdata are denoted with a single arrow, the sensed data Sdata may include a plurality of data and may be conveyed over a plurality of data lines. For example, the sensed data Sdata may include temperature data, voltage data, current data, and the like. In addition, the data may be transmitted to the microcontroller130through separate signal transfer lines, respectively.

The analog front-end120operates using a voltage of the battery cell200. The analog front-end120includes a regulator121to generate a power voltage Vreg and to apply the power voltage Vreg to the microcontroller130.

The analog front-end120receives a command signal Scom from the microcontroller130, and applies a charge control signal Sc or a discharge control signal Sd to the charging/discharging switch150according to the command signal Scom to control an On/Off state of the charging/discharging switch150.

The analog front-end120may include a failure determination processor123and a switch controller124. The failure determination processor123receives a signal output from the status indicator circuit140via a status input terminal P1, and determines that the microcontroller130is malfunctioning, if the magnitude of the received signal falls within predetermined conditions. For example, the failure determination processor123may determine that the microcontroller130is malfunctioning, if the magnitude of the received signal is smaller or equal to that of a reference voltage Vref. Alternatively, the failure determination processor123may determine that the microcontroller130is malfunctioning, when the received signal changes from a logic high to a logic low or vice versa. If the failure determination processor123determines that the microcontroller130is malfunctioning, the switch controller124transmits the charge control signal Sc or the discharge control signal Sd to the charging/discharging switch150to turn off the charging/discharging switch150.

The microcontroller130receives the power voltage Vreg from the analog front-end120as a power source. The microcontroller130receives the sensed data Sdata from the analog front-end120, and transmits the command signal Scom to the analog front-end120according to the sensed data Sdata to control the operation of the analog front-end120. For example, if there is a voltage variation among individual bare cells of the battery cell200, the microcontroller130may control the analog front-end120to control a cell balancing operation in order for the bare cells to have a constant voltage. As another example, if the battery cell200has an over-charge or over-discharge status, the microcontroller130may execute control to stop a charge or discharge operation of the battery cell200. Although inFIG. 1the command signal Scorn is denoted with a single arrow, for convenience of explanation, the command signal Scorn may include a plurality of commands. In some embodiments, the plurality of command signals may be transmitted to the analog front-end120through separate signal transfer lines.

In some embodiments, if the analog front-end120is malfunctioning, the microcontroller130senses that the analog front-end120is malfunctioning and to protect the battery pack, controls the protection device160to stop a charge or discharge operation of the battery cell200. In some embodiments, the protection device160does not require external control and operates autonomously.

The microcontroller130outputs an operation status signal Sos to the status indicator circuit140via a terminal P2for the analog front-end120to sense a failure or a malfunction of the microcontroller130. For example, if the microcontroller130is in a normal condition, a logic high signal may be output as the operation status signal Sos. Alternatively, if the microcontroller130is in a normal condition, a continuous series of pulses may be output as the operation status signal Sos.

The status indicator circuit140receives the operation status signal Sos and generates a status signal for the analog front-end120. The status indicator circuit140outputs status signals to the analog front end120indicating whether the microcontroller130is in a normal condition or in an abnormal condition, so that the failure determination processor123of the analog front-end120can sense the status signals.

The charging/discharging switch150includes a charge control switch151and a discharge control switch152. Each of the charge control switch151and the discharge control switch152may include a field effect transistor (FET) and a parasitic diode. For example, the charge control switch151includes a field effect transistor FET11and a parasitic diode D11. The discharge control switch152includes a field effect transistor FET12and a parasitic diode D12. The direction in which a source and a drain of the field effect transistor FET1of the charge control switch151are connected is opposite to the direction in which those of the field effect transistor FET2of the discharge control switch device152are connected. In other words, in this embodiment, the field effect transistor FET11of the charge control switch151is connected so as to restrict the flow of current between the positive terminal111and the battery cell200. On the other hand, the field effect transistor FET12of the discharge control switch152is connected so as to restrict the flow of current between the battery cell200and the positive terminal111. In this regard, the field effect transistor FET11of the charge control switch151and the field effect transistor FET12of the discharge control switch152are switching devices. However, the field effect transistors FET11and FET12are not limited thereto and may be any electric device with a switching function. The parasitic diode D11of the charge control switch151and the parasitic diode D12of the discharge control switch152may be arranged in such a way that currents flow therethrough in directions opposite to directions in which the field effect transistors FETs11and12respectively restrict flow of current.

The protection device160is arranged in a high current path (HCP) to control the flow of current out of the battery cell200or the flow of current into the battery cell200. The protection device160operates when the analog front-end120experiences a failure. The protection device160may be a fuse or a positive temperature coefficient (PTC) thermistor. Alternatively, the protection device160may be a device that may autonomously operate according to a flow of current therethrough. Alternatively, the protection device160may be a device that may operate under the control of the microcontroller130.

Hereinafter, the status indicator circuit140is described in greater detail.

FIGS. 2 and 3are circuit diagrams of embodiments of the status indicator circuit140ofFIG. 1, respectively.

Referring toFIG. 2, the status indicator circuit140may be a signal line directly connecting the terminal P2of the microcontroller130and the status input terminal P1of the analog front-end120. in some embodiments, if in a normal condition, the microcontroller130outputs a logic high signal as the operation status signal Sos. The analog front-end120may determine that the microcontroller130is having a failure, if the failure determination processor123determines that the level of the operation status signal Sos received via the status input terminal P1and the status indicator circuit140is smaller or equal to the level of the reference voltage Vref. The reference voltage Vref may have a level that is predetermined when manufacturing the battery pack1.

Referring toFIG. 3, in some embodiments, the status indicator circuit140comprises a level shifter circuit including a plurality of resistors R31and R32, and a switching device SW1. The resistor R31is connected between the status input terminal P1and a voltage source of a first voltage Vcc. The resistor R32is connected between the status input terminal P1and a first electrode of the switching device SW1. A second electrode of the switching device SW1is connected to ground. A gate electrode of the switching device SW1is connected to the terminal P2. The switching device SW1may be a p-channel field effect transistor (FET).

Under normal conditions, the microcontroller130outputs a logic high signal as the operation status signal Sos. Accordingly, the switching device SW1of the status indicator circuit140is turned off by the operation status signal Sos, so that the first voltage Vcc is applied to the status input terminal P1. The first voltage Vcc has a level greater than the reference voltage Vref. The failure determination processor123determines that the first voltage Vcc received through the status input terminal P1has a level greater than the reference voltage Vref, and the analog front-end120determines that the microcontroller130is in a normal condition.

On the other hand, if a failure or malfunction condition occurs, the microcontroller130outputs a logic low signal as the operation status signal Sos or stops outputting the operation status signal Sos. As a result, the switching device SW1of the status indicator circuit140is turned on by the operation status signal Sos, so that a voltage divided from the first voltage Vcc by the resistors R31and R32is applied to the status input terminal P1. For example, the voltage applied to the status input terminal P1may be approximated as Vcc*R32/(R31+R32). In this regard, the resistors R31and R32may be designed in such a way that the voltage has a level less than the reference voltage Vref. Accordingly, the failure determination processor123determines that the output signal of the status indicator circuit140received through the status input terminal P1has a level less than the reference voltage Vref, and the analog front-end120determines that the microcontroller130has failed.

FIG. 4is a circuit diagram of an embodiment of the status indicator circuit140ofFIG. 1.

Referring toFIG. 4, the status indicator circuit140according to the embodiment ofFIG. 4comprises an inverting level shifter circuit including a plurality of resistors R41and R42, and a switching device SW2. The resistor R41is connected between the status input terminal P1and a voltage source of a first voltage Vcc. The resistor R42is connected between the status input terminal P1and a first electrode of the switching device SW2. A second electrode of the switching device SW2is connected to ground. A gate electrode of the switching device SW2is connected to the terminal P2. The switching device SW2may be an n-channel field effect transistor (FET).

In a normal condition, the microcontroller130outputs a logic high signal as the operation status signal Sos. As a result, the switching device SW2of the status indicator circuit140is turned on by the operation status signal Sos, so that a voltage divided from the first voltage Vcc by the resistors R41and R42is applied to the status input terminal P1. For example, the partial voltage applied to the status input terminal P1may be approximated as Vcc*R42/(R41+R42). In this regard, the resistors R41and R42may be designed such that the voltage has a level less than the reference voltage Vref. The failure determination processor123determines that the output signal of the status indicator circuit140received through the status input terminal P1is less than the reference voltage Vref, and the analog front-end120determines that the microcontroller130is in a normal condition.

On the other hand, if a failure or malfunction condition occurs, the microcontroller130outputs a logic low signal as the operation status signal Sos or stops outputting the operation status signal Sos. As a result, the switching device SW2of the status indicator circuit140is turned off by the operation status signal Sos, so that the first voltage Vcc is applied to the status input terminal P1. The first voltage Vcc has a level greater than the reference voltage Vref. The failure determination processor123determines that the first voltage Vcc received through the status input terminal P1has a level greater than the reference voltage Vref, and the analog front-end120determines that the microcontroller130has failed.

The status indicator circuit140ofFIG. 4operates with an opposite polarity as the status indicator circuit140described above with reference toFIG. 3.

FIG. 5is a circuit diagram of another embodiment of the status indicator circuit140ofFIG. 1. Referring toFIG. 5, the status indicator circuit140according to the embodiment ofFIG. 5includes a plurality of resistors R51and R52, a plurality of capacitors C51and C52, and a plurality of diodes D51and D52.

In this embodiment, diode D51, the capacitor C51and the resistor R51are connected in series between the terminals P1and P2. A cathode of the diode D51is connected to the status input terminal P1, and an anode of the diode D51is connected to the capacitor C51to prevent a reverse flow of current from the status input terminal P1to the terminal P2. The capacitor C51removes an offset component from the operation status signal Sos output through the terminal P2.

The capacitor C52and the resistor R52are connected in parallel between the status input terminal P1and ground. A cathode of the diode D52is connected to the anode of the diode D51, and an anode of the diode D52is connected to ground.

In a normal condition, the microcontroller130may output, for example, a pulse signal at a repeated constant interval as the operation status signal Sos. As the operation status signal Soc is applied to the status indicator circuit140, charge is accumulated in the capacitor C52, and a voltage across the capacitor C52is applied to the status input terminal P1. The failure determination processor123has a voltage comparison unit122, which compares the voltage across the capacitor C52and the reference voltage Vref, and determines that the microcontrollers130is in a normal condition if the voltage across the capacitor C52has a level greater than the reference voltage Vref. The magnitude of the voltage across the capacitor C52is determined according to the duty ratio of the operation status signal Sos. The microcontroller130controls the duty ratio of the operation status signal Sos so that the voltage across the capacitor C52has a level greater than the reference voltage Vref if the microcontroller130is in a normal condition.

On the other hand, if a failure or malfunction condition occurs, the microcontroller130may output a logic low signal or a DC signal as the operation status signal Sos or stops outputting the operation status signal Sos. As a result, charge in the capacitor C52flow to ground through the resistor R52, and the voltage across the capacitor C52decreases to a level less than the reference voltage Vref, and the analog front-end120determines that the microcontroller130has failed.

FIG. 6illustrates a timing diagram of input and output signals of the status indicator circuit140ofFIG. 5, according to an embodiment,

Referring toFIG. 6, a voltage having a level that is greater than or equal to the reference voltage Vref is output to the status input terminal P1while a pulse signal is received from the terminal P2. Thus, the analog front-end120determines that the microcontroller130is in a normal condition. However, if the pulse signal is no longer received after a time t1, the capacitor C52begins to discharge and the voltage across the capacitor C52decreases and reaches a level that is less than the reference voltage at a time t2. Thus, the analog front-end120may determine starting from the time t2that the microcontroller130has failed.

The reference voltage Vref and the components of the status indicator circuit140may be designed so that an interval between the time t1and the time t2is greater than the width of a logic low period of the pulse signal output from the terminal P2. This may be beneficial because if the width of the logic low period of the pulse signal output from the terminal P2is greater than the interval between the time t1and the time t2, the voltage across the capacitor C52may have a level less than the reference voltage Vref while the pulse signal output from the terminal P2is at a logic low, leading to an erroneous determination that the microcontroller130is having a failure.

As described above, according to the battery protection circuit100ofFIG. 1, the analog front-end120may stop a charging and discharging operation of the battery pack1if a failure or malfunctioning of the microcontroller120is sensed. Thus, the operation of the battery pack1may be stably controlled.

FIG. 7illustrates a block diagram of a battery pack2according to another embodiment. The battery pack2according to the current embodiment has a similar structure and function to those of the battery pack1ofFIG. 1.

Referring toFIG. 7, the battery pack2includes a protection circuit300and a battery cell400. The protection circuit300includes a terminal unit310, an analog front-end320, a microcontroller330, a status indicator circuit340, a charging/discharging switch350, and a protection device360.

In the current embodiment, the failure determination processor323includes a timer322. The timer322receives the operation status signal Sos from the status indicator circuit340via the status indicator circuit340and the status input terminal P1, and the analog front-end circuit320determines that the microcontroller330is malfunctioning if the operation status signal Sos is not received for a reference time duration Δt. Alternatively, the timer320may determine that the microcontroller330is malfunctioning, if a signal having a level greater than or equal to a reference voltage Vref is received or not received for a reference time duration Δt.

If the analog front-end320determines that the microcontroller130is malfunctioning, the analog front-end320transmits a charge control signal Sc or a discharge control signal Sd to the charging/discharging switch350to turn off the charging/discharging switch350.

An operation of the protection circuit300according to an embodiment is described.

FIG. 8illustrates a timing diagram of input and output signals of the status indicator circuit340. The status indicator circuit340may, for example, be any one of the circuits ofFIGS. 2 through 4.

For example, if the status indicator circuit340has a configuration as shown inFIG. 2, when the operation status signal Sos received from the terminal P2changes from a logic high to a logic low at a time t3, the status signal at the status input terminal P1changes from a logic high to a logic low at substantially the same time. The failure determination processor323uses timer322to measure a time duration from the time t3at which the signal received through the status input terminal P1changes from the logic high to the logic low, and determines that the microcontroller330has failed after the reference time duration Δt. The operating principles of the circuits ofFIGS. 3 and 4are substantially the same as the operation of the circuit ofFIG. 2, except for the level of the voltage applied to the status input terminal P1.

FIG. 9is a timing diagram of input and output signals of the status indicator circuit340, according to another embodiment. The status indicator circuit340may be the circuit ofFIG. 5.

In a normal condition, the microcontroller330outputs a pulse signal at an interval as the operation status signal Sos. As the operation status signal Soc is applied to the status indicator circuit340, charge is accumulated in the capacitor C52, and a voltage across the capacitor C52is applied as the status signal to the status input terminal P1. The failure determination processor323uses timer322to determine that the microcontroller330is in a normal condition if a status signal having a level is continuously applied to the status input terminal P1.

On the other hand, if a failure or malfunction condition occurs, the microcontroller330may output a logic low signal as the operation status signal Sos or stops outputting the operation status signal Sos. Then, the capacitor C52begins to discharge, and the level of the voltage across the capacitor52is reduced to a level less than the level of the reference voltage Vref from a time t6. The failure determination processor323uses timer322to measure a time duration from the time t6, and determines that the microcontroller330is having a failure, if the time duration reaches the reference time duration (Δt).

The reference voltage Vref and the reference time duration Δt may be defined so that an interval between the time t5and the time t7is to be greater than the width of a logic low period of the pulse signal output from the terminal P2for the following reason. If the width of the logic low period of the pulse signal output from the terminal P2is greater than the interval between the time t5and the time t7, the voltage across the capacitor C52may have a level less than the reference voltage Vref and the reference time duration Δt may have lapsed while the pulse signal from the terminal P2is at a logic low, leading to an erroneous determination that the microcontroller330is having a failure.

As described above, in the battery protecting circuit300, the analog front-end320may stop charging and discharging of the battery pack2if a failure or malfunction of the microcontroller330is sensed. Thus, the operation of the battery pack2may be stably controlled.

FIG. 10illustrates a block diagram of a battery pack3according to another embodiment. The battery pack3has a similar structure and function to that of the battery pack1ofFIG. 1.

Referring toFIG. 10, the battery pack3includes a protection circuit500and a battery cell600. The protection circuit500includes a terminal unit510, an analog front-end520, a microcontroller or processor530, a charging/discharging switch560, and a protection device560.

The analog front-end520includes a failure determination processor522. The failure determination processor523receives a command signal Scom from the microcontroller530. The failure determination processor523may determine whether the microcontroller530has failed or is malfunctioning by comparing the voltage level of the command signal Scom with a reference voltage Vref. In addition, since the command signal Scom is used to determine the operation condition of the microcontroller530, the microcontroller530and the analog front-end520may have a reduced number of ports. The method in the failure determination processor523of determining whether the microcontroller530is having a failure or is malfunctioning may be similar to that described above with reference to other embodiments.

In some embodiments, the command signal Scom is monitored by the failure determination processor523and the status signal is encoded within the commands of the command signal Scorn. In some embodiments, the frequency of command generation is monitored to determine whether the microcontroller530is functioning properly, and if the frequency of command generation is below a threshold, the failure determination processor523determines that the microcontroller530has experienced a failure.

As described above, in the battery protecting circuit500according to the current embodiment, the analog front-end520may stop a charging and discharging operation of the battery pack3if a failure or malfunctioning of the microcontroller530is sensed. Thus, the operation of the battery pack3may be stably controlled.

FIG. 11illustrates a block diagram of a battery pack4according to another embodiment. The battery pack4has a similar structure and function to that of the battery pack3ofFIG. 10.

Referring toFIG. 11, the battery pack4includes a protection circuit700and a battery cell800. The protection circuit700includes a terminal unit710, an analog front-end720, a microcontroller730, a charging/discharging switch750, and a protection device760.

In the battery pack4, the failure determination processor723includes a timer722. The timer722receives a command signal Scom transmitted from the microcontroller or processor730. Using the timer722, the failure determination processor723determines whether the command signal Scom is transmitted, and determines that the microcontroller720is having a failure if the signal Scom does not indicate normal function for a reference time duration (Δt). Thus, in battery pack4, the protection circuit700may not include the status indicator circuit140ofFIG. 1. In addition, since the command signal Scom is used to determine the operation condition of the microcontroller730, the microcontroller730and the analog front-end720may have a reduced number of ports. The method of determining whether the microcontroller730is having a failure or is malfunctioning may be similar to that described above with reference to other embodiments.

As described above, in the battery protecting circuit700, the analog front-end720may stop charging and discharging of the battery pack4if a failure or malfunctioning of the microcontroller730is sensed. Thus, the operation of the battery pack4may be stably controlled.

Programs for executing the control methods according to the one or more embodiments of the present invention in the battery protecting circuits100,300,500, and700and the battery packs1through4may be stored in non-transitory computer readable media. The media may be semiconductor media, for example, flash memory. The media are readable and comprise instructions, which are executable by a processor. The methods may be performed by various modules. As can be appreciated by one of ordinary skill in the art, each of the modules may comprise various sub-routines, procedures, definitional statements, and macros. Each of the modules may be separately compiled and linked into a single executable program. Therefore, the following description of each of the method steps is used for convenience to describe the functionality of the methods. Thus, the processes that are undergone by each of the modules may be arbitrarily redistributed to one of the other modules, combined together in a single module, or made available in a shareable dynamic link library. Further each of the modules may be implemented in hardware as functional blocks.

Although systems and methods as disclosed, is embodied in the form of various discrete functional blocks, the system could equally well be embodied in an arrangement in which the functions of any one or more of those blocks or indeed, all of the functions thereof, are realized, for example, by one or more appropriately programmed processors or devices.

It is to be noted that the processor or processors may be a general purpose, or a special purpose processor, and may be for inclusion in a device, e.g., a chip that has other components that perform other functions. Thus, one or more aspects of the present invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Furthermore, aspects of the invention can be implemented in a computer program product stored in a computer-readable medium for execution by a programmable processor. Method steps of aspects of the invention may be performed by a programmable processor executing instructions to perform functions of those aspects of the invention, e.g., by operating on input data and generating output data. Accordingly, the embodiment includes a computer program product which provides the functionality of any of the methods described above when executed on a computing device. Further, the embodiment includes a data carrier such as for example a CD-ROM or a diskette which stores the computer product in a machine-readable form and which executes at least one of the methods described above when executed on a computing device.

While the above-detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the art without departing from the scope of the re as defined by the appended claims.

It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments.