Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure

Disclosed are embodiments of a semiconductor structure with fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer and, thus, allows the beta ratio in devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.

BACKGROUND

1. Field of the Invention

The embodiments of the invention generally relate to field effect transistors and, more particularly, to fin-type field effect transistors having different channel region heights and, thus, different effective channel widths.

2. Description of the Related Art

As transistor design is improved and evolves, the number of different types of transistors continues to increase. Multi-gate non-planar metal oxide semiconductor field effect transistors (FETs), including dual-gate non-planar FETs (e.g., finFETs) and tri-gate non-planar FETs, were developed to provide scaled devices with faster drive currents and reduced short channel effects over planar FETs.

Dual-gate non-planar FETs are FETs in which a channel region is formed in the center of a thin semiconductor fin. The source and drain regions are formed in the opposing ends of the fin on either side of the channel region. Gates are formed on each side of the thin semiconductor fin, and in some cases, on the top or bottom of the fin as well, in an area corresponding to the channel region. FinFETs are a type of dual-gate non-planar FETs in which the fin is so thin as to be fully depleted. The effective fin width is determined by the fin height (e.g., wide fins can cause partial depletion of a channel). For a finFET, a fin thickness of approximately two-third the length of the gate (or less) can ensure suppression of deleterious short-channel effects, such as variability in threshold voltage and excessive drain leakage currents. FinFETs are discussed at length in U.S. Pat. No. 6,413,802 to Hu et al., which is incorporated herein by reference

Tri-gate non-planar FETs have a similar structure to that of dual-gate non-planar FETs; however, the fin width and height are approximately the same so that gates can be formed on three sides of the channel, including the top surface and the opposing sidewalls. The height to width ratio is generally in the range of 3:2 to 2:3 so that the channel will remain fully depleted and the three-dimensional field effects of a tri-gate FET will give greater drive current and improved short-channel characteristics over a planar transistor. For a detail discussion of the structural differences between dual-gate and tri-gate FETs see “Dual-gate (finFET) and Tri-Gate MOSFETs: Simulation and Design” by A Breed and K. P. Roenker, Semiconductor Device Research Symposium, 2003, pages 150-151, December 2003 (incorporated herein by reference).

Recently, static random access memory (SRAM) cells (e.g., 6T-SRAM cells having two pass-gate transistors, two pull-up transistors and two pull-down transistors) have incorporated such multi-gate non-planar FETs. SRAM cells are typically designed with stronger pull-down strength, where the width ratio of pull-down (drive) FETs to pass-gate (load) FETs (i.e., the beta ratio) is greater than approximately two. One method of achieving such a beta ratio (i.e. a greater effective channel width in the pull-down transistors as compared to the pass-gate transistors) in an SRAM cell is by incorporating multiple fins into the pull-down FETs and/or pass-gate FETs (e.g., to achieve a ratio of 2:1). However, due to the conventional lithographic techniques used to pattern semiconductor fins, it may be difficult to fit the multiple fins required within the allotted space. Additionally, frequency doubling of fin pitch is not easily achieved using current state of the art lithographic technology, and thus, multi-gate non-planar FET SRAM cells may be compromised for either density or performance.

Therefore, there is a need in the art for an improved semiconductor structure and an associated method of forming the structure that allows a greater effective channel width to be achieved in one multi-gate non-planar transistor as compared to another on the same wafer.

SUMMARY

In view of the foregoing, disclosed herein are embodiments of an improved semiconductor structure that comprises semiconductor fins with different channel region heights on the same wafer. These fins with different channel region heights allow different multi-gate non-planar field effect transistors with different effective channel widths to be formed on the same wafer and, thus, optionally, to be incorporated into the same device (e.g., a single static random access memory (SRAM) cell).

An embodiment of the semiconductor structure comprises first and second fins on an isolation layer. These fins have approximately equal overall heights. Each fin comprises a semiconductor layer adjacent to the isolation layer and at least one additional layer above the semiconductor layer. However, the height of the semiconductor layer of the first fin is less than the height of the semiconductor layer of the second fin. Specifically, in the first fin, the semiconductor layer comprises a single layer of semiconductor material (e.g., silicon) above the isolation layer. In the second fin, the semiconductor layer comprises multiple layers of semiconductor materials (e.g., a silicon layer, a silicon germanium layer, another silicon layer, etc.).

Additionally, depending upon whether the fins will be incorporated into tri-gate or dual-gate non-planar FETs, the composition of the additional layers will vary. For example, for tri-gate FETs, the additional layers can comprise a dielectric layer adjacent to the semiconductor layer and a conductor layer (e.g., a metal layer, a doped semiconductor layer, such as a doped polysilicon or doped polysilicon germanium layer, etc.) on the dielectric layer. Alternatively, for dual-gate FETs, the additional layers can comprise multiple dielectric layers.

An embodiment of the method of forming the semiconductor structure, described above, comprises providing a wafer with a first semiconductor layer on an isolation layer (e.g., a silicon-on-insulator (SOI) wafer). A second different semiconductor layer (e.g., a silicon germanium layer) can be formed on the first semiconductor layer. Optionally, one or more third semiconductor layers can be formed on the second semiconductor layer.

The combined thickness of all of the semiconductor layers as compared to that of the first semiconductor layer alone is predetermined, during this process, to ensure the desired beta ratio for the subsequently formed semiconductor structure. Then, one or more cap layers can be formed above the various semiconductor layers.

Next, multi-layer identical fins can be patterned and etched into the wafer stopping at the first semiconductor layer. Thus, each of the multi-layer fins comprises portions of the second semiconductor layer, the optional third semiconductor layer and the cap layer. Once the multi-layer fins are formed, a sacrificial material can be deposited over the multi-layer fins and planarized to expose the top surface of the cap layer. Then, one of the multi-layer fins can be removed such that a first trench is formed in the sacrificial material. The cap layer from another of the multi-layer fins can also be removed such that a second trench is formed in the sacrificial material.

Once the first and second trenches are formed in the sacrificial material, they are filled with at least one additional layer. Depending upon whether the semiconductor structure being formed will be incorporated into a device with tri-gate or dual-gate non-planar FETs, the composition of the additional layers will vary. For example, for tri-gate FETs, the additional layers are formed by forming a dielectric layer (e.g., a thin gate oxide layer) on the bottom surfaces of the first and second trenches and, then, by forming a conductor layer (e.g., metal, doped polysilicon, doped polysilicon germanium, etc.) on the dielectric layer. For dual-gate FETs, the additional layers can be formed by forming multiple dielectric layers.

After the additional layers are formed, the sacrificial material and the first semiconductor layer are selectively and anisotropically etched stopping on the isolation layer. Thus, a first fin, comprising portions of the first semiconductor layer and the additional layer(s), and a second fin, comprising portions of the first semiconductor layer, the second semiconductor layer, the optional third semiconductor layer and the additional layer(s), are formed above the isolation layer. Due to the processes, described above, the first and second fins will have approximately the same overall height, but the combined height of the semiconductor layers within the fins will be different.

Another embodiment of the semiconductor structure comprises a wafer with an isolation layer that has a planar top surface and first and semiconductor fins on the planar top surface. The first semiconductor fin can extend vertically to a first height above the planar top surface, whereas the second fin can extend vertically to a second different height above the planar top surface. Specifically, both the first semiconductor fin and second semiconductor fin can each comprise a semiconductor layer (e.g., a silicon layer) adjacent to the isolation layer. This semiconductor layer can have approximately the same thickness in each of the fins. However, to achieve a greater height in the first fin, the first fin can further comprise an epitaxial semiconductor layer (e.g., an epitaxial silicon or epitaxial silicon germanium layer) on the semiconductor layer.

An embodiment of the method of forming the semiconductor structure, described above, comprises providing a wafer with a semiconductor layer on an isolation layer. A cap layer can be deposited on the semiconductor layer. The combined thickness of the semiconductor layer and cap layer as compared to that of the semiconductor layer alone is predetermined, during this process, to ensure the desired beta ratio for the subsequently formed semiconductor structure.

Then, multi-layer identical fins can be patterned and etched into the wafer stopping on the isolation layer. Thus, each of the multi-layer fins comprises portions of the semiconductor layer and the cap layer. Once the multi-layer fins are formed, a sacrificial material (e.g., an oxide) can be deposited and planarized to expose the cap layer. The cap layer can be removed from one of the multi-layer fins such that a trench is formed in the sacrificial material. This trench can then be filled with a semiconductor material (e.g., by epi growth of silicon or silicon germanium from the top surface of the semiconductor layer exposed at the bottom of the trench). After the trench is filled, the cap layer from another one of the multi-layer fins as well as the sacrificial material can be selectively removed such that a first semiconductor fin and a second semiconductor fin are formed on the planar top surface of the insulator layer. Due to the processes, described above, the first semiconductor fin will extend a first height above the planar top surface of the insulator layer, whereas the second semiconductor fin will extend a second different height above the planar top surface of the insulator layer.

These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Recently, static random access memory (SRAM) cells have incorporated multi-gate non-planar FETs. These SRAM cells can be formed, for example, using silicon-on-insulator (SOI) wafers, bulk wafers or hybrid orientation (HOT) wafers. Typically, such SRAM cells comprise two first type (e.g., n-type) pass-gate field effect transistors (FETs), two second type (e.g., p-type) pull-up FETs and two first type (e.g., n-type) pull-down FETs. For illustration purposes, embodiments of the SRAM cell are described herein with the pass-gate FETs and pull-down FETs being n-FETs and with the pull-up FETs being p-FETs. However, those skilled in the art will recognize that such SRAM cells can, alternatively, be formed with the pass-gate FETs and pull-down FETs being p-FETs and with the pull-up FETs being n-FETs. Furthermore, such SRAM cells are typically designed with stronger pull-down strength, where the width ratio of pull-down (drive) FETs to pass-gate (load) FETs (i.e., the beta ratio) is greater than approximately two. One method of achieving such a beta ratio (i.e. a greater effective channel width in the pull-down transistors as compared to the pass-gate transistors) in an SRAM cell is by incorporating multiple fins into the pull-down FETs and/or pass-gate FETs (e.g., at a ratio of 2:1). However, due to the conventional lithographic techniques used to pattern semiconductor fins, it may be difficult to fit the multiple fins required within the allotted space. Additionally, frequency doubling of fin pitch is not easily achieved using current state of the art lithographic technology, and thus, multi-gate non-planar FET SRAM cells may be compromised for either density or performance.

Therefore, there is a need in the art for an improved semiconductor structure and an associated method of forming the structure that allows a greater effective channel width to be achieved in pull-down FETs as compared to pass-gate FETs in the same multi-gate non-planar FET SRAM cell. One method of increasing the effective channel width of a non-planar FET is to increase the height of the semiconductor body (i.e., the height of the fin) that forms the channel and source/drain regions of the transistor. Consequently, the effective channel width of adjacent FETs on the same wafer can be varied by varying the heights of the fins that are incorporated into those transistors. U.S. Pat. No. 6,909,147 issued to Aller et al. on Jun. 21, 2005 and incorporated herein by reference discloses a semiconductor structure with semiconductor fins having different heights and a method of forming the structure. The semiconductor structure and method of Aller are suitable for the purpose for which they are disclosed. However, it would be advantageous to provide an improved semiconductor structure with semiconductor fins having different heights as well as an alternative method of forming such structure.

In view of the foregoing, disclosed herein are embodiments of an improved semiconductor structure that comprises semiconductor fins with different channel region heights on the same wafer. These fins with different channel region heights allow different multi-gate non-planar field effect transistors with different effective channel widths to be formed on the same wafer and, thus, to be incorporated into the same device (e.g., a static random access memory (SRAM) cell).

Referring toFIGS. 1 and 2, an embodiment of the semiconductor structure100a,100bof the invention comprises first and second fins151,152on an isolation layer101(e.g., on the top surface of a planar buried oxide layer). These fins (i.e., the first and second fin151,152) have approximately equal overall heights160above the isolation layer101. Each fin151,152comprises a semiconductor layer121,122adjacent to the isolation layer101and at least one additional layer131,132above the semiconductor layer. However, the height above the isolation layer101of the semiconductor layer121of the first fin151(i.e., a first height161) is less than the height above the isolation layer101of the semiconductor layer122of the second fin152(i.e., a second height162). More specifically, in the first fin151, the semiconductor layer121comprises a single layer of semiconductor material (e.g., a silicon layer102) above the isolation layer101. In the second fin152, the semiconductor layer122comprises multiple layers102-104of semiconductor materials (e.g., a silicon layer102with the same thickness as the single layer of silicon in the first fin151, a thin layer of silicon germanium103above the silicon layer102, another layer of silicon104above the silicon germanium103, etc.) above the isolation layer101. Thus, the height of the semiconductor layer121of the first fin151(i.e., a first height161) is less than the height of the semiconductor layer122of the second fin152(i.e., a second height162).

Consequently, given that the overall heights160of the fins151,152are approximately equal, but that the heights161,162of the semiconductor layer121,122in the different fins151,152are different, the height of the additional layer(s)131in the first fin151is necessarily greater than the height of the additional layer(s)132in the second fin152.

Additionally, depending upon whether the fins151,152will be incorporated into tri-gate or dual-gate non-planar FETs with different effective channel widths during subsequent processing, the composition of the additional layers131,132of the first and second fins151,152, respectively, will vary. For example, as illustrated in structure100aofFIG. 1, for tri-gate FETs (i.e., FETs having a gate on the top surface and sidewalls of the fin), the additional layers131,132can comprise a dielectric layer116(e.g., a thin gate oxide layer) adjacent to the semiconductor layer121,122of each fin and a conductor layer117(e.g., a metal layer, a doped semiconductor layer, such as a doped polysilicon or doped polysilicon germanium layer, etc.) on the dielectric layer116. Alternatively, as illustrated in structure100bofFIG. 2, for dual-gate FET (i.e., FETs having gates on only the sidewalls of the fin), the additional layers131,132can comprise multiple dielectric layers116-118, such as first dielectric layer116(e.g., a thin oxide layer) adjacent to the semiconductor layer121,122of each fin and a second dielectric layer118(e.g., a thick nitride layer) on the first dielectric layer116.

It should be noted that the relative difference in the height161of the semiconductor layer121in the first fin151and height162of the semiconductor layer122in the second fin152can be predetermined to achieve a desired beta ratio. For example, if the first fin151is to be incorporated into a pass-gate (load) FET and the second fin152is to be incorporated into a pull-down (drive) FET, then the ratio of height161of semiconductor layer121of the first fin151to the height162of the semiconductor layer122of the second fin152should be approximately 1:2. Thus, the beta ratio will be approximately two.

Referring toFIG. 3, an embodiment of the method of forming the semiconductor structures100a-b, described above and illustrated inFIGS. 1-2, comprises providing a wafer with a first semiconductor layer102on an isolation layer101(e.g., a silicon-on-insulator (SOI) wafer) (302, seeFIG. 3).

A second semiconductor layer103that comprises a different semiconductor material than the first semiconductor layer102can be formed on the first semiconductor layer102(304). For example, a thin (e.g., approximately 5-10 nm) single crystalline silicon germanium layer with approximately 1-5% germanium can be epitaxially grown on the first semiconductor layer102. Optionally, one or more third semiconductor layers104can be formed on the second semiconductor layer103. For example, a thick (e.g., approximately 20-50 nm) single crystalline silicon layer can be epitaxially grown on the silicon germanium layer103such that a silicon/silicon germanium/silicon stack is formed. The combined thickness of the silicon/silicon germanium/silicon stack102-104as compared to that of the first silicon layer102alone is predetermined, during process304, to ensure the desired beta ratio for a subsequently formed semiconductor device (e.g., SRAM) that will incorporate the subsequently formed semiconductor structure100aor100b. For example, for a beta ratio of two in a static random access memory (SRAM) cell, the thickness of stack102-104should be approximately twice that of the first silicon layer102. Following formation of the multiple semiconductor layers102-104at process304, one or more cap layers105-106(seeFIG. 4) can be formed on the wafer (306). For example, a thin (e.g., approximately 5-10 nm) blanket oxide layer can be deposited. Then, a thick (e.g., approximately 10-30 nm) blanket nitride layer can be deposited.

Next, multi-layer identical fins110a-bcan be formed in the wafer such that they extend vertically from the top surface180of the first semiconductor layer102(308, seeFIG. 5). Formation of these identical multi-layer fins110a-bcan be accomplished using conventional processing techniques. For example, a photoresist layer can be deposited onto the cap layer106. The photoresist layer can then be lithographically patterned. Following lithographic patterning, multiple reactive ion etch (RIE) processes can be performed to selectively and directionally etch the nitride layer106, the oxide layer105, the silicon layer104and the silicon germanium layer103stopping at the silicon layer102. Following, the selective RIE processes, the photoresist layer can be removed. Thus, each of the identical multi-layer fins110a-bcomprises portions of the second semiconductor layer103, the third semiconductor layer104and the cap layers105-106.

Once the multi-layer fins110a-bare formed above the first semiconductor layer102, a sacrificial material107is deposited over the multi-layer fins110a-band planarized to expose the top surface191of the cap layer106(310, seeFIG. 6). The sacrificial material107can, for example, comprise a dielectric material, such as a high density plasma (HDP) oxide which has good filling characteristics so as to completely fill the narrow spaces between the fins110a-b.

Next, one of the multi-layer fins (e.g., fin110a) is removed such that a first trench115ais formed in the sacrificial material107(312, seeFIG. 7). Removal of the fin110acan be accomplished, for example, by masking fin110b(e.g., with a patterned photo resist) and performing multiple reactive ion etch (RIE) processes to selectively remove the different layers103-106within the fin110a. Those skilled in the art will recognize that the RIE process used to remove the oxide layer105from the fin110awill also etch back the sacrificial material107if that material is an oxide. However, as mentioned above, the oxide layer105is preferably a very thin (e.g., approximately 5-10 nm) layer and etching back the sacrificial material to this degree will have negligible effects on the completed semiconductor structure100aor100b. Once, the multi-layer fin110ais completely removed. The mask above the fin110bis removed. Then, the cap layers105-106from fin110bare also removed (e.g., by multiple RIE processes) such that a second trench115bis formed in the sacrificial material107(312, seeFIG. 8). Since only the cap layers105-106, as opposed to the entire fin110b, are removed to form the second trench115b, the first trench115awill be deeper than the second trench1115b.

Once the first and second trenches115a-bare formed, they are filled with at least one additional layer (314). Depending upon whether the semiconductor structure being formed is to be incorporated into a device with tri-gate or dual-gate FETs, the composition of the additional layers will vary.

For example, to complete the structure100aofFIG. 1that can be used to form multiple tri-gate non-planar FETs with different effective channel widths on the same wafer, the additional layers are formed by forming a dielectric layer116on the bottom surfaces192a-bof the first and second trenches115a-b, respectively, and, then, by forming a conductor layer117on the dielectric layer116(316, seeFIGS. 9-10). Specifically, an approximately 1-2 nm gate oxide layer can be formed on the bottom surfaces192a-bof the trenches115a-busing a conventional thermal oxidation process. Then, the conductor layer117can be formed on the dielectric layer116by depositing and planarizing and/or etching back a conductive material (e.g., a metal). Alternatively, the conductor layer117can be formed on the dielectric layer by depositing and planarizing and/or etching back a semiconductor material (e.g., polysilicon, polysilicon germanium with approximately 1-5% germanium, etc.). The semiconductor material can be made conductive by doping with the appropriate first type dopant (e.g., an n-type dopant, such as phosphorus (P), antimony (Sb) or arsenic (As)) or second type dopant (e.g., a p-type dopant, such as boron (B)) using a conventional ion implantation process. If necessary, the conductor layers117in the different trenches115a-bmay be doped with different type dopants by performing separate masked implantation processes.

Alternatively, to complete the structure100bofFIG. 2that can be used to form multiple dual-gate non-planar FETs with different effect channel widths on the same wafer, the additional layers can be formed by forming multiple dielectric layers116and118within the trenches115a-b(318, seeFIGS. 9 and 11). For example, a first dielectric layer116(e.g., an approximately 1-2 nm oxide layer) can be formed (e.g., by thermal oxidation) on the bottom surfaces192a-bof the first and second trenches115a-band, then, a second dielectric layer118can be formed on the first dielectric layer116. The second dielectric layer118can be formed, for example, by depositing a nitride layer and planarizing and/or etching back the nitride layer.

After the additional layers are formed at process314, the sacrificial material107and the first semiconductor layer102are selectively and anisotropically etched, stopping at the isolation layer101(320). This etching process320results in a first fin151and a second fin152extending vertically from the isolation layer101(see structure100aofFIG. 1,100bofFIG. 2and detail descriptions thereof, above).

Following formation of the structure100aofFIG. 1or100bofFIG. 2, additional conventional processing techniques are performed (e.g., gate oxide formation on the fin sidewalls by thermal oxidation, gate conductor deposition and patterning, source/drain extension formation, halo formation, spacer formation, source/drain region formation, deposition and planarization of a blanket dielectric layer, contact formation, etc.) so as to complete the FET structures having different effective channel widths on the same wafer and, optionally, within the same device (e.g., within a single static random access memory (SRAM) cell).

Referring toFIG. 12, another embodiment of the semiconductor structure200of the invention comprises a wafer with an isolation layer201that has a planar top surface290and first and semiconductor fins251,252on the planar top surface290. The first semiconductor fin251can extend vertically to a first height261above the planar top surface290, whereas the second fin252can extend vertically to a second different height262above the planar top surface290(e.g., the first height261can be greater than the second height262).

In structure200, the first semiconductor fin251and second semiconductor fin252can each comprise a first semiconductor layer202(e.g., a silicon layer) adjacent to the isolation layer201. This first semiconductor layer can have approximately the same thickness in each of the fins251,252. However, to achieve the greater height in the first fin251, the first fin251can further comprise an epitaxial semiconductor layer219(e.g., an epitaxial silicon or epitaxial silicon germanium layer) on the first semiconductor layer202.

It should be noted that the relative difference in the height261of the first fin251and height262of the second fin252can be predetermined to achieve a desired beta ratio. For example, if the second fin252is to be incorporated into a pass-gate (load) FET and the first fin251is to be incorporated into a pull-down (drive) FET, then the ratio of height262of the second fin252to the height261of the first fin251should be approximately 1:2. Thus, the beta ratio will be approximately two.

Referring toFIG. 13, an embodiment of the method of forming the semiconductor structure200, described above, comprises providing a wafer comprising a semiconductor layer202on an isolation layer201(e.g., a silicon-on-insulator (SOI) wafer). A cap layer206(e.g., a thick nitride layer) can be deposited on the semiconductor layer202and planarized (1304, seeFIG. 14). The combined thickness of the cap layer-semiconductor layer202-206stack as compared to that of the semiconductor layer202alone is predetermined, during process1304, to ensure the desired beta ratio for the subsequently formed device (e.g., SRAM) that will incorporate the semiconductor structure200. For example, for a beta ratio of 2, the thickness of stack202-206should be approximately twice that of the semiconductor layer202.

Then, multi-layer identical fins210a-bcan be formed into the wafer such that they extend vertically from the planar top surface290of the insulator layer (1306, seeFIG. 15). Formation of these identical multi-layer fins210a-bcan be accomplished using conventional processing techniques. For example, a photoresist layer can be deposited onto the cap layer206. The photoresist layer can then be lithographically patterned. Following lithographic patterning of the photoresist layer, multiple reactive ion etch (RIE) processes can be performed to selectively and directionally etch the nitride layer206and silicon layer202, stopping at the isolation layer201. Following, the selective RIE processes, the photoresist layer can be removed. Thus, each of the multi-layer fins210a-bcomprises portions of the semiconductor layer202and the nitride layer206.

Once the identical multi-layer fins210a-bare formed above the planar top surface290of the isolation layer201, a sacrificial material207is deposited over the multi-layer fins210a-band planarized to expose the top surface291of the cap layer206(1308, seeFIG. 16). The sacrificial material207can, for example, comprise a dielectric material, such as a high density plasma (HDP) oxide which has good filling characteristics so as to completely fill the narrow spaces between the fins210a-b.

Then, the cap layer206is selectively removed from one of the multi-layer fins (e.g., fin210a) such that a trench215is formed in the sacrificial material207(1310, seeFIG. 17). This process1310can be accomplished, for example, by depositing a thin oxide layer over the wafer followed by an oxide disposable mask layer. The mask layer is lithographically patterned and the thin oxide layer is etched to expose the cap layer206of the fin210a. Then, a wet nitride etch process (e.g., using hot phosphoric acid (H3PO4) is performed, which simultaneously removes the cap layer206from fin210aand removes the mask layer from above the fin210b, leaving the thin oxide layer.

This trench215is then filled with a semiconductor material219(1312, seeFIG. 18). For example, the semiconductor material219, such as a single crystalline silicon or single crystalline silicon germanium, can be epitaxially grown from the top surface292of the semiconductor layer202exposed at the bottom of the trench215.

After the trench215is filled at process1312, the cap layer206from another one of the multi-layer fins as well as the sacrificial material207can be selectively removed (1314). Specifically, the cap layer206(i.e., nitride layer206from fin210bcan be removed, for example, by using a wet (hot phosphoric acid (H3PO4)) etch process (seeFIG. 19). Then, the sacrificial material207(i.e., HDP oxide) can be removed, for example, by using a wet (hydrofluoric acid (HF)) etch process (see completed structure200ofFIG. 12). The resulting structure200comprises a first semiconductor fin251and a second semiconductor fin252on the planar top surface291of the insulator layer201. Due to the processes1302-1314, described above, the first semiconductor fin251will extend a first height261above the planar top surface291of the insulator layer201, whereas the second semiconductor fin261will extend a second different height262above the planar top surface291of the insulator layer201(e.g., the second height262will be less than the first height261).

Following completion of the semiconductor structure200ofFIG. 12, additional conventional processing techniques are performed (e.g., gate oxide formation on the fin sidewalls, gate conductor deposition and patterning, source/drain extension formation, halo formation, spacer formation, source/drain region formation, deposition and planarization of a blanket dielectric layer, contact formation, etc.) so as to complete the FET structures having different effective channel widths on the same wafer and, optionally, within the same device (e.g., within a single static random access memory (SRAM) cell).

Therefore, disclosed above are embodiments of an improved semiconductor structure that comprises fins that are positioned on the same planar surface of a wafer and that have channel regions with different heights. In one embodiment the different channel region heights are accomplished by varying the overall heights of the different fins. In another embodiment the different channel region heights are accomplished by varying, not the overall heights of the different fins, but rather by varying the heights of a semiconductor layer within each of the fins. This embodiment has the advantage of simplifying subsequent lithographic processes, due to the fact that the top of each fin is at the same level. The disclosed semiconductor structure embodiments allow different multi-gate non-planar FETs (i.e., tri-gate or dual-gate FETs) with different effective channel widths to be formed of the same wafer. The disclosed method embodiments allow for accurate control of the different channel region heights and, thus, accurate control of the different effective channel widths for the individual FETs. The ability to accurately adjust the effective channel widths of individual FETs on the same wafer in turn allows the beta ratio of devices that incorporate multiple FETs (e.g., static random access memory (SRAM) cells) to be selectively adjusted.