Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises sacrificial material of different composition from the first-tier material there-above and from the second-tier material tier there-above. The sacrificial material is of different composition from that of an uppermost portion of the conductor material of the conductor tier. The sacrificial material is isotropically etched selectively relative to the uppermost portion of the conductor material of the conductor tier, selectively relative to the first-tier material there-above, and selectively relative to the second-tier material there-above. After the isotropic etching, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other methods and structure independent of method are disclosed.

TECHNICAL FIELD

Embodiments disclosed herein pertain to memory arrays and to methods used in forming a memory array.

BACKGROUND

Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate.

NAND may be a basic architecture of integrated flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). NAND architecture may be configured in a three-dimensional arrangement comprising vertically-stacked memory cells individually comprising a reversibly programmable vertical transistor. Control or other circuitry may be formed below the vertically-stacked memory cells. Other volatile or non-volatile memory array architectures may also comprise vertically-stacked memory cells that individually comprise a transistor.

Memory arrays may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks), and memory planes, for example as shown and described in any of U.S. Patent Application Publication Nos. 2015/0228651, 2016/0267984, and 2017/0140833. The memory blocks may at least in part define longitudinal outlines of individual wordlines in individual wordline tiers of vertically-stacked memory cells. Connections to these wordlines may occur in a so-called “stair-step structure” at an end or edge of an array of the vertically-stacked memory cells. The stair-step structure includes individual “stairs” (alternately termed “steps” or “stair-steps”) that define contact regions of the individual wordlines upon which elevationally-extending conductive vias contact to provide electrical access to the wordlines.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass methods used in forming a memory array, for example an array of NAND or other memory cells that may have at least some peripheral control circuitry under the array (e.g., CMOS-under-array). Embodiments of the invention encompass so-called “gate-last” or “replacement-gate” processing, so-called “gate-first” processing, and other processing whether existing or future-developed independent of when transistor gates are formed. Embodiments of the invention also encompass a memory array (e.g., NAND architecture) independent of method of manufacture. First example method embodiments are described with reference toFIGS. 1-19which may be considered as a “gate-last” or “replacement-gate” process, and starting withFIGS. 1-5.

FIGS. 1 and 2show a construction10having an array or array area12in which elevationally-extending strings of transistors and/or memory cells will be formed. Construction10comprises a base substrate11having any one or more of conductive/conductor/conducting, semiconductive/semiconductor/semiconducting, or insulative/insulator/insulating (i.e., electrically herein) materials. Various materials have been formed elevationally over base substrate11. Materials may be aside, elevationally inward, or elevationally outward of theFIGS. 1-5-depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate11. Control and/or other peripheral circuitry for operating components within an array (e.g., array12) of elevationally-extending strings of memory cells may also be fabricated and may or may not be wholly or partially within an array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. In this document, a “sub-array” may also be considered as an array.

A conductor tier16comprising conductor material17has been formed above substrate11. In one embodiment, conductor material17comprises conductively-doped semiconductive material13(e.g., n-type conductively-doped polysilicon) atop (directly above, and e.g., directly against) metal material15(e.g., WSix). Conductor tier16may comprise part of control circuitry (e.g., peripheral-under-array circuitry and/or a common source line or plate) used to control read and write access to the transistors and/or memory cells that will be formed within array12. A stack18comprising vertically-alternating insulative tiers20* and conductive tiers22* has been formed above conductor tier16(an * being used as a suffix to be inclusive of all such same-numerically-designated components that may or may not have other suffixes). Example thickness for each of tiers20* and22* is 20 to 60 nanometers. Only a small number of tiers20* and22* is shown, with more likely stack18comprising dozens, a hundred or more, etc. of tiers20* and22*. Other circuitry that may or may not be part of peripheral and/or control circuitry may be between conductor tier16and stack18. For example, multiple vertically-alternating tiers of conductive material and insulative material of such circuitry may be below a lowest of the conductive tiers22* and/or above an uppermost of the conductive tiers22*. For example, one or more select gate tiers (not shown) may be between conductor tier16and the lowest conductive tier22* and one or more select gate tiers may be above an uppermost of conductive tiers22*. Alternately or additionally, at least one of the depicted uppermost and lowest conductive tiers22* may be a select gate tier. Regardless, conductive tiers22* (alternately referred to as first tiers) may not comprise conducting material and insulative tiers20* (alternately referred to as second tiers) may not comprise insulative material or be insulative at this point in processing in conjunction with the hereby initially-described example method embodiment which is “gate-last” or “replacement-gate”.

In some embodiments, a lowest first tier22zis thicker than the first tiers22* there-above and in one such embodiment is at least 1.5 times thicker than first tiers22* there-above. In one embodiment and as shown, lowest first tier22zis not directly against conductor material17of conductor tier16, for example where a lowest second tier20zis vertically between conductor material17of the conductor tier16and lowest first tier22z. Alternately, the lowest first tier may be directly against the conductor material of the conductor tier (not shown). In one embodiment, lowest second tier20zis thinner than second tiers20* there-above. In one embodiment, a next-lowest second tier20xthat is above lowest second tier20zis thicker than second tiers20* there-above. In one embodiment, lowest second tier20zis directly against a top19of conductor material17of conductor tier16.

Material of the first tiers is of different composition from material of the second tiers. Example conductive tiers22comprise first material26(e.g., silicon nitride) which may be wholly or partially sacrificial. Example insulative tiers20* comprise second material24(e.g., silicon dioxide) which may be wholly or partially sacrificial. Lowest first tier22zcomprises sacrificial material21of different composition from first-tier material26there-above and from second-tier material24there-above. Sacrificial material21is of different composition from that of an uppermost portion23of conductor material17of conductor tier16. Sacrificial material21may be of different composition from all of conductor material17(not shown). In one embodiment, the different compositions comprise different composition dopants in sacrificial material21and uppermost portion23of conductor material17. For example, and by way of example only, sacrificial material21is shown as comprising a dopant31indicated in the drawings by stippling/dots. Example conductively-doped semiconductive material13is also shown as comprising dopant31throughout, with example upper portion23also comprising a different composition dopant33. Different composition dopants31and33may be homogenously distributed throughout the regions or material in which such are received or may be non-homogenously distributed. In one embodiment and as is intended to be shown, sacrificial material21and uppermost portion23of conductor material17are of the same composition but for said different composition dopants (e.g., dopant33being in uppermost portion23and not being in sacrificial material21). Regardless, in one embodiment, the different composition dopant33in uppermost portion23is at a concentration of at least 1×1014atoms/cm3in uppermost portion23. Example different composition dopant33in uppermost portion23comprises at least one of carbon, nitrogen, boron, arsenic, or metal material (e.g., gallium, antimony, aluminum, indium, tungsten, tungsten silicide, titanium, titanium nitride, etc.). Dopant33may be provided in uppermost portion23of conductor material17regardless of whether material13is conductively-doped semiconductive material (e.g., example dopant33may be provided within metal material). Further, as an example, material21of lowest first tier22zmay be undoped. In the context of this document, undoped means anywhere from 0 atoms/cm3up to 1×1013atoms/cm3. In one embodiment, material21of lowest first tier22zcomprises undoped or phosphorus-doped polysilicon and, in one embodiment, material13comprises phosphorus-doped polysilicon.

Regardless, in one embodiment, sacrificial material21comprises polysilicon, and in one such embodiment uppermost portion23of conductor material17comprises polysilicon of different composition from that of sacrificial material21(e.g., at least by the presence of different composition dopant33). Regardless, in one embodiment, uppermost portion23of conductor material17of conductor tier16comprises polysilicon. In one embodiment, at least a next-lower portion (e.g.,27) under uppermost portion23of conductor material17is of the same composition as that of sacrificial material21.

Channel openings25have been formed (e.g., by etching) through insulative tiers20* and conductive tiers22* to conductor tier16. Channel openings25may taper radially-inward (not shown) moving deeper in stack18. In some embodiments, channel openings25may go into conductor material17of conductor tier16as shown or may stop there-atop (not shown). Alternately, as an example, channel openings25may stop atop or within the lowest insulative tier20. A reason for extending channel openings25at least to into conductor material17of conductor tier16is to provide and anchoring effect to material that is within channel openings25. Etch-stop material (not shown) may be within or atop conductor material17of conductor tier16to facilitate stopping of the etching of channel openings25relative to conductor tier16when such is desired. Such etch-stop material may be sacrificial or non-sacrificial.

Horizontally-elongated trenches40have been formed (e.g., by anisotropic etching) into stack18to form laterally-spaced memory-block regions58. Trenches40may have respective bottoms that are directly against conductor material17(atop or within) of conductor tier16(as shown). By way of example and for brevity only, channel openings25are shown as being arranged in groups or columns of staggered rows of four and five channel openings25per row and being arrayed in laterally-spaced memory-block regions58that will comprise laterally-spaced memory blocks58in a finished circuitry construction. In this document, “block” is generic to include “sub-block”. Memory-block regions58and resultant memory blocks58(not yet shown) may be considered as being longitudinally elongated and oriented, for example along a direction55. Any alternate existing or future-developed arrangement and construction may be used.

Transistor channel material may be formed in the individual channel openings elevationally along the insulative tiers and the conductive tiers, thus comprising individual channel-material strings, which is directly electrically coupled with conductive material in the conductor tier. Individual memory cells of the example memory array being formed may comprise a gate region (e.g., a control-gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to comprise a charge-blocking region, storage material (e.g., charge-storage material), and an insulative charge-passage material. The storage material (e.g., floating gate material such as doped or undoped silicon or charge-trapping material such as silicon nitride, metal dots, etc.) of the individual memory cells is elevationally along individual of the charge-blocking regions. The insulative charge-passage material (e.g., a band gap-engineered structure having nitrogen-containing material [e.g., silicon nitride] sandwiched between two insulator oxides [e.g., silicon dioxide]) is laterally between the channel material and the storage material.

FIGS. 1-4show one embodiment wherein charge-blocking material30, storage material32, and charge-passage material34have been formed in individual channel openings25elevationally along insulative tiers20* and conductive tiers22*. Transistor materials30,32, and34(e.g., memory-cell materials) may be formed by, for example, deposition of respective thin layers thereof over stack18and within individual openings25followed by planarizing such back at least to a top surface of stack18.

Channel material36has also been formed in channel openings25elevationally along insulative tiers20* and conductive tiers22*, thus comprising individual operative channel-material strings53in channel openings25. Channel material36may be considered as having a lowest surface71thereof. Channel-material strings53in one embodiment have memory-cell materials (e.g.,30,32, and34) there-along and with second-tier material (e.g.,24) being horizontally-between immediately-adjacent channel-material strings53. Materials30,32,34, and36are collectively shown as and only designated as material37inFIGS. 1 and 2due to scale. Example channel materials36include appropriately-doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called III/V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). Example thickness for each of materials30,32,34, and36is 25 to 100 Angstroms. Punch etching may be conducted to remove materials30,32, and34from the bases of channel openings25(not shown) to expose conductor tier16such that channel material36is directly against conductor material17of conductor tier16. Such punch etching may occur separately with respect to each of materials30,32, and34(as shown) or may occur with respect to only some (not shown). Alternately, and by way of example only, no punch etching may be conducted and channel material36may be directly electrically coupled to conductor material17of conductor tier16only by a separate conductive interconnect (not yet shown). Channel openings25are shown as comprising a radially-central solid dielectric material38(e.g., spin-on-dielectric, silicon dioxide, and/or silicon nitride). Alternately, and by way of example only, the radially-central portion within channel openings25may include void space(s) (not shown) and/or be devoid of solid material (not shown).

Referring toFIGS. 6 and 7, sacrificial material21(not shown) has been isotropically etched selectively relative to uppermost portion23of conductor material17of conductor tier16, selectively relative to first-tier material26there-above, and selectively relative second-tier material24there-above. In one embodiment where lowest second tier20zis present, and as shown, the isotropic etching may also be conducted selectively relative to material24thereof. The artisan is capable of selecting any existing or future-developed etching chemistry (e.g., wet) and conditions capable of producing the construction ofFIG. 6from that ofFIG. 2. As an example, and by way of example only, some embodiments of the invention were motivated where polysilicon is the primary component in each of materials21and13and using tetramethyl ammonium hydroxide (TMAH) for such isotropic etching. TMAH may be used to etch polysilicon selectively relative to silicon dioxide and silicon nitride (examples for materials24and26in gate-last processing) if the polysilicon is undoped or phosphorus doped. Addition of a dopant33(other than phosphorus) to polysilicon renders such polysilicon largely not etchable by TMAH, thus in such example enabling producing the construction ofFIG. 6from that ofFIG. 2using an etching fluid comprising TMAH.

In one embodiment, after the isotropically etching, second-tier material24of lowest second tier20zis etched to expose an upper surface (e.g.,19) of conductor material17of conductor tier16, and a sidewall of channel material36of channel-material strings53in lowest first tier22zis exposed.FIGS. 8 and 9show example such subsequent processing where, in one embodiment, material30(e.g., silicon dioxide), material32(e.g., silicon nitride), and material34(e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) have been etched in each of tiers22zand20zto expose a sidewall41of channel material36of channel-material strings53in tier22z. Any of materials30,32, and34in tier22zmay be considered as being sacrificial material therein.

As an example, consider an embodiment where material13comprises polysilicon, material24is silicon dioxide, and memory-cell materials30,32, and34individually are one or more of silicon dioxide and silicon nitride layers. In such example, the depicted construction can result by using modified or different chemistries for sequentially etching silicon dioxide and silicon nitride selectively relative to the other. As examples, a solution of 100:1 (by volume) water to HF will etch silicon dioxide selectively relative to silicon nitride, whereas a solution of 1000:1 (by volume) water to HF will etch silicon nitride selectively relative to silicon dioxide. Accordingly, and in such example, such etching chemistries can be used in an alternating manner where it is desired to achieve the example construction shown byFIGS. 8 and 9. The artisan is capable of selecting other chemistries for etching other different materials where a construction as shown inFIGS. 8 and 9is desired.

Referring toFIGS. 10 and 11, conductive material42has been formed in lowest first tier22zto directly electrically couple together channel material36of individual of channel-material strings53and conductor material17of conductor tier16. Example conductive materials include conductively-doped semiconductor material (e.g., conductively-doped polysilicon, such as comprising dopant31in sufficient quantity/concentration to render the polysilicon conductive) and metal material. In one embodiment, conductive material42in lowest first tier22zis directly against sidewall41of channel material36of channel-material strings53and in one embodiment conductive material42in lowest first tier22zis directly against an uppermost surface (e.g.,19) of uppermost portion23of conductor material17of conductor tier16.

Referring toFIGS. 12 and 13, conductive material42has been removed from trenches40, for example by timed isotropic etching that may be conducted selectively relative to materials24,26, and17. Such may result in lateral recessing of conductive material42towards channel-material strings53(not shown). Such may result in some etching of conductor material17when exposed (not shown). An example etching chemistry where material42is conductively-doped polysilicon, material24is silicon dioxide, material26is silicon nitride, and uppermost portion23of material13includes at least one dopant other than phosphorus (including in addition thereto) is TMAH.

Referring toFIGS. 14-19, material26(not shown) of conductive tiers22has been removed, for example by being isotropically etched away through trenches40ideally selectively relative to the other exposed materials (e.g., using liquid or vapor H3PO4as a primary etchant where material26is silicon nitride and other materials comprise one or more oxides or polysilicon). Material26(not shown) in conductive tiers22in the example embodiment is sacrificial and has been replaced with conducting material48, and which has thereafter been removed from trenches40, thus forming individual conductive lines29(e.g., wordlines) and elevationally-extending strings49of individual transistors and/or memory cells56.

A thin insulative liner (e.g., Al2O3and not shown) may be formed before forming conducting material48. Approximate locations of transistors and/or memory cells56are indicated with a bracket inFIG. 19and some with dashed outlines inFIGS. 14, 15, 17, and 18, with transistors and/or memory cells56being essentially ring-like or annular in the depicted example. Alternately, transistors and/or memory cells56may not be completely encircling relative to individual channel openings25such that each channel opening25may have two or more elevationally-extending strings49(e.g., multiple transistors and/or memory cells about individual channel openings in individual conductive tiers with perhaps multiple wordlines per channel opening in individual conductive tiers, and not shown). Conducting material48may be considered as having terminal ends50(FIG. 19) corresponding to control-gate regions52of individual transistors and/or memory cells56. Control-gate regions52in the depicted embodiment comprise individual portions of individual conductive lines29. Materials30,32, and34may be considered as a memory structure65that is laterally between control-gate region52and channel material36. In one embodiment and as shown with respect to the example “gate-last” processing, conducting material48of conductive tiers22is formed after forming channel openings25and/or trenches40. Alternately, the conducting material of the conductive tiers may be formed before forming channel openings25and/or trenches40(not shown), for example with respect to “gate-first” processing.

A charge-blocking region (e.g., charge-blocking material30) is between storage material32and individual control-gate regions52. A charge block may have the following functions in a memory cell: In a program mode, the charge block may prevent charge carriers from passing out of the storage material (e.g., floating-gate material, charge-trapping material, etc.) toward the control gate, and in an erase mode the charge block may prevent charge carriers from flowing into the storage material from the control gate. Accordingly, a charge block may function to block charge migration between the control-gate region and the storage material of individual memory cells. An example charge-blocking region as shown comprises insulator material30. By way of further examples, a charge-blocking region may comprise a laterally (e.g., radially) outer portion of the storage material (e.g., material32) where such storage material is insulative (e.g., in the absence of any different-composition material between an insulative storage material32and conducting material48). Regardless, as an additional example, an interface of a storage material and conductive material of a control gate may be sufficient to function as a charge-blocking region in the absence of any separate-composition-insulator material30. Further, an interface of conducting material48with material30(when present) in combination with insulator material30may together function as a charge-blocking region, and as alternately or additionally may a laterally-outer region of an insulative storage material (e.g., a silicon nitride material32). An example material30is one or more of silicon hafnium oxide and silicon dioxide.

In one embodiment and as shown, lowest surface71of channel material36of channel-material strings53is never directly against any of conductor material17of conductor tier16.

Intervening material57has been formed laterally-between and longitudinally-along immediately-laterally-adjacent memory blocks58. Intervening material57may provide lateral electrical isolation (insulation) between immediately-laterally-adjacent memory-blocks. Such may include one or more of insulative, semiconductive, and conducting materials and, regardless, may facilitate conductive tiers22from shorting relative one another in a finished circuitry construction. Example insulative materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Intervening material57may include through array vias (not shown).

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

Alternate embodiment constructions may result from method embodiments described above, or otherwise. Regardless, embodiments of the invention encompass existing or future-developed integrated circuitry independent of method of manufacture. Nevertheless, such circuitry may have any of the attributes as described herein in method embodiments. Likewise, the above-described method embodiments may incorporate, form, and/or have any of the attributes described with respect to device embodiments.

In one embodiment, a memory array (e.g.,12) comprising strings (e.g.,49) of memory cells (e.g.,56) comprises a conductor tier (e.g.,16) comprising conductor material (e.g.,17). The array comprises laterally-spaced memory blocks (e.g.,58) individually comprising a vertical stack (e.g.,18) comprising alternating insulative tiers (e.g.,20*) and conductive tiers (e.g.,22*) directly above the conductor tier. Channel-material strings (e.g.,53) of memory cells (e.g.,56) extend through the insulative tiers and the conductive tiers. Conducting material (e.g.,42) of a lowest (e.g.,22z) of the conductive tiers directly electrically couples together the channel material (e.g.,36) of individual of the channel-material strings and the conductor material of the conductor tier. Intervening material (e.g.,57) is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises insulating material. The conductor material in the conductor tier comprises conductively-doped semiconductive material having one of a primary n-type or p-type conductivity-producing dopant therein (e.g.,31). The primary n-type dopant or the primary p-type dopant in this context is what renders what would be an otherwise semiconductive material to be conductive as a result of concentration of such primary dopant type. At least an uppermost portion (e.g.,23) of the conductor material in the conductor tier comprises at least one secondary dopant (e.g.,33) of different composition from that of the primary dopant.

In one embodiment, the different primary and secondary dopants are of the same n or p type, and in another embodiment are of different n or p type. In one embodiment, the secondary dopant is one or more of carbon, nitrogen, boron, arsenic, or metal material. In one embodiment, the secondary dopant is one or more of Sb, Bi, Li, Al, or In. In one embodiment, the secondary dopant comprises multiple different compositions.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a memory array (e.g.,12) comprising strings (e.g.,49) of memory cells (e.g.,56) comprises a conductor tier (e.g.,16) comprising n-type conductively-doped polysilicon (e.g.,13) having a primary n-type conductivity-producing dopant therein (e.g.,31). The array comprises laterally-spaced memory blocks (e.g.,58) individually comprise a vertical stack (e.g.,18) comprising alternating insulative tiers (e.g.,20*) and conductive tiers (e.g.,22*) directly above the conductor tier. Channel-material strings (e.g.,53) of memory cells (e.g.,56) extend through the insulative tiers and the conductive tiers. A lowest (e.g.,20z) of the conductive tiers comprises n-type conductively-doped polysilicon directly against the n-type conductively-doped polysilicon of the conductor tier and directly against a sidewall (e.g.,41) of channel material (e.g.,36) of the channel-material strings in the lowest conductive tier. Intervening material (e.g.,57) is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises insulating material. At least an uppermost portion (e.g.,23) of the n-type conductively-doped polysilicon in the conductor tier comprise at least one secondary dopant of different composition from that of the primary dopant. In one embodiment, the primary dopant is P and the secondary dopant is one or more of C, N, B, As, Sb, Bi, Li, Al, In, or metal material. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

The above processing(s) or construction(s) may be considered as being relative to an array of components formed as or within a single stack or single deck of such components above or as part of an underlying base substrate (albeit, the single stack/deck may have multiple tiers). Control and/or other peripheral circuitry for operating or accessing such components within an array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., CMOS under-array). Regardless, one or more additional such stack(s)/deck(s) may be provided or fabricated above and/or below that shown in the figures or described above. Further, the array(s) of components may be the same or different relative one another in different stacks/decks and different stacks/decks may be of the same thickness or of different thicknesses relative one another. Intervening structure may be provided between immediately-vertically-adjacent stacks/decks (e.g., additional circuitry and/or dielectric layers). Also, different stacks/decks may be electrically coupled relative one another. The multiple stacks/decks may be fabricated separately and sequentially (e.g., one atop another), or two or more stacks/decks may be fabricated at essentially the same time.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

Further, “directly above”, “directly below”, and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “below” and “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is below/under the other be elevationally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Where one or more example composition(s) is/are provided for any material, that material may comprise, consist essentially of, or consist of such one or more composition(s). Further, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.

Any use of “row” and “column” in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features and along which components have been or may be formed. “Row” and “column” are used synonymously with respect to any series of regions, components, and/or features independent of function. Regardless, the rows may be straight and/or curved and/or parallel and/or not parallel relative one another, as may be the columns. Further, the rows and columns may intersect relative one another at 90° or at one or more other angles (i.e., other than the straight angle).

The composition of any of the conductive/conductor/conducting materials herein may be metal material and/or conductively-doped semiconductive/semiconductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compound(s).

Herein, any use of “selective” as to etch, etching, removing, removal, depositing, forming, and/or formation is such an act of one stated material relative to another stated material(s) so acted upon at a rate of at least 2:1 by volume. Further, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials at a rate of at least 2:1 by volume for at least the first 75 Angstroms of depositing, growing, or forming.

Unless otherwise indicated, use of “or” herein encompasses either and both.

CONCLUSION

In some embodiments, a method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises sacrificial material of different composition from the first-tier material there-above and from the second-tier material tier there-above. The sacrificial material is of different composition from that of an uppermost portion of the conductor material of the conductor tier. The sacrificial material is isotropically etched selectively relative to the uppermost portion of the conductor material of the conductor tier, selectively relative to the first-tier material there-above, and selectively relative to the second-tier material there-above. After the isotropic etching, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.

In some embodiments, a method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material comprising n-type conductively-doped polysilicon on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises undoped or phosphorus-doped polysilicon. A lowest of the second tiers is vertically between the lowest first tier and the conductor tier. The undoped or phosphorus-doped polysilicon of the lowest first tiers is isotropically etched selectively relative to the n-type conductively-doped polysilicon of the conductor tier and selectively relative to the first-tier material there-above and the second-tier material there-above. The etching uses an etching fluid comprising tetramethyl ammonium hydroxide. After the isotropic etching, the second-tier material of the lowest second tier to is etched to expose an upper surface of the n-type conductively-doped polysilicon of the conductor tier. After the isotropic etching, a sidewall of the channel material of the channel-material strings is exposed in the lowest first tier. Conductive material in the lowest first tier is formed directly against the n-type conductively-doped polysilicon of the conductor tier and directly against the exposed sidewalls of the channel material of the channel-material strings in the lowest first tier to directly electrically couple together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.

In some embodiments, a memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lowest of the conductive tiers directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises insulating material. The conductor material in the conductor tier comprises conductively-doped semiconductive material that has one of a primary n-type or p-type conductivity-producing dopant therein. At least an uppermost portion of the conductor material in the conductor tier comprises a secondary dopant of different composition from that of the primary dopant.

In some embodiments, a memory array comprising strings of memory cells comprises a conductor tier comprising n-type conductively-doped polysilicon that has a primary n-type conductivity-producing dopant therein. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprise n-type conductively-doped polysilicon directly against the n-type conductively-doped polysilicon of the conductor tier and directly against a sidewall of channel material of the channel-material strings in the lowest conductive tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises insulating material. At least an uppermost portion of the n-type conductively-doped polysilicon in the conductor tier comprises a secondary dopant of different composition from that of the primary dopant.