MOS logic circuit responsive to an irreversible control voltage for permanently varying its signal transfer characteristic

A MOS logic circuit including a known MOS logic circuit arrangement having a particular input/output signal transfer characteristic and a control gating circuit including an FET connected to the known MOS logic circuit arrangement, the gate of which gating circuit receives a control voltage derived from an irreversible control voltage generator utilizing a fuse. Under the control of the irreversible control voltage, the MOS logic circuit can permanently change the known logic circuit arrangement's signal transfer characteristic without varying its logic function.

BACKGROUND OF THE INVENTION 
This invention relates to a MOS logic circuit including MOS transistors and 
in particular to a MOS logic circuit capable of changing either its logic 
functions or changing its transfer signal characteristic without varying 
its logic functions by varying an output voltage of a voltage generating 
means in an irreversible fashion. 
Where in a conventional MOS logic circuit there occurs a discrepancy 
between the expected difference in transmission speeds of a plurality of 
signals and the actual value obtained when the circuit is integrated, it 
is sometimes necessary to change the logic functions thereof. In the prior 
art techniques, once a logic circuit has been realized as an integrated 
circuit, if it is desired to change its logic functions, it is necessary 
to produce a new integrated circuit. In order to avoid such a time 
consuming effort, an attempt has been made at a circuit design step to 
prepare two sorts of circuit patterns, i.e., one having the originally 
designed logic function and the other having a changed logic function 
whose design modification is based on initially anticipated problems. In 
order to avoid producing a logical change to correct for a difference in 
transmission speeds of a plurality of signals, another attempt is made to 
design a MOS logic circuit with an excess signal transmission speed 
allowance or to design a MOS logic circuit by providing an excess 
allowance to the signal transmission time. However, as the circuit becomes 
larger in size, complicated in design and higher in circuit operation 
speed, the conventional method requires difficult to design circuit 
patterns and suffers a disadvantage of reducing the functionability of the 
circuit. 
On the other hand, in a conventional MOS logic circuit, an input signal 
voltage/output signal voltage relation, a time variation ratio of the 
output signal voltage to the input signal voltage or a transmission time 
ratio of the output signal to the input signal is determined by the 
electrical characteristic of MOS transistors by which a logic circuit is 
made up. Once the input/output characteristic has been determined in the 
conventional MOS logic circuit, the input/output characteristic of the MOS 
logic circuit cannot be changed unless the process parameters relating to 
the electrical characteristic of the MOS transistors are varied, thus 
requiring an excess voltage allowance and excess time allowance and thus 
complicating the circuit design. As the circuit becomes larger in size and 
higher in packing density and operation speeds, it becomes more and more 
difficult to design a proper logic circuit with minimal excess redundancy. 
SUMMARY OF THE INVENTION 
It is therefore an object of this invention to provide a MOS logic circuit 
without any excess redundancy in design, of which the relation between an 
input signal and an output signal can be changed under the control of an 
irreversible control voltage. 
It is another object of this invention to provide a MOS logic circuit 
without any excess redundancy in design, of which the logic function can 
be changed under the control of an irreversible control voltage. 
It is another object of this invention to provide a MOS logic circuit 
without any excess redundancy in design, of which the signal transfer 
characteristic can be changed under the control of an irreversible control 
voltage with no change of the logic function thereof. 
The MOS logic circuit in accordance with the invention comprises a known 
logic circuit, a control circuit connected to the known logic circuit, and 
a generating circuit for generating an irreversible voltage to be applied 
to the control circuit. 
The MOS logic circuit in accordance with the invention comprises: 
a MOS logic circuit means including at least a first and a second MOS field 
effect transistor, at least one gate electrode of which first and second 
MOS transistors being connected to a signal input terminal, each one end 
of both current paths of which first and second MOS transistors being 
mutually connected together to form a node for a signal output terminal, 
and which circuit means being coupled between a pair of power supply 
terminals; 
a generator means including a fuse for generating an irreversible control 
voltage; 
a control circuit means including at least a third MOS field effect 
transistor, the source-drain current path of which being series-connected 
between one of the power supply terminals and one of the other ends of the 
first and second MOS transistors, the gate electrode of which being 
connected to receive the irreversible control voltage derived from said 
generator means; and 
logic functions between the input/output signals of the MOS logic circuit 
being changed under the control of the control circuit means. 
Further, the MOS logic circuit in accordance with the invention comprises: 
a MOS logic circuit means which is coupled between a pair of power supply 
terminals, including at least a first and a second MOS field effect 
transistor, at least one gate electrode of which being connected to a 
signal input terminal and each one end of both current paths of which 
being mutually connected together to form a node for a signal output 
terminal, and a third MOS field effect transistor, the gate electrode of 
which being connected to the signal input terminal and the drain of which 
being connected to the node for the signal output terminal; 
a generator means including a fuse for generating an irreversible control 
voltage; 
a control circuit means including at least a fourth MOS field effect 
transistor, the gate electrode of which being connected to receive the 
irreversible control voltage derived from the generator means, and the 
source-drain current path of which being connected between one of the 
power supply terminals and the node through the source-drain current path 
of the third transistor; and 
signal transfer characteristics between input/output signals of the MOS 
logic circuit being changed under the control of the control circuit means 
with the logic functions thereof remaining unchanged. 
Furthermore, the MOS logic circuit in accordance with the invention 
comprises: 
a MOS logic circuit means which is coupled between a pair of power supply 
terminals, including at least a first and a second MOS field effect 
transistor, at least one gate electrode of which being connected to a 
signal input terminal and each one end of both current paths of the first 
and second MOS field effect transistors being mutually connected together 
to form a node for a signal output terminal; 
a generator means including a fuse for generating an irreversible control 
voltage; and 
a control circuit means including at least a third MOS field effect 
transistor, the gate electrode of which being connected to receive the 
irreversible control voltage derived from the generator means, and the 
drain-source current path of which being connected between the node for 
the signal output terminal and one of the power supply terminals; and 
signal transfer characteristics between input/output signals of the MOS 
logic circuit being changed under the control of the control circuit with 
the logic functions thereof remaining unchanged. 
According to this invention, there is an advantage that a MOS logic circuit 
without excess voltage allowance as well as excess circuit operation 
allowance may be obtained by way of introduction of the irreversible 
control voltage derived from the generator to change the input/output 
signal transfer characteristics with the logic functions thereof 
unchanged. 
Another advantage in accordance with the invention is obtained in that, 
since the MOS logic circuit has the redundancy function of performing a 
change of logic functions by utilizing the irreversible control voltage 
derived from the generator, it is possible to avoid a design modification 
resulting from the presence or absence of a logic function change and thus 
to permit a simpler, proper circuit design without involving any excess 
redundancy.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
A MOS logic circuit of this invention is broadly classified into the 
following two categories: 
(1) A MOS logic circuit adapted to vary logic functions of a whole MOS 
logic circuit by varying an irreversible control voltage; 
(2) A MOS logic circuit adapted to vary a signal transfer characteristic 
between the input/output signals thereof by varying an irreversible 
control voltage with the logic functions of a whole MOS logic circuit 
unchanged. 
The preferred embodiments of the MOS logic circuit according to this 
invention will be explained hereinafter in connection with the 
first-mentioned category. 
FIG. 1 shows a block diagram of the basic construction of the 
above-mentioned MOS logic circuit which comprises a known MOS logic 
circuit 100, such as an AND gate, having an input Vin and an output Vout, 
a control circuit 200 connected to the known MOS logic circuit and having 
an input V.sub.C, and a generating circuit 300 for producing an 
irreversible control voltage V.sub.O to be applied to the input V.sub.C of 
the control circuit 200. It should be understood in this specification 
that "irreversible control voltage" is a voltage which, once changed from 
an original value to a new value is then permanently fixed to this new 
value, that is to say, the value never reverts back to the original 
potential. This will be explained in more detail with reference to the 
embodiments. 
Referring to FIGS. 2 and 3, there are shown circuit diagrams of a typical 
generator 300 for producing an irreversible control voltage. 
The generator shown in FIG. 2 is shown per se and has complementary MOS 
structure (hereinafter referred to as "C-MOS"). 
Between a power supply terminal V.sub.DD and a power supply terminal 
V.sub.SS (ground potential) are serially connected a current path of a 
p-channel MOS transistor 1 and a fuse element 2 made of an electrically or 
thermally blowable polysilicon connection layer, metal connection layer, 
etc. The gate of a MOS transistor 1 is connected to the terminal V.sub.SS. 
p- and n-channel MOS transistors 3 and 4 have their current paths 
connected in series between the terminal V.sub.DD and V.sub.SS and their 
gates connected to a junction or a node of the MOS transistor 1 and fuse 
element 2. An irreversible control voltage V.sub.O is derived at the 
junction between the C-MOS transistors 3 and 4. 
In the circuit as shown, if the fuse element 2 is not yet burned out, then 
the MOS transistor 3 is turned on and the MOS transistor 4 is turned off, 
causing the output voltage V.sub.O to become a voltage V.sub.H (high 
level) on the V.sub.DD side. If the fuse element 2 is burned out by 
directing a laser beam at the fuse element or flowing a large current 
therethrough, the MOS transistor 3 is turned off and the MOS transistor 4 
is turned on, causing the output voltage V.sub.O to become a voltage 
V.sub.L (low level). With the fuse element 2 once blown out, it cannot be 
returned to the original state. That is, if the output voltage V.sub.O is 
changed into the voltage V.sub.L it is not possible to change it into the 
voltage V.sub.H. Thus, it follows that a change from the voltage V.sub.H 
to the voltage V.sub.L is a so-called "irreversible voltage change". 
The generator shown in FIG. 3 is also shown per se and has an 
enhancement/depletion structure (hereinafter referred to as "E/D"). In the 
circuit shown, the current paths of a depletion mode MOS transistor 11 and 
fuse element 12 are series-connected between a power supply terminal 
V.sub.DD and a power supply terminal V.sub.SS. The gate of the MOS 
transistor 11 is connected to a junction, or a node of the MOS transistor 
11 and fuse element 12. The current paths of a depletion mode MOS 
transistor 13 and enhancement mode or type MOS transistor 14 are connected 
in series between the power supply terminal V.sub.DD and the power supply 
terminal V.sub.SS. The gate of one (i.e. the MOS transistor 14) of the MOS 
transistors 13 and 14 is connected to the junction mentioned. An 
irreversible control voltage V.sub.O is taken as an output from the 
junction of the MOS transistors 13 and 14. 
If the fuse element 12 is not yet burned out, the MOS transistor 14 is 
turned off and an output voltage V.sub.O becomes a voltage V.sub.H (high 
level) on the V.sub.DD side. With the fuse element 12 burned out, the MOS 
transistor 14 is turned on and the output voltage V.sub.O becomes a 
voltage V.sub.L (low level) on the V.sub.SS side. In this case also, once 
the fuse element is burned out, it is not returned to the original state. 
With a change from the voltage V.sub.H to the voltage V.sub.L back is not 
possible to change it to the voltage V.sub.H. The change is an 
irreversible change. Consequently, the resulting output voltage derived 
from this generator is an example of an "irreversible control voltage" as 
that term is used in this specification. 
FIG. 4 shows a circuit diagram of a known C-MOS inverter corresponding to 
the circuit 100 in FIG. 1. The C-MOS inverter as shown in FIG. 4 comprises 
a p-channel MOS transistor Qp1 having its source connected to a V.sub.DD 
supply terminal, its drain connected to an output Vout and its gate 
electrode adapted to receive an input signal Vin as a gate input signal, 
and an n-channel MOS transistor Qn1 having its source connected to a 
V.sub.SS supply terminal, its drain connected to the above-mentioned Vout, 
and its gate electrode adapted to receive the above-mentioned input signal 
Vin. 
Table 1 shows the relation between the input voltage Vin and the output 
voltage Vout, and is analogous to the ordinary truth table where the 
voltages are represented by the logical values "1" and "0". Accordingly, 
it will be called "a truth table". 
TRUTH TABLE 1 
______________________________________ 
Vout 
______________________________________ 
Vin H L 
L H 
______________________________________ 
In connection with this truth table, the definition on "H" and "L" is 
given: 
"H" is the voltage which has logically "High" level, and 
"L" is the voltage which has logically "Low" level. 
Now the circuit diagrams shown in FIG. 5 through FIG. 8 represent a part of 
the embodiment according to the invention. It can be easily seen from 
these circuit diagrams that they represent the combination of circuit 
arrangements 100 and 200 in FIG. 1, with the generator 300 omitted. 
This MOS logic circuit, as shown in FIG. 5, according to an embodiment of 
this invention includes a known C-MOS inverter consisting of MOS 
transistors Qp1 and Qn1, the drains of which are mutually connected to 
form a node for the output terminal Vout, the source of which transistor 
Qp1 is connected to one of the supply terminals V.sub.DD, and both gate 
electrodes of which are mutually connected together to receive the input 
signal Vin, and an additional n-channel MOS transistor Qn2. In this 
circuit, the transistor Qn2 corresponding to the control circuit 200 in 
FIG. 1, has its drain connected to the source of the MOS transistor Qn1, 
its source connected to one of the supply terminals V.sub.SS, and its gate 
electrode connected to the output voltage V.sub.O (=irreversible voltage) 
of the generator 300 in FIG. 1, such as the actual generator in FIG. 2. 
Namely, the drain to source current path or channel of the MOS transistor 
Qn2 is connected to the node for the output terminal Vout through that of 
the MOS transistor Qn1. Each gate electrode of both MOS transistors Qp1 
and Qn1 is mutually connected together to the signal input terminal Vin, 
the same as is done in FIG. 4 with a known C-MOS inverter, and the source 
of transistor Qp1 is connected to the other of the supply terminals 
V.sub.DD. Here, the same reference numerals as shown in FIG. 4 will be 
employed to denote the same circuit elements corresponding to those shown 
in the following Figures. In the operation of the circuit as shown in FIG. 
5, when V.sub.O =V.sub.H, the MOS transistor Qn2 is always turned on and 
at this time the logical relation is as shown in Truth Table 2, i.e. the 
same as in an ordinary C-MOS inverter. When V.sub.O =V.sub.L, the MOS 
transistor Qn2 is always turned off. With the input signal Vin at the "L" 
level, the MOS transistor Qp1 turns on and thus an output signal Vout 
becomes an "H" level. With Vin at the high level, the output Vout becomes 
a high impedance condition, i.e. the "undefined" or "indeterminate" state. 
TRUTH TABLE 2 
______________________________________ 
Vout 
V.sub.O =V.sub.H 
V.sub.O =V.sub.L 
______________________________________ 
Vin H L X 
(indeterminate) 
L H H 
______________________________________ 
It should be noted that "V.sub.H " of the irreversible voltage is the 
voltage of which level is logically "High", and "V.sub.L " is the voltage 
of which level is logically "Low". 
FIG. 6 shows a MOS logic circuit according to a modified form of the 
first-explained embodiment. Although in the first embodiment an n-channel 
MOS transistor for receiving the irreversible voltage V.sub.O as a gate 
input signal has been connected in series with the n-channel MOS 
transistor Qn1 of the C-MOS inverter, a source-drain current path of a 
p-channel MOS transistor Qp2 is additionally inserted between the node 
through that of the p-channel MOS transistor Qp1 and supply terminal 
V.sub.DD and the output voltage V.sub.O of the circuit 300 as shown in 
FIG. 1 is applied to the gate of the MOS transistor Qp2. In this 
embodiment, when the irreversible control voltage V.sub.O =V.sub.L, the 
MOS transistor is always turned on, and the logic function is as shown in 
Table 3, i.e. the same as in an ordinary C-MOS inverter. At V.sub.O 
=V.sub.H, the MOS transistor Qp2 is always turned off. With an input Vin 
at the "H" level, the MOS transistor Qn1 turns on, the output signal Vout 
becomes an "L" level. With Vin at the "L" level, the output Vout becomes 
similarly a high impedance state and thus the "indeterminate" state as 
shown in Truth Table 3. 
TRUTH TABLE 3 
______________________________________ 
Vout 
V.sub.O =V.sub.L 
V.sub.O =V.sub.H 
______________________________________ 
Vin H L L 
L H X 
______________________________________ 
FIGS. 7 and 8, each, show a MOS logic circuit according to another 
modification of the before-mentioned embodiments, by which the "undefined" 
or "indeterminate" state can be eliminated. In the modification as shown 
in FIG. 7 an n-channel MOS transistor Qn2 is inserted the same as in the 
embodiment of FIG. 5 and additionally a source-drain current path, or 
channel of a p-channel MOS transistor Qp3 is series-connected between the 
output terminal Vout and the supply terminal V.sub.DD to permit the output 
voltage V.sub.O of the generator 300 as shown in FIG. 1 to be applied in 
parallel to both gate electrodes of the MOS transistors Qn2 and Qp3. At 
V.sub.O =V.sub.H the MOS transistor Qn2 is turned on and the MOS 
transistor Qp3 is turned off, performing a logical operation as in an 
ordinary C-MOS inverter. When V.sub.O =V.sub.L, the MOS transistor Qn2 is 
turned off, interrupting the current path from Vout to V.sub.SS, and the 
MOS transistor Qp3 is turned on, establishing a current path from V.sub.DD 
to Vout. As a result, a logic function of this circuit is as shown in 
Truth Table 4. 
TRUTH TABLE 4 
______________________________________ 
Vout 
V.sub.O =V.sub.H 
V.sub.O =V.sub.L 
______________________________________ 
Vin H L H 
L H H 
______________________________________ 
In the modification the shown in FIG. 8, a p-channel MOS transistor Qp2 is 
provided as same as in the modification of FIG. 6, and additionally a 
drain-source current path of an n-channel MOS transistor Qn3 is 
series-connected between the node or the output terminal Vout and the 
output terminal V.sub.SS. The irreversible voltage V.sub.O of the 
generator 300 as shown in FIG. 1 is applied in parallel to both gate 
electrodes of the MOS transistors Qp2 and Qn3, and the logic function of 
the circuit is as shown in Truth Table 5. 
TRUTH TABLE 5 
______________________________________ 
Vout 
V.sub.O =V.sub.L 
V.sub.O =V.sub.H 
______________________________________ 
Vin H L L 
L H L 
______________________________________ 
Next a MOS logic circuit having two or more input terminals will be 
explained. 
Before proceeding with the description on the two-input MOS logic circuit 
according to this invention, a known two-input C-MOS NAND gate will be 
described below with reference to FIG. 9. 
In the circuit of FIG. 9 p-channel MOS transistors Qp4 and Qp5 have their 
source-drain current paths connected in parallel between a terminal 
V.sub.DD and a node or an output Vout and are adapted to receive input 
signals Vin1 and Vin2 as gate input signals, respectively. N-channel MOS 
transistors Qn4 and Qn5 have their drain-source current paths connected in 
series between the node or the output Vout and a terminal V.sub.SS and are 
adapted to receive the input signals Vin1 and Vin2 as gate input signals. 
The logic function of this circuit is as indicated in Truth Table 6. 
TRUTH TABLE 6 
______________________________________ 
Vin1 
H L 
______________________________________ 
Vin2 H L H 
L H H 
______________________________________ 
FIG. 10 shows a circuit diagram of a MOS logic circuit embodying this 
invention by utilizing the two-input C-MOS NAND gate of FIG. 9. In this 
circuit, the drain-source current path of an additional p-channel MOS 
transistor Qp6 is series-connected between the supply terminal V.sub.DD 
and output terminal Vout through that of the MOS transistor Qp5. The 
irreversible control voltage V.sub.O of generator 300 of FIG. 1 is applied 
to the gate electrode of the MOS transistor Qp6. In this circuit, at 
V.sub.O =V.sub.L the MOS transistor Qp6 is always turned on and, 
therefore, a current path leading from V.sub.DD to Vout through the 
transistors Qp6 and Qp5 is determined by the ON-OFF control of the MOS 
transistor Qp5. At this time, the logic function is as shown in Truth 
Table 7, i.e. the same as in an ordinary two-input C-MOS NAND gate. When 
V.sub.O =V.sub.H, the MOS transistor Qp6 is always turned off. With MOS 
transistor Qp4 turned off and the MOS transistor Qp5 on, that is, with 
Vin1=an H level and Vin2=an L level, a current path from V.sub. DD to Vout 
is interrupted and also a current path from V.sub.SS to Vout is 
interrupted, causing the output Vout to come to a high impedance state. 
The output Vout becomes an "indeterminate" state as shown in Truth Table 
7. 
TRUTH TABLE 7 
______________________________________ 
V.sub.O =V.sub.L 
V.sub.O =V.sub.H 
Vin1 Vin1 
H L H L 
______________________________________ 
Vin2 H L H L H 
L H H X H 
______________________________________ 
FIG. 11 shows a modified form of the embodiment as shown in FIG. 10, 
eliminating the "indeterminate" state of the logic from it. The circuit of 
FIG. 11 employs an additional a MOS transistor Qp6 and an n-channel MOS 
transistor Qn6. The source-drain current path of transistor Qp6 is 
series-connected between the supply terminal V.sub.DD and the output 
terminal V.sub.DD through the source-drain current path of transistor Qp5. 
The source-drain current path of transistor Qn6 is connected in parallel 
with that of transistor Qn5, and the gate electrodes of transistors Qp6 
and Qn6 are mutually connected to receive the irreversible control voltage 
from the generator 300 in FIG. 1. In this circuit, when V.sub.O =V.sub.L 
the MOS transistor Qn6 is always turned off and the MOS transistor Qp6 is 
always turned on. In this case, the logic function is as shown in Truth 
Table 8, i.e. the same as in an ordinary two-input C-MOS NAND gate. With 
V.sub.O =V.sub.H, the MOS transistor Qn6 is always turned on. If under 
this condition, the MOS transistor Qn4 is turned on (Vin1="H" level), a 
current path from Vout to V.sub.SS is established. On the other hand, 
since the MOS transistor Qp6 is always turned off, when Vin2 becomes an L 
level, a current path from V.sub.DD to Vout is not created even if MOS 
transistor Qp5 is turned on. The logic function of the MOS logic circuit 
is as shown in Truth Table 8. 
TRUTH TABLE 8 
______________________________________ 
V.sub.O =V.sub.L 
V.sub.O =V.sub.H 
Vin1 Vin1 
H L H L 
______________________________________ 
Vin2 H L H L H 
L H H L H 
______________________________________ 
FIG. 12 shows a circuit diagram of a MOS logic circuit embodying this 
invention by utilizing a two-input C-MOS NOR gate. A drain-source current 
path of an n-channel MOS transistor Qn9 for receiving V.sub.O as a gate 
input signal is inserted between a V.sub.SS supply terminal and the output 
node Vout through the source-drain current path of an n-channel MOS 
transistor Qn8 which, together with an n-channel MOS transistor Qn7 and 
p-channel MOS transistors Qp7 and Qp8, constitutes an ordinary NOR gate. 
When V.sub.O =V.sub.H, the MOS transistor Qn9 is always turned on and the 
logic function of Vout to Vin1 and Vin2 is the same as in the ordinary 
two-input C-MOS NOR gate, as shown in Truth Table 9 below. It V.sub.O 
=V.sub.L, the MOS transistor Qn9 is always turned off. With the MOS 
transistor Qn7 OFF and MOS transistor Qn8 ON, i.e. with Vin1=an L level 
and Vin2=an H level, a current path from Vout to V.sub.SS, as well as a 
current path from V.sub.DD to Vout, are cut off and thus the output Vout 
becomes a high impedance state, i.e. an indeterminate state as indicated 
in Truth Table 9. 
TRUTH TABLE 9 
______________________________________ 
V.sub.O =V.sub.H 
V.sub.O =V.sub.L 
Vin1 Vin1 
H L H L 
______________________________________ 
Vin2 H L L L X 
L L H L H 
______________________________________ 
FIG. 13 shows a MOS logic circuit according to a modified form of the 
embodiment of FIG. 12, in which the indeterminate state of the logic of 
the above-mentioned embodiment can be eliminated. In this MOS logic 
circuit, a MOS transistor Qn9 is inserted. The drain-source current path 
of p-channel transistor Qp9 is connected in parallel with that of a MOS 
transistor Qp7, and V.sub.O is supplied to the gate electrode of the MOS 
transistor Qp9. When V.sub.O =V.sub.L, the MOS transistor Qp9 is always 
turned on. With the MOS transistor Qp8 turned on, a current path from the 
terminal V.sub.DD to an output Vout is established. As the MOS transistor 
Qn9 is always turned off even if Vin2 becomes an H level and MOS 
transistor Qn8 is turned on, a current path from the output Vout to 
V.sub.SS is not established. Therefore, the logic function of this circuit 
is as indicated in Truth Table 10 below. 
TRUTH TABLE 10 
______________________________________ 
V.sub.O =V.sub.H 
V.sub.O =V.sub.L 
Vin1 Vin1 
H L H L 
______________________________________ 
Vin2 H L L L H 
L L H L H 
______________________________________ 
FIG. 14 shows a MOS logic circuit according to another embodiment this 
invention. This circuit includes an ordinary C-MOS OR type delay circuit 
comprising a p-channel MOS transistor Qp10 having its source-drain current 
path connected between one of the supply terminal V.sub.DD and a node N1 
and its gate connected to another supply terminal V.sub.SS and acting as a 
load transistor. Three n-channel MOS transistors Qn10, Qn11 and Qn12 have 
their drain-source current paths connected in parallel between the node N1 
and the terminal V.sub.SS, and are adapted to receive gate input signals 
Vin1, Vin2 and Vin3, respectively. These transistors serve as driver 
transistors. A C-MOS inverter I1 is provided for inverting a signal on the 
node N1 to obtain an output signal Vout, and the drain-source current path 
of an n-channel MOS transistor Qn13 is series-connected with MOS 
transistor Qn12 between the node N1 and the terminal V.sub.SS. The gate 
electrode of transistor Qn13 is adapted to receive the irreversible 
voltage V.sub.O as a gate input signal. 
It should be noted that the meaning of the "load transistor" should be 
understood in this specification as referring to a transistor for which 
the gate electrode is connected to the source, the drain thereof to one of 
a pair of supply terminals V.sub.DD, V.sub.SS and which is usually turned 
on, and also that of a "driver transistor" should be considered a 
transistor for which the gate electrode is connected to a signal input 
terminal. 
Now assuming that in this circuit the irreversible control voltage V.sub.O 
is at a level V.sub.H, the MOS transistor Qn13 is always turned on. If in 
this case any one of the signals Vin1, Vin2 and Vin3 becomes an H level, 
an output signal Vout becomes an H level after a given delay time, and 
thus this circuit works as a three-input OR type delay circuit. It is to 
be noted here that the ratio of conductance of the three n-channel MOS 
transistors Qn10, Qn11 and Qn12 to that of a p-channel MOS transistor Qp10 
should be predetermined to have, even if any of the three n-channel MOS 
transistors Qn10, Qn11 and Qn12 is turned on, "drivability" enough to 
effect a signal inversion of the inverter I1 from V.sub.L to V.sub.H. When 
V.sub.O =V.sub.L, the MOS transistor Qn13 is turned off. In this case, 
even if any signal is supplied as a gate input signal Vin3 to the gate 
electrode of the MOS transistor Qn12 connected in series with the MOS 
transistor Qn13, no influence is given to the node N1 and thus the circuit 
as a whole serves as a two-input OR type delay circuit. As appreciated 
from the above, the circuit of this embodiment serves as a three-input or 
a two-input OR type delay circuit (i.e. two kinds of logic functions). 
FIG. 15 shows a MOS logic circuit according to another embodiment of this 
invention, in which a C-MOS AND type delay circuit is utilized. This 
circuit includes an ordinary C-MOS AND type delay circuit constituted by 
an n-channel MOS transistor Qn14 having its drain-source current path 
connected between a node N2 and a terminal V.sub.SS, its gate electrode 
connected to a terminal V.sub.DD and functioning as a load transistor. 
Three p-channel transistors Qp11, Qp12 and Qp13 have their source-drain 
current paths connected in parallel between the terminal V.sub.DD and the 
node N2 and their gate electrodes connected to receive input signals Vin1, 
Vin2 and Vin3, respectively. These transistors serve as a driver 
transistor. A C-MOS inverter 12 is provided for inverting a signal on the 
node N2 to obtain an output signal Vout, and p-channel MOS transistor Qp14 
is additionally series connected with its drain-source current path to 
that of the MOS transistor Qp13 between the node N2 and the supply 
terminal V.sub.DD. The gate electrode of transistor Qp14 is connected to 
receive the irreversible control voltage. 
When the irreversible control voltage V.sub.O is equal to V.sub.L, the MOS 
transistor Qp14 is always turned on. If any one of the input signals Vin1, 
Vin2 and Vin3 are an L level, an output signal Vout becomes an L level. It 
should be noted, however, that the ratio of the conductance of the three 
p-channel MOS transistors Qp11, Qp12 and Qp13 to that of the n-channel MOS 
transistor Qn14 should be initially determined to have, even if any of the 
p-channel MOS transistors Qp11, Qp12 and Qp13 is turned on, such 
drivability so as to invert an input signal of the inverter I2. When, on 
the other hand, V.sub.O =V.sub.H, the MOS transistor Qp14 is turned off. 
Even if an input signal of any level is supplied as a gate input signal 
Vin3 to the gate electrode of the MOS transistor Qp13 connected in series 
with the MOS transistor Qp14, no influence is given to the node N2 and the 
circuit acts as a two-input (Vin1 and Vin2) AND type delay circuit. The 
logic functions of this circuit can be chosen to be either a three-input 
or two-input AND type delay circuit by controlling the irreversible 
voltage V.sub.O. 
FIG. 16 shows a MOS logic circuit of another embodiment according to this 
invention, in which an ordinary C-MOS exclusive OR type circuit is used. 
This MOS logic circuit includes an ordinary C-MOS exclusive-OR gate 
comprising a p-channel MOS transistor Qp15 having its source-drain current 
path series-connected between a terminal V.sub.DD and a node N3 and its 
gate connected to a terminal V.sub.SS and serving as a load transistor; 
and three n-channel MOS transistors Qn15, Qn16 and Qn17 having their 
drain-source current paths connected in series between the node N3 and the 
terminal V.sub.SS and their gate electrodes connected to receive input 
signals Vin1, Vin2 and Vin3, respectively, and acting as driver 
transitors. Furthermore, the circuit of FIG. 16 includes three n-channel 
MOS transistors Qn18, Qn19 and Qn20 connected in series between the node 
N3 and the supply terminal V.sub.SS with their gate electrodes connected, 
respectively, through C-MOS inverters I3, I4 and I5 to receive input 
signals Vin1, Vin2 and Vin3; and a C-MOS inverter I6 connected between the 
node N3 and the output terminal Vout for inverting an input on the node N3 
to obtain an output signal Vout. An n-channel MOS transistor Qn21 having 
drain-source current path is connected in parallel with that the MOS 
transistor Qn17 is connected to receive the irreversible control voltage 
V.sub.O as a gate input signal, and an n-channel MOS transistor Qn22 
having its drain-source current path connected parallel to that of the MOS 
transistor Qn20 is also connected to receive the V.sub.O as a gate input. 
When V.sub.O =V.sub.L in this circuit, the MOS transistors Qn21 and Qn22 
are always turned off and therefore the circuit of this embodiment works 
as a three-input Exclusive-OR circuit. When V.sub.O =V.sub.H, the MOS 
transistors Qn21 and Qn22 are always turned on and the input signal Vin3 
cannot give influence to their operations. That is, transistors Qn17 and 
Qn20 are short-circuited by the transistors Qn21 and Qn22, respectively. 
In this case, the circuit of the embodiment acts as a two-input 
Exclusive-OR circuit. 
FIG. 17 is a circuit diagram of a C-MOS logic circuit of another embodiment 
according to this invention, in which two kinds of logic circuits 
(functions) are realized: a NOR gate and a NAND gate. In this circuit, two 
p-channel MOS transistors Qp16 and Qp17 have their source-drain current 
paths connected in series between one terminal V.sub.DD and the node for 
the output Vout and are adapted to receive input signals Vin1 and Vin2 as 
gate input signals, respectively. Two n-channel MOS transistors Qn23 and 
Qn24 have their drain-source current paths connected in series between the 
node for the output Vout and the other terminal V.sub.SS and are adapted 
to receive input signals Vin1 and Vin2 as gate input signals. As a result, 
a series arrangement of the p-channel transistors Qp16 and Qp17 and 
n-channel transistors Qn23 and Qn24 is connected in series between a pair 
of the supply terminals V.sub.DD and V.sub.SS. This circuit further 
includes a series arrangement connected between a pair of the supply 
terminals V.sub.DD and V.sub.SS of p-channel transistors Qp19 and Qp20 as 
well as n-channel transistors Qn26 and Qn27, both gate electrodes of which 
transistors Qp19 and Qn26 are connected to that of transistor Qp17 and 
Qn24, and both drains of which are connected to the node for the output 
Vout. Finally the circuit of FIG. 17 includes a p-channel transistor Qp18 
having a source-drain current path connected parallel to that of the 
transistor Qp17, and an n-channel transistor Qn25 having a drain-source 
current path connected parallel to that of the transistor Qn24, each gate 
electrode of which being mutually connected to that of transistors Qp20 
and Qn27, respectively, to receive the irreversible control voltage 
V.sub.O derived from the generator 300 in FIG. 1. 
When the irreversible control voltage V.sub.O is at the level V.sub.L, the 
n-channel MOS transistors Qn25 and Qn27 are always turned off. A current 
path from Vout to V.sub.SS is created by a series circuit of the n-channel 
MOS transistors Qn23 and Qn24 connected to receive input signals Vin1 and 
Vin2 as gate input signals. Simultaneously, since the p-channel MOS 
transistors Qp18 and Qp20 are turned on, the current paths from V.sub.DD 
to Vout are established in parallel with one through the p-channel MOS 
transistor Qp16 and one through the p-channel MOS transistor Qp19, the MOS 
transistors Qp16 and Qp19 being connected to receive the input signals 
Vin1 and Vin2 as gate input signals. Thus, the circuit serves as an 
ordinary C-MOS NAND gate. On the other hand, since at V.sub.O =V.sub.H the 
n-channel MOS transistors Qn25 and Qn27 are always turned on, two current 
paths from Vout to V.sub.SS are created in parallel with one through the 
n-channel MOS transistor Qn23 and one through the n-channel MOS transistor 
Qn26, the gate electrodes of the MOS transistors Qn23 and Qn26 being 
connected to receive the input signals Vin1 and Vin2, respectively. 
Simultaneously, when the V.sub.O =V.sub.H, the p-channel MOS transistors 
Qp18 and Qp20 are always turned off and thus a current path from Vout to 
V.sub.DD is constituted by a series circuit of the p-channel MOS 
transistors Qp16 and Qp17 for receiving the input signals Vin1 and Vin2 as 
gate input signals, respectively. Thus, the circuit functions in the same 
way as an ordinary C-MOS NOR gate. As a result, the circuit has two kinds 
of logic functions under the control of V.sub.O, as shown in Truth Table 
11 below. 
TRUTH TABLE 11 
______________________________________ 
V.sub.O =V.sub.H 
V.sub.O =V.sub.L 
Vin1 Vin1 
H L H L 
______________________________________ 
Vin2 H L L L H 
L L H H H 
______________________________________ 
Kinds of NOR NAND 
logics 
______________________________________ 
So far the C-MOS type logic circuits have been explained in connection with 
the embodiments and modified embodiments. Enhancement/Depletion type logic 
circuits will now be explained in which a depletion type MOS transistor is 
used as the load transistor and an enhancement type MOS transistor is used 
as a driver transistor. 
FIGS. 18 and 23 each show a MOS logic circuit according to the embodiments 
of this invention in which an ordinary E/D type MOS logic circuit is used. 
The MOS logic circuit as shown in FIG. 18 includes the ordinary E/D type 
inverter comprising a depletion type MOST transistor Q.sub.D1 having its 
source-drain current path, or channel connected between one of the supply 
terminals V.sub.DD and an output Vout and its gate electrode connected to 
Vout Thus, transistor Q.sub.D1 serves as a load transistor. An enhancement 
type MOS transistor Q.sub.E1 having its source-drain current path 
connected between the other supply terminal V.sub.SS (through enhancement 
type transistor Q.sub.E2) and the output Vout and its gate electrode 
connected to receive an input signal Vin, serves as a driver transistor. 
The drains of transistors Q.sub.D1 and Q.sub.E2 serve the node for the 
output terminal Vout. It further includes as the control circuit 200 in 
FIG. 1 an enhancement type MOS transistor Q.sub.E2, the drain-source 
current path of which being connected between the source of the MOS 
transistor Q.sub.E1 of the inverter and the supply terminal V.sub.SS and 
the gate electrode of which being connected to the output voltage V.sub.O 
of the irreversible control circuit 300 in FIG. 1 (e.g. the actual 
generator circuit shown in FIG. 3). 
When V.sub.O =V.sub.H in this circuit, the MOS transistor Q.sub.E2 is 
always turned on. When the input signal Vin becomes an H level, the MOS 
transistor Q.sub.E1 is turned on and the output Vout becomes a low voltage 
level i.e., the L level as determined by a ratio between the series 
conductance of the MOS transistors Q.sub.E1, Q.sub.E2 and the conductance 
of the MOS transistor Q.sub.D1. While, on the other hand, the input signal 
Vin becomes L level, the MOS transistor Q.sub.E1 is turned off, causing 
the output Vout to become an H level. Then, when V.sub.O =V.sub.L, the MOS 
transistor Q.sub.E2 is always turned off, causing the output Vout to 
always become the H level independent of the input signal Vin. 
Consequently, the circuit has two kinds of the logical functions, as 
indicated in Truth Table 12, under the control of the irreversible voltage 
V.sub.O. 
TRUTH TABLE 12 
______________________________________ 
Vout 
V.sub.O =V.sub.H 
V.sub.O =V.sub.L 
______________________________________ 
Vin H L H 
L H H 
______________________________________ 
FIG. 19 is a modified form of the above-mentioned embodiment. In this 
circuit, a drain-source current path of a MOS transistor Q.sub.E2 is 
inserted between an output Vout, through the source-drain current path of 
the transistor Q.sub.E1 and terminal V.sub.SS, and a drain-source current 
path of a depletion type MOS transistor Q.sub.D2 is connected between the 
node Vout, through the source-drain current path of the depletion type MOS 
transistor Q.sub.D1, and the supply terminal V.sub.DD, a voltage V.sub.O 
being supplied to the gate electrodes of the MOS transistors Q.sub.E2, 
Q.sub.D2. 
It should be noted here that the voltage "V.sub.O '" is set to either a 
value "V.sub.H '" greater than the threshold value of the enhancement type 
MOS transistor Q.sub.E2, or a value "V.sub.L '" less than the threshold 
value of the depletion type MOS transistor Q.sub.D2. 
When V.sub.O '=V.sub.H ' in this circuit, the MOS transistors Q.sub.E2 and 
Q.sub.D2 are both turned on and thus the circuit is operated the same as 
in an ordinary E/D type inverter. When, on the other hand, V.sub.O 
'=V.sub.L ', the MOS transitors Q.sub.E2 and Q.sub.d2 are both turned off, 
cutting off two current paths, one between Vout and V.sub.DD and other 
between Vout and V.sub.SS. As a result, the output terminal Vout becomes a 
high impedance state, i.e. an indeterminate state. Consequently, the 
circuit has two kinds of logical functions, as indicated in Truth Table 
13, under the control of the irreversible voltage. 
TRUTH TABLE 13 
______________________________________ 
Vout 
V.sub.O '=V.sub.H ' 
V.sub.O '=V.sub.L ' 
______________________________________ 
Vin H L X 
L H X 
______________________________________ 
FIG. 20 shows a MOS logic circuit according to an embodiment of this 
invention, using an ordinary E/D type NAND gate. The circuit includes the 
ordinary E/D type NAND gate comprising a depletion type MOS transistor 
Q.sub.D3 having its source-drain current path connected between a V.sub.DD 
supply terminal and an output Vout and its gate electrode connected to 
Vout for serving as a load transistor, and two enhancement type MOS 
transistors Q.sub.E3 and Q.sub.E4 having their drain-source current paths 
connected in series between the output Vout and a terminal V.sub.SS and 
their gates connected to receive input signals Vin1 and Vin2, 
respectively, and serving as driving transistors. The drain-source current 
path of an enhancement type MOS transistor Q.sub.E5 is connected in 
parallel with that of the MOS transistor Q.sub.E3 and the gate electrode 
thereof is connected to receive the output voltage V.sub.O of the 
generator 300. With V.sub.O =V.sub.L, the MOS transistor Q.sub.E5 is 
always turned off and, only when input signals Vin1 and Vin2 become the H 
levels, the output Vout becomes an L level. In this way, the circuit works 
as the ordinary NAND gate. When, on the other hand, V.sub.O =V.sub.H, the 
MOS transistor Q.sub.E5 is always turned on. In this case, the output Vout 
becomes irrelevant to the signal Vin2 and the circuit works merely as an 
inverter for Vin1. As a consequence, the circuit has two kinds of logical 
functions, as shown in Truth Table 14, on account of the presence of 
V.sub.O. 
TRUTH TABLE 14 
______________________________________ 
V.sub.O =V.sub.L 
V.sub.O =V.sub.H 
Vin1 Vin1 
H L H L 
______________________________________ 
Vin2 H L H L H 
L H H L H 
______________________________________ 
FIG. 21 shows a MOS logic circuit according to another embodiment of this 
invention, using an ordinary E/D type NOR gate. This circuit includes the 
ordinary E/D type NOR circuit comprising a depletion type MOS transistor 
Q.sub.D4 having its source-drain current path connected between one 
terminal V.sub.DD and a node for an output Vout and its gate electrode 
connected to the node for the output Vout and functioning as a load 
transistor, two enhancement type MOS transistors Q.sub.E6 and Q.sub.E7 
having their drain-source current paths connected in parallel between the 
node for the output Vout and the other terminal V.sub.SS and their gate 
electrodes connected to receive input signals Vin1 and Vin2, respectively, 
and functioning as driver transistors, and an enhancement type MOS 
transistor Q.sub.E8 having its drain-source current path connected between 
the node, through the source-drain current path of the MOS transistor 
Q.sub.E7, and the other terminal V.sub.SS and its gate electrode connected 
to the irreversible control voltage V.sub.O of the generator 300 as shown 
in FIG. 1. 
With V.sub.O =V.sub.H and thus the MOS transistor Q.sub.E8 turned on, this 
MOS logic circuit acts as an ordinary NOR gate. Since in this case the two 
MOS transistors Q.sub.E7 and Q.sub.E8 are connected in series between Vout 
and V.sub.SS, it is necessary to determine properly the conductance ratio 
of the transistor Q.sub.D4 to the series-connected transistors Q.sub.E7 
and Q.sub.E8 in order that when the transistor Q.sub.E7 is turned on upon 
receipt of an "H" level signal of Vin2, the level of the output Vout can 
become low. With V.sub.O =V.sub.L and the MOS transistor Q.sub.E8 turned 
off, the output Vout is determined by the input signal Vin1 irrespective 
of the input signal Vin2, and when the input signal Vin1 becomes an "H" 
level or an "L" level, the output Vout becomes an "L" level or an "H" 
level, respectively. In this case, the circuit works merely as an 
inverter. As a consequence, the circuit has two kinds of logic functions, 
as shown in Truth Table 15 owing to V.sub.O. 
TRUTH TABLE 15 
______________________________________ 
V.sub.O =V.sub.H 
V.sub.O =V.sub.L 
Vin1 Vin1 
H L H L 
______________________________________ 
Vin2 H L L L H 
L L H L H 
______________________________________ 
FIG. 22 shows a MOS logic circuit according to an embodiment of this 
invention. This circuit includes firstly an ordinary three-input E/D type 
Exclusive-OR gate comprising a depletion type MOS transistor Q.sub.D5 
functioning as a load transistor, having its a source-drain current path 
connected between one terminal V.sub.DD and a node N4 and its gate 
electrode connected to the node N4; and three depletion type MOS 
transistor Q.sub.E9, Q.sub.E10 and Q.sub.E11 functioning as driver 
transistors having their drain-source current paths connected in series 
between the node N4 and the other terminal V.sub.SS and their gate 
electrodes connected to receive input signals Vin1, Vin2 and Vin3, 
respectively, and secondly three depletion type MOS transistors Q.sub.E12, 
Q.sub.E13 and Q.sub.E14 functioning as driver transistors having their 
drain-source current paths connected in series between the node N4 and the 
other terminal V.sub.SS and their gate electrodes connected, respectively, 
via E/D type inverters I7, I8 and I9 to receive input signals Vin1, Vin2 
and Vin3 thirdly an E/D type inverter I10 for inverting a signal on the 
node N4 to obtain an output signal Vout; and fourthly, two enhancement 
type MOS transistors Q.sub.E15 and Q.sub.E16 having their drain-source 
current paths connected in parallel with that of the transistors Q.sub.E11 
and Q.sub.E14, respectively, and their gate electrodes connected together 
to receive the irreversible control voltage V.sub.O derived from the 
generator 300 in FIG. 1. With V.sub.O =V.sub.L and thus the MOS 
transistors Q.sub.E15 and Q.sub.E16 turned off, an output Vout becomes an 
"H" level if the input signals Vin1, Vin2 and Vin3 become all the "H" 
levels or the "L" levels. In this case, the circuit serves as an ordinary 
three-input exclusive OR gate logic circuit. It is to be noted here that, 
if one series-arrangement of the three MOS transistors Q.sub.E9 to 
Q.sub.E11 or three MOS transistors Q.sub.E12 to Q.sub.E14 is turned on, it 
is necessary to initially determine a ratio between the series conductance 
of the three enhancement type MOS transistors and the conductance of the 
depletion type MOS transistor Q.sub.D5 to have enough drive to invert the 
input of the inverter I10. 
With V.sub.O =V.sub.H and the MOS transistors Q.sub.E15 and Q.sub.E16 both 
turned on, the input signal Vin3 has no relevancy to the operation of the 
other input circuits. In other words, both transistors Q.sub.E11 and 
Q.sub.E14 to which gate electrodes the input signal Vin3 is applied are 
short-circuited by those transistors Q.sub.E15 and Q.sub.E16, 
respectively. In this case, the circuit works as a two-input (Vin1 and 
Vin2) Exclusive-OR gate logic circuit. 
FIG. 23 shows an E/D MOS logic circuit according to another embodiment of 
this invention, whose logic function can be changed between a NOR gate and 
a NAND gate This MOS logic circuit includes an Exclusive-OR gate 
comprising a depletion type MOS transistor Q.sub.D6 functioning as a load 
transistor having its source-drain current path connected between one 
terminal V.sub.DD and a node for an output Vout and its gate electrode 
connected to the node; two enhancement type MOS transistors Q.sub.E17 and 
Q.sub.E18 functioning as driver transistors having their drain-source 
current paths series-connected between the node for the output Vout and 
the other terminal V.sub.SS and their gate electrodes connected to receive 
input signals Vin1 and; Vin2, respectively, and an enhancement type MOS 
transistor Q.sub.E20 having its gate electrode connected to receive the 
input signal Vin2; and further two enhancement type transistors Q.sub.E19 
and Q.sub.E21, the drain-source current path of which transistor Q.sub.E21 
being series-connected to the node through the drain-current path of the 
transistor Q.sub.E20, the drain-source current path of which transistor 
Q.sub.E19 being connected in parallel with that of the transistor 
Q.sub.E18, and gate electrodes of which are connected to receive the 
irreversible control voltage V.sub.O. With V.sub.O =V.sub.L in this 
circuit, the MOS transistors Q.sub.E19 and Q.sub.E21 are always turned 
off. Only when the input signals Vin1 and Vin2 are simultaneously at the H 
levels, the output Vout becomes an L level via a series circuit of the MOS 
transistors Q.sub.E17 and Q.sub.E18. In this way, the circuit acts as an 
ordinary NAND gate. With V.sub.O =V.sub.H, the MOS transistors Q.sub.E19 
and Q.sub.E21 are always turned on and ON-OFF operation of the transistor 
Q.sub.E18 can give no influence to the output Vout. If one of the input 
signals Vin1 and Vin2 becomes an H level, the output Vout becomes an L 
level via a series circuit of the MOS transistors Q.sub.E17 and Q.sub.E19 
or through a series circuit of the MOS transistors Q.sub.E20 and 
Q.sub.E21. In this way, the circuit works as an ordinary NOR gate. As a 
consequence, the circuit has two kinds of logic functions, as shown in 
Truth Table 16, under the control of V.sub.O. 
TRUTH TABLE 16 
______________________________________ 
V.sub.O =V.sub.H 
V.sub.O =V.sub.L 
Vin1 Vin1 
H L H L 
______________________________________ 
Vin2 H L L L H 
L L H H H 
______________________________________ 
Kinds of NOR NAND 
logics 
______________________________________ 
In this way, the MOS logic circuits of the above-mentioned embodiments and 
modified embodiments have two kinds of logic functions. 
As stated above, the MOS logic circuits according to the invention can have 
two kinds of the logic functions, e.g. NOR or NAND logic determined under 
the control of the irreversible voltage V.sub.O or V.sub.O ' derived from 
the generator 300 as shown in FIG. 1. 
In accordance with the invention, there is an advantage that, first, a MOS 
logic circuit with no excess redundancy and the predetermined first logic 
function is prepared and, if it is properly operated as a whole, a proper 
circuit is completed with no excess redundancy, and secondly if no 
adequate circuit operation is obtained from the above circuit, the 
above-mentioned fuse element 2 or 12 of the generator is burned out to 
permit the irreversible control voltage V.sub.O to vary, causing the first 
logic function of this circuit to be changed into the second one under the 
ON/OFF control of the control circuit 200, e.g. the MOS transistor Qn2. In 
other words, a circuit pattern design modification resulting from a change 
of the logic function can be avoided by selecting the proper kind of logic 
functions in irreversible fashion. Furthermore, an adequate design for the 
MOS logic circuit can be made by eliminating the extra redundancy. 
Consequently, according to the above-mentioned embodiments, since the MOS 
logic circuits hold such redundancy functions that the logic functions 
thereof can be changed by way of the irreversible control voltage from the 
generator, it is possible to provide the MOS logic circuit with simpler 
design or without extra redundancies; a design modification on the logic 
functions for the circuits; an improper signal propagation speed; or an 
excess signal propagation time. 
Next, a MOS logic circuit belonging to the aforementioned second category 
will be explained below in connection with the following preferred 
embodiments. Namely, setting the voltage level of the irreversible control 
voltage enables the transfer characteristics between the input signal and 
the output signal to be changed with the logic function of the entire MOS 
circuit unchanged. 
It should be understood in this specification that the definition of 
input/output signal transfer characteristics includes: 
a ratio of the rise time delay to the fall time delay on the output voltage 
and the input voltage; and 
a signal transfer speed from the input to the output, and an input 
inversion voltage defined as the input voltage where the output voltage 
shifts to be the center voltage between two voltages of the power supply, 
i.e., from one stable voltage to the other one. 
FIGS. 24 through 37 show MOS logic circuits according to the preferred 
embodiments of this invention in which the known logic circuit essentially 
consisting of a C-MOS structure is utilized. 
FIGS. 24A, 24B, 24C and 24D show the circuit diagram, equivalent circuit 
diagrams and signal transfer characteristic curves, respectively, of the 
embodiment of this invention in which a known C-MOS inverter is utilized. 
In the MOS logic circuit as shown in FIG. 24A, C-MOS transistor inverters 
Qp51 and Qn51 have their source-drain current paths connected in series 
between one terminal V.sub.DD and the other terminal V.sub.ss, with the 
common connection point forming a node for the output terminal Vout, and 
their gate electrodes connected together to receive an input signal Vin, 
Two p-channel MOS transistors Qp52 and Qp53 have their source-drain 
current paths connected in series between the one terminal V.sub.DD and 
the node, the gate electrode of which MOS transistor Qp53 is connected 
also to receive the input terminal Vin and, to the gate electrode of which 
MOS transistor Qp52 is connected to receive the irreversible control 
voltage V.sub.O derived from the generator 300, e.g. the generator in FIG. 
2. 
It is assumed in this specification that the beta of the above-mentioned 
MOS transistors Qp51, Qp52, Qp53 and Qn51 are .beta.p1, .beta.p2, .beta.p3 
and .beta.n1, respectively. 
The "beta", i.e., the gain coefficient of transconductance of a MOS 
transistor should be defined as a constant that can be determined by the 
thickness and permittivity of a gate insulating layer, mobility of 
carriers, channel length and channel width (consequently .beta.&gt;1). 
When V.sub.O =V.sub.H (the voltage on the terminal V.sub.DD) in the circuit 
as shown in FIG. 24A, the MOS transistor Qp52 is turned off and, in this 
case the two MOS transistors Qp52 and Qp53 are irrelevant to the operation 
of the input circuits Qp51 and Qn51. An equivalent circuit at this time is 
as shown in FIG. 24B and the drivability at the p-channel side corresponds 
to .beta.p1 of the MOS transistor Qp51 per se and the drivability at the 
n-channel side corresponds to .beta.n1 of the MOS transistor Qn51 per se. 
When, on the other hand, V.sub.O =V.sub.L (the voltage on the terminal 
V.sub.SS), the MOS transistor Qp52 is always turned on. With Vin at the L 
level, the MOS transistor Qp53 is rendered in the ON state. At this time, 
two current paths from the supply terminal V.sub.DD to the output terminal 
Vout are established, one including the MOS transistor Qp51 and the other 
including the series arrangement of MOS transistors Qp52 and Qp53. In this 
case, an equivalent circuit serves as an inverter, as shown in FIG. 24C, 
constituted by a p-channel MOS transistor Qpa having the synthesized beta 
of 
##EQU1## 
and an n-channel MOS transistor Qn51 having the beta of .beta.nl. With 
V.sub.O =V.sub.L, it is possible to obtain the equivalent C-MOS inverter 
in which the beta at the p-channel side can be increased effectively 
##EQU2## 
times more than that beta in the case of V.sub.O =V.sub.H, i.e., .beta.p1. 
Consequently, when V.sub.O =V.sub.L, the rise time delay (i.e. the time 
delay of the rising slope of an output signal waveform upon receipt of a 
falling input signal waveform) can be shortened to be approximately 
##EQU3## 
times than that at V.sub.O =V.sub.H. Furthermore, the input inversion 
voltage is closer to V.sub.DD than that when V.sub.O =V.sub.H. The input 
inversion voltage means an input voltage of the inverter when the output 
voltage of the inverter becomes 1/2(V.sub.DD +V.sub.SS) so as to invert 
the inverter output voltage. FIG. 25D shows an input/output signal 
characteristic curve at V.sub.O =V.sub.H and V.sub.O =V.sub.L in this 
embodiment. 
FIG 25A shows a C-MOS logic circuit according to another embodiment of this 
invention in which a C-MOS inverter is used. FIGS. 25B, 25C and 25D show 
equivalent circuits and characteristic curves, respectively. Although in 
the embodiment as shown in FIG. 24A the MOS transistor is provided at the 
p-channel side to receive the irreversible control voltage V.sub.O as a 
gate input signal, the embodiment as shown in FIG. 25A is such that the 
source-drain current paths of two n-channel MOS transistors Qn52 and Qn53 
are connected in series between a terminal V.sub.SS and the node for the 
output Vout with transistor Qn53 nearer V.sub.SS and transistor Qn52 
nearer the node for Vout, the output voltage V.sub.O of the generator 300 
shown in FIG. 1 is applied to the gate of the MOS transistor Qn53 and an 
input signal Vin is applied to the gate of the MOS transistor Qn52. The 
MOS transistors Qn52 and Qn53 take the beta of .beta.n2 and .beta.n3, 
respectively. With V.sub.O =V.sub.L in this circuit the MOS transistor 
Qn53 is turned off and thus the two MOS transistors Qn52 and Qn53 become 
independent of the operation of the input circuits Qp51 and Qn51. At this 
time, the equivalent circuit is as shown in FIG. 25B and the drivability 
of the p-channel side corresponds to .beta.p1 of the MOS transistor Qp51 
per se and the drivability of the n-channel side to .beta.n1 of the MOS 
transistor Qn51 per se. 
With V.sub.O =V.sub.H the MOS transistor Qn53 is always at the ON state and 
with Vin at the "H" level the MOS transistor Qn52 assumes the ON state. At 
this time, two current paths from Vout to V.sub.SS are established: one 
through the MOS transistor Qn51 and the other through the MOS transistors 
Qn52 and Qn53. In this case, the equivalent circuit is an inverter, as 
shown in FIG. 25C, in which an n-channel MOS transistor Qna has a value of 
##EQU4## 
and the p-channel MOS transistor Qp51 has a value of .beta.p1. 
Accordingly, with V.sub.O =V.sub.H it is possible to obtain such an 
equivalent C-MOS inverter that beta of the n-channel side thereof can be 
increased effectively 
##EQU5## 
times more than that beta when at V.sub.O =V.sub.L. In other words, in 
case of V.sub.O =V.sub.H the fall time delay of Vout will be shortened to 
be approximately 
##EQU6## 
times than that at V.sub.O =V.sub.L. FIG. 25D shows an input/output signal 
transfer characteristic at V.sub.O =V.sub.H and V.sub.O =V.sub.L in this 
circuit. 
FIG. 26A shows a MOS logic circuit according to another embodiment of this 
invention, in which a C-MOS inverter is used, FIGS. 26B and 26C being the 
corresponding equivalent circuits. Although in the embodiments as shown in 
FIGS. 24A and 25A the MOS transistor adapted to receive V.sub.O as a gate 
input signal has been provided in either the p-channel side or the 
n-channel side, this embodiment is such that p-channel MOS transistors 
Qp52 and Qp53 and n-channel MOS transistors Qn52 and Qn53 are connected as 
shown in FIG. 26A in which the irreversible voltage V.sub.O is applied 
directly to the gate electrode of the MOS transistor Qp52 and through a 
C-MOS inverter I10 to the gate electrode of the MOS transistor Qn53 and an 
input signal Vin is supplied to the gate electrodes of the MOS transistors 
Qp53 and Qn52. In the circuit as shown in FIG. 26A, when V.sub.O =V.sub.H 
the MOS transistors Qp52 and Qn53 are turned off, so that the MOS 
transistors Qp52, Qp53, Qn52 and Qn53 become independent from the 
operation of input circuits Qp51 and Qn51. At this time, the equivalent 
circuit becomes an ordinary C-MOS inverter, as shown in FIG. 26B, 
comprising only MOS transistors Qp51 and Qn51. With V.sub.O =V.sub.L the 
MOS transistors Qp52 and Qn53 are always in the ON state. In this case, 
the equivalent circuit is an inverter comprising a p-channel MOS 
transistor Qpa having the composed beta of 
##EQU7## 
and an n-channel MOS transistor Qna having a composed beta of 
##EQU8## 
FIG. 27A is a circuit diagram showing a C-MOS logic circuit according to 
another embodiment of this invention, in which an ordinary C-MOS inverter 
is used, FIGS. 27B to 27E being the corresponding equivalent circuits. In 
this embodiment, two kinds of voltages V.sub.O1 and V.sub.O2 from the 
irreversible control voltage generator 300 in FIG. 1 are prepared, 
permitting four kinds of effective drivability at the p-channel side. The 
circuit as shown in FIG. 27A includes the ordinary C-MOS inverter 
comprising a p-channel MOS transistor Qp51 and n-channel MOS transistor 
Qn51. In this circuit, the source-drain current paths of p-channel MOS 
transistors Qp54 and Qp55 are connected in series between an output signal 
Vout and a terminal V.sub.DD and p-channel MOS transistors Qp56 and Qp57 
are connected in parallel with the MOS transistors Qp54 and Qp55. The 
voltage V.sub.O1 is applied to the gate electrode of the MOS transistor 
Qp54, the voltage V.sub.O2 is applied to the gate electrode of the MOS 
transistor Qp56 in the V.sub.DD side, and an input signal Vin is applied 
to the gate electrodes of the MOS transistors Qp55 and Qp57. The MOS 
transistors Qp54 to Qp57 correspond to the beta of .beta.p4 to .beta.p7, 
respectively. With V.sub.O1 =V.sub.O2 =V.sub.H, the MOS transistors Qp54 
and Qp56 are turned off and the MOS transistors Qp54 to Qp57 become 
independent of the operation of the input circuit. At this time, the 
equivalent circuit becomes an ordinary C-MOS inverter, as shown in FIG. 
27B, comprising the MOS transistors Qp51 and Qn51. With V.sub.O1 =V.sub.L 
and V.sub.O2 =V.sub.H, the equivalent circuit is as shown in FIG. 27C and 
at this time the beta of the MOS transistor Qpb at the p-channel side 
becomes 
##EQU9## 
With V.sub.O1 =V.sub.H and V.sub.O2 =V.sub.L the equivalent circuit is as 
shown in FIG. 27D and at this time the beta of the MOS transistor Qpc at 
the p-channel side becomes 
##EQU10## 
With V.sub.O1 =V.sub.O2 =V.sub.L, the equivalent circuit is as shown in 
FIG. 27E and at this time the beta of the MOS transistor Qpd at the 
p-channel side is given by 
##EQU11## 
FIG. 28A is a MOS logic circuit according to another embodiment of this 
invention, in which a delay circuit of a two-stage inverter structure is 
used, FIGS. 28B and 28C being the corresponding equivalent circuits. The 
MOS logic circuit as shown in FIG. 28A includes a delay circuit comprising 
a first stage C-MOS inverter I20 constituted by a p-channel MOS transistor 
Qp58 having its source-drain current path connected between one terminal 
V.sub.DD and a node N5 and its gate electrode connected to the other 
terminal V.sub.SS and an n-channel MOS transistor Qn54 having a 
drain-source current path connected between the node N5 and the terminal 
V.sub.SS and its gate electrode connected to receive an input signal, Vin; 
and a second stage C-MOS inverter I30 constituted by a p-channel MOS 
transistor Qp59 having its source-drain current path connected between the 
terminal V.sub.DD and an output Vout and its gate electrode connected to 
receive a signal on the node N5 and an n-channel MOS transistor Qn55 
having its drain-source current path connected between the output Vout and 
the terminal V.sub.SS and its gate electrode connected to receive the 
signal on the node N5. It should be noted that since the gate electrode of 
the transistor Qp58 of the first stage C-MOS inverter I20 is directly 
connected to the supply terminal V.sub.SS, it works as the load 
transistor, and precisely speaking, although it is not called a "C-MOS 
inverter", practically it is preferable to call it so in this 
specification. In this MOS logic circuit, a p-channel MOS transistor Qp60 
has its source-drain current path between the terminal V.sub.DD and the 
node N5 has its gate and connected to receive as a gate input signal (the 
irreversible control voltage) V.sub.O from the generator 300 in FIG. 1. It 
would be supposed that the MOS transistors Qn54, Qp58 and Qp60 have the 
beta of .beta.n4, .beta.p8 and .beta.p10, respectively, and that the rise 
time delay and fall time delay of the C-MOS inverters I20 and I30 when the 
input signal Vin falls are represented by .tau.2 and .tau.3, respectively. 
When V.sub.O =V.sub.H, the MOS transistor Qp60 is turned off. At this 
time, the equivalent circuit is as shown in FIG. 28B and an entire fall 
time delay .tau. f is given by a sum of .tau.2+.tau.3. When at V.sub.O 
=V.sub.L the MOS transistor Qp60 is turned on, the p-channel side of the 
C-MOS inverter I20 is represented by a MOS transistor Qpe having a 
composed value of .beta.p8 and .beta.p10, as indicated by the equivalent 
circuit of FIG. 28C. As a result, the signal delay time of the first stage 
C-MOS inverter 20 will be shortened to be approximately 
##EQU12## 
times than that at V.sub.O =V.sub.H and thus an entire fall time delay 
.tau.f corresponds to approximately 
##EQU13## 
It is to be noted here that, even if .beta.n4&gt;.beta.p8+.beta.p10 and the 
transistor Qp60 is turned on, the transistor Qn54 has enough drive to 
cause the output Vout of the inverter I30 to be changed to the V.sub.DD 
side. 
FIG. 29A shows a MOS logic circuit according to another embodiment of this 
invention, in which a delay circuit of a two-stage inverter structure is 
utilized, FIGS. 29B and 29C being the corresponding equivalent circuits. 
Although in the embodiment of FIG. 28A the MOS transistor Qp60 connected 
to receive V.sub.O as the gate input signal is provided at the p-channel 
side, the MOS logic circuit as shown in FIG. 29A is such that an n-channel 
MOS transistor Qn56 has its drain-source current path connected between 
the node N5 and the terminal V.sub.SS and connected to receive V.sub.O as 
a gate input signal. 
In order to transfer the input rising signal with a delay in this 
embodiment, an input signal Vin is applied to the gate electrode of a 
p-channel MOS transistor Qp58 in a first stage C-MOS inverter I22 and the 
gate of an n-channel MOS transistor Qn54 is connected to a terminal 
V.sub.DD. It is assumed that the MOS transistors Qp58, Qn54 and Qn56 have 
the values of .beta.p8, .beta.n4 and .beta.n6, respectively, and that the 
fall time delay and rise time delay of the C-MOS inverters I22 and I30 
when the input signal Vin rises are represented by .tau.2' and .tau.3', 
respectively. When V.sub.O =V.sub.L, the MOS transistor Qn56 is turned 
off. At this time, the equivalent circuit is as shown in FIG. 29B and an 
entire rise time delay .tau.r corresponds to a sum of .tau.2' and .tau.3'. 
With V.sub.O =V.sub.H, the MOS transistor Qn56 is turned on and the 
n-channel side of the C-MOS inverter I22 is represented by a MOS 
transistor Qnb having a composed beta of .beta.n4+.beta.n6 as indicated by 
the equivalent circuit of FIG. 29C and a signal time delay in the first 
stage C-MOS inverter I22 will be shortened to 
##EQU14## 
As a result, an entire rise time delay .tau.r will be given by 
##EQU15## 
It is to be noted here that even if .beta.p8&gt;.beta.n4+.beta.n6 and the MOS 
transistor Qn6 is turned on, the MOS transistor Qp8 has enough drive to 
cause the output Vout of an inverter I3 to be changed to the V.sub.SS 
side. 
The following is an explanation of MOS logic circuits utilizing a logic 
circuit having two or more inputs. 
FIG. 30 shows a MOS logic circuit including a multi-input OR type delay 
circuit obtained by modifying the first stage inverter of the embodiment 
of FIG. 28A into a multi-input version, in which input signals Vin1, Vin2 
and Vin3 are applied to the gates of n-channel MOS transistors Qn61, Qn62 
and Qn63, respectively. 
FIG. 31 shows a MOS logic circuit including an AND type delay circuit 
obtained by modifying the first stage inverter of the embodiment of FIG. 
29A into a mutli-input version, in which input signals Vin1, Vin2 and Vin3 
are applied to the gate electrodes of p-channel MOS transistors Qp81, Qp82 
and Qp83, respectively. 
When in the embodiment shown in FIG. 30 or FIG. 31 a MOS transistor Qp60 or 
Qn56 is turned on, the fall time delay or the rise time delay thereof will 
be made shorter than when the MOS transistor Qp60 or Qn56 is turned off. 
FIGS. 32 to 34 show MOS logic circuits according to the embodiments of this 
invention, in which an ordinary two-input C-MOS NAND circuit is utilized. 
The MOS logic circuit of FIG. 32 includes the ordinary two-input C-MOS NAND 
gate comprising p-channel MOS transistors Qp61 and Qp62 having their 
source-drain current paths connected in parallel between one terminal 
V.sub.DD and the node for the output Vout and connected to receive input 
signals Vin1 and Vin2 as gate input signals, respectively, and n-channel 
MOS transistors Qn57 and Qn58 having their drain-source current paths 
connected in series between the output Vout and a terminal V.sub.SS and 
connected to receive the input signals Vin1 and Vin2 as gate input 
signals, and further p-channel MOS transistors Qp63 and Qp64 having their 
source-drain current paths connected in series between the one terminal 
V.sub.DD and the node for the output Vout and a p-channel MOS transistor 
Qp65 having its source-drain current path connected between the drain of 
the MOS transistor Qp63 and the output Vout. The irreversible control 
voltage V.sub.O is applied to the gate of the MOS transistor Qp63 as a 
gate input signal and the input signals Vin1 and Vin2 are applied to the 
gate electrodes of the MOS transistors Qp64 and Qp65. 
The MOS logic circuit as shown in FIG. 33 includes an ordinary two-input 
C-MOS NAND gate comprising MOS transistors Qp61, Qp62, Qn57 and Qn58 
connected as shown in FIG. 32, and further includes n-channel MOS 
transistors Qn59, Qn60 and Qn61 having their drain-source current paths 
connected in series between the output Vout and a terminal V.sub.SS, input 
signals Vin1 and Vin2 being applied to the gate electrodes of which MOS 
transistors Qn59 and Qn60, respectively, and a voltage V.sub.O having an 
opposite relation to V.sub.O being applied to the gate of the MOS 
transistor Qn61. 
In the MOS logic circuit of FIG. 34, MOS transistors Qp63, Qp64, Qp65 and 
Qn59, Qn60, Qn61 are all added to an ordinary two-input C-MOS NAND circuit 
and a C-MOS inverter I40 is added to obtain the inverted voltage V.sub.O. 
If in the embodiments as shown in FIGS. 32 to 34 the beta of the MOS 
transistors Qp61 to Qp65 are represented by .beta.p11 to .beta.p15, 
respectively, and the beta of the MOS transistors Qn57 to Qn61 by .beta.n7 
to .beta.n11, respectively, then the effective beta .beta.p at the 
p-channel side of Vout and the effective beta .beta.n at the n-channel 
side thereof with respect to Vin1, Vin2 and V.sub.O or V.sub.O will be as 
indicated by the following Tables 17 to 19. 
TABLE 17 
______________________________________ 
(C-MOS NAND gate shown in FIG. 32) 
______________________________________ 
V.sub.O = V.sub.H 
Vin1 = L .beta.p = .beta.p11 
##STR1## Vin2 = H 
Vin1 = H .beta.p = .beta.p12 
Vin2 = L 
Vin1 = L .beta.p = .beta.p11 + .beta.p12 
Vin2 = L 
Vin1 = H Vin2 = H 
##STR2## 
##STR3## Vin1 = L Vin2 = H 
##STR4## 
Vin1 = H Vin2 = L 
##STR5## 
Vin1 = L .beta.p .perspectiveto. .beta.p11 + .beta.p12 + 
Vin2 = L 
##STR6## 
Vin1 = H Vin2 = H 
##STR7## 
______________________________________ 
TABLE 18 
______________________________________ 
(C-MOS NAND gate shown in FIG. 33) 
______________________________________ 
V.sub.O = V.sub.H 
Vin1 = L .beta.p = .beta.p11 
##STR8## Vin2 = H 
Vin1 = H .beta.p = .beta.p12 
Vin2 = L 
Vin1 = L .beta.p = .beta.p11 + .beta.p12 
Vin2 = L 
Vin1 = H Vin2 = H 
##STR9## 
##STR10## 
Vin1 = L Vin2 = H 
.beta.p = .beta.p11 
Vin1 = H .beta.p = .beta.p12 
Vin2 = L 
Vin1 = L .beta.p = .beta.p11 + .beta.p12 
Vin2 = L 
Vin1 = H Vin2 = H 
##STR11## 
##STR12## 
______________________________________ 
TABLE 19 
______________________________________ 
(C-MOS NAND gate shown in FIG. 34) 
______________________________________ 
V.sub.O = V.sub.H 
Vin1 = L .beta.p = .beta.p11 
##STR13## 
Vin2 = H 
Vin1 = H .beta.p = .beta.p12 
Vin2 = L 
Vin1 = L .beta.p = .beta.p11 + .beta.p12 
Vin2 = L 
Vin1 = H Vin2 = H 
##STR14## 
##STR15## 
Vin1 = L Vin2 = H 
##STR16## 
Vin1 = H Vin2 = L 
##STR17## 
Vin1 = L .beta.p .perspectiveto. .beta.p11 + .beta.p12 + 
Vin2 = L 
##STR18## 
Vin1 = H Vin2 = H 
##STR19## 
##STR20## 
______________________________________ 
FIGS. 35 to 37 show MOS logic circuits according to the embodiments of this 
invention, in which an ordinary two-input C-MOS NOR gate is utilized. 
The MOS logic circuit of FIG. 35 includes the ordinary two-input C-MOS NOR 
gate constituted by p-channel MOS transistors Qp66 and Qp67 having their 
source-drain current paths connected in series between one terminal 
V.sub.DD and the node for the output Vout and their gate electrodes 
connected to receive input signals Vin2 and Vin1 as gate input signals 
respectively; and n-channel MOS transistors Qn62 and Qn63 connected in 
parallel between the output Vout and a terminal V.sub.SS and connected to 
receive the input signals Vin1 and Vin2 as gate input signals, 
respectively; and further n-channel MOS transistors Qn64 and Qn65 having 
their drain-source current paths connected in series between the output 
Vout and the terminal V.sub.SS, an n-channel MOS transistor Qn66 having 
its source-drain current path connected in parallel to the MOS transistor 
Qn64 between the output Vout and the MOS transistor Qn65, the input 
signals Vin2 and Vin1 being applied to the gates of the MOS transistors 
Qn64 and Qn66, respectively, and V.sub.O being applied to the gate 
electrode of the MOS transistor Qn65. 
The MOS logic circuit as shown in FIG. 36 includes an ordinary two-input 
C-MOS NOR circuit constituted by MOS transistors Qp66, Qp67, Qn62 and Qn63 
as discussed above, and further p-channel MOS transistors Qp68, Qp69 and 
Qp70 having their source-drain current paths connected in series between a 
terminal V.sub.DD and an output Vout, V.sub.O having an opposite relation 
to V.sub.O being applied to the gate electrode of the MOS transistor Qp68 
and input signals Vin2 and Vin1 being applied to the gate electrodes of 
the MOS transistors Qp69 and Qp70, respectively. 
In the MOS logic circuit as shown in FIG. 37, MOS transistors Qn64, Qn65, 
Qp68, Qp69 and Qp70 are added to an ordinary two-input C-MOS NOR gate as 
modified in FIG. 36, and a C-MOS inverter I50 is added to the circuit to 
obtain V.sub.O. 
If in the embodiments of FIGS. 35 to 37 the MOS transistors Qp66 to Qp70 
have the beta of .beta.p16 to .beta.p20, respectively, and the MOS 
transistors Qn62 to Qn66 the beta of .beta.n12 to .beta.n16, respectively, 
then an effective beta .beta.p at the p-channel side of Vout and effective 
beta .beta.n at the n-channel side thereof with respect to Vin1, Vin2 and 
V.sub.O or V.sub.O will be as indicated by the following Tables 20 to 22. 
TABLE 20 
______________________________________ 
(C-MOS NOR gate shown in FIG. 35) 
______________________________________ 
V.sub.O = V.sub.L 
Vin1 = H .beta.n = .beta.n12 
##STR21## 
Vin2 = L 
Vin1 = L .beta.n = .beta.n13 
Vin2 = H 
Vin1 = H .beta.n = .beta.n12 + .beta.n13 
Vin2 = H 
Vin1 = L Vin2 = L 
##STR22## 
##STR23## 
Vin1 = H Vin2 = L 
##STR24## 
Vin1 = L Vin2 = H 
##STR25## 
Vin1 = H .beta.n .perspectiveto. .beta.n12 + .beta.n13 + 
Vin2 = H 
##STR26## 
Vin1 = L Vin2 = L 
##STR27## 
______________________________________ 
TABLE 21 
______________________________________ 
(C-MOS NOR gate shown in FIG. 36) 
______________________________________ 
V.sub.O = V.sub.L 
Vin1 = H .beta.n = .beta.n12 
##STR28## 
Vin2 = L 
Vin1 = L .beta.n = .beta.n13 
Vin2 = H 
Vin1 = H .beta.n = .beta.n12 + .beta.n13 
Vin2 = H 
Vin1 = L Vin2 = L 
##STR29## 
V.sub.O = V.sub.H 
Vin1 = H .beta.n = .beta.n12 
##STR30## 
Vin2 = L 
Vin1 = L .beta.n = .beta.n13 
Vin2 = H 
Vin1 = H .beta.n = .beta.n12 + .beta.n13 
Vin2 = H 
Vin1 = L 
##STR31## 
Vin2 = L 
##STR32## 
______________________________________ 
TABLE 22 
______________________________________ 
(C-MOS NOR gate shown in FIG. 37) 
______________________________________ 
V.sub.O = V.sub.L 
Vin1 = H .beta.n = .beta.n12 
##STR33## 
Vin2 = L 
Vin1 = L .beta.n = .beta.n13 
Vin2 = H 
Vin1 = H .beta.n = .beta.n12 + .beta.n13 
Vin2 = H 
Vin1 = L Vin2 = L 
##STR34## 
##STR35## 
Vin1 = H Vin2 = L 
##STR36## 
Vin1 = L Vin2 = H 
##STR37## 
Vin1 = H .beta.n .perspectiveto. .beta.n12 + .beta.n13 + 
Vin2 = H 
##STR38## 
Vin1 = L 
##STR39## 
Vin2 = L 
##STR40## 
______________________________________ 
FIG. 38 shows a MOS logic circuit according to another embodiment of this 
invention, in which an ordinary three-input C-MOS Exclusive-OR type delay 
circuit is utilized. The MOS logic circuit includes firstly an ordinary 
delay type three-input C-MOS Exclusive-OR gate comprising a p-channel MOS 
transistor Qp71 having its source-drain current path connected between one 
terminal V.sub.DD and a node N6 and its gate electrode connected to the 
other terminal V.sub.SS and functioning as a load transistor, secondly 
n-channel MOS transistors Qn67, Qn68 and Qn69 functioning as driver 
transistors having their drain-source current paths connected in series 
between the node N6 and the other terminal V.sub.SS and their gate 
electrodes connected to receive input signals Vin1, Vin2 and Vin3 as gate 
input signals, respectively, thirdly n-channel MOS transistors Qn70, Qn71 
and Qn72 functioning as driver transistors having their drain-source 
current paths connected in series between the node N6 and the other 
terminal V.sub.SS and their gate electrodes connected to receive the input 
signals Vin1, Vin2 and Vin3, respectively, through C-MOS inverters I60, 
I70 and I80, fourthly a C-MOS inverter I90 adapting to invert a signal on 
the node N6 to obtain an output Vout, and finally a p-channel MOS 
transistor Qp72 having its source-drain current path connected between one 
terminal V.sub.DD and the node N6 and its gate electrode connected to 
receive the voltage V.sub.O as a gate input signal which is the reversed 
voltage. 
In this embodiment, the beta (=drive) of the load transistor Qp71 with 
respect to the node N6 can be varied by varying V.sub.O and thus the time 
delay can be varied. That is, with V.sub.O =V.sub.H the MOS transistor 
Qp72 is turned off and the load capability of the p-channel side becomes 
relatively small and thus the fall time delay of Vout becomes longer. With 
V.sub.O =V.sub.L, on the other hand, the MOS transistor Qp72 is turned on 
and the load capability of the p-channel side becomes relatively great and 
thus the fall time delay of Vout becomes smaller. Needless to say even if 
the MOS transistor Qp72 is turned on, the series-connected n-channel MOS 
transistors Qn67 and Qn69 to Qn72 have enough drive to change the output 
of the inverter to the V.sub.DD side. 
Having explained the invention in connection with the C-MOS structures, the 
following description of the invention explain the embodiments as shown in 
FIGS. 39 through 48 which employ Enhancement/Depletion mode structures 
with a depletion mode MOS transistor as a load transistor and an 
enhancement mode MOS transistor as a driver transistor. 
FIG. 39A shows a MOS logic circuit according to the embodiment of this 
invention in which an ordinary E/D type inverter is utilized, FIGS. 39B, 
39C and 39D showing the corresponding equivalent circuits and transfer 
characteristic curves. This MOS logic circuit includes the E/D type 
inverter comprising a depletion type MOS transistor Q.sub.D51 functioning 
as a load transistor having its source-drain current path connected 
between one terminal V.sub.DD and a node for an output Vout and its gate 
electrode connected to the node and an enhancement type MOS transistor 
Q.sub.E51 functioning as a driver transistor having its drain-source 
current path connected between the other terminal V.sub.SS and the node 
for the output Vout and its gate electrode connected to receive an input 
signal Vin, and further, enhancement type MOS transistors Q.sub.E52 and 
Q.sub.E53 having their drain-source current paths connected in series 
between the node for the output Vout and the other terminal V.sub.SS with 
transistor Q.sub.E52 nearer the node for Vout and transistor Q.sub.E53 
nearer the node for V.sub.SS, the input signal Vin being applied to the 
gate electrode of the MOS transistor Q.sub.E52 and the irreversible 
control voltage V.sub.O from the generator 300 or the generator as shown 
in FIG. 3 being applied to the gate electrode of the MOS transistor 
Q.sub.E53. The beta of the MOS transistors Q.sub.D51, Q.sub.E51 to 
Q.sub.E53 are represented by .beta..sub.D51, .beta..sub.E51 to 
.beta..sub.E53, respectively. When V.sub.O =V.sub.L, the MOS transistor 
Q.sub.E53 is turned off and thus the MOS transistors Q.sub.E52 and 
Q.sub.E53 become irrelevant to the input circuit. At this time, the 
equivalent circuit is as shown in FIG. 39B and the loading capability 
corresponds to .beta..sub.D1 of the MOS transistor Q.sub.D51 per se and 
the drivability corresponds to .beta..sub.E1 of the MOS transistor 
Q.sub.E51. With V.sub.O =V.sub.H the MOS transistor Q.sub.E53 is always 
rendered in the ON state. At this time, the MOS transistor Q.sub.E52 
(Vin=V.sub.H) is turned on and two current paths from Vout to V.sub.SS are 
established: one through the MOS transistor Q.sub.D51 and the other 
through the series-connected drain-source current path of MOS transistors 
Q.sub.E52 and Q.sub.E53. With V.sub.O =V.sub.H the equivalent circuit 
becomes an inverter as shown in FIG. 39C which comprises an enhancement 
type MOS transistor Q.sub.Ea having a composed beta of 
##EQU16## 
and a depletion MOS transistor having a beta of .beta..sub.D1. In this 
case, it is assumed that the source-substrate bias effect, so-called "the 
back gate effect" on the threshold of the transistor Q.sub.E52 is 
disregarded. When V.sub.O =V.sub.H, the beta of the MOS transistor at the 
enhancement mode side of the E/D type inverter is effectively 
##EQU17## 
times larger than that in case of V.sub.O =V.sub.L. In other words, the 
fall time delay of Vout will be shortened to be approximately 
##EQU18## 
times the fall time delay when V.sub.O =V.sub.H. FIG. 39D shows an 
input/output signal transfer characteristic curve when V.sub.O =V.sub.H 
and V.sub.O =V.sub.L in this embodiment. V.sub.TE in FIG. 39D shows the 
threshold voltage of the enhancement mode MOS transistor. 
FIG. 40A shows a MOS logic circuit according to another embodiment of this 
invention in which an ordinary Enhancement/Depletion type inverter is 
utilized, FIG. 40B showing a transfer characteristic curve of this 
circuit. This MOS logic circuit includes the ordinary E/D type inverter 
constituted by MOS transistors Q.sub.D51 and Q.sub.E51, and further a 
depletion type MOS transistors Q.sub.D52 and an enhancement type MOS 
transistor Q.sub.E54, both source-drain current paths of which being 
series-connected between one terminal V.sub.DD and the node for the output 
terminal Vout, the gate electrode of which transistor Q.sub.D52 being 
connected to that of the transistor Q.sub.D51 so as to receive the input 
signal Vin, and the gate electrode of transistor Q.sub.E54 being connected 
to receive the irreversible control voltage V.sub.O derived from the 
generator 300. 
In this circuit, the fall transfer characteristic of Vout is substantially 
determined only by the MOS transistor Q.sub.E51. As to the rise transfer 
characteristics of Vout, when V.sub.O =V.sub.H, however, not only the MOS 
transistor Q.sub.E54 but also the MOS transistors Q.sub.E54 and Q.sub.D52 
are associated with an increase in load drivability and the rise time 
delay will be shortened to a given extent. Because the MOS logic circuit 
includes a series arrangement of the MOS transistors Q.sub.E54 and 
Q.sub.D52, it is not easily possible to calculate the load drivability. 
Under the following conditions, however, a composed effective beta 
.beta..sub.D at V.sub.O =V.sub.H can be given by (the beta of the MOS 
transistors Q.sub.E54 and Q.sub.D52 is .beta..sub.E4 and .beta..sub.D2 
respectively): 
(1) For .beta..sub.E4 &gt;&gt;.beta..sub.D2 as well as Vout&lt;V.sub.DD -V.sub.TE4 
(where V.sub.Te4 denotes a threshold voltage of the MOS transistor 
Q.sub.E54) 
EQU .beta..sub.D .perspectiveto..beta..sub.D1 +.beta..sub.D2 
(2) For .beta..sub.E4 &gt;&gt;.beta..sub.D2 as well as Vout.gtoreq.V.sub.DD 
-V.sub.TE4 
EQU .beta..sub.D .perspectiveto..beta..sub.D1 
(3) For .beta..sub.E4 &gt;&gt;.beta..sub.D2 as well as Vout&lt;V.sub.DD -V.sub.TE4 
##EQU19## 
where 
##EQU20## 
and that -V.sub.TD2 stands for the threshold value of the MOS transistor 
Q.sub.D52. 
(4) For .beta..sub.E4 &lt;&lt;.beta..sub.D2 as well as Vout.gtoreq.V.sub.DD 
-V.sub.TE4 
EQU .beta..sub.D .perspectiveto..beta..sub.D1 
FIG. 40B shows the input/output signal transfer characteristic curve of 
this embodiment at V.sub.O =V.sub.H and V.sub.O =V.sub.L. 
FIG. 41A shows a MOS logic circuit according to another embodiment of this 
invention, in which an E/D type inverter is utilized. Where it is possible 
to obtain a larger negative going voltage V.sub.L ' as the irreversible 
voltage V.sub.O (V.sub.O ') than the threshold voltage (-V.sub.TD) of the 
depletion type MOS transistor and since V.sub.L is closer to V.sub.SS than 
V.sub.L ' enhancement type MOS transistor Q.sub.E54 in FIG. 40A may be 
omitted as shown in FIG. 41A and the voltage V.sub.O ' (which may have one 
or two voltages of either V.sub.L ' or V.sub.H) may be applied to the gate 
electrode of a MOS transistor Q.sub.D52. At this time, the input/output 
signal transfer characteristic curve will be as shown in FIG. 41B. 
FIGS. 42A and 42B each show a MOS logic circuit according to another 
embodiment of this invention, in which an ordinary E/D type inverter is 
used and the beta of both the load transistor side and driver transistor 
side are adapted to be varied. The MOS logic circuit of FIG. 42A includes 
the ordinary E/d type inverter comprising MOS transistors Q.sub.D51 and 
E.sub.D51, in which at the load transistor Q.sub.D51 side of the inverter 
an enhancement type MOS transistor Q.sub.E55 is connected between one 
terminal V.sub.DD and the node for output Vout and has its gate electrode 
connected to receive the irreversible voltage V.sub.O as a gate input 
signal and at the driver transistor Q.sub.E51 side thereof two enhancement 
type MOS transistors Q.sub.E56 and Q.sub.E57 are connected in series 
between an output Vout and the other terminal V.sub.SS. The MOS transistor 
Q.sub.E56 is connected to receive an input signal Vin as a gate input 
signal and the MOS transistor Q.sub.E57 is connected to receive the 
voltage V.sub.O as a gate input signal. In the MOS logic circuit as shown 
in FIG. 42B a depletion type MOS transistor Q.sub.D53 is used instead of 
the above-mentioned enhancement type MOS transistor Q.sub.E55 and the 
above-mentioned V.sub.O ' is used instead of V.sub.O. 
FIGS. 43A through 43E each show a MOS logic circuit according to another 
embodiment of this invention, in which an ordinary E/D type inverter is 
used. In this case, there are two kinds of voltage selections for the 
irreversible control voltage V.sub.O ; one is to use independently 
V.sub.O1 and V.sub.O2, the other is to use a V.sub.L ' as V.sub.O1 ' and 
V.sub.O2 ' which goes more negative than the threshold voltage -V.sub.TD 
of the depletion type MOS transistor. By using these irreversible voltages 
it is possible for the beta to have two kinds of redundancy. 
The MOS logic circuit of FIG. 43A includes the ordinary E/D type inverter 
comprising MOS transistors Q.sub.D51 and Q.sub.E51. In the driver 
transistor Q.sub.E51 side of the inverter, two enhancement type MOS 
transistors Q.sub.E58 and Q.sub.E59 are connected in series between the 
node for the output Vout and one terminal V.sub.SS and connected to 
receive Vin and V.sub.O1 as gate input signals, respectively, and two 
enhancement type MOS transistors Q.sub.E60 and Q.sub.E61 are connected in 
series between the node, the output Vout and one terminal V.sub.SS and in 
parallel with the series arrangement of the MOS transistors Q.sub.E58 and 
Q.sub.E59 and connected to receive Vin and V.sub.O2 as gate input signals, 
respectively, whereby two kinds of redundancies are given to the beta of 
the driver transistor Q.sub.E51 side. 
The MOS logic circuit of FIG. 43B includes the ordinary E/D inverter 
comprising MOS transistors Q.sub.D51 and Q.sub.E51 side. In the load 
transistor Q.sub.D51 of the inverter, enhancement type MOS transistors 
Q.sub.E62 and Q.sub.E63 are connected in parallel between one terminal 
V.sub.DD and the node for the output Vout and connected to receive 
V.sub.O1 and V.sub.O2 as gate input signals, respectively, whereby two 
kinds of redundancies are given to the beta of the load transistor 
Q.sub.D51 side. 
In the MOS logic circuit as shown in FIG. 43C, the enhancement type MOS 
transistors Q.sub.E62 and Q.sub.E63 in the MOS logic circuit of FIG. 43B 
have been replaced by depletion type MOS transistors Q.sub.D54 and 
Q.sub.D55, and the irreversible voltages V.sub.O1 ' and V.sub.O2 ' are 
applied to the gate electrodes of the MOS transistors Q.sub.D54 and 
Q.sub.D55, instead of V.sub.O1 and V.sub.O2. 
The MOS logic circuit of FIG. 43D includes the ordinary E/D inverter 
comprising MOS transistors Q.sub.D51 and Q.sub.E51. In the driver 
transistor Q.sub.E51 side of the inverter, two enhancement type MOS 
transistors Q.sub.E64 and Q.sub.E65 are connected in series between the 
node for the output Vout and a terminal V.sub.SS and connected to receive 
Vin and V.sub.O1 as gate input signals, respectively, and in the load 
transistor Q.sub.D51 side an enhancement type MOS transistor Q.sub.E66 is 
connected between one terminal V.sub.DD and the node for the output Vout 
and connected to receive V.sub.O2 as a gate input signal, whereby one kind 
of redundancy is provided to each the beta of the load transistor 
Q.sub.D51 side and the driver transistor Q.sub.E51 side. 
In the MOS logic circuit as shown in FIG. 43E, the above-mentioned 
enhancement type MOS transistors Q.sub.E65 and Q.sub.E66 in the MOS logic 
circuit of FIG. 43D have been replaced by two depletion type MOS 
transistors Q.sub.D56 and Q.sub.D57 and the irreversible control voltages 
V.sub.O1 ' and V.sub.O2 ' are applied to the gate electrodes of the MOS 
transistors Q.sub.D56 and Q.sub.D57, respectively. 
FIGS. 44A and 44B each show a MOS logic circuit according to another 
embodiment of this invention, in which an ordinary E/D type two-input NAND 
gate is used. 
The MOS logic circuit of FIG. 44A includes the ordinary E/D type two-input 
NAND gate comprising a depletion type MOS transistor Q.sub.D58 functioning 
as a load transistor having its source-drain current path connected 
between one terminal V.sub.DD and the node for the output Vout and and two 
enhancement type MOS transistors Q.sub.E67 and Q.sub.E68 functioning as 
driver transistors having their source-drain current paths connected in 
series between the output Vout and the other terminal V.sub.SS and having 
their gates connected to receive Vin1 and Vin2 as gate input signals, 
respectively, and further an enhancement type MOS transistor Q.sub.E69 and 
a depletion type MOS transistor Q.sub.D59 having their source-drain 
current paths connected in series between the one terminal V.sub.DD and 
the output Vout, and the irreversible voltages V.sub.O and Vout being 
applied to the gate electrodes of the MOS transistors Q.sub.E69 and 
Q.sub.D59, respectively. 
In the MOS logic circuit as shown in FIG. 44B, the enhancement type MOS 
transistor Q.sub.E69 of FIG. 44A has been replaced by the depletion type 
MOS transistor Q.sub.D69 and V.sub.O ' is applied to the gate of the MOS 
transistor Q.sub.D60 instead of V.sub.O. 
In the MOS logic circuit the MOS transistor Q.sub.E69 (FIG. 44A) or 
Q.sub.D60 (FIG. 44B) is turned on or off by varying V.sub.O or V.sub.O '. 
By so doing, it is possible to select a relatively greater or smaller load 
capability. 
FIG. 45 shows a MOS logic circuit according to another embodiment of this 
invention, in which an ordinary E/D type two-input NAND gate is used. This 
MOS logic circuit includes the ordinary E/D type two-input NAND gate 
comprising a depletion type MOS transistor Q.sub.D61 connected between 
V.sub.DD and Vout and acting as a load transistor and an enhancement type 
MOS transistors Q.sub.E70 and Q.sub.E71 connected in series between Vout 
and V.sub.SS and acting as driver transistors, and further three 
enhancement type MOS transistors Q.sub.E72, Q.sub.E73 and Q.sub.E74 having 
their drain-source current paths connected in series between the node for 
the output Vout and one terminal V.sub.SS and connected to receive Vin1, 
Vin2 and V.sub.O as gate input signals, respectively. By setting V.sub.O 
=V.sub.H or V.sub.O =V.sub.L, the MOS transistor Q.sub.E74 is turned on or 
off, whereby it is possible to select a relatively greater or smaller 
drivability. 
FIGS. 46A through 48B each show a MOS logic circuit according to another 
embodiment of this invention, in which an ordinary E/D type two-input NOR 
gate is used. The MOS logic circuit 46A includes the ordinary E/D type 
two-input NOR gate comprising a depletion type MOS transistor Q.sub.D62 
connected between one terminal V.sub.DD and the node for the output Vout 
and functioning as a load transistor and enhancement type MOS transistors 
Q.sub.E75 and Q.sub.E76 connected in parallel between an output Vout and 
the other terminal V.sub.SS and functioning as driver transistors, and 
further an enhancement type MOS transistor Q.sub.E77 and a depletion type 
MOS transistor Q.sub.D63 having their first source-drain current paths 
connected in series between the terminal V.sub.DD and the output Vout and 
the irreversible control voltages V.sub.O and Vout being applied to the 
gate electrodes of the MOS transistors Q.sub.D77 and Q.sub.D63, 
respectively. 
In the MOS logic circuit as shown in FIG. 46B, a depletion type MOS 
transistor Q.sub.D64 is inserted in place of the above-mentioned 
enhancement type MOS transistor Q.sub.E77 in FIG. 46A and the irreversible 
voltage V.sub.O ' is applied to the gate electrode of the MOS transistor 
Q.sub.D64 instead of V.sub.O. 
In the MOS logic circuits as shown in FIGS. 46A and 46B the MOS transistors 
Q.sub.E77 or Q.sub.D64 are turned on or off, respectively, by varying 
V.sub.O or V.sub.O ', whereby a relatively greater or smaller load 
capability can be selected. 
FIG. 47 shows a MOS logic circuit according to another embodiment of this 
invention. This MOS logic circuit includes an ordinary E/D type two-input 
NOR gate comprising a depletion type MOS transistor Q.sub.D62 connected 
between one terminal V.sub.DD and the node for the output Vout and 
enhancement type MOS circuits Q.sub.E75 and Q.sub.E76 connected in 
parallel between the output Vout and the other terminal V.sub.SS, and 
further two enhancement type MOS transistors Q.sub.E78 and Q.sub.E79 
having their source-drain current paths connected in series between the 
output Vout and the terminal V.sub.SS and an enhancement type MOS 
transistor Q.sub.E80 having its drain-source current path connected 
between the output Vout and the source of the MOS transistor Q.sub.E79 and 
Vin1, Vin2 and V.sub.O being applied to the gate electrodes of the MOS 
transistors Q.sub.E78, Q.sub.E80 and Q.sub.E79, respectively. In this MOS 
logic circuit, the MOS transistor Q.sub.E79 is turned on or off by varying 
V.sub.O, whereby a relatively greater or smaller drivability can be 
selected. 
In the MOS logic circuit as shown in FIG. 48A, both the MOS transistors 
Q.sub.E77 and Q.sub.D63 as shown in FIG. 46A and the MOS transistors 
Q.sub.E78, Q.sub.E79 and Q.sub.E80 in FIG. 47 are all inserted, whereby a 
relatively greater or smaller load capability and drivability can be 
selected. 
Finally, the MOS logic circuit as shown in FIG. 48B is the modified one as 
shown in FIG. 46B. Namely, instead of the above-mentioned enhancement 
transistor Q.sub.E77 in FIG. 48A, a depletion MOS transistor Q.sub.D64 is 
provided in the same circuit position. As a result, a relatively greater 
or smaller load capability and drivability can be realized. 
In the above-mentioned respective MOS logic circuits, the input/output 
signal transfer characteristics, such as the drivability of the transistor 
can be changed by varying the irreversible voltages V.sub.O or V.sub.O ', 
or V.sub.O1, V.sub.O2, V.sub.O1 ' or V.sub.O2 ', with the logic functions 
thereof unchanged. Consequently, if in the first instance, a MOS logic 
circuit is constructed without having any excess redundancy in electrical 
characteristics and in this case this circuit is properly operated, then 
it follows that a proper MOS logic circuit without any excess redundancy 
can be realized. To the contrary, if no adequate operation can be obtained 
from this circuit, the above-mentioned fuse element 2 or 12 is caused to 
burn out so as to vary the irreversible voltage V.sub.O which is applied 
to the MOS transistor as the control circuit 200, whereby the signal 
transfer characteristic of the circuit is changed to another one which has 
been initially designed. By so doing, the whole MOS logic circuit can be 
properly operated. 
In other words, two or more design choices are prepared for a given MOS 
logic circuit and, by selecting one of them in irreversible fashion in 
connection with any proper circuit operation, it is possible to implement 
a MOS logic circuit having a proper circuit arrangement free from any 
excess redundancy. 
This invention is not restricted to the above-mentioned embodiments and a 
variety of changes or modifications can be effected without departing from 
the scope and spirit of the invention. Although hereinbefore the NOR and 
NAND gates having two input signals have been explained, they may have 
three or more input signals. 
Further, in the aforementioned embodiments, the drain-source current path 
of said control circuit transistor, e.g. third transistor Qn2 in FIG. 5 is 
connected between said node for the output terminal Vout and one of the 
supply terminals, e.g. V.sub.SS through the source-drain current path of 
one of the transistors employed in a logic circuit, e.g. the second 
transistor Qn1. It is, of course possible to reverse this series 
connection of the drain-source current paths for the second and third 
transistors. Also, in FIG. 20 where the drain-source current path of the 
second transistor Q.sub.E3 to which gate electrode the first input signal 
is supplied, is connected between the node for Vout and V.sub.SS through 
the parallel-connected drain-source current paths of the third and fourth 
transistors Q.sub.E5 and Q.sub.E4 the irreversible control voltage maybe 
applied to the gate electrode of the third transistor Q.sub.E4 and the 
second input signal maybe applied to the gate electrode of the fourth 
transistor Q.sub.E5. 
As stated above, according to the invention, by varying the irreversible 
control voltage derived from the generator having, e.g. the fuse element, 
a MOS logic circuit can have, on one hand, the capacity to change the 
logic functions thereof, whereby there is one advantage in avoiding a 
design modification which would require a change of the logic functions as 
well as an extra design allowance with regard to the signal transmission 
speed, and also have, on the other hand, redundancy of a change of the 
transfer characteristics between the input/output signals with the logic 
functions thereof remaining unchanged, whereby there is another advantage 
to avoid requiring a design involving excess voltage allowance as well as 
excess operation allowance. 
Accordingly, the design for the MOS logic circuits according to the 
invention can be simplified, and it is possible to realize the MOS logic 
circuits cheaper in price without unnecessary allowances.