Active matrix substrate

Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).

TECHNICAL FIELD

The present invention relates to an active matrix substrate formed using an oxide semiconductor.

BACKGROUND ART

An active matrix substrate used in a liquid crystal display apparatus or the like includes a switching element such as a thin film transistor (hereinafter, referred to as a “TFT”) in each of pixels. As such a switching element, a TFT including an amorphous silicon film as an active layer (hereinafter, referred to as an “amorphous silicon TFT”) or a TFT including a polycrystalline silicon film as an active layer (hereinafter, referred to as a “polycrystalline silicon TFT”) is widely used conventionally.

Recently, it has been proposed to use, as a material of an active layer of a TFT, an oxide semiconductor instead of amorphous silicon or polycrystalline silicon. Such a TFT is referred to as an “oxide semiconductor TFT”. An oxide semiconductor has a mobility higher than that of amorphous silicon. Therefore, an oxide semiconductor TFT is operable at a higher speed than an amorphous silicon TFT.

Meanwhile, a technology of providing a driving circuit such as a gate driver, a source driver or the like on a substrate in a monolithic manner (integrally) is known. Such a driving circuit (monolithic driver) is usually formed using a TFT. Recently, a technology of producing a monolithic driver on a substrate using an oxide semiconductor TFT is used. With such a technology, the frame region is narrowed and the mounting process is simplified, and as a result, the cost is decreased.

A TFT included in a driving circuit (hereinafter, referred to as a “circuit TFT”) is generally produced in a step of producing a TFT to be located as a switching element in each of pixels (hereinafter, such a TFT will be referred to as a “pixel TFT”), namely, produced at the same time as the pixel TFT. Therefore, the circuit TFT and the pixel TFT are often formed of the same oxide semiconductor film and have the same structure as, or similar structures to, each other. However, the pixel TFT and the circuit TFT are required to have different characteristics from each other, and it is difficult to form an oxide semiconductor TFT having both of the characteristics.

In such a situation, it has been proposed to form a circuit TFT and a pixel TFT of different structures from each other. For example, Patent Document No. 1 discloses a structure in which a back-gate electrode is provided in a circuit TFT for the purpose of controlling the threshold voltage whereas no back-gate electrode is provided in a pixel TFT. The “back-gate electrode” is an additional gate electrode located to face a main gate electrode with a semiconductor layer being located between the back-gate electrode and the main gate electrode. In this specification, a TFT including a back-gate electrode may be referred to as a “back-gate structure TFT”.

FIG. 25provides cross-sectional views respectively showing two types of TFTs201and202disclosed in Patent Document No. 1. The TFT201is a pixel TFT, and the TFT202is a circuit TFT. These TFTs201and202are supported on a substrate1, and each include a gate electrode3, an oxide semiconductor layer5located on the gate electrode3with a gate insulating film4being located between the oxide semiconductor layer5and the gate electrode3, and a source electrode7and a drain electrode8connected with the oxide semiconductor layer5. The pixel TFT1is covered with a passivation layer (first inorganic insulating layer)11and an organic insulating layer12. The drain electrode8of the pixel TFT201is electrically connected with a pixel electrode PE located on the organic insulating layer12. The circuit TFT202includes a back-gate electrode BG located on the first inorganic insulating layer11so as to overlap the oxide semiconductor layer5. The organic insulating layer12is not provided between the first inorganic insulating layer11and the back-gate electrode BG. If the organic insulating layer12, which is relatively thick, is provided between the oxide semiconductor layer5and the back-gate electrode BG, the back-gate electrode BG may not be capable of appropriately controlling the threshold voltage of the back-gate structure TFT202.

In the structure shown inFIG. 25, a layer containing oxygen (e.g., an oxide layer formed of SiO2or the like) is preferably usable for the first inorganic insulating layer11in contact with the oxide semiconductor layer5. With such a structure, even if oxygen deficiency occurs to the oxide semiconductor layer, the oxide semiconductor layer is recovered from the oxygen deficiency by the oxygen contained in the oxide layer.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

Regarding an oxide semiconductor TFT, it is known that if reducing gas (e.g., hydrogen gas) contacts the oxide semiconductor layer during the production process of the TFT, oxygen deficiency occurs and thus the characteristics of the TFT are changed. It is also known that even after the production of the oxide semiconductor TFT, the characteristics of the TFT are changed if hydrogen or moisture invades the oxide semiconductor layer from outside. Specifically, if an n-type oxide semiconductor layer is reduced by the invasion of moisture or the like, the threshold voltage Vth is shifted to the negative side, and as a result, an off-leak current may be increased or a depletion state (normally-on state) may occur.

As a result of studies made by the present inventors, it has been found that especially in a circuit TFT, the amount of hydrogen or moisture invading the oxide semiconductor layer needs to be further decreased to suppress the occurrence of the depletion state. In a pixel TFT, even if the threshold voltage is shifted to the negative side, there is no problem as long as the off-leak current is sufficiently small when the gate voltage Vg is at a Low potential VGL (e.g., −6 V). By contrast, in a circuit TFT included in a peripheral circuit such as, for example, a gate driver, if an off-leak current flows even slightly due to the depletion at the gate voltage Vg=0 V, an operation abnormality may occur to the circuit.

As a result of further studies made by the present inventors based on the above-described knowledge, it has been found that in the circuit TFT201disclosed in Patent Document No. 1, it may be difficult to sufficiently suppress the invasion of moisture or the like into the oxide semiconductor layer5of the circuit TFT201from an area above the back-gate electrode BG. The oxide semiconductor layer5is covered with the inorganic insulating layer (preferably, silicon oxide film)11, but the moisture-preventive effect of the silicon oxide film is relatively small. Therefore, it may be difficult to sufficiently suppress the TFT from being put into a depletion state due to the invasion of moisture.

An embodiment of the present invention made in light of the above-described situation has an object of providing an active matrix substrate, including an oxide semiconductor TFT as each of a circuit TFT and a pixel TFT, that is capable of controlling the characteristics of each of the oxide semiconductor TFTs in accordance with the use thereof and is capable of suppressing the characteristics of the circuit TFT from being deteriorated due to moisture or hydrogen.

Solution to Problem

An active matrix substrate according to an embodiment of the present invention is an active matrix substrate including a display region including a plurality of pixels and a non-display region provided around the display region. The active matrix substrate includes a substrate; a first oxide semiconductor TFT supported by the substrate and provided in the non-display region; a peripheral circuit including the first oxide semiconductor TFT; a plurality of second oxide semiconductor TFTs supported by the substrate and provided in the display region; and a first inorganic insulating layer covering the plurality of second oxide semiconductor TFTs. The first oxide semiconductor TFT includes a lower gate electrode, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer located to face the lower gate electrode with the gate insulating layer being located between the oxide semiconductor layer and the lower gate electrode, a source electrode and a drain electrode each connected with the oxide semiconductor layer, and an upper gate electrode provided on the oxide semiconductor layer with an insulating layer including the first inorganic insulating layer being located between the upper gate electrode and the oxide semiconductor layer. The active matrix substrate further includes a second inorganic insulating layer provided on the upper gate electrode, the second inorganic insulating layer covering the first oxide semiconductor TFT.

In an embodiment, the active matrix substrate further includes an organic insulating layer located between the first inorganic insulating layer and the second inorganic insulating layer. The organic insulating layer has an opening located to overlap at least a part of the oxide semiconductor layer of the first oxide semiconductor TFT as seen in a direction normal to the substrate, and at least a part of the upper gate electrode is located in the opening of the organic insulating layer.

In an embodiment, the active matrix substrate further includes a transparent conductive layer located on the second inorganic insulating layer so as to overlap the upper gate electrode with the second inorganic insulating layer being located between the transparent conductive layer and the upper gate electrode.

In an embodiment, the transparent conductive layer covers at least a part of the peripheral circuit.

In an embodiment, the active matrix substrate further includes a lower transparent electrode provided on the first inorganic insulating layer in the display region, and an upper transparent electrode located on the lower transparent electrode with the second inorganic insulating layer being located between the upper transparent electrode and the lower transparent electrode. The upper gate electrode is formed of a same transparent conductive film as the lower transparent electrode, and the transparent conductive layer is formed of a same transparent conductive film as the upper transparent electrode.

In an embodiment, one of the lower transparent electrode and the upper transparent electrode is a pixel electrode, and the other of the lower transparent electrode and the upper transparent electrode is a common electrode.

In an embodiment, the active matrix substrate further includes a lower transparent electrode provided on the first inorganic insulating layer in the display region, an upper transparent electrode located on the lower transparent electrode with the second inorganic insulating layer being located between the upper transparent electrode and the lower transparent electrode, and another line located between the first inorganic insulating layer and the upper transparent electrode. One of the lower transparent electrode and the upper transparent electrode is a pixel electrode, the other of the lower transparent electrode and the upper transparent electrode is a common electrode, and the another line is not electrically connected with the pixel electrode or the common electrode.

In an embodiment, the upper gate electrode is formed of a same conductive film as the another line.

In an embodiment, the upper gate electrode has a stack structure including a lower layer formed of a same transparent conductive film as the lower transparent electrode and an upper layer formed of a same conductive film as the another line.

In an embodiment, the active matrix substrate further includes a third inorganic insulating layer provided on the upper gate electrode, the third inorganic insulating layer covering the first oxide semiconductor TFT.

In an embodiment, the transparent conductive layer is electrically connected with the common electrode.

In an embodiment, the active matrix substrate further includes an upper gate contact portion electrically connecting the upper gate electrode and the source electrode or the drain electrode of the first oxide semiconductor TFT to each other.

In an embodiment, the active matrix substrate further includes an upper gate contact portion electrically connecting the upper gate electrode and the lower gate electrode to each other.

In an embodiment, the active matrix substrate further includes an upper gate contact portion electrically connecting the upper gate electrode and the common electrode to each other.

In an embodiment, the active matrix substrate further includes an upper gate contact portion electrically connecting the upper gate electrode and the source electrode of the first oxide semiconductor TFT to each other, and a connection portion formed of a same transparent conductive film as the upper transparent electrode. In the upper gate contact portion, the upper gate electrode and the source electrode are connected to each other via the connection portion.

In an embodiment, as seen in a direction normal to the substrate, an outer edge of the oxide semiconductor layer is located inside an outer edge of the upper gate electrode, and a distance between the outer edge of the oxide semiconductor layer and the outer edge of the upper gate electrode is 1 μm or longer.

In an embodiment, as seen in a direction normal to the substrate, an outer edge of the upper gate electrode is located inside an outer edge of the transparent conductive layer, and a distance between the outer edge of the upper gate electrode and the outer edge of the transparent conductive layer is 1 μm or longer.

In an embodiment, the second inorganic insulating layer includes a silicon nitride layer.

In an embodiment, the first inorganic insulating layer includes a silicon oxide layer.

In an embodiment, the peripheral circuit includes a gate driver.

In an embodiment, the first oxide semiconductor TFT and the plurality of second oxide semiconductor TFTs are each an etch-stop TFT.

In an embodiment, the first oxide semiconductor TFT and the plurality of second oxide semiconductor TFTs are each a channel-etch TFT.

In an embodiment, the oxide semiconductor layer contains an In—Ga—Zn—O-based semiconductor.

In an embodiment, the In—Ga—Zn—O-based semiconductor includes a crystalline portion.

In an embodiment, the oxide semiconductor layer has a stack structure.

Advantageous Effects of Invention

According to an embodiment of the present invention, in an active matrix substrate including an oxide semiconductor TFT as each of a circuit TFT and a pixel TFT, the characteristics of each of the oxide semiconductor TFTs are controllable in accordance with the use thereof, and the characteristics of the circuit TFT are suppressed from being deteriorated due to the invasion of moisture or hydrogen into the oxide semiconductor layer.

DESCRIPTION OF EMBODIMENTS

An active matrix substrate according to an embodiment of the present invention includes a pixel TFT located as a switching element in each of pixels and circuit TFTs included in peripheral circuits. The pixel TFT and the circuit TFTs are provided on the same substrate. At least one of the circuit TFTs is an oxide semiconductor TFT having a back-gate structure (hereinafter, this TFT will be referred to as a “first TFT”). The pixel TFT is an oxide semiconductor TFT that is formed on the same substrate as the first TFT and includes no back-gate electrode (hereinafter, this TFT will be referred to as a “second TFT”). The first and second TFTs may be formed of the same oxide semiconductor film as each other. The active matrix substrate according to this embodiment may further include an oxide semiconductor TFT other than the first and second TFTs.

FIG. 1is a cross-sectional view showing a first TFT having a back-gate structure and a second TFT with no back-gate structure as examples. The TFTs101and102are supported on the same substrate1. In this example, the TFT102is a bottom-gate TFT and is covered with a first inorganic insulating layer11(passivation film).

The first TFT101includes a main gate electrode (hereinafter, referred to simply as the “gate electrode”)3A supported on the substrate1, a gate insulating layer4covering the gate electrode3A, an oxide semiconductor layer5A formed on the gate insulating layer4and acting as an active layer, a source electrode7A, a drain electrode8A, and a back-gate electrode BG located on the oxide semiconductor layer5A with an inorganic insulating layer including the first inorganic insulating layer11being located between the back-gate electrode BG and the oxide semiconductor layer5A. The oxide semiconductor layer5A is located to face the main gate electrode3A with the gate insulating layer4being located between the oxide semiconductor layer5A and the main gate electrode3A, and also to face the back-gate electrode BG with the first inorganic insulating layer11being located between the oxide semiconductor layer5A and the back-gate electrode BG. A second inorganic insulating layer17is located on the back-gate electrode BG so as to cover the first TFT101.

In this specification, among the main gate electrode and the back-gate electrode of the back-gate structure TFT, an electrode that is located on the substrate side with respect to the oxide semiconductor layer may be referred to as a “lower gate electrode”, and an electrode located on the oxide semiconductor layer may be referred to as an “upper gate electrode”. One of the upper electrode and the lower electrode acts as the “main gate electrode”, and the other electrode acts as the “back-gate electrode”, which is additional. In the example shown in the figure, the upper gate electrode is the back-gate electrode BG and the lower gate electrode is the main gate electrode3A.

The source electrode7A and the drain electrode8A are electrically connected with the oxide semiconductor layer5A. A region of the oxide semiconductor layer5A that is in contact with the source electrode7A is referred to as a “source contact region”, and a region of the oxide semiconductor layer5A that is in contact with the drain electrode8A is referred to as a “drain contact region”. A region of the oxide semiconductor layer5A that is located between the source contact region and the drain contact region and overlaps the gate electrode3A with the gate insulating layer4being located therebetween is a channel region.

The back-gate electrode BG is located on the oxide semiconductor layer5A with the first inorganic insulating layer11being located between the back-gate electrode BG and the oxide semiconductor layer5A. The first inorganic insulating layer11is a protective film (passivation film) covering the second TFT102. The back-gate electrode BG is located to overlap at least a part of the channel region of the oxide semiconductor layer5A as seen in a direction normal to the substrate.

In this example, the back-gate electrode BG is located to contact a top surface of the first inorganic insulating layer11and also to overlap the entirety of the oxide semiconductor layer5A as seen in the direction normal to the substrate. Between the oxide semiconductor layer5A and the back-gate electrode BG, only the first inorganic insulating layer11is located. Alternatively, another inorganic insulating layer (e.g., etch-stop layer described below) may further be located between the oxide semiconductor layer5A and the back-gate electrode BG. An insulating layer located between the oxide semiconductor layer5A and the back-gate electrode BG acts as an upper gate insulating layer.

The back-gate electrode BG may be electrically connected with the source electrode7A or the drain electrode8A of the first TFT101, or may be electrically connected with the gate electrode3A. Alternatively, the back-gate electrode BG may be electrically connected with a common electrode and set to have a common potential. Still alternatively, the back-gate electrode BG may be set to have a negative-side power supply potential VSS or may be connected with another, independent power supply.

Preferably, the first inorganic insulating layer11includes an oxide film in order to alleviate the oxygen deficiency occurring in the oxide semiconductor layer5A or an oxide semiconductor layer5B. The first inorganic insulating layer11may be, for example, an oxide film of silicon oxide or the like or a stack film including a silicon oxide layer and a silicon nitride layer stacked in this order (seeFIG. 5). The first inorganic insulating layer11has a thickness of, for example, 100 nm or greater and 500 nm or less. The second inorganic insulating layer17is, for example, a silicon nitride layer (thickness: e.g., 70 nm or greater and 300 nm or less).

The second TFT102has substantially the same structure as that of the first TFT101, but includes no back-gate electrode. The second TFT102includes a gate electrode3B supported on the substrate1, the gate insulating layer4covering the gate electrode3B, an oxide semiconductor layer5B formed on the gate insulating layer4and acting as an active layer, a source electrode7B, and a drain electrode8B. The source electrode7B and the drain electrode8B are electrically connected with the oxide semiconductor layer5B. The gate electrode3B is electrically connected with a gate line described below, and the source electrode7B is electrically connected with a source line described below. The drain electrode8B is electrically connected with a pixel electrode not shown. From the point of view of simplifying the production process, it is preferred that the gate electrode3B, the oxide semiconductor layer5B, the source electrode7B and the drain electrode8B are respectively formed in the same layers as the gate electrode3A, the oxide semiconductor layer5A, the source electrode7A and the drain electrode8A of the first TFT101.

The second TFT102merely needs to be covered with the first inorganic insulating layer11, and is not limited to having the TFT structure shown in the figure. The second TFT102may have a TFT structure different from that of the first TFT101.

According to this embodiment, the oxide semiconductor layer5A of the first TFT101is covered with the second inorganic insulating layer17located on the back-gate electrode BG in addition to with the first inorganic insulating layer11and the back-gate electrode BG. Therefore, the invasion of moisture into the oxide semiconductor layer5A is alleviated, and thus deterioration of the TFT characteristics due to the moisture is suppressed.

As described above, it is undesirably possible that the invasion of moisture into the oxide semiconductor layer5A is not suppressed merely by the first inorganic insulating layer11. It is preferred to use a silicon oxide layer as the first inorganic insulating layer11, but silicon oxide is poor in moisture resistance. A stack film including a silicon oxide layer and a silicon nitride layer may be used as the first inorganic insulating layer11. In this case, since a silicon nitride layer has a high moisture resistance, a higher moisture-preventive effect is provided than in the case where the first inorganic insulating layer11has a single-layer film structure formed of a silicon oxide layer. However, it is difficult to form the silicon nitride layer of the first inorganic insulating layer11to be sufficiently thick, and the thickness of the silicon nitride layer is suppressed to, for example, 100 nm or less. A reason for this is that if the silicon nitride layer is too thick, the oxide semiconductor may undesirably be reduced by hydrogen generated by the formation of the silicon nitride layer. Therefore, even if the stack film is used as the first inorganic insulating layer11, it may not be guaranteed that the invasion of moisture into the oxide semiconductor layer5A is suppressed sufficiently. By contrast, in this embodiment, the oxide semiconductor layer5A is covered with the second inorganic insulating layer17in addition to with the first inorganic insulating layer11. The second inorganic insulating layer17may include a nitride film such as, for example, a silicon nitride layer. The back-gate electrode BG is located between the second inorganic insulating layer17and the oxide semiconductor layer5A. Therefore, even in the case where the silicon nitride layer is formed as the second inorganic insulating layer17, the back-gate electrode BG blocks the invasion of hydrogen, desorbed from the second inorganic insulating layer17, into the oxide semiconductor layer5A. Therefore, a silicon nitride layer having a sufficient thickness (e.g., exceeding 100 nm) is allowed to be formed as the second inorganic insulating layer17. Thus, the first TFT101is more suppressed from being put into a depletion state due to the invasion of moisture than by a conventional structure.

FIG. 2throughFIG. 4respectively provide schematic cross-sectional views of the first TFT101and the second TFT102in modifications 1 through 3. InFIG. 2throughFIG. 4, elements substantially the same as those inFIG. 2bear the identical reference signs thereto. In the following, only differences fromFIG. 1will be described.

In modification 1 shown inFIG. 2, an organic insulating layer12is provided between the first inorganic insulating layer11and the second inorganic insulating layer17. The organic insulating layer12is thicker than the first inorganic insulating layer11, and has a thickness of, for example, 1 μm or greater and 3 μm or less. The organic insulating layer12is used to, for example, flatten a top surface of the second TFT102as the pixel electrode or decrease the static capacitance formed between the pixel electrode PE and the source line or the like.

In a display region, the second TFT102is covered with the first inorganic insulating layer11and the organic insulating layer12. The first inorganic insulating layer11and the organic insulating layer12will be collectively referred to as an “interlayer insulating layer13”. On the interlayer insulating layer13, the pixel electrode PE is formed. The pixel electrode PE is connected with the drain electrode8B of the second TFT102in a contact hole (not shown) formed in the interlayer insulating layer13.

In a non-display region, the organic insulating layer12has an opening12P above the first TFT101. The opening12P is located to overlap at least the channel region of the first TFT101as seen in the direction normal to the substrate1. The opening12P may be located to overlap the entirety of the oxide semiconductor layer5A. At least a part of the back-gate electrode BG is located to contact the first inorganic insulating layer11in the opening12P. The second inorganic insulating layer17is formed on the organic insulating layer12and the back-gate electrode BG. In this example, the entirety of the back-gate electrode BG is located in the opening12P. Alternatively, a part of the back-gate electrode BG may be located in the opening12P and the remaining part of the back-gate electrode BG may be located on a side surface and a top surface of the organic insulating layer12. As shown in the figure, the second inorganic insulating layer17may be in contact with the back-gate electrode BG.

According to modification 1, the organic insulating layer12is not located between the back-gate electrode BG and the oxide semiconductor layer5A. Therefore, the effect provided by the back-gate electrode BG (control on the threshold voltage, etc.) is provided certainly.

In modification 2 shown inFIG. 3, the first TFT101is covered with a transparent conductive layer30located on the second inorganic insulating layer17. As seen in the direction normal to the substrate, the transparent conductive layer30and the back-gate electrode BG overlap each other at least partially with the second inorganic insulating layer17being located between the transparent conductive layer30and the back-gate electrode BG. The transparent conductive layer30is provided, in addition to the back-gate electrode BG, the first inorganic insulating layer11and the second inorganic insulating layer17, on the oxide semiconductor layer5A, so that the invasion of humidity (moisture) into the oxide semiconductor layer5A is alleviated more effectively.

The transparent conductive layer30may be a shield layer provided to overlap at least a part of the peripheral circuit including the first TFT101. The transparent conductive layer (hereinafter, referred to as the “shield layer”)30is set to have, for example, the common potential. In the case where the back-gate electrode BG is not set to have the common potential (e.g., in the case where the back-gate electrode BG is connected with the gate electrode3A, the drain electrode8A or the source electrode7A), the shield layer30set to have the common potential may be provided. In this manner, the display characteristics are suppressed from being deteriorated due to the potential of the back-gate electrode BG charging a counter substrate (color filter substrate) located to face the active matrix substrate.

The problem caused by the counter substrate being charged is described in, for example, Japanese Laid-Open Patent Publication No. 2009-265484. When the counter substrate is charged, the display may undesirably be whitened in a peripheral region of the display region. By contrast, in modification 2, the charge of the counter substrate is alleviated, and therefore, the generation of such whitened display is suppressed.

In modification 3 shown inFIG. 4, the shield layer30is provided unlike in modification 1 (FIG. 2). The shield layer30is located on the second inorganic insulating layer17so as to cover the first TFT101. As seen in the direction normal to the substrate, the shield layer30and the back-gate electrode BG overlap each other at least partially. In this example, the shield layer30is located on the organic insulating layer12and in the opening12P, and overlaps the entirety of the back-gate electrode BG as seen in the direction normal to the substrate.

In each of the examples shown inFIG. 1throughFIG. 4, the first inorganic insulating layer11may be a stack film. A shown in, for example,FIG. 5, the first inorganic insulating layer11may have a stack structure including a silicon oxide layer (SiO2)11alocated on the substrate side and a silicon nitride (SiN) layer11blocated on the silicon oxide layer11a(on the back-gate BG side). In this example, the silicon oxide layer11ais located to contact the oxide semiconductor layer5A. A silicon nitride film has a moisture resistance higher than that of a silicon oxide film. Therefore, in the case where the first inorganic insulating layer11has such a stack structure, the invasion of hydrogen into the oxide semiconductor layer5A from the second inorganic insulating layer17is alleviated more effectively than in the case where the first inorganic insulating layer11has a single-layer structure formed of a silicon oxide layer.

<Positional Arrangement of the Back-Gate Electrode BG and the Shield Layer30>

Now, a preferred positional arrangement of the back-gate electrode BG, the oxide semiconductor layer5A and the shield layer30will be described. In this example, modification 3 will be described as an example. The same is applicable to the other examples shown inFIG. 1throughFIG. 4.

FIG. 6(a)is a cross-sectional view showing the first TFT101in modification 3 as an example.FIG. 6(b)is a plan view showing perimeters of the oxide semiconductor layer5A, the back-gate electrode BG and the shield layer30.

As shown in the figure, it is preferred that the back-gate electrode BG is located to overlap the entirety of the oxide semiconductor layer5A. Namely, it is preferred that as seen in the direction normal to the substrate, the outer edge of the oxide semiconductor layer5A is located inside the outer edge of the back-gate electrode BG. In order to cover the oxide semiconductor layer5A with the back-gate electrode BG more certainly, the oxide semiconductor layer5A and the back-gate electrode BG may be designed in consideration of the photoalignment precision, the variance in the line widths of the oxide semiconductor layer5A and the back-gate electrode BG, and the like. More specifically, the oxide semiconductor layer5A and the back-gate electrode BG may be designed such that, for example, width w2of the back-gate electrode BG in an arbitrary direction is longer than width w1of the oxide semiconductor layer5A in the arbitrary direction by 2 μm or greater, or 6 μm or greater depending on the alignment precision.

Distance d1between the outer edge of the oxide semiconductor layer5A and the outer edge of the back-gate electrode BG merely needs to exceed 0 μm. Distance d1is preferably 1 μm or longer, and more preferably 3 μm or longer. In other words, it is preferred that the shortest distance between the outer edge of the oxide semiconductor layer5A and the outer edge of the back-gate electrode BG is 1 μm or greater (or 3 μm or greater). With such a structure, the invasion of moisture into the oxide semiconductor layer5A is suppressed more effectively.

Especially in the case where the second inorganic insulating layer17is formed after the organic insulating layer12is formed (modifications 1 and 3), the second inorganic insulating layer17needs to be formed at a temperature lower than in a usual case. Therefore, the second inorganic insulating layer17contains a large amount of hydrogen. Hydrogen desorbed from the second inorganic insulating layer17may undesirably invade the oxide semiconductor layer5A, and as a result, the oxide semiconductor may undesirably be reduced to put the first TFT101into a depletion state. In the case where as shown inFIG. 6, the oxide semiconductor layer5A is covered with the back-gate electrode BG and distance d1is 1 μm or longer, the invasion of hydrogen desorbed from the second inorganic insulating layer17is suppressed more effectively.

In the meantime, in the case where the back-gate electrode BG is formed of a transparent conductive film, the adhesiveness between the back-gate electrode BG and the second inorganic insulating layer17formed thereon is low, and the second inorganic insulating layer17may undesirably be delaminated. Especially in the case where the stress difference between the second inorganic insulating layer17and the back-gate electrode BG is large, the second inorganic insulating layer17is easily delaminated. In order to suppress such delamination, it is preferred that the shield layer30is located to cover the back-gate electrode BG. Namely, it is preferred that as seen in the direction normal to the substrate, the outer edge of the back-gate electrode BG is located inside the outer edge of the shield layer30. For example, if the back-gate electrode BG has a compression stress and the second inorganic insulating layer17has a tensile stress, the back-gate electrode BG and the second inorganic insulating layer17are pulled in opposite directions from each other, and are easily delaminated from each other. However, in the case where the shield layer30having a compression stress is located on the second inorganic insulating layer17, the stress of the second inorganic insulating layer17is counteracted. Therefore, the stress difference between the second inorganic insulating layer17and the back-gate electrode BG is decreased, and the delamination is suppressed.

In order to cover the back-gate electrode BG with the shield layer30more certainly, the back-gate electrode BG and the shield layer30may be designed in consideration of the photoalignment precision and the variance in the line widths of the back-gate electrode BG and the shield layer30. More specifically, the shield layer30and the back-gate electrode BG may be designed such that, for example, the width of the shield layer30in an arbitrary direction is longer than width w2of the back-gate electrode BG in the arbitrary direction by 2 μm or greater, or 6 μm or greater depending on the alignment precision. Distance d2between the outer edge of the back-gate electrode BG and the outer edge of the shield layer30merely needs to exceed 0 μm. Distance d2is preferably 1 μm or longer, and more preferably 3 μm or longer. In other words, it is preferred that the shortest distance between the outer edge of the back-gate electrode BG and the outer edge of the shield layer30is 1 μm or greater (or 3 μm or greater). With such a structure, the delamination of the second inorganic insulating layer17is suppressed more effectively. Distance d2may be 3 μm or greater.

Hereinafter, embodiment 1 of the active matrix substrate according to the present invention will be described with reference to the drawings. The active matrix substrate according to this embodiment is widely applicable to a liquid crystal display apparatus, an organic EL display device, an inorganic EL display device or the like.

FIG. 7is a schematic plan view illustrating an active matrix substrate1001according to this embodiment.

The active matrix substrate1001includes a display region800including a plurality of pixel regions and a region900other than the display regions800(non-display region). The “pixel region” is a region corresponding to a pixel in a display device, and in this specification, may be referred to simply as a “pixel”.

In the display region800, a plurality of gate lines GL and a plurality of source lines SL are formed. Each of regions defined by these lines is the “pixel”. A plurality of such pixels are located in a matrix. In each of the pixels, a pixel TFT (not shown) is formed in the vicinity of each of intersections of the plurality of source lines SL and the plurality of gate lines GL. In this embodiment, an oxide semiconductor TFT of a bottom-gate structure that includes no back-gate electrode is used as the pixel TFT. A pixel electrode (not shown) is formed in each pixel. The drain electrode of each pixel TFT is electrically connected with the pixel electrode.

In the non-display region900, circuits such as a gate driver circuit940, an inspection circuit970, a source switching circuit950and the like; terminals electrically connecting a common line (COM line), the gate lines GL or the source lines SL with external lines; and the like are provided. In the non-display region900, a circuit TFT is formed as a circuit element of either one of the above-described circuits.

Now, a more specific structure of a part of the display region800and a part of the non-display region900will be described by way of an active matrix substrate usable for an FFS (Fringe Field Switching) mode display device as an example.

In an active matrix substrate usable in an FFS mode display device, a pixel TFT, a pixel electrode PE and a common electrode CE to be supplied with a common signal are provided in each of the pixel regions in the display region800. The pixel electrode PE and the common electrode CE are located to partially overlap each other with a dielectric layer (in this example, the second inorganic insulating layer) being located between the pixel electrode PE and the common electrode CE. The pixel electrode PE may be located on the common electrode CE with the dielectric layer being located therebetween. Alternatively, the common electrode CE may be located on the pixel electrode PE with the dielectric layer being located therebetween. In this specification, among the pixel electrode PE and the common electrode CE, an electrode that is located on the substrate side may be referred to as a “lower transparent electrode”, and the other electrode may be referred to as an “upper transparent electrode”.

In this embodiment, an example in which the lower transparent electrode is the common electrode CE and the upper transparent electrode is the pixel electrode PE will be described. Such an electrode structure is described in, for example, WO2011/086513. The lower transparent electrode may be the pixel electrode PE, and the upper transparent electrode may be the common electrode CE. Such an electrode structure is described in, for example, Japanese Laid-Open Patent Publication No. 2008-032899 and Japanese Laid-Open Patent Publication No. 2010-008758. The entirety of the disclosures of WO2011/086513, Japanese Laid-Open Patent Publication No. 2008-032899 and Japanese Laid-Open Patent Publication No. 2010-008758 are incorporated herein by reference.

FIG. 8is a schematic plan view showing the active matrix substrate1001according to this embodiment as an example.FIG. 9(a)andFIG. 9(b)are each a schematic cross-sectional view of the active matrix substrate1001, and respectively show cross-sectional structures taken along lines A-A and B-B inFIG. 8.FIG. 8andFIG. 9each show a circuit region910and a COM line region920in the non-display region900and one pixel region of the display region800. In the circuit region910, peripheral circuits are formed. In the COM line region920, the common line (COM line) is formed. The “pixel region” is a region corresponding to a pixel in the display device. The COM line region920is located, for example, between the display region800and the circuit region910as seen in the direction normal to the substrate. In the following, the same descriptions as those made above with reference toFIG. 1throughFIG. 5will be omitted appropriately.

In this example, the upper transparent electrode acts as the pixel electrode PE, and the lower transparent electrode acts as the common electrode CE. The back-gate electrode BG is formed of the same transparent conductive film as that of the common electrode CE. The shield layer30is formed of the same transparent conductive film as that of the pixel electrode PE.

In this specification, a layer formed of the same transparent conductive film as that of the lower transparent electrode (in this example, the common electrode CE) will be referred to as a “first transparent electrode layer15”, and a layer formed of the same transparent conductive film as that of the upper transparent electrode (in this example, the pixel electrode PE) will be referred to as a “second transparent electrode layer19”. In this example, the first transparent electrode layer15includes the common electrode CE and the back-gate electrode BG. The second transparent electrode layer19includes the pixel electrode PE and the shield layer30.

In each of the pixel regions of the display region800, the second TFT102as the pixel TFT, the source line SL, the gate line GL, the interlayer insulating layer13covering the source line SL and the gate line GL, the common electrode CE provided on the interlayer insulating layer13, and the pixel electrode PE located on the common electrode CE with the second inorganic insulating layer17being provided between the pixel electrode PE and the common electrode CE are formed.

The second TFT102has substantially the same structure as that in modification 3 shown inFIG. 4.

The common electrode CE may be formed in substantially the entirety of the display region without being divided in correspondence with the pixels. The common electrode CE has an opening15pon the drain electrode8B of the second TFT102in each of the pixel regions. A pixel contact hole described below is formed in the opening15p. In this example, the common electrode CE covers substantially the entirety of the display region except for regions located on the pixel contact holes.

The pixel electrode PE is provided in each of the pixels. The pixel electrode PE in each pixel has at least one slit or cutout. The pixel electrode PE is electrically connected with the drain electrode8B of the corresponding second TFT102in the pixel contact hole formed in the interlayer insulating layer13and the second inorganic insulating layer17. In this example, as seen in the direction normal to the substrate, the pixel contact hole is located inside the opening15p. As seen in the direction normal to the substrate, the pixel contact hole includes an opening12Q formed in the organic insulating layer12and openings11pand7pformed inside the opening12Q and formed in the first inorganic insulating layer11and the second inorganic insulating layer17.

In the circuit region910, a peripheral circuit including the first TFT101is formed. The peripheral circuit is, for example, a gate driver. The first TFT101may be an output driver of the gate driver. In this example, the first TFT101has substantially the same structure as that in modification 3 described above. Namely, the back-gate electrode BG of the first TFT101is located in the opening12P of the organic insulating layer12. On the back-gate electrode BG, the shield layer30is formed with the second inorganic insulating layer17being located between the shield layer30and the back-gate electrode BG. As described above, in this example, the back-gate electrode BG is formed in the first transparent electrode layer15, and the shield layer30is formed in the second transparent electrode layer19.

In the circuit region910, a back-gate contact portion (also referred to as an “upper gate contact portion”)40electrically connecting the back-gate electrode BG with the source electrode7A or the drain electrode8A (in this example, the source electrode7A) of the first TFT101is provided. The back-gate contact portion40is located in the opening12P of the organic insulating layer12so as to be adjacent to the first TFT101.

In this example, the back-gate contact portion40is located in an opening30tof the shield layer30, and includes a transparent connection portion32formed of the same transparent conductive film as that of the shield layer30(namely, formed in the second transparent electrode layer19). The transparent connection portion32is electrically isolated from the shield layer30. In the back-gate contact portion40, the back-gate electrode BG is electrically connected with the source electrode7A via the transparent connection portion32. Specifically, an opening17sexposing the back-gate electrode BG is formed in the second inorganic insulating layer17, and a back-gate contact hole exposing the source electrode7A is formed in the back-gate electrode BG, the second inorganic insulating layer17and the first inorganic insulating layer11. As seen in the direction normal to the substrate, the back-gate contact hole includes an opening15tformed in the back-gate electrode BG and openings17tand11tformed in the second inorganic insulating layer17and the first inorganic insulating layer11and located inside the opening15t. The transparent connection portion32is formed on the second inorganic insulating layer17, in the opening17sand in the back-gate contact hole, is in contact with the back-gate electrode BG in the opening17s, and is in contact with the source electrode7A in the back-gate contact hole.

The source electrode7A of the first TFT101may be connected with the gate line GL. In this example, the source electrode7A is in direct contact with the gate line GL in an opening formed in the gate insulating layer4.

The shield layer30is located to cover at least a part of the peripheral circuit (in this example, gate driver). Preferably, the shield layer30overlaps the back-gate electrode BG at least partially as seen in the direction normal to the substrate. More preferably, the shield layer30is located to overlap the entirety of the back-gate electrode BG. In this example, the shield layer30covers the circuit region910except for a region where the back-gate contact portion40is formed.

In the COM line region920, a COM contact portion50is provided. The COM contact portion50electrically connects the common electrode CE extending from the pixel region and the shield layer30extending from the circuit region910with a common line (COM line)7C. The COM line7C is formed of, for example, the same conductive film as that of the source line SL.

In this example, in the COM contact region920, the common electrode CE is electrically connected with the COM line7C via the shield layer30. Specifically, an opening17qexposing the common electrode CE is formed in the second inorganic insulating layer17, and a COM contact hole exposing the COM line7C is formed in the second inorganic insulating layer17and the interlayer insulating layer13. As seen in the direction normal to the substrate, the COM contact hole includes an opening12R formed in the organic insulating layer12and openings17rand11rformed in the second inorganic insulating layer17and the first inorganic insulating layer11and located inside the opening12R. The shield layer30is formed on the second inorganic insulating layer17, in the opening17qand in the COM contact hole, is in contact with the common electrode CE in the opening17q, and is in contact with the COM line7C in the COM contact hole.

The structure of the active matrix substrate according to this embodiment is not limited to the structure shown inFIG. 8andFIG. 9. For example, the back-gate electrode BG is connected with the source electrode7A in the back-gate contact region40. Alternatively, the back-gate electrode BG may be connected with the drain electrode8A or the gate electrode3A. Still alternatively, the back-gate electrode BG may be electrically connected with the common electrode CE. The back-gate electrode BG may be connected with another power supply. The planar shape of each layer, the positional arrangement of the layers, and the like are not limited to those shown in the figures.

In the case where the back-gate electrode BG is connected with the common electrode CE, the shield layer30may or may not overlap the first TFT101. Even if the shield layer30does not overlap the first TFT101, the display characteristics are suppressed from being deteriorated due to the charge because the back-gate electrode BG acts also as a shield layer. It should be noted that in the case where the shield layer30overlaps the first TFT101, the invasion of moisture or the like into the oxide semiconductor layer5A is suppressed more effectively.

For example, Japanese Laid-Open Patent Publication No. 2014-103142 proposes a structure in which a back-gate electrode is provided on an organic insulating layer. However, in the case where the back-gate electrode is provided on the organic insulating layer, the organic insulating layer, which is relatively thick, is located between the semiconductor layer and the back-gate electrode. This decreases the effect of suppressing the change in the threshold voltage. By contrast, in this embodiment, the opening12P is formed in the organic insulating layer12, and therefore, no organic insulating layer is located between the back-gate electrode BG and the oxide semiconductor layer5A. Only a relatively thin inorganic insulating layer (in an etch-stop structure, the first inorganic insulating layer11and the etch-stop layer; and in a channel-etch structure, the first inorganic insulating layer11) is located between the back-gate electrode BG and the oxide semiconductor layer5A. For this reason, the control on the threshold value of the first TFT101by the back-gate electrode BG is performed more appropriately.

<Method for Producing the Active Matrix Substrate1001>

With reference toFIG. 8andFIG. 9, a method for producing the active matrix substrate1001will be described.

First, a circuit including the first TFT101, the second TFT102, the gate line GL, the source line SL and the like are formed on the substrate by a known method.

Specifically, a gate line layer including the gate line GL and the gate electrodes3A and3B is formed on the substrate. As the substrate, for example, a glass substrate, a silicon substrate, a heat-resistant plastic substrate (resin substrate) or the like is usable. The gate line layer is obtained by forming a conductive film for the gate (thickness: e.g., 50 nm or greater and 500 nm or less) on the substrate1by sputtering or the like and patterning the conductive film. As the conductive film for the gate, a film containing a metal material such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Co) or the like, an alloy thereof, or a metal nitride thereof is appropriately usable. Alternatively, a stack film including a plurality of such films in a stacked manner is usable. A Cu film and a Ti film are formed in this order to obtain the stack film.

Next, a gate insulating layer (thickness: e.g., 200 nm or greater and 500 nm or less)4is formed by CVD or the like so as to cover the gate line layer. As the gate insulating layer4, a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, a silicon oxide nitride (SiOxNy; x>y) layer, a silicon nitride oxide (SiNxOy; x>y) layer or the like is appropriately usable. The gate insulating layer4may have a stack structure. In this example, a stack film including an SiNxlayer as a lower layer and an SiOxlayer as an upper layer is used.

Next, an oxide semiconductor film is formed on the gate insulating layer4, and the oxide semiconductor film (thickness: e.g., 15 nm or greater and 200 nm or less) is patterned, so that the oxide semiconductor layer5A to act as the active layer of the first TFT101and the oxide semiconductor layer5B to act as the active layer of the second TFT102are formed. The oxide semiconductor film may have a stack structure.

Next, an opening4ureaching the gate line GL is formed in the gate insulating layer4by known photolithography.

Then, a conductive film for the source (thickness: e.g., 50 nm or greater and 500 nm or less) is formed on the substrate and is patterned, so that the source line SL, the source electrodes7A and7B and the drain electrodes8A and8B in contact with the oxide semiconductor layers5A and5B, and the COM line7C are formed. Thus, the first TFT101and the second TFT102are obtained. As the conductive film for the source, a film containing a metal material such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Co) or the like, an alloy thereof, or a metal nitride thereof is appropriately usable. Alternatively, a stack film including a plurality of such films in a stacked manner is usable. Still alternatively, a conductive oxide film of IZO (In—Zn—O) or the like is usable. In this example, a Ti film and a Cu film are formed in this order to obtain the stack film.

Next, the first inorganic insulating layer (thickness: e.g., 100 to 500 nm, preferably 200 to 500 nm)11is formed by, for example, CVD so as to cover the first TFT101and the second TFT102.

As the first inorganic insulating layer11, an inorganic insulating film (passivation film) such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxide nitride (SiOxNy; x>y) film, a silicon nitride oxide (SiNxOy; x>y) film or the like is usable. As described above, it is preferred to use an silicon oxide film from the point of view of recovering the oxide semiconductor layers5A and5B from oxygen deficiency. Alternatively, the first inorganic insulating layer11may be a stack film. In this example, a stack film including an SiOxfilm as a lower layer and an SiNxfilm as an upper layer is formed as the first inorganic insulating layer11.

Next, an organic insulating layer (thickness: e.g., 1 to 3 μm, preferably 2 to 3 μm)12is formed on the first inorganic insulating layer11. As the organic insulating layer12, an organic insulating film containing a photosensitive resin material may be formed. Next, the organic insulating layer12is patterned by a photolithography step, so that the openings12P,12Q and12R are formed in the organic insulating layer12. The opening12P is located to expose a portion of the first inorganic insulating layer11that is located above the first TFT101. The opening12Q is located in each pixel region of the display region800so as to expose a part of the drain electrode8B. The opening12R is located on the COM line7C in the COM line region920.

Next, a first transparent conductive film (thickness: e.g., 50 nm or greater and 200 nm or less) is formed on the organic insulating layer12and in the openings12P,12Q and12R. As the first transparent conductive film, for example, an ITO (indium tin oxide) film, an In—Zn—O-based oxide (indium zinc oxide) film, a ZnO film (zinc oxide film) or the like is usable.

Next, the first transparent conductive film is patterned, so that the first transparent electrode layer15including the common electrode CE and the back-gate electrode BG is formed. The back-gate electrode BG is located in the opening12P of the organic insulating layer12, and includes the opening15texposing the first inorganic insulating layer11. The common electrode CE is provided in substantially the entirety of the display region800. As seen in the direction normal to the substrate, the common electrode CE includes the opening15plocated outside the opening12Q The common electrode CE is not formed in a region of the COM line7C where the COM contact portion50is to be formed. In this example, the common electrode CE covers a part of the COM line7C, and has an end portion15eon the COM line7C.

Next, the second inorganic insulating layer17is formed to cover the first transparent electrode layer15. As the second inorganic insulating layer17, a silicon nitride (SiNx) film, a silicon oxide (SiOx) film, a silicon oxide nitride (SiOxNy; x>y) film, a silicon nitride oxide (SiNxOy; x>y) film or the like is appropriately usable. In the case where a storage capacitance is formed by the common electrode CE, the second inorganic insulating layer17and the pixel electrode PE, SiNxis preferably usable as the second inorganic insulating layer17from the points of view of the dielectric constant and the insulating property. SiNxalso has a high moisture resistance and thus more effectively suppresses the invasion of moisture into the oxide semiconductor layer5A. The second inorganic insulating layer17has a thickness of, for example, 70 nm or greater and 300 nm or less.

Then, a resist layer (not shown) is formed, and the second inorganic insulating layer17and the first inorganic insulating layer11are etched, using the resist layer and the organic insulating layer12as an etching mask. The second inorganic insulating layer17and the first inorganic insulating layer11may be etched at the same time. In this case, end surfaces of the second inorganic insulating layer17and the first inorganic insulating layer11are aligned to each other.

As a result of the above-described etching, in the opening12Q, an opening17pand the opening lip are formed in the second inorganic insulating layer17and the first inorganic insulating layer11, so that the pixel contact hole is obtained. In the opening12R, the openings17rand11rare formed in the second inorganic insulating layer17and the first inorganic insulating layer11, so that the COM contact hole is obtained. In the opening15tof the back-gate electrode BG, the openings17tand11tare formed in the second inorganic insulating layer17and the first inorganic insulating layer11, so that the back-gate contact hole is obtained. The openings17qand17aare formed in the second inorganic insulating layer17, using the common electrode CE and the back-gate electrode BG as an etch-stop.

Next, a second transparent conductive film is formed on the second inorganic insulating layer17and in the contact holes and is patterned, so that the second transparent electrode layer19including the pixel electrode PE, the shield layer30and the transparent connection portion32is formed. The pixel electrode PE is located to contact the drain electrode8B in the pixel contact hole. The shield layer30is located to overlap at least a part of the first TFT101and at least a part of the peripheral circuit. The shield layer30contacts the COM line7C in the COM contact hole, and contacts the common electrode CE in the opening17q. The transparent connection portion32is located to contact the back-gate electrode BG in the opening17aand to contact the source electrode7A in the back-gate contact hole. The preferred material and the thickness of the second transparent conductive film may be the same as those of the first transparent conductive film. In this manner, the active matrix substrate1001is produced.

According to the above-described method, the active matrix substrate1001is produced by use of a conventional process for producing a TFT substrate for a display device, with no addition of a step of providing the back-gate electrode BG.

FIG. 10is a schematic plan view showing another active matrix substrate1002according to this embodiment as an example.FIG. 11(a)andFIG. 11(b)are each a schematic cross-sectional view of the active matrix substrate1002, and respectively show cross-sectional structures taken along lines A-A and B-B inFIG. 10. InFIG. 10andFIG. 11, elements substantially the same as those inFIG. 8andFIG. 9bear the identical reference signs thereto. The active matrix substrate1002and the active matrix substrate1001shown inFIG. 8andFIG. 9are different from each other in the structures of the back-gate contact portion40and the COM contact portion50. In the following, differences from the active matrix substrate1001will be described, and the same descriptions as those made above will be omitted appropriately.

In the back-gate contact portion40, the back-gate electrode BG is in contact with the source electrode7A in the opening11t(back-gate contact hole) formed in the first inorganic insulating layer11. In this example, there is no need to form an opening for forming the back-gate contact hole in the shield layer30. Therefore, as shown in the figures, the shield layer30may be located to cover the entirety of the first TFT101and the entirety of the back-gate contact portion40.

In the COM contact portion50, the common electrode CE is in direct contact with the COM line7C in the opening (COM contact hole)11rformed in the first inorganic insulating layer11. The shield layer30is in contact with the common electrode CE in the opening17qformed in the second inorganic insulating layer17. In this example, the common electrode CE, the second inorganic insulating layer17and the shield layer30are located to cover the COM contact portion50. The shield layer30extending to the COM line region920has an end portion30eon, for example, the COM line7C.

In the active matrix substrate1001shown inFIG. 8andFIG. 9, the back-gate electrode BG is connected with the source electrode7A via the transparent connection portion formed of the same transparent conductive film as that of the shield layer30. Therefore, the region where the back-gate contact portion40is formed is not allowed to be covered with the shield layer30. By contrast, in the active matrix substrate1002, the entirety of the back-gate contact portion40is allowed to be covered with the shield layer30. Therefore, the display characteristics are suppressed more effectively from being deteriorated due to the charge.

Now, with reference toFIG. 10andFIG. 11, a method for producing the active matrix substrate1002will be described. In the following, only differences from the method for producing the active matrix substrate1001will be described. The materials, the thicknesses, the formation processes and the like of the layers are substantially the same as those for the active matrix substrate1001, and the same descriptions as those made above will be omitted appropriately.

The peripheral circuit including the first TFT101, the second TFT102, the gate line GL, the source line SL, the COM line7C and the like are formed on the substrate by substantially the same method as for the active matrix substrate1001. Then, the first inorganic insulating layer11and the organic insulating layer12are formed in this order by, for example, CVD so as to cover the first TFT101and the second TFT102. In the organic insulating layer12, the openings12P,12R and12Q are formed.

After the organic insulating layer12is formed, the first inorganic insulating layer11is etched, using the resist layer (not shown) and the organic insulating layer12as an etching mask. In this example, in the COM line region920, the opening11rexposing the COM line7C is formed in the opening12R of the organic insulating layer12. In the circuit region910, the opening11texposing the source electrode7A is formed in the opening12P of the organic insulating layer12.

Next, the first transparent conductive film is formed on the organic insulating layer12and in the openings and is patterned, so that the first transparent electrode layer15including the common electrode CE and the back-gate electrode BG is formed. The common electrode CE is located to have the opening15pon the drain electrode8B and to contact the COM line7C in the opening11rin the COM line region920. The back-gate electrode BG is located to contact the source electrode7A in the opening11t.

Next, the second inorganic insulating layer17covering the first TFT101and the second TFT102is formed. Then, the resist layer (not shown) is formed, and the second inorganic insulating layer17and the first inorganic insulating layer11are etched, using the resist layer and the organic insulating layer12as an etching mask, so that the openings17pand11pare formed. In this manner, the pixel contact hole is obtained.

Next, the second transparent conductive film is formed on the second inorganic insulating layer17and in the pixel contact hole and is patterned, so that the second transparent electrode layer19including the pixel electrode PE and the shield layer30is formed. The pixel electrode PE contacts the drain electrode8B in the pixel contact hole. The shield layer30is located to contact the common electrode CE in the opening17q. As a result, the shield layer30is electrically connected with the COM line7C via the common electrode CE. In this manner, the active matrix substrate1002is produced.

FIG. 12provides cross-sectional views showing still another active matrix substrate according to this embodiment. A plan view is substantially the same asFIG. 8and thus will be omitted.FIG. 12(a)andFIG. 12(b)respectively show cross-sectional structures taken along lines A-A and B-B inFIG. 8.

In an active matrix substrate1003shown inFIG. 12, the first TFT101and the second TFT102are etch-stop TFTs, unlike in the active matrix substrate1001(FIG. 8andFIG. 9). In the following, differences from the active matrix substrate1001will be described, and the same descriptions as those made above will be omitted appropriately.

The oxide semiconductor layer5A of the first TFT101and the oxide semiconductor layer5B of the first TFT102are covered with an etch-stop layer9. The etch-stop layer9is an inorganic insulating layer. In the etch-stop layer9, openings reaching the source contact regions and the drain contact regions of the oxide semiconductor layers5A and5B are formed. The source and drain electrodes7A,8A,7B and8B are in contact with the oxide semiconductor layers5A and5B in the openings of the etch-stop layer9. It is sufficient that the etch-stop layer9covers at least the channel regions of the oxide semiconductor layers5A and5B, and the etch-stop layer9is not limited to having the structure shown in the figures.

In the active matrix substrate1003, in the first TFT101, the first inorganic insulating layer11and the etch-stop layer9are located between the back-gate electrode BG and the oxide semiconductor layer5B, and act together as the upper gate insulating layer.

The active matrix substrate1003may be produced by substantially the same method as for the active matrix substrate1001. It should be noted that the etch-stop layer9is formed after the oxide semiconductor layers5A and5B are formed but before a source line layer is formed. As the etch-stop layer9, a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, a silicon oxide nitride (SiOxNy; x>y) layer, a silicon nitride oxide (SiNxOy; x>y) layer or the like is appropriately usable. The etch-stop layer9may have a stack structure. The etch-stop layer9may have a thickness of, for example, 30 nm or greater and 200 nm or less. Then, the etch-stop layer9is patterned, so that the openings exposing the source contact regions and the drain contact regions of the oxide semiconductor layers5A and5B are formed. Then, a source conductive film is formed and is patterned, so that the source line layer including the source electrodes7A and7B and the drain electrodes8A and8B is obtained. In this patterning (source/drain separation) step, the etch-stop layer9acts as a protective layer for the oxide semiconductor layers5A and5B.

In an active matrix substrate according to embodiment 2, the upper transparent electrode acts as the common electrode CE and the lower transparent electrode acts as the pixel electrode PE, unlike in the active matrix substrate according to embodiment 1. In this embodiment, the back-gate electrode BG of the first TFT is formed of the same transparent conductive film as that of the pixel electrode PE, and the shield layer30is formed of the same transparent conductive film as that of the common electrode CE.

FIG. 13is a schematic plan view showing an active matrix substrate1004according to this embodiment as an example.FIG. 14(a)andFIG. 14(b)are each a schematic cross-sectional view of the active matrix substrate1004, and respectively show cross-sectional structures taken along lines A-A and B-B inFIG. 13. InFIG. 13andFIG. 14, elements substantially the same as those inFIG. 8throughFIG. 10bear the identical reference signs thereto. In the following, differences from the active matrix substrate1002will be described, and the same descriptions as those made above will be omitted appropriately.

In each of the pixel regions of the display region800, the second TFT102as the pixel TFT, the source line SL, the gate line GL, the interlayer insulating layer13covering the source line SL and the gate line GL, the pixel electrode PE provided on the interlayer insulating layer13, and the common electrode CE located on the pixel electrode PE with the second inorganic insulating layer17being located between the common electrode CE and the pixel electrode PE are formed.

The pixel electrode PE is provided in each of the pixels. The pixel electrode PE is connected with the drain electrode8B of the second TFT102in the pixel contact hole formed in the interlayer insulating layer13. In this example, the pixel contact hole includes the opening12Q formed in the organic insulating layer12and the opening11pformed in the first inorganic insulating layer11. The opening11pis located inside the opening12Q of the organic insulating layer12as seen in the direction normal to the substrate.

The common electrode CE does not need to be provided in each of the pixels. In this example, the common electrode CE is formed in substantially the entirety of the display region, and has at least one slit or cutout in each pixel region.

In the COM contact portion50, the common electrode CE is electrically connected with the common line7C in the COM contact hole. As seen in the direction normal to the substrate, the COM contact hole includes the openings12R and11rformed in the organic insulating layer12and the first inorganic insulating layer11and the opening17rformed in the second inorganic insulating layer17and located inside the opening12R. The common electrode CE extends to the circuit region910and acts also as the shield layer30. Namely, the common electrode CE and the shield layer30are formed integrally (continuously) with each other and may have the same potential as each other. Therefore, in this embodiment, a contact portion connecting the shield layer30and the common electrode CE to each other is not needed.

The structures of the first TFT101and the back-gate contact portion40in the circuit region910are substantially the same as those in the active matrix substrate1002shown inFIG. 10andFIG. 11.

<Method for Producing the Active Matrix Substrate1004>

With reference toFIG. 13andFIG. 14, a method for producing the active matrix substrate1004will be described. In the following, only differences from the method for producing the active matrix substrate1002(FIG. 10andFIG. 11) will be described. The materials, the thicknesses, the formation processes and the like of the layers are substantially the same as those for the active matrix substrate1001and the active matrix substrate1002, and the same descriptions as those made above will be omitted appropriately.

First, the peripheral circuit including the first TFT101, the second TFT102, the gate line GL, the source line SL, the COM line7C and the like are formed on the substrate. Then, the first inorganic insulating layer11and the organic insulating layer12are formed in this order by, for example, CVD so as to cover the first TFT101and the second TFT102. In the organic insulating layer12, the openings12P,12R and12Q are formed as in the above-described embodiment.

After the organic insulating layer12is formed, the first inorganic insulating layer11is etched, using the resist layer (not shown) and the organic insulating layer12as an etching mask. In the display region800, the opening11pis formed in the first inorganic insulating layer11in the opening12Q, so that the pixel contact hole is obtained. In the COM line region920, the opening11ris formed in the first inorganic insulating layer11in the opening12R. In the circuit region910, the opening11tis formed in the first inorganic insulating layer11in the opening12P, so that the back-gate contact hole is obtained.

Next, the first transparent conductive film is formed on the organic insulating layer12and in the openings and is patterned, so that the first transparent electrode layer15including the pixel electrode PE and the back-gate electrode BG is formed. In the display region800, the pixel electrode PE is provided on the organic insulating layer12and in the pixel contact hole, and is located to contact the drain electrode8B in the pixel contact hole. The back-gate electrode BG is located to contact the source electrode7A in the opening11t.

Next, the second inorganic insulating layer17covering the first TFT101and the second TFT102is formed. Then, the opening17ris formed in the second inorganic insulating layer17in the opening12R, using the resist layer (not shown) as an etching mask, so that the COM contact hole is obtained.

Next, the second transparent conductive film is formed on the second inorganic insulating layer17and in the COM contact hole and is patterned, so that the second transparent electrode layer19including the common electrode CE and the shield layer30is obtained. The shield layer30and the common electrode CE are formed integrally with each other and contact the COM line7C in the COM contact hole. In this manner, the active matrix substrate1004is produced.

In an active matrix substrate according to embodiment 3, the interlayer insulating layer13includes no organic insulating layer, unlike in the active matrix substrate according to embodiment 1 or 2.

FIG. 15is a schematic plan view showing an active matrix substrate1005according to this embodiment as an example.FIG. 16(a)andFIG. 16(b)are each a schematic cross-sectional view of the active matrix substrate1005, and respectively show cross-sectional structures taken along lines A-A and B-B inFIG. 15. InFIG. 15andFIG. 16, elements substantially the same as those inFIG. 8throughFIG. 14bear the identical reference signs thereto. In this embodiment, an example in which the upper transparent electrode acts as the common electrode CE and the lower transparent electrode acts as the pixel electrode PE will be described. Alternatively, the upper transparent electrode may act as the pixel electrode PE and the lower transparent electrode may act as the common electrode CE. In the following, differences from the active matrix substrate1004(FIG. 13andFIG. 14) according to embodiment 2 will be described, and the same descriptions as those made above will be omitted appropriately.

In the active matrix substrate1005, the first TFT101and the second TFT102have substantially the same structures as those in modification 2 shown inFIG. 3. The interlayer insulating layer13includes the inorganic insulating layer (passivation layer)11but does not include a flattening film or an organic insulating film.

In the display region800, the first inorganic insulating layer11is formed to cover the second TFT102, and the pixel electrode PE is provided on the first inorganic insulating layer11. The pixel electrode PE is in contact with the drain electrode8B in the opening11p(pixel contact hole) formed in the first inorganic insulating layer11. On the pixel electrode PE, the second inorganic insulating layer17and the common electrode CE are provided.

In the COM line region920, the common electrode CE is in contact with the COM line7C in the COM contact hole formed in the first inorganic insulating layer11and the second inorganic insulating layer12. In this example, as seen in the direction normal to the substrate, the COM contact hole includes the opening11rformed in the first inorganic insulating layer11and the opening17rformed in the second inorganic insulating layer17and located inside the opening11r. It is sufficient that the opening17ris located to overlap the opening11rat least partially as seen in the direction normal to the substrate.

The circuit region910has substantially the same structure as that in the active matrix substrate1004except that the organic insulating layer12is not formed in this embodiment. In this example also, the shield layer30is formed integrally with the common electrode CE and has the common potential.

In the active matrix substrate1004according to the above-described embodiment, the second inorganic insulating layer17, which acts as a protective film, is formed on the organic insulating layer. Therefore, it is difficult to form the second inorganic insulating layer17at a high temperature. The temperature at which the second inorganic insulating layer17is to be formed is set to, for example, 150° C. or higher and 200° C. or lower. Therefore, the amount of hydrogen contained in the formed second inorganic insulating layer17may possibly be increased. By contrast, in this embodiment, the organic insulating layer is not formed. Therefore, the second inorganic insulating layer17is allowed to be formed at a higher temperature (e.g., 200° C. or higher and 350° C. or lower). Since the amount of hydrogen contained in the formed second inorganic insulating layer17is decreased for this reason, the first TFT101is suppressed more effectively from being put into a depletion state due to hydrogen desorbed from the second inorganic insulating layer17(desorbed hydrogen).

<Method for Producing the Active Matrix Substrate1005>

With reference toFIG. 15andFIG. 16, a method for producing the active matrix substrate1005will be described. In the following, only differences from the method for producing the active matrix substrate1004will be described, and the same descriptions as those made above will be omitted appropriately.

First, the peripheral circuit including the first TFT101, the second TFT102, the gate line GL, the source line SL, the COM line7C and the like are formed on the substrate. Then, the first inorganic insulating layer11is formed by, for example, CVD so as to cover the first TFT101and the second TFT102.

Then, the first inorganic insulating layer11is etched, using the resist layer (not shown). In the display region800, the opening lip is formed in the first inorganic insulating layer11, so that the pixel contact hole exposing the drain electrode8B of the second TFT102is obtained. In the COM line region920, the opening11rexposing the COM line7C is formed in the first inorganic insulating layer11. In the circuit region910, the opening11texposing the source electrode7A is formed in the first inorganic insulating layer11, so that the back-gate contact hole exposing the source electrode7A of the first TFT101is obtained.

Next, the first transparent conductive film is formed on the first inorganic insulating layer11and is patterned, so that the first transparent electrode layer15including the pixel electrode PE and the back-gate electrode BG is formed. In the display region800, the pixel electrode PE is provided on the first inorganic insulating layer11and in the pixel contact hole, and is located to contact the drain electrode8B in the pixel contact hole. The back-gate electrode BG is located to contact the source electrode7A in the opening11t.

Next, the second inorganic insulating layer17covering the first TFT101and the second TFT102is formed. Then, the opening17rexposing the COM line7C is formed in the second inorganic insulating layer17, using the resist layer (not shown) as an etching mask. The opening17ris located inside the opening11rof the first inorganic insulating layer11. In this manner, the COM contact hole is obtained.

Next, the second transparent conductive film is formed on the second inorganic insulating layer17and in the COM contact hole and is patterned, so that the second transparent electrode layer19including the common electrode CE and the shield layer30is obtained. The shield layer30and the common electrode CE are formed integrally with each other and contact the COM line7C in the COM contact hole. In this manner, the active matrix substrate1005is produced.

An active matrix substrate according to embodiment 4 further includes another line layer, different from the first transparent electrode layer15or the second transparent electrode layer19, between the interlayer insulating layer13and the second transparent electrode layer19. The another line layer is, for example, a metal line layer. This line layer may include another line electrically isolated from the pixel electrode and the common electrode. This line layer is usable as a driving line for, for example, a touch panel. In this embodiment, an example in which the upper transparent electrode acts as the common electrode CE and the lower transparent electrode acts as the pixel electrode PE like in the active matrix substrate1004(FIG. 13andFIG. 14) will be described. Alternatively, the upper transparent electrode may act as the pixel electrode PE and the lower transparent electrode may act as the common electrode CE.

FIG. 17is a schematic plan view showing an active matrix substrate1006according to this embodiment as an example.FIG. 18(a)andFIG. 18(b)are each a schematic cross-sectional view of the active matrix substrate1006, and respectively show cross-sectional structures taken along lines A-A and B-B inFIG. 17. InFIG. 17andFIG. 18, elements substantially the same as those inFIG. 8throughFIG. 16bear the identical reference signs thereto. In the following, differences from the active matrix substrate1004(FIG. 13andFIG. 14) will be described, and the same descriptions as those made above will be omitted appropriately.

The active matrix substrate1006further includes another line layer22between the first transparent electrode layer15and the second transparent electrode layer19. In this example, the line layer22is in contact with a top surface of the first transparent electrode layer15. The line layer22is, for example, a metal layer such as a Cu layer or the like.

In the display region800, the pixel electrode PE and a line24electrically isolated from the pixel electrode PE are formed on the interlayer insulating layer13. The line24is located to overlap the source line SL as seen in the direction normal to the substrate. The line24is a stack line including a lower layer24aformed of the same transparent conductive film as that of the pixel electrode PE (namely, formed in the line layer22) and an upper layer24bformed in the line layer22. The pixel electrode PE and the line24are covered with the second inorganic insulating layer17, and the common electrode CE is located on the second inorganic insulating layer17.

The back-gate electrode BG of the first TFT101has substantially the same stack structure as that of the line24. Namely, the back-gate electrode BG is a stack electrode including a lower layer BGa formed of the same transparent conductive film as that of the pixel electrode PE and an upper layer BGb formed in the line layer22. The rest of the structure is substantially the same as that of the active matrix substrate1004.

According to this embodiment, the line layer22is used to form the back-gate electrode BG including a metal film. Therefore, the invasion of moisture into the oxide semiconductor layer5A is further alleviated, and the electrical resistance of the back-gate electrode BG is decreased.

<Method for Producing the Active Matrix Substrate1006>

With reference toFIG. 17andFIG. 18, a method for producing the active matrix substrate1006will be described. In the following, only differences from the method for producing the active matrix substrate1004(FIG. 13andFIG. 14) will be described, and the same descriptions as those made above will be omitted appropriately.

First, the first TFT101, the second TFT102, the first inorganic insulating layer11and the organic insulating layer12are formed in this order on the substrate by substantially the same method as for the active matrix substrate1004. In the organic insulating layer12, the openings12P,12Q and12R are formed. Then, the first inorganic insulating layer11is etched, using the resist layer (not shown) and the organic insulating layer12as an etching mask. As a result, the pixel contact hole and the back-gate contact hole are formed, and in the COM line region920, the opening11ris formed in the opening12R of the organic insulating layer12.

Next, the first transparent conductive film and a conductive film for the line layer are formed in this order on the organic insulating layer12and in the openings. The conductive film for the line layer is, for example, a metal film. As a material of the conductive film for the line layer, a material substantially the same as that of the conductive film for the source or the conductive film for the gate described above is usable. In this example, a Cu film (thickness: e.g., 50 nm or greater and 300 nm or less) is used.

Next, the first transparent conductive film and the conductive film for the line layer are patterned. As a result, the line24and the back-gate electrode BG each having a stack structure are formed, and in the region where the pixel electrode is to be formed, a stack body including the first transparent conductive film and the conductive film for the line layer is formed. The line24is located to overlap the source line SL as seen in the direction normal to the substrate. The back-gate electrode BG is located to contact the source electrode7A in the back-gate contact hole.

Next, from the stack body on the region where the pixel electrode is to be formed, only an upper layer formed of the conductive film for the line layer (in this example, the Cu layer) is removed by etching, using the resist layer (not shown). In this manner, the pixel electrode PE formed of the first transparent conductive film is obtained.

Next, the second inorganic insulating layer17covering the first TFT101, the second TFT102, the pixel electrode PE and the line24is formed. Then, the second transparent electrode layer19including the common electrode CE and the shield layer30is formed. In this manner, the active matrix substrate1006is produced.

Now, modifications of the active matrix substrate according to this embodiment will be described with reference to the drawings.

FIG. 19is a schematic plan view showing another active matrix substrate1007according to this embodiment as an example.FIG. 20(a)andFIG. 20(b)are each a schematic cross-sectional view of the active matrix substrate1007, and respectively show cross-sectional structures taken along lines A-A and B-B inFIG. 19.

In the active matrix substrate1007, the line layer22and a third inorganic insulating layer26located on the line layer22are provided between the second inorganic insulating layer17and the second transparent electrode layer19. The line layer22is, for example, a metal layer such as a Cu layer or the like.

In the display region800, the line24formed in the line layer22is provided on the second inorganic insulating layer17. The line24is located to overlap the source line as seen in the direction normal to the substrate. The third inorganic insulating layer26covers the line24. Although not shown, a connection portion electrically connecting the line24and the common electrode CE on the third inorganic insulating layer26to each other is provided in, for example, each of the pixels.

In the COM line region920, the common electrode CE is in contact with the COM line7C in the COM contact hole formed in the third inorganic insulating layer26, the second inorganic insulating layer17and the interlayer insulating layer13. As seen in the direction normal to the substrate, the COM contact hole includes the opening12R of the organic insulating layer12, the opening11rof the first inorganic insulating layer11, and the opening17rand an opening26rof the second inorganic insulating layer17and the third inorganic insulating layer26that are located inside the openings12R and11r.

In the circuit region910, the third inorganic insulating layer26extends to be located between the second inorganic insulating layer17and the shield layer30. The rest of the structure is substantially the same as that of, for example, the active matrix substrate1004(FIG. 13andFIG. 14).

In the active matrix substrate1007, the third inorganic insulating layer26, in addition to the second inorganic insulating layer17, is located to cover the oxide semiconductor layer5A. Therefore, the invasion of moisture into the oxide semiconductor layer5A is suppressed more effectively.

The active matrix substrate1007is produced by substantially the same method as for the active matrix substrate1004. It should be noted that the line24and the third inorganic insulating layer26are formed after the second inorganic insulating layer17is formed but before the second transparent electrode layer19is formed.

Specifically, after the second inorganic insulating layer17is formed to cover the first TFT101, the second TFT102and the pixel electrode PE, the conductive film for the line is formed on the second inorganic insulating layer17and is patterned, so that the line24is obtained. The material of the conductive film for the line is substantially the same as described above. In this example, a Cu film is used.

Next, the third inorganic insulating layer26is formed on the second inorganic insulating layer17so as to cover the line24. As the third inorganic insulating layer26, an inorganic insulating film substantially the same as that of the second inorganic insulating layer17is usable. In this example, an SiN film is used as the third inorganic insulating layer26. The third inorganic insulating layer26has a thickness of, for example, 70 nm or greater and 300 nm or less. In the active matrix substrate1007, a stack film including the second inorganic insulating layer17and the third inorganic insulating layer26acts as a dielectric layer of a storage capacitance formed by the common electrode CE and the pixel electrode PE. From this point of view, a total thickness of the second inorganic insulating layer17and the third inorganic insulating layer26may be set to, for example, 140 nm or greater and 500 nm or less.

Next, the second inorganic insulating layer17and the third inorganic insulating layer26are etched at the same time, using the resist layer (not shown) as an etching mask. As a result, in the opening12R, the opening17ris formed in the second inorganic insulating layer17and the opening26ris formed in the third inorganic insulating layer26, so that the COM contact hole is obtained. In this example, side surfaces of the openings17rand26rare aligned to each other.

Next, the second transparent conductive film is formed on the third inorganic insulating layer26and in the COM contact hole and is patterned, so that the common electrode CE and the shield layer30are obtained. The shield layer30and the common electrode CE are formed integrally with each other, and contact the COM line7C in the COM contact hole. In this manner, the active matrix substrate1007is produced.

FIG. 21is a schematic plan view showing a still another active matrix substrate1008according to this embodiment as an example.FIG. 22(a)andFIG. 22(b)are each a schematic cross-sectional view of the active matrix substrate1008, and respectively show cross-sectional structures taken along lines A-A and B-B inFIG. 21.

In the active matrix substrate1008, the line layer22and the third inorganic insulating layer26located on the line layer22are provided between the interlayer insulating layer13and the first transparent electrode layer15. The line layer22is, for example, a metal layer such as a Cu layer or the like.

In the display region800, the line24formed in the line layer22is provided on the interlayer insulating layer13. The line24is located to overlap the source line as seen in the direction normal to the substrate. The third inorganic insulating layer26covers the line24. On the third inorganic insulating layer26, the pixel electrode PE, the second inorganic insulating layer17and the common electrode CE are provided in this order.

The pixel electrode PE is in contact with the drain electrode8B in the pixel contact hole. The pixel contact hole includes the opening12Q formed in the organic insulating layer12and the openings26pand11pformed in the third inorganic insulating layer26and the first inorganic insulating layer11. As seen in the direction normal to the substrate, the openings26pand11pare aligned to each other, and are located inside the opening12Q.

In the COM line region920, the COM contact portion50includes a metal connection portion23formed of the same conductive film as that of the line24(namely, formed in the line layer22). The common electrode CE is electrically connected with the COM line7C via the metal connection portion23. Specifically, the metal connection portion23is located in the openings12R and11rof the organic insulating layer12and the first inorganic insulating layer11. The third inorganic insulating layer26and the second inorganic insulating layer17are provided on the metal connection portion23, and have the openings26rand17rexposing a part of the metal connection portion23. The common electrode CE is in contact with the metal connection portion23in the openings26rand17r. As seen in the direction normal to the substrate, the openings26rand17rare aligned to each other.

In the circuit region910, the back-gate electrode BG is formed of the same conductive film as that of the line24(namely, formed in the line layer22). The third inorganic insulating layer26and the second inorganic insulating layer17are formed between the back-gate electrode BG and the shield layer30. The rest of the structure is substantially the same as that of, for example, the active matrix substrate1004(FIG. 13andFIG. 14).

In the active matrix substrate1008, the third inorganic insulating layer26, in addition to the second inorganic insulating layer17, is located to cover the oxide semiconductor layer5A. In addition, a metal electrode is allowed to be formed as the back-gate electrode BG. Therefore, the invasion of moisture into the oxide semiconductor layer5A is suppressed more effectively, and the electrical resistance of the back-gate electrode BG is decreased.

The active matrix substrate1008is produced by substantially the same method as for the active matrix substrate1004. It should be noted that the line layer22and the third inorganic insulating layer26are formed after the interlayer insulating layer13is formed but before the first transparent electrode layer15is formed.

Specifically, after the interlayer insulating layer13is formed, the first inorganic insulating layer11is etched, using the resist layer (not shown) and the organic insulating layer12as an etching mask. As a result, in the COM line region920, the opening11ris formed in the first inorganic insulating layer11in the opening12R. In the circuit region910, the opening11tis formed in the first inorganic insulating layer11in the opening12P, so that the back-gate contact hole is obtained.

Next, the conductive film for the line is formed on the interlayer insulating layer13and in the openings, and is patterned. The material of the conductive film for the line is substantially the same as described above. In this example, a Cu film is used. As a result, the line layer22including the line24, the metal connection portion23and the back-gate electrode BG is obtained. The metal connection portion23is located to contact the COM line7C in the COM contact hole. The position of the back-gate electrode BG is substantially the same as in the active matrix substrate1004, and the position of the line24is substantially the same as in the active matrix substrate1007.

Next, the third inorganic insulating layer26is formed to cover the line layer22. The material and the thickness of the third inorganic insulating layer26are substantially the same as the material and the thickness described above. In this example, an SiN film is used. Next, the third inorganic insulating layer26and the first inorganic insulating layer11are etched at the same time, using the resist layer (not shown). As a result, in the opening12Q, the openings26pand11pare formed in the third inorganic insulating layer26and the first inorganic insulating layer11, so that the pixel contact hole exposing the drain electrode8B is obtained.

Next, the first transparent conductive film is formed on the second inorganic insulating layer17and in the pixel contact hole and is patterned, so that the first transparent electrode layer15including the pixel electrode PE is formed.

Next, the second inorganic insulating layer17is formed on the pixel electrode PE and the third inorganic insulating layer26. Then, the second inorganic insulating layer17and the third inorganic insulating layer26are etched at the same time, using the resist layer (not shown) as an etching mask. As a result, in the opening12R, the opening17ris formed in the inorganic insulating layer17and the opening26ris formed in the third inorganic insulating layer26, so that the COM contact hole exposing the metal connection portion23is obtained.

Next, the second transparent conductive film is formed on the third inorganic insulating layer26and in the COM contact hole and is patterned, so that the second transparent electrode layer19including the common electrode CE and the shield layer30is obtained. In this manner, the active matrix substrate1008is produced.

(Structure of the Peripheral Circuit)

In this embodiment, the peripheral circuit including the first TFT101is, for example, a gate driver. The gate driver includes a shift register including a plurality of stages.

FIG. 23shows an example of circuit configuration of the shift register.FIG. 24shows waveforms of input/output signals of and waveforms of voltages of netA and netB of each of the stages of the shift register. The structure and the operation of the shift register shown inFIG. 23andFIG. 24are disclosed in, for example, WO2013/137069 of the application filed by the present applicant and Japanese Laid-Open Patent Publication No. 2010-192019 of the application filed by the present applicant, and will not be described herein. The entirety of the disclosures of the above-mentioned patent documents is incorporated herein by reference.

Each stage of the shift register includes an input terminal receiving a gate start pulse GSP or an output signal Gout(n−2) from the immediately previous stage of the shift register, an output terminal outputting an output signal Gout(n), and terminals respectively receiving a plurality of clock signals CKA, CKB, CKC and CED having different phases from each other. One of the output terminals is connected with a corresponding gate bus line, and another one of the output terminals is connected with an input terminal of the shift register of the immediately subsequent stage.

As shown inFIG. 23, each stage of the shift register includes a first transistor (also referred to as an “output transistor”) M10outputting the output signal Gout(n), and a plurality of second transistors M1, M2, M8and M9each having a source or a drain electrically connected with a gate (main gate electrode) of the transistor M10. The first transistor M10is a so-called pull-up transistor, and a line connected with the main gate electrode of the first transistor M10is referred to as “netA”. One of the source and the drain of each of the second transistors M, M2, M8and M9is connected with netA, and the other of the source and the drain is connected with a Low potential (negative-side power supply VSS or Gout).

In this embodiment, in the above-described shift register, one or a plurality of transistors among the first transistor and the second transistors adopts a back-gate structure.

In the case where the back-gate structure is applied to the first transistor (output transistor)110, the back-gate electrode may be electrically connected with, for example, the source or the drain of the first transistor (in this example, the source (S-side line in the figure)). Alternatively, the back-gate electrode may be independently connected with another power supply. In the case where the back-gate structure is applied to the second transistors M1,112, M8or M9, the back-gate electrode may be set to have a negative-side power supply potential VSS or may be independently connected with another power supply.

The back-gate structure may be applied to a transistor other than the first and the second transistors. The back-gate electrode of such a transistor may be connected with another power supply.

<TFT Structure and Oxide Semiconductor>

The first TFT101and the second TFT102in each of the above-described embodiments may each be a channel-etch TFT. In a channel-etch TFT, no etch-stop layer is formed on the channel region, and a bottom surface of a channel-side end portion of each of the source and drain electrodes is located to contact a top surface of the oxide semiconductor layer (seeFIG. 9). Such a channel-etch TFT is formed by, for example, forming a conductive film for the source and drain electrodes on the oxide semiconductor layer and separating the source and the drain from each other. There may be a case where in such a source/drain separation step, a surface of the channel region is etched. The first TFT101and the second TFT102may each be an etch-stop TFT (seeFIG. 12). In an etch-stop TFT, a protective layer (etch-stop layer) is formed on the channel region. A bottom surface of a channel-side end portion of each of the source and drain electrodes is located on, for example, the etch-stop layer. Such an etch-stop TFT is formed by, for example, forming an etch-stop layer covering a portion of the oxide semiconductor layer that is to be a channel region, then forming a conductive film for the source and drain electrodes on the oxide semiconductor layer and the etch-stop layer, and separating the source and the drain from each other.

In each of the above-described embodiments, the oxide semiconductor contained in the oxide semiconductor layers5A and5B may be an amorphous oxide semiconductor or a crystalline oxide semiconductor including a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, a crystalline oxide semiconductor having a c axis aligned generally perpendicular to a layer surface, and the like.

The oxide semiconductor layers5A and5B may each have a stack structure including two or more layers. In the case of having the stack structure, the oxide semiconductor layers5A and5B may each include a non-crystalline oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, the oxide semiconductor layers5A and5B may each include a plurality of crystalline oxide semiconductor layers having different crystalline structures. Still alternatively, the oxide semiconductor layers5A and5B may each include a plurality of non-crystalline oxide semiconductor layers. In the case where the oxide semiconductor layers5A and5B each have a two-layer structure including an upper layer and a lower layer, it is preferred that the energy gap of the oxide semiconductor contained in the upper layer is larger than the energy gap of the oxide semiconductor contained in the lower layer. It should be noted that the energy gap of the oxide semiconductor contained in the lower layer may be larger than the energy gap of the oxide semiconductor contained in the upper layer as long as the energy gap difference between these layers is relatively small.

The material, structure, and film formation method of the non-crystalline oxide semiconductor and the above-described types of crystalline oxide semiconductors, the structure of the oxide semiconductor layers having a stack structure, and the like are described in, for example, Japanese Laid-Open Patent Publication No. 2014-003799. The entirety of the disclosure of Japanese Laid-Open Patent Publication No. 2014-003799 is incorporated herein by reference.

The oxide semiconductor layers5A and5B may each contain, for example, at least one metal element among In, Ga and Zn. In this embodiment, the oxide semiconductor layers5A and5B each contain, for example, an In—Ga—Zn—O-based semiconductor (e.g., indium gallium zinc oxide). The In—Ga—Zn—O-based semiconductor is a three-component oxide of In (indium), Ga (gallium) and Zn (zinc). There is no specific limitation on the ratio (composition ratio) among In, Ga and Zn. The ratio may be, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, or the like. The oxide semiconductor layers5A and5B may each be formed of an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor.

The In—Ga—Zn—O-based semiconductor may be amorphous or crystalline. A preferred crystalline In—Ga—Zn—O-based semiconductor is a crystalline In—Ga—Zn—O-based semiconductor having a c axis aligned generally perpendicular to a layer surface.

The crystalline structure of the crystalline In—Ga—Zn—O-based semiconductor is disclosed in, for example, Japanese Laid-Open Patent Publication No. 2014-007399 mentioned above, Japanese Laid-Open Patent Publication No. 2012-134475, Japanese Laid-Open Patent Publication No. 2014-209727 and the like. The entirety of the disclosures of Japanese Laid-Open Patent Publication No. 2012-134475 and Japanese Laid-Open Patent Publication No. 2014-209727 is incorporated herein by reference. A TFT including an In—Ga—Zn—O-based semiconductor layer has a high mobility (20 times the mobility of a-SiTFT) and a low leak current (less than 1/100 of the leak current of a-SiTFT). Therefore, such a TFT is preferably usable as a driving TFT (e.g., TFT included in a driving circuit provided in the vicinity of a display region including a plurality of pixels, on the same substrate as the display region) or a pixel TFT (TFT provided in a pixel).

The oxide semiconductor layers5A and5B may each contain another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor. The oxide semiconductor layers5A and5B may each contain, for example, an In—Sn—Zn—O-based semiconductor (e.g., In2O3—SnO2—ZnO; InSnZnO). The In—Sn—Zn—O-based semiconductor is a three-component oxide of In (indium), Sn (tin) and Zn (zinc). Alternatively, the oxide semiconductor layers5A and5B may each contain an In—Al—Zn—O-based semiconductor, an In—Al—Sn—Zn—O-based semiconductor, a Zn—O-based semiconductor, an In—Zn—O-based semiconductor, a Zn—Ti—O-based semiconductor, a Cd—Ge—O-based semiconductor, a Cd—Pb—O-based semiconductor, CdO (cadmium oxide), an Mg—Zn—O-based semiconductor, an In—Ga—Sn—O-based semiconductor, an In—Ga—O-based semiconductor, a Zr—In—Zn—O-based semiconductor, a Hf—In—Zn—O-based semiconductor, an Al—Ga—Zn—O-based semiconductor, a Ga—Zn—O-based semiconductor, or the like.

INDUSTRIAL APPLICABILITY

The embodiments of the present invention are applicable to an oxide semiconductor TFT and any of various types of active matrix substrates including an oxide semiconductor TFT. The embodiments of the present invention are especially preferably applicable to an active matrix substrate including two transparent electrode layers facing each other while having an insulating layer therebetween. An active matrix substrate according to each of these embodiments is preferably usable for a liquid crystal display apparatus, for example, a liquid crystal display apparatus providing display in a transverse electric field mode such as an FFS mode or the like. An active matrix substrate according to each of these embodiments is also applicable to a display device such as an organic electroluminescence (EL) display device, an inorganic electroluminescence display device or the like, an image capturing device such as an image sensor device or the like, an image input device, a fingerprint reading device, and any of various electronic devices such as a semiconductor memory or the like.

REFERENCE SIGNS LIST