Electrostatic discharge (ESD) protection circuits, integrated circuits, systems, and operating methods thereof

An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad. The ESD protection circuit includes a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage. An inverter includes an input end and an output end. The output end of the inverter is coupled with a gate of the clamp FET. A RC time constant circuit is disposed between the first supply voltage and the second supply voltage. A current mirror includes a first transistor. The current mirror is coupled between the input end of the inverter and the second supply voltage. A circuit is coupled with the input end of the inverter. The circuit is capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current.

TECHNICAL FIELD

The present disclosure relates generally to the field of semiconductor circuits, and more particularly, to electrostatic discharge (ESD) protection circuits, integrated circuits, systems, and methods for forming the integrated circuits.

BACKGROUND

ESD protection mechanisms generally work in two ways. First, by dissipating the ESD current transient safely using a low-impedance discharging channel that prevents thermal damage in the structures of the integrated circuit. Secondly, by clamping any ESD induced voltage to a safe level to avoid dielectric degradation or rupture. Ideally the complete ESD protection solution should be realized on the integrated circuit (IC) creating an effective discharging channel from any pin to every other pin on the integrated circuit.

Devices that are used as ESD protection elements include diodes, bipolar transistors, metal-oxide-semiconductor field effect transistors (MOSFETs), and silicon-controlled rectifiers (SCRs). SCRs function as switches that can be configured to turn on and shunt voltage from the input/output (I/O) pads of an integrated circuit to ground.

In ESD protection some integrated circuit elements may be vulnerable by discharges occurring within automated equipment, while others may be more prone to damage from handling by personnel. This can occur from direct transfer of electrostatic charge from the human body or from a charged material to the electrostatic discharge sensitive (ESDS) element. When one walks across a floor, an electrostatic charge accumulates on the body. Simple contact of a finger to the leads of an ESDS device or assembly allows the body to discharge, possibly causing device damage. The model used to simulate this event is the Human Body Model (HBM).

The HBM testing model represents the discharge from the fingertip of a standing individual delivered to the device. It is modeled by a 100 pF capacitor discharged through a switching component and a 1.5 kOhm series resistor into the component. Typically, integrated circuit designers would like to see protection from the HBM testing to be greater than 2,000 volts.

An electrostatic discharge can also occur from a charged conductive object, such as a metallic tool or fixture. To test for this, designers use the Machine Model (MM). The machine model consists of a 200 pF capacitor discharged directly into a circuit without a series resistor. Typically, integrated circuit designers would like to see protection from the machine model to be greater than 200 volts.

DETAILED DESCRIPTION

A conventional ESD protection circuit has a clamp field effect transistor (FET). The conventional ESD protection circuit also has a resistor coupled with a capacitor. While an ESD pulse occurs at an I/O pad of a circuit, the resistor and the capacitor can provide a RC time constant, e.g., about 2 μs, for keeping or maintaining the clamp FET on so as to discharge the ESD pulse to a ground. It is found that the resistance of the resistor and the capacitance of the capacitor should be large enough to provide the desired RC time constant. The resistor and the capacitor would consume a large area of the circuit.

To reduce the area of the capacitor, a current mirror has been proposed to be disposed within the conventional ESD protection circuit. The current mirror with a current amplification can be used to amplify the capacitance of the capacitor. Since the capacitance of the capacitor can be amplified, the area of the capacitor can be reduced to achieve the same capacitance. Accordingly, the resistor and the capacitor that are coupled with the current mirror can have an area smaller than that of the resistor and capacitor without the current mirror.

However, it is found that while the integrated circuit is subjected to a latch-up test using a negative current, the clamp FET is turned on. The turned-on clamp FET allows a large current flowing between the source and the drain of the clamp FET. The current flow can result in an electrical overstress (EOS) failure to the clamp FET.

Based on the foregoing, integrated circuits that are capable of substantially eliminating the EOS failure while the integrated circuit is subjected to the latch-up test using a negative current, systems, and operating methods thereof are desired.

FIG. 1is a schematic drawing illustrating an exemplary integrated circuit including an electrostatic discharge (ESD) protection circuit. An integrated circuit100can include an input/output (I/O) pad101. The I/O pad101can be coupled with an ESD protection circuit110. In various embodiments, the I/O pad101can be coupled with the ESD protection circuit110through at least one diode, e.g., diodes103aand103b. The I/O pad101can be coupled with an internal circuit105. In various embodiments, a resistor104can be disposed between the internal circuit105and the I/O pad101for protecting the internal circuit105from being damaged by an ESD pulse. The internal circuit105can include, for example, static random access memory (SRAM) array, an embedded SRAM array, dynamic random access memory (DRAM) array, an embedded DRAM array, a field-programmable gate array, a non-volatile memory, e.g., FLASH, EPROM, E2PROME, a logic circuit, an analog circuit, any other kind of integrated circuits, and/or any combinations thereof.

Referring toFIG. 1, the ESD protection circuit110can include a clamp field effect transistor (FET)115. The clamp FET115can be disposed between a first supply voltage, e.g., a supply voltage VDD, and a second supply voltage, e.g., a supply voltage VSS. The supply voltage VDD can be a voltage provided for operations of the internal circuit105. In various embodiments, the VDD can be 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V, 9 V, 12 V, or any other voltage that is desired for the operations of the internal circuit105. The supply voltage VSS can be a ground provided by a ground terminal coupled with the internal circuit105. In various embodiments, the ground that is capable of providing the supply voltage VSS can be referred to as a core ground.

The ESD protection circuit110can include an inverter120. The inverter120can have an input end120aand an output end120b. The output end120bof the inverter120can be coupled with a gate of the clamp FET115. In various embodiments, the inverter120can include a PMOS transistor and an NMOS transistor. The source end of the PMOS transistor can be coupled with the supply voltage VDD. The drain end of the PMOS transistor can be coupled with the output end120bof the inverter120. The source end of the NMOS transistor can be coupled with the supply voltage VSS. The drain end of the NMOS transistor can be coupled with the output end120bof the inverter120.

The ESD protection circuit110can include a resistance-capacitance (RC) time constant circuit121. The RC time constant circuit121can be coupled between the supply voltages VDD and VSS. The RC time constant circuit121can provide a RC time constant to keep or maintain the voltage state on the input end120aof the inverter120low for a desired time period. The low voltage state on the input end120aof the inverter120can output a high voltage state on the gate of the clamp FET115, turning on the clamp FET115. If an ESD pulse occurs on the I/O pad101, the turned-on clamp FET115can discharge the ESD pulse to the supply voltage VSS or the core ground.

In various embodiments, the RC time constant circuit121can include a resistor125coupled with a capacitor130. The resistor125can be disposed between the supply voltage VDD and the input end120aof the inverter120. The capacitor130can be disposed between the supply voltage VSS and the input end120aof the inverter120.

Referring toFIG. 1, the ESD protection circuit110can include a current mirror140. The current mirror140can be coupled between the input end120aof the inverter120and the supply voltage VSS. In various embodiments, the current mirror140can include a transistor141and a transistor143. The transistor141can be coupled between the input end120aof the inverter120and the supply voltage VSS. The transistor143can be coupled between the capacitor130and the supply voltage VSS.

The ESD protection circuit110can include a circuit145. The circuit145can be coupled with the input end120aof the inverter120. The circuit145can output a voltage state on the input end120aof the inverter120that is capable of substantially turning on the clamp FET115while the I/O pad101is subjected to a latch-up test using a negative current.

During a normal operation without an ESD pulse, the supply voltage VDD can be coupled to the RC time constant circuit121. Since no substantial current flows to or from the capacitor130, the voltage state on the input end120aof the inverter120is high. The inverter120can in turn output a low voltage state on the gate of the clamp FET115, turning off the clamp FET115. Since the clamp FET115is turned off, the supply voltage VDD can be desirably supplied to the internal circuit105for operations.

If an ESD pulse occurs on the I/O pad101, the ESD pulse can be coupled to the RC time constant circuit121, triggering a substantial current flowing to or from the capacitor130. The current flowing to or from the capacitor130can pull down the voltage state on the input end120aof the inverter120, which in turn outputs a high voltage state on the gate of the clamp FET115. The turned-on clamp FET115can desirably discharge the ESD pulse to the supply voltage VSS. Since the ESD pulse is discharged, the internal circuit105can be desirably protected from being damaged by the ESD pulse.

As noted, the current flows to or from the capacitor130while the ESD pulse occurs on the I/O pad101. The current mirror140with a current amplification can amplify the capacitance of the capacitor130. The amplified capacitance of the capacitor130and the resistance of the resistor125can provide a desired RC time constant to keep or maintain the voltage state of the input end120aof the inverter120low for a desired period, e.g., 2 microsecond (μs), such that the clamp FET115can be turned on to desirably discharge the ESD pulse.

As noted, the current mirror140can include the transistor141. The transistor141can include a source, a bulk, and a drain. The bulk can be a doped region, e.g., a well, or a semiconductor substrate. It is found that while the I/O pad101is subjected to a latch-up test using a negative current, a parasitic transistor, e.g., an npn transistor, constituted from the drain-bulk-source of the transistor141can be activated. The voltage state on the bulk of the transistor141can be pulled up to high. The activated parasitic npn transistor of the transistor141can couple the input end120aof the inverter120to the supply voltage VSS, pulling down the voltage state on the input end120a. The low voltage state on the input end120aof the inverter120can output a high voltage state that can turn on the clamp FET115. During the latch-up test, the turned-on clamp FET115can allow substantial currents flowing between the source end and drain end of the clamp FET115. The current flow between the source end and drain end of the clamp FET115may result in the clamp FET115failing.

To substantially eliminate the issue described above, the circuit145can provide or output a high voltage state on the input end120aof the inverter120while the I/O pad101is subjected to a latch-up test using a negative current. The high voltage state on the input end120aof the inverter120can output a low voltage state on the gate of the clamp FET115for substantially turning off the clamp FET115, such that no substantial current would flow between the source end and drain end of the clamp FET115. While I/O pad101is subjected to a latch-up test using a negative current, the failure of the clamp FET115described above can be desirably eliminated.

In various embodiments, the circuit145can include a transistor147, e.g., an NMOS transistor, and a transistor149, e.g., a PMOS transistor. A source end of the transistor147can be coupled with the supply voltage VSS. A gate of the transistor147can be coupled with the bulk of the transistor141of the current mirror140. A gate of the transistor149can be coupled with the transistor147. A drain end of the transistor149can be coupled with the input end120aof the inverter120. A source end of the transistor149can be coupled with the supply voltage VDD.

As noted, the parasitic npn transistor of the transistor141can be activated while the I/O pad101is subjected to the latch-up test using the negative current. It is found that a parasitic npn transistor of the transistor147can also be activated, coupling the supply voltage VSS with the gate of the transistor149and turning on the transistor149. The turned-on transistor149can couple the voltage supply VDD with the input end120aof the inverter120, pulling up the voltage state on the input end120aof the inverter120. The high voltage state on the input end120aof the inverter120can output a low voltage state on the gate of the clamp FET115, turning off the clamp FET. From the foregoing, while the I/O pad101is subjected to the latch-up test using the negative current, no substantial current flows between the source end and drain end of the clamp FET115.

In various embodiments, the impedance of the transistor149can be lower than the impedance of the transistor141. For example, the transistors141and149may have the same channel length. The transistor149may have a channel width larger than that of the transistor141.

It is noted that the structure of the circuit145described above in conjunction withFIG. 1is merely exemplary. In various embodiments, the circuit145can include a single transistor or a diode. For example, the circuit145can include a single PMOS transistor. The gate of the PMOS transistor can be coupled with the drain end of the transistor141. The drain of the PMOS transistor can be coupled with the input end120a. The source of the PMOS transistor can be coupled with the supply voltage VDD. In other embodiments, the circuit145can include other resistors, diodes, transistors, capacitors, and/or any other electronic components in addition to the transistors147and149. One of skill in the art can modify the structure of the circuit145to achieve a desired circuit.

FIG. 2is a schematic drawing illustrating another exemplary integrated circuit including an ESD protection circuit. Items of an integrated circuit200inFIG. 2that are the same items of the integrated circuit100inFIG. 1are indicated by the same reference numerals, increased by 100. InFIG. 2, the source end of the transistor247can be coupled with a supply voltage. The supply voltage can be a ground provided by a ground terminal. In various embodiments, the ground can be referred to as an I/O ground.

As noted, the parasitic npn transistor of the transistor241can be activated while the I/O pad201is subjected to the latch-up test using the negative current. The voltage state on the bulk of the transistor241can be pulled up to high. Since high voltage state on the bulk of the transistor241can be coupled to the gate of the transistor247, the transistor247can be turned on. The turned-on transistor247can couple the gate of the transistor249with the I/O ground, pulling down the voltage state on the gate of the transistor249and turning on the transistor249. The turned-on transistor249can couple the voltage supply VDD with the input end220aof the inverter220, pulling up the voltage state on the input end220a. The high voltage state on the input end220aof the inverter220can output a low voltage state on the gate of the clamp FET215, turning off the clamp FET215. From the foregoing, while the I/O pad201is subjected to the latch-up test using the negative current, no substantial current flows between the source end and drain end of the clamp FET215.

In various embodiments, the integrated circuit200can include a back-to-back diode250. The back-to-back diode250can be disposed between the I/O ground and the core ground. The back-to-back diode250can desirably isolate the I/O ground from the core ground. In various embodiments, the back-to-back diode250can be an n/p diode coupled with a p/n diode in series.

FIG. 3is a schematic drawing showing a system including an exemplary integrated circuit. InFIG. 3, a system300can include a processor310coupled with an integrated circuit301. The integrated circuit301can be similar to the integrated circuits100and200described above in conjunction withFIGS. 1 and 2. In various embodiments, the processor310can be a processing unit, central processing unit, digital signal processor, or other processor that is suitable for accessing data of a memory circuit.

In various embodiments, the processor310and the integrated circuit301can be formed within a system that can be physically and electrically coupled with a printed wiring board or printed circuit board (PCB) to form an electronic assembly. The electronic assembly can be part of an electronic system such as computers, wireless communication devices, computer-related peripherals, entertainment devices, or the like.

In various embodiments, the system300including the integrated circuit301can provides an entire system in one IC, so-called system on a chip (SOC) or system on integrated circuit (SOIC) devices. These SOC devices may provide, for example, all of the circuitry needed to implement a cell phone, personal data assistant (PDA), digital VCR, digital camcorder, digital camera, MP3 player, or the like in a single integrated circuit.