Semiconductor device and method for manufacturing the same

Semiconductor device 101 includes semiconductor substrate 10, drift layer 20, first electrode 50, and second electrode 60. Semiconductor substrate 10 is of a first conductivity type and is formed of a silicon carbide semiconductor, a gallium nitride semiconductor, or the like. For example, semiconductor substrate 10 is an n-type silicon carbide semiconductor substrate. Drift layer 20 is an epitaxial semiconductor layer of the first conductivity type which is formed on upper surface 10a of semiconductor substrate 10 by epitaxial growth. Drift layer 20 is formed of for example, an n-type silicon carbide semiconductor. Drift layer 20 has a thickness of t. For example, the thickness t is between about 5 μm and about 100 μm (inclusive).

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

2. Description of the Related Art

In recent years, the development of semiconductor devices for power electronics applications has been promoted. Power semiconductor devices have large-area semiconductor chips, and these large area semiconductor chips are apt to contain defects. This decreases the yield of the semiconductor devices. To address this problem, various traditional technologies have been presented to prevent the defects from causing a reduction in yield, as is disclosed in PTL 1.

CITATION LIST

Patent Literature

SUMMARY

The present disclosure provides a new technology that prevents defects from causing a reduction in yield.

A semiconductor device of the present disclosure includes a semiconductor substrate, a drift layer, a first electrode, and a second electrode. The drift layer is on a surface of the semiconductor substrate. The first electrode is in a region, on a surface of the drift layer, except a depletion control region and has an ohmic contact or a Schottky contact with the drift layer. The second electrode has an ohmic contact with a rear surface of the semiconductor substrate. The drift layer has a thickness of t. The depletion control region includes a circular or sector-shaped region having a radius of not less than t.

The technique provided by the present disclosure prevents a defect from causing a reduction in yield.

DETAILED DESCRIPTION

(Knowledge that Underlies the Present Disclosure)

Prior to describing exemplary embodiments of the present disclosure, knowledge that underlies the present disclosure will now be described. It is desirable that semiconductor chips extracted from semiconductor wafers by epitaxial growth should each have an area of several centimeters square to implement a high current of several hundred amperes in power devices. However, securing the yield for large-area power devices is not easy. Following, semiconductor wafer by epitaxial growth is denoted ‘epi wafer’.

For example, in the case of a silicon carbide semiconductor gathering attention for use in power devices, a micropipe which is one type of screw dislocation is created in a crystal growth direction and penetrates through the crystal. The micropipe is a crystalline defect, and a leakage current can arise via the micropipe. When a micropipe is in a silicon carbide substrate, the micropipe can be transferred (propagated) to an epitaxial semiconductor layer stacked on the silicon carbide substrate. Further, a leakage current can arise via a defect (epitaxial defect) newly generated in the epitaxial semiconductor layer. Examples of the epitaxial defect include a downfall defect which is a deposited matter on am epitaxial equipment taken in into the epitaxial semiconductor layer, and include an epitaxial defect such as an stacking defect (for example, a triangular defect and a carrot defect) caused by epitaxial growth conditions.

For example, density of micropipes in a silicon carbide semiconductor substrate and density of epitaxial defects in an epitaxial semiconductor layer add up to about several pieces/cm2. Many of the power devices using a silicon carbide semiconductor employ a vertical structure. Therefore, if a power device contains a micropipe, the micropipe can be a path through which a leakage current flows when a reverse bias is applied to the device. Therefore, even if such a power device has only one micropipe or epitaxial defect in the device, an amount of a leakage current when a reverse bias is applied can be greater than the product specification, thereby making the device defective.

For example, if an SiC substrate having defect density of one piece/cm2is used to manufacture a device in one centimeter square, the yield on the device is estimated at around 50% in the Seeds model. According to the Seeds model, estimated yield Y is given by: Y=1/(1+AD), where A is the chip area and D is the defect density.

PTL 1 discloses that in the case of a Schottky barrier diode of a silicon carbide semiconductor, a surface part of a micropipe is covered by an insulation layer to reduce an influence of the micropipe. However, according to PTL 1, an electrode is formed also on the insulation layer. According to a detailed study of the present inventor, a high voltage is applied by this electrode also to a region including the micropipe, and the micropipe functions as a path of a leakage, thereby causing a breakdown.

In view of this issue, the present inventor has conceived a novel semiconductor device and a method for manufacturing the semiconductor device. The following is a general description of a semiconductor device and a method for manufacturing the semiconductor device of the present disclosure.

A semiconductor device includes a semiconductor substrate, a drift layer, a first electrode, and a second electrode. The drift layer is on a surface of the semiconductor substrate. The first electrode is in a region, on a surface of the drift layer, except a depletion control region and has an ohmic contact or a Schottky contact with the drift layer. The second electrode has an ohmic contact with a rear surface of the semiconductor substrate. The drift layer has a thickness of t, and the depletion control region includes a circular or sector-shaped region having a radius not less than t.

Regarding the semiconductor device of Item 1, at least one of the drift layer in the depletion control region and the semiconductor substrate has a crystalline defect or a process-related defect in a plan view parallel to the surface of the drift layer. Further, in the plan view, a distance from the crystalline defect or the process-related defect to an outer edge of the depletion control region is not less than t.

Regarding the semiconductor device of Item 1, the crystalline defect is a micropipe or an epitaxial defect.

Regarding the semiconductor device of Items 1 to 3, the first electrode makes the Schottky contact with the drift layer, and the semiconductor device is a Schottky barrier diode.

Regarding the semiconductor device of Items 1 to 3, the drift layer has a plurality of well regions in a surface part including a first principal surface. The well regions each include a source region. The semiconductor device further, includes a gate insulation layer, a gate electrode, and an insulation layer.

The gate insulation layer is on the first principal layer of the drift layer, and exposes at least part of each of the source regions in the plurality of well regions. Outside the depletion control region, the gate electrode is formed on the gate insulation layer; and inside the depletion control region, the gate electrode is not formed on the gate insulation layer. Outside the depletion control region, the insulation layer covers the gate electrode; and inside the depletion control region, the insulation layer covers at least part of the gate insulation layer. Further, outside the depletion control region, the first electrode covers the insulation layer.

A method for manufacturing a semiconductor device includes step (a), step (b), and step (c). In step (a), a semiconductor substrate having a tuft layer is prepared. In step (b), at least one of a crystalline defect and a process-related defect in the drift layer and the semiconductor substrate is inspected. Then, coordinates of the crystalline defect or the process-related defect are obtained. Depending on the coordinates, a depletion control region is determined. In step (c), in a region, on a surface of the drift layer, except the depletion control region, a first electrode is formed to have an ohmic contact or a Schottky contact with the drift layer. Here, the drift layer has a thickness of t, and the depletion control region includes a circular or sector-shaped region having a radius not less than t.

Regarding the method for manufacturing the semiconductor device of Item 6, in a plan view, a distance from a coordinate position of the crystalline defect or the process-related defect to an outer edge of the depletion control region is not less than t.

Regarding the method for manufacturing the semiconductor device of Item 7, the crystalline defect is a micropipe or an epitaxial defect.

Regarding the methods for manufacturing the semiconductor device of Items 7 to 9, the first electrode makes the Schottky contact with the drift layer, and the semiconductor device is a Schottky harrier diode.

In step (a), the drift layer has a plurality of well regions in a surface part including a first principal surface, the well regions each including a source region. Further, between step (b) and step (c), there are a step of forming a gate insulation layer, a step of forming a gate electrode, and a step of forming an insulation layer. In the step of forming the gate insulation layer, the gate insulation layer is formed on the surface of the drift layer so as to expose at least part of each of the source regions in the plurality of well regions. In the step of forming the gate electrode, the gate electrode is formed such that, outside, the depletion control region, the gate electrode is on the gate insulation layer and such that, inside the depletion control region, the gate electrode is not on the gate insulation layer. In the step of forming the insulation layer, outside the depletion control region, the insulation layer covers the gate electrode; and inside the depletion control region, the insulation layer covers at least part of the gate insulation layer. In step (c), the first electrode is formed such that, inside the depletion control region, the first electrode does not cover the insulation layer; and outside the depletion control region, the first electrode covers the insulation layer.

Hereinafter, more specific exemplary embodiments of the present disclosure will be described.

First Exemplary Embodiment

FIG. 1Ais a plan view of semiconductor device101of the present exemplary embodiment, andFIG. 1Bis a cross-sectional view of semiconductor device101. In the present exemplary embodiment, semiconductor device101is a Schottky barrier diode. Semiconductor device101includes semiconductor substrate10, drift layer20, first electrode50, and second electrode GO.

Semiconductor substrate10is of a first conductivity type and is formed of a silicon carbide semiconductor, gallium nitride semiconductor, or the like, For example, semiconductor substrate10is an n-type silicon carbide semiconductor substrate.

Drift layer20is an epitaxial semiconductor layer of the first conductivity type which is formed on upper surface10aof semiconductor substrate10by epitaxial growth. Drift layer20is formed of, for example, an n-type silicon carbide semiconductor. Drift layer20has a thickness of t. For example, the thickness t is between about 5 μm and about 100 μm (inclusive). InFIG. 1B, drift layer20is shown to be thicker than semiconductor substrate10for easy understanding: however, in an actual semiconductor device, the thickness of drift layer20may be thicker than or thinner than the thickness of semiconductor substrate10. Further, semiconductor device101may have a buffer layer between drift layer20and semiconductor substrate10.

FIG. 1Cis a plan view of drift layer20. On upper surface20aof drift layer20, there are provided annular guard ring21and a plurality of field. limiting rings (FLRs)22surrounding guard ring21. Guard ring21and FLRs22are provided inside drift layer20from upper surface20ato have predetermined depths. That is, guard ring21and FLRs22are provided in a surface part of the drift layer. Guard ring21and as22are of a second conductivity type.

Semiconductor device101has defect30in at least one of semiconductor substrate10and drift layer20. Defect30is a crystalline defect or a process-related defect, and there is at least one defect30.FIG. 113shows an example in which semiconductor device101has in drift layer20a micropipe, which is one type of screw dislocation, as defect30. Examples of the crystalline defect include a downfall defect, a triangular defect, a carrot defect, and a stripe defect which are on the surfaces of semiconductor substrate10and drift layer20. Further, examples of a defect inside semiconductor substrate10and drift layer20include a stacking fault, a basal plane dislocation, and a screw dislocation. The micropipe is one type of the screw dislocation. Examples of a process-related defect include: a conductive or non-conductive foreign substance which is on upper surface10aof semiconductor substrate10and upper surface20aof drift layer20; an unintended implantation region formed inside drift layer20due to an abnormality of a mask used, when above-described guard ring21and FLRs22are formed; and an abnormality due to a thermal treatment of upper surface20aof drift layer20.

Defect30on upper surface10aof semiconductor substrate10and upper surface20aof drift layer20can be observed, for example, with an optical microscope. Further, the defect inside semiconductor substrate10and drift layer20can be observed by a photoluminescence method or the like. There is commercially available a defect inspection apparatus in which optical observation or a photoluminescence method is used, and by using the defect inspection apparatus, it is possible to identify and, record, position coordinates of the defect on the semiconductor wafer. Further, in some cases, it is possible to detect as the abnormality of electric characteristics the unintended implantation region, the abnormality due to a thermal treatment on upper, surface20aof drift layer20, and other defects. In this case, it is possible to detect these abnormalities, for example, by using a defect inspection apparatus which measures electric characteristics.

First electrode50is in a region, on upper surface20aof drift layer20, except at least depletion control region20c.An outer edge of first electrode50is on guard ring21.FIG. 1DtoFIG. 1Fare partially enlarged plan views of first electrode50. In the plan view parallel to upper surface20aof drift layer20of semiconductor device101, defect30is in depletion control region20crepresented by a solid line. Depletion control region20chas a shape containing a circle or a sector having a radius of not less than t. In other words, depletion control region20cincludes whole of a circular or sector-shaped region having a radius not less than t.FIG. 1Dshows an example of depletion control region20cincluding a circular region represented by a broken line, andFIG. 1Eshows an example of depletion control region20cincluding a sector-shaped region represented by a broke line. When defect30in an end part of a region surrounded by guard ring21on upper surface20aof drift layer20, depletion control region20cmay include a semicircular region, for example. Depletion control region20chas only to include a circular or sector-shaped region satisfying the above-described conditions, and depletion control region20cis not limited to a circle or a sector. For example, as, shown inFIG. 1F, depletion control region20cmay have a rectangular shape, and may have a shape such as a triangular shape, a hexagonal shape, and the like. Further, if there are two or more defects30, there may be independently provided depletion control regions20ceach corresponding to each of the defects, depending on the positions of defects30; or alternatively, of a plurality of depletion control regions20c,depletion control regions20cfor closely-lying two or more defects30may be provided as one body.

In a plan view, a distance from defect30in depletion control region20cto the outer edge of depletion control region20cis not less than t. First electrode50is not provided on depletion control region20cof upper surface20aof drift layer20. Therefore, first electrode50has an opening or a hole corresponding to depletion control region20c.A distance between an inner edge of first electrode50defining this opening or hole and defect30is not less than t.

First electrode50having the opening corresponding to depletion control region20ccan be formed by forming a resist pattern in a region including depletion control region20cor by forming in a resist layer the opening corresponding to depletion control region20c.The above-described resist pattern can be formed by using the position coordinates of the defect. determined by the above-described defect inspection apparatus, by dropping uncured resist material on the position, and curing the resist material; or alternatively, the resist pattern can be formed by applying a laser beam to the resist layer to remove part of the resist layer. A detailed description will be given below.

First electrode50has an ohmic contact or a Schottky contact with drift layer20. In the present exemplary embodiment, since semiconductor device101is a Schottky barrier diode, first electrode50makes the Schottky contact with drift layer20. First electrode50is formed of an electrode material which can make the ohmic contact or the Schottky contact with drift layer20. In the present exemplary embodiment, first electrode50is formed of metal such as nickel, titanium, or aluminum. First electrode50may be a single layer or stacked layers.

In the present exemplary embodiment, on upper surface20aof drift layer20, insulation layer40covers an outer side of guard ring21, and an inner edge of the insulation layer is on guard ring21. On upper surface20aof drift layer20, insulation layer40preferably covers depletion control region20c.

Second electrode60is on lower surface10bof semiconductor substrate10and has an ohmic contact with semiconductor substrate10. Second electrode60may be a single layer or stacked layers. AlthoughFIG. 1Band other drawings do not show, semiconductor device101may further include a film protective covering part of the whole structure.

In semiconductor device101, when a voltage is applied between first electrode50and second electrode60such that the Schottky contact between first electrode50and drift layer20is reversely biased, depletion layer20dis formed on an interface between first electrode50and drift layer20. As the applied voltage is increased, depletion layer20dextends and reaches an interface between semiconductor substrate10and drift layer20. That is, a thickness of depletion layer20dbecomes equal to the thickness t of drift layer20. At this time, depletion layer20dextends also in a direction parallel to upper surface20a,which is a direction perpendicular to a thickness direction of drift layer20. When the applied voltage is higher than the voltage with which depletion layer20dreaches the interface between semiconductor substrate10and drift layer20, depletion layer20dextends more largely in the parallel direction than in the thickness direction. However, a maximum apply voltage is usually specified by a device specification; thus, depletion layer20ddoes not extremely extend in the parallel direction. The radius of depletion control region20cis preferably not less than t and is more preferably not less than 2t.

With this arrangement, even if a reverse bias voltage is applied between first electrode50and second electrode60, the region, of drift layer20, having the defect30is not depleted: thus, a high reverse bias voltage is not applied to defect30, thereby preventing or reducing generation of a leakage current.

FIG. 2shows the semiconductor device disclosed in PTL 1 at a state where a reverse bias voltage is applied. Insulation layer40is provided on upper surface20aof drift layer20to cover defect30as shown inFIG. 2; however, first electrode50is on defect30. Therefore, the reverse bias voltage is applied also to a part of drift layer20, on which defect30lies, via insulation layer40, and the depletion layer extends also to the part on which defect30lies. Further, the depletion layer also extends toward defect30in the horizontal direction from an end part of insulation layer40on defect30. As, a result, in the semiconductor device shown inFIG. 2, defect30lies in depletion layer20d. Defect30in depletion layer20dto which a high electric field is applied functions as a path of a leakage current: thus, in the semiconductor device shown inFIG. 2, when a reverse bias voltage is applied between first electrode50and second electrode60, a leakage current can be easily generated via defect30.

As described above, a semiconductor device of the present exemplary. embodiment includes a first electrode which has an ohmic contact or a Schottky contact with a drift layer in a region, on a surface of the drift layer, except a depletion control region, and the depletion control region has a shape including a circle or a sector having a radius of not less than t. With this arrangement, it is possible to set a distance from the defect to an outer edge of the depletion control region to a distance not less than t, and it is thus possible to prevent or reduce extension of the depletion layer to the defect when a reverse bias is applied. Therefore, it is possible to prevent or reduce generation of a leakage current via the defect. That is, even if the semiconductor substrate and the drift layer have a defect, it is possible to manufacture a semiconductor device which has a small leakage current and can thus satisfy the specification of the product, whereby the product yield can be improved.

With reference toFIG. 3AtoFIG. 3JandFIG. 4, a method for manufacturing semiconductor device101will be described.FIG. 3AtoFIG. 3Jare process cross-sectional views illustrating the method for manufacturing semiconductor device101, andFIG. 4is a flowchart.

As shown inFIG. 3A, semiconductor substrate10on which drift layer20is formed is prepared (step S1). For example, drift layer20made of an u-type silicon carbide is epitaxial-grown on semiconductor substrate10made of an n-type silicon carbide semiconductor. As shown inFIG. 3A, drift layer20has defect30.

Next, the defect in semiconductor substrate10on which drift layer20is formed is detected by using, a defect inspection apparatus, and position coordinates of the detected defect is recorded (step S2). As described above, to detect a crystalline defect in drift layer20, it is possible to use a defect inspection apparatus using a photoluminescence method. Further, to detect defect30on, upper surface20aof drift layer20, it is possible to use a defect inspection apparatus using optical image recognition, for example. Also before drift layer20is formed, defects may be detected by using the defect inspection apparatus.

A mask pattern for guard ring21and FLRs22is formed on the surface of drift layer20, and p-type impurities are implanted. After that, drift layer20is subjected to a thermal treatment to activate the impurities to form patterns of guard ring21and FLRs22on drift layer20as shown inFIG. 3B(step S3). After the patterns of guard ring21and FLRs22are formed, an inspection for defect30may be performed again using the defect inspection it) apparatus to inspect presence or absence of an abnormally implanted region, an abnormality of the surface of drift layer20, and the like (step S4).

On the basis of the defect30and the position coordinates of the defect30recorded through the above-described steps, depletion control region20cis determined (step S5). For example, if the thickness of the drift layer20is t, depletion control region20cis determined to be an inside of a circle which is centered at the position coordinates of defect30and has a radius of t.

Insulation layer40is formed on upper surface20aof drift layer20(step S6). Specifically, as shown inFIG. 3C, insulation layer40′ is first formed on upper surface20aof drift layer20by using an insulation material such as silicon oxide or silicon nitride. After that, mask layer42is formed to have an opening pattern42cwhose outer edge is on guard ring21. Further, as shown inFIG. 3D, resist pattern43covering depletion control region20cis formed on insulation layer40′ in opening pattern42c.Resist pattern43can be formed, for example, by dropping resist at the recorded position coordinates of the defect. By adjusting viscosity and an amount of the resist, resist pattern43can be formed to have a circular shape whose center coincides in a plan, view with the position coordinates of defect30and has a radius of not less than t. As long as an outer edge of resist pattern43is not less than t distant from the position coordinates of defect30, the center of resist pattern43does not have to coincide with the position coordinates of defect30. In addition, the value of the radius may be greater than t, and opening pattern42cmay have a shape other than a circle. Here, taking overlapping of insulation layer40and first electrode50into consideration, mask layer42is formed to have a circular shape with a radius of 1.1 t, for example.

Mask layer42and resist pattern43are used to etch insulation layer40′ by a dry etching process or a wet etching process, so that insulation layer40is formed as shown inFIG. 3E.

Next, first electrode50will be formed (step S7). First, as shown inFIG. 3F, a film of an electrode material is formed on drift layer20to cover the above-described structure and is then patterned to form first electrode50′ which covers an exposed part of upper surface20aof drift layer20. Further, as shown inFIG. 3G, resist layer51is formed on first electrode50′, and opening51cis formed in resist layer51to coincide with depletion control region20cas shown inFIG. 3H. Opening Sic can be formed by removing part of resist layer51by, for example, laser machining. By removing first electrode50′ in opening51cof resist layer51, first electrode50is formed as shown inFIG. 3I.

After that, as shown inFIG. 3Jresist layer51is removed, and second electrode60is then formed on lower surface10bof semiconductor substrate10(step58). With these steps, semiconductor device101is completed.

Second Exemplary Embodiment

FIG. 5Ais a plan view of semiconductor device102of the present exemplary embodiment, andFIG. 5Bis an enlarged cross-sectional view in the vicinity of depletion control region20cof semiconductor device102. In the present exemplary embodiment, semiconductor device102is a power metal oxide semiconductor field effect transistor (MOSFET). Semiconductor device102includes semiconductor substrate10, drift layer20, first electrode50, and second electrode60. Semiconductor device102is different from semiconductor device101of the first exemplary embodiment in a function as a semiconductor device but is similar in the configuration for preventing or reducing the leakage current due to defect30in semiconductor substrate10and drift layer20. Therefore, the structure similar to the structure in the first exemplary embodiment is not described again in seine cases.

Semiconductor device102includes a plurality of unit cells102u.Since each unit cell102uhas one field effect transistor (FET), semiconductor device102including the plurality of unit cells102uincludes a plurality of parallel connected FETs.

Similarly to, the first exemplary embodiment, semiconductor substrate10is of a first conductivity type and is formed of a silicon carbide semiconductor, gallium nitride semiconductor, or the like. For example, semiconductor substrate10is an n-type silicon carbide semiconductor substrate.

Further, drift layer20is an epitaxial semiconductor layer of the first conductivity type which is formed on upper surface10aof semiconductor substrate10by epitaxial growth. Drift layer20is formed of, for example, an n-type silicon carbide semiconductor. Drift layer20has a thickness of t. Semiconductor device102may have a buffer layer between drift layer20and semiconductor substrate10.

Drift layer20has a plurality of well regions23, of a second conductivity type, on a surface part including upper surface20a.Each well region23includes source region24of the first conductivity type and contact region25of the second conductivity type which is provided in source region24and is connected, below source region24, to well region23.

Semiconductor device102includes: gate insulation layer31which is on upper surface20aof drift layer20and exposes at least part of source region24of each well region23, and gate electrodes32which are formed on gate insulation layer31outside depletion control region23cbut, are not formed on gate insulation layer31inside depletion control region23c.Semiconductor device102may further include a channel layer made of silicon carbide of the first conductivity type between drift layer20and gate insulation layer31. Semiconductor device102further includes insulation layer40covering gate electrodes32and covering a structure on upper surface20aof drift layer20. Insulation layer40functions as an interlayer insulation layer.

Similarly to the first exemplary embodiment, first electrode50is in a region, on upper surface20aof drift layer20, except depletion control region20c.Outside depletion control region20c,first electrode50has ohmic contacts with source regions24and contact regions25at parts, of respective source regions24, exposed from gate insulation layer31. Further, outside depletion control region20c,first electrode50covers insulation layer40. In semiconductor device102, first electrode50functions as a source wire.

Similarly to the first exemplary embodiment, semiconductor device102has defect30in at least one of semiconductor substrate10and drift layer20, As described with reference toFIG. 1DtoFIG. 1F, in the plan view parallel to upper surface20aof drift layer20of semiconductor device102, defect30is in depletion control region20c.Depletion control region20chas a shape. including a circle or a sector having a radius of not less than t. Further, in a plan view, a distance from defect30in depletion control region20cto an outer edge of depletion control region20cis not less than t.

Second electrode60is on lower surface10bof semiconductor substrate10and has an ohmic contact with semiconductor substrate10. Second electrode60may be a single layer or stacked layers. Second electrode60is a drain electrode in the present exemplary embodiment. AlthoughFIG. 5Band other drawings do not show, semiconductor device102may further include a protective film covering part of the whole structure. Further, gate electrodes32are connected to gate wire55shown inFIG. 5Aat positions not shown inFIG. 5B.

In semiconductor device102, interfaces of well regions23and a part, of drift layer20, except well regions23make p-n junctions. Therefore, when a voltage is applied between first electrode50and second electrode60so as to reversely bias the p-n junctions, depletion layers are formed in well regions23and in a part, of drift layer20, except well regions23. As the applied voltage is increased, depletion layer20dextends and reaches upper surface20aof drift layer20and an interface between semiconductor substrate10and drift layer20. That is, depletion layer20c1has a thickness of tin a thickness direction of drift layer20. At this time, depletion layer20dextends also in a direction parallel, to upper surface20a,which is, a direction perpendicular to the thickness direction of drift layer20. When the applied voltage is higher than the voltage with which depletion layer20dreaches the interface between semiconductor substrate10and drift layer20, depletion layer20dextends more largely in the parallel direction than in the thickness direction. However, a maximum apply voltage is normally specified by a device specification; thus, depletion layer20ddoes not extremely extend in the parallel direction. The radius of depletion control region20cis preferably not less than t and is more preferably not less than 2t.

With this arrangement, even if a reverse bias voltage is applied between first electrode50and second electrode60, the region, of drift layer20, having the defect30is not depleted; thus, a high reverse bias voltage is not applied to defect30, thereby preventing or reducing generation of a leakage current. Thus, according to the semiconductor device of the present exemplary embodiment, similarly to the first exemplary embodiment, even if the semiconductor substrate and the drift layer have a defect, it is possible to manufacture a semiconductor device which has a small leakage current and can thus satisfy the specification of the product, whereby the product yield can he improved.

With reference toFIG. 3A,FIG. 6AtoFIG. 6JandFIG. 4, a method for manufacturing semiconductor device102will be described.FIG. 6AtoFIG. 6Jare process cross-sectional views illustrating the method for manufacturing semiconductor device102, andFIG. 4is a flowchart.

First, similarly to the first exemplary embodiment, semiconductor substrate10on which drift layer20is formed is prepared (step S1). Further, the defect in semiconductor substrate10on which drift layer20is formed is detected by using a defect inspection apparatus, and position coordinates of detected defect30are recorded (step S2).

As shown inFIG. 6A, by implanting impurities and then performing a thermal treatment, well regions23, source regions24, and contact regions25are formed in a surface part of drift layer20. As described in the first exemplary embodiment, the defect inspection may be performed again after the thermal treatment (step S4).

On the basis of the defect30and the position coordinates of the defect30recorded through the above-described steps, depletion control region20cis determined (step S5). For example, if the thickness of the drift layer20is t, depletion control region20cis determined to be an inside of a circle which is centered at the position coordinates of defect30and has a radius of t.

As shown inFIG. 6B, gate insulation layer31is formed on upper surface20aof drift layer20, and gate electrodes32′ are formed on gate insulation layer31. As shown inFIG. 6C, resist layer71is formed to cover gate electrodes32′ and gate insulation layer31, and opening71cis formed in resist layer71as shown inFIG. 6D. Opening71ccoincides with depletion control region20c.Opening71ccan be formed by removing part of resist layer71by, for example, laser machining.

As shown inFIG. 6E, gate electrodes32′ exposed in opening71care removed by a dry etching process or a wet etching process so as to form gate electrodes32such that gate electrodes32are not on gate insulation layer31inside depletion control region20c.

As shown inFIG. 6F, after resist layer71is removed, insulation layer40′ is formed to cover gate electrodes32and gate insulation layer31(step S6). Subsequently, on insulation layer40′, there is formed resist layer72having openings72cfor defining contact holes.

As shown inFIG. 6G, resist pattern73is formed to cover depletion control region20c.Resist pattern73can be formed, for example, by dropping resist at the recorded position coordinates of the defect. By adjusting viscosity and an amount of the resist, resist pattern73can be formed to have a circular shape whose center coincides in a plan view with the position coordinates of defect30and has a radius of not less than t. As long as an outer edge of resist pattern73is not less than t distant from the position coordinates of defect30, the center of resist pattern73does not have to coincide with the position coordinates of defect30. In addition, the value of the radius may be greater than t, and resist pattern73may have a shape other than a circle. Here, taking overlapping of insulation layer40′ and first electrode50into consideration, resist pattern73is formed to have a circular shape with a radius of 1.1 t, for example.

Resist layer72and resist pattern73are used to etch insulation layer40′ by a dry etching process or a wet etching process, so that insulation layer40is formed to have contact holes40ceach of Which part of each source region24and each contact region25are exposed, as shown inFIG. 6H. After that, resist layer72and resist pattern73are removed.

Next, first electrode50will be formed (step S7). First, as shown inFIG. 6I, an electrode material is deposited on insulation layer40and in contact holes40cso as to cover the above-described structure, and first electrode50′ is formed to be in contact with part of each source region24and each contact region25. On first electrode50′, there is formed resist layer74having opening74cwhich coincides with depletion control region20c.Opening74ccan be formed by removing part of resist layer74by, for example laser machining while the position coordinate of defect30is being used.

Resist layer74is used to remove first electrode50′ in opening74c;thus, first electrode50is formed such that, inside depletion control region20c,first electrode30does not cover insulation layer40and such that, outside depletion control region20c,first electrode50covers insulation layer40.

A semiconductor device and a method for manufacturing the semiconductor device in the exemplary embodiments according to the present disclosure can be suitably used for semiconductor devices for various use, and, in particular, can be suitably used for a power device such as a semiconductor device having a large chip area.