Method of forming fine patterns using double patterning process

A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of forming fine patterns, such as those used in the fabrication of a semiconductor device using a double patterning process. More particularly, the invention relates to a method of forming contact holes having a very fine pitch using a double patterning process.

This application claims the benefit of Korean Patent Application No. 10-2006-0111225, filed on Nov. 10, 2006, the subject matter of which is hereby incorporated by reference.

2. Description of the Related Art

The fabrication of semiconductor devices involves the application of a complex sequence of processes. Included within this complex sequence are multiple processes adapted to form fine patterns on the various material layers forming contemporary semiconductor devices. The extreme integration densities that characterize contemporary semiconductor devices require the formation of patterns with very small geometries, vertical contact holes with very high aspect ratios, and/or very sharp pitches (i.e., relationships between pattern widths and corresponding separation distances between adjacent pattern components).

An aggregate measure or definition of these pattern sizes and relationships is commonly referred to as a design rule. Recent design rules for contemporary semiconductor devices have been drastically reduced to implement emerging integration density demands. The pressure created by these new design rules is pushing (or exceeding) the very limits of conventional fabrication techniques and related equipment. Indeed, available techniques and equipment can not accurately form the fine patterns and pitches demanded by new design rules.

Many of the inherent limitations of conventional techniques and equipment are related to the photolithography processes commonly applied to the formation of patterns. No where are such limitations more apparent than the formation of contact holes in an insulating layer. Contact holes are a basic structure used in semiconductor devices to vertically connect portions of overlying material layers.

As design rule geometries shrink, the lateral area of a contact hole is reduced relative to its vertical depth. In other words, its aspect ratio increases. The formation of relatively smaller and deeper contacts (i.e., contact holes with higher aspect ratios) presents great challenges to conventional photolithography processes which have reached the limit of their resolution. As a result, it is very difficult to reduce minimal separation distances between contacts (i.e., limitations imposed by conventional photolithography processes define contact hole alignment margins that preclude further reductions in the spacing of contact holes).

The formation of high aspect ratio contact holes presents other challenges unrelated to the resolution limitations imposed by conventional photolithography processes. For example, the physical formation of a contact hole requires etching of a material layer. Given the reduced contact hole alignment margins required by emerging design rules, relatively slow etching processes must be applied to the formation of contact holes. Unfortunately, such relatively low etch rate processes sometimes fail to fully form the desired set of contact holes and overall fabrication productivity and quality suffers.

SUMMARY OF THE INVENTION

Embodiments of the invention provides a method of forming fine patterns, such as those used in the fabrication of a semiconductor device, that includes a process of forming a contact hole pattern having a very fine pitch. Such a pattern may be formed despite the resolution limitations inherent in conventional photolithography processes.

In one embodiment of the invention, a method of forming a plurality of contact holes in a material layer formed on a substrate comprises; forming a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, forming a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, forming a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns, etching non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and etching the selected portions of the material layer to form the plurality of contact holes.

DESCRIPTION OF EMBODIMENTS

Embodiments of the invention will now be described with reference to the accompanying drawings. Throughout the drawings and written description, like reference numbers are used to indicate like or similar elements.

FIG. 1Bis a sectional view taken along line Ib-Ib′ ofFIG. 1A. Referring toFIG. 1AandFIG. 1B, a material layer, such as an insulating layer,120is formed on a substrate100. Material layer120may be formed with many different types of material compositions. Similarly, substrate100may take many different forms and be formed from different types of materials (e.g., semi-conducting, semi-insulating, glass, ceramic, silicon-on-insulator, etc.).

A conventional photolithography process is performed in relation to material layer120to form a plurality of first hard mask patterns130. First hard mask patterns130have a first pitch “2P” that is two times greater than a final pitch “P” for the final hard mask patterns ultimately formed by the illustrated method. First hard mask patterns130are formed in a first parallel arrangement along a first direction. In the illustrated example, first hard mask patterns130are formed in a parallel line pattern, but this is just one possible example. Each first hard mask pattern130A is formed with a first width W1. In the illustrated example, first width W1is equal to ¼ of the first pitch 2P of first hard mask patterns130, but other widths are possible. First hard mask patterns130may be formed from one or more of a number of different materials selected in relation to the material composition of material layer120and the etching process that will eventually be used to form a contact hole through material layer120. For example, first hard mask patterns130may be formed from an oxide, a nitride, an oxynitride, a polysilicon, or a metal or metal alloy. In general, however, first hard mask patterns130will be formed from one or more materials having different etch characteristics than material layer120relative to an anticipated etching process.

FIG. 2Bis a sectional view taken along line IIb-IIb′ ofFIG. 2A. Referring toFIG. 2AandFIG. 2B, a buffer layer140is formed with a uniform thickness (third width W3) on first hard mask patterns130and on portions of material layer120exposed through first hard mask patterns130. Buffer layer140is formed with upper surface recesses142each having a second width W2defined by the separation distance between adjacent first hard mask patterns130and the third width W3on first hard mask patterns130.

In the illustrated example, the third width W3thickness of buffer layer140is defined such that the second width W2of each upper surface recess142is equal to ¼ of the first pitch 2P. With this design definition, the third width W3thickness of buffer layer140will also be ¼ of the first pitch 2P. That is, in the illustrated example, the third width W3thickness of buffer layer140is equal to the second width W2of each upper surface recess142, and the first width W1of each first hard mask pattern130.

In one possible fabrication embodiment, buffer layer140is formed using an atomic layer deposition (ALD) method in order to ensure that buffer layer140has the desired uniform thickness on both the upper surface and sidewalls of first hard mask patterns130, as well as the exposed portions of material layer120. Buffer layer140will be formed from a material having different etch characteristics from those of first hard mask patterns130(i.e., a different etch selectivity) relative to a predetermined etching process.

In some embodiments buffer layer140may be formed from at least one oxide selected from a group oxides including a thermal oxide, a chemical vapor deposition (CVD) oxide, an un-doped silicate glass (USG), and a high density plasma (HDP) oxide. Alternately, buffer layer140may be formed from a nitride, an oxynitride, a polysilicon, a metal or metal alloy.

In one embodiment that assumes first hard mask patterns130are formed from an oxide or a polysilicon, buffer layer140may be formed from at least one nitride layer selected from the group consisting of SiON, SiN, SiBN and BN.

In another embodiment, that assumes first hard mask patterns130are formed from an oxide or a nitride, buffer layer140may be formed from a polysilicon layer.

More generally speaking, however, buffer layer140will be formed from a material having different etch characteristics from the material forming first hard mask patterns130and the material forming material layer120relative to a predetermined etching process.

FIG. 3Bis a sectional view taken along line IIIb-IIIb′ ofFIG. 3A. Referring toFIG. 3AandFIG. 3B, a second hard mask layer150is formed on the resultant structure shown inFIG. 2B, including buffer layer140. Second hard mask layer150may be formed from a material having the same (or similar) etch characteristics as the material forming first hard mask patterns130. For example, second hard mask layer150may be formed from an oxide, a nitride, an oxynitride, a polysilicon or metal. In one embodiment assuming buffer layer140is formed from an oxide or nitride, second hard mask layer150may be formed from a polysilicon.

In the illustrated example, second hard mask layer150is formed to completely fill upper surface recesses142. Continuing forward with the working example that assumes a third width W3thickness for buffer layer140equal to ¼ of the first pitch 2P, second mask layer150will include downwardly extending fill portions having a fourth width W4and filling upper surface recesses142. Under the foregoing assumptions, fourth width W4is equal to second width W2for each upper surface recess142which is equal to ¼ of the first pitch 2P.

FIG. 4Bis a sectional view taken along line IVb-IVb′ ofFIG. 4A. Referring toFIG. 4AandFIG. 4B, an upper portion of second hard mask layer150is selectively removed to expose the upper surface of buffer layer140, and thereby form a plurality of second hard mask patterns150ain-filling the upper surface recesses142respectively. In one possible fabrication example, a chemical mechanical polishing (CMP) process may be conventionally applied to remove the upper portion of second hard mask layer150.

In the illustrated embodiment, second hard mask patterns150aare aligned in a second parallel arrangement parallel to and along the first direction defining the first parallel arrangement of first hard mask pattern130. Here again, second hard mask patterns150aare formed in a line pattern.

Interleaving first hard mask patterns130and second hard mask patterns150aform a plurality of composite hard mask patterns156that will be used as an etching mask during an etching process (e.g., a dry etch process) subsequently applied to material layer120. Each one of the paired hard mask pattern elements (i.e., one from the plurality of first hard mask patterns130and one from the plurality of second hard mask patterns150a) forming each one of the plurality of composite hard mask patterns156has a similar width (e.g., first width W1and fourth width W4, each equal to ¼ the first pitch 2P). Accordingly, composite hard mask patterns156has a final pitch P half that of first pitch 2P. Hereafter each composite mask pattern156is said to comprise a first composite mask pattern element formed from one first hard mask pattern130and a related second composite mask pattern element formed from one second hard mask pattern150.

FIG. 5Bis a sectional view taken along line Vb-Vb′ ofFIG. 5A. Referring toFIGS. 5A and 5B, upper mask patterns160are formed on the resultant structure shown inFIG. 4Band including composite hard mask patterns156. Upper mask patterns are formed along a second direction intersecting the first direction so as to partially cover a selected portion of the upper surface of buffer layer140and a respective first composite mask pattern element130in a composite hard mask pattern156.

As shown in the illustrated example ofFIG. 5A, upper mask patterns160may be aligned in a diagonal second direction relative to a horizontally oriented first direction. In certain embodiments of the invention this diagonal second direction may range from between about 5 to 90 degrees relative to the first direction.

Upper mask patterns160may be formed with various geometric properties in accordance with the desired shape and size of the contact holes to be formed through material layer120.

In the foregoing configuration, upper mask patterns160expose a predetermined portion of the upper surface of buffer layer140and second hard mask patterns150a. The exposed portion of the upper surface of buffer layer140corresponds to placement of contact holes formed through material layer120during a subsequent etching process.

Upper mask patterns160may be formed, for example, from a photoresist layer, a three-layered structure formed by a spin on carbon (SOC) film, a Si anti-reflective coating (ARC) film, and a photoresist layer, or a four-layered structure formed by a SOC film, a Si ARC film, an organic ARC film, and a photoresist layer.

FIG. 6Bis a sectional view taken along line VIb-VIb′ ofFIG. 6A. Referring toFIG. 6AandFIG. 6B, the exposed (i.e., portions non-selected by the masking operation performed by upper mask patterns160) portion of buffer layer140is anisotropically etched using upper mask patterns160and composite mask patterns156as an etch mask, thereby forming a plurality of hard mask holes170. Each hard mask hole170exposes the sidewall of a first composite hard mask pattern element130and the sidewall of a corresponding second composite hard mask pattern element150a. A dry etching process or a plasma enhanced reactive ion etching process may be used to form hard mask holes170. An upper surface region of material layer120is exposed through each hard mask hole170.

FIG. 7Bis a sectional view taken along line VIIb-VIIb′ ofFIG. 7A. Referring toFIG. 7AandFIG. 7B, the portions of material layer120exposed through hard mask holes170may now be anisotropically etched using upper mask patterns160and composite hard mask patterns156as an etch mask to thereby form patterned insulating layer120acontaining a plurality of contact holes120h. At this point in the fabrication process, upper mask patterns160, residual portions of buffer layer140, first hard mask patterns130, and second hard mask patterns150aremaining on patterned material layer120amay be removed.

Contact holes120hformed through patterned material layer120aare aligned and separated on semiconductor substrate100by a final pitch P that is half the first pitch 2P. Assuming that first pitch 2P is the minimum pitch that may be accurately implemented using a conventional photolithography process, final pitch P of contact holes120hmay be up to half as small the original pitch limit. Thus, embodiments of the invention offer dramatic improvements in the realizable pitch between adjacent contact holes in a set of fabrication contact holes.

In the foregoing embodiments, the interleaving first and second hard mask patterns may be formed using a self-aligned process. Since contact holes120hin the illustrated example are formed using a dry etching process in conjunction with composite hard mask patterns156and upper mask patterns160, they may be formed with proper alignment and with sufficient etching margin. Contact holes120hmay be readily formed with a desired cross-section geometry by manipulating the respective geometries and layout orientation of first hard mask patterns130, second hard mask patterns150a, and upper mask patterns160.

FIG. 8is a layout diagram illustrating a set of contacts280which may be realized using a fabrication method consistent with an embodiment of the present invention. InFIG. 8, each contact280may be electrically connected within one of a plurality of island-shaped active regions202on a semiconductor substrate200. The set of contacts may serve many different purposes, such as for example, a buried contact (BC) electrically connecting the storage node of a capacitor to a corresponding active region202, or a direct contact (DC) electrically connecting a bit line to a corresponding active region202. The geometry and composition of active regions202, as well as the geometry and layout of contacts280will vary by application, the example illustrated inFIG. 8being one of many such possibilities.

FIGS. 9A,10A, throughFIG. 14Aare plan views illustrating a method of forming fine patterns to embodiments of the present invention.FIGS. 9B,10B, throughFIG. 14Bare related sectional views ofFIGS. 9A,1A, through14A. The geometry and location of an exemplary active region202is incorporated in the description that follows to facilitate a better understanding of the embodiments illustrated inFIGS. 9A,10A throughFIG. 14A.

FIG. 9Bis a sectional view taken along line IXb-IXb′ ofFIG. 9A. Referring toFIG. 9AandFIG. 9B, a material layer220is formed on a semiconductor substrate200in similar manner to that of material layer120ofFIGS. 1A and 1B. A plurality of first hard mask patterns230are formed on material layer220in similar manner to that of first hard mask patterns130ofFIGS. 1A and 1B.

In embodiments illustrated inFIGS. 9AthroughFIG. 14B, first hard mask patterns230are formed in a parallel arrangement in a first direction. As illustrated inFIGS. 9A and 9B, a line pattern may be formed for first hard mask patterns230with a first pitch P′. As also illustrated inFIG. 9A, respective first hard mask patterns230may be formed with a first variable (non-uniform) width W5in the first direction. For example, first hard mask patterns230include first width portions having a first width Ws1. First width portions of first hard mask pattern230are formed in correlation with an active region202. Each first hard mask pattern230also includes second width portions having a second width Ws2less than the first width Ws1. Second width portions of the first hard mask patterns connect adjacent first width portions, and generally reside outside the boundaries of active regions202. With this type of arrangement, the sidewalls of the first hard mask patterns230may be formed with a curved shape, for example, an S type (or serpentine type) shape.

FIG. 10Bis a sectional view taken along line Xb-Xb′ ofFIG. 10A. Referring toFIG. 10AandFIG. 10B, a buffer layer240is formed with a uniform thickness on first hard mask patterns230and portions of material layer220exposed through first hard mask patterns230in similar manner to that of buffer layer140ofFIGS. 2A and 2B. Referring toFIGS. 9AthroughFIG. 14B, since buffer layer240is formed on the sidewalls of first hard mask patterns230—which has a variable width, upper surface recesses242having a second variable width Wr are formed. The second variable width will vary with the thickness of buffer layer240and in relation to the varying separation distances between adjacent first hard mask patterns230. In some cases, the second variable width Wr associated with upper surface recess242may actually reach zero. Hence, some upper surface recesses242may not be formed in relation to some adjacent first hard mask patterns230.

FIG. 11Bis a sectional view taken along line XIb-XIb′ofFIG. 11A. Referring toFIG. 11AandFIG. 11Ba hard mask layer is formed on the resultant structure shown inFIG. 10Bincluding buffer layer240in a manner similar to that of second hard mask patterns150aofFIGS. 3A,3B,4A and4B. Again, a conventional CMP process may be used to polish the hard mask layer until an upper surface portion is removed to expose the upper surface of buffer layer240. In this manner, interleaving second hard mask patterns250are formed by the portions of the hard mask layer in-filling upper surface recesses242. As before, first hard mask patterns230and second hard mask patterns250form a composite hard mask pattern256that is subsequently used as an etch mask for etching material layer220.

FIG. 12Bis a sectional view taken along line XIIb-XIIb′ ofFIG. 12A. Referring toFIG. 12AandFIG. 12B, upper mask patterns260are formed on the resultant structure shown inFIG. 11Bincluding composite mask pattern256in a manner similar to that of composite mask patterns156ofFIGS. 5A and 5B.FIG. 12Ashows upper mask patterns260having a line pattern shape, but the invention is not limited thereto. Upper mask patterns260may be formed in various other shapes depending on the desired cross-sectional geometry of the contact holes formed through material layer220.

Predetermined portions of the upper surface of buffer layer240and the second hard mask patterns250are exposed by mask patterns260. The exposed portions of the upper surface of buffer layer240correspond to regions where contact holes220h(FIGS. 14A and 14B) are to be formed through insulating layer220during a subsequent etching process.

FIG. 13Bis a sectional view taken along line XIIIb-XIIIb′ ofFIG. 13A. Referring toFIG. 13AandFIG. 13B, portions of buffer layer240exposed by mask patterns260and composite hard mask256are anisotropically etched in a manner similar to that described in relation toFIGS. 6A and 6Bto form hard mask holes270exposing sidewalls of first hard mask patterns230and second hard mask patterns250. Selected portions of the upper surface of material layer220are exposed through hard mask holes270.

FIG. 14Bis a sectional view taken along line XIVb-XIVb′ ofFIG. 14A. Referring toFIG. 14AandFIG. 14B, portions of the material layer220exposed through hard mask holes270are anisotropically etched using upper mask patterns260, first hard mask patterns230, and second hard mask patterns250as an etch mask in a manner similar to that described above in relation toFIGS. 7A and 7Bin order to form patterned material layer220aincluding contact holes220h. At this point in the fabrication process, upper mask patterns260, residual portions of buffer layer240, first hard mask patterns230, and second hard mask patterns250remaining on patterned material layer patterns220amay be removed.

If the first pitch P′ of first hard mask patterns230is a minimum pitch allowable within a limit of resolution for a conventional photolithography process, contact holes220hmay be formed in patterned material layer220awith a final pitch P″ that is much smaller than the first pitch P′. Thus, contact hole220hwidths and separation distances between adjacent contact holes220hmay be realized with a much finer pitch than that realizable through the use of conventional photolithography processes. Furthermore, the disclosed double patterning process makes use of self-aligned second hard mask patterns250and first hard mask patterns230to form composite hard mask patterns256. Since contact holes220hmay be formed using a dry-etching process in conjunction with composite hard mask patterns256and upper mask patterns260, it is relatively easy to align contact holes220hinto desired positions while also providing adequate etch margins. Contact holes220hmay be readily formed in a variety of cross-sectional geometries, including one or more curved surfaces. This may be accomplished by defining geometries and relative layout arrangements for first hard mask patterns230, second hard mask patterns250, and upper mask patterns260.

In a method of forming fine patterns, such as those used in the fabrication of semiconductor devices, according to embodiments of the present invention, contact patterns may be formed with very fine pitches and excellent critical dimension (CD) uniformity by employing the double patterning process that effectively overcomes the resolution limits of conventional photolithography processes. This is particularly true in the formation of the hard masks defining the geometry of a set of contact holes having a very fine pitch. That is, the location of the contact holes may be determined by the layout positioning of first hard mask patterns formed using a conventional photolithography process, and the self-aligned, relative layout positioning of second (sacrificial) hard mask patterns and upper mask patterns. Therefore, the process of accurately defining the cross-sectional geometry of the contact holes is relatively straight-forward and well controlled. In this manner, sufficient etch margin may be ensured between adjacent contact holes.

In the foregoing description, the use of terms such as first, second, etc., vertical and horizontal, upper and lower, etc., is entirely relative. No particular ordering or orientation is mandated. Such terms merely distinguish related components in the foregoing embodiments.