A method to form an ultra-shallow junction is described. In one embodiment, a replacement gate process is utilized to enable the overlap of a gate electrode over the regions of a semiconductor substrate where tip extensions reside. In another embodiment, a sacrificial spacer is utilized in conjunction with the replacement gate process. In one embodiment, an initial gate electrode is formed with a gate length smaller than the desired final gate length and is subsequently replaced with an expanded gate electrode having the desired gate length.

BACKGROUND OF THE INVENTION

1) Field of the Invention

The invention is in the field of Semiconductor Devices.

2) Description of Related Art

For the past several years, the performance of semiconductor devices, such as Metal Oxide Semiconductor Field-Effect Transistors (MOS-FETs), has been greatly enhanced by the incorporation of shallow junctions into the active portions of a semiconductor substrate, e.g. the use of shallow tip extensions. The presence of such shallow junctions may greatly enhance the rate at which charge migrates in a channel when a semiconductor is in an ON state.

In the drive for ever-shallower junction depths, laser annealing of a dopant-implanted region of a semiconductor substrate may be utilized. Under appropriate annealing conditions, a laser anneal process may activate dopants, i.e. cause them to be substitutionally incorporated into the lattice of a substrate material, with negligible diffusion of the dopants into other regions of the substrate. This effect may be desirable because the depth of a junction may be kept confined to the implant depth of the dopant impurities, providing an ultra-shallow junction. However, the lateral diffusion of the dopants may also be restricted by the above annealing process. This may be undesirable in the case where overlap of a gate electrode over tip extensions is insufficient for optimal performance of, e.g. a MOS-FET. Thus, a method to fabricate ultra-shallow junctions is described herein.

DETAILED DESCRIPTION

A process for fabricating semiconductor devices and the resultant devices are described. In the following description, numerous specific details are set forth, such as specific dimensions and chemical regimes, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as patterning steps or wet chemical cleans, are not described in detail in order to not unnecessarily obscure the present invention. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Disclosed herein is a method to form ultra-shallow junctions for semiconductor devices. Laser annealing of dopant impurity atoms implanted into a substrate may activate the dopant impurity atoms, i.e. cause them to be substitutionally integrated into the lattice of the substrate, while minimizing the extent of diffusion of the dopant impurity atoms during the annealing process. By minimizing the diffusion of the dopant impurity atoms, a highly doped ultra-shallow junction may be achieved. The ultra-shallow junction may enable the formation of high performance semiconductor devices, such as high speed MOS-FETs for use in logic and memory applications. In order to accommodate for a low-diffusion annealing process, an expansion replacement gate process may be employed to cause a gate electrode to overlap the ultra-shallow junctions. Thus, optimization of a high performance semiconductor device may be achieved.

Charge-carrier dopant impurity atoms may be incorporated into a crystalline substrate or an epitaxial film, e.g. carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium in a III-V substrate/epitaxial film or phosphorus, boron, indium or arsenic in a silicon substrate/epitaxial film. An implant process may be used to deliver a high concentration of dopant impurity atoms into the crystalline lattice of a semiconductor substrate or epitaxial film to form shallow interstitial implant regions within the crystalline lattice. Activation of the implanted dopant impurity atoms to cause substitutional doping in the lattice of the semiconductor may be achieved by a variety of annealing methods. Laser annealing may be used to activate dopant impurity atoms to form ultra-shallow junctions, such as ultra-shallow tip extensions for high performance MOS-FETs. Since laser annealing may mitigate diffusion of the dopant impurity atoms deeper into the semiconductor substrate, an ultra-shallow profile may be maintained. Thus, high concentration, yet very shallow, tip extensions may be formed.

In order to optimize the performance of a semiconductor device that incorporates ultra-shallow junctions, such as ultra-shallow tip extensions, it may be desirable to expand the gate length of a gate electrode used in conjunction with the ultra-shallow junctions. For example, in accordance with an embodiment of the present invention, tip extensions are formed by implanting dopant impurity atoms in a process that is self-aligned to a gate electrode placeholder. Thus, implant regions may be formed in the substrate, on either side of a gate electrode, and subsequently laser annealed to form ultra-shallow tip extensions. The diffusion of the dopant impurity atoms may be mitigated to the extent that the gate electrode negligibly overlaps the portions of the semiconductor substrate containing the tip extensions. For optimal performance of the semiconductor device that comprises such ultra-shallow tip extensions and a gate electrode, it may be desirable to expand the gate electrode, either before or after the annealing process, in order to cause the gate electrode to overlap the tip extensions. In accordance with an embodiment of the present invention, a replacement gate process is utilized to enable the overlap of a gate electrode over the regions of a semiconductor substrate where tip extensions reside. A sacrificial spacer may be utilized in conjunction with the replacement gate process. Thus, by forming an initial gate electrode with a gate length smaller than the desired final gate length and subsequently replacing the initial gate electrode with an expanded gate electrode having the desired gate length, optimization of semiconductor devices that incorporate ultra-shallow junctions may be achieved.

A replacement gate technique may be used to optimize the incorporation of ultra-shallow junctions into a high performance semiconductor device.FIGS. 1A-Billustrate cross-sectional views representing the formation of a planar MOS-FET with ultra-shallow junctions, in accordance with an embodiment of the present invention. MOS-FET100A may be comprised of substrate or epitaxial layer102which includes a channel region104, a gate dielectric layer106A, a gate electrode placeholder108A, ultra-shallow tip extensions110, source/drain regions112, an inner set of gate isolation spacers114and an outer set of gate isolation spacers116. In accordance with an embodiment of the present invention, gate electrode placeholder108A overlaps negligibly over ultra-shallow tip extensions110, as depicted inFIG. 1A.

Referring toFIG. 1B, inner set of gate isolation spacers114may be removed. Additionally, gate dielectric layer106A and gate electrode placeholder108A may be replaced with gate dielectric layer106B and gate electrode108B, respectively. In accordance with an embodiment of the present invention, gate electrode108B overlaps the region of substrate or epitaxial layer102that comprises ultra-shallow tip extensions110. Thus, the dimensions of a gate electrode placeholder108A with a smaller than desirable gate length, coupled with a removable inner set of gate isolation spacers114, may be targeted for fabrication of gate electrode108B with an expanded, and desired, gate length, which overlaps ultra-shallow tip extensions110.

Ultra-shallow junctions with overlapping features, such as ultra-shallow tip extensions with an overlapping gate electrode, may be formed for any semiconductor device. In one embodiment, the semiconductor device is a planar MOS-FET, a bipolar transistor, a memory transistor or a micro-electronic machine (MEM). In another embodiment, the semiconductor device is a non-planar device, such as a tri-gate or double-gate transistor, an independently-accessed double gated MOS-FET, or a gate-all-around MOS-FET with a nanowire channel.FIGS. 2A-Iillustrate cross-sectional views representing the formation of a planar MOS-FET with ultra-shallow junctions, in accordance with an embodiment of the present invention. As will be appreciated in the typical integrated circuit, both N- and P-channel transistors may be fabricated in a single substrate or epitaxial layer to form a CMOS integrated circuit.

As an example of one embodiment of the present invention,FIGS. 2A-Killustrate the formation of ultra-shallow tip extensions optimized with a replacement gate process scheme. Referring toFIG. 2A, a gate electrode placeholder208A is formed above a gate dielectric layer206A, which is formed above substrate or epitaxial layer202. Substrate or epitaxial layer202may be non-insulating and may comprise a semiconducting material. In one embodiment, substrate or epitaxial layer202is formed by doping a crystalline silicon, germanium or silicon/germanium layer with an appropriate charge carrier, such as but not limited to phosphorus, arsenic, boron, indium or a combination thereof. In another embodiment, substrate or epitaxial layer202is comprised of a III-V material such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide or indium antimonide.

Gate dielectric layer206A may be formed with any material suitable to insulate gate electrode208A from substrate or epitaxial layer202. In accordance with one embodiment of the present invention, gate dielectric layer206A is formed with a material suitable for removal without impacting substrate or epitaxial layer202. In one embodiment, gate dielectric layer206A is formed by a thermal oxidation process or a PE-CVD process and is comprised of silicon dioxide or silicon oxy-nitride. In another embodiment, gate dielectric layer206A is formed by chemical vapor deposition or atomic layer deposition and is comprised of a high-k dielectric layer such as, but not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride or lanthanum oxide. In one embodiment, gate dielectric206A is the final gate dielectric layer, i.e. it is not subsequently replaced.

Gate electrode placeholder208A may be formed with any material suitable for patterning at dimensions smaller than the desired gate length of the final semiconductor device. In accordance with an embodiment of the present invention, gate electrode placeholder208A is formed with a material suitable for removal at the replacement gate step, as discussed below. In one embodiment, gate electrode placeholder208A is comprised of polycrystalline silicon, amorphous silicon, silicon dioxide, silicon nitride, a metal layer or a combination thereof. In another embodiment, a protective capping layer218, such as a silicon dioxide or silicon nitride layer, is formed above gate electrode placeholder208A.

Ultra-shallow tip extensions210may be formed by implanting charge carrier dopant impurity atoms into substrate or epitaxial layer202, as depicted in FIG.2B. In accordance with an embodiment of the present invention, gate electrode placeholder208A acts to mask a portion of substrate or epitaxial layer202, forming self-aligned ultra-shallow tip extensions210. By self-aligning ultra-shallow tip extensions210with gate electrode placeholder208A, channel region204may be formed in the region of substrate or epitaxial layer202that is underneath gate electrode placeholder208A and gate dielectric layer206A, as depicted inFIG. 2B. In one embodiment, boron, arsenic, phosphorus, indium or a combination thereof is implanted into substrate or epitaxial layer202to form ultra-shallow tip extensions210. In another embodiment, the charge carrier dopant impurity atoms implanted to form ultra-shallow tip extensions210are of opposite conductivity to channel region204.

In order to activate the charge carrier dopant impurity atoms implanted into substrate or epitaxial layer202to form ultra-shallow tip extensions210, any suitable annealing technique may be used. In accordance with an embodiment of the present invention, a laser annealing technique is employed to cause the charge carrier dopant impurity atoms of ultra-shallow tip extensions210to become substitutionally incorporated into the atomic lattice of substrate or epitaxial layer202. Conditions of the laser anneal process may be selected such that diffusion of the charge carrier dopant impurity atoms from ultra-shallow tip extensions210into other regions of substrate or epitaxial layer202is negligible. In one embodiment, ultra-shallow tip extensions210are annealed with an eximer laser for a duration of 10 nanoseconds-1000 nanoseconds. In another embodiment, ultra-shallow tip extensions210are formed by implanting phosphorus dopant atoms with an energy in the range of 2 keV-10 keV at a dose in the range of 5E14 atoms/cm2-5E15 atoms/cm2to form a post-annealing phosphorus dopant concentration in the range of 1E20 atoms/cm3-1E21 atoms/cm3, or by implanting arsenic dopant atoms with an energy in the range of 1 keV-5 keV at a dose in the range of 5E14 atoms/cm2-5E15 atoms/cm2to form a post-annealing arsenic dopant concentration in the range of 1E20 atoms/cm3-1E21 atoms/cm3, or by implanting boron dopant atoms with an energy in the range of 0.2 keV-1 keV at a dose in the range of 5e14 atoms/cm2-5E15 atoms/cm2to form a post-annealing boron dopant concentration in the range of 1E20 atoms/cm3-1E21 atoms/cm3. In one embodiment, subsequent to the laser annealing step, ultra-shallow tip extensions210have a depth in substrate or epitaxial layer202in the range of 5 nanometers-30 nanometers.

A pair of inner gate isolation spacers may then be formed by any suitable technique. In one embodiment, referring toFIG. 2C, a material layer230is deposited by a chemical vapor deposition process and is conformal with the structure formed inFIG. 2B. In an embodiment, material layer230is comprised of an insulating layer. In a particular embodiment, material layer230is comprised of silicon dioxide, silicon oxy-nitride, carbon-doped silicon oxide or a combination thereof. In another embodiment, material layer230is comprised of silicon nitride or carbon-doped silicon nitride.

Material layer230may be deposited to a thickness selected to determine the final width of the inner gate isolation spacers. Since the inner gate isolation spacers may subsequently be removed during the replacement gate process, material layer230may be deposited to a thickness that determines the expansion width of the replacement gate electrode, i.e. to determine the amount that the replacement gate electrode will overlap ultra-shallow tip extensions210. In accordance with an embodiment of the present invention, material layer230is deposited to a thickness of half the desired gate electrode expansion width. In one embodiment, material layer230is deposited to a thickness in the range of 50-200 Angstroms. In another embodiment, material layer230is deposited to a thickness in the range of 75-150 Angstroms and the width (i.e. gate length) of gate electrode placeholder208is in the range of 10-20 nanometers.

Referring toFIG. 2D, inner gate isolation spacers214may be formed from material layer230by an anisotropic etch process. In one embodiment, material layer230is dry etched by a remote plasma etch or a reactive ion etch process. In another embodiment, material layer230is patterned to form inner gate isolation spacers214by using a vertical dry or plasma etch process comprising fluorocarbons of the general formula CxFy, where x and y are natural numbers. In another embodiment, material layer230is patterned to form inner gate isolation spacers214by using a vertical dry or plasma etch process comprising free radical fluorocarbons. Inner gate isolation spacers214may sit above the top surface of substrate or epitaxial layer202and may have a width at the top surface of substrate or epitaxial layer202substantially equal to the original thickness of material layer230. In accordance with an embodiment of the present invention, inner gate isolation spacers214reside above ultra-shallow tip extensions210. In one embodiment, inner gate isolation spacers214form a hermetic seal with gate electrode placeholder208A and the top surface of substrate or epitaxial layer202to encapsulate gate dielectric layer206A, as depicted inFIG. 2D. In one embodiment, a wet chemical cleaning process step comprising the application of an aqueous solution of hydrofluoric acid, ammonium fluoride or both follows the formation of inner gate isolation spacers214.

A pair of outer gate isolation spacers may then be formed by any suitable technique. In one embodiment, referring toFIG. 2E, a material layer240is deposited by a chemical vapor deposition process and is conformal with the structure formed inFIG. 2D. In an embodiment, material layer240is comprised of an insulating layer. In a particular embodiment, material layer240is comprised of silicon dioxide, silicon oxy-nitride or carbon-doped silicon oxide. In another embodiment, material layer240is comprised of silicon nitride or carbon-doped silicon nitride. In accordance with an embodiment of the present invention, material layer240has different etch characteristics as compared to the etch characteristics of material layer230used to from inner gate isolation spacers214. Thus, inner gate isolation spacers214may be etched selectively without impacting material layer240or structures formed therefrom. In one embodiment, material layer240is comprised of silicon dioxide, silicon oxy-nitride or carbon-doped silicon oxide and inner gate isolation spacers214are comprised of silicon nitride or carbon-doped silicon nitride. In another embodiment, material layer240is comprised of silicon nitride or carbon-doped silicon nitride and inner gate isolation spacers214are comprised of silicon dioxide, silicon oxy-nitride or carbon-doped silicon oxide.

Material layer240may be deposited to a thickness selected to determine the final width of the outer gate isolation spacers. In accordance with an embodiment of the present invention, material layer240is deposited to a thickness of that determines the location of self-aligned source/drain regions. In one embodiment, material layer240is deposited to a thickness in the range of 5-300 Angstroms.

Referring toFIG. 2F, outer gate isolation spacers216may be formed from material layer240by an anisotropic etch process. In one embodiment, material layer240is dry etched by a remote plasma etch or an active ion etch process. In another embodiment, material layer240is patterned to form outer gate isolation spacers216by using a vertical dry or plasma etch process comprising fluorocarbons of the general formula CxFy, where x and y are natural numbers. In another embodiment, material layer240is patterned to form outer gate isolation spacers216by using a vertical dry or plasma etch process comprising free radical fluorocarbons. Outer gate isolation spacers216may sit above the top surface of substrate or epitaxial layer202and may have a width at the top surface of substrate or epitaxial layer202substantially equal to the original thickness of material layer240. In accordance with an embodiment of the present invention, outer gate isolation spacers216reside above ultra-shallow tip extensions210. In one embodiment, outer gate isolation spacers216form a hermetic seal with inner gate isolation spacers214and the top surface of substrate or epitaxial layer202, as depicted inFIG. 2F. In one embodiment, a wet chemical cleaning process step comprising the application of an aqueous solution of hydrofluoric acid, ammonium fluoride or both follows the formation of outer gate isolation spacers216.

Referring toFIG. 2F, source/drain regions212may subsequently be formed by implanting charge carrier dopant impurity atoms into substrate or epitaxial layer202. Outer gate isolation spacers216, inner gate isolation spacers214and gate electrode placeholder208A may act to mask a portion of substrate or epitaxial layer202, forming self-aligned source/drain regions212. In effect, the width of outer gate isolation spacers216may play a role in determining the dimensions and location of source/drain regions212. In one embodiment, boron, arsenic, phosphorus, indium or a combination thereof is implanted into substrate or epitaxial layer202to form source/drain regions212. Subsequent to the formation of source/drain regions212, raised source/drain regions which strain the channel region may be formed and/or a silicide process may be carried out; these process steps are known in the art.

Subsequent to the formation of outer gate isolation spacers216and source/drain regions212, process steps compatible with a replacement gate process scheme may be carried out. In accordance with an embodiment of the present invention, an interlayer dielectric layer is formed over the structure ofFIG. 2Fand the interlayer dielectric layer is polished back with a chemical-mechanical polish step to reveal gate electrode placeholder208A. In one embodiment, protective capping layer218acts as a polish-stop layer and a wet etch process is used to remove protective capping layer218in order to reveal the top surface of gate electrode placeholder208A. Referring toFIG. 2G, the interlayer dielectric layer may be polished such that the top surface of the resulting interlayer dielectric blocks220is flush with the top surface of gate electrode placeholder208A, revealing inner gate isolation spacers214and outer gate isolation spacers216.

Referring toFIG. 2H, gate electrode placeholder208A may be removed by any suitable technique that does not significantly impact interlayer dielectric blocks220, outer gate isolation spacers216, inner gate isolation spacers214or gate dielectric layer206A. In accordance with an embodiment of the present invention, gate electrode placeholder208A is removed by a dry etch or wet etch process. In one embodiment, gate electrode placeholder208A is comprised of polycrystalline silicon or amorphous silicon and is removed with a dry etch process comprising SF6. In another embodiment, gate electrode placeholder208A is comprised of polycrystalline silicon or amorphous silicon and is removed with a wet etch process comprising aqueous NH4OH or tetramethylammonium hydroxide. In an embodiment, gate electrode placeholder208A is comprised of silicon dioxide and is removed with a wet etch comprising aqueous hydrofluoric acid, ammonium fluoride or both. In one embodiment, gate electrode placeholder208A is comprised of silicon nitride and is removed with a wet etch comprising aqueous phosphoric acid.

Referring toFIG. 2I, gate dielectric layer206A may be removed by any suitable technique that does not significantly impact interlayer dielectric blocks220, outer gate isolation spacers216or substrate or epitaxial layer202, including ultra-shallow tip extensions210and source/drain regions212. In accordance with an embodiment of the present invention, gate dielectric layer206A is removed by a dry etch or wet etch process. In one embodiment, gate dielectric layer206A is comprised of silicon dioxide or silicon oxy-nitride and is removed with a wet etch comprising aqueous hydrofluoric acid, ammonium fluoride or both. In another embodiment, gate dielectric layer206A is comprised of a high-k dielectric layer and is removed with a wet etch comprising aqueous phosphoric acid. In one embodiment, inner gate isolation spacers214are removed in the same step as the removal of gate dielectric layer206A. In another embodiment, the final gate dielectric layer comprises gate dielectric206A, i.e.206A is not removed. In one embodiment, gate dielectric layer206A is removed in the same step as the removal of gate electrode placeholder208A.

Referring toFIG. 2J, inner gate isolation spacers214may be removed by any suitable technique that does not significantly impact interlayer dielectric blocks220, outer gate isolation spacers216or substrate or epitaxial layer202, including ultra-shallow tip extensions210and source/drain regions212. In accordance with an embodiment of the present invention, inner gate isolation spacers214are removed by a dry etch or wet etch process. In one embodiment, inner gate isolation spacers214are comprised of silicon dioxide, silicon oxy-nitride or carbon-doped silicon oxide and are removed with a wet etch comprising aqueous hydrofluoric acid, ammonium fluoride or both. In another embodiment, inner gate isolation spacers214are comprised of silicon nitride or carbon-doped silicon nitride and are removed with a wet etch comprising aqueous phosphoric acid. In one embodiment, inner gate isolation spacers214are removed in the same step as the removal of gate electrode placeholder208A. In another embodiment, inner gate isolation spacers214are removed in the same step as the removal of gate dielectric layer206A. In one embodiment, inner gate isolation spacers214are removed in the same step as the removal of gate electrode placeholder208A and gate dielectric layer206A.

The structure fromFIG. 2Jmay provide a framework for a replacement gate process. Referring toFIG. 2K, a replacement gate dielectric layer206B may be formed above substrate or epitaxial layer202. In accordance with an embodiment of the present invention, replacement gate dielectric layer206B is formed with any material suitable to insulate gate electrode208B from substrate or epitaxial layer202. In one embodiment, replacement gate dielectric layer206B is formed by a thermal oxidation process and is comprised of silicon dioxide or silicon oxy-nitride. In another embodiment, replacement gate dielectric layer206B is formed by chemical vapor deposition or atomic layer deposition and is comprised of a high-k dielectric layer such as, but not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride or lanthanum oxide. In one embodiment, replacement gate dielectric layer206B is deposited conformally with the top surface of substrate or epitaxial layer202and with the sidewalls of outer gate isolation spacers216, as depicted inFIG. 2K.

Gate electrode208B may be formed with any material with conductive properties and suitable for filling the region between outer gate isolation spacers216. In one embodiment, gate electrode208B is comprised of doped polycrystalline silicon or a silicide thereof. In another embodiment, gate electrode208B is comprised of a metal layer such as but not limited to metal nitrides, metal carbides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides, e.g. ruthenium oxide. In one embodiment, a chemical-mechanical process step is used subsequent to forming gate electrode208B in order to remove unwanted material from the surface of interlayer dielectric blocks220, as depicted inFIG. 2K. In accordance with an embodiment of the present invention, gate electrode208B overlaps the portion of substrate or epitaxial layer202that comprises ultra-shallow tip extensions210, as depicted inFIG. 2K.

Thus, referring toFIG. 2K, a planar MOS-FET200comprising a gate electrode that overlaps ultra-shallow junctions may be formed by way of an expansion replacement gate process utilizing sacrificial gate isolation spacers. Planar MOS-FET200may be an N-type or a P-type semiconductor device. As will be appreciated in the typical integrated circuit, both N- and P-channel transistors may be fabricated in a single substrate or epitaxial layer to form a CMOS integrated circuit.

The present invention is not limited to a two-spacer process. For example, a single spacer process may be used to form semiconductor device comprising a gate electrode that overlaps ultra-shallow junctions.FIGS. 3A-Dillustrate cross-sectional views representing the formation of a planar MOS-FET with ultra-shallow junctions, in accordance with an embodiment of the present invention. Referring toFIG. 3A, MOS-FET300A may be comprised of substrate or epitaxial layer302which includes a channel region304, a gate dielectric layer306A, a gate electrode placeholder308A, ultra-shallow tip extensions310, source/drain regions312and a single set of gate isolation spacers314. In accordance with an embodiment of the present invention, gate electrode placeholder308A overlaps negligibly over ultra-shallow tip extensions310, as depicted inFIG. 3A.

Referring toFIG. 3B, gate electrode placeholder308A may be removed by any suitable technique that does not significantly impact interlayer dielectric blocks320, gate isolation spacers314or gate dielectric layer306A. In accordance with an embodiment of the present invention, gate electrode placeholder308A is removed by a dry etch or wet etch process. In one embodiment, gate electrode placeholder308A is comprised of polycrystalline silicon or amorphous silicon and is removed with a dry etch process comprising SF6. In another embodiment, gate electrode placeholder308A is comprised of polycrystalline silicon or amorphous silicon and is removed with a wet etch process comprising aqueous NH4OH or tetramethylammonium hydroxide. In an embodiment, gate electrode placeholder308A is comprised of silicon dioxide and is removed with a wet etch comprising aqueous hydrofluoric acid, ammonium fluoride or both. In one embodiment, gate electrode placeholder308A is comprised of silicon nitride and is removed with a wet etch comprising aqueous phosphoric acid. In another embodiment, gate electrode placeholder308A comprises a metal layer that is removed with a Piranha (H2SO4/H2O2/H2O) wet etch.

Referring toFIG. 3B, gate dielectric layer306A may be removed by any suitable technique that does not significantly impact interlayer dielectric blocks320, gate isolation spacers314or substrate or epitaxial layer302, including ultra-shallow tip extensions310and source/drain regions312. In accordance with an embodiment of the present invention, gate dielectric layer306A is removed by a dry etch or wet etch process. In one embodiment, gate dielectric layer306A is comprised of silicon dioxide or silicon oxy-nitride and is removed with a wet etch comprising aqueous hydrofluoric acid, ammonium fluoride or both. In another embodiment, gate dielectric layer306A is comprised of a high-k dielectric layer and is removed with a wet etch comprising aqueous phosphoric acid. In one embodiment, gate isolation spacers316are thinned in the same step as the removal of gate dielectric layer306A.

Referring toFIG. 3C, gate isolation spacers314may be thinned to form thinned gate isolation spacers316by any suitable technique that does not significantly impact interlayer dielectric blocks320or substrate or epitaxial layer302, including ultra-shallow tip extensions310and source/drain regions312. In accordance with an embodiment of the present invention, gate isolation spacers314are thinned by a dry etch or wet etch process. In one embodiment, gate isolation spacers314are comprised of silicon dioxide, silicon oxy-nitride or carbon-doped silicon oxide and are thinned with a wet etch comprising aqueous hydrofluoric acid, ammonium fluoride or both. In another embodiment, gate isolation spacers314are comprised of silicon nitride or carbon-doped silicon nitride and are thinned with a wet etch comprising aqueous phosphoric acid. In accordance with an embodiment of the present invention, gate isolation spacers314are thinned to an extent determined by the desired amount of overlap of a replacement gate electrode over ultra-shallow tip extensions. In one embodiment, gate isolation spacers314are thinned by an amount in the range of 50-200 Angstroms and the width (i.e. gate length) of gate electrode placeholder308is in the range of 10-20 nanometers.

The structure fromFIG. 3Cmay provide a framework for a replacement gate process. Referring toFIG. 3D, a replacement gate dielectric layer306B may be formed above substrate or epitaxial layer302. In accordance with an embodiment of the present invention, replacement gate dielectric layer306B is formed with any material suitable to insulate gate electrode308B from substrate or epitaxial layer302. In one embodiment, replacement gate dielectric layer306B is formed by a thermal oxidation process and is comprised of silicon dioxide or silicon oxy-nitride. In another embodiment, replacement gate dielectric layer306B is formed by chemical vapor deposition or atomic layer deposition and is comprised of a high-k dielectric layer such as, but not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride or lanthanum oxide. In one embodiment, replacement gate dielectric layer306B is deposited conformally with the top surface of substrate or epitaxial layer302and with the sidewalls of thinned gate isolation spacers316, as depicted inFIG. 3D.

Gate electrode308B may be formed with any material with conductive properties and suitable for filling the region between thinned gate isolation spacers316. In one embodiment, gate electrode308B is comprised of doped polycrystalline silicon or a silicide thereof. In another embodiment, gate electrode308B is comprised of a metal layer such as but not limited to metal nitrides, metal carbides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides, e.g. ruthenium oxide. In one embodiment, a chemical-mechanical process step is used subsequent to forming gate electrode308B in order to remove unwanted material from the surface of interlayer dielectric blocks320, as depicted inFIG. 3D. In accordance with an embodiment of the present invention, gate electrode308B overlaps the portion of substrate or epitaxial layer302that comprises ultra-shallow tip extensions310, as depicted inFIG. 3D.

Thus, referring toFIG. 3D, a planar MOS-FET300B comprising a gate electrode that overlaps ultra-shallow junctions may be formed by way of a replacement gate process. Planar MOS-FET300B may subsequently be incorporated into an integrated circuit by conventional process steps, as known in the art.

The present invention is not limited to the formation of a planar MOS-FETs comprising a gate electrode that overlaps ultra-shallow junctions. For example, devices with a three-dimensional architecture, such a independently accessed double gate devices, FIN-FETs, tri-gate devices and gate-all-around devices, may benefit from the above process. As an exemplary embodiment in accordance with the present invention,FIGS. 4A-Billustrate cross-sectional views representing the formation of an independently-accessed double gated MOS-FET with ultra-shallow junctions.

Referring toFIG. 4A, independently accessed double gate MOS-FET400A may be comprised of substrate or epitaxial layer402which includes channel regions404, gate dielectric layers406A, gate electrode placeholders408A, ultra-shallow tip extensions410, inner sets of gate isolation spacers414and outer sets of gate isolation spacers416. In accordance with an embodiment of the present invention, gate electrode placeholders408A overlap negligibly over ultra-shallow tip extensions410, as depicted inFIG. 4A.

Referring toFIG. 4B, the inner sets of gate isolation spacers414may be removed. Additionally, gate dielectric layers406A and gate electrode placeholders408A may be replaced with gate dielectric layers406B and gate electrodes408B, respectively. In accordance with an embodiment of the present invention, gate electrodes408B overlap the regions of substrate or epitaxial layer402that comprise ultra-shallow tip extensions410. Thus, the dimensions of gate electrode placeholders408A with a smaller than desirable gate length, coupled with removable inner sets of gate isolation spacers414, may be targeted for the fabrication of gate electrode408B with an expanded, and desired, gate length.

Thus, referring toFIG. 4B, an independently accessed double gate MOS-FET400B comprising gate electrodes that overlap ultra-shallow junctions may be formed by way of an expansion replacement gate process utilizing sacrificial gate isolation spacers. Independently accessed double gate MOS-FET400B may subsequently be incorporated into an integrated circuit by conventional process steps, as known in the art. As will be appreciated by one of ordinary skill in the art, other three-dimensional semiconductor devices may be formed in a similar manner. For example, in accordance with an embodiment of the present invention, a tri-gate device with a top gate above substrate402is formed by way of an expansion replacement gate process utilizing sacrificial gate isolation spacers. Other devices such as double-gated devices and FIN-FETs may also be formed.

As another exemplary embodiment in accordance with the present invention,FIGS. 5A-Billustrate cross-sectional views representing the formation of a gate-all-around MOS-FET with ultra-shallow junctions. Referring toFIG. 5A, gate-all-around MOS-FET500A may be comprised of a nanowire502, e.g. a silicon, germanium, silicon/germanium or III-V composite nanowire, a gate electrode placeholder508A, ultra-shallow tip extensions (not shown), an inner set of gate isolation spacers514and an outer set of gate isolation spacers516. In accordance with an embodiment of the present invention, gate electrode placeholder408A overlaps negligibly over the ultra-shallow tip extensions.

Referring toFIG. 5B, the inner set of gate isolation spacers514may be removed. Additionally, a gate dielectric layer (not shown) and gate electrode placeholder508A may be replaced with gate dielectric layer506B and gate electrode508B, respectively. In accordance with an embodiment of the present invention, gate electrode508B overlaps the regions of nanowire502that comprise ultra-shallow tip extensions (not shown). Thus, the dimensions of gate electrode placeholder508A with a smaller than desirable gate length, coupled with a removable inner set of gate isolation spacers514, may be targeted for the fabrication of gate electrode508B with an expanded, and desired, gate length.

Thus, referring toFIG. 5B, a gate-all-around MOS-FET500B comprising a gate electrode that overlaps ultra-shallow junctions may be formed by way of a replacement gate process. Gate-all-around MOS-FET500B may subsequently be incorporated into an integrated circuit by conventional process steps, as known in the art.

Therefore, a replacement gate process may be utilized to enable the overlap of a gate electrode over the regions of a semiconductor substrate where ultra-shallow junctions reside. In one embodiment, a sacrificial spacer may be utilized in conjunction with the replacement gate process. In another embodiment an initial gate electrode is formed with a gate length smaller than the desired final gate length and is subsequently replaced with an expanded gate electrode having the desired gate length.