Memory device with charge storage layers at the sidewalls of the gate and method for fabricating the same

A memory device is described, including a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an integrated circuit (IC) device and fabrication thereof, and more particularly relates to a memory device and a method for fabricating the same.

2. Description of Related Art

A memory is a semiconductor device for storing information or data. As the computer microprocessors become more and more powerful, programs and operations executed by the software are increased correspondingly. Consequentially, the demand for high storage capacity memories is getting more.

Among various types of memory products, a non-volatile memory allows multi-time data programming, reading and erasing operations, and the data stored therein can be retained even after the power to the memory is terminated. With these advantages, the non-volatile memory has become one of the most widely adopted memories for personal computers and electronic equipment.

Electrically programmable and erasable non-volatile memory technologies based on charge storage structures and known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in various modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Traditional flash memory cells store charges in a floating gate, but another type of flash memory uses a charge-trapping structure, such as a layer of non-conductive SiN material, instead of a floating gate including a conductive material. When a charge-trapping cell is programmed, charges are trapped and do not move through the non-conductive layer. The charges are retained by the charge trapping layer until the cell is erased, retaining the data state without continuously applied electrical power. Charge-trapping cells can be operated as two-sided cells. That is, because the charges do not move through the non-conductive charge trapping layer, the charges can be localized on different charge-trapping sites. On the other words, in the flash memory devices with the use of the charge-trapping structure, more than one bit of information is stored in each memory cell.

A single memory cell can be programmed to store two physically separated bits in the trapping structure, in the form of a concentration of charges near the source and another concentration of charges near the drain. Programming of the memory cell can be performed by Channel Hot Electron (CHE) injection, which generates hot electrons in the channel region. Some of the hot electrons gain enough energy to be trapped in the charge-trapping structure. By interchanging the biases applied to the source and drain terminals, charges are trapped either in a portion of the charge-trapping structure near the source region, near the drain region, or both.

Usually, one of four distinct combinations of bits 00, 01, 10 and 11 can be stored in a memory cell having a charge-trapping structure, wherein each combination has a corresponding threshold voltage (Vt). In a read operation, the current flowing through the memory cell varies depending upon the Vt of the cell. Typically, such current has one of four different values each corresponding to a different Vt. Accordingly, by sensing such current, the particular bit combination stored in the cell is determined.

The total available charge range or Vt range may be referred to as the memory operation window. In other words, the memory operation window is defined by the difference between the program level and the erase level. A large memory operation window is desired as good level separation between states is needed for cell operation. The performance of two-bit memory cells, however, is often degraded by the so-called “second bit effect” in which localized charges in the charge-trapping structure interact with each other. For example, during a reverse read operation, a read bias is applied to the drain terminal and the charge stored near the source region (i.e., a “first bit”) is sensed, then the bit near the drain region (i.e., the “second bit”), however, creates a potential barrier for reading the first bit near the source region. This barrier may be overcome by applying a bias with a suitable magnitude, using the drain-induced barrier lowering (DIBL) effect to suppress the effect of the second bit near the drain region and allow the sensing of the storage status of the first bit. However, when the second bit near the drain region is programmed to a high Vt state and the first bit near the source region is at un-programmed state, the second bit raises this barrier substantially. Thus, as the Vt associated with the second bit increases, the read bias for the first bit becomes insufficient to overcome the potential barrier created thereby, and the Vt associated with the first bit is raised as a result of the higher Vt of the second bit reducing the memory operation window. The second bit effect decreases the memory operation window for 2-bit/cell operation, so there is a need for methods and devices capable of suppressing the second bit effect in memory devices.

SUMMARY OF THE INVENTION

Accordingly, this invention provides a memory device that has a well confined charge storage region so that the charges stored are fully localized to reduce the second-bit effect, minimize program disturbance behaviors and reduce the short channel effect.

This invention also provides a method for fabricating a memory device, which utilizes few steps to allow the fabricated memory device to have a well confined charge storage region, so that the charges stored are fully localized to reduce the second-bit effect, minimize program disturbance behaviors and reduce the short channel effect.

In a first aspect of this invention, the memory device includes a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. Two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion.

In an embodiment, the body portions, the first extension portions and the second extension portions of the charge storage layer comprise the same material.

In an embodiment, the memory device further includes two doped regions in the substrate at both sides of the gate, wherein the first and the second extension portions of each charge storage layer are located over one of the doped regions.

In an embodiment, the memory device further includes two liner layers and two spacer layers. Each of the liner layers is between the gate and the second extension portion of one of the charge storage layers. The two spacer layers are disposed over the edges of the first extension portions of the charge storage layers, wherein the second extension portion of each charge storage layer is between one of the liner layers and one of the spacer layers.

In an embodiment, the ratio of the length of the body portion to that of the first extension portion ranges from 2:1 to 5:1.

In a second aspect of this invention, the memory device includes the above gate and gate dielectric, and two charge storage layers and two liner layers. Each charge storage layer includes a body portion in one of the gaps, and an extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate. The two liner layers are disposed on the sidewalls of the gate, wherein the edge of the extension portion of each charge storage layer protrudes out of the sidewall of one of the liner layers.

In an embodiment, the above memory device further includes two doped regions in the substrate at both sides of the gate, wherein the extension portion of each charge storage layer extends to over one of the doped regions.

In an embodiment, the ratio of the length of the body portion to that of the extension portion ranges from 2:1 to 5:1.

In a third aspect of this invention, the memory device includes the above gate, the above gate dielectric, two above charge storage layers each including a body portion and an extension portion, and two doped regions in the substrate at both sides of the gate. The extension portion of each charge storage layer extends to over one of the doped regions.

The method for fabricating a memory device is described as follows. A gate dielectric and a gate thereon are formed on a substrate, wherein two gaps are formed at both sides of the gate dielectric and between the gate and the substrate. Two charge storage layers are formed, each including a body portion in one of the gaps, and a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate. Two doped regions are formed in the substrate at both sides of the gate, wherein the first extension portion of each charge storage layer extends to over one of the doped regions.

In an embodiment, each charge storage layer further includes a second extension portion connected to the first extension portion and extending along the corresponding sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion.

In an embodiment, the above method further includes forming, before the charge storage layers are formed, a liner material layer covering a surface of the substrate, the sidewalls of the gate dielectric, and a bottom, the sidewalls and the upper surface of the gate, such that after the charge storage layers are formed, the edge of the first extension portion of each charge storage layer protrudes out of the liner material layer on the corresponding sidewall of the gate.

In an embodiment, forming the charge storage layers includes the steps below. A charge storage material layer is formed on the liner material layer, filling the gaps. A spacer material layer is formed covering the charge storage material layer. The spacer material layer, the charge storage material layer and the liner material layer are anisotropically etched to exposes surfaces of the gate and the substrate, wherein the remaining spacer material layer, the remaining charge storage material layer and the remaining liner material layer serve as spacer layers, the charge storage layers and liner layers, respectively.

In an embodiment, the first extension portion and the second extension portion of each charge storage layer are located over one of the doped regions.

In an embodiment, the method further includes forming liner layers on the sidewalls of the gate, wherein the first extension portion of each charge storage layer protrudes out of the sidewall of a liner layer.

Since the body portions of the two charge storage layers are separated from each other, the memory device of this invention has two well confined charge storage regions so that the charges stored are fully localized to reduce the second-bit effect, minimize the program disturbance behaviors and reduce the short channel effect. Such structure of the charge storage layers can be made by a simple process in the fabricating method of this invention.

DESCRIPTION OF EMBODIMENTS

The following embodiment is intended to further explain this invention, but is not intended to restrict the scope of this invention.

FIGS. 1-7illustrate, in a cross-sectional view, a method for fabricating a memory device according to an embodiment of this invention.

Referring toFIG. 1, a gate dielectric12is formed on a substrate10, and then a gate conductive layer14is formed on the gate dielectric12. The substrate10may include a semiconductor material, such as bulk silicon or silicon on insulator (SOI), or a semiconductor compound. The gate dielectric12may include silicon oxide or other suitable material, and may be formed by thermal oxidation, CVD or other suitable method. The gate conductive layer14may include doped poly-Si, and may be formed by depositing undoped poly-Si through CVD and ion-implanting the same, or by poly-Si CVD with in-situ doping.

Then, a patterned hard mask layer16and a patterned mask layer18are formed on the gate conductive layer14. The hard mask layer16may include an advanced patterning film (APF), and may be formed by CVD. The patterned mask layer18may included a photoresist material. The patterns of the mask layer18can be formed through exposure and development, and the patterns of the hard mask layer16can be transferred from the mask layer18.

Referring toFIG. 2, an etching process is performed, with the patterned mask layer18and the hard mask layer16as a mask and the substrate10as an etching end, to pattern the gate conductive layer14into a plurality of gates14aand successively pattern the gate dielectric12. The etching process may be an anisotropic etching process. The anisotropic etching process may be a plasma etching process. Then, the patterned mask layer18and the patterned hard mask layer16are removed.

Referring toFIG. 3, an isotropic etching process is performed to remove a portion of the gate dielectric12and produce an undercut under the gate14a, so that two recesses20are formed at both sides of the gate dielectric12under the gate14aas local storage spaces.

Referring toFIG. 4, a liner material layer22is formed covering the top surface, the sidewalls and the exposed bottoms of each gate14a, the sidewalls of the gate dielectric12, and the exposed surfaces of the substrate10. In an embodiment, the liner material layer22conformally covers the top surface, the sidewalls and the exposed bottoms of each gate14a, the sidewalls of the gate dielectric12, and the exposed surfaces of the substrate10. The liner material layer22fills in the recesses20shown inFIG. 3but does not fill up the same, so that two gaps20a(FIG. 4) remain in the recesses20. The liner material layer22may include silicon oxide, may be formed through thermal oxidation, ISSG (in-situ steam generation) oxidation, CVD, atomic layer deposition (ALD) or furnace oxidation.

Referring toFIG. 5, a charge storage material layer24′ is formed, covering the liner material layer22on the top surfaces and the sidewalls of each gate14aand on the substrate10, and filling the gaps20a. The charge storage material layer24′ may include silicon nitride (SiN) or doped poly-Si. SiN may be formed through furnace deposition, LPCVD or ALD. Doped poly-Si may be formed by poly-Si CVD with in-situ doping.

Then, a spacer material layer26is formed covering the charge storage material layer24′ on the top surfaces and the sidewalls of each gate14aand over the substrate10. In an embodiment, the spacer material layer26is conformal to the charge storage material layer24′ on the top surfaces and the sidewalls of each gate14aand over the substrate10. The spacer material layer26may include silicon oxide, may be formed through furnace oxidation, CVD or high-temperature thermal oxidation.

Referring toFIG. 6, the spacer material layer26, the charge storage material layer24and the liner material layer22are anisotropically etched such that the top surface of each gate14aand surfaces of the substrate10are exposed. The remaining charge storage material layer24′ serves as a plurality of charge storage layers24, each of which includes a body portion24ain one of the gaps20a, a first extension portion24bconnected with the body portion24aand protruding out of the corresponding sidewall of the gate14a, and a second extension portion24cdisposed on the sidewall of the gate14aand extending down to connect with the first extension portion24b, wherein the edge of the first extension portion24bprotrudes from the sidewall of the second extension portion24c.

The remaining liner material layer22includes three portions22a,22band22c. The first portion22aof the liner material layer22is between the substrate10and the charge storage layer24, serving as a tunneling dielectric layer. The second portion22bof the liner material layer22is between the gate14aand the body portion24aof the charge storage layer24, serving as a top dielectric layer. The third portion22cof the liner material layer22is on the sidewall of the gate14a, and is between the gate14aand the second extension portion24cof the charge storage layer24to serve as a liner layer. The remaining spacer material layer serves as spacer layers26a, each of which is located on the edge of the first extension portion24bof one of the charge storage layers24and on the sidewall of the corresponding second extension portion24c.

Thereafter, an ion-implantation process is performed to form doped regions28and30in the substrate10at both sides of the gate14a, wherein the first extension portions24band the second extension portions24cof the charge storage layers24are located over the doped regions28and30. The dopant implanted in the dope region28and the dopant implanted in the doped region30have the same conductivity type, which is different from the conductivity type of the substrate10. In an embodiment, the substrate10is P-doped and the doped regions28and30are N-doped. In another embodiment, the substrate10is N-doped and the doped regions28and30are P-doped. The N-type dopant may be phosphorus or arsenic. The P-type dopant may be boron or boron difluoride. The doped regions28and30can serve as a source region and a drain region of a memory cell.

Referring toFIG. 7, a dielectric layer32is formed over the substrate10, filling up the gaps between the gates14aand exposing the top surfaces of the gates14a. The dielectric layer32may include silicon oxide, and may be formed by depositing a dielectric material layer through CVD and then planarizing the same. The planarization process may include etching-back or CMP.

Then, a word line34is formed on the dielectric layer32and on the top surfaces of the gates14a. The word line34includes a conductive material, and is electrically connected with the gates14a. In an embodiment, the extension direction of the word line34is different from that of the doped regions28and30, and may be perpendicular to the latter. The word line34may be formed by depositing a conductive material layer and then patterning the same through lithography and etching. The conductive material may be doped poly-Si, metal, metal alloy, or a combination thereof. Doped poly-Si may be formed by poly-Si CVD with in-situ doping. The metal or metal alloy may be formed by sputtering or CVD, or other suitable method.

Referring toFIG. 7again, the memory device according to the above embodiment of this invention includes a gate14a, a gate dielectric12, two charge storage layers24, two doped regions28and30, and a word line34.

The gate14ais disposed on the substrate10. The gate dielectric12is between the gate14aand the substrate10. The width of the gate dielectric12is smaller than that of the gate14ain a symmetric manner, so that two gaps20aare present at both sides of the gate dielectric12and between the gate14aand the substrate10.

The material of the two charge storage layers24is different from that of the gate dielectric12. Each charge storage layer24includes a body portion24ain one of the gaps20a, a first extension portion24bconnected with the body portion24aand protruding out of the corresponding sidewall of the gate14a, and a second extension portion24cconnected with the first extension portion24band extending upward along the sidewall of the gate14a, wherein the edge of the first extension portion24bprotrudes from the sidewall of the second extension portion24c. Thus, each charge storage layer24has an inversed T-shape. When the length L1of the body portion24ais too short, the programming efficiency is limited. When the length L1of the body portion24ais larger, the programming speed is higher but the second-bit effect gets greater. When the length of the first extension portion24bis larger, the control thereof by the gate14ais weaker so that the second-bit effect is smaller, but the programming speed still can be improved. The length L1of the body portion24amay be 50-150 angstroms, and the length L2of the first extension portion24bmay be 10-75 angstroms. In an embodiment, the ratio of the length of the body portion24ato that of the first extension portion24branges from 2:1 to 5:1. The body portions24a, the first extension portions24band the second extension portions24cof the charge storage layers24may include the same material.

The tunneling dielectric layer22ais disposed between the charge storage layer24and the substrate10. The top dielectric layer22bis disposed under the gate14aand is between the gate14aand the body portion24aof the charge storage layer24. The liner layer22cis disposed on a sidewall of the gate14aand between the gate14aand the second extension portion24cof the charge storage layer24. The spacer layer26ais disposed on the edge of the first extension portion24bof the charge storage layer24and on the sidewall of the second extension portion24c. In an embodiment, the material of the tunneling dielectric layers22a, the top dielectric layers22b, the liner layers22cand the spacer layers26ais different from that of the charge storage layer24.

The doped regions28and30are located in the substrate10at both sides of the gate14a, wherein the first extension portions24band the second extension portions24cof the charge storage layers24are located over the doped regions28and30. The dopant implanted in the dope region28and the dopant implanted in the doped region30have the same conductivity type, which is different from the conductivity type of the substrate10.

FIG. 8shows the variations of the programming speed with the drain voltage (Vd) for three different memory devices according to the embodiments of this invention, wherein dVt means the Vt-increasing rate of the programmed bit.

Referring toFIG. 8, the curve100is the result of programming the memory device of the embodiment shown inFIG. 7that includes an inversed T-shaped charge storage layer24including the body portion24a, the first extension portion24band the second extension portion24c. The curve200is the result of programming the prior-art memory device shown inFIG. 9that includes a charge storage layer24including the body portion24aonly. The curve300is the result of programming the prior-art memory device shown inFIG. 10that includes an L-shaped charge storage layer24including the first extension portion24band the second extension portion24conly. It is clear fromFIG. 8that when the drain voltage for programming is the same, the memory with an inversed T-shaped charge storage layer (corresponding to curve100) has a higher Vt-increasing rate (dVt), i.e., a higher programming speed.

Since the body portions of the two charge storage layers are separated from each other, the memory device of this invention has two well confined charge storage regions so that the charges stored are fully localized to reduce the second-bit effect, minimize the program disturbance behaviors and reduce the short channel effect. Such structure of the charge storage layers can be made by a simple process in the fabricating method of this invention.

This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.