Overlay key, method of forming the overlay key and method of measuring overlay accuracy using the overlay key

In an overlay key used for measuring overlay accuracy between first and second layers on a substrate, a first mark may be formed in the first layer, and a second mark may be formed on the second layer. The first mark may include first patterns having a first pitch and extending in a first direction. The second mark may include second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch. First and second images may be acquired from the first and second marks. The overlay accuracy may be produced from position information of first and second interference fringes formed by overlaying a test image having a third pitch onto the first and second images.

PRIORITY STATEMENT

This application claims the benefit of priority under 35 USC §119 to Korean Patent Application No. 2005-92637 filed on Oct. 1, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Example embodiments relate to an overlay key used in a semiconductor manufacturing process. More particularly, example embodiments relate to an overlay key for measuring overlay accuracy between patterned layers stacked on a semiconductor substrate, method of forming the overlay key and method of measuring the overlay accuracy using the overlay key.

2. Description of the Related Art

Generally, a semiconductor device is manufactured by repeatedly forming patterned layers on a semiconductor substrate such as a silicon wafer, for example. The patterned layers may be formed by one or more layer formation processes including, but not limited to, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition, etc., and may be patterned by a photolithography process and/or an etching process, for example.

The overlay accuracy between the patterned layers may be measured using an overlay key formed in the patterned layers. In general, a conventional overlay key may include a lower overlay pattern formed in a lower layer and an upper overlay pattern formed on an upper layer. A conventional overlay key may have a box-in-box shape.

The overlay accuracy may be determined by measuring the alignment accuracy between the lower and upper overlay patterns, and an alignment correction value between a semiconductor substrate and a photo mask (or reticle) may be determined according to the overlay accuracy in a photolithography process.

As the packing density of semiconductor devices increase, the significance of measuring the overlay accuracy generally increases.

SUMMARY

Example embodiments provide an advanced form of an overlay key to improve measurement of overlay accuracy.

Example embodiments provide a method of forming an advanced overlay key.

Example embodiments also provide a method of measuring overlay accuracy using an overlay key.

In an example embodiment, an overlay key may be used for measuring overlay accuracy between a first layer and a second layer on a substrate. An example embodiment of an overlay key may include a first mark formed in the first layer and having first patterns with a first pitch extending in a first direction; and a second mark formed on the second layer adjacent to the first mark and having second patterns with a second pitch substantially equal to the first pitch and extending in a substantially same direction as the first direction.

In some example embodiments, the second mark may be disposed adjacent to the first mark in the first direction.

In some example embodiments, the second mark may be disposed adjacent to the first mark in a second direction substantially perpendicular to the first direction.

In some example embodiments, the first and second patterns may be arranged such that each of the first and second marks has a rectangular box shape. The first and second marks may be arranged such that a side portion of the first mark is adjacent to a side portion of the second mark.

In another example embodiment, an overlay key may be used for measuring overlay accuracy between a first layer and a second layer on a substrate. In addition, the overlay key may include a first mark having first patterns with a first pitch extending in a first direction; a second mark having second patterns formed in the first layer with a second pitch and extending in a second direction substantially perpendicular to the first direction; a third mark having third patterns formed on the second layer adjacent to the first mark, extending substantially the same direction as the first direction, and having a third pitch substantially equal to the first pitch; and a fourth mark formed on the second layer adjacent to the second mark and having fourth patterns with a fourth pitch substantially equal to the second pitch and extending in substantially the same direction the second direction.

In some example embodiments, the third mark may be adjacent to the first mark in the first direction and the fourth mark may be adjacent to the second mark in the first direction.

In some example embodiments, the fourth mark may be adjacent to the second mark in the second direction.

In some example embodiments, the third mark may be disposed adjacent to the first mark in the second direction.

In still another example embodiment, a first layer may be formed on a substrate and patterned to form a first mark having first patterns with a first pitch and extending in a first direction. A second layer may be formed on the patterned first layer, and a second mark may be formed on the second layer. The second mark may be adjacent to the first mark. Also, the second mark may have second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch.

In some example embodiments, the second mark may be adjacent to the first mark in the first direction.

In some example embodiments, the second mark may be adjacent to the first mark in a second direction substantially perpendicular to the first direction.

In some example embodiments, the first and second patterns may be arranged such that each of the first and second marks has a rectangular box shape. Also, the first and second marks may be arranged such that a side portion of the first mark is adjacent to a side portion of the second mark.

In still another example embodiment, a first layer may be formed on a substrate and patterned to form a first mark and a second mark. The first mark may include first patterns extending in a first direction and having a first pitch. The second mark may include second patterns extending in a second direction substantially perpendicular to the first direction and having a second pitch. A second layer may be formed on the patterned first layer. A third mark and a fourth mark may be formed on the second layer. The third mark may be adjacent to the first mark, and the fourth mark may be adjacent to the second mark. The third mark may include third patterns extending in a substantially same direction as the first direction and having a third pitch substantially equal to the first pitch. The fourth mark may include fourth patterns extending in substantially the same direction as the second direction and having a fourth pitch substantially equal to the second pitch.

In some example embodiments, the third mark may be adjacent to the first mark in the first direction, and the fourth mark may be adjacent to the second mark in the first direction.

In some example embodiments, the fourth mark may be disposed adjacent to the second mark in the second direction.

In some example embodiments, the third mark may be disposed adjacent to the first mark in the second direction.

In still another example embodiment, an overlay key may be used for measuring a first layer and a second layer on a substrate. The overlay key may include a first mark formed in the first layer and a second mark formed on the second layer adjacent to the first mark. The first mark may include first patterns extending in a first direction and having a first pitch; and the second mark may include second patterns extending in substantially the same direction as the first direction and having a second pitch substantially equal to the first pitch. A first image and a second image may be acquired from the first mark and the second mark, respectively. A test image may have a third pitch and may be overlaid onto the first and second images. The overlay accuracy between the first and second layers may be produced from position information of a first interference fringe formed by overlaying the test image onto the first image and a second interference fringe formed by overlaying the test image onto the second image.

In some example embodiments, the test image may include a line-and-space pattern extending in substantially the same direction as the first direction.

In some example embodiments, the third pitch may be different from the first pitch and a ratio of the third pitch to the first pitch may be within a range of about 0.5 to about 1.5.

In some example embodiments, the second mark may be disposed adjacent to the first mark in the first direction, and the overlay accuracy may be produced according to a phase difference between the first and second interference fringes.

In some example embodiments, the second mark may be adjacent to the first mark in a second direction substantially perpendicular to the first direction, and the overlay accuracy may be produced according to an angle between the first and second interference fringes.

In some example embodiments, the test image may include a line-and-space pattern extending in a second direction that is tilted with respect to the first direction.

According to the example embodiments, the overlay accuracy may be measured more easily and precisely using interference fringes formed by overlaying the test image onto the images obtained from the marks of the overlay key.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first thin film could be termed a second thin film, and, similarly, a second thin film could be termed a first thin film without departing from the teachings of the disclosure.

Hereinafter, example embodiments are explained in detail with reference to the accompanying drawings.

FIG. 1is a plan view illustrating an example embodiment of an overlay key, andFIGS. 2 and 3are cross-sectional views illustrating the overlay key shown inFIG. 1.

Referring toFIGS. 1 to 3, a semiconductor substrate10, for example, a silicon wafer may have a plurality of device forming regions, which may be divided by a plurality of scribe lanes12. The scribe lanes12may intersect at right angles. A first layer14and a second layer16may be arranged on the substrate10. An example embodiment of an overlay key100may be used for measuring overlay accuracy between a first circuit pattern (not shown) formed in the first layer14and a second circuit pattern (not shown) formed in the second layer16. The overlay key100may include a first mark110formed in the first layer14and a second mark120formed on the second layer16. The overlay key may be formed on the scribe lane12.

The first mark110may include first patterns112, which may be repeatedly formed in the first layer14and may have a first pitch P1. According to an example embodiment, the first mark110may have a line-and-space shape extending in a first direction. The first pitch P1may be within a range of about 200 nm to about 2 μm. For example, the first pitch P1may be about 1 μm.

The second layer16may be formed on the first layer14. The second mark120and a photoresist pattern (not shown) may be formed on the second layer16. The photoresist pattern may be used as an etching mask in a subsequent patterning process for forming the second circuit pattern.

The second mark120may be disposed adjacent to the first mark110and may include second patterns122that are repeatedly formed on the second layer16. Further, the second patterns122of the second mark120may have a second pitch P2substantially equal to the first pitch P1. The second mark120may have a line-and-space shape and may extend in a direction substantially the same as the first direction.

The first patterns112and the second patterns122may be arranged such that each of the first and second marks110and120has a rectangular box shape. Further, the first and second marks110and120may be arranged such that a side portion of the first mark110is disposed adjacent to a side portion of the second mark120. As shown in the example embodiment ofFIG. 1, the first mark110may be disposed adjacent to the second mark120in the first direction.

FIG. 4is a plan view illustrating another example embodiment of an overlay key, andFIGS. 5 and 6are cross-sectional views of the overlay key shown inFIG. 4.

Referring toFIGS. 4 to 6, a first layer24having a first circuit pattern (not shown) may be formed on a semiconductor substrate20, and a second layer26may be formed on the first layer24. A photoresist pattern (not shown) may be formed on the second layer26, which may be used for patterning the second layer26to form a second circuit pattern (not shown).

An overlay key200may be used for measuring overlay accuracy between the first and second circuit patterns. The overlay key200may include a first mark210formed in the first layer24and a second mark220formed on the second layer26. The first and second marks210and220may be formed on a scribe lane22of the substrate20.

The first mark210may include first patterns212that are repeatedly formed in a first direction in the first layer24. The first patterns212may have a first pitch P1. The first mark210may have a line-and-space shape extending in a second direction substantially perpendicular to the first direction. The first pitch P1may be within a range of about 200 nm to about 2 μm. For example, the first pitch P1may be about 1 μm.

The second mark220may be disposed adjacent to the first mark210and may include second patterns222that are repeatedly formed in the first direction. Further, the second mark220may have a second pitch P2substantially equal to the first pitch P1. The second mark220may have a line-and-space shape extending in the second direction.

The first patterns212and second patterns222may be arranged such that the first mark210and second mark220each have a rectangular box shape. The first mark210may be disposed adjacent to the second mark220in the first direction.

FIG. 7is a plan view illustrating still another example embodiment of an overlay key.

Referring toFIG. 7, a first layer having a first circuit pattern may be formed on a semiconductor substrate30, and a second layer to be patterned may be formed on the first layer. A photoresist pattern may be formed on the second layer, which may be used as etching mask during a patterning process of the second layer. An overlay key300may be formed on a scribe lane32of the substrate30. In addition, the overlay key300may include first and second marks310and320formed in the first layer, and third and fourth marks330and340formed on the second layer.

The first mark310may include first patterns312extending in a first direction and having a first pitch P1. The second mark320may include second patterns322extending in a second direction substantially perpendicular to the first direction and having a second pitch P2. The first pitch P1may be substantially equal to the second pitch P2. However, the first pitch P1may be different from the second pitch P2according to alternative example embodiments.

The third mark330may be formed on the second layer adjacent to the first mark310and may include third patterns332extending in substantially the same direction as the first direction. Further, the third mark330may have a third pitch P3substantially equal to the first pitch P1.

The fourth mark340may be formed on the second layer adjacent to the second mark320and may include fourth patterns342extending in substantially the same direction as the second direction. Further, the fourth patterns342of the fourth mark340may have a fourth pitch P4substantially equal to the second pitch P2.

As shown in figures, the third and fourth marks330and340may be disposed adjacent to the first and second marks310and320in the first direction.

However, the third mark330may be disposed adjacent to the first mark310and have third patterns332extending in the first direction, and the fourth mark340may be disposed adjacent to the second mark320and have fourth patterns342extending in the second direction. Further, the third mark330may be disposed adjacent to the fourth mark340in the second direction, and the fourth mark340may be disposed adjacent to the second mark320in the first direction.

Moreover, the marks may be disposed in different configurations, and examples of the configurations and relations of the marks are shown inFIGS. 8 and 9.

Referring toFIG. 8, a first mark410may be disposed on a first scribe lane extending in a first direction, and a second mark420may be disposed on a second scribe lane extending in a second direction substantially perpendicular to the first direction. The first mark410may extend in the first direction, and the second mark420may extend in the second direction.

A third mark430may be disposed adjacent to the first mark410in the first direction, and a fourth mark440may be disposed adjacent to the second mark420in the second direction. Further, the third mark430may extend in the first direction, and the fourth mark440may extend in the second direction.

Referring toFIG. 9, a first mark510may be disposed on a first scribe lane extending in a first direction, and a second mark520may be disposed on a second scribe lane extending in a second direction substantially perpendicular to the first direction. The first mark510may extend in the second direction, and the second mark520may extend in the first direction.

A third mark530may be disposed adjacent to the first mark510in the first direction, and a fourth mark540may be disposed adjacent to the second mark520in the second direction. Further, the third mark530may extend in the second direction, and the fourth mark540may extend in the first direction.

FIGS. 10 to 13are plan views and cross-sectional views illustrating a method of forming example embodiments of overlay keys such as the example embodiment of the overlay key shown inFIG. 7, for example.

Referring toFIGS. 10 and 11, a first layer34may be formed on a semiconductor substrate30. The first layer34may have a first circuit pattern (not shown) and first and second marks310and320. The first and second marks310and320may be used for measuring overlay accuracy. The first layer may include conductive material or insulating material and may be formed using one or more layer formation processes including, but not limited to, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, etc.

A mask pattern may be formed on the first layer34and then, the first circuit pattern, the first mark310and the second mark320may be formed by an anisotropic etching process using the mask pattern as an etching mask. The mask pattern may be a photoresist pattern. Alternatively, the mask pattern may be a nitride layer pattern formed using the photoresist pattern.

The first and second marks310and320may be formed on a scribe lane32of the substrate30. The first mark310may extend in a first direction and may include first patterns312having a line-and-space shape. The first patterns312of the first mark310may have a first pitch P1. The second mark320may extend in a second direction substantially perpendicular to the first direction. The second mark320may include second patterns having a line-and-space shape and a second pitch P2.

Referring toFIGS. 12 and 13, a second layer36may be formed on the first layer34. Then, a photoresist pattern (not shown) for patterning the second layer36, as well as third and fourth marks330and340for measuring the overlay accuracy may be formed on the second layer36. A second circuit pattern may be formed in the second layer36by patterning the second layer36. The first, second, third and fourth marks310,320,330and340may be used for measuring the overlay accuracy between the first and second circuit patterns before forming the second circuit pattern.

The third and fourth marks330and340may include photoresist and may be disposed adjacent to the first and second marks310and320, respectively.

The third mark330may include third patterns332extending in substantially the same direction as the first direction and having a third pitch P3substantially equal to the first pitch P1. The fourth mark340may include fourth patterns extending in substantially the same direction as the second direction and having a fourth pitch P4substantially equal to the second pitch P2.

The second layer36may include conductive material or insulating material and may be formed by a layer formation process well known to those skilled in the art. The photoresist pattern, the third mark330and the fourth mark340may be formed by a photolithography process well known to those skilled in the art.

FIG. 14is a flow chart illustrating a method of measuring overlay accuracy using an example embodiment of an overlay key such as the overlay key shown inFIG. 1, for example.FIG. 15is a schematic view illustrating a test image, and example first and second images acquired from first and second marks110and120shown inFIG. 1.FIG. 16is a schematic view illustrating example first and second interference fringes formed by overlaying the test image onto the first and second images as shown inFIG. 15.

Referring toFIGS. 1 and 14to16, a first image610and a second image620may be acquired from the first and second marks110and120formed on the substrate10(S100). The first and second images610and620may be acquired by an optical microscope, for example.

The first mark110may include first patterns112extending in a first direction and having a line-and-space shape and a first pitch P1. The second mark120may include second patterns122extending in substantially the same direction as the first direction and having a line-and-space shape and a second pitch P2substantially equal to the first pitch P1.

A test image630may be overlaid onto the first and second images610and620(S110). The test image may include an image corresponding to a line-and-space pattern extending in substantially the same direction as the first direction and having a fifth pitch P33different from the first pitch P1. Particularly, a ratio of the fifth pitch P33to the first pitch P1may be within a range of about 0.5 to about 1.5. For example, if the first pitch is about 1 μm, the fifth pitch P33is within a range of about 0.5 μm to about 1.5 μm. According to another example embodiment, if the first pitch P1is about 1 μm, the fifth pitch P33may be set within a range of about 0.8 μm to about 1.2 μm.

According to an example embodiment, a first interference fringe640may be formed by overlaying the test image630onto the first image610and a second interference fringe650may be formed by overlaying the test image630onto the second image620(S110). The first and second interference fringes640and650may be formed according to a difference between the first pitch P1and fifth pitch P33. The overlay accuracy may be produced from position information of the first and second interference fringes640and650(S120).

Each of the first and second interference fringes640and650may have a regularly repeated pattern. However, the second interference fringe650may shift in a second direction substantially perpendicular to the first direction with respect to the first interference fringe640in accordance with the overlay accuracy between the first and second marks110and120. That is, the overlay accuracy may be produced from a phase difference between the first and second interference fringes640and650.

If the second mark120shifts by the first pitch P1from the first mark110in the second direction, the phase difference does not occur between the first and second interference fringes640and650. Thus, a measurement range of the overlay accuracy using the first and second interference fringes640and650may be smaller than the first pitch P1.

Thus, the overlay accuracy measurement using the phase difference between the first and second interference fringes640and650may be desirably performed after an overlay accuracy measurement using the first and second images610and620is performed according to an example embodiment. In detail, the overlay accuracy may be produced more precisely by first measuring misalignment between the first and second marks110and120using the first and second images610and620, and second producing misalignment between the first and second marks110and120using the first and second interference fringes640and650.

FIG. 17is a schematic view illustrating another example of first and second interference fringes formed by overlaying the test image onto the example first and second images shown inFIG. 15.

Referring toFIG. 17, a test image630a is tilted at approximately 2° with respect to the extension direction (e.g., the first direction) of the first image610. The overlay accuracy in the second direction may be produced from the phase difference between first and second interference fringes640aand650aformed by overlaying the tilted test image630aonto the first and second images610and620according to an example embodiment.

In an example embodiment using a tilted test image630a, the tilted test image630amay have a fifth pitch P33substantially equal to the first pitch P1. Further, the tilt angle of the tilted test image630amay be suitably determined to improve a reliability of the overlay accuracy measurement.

FIG. 18is a schematic view illustrating variation of interference fringes according to rotation of a second mark of the example embodiment of the overlay key shown inFIG. 1.

As shown inFIG. 18, if the second mark120is rotated by approximately 1° with respect to the first mark110, the overlay accuracy may be readily produced using the first interference fringe640and a second interference fringe650bthat is formed by overlaying the test image630onto the first image610and the rotated image620a. In detail, the overlay accuracy may be produced from an angle between extension directions of the first and second interference fringes640and650b.

FIG. 19is a schematic view illustrating first and second interference fringes formed by overlaying a test image onto first and second images acquired from example first and second marks shown inFIG. 3.

Referring toFIG. 19, a first image710acquired from the first mark210shown inFIG. 3may extend in a second direction and have a first pitch P1. A second image720acquired from the second mark220shown inFIG. 3may extend in substantially the same direction as the second direction and may have a second, pitch P2substantially equal to the first pitch P1. The first image710may be disposed adjacent to the second image720in a first direction substantially perpendicular to the second direction.

A test image may extend in the second direction and may have a fifth pitch P33different from the first pitch P1. In an example embodiment of overlaying the test image730onto the first and second images710and720, misalignment between the first and second images710and720may be produced from variation of a period between first and second interference fringes740and750.

FIG. 20is a schematic view illustrating another example embodiment of first and second interference fringes formed by overlaying a test image onto first and second images acquired from example first and second marks shown inFIG. 3.

Referring toFIG. 20, a test image730amay be tilted by approximately50with respect to the extension direction (e.g., the second direction) of the first image710. The overlay accuracy in the first direction substantially perpendicular to the second direction may be produced from the phase difference between the first and second interference fringes740aand750aformed by overlaying the tilted test image730aonto the first and second images710and720. In detail, the phase difference may be varied in accordance with a distance between the first and second images710and720. Thus, the overlay accuracy in the first direction may be easily produced according to the phase difference. In example embodiments, the tilted test image730amay have a pitch substantially equal to that of the first or second image.

FIG. 21is a schematic view illustrating variation of interference fringes according to rotation of a second mark of the example embodiment of the overlay key shown inFIG. 3.

As shown inFIG. 21, if the second mark220is rotated by approximately10with respect to the first mark210, the overlay accuracy may be produced from first and second interference fringes740and750bformed by overlaying the test image730onto the first image710and the rotated second image720a.

Further detailed descriptions on methods of measuring overlay accuracy using the overlay keys as shown inFIGS. 7 to 9will be omitted because these methods are similar to those already described with reference toFIGS. 15 to 21.

In accordance with the example embodiments, the overlay accuracy may be measured more precisely and easily using the interference fringes formed by overlaying the test image onto the images acquired from the marks of the overlay key.

Although example embodiments have been described above, it is understood that the present invention should not be limited to these example embodiments but various changes and modifications can be made by those skilled in the art within the spirit and scope of the present invention as hereinafter claimed.