Method and apparatus for source-synchronous capture using a first-in-first-out unit

A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.

FIELD OF THE INVENTION

Embodiments of the present invention relate to hardware for supporting source synchronous standards. More specifically, embodiments of the present invention relate to a method and apparatus for strobe-based source-synchronous capture using a first-in-first-out (FIFO) buffer.

BACKGROUND OF THE INVENTION

Source synchronous communication standards are important to enable high-speed data transfer between devices. Board skews and delay variation make it challenging to complete a synchronous transfer with a single central board clock or even a single clock forwarded with a large number of data bits. Consequently, what is typically done is a large data bus is divided into small groups of bits and a clock or strobe associated with each group of bits is forwarded along with the respective data. An assumption is made that any board skew or delay variation will affect both the clock or strobe and data bits in each group such that the clock or strobe can be reliably used to capture the respective data.

One issue with this approach is that data synchronized to various different clocks or strobes must often be synchronized to a single clock in the receiving device to facilitate data processing on all the data received. There are a few known approaches that have been used to achieve this in programmable-logic devices (PLDs), or, more specifically, field-programmable gate arrays (FPGAs).

Run-time controllable delay chains may be used on the input data paths to delay the data as necessary so it can be successfully captured by a single clock in the receiving device. To achieve this, it is important to determine the phase relationship between the incoming data and the clock in the receiving device. This can be done on a group basis (data bits and associated clock/strobe) by sampling different delayed versions of the clock/strobe with the clock in the receiving device. Using that information, the data can be appropriately delayed to facilitate reliable capture. The disadvantage of this approach is the complexity associated with the hardware needed to support dynamic delay calibration to adjust delays for process/voltage/temperature variations. There can be additional complexity in the controller logic to keep the data capture reliable and ensure all the data is aligned.

In another approach, the clock within the receiving device can be adjusted so that the data can be reliably transferred directly from the clock/strobe domains to the receiving device clock domain. This approach may be combined with circuitry (in the IO periphery of FPGAs) that capture the data using the strobe and de-serialize it so that the data is still synchronous to the strobe, but it toggles at a more manageable frequency (which is desirable for FPGAs that have slower core logic speeds than comparable ASICs). That lower-frequency data is then re-synchronized to a receiving device clock domain. A disadvantage with this approach is that it can be difficult if not impossible to determine a single clock phase within the receiving device that will suit all the clock/strobe domains at high speeds.

SUMMARY

According to an embodiment of the present invention, a FIFO unit is used to perform re-synchronization of data from a non-free-running strobe domain or a memory device clock domain to a receiving device clock domain to complete a source synchronous transfer. The FIFO unit includes a write clock port and a read clock port which can be connected to (phase) independent clocks. Data may be written into the write side of the FIFO, and data may be read out on the read side of the FIFO in the same order which the data was written. The FIFO unit performs resynchronization without requiring components such as specially-calibrated data-path delay elements, hardware which supports dynamic delay calibration of those delay elements, state machines which keep data aligned, and clock-phase re-calibration circuitry. This approach also avoids the timing marginality associated with transferring data directly and synchronously from multiple domains to a single clock domain that may be difficult to determine. The FIFO units handle these transfers asynchronously, and independently, so no timing window interactions need to be considered.

According to an embodiment of the present invention, re-synchronization of data from a free running clock may also be performed by a source synchronous capture unit. The source synchronous capture unit utilizes a first FIFO unit to synchronize a write enable signal from the receiving device clock domain to the transmitting device clock domain to generate a synchronized write enable signal. The write enable signal may be generated in response to a read operation by the receiving circuit. The source synchronous capture unit also utilizes a second FIFO unit such as the FIFO unit described above. Data is written into the second FIFO unit in response to the synchronized write enable signal. By writing data into the second FIFO unit in response to the synchronized write enable signal, invalid data is prevented from being written into the second FIFO unit.

DETAILED DESCRIPTION

In the following description, for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that specific details in the description may not be required to practice the embodiments of the present invention. In other instances, well-known circuits, devices, and components are shown in block diagram form to avoid obscuring embodiments of the present invention unnecessarily.

FIG. 1is a block diagram of a source synchronous capture unit100according to an exemplary embodiment of the invention. The source synchronous capture unit100may be used at a receiving device to capture source synchronous data from a transmitting device and to synchronize the data to a receiving device clock. The source synchronous capture unit100can support source-synchronous communication standards, such as double-data-rate (DDR), that do not send a free-running clock along with the data. A non-free running clock, such as a strobe, may be transmitted with the data that toggles when the data is being sent. The source synchronous capture unit100may include a cleaning unit110, when non-free running clocks are being processed. The cleaning unit110adjusts the non-free running clock so that it may be used directly for capturing data. According to an embodiment of the present invention, the cleaning unit110may be removed or bypassed when the system uses a free-running clock. The cleaning unit110may gate the non-free running clock with logic that performs an AND function and a control (enable) signal that is timed to be high when the non-free running clock is active. It should be appreciated that other techniques, such as electrical methods based on level detection of the non-free running clock to interpret an intermediate voltage level as high or low, may be used to clean up the non-free running clock.

The source synchronous capture unit100includes a shifting unit120. The shifting unit120shifts the clock or strobe to facilitate data capture so that the edges of the clock or strobe are centered in the data valid window, in one embodiment. According to one embodiment, a delay lock loop may be used to calibrate a delay chain to shift the clock or strobe. It is appreciated that other techniques may be used to shift the clock or strobe.

FIG. 2is a timing diagram illustrating how a strobe signal is adjusted by a source synchronous capture unit according to an embodiment of the present invention. Signal210is a strobe signal which is used for a non-free running clock. Signal220is a data signal. In some strobe-based applications, the strobe may go tri-state when data is not being read or written. In those cases, it is difficult to make use of the strobe directly for capturing data. Signal230is a clean strobe signal. The clean strobe signal230represents the strobe signal210after being adjusted by a cleaning unit. Signal240is a shifted clean strobe signal. The shifted clean strobe signal240represents the clean strobe signal230after being adjusted by a shifting unit. As shown inFIG. 2, data from the data signal220may be captured by every edge of the shifted clean strobe signal240after being processed by the cleaning unit and shifting unit120of a source synchronous capture unit. After the data capture, the data can be de-serialized such that two bits become available at a negative clock edge, for example.

Referring back toFIG. 1, the source synchronous capture unit100includes a data register unit130. The data register unit130is coupled to a first line that carries data and a second line that carries a non-free running clock (that may be cleaned by the cleaning unit110and shifted by the shifting unit120). The data register unit130registers data clocked in by the clock or strobe. Registering incoming source synchronous data is important because transfers from an input/output (IO) pin to a core of the receiving device may introduce additional skew between the non-free running clock and the data that may cause capture failures of the data in the core, using the clock or strobe. Registering (or re-registering) the data in the FPGA IO periphery reduces data timing drift relative to the clock or strobe that may have happened outside of the FPGA. As such, the data transfer from the FPGA IO periphery into the FPGA core has more margin after the registering. Another advantage of the registering is that de-serialization can be easily done at the same time.

The source synchronous capture unit100includes a delay unit140. The delay unit140is coupled to the shifting unit120and receives the clock or strobe. The delay unit140adds clock skew to delay the clock or strobe signal. The delay unit140may be implemented using hardware components dedicated to producing a delay. Alternatively, the delay unit140may be implemented using programmable routing. The delay unit140allows data to be written into a FIFO using the same clock edge that is used to capture the data by the data register unit130. This is important since a non-free running clock, such as a strobe, may not be a continuous clock. For example, consider a receiving device that performs a double-data rate capture and de-serialization into a single-data rate, all synchronized to a non-free running clock, such as a strobe. If 4 bits of data are being received, there will only be 4 edges of the strobe (rising then falling then rising then falling). Two bits of data are made available at the data register unit130every negative edge of the strobe. After the second negative edge of the strobe, the last two bits of data are still at the data register unit130and only the first two bits of data have been written into the FIFO unit. When the strobe stops, the last two bits of data will be “stranded” at the data register unit130. The delay unit140allows the source synchronous capture unit100to prevent stranding bits of data at the data register unit130by having data written into the FIFO unit use the same clock edge that is used to capture the data at the data register unit130. All the data gets written into the FIFO unit when the non-free running clock stops toggling.

According to an embodiment of the source synchronous capture unit100, the data has “Delay” worth of time to travel from the data register unit130to the FIFO. If “Delay” equals a period of the clock or strobe, the data has one period to travel. If “Delay” is larger, the data has even more time. In order to prevent data corruption at the FIFO, there is a minimum data travel time of “Delay” minus the clock or strobe period.

The source synchronous capture unit100includes a FIFO unit150. The FIFO unit150may include the features described above. The FIFO unit150writes (stores) data received from the data register unit in response to the clock or strobe and reads (outputs) the data stored in the FIFO unit150in response to a free running clock on the receiving device. The FIFO unit150may be implemented by one or more FIFOs. According to an embodiment of the present invention, the FIFO unit150may be an asynchronous FIFO unit that includes one or more asynchronous FIFOs.

FIG. 3illustrates a source synchronous capture unit300implementing a single FIFO according to an embodiment of the present invention. The components illustrated inFIG. 3may be used to implement portions of the source synchronous capture unit100illustrated inFIG. 1. The source synchronous capture unit300includes a data register unit310. The data register unit310includes a plurality of registers311-313that are coupled to a first line301that carries data and a second line302that carries a clock or strobe. According to one embodiment, the second line302carries a strobe that has been cleaned and shifted. The data register unit310captures data received from the first line301and is synchronized to the clock or strobe on the second line302.

The source synchronous capture unit300includes a delay unit320. The delay unit320is coupled to the second line302that carries the clock or strobe. The delay unit320adds a delay to the clock or strobe that is transmitted to a FIFO unit350in the source synchronous capture unit300. The delay added to the clock or strobe allows data to be written to the FIFO unit350using the same clock edge that is used to capture the data by the register unit310.

The source synchronous capture unit300includes the FIFO unit350. The FIFO unit350implements a single FIFO351according to an exemplary embodiment of the present invention. The FIFO351has a read side and a write side. The write side of the FIFO351receives the clock or strobe from the delay unit320and writes data into the FIFO351from the data register unit310in response to the clock or strobe. The read side of the FIFO351is coupled to a third line303that carries a clock associated with the receiving device and reads data out from the FIFO351in response to the clock associated with the receiving device. It should be noted that in some embodiments the FIFO is implemented out of programmable core logic. This permits a variety of FIFO implementations and avoids permanent area penalty associated with dedicated FIFOs. According to an embodiment of the present invention, the FIFO unit350may be an asynchronous FIFO unit that implements a single asynchronous FIFO351.

FIG. 4illustrates a source synchronous capture unit400implementing two FIFOs according to an exemplary embodiment of the present invention. The components illustrated inFIG. 4may be used to implement portions of the source synchronous capture unit100illustrated inFIG. 1. The source synchronous capture unit400includes a data register unit410similar to data register unit310shown inFIG. 3. The data register unit410includes a plurality of registers411-413that are coupled to a first line401that carries data and a second line402that carries a clock or strobe. According to one embodiment, the second line402carries a strobe that has been cleaned and shifted. The data register unit410captures data received from the first line401and is synchronized to the clock or strobe on the second line402.

The source synchronous capture unit400includes a delay unit420similar to the delay unit320shown inFIG. 3. The delay unit420is coupled to the second line402that carries the clock or strobe. The delay unit420adds a delay to the clock or strobe that is transmitted to an FIFO unit450in the source synchronous capture unit400. The delay added to the clock or strobe allows data to be written to the FIFO unit450using the same clock edge that is used to capture the data by the register unit410.

The source synchronous capture unit400includes a divider unit430. The divider unit430receives the clock or strobe from the delay unit420and divides the clock or strobe. The divider unit430is implemented by a register431and an inverter432.

The source synchronous capture unit400includes the FIFO unit450. The FIFO unit450implements two FIFOs451and452according to an exemplary embodiment of the present invention. The FIFO451operates off the negative edge of the clock or strobe and FIFO452operates off the positive edge of the clock or strobe. This allows the FIFOs451and452to operate at a lower frequency than the data hits are being captured at by the data register unit410.

The speed at which logic can run in a programmable logic device may limit the maximum speed the FIFOs can operate at. The configuration of the source synchronous capture unit400allows data to be written into the FIFOs451and452at half the rate of the clock or strobe. Data is written into alternating FIFOs, every falling edge of the clock or strobe. In some embodiments, the FIFO speed need only be a quarter of the incoming data rate (the data is de-serialized in the register unit and again when being written to the FIFOs).

The FIFOs451and452each have a read side and a write side. The write side of the FIFOs451and452receive the clock or strobe from the delay unit420and write data into the FIFOs451and452from the data register unit410in response to the clock or strobe. The read side of the FIFOs451and452are fed by a clock in the receiving device, and read data out from the FIFOs451and452in response to the receiving-device clock.

The source synchronous capture unit400may optionally include a multiplexer440. The multiplexer440may be used to select one of either the clock or strobe signal from line402or a divided clock or strobe from the divider unit430. In a situation where the clock or strobe rate is supported by the speed at which logic can run in a programmable logic device, the clock or strobe signal from line402may be directly selected by the multiplexer440and only 1 FIFO can be used as illustrated inFIG. 3. This avoids introducing additional logic when it is unneeded. According to an embodiment of the present invention, the FIFO unit450may be an asynchronous FIFO unit implementing two asynchronous FIFOs451and452.

FIG. 5illustrates the components in a FIFO500according to an exemplary embodiment of the present invention. The FIFO500may be used to implement any one of the FIFOs shown inFIGS. 3 and 4. The FIFO500receives data (labeled “Write Data”) from a first line501, a clock or strobe signal (labeled “Write Clock”) from a second line502, and a receiving device clock (labeled “Read Clock”) from a third line503.

The FIFO500includes a write counter510. The write counter510receives the clock or strobe and increments its counter value with every rising or falling edge from the clock or strobe. According to an embodiment of the FIFO500, the write counter510is a Gray counter.

The FIFO500includes a data steering unit520. The data steering unit520is coupled to the first line501and receives data. The data steering unit520is coupled to the write counter510and receives counter values. The data steering unit520steers the data received to the appropriate element (storage locations) in a data storage buffer in response to the counter values.

The FIFO500includes a data storage buffer530. The data storage buffer530includes a plurality of elements. The data storage buffer530is coupled to the clock or strobe and clocks data from the data steering unit510in response to the clock or strobe.

The FIFO500includes a read counter540. The read counter540is coupled to the third line503and receives the receiving device clock. The read counter540increments its counter value in response to the receiving device clock signal and a read enable signal that indicates that data had previously been read out successfully. According to an embodiment of the FIFO500, the read counter540is a Gray counter.

The FIFO500includes a data selecting unit550. The data selecting unit550is coupled to the read counter540and receives counter values. The data selecting unit550selects which element (storage location) in the data storage buffer to select to read from in response to the counter values.

The FIFO500includes a data resynchronization stage560. The data resynchronization stage560resynchronizes data from the domain of the clock or strobe (the “Write Clock” domain) into the domain of the receiving device clock (the “Read Clock” domain) so that the receiving device domain (“Read Clock” domain) can present the data synchronized to the receiving device clock.

The FIFO500includes a write counter resynchronization unit570. The write counter resynchronization unit570is coupled to the third line503and receives the receiving device clock. The write counter resynchronization unit570resynchronizes the write counter state into the receiving device domain (the “Read Clock” domain). To implement the data resynchronization stage560and the write counter resynchronization unit570, cascades of registers for each bit being re-synchronized may be used. For example, some embodiments may use two registers in series for each bit being re-synchronized. The first register captures the data into the “new” clock domain, if the data changes at a clock edge, the register may go meta-stable for a short while. The purpose of the second register is to pass only the final decision of that first register once it has stabilized, and filter out the instability. The second register can be the output of the resynchronization unit. It will have stable data synchronized to the “new” clock domain.

The FIFO500includes a data availability unit580. The data availability unit580compares the re-synchronized write counter values with the read counter values to determine whether data is available for reading from the data storage buffer530. If data is available for reading, the data available unit580generates an indication that the data from the data resynchronization stage560is valid.

According to an embodiment of the present invention, the FIFO500is implemented such that the last data written to the FIFO500can be read even if the non-free running clock (Write Clock) stops. That is, the FIFO500should not have any write latency. This is important to avoid “stranding” data when the non-free running clock stops. The depth of the data storage buffer530can be sized so that there is reduced chance of overflow (based on the application and the environment the FIFO500is run in). If it is assumed that data will be read from the FIFO500as soon as all the elements in the FIFO500have the relevant data, the depth will mainly be a function of the maximum inter-strobe skews. As long as the FIFO500is sized appropriately, there is no need for an overflow or full signal. Consequently, the only ports the FIFO500needs is a write data port (for receiving data), write clock (for the clock or strobe), read data port, read clock (for the receiving device clock), and a data available flag.

There is an important timing consideration for the FIFO500. The timing of various paths must be met in order to ensure that the read data is valid when an indication is generated by the data available unit580that the read data is valid. For example, when the FIFO500transitions from being empty to having some data, the valid data needs to be available at the output of the data resynchronization stage unit560when the write counter resynchronization unit570presents the up-to-date write counter state to the data available unit580. According to an embodiment of the present invention, this may be achieved by delaying the path from the write counter510to the write counter resynchronization unit570. According to an alternate embodiment of the present invention, the delay from the data storage buffer530to the data resynchronization stage unit560may be reduced. According to another embodiment of the present invention, the skew on the clock or strobe may be adjusted to delay the update of the write counter510relative to when data is written into the data storage buffer530. It is appreciated that the FIFO500may be implemented as an asynchronous FIFO.

Referring back toFIG. 1, according to an alternate embodiment of the present invention, when receiving a free-running clock with data, shifting unit120and delay unit140may shift and add clock skew to free running clock signals similar to the shift and add clock skew to non-free running clock signals as described with respect to the earlier described embodiment above. In these embodiments, cleaning unit110is typically not required to adjust the clock signal because the free-running clock does not go to tri-state. Furthermore, FIFO unit150operates to write (store) data received in response to a first free running clock corresponding to the transmitting device and a write enable signal that is synchronized. The FIFO unit150also operates to output the data stored in response to a second free running clock corresponding to the receiving device.

FIG. 6illustrates a source synchronous capture unit600operable to synchronize data transmitted with a free running clock according to an exemplary embodiment of the present invention. The source synchronous capture unit600receives data that is synchronized with a first free running clock associated with a transmitting device. The source synchronous capture unit600synchronizes the data with a second free running clock that is associated with a receiving device. The components illustrated inFIG. 6may be used to implement portions of the source synchronous capture unit100illustrated inFIG. 1.

The source synchronous capture unit600includes a data register unit610. The data register unit610includes a plurality of registers611-613that are coupled to a first line601that carries data and a second line602that carries a free running clock signal from the first free running clock. According to an embodiment of the present invention, the registers may be implemented using flip-flops. The data and the free running clock signal may originate from a transmitting device residing external to a receiving device which the source synchronous capture unit resides on. According to one embodiment, the second line602carries a first free running clock signal that has been shifted. The data register unit610captures data received from the first line601and is synchronized to the first free running clock on the second line602.

The source synchronous capture unit600includes a delay unit620. The delay unit620is coupled to the second line602that carries the first free running clock. The delay unit620adds a delay to the first free running clock that is transmitted to a FIFO unit650in the source synchronous capture unit600. The delay added to the first free running clock allows data to be written to the FIFO unit650using the same clock edge that is used to capture the data by the register unit610.

The FIFO unit650includes a first FIFO652. The first FIFO652may be referred to as an “enable FIFO”. The first FIFO652has a read side and a write side. The write side of the first FIFO652is coupled to a third line603that carries a second free running clock signal from a second free running clock associated with the receiving device. The write side of the first FIFO652writes write enable signals into the FIFO652transmitted by the receiving device in response to the second free running clock signal. According to an embodiment of the present invention, the write enable signals from the receiving device are generated in response to a read operation. The read side of the first FIFO652receives the first free running clock signal from the delay unit620and reads out a synchronized write enable signal in response to the first free running clock signal.

The FIFO unit650includes a second FIFO651. The second FIFO651may be referred to as a “data FIFO”. The second FIFO651has a read side and a write side. The write side of the second FIFO651receives a first free running clock signal from the delay unit620and writes data into the second FIFO651from the data register unit610in response to the first free running clock and a synchronized write enable signal from the first FIFO652. The read side of the second FIFO651is coupled to the third line603that carries the second free running clock associated with the receiving device. Data is read out from the second FIFO651in response to the second free running clock associated with the receiving device. According to an embodiment of the present invention, the FIFO unit650may be an asynchronous FIFO unit that implements asynchronous FIFOs651and652.

By writing data into the second FIFO651in response to the synchronized write enable signal from the first FIFO652, the source synchronous capture unit600will write valid data into the second FIFO651. This approach differs from prior art approaches which would write data into a data FIFO every cycle of a free running clock, regardless of whether the data was valid or not.

FIG. 7illustrates components in FIFOs of a source synchronous capture unit operable to synchronize data originating from a domain utilizing a free running clock according to an exemplary embodiment of the present invention. The components illustrated inFIG. 7may be used to implement the first FIFO652and the second FIFO651inFIG. 6. A first plurality of components is used to implement a first FIFO (enable FIFO)710for synchronizing a write enable signal received from a receiving device clock domain to a transmitting device clock domain. According to an embodiment of the present invention, the write enable signal is generated in response to a read operation by the receiving device. A plurality of registers and an adder are used to implement a write counter711for the first FIFO710. The write counter711receives a second free running clock signal from the receiving device clock domain and increments a counter value with every rising or falling edge of the second free running clock signal.

A register bank712for the first FIFO710is coupled to the write counter711and receives a write address at its select input from the write counter711. The write address selects an appropriate location in the register bank712to store write enable signals generated by the receiving device.

A plurality of registers and an adder are used to implement a read counter713for the first FIFO710. The read counter713receives a first free running clock signal from the transmitting device clock domain and increments a counter value with every rising or falling edge of the first free running clock signal.

A selector714for the first FIFO710is coupled to the read counter713and receives a read address at its select input from the read counter713. The read address selects an appropriate output received from the register bank712to transmit. The output of the selector714is a synchronized write enable signal that is synchronized to the clock domain of the transmitting device.

A second plurality of components is used to implement a second FIFO (data FIFO)720for synchronizing data received from the transmitting device clock domain to the receiving device clock domain. A plurality of registers and an adder are used to implement a write counter721for the second FIFO720. The write counter721receives a first free running clock signal from the transmitting device clock domain and increments a counter value in response to the first free running clock signal and the synchronized write enable signal output from the selector714.

A register bank722for the second FIFO720is coupled to the write counter721and receives a write address at its select input from the write counter721. The write address selects an appropriate location in the register bank722to store data received from the transmitting device. By generating a write address in response to the synchronized write enable signal, data is written into the register bank722when valid data is returned from the transmitting device.

A plurality of registers and an adder are used to implement a read counter723for the second FIFO720. The read counter723receives the second free running clock signal from the receiving device clock domain and increments a counter value in response to the second free running clock signal and a read enable signal from the receiving device.

A selector724for the second FIFO720is coupled to the read counter723and receives a read address at its select input from the read counter723. The read address selects an appropriate output received from the register bank722to transmit. The output of the selector724is a synchronized data that is synchronized to the clock domain of the receiving device.

According to an embodiment of the present invention, the latency of the first FIFO710may be adjusted to ensure that write enable signals emerge in a corresponding cycle of the first free running clock to enable the second FIFO to latch the appropriate data. This may be achieved by using the +1 or +2 input and write address increment signals inputted to the write counter711. When data is written into the second FIFO (data FIFO)720, it is read out in response to a read enable signal. According to an embodiment of the present invention, the timing of the read enable signal is also calibrated to minimize latency while providing sufficient guardband to prevent under run if data arrives late. According to an embodiment of the present invention, the calibration procedure described in U.S. patent application Ser. No. 13/151,245 entitled “Method and Apparatus for Supporting Low-Latency External Memory Interfaces for Integrated Circuits” filed on Jun. 1, 2011, (which claims priority to provisional application 61/396,717 filed on Jun. 2, 2010) which is incorporated by reference, may be used to calibrate first FIFO710. If the minimum latency the calibration procedure finds is larger than the latency required to have the write enable signal emerge in the corresponding cycle of the first free-running clock, some embodiments may make adjustments to command-path latencies to compensate, while others will issue an error.

It is appreciated that minor modifications may be made to the configuration of components illustrated inFIGS. 6 and 7to support a source synchronous capture unit that synchronizes data originating from a domain utilizing a non-free running clock.

FIG. 8illustrates components in a FIFO of a source synchronous capture unit operable to synchronize data originating from a domain utilizing a non-free running clock according to an exemplary embodiment of the present invention. Transmitting devices utilizing non-free running clocks, such as strobe-reliant memory interfaces like DDR, toggles strobes when data is sent. Since the strobes are toggled when data is valid, synchronized write enable signals need not be generated. Thus, the components supporting the first FIFO710inFIG. 7may be removed and the enable input on write counter721may be tied to true. Gating circuitry810may be implemented to gate raw non-free running clock signals in the event a signal goes tri state, in response to a core-synchronized DQS enable signal. Write counter721, register bank722, read counter723, and selector724inFIG. 8operate similarly to their corresponding components inFIG. 7.

According to an embodiment of the present invention, the source synchronous capture unit is operable to interface with devices that transmit data with either a free running clock signal or a non-free running clock signal with minor modifications to its operability. Due to the flexibility of the design of the source synchronous capture units illustrated inFIGS. 6,7, and8, the modifications may be made during design of the source synchronous capture unit or during operation of the source synchronous capture unit. To modify the operability of the source synchronous capture unit during operation, both the data FIFO and enable FIFO may be implemented on a circuit and the user is given an option to select whether to use the enable FIFO to synchronize a write enable signal.

According to an embodiment of the present invention, a calibration technique may be used to determine when the read enable signals illustrated inFIGS. 7 and 8are generated to achieve consistent and reliable data transfer with low latency. This is different than the synchronization-based approach described with respect toFIG. 5. Calibration based data FIFOs are advantageous when synchronization latency is large. Calibration-based data FIFOs that are far from a central controller/scheduler may be fed by pipelined read enable signals whose latency is adjusted based on calibration results to avoid broadcast latency penalties between the controller/scheduler and the FIFOs. According to an embodiment of the present invention, synchronizer chains are used to assist FIFO calibration. When data is written into the FIFO, a signal can be sent to the read side through a synchronizer, similar toFIG. 5. Once the signal is synchronized, the read side can use that information to calibrate when it is safe to read out of the FIFO. The appropriate guardband/latency can be added and/or latency through the synchronizer can be factored out.

It is appreciated that synchronization-based approach described with respect toFIG. 5may be used in place of calibration. For example, a write counter resynchronization unit such as the one described with reference toFIG. 5may be used instead of performing calibration to avoid FIFO under-run and minimize latency.

Data FIFOs may be used to perform rate conversion in addition to synchronization. For example, data written into a data FIFO may have a different width and rate than the data read from the data FIFO. According to an embodiment of the present invention, 32 bits of data may be written into a data FIFO every clock cycle of a transmitting device, and 64 bits of data may be read out of the data FIFO every clock cycle of the receiving device. In order to achieve this, the write address would be 1 bit longer than the read address. Furthermore, the selector used for selecting data from the register bank of the data FIFO would be structured to read out wider words than the write address selects. Similarly, two write enable bits may be written into the enable FIFO every clock cycle of the receiving device while one write enable bit may be read out of enable FIFO every clock cycle of the transmitting device.

It is appreciated that embodiments of the source synchronous capture units illustrated inFIGS. 6-8may be modified to increase the transmitting-device clock rate supported. This may be achieved by dividing each respective FIFO into two FIFOs that latch data off different edges (rising and falling, similar to that illustrated inFIG. 4) of a half-rate clock created by dividing the strobe or clock coming from the transmitting device. Data is read out of the two FIFOs using a half-rate clock from the receiving device. As a result, the maximum clock rate on the write side of the data FIFO is reduced. This technique may be applied to the write side of the data FIFO and the read side of the enable FIFO to reduce how fast those FIFO ports need to operate.

FIG. 9illustrates a target device900in which the source synchronous capture unit may be implemented on according to an exemplary embodiment of the present invention. The target device900is an FPGA having a chip with a hierarchical structure that may take advantage of wiring locality properties of circuits formed therein.

The target device900includes a plurality of logic-array blocks (LABs). Each LAB may be formed from a plurality of logic blocks, carry chains, LAB control signals, (lookup table) LUT chain, and register chain connection lines. A logic block is a small unit of logic providing efficient implementation of user logic functions. A logic block includes one or more combinational cells and registers. According to one embodiment of the present invention, the logic block may operate similarly to a logic element (LE), or adaptive logic module (ALM), such as those found in Stratix II/III/IV devices manufactured by Altera® Corporation, or a slice such as those found in Virtex devices manufactured by Xilinx Inc. In this embodiment, the logic block may include a four input lookup table (LUT) with a configurable register. Columns of LABs are shown as911-916. It should be appreciated that the logic block may include additional or alternate components.

The target device900includes memory blocks. The memory blocks may be, for example, dual port random access memory (RAM) blocks that provide dedicated true dual-port, simple dual-port, or single port memory up to various bits wide at up to various frequencies. The memory blocks may be grouped into columns across the target device in between selected LABs or located individually or in pairs within the target device900. Columns of memory blocks are shown as921-924.

The target device900includes digital signal processing (DSP) blocks. The DSP blocks may be used to implement multipliers of various configurations with add or subtract features. The DSP blocks include shift registers, multipliers, adders, and accumulators. The DSP blocks may be grouped into columns across the target device900and are shown as931.

The target device900includes a plurality of input/output elements (IOEs)940. Each IOE feeds an I/O pin (not shown) on the target device900. The IOEs may be located at the end of LAB rows and columns around the periphery of the target device900. Each IOE includes a bidirectional I/O buffer and a plurality of registers for registering input, output, and output-enable signals.

The target device900includes LAB local interconnect lines (not shown) that transfer signals between LEs in the same LAB. The LAB local interconnect lines are driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, memory blocks, or DSP blocks may also drive the LAB local interconnect lines through direct link connections. The target device900also includes a plurality of row and column interconnect lines (not shown) that span fixed distances. Dedicated row and column interconnect lines, route signals to and from LABs, DSP blocks, and memory blocks within the same row and column, respectively.

With respect to the components illustrated inFIGS. 3,4, and6, the data register unit and delay/divider unit may be implemented at the input/output periphery (the IOEs inFIG. 9) and the FIFO(s) may be implemented at the core of an FPGA (using the non-10E blocks inFIG. 9). It should be appreciated that the data register unit, the delay/divider unit, and the FIFOs may be implemented at other locations on the FPGA. For example, in some embodiments, the delay/divider unit may be implemented in the core of the FPGA.

FIG. 9illustrates an exemplary embodiment of a target device. It should be appreciated that a system may include a plurality of target devices, such as that illustrated inFIG. 9, cascaded together. It should also be appreciated that the target device may include FPGA resources arranged in a manner different than that on the target device900. A target device may also include FPGA resources other than those described in reference to the target device900. Thus, while the invention described herein may be utilized on the architecture described inFIG. 9, it should be appreciated that it may also be utilized on different architectures.