Ground fault circuit interrupter with enhanced radio frequency interference suppression

A ground fault circuit interrupter device having a feedthrough capacitor for substantially reducing interference from radio frequency signals such as those emitted from cell phones and 2-way radios. The ground fault circuit interrupter device includes a printed circuit board having a system ground terminal and a detection terminal for receiving a fault detection signal. A chip is provided having a ground pin connected to the system ground terminal and an input pin for receiving the fault detection signal. The feedthrough capacitor has a through conductor connected between the input pin and the detection terminal and a capacitor coupled between the through conductor and the system ground terminal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to ground fault circuit interrupters (GFCI's) and more specifically to a GFCI having reduced sensitivity to interference caused by radio frequency signals.

2. Description of the Related Art

Present day GFCI circuits include by-pass capacitors, inductive chokes, and noise filters on signal lines and sensitive parts of the circuitry to the direct current (DC) Ground terminal to suppress interference caused by radio frequencies. While the components that are currently being used are adequate for radio frequency signals used in the past, they are not fully effective for signals in the spectrum of radio frequencies which are now being used. For example, cell phones use signals having frequencies which can interfere with the operation of a GFCI by not only causing nuisance tripping of the GFCI, but can also cause a GFCI to fail by subjecting one or more of the components in the GFCI to excessive stress. What is needed is GFCI circuitry for reducing interference caused by radio frequencies.

SUMMARY OF THE INVENTION

The present invention solves the above noted problems by providing a GFCI device with a feedthrough capacitor to substantially suppress interference caused by radio frequency signals such as those generated by cell phones.

In one embodiment of the invention, the GFCI device includes a printed circuit board having a system ground terminal and a detection terminal for receiving a fault detection signal. A chip is provided having a ground pin connected to the system ground terminal and an input pin for receiving the fault detection signal. A feedthrough capacitor is provided having a through conductor connected between the input pin and the detection terminal and a capacitor coupled between the through conductor and the system ground terminal. The feedthrough capacitor substantially reduces interference from radio frequency signals such as those emitted from cell phones.

In other embodiments, a feedthrough capacitor can be connected to other locations of the circuitry of GFCI device to further reduce interference from radio frequency signals. For example, the through conductor of the feedthrough capacitor can be connected to the input or output of a chip having ground fault interrupting functions, the gate terminal of a semiconductor switch, the power supply terminal of the printed circuit board holding the circuitry.

The present invention provides one or more of the following advantages. The arrangement of the feedthrough capacitor reduces unwanted radio frequency signals by shunting or filtering the signals with respect to the system ground terminal GND thereby reducing interference from such signals. As a result, nuisance tripping of the GFCI may be reduced. In addition, the components of the GFCI may be subjected to less stress which would have been caused from such signals thereby improving the performance of the GFCI.

DETAILED DESCRIPTION OF THE INVENTION

The present invention discloses GFCI circuitry having a feedthrough capacitor connected in close proximately to the circuitry at sensitive locations for substantially reducing interference from radio frequency signals such as those emitted from cell phones.

Referring toFIG. 1, there is shown a schematic wiring diagram of GFCI circuitry100for detecting a predetermined fault condition such as a ground fault and disconnecting the input terminals from the output terminals in response thereto. The circuitry100has a feedthrough capacitor C11for substantially reducing interference from radio frequency signals such as those emitted from cell phones. The circuitry100includes a printed circuit board (not shown) with a direct current (DC) system ground terminal (GND) and a detection terminal (+VE) for receiving a fault detection signal from a differential transformer XF1. The system ground terminal GND is connected to the ground pin4of a chip IC-1that performs fault detection functions. The feedthrough capacitor C11has a through conductor connected between the input pin3of IC-1and the detection terminal +VE and has a capacitor coupled between the through conductor and the system ground terminal GND. The input pin3is internally coupled to the non-inverting input of an operational amplifier (not shown) within IC-1which is typically configured for handling a ground fault condition.

In one embodiment, the capacitor C11has attenuation characteristics that increase at 20 dB per decade from its cutoff frequency to at least that frequency where it exhibits a minimum attenuation of 60 dB and maintains this attenuation at higher frequencies. The cutoff frequency of the feedthrough capacitor can be selected from a band of frequencies in the 1 to 300,000 megahertz band of the radio spectrum. There are presently two frequency bands for cellular service centered on approximately 850 and 1850 MHz. The cutoff frequency of the feedthrough capacitor also can be selected from a range of frequencies in the 850 megahertz band, 1850 megahertz band or other bands for cell phone service. The frequency characteristics of the feedthrough capacitor C11along with the proximate placement of the capacitor to the circuitry at sensitive locations help reduce interference from radio frequency signals such as those emitted from cell phones.

The GFCI circuitry100includes a sensing circuit for detecting a predetermined condition such as a ground fault. The sensing circuit comprises a differential transformer XF1and a ground/neutral (G/N) transformer XF2each of which can comprise a magnetic core having a coil winding with two ends. The differential transformer XF1is used for detecting a current imbalance on the line terminals102,104. The G/N transformer XF2is used for detecting a remote ground voltage that may be present on one of the load terminals106,108. The first end of the differential transformer XF1is connected to the input pin2of IC-1through series resistor R3and the second end of the transformer XF1is connected to input pin3of IC-1through the through conductor of the feedthrough capacitor C11. Filter capacitor C8is placed in series with the second end of transformer XF1and the capacitor C11for filtering unwanted signals. Filter capacitor C7is placed across pin2of IC-1and the first conductor of feedthrough capacitor C11to filter unwanted signals. Filter capacitor C6is placed across the through conductor of capacitor C11and the system ground terminal GND for reducing unwanted signals. A zener diode Z1is placed across the transformer XF1to limit any potential overvoltage surges across the transformer XF1. It should be noted that input pin2is internally connected to the inverting input of an operational amplifier (not shown) in IC-1and input pin3is internally connected to the non-inverting input of the operational amplifier. The first end of the transformer XF2is connected to the output pin5of IC-1and the second end of the transformer XF2is connected to the system ground terminal GND through a filter capacitor C3for filtering unwanted signals. It should be noted that pin5is the output from the internal sense amplifier (not shown) of IC-1. A filter capacitor C9is placed across the first and second ends of the transformer XF2for reducing unwanted signals.

Chip IC-1can be one of the integrated circuits typically used in ground fault circuits, for example LM-1851, manufactured by National Semiconductor or other well known semiconductor manufacturers. IC-1has an output pin1connected to the gate terminal of a semiconductor switch device SC1for trigging the switch in response to a fault detection signal received by IC-1. A filter capacitor C2is connected across pin1of IC-1and the system ground terminal GND for reducing unwanted signals. A filter capacitor C4is connected across the power supply terminal VCC and the system ground terminal GND for reducing unwanted signals. A timing capacitor C5is connected across pin7of IC-1and the system ground terminal GND for setting the timing of IC-1. Resistor R2is connected across pins6and8of IC-1for setting the sensitivity of IC-1. The cathode of diode D1is connected to the power supply terminal VCC and the anode of the diode is connected to the anode of switch SC1through resistor R1. Diode D1performs a rectification function providing the power supply voltage at the VCC terminal for powering IC-1and the other components. Diode D1also helps prevent capacitor C10from “bleeding” when switch device SC1is turned on (when capacitor C10discharges, chip IC-1would not operate properly). The cathode terminal of the switch SC1is connected to the system ground terminal GND and the anode terminal is connected to the DC side of a full wave bridge comprising diodes D2-D5. A filter capacitor C10is connected across the anode and cathode terminals of switch SC1for reducing unwanted signals. Although the switch SC1is shown as a silicon controlled rectifier (SCR) other semiconductor or mechanical switches can be used.

Chip IC-1is configured for detecting a current from the transformers in response to a ground fault and generating a signal causing a relay assembly to connect/disconnect power received at the input line terminals (102,104) from any loads connected to the device via the output load terminals (106,108). The relay assembly comprises a coil112and relay contacts110, shown as a pair of switches SW2, SW3, to connect the line terminals102,104to respective load terminals106,108. The line terminals102,104and load terminals106,108are electrically isolated from each other unless connected by the switches SW2, SW3. A switch assembly comprising a switch SW1in series with current limiting resistor R4is coupled between line terminal102and one end of the relay coil112(through jumper J1being connected and providing an electrical path) for manually generating a fault condition. A surge suppressor MV1is coupled across the AC portion of the full wave bridge comprising diodes D2-D5for absorbing extreme electrical energy levels that may be present at the line terminals102,104. A filter capacitor C1is coupled across the surge suppressor MV1for filtering out unwanted signals.

The circuitry100includes test points and jumpers for various purposes such as testing the functionality of the circuitry. For example, test points TP1-TP9are terminals which facilitate testing the circuitry of the GFCI100by providing a means for taking measurements, such as voltage levels, using test equipment such as a voltage meter. Jumper elements or connectors are employed for providing a means of selecting certain features of the GFCI100. For example, jumper element JP1(for connection across terminals JP1A, JP1B) can be used to connect/disconnect an electrical path between the surge suppressor MV1and the line terminal102. Likewise, jumper element JP2(for connection across terminals JP2A, JP2B) and header terminal J1can be used to connect/disconnect an electrical path between relay coil112and the line terminal102. Although not shown, for proper operation, a connector is placed across the terminal J1for providing a complete electrical path between the line terminal102and the relay coil112.

Further suppression of interference signals can be obtained by placing the first through conductor of the feedthrough capacitor C11in close proximity to the input or output of an operational amplifier (not shown) which can be in chip IC-1, the gate terminal of semiconductor switch SC1, and the power supply terminal VCC on the printed circuit board. The layout and location of components on the printed circuit board is also important in reducing interference. The system ground terminal GND should have a large conductor width and include a ground loop. The distance between critical components should be kept to a minimum. In addition, filter capacitors should be positioned as close as possible to the circuitry100.

In operation, with regard to unwanted radio frequency signals, the feedthough capacitor C11shunts or filters the signals with respect to the system ground terminal GND thereby reducing interference from such signals. As a result, nuisance tripping of the GFCI is reduced. In addition, the components of the GFCI are subjected to less stress which would have been caused from such signals thereby improving the performance of the GFCI.

During a ground fault condition, a current provided by the differential transformer XF1, chip IC-1generates a voltage on pin1which triggers the gate terminal of switch SC1. The full wave bridge comprising diodes D2-D5has a DC side which is connected to the anode of SC1. SC1is turned on, allowing current to flow through the DC side of the full wave bridge activating relay coil112causing the relay switches SW2, SW3to open thereby removing power from the load terminals106,108. The relay coil112can also be activated when mechanical switch SW1is closed which causes a current imbalance on the line terminal conductors that is detected by the differential transformer XF1. The G/N transformer XF2detects a remote ground voltage that may be present on one of the load terminals and provides a signal (current or voltage) to IC-1upon detection of this remote ground which again activates relay coil112. Thus, the sensing circuit engages a circuit interrupting portion of the GFCI device causing the device to be tripped. In the tripped condition the line terminals and the load terminals are electrically isolated from each other.

Referring toFIG. 2, there is shown a feedthrough capacitor C11connected to another embodiment of a GFCI circuit200. The placement of the feedthrough capacitor C11in GFCI circuit200is similar to the placement of the feedthrough capacitor C11in GFCI circuit100ofFIG. 1. Like GFCI100, the input of the GFCI200is connected to line terminals (phase terminal202and neutral terminal204) and load terminals (phase terminal210and neutral terminal212). However, GFCI200is also connected to face terminals (phase terminal206and neutral terminal208). In one embodiment, the GFCI is part of a wiring device such as a receptacle and the line terminals are connected to a cable providing a source of power, the load terminals are connected to another power cable which in turn is connected to a load, and the face terminals are provided on the face of the receptacle for receiving a plug with a cable as part of a load. In addition, to accommodate the face terminals, GFCI200has a relay coil216coupled to relay contacts214comprising a movable bridge assembly with face switches and load switches. The face switches SW2, SW3are connected between the line terminals202,204and the face terminals206,208. The load switches SW4, SW5are connected between the line terminals202,204and the load terminals210,212.

The operation of the GFCI circuit200is similar to the operation of the GFCI circuit100ofFIG. 1. For example, in response to a current or potential provided by the differential transformer XF1, chip IC-1generates a voltage on pin1turning on SC1and activating relay coil216. The activation of relay coil216causes the relay face switches SW2, SW3to remove power from the face terminals206,208and the relay load switches SW4, SW5to remove power from the load terminals210,212. Likewise, the G/N transformer XF2detects a fault condition and provides a current to IC-1which activates relay coil216causing the movable bridge assembly214to remove power from the face terminals and the load terminals as described above. Test points TP1-TP10and jumper elements JP1-JP4provide various functions such as a means for testing the circuitry of the GFCI200.

It should be noted that although the present invention is described in the context of a GFCI, the techniques of the present invention are equally applicable to other circuit interrupting devices and systems such as arc fault circuit interrupters (AFCI's), immersion detection circuit interrupters (IDCI's), appliance leakage circuit interrupters (ALCI's) and equipment leakage circuit interrupters (ELCI's). Exemplary values for the components of GFCI100and200of the present invention include: Resistors R1(15K, 2 W), R2-R3(⅛W), R4(15K), capacitors C1(0.01 uF, 400V), C2-C3(0.01 uF, 50V), C4(1 uF, 50V), C5(0.018 uF, 100V, 10%), C6(100 pF, 50V), C7(0.0033 uF, 50V), C8(10 uF, 5.3V), C9(100 pF, 50V), C10(680 pF, 1000V), zener diode Z1(4.7V) and surge suppressor MV1is a metal oxide varistor (MOV) rated at 210V.

While there have been shown and described and pointed out the fundamental novel features of the invention as applied to the preferred embodiments, it will be understood that various omissions and substitutions and changes of the form and details of the method and apparatus illustrated and in the operation may be done by those skilled in the art, without departing from the spirit of the invention.