Data storage device for performing decoding operation and operating method thereof

A data storage device includes a nonvolatile memory device configured to store a codeword; and a controller configured to read the codeword from the nonvolatile memory device, and perform a decoding process for the codeword, wherein, when performing the decoding process, the controller calculates a flag of the codeword, calculates an expected number of errors by applying an adjustment coefficient to the flag, compares the expected number of errors to an allowed number of errors, and skips or performs a decoding operation for the codeword depending on a comparison result.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2017-0105006, filed on Aug. 18, 2017, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments of the present disclosure generally relate to a data storage device. Particularly, the embodiments relate to a data storage device including a nonvolatile memory device.

2. Related Art

Memory systems store data provided by an external device in response to a write request. Memory systems may also provide stored data to an external device in response to a read request. Examples of external devices that use memory systems include computers, digital cameras, cellular phones, and the like. Memory systems may be embedded in an external device during manufacturing of the external devices or may be fabricated separately and then connected afterwards to an external device.

SUMMARY

Various embodiments are directed to a data storage device capable of quickly performing a booting operation, and an operating method thereof.

In an embodiment, a data storage device may include: a nonvolatile memory device configured to store a codeword; and a controller configured to read the codeword from the nonvolatile memory device, and perform a decoding process for the codeword, wherein, when performing the decoding process, the controller calculates a flag of the codeword, calculates an expected number of errors by applying an adjustment coefficient to the flag, compares the expected number of errors to an allowed number of errors, and skips or performs a decoding operation for the codeword depending on a comparison result.

In an embodiment, a method for operating a data storage device may include: reading a codeword from a nonvolatile memory device; and performing a decoding process for the codeword, the performing of the decoding process including calculating a flag of the codeword; calculating an expected number of errors by applying an adjustment coefficient to the flag; comparing the expected number of errors to an allowed number of errors; and skipping or performing a decoding operation for the codeword depending on a comparison result.

In an embodiment, a memory system may include: a memory device configured to store a plurality of codewords composed of same data used to boot the memory system; and a controller configured to selectively perform a decoding operation for one of the codewords based on an expected number of errors and an allowed number of errors of the respective codewords during booting the memory system.

The data storage device and the operating method thereof according to the embodiments may quickly complete a booting operation.

DETAILED DESCRIPTION

Hereinafter, a memory system and an operating method thereof according to the present invention will be described with reference to the accompanying drawings through exemplary embodiments of the present invention. The present invention may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to describe the present invention in detail to the extent that a person skilled in the art to which the invention pertains can enforce the technical concepts of the present invention.

It is to be understood that embodiments of the present invention are not limited to the particulars shown in the drawings, that the drawings are not necessarily to scale, and, in some instances, proportions may have been exaggerated in order to more clearly depict certain features of the invention. While particular terminology is used, it is to be appreciated that the terminology used is for describing particular embodiments only and is not intended to limit the scope of the present invention.

The phrase “at least one of . . . and . . . ,” when used herein with a list of items, means a single item from the list or any combination of items in the list. For example, “at least one of A, B, and C” means, only A, or only B, or only C, or any combination of A, B, and C.

The term “or” as used herein means either one of two or more alternatives but not both nor any combinations thereof.

It is also noted, that in some instances, as would be apparent to those skilled in the relevant art, an element also referred to as a feature described in connection with one embodiment may be used singly or in combination with other elements of another embodiment, unless specifically indicated otherwise.

FIG. 1is a block diagram illustrating a data storage device10in accordance with an embodiment of the present disclosure.

The data storage device10may store data provided from an external device in response to a write request from the external device. Also, the data storage device10may provide the stored data to the external device in response to a read request from the external device.

The data storage device10may be configured by a Personal Computer Memory Card International Association (PCMCIA) card, a Compact Flash (CF) card, a smart media card, a memory stick, various multimedia cards (MMC, eMMC, RS-MMC, and MMC-Micro), various secure digital cards (SD, Mini-SD, and Micro-SD), a Universal Flash Storage (UFS), a Solid State Drive (SSD), and the like.

The data storage device10may include a controller100and a nonvolatile memory device200.

The controller100may control general operations of the data storage device10. The controller100may store data in the nonvolatile memory device200in response to a write request transmitted from the external device, and may read data stored in the nonvolatile memory device200and output the read data to the external device in response to a read request transmitted from the external device.

The controller100may include a booting section110and a decoder120.

The booting section110may read codewords CW1to CW3, which are composed of the same data, from the nonvolatile memory device200, and may perform a booting operation by using a codeword for which a decoding operation has succeeded, among the codewords CW1to CW3. That is, a single codeword may be stored in the nonvolatile memory device200as a plurality of copies, i.e., the codewords CW1to CW3, in case of a corruption. After being powered on, the booting section110may simultaneously read the codewords CW1to CW3, and may sequentially input the codewords CW1to CW3to the decoder120. According to an embodiment, the booting section110may input a subsequent codeword to the decoder according to a predetermined sequence120when the decoding operation for a previous codeword fails.

The decoder120may perform the decoding process for each of the codewords CW1to CW3to correct the errors included in the codewords CW1to CW3. The codewords CW1to CW3may sequentially undergo the decoding process according to a predetermined decoding sequence. The decoding process may be performed until the decoding operation succeeds for any one among the codewords CW1to CW3. When the decoding operation succeeds for any one of the codewords CW1to CW3, the decoding process may not be performed for the remaining codewords.

Meanwhile, the decoding sequence of the codewords CW1to CW3may be determined irrespective of the error states of the codewords CW1to CW3. In this case, if a codeword of a preceding decoding order includes too many errors, a booting operation may not be quickly performed. This is because the decoding process for a codeword having a relatively low probability of correcting due to a high percentage of errors included therein may require a long decoding time, which may exceed a predefined allowed time for each controller. Therefore, as will be described later, the decoder120according to the embodiment may selectively terminate quickly the decoding process for a previous codeword where too many errors are expected, and may proceed to the decoding process for a subsequent codeword. Thus, because the decoder120does not perform an unnecessary decoding operation for a codeword having a low probability of succeeding in decoding, the data storage device10may complete booting within an allowed time range.

The decoding process performed for any one codeword, for example, the codeword CW1, may be described in detail as follows. First, the decoder120may calculate the flag of the codeword CW1, calculate an expected number of errors by applying an adjustment coefficient to the flag, and compare the expected number of errors with an allowed number of errors. The decoder120may calculate the row syndromes of the row codewords of the codeword CW1, calculate the column syndromes of the column codewords of the codeword CW1, and calculate as the flag the product of the sum of the row syndromes and the sum of the column syndromes. The expected number of errors may be obtained by predicting the number of errors included in the codeword CW1. The expected number of errors may be calculated as the product of the flag and the adjustment coefficient. The adjustment coefficient may be determined experimentally as will be described later, and may be used in converting the flag of the codeword CW1into the number of errors included in the corresponding codeword CW1.

The decoder120may skip or perform the decoding operation for the codeword CW1depending on a result of comparing the expected number of errors and the allowed number of errors. In detail, when the expected number of errors exceeds the allowed number of errors, the decoder120may skip the decoding operation for the codeword CW1and output a decoding failure signal and terminate the decoding process.

However, when the expected number of errors is less than the allowed number of errors, the decoder120may perform the decoding operation for the codeword CW1.

The decoder120may repeat the decoding operation for the codeword CW1. The codeword CW1may be corrected while repeatedly undergoing the decoding operation. In order for quick termination of the decoding process, according to an embodiment, the decoder120may repeat the decoding operation for the codeword CW1up to an allowed repetition count. In other words, when a repetition count of the decoding operation exceeds the allowed repetition count although the decoding operation for the codeword CW1has not succeeded yet, the decoder120may stop the decoding operation and output a decoding failure signal and terminate the decoding process. However, when a repetition count of the decoding operation is less than the allowed repetition count and the decoding operation for the codeword CW1has not succeeded yet, the decoder120may repeat the decoding operation for the codeword CW1.

Also, in order for a quick termination of the decoding process, according to an embodiment, the decoder120may determine whether to continue or stop the decoding operation according to the method described above even while performing the decoding operation for the codeword CW1. In detail, the decoder120may calculate a second flag corrected from the codeword CW1while performing the decoding operation for the codeword CW1, calculate a second expected number of errors by applying the adjustment coefficient to the second flag, and compare the second expected number of errors with the allowed number of errors. When the second expected number of errors is less than the allowed number of errors, the decoder120may subsequently perform the decoding operation for a second codeword. However, when the second expected number of errors exceeds the allowed number of errors, the decoder120may stop the decoding operation for the second codeword, output a decoding failure signal and terminate the decoding process. Such an operation may be to prepare for a case where the number of errors rather increases in a subsequent codeword due to the decoding operation for previous codewords, thereby increasing a time required for the decoding process on the subsequent codeword.

The nonvolatile memory device200may store the data transmitted from the controller100, read stored data, and transmit the read data to the controller100according to the control of the controller100.

The nonvolatile memory device200may store the codewords CW1to CW3which are composed of the same data, read the codewords CW1to CW3, and transmit the read codewords CW1to CW3to the controller100according to the control of the controller100. Each of the codewords CW1to CW3may be encoded based on the turbo product code (TPC) algorithm and be then stored in the nonvolatile memory device200. WhileFIG. 1illustrates that three copies of a codeword are stored, the present disclosure is not limited thereto. That is, any suitable number of copies of a codeword may be stored.

The nonvolatile memory device200may include a flash memory, such as a NAND flash or a NOR flash, a Ferroelectrics Random Access Memory (FeRAM), a Phase-Change Random Access Memory (PCRAM), a Magneto-resistive Random Access Memory (MRAM), a Resistive Random Access Memory (ReRAM), and the like.

While it is illustrated inFIG. 1that the data storage device10includes one nonvolatile memory device200, it is to be noted that the number of nonvolatile memory devices included in the data storage device10is not limited thereto. When the data storage device10includes a plurality of nonvolatile memory devices200, the codewords CW1to CW3may be distributed to at least two nonvolatile memory devices200.

FIG. 2is a diagram illustrating an example of the codeword CW1based on the TPC algorithm. The codewords CW2and CW3ofFIG. 1may be composed of the same data as the codeword CW1ofFIG. 2.

Referring toFIG. 2, the codeword CW1generated based on the TPC algorithm may include a plurality of data blocks. While not shown, each of the data blocks may include a plurality of data bits. The data blocks may be combined to configure row codewords RC1to RC4and column codewords CC1to CC4. Each data block may be included in a certain one row codeword and at the same time may be included in a certain one column codeword. WhileFIG. 2illustrates the codeword CW1which is configured by the four row codewords RC1to RC4and the four column codewords CC1to CC4, it is to be noted that the numbers of row codewords and column codewords included in a codeword are not limited thereto.

The row codewords RC1to RC4may include row parity blocks RP1to RP4. Each of the row codewords RC1to RC4may include a row parity block which is generated as corresponding data blocks are encoded. For example, the row codeword RC2may include the row parity block RP2which is generated as data blocks D21to D24are encoded. While an encoding operation may be performed based on, for example, the Bose-Chaudhuri-Hocquenghem (BCH) code, to generate each of the row parity blocks RP1to RP4, it is to be noted that an encoding operation is not limited thereto in the present embodiment and may be performed based on various other ECC algorithms.

The column codewords CC1to CC4may include column parity blocks CP1to CP4. Each of the column codewords CC1to CC4may include a column parity block which is generated as corresponding data blocks are encoded. For example, the column codeword CC1may include the column parity block CP1, which is generated as data blocks D11to D41are encoded. While an encoding operation may be performed based on, for example, the BCH code, to generate each of the column parity blocks CP1to CP4, it is to be noted that an encoding operation is not limited thereto in the present embodiment and may be performed based on various other ECC algorithms.

The decoding operation for the codeword CW1may include sub-decoding operations for the row codewords RC1to RC4and the column codewords CC1to CC4. The sub-decoding operations for the row codewords RC1to RC4may be performed based on the row parity blocks RP1to RP4. In detail, a decoding operation for each of the row codewords RC1to RC4may be performed by correcting error bits included in corresponding data blocks based on a corresponding row parity block. For example, a decoding operation for the row codeword RC2may be performed by correcting error bits included in the data blocks D21to D24based on the row parity block RP2.

Similarly, the sub-decoding operations for the column codewords CC1to CC4may be performed based on the column parity blocks CP1to CP4. In detail, a decoding operation for each of the column codewords CC1to CC4may be performed by correcting error bits included in corresponding data blocks based on a corresponding column parity block. For example, a decoding operation for the column codeword CC1may be performed by correcting error bits included in the data blocks D11to D41based on the column parity block CP1.

FIG. 3is a diagram explaining how the decoder120ofFIG. 1calculates the flag SFLAG of the codewords CW1.

Referring toFIG. 3, the decoder120may calculate row syndromes RS1to RS4of the row codewords RC1to RC4and calculate column syndromes CS1to CS4of the column codewords CC1to CC4. Each of the row syndromes RS1to RS4may indicate whether a corresponding row codeword includes at least one error bit. For example, each of the row syndromes RS1to RS4may be generated as “1” when a corresponding row codeword includes at least one error bit, and may be generated as “0” when the corresponding row codeword does not include an error bit. Similarly, each of the column syndromes CS1to CS4may indicate whether a corresponding column codeword includes at least one error bit. For example, each of the column syndromes CS1to CS4may be generated as “1” when a corresponding column codeword includes at least one error bit, and may be generated as “0” when the corresponding column codeword does not include an error bit.

A method for generating the row syndromes RS1to RS4and the column syndromes CS1to CS4may be determined depending on an ECC algorithm that is used in the encoding operation of the row codewords RC1to RC4and the column codewords CC1to CC4. Since the method is generally known to a person skilled in the art, detailed descriptions thereof will be omitted herein.

The flag SFLAG of the codeword CW1may be the product of the sum SRS of the row syndromes RS1to RS4and the sum SCS of the column syndromes CS1to CS4. Namely, in the embodiment, in order to represent the density of the errors included in the codeword CW1, the product of the sum SRS of the row syndromes RS1to RS4and the sum SCS of the column syndromes CS1to CS4may be calculated as the flag SFLAG of the codeword CW1. Therefore, in general, the larger the value of the flag SFLAG is, the larger the number of errors included in the code word CW1may be. On the other hand, the smaller the value of the flag SFLAG is, the smaller the number of errors included in the code word CW1may be.

As described above, the decoder120may perform the decoding process for the codeword CW1by comparing the expected number of errors that is calculated as the adjustment coefficient is applied to the flag SFLAG and the allowed number of errors. That is, the decoder120may perform or skip the decoding operation for the codeword CW1depending on whether the following Equation 1 is satisfied. The expected number of errors may be the product of the flag SFLAG and the adjustment coefficient A. The allowed number of errors NoEλmay be related with the performance of the decoder120that is determined when the decoder120is designed.
A*SFLAG>NoEλ[Equation 1]

When the equation 1 is satisfied, that is, when the expected number of errors A*SFLAG exceeds the allowed number of errors NoEA, the decoder120may skip the decoding operation for the codeword CW1, output a decoding failure signal and terminate the decoding process for the codeword CW1. When the equation 1 is not satisfied, that is, when the expected number of errors A*SFLAG is equal to or less than the allowed number of errors NoEA, the decoder120may perform the decoding operation for the codeword CW1.

Hereinbelow, a method for calculating the adjustment coefficient A will be described in detail. The adjustment coefficient A may be determined through a test at the development stage of a decoder.

The following equation 2 indicates that, for a certain ECC algorithm, the number of errors with which the decoding operation may fail, that is, the allowed number of errors NOEλ, and the flag SFLAG of a codeword are in a linear relationship. Such a linear relationship may be generally observed when errors are uniformly distributed in the codeword. In the equation 2, the coefficient A1may be changed depending on an ECC algorithm.
NoEλ=A1*SFLAG  [Equation 2]

Meanwhile, the test may be performed by using a plurality of test codewords. Test codewords may have uncorrectable errors at the same error rate.

In the test, the flag SFLAG of each of the test codewords may be calculated according to the method described above with reference toFIG. 3. A value that is obtained through dividing the actual number of errors NoE of a given test codeword by the flag SFLAG of the corresponding test codeword may be calculated as the test coefficient TA of the corresponding test codeword. The calculation may be expressed as the following equation 3.
TA=NoE/SFLAG  [Equation 3]

The average E[TA] of the test coefficients TA of the test codewords may be calculated as the adjustment coefficient A. The calculation may be expressed as the following equation 4.
A=E[TA]  [Equation 4]

Meanwhile, the adjustment coefficient A is calculated based on the test codewords which have a predetermined error rate. By applying the corresponding method to each of different error rates, the values of adjustment coefficients corresponding to the different error rates, respectively, may be determined. Thus, when a specific error rate is determined together with an allowed number of errors at the time of designing a decoder, an adjustment coefficient corresponding to the determined error rate may be determined and be set in the decoder. The decoder may perform the decoding process based on the set adjustment coefficient.

If uncorrectable test codewords cannot be obtained, a new coefficient A2may be calculated for correctable test codewords, as in the following equation 5, through the same process as the aforementioned process of deriving the adjustment coefficient A. In the equation 5, a test coefficient TA2may be a value that is obtained through dividing the actual number of errors of a correctable test codeword by the flag of the corresponding test codeword as described above with reference to the equation 3. The new coefficient A2may be the average of test coefficients TA2.
A2=E[TA2]  [Equation 5]

The adjustment coefficient A may be newly calculated by adding the standard deviation a of the test coefficients TA2reflected with reliability β, to the coefficient A2. The reliability β may be calculated through a test. This may be expressed in the following equation 6.
A=A2+β·σ  [Equation 6]

FIG. 4is a flow chart describing a method for operating the data storage device10shown inFIG. 1. Specifically,FIG. 4illustrates how the controller100ofFIG. 1performs a booting operation after being powered on.

Referring toFIG. 4, at step S110, the booting section110may read the codewords CW1to CW3from the nonvolatile memory device200. The codewords CW1to CW3may be transmitted to the decoder120.

At step S120, the decoder120may perform a decoding process for a selected codeword CW1among the codewords CW1to CW3according to a decoding sequence. The decoding process may be terminated by outputting a decoding success signal or a decoding failure signal.

At step S130, the decoder120may determine whether the result of the decoding process for the selected codeword CW1is a decoding success (i.e., when the output is a decoding success signal). When the result of the decoding process is a decoding success, the process may proceed to step S140.

At the step S140, the booting section110may perform a booting operation based on the selected codeword CW1, which is error-corrected through the decoding process.

Meanwhile, when, at the step S130, the result of the decoding process is not a decoding success, that is, is a decoding failure (i.e., when the output is a decoding failure signal), the process may proceed to step S150.

At the step S150, the decoder120may determine whether another codeword for which the decoding process is not performed exists among the codewords CW1to CW3. When another codeword for which the decoding process is not performed exists, the process may proceed to the step S120. In other words, at the step S120, the decoder120may perform the decoding process for another codeword selected among the codewords CW1to CW3according to the decoding sequence.

Meanwhile, when, at the step S150, another codeword for which the decoding process is not performed does not exist among the codewords CW1to CW3, that is, when the decoding process is performed for all the read codewords CW1to CW3, the process may proceed to step S160. As a result, when the result of the decoding process for all the read codewords CW1to CW3is a decoding failure, the process may proceed to the step S160.

At the step S160, the booting section110may determine that the booting operation has failed.

FIG. 5is a flow chart describing a method for operating the data storage device10shown inFIG. 1. Specifically,FIG. 5illustrates how the decoder120ofFIG. 1performs a decoding process for a selected codeword CW1among the codewords CW1to CW3. InFIG. 5, the decoding process may be terminated by outputting a decoding success signal or a decoding failure signal. The process shown inFIG. 5may be a detailed method of performing the step S120ofFIG. 4.

Referring toFIG. 5, at step S210, the decoder120may calculate the flag SFLAG of the selected codeword CW1among the codewords CW1to CW3. As described above, the decoder120may calculate the row syndromes RS1to RS4of the row codewords RC1to RC4of the selected codeword CW1, calculate the column syndromes CS1to CS4of the column codewords CC1to CC4of the selected codeword CW1, and calculate as the flag SFLAG the product of the sum SRS of the row syndromes RS1to RS4and the sum SCS of the column syndromes CS1to CS4.

At step S220, the decoder120may calculate an expected number of errors by applying an adjustment coefficient A to the flag SFLAG.

At step S230, the decoder120may determine whether the expected number of errors exceeds an allowed number of errors. When the expected number of errors exceeds the allowed number of errors, the process may proceed to step S240.

At the step S240, the decoder120may skip a decoding operation for the selected codeword CW1.

At step S250, the decoder120may terminate the decoding process for the selected codeword CW1by outputting a decoding failure signal.

Meanwhile, when, at the step S230, the expected number of errors does not exceed the allowed number of errors, the process may proceed to step S260.

At the step S260, the decoder120may perform the decoding operation for the selected codeword CW1.

At step S270, the decoder120may determine whether the result of performing the decoding operation for the selected codeword CW1is a decoding success. When the result of performing the decoding operation is a decoding success (i.e., when the output is a decoding success signal), the process may proceed to step S280.

At the step S280, the decoder120may terminate the decoding process for the selected codeword CW1by outputting a decoding success signal.

Meanwhile, when, at the step S270, the result of performing the decoding operation for the selected codeword CW1is not a decoding success, that is, is a decoding failure (i.e., when the output is a decoding failure signal), the process may proceed to the step S260. Namely, at the step S260, the decoder120may repeat the decoding operation for the selected codeword CW1.

FIG. 6is a flow chart describing a method for operating the data storage device10shown inFIG. 1. Specifically,FIG. 6illustrates how the decoder120ofFIG. 1performs a decoding process for a selected codeword CW1among the codewords CW1to CW3. Steps S310to S380in the process ofFIG. 6may be substantially the same as the steps S210to S280in the process ofFIG. 5, and therefore, overlapping descriptions thereof will be omitted herein.

Referring toFIG. 6, when, at the step S370, the result of performing the decoding operation for the selected codeword CW1is not a decoding success signal, that is, is a decoding failure signal, the process may proceed to step S390.

At the step S390, the decoder120may determine whether the repetition count of the decoding operation for the selected codeword CW1exceeds an allowed repetition count. When the repetition count exceeds the allowed repetition count, the process may proceed to the step S350. That is, at the step S350, the decoder120may stop the decoding operation for the selected codeword CW1and terminate the decoding process for the selected codeword CW1by outputting a decoding failure signal.

Meanwhile, when, at the step S390, the repetition count does not exceed the allowed repetition count, the process may proceed to the step S360. In other words, at the step S360, the decoder120may repeat the decoding operation for the selected codeword CW1.

FIG. 7is a diagram illustrating a data processing system including a solid state drive (SSD) in accordance with an embodiment of the present disclosure. Referring toFIG. 7, a data processing system1000may include a host device1100and a solid state drive (SSD)1200.

The SSD1200may include a controller1210, a buffer memory device1220, nonvolatile memory devices1231to123n, a power supply1240, a signal connector1250, and a power connector1260.

The controller1210may control general operations of the SSD1200. The controller1210may include a host interface unit1211, a control unit1212, a random access memory1213, an error correction code (ECC) unit1214, and a memory interface unit1215.

The host interface unit1211may exchange a signal SGL with the host device1100through the signal connector1250. The signal SGL may include a command, an address, data, and so forth. The host interface unit1211may interface the host device1100and the SSD1200according to the protocol of the host device1100. For example, the host interface unit1211may communicate with the host device1100through any one of standard interface protocols such as secure digital, universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), personal computer memory card international association (PCMCIA), parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCI-E) and universal flash storage (UFS).

The control unit1212may analyze and process a signal SGL inputted from the host device1100. The control unit1212may control operations of background function blocks according to a firmware or a software for driving the SSD1200. The random access memory1213may be used as a working memory for driving such a firmware or software.

The error correction code (ECC) unit1214may generate the parity data of data to be transmitted to the nonvolatile memory devices1231to123n. The generated parity data may be stored together with the data in the nonvolatile memory devices1231to123n. The error correction code (ECC) unit1214may detect an error of the data read out from the nonvolatile memory devices1231to123n, based on the parity data. If a detected error is within a correctable range, the error correction code (ECC) unit1214may correct the detected error.

The memory interface unit1215may provide control signals such as commands and addresses to the nonvolatile memory devices1231to123n, according to control of the control unit1212. Moreover, the memory interface unit1215may exchange data with the nonvolatile memory devices1231to123n, according to control of the control unit1212. For example, the memory interface unit1215may provide the data stored in the buffer memory device1220, to the nonvolatile memory devices1231to123n, or provide the data read out from the nonvolatile memory devices1231to123n, to the buffer memory device1220.

The buffer memory device1220may temporarily store data to be stored in the nonvolatile memory devices1231to123n. Further, the buffer memory device1220may temporarily store the data read out from the nonvolatile memory devices1231to123n. The data temporarily stored in the buffer memory device1220may be transmitted to the host device1100or the nonvolatile memory devices1231to123naccording to control of the controller1210.

The nonvolatile memory devices1231to123nmay be used as storage media of the SSD1200. The nonvolatile memory devices1231to123nmay be coupled with the controller1210through a plurality of channels CH1to CHn, respectively. One or more nonvolatile memory devices may be coupled to one channel. The nonvolatile memory devices coupled to each channel may be coupled to the same signal bus and data bus.

The power supply1240may provide power PWR inputted through the power connector1260, to the background of the SSD1200. The power supply1240may include an auxiliary power supply1241. The auxiliary power supply1241may supply power to allow the SSD1200to be normally terminated when a sudden power-off occurs. The auxiliary power supply1241may include large capacity capacitors.

The signal connector1250may be configured by various types of connectors depending on an interface scheme between the host device1100and the SSD1200.

The power connector1260may be configured by various types of connectors depending on a power supply scheme of the host device1100.

FIG. 8is a diagram illustrating a data processing system including a data storage device in accordance with an embodiment of the present disclosure. Referring toFIG. 8, a data processing system2000may include a host device2100and a data storage device2200.

The host device2100may be configured in the form of a board such as a printed circuit board. Although not shown, the host device2100may include background function blocks for performing the function of a host device.

The host device2100may include a connection terminal2110such as a socket, a slot or a connector. The data storage device2200may be mounted to the connection terminal2110.

The data storage device2200may be configured in the form of a board such as a printed circuit board. The data storage device2200may be referred to as a memory module or a memory card. The data storage device2200may include a controller2210, a buffer memory device2220, nonvolatile memory devices2231and2232, a power management integrated circuit (PMIC)2240, and a connection terminal2250.

The controller2210may control general operations of the data storage device2200. The controller2210may be configured in the same manner as the controller1210shown inFIG. 7.

The buffer memory device2220may temporarily store data to be stored in the nonvolatile memory devices2231and2232. Further, the buffer memory device2220may temporarily store the data read from the nonvolatile memory devices2231and2232. The data temporarily stored in the buffer memory device2220may be transmitted to the host device2100or the nonvolatile memory devices2231and2232according to control of the controller2210.

The nonvolatile memory devices2231and2232may be used as storage media of the data storage device2200.

The PMIC2240may provide the power inputted through the connection terminal2250, to the background of the data storage device2200. The PMIC2240may manage the power of the data storage device2200according to control of the controller2210.

The connection terminal2250may be coupled to the connection terminal2110of the host device2100. Through the connection terminal2250, signals such as commands, addresses, data and so forth and power may be transferred between the host device2100and the data storage device2200. The connection terminal2250may be configured into various types depending on an interface scheme between the host device2100and the data storage device2200. The connection terminal2250may be disposed on any one side of the data storage device2200.

FIG. 9is a diagram illustrating a data processing system including a data storage device in accordance with an embodiment of the present disclosure. Referring toFIG. 9, a data processing system3000may include a host device3100and a data storage device3200.

The host device3100may be configured in the form of a board such as a printed circuit board. Although not shown, the host device3100may include background function blocks for performing the function of a host device.

The data storage device3200may be configured in the form of a surface-mounting type package. The data storage device3200may be mounted to the host device3100through solder balls3250. The data storage device3200may include a controller3210, a buffer memory device3220, and a nonvolatile memory device3230.

The controller3210may control general operations of the data storage device3200. The controller3210may be configured in the same manner as the controller1210shown inFIG. 7.

The buffer memory device3220may temporarily store data to be stored in the nonvolatile memory device3230. Further, the buffer memory device3220may temporarily store the data read out from the nonvolatile memory device3230. The data temporarily stored in the buffer memory device3220may be transmitted to the host device3100or the nonvolatile memory device3230according to control of the controller3210.

The nonvolatile memory device3230may be used as a storage medium of the data storage device3200.

FIG. 10is a diagram illustrating a network system including a data storage device in accordance with an embodiment of the present disclosure. Referring toFIG. 10, a network system4000may include a server system4300and a plurality of client systems4410to4430which are coupled through a network4500.

The server system4300may service data in response to requests from the plurality of client systems4410to4430. For example, the server system4300may store the data provided from the plurality of client systems4410to4430. For another example, the server system4300may provide data to the plurality of client systems4410to4430.

The server system4300may include a host device4100and a data storage device4200. The data storage device4200may be constructed by the data storage device10shown inFIG. 1, the SSD1200shown inFIG. 7, the data storage device2200shown inFIG. 8or the data storage device3200shown inFIG. 9.

FIG. 11is a block diagram illustrating a nonvolatile memory device included in a data storage device in accordance with an embodiment of the present disclosure. Referring toFIG. 11, a nonvolatile memory device300may include a memory cell array310, a row decoder320, a data read/write block330, a column decoder340, a voltage generator350, and a control logic360.

The memory cell array310may include memory cells MC which are arranged at areas where word lines WL1to WLm and bit lines BL1to BLn intersect with each other.

The row decoder320may be coupled with the memory cell array310through the word lines WL1to WLm. The row decoder320may operate according to the control of the control logic360. The row decoder320may decode an address provided from an external device (not shown). The row decoder320may select and drive the word lines WL1to WLm, based on a decoding result. For instance, the row decoder320may provide a word line voltage provided from the voltage generator350, to the word lines WL1to WLm.

The data read/write block330may be coupled with the memory cell array310through the bit lines BL1to BLn. The data read/write block330may include read/write circuits RW1to RWn respectively corresponding to the bit lines BL1to BLn. The data read/write block330may operate according to the control of the control logic360. The data read/write block330may operate as a write driver or a sense amplifier depending on an operation mode. For example, the data read/write block330may operate as a write driver which stores data provided from the external device, in the memory cell array310in a write operation. For another example, the data read/write block330may operate as a sense amplifier which reads out data from the memory cell array310in a read operation.

The column decoder340may operate according to the control of the control logic360. The column decoder340may decode an address provided from the external device. The column decoder340may couple the read/write circuits RW1to RWn of the data read/write block330respectively corresponding to the bit lines BL1to BLn with data input/output lines (or data input/output buffers), based on a decoding result.

The voltage generator350may generate voltages to be used in background operations of the nonvolatile memory device300. The voltages generated by the voltage generator350may be applied to the memory cells of the memory cell array310. For example, a write voltage generated in a write operation may be applied to a word line of memory cells for which the write operation is to be performed. For still another example, an erase voltage generated in an erase operation may be applied to a well area of memory cells for which the erase operation is to be performed. For still another example, a read voltage generated in a read operation may be applied to a word line of memory cells for which the read operation is to be performed.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the data storage device and the operating method thereof described herein should not be limited based on the described embodiments.