Memory array with reduced leakage current

An apparatus for reading a bit of a memory array includes a bit cell column, voltage enhancement circuitry, and control circuitry. The voltage enhancement circuitry is configured to couple a bitline to a reference node. The control circuitry is configured to, in response to a read request for a bitcell element of a plurality of bitcell elements, couple a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and the voltage enhancement circuitry, to the reference node and determine a state for the bitcell element based on a voltage between the source line and the reference node. The voltage enhancement circuitry is configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node.

TECHNICAL FIELD

The disclosure relates to computer memory circuitry.

BACKGROUND

A conventional memory array has control access circuitry, e.g., a transistor, in each memory array to select a bitcell element for both read operations and write operations. The access circuitry is designed to conduct a relatively large current during a write operation in order to coerce the bitcell element to a desired state, for example, high or low (1 or 0). During a read operation, the access circuitry may conduct a much smaller current in order to sense the state of the bitcell element without altering the stored state. The read operation therefore depends on sensing a small signal on a bitline. In a conventional memory array, thousands of bitcell cells are connected to the bitline and a sourceline.

SUMMARY

During a read operation, control circuitry may access, for a read operation, a particular bitcell element between a bitline and sourceline of a column of bitcell elements. While accessing the particular bitcell element, current leakage of other bitcell elements between the bitline and sourceline of the column of bitcell elements may reduce current through the read resistance and thus the voltage signal across the read resistance, thereby resulting in the resistance appearing smaller. The leakage current of other bitcell elements may cause the resulting read resistance signal (e.g., a difference between a read high resistance state of the particular bitcell element and a read low resistance state of the particular bitcell element) to be small enough that the control circuit cannot determine the resistance state of the particular bitcell element.

In accordance with the techniques of the disclosure, an apparatus for reading a bit of a memory array may be configured to reduce a gate-to-source voltage (VGS) of unaccessed bitcell elements. For example, the apparatus may include voltage enhancement circuitry configured to increase a source voltage of unaccessed bitcell elements to be greater than a reference voltage (e.g., ground). In this way, the gate-to-source voltage (VGS) of unaccessed bitcell elements may be less than zero, which may help to reduce leakage current, thereby improving an accuracy in determining the resistance state of an accessed bitcell element.

In one example, an apparatus for reading a bit of a memory array comprises a bitcell column comprising a plurality of bitcell elements arranged in parallel. Each bitcell element of the plurality of bitcell elements comprises a series string including a first terminal coupled to a source line and a second terminal coupled to a bitline. The series string comprises a switching element coupled in series with a resistive element. The voltage enhancement circuitry is configured to couple the bitline to a reference node. The apparatus further comprises control circuitry configured to, in response to a read request for a bitcell element of the plurality of bitcell elements, couple a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and the voltage enhancement circuitry, to the reference node. The control circuitry is further configured to determine a state for the bitcell element based on a voltage between the source line and the reference node. The voltage enhancement circuitry is further configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node.

In another example, an apparatus for reading a bit of a memory array comprises a current source configured to generate a read current, a bitcell column, voltage enhancement circuitry, and control circuitry. The bitcell column comprises a plurality of bitcell elements arranged in parallel, each bitcell element of the plurality of bitcell elements comprising a series string including a first terminal coupled to a source line and a second terminal coupled to a bitline. The series string comprises a switching element coupled in series with a resistive element. The voltage enhancement circuitry is configured to couple the bitline to a reference node. The control circuitry is configured to, in response to a read request for a bitcell element of the plurality of bitcell elements, couple a current source to the bitcell column such that the read current from the current source flows from the source line, through the bitcell column and the voltage enhancement circuitry, to the reference node. The control circuitry is further configured to determine a state for the bitcell element based on a voltage between the source line and the reference node. The voltage enhancement circuitry is further configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node.

In one example, a method of operating a memory device includes receiving a read request for a bitcell element of a plurality of bitcell elements. The plurality of bitcell elements are arranged in parallel to form a bitcell column, each bitcell element of the plurality of bitcell elements comprising a series string including a first terminal coupled to a source line and a second terminal coupled to a bitline. The series string comprises a switching element coupled in series with a resistive element. The method further includes, in response to the read request, coupling a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and voltage enhancement circuitry, to a reference node. The voltage enhancement circuitry is configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node. The method further includes determining a state for the bitcell element based on a voltage between the source line and the reference node.

DETAILED DESCRIPTION

During a read operation of a memory array (e.g., magnetoresistive random-access memory (MRAM), resistive random access memory (RRAM), etc.), control circuitry may access, for a read operation, a particular bitcell element between a bitline and sourceline of a column of bitcell elements. The column of bitcell elements may include hundreds of bitcell elements, thousands of bitcell elements, or another number of bitcell elements. While accessing the particular bitcell element, current leakage of other bitcell elements between the bitline and sourceline of the column of bitcell elements may reduce an effective read resistance of the particular bitcell element that can be sensed between the sourceline and bitline.

For example, when a bitcell is in the off state, although unintended, a small amount of current may actually flow through the bitcell element. This small amount of current is leakage current. This leakage current may create a problem during the read operation. For example, many (e.g., hundreds, thousands, etc.) of unaccessed ‘off’ bitcell elements may leak current that is added to a current output by the single accessed bitcell element. While the leakage current from each of the unaccessed bitcell elements may be relatively small compared to current flow in the accessed bitcell element, the combined leakage current of all the unaccessed bitcell elements may interfere with a computing device sensing the intended signal developed by the accessed bitcell element during the read operation. For example, a computing device may erroneously read a bit as low or 0 due to the combined leakage current when the actual stored bit is a high or 1.

In accordance with the techniques of the disclosure, an apparatus for reading a bit of a memory array may be configured to reduce a gate-to-source voltage (VGS) of unaccessed bitcell elements. Rather than relying on a voltage source to generate a negative voltage at the gate of unaccessed bitcell elements, voltage enhancement circuitry may increase a voltage at a source of unaccessed bitcell elements, which reduces the gate-to-source voltage (VGS) of the unaccessed bitcell elements. For example, the voltage enhancement circuitry may be configured to increase a source voltage of unaccessed bitcell elements to be greater than a reference voltage (e.g., ground). The voltage enhancement circuitry may include a resistive element, a diode, a diode connected a metal-oxide-semiconductor field-effect transistor (MOSFET), or other voltage enhancement circuitry. In this way, the gate-to-source voltage (VGS) of unaccessed bitcell elements may be less than zero, which may help to reduce leakage current, thereby improving an accuracy in determining the resistance state of an accessed bitcell element. The foregoing description assumes the access device is an Nch MOSFET, however, other access devices may be used.

FIG.1is a conceptual diagram illustrating an example of a memory array100with voltage enhancement circuitry110, in accordance with the techniques of the disclosure. As shown, memory array100includes current source104, bitcell elements106A-106N (collectively, bitcell elements106), control circuitry108A and108B (collectively, control circuitry108), and voltage enhancement circuitry110. As shown inFIG.1, bitcell elements106form a bitcell column. WhileFIG.1illustrates one column of bitcell cell elements106, memory array100may include more than one bitcell column. For instance, memory array100may include hundreds or thousands of bitcell columns.

Current source104may be configured to generate a read current during a read operation on the bitcell column formed by bitcell elements106. Current source104may include a voltage source and resistive elements. In some examples, current source104may include a MOSFET configured to provide a constant current. While current source104is discussed herein with respect to a read current, in some examples current source104or another current source may provide a write current for changing a state of bitcell elements106.

Bitcell elements106may be configured to store a state (e.g., 0 or 1). Bitcell elements106may be assembled into an array where each column in the array contains N bitcell elements connected to sourceline (SL)116and a bitline (BL)112. While examples herein are directed to bitcell elements106configured to store one of two states (e.g., 0 or 1), bitcell elements106may be configured to store more than two states. Bitcell elements106may include read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric memory (FeRAM), magnetic random-access memory (MRAM), phase-change memory (PCM), flash memory or any other volatile or non-volatile memory element. For example, one or more of bitcell elements106may include a programmable resistive element.

Control circuitry108may be configured to couple current source104to the bitcell column formed by bitcell elements106such that a read current from current source104flows from source line116, through the bitcell column formed by bitcell elements106and voltage enhancement circuitry110, to reference node114. Control circuitry108may include data selection components, such as, for example, a multiplexer (mux) and demultiplexer. For example, control circuitry108A may include a multiplexer configured to output read current from current source104to the column formed by bitcell elements106when a read operation is being performed on the column formed by bitcell elements106. Control circuitry108B may include a demultiplexer configured to output the read current from the column formed by bitcell elements106to ground when the read operation is being performed on the column formed by bitcell elements106. In this way, control circuitry108may select a column of bitcell elements.

Control circuitry108may select a particular bitcell element of bitcell elements106by providing an access signal to a wordline of bitcell elements106. For example, to access bitcell106A, control circuitry108may be configured to, in response to a read request for a particular bitcell element, drive the switching element (e.g., MOSFET) of the particular bitcell element to activate. For instance, control circuitry108may provide an access signal (e.g., a logical 1) to wordline ‘1’ (WL1) and provide an unaccessed signal (e.g., a logical 0) to wordline ‘n’ (WLN) in response to a read request for bitline element106A.

Control circuitry108may include an analog circuit. In some examples, control circuitry108may be a microcontroller on a single integrated circuit containing a processor core, memory, inputs, and outputs. For example, control circuitry108may include one or more processors, including one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuitry, as well as any combinations of such components. The term “processor” or “processing circuitry” may generally refer to any of the foregoing logic circuitry, alone or in combination with other logic circuitry, or any other equivalent circuitry. In some examples, control circuitry108may be a combination of one or more analog components and one or more digital components.

Voltage enhancement circuitry110may be configured to generate, when the read current flows through voltage enhancement circuitry110, a voltage at the bitline (BL)112that is greater than a voltage at reference node114. Voltage enhancement circuitry110may include a diode. For instance, voltage enhancement circuitry110may include a PN diode comprising an anode coupled to bitline112and a cathode coupled to reference node114. Voltage enhancement circuitry110may include a Zener diode. For example, the Zener diode may comprise an anode coupled to reference node114and a cathode coupled to bitline112. In some examples, the Zener diode may comprise an anode coupled to bitline112and a cathode coupled to reference node114.

Voltage enhancement circuitry110may include a resistor comprising a first node coupled to bitline112and a second node coupled to reference node114.

In some examples, voltage enhancement circuitry110may include a switching element. For instance, voltage enhancement circuitry110may comprise a diode connected p-channel MOSFET or n-channel MOSFET. Some examples of switching elements may include, but are not limited to, a silicon-controlled rectifier (SCR), a Field Effect Transistor (FET), and a bipolar junction transistor (BJT). Examples of FETs may include, but are not limited to, a junction field-effect transistor (JFET), a metal-oxide-semiconductor FET (MOSFET), a dual-gate MOSFET, an insulated-gate bipolar transistor (IGBT), any other type of FET, or any combination of the same. Examples of MOSFETS may include, but are not limited to, a depletion mode p-channel MOSFET (PMOS), an enhancement mode PMOS, depletion mode n-channel MOSFET (NMOS), an enhancement mode NMOS, a double-diffused MOSFET (DMOS), any other type of MOSFET, or any combination of the same. Examples of BJTs may include, but are not limited to, PNP, NPN, heterojunction, or any other type of BJT, or any combination of the same. It should be understood that access circuitry may be high-side or low-side access circuitry. Additionally, switching elements may be voltage-controlled and/or current-controlled. Examples of current-controlled access circuitry may include, but are not limited to, gallium nitride (GaN) MOSFETs, BJTs, or other current-controlled elements.

Control circuitry108may be configured to determine a state for each bitcell element of bitcell elements106based on a voltage between source line116and reference node114. For example, control circuitry108may include a voltage comparator (implemented in hardware or implemented in software) configured to compare the voltage at source line116with a reference voltage (VREF). In this example, control circuitry108may determine that the accessed bitcell element of bitcell elements is in a first state (e.g., 0 or 1) when the voltage at source line116is greater than the reference voltage and determine that the accessed bitcell element of bitcell elements is in a second state (e.g., 1 or 0) when the voltage at source line116is not greater than the reference voltage.

In operation, control circuitry108may select the column formed by bitcell elements106. The bitline voltage at bitline112may be set to Vgnd≈0V plus the voltage provided by voltage enhancement circuitry110. In this example, control circuitry108may set bitcell element106A ON (e.g., WL1=On) and may set bitcell element106N OFF (WLN=Off) to determine a state of bitcell element106A. Current source104may supply a read current (Iread) to the selected column SL (i.e., the column formed by bitcell elements106) and control circuitry108compares the resulting voltage drop (Vdrop) across source line (SL)116and bitline112to a reference voltage (VREF) to determine if the resulting Vdropacross source line (SL)116and bitline112represents a high or low resistance state.

In systems omitting voltage enhancement circuitry110, the read current provided by current source104(SL_Iread) to the column formed by bitcell elements106may include current (Ion) through the access bitcell element (e.g., bitcell element106A) and leakage current (Ioff) at the N−1 unaccessed bitcell elements (e.g., bitcell element106N), which may be defined as follows.
SL_Iread=Ion+Ioff*(N−1)  Equation 1

The resulting Vdropacross source line (SL)116and bitline112, which may be referred to herein as SL_Vsense, may be calculated as follows.
SL_Vsense=Ion*(Rmosfet+Rpre)  Equation 2

wherein Rmosfet is a resistance of a switching element of an accessed bitcell element (e.g., bitcell element106A) and Rpre is a resistance of a programmable resistive element of the accessed bitcell element.

Using Equations 1 and 2, SL_Vsense may be derived as follows.
SL_Vsense=(SL_Iread−Ioff*(N−1))*(Rmosfet+Rpre)  Equation 3

That is, SL_Vsense is reduced if the leakage current is greater than zero (Ioff>0). In this example, Rpre may be programmed to a low state (Rpre_l) having a first resistance or a high state (Rpre_h) having a second resistance. As such, the resulting Vdropacross source line (SL)116and bitline112may be SL_Vsense_l when the resistance of the programmable resistive element is in a low state and may be SL_Vsense_h when the resistance of the programmable resistive element is in a high state as follows.
SL_Vsense 1=(SL_Iread−Ioff*(N−1))*(Rmosfet+Rpre_l)  Equation 4
SL_Vsense_h=(SL_Iread−Ioff*(N−1))*(Rmosfet+Rpre_h)  Equation 5

As such, the reference voltage (VREF) of the read circuit may be set between SL_Vsense_l and SL_Vsense_h. However, if the leakage current (Ioff) is large enough to reduce SL_Vsense_h to <VREFthen the high resistance state of the programmable resistive element may not be discerned by control circuitry108.

In accordance with the techniques of the disclosure, voltage enhancement circuitry110may be configured to reduce the leakage current (Ioff) by reducing a drain-to-source voltage (VDS) and/or reducing a gate-to-source voltage (VGS) to <0V. For instance, voltage enhancement circuitry110may reduce both the VDSand the VGSof switching elements of bitcell elements106by increasing the source voltage (VS). In the example ofFIG.1, voltage enhancement circuitry110may increase the source voltage by increasing the voltage on bitline112relative to reference node114. In some examples, voltage enhancement circuitry110includes a diode connected n-channel MOSFET connected between bitline112and reference node114, which may result in a voltage drop (Vdrop) between bitline112and reference node114that would be approximately a threshold voltage of an n-channel MOSFET (Vt) of voltage enhancement circuitry110. The threshold voltage of the n-channel MOSFET may be about 0.25 Volts. In other examples, voltage enhancement circuitry110may generate other voltages and/or include other components.

In some examples, voltage enhancement circuitry110includes a PN junction diode connected between bitline112and reference node114, which would result in a voltage drop (Vdrop) between bitline112and reference node114equal to a forward voltage of the PN junction diode (e.g., about 0.7 Volts). However, for low VDDtechnologies a forward voltage of a PN junction diode may be too large. As presented in Equations 6 and 7, voltage enhancement circuitry110may include a diode connected n-channel MOSFET for low VDDtechnologies, which would provide a smaller voltage drop (Nch Vt) than the forward voltage (Vforward) of a PN junction diode.
Vdrop=Nch Vt<Vforward  EQUATION 6
Vdrop=Nch Vt<VDD/2  EQUATION 7

For example, voltage enhancement circuitry110may be configured to generate a voltage of less than 0.6 volts between to the reference node and the bitline when the read current flows through the voltage enhancement circuitry. For instance, voltage enhancement circuitry110may include a diode connected n-channel MOSFET that generates a voltage drop of about 0.25 Volts.

The example ofFIG.1shows one example arrangement of bitline112and sourceline116, however, in other examples, sourceline116and bitline112may be switched in another arrangement. One or more of bitcell elements106may include an n-channel MOSFET. In some examples, one or more of bitcell elements106may include a p-channel MOSFET.

Some systems apply a negative voltage on the bitcell wordline (e.g., G) to reduce the leakage current (Ioff). However, techniques described herein using voltage enhancement circuitry110may reduce a design complexity and increases a reliability compared to systems that apply a negative voltage on the bitcell Wordline (i.e., G). For example, system100may omit a voltage source configured to generate a negative gate voltage. Circuitry for generating the negative voltage may be complex and may be difficult to configure to define a negative voltage compared to using voltage enhancement circuitry110. In some examples, a negative voltage on the gate (G) may increase VDG, which can exceed the allowed the maximum voltage across a gate oxide for long term reliability. Techniques described herein for using voltage enhancement circuitry110may provide a simpler circuit that is easier to design, has a smaller area, and better yield and thus a lower cost compared to systems relying on a negative gate voltage. Additionally, techniques described herein for using voltage enhancement circuitry110may decrease voltage across the bitcell gate oxide, which may increase long term reliability of system100.

FIG.2is a conceptual diagram illustrating an example of a bitcell element206, in accordance with the techniques of the disclosure. Bitcell element206may be an example of one or more of bitcell elements106ofFIG.1. Bitcell element206includes n-type MOSFET230and programmable resistive element (Rpre)232. Bitcell elements206may comprise a series string including a first terminal coupled to a source line and a second terminal coupled to a bitline. As shown, the series string may comprise a switching element (e.g., n-type MOSFET230) coupled in series with a resistive element (e.g., programmable resistive element232).

Programmable resistive element232may be written to a high resistance state (Rpre_h) or low resistance state (Rpre_l). When programmable resistive element232is read, the high or low resistance state can be sensed and interpreted as a binary 1 or 0 state respectively (or as a binary 0 or 1 state respectively). AlthoughFIG.2illustrates n-type MOSFET230as coupled to sourceline216and programmable resistive element232as coupled to bitline212, in some examples, n-type MOSFET230as coupled to bitline212and programmable resistive element232as coupled to source line216.

When bitcell element206in a selected column is read, n-type MOSFET230is turned on (e.g., by control circuitry108) to direct current through programmable resistive element232(Ion), n-type MOSFET230and each of the other N−1 unaccessed bitcell elements is kept off. However, leakage current (Ioff) in the N−1 unaccessed bitcell elements flows parallel to the direct current (Ion) thought programmable resistive element232in the on bitcell element. The leakage current may result in an effective parallel leakage resistance to programmable resistive element232(e.g., (N−1)*Ioff flows parallel to Ion). The consequence may be a reduction in the read resistance that can be sensed between sourceline216and bitline212. If the leakage current ((N−1)*Ioff) is not significantly less than the direct current (Ion) thought programmable resistive element232, the resulting difference between the read high and low resistance states can be small enough that the read circuit cannot determine if the resistance state of programmable resistive element232is high or low.

FIG.3is a conceptual diagram illustrating first example voltage enhancement circuitry310, in accordance with the techniques of the disclosure. In this example, voltage enhancement circuitry310includes a diode connected n-channel MOSFET311comprising a gate coupled to a bitline, a drain coupled to the bitline, and a source coupled to a reference node.

FIG.4is a conceptual diagram illustrating second example voltage enhancement circuitry410, in accordance with the techniques of the disclosure. In this example, voltage enhancement circuitry410includes a diode connected p-channel MOSFET411comprising a gate coupled to a reference node, a source coupled to a bitline, and a drain coupled to the reference node.

FIG.5is a conceptual diagram illustrating third example voltage enhancement circuitry510, in accordance with the techniques of the disclosure. In this example, voltage enhancement circuitry510includes a diode connected n-channel MOSFET511comprising a gate, a drain coupled to a bitline, and a source coupled to a reference node.

Voltage enhancement circuitry510comprises a diode enable input configured to enable voltage enhancement circuitry510to generate a channel that electrically couples the bitline and the reference node during the read request for the bitcell element. For example, voltage enhancement circuitry510includes a transmission gate542and an inverter544. Transmission gate542and inverter544may control n-channel MOSFET511to operate as a diode in response to a diode enable signal. For example, the gate of n-channel MOSFET511may be controlled to increase functionality such that n-channel MOSFET511is enabled when performing a read operation and disabled when not performing the read operation. While this example refers to an n-channel MOSFET, other examples may include a p-channel MOSFET.

FIG.6is a conceptual diagram illustrating fourth example voltage enhancement circuitry, in accordance with the techniques of the disclosure. In this example, voltage enhancement circuitry610includes a diode connected n-channel MOSFET611comprising a gate, a drain coupled to a bitline, and a source coupled to a reference node.

Voltage enhancement circuitry610comprises an other enable input configured to drive the voltage enhancement circuitry610to generate a channel that electrically couples the bitline and the reference node. For example, voltage enhancement circuitry610includes a multiplexer650and an inverter644. Multiplexer650and inverter644may control n-channel MOSFET611to operate as a diode in response to a diode enable signal and other enable signal. For example, the gate of n-channel MOSFET611may be controlled to increase functionality such that n-channel MOSFET611is enabled when performing a read operation (i.e., the diode enable signal), enabled when performing the other function (i.e., other enable), and disabled when not performing the read operation or the other function.

The other function could be used during a write operation as directed by “other enable” and the other function in the “read other” box. The other function could enable n-channel MOSFET611when not doing a read or write as directed by “other enable” and the other function in the “read other” box. Although multiplexer650is shown as a 2:1 multiplexer, multiplexer650may be an N:1 MUX to add additional functionalities, where N is greater than 2. While this example refers to an n-channel MOSFET, other examples may include a p-channel MOSFET.

FIG.7is a flow chart illustrating an example operation of reading a multiple-access memory device according to one or more techniques of this disclosure.FIG.7is discussed with reference toFIGS.1-6for example purposes only.

Control circuitry108receives a read request for a bitcell element of a plurality of bitcell elements (702). For example, control circuitry108receives a read request for bitcell element106A of bitcell elements106A. The plurality of bitcell elements may be arranged in parallel to form a bitcell column (e.g., see bitcell elements106ofFIG.1). Each bitcell element of the plurality of bitcell elements may comprise a series string including a first terminal coupled to a source line and a second terminal coupled to a bitline, the series string comprising a switching element coupled in series with a resistive element. For example, each bitcell element of the plurality of bitcell elements may comprise n-type MOSFET230arranged in series with programmable resistive element232.

In response to the read request, control circuitry108may couple a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and voltage enhancement circuitry, to a reference node (704). For example, controller circuit108may couple current source104to the bitcell column formed by bitcell elements106such that a read current from current source102flows from source line116, through the bitcell column formed by bitcell elements106and voltage enhancement circuitry110, to reference node114.

In response to the read request, control circuitry108may drive the switching element of the bitcell to activate (706). For example, controller circuit108may provide an access signal (e.g., a logical 1) to wordline ‘1’ (WL1) and provide an unaccessed signal (e.g., a logical 0) to wordline ‘n’ (WLN) in response to a read request for bitline element106A.

Voltage enhancement circuitry110may be configured to generate, when the read current flows through voltage enhancement circuitry110, a voltage at bitline112that is greater than a voltage at reference node114(708). For example, voltage enhancement circuitry110may include a diode connected MOSFET. For instance, voltage enhancement circuitry110may generate a voltage of less than 0.6 volts between the reference node114and bitline112when the read current flows through voltage enhancement circuitry110. Increasing the voltage at bitline112may cause voltage enhancement circuitry110to reduce a gate-to-source voltage of a switching element of a second bitcell element (e.g., bitcell element106B) of bitcell elements106to be less than zero. For instance, a gate-to-source voltage of a switching element of a second bitcell element (e.g., bitcell element106B) of bitcell elements106may be −0.25 volts when voltage enhancement circuitry110generates 0.25 volts between the reference node114and bitline112and controller circuitry108applies a voltage at reference node114(e.g., 0 volts).

Control circuitry110may determine a state for the bitcell element based on a voltage between source line116and reference node114(710). For example, control circuitry108may determine that the accessed bitcell element of bitcell elements is in a first state (e.g., 0 or 1) when the voltage at source line116is greater than the reference voltage and determine that the accessed bitcell element of bitcell elements is in a second state (e.g., 1 or 0) when the voltage at source line116is not greater than the reference voltage. Control circuitry110may output the state for the bitcell element (712).