Method and apparatus for read measurement of a plurality of resistive memory cells

A method for read measurement of a plurality N of resistive memory cells having a plurality K of programmable levels. The method includes a step of applying a first read voltage to each of the plurality N of resistive memory cells and, at each of the plurality N of resistive memory cells, measuring a first read current due to the applied first read voltage, determining a respective second read voltage based on the first read current measured at the plurality N of resistive memory cells and a target read current determined for the plurality N of resistive memory cells for each of the plurality N of resistive memory cells, and applying the respective determined second read voltage to the plurality N of resistive memory cells for obtaining a second read current for each of the plurality N of resistive memory cells.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 from Patent Application No. GB1301621.7 filed Jan. 30, 2013, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of integrated circuit memories, more specifically, the present invention relates to a method and to an apparatus for read measurement of a plurality of resistive memory cells having a plurality of programmable levels.

2. Description of Related Art

A prominent example for resistive memory cells having a plurality of programmable levels is Resistive Random Access Memory (RRAM), particular Phase Change Memory (PCM). PCM is a non-volatile solid-state memory technology that exploits the reversible, thermally-assisted switching of specific chalcogenides between certain states of different electrical conductivity.

PCM is a promising and advanced emerging non-volatile memory technology mainly due to its excellent features including low latency, high endurance, long retention and high scalability. PCM can be considered a prime candidate for Flash replacement, embedded/hybrid memory and storage-class memory. Key requirements for competitiveness of PCM technology can be multi-level cell functionality, in particular for low cost per bit, and high-speed read/write operations, in particular for high bandwidth. Multilevel functionality, i.e. multiple bits per PCM cell, can be a way to increase storage capacity and thereby to reduce cost.

Multi-level PCM is based on storing multiple resistance levels between a lowest (SET) and a highest (RESET) resistance value. Multiple resistance levels or levels correspond to partial-amorphous and partial-crystalline phase distributions of the PCM cell. Phase transformation, i.e. memory programming, can be enabled by Joule heating. In this regard, Joule heating can be controlled by a programming current or voltage pulse. Storing multiple resistance levels in a PCM cell is a challenging task.

In Wong, H.-S Philip et al., “Recent Progress of Phase Change Memory and Resisitve Switching Random Access Memory”, ICSICT, 2010, Proc. IEEE, it is described that multi-level cell (MLC) programming is the most efficient way to increase the storage capacity of PCM. In order to achieve MLC programming, an iterative algorithm can be used, which adapts the programming current to the characteristics of each cell in every cycle so that the cell is programmed to the desired cell-state with minimum write latency (PAPANDREOU, N. et al., “Enabling Technologies for Multilevel Phase-Change Memory”, European Phase Change and Ovonics Symposium, 2011).

When reading MLC data from a memory array including a plurality of memory cells, the read-back signals form Gaussian-like distributions corresponding to the different levels. This is mainly due to noise during the read process, a distribution of programmed cell-states for each level within each target bin during the write process and a non-uniform drift of the difference resistance levels (POZIDIS, H. et al., “A Framework for Reliability Assessment in Multilevel Phase-Change Memory”, Memory Workshop (IMW), pages 1-4, May 2012, 2012 4th IEEE International). Further, the actual level statistics are data-dependent and typically change over time. As a result, an estimation of the first and second-order statistics is essential for reliable level detection (European Patent Application No. 11183336.4). The accuracy of the estimation depends heavily on the number of available data. In main memory applications and hybrid memory applications, the number of data that is collected during memory access can be limited.

Accordingly, it is an aspect of the present invention to improve the read measurement of a plurality of resistive memory cells.

BRIEF SUMMARY OF THE INVENTION

The present invention provides a method for read measurement of a plurality N of resistive memory cells having a plurality K of programmable levels, the method including: applying a first read voltage to the plurality N of resistive memory cells; measuring a first read current due to the first read voltage; determining a second read voltage based on the first read current measured at the plurality N of resistive memory cells; determining a target read current for the plurality N of resistive memory cells; applying the second read voltage to the plurality N of resistive memory cells; and obtaining a second read current.

Another aspect of the present invention provides an apparatus for read measurement of a plurality N of resistive memory cells having a plurality K of programmable levels, the apparatus including: a voltage generator for applying a voltage to the plurality N of resistive memory cells; a measurement circuit for making a measurement indicative of cell current; a controller for controlling operation; wherein the voltage generator applies a first read voltage to the plurality N of resistive memory cells; wherein the measurement circuit measures a first read current due to the first read voltage; wherein the controller determines a second read voltage for the plurality N of resistive memory cells based on the first read current and a target read current determined for the plurality N of resistive memory cells; and wherein the voltage generator applies the second read voltage to the plurality N of resistive memory cells for obtaining a second read current for the plurality N of resistive memory cells.

Another aspect of the present invention provides a resistive memory device including: a memory including a plurality N of resistive memory cells having a plurality K of programmable levels; a voltage generator for applying a voltage to the plurality N of resistive memory cells; a measurement circuit for making a measurement indicative of cell current; a controller for controlling operation; wherein the voltage generator applies a first read voltage to the plurality N of resistive memory cells; wherein the measurement circuit measures a first read current due to the first read voltage; wherein the controller determines a second read voltage for the plurality N of resistive memory cells based on the first read current and a target read current determined for the plurality N of resistive memory cells; and wherein the voltage generator applies the second read voltage to the plurality N of resistive memory cells for obtaining a second read current for the plurality N of resistive memory cells.

Similar or functionally similar elements in the figures have been allocated the same reference signs if not otherwise indicated.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

According to an embodiment of a first aspect of the present invention, a method for read measurement of a plurality N of resistive memory cells having a plurality K of programmable levels is described. The method includes a step of applying a first read voltage to each of a plurality N of resistive memory cells and, at each of the plurality N of resistive memory cells, measuring a first read current due to an applied first read voltage, a step of determining a respective second read voltage based on the first read current measured at the memory cell and a target read current determined for the memory cell for each of the plurality N of resistive memory cells, and a step of applying the respective determined second read voltage to the memory cell for obtaining a second read current for each of the plurality N of resistive memory cells.

According to embodiments of the invention, a two-step read process is used for improving read signals from multi-level cell distributions. In the two-step read process, all memory cells are read at a first read voltage in a first step and with a second read voltage in the second step. In most cases, the second read voltage is different from the first read voltage. But, for the case that the first read current is equal to the mean value of the read current distribution, the second read voltage is the same as the first read voltage. Thereby, the non-linear current-voltage characteristic of the memory cells is exploited in order to determine the second read voltage of each of the plurality N of resistive memory cells. For determining the second read voltage, at least the first read current measured at the memory cell and a predefined target read current is used. The determined second read voltage results in a confinement of the level distributions at the mean values which can enhance the effective signal-to-noise ratio (SNR) and improve the estimation and detection under small data records. This method can lead to a better error-rate performance. Further, by means of the present read measurement, drift can be compensated.

According to embodiments of the present invention, the resistive memory cell is a PCM cell (PCM, Phase Change Memory).

The PCM cell can be understood as a non-linear resistive device. The larger the amorphous size of the PCM cell the stronger is the non-linearity in the current-voltage characteristic at the cell-state read regime.

In an embodiment of the present invention, the second read voltage is determined such that the second read current is constant for all the memory cells programmed with the same programmable level from a plurality K of programmable levels. By exploiting the non-linear current-voltage-characteristics of the plurality N of resistive memory cells, a variable read voltage, here the second read voltage, determined for each cell can be used to read the different cells of the same programmable level with almost the same read current.

In a further embodiment of the present invention, the method includes determining one respective target read current for each of the plurality K of programmable levels. For an example that K=4, there are four programmable levels and therefore four different target read currents. By applying the first read voltage, each programmed cell can be mapped to one of the four target read currents.

In a further embodiment of the present invention, for each of the plurality K of programmable levels, the target read current is determined as the mean value of the first read currents of the plurality N of resistive memory cells programmed with the same programmable level.

For the above-mentioned example that K=4, there are four level means or mean distribution values for the target read currents. The level means is a good approximation for determining the respective target read currents.

In a further embodiment of the present invention, the target read currents for the plurality K of programmable levels are determined by a blind estimation. Within the blind estimation, a batch of the plurality N of resistive memory cells is read for estimating the target read currents.

In a further embodiment of the present invention, the target read currents for the plurality K of programmable levels is determined by using a plurality of reference cells. The memory cells and the reference cells are structurally identical.

In another embodiment of the present invention, for each of the plurality K of programmable levels, the target read currents are determined as the nominal read currents used when programming the cells to the plurality K of programmable levels. In particular in this embodiment of the present invention, the present method can easily compensate for drift.

In a further embodiment, the method includes mapping one target read current of the target read currents to the cell for each of the plurality N of resistive memory cells, and determining the second read voltage based on the first read current measured at the cell and the target read current mapped to the cell. Thus, one target read current can be mapped to each of the cells individually.

In a further embodiment, the step of mapping one target read current of the K target read currents to the plurality N of resistive cells includes: dividing a read current space of the first read current into a plurality K of distinct regimes and associating each target read current with one of the K distinct regimes, and for each of the plurality N of resistive memory cells, allocating the first read current measured at the memory cell to one of the K distinct regimes and mapping the target read current associated with the allocated distinct regime to the memory cell.

In another embodiment of the present invention, the plurality K of distinct regimes merge and are disjunct to each other, wherein the measured first read current is allocated to that of the plurality K of distinct regimes including a value corresponding to the measured first read current.

In a further embodiment of the present invention, the read current space is digitized by an analog-to-digital converter. By use of an analogue-to-digital converter, a direct mapping of voltage values and read currents is easily possible.

In a further embodiment of the present invention, for each of the plurality N of resistive memory cells, the second read voltage is calculated based on the first read current measured at the memory cell, the first read voltage and the target read current determined for the memory cell.

For example, the second read voltage can be calculated by: V2=V1+k.ln(It/I1), where V2indicates the second read voltage, V1the first read voltage, It the target read current determined for the memory cell, I1the first read current measured at the memory cell at the read voltage V1, and k>0 is a constant which can be cell-state dependent.

According to an embodiment of a second aspect of the present invention, the present invention relates to a computer program including a program code for executing at least one step of the method of the first aspect for read measurement of a plurality N of resistive memory cells having a plurality K of programmable levels when run on at least one computer.

According to an embodiment of a third aspect of the present invention, an apparatus for read measurement of a plurality N of resistive memory cells having a plurality K of programmable levels is described. The apparatus includes a voltage generator for applying a voltage to the plurality N of resistive memory cells, a measurement circuit for making a measurement indicative of the cell current of the plurality N of resistive memory cells, and a controller for controlling operation of the apparatus such that the voltage generator applies a first read voltage to each of the plurality N of resistive memory cells, the measurement circuit measures a first read current due to the applied first read voltage at each of the plurality N of resistive memory cells, the controller determines a second read voltage for the plurality N of resistive memory cells based on the first read current measured at the memory cell and a target read current determined for the plurality N of resistive memory cells, and the voltage generator applies the respective determined second read voltage to the plurality N of resistive memory cells for obtaining a second read current for the plurality N of resistive memory cells.

According to an embodiment of a fourth aspect of the present invention, a resistive memory device is described. The resistive memory device includes a memory with a plurality N of resistive memory cells having a plurality K of programmable levels, and a read/write apparatus for reading and writing data in the plurality N of resistive memory cells, wherein the read/write apparatus includes an apparatus of above mentioned third aspect.

In the following, exemplary embodiments of the present invention are described with reference to the enclosed figures.

Embodiments of the present invention will now be described below with reference to the accompanying drawings. In the following description, elements that are identical are referenced by the same reference numbers in all the drawings unless noted otherwise. The configurations explained here are provided as preferred embodiments, and it should be understood that the technical scope of the present invention is not intended to be limited to these embodiments.

InFIG. 1, according to an embodiment of the present invention, a sequence of method steps for read measurement of a plurality N of resistive memory cells having a plurality K of programmable levels is depicted. For example, K=4. The plurality N of resistive memory cells11, shown inFIG. 12, is embodied by a PCM cell, PCM cell11, for example. The respective PCM cell11is controllable by a first terminal connected to a bitline, BL, and by a second terminal connected to a wordline, WL (FIG. 12). Alternatively, a selection device with one terminal controlling the PCM cell11can be employed, as in the case of a diode (not shown).

InFIG. 1, a step101, a first read voltage V1is applied to each of the plurality N of resistive memory cells11(seeFIG. 12) and, at each of the plurality N of resistive memory cells11, a first read current I1due to the applied first read voltage V1is measured.

In step102, for each of the plurality N of resistive memory cells11, a respective second read voltage V2is determined based on the first read current I1measured at the plurality N of resistive memory cells11and a target read current It1-It4determined for the N resistive memory cell11. In particular, the respective second read voltage V2is determined such that the second read current I2is constant for all the plurality N of resistive memory cells11programmed with the same programmable level L1-L4, from a plurality K of programmable levels. Thus, one respective target current It1-It4is determined for each of the plurality K of programmable levels. For the example that K=4, there are four different target read currents It1-It4for the four different programmable levels L1-L4. For example, for each of the four programmable levels L1-L4, the target read current It1-It4is determined as the mean value of the first read current I1of the plurality N of resistive memory cells11programmed with the same programmable level L1-L4. For determining the target read currents It1-It4, a blind estimation can be used. Within such a blind estimation, a batch of the plurality N of resistive memory cells11can be read for estimating the four target read currents It1-It4. Alternatively, a plurality of reference cells can be used for determining the four target read currents It1-It4.

In step103, for each of the plurality N of resistive memory cells11, the respective determined second read voltage V2is applied to the memory cell11for obtaining a second read current I2.

InFIGS. 2-4, an example is shown which illustrates the use of variable read voltages to confine MLC distributions. In this regard,FIG. 2depicts an example of a histogram of read current values for a fixed first read voltage V1(step101ofFIG. 1).FIG. 3depicts a diagram illustrating read voltage waveforms as a function of the first read current I1due to the applied first read voltage V1, andFIG. 4depicts an example of a histogram of the read current values for a variable second read voltage adjusted by means ofFIG. 3. In the example ofFIGS. 2-4, K=4, and therefore four levels L1-L4and four target read currents It1-It4are used.

InFIG. 2, the histogram shows four distributions for the four levels L1-L4which are around their respective mean value. The read voltage waveforms ofFIG. 3have a 10 mV resolution and are a function of the first read current I1at the first read voltage V1and the target read current It1-It4. In this example V1is 0.28V and the target read currents It1-It4correspond to the mean values of the four distributions L1-L4. Also, the curves inFIG. 3show how the second read voltage V2is shaped as a function of the first read current I1and the respective target read current It1-It4. When the read current I1is lower than the target value It1-It4then the read current I2, here the second read current, has to be increased. Accordingly, when the read current I1is higher than the respective target value then the read current, here the second read current I2has to be decreased. For each of the four level distributions L1-L4, the new read voltage as shown inFIG. 3, namely the second read voltage can be applied in step103ofFIG. 1. ComparingFIGS. 2 and 4, the distributions inFIG. 4are tighter resulting in a higher signal-to-noise ratio (SNR).

InFIG. 5, according to a second embodiment of the present invention, a sequence of method steps for read measurement of a plurality N of resistive memory cells11having a plurality K of programmable levels L1-L4is shown. This second embodiment is also explained with reference toFIGS. 6-8.

In step501, a first read voltage V1is applied to each of the plurality N of resistive memory cells11(seeFIG. 12) and, at each of the plurality N of resistive memory cells11, a first read current I1due to the applied first read voltage V1is measured.

In step502, a read current space of the first read current I1is divided into a plurality K of distinct regimes R1-R4and each target read current It1-It4is associated with one of the plurality K of distinct regimes R1-R4. InFIG. 7, K=4 and the reference currents Iref1-Iref3are used to define the four distinct regimes R1-R4.

In step503, for each of the plurality N of resistive memory cells11, the first read current I1measured at the plurality N of resistive memory cells11is allocated to one of the plurality K of distinct regimes R1-R4and the target read current It1-It4is associated with the allocated K distinct regime R1-R4is mapped to the plurality N of resistive memory cells11.

In step504, the second read voltage V2is determined based on the first read current I1measured at the plurality N of resistive memory cells11and the target read current It1-It4mapped to the plurality N of resistive memory cells11.

In step505, for each of the plurality N of resistive memory cells11, the respective determined second read voltage V2is applied to the plurality N of resistive memory cells11for obtaining a second read current I2.

InFIGS. 6-8, an example is depicted for the shaping of the read voltage V2for MLC distributions. In this regard,FIG. 6shows a level distribution D1at the first level L1where the mean of the distribution is characterized by M1. V1indicates the first read voltage (step501ofFIG. 5), where V2indicates the second read voltage (see step504ofFIG. 5). The target read current It1equals the mean value of the read current of the distribution D1when using the first read voltage V1. The arrow A1illustrates that a higher voltage is used for the second read voltage V2for the plurality N of resistive memory cells11with a first read current at V1which is lower than the mean value. In contrast, the arrow A2shows that a lower voltage is used for the second read voltage V2for the plurality N of resistive memory cells11with a first read current at V1which is higher than the mean value. A corresponding example for the four programmable levels L1-L4is depicted inFIG. 7, where M1-M4show the mean current values for the four programmable levels L1-L4at the first read voltage V1. Estimation of the programmable level means based on blind estimation techniques or reference cells can be used in order to track temporal variations of the MLC distributions due to drift, according to embodiments of the present invention. Then arrows A3inFIG. 8illustrate that both the target currents It1-1t4and the reference currents Iref1-Iref3can be adjusted by tracking the level means during drift using reference cells or blind estimation techniques. ComparingFIGS. 8 and 7, one can recognize that the present shaping of the read voltage V2can be easily adjusted in order to follow drift.

InFIG. 9, an example for the design of the read voltage function for the second read voltage V2is depicted in detail for the general case of levels n−1, n and n+1.

The boundaries for the negative feedback second read voltage V2can be determined by a second-order statistics estimate for each level n−1, n, n+1 using either blind estimation techniques or reference cells. As a practical example, a rule of −/+kσ2around the mean value M can be used, e.g. k=4 or 5. In a case of a distribution overlap, the reference current values Iref1-Iref3used to select the correct target current It1-It4can serve as boundaries (seeFIG. 7).

InFIGS. 10 and 11, an example is given for the design of a read voltage function for the second read voltage V2.

InFIG. 10, O1shows a positive offset, wherein O2shows a negative offset. Further, the following actions can be derived from lines I1and I2ofFIG. 10: in line |1: +/−: increase/decrease of the read current with respect to the mean of the distribution, and in line I2: +/−: increase/decrease of the read current with respect to the value at the first read voltage V1.

For the examples ofFIGS. 10 and 11, the following equation can be used: Voffs=V1−β log(Iref/I1), β>0. The offset Voffswith respect to the first read voltage V1can be calculated based on the reference currents Iref that are used to divide the current space (seeFIG. 7, for example). Then, the locally shaped second read voltage V2is used to confine the MLC distributions. The combined result can then be used to enhance the signal-to-noise ratio (SNR) which will ultimately lead to a better error-rate performance.

FIG. 12shows an embodiment of an apparatus10for a read measurement of a plurality N of resistive memory cells11having a plurality K of programmable levels L1-L4. Without loss of generality and because of illustration,FIG. 12shows only one N resistive memory cell11. The apparatus10ofFIG. 12can be called read measurement apparatus and can be included in a read/write apparatus. The apparatus10is connected to the N resistive memory cell11, for example a PCM cell11, according to embodiments of the present invention. InFIG. 12, the PCM cell11is represented as a variable resistance. The N resistive memory cell11is assessed via appropriate voltages applied to the appropriate wordline, WL, and bitline, BL, for the N resistive memory cell11.

An access device12, here a field-effect transistor (FET)12, according to an embodiment of the present invention, is connected in series with the N resistive memory cell11for controlling the access to the N resistive memory cell11. The gate of the FET12is connected to the wordline, WL, whereby application of a wordline, WL, voltage switches on FET12, allowing current to flow in N resistive memory cell11.

The apparatus10includes a voltage generator13for applying a voltage, here a read voltage V1, V2, to the cell bitline, BL. The apparatus10also includes a measurement circuit, for example a current detector14, for making a measurement indicative of current I1,12flowing through the N resistive memory cell11due to the applied read voltage V1, V2. Further, the apparatus10includes a controller15, a so-called measurement controller15, for controlling the operation of the apparatus10. The measurement controller15receives the output of the current detector14and controls the generation of the voltage generator13to implement the following: In particular, the controller15is adapted to control the operation of the apparatus10such that the voltage generator13applies a first read voltage V1to each of the plurality N of resistive memory cells11. The measurement circuit14measures a first read current I1due to the applied first read voltage V1at each of the plurality N of resistive memory cells11. Further, the controller15determines a respective second read voltage V2for each of the plurality N of resistive memory cells11based on the first read current I1measured at the memory cell11and the target read current It1-It4determined for the respective memory cell11. Then, the voltage generator13applies to the respective determined second read voltage V2to the memory cell11for obtaining a second read current I2for each of the plurality N of resistive memory cells11.

Computerized devices can be suitably designed for implementing embodiments of the present invention as described herein. In that respect, it can be appreciated that the methods described herein are largely non-interactive and automated. In exemplary embodiments of the present invention, the methods described herein can be implemented either in an interactive, partly-interactive or non-interactive system. The methods described herein can be implemented in software (e.g., firmware), hardware, or a combination thereof. In exemplary embodiments, the methods described herein are implemented in software, as an executable program, the latter executed by suitable digital processing devices. In further exemplary embodiments, at least one step or all steps of above method ofFIG. 1or5can be implemented in software, as an executable program, the latter executed by suitable digital processing devices. More generally, embodiments of the present invention can be implemented wherein general-purpose digital computers, such as personal computers, workstations, etc., are used.

For instance, the system800depicted inFIG. 13schematically represents a computerized unit801, e.g., a general-purpose computer. For example, the system800can include an apparatus10as shown inFIG. 12. In exemplary embodiments of the present invention, in terms of hardware architecture, as shown inFIG. 13, the unit801includes a processor805, memory810coupled to a memory controller815, and one or more input and/or output (I/O) devices840,845,850,855(or peripherals) that are communicatively coupled via a local input/output controller835. In particular, the memory controller815can include the apparatus10ofFIG. 12. The input/output controller835can be, but is not limited to, one or more buses or other wired or wireless connections, as is known in the art. The input/output controller835can have additional elements, which are omitted for simplicity, such as controllers, buffers (caches), drivers, repeaters, and receivers, to enable communications. Further, the local interface can include address, control, and/or data connections to enable appropriate communications among the aforementioned components.

The processor805is a hardware device for executing software, particularly that stored in memory810. The processor805can be any custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with the computer801, a semiconductor based microprocessor (in the form of a microchip or chip set), or generally any device for executing software instructions.

The memory810can include any one or combination of volatile memory elements (e.g., random access memory) and nonvolatile memory elements. Moreover, the memory810can incorporate electronic, magnetic, optical, and/or other types of storage media. Note that the memory810can have a distributed architecture, where various components are situated remote from one another, but can be accessed by the processor805.

The software in memory810can include one or more separate programs, each of which includes an ordered listing of executable instructions for implementing logical functions. In the example ofFIG. 13, the software in the memory810includes methods described herein in accordance with exemplary embodiments and a suitable operating system (OS)811. The OS811essentially controls the execution of other computer programs, such as the methods as described herein (e.g.,FIG. 1or5), and provides scheduling, input-output control, file and data management, memory management, and communication control and related services.

The methods described herein can be in the form of a source program, executable program (object code), script, or any other entity including a set of instructions to be performed. When in a source program form, then the program needs to be translated via a compiler, assembler, interpreter, or the like, as known per se, which can be included within the memory810, so as to operate properly in connection with the OS811. Furthermore, the methods can be written as an object oriented programming language, which has classes of data and methods, or a procedure programming language, which has routines, subroutines, and/or functions.

Possibly, a conventional keyboard850and mouse855can be coupled to the input/output controller835. Other I/O devices840-855can include sensors (especially in the case of network elements), i.e., hardware devices that produce a measurable response to a change in a physical condition like temperature or pressure (physical data to be monitored). Typically, the analog signal produced by the sensors is digitized by an analog-to-digital converter and sent to controllers835for further processing. Sensor nodes are ideally small, consume low energy, are autonomous and operate unattended.

In addition, the I/O devices840-855can further include devices that communicate both inputs and outputs. The system800can further include a display controller825coupled to a display830. In exemplary embodiments of the present invention, the system800can further include a network interface or transceiver860for coupling to a network865.

The network865transmits and receives data between the unit801and external systems. The network865is possibly implemented in a wireless fashion, e.g., using wireless protocols and technologies, such as IEEE 802.15.4 or similar. The network865can be a fixed wireless network, a wireless local area network (LAN), a wireless wide area network (WAN) a personal area network (PAN), a virtual private network (VPN), intranet or other suitable network system and includes equipment for receiving and transmitting signals.

When the unit801is in operation, the processor805is configured to execute software stored within the memory810, to communicate data to and from the memory810, and to generally control operations of the computer801pursuant to the software. The methods described herein and the OS811, in whole or in part are read by the processor805, typically buffered within the processor805, and then executed. When the methods described herein (e.g. with reference toFIG. 1or5) are implemented in software, the methods can be stored on any computer readable medium, such as storage820, for use by or in connection with any computer related system or method.

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects. Furthermore, aspects of the present invention can take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. Any combination of one or more computer readable medium(s) can be utilized. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium can be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium can include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal can take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium can be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium can be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.