Voltage level setting circuit

A voltage level setting circuit sets a voltage level of a predetermined portion of an input signal received through a coupling capacitor to a desired reference voltage level suited for a signal processing which is carried out in a signal processing circuit, where the voltage level of the predetermined portion is used as a reference level of the input signal. The voltage level setting circuit comprises a charge injecting circuit for injecting a quantity of charge to a node between the coupling capacitor and the signal processing circuit, and a control circuit for controlling the injection of charge by the charge injection circuit responsive to a signal from the signal processing circuit so that the voltage level of the predetermined portion at the node is set to the desired reference voltage level.

BACKGROUND OF THE INVENTION 
The present invention generally relates to voltage level setting circuits, 
and more particularly to a voltage level setting circuit for setting in a 
signal processing circuit system a voltage level of a reference portion of 
an input signal which is obtained from a signal source circuit system. 
FIG. 1 shows an example of an image signal processing circuit employing the 
conventional voltage level setting circuit. An image signal from a signal 
source circuit system (not shown) is applied to a terminal 10 and is 
supplied to an image signal processing circuit system 11 through a 
coupling capacitor C1. The image signal processing circuit system 11 
comprises an amplifier 12 for amplifying the incoming image signal from 
the coupling capacitor C1, an analog-to-digital (A/D) converter 13 for 
converting an output signal of the amplifier 12 into a digital signal, a 
digital signal processing circuit 14 for subjecting the digital signal 
from the A/D converter 13 to a signal processing including a luminance 
correction and the like, and a voltage level setting circuit 15. The 
amplifier 12, the A/D converter 13 and the digital signal processing 
circuit 14 constitute a signal processing circuit. An output digital 
signal of the image signal processing circuit system 11 is supplied to a 
circuit system (not shown) in a subsequent stage through a terminal 16. 
When the voltage level of the image signal is within a voltage level range 
which can be processed in the image signal processing circuit system 11, 
there is no need to provide the coupling capacitor C1 nor the voltage 
level setting circuit 15. However, the voltage level of the image signal 
generally does not always fall within the voltage level range which can be 
processed in the image signal processing circuit system 11. 
For example, it will be assumed for convenience, sake that the image signal 
is obtained from a charge coupled device (CCD) of the signal source 
circuit system. In this case, the voltage level of the image signal is 6 V 
to 7 V, but a reference voltage level of a reference portion of the image 
signal can be converted by use of the coupling capacitor C1 and the 
voltage level setting circuit 15. The reference voltage is used as a 
reference level of the input signal. For this reason, the voltage level of 
the image signal can be converted so as to fall within the voltage level 
range which can be processed in the image signal processing circuit system 
11, such as to a voltage level range of 2 V to 4 V, for example. 
FIG. 2 is a circuit diagram for explaining the operation of a first example 
of the voltage level setting circuit 15. In FIG. 2, those parts which are 
the same as those corresponding parts in FIG. 1 are designated by the same 
reference numerals, and a description thereof will be omitted. The image 
signal from a signal source 17 such as the CCD is applied to the terminal 
10. A voltage level setting circuit 15a comprises a bias resistor R1 and a 
bias voltage source for supplying a bias voltage V.sub.B. 
When the image signal from the signal source 17 has a voltage level V1 as 
shown in FIG. 3(A) made up of a D.C. component indicated by a phantom line 
and an A.C. component, this image signal has a voltage level V2 shown in 
FIG. 3(B) after it passes through the coupling capacitor C1. In other 
words, it is possible to set a reference voltage level of the image signal 
(V2) to the bias voltage V.sub.B. 
However, according to the voltage level setting circuit 15a, a signal 
component having a frequency lower than a frequency determined by the 
coupling capacitor C1 and the bias resistor R1 becomes attenuated. For 
example, a D.C. step shown in FIG. 3(A) becomes attenuated exponentially 
(by e.sup.-t/C1R1, where t denotes the time) as indicated by a phantom 
line in FIG. 3(B). For this reason, there is a problem in that an 
appropriate signal transmission cannot be carried out for the D.C. signal 
component and the low-frequency signal component having a time constant 
greater than the time constant determined by the coupling capacitor C1 and 
the resistor R1. 
FIG. 4 is a circuit diagram for explaining the operation of a second 
example of the voltage level setting circuit 15. In FIG. 4, those parts 
which are the same as those corresponding parts in FIG. 2 are designated 
by the same reference numerals, and a description thereof will be omitted. 
A voltage level setting circuit 15b comprises a switching circuit S1 and a 
bias voltage source for supplying the bias voltage V.sub.b. 
The image signal from the signal source 17 has a voltage level V3 as shown 
in FIG. 5(A), for example, and the switching circuit S1 is turned ON while 
the image signal (V3) has a reference voltage level a during the 
predetermined time period. Hence, this image signal has a voltage level V4 
shown in FIG. 5(B) after it passes through the coupling capacitor C1 and 
the reference voltage level is clamped to the bias voltage V.sub.B. On the 
other hand, the switching circuit S1 is turned OFF while a picture 
information portion b of the image signal (V3) is received at the terminal 
10, and a D.C. voltage part of the picture information portion b is 
clamped. 
The voltage level setting circuit 15b forcibly sets the voltage level of 
the image signal to the bias voltage V.sub.B during the predetermined time 
period corresponding to the reference portion of the image signal. Since 
this forced setting of the voltage level must be carried out 
instantaneously, there is a need to carry out a charge and discharge 
operation at a high speed. Hence, the switching circuit S1 is generally 
constituted by a semiconductor element such as metal oxide semiconductor 
(MOS) element and a bipolar element through which a relatively large 
current may flow. But when the semiconductor element is used to constitute 
the switching circuit S1, a clock signal feedthrough occurs thereby 
generating an offset voltage .DELTA.V shown in FIG. 5(B). This clock 
signal feedthrough occurs because a charge is generated at a channel of 
the MOS element (transistor) when the MOS element is turned ON and this 
charge affects the voltages V4 and V.sub.B when the MOS element is turned 
OFF. Furthermore, it is difficult to maintain the bias voltage V.sub.B 
stable when the relatively large current flows through the switching 
circuit S1. Therefore, there is a problem in that an appropriate signal 
transmission cannot be carried out. 
SUMMARY OF THE INVENTION 
Accordingly, it is a general object of the present invention to provide a 
novel and useful voltage level setting circuit in which the problems 
described heretofore are eliminated. 
Another and more specific object of the present invention is to provide a 
voltage level setting circuit for setting a D.C. voltage level of a 
predetermined portion of an input signal which is received by a signal 
processing circuit system from a signal source circuit system through a 
coupling capacitor, by controlling a quantity of charge which is injected 
at a node between the coupling capacitor and the signal processing circuit 
system. According to the voltage level setting circuit of the present 
invention, it is possible to accurately set the D.C. voltage level of the 
predetermined portion of the input signal at the node between the coupling 
capacitor and the signal processing circuit system, thereby ensuring an 
appropriate signal processing in the signal processing circuit system. 
Still another object of the present invention is to provide a voltage level 
setting circuit in which a voltage level of a predetermined portion of an 
input signal is set, that is, a clamping voltage is set, by use of an 
output digital signal of a signal processing circuit. The value of the 
output digital signal of the signal processing circuit is compared with a 
digital code which corresponds to a reference voltage level, and a digital 
error signal obtained by the comparison is converted into an analog 
voltage. This analog voltage is added to or subtracted from the input 
signal during a predetermined time period corresponding to the 
predetermined portion of the input signal. The clamping voltage is 
corrected until the digital error signal becomes zero. Therefore, a 
feedback loop includes an analog-to-digital converter of the signal 
processing circuit, and it is possible to eliminate an offset voltage 
generated in the signal processing circuit. Furthermore, since the 
comparison is made between digital quantities, it is possible to compress 
an offset voltage generated in the comparing part. 
Other objects and further features of the present invention will be 
apparent from the following detailed description when read in conjunction 
with the accompanying drawings.

DETAILED DESCRIPTION 
FIG. 6 shows a signal processing circuit system employing a first 
embodiment of the voltage level setting circuit according to the present 
invention. An input signal such as an image signal received from a signal 
source 20 of a signal source circuit system is applied to a terminal 21, 
and is supplied to a signal processing circuit system through a coupling 
capacitor C2. The signal processing circuit system comprises a signal 
processing circuit 22 and a charge injecting circuit 23 which is used as 
an essential part of the voltage level setting circuit. An output signal 
of the signal processing circuit 22 is supplied to a circuit system (not 
shown) in a subsequent stage through a terminal 24. 
A voltage level at a node N between the coupling capacitor C2 and the 
signal processing circuit system is determined by a quantity of charge 
injected by the charge injecting circuit 23. The input signal from the 
signal source 20 has a voltage level V5 shown in FIG. 7(A) at the terminal 
21 and has a voltage level V6 shown in FIG. 7(B) at the node N. 
According to the present embodiment, the charge injecting circuit 23 
injects the charge only during a predetermined time period corresponding 
to the reference portion of the input signal (V5), and electrically 
disconnects the charge injecting circuit 23 from the reception side of the 
signal processing circuit system during other time periods so as to block 
a D.C. current path and hold the injected charge. As a result, the input 
signal (V5) can be received by the signal processing circuit system as a 
signal (V6) which has the reference portion thereof accurately clamped to 
a predetermined voltage. Since the voltage level of the reference portion 
is set by the injection of the charge, no offset voltage occurs due to the 
clock signal feedthrough as in the case of the conventional voltage level 
setting circuit. For example, in the case where the input signal (V5) from 
the signal source 20 is an image signal, the image signal is clamped to 
the predetermined voltage during a synchronizing signal period thereof. 
Next, a description will be given on the circuit construction and operation 
of an essential part of the first embodiment, by referring to FIG. 8. An 
essential part of the signal processing circuit 22 related to the charge 
injecting circuit 23 comprises a buffer 30, sample and hold circuits 31 
and 32, a control circuit 33 and an inverter 34. The sample and hold 
circuits 31 and 32 have the same construction and each comprise a switch, 
a capacitor and a buffer. The control circuit 33 comprises a differential 
amplifier 35, operational amplifiers 36 and 37, resistors R.sub.N and 
R.sub.P, a p-channel MOS field effect transistor (FET) TP1 and an 
n-channel MOSFET TN1. On the other hand, the charge injecting circuit 23 
comprises p-channel MOSFETs TP2 through TP5, n-channel MOSFETs TN2 through 
TN5, and an inverter 39. In FIG. 8, V.sub.DD denotes a power source 
voltage, V.sub.CK denotes a clock signal, and V.sub.S denotes a reference 
voltage to which the input signal (V5) is clamped during the predetermined 
time period thereof. 
The input signal (V5) from the signal source 20 shown in FIG. 9(B) is 
passed through the coupling capacitor C2 and is converted into a signal 
(V6) shown in FIG. 9(C) which is amplified in the buffer 30. An output 
signal of the buffer 30 is passed through the sample and hold circuits 31 
and 32, and the signal (V6) during the predetermined time period is 
supplied to an inverting input terminal of the differential amplifier 35 
of the control circuit 33. The output signal of the buffer 30 is also 
supplied to other parts (not shown) of the signal processing circuit 22. 
The sample and hold circuit 31 samples the signal (V6) during a high-level 
period of the clock signal V.sub.CK shown in FIG. 9(A), while the sample 
and hold circuit 32 holds the sampled signal during the high-level period 
of the clock signal V.sub.CK. Hence, a voltage which is sampled during the 
high-level period (for example, CK1) of the clock signal V.sub.CK is 
supplied to the inverting input terminal of the differential amplifier 35 
from a time when the level of the clock signal V.sub.CK falls to a low 
level. 
The differential amplifier 35 is also supplied with the voltage V.sub.S to 
a non-inverting input terminal thereof, and compares the sampled voltage 
from the sample and hold circuit 32 with the reference voltage V.sub.S. A 
voltage V.sub.C shown in FIG. 9(D) which is dependent on a difference 
between the two compared voltages is outputted from the differential 
amplifier 35. This voltage V.sub.C is supplied to first and second 
voltage-to-current converting circuits, where the first voltage-to-current 
converting circuit comprises the operational amplifier 36, the p-channel 
MOSFET TP1 and the resistor R.sub.N and the second voltage-to-current 
converting circuit comprises the operational amplifier 37, the n-channel 
transistor TN1 and the resistor R.sub.P. The first voltage-to-current 
converting circuit converts the voltage V.sub.C into a current I.sub.RN 
shown in FIG. 9(E) while the second voltage-to-current converting circuit 
converts the voltage V.sub.C into a current I.sub.RP shown in FIG. 9(F). 
One of the currents I.sub.RP and I.sub.RN flows depending on whether the 
voltage V6 during the predetermined time period is greater than or less 
than the reference voltage V.sub.S. When the reference voltage V.sub.S is 
greater than the voltage V6 during the predetermined time period and the 
voltage V.sub.C is greater than zero, it is necessary to raise the voltage 
level of the voltage V6 at the node N. In this case, the operational 
amplifier 37 and the n-channel MOSFET TN1 cooperate so that the two inputs 
of the operational amplifier 37 become the same, and a current V.sub.C 
/R.sub.P flows through the resistor R.sub.P. On the other hand, when the 
reference voltage V.sub.S is less than the voltage V6 during the 
predetermined time period and the voltage V.sub.C is less than zero, it is 
necessary to lower the voltage level of the voltage V6 at the node N. 
Thus, in this case, the operational amplifier 36 and the p-channel MOSFET 
TP1 cooperate so that the two inputs of the operational amplifier 36 
become the same, and a current - V.sub.C /R.sub.N flows through the 
resistor R.sub.N. Therefore, the current I.sub.RN is -V.sub.C /R.sub.N 
when the voltage V.sub.C is less than or equal to zero, and is zero when 
the voltage V.sub.C is greater than zero. The current I.sub.RP is V.sub.C 
/R.sub.P when the voltage V.sub.C is greater than or equal to zero, and is 
zero when the voltage V.sub.C is less than zero. 
The current I.sub.RP is applied to the MOSFET TP2 of the charge injecting 
circuit 23 to generate a voltage drop at the MOSFET TP2. The voltage drop 
generated at the MOSFET TP2 is applied to a gate of the MOSFET TP5 during 
a time period in which the MOSFET TN3 is turned ON responsive to the 
high-level period of the clock signal V.sub.CK. The voltage V6 at the node 
N is raised by a current which flows through this MOSFET TP5. On the other 
hand, the current I.sub.RN is applied to the MOSFET TN2 of the charge 
injecting circuit 23 to generate a voltage drop at the MOSFET TN2. The 
voltage drop generated at the MOSFET TN2 is applied to a gate of the 
MOSFET TN5 during a time period in which the MOSFET TP4 is turned ON 
responsive to the high-level period of the clock signal V.sub.CK. The 
voltage V6 at the node N is lowered by a current which flows through this 
MOSFET TN5. 
The charge injecting circuit 23 has the construction shown in FIG. 8 for 
the following reasons. That is, the currents I.sub.RN and I.sub.RP can be 
controlled by appropriately selecting the circuit constants of the part of 
the signal processing circuit 22 shown in FIG. 8. The gate voltages of the 
MOSFETs TP2 and TN2 can thus be controlled. Hence, when identical 
transistors are used for the MOSFETs TP2 and TP5, the gate voltage of the 
MOSFET TP2 becomes the gate voltage of the MOSFET TP5 when the MOSFET TN3 
is turned ON, and it becomes possible to control the current which flows 
through the MOSFET TP5. The MOSFETs TP3 and TN3 cooperate so that the 
positive charge is injected to the node N only during the predetermined 
time period of the input signal. The positive charge is injected when the 
MOSFET TN3 is ON and is not injected when the MOSFET TP3 is ON. 
Similarly, when identical transistors are used for the MOSFETs TN2 and TN5, 
the gate voltage of the MOSFET TN2 becomes the gate voltage of the MOSFET 
TN5 when the MOSFET TP4 is turned ON, and it becomes possible to control 
the current which flows through the MOSFET TN5. The MOSFETs TP4 and TN4 
cooperate so that the negative charge is injected to the node only during 
the predetermined time period of the input signal. The negative charge is 
injected when the MOSFET TP4 is ON and is not injected when the MOSFET TN4 
is ON. 
In FIG. 9(A), the voltage V6 is less than the reference voltage V.sub.S 
during the high-level period CK1 of the clock signal V.sub.CK, the voltage 
V6 is greater than the reference voltage V.sub.S during a high-level 
period CK2, and the voltage V6 is equal to the reference voltage V.sub.S 
during a high-level period CK3. Hence, as shown in FIG. 10, the positive 
charge is injected during the high-level period CK2, the negative charge 
is injected during the high-level period CK3, and no charge is injected 
during a high-level period CK4. 
The characteristic of the MOSFET TP5 can be described by I.sub.DP 
=.beta..sub.P (V.sub.GSP -V.sub.thP).sup.2, where .beta..sub.P denotes a 
constant, I.sub.DP denotes a drain current of the MOSFET TP5, V.sub.GSP 
denotes a gate-source voltage of the MOSFET TP5, and V.sub.thP denotes a 
threshold voltage of the MOSFET TP5. Similarly, the characteristic of the 
MOSFET TN5 can be described by I.sub.DN =.beta..sub.N (V.sub.GSN 
-V.sub.thN).sup.2, where .beta..sub.N denotes a constant, I.sub.DN denotes 
a drain current of the MOSFET TN5, V.sub.GSN denotes a gate-source voltage 
of the MOSFET TN5, and V.sub.thN denotes a threshold voltage of the MOSFET 
TN5. 
Therefore, the quantity q.sub.P of positive charge which is injected to the 
node N may be described by the following formula (1), where V.sub.A1 
denotes a voltage at a node N1 applied with the current I.sub.RP and 
.DELTA.t1 denotes a pulse width of the clock signal V.sub.CK applied to 
the MOSFETs TP3 and TN3. 
EQU q.sub.P =.beta..sub.P (V.sub.DD -V.sub.A1 -V.sub.thP)..DELTA.t1 (1) 
The quantity q.sub.N of negative charge which is injected to the node N may 
be described by the following formula (2), where V.sub.A2 denotes a 
voltage at a node N2 applied with the current I.sub.RN and .DELTA.t2 
denotes a pulse width of the inverted clock signal V.sub.CK applied to the 
MOSFETs TP4 and TN4. 
EQU q.sub.N =.beta..sub.N (V.sub.DD -V.sub.A2 -V.sub.thN)..DELTA.t2(2) 
FIGS. 10(A) and 10(B) show the timings of the clock signal V.sub.CK and the 
inverted clock signal V.sub.CK, respectively. 
It may be seen from the formulas (1) and (2) that the quantity q.sub.P of 
positive charge which is injected to the node N may be controlled by 
varying V.sub.A1 and .DELTA.t1, and the quantity q.sub.N of negative 
charge which is injected to the node N may be controlled by varying 
V.sub.A2 and .DELTA.t2. For this reason, the positive or negative charge 
is injected to the node N during the predetermined time period of the 
input signal until the predetermined voltage, that is, the reference 
voltage V.sub.S, is reached, and the D.C. voltage level at the node N can 
be set with a high accuracy. 
Next, a description will be given on a second embodiment of the voltage 
level setting circuit according to the present invention. FIG. 11 shows an 
essential part of the second embodiment. In FIG. 11, those parts which are 
the same as those corresponding parts in FIG. 6 are designated by the same 
reference numerals, and a description thereof will be omitted. 
In FIG. 11, a charge injecting circuit 43 comprises switching circuits S2 
through S7 and capacitors C7 through C9. V.sub.B1 and V.sub.B2 denote 
mutually different constant voltages, where V.sub.B1 &gt;V.sub.B2. 
A description will be given on the case where the capacitor C7 is charged. 
In this case, the switching circuit S2 is first connected to a terminal q1 
as shown in FIG. 12(A) and the switching circuit S3 is connected to a 
terminal t1 as shown in FIG. 12(B) so as to initially discharge the 
capacitor C7. Then, the switching circuit S3 is connected to a terminal r1 
as shown in FIG. 12(B) and the switching circuit S2 is thereafter 
connected to a terminal pl as shown in FIG. 12(A). Accordingly, a quantity 
Q1 of positive charge described by the following is injected to the node 
N, where C7 denotes the capacitance of the capacitor C7 and V.sub.0 
denotes the output voltage of the charge injecting circuit 43. 
##EQU1## 
On the other hand, in the case where the switching circuit S2 is connected 
to the terminal p1, the switching circuit S3 is then connected to the 
terminal r1 and the switching circuit S2 is thereafter connected to the 
terminal q1 as shown in FIGS. 12(A) and 12(B), it is possible to inject a 
quantity Q2 of negative charge identical to the quantity Q1 of positive 
charge described before. 
##EQU2## 
When V.sub.B2 is set approximately equal to V.sub.0, it is possible to 
determine the quantity of charge which is injected by the voltages 
V.sub.B1 and V.sub.B2 and the capacitance of the capacitor C7. 
In FIG. 11, it is possible to set the capacitances of the three capacitors 
C7 through C9 so 
that C7=2.times.C8=2.sup.2 .times.C9, where the capacitances of the 
capacitors are denoted by the same designation of the capacitors. In this 
case, the switching circuits S2 through S7 can be controlled by a control 
circuit (not shown) of the signal processing circuit 22, for example, so 
as to switch and select specific ones of the capacitances C7 through C9, 
and it is possible to select from fifteen different quantities of charges 
depending on the selection. That is, seven different quantities of 
positive charges, seven different quantities of negative charges and one 
quantity of charge which is injected by non-selection of the capacitances 
C7 through C9 can be selected. 
Accordingly, it is possible to inject the positive or negative charge to 
the node N during the predetermined time period corresponding to the 
reference portion of the input signal, and the D.C. voltage level at the 
node N can be set with a high accuracy. In FIG. 11, only three capacitors 
C7 through C9 are provided, but it is possible to provide an arbitrary 
number of capacitors according to the needs. 
FIG. 13 shows an embodiment of the switching circuit which may be used for 
the switching circuits S2 through S7. The switching circuit has a 
complementary MOS (CMOS) structure and comprises an inverter 45 and 
transmission gates 46 and 47 which are connected as shown. A control 
signal for controlling the switching of the switching circuit is applied 
to a terminal 49. This control signal may be obtained from the signal 
processing circuit 22. A signal applied to a terminal 50 is supplied to an 
arbitrary terminal p.sub.i out of the terminals p1 through p3 or to an 
arbitrary terminal r.sub.i out of the terminals r1 through r3 in FIG. 11. 
A signal applied to a terminal 51 is supplied to an arbitrary terminal 
q.sub.i out of the terminals q1 through q3 or to an arbitrary terminal 
t.sub.i out of the terminals t1 through t3 in FIG. 11. A terminal 52 is 
connected to an arbitrary capacitor Ci out of the capacitors C7 through C9 
in FIG. 11. The terminal 50 or 51 becomes connected to the terminal 52 
responsive to the voltage level of the control signal applied to the 
terminal 49. 
FIG. 14 shows a signal processing circuit system employing a third 
embodiment of the voltage level setting circuit according to the present 
invention. In FIG. 14, those parts which are the same as those 
corresponding parts in FIG. 6 are designated by the same reference 
numerals, and a description thereof will be omitted. In the present 
embodiment, a switching circuit S8 is additionally provided and connected 
to a bias voltage source for supplying a bias voltage V.sub.BX. It is 
possible to use the charge injecting circuit 43 in place of the charge 
injecting circuit 23. 
When a reference portion of the input signal (V5) shown in FIG. 15(A) is 
obtained at the node N, the switching circuit S8 is turned ON by a control 
circuit (not shown) so as to supply the bias voltage V.sub.BX to the node 
N. As a result, the voltage (V6) at the node N, that is, the terminal 
voltage of the coupling capacitor C2, is set to the bias voltage V.sub.BX 
during the predetermined time period of the input signal (V5) as shown in 
FIG. 15(B), but an offset voltage is included due to the clock signal 
feedthrough generated when the switching circuit S8 is turned OFF. In 
other words, the voltage (V6) at the node N during the predetermined time 
period is slightly different from the bias voltage V.sub.BX. When the next 
reference portion of the input signal (V5) is obtained at the node N, the 
charge injecting circuit 23 injects a quantity of charge to the node N 
thereby setting the voltage (V6) at the node N to the bias voltage 
V.sub.BX. 
According to the present embodiment, the injection of charge by the charge 
injecting circuit 23 can be adjusted quickly and carried out accurately, 
because the node N is first set to a voltage close to the reference 
voltage level (V.sub.BX) by the bias voltage source. 
According to the first through third embodiments described heretofore, it 
is possible to set the D.C. voltage level at the node N during the 
predetermined time period of the input signal with a high accuracy because 
the embodiments use a feedback from the signal processing circuit 22, 
while the conventional circuits shown in FIGS. 1, 2 and 4 do not. However, 
in these embodiments, an A/D converter (not shown) of the signal 
processing circuit 22 is not included in a feedback loop, and for this 
reason, it is impossible to eliminate an offset voltage generated from the 
A/D converter. Hence, a description will be given hereunder on embodiments 
which can also eliminate the offset voltage generated from the A/D 
converter of the signal processing circuit. 
In the embodiments described hereunder, the voltage level of the reference 
portion of the input signal is set, that is, the clamping voltage is set, 
by use of an output digital signal of the signal processing circuit. In 
other words, the output digital signal of the signal processing circuit is 
compared with a digital code which corresponds to a reference voltage 
level, and a digital error signal obtained by the comparison is converted 
into an analog voltage. This analog voltage is added to or subtracted from 
the input signal during the predetermined time period of the input signal. 
The clamping voltage is corrected until the digital error signal becomes 
zero. Therefore, a feedback loop includes the A/D converter of the signal 
processing circuit, and it is possible to eliminate the offset voltage 
generated in the signal processing circuit. Furthermore, since digital 
signals are compared, it is possible to compress an offset voltage 
generated in the comparing part. 
FIG. 16 shows a signal processing circuit system employing a fourth 
embodiment of the voltage level setting circuit according to the present 
invention. In FIG. 16, those parts which are basically the same as those 
corresponding parts in FIG. 14 are designated by the same reference 
numerals, and a description thereof will be omitted. In FIG. 16, a signal 
processing circuit 62 comprises an analog-to-digital (A/D) converter 64, a 
digital adder 65, a portion of a digital-to-analog (D/A) converter 66 and 
the like. A charge injecting circuit 63 comprises a remaining portion of 
the D/A converter 66 and an integrator 67. An analog adder 68 adds the 
input signal received through the coupling capacitor C2 and an output 
signal of the charge injecting circuit 63, and supplies an added signal to 
the signal processing circuit 62. 
The digital adder 65 compares a digital output signal of the A/D converter 
64 having a voltage level V12 with a digital code corresponding to the 
reference voltage level, and outputs a digital error signal dependent on a 
voltage difference between the two compared values. The digital error 
signal is converted into an analog voltage in the D/A converter 66, and is 
integrated in the integrator 67. An output signal of the integrator 67 is 
supplied to the analog adder 68 and is added with the input signal 
obtained through the coupling capacitor C2. Accordingly, during the 
predetermined time period of the input signal which has a voltage level 
V10 at the terminal 21, a voltage level V11 at the node is set to the bias 
voltage V.sub.BX or at least to a voltage close to V.sub.BX by the 
operation of the switching circuit S8, and the voltage during the 
predetermined time period can be set accurately and quickly to the 
reference voltage level (V.sub.BX) by the feedback loop which includes the 
A/D converter 64 of the signal processing circuit 62. 
FIG. 17 shows the circuit construction of the fourth embodiment. The signal 
processing circuit 62 comprises a buffer 71 for amplifying the voltage 
level V11 of the input signal at the node N, an A/D converter 72 for 
converting an output voltage of the buffer 71 into an m-bit digital signal 
corresponding to the voltage level V12, an inverter 73 for inverting the 
m-bit digital signal to produce a complementary digital signal, a digital 
adder 74 for adding the complementary digital signal and an m-bit digital 
code corresponding to the reference voltage level of the input signal, and 
a control circuit 75 supplied with bits X.sub.0 through X.sub.m-1 of an 
output digital error signal of the digital adder 74. The digital error 
signal indicates a difference between the digital values of the 
complementary digital signal and the digital code. The control circuit 75 
is also supplied with a clock signal CLKl. The control circuit 75 
generates various control signals for controlling switching circuits which 
will be described hereunder. 
On the other hand, the charge injecting circuit 63 comprises switching 
circuits SW.sub.0 through SW.sub.m-1, S.sub.R and S.sub.J, and capacitors 
CA.sub.0 through CA.sub.m-1. The D/A converter 66 shown in FIG. 16 is 
substantially constituted by the control circuit 75, the switching 
circuits SW.sub.0 through SW.sub.m-1, S.sub.R and S.sub.J, and the 
capacitors CA.sub.0 through CA.sub.m-1. In FIG. 17, the functions of the 
integrator 67 and the analog adder shown in FIG. 16 are essentially 
carried out by the provision of the coupling capacitor C2. 
The control circuit 75 generates control signals Y.sub.S, Y.sub.R, Y.sub.J 
and Y.sub.0 through Y.sub.m-1 responsive to the clock signal CLK1 and the 
output digital error signal of the digital adder 74. The control signals 
Y.sub.S, Y.sub.R and Y.sub.J control the ON/OFF state of the switching 
circuits S8, S.sub.R and S.sub.J, respectively. The control signals 
Y.sub.0 through Y.sub.m-1 control the ON/OFF state of the switching 
circuits SW.sub.0 through SW.sub.m-1, respectively. 
FIG. 18 shows an essential part of a control circuit of the circuit 75 
shown in FIG. 17. The circuit shown in FIG. 18 generates the control 
signals Y.sub.0 through Y.sub.m-1 for controlling the switching circuits 
SW.sub.0 through SW.sub.m-1. A digital signal X.sub.i from the digital 
adder 74 is applied to a terminal 77, and is latched in a latch circuit 76 
with a timing controlled by the clock signal CLKl from a terminal 79. A 
latched signal from the latch circuit 76 is outputted through a terminal 
78 and is supplied to a corresponding one of the switching circuits 
SW.sub.0 through SW.sub.m-1 as a control signal Y.sub.i. Although not 
shown, a circuit also generates the control signals Y.sub.S, Y.sub.R and 
Y.sub.J for the switching circuits S8, S.sub.R and S.sub.J in synchronism 
with the clock signal CLK1. 
The capacitors CA.sub.0 through CA.sub.m-1 are used for storing the charge, 
and a relation CA.sub.k =2.sup.k .times.CA.sub.0 stands among the 
capacitances of the capacitors CA.sub.0 through CA.sub.m-1, where k is 
greater than or equal to one but less than or equal to m-1 and the 
capacitances of the capacitors are denoted by the same designation of the 
capacitors. V.sub.B1 and V.sub.B2 denote mutually different reference 
voltages. Accordingly, when the switching circuit SW.sub.i is switched 
from the voltage V.sub.B1 and connected to the voltage V.sub.B2 in a state 
where the switching circuit S.sub.J is ON (closed) and the switching 
circuit S.sub.R is OFF (open), it is possible to inject a quantity Q.sub.i 
of charge to the node N through the capacitor CA.sub.i, where Q.sub.i 
=2.sup.i .times.CA.sub.0 .times.(V.sub.B2 -B.sub.B1). The switching of the 
switching circuit SW.sub.m-1 of corresponding to a most significant bit 
(MSB) of the output digital signal of the digital adder 74 is carried out 
in reverse to the other switching circuits SW.sub.0 through SW.sub.m-2. 
For example, when the control signal Y.sub.i for controlling the switching 
circuit SW.sub.i is "1" (high), the switching circuit SW.sub.i is 
connected to the voltage V.sub.B2, but the switching circuit SW.sub.m-1 is 
connected to the voltage V.sub.B1. The switching of the switching circuit 
SW.sub.m-1 is reversed because the MSB is described by a complementary 
number for calculation's sake. 
The switching circuit having the CMOS structure shown in FIG. 13 described 
before may be used for the switching circuits SW.sub.0 through SW.sub.m-1. 
In this case, the terminals 50 and 51 are respectively connected to the 
voltages V.sub.B1 and V.sub.B2, and the terminal 52 is connected to the 
capacitor CA.sub.i. When the control signal Y.sub.i applied to the 
terminal 49 is "1", the terminal of the capacitor CA.sub.i becomes 
connected to the voltage V.sub.B2. On the other hand, the terminal of the 
capacitor CA.sub.i becomes connected to the voltage V.sub.B1 when the 
control signal Y.sub.i applied to the terminal 49 is "0" (low). 
As in the case of the third embodiment described before, the switching 
circuit S8 in FIG. 17 causes the reference portion of the input signal at 
the node N to be clamped to the bias voltage V.sub.BX during the 
predetermined time period of the input signal. The switching circuit 
S.sub.R is used to appropriately set the terminal voltage of the capacitor 
CA.sub.i to the bias voltage V.sub.BX, and it is possible to thereby 
accurately inject a quantity of charge to the node N through the capacitor 
CA.sub.i. For example, the bias voltage V.sub.BX is set equal to the 
voltage V.sub.B1. In this case, the switching circuit S.sub.R is first 
turned ON to set the terminal voltage of the capacitor CA.sub.i to the 
bias voltage V.sub.BX, and the switching circuit SW.sub.i is then switched 
over and connected to the voltage V.sub.B1. Hence, the charge stored in 
the capacitor CA.sub.i becomes zero and assumes a reset state. Next, when 
the switching circuit S8 is turned ON to disconnect the terminal of the 
capacitor CA.sub.i from the bias voltage V.sub.BX and the switching 
circuit SW.sub.i is thereafter switched over and connected to the voltage 
V.sub.B2, a quantity Q.sub.i of charge is injected to the node N, where 
Q.sub.i =CA.sub.i .times.(V.sub.B2 -V.sub.B1). The charge injected by the 
capacitor CA.sub.m-1 is CA.sub.m-1 .times.(V.sub.B1 -V.sub.B2). 
The switching circuit S.sub.J is used to appropriately connect the terminal 
of the capacitor CA.sub.i to the coupling capacitor C2, that is, the node 
N. Thus, the quantity Q.sub.i of charge stored in the capacitor CA.sub.i 
is injected to the terminal of the coupling capacitor C2, that is, to the 
node N. Therefore, the voltage change at the node due to the injection of 
the charge is CA.sub.i /C2.times.(V.sub.B2 -V.sub.B1) or CA.sub.m-1 
/C2.times.(V.sub.B1 -V.sub.B2). 
Next, a description will be given on the operation of the circuit shown in 
FIG. 17 by referring to FIGS. 19(A) through 19(F). When the reference 
portion of the input signal (V10) is received at the terminal 21, the 
control circuit 75 outputs the control signal Y.sub.S to turn the 
switching circuit S8 ON. In this state, the switching circuit S.sub.R is 
ON responsive to the control signal Y.sub.R and the switching circuit 
S.sub.J is OFF responsive to the control signal Y.sub.J. As a result, the 
reference portion of the input signal (V11) is clamped to a voltage 
extremely close to the bias voltage V.sub.BX. 
Then, the signals X.sub.0 through X.sub.m-1 indicative of the voltage 
difference between the next reference portion of the input signal (V10) 
and the reference voltage level are outputted from the digital adder 74. 
The control circuit 75 generates the control signals Y.sub.S, Y.sub.R, 
Y.sub.J and Y.sub.0 through Y.sub.m-1 based on the signals X.sub.0 through 
X.sub.m-1 and the clock signal CLK1. Hence, the switching circuit S.sub.R 
is first turned ON responsive to the control signal Y.sub.R, and the 
connecting terminals of the switching circuits SW.sub.0 through SW.sub.m-1 
are thereafter changed depending on the control signals Y.sub.0 through 
Y.sub.m-1. Consequently, the quantity Q.sub.i of charge is injected 
through the capacitor CA.sub.i, and the total charge is stored at one 
terminal of the capacitor CA.sub.i. Next, the control signal Y.sub.J 
controls the switching circuit S.sub.J so that the charge is injected to 
the coupling capacitor C2, that is, to the node N. For this reason, the 
reference portion of the input signal (V11) changes and is clamped to the 
reference voltage level (predetermined voltage). 
When receiving the portion other than the reference portion of the input 
signal (V10), that is, the picture information portion, the switching 
circuits S8 and S.sub.J are turned OFF. As a result, the input signal is 
converted into an appropriate signal in which the reference portion is 
appropriately clamped to the reference voltage level. 
The circuit construction of charge injecting circuit 63 is of course not 
limited to that shown in FIG. 17, and for example, it is possible to use 
the charge injecting circuits employed in the first through third 
embodiments described before. 
The concept of setting the reference voltage of the input signal, that is, 
setting the clamping voltage, by use of an output digital signal of the 
signal processing circuit can also be applied to a case where no 
capacitive coupling is provided between the signal source circuit system 
and the signal processing circuit system. A description will now be given 
on a fifth embodiment of the voltage level setting circuit according to 
the present invention in which no capacitive coupling is provided between 
the signal source circuit system and the signal processing circuit system, 
by referring to FIG. 20. 
In FIG. 20, an input signal such as an image signal is obtained from a 
signal source 80 of the signal source circuit system and is applied to a 
terminal 81 as a voltage V20. The input signal (V20) is supplied to an 
analog adder 82, and an output signal (V21) of the analog adder 82 is 
supplied to an A/D converter 83. An output digital signal (V22) of the A/D 
converter 83 is supplied to a digital adder 84 which is also supplied with 
a digital code corresponding to a reference voltage level. The digital 
adder 84 outputs a digital error voltage dependent on a voltage difference 
between the two compared voltages, and this digital error voltage is 
converted into an analog error voltage responsive to a clock signal CLK2 
in a D/A converter 85. The analog voltage from the D/A converter 85 is 
integrated in an integrator 86 and is supplied to the analog adder 82. The 
A/D converter 83 and the digital comparator 84 constitute an essential 
part of a signal processing circuit 88 related to the voltage level 
setting circuit. On the other hand, the D/A converter 85, the integrator 
86 and the analog adder 82 constitute an essential part of a voltage level 
setting circuit 89. 
FIG. 21 shows the circuit construction of the fifth embodiment shown in 
FIG. 20. In FIG. 21, those parts which are the same as those corresponding 
parts in FIG. 20 are designated by the same reference numerals, and a 
description thereof will be omitted. In FIG. 21, the analog adder 82 and 
the integrator 86 are constituted by operational amplifiers 91 and 92, a 
capacitor C30 and resistors R30 through R32. 
Next, a description will be given on the operation of the circuit shown in 
FIG. 21 by referring to FIGS. 22(A) through 22(E). FIGS. 22(A) and 22(B) 
show the voltage levels of the output signal (V21) of the operational 
amplifier 91 and the output digital signal (V22) of the A/D converter 83, 
respectively. In FIG. 22(B), .DELTA.V denotes the offset voltage. FIG. 
22(C) shows the clock signal CLK2 supplied to the D/A converter 85. FIGS. 
22(D) and 22(E) show the analog error voltage (V23) outputted from the D/A 
converter 85 and an output voltage (V24) of the operational amplifier 92, 
respectively. This output voltage (V24) of the operational amplifier 92 is 
an integrated voltage of the analog error voltage (V23). 
First, the input signal (V20) is applied to a non-inverting input terminal 
of the operational amplifier 91 and is outputted therefrom as the signal 
(V21). This signal (V21) is converted into the digital signal (V22) in the 
A/D converter 83), and the digital signal (V22) is compared with the 
digital code corresponding to the reference voltage level in the digital 
adder 84. When a voltage difference exists between the two compared 
voltages, the digital error voltage indicative of the voltage difference 
is outputted from the digital adder 84. The digital error voltage is 
converted into the analog error voltage in the D/A converter 85 with a 
timing determined by the clock signal CLK2, so that the D/A converter 85 
outputs the analog error voltage (V23) only during the predetermined time 
period corresponding to the reference portion of the input signal (V20). 
As a result, the D/A converter 85 outputs the analog error voltage (V23) 
indicative of the voltage difference between the input signal (V21) and 
the reference voltage level during the predetermined time period of the 
input signal (V20). The analog error voltage (V23) is integrated into the 
voltage (V24) in the operational amplifier 92, and the voltage (V24) is 
applied to an inverting input terminal of the operational amplifier 91. 
Therefore, a feedback is made so that the reference portion of the input 
signal (V21) is set (clamped) to the reference voltage level with a high 
accuracy during the predetermined time period of the input signal (V20). 
For example, in the case where the input signal (V20) is an image signal, 
the predetermined time period corresponds to the synchronizing signal 
period of the image signal. 
According to the present embodiment, circuit parts in which an offset 
voltage may be generated are all included in the feedback loop, so as to 
effectively eliminate the offset voltage. In addition, because the voltage 
level of the reference portion of the input signal is set by comparing a 
digital quantity of the input signal and a digital quantity of the 
reference voltage level, it is possible to eliminate the offset voltage 
which would be generated from the comparator itself in the case where 
analog quantities are compared. Accordingly, it is possible to set the 
clamping voltage with a high accuracy. 
Further, the present invention is not limited to these embodiments, but 
various variations and modifications may be made without departing from 
the scope of the present invention.