Memory device and reference circuit thereof

A device is disclosed that includes memory cells, a reference circuit, and a sensing unit. Each of the memory cells is configured to store bit data. The reference circuit includes reference switches and reference storage units. The reference switches are disposed. A first reference storage unit of the reference storage units is configured to generate a first signal having a first logic state when a first reference switch the reference switches is turned on. A second reference storage unit of the reference storage units is configured to generate a second signal having a second logic state when a second reference switch of the reference switches is turned on. The sensing unit is configured to determine a logic state of the bit data of one of the memory cells according to the first signal and the second signal.

BACKGROUND

Memory devices have been widely utilized in many applications. In various applications, the memory devices include a volatile memory and a non-volatile memory that is applicable for long term data storage. For example, the non-volatile memory includes the non-volatile memory includes an eFuse, an electrically-erasable programmable read-only memory (EEPROM), a flash memory, or a magneto resistive random-access memory (MRAM). A robust reference scheme is required to adequately read data stored in memory cells of the non-volatile memory.

DETAILED DESCRIPTION

FIG. 1is a schematic diagram of an electronic device100in accordance with various embodiment of the present disclosure.

As illustratively shown inFIG. 1, the electronic device100includes a memory array110, a reference circuit120, a sensing unit130, and a selection circuit140. The memory array110includes memory columns111, bit lines BL[1]-BL[m], word lines WL[1]-WL[n], and data lines DL[1]-DL[m], in which n and m are positive integers.

For illustration, the memory columns111are disposed in parallel with each other. Each memory column111includes n memory cells112. Each n memory cells112includes a switch SW and a storage unit112A. The switch SW is coupled to a corresponding one of the word lines WL[1]-WL[n] and a corresponding one of the bit lines BL[1]-BL[m]. The storage unit112A is coupled between the switch SW and a corresponding one of the data lines DL[1]-DL[m]. Each of the storage units112A is configured to store bit data.

The reference circuit120is disposed at a side of the memory array110. The reference circuit120includes reference switches RSW, a reference storage unit122, a reference storage unit123, reference bit lines RBL[1]-RBL[2], and reference data lines RDL[1]-RDL[2]. The reference switches RSW are disposed in rows and columns. For illustration, the reference switches RSW are arranged in two columns121A and121B. First terminals of the reference switches RSW in the column121A are coupled to the reference bit line RBL[1], second terminals of the reference switches RSW in the column121A are coupled to the reference data line RDL[1], and control terminals of the reference switches RSW in the column121A are coupled to the word lines WL[1]-WL[n], respectively. The reference storage unit122is coupled between the reference data line RDL[1] and the sensing unit130, and configured to store bit data having a logic high state. Accordingly, when one of the reference switches RSW in the column121A is turned on, the reference storage unit122is then biased to transmit the signal I1having the logic high state according to the stored bit data. First terminals of the reference switches RSW in the column121B are coupled to the reference bit line RBL[2], second terminals of the reference switches RSW in the column121B are coupled to the reference data line RDL[2], and control terminals of the reference switches RSW in the column121B are coupled to the word lines WL[1]-WL[n], respectively. The reference storage unit123is coupled between the reference data line RDL[2] and the sensing unit130, and configured to store bit data having a logic low state. Accordingly, when one of the reference switches RSW in the column121B is turned on, the reference storage unit123is then biased to generated signal I2having the logic low state according to the stored bit data.

In some embodiments, the storage units112A, the reference storage unit122and the reference storage unit123are implemented with non-volatile memory devices. In further embodiments, the non-volatile memory devices include resistive random-access memory (RRAM) device. The resistance of the RRAM device is able to be adjusted to present the bit data having the logic high state or the logic low state. In some other embodiments, the non-volatile memory devices include magnetic tunnel junction (MTJ) devices. The magneto resistance of the MTJ device is able to be adjusted to present the bit data having the logic high state or the logic low state.

The implementations of the storage units112A, the reference storage unit122and the reference storage unit123are given for illustrative purposes only. Various implementations of the storage units112A, the reference storage unit122and the reference storage unit123are within the contemplated scope of the present disclosure.

In some embodiments illustrated inFIG. 1, during a read operation, a corresponding one of the word lines WL[1]-WL[n] is activated. Accordingly, two reference switches RSW in the columns121A and121B, which are coupled to the activated one of the word lines WL[1]-WL[n], are turned on. The reference storage unit122then generates the signal I1to the sensing unit130, and the reference storage unit123then generates the signal I2to the sensing unit130. As a result, the sensing unit130is able to determine a logic state of the bit data of the selected one of the n memory cells112according to the signals I1and I2. The detailed operations are described below with reference toFIG. 2.

Furthermore, the selection circuit140includes switches SEL[1]-SEL[m]. First terminals of the switches SEL[1]-SEL[m] are coupled to the data lines DL[1]-DL[m], respectively, second terminals of the switches SEL[1]-SEL[m] are coupled to the sensing unit130, and control terminals of the switches SEL[1]-SEL[m] are configured to receive selection signals VSE[1]-VSE[m]. During the read operation, one of the switches SEL[1]-SEL[m] is turned on, and one of the word lines WL[1]-WL[n] is activated. Accordingly, the switch SW, which is coupled to the activated one of the word lines WL[1]-WL[n], are turned on by the corresponding one of the selection signals VSE[1]-VSE[m]. A current ICELL, indicating the bit data of the selected one of the n memory cells112, is then transmitted to the sensing unit130. Accordingly, the bit data of the selected memory cell112is able to be determined by the sensing unit130.

The sensing unit130is coupled to the memory array110and the reference circuit120. The sensing unit130is configured to determine the logic state of the bit data of the selected memory cell112according to the signals I1and I2. For illustration, in some embodiments illustrated inFIG. 1, the sensing unit130includes an average current circuit131and a sense amplifier132. Input terminals of the average current circuit131are coupled to the reference storage units122and123to receive the signals I1and I2. A first input terminal of the sense amplifier132is coupled to an output terminal of the average current circuit131to receive a reference signal IREF. A second input terminal of the sense amplifier132is coupled to the switches SEL[1]-SEL[m] to receive the current ICELL. The average current circuit131is configured to average the signals I1and I2to generate the reference signal IREF. The sense amplifier132is configured to compare the reference signal IREF with the current ICELL, in order to determine the logic state of the bit data. In some embodiments, the average current circuit131is implemented with various types of current mirror circuit.

FIG. 2is a flow chart of a method200illustrating operations of the electronic device100inFIG. 1, in accordance with various embodiments of the present disclosure. For illustration, the operations of the device100inFIG. 1are described by the method200with reference toFIG. 2. In some embodiments, the method200includes operations S210-S260.

In operation S210, during a read operation, one of the word lines WL[1]-WL[n] is activated, and a corresponding one of the switches SEL[1]-SEL[m] is turned on, in order to select a corresponding one of the memory cells112.

In operation S220, the current ICELL, indicating the bit data of the selected memory cell112, is transmitted from a corresponding one of the data lines DL[1]-DL[m] to the sense amplifier132.

For illustration, as illustrated inFIG. 1, during the read operation, the first word line WL[1] is activated, the switch SEL[1] is turned on by the selection signal VSE[1], and the other switches SEL[2]-SEL[m] are turned off by the selection signals VSE[2]-VSE[m]. Accordingly, the memory cell112(hereinafter the selected memory cell1121) coupled to the word line WL[1] and the data line DL[1] is selected. The switch SW of the selected memory cell1121is then turned on to bias the storage unit112A of the selected memory cell1121. Thus, the current ICELL, which is able to indicate the bit data stored in the storage unit112A, is transmitted from the storage unit112A to the sense amplifier132via the data line DL[1] and the switch SEL[1].

With continued reference toFIG. 2, in operation S230, a corresponding one of the switches RSW in the column121A is turned on to generate the signal I1to the average current circuit131. In operation S240, a corresponding one of the switches RSW in the column121B is turned on to generate the signal I2to the average current circuit131. In operation S250, the average current circuit131averages the sum of the signal I1and the signal I2to generate the reference signal IREF to the sense amplifier132. In operation S260, the sense amplifier132compares the current ICELL with the reference signal IREF, to determine the logic state of the bit data of the selected memory cell1121.

For illustration inFIG. 1, when the word line WL[1] is activated, the reference switches RSW in the columns121A and121B, which are coupled to the word line WL[1], are turned on. Accordingly, the reference storage units122and123are biased by the turn-on reference switches RSW, to generate the signals I1and I2to the average current circuit131. The average current circuit131then averages the signals I1and I2, to generate the reference signal IREF to the sense amplifier132. In other words, the level of the reference signal IREF is about half of a sum of the signals I1and I2. The sense amplifier132then compares the current ICELL with the reference signal IREF, to determine the logic state of the bit data of the selected memory cell1121. For example, when the current ICELL is higher than the reference signal IREF, the bit data of the selected memory cell1121is determined to have the logic high state. Alternatively, when the current ICELL is lower than the reference signal IREF, the bit data of the selected memory cell1121is determined to have the logic low state. Effectively, the bit data of the selected memory cell1121is read by the electronic device100.

The above description includes exemplary operations, but the operations are not necessarily performed in the order described. The order of the operations disclosed in the present disclosure are able to be changed, or the operations are able to be executed simultaneously or partially simultaneously as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure.

In some embodiments, the reference switches RSW and the switch SW in the n memory cells112are configured to have a same feature size. Thus, process/voltage/temperature variations on the memory array110are similar to those on the reference circuit120, and accordingly, the reference circuit120is able to be utilized to detect process/voltage/temperature variations on the memory array110. For illustration, with the arrangements of the switches RSW inFIG. 1, the reference circuit120is able to track the variations of the wire loading of the memory array110, for example, including the bit lines BL[1]-B[m], the switches SW coupled to the bit lines BL[1]-BL[m], data lines DL[1]-DL[m], etc. Thus, the reference signal IREF is able to be generated with the similar variations on the memory array110.

Compared to some approaches using an external fixed reference signal, a more accurate reference signal IREF is generated by the reference circuit120, as illustrated in the embodiments ofFIG. 1.

Moreover, in some other approaches, a reference circuit employs the same architecture of the memory array110. In such approaches, the bit data stored in reference storage units of the reference circuit are varied with each other due to various variations between the reference storage units. As a result, the reference signal generated by the reference circuit in such approaches is inaccurate.

Compared with the approaches described above, as illustrated inFIG. 1, the reference switches RSW in the column121A are coupled to the single reference storage unit122, and the reference switches RSW in the column121B are coupled to the single reference storage unit123. Effectively, the variations between the storage units in the reference circuit120are minimized. As a result, a more accurate reference signal IREF is able to be generated, compared with the aforementioned approaches.

Reference is now made toFIG. 3A.FIG. 3Ais a schematic diagram of the reference storage unit122inFIG. 1having the logic high state, in accordance with various embodiments of the present disclosure.

As described above, in some embodiments, the reference storage units122and123are implemented with the MTJ devices. In some embodiments, the MTJ device includes a free layer and a pinned layer. As illustratively shown inFIG. 3A, the reference storage unit122includes a free layer122A and a pinned layer123B. The free layer122A of the reference storage unit122is coupled to a first terminal of the reference storage unit122, and the pinned layer122B is coupled to a second terminal of the reference storage unit122. In some embodiments, the reference storage unit122is configured to receive a current IT1flowing from its first terminal, i.e., the free layer122A, to its second terminal, i.e., the pinned layer122B. Accordingly, as shown inFIG. 3A, the magnet moment of the free layer122A is anti-parallel to the magnet moment of the pinned layer122B. Under this condition, the reference storage unit122is configured to have a high magneto resistance. Effectively, the reference storage unit122is programmed to have the bit data having the logic high state.

FIG. 3Bis a schematic diagram of the reference storage unit123inFIG. 1having the logic low state, in accordance with various embodiments of the present disclosure. Corresponding to the reference storage unit122, as illustrated in some embodiments inFIG. 3B, the reference storage unit123includes a free layer123A and a pinned layer123B. The free layer123A is coupled to the first terminal of the reference storage unit123. The pinned layer123B is coupled to the second terminal of the reference storage unit123. In some embodiments, the reference storage unit123is configured to receive a current IT2flowing from its second terminal, i.e., the pinned layer123B, to its second terminal, i.e., the free layer123A. Accordingly, as shown inFIG. 3B, the magnet moment of the free layer123A is parallel to the magnet moment of the pinned layer123B. Under this condition, the reference storage unit123is configured to have a low magneto resistance. Effectively, the reference storage unit123is programmed to have the bit data having the logic low state.

With continued reference to both ofFIG. 1,FIG. 3A, andFIG. 3B, in the embodiments illustrated inFIG. 1, the first terminal, i.e., the free layer122A, of the reference storage unit122is coupled to the reference data line RDL[1], and the second terminal, i.e., the pinned layer122B, of the reference storage unit122is coupled to the average current circuit131. Furthermore, the first terminal, i.e., the free layer123A, of the reference storage unit123is coupled to the reference data line RDL[2], and the second terminal, i.e., the pinned layer123B, of the reference storage unit123is coupled to the average current circuit131.

FIG. 4is a schematic diagram of the reference circuit120inFIG. 1, in accordance with some other embodiments of the present disclosure. With respect to the embodiment ofFIG. 1, like elements inFIG. 4are designated with the same reference numbers for ease of understanding. Alternatively, in the embodiments illustrated inFIG. 4, the second terminal, i.e., the pinned layer123B, of the reference storage unit123is coupled to the reference data line RDL[2], and the first terminal, i.e., the free layer123A, of the reference storage unit123is coupled to the average current circuit131. In some embodiments, the arrangement of the reference storage unit123inFIG. 4is achieved in a different layout design.

As illustratively shown inFIG. 4, the current, for the read operation, flows from the pinned layer123B to the free layer123A. As described above inFIG. 3B, the current IT2, for the programming operation of the reference storage unit123, also flows from the pinned layer123B to the free layer123A. In other words, in the embodiments illustrated inFIG. 4, the direction of the current for the read operation is the same as the direction of the current for the programming operation. Accordingly, the operational reliability is able to be further improved, compared with the embodiments illustrated inFIG. 1.

FIG. 5is a schematic diagram of the reference circuit120inFIG. 1, in accordance with some other embodiments of the present disclosure. With respect to the embodiment ofFIG. 1, like elements inFIG. 5are designated with the same reference numbers for ease of understanding.

Compared with the reference circuit120inFIG. 1, in some embodiments illustrated inFIG. 5, the second terminal, i.e., the pinned layer123B, of the reference storage unit123is coupled to the reference bit line RBL[2], and the first terminal, i.e., the free layer123A, of the reference storage unit123is coupled to the second terminals of the reference switches RSW in the column121B. The first terminals of the reference switches RSW in the column121B are coupled to the reference data line RDL[2]. With such arrangements, the direction of the current for the read operation is the same as the direction of the current for the programming operation of the reference storage unit123. As a result, the operational reliability of the electronic device100is further improved.

Reference is now made toFIG. 6.FIG. 6is a schematic diagram of the reference circuit120inFIG. 1, in accordance with still other embodiments of the present disclosure. With respect to the embodiment ofFIG. 1, like elements inFIG. 6are designated with the same reference numbers for ease of understanding.

Compared with the reference circuit120inFIG. 1, in some embodiments illustrated inFIG. 6, the reference circuit120further includes a reference word line RWL, and the reference circuit120only utilizes two reference switches RSW1and RSW2. For illustration, a first terminal of the reference switch RSW1is coupled to the reference bit line RBL[1], a second terminal of the reference switch RSW1is coupled to the first terminal of the reference storage unit122, and a control terminal of the reference switch RSW1is coupled to the reference word line RWL. A first terminal of the reference switch RSW2is coupled to the reference bit line RBL[2], a second terminal of the reference switch RSW2is coupled to the first terminal of the reference storage unit123, and a control terminal of the reference switch RSW2is coupled to the reference word line RWL. Second terminals of the reference switches are configured to transmit the signals I1and I2to the average current circuit131.

In some embodiments, during the read operation, the reference word line RWL and one of the word lines WL[1]-WL[n] are activated at the same time, in order to transmit the current ICELL and the signals I1and I2. Alternatively, in some other embodiments, the reference word line RWL is kept being activated. The operations of the reference circuit120inFIG. 6are similar with the operations illustrated inFIG. 2, and the repetitious descriptions are thus not given here.

The configurations of the reference word line RWL is given for illustrative purposes only. Various configurations of the reference word line RWL are within the contemplated scoped of the present disclosure.

Compared with some approaches employing the same architecture of the memory array as the reference circuit, as discussed above, in the embodiments illustrated inFIG. 6, the variations between the reference storage units in the reference circuit120are minimized. Accordingly, a more accurate reference signal IREF is able to be generated.

Reference is now made to both ofFIG. 3BandFIG. 7.FIG. 7is a schematic diagram of the reference circuit120inFIG. 6, in accordance with various embodiments of the present disclosure. With respect to the embodiment ofFIG. 1, like elements inFIG. 7are designated with the same reference numbers for ease of understanding.

As illustrated inFIG. 3B, the reference storage unit123is able to be implemented with the MTJ device. Compared with the reference circuit120inFIG. 6, in some embodiments illustrated inFIG. 7, the second terminal, i.e. the pinned layer123B inFIG. 3B, of the reference storage unit123is coupled to the second terminal of the reference switch RSW2, and the first terminal, i.e., the free layer123A inFIG. 3B, of the reference storage unit123is coupled to the average current circuit131. As described above, with such arrangements, the direction of the current for the read operation is the same as the direction of the current for the programming operation of the reference storage unit123. As a result, the operational reliability of the electronic device100is further improved.

Reference is now made to both ofFIG. 3BandFIG. 8.FIG. 8is a schematic diagram of the reference circuit120inFIG. 6, in accordance with various embodiments of the present disclosure. With respect to the embodiment ofFIG. 1, like elements inFIG. 8are designated with the same reference numbers for ease of understanding.

Compared with the reference circuit120inFIG. 6, in some embodiments illustrated inFIG. 8, the second terminal, i.e., the pinned layer123B, of the reference storage unit123is coupled to the reference bit line RBL[2], and the first terminal, i.e., the free layer123A, of the reference storage unit123is coupled to the second terminal of the reference switch RSW2. The first terminal of the reference switch RSW2is coupled to the reference data line RDL[2]. With such arrangements, the direction of the current for the read operation is the same as the direction of the current for the programming operation of the reference storage unit123. As a result, the operational reliability of the electronic device100is improved.

As described above, the device100in the present disclosure is able to generate a reference signal to be compared with the bit data. Moreover, with the arrangements of the reference circuit illustrated in various embodiments, a more accurate reference signal is generated. Accordingly, the operational reliability of the memory device is able to be improved.

In this document, the term “coupled” may also be termed as “electrically coupled,” and the term “connected” may be termed as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

In some embodiments, a device is disclosed that includes memory cells, a reference circuit, and a sensing unit. Each of the memory cells is configured to store bit data. The reference circuit includes reference switches and reference storage units. The reference switches are disposed in rows and columns. A first reference storage unit of the reference storage units is configured to generate a first signal having a first logic state when one of the reference switches in a first column is turned on. A second reference storage unit of the reference storage units is configured to generate a second signal having a second logic state when one of the reference switches in a second column is turned on. The sensing unit is configured to determine a logic state of the bit data of one of the memory cells according to the first signal and the second signal.

Also disclosed is a device that includes memory cells, a reference circuit, and a sensing unit. Each of the memory cells is configured to transmit bit data when a corresponding one of word lines is activated. The reference circuit includes a first reference switch, a second reference switch, and reference storage units. The first reference switch is configured to be turned on when a reference word line is activated. The second reference switch is configured to be turned on when the reference word line is activated. The reference storage units include a first reference storage unit and a second reference storage unit. The first reference storage unit is configured to generate a first signal having a first logic state when the first reference switch is turned on. The second reference storage unit is configured to generate a second signal having a second logic state when the second reference switch is turned on. The sensing unit is configured to determine a logic state of the bit data of one of the memory cells according to the first signal and the second signal.

Also disclosed is a method that includes the operation below. A first signal having a first logic state is generated by a first reference storage unit when one of a plurality of the word lines and a reference word line is activated. A second signal having a second logic state is generated by a second reference storage unit when the one of the word lines and the reference word line is activated. A logic state of bit data of one of memory cells is determined by a sensing unit according to the first signal and the second signal, in which the memory cells are coupled to the word lines.