Electrostatic discharge (ESD) tolerance for a lateral double diffusion metal oxide semiconductor (LDMOS) transistor

An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate.

CROSS-REFERENCE OF THE INVENTION

This application claims priority from Japanese Patent Application No. 2010-201584, the content of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor device, specifically to an LDMOS transistor that has an excellent ESD tolerance.

2. Description of the Related Art

The LDMOS transistor, as well as an IGBT, is widely used in a switching power supply such as a DC-DC converter, an inverter circuit of lighting apparatus, an inverter circuit for a motor and the like, because it is excellent in high current drivability, high withstand voltage and switching characteristics, and is easy to use compared with a bipolar type power transistor. The LDMOS is an acronym for Lateral Double Diffusion Metal Oxide Semiconductor. And the ESD is an acronym for Electro-Static Discharge.

A simplified cross-sectional view of the LDMOS transistor is shown inFIG. 12B, for example. The LDMOS transistor shown inFIG. 12Bis structured as an N channel MOS transistor. It is composed of an N type semiconductor layer51, an N− type drift layer52, an N+ type drain layer57, a P type base layer53, an N+ type source layer56, a P+ type contact layer58, a gate insulation film54and a gate electrode55.FIG. 12Ashows a structure formed by removing the P+ type contact layer58from the structure shown inFIG. 12B. Considering the operations of the LDMOS transistor, the structure shown inFIG. 12Ahaving no P+ type contact layer58seems to be sufficient.

However, following problem is caused with the LDMOS transistor having no P+ type contact layer58as shown inFIG. 12A, when the LDMOS transistor is turned on by applying a positive high voltage +Vd to the N+ type drain layer57, grounding the N+ type source layer56, and applying a positive voltage to the gate electrode55. The problem is that a parasitic NPN transistor, which is composed of an emitter made of the N+ type source layer56, a base made of the P type base layer53and a collector made of the N+ type drain layer57and the like, is turned on by the reason to be described below to increase an unnecessary current that can be not controlled by the gate electrode55, when the LDMOS transistor is turned on and an electron current flows from the N+ type source layer56to the N+ type drain layer57.

When the LDMOS transistor is turned on, electrons flow out of the N+ type source layer56into the N− type drift layer52through a channel layer, are accelerated by a high electric field in the N− type drift layer52, and flow into the N+ type drain layer57. In this case, electrons accelerated in the N− type drift layer52are turned into hot electrons having high energy, and interact with lattices and the like in the N− type drift layer52to generate a large number of electron-hole pairs. InFIG. 12A, a circled e−represents the hot electron, and e−and e+represent the electron-hole pair generated by the interaction with the hot electron.

While the electrons generated as described above flow into the N+ type drain layer57, the holes flow toward the N+ type source layer56at the ground electric potential. The holes that reached the N+ type source layer56are blocked by its potential bather and remain dispersed in the P type base layer53around the N+ type source layer56, so that an electric potential at the P type base layer53becomes higher than the electric potential at the N+ type source layer56.

As a result, the parasitic NPN transistor, which is composed of the emitter made of the N+ type source layer56, the base made of the P type base layer53and the collector made of the N+ type drain layer57, is turned on and the electron current flows out of the N+ type source layer56to the P type base layer53, since the electric potential at the P type base layer53that makes the base layer becomes higher than the electric potential at the N+ type source layer56that makes the emitter layer. The electron current that has flown into the P type base layer53further flows into the N+ type drain layer57at the positive voltage +Vd. As a result, there is caused the problem that the unnecessary current which can be not controlled by the gate electrode55is increased.

In the case where the P+ type contact layer58is formed in parallel with the N+ type source layer56and extending into the P type base layer53as shown inFIG. 12B, on the other hand, the structure is impervious to the problem that the parasitic NPN transistor is turned on. The electron-hole pairs are generated in the N− type drain layer52by the hot electrons and the electrons flow into the N+ type drain layer57as in the case of the structure shown inFIG. 12A. However, there is a difference regarding the holes.

Unlike in the structure shown inFIG. 12A, most of holes flowing toward the N+ type source layer56at the ground electric potential flow into the P+ type contact layer58formed in parallel with the N+ type source layer56and extending into the P type base layer53. That is because the P+ type contact layer58does not make the potential barrier against the holes. Therefore, a difference between the electric potential at the N+ type source layer56and the electric potential at the P type base layer53adjacent the N+ type source layer56is decreased to reduce a possibility that the parasitic NPN transistor described above would be turned on.

However, if the parasitic NPN transistor would be not turned on, a dielectric breakdown between the source and the drain would be caused to destroy the LDMOS transistor when a large positive surge voltage due to an ESD extremely larger than a normal power supply voltage is applied to the N+ type drain layer57. The problem and its countermeasure in the case where the large positive surge voltage due to the ESD is applied to the N+ type drain layer57are disclosed in Japanese Patent Application Publication No. 2001-320047.

When the large positive surge voltage due to the ESD is applied to the N+ type drain layer57, an avalanche breakdown occurs in the vicinity of the N+ type drain layer57under a strong electric field so that a large number of electron-hole pairs are generated. The generated electrons flow into the N+ type drain layer57, while the generated holes flow into the P type base layer53.

The electric potential at the P type base layer53is raised above the electric potential at the N+ type source layer56by the holes that flow into the P type base layer53. As a result, the parasitic NPN transistor, which is composed of the emitter made of the N+ type source layer56, the base made of the P type base layer53and the collector made of the N+ type drain layer57and the like, is turned on.

A voltage between the N+ type source layer56and the N+ type drain layer57is clamped at a low voltage and the destruction of the device due to the ESD is prevented by the turning on of the parasitic NPN transistor. However, a localized current convergence occurs in the vicinity of the N+ type drain layer57to cause a thermal runaway in this region.

Thus, sufficient ESD tolerance is not obtained and there is caused a problem in extreme cases that the vicinity of the N+ type drain layer57is destroyed. There is disclosed that an LDMOS transistor with an improved ESD tolerance is realized by forming a P+ type anode layer (not shown) adjacent the N+ type drain layer57.

In the same Japanese publication, the insufficient ESD tolerance is attributed to the thermal runaway due to the localized convergence of the avalanche current in the vicinity of the N+ type drain layer57, and its countermeasure is modification in the drain-side structure. It is taken for granted that the parasitic NPN transistor is turned on. However, the P+ type contact layer58also serves to prevent the parasitic NPN transistor from turning on.

Therefore, it is necessary that the parasitic transistor is turned on when the abnormally large surge voltage is applied, while the parasitic NPN transistor is prevented from turning on in the normal operation. The inventors investigated how the P+ type contact layer58and the N+ type source layer56should be structured to meet the requirements described above.

SUMMARY OF THE INVENTION

The invention provides a semiconductor transistor that includes a semiconductor layer of a first general conductivity type, a drift layer of the first general conductivity type formed in a surface portion of the semiconductor layer, a drain layer of the first general conductivity type formed in a surface portion of the drift layer, a base layer of a second general conductivity type formed in a surface portion of the semiconductor layer apart from the drift layer, a source layer of the first general conductivity type formed in a surface portion of the base layer and comprising a plurality of openings, a contact layer of the second general conductivity type filling each of the openings in the source layer so that there is a distance between an edge of the contact layer and a corresponding edge of the source layer, a gate insulation film covering at least part of the base layer and part of the semiconductor layer, and a gate electrode disposed on the gate insulation film. The distance is larger than or equal to a distance between the edge of the contact layer and the corresponding edge of the source layer at which an ESD tolerance of the transistor begins to saturate.

DETAILED DESCRIPTION OF THE INVENTION

LDMOS transistors according to embodiments of this invention will be explained referring toFIG. 1A-FIG.11C. In one of preferable embodiments, the transistor has the structure shown inFIGS. 3A,3B and3C, wherein a distance X3shown inFIG. 3Bis around 1.5 μm. This invention relates to increasing an area of an N+ type source layer3, which is shaped in a ladder having a plurality of evenly spaced openings7in its center. Specifically, this invention relates to a correlation between a distance X from an edge of the opening7, in which a P+ type contact layer4is buried, to an edge of the N+ type source layer3and an HBM ESD tolerance that increases and eventually saturates as the distance X increases. Therefore, a drain region is omitted from the drawings, and the explanation is given referring to simplified drawings in which a source region is represented by a single N+ type source layer3. The N+ type source layer3is formed in a P type base layer2. Gate electrode5is extended outward from an end portion of the N+ type source layer3on the P type base layer2. It is noted that conductivity types such as N+, N and N− belong in one general conductivity type and conductivity types such as P+, P and P− belong in the other general conductivity type.FIG. 13Ais a schematic plan view showing the LDMOS transistor according to the embodiment of this invention.FIG. 13Bis a cross-sectional view showing a section A-A inFIG. 13A.FIG. 13Bshows drift layer11, drain layer12, gate insulation film13, N type epitaxial layer1, interlayer insulation layer6, P type layer4a, contact groove8and contact groove8a.

The distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is increased from X1to X4in structures shown inFIGS. 1B,2B,3B and4B.FIG. 1Bshows the structure in which the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is X1, that is 0.6 μm to be more specific. A width of the opening7in the N+ type source layer3shown inFIG. 1Bis 1.2 μm, which is common to the structures shown inFIG. 1B,FIG. 2B,FIG. 3BandFIG. 4B.

FIG. 1Ais a plan view showing a source region of a semiconductor device according to a reference example.FIG. 1Bis a cross-sectional view showing a section A-A inFIG. 1A, which includes the opening7in the N+ type source layer3. Boron ions or the like are implanted into the opening7through a contact groove8formed in an interlayer insulation film6to form the P+ type contact layer4.FIG. 1Cis a cross-sectional view showing a section B-B inFIG. 1A. A portion of the N+ type source layer3is exposed in the contact groove8. A P type layer4athat is contiguous to the P+ type contact layer4formed in the opening7is formed under the exposed portion of the N+ source layer3.

FIG. 2Bshows the structure in which the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is X2, that is 1.6 μm to be more specific. Other dimensions including the width of the contact groove8are the same as those in the structure shown inFIG. 1B. Since a total width of the N+ type source layer3in the structure shown inFIG. 2Bis larger by 2 μm than that in the structure shown inFIG. 1B, a current flows more easily in the structure shown in FIG.2B.

In the structure shown inFIG. 3B, the width of the contact groove8formed in the interlayer insulation film6is larger than the width of the opening7in the N+ type source layer3as shown inFIG. 3B, while the distance X3from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is 1.6 μm, that is the same as the distance X2in the structure shown inFIG. 2B.

On the other hand, the structure shown inFIG. 3Bis similar to the structure shown inFIG. 1Bin that a distance from an edge of the contact groove8to the edge of the N+ source layer3is 0.6 μm at each of both edges of the contact groove8.

However, the distance X3from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is 1.6 μm, which is the same as the distance X2in the structure shown inFIG. 2B. Since the width of the opening7in the N+type source layer3and the width of the contact groove8are equal to each other in the structure shown inFIG. 2B, the opening7in the N+ type source layer3is not always completely filled with the P+ type contact layer4due to a misalignment of masks used in photolithography. As a result, there may be caused variation in capability to absorb the holes. In the structure shown inFIG. 3B, on the other hand, the width of the contact groove8, which also serves as a mask in forming the P+ type contact layer4, is larger than the width of the opening7in the N+ type source layer3. Therefore, the opening7in the N+ type source layer3is completely filled with the P+ type contact layer4by implanting boron ions or the like through the contact groove8. In this case, the boron ions or the like are also implanted into a region under the portion of the N+ type source layer3exposed in the contact groove8to form the P type layer4athat is contiguous to the P+ type contact layer4.

FIG. 4Bshows the structure in which the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is X4, that is 2.6 μm to be more specific. The structure shown inFIG. 4Bis the same as the structure shown inFIG. 3Bin that the contact groove8larger than the opening7in the N+ type source layer3is formed in the interlayer insulation film6so as to expose the N+ type source layer3except for an edge region of 0.6 μm at each of both edges.

Next, HBM+ESD tolerances are compared to show how the ESD tolerance of the LDMOS transistor is improved as the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is increased, as shown inFIG. 1B-FIG.4B. The ESD is regarded as a pulse of high energy discharged when a human body or a material body charged with electrostatic charge touches a semiconductor device.

Although there are the HBM (Human Body Model) ESD tolerance and an MM (Machine Model) ESD tolerance as measures to compare the ESD tolerances, the HBM ESD tolerance is used in general. The HBM ESD tolerance is measured with a test circuit shown inFIG. 5, assuming that the human body is a charged body having a capacitance C=100 pF and a resistance R=1.5 kΩ. That is, after a capacitor C of 100 pF is charge by applying a voltage VESD, a switch is turned to the right to discharge the stored charge through a resistor R of 1.5 kΩ as a pulse of the voltage VESD, which is applied to a device under test, as shown inFIG. 5.

HBM+ESD tolerances of the LDMOS transistors each having the structure shown in each ofFIGS. 1B,2B,3B and4B, respectively, are measured with the test circuit described above and are shown inFIGS. 6A,6B,6C,7A and7B. The HBM+ESD tolerance is a breakdown tolerance of the LDMOS transistor when a large positive ESD pulse is applied to an N+ type drain layer (not shown) of the LDMOS transistor.

FIGS. 6A,6B and6C show distributions of the HBM+ESD tolerances corresponding to the structures shown inFIG. 1B,FIG. 3BandFIG. 4B, in which the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is varied.FIG. 6Ashows a distribution of the HBM+ESD tolerances of the structure shown inFIG. 1B, in which the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is 0.6 μm. An average value of the distribution is as low as 1,330V.

On the other hand,FIG. 6Bshows a distribution of the HBM+ESD tolerances of the structure shown inFIG. 3B, in which the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is 1.6 μm. The average value of the distribution is improved to 2,143V. WhileFIG. 6Bcorresponds to the structure shown inFIG. 3B,FIGS. 7A and 7Bshow comparison between the HBM+ESD tolerances of the structures shown inFIGS. 2B and 3B.

FIG. 7BandFIG. 6Bcorrespond to the same sample that has the structure shown inFIG. 3B.FIG. 7Acorresponds to the structure shown inFIG. 2B. Although there is a difference of about 60V between the two distributions, it is within a range of variations and the HBM+ESD tolerances of the both structures are regarded as approximately equal to each other.

FIG. 6Cshows a distribution of the HBM+ESD tolerances of the structure shown inFIG. 4B, in which the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is 2.6 μm. Although the distribution shown inFIG. 6Cis about 30V lower than the distribution shown inFIG. 6B, the difference is considered to be within a range of variations.

From the HBM+ESD tolerances shown inFIG. 6A-FIG.6C, it appears that the HBM+ESD tolerance does not keep increasing but becomes saturated to a predetermined level when the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is increased beyond a predetermined distance.

FIG. 8shows a correlation between the HBM+ESD tolerance represented by the vertical axis and the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3represented by the horizontal axis, which is derived from the data shown inFIG. 6A-FIG.6C,FIG. 7AandFIG. 7B. It is understood fromFIG. 8that the LDMOS transistor according to the embodiment of this invention having the maximum HBM+ESD tolerance of about 2,100V can be realized by designing so that the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is around 1.5 μm.

A mark X at a location where the distance X is 1.6 μm inFIG. 8represents the average HBM+ESD tolerance of a structure formed by modifying the plurality of openings7in the N+ type source layer3in the structure shown inFIG. 3Ainto a single stripe of opening groove9as shown inFIG. 9A. A distribution of the HBM+ESD tolerances in this case is shown inFIG. 10B. Compared with the distribution of the HBM+ESD tolerances shown inFIG. 10C, which corresponds to the structure shown inFIG. 3B,FIG. 10Bshows that the HBM+ESD tolerances are distributed to lower side and disadvantageous, although its average value of about 2,000V is reasonably good.

FIG. 11Bshows a structure of an LDMOS transistor that differs from the structure shown inFIG. 3Bin that the opening7is enlarged to have the same width as the contact groove8. The distance X from the edge of the opening7in the N+ type source layer3, in which the P+ type contact layer4is formed, to the edge of the N+ type source layer3is reduced to 0.6 μm which is the same as that in the structure shown inFIG. 1B. As a result, the HBM+ESD tolerance becomes lower than the average value of the HBM+ESD tolerances shown inFIG. 10Cof the structure shown inFIG. 3Bby nearly 600V, as shown inFIG. 10A.

The reason why the HBM+ESD tolerance is increased as the distance X from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3is increased will be explained below Increasing the distance X as shown inFIG. 3Bor the like compared with that inFIG. 1Bmeans increasing an area of the source and allowing the current flow more easily through the source layer3in the structure shown inFIG. 3Bor the like than in the structure shown inFIG. 1B. When the distance X is increased, a large amount of holes that are generated by an avalanche breakdown caused by an abnormally high surge voltage due to the HBM+ESD and gathered around the N+ type source layer3may not be absorbed instantaneously by the P+ type contact layer4.

Or, since the large amount of holes flow into the P+ type contact layer4, there is caused an electric potential gradient in the P type base layer2under the N+ type source layer3, which serves as a path for the holes. Thus, a PN junction formed of the N+ type source layer3and the P type base layer2is forward biased. As a result, the parasitic NPN transistor, which is composed of the emitter made of the N+ type source layer3, the base made of the P type base layer2and the collector made of the N+ type drain layer, is turned.

Once the parasitic NPN transistor is turned on at a portion of the N+ type source layer3, the ON state of the parasitic NPN transistor spreads all over the N+ type source layer3that is laterally extended to provide a broad current path, so that a large amount of surge current is allowed to flow into the ground line rapidly. As a result, the LDMOS transistor is protected against the surge voltage due to the HBM+ESD. Therefore, it is made possible to secure the high HBM+ESD tolerance.

In the case where the distance X is as short as 0.6 μm as shown inFIG. 1B, on the other hand, the parasitic NPN transistor is not easily turned on because most of the large amount of holes generated by the avalanche breakdown is absorbed instantaneously by the P+ type contact layer4. Even if the parasitic NPN transistor is turned on at a portion of the N+ type source layer3, the parasitic NPN transistor never turns on over the entire N+ type source layer3since the area of the N+ type source layer3is small. Therefore, the HBM+ESD tolerance is compelled to be reduced.

The ON state of the parasitic NPN transistor can be confirmed by a TLP (Transmission Line Pulse) method, in which a pulse voltage of a certain width is applied and a response to it is observed. When the parasitic NPN transistor is turned on at a certain location, the location emits light that can be observed with an emission microscope.

In the case where the distance X is as small as 0.6 μm as shown inFIG. 1B, several spots of light emission are observed at localized locations in the N+ type source layer3. Their spread is not observed since the area of the N+ type source layer3is small. In the case where the distance X is as large as 1.6 μm as shown inFIG. 3B, on the other hand, there are observed fine light-emitting spots uniformly distributed over the entire surface of the N+ type source layer3.

That is, when the distance X is increased, the localized light-emitting spots observed in the beginning spread all over the N+ type source layer3in a short period of time so that the N+ type source layer3is turned into an aggregation of fine light-emitting spots. From the observation of the light emission described above, it is confirmed that the parasitic NPN transistor is turned on over a broad area of the N+ type source layer3.

A difference in the light emission showing the ON state of the parasitic NPN transistor between the case in which the P+ type contact layer4is formed in the opening7in the N+ type source layer3as shown inFIG. 3Aand the case in which the P+ type contact layer4is formed in the opening groove9in the N+ type source layer3as shown inFIG. 9Acan be confirmed by using the TLP method and the emission microscope. It was confirmed that while the N+ type source layer3on both sides of the opening7emitted light in the structure as shown inFIG. 3A, the N+ type source layer3on only one side of the opening groove9emitted light in the structure as shown inFIG. 9A.

It is because the N+ type source layer3is divided by the opening groove9, and even when the parasitic NPN transistor is turned on in a region on the one side of the opening groove9, the ON state is not easily propagated to the other side of the opening groove9in the structure as shown inFIG. 9A. Also, it is because the parasitic NPN transistor is not easily turned on in the structure as shown inFIG. 9A, since the area of the P+ type contact layer4is increased by modifying the opening7to the opening groove9so that the holes are more easily absorbed by the P+ type contact layer4.

Further investigation was conducted using the TLP method and the emission microscope on the light emission in a structure modified from the structure shown inFIG. 3Aso that the openings7in the N+ type source layer3are separated from each other by varying distances. The investigation revealed that the light emission was strong in a region where the separation between the openings7is large and the light emission is weak in a region where the separation between the openings7is small. The results of the investigation are related to the variation in the HBM+ESD tolerances. Thus, it was found that the separation between the openings7should be uniform.

Setting the uniform separation between the openings7so that the light emission at the portion of the separation turns from a non-uniform state to a uniform state is effective to improve the variation in the HBM+ESD tolerances and the like.

As understood from the above explanations, in the LDMOS transistor formed to include the N+type source layer3having the opening7in its center and the P+ type contact layer4buried in the opening7, the broad current path can be secured by extending the width of the N+ type source layer3to increase its area so that the parasitic NPN transistor can be turned on in the broad area of the N+ type source layer3.

That is, by making a distance from an edge of the P+ type contact layer4, which is the edge of the opening7in the N+ type source layer4, to the edge of the N+ type source layer3equal to or larger than a predetermined length, the parasitic NPN transistor can be turned on in the broad area of the N+ type source layer3so as to maximize the HBM+ESD tolerance. The predetermined length is around 1.5 mm in this embodiment as shown inFIG. 8. In general, after the distance X at which the HBM+ESD tolerance becomes saturated is confirmed with a TEG (Test Element Group), the distance from the edge of the opening7in the N+ type source layer3to the edge of the N+ type source layer3in the LDMOS transistor is set equal to the distance X confirmed as described above.

Also, a depth of the P+ type contact layer4is formed to be deeper than the N+ type source layer3in this embodiment. Therefore, the P type layer4ais also formed at a location where there is no opening7in the N+ type source layer3, as shown inFIG. 3C. The P type layer4ais connected with the P+ type contact layer4buried in the opening7in the N+ type source layer3, and serves to reduce a difference between an electric potential of the P type base layer2at a location shown inFIG. 3Cand an electric potential of the P type base layer2at a location shown inFIG. 3B.

As a result, a difference between an easiness to put the parasitic NPN transistor at the location shown inFIG. 3Binto operation and an easiness to put the parasitic NPN transistor at the location shown inFIG. 3Cinto operation is reduced and the ON state of the parasitic NPN transistor is more easily spread over the entire region of the N+ type source layer3so that the LDMOS transistor is protected from the surge voltage due to the ESD.

Although a difference between a structure of the parasitic NPN transistor formed at the location shown inFIG. 3Band a structure of the parasitic NPN transistor formed at the location shown inFIG. 3Ccan be eliminated by forming the opening groove as shown inFIG. 9A, there is caused a problem in this case that the parasitic NPN transistors on both sides of the N+ type source layer3are not easily turned on because the N+ type source layer3is divided into left and right portions.

A manufacturing method of the LDMOS transistor according to the embodiment of this invention will be briefly described referring toFIG. 3Band the like. First, a P type semiconductor substrate (not shown) is provided, and an N+ type buried layer (not shown) is formed in the P type semiconductor substrate. Next, an N type epitaxial layer1is formed by a predetermined epitaxial method on the P type semiconductor substrate in which the N+type buried layer has been formed.

Next, a P+ type isolation layer (not shown) extending from a surface of the N type epitaxial layer1into the P type semiconductor substrate is formed by a predetermined method, and an device isolation insulation film (not shown) is formed on necessary regions by a predetermined method.

Next, an N type drift layer (not shown) is formed in a region of the N type epitaxial layer1isolated by the device isolation insulation film and the like by implanting phosphorus (P) ions or the like by a predetermined ion implantation method or the like.

Next, a gate insulation film (not shown) is formed on the N type epitaxial layer1excluding the device isolation insulation film. After that, a gate electrode5extending from above the gate insulation film to above the device isolation insulation film is formed of a polysilicon film or the like by a predetermined method.

The P type base layer2is formed in a region of the N type epitaxial layer1, which is adjacent through the device isolation insulation film to the region of the N type epitaxial layer1in which the N type drift layer has been formed, by implanting boron ions or the like by an ion implantation method or the like using the gate electrode5and a resist film (not shown) as a mask.

Next, the N+ type source layer3having the plurality of openings7in its center is formed by implanting arsenic (As) ions or the like by a predetermined ion implantation method using the gate electrode5and a resist film as a mask.

A feature of this invention is to set the distance from the edge of the opening7to the edge of the N+ type source layer3equal to the distance that maximizes the HBM+ESD tolerance of the LDMOS transistor. Here, the maximum HBM+ESD tolerance means a saturation value of the HBM+ESD tolerance that increases as the distance from the edge of the opening7to the edge of the N+ type source layer3increases.

At the same time, the N+ type drain layer (not shown) is formed in the N type drift layer. Next, the interlayer insulation film6is formed by a predetermined CVD method or the like to cover the P type semiconductor substrate in which the N+ type source layer3and the like are formed. Next, the contact groove8or the like is formed in the interlayer insulation film6through a predetermined photolithography.

Next, a resist mask CP is formed to cover the contact groove8or the like formed on the N+ type drain layer so that the P+ type contact layer4is formed in the N+ type source layer3by implanting boron (B) ions or the like. After that, the P+ type contact layer4is formed by a predetermined ion implanting method. At that time, ion implantation energy is set at an appropriate level so that the P+ type contact layer4is formed to be deeper than the N+ type source layer3.

Next, a metal film made of aluminum or the like is deposited by a predetermined sputtering method or the like over the P type semiconductor substrate in which the contact groove8or the like has been formed, and a source electrode (not shown) and the like are formed through a predetermined photolithography. After multi-layer wirings or the like are formed, a passivation film is formed by a predetermined CVD method or the like to complete the LDMOS transistor.

With the semiconductor device according to the embodiment of this invention, the ESD tolerance of the LDMOS transistor and its variation can be substantially improved.