Voltage regulator with variable drive strength for improved phase margin in integrated circuits

A voltage supply circuit having variable drive strength can optionally be used to provide improved phase margin in an integrated circuit. A bandgap circuit drives an operational amplifier, with the second input of the operational amplifier being a regulated voltage node. The operational amplifier drives multiple pull-ups in a pull-up network coupled to the regulated voltage node, of which the different pull-ups can be separately enabled to control the effective channel width of the pull-up network. In some embodiments, a control circuit (e.g., one or two additional operational amplifiers driving a counter) accepts the output of the operational amplifier as an input signal and provides multiple enable signals to the pull-up network.

FIELD OF THE INVENTION

The invention relates to integrated circuits. More particularly, the invention relates to voltage regulation in integrated circuits.

BACKGROUND OF THE INVENTION

Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.

Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.

Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.

For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD”, “programmable logic device”, and “programmable integrated circuit” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.

As noted above, advanced FPGAs can include several different types of programmable logic blocks in the array. For example,FIG. 1illustrates an FPGA architecture100that includes a large number of different programmable tiles including multi-gigabit transceivers (MGTs101), configurable logic blocks (CLBs102), random access memory blocks (BRAMs103), input/output blocks (IOBs104), configuration and clocking logic (CONFIG/CLOCKS105), digital signal processing blocks (DSPs106), specialized input/output blocks (I/O107) (e.g., configuration ports and clock ports), and other programmable logic108such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (PROC110).

For example, a CLB102can include a configurable logic element (CLE112) that can be programmed to implement user logic plus a single programmable interconnect element (INT111). A BRAM103can include a BRAM logic element (BRL113) in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as four CLBs, but other numbers (e.g., five) can also be used. A DSP tile106can include a DSP logic element (DSPL114) in addition to an appropriate number of programmable interconnect elements. An IOB104can include, for example, two instances of an input/output logic element (IOL115) in addition to one instance of the programmable interconnect element (INT111). As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element115are manufactured using metal layered above the various illustrated logic blocks, and typically are not confined to the area of the input/output logic element115.

In the pictured embodiment, a columnar area near the center of the die (shown shaded inFIG. 1) is used for configuration, clock, and other control logic. Horizontal areas109extending from this column are used to distribute the clocks and configuration signals across the breadth of the FPGA.

Some FPGAs utilizing the architecture illustrated inFIG. 1include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, the processor block PROC110shown inFIG. 1spans several columns of CLBs and BRAMs.

Note thatFIG. 1is intended to illustrate only an exemplary FPGA architecture. For example, the numbers of logic blocks in a column, the relative width of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top ofFIG. 1are purely exemplary. For example, in an actual FPGA more than one adjacent column of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB columns varies with the overall size of the FPGA.

For many FPGA devices, such as FPGA100ofFIG. 1, core logic elements such as CLBs102are powered by a main voltage supply (VDD), I/O circuitry such as IOBs104are powered by a separate auxiliary voltage supply (VCCAUX), where VCCAUX is typically greater than VDD, and the configuration memory cells are powered by a regulated voltage (Vgg) that is typically generated using a well-known bandgap reference voltage (Vbg_ref). In some FPGAs, for example, VDD has a voltage of between approximately 1.0-1.2 volts, VCCAUX has a voltage of approximately 2.5 volts, and Vgg is typically regulated to approximately one transistor threshold voltage (VT) above VDD (e.g., to between approximately 1.3-1.5 volts).

For example,FIG. 2shows a simplified portion200of FPGA100that includes a bandgap reference voltage circuit205, a VCCAUX voltage regulator circuit210, a plurality of configuration memory cells230, I/O circuitry250, and core logic260. Voltage regulator210, which includes a PMOS transistor211and an operational amplifier (op-amp)212, generates a regulated voltage Vgg at a power node A for powering memory cells230, which store configuration bits (CB) that may be provided to control various configurable elements within I/O circuitry250and core logic260via signal lines231A and231B, respectively, which are shown collectively inFIG. 2for simplicity. (Note that in the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals and voltages.)

In VCCAUX voltage regulator circuit210, PMOS transistor211is coupled between auxiliary voltage supply VCCAUX and node A, and has a well region tied to VCCAUX. Operational amplifier212, which is well-known, includes a first input terminal coupled to receive a bandgap reference voltage Vbg_ref from bandgap reference voltage circuit205, a second input terminal coupled to node A, and an output terminal coupled to the gate of PMOS transistor211. Bandgap reference voltage circuit205can generate a value of Vbg_ref that is relatively insensitive to process and temperature variations, for example, so that configuration memory cells230which store logic high values of CB drive signal lines231with a CB signal having a voltage approximately equal to a specified value of Vgg, irrespective of the operating temperature.

FIG. 3shows a programmable interconnect point (PIP)300that can be included, for example, in the programmable interconnect element111shown inFIG. 1. PIP300includes an NMOS pass transistor310and a configuration memory cell230. NMOS pass transistor310is coupled between interconnect signal lines303A and303B, and has a gate terminal coupled to memory cell230via signal line231. Memory cell230stores a CB that controls operation of NMOS pass transistor310, and although not shown for simplicity inFIG. 3, includes a power terminal coupled to receive regulated voltage Vgg. CB is typically loaded into memory cell230during configuration of FPGA100. During normal operation of FPGA100, a logic high value of CB (e.g., CB≈Vgg) turns on transistor310and connects signal lines303A-303B together, and conversely, a logic low value of CB (e.g., CB≈0 volts) turns off transistor310and isolates signal lines303A-303B from each other. As mentioned above, regulated voltage Vgg is typically regulated to approximately one transistor threshold voltage VT above VDD. Because the voltage swing of logic signals on signal lines303A-303B is typically between 0 volts and VDD, driving the gate of NMOS transistor310with a value of regulated voltage Vgg that is approximately one transistor threshold voltage VT greater than VDD allows NMOS transistor310to pass a logic high signal without a VT drop across transistor310.

FIG. 4illustrates a voltage supply circuit400in an exemplary FPGA, e.g., the FPGA ofFIG. 2. Voltage supply circuit400includes bandgap circuit410, regulator circuit420, start-up circuit430, and NMOS transistor MN2, and provides regulated voltage Vgg to memory cells230via regulated voltage node440. Bandgap circuit410generates bandgap reference voltage Vbg_ref and supplies the bandgap reference voltage Vbg_ref to voltage regulator circuit420, where Vbg_ref drives one input terminal of operational amplifier422. The other input terminal of operational amplifier422is driven by regulated voltage node440, and the output terminal of operational amplifier422provides pass voltage Vgg_pass. Note that some known voltage supply circuits include a resistor divider (not shown, but seeFIG. 10) on the feedback path between regulated voltage node440and operational amplifier422, while in other voltage supply circuits the reference voltage Vbg_ref is brought up to the Vgg voltage level. Regulator circuit420also includes PMOS pull-up transistors MP1and MP2, coupled in series between auxiliary voltage supply VCCAUX and regulated voltage node440. The gate terminal of PMOS transistor MP1is coupled to receive pass voltage Vgg_pass. The gate terminal of PMOS transistor MP2is coupled to receive a power down signal PDNB, inverted by inverter421. The bodies of PMOS transistors MP1and MP2are coupled to VCCAUX, e.g., through well biasing.

Start-up circuit430includes PMOS transistor MP3and NMOS transistor MN1. PMOS transistor MP3and NMOS transistor MN1are coupled in series between VCCAUX and regulated voltage node440, with the gate of PMOS transistor MP3coupled to ground GND and the gate of NMOS transistor MN1receiving a voltage clamp signal CLMP.

NMOS transistor MN2is a diode-connected transistor coupled between regulated voltage node440and ground GND, and provides current for a closed loop phase margin, as is described in more detail below.

For simplicity,FIG. 4omits the one or more well-known unity-gain buffers that may be coupled between the output of operational amplifier422and the gate of transistor MP1. In addition, although not shown for simplicity, bandgap reference voltage Vbg_ref may be provided to a plurality of regulator circuits420and start-up circuits430distributed across the integrated circuit. Also not shown for simplicity, a single operational amplifier422can be used to drive many pull-up transistors MP1and MP2, if desired.

Voltage supply circuit400functions as follows. During operation of the integrated circuit, bandgap circuit410provides a bandgap reference voltage Vbg_ref, using any of many known methods. Operational amplifier422is well known, and generates a value for pass voltage Vgg_pass that results in a negligible voltage differential between its input terminals, thereby maintaining the regulated voltage Vgg approximately equal to the voltage of bandgap reference voltage Vbg_ref. Pass voltage Vgg_pass, which controls the conductivity of PMOS transistor MP1, is adjusted by operational amplifier422so that the current provided by MP1pulls up the voltage of regulated voltage Vgg in response to dips in Vgg caused by leakage current in memory cells230and/or current from transistor MN2. (Note that power down signal PDNB is high while the integrated circuit is operating, so the output of inverter421is low and PMOS transistor MP2is on.) In this manner, the dynamic current provided by PMOS transistor MP1compensates for leakage current in memory cells230to maintain the regulated voltage Vgg at the desired voltage level (e.g., Vbg_ref).

Start-up circuit430, which is well-known, is primarily used during device power-up operations. For example, upon device power-on, voltage clamp signal CLMP is driven to a positive voltage that turns on transistor MN1to quickly charge regulated voltage Vgg until Vgg reaches a level that causes transistor MN1to turn off, for example, when regulated voltage Vgg becomes greater than one threshold voltage VT below the voltage of voltage clamp signal CLMP. In this manner, when operational amplifier422becomes operational, the reference voltage Vgg is sufficient to allow operational amplifier422to operate normally (i.e., to avoid overshoot conditions).

An important characteristic of voltage supply circuits is the value of the phase margin. As shown inFIG. 4, voltage supply circuits have the inherent characteristic that the regulated voltage Vgg is controlled using negative feedback. In other words, the voltage supply circuit includes a loop, which in the circuit ofFIG. 4includes the path through operational amplifier422, via pass voltage Vgg_pass to PMOS transistor MP1, and back to operational amplifier422via PMOS transistor MP2and regulated voltage node440. In adverse conditions (e.g., in high temperatures, or in an integrated circuit manufactured at the fast process corner) such a loop can begin to oscillate. If the phase margin of the circuit is sufficiently large, the oscillation will die out. If the phase margin of the circuit is too small, the loop will continue to oscillate and the integrated circuit will not function properly. Therefore, it is desirable to increase the phase margin of a voltage supply circuit.

A reduction in the phase margin of a voltage regulator circuit can have many causes. For example, a variation in temperature can cause a reduction in phase margin. Further, an integrated circuit manufactured in one corner of the fabrication process can have a lower phase margin that an otherwise identical integrated circuit manufactured at a different process corner. The size of NMOS transistor MP1is typically selected to handle the leakage current under worst-case conditions, plus a margin of error, typically resulting in an over-design of transistor strength. The larger size of transistor MP1increases the loop gain of the circuit, which further reduces the phase margin.

One known method of increasing the phase margin is illustrated inFIG. 4. The addition of a diode to ground (e.g., NMOS transistor MN2, coupled as shown inFIG. 4) can increase the phase margin by providing for additional leakage current between regulated voltage Vgg and ground GND. This additional leakage current makes the current requirements more predictable across temperature and process variations, by increasing the current requirements for all of the integrated circuits. Because the current requirements are more predictable, regulator circuit420can be better designed (e.g., transistor MP1can be properly sized) to provide a consistent phase margin across temperature and process variations. However, the addition of such “leaker circuits” (e.g., transistor MN2) increases the power consumption of the integrated circuit. Further, this approach is of limited value, because it does not address the increase in loop gain caused by the increasing loads as integrated circuits increase in size.

Therefore, it is desirable to provide additional circuits and methods of increasing the phase margin of a supply voltage circuit in an integrated circuit.

SUMMARY OF THE INVENTION

The invention provides a voltage supply circuit having variable drive strength that can be used, for example, to provide improved phase margin in an integrated circuit. A bandgap circuit drives an operational amplifier, with the second input of the operational amplifier being a regulated voltage node. The operational amplifier drives multiple pull-ups in a pull-up network coupled to the regulated voltage node, of which the different pull-ups can be separately enabled to control the effective channel width of the pull-up network. In some embodiments, a control circuit accepts the output of the operational amplifier as an input signal and provides multiple enable signals to the pull-up network. In some embodiments, the control circuit includes a second operational amplifier driven by the first operational amplifier and a reference voltage signal, and in turn driving a counter that provides the enable signals to the pull-up network. In some embodiments, the control circuit also includes a third operational amplifier driven by the first operational amplifier and a second reference voltage signal. The third operational amplifier drives the counter in the opposite direction from the second operational amplifier.

Some embodiments also include one or more of a start-up circuit coupled to the regulated voltage node, a diode coupled between the regulated voltage node and ground, and/or one or more programmable logic circuits coupled between a regulated voltage node and ground.

In some embodiments, the bandgap circuit includes two bandgap generators having different performance characteristics, both bandgap generators driving a select circuit that selects between output signals from the two bandgap generators based on temperature or other operating conditions.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is applicable to a variety of integrated circuits (ICs). The present invention has been found to be particularly applicable and beneficial for programmable logic devices (PLDs). Therefore, an appreciation of the present invention is presented by way of specific examples utilizing PLDs such as field programmable gate arrays (FPGAs). However, the present invention is not limited by these examples, and it will be apparent to those of skill in the art that many embodiments of the present invention can be applied to programmable, non-programmable, and/or partially programmable integrated circuits.

Further, in the following description numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention can be practiced without these specific details.

FIG. 5illustrates a first novel voltage supply circuit500that can be included, for example, in a programmable logic device. Voltage supply circuit500ofFIG. 5includes a bandgap circuit510, an operational amplifier422, a pull-up network525, a start-up circuit430, a leaker circuit (diode-coupled transistor) MN2, and a control circuit550, coupled together as shown inFIG. 5. Operational amplifier422, start-up circuit430, and leaker circuit MN2can be implemented using known techniques, if desired. For example, these elements can be implemented in the same fashion as the similarly-numbered elements included in known voltage supply circuit400ofFIG. 4. Bandgap circuit510can be implemented in the same fashion as bandgap circuit410ofFIG. 4, if desired. However, other possible implementations for bandgap circuit510are presented below, in conjunction withFIGS. 9 and 11.

In the pictured embodiment, pull-up network525includes five pull-up transistors P1, P2, P4, P8, and P16. In the pictured embodiment, pull-up transistors P1, P2, P4, P8, and P16are implemented as PMOS transistors with bodies tied to the auxiliary voltage supply VCCAUX. In other embodiments, the pull-up transistors are implemented using other techniques. In the pictured embodiment, P1has a first channel width, P2has twice the channel width of transistor P1, P4has four times the channel width of transistor P1, and so forth. Each pull-up transistor has a source terminal coupled to the auxiliary voltage supply VCCAUX, and a gate terminal coupled to the pass voltage output terminal Vgg_pass of operational amplifier422. Each pull-up transistor P1, P2, P4, P8, and P16has a drain terminal coupled to the source terminal of an enable transistor E1, E2, E4, E8, and E16, respectively. In the pictured embodiment, enable transistors E1, E2, E4, E8, and E16are implemented as PMOS transistors with bodies tied to VCCAUX. The drain terminals of the enable transistors are coupled to regulated voltage node540. The gate terminal of each enable transistor is coupled to receive a different enable signal from control circuit550.

In some embodiments (not shown), fewer or more than five pull-up transistors and five enable transistors are included in the pull-up network. In other embodiments, the pull-up transistors have different relative sizes, and/or the enable transistors have different relative sizes. In some embodiments, the pull-up transistors and/or the enable transistors are laid out as multiple smaller transistors. In one embodiment, for example, transistor P1is laid out as one unit transistor, transistor P2is laid out as two unit transistors, transistor P4is laid out as four unit transistors, and so forth.

For simplicity,FIG. 5omits the one or more well-known unity-gain buffers that may be coupled between the output of operational amplifier422and the input terminal of pull-up transistor network525. In addition, although not shown for simplicity, bandgap reference voltage Vbg_ref may be provided to a plurality of operational amplifiers distributed across the integrated circuit.

Control circuit550can be implemented, for example, as shown inFIG. 6. The control circuit ofFIG. 6includes a second operational amplifier620. Operational amplifier620has two input terminals coupled to receive pass voltage Vgg_pass and an input reference voltage Vref, and a CountUp output terminal. The CountUp output signal drives up counter610, which provides the enable signals En_Leg[4:0] to pull-up transistor network525(seeFIG. 5).

In some embodiments (not shown), control circuit550is coupled to receive a power down signal, which is then gated with the enable output signals. For example, in some embodiments the power down signal is active low, i.e., has a high value when the circuit is operating. In one such embodiment, inverters630are replaced by NAND gates driven by signals En_Leg[4:0] and the power down signal. Thus, when the integrated circuit is powered down (i.e., the power down signal is low), the enable signals are all high, i.e., none of the pull-ups are enabled. When the integrated circuit is operating (i.e., the power down signal is high), the enable control signals En_Leg_B[4:0] behave in the same fashion as the circuit shown inFIG. 6.

Returning now toFIG. 5, voltage supply circuit500includes the basic functionality of voltage supply circuit400ofFIG. 4. During operation of the integrated circuit, bandgap circuit510provides bandgap reference voltage Vbg_ref, e.g., using known methods or the methods described below in conjunction withFIGS. 9 and 11. Operational amplifier422is well known, and generates a value for pass voltage Vgg_pass that results in a negligible voltage differential between its input terminals, thereby maintaining the regulated voltage Vgg approximately equal to the voltage of bandgap reference voltage Vbg_ref. Pass voltage Vgg_pass, which drives the pull-up transistor network525, is adjusted by operational amplifier422so that the current provided by pull-up transistor network525pulls up regulated voltage Vgg in response to dips in Vgg caused by leakage current in memory cells230. In this manner, the dynamic current provided by pull-up transistor network525compensates for leakage current in memory cells230to maintain the regulated voltage Vgg at the desired voltage level (e.g., Vbg_ref).

However, voltage supply circuit500has an added functionality, which allows the effective channel width of the pull-up network525to be dynamically controlled. This capability allows voltage supply circuit500to avoid reducing phase margin more than is necessary to enable proper functioning of the integrated circuit. This capability is provided by control circuit550and the configurable nature of pull-up transistor network525. In brief, control circuit550continually checks the regulated voltage Vgg and tries to keep the regulated voltage Vgg at a desired level, by adjusting the strength of pull-up network525, e.g., by turning on and off additional pull-ups in the network.

Under some conditions (e.g., at some temperatures or process corners), more current passes through memory cells230. This increase in current acts to reduce regulated voltage Vgg, by reducing pass voltage Vgg_pass. To overcome this response (i.e., to restore the preferred value of Vgg_pass), control circuit550simply enables more pull-ups, as follows. When regulated voltage Vgg is reduced, pass voltage Vgg_pass is also reduced. Operational amplifier620(seeFIG. 6) detects that the pass voltage Vgg_pass has gone below a target voltage defined by reference voltage Vref, and signal CountUp goes high. The value stored in counter610increases, and the value represented by signals En_Leg[4:0] also increases. In other words, one or more of signals En_Leg[4:0] changes from a low value to a high value. Signals En_Leg[4:0] are inverted by inverters630(5 inverters, in the illustrated embodiment), therefore one or more of enable control signals En_Leg_B[4:0] changes from a high value to a low value. One or more additional pull-ups in pull-up network525are enabled, increasing the drive strength (i.e., increasing the effective channel width) of pull-up network525. Pass voltage Vgg_pass increases toward the desired level.

In the pictured embodiment, enable control signal En_Leg_B[4] controls the P16pull-up, enable control signal En_Leg_B[3] controls the P8pull-up, enable control signal En_Leg_B[2] controls the P4pull-up, enable control signal En_Leg_B[1] controls the P2pull-up, and enable control signal En_Leg_B[0] controls the P1pull-up. Thus, a more significant bit of the value stored in counter610has a larger impact on the effective channel width of pull-up network525than a less significant bit, with the effect of each bit being twice as strong as the effect of the next less significant bit. In other embodiments, the relationships between the enable signals and the pull-up transistors follow other patterns.

Under other conditions (e.g., at different temperatures or process corners), less current passes through memory cells230. This reduction in current acts to increase regulated voltage Vgg, by increasing pass voltage Vgg_pass. In this situation (i.e., to restore the preferred value of Vgg_pass), control circuit550enables fewer pull-ups, as follows. When regulated voltage Vgg increases, pass voltage Vgg_pass also increases. Operational amplifier620(seeFIG. 6) detects that the pass voltage Vgg_pass has gone above a target voltage defined by reference voltage Vref, and signal CountUp goes low. The value stored in counter610decreases, and the value represented by signals En_Leg[4:0] also decreases. In other words, one or more of signals En_Leg[4:0] changes from a high value to a low value. Signals En_Leg[4:0] are inverted by inverters630, therefore one or more of enable control signals En_Leg_B[4:0] changes from a low value to a high value. One or more additional pull-ups in pull-up network525is disabled, decreasing the drive strength (i.e., decreasing the effective channel width) of pull-up network525. Pass voltage Vgg_pass decreases toward the desired level.

Clearly, the maximum current that can be handled by the pull-up network525should be more than the estimated worst case leakage from memory cells230, plus a safety margin. In other words, the total number of pull-ups in pull-up network525must be large enough to cover the most severe anticipated leakage current, plus the safety margin. In known voltage supply circuits, the pull-up strength is typically over-designed for most applications. In the voltage supply circuit ofFIG. 5, under these conditions the number of active pull-ups can be reduced by disabling the unneeded pull-ups, which reduces the gain of the closed loop, which in turn improves the phase margin of the circuit.

In some embodiments, a delay element730is included between operational amplifier620and counter610, as shown inFIG. 7. This delay element increases the response time of the control circuit, reducing the volatility of enable control signals En_Leg_B[4:0]. For example, delay element730can prevent the effective channel width of pull-up network525from increasing or decreasing past the desired point, before control circuit550can detect the fact that the optimum setting has been reached. In some embodiments, delay element730prevents counter610from changing values continuously (e.g., adding one, subtracting one, adding one, subtracting one . . . ) at a frequency that might interfere with the Vgg feedback loop.

FIG. 8illustrates another embodiment of control circuit550. In this embodiment, a range of acceptable voltage levels is specified for regulated voltage Vgg, e.g., Vref1≦Vref≦Vref2. When regulated voltage Vgg falls below a first reference voltage Vref1, operational amplifier620detects the change, and signal CountUp goes high. The value stored in counter810increases in value, and one or more of signals En_Leg[4:0] changes from a low value to a high value. One or more of enable control signals En_Leg_B[4:0] changes from a high value to a low value. One or more additional pull-ups in pull-up network525is enabled, increasing the drive strength of pull-up network525. Regulated voltage Vgg increases towards the desired level.

When regulated voltage Vgg rises above a second reference voltage Vref2, operational amplifier820detects the change, and signal CountDown goes high. The value stored in counter810decreases in value, and one or more of signals En_Leg[4:0] changes from a high value to a low value. One or more of enable control signals En_Leg_B[4:0] changes from a low value to a high value. One or more additional pull-ups in pull-up network525is disabled, decreasing the drive strength of pull-up network525. Regulated voltage Vgg decreases towards the desired level.

FIG. 9illustrates an exemplary bandgap circuit900that can be included, for example, in the voltage supply circuit ofFIG. 5. Bandgap circuit900includes first and second bandgap generators901,902and a select circuit910, which includes a comparator (CMP)912and a multiplexer914. These elements are coupled together as shown inFIG. 9.

Bandgap circuit900functions as follows. First bandgap generator901provides voltage Vbg1to a first input terminal of comparator912and to a first input terminal of multiplexer914, via node N1. Second bandgap generator902provides voltage Vbg2to a second input terminal of comparator912and to a second input terminal of multiplexer914, via node N2. Comparator912provides a select signal SEL to the control terminal of multiplexer914, where signal SEL indicates whether the voltage of Vbg1is less than the voltage of Vbg2. Multiplexer914has an output terminal to provide either Vbg1or Vbg2as bandgap reference voltage Vbg_ref in response to select signal SEL.

In one embodiment, voltage Vbg1has a negligible temperature coefficient and thus is relatively insensitive to temperature variations, and voltage Vbg2has a negative temperature coefficient and thus is inversely proportional to the operating temperature. In other embodiments, voltages Vbg1and/or Vbg2have other suitable temperature coefficients.

In one embodiment, bandgap circuit900functions as follows. First bandgap generator901generates voltage Vbg1as having a substantially zero temperature coefficient, and second bandgap generator902generates voltage Vbg2as having a negative temperature coefficient, as described above. Comparator912compares the value of voltage Vbg1at node N1with the value of voltage Vbg2at node N2, and in response thereto generates select signal SEL. In the pictured embodiment, if voltage Vbg1is less than voltage Vbg2, comparator912drives select signal SEL to a first state, which causes multiplexer914to provide voltage Vbg1as bandgap reference voltage Vbg_ref to operational amplifier422(seeFIG. 5). Conversely, if voltage Vbg1is greater than or equal to voltage Vbg2, comparator912drives select signal SEL to a second state, which causes multiplexer914to provide voltage Vbg2as bandgap reference voltage Vbg_ref to operational amplifier422.

FIG. 10illustrates a second novel voltage supply circuit1000that can be included, for example, in a programmable logic device. Voltage supply circuit1000is similar to voltage supply circuit500ofFIG. 5. Therefore, only the differences are described here.

Voltage supply circuit1000includes a voltage divider network VDN1coupled between regulated voltage node540and the input terminal of operational amplifier422, as illustrated inFIG. 10. Voltage divider network VDN1includes resistors R1and R2, coupled together in series between regulated voltage node540and ground as shown inFIG. 10. Voltage divider network VDN1provides a ratioed voltage of K1*Vgg to operational amplifier422, where the value of K1is determined by the relative resistances of resistors R1and R2.

FIG. 11illustrates an exemplary bandgap circuit1100that can be included, for example, in the voltage supply circuits ofFIGS. 5and/or10. Bandgap circuit1100is similar to bandgap circuit900ofFIG. 9. Therefore, only the differences are described here.

Bandgap circuit1100includes a second voltage divider network VDN2coupled between voltage Vbg1and node N1, as illustrated inFIG. 11. Voltage divider network VDN2includes resistors R3and R4, coupled together in series between Vbg1and ground as shown inFIG. 10. Voltage divider network VDN2provides a ratioed voltage of K2*Vbg1to comparator912and multiplexer914, where the value of K2is determined by the relative resistances of resistors R3and R4. Further, although not shown inFIG. 11for simplicity, bandgap circuit1100may include a third voltage divider network that provides a ratioed Vbg2voltage of K3*Vbg2to node N2, where the value of K3is determined by the relative resistances of the resistors (not shown) which form the third voltage divider network.

As described above with respect to the various exemplary embodiments of bandgap circuit510, first bandgap generator901generates a waveform for voltage Vbg1that is relatively insensitive to process and temperature variations, and second bandgap generator902generates a waveform for voltage Vbg2that has a negative temperature coefficient. However, in other embodiments first bandgap generator901may generate a voltage Vbg1having a negative temperature coefficient, having a positive temperature coefficient, or that is relatively insensitive to temperature variations. Similarly, in other embodiments, second bandgap generator902may generate a voltage Vbg2having a negative temperature coefficient, having a positive temperature coefficient, or that is relatively insensitive to temperature variations.

In addition, although described above as using the lesser of Vbg1and Vbg2to generate bandgap reference voltage Vbg_ref, in other embodiments, the bandgap circuits may be configured to use the greater of Vbg1and Vbg2to generate bandgap reference voltage Vbg_ref.

It will be apparent to one skilled in the art after reading this specification that the present invention can be practiced within these and other architectural variations.

Those having skill in the relevant arts of the invention will now perceive various modifications and additions that can be made as a result of the disclosure herein. For example, resistors, bandgap circuits, bandgap generators, control circuits, pull-ups, pull-up networks, start-up circuits, transistors, PMOS transistors, NMOS transistors, diodes, leaker circuits, operational amplifiers (op-amps), memory cells, and other components other than those described herein can be used to implement the invention. Active-high signals can be replaced with active-low signals by making straightforward alterations to the circuitry, such as are well known in the art of circuit design. Logical circuits can be replaced by their logical equivalents by appropriately inverting input and output signals, as is also well known.

Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection establishes some desired electrical communication between two or more circuit nodes. Such communication can often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art.

Accordingly, all such modifications and additions are deemed to be within the scope of the invention, which is to be limited only by the appended claims and their equivalents.