Highly efficient charge pump synchronized to the drive signal of a touch screen system

An alternating current (AC) drive signal having a first frequency and a high logic level at a boosted supply voltage is applied to drive a capacitive sensing line of a capacitive touch panel. The boosted supply voltage is generated by boosting an input voltage. The voltage boosting is effectuate by a charge pump circuit operating synchronous to assertion of the AC drive signal with a charge transfer time that is adaptable to different capacitive load conditions.

TECHNICAL FIELD

The present invention relates to a capacitive touch screen system and, in particular, to the operation of a charge pump circuit powering driver circuits that generate touch screen drive signals.

BACKGROUND

Reference is made toFIG. 1showing a conventional configuration for a touch screen system10. The system10includes a touch panel12formed by a plurality of parallel drive lines14and a plurality of parallel sense lines16. The drive lines14and sense lines16are typically formed of a transparent material (such as, for example, indium tin oxide ITO) so as to not obscure a visual display system (not shown) positioned underneath the panel12. The drive lines14and sense lines16can, for example, each be formed of a plurality of series connected diamond shapes. The drive lines14extend across the panel12with a first orientation direction (for example, horizontal) and the sense lines extend across the panel12with a second orientation direction (for example, vertical) such that the lines14cross over the lines16(or vice versa). However, the plane containing the lines14and the plane containing the lines16are typically separated from each other by a layer of dielectric material. A sense capacitor18is accordingly formed at each location where the lines14and16cross.

A digital controller circuit20generates an alternating current (AC) drive signal (VTX), for example, in the form of a square wave, and sequentially applies that AC drive signal to the drive lines14through a driver circuit22. The AC drive signal has a frequency fd that is, for example, in the range of 100-300 kHz and is typically at 200 kHz.

The digital controller circuit20is powered from a power supply voltage Vdd, with Vdd typically at 3.3V. The driver circuit22, however, is powered from a power supply voltage Vddh, where Vddh>Vdd, with Vddh for example at 6V, 9V, 12V, 16V higher as needed. A charge pump circuit24, powered from the power supply voltage Vdd, operates to boost the Vdd voltage to produce the Vddh voltage. An oscillator circuit26provides an AC signal28to the charge pump circuit24to control the boost switching operation of a flyback capacitor that generates the Vddh voltage. The AC signal28has a frequency fo that is, for example, in the range of 10-100 MHz and is typically at 48 MHz.

The driver circuit22includes a level shifting and buffering circuit to level shift the AC drive signal output from the digital controller circuit20from the Vdd voltage level to the Vddh voltage level to generate the level-shifted AC drive signal (Vdrive) for application to the drive lines14.

A charge conversion circuit30such as a charge to voltage (C2V) converter circuit (or a charge to current (C2I) converter circuit) is coupled to the sense lines16. The conversion circuit30senses the charge at each sense capacitor18and converts the sensed charge to an output signal (voltage or current) indicative of the sensed charge. The amount of charge at each sense capacitor18is a function of the AC drive signal, the capacitance between the drive line14and sense line16at the sense capacitor18and the influence of a touch capacitance contributed by the presence of an object (such as a finger or stylus) in proximity to the drive lines14and sense lines16of the panel12. A processing circuit32receives the output voltages from the conversion circuit30for each sense capacitor18. The output voltages are processed to determine the presence (touch and/or hover) of the object and the location of the object.

SUMMARY

In an embodiment, a circuit comprises: a driver circuit configured to apply an alternating current (AC) drive signal having a first frequency to a capacitive sensing line of a capacitive touch panel, said driver circuit powered by a boosted supply voltage; and a charge pump circuit configured to receive an input supply voltage and output the boosted supply voltage, wherein said charge pump circuit is enabled to perform a voltage boosting operation synchronous to assertion of the AC drive signal. This voltage boosting operation is further adaptive to different capacitive loads of the capacitive touch panel receiving the AC drive signal by adjusting a slew-rate for charge transfer in the voltage boosting operation.

In an embodiment, a circuit comprises: a driver circuit configured to apply an alternating current (AC) drive signal having a first frequency to a capacitive sensing line of a capacitive touch panel, said driver circuit powered by a boosted supply voltage; and a charge pump circuit configured to receive an input supply voltage and output the boosted supply voltage, wherein a switching operation of said charge pump circuit to generate the boosted supply voltage occurs at a second frequency equal to an integer multiple of said first frequency. The integer multiple may, for example, comprise any integer greater than or equal to one.

In an embodiment, a method comprises: applying an alternating current (AC) drive signal having a first frequency and a high logic level at a boosted supply voltage to a capacitive sensing line of a capacitive touch panel; and boosting an input voltage to generate the boosted supply voltage, wherein boosting is performed synchronous to assertion of the AC drive signal. This boosting operation is further adaptive to different capacitive load of a touch panel receiving the AC drive signal by adjusting a slew-rate for charge transfer in the voltage boosting operation.

DETAILED DESCRIPTION OF THE DRAWINGS

Reference is now made toFIG. 2showing a configuration for a touch screen system100. The system100includes a touch panel12formed by a plurality of parallel drive lines14and a plurality of parallel sense lines16. The drive lines14and sense lines16are typically formed of a transparent material (such as, for example, indium tin oxide ITO) so as to not obscure a visual display system (not shown) positioned underneath the panel12. The drive lines14and sense lines16can, for example, each be formed of a plurality of series connected diamond shapes. The drive lines14extend across the panel12with a first orientation direction (for example, horizontal) and the sense lines extend across the panel12with a second orientation direction (for example, vertical) such that the lines14cross over the lines16(or vice versa). However, the plane containing the lines14and the plane containing the lines16are separated from each other by a layer of dielectric material. A sense capacitor18is accordingly formed at each location where the lines14and16cross.

A digital controller circuit200generates an alternating current (AC) drive signal (VTX), for example, in the form of a square wave, and sequentially applies that AC drive signal to the drive lines14through a driver circuit22. The AC drive signal has a frequency fd that is, for example, in the range of 100-300 kHz and is typically at 200 kHz.

The digital controller circuit200is powered from a power supply voltage Vdd, with Vdd typically at 3.3V. The driver circuit22, however, is powered from a power supply voltage Vddh, where Vddh>Vdd, with Vddh for example at 6V, 9V, 12V, 16V higher as needed. A charge pump circuit204, powered from the power supply voltage Vdd, operates to boost the Vdd voltage to produce the Vddh voltage. The digital controller circuit200supplies an AC control signal208to the charge pump circuit204to control the boost switching operation that generates the Vddh voltage. The AC control signal208has a frequency fo that is, for example, the same frequency fd as the AC drive signal. In an embodiment, the AC control signal208and the AC drive signal are phase aligned.

The driver circuit22includes a level shifting and buffering circuit to level shift the AC drive signal output from the digital controller circuit200from the Vdd voltage level to the Vddh voltage level to generate the level-shifted AC drive signal (Vdrive) for application to the drive lines14.

A conversion circuit30such as a charge to voltage (C2V) converter circuit (or a charge to current (C2I) converter circuit) is coupled to the sense lines16. The conversion circuit30senses the charge at each sense capacitor18and converts the sensed charge to an output signal (voltage or current) indicative of the sensed charge. The amount of charge at each sense capacitor18is a function of the AC drive signal, the capacitance between the drive line14and sense line16at the sense capacitor18and the influence of a touch capacitance contributed by the presence of an object (such as a finger or stylus) in proximity to the drive lines14and sense lines16of the panel12. A processing circuit32receives the output voltages from the conversion circuit30for each sense capacitor18. The output voltages are processed to determine the presence (touch and/or hover) of the object and the location of the object.

The touch screen system100is configured with the charge pump circuit204synchronized to the application of the AC drive signal to the drive lines14of the panel12and adaptive to different capacitive loads in different modes of operation (for example, mutual-capacitance sensing or self-capacitance sensing) of the panel12. This results in a higher efficiency of the charge pump circuit204and a reduction in system noise in comparison to theFIG. 1circuit. The principle of operation with system100is to take advantage of the fact that the load of the charge pump circuit204is not a continuously resistive load (as inFIG. 1), but is instead a sample switching capacitor load. The charge pump circuit204is controlled for operation at a much lower operating frequency fo (that is equal to the frequency fd of the AC drive signal) resulting in an improvement in power consumption (with an efficiency of 85-90%). Additionally, the synchronized operation of the charge pump advantageously ensures that the voltage is well settled by the time the conversion circuit30senses the charge at the sense capacitor18. At all other times, accurate regulation of the voltage output from the charge pump circuit204is not required.

FIG. 3Ashows an example of the waveform for the AC drive signal (VTX) generated by the digital controller circuit200.FIG. 3Bshows an example of the waveform for the AC control signal208generated by the digital controller circuit200. These signals have a same frequency with substantially aligned phases. In an alternative embodiment, the control signal208may instead have a frequency that is an integer multiple of the frequency of the AC drive signal (VTX) with phase alignment to the AC drive signal VTX as shown in the example ofFIG. 3Cwhere the integer multiple is two.

Reference is now made toFIG. 4showing a circuit diagram of the charge pump circuit204. The circuit204includes an n-channel MOS transistor MN1having source terminal coupled to receive the input Vdd voltage level and a drain terminal coupled to an intermediate node220. The gate terminal of transistor MN1is controlled by a first control signal (ϕ1). A first plate of a flyback capacitor Cfly is coupled to the intermediate node220. An n-channel transistor MN2has a drain terminal coupled an intermediate node222and a source terminal coupled to receive the ground voltage. The gate terminal of transistor MN2is controlled by a second control signal (ϕ2). A second plate of the flyback capacitor Cfly is coupled to the intermediate node222. A p-channel MOS transistor MP1has a source terminal coupled to receive the input Vdd voltage level and a drain terminal coupled to the intermediate node222. The gate terminal of transistor MP1is controlled by a third control signal (ϕ3). A p-channel MOS transistor MP2has a drain terminal coupled to the intermediate node220and a source terminal coupled to an output node226which generates the Vddh voltage level. The gate terminal of transistor MP2is controlled by a fourth control signal (ϕ4). A first plate of an output tank capacitor Ctank is coupled to the output node226. A second plate of an output tank capacitor Ctank is coupled to the ground voltage.

The n-channel transistor MN2may comprise a tunable transistor. In particular, the transistor MN2has a conduction that is tuned in response to a control signal TC1. During start-up operation of the charge pump circuit204, the control signal TC1can exercise control over MOSFET drive and time duration so as to reduce the change of an excessive inrush current.

The p-channel MOS transistor MP1may also comprise a tunable transistor. In particular, the transistor MP1has a conduction that is tunable in response to control signal TC2. Responsive to operating mode, the control signal TC2can exercise control over device conduction based on the capacitive load coupled to receive the Vddh voltage level. For example, the panel12has a relatively lower capacitive load when operating in a mutual capacitance operating mode, but has a relatively higher capacitive load when operating in a self capacitance operating mode. The charge pump circuit204must be able to adapt to these capacitive load differences. This is accomplished through control signal TC2, with adjust of transistor MP1conduction effectuating control over the slew-rate (transfer time) of the charge pump circuit204. When the panel is in the mutual capacitance operating mode, the control signal TC2tunes transistor MP1for increased transfer time so that over pumping is reduced and the charge pump waveform is periodic in each cycle. When the panel is in the self capacitance operating mode, the control signal TC2tunes transistor MP1for decreased transfer time so that the output voltage reaches a desired value in each pump cycle. In effect, the control signal TC2adjusts the charge rate dependent on operating mode.

The control signals ϕ1-ϕ4are generated by a control signal generation circuit230. The circuit230may, for example, comprise a logic circuit or microcontroller circuit. The circuit230receives the AC control signal208generated by the digital controller circuit200and generates from that AC control signal208and a sensing of the Vddh voltage level the various control signals ϕ1-ϕ4with appropriate timings of edges to control switching of the transistors MN1, MN2, MP1and MP2to effectuate boosting of the input Vdd voltage level to generate the output Vddh voltage level.

AlthoughFIG. 4shows the control signals TC1and TC2as being generated by the control signal generator230, this is by example only. The control signals TC1and TC2could alternatively be generated by some other control circuit for the system responsive to a sensing of or setting of the operation mode for the panel12.

The charge pump circuit204further includes a voltage sensing circuit in the form of a resistive voltage divider comprised of series connected resistors R1and R2coupled between the output node226and the ground voltage. The intermediate node232of the series connected resistors R1and R2is a tap node outputting sensed voltage Vsense that is a fraction of the Vddh voltage level. A voltage comparator circuit240has an inverting input terminal coupled to the intermediate node232and a non-inverting input terminal coupled to receive a reference voltage VCM. The voltage comparator circuit240outputs a control signal Vcomp. The reference voltage may, for example, comprise a common mode voltage for the touch screen system10generated by a bandgap voltage generator circuit in a manner well known to those skilled in the art. The resistive voltage divider R1/R2and voltage comparator circuit240function to sense the Vddh voltage level in comparison to a threshold voltage and generate the output control signal Vcomp indicative of that comparison. When Vcomp is in a first logic state (for example, logic “1”), this means that the Vddh voltage level is less than the threshold voltage and the control signal generation circuit230is enabled for operation to generate the various control signals ϕ1-ϕ4from the AC control signal208. Conversely, when Vcomp is in a second logic state (for example, logic “0”), this means that the Vddh voltage level is greater than or equal to the threshold voltage and the control signal generation circuit230is disabled from operation.

FIG. 5shows waveforms for operation of the charge pump circuit and touch screen system. Prior to time t1, the logic states of the control signals ϕ1-ϕ4cause transistors MN1and MN2to be turned on (with transistors MP1and MP2turned off) and thus the voltage Vdd is stored across the flyback capacitor Cfly. At time t1, the digital controller circuit200asserts the AC drive signal VTX and the AC control signal208is simultaneously asserted. The driver circuit22receives the AC drive signal VTX, performs the level shifting operation and asserts the AC drive signal Vdrive. The level shifting and drive operation performed by the driver circuit22causes a drop in the Vddh voltage level (reference250). The voltage drop is sensed by the resistive voltage divider R1/R2and voltage comparator circuit240, with the output Vcomp of the voltage comparator circuit240being asserted at time t2. The control signal generation circuit230is thus enabled for operation to generate logic state changes for the various control signals ϕ1-ϕ4responsive to the assertion of the AC control signal208. The change in logic states of the control signals ϕ1-ϕ4near time t2causes transistors MP1and MP2to be turned on (with transistors MN1and MN2turned off). The Vddh voltage is applied to the second plate of the flyback capacitor Cfly, and the first plate of the flyback capacitor Cfly is connected to the output node226. Twice the Vddh voltage minus threshold voltage losses is supplied at the output node226and charge sharing occurs with the tank capacitor Ctank. As a result, the output voltage Vddh at the output node is boosted to recover from the voltage drop250.

In a preferred embodiment, only one full cycle252of the generation of the control signals ϕ1-ϕ4is performed in response to the AC control signal208and the assertion of the output Vcomp signal. In this context, one full cycle means one period such that one pulse254(with two edges) of each of the control signals ϕ1-ϕ4occurs. The single full cycle is sufficient to cause the charge pump circuit204to boost the Vddh voltage level (reference258).

The slew-rate of the charge transfer between times t2and t3is controlled by the tuning of transistor MP1using control signal TC2. At time t3, the Vddh voltage level has recovered to the point where the Vddh voltage level exceeds the threshold. The output Vcomp of the voltage comparator circuit240is then deasserted. The charge pump circuit204is disabled and the control signal generation circuit230responds to the change in state of the output Vcomp by changing the logic state of the control signals ϕ1-ϕ4. Transfer of charge from the flyback capacitor Cfly to the tank capacitor Ctank terminates because transistor MP2is turned off. The current logic states of the control signals ϕ1-ϕ4after time t3accordingly cause transistors MN1and MN2to be turned on (with transistors MP1and MP2turned off) and thus the voltage Vdd is again stored across the flyback capacitor Cfly. The operation of the charge pump circuit204to charge the flyback capacitor Cfly, boost and then dump charge to tank capacitor Ctank is accordingly performed synchronous to the assertion of the AC drive signal Vdrive and responsive to sensing the voltage level of the Vddh voltage.

At time t4, the digital controller circuit200deasserts the AC drive signal VTX and the AC control signal208is simultaneously deasserted. The driver circuit22responds to the AC drive signal VTX and deasserts the AC drive signal Vdrive. The Vddh voltage level recovers sufficiently from the charge sharing after boosting and settles prior to the time t5that the C2V converter circuit30operates to sense the charge at the sense capacitor18and convert the sensed charge to an output voltage indicative of the sensed charge.

Thus, in operation, the enabling of the charge pump circuit204for operation to apply the boosted voltage to the output node226occurs synchronous to the assertion of the AC drive signals VTX and Vdrive. The switching control signals ϕ1-ϕ4of the charge pump circuit204have a same frequency as the AC control signal208(and thus a same frequency as the AC drive signals VTX and Vdrive).

In an example implementation, the Vdd voltage level is 3.3V, the Vddh voltage level is 6.1 V, the logic low voltage level of the AC control signal208, AC drive signal VTX, AC drive signal Vdrive and Vcomp signal is 0V, the logic high voltage level of the AC control signal208, AC drive signal VTX and Vcomp signal is 3.3V, the logic high voltage level of the AC drive signal Vdrive is 6.1V, the logic low voltage level of the switching control signals ϕ2and ϕ3is 0V, the logic high voltage level of the switching control signals ϕ2and ϕ3is 3.3V, the logic low voltage level of the switching control signals ϕ1and ϕ4is 3.3V, and the logic high voltage level of the switching control signals ϕ1and ϕ4is 6.1V. It is accordingly noted that the switching control signals ϕ1and ϕ4are bootstrapped signals generated by the control signal generation circuit230.

With reference to the waveforms for the control signals ϕ1-ϕ4, it will be noted that the edges of the signals are not aligned. This is purposeful in order to ensure that the control signals are not overlapping.

The MP1transistor is tunable transistor responsive to the control signal TC2in order to set the resistive-capacitive (RC) time constant of the circuit (where R is the on-resistance of the transistor and C is the capacitive load). The tuning of the transistor comprises changing the transistor drive which affects the on-resistance. The concern here is that if the RC time constant is too small, the charge pump will react too quickly and the inherent latency of the voltage comparator circuit240will cause the pumped Vddh voltage level to exceed the threshold set by the resistive voltage divider R1/R2and VCM. Conversely, if the RC time constant is too large, the charge pump will react too slowly and the pumped Vddh voltage level will not reach the threshold set by the resistive voltage divider R1/R2and VCM.

The tuning of the transistor MP1may, for example, be performed in connection with the start-up of the circuit in dependence on an indication of whether the panel12is operating in the mutual capacitance sensing mode or the self capacitance sensing mode.

The implementation shown inFIG. 2is specific to operation of the panel12in a mutual-capacitance mode of operation where the sensed capacitance is between two selected lines14and16at the sense capacitor18. The synchronized charge pump circuit204is equally applicable to a panel12operating in a self-capacitance mode of operation. Such a configuration is illustrated inFIG. 6. In self-capacitance mode, the C2V converter circuit30senses the charge at a selected one of the drive or sense lines14,16relative to a ground plane of the panel12. The illustration of the circuits inFIG. 6shows the configuration for the lines14. The circuitry is duplicated for the lines16(not shown). In self-capacitance mode, the amount of charge at a given line14or16is a function of the AC drive signal, the capacitance between the line14or16and the ground plane and the influence of a touch capacitance contributed by the presence of an object (such as a finger or stylus) in proximity to the lines14and16of the panel12.

There are a number of advantages which accrue from synchronization of the charge pump circuit204to the AC drive signals and adaptability of charge transfer time to different loading conditions: a) the operating behavior of the circuit is repetitive and thus does not inject unwanted switching noise which can be a concern with prior art charge pump circuit like that shown inFIG. 1; b) there is a decrease in power consumption because the Vddh voltage is regulated by the charge pump circuit only when necessary (specifically coincident with the assertion of the AC drive signals on the panel lines); c) charge is transferred in a single cycle as opposed to multiple cycles as inFIG. 1; and d) the timing of the assertion of the AC drive signals is known and regular and thus the circuit effectively anticipates the need to regulate the Vddh voltage and performs this operation only when needed.

With respect to adaptability of charge transfer time to different loading conditions: The voltage boosting circuit adapts the voltage boosting operation to the mutual-capacitance sensing mode of operation by tuning charge transfer time (slew-rate) so that over-pumping is reduced and a charge pump waveform is periodic in each pump cycle. Furthermore, the voltage boosting circuit adapts the voltage boosting operation to the self-capacitance sensing mode of operation by tuning charge transfer time (slew-rate) so that an output reaches a certain value in each pump cycle.