Variably controlled delay line for read data capture timing window

Disclosed is a method and circuit for variably controlling a delay line for a read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal.

BACKGROUND OF THE INVENTION

FIG. 1illustrates a microprocessor10coupled to a memory device12via data bus14. Data bus14includes a plurality of conductive lines (not shown) for transmitting data bit signals and a strobe signal in parallel between memory device12and microprocessor10. As used herein, a memory device may include SRAMs, DRAMs, or other memory capable of storing digital data.

Microprocessor10includes a plurality of input/output (“I/O”) devices (not shown inFIG. 1) coupled to respective conductive lines of data bus14. These I/O devices are capable of transmitting or receiving data bit signals.FIG. 2shows relevant components of I/O devices of microprocessor10. More particularly,FIG. 2shows a plurality of FIFOs20(0) through20(n) each one of which is contained in a respective I/O device.FIG. 2also shows a strobe buffer22. Lastly,FIG. 2shows a plurality of data buffers24(0) through24(n) each one of which is contained in a respective I/O device.

Data buffers24(0) through24(n) are coupled between respective data inputs of FIFOs20(0) through20(n) and respective conductive lines of data bus14. The output of strobe buffer22is coupled between a conductive line of data bus14and FIFOs20(0) through20(n). For purposes of definition, two devices (e.g., a buffer and a FIFO) may be coupled together directly by a conductor or data link, or indirectly via a third device. For example,FIG. 2show data buffers24(0) through24(n) coupled directly to data inputs of FIFOs20(0) through20(n), respectively. Further, although not shown, buffers24(0) through24(n) are coupled indirectly to respective data bus lines via output bumps of microprocessor10and conductive traces of a semiconductor packaging in which microprocessor is contained.

Data bus14transmits the strobe signal in parallel with data bit signals. The strobe signal is essentially a clock having a 50% duty cycle. Memory12transmits data at a double data rate (DDR). More particularly, I/O devices of memory12transmit a set of data bit signals Din(0) through Din(n) with each transition edge (i.e., a rising edge and falling edge) of the strobe signal.

Data bit signals Din(0) through Din(n) are received by data buffers24(0) through24(n) around the same time strobe buffer22receives the transition edges of the strobe signal. Buffers22and24(0) through24(n), when the enable signal provided thereto are asserted, transmit the strobe signal and data bit signals Din(0) through Din(n) to FIFOs20(0) through20(n).

FIFOs20(0) through20(n) capture or store data bit signals Din(0) through Din(n), respectively, upon the transition edges of the strobe signal provided thereto by strobe buffer22. FIFOs20(0) through20(n) store data bit signals Din(0) through Din(n), respectively, for subsequent processing by the core of microprocessor10. It is essential that that FIFOs20(0) through20(n) receive the transition edges of the strobe signal during a read data capture timing window. The read data capture timing window is a period of time when: (1) all data bit signals Din(0) through Din(n) are present at the inputs of FIFOs20(0) through20(n) with sufficient set-up time before FIFOs20(0) through20(n) receive transition edges of the strobe signal from buffer22, and; (2) all data bit signals Din(0) through Din(n) are present at the inputs of FIFOs20(0) through20(n) with sufficient hold time after FIFOs20(0) through20(n) receive the transition edges of the strobe signal from buffer22. If the transition edges of the strobe signal do not arrive at FIFOs20(0) through20(n) during the read capture timing window, false data will be stored in FIFOs20(0) through20(n).

Transmission of the strobe signal and data bit signals Din(0) through Din(n) between memory device12and FIFOs20(0) through20(n), are subject to unexpected delays. Because of relative delays in the transmission of the data bit signals Din(0) through Din(n) to the inputs of FIFOs20(0) through20(n), the read capture timing window may be substantially small. Additionally, because of unexpected delays, the transition edges of the strobe signal may arrive at FIFOs20(0) through20(n) with an unexpected delay relative to the read capture timing window.

A variety of factors induce transmission delay in the data bit and strobe signals. For example, the conductive line of bus14that transmits the strobe signal may be shorter or longer in length than one or more of the conductive lines of bus14that transmit the data bit signals. Another source of relative signal delay relates to variations in the process used to manufacture microprocessor10. Microprocessors are manufactured using complex equipment and processes. Variations in the equipment and processes may result in unexpected physical variations of the structure of, for example, the transistors in strobe buffer22. These physical variations in transistor structure may introduce unexpected delays in the strobe signal transmitted through strobe buffer22.

The unexpected delays described above are fixed. Delays in the strobe and data bit signals may vary. For example, delays in the strobe signal may vary during operation of the microprocessor due to changes in temperature of strobe buffer22or changes in the power supply voltage provided to strobe buffer22. Increases in operating temperature of strobe buffer22will typically increase delay in strobe signal transmission therethrough, and vice versa. An increase power supply voltage provided to strobe buffer22will typically decrease delay in strobe signal transmission therethrough, and vice versa.

As noted above, the transition edges of strobe signal and the data bit signals Din(0) through Din(n) are received by buffers of microprocessor12around the same point in time.FIG. 3is a timing diagram illustrating the data bit signal Din(0) and the strobe signal provided to inputs of FIFO20(0). Except for relative delays between data signals, inputs to the remaining FIFOs20(1) through20(n) are identical. Strobe buffer22is designed to delay transmission of the strobe signal by a fixed amount of time (e.g., 25% of the strobe signal's duty cycle) so that FIFOs20(0) through20(n) receive the transition edges (e.g., rising edge at time=t1) within a read capture timing window thereof.

FIG. 3illustrates the relative effects of unexpected delays on the strobe signal. InFIG. 3, unexpected delays may cause the transition edges of the strobe signal to move in time relative to data bit signal Din(0) in either the Dpositiveor Dnegativedirections by an undetermined magnitude. Unfortunately, if the magnitude of Dpositiveor Dnegativeis great enough, the transition edges of the strobe signal may fall outside the read capture timing window.

SUMMARY OF THE INVENTION

Disclosed is a method and circuit for variably controlling a delay line for read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal.

DETAILED DESCRIPTION

Computer systems, including computer servers, employ one or more microprocessors coupled to one or more memory devices, via a serial or parallel data bus. The present invention will be described with reference to a microprocessor coupled to a memory device via a parallel data bus, it being understood that the present invention should not be limited thereto. The term device includes circuits of transistors coupled together to perform an electronic function.

FIG. 4is a block diagram illustrating a microprocessor26coupled to a memory device30via a data bus32. Microprocessor26employs the present invention. The present invention may find application in devices other than a microprocessor and should not be limited to use in a microprocessor. For example, the present invention may find application in memory30.

Data bus32includes a plurality of conductive lines (not shown) for transmitting data bit signals and a strobe signal in parallel between memory device30and microprocessor26. Microprocessor26includes a plurality of I/O devices (not shown inFIG. 4) coupled to respective conductive lines of data bus32. These I/O devices are capable of transmitting or receiving data bit signals.

FIG. 5shows relevant components of I/O devices of microprocessor10. More particularly,FIG. 5shows a plurality of FIFOs34(0) through34(n) each one of which is contained in a respective I/O device.FIG. 5shows a plurality of data buffers36(0) through36(n) each one of which is contained in a respective I/O device of microprocessor26.FIG. 5shows a strobe buffer40. Lastly,FIG. 5shows a variable control delay circuit42.

Data buffers36(0) through36(n) are coupled between respective data inputs of FIFOs34(0) through34(n) and respective conductive lines of data bus32. Although not shown, buffers36(0) through36(n) are coupled to respective data bus lines via output bumps of microprocessor26and conductive traces of a semiconductor packaging in which microprocessor26is contained. The output of strobe buffer40is coupled between a conductive line of data bus14and variable delay circuit42. The output of variable delay circuit42is coupled to FIFOs34(0) through34(n).

Data bus32transmits the strobe signal in parallel with data bit signals. In one embodiment, the strobe signal is essentially a clock signal having a 50% duty cycle. Memory30transmits data at DDR. The present invention, it is understood, should not be limited to use in a system employing a DDR data bus.

Data bit signals Din(0) through Din(n) are received by data buffers36(0) through36(n) around the same time strobe buffer40receives transition edges of the strobe signal. Buffers36(0) through36(n), when the enable signals provided thereto are asserted, transmit the strobe signals and data bit signals Din(0) through Din(n) to FIFOs34(0) through34(n). Buffer40transmits the strobe signal to variable delay circuit42. Variable delay circuit42transmits the strobe signal to FIFOs34(0) through34(n).

FIFOs34(0) through34(n) capture or store data bit signals Din(0) through Din(n), respectively, upon the transition edges of the strobe signal provided thereto by variable delay circuit42. It is essential that FIFOs34(0) through34(n) receive the transition edges of the strobe signal during the read capture timing window thereof.

The data bit signals Din(0) through Din(n) and/or the strobe signal may be subject to one or more of the unexpected fixed or variable delays mentioned above. Variable delay circuit42operates to offset the one or more unexpected fixed or variable delays of strobe signal transmission.FIG. 6is a timing diagram illustrating the data bit signal Din(0) and the strobe signal provided to inputs of FIFO34(0). Except for relative delays between data signals, inputs to the remaining FIFOs34(1) through34(n) are identical.FIG. 6shows the strobe signal after delayed transmission by variable delay circuit42. Variable delay circuit delays the strobe signal by a first delay time in response to receiving a first variable delay control code. Ideally, the strobe signal is delayed by variable delay circuit42so that its transition edges (e.g., the falling edge at time=t2) fall within the read capture timing window of FIFOs34(1) through34(n).

With continuing reference toFIGS. 5 and 6, during operation, one or more variable delays may unexpectedly cause the transition edges of the strobe signal to drift in either the Dpositiveor Dnegativedirections by an undetermined magnitude. For example, the temperature of strobe buffer40may decrease or the magnitude of the power supply provided to buffer40may increase thereby causing the transition edges of the strobe signal to drift in the Dnegativedirection. This drift may cause the transition edges to fall outside the read capture timing window. In response to a decrease in temperature, an increase in the power supply voltage, or both, a second variable delay code may be generated. The variable delay circuit42receives the second variable delay code, and in response variable delay circuit42increases the delay of strobe signal transmission therethrough so that the transition edges of the strobe signal move in the Dpositivedirection. After further operation, the temperature of strobe buffer40may increase or the magnitude of the power supply provided to buffer40may decrease thereby causing the transition edges of the strobe signal to drift in the Dpositivedirection. This drift may cause the transition edges to again fall outside the read capture timing window. In response to an increase in temperature, a decrease in the power supply voltage, or both, a third variable delay code may be generated. The variable delay circuit42receives the third variable delay code, and in response variable delay circuit42decrease the delay of strobe signal transmission therethrough so that the transition edges of the strobe signal move in the Dnegativedirection.

A variable delay control code generator (not shown) is provided for generating an initial and subsequent variable control delay codes to variable delay circuit42. In one embodiment, the variable delay control code generator generates the initial variable delay control code in response to: an initial temperature of the variable delay control code generator, the microprocessor26, the strobe buffer42, and/or one or more of the data buffers34(0) through34(n); an initial magnitude of the power supply voltage provided to the variable delay circuit, the microprocessor10, the strobe buffer and/or one or more of the data buffers34(0) through34(n); unexpected variations in the transistors that form the variable delay control code generator, the microprocessor26, the strobe buffer42, and/or one or more of the data buffers34(0) through34(n); or other factors; or any combination of the foregoing factors. In one embodiment, the variable delay code generator generates the subsequent variable delay codes in response to: a change in temperature of the variable delay control code generator, the microprocessor26, the strobe buffer42, and/or one or more of the data buffers34(0) through34(n); a change in the magnitude of the power supply voltage provided to the variable delay circuit, the microprocessor10, the strobe buffer and/or one or more of the data buffers34(0) through34(n); or any combination of the foregoing factors. In one embodiment, the variable delay control code represents an average of a pull up control code and a pull down control code. The pull up and pull down control codes can be generated by circuits described in U.S. Pat. No. 6,060,907 which is incorporated herein by reference in its entirety. The average of pull up and pull down control codes can be generated by a circuit described in copending U.S. patent application Ser. No. 10/158,695 filed May 30, 2002, entitled Average Code Generation Circuit by Cong Khieu and Louise Gu, which is incorporated herein by reference in its entirety.

Variable delay circuit42, as noted above, operates to adjust strobe signal delay in accordance with the variable delay code provided thereto.FIG. 7illustrates in block diagram form, one embodiment of the variable delay circuit42. More particularly, variable delay circuit42ofFIG. 7includes controllable delay circuits44(0) through44(m) coupled in series between strobe signal input and a strobe signal output. In operation, controllable delay circuit44(0) receives the strobe signal. Controllable delay circuits44(0) through44(m) receive control bits CB(0) through CB(m), respectively, of the variable delay control code provided to variable delay circuit42.

In one embodiment, each controllable delay circuit44(0) through44(m) transmits the strobe signal provided at its input via a short transmission delay circuit or a long transmission delay circuit. The transmission delays of the two circuits are distinct from each other. The transmission circuit used to transmit the strobe signal in each of the delay circuits44(0) through44(m) depends on the control bit provided thereto. For example, controllable delay circuit44(0) transmits the strobe signal to controllable delay circuit44(1) via the short transmission delay circuit of controllable delay circuit44(0) if CB(0) provided thereto is as a logical one. In contrast, if CB(0) is provided to controllable delay circuit44(0) as a logical zero, then controllable delay circuit44(0) transmits the strobe signal via its long transmission delay circuit. Each of the controllable delay circuits44(0) through44(m) operates in a substantially similar manner.

The time delay of the short transmission delay circuits in the controllable delay circuits44(0) through44(m) may be equal to each other in one embodiment or different from each other in another embodiment. The time delay of the long transmission delay circuits of the controllable delay circuits44(0) through44(m) may be equal to each other in one embodiment or different from each other in another embodiment.

FIG. 8illustrates one embodiment of one of the controllable delay circuits44(x) shown inFIG. 7. More particularly,FIG. 8shows an inverting gate52, a long transmission delay circuit54, a short transmission delay circuit56, a multiplexer60, and an inverting gate62. The long transmission delay circuit54has an input and an output between which a signal is transmitted. Signals are transmitted through long transmission delay circuit54with a time delay Tlong. Short transmission delay circuit includes an input and an output between which signals are transmitted with a time delay Tshort. Tlongis greater than Tshort.

The outputs of the long and short transmission delay circuits54and56, respectively, are provided to inputs of multiplexer60. A selector input or a control input receives one of the bits CB(x) of the variable delay control code. In response to receiving CB(x), multiplexer60selects or multiplexes one of the inputs to its output, which in turn is provided to inverting gate62. Thus, controllable delay circuit44shown inFIG. 8has a variable delay between its input and output which depends upon the state of the control bit CB(x) provided thereto.

FIG. 9illustrates one embodiment of a controllable delay circuit44(x) shown inFIG. 8. More particularly,FIG. 9shows that multiplexer60consists of a pair of n-channel field effect transistors (FETs)64and66and a pair of p-channel FETs70and72. The long transmission delay circuit54shown inFIG. 9includes a pair of inverter gates74and76, n-channel FET80, and p-channel FET82. It is noted that the inverse of control bit CB(x) is provided to the gates of n-channel FET64and p-channel FET72. The inverse of CB(x) may be provided by a separate inverter (not shown) contained within the controllable delay circuit44(x) shown inFIG. 9. As will be appreciated by one of ordinary skill in the art, the signal transmission delay of circuit54, will be longer than the signal delay transmission of circuit56.

FIG. 10illustrates another embodiment of the controllable delay circuit44(x) ofFIG. 8. The long transmission delay circuit54shown inFIG. 10includes inverter gates84and86, and capacitor90. The short transmission delay circuit56shown inFIG. 10, like the short transmission delay circuit56shown inFIG. 9, consists of only a conductor. As can be appreciated by one of ordinary skill in the art, the signal transmission delay associated with circuit54shown inFIG. 10will be substantially longer than the signal transmission delay of the conductor of circuit56.

FIG. 11illustrates another embodiment of one of the controllable delay circuits44(x) shown inFIG. 7. More particularly, the controllable delay circuit44(x) shown inFIG. 11includes a pair of inverting gates92and94, an n-channel FET96, p-channel FET100, and a capacitor102. The gate of p-channel FET100receives one bit CB(x) of the multi-bit variable control code, while the gate of n-channel FET96receives the inverse of CB(x).

Although the present invention has been described in connection with several embodiments, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the spirit and scope of the invention as defined by the appended claims.