SEMICONDUCTOR PACKAGE FOR PERFORMING TRAINING OPERATION

A semiconductor package includes a first memory device configured to output master data after the start of a training operation, and a second memory device configured to sample internal data based on the master data after the start of the training operation, configured to store test codes that adjust a time point at which the internal data are output when a time point at which the master data are output and the time point at which the internal data are output become identical with each other, and configured to program the stored test codes when the training operation is terminated.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2022-0098596, filed in the Korean Intellectual Property Office on Aug. 8, 2022, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

The present disclosure relates to a semiconductor package for performing a training operation for making identical operating speeds of multiple memory devices.

A semiconductor memory device is a memory device that is implemented by using a semiconductor, such as silicon, germanium, gallium arsenide, or indium phosphide. The semiconductor memory device may be basically divided into a volatile memory device and a nonvolatile memory device. The volatile memory device is a memory device in which data stored therein is lost when power supplied to the memory device is blocked. The volatile memory device includes static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. The nonvolatile memory device is a memory device in which data stored therein is retained although power supplied to the memory device is blocked. The nonvolatile memory device includes read only memory (ROM), programmable ROM (PROM), electrically PROM (EPROM), electrically erasable and programmable ROM (EEPROM), a flash memory device, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

In general, access to a memory device may be performed through a controller. For example, after the start of data read for the memory device, a host may transmit a read command and an address to the controller. The controller may read data from the memory device and then transmit the read data to the host. After the start of data write for the memory device, the host may transmit a write command, write data, and an address to the controller. The controller may write the write data in the memory device. In such an access process for the memory device, clock signals for strobing data that are input and output in memory devices may be generated at different time points due to a process, voltage, temperature (PVT) variation. Accordingly, it is necessary to perform a training operation that adjusts time points at which the clock signals are generated to be identical.

SUMMARY

In an embodiment, a semiconductor package may include a first memory device configured to output master data after the start of a training operation, and a second memory device configured to sample internal data based on the master data after the start of the training operation, configured to store test codes that adjust a time point at which the internal data are output when a time point at which the master data are output and a time point at which the internal data are output become identical, and configured to program the stored test codes when the training operation is terminated.

In another embodiment, a semiconductor package may include a first memory device configured to sample first internal data based on master data after the start of a training operation and configured to program, in multiple electrical fuses, test codes that adjust a time point at which the first internal data are output when a time point at which the master data are output and the time point at which the first internal data are output become identical, and a second memory device configured to sample second internal data based on the master data after the start of the training operation and configured to program, in multiple electrical fuses, test codes that adjust a time point at which the second internal data are output when a time point at which the master data are output and a time point at which the second internal data are output become identical.

In still another embodiment, a semiconductor package may include a controller configured to output chip IDs having the same logic level combination after the start of a training operation and configured to output test codes that are sequentially counted, and a semiconductor package including a semiconductor device having multiple memory devices. The multiple memory devices are simultaneously enabled based on the chip IDs after the start of the training operation, and the multiple memory devices program the respective test codes when time points at which multiple internal data are output and a time point at which master data are output become identical by adjusting a delay based on the test codes.

DETAILED DESCRIPTION

In the descriptions of the following examples, the term “preset” indicates that the numerical value of a parameter is previously decided, when the parameter is used in a process or algorithm. According to an embodiment, the numerical value of the parameter may be set when the process or algorithm is started or while the process or algorithm is performed.

Terms such as “first” and “second,” which are used to distinguish among various components, are not limited by the components. For example, a first component may be referred to as a second component, and vice versa.

When one component is referred to as being “coupled” or “connected” to another component, it should be understood that the components may be directly coupled or connected to each other or coupled or connected to each other through another component interposed therebetween. On the other hand, when one component is referred to as being “directly coupled” or “directly connected” to another component, it should be understood that the components are directly coupled or connected to each other without another component interposed therebetween.

A “logic high level” and a “logic low level” are used to describe the logic levels of signals. A signal having a “logic high level” is distinguished from a signal having a “logic low level.” For example, when a signal having a first voltage corresponds to a signal having a “logic high level,” a signal having a second voltage may correspond to a signal having a “logic low level.” According to an embodiment, a “logic high level” may be set to a voltage higher than a “logic low level.” According to an embodiment, the logic levels of signals may be set to different logic levels or opposite logic levels. For example, a signal having a logic high level may be set to have a logic low level in some embodiments, and a signal having a logic low level may be set to have a logic high level in some embodiments.

Hereafter, the teachings of the present disclosure will be described in more detail through embodiments. The embodiments are only used to exemplify the teachings of the present disclosure, and the scope of the present disclosure is not limited by the embodiments.

The present disclosure provides a semiconductor package for programming a test code when time points at which master data that are output by one of multiple memory devices and internal data that is generated within the remaining memory devices are identical after the start of a training operation.

According to the present disclosure, operating speeds of multiple memory devices can be adjusted to be identical by programming a test code when time points at which master data that are output by one of multiple memory devices and internal data that is generated within the remaining memory devices are identical after the start of a training operation.

Furthermore, according to the present disclosure, an error of data input and output operations in a normal operation can be prevented by adjusting operating speeds of multiple memory devices to be identical by programming a test code when time points at which data that are output by the multiple memory devices is input are identical after the start of a training operation.

FIG.1is a block diagram illustrating a construction of a semiconductor package1according to an example of the present disclosure. As illustrated inFIG.1, the semiconductor package1may include a controller10and a semiconductor device20. The semiconductor device20may include a first memory device210, a second memory device220, a third memory device230, and a fourth memory device240.

The controller10may output a chip ID CID and a test code TM for performing a training operation to the first memory device210, the second memory device220, the third memory device230, and the fourth memory device240. The controller10may output a command (not illustrated) and an address (not illustrated) for performing a normal operation to the first memory device210, the second memory device220, the third memory device230, and the fourth memory device240. The controller10may output data (not illustrated) for performing the normal operation to the first memory device210, the second memory device220, the third memory device230, and the fourth memory device240. The controller10may receive data (not illustrated) from the first memory device210, the second memory device220, the third memory device230, and the fourth memory device240in the normal operation. The training operation may be set as an operation that adjusts operating speeds of the first memory device210, the second memory device220, the third memory device230, and the fourth memory device240to be equal by adjusting time points at which data that are input to and output by the first memory device210, the second memory device220, the third memory device230, and the fourth memory device240to be identical. The normal operation may include a common write operation, read operation, refresh operation, etc.

The first memory device210may be implemented as a master device. The first memory device210may be activated by a chip ID CID after the start of a training operation and may output master data MD to the second memory device220, the third memory device230, and the fourth memory device240.

The second memory device220may be implemented as a slave device. The second memory device220may be activated by a chip ID CID after the start of a training operation and may store a test code TM when time points at which master data MD and internal data (not illustrated) that are output within the second memory device220are output becomes identical. The second memory device220may program a test code TM that is stored when the training operation is terminated. Based on the programmed test code TM, the second memory device220may adjust a time point at which the internal data (not illustrated) is output.

The third memory device230may be implemented as a slave device. The third memory device230may be activated by a chip ID CID after the start of a training operation and may store a test code TM when time points at which master data MD and internal data (not illustrated) that are output within the third memory device230are output become identical. The third memory device230may program a test code TM that is stored when the training operation is terminated. Based on the programmed test code TM, the third memory device230may adjust a time point at which the internal data (not illustrated) is output.

The fourth memory device240may be implemented as a slave device. The fourth memory device240may be activated by a chip ID CID after the start of a training operation and may store a test code TM when time points at which master data MD and internal data (not illustrated) that are output within the fourth memory device240are output become identical. The fourth memory device240may program a test code TM that is stored when the training operation is terminated. Based on the programmed test code TM, the fourth memory device240may adjust a time point at which the internal data (not illustrated) is output.

Operating speeds of the first memory device210, the second memory device220, the third memory device230, and the fourth memory device240may be differently set based on a PVT variation.

The controller10and the semiconductor device20shown inFIG.1are included in one package, but in other embodiments, the controller10and the semiconductor device20may be configured as separate packages.

FIG.2is a block diagram illustrating a construction according to an embodiment of the first memory device210. As illustrated inFIG.2, the first memory device210may include a first input/output control circuit (I/O CTR1)211, a first clock generation circuit (CLK GEN1)212, a first core circuit (CORE1)213, first to fourth master transmitters T211to T214, first to fourth master receivers R211to R214, and first to fourth master pads P211to P214.

The first input/output control circuit211may generate first to fourth master transmission control signals MT<1:4> and first to fourth master reception control signals MR<1:4> that are selectively enabled based on first and second chip IDs CID<1:2> that are input after the start of a normal operation. Combinations of logic levels of the first and second chip IDs CID<1:2> that are input after the start of the normal operation are specifically described with reference toFIG.3.

The first clock generation circuit212may generate a first internal clock ICLK1based on the first to fourth test codes TM<1:4> after the start of a training operation. The first clock generation circuit212may generate the first internal clock ICLK1with a fixed delay when first to fourth test codes TM<1:4> are input after the start of the training operation.

The first core circuit213may be activated by the first and second chip IDs CID<1:2> after the start of a training operation and may output master data MD that has been stored in the first core circuit213in synchronization with the first internal clock ICLK1. The first core circuit213may be activated by the first and second chip IDs CID<1:2> after the start of a write operation of a normal operation and may store the master data MD in synchronization with the first internal clock ICLK1. The first core circuit213may be activated by the first and second chip IDs CID<1:2> after the start of a read operation of a normal operation and may output the master data MD that has been stored in the first core circuit213in synchronization with the first internal clock ICLK1. The first core circuit213may be implemented as a common core circuit and may include a command decoder, an address decoder, a data input/output control circuit, etc. that are activated by the first and second chip IDs CID<1:2>. The command decoder, the address decoder, the data input/output control circuit, etc. that are included in the first core circuit213may be activated by the first and second chip IDs CID<1:2> having the same logic level combination after the start of a training operation. The command decoder, the address decoder, the data input/output control circuit, etc. that are included in the first core circuit213may be activated by the first chip ID CID<1> having a logic low level and the second chip ID CID<2> having a logic low level after the start of a normal operation.

The first master transmitter T211and the first master receiver R211may be connected to the first master pad P211. The first master transmitter T211may be activated when the first master transmission control signal MT<1> is enabled and may output the master data MD through the first master pad P211. The first master receiver R211may be activated when the first master reception control signal MR<1> is enabled and may generate the master data MD by receiving data from the first master pad P211.

The second master transmitter T212and the second master receiver R212may be connected to the second master pad P212. The second master transmitter T212may be activated when the second master transmission control signal MT<2> is enabled and may output the master data MD through the second master pad P212. The second master receiver R212may be activated when the second master reception control signal MR<2> is enabled and may generate the master data MD by receiving data from the second master pad P212.

The third master transmitter T213and the third master receiver R213may be connected to the third master pad P213. The third master transmitter T213may be activated when the third master transmission control signal MT<3> is enabled and may output the master data MD through the third master pad P213. The third master receiver R213may be activated when the third master reception control signal MR<3> is enabled and may generate the master data MD by receiving data from the third master pad P213.

The fourth master transmitter T214and the fourth master receiver R214may be connected to the fourth master pad P214. The fourth master transmitter T214may be activated when the fourth master transmission control signal MT<4> is enabled and may output the master data MD through the fourth master pad P214. The fourth master receiver R214may be activated when the fourth master reception control signal MR<4> is enabled and may generate the master data MD by receiving data from the fourth master pad P214.

FIG.3is a table for describing logic levels of the first and second chip IDs CID<1:2> after the start of a normal operation and a training operation according to an example.

After the start of a normal operation, in order to activate the first memory chip210, the logic level of the first chip ID CID<1> may be input as a logic low level L, and the logic level of the second chip ID CID<2> may be input as a logic low level L. After the start of the normal operation, in order to activate the second memory chip220, the logic level of the first chip ID CID<1> may be input as a logic high level H, and the logic level of the second chip ID CID<2> may be input as a logic low level L. After the start of the normal operation, in order to activate the third memory chip230, the logic level of the first chip ID CID<1> may be input as a logic low level L, and the logic level of the second chip ID CID<2> may be input as a logic high level H. After the start of the normal operation, in order to activate the fourth memory chip240, the logic level of the first chip ID CID<1> may be input as a logic high level H, and the logic level of the second chip ID CID<2> may be input as a logic high level H.

After the start of the normal operation, in order to selectively activate the first to fourth memory chips210to240, the logic levels of the first and second chip IDs CID<1:2> may be input as different logic level combinations.

After the start of a training operation, in order to activate the first memory chip210, the logic level of the first chip ID CID<1> may be input as a logic low level L, and the logic level of the second chip ID CID<2> may be input as a logic low level L. After the start of the training operation, in order to activate the second memory chip220, the logic level of the first chip ID CID<1> may be input as a logic low level L, and the logic level of the second chip ID CID<2> may be input as a logic low level L. After the start of the training operation, in order to activate the third memory chip230, the logic level of the first chip ID CID<1> may be input as a logic low level L, and the logic level of the second chip ID CID<2> may be input as a logic low level L. After the start of the training operation, in order to activate the fourth memory chip240, the logic level of the first chip ID CID<1> may be input as a logic low level L, and the logic level of the second chip ID CID<2> may be input as a logic low level L.

After the start of the training operation, in order to activate all of the first to fourth memory chips210to240, the logic levels of the first and second chip IDs CID<1:2> may be input as the same logic level combination.

FIG.4is a block diagram illustrating a construction according to an embodiment of the first input/output control circuit211. As illustrated inFIG.4, the first input/output control circuit211may include a master ID generation circuit (MID GEN)310and a first decoder320(DEC1).

The master ID generation circuit310may receive the first and second chip IDs CID<1:2> after the start of a normal operation. The master ID generation circuit310may receive the first and second chip IDs CID<1:2> when a training flag signal TF is disabled after the start of a normal operation. The master ID generation circuit310may generate first and second master IDs MID<1:2> by latching the first and second chip IDs CID<1:2> that have been input in a normal operation after the start of a training operation. The master ID generation circuit310may generate the first and second master IDs MID<1:2> by latching the first and second chip IDs CID<1:2> that have been input in a normal operation when the training flag signal TF is enabled after the start of a training operation.

The first decoder320may generate the first to fourth master transmission control signals MT<1:4> by decoding the first and second master IDs MID<1:2>. The first decoder320may generate the first to fourth master reception control signals MR<1:4> by decoding the first and second master IDs MID<1:2>.

FIG.5is a circuit diagram illustrating a construction according to an embodiment of the master ID generation circuit310. As illustrated inFIG.5, the master ID generation circuit310may include a first master ID generation circuit311and a second master ID generation circuit312.

The first master ID generation circuit311may be implemented as inverters311<1>,311<2>, and311<3>. The inverter311<1> may receive the first chip ID CID<1> when the logic level of the training flag signal TF is disabled to a logic low level after the start of a normal operation. The inverter311<1> may invert and output the first chip ID CID<1> that is input after the start of the normal operation. The inverters311<2> and311<3> may be implemented as a latch in which the input stages and output stages of the inverters311<2> and311<3> are connected. The inverter311<2> may invert the output signal of the inverter311<1> and may output the inverted signal as the first master ID MID<1>. The inverters311<2> and311<3> may latch the output signal of the inverter311<1> when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation. The inverted training flag signal TFB may be set as a signal that has been inverted from the training flag signal TF.

The second master ID generation circuit312may be implemented as inverters312<1>,312<2>, and312<3>. The inverter312<1> may receive the second chip ID CID<2> when the logic level of the training flag signal TF is disabled to a logic low level after the start of a normal operation. The inverter312<1> may invert and output the second chip ID CID<2> that is input after the start of a normal operation. The inverters312<2> and312<3> may be implemented as a latch in which the input stages and output stages of the inverters312<2> and312<3> are connected. The inverter312<2> may invert the output signal of the inverter312<1> after the start of a training operation and may output the inverted signal as the second master ID MID<2>. The inverters312<2> and312<3> may latch the output signal of the inverter312<1> when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation.

FIG.6is a circuit diagram illustrating a construction according to an embodiment of the first decoder320. As illustrated inFIG.6, the first decoder320may include a first logic circuit321, a second logic circuit322, a third logic circuit323, and a fourth logic circuit324.

The first logic circuit321may generate the first master transmission control signal MT<1> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a first pre-master transmission control signal MTP<1> is input as a logic high level, the logic level of the first master ID MID<1> is input as a logic low level, and the logic level of the second master ID MID<2> is input as a logic low level. The first logic circuit321may generate the first master reception control signal MR<1> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a first pre-master reception control signal MRP<1> is input as a logic high level, the logic level of the first master ID MID<1> is input as a logic low level, and the logic level of the second master ID MID<2> is input as a logic low level. The first logic circuit321may generate the first master transmission control signal MT<1> that is enabled to a logic high level when the logic level of the first pre-master transmission control signal MTP<1> is input as a logic high level after the start of a normal operation. The first logic circuit321may generate the first master reception control signal MR<1> that is enabled to a logic high level when the logic level of the first pre-master reception control signal MRP<1> is input as a logic high level after the start of a normal operation. The first pre-master transmission control signal MTP<1> and the first pre-master reception control signal MRP<1> may be set as a signal that is input as a logic high level after the start of a training operation and that is input as a logic high level when the logic level of the first chip ID CID<1> is a logic low level and the logic level of the second chip ID CID<2> is a logic low level after the start of a normal operation.

The second logic circuit322may generate the second master transmission control signal MT<2> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a second pre-master transmission control signal MTP<2> is input as a logic high level, the logic level of the first master ID MID<1> is input as a logic high level, and the logic level of the second master ID MID<2> Is input as a logic low level. The second logic circuit322may generate the second master reception control signal MR<2> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a second pre-master reception control signal MRP<2> is input as a logic high level, the logic level of the first master ID MID<1> is input as a logic high level, and the logic level of the second master ID MID<2> is input as a logic low level. The second logic circuit322may generate the second master transmission control signal MT<2> that is enabled to a logic high level when the logic level of the second pre-master transmission control signal MTP<2> is input as a logic high level after the start of a normal operation. The second logic circuit322may generate the second master reception control signal MR<2> that is enabled to a logic high level when the logic level of the second pre-master reception control signal MRP<2> Is input as a logic high level after the start of a normal operation. The second pre-master transmission control signal MTP<2> and the second pre-master reception control signal MRP<2> may be set as a signal that is input as a logic high level after the start of a training operation and that is input as a logic high level when the logic level of the first chip ID CID<1> is a logic high level and the logic level of the second chip ID CID<2> is a logic low level after the start of a normal operation.

The third logic circuit323may generate the third master transmission control signal MT<3> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a third pre-master transmission control signal MTP<3> is input as a logic high level, the logic level of the first master ID MID<1> is input as a logic low level, and the logic level of the second master ID MID<2> is input as a logic high level. The third logic circuit323may generate the third master reception control signal MR<3> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a third pre-master reception control signal MRP<3> is input as a logic high level, the logic level of the first master ID MID<1> is input as a logic low level, and the logic level of the second master ID MID<2> is input as a logic high level. The third logic circuit323may generate the third master transmission control signal MT<3> that is enabled to a logic high level when the logic level of the third pre-master transmission control signal MTP<3> is input as a logic high level after the start of a normal operation. The third logic circuit323may generate the third master reception control signal MR<3> that is enabled to a logic high level when the logic level of the third pre-master reception control signal MRP<3> is input as a logic high level after the start of a normal operation. The third pre-master transmission control signal MTP<3> and the third pre-master reception control signal MRP<3> may be set as a signal that is input as a logic high level after the start of a training operation and that is input as a logic high level when the logic level of the first chip ID CID<1> is a logic low level and the logic level of the second chip ID CID<2> is a logic high level after the start of a normal operation.

The fourth logic circuit324may generate the fourth master transmission control signal MT<4> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a fourth pre-master transmission control signal MTP<4> is input as a logic high level, the logic level of the first master ID MID<1> is input as a logic high level, and the logic level of the second master ID MID<2> is input as a logic high level. The fourth logic circuit324may generate the fourth master reception control signal MR<4> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a fourth pre-master reception control signal MRP<4> is input as a logic high level, the logic level of the first master ID MID<1> is input as a logic high level, and the logic level of the second master ID MID<2> is input as a logic high level. The fourth logic circuit324may generate the fourth master transmission control signal MT<4> that is enabled to a logic high level when the logic level of the fourth pre-master transmission control signal MTP<4> is input as a logic high level after the start of a normal operation. The fourth logic circuit324may generate the fourth master reception control signal MR<4> that is enabled to a logic high level when the logic level of the fourth pre-master reception control signal MRP<4> is input as a logic high level after the start of a normal operation. The fourth pre-master transmission control signal MTP<4> and the fourth pre-master reception control signal MRP<4> may be set as a signal that is input as a logic high level after the start of a training operation and that is input as a logic high level when the logic level of the first chip ID CID<1> is a logic high level and the logic level of the second chip ID CID<2> is a logic high level after the start of a normal operation.

FIG.7is a block diagram illustrating a construction according to an embodiment of the second memory device220. As illustrated inFIG.7, the second memory device220may include a second input/output control circuit (I/O CTR2)221, a second clock generation circuit (CLK GEN2)222, a second core circuit (CORE2)223, a first comparison circuit (CMP1)224, first to fourth slave transmitters T221to T224, first to fourth slave receivers R221to R224, and first to fourth slave pads P221to P224.

The second input/output control circuit221may generate first to fourth slave transmission control signals ST<1:4> and first to fourth slave reception control signals SR<1:4> that are selectively enabled based on the first and second chip IDs CID<1:2> that are input after the start of a normal operation.

The second clock generation circuit222may generate a second internal clock ICLK2based on the first to fourth test codes TM<1:4> after the start of a training operation. The second clock generation circuit222may generate the second internal clock ICLK2with a delay that is adjusted based on a combination of logic levels of the first to fourth test codes TM<1:4> after the start of a training operation. The first to fourth test codes TM<1:4> may be sequentially counted after the start of a training operation. For example, the logic levels of the first to fourth test codes TM<1:4> may be generated as “L, L, L, L” after the start of the first training operation, the logic levels of the first to fourth test codes TM<1:4> may be generated as “L, L, L, H” after the start of the second training operation, the logic levels of the first to fourth test codes TM<1:4> may be generated as “L, L, H, L” after the start of the third training operation. The second clock generation circuit222may store the first to fourth test codes TM<1:4> when a first test latch signal TM_LAT1is enabled after the start of a training operation. The second clock generation circuit222may program the first to fourth test codes TM<1:4> that are stored when the training operation is terminated. The second clock generation circuit222may generate the second internal clock ICLK2having a delay that has been adjusted based on the programmed first to fourth test codes TM<1:4>, after the start of a normal operation. The second clock generation circuit222may program first to sixteenth failure addresses FADD<1:16> after the start of a normal operation and may output the programmed first to sixteenth failure addresses FADD<1:16> as first to sixteenth repair addresses RADD<1:16>. The second clock generation circuit222may output the first to sixteenth failure addresses FADD<1:16> as the first to sixteenth repair addresses RADD<1:16> after the start of a normal operation.

The second core circuit223may be activated by the first and second chip IDs CID<1:2> after the start of a training operation and may output first internal data ID1that has been stored in the second core circuit223in synchronization with the second internal clock ICLK2. The second core circuit223may be activated by the first and second chip IDs CID<1:2> after the start of a write operation of a normal operation and may store the first internal data ID1in synchronization with the second internal clock ICLK2. The second core circuit223may be activated by the first and second chip IDs CID<1:2> after the start of a read operation of a normal operation and may output the first internal data ID1that has been stored in the second core circuit223in synchronization with the second internal clock ICLK2. The second core circuit223may perform a repair operation of replacing an area in which an error has occurred based on the first to sixteenth repair addresses RADD<1:16> after the start of a normal operation. The second core circuit223may perform a write operation and a read operation through an area that has been replaced based on the first to sixteenth repair addresses RADD<1:16> after the start of a normal operation. The second core circuit223may be implemented as a common core circuit and may include a command decoder, an address decoder, a data input/output control circuit, etc. that are activated by the first and second chip IDs CID<1:2>. The command decoder, the address decoder, the data input/output control circuit, etc. that are included in the second core circuit223may be activated by the first and second chip IDs CID<1:2> having the same logic level combination after the start of a training operation. The command decoder, the address decoder, the data input/output control circuit, etc. that are included in the second core circuit223may be activated by the first chip ID CID<1> having a logic high level and the second chip ID CID<2> having a logic low level after the start of a normal operation.

The first comparison circuit224may generate the first test latch signal TM_LAT1by sampling a first transfer internal data TID1based on first transfer master data TMD1after the start of a training operation. The first comparison circuit224may generate the first test latch signal TM_LAT1by comparing a time point at which the first transfer master data TMD1, received from the first slave receiver R221, are input to a time point at which the first transfer internal data TID1, received from the second slave receiver R222, are input after the start of a training operation.

The first slave transmitter T221and the first slave receiver R221may be connected to the first slave pad P221. The first slave transmitter T221may be activated when the first slave transmission control signal ST<1> is enabled and may output the first internal data ID1through the first slave pad P221. The first slave receiver R221may be activated when the first slave reception control signal SR<1> is enabled after the start of a normal operation and may generate the first internal data ID1by receiving data from the first slave pad P221. The first slave receiver R221may output the first internal data ID1to the second core circuit223after the start of a normal operation. The first slave receiver R221may be activated when the first slave reception control signal SR<1> is enabled after the start of a training operation and may generate the first transfer master data TMD1by receiving the master data MD from the first slave pad P221. The first slave receiver R221may output the first transfer master data TMD1to the first comparison circuit224after the start of a training operation. InFIG.7, the first slave receiver R221has been implemented to generate the first internal data ID1and the first transfer master data TMD1. However, a switch (not illustrated) may be connected to the first slave receiver R221and may be implemented to output the first internal data ID1to the second core circuit223after the start of a normal operation and to output the first transfer master data TMD1to the first comparison circuit224after the start of a training operation.

The second slave transmitter T222and the second slave receiver R222may be connected to the second slave pad P222. The second slave transmitter T222may be activated when the second slave transmission control signal ST<2> is enabled and may output the first internal data ID1through the second slave pad P222. The second slave receiver R222may be activated when the second slave reception control signal SR<2> is enabled after the start of a normal operation and may generate the first internal data ID1by receiving data from the second slave pad P222. The second slave receiver R222may output the first internal data ID1to the second core circuit223after the start of a normal operation. The second slave receiver R222may be activated when the second slave reception control signal SR<2> is enabled after the start of a training operation and may generate the first transfer internal data TID1by receiving the first internal data ID1from the second slave pad P222. The second slave receiver R222may output the first transfer internal data TID1to the first comparison circuit224after the start of a training operation. InFIG.7, the second slave receiver R222has been implemented to generate the first internal data ID1and the first transfer internal data TID1. However, a switch (not illustrated) may be connected to the second slave receiver R222and may be implemented to output the first internal data ID1to the second core circuit223after the start of a normal operation and to output the first transfer internal data TID1to the first comparison circuit224after the start of a training operation. The third slave transmitter T223and the third slave receiver R223may be connected to the third slave pad P223. The third slave transmitter T223may be activated when the third slave transmission control signal ST<3> is enabled and may output the first internal data ID1through the third slave pad P223. The third slave receiver R223may be activated when the third slave reception control signal SR<3> is enabled and may generate the first internal data ID1by receiving data from the third slave pad P223.

The fourth slave transmitter T224and the fourth slave receiver R224may be connected to the fourth slave pad P224. The fourth slave transmitter T224may be activated when the fourth slave transmission control signal ST<4> is enabled and may output the first internal data ID1through the fourth slave pad P224. The fourth slave receiver R224may be activated when the fourth slave reception control signal SR<4> is enabled and may generate the first internal data ID1by receiving data from the fourth slave pad P224.

The third memory device230and the fourth memory device240may be implemented as the same circuits as the second memory device220, illustrated inFIG.7, and may perform the same operations as that of the second memory device220, and thus detailed descriptions thereof are omitted.

FIG.8is a block diagram illustrating a construction according to an embodiment of the second input/output control circuit221. As illustrated inFIG.8, the second input/output control circuit221may include a slave ID generation circuit (SID GEN)410and a second decoder (DEC2)420.

The slave ID generation circuit410may receive the first and second chip IDs CID<1:2> after the start of a normal operation. The slave ID generation circuit410may receive the first and second chip IDs CID<1:2> when the training flag signal TF is disabled after the start of a normal operation. The slave ID generation circuit410may generate first and second slave IDs SID<1:2> by latching the first and second chip IDs CID<1:2> that have been received in a normal operation after the start of a training operation. The slave ID generation circuit410may generate the first and second slave IDs SID<1:2> by latching the first and second chip IDs CID<1:2> that have been received in a normal operation when the training flag signal TF is enabled after the start of a training operation.

The second decoder420may generate the first to fourth slave transmission control signals ST<1:4> by decoding the first and second slave IDs SID<1:2>. The second decoder420may generate the first to fourth slave reception control signal SR<1:4> by decoding the first and second slave IDs SID<1:2>.

FIG.9is a circuit diagram illustrating a construction according to an embodiment of the slave ID generation circuit410. As illustrated inFIG.9, the slave ID generation circuit410may include a first slave ID generation circuit411and a second slave ID generation circuit412.

The first slave ID generation circuit411may be implemented as inverters411<1>,411<2>, and411<3>. The inverter411<1> may receive the first chip ID CID<1> when the logic level of the training flag signal TF is disabled to a logic low level after the start of a normal operation. The inverter411<1> may invert and output the first chip ID CID<1> that has been input after the start of a normal operation. The inverters411<2> and411<3> may be implemented as a latch in which the input stages and output stages of the inverters411<2> and411<3> are connected. The inverter411<2> may output the first slave ID SID<1> by inverting the output signal of the inverter411<1>. The inverters411<2> and411<3> may latch the output signal of the inverter411<1> when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation.

The second slave ID generation circuit412may be implemented as inverters412<1>,412<2>, and412<3>. The inverter412<1> may receive the second chip ID CID<2> when the logic level of the training flag signal TF is disabled to a logic low level after the start of a normal operation. The inverter412<1> may invert and output the second chip ID CID<2> that has been input after the start of a normal operation. The inverters412<2> and412<3> may be implemented as a latch in which the input stages and output stages of the inverters412<2> and412<3> are connected. The inverter412<2> may invert the output signal of the inverter412<1> and output the inverted signal as the second slave ID SID<2>, after the start of a training operation. The inverters412<2> and412<3> may latch the output signal of the inverter412<1> when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation.

FIG.10is a circuit diagram illustrating a construction according to an embodiment of the second decoder420. As illustrated inFIG.10, the second decoder420may include a fifth logic circuit421, a sixth logic circuit422, a seventh logic circuit423, and an eighth logic circuit424.

The fifth logic circuit421may generate the first slave transmission control signal ST<1> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a first pre-slave transmission control signal STP<1> is input as a logic high level, the logic level of the first slave ID SID<1> is input as a logic low level, and the logic level of the second slave ID master ID SID<2> is input as a logic low level. The fifth logic circuit421may generate the first slave reception control signal SR<1> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a first pre-slave reception control signal SRP<1> is input as a logic high level, the logic level of the first slave ID SID<1> is input as a logic low level, and the logic level of the second slave ID SID<2> is input as a logic low level. The fifth logic circuit421may generate the first slave transmission control signal ST<1> that is enabled to a logic high level when the logic level of the first pre-slave transmission control signal STP<1> is input as a logic high level after the start of a normal operation. The fifth logic circuit421may generate the first slave reception control signal SR<1> that is enabled to a logic high level when the logic level of the first pre-slave reception control signal SRP<1> is input as a logic high level after the start of a normal operation. The first pre-slave transmission control signal STP<1> and the first pre-slave reception control signal SRP<1> may be set as a signal that is input as a logic high level after the start of a training operation and that is input as a logic high level when the logic level of the first chip ID CID<1> is a logic low level and the logic level of the second chip ID CID<2> is a logic low level after the start of a normal operation.

The sixth logic circuit422may generate the second slave transmission control signal ST<2> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a second pre-slave transmission control signal STP<2> is input as a logic high level, the logic level of the first slave ID SID<1> is input as a logic high level, and the logic level of the second slave ID SID<2> is input as a logic low level. The sixth logic circuit422may generate the second slave reception control signal SR<2> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a second pre-slave reception control signal SRP<2> is input as a logic high level, the logic level of the first slave ID SID<1> is input as a logic high level, and the logic level of the second slave ID SID<2> is input as a logic low level. The sixth logic circuit422may generate the second slave transmission control signal ST<2> that is enabled to a logic high level when the logic level of the second pre-slave transmission control signal STP<2> is input as a logic high level after the start of a normal operation. The sixth logic circuit422may generate the second slave reception control signal SR<2> that is enabled to a logic high level when the logic level of the second pre-slave reception control signal SRP<2> is input as a logic high level after the start of a normal operation. The second pre-slave transmission control signal STP<2> and the second pre-slave reception control signal SRP<2> may be set as a signal that is input as a logic high level after the start of a training operation and that is input as a logic high level when the logic level of the first chip ID CID<1> is a logic high level and the logic level of the second chip ID CID<2> is a logic low level after the start of a normal operation.

The seventh logic circuit423may generate the third slave transmission control signal ST<3> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a third pre-slave transmission control signal STP<3> is input as a logic high level, the logic level of the first slave ID SID<1> is input as a logic low level, and the logic level of the second slave ID SID<2> is input as a logic high level. The seventh logic circuit423may generate the third slave reception control signal SR<3> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a third pre-slave reception control signal SRP<3> is input as a logic high level, the logic level of the first slave ID SID<1> is input as a logic low level, and the logic level of the second slave ID SID<2> is input as a logic high level. The seventh logic circuit423may generate the third slave transmission control signal ST<3> that is enabled to a logic high level when the logic level of the third pre-slave transmission control signal STP<3> is input as a logic high level after the start of a normal operation. The seventh logic circuit423may generate the third slave reception control signal SR<3> that is enabled to a logic high level when the logic level of the third pre-slave reception control signal SRP<3> is input as a logic high level after the start of a normal operation. The third pre-slave transmission control signal STP<3> and the third pre-slave reception control signal SRP<3> may be set as a signal that is input as a logic high level after the start of a training operation and that is input as a logic high level when the logic level of the first chip ID CID<1> is a logic low level and the logic level of the second chip ID CID<2> is a logic high level after the start of a normal operation.

The eighth logic circuit424may generate the fourth slave transmission control signal ST<4> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a fourth pre-slave transmission control signal STP<4> is input as a logic high level, the logic level of the first slave ID SID<1> is input as a logic high level, and the logic level of the second slave ID SID<2> is input as a logic high level. The eighth logic circuit424may generate the fourth slave reception control signal SR<4> that is enabled to a logic high level when the logic level of the training flag signal TF is enabled to a logic high level after the start of a training operation, the logic level of a fourth pre-slave reception control signal SRP<4> is input as a logic high level, the logic level of the first slave ID SID<1> is input as a logic high level, and the logic level of the second slave ID SID<2> is input as a logic high level. The eighth logic circuit424may generate the fourth slave transmission control signal ST<4> that is enabled to a logic high level when the logic level of the fourth pre-slave transmission control signal STP<4> is input as a logic high level after the start of a normal operation. The eighth logic circuit424may generate the fourth slave reception control signal SR<4> that is enabled to a logic high level when the logic level of the fourth pre-slave reception control signal SRP<4> is input as a logic high level after the start of a normal operation. The fourth pre-slave transmission control signal STP<4> and the fourth pre-slave reception control signal SRP<4> may be set as a signal that is input as a logic high level after the start of a training operation and that is input as a logic high level when the logic level of the first chip ID CID<1> is a logic high level and the logic level of the second chip ID CID<2> is a logic high level after the start of a normal operation.

FIG.11is a block diagram illustrating a construction according to an embodiment of the second clock generation circuit222. As illustrated inFIG.11, the second clock generation circuit222may include a code generation circuit (CODE GEN)510, a DLL circuit (DLL)520, and a fuse array circuit (ARE)530.

The code generation circuit510may generate first to sixteenth code signals CODE<1:16> by decoding the first to fourth test codes TM<1:4> after the start of a training operation. The code generation circuit510may generate the first to sixteenth code signals CODE<1:16> that are selectively enabled by decoding the first to fourth test codes TM<1:4> after the start of a training operation.

The DLL circuit520may generate the second internal clock ICLK2having a delay that is adjusted based on a combination of logic levels of the first to sixteenth code signals CODE<1:16>, after the start of a training operation. For example, after the start of a training operation, the DLL circuit520may generate the second internal clock ICLK2having a delay that is smaller when the second code signal CODE<2> is enabled than when the first code signal CODE<1> is enabled. After the start of a training operation, the DLL circuit520may generate the second internal clock ICLK2having a delay that is set based on a combination of logic levels of the first to sixteenth delay control signals DCTR<1:16>, after the start of a normal operation.

The fuse array circuit530may store the first to sixteenth code signals CODE<1:16> when the first test latch signal TM_LAT1is enabled after the start of a training operation. The fuse array circuit530may program the first to sixteenth code signals CODE<1:16> that are stored when the training operation is terminated. The fuse array circuit530may output the programmed first to sixteenth code signals CODE<1:16> as first to sixteenth delay control signals DCTR<1:16> after the start of a normal operation. The fuse array circuit530may store, in the second core circuit223, the first to sixteenth failure addresses FADD<1:16> that include location information of an area in which a failure has occurred, after the start of a normal operation. The fuse array circuit530may program the first to sixteenth failure addresses FADD<1:16> after the start of a normal operation. The fuse array circuit530may output the programmed first to sixteenth failure addresses FADD<1:16> as the first to sixteenth repair addresses RADD<1:16> after the start of a normal operation.

FIG.12is a block diagram illustrating a construction according to an embodiment of the fuse array circuit530. As illustrated inFIG.12, the fuse array circuit530may include a fuse data generation circuit (FD GEN)531and a fuse circuit (FUSE)532.

The fuse data generation circuit531may store the first to sixteenth code signals CODE<1:16> when a selection signal TM_SEL and the first test latch signal TM_LAT1are enabled and may generate first to sixteenth fuse data FD<1:16> from the stored first to sixteenth code signals CODE<1:16>. The fuse data generation circuit531may store the first to sixteenth failure addresses FADD<1:16> when the selection signal TM_SEL is disabled and a repair input signal RIN is enabled after the start of a repair operation of a normal operation and may generate the first to sixteenth fuse data FD<1:16> from the stored first to sixteenth failure addresses FADD<1:16>. The fuse data generation circuit531may generate the first to sixteenth fuse data FD<1:16> from first to sixteenth mode information signals MRD<1:16> when a mode selection signal MR_SEL is enabled in a mode register write operation. The selection signal TM_SEL may be set as a signal that is enabled after the start of a training operation. The repair input signal RIN may be set as a signal that is enabled after the start of a repair operation of a normal operation. The mode selection signal MR_SEL may be set as a signal that is enabled after the start of a mode register write operation. The first to sixteenth mode information signals MRD<1:16> may be set as a signal that adjusts the delay of the second internal clock ICLK2based on an external condition.

The fuse circuit532may include multiple electrical fuses (not illustrated). The fuse circuit532may have the multiple electrical fuses (not illustrated) ruptured when a training operation is terminated and may program the first to sixteenth fuse data FD<1:16>. The fuse circuit532may output the programmed first to sixteenth fuse data FD<1:16> as the first to sixteenth delay control signals DCTR<1:16> after the start of a normal operation. The fuse circuit532may have the multiple electrical fuses (not illustrated) ruptured after the start of a normal operation and may program the first to sixteenth fuse data FD<1:16>. The fuse circuit532may output the programmed first to sixteenth fuse data FD<1:16> as the first to sixteenth repair addresses RADD<1:16> after the start of a normal operation. An operation of the multiple electrical fuses (not illustrated) being ruptured may be set as an operation that programs the first to sixteenth fuse data FD<1:16> by destroying a silicon insulating film that is connected to gates of the multiple electrical fuses (not illustrated) by applying a high voltage to the multiple electrical fuses (not illustrated).

FIG.13is a block diagram illustrating a construction according to an embodiment of the fuse data generation circuit531. As illustrated inFIG.13, the fuse data generation circuit531may include a first selection transferrer531<1>, a second selection transferrer531<2>, a latch531<3>, and a third selection transferrer531<4>.

The first selection transferrer531<1> may output one of the first to sixteenth code signals CODE<1:16> and the first to sixteenth failure addresses FADD<1:16> as first to sixteenth selection code signals SCD<1:16> based on a logic level of the selection signal TM_SEL. The first selection transferrer531<1> may output the first to sixteenth code signals CODE<1:16> as the first to sixteenth selection code signals SCD<1:16> when the logic level of the selection signal TM_SEL is enabled to a logic high level. The first selection transferrer531<1> may output the first to sixteenth failure addresses FADD<1:16> as the first to sixteenth selection code signals SCD<1:16> when the logic level of the selection signal TM_SEL is disabled to a logic low level.

The second selection transferrer531<2> may output one of the first test latch signal TM_LAT1and the repair input signal RIN as a latch control signal LCTR based on a logic level of the selection signal TM_SEL. The second selection transferrer531<2> may output the first test latch signal TM_LAT1as the latch control signal LCTR when the logic level of the selection signal TM_SEL is enabled to a logic high level. The second selection transferrer531<2> may output the repair input signal RIN as the latch control signal LCTR when the logic level of the selection signal TM_SEL is disabled to a logic low level.

The latch531<3> may store the first to sixteenth selection code signals SCD<1:16> when the latch control signal LCTR is enabled. The latch531<3> may output the stored first to sixteenth selection code signals SCD<1:16> as the first to sixteenth latch code signals LCD<1:16> when the latch control signal LCTR is enabled.

The third selection transferrer531<4> may output one of the first to sixteenth latch code signals LCD<1:16> and the first to sixteenth mode information signals MRD<1:16> as the first to sixteenth fuse data FD<1:16> based on a logic level of the mode selection signal MR_SEL. The third selection transferrer531<4> may output the first to sixteenth mode information signals MRD<1:16> as the first to sixteenth fuse data FD<1:16> when the logic level of the mode selection signal MR_SEL is enabled to a logic high level. The third selection transferrer531<4> may output the first to sixteenth latch code signals LCD<1:16> as the first to sixteenth fuse data FD<1:16> when the logic level of the mode selection signal MR_SEL is disabled to a logic low level.

A transmitter and a receiver that are activated after the start of a normal operation of the semiconductor package1, according to an embodiment of the present disclosure, are described as follows with reference toFIG.14.

When the logic level of the first chip ID CID<1> is a logic low level L and the logic level of the second chip ID CID<2> is a logic low level L in a normal operation, the first master transmitter T211and first master receiver R211of the first memory device210may be activated and may input and output the master data MD.

When the logic level of the first chip ID CID<1> is a logic high level H and the logic level of the second chip ID CID<2> is a logic low level L in a normal operation, the second slave transmitter T222and second slave receiver R222of the second memory device220may be activated and may input and output the first internal data ID1.

When the logic level of the first chip ID CID<1> is a logic low level L and the logic level of the second chip ID CID<2> is a logic high level H in a normal operation, a seventh slave transmitter T233and seventh slave receiver R233of the third memory device230may be activated and may input and output second internal data ID2.

When the logic level of the first chip ID CID<1> is a logic high level H and the logic level of the second chip ID CID<2> is a logic high level H in a normal operation, a twelfth slave transmitter T244and twelfth slave receiver R244of the fourth memory device240may be activated and may input and output third internal data ID3.

A transmitter and a receiver that are activated after the start of a training operation of the semiconductor package1, according to an embodiment of the present disclosure, are described as follows with reference toFIG.15.

In a training operation, the first master transmitter T211of the first memory device210may be activated and may output the master data MD. The first slave receiver R221of the second memory device220may be activated and may receive the master data MD. The second slave transmitter T222and second slave receiver R222of the second memory device220may be activated and may input and output the first internal data ID1. A fifth slave receiver R231of the third memory device230may be activated and may receive the master data MD. The seventh slave transmitter T233and seventh slave receiver R233of the third memory device230may be activated and may input and output the second internal data ID2. A ninth slave receiver R241of the fourth memory device240may be activated and may receive the master data MD. A twelfth slave transmitter T244and twelfth slave receiver R244of the fourth memory device240may be activated and may input and output the third internal data ID3.

An operation that programs a test code by inputting and outputting data through a transmitter and a receiver that are activated after the start of a training operation of the semiconductor package1, according to an embodiment of the present disclosure, is described as follows with reference toFIG.16.

The first clock generation circuit212of the first memory device210may generate the first internal clock ICLK1having a fixed delay when the first to fourth test codes TM<1:4> are input.

The first core circuit213of the first memory device210may be activated by the first chip ID CID<1> having a logic low level and the second chip ID CID<2> having a logic low level and may output the master data MD that has been stored in the first core circuit213in synchronization with the first internal clock ICLK1.

The first master transmitter T211of the first memory device210may be activated by the first chip ID CID<1> having a logic low level and the second chip ID CID<2> having a logic low level, which are input after the start of a normal operation and may output the master data MD.

The second clock generation circuit222of the second memory device220may generate the second internal clock ICLK2having a delay that is adjusted based on a combination of logic levels of the first to fourth test codes TM<1:4> that are sequentially counted.

The second core circuit223of the second memory device220may be activated by the first chip ID CID<1> having a logic low level and the second chip ID CID<2> having a logic low level and may output the first internal data ID1that has been stored in the second core circuit223in synchronization with the second internal clock ICLK2.

The first slave receiver R221of the second memory device220may be activated by the first chip ID CID<1> having a logic high level and the second chip ID CID<2> having a logic low level, which are input after the start of a normal operation and may generate the first transfer master data TMD1by receiving the master data MD. The second slave transmitter T222and the second slave receiver R222may be activated by the first chip ID CID<1> having a logic high level and the second chip ID CID<2> having a logic low level, which are input after the start of a normal operation and may generate the first transfer internal data TID1by receiving the first internal data ID1.

The first comparison circuit224of the second memory device220may generate the first test latch signal TM_LAT1that is enabled when a time point at which the first transfer master data TMD1, received from the first slave receiver R221, are input is identical to a time point at which the first transfer internal data TID1, received from the second slave receiver R222, are input.

The second clock generation circuit222of the second memory device220may store the first to fourth test codes TM<1:4> when the first test latch signal TM_LAT1is enabled. The second clock generation circuit222may program the stored first to fourth test codes TM<1:4> when a training operation is terminated.

A third clock generation circuit232of the third memory device230may generate a third internal clock ICLK3having a delay that is adjusted based on a combination of logic levels of the first to fourth test codes TM<1:4> that are sequentially counted.

A third core circuit233of the third memory device230may be activated by the first chip ID CID<1> having a logic low level and the second chip ID CID<2> having a logic low level and may output the second internal data ID2that has been stored in the third core circuit233in synchronization with the third internal clock ICLK3.

The fifth slave receiver R231of the third memory device230may be activated by the first chip ID CID<1> having a logic low level and the second chip ID CID<2> having a logic high level, which are input after the start of a normal operation and may generate second transfer master data TMD2by receiving the master data MD. The seventh slave transmitter T233and the seventh slave receiver R233may be activated by the first chip ID CID<1> having a logic low level and the second chip ID CID<2> having a logic high level, which are input after the start of a normal operation and may generate second transfer internal data TID2by receiving the second internal data ID2.

The second comparison circuit234of the third memory device230may generate a second test latch signal TM_LAT2that is enabled when a time point at which the second transfer master data TMD2, received from the fifth slave receiver R231, are input is identical to a time point at which the second transfer internal data TID2, received from the seventh slave receiver R233, are input.

The third clock generation circuit232of the third memory device230may store the first to fourth test codes TM<1:4> when the second test latch signal TM_LAT2is enabled. The third clock generation circuit232may program the stored first to fourth test codes TM<1:4> when the training operation is terminated.

A fourth clock generation circuit242of the fourth memory device240may generate a fourth internal clock ICLK4having a delay that is adjusted based on a combination of logic levels of the first to fourth test codes TM<1:4> that are sequentially counted.

A fourth core circuit243of the fourth memory device240may be activated by the first chip ID CID<1> having a logic low level and the second chip ID CID<2> having a logic low level and may output the third internal data ID3that has been stored in the fourth core circuit243in synchronization with the fourth internal clock ICLK4.

A ninth slave receiver R241of the fourth memory device240may be activated by the first chip ID CID<1> having a logic high level and the second chip ID CID<2> having a logic high level, which are input after the start of a normal operation and may generate third transfer master data TMD3by receiving the master data MD. The twelfth slave transmitter T244and the twelfth slave receiver R244may be activated by the first chip ID CID<1> having a logic high level and the second chip ID CID<2> having a logic high level, which are input after the start of a normal operation and may generate the third transfer internal data TID3by receiving the third internal data ID3. A third comparison circuit244of the fourth memory device240may generate a third test latch signal TM_LAT3that is enabled when a time point at which the third transfer master data TMD3, received from the ninth slave receiver R241, are input is identical to a time point at which the third transfer internal data TID3, received from the twelfth slave receiver R244, are input.

The fourth clock generation circuit242of the fourth memory device240may store the first to fourth test codes TM<1:4> when the third test latch signal TM_LAT3is enabled. The fourth clock generation circuit242may program the stored first to fourth test codes TM<1:4> when a training operation is terminated.

The semiconductor package1according to such an embodiment of the present disclosure can simultaneously adjust operating speeds of the first to fourth memory devices210to240in a way to program the first to fourth test codes TM<1:4> having different logic level combinations by comparing a time point at which the master data MD, output by the first memory device210, are input to each of the time points at which the first to third internal data ID1to ID3that are generated within the second to fourth memory devices220to240are input after the start of a training operation.

A training operation of the semiconductor package1according to an embodiment of the present disclosure is described with reference toFIG.17, but an operation that programs, by the first memory device210and the second memory device220, a test code by inputting and outputting data is described as follows. The master data MD, illustrated inFIG.17, may be set identically with the first transfer master data TMD1, and the first internal data ID1, illustrated inFIG.17, may be set identically with the first transfer internal data TID1.

First, a first training operation is described. At a time point T1, the first master transmitter T211of the first memory device210may be activated and may output the master data MD. At a time point T3, the first slave receiver R221of the second memory device220may be activated and may receive the master data MD, and the second slave transmitter T222and second slave receiver R222of the second memory device220may be activated and may input and output the first internal data ID1. At this time, the first first to fourth test codes TM<1:4> might not be programmed because the master data MD are input at the time point T1and the first internal data ID1are input at the time point T3.

Next, a second training operation is described. At the time point T1, the first master transmitter T211of the first memory device210may be activated and may output the master data MD. At a time point T2, the first slave receiver R221of the second memory device220may be activated and may receive the master data MD, and the second slave transmitter T222and second slave receiver R222of the second memory device220may be activated and may input and output the first internal data ID1. At this time, the second first to fourth test codes TM<1:4> might not be programmed because the master data MD are input at the time point T1and the first internal data ID1are input at the time point T2.

Next, a third training operation is described. At the time point T1, the first master transmitter T211of the first memory device210may be activated and may output the master data MD. At the time point T1, the first slave receiver R221of the second memory device220may be activated and may receive the master data MD, and the second slave transmitter T222and second slave receiver R222of the second memory device220may be activated and may input and output the first internal data ID1. At this time, the second memory device220may store the third first to fourth test codes TM<1:4> because the master data MD are input at the time point T1and the first internal data ID1are input at the time point T1. The second memory device220may program the stored third first to fourth test codes TM<1:4> when the training operation is terminated.

The semiconductor package1according to such an embodiment of the present disclosure can adjust operating speeds of the first memory device210and the second memory device220to be identical by programming the first to fourth test codes TM<1:4> by comparing a time point at which the master data MD, output by the first memory device210, are input to a time point at which the first internal data ID1, generated within the second memory device220, are input after the start of a training operation. The semiconductor package1can prevent an error of data input and output operations in a normal operation by adjusting operating speeds of the first memory device210and the second memory device220to be identical by programming each of the first to fourth test codes TM<1:4> that adjusts the operating speeds to be identical after the start of a training operation.

A training operation of the semiconductor package1according to an embodiment of the present disclosure is described with reference toFIG.18, but an operation that programs, by the first to fourth memory devices210to240, a test code by inputting and outputting data is described as follows. First, training operations of the first memory device210and the second memory device220are described as follows. In this case, the master data MD, illustrated inFIG.18, may be set identically with the first transfer master data TMD1, and the first internal data ID1, illustrated inFIG.18, may be set identically with the first transfer internal data TID1.

In the first training operation and the second training operation, the first first to fourth test codes TM<1:4> and the second first to fourth test codes TM<1:4> might not be programmed because the master data MD and the first internal data ID1are input at different time points.

In the third training operation, at a time point T11, the first master transmitter T211of the first memory device210may be activated and may output the master data MD. At the time point T11, the first slave receiver R221of the second memory device220may be activated and may receive the master data MD, and the second slave transmitter T222and second slave receiver R222of the second memory device220may be activated and may input and output the first internal data ID1. At this time, since the master data MD are input at the time point T11and the first internal data ID1are input at the time point T11, the second clock generation circuit222of the second memory device220may store the third first to fourth test codes TM<1:4>. When the third training operation is terminated, the second clock generation circuit222of the second memory device220may program the stored third first to fourth test codes TM<1:4>.

Next, training operations of the first memory device210and the third memory device230are described as follows. In this case, the master data MD, illustrated inFIG.18, may be set identically with the second transfer master data TMD2, and the second internal data ID2, illustrated inFIG.18, may be set identically with the second transfer internal data TID2.

In the first training operation, the first first to fourth test codes TM<1:4> might not be programmed because the master data MD and the second internal data ID2are input at different time points.

In the second training operation, at a time point T21, the first master transmitter T211of the first memory device210may be activated and may output the master data MD. At the time point T21, the fifth slave receiver R231of the third memory device230may be activated and may receive the master data MD, and the seventh slave transmitter T233and seventh slave receiver R233of the third memory device230may be activated and may input and output the second internal data ID2. At this time, the third clock generation circuit232of the third memory device230may store the second first to fourth test codes TM<1:4> because the master data MD are input at the time point T21and the second internal data ID2are input at the time point T21. When the second training operation is terminated, the third clock generation circuit232of the third memory device230may program the stored second first to fourth test codes TM<1:4>.

Next, training operations of the first memory device210and the fourth memory device240are described as follows. In this case, the master data MD, illustrated inFIG.18, may be set identically with the third transfer master data TMD3, and the third internal data ID3, illustrated inFIG.18, may be set identically with the third transfer internal data TID3.

In the first training operation, the first first to fourth test codes TM<1:4> might not be programmed because the master data MD and the third internal data ID3are input at different time points.

In the second training operation, at a time point T31, the first master transmitter T211of the first memory device210may be activated and may output the master data MD. At the time point T31, the ninth slave receiver R241of the fourth memory device240may be activated and may receive the master data MD, and the twelfth slave transmitter T244and twelfth slave receiver R244of the fourth memory device240may be activated and may input and output the third internal data ID3. At this time, the fourth clock generation circuit242of the fourth memory device240may store the second first to fourth test codes TM<1:4> because the master data MD are input at the time point T31and the third internal data ID3are input at the time point T31. When the second training operation is terminated, the fourth clock generation circuit242of the fourth memory device240may program the stored second first to fourth test codes TM<1:4>.

The semiconductor package1, according to such an embodiment of the present disclosure, can adjust operating speeds of the first to fourth memory devices210to240to be identical by programming each of the first to fourth test codes TM<1:4> having different logic level combinations by comparing a time point at which the master data MD, output by the first memory device210, are input and each of time points at which the first to third internal data ID1to ID3, generated within the second to fourth memory devices220to240, are input after the start of a training operation. The semiconductor package1can prevent an error of data input and output operations in a normal operation by adjusting operating speeds of the first to fourth memory devices210to240to be identical by programming each of the first to fourth test codes TM<1:4> having different logic level combinations and by adjusting the operating speeds to be identical after the start of a training operation.

FIG.19is a diagram for describing a block that is activated after the start of a training operation of a semiconductor device according to an example of the present disclosure.

Prior to a description, the internal components of a first memory device210_1, a second memory device220_1, a third memory device230_1, and a fourth memory device240_1that are included in a semiconductor device20_1may be identically implemented. The first memory device210_1may be implemented as a master device, and the second memory device220_1, the third memory device230_1, and the fourth memory device240_1may be implemented as slave devices. The memory device that is implemented as the master device may be implemented as any one of the first memory device210_1, the second memory device220_1, the third memory device230_1, and the fourth memory device240_1in different embodiments. The memory devices that are implemented as the slave devices may be implemented as memory devices, except a master device, which can be the first memory device210_1, the second memory device220_1, the third memory device230_1, or the fourth memory device240_1in different embodiments.

The first memory device210_1may include a first clock generation circuit (CLK GEN1)212_1, a first core circuit (CORE1)213_1, a first comparison circuit (CMP1)214_1, first to fourth master transmitters, and first to fourth master receivers.

The first clock generation circuit2121may be activated after the start of a training operation and may generate a first internal clock ICLK1having a fixed delay when first to fourth test codes TM<1:4> are input.

The first core circuit213_1may be activated after the start of a training operation and may output master data MD that has been stored in the first core circuit213_1in synchronization with the first internal clock ICLK1.

A first master transmitter T211_1, among the first to fourth master transmitters, may be activated and may output the master data MD after the start of a training operation.

The second to fourth master transmitter and the first to fourth master receivers may be deactivated after the start of a training operation.

The first comparison circuit214_1may be deactivated after the start of a training operation. The first comparison circuit214_1may generate a first test latch signal TM_LAT1by sampling a transfer internal data TID that is generated from any one of first to third internal data ID1to ID3that are output by the second memory device220_1, the third memory device230_1, and the fourth memory device240_1, based on transfer master data TMD that is generated from the master data MD.

The second memory device220_1may include a second clock generation circuit (CLK GEN2)222_1, a second core circuit (CORE2)2231, a second comparison circuit (CMP2)224_1, first to fourth slave transmitters, and first to fourth slave receivers.

The second clock generation circuit222_1may be activated after the start of a training operation and may generate a second internal clock ICLK2based on the first to fourth test codes TM<1:4>. The second clock generation circuit222_1may generate the second internal clock ICLK2having a delay that is adjusted based on a combination of logic levels of the first to fourth test codes TM<1:4> after the start of a training operation. The second clock generation circuit222_1may store the first to fourth test codes TM<1:4> when a second test latch signal TM_LAT2is enabled after the start of a training operation. The second clock generation circuit222_1may program the stored first to fourth test codes TM<1:4> when the training operation is terminated. The second clock generation circuit222_1may generate the second internal clock ICLK2having a delay that has been adjusted based on the programmed first to fourth test codes TM<1:4> after the start of a normal operation.

The second core circuit223_1may be activated after the start of a training operation and may output the first internal data ID1that has been stored in the second core circuit223_1in synchronization with the second internal clock ICLK2.

A first slave receiver R221_1, among the first to fourth slave receivers, may be activated after the start of a training operation and may generate first transfer master data TMD1by receiving the master data MD.

A second slave transmitter T222_1, among the first to fourth slave transmitters, may be activated after the start of a training operation and may output the first internal data ID1. A second slave receiver R222_1, among the first to fourth slave receivers, may be activated after the start of a training operation and may generate the first transfer internal data TID1by receiving the first internal data ID1from the second transmitter T222_1.

The first slave transmitter, the third slave transmitter, and the fourth slave transmitter may be deactivated after the start of a training operation. The third slave receiver and the fourth slave receiver may be deactivated after the start of a training operation.

The second comparison circuit224_1may be activated after the start of a training operation and may generate the second test latch signal TM_LAT2by sampling first transfer internal data TID1based on the first transfer master data TMD1. The second comparison circuit224_1may be activated after the start of a training operation and may generate the second test latch signal TM_LAT2by comparing a time point at which the first transfer master data TMD1, received from the first slave receiver R221_1, are input to a time point at which the first transfer internal data TID1, received from the second slave receiver R222_1, are input. The second comparison circuit224_1may generate the second test latch signal TM_LAT2that is enabled when the time point at which the first transfer master data TMD1are input is identical to the time point at which the first transfer internal data TID1are input after the start of the training operation.

The third memory device230_1may include a third clock generation circuit (CLK GEN3)232_1, a third core circuit (CORE3)233_1, a third comparison circuit (CMP3)234_1, first to fourth slave transmitters, and first to fourth slave receivers.

The third clock generation circuit232_1may be activated after the start of a training operation and may generate a third internal clock ICLK3based on the first to fourth test codes TM<1:4>. The third clock generation circuit232_1may generate the third internal clock ICLK3having a delay that is adjusted based on a combination of logic levels of the first to fourth test codes TM<1:4> after the start of a training operation. The third clock generation circuit232_1may store the first to fourth test codes TM<1:4> when a third test latch signal TM_LAT3is enabled after the start of a training operation. The third clock generation circuit232_1may program the stored first to fourth test codes TM<1:4> when the training operation is terminated. The third clock generation circuit232_1may generate the third internal clock ICLK3having a delay that has been adjusted based on the programmed first to fourth test codes TM<1:4> after the start of a normal operation.

The third core circuit233_1may be activated after the start of a training operation and may output the second internal data ID2that has been stored in the third core circuit233_1in synchronization with the third internal clock ICLK3.

A first slave receiver R231_1, among the first to fourth slave receivers, may be activated after the start of a training operation and may generate second transfer master data TMD2by receiving the master data MD.

A third slave transmitter T233_1, among the first to fourth slave transmitters, may be activated after the start of a training operation and may output the second internal data ID2. A third slave receiver R233_1, among the first to fourth slave receivers, may be activated after the start of a training operation and may generate the second transfer internal data TID2by receiving the second internal data ID2from the third transmitter T233_1.

The first slave transmitter, the second slave transmitter, and the fourth slave transmitter may be deactivated after the start of a training operation. The second slave receiver and the fourth slave receiver may be deactivated after the start of a training operation.

The third comparison circuit234_1may be activated after the start of a training operation and may generate the third test latch signal TM_LAT3by sampling second transfer internal data TID2based on the second transfer master data TMD2. The third comparison circuit234_1may be activated after the start of a training operation and may generate the third test latch signal TM_LAT3by comparing a time point at which the second transfer master data TMD2, received from the first slave receiver R231_1, are input to a time point at which the second transfer internal data TID2, received from the third slave receiver R233_1, are input. The third comparison circuit234_1may generate the third test latch signal TM_LAT3that is enabled when the time point at which the second transfer master data TMD2are input is identical to the time point at which the second transfer internal data TID2are input after the start of the training operation.

The fourth memory device240_1may include a fourth clock generation circuit (CLK GEN4)242_1, a fourth core circuit (CORE4)243_1, a fourth comparison circuit (CMP4)244_1, first to fourth slave transmitters, and first to fourth slave receivers.

The fourth clock generation circuit242_1may be activated after the start of a training operation and may generate a fourth internal clock ICLK4based on the first to fourth test codes TM<1:4>. The fourth clock generation circuit242_1may generate the fourth internal clock ICLK4having a delay that is adjusted based on a combination of logic levels of the first to fourth test codes TM<1:4> after the start of a training operation. The fourth clock generation circuit242_1may store the first to fourth test codes TM<1:4> when the fourth test latch signal TM_LAT4is enabled after the start of a training operation. The fourth clock generation circuit242_1may program the stored first to fourth test codes TM<1:4> when the training operation is terminated. The fourth clock generation circuit242_1may generate the fourth internal clock ICLK4having a delay that has been adjusted based on the programmed first to fourth test codes TM<1:4> after the start of a normal operation.

The fourth core circuit243_1may be activated after the start of a training operation and may output the third internal data ID3that has been stored in the fourth core circuit243_1in synchronization with the fourth internal clock ICLK4.

A first slave receiver R241_1, among the first to fourth slave receivers, may be activated after the start of a training operation and may generate third transfer master data TMD3by receiving the master data MD.

A fourth slave transmitter T244_1, among the first to fourth slave transmitters, may be activated after the start of a training operation and may output the third internal data ID3. A fourth slave receiver R244_1, among the first to fourth slave receivers, may be activated after the start of a training operation and may generate third transfer internal data TID3by receiving the third internal data ID3from the fourth transmitter T244_1.

The first slave transmitter, the second slave transmitter, and the third slave transmitter may be deactivated after the start of a training operation. The second slave receiver and the third slave receiver may be deactivated after the start of a training operation.

The fourth comparison circuit244_1may be activated after the start of a training operation and may generate a fourth test latch signal TM_LAT4by sampling the third transfer internal data TID3based on the third transfer master data TMD3. The fourth comparison circuit244_1may be activated after the start of a training operation and may generate the fourth test latch signal TM_LAT4by comparing a time point at which the third transfer master data TMD3, received from the first slave receiver R241_1, are input to a time point at which the third transfer internal data TID3, received from the fourth slave receiver R244_1, are input. The fourth comparison circuit244_1may generate the fourth test latch signal TM_LAT4that is enabled when the time point at which the third transfer master data TMD3are input is identical to the time point at which the third transfer internal data TID3are input are identical after the start of a training operation.

FIG.20is a diagram illustrating a cross-sectional structure according to an example of a semiconductor device20aof the present disclosure. As illustrated inFIG.20, the semiconductor device20amay include a substrate200a, and multiple first to eighth memory devices210ato280a.

A cross-sectional structure of the semiconductor device20ais described. The multiple first to eighth memory devices210ato280amay be constructed in the form of a structure in which the first to eighth memory devices210ato280aare vertically stacked on the substrate200ain a stair form.

The first memory device210a, that is, a master device, may be stacked on the substrate200a. The second memory device220a, that is, a slave device, may be stacked on the first memory device210a. The third memory device230a, that is, a slave device, may be stacked on the second memory device220a. The fourth memory device240a, that is, a slave device, may be stacked on the third memory device230a.

The first memory device210amay include multiple sub-pads (SUB PAD) and a main pad (MAIN PAD). Each of the second memory device220a, the third memory device230a, and the fourth memory device240amay include the multiple sub-pads. The multiple sub-pads that are included in the first memory device210aand the multiple sub-pads that are included in the second memory device220a, the third memory device230a, and the fourth memory device240amay be electrically connected by a first wire W1. The first memory device210a, the second memory device220a, the third memory device230a, and the fourth memory device240amay be implemented to input and output commands, addresses, data, and signals through the first wire W1.

The fifth memory device250a, that is, a master device, may be stacked on the fourth memory device240a. The sixth memory device260a, that is, a slave device, may be stacked on the fifth memory device250a. The seventh memory device270a, that is, a slave device, may be stacked on the sixth memory device260a. The eighth memory device280a, that is, a slave device, may be stacked on the seventh memory device270a.

The fifth memory device250amay include multiple sub-pads (SUB PAD) and a main pad (MAIN PAD). Each of the sixth memory device260a, the seventh memory device270a, and the eighth memory device280amay include the multiple sub-pads. The multiple sub-pads that are included in the fifth memory device250aand the multiple sub-pads that are included in the sixth memory device260a, the seventh memory device270a, and the eighth memory device280amay be electrically connected through a second wire W2. The fifth memory device250a, the sixth memory device260a, the seventh memory device270a, and the eighth memory device280amay be implemented to input and output commands, addresses, data, and signals through the second wire W2.

The main pad that is included in the first memory device210aand the main pad that is included in the fifth memory device250amay be electrically connected through a third wire W3. The first memory device210aand the fifth memory device250amay be implemented to input and output commands, addresses, data, and signals through the third wire W3.

FIG.21is a block diagram illustrating a construction according to an embodiment of an electronic system1000according to an embodiment of the present disclosure. As illustrated inFIG.21, the electronic system1000may include a host1100and a semiconductor system1200.

The host1100and the semiconductor system1200may mutually transmit signals by using an interface protocol. The interface protocol that is used between the host1100and the semiconductor system1200may include a multi-media card (MMC), an enhanced small disk interface (ESDI), integrated drive electronics (IDE), peripheral component interconnect-express (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA), a serial attached SCSI (SAS), a universal serial bus (USB), etc.

The semiconductor system1200may include a controller1300and semiconductor devices1400(K:1). The controller1300may control operations of the semiconductor devices1400(K:1). Each of the semiconductor devices1400(K:1) can adjust operating speeds of multiple memory devices to be identical by programming each of test codes when a time point at which master data that are output by one of the multiple memory devices is input is identical to a time point at which internal data that are generated within the remaining memory devices are input after the start of a training operation. Each of the semiconductor devices1400(K:1) can prevent an error of data input and output operations in a normal operation by adjusting operating speeds of the multiple memory devices to be identical by programming each of the test codes when time points at which data that are output by the multiple memory devices are input are identical after the start of a training operation.

The controller1300may be implemented as the controller10, illustrated inFIG.1. Each of the semiconductor devices1400(K:1) may be implemented as the semiconductor device20, illustrated inFIG.1. In different embodiments, each of the semiconductor devices1400(K:1) may be implemented as one of dynamic random access memory (DRAM), phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM).