Gate driver on array circuit driving system and display device

The present disclosure provides a gate driver on array (GOA) circuit driving system and a display panel. The GOA circuit driving system includes a power chip including a plurality of output pins, a plurality of filter units respectively corresponding to the plurality of output pins, and a GOA circuit including a plurality of signal input terminals respectively corresponding to the plurality of output pins, wherein each of the plurality of output pins is electrically connected to the corresponding signal input terminal through the corresponding filter unit, and each of the plurality of filter units is configured to filter an electrostatic voltage transmitted from the corresponding signal input terminal to the corresponding output pin, therefore solving a problem that the power chip cannot work normally due to a release of static electricity from the GOA circuit to the power chip during an ESD test.

FIELD OF INVENTION

The present disclosure relates to the field of display technologies, and more particularly, to a gate driver on array (GOA) circuit and a display device.

BACKGROUND OF INVENTION

Liquid crystal display (LCD) has many advantages such as thin body, power saving, no radiation, etc., and is widely applied in areas such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens, notebook computer screens, etc.

Currently, most of the liquid crystal display devices on the market are backlight type liquid crystal display devices, which include a casing, a liquid crystal display panel disposed in the casing, and a backlight module disposed in the casing. The structure of the conventional liquid crystal display panel consists of a color filter, a thin film transistor (TFT) array substrate, and a liquid crystal layer disposed between the color filter and the thin film transistor array substrate.

Gate driver on array (GOA) technology is an array substrate row driving technology, which uses a TFT liquid crystal display array process to fabricate a gate scan driving circuit on a thin film transistor array substrate, in order to achieve the progressive scanning driving method. It has advantages of reducing production cost and realizing narrow frame design of panels, and are used for various displays.

Electro-static discharge (ESD) refers to charge transfer caused by objects with different electrostatic potentials coming close to each other or directly contacting each other. In current display devices, static electricity is inevitably generated during use and causes electrostatic discharge, and extremely high transient voltage generated causes electrostatic damage. For this reason, an ESD test is performed during the manufacturing process of the display device, and a discharge operation is performed to the display device during the testing process in the prior art.

Please refer toFIG. 1, the current GOA circuit driving system includes a power chip (Power IC)100and a GOA circuit200electrically connected to the power chip100. The power chip100includes a plurality of output pins110, the GOA circuit200includes a plurality of signal input terminals210, and each signal input terminal210is correspondingly connected to an output pin110, so that the power chip100outputs a plurality of drive signals including a clock signal, a constant voltage low potential, a start signal, and a low-frequency control signal by the plurality of output pins110respectively. The plurality of drive signals are transmitted to the GOA circuit200via the plurality of signal inputs210, respectively, to drive the GOA circuit200to generate gate scan signal. When performing the ESD test on the display device having the GOA circuit driving system, the GOA circuit200reverses the electrostatic voltage of a pulse voltage having a maximum value exceeding 20 V to the power chip100through the plurality of signal input terminals210and the plurality of output, pins110, affecting normal operation of the power chip100and causing the ESD test to fail. To solve this problem, please refer toFIG. 1, in the prior art, one resistor R is connected between each signal input terminals210and the corresponding output pin110. However, this method does not effectively solve the problem that the GOA circuit200reverses the static electricity to the power chip100. To solve this problem, the internal structure of the power chip100is generally redesigned, but this will increase product cost.

SUMMARY OF INVENTION

An object of the present disclosure is to provide a GOA circuit driving system, which can effectively solve the problem that the power supply chip cannot normally operate due to the static electricity transmitted from the GOA circuit to the power chip.

Another object of the present disclosure is to provide a display device, can effectively solve the problem causing the power chip fail to normally operate because the GOA circuit transmits static electricity to the power chip.

To achieve the above object, the present disclosure provides a gate driver on array (GOA) circuit driving system, including a power chip including a plurality of output pins;

a GOA circuit including a plurality of signal input terminals respectively corresponding to the plurality of output pins; and a plurality of filter units respectively corresponding to the plurality of output pins;

wherein each of the plurality of output pins is electrically connected to the corresponding signal input terminal through the corresponding filter unit, and each of the plurality of filter units is configured to filter an electrostatic voltage transmitted from the corresponding signal input terminal to the corresponding output pin.

Each of the plurality of filter units includes a filter capacitor, each of the plurality of output pins and the corresponding signal input terminal are electrically connected to a first terminal of the filter capacitor of the corresponding filter unit, and a second terminal of each of the plurality of filter capacitors is grounded.

The filter capacitor is provided with a withstand voltage of 45 to 55 volts.

The plurality of output pins includes a plurality of clock signal output pins, a plurality of low-frequency control signal output pins, a start signal output pin, and a low electric potential output pin;

wherein the plurality of signal input terminals includes:

a plurality of clock signal input terminals, the plurality of clock signal input terminals respectively corresponding to the plurality of clock signal output pins;

a plurality of low-frequency control signal input terminals, the plurality of low-frequency control signal input terminals respectively corresponding to the plurality of low-frequency control signal output pins;

a start signal input terminal corresponding to the start signal output pin; and

a constant voltage low electric potential input terminal corresponding to the low electric potential output pin.

A capacitance of the filter capacitor of the filter unit corresponding to the plurality of clock signal output pins, the plurality of low-frequency control signal output pins, and the start signal output pin is at 90 to 110 pF; and a capacitance of the filter capacitor of the filter unit corresponding to the low electric potential output pin is 0.9 to 1.1 μF.

Each of the plurality of the filter units further includes a resistor,

a terminal of the resistor of the filter unit corresponding to the plurality of clock signal output pins, the plurality of low-frequency control signal output pins, and the start signal output pin is connected to a first terminal of the filter capacitor, another terminal of the resistor corresponding to the plurality of clock signal output pins, the plurality of low-frequency control signal output pins, and the start signal output pin is connected to a corresponding signal input terminal, thereby connecting the corresponding signal input terminal and the first terminal of the filter capacitor;

a terminal of the resistor of the filter unit corresponding to the low electric potential output pin is electrical connected to a first terminal of the filter capacitor, another terminal of the resistor of the filter unit corresponding to the low electric potential output pin is connected to the low electric potential output pin, thereby connecting the first terminal of the filter capacitor and the low electric potential output pin.

A resistance of the resistor of the filter unit corresponding to the plurality of clock signal output pins is 50 to 60Ω;

a resistance of the resistor of the filter unit corresponding to the plurality of low-frequency control signal output pins is 810 to 830Ω;

a resistance of the resistor of the filter unit corresponding to the start signal output pin is 140 to 160Ω; and

a resistance of the resistor of the filter unit corresponding to the low electric potential output pin is 9 to 11Ω.

The power chip further includes a plurality of driving signal generating units respectively corresponding to the plurality of output pins;

each input terminal of the plurality of driving signal generating units receives an original input signal corresponding to the output pin, each output terminal of the plurality of driving signal generating units is electrically connected to the output pin, and the driving signal generating units are configured to convert the original input signal to generate the driving signal, and output the driving signal by the output terminal of the driving signal generating unit to the output pin.

Each of the plurality of driving signal generating units includes an electric potential converting unit and an inverter, an input terminal of the electric potential converting unit receives the corresponding original input signal, an output terminal of the electric potential converting unit is electrically connected to an input terminal of the inverter, and an output terminal of the inverter is electrically connected to the corresponding output pin;

wherein the electric potential converting unit is configured to perform electric potential conversion on the original input signal to generate a converted input signal, and output the converted input signal from the output terminal of the electric potential converting unit to the inverter, and the inverter is configured to perform an inverting process on the converted input signal to generate the corresponding driving signal and outputs the driving signal to the corresponding output pin by the output terminal of the inverter.

The present disclosure further provides a display device, includes the GOA circuit driving system described above.

Advantageous effects of the present disclosure: the present disclosure provides a GOA circuit driving system which includes a power chip including a plurality of output pins, a plurality of filter units respectively corresponding to the plurality of output pins, and a GOA circuit including a plurality of signal input terminals respectively corresponding to the plurality of output pins, wherein each of the plurality of output pins is electrically connected to the corresponding signal input terminal through the corresponding filter unit, and each of the plurality of filter units is configured to filter an electrostatic voltage transmitted from the corresponding signal input terminal to the corresponding output pin, therefore solving a problem that the power chip cannot work normally due to a release of static electricity from the GOA circuit to the power chip during an ESD test.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In order to further clarify the technical means and effects of the present disclosure, the following detailed description will be made in conjunction with the preferred embodiments of the present disclosure and the accompanying figures.

Referring toFIG. 2, the present disclosure provides a gate driver on array (GOA) circuit driving system, which includes a power chip10including a plurality of output pins11. A GOA circuit30includes a plurality of signal input terminals31respectively corresponding to the plurality of output pins11. A plurality of filter units20respectively correspond to the plurality of output pins11; wherein each of the plurality of output pins11is electrically connected to the corresponding signal input terminal31through the corresponding filter unit20. Each of the plurality of filter units20is configured to filter an electrostatic voltage transmitted from the corresponding signal input terminal31to the corresponding output pin11.

Specifically, referring toFIG. 2, each of the plurality of filter units20includes a filter capacitor C1, and each of the plurality of output pins11and the corresponding signal input terminal31are electrically connected to a first terminal of the filter capacitor C1of the corresponding filter unit20. A second terminal of each of the plurality of filter capacitors C1is grounded.

Preferably, the filter capacitor C1is provided with a withstand voltage of 45 to 55 volts, preferably 50 volts.

Specifically, referring toFIG. 2, the plurality of output pins11include a plurality of clock signal output pins, a plurality of low-frequency control signal output pins, a start signal output pin STVOUT, and a low electric potential output pin DCHG; wherein the plurality of signal input terminals31include a plurality of clock signal input terminals respectively corresponding to the plurality of clock signal output pins, a plurality of low-frequency control signal input terminals respectively corresponding to the plurality of low-frequency control signal output pins, a start signal input terminal STV corresponding to the start signal output pin STVOUT, and a constant voltage low voltage potential input terminal VSS corresponding to the low electric potential output pin DCHG.

Further, referring toFIG. 2, the plurality of clock signal output pins include a first clock signal output pin CLK1, a second clock signal output pin CLK2, a third clock signal output pin CLK3, a fourth clock signal output pin CLK4, a fifth clock signal output pin CLK5, and a sixth clock signal output pin CLK6. The plurality of clock signal input terminals include a first clock signal input terminal CK1, a second clock signal input terminal CK2, a third clock signal input terminal CK3, a fourth clock signal input terminal CK4, a fifth clock signal input terminal CK5, and a sixth clock signal input terminal CK6, respectively corresponding to the first clock signal output pin CLK1, the second clock signal output pin CLK2, the third clock signal output pin CLK3, the fourth clock signal output pin CLK4, the fifth clock signal output pin CLK5, and the sixth clock signal output pin CLK6. The plurality of low-frequency control signal output pins31include a first low-frequency control signal output pin LC1and a second low-frequency control signal output pin LC2. The plurality of low-frequency control signal input terminals include a first low-frequency control signal input terminal Ic1and a second low-frequency control signal input terminal Ic2respectively corresponding to the first low-frequency control signal output pin LC1and the second low-frequency control signal output pin LC2.

Further, a capacitance of the filter capacitor C1of the filter unit20corresponding to the plurality of clock signal output pins, the plurality of low-frequency control signal output pins, and the start signal output pin is 90 to 110 pF, preferably 100 pF. A capacitance of the filter capacitor C1of the filter unit20corresponding to the low voltage potential output pin DCHG is 0.9 to 1.1 μF, preferably 1 μF.

Specifically, referring toFIG. 2, each filter unit20further includes a resistor R1, a terminal of the resistor R1of the filter unit20corresponding to the plurality of clock signal output pins, the plurality of low-frequency control signal output pins, and the start signal output pin STVOUT is electrically connected to a first terminal of the filter capacitor C1, and another terminal of the resistor R1is electrically connected to the corresponding signal input terminal31, thereby electrically connecting the corresponding signal input terminal31and the first terminal of the filter capacitor C1. A terminal of the resistor R1of the filter unit20corresponding to the low voltage potential output pin DCHG is electrically connected to a first terminal of the filter capacitor C1, and another terminal of the resistor R1of the filter unit20corresponding to the low voltage potential output pin DCHG is electrically connected to the low voltage potential output pin DCHG, thereby electrically connecting the first terminal of the filter capacitor C1and the low voltage potential output pin DCHG.

Further, a resistance of the resistor R1of the filter unit20corresponding to the plurality of clock signal output pins is 50 to 60Ω, preferably 56Ω; a resistance of the resistor R1of the filter unit20corresponding to the plurality of low-frequency control signal output pins is 810 to 830Ω, preferably 820Ω; a resistance of the resistor R1of the filter unit20corresponding to, the start signal output pin STVOUT is 140 to 160Ω, preferably 150Ω; and a resistance of the resistor R1of the filter unit20corresponding to the low voltage potential output pin DCHG is 9 to 11Ω, preferably 10Ω.

Specifically, referring toFIG. 2, the power chip10further includes a plurality of driving signal generating units12respectively corresponding to the plurality of output pins11. Each input terminal of the plurality of driving signal generating units12receives an original input signal corresponding to the corresponding output pin11, each output terminal of the plurality of driving signal generating unit12is electrically connected to the corresponding output pin11, and the driving signal generating units12are configured to convert the original input signal to generate the driving signal, and output the driving signal by the output terminal of the driving signal generating unit12to the corresponding output pin11.

Further, referring toFIG. 2, each of the plurality of driving signal generating units12includes an electric potential converting unit121and an inverter122. An input terminal of the electric potential converting unit121receives the corresponding original input signal, an output terminal of the electric potential converting unit122is electrically connected to an input terminal of the inverter122. An output terminal of the inverter122is electrically connected to the corresponding output pin11. The electric potential converting unit121is configured to perform electric potential conversion on the original input signal to generate a converted input signal, and output the converted input signal from the output terminal of the electric potential converting unit121to the inverter122. The inverter122is configured to perform an inverting process on the converted input signal to generate the corresponding driving signal and output the driving signal to the corresponding output pin11by the output terminal of the inverter122.

Further, please refer toFIG. 2, the first clock signal output pin CLK1, the second clock signal output pin CLK2, the third clock signal output pin CLK3, the fourth clock signal output pin CLK4, the fifth clock signal output pin CLK5, the sixth clock signal output pin CLK6, the first low-frequency control signal output pin LC1, the second low-frequency control signal output pin LC2, the start signal output pin STVOUT, and the low potential output pin DCHG correspond to a first input signal CLK10, a second input signal CLK20, a third input signal CLK30, a fourth input signal CLK40, a fifth input signal CLK50, a sixth input signal CLK60, a seventh input signal LC10, an eighth input signal LC20, a ninth input signal STV1, and a tenth input signal VSS1of the original input signals, respectively. The plurality of driving signal generating units12respectively convert the first input signal CLK10, the second input signal CLK20, the third input signal CLK30, the fourth input signal CLK40, the fifth input signal CLK50, the sixth input signal CLK60, the seventh input signal LC10, the eighth input signal LC20, the ninth input signal STV1, and the tenth input signal VSS1to generate a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock, a first low-frequency control signal, a second low-frequency control signal, a start signal, and a constant voltage low electric potential signal, respectively, and output to the first clock signal output pin CLK1, the second clock signal output pin CLK2, the third clock signal output pin CLK3, the fourth clock signal output pin CLK4, the fifth clock signal output pin CLK5, the sixth clock signal output pin CLK6, the first low-frequency control signal output pin LC1, the second low-frequency control signal output pin LC2, the start signal output pin STVOUT, and the low electric potential output pin DCHG, and further transmit the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the fifth clock signal, the sixth clock signal, the first low-frequency control signal, the second low-frequency control signal, the start signal, and the constant voltage low electric potential to the first clock signal input terminal CK1, the second clock signal input terminal CK2, the third clock signal input terminal CK3, the fourth clock signal input terminal CK4, the fifth clock signal input terminal CK5, the sixth clock signal input terminal CK6, the first low-frequency control signal input terminal Ic1, the second low-frequency control signal input terminal Ic2, the start signal input terminal STV, and the low potential input terminal VSS, respectively, thereby driving the GOA circuit30to generate the gate scan signals.

Specifically, the inverter13includes a P-type field effect transistor Q1and an N-type field effect transistor Q2. A gate of the P-type field effect transistor Q1is the input terminal of the inverter13and is electrically connected to the gate of the N-type field effect transistor Q2, a source of the P-type field effect transistor Q1is connected to the constant voltage high electric potential VGH, and a drain of the P-type field effect transistor Q1is the output terminal of the inverter13and is electrically connected to the drain of the N-type field effect transistor Q2. A source of the N-type field effect transistor Q2is connected to a constant voltage negative low electric potential VGL.

It should be noted that the GOA circuit driving system of the present disclosure provides the plurality of filter units20corresponding to the plurality of output pins11respectively, and each output pin11is electrically connected the corresponding signal input terminal31through the corresponding filter unit20, the filter unit20includes a capacitor C1having less capacitance, so that when performing the EDA test, when the GOA circuit30discharges the electrostatic voltage through the plurality of signal input terminals31, because of the short time of the electrostatic discharge, the plurality of capacitors C1of the plurality of filter units20can filter the electrostatic voltage transmitted by the corresponding signal input terminal31to the corresponding output pin11to prevent the electrostatic voltage from being reversed into the power chip10via the plurality of output pins11, solving the problem that the power supply chip10cannot work normally due to the release of static electricity from the GOA circuit30to the power chip10in the ESD test. At the same time, because the capacitance of the capacitor C1in the present disclosure is less, the waveform of the signal output from the plurality of output pins11would not be influenced during normal driving.

Based on the same inventive concept, the present disclosure also provides a display device including the above-described GOA circuit driving system, and the structure of the GOA circuit system will not be repeatedly described herein.

It should be noted that the GOA circuit driving system of the display device of the present disclosure provides the plurality of filter units20corresponding to the plurality of output pins11respectively, and each output pin11is electrically connected the corresponding signal input terminal31through the corresponding filter unit20, the filter unit20includes a capacitor C1having less capacitance, so that when performing the EDA test, when the GOA circuit30discharges the electrostatic voltage through the plurality of signal input terminals31, because of the short time of the electrostatic discharge, the plurality of capacitors C1of the plurality of filter units20can filter the electrostatic voltage transmitted by the corresponding signal input terminal31to the corresponding output pin11to prevent the electrostatic voltage from being reversed into the power chip10via the plurality of output pins11, solving the problem that the power supply chip10cannot work normally due to the release of static electricity from the GOA circuit30to the power chip10in the ESD test. At the same time, because the capacitance of the capacitor C1in the present disclosure is less, the waveform of the signal output from the plurality of output pins11would not be influenced during normal driving.

In summary, the GOA circuit driving system of the present disclosure includes a power chip including a plurality of output pins, a plurality of filter units respectively corresponding to the plurality of output pins, and a GOA circuit including a plurality of signal input terminals respectively corresponding to the plurality of output pins, wherein each of the plurality of output pins is electrically connected to the corresponding signal input terminal through the corresponding filter unit, and each of the plurality of filter units is configured to filter an electrostatic voltage transmitted from the corresponding signal input terminal to the corresponding output pin, therefore solving the problem that the power chip cannot work normally due to the release of static electricity from the GOA circuit to the power chip in the ESD test.

In the above, various other changes and modifications can be made in accordance with the technical solutions and technical concept of the present disclosure, and all such changes and modifications are within the scope of the claims of the present disclosure.