Gate-all-around structures and manufacturing method thereof

Some implementations described herein provide a semiconductor device that includes a first set of gate-all-around (GAA) structures, having a first gate pitch, that includes a first set of source/drains having a first source/drain width and a first set of top spacers, having a first spacer width, disposed between a first set of gates of the first set of GAA structures and the first set of source/drains. The semiconductor device includes a second set of GAA structures having a second gate pitch, that, includes a second set of source/drains having a second source/drain width and a second set of top spacers, having a second spacer width, disposed between a second set of gates of the second set of GAA structures and the second set of source/drains.

BACKGROUND

A field-effect transistor (FET) is a type of transistor that uses an electric field to control the flow of current. A FET includes three terminals: a source, a gate, and a drain. In operation, a FET controls the flow of current through the application of a voltage to the gate which, in turn, alters conductivity between the drain and the source. A commonly used type of FET is a metal-oxide-semiconductor field-effect transistor (MOSFET). A MOSFET can be used, for example, as a switch for an electrical signal (e.g., a radio frequency (RF) switch) or as an amplifier for an electrical signal (e.g., a low-noise amplifier (LNA)), among other examples. A gate-all-around (GAA) structure may be formed as a type of MOSFET in which multiple alternating layers of gate material and silicon material are stacked between epitaxial structures. GAA structures may have improved device density in a width dimension (e.g., a critical dimension) when compared to a fin field-effect transistor (FinFET) structure. For example, GAA structures may be formed with sub-7 nanometer dimensions.

DETAILED DESCRIPTION

A semiconductor device may be formed having multiple field-effect transistors (FET) structures having different specifications that optimize different structures for different applications. For example, a first set of FET structures may be configured with a relatively high threshold voltage (Vt) and a second set of FET structures may be configured with a relatively low Vt. To form a fin field-effect transistor (FinFET) structure having devices with different Vts, one or more semiconductor processing tools may deposit a first set of materials for a first set of devices, selectively remove the first set of materials from one or more portions of the FinFET structure, and deposit a second set of materials to form a second set of devices (having a different Vt from the first set of devices) on the one or more portions of the FinFET structure.

Manufacturing processes present challenges for forming semiconductor devices that include GAAs structures having different Vts based on GAA structures being formed with sub-7 nanometer dimensions, and based on GAA structures being formed using multiple layers of gate material, channel material, and dielectric material stacked between epitaxial structures. For example, a manufacturing process may include depositing a first layer of a first set of GAA structures (e.g., configured for a first Vt) between a first set of epitaxial structures, attempting to remove the first layer from between a second set of epitaxial structures, and depositing a second layer of a second set of GAA structures (e.g., configured for a second Vt) between a second set of epitaxial structures. However, one or more semiconductor processing tools may fail to remove all of the first layer and/or may remove a portion of an additional layer below the first layer between the second set of epitaxial structures. The layer below the first layer may include a thin dielectric material, removal of which may cause the GAA structure to fail. Additionally, or alternatively, a processing time may increase based on increasing an amount of time for a removal operation used to attempt to remove the first layer and to remove subsequent layers of stacked materials to form the first set of GAA structures and the second set of GAA structures.

In some implementations described herein, dimensions (e.g., a gate pitch, a spacer width, a source/drain width, and/or a gate width, among other examples) of a first set of GAA structures may differ from dimensions of a second set of gate structures to configure the first set of GAA structures with a first Vt that is different from a second Vt of the second set of GAA structures. The dimensions may include a width (e.g., along one or more logical axes) of one or more layers of the first set of GAA structures and the second set of GAA structures. For example, a first width of a first set of layers of the first set of GAA structures may be different from a second width of a second set of layers of the second set of GAA structures. In some implementations, the first set of layers may have a same thickness as the second set of layers and/or may be formed in a same deposition process as the second set of layers. In this way, a semiconductor device may be formed with a first set of GAA structures configured with a first Vt and a second set of GAA structures configured with a second Vt without a need to deposit and remove layers of the GAA structures separately for the first set of GAA structures and the second set of GAA structures. This may allow the first set of GAA structures to be optimized for a first application and the second set of GAA structures to be optimized for a second application.

In some implementations, a first set of GAA structures is formed with a first gate pitch (e.g., spacing between gates along a width of a semiconductor structure and/or a sum of a gate width, spacer widths, and/or dielectric structure widths) and a second set of GAA structures is formed with a second gate pitch that is greater than the first gate pitch. The first set of GAA structures may be formed with a first set of source/drains having widths that are less than widths of a second set of source/drains of the second set of GAA structures. The second set of source/drains may be formed with a doping concentration that is greater than a doping concentration of the first set of source/drains. In this way, the first set of GAA structures may be configured for high density and low leakage applications and the second set of GAA structures may be configured for low resistance and/or low power consumption applications.

In some implementations, a first set of GAA structures is formed with a first gate width (e.g., along a width of a semiconductor structure) and a second set of GAA structures is formed with a second gate width that is less than the first gate width. The first set of GAA structures may be formed with a first set of source/drains having widths that are less than widths of a second set of source/drains of the second set of GAA structures. The second set of source/drains may be formed with a doping concentration that is greater than a doping concentration of the first set of source/drains. The first set of GAA structures and the second set of GAA structures may have a same gate pitch. In this way, the first set of GAA structures may be configured for low leakage and higher Vt applications and the second set of GAA structures may be configured for low resistance, lower Vt, and/or low power consumption applications. In some aspects, the first set of GAA structures has a Vt that is greater than the Vt of the second set of GAA structures by an amount in a range of approximately 10 millivolts to approximately 50 millivolts.

In some implementations, a first set of GAA structures is formed with a first gate pitch (e.g., spacing between gates along a width of a semiconductor structure) and a second set of GAA structures is formed with a second gate pitch that is greater than the first gate pitch. The first set of GAA structures may be formed with a first set of top spacers having widths that are less than widths of a second set of top spacers of the second set of GAA structures. In this way, the first set of GAA structures may be configured for high density applications and the second set of GAA structures may be configured for gate to contact capacitance reduction.

FIG.1is a diagram of an example environment100in which systems and/or methods described herein may be implemented. As shown inFIG.1, environment100may include a plurality of semiconductor processing tools102-108and a wafer/die transport tool110. The plurality of semiconductor processing tools102-108may include a deposition tool102, an etching tool104, a planarization tool106, an ion implantation tool108, and/or another semiconductor processing tool. The tools included in the example environment100may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing and/or manufacturing facility, or another location.

The deposition tool102is a semiconductor processing tool that is capable of depositing various types of materials onto a substrate. In some implementations, the deposition tool102includes a spin coating tool that is capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, the deposition tool102includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some implementations, the deposition tool102includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the example environment100includes a plurality of types of deposition tools102.

The etching tool104is a semiconductor processing tool that is capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool104may include a wet etching tool, a dry etching tool, and/or another type of etching tool. A wet etching tool may include a chemical etching tool or another type of wet etching tool that includes a chamber filled with an etchant. The substrate may be placed in the chamber for a particular time period to remove particular amounts of one or more portions of the substrate. A dry etching tool may include a plasma etching tool, a laser etching tool, a reactive ion etching tool, or a vapor phase etching tool, among other examples. A dry etching tool may remove one or more portions of a the substrate using a sputtering technique, a plasma-assisted etch technique (e.g., a plasma sputtering technique or another type of technique involving the use of an ionized gas to isotropically or directionally etch the one or more portions), or another type of dry etching technique.

The planarization tool106is a semiconductor processing tool that is capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, the planarization tool106may include a chemical mechanical planarization (CMP) tool and/or another type of planarization tool that polishes or planarizes a layer or surface of deposited or plated material. The planarization tool106may polish or planarize a surface of a semiconductor device with a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). The planarization tool106may utilize an abrasive and corrosive chemical slurry in conjunction with a polishing pad and retaining ring (e.g., typically of a greater diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head may rotate with different axes of rotation to remove material and even out any irregular topography of the semiconductor device, making the semiconductor device flat or planar.

The ion implantation tool108is a semiconductor processing tool that is capable of implanting ions into a substrate such as a semiconductor wafer. The ion implantation tool108generates ions in an arc chamber from a source material such as a gas or a solid. The source material is provided into the arc chamber, and an arc voltage is discharged between a cathode and an electrode to produce a plasma containing ions of the source material. One or more extraction electrodes are used to extract the ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam may be directed toward the substrate such that the ions are implanted below the surface of the substrate to dope the substrate.

Wafer/die transport tool110includes a mobile robot, a robot arm, a tram or rail car, an overhead hoist transfer (OHT) vehicle, an automated material handling system (AMES), and/or another type of tool that is used to transport wafers and/or dies between semiconductor processing tools102-106and/or to and from other locations such as a wafer rack, a storage room, or another location. In some implementations, wafer/die transport tool110may be a programmed tool to travel a particular path and/or may operate semi-autonomously or autonomously.

The number and arrangement of tools shown inFIG.1are provided as one or more examples. In practice, there may be additional tools, fewer tools, different tools, or differently arranged tools than those shown inFIG.1. Furthermore, two or more tools shown inFIG.1may be implemented within a single tool, or a single tool shown inFIG.1may be implemented as multiple, distributed tools. Additionally, or alternatively, a set of tools (e.g., one or more tools) of environment100may perform one or more functions described as being performed by another set of tools of environment100.

FIGS.2A-2Dare diagrams of an example semiconductor device200described herein. The semiconductor device200may include one or more additional devices, structures, and/or layers not shown inFIGS.2A-2D. For example, the semiconductor device200may include additional layers formed on layers above and/or below the portion of the semiconductor device200shown inFIGS.2A-2D. Additionally, or alternatively, one or more additional semiconductor structures may be formed in a same layer, with a lateral displacement, as the portion of the semiconductor device200shown inFIGS.2A-2D.

FIG.2Ashows a top view of the semiconductor device200,FIG.2Bshows a cross-section of the semiconductor device200at locations indicated by X1 and X3 inFIG.2A,FIG.2Cshows a cross-section of the semiconductor device200at locations indicated by X2 and X4 inFIG.2A, andFIG.2Dshows a cross-section of the semiconductor device200at locations indicated by Y1 and Y2 inFIG.2A.

As shown inFIG.2A, a set of GAA structures202have a gate pitch204(e.g., a lateral distance between gates of the set of GAA structures202). The set of GAA structures202includes source/drains206and208. Source/drains206may be N-doped source/drains (e.g., with phosphorus doping) and source/drains208may be P-doped source/drains (e.g., with boron doping), or source/drains206may be P-type source/drains and source/drains208may be N-type source/drains. The source/drains206and208may include silicon-based material and/or silicon germanium-based material. For example, N-doped source/drains may include silicon and phosphorus (SiP), silicon and carbon (SiC), silicon phosphorus and carbon (SiPC), and/or silicon boron and arsenic (SiPAs), among other examples. P-doped source/drains may include silicon and germanium with boron doping (SiGe+B), silicon germanium and carbon with boron doping (SiGeC+B), germanium with boron doping (Ge+B), and/or silicon with boron doping (Si+B), among other examples. The source/drains206and/or208may be epitaxial structures.

The set of GAA structures202includes top spacers210disposed between gates212and the source/drains206and208. The top spacers210may be formed of a dielectric material that provides electrical insulation between the gates212and the source/drains206and208. The top spacers210may be formed adjacent to a top-most gate212. Additional spacers (e.g., inner spacers, may be disposed below the top spacers210and adjacent to lower gates212. The inner spacers may have a higher K value than the one or more top spacers. The inner spacers may include SiO2, Si3N4, SiON, SiOC, SiOCN, and/or an air gap, among other examples. The inner spacers may have a width that is different from (e.g., less than) a width of the top spacers210. The one or more top spacers210may include SiO2, Si3N4, carbon-doped oxide, nitrogen-doped oxide, porous oxide, and/or an air gap, among other examples. The set of GAA structures202may include gate end dielectrics at the ends of the gates212to electrically insulate the gates212from other structures of the semiconductor device200. In some implementations, the set of GAA structures202includes a gate-top dielectric layer disposed on a top surface of the gates212. The gate-top dielectric layer may have a thickness in a range of approximately 2 nanometers to approximately 60 nanometers. The gate-top dielectric layer may include SiOC, SiON, SiOCN, nitride base dielectric, metal oxide dielectric, Hf oxide (HfO2), Ta oxide (Ta2O5), Ti oxide (TiO2), Zr oxide (ZrO2), Al oxide (Al2O3), and/or Y oxide (Y2O3), among other examples.

The set of GAA structures202may include a conductive structure214(e.g., in an M1 layer) that provides an electrical connection to a voltage drain (Vdd) for the semiconductor device200. The set of GAA structures202may also include a conductive structure216(e.g., in the M1 layer) that provides an electrical connection to a voltage source (Vss) for the semiconductor device200.

The set of GAA structures202may include a set of N-type metal-oxide field-effect transistors218(NMOSFETs) and a set of P-type metal-oxide field-effect transistors220(PMOSFETs). Active areas of the NMOSFETs (e.g., where writing, erasing, and reading functions are performed) may include a region of the set of GAA structures that includes the X1 cross-section and a region of the set of GAA structures that includes the X2 cross-section.

A set of GAA structures222have a gate pitch224(e.g., a distance between gates of the set of GAA structures222). In some implementations, the gate pitch224has a same pitch as the gate pitch204. In some implementations, the gate pitch224has a different pitch from the gate pitch204. The set of GAA structures222includes source/drains226and228. Source/drains226may be N-doped source/drains (e.g., with boron doping) and source/drains228may be P-doped source/drains (e.g., with phosphorus doping), or source/drains226may be P-type source/drains and source/drains228may be N-type source/drains. The source/drains226and228may include silicon-based material and/or silicon germanium-based material. For example, N-doped source/drains may include silicon and phosphorus (SiP), silicon and carbon (SiC), silicon phosphorus and carbon (SiPC), and/or silicon boron and arsenic (SiPAs), among other examples. P-doped source/drains may include silicon and germanium with boron doping (SiGe+B), silicon germanium and carbon with boron doping (SiGeC+B), germanium with boron doping (Ge+B), and/or silicon with boron doping (Si+B), among other examples. The source/drains226and/or228may be epitaxial structures.

In some implementations, the source/drains226and228may be formed in a same set of processes used to form the source/drains206and208. For example, a first set of deposition and etching processes may be used to form the source/drains206and226and a second set of deposition and etching processes may be used to form the source/drains208and228.

The set of GAA structures222includes top spacers230disposed between gates232and the source/drains226and228. The top spacers230may be formed of a dielectric material that provides electrical insulation between the gates232and the source/drains226and228. In some implementations, the top spacers230may be formed in a same set of processes used to form the top spacers210. The top spacers230may be adjacent to a top-most gate232. Additional spacers (e.g., inner spacers) may be disposed below the top spacers230and adjacent to lower gates232. The one or more inner spacers may have a higher K value than the one or more top spacers230. The one or more inner spacers may include SiO2, Si3N4, SiON, SiOC, SiOCN, and/or an air gap, among other examples. The inner spacers may have a width that is different from (e.g., less than) a width of the top spacers230. The one or more top spacers230may include SiO2, Si3N4, carbon-doped oxide, nitrogen-doped oxide, porous oxide, and/or an air gap, among other examples. In some implementations, the gate end dielectrics at the ends of the gates232may be formed in a same set of processes used to form the gate end dielectrics at the ends of the gates212. In some implementations, the set of GAA structures222includes a gate-top dielectric layer disposed on a top surface of the gates232. The gate-top dielectric layer may have a thickness in a range of approximately 2 nanometers to approximately 60 nanometers. The gate-top dielectric layer may include SiOC, SiON, SiOCN, nitride base dielectric, metal oxide dielectric, Hf oxide (HfO2), Ta oxide (Ta2O5), Ti oxide (TiO2), Zr oxide (ZrO2), Al oxide (Al2O3), and/or Y oxide (Y2O3), among other examples.

The set of GAA structures222may include a conductive structure234(e.g., in the M1 layer) that provides an electrical connection to a voltage drain (Vdd) for the semiconductor device200. The set of GAA structures222may also include a conductive structure236(e.g., in the M1 layer) that provides an electrical connection to a voltage source (Vss) for the semiconductor device200.

The set of GAA structures222may include a set of NMOSFETs238and a set of PMOSFETS240. Active areas of the NMOSFETs (e.g., where writing, erasing, and reading functions are performed) may include a region of the set of GAA structures that includes the X3 cross-section and a region of the set of GAA structures that includes the X4 cross-section.

FIG.2Bshows the gate pitch204, the source/drains206, the top spacers210, and the gates212ofFIG.2A. Additionally, the semiconductor device200includes a substrate242and a P_Well244(disposed on the substrate242) on which the source/drains206, the top spacers210, and the gates212are disposed. In some implementations, the source/drains206may extend into the P_Well244to a depth that is greater than a depth of the gates212, the top spacers210, and/or dielectric structures associated with the gates212. For example, the source/drains206may extend into the P_Well244to a depth that is greater than the depth of the gates212, the top spacers210, and/or the dielectric structures by an amount within a range of approximately 3 nanometers to approximately 40 nanometers. The source/drains206may extend into the P_Well244based on migration of source/drain material of the source/drains206into the P_Well244.

The semiconductor device200also includes a set of gate dielectric structures246that surround and encapsulate the gates212. The set of gate dielectric structures246may provide electrical insulation between the gates212and the top spacers210. In some implementations, the gate dielectric structures246may include an interfacial layer (e.g., a tunneling-oxide material) that is disposed between the gates212and channels248(e.g., silicon-based channels) that extend from the gates212to the source/drains206. In some implementations, the gate dielectric structures246include oxide with nitrogen that is a doped dielectric (a first layer of the gate dielectric structures246) and a high-k dielectric (e.g., with K≥13) that includes dielectric material with metal content. The high-k dielectric may include Ta2O5, Al2O3, Hf content oxide, Ta content oxide, Ti content oxide, Zr content oxide, Al content oxide, La content oxide, and/or a high-k dielectric material (K≥9). The gate dielectric structures246may have a thickness in a range of approximately 0.5 nanometers to approximately 3 nanometers. The channels248may extend from a first source/drain206to a second source/drain206between the gates212and the top spacers210.

On a top surface of a top layer gate212, the semiconductor device200may include a dielectric layer250. The dielectric layer250provides electrical insulation between the gates212and upper layers of the semiconductor device200.

The semiconductor device200may include a conductive structure that provides an electrical connection to a top surface of the source/drains206. The conductive structure may include a sidewall liner252(e.g., a silicon germanium-based material, or another type of contact etch stop layer) and/or a bottom liner254(e.g., a silicide-based material). The conductive structure may further include a contact256that includes a conductive material, such as titanium, titanium nitride, platinum, tungsten, cobalt, ruthenium, iridium, rhodium, tantalum nitride, and/or copper, among other examples.

The semiconductor device200may include an inter-layer dielectric258disposed on a top surface of the dielectric layer250, the contact256, and/or the sidewall liner252. The inter-layer dielectric258may include a low-k material, such as silicon dioxide, silicon nitride, or silicon oxynitride, among other examples. The inter-layer dielectric258may provide structural support to the semiconductor device200and electrical insulation between structures within the semiconductor device200.

The semiconductor device200may include a conductive structure260(e.g., a gate via) that extends through the inter-layer dielectric258and the dielectric layer250to a top surface of the top layer gate212. The conductive structure260may include an interconnect and/or a plug that includes, for example, titanium, titanium nitride, platinum, tungsten, cobalt, ruthenium, iridium, rhodium, tantalum nitride, and/or copper, among other examples. The conductive structure260provides an electrical connection between the gates212and a conductive structure262in a layer (e.g., an M1 layer) of the semiconductor device200. The conductive structure262may include a metal material such as copper (e.g., a copper bit line), cobalt, or tungsten, among other examples. The semiconductor device200may include an inter-metal dielectric264disposed on a top surface, and between elements (e.g., and on a top surface of the inter-layer dielectric258), of the conductive structure262.

FIG.2Balso shows the gate pitch224, the source/drains226, the top spacers230, and the gates232ofFIG.2A. The semiconductor device200also includes a P_Well244disposed on the substrate242on which the source/drains226, the top spacers230, and the gates232are disposed. In some implementations, the P_Well244includes a same material as the P_Well244. The P_Well244and the P_Well244may be disposed in a same deposition process and/or may have a same thickness. In some implementations, the source/drains226may extend into the P_Well244to a depth that is greater than a depth of the gates232, the top spacers230, and/or dielectric structures associated with the gates232. For example, the source/drains226may extend into the P_Well244to a depth that is greater than the depth of the gates232, the top spacers230, and/or the dielectric structures by an amount within a range of approximately 3 nanometers to approximately 40 nanometers. The source/drains226may extend into the P_Well244based on migration of source/drain material of the source/drains226into the P_Well244.

The semiconductor device200also includes a set of gate dielectric structures266that surround and encapsulate the gates232. The set of gate dielectric structures266may provide electrical insulation between the gates232and the top spacers230. In some implementations, the gate dielectric structures266may include an interfacial layer (e.g., a tunneling-oxide material) that is disposed between the gates232and channels268(e.g., silicon-based channels) that extend from the gates232to the source/drains226. In some implementations, the gate dielectric structures266include oxide with nitrogen that is a doped dielectric (a first layer of the gate dielectric structures266) and a high-k dielectric (e.g., with K≥13) that includes dielectric material with metal content. The high-k dielectric may include Ta2O5, Al2O3, Hf content oxide, Ta content oxide, Ti content oxide, Zr content oxide, Al content oxide, La content oxide, and/or a high-k dielectric material (K≥9). The gate dielectric structures266may have a thickness in a range of approximately 0.5 nanometers to approximately 3 nanometers. The channels268may extend from a first source/drain226to a second source/drain226between the gates232and the top spacers230.

On a top surface of a top layer gate232, the semiconductor device200may include a dielectric layer270. The dielectric layer270provides electrical insulation between the gates232and upper layers of the semiconductor device200.

The semiconductor device200may include a conductive structure that provides an electrical connection to a top surface of the source/drains226. The conductive structure may include a sidewall liner272(e.g., a silicon germanium-based material, or another type of contact etch stop layer) and/or a bottom liner274(e.g., a silicide-based material). The conductive structure may further include a contact256that includes a conductive material, such as titanium, titanium nitride, platinum, tungsten, cobalt, ruthenium, iridium, rhodium, tantalum nitride, and/or copper, among other examples

The semiconductor device200may include an inter-layer dielectric278disposed on a top surface of the dielectric layer270, the contact276, and/or the sidewall liner272. The inter-layer dielectric278may include a low-k material, such as silicon dioxide, silicon nitride, or silicon oxynitride, among other examples. The inter-layer dielectric278may provide structural support to the semiconductor device200and electrical insulation between structures within the semiconductor device200.

The semiconductor device200may include a conductive structure280(e.g., a gate via) that extends through the inter-layer dielectric278and the dielectric layer270to a top surface of the top layer gate232. The conductive structure280may include an interconnect and/or a plug that includes, for example, titanium, titanium nitride, platinum, tungsten, cobalt, ruthenium, iridium, rhodium, tantalum nitride, and/or copper, among other examples. The conductive structure280provides an electrical connection between the gates232and a conductive structure282in a layer (e.g., the M1 layer) of the semiconductor device200. The conductive structure282may include a metal material such as copper (e.g., a copper bit line), cobalt, or tungsten, among other examples. The semiconductor device200may include an inter-metal dielectric284disposed on a top surface, and between elements (e.g., and on a top surface of the inter-layer dielectric278), of the conductive structure282.

As shown inFIG.2B, the source/drains206have a width W1, the gates212have a width W2, the contact256has a width W3, and the top spacers210have a width W4. In some implementations, W1 is greater than W3 based on the contact256and the sidewall liner252having a combined width that is approximately equal to W1. W3 may be greater than W2 and W2 may be greater than W4. In some implementations, W4 may be in a range of approximately 3 nanometers to approximately 12 nanometers.

As further shown inFIG.2B, the source/drains226have a width W5, the gates232have a width W6, the contact276has a width W7, and the top spacers210have a width W8. In some implementations, W5 is greater than W7 based on the contact276and the sidewall liner272having a combined width that is approximately equal to W5. W7 may be greater than W6 and W6 may be greater than W8. In some implementations, W8 may be in a range of approximately 3 nanometers to approximately 12 nanometers.

The width W1 relative to the width W5, the width W2 relative to the width W6, the width W3 relative to the width W7, and/or the width W4 relative to the width W8 may be configured to optimize the set of GAA structures202and the set of GAA structures222for different applications. These relative widths for optimizations are discussed in greater detail in connection withFIGS.4A-4C.

FIG.2Cshows structures also shown inFIGS.2A and2B. In the X2 and X4 cross-sections shown inFIG.2C, the semiconductor device200includes an N_Well286(e.g., with boron doping) disposed on the substrate242instead of the P_Well244shown in the X1 and X3 cross-sections ofFIG.2B. Additionally, the X2 and X4 cross-sections show an N_Well286(e.g., with boron doping) instead of the P_Well244shown in the X1 and X3 cross-sections ofFIG.2B. In some implementations, the N_Well286includes a same material as the N_Well286. The N_Well286and the N_Well286may be disposed in a same deposition process and/or may have a same thickness.

In some implementations, the source/drains208may extend into the N_Well286to a depth that is greater than a depth of the gates212, the top spacers210, and/or the gate dielectric structures246associated with the gates212. For example, the source/drains206may extend into the N_Well286to a depth that is greater than the depth of the gates212, the top spacers210, and/or the gate dielectric structures246by an amount within a range of approximately 3 nanometers to approximately 40 nanometers.

In some implementations, the source/drains228may extend into the N_Well286to a depth that is greater than a depth of the gates232, the top spacers230, and/or the gate dielectric structures266associated with the gates232. For example, the source/drains228may extend into the N_Well286to a depth that is greater than the depth of the gates232, the top spacers230, and/or the gate dielectric structures266by an amount within a range of approximately 3 nanometers to approximately 40 nanometers.

As further shown inFIG.2C, the set of GAA structures202includes a conductive structure288(e.g., a source/drain via) that provides an electrical connection between the contact256and the conductive structure262through the inter-layer dielectric258. The conductive structure288may include titanium, titanium nitride, platinum, tungsten, cobalt, ruthenium, iridium, rhodium, tantalum nitride, and/or copper, among other examples. Similarly, the set of GAA structures222includes a conductive structure290(e.g., a source/drain via) that provides an electrical connection between the contact276and the conductive structure282through the inter-layer dielectric278. The conductive structure290may include titanium, titanium nitride, platinum, tungsten, cobalt, ruthenium, iridium, rhodium, tantalum nitride, and/or copper, among other examples.

FIG.2Dshows structures also shown inFIGS.2A-2C. In the Y1 cross-section shown inFIG.2D, the P_Well244and the N_Well286include portions that extend upward between trench isolation structures292(e.g., shallow trench isolation structures). In some implementations, the trench isolation structures292have a thickness in a range of approximately 30 nanometers to approximately 80 nanometers. A dielectric structure246of the gate dielectric structures246may be disposed on a top surface of the portion of the P_Well244that extends upward and another dielectric structure246of the gate dielectric structures246may be disposed on a top surface of the portion of the N_Well286that extends upward. The gate dielectric structures246provide electrical insulation for the P_Well244and the N_Well286, for example, as a gate dielectric.

A volume of first work function metal (e.g., a first NMOSFET-work-function metal), that forms the gates212shown inFIGS.2B and2C, is disposed on a dielectric structure246above the P_Well244and on the trench isolation structures292. A first set of the channels248are disposed within the first work function metal and above the portion of the P_Well244that extends upward. The first set of the channels248are electrically insulated from the first work function metal by the gate dielectric structures246(e.g., gate dielectrics and/or gate oxides, among other examples). In some implementations, the gate dielectric structures246may fully or partially surround portions of the first set of the channels248that are within a portion of the set of GAA structures202having the first work function metal. For example, the first set of the channels248extend between the source/drains206, and the gate dielectric structures246may be disposed between the first set of the channels248and the first work function metal, but may not be disposed between the first set of the channels248and the source/drains206.

A volume of second work function metal (e.g., a first NMOSFET-work-function metal), that forms the gates212shown inFIGS.2B and2C, is disposed on a dielectric structure246above the N_Well286and on the trench isolation structures292. A second set of the channels248are disposed within the second work function metal and above the portion of the N_Well286that extends upward. The second set of the channels248are electrically insulated from the second work function metal by the gate dielectric structures246. In some implementations, the gate dielectric structures246may fully or partially surround portions of the second set of the channels248that are within a portion of the set of GAA structures202having the second work function metal. For example, the second set of the channels248extend between the source/drains206, and the gate dielectric structures246may be disposed between the second set of the channels248and the second work function metal, but may not be disposed between the second set of the channels248and the source/drains206.

In some implementations, the first work function metal and the second work function metal may be electrically insulated from other structures of the semiconductor device200by one or more gate end dielectrics294.

In the Y2 cross-section shown inFIG.2D, the P_Well244and the N_Well286include portions that extend upward between the trench isolation structures292. A dielectric structure266of the gate dielectric structures266may be disposed on a top surface of the portion of the P_Well244that extends upward and another dielectric structure266of the gate dielectric structures266may be disposed on a top surface of the portion of the N_Well286that extends upward. The gate dielectric structures266provide electrical insulation for the P_Well244and the N_Well286, for example, as a gate dielectric.

A volume of the first work function metal (e.g., the same first work function metal used in the set of GAA structures202), that forms the gates232shown inFIGS.2B and2C, is disposed on a dielectric structure266above the P_Well244and on the trench isolation structures292. A first set of the channels268are disposed within the first work function metal and above the portion of the P_Well244that extends upward. The first set of the channels268are electrically insulated from the first work function metal by the gate dielectric structures266(e.g., gate dielectrics and/or gate oxides, among other examples). In some implementations, the gate dielectric structures266may fully or partially surround portions of the first set of the channels268that are within a portion of the set of GAA structures222having the first work function metal. For example, the first set of the channels268extend between the source/drains226, and the gate dielectric structures266may be disposed between the first set of the channels268and the first work function metal, but may not be disposed between the first set of the channels268and the source/drains226.

A volume of second work function metal (e.g., a first NMOSFET-work-function metal), that forms the gates232shown inFIGS.2B and2C, is disposed on a dielectric structure266above the N_Well286and on the trench isolation structures292. A second set of the channels268are disposed within the second work function metal and above the portion of the N_Well286that extends upward. The second set of the channels268are electrically insulated from the second work function metal by the gate dielectric structures266. In some implementations, the gate dielectric structures266may fully or partially surround portions of the second set of the channels268that are within a portion of the set of GAA structures222having the second work function metal. For example, the second set of the channels268extend between the source/drains226, and the gate dielectric structures266may be disposed between the second set of the channels268and the second work function metal, but may not be disposed between the second set of the channels268and the source/drains226.

In some implementations, the first work function metal and the second work function metal may be electrically insulated from other structures of the semiconductor device200by one or more gate end dielectrics296.

As shown inFIG.2D, the first set of the channels248have a thickness T1, a width W9, and a spacing (e.g., vertical spacing) of S1. The second set of the channels248have a thickness T2, a width W10, and a spacing (e.g., vertical spacing) of S2. The first set of the channels268have a thickness T3, a width W11, and a spacing (e.g., vertical spacing) of S3. The second set of the channels268have the thickness T4, a width W12, and a spacing (e.g., vertical spacing) S4. In some implementations, the thickness T1 is approximately equal (e.g., within approximately 5%) to the thickness T2, the thickness T3 is approximately equal (e.g., within approximately 5%) to the thickness T4, the spacing S1 is approximately equal (e.g., within approximately 5%) to the spacing S3, and/or the spacing S2 is approximately equal (e.g., within approximately 5%) to the spacing S4 based on, for example, using a same set of deposition and/or etching processes to form the channels248and the channels268, the gates212and the gates232, and/or the gate dielectric structures246and the gate dielectric structures266.

In some implementations, the set of gate dielectric structures246may have a same thickness as the set of gate dielectric structures266. In some implementations, the set of gate dielectric structures246may be deposited in a same process used to deposit the set of gate dielectric structures266. In this way, a manufacturing process may reduce a number of depositions and removals of materials to separately form the set of gate dielectric structures246and the gate dielectric structures266.

In some implementations, S1 is approximately equal to S2 (e.g., within 5%), S1 is approximately equal to S3 (e.g., based on being formed in a same deposition process), S2 is approximately equal to S4 (e.g., based on being formed in a same deposition process), and/or S3 is approximately equal to S4 (e.g., within 5%). In some implementations, the channels248and268have a pitch (e.g., T1+S1, T2+S2, T3+S3, and T4+S4) that is in a range of approximately 10 nanometers to approximately 23 nanometers. In some implementations, T1, T2, T3, and T4 are in a range of approximately 4 nanometers to approximately 8 nanometers. In some implementations, S1, S2, S3, and S4 are in a range of approximately 6 nanometers to approximately 15 nanometers

In some implementations, a first work function metal used to form a first subset of the gates212(e.g., above the P_Well244) may be a same work function metal used to form a first subset of the gates232(e.g., above the P_Well244). In some implementations, a second work function metal (e.g., a different material from the first work function metal or a same material as the first work function metal) used to form a second subset of the gates212(e.g., above the N_Well286) may be a same work function metal used to form a second subset of the gates232(e.g., above the N_Well286). In this way, a manufacturing process may include using a combined deposition process (e.g., including one or more deposition steps) to deposit layers of the first subset of the gates212and the first subset of the gates232and may include using a combined deposition process to deposit layers of the second subset of the gates212and the second subset of the gates232, which may reduce a number of depositions and removals of materials to separately form each of the four work function metals and the associated gates between the channels248and268. This may reduce occurrences of etching away the set of gate dielectric structures246and266, which may cause a short between the gates212and232and the channels248and268, respectively.

In some implementations, the first set of channels248are deposited in a same process used to deposit the first set of the channels268. In some implementations, the second set of channels248are deposited in a same process used to deposit the second set of the channels268. In some implementations, T1 is approximately equal to T2 (e.g., within 5%), T1 is approximately equal to T3, and/or T2 is approximately equal to T4. A manufacturing process may include using a combined deposition process (e.g., including one or more deposition steps) to deposit the first set of channels248and the first set of the channels268and may include using a combined deposition process to deposit the second set of channels248and the second set of the channels268, which may reduce a number of depositions and removals of materials to separately form each of the four sets of channels248and268. This may reduce occurrences of etching away the set of gate dielectric structures246and266, which may cause a short between the gates212and232and the channels248and268, respectively.

As also shown inFIG.2D, the conductive structure262may include multiple elements that are separated via the inter-metal dielectric264. In some implementations, the conductive structure260is electrically coupled to one or more of the elements of the conductive structure262. In some implementations, a first element of the conductive structure262provides electrical coupling to an input voltage (e.g., a source voltage (Vss)) and a second element of the conductive structure262provides electrical coupling to an output voltage (e.g., a drain voltage (Vdd)). Similarly, the conductive structure282may include multiple elements that are separated via the inter-metal dielectric284. In some implementations, the conductive structure280is electrically coupled to one or more of the elements of the conductive structure282. In some implementations, a first element of the conductive structure282provides electrical coupling to an input voltage (e.g., a source voltage (Vss)) and a second element of the conductive structure282provides electrical coupling to an output voltage (e.g., a drain voltage (Vdd)). In some implementations, the conductive structure282and the conductive structure262are a same structure and/or are disposed in a same metal layer of the semiconductor device200.

In some implementations, dimensions of structures of the set of GAA structures202may be different from dimensions of structures of the set of GAA structures222. The different dimensions may cause the set of GAA structures202to be optimized for different applications than the set of GAA structures222. For example, the GAA structures202may be optimized with different Vts, different standby power, different speeds (e.g., for program, erase, and/or read operations), capacitance, and/or resistances.

As indicated above,FIGS.2A-2Dare provided as examples. Other examples may differ from what is described with regard toFIGS.2A-2D.

As shown inFIG.3A, an N_Well286is disposed on a substrate242. In some implementations, the N_Well286may include portions that extend upward between trench isolation structures. In some implementations, one or more semiconductor processing tools form the N_Well286on a top surface of the substrate242based on depositing a layer of well material and implanting ions into the well material (e.g., using the ion implantation tool108). In some implementations, the one or more semiconductor processing tools (e.g., the etching tool104) etches one or more portions of the well material to form one or more recesses in the well material. After forming the one or more recesses in the well material, the one or more semiconductor processing tools (e.g., the deposition tool102) may deposit a trench isolation material into the one or more recesses in the well material.FIG.3Ashows portions of the N_Well286that are between trench isolation structures.

In some implementations, a semiconductor processing tool (e.g., the planarization tool106) may polish and/or planarize the substrate242before depositing the N_Well286and/or may polish and/or planarize the N_Well286after depositing the well material to form a generally planar top surfaces of the substrate242and/or the N_Well286. In this way, the top surface of the second substrate242and/or the N_Well286may be suitable for depositing additional material of the semiconductor device200.

As shown inFIG.3B, example implementation300may include depositing a first set of stacks of first silicon-base layers (to be formed into channels248, also referenced as the first silicon-based layers248) and second silicon-based layers302and304. The second silicon-based layers302and304may be deposited on the N_Well286(or the P_Well in other implementations) and the first silicon-based layers may be deposited on the second silicon-based layers in an alternating pattern. In some implementations, the one or more semiconductor processing tools (e.g., deposition tool102) alternatingly deposits material for the first silicon-based layers and material for the second silicon-based layers until a desired number of layers are formed. For example, the deposition tool102may alternatingly deposit the material for the first silicon-based layers the second silicon-based layers on the top surface of the N_Well286using chemical vapor deposition or physical vapor deposition, among other examples.

In some implementations, the first silicon-based layers include a germanium-free silicon material (e.g., having a concentration of silicon that is less than approximately 1%) and the second silicon-based layers include a germanium and silicon material (e.g., having a concentration of silicon that is greater than approximately 1%). Alternatively, the second silicon-based layers may include a germanium-free silicon material (e.g., having a concentration of silicon that is less than approximately 1%) and the first silicon-based layers may include a germanium and silicon material (e.g., having a concentration of silicon that is greater than approximately 1%).

The first silicon-based layers may have a first thickness in the set of GAA structures202and a second thickness in the set of GAA structures222. The first thickness may be approximately equal to the second thickness. The second silicon-based layers may have a first thickness in the set of GAA structures202and a second thickness in the set of GAA structures222. The first thickness may be approximately equal to the second thickness. In some implementations, the first thickness of the first silicon-based layers may be approximately equal to the first thickness of the second silicon-based layers and/or the second thickness of the first silicon-based layers may be approximately equal to the second thickness of the second silicon-based layers.

In some implementations, the first silicon-based layers for the set of GAA structures202are deposited in a same operation as deposition of the first silicon-based layers for the set of GAA structures222. In some implementations, the second silicon-based layers for the set of GAA structures202are deposited in a same operation as deposition of the second silicon-based layers for the set of GAA structures222.

In some implementations, the one or more semiconductor processing tools (e.g., planarization tool106) polish and/or planarize top surfaces of the first silicon-based layers and/or the second silicon-based layers to form generally planar top surfaces. In this way, the top surfaces of the first silicon-based layers and/or the second silicon-based layers may be suitable for depositing additional material of the semiconductor device200and/or may improve uniformity of a subsequent etching process.

As shown inFIG.3C, example implementation300may include removing portions of the second silicon-based layers302and304at a source/drain region306and at a source/drain region308of the semiconductor device200. In some implementations, the one or more semiconductor processing tools (e.g., etching tool104) etch the one or more portions of the second silicon-based layers302and304. In some implementations, the one or more semiconductor processing tools performs wet etching using a chemical that is configured to selectively etch material of the second silicon-based layers302and304and to have reduced etching of the first silicon-based layers248relative to the second silicon-based layers302and304. In some implementations, the one or more semiconductor processing tools may perform one or more operations to prevent or reduce etching outside of the source/drain portion of the semiconductor device200. For example, a hard mask or a photoresist may be applied to a top surface of the top-most layer of the second silicon-based layers302and304at regions outside of the source/drain regions306and308before etching the portions of the second silicon-based layers302and304at the source/drain regions306and308.

As shown inFIG.3D, example implementation300may include forming a first set of source/drains208between stacks of the first set of stacks and forming a second set of source/drains228between stacks of the second set of stacks. Additionally, example implementation may include forming a first set of top spacers210between source/drains of the first set of source/drains208and stacks of the first set of stacks and forming a second set of top spacers230between source/drains of the second set of source/drains228and stacks of the second set of stacks. In some implementations, the one or more semiconductor processing tools (e.g., deposition tool102) deposit (e.g., using a chemical vapor deposition or an atomic layer deposition, among other examples) the first set of top spacers210on sidewalls of the stacks of the first set of stacks and deposits the second set of top spacers230on sidewalls of the stacks of the second set of stacks. In some implementations, an etching tool removes a portion of material of the first set of top spacers210from the source/drain regions306after depositing the first set of top spacers210and removes a portion of material of the second set of top spacers230from the source/drain regions308after depositing the second set of top spacers230. In some implementations, the one or more semiconductor processing tools deposits (e.g., using a chemical vapor deposition or an atomic layer deposition, among other examples) material of the source/drains208between elements of the first set of top spacers210(and inner spacers below the top spacers210) and deposits material of the source/drains228between elements of the second set of top spacers230(and inner spacers below the top spacers230) In some implementations, deposition of the source/drains208includes depositing epitaxial material on portions of the first silicon-based layers248within the source/drain region306and/or deposition of the source/drains228includes depositing epitaxial material on portions of the first silicon-based layers268within the source/drain region308. In some implementations, example implementation300includes depositing the top spacers210and230before depositing the source/drains208and228, respectively. Alternatively, example implementation300may include depositing the top spacers210and230after depositing the source/drains208and228.

As shown inFIG.3E, example implementation300may include removing portions of the second silicon-based layers302and304at a gate regions310and at a gate regions312of the semiconductor device200. In some implementations, the one or more semiconductor processing tools (e.g., etching tool104) etch the one or more portions of the second silicon-based layers302and304using, for example, wet etching with a chemical that is configured to selectively etch material of the second silicon-based layers302and304and to have reduced etching of the first silicon-based layers248relative to the second silicon-based layers302and304. In some implementations, the one or more semiconductor processing tools may perform one or more operations to prevent or reduce etching outside of the gate portion of the semiconductor device200. For example, a hard mask or a photoresist may be applied to a top surface of the top-most layer of the second silicon-based layers302and304at regions outside of the gate regions310and312before etching the portions of the second silicon-based layers302and304at the gate regions310and312. In some implementations, the portions of the second silicon-based layers302and304at the gate regions310and at the gate regions312may be removed before forming the top spacers210and230and/or the source/drains208and228. In some implementations, a dummy gate may be dispose into the gate regions310and312after removing the second silicon-based layers302and304at the gate regions310and at the gate regions312and before forming the top spacers210and230and/or the source/drains208and228.

As shown inFIG.3F, example implementation300may include forming gates212within the gate regions310to surround the channels248within the gate regions310and may include forming gates232within the gate regions312to surround the channels268within the gate regions330. Additionally, example implementation300may include forming gate dielectric structures246between the channels248and the gates212within the gate regions310and forming gate dielectric structures266between the channels268and the gates232within the gate regions312. In some implementations, the one or more semiconductor processing tools (e.g., deposition tool102) deposit (e.g., using a chemical vapor deposition or an atomic layer deposition, among other examples) the gate dielectric structures246on the channels248before depositing the gates212(e.g., using a chemical vapor deposition, an atomic layer deposition, and/or a reflow deposition) to fill the gate regions310. Similarly, the one or more semiconductor processing tools (e.g., deposition tool102) may deposit (e.g., using a chemical vapor deposition or an atomic layer deposition, among other examples) the gate dielectric structures266on the channels268before depositing the gates232(e.g., using a chemical vapor deposition, an atomic layer deposition, and/or a reflow deposition) to fill the gate regions312. In some implementations, before depositing material for the gates212and232, the one or more semiconductor processing tools (e.g., etching tool104) may remove a dummy gate from the gate regions310and312.

In some implementations, the gates212and/or232include a work function metal deposited between and/or around the channels248and/or the channels268to form portions of the gates212and the gates232. In some implementations, the work function metal deposited between and/or around the channels248and the work function metal deposited between and/or around the channels268may be a same work function metal and/or may be deposited in a same set of operations. In some implementations, the one or more semiconductor processing tools (e.g., the deposition tool102) deposit the work function metal between and/or around the channels248and/or the channels268. In some implementations, the deposition tool102uses chemical vapor deposition, physical vapor deposition, and/or reflow, among other examples, to deposit the work function metal. In some implementations, the deposition tool102may deposit the work function metal in multiple operations. For example, the deposition tool may deposit a first layer of the work function metal (e.g., a first type of material) using a first deposition technique to coat the channels and/or gate dielectric structures246and266(e.g., using chemical vapor deposition or physical vapor deposition, among other examples) and may deposit a fill material (e.g., tungsten) of the work function metal using a second deposition technique (e.g., using reflow, among other examples). In some implementations, the work function material may have a width W2 in the first set of GAA structures202and a width W6 in the second set of GAA structures222.

As shown inFIG.3G, example implementation300may include depositing a dielectric layer250on a top surface of a top-most gate212, a top surface of a top spacer210, and/or a top surface of the source/drains228, and a dielectric layer270may be disposed on a top surface of a top-most gate232, a top surface of the top spacers230, and/or a top surface of the source/drains228. In some implementations, the dielectric layer250and the dielectric layer270may be a same dielectric material and/or may be disposed in a same operation. In some implementations, the one or more semiconductor processing tools (e.g., the deposition tool102) deposit the dielectric layer250and the dielectric layer270using chemical vapor deposition or physical vapor deposition, among other examples.

In some implementations, the one or more semiconductor processing tools (e.g., planarization tool106) polish and/or planarize a top surface of the dielectric layer250and a top surface of the dielectric layer270. In this way, the top surfaces of the dielectric layer250and the dielectric layer270may be suitable for depositing additional material of the semiconductor device200and/or may improve uniformity of a subsequent etching process.

As shown inFIG.3F, conductive structures (e.g., including a bottom liner254, a sidewall liner252, and/or a contact256, among other examples) may be disposed into recessed portions of the semiconductor device200that extends through the dielectric layer250to the source/drains208. Similarly, conductive structures (e.g., including a bottom liner274, a sidewall liner272, and/or a contact276, among other examples) may be disposed into recessed portions of the semiconductor device200that extend through the dielectric layer270to the source/drains228. In some implementations, the bottom liner254is formed of a same material and/or using a same deposition operation as the bottom liner274, the sidewall liner252is formed of a same material and/or using a same deposition operation as the sidewall liner272, and/or the contact256is formed of a same material and/or using a same deposition operation as the contact276. In some implementations, the one or more semiconductor processing tools (e.g., the deposition tool102) deposit the bottom liner254, the sidewall liner252, the contact256, the bottom liner274, the sidewall liner272, and/or the contact276. In some implementations, the deposition tool102uses chemical vapor deposition or physical vapor deposition, among other examples, to deposit the bottom liner254, the sidewall liner252, the contact256, the bottom liner274, the sidewall liner272, and/or the contact276.

In some implementations, the one or more semiconductor processing tools (e.g., planarization tool106) polish and/or planarize top surfaces of the dielectric layer250, the contact256, the sidewall liner252, the dielectric layer270, the contact276, and/or the sidewall liner272. In this way, the top surfaces of the dielectric layer250, the contact256, the sidewall liner252, the dielectric layer270, the contact276and/or the sidewall liner272may be suitable for depositing additional material of the semiconductor device.

As shown inFIG.3I, an inter-layer dielectric258may be deposited onto top surfaces of the dielectric layer250, the contact256, and/or the sidewall liner252. Similarly, an inter-layer dielectric278structure may be deposited onto top surfaces of the dielectric layer270, the contact276, and/or the sidewall liner272. In some implementations, the inter-layer dielectric258is formed of a same material and/or using a same deposition operation as the inter-layer dielectric278. In some implementations, the one or more semiconductor processing tools (e.g., the deposition tool102) deposit the inter-layer dielectric258and the inter-layer dielectric278. In some implementations, the deposition tool102uses chemical vapor deposition or physical vapor deposition, among other examples, to deposit the inter-layer dielectric258and the inter-layer dielectric278.

In some implementations, the one or more semiconductor processing tools (e.g., planarization tool106) polish and/or planarize top surfaces of the inter-layer dielectric258and the inter-layer dielectric278. In this way, the top surfaces of the inter-layer dielectric258and the inter-layer dielectric278may be suitable for depositing additional material of the semiconductor device200and/or may improve uniformity of a subsequent etching process.

As also shown inFIG.3I, a conductive structure288(e.g., a source/drain via) may be deposited through the inter-layer dielectric258to provide an electrical connection to the contact256through the inter-layer dielectric258. Similarly, a conductive structure290(e.g., a source/drain via) may be deposited through the inter-layer dielectric278to provide an electrical connection to the contact276through the inter-layer dielectric278. In some implementations, the one or more semiconductor processing tools (e.g., the etching tool104) etch portions of the inter-layer dielectric258and the inter-layer dielectric278to provide a recessed portion into which the conductive structure288and the conductive structure290may be deposited, respectively. In some implementations, the one or more processing tools (e.g., the deposition tool102) deposit the inter-layer dielectric258and the inter-layer dielectric278into the recessed portions of the inter-layer dielectric258and the inter-layer dielectric278, respectively. In some implementations, the deposition tool102uses chemical vapor deposition or physical vapor deposition, among other examples, to deposit the inter-layer dielectric258and the inter-layer dielectric278.

In some implementations, the one or more semiconductor processing tools (e.g., planarization tool106) polish and/or planarize top surfaces of the inter-layer dielectric258, the conductive structure288, the inter-layer dielectric278, and the conductive structure280. In this way, the top surfaces of the inter-layer dielectric258, the conductive structure288, the inter-layer dielectric278, and the conductive structure280may be suitable for depositing additional material of the semiconductor device.

As further shown inFIG.3I, a conductive structure262(e.g., having multiple elements coupled to different portions of the semiconductor device200) may be deposited onto top surfaces of the inter-layer dielectric258and the conductive structure288to provide an electrical connection to the conductive structure288. Similarly, conductive structure282may be deposited onto top surfaces of the inter-layer dielectric278and the conductive structure290. In some implementations, the conductive structure262is formed of a same material and/or using a same deposition operation as the conductive structure282. In some implementations, the inter-metal dielectric264is formed of a same material and/or using a same deposition operation as the inter-metal dielectric284. In some implementations, the deposition tool102uses chemical vapor deposition or physical vapor deposition, among other examples, to deposit the conductive structure262the conductive structure282, the inter-metal dielectric264, and the inter-metal dielectric284.

As additionally shown inFIG.3I, an inter-metal dielectric264may be deposited onto the conductive structure262and/or between elements of the conductive structure262to provide electrical isolation between the elements of conductive structure262. Similarly, an inter-metal dielectric284may be deposited onto the conductive structure282and/or between elements of the conductive structure282to provide electrical isolation between the elements of conductive structure282. In some implementations, the inter-metal dielectric264is formed of a same material and/or using a same deposition operation as the inter-metal dielectric284. In some implementations, the one or more semiconductor processing tools (e.g., the deposition tool102) deposit the inter-metal dielectric264and the inter-metal dielectric284. In some implementations, the deposition tool102uses chemical vapor deposition or physical vapor deposition, among other examples, to deposit the inter-metal dielectric264and the inter-metal dielectric284.

In some implementations, the one or more semiconductor processing tools (e.g., planarization tool106) polish and/or planarize top surfaces of the inter-metal dielectric264and the inter-metal dielectric284. In this way, the top surfaces of the inter-metal dielectric264and the inter-metal dielectric284may be suitable for depositing additional material of the semiconductor device200.

As indicated above,FIGS.3A-3Iare provided as an example. Other examples may differ from what is described with regard toFIGS.3A-3I. For example, an order of forming the channels248and/or268and for forming the gates212and/or232may differ from that described in connection withFIGS.3A-3I. For example, the gates212and/or232may be formed in layers along with the channels248and/or268instead of the gates212and/or232being formed after all of the channels248and/or268are formed.

FIGS.4A-4Care diagrams of example semiconductor devices400A-400C described herein. The example semiconductor devices400A-400C are examples of the semiconductor device200shown inFIGS.2A-3Iand include some or all of the same structures of the semiconductor device200. The example semiconductor devices400A-400C may include alternative dimensions of elements, which alternatives optimize the example semiconductor devices400A-400C for different applications.

As shown inFIG.4A, semiconductor device400A includes source/drains206(and source/drains208not shown) having the width W5 that is greater than the width W1 of source/drains206(and source/drains208not shown). The width W5 may be in a range of approximately 105% to approximately 140% of the width W1. Additionally, the source/drains206and/or208may have a first doping concentration that is less than a second doping concentration of the second set of source/drains226and/or228. In some implementations, N-doped source/drains of the set of GAA structures222may have a doping concentration (e.g., with phosphorus) that is in a range of approximately 140% to approximately 300% of a doping concentration of N-doped source/drains of the set of GAA structures202. Additionally, or alternatively, P-doped source/drains of the set of GAA structures222may have a doping concentration (e.g., with boron) that is in a range of approximately 150% to approximately 500% of a doping concentration of P-doped source/drains of the set of GAA structures202. In some aspects, the GAA structures202may include a doping concentration (e.g., of boron), in a set of source/drains, in a range of approximately (10{circumflex over ( )}19 elements)/centimeter{circumflex over ( )}3 to approximately (6×10{circumflex over ( )}20 elements)/centimeter{circumflex over ( )}3.

In this way, conductivities of the source/drains226and/or228may be greater than the conductivities of the source/drains206and208. In some implementations, the source/drains226and/or228are disposed into the P_Well244with a depth that is greater than a depth at which the source/drains206and/or208are disposed into the P_Well244. For example, the source/drains226and/or228may be disposed at a depth that is in a range of approximately 103% to 110% of a depth at which the source/drains206and/or208are disposed into the P_Well244and/or at a depth that is in a range of approximately 3 nanometers to approximately 10 nanometers deeper than the depth at which the source/drains206and/or208are disposed into the P_Well244. These features may increase a conductivity between the source/drains226and/or228with the P_Well244relative to a conductivity between the source/drains206and/or208with the P_Well244. Based on increasing conductivity, a resistance (e.g., for operations of the set of GAA structures222) of the set of GAA structures222relative to the set of GAA structures202is reduced. Additionally, or alternatively, the width W7 of the contact276may be greater than the width W3 of the contact256to reduce a resistance between the conductive structure288and the source/drains208. For example, the width W7 may be in a range of 110% to approximately 200% of the width W3. In this way, the resistance of the set of GAA structures222relative to the set of GAA structures202may be further reduced.

In some implementations, based on the width W5 being greater than the width W1, the gate pitch224is greater than the gate pitch204. In some implementations, the width W4 of the top spacers210is approximately equal to the width W8 of the top spacers230and/or the width W2 of the gates212is approximately equal to the width W6 of the gates232. Alternatively, the width W8 may be larger than the width W4 by an amount in a range of approximately 0.5 nanometers to approximately 5 nanometers to increase an amount by which the gate pitch224is greater than the gate pitch204and to reduce an amount of leakage from the set of GAA devices222.

Based on the gate pitch224being greater than the gate pitch204, the width W5 being greater than the width W1, and/or a doping concentration of the source/drains226and228being greater than the doping concentrations of the source/drains206and208, a resistance of the set of GAA structures222of semiconductor device400A may be reduced (e.g., based on improved ionization within the set of GAA structures222) to optimize for low Vt applications, and the GAA structures202of semiconductor device400A are optimized for high density and/or low leakage applications.

As shown inFIG.4B, the gate pitch224is greater than the gate pitch204based on the width W8 of the top spacers230being greater than the width W4 of the top spacers210. For example, the gate pitch224is in a range of approximately 105% to approximately 140% of the gate pitch204. Additionally, or alternatively, the width W8 may be in a range of approximately 110% to approximately 200% of the width W4. In some implementations, the width W2 may be approximately equal to the width W6.

Additionally, the source/drains206and/or208may have a first doping concentration that is less than a second doping concentration of the second set of source/drains226and/or228. In some implementations, N-doped source/drains of the set of GAA structures222may have a doping concentration (e.g., with phosphorus) that is in a range of approximately 140% to approximately 300% of a doping concentration of N-doped source/drains of the set of GAA structures202. Additionally, or alternatively, P-doped source/drains of the set of GAA structures222may have a doping concentration (e.g., with boron) that is in a range of approximately 150% to approximately 500% of a doping concentration of P-doped source/drains of the set of GAA structures202. In this way, conductivities of the source/drains226and/or228may be greater than the conductivities of the source/drains206and208. In some implementations, the source/drains226and/or228are disposed into the P_Well244with a depth that is greater than a depth at which the source/drains206and/or208are disposed into the P_Well244. For example, the source/drains226and/or228may be disposed at a depth that is in a range of approximately 103% to 110% of a depth at which the source/drains206and/or208are disposed into the P_Well244and/or at a depth that is in a range of approximately 3 nanometers to approximately 10 nanometers deeper than the depth at which the source/drains206and/or208are disposed into the P_Well244. These features may increase a conductivity between the source/drains226and/or228with the P_Well244relative to a conductivity between the source/drains206and/or208with the P_Well244. Based on increasing conductivity, a resistance (e.g., for operations of the set of GAA structures222) of the set of GAA structures222relative to the set of GAA structures202is reduced. Additionally, or alternatively, the width W7 may be greater than the width W3 to reduce a resistance between the conductive structure288and the source/drains208(shown inFIG.2C). For example, the width W7 may be in a range of 110% to approximately 200% of the width W3. In this way, the resistance of the set of GAA structures222relative to the set of GAA structures202may be further reduced. Further, a first capacitance associated with the top spacers210and corresponding first gate contacts260may be greater than a second capacitance associated with the second set of top spacers230and corresponding second gate contacts280.

Based on the gate pitch224being greater than the gate pitch204, the width W8 being greater than the width W4, and/or a doping concentration of the source/drains226and228being greater than the doping concentrations of the source/drains206and208, a contact to gate capacitance may be reduced for the set of GAA structures222and a gate-contact breakage voltage may be improved, and the GAA structures202are optimized for high density and reduced contact resistance and/or reduced Vt (e.g., based on having a thinner spacer) applications.

As shown inFIG.4C, the width W6 of the gates232is less than the width W2 of the gates212and the width W5 of the source/drains226is greater than the width W1 of the source/drains206. Additionally, the gate pitch204may be approximately equal to the gate pitch224. In some implementations, the width W2 is in a range of approximately 105% to approximately 240% of the width W6. The width W2 may have a width in a range of approximately 8 nanometers to approximately 20 nanometers and/or the width W6 may have a width in a range of approximately 8 nanometers to approximately 16 nanometers. In some implementations, the source/drains226and228have doping concentrations that are greater than doping concentrations of the source/drains206and208. In some implementations, the source/drains226and/or228are disposed into the P_Well244with a depth that is greater than a depth at which the source/drains206and/or208are disposed into the P_Well244. For example, the source/drains226and/or228may be disposed at a depth that is in a range of approximately 103% to 110% of a depth at which the source/drains206and/or208are disposed into the P_Well244and/or at a depth that is in a range of approximately 3 nanometers to approximately 10 nanometers deeper than the depth at which the source/drains206and/or208are disposed into the P_Well244. These features may increase a conductivity between the source/drains226and/or228with the P_Well244relative to a conductivity between the source/drains206and/or208with the P_Well244. Based on increasing conductivity, a resistance (e.g., for operations of the set of GAA structures222) of the set of GAA structures222relative to the set of GAA structures202is reduced. Additionally, or alternatively, the width W7 may be greater than the width W3 to reduce a resistance between the conductive structure288and the source/drains208. For example, the width W7 may be in a range of 110% to approximately 200% of the width W3. In this way, the resistance of the set of GAA structures222relative to the set of GAA structures202may be further reduced. Further, based on the gate pitch204being approximately equal to the gate pitch224, the set of GAA structures222may have a decreased resistance without decreasing a device density relative to the set of GAA structures202.

In some implementations, N-doped source/drains of the set of GAA structures222may have a doping concentration (e.g., with phosphorus) that is in a range of approximately 140% to approximately 300% of a doping concentration of N-doped source/drains of the set of GAA structures202. Additionally, or alternatively, P-doped source/drains of the set of GAA structures222may have a doping concentration (e.g., with boron) that is in a range of approximately 150% to approximately 500% of a doping concentration of P-doped source/drains of the set of GAA structures202. In this way, conductivities of the source/drains226and/or228may be greater than the conductivities of the source/drains206and208.

Based on the gate pitch224being approximately equal to the gate pitch204, the width W6 being less than the width W2, and/or a doping concentration of the source/drains226and228being greater than the doping concentrations of the source/drains206and208, a resistance of the set of GAA structures222may be reduced (e.g., based on improved ionization within the set of GAA structures222) to optimize for low Vt applications, and the GAA structures202are optimized for low leaking, high Vt, and low power circuit applications.

As indicated above,FIGS.4A-4Care provided as examples. Other examples may differ from what is described with regard toFIGS.4A-4C.

FIG.5is a diagram of example components of a device500, which may correspond to the deposition tool102, the etching tool104, the planarization tool106, the ion implantation tool108, and/or the wafer/die transport tool110. In some implementations, the deposition tool102, the etching tool104, the planarization tool106, the ion implantation tool108, and/or the wafer/die transport tool110may include one or more devices500and/or one or more components of device700. As shown inFIG.5, device500may include a bus510, a processor520, a memory530, a storage component540, an input component550, an output component560, and a communication component570.

Bus510includes a component that enables wired and/or wireless communication among the components of device500. Processor520includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. Processor520is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor520includes one or more processors capable of being programmed to perform a function. Memory530includes a random access memory, a read only memory, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory).

Storage component540stores information and/or software related to the operation of device500. For example, storage component540may include a hard disk drive, a magnetic disk drive, an optical disk drive, a solid state disk drive, a compact disc, a digital versatile disc, and/or another type of non-transitory computer-readable medium. Input component550enables device500to receive input, such as user input and/or sensed inputs. For example, input component550may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system component, an accelerometer, a gyroscope, and/or an actuator. Output component560enables device500to provide output, such as via a display, a speaker, and/or one or more light-emitting diodes. Communication component570enables device500to communicate with other devices, such as via a wired connection and/or a wireless connection. For example, communication component570may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.

Device500may perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory530and/or storage component540) may store a set of instructions (e.g., one or more instructions, code, software code, and/or program code) for execution by processor520. Processor520may execute the set of instructions to perform one or more processes described herein. In some implementations, execution of the set of instructions, by one or more processors520, causes the one or more processors520and/or the device500to perform one or more processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

The number and arrangement of components shown inFIG.5are provided as an example. Device500may include additional components, fewer components, different components, or differently arranged components than those shown inFIG.5. Additionally, or alternatively, a set of components (e.g., one or more components) of device500may perform one or more functions described as being performed by another set of components of device500.

FIG.6is a flowchart of an example process600relating to forming GAA structures. In some implementations, one or more process blocks ofFIG.6may be performed by one or more semiconductor processing tools (e.g., deposition tool102, etching tool104, planarization tool106, ion implantation tool108, and/or wafer/die transport tool110). Additionally, or alternatively, one or more process blocks ofFIG.6may be performed by one or more components of device500, such as processor520, memory530, storage component540, input component550, output component560, and/or communication component570.

As shown inFIG.6, process600may forming a first set of stacks of first silicon-base layers and second silicon-based layers (block610). For example, the one or more semiconductor processing tools may form the first set of stacks (e.g., of the set of GAA structures202) of first silicon-base layers248and second silicon-based layers302and304, as described above.

As further shown inFIG.6, process600may forming a second set stacks of the first silicon-base layers and the second silicon-based layers (block620). For example, the one or more semiconductor processing tools may form the second set of stacks (e.g., of the set of GAA structures222) of first silicon-base layers248and second silicon-based layers302and304, as described above.

As further shown inFIG.6, process600may forming a first set of source/drains between stacks of the first set of stacks, the first set of source/drains having a first source/drain width (block630). For example, the one or more semiconductor processing tools may form the first set of source/drains208between stacks of the first set of stacks, the first set of source/drains208having a first source/drain width W1, as described above.

As further shown inFIG.6, process600may forming a second set of source/drains between stacks of the second set of stacks, the second set of source/drains having a second source/drain width (block640). For example, the one or more semiconductor processing tools may form the second set of source/drains228between stacks of the first set of stacks, the first set of source/drains228having a second source/drain width W5, as described above.

As further shown inFIG.6, process600may forming a first set of top spacers between source/drains of the first set of source/drains and stacks of the first set of stacks (block630). For example, the one or more semiconductor processing tools may form the first set of top spacers210between source/drains of the first set of source/drains208and stacks of the first set of stacks, as described above.

As further shown inFIG.6, process600may forming a second set of top spacers between source/drains of the second set of source/drains and stacks of the second set of stacks (block640). For example, the one or more semiconductor processing tools may form the second set of top spacers230between source/drains of the second set of source/drains228and stacks of the second set of stacks, as described above.

As further shown inFIG.6, process600may forming a first set of gates between spacer elements of the first set of top spacers (block630). For example, the one or more semiconductor processing tools may form the gates212between spacer elements of the first set of top spacers210, as described above.

As further shown inFIG.6, process600may forming a second set gates between spacer elements of the second set of top spacers (block640). For example, the one or more semiconductor processing tools may form the second set of gates232between spacer elements of the first set of top spacers230, as described above. In some implementations, the first set of top spacers210have a first spacer width W4 and the second set of top spacers230have a second spacer width W8. In some implementations, the first set of gates212have a first gate width W2 and the second set of gates32have a second gate width W6. In some implementations, the first set of gate-all-around (GAA) structures202, including the first set of source/drains208, the first set of top spacers210, and the first set of gates212, is configured with a first threshold voltage. In some implementations, a second set of GAA structures222, including the second set of source/drains228, the second set of top spacers230, and the second set of gates232, is configured with a second threshold voltage. In some implementations, the first threshold voltage is different from the second threshold voltage based on one or more of the second source/drain width W5 being different from the first source/drain width W1, the second spacer width W8 being different from the first spacer width W4, or the second gate width W6 being different from the first gate width W2.

In a first implementation, forming the first set of source/drains between the stacks of the first set of stacks includes removing, at a source/drain region, the first silicon-based layers or the second silicon-based layers to form a remaining portion of the first set of stacks at the source/drain region, and depositing a epitaxial material on the remaining portion of the first set of stacks at the source/drain region.

In a second implementation, alone or in combination with the first implementation, forming the first set of gates between spacer elements of the first set of top spacers includes removing, at a gate region, the first silicon-based layers or the second silicon-based layers to form a remaining portion of the first set of stacks at the gate region, and depositing a gate material on the remaining portion of the first set of stacks at the gate region.

AlthoughFIG.6shows example blocks of process600, in some implementations, process600may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted inFIG.6. Additionally, or alternatively, two or more of the blocks of process600may be performed in parallel.

In this way, a semiconductor device may be formed with a first set of GAA structures configured with a first Vt and a second set of GAA structures configured with a second Vt without a need to deposit and remove layers of the GAA structures separately for the first set of GAA structures and the second set of GAA structures based on dimensions (e.g., widths and not thicknesses) of the first set of GAA structures differing from dimensions of the second set of gate structures. This may allow the first set of GAA structures to be optimized for a first application and the second set of GAA structures to be optimized for a second application in a way that reduces and/or avoids process limitations that would otherwise be associated with forming the first set of GAA structures and the second set of GAA structures separately using additional depositions and removals of layers having different thicknesses.

As described in greater detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a first set of GAA structures having a first gate pitch. The first set of GAA structures includes a first set of source/drains having a first source/drain width and a first set of top spacers, having a first spacer width, disposed between a first set of gates of the first set of GAA structures and the first set of source/drains. The semiconductor device includes a second set of GAA structures having a second gate pitch. The second set of GAA structures includes a second set of source/drains having a second source/drain width and a second set of top spacers, having a second spacer width, disposed between a second set of gates of the second set of GAA structures and the second set of source/drains. The second gate pitch is greater than the first gate pitch based on one or more of the second source/drain width being greater than the first source/drain width, or the second spacer width being greater than the first spacer width.

As described in greater detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a first set of GAA structures having a first gate pitch. The first set of GAA structures includes a first set of source/drains having a first doping concentration. The semiconductor device includes a second set of GAA structures having a second gate pitch that is a same gate pitch as the first gate pitch. The second set of GAA structures includes a second set of source/drains having a second doping concentration that is greater than the first doping concentration.

As described in greater detail above, some implementations described herein provide a method of manufacturing a semiconductor device. The method includes forming a first set of stacks of first silicon-base layers and second silicon-based layers. The method also includes forming a second set stacks of the first silicon-base layers and the second silicon-based layers. The method further includes forming a first set of source/drains between stacks of the first set of stacks, the first set of source/drains having a first source/drain width. The method additionally includes forming a second set of source/drains between stacks of the second set of stacks with the second set of source/drains having a second source/drain width. The method also includes forming a first set of top spacers between source/drains of the first set of source/drains and stacks of the first set of stacks. The method further includes forming a second set of top spacers between source/drains of the second set of source/drains and stacks of the second set of stacks. The method additionally includes forming a first set of gates between spacer elements of the first set of top spacers. The method also includes forming a second set of gates between spacer elements of the second set of top spacers. The first set of top spacers have a first spacer width and the second set of top spacers have a second spacer width, the first set of gates have a first gate width and the second set of gates have a second gate width. A first set of GAA structures, including the first set of source/drains, the first set of top spacers, and the first set of gates, is configured with a first threshold voltage. A second set of GAA structures, including the second set of source/drains, the second set of top spacers, and the second set of gates, is configured with a second threshold voltage. The first threshold voltage is different from the second threshold voltage based on the second source/drain width being different from the first source/drain width, the second spacer width being different from the first spacer width, and/or the second gate width being different from the first gate width.