Digitally controlled transconductance cell

A digitally controlled transconductance cell includes a differential transistor pair coupled to load elements (either passive or active with resistive or impedance loads) and a variable bias current source, where the transconductance or gain is digitally varied by changing the aspect ratio of the transistors and the bias current.

BACKGROUND

1. Field of the Invention

The present invention relates to electrical circuits, and in particular, to transconductance cells.

2. Related Art

As is known in the art, a transconductance cell is a basic electrical circuit or block used to build more complex electrical circuits, such as low noise amplifiers and analog filters. The transconductance cell performs the function of converting a voltage input into different current outputs, such as by varying the transconductance gmof the cell (iout=gm*vin) The characteristics of a desirable transconductance cell include high bandwidth, low power consumption, high output impedance, low distortion, and good common mode rejection. Furthermore, with an ever-increasing need and use of high speed analog circuits and chips, transconductance cells should be able to provide these characteristics at high speeds with wide linear dynamic range and low power dissipation.

FIG. 1Ashows a conventional transconductance cell100, in which transconductance gmis varied by varying the current. Transconductance cell100includes two transistors102and104, such as N-channel MOS transistors, resistive or impedance load elements106and108connected between the drain of transistors102and104, respectively, and a voltage source110, and a variable current source112connected between the source of both transistors102and104and ground. The transconductance is varied in such a cell by varying the amount of bias current generated by current source112, such as with a control signal, of the differential transconductance pair. This, however, changes the linearity and increases power dissipation. Furthermore, to increase the gain (where gain is equal to gm*RL(the load resistance)) by m, the drain current IDneeds to be increased by a factor of m2. The large increase in the drain current results in a large overhead in power dissipation. The voltage headroom (Vds, viz. drain to source voltage of a MOS transistor) is also lowered and the variation in linearity is disadvantageously widened.

FIG. 1Bshows another conventional transconductance cell140, in which gain is changed by varying the load resistance. The structure of cell140is the same as cell100ofFIG. 1A, except that load elements106and108are variable and current source112is constant. The load resistance of load elements106and108can be changed by varying characteristics of the components forming load elements106. For example, load elements106may include an inductor and resistor in series (for a load impedance). The load impedance can then be changed by varying the resistance of the resistor and/or the inductance of the inductor. However, such a transconductance cell has limited gain controllability at higher speeds, e.g., in the multi-GHz range. Further, if the gain is to be increased, e.g., by a factor of m, the load resistance RLmust be increased by m. This reduces the bandwidth BW of the device by m, since BW is proportional to 1/RL(more specifically, BW=1/(2πRLCL), where CLis the load capacitance).

FIG. 1Cshows a third kind of transconductance cell180that uses source degeneration to maintain a constant transconductance gmfor the device. Cell180includes two transistors102and104coupled together at the respective sources by two resistors182and184in series. Current sources186and188are coupled to the respective sources of transistors102and104. When the gate voltage is changed, the saturation current changes, with some of the current flowing through the resistors. This causes the source voltage to increase, which reduces the original increase in the saturation current caused by the increase in the gate voltage. The transconductance is reduced from its value with the source voltage held constant. Mathematically, the effective gmfor this structure can be shown to be as follows:gmeff=gm1+gm⁢Rs
where Rsis the source degeneration resistance associated with resistors182and184, which is varied to get variable transconductance. Hence, in this type of cell, the resistances associated with resistors182and184can be shown to be varying. However, such cells180can only be used at low speeds, since the effective lowering of the inherent gmreduces the transit frequency (Ft) of the device.

Accordingly, there is a need for a transconductance cell that provides variable transconductance at low power dissipation, while maintaining high bandwidth and linearity.

SUMMARY

According to one aspect of the present invention, both the aspect ratio of transistors and the current source are varied together to change the transconductance or gain of a transconductance cell. A constant ratio is maintained, where the ratio is the ratio of the current and the transistor size or aspect ratio [I/(W/L)]. This ratio determines the gate-to-source overdrive voltage of the device, i.e., ΔV=(Vgs−Vth), which determines the linearity of the device. Accordingly, the ratio can be determined based on the linearity requirement so that the linearity is not affected (since the gate-source overdrive voltage for the transistors does not change). In one embodiment, the cell is formed with a differential transistor pair, wherein each drain is coupled to a resistive load and each source is coupled to a common variable bias current source. In one embodiment, the width of the device is changed to vary the aspect ratio. Changing the aspect ratio and bias current can be achieved by digitally switching on/off MOS device fingers both in the input differential pair as well as in the tail current source.

The transconductance cell can be utilized in a gain circuit with multiple transconductance stages. In different embodiments, each stage uses different combinations of variable bias current sources and differential input signals. In one embodiment, each stage uses the same variable bias current and same differential input signals, thereby allowing the circuit to provide high speed gain controllability while maintaining linearity. In another embodiment, each stage uses separate variable bias currents with the same differential input signals, which provides the circuit another degree of freedom in gain, bandwidth, and linearity control. In other embodiments, each stage uses different differential input signals, either with separate or same variable bias currents, which enables switching, summation, subtraction or multiplication at high speeds while maintaining bandwidth and linearity. Such circuits may also be used as linear interpolators, switchable delay cells, and continuous delay interpolators due to a linear relation between two different input signals.

In yet another embodiment, each transconductance stage uses the same input signals, but different outputs, taken at the drains of the differential transistor pair, allowing demultiplexing at higher speeds.

Digitally switched transconductance using cells of the present invention can also be applied to a multiplier circuit, where different differential input signals or voltages are can multiplied by different gains with high gain controllability and linearity at high speeds.

The transconductance cell of the present invention can achieve programmable transconductance, while maintaining high bandwidth, linearity, and voltage headroom at low power dissipation. It can be used to achieve many analog functionalities like constant and variable gain control, variable and constant gmcontrol, multiplexing/demultiplexing, summation, subtraction, multiplication, linear combination and delay interpolation, all at high speeds (e.g., multi-GHz bandwidth) and low voltage supply with wide linear dynamic range.

This invention will be more fully understood in conjunction with the following detailed description taken together with the following drawings.

Use of the same or similar reference numbers in different figures indicates same or like elements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

According to one aspect of the invention, a transconductance cell includes two variable sized transistors, a variable bias current source coupled to the sources of the two transistors, and two resistive load elements coupled to respective drains of the two transistors. The transconductance gmof the cell is varied by changing the size (or aspect ratio) of the transistors and the bias current. In one embodiment, the load elements may also be variable.

FIG. 2shows a transconductance cell200according to one embodiment of the present invention.

Transconductance cell200is formed with two transistors202and204, such as N-channel MOS transistors (as shown) or P-channel MOS transistors. The drain of transistors202and204are each coupled to one terminal of a load element206and208, with the other terminal coupled to a voltage source Vs. Load elements206and208may be any suitable load having a resistance RLor impedance ZL, as will be discussed below. The load may also be comprised of active elements, such as, but not limited to, diode-connected PMOS loads and active inductors. The source of each transistor202and204is coupled to a variable current source210that provides a bias current. The transconductance gm of cell200can be varied by changing size or aspect ratio (W/L) of the transistors, where W is the width of the transistor and L is the length, and the bias current (which changes the drain current ID). High speed gain controllability can be achieved with cell200, as will be discussed below.

Large channel length approximation has been assumed for the MOS transistors to simplify the analysis, but the concepts are also valid for deep submicron MOS transistors. In the saturation region of operation, the transconductance gm is given below in equation (1):gm=2⁢ID⁢β⁢WL(1)
where IDis the drain current, W is the transistor width, L is the transistor length, and β is equal to μCox, where μ is the mobility and Coxis the capacitance associated with the gate oxide of the transistor. Varying the transconductance gmvaries the gain, since gain is equal to gmRL, where RLis the load resistance of load elements206and208. Note that load resistance RLcan also be an impedance ZL, depending on the components forming load elements206and208.

Thus, according to equation (1), the transconductance (or gain) can be varied by changing the drain current and the size (or aspect ratio W/L) of the transistors. In one embodiment, the width of the transistor is changed to vary the aspect ratio. The drain current is changed by varying the current of current source210, such as with a control signal. Variable current sources and methods of varying the current are well known and not discussed in detail herein. In some embodiments, digital bits are used to control the bias current and the aspect ratio. Using digital bits to control the bias current (i.e., the reference current that is coming in to get mirrored into the tail current sources) can be with any known conventional method. Varying the transistor size and current, according to equation (1), allows a system designer a wide range of transconductance gains for the cell. For example, if both IDand W/L (or W) is increased by a factor of m, then the gain is increased by a factor of m.

In addition to a wide range of gain adjustments, transconductance cell200allows highly linear operations. This can be shown by the gate overdrive voltage ΔV of the transistor, given below in equation (2):Δ⁢⁢V=2⁢IDβ⁢WL(2)
ΔV determines linearity of the differential transconductance pair. Linearity is maintained if the gate overdrive voltage is kept constant. So, if the drain current and width (or aspect ratio) are both changed by a factor of m (which changes the gain by a factor of m), ΔV remains unchanged. As a result, linearity is maintained.

The present invention provides significant advantages over conventional transconductance cells. For example, assume gain is increased by a factor of m. In the transconductance cell ofFIG. 1A, IDneeds to be increased by a factor of m2, which implies a huge overhead in power dissipation. The voltage headroom is also lowered (IRLdrop), as discussed above. However, with cell200of the present invention, the current only needs to increase by a factor of m (along with an increase in aspect ratio of m). This results in a lower power dissipation and a higher voltage headroom (the Vdsvoltage of the MOS devices in the transconductance pair) than the cell of FIG.1A. The gain variation of the transconductance cell of the present invention is also higher than that of the cell ofFIG. 1A, since the cell ofFIG. 1Auses only current variation to change gm(or gain). Consequently, gm(or gain) soon reaches a peak value and then decreases.

The present invention also provides a cell that has a higher bandwidth than conventional cells, such as cell140of FIG.1B. The bandwidth BW of a cell (a first order system is assumed for simplicity) is given below in equation (3):BW=12⁢π⁢⁢RL⁢CL(3)
where RLis the load resistance and CLis the load capacitance of the load elements. Assuming a cascaded system where a standard cell is driving itself, CL=Cg+Cp, where Cgis the gate capacitance of the device and Cpis the parasitic routing capacitance. In order to increase the transconductance or gain by a factor of m, RLneeds to be increased by a factor of m for cell140ofFIG. 1B, thereby reducing the bandwidth by the same factor, i.e., BW=1/(2πRLm(Cg+Cp)). However, with cell200of the present invention, the reduction of bandwidth will be less, i.e., BW=1/(2πRL(mCg+Cp)). At higher speeds, when parasitics increase significantly, the increased difference in bandwidth will be even more pronounced. Moreover, unlike the present invention, resistor variation (whether achieved by digital switching or by active device tuning) has a substantial amount of parasitic cap, which further lowers the bandwidth.

The transconductance cell of the present invention can be used in many types of circuits to provide various benefits over circuits utilizing conventional cells. For example, the cell can be used to form a plurality of transconductance stages for use in a gain stage or stages of an AGC core. Each gain stage may receive control fine and coarse control signals to provide fine and coarse gain control within the particular gain stage.

FIG. 3shows an N-stage transconductance circuit300that uses the same bias currents and same input for each of the N stages according to one embodiment of the invention. Circuit300includes a number of digitally-switched transconductance (gm) stages302(e.g., stages302(1),302(2), . . . ,302(N), where N corresponds to the number of desired stages and also the number of bits required from a control signal304for coarse gain control. Each stage302uses the same bias current from a variable current source308and the same differential input signals312.

Each stage302includes a pair of complementary switches310(e.g., switches310(1a) and310(1b),310(2a) and310(2b), through310(Na) and310(Nb) corresponding to stage302(1), stage302(2), through stage302(N), respectively), which provide coarse control gain for circuit300. Control signal304, which includes N bits or bits, provides coarse gain control by controlling switches310within circuit300. For example, if a first bit of control signal304, corresponding to stage302, is asserted, then switch310(1a) is closed and switch310(1b) is opened so that stage302(1) provides its gain to an input signal312. If the first bit of control signal304is deasserted, then switch310(1a) is opened and switch310(1b) is closed so that stage302(1) does not provide its gain to input signal312. Similarly, a second bit through to the last bit (N-bit) of control signal304controls corresponding switches310(2a,2b) to310(Na, Nb) of corresponding stages302(2) to302(m) to provide the desired coarse gain for an output signal320. Output signal320may represent the output signal for the AGC core or an input signal to the next gain stage.

A fine gain control signal314(fine gain control) controls variable current source308(e.g., a digitally-controlled current source) to control a bias current provided (e.g., mirrored) for each stage302to provide fine gain control to circuit300. The combination of coarse and fine gain control, with a variable bias current and transistor sizes, enables precise gain control to maintain an approximately constant gain linearity across a wide dynamic range for input signal312at high speeds (e.g., multi-GHz).

FIG. 4shows an N-stage transconductance circuit400that uses the same input signals, but different bias current sources according to one embodiment. Each stage402of circuit400includes a variable current source408-1to408-N, with each current source408controlled by a separate control signal414-1to414-N, respectively. The differential input signal is the same for each stage. By using different bias currents, circuit400provides an additional degree of freedom for gain, bandwidth and linearity control.

FIG. 5shows an N-stage transconductance circuit500that uses the same variable bias current source, but different differential input signals according to another embodiment of the invention. The differential transistor pair of each stage502uses a separate input signal512-1to512-N. A single variable bias current source508is digitally controlled to provide the same bias current to each stage502.FIG. 6shows an N-stage transconductance circuit600similar to circuit500ofFIG. 5, except that each of N transconductance stages602uses a separate variable current source608-1to608-N. Both circuits use different differential input signals in1, in2, . . . , inN for each of the N transconductance stages.

With circuits500and600, digitally switched transconductance can enable switching, summation, subtraction, or multiplexing, all at high speed maintaining bandwidth and linearity. Such circuits can also be used as linear interpolaters, since essentially, the differential output signal out=r1*in1+r2*in2, where r1and r2are the respective gains of two transconductance stages (e.g., the first and second stage),and in1and in2are the respective differential input signals of the two stages. For example, if one of the input signals is a delayed version of the other, e.g., in2(t)=in1(t−T), the circuit can be used as a switchable delay-cell and/or a continuous delay interpolator by varying the currents in addition.

FIG. 7shows an N-stage transconductance circuit700that uses the same input differential signal, but different outputs and variable bias current sources at each stage702. Each output signal out1, out2, . . . , outN is taken at the drain of each differential transistor pair. Circuit700, with digitally switched transconductance, enables demultiplexing at much higher speed compared to conventional switching which lowers the bandwidth dramatically.

FIG. 8shows another embodiment of an N-stage transconductance circuit800, where the digitally switched transconductance described above is applied to a multiplier topology. In this example, the multiplier topology is a Gilbert cell multiplier, which uses the transconductance cell of the present invention for enabling gain controllability for the multiplier. Gilbert cell multipliers or mixers are known in the art, such as described in U.S. Pat. No. 5,847,623, entitled “Low noise Gilbert Multiplier Cells and quadrature modulators”, which is incorporated by reference in its entirety. The variable bias current is the same for each stage. However, each stage has two separate input differential signals. Circuit800can be used to achieve gain controllability without sacrificing bandwidth and linearity in a high speed amplifier circuit.

In the above embodiments, the number of stages N depends, in part, on how much variability is required in the gain. For example, one implementation can be three stages with 1×, 2×, and 4× fingers (binary weighted), respectively, in both the differential pairs as well as the corresponding tail current sources. That way one can obtain 1×to 7× variation of gain without sacrificing linear dynamic range.

Other circuits in which the transconductance cell of the present invention can be used can be found in commonly-owned U.S. patent application Ser. No. 10/724,444, entitled “Method and Apparatus for Automatic Gain Control”, filed Nov. 26, 2003, and U.S. patent application Ser. No. 10/724,561 entitled “Analog Signal Interpolation”, filed Nov. 26, 2003, both of which are incorporated herein by reference in their entirety.

As discussed above, transconductance or gain is changed by varying the bias current and transistor size (e.g., width). However, as discussed above, the gain is equal to the transconductance gmmultiplied by the load resistance or impedance. Therefore, the gain can also be changed by varying the load resistance or impedance for a particular circuit or application.

FIGS. 9A-9Gshow different circuits for load elements206and208ofFIG. 2in accordance with an embodiment of the present invention.FIG. 9Ashows a shunt (or shunt-peaked) load configuration900for load elements206and208having a resistor R in series with an inductor L. Also shown in FIG.9A and the followingFIGS. 9B through 9Gare the coupling relationships of an output signal902relative to the exemplary implementations of load elements206and208.FIGS. 9A-9Galso show a transistor904, such as an NMOS transistor, coupled to load element900via the drain of the transistor and an input signal906to the gate of transistor904.

FIGS. 9B and 9Cshow a shunt-series and a series-shunt load configuration, respectively, for load element900having inductors L1and L2coupled to resistor R.FIG. 9Dillustrates a series-shunt-series load configuration for load element900having inductors L1, L2, and L3coupled to resistor R as shown.FIGS. 9E and 9Fillustrate a T-coil and a T-coil with cross-coupled capacitor C load configuration, respectively, for load element900having inductors L1and L2with associated magnetic coupling factor k.FIG. 9Gillustrates a series-T-coil load configuration for load element900having resistor R, cross-coupled capacitor C, inductor L3, and inductors L1and L2with associated magnetic coupling factor k.

In general, different types of broad-banding loads can be utilized for bandwidth extension per design requirements or desired application. The transconductance stages in combination with broad-band loads enables wide linear dynamic range with high bandwidth (e.g., multi-gigahertz). The transconductance circuits described herein also include load impedances, which may be optimized through appropriate broad-banding techniques to further enhance the bandwidth. Note, however, that the load impedances or resistances do not need to be varied or changed on-the-fly. Only the bias current and transistor size are changed for gain variation, although the load may be changed depending on the application, such as based on bandwidth requirements or limitations.

The above-described embodiments of the present invention are merely meant to be illustrative and not limiting. It will thus be obvious to those skilled in the art that various changes and modifications may be made without departing from this invention in its broader aspects. For example, the differential transistor pairs have been shown as NMOS transistors; however, PMOS transistors can also be used, with corresponding changes in the circuitry and control signals, as is known in the art. Therefore, the appended claims encompass all such changes and modifications as fall within the true spirit and scope of this invention.