Covered devices in a semiconductor package

An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base plate. The sidewalls have a height. A plurality of devices is attached to underside of the base plate. The devices have length corresponding to the height such that the devices are sealed within the cover when the cover is attached to a surface.

BACKGROUND

1. Field of the Invention

Embodiments of the invention relate to the field of semiconductor, and more specifically, to semiconductor packaging.

2. Description of Related Art

In semiconductor packages, devices performing specific functions may be included in the packages. Examples of these devices may include thin film (TF) thermo-electric coolers (TECs) or sensors. The TFTECs are solid state cooling devices that offer higher cooling density, smaller form factor, and higher reliability than traditional bulk thermo-electric coolers. By matching the cooling density of the TFTEC to the size and the power density of the heat-generating source, cooling losses and overall power efficiencies may be increased. Due to superior performance, TFTECs are used on semiconductor dice to improve the thermal management performance in semiconductor packages.

Existing techniques to assemble TFTECs on dice have a number of disadvantages. A typical process first deposits an insulation layer on the die. Then, an interconnect pattern is placed on the insulation layer. The elements of the TFTEC are next soldered individually onto the interconnect pattern. The region around and between the TFTEC elements is then filled with an underfill or sealant to prevent the thermal interface material (TIM) from penetrating between the elements. The process is complex, requiring several steps. In addition, the use of the underfill or sealant may diminish the TFTEC cooling performance.

DESCRIPTION

An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base plate. The sidewalls have a height. A plurality of devices is attached to underside of the base plate. The devices have length corresponding to the height such that the devices are sealed within the cover when the cover is attached to a surface.

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown to avoid obscuring the understanding of this description.

One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a program, a procedure, a method of manufacturing or fabrication, etc.

An embodiment of the present invention is a technique to provide a cover assembly for devices on semiconductor packages. The devices may be thin film thermoelectric coolers (TFTECs). The TFTECs are enclosed in a cover or an enclosure. The individual TFTECs are assembled and attached to the underside of the cover. The cover assembly may then be attached to back side of a die or the underside of an integrated heat spreader (IHS). The cover assembly may be attached to the electrical interconnect pattern on the backside of the die or the underside of the IHS using a process similar to the flip-chip process. The cover assembly may be placed near hotspots of the die to cool the die efficiently. Since the entire TFTECs are sealed inside the cover, it is not necessary to use underfill or sealant between the elements of the TFTECs. In addition, the electrical insulation covering the elements of the TFTECs is not needed because the cover or enclosure provides the required insulation. The cover assembly having the TFTECs may be assembled inside the IHS at the IHS supplier. During the IHS manufacturing process, the electrical insulation and metal interconnect layers may be placed on the IHS. Then, the IHS with the cover assembly may be shipped to the semiconductor manufacturer for packaging. The cover assembly may also be attached to the die during the die fabrication process. The covered TFTECs may be positioned on strategic locations on the metal interconnect pattern on the backside of the die using a pick-and-place process. In either case, the complete cover assembly with the TFTECs is available as a single part ready to be attached to the die or the IHS. The solder TIM attachment is simplified because there is only one single cover assembly rather than individual TFTECs. This may reduce the potential for trapped air creating the solder TIM voids during the TIM soldering process.

Although the technique is described with the TFTEC, it is contemplated that any other devices with similar characteristics may be used. For example, devices such as pressure sensors, humidity sensors, etc. that may be used in multiple units may be attached to a cover or enclosure so that the multiple devices may be attached as a single unit to the backside of the die or the underside of the IHS.

FIG. 1Ais a diagram illustrating a manufacturing system10in which one embodiment of the invention can be practiced. The system10includes a wafer fabrication phase15, wafer preparation phase20, a wafer dicing phase25, a die attachment phase30, an encapsulation phase40, and a stress testing phase50. The system10represents a manufacturing flow of a semiconductor packaging process.

The wafer fabrication phase15fabricates the wafer containing a number of dice. The individual dice may be any microelectronic devices such as microprocessors, memory devices, interface circuits, etc. Each die may have a cover assembly having multiple devices (e.g., TFTECs) or multiple cover assemblies mounted on its back side. The wafer fabrication phase15includes typical processes for semiconductor fabrication such as preparation of the wafer surface, growth of silicon dioxide (SiO2), patterning and subsequent implantation or diffusion of dopants to obtain the desired electrical properties, growth or deposition of a gate dielectric, and growth or deposition of insulating materials, depositing layers of metal and insulating material and etching it into the desired patterns. Typically the metal layers consist of aluminium or copper. The various metal layers are interconnected by etching holes, called “vias,” in the insulating material. During this phase, the cover assembly may be strategically mounted on each die together with the fabrication process for the circuit of the device.

The wafer preparation phase20prepares a wafer containing dice for packaging and testing. During this phase, the wafers are sorted after the patterning process. An inspection may be carried out to check for wafer defects. Then, the wafer may be mounted on a backing tape that adheres to the back of the wafer. The mounting tape provides mechanical support for handling during subsequent phases.

The wafer dicing phase25dices, cuts, or saws the wafer into individual dice. High precision saw blade and image recognition unit may be used. De-ionized water may be dispensed on the wafer to wash away any residual particles or contaminants during the dicing. Then, the wafer is dried by being spun at high spinning speed.

The die attachment phase30attaches the die to a package substrate. The substrate material depends on the packaging type. It may be lead-frame, plastic, or epoxy.

The encapsulation phase40encapsulates the die and the substrate. Depending on the packaging type, this may include molding, wire bonding, and solder ball attachment. Underfill material may be dispensed between the die and the substrate. Integrated heat spreader (IHS) may be attached to the die and substrate assembly. The encapsulated assembly of the die and substrate becomes a device package65ready to be tested. During this phase, a cover assembly may be mounted on, or attached to, the cavity side, or the underside, of the IHS.

The stress testing phase50performs one or more tests such as Highly Accelerated Stress Test (HAST) or biased-HAST on the device package under stress conditions. A test chamber60may be designed to conduct a stress test. It may have monitoring circuits, measurement circuits, and other data processing equipment. The package65is placed in the test chamber60subject to the stress test. It may be powered or non-powered. Various stress tests may be performed on the wafer or on the packaged devices65at various points of the manufacturing process flow. The tests may follow standards such as Joint Electron Device Engineering Council (JEDEC) standards or military standards. Examples of these tests may include electrostatic discharge (ESD), or human body model (HBM), high temperature operational life (HTOL), thermal shock, temperature cycle, high temperature storage, vibration and mechanical loading, shear testing, and accelerated moisture resistance.

FIG. 1Bis a diagram illustrating a system100according to one embodiment of the invention. The system100represents a mobile communication module. It includes a system on package (SOP)110, an intermediate frequency processing unit160, and a base-band processing unit170.

The SOP110represents the front end processing unit for the mobile communication module. It is a transceiver incorporating on-package integrated lumped passive components as well as radio frequency (RF) components. It includes an antenna115, a duplexer120, a filter125, a system-on-chip (SOC)150, a power amplifier (PA)180, and a filter185.

The antenna115receives and transmits RF signals. The RF signals may be converted to digital data for processing in subsequent stages. It is designed in compact micro-strip and strip-line for L and C-band wireless applications. The duplexer120acts as a switch to couple to the antenna115to the receiver and the transmitter to the antenna115. The filters125and185are C-band LTCC-strip-line filter or multilayer organic lumped-element filter at 5.2 GHz and narrowband performance of 200 MHz suitable for the Institute of Electrical and Electronic Engineers (IEEE) 802.11 wireless local area network (WLAN). The SOC150includes a low noise amplifier (LNA)130, a down converter135, a local voltage controlled oscillator (VCO)140, an up converter170, and a driver amplifier175. The LNA130amplifies the received signal. The down converter135is a mixer to convert the RF signal to the IF band to be processed by the IF processing unit160. The up converter170is a mixer to convert the IF signal to the proper RF signal for transmission. The VCO140generates modulation signal at appropriate frequencies for down conversion and up conversion. The driver amplifier175drives the PA180. The PA180amplifies the transmit signal for transmission.

The IF processing unit160includes analog components to process IF signals for receiving and transmission. It may include a band-pass filter and a low pass filter at suitable frequency bands. The filter may provide base-band signal to the base-band processing unit170. The base-band processing unit170may include an analog-to-digital converter (ADC)172, a digital-to-analog converter (DAC)174, and a digital signal processor (DSP)176. The ADC172and the DAC174are used to convert analog signals to digital data and digital data to analog signal, respectively. The DSP176is a programmable processor that may execute a program to process the digital data. The DSP176may be packaged using Flip-Chip Ball Grid Array (FCBGA) packaging technology or any other suitable packaging technologies. The DSP176may be manufactured according to the manufacturing flow10shown inFIG. 1A. It may be the device package65. The base-band processing unit170may also include memory and peripheral components. The DSP176may, therefore, be coupled to the front end processing unit via the IF processing unit160and/or the base-band processing unit170to process the digital data.

The SOP110may be a multi-layer three-dimensional (3D) architecture for a monolithic microwave integrated circuit (MMIC) with embedded passives (EP) technology. It may be implemented using Low Temperature Co-fired Ceramics (LTCC) and organic-based technologies. The 3D architecture may include multiple layers include a layer117to implement the antenna115, layers122,124, and186for the filters125and185, and layer188for the SOC150and the passive components using EP technology. Typically, the packaging technology involves embedded passives with multiple layers.

FIG. 2Ais a diagram illustrating the package device65or176shown inFIG. 1AandFIG. 1B, respectively, having a cover assembly attached to the die according to one embodiment of the invention. The package device65/176includes a substrate210, a die220, an underfill230, an integral heat spreader (IHS)250, and a cover assembly260.

The substrate210is a package substrate that provides support for the die220. The substrate210may be polymer or a composite. The substrate210may be selected for any suitable packaging technologies including Ball Grid Array (BGA), Pin Grid Array (PGA), or Land Grid Array (LGA). The substrate210may be attached to a number of solder balls215. The solder balls215allow attachment of the package device165to a circuit board or to any other mounting component. The die220is any semiconductor die. It may have a microelectronic device such as a microprocessor, a memory, an interface chip, an integrated circuit, etc. The die220is attached to the substrate110by a number of solder bumps225. The bumps225provide contact with the contact pads on the substrate. The bumps225may be fabricated using any standard manufacturing or fabrication techniques such as the controlled collapse chip connect (C4) technique. The underfill230is dispensed between die220and the substrate210to strengthen the attachment of die220to the substrate210to help prevent the thermal stresses from breaking the connections between die220and the substrate210. The stresses may be caused by the difference between the coefficients of thermal expansion of die220and the substrate210. The underfill230may contain filler particles suspended in an organic resin. The size of the filler particles are typically selected according to a gap between the die220and the substrate210, e.g., the filler particles have a diameter about one third the size of the gap. Generally, the composition and concentration of filler particles are selected to control the coefficient of thermal expansion and the shrinkage of the underfill230.

The IHS250may house or cover the die220on the substrate210. It may include a flat surface and supporting walls on both or four sides of the die220. During operation, the die220may generate heat. The heat may be transferred to the IHS250through a thermal interface material (TIM)240. The TIM240may be located, or interposed, between the bottom surface of the IHS250and the top surface of the die220to encapsulate the cover assembly260. It may be attached to a heat generating device, such as the die220, to transfer the heat to a heat spreader or a heat sink or any another heat dissipating device. The TIM240may be made of thermal grease, phase change material (PCM), pads, films, and gels, or any thermally conducting material such as Sn solder, or alloys, or a combination of such materials, which also show good adhesion (e.g., wetting) with the IHS250and the die220.

The cover assembly260includes a cover and a number of devices (e.g., TFTECs). The TFTEC may be a solid state heat pump that operates on the Peltier effect. The TFTEC may include an array of p- and n-type semiconductor elements that act as two dissimilar conductors. The array of elements is connected between two metal interconnects, and may be connected in series and/or in parallel. As a direct current (DC) current passes through one or more pairs of elements from n- to p-, there is a decrease in temperature at the junction, resulting in the absorption of heat from the environment, e.g., from the die220. The heat is carried through the TFTEC by electron transport and released on the opposite side as the electrons move from a high to low energy state. The cover assembly260is attached to the die via an interconnect pattern on the backside of the die. It receives power from the power contacts in the substrate210.

FIG. 2Bis a diagram illustrating the package device65or176shown inFIG. 1AandFIG. 1B, respectively, having a cover assembly attached to the underside of the IHS according to one embodiment of the invention. The package device65/176includes the substrate210, the die220, the underfill230, the integral heat spreader (IHS)250, and the cover assembly260as inFIG. 2A.

The substrate210, the die220, the underfill230, the integral heat spreader (IHS)250, and the cover assembly260are the same as described inFIG. 2A. The difference is that the cover assembly260is attached to the IHS250via an interconnect pattern on the underside or the cavity of the IHS250. The attachment of the cover assembly260may be performed at the IHS manufacturing facility. In addition, when the devices are TFTECs, the arrangement of the TFTECs in the cover assembly260may be reversed as explained inFIGS. 5A and 5B.

FIG. 3is a diagram illustrating the cross section of the cover assembly260and its attachment to the die or the IHS according to one embodiment of the invention. The cover assembly260includes a cover310and a number of devices326.

The cover310has a base plate322and sidewalls324attached to perimeter of the base plate322. The sidewalls have a height H. Depending on the application, the base plate322and the sidewalls324may be made of the same material or different materials. When the devices326are the TFTECs, the base plate322is made of a thermally conductive material while the sidewalls324may be made of a different material. The thermally conductive material may be metal such as copper to allow efficient heat transfer.

The devices326are attached to the underside of the surface322which is internal to the cover. The devices have a length L corresponding to the height H of the sidewalls such that the entire devices326are completely sealed or enclosed inside the cover310when the cover310is attached to a surface such as the backside of the die or the underside of the IHS. When the devices are the TFTECs, they are attached to the underside of the base plate322though an electrical insulator layer340. The individual TFTECs may have a device interconnect layer340to electrically connect them in groups such as in pairs. The individual TFTECs may be separated by a gap G. Since the cover310encloses the entire TFTECs in a sealed environment when it is attached to the die or the IHS, there is no need to fill the gap G with underfill or sealant.

The cover assembly260is attached to the backside of the die or the underside of the IHS as a single unit. This attachment process is therefore much simpler and more efficient than attaching individual devices326. On the surface of the backside of the die or the underside of the IHS, there is an insulation layer355and an interconnect pattern350. The interconnect pattern350is placed on the surface of the backside of the die or the underside of the IHS on the insulation layer355to correspond to the positions of the devices326. When the interconnect pattern350is on the backside of the die, its location is selected to correspond to the hotspots of the die. The interconnect pattern350may have leads that are plated or sputtered and pass through the edge of the cover to provide power to the devices326. In addition, there are attachment lands360around the interconnect pattern350. These attachment lands360correspond to the sidewalls324.

When the cover assembly260is attached to the backside of the die or the underside of the IHS, the devices are attached or soldered to the interconnect pattern350and the sidewalls324are attached to the attachment lands360. A layer of solder or attachment material370is deposited on the interconnect pattern350. In addition, an attachment material365, such as solder, epoxy or glue sealant, is dispensed on the attachment lands360. The attachment process may be performed using the flip-chip process. The height H of the sidewalls is selected such that when the cover assembly is attached to the die or the IHS, the entire set of devices326are completely sealed within the cover310. The height H is selected such that the total height of the sidewalls324and the attachment lands360is approximately equal to the length L of the devices and the height of the interconnect pattern350.

FIG. 4is a diagram illustrating the cover310in the cover assembly according to one embodiment of the invention. The cover310may have any desired shape that matches to the desired geometry of the placement of the devices. The shape of the cover310may be circular, square, rectangular, hexagonal, or any other shape that may accommodate the proper placement of the devices.

FIG. 4shows the cover310without the devices in a rectangular shape. As shown, there are four sidewalls324attached to the perimeter of the base plate322. The base plate322may be a thin plate of a first material. For TFTECs, the first material is a thermally conductive material such as copper. The sidewalls324may be made of a second material different from the first material. The sidewalls324have the height H selected to provide complete sealing of the devices when the cover310is attached to the backside of the die or the underside of the IHS.

FIG. 5Ais a diagram illustrating an arrangement of the TFTECs in the cover when attached to backside of a die according to one embodiment of the invention.

As discussed above, the TFTEC326may include an array of p- and n-type semiconductor elements that act as two dissimilar conductors. The TFTEC326has a TEC core510, a cool side520, and a hot side530. The TFTEC326, when energized, operates to transfer the heat generated from the die to the cool side520and then out to the hot side530.

When the TFTECs326are attached to the backside of the die as shown inFIG. 5A, the cool side520is attached to the interconnect pattern350on the backside of the die and the hot side530is attached to the underside of the base plate322of the cover310.

FIG. 5Bis a diagram illustrating an arrangement of the TFTECs in the cover when attached to underside of an IHS according to one embodiment of the invention.

When the cover assembly260is attached to the underside of the IHS, it is turned upside down compared to when it is attached to the backside of the die. Therefore, the TFTECs are also attached in reverse. The cool side520is attached to the underside of the base plate322of the cover310and the hot side530is attached to the interconnect pattern350on the underside of the IHS.

In either case, the heat flows from the die, into the cool side520of the TEC elements, out of the hot side530of the TEC elements and finally into the IHS.

FIG. 6is a flowchart illustrating a process600to fabricate a cover assembly according to one embodiment of the invention.

Upon START, the process600forms a cover having a base plate and sidewalls attached to perimeter of the base plate (Block610). The sidewalls have a height. Then, the process500attaches a number of devices to the underside of the base plate (Block620). The devices have length corresponding to the height such that the devices are enclosed or sealed within the cover when the cover is attached to a surface.

Next, the process600attaches the cover to the backside of a die or to the underside of an integrated heat spreader (IHS) (Block630). The attachment process may be similar to the flip-chip attachment process. The attachment is such that the devices are completely sealed within the cover. The process600is then terminated.

FIG. 7is a flowchart illustrating a process630to attach the cover assembly according to one embodiment of the invention

Upon START, the process630deposits an insulation layer and an interconnect pattern on the backside of the die or on the underside of the IHS (Block710). The interconnect pattern corresponds to position of the devices. For thermal applications, the devices may be the TFTECs and the interconnect pattern is placed at a hotspot or hotspots of the backside of the die or a strategic location on the underside of the IHS. Leads may be plated or sputtered and pass under the edge of the cover to provide power to the devices.

Next, the process630deposits or dispenses attachment material on attachment lands around the interconnect pattern to correspond to the sidewalls (Block720). The attachment material may be solder, epoxy, or glue sealant.

Then, the process630attaches the devices to the interconnect pattern (Block730) using a layer of solder dispensed on the interconnect pattern. Next, the process630attaches the sidewalls of the cover to the attachment lands (Block740). The process630is then terminated.

Embodiments of the invention have been described with a cover assembly having a number of devices. For thermal applications, the devices may be TFTECs. Any external devices other than TFTECs may be attached to the surface of the cover such as a moisture sensor, pressure sensor, etc.