Thin film transistor array panel

A thin film transistor array panel includes a gate line and the driver connection line formed with the same layer material, a data line and a driving pad formed with the same layer material, a first field generating electrode and a connecting member formed with the same layer material, and a second field generating electrode and a dummy electrode layer formed with the same layer material.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 10-2011-0095209, filed on Sep. 21, 2011, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

Exemplary embodiments of the present invention relate to a thin film transistor array panel.

2. Discussion of the Background

Among display panels, a liquid crystal display (“LCD”) is one type of flat panel display that is currently being widely used, and includes two display panels in which field generating electrodes, such as a pixel electrode and a common electrode, etc., are formed, and a liquid crystal layer is disposed therebetween. The LCD displays images by applying voltages to the field-generating electrodes to generate an electric field in the liquid crystal (“LC”) layer that determines the orientations of LC molecules therein to adjust the polarization of incident light. In the liquid crystal display, the pixel electrode and the common electrode generating an electric field to the liquid crystal layer may be formed on a thin film transistor array panel.

On the other hand, a chip-on-glass type directly mounting a data driving circuit to apply a data voltage to the field generating electrode of the liquid crystal display on the thin film transistor array panel has been proposed. When directly mounting the data driving circuit on the thin film transistor array panel through the chip-on-glass type, a driver connection line to connect a data pad unit of a data line and the data driving circuit may be formed of a gate wire or a data wire.

When forming the driver connection line of the gate wire, the driver connection line may be narrowly formed such that an area of a non-display area may be reduced. However, a thickness of a layer formed on the gate wire is correspondingly increased such that the connection with the driving circuit chip becomes difficult. Also, when forming the driver connection line of the data wire, the thickness of the layer formed on the data wire is small such that the connection with the driving circuit chip is easy. However, it is difficult to narrowly form the driver connection line such that the area of the non-display area is increased. However, a contact hole exposing the driver connection line is covered only by a connecting member made of a transparent conductor, and is therefore subject to corrosion.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a thin film transistor array panel including a driver connection line for easy connection with a driving circuit chip while reducing an area of a non-display area of the chip.

An exemplary embodiment of the invention discloses a thin film transistor array panel including: a substrate having a display area and a peripheral area of the display area; a gate line disposed in the display area of the substrate; a driver connection line disposed in the peripheral area of the substrate; a gate insulating layer disposed on the gate line and the driver connection line; a data line disposed on the gate insulating layer and disposed in the display area of the substrate; a driving pad disposed on the gate insulating layer and disposed in the peripheral area of the substrate; a first insulating layer disposed on the data line and the driving pad; a first field generating electrode disposed on the first insulating layer and disposed in the display area of the substrate; a connecting member disposed on the first insulating layer and disposed in the peripheral area of the substrate; a second insulating layer disposed on the first field generating electrode and the connecting member; a second field generating electrode disposed on the second insulating layer and disposed in the display area of the substrate; and a dummy electrode layer disposed on the second insulating layer and disposed in the peripheral area of the substrate. The gate line and the driver connection line are formed of the same layer material, the data line and the driving pad are formed of the same layer material, the first field generating electrode and the connecting member are formed of the same layer material, and the second field generating electrode and the dummy electrode layer are formed of the same layer material.

The first insulating layer and the second insulating layer have a first contact hole exposing the driving pad, the gate insulating layer, the first insulating layer, and the second insulating layer have a second contact hole exposing the driver connection line, and the connecting member covers the first contact hole and the second contact hole.

A portion of the second insulating layer and the dummy electrode layer may be disposed on the second contact hole.

A bump may be disposed on the first contact hole.

A portion of the driver connection line may be disposed under the driving pad and they overlap each other.

The first insulating layer may include an organic insulator and a surface thereof is flat.

One of the first field generating electrode and the second field generating electrode may have a plate shape, and the other may include a branch electrode.

An exemplary embodiment of the present invention also discloses a thin film transistor array panel including: a substrate having a display area and a peripheral area of the display area; a gate line disposed in the display area of the substrate; a driver connection line disposed in the peripheral area of the substrate; a gate insulating layer disposed on the gate line and the driver connection line; a data line disposed on the gate insulating layer and disposed in the display area of the substrate; a plurality of driving pads disposed on the gate insulating layer in the peripheral area of the substrate; a first insulating layer disposed on the data line and the driving pad; a second insulating layer disposed on the first insulating layer in the display area of the substrate; a first field generating electrode disposed on the second insulating layer in the display area of the substrate; a third insulating layer disposed on the substrate on the first field generating electrode; a second field generating electrode disposed on the third insulating layer in the display area of the substrate; and a first connecting member disposed on the third insulating layer and covering the plurality of driving pads. The gate line and the driver connection lines are formed with the same layer material, the data line and the driving pad are formed with the same layer material, and the second field generating electrode and the first connecting member are formed with the same layer material.

An output line respectively extending from a plurality of driving pads may be further included, the first insulating layer and the third insulating layer may have a first contact hole exposing the driving pad and a second contact hole exposing the output line, the gate insulating layer, the first insulating layer, and the second insulating layer may have a third contact hole exposing the driver connection lines, and a second connecting member covering the second contact hole and the third contact hole may be further included, wherein the second connecting member may be formed with the same layer as the second field generating electrode.

Among a plurality of driving pads, two neighboring driving pads may be separated from each other in a vertical direction.

Among a plurality of driving pads, the output line may be disposed between two adjacent driving pads disposed on the same line in the horizontal direction.

A bump may be disposed on the first contact hole.

A portion of the driver connection lines may be disposed to be overlapped by the driving pad.

The second insulating layer may include an organic insulator and has a flat surface.

The second insulating layer may not be disposed in the peripheral area.

As described above, the thin film transistor array panel according to an exemplary embodiment of the present invention forms the driver connection line with the gate wire such that the driver connection line may be narrowly formed and the area of the non-display area may be reduced, the connection along with the driving circuit chip is formed with a dual layer of the gate wire and the data wire such that the driving circuit chip may be stably connected, and the upper portion of the driver connection line is covered and protected by the interlayer insulating layer and two electrode layers that overlap to each other via the interlayer insulating layer such that the corrosion of the driver connection line exposed by the contact hole may be prevented

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. It will be understood that for the purposes of this disclosure, “at least one of X, Y, and Z” can be construed as X only, Y only, Z only, or any combination of two or more items X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ).

First, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference toFIG. 1.FIG. 1is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

Referring toFIG. 1, a thin film transistor array panel according to an exemplary embodiment of the present invention includes a plurality of pixels PX and includes a display area10to display images, a peripheral area20arranged at the periphery of the display area10, and a driving region30disposed near the peripheral area20. A driving circuit chip40is disposed in the driving region30, and a driver connection unit50which connects a signal line disposed in the display area10and the driving circuit chip40of the driving region30is disposed in the peripheral area20.

Referring to the enlarged view of a portion of the peripheral area20and the driving region30, a plurality of driver connection lines123are disposed in the driver connection unit50. A first driving input pad50aand a first driving output pad50bare disposed in the driving region30. An end of the driver connection line123forms the first driving input pad50a. A first driver contact hole181ais formed to expose the first driving output pad50b, and a second driver contact hole181bis formed to expose the first driving input pad50a. The first driving output pad50band the first driving input pad50athat are respectively exposed through the first driver contact hole181aand the second driver contact hole181bare connected by a connecting member91. The first driving output pad50bis connected to the driving circuit chip40through a bump (shown later).

If a driving signal is output from the driving circuit chip40to the first driving output pad50b, the output driving signal is transmitted to the first driving input pad50aconnected to the first driving output pad50bthrough the connecting member91. The driving signal input to the first driving input pad50ais transmitted through the driver connection line123, thereby being transmitted to the signal line of the pixel PX.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference toFIG. 4andFIG. 5as well asFIG. 2andFIG. 3.FIG. 2is a layout view of one pixel of a display area of a thin film transistor array panel according to an exemplary embodiment of the present invention, andFIG. 3is a cross-sectional view of the thin film transistor array panel taken along the line III-III ofFIG. 2.FIG. 4is a layout view of a portion of a peripheral area and a driving region of a thin film transistor array panel according to an exemplary embodiment of the present invention, andFIG. 5is a cross-sectional view of the thin film transistor array panel taken along the line V-V′ ofFIG. 4.

First, a display area of a thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference toFIG. 2andFIG. 3.

Referring toFIG. 2andFIG. 3, a plurality of gate conductors including a plurality of gate lines121and a plurality of common voltage lines125are formed on an insulation substrate110.

The gate lines121transmit gate signals and substantially extend in a transverse direction. Each gate line121includes a plurality of gate electrodes124.

The common voltage line125may transfer a predetermined voltage such as common voltage Vcom, may extend substantially in a transverse direction, and may be substantially parallel with the gate line121. Each common voltage line125may include a plurality of extensions126.

A gate insulating layer140is formed on the gate conductors121and125. The gate insulating layer140may be made of an inorganic insulating material, or the like, such as silicon nitride (SiNx), silicon oxide (SiOx), or the like.

A plurality of semiconductors151including a plurality of projections154are formed on the gate insulating layer140. Ohmic contacts161may be disposed on the semiconductors151, but the ohmic contacts may be omitted.

A data conductor including a plurality of data lines171and a plurality of drain electrodes175is formed on the ohmic contacts.

The data line171transmits data signals and substantially extends in a longitudinal direction to intersect the gate lines121and the common voltage lines125. Each data line171includes a plurality of source electrodes173extending toward the gate electrode124.

The drain electrode175includes a bar-type end facing the source electrode173with respect to the gate electrode124and the other end having a wide area.

The gate electrode124, the source electrode173, and the drain electrode175form a thin film transistor TFT as a switching element along with the exposed portions of the projections154of the semiconductor151. The semiconductor151may have substantially the same plane as the data line171and the drain electrode175except for the channel of the thin film transistor.

A first passivation layer180xis positioned on the data conductors171and175and the exposed portions of the projections154, and the first passivation layer180xmay be made of an organic insulating material or an inorganic insulating material.

A second passivation layer180yis positioned on the first passivation layer180x. The second passivation layer180yincludes an organic material and may be formed on the whole surface of the substrate110while covering the data lines171. The surface of the second passivation layer180ymay be substantially flat.

The first passivation layer180xand the second passivation layer180yhave a first contact hole181exposing a portion of the drain electrode175.

A plurality of pixel electrodes191are positioned on the second passivation layer180y. Each pixel electrode191may have a plane shape filling most of the region enclosed by the gate line121and the data line171. The entire shape of the pixel electrode191may be a polygon having edges substantially parallel to the gate line121and the data line171and both lower edges where the thin film transistor is positioned may be chamfered, however it is not limited thereto. The pixel electrode191may be made of a transparent conductive material such as ITO or IZO. The pixel electrode191receives a data voltage from the drain electrode175, which is connected to the pixel electrode191via the first contact hole181.

A third passivation layer180zis formed on the pixel electrode191. The third passivation layer180zmay be made of an inorganic insulator or an organic insulator. The third passivation layer180z, the second passivation layer180y, the first passivation layer180x, and the gate insulating layer140have a plurality of second contact holes182exposing a portion of the common voltage line125(e.g., a portion of the extension126).

A plurality of common electrodes131are formed on the third passivation layer180z. The common electrodes131may be made of the transparent conductive material such as ITO or IZO.

Each common electrode131includes a pair of longitudinal portions135covering the data line171, a plurality of branch electrodes133positioned between two longitudinal portions135and separated from each other, and a lower transverse portion132aand an upper transverse portion132bconnecting ends of a plurality of branch electrodes133. The longitudinal portion135is substantially parallel to the data line171and overlaps the data line171while covering it. The lower and upper transverse portions132aand132bare substantially parallel to the gate line121. A plurality of branch electrodes133are substantially parallel to each other and form an oblique angle with respect to the extending direction of the gate line121, and the oblique angle may be more than 45 degrees. The branch electrode133at the upper side and the branch electrode133at the lower side may be inversely symmetrical with respect to an imaginary transverse center line of the common electrode131. The neighboring common electrodes131are connected to each other while sharing one longitudinal portion135. The common electrode131receives a voltage such as a common voltage Vcom from the common voltage line125through the second contact hole182. The common electrode131according to an exemplary embodiment of the present invention overlaps the pixel electrode191. Particularly, at least two neighboring branch electrodes133of the common electrode131overlap one pixel electrode191having a plane shape.

Next, a portion of the peripheral area and the driving region of the thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference toFIG. 4andFIG. 5.

Referring toFIG. 4andFIG. 5, a plurality of driver connection lines123are formed on the insulation substrate110. The driver connection lines123may be made of the gate conductor material. The end of the driver connection line123forms the first driving input pad50a.

The gate insulating layer140is formed on the driver connection line123. The first driving output pad50bis formed on the gate insulating layer140. A portion of the driver connection line123is extended and disposed under the first driving output pad50b. The first driving output pad50bincludes a first layer150, which may be formed with the same layer material as the semiconductor151of the display area, a second layer160, which may be formed with the same layer material as the ohmic contact of the display area, and a third layer170, which may be made of the data conductor material of the display area. The second layer160may be omitted.

The first passivation layer180xis formed on the first driving output pad50band the gate insulating layer140. The second passivation layer180yis positioned on the first passivation layer180x. The first passivation layer180xand the second passivation layer180yhave the first driver contact hole181aexposing the first driving output pad50b, and the first passivation layer180x, the second passivation layer180y, and the gate insulating layer140have the second driver contact hole181bexposing the first driving input pad50aof the driver connection line123. The first driving output pad50band the first driving input pad50a, which are respectively exposed through the first driver contact hole181aand the second driver contact hole181b, are connected by the connecting member91.

The connecting member91may be formed with the same layer material as the pixel electrode191of the display area.

A bump61is disposed on the connecting member91disposed at the position corresponding to the first driving output pad50b. Through the bump61, the driving circuit chip40and the first driving output pad50bare electrically connected to each other.

The third passivation layer180zis disposed on the connecting member91disposed at the position corresponding to the first driving input pad50a, and a dummy electrode layer92formed with the same layer material as the common electrode131is disposed on the third passivation layer180z.

In the case of the thin film transistor array panel according to the present exemplary embodiment, the first driving output pad50bwhere the driving signal is output from the driving circuit chip40includes a layer made of the data conductor material of the display area. Accordingly, compared with a case of forming the first driving output pad50bwith the gate conductor material, a depth of the first driver contact hole181aexposing the first driving output pad50bis not relatively large. Also, the layer made of the gate conductor material is disposed under the first driving output pad50bmade of the data conductor material such that the depth of the first driver contact hole181amay be further reduced. Accordingly, the interval between the driving circuit chip40and the first driving output pad50bis small such that the connection using bump61is easy. Also, in the case of the thin film transistor array panel according to the present exemplary embodiment, the driver connection line123connecting the driving circuit chip40and the display area is formed with the gate conductor material through one etch process such that the width may be small compared with the driver connection line123being formed with the data conductor material, and thereby the width of the peripheral area near the display area may be reduced.

Also, in the case of the thin film transistor array panel according to the present exemplary embodiment, the second driver contact hole181bexposing the first driving input pad50aas the end of the driver connection line123is covered and protected by the third passivation layer180zas the interlayer insulating layer disposed between the pixel electrode191and the common electrode131; the dummy electrode layer92made with the same layer material as the common electrode131; and the connecting member91made with the same layer material as the pixel electrode191. Thereby, corrosion of the driver connection line123may be prevented.

Next, a thin film transistor array panel according to another exemplary embodiment of the present invention will be described with reference toFIG. 8andFIG. 9as well asFIG. 6andFIG. 7.FIG. 6is a layout view of one pixel of a display area of a thin film transistor array panel according to another exemplary embodiment of the present invention, andFIG. 7is a cross-sectional view of the thin film transistor array panel taken along the line VII-VII ofFIG. 6.FIG. 8is a layout view of a portion of a peripheral area and a driving region of a thin film transistor array panel according to an exemplary embodiment of the present invention, andFIG. 9is a cross-sectional view of the thin film transistor array panel taken along the line IX-IX′ ofFIG. 8.

First, a display area of a thin film transistor array panel according to another exemplary embodiment of the present invention will be described with reference toFIG. 6andFIG. 7.

Referring toFIG. 6andFIG. 7, the display area of the thin film transistor array panel according to the present exemplary embodiment is the same as most of the display area of the thin film transistor array panel shown inFIG. 2andFIG. 3. A plurality of gate conductors including a plurality of gate lines121and a plurality of common voltage lines125are formed on an insulation substrate110.

A gate insulating layer140is formed on the gate conductors121and125.

A plurality of semiconductors151including a plurality of projections154are formed on the gate insulating layer140. An ohmic contact161may be disposed on the semiconductor151, but the ohmic contact may be omitted.

A data conductor including a plurality of data lines171and a plurality of drain electrodes175is formed on the ohmic contact. In contrast to the thin film transistor array panel according to the exemplary embodiment shown inFIG. 2andFIG. 3, the data line171of the thin film transistor array panel according to the present exemplary embodiment is periodically bent, thereby forming an oblique angle by the extending direction of the gate line121. The oblique angle between the data line171and the extending direction of the gate line121may be more than 45 degrees.

A gate electrode124, the source electrode173, and the drain electrode175form the thin film transistor as the switching element along the exposed portion of the projections154of the semiconductor151. The semiconductor151may have almost the same plane shape as the data line171and the drain electrode175except for the channel of the thin film transistor.

A first passivation layer180xis positioned on the data conductors171and175and the exposed portions of the projections154, and the first passivation layer180xmay be made of the organic insulating material or the inorganic insulating material.

A second passivation layer180yis positioned on the first passivation layer180x. The second passivation layer180yincludes the organic material and covers the data line171, and may be formed on the entire surface of the substrate110. The surface of the second passivation layer180ymay be substantially flat.

The first passivation layer180xand the second passivation layer180yhave a fourth contact hole183exposing a portion of the drain electrode175, and the first passivation layer180x, the second passivation layer180yand the gate insulating layer140have a third contact hole184exposing a portion of the common voltage line125.

A common electrode131is formed on the second passivation layer180y. The common electrode131is electrically connected to the common voltage line125through the third contact hole184, thereby receiving the predetermined voltage such as the common voltage Vcom from the common voltage line125. The common electrode131has an opening138exposing a contact hole183described later. In the present exemplary embodiment, the common electrode131may be formed with a single plate on the entire surface of the substrate110.

A third passivation layer180zis formed on the common electrode131, and a pixel electrode191is formed thereon. The first passivation layer180x, the second passivation layer180y, and the third passivation layer180zhave a plurality of fourth contact holes183exposing a portion of the drain electrode175, and the pixel electrode191is electrically connected to the drain electrode175through the third contact hole184and the fourth contact hole183, thereby receiving the data voltage. The pixel electrode191includes a plurality of branch electrodes193substantially parallel to each other and separated from each other, and lower and upper transverse portions192connecting upper and lower ends of the branch electrode193. The branch electrodes193of the pixel electrode191may be bent similarly to the data line171.

The data voltage applied to the pixel electrode191and the common voltage applied to the common electrode131generate an electric field to the liquid crystal layer.

Next, a peripheral area of a thin film transistor array panel according to another exemplary embodiment of the present invention will be described with reference toFIG. 8andFIG. 9.

Referring toFIG. 8andFIG. 9, the peripheral area and the driving region of the thin film transistor array panel according to the present exemplary embodiment is the same as most of the display area of the thin film transistor array panel shown inFIG. 4andFIG. 5.

Referring toFIG. 8andFIG. 9, a plurality of driver connection lines123are formed on the insulation substrate110. The driver connection line123may be made of the gate conductor material. The end of the driver connection line123forms a first driving input pad50a.

The gate insulating layer140is formed on the driver connection line123. A first driving output pad50bis formed on the gate insulating layer140. A portion of the driver connection line123is extended under the first driving output pad50b. The first driving output pad50bincludes a first layer150, which may be made with the same layer material as the semiconductor151of the display area, a second layer160, which may be made with the same layer material as the ohmic contact of the display area, and a third layer170, which may be made of the data conductor material of the display area. Here, the second layer160may be omitted.

The first passivation layer180xis disposed on the first driving output pad50band the gate insulating layer140. The second passivation layer180yis positioned on the first passivation layer180x. The first passivation layer180xand the second passivation layer180yhave a first driver contact hole181aexposing the first driving output pad50b, and the first passivation layer180x, the second passivation layer180y, and the gate insulating layer140have a second driver contact hole181bexposing the first driving input pad50aof the driver connection line123. The first driving output pad50band the first driving input pad50a, which are respectively exposed through the first driver contact hole181aand the second driver contact hole181bare connected by a connecting member91.

The connecting member91may be made with the same layer as the common electrode131of the display area.

A bump61is disposed on the connecting member91disposed at the position corresponding to the first driving output pad50b. Through the bump61, the driving circuit chip40and the first driving output pad50bare electrically connected to each other.

The third passivation layer180zis disposed on the connecting member91disposed at the position corresponding to the first driving input pad50a, and a dummy electrode layer92made with the same layer material as the pixel electrode191is disposed on the third passivation layer180z.

In the case of the peripheral area of the thin film transistor array panel according to the present exemplary embodiment, differently from the peripheral area of the thin film transistor array panel according to the exemplary embodiment shown inFIG. 4andFIG. 5, the connecting member91is made with the same layer material as the common electrode131, and the dummy electrode layer92is made with the same layer material as the pixel electrode191.

In the case of the thin film transistor array panel according to the present exemplary embodiment, the first driving output pad50boutputting the driving signal from the driving circuit chip40includes the data conductor of the display area. Accordingly, compared with the case of forming the first driving output pad50bwith the gate conductor, the depth of the first driver contact hole181aexposing the first driving output pad50bis not large. Also, a layer made of the gate conductor is disposed under the first driving output pad50bmade of the data conductor such that the depth of the first driver contact hole181amay be further decreased. Accordingly, the interval between the driving circuit chip40and the first driving output pad50bis not large, and thereby the connection using the bump61is easy. Also, in the case of the thin film transistor array panel according to the present exemplary embodiment, the driver connection line123connecting the driving circuit chip40and the display area is formed with the gate conductor through one etching process such that the width is narrowly formed compared with a data conductor formed through two etching processes, and thereby the area of the peripheral area near the display area may be reduced.

Also, in the case of the thin film transistor array panel according to the present exemplary embodiment, the second driver contact hole181bexposing the first driving input pad50aas the end of the driver connection line123is covered and protected by the third passivation layer180zas the interlayer insulating layer disposed between the pixel electrode191and the common electrode131; the dummy electrode layer92made with the same layer material as the pixel electrode191; and the connecting member91made with the same layer material as the common electrode131, thereby preventing the corrosion of the driver connection line123. That is, in the case of the peripheral area of the thin film transistor array panel according to an exemplary embodiment of the present invention, the driver connection line123exposed through the contact hole is covered and protected by the connecting member91made with the same layer material as one of two field generating electrodes191and131; the third passivation layer180zas the interlayer insulating layer between the two field generating electrodes191and131; and the dummy electrode layer92made with the same layer material as one of the two field generating electrodes191and131.

Next, a thin film transistor array panel according to another exemplary embodiment of the present invention will be described with reference toFIG. 10toFIG. 13.FIG. 10is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention,FIG. 11is a layout view of one pixel in a display area of a thin film transistor array panel according to another exemplary embodiment of the present invention,FIG. 12is a cross-sectional view of the thin film transistor array panel ofFIG. 11taken along the line XII-XII, andFIG. 13is a cross-sectional view of the thin film transistor array panel ofFIG. 10taken along the line XIII-XIII′

First, referring toFIG. 10, a thin film transistor array panel according to another exemplary embodiment of the present invention includes a display area10to display images, a peripheral area20arranged at the periphery of the display area10, and a driving region30disposed near the peripheral area20, similarly to the thin film transistor array panel of the exemplary embodiment shown inFIG. 1. A driving circuit chip40is disposed in the driving region30, and a driver connection unit50which connects a signal line is disposed in the display area10, and the driving circuit chip40of the driving region30is disposed in the peripheral area20.

However, in the thin film transistor array panel according to the present exemplary embodiment, the structure of the peripheral area20and the driving region30differs from the thin film transistor array panel of the exemplary embodiment shown inFIG. 1. Referring to the enlarged view of a portion of the peripheral area20and the driving region30inFIG. 10, a plurality of driver connection lines123, a second driving output pad51a, an output line51bextending from the second driving output pad51a, and a second driving input pad51care disposed in the driver connection unit50. The driver connection lines123are formed with the same layer material as the second driving input pad51c, and are connected to each other.

A first connecting member91ais formed on a plurality of third driver contact holes182aexposing portions of the second driving output pad51a. A second connecting member91bis disposed on a plurality of fourth driver contact holes182bexposing a portion of the end of the output line51band a plurality of fifth driver contact holes182cexposing a portion of the second driving input pad51c. The second driving output pad51ais connected to the driving circuit chip40through a bump (not shown).

Whenever the driving signal is output from the driving circuit chip40to the first driving output pad50bthrough the bump and the first connecting member91a, the output driving signal is transmitted through the output line51band is transmitted to the second driving input pad51cconnected to the output line51bby the second connecting member91b. The driving signal input to the second driving input pad51cis transmitted through the driver connection lines123, thereby being transmitted to the signal line of the pixel PX.

Next, the thin film transistor array panel according to the present exemplary embodiment of the present invention will be described with reference toFIGS. 10 to 13.

First, referring toFIG. 11andFIG. 12, a display area of the thin film transistor array panel according to the present exemplary embodiment is similar to the display area of the thin film transistor array panel according to the exemplary embodiment described with reference toFIG. 6andFIG. 7.

In detail, a plurality of gate conductors including a plurality of gate lines121and a plurality of common voltage lines125are formed on the insulation substrate110, and a gate insulating layer140is formed on the gate conductors121and125. A plurality of semiconductors151including a plurality of projections154are formed on the gate insulating layer140, and ohmic contacts (not shown) may be formed on the semiconductors151and154. The ohmic contacts may be omitted. A data conductor including a plurality of data lines171and a plurality of drain electrodes175is formed on the ohmic contacts. A gate electrode124, a source electrode173, and a drain electrode175form a thin film transistor as a switching element along with the projections154. The semiconductors151and154may have almost the same plane shape as the data line171and the drain electrode175except for the semiconductor154including the channel portion of the thin film transistor.

A first passivation layer180xis positioned on the data conductor171and175and the exposed portions of the projections154. A second passivation layer180yis positioned on the first passivation layer180x. The second passivation layer180yincludes the organic material and may be formed on the whole surface of the substrate110while covering the data lines171. The surface of the second passivation layer180ymay be substantially flat.

The first passivation layer180xand the second passivation layer180yhave a first contact hole181exposing a portion of the drain electrode175, and the first passivation layer180x, the second passivation layer180y, and the gate insulating layer140have a third contact hole184exposing a portion of the common voltage line125.

A common electrode131is formed on the second passivation layer180y. The common electrode131is electrically connected to the common voltage line125through the third contact hole184, thereby receiving the predetermined voltage such as the common voltage Vcom from the common voltage line125. In the present exemplary embodiment, the common electrode131may be formed with a plate shape on the entire surface of the substrate110.

The third passivation layer180zis formed on the common electrode131and the pixel electrode191is formed thereon. The first passivation layer180x, the second passivation layer180y, and the third passivation layer180zhave a plurality of fourth contact holes183exposing a portion of the drain electrode175, and the pixel electrode191is electrically connected to the drain electrode175through the first contact hole181and the fourth contact hole183, thereby receiving the data voltage. The pixel electrode191includes a plurality of branch electrodes193that substantially extend parallel to each other and are spaced apart from each other, and upper and lower horizontal portions192that connect a lower end part and an upper end part of the branch electrodes193. The branch electrodes193of the pixel electrode191may be curved along the data lines171.

The data voltage applied to the pixel electrode191generates the electric field to the liquid crystal layer3along with the common electrode131applied with the common voltage.

Next, a portion of the peripheral area and the driving region of the thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference toFIG. 13along withFIG. 10.

Referring toFIG. 10andFIG. 13, a plurality of driver connection lines123are formed on the insulation substrate110. The driver connection lines123are made of the gate conductor material. A portion of the driver connection lines123forms the second driving input pad51c.

The gate insulating layer140is formed on the driver connection lines123and the second driving input pad51cmade of the gate conductor. The second driving output pad51aand the output line51bare formed on the gate insulating layer140. The second driving output pad51aand the output line51binclude the first layer150formed with the same layer material as the semiconductor151of the display area, the second layer160formed with the same layer material as the ohmic contact of the display area, and the third layer170made of the data conductor material of the display area. Here, the second layer160may be omitted.

The first passivation layer180xis disposed on the second output pad51a, the output line51b, and the gate insulating layer140. The third passivation layer180zis disposed on the first passivation layer180x. In the case of the thin film transistor array panel according to the present exemplary embodiment, in the peripheral area and the driving region of the display panel, the second passivation layer180ymade of the organic layer is omitted, differently from the display area.

The first passivation layer180xand the third passivation layer180zhave a plurality of third driver contact holes182aexposing the second driving output pad51aand a fourth driver contact hole182bexposing the portion of the output line51b. The first passivation layer180x, the third passivation layer180z, and the gate insulating layer140have a plurality of fifth driver contact holes182cexposing the second driving input pad51c.

The first connecting member91ais disposed on a plurality of the third driver contact holes182aexposing the portion of the second driving output pad51a.

A bump61is disposed on the first connecting member91acovering the second driving output pad51aexposed through the third driver contact hole182a. Through the bump61, the driving circuit chip40and the second driving output pad51aare electrically connected to each other.

The second connecting member91bis disposed on a plurality of the fourth driver contact holes182bexposing a portion of the end of the output line51band a plurality of the fifth driver contact holes182cexposing the portion of the second driving input pad51c.

The first connecting member91aand the second connecting member91bare formed with the same layer material as the pixel electrode191.

In the present exemplary embodiment, the first connecting member91aconnecting the second driving output pad51aand the bump61, the output line51bconnected to the second driving output pad51a, and the second connecting member91bconnected to the second driving input pad51care formed with the same layer material as the pixel electrode191. However, the first connecting member91aand the second connecting member91bmay be formed with the same layer material as the common electrode131, and not the pixel electrode191. In detail, the first connecting member91aand the second connecting member91bare formed with the same layer material as the field generating electrode that is disposed at the upper side among two field generating electrodes of the thin film transistor array panel. In the case of the thin film transistor array panel of another exemplary embodiment of the present invention, the pixel electrode191may be disposed under the third passivation layer180zand the common electrode131may be disposed on the third passivation layer180z, and in this case, the first connecting member91aand the second connecting member91bmay be formed with the same layer material as the common electrode131.

In the thin film transistor array panel according to the present exemplary embodiment, the second driving output pad51afrom which the driving signal is output from the driving circuit chip40includes a layer formed with the same layer material as the data conductor of the display area. Accordingly, compared with the case where the second driving output pad51ais formed of the gate conductor material, a depth of the third driver contact hole182aexposing the second driving output pad51ais not relatively deep. Also, the layer made of the gate conductor material is disposed under the second driving output pad51aincluding the layer made of the data conductor material such that the depth of the third driver contact hole182amay be further decreased. Accordingly, the interval between the driving circuit chip40and the second driving output pad51ais not wide, thereby facilitating easy connection using the bump61. Also, in the thin film transistor array panel according to the present exemplary embodiment, the driver connection lines123connecting the driving circuit chip40and the display area are formed of the gate conductor material using only one etching process, thereby reducing the width compared with the data conductor formed through two etching processes such that the area of the peripheral area near the display area may be reduced.

Further, in the thin film transistor array panel according to the present exemplary embodiment, the output line51b(e.g., p ofFIG. 10) covered by the passivation layers180xand180zis disposed between two neighboring second driving output pads51a(e.g., x and y ofFIG. 10) disposed on the same line in the horizontal direction, not the second driving output pad51a. That is, two neighboring second driving output pads51a(e.g., x and z ofFIG. 10) are separated in the vertical direction. Therefore, the interval of the neighboring second driving output pads51a(e.g., x and y ofFIG. 10) disposed on the same line in the horizontal direction may be increased. Accordingly, even if a misalignment is generated between the driving pad40and the second driving output pad51a(e.g., x ofFIG. 10), the misaligned driving pad40overlaps the output line51b(e.g., p ofFIG. 10), not the second driving output pad51a(e.g., z ofFIG. 10), and thereby the crosstalk of the driving signal due to the misalignment between the driving pad40and the second driving output pad51amay be avoided.

In the case of the thin film transistor array panel according to the above-described exemplary embodiments, one of two field generating electrodes which overlap each other has a plate shape and the other includes the branches. However, the present invention may be applied to a thin film transistor array panel of all shapes in which one display panel has two field generating electrodes.