Apparatus and method for processing data

A data processing device includes a compression circuit and a padding circuit. The compression circuit is configured to compare pairs of two contiguous bits within data composed of 2n bits (where n is a natural number), and compress the data based on a result of the comparison. The padding circuit is configured to generate transmission data of 2n bits by padding the compressed data with a dummy pad.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority based upon Korean patent application No. 10-2013-0168660, filed on Dec. 31, 2013, the disclosure of which is hereby incorporated in its entirety by reference herein.

BACKGROUND

Embodiments of the present disclosure relate to an apparatus and method for processing data, and more particularly, to an apparatus and method for processing data, capable of compressing data and transmitting/receiving the compressed data.

In recent times, as the desire for smaller-sized and higher-speed electronic appliances has increased, research into miniaturization and increasing the speed of electronic appliances has been conducted. For miniaturization of electronic appliances, techniques for miniaturizing circuits included in the electronic appliance may be used. For implementation of higher-speed electronic appliances, techniques for improving internal signal transmission timing may be used.

When a process for implementing a specific operational purpose of the electronic appliance is simplified, circuits within the electronic appliance can be simplified and the internal operating speed of the circuits can be increased, such that smaller-sized and higher-speed electronic appliances can be achieved.

SUMMARY

Various embodiments of the present disclosure are directed to an apparatus and method for processing data that substantially obviates one or more problems due to limitations and disadvantages of the related art.

Embodiments of the present disclosure include an apparatus and method for processing data which can reduce an amount of transmission (Tx) data by performing data compression on the basis of transmission/reception (Tx/Rx) data values and can increase a speed of data transmission.

An embodiment relates to an apparatus and method for processing data, which can perform data processing optimal for each operation by changing a compression scheme according to characteristics of Tx/Rx data.

In an embodiment, a data processing device includes a controller. The controller includes a compression circuit configured to compare pairs of two contiguous bits of data composed of 2n bits, where n is a natural number, and compress the data according to a result of the comparisons. The controller also includes a padding circuit configured to generate transmission (Tx) data of 2n bits by padding the compressed data with a dummy pad.

In another embodiment, a data processing method includes comparing pairs of two contiguous bits of data composed of 2n bits, where n is a natural number, compressing the data according to a result of the comparison, generating flag information indicating compression or non-compression of the data, generating transmission (Tx) data of 2n bits by padding the compressed data with a dummy pad, and transmitting the Tx data and the flag information through a physical connector.

Both the foregoing general description and the following detailed description of the present invention are illustrative and explanatory, and are intended to provide further explanation of the invention as claimed.

DETAILED DESCRIPTION

In association with embodiments, specific structural and functional descriptions are disclosed for illustrative purposes. Embodiments can be implemented in various ways without departing from the scope or spirit of the present disclosure.

FIG. 1is a block diagram illustrating a data processing apparatus10according to an embodiment. The data processing apparatus10includes a controller100and a memory device200.

The controller100generates various signals for controlling the memory device200, and transmits the generated signals to the memory device200. The controller100may transmit various data and control signals such as commands and address signals to the memory device200, including transmission (Tx) data DQPand flag information CF.

Although not shown in the drawings, in an embodiment, the controller100receives data from the memory device200. The received (Rx) data may be compressed and processed by the memory device200in the same manner as when the controller100compresses and processes Tx data DQPto be transmitted to the memory device200. The controller100receives the Rx data from the memory device200, and at the same time receives flag information CF indicating compression or non-compression of the Rx data. The controller100includes an encoder110and a transmitter120.

The encoder110determines a compression scheme on the basis of a mode signal mode, and compresses data Dm of 2n bits, where n is a natural number. The encoder110may pad the compressed data with one or more dummy bits so that the encoder110generates Tx data DQPcomposed of 2n bits. The encoder110also generates flag information CF indicating compression or non-compression of the data Dm.

The encoder110compares pairs of contiguous bits of the 2n bits of data Dm to each other. In more detail, the data Dm is composed of n bit-pairs. The encoder110compares the bits of each of the n bit-pairs to each other and performs data compression according to the comparison results. Since the encoder110compares values of bits included in the data Dm with each other and then performs data compression, additional information, such as a dictionary or look-up table, is not required to perform the compression. The data processing apparatus10can reduce the amount of information through data compression, need not use additional information for the data compression, and thus can be implemented as a simple structure.

In another embodiment, the Tx data DQPand the flag information CF are transmitted through a same physical connector. If the Tx data DQPand the flag information CF are transmitted through the same physical connector, the flag information CF may be attached to a front end or a back end of the Tx data DQP, such that the resultant data including the flag information CF can be transmitted.FIG. 10, discussed below, relates to an embodiment in which the flag information CF and the Tx data DQPare transmitted through a same physical connector.

The memory device200includes a receiver210and a decoder220. The receiver210receives the Tx data DQPand the flag information CF from the controller100, and provides the received Tx data DQPand flag information CF to the decoder220.

The decoder220determines the scheme used for compressing the Tx data DQp using the mode signal mode, and determines whether the data Dm is compressed or not using the flag information CF. Accordingly, the compression of Tx data DQPis reversed, that is, the Tx data DQPis decompressed, and the data Dm is recovered.

The memory device200may further include a storage circuit230. The storage circuit230may be capable of storing the recovered data Dm and may include a memory cell array. The storage circuit230may include a memory cell array composed of volatile or non-volatile memory cells.

The controller100and the memory device200shown inFIG. 1may be used as physical components, populated on a printed circuit board (PCB), and interconnected through the PCB, such that the controller100and the memory device200may each be circuits in different hardware devices.

FIG. 2is a block diagram illustrating the encoder110ofFIG. 1according to an embodiment. The encoder110includes a compression circuit111and a padding circuit113.

The compression circuit111determines a compression scheme according to the mode signal mode, and compresses the data Dm on the basis of the determined compression scheme. The compression circuit111provides compressed data CDQIand the flag information CF indicating compression or non-compression of the data Dm to the padding circuit113.

If the bits of pairs of two contiguous bits of the data Dm are identical, the compression circuit111may compress the two-bit pairs into one bit. If the bits of pairs of two contiguous bits are different, the two bits may or may not be compressed, depending on the mode signal mode.

In an embodiment, the mode signal mode may specify one or more of a loss mode and a lossless mode in association with the compression scheme. In the loss mode, the maximum number of bits allowed to be lost may be established by the mode signal mode. In addition, if data is compressed in the loss mode, that is, under the condition that data loss is allowed, the mode signal mode may further include specific information indicating how to determine which specific bit information will be lost.

If the mode signal mode corresponds to the lossless mode, the compression circuit111does not compress two bits that are different from each other. If the mode signal mode corresponds to the loss mode, the compression circuit111may perform data compression by replacing two different bits with one bit, or may give priority to one of the two bits and replace the two bits with one bit equal to the bit having priority. In an embodiment, when the compression circuit111compresses the data Dm in the loss mode, it sequentially assigns priority in the order from a most significant bit (MSB) to a least significant bit (LSB). The compression circuit111then selects a bit having a higher priority of the bits in a bit-pair, and replaces a bit having a lower priority of the bits in the bit-pair, that is, the bit to be lost, with the selected bit.

In an embodiment, the loss mode may be used during processing of graphic data. When processing the graphic data using the loss mode, although a predetermined number of bits are lost, no fatal error occurs in graphic data supplied to a user and a higher operation speed can be achieved.

In an embodiment, an allowable number of bits to be lost are indicated by the mode signal mode. In an embodiment, the compression circuit111compares 8 bit-pairs (that is, 16 bits of data) included in the data Dm with each other. The comparison result may indicate that the bits in three bit-pairs have the same values, indicating that these three bit pairs can be compressed without data loss. The comparison result may also indicate that the bits of 5 bit-pairs have different values, indicating that it is impossible to perform data compression without data loss.

If the mode signal mode corresponds to the loss mode, each of the five bit-pairs having different bits may be replaced with one bit so that the resultant bit-pairs may be compressed. As a result, the replaced bit is lost from each of the 5 bit-pairs in the data compression process, and thus 5 bits are unavoidably lost. If the lost bits were necessary to an operation, the operation may encounter unexpected errors. Accordingly, the mode signal mode may specify a number of lost bits to be less than a predetermined number of bits.

If the mode signal mode indicates that only two bits from among 16-bit data Dm can be lost, only two bit-pairs from among the 5 bit-pairs having different bits may be compressed in the loss mode, and accordingly the compression circuit111selects two bit-pairs to be compressed. When the compression circuit111selects the two bit-pairs to be compressed, a predetermined criteria for the selection may be used. In an embodiment, during the compression process, the compression circuit111may first discard or lose the least significant bit (LSB), and gradually reduces a loss rate of bits as the bit location approaches the most significant bit (MSB).

A data processing apparatus and method according to an embodiment will hereinafter be described with reference toFIGS. 3 through 10.FIGS. 3 through 10are tables showing binary data, and associated data processing will be described with reference to the block diagrams shown inFIGS. 1 and 2.FIGS. 3 through 10illustrate an embodiment wherein data has a burst length of 16, each burst comprising 8 bits.

FIG. 3shows data Dm received from an external source by the controller100ofFIG. 1.FIG. 4shows flag information CF and compressed data CDQIobtained when the data Dm ofFIG. 3is compressed by the compression circuit111.FIG. 5shows the flag information CF and Tx data DQPobtained after the padding circuit113appends a dummy pad to the compressed data CDQI.

FIG. 3shows a total of 128 bits of the data Dm that are to be processed by the controller100. Bits D0through D7of the portion of the data Dm provided at each of 1stthrough 16thpoints in time will hereinafter be denoted as 1stthrough 16thbursts B0through B15. The first burst B0corresponds to “00001111”, the second burst B1corresponds to “11110000”, and the third burst B2corresponds to “11001100,” and so on.

When the compression circuit111compares two contiguous bits of the data Dm with each other, the two bits compared may be two contiguous bits of one burst.

InFIG. 3, the first burst B0of the data Dm is denoted by “00001111”. Four bit-pairs, each of which includes two contiguous bits (i.e., a bit-pair) of the first burst B0, therefore contain “00”, “00”, “11”, and “11”. The compression circuit111compares the bits in each bit-pair with each other and determines that the bits in each bit-pair have a same value. If the bits in each bit-pair have the same value, the compression circuit111compresses each of the bit-pairs into one bit.

Accordingly, referring toFIG. 4, a first compression burst CB0of the compressed data CDQIproduced by the compression circuit111has the value of “0011”, and2nbits of the data Dm are compressed into n bits.

Likewise, the second burst B1of the data Dm is comprised of bit-pairs “11”, “11”, “00”, and “00”. The compression circuit111compares the values of the bits in each bit-pair with each other, determines that they all match, and compresses2nbits of the bit-pairs into n bits having the value “1100” in a second compression burst CB1. In the same manner, the third burst B2comprised of bit-pairs “11”, “00”, “11”, and “00” is compressed into a third compression burst CB2having the value “1010.”

As described above, assuming that all bit-pairs within each of the 16 bursts CB0, CB1, CB2, CB3, . . . , CB15of the data Dm are comprised of matching bits, each of the bit-pairs are compressed to one bit, such that the compressed data CDQIis 64 bits long compressed from the 128 bits of the data Dm. However, because one bit according to flag information CF indicating compression or non-compression of data is added to each burst, information actually needed for data recovery, that is, information needed to decompress the compressed data CDQI, is 80 bits long (SeeFIG. 4).

Referring toFIGS. 3 and 4, if all bursts of the data Dm are compressed, a compression rate of the compression circuit111may be calculated as 80/128, i.e., 62.5%.

Although the above-mentioned embodiment discloses compressing the data Dm in units of a burst occurring at one point in time, the data Dm may also be compressed in units of data through one connector. Accordingly, in another embodiment, when the first data D0may have 16 bits denoted by “0110110110110110” as shown inFIG. 3, the values of 8 bit-pairs corresponding to the 16 bits may be compared and compressed according to a certain compression scheme, and each of D1through D7may be similarly compressed.

Referring toFIG. 4, the data Dm having the input/output (I/O) width of 8 bits is converted and compressed into 4 bits of compressed data CDQI.

Referring toFIG. 5, the padding circuit113pads the 4 bits of compressed data CDQIwith a plurality of dummy bits D, generating Tx data DQPhaving an I/O width of 8 bits. The padding circuit113provides the Tx data DQPto the transmitter120, which transmits the Tx data DQPto the memory device200. The memory device200may discard the dummy bits on the basis of the flag information CF, and decode the remainder of the received TX data DQPto recover the data Dm.

In an embodiment, if all bits of the data Dm are compressed as shown in relation toFIG. 3, only compression data CDQIand flag information CF may be supplied to the memory device200. For example, if all data Dm is compressed as shown inFIG. 4, each of the compression bursts CB0, . . . , CB15has 4 bits, and therefore a predetermined amount of I/O pads may not be used since an amount of transmission data is reduced. In an embodiment wherein the data Dm has a burst length of 16 and is transmitted through first through eighth I/O pads, the compressed data CDQImay be transmitted only through the first through fourth I/O pads, and non-used I/O pads, e.g., the fifth through eighth I/O pads, may be used for transmission of flag information CF or for transmission/reception of other signals.

However, because all of the data Dm is not always compressed, the padding circuit113fills the compressed data CDQIwith dummy bits.

FIG. 5shows not only Tx data generated by the padding circuit113, but also flag information.

As can be seen fromFIG. 5, each dummy bit is denoted by “D”. The dummy bits may be “0” or “1”, and all of the dummy bits used as padding bits may have a same value. In an embodiment, the bits used as the dummy bits may be predetermined bits, and may be bits capable of minimizing power consumed for data transmission/reception (Tx/Rx).

In another embodiment, the dummy bits may be determined on the basis of bit values comprising the compressed data CDQI. InFIG. 3, the number of ‘0’ bits is identical to the number of ‘1’ bits in each unit of the data Dm being compressed. However, if the number of ‘0’ bits and the number of ‘1’ bits differ, the dummy bit(s) may be filled according to the value corresponding to the majority of the bits, which may minimize the power consumption needed for bit conversion.

However, bit-pairs included in the data Dm may include bits having the same bit values or different bit values. In other words, although the data Dm ofFIG. 3show the case in which all bit-pairs have matching bit values, the matching bit values may not always be present in the bit-pairs, and as a result data compression may not be performed.

In an embodiment, the data processing apparatus10is configured to perform data compression even in the case in which two contiguous bits of the data Dm are not identical when operating in a loss mode, according to a compression scheme indicated by the mode signal mode.

FIGS. 6 through 9illustrate an operation in a loss mode of the data processing apparatus10according to an embodiment.FIG. 6shows data Dm to be compressed, andFIGS. 7 through 9each show transmission data DQPgenerated when the data Dm is compressed in different ways according to the mode signal mode.

In the same manner as inFIG. 3,FIG. 6shows the data Dm with a burst length of 16, with each of the 16 bursts B0, B1, B2, . . . , B15having 8 bits of the data Dm.

Referring toFIG. 6, in all the bursts other than the fourth burst B3, the eighth burst B7, the twelfth burst B11, and the fifteenth burst B14, the bits in all pairs of two contiguous bits are identical. Each burst in which all pairs of two contiguous bits are identical may be compressed into 4 bits, and flag information CF associated with the burst is generated as ‘1,’ as shown inFIG. 7. The compression formats of lossless compressed data CB0, CB1, CB2, CB4, CB5, CB6, CB8, CB9, CB10, CB12, CB13, and CB15inFIG. 7are identical to the compression formats used inFIG. 5.

In order to compress the fourth burst B3, eighth burst B7, twelfth burst B11, and fifteenth burst B14ofFIG. 6, each of which includes 8 bits of data and has at least one 2-bit pair having different bits, some bits are lost.

To compress the 8 bits comprising the fourth burst B3of the data Dm, one of the third bit “0” and the fourth bit “1” is lost. Likewise, to compress the eighth burst B7, two of the third bit “1”, fourth bit “0”, seventh bit “1”, and eighth bit “0” of the eighth burst B7are lost. To compress the twelfth burst B11, two of the third bit “0”, fourth bit “1”, seventh bit “1”, and eighth bit “0” of the twelfth burst B11are lost. Finally, to compress the fifteenth burst B14, one of the third bit “0” and the fourth bit “1” of the fifteenth burst B14is lost.

FIG. 7shows a case in which the mode signal mode corresponds to the lossless mode. During the lossless mode, even one bit from among all bits should not be lost or damaged by data compression. Accordingly, the compression circuit111does not compress the fourth burst B3, the eighth burst B7, the twelfth burst B11, and the fifteenth burst B14, and instead transmits these bursts B3, B7, B11, and B14as compressed data CDQIwithout change, and generates flag information CF of the value of “0” indicating an uncompressed state for each of these bursts.

Since all 8 bits of information are included in each of the fourth burst B3, eighth burst B7, twelfth burst B11, and fifteenth burst B14, the padding circuit113does not insert dummy bits into the bursts B3, B7, B11, and B14.

The memory device200having received transmission data DQPmay detect an uncompressed state of a specific burst on the basis of the flag information CF, and may record the corresponding burst in the storage circuit230without change. In the case shown inFIG. 7, the memory device200may determine that each of the fourth bit, the seventh bit, the twelfth bit, and the fifteenth bit of the flag information CF is set to “0,” and that the corresponding fourth, seventh, twelfth, and fifteenth bursts of the transmission data DQPare uncompressed.

In the case shown inFIG. 7, in which data loss caused by compression is not allowed, 12 bursts except the fourth, seventh, twelfth, and fifteenth bursts are compressed into 4 bits to produce a total of 48 bits, 4 bursts of 8 bits, i.e., the fourth, seventh, twelfth, and fifteenth bursts, remain uncompressed to produce a total of 32 bits, and the flag information CF is composed of 16 bits, such that a total number of bits is 96 (=48+32+16). Accordingly, the compression rate is calculated as 96/128, i.e., 75%.

FIG. 8illustrates the compressed data CDQIproduced when the mode signal mode corresponds to the loss mode. InFIG. 8, although bit loss caused by compression is allowed, only one bit is allowed to be lost for each burst serving as a data compression unit.

Accordingly, the compression circuit111compresses the fourth burst B3and the fifteenth burst B14in which the third bit “0” and the fourth bit “1” are different from each other, i.e., only one bit-pair has different bits therein. The eighth burst B7and the twelfth burst B11, each of which would lose two bits as a result of the compression, are not compressed since the eighth burst B7and the twelfth burst B11each includes two bit-pairs having different bits therein, i.e., a bit-pair of D2and D3and a bit-pair of D6and D7.

When performing data compression in the loss mode, one of the third bit and the fourth bit is replaced with another bit to permit the compression, and data compression is then carried out. The compression circuit111selects which bit will be replaced with another bit.

In an embodiment, when data is lost, all the lost bits may be replaced with the same bit value. Accordingly, in an embodiment, when data is lost and compressed, the lost data may be replaced with “0,” so that in the fourth burst B3ofFIG. 6, “00011111” is replaced with “00001111”, such that the resultant data can be compressed into “0011,” as shown inFIG. 8. In another embodiment, the lost data may be replaced with “1,” so that in the fourth burst B3ofFIG. 6, “00011111” is replaced with “00111111”, such that the resultant data can be compressed into “0111.”

In another embodiment, one of the two bits in a bit-pair wherein a bit must be lost may be replaced with the other bit of the bit-pair, such as the more significant bit replacing the less significant bit of the bit-pair, and the resultant data may then be compressed. Accordingly, if the fourth bit of a burst is not identical to the third bit of the burst, and the fourth bit is determined to be more significant than the third bit, the third bit is replaced with the value of the fourth bit. That is, in the case of the fifteenth burst B14, “11011100” is replaced with “11111100”, such that the resultant data can be compressed into “1110”.

InFIG. 8, because the third burst B4and the fifteenth burst B14are compressed, the associated flag information CF is generated with the value of 1 to indicate this compression state.

If loss of one bit is allowed as shown inFIG. 8, all the non-dummy bits of the Tx data DQPare 88 bits and therefor have a compression rate denoted by 88/128, i.e., 68.75%. The compression using the loss mode, as shown inFIG. 8, has higher compression efficiency than the compression using the lossless mode, as shown inFIG. 7. However, the compression shown inFIG. 8introduces an error such that 2 bits from among the 128 bits are different from the corresponding bits inFIG. 6, such that in the case shown inFIG. 8, the compression using the loss mode has an error rate of 1.56%.

FIG. 9illustrates compression when the mode signal mode corresponds to the loss mode and up to two bits are allowed to be lost for each burst serving as a data compression unit.

When the mode signal mode indicates that up to two bits may be lost, the compression circuit111may compress the eighth burst B7and the twelfth burst B11. In each of the eighth and twelfth bursts B7and B11, the third bit and the fourth bit constituting a bit-pair are not identical, and the seventh bit and the eighth bit constituting a bit-pair are not identical.

In an embodiment, the compression circuit111may receive a mode signal mode that allows the loss of up to two bits per burst and also specifies that an LSB is replaced with an MSB to compress the lost bits.

The compression circuit111replaces the eighth burst B7of “11100010” with “11000000”, compresses the resultant data into “1000”, and generates flag information CF of “1”.

Similarly, the compression circuit111replaces the twelfth burst B11of “11011110” with “11111100”, compresses the resultant data into “1110”, and generates flag information CF of “1”.

InFIG. 9, the padding circuit113may pad the compressed data CDQIwith dummy pad(s). As described above, the dummy bits may be predetermined bits, or the dummy bits may be generated on the basis of the values of bits included in the compressed data CDQI.

In more detail, the fourth compression burst CB3includes three bits of “1” and one bit of “0”. Because the number of “1” bits is greater than the number of “0” bits, the dummy bits padded to the fourth compression burst CB3may be set to “1.” Similarly, in the eighth compression burst CB7, the number of “0” bits is greater than the number of “1” bits, and accordingly the dummy bits padded to the eighth compression burst CB7may be set to “0.”

Considering the efficiency of the compression scheme illustrated byFIG. 9, which scheme uses a loss mode allowing 2 bits of loss per compression unit, all bursts of the data Dm are compressed. Therefore the Tx data DQPhas 80 valid bits, and the compression rate is 80/128, i.e., 62.5%, which is a higher compression rate than that of the lossless compression shown inFIG. 7. However, there arises an error of 6 bits in the compression illustrated byFIG. 9, such that the compression scheme illustrated byFIG. 9has a total error rate of 4.69%.

InFIG. 9, there arises an error of 6 bits within the 128 bits of contemporaneously transmitted data. In an embodiment, the number of erroneous bits may be based on a specific unit determined by the mode signal mode. The mode signal mode may specify that, e.g., an error of more than 5 bits within the 128 bits of contemporaneously transmitted data may not be allowed.

Although the mode signal mode may indicate that the compression circuit111may allow the loss of two bits per burst in the loss mode, the compression circuit111may allow the loss of a maximum of 5 bits among the 128 bits, and may not compress remaining bits other than the 5 bits. When deciding which bits will not be compressed, MSBs may have priority.

In another embodiment, the mode signal mode may decide an error rate which limits the number of allowable lost bits. The number of allowed lost bits may be determined in proportion to the number of bits of data transmitted during a predetermined time.

In the data processing apparatus10according to an embodiment, the compression rate and the error rate have a trade-off relationship. Accordingly, the mode signal mode may indicate that a higher compression rate is allowed according to an acceptable number of bit errors, or may indicate that accurate data is desired and the data compression should be performed without introducing errors.

FIG. 10illustrates an embodiment in which flag information CF is transmitted using the same physical connector as in Tx data DQP. The flag information CF is inserted before the bursts CB0, CB1, . . . , CB15of Tx data DQP. For convenience of description, first compression flag information is denoted by CF0, and second compression flag information is denoted by CF1.

InFIGS. 4, 5, 7, 8, and 9, the relationship between flag information CF and Tx data DQPis a parallel relationship. The parallel relationship may indicate that Tx data DQPand flag information CF are communicated between the controller100and the memory device200through physically separate connectors.

In the embodiment shown inFIG. 10, an additional connector for the flag information CF is not required, and the flag information CF may be transmitted/received using the connector used for transmitting/receiving the Tx data DQP.

The Tx data DQPshown inFIG. 10has 16 bits of flag information CF, each bit of the flag information CF being associated with one of the 16 bursts, and each burst having an I/O width of 8 bits. Flag information CF is generated using the compression circuit111, and may be supplied to the transmitter120after passing through the padding circuit113.

The transmitter120may parallelize the Tx data DQPand the flag information CF according to the connector used for transmission of the flag information CF, as shown inFIG. 10.

Because the flag information CF is 16 bits long, two bursts each comprising 8 data bits DQ0through DQ7are allocated to the flag information CF, and the flag information CF may be inserted as two bursts immediately in front of the Tx data DQP, the two bursts comprising the first and second compression flag information CF0and CF1. The first compression flag information CF0may indicate whether the first through eighth compression bursts CB0through CB7of the Tx data DQPare compressed, and the second compression flag information CF1may indicate whether or not the 9ththrough 16thcompression bursts CB8through CB15of the Tx data DQPare compressed.

In an embodiment, rearrangement of flag information CF may be performed by the transmitter120. In another embodiment, rearrangement of flag information CF may be performed by the encoder110.

FIG. 11is a flowchart illustrating data processing according to an embodiment.

At S1110, the compression circuit111of the encoder110compares 2-bit pairs (i.e., pairs each having 2 contiguous bits) of data Dm composed of 2n bits, where ‘n’ is a natural number, and compresses the data Dm when the comparison produces a specified result. In addition, the compression circuit111generates flag information CF indicating whether compression of the data Dm was performed.

The compression circuit111may perform data compression in different ways according to a result of the comparison between the bits of the 2-bit pairs, according to a received mode signal mode.

If the bits of the 2-bit pairs are identical to each other, the 2-bit pairs are compressed into one identical bit (SeeFIGS. 3 to 5). If the bits of the 2-bit pairs are different from each other, the two bits are selectively compressed according to the mode signal mode.

If the mode signal mode corresponds to the lossless mode, two different bits are not compressed (SeeFIGS. 6 and 7).

If the mode signal mode corresponds to the loss mode, two different bits may be replaced with one predetermined bit, or may be replaced with one bit selected from the two different bits, and data compression is performed (SeeFIGS. 6, 8, and 9).

In addition, if the mode signal mode corresponds to the loss mode, bit replacement may be used for compression and the allowable degree of error may be established.

At S1120, the padding circuit113included in the encoder110may pad the compressed data with dummy bit(s), such that Tx data DQPof 2n bits is generated.

In an embodiment, the dummy bits may be predetermined bits. In another embodiment, the compressed data is analyzed so that a specific value capable of minimizing transmission (Tx) power may be allocated as the dummy bits. For the clarity of description, the encoder110may be referred as a data processing system.

At S1130, the transmitter120may transmit the Tx data DQPand the flag information CF through a physical connector. In an embodiment, the Tx data DQPand the flag information CF may be transmitted through distinct physical connectors. In another embodiment, the Tx data DQPand the flag information CF may be transmitted through the same physical connector.

The receiver210of the memory device200receives the Tx data DQPand the flag information CF from the controller100through the physical connector or connectors. The decoder220recognizes the compression scheme of the Tx data DQPaccording to the mode signal mode, and recognizes whether or not data is compressed according to the flag information CF. By use of the decoder220, the data DM may be restored from the Tx data DQPand may then be stored in the storage circuit230.

FIG. 12is a block diagram illustrating a computing system including the data processing apparatus10according to an embodiment. The computing system1200includes a processor1210, first and second memory devices1220and1230, and first and second interface (I/F) circuits1225and1235.

The processor1210may correspond to the controller100ofFIG. 1, and first and second memory devices1220and1230may correspond to the memory device200ofFIG. 1.

The computing system1200may include various digital computers, for example, a laptop, a desktop, a workstation, a personal digital assistant (PDA), a server, a blade server, a mainframe, and the like.

Constituent elements of the computing system1200may be populated on a printed circuit board (PCB) such as a mother board. The processor1210and the first memory device1220may be interconnected through the first interface circuit1225, and the processor1210and the second memory device1230may be interconnected through the second interface circuit1235.

The processor1210may process a command executed in the computing system1200. The command processed by the processor1210may include a command to perform high-speed data input and/or output (I/O) actions using the first memory device1220and a command to perform low-speed data I/O actions using the second memory device1230. In an embodiment, multiple processors and/or multiple buses may be used along with multiple memories and memory types.

In an embodiment, the processor1210receives a command, such as a mode signal, indicating a data processing scheme, compares bits of 2-bit pairs of data Dm composed of 2n bits, compresses the 2-bit pairs according to the comparison result and the data processing scheme, and thereby provides Tx data DQPand flag information CF to the memory devices1220and1230.

The first memory device1220and the second memory device1230may store various pieces of information in the computing system1200. In an embodiment, the first memory device1220and the second memory device1230may include a volatile memory device or a non-volatile memory device. The volatile memory device and the non-volatile memory device may include various circuits for writing data to and reading data from the respective memory cell array.

The first interface circuit1225may perform high-speed interfacing, and the first memory device1220may include a volatile memory cell array supporting high-speed operations. The first memory device1220may store various information in the computing device1200. In an embodiment, the first interface circuit1225may be coupled to a high-speed extension port configured to accommodate various extension cards.

The second interface circuit1235may perform low-speed interfacing, and the second memory device1230may include a non-volatile memory cell array supporting low-speed operations. The second memory device1230may provide mass storage for the computing system1200. In an embodiment, the second memory device1230may include one or more of a floppy disc drive, a hard disc drive (HDD), an optical disc device, a tape unit, a flash memory or other similar solid-state memory devices, a storage-area network, and combinations thereof.

In some embodiments, the second interface circuit1235may be coupled to a low-speed extension port. The low-speed extension port may include any of various communication ports (e.g., USB, Bluetooth, Ethernet, Wireless Ethernet, etc.) and may be coupled to a networking device through a network adaptor.

Each of the first and second memory devices1220and1230may include a plurality of memory chips. In an embodiment, either or both of the first and second memory devices1220and1230may be implemented as a plurality of stacked dies.

The first and second memory devices1220and1230may perform recovery, including decompression, of the Tx data DQPreceived from the processor1210on the basis of the mode signal mode and the flag information CF.

The first and second interface circuits1225and1235may perform interfacing between constituent elements having different operation speeds in the computing system1200. Arrangement of the above constituent elements shown in the drawings is disclosed for illustrative purposes only, and embodiments are not limited thereto.

In an embodiment, the computing system1200may further include an input/output (I/O) unit1240. The I/O unit1240may include an input circuit such as a keyboard or mouse and an output circuit such as a printer or display.

Embodiments of the present disclosure may be implemented by a digital electronic circuit, an integrated circuit (IC), an application specific integrated circuit (ASIC) designed for special purposes, hardware, firmware, software, and/or a combination thereof.

The computing system1200may be implemented using one or more computer programs. Each computer program (also called a program, software, software application, or a code) may be implemented using one or more of machine instructions for a programmable processor, high-level procedure and/or object-oriented programming languages, and assembly/machine language.

The computer program can be executed on a programmable system. The programmable system may include at least one special-purpose or general-purpose processor, at least one input circuit, and at least one output circuit, which are coupled to a storage system for transmission/reception of data and commands.

Constituent elements of the computing system1200may be interconnected in an arbitrary format or may be interconnected by a digital data communication medium such as a communication network. The communication network may include one or more of a local area network (LAN), a Wide Area Network (WAN), and the Internet.

Apparatus and methods for processing data according to the embodiments may compress data using only the result of comparisons between pieces of the data without using additional information, and transmit the resultant compressed data, such that the data can be easily compressed and transmitted without difficulty.

Depending on whether a higher data compression rate or a higher data accuracy is desired, embodiments may selectively determine whether data will be lost during compression, and may determine one or more bits to be lost to facilitate the compression operation.

Embodiments compare contiguous data bit values with each other and compress the data bit values, resulting in a reduction of the amount of transmitted (Tx) data. Since the amount of Tx data is reduced, a load of an input/output (I/O) driver and of a channel can be reduced and a quality of the Tx data can be improved.

Embodiments perform data compression by comparing the values of pieces of data to be compressed, and no additional information is needed to perform the data compression.

Those skilled in the art will appreciate that embodiments may be carried out in ways other than those specifically set forth herein without departing from the spirit and essential characteristics of the present disclosure. The above embodiments are therefore to be construed in all aspects as illustrative, and embodiments are not limited thereby. The scope of the appended claims should be determined by the claims and their legal equivalents, not by the above description, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein. Claims that are not explicitly cited in each other in the appended claims may be presented in combination in an embodiment or may be included as a new claim by a subsequent amendment.

Although a number of embodiments have been described, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the present disclosure. Particularly, numerous variations and modifications are possible in the component parts and/or arrangements which are within the scope of the disclosure, the drawings, and the accompanying claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent in light of the disclosures and teachings herein to those skilled in the art.