Voltage supply circuit, display device, electronic equipment, and voltage supply method

A voltage supply circuit including: first and second nodes; a predetermined potential; and an output transistor having its control terminal connected to the first node, its first terminal connected to the second node and its second terminal connected to an output terminal. The circuit further includes: a switching element which turns on in response to an active reset signal to connect the potential and the first and second nodes together; a first capacitor connected to the first node and supplied with a clock; a second capacitor connected to the second node and supplied with another clock; and an adjustment section adapted to adjust the clock amplitudes so that the potentials of the first and second nodes vary with a predetermined difference maintained therebetween. The reset signal is basically reverse in phase to the clocks.

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese Patent Application JP 2006-355771 filed with the Japan Patent Office on Dec. 28, 2006, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a voltage supply circuit including components such as a DC-DC converter adapted to supply a positive or negative drive voltage to a display device driver. The present invention also relates to a display device and electronic equipment having the same and a voltage supply method using the same.

2. Description of the Related Art

An image display device such as liquid crystal display or organic EL (Electro luminescence) display has a number of pixels arranged in a matrix form. Such a display device displays an image by controlling the optical intensity of each pixel according to image information to be displayed.

In this type of display device, a power supply circuit including a DC-DC converter may be provided in the display panel.

FIG. 1is a circuit diagram illustrating a configuration example of a DC-DC converter.FIG. 2is a timing diagram of the DC-DC converter illustrated inFIG. 1.

A node A is formed by a connection point between the source of the output transistor2and the drain of the transistor3. A node B is connected to the gate of the output transistor2, the gate of the transistor3and the drain of the transistor4.

The node A is connected to a capacitor5(Cap1) supplied with a clock CKg. The node B is connected to a capacitor6(Cap2) supplied with a clock xCKg which is reverse in phase to the clock CKg.

In the DC-DC converter1, the gate and source of the output transistor2are supplied with the capacitively coupled clock pulses, thus generating a negative supply voltage Vssg.

Incidentally, the D-D converter has a CMOS configuration.

Among techniques to provide larger panel production volume is a technique in which a TFT circuit is configured using single-type transistors (transistors of identical polarity) (PMOS or NMOS).

A variety of single-type configuration circuits have been proposed for level shifter, buffer, inverter, and shift register used in this type of power supply circuit. For more information, refer to Japanese Patent Laid-Open Nos. 2005-123864, 2005-123865, 2005-143068, 2005-149624.

SUMMARY OF THE INVENTION

However, forming a panel with these circuits requires several types of power supplies.

Normally, a panel having a CMOS configuration receives two supply voltages (including GND) from external sources and generates others within itself.

This results in increased number of manufacturing processes, making it difficult to provide greater production volume.

Further, it is more advantageous in terms of cost to have a DC-DC converter in the panel rather than having one thereoutside. Therefore, it is desirable to provide a DC-DC converter in the panel even in the case of a single-type configuration.

It is desirable to provide a voltage supply circuit, a display device and electronic equipment having the same, and a voltage supply method using the same, which can be incorporated in a panel and other device formed by transistors of identical polarity and which can ensure greater production volume, reduced manufacturing processes and cost.

A voltage supply circuit according to a first embodiment of the present invention includes first and second nodes and a predetermined potential. The voltage supply circuit further includes an output transistor having its control terminal connected to the first node, its first terminal connected to the second node, and its second terminal connected to an output terminal. The voltage supply circuit still further includes a switching element which turns on in response to an active reset signal to connect the potential and the first and second nodes together. The voltage supply circuit still further includes a first capacitor connected to the first node and supplied with a clock and a second capacitor connected to the second node and supplied with another clock. The voltage supply circuit still further includes an adjustment section adapted to adjust the clock amplitudes so that the potentials of the first and second nodes vary with a predetermined difference maintained therebetween. The reset signal is basically reverse in phase to the clock.

Preferably, the adjustment section has the capability to generate first and second clocks different in amplitude from each other and feed the first clock to the first capacitor and the second clock to the second capacitor. The same section sets the first clock to an amplitude larger than that of the second clock.

Preferably, the adjustment section has an additional capacitance connected to the second node and the capability to feed a single clock in parallel to the first and second capacitors.

A display device according to a second embodiment of the present invention includes a plurality of pixel circuits arranged in a matrix manner. The display device further includes at least a scanner operable to output a drive signal adapted to drive elements forming the pixel circuits. The display device still further includes a voltage supply circuit adapted to supply a drive voltage to the scanner. The voltage supply circuit includes first and second nodes and a predetermined potential. The voltage supply circuit further includes an output transistor having its control terminal connected to the first node, its first terminal connected to the second node, and its second terminal connected to an output terminal. The voltage supply circuit still further includes a switching element which turns on in response to an active reset signal to connect the predetermined potential and the first and second nodes together. The voltage supply circuit still further includes a first capacitor connected to the first node and supplied with a clock and a second capacitor connected to the second node and supplied with another clock. The voltage supply circuit still further includes an adjustment section adapted to adjust the clock amplitudes so that the potentials of the first and second nodes vary with a predetermined difference maintained therebetween. The reset signal is basically reverse in phase to the clocks.

A third embodiment of the present invention is electronic equipment having a display device. The display device includes a plurality of pixel circuits arranged in a matrix manner. The display device further includes at least a scanner operable to output a drive signal adapted to drive elements forming the pixel circuits. The display device still further includes a voltage supply circuit adapted to supply a drive voltage to the scanner. The voltage supply circuit includes first and second nodes and a predetermined potential. The voltage supply circuit further includes an output transistor having its control terminal connected to the first node, its first terminal connected to the second node, and its second terminal connected to an output terminal. The voltage supply circuit still further includes a switching element which turns on in response to an active reset signal to connect the potential and the first and second nodes together. The voltage supply circuit still further includes a first capacitor connected to the first node and supplied with a clock and a second capacitor connected to the second node and supplied with another clock. The voltage supply circuit still further includes an adjustment section adapted to adjust the clock amplitudes so that the potentials of the first and second nodes vary with a predetermined difference maintained therebetween. The reset signal is basically reverse in phase to the clock.

A fourth embodiment of the present invention is a voltage supply method for supplying voltage using first and second capacitors and an output transistor. The first capacitor is connected to a first node and supplied with a clock. The second capacitor is connected to a second node and supplied with another clock. The output transistor has its control terminal connected to the first node, its first terminal connected to the second node, and its second terminal connected to an output terminal. The voltage supply method includes first, second and third steps. The first step connects a predetermined potential and the first and second nodes while a reset signal which is basically reverse in phase to the clock is active. The second step adjusts the clock amplitude so that the potentials of the first and second nodes vary with a predetermined difference maintained therebetween. The third step outputs a voltage commensurate with the potential of the second node from the output transistor in response to a variation in potential.

According to the embodiments of the present invention, the switching element turns on while the reset signal is active, initializing, for example, the first and second nodes to a predetermined potential level.

The first and second nodes vary in potential with change in amplitude of the first and second clocks relative to the predetermined potential.

A predetermined potential is output from the output transistor as a result of a variation in potential of the first and second nodes.

A voltage supply circuit according to one embodiment of the present invention can be incorporated in a panel formed by transistors of identical polarity, providing improved production volume and ensuring reduced manufacturing processes and cost.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIG. 3is a block diagram illustrating a configuration example of a voltage supply circuit according to a first embodiment of the present invention.FIG. 4is a circuit diagram illustrating a configuration example of a DC-DC converter according to the first embodiment.FIG. 5is a timing diagram of the voltage supply circuit according to the first embodiment.

A voltage supply circuit10according to the first embodiment includes an adjustment section11and a DC-DC converter (DDcon)12.

A denotes a first node, B a second node, ck1and ck2first and second clocks which are in phase with each other, and rst a reset signal which is basically reverse in phase to the clocks ck1and ck2.

The adjustment section11has level shifters (lvlsft)111,112and113adapted to adjust the levels of the reset signal rst and the clocks ck1and ck2.

The level shifter111shifts the amplitude of the reset signal rst to produce a signal having an intermediate amplitude between a supply voltage Vdd and a ground potential GND and supplies the signal to the DC-DC converter12.

The level shifter112shifts the amplitude of the clock ck1to produce a signal having an intermediate amplitude between the supply voltage Vdd and the ground potential GND and supplies the signal to the DC-DC converter12.

The level shifter113shifts the amplitude of the clock ck2to produce a signal having an intermediate amplitude between a supply voltage Vdd2and the ground potential GND and supplies the signal to the DC-DC converter12.

The supply voltages Vdd and Vdd2satisfy the relationship Vdd>Vdd2.

Therefore, when the first and second clocks ck1and ck2supplied to the DC-DC converter12are compared, an amplitude ΔV1of the first clock ck1is larger than an amplitude ΔV2of the second clock ck2(ΔV1>ΔV2).

For example, Vdd is set to 10V, and Vdd2to 8V.

The DC-DC converter12includes an output transistor121(p11) formed by a PMOS transistor, switching transistors (switching elements)122(p12) and123(p13) formed similarly by PMOS transistors, and first and second capacitors124and125, as illustrated inFIG. 4.

On the other hand, Vref in the figure denotes a predetermined potential. Further, C1denotes the capacitance of the first capacitor124, and C2the capacitance of the second capacitor125.

The output transistor121has its gate connected to the first node A, its source connected to the second node B, and its drain connected to an output terminal tout.

The switching transistor elements122and123have their sources connected to the predetermined potential Vref. The switching transistor122has its drain connected to the first node A. The switching transistor123has its drain connected to the second node B. The switching transistors122and123have their gates connected to an input terminal trst of the reset signal rst (output of the level shifter111).

The first capacitor124has its first electrode connected to the first node A and its second electrode connected to an input terminal tck1of the clock ck1(output of the level shifter112).

The second capacitor125has its first electrode connected to the second node B and its second electrode connected to an input terminal tck2of the clock ck2(output of the level shifter113).

In the DC-DC converter12configured as described above, the amplitudes of the clocks are adjusted by the adjustment section11so that the potential ΔV1of the first node A is larger than the potential ΔV2of the second node B.

More specifically, as described above, when the first and second clocks ck1and ck2supplied to the DC-DC converter12are compared, the amplitude ΔV1of the first clock ck1is larger than the amplitude ΔV2of the second clock ck2(ΔV1>ΔV2).

The first and second clocks ck1and ck2cause the potentials of the first and second nodes A and B to change via the first and second capacitors124and125.

As illustrated inFIG. 5, the switching transistors122and123are on while the reset pulse signal rst is at low level. This causes the first and second nodes A and B to be initialized to the predetermined potential Vref.

The first and second nodes A and B vary in potential relative to the predetermined potential Vref respectively at the amplitudes of the clocks ck1and ck2.

A negative potential Vss2is output from the output transistor121as a result of variations in potential of the first and second nodes A and B.

The negative potential Vss2is the low (Lo) potential of the second node B. A negative potential Vss3is the low (Lo) potential of the first node A.

Here, letting a threshold voltage Vth of the output transistor121be denoted by Vth(p11), the output condition of the negative potential Vss2can be expressed as follows:

Letting a parasitic capacitance of the first node A and that of the second node B be denoted respectively by Cpa and Cpb, the amplitudes ΔV1′ and ΔV2′ of the first and second nodes A and B can be determined by equations (2) and (3) given below.

Hence, the amplitudes of the clocks ck1and ck2must be determined in consideration of the relationship between the aforementioned Equations (1), (2) and (3).

Using the amplitudes ΔV1′ and ΔV2′ of the first and second nodes A and B, the drive condition of the output transistor121can be expressed as follows:

Here, if ΔV1and ΔV2are correlated with each other by using a factor k as shown below in Equation (5), the relationship as shown in Equation (6) can be obtained.

According to the first embodiment, the DC-DC converter includes the output transistor121, the switching transistors122and123, the first and second capacitors124and125and the adjustment section11. The output transistor121has its gate (control terminal) connected to the first node A, its source connected to the second node B, and its drain connected to the output terminal tout. The switching transistor122has its source connected to the predetermined potential Vref, its drain connected to the first node A, and its gate connected to the supply line of the reset signal rst. The switching transistor123has its source connected to the predetermined potential Vref, its drain connected to the second node B, and its gate connected to the supply line of the reset signal rst. The first capacitor124has its first electrode connected to the first node A and its second electrode connected to the supply line of the first clock ck1. The second capacitor125has its first electrode connected to the second node B and its second electrode connected to the supply line of the second clock ck2. The adjustment section11adjusts the amplitudes of the first and second clocks ck1and ck2so that the amplitude ΔV1of the first clock is larger than the amplitude ΔV2of the second clock and that the potentials of the first and second nodes vary in accordance with the adjusted amplitudes. The first and second clocks ck1and ck2are in phase with each other. The reset signal is basically reverse in phase to the clocks. As a result, the DC-DC converter according to the first embodiment provides the following effects.

The DC-DC converter can be formed by transistors of identical polarity such as p-channel transistors (e.g., TFTs), thus allowing to output a negative potential in an accurate manner.

This permits the DC-DC converter to be incorporated in a panel formed by transistors of identical polarity, providing improved production volume and ensuring reduced manufacturing processes and cost.

Second Embodiment

FIG. 6is a block diagram illustrating a configuration example of the voltage supply circuit according to a second embodiment of the present invention.FIG. 7is a circuit diagram illustrating a configuration example of the DC-DC converter according to the second embodiment.FIG. 8is a timing diagram of the voltage supply circuit according to the second embodiment.

A voltage supply circuit10A according to the second embodiment differs from the voltage supply circuit10according to the first embodiment in that a single clock ck is used rather than two clocks. The same circuit10A further differs from the circuit10in that the level shifter112of an adjustment section11A shifts the amplitude of the clock ck as with that of the reset signal rst to produce a signal having an intermediate amplitude between the supply voltage Vdd and the ground potential GND and supplies the signal to a DC-DC converter12A. The same circuit10A still further differs from the circuit10in that the DC-DC converter12A adjusts the clock amplitude so that the signals having different amplitudes are supplied to the first and second nodes A and B.

More specifically, as illustrated inFIG. 7, the capacitors124and125have their second electrodes connected to a clock input terminal tck. Also, a capacitor Cb is provided between the second node B and the reference potential (e.g., ground potential GND) to serve as a parasitic capacitance (capacitor).

In the DC-DC converter12A, the potentials of the first and second nodes A and B are initialized by the reset signal rst, as illustrated inFIGS. 7 and 8. Then, the potentials thereof are reduced by the coupling of the input ck using the capacitances C1and C2of the capacitors124and125.

At this time, a parasitic capacitance126(Cb) is connected to the second node B. Therefore, the coupling gain of the first and second nodes A and B is adjusted. As a result, only the low (Lo) potential of the node B is output.

Letting the parasitic capacitances of the first and second nodes A and B be denoted respectively by Cpa and Cpb, the amplitudes ΔV1′ and ΔV2′ of the first and second nodes A and B can be determined by Equations (7) and (8) given below.

Hence, the amplitudes of the clocks ck1and ck2must be determined in consideration of the relationships expressed by the Equations (1), (7) and (8).

Using the amplitudes ΔV1′ and ΔV2′ of the first and second nodes A and B, the drive condition of the output transistor121can be expressed as follows:

As a result, the relationship expressed by Equation (10) can be obtained as shown below.

Hence, it is necessary to determine Cb so that the above condition is satisfied.

The second embodiment provides the same effects as the first embodiment. Further, the voltage supply circuit according to this embodiment can be driven with two pulses (ck, rst) and three power supplies (Vdd, Vss, Vref). Using single-type CMOS transistors (PMOS and NMOS) in panel circuit design ensures reduced manufacturing processes and greater production volume.

Third Embodiment

FIG. 9is a block diagram illustrating a configuration example of the voltage supply circuit according to a third embodiment of the present invention.

A voltage supply circuit10B according to the third embodiment differs from the voltage supply circuit10according to the first embodiment in that, because the reset signal rst is reverse in phase to the first and second clocks ck1and ck2, and because the first and second clocks ck1and ck2are in phase with each other, the single clock ck is used to generate the reset signal rst and the first and second clocks ck1and ck2following the amplitude shifting.

More specifically, a level shifter111B for the reset signal rst is a level shifter with the inverting function (inverter). The clock ck is fed to three level shifters111B,112and113in parallel.

It should be noted that the inverter111B can be configured only with transistors of identical polarity, namely, PMOS transistors, as with the DC-DC converter12.

FIG. 10is a circuit diagram illustrating an example of inverter configured only with transistors of identical polarity, namely, PMOS transistors.

The transistor131has its source connected to the node ND131and its gate and drain connected to the reference potential Vss. The transistor132has its source connected to the node ND132, its drain connected to the reference potential Vss, and its gate connected to the node ND131.

The transistor133has its source connected to the supply line of the supply voltage Vdd, its drain connected to the node ND132, and its gate connected to a signal input line IN.

The capacitor134has its first electrode connected to the node ND131and its second electrode connected to the node ND132. The node ND132is connected to an output OUT.

In the inverter130configured as described above, when a low level signal is input, the transistor133turns on, raising the potential of the node ND132. This causes the potential of the node ND131to be raised via the capacitor C134, turning off the transistor132. As a result, a signal at the Vdd level is output to the output OUT.

When a high level signal is input, the transistor133turns off. This causes the potential of the node ND131to be discharged via the transistor131, turning on the transistor132. As a result, a signal at the Vss level is output to the output OUT.

Except for the above, the voltage supply circuit according to this embodiment is configured in the same manner as with that according to the first embodiment.

The third embodiment provides the same effects as the first embodiment.

Fourth Embodiment

FIG. 11is a block diagram illustrating a configuration example of the voltage supply circuit according to a fourth embodiment of the present invention.

A voltage supply circuit10C according to the fourth embodiment differs from the voltage supply circuit10A according to the second embodiment in that, because the reset signal rst is reverse in phase to the clock signal ck, the single clock ck is used to generate the reset signal rst following the amplitude shifting.

More specifically, a level shifter111C for the reset signal rst is a level shifter with the inverting function (inverter). The clock ck is fed to two level shifters111C and112in parallel.

It should be noted that the inverter111C can be configured only with transistors of identical polarity, namely, PMOS transistors, as with the DC-DC converter12A as illustrated inFIG. 10.

Except for the above, the voltage supply circuit is configured in the same manner as with that according to the second embodiment.

The fourth embodiment provides the same effects as the second embodiment.

Fifth Embodiment

FIG. 12is a block diagram illustrating a configuration example of the voltage supply circuit according to a fifth embodiment of the present invention.

A voltage supply circuit10D according to the fifth embodiment differs from the voltage supply circuit10C according to the fourth embodiment in that a delay circuit114is provided in a stage previous to the level shifter112for the clock.

The reason why the delay circuit114is provided will be described with reference toFIGS. 13 and 14.

FIG. 13is a timing diagram illustrating a case where the reset signal rst lags the clock signal ck.

FIG. 14is a timing diagram illustrating a case where the reset signal rst leads the clock signal ck.

The reset signal rst is reverse in phase to the clock ck. Therefore, the voltage supply circuit10D according to the fifth embodiment can be configured in the same manner as the voltage supply circuit10C according to the fourth embodiment.

However, caution must be exercised with the phase relationship.

If the reset signal rst lags the clock signal ck as illustrated inFIG. 13, a sufficient coupling of the clock ck cannot be achieved to reduce the potentials of the first and second nodes A and B because the switching transistors122and123illustrated inFIG. 7are both on. This makes it impossible to ensure proper operation.

In contrast, if the reset signal rst leads the clock signal ck, this does not pose any serious problem to the operation. If anything, the Lo period of the first and second nodes A and B (Vss2output period) is shorter. As a result, the supply capability of the negative supply voltage Vss2drops. Also, the floating period of the output OUT node (non-supply period of Vss2) is longer.

The Vss2potential of the output OUT node may change during the non-supply period. Therefore, the non-supply period should be as short as possible.

InFIG. 14, the non-supply period is shorter. Despite the decline in supply capability of the DC-DC converter12A, sufficient supply of Vss2can be achieved by controlling the delay of the reset signal rst relative to the clock ck with the delay circuit114. Therefore, so long as Vss2is sufficiently supplied, the voltage supply circuit10D can be used.

Except for the above, the voltage supply circuit according to this embodiment is configured in the same manner as with those according to the second and fourth embodiments.

The fifth embodiment provides the same effects as the second and fourth embodiments.

Sixth Embodiment

FIG. 15is a block diagram illustrating a configuration example of the voltage supply circuit according to a sixth embodiment of the present invention.

A voltage supply circuit10E according to the sixth embodiment differs from the voltage supply circuit10B according to the third embodiment in that the delay circuit114is provided in a stage previous to the level shifters112and113for the clocks for the same reason as described in the fifth embodiment.

It should be noted that, in the configuration illustrated inFIG. 15, it is also essential to ensure that the first and second clocks ck1and ck2remain in phase with each other.

Except for the above, the voltage supply circuit according to this embodiment is configured in the same manner as with those according to the first and third embodiments.

The sixth embodiment provides the same effects as the first and third embodiments.

Seventh Embodiment

FIG. 16is a timing diagram illustrating a configuration example of the voltage supply circuit according to a seventh embodiment of the present invention.

A voltage supply circuit10F according to the seventh embodiment differs from the voltage supply circuit10A according to the second embodiment in that the off period (high level period) of the reset signal rst is longer so that the supply period of the negative potential Vss2is not reduced by the reset signal rst timing.

Except for the above, the voltage supply circuit according to this embodiment is configured in the same manner as with that according to the second embodiment.

The seventh embodiment provides the same effects as the second embodiment.

It should be noted that this configuration is also applicable to the first embodiment.

Eighth Embodiment

FIG. 17is a block diagram illustrating a configuration example of the voltage supply circuit according to an eighth embodiment of the present invention.FIG. 18is a timing diagram of the voltage supply circuit according to the eighth embodiment.

A voltage supply circuit10G according to the eighth embodiment differs from the voltage supply circuit10C according to the fourth embodiment in that a NAND circuit function section115is provided in place of the inverting function to serve as the level shifter adapted to generate the reset signal rst so that the reset signal rst can be selectively generated from the clock ck and an enable signal en.

In this case, as illustrated inFIG. 18, the off period (high level period) of the reset signal rst is longer as with the seventh embodiment so that the reset signal rst timing can be determined as desired to ensure that the supply period of the negative potential Vss2is not reduced.

FIG. 19is a circuit diagram illustrating an example of NAND circuit configured only with transistors of identical polarity, namely, PMOS transistors.

The transistor141has its source connected to the node ND141and its gate and drain connected to the reference potential Vss. The transistor142has its source connected to the node ND142, its drain connected to the reference potential Vss and its gate connected to the node ND141.

The transistor143has its source connected to the supply line of the supply voltage Vdd, its drain connected to the node ND142and its gate connected to a signal input line IN1.

The transistor144has its source connected to the supply line of the supply voltage Vdd, its drain connected to the node ND142and its gate connected to a signal input line IN2.

The capacitor145has its first electrode connected to the node ND141and its second electrode connected to the node ND142. The node ND142is connected to the output OUT.

In the NAND circuit140configured as described above, if the two signals en and ck are both at low level, or if one of the signals is at high level and the other at low level, both or either of the transistors143and144turns on, raising the potential of the node ND142. This causes the potential of the node ND141to be raised via the capacitor145, turning off the transistor142. As a result, the reset signal rst at the Vdd level is output to the output OUT.

If the NAND circuit140receives the two signals en and ck both of which are at high level, both of the transistors143and144turn off. This causes the potential of the node ND141to be discharged via the transistor141, turning on the transistor142. As a result, the reset signal rst at the Vss level is output to the output OUT.

Except for the above, the voltage supply circuit according to this embodiment is configured in the same manner as with those according to the second and fourth embodiments.

The eighth embodiment provides the same effects as the second and fourth embodiments.

Ninth Embodiment

FIG. 20is a block diagram illustrating a configuration example of the voltage supply circuit according to a ninth embodiment of the present invention.

A voltage supply circuit10H according to the ninth embodiment differs from the voltage supply circuit10B according to the third embodiment in that the NAND circuit function section115, configured as illustrated inFIG. 19, is provided in place of the inverting function to serve as the level shifter adapted to generate the reset signal rst as in the eighth embodiment so that the reset signal rst can be selectively generated from the clock ck and the enable signal en.

Also in this case, the ninth embodiment offers the same advantage as the seventh embodiment in that the off period (high level period) of the reset signal rst is longer so that the reset signal rst timing can be determined as desired to ensure that the supply period of the negative potential Vss2is not reduced.

Except for the above, the voltage supply circuit according to this embodiment is configured in the same manner as with those according to the first and third embodiments.

The ninth embodiment provides the same effects as the first and third embodiments.

Tenth Embodiment

FIG. 21is a block diagram illustrating a configuration example of the voltage supply circuit according to a tenth embodiment of the present invention.

A voltage supply circuit10I according to the tenth embodiment differs from the voltage supply circuit10G according to the eighth embodiment in that a NOR circuit function section116is provided in place of the NAND circuit function section115to serve as the level shifter adapted to generate the reset signal rst so that the reset signal rst can be selectively generated from the clock ck and the enable signal en.

FIG. 22is a circuit diagram illustrating an example of NOR circuit configured only with transistors of identical polarity, namely, PMOS transistors.

The transistor151has its source connected to the node ND151and its gate and drain connected to the reference potential Vss. The transistor152has its source connected to the node ND152, its drain connected to the reference potential Vss and its gate connected to the node ND151.

The transistor153has its source connected to the supply line of the supply voltage Vdd, its drain connected to the source of the transistor154and its gate connected to the signal input line IN1.

The transistor154has its drain connected to the node ND152and its gate connected to the signal input line IN2.

The capacitor155has its first electrode connected to the node ND151and its second electrode connected to the node ND152. The node ND152is connected to the output OUT.

In the NOR circuit150configured as described above, if both of the two signals en and ck are at low level, both of the transistors153and154turn on, raising the potential of the node ND152. This causes the potential of the node ND151to be raised via the capacitor155, turning off the transistor152. As a result, the reset signal rst at the Vdd level is output to the output OUT.

If the NOR circuit150receives the two signals en and ck both or either of which is at high level, both or either of the transistors153and154turns off. This causes the potential of the node ND151to be discharged via the transistor151, turning on the transistor152. As a result, the reset signal rst at the Vss level is output to the output OUT.

Except for the above, the voltage supply circuit according to this embodiment is configured in the same manner as with those according to the second, fourth and eighth embodiments.

The tenth embodiment provides the same effects as the second, fourth and eighth embodiments.

Although not illustrated, a NOR circuit is applicable to the ninth embodiment in place of the NAND circuit.

Although, in the above embodiments, the cases have been described where PMOS transistors are used as transistors of identical polarity, these embodiments can be configured in the same manner with NMOS transistors. When NMOS transistors are used, a positive potential is output rather than a negative potential. Except for this, the aforementioned voltage supply circuits can be basically configured in the same manner with NMOS transistors.

Using NMOS transistors to configure a voltage supply circuit facilitates, for example, the formation of TFTs using amorphous silicon. As a result, the voltage supply circuit can be readily incorporated in a panel of an organic EL display device using the pixel circuit which will be described later.

A description will be made below about the preferred embodiments of the voltage supply circuit formed by NMOS transistors.

It should be noted that the circuit functions are basically the same. Therefore, the description will be given with emphasis on the differences from the circuits using PMOS transistors.

Eleventh Embodiment

FIG. 23is a circuit diagram illustrating a configuration example of the DC-DC converter according to an eleventh embodiment.FIG. 24is a timing diagram of the voltage supply circuit according to the eleventh embodiment.

A voltage supply circuit10J according to the eleventh embodiment differs from the voltage supply circuit10according to the first embodiment in that the PMOS transistors121,122and123have been replaced with NMOS transistors121N,122N and123N (n11to n13).

In this case, the negative potential Vss2is replaced with the positive potential Vdd2. The negative potential Vss3is replaced with a positive potential Vdd3(Vdd3>Vdd2>Vdd>Vref).

In a DC-DC converter12J configured as described above, the adjustment section11adjusts the clock amplitude so that the potential ΔV1of the first node A is larger than the potential ΔV2of the second node B.

More specifically, as described above, when the first and second clocks ck1and ck2supplied to the DC-DC converter12J are compared, the amplitude ΔV1of the first clock ck1is larger than the amplitude ΔV2of the second clock ck2(ΔV1>ΔV2).

The first and second clocks ck1and ck2cause the potentials of the first and second nodes A and B to change via the first and second capacitors124and125.

As illustrated inFIG. 24, the switching transistors122N and123N are on while the reset pulse signal rst is at low level. This causes the first and second nodes A and B to be initialized to the predetermined potential Vref.

The first and second nodes A and B vary in potential relative to the predetermined potential Vref respectively at the amplitudes of the clocks ck1and ck2.

The positive potential Vdd2is output from the output transistor121N as a result of variations in potential of the first and second nodes A and B.

The positive potential Vdd2is the high (Hi) potential of the second node B. The positive potential Vdd3is the high (Hi) potential of the first node A.

Here, letting the threshold voltage Vth of the output transistor121N be denoted by Vth(n11), the output condition of the negative potential Vss2can be expressed as follows:

Letting the parasitic capacitance of the first node A and that of the second node B be denoted respectively by Cpa and Cpb, the amplitudes ΔV1′ and ΔV2′ of the first and second nodes A and B can be determined by equations (12) and (13) given below.

Hence, the amplitudes of the clocks ck1and ck2must be determined in consideration of the relationship between the aforementioned Equations (11), (12) and (13).

Using the amplitudes ΔV1′ and ΔV2′ of the first and second nodes A and B, the drive condition of the output transistor121N can be expressed as follows:

Here, if ΔV1and ΔV2are correlated with each other by using the factor k as shown below in Equation (15), the relationship as shown in Equation (16) can be obtained.

The eleventh embodiment provides the same effects as the first embodiment. Further, the present embodiment is readily applicable to panels made of amorphous silicon, thus allowing to implement a voltage supply circuit tailored to practical use.

Twelfth Embodiment

FIG. 25is a circuit diagram illustrating a configuration example of the DC-DC converter according to a twelfth embodiment.FIG. 26is a timing diagram of the voltage supply circuit according to the twelfth embodiment.

A voltage supply circuit10K according to the twelfth embodiment differs from the voltage supply circuit10A according to the second embodiment in that the PMOS transistors121,122and123have been replaced with the NMOS transistors121N,122N and123N.

In a DC-DC converter12K configured as described above, the potentials of the first and second nodes A and B are initialized by the reset signal rst, as illustrated inFIGS. 25 and 26. Then, the potentials thereof are raised by the coupling of the input ck using the capacitances C1and C2of the capacitors124and125.

At this time, the parasitic capacitance126(Cb) is connected to the second node B. Therefore, the coupling gain of the first and second nodes A and B is adjusted. As a result, only the high (Hi) potential of the node B is output.

Letting the parasitic capacitances of the first and second nodes A and B be denoted respectively by Cpa and Cpb, the amplitudes ΔV1′ and ΔV2′ of the first and second nodes A and B can be determined by Equations (17) and (18) given below.

Hence, the amplitudes of the clocks ck1and ck2must be determined in consideration of the relationship between the aforementioned Equations (11), (17) and (18).

Using the amplitudes ΔV1′ and ΔV2′ of the first and second nodes A and B, the drive condition of the output transistor121N can be expressed as follows:

As a result, the relationship as given below by Equation (20) can be obtained.

Hence, it is necessary to determine Cb so that the above condition is satisfied.

The twelfth embodiment provides the same effects as the first embodiment. Further, the voltage supply circuit according to this embodiment can be driven with two pulses (ck, rst) and three power supplies (Vdd, Vss, Vref). Using single-type CMOS transistors (PMOS and NMOS) in panel circuit design ensures reduced manufacturing processes and greater production volume.

Thirteenth Embodiment

FIG. 27is a timing diagram for describing the voltage supply circuit according to a thirteenth embodiment of the present invention.

A voltage supply circuit10L according to the thirteenth embodiment differs from the voltage supply circuit10K according to the twelfth embodiment in that the off period (high level period) of the reset signal rst is longer so that the supply period of the negative potential Vss2is not reduced by the reset signal rst timing.

Except for the above, the voltage supply circuit according to this embodiment is configured in the same manner as with that according to the twelfth embodiment.

The thirteenth embodiment provides the same effects as the twelfth embodiment.

Although not illustrated, this configuration is applicable to the eleventh embodiment.

Fourteenth Embodiment

FIG. 28is a block diagram illustrating a configuration example of the voltage supply circuit according to a fourteenth embodiment of the present invention.FIG. 29is a timing diagram of the voltage supply circuit according to the fourteenth embodiment.

A voltage supply circuit10M according to the fourteenth embodiment differs from the voltage supply circuit10K according to the twelfth embodiment in that a NOR circuit function section116N is provided in place of the inverting function to serve as the level shifter adapted to generate the reset signal rst so that the reset signal rst can be selectively generated from the clock ck and the enable signal en.

Also in this case, the fourteenth embodiment offers the same advantage as the seventh embodiment in that the off period (high level period) of the reset signal rst is longer so that the reset signal rst timing can be determined as desired to ensure that the supply period of the negative potential Vss2is not reduced.

FIG. 30is a circuit diagram illustrating an example of NOR circuit configured only with transistors of identical polarity, namely, NMOS transistors.

A NOR circuit150N includes NMOS transistors151N to154N, a capacitor155N and nodes ND151N and ND152N, as illustrated inFIG. 30.

The transistor151N has its source connected to the node ND151N and its gate and drain connected to the supply potential Vdd. The transistor152N has its source connected to the node ND152N, its drain connected to the supply potential Vdd and its gate connected to the node ND151N.

The transistor153N has its source connected to the supply line of the reference voltage Vss, its drain connected to the source of the transistor154N and its gate connected to the signal input line IN1. The transistor154N has its drain connected to the node ND152N and its gate connected to the signal input line IN2.

The capacitor155N has its first electrode connected to the node ND151N and its second electrode connected to the node ND152N. The node ND152N is connected to the output OUT.

In the NOR circuit150N configured as described above, if both or either of the two signals en and ck is at high level, both or either of the transistors153N and154N turns on, lowering the potential of the node ND152N. This causes the potential of the node ND151N to be lowered via the capacitor155N, turning off the transistor152N. As a result, the reset signal rst at the Vss level is output to the output OUT.

If the NOR circuit150N receives the two signals en and ck both of which are at low level, both of the transistors153N and154N turn off. This causes the potential of the node ND151N to be discharged via the transistor151N, turning on the transistor152N. As a result, the reset signal rst at the Vdd level is output to the output OUT.

Except for the above, the voltage supply circuit according to this embodiment is configured in the same manner as with that according to the twelfth embodiment.

The fourteenth embodiment provides the same effects as the twelfth embodiment.

Fifteenth Embodiment

FIG. 31is a block diagram illustrating a configuration example of the voltage supply circuit according to a fifteenth embodiment of the present invention.

A voltage supply circuit10N according to the fifteenth embodiment differs from the voltage supply circuit10J according to the eleventh embodiment in that the NOR circuit function section116N is provided to serve as the level shifter adapted to generate the reset signal rst, as in the fourteenth embodiment, so that the reset signal rst can be selectively generated from the clock ck and the enable signal en.

Also in this case, the fifteenth embodiment offers the same advantage as the seventh embodiment in that the off period (high level period) of the reset signal rst is longer so that the reset signal rst timing can be determined as desired to ensure that the supply period of the negative potential Vss2is not reduced.

Except for the above, the voltage supply circuit according to this embodiment is configured in the same manner as with that according to the eleventh embodiment.

The fifteenth embodiment provides the same effects as the eleventh embodiment.

It should be noted that an inverter130N or a NAND circuit140N, each of which includes only NMOS transistors, is applicable to the fourteenth and fifteenth embodiments in place of the NOR circuit.

FIG. 32is a circuit diagram illustrating an example of inverter configured only with transistors of identical polarity, namely, NMOS transistors.

The inverter130N includes NMOS transistors131N to133N, a capacitor134N and nodes ND131N and ND132N, as illustrated inFIG. 32.

The transistor131N has its source connected to the node ND131N and its gate and drain connected to the supply potential Vdd. The transistor132N has its source connected to the node ND132N, its drain connected to the supply potential Vdd, and its gate connected to the node ND131N.

The transistor133N has its source connected to the reference potential Vss, its drain connected to the node ND132N, and its gate connected to the signal input line IN.

The capacitor134N has its first electrode connected to the node ND131N and its second electrode connected to the node ND132N. The node ND132N is connected to the output OUT.

In the inverter130N configured as described above, when a high level signal is input, the transistor133N turns on, lowering the potential of the node ND132N. This causes the potential of the node ND131N to be lowered via the capacitor C134N, turning off the transistor132N. As a result, a signal at the Vss level is output to the output OUT.

When a low level signal is input, the transistor133N turns off. This causes the potential of the node ND131N to be charged via the transistor131N, turning on the transistor132N. As a result, a signal at the Vdd level is output to the output OUT.

FIG. 33is a circuit diagram illustrating an example of NAND circuit configured only with transistors of identical polarity, namely, NMOS transistors.

A NAND circuit140N includes NMOS transistors141N to144N, a capacitor145N and nodes ND141N and ND142N as illustrated inFIG. 33.

The transistor141N has its source connected to the node ND141N and its gate and drain connected to the supply potential Vdd. The transistor142N has its source connected to the node ND142N, its drain connected to the supply potential Vdd and its gate connected to the node ND141N.

The transistor143N has its source connected to the reference potential Vss, its drain connected to the node ND142N and its gate connected to the signal input line IN1.

The transistor144N has its source connected to the supply line of the supply voltage Vdd, its drain connected to the node ND142N and its gate connected to the signal input line IN2.

The capacitor145N has its first electrode connected to the node ND141N and its second electrode connected to the node ND142N. The node ND142N is connected to the output OUT.

In the NAND circuit140N configured as described above, if the two signals en and ck are both at high level, both of the transistors143N and144N turn on, lowering the potential of the node ND142N. This causes the potential of the node ND141N to be lowered via the capacitor145N, turning off the transistor142N. As a result, the reset signal rst at the Vss level is output to the output OUT.

If the NAND circuit140N receives the two signals en and ck both or either of which is at low level, both or either of the transistors143N and144N turns off. This causes the potential of the node ND141N to be discharged via the transistor141N, turning on the transistor142N. As a result, the reset signal rst at the Vdd level is output to the output OUT.

Thus, the voltage supply circuits made up of NMOS transistors have been described up to this point. It should be noted that there are some configurations which have not been described. Needless to say, however, the configurations of the voltage supply circuits according to the first to tenth embodiments made up of PMOS transistors are applicable.

As mentioned earlier, using NMOS transistors to configure a voltage supply circuit facilitates, for example, the formation of TFTs using amorphous silicon. As a result, the voltage supply circuit can be readily incorporated in a panel of an organic EL display device using the pixel circuit which will be described later.

A description will be made below about configuration examples in which the voltage supply circuits10and10A to10N according to the preferred embodiments are used and incorporated in an organic EL display device.

Sixteenth Embodiment

FIG. 34is a block diagram illustrating the configuration of an organic EL display device using a pixel circuit according to a sixteenth embodiment of the present invention.

FIG. 35is a circuit diagram illustrating a specific configuration of the pixel circuit according to the sixteenth embodiment.

As illustrated inFIGS. 34 and 35, a display device200includes a pixel array section202having pixel circuits201arranged in an m by n matrix. The display device200further includes a horizontal selector (HSEL)203, a write scanner (WSCN)204, a power drive scanner (PDSCN)205and a voltage supply circuit (P1)206adapted to supply a drive voltage to the write scanner204. The display device200still further includes a voltage supply circuit (P2)207adapted to supply a drive voltage to the power drive scanner205and signal lines SGL201to SGL20nselected by the horizontal selector203and supplied with an input signal SIN of a data signal Vsig or an offset signal Vofs according to brightness information. The display device200still further includes scan lines WSL201to WSL20madapted to serve as drive wirings to be driven by a gate pulse (scan pulse) GP from the write scanner204. The display device200still further includes power drive lines PSL201to PSL20m. The power drive lines PSL201to PSL20mserve as drive wirings and are driven as a power signal PSG is applied thereto. The power signal PSG is selectively set to VCC (e.g., supply voltage) or VSS (e.g., negative voltage) by the power drive scanner205.

It should be noted that these components are formed, for example, on the same panel.

Although, in the pixel array section202, the pixel circuits201are arranged in an m by n matrix,FIG. 34illustrates an example in which the same circuits201are arranged in a 2 (=m) by 3 (=n) matrix for simplification of the drawing.

FIG. 35also illustrates a specific configuration of the single pixel circuit for simplification of the drawing.

As illustrated inFIG. 35, the pixel circuit201according to the present embodiment includes an n-channel TFT211serving as a drive transistor, an n-channel TFT212serving as a switching transistor and a capacitor C211. The same circuit201further includes a light emitting element213which includes an organic EL light emitting device (OLED) and first and second nodes ND211and ND212.

In the pixel circuit201, the TFT211serving as a drive transistor, the node ND211and the light emitting element (OLD)213are connected in series between the power drive line (power supply line) PSL (20lto20m) and a predetermined reference potential Vcat (e.g., ground potential).

More specifically, the light emitting element213has its cathode connected to the reference potential Vcat and its anode connected to the first node ND211. The TFT211has its source connected to the first node ND211and its drain connected to the power drive line PSL.

The TFT211has its gate connected to the second node ND212.

The capacitor C211has its first electrode connected to the first node ND211and its second electrode connected to the second node ND212.

The TFT212has its source and drain connected between the signal line SGL and the second node ND212. The TFT212has its gate connected to the scan line WSL.

As described above, in the pixel circuit201according to the sixteenth embodiment, the TFT211serving as a drive transistor has the capacitor C211connected between its gate and source. The capacitor C211serves as a pixel capacitance.

Next, a more specific operation of the above configuration will be described below with emphasis on the pixel circuit operation with reference toFIGS. 36A to 36EandFIGS. 37 to 44.

FIG. 36Aillustrates the gate pulse (scan pulse) GP applied to the scan line WSL.FIG. 36Billustrates the power signal PSG applied to the power drive line PSL.FIG. 36Cillustrates the input signal SIN applied to the signal line SGL.FIG. 36Dillustrates a potential VND212of the second node ND212.FIG. 36Eillustrates a potential VND211of the first node ND211.

First, when the EL light emitting element213emits light, the potential of the power drive line PSL is at the supply voltage VCC and the TFT212is off, as illustrated inFIGS. 36B and 37.

At this time, the TFT211serving as a drive transistor is designed to operate in the saturated region. Therefore, a current Ids flowing through the EL light emitting element213takes on a predetermined value according to a gate-to-source voltage Vgs of the TFT211.

Next, during a non-emission period, the potential of the power drive line PSL, which is the power supply line, is lowered to Vss, as illustrated inFIGS. 36B and 38. At this time, if the voltage Vss is smaller than the sum of the threshold Vthel of the EL light emitting element213and the cathode voltage Vcat, that is, if Vss<Vthel+Vcat, then the EL light emitting element213stops emitting light. This causes the power drive line PSL, which is the power supply line, to become the source of the NT211serving as a drive transistor. At this time, the anode of the EL light emitting element213(node ND211) is charged to Vss, as illustrated inFIG. 36E.

Further, as illustrated inFIGS. 36A,36C,36D,36E and39, when the potential of the signal line SGL reaches the offset voltage Vofs, the gate pulse is set to high level, turning on the TFT212and bringing the potential of the TFT211to Vofs.

At this time, the gate-to-source voltage of the TFT211takes on the value (Vofs-Vss). If this gate-to-source voltage (Vofs-Vss) of the TFT211is not greater (smaller) than its threshold voltage Vth, the threshold correction cannot be performed. Therefore, the gate-to-source voltage (Vofs-Vss) of the TFT211must be greater than its threshold voltage Vth. That is, the relationship Vofs-Vss>Vth must hold.

Then, during the threshold correction, the power signal PSG applied to the power drive line PSL is set back to the supply voltage Vcc again.

As the power drive line PSL is set to the supply voltage Vcc, the anode of the EL light emitting element213(node ND211) functions as the source of the TFT211, causing a current to flow in the direction as illustrated inFIG. 40.

The equivalent circuit of the EL light emitting element213is represented by a diode and a capacitor as illustrated inFIG. 40. Therefore, so long as the relationship Vel≦Vcat+Vthel is satisfied (so long as the leak current of the EL light emitting element213is considerably smaller than the current flowing through the TFT211), the current flowing through the TFT211is used to charge the capacitors C211and Cel.

At this time, the voltage Vel across the capacitor Cel rises with time as illustrated inFIG. 41. After elapse of a predetermined period of time, the gate-to-source voltage of the TFT211takes on the value Vth. At this time, the relationship Vel=Vofs−Vth≦Vcat+Vthel holds.

After the threshold cancellation, the potential of the signal line SGL is raised to Vsig with the TFT212left on as illustrated inFIGS. 36A,36C and42. The data signal Vsig is at the voltage level commensurate with the gray level. At this time, the gate potential of the TFT211is equal to Vsig as illustrated inFIG. 36Dbecause the TFT212is on. However, the source potential rises with time because the current Ids flows from the power drive line PSL.

At this time, so long as the source voltage of the TFT211does not exceed the sum of the threshold voltage Vtel of the EL light emitting element213and the cathode voltage Vcat (so long as the leak current of the EL light emitting element213is considerably smaller than the current flowing through the TFT211), the current flowing through the TFT211is used to charge the capacitors C211and Cel.

At this time, the threshold correction of the TFT211is already complete. Therefore, the current flowing through the TFT211reflects a mobility μ.

More specifically, as illustrated inFIG. 43, the larger the mobility μ, the larger the current flow and the faster the source voltage rises. Conversely, the smaller the mobility μ, the smaller the current flow and the slower the source voltage rises. As a result, the gate-to-source voltage of the TFT211diminishes as it reflects the mobility μ. The gate-to-source voltage will eventually be equal to Vgs in a predetermined period of time for complete correction of the mobility.

Finally, as illustrated inFIGS. 36A to 36Cand44, the gate pulse GP is switched to low level, turning off the TFT212to terminate the write operation, and causing the EL light emitting element213to emit light.

The gate-to-source voltage of the TFT211is constant. Therefore, a constant current Ids′ flows from the TFT211into the EL light emitting element213. Vel rises to a voltage Vx where the current Ids′ flows through the same element213. As a result, the same element213emits light.

Also in the present pixel circuit201, the I-V characteristic thereof changes if the emission time of the EL light emitting element213is long. As a result, the potential of a point B (node ND211) shown inFIG. 44also changes. However, the gate-to-source voltage of the TFT211is maintained constant. Therefore, the current flowing through the EL light emitting element213remains unchanged. Hence, even if the I-V characteristic of the same element213deteriorates, the constant current Ids′ continues to flow. As a result, the brightness of the same element213remains unchanged.

Thus, in the sixteenth embodiment, a description has been made about the display device200having the circuit shown inFIG. 38, namely, a 2 Tr+1 C pixel circuit which includes two transistors and one capacitor.

It should be noted, however, that the present embodiment is applicable to other display devices in addition to the display device200having the 2 Tr+1 C pixel circuit. That is, the present embodiment is also applicable to display devices having TFTs or other components separately for cancellation of the mobility or threshold, in addition to drive and switching transistors connected in series with the OLED.

A description will be made below about a configuration example of a display device having a 5 Tr+1 C pixel circuit which includes five transistors and one capacitor among the above-described display devices.

Seventeenth Embodiment

FIG. 45is a block diagram illustrating the configuration of an organic EL display device using the pixel circuit according to a seventeenth embodiment of the present invention.FIG. 46is a circuit diagram illustrating a specific configuration of the pixel circuit according to the seventeenth embodiment.

As illustrated inFIGS. 45 and 46, a display device300includes a pixel array section302having pixel circuits301arranged in an m by n matrix. The display device300further includes a horizontal selector (HSEL)303, a write scanner (WSCN)304, a drive scanner (DSCN)305, first and second auto-zero circuits (AZRD1)306and (AZRD2)307and a voltage supply circuit (P11)317adapted to supply a drive voltage to the write scanner304. The display device300still further includes a voltage supply circuit (P12)308adapted to supply a drive voltage to the drive scanner305, a voltage supply circuit (P13)309adapted to supply a drive voltage to the first auto-zero circuit (AZRD1)306and a voltage supply circuit (P14)310adapted to supply a drive voltage to the second auto-zero circuit (AZRD2)307. The display device300still further includes the signal line SGL selected by the horizontal selector303and supplied with an input signal SIN of a data signal according to brightness information. The display device300still further includes the scan line WSL adapted to serve as a second drive wiring to be selected and driven by the write scanner304and a drive line DSL adapted to serve as a first drive wiring to be selected and driven by the drive scanner305. The display device300still further includes a first auto-zero line AZL1adapted to serve as a fourth drive wiring to be selected and driven by the first auto-zero circuit306and a second auto-zero line AZL2adapted to serve as a third drive wiring to be selected and driven by the second auto-zero circuit307.

It should be noted that these components are formed, for example, on the same panel.

As illustrated inFIGS. 45 and 46, the pixel circuit301according to the seventeenth embodiment includes a p-channel TFT311, n-channel TFTs312to315and a capacitor C311. The same circuit301further includes a light emitting element316which includes an organic light emitting diode (OLED), and first and second nodes ND311and ND312.

A first switching transistor is formed by the TFT311, a second switching transistor by the TFT313, a third switching transistor by the TFT315, and a fourth switching transistor by the TFT314.

It should be noted that the supply line of the supply voltage Vcc (supply potential) corresponds to a first reference potential, and the ground potential GND to a second reference potential. Further, VSS1corresponds to a fourth reference potential, and VSS2to a third reference potential.

In the pixel circuit301, the TFT311, the TFT312serving as a drive transistor, the first node ND311and the light emitting element (OLED)316are connected in series between the first reference potential (supply potential Vcc in the present embodiment) and the second reference potential (ground potential GND in the present embodiment). More specifically, the light emitting element316has its cathode connected to the ground potential GND and its anode connected to the first node ND311. The TFT312has its source connected to the first node ND311. The TFT311has its drain connected to the drain of the TFT312and its source connected to the supply voltage Vcc.

The TFT312has its gate connected to the second node ND312. The TFT311has its gate connected to the drive line DSL.

The TFT313has its drain connected to the first node311and the first electrode of the capacitor C311. The TFT313has its source connected to a fixed potential VSS2and its gate connected to the second auto-zero line AZL2. The capacitor C311has its second electrode connected to the second node ND312.

The TFT314has its source and drain connected between the signal line SGL and the second node ND312. The TFT314has its gate connected to the scan line WSL.

Further, the TFT315has its source and drain connected between the second node ND312and the predetermined potential Vss1. The TFT315has its gate connected to the first auto-zero line AZL1.

As described above, in the pixel circuit301according to the seventeenth embodiment, the capacitor C311is connected as a pixel capacitance between the gate and source of the TFT312serving as a drive transistor. In the same circuit301, the source potential of the TFT312is connected to the fixed potential via the TFT313serving as a switching transistor during a non-emission period. Also in the same circuit301, the gate and drain of the TFT312are connected together for correction of the threshold Vth during the same period.

Next, the operation of the above configuration will be described below with emphasis on the pixel circuit operation with reference toFIGS. 47A to 47F.

FIG. 47Aillustrates a drive signal DS applied to the drive line DSL.FIG. 47Billustrates a drive signal WS (corresponds to the gate pulse GP in the sixteenth embodiment) applied to the scan line WSL.FIG. 47Cillustrates a drive signal AZ1applied to the first auto-zero line AZL1.FIG. 47Dillustrates a drive signal AZ2applied to the second auto-zero line AZL2.FIG. 47Eillustrates the potential of the second node ND312.FIG. 47Fillustrates the potential of the first node ND311.

The drive signal DS applied to the drive line DSL by the drive scanner305is maintained at high level. The drive signal WS applied to the scan line WSL by the write scanner304is maintained at low level. The drive signal AZ1applied to the auto-zero line AZL1by the auto-zero circuit306is maintained at low level. The drive signal AZ2applied to the auto-zero line AZL2by the auto-zero circuit307is maintained at high level.

As a result, the TFT313turns on. At this time, a current flows via the TFT313, lowering the source potential of the TFT312(potential of the node ND311) to VSS2. As a result, the voltage applied to the light emitting element316drops to 0 V, causing the same element316to stop emitting light.

In this case, even if the TFT314turns on, the voltage held by the capacitor C311, namely, the gate voltage of the TFT312, remains unchanged.

Next, during a non-emission period of the light emitting element316, the drive signal AZ1applied to the auto-zero line AZL1is set to high level, with the drive signal AZ2applied to the auto-zero line AZL2maintained at high level as shown inFIGS. 47C and 47D. This causes the potential of the second node ND312to drop to VSS1.

Then, after the drive signal AZ2applied to the auto-zero line AZL2is switched back to low level, the drive signal DS applied to the drive line DSL by the drive scanner305is switched to low level only for a predetermined period of time.

This causes the TFT313to turn off and the TFTs315and312to turn on. As a result, a current flows through the TFTs312and311, raising the potential of the first node.

Then, the drive signal DS applied to the drive line DSL by the drive scanner305is switched back to high level, and the drive signal AZ1back to low level.

As a result, the threshold Vth of the drive transistor TFT312is corrected, bringing the potential difference between the second and first nodes ND312and ND311equal to Vth.

After a predetermined period of time elapses in this condition, the drive signal WS applied to the scan line WSL by the write scanner304is maintained at high level for a predetermined period of time. This causes data to be written to the node ND312from the data line. While the drive signal WS is at high level, the drive signal DS applied to the drive line DSL by the drive scanner305is switched to high level. Then, the drive signal WS is switched to low level.

At this time, the TFT312turns on, and the TFT314turns off, allowing the mobility to be corrected.

In this case, the TFT314is off. The gate-to-source voltage of the TFT312is constant. Therefore, the constant current Ids flows from the TFT312into the EL light emitting element316. As a result, the potential of the first node ND311rises to the voltage Vx where the current Ids flows through the same element316, causing the same element316to emit light.

Also in the present pixel circuit, the current-to-voltage (I-V) characteristic thereof changes if the emission time of the EL light emitting element is long. As a result, the potential of the first node ND311also changes. However, the gate-to-source voltage of the TFT312is maintained constant. Therefore, the current flowing through the EL light emitting element316remains unchanged. Hence, even if the I-V characteristic of the same element316deteriorates, the constant current Ids continues to flow. As a result, the brightness of the same element316remains unchanged.

A display device having the pixel circuit driven as described above can be formed with transistors of identical polarity, namely, n-channel or p-channel transistors (e.g., TFTs), thus allowing to output a positive or negative potential in an accurate manner.

The display device according to the present embodiment can be incorporated in a panel formed by transistors of identical polarity, providing improved production volume and ensuring reduced manufacturing processes and cost.

The display device according to the present embodiment is applicable to a variety of electronic equipment as illustrated inFIG. 48. Among such electronic equipment are a display section410of a television set400as illustrated inFIG. 48A, display devices510and610of digital cameras500and camcorder600as illustrated inFIGS. 48B to 48D, a display device710of a laptop PC700as illustrated inFIG. 48Gand display sections810and910of mobile terminal devices800and900as illustrated inFIGS. 48E and 48F.