Semiconductor device and method for manufacturing the same

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-137963, filed on Jul. 23, 2018; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

BACKGROUND

For example, there is a semiconductor device that uses a nitride semiconductor. It is desirable for the semiconductor device to have stable characteristics.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes first to third electrodes, a first semiconductor layer, a second semiconductor layer, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between a position in the first direction of the first electrode and a position in the first direction of the second electrode. The first semiconductor layer includes Alx1Ga1-x1N (0<x1≤1). The first semiconductor layer includes first to fifth partial regions. A direction from the fourth partial region toward the first electrode, a direction from the fifth partial region toward the second electrode, and a direction from the third partial region toward the third electrode are aligned with a second direction crossing the first direction. The first partial region is between the fourth partial region and the third partial region in the first direction. The second partial region is between the third partial region and the fifth partial region in the first direction. The nitride layer includes silicon and nitrogen. A ratio Si/N of a concentration of silicon (Si) in the nitride layer to a concentration of nitrogen (N) in the nitride layer is not less than 0.68 and not more than 0.72. The nitride layer includes a first nitride region and a second nitride region. The second semiconductor layer includes Alx2Ga1-x2N (0<x2≤1). The second semiconductor layer includes a first semiconductor region and a second semiconductor region. The first semiconductor region is provided between the first partial region and the first nitride region in the second direction and contacts the first nitride region. The second semiconductor region is provided between the second partial region and the second nitride region in the second direction and contacts the second nitride region. The oxide layer includes silicon and oxygen. A concentration of nitrogen in the oxide layer is lower than a concentration of nitrogen in the nitride layer. The oxide layer includes first to third oxide regions. At least a portion of the first nitride region is provided between the first oxide region and the second semiconductor region. At least a portion of the second nitride region is provided between the second oxide region and the first semiconductor region. The third oxide region is provided between the third partial region and the third electrode and contacts the third partial region and the third electrode.

According to another embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include performing heat treatment of a stacked body. The stacked body includes a first semiconductor layer, a second semiconductor layer, and a nitride layer. The first semiconductor layer includes Alx1Ga1-x1N (0<x1≤1). The second semiconductor layer includes Alx2Ga1-x2N (0<x2≤1). The nitride layer includes silicon and nitrogen. The second semiconductor layer is provided between the first semiconductor layer and the nitride layer. A ratio Si/N of a concentration of silicon (Si) in the nitride layer to a concentration of nitrogen (N) in the nitride layer is not less than 0.68 and not more than 0.72. The method can include removing a portion of the nitride layer and a portion of the second semiconductor layer after the heat treatment and forming an oxide layer at a remaining portion of the nitride layer and a remaining portion of the second semiconductor layer. The oxide layer includes silicon and oxygen. A concentration of nitrogen in the oxide layer is lower than a concentration of nitrogen in the nitride layer. In addition, the method can include forming an electrode, the oxide layer being provided between the electrode and the remaining portion of the second semiconductor layer.

First Embodiment

FIG. 1is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment.

As shown inFIG. 1, the semiconductor device110according to the embodiment includes first to third electrodes51to53, a first semiconductor layer10, a second semiconductor layer20, a nitride layer30, and an oxide layer40.

The direction from the second electrode52toward the first electrode51is aligned with a first direction. The first direction is taken as an X-axis direction. One direction perpendicular to the X-axis direction is taken as a Z-axis direction. A direction perpendicular to the X-axis direction and the Z-axis direction is taken as a Y-axis direction.

The position in the first direction (the X-axis direction) of the third electrode53is between the position in the first direction of the first electrode51and the position in the first direction of the second electrode52. For example, the third electrode53is between the first electrode51and the second electrode52in the X-axis direction.

The first semiconductor layer10includes Alx1Ga1-x1N (0<x1≤1). The composition ratio x1 may be, for example, not less than 0 and not more than 0.2. The first semiconductor layer10is, for example, a GaN layer.

The first semiconductor layer10includes first to fifth partial regions p1to p5. The direction from the fourth partial region p4toward the first electrode51is aligned with the second direction. The second direction crosses the first direction (the X-axis direction). The second direction may be the Z-axis direction.

The direction from the fifth partial region p5toward the second electrode52is aligned with the second direction (e.g., the Z-axis direction) recited above. The direction from the third partial region p3toward the third electrode53is aligned with the second direction (e.g., the Z-axis direction) recited above.

The first partial region p1is between the fourth partial region p4and the third partial region p3in the first direction (the X-axis direction). The second partial region p2is between the third partial region p3and the fifth partial region p5in the first direction (the X-axis direction).

The nitride layer30includes silicon and nitrogen. The ratio Si/N of the concentration of silicon (Si) in the nitride layer30to the concentration of nitrogen (N) in the nitride layer30is not less than 0.68 and not more than 0.72. The nitride layer30is a “N-rich layer.” The nitride layer30includes a first nitride region31and a second nitride region32.

The second semiconductor layer20includes Alx2Ga1-x2N (0<x2≤1). The composition ratio x2 is, for example, not less than 0.05 and not more than 0.35. The second semiconductor layer20is, for example, an AlGaN layer.

The second semiconductor layer20includes a first semiconductor region21and a second semiconductor region22. The first semiconductor region21is provided between the first partial region p1and the first nitride region31in the second direction (e.g., the Z-axis direction). The first semiconductor region21contacts the first nitride region31. The second semiconductor region22is provided between the second partial region p2and the second nitride region32in the second direction (e.g., the Z-axis direction). The second semiconductor region22contacts the second nitride region32.

The oxide layer40includes silicon and oxygen. The concentration of nitrogen in the oxide layer40is lower than the concentration of nitrogen in the nitride layer30. The oxide layer40is, for example, a SiO2layer. The oxide layer40includes first to third oxide regions41to43. At least a portion of the first nitride region31is provided between the first oxide region41and the first semiconductor region21. At least a portion of the second nitride region32is provided between the second oxide region42and the second semiconductor region22. The third oxide region43is provided between the third partial region p3and the third electrode53.

For example, the at least a portion of the first nitride region31recited above contacts the first oxide region41. For example, the at least a portion of the second nitride region32recited above contacts the second oxide region42. For example, the third oxide region43contacts the third partial region p3and the third electrode53.

A substrate5sand a buffer layer5bare provided in the example. The buffer layer5bis provided between the substrate5sand the first semiconductor layer10. The substrate5smay be, for example, a sapphire substrate. The substrate5smay be, for example, a silicon substrate. The buffer layer5bmay include, for example, multiple nitride layers. For example, multiple nitride layers that have different compositions may be stacked in the buffer layer5b.

For example, the buffer layer5bis provided on the substrate5s. The first semiconductor layer10is provided on the buffer layer5b. The second semiconductor layer20is provided on the first semiconductor layer10. The nitride layer30is provided on a portion of the second semiconductor layer20. The third oxide region43of the oxide layer40is provided on another portion of the second semiconductor layer20. The third electrode53is provided on the third oxide region43. For example, the first electrode51is electrically connected to a portion (the first semiconductor region21) of the second semiconductor layer20. For example, the second electrode52is electrically connected to another portion (the second semiconductor region22) of the second semiconductor layer20.

For example, the first electrode51functions as a drain electrode. For example, the second electrode52functions as a source electrode. For example, the third electrode53functions as a gate electrode. At least a portion (e.g., the third oxide region43) of the oxide layer40functions as a gate insulating film.

For example, the current that flows between the first electrode51and the second electrode52can be controlled according to the potential of the third electrode53. The semiconductor device110is, for example, a HEMT (high-electron mobility transistor). For example, the semiconductor device110may have a normally-off operation.

In the semiconductor device110according to the embodiment as described above, the “N-rich” nitride layer30is provided as a layer contacting the second semiconductor layer20. The ratio Si/N of the nitride layer30is not less than 0.68 and not more than 0.72. Stable characteristics are obtained thereby. For example, a stable current is obtained. For example, a high breakdown voltage is obtained. Examples of the characteristics of the semiconductor device110are described below.

As shown inFIG. 1, at least a portion of the third oxide region43may be provided between the first semiconductor region21and the second semiconductor region22in the first direction (the X-axis direction). For example, a portion of the third oxide region43may be between the first partial region p1and the second partial region p2in the first direction (the X-axis direction). A high threshold voltage is obtained by such a configuration. For example, a normally-off operation is obtained easily.

In the example, the third electrode53includes first to third electrode regions53ato53c. The position in the first direction (the X-axis direction) of the third electrode region53cis between the position in the first direction of the first electrode region53aand the position in the first direction of the second electrode region53b.

On the other hand, the oxide layer40may include a fourth oxide region44and a fifth oxide region45in addition to the first to third oxide regions41to43.

The nitride layer30may further include a third nitride region33and a fourth nitride region34. The third nitride region33is positioned between the first nitride region31and the second nitride region32in the first direction (the X-axis direction). The fourth nitride region34is positioned between the third nitride region33and the second nitride region32in the first direction (the X-axis direction).

The fourth oxide region44is between the third nitride region33and the first electrode region53ain the second direction (e.g., the Z-axis direction). The fifth oxide region45is between the fourth nitride region34and the second electrode region53bin the second direction.

The third oxide region43is provided between the third partial region p3and the third electrode region53c.

The thicknesses along the second direction (the Z-axis direction) of the first to fifth oxide regions41to45are respectively taken as thicknesses t1to t5. In one example, the thickness t3along the second direction of the third oxide region43may be thinner than the thickness t4along the second direction of the fourth oxide region44. The thickness t3may be thinner than the thickness t5along the second direction of the fifth oxide region45.

For example, the thickness t3is set to obtain the target threshold voltage. In one example, the thickness t3is, for example, not less than 25 nm and not more than 35 nm.

On the other hand, the electric field of the fourth oxide region44and the fifth oxide region45can be reduced by increasing the thickness t4and the thickness t5. For example, the breakdown voltage can be increased. For example, fluctuation of the characteristics due to a continuous operation for a long period of time or breakdown of the fourth oxide region44and the fifth oxide region45can be suppressed.

For example, the first thickness t1and the second thickness t2each are, for example, not less than 25 nm and not more than 100 nm. The first thickness t1may be the same as the fourth thickness t4. The second thickness t2may be the same as the fifth thickness t5. As described below, these thicknesses may be different from each other.

The length along the first direction (the X-axis direction) of the first electrode region53ais taken as a length L1. If the length L1is excessively long, the electric field between the first electrode51and the first electrode region53abecomes excessively high. Thereby, for example, there are cases where fluctuation of the characteristics occurs easily. If the length L1is excessively short, the function of the first electrode region53aas a field plate becomes small. The fluctuation of the characteristics can be suppressed by appropriately setting the length L1.

In one example, the length L1is 5 μm or less. The length L1along the first direction of the first electrode region53amay be not less than 0.035 times and not more than 0.35 times a length LD along the first direction between the first electrode region53aand the first electrode51.

In the embodiment, for example, the thickness of the nitride layer30is thinner than the thickness t3of the third oxide region43. The thickness along the second direction (e.g., the Z-axis direction) of the first nitride region31is taken as a first thickness t31. The thickness along the second direction (e.g., the Z-axis direction) of the second nitride region32is taken as a second thickness t32. For example, the first thickness t31and the second thickness t32each are thinner than the thickness t3. An example of the relationship between the characteristics and the first thickness t31and the second thickness t32is described below.

An example of experimental results relating to the characteristics of the nitride layer30will now be described. In the experiment described below, samples that include a MIS (metal-insulator semiconductor) are evaluated. The samples include a silicon substrate, a nitride layer provided on the silicon substrate, and an electrode provided on the nitride layer. The nitride layer includes silicon and nitrogen. A voltage that is positive when referenced to the silicon substrate is applied to the electrode. A current (a leakage current) that flows between the silicon substrate and the electrode is measured.

FIG. 2is a graph illustrating a characteristic of the nitride layer.

The horizontal axis ofFIG. 2is an electric field EF (MV/cm). The product of the electric field EF and the thickness of the nitride layer corresponds to the applied voltage. The vertical axis is a leakage current IL (A). The result of a first measurement MS-1and the result of a second measurement MS-2are shown inFIG. 2. For the first measurement MS-1, the measurement is performed after making the sample and before performing heat treatment. For the second measurement MS-2, the measurement is performed after making the sample and after performing the heat treatment. The heat treatment is performed in a nitrogen atmosphere for 5 minutes at 700° C.

As shown inFIG. 2, the leakage current IL increases as the electric field EF increases. Compared to the first measurement MS-1before the heat treatment is performed, the leakage current IL is larger for the second measurement MS-2measured after the heat treatment is performed.

The results ofFIG. 2are for samples having the MIS structure. For example, in a semiconductor device that uses a nitride semiconductor, fluctuation of the characteristics, breakdown of the device, etc., occur easily when the leakage current IL is large.

Generally, in a semiconductor device that uses a semiconductor such as Si, SiC, etc., a silicon oxide film that is obtained by thermal oxidation of the surface portion of these semiconductors can be used as an insulating film. Conversely, in a semiconductor device that uses a nitride semiconductor including AlGaN, etc., it is difficult to use an oxide film made by thermal oxidation as the insulating film.

Therefore, in a semiconductor device that uses a nitride semiconductor including AlGaN, etc., a film that includes silicon or the like is formed as the insulating film by CVD (chemical vapor deposition), etc. Many impurities are included in films formed by CVD, etc. Therefore, to remove the impurities, heat treatment is performed after the film is formed.

However, as shown inFIG. 2, it was found that the leakage current IL increases when the heat treatment is performed. It is considered that, for example, the quality of the nitride layer changes due to the heat treatment. For example, there is a possibility that the quality of the interface between the nitride layer and the AlGaN layer degrades due to the heat treatment.

There is a possibility that the increase of the leakage current IL is related to the amount of dangling bonds inside the nitride layer. There is a possibility that the amount of dangling bonds inside the nitride layer is related to the ratio of silicon and nitrogen in the nitride layer.

An example of the measurement results of the relationship between the dangling bonds and a composition ratio R1(Si/N) of the nitride layer will now be described. In the following samples, a nitride layer that includes silicon and nitrogen is formed by CVD on a GaN layer. The composition ratio R1(Si/N) of the nitride layer is controlled by the flow rate of ammonia when forming the nitride layer.

FIG. 3is a graph illustrating a characteristic of the nitride layer.

The horizontal axis ofFIG. 3is the composition ratio R1(Si/N). The composition ratio R1(Si/N) is the ratio of the concentration of silicon (Si) in the nitride layer to the concentration of nitrogen (N) in the nitride layer. The stoichiometric composition of silicon nitride is Si3N4. The composition ratio R1(Si/N) in the stoichiometric composition of silicon nitride is 0.75. The composition ratio R1(Si/N) is silicon-rich (“Si-rich”) when greater than 0.75. The composition ratio R1(Si/N) is nitrogen-rich (“N-rich”) when less than 0.75. The vertical axis ofFIG. 3is a concentration C1(×1018cm−3) of the dangling bonds. The dangling bond concentration C1is measured by ESR (Electron Spin Resonance).

FIG. 3illustrates the result of the first measurement MS-1(the measurement before the heat treatment) and the result of the second measurement MS-2(the measurement after the heat treatment).

It can be seen fromFIG. 3that the dangling bond concentration C1is different between the first measurement MS-1and the second measurement MS-2. When the composition ratio R1(Si/N) is high (e.g., 0.94), the dangling bond concentration C1is higher for the second measurement MS-2(the measurement after the heat treatment) than for the first measurement MS-1(the measurement before the heat treatment).

Conversely, it was found that when the composition ratio R1(Si/N) is low (e.g., 0.7), the dangling bond concentration C1is lower for the second measurement MS-2(the measurement after the heat treatment) than for the first measurement MS-1(the measurement before the heat treatment). The dangling bond concentration C1after the heat treatment is performed can be reduced by reducing the composition ratio R1(Si/N) to be nitrogen-rich.

FIG. 4is a graph illustrating a characteristic of the nitride layer.

The horizontal axis ofFIG. 4is the composition ratio R1(Si/N). The vertical axis ofFIG. 4is a concentration BC (Si—H) (cm−3) of the bond (Si—H) of Si and hydrogen in the nitride layer. The concentration BC (Si—H) of the bond of Si and hydrogen is evaluated using FT-IR (Fourier Transform Infrared Spectroscopy).FIG. 4corresponds to the result before the heat treatment.

As shown inFIG. 4, the concentration BC (Si—H) of the bond of Si and hydrogen decreases as the composition ratio R1(Si/N) decreases.

For example, many Si—H groups exist inside a “Si-rich” nitride layer. Si—H bonds are broken by the heat treatment; and the hydrogen (H) is consumed. It is considered that many unbonded defects (dangling bonds) are formed in the remaining Si. For example, it is considered that the leakage current increases easily due to the dangling bonds.

For example, it is considered that the desorption of Ga or nitrogen occurs easily at the interface between the nitride layer and the AlGaN layer in the “Si-rich” nitride layer. It is considered that the dangling bonds increase easily at the interface. It is considered that the reliability degrades easily thereby.

The concentration BC (Si—H) of the Si—H groups is lower in the “N-rich” nitride layer. For example, it is considered that the leakage current can be suppressed thereby. In the “N-rich” nitride layer, the consumption of the Ga or the nitrogen at the interface between the nitride layer and the AlGaN layer can be suppressed. For example, the dangling bonds at the interface are suppressed. For example, high reliability is obtained.

An example of measurement results of the relationship between the composition ratio of the nitride layer and the current flowing in the nitride layer will now be described. The samples described below have a MIS structure. In the MIS structure, a nitride layer that includes silicon and nitrogen is formed by CVD on a GaN layer. The composition ratio R1(Si/N) of the nitride layer is controlled by the flow rate of ammonia when forming the nitride layer. An electrode is provided on the nitride layer. A voltage is applied between the GaN layer and the electrode; and the current that flows at this time is measured. The current is measured for a positive and negative voltage (electric field) with respect to the GaN layer. The characteristics when positive correspond to a forward breakdown voltage test of the semiconductor device. The characteristics when negative correspond to a reverse breakdown voltage test of the semiconductor device.

FIG. 5is a graph illustrating a characteristic of the nitride layer.

The horizontal axis ofFIG. 5is the electric field EF (MV/cm). The vertical axis is a current density CD (A/cm2).FIG. 5shows measurement results relating to a “Si-rich” sample, a “N-rich” sample, and a “Stoich” sample. In the “Si-rich” sample, the composition ratio R1(Si/N) is 0.94. In the “N-rich” sample, the composition ratio R1(Si/N) is 0.69. In the “Stoich” sample, the composition ratio R1(Si/N) is 0.76. The composition ratios are measured by RBS (Rutherford Backscattering Spectrometry).

As shown inFIG. 5, the current density CD is lower for the “N-rich” sample and the “Stoich” sample compared to the “Si-rich” sample.

For the positive electric field EF, the current density CD increases abruptly when the electric field EF is about 10 MV/cm for all of the samples. The abrupt increase of the current density CD corresponds to element breakdown. The resistance to the positive electric field EF is substantially independent of the composition ratio R1(Si/N).

On the other hand, for the negative electric field EF, an abrupt increase of the current density CD is not observed for the “N-rich” sample and the “Stoich” sample. Conversely, for the “Si-rich” sample, the current density CD increases abruptly when the electric field EF is about −12 MV/cm.

Thus, good voltage tolerance is obtained for the “N-rich” sample and the “Stoich” sample.

As recited above, the dangling bond concentration C1after the heat treatment is low for the “N-rich” nitride layer (referring toFIG. 3). For example, the concentration BC (Si—H) of the Si—H groups is low for the “N-rich” nitride layer (referring toFIG. 4). Further, good voltage tolerance is obtained is for the “N-rich” nitride layer (referring toFIG. 5). For example, element breakdown is suppressed. For example, a semiconductor device that has stable characteristics can be provided.

A relationship between the composition ratio of the nitride layer and the characteristics of the semiconductor device using the nitride layer will now be described. The semiconductor device has the configuration described in reference toFIG. 1. The composition ratio R1(Si/N) is modified for the nitride layer30described in reference toFIG. 1.

FIG. 6is a graph illustrating a characteristic of the semiconductor device.

The horizontal axis ofFIG. 6is a drain voltage VD (V). The drain voltage VD corresponds to the voltage applied to the first electrode51. The vertical axis is a drain current ID (A).FIG. 6shows measurement results relating to the “Si-rich” sample, the “N-rich” sample, and the “Stoich” sample. In the “Si-rich” sample, the composition ratio R1(Si/N) is 0.94. In the “N-rich” sample, the composition ratio R1(Si/N) is 0.69. In the “Stoich” sample, the composition ratio R1(Si/N) is 0.76.FIG. 6shows the measurement results after the heat treatment.

As shown inFIG. 6for the “Si-rich” sample, the drain current ID is large when the drain voltage VD is low. The drain current ID increases abruptly when the drain voltage VD is about 30 V. The abrupt increase corresponds to the breakdown of the semiconductor device.

As shown inFIG. 6for the “Stoich” sample, the drain current ID becomes large when the drain voltage VD exceeds about 52 V. The drain current ID increases abruptly when the drain voltage VD is about 120 V. The abrupt increase corresponds to the breakdown of the semiconductor device.

Conversely, as shown inFIG. 6for the “N-rich” sample, the drain current ID is small even when the drain voltage VD increases. Thus, a high breakdown voltage is obtained for the “N-rich” sample.

For example, it is considered that by using a “N-rich” film as the nitride layer30, the dangling bonds (the defects) inside the nitride layer30can be low. It is considered that the leakage current is suppressed thereby. For example, the reverse leakage is suppressed even after the heat treatment. For example, a good device breakdown voltage is obtained even after the heat treatment.

For example, it is considered that the “N-rich” film suppresses the desorption of nitrogen from the second semiconductor layer20(e.g., the AlGaN layer). For example, it is considered that interface defects are reduced. It is considered that by reducing the interface defects, for example, the reverse leakage is suppressed. The interface defects are reduced. A good device breakdown voltage is obtained.

An example of current collapse will now be described. For example, in a GaN power device, the on-resistance may increase when voltage stress is continuously applied to the drain electrode. The phenomenon of the on-resistance increasing due to the drain voltage stress is, for example, current collapse.

FIG. 7is a graph illustrating a characteristic of the semiconductor device.

The horizontal axis ofFIG. 7is the drain voltage VD (V) used as the stress. The vertical axis is a resistance increase rate CC1. The resistance increase rate CC1is the ratio of the resistance when stress is applied to the resistance when stress is not applied (when the drain voltage VD is 0). As shown inFIG. 7, the resistance increase rate CC1increases as the drain voltage VD which is the stress increases.

The inventor discovered by experiments that the resistance increase rate CC1changes according to the formation conditions of the nitride layer30. Measurement results of the resistance increase rate CC1when changing the flow rate of ammonia which is one source gas when forming the nitride layer30will now be described. The samples have the configuration illustrated inFIG. 1.

FIG. 8is a graph illustrating a characteristic of the semiconductor device.

The horizontal axis ofFIG. 8is a flow rate FL (sccm) of ammonia when forming the nitride layer30. The vertical axis is the resistance increase rate CC1. In the example, the drain voltage VD which is the stress is 175 V. A “N-rich” film is obtained when the flow rate FL of ammonia is large. A “Si-rich” film is obtained when the flow rate FL of ammonia is small. It can be seen fromFIG. 8that it was found that a low resistance increase rate CC1is obtained for the “N-rich” nitride layer30when the flow rate FL of ammonia is large.

FIG. 9is a graph illustrating a characteristic of the semiconductor device.

The horizontal axis ofFIG. 9is the composition ratio R1(Si/N) of the nitride layer30. The vertical axis is the resistance increase rate CC1. In the example, the drain voltage VD which is the stress is 175 V. The samples have the configuration illustrated inFIG. 1.

It can be seen fromFIG. 9that the resistance increase rate CC1decreases as the composition ratio R1(Si/N) of the nitride layer30decreases. The decrease of the resistance increase rate CC1is pronounced when the composition ratio R1(Si/N) is 0.722 or less.

In the embodiment, it is favorable for the composition ratio R1(Si/N) of the nitride layer30to be 0.722 or less. It is more favorable for the composition ratio R1(Si/N) to be 0.72 or less. It is more favorable for the composition ratio R1(Si/N) to be 0.702 or less. A low resistance increase rate CC1is obtained.

It is considered that the interface state between the second semiconductor layer20(the AlGaN layer) and the nitride layer30is reduced by setting the composition ratio R1(Si/N) of the nitride layer30to be less than 0.75 (e.g., 0.722 or less, etc.). It is considered that the resistance increase rate CC1can be reduced thereby. For example, the current collapse is suppressed.

PBTI (Positive Bias Temperature Instability) will now be described. A positive voltage (e.g., +10 V or the like) is applied to the gate electrode (e.g., the third electrode53) of a GaN power device in the on-state. At this time, PBTI occurs; for example, the threshold voltage fluctuates (e.g., decreases). An example of evaluation results of PBTI will now be described.

FIG. 10is a graph illustrating a characteristic of the semiconductor device.

The horizontal axis ofFIG. 10is a gate stress time ts (s). The vertical axis is a threshold voltage fluctuation amount ΔVth1(V). The threshold voltage fluctuation amount ΔVth1is the absolute value of the difference between the threshold voltage when the gate stress time ts is 0 and the threshold voltage after the gate stress is applied.FIG. 10illustrates the measurement result of the “Si-rich” sample, the measurement result of the “N-rich” sample, and the measurement result of the “Stoich” sample.

It can be seen fromFIG. 10that the threshold voltage fluctuation amount ΔVth1(the absolute value) is small for the “Si-rich” sample and the “Stoich” sample. The threshold voltage fluctuation amount ΔVth1(the absolute value) is large for the “N-rich” sample. Thus, in the case of the “N-rich” nitride layer30, the PBTI characteristic may be low.

An example of evaluation results of the relationship between the PBTI characteristic and the composition ratio R1(Si/N) of the nitride layer30will now be described.

FIG. 11is a graph illustrating a characteristic of the semiconductor device.

The horizontal axis ofFIG. 11is the composition ratio R1(Si/N) of the nitride layer30. The vertical axis is the threshold voltage fluctuation amount ΔVth1(V).FIG. 11shows the results when gate stress is applied at room temperature.

It can be seen fromFIG. 11that the threshold voltage fluctuation amount ΔVth1(V) becomes large when the composition ratio R1(Si/N) is excessively low. It is favorable for the composition ratio R1(Si/N) to be 0.67 or more. It is more favorable for the composition ratio R1(Si/N) to be 0.68 or more. It is more favorable for the composition ratio R1(Si/N) to be 0.69 or more. For example, fluctuation of the threshold voltage can be suppressed.

In the embodiment, it is favorable for the composition ratio R1(Si/N) to be, for example, not less than 0.68 and not more than 0.72. The fluctuation of the threshold voltage can be suppressed while suppressing the current collapse. In the embodiment, it is more favorable for the composition ratio R1(Si/N) to be not less than 0.69 and not more than 0.71. The fluctuation of the threshold voltage can be suppressed further while further suppressing the current collapse (the resistance increase rate CC1).

An example of a characteristic when changing the thickness of the nitride layer30will now be described. The samples described below have the configuration illustrated inFIG. 1. The composition ratio R1(Si/N) of the nitride layer30is 0.69.

FIG. 12is a graph illustrating a characteristic of the semiconductor device.

The horizontal axis ofFIG. 12is a thickness t30(nm) of the nitride layer30. For example, the thickness t30corresponds to the first thickness t31(referring toFIG. 1). The thickness t30is substantially the same as the second thickness t32(referring toFIG. 1). The vertical axis ofFIG. 12is the resistance increase rate CC1when applying the drain voltage stress. As shown inFIG. 12, the resistance increase rate CC1increases as the thickness t30increases.

In the embodiment, it is favorable for the thickness t30to be 10 nm or less. The thickness t30may be 5 nm or less. For example, the resistance increase rate CC1can be suppressed.

In the embodiment, it is favorable for the first thickness t31along the second direction (e.g., the Z-axis direction) of the first nitride region31to be, for example, 10 nm or less. The first thickness t31may be 5 nm or less. It is favorable for the first thickness t31to be 0.2 nm or more. For example, a uniform layer is obtained easily by setting the first thickness t31to be 0.2 nm or more. For example, the oxidization of the AlGaN layer (the second semiconductor layer20) provided under the nitride layer30is suppressed easily.

FIG. 13is a graph illustrating a characteristic of the semiconductor device.

The horizontal axis ofFIG. 13is the length L1(μm) along the first direction (the X-axis direction) of the first electrode region53a. For example, the length L1corresponds to the overlap length. In the example, the length LD along the first direction between the first electrode region53aand the first electrode51(referring toFIG. 1) is 14 μm. The vertical axis ofFIG. 13is the resistance increase rate CC1when the drain voltage stress is applied.FIG. 13shows the characteristic when the drain voltage VD which is the stress is 125 V and the characteristic when the drain voltage VD is 175 V.

It can be seen fromFIG. 13that a low resistance increase rate CC1is obtained when the length L1is short. The decrease is pronounced when the drain voltage VD which is the stress is high.

In the embodiment, it is favorable for the length L1to be 5 μm or less. It is favorable for the ratio of the length L1to the length LD to be, for example, 0.35 or less. A low resistance increase rate CC1is obtained.

FIG. 14is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

As shown inFIG. 14, the semiconductor device111according to the embodiment also includes the first to third electrodes51to53, the first semiconductor layer10, the second semiconductor layer20, the nitride layer30, and the oxide layer40. In the semiconductor device111, the position of the lower end of the third electrode53is lower than that of the semiconductor device110. Otherwise, the configuration of the semiconductor device111is similar to the configuration of the semiconductor device110. An example of the third electrode53of the semiconductor device111will now be described.

As shown inFIG. 14, a portion of the third electrode region53cis between at least a portion of the first semiconductor region21and at least a portion of the second semiconductor region22in the first direction (the X-axis direction). For example, the lower end of the third electrode region53cmay be positioned lower than the upper end of the second semiconductor layer20. For example, the target threshold voltage is obtained easily. For example, a normally-off element is obtained easily.

FIG. 15is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

As shown inFIG. 15, the semiconductor device112according to the embodiment also includes the first to third electrodes51to53, the first semiconductor layer10, the second semiconductor layer20, the nitride layer30, and the oxide layer40. In the semiconductor device112, the oxide layer40includes a first oxide film40A and a second oxide film40B. Otherwise, the configuration of the semiconductor device112is similar to the configuration of the semiconductor device110. An example of the oxide layer40of the semiconductor device112will now be described.

As shown inFIG. 15, the oxide layer40includes the first oxide film40A and the second oxide film40B. The second oxide film40B is provided between the first oxide film40A and the nitride layer30. The first oxide film40A and the second oxide film40B each are, for example, silicon oxide films. The boundary between the first oxide film40A and the second oxide film40B may not be distinct.

For example, the second oxide film40B is formed on the nitride layer30. For example, the first oxide film40A is formed on the third partial region p3and the second oxide film40B.

The first oxide film40A and the second oxide film40B are used as the first oxide region41above the first nitride region31. The first oxide film40A and the second oxide film40B are used as the second oxide region42above the second nitride region32. In the example, the second oxide film40B is not provided between the third partial region p3and the third electrode.

The thickness of the second oxide film40B is, for example, not less than 30 nm and not more than 100 nm.

In such a configuration, the thickness of the oxide layer40is different by location. The thickness t3along the second direction (e.g., the Z-axis direction) of the third oxide region43is thinner than the thickness t4along the second direction of the fourth oxide region44. The absolute value of the difference between the thickness t3and the thickness t4is, for example, not less than 30 nm and not more than 100 nm. The thickness t3of the third oxide region43may be thinner than the thickness t1along the second direction of the first oxide region41. The absolute value of the difference between the thickness t3and the thickness t1is, for example, not less than 30 nm and not more than 100 nm. The thickness t3of the third oxide region43may be thinner than the thickness t5along the second direction of the fifth oxide region45. The absolute value of the difference between the thickness t3and the thickness t5is, for example, not less than 30 nm and not more than 100 nm. The thickness t3of the third oxide region43may be thinner than the thickness t2along the second direction of the second oxide region42. The absolute value of the difference between the thickness t3and the thickness t2is, for example, not less than 30 nm and not more than 100 nm.

In the semiconductor device112, the thickness t4of the fourth oxide region44(the oxide layer40at the portion corresponding to the first electrode region53a) is thicker than the thickness t3of the third oxide region43(the portion corresponding to the third electrode region53c). The electric field in the fourth oxide region44is suppressed thereby. Thereby, the degradation of the characteristics of the fourth oxide region44, etc., can be suppressed. For example, the characteristic fluctuation due to PBTI, etc., can be suppressed.

FIG. 16is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

As shown inFIG. 16, the semiconductor device113according to the embodiment also includes the first to third electrodes51to53, the first semiconductor layer10, the second semiconductor layer20, the nitride layer30, and the oxide layer40. A first intermediate region35aand a second intermediate region35bare further provided in the semiconductor device113. Otherwise, the configuration of the semiconductor device113is similar to the configuration of the semiconductor device112. An example of the first intermediate region35aand the second intermediate region35bof the semiconductor device113will now be described.

As shown inFIG. 16, the first intermediate region35ais provided between the first nitride region31and the first oxide region41. The second intermediate region35bis provided between the second nitride region32and the second oxide region42. In an example, the first intermediate region35aincludes silicon, oxygen, and nitrogen. The second intermediate region35bincludes silicon, oxygen, and nitrogen. The first intermediate region35aand the second intermediate region35b(the intermediate region35) are, for example, a SiON region. In another example, the first intermediate region35aincludes aluminum and nitrogen. The second intermediate region35bincludes aluminum and nitrogen. The first intermediate region35aand the second intermediate region35b(the intermediate region35) are, for example, an AlN region. Thus, the first intermediate region may include one of a first material or a second material. The first material includes silicon, oxygen, and nitrogen. The second material includes aluminum and nitrogen. The second intermediate region includes the one of the first material or the second material. Such an intermediate region35may be provided between the nitride layer30and the oxide layer40.

FIG. 17is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment.

As shown inFIG. 17, the semiconductor device114according to the embodiment also includes the first to third electrodes51to53, the first semiconductor layer10, the second semiconductor layer20, the nitride layer30, and the oxide layer40. In the semiconductor device114, the second oxide film40B is provided at a portion of the nitride layer30. Otherwise, the configuration of the semiconductor device114is similar to the configuration of the semiconductor device112. An example of the second oxide film40B of the semiconductor device114will now be described.

A portion of the second oxide film40B is provided between the first electrode region53aand the first nitride region31in the second direction (e.g., the Z-axis direction). Another portion of the second oxide film40B is provided between the second electrode region53band the second nitride region32in the second direction (e.g., the Z-axis direction).

Thereby, for example, the thickness t4along the second direction (e.g., the Z-axis direction) of the fourth oxide region44is locally thick. For example, the thickness t5along the second direction (e.g., the Z-axis direction) of the fifth oxide region45is locally thick.

For example, the thickness t4is thicker than the thickness t1along the second direction (e.g., the Z-axis direction) of the first oxide region41. The thickness t5is thicker than the thickness t2along the second direction of the second oxide region42.

In the semiconductor device114, the thickness t4of the fourth oxide region44is thicker than the thickness t3of the third oxide region43. The electric field in the fourth oxide region44is suppressed thereby. Thereby, the degradation of the characteristics of the fourth oxide region44, etc., can be suppressed. For example, the characteristic fluctuation due to PBTI, etc., can be suppressed. The thickness t5is thicker than the thickness t3of the third oxide region43. The electric field in the fifth oxide region45is suppressed thereby. Thereby, the degradation of the characteristics of the fifth oxide region45, etc., can be suppressed. For example, the characteristic fluctuation due to PBTI, etc., can be suppressed.

For example, the difference between the thickness t4and the thickness t1is not less than 30 nm and not more than 100 nm. For example, the difference between the thickness t5and the thickness t2is not less than 30 nm and not more than 100 nm.

FIG. 18is a graph illustrating a characteristic of the semiconductor device.

FIG. 18illustrates the PBTI characteristic of the semiconductor device. The horizontal axis ofFIG. 18is the total thickness of the first thickness t31(nm) and the thickness t4(nm) of the fourth oxide region44. The vertical axis ofFIG. 18is the threshold voltage fluctuation amount ΔVth1(V).FIG. 18shows the results when gate stress is applied at room temperature.

It can be seen fromFIG. 18that the threshold voltage fluctuation amount ΔVth1decreases when the total thickness is large. It is considered that this is because the electric field in the fourth oxide region44is suppressed. The characteristic fluctuation due to PBTI can be suppressed by increasing the thickness t4of the fourth oxide region44. For example, it is favorable for the thickness t4to be 30 nm or more.

If the difference between the thickness t3and the thickness t4is too large, for example, the coverage degrades; and element breakdown occurs easily. It is desirable for the absolute value of the difference between the thickness t3and the thickness t4to be, for example, 100 nm or less. Good coverage is obtained easily. For example, the element breakdown is suppressed.

In the embodiment recited above, the concentration BC (Si—H) of the bond of Si and hydrogen of the nitride layer30(referring toFIG. 4) is, for example, 6×1021cm−3or less. The dangling bond concentration C1of Si of the nitride layer30(referring toFIG. 3) is, for example, 4×1018cm−3or less.

In the embodiment, it is favorable for the concentration of hydrogen in the third oxide region43to be low. The concentration of hydrogen in the third oxide region43is, for example, 2×1019cm−3or less. Thereby, the characteristics are more stable. For example, the characteristic fluctuation of the element due to PBTI does not occur easily.

For example, it is considered that the characteristics necessary for the insulating film of a normally-off device are different from the characteristics necessary for the insulating film of a normally-on device. For example, the characteristics that are necessary for the insulating film to reduce the current collapse recited above are unique to normally-off. By using the “N-rich” nitride layer30, the fluctuation of the characteristics of a normally-off device can be suppressed effectively.

Second Embodiment

A second embodiment relates to a method for manufacturing a semiconductor device.

FIG. 19AtoFIG. 19Dare schematic cross-sectional views in order of the processes, illustrating the method for manufacturing the semiconductor device according to the second embodiment.

A stacked body SB is prepared as shown inFIG. 19A. The stacked body SB includes the first semiconductor layer10including Alx1Ga1-x1N (0<x1≤1), the second semiconductor layer20including Alx2Ga1-x2N (0<x2≤1), and the nitride layer30including silicon and nitrogen. The second semiconductor layer20is provided between the first semiconductor layer10and the nitride layer30. The ratio Si/N of the concentration of silicon (Si) in the nitride layer30to the concentration of nitrogen (N) in the nitride layer30is not less than 0.68 and not more than 0.72. For example, the nitride layer30contacts the second semiconductor layer20. In the example, the buffer layer5bis provided on the substrate5s; and the stacked body SB is provided on the buffer layer5b.

For example, the nitride layer30is formed by a technique such as CVD, etc. The ratio Si/N in the nitride layer30is controlled by controlling the flow rate of the source gas (e.g., ammonia), etc.

In the manufacturing method according to the embodiment, heat treatment of the stacked body SB is performed after forming the nitride layer30. For example, the heat treatment is performed in a nitrogen atmosphere for 5 minutes or more at 700° C. or more.

For example, as shown inFIG. 19B, a portion of the nitride layer30and a portion of the second semiconductor layer20after the heat treatment may be removed.

For example, as shown inFIG. 19C, the oxide layer40that includes silicon and oxygen is formed at the remaining portion of the nitride layer30and the remaining portion of the second semiconductor layer20. The concentration of nitrogen in the oxide layer40is lower than the concentration of nitrogen in the nitride layer30.

For example, an electrode (e.g., the third electrode53) is formed as shown inFIG. 19D. At least a portion of the oxide layer40recited above is provided between the electrode (the third electrode53) and the remaining portion of the second semiconductor layer20recited above. Other electrodes are formed as appropriate. Thereby, for example, the semiconductor device110is obtained. According to the manufacturing method according to the embodiment, a method for manufacturing a semiconductor device having stable characteristics can be provided.

According to the embodiments, a semiconductor device and a method for manufacturing the semiconductor device having stable characteristics can be provided.

Hereinabove, exemplary embodiments of the invention are described with reference to specific examples. However, the embodiments of the invention are not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components included in semiconductor memory devices such as electrodes, semiconductor layers, nitride layers, oxide layers, substrates, etc., from known art. Such practice is included in the scope of the invention to the extent that similar effects thereto are obtained.

Moreover, all semiconductor devices, and methods for manufacturing the same practicable by an appropriate design modification by one skilled in the art based on the semiconductor devices, and the methods for manufacturing the same described above as embodiments of the invention also are within the scope of the invention to the extent that the purport of the invention is included. Various other variations and modifications can be conceived by those skilled in the art within the spirit of the invention, and it is understood that such variations and modifications are also encompassed within the scope of the invention.