Stitched micro-via to enhance adhesion and mechanical strength

A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material. The integrated circuit packaging substrate also includes a via for interconnecting the first layer of conductive material and the second layer of conductive material having a base that includes an interfacial adhesion material to stitch the base of the via to a layer of circuitry.

FIELD OF THE INVENTION

The present invention is related to formation of structures associated with semiconductor devices. More specifically, the present invention relates to methods and apparatus for forming a stitched micro-via to enhance adhesion and mechanical strength.

BACKGROUND OF THE INVENTION

The semiconductor industry has seen tremendous advances in technology in recent years that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of several gigahertz (GHz), to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high density and high functionality in semiconductor devices has been an ongoing pressure to further miniaturize the individual circuit features within an integrated circuit and packaging substrate, such as a microprocessor or a chip set component or the like.

There are many different features within an integrated circuit packaging substrate. One feature is a via. An integrated circuit packaging substrate contains several levels of circuitry. A via is a vertical opening filled with conducting material used to connect conductor trace on one layer to the next layer. Vias can also provide conductive paths from a layer of integrated circuit to the exterior of the package. As vias are made smaller, there are some occurrences where the structure within the via fails to provide an electrical connection. This is the type of failure that may not occur immediately. Rather, this type of failure may occur after the integrated circuit within a die has been packaged and shipped. One form of this type of failure is delamination of the via structure. This may be due to excessive mechanical stress, contamination of dielectric residues trapped from laser drilling of the via opening, or sulfur contamination on electroless copper (Cu) plating.

The description set out herein illustrates the various embodiments of the invention, and such description is not intended to be construed as limiting in any manner.

DETAILED DESCRIPTION

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention can be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments can be utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of present inventions. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments of the invention is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.

FIG. 1is a cross-sectional schematic view of an integrated circuit packaging substrate120that includes a plurality of devices110thereon, according to an embodiment of this invention. The devices110provide electrical and physical interface of the packaging substrate120. In actuality, the devices are embedded inside the packaging substrate120. Generally, the packaging substrate120will include as many as several thousand identical or nearly identical devices110.

An integrated circuit packaging substrate120is processed to form the various layers that form the circuitry within the individual devices. One of the features commonly formed on an integrated circuit packaging substrate120and, therefore in an individual circuit associated with a wafer or a chip, is a via130. A via is a vertical opening filled with conducting material131used to connect circuits on the various levels of a device to one another. Vias also provide conductive paths from a level of circuitry to the exterior of the packaging substrate.

FIG. 2illustrates a schematic cross-sectional view of a delaminated via200of the prior art. The via200is for connecting circuitry at a first level210to circuitry at a second level220. The via200includes a cylindrical or frusto-conical shaped barrel portion202and a base204. It is desirable to have the bottom or base204of the via200to make a good mechanical and a good electrical connection between the base204and the second level of circuitry220. As shown inFIG. 2, the base, or the bottom of the base204, is delaminated from the second level of circuitry220. The delamination is depicted by a crack or spacing which carries the reference numeral230.

FIG. 3illustrates a schematic cross-sectional view of the portion of the via where the base interfaces or contacts with the second level of circuitry220as presented in the prior art. EssentiallyFIG. 3is an exploded view of the encircled section of the via200shown inFIG. 2. The delamination is shown by reference line230inFIG. 3. The second level of circuitry220is formed of a conductive material, such as electrolytic copper. In the prior art, the base204of the via200includes a layer of electroless copper depicted by reference numeral310and a layer of electrolytic copper312. The electrolytic copper312of the via is also used to line the entire cylindrical portion202of the via, as well as form a portion of the first level of circuitry210. The second level of circuitry220has a thickness of approximately 1 mil or 25.4 micrometers. The electrolytic copper layer312also has a thickness height of approximately 1 ml. or 25.4 micrometers. The thickness height of the second level of circuitry220is depicted by the reference numeral h2, while the thickness height of the electrolytic copper layer312is depicted by h1. The layer of electroless copper310also has a thickness height h3, which is approximately 100 nanometers. The thickness height of the electroless copper layer310is depicted by the reference h3.

FIG. 4Aillustrates a schematic cross-sectional view of a feature of a device400, according to an embodiment of this invention. The feature400is a via. The feature or via400will now be discussed in more detail. The feature or via400is part of an integrated circuit packaging substrate (120) which, as mentioned earlier. The via400includes a first level of circuitry410and a second level of circuitry420. The via400also includes a cylindrical portion of barrel402. As shown inFIG. 4Athe cylindrical portion is frusto-conically shaped. The via400also includes a base404. The base404is mechanically and electrically joined to the second level of circuitry420at the joint or adhesion area440. The joint or adhesion area is depicted by the reference numeral440and also shown encircled inFIG. 4A.

FIG. 4Billustrates a schematic cross-sectional view of the feature400of a device at the location where the feature400is electrically connected to the second level420of circuitry, according to an embodiment of this invention. The base404of the via or device410includes an electrolytic copper layer412and an electroless copper layer414. The second level of circuitry420also includes an electrolytic copper layer418. The area also includes an interfacial adhesion layer450. The interfacial adhesion layer450is comprised of an interfacial adhesion material which is diffused into the electroless copper layer414and the electrolytic copper layer418associated with the second level of circuitry420as well as the electrolytic copper layer412associated with the base404of the feature or via400. The interfacial adhesion layer450has a multiple inter-diffused structure. The individual inter-diffused structure, such as tooth451, extend from the electroless copper layer414into the electrolytic copper layer412associated with the base404of the feature or via400. Other individual inter-diffused structure, such as a tooth452, extends between the electrolytic copper layer418and the electroless copper layer414. The inter-diffused structures of the interfacial adhesion layer450produces an enhanced mechanical bond at the interface between the base404of the feature or micro-via and the second level of circuitry420associated with the integrated circuit packaging substrate110shown inFIG. 1.

An integrated circuit packaging substrate includes a first layer of conductive material410, and a second layer of conductive material420. The integrated circuit packaging substrate also includes a feature or via400for interconnecting the first layer of conductive material410and the second layer of conductive material420. The via400further includes a base404positioned at the second layer of conductive material420. The base404includes a conductive material414,418and an interfacial adhesion material450. The interfacial adhesion material450forms a solid solution with the conductive material412,414,418. In one embodiment, the interfacial adhesion material450is palladium and the conductive material412,414,418is copper. The palladium forms a solid solution with the copper. In some embodiments the interfacial adhesion material450interdiffuses with the conductive material412,414,418. The interdiffusion of the interfacial adhesion material and the conductive material is nonuniform. The interdiffusion of the interfacial adhesion material and the conductive material forms a plurality of structures451,452that extend into the conductive material412,414,418. The plurality of interdiffusion structures451,452form a stitched bonding between the base404of the feature or via400and the second level of circuitry420to which the via400connects. The inter-diffused structures451,452or the stitched bonding prevents failures at the interface between the base404of the feature or via400and the second level of circuitry420.

Now turning toFIGS. 5A to 5E, the details of the formation of the inter-diffused structure or interfacial adhesion layer450will now be discussed.FIG. 5Aillustrates formation of the feature at its initial stages, according to an embodiment of the invention. In order to form a via, initially an opening is drilled. A blind hole or an opening510is drilled through to the base of the electrolytic copper layer associated with the second level of circuitry420. The opening510can be made with any sort of tool. In this particular embodiment, for a miniaturized via, or a micro-via, the opening510is formed using a laser. The opening510is made in a substrate520which previously covered the second level of circuitry420in the integrated circuit packaging substrate. The substrate520includes a top surface521.

FIG. 5Billustrates another stage during the process of formation of a via in an integrated circuit packaging substrate, according to an embodiment of this invention. As shown inFIG. 5B, surface521of the substrate520is masked with a mask530. The mask530is treated to form an opening531therein. The diameter of the opening531is essentially equal to the diameter of the base of the via404(shown inFIGS. 4A and 5B). The diameter of the opening531is also equal to the diameter of the exposed portion of the second level of circuitry420, which is found at the closed end of511of the opening510. The closed end511of the opening510has exposed conductive material from the second level of circuitry420. An interfacial material550is deposited on the mask and through the opening531in the mask530to the surface of the second level of circuitry420found at the closed end511of the opening510. The deposition of the interfacial material550is depicted by the arrows551which are passing through the opening531in the mask530and by the arrows532and533, which show that some of the interfacial layer material550is being deposited on the surface of the mask530. In one embodiment the interfacial layer material that is being deposited is palladium (Pd). Also in some embodiments the palladium or interfacial or layer material is deposited using a selective sputtering process. The result, as shown inFIG. 5B, is a layer of interfacial material550deposited on the surface of the second level of circuitry420at the closed end511of the opening510in the substrate520. The next step, as shown inFIG. 5C, is to remove the mask530and plate the opening510. The closed end511of the opening is initially plated with a layer of electroless copper414. Next the entire opening510is plated with a layer of electrolytic copper412. The end result of this step is to form the base404of the feature or via400and the barrel portion402of the via400. The plating process also forms the interconnection to the first level of electronic, depicted by reference numeral410. It should be noted that the base404includes a layer of the interfacial adhesion material555as well as a layer of electroless copper414and a layer of the electrolytic copper412.

FIG. 5Dillustrates still another stage during the process of formation of a via400in an integrated circuit packaging substrate, according to an embodiment of this invention. As shown inFIG. 5Da laser560directs a laser beam562toward or at the base404of the via or feature400. The laser energy is depicted by the dotted arrows carrying the reference numeral562. The laser energy562heats the joint area440to a range of approximately 400 to 600° C. The directing of the laser beams562toward the joint area440is also referred to as laser brazing. Laser brazing enhances diffusion of the interfacial adhesion materials, such as palladium, into the electroless layer414and into the electrolytic copper layer412and the electrolytic layer418. The laser has a diameter d1, which is approximately half the diameter of the diameter of the base404depicted by dB.

FIG. 5Eshows a completed via400formed by the process shown inFIGS. 5A to 5Dand further discussed inFIGS. 7 and 8below, according to an embodiment of this invention. After the laser step the via is capped with a cap570. The end result is a via as shown inFIGS. 4A and 4B. This particular process is very good for any formation of a feature such as a via. This particular process is particularly effective when forming a micro-via.

FIG. 6is a Cu—Pd (Copper and Palladium) phase diagram600showing the formation of an alloy of copper and palladium, according to an embodiment of this invention. The phase diagram600shows that a Cu—Pd solid solution is formed at much lower temperatures than the temperature produced by directing energy from the laser560to the base404of the via400, as shown inFIG. 5Dabove. At various weight percentages of Copper and Palladium, various phases of the compound of Cu—Pd are formed. The palladium forms a solid solution with the copper. In some embodiments the interfacial adhesion material450(shown inFIGS. 4A and 4B) interdiffuses with the conductive material412,414,418(shown inFIGS. 4A and 4B). The interdiffusion of the interfacial adhesion material and the conductive material is non-uniform. It is contemplated that the resulting structure451,452(shown inFIGS. 4A and 4B) of the interfacial adhesion material450(shown inFIGS. 4A and 4B) includes alloys of copper and palladium as well as areas of high percentages of palladium and areas of high percentages of copper, in addition to the interdiffusion mentioned above. It is also contemplated that the interfacial adhesion material450will also include the alpha phase and beta phase Cu—Pd materials in addition to the interdiffusion of the copper and palladium. It should be noted that even though the above example shows deposition of a layer of palladium555on the surface of the second level of electronics420at the closed end of the opening510, other adhesion materials could be substituted for palladium. For example, nickel, cobalt and platinum are some of the metals that could be used to form the interfacial adhesion area450used to stitch the via400to the second level of circuitry420. In fact, any material that formed an interfacial adhesion area450used to stitch the via400to the second level of circuitry420is contemplated by this invention.

FIG. 7is a flow diagram showing a method for forming a via in a semiconductor device700, according to an embodiment of this invention. The method for forming a via in an integrated circuit packaging substrate includes making a via opening having a base so that the base of the via opening is positioned at a selected level within an integrated circuit packaging substrate710. The base may also adjoin conductive material within the integrated circuit packaging substrate. The method700also includes masking the surface of the semiconductor device712. The mask formed has a mask opening therein positioned above to the base of the via opening. The method700also includes depositing an interfacial layer material within at the base of opening714, placing a conductive material over the interfacial material716, and heating the materials at the base of the opening718. Depositing an interfacial layer material within the via opening includes sputtering the interfacial material onto the mask and into the via opening. The method further includes removing the mask.

The interfacial layer material450(FIGS. 4A–4B) is a material that will diffuse into the conductive material414,412,418(FIGS. 4A–4B) at the temperature produced by heating the materials at the base of the via opening. The interfacial material450(seeFIGS. 4A–4B) may include palladium, platinum, cobalt or nickel. In one embodiment, the interfacial material450(FIGS. 4A–4B) includes palladium. Heating the materials at the base of the via opening includes directing energy from a laser560(seeFIG. 5D) at the base404of the opening. The laser energy is higher at the center of the laser560(seeFIG. 5D). In other words, the laser560has a Gaussian energy distribution. The laser560(seeFIG. 5D) produces temperatures at the base404(seeFIGS. 4A–4B) of the via opening in the range of 400 to 600 degrees C. The laser560(seeFIG. 5D) has a diameter of approximately half the diameter of the base of the via opening. Placing a conductive material414,412over the interfacial material555(seeFIG. 5C) includes plating copper within the via opening. Placing a conductive material over the interfacial material further includes plating electroless copper at the base of the via opening, and plating the via opening with electrolytic copper. The method also includes capping the via.

FIG. 8is a flow diagram showing a method for forming a via in an integrated circuit packaging substrate800, according to another embodiment of this invention. The method for forming a via in an integrated circuit packaging substrate800includes embedding an interfacial adhesion layer at a base of a via810, and heating the materials at the base of the via812. Embedding the interfacial adhesion layer810further includes placing a conductive material over the interfacial adhesion layer814. Heating the materials at the base of the via412includes directing the energy of a laser560(seeFIG. 5D) at the base of the via. Heating the materials at the base of the via812includes heating the materials at the base of the via to a temperature within the range of 400–600 degrees C. The interfacial adhesion material interdiffuses with the conductive material. In some embodiments, the interdiffusion of the interfacial adhesion material and the conductive material is nonuniform and forms teeth-like structures that extend into the conductive layers at the base of the via.

The foregoing description of the specific embodiments reveals the general nature of the invention sufficiently that others can, by applying current knowledge, readily modify and/or adapt it for various applications without departing from the generic concept, and therefore such adaptations and modifications are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments.

It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Accordingly, the invention is intended to embrace all such alternatives, modifications, equivalents and variations as fall within the spirit and broad scope of the appended claims.