Electronic device for recovering from buffer overrun in a bus system

An electronic device includes a memory, plural master circuits, a transmission path, a detection unit, and a reset control unit. The plural master circuits read and write data from and into the memory. Plural instructions and data are transmitted through the transmission path while buffering and arbitrating the instructions and the data. The detection unit detects a buffer overrun in the transmission path. The reset control unit performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plural master circuits, affected by the buffer overrun.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2017-135525 filed Jul. 11, 2017.

BACKGROUND

(i) Technical Field

The present invention relates to an electronic device.

(ii) Related Art

In electronic devices, a variety of electronic components such as a processor that serves as a computation unit and a memory are connected to each other via buses. In a bus system, data being transferred are occasionally lost because of an increase in load, occurrence of a trouble, or the like. In this case, the bus system is reset for recovery.

A split transaction is performed to improve the use efficiency of the buses. In the split transaction, when a certain device starts a data transfer process, the process is suspended while the device is waiting for an acknowledgment to allow another device to perform a data transfer process. The use efficiency of the buses may be improved by preventing one device from occupying the buses for a long time.

SUMMARY

According to an aspect of the present invention, there is provided an electronic device including: a memory; plural master circuits that read and write data from and into the memory; a transmission path through which plural instructions and data are transmitted while buffering and arbitrating the instructions and the data; a detection unit that detects a buffer overrun in the transmission path; and a reset control unit that performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plural master circuits, affected by the buffer overrun.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

<Example of Configuration of Electronic Device According to Present Exemplary Embodiment>

Examples of a split bus as an on-chip bus for use in an integrated circuit formed on a chip such as a system on a chip (SoC) include an advanced extensible interface (AXI) bus and an open core protocol (OCP) bus. In the description of a present exemplary embodiment, the AXI bus is used. However, the present invention may also be applied to other split buses.

FIG. 1illustrates an example of the configuration of a bus system according to a present exemplary embodiment. In a bus system100according to the present exemplary embodiment illustrated inFIG. 1, a memory40is accessed from plural direct memory access (DMA) masters10by way of plural buses20and bus bridges30. A random access memory (RAM) (such as a double-data-rate synchronous dynamic random access memory (DDR-SDRAM), for example) and a RAM controller (such as a DDR-SDRAM memory controller+PHY, for example) are used as the memory40. InFIG. 1, the buses20include basic virtual component interface (BVCI) buses21and AXI buses22. The bus bridges30include bus bridges31that relay between the BVCI bus21and the AXI bus22and bus bridges32that relay between the AXI buses22. The DMA masters10and the bus bridges30are each provided with a monitoring device50that monitors the state of data transfer. Each monitoring device50is connected to a bus control section60that controls operation of the bus system100. InFIG. 1, the DMA masters10and the bus bridges31and32are provided with an index (such as a and b). In the case where the individual constituent elements are not differentiated from each other, however, the constituent elements are not provided with an index as described above. A central processing unit (CPU) that configures the DMA masters10(suspends or resumes DMA) in the bus system100illustrated inFIG. 1is provided, although not specifically illustrated.

The DMA master10is a master circuit that reads and writes data from and into the memory40through DMA. In the example illustrated inFIG. 1, the DMA master10includes a module11that performs various types of operation (such as data processing and control), a DMAC12for access to the memory40through DMA, and a monitoring device50. The monitoring device50which is provided in the DMA master10monitors data transfer (DMA transfer) in the DMA master10, and counts requests (REQs) issued (transmitted) by the DMA master10and acknowledgments (ACKs) received by the DMA master10. InFIG. 1, some of the DMA masters10are not illustrated, and two DMA masters10aand10bare illustrated.

The bus20is used to transmit data (instructions and data to be read and written) between the DMA master10and the memory40. The bus bridge30connects between the buses20. In the example illustrated inFIG. 1, as discussed above, the BVCI bus21and the AXI bus22are used as the bus20. The DMA master10a, for example, is connected to the memory40via the BVCI bus21, the bus bridge31a, the AXI bus22, the bus bridge32a, the AXI bus22, the bus bridge32c, and the AXI bus22.

The bus bridge30connects between different buses, and arbitrates data transfer between the connected buses. In the example illustrated inFIG. 1, the bus bridges30includes the bus bridges31which connect between the BVCI bus21and the AXI bus22, and the bus bridges32which connect between the AXI buses22. The bus bridges31and32each include the monitoring device50. The monitoring device50which is provided in the bus bridge31,32monitors data transfer in the bus bridge31,32, and counts requests (REQs) and acknowledgments (ACKs) transmitted and received. InFIG. 1, components on the DMA master10side with respect to the bus bridge32bare not illustrated.

The configuration of connection between the buses20and the bus bridges30in the bus system100according to the present exemplary embodiment is not limited to the example illustrated inFIG. 1. In the example illustrated inFIG. 1, for example, transmission paths from the DMA masters10aand10bto the memory40each include four buses20and three bus bridges30. However, the transmission paths may each include different numbers of buses20and bus bridges30. The BVCI bus21is connected to the DMA master10as the bus20. However, the AXI bus22may be connected to the DMA master10as the bus20. In the bus system100for DMA with plural DMA masters10, in general, as the distance from the memory40to be accessed is shorter, the transmission paths are more integrated and aggregated, and therefore buses20with a higher transmission efficiency are used. On the contrary, buses20with a higher transmission efficiency do not need to be used at positions closer to the DMA masters10compared to positions closer to the memory40. In the example illustrated inFIG. 1, the BVCI buses21with a lower transmission efficiency than that of the AXI buses22are used only as the buses20which are connected to the DMA masters10, by way of example.

As discussed above, the monitoring device50is provided in each of the DMA masters10and the bus bridges30, and monitors data transfer in the bus system100. InFIG. 1, one monitoring device50is provided in each of the bus bridges30. However, the monitoring device50monitors data transfer for each of the buses20. For example, the monitoring device50in the bus bridge32aillustrated inFIG. 1monitors data transfer for each of the three AXI buses22for connection with the bus bridges31aand31bon the DMA master10side and the bus bridge32con the memory40side. In many cases, the bus system100is provided with a bus arbiter that arbitrates data transfer in the entire bus system100, although not specifically illustrated. In such cases, the bus arbiter is also provided with the monitoring device50, and the monitoring device50monitors data transfer arbitrated by the bus arbiter.

The bus control section60acquires monitoring information (count of transferred data (requests and acknowledgments)) on data transfer from the monitoring device50, and determines on the basis of the acquired count whether or not data related to the requests and acknowledgments have been lost at any location in the bus system100. The bus control section60is an example of a reset control unit (circuit) that performs reset control, in the case where a loss of data is detected, for the DMA masters10and the bus bridges30which are involved in the detected loss of data.

In the bus system100, data such as requests issued by the plural DMA masters10are transmitted to the memory40while performing arbitration, and therefore a buffer is provided to temporarily hold the data in the bus system100. If data in an amount that exceeds the capacity of the prepared buffer are transmitted, however, a buffer overflow (data overrun) is caused, and the data may be lost. Split buses such as the AXI bus22perform complicated arbitration in order to transmit a second request without waiting for an acknowledgment to a first request or transmit a reading request and a writing request at the same time. Therefore, the split buses have a higher risk of occurrence of a buffer overflow than buses that do not support a split transaction. Thus, in the present exemplary embodiment, the bus control section60detects occurrence of a buffer overflow on the basis of monitoring information acquired by the monitoring device50, specifies the location at which the buffer overflow has occurred, and performs reset control for recovering the bus system100. Thus, the monitoring devices50and the bus control section60function as a detection unit that detects a buffer overrun in the bus system100which serves as a transmission path.

The bus control section60detects a buffer overflow as follows. The bus control section60compares, for each of the buses20, the number of requests and the number of acknowledgments transmitted via the bus20on the basis of monitoring information from the monitoring devices50of the DMA masters10and the bus bridges30. The bus control section60also compares the number of data transmitted via the bus20on the transmission side and the number of data transmitted via the bus20on the reception side. The bus control section60also compares the number of data received at each of the bus bridges30and the number of data transmitted at each of the bus bridges30. The bus control section60specifies a location at which a buffer overflow has occurred in the bus system100on the basis of the results of the comparisons. That is, the bus control section60determines that a buffer overflow has occurred in the case where the number of data directed from the DMA master10side toward the memory40side and the number of data directed from the memory40side toward the DMA master10side do not match each other.

A specific example will be described further. Focus is placed on the AXI bus22between the bus bridge31aand the bus bridge32a, by way of example. The AXI bus22is a part of a transmission path for transmission of an instruction issued by the DMA master10ato the memory40. In this example, the bus control section60calculates the difference between the number of requests transmitted by the bus bridge31aand the number of acknowledgments received by the bus bridge31a. If the number of acknowledgments is smaller than the number of requests, the bus control section60determines that a buffer overflow has occurred on the memory40side with respect to the bus bridge31a, and that a request or an acknowledgment is lost.

The bus control section60also calculates the difference between the number of requests received by the bus bridge32aand the number of acknowledgments transmitted by the bus bridge32a. If the number of acknowledgments is smaller than the number of requests, the bus control section60determines that a buffer overflow has occurred on the memory40side with respect to the bus bridge32a, and that a request or an acknowledgment is lost.

The bus control section60also calculates the difference between the number of requests transmitted by the bus bridge31aand the number of requests received by the bus bridge32a, and the difference between the number of acknowledgments transmitted by the bus bridge32aand the number of acknowledgments received by the bus bridge31a. If the number of requests received by the bus bridge32ais smaller than the number of requests transmitted by the bus bridge31a, the bus control section60determines that a request is lost during transmission through the AXI bus22between the bus bridge31aand the bus bridge32a. Similarly, if the number of acknowledgments received by the bus bridge31ais smaller than the number of acknowledgments transmitted by the bus bridge32a, the bus control section60determines that an acknowledgment is lost during transmission through the AXI bus22between the bus bridge31aand the bus bridge32a.

The bus control section60also calculates the difference between the number of requests received from the DMA master10side and the number of requests transmitted to the memory40side at each of the bus bridges30. Similarly, the bus control section60calculates the difference between the number of acknowledgments received from the memory40side and the number of acknowledgments transmitted to the DMA master10side. If the number of transmitted requests is smaller than the number of received requests, the bus control section60determines that a buffer overflow has occurred in the bus bridge30, and that a request is lost. If the number of transmitted acknowledgments is smaller than the number of received acknowledgments, the bus control section60determines that a buffer overflow has occurred in the bus bridge30, and that an acknowledgment is lost.

The detection of a buffer overflow will be further described using a simple model.FIG. 2illustrates a method of detecting a buffer overflow in the bus system100. In the example illustrated inFIG. 2, the bus system100is represented by a simple model that includes a DMAC12(DMA master10), a bus bridge30a, a bus bridge30b, a memory40, and buses20.

FIGS. 3A and 3Bare each a table illustrating how a request (REQ) and an acknowledgment (ACK) are transferred in the bus system100illustrated inFIG. 2.FIG. 3Aillustrates an example of operation to transmit a request (REQ) from the DMAC12to the memory40via the bus bridges30aand30bduring normal times.FIG. 3Billustrates an example of operation during occurrence of an abnormality. InFIGS. 3A and 3B, the bus bridge30awhich is the first from the DMAC12and the bus bridge30bwhich is the second from the DMAC12are abbreviated, as appropriate, as “BB-a” and “BB-b”, respectively. In the example illustrated inFIGS. 3A and 3B, variations in state of request (REQ) and acknowledgment (ACK) signals monitored by the monitoring device50at the respective constituent elements, namely the DMAC12, the bus bridge30a, and the bus bridge30b, are indicated. InFIGS. 3A and 3B, each of the signals has a value “0” in the initial state, and is varied to a value “1” at the time (position with a thick box) when operation related to the signal (generation or reception (indicated as “reception” in the drawings) of the signal) is caused.

An example of operation during normal times will be described with reference toFIG. 3A. First, the DMAC12issues a request (REQ), which is sent to the bus bridge30avia the bus20. InFIG. 3A, the signal “REQ” of the DMAC12has a value “1” since the article “REQ generated by DMAC”. The generated request (REQ) is transmitted through the bus20, and received by a master-side terminal (terminal on the DMA master10side) of the bus bridge30a. InFIG. 3A, the signal “REQ” on the master side of the bus bridge30a(BB-a) has a value “1” since the article “REQ received on master side of BB-a”. Upon receiving the signal, the bus bridge30areturns an acknowledgment (ACK) to the DMAC12which transmitted the signal. InFIG. 3A, the signal “ACK” on the master side of the bus bridge30ahas a value “1” since the article “ACK generated on master side of BB-a”. In addition, the signal “ACK” of the DMAC12has a value “1” since the article “ACK received by DMAC”.

Next, the bus bridge30asends the received request (REQ) from a terminal on the memory40side to the bus bridge30bvia the bus20. InFIG. 3A, the signal “REQ” on the memory side of the bus bridge30a(BB-a) has a value “1” since the article “REQ generated on memory side of BB-a”. The request (REQ) which is sent from the bus bridge30ais transmitted through the bus20, and received by a master-side terminal of the bus bridge30b. InFIG. 3A, the signal “REQ” on the master side of the bus bridge30b(BB-b) has a value “1” since the article “REQ received on master side of BB-b”. Upon receiving the signal, the bus bridge30breturns an acknowledgment (ACK) to the bus bridge30awhich transmitted the signal. InFIG. 3A, the signal “ACK” on the master side of the bus bridge30bhas a value “1” since the article “ACK generated on master side of BB-b”. In addition, the signal “ACK” on the memory side of the bus bridge30ahas a value “1” since the article “ACK received on memory side of BB-a”.

Next, the bus bridge30bsends the received request (REQ) from a terminal on the memory40side to the memory40via the bus20. InFIG. 3A, the signal “REQ” on the memory side of the bus bridge30b(BB-b) has a value “1” since the article “REQ generated on memory side of BB-b”. When the request (REQ) reaches the memory40, an acknowledgment (ACK) is returned from the memory40to the bus bridge30b. InFIG. 3A, the signal “ACK” on the memory side of the bus bridge30b(BB-b) has a value “1” since the article “ACK received on memory side of BB-b”. It is seen from the above that the request (REQ) which was issued by the DMAC12has reached the memory40.

Next, an example of operation during occurrence of an abnormality will be described with reference toFIG. 3B. In the operation illustrated inFIG. 3B, a request (REQ) is issued by the DMAC12and transmitted toward the memory40as in the operation example illustrated inFIG. 3A, but a buffer overflow occurs in the bus bridge30b. Operation until the request (REQ) which is issued by the DMAC12reaches the bus bridge30bis the same as the operation discussed above with reference toFIG. 3A, and thus will not be described.

InFIG. 3B, upon receiving the request (REQ), the bus bridge30breturns an acknowledgment (ACK) to the bus bridge30awhich transmitted the signal. InFIG. 3B, the signal “ACK” on the master side of the bus bridge30bhas a value “1” since the article “ACK generated on master side of BB-b”. In addition, the signal “ACK” on the memory side of the bus bridge30ahas a value “1” since the article “ACK received on memory side of BB-a”. Here, it is assumed that a buffer overflow has occurred at the bus bridge30b. Therefore, a request (REQ) is not transmitted from the bus bridge30bto the memory40. InFIG. 3B, the signal “REQ” on the memory side of the bus bridge30b(BB-b) continues to have a value “0” also in the article “REQ generated on memory side of BB-b” (thick box in the broken line in the drawing”. Since a request (REQ) is not transmitted to the memory40, an acknowledgment (ACK) is also not returned from the memory40to the bus bridge30b. Thus, inFIG. 3B, the signal “ACK” on the memory side of the bus bridge30b(BB-b) continues to have a value “0” also in the article “ACK received on memory side of BB-b”.

Since the signal state is not varied in a portion of the transmission path after the terminal of the bus bridge30b(BB-b) on the memory side as described above, it is seen that the signal “REQ” is lost because of the buffer overflow which has occurred in an internal buffer of the bus bridge30b. In the bus system100, the signals are transmitted while being arbitrated, and therefore there is a slight time difference since a signal is detected at a preceding monitoring position in the transmission path until the signal is detected at a following monitoring position. Thus, it is determined that a buffer overflow has occurred in the case where the signal state is not varied, after the time which is needed for arbitration has elapsed, for a monitoring position that follows the monitoring position at which variations in signal state are detected, for example.

In the AXI bus22, as discussed above, requests (REQs) and acknowledgments (ACKs) are transferred via separate transmission paths (channels). In the AXI bus22, in addition, a reading instruction (address) and reading data and a writing instruction (address) and writing data are transferred via separate transmission paths (channels) in response to a reading request and a writing request. Therefore, a buffer overflow may occur in each such transfer. In the entire bus system100, as illustrated inFIG. 1, the transmission paths are aggregated from the DMA master10side toward the memory40. Therefore, a buffer overflow tends to occur in transfer from the DMA master10side toward the memory40. Specifically, a buffer overflow tends to be caused for a reading instruction, a writing instruction, writing data, etc. In data reading, in particular, many requests may be successively issued by the DMA masters10. Therefore, a buffer overflow tends to occur in data reading compared to other types of transfer. In data writing, a writing request may not be issued unless all data to be written have been prepared, and therefore requests are rarely issued successively (there is often an interval from the issuance of one request to the issuance of the next request). Thus, a buffer overflow is less likely to occur in data writing than in data reading. With the monitoring device50and the bus control section60according to the present exemplary embodiment, however, occurrence of a buffer overflow may be detected, and the location of the occurrence of the buffer overflow may be specified, irrespective of the type of transfer.

Next, reset control by the bus control section60will be described. The bus control section60specifies, on the basis of the location of the occurrence of a buffer overflow specified as described above, a portion of the transmission path which forms the bus system100affected by the buffer overflow. The bus control section60performs reset control for recovering operation for the specified transmission path portion.

FIG. 1is referenced again. It is assumed that a buffer overflow has occurred at the bus bridge32ain the configuration example illustrated inFIG. 1. In this case, transmission path portions on the DMA master10side with respect to the bus bridge32a, at which the buffer overflow has occurred, may be affected by the buffer overflow. That is, requests issued by or acknowledgments to be received by the DMA masters10which use the transmission path portions (the DMA masters10aand10bin the example illustrated inFIG. 1) may be lost. Thus, in the case where a buffer overflow has occurred at the bus bridge32ain the configuration illustrated inFIG. 1, transmission path portions in a region A indicated by the broken line inFIG. 1are affected by the buffer overflow. Reset control is performed for the DMACs12(DMA masters10) and the bus bridges30which are included in the region A.

FIGS. 4 and 5are each a sequence diagram illustrating operation of reset control by the bus control section60.FIG. 4illustrates operation prior to reset execution.FIG. 5illustrates operation subsequent to the reset execution. InFIGS. 4 and 5, a CPU70performs various types of data processing and control, and functions as a configuration unit that configures the DMA masters10in the bus system100(suspends or resumes DMA transfer). A non-target DMAC12is a DMAC12that is not subjected to reset control (positioned outside the region A in the example illustrated inFIG. 1). A target DMAC12is a DMAC12that is subjected to reset control (positioned inside the region A in the example illustrated inFIG. 1). A target bus bridge30is a bus bridge30that is subjected to reset control (positioned inside the region A in the example illustrated inFIG. 1).

As illustrated inFIG. 4, when occurrence of a buffer overflow is detected on the basis of monitoring information acquired from the monitoring device50(S101), the bus control section60specifies a range for performing reset control (S102). The bus control section60performs an interrupt process for the CPU70to notify the CPU70that a buffer overflow has occurred (S103). As discussed above, the range for performing reset control is a range affected by the buffer overflow which has occurred, and includes transmission path portions on the DMAC12(DMA master10) side with respect to the location at which the buffer overflow has occurred. The CPU70is notified of the occurrence of the buffer overflow in order to perform operation control for the DMAC12which has been subjected to the reset control and the DMAC12which is not subjected to the reset control in the subsequent operation.

Next, the bus control section60instructs the non-target DMAC12to stop DMA transfer (S104). This is to avoid data transfer through DMA from the DMAC12which is not subjected to the reset control during the reset control. When DMA transfer by the non-target DMAC12which has received the instruction from the bus control section60is stopped, a notification that DMA transfer has been stopped is delivered from the non-target DMAC12to the bus control section60.

The bus control section60instructs the target bus bridge30to mask issuance and reception of a new request (S105). Here, masking issuance corresponds to not transmitting a new request to the following bus bridge30, and masking reception corresponds to not returning an acknowledgment even if a new request is received. When the target bus bridge30which has received the instruction from the bus control section60finishes masking issuance and reception of a new request, a notification that masking has been completed is delivered from the target bus bridge30to the bus control section60.

Next, upon receiving the notification from the non-target DMAC12and the target bus bridge30, the bus control section60resets the target DMAC12and the target bus bridge30, and subsequently cancels resetting (S106inFIG. 5). The bus control section60instructs the target bus bridge30to resume operation (S107), and further instructs the target bus bridge30to cancel masking of issuance and reception of a new request (S108). When the target bus bridge30which has received the instruction from the bus control section60cancels masking of issuance and reception of a new request, a notification that masking has been canceled is delivered from the target bus bridge30to the bus control section60.

The bus control section60performs an interrupt process for the CPU70to notify the CPU70that the reset control has been finished, and request the CPU70to resume DMA transfer by the DMACs12(the target DMAC12and the non-target DMAC12) (S109). The bus control section60resumes operation (analysis of monitoring information acquired from the monitoring device50) for detecting a buffer overflow in preparation for DMA transfer to be resumed (S110). When the request is received from the bus control section60, the CPU70resumes DMA transfer by the DMACs12.

Other Embodiments

In the configuration example illustrated inFIG. 1, the monitoring device50which is provided in each of the DMA masters10and the bus bridges30acquires monitoring information that indicates the state of data transfer, and the bus control section60detects occurrence of a buffer overflow by analyzing the monitoring information, and specifies the location of the occurrence of the buffer overflow. On the contrary, a detection device that detects occurrence of a buffer overflow may be provided in each of the DMA masters10and the bus bridges30.

FIG. 6illustrates an example of the configuration of a bus system according to another exemplary embodiment such as that described above. In the configuration example illustrated inFIG. 6, the DMA masters10, the buses20, the bus bridges30, and the memory40, and their connection relationship are the same as those in the configuration example illustrated inFIG. 1. In the exemplary embodiment illustrated inFIG. 6, a detection device80is provided in each of the bus bridges30. The detection device80monitors the state of buffer or the state of data transfer of the bus bridge30in which the detection device80itself is provided, and detects a buffer overflow in the case where the buffer overflow has occurred.

In the configuration example illustrated inFIG. 6, each detection device80is connected to a reset control section90. Upon detecting occurrence of a buffer overflow, the detection device80notifies the reset control section90. Upon receiving a notification from the detection device80, the reset control section90specifies a range affected by the buffer overflow which has occurred, and performs reset control for the DMA masters10and the bus bridges30in the specified range. Specifically, the DMA masters10and the bus bridges30in transmission path portions on the DMAC12(DMA master10) side with respect to the bus bridge30in which the detection device80which has transmitted the notification of the detection of the buffer overflow is provided are subjected to reset control.