Techniques for developing a negative impedance

Techniques to develop negative impedance circuits that may operate to their power supply rails. The techniques may include generating currents in response to voltage signals presented at respective input terminals of a negative impedance circuit. The voltage signals may be differential signals. The generated currents may be driven through a common impedance within the negative impedance circuit. The currents flowing through the common impedance may be mirrored back to the input terminals of the negative impedance circuit. The negative impedance circuit may be controlled to operate about a common-mode voltage for the circuit.

BACKGROUND

A negative impedance circuit is a device whose current is inversely proportional to the voltage across it. A negative impedance circuit can only be achieved with active circuitry.

Existing techniques for developing a negative impedance typically involve operational amplifier (op-amp) circuits having a “deboo” type structure that direct feedback current to a non-inverting terminal of the op-amp. These negative impedance circuits, however, may have limited operating ranges. This is caused by a requirement that the op-amps have a gain greater than unity in order to develop the negative impedance. Thus, if the voltage at the non-inverting terminal of the op-amp should approach the supply rails for the op-amp, the op-amp will saturate and the negative impedance circuit will become a positive resistance. The op-amp will cease generating a gain and the negative impedance circuit will merely become a positive resistance load.

Accordingly, there is a need in the art to provide techniques to develop a negative impedance circuit that operates to its supply rails.

DETAILED DESCRIPTION

Embodiments of the present invention provide techniques to develop negative impedance circuits that may operate to their power supply rails. The techniques may include generating currents in response to voltage signals presented at respective input terminals of a negative impedance circuit. The voltage signals may be differential signals. The generated currents may be driven through a common impedance within the negative impedance circuit. The currents flowing through the common impedance may be mirrored back to the input terminals of the negative impedance circuit. The negative impedance circuit may be controlled to operate about a common-mode voltage for the circuit.

FIG. 1illustrates a negative impedance system100according to an embodiment of the present invention. As illustrated inFIG. 1(a), a negative impedance system100may include a positive resistance R, and a negative impedance circuit110coupled in parallel to the positive resistance R. The system100may receive respective positive and negative supply voltages VDD and VSS. The system100may further receive differential input signals. The negative impedance circuit110may provide a response that acts as if a negative valued impedance had been placed in the system100. The impedance magnitude for the negative impedance circuit110may be tuned for various operating configurations, and, in some applications, may cancel a traditional resistance R provided in the system100. The combination of the positive resistance R and the negative impedance circuit110inFIG. 1(a) may provide an increase in the overall impedance for the system100.

For a first operating configuration, the magnitude of the impedance for the negative impedance circuit110may be tuned to match the magnitude of the resistance for the positive resistance R. The effect of matching the impedance magnitudes may produce an approximately infinite impedance at input nodes of the system100. The circuit ofFIG. 1(a) may be operated in this configuration.

In one example, the positive resistance R may be configured within a resistor-capacitor (RC) circuit. When the capacitor of the RC circuit may be coupled in parallel with the negative impedance circuit120having a matched negative impedance, the combined circuits may generate gain for DC signals that may be input to the system100.

For a second operating configuration, the magnitude of the impedance for the negative impedance circuit110may be configured such that it may not be matched to the magnitude of the resistance for the positive resistance R. The effect of the unmatched impedance magnitude for the negative impedance circuit110may produce a finite positive impedance for the system100. Either the circuit ofFIG. 1(a) or the circuit ofFIG. 1(b) may be operated in this configuration.

In one example, the positive resistance R may be configured within a resistor-capacitor (RC) circuit. When the capacitor of the RC circuit may be coupled in parallel with the negative impedance circuit110, the unmatched magnitude of the negative impedance circuit110may be tuned to generate gain for the combined circuits for predetermined signal frequencies that may be input to the system100.

FIG. 2illustrates a negative impedance circuit200according to an embodiment of the present invention. As illustrated inFIG. 2, the circuit200may include a pair of operational amplifiers210,220(“op-amps”) each having its positive input terminal coupled to a respective circuit input terminal INP, INNand its output terminal coupled to its negative terminals. The input signals presented at the input terminals may be differential signals. The circuit200may include a pair of current mirrors CM1, CM2each coupled to an output of a respective op-amp210,220and to a common resistor R1. The current mirrors CM1, CM2may have a current output coupled to respective input terminals INP, INN, and to respective inverting input terminals for each op-amp210,220.

The circuit200may receive voltages, positive supply rail VDD and negative supply rail VSS, which may provide operating power for each op-amp210,220. The gain for each op-amp210,220may be set to less than unity. The resistance for resistor R1may be set to a value that determines the negative impedance of the circuit200. The resistance may be tailored to suit individual design needs for the circuit200.

During operation, respective op-amps210,220may receive differential input signals from respective inputs INPand INN. From these respective differential input signals, each op-amp210,220may generate respective output signals IOUT1, IOUT2that may drive a current through the resistor230. As each op-amp210,220generates output signals IOUT1, IOUT2, respective currents IOUT1′ and IOUT2′ may be mirrored back to the respective inputs INPand INNfrom respective current mirrors CM1and CM2. The currents IOUT1′, IOUT2′ may have a magnitude that may be proportional to the respective input signals for each op-amp210,220. The currents IOUT1′ and IOUT2′ may propagate out the respective input terminals INP, INN, which may emulate a negative impedance at the input terminals INPand INN.

For example, say a differential signal input at circuit input INPmay an increase in amplitude while a differential signal input at input INNmay decrease in amplitude. In turn, the voltage output from the op-amp210may increase while the voltage output from op-amp220may decrease. The current flow through resistor230may increase from op-amp210toward op-amp220. The current from op-amp210may be mirrored through CM1back to the input INP. The current from op-amp220may be mirrored through CM2back to the input INNmay also decrease. The circuit200may operate in a reverse manner if a differential signal input at input INPmay decrease in amplitude while a differential signal input at input INNmay increase in amplitude. For the purpose of this example, the current mirrors CM1and CM2may be considered ideal mirrors with zero voltage drop across each mirror. In an embodiment, the current mirrored back to the respective inputs may be derived from output stage transistors (not shown) of the respective op-amps210and220that may carry the load current for each op-amp.

In an embodiment, the circuit200may include a common-mode controller240that may be coupled to the inverting inputs for each op-amp210,220. The common-mode controller240may include an internal resistance (not shown) which may be greater than the resistance set for the resistor230. The internal resistance may be set sufficiently high to ensure that the mirrored currents IOUT1and IOUT2may not flow into the controller240, but rather, flow to the respective inputs INPand INN.

The common-mode controller240may control operation of the circuit200about a predetermined common-mode voltage. As noted, the input signals presented at the input terminals INPand INNmay be differential signals. The magnitude of the differential input signals may be related to the common-mode voltage and may vary in a differential manner about the common-mode voltage. However, if during operation of the circuit200, the differential input signals at INPand INNmay diverge from the common-mode voltage in a non-differential manner, the controller240may adjust or re-balance operation of the circuit200back to the common-mode voltage.

FIG. 3illustrates a negative impedance circuit300according to another embodiment of the present invention. As illustrated inFIG. 3, the circuit300may include a pair of current sources310,320; a pair of op-amps330,340, a pair of level-shifting transistors T1, T2, and a pair of current mirrors350,360. The op-amps each may have output terminal coupled to its negative input terminal.

Each level-shifting transistor T1, T2may have a gate coupled to an input terminal INP, INNfor an input signal. The input signals presented at the input terminals may be differential signals. Each transistor T1, T2may have a drain coupled to respective current sources310,320and to a positive input terminal of respective op-amps330,340. Each transistor T1, T2may have a source coupled to a common resistor R1and to a respective current mirror350,360. Current mirror350may have a mirror transistor T3having a drain coupled to the source of transistor T1and to the common resistor R1. Current mirror350may have a mirror transistor T4having a drain coupled to the input terminal INP and to the gate of transistor T1. Current mirror360may have a mirror transistor T6having a drain coupled to the source of transistor T2and to the common resistor R1. Current mirror360may have a mirror transistor T5having a drain coupled to the input terminal INN and to the gate of transistor T2. The mirror transistors T3and T4may be source and gate coupled, wherein the gates may further be coupled to an output from the op-amp330. The mirror transistors T5and T6may be source and gate coupled, wherein the gates may further be coupled to an output from the op-amp340.

The circuit300may receive voltages, positive supply rail VDD and negative supply rail VSS, which may provide power for the current sources310,320and the current mirrors350,360. The current sources310,320may each be configured to generate equal predetermined currents. The resistance for resistor R1may be set to a value such that determines the negative impedance for the circuit300.

Each level shifting transistor T1, T2may level shift a respective member of a differential input signal at input terminals INPand INNand apply this signal across the resistor R1. The current mirrors350,360may operate in a fixed current feedback manner to mirror signal changes present at the circuit300inputs INPand INNback to those respective inputs. The feedback currents for the respective current mirrors350,360may be fixed by the op-amps330,340driving the mirroring transistors for each current mirror—drain connected mirror transistors T3and T4for the first current mirror350, and drain connected mirror transistors T5and T6for the second current mirror360.

For one example, say a differential signal input at circuit input INPmay increase in voltage while a differential signal input at circuit input INNmay decrease in voltage. The increase in voltage at INPmay increase the current across R1from the level shifting transistor T1toward the level shifting transistor T2. Less current may flow into mirror transistor T3thus less current may be sunk through mirror transistor T4. Conversely, more current may flow into mirror transistor T6thus, more current may be sunk through mirror transistor T5. The effect of raising the voltage and lowering the current of mirror transistor T2and conversely lowering the voltage and raising the current at mirror transistor T5may emulate a negative impedance at the input terminals INPand INN.

The operation of the circuit300may generate a non-linear response with respect to the differential input signals that may be applied to INPand INN. Transistors T1and T2may not become fully conductive until the voltage applied to their respective gates overcomes a threshold voltage for each transistor. Thus, operation of the circuit300may be non-linear in response to input signal voltages which may be below the threshold voltage for each transistor. In an embodiment, a pair of voltage sources V1and V2may be coupled between respective input terminals and gates for respective level shifting transistors T1, T2to correct the nonlinearity. The voltage sources V1and V2may bootstrap the level shifting transistors T1and T2so that their drain-source voltage may remain independent of input signal voltages. However, the operating range for the circuit may be limited by the amount of level shifting required to facilitate bootstrapping transistors T1and T2.

FIG. 4illustrates a negative impedance circuit400according to another embodiment of the present invention. As illustrated inFIG. 4, the circuit400may include a differential op-amp410having a positive input terminal coupled to an input terminal INPthrough a first resistor R1, and a negative input terminal coupled to an input INNthrough a second resistor R2. The op-amp410may have a negative output terminal OUT_NEG coupled in an inverting manner to the op-amp410positive input terminal through a third resistor R3. The op-amp410may have a positive output terminal OUT_POS coupled in an inverting manner to the op-amp410negative input terminal through a fourth resistor R4. The circuit400may include current mirrors CM1and CM2coupled respectively to output terminals OUT_NEG and OUT_POS and to opposite terminals of a common resistor R5. The circuit400may receive voltages, positive supply rail VDD and negative supply VSS, which may provide operating power to the differential op-amp410.

The input terminals INPand INNmay have a predetermined common-mode potential. Common-mode control for the op-amp410outputs OUT_POS and OUT_NEG may be set by a common-mode controller (not shown) internal to the op-amp410. The resistance for resistor R5may be set to a value that determines the negative impedance of the circuit400. The resistance may be tailored to suit individual design needs for the circuit400. The resistances for resistors R1-R4may be set such that they be greater in magnitude than resistor R5and may be balanced for each respective op-amp output (e.g., R1and R2may have equal resistances; R3and R4may have equal resistances).

During operation, the circuit400may be configured to generate an inverting voltage gain from op-amp410across resistor R5. Differential input signals that may be input to the circuit400at input terminals INPand INNmay be replicated across the resistor R5. The op-amp410may generate differential output voltages that may drive a current through the resistor R5. As the op-amp410may generate the output signals, respective currents IOUT_POS and IOUT_NEG may be mirrored back to the respective inputs INPand INNfrom respective current mirrors CM1and CM2. The currents IOUT_POS and IOUT_NEG may propagate out the respective input terminals INP, INN, which may emulate a negative impedance at the input terminals INPand INN.

For example, say a differential signal input at the input terminal INPmay increase in amplitude while a differential signal input at the input terminal INNmay decrease in amplitude. In turn, the voltage output from the terminal OUT_POS may increase while the voltage output from the terminal OUT_NEG may decrease. The current flow through the resistor R5may increase from the OUT_POS terminal toward the OUT_NEG terminal. The current IOUT_POS flowing from the output terminal OUT_POS may be mirrored through CM1back to the input terminal INP. The current IOUT_NEG flowing from the output terminal OUT_NEG may be mirrored through CM2back the input terminal INN. The circuit400may operate in a reverse manner if a signal input at input INPmay decrease in amplitude while a signal input at input INNmay increase in amplitude.

FIG. 5illustrates a common-mode controller500according to an embodiment of the present invention. As illustrated inFIG. 5, the common-mode controller500may include an op-amp510having a pair of outputs OUT1and OUT2coupled to a respective a first and second resistor R1and R2. Each resistor R1and R2may further be coupled to an inverting input terminal for the op-amp510. The op-amp510may further receive a reference voltage VREFcoupled to a non-inverting input terminal for the op-amp. The controller500may receive voltages, positive supply rail VDD and negative supply rail VSS, which may provide operating rails to the op-amp510. The output terminals OUT1and OUT2may further be coupled to respective input terminals for a negative impedance circuit (i.e., input terminals INPand INNofFIG. 2). The resistances for the first and second resistors R1and R2may be equal to each other. Clearly, the resistances for resistors R1and R2may be set sufficiently high to ensure that the resistors R1and R2do not excessively load the negative impedance circuit.

During operation, the average voltage between OUT1and OUT2(as driven across R1and R2) may be input to the inverting terminal of the op-amp510. The op-amp510may compare the average voltage to the reference voltage VREFand steer its respective output currents toward the reference voltage VREF. Thus, the controller500may dynamically control a negative impedance circuit to manage voltage drift for the circuit with respect to the reference voltage VREF.

FIG. 6illustrates a method600for developing a negative impedance according to an embodiment of the present invention. As illustrated inFIG. 6, the method600may derive an internal current from differential input voltages (block610). The method600may drive the current through an internal resistance (block620). The method600may mirror the current to input terminals to emulate the effect of a negative impedance (block630).

Several embodiments of the present invention are specifically illustrated and described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings. In other instances, well-known operations, components and circuits have not been described in detail so as not to obscure the embodiments. It can be appreciated that the specific structural and functional details disclosed herein may be representative and do not necessarily limit the scope of the embodiments.

Those skilled in the art may appreciate from the foregoing description that the present invention may be implemented in a variety of forms, and that the various embodiments may be implemented alone or in combination. Therefore, while the embodiments of the present invention have been described in connection with particular examples thereof, the true scope of the embodiments and/or methods of the present invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.