Regulator and high voltage generator including the same

A regulator includes a current path unit coupled between an input terminal and a ground terminal and including a first current determination unit coupled between the input terminal and a control node and configured to supply the high voltage to the control node so that a first or second current path is selected depending on a voltage of the control node, and a second current determination unit coupled between the control node and the ground terminal and configured to control the voltage of the control node depending on an input voltage, a voltage supply unit configured to supply the high voltage to an output terminal depending on the voltage of the control node, a voltage division unit configured to create a division voltage, and an amplification unit configured to amplify a difference between the division voltage and a first reference voltage.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Korean patent application number 10-2011-0100711 filed on Oct. 4, 2011, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Example embodiments relate to a high voltage generator and, more particularly, to a high voltage generator capable of reducing current consumption.

2. Related Art

A semiconductor memory device, in particular, a flash memory device requires high voltage for performing operations. A charge pump circuit for generating the high voltage is used in the flash memory device. A voltage regulator is used to control output voltage of the charge pump circuit. In a known regulator, the increase or decrease of current consumed in the regulator is changed depending on a high voltage output range. Thus, a large amount of current is necessary to maintain a pumping voltage. The required current leads to an increase in an internal consumption current (ICC), and thus the internal consumption current (ICC) of a memory chip is greatly influenced. Accordingly, the amount of current consumed in the regulator of the high voltage generator should be controlled.

BRIEF SUMMARY

In accordance with example embodiments, current necessary to drive a charge pump circuit can be minimized by minimizing current consumed by a regulator.

A regulator according to an aspect of the present disclosure includes a current path unit coupled between an input terminal and a ground terminal and configured to include a first current determination unit coupled between the input terminal and a control node and configured to supply the high voltage of a high voltage generator to the control node so that a first or second current path each having a different current load is selected depending on a voltage of the control node and a second current determination unit coupled between the control node and the ground terminal and configured to control the voltage of the control node by changing the current load depending on an input voltage, a voltage supply unit configured to supply the high voltage to an output terminal depending on the voltage of the control node, a voltage division unit configured to divide the high voltage supplied to the output terminal to create a division voltage, and an amplification unit configured to amplify a difference between the division voltage of the voltage division unit and a first reference voltage and output the amplified voltage to the second current determination unit.

A regulator according to another aspect of the present disclosure includes a current path unit coupled between an input terminal and a ground terminal and configured to include a first current determination unit coupled between the input terminal and a control node and configured to supply the high voltage of a high voltage generator to the control node and autonomously control a current load depending on a voltage of the control node and a second current determination unit coupled between the control node and the ground terminal and configured to control the voltage of the control node by changing the current load depending on an input voltage, a voltage supply unit configured to supply the high voltage to an output terminal depending on the voltage of the control node, a voltage division unit configured to divide the high voltage supplied to the output terminal, and an amplification unit configured to amplify a difference between the division voltage of the voltage division unit and a first reference voltage and output the amplified voltage to the second current determination unit.

In accordance with yet another aspect of the present disclosure, there is provided a high voltage generator including a first regulator for stabilizing an output voltage of a charge pump into a first regulation voltage and a second regulator for converting the first regulation voltage into a regular voltage, wherein the second regulator includes a current path unit coupled between an input terminal and a ground terminal and configured to include a first current determination unit coupled between the input terminal and a control node and configured to supply the high voltage of a high voltage generator to the control node so that a first or second current path having a different current load is selected depending on a voltage of the control node and a second current determination unit coupled between the control node and the ground terminal and configured to control the voltage of the control node by changing the current load depending on an input voltage, where the second regulator is configured to supply a high voltage to an output terminal.

DESCRIPTION OF EMBODIMENTS

Hereinafter, some example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The figures are provided to allow those having ordinary skill in the art to understand a scope of the embodiments of this disclosure.

FIG. 1is a circuit diagram of a high voltage generator according to a first embodiment of this disclosure, andFIG. 4Ais a waveform illustrating a current load according to voltage of a control node in the high voltage generator ofFIG. 1.

Referring toFIG. 1, the high voltage generator100according to the first embodiment of this disclosure includes an oscillator110, a clock driver120, a charge pump130, a first regulator140, and a second regulator150.

The oscillator110generates a clock signal CLK1having a specific frequency and outputs the clock signal CLK1to the clock driver120.

The clock driver120generates clock signals CLK2and CLK2bhaving opposite levels by delaying the clock signal CLK1in response to the output signal of a first comparator142included in the first regulator140. To this end, the clock driver120includes a first inverter group (not shown) in which n inverters are coupled in series and a second inverter group (not shown) in which (n+1) inverters are coupled in series.

The charge pump130generates a pumping voltage VPP by performing a pumping operation in response to the clock signals CLK2and CLK2b.

The first regulator140stabilizes the pumping voltage VPP into a regular voltage and supplies the stabilized pumping voltage VPP as a first regulation voltage. The first regulator140includes a first voltage divider144for generating a first division voltage VL1by dividing the pumping voltage VPP, and the first comparator142for controlling the operation of the clock driver120by comparing the first division voltage VL1and a first reference voltage Vref_1.

The first voltage divider144includes a plurality of passive elements (preferably, first and second resistors R1and R2) and outputs the first division voltage VL1to the first comparator142according to a ratio of resistances of the resistors R1and R2.

The first and the second resistors R1and R2are coupled in series between the output terminal of the pumping voltage VPP and a ground terminal. The first division voltage VL1is inputted to the first comparator142according to a ratio of resistances of the resistors R1and R2.

If, as a result of the comparison, the first reference voltage Vref_1is higher than the first division voltage VL1, the first comparator142outputs a signal of a high level to the clock driver120. To this end, the first comparator142includes an amplifier (e.g., an OP AMP) having a non-inverting terminal (+) to which the first reference voltage Vref_1is inputted and an inverting terminal (−) to which the first division voltage VL1is inputted.

Accordingly, the final pumping voltage VPP becomes the first regulation voltage.

A ripple output of the first regulator140may be severe because the first regulator140generates the first regulation voltage VPP by controlling only whether the charge pump130is operated. In order to temper the ripple output, the second regulator150using a current control method is further added.

The second regulator150generates a second regulation voltage by converting the first regulation voltage VPP into a regular voltage. The second regulator150includes an amplification unit152, a second voltage divider154, a current path unit including first and second current determination units157and156, and a voltage supply unit158.

The second voltage divider154includes a plurality of passive elements (preferably, third to sixth resistors R3to R6). The second voltage divider154generates a second division voltage VL2by dividing the second regulation voltage according to a ratio of resistances of the resistors R3to R6. The second voltage divider154includes the third to sixth resistors R3to R6coupled in series between an output terminal Vout and the ground terminal, an NMOS transistor M4coupled between the third resistor R3and the fifth resistor R5in order to change the ratio and configured to couple the third resistor R3and the fifth resistor R5in response to a first control signal T<0>, where the NMOS transistor M4may operate as a switching element. The second voltage divider154may also include an NMOS transistor M3coupled between the third resistor R3and the sixth resistor R6and configured to couple the third resistor R3and the sixth resistor R6in response to a second control signal T<1> in order to change the ratio, where the NMOS transistor M3may operate as a switching element. The second voltage divider154outputs the second division voltage VL2to the amplification unit152according to a ratio of the resistances.

The amplification unit152controls the operation of the second current determination unit156by amplifying a difference between the second division voltage VL2and a second reference voltage Vref_2. To this end, the amplification unit152includes an amplifier (e.g., an OP AMP) having an inverting terminal (−) to which a second reference voltage Vref_2is inputted, and a non-inverting terminal (+) to which the second division voltage VL2is inputted. Here, the second reference voltage Vref_2having the same voltage level as the second division voltage VL2is supplied. The amplification unit152outputs a difference between the second division voltage VL2actually inputted and the second reference voltage Vref_2Accordingly, the amplification unit152outputs an analog signal according to the difference. The amplification unit152may output the analog signal to an output node nd.

The first current determination unit157and the second current determination unit156form a current path between the output terminal of the first regulator140and the ground terminal. The first current determination unit157includes a resistor RK coupled between the output terminal of the charge pump130and the second current determination unit156. The second current determination unit156includes an NMOS transistor M1turned on based on the output voltage of the amplification unit152, thus the NMOS transistor M1may operate as switching element. The NMOS transistor M1is coupled between the first current determination unit157and the ground terminal, and the NMOS transistor M1is configured to form a current path between the output terminal of the charge pump130(or the output terminal of the first regulator140) and the ground terminal. A diode (i.e., a unilateral element) (not shown) for preventing an adverse current may be further included, where the unilateral element may be coupled between the NMOS transistor M1and the ground terminal.

As described above, the amplification unit152outputs an analog signal according to a difference between the second reference voltage Vref_2and the division voltage VL2, where the amplification unit152outputs the analog signal to the output node nd. Thus, a current path is formed through the second current determination unit156. Here, the amount of current flowing through the formed current path is increased as the second division voltage VL2becomes higher than the second reference voltage Vref_2. Furthermore, when the current path is formed, the first regulation voltage VPP is decreased. When the second division voltage VL2is lower than the second reference voltage Vref_2, a low voltage is outputted from the amplification unit152in the form of a comparison signal. Thus, the NMOS transistor M1is turned off, thereby cutting off the current path.

The voltage supply unit158supplies the first regulation voltage VPP to the output terminal Vout of the second regulator150depending on the voltage of a control node rd. To this end, the voltage supply unit158includes an NMOS transistor M0coupled between the output terminal of the charge pump130and the output terminal Vout of the second regulator150, where the transistor NMOS transistor M0may operate as a switching element. Here, the voltage of the control node rd between the resistor RK and the second current determination unit156is supplied to the gate of the NMOS transistor M0.

If the current path is not formed, the voltage supply unit158directly supplies the first regulation voltage VPP to the gate of the NMOS transistor M0, thereby turning on the NMOS transistor MO. Thus, the first regulation voltage VPP is supplied to the output terminal Vout of the second regulator150. If the current path is formed, however, the degree that the NMOS transistor M0is turned on is changed depending on voltage supplied to the gate of the NMOS transistor M0. Thus, the amount of the first regulation voltage VPP supplied to the output terminal Vout of the second regulator150is also changed.

A load current consumed by the first regulator140and the second regulator150of the high voltage generator100is determined by the sum of a first load current I_load_1, a second load current I_load_2, and a third load current I_load_3. The first regulation voltage VPP maintains a fixed voltage, but the second regulation voltage of the output terminal Vout ranges from a maximum value Vout_H to a minimum value Vout_L. The maximum value Vout_H of the second regulation voltage is (R6+R5+R4+R3)/(R3)*Vref_2when the NMOS transistor M4and the NMOS transistor M3are turned off, and the minimum value Vout_L thereof is (R6+R3)/(R3)*Vref_2when the NMOS transistor M4is turned off and the NMOS transistor M3is turned on. Accordingly, the first load current I_load_1and the third load current I_load_3have a fixed value, whereas the second load current I_load_2has a variable value.

A change of the first load current I_load_1to the third load current I_load_3is described below.

The first regulation voltage VPP is determined by the first reference voltage Vref_1and a ratio of resistances of the first resistor R1and the second resistor R2(i.e., VPP=(R1+R2)/(R1)*Vref_1. Accordingly, the first load current I_load_1has a value of Vref_1/R1. When the first reference voltage Vref_1and resistance of the first resistor R1are determined, the first load current I_load_1becomes regular.

As described above, the gate of the NMOS transistor M0is coupled to the control node rd, and the source thereof is coupled to the output terminal Vout of the second regulator150. Thus, voltage of the control node rd and voltage of the output terminal Vout have a difference equal to the threshold voltage Vth of the NMOS transistor M0(i.e., Vrd=Vout+Vth). Since the voltage of the output terminal Vout of the second regulator150ranges from the maximum value Vout_H to the minimum value Vout_L, the voltage of the control node rd ranges from a maximum value Vrd_H (=Vout_H+Vth) to a minimum value Vrd_L (=Vout_L+Vth).

Referring toFIG. 4A, the second load current I_load_2of the high voltage generator100according to the first embodiment of this disclosure varies depending on a first load curve Load_a. Since the second load current I_load_2is determined by VPP−RD/RK, the second load current I_load_2has the first load curve Load_a in a load curve in which the voltage of the control node rd is an X axis and current is a Y axis. Here, the second load current I_load_2varies depending on the resistance of the resistor RK because the first load curve Load_a has a varying slope according to the resistance of the resistor RK.

As described above, the voltage of the control node rd varies depending on a gate voltage ND of the NMOS transistor M1included in the second current determination unit156. Accordingly, the second load current I_load_2is determined by an intersecting point of the first load curve Load_a and the Id curve of the NMOS transistor M1.

If the gate voltage ND is high, a current path is formed between the control node rd and the ground terminal because the NMOS transistor M1is turned on. Accordingly, the voltage of the control node rd is lowered. If the gate voltage ND is low, the NMOS transistor M1is not turned on, and thus a current path is not formed between the control node rd and the ground terminal. Accordingly, the voltage of the control node rd remains high.

When the gate voltage ND is a minimum value ND_L, the intersecting point of the first load curve Load_a and the Id curve of the NMOS transistor M1is a maximum value RD_H of voltage of the control node rd. In this case, the second load current I_load_2has a minimum value I_a. When the gate voltage ND is a maximum value ND_H, the intersecting point of the first load curve Load_a and the Id curve of the NMOS transistor M1is a minimum value RD_L of voltage of the control node rd. In this case, the second load current I_load_2has a maximum value I_c.

As described above, the second load current I_load_2has a variable current between the minimum value I_a and the maximum value I_c depending on the voltage of the control node rd.

The third load current I_load_3is regular because it is determined as Vref_2/R3irrespective of the voltage range Vout_L to Vout_H of the output terminal Vout.

Consequently, the first load current I_load_1and the third load current I_load_3have fixed values, whereas the second load current I_load_2has a variable value.

This disclosure provides regulators and a high voltage generator which can maintain the lowest current consumption while controlling the amount of the second load current I_load_2.

FIG. 2is a circuit diagram of a high voltage generator according to a second embodiment of this disclosure.

Referring toFIG. 2, the high voltage generator200according to the second embodiment of this disclosure includes an oscillator210, a clock driver220, a charge pump230, a first regulator240, and a second regulator250. The oscillator210, the clock driver220, the charge pump230, and the first regulator240have the same constructions as those of the high voltage generator100ofFIG. 1, and thus a redundant description thereof is omitted for simplicity.

The second regulator250includes a current path unit including a first current determination unit257and a second current determination unit256, a voltage supply unit258, a voltage division unit254, and an amplification unit252.

The current path unit may be coupled between an input terminal and a ground terminal. The current path unit includes the first current determination unit257and the second current determination unit256. The first current determination unit257is coupled between the input terminal and a control node rd. The first current determination unit257supplies a high voltage (i.e., a second regulator voltage VPP) from the first regulator240to the control node rd so that one of first and second current paths having different current loads is selected depending on voltage of the control node rd.

The first current determination unit257includes a first resistor RK, a second resistor RA, and an NMOS transistor M2which may operate as a switching element. The first resistor RK is coupled between the input terminal and the control node rd. The NMOS transistor M2and the second resistor RA are coupled in parallel between the first resistor RK and the control node rd. When the voltage of the control node rd is a specific level or higher, the NMOS transistor M2couples the first resistor RK and the control node rd in response to a gate signal C_NCON. The first current determination unit257may further include a comparator (not shown) for comparing a preset reference voltage and the voltage of the control node rd and outputting a result of the comparison to the gate of the NMOS transistor M2.

The second current determination unit256is coupled between the control node rd and the ground terminal and is configured to control the voltage of the control node rd by changing a current load depending on voltage of the output node nd of the amplification unit252. The second current determination unit256includes an NMOS transistor M1coupled between the control node rd and the ground terminal and configured to couple the control node rd and the ground terminal in response to the output signal of the amplification unit252. An NMOS transistor M1has a gate coupled to the output terminal nd of the amplification unit252, a drain coupled to the control node rd, and a source coupled to the ground terminal. Although not shown inFIG. 2, the second current determination unit256may further include a unilateral element (e.g., a diode) coupled between the NMOS transistor M1and the ground terminal.

The voltage supply unit258supplies the high voltage VPP to an output terminal Vout depending on the voltage of the control node rd. The voltage supply unit258includes an NMOS transistor M0for controlling the amount of the high voltage VPP, supplied to the output terminal Vout, depending on the voltage of the control node rd. The NMOS transistor M0has a gate coupled to the control node rd, a drain coupled to an input terminal, and a source coupled to the output terminal Vout.

The voltage division unit254divides the voltage supplied to the output terminal Vout. The voltage division unit254includes a third resistor R3to a sixth resistor R6coupled in series between the output terminal Vout and the ground terminal. A composite resistance of the third resistor R3to the sixth resistor R6is varied depending on whether an NMOS transistor M4and an NMOS transistor M3are turned on. Here, a division voltage VL2supplied to the third resistor R3is inputted to the amplification unit252.

When the amplification unit252receives the division voltage VL2and a reference voltage Vref_2, the amplification unit252amplifies a difference between the division voltage VL2and the reference voltage Vref_2and outputs the amplified voltage in the form of an analog signal. The amplification unit252outputs the analog signal to the output node nd by amplifying the difference between the division voltage VL2and the reference voltage Vref_2in order to control the voltage of the control node rd. The amplification unit252may include an amplifier (e.g., an OP AMP) having an inverting terminal (−) to which the reference voltage Vref_2is inputted and a non-inverting terminal (+) to which the division voltage VL2is inputted.

A method of controlling the second load current I_load_2of the second regulator250is described below.

FIG. 4Bis a waveform illustrating current loads according to voltage of the control node rd in the high voltage generator200ofFIG. 2.

Referring toFIGS. 2 and 4B, in the second embodiment of this disclosure, the amount of the second load current I_load_2can be minimized by controlling a load curve of the first and the second current determination units257and256for determining the second load current I_load_2. The second regulator100ofFIG. 1includes only the resistor RK, and the first current determination unit257controls the resistance of the resistor RK at the two load curves in order to suppress an increase of the maximum current I_c.

A factor to determine the amount of the second load current I_load_2inFIG. 4Ais the resistor RK. If the output range Vout_H to Vout_L of the second regulation voltage VPP is divided into a first section Vout_H to Vout_M and a second section Vout_M to Vout_L, a first load curve Load_a according to the resistance of the resistor RK controls the entire section RD_H to RD_L of voltage of the control node rd, but there exists a current path (when C_NCON=High is supplied to the gate of NMOS transistor M2) ranging from the first resistor RK to the NMOS transistor M1depending on a first load curve Load_a to control the first section RD_H to RD_M and a current path (when C_NCON=Low is supplied to the gate of NMOS transistor M2) ranging from the first resistor RK to the second resistor RA depending on a second load curve Load_b to control the second section RD_M to RD_L. In this case, a shift range of the second load current I_load_2becomes a second range I_a to I_b instead of the first range I_a to I_c inFIG. 4A. Accordingly, current necessary to maintain the output voltage (i.e., the second regulation voltage VPP) of the charge pump230by reducing the shift range of the second load current I_load_2can be minimized.

FIG. 3is a circuit diagram of a high voltage generator according to a third embodiment of this disclosure.

The high voltage generator300according to the third embodiment of this disclosure has the same construction as the high voltage generator200ofFIG. 2except that a first current determination unit357may differ. Therefore, a redundant description thereof of substantially similar components is omitted for simplicity.

Referring toFIG. 3, the first current determination unit357includes a high voltage PMOS transistor M5, which may operate as a switching element, coupled between the input terminal and the control node rd and configured to supply the high voltage VPP to the control node rd in response to a voltage supply signal C_PCON.

The high voltage PMOS transistor M5has a high breakdown voltage BV.

In the high voltage generator300according to the third embodiment of this disclosure, the high voltage PMOS transistor M5may be used in a part corresponding to the variable resistor circuit ofFIG. 2in order to minimize the amount of the second load current I_load_2.

FIG. 4Cis a waveform illustrating a current load according to voltage of the control node rd in the high voltage generator300ofFIG. 3.

Referring toFIGS. 3 and 4C, when the high voltage PMOS transistor M5is used in the first current determination unit357as described above, a third load curve Load_c, such as that shown inFIG. 4C, is obtained. That is, if the high voltage PMOS transistor M5is used as the current load of the first current determination unit357instead of the resistors as inFIG. 2, the second load current I_load_2can be minimized to a third range I_d to I_e because an increment of current in the saturation mode range of the high voltage PMOS transistor M5is very small. In this case, the third load curve Load_c is obtained, and the voltage of the control node rd may range from a minimum value RD_L to a maximum value RD_H.

FIG. 5is a waveform illustrating the number of clock signals supplied depending on a current load of the high voltage generator according to an embodiment of this disclosure.

Referring toFIG. 5, if the second load current I_load_2has a low current load (i.e., I_a) because it is changed between the minimum value I_a and the maximum value I_c, the high voltage VPP can be maintained although a clock signal CLOCK is supplied to the charge pump only twice. If the second load current I_load_2has a high current load (I_c), the high voltage VPP can be maintained only when the clock signal CLOCK is supplied to the charge pump three times or higher. Accordingly, if the amount of the second load current I_load_2is minimized as in the embodiments of this disclosure, the number of clock signals CLOCK supplied can be reduced.

In accordance with this disclosure, an operating current necessary for a pumping operation can be minimized by controlling a load of the regulator, and thus current consumed by a memory chip can be reduced.