Display apparatus

A display apparatus includes a lower substrate including a peripheral area around a display area, an upper substrate facing the lower substrate, a display unit in the display area including a pixel circuit and a display device electrically connected to the pixel circuit, a seal in the peripheral area to surround the display unit, the seal adhering the lower substrate to the upper substrate, a power supply line between the lower substrate and the seal such that at least a portion of the power supply line and the seal overlap each other, and a first thermally conductive layer between the power supply line and the lower substrate, at least a part of the first thermally conductive layer overlapping an end portion of the power supply line, the first thermally conductive layer being connected to the power supply line and extending toward an edge of the lower substrate.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2018-0108510, filed on Sep. 11, 2018, in the Korean Intellectual Property Office, and entitled: “Display Apparatus,” is incorporated by reference herein in its entirety.

BACKGROUND

Embodiments relate to a display apparatus.

2. Description of the Related Art

Since an organic light-emitting display apparatus is a self-emissive display apparatus that does not need an additional light source, the organic light-emitting display apparatus may operate at a low voltage and may be configured as a lightweight thin apparatus. Also, since the organic light-emitting display apparatus has high quality characteristics such as a wide viewing angle, a high contrast ratio, and a fast response time, the organic light-emitting display apparatus has attracted attention as a next-generation display apparatus.

SUMMARY

Embodiments are directed to a display apparatus including a lower substrate including a display area and a peripheral area around the display area, an upper substrate facing the lower substrate, a display unit located in the display area, the display unit including a pixel circuit and a display device electrically connected to the pixel circuit, a seal located in the peripheral area to surround the display unit, the seal adhering the lower substrate to the upper substrate, a power supply line located between the lower substrate and the seal such that at least a portion of the power supply line and the seal overlap each other, and a first thermally conductive layer located between the power supply line and the lower substrate such that at least a part of the first thermally conductive layer overlaps an end portion of the power supply line, the first thermally conductive layer being connected to the power supply line and extending toward an edge of the lower substrate.

The display apparatus may further include a first connection layer located between the power supply line and the first thermally conductive layer. The power supply line and the first thermally conductive layer may be connected to each other through the first connection layer.

The first connection layer may extend to the edge of the lower substrate such that an end surface of the first connection layer and an end surface of the edge of the lower substrate are aligned with each other.

An end surface of an end portion of the first thermally conductive layer may be exposed to the outside.

At least a part of the first thermally conductive layer including the end surface may have a pattern.

The end surface of the end portion of the first thermally conductive layer and an outer wall of the seal may be on a same plane.

The display apparatus may further include a first driver located under the power supply line and overlapping the seal, the first driver being located between the first thermally conductive layer and the display unit.

The display apparatus may further include a second thermally conductive layer connected to the power supply line and located between the power supply line and the lower substrate such that at least a part of the second thermally conductive layer and another end portion of the power supply line overlap each other.

The second thermally conductive layer and the first thermally conductive layer may be made of a same material.

The display apparatus may further include a second connection layer located between the power supply line and the second thermally conductive layer. The power supply line and the second thermally conductive layer may be connected to each other through the second connection layer.

The second connection layer is located between the seal and the display unit.

The display apparatus may further include a first driver located in an area between the first thermally conductive layer and the second thermally conductive layer located under the power supply line to overlap the seal and a second driver located in an area between the display unit and the second thermally conductive layer.

The second thermally conductive layer may extend toward the first driver.

The first driver may include an emission control driving circuit and the second driver may include a scan driving circuit.

The pixel circuit of the display unit may include a thin-film transistor including a semiconductor layer, a gate electrode having at least a part that overlaps the semiconductor layer, and a first conductive layer including at least one of a source electrode and a drain electrode, a storage capacitor located between the gate electrode and the first conductive layer, the storage capacitor including an upper electrode having at least a part that overlaps the gate electrode, and a second conductive layer located on the first conductive layer.

The power supply line and the second conductive layer may be made of a same material.

The first thermally conductive layer and the upper electrode may be made of a same material.

The display apparatus may further include a first interlayer insulating layer located between the gate electrode and the upper electrode, a second interlayer insulating layer located between the upper electrode and the first conductive layer, and an inorganic insulating layer located between the upper electrode and the second conductive layer. The first interlayer insulating layer, the second interlayer insulating layer, and the inorganic insulating layer extend to the edge of the lower substrate, and the power supply line is located on the inorganic insulating layer.

Outer walls of the lower substrate, the upper substrate, and the seal may be aligned with one another.

The first thermally conductive layer may include a metal material that is less reactive than a metal material of the power supply line.

DETAILED DESCRIPTION

Examples of a display apparatus for displaying an image may include a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic light-emitting display, a field emission display, a surface-conduction electron-emitter display, a plasma display, and a cathode ray display. Although an organic light-emitting display apparatus will be described as a display apparatus according to an embodiment, various types of display apparatuses may be used.

FIG. 1illustrates a plan view of a display apparatus1according to an embodiment.FIG. 2illustrates an equivalent circuit diagram of a pixel of the display apparatus1according to an embodiment.

Referring toFIG. 1, the display apparatus1may include a display unit10located on a lower substrate100. The display unit10may include pixels P connected to a scan line SL extending in a y-direction and a data line DL extending in an x-direction perpendicular to the y-direction. The display unit10may provide a predetermined image through light emitted by the pixels P and may define a display area DA.

Each pixel P may emit, for example, red, green, blue, or white light. Each pixel P may include a display device. The display device may include an organic light-emitting diode (OLED). The term ‘pixel P’ used herein refers to a pixel that emits red, green, blue, or white light as described above.

Referring toFIG. 2, the pixel P may include a pixel circuit PC connected to the scan line SL and the data line DL and an OLED connected to the pixel circuit PC. The pixel circuit PC may include a driving thin-film transistor (TFT) Td, a switching TFT Ts, and a storage capacitor Cst. The switching TFT Ts may be connected to the scan line SL and the data line DL. The switching TFT Ts may transmit a data signal input through the data line DL to the driving TFT Td according to a scan signal input through the scan line SL.

The storage capacitor Cst may be connected to the switching TFT Ts and a driving voltage line PL. The storage capacitor Cst may store a voltage corresponding to a difference between a voltage received from the switching TFT Ts and a driving voltage ELVDD supplied to the driving voltage line PL.

The driving TFT Td may be connected to the driving voltage line PL and the storage capacitor Cst. The driving TFT Td may control driving current flowing through the OLED from the driving voltage line PL according to a value of the voltage stored in the storage capacitor Cst. The OLED may emit light having a predetermined luminance due to the driving current. The OLED may emit, for example, red, green, blue, or white light.

Referring toFIG. 2, the pixel P is shown as including two TFTs and one storage TFT. In some implementations, various modifications may be made. For example, the pixel circuit PC of the pixel P may include three or more TFTs or may include two or more capacitors Cst.

Referring back toFIG. 1, a peripheral area PA may be located outside the display area DA. For example, the peripheral area PA may surround the display area DA. The portion of the peripheral area PA where the pixels P are not located may be a non-display area where no image is provided.

A driving circuit including, for example, a first driver, a second driver, a terminal unit40, a driving power supply line60, and a common power supply line70, may be located in the peripheral area PA. The first driver may include first and second light-emitting driving circuits30and32. The second driver may include first and second scan driving circuits20and22.

The first and second scan driving circuits20and22may be located in the peripheral area PA of the lower substrate100. The first and second scan driving circuits20and22may generate a scan signal and transmit the scan signal to each pixel P through the scan line SL. InFIG. 1, the first scan driving circuit20is shown as being located at the left of the display unit10and the second scan driving circuit22is shown as being located at the right of the display unit10. In some implementations, only one scan driving circuit may be provided.

The terminal unit40may be located at an end portion of the lower substrate100. The terminal unit40may include a plurality of terminals41,42,43,44, and45. The terminal unit40may be exposed without being covered by an insulating layer. The terminal unit40may be electrically connected to a flexible printed circuit board (FPCB). The terminal unit40may be located at a side of the lower substrate100where the first and second scan driving circuits20and22are not located.

The FPCB may electrically connect a controller55to the terminal unit40. A signal or power transmitted from the controller55may be applied through connection wirings21,31,41,51,61, and71connected to the terminal unit40.

The controller55may receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal and may generate a control signal for controlling operations of the first and second scan driving circuits20and22. The generated control signal may be transmitted to the first and second scan driving circuits20and22through the terminal44connected to the FPCB and the connection wirings21and31. Scan signals of the first and second scan driving circuits20and22may be applied to each pixel P through the scan line SL. The controller55may supply driving power ELVDD and common power ELVSS to the driving power supply line60and the common power supply line70through the terminals42and45connected to the FPCB and the connection wirings61and71. The driving power ELVDD may be supplied to each pixel P through the driving voltage line PL. The common power ELVSS may be supplied to a common electrode of the pixel P.

A data driving circuit50may be located on the FPCB. The data driving circuit50may apply a data signal to each pixel P. The data signal of the data driving circuit50may be applied to each pixel P through the connection wiring51connected to the terminal41and the data line DL connected to the connection wiring51. As shown inFIG. 1, the data driving circuit50may be located on the FPCB. In some implementations, the data driving circuit50may be located in the peripheral area PA of the lower substrate100.

The driving power supply line60may be located in the peripheral area PA. For example, the driving power supply line60may be located between the terminal unit40and a portion of the display unit10adjacent to the terminal unit40. The driving power ELVDD supplied through the connection wiring61connected to the terminal41may be supplied to each pixel P through the driving voltage line PL.

The common power supply line70may be located in the peripheral area PA and may partially surround the display unit10. For example, the common power supply line70may have a loop shape. A side of the loop shape adjacent to the terminal unit40may be open and may extend along edges of the lower substrate100excluding the terminal unit40.

The common power supply line70may be electrically connected to the connection wiring71connected to the terminal45. The common power supply line70may supply the common power ELVSS to a common electrode (e.g., a cathode) of the OLED of the pixel P. InFIG. 1, the connection wiring71is shown as contacting an end portion and an other end portion of the common power supply line70. In some implementations, the connection wiring71may have a loop shape that partially surrounds the display unit10and has an open side. When the connection wiring71contacts the end portion and the other end portion of the common power supply line70and when the connection wiring71partially surrounds the display unit10, the connection wiring71may extend beyond the common power supply line70toward an end portion of the lower substrate100, for example, toward the terminal unit40.

The first and second light-emitting driving circuits30and32may be located in the peripheral area PA of the lower substrate100. The first and second light-emitting driving circuits30and32may generate an emission control signal and transmit the emission control signal to each pixel P through an emission control line. In an embodiment, the first light-emitting driving circuit30may be located at the left of the display unit10and the second light-emitting driving circuit32may be located at the right of the display unit10. In some implementations, only one light-emitting driving circuit may be provided.

Referring toFIG. 1, the first and second scan driving circuits20and22may be located adjacent to the display unit10, and the first and second light-emitting driving circuits30and32may be located relatively adjacent to an edge of the lower substrate100. In this case, the first and second light-emitting driving circuits30and32may overlap the common power supply line70and may be located under the common power supply line70.

An upper substrate300may be located on the lower substrate100to face the lower substrate100. A seal400may be located between the lower substrate100and the upper substrate300. The seal400may surround the display unit10in the plan view ofFIG. 1. A space defined by the lower substrate100, the upper substrate300, and the seal400may be separated from an external space to prevent penetration of external moisture or impurities. The seal400may include, for example, an inorganic material such as fit. In some implementations, the seal400may include epoxy.

Referring toFIG. 1, the seal400may entirely surround the display unit10and the first and second scan driving circuits20and22. The display unit10and the first and second scan driving circuits20and22may be located in a space, for example, an inner space, defined by the lower substrate100, the upper substrate300, and the seal400.

The seal400may be located such that at least a part of the seal400and the common power supply line70overlap each other in the z direction. The first and second light-emitting driving circuits30and32may be located under the common power supply line70to overlap the common power supply line70in the z direction, and may also overlap the seal400in the z direction.

A first thermally conductive layer80may be located in the peripheral area PA of the lower substrate100. The first thermally conductive layer80may be located such that a part of the first thermally conductive layer80overlaps the seal400and the common power supply line70in the z direction. The first thermally conductive layer80may extend to an outermost portion including the edges of the lower substrate100. The first thermally conductive layer80may outwardly discharge heat produced by laser energy emitted to cure the seal400.

Referring toFIG. 1, the first thermally conductive layer80may have an open loop shape and may surround a part of the display unit10. The first thermally conductive layer80may be located along three edges of the lower substrate100. In some implementations, a width and a structure of the first thermally conductive layer80may be modified according to a desired heat dissipation efficiency, as will be described in detail with reference toFIG. 3and other figures.

FIG. 3illustrates a cross-sectional view of a display apparatus according to an embodiment.FIG. 3shows a view taken along line III-III′ ofFIG. 1.

Referring toFIG. 3, the display apparatus may include the display area DA and the peripheral area PA. Each of the lower substrate100and the upper substrate300may include the display area DA and the peripheral area PA.

The lower substrate100may include a suitable material such as a glass material, a metal material, or a plastic material (e.g., polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyimide). The upper substrate300may include a transparent material. For example, the upper substrate300may include a suitable material such as a glass material or a plastic material (e.g., PET, PEN, or polyimide). The lower substrate100and the upper substrate300may include the same material or different materials.

Referring to the display area DA ofFIG. 3, a buffer layer101may be formed on the lower substrate100. The buffer layer101may prevent moisture or a foreign material from penetrating through the lower substrate100. For example, the buffer layer101may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or/and silicon oxynitride (SiON), and may have a single layer structure or a multi-layer structure.

A TFT130and a storage capacitor140may be provided to correspond to the display area DA. A display device200may be electrically connected to the TFT130. The display device may be an OLED. The storage capacitor140may be located on the lower substrate100. The TFT130ofFIG. 3may correspond to one of TFTs, e.g., the driving TFT Td, provided in the pixel circuit PC ofFIG. 2. The storage capacitor140ofFIG. 3may correspond to the storage capacitor Cst ofFIG. 2.

The TFT130may include a semiconductor layer134and a gate electrode136. The semiconductor layer134may include, for example, polysilicon. The semiconductor layer134may include a channel region131overlapping the gate electrode136and a source region132and a drain region133located at both sides of the channel region131and having a higher impurity concentration than the channel region131. Impurities may include N-type impurities or P-type impurities. The source region132and the drain region133may be understood respectively as a source electrode and a drain electrode of the TFT130.

The semiconductor layer134may include polysilicon. In some implementations, the semiconductor layer134may include amorphous silicon or an organic semiconductor material. In another implementations, the semiconductor layer134may include an oxide semiconductor.

The pixel circuit PC may include the driving TFT Td and the switching TFT Ts ofFIG. 2. A semiconductor layer of the driving TFT Td and a semiconductor layer of the switching TFT Ts may include different materials. For example, one of the semiconductor layers of the TFT Td and the switching TFT Ts may include an oxide semiconductor, and the remaining one may include polysilicon.

A gate insulating layer103may be located between the semiconductor layer134and the gate electrode136. The gate insulating layer103may be an inorganic insulating layer formed of SiON, SiOx, and/or SiNx. The inorganic insulating layer may have a single layer structure or a multi-layer structure.

The storage capacitor140may include a lower electrode144and an upper electrode146overlapping each other in the z direction. A first interlayer insulating layer105may be located between the lower electrode144and the upper electrode146.

The first interlayer insulating layer105, which is a layer having a predetermined dielectric constant, may be an inorganic insulating layer formed of SiON, SiOx, and/or SiNx. The first interlayer insulating layer105may be formed to have a single layer structure or a multi-layer structure. As shown inFIG. 3, the storage capacitor140may overlap the TFT130. As shown inFIG. 3, the lower electrode144of the storage capacitor140may also serve as the gate electrode136of the TFT130. In some implementations, the storage capacitor140may not overlap the TFT130, and the lower electrode144may be an independent element separate from the gate electrode136of the TFT130.

The storage capacitor140may be covered by a second interlayer insulating layer107. The second interlayer insulating layer107may be an inorganic insulating layer formed of SiON, SiOx, and/or SiNx, and may be formed to have a single layer structure or a multi-layer structure.

The driving voltage line PL may be located on a first organic insulating layer111. The driving voltage line PL may include aluminum (Al), copper (Cu), or titanium (Ti) and may be formed to have a single layer structure or a multi-layer structure. In an embodiment, the driving voltage line PL may have a multi-layer structure formed of Ti/Al/Ti.

InFIG. 3, a lower driving voltage line PL1may be located under the first organic insulating layer111. The lower driving voltage line PL1may be electrically connected to the driving voltage line PL through a contact hole passing through the first organic insulating layer111. The lower driving voltage line PL1may prevent a voltage drop of the driving voltage ELVDD applied through the driving voltage line PL. The lower driving voltage line PL1may include the same material as the data line DL. For example, each of the lower driving voltage line PL1and the data line DL may include Al, Cu, or Ti, and may be formed to have a single layer structure or a multi-layer structure. In an embodiment, each of the lower driving voltage line PL1and the data line DL may have a multi-layer structure formed of Ti/Al/Ti or TiN/Al/Ti.

The first organic insulating layer111may include an organic insulating material. The organic insulating material may include an imide-based polymer, a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol-based group, an acryl-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and/or a blend thereof. In an embodiment, the first organic insulating layer111may include polyimide.

The driving voltage line PL may be covered by a second organic insulating layer113. The second organic insulating layer113may include an imide-based polymer, a general-purpose polymer such as PMMA or PS, a polymer derivative having a phenol-based group, an acryl-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and/or a blend thereof. In an embodiment, the second organic insulating layer113may include polyimide.

A pixel electrode210may be located on the second organic insulating layer113. A pixel-defining film120may be located on the pixel electrode210. The pixel-defining film120may have an opening that corresponds to each sub-pixel At least a central portion of the pixel electrode210may be exposed through the opening to define a pixel. The pixel-defining film120may increase a distance between an edge of the pixel electrode210and a common electrode230, thereby preventing an arc or the like from occurring between the edge of the pixel electrode210and the common electrode230. The pixel-defining film120may be formed of an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

An intermediate layer220may include a low-molecular-weight material or a high-molecular-weight material. When the intermediate layer220includes a low-molecular-weight material, the intermediate layer220may have a stacked structure of a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and/or an electron injection layer (EIL), and may include any of various organic materials such as copper phthalocyanine (CuPc), N,N′-di(naphthalene-1-yl)-N,N′-diphenyl-benzidine (NPB), or tris-8-hydroxyquinoline aluminum (Alq3). Such layers may be formed by using vacuum deposition.

When the intermediate layer220includes a high-molecular-weight material, the intermediate layer220may have a structure including an HTL and an EML. In this case, the HTL may include poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML may include a high-molecular-weight material such as a poly-phenylenevinylene (PPV)-based material or a polyfluorene-based material. The intermediate layer220may have any of various other structures. For example, at least one of layers constituting the intermediate layer220may be integrally formed over a plurality of the pixel electrodes210. In some implementations, the intermediate layer220may include a layer that is patterned to correspond to each of the plurality of pixel electrodes210.

The common electrode230may be located over the display area DA to cover the display area DA. The common electrode230may be integrally formed to cover a plurality of pixels.

A filler may be located between the common electrode230and the upper substrate300. The filler may include, for example, at least one of a photocurable epoxy-based material and an acrylate-based material.

Referring to the peripheral area PA ofFIG. 3, a driving circuit including, for example, a first driver and a second driver, may be located on the lower substrate100. The first driver may be the first light-emitting driving circuit30, and the second driver may be the first scan driving circuit20.

Each of the first scan driving circuit20and the first light-emitting driving circuit30may include TFTs and a wiring connected to the TFTs. The TFTs may be formed in the same process as that used to form the TFT130of the pixel circuit PC.

Each of the first scan driving circuit20and the first light-emitting driving circuit30may include an insulating layer located between elements (e.g., a semiconductor layer and a gate electrode) constituting the TFTs. For example, at least one of the buffer layer101, the gate insulating layer103, and the first and second interlayer insulating layers105and107may extend to the peripheral area PA to form an insulating layer110. The insulating layer110includes an inorganic insulating material.

The first scan driving circuit20may be located closer to the display area DA than the first light-emitting driving circuit30. As shown inFIG. 3, portions, portions of the first and second organic insulating layers111and113on the first scan driving circuit20may extend to the peripheral area PA to cover the first scan driving circuit20. In some implementations, the first and second organic insulating layers111and113may not cover the first scan driving circuit20, and only an inorganic insulating layer109may be located on the first scan driving circuit20.

The first scan driving circuit20and the first light-emitting driving circuit30may be covered by the inorganic insulating layer109. The inorganic insulating layer109may prevent the connection wiring71including a metal such as Al, which is susceptible to damage from an etchant used in a process of manufacturing the display apparatus, from being exposed to an etching environment. As shown inFIG. 3, the inorganic insulating layer109may also located in the display area DA.

The inorganic insulating layer109may include an inorganic material such as SiOx, SiNx, or/and SiON, and may be formed to have a single layer structure or a multi-layer structure. In an embodiment, the inorganic insulating layer109may include SiNx. The inorganic insulating layer109may have a thickness equal to or greater than about 500 Å. In some implementations, a thickness of the inorganic insulating layer109may be equal to or greater than 1,000 Å, equal to or greater than 1,500 Å, equal to or greater than 2,000 Å, equal to or greater than 2,500 Å, equal to or greater than 3,000 Å, equal to or greater than 3,500 Å, equal to or greater than 4,000 Å, equal to or greater than 4,500 Å, equal to or greater than 5,000 Å, equal to or greater than 5,500 Å, equal to or greater than 6,000 Å, or equal to or greater than 6,500 Å. In some implementations, the inorganic insulating layer109may have a thickness ranging from about 7,000 Å to about 10,000 Å.

The common power supply line70may overlap the first light-emitting driving circuit30with the inorganic insulating layer109therebetween. The common power supply line70may include the same material as the driving voltage line PL. A first end portion70E1of the common power supply line70may be covered by the seal400. A second end portion70E2that is opposite to the first end portion70E1may extend toward the display area DA and may be covered by a conductive film212.

In an embodiment, the second end portion70E2of the common power supply line70may further extend toward the display area DA and may contact the first organic insulating layer111and/or the second organic insulating layer113. In an embodiment, the second end portion70E2of the common power supply line70may be covered by the seal400, like the first end portion70E1.

The seal400may overlap the first light-emitting driving circuit30and the common power supply line70. The seal400may adhere the lower substrate100to the upper substrate300with the first light-emitting driving circuit30and the common power supply line70therebetween.

When the display apparatus includes the seal400and is manufactured by using a method of cutting a panel in the present embodiment, the lower substrate100, the seal400, and the upper substrate300may be cut together along a cutting line CL in a manufacturing process. Accordingly, an edge100E of the lower substrate100, an edge300E of the upper substrate300, and an outer wall400OE of the seal400may be aligned with one another, and may be on the same plane, for example, on the same vertical plane.

A first thermally conductive layer80may be located between the common power supply line70and the lower substrate100. At least a part of the first thermally conductive layer80may overlap the first end portion70E1of the common power supply line70. The first thermally conductive layer80may extend to the edge100E of the lower substrate100. Accordingly, an end surface80E of an end portion of the first thermally conductive layer80may be exposed to the outside of the panel. As described above, the end surface80E of the first thermally conductive layer80may be aligned with the edge100E of the lower substrate100, the edge300E of the upper substrate300, and the outer wall400OE of the seal400.

As shown inFIG. 3, the first thermally conductive layer80and the upper electrode146of the pixel circuit PC of the display area DA may be located on the same layer and may include the same material. In an embodiment, the first thermally conductive layer80and at least one of the data line DL of the pixel circuit PC, the upper electrode146, and the gate electrode136may be located on the same layer and may include or be made of the same material.

The first thermally conductive layer80may be physically connected to the common power supply line70with a first connection layer82therebetween. As shown inFIG. 3, the first connection layer82and the data line DL of the pixel circuit PC are located on the same layer and include the same material. The first connection layer82may be located between the first light-emitting driving circuit30and the edge100E of the lower substrate100.

In a general method, a driver such as a first light-emitting driving circuit and a common power supply line are located in a region separate from a seal, unlike in the present disclosure, and thus a dead area that is a non-emitting portion may be increased.

In the present disclosure, a dead area may be reduced by locating the first light-emitting driving circuit30in the peripheral area PA to be under the common power supply line70, thereby allowing the first light-emitting driving circuit30and the common power supply line70to overlap each other, and allowing the seal400to overlap at least a part of the common power supply line70.

However, in this structure, in a curing process of emitting laser energy to the seal400to adhere the lower substrate100to the upper substrate300through the seal400, the first light-emitting driving circuit30located under the seal400may be susceptible to damage due to heat. Even if damage to the first light-emitting driving circuit30were to be prevented by increasing a width W1of the common power supply line70between the seal400and the first light-emitting driving circuit30, heat transferred to the common power supply line70may not be dissipated to the outside but may be transferred to the first light-emitting driving circuit30located under the common power supply line70.

In the display apparatus according to an embodiment, heat applied to the common power supply line70due to laser energy in a process of curing the seal400after the lower substrate100is adhered to the upper substrate300may be easily diffused to the outside of the panel by locating the first thermally conductive layer80under the common power supply line70.

FIG. 4illustrates a cross-sectional view of a stage of a process of manufacturing the display apparatus ofFIG. 1.

Referring toFIG. 4, a process of curing the seal400may be performed in the peripheral area PA of the display apparatus by emitting laser energy L after the lower substrate100has been adhered to the upper substrate300. A display panel may be formed by simultaneously cutting the upper substrate300, the seal400, the lower substrate100, and the first thermally conductive layer80along the cutting line CL.

InFIG. 4, the laser energy L is emitted from the upper substrate300toward the seal400. The laser energy L provides high temperature heat H. The heat H transferred to cure the seal400may be transferred to the common power supply line70, which is a conductive layer that is in surface contact with the seal400.

In the present embodiment, the heat H transferred to the common power supply line70may be transferred to the first thermally conductive layer80connected to the common power supply line70through the first connection layer82. The heat H may be diffused to the outside of the panel along the first thermally conductive layer80. Accordingly, in the display apparatus according to an embodiment, a dead area may be reduced by locating the seal400, the common power supply line70, and the first light-emitting driving circuit30to overlap each other. Deterioration of the first light-emitting driving circuit30in a process of curing of the seal400may be prevented or reduced by providing the first thermally conductive layer80having a heat dissipation structure.

FIG. 5illustrates a cross-sectional view of a display apparatus2according to an embodiment.

The display apparatus2ofFIG. 5, as compared to the embodiment ofFIG. 3, further includes a second thermally conductive layer90located under the common power supply line70. The display area DA other than the peripheral area PA may be the same as that ofFIG. 3Thus an explanation thereof will not be repeated and the following will focus on differences.

InFIG. 5, the second thermally conductive layer90may be located between the common power supply line70and the lower substrate100. The second thermally conductive layer90may overlap the second end portion70E2of the common power supply line70. A side of the second thermally conductive layer90may be substantially aligned with the second end portion70E2of the common power supply line70, and the other side of the second thermally conductive layer90may extend toward the first light-emitting driving circuit30. In this case, the second thermally conductive layer90may be spaced apart from the first light-emitting driving circuit30by a predetermined interval.

InFIG. 5, the second thermally conductive layer90and the upper electrode146of the pixel circuit PC of the display area DA may be located on the same layer and may include the same material. In an embodiment, the second thermally conductive layer90and at least one of the data line DL of the pixel circuit PC, the upper electrode146, and the gate electrode136may be located on the same layer and may include the same material.

Although the first thermally conductive layer80and the second thermally conductive layer90are shown inFIG. 5as being located on the same layer, in some implementations, the first thermally conductive layer80and the second thermally conductive layer90may be located on different layers.

The second thermally conductive layer90may be physically connected to the common power supply line70with a second connection layer92therebetween. When the second thermally conductive layer90is physically connected to the common power supply line70, heat transferred to the common power supply line70may be diffused to the second thermally conductive layer90through the second connection layer92.

For example, the second thermally conductive layer90and the second connection layer92may diffuse heat applied to the common power supply line70due to laser energy applied in a process of curing of the seal400after the lower substrate100is adhered to the upper substrate300, in a similar manner as the first thermally conductive layer80and the first connection layer82. However, since the end surface80E of the first thermally conductive layer80is exposed to the outside of the panel whereas the second thermally conductive layer90does not have a portion exposed to the outside, the first thermally conductive layer80may perform a main heat dissipation function and the second thermally conductive layer90may perform an auxiliary heat dissipation function.

The first connection layer82and the data line DL of the pixel circuit PC may be located on the same player and include the same material. The first connection layer82may be located between the first light-emitting driving circuit30and the edge100E of the lower substrate100.

InFIG. 5, the first width W1of the common power supply line70may be greater than a width of the first light-emitting driving circuit30. The common power supply line70may cover the first light-emitting driving circuit30. The first end portion70E1of the common power supply line70may extend toward the edge100E of the lower substrate100and the second end portion70E2of the common power supply line70may extend toward the first scan driving circuit20.

End portions of the second connection layer92and the second thermally conductive layer90may be substantially aligned with each other with respect to the second end portion70E2of the common power supply line70. When the second connection layer92and the second thermally conductive layer90providing a path through which heat is diffused are located so that the end portions of the second connection layer92and the second thermally conductive layer90are substantially aligned with each other with respect to the second end portion70E2of the common power supply line70, heat applied in forming the seal400may be prevented from being transferred to the first scan driving circuit20located adjacent to the display area DA.

The second connection layer92and the second end portion70E2of the common power supply line70may be connected through a first contact hole CH1formed in the inorganic insulating layer109. The second connection layer92may be connected through a second contact hole CH2formed in the second interlayer insulating layer107. As shown inFIG. 5, the first contact hole CH1and the second contact hole CH2may overlap each other.

Even if the first contact hole CH1and the second contact hole CH2were to not overlap each other, as in some implementations, the first contact hole CH1and the second contact hole CH2do not overlap the seal400. When the first contact hole CH1and the second contact hole CH2, providing a path through which heat applied in forming the seal400is diffused, do not overlap the seal400, higher heat diffusion efficiency may be achieved.

Positions of the first contact hole CH1and the second contact hole CH2may be determined by a position of the second connection layer92. Accordingly, when the first contact hole CH1and the second contact hole CH2do not overlap the seal400, the second connection layer92may also not overlap the seal400. For example, the second connection layer92may be located between an inner surface400IE of the seal400and the first scan driving circuit20.

FIG. 6illustrates a plan view of a portion of a display apparatus1A according to an embodiment.FIG. 7illustrates a plan view of a part of a display apparatus1B according to an embodiment.FIGS. 6 and 7illustrate plan views of a structure of the first thermally conductive layer80overlapping the first end portion70E1of the common power supply line70.

Referring toFIG. 6, at least a part of the first thermally conductive layer80may overlap the common power supply line70. The first connection layer82may be located between the first thermally conductive layer80and the common power supply line70. The end surface80E of the first thermally conductive layer80may be aligned with the edge100E of the lower substrate100and may be exposed to the outside, as shown inFIG. 3.

InFIG. 6, a left portion of the common power supply line70and a right portion of the first thermally conductive layer80may overlap each other. The first connection layer82may be located in overlapping portions of the common power supply line70and the first thermally conductive layer80. The first connection layer82may be connected to the common power supply line70and the first thermally conductive layer80through a contact hole CH.

The first thermally conductive layer80may be integrally formed without an additional pattern for effective heat dissipation. For example, heat dissipation efficiency increases as the area of the first thermally conductive layer80increases. Accordingly the first thermally conductive layer80may be integrally formed as shown in the plan view ofFIG. 1.

In a modified embodiment, at least a part of the first thermally conductive layer80including the end surface80E ofFIG. 7may be formed to have a pattern80P. As described with reference toFIG. 3, the upper substrate300, the seal400, the lower substrate100, and the first thermally conductive layer80on the lower substrate100may be simultaneously cut along the cutting line CL. In this case, cutting the first thermally conductive layer80including a metal may be more difficult than cutting other structures, and metal fragments in the cutting process could be introduced into the panel in this cutting process.

Accordingly, a process of cutting the first thermally conductive layer80may be facilitated by patterning a portion of the first thermally conductive layer80corresponding to the cutting line CL and removing a part of the first thermally conductive layer80.

A part of the first thermally conductive layer80is shown inFIG. 7as having a slit shape including the pattern80P In some implementations, the first thermally conductive layer80may have other suitable shapes.

FIG. 8illustrates is a plan view of a display apparatus1B′ that is a modification ofFIG. 7, illustrating a step before a cutting process. Referring toFIG. 8, the end surface80E of the first thermally conductive layer80may be aligned with the cutting line CL. Accordingly, it is desirable that patterns of the first thermally conductive layer80be formed to correspond to the cutting line CL. Defects due to difficulty in cutting the first thermally conductive layer80during a cutting process may be reduced or prevented by continuously forming hole patterns HP in a portion corresponding to the cutting line CL. Heat dissipation efficiency of the first thermally conductive layer80may be improved by minimizing the area of the hole patterns HP formed in the portion corresponding to the cutting line CL to maximize the area of the first thermally conductive layer80.

FIG. 9illustrates a plan view of a part of a display apparatus1C according to an embodiment.FIG. 9illustrates a plan view of a structure of the second thermally conductive layer90overlapping the second end portion70E2of the common power supply line70.

InFIG. 9, a right portion of the common power supply line70and the second thermally conductive layer90completely overlap each other. The second connection layer92is located between the common power supply line70and the second thermally conductive layer90. The second connection layer92is connected to the common power supply line70and the second thermally conductive layer90through a contact hole CH.

The second thermally conductive layer90has no issues regarding cutting, unlike the first thermally conductive layer80. Accordingly, the second thermally conductive layer90may be integrally formed without a patterned portion. The second thermally conductive layer90may extend toward an edge of the lower substrate100that is opposite to a display area in order to minimize damage to an adjacent driving circuit that could be caused by heat transferred to the second thermally conductive layer90. The second thermally conductive layer90may be spaced apart from the first light-emitting driving circuit30by a predetermined interval D.

FIG. 10illustrates a cross-sectional view of a portion of a display apparatus3according to another embodiment.FIG. 10illustrates a portion of the peripheral area PA including the edge100E of the lower substrate100and a part of the seal400.

The embodiment ofFIG. 10may be the same as one of the above embodiments except for structure of the first connection layer82.

As shown inFIG. 10, the first connection layer82may extend to the edge100E of the lower substrate100. The end surface82E of the first connection layer82and the edge100E of the lower substrate100may be aligned with each other.

The end surface82E of the first connection layer82may be exposed to the outside, like the end surface80E of the first thermally conductive layer80. Accordingly, the end surface82E of the first connection layer82and the end surface80E of the first thermally conductive layer80may be aligned with each other and may be on the same plane.

When the first connection layer82extends to the edge100E of the lower substrate100, like the first thermally conductive layer80, and is exposed to the outside of a panel, higher heat dissipation efficiency may be achieved.

When the end surfaces82E and80E of the first connection layer82and the first thermally conductive layer80are exposed to the outside of the panel, in the end surfaces82E and80E could be susceptible to oxidation. Accordingly, a metal material included in each of the first connection layer82and the first thermally conductive layer80may include a metal that is less reactive than a metal material included in the common power supply line70. For example, when the common power supply line70includes aluminum (Al), each of the first connection layer82and the first thermally conductive layer80may include molybdenum (Mo), which is less reactive than Al.

The configuration may apply even when only the end surface80E of the first thermally conductive layer80is exposed to the outside of the panel.

By way of summation and review, various display apparatuses including an organic light-emitting display apparatus may display a predetermined image to a user. Research has been conducted to reduce a dead area where an image is not displayed in accordance with various consumer demands.

Embodiments relate to a display apparatus including a display area and a dead area, wherein damage to the display area due to heat in a manufacturing process of the display apparatus may be minimized and the dead area may be reduced.