Pulsed time-of-flight sensor, pulsed time-of-flight pixel array and operation method therefor

A pToF sensor, a pToF pixel array and an operation method therefor are provided. The pToF pixel array includes a plurality of pToF pixels distributed in an array, a control circuit, and a conversion circuit. Each of the pToF pixels includes a photo sensitive unit configured to detect a return signal of a light pulse signal, and a first conversion unit configured to convert a time signal corresponding to each of the pToF pixels to an analog signal. The control circuit is connected to each of the pToF pixels, and configured to control an operation mode of each of the pToF pixels. The conversion circuit is connected to each of the pToF pixels, and configured to calculate a time-of-fight corresponding to each of the pToF pixels according to the analog signal corresponding to each of the pToF pixels.

TECHNICAL FIELD

The present disclosure relates to the field of the sensor technologies for Light Detection and Ranging (LiDAR), and more particularly relates to a pulsed Time-of-Flight (pToF) sensor, a pulsed Time-of-Flight pixel array and an operation method therefor.

BACKGROUND

LiDAR is more and more demanded than before in recent years for autonomous driving, robots, face ID,3D modeling and AR/VR (Augmented Reality/Virtual Reality) applications, etc. Particularly for the autonomous driving, a long range operation under strong background sunshine is highly demanded, which requires a high sensitivity and a fast ToF (Time-of-Flight) response. A structure of a pulsed ToF sensor is theoretically preferred because of the following fundamental advantages.

a) Strong but ultra-short laser pulses significantly increase signal-noise-ratio (SNR) during a ToF operation, within the limitation of eye-safe regulations.

b) A pulsed operation mode is better to catch time points more accurately within a single shot, compared with that of a continuous wave (CW) operation mode.

However, regardless of these fundamental advantages, the development of a large scale array of the pToF sensors is somehow lagged behind.

SUMMARY

A pulsed Time-of-Flight (pToF) sensor, a pulsed Time-of-Flight pixel array and an operation method therefor are provided, which are suitable for implementing both small and large scale array integration.

A pToF pixel array is provided according to an aspect of the present disclosure.

The pToF pixel array includes a plurality of pToF pixels distributed in an array, a control circuit, and a conversion circuit. Each of the pToF pixels includes a photo sensitive unit configured to detect a return signal of a light pulse signal, and a first conversion unit provided inside of each of the pToF pixels and configured to convert a time signal corresponding to each of the pToF pixels to an analog signal. The control circuit is provided outside of the pToF pixels, connected to each of the pToF pixels, and configured to control an operation mode of each of the pToF pixels. The conversion circuit is provided outside of the pToF pixels, connected to each of the pToF pixels, and configured to calculate a time-of-fight corresponding to each of the pToF pixels according to the analog signal corresponding to each of the pToF pixels, wherein the time-of-flight is a time from sending out the light pulse signal to receiving the return signal of the light pulse signal by each of the pToF pixels.

A pToF sensor is provided according to another aspect of the present disclosure.

The pToF sensor includes a pToF pixel array. The pToF pixel array includes a plurality of pToF pixels distributed in an array, a control circuit, and a conversion circuit. Each of the pToF pixels includes a photo sensitive unit configured to detect a return signal of a light pulse signal, and a first conversion unit provided inside of each of the pToF pixels and configured to convert a time signal corresponding to each of the pToF pixels to an analog signal. The control circuit is provided outside of the pToF pixels, connected to each of the pToF pixels, and configured to control an operation mode of each of the pToF pixels. The conversion circuit is provided outside of the pToF pixels, connected to each of the pToF pixels, and configured to calculate a time-of-fight corresponding to each of the pToF pixels according to the analog signal corresponding to each of the pToF pixels, wherein the time-of-flight is a time from sending out the light pulse signal to receiving the return signal of the light pulse signal by each of the pToF pixels.

An operation method for a pToF pixel array is provided according to another aspect of the present disclosure.

The pToF pixel array includes a plurality of pToF pixels distributed in an array, and the operation method for a pToF pixel array includes: receiving a pixel address and mode information; when the mode information indicates a first mode, triggering sending out of a light pulse signal, and obtaining a first voltage signal when sending out the light pulse signal simultaneously; storing the first voltage signal when the pToF pixel corresponding to the pixel address receives a return signal of the light pulse signal in a preset time period and a signal value of the return signal is higher than a preset threshold value; obtaining a second voltage signal and a third voltage signal related to the first voltage signal after the pToF pixel corresponding to the pixel address receives the return signal of the light pulse signal in the preset time period and the signal value of the return signal is higher than the preset threshold value; and and calculating a time-of-flight corresponding to the pToF pixel corresponding to the pixel address, wherein the time-of-flight is a time from sending out the light pulse signal to receiving the return signal of the light pulse signal by the pToF pixel.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a diagram illustrating a structure of a pToF array according to the prior art. In this structure, the pToF array includes a plurality of pToF pixels100. Each of the pToF pixels100includes a photo sensitive device with its direct supporting circuit, referred to as “PD”120inFIG. 1, and a Time-to-Digital Converter (TDC)110provided inside of the PD120. Within each of the pToF pixels100, one TDC110corresponds to one PD120. To accurately catch a waveform of a fast transient response of the PD120, a very fast TDC110beyond gigahertz is normally required. When trying to integrate such pToF pixel structure into a large scale array, several structural issues will occur.

Firstly, due to the added complexity of the fast TDC110in the pToF pixel100, normally a pixel size of the pToF pixel100is relatively large with a reduced fill-factor. The fill-factor herein means a ratio of an effective light sensitive area over a total pixel layout area.

Secondly, the added TDCs in the pToF pixel100also increase a gap area between the neighbor pToF pixels100. It is not a big issue in a traditional photography imaging system, but it could be a more serious issue in a LiDAR application. Specifically, some small objects, such as a thin pillar, may not be detected by the LiDAR application because of the relatively large gap area between the neighbor pFoF pixels100, which could lead to a potential accident.

Thirdly, the fast TDC110in the pToF pixel100normally consumes a certain amount of power. When a large number of the fast TDCs110in the pToF pixel100are used for a large scale array, the total power consumption may be significant. The large power consumption not only adds a heavy burden to a system power budget, but also heats up the array locally, thereby causing the drop in performance or even the occurrence of a malfunction at a high temperature.

Last but not least, the fast TDC100in the pToF pixel100normally requires a high speed clock signal with a minimum jitter and delay. Unfortunately, distributing a multi-gigahertz clock signal into each pToF pixel100within a large scale array evenly and quietly is nearly a mission-impossible. As a result, a conversion error introduced by a jitter and delay variation between each pToF pixels100will definitely cause a significant drop in performance drop when trying to implement a large scale array.

Alternatively, a direct connection from each pToF pixel to the TDC provided outside of the pToF array may be used instead.FIG. 2is a diagram illustrating another structure of a pToF array according to the prior art. As illustrated inFIG. 2, PDs200form a central part of the pToF array. Each PD200has a direct routing path to connect to one TDC210located outside of the pToF array. In this way, a smaller gap area between neighbor pToF pixels and a large fill-factor may be achieved. However, the following issues still exist.

Firstly, there is no way to route the direct connection for each PD200to the TDC210provided outside of the pToF array, when the scale of the pToF array is large. In the example illustrated inFIG. 2, it is only a small pToF array of 4×4, but it already used two-side TDC floorplan, and in each side, all gap areas are occupied with routing lines.

Secondly, since the principle of one PD corresponding to one TDC still exists, the amount of TDCs is still large if the scale of the pToF array is large. As a result, the total power consumption is still as large as that of the pToF array with the TDCs provided inside of the pToF pixel100illustrated inFIG. 1.

Thirdly, a large count of TDCs also means a large area, which leads to a larger chip cost.

At the same time, a high speed clock signal distribution over a large area still remains an issue, with introducing a significant amount of measurement errors.

FIG. 3is a diagram illustrating another structure of a pToF array according to the prior art. In this structure, each TDC310or320is shared by one row of the pToF pixels300, or one column of the pToF pixels300, or both. In this way, the amount of the TDCs may be significantly reduced from a level of M*N to a level of M+N, where M and N represents a number of rows and a number of columns of the pToF array respectively. As a result, a relatively larger scale pToF array may be realized than the two prior arts discussed above. However, there are still some basic limitations.

Firstly, it can only detect a firing pulse of one row, or one column, or one pToF pixel300at a time, depending on an operation method for the pToF array with shared TDCs. When multiple pToF pixels300fire at the same or close enough time period, the shared TDCs310or320may only response to some firing pulses of the pToF pixels300and ignore others. In many cases, the ignored firing pulses are actually real important signals which need immediate attentions.

Secondly, a large circuit loading and a parasitic RC component on the column or row line strongly limit a response speed of the TDC. Particularly, when a large scale pToF array is implemented, each shared column/row lines may have hundreds or even thousands of pToF pixels connecting to it, which act as RC loadings on a fast pulse readout path. The pulses to be readout are significantly slowed down by these RC loadings and related parasitic RC components, and at the same time unwanted clock jitters, power noises and signal coupling noises are introduced.

As a brief conclusion, the above prior arts cannot implement a large scale pToF array with good performance.

FIG. 4is a diagram illustrating a structure of a pToF pixel array according to an embodiment of the present disclosure. As shown inFIG. 4, the pToF pixel array405includes a plurality of pToF pixels400distributed in an array, a control circuit410, and a conversion circuit420.

Each of the pToF pixels400includes a photo sensitive unit430configured to detect a return signal of a light pulse signal and a first conversion unit440provided inside of each of the pToF pixels and configured to convert a time signal corresponding to each of the pToF pixels to an analog signal. The photo sensitive unit430may be a photo sensitive device with its direct supporting bias circuit, marked as PD unit430inFIG. 4. The first conversion unit440may be a time-to-analog conversion circuit, marked as TAC unit440inFIG. 4. The conversion circuit420may be an analog-to-digital conversion circuit, marked as ADC unit420inFIG. 4.

The control circuit is provided outside of the pToF pixels, connected to each of the pToF pixels, and configured to control an operation mode of each of the pToF pixels. The conversion circuit is provided outside of the pToF pixels, connected to each of the pToF pixels, and configured to calculate a time-of-flight corresponding to each of the pToF pixels according to the analog signal corresponding to each of the pToF pixels. The time-of-flight is a time from sending out the light pulse signal to receiving the return signal of the light pulse signal by each of the pToF pixels.

In some embodiments, the pToF pixel array405may include one conversion circuit420connected to all pToF pixels400. In other embodiments, the pToF pixel array405may include a plurality of conversion circuits420, each of which is connected to one column/row of the pToF pixels400, or to several columns/rows of the pToF pixels400.FIG. 4shows an example that each of the conversion circuits420is connected to one column of the pToF pixels400.

In the embodiment, a time-to-digital conversion to calculate a time-of-flight is not fully completed in a pToF pixel, or outside of a pToF pixel. Instead, the time-to-digital conversion is split into two parts, including a time-to-analog conversion in a pToF pixel, and an analog-to-digital conversion outside the pToF pixel.

In the pToF pixel array according to the embodiment, there is no need to distribute a high speed clock signal for each pToF pixel or provide a parasitic RC component, so that a smaller gap area between the neighbor pToF pixels and a higher fill-factor may be obtained. Without the high speed clock signal or the parasitic RC component, the first conversion unit (TAC unit)440in the pToF pixel may be realized with a much smaller layout area, which is beneficial to get a smaller gap area between the neighbor pToF pixels and is good for LiDAR applications.

Furthermore, the total layout area and power consumption of the pToF pixel array may be reduced. With no need of the distribution of the high speed clock signal and the RC components, the first conversion unit440in the pToF pixel may be much more power efficient than the TDC in the pToF pixel. Additionally, the conversion circuit (ADC unit)420may be shared by one column or one row of the pToF pixels400, thus the amount of the conversion circuits may be acceptable in similar designs widely used in the traditional photography CIS (CMOS Image Sensor) industry, particularly in the mobile phone camera industry. As a result, the total layout area and the power consumption is significantly reduced compared with most other structures trying to implement the large scale pToF pixel array.

Moreover, the pToF pixel array405according to the embodiment of the present disclosure is mostly suitable for scalable integration. With no need of distributing the high speed clock signal for each pToF pixel, it is possible to implement a large scale pToF pixel array with a mega-pixel level as demanded by the applications.

The structure of the pToF pixel array according to the embodiment of the present disclosure introduces more flexibility in an operation mode. The first conversion unit440in the pToF pixel400may also function as a temporary storage node, which adds capability of decoupling the photon capture timing and the readout timing. The structure of the pToF pixel array may be compatible with a global shutter mode, a line scan mode, as well as a pixel scan mode, which will be described in more detail below.

FIG. 5is a circuit diagram of a photo sensitive unit according to an embodiment of the present disclosure. As shown inFIG. 5, the photo sensitive unit430may include a photodiode700, an adjustable quenching resistor710, an enable switch720, and a comparator730.

In the embodiment, one end of the photodiode700is connected to a first power supply ‘PIX_VDD’, and the other end of the photodiode700is connected to the adjustable quenching resistor710via the enable switch720and to a first input end (an analog input end) of the comparator730. A control end of the enable switch720is connected to the control circuit410. A second input end (another analog input end) of the comparator730is connected to a reference voltage ‘vref’, a third input end (an enable input end) of the comparator730is connected to the control circuit410, and an output end of the comparator730is connected to the first conversion unit440. The reference voltage ‘vref’ may be functioned as a threshold voltage. The third input end is configured to control the comparator730to be functional or to stay in an idle state.

The first power supply ‘PIX_VDD’ may be a high voltage and the photodiode700may be reversed biased by the high voltage. A connection point of the photodiode, the first input end of the comparator and the enable switch is referred to as a first node ‘SN’ (sense node). The first node is a P type node of the photodiode700.

The photodiode may be any one of a simple P-I-N photodiode, an Avalanche Photodiode (APD), a Silicon Photomultiplier (SiPM), a Single Photon Avalanche Photodiode (SPAP), or any possible photodiode which can absorb incident photons and convert the incident photons into electrons.

In some embodiments, when the enable switch720is enabled, a group of photons are detected by the photodiode700within a short period of time, and electrons are generated by the photodiode700, resulting in current passing through the photodiode700and increase of the adjustable quenching resistor710. Accordingly, the voltage at the first node ‘SN’ will rise rapidly. When the voltage at the first node ‘SN’ is higher than the reference voltage ‘vref’, the comparator730will output a “high” for an output signal ‘L_pulse’ to trigger the first conversion unit440, which will be described below. After the voltage at the first node ‘SN’ rises to a certain amplitude, quenching will happen and the voltage at the first node ‘SN’ starts to drop gradually until the next time to fire another pulse.

FIG. 6is a circuit diagram of a first conversion unit according to an embodiment of the present disclosure. As shown inFIG. 6, the first conversion unit440may include a logic circuit540, a sample switch530, a capacitor500, a first MOS510, a second MOS520, a first buffer550, a selective switch560, and an output bitline570.

In the embodiment, a first input end of the logic circuit540is connected to the control circuit410, a second input end of the logic circuit540is connected to the output end of the comparator730, and an output end of the logic circuit540is connected to a control end of the sample switch530. A first end of the sample switch530is introduced to a first time signal ‘v_time’, and a second end of the sample switch530is grounded via the capacitor500. A first end of the first MOS510is connected to the control circuit410, a second end of the first MOS510is grounded via the capacitor500, and a third end of the first MOS510is connected to an input end of the first buffer550. A first end of the second MOS520is connected to the control circuit410, a second end of the second MOS520is connected a second power supply ‘vdd’, and a third end of the second MOS520is connected to the input end of the first buffer550. A first end of the selective switch560is connected to an output end of the first buffer550, a second end of the selective switch560is connected to the output bitline570, and a control end of the selective switch560is connected to the control circuit410. The output bitline570is connected to the conversion circuit420.

In some embodiments, the logic circuit540may be implemented as a simple DFF (D-Flip-Flop) circuit. The first input end of the logic circuit540may receive a reset signal ‘rst 1’, and the second input end of the logic circuit540may receive a trigger signal ‘L_pulse’ received from the comparator730. The output end of the logic circuit540may be a node NQ for controlling the on/off states of the sample switch530.

A connection point of the sample switch530, the capacitor500and the first MOS510is referred to as a second node ‘SD’ (storage node). A connection point of the first MOS510, the second MOS520and the first buffer550is referred to as a third node ‘FD’ (floating node). The capacitor500is a key component to store a captured time-to analog voltage onto the second node ‘SD’.

The first MOS510connects the second node ‘SD’ to the third node ‘FD’ and reads out the third node ‘FD’. Thus, the first MOS510may function as a transfer MOS. The second MOS520connects the third node ‘FD’ to the second power supply ‘vdd’. Thus, the second MOS520may function as a reset MOS. The third node ‘FD’ is connected to the first buffer550for readout. The first buffer550may be an unity gain buffer. The components of the first MOS510, the second MOS520, the first buffer550, the selective switch560and the output bitline570actually form a CIS (CMOS Image Sensor) pixel structure.

FIG. 7is a diagram illustrating an example of a first time signal according to an embodiment of the present disclosure. The first time signal ‘v_time’ is a voltage waveform representation of the time. In some embodiments, the first time signal ‘v_time’ may be implemented as shown inFIG. 7. As shown inFIG. 7, the first time signal ‘v_time’ may be a voltage waveform with repeated voltage ramps rising from a first time point ‘T_start’, increasing linearly by a certain slope, and resetting back to its origin at a second time point ‘T_end’. The voltage ramp may be repeated many times as required by the operation of the pToF pixel array.

In some embodiments, in an operation period, firstly, the first input end of the logic circuit540receives a reset signal ‘rst 1’ to reset the state of the sample switch530to on, thus the voltage at the second node ‘SD’ tracks the voltage of the first time signal ‘v_time’. At a certain time point when the photodiode700of the photo sensitive unit430detects enough photons and thereby the comparator730outputs a spike voltage wave as signal ‘L_pulse’, the logic circuit540then changes the state of the sample switch530to off, so as to hold a time-related voltage on the second node ‘SD’ until it is read out by following circuits.

The above description describes the embodiments of the pToF pixel. The pToF pixel may be integrated to a pToF pixel array for better functionality. The control circuit410and the conversion circuit420are used in the pToF pixel array as illustrated inFIG. 4.

FIG. 8is a diagram illustrating a structure of a control circuit according to an embodiment of the present disclosure. The control circuit800may include a plurality of control units. In some embodiments, each of the control units is configured to be connected to a row of the pToF pixels. InFIG. 8, the control unit804illustrates an enlarged structure of one of the control units.

The control unit804may include: an address decoder808configured to receive a pixel address; an latch810configured to receive mode information about an operation mode of the pToF pixels400; a first control logic unit820configured to control the photo sensitive unit430of the pToF pixel400corresponding to the pixel address, according to the pixel address and the operation mode; and a second control logic unit830configured to control the first conversion unit440of the pToF pixel400corresponding to the pixel address, according to the pixel address and the operation mode.

In the embodiment, an input end of the latch810is connected to the address decoder808, and an output end of the latch810is connected the first control logic unit820and the second control logic unit830respectively. Output ends of the first control logic unit820are connected to the control end of the enable switch720and the third input end of the comparator730in the photo sensitive unit430respectively. Output ends of the second control logic unit830are connected to the first input end of the logic circuit540, the first end of the first MOS510, the first end of the second MOS520and the control end of the selective switch560respectively.

The pixel address may be a row address or an address of one or more pToF pixels in code. Accordingly, the control circuit may scan the pToF pixels line-by-line, one-by-one or globally. When the address decoder808receives a row address as an input signal, the control unit804enables to select or not select a certain row of pToF pixels. When selected, the latch810is enabled and mode information may be received and stored into the latch810. The mode information may be a code having multi-bits, which represents different functional mode of the pToF pixel.

The output of the latch810controls the first control logic unit820and the second control logic unit830to drive the photo sensitive unit430and the first conversion unit440.

The first control logic unit820is a PD control logic unit. The first control logic unit820may output a control signal ‘enable_PD’ to the enable switch720and output a control signal ‘enable_CMP’ to the third input end of the comparator730in the photo sensitive unit430.

The second control logic unit830is a readout control logic unit. The second control logic unit830may output the control signal ‘rst1’ to the first input end of the logic circuit540, output a control signal ‘rst2’ to the first end of the second MOS520, output a control signal ‘TX’ to the first end of the first MOS510, and output a control signal ‘select’ to the control end of the selective switch560.

When all control signal lines in one row are shared lines and connects to all pToF pixels in this row, the RC loading is relatively large. Thus, the control unit804may further include a plurality of second buffers840connected to the output ends of the first control logic unit820and the second control logic unit830, so as to enhance the driving ability of the first control logic unit820and the second control logic unit830. It is noted that, in some embodiments, the structure of each control unit is identical but with different connections of the pixel address.

In some embodiments, each of the control units804is configured to receive the pixel address and the mode information; and when the mode information indicates a first mode, to control the operation mode of the pToF pixel400corresponding to the pixel address to the first mode by the first control logic unit820and the second control logic unit830, and to trigger the sending out of the light pulse signal simultaneously.

When the pToF pixel400operates in the first mode, the pToF pixel400is configured to control the sample switch530to be turned on; to obtain a first voltage signal corresponding to the first time signal at the second node; when the photodiode receives the return signal of the light pulse signal in a preset time period, and a voltage of the photodiode700at the first node is higher than the reference voltage of the comparator730, to control the sample switch530to be turned off by the logic circuit540; and to maintain the first voltage signal at the second node.

Specifically, for example, by setting the pixel address and the mode information at the same time, when the mode information received by the latch810indicates the first mode, an external illumination module may be triggered to send out a laser or LED pulse signal, and the pToF pixel400corresponding to the pixel address is simultaneously enabled into the first mode, which is referred to as a ‘capture mode’.

In the first mode, the first control logic unit820outputs the control signals ‘enable_PD’ and ‘enable_CMP’ to enable the photodiode700and the comparator730. Additionally, there may be a short delay between the control signal ‘enable_PD’ and control signal ‘enable_CMP’ to allow smooth circuit response.

In the first mode, the first input end of the logic circuit540is reset by the control signal ‘rst1’, thus the state of the sample switch530is reset to on, and the voltage at the second node ‘SD’ tracks the voltage of the first time signal ‘v_time’. Therefore, the first voltage signal corresponding to the first time signal at the second node ‘SD’ is obtained. The photo sensitive unit430and the first conversion unit440are prepared. Then the pToF pixel400is waiting until the return signal of the light pulse signal being detected.

When the return signal is detected in a preset time period by the photodiode700and the voltage at the first node ‘SN’ is higher than the reference voltage ‘vref’, the comparator730generates a spike ‘L_pulse’. The ‘L_pulse’ triggers the logic circuit540to change the state of the sample switch530to off, so as to hold a first voltage signal corresponding to the first time signal at the second node ‘SD’. There should be a limiting timer to limit the maximum waiting time, i.e., the preset time period, which also defines the maximum distance that the pToF pixel array can measure.

In some embodiments, each of the control units is configured to control the operation mode of the pToF pixel400corresponding to the pixel address to a second mode by the second control logic unit830, after the photo sensitive unit430of the pToF pixel400receives the return signal of the light pulse signal in the preset time period, and the voltage of the photodiode700at the first node is higher than the reference voltage of the comparator730.

When the pToF pixel400operates in the second mode, the pToF pixel400is configured to control the selective switch560and the second MOS520to be turned on; to obtain a second voltage signal at the third node ‘FD’, and to transmit the second voltage signal to the conversion circuit420corresponding to the pToF pixel400; to control the first MOS to be turned on; and to obtain a third voltage signal at the third node and to transmit the third voltage signal to the conversion circuit420corresponding to the pToF pixel400.

Specifically, for example, after the state of the sample switch530is changed to off, the pToF pixel corresponding to the pixel address is control to the second mode. Additionally, it also may be done by input related pixel address and mode information to the control unit804. In the second mode, firstly, the selective switch560is enabled by the control signal ‘select’ received from the second control logic unit830, and the second buffer is connected to the outline570via the selective switch560. Then, the second MOS520is controlled to be turned on by the control signal ‘rst2’ to reset the third node ‘FD’. After that, the second voltage signal at the third node ‘FD’ is obtained and transmitted to the conversion circuit420corresponding to the pToF pixel400through the output bitline570. The second voltage signal may be expressed as data1=reset FD voltage. Then the first MOS510is controlled to be turned on by the control signal ‘TX’ to transfer the charges at the second node ‘SD’ to the third node ‘FD’. After the transfer, the third voltage signal at the third node ‘FD’ is obtained and transmitted to the conversion circuit420corresponding to the pToF pixel400through the output bitline570. The third voltage signal may be expressed as data2=FD voltage.

In some embodiments, the control signals ‘rst1’, ‘rst2’ and ‘TX’ may be pulse signals.

In some embodiments, the conversion circuit420is configured to calculate the time-of-flight corresponding to the pToF pixel400according to the received second voltage signal and the third voltage signal.

Specifically, for example, a CDS (Correlated Double Sampling) operation may be done to get the result as data (time-of-flight)=data2−data1.

The process to obtain the time-of-flight may be repeated line-by-line, one-by-one or globally to obtain the time-of-flight corresponding to each of the pToF pixels in the pToF pixel array.

In some embodiments, the control circuit800is configured to receive a pixel address and mode information; and when the mode information indicates a first mode, to control the operation mode of the pToF pixel400corresponding to the pixel address to a first mode, and to trigger the sending out of the light pulse signal simultaneously.

When the pToF pixel400operates in the first mode, the pToF pixel400is configured to obtain a first voltage signal when the light pulse signal is sent out; and when receiving the return signal of the light pulse signal in a preset time period and a signal value of the return signal is higher than a preset threshold value, to store the first voltage signal.

In some embodiments, the control circuit is configured to control the operation mode of the pToF pixel corresponding to the pixel address to a second mode, after the pToF pixel receives the return signal of the light pulse signal in the preset time period and the signal value of the return signal is higher than the preset threshold value.

When the pToF pixel operates in the second mode, the pToF pixel is configured to obtain a second voltage signal and a third voltage signal related to the first voltage signal respectively; and to transmit the second voltage signal and the third voltage signal to the conversion circuit corresponding to the pToF pixel.

Furthermore, the conversion circuit420is configured to calculate the time-of-flight corresponding to the pToF pixel400according to the received second voltage signal and the third voltage signal.

A pToF sensor is provided according to an embodiment of the present disclosure. The pToF sensor may include the pToF pixel array according to any embodiments described above, and details are not described herein again.

An operation method for a pToF pixel array is further provided according to an embodiment of the present disclosure.FIG. 9is a flow chart illustrating an operation method for a pToF pixel array according to an embodiment of the present disclosure.

An operation method for a pToF pixel array is suitable for the pToF pixel array according to any embodiments described above. The operation method includes the following steps.

Step901, receiving a pixel address and mode information.

For example, referring toFIG. 10, the address decoder808receives the pixel address indicating the first row and the latch810receives the mode information indicating a first mode, thus the operation method starts from the first row which is referred as to a current row (S1001).

Step902, when the mode information indicates a first mode, triggering sending out of a light pulse signal, and obtaining a first voltage signal when sending out the light pulse signal simultaneously.

For example, referring toFIG. 10, when the latch810receives the mode information indicating the first mode, the first control logic unit820and the second control logic unit830output control signals to drive the photo sensitive unit430and the first conversion unit440in the first row (the current row) of the pToF pixels, so as to enable the first row (the current row) of the pToF pixels into the first mode (capture mode) (S1002).

Specifically, the first control logic unit820may output a control signal ‘enable_PD’ to the enable switch720, and output a control signal ‘enable_CMP’ to the third input end of the comparator730, so that the enable switch720is turned on and the comparator730is functioned (S1003). Additionally, there may be a short delay between the control signal ‘enable_PD’ and control signal ‘enable_CMP’ to allow smooth circuit response.

At the same time, the first conversion unit440is reset (S1004) and the external light pulse signal is triggered to be sent out (S1005). Specifically, the logic circuit540receives the control signal ‘rst1’ from the second control logic unit830, and thus the state of the sample switch530is reset to on. Then the sample switch530introduces the first time signal ‘v_time’ and the voltage the second node ‘SD’ tracks the voltage of the first time signal ‘v_time’ (S1006).

Step903, storing the first voltage signal when the pToF pixel corresponding to the pixel address receives a return signal of the light pulse signal in a preset time period and a signal value of the return signal is higher than a preset threshold value.

For example, referring toFIG. 10, the photodiodes700in the first row of the pToF pixels400are waiting until the return signal of the light pulse signal being detected in a preset time period (S1007). When the voltage at the first node ‘SN’ is higher than the reference voltage ‘vref’ of the comparator730, the comparator730outputs the signal ‘L_pulse’. The signal ‘L_pulse’ triggers the logic circuit540to change the state of the sample switch530to off, so as to hold a first voltage signal corresponding to the first time signal at the second node ‘SD’.

Step904, obtaining a second voltage signal and a third voltage signal related to the first voltage signal after the pToF pixel corresponding to the pixel address receives the return signal of the light pulse signal in the preset time period and the signal value of the return signal is higher than the preset threshold value.

For example, referring toFIG. 10, the second control logic unit830outputs control signals to drive the first conversion unit440in the first row of the pToF pixels, so as to enable the first row of the pToF pixels into the second mode (readout mode) (S1008).

Specifically, the selective switch560is turned on by the received control signals ‘select’ form the second control logic unit830, thus the output end of the second buffer550is connected to the output bitline570(S1009). The second MOS520is turned on by the received control signal ‘rst2’ form the second control logic unit830, thus the third node ‘FD’ is reset (S1010). The second voltage signal at the third node ‘FD’ is read out as data1=reset FD voltage (S1011) and transmitted to the conversion circuit corresponding to the first row of the pToF pixels400. Then the first MOS510is turned on by the received control signal ‘TX’ from the second control logic unit830, and the charges at the second node ‘SD’ is transferred to the third node ‘FD’ (S1012). After the transfer, the third voltage signal at the third node ‘FD’ is read out as data2=FD voltage (S1013) and transmitted to the conversion circuit corresponding to the first row of the pToF pixels400.

Step905, calculating a time-of-flight corresponding to the pToF pixel corresponding to the pixel address. The time-of-flight is a time from sending out the light pulse signal to receiving the return signal of the light pulse signal by the pToF pixel.

For example, referring toFIG. 10, the conversion circuit420corresponding to the first row of the pToF pixels400calculates the time-of-flight corresponding to the first row of the pToF pixels400according to the first voltage signal ‘data1’ and the second voltage signal ‘data2’. Specifically, the conversion circuit420gets the result as data (time-of-flight)=data2−data1 by a CDS operation (S1014).

After that, the control circuit may determine whether the row of the pToF pixels400is the low of the pToF pixel array (S1015), if yes, the operation returns to the step S1001, and if no, the operation proceeds to the next row of the pToF pixels and repeats the steps S1002to S1015.

In some embodiments, the pToF pixels distributed in the array may be scanned line-by-line, one-by-one or globally, to calculate the time-of-flight corresponding to each of the pToF pixels. For example, the pixel address may be a row address, that is, a row of pixels are selected and the time-of-flights corresponding to the row of pixels are calculated. In particular, the operation method may start from the first row of the pToF pixel array, and perform the calculation line-by-line.

The above description in detail focuses on the embodiments of the present disclosure. Several obvious variations may be applied for performance improvement or to make it adapt to different application demands. For example,FIG. 4illustrates that a conversion circuit420in column level is used using column ADC to do the last stage of the analog-to-digital conversion. Alternatively, it is also possible to just use a sample and hold circuit in column level, and transfer the sampled voltages to one or several conversion circuit in global level to do the analog-to-digital conversion. Furthermore, even the conversion circuit in column level is used, it can be one conversion circuit per column, as illustrated inFIG. 4, and it can also be one conversion circuit shared by several columns to get better cost effective layout area.

For another example,FIG. 6illustrates a simple example of the first time signal v_time. Alternatively, it can be more complex. For example, it can be a non-linear mapping curve instead of a linear curve. It may also be a signal array instead of one signal, i.e., V_time[0] and V_time[1]. A combination of two or more v_time signal in which one has a fast slope and the other has a slow slop may help cover more dynamic range of the time, thereby helping to measure both the long and short distances at the same time.

A further example is about the comparator730used in the photo sensitive unit430. In the description above, a simple comparator is used without any additional limitations. Alternatively, one can add necessary auto-zero circuit, hysteresis circuit, etc., to improve its performance as well as its robusticity. Additionally, the above described operation method illustrates a typical way to run the embodiment in rolling-shutter, line-scan mode, it is not hard to make some small changes, so that it can also run in frame global shutter mode, or one-by-one pixel scan mode. Finally, single light pulse operation is described as an embodiment of the pToF method, it is also possible to do multi-pulses for better performance and advanced functions.

The present disclosure has been described in terms of particular embodiments and applications, in both summarized and detailed forms, it is not intended that these descriptions in any way limit the scope of the present disclosure to any such embodiments and applications. It will be understood that many substitutions, changes and variations in the described embodiments, applications and details of the present disclosure illustrated herein can be made by those skilled in the art without departing from the spirit of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the appended claims.