Hue and saturation control circuitry requiring single coupling capacitor

A signal-processing circuit comprises a first gate circuit, a chrominance signal amplifier, a hue control circuit, means for reproducing a composite color signal, an AC coupling capacitor, and a second gate circuit. The first gate circuit receives a composite color signal consisting of chrominance signals and burst signals which are arranged alternately and then extracts the chrominance signals and burst signals from the composite color signal. The extracted chrominance signal is amplified by the chrominance signal amplifier, while the phase of the extracted burst signal is controlled by the hue control circuit. The outputs of the chrominance signal amplifier and the hue control circuit are added by said reproducing means, thereby reproducing a composite color signal. The AC coupling capacitor is coupled to the output of said means. The second gate circuit extracts from the output of the AC coupling capacitor chrominance signals and burst signals.

This invention relates to an analog signal-processing integrated circuit 
which comprises various circuits formed on one chip and wherein the number 
of necessary terminal pins is reduced. 
Generally, the more circuits are used to constitute an analog IC, the more 
transistors should be connected in cascade. The more transistors are 
connected in cascade, the more is varied the DC component of an analog 
signal. Thus, it is necessary to cut the DC transmission path at a point 
and to apply only the AC component of the analog signal to the succeeding 
stages. To apply the AC component of the analog signal alone, a capacitor 
of a large capacity should be used. But it is difficult to incorporate 
such a capacitor into an integrated circuit. Thus a capacitor of a large 
capacity should be connected to the external terminal pins of the analog 
IC. In consequence, the number of necessary terminal pins of the analog IC 
increased inevitably. 
With reference to FIGS. 1 and 2 a conventional chrominance 
signal-processing circuit, an example of an analog IC used in TV sets, 
will be described. As shown in FIG. 1, the conventional chrominance 
signal-processing circuit comprises a composite color signal amplifier 1, 
a gate circuit 2, a hue control circuit 3, a chrominance signal amplifier 
4, a demodulator 5 and a phase detector 6. The gate circuit 2 extracts a 
burst signal e.sub.b and a chrominance signal e.sub.c from an amplified 
chrominance signal (e.sub.b +e.sub.c) from the amplifier 1 in response to 
a gate pulse generated in synchronism with the burst signal. The burst 
signal e.sub.b is supplied to the hue control circuit 3, while the 
chrominance signal e.sub.c is supplied to the chrominance signal amplifier 
4, which controls the gain of the chrominance signal e.sub.c. The phase 
detector 6 is to control a subcarrier wave oscillator (not shown) or to 
generate a control signal for automatic color control or color killer 
control. 
The chrominance signal amplifier 4 and the hue control circuit 3 have 
output terminals P.sub.1 and P.sub.3, respectively. Similarly, the 
demodulator 5 and the phase detector 6 have input terminals P.sub.2 and 
P.sub.4, respectively. A capacitor C.sub.1 is connected between the 
terminals P.sub.1 and P.sub.2, and another capacitor C.sub.2 between the 
terminals P.sub.3 and P.sub.4. Both capacitors act as AC coupling 
elements. 
Each of demodulator 5 and phase detector 6 usually includes such 
differential amplifiers of double balanced type as illustrated in FIG. 2. 
More specifically, transistors Q.sub.1 and Q.sub.2 constitute a 
differential amplifier, transistors Q.sub.3 and Q.sub.4 another 
differential amplifier, and transistors Q.sub.5 and Q.sub.6 still another 
differential amplifier. The emitters of the transistors Q.sub.3 and 
Q.sub.4 are connected to the collector of the transistor Q.sub.1, the 
emitters of the transistors Q.sub.5 and Q.sub.6 to the collector of the 
transistor Q.sub.2, and the emitters of the transistors Q.sub.1 and 
Q.sub.2 to a current source I.sub.o. The collectors of the transistors 
Q.sub.3 and Q.sub.5 are connected to a power source V.sub.cc through a 
load resistor R.sub.1. The collectors of the transistors Q.sub.4 and 
Q.sub.6 are connected also to the power source V.sub.cc. To one end of the 
resistor R.sub.1 there is connected an output terminal P.sub.11. 
A burst signal e.sub.b or a chrominance signal e.sub.c is supplied to the 
base terminal P.sub.7 of the transistor Q.sub.1 and/or the base terminal 
P.sub.8 of the transistor Q.sub.2. Subcarrier waves are supplied to the 
common base terminal P.sub.9 of the transistors Q.sub.3 and Q.sub.6 and/or 
the common base terminal P.sub.10 of the transistors Q.sub.4 and Q.sub.5. 
If a circuit in the preceding stage is connected to the base terminals 
P.sub.7 and P.sub.8, the voltage across the terminals P.sub.7 and P.sub.8, 
i.e. DC bias on the differential amplifier constituted by the transistors 
Q.sub.1 and Q.sub.2, will be lowered. As a result, the maximum amplitude 
of an input signal will be limited, or the voltage at the output terminal 
P.sub.11 will vary. Consequently, the demodulator 5 may change the color 
of the background on the TV screen, and the phase detector 6 may 
eventually vary the frequency of the subcarrier waves from the subcarrier 
wave oscillator (not shown). 
To avoid the variation of the voltage across the terminals P.sub.7 and 
P.sub.8, an AC coupling capacitor is connected to the terminal P.sub.7 or 
P.sub.8. The conventional chrominance signal-processing circuit shown in 
FIG. 1, which controls chrominance signals (first signals) and burst 
signals (second signals) alternately transmitted in time-share fashion, 
requires two AC coupling capacitors, i.e. capacitors C.sub.1 and C.sub.2. 
In case the signal-processing circuit is used in a TV set, the capacitors 
C.sub.1 and C.sub.2 should have such a large capacity as would provide a 
sufficiently small impedance to the TV signal frequency, e.g. 3.58 MHz. 
With such a large capacity, the capacitors C.sub.1 and C.sub.2 can hardly 
be made into an integrated circuit. For this reason they should be 
arranged outside the signal-processing circuit which is an IC. In 
conventional circuit the signal-processing circuit should therefore be 
provided with four external terminal pins P.sub.1 to P.sub.4. A large 
number of pins is one of the factors which make it difficult to 
incorporate various circuits into an integrated circuit. If four terminal 
pins P.sub.1 to P.sub.4 are used merely to allow the use of two AC 
coupling capacitors, it means that the pins P.sub.1 to P.sub.4 are not 
used effectively. 
The object of this invention is to provide a signal-processing circuit 
which comprises various circuits performing different functions and 
wherein the number of necessary terminal pins is reduced thereby to make 
it easier to incorporate the various circuits into an integrated circuit. 
According to one aspect of this invention there is provided a 
signal-processing circuit comprising signal-separating means for 
separating and extracting a first signal and a second signal from a 
multiplex signal; a gain control circuit for controlling the gain of the 
first signal from said signal-separating means; a phase control circuit 
for controlling the phase of the second signal from said signal-separating 
means; means for synthesizing the outputs of said gain control circuit and 
said phase control circuit to form a time-shared type signal; and an AC 
coupling capacitor for supplying the time-shared type signal from said 
signal-synthesizing means to a circuit in the next stage.

As shown in FIG. 3, an embodiment of the signal-processing circuit 
according to this invention comprises a composite color signal amplifier 
1, a first gate circuit 2, a hue control circuit 3, a second chrominance 
signal amplifier 4, a demodulator 5, a phase detector 6 and a second gate 
circuit 7. The first gate circuit 2 separates a chrominance signal e.sub.c 
and a burst signal e.sub.b when a gate pulse is applied to the first gate 
circuit 2. The hue control circuit 3 and the chrominance signal amplifier 
4 have a common output terminal P.sub.5, and the second gate circuit 7 has 
an input terminal P.sub.6. Between the terminals P.sub.5 and P.sub.6 there 
is connected an AC coupling capacitor C.sub.3. 
Unlike in the conventional signal-processing circuit of FIG. 1, the outputs 
of the hue control circuit 3 and second chrominance circuit 4 are 
synthesized at the output terminal P.sub.5 to form a sum signal (e.sub.c 
+e.sub.b), which is supplied to the second gate circuit 7 through the 
capacitor C.sub.3. That is, the sum signal consisting of a chrominance 
signal e.sub.c and a burst signal e.sub.b passes through the capacitor 
C.sub.3, and the chrominance signal e.sub.c separated again from the burst 
signal e.sub.b by the second gate circuit 7. The chrominance signal 
e.sub.c is then supplied to the demodulator 5, and the burst signal 
e.sub.b to the phase detector 6. Instead, to the capacitor C.sub.3 there 
may be connected two gate circuits, one for extracting the chrominance 
signal from the sum signal and the other for extracting the burst signal 
from the sum signal. 
As shown in FIG. 3, the signal-processing circuit requires but a single AC 
coupling capacitor in order to supply a chrominance signal e.sub.c and a 
burst signal e.sub.b, which have undergone a specific control, to the 
demodulator 5 and the phase detector 6, respectively. Provided with only 
one AC coupling capacitor, the signal-processing circuit requires only two 
terminal pins. Indeed the second gate circuit 7 is an additional element, 
and it changes little the DC component of the sum signal. Thus the 
operation of the demodulator 5 or the phase detector 6 is hardly affected 
by the variation of the DC component. Further, the hue control may be 
effected by subcarrier wave signals instead of burst signals e.sub.b from 
the first gate circuit 2. The hue control can be carried out even if the 
second chrominance signal amplifier 4 is not provided. 
A concrete circuit diagram of one embodiment of this invention is shown in 
FIG. 4, which is not provided with a hue control circuit corresponding to 
the hue control circuit amplifier 3 of the circuit shown in FIG. 3. This 
embodiment comprises a composite color signal amplifier 1, a first gate 
circuit 2, a chrominance signal amplifier 4, an AC coupling capacitor 
C.sub.3, a demodulator 5 and a phase detector 6. The demodulator 5 denotes 
only one demodulated axis, and the phase detector 6 actuates a 
voltage-controlled oscillator VCO. 
In the signal-processing circuit of FIG. 4, the gate circuit 2 is 
constituted by a by-pass capacitor C.sub.B, transistors Q.sub.7 and 
Q.sub.8, resistors R.sub.2 to R.sub.4, a differential amplifier of double 
balanced type comprised of transistors Q.sub.9 to Q.sub.12, and a base 
terminal P.sub.12 connected to the bases of the transistors Q.sub.9 and 
Q.sub.12. The gate circuit 2 separates a burst signal e.sub.b from a 
composite color signal (e.sub.b +e.sub.c) when a gate pulse is applied to 
the terminal P.sub.12. The phase detector 6 is constituted by transistors 
Q.sub.16 to Q.sub.20 and Q.sub.22 to Q.sub.25, resistors R.sub.10 to 
R.sub.12 and capacitors C.sub.5 and C.sub.6. The chrominance signal 
amplifier 4 is constituted by transistors Q.sub.13 to Q.sub.15, resistors 
R.sub.5 to R.sub.8 and a variable resistor RV.sub.1. The demodulator 5 is 
constituted by transistors Q.sub.26 to Q.sub.35 and resistors R.sub.13 to 
R.sub.17. The gate circuit 2, chrominance signal amplifier circuit 4, 
demodulator 5 and phase detector 6 are of well-known type, and their 
constructions are not described here in detail. 
A processed composite signal (e.sub.b +e.sub.c) from the chrominance signal 
amplifier 1 is applied to the base of the transistor Q.sub.7 of the gate 
circuit 2. But the base of the transistor Q.sub.8 is DC-biased by the 
by-pass capacitor C.sub.B. The collectors of the transistors Q.sub.10 and 
Q.sub.12 are connected to the junction between the emitters of the 
transistors Q.sub.13 and Q.sub.14 of the chrominance signal amplifier, and 
the collectors of the transistors Q.sub.9 and Q.sub.11 to the base of 
transistor Q.sub.15 of the chrominance signal amplifier 4. 
When a gate pulse is applied to the terminal P.sub.12, the transistors 
Q.sub.9 and Q.sub.12 of the gate circuit 2 are rendered conductive. The 
transistors Q.sub.9 and Q.sub.12 remain conductive for a burst period, 
during which time a burst signal e.sub.b is extracted from the composite 
color signal (e.sub.b +e.sub.c) and supplied to the base of the transistor 
Q.sub.15 through the transistor Q.sub.9. During a chrominance signal 
period the transistors Q.sub.10 and Q.sub.11 remain conductive and a 
chrominance signal e.sub.c is supplied to the emitters of the transistors 
Q.sub.13 and Q.sub.14 through the transistor Q.sub.10. The chrominance 
signal e.sub.c is supplied further to the base of the transistor Q.sub.15 
which is connected to the resistor R.sub.8. 
The ratio of the current flowing through the transistor Q.sub.14 and the 
current flowing through the transistor Q.sub.13 is controlled by the 
variable resistor VR.sub.1. The chrominance signal e.sub.c which has 
passed through the transistor Q.sub.14 is supplied to the transistor 
Q.sub.15. In this way the color gain of the chrominance signal e.sub.c is 
controlled. 
The transistor Q.sub.15 and the resistor R.sub.9 of the chrominance signal 
amplifier 4 form a emitter follower. The chrominance signal e.sub.c which 
has undergone amplitude control and the burst signal e.sub.b which has 
undergone no amplitude control appear alternately in time-share fashion at 
the output terminal P.sub.5 of the chrominance signal amplifier 4. These 
signal e.sub.c and e.sub.b are supplied through the AC coupling capacitor 
C.sub.3 to the phase detector 6 and the demodulator 5. The sum signal 
(e.sub.c +e.sub.b) is applied to the base of the transistor Q.sub.17 of 
the phase detector 6 and to the base of the transistor Q.sub.27 of the 
demodulator 5. 
In the phase detector 6, the transistors Q.sub.17 to Q.sub.20 constitute a 
differential amplifier. The transistors Q.sub.18 and Q.sub.19 have their 
bases connected mutually, their emitters connected to the emitter of the 
transistor Q.sub.17 and the emitter of the transistor Q.sub.20, 
respectively, and their collectors connected to the collector of the 
transistor Q.sub.17 and the collector of the transistor Q.sub.20, 
respectively. The bases of the transistors Q.sub.18 and Q.sub.19 are 
connected to a terminal P.sub.13. When a negative gate pulse is applied to 
the terminal P.sub.13, the transistors Q.sub.18 and Q.sub.19 become 
inconductive and the transistors Q.sub.17 and Q.sub.20 become conductive, 
whereby the phase detector 6 comes into operation. Namely, the phase 
detector 6 operates during the burst signal period and remains inoperative 
during the other period. 
In the demodulator 5, the transistors Q.sub.27 to Q.sub.30 constitute a 
differential amplifier. The transistors Q.sub.28 and Q.sub.29 have their 
bases connected mutually, their emitters connected to the emitter of the 
transistor Q.sub.27 and the emitter of the transistor Q.sub.30, 
respectively, and their collectors connected to the collector of the 
transistor Q.sub.27 and the collector of the transistor Q.sub.30, 
respectively. The bases of the transistors Q.sub.28 and Q.sub.29 are 
connected to a terminal P.sub.14. To the terminal P.sub.14 a positive gate 
pulse is applied. When a positive gate pulse synchronized with the 
negative gate pulse is applied to the terminal P.sub.14, the transistors 
Q.sub.28 and Q.sub.29 become conductive and the transistors Q.sub.27 and 
Q.sub.30 become nonconductive. As a result, a burst signal e.sub.b is shut 
off. While no burst signal e.sub.b is applied to the transistor Q.sub.27, 
the transistors Q.sub.27 and Q.sub.30 remains conductive. That is, during 
the chrominance signal period these transistors are conductive, thereby to 
demodulate the chrominance signal e.sub.c. Thus, the demodulator 5 
operates during the chrominance signal period, while the phase detector 6 
operates during the burst signal period. 
The gate pulse used in the conventional signal-processing circuit as shown 
in FIGS. 1 and 2 is a flyback pulse or a horizontal synchronizing signal. 
A horizontal synchronizing signal is preferred because it has a stable 
phase relationship with a burst signal e.sub.b. In a weak electric field, 
however, a horizontal synchronizing signal contains noise and in some 
cases it fails to perform a perfect gating operation. As a result, a 
chrominance signal e.sub.c may erroneously enter the hue control circuit 3 
during the chrominance signal period. If this happens, color killer 
control should be carried out in the demodulator 5 or the phase detector 
6. 
FIG. 5 shows another embodiment of this invention which differs from the 
signal-processing circuit of FIG. 4 only in that a color killer control 
circuit 8 is connected between demodulator 5 and a phase detector 6. The 
color killer control circuit 8 is constituted by transistors Q.sub.36 to 
Q.sub.38 and resistors R.sub.18 to R.sub.21. The output of the phase 
detector 6 is coupled to the base of the PNP transistor Q.sub.38, the 
emitter of which is connected to a power source V.sub.cc through the 
resistor R.sub.21. The collector of the transistor Q.sub.38 is grounded 
through the resistor R.sub.20 and connected to the base of the transistor 
Q.sub.37. The emitter of the transistor Q.sub.37 is grounded, and the 
collector thereof is connected to the emitter of the transistor Q.sub.36 
via the resistor R.sub.19. The collector of the transistor Q.sub.36 is 
connected to a voltage source V.sub.B7 through the resistor R.sub.18 and 
further to the terminal P.sub.14 of the demodulator 5. The base of the 
transistor Q.sub.36 is connected to a terminal P.sub.16, to which a 
negative gate pulse is applied. 
In a sufficient electric field, the transistor Q.sub.38 is conductive, and 
a current flows through the resistor R.sub.20. Thus the transistor 
Q.sub.37 is saturated, and the resistor R.sub.19 is equivalently grounded. 
As a result, the transistor Q.sub.36 comes into operation to supply a 
positive gate pulse to the terminal P.sub.14 of the demodulator 5. In a 
weak electric field, the transistor Q.sub.38 is nonconductive, and no 
current flows through the resistor R.sub.20. The transistor Q.sub.37 is 
therefore turned off, and then the transistor Q.sub.36 is turned off, too, 
whereby the positive gate pulse is not supplied to the terminal P.sub.14 
of the demodulator 5. Eventually the potential at the terminal P.sub.14 
reaches the value at the voltage source V.sub.B7, and the transistors 
Q.sub.28 and Q.sub.29 of the demodulator 5 remain conductive thereafter, 
whereby color killer operation is carried out. 
FIG. 6 shows a further embodiment of this invention, which differs from the 
signal-processing circuits shown in FIG. 4 in that it has further a hue 
control circuit. The circuit of FIG. 6 is divided into two parts by a 
dotted line. The right part is identical with the combination of the gate 
circuit 2 and the chrominance signal amplifier 4 of the signal-processing 
circuit shown in FIG. 4, except that the collectors of transistors Q.sub.9 
and Q.sub.11 are connected to a power source V.sub.cc. 
In the left part of the circuit of FIG. 6, the output of a composite color 
signal amplifier 1 which amplifies both a burst signal e.sub.b and a 
chrominance signal e.sub.c is coupled to the bases of transistors Q.sub.39 
and Q.sub.46 through a resistor R.sub.22. The base of the transistor 
Q.sub.39 is grounded through a capacitor C.sub.4. Thus, the resistor 
R.sub.22 and the capacitor C.sub.4 constitute a phase delay circuit. The 
output of the composite color signal amplifier 1 is supplied also to the 
base of a transistor Q.sub.42 and further to the base of a transistor 
Q.sub.7. The emitter of the transistor Q.sub.39 is connected to the 
emitter of a transistor Q.sub.40. The emitters of these transistors 
Q.sub.39 and Q.sub.40 are connected to a current source I.sub.o1 through 
a resistor R.sub.23. The other end of the current source I.sub.o1 is 
grounded. The emitters of a pair of transistors Q.sub.41 and Q.sub.42 are 
mutually connected and are connected to the current source I.sub.o1 
through a resistor R.sub.24. The emitters of another pair of transistors 
Q.sub.43 and Q.sub.44 are mutually connected and are coupled to a current 
source I.sub.o2 through a resistor R.sub.25. Similarly, the emitters of 
another pair of transistors Q.sub.45 and Q.sub.46 are mutually connected 
and are coupled to the current source I.sub.o2 through a resistor 
R.sub.26. 
The base of the transistor Q.sub.43 is connected to the base of a 
transistor Q.sub.8, while the bases of the transistors Q.sub.40, Q.sub.41, 
Q.sub.44 and Q.sub.45 are connected to a terminal P.sub.17, to which a 
gate pulse is applied. The collectors of the transistors Q.sub.39 and 
Q.sub.40 are mutually connected to the junction between the emitters of a 
pair of transistors Q.sub.47 and Q.sub.48. The collectors of the 
transistors Q.sub.41 and Q.sub.42 are mutually connected and are coupled 
to the power source V.sub.cc l through a resistor R.sub.30 and also to a 
terminal P.sub.18. The collectors of the transistors Q.sub.43 and Q.sub.44 
are mutually connected and are coupled to the junction between the 
emitters of a pair of transistors Q.sub.49 and Q.sub.50. The collectors of 
the transistors Q.sub.45 and Q.sub.46 are mutually connected and are 
coupled to the power source V.sub.cc. 
The bases of the transistors Q.sub.47 and Q.sub.50 are mutually connected 
and coupled to a voltage source V.sub.B2 through a resistor R.sub.29 and 
to a DC control variable resistor VR.sub.2 through a resistor R.sub.27. 
The bases of the transistors Q.sub.48 and Q.sub.49 are mutually connected 
and coupled to the voltage source V.sub.B2 through a resistor R.sub.28. 
The collectors of the transistors Q.sub.47 and Q.sub.49 are mutually 
connected and coupled to the power source V.sub.cc, while the collectors 
of the transistors Q.sub.48 and Q.sub.50 are mutually connected and 
coupled to the base of a transistor Q.sub.15. 
It will be described how hue control is carried out by the circuit of FIG. 
6, with reference to FIG. 7. 
Suppose the output signal of the composite color signal amplifier 1 is 
vector a as shown in FIG. 7 and applied to the bases of the transistors 
Q.sub.42 and Q.sub.7. If the phase of the output signal is delayed by, for 
example, 45.degree. by the phase delay circuit constituted by the resistor 
R.sub.22 and the capacitor C.sub.4, vector a will be converted into such 
vector b as illustrated in FIG. 7. 
When a gate pulse is applied to the terminal P.sub.17, the transistors 
Q.sub.40, Q.sub.41, Q.sub.44 and Q.sub.45 are rendered inconductive, while 
the transistors Q.sub.39 and Q.sub.42 start operating as a differential 
amplifier and the transistors Q.sub.43 and Q.sub.46 start operating as a 
differential amplifier. If a difference between vectors a and b (=a-b), as 
shown in FIG. 7, vector c appears at the collector of the transistor 
Q.sub.39, and vector b appears at the collector of the transistor 
Q.sub.43. Let vector a be the reference phase, here. Then, vector c is 
regarded as having a phase of +45.degree., and vector b as having a phase 
of -45.degree.. Thus, .vertline.b.vertline.=.vertline.c.vertline.. In the 
differential amplifier of double balanced type constituted by the 
transistors Q.sub.47 to Q.sub.50 the amplitude ratio between vectors b and 
c is controlled by the variable resistor VR.sub.2. Further, vectors b and 
c are synthesized into a signal, which is applied to the base of the 
transistor Q.sub.15. The phase of this signal may thus range from 
-45.degree. to +45.degree. with respect to vector a. A burst signal with a 
controlled phase and a chrominance signal having its amplitude controlled 
by transistor Q.sub.14 are synthesized at the base of the transistor 
Q.sub.15 into a signal. The signal thus obtained is supplied from the 
emitter of the transistor Q.sub.15 to the circuit in the next stage 
through an AC coupling capacitor C.sub.3. 
As mentioned above, in the signal-processing circuit according to this 
invention the number of the necessary AC coupling capacitors which serve 
to reduce the offset of DC coupling among the various circuits. Thus the 
number of the terminal pins of the signal-processing circuit is reduced 
proportionally. The signal-processing circuit is therefore made into an 
integral circuit more easily than otherwise. In addition, since the number 
of AC coupling capacitors is reduced, the signal-processing circuit can be 
manufactured at a lower cost.