Level shifters and semiconductor devices including the same

A level shifter includes an input circuit configured to generate and output first and second intermediate signals based on an input signal that transitions between a first voltage level and a second voltage level. The level shifter includes a feed forward circuit configured to receive the first intermediate signal from the input circuit and generate and output a third intermediate signal enabled in a part of a period in which the first intermediate signal is enabled and to receive the second intermediate signal from the input circuit and generate and output a fourth intermediate signal enabled in a part of a period in which the second intermediate signal is enabled. Moreover, the level shifter includes a level shifting circuit configured to receive the first through fourth intermediate signals and to shift the input signal to an output signal that transitions between a third voltage level and the second voltage level.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of Korean Patent Application No. 10-2020-0099229, filed on Aug. 7, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

The present disclosure relates to level shifters.

2. Description of the Related Art

A level shifter is a device that shifts a swing size of an input signal and outputs the input signal with the shifted swing size as an output signal. For example, the level shifter may shift an input signal that transitions between 0 volts (V) and 0.75 V to an output signal that transitions between 0 V and 1.2 V or to an output signal that transitions between 0 V and 0.5 V.

Such a level shifter may serve as an interface between circuits that use power supply voltages of different voltage levels. Therefore, a semiconductor device or electronic device composed of circuits using power supply voltages of different voltage levels may use a level shifter for shifting from one power supply voltage level to another power supply voltage level or to a specific voltage level.

However, as the size by which an input signal needs to be shifted increases, the size of an element included in the level shifter also increases. Therefore, research is being conducted on a method of reducing the size of the level shifter while maintaining the operating performance of the level shifter.

SUMMARY

Aspects of the present disclosure provide a level shifter which can be miniaturized

Aspects of the present disclosure also provide a semiconductor device which can be miniaturized.

A level shifter, according to some embodiments, may include an input circuit configured to generate and output first and second intermediate signals based on an input signal that transitions between a first voltage level and a second voltage level. The level shifter may include a feed forward circuit configured to receive the first intermediate signal from the input circuit and generate and output a third intermediate signal enabled in a part of a period in which the first intermediate signal is enabled and to receive the second intermediate signal from the input circuit and generate and output a fourth intermediate signal enabled in a part of a period in which the second intermediate signal is enabled. Moreover, the level shifter may include a level shifting circuit configured to receive the first and second intermediate signals from the input circuit and the third and fourth intermediate signals from the feed forward circuit and to shift the input signal to an output signal that transitions between a third voltage level and the second voltage level. The third voltage level may be different from the first voltage level.

A level shifter, according to some embodiments, may include a first pull-down transistor that is gated based on a first intermediate signal generated by inverting an input signal that transitions between a first voltage level and a second voltage level and is configured to pull down a voltage level of a first node to the second voltage level. The level shifter may include a second pull-down transistor that is gated based on a second intermediate signal generated by inverting the first intermediate signal and is configured to pull down a voltage level of a first output node to the second voltage level. The level shifter may include a first pull-up transistor that is gated based on the voltage level of the first node and is configured to pull up the first output node to a third voltage level greater than the first voltage level. The level shifter may include a first feed forward transistor that is gated based on a third intermediate signal generated by delaying the first intermediate signal and is configured to provide the second intermediate signal to the first node. Moreover, the level shifter may include a second feed forward transistor that is gated based on a fourth intermediate signal generated by delaying the second intermediate signal and is configured to provide the first intermediate signal to the first output node.

A level shifter, according to some embodiments, may include a first transistor that is configured to receive an input signal that transitions between a first voltage level and a second voltage level and to generate a first intermediate signal by inverting the input signal. The level shifter may include a second transistor that is configured to receive the first intermediate signal and to generate a second intermediate signal by inverting the first intermediate signal. The level shifter may include a first pull-down transistor that is gated based on the first intermediate signal and is configured to pull down a voltage level of a first node to the second voltage level. The level shifter may include a second pull-down transistor that is gated based on the second intermediate signal and is configured to pull down a voltage level of a first output node to the second voltage level. The level shifter may include a first pull-up transistor that is gated based on the voltage level of the first node and is configured to pull up the first output node to a third voltage level different from the first voltage level. The level shifter may include a first feed forward transistor that is gated based on a third intermediate signal and is configured to provide the second intermediate signal to the first node. Moreover, the level shifter may include a second feed forward transistor that is gated based on a fourth intermediate signal and is configured to provide the first intermediate signal to the first output node. A threshold voltage of the first transistor may be smaller than a threshold voltage of the second pull-down transistor.

A semiconductor device, according to some embodiments, may include a logic circuit that is configured to generate a first signal that transitions between a first voltage level corresponding to a first voltage and a second voltage level by using the first voltage. The semiconductor device may include a level shifter that is configured to receive the first signal and to shift the first signal to a second signal that transitions between a third voltage level and the second voltage level. The third voltage level may be different from the first voltage level. Moreover, the semiconductor device may include an input/output (I/O) circuit that is configured to buffer the second signal by using a second voltage corresponding to the third voltage level. The level shifter may include: an input circuit that is configured to generate and output a first intermediate signal from the first signal and a second intermediate signal different from the first intermediate signal; a feed forward circuit that is configured to receive the first intermediate signal from the input circuit and to generate and output a third intermediate signal enabled in a part of a period in which the first intermediate signal is enabled; and a level shifting circuit that is configured to receive the first and second intermediate signals from the input circuit and the third intermediate signal from the feed forward circuit and to shift the first signal to the second signal.

DETAILED DESCRIPTION

Hereinafter, embodiments according to the present disclosure will be described with reference to the accompanying drawings.

FIG. 1is a block diagram of a level shifter100according to some embodiments.FIG. 2is a circuit diagram of an input circuit110ofFIG. 1.FIG. 3is a circuit diagram of a feed forward circuit120ofFIG. 1.FIG. 4is a circuit diagram of the input circuit110and a level shifting circuit130ofFIG. 1.

Referring toFIGS. 1 through 4, the level shifter100may include the input circuit110, the feed forward circuit120, and the level shifting circuit130.

The input circuit110may receive an input signal IS provided to an input terminal IN. The input circuit110may generate intermediate signals IMS1and IMS2from (e.g., based on/responsive to) the input signal IS.

The input signal IS may transition between a first voltage level (e.g., VDD1, shown inFIG. 4) and a second voltage level (e.g., a ground voltage GND, shown inFIG. 7). That is, when the input signal IS is at a logic high level (hereinafter, referred to as an H level), the input signal IS may have a voltage value of VDD1. When the input signal IS is at a logic low level (hereinafter, referred to as an L level), the input signal IS may have a ground voltage GND value.

When the input signal IS is as described above, the intermediate signals IMS1and IMS2generated by the input circuit110may also have the same signal level as the input signal IS. Specifically, when the intermediate signals IMS1and IMS2are at the H level, they may have a voltage value of VDD1. When the intermediate signals IMS1and IMS2are at the L level, they may have a ground voltage GND value. That is, the input circuit110does not shift the level of the input signal IS.

In some embodiments, the input circuit110may generate the intermediate signal IMS1by performing a first logical operation on the input signal IS and may generate the intermediate signal IMS2by performing a second logical operation on the intermediate signal IMS1.

A case where the input circuit110generates the intermediate signal IMS1by inverting the input signal IS and generates the intermediate signal IMS2by inverting the intermediate signal IMS1will be described below as an example, but embodiments are not limited thereto.

The inverter INV1and the inverter INV2may be connected in series as illustrated in the drawing.

The inverter INV1may output the intermediate signal IMS1by inverting the input signal IS, and the inverter INV2may output the intermediate signal IMS2by inverting the intermediate signal IMS1.

Accordingly, the signal level of the intermediate signal IMS1is opposite to that of the input signal IS. That is, when the input signal IS is at the H level, the intermediate signal IMS1is at the L level. When the input signal IS is at the L level, the intermediate signal IMS1is at the H level. On the other hand, the signal level of the intermediate signal IMS2is the same as that of the input signal IS. That is, when the input signal IS is at the H level, the intermediate signal IMS2is also at the H level. When the input signal IS is at the L level, the intermediate signal IMS2is also at the L level.

Referring again toFIG. 1, the intermediate signals IMS1and IMS2generated by the input circuit110may be provided to the feed forward circuit120and the level shifting circuit130.

The feed forward circuit120may generate intermediate signals IMS3and IMS4from the intermediate signals IMS1and IMS2provided by the input circuit110. The intermediate signals IMS3and IMS4may be provided to the level shifting circuit130to perform a feed forward function. This will be described in more detail later.

When the input signal IS is a signal that transitions between VDD1and the ground voltage GND, the intermediate signals IMS3and IMS4generated by the feed forward circuit120may also have the same signal level as the input signal IS. Specifically, when the intermediate signals IMS3and IMS4are at the H level, they may have a voltage value of VDD1. When the intermediate signals IMS3and IMS4are at the L level, they may have a ground voltage GND value. That is, the feed forward circuit120does not shift the level of the input signal IS or the intermediate signals IMS1and IMS2.

Although a case where the input signal IS and the intermediate signals IMS1through IMS4are signals that transition between VDD1and the ground voltage GND has been described above as an example, embodiments are not limited thereto. In some embodiments, the input signal IS and the intermediate signals IMS1through IMS4may also be signals that transition between VDD1and another voltage (which may be referred to as “VSS”), not the ground voltage GND. Here, VSS can be modified as long as it is smaller than VDD1.

In some embodiments, the feed forward circuit120may generate the intermediate signal IMS3by performing a third logical operation on the intermediate signal IMS1and generate the intermediate signal IMS4by performing a fourth logical operation on the intermediate signal IMS2.

A case where the feed forward circuit120generates the intermediate signal IMS3by performing an AND operation on the intermediate signal IMS1and a signal obtained by delaying the intermediate signal IMS1and generates the intermediate signal IMS4by performing an AND operation on the intermediate signal IMS2and a signal obtained by delaying the intermediate signal IMS2will be described below as an example, but embodiments are not limited thereto.

Referring toFIG. 3, the feed forward circuit120may include delay units DE1and DE2and AND gates AND1and AND2.

The delay unit DE1may receive the intermediate signal IMS1, delay the intermediate signal IMS1for a predetermined time, and then output the delayed intermediate signal IMS1.

The AND gate AND1may receive the intermediate signal IMS1and an output (e.g., the delayed intermediate signal IMS1) of the delay unit DE1and may output the result of performing an AND operation on them as the intermediate signal IMS3.

Accordingly, the intermediate signal IMS3may be enabled in a part of a period in which the intermediate signal IMS1is enabled (hereinafter, an enabled period will be described as a period in which a signal maintains the H level).

For example, referring toFIG. 7, the intermediate signal IMS3may be enabled in the period in which the intermediate signal IMS1is enabled, excluding a delay time d. Accordingly, a time when the intermediate signal IMS1is enabled is faster/earlier than a time when the intermediate signal IMS3is enabled, and a time when the intermediate signal IMS1is disabled (hereinafter, a time when a signal becomes the L level will be described as an example) is substantially the same as a time when the intermediate signal IMS3is disabled. Here, “substantially the same” means that disable times of two signals may slightly differ due to the process margin of the circuit or a delay due to wiring but are not made different by a separate delay circuit.

Similarly, the delay unit DE2may receive the intermediate signal IMS2, delay the intermediate signal IMS2for a predetermined time, and then output the delayed intermediate signal IMS2.

The AND gate AND2may receive the intermediate signal IMS2and an output (e.g., the delayed intermediate signal IMS2) of the delay unit DE2and may output the result of performing an AND operation on them as the intermediate signal IMS4.

Accordingly, the intermediate signal IMS4may be enabled in a part of a period in which the intermediate signal IMS2is enabled.

For example, referring toFIG. 7, the intermediate signal IMS4may be enabled in the period in which the intermediate signal IMS2is enabled, excluding the delay time d.

Accordingly, a time when the intermediate signal IMS2is enabled is faster/earlier than a time when the intermediate signal IMS4is enabled, and a time when the intermediate signal IMS2is disabled is substantially the same as a time when the intermediate signal IMS4is disabled.

In some embodiments, each of the delay unit DE1and the delay unit DE2may include a delay line implemented as a plurality of delay inverters DINV. However, embodiments are not limited thereto.

The level shifting circuit130may receive the intermediate signals IMS1and IMS2from the input circuit110and the intermediate signals IMS3and IMS4from the feed forward circuit120and shift the input signal IS.

Specifically, the level shifting circuit130may shift the input signal IS that transitions between VDD1and the ground voltage GND to an output signal OS that transitions between VDD2and the ground voltage GND by using the intermediate signals IMS1through IMS4. In some embodiments, VDD2may be a power supply voltage greater than VDD1, but embodiments are not limited thereto. In addition, as described above, the level shifting circuit130may shift the input signal IS that transitions between VDD1and VSS to the output signal OS that transitions between VDD2and VSS by using the intermediate signals IMS1through IMS4.

Referring toFIG. 4, the input circuit110may include a plurality of transistors MN1, MN2, MP1and MP2, and the level shifting circuit130may include a plurality of transistors MN3through MN9and MP3through MP6.

The transistors MN1and MP1included in the input circuit110may correspond to the inverter INV1(seeFIG. 2) described above, and the transistors MN2and MP2may correspond to the inverter INV2(seeFIG. 2) described above.

The power supply voltage VDD1may be provided to the input circuit110. Although a detailed circuit diagram of circuit elements included in the feed forward circuit120(seeFIG. 3) is omitted fromFIG. 4, the power supply voltage VDD1may also be provided to the feed forward circuit120(seeFIG. 3).

The transistors MN1and MP1may output the intermediate signal IMS1by inverting the input signal IS input to the input terminal IN. The transistor MP1and the transistor MN1may be connected in series between the power supply voltage VDD1and a ground terminal.

The transistors MN2and MP2may output the intermediate signal IMS2by inverting the intermediate signal IMS1. The transistor MP2and the transistor MN2may be connected in series between the power supply voltage VDD1and the ground terminal.

The power supply voltage VDD2may be provided to the level shifting circuit130. In some embodiments, the power supply voltage VDD2may be greater than the power supply voltage VDD1. Specifically, the power supply voltage VDD1may be, for example, 0.7 to 0.8 V, and the power supply voltage VDD2may be, for example, 1.1 to 1.3 V. However, embodiments are not limited thereto.

The transistor MN3may be gated based on the first intermediate signal IMS1, and the transistor MN4may be gated based on the second intermediate signal IMS2.

The transistor MN3may be turned on to connect a node X and the ground terminal through the transistor MN7. That is, the transistor MN3may be turned on to operate as a pull-down transistor that pulls down the voltage level of the node X (e.g., down to the ground voltage GND).

The transistor MN4may be turned on to connect an output node YB and the ground terminal. That is, the transistor MN4may be turned on to operate as a pull-down transistor that pulls down the voltage level of the output node YB (e.g., down to the ground voltage GND).

The transistor MN5may be connected between a gate terminal of the transistor MN3and the output node YB. The transistor MN5may be gated based on the intermediate signal IMS4to provide the intermediate signal IMS1to the output node YB. Since a feed forwarding path through which the intermediate signal IMS1is provided to the output node YB is formed when the transistor MN5is turned on, the transistor MN5may operate as a feed forward transistor.

The transistor MN6may be connected between a gate terminal of the transistor MN4and the node X. The transistor MN6may be gated based on the intermediate signal IMS3to provide the intermediate signal IMS2to the node X. Since a feed forwarding path through which the intermediate signal IMS2is provided to the node X is formed when the transistor MN6is turned on, the transistor MN6may operate as a feed forward transistor.

Although only an embodiment in which the transistors MN5and MN6operating as feed forward transistors are included in the level shifting circuit130is illustrated in the drawing, embodiments are not limited thereto. The embodiment may also be modified to an embodiment in which the transistors MN5and MN6are included in the feed forward circuit120.

The transistor MP4may be gated based on the voltage level of the node X, and the transistor MP5may also be gated based on the voltage level of the node X.

The transistor MP4may be turned on to connect the node X and the power supply voltage VDD2. That is, the transistor MP4may be turned on to operate as a pull-up transistor that pulls up the voltage level of the node X.

The transistor MP5may be turned on to connect the output node YB and the power supply voltage VDD2. That is, the transistor MP5may be turned on to operate as a pull-up transistor that pulls up the voltage level of the output node YB (e.g., up to the power supply voltage VDD2).

The transistor MN7may be gated based on the inverted voltage level of the output node YB (or the voltage level of an output node Y) to connect the node X and the ground terminal. In an embodiment, the transistor MN7may operate as a pull-down transistor that pulls down the voltage level of the node X (e.g., down to the ground voltage GND).

The transistor MP3may be gated based on the voltage level of the output node YB to connect the node X and the power supply voltage VDD2. In an embodiment, the transistor MP3may operate as a keeper transistor that maintains the voltage level of the node X at the power supply voltage VDD2.

The transistor MN8may be gated based on the inverted voltage level of the output node YB (or the voltage level of the output node Y) to connect the output node YB and the ground terminal. In an embodiment, the transistor MN8may operate as a keeper transistor that maintains the voltage level of the output node YB at the ground voltage GND.

The transistors MP6and MN9may invert the voltage level of the output node YB and provide it to the output node Y. That is, the transistors MP6and MN9may operate as an inverter. Accordingly, the voltage level of the output node YB may be inverted and output to an output terminal OUT in the form of the output signal OS.

As described above, when the input signal IS and the intermediate signals IMS1through IMS4are signals that transition between VDD1and VSS and the output signal OS is a signal that transitions between VDD2and VSS, the configuration of the circuit may be modified such that VSS is supplied to the ground terminal of the illustrated circuit.

In addition, although N-type transistors and P-type transistors are distinguished in the drawing, embodiments are not limited thereto. When the forms of the intermediate signals IMS1through IMS4are modified, the types of transistors may also be modified.

Referring toFIG. 4, in some embodiments, the transistors MN1, MN2, MP1and MP2included in the input circuit110and the transistors MN3through MN9and MP3through MP6included in the level shifting circuit130may be turned on at different threshold voltages.

For example, if the power supply voltage VDD2provided to the level shifting circuit130is greater than the power supply voltage VDD1provided to the input circuit110as in the illustrated example, threshold voltages of the transistors MN3through MN9and MP3through MP6included in the level shifting circuit130may be greater than threshold voltages of the transistors MN1, MN2, MP1and MP2included in the input circuit110to improve circuit driving capability.

Specifically, the threshold voltages of the transistors MN3and MN5which receive the intermediate signal IMS1may be greater than the threshold voltages of the transistors MP1and MN1which provide the intermediate signal IMS1, and the threshold voltages of the transistors MN4and MN6which receive the intermediate signal IMS2may be greater than the threshold voltages of the transistors MP2and MN2which provide the intermediate signal IMS2.

More specifically, the threshold voltages of the transistors MN3through MN9and MP3through MP6included in the level shifting circuit130may be, for example, 1 to 1.5 V, and the threshold voltages of the transistors MN1, MN2, MP1and MP2included in the input circuit110may be, for example, 0.5 to 1 V. However, embodiments are not limited thereto.

Although not illustrated in detail, transistors included in the feed forward circuit120and the transistors MN3through MN9and MP3through MP6included in the level shifting circuit130may also have different threshold voltages.

Specifically, the threshold voltages of the transistors MN3through MN9and MP3through MP6included in the level shifting circuit130may be greater than the threshold voltages of the transistors included in the feed forward circuit120to improve the circuit driving capability.

In some embodiments, the transistors MN1, MN2, MP1and MP2included in the input circuit110and the transistors MN3through MN9and MP3through MP6included in the level shifting circuit130may have different sizes.

For example, if the power supply voltage VDD2provided to the level shifting circuit130is greater than the power supply voltage VDD1provided to the input circuit110as in the illustrated example, sizes of the transistors MN3through MN9and MP3through MP6included in the level shifting circuit130may be larger than sizes of the transistors MN1, MN2, MP1and MP2included in the input circuit110to improve the circuit driving capability.

This will now be described in more detail with reference toFIGS. 5 and 6.

FIGS. 5 and 6are diagrams comparing the sizes of the transistors illustrated inFIG. 4.

First,FIG. 5is a diagram comparing the size of the transistor MN4included in the level shifting circuit130with the size of the transistor MN1included in the input circuit110. The following description may also be applied to other transistors included in the level shifting circuit130and other transistors included in the input circuit110.

Referring toFIG. 5, in some embodiments, each of the transistor MN4and the transistor MN1may include a fin field-effect transistor (FinFET).

A gate electrode GE constituting the transistor MN4may extend while conformally covering a plurality of fins F, each having a source SO and a drain DR, and may overlap M fins F.

A gate electrode GE constituting the transistor MN1may also extend while conformally covering a plurality of fins F, each having a source SO and a drain DR, and may overlap N fins F.

When the power supply voltage VDD2is greater than the power supply voltage VDD1as described above, M may be greater than N. That is, the transistor MN4may include (e.g., have a gate electrode GE that overlaps) a larger number of fins F than the transistor MN1.

Next,FIG. 6is a diagram comparing the size of the transistor MN4and the size of the transistor MP5included in the level shifting circuit130.

Referring toFIG. 6, in some embodiments, each of the transistor MN4and the transistor MP5may include a FinFET.

The gate electrode GE constituting the transistor MN4may extend while conformally covering a plurality of fins F, each having the source SO and the drain DR, and may overlap M fins F.

A gate electrode GE constituting the transistor MP5may also extend while conformally covering a plurality of fins F, each having a source SO and a drain DR, and may overlap M fins F.

In the level shifting circuit130according to the current embodiment, the transistor MN4and the transistor MP5may have substantially the same size as described above. Here, the fact that the transistor MN4and the transistor MP5have substantially the same size is a concept including a change in size according to a process variation. That is, although the transistor MN4and the transistor MP5are designed to have the same size, size changes that occur in the process of forming the transistor MN4and the transistor MP5may be treated as being substantially the same for each transistor.

In the current embodiment, the transistor MN4and the transistor MP5may include (e.g., have a gate electrode GE that overlaps) the same number of fins F. This may be the effect of the feed forward circuit120and the feed forward transistor MN5described above.

If the feed forward circuit120and the feed forward transistor MN5do not exist (i.e., are absent from the level shifter100), the transistor MN4may have to be formed larger than the transistor MP5to improve its driving capability. That is, the number of fins F included in the transistor MN4may have to be larger than the number of fins F included in the transistor MP5.

In the current embodiment, however, since the driving capability of the transistor MN4is improved by the feed forward circuit120and the feed forward transistor MN5, the size of the transistor MN4can be reduced.

Although not illustrated in detail, in the level shifting circuit130according to the current embodiment, the transistor MN3and the transistor MP4may also have substantially the same size. That is, the transistor MN3and the transistor MP4may include (e.g., have a gate electrode GE that overlaps) the same number of fins F, which may also be the effect of the feed forward circuit120and the feed forward transistor MN6described above.

If the feed forward circuit120and the feed forward transistor MN6do not exist (i.e., are absent from the level shifter100), the transistor MN3may have to be formed larger than the transistor MP4to improve its driving capability. That is, the number of fins F included in the transistor MN3may have to be larger than the number of fins F included in the transistor MP4.

In the current embodiment, however, since the driving capability of the transistor MN3is improved by the feed forward circuit120and the feed forward transistor MN6, the size of the transistor MN3can be reduced.

The operation of the level shifter100will now be described with reference toFIGS. 3 and 7 through 11.

FIG. 7is a timing diagram illustrating the operation of the level shifter100according to some embodiments.FIGS. 8 through 11are diagrams for explaining the operation of the level shifter100according to some embodiments.

FIG. 7illustrates timing of voltage levels of the input signal IS, the intermediate signals IMS1through IMS4, and the output node YB. A minute/small delay between the input signal IS and the intermediate signals IMS1and IMS2is ignored, and the voltage level of the output node YB is rather exaggerated in the drawing for ease of description. In the following description, a signal will be regarded as being enabled when transitioning to the H level and as being disabled when transitioning to the L level. However, embodiments are not limited thereto.

Referring toFIGS. 3, 7 and 8, at a first time T1, the input signal IS transitions to the H level and is enabled. When the input signal IS becomes the H level, the intermediate signal IMS1transitions to the L level and is disabled, and the intermediate signal IMS2transitions to the H level and is enabled.

Since the intermediate signal IMS1is at the L level, an output of the AND gate AND1of the feed forward circuit120is at the L level. Therefore, the intermediate signal IMS3transitions to the L level.

Although the intermediate signal IMS2is at the H level, an output of the delay unit DE2is at the L level while the intermediate signal IMS2is delayed by the delay unit DE2. Therefore, an output of the AND gate AND2of the feed forward circuit120is also at the L level. Accordingly, the intermediate signal IMS4maintains the L level.

Since the intermediate signal IMS1is at the L level, the transistor MN3is turned off. Since the intermediate signal IMS2is at the H level, the transistor MN4is turned on. As the transistor MN4is turned on, the output node YB is connected to the ground terminal. Accordingly, the voltage level of the output node YB starts to fall with a first slope.

Since the voltage level of the output node YB was at the H level at the first time T1, the transistors MN7and MN8are kept turned off. In addition, the transistors MP3through MP5are kept turned off.

Next, referring toFIGS. 3, 7 and 9, at a second time T2delayed from the first time T1by the delay time d, the output of the delay unit DE2becomes the H level. Therefore, the output of the AND gate AND2of the feed forward circuit120becomes the H level. Accordingly, the intermediate signal IMS4becomes the H level.

Since the intermediate signal IMS4is at the H level, the transistor MN5is turned on. Accordingly, the intermediate signal IMS1at the L level is provided to the output node YB. When such a feed forward path is formed, the voltage level of the output node YB falls more steeply. That is, the voltage level of the output node YB falls with a second slope greater than the first slope described above.

As the voltage level of the output node YB falls rapidly, the transistor MN8is turned on to connect the output node YB and the ground terminal. In addition, the transistor MP3is turned on to supply the power supply voltage VDD2to the node X. In addition, the transistor MN7is turned on. Since the power supply voltage VDD2is supplied to the node X, the transistors MP4and MP5are kept turned off.

When a sufficient time elapses from the second time T2, the output node YB transitions to the ground voltage GND level. Accordingly, the output signal OS having the level of the power supply voltage VDD2is output to the output terminal OUT by the transistors MP6and MN9.

Next, referring toFIGS. 3, 7 and 10, at a third time T3, the input signal IS transitions to the L level and is disabled. When the input signal IS becomes the L level, the intermediate signal IMS1transitions to the H level and is enabled, and the intermediate signal IMS2becomes the L level and is disabled.

Since the intermediate signal IMS2is at the L level, the output of the AND gate AND2of the feed forward circuit120is at the L level. Therefore, the intermediate signal IMS4transitions to the L level.

Although the intermediate signal IMS1is at the H level, the output of the delay unit DE1is at the L level while the intermediate signal IMS1is delayed by the delay unit DE1. Therefore, the output of the AND gate AND1of the feed forward circuit120is also at the L level. Accordingly, the intermediate signal IMS3maintains the L level.

Since the intermediate signal IMS2is at the L level, the transistor MN4is turned off. Since the intermediate signal IMS1is at the H level, the transistor MN3is turned on. Since the output node YB still maintains the ground voltage GND level, the transistor MN7is kept turned off. Accordingly, the node X is connected to the ground terminal, and the voltage level of the node X falls.

As the voltage level of the node X falls, the transistors MP4and MP5are turned on. As the transistor MP5is turned on, the power supply voltage VDD2is supplied to the output node YB, and thus the voltage level of the output node YB starts to rise with a third slope. As the voltage level of the output node YB rises, the transistor MP3and the transistor MN8are turned off.

Next, referring toFIGS. 3, 7 and 11, at a fourth time T4delayed from the third time T3by the delay time d, the output of the delay unit DE1becomes the H level. Therefore, the output of the AND gate AND1of the feed forward circuit120becomes the H level. Accordingly, the intermediate signal IMS3becomes the H level.

Since the intermediate signal IMS3is at the H level, the transistor MN6is turned on. Accordingly, the intermediate signal IMS2at the L level is provided to the node X. When such a feed forward path is formed, the voltage level of the node X falls more steeply. Therefore, the voltage level of the output node YB rises with a fourth slope greater than the third slope described above.

When a sufficient time elapses from the fourth time T4, the output node YB transitions to the level of the power supply voltage VDD2. Accordingly, the output signal OS having the ground voltage GND level is output to the output terminal OUT by the transistors MP6and MN9.

As described above, in the current embodiment, a level shifting operation is performed more efficiently by forming a feed forward path in a level shifting process. Accordingly, the driving load of the transistors MN3and MN4can be reduced, thereby lowering the threshold voltages of the transistors MN3and MN4and reducing the sizes of the transistors MN3and MN4. That is, a miniaturized level shifter can be manufactured.

Although an embodiment in which the level shifting circuit130receives the first and second intermediate signals IMS1and IMS2through the input circuit110has been described above, embodiments are not limited thereto. In some embodiments, the level shifting circuit130may also operate by simultaneously receiving a first signal provided to the input terminal IN and a second signal obtained by inverting the first signal directly without passing through the input circuit110. In this case, the feed forward circuit120may generate the feed forward signals described above based on the first signal and the second signal.

FIG. 12is a circuit diagram of a level shifter200according to some embodiments.

Differences from the above-described embodiments will be mainly described below.

Referring toFIG. 12, the level shifter200includes an input circuit210and a level shifting circuit230. Although not illustrated in detail, the level shifter200may include a feed forward circuit which generates intermediate signals IMS3and IMS4.

A power supply voltage VDD3may be provided to the level shifting circuit230. Here, the power supply voltage VDD3may be a voltage lower than the power supply voltage VDD2provided to the level shifting circuit130(seeFIG. 4) described above.

In some embodiments, when the power supply voltage VDD2is, for example, 1.1 to 1.3 V, the power supply voltage VDD3may be 0.9 to 1.0 V. However, embodiments are not limited thereto.

In some embodiments, transistors MN1, MN2, MP1and MP2included in the input circuit210and transistors MN3through MN9and MP3through MP6included in the level shifting circuit230may be turned on at substantially the same threshold voltage.

Here, “substantially the same” is a concept including a change in threshold voltage according to a process variation. That is, although the transistors MN1, MN2, MP1and MP2included in the input circuit210and the transistors MN3through MN9and MP3through MP6included in the level shifting circuit230are designed to have the same threshold voltage, minute/small threshold voltage changes that occur in the process of forming the transistors may be treated as being substantially the same for each transistor.

In some embodiments, the transistors MN1, MN2, MP1and MP2included in the input circuit210and the transistors MN3through MN9and MP3through MP6included in the level shifting circuit230may have substantially the same size.

If the transistors MN1, MN2, MP1and MP2included in the input circuit210and the transistors MN3through MN9and MP3through MP6included in the level shifting circuit230include FinFETs, they may be configured to include the same number of fins.

FIG. 13is a partial cross-sectional view of a semiconductor device1000according to some embodiments.

Referring toFIG. 13, the semiconductor device1000may include, for example, a memory device. Specifically, the semiconductor device1000may include a high bandwidth memory (HBM).

The semiconductor device1000may include a base substrate1050, an interposer1100, a logic chip1200, and a memory chip1320. Although one memory chip1320is illustrated in the drawing, the semiconductor device1000may include a plurality of memory chips. In some embodiments, the memory chips may be arranged symmetrically to each other with respect to the logic chip1200.

The memory chip1320may be disposed on a side surface of the interposer1100, and the logic chip1200may be disposed on a center of an upper surface of the interposer1100. The logic chip1200may control the memory chip1320.

The memory chip1320may include memory dies MD1through MD4and a base die BD (or a buffer die). The memory dies MD1through MD4and the base die BD may be sequentially staked as illustrated inFIG. 13.

The memory dies MD1through MD4may be stacked on the base die BD. First bumps MB may be disposed between the stacked memory dies MD1through MD4and the base die BD, and through silicon vias TSV may penetrate the memory dies MD1through MD4while electrically connecting the first bumps MB to each other.

First direct access (DA) bumps dab, first power bumps pb1, and first command and address bumps and data bumps cadb1may be disposed on a lower surface of the base die BD.

Although only the memory chip1320is illustrated inFIG. 13, the other unillustrated memory chips of the semiconductor device1000may have the same structure as the illustrated structure.

Second command and address bumps and data bumps cadb2, second power bumps pb2, and first control signal and data bumps cdb may be disposed on a lower surface of the logic chip1200.

The logic chip1200may be, for example, a graphics processing unit (GPU) die, a central processing unit (CPU) die, or a system on chip (SoC).

The first bumps MB, the first DA bumps dab, the first and second power bumps pb1and pb2, the first and second command and address bumps and data bumps cadb1and cadb2, and the first control signal and data bumps cdb may be, but are not limited to, micro-bumps.

Second DA bumps DAFB, third power bumps PBFB, and second control signal and data bumps CDFB may be disposed on a lower surface of the interposer1100.

The second DA bumps DAFB, the third power bumps PBFB, and the second control signal and data bumps CDFB may include, but are not limited to, at least one of, e.g., tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations of the same.

The interposer1100may include DA lines dal connecting the first DA bumps dab and the second DA bumps DAFB, command and address lines and data lines cad1connecting the first command and address bumps and data bumps cadb1and the second command and address bumps and data bumps cadb2, and control signal and data lines cdl connecting the first control signal and data bumps cdb and the second control signal and data bumps CDFB.

Although not illustrated in detail, the interposer1100may additionally include power lines connecting the first power bumps pb1and the third power bumps PBFB and connecting the second power bumps pb2and the third power bumps PBFB.

The interposer1100may include, but is not limited to, at least one of silicon, glass, ceramic, and plastic.

The second DA bumps DAFB, the third power bumps PBFB, and the second control signal and data bumps CDFB may be, but are not limited to, flip die bumps.

DA balls DAB, power balls PB, and control signal and data balls CDB may be disposed on a lower surface of the base substrate1050.

The DA balls DAB, the power balls PB, and the control signal and data balls CDB may include, but are not limited to, at least one of, e.g., tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations of the same.

In the base substrate1050, the second DA bumps DAFB may be connected to the DA balls DAB, the third power bumps PBFB may be connected to the power balls PB, and the second control signal and data bumps CDFB may be connected to the control signal and data balls CDB.

The base substrate1050may be, but is not limited to, a printed circuit board (PCB) or a ceramic substrate.

When the base substrate1050is a PCB, it may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the base substrate1050may include at least one material selected from FR4, tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimide triazine (BT), thermount, cyanate ester, polyimide, and liquid crystal polymer. A surface of the base substrate1050may be covered by solder resist, but the invention of the present disclosure is not limited to this case.

The logic chip1200may process data in response to a control signal received through the second control signal and data bumps CDFB, generate the processed data as channel data, and transmit the channel data to the base die BD through the first command and address bumps and data bumps cadb1, together with channel commands and addresses.

FIG. 14is a block diagram of the semiconductor device1000ofFIG. 13.

Referring toFIG. 14, the logic chip1200may include a plurality of input/output (I/O) circuits1230. The I/O circuits1230may be connected to a plurality of wirings1110disposed in the interposer1100, respectively. The wirings1110disposed in the interposer1100may be connected to a plurality of memory elements1321disposed in the memory chip1320, respectively.

Level shifters (LS)1220may transfer signals between digital logic (DL) circuits1210and the I/O circuits1230. For example, each of the digital logic circuits1210may output a first signal which transitions between the level of a power supply voltage VDD4and a ground voltage GND level, and each of the level shifters1220may shift the first signal to a second signal which transitions between the level of a power supply voltage VDD5and the ground voltage GND level. The second signal may be transmitted to each memory element1321through an I/O circuit1230and a wiring1110disposed in the interposer1100.

If the first signal is not shifted to the second signal by a level shifter1220, it may fail to meet interface specifications. Thus, an I/O circuit1230cannot output the first signal to a memory element1321through a wiring1110disposed in the interposer1100.

In some embodiments, the configuration of each level shifter1220may employ the configurations of the level shifters100and200described above.

FIG. 15is a block diagram of a semiconductor device2000according to some embodiments.

Referring toFIG. 15, the semiconductor device2000may include, for example, an image sensing device that converts an optical image into an electrical signal.

The semiconductor device2000may include a timing generator2200, a row driver2300, and a pixel array2400.

The timing generator2200may generate a signal which is a reference for operation timing of various components of the image sensing device. The operation timing reference signal generated by the timing generator2200may be transmitted to the row driver2300and an analog-to-digital converter, a ramp signal generator, etc. not illustrated in the drawing.

The pixel array2400may sense an external image. The pixel array2400may include a plurality of pixels (or unit pixels). The row driver2300may selectively activate rows of the pixel array2400.

The row driver2300may include vertical decoders2320, logic units2340, level shifters2360, and drivers2380.

The row driver2300may receive the operation timing reference signal generated by the timing generator2200.

Each of the logic units2340may provide an enable signal to a level shifter2360according to the decoding result of a vertical decoder2320.

Each of the level shifters2360may be enabled by the enable signal and provide an output signal, whose level has been changed, to a driver2380. For example, the level shifters100and200described above may be employed as the level shifters2360.

Each of the drivers2380may correct the signal output from a level shifter2360and input the corrected signal to the pixel array2400.

In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the example embodiments without substantially departing from the principles of the present invention. Therefore, the disclosed example embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation.