Nonvolatile memory devices, channel boosting methods thereof, programming methods thereof, and memory systems including the same

Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C §119 to Korean Patent Application No. 10-2010-0077473 filed Aug. 11, 2010 in the Korean Intellectual Property Office (KIPO), the entire contents of which is incorporated herein by reference.

BACKGROUND

Example embodiments of the inventive concepts relate to non-volatile memory devices, channel boosting methods thereof, programming methods thereof, and memory systems including the same.

2. Description of the Related Art

Semiconductor memory devices are vital microelectronic components commonly found in digital logic systems, such as computers, and microprocessor-based applications ranging from satellites to consumer electronics. Therefore, advances in the fabrication of semiconductor memory devices, including process enhancements and circuit-design-related developments that allow scaling to higher memory densities and faster operating speeds, help establish performance standards for other digital logic families.

Semiconductor memory devices generally include volatile semiconductor memory devices and non-volatile semiconductor memory devices. Non-volatile semiconductor memory devices are capable of storing data even with the power turned off. The non-volatile memory data storage state may be permanent or reprogrammable, depending upon the fabrication technology used. Non-volatile semiconductor memories are used for program and microcode storage in a wide variety of applications in the computer, avionics, telecommunications, and consumer electronics industries.

A representative non-volatile memory device is a flash memory device. As the demand on the high integration of a memory device increases, multi-bit memory devices storing multi-bit data per memory cell are becoming more common.

SUMMARY

At least one example embodiment of the inventive concepts provides a channel boosting method of a non-volatile memory device in which at least two strings are connected to one bit line. The channel boosting method includes applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings and boosting channels of the floated inhibit strings.

According to example embodiments, the initial channel voltage may be a bit line program voltage. According to example embodiments, the initial channel voltage may be a bit line program-inhibit voltage. According to example embodiments, each of the strings may be connected with a corresponding bit line and extends in a direction vertical to a substrate. According to example embodiments, program strings each having a memory cell to be programmed may be shut off to be floated. According to example embodiments, inhibit strings corresponding to selected bit lines may be shut off to be floated, and inhibit strings corresponding to unselected bit lines may be electrically isolated to be floated. According to example embodiments, the channel boosting may be accomplished by applying a pass voltage to unselected word lines, and the pass voltage may be applied to a selected word line during a predetermined period.

Other example embodiments of the inventive concepts provide a program method of a non-volatile memory device which includes groups of memory cells sequentially provided in a direction vertical to a substrate and in which at least two strings are connected to one bit line. The program method includes performing a bit line setup operation together with a channel boosting operation and performing a program execution operation by applying a program voltage to a selected word line.

According to example embodiments, the bit line setup operation may include a first bit line setup period, during the first bit line setup period, a power supply voltage being applied to unselected bit lines, all strings of a selected memory block being floated by the selected word line, a pass voltage being applied to the selected word line and unselected word lines. According to example embodiments, during the first bit line setup period, the all strings may be floated by applying a ground voltage to a ground selection line and to all string selection lines. According to example embodiments, the bit line setup operation may further include a second bit line setup period, and during the second bit line setup period, a channel of a string corresponding to a selected one of all string selection lines is set to a ground voltage by applying a power supply voltage to the selected string selection line.

According to example embodiments, the program voltage may be applied to the selected word line following the second bit line setup period. According to example embodiments, the bit line setup operation may include a first bit line setup period in which a power supply voltage is applied to all bit lines and all string selection lines and a ground voltage is applied to a ground selection line. According to example embodiments, a ground voltage may be applied to at least one unselected one of the all string selection lines. According to example embodiments, the bit line setup operation may further include a second bit line setup period in which a ground voltage is applied to a selected one of the all bit lines in synchronization with applying of a ground voltage into the at least one unselected string selection line, and a pass voltage is applied to unselected word lines following the second bit line setup period.

According to at least one example embodiment, a channel boosting method of a non-volatile memory device in which at least two strings are connected to one bit line includes applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings of the strings in the selected memory block and boosting channel voltages of the floated inhibit strings.

According to at least one example embodiment, a method of programming a three-dimensional (3D) non-volatile memory device includes applying a first channel voltage to a channel of a selected memory string and channels of a plurality of unselected memory strings and applying a second channel voltage to the channel of the selected memory string.

DETAILED DESCRIPTION

According to example embodiments of the inventive concepts, non-volatile memory devices may be configured such that at least two strings are connected with one bit line. At programming, all inhibit strings that are floated may be channel boosted after an initial voltage is applied to channels of all strings within a selected memory block. Inhibit strings are strings each having a program inhibited memory cell among strings each having a memory cell connected with a selected word line.

According to example embodiments, the inhibit string may be a string (hereinafter, referred to as the first inhibit string) with a memory cell connected with a selected word line and an unselected bit line or a string (hereinafter, referred to as the second inhibit string) having a program inhibited memory cell connected with a selected word line and a selected bit line. A program string may be a string with a memory cell to be programmed among strings each with a memory cell connected with a selected word line and a selected bit line.

Channel boosting according to an example embodiments of the inventive concepts may be performed under the same initial condition. This may allow an optimized and/or improved pass voltage to be determined. No program disturbance may be generated. A program disturbance may represent that memory cells connected with unselected word lines adjacent to a selected word line are programmed according to a program voltage.

A non-volatile memory device according to at least one example embodiments of the inventive concepts may be, for example, a vertical NAND flash memory, a NAND flash memory, a NOR flash memory, a resistive RAM (RRAM), a phase-change RAM (PRAM), a magnetroresistive RAM (MRAM), a ferroelectric RAM (FRAM), and/or a spin transfer torque RAM (STT-RAM). The non-volatile memory device may be implemented with a three-dimensional array structure. Example embodiments of the inventive concepts may be applied to both a flash memory device with a conductive floating gate as a charge storing layer and a charge trap flash (CTF) memory with an insulation film as a charge storing layer. For ease of description, it may be assumed that the non-volatile memory device according to example embodiments of the inventive concepts may be a vertical NAND flash memory.

FIG. 1is a block diagram of non-volatile memory devices according to example embodiments of the inventive concepts. Referring toFIG. 1, a non-volatile memory device100may include a memory cell array110, an address decoder120, a read and write circuit130, a data input/output circuit140, and control logic150. The memory cell array110may be connected both to the address decoder120via word lines WL and to the read and write circuit130via bit lines BL. The memory cell array110may include a plurality of memory cells. Each memory cell may store one or more data bits.

The memory cell array110may include a plurality of memory blocks BLK1-BLKh, each of which may be of a three-dimensional (or, vertical) structure. For example, each of the memory blocks BLK1-BLKh may include structures extending in the first to third directions. In at least one example embodiment, each of the memory blocks BLK1-BLKh may include a plurality of strings extending in the second direction. For example, a plurality of strings may be provided in the first and third directions. Each string may be connected with a bit line BL, a string selection line SSL, a ground selection line GSL, word lines WL and a common source line CSL. The respective memory blocks BLK1-BLKh may be connected with a plurality of bit lines BL, a plurality of string selection lines SSL, a plurality of ground selection line GSL, a plurality of word lines WL, and a plurality of common source lines CSL.

The address decoder120may be connected with the memory cell array110via the word lines WL. The address decoder120may be configured to operate responsive to the control of the control logic150. The address decoder120may receive an address ADDR from the outside. The address decoder120may decode a row address of the input address ADDR to select corresponding word lines of the plurality of word lines WL. The address decoder120may decode a column address of the input address ADDR to transfer the decoded address to the read and write circuit130. According to at least one example embodiment, the address decoder120may include well-known constituent elements such as a row decoder, a column decoder, an address buffer, and the like.

The read and write circuit130may be connected to the memory cell array110via the bit lines BL and to the data input/output circuit140via data lines DL. The read and write circuit130may operate responsive to the control of the control logic150. The read and write circuit130may receive the decoded column address from the address decoder120. The read and write circuit130may select the bit lines BL using the decoded column address. According to at least one example embodiment, the read and write circuit130may receive data from the data input/output circuit140to store it in the memory cell array110. The read and write circuit130may read data from the memory cell array110to send it to the data input/output circuit140. The read and write circuit130may be configured to perform a copy-back operation.

According to example embodiments, the read and write circuit130may include well-known elements such as a page buffer (or, a page register), a column selecting circuit, and the like (not shown). According to other example embodiments, the read and write circuit130may include well-known elements such as a sense amplifier, a write driver, a column selecting circuit, and the like (not shown). The data input/output circuit140may be connected to the read and write circuit130via the data lines DL. The data input/output circuit140may operate responsive to the control of the control logic150. The data input/output circuit140may be configured to exchange data DATA with an external device. The data input/output circuit140may be configured to transfer data DATA provided from the external device to the read and write circuit130via the data lines DL.

The data input/output circuit140may be configured to output data DATA transferred from the read and write circuit130via the data lines to the external device. According to at least one example embodiment, the data input/output circuit140may include a well-known element, for example, a data buffer (not shown). The control logic150may be connected with the address decoder120, the read and write circuit130, and the data input/output circuit140and may be configured to control an overall operation of the flash memory device100. The control logic150may operate responsive to control signals CTRL transferred from the external device.

The control logic150may control a program operation such that inhibit strings may be channel boosted from the same initial channel voltage (e.g., a ground voltage or a pre-charge voltage). According to the control of the control logic150, at a program operation, channels of all inhibit strings may have the same initial channel voltage, and then channels of floated inhibit strings may be boosted.

The following advantages may be obtained by setting inhibit strings to the same initial channel voltage. Typically, at a program operation, a non-volatile memory device may set up bit lines and then may perform a channel boosting operation. For this reason, an initial channel voltage of a first inhibit string connected with an unselected bit line may be different from that of the second inhibit string connected with a selected bit line. That is, channel boosting may be made under different initial conditions. For example, an initial channel voltage of the second inhibit string connected with a selected bit line may be a bit line program voltage (e.g., 0V), and an initial channel voltage of the first inhibit string connected with an unselected bit line may be a bit line program inhibit voltage (e.g., a pre-charge voltage). Accordingly, initial conditions of the first and second inhibit strings are different from each other. This may make it difficult to secure a pass voltage window (a Vpass window). It may be difficult to determine an optimum and/or improved pass voltage for optimizing the program disturbance.

The non-volatile memory device100according to at least one example embodiment of the inventive concepts may be configured, at a program operation, such that channel boosting may be made after the same initial channel voltage may be applied to inhibit strings. The non-volatile memory device100may make it easy to secure the pass voltage window. In other words, it may be easy to determine an optimum and/or improved pass voltage of the non-volatile memory device100. A non-volatile memory device100according to example embodiments of the inventive concepts may perform a bit line setup operation together with channel boosting at a program operation. It may be possible to reduce a program time as compared with the case that channel boosting may be made after a bit line setup operation is executed.

FIG. 2is a perspective view of one of memory blocks illustrated inFIG. 1.FIG. 3is a cross-sectional view taken along line of the memory block illustrated inFIG. 2. Referring toFIGS. 2 and 3, a memory block BLKi may include structures that extend in the first to third directions. A substrate111may be provided. The substrate111may include a silicon material to which a first type impurity may be injected. For example, the substrate111may include a silicon material to which a p-type impurity is injected. As an example, the substrate111may be a p-type well (or, a pocket p-well). For example, the substrate may include an n-type well which surrounds a p-type well. For purposes of explanation, it may be assumed that the substrate111is p-type silicon. However, the substrate111is not limited thereto.

A plurality of doping regions311-314extending in the first direction may be provided onto the substrate111. For example, a plurality of doping regions311-314may be a second conductivity type different from that of the substrate111. For example, the doping regions311-314may be n-type. It may be assumed for purposes of explanation that the first to fourth doping regions311-314are n-type. However, the first to fourth doping regions311-314are not limited thereto. In a region on the substrate111between the first and second doping regions311and312, a plurality of insulating materials112extending in the first direction may be sequentially provided in the second direction. For example, the plurality of insulating materials112and the substrate111may be formed to be separated by a distance in the second direction. For example, the insulating materials112may be separated by a distance in the second direction. The insulating materials112may include an insulating material, for example, silicon oxide.

In the region on the substrate111between the first and second doping regions311and312, a plurality of pillars113may be provided, sequentially disposed in the first direction, and pass through the insulating materials112in the second direction. The pillars113may be connected to the substrate111through the insulating materials112. Each of the pillars113may include a plurality of materials. For example, the surface layer114of each pillar113may include a silicon material having the first type. For example, the surface layer114of each pillar113may include a silicon material which may be doped a material of the same conductivity type as the substrate111. It may be assumed for purposes of explanation that the surface layer114of each pillar113may include p-type silicon. However, the surface layer114of each pillar113are not limited thereto.

The inner layer115of each pillar113may be an insulating material. For example, the inner layer115of each pillar113may include silicon oxide. In a region between the first and second doping regions311and312, an insulation layer116may be provided along an exposed surface of the substrate11, the insulating materials112and the pillars113. For example, the thickness of the insulation layer116may be less than half a distance between the insulating materials112. A region where a material other than the insulating materials112and the insulation layer116may be disposed, may be provided between an insulation layer116on a lower surface of the first insulating material among the insulating materials112and an insulation layer116on an upper surface of the second insulating material and at the lower portion of the first insulating material.

In the region between the first and second doping regions311and312, conductive materials211-291may be on an exposed surface of the insulation layer116. For example, the conductive material211extending in the first direction may be between the substrate111and the insulating material112adjacent to the substrate111. The conductive material211extending in the first direction may be between the substrate111and the insulation layer116on the lower surface of the insulating material112adjacent to the substrate111. A conductive material extending in the first direction may be between the insulation layer116of an upper surface of a specific insulating material among the insulating materials112and the insulation layer116of a lower surface of an insulating material at the upper portion of the specific insulating material.

The conductive materials221-281extending in the first direction may be between the insulating materials112. The first conductive materials211-291may be, for example, metal materials. The conductive materials211-291may be, for example, polysilicon. The same structure as the first and second doping regions311and312may be provided between the second and third doping regions312and313. Between the second and third doping regions312and313, there may be insulating materials112extending in the first direction, the pillars113sequentially disposed in the first direction and passing through the insulating materials112in the third direction, the insulation layer116on the insulating materials112and exposed surfaces of the pillars113, and the conductive materials212-292, extending in the first direction.

The same structure as a structure on the first and second doping regions311and312may be provided between the third and fourth doping regions313and314. Between the third and fourth doping regions313and314, there may be insulating materials112extending in the first direction, the pillars113sequentially disposed in the first direction and passing through the insulating materials112in the third direction, the insulation layer116on the insulating materials112and the exposed surfaces of the pillars113, and the conductive materials213-293extending in the first direction.

Drains320may be provided on the pillars113, respectively. Exemplarily, the drains320may be silicon materials that are doped in a second type. For example, the drains320may be silicon materials that are n-type. It may be assumed for purposes of explanation that the drains320include n-type silicon. However, the drains320are not limited thereto. The width of each of the drains320may be greater than that of a corresponding pillar113. For example, each drain320may be provided in a pad shape on the upper surface of a corresponding pillar113.

Conductive materials331-333extending in the third direction may be provided on the drains320. The conductive materials331-333may be sequentially disposed in the first direction. The conductive materials331-333may be connected to the drains320of corresponding regions, respectively. The drains320and the conductive material extending in the third direction may be connected through contact plugs (not shown). The conductive materials331-333extending in the third direction may be, for example, metal materials. The conductive materials331-333may be, for example, polysilicon.

InFIGS. 2 and 3, each pillar113may form a string together with adjacent ones among conductive lines211-291,212-292and213-293extending in the first direction. For example, each pillar113may form a string ST together with adjacent ones among conductive lines211-291,212-292and213-293extending in the first direction. The string ST may include a plurality of transistor structures ST.

FIG. 4is a cross-sectional diagram of a transistor structure ST illustrated inFIG. 3. Referring toFIGS. 2-4, an insulation layer116may include the first to third sub-insulation layers117-119. P-type silicon114of the pillar113may act as a body. The first sub-insulation layer117adjacent to a pillar113may act as a tunnel insulation film. For example, the first sub-insulation layer117adjacent to a pillar113may include a thermal oxide layer. The second sub-insulation layer118may serve as a charge storage layer. For example, the second sub-insulation layer118may serve as a charge trap layer. For example, the second sub-insulation layer118may include a nitride layer and/or metal oxide layer (e.g., an aluminum oxide layer and/or a hafnium oxide layer).

The third sub-insulating layer119adjacent to the conductive material233may serve as a blocking insulation layer. The third sub-insulation layer119adjacent to the conductive material233extending in the first direction may be formed as a single layer or a multi-layer. The third sub-insulation layer119may be a high dielectric layer (e.g., an aluminum oxide layer and/or a hafnium oxide layer) having a higher dielectric constant than the first and second sub-insulation layers117and118. The conductive material233may serve as a gate (or a control gate). The gate (or, control gate)233, the blocking insulation layer119, the charge storage layer118, the tunneling insulation layer117, and the body114may form a transistor (or, a memory cell transistor structure). The first to third sub-insulation layers117-119may form oxide-nitride-oxide (ONO). The p-type silicon114of the pillar113may be called the second direction body.

A memory block BLKi may include a plurality of pillars113. The memory block BLKi may include a plurality of strings ST. The memory block BLKi may include a plurality of strings ST extending in the second direction (or a direction vertical to the substrate). Each string ST may include a plurality of transistor structures ST disposed in the second direction. At least one of the transistor structures ST of each string ST may serve as a string selection transistor SST. At least one of the transistor structures ST of each string ST may serve as a ground selection transistor GST.

Gates (or control gates) may correspond to the conductive materials211-291,212-292and213-293extending in the first direction. The gates (or the control gates) may extend in the first direction and form word lines and at least two selection lines (e.g., at least one string selection line SSL and at least one ground selection line GSL). The conductive materials331-333extending in the third direction may be connected to one end of the strings ST, respectively. The conductive materials331-333extending in the third direction may serve as bit lines BL. In one memory block BLKi, a plurality of strings may be connected to one bit line BL.

Second-type doping regions311-314extending in the first direction may be provided to other ends of the strings ST, respectively. The second-type doping regions311-314extending in the first direction may serve as the common source line CSL. To sum up the above-described, the memory block BLKi may include a plurality of strings extending in a direction (e.g., the second direction) vertical to the substrate111, and may serve as a flash memory block (e.g., a charge trapping type) where the plurality of strings ST may be connected to one bit line BL.

FIGS. 2-4are described assuming the conductive lines211-291,212-292and213-293are formed in nine layers. However, the layer number of the conductive lines211-291,212-292and213-293extending in the first direction are not limited thereto. For example, the conductive lines may be formed in eight layers, sixteen layers, or more layers. One string may include 8, 16, or more transistors.FIGS. 2-4are described under the assumption that three strings ST may be connected to one bit line BL. The inventive concept may not be limited thereto. The memory block BLKi may be formed such that m strings ST are connected to one bit line BL. The number of conductive materials211-291,212-292and213-293extending in the first direction and the number of common source lines311-314may be determined in proportion to the number of strings ST connected to one bit line BL.

FIGS. 2-4are described under the assumption that three strings ST may be connected to one conductive material extending in the first direction. It is well understood that example embodiments of the inventive concepts are not limited thereto. For example, n strings ST may be connected to one conductive material. The number of bit lines may be determined in proportion to the number of strings ST that may be connected to one conductive material extending in the first direction.

FIG. 5is an equivalent circuit diagram of a memory block illustrated inFIGS. 2-4. Referring toFIGS. 2-5, strings ST11, ST21and ST31may be between the first bit line BL0and a common source line CSL. The first bit line BL0may correspond to a conductive material331extending in the third direction. Strings ST12, ST22and ST32may be between the second bit line BL1and the common source line CSL. The second bit line BL1may correspond to a conductive material332extending in the third direction. Strings ST13, ST23and ST33may be between the third bit line BL2and the common source line CSL. The third bit line BL2may correspond to a conductive material333extending in the third direction.

A string selection transistor SST of each string ST may be connected to a corresponding bit line BL. A ground selection transistor GST of each string ST may be connected to the common source line CSL. In each string ST, memory cells MC may be between the string selection transistor SST and the ground selection transistor GST. Strings ST may be defined by the row and by the column. The strings ST connected to one bit line in common may form one column. For example, the strings ST11-ST31connected to the first bit line BL0may correspond to the first column. The strings ST12-ST32connected to the second bit line BL1may correspond to the second column. The strings ST13-ST33connected to the third bit line BL2may correspond to the third column.

The strings connected to one string selection line SSL may form one row. For example, the strings ST11-ST13connected to the first string selection line SSL0may form the first row. The strings ST21-ST23connected to the second string selection line SSL1may form the second row. The strings ST31-ST33connected to the third string selection line SSL2may form the third row. In each string ST, a height may be defined. In each string ST, a memory cell MC1adjacent to the ground selection transistor GST may be defined to have a height of 1. In each string ST, a height of a memory cell may increase as it becomes close to the string selection transistor SST. In each string ST, a memory cell MC7(not shown) adjacent to the string selection transistor SST may be defined to have a height of 7.

Strings ST in the same row may share a string selection line SSL. Strings ST in different rows may be connected with different sting selection lines SSL0, SSL1and SSL2. In each string in the same row, memory cells with the same height may share a word line WL. Word lines WL connected with memory cells MC of strings ST placed in different rows and having the same height may be connected in common. According to at least one example embodiment, word lines WL may be connected in common at a layer where conductive materials211-291,212-292, and213-293extending in the first direction are provided. For example, the conductive materials211-291,212-292, and213-293extending in the first direction may be connected at an upper layer via contacts. The conductive materials211-291,212-292, and213-293extending in the first direction may be connected in common at the upper layer.

Strings ST in the same row may share a ground selection line GSL. Strings ST in different rows may share a ground selection line GSL. For example, strings ST11-ST13, ST21-ST23and ST31ST33may be connected in common with the ground selection line GSL.

The common source line CSL may be connected to strings ST in common. For example, the first to fourth doping regions311-314may be connected at an active region on the substrate111. The first to fourth doping regions311to314may be connected to an upper layer via contacts so as to be connected in common at the upper layer.

As illustrated inFIG. 5, the word lines WL with the same height may be connected in common. When a specific word line WL is selected, all strings ST connected to the specific word line WL may be selected. The strings ST of different rows may be connected to different string selection lines SSL. By selecting the string selection lines SSL0-SSL2, strings ST in an unselected row among strings ST connected to the same word line WL may be separated from bit lines BL0, BL1, and BL2. A row of strings ST may be selected by selecting the string selection lines SSL0-SSL2. Strings in the selected row may be selected by the column by selecting the bit lines BL0-BL2.

According to at least one example embodiment, at programming and reading, one of string selection lines SSL0-SSL2may be selected. Programming and reading may be carried out by the row of strings ST11-ST13, ST21-ST23and ST31-ST33. According to at least one example embodiment, at programming and reading, a selection voltage may be applied to a selected word line in a selected row and a non-selection voltage may be applied to unselected word lines. For example, the selection voltage may be a program voltage Vpgm or a read voltage Vr. For example, the non-selection voltage may be a pass voltage Vpass or a non-selection read voltage Vread. Programming and reading may be performed by the word line of a selected row of strings ST11-ST13, ST21-ST23and ST31-ST33.

According to at least one example embodiment, a first voltage may be applied to a bit line corresponding to a memory cell to be programmed. A second voltage may be applied to a bit line corresponding to a program inhibited memory cell. A bit line corresponding to a memory cell to be programmed may be called a selected bit line, and a bit line corresponding to a program inhibited memory cell may be called an unselected bit line. It is assumed for purposes of explanation that strings ST11-ST13, ST21-ST23and ST31-ST33in the first row may be selected at programming. It is assumed that the second bit line BL1may be selected and the first and third bit lines BL0and BL2may be unselected.

FIG. 6is a schematic diagram showing a bias condition of a program operation according to example embodiments of the inventive concepts. Referring toFIG. 6, a bias condition of a program operation on a memory cell MC connected with a word line WL4and a bit line BL0may be as follows. A string ST21including a memory cell MC being programmed may be referred to as a program string, and strings ST11and ST22not including a memory cell being programmed may be referred to as inhibit strings. A ground voltage GND may be applied to string selection lines SSL0and SSL1and a ground selection line GSL. This may float the inhibit strings ST11and ST22. Channels CH11and CH22of the inhibit strings ST11and ST22may have an initial voltage of a ground voltage GND.

At, for example, the same time, a bit line program voltage (e.g., a ground voltage: GND) may be applied to a selected bit line BL0, and a bit line program inhibit voltage (e.g., a power supply voltage: VDD) may be applied to an unselected bit line BL1. The bit lines BL0and BL1may be set up. Afterward, a power supply voltage VDD may be applied to a selected string selection line SSL1, a pass voltage Vpass may be applied to unselected word lines WL0, WL1, WL2, WL3, WL5, and WL6and a program voltage Vpgm may be applied to a selected word line WL4. According to this bias condition, channels of the inhibit strings ST11and ST22may be boosted, and the memory cell MC of the program string ST21may be programmed. According to at least one example embodiment, the program voltage Vpgm may be applied to the selected word line WL4after the pass voltage Vpass may be applied to the selected word line WL4during a period of time.

A program voltage applying method according to at least one example embodiment of the inventive concepts may include boosting channels after channels CH11and CH22of the inhibit strings ST11and ST22may be reset to a ground voltage GND. With the program voltage applying method, a bit line setup operation may be performed together with the channel boosting.

FIG. 7is a timing diagram of a program operation according to example embodiments of the inventive concepts. Referring toFIGS. 6 and 7, during the first word line setup period WL Setup1, a pass voltage may be applied to all word lines, that is, selected and unselected word lines. During the second word line setup period WL Setup2, a program voltage Vpgm may be applied to the selected word line. At this time, the pass voltage Vpass may be continuously applied to the unselected word lines.

During the first bit line setup period BL Setup1, a ground voltage GND may be applied to selected and unselected string selection lines. During the second bit line setup period BL Setup2, a power supply voltage VDD may be applied to the selected string selection line, and the unselected string selection line may be continuously supplied with a ground voltage GND. During the first bit line setup period, all strings may be floated, and simultaneously a pass voltage Vpass may be applied to all word lines. At this time, channels of all strings may be boosted. For example, channels of all strings may increase up to a boost voltage Vbst from a ground voltage by the channel boosting.

At the first bit line setup period, a ground voltage GND may be applied to the selected bit line, and a power supply voltage VDD may be applied to the unselected bit line. During the second bit line setup period, the selected bit line may be electrically connected with a channel of a program string, which may be connected with the selected bit line, when a power supply voltage VDD is applied to the selected string selection line. This may make charges corresponding to the boost voltage Vbst be shared by the selected bit line and the program string. Afterwards, a ground voltage GND may be applied to the selected bit line for programming. The second bit line setup operation may be completed. A program execution operation may be made within the second word line setup period.

The program method according to example embodiments of the inventive concepts may include boosting channels of all strings at the first bit line setup period, lowering a boost voltage Vbst of a program string to a ground voltage via charge sharing at the second bit line setup period, and performing a program execution operation.

InFIGS. 6 and 7, all strings may have an initial channel voltage of a ground voltage GND before a channel boosting operation is performed. Example embodiments of the inventive concepts are not limited to this disclosure. All strings may be set to have a channel voltage (e.g., a pre-charge voltage) higher in level than a ground voltage GND before a channel boosting operation may be performed.

FIG. 8is a schematic diagram showing a bias condition of a program operation according to other to example embodiments of the inventive concepts. Referring toFIG. 8, a bias condition of a program operation on a memory cell MC connected with a word line WL4and a bit line BL0may be as follows. A power supply voltage VDD may be applied to all string selection lines SSL0and SSL1, and a ground voltage GND may be applied to a ground selection line GSL. At the same time, a pre-charge voltage (e.g., a power supply voltage: VDD) may be applied to all bit lines BL0and BL1. Under this bias condition, channels of all strings ST11, ST12and ST22may be set to a voltage of (VDD-Vth) (Vth being a threshold voltage of a string selection transistor). Afterwards, a ground voltage GND may be applied to an unselected string selection line SSL0for channel boosting.

A ground voltage GND may be applied to the selected bit line BL0to set a channel voltage of a program string ST21to a ground voltage. An inhibit string ST11may be floated by electrically isolating it from the selected bit line BL0and a common source line CSL. Floating of an inhibit string ST22may be accomplished by electrically isolating it from the common source line CSL with a string selection transistor connected with SSL1being shut off. The inhibit string ST22may be shut off from the bit line BL1because a channel CH22of the inhibit string ST22is set to a voltage of (VDD-Vth) and a power supply voltage VDD may be applied to the selected string selection line SSL1. Because a string selection transistor connected with SSL1and BL1may be shut off, the inhibit string ST22may be floated.

Afterwards, channels of the floated inhibit strings ST11and ST22may be boosted by applying a pass voltage Vpass to unselected word lines WL0-WL3, WL5and WL6and a program voltage Vpgm to a selected word line WL4. At the same time, the memory cell MC in the program string ST21may be programmed. According to at least one example embodiment, a program voltage Vpgm may be applied to a selected word line after a pass voltage Vpass may be applied thereto during a period of time. A program voltage applying method according to example embodiments of the inventive concepts may include boosting channels after channels CH11and CH22of the inhibit strings ST11and ST22are set to a pre-charge voltage (VDD-Vth). With the program voltage applying method, a bit line setup operation may be performed together with the channel boosting.

FIG. 9is a timing diagram of a program operation according to other example embodiments of the inventive concepts. Referring toFIGS. 8 and 9, during the first word line setup period WL Setup1, a pass voltage may be applied to all word lines, that is, selected and unselected word lines. During the second word line setup period WL Setup2, a program voltage Vpgm may be applied to the selected word line. At this time, the pass voltage Vpass may be continuously applied to the unselected word lines. At the first bit line setup period BL setup1, a power supply voltage VDD may be applied to selected and unselected string selection lines and to selected and unselected bit lines. With this bias condition, channels of all strings may be pre-charged by a voltage of (VDD-Vth). At this time, strings connected with the selected string selection line may be shut off from bit lines. The strings connected with the selected string selection line may be floated.

During the second bit line setup period BL Setup2, the selected string selection line may be maintained with a power supply voltage VDD, and a ground voltage may be applied to the unselected string selection line. According to at least one example embodiment, a ground voltage GND may be applied to the unselected string selection line prior to the second bit line setup period. An inhibit string may be electrically blocked from a bit line. The inhibit string may be floated. During the second bit line setup period, a ground voltage GND may be applied to the selected bit line, and the unselected bit line may be maintained with the power supply voltage VDD. A ground voltage GND may be applied to the selected bit line in synchronization with setting of the unselected string selection line to a ground voltage GND.

As illustrated inFIG. 9, channels of floated inhibit strings may be boosted by applying a pass voltage Vpass to all word lines at the second bit line setup period. Afterwards, a program execution operation may be performed within the second word line setup period. A program method according to at least one example embodiment of the inventive concepts may include setting channels of all strings to a pre-charge voltage during the first bit line setup period and boosting channels during the second bit line setup period. It may be possible to set initial channel voltages of inhibit strings to the same voltage level.

FIG. 10is a flowchart of channel boosting methods of non-volatile memory devices according to example embodiments of the inventive concepts. Referring toFIGS. 1-10, in operation S110, an initial channel voltage may be applied to channels of all strings within a selected memory block. The initial channel voltage may be a ground voltage or a pre-charge voltage. The initial channel voltage may be applied to channels of strings via corresponding bit lines. In operation S120, inhibit strings among all strings may be floated. According to at least one example embodiment, program strings may be floated. In operation S130, channels of the floated inhibit strings may be boosted by applying a pass voltage to unselected word lines. Channels of all inhibit strings may be boosted from an initial channel voltage. Channels of all inhibit strings may be boosted under the same initial condition.

FIG. 11is a flowchart of program methods of non-volatile memory devices according to example embodiments of the inventive concepts. Referring toFIGS. 1-11, in operation S210, data to be programmed at a program operation may be loaded onto a read and write circuit130via a data input/output circuit140. A voltage generator (not shown) may generate bias voltages (e.g., a program voltage, a pass voltage, a high voltage, a well voltage and/or a verification read voltage) needed for the program operation according to the control of control logic150. In operation5220, the control logic150may set a value (i) indicating a program loop such that the first program loop is executed.

In operation S330, bit lines may be set up according to the loaded data in the read and write circuit130together with channel boosting. According to at least one example embodiment, when the channel boosting may be executed, initial channel voltages of all inhibit strings may be a ground voltage or a pre-charge voltage (VDD-Vth). In operation S240, memory cells may be programmed by applying a pass voltage to unselected word lines and a program voltage to a selected word line. The program voltage may increase stepwise according to iteration of program loops. A pass voltage may be applied to a selected word line for a predetermined time before a program voltage is applied thereto. Afterwards, a program recovery operation may be performed such that bias voltages of word lines, string selection lines, and bit lines may be discharged.

In operation S250, the control logic150may perform a verification operation to judge whether a program operation is executed normally. If passed, the program operation may be ended. If failed, the method may proceed to operation S260, in which the control logic150judges whether a loop number (i) may be a maximum value. If so, the program operation may be processed as failed. If not, the method may proceed to operation S270, in which the program number (i) may increase by 1. As the loop number (i) may increase, the program voltage may increase by an increment. According to example embodiments of the inventive concepts, a bit line setup operation may be performed together with channel boosting.

FIG. 12is an equivalent circuit diagram of a memory block illustrated inFIGS. 1-4according to example embodiments of the inventive concepts. As compared with a memory block BLKi inFIG. 5, in a memory block BLKi_1each string ST may include two ground selection transistors GST0and GST1placed between memory cells MC0-MC5and a common source line CSL. Ground selection lines GSL0or GSL1corresponding to ground selection transistors GST0or GST1at the same height may be connected in common. The ground selection line GSL0and GSL1connected with the ground selection transistors GST0and GST1within the same string ST may be connected in common.

FIG. 13is an equivalent circuit diagram of a memory block illustrated inFIGS. 1-4according to still other example embodiments of the inventive concepts. As compared withFIG. 2, in a memory block BLK_2each string ST may include two string selection transistors SST0and SST1placed between memory cells MC0-MC4and a bit line GL. String selection lines SSL10-SSL23may be connected to respective string selection transistors SST0and SST1.FIG. 14is an equivalent circuit diagram of a memory block illustrated inFIGS. 1-4according to yet other example embodiments of the inventive concepts. As compared withFIG. 13, in a memory block BLK_3, string selection lines connected with string selection transistors SST0and SST1in each string ST may be connected in common.

FIG. 15is an equivalent circuit diagram of a memory block illustrated inFIGS. 1-4according to further example embodiments of the inventive concepts. As compared withFIG. 5, in a memory block BLKi_4each string ST may include a dummy memory cell DMC placed between a string selection transistor SST and memory cells MC0-MC5. The dummy memory cells DMC may be connected in common with a dummy word line DWL. The dummy word line DWL may be provided between string selection lines SSL0-SSL2and word lines WL0-WL5.

FIG. 16is an equivalent circuit diagram of a memory block illustrated inFIGS. 1-4according to still further example embodiments of the inventive concepts. As compared withFIG. 5, in a memory block BLKi_5, each string ST may include a dummy memory cell DMC placed between a ground selection transistor GST and memory cells MC0-MC5. The dummy memory cells DMC may be connected in common with a dummy word line DWL. The dummy word line DWL may be provided between a ground selection line GSL and word lines WL0-WL5.FIG. 17is an equivalent circuit diagram of a memory block illustrated inFIGS. 1-4according to yet still other example embodiments of the inventive concepts. As compared withFIG. 5, in a memory block BLKi_6, each string ST may include a dummy memory cell DMC placed between a string selection transistor SST and memory cells MC0-MC4. The dummy memory cells DMC may be connected in common with the first dummy word line DWL1. The first dummy word line DWL1may be provided between string selection lines SSL0-SSL2and word lines WL0-WL4. Each string ST may include a dummy memory cell DMC placed between a ground selection transistor GST and memory cells MC0-MC4. The dummy memory cells DMC may be connected in common with the second dummy word line DWL2. The second dummy word line DWL2may be provided between a ground selection line GSL and word lines WL0-WL4.

FIG. 18is a perspective view of one of memory blocks illustrated inFIG. 1according to other example embodiments of the inventive concepts. As compared withFIG. 2, a memory block BLKi′ may include pillars113′ which may be square shaped. Insulation materials120may be between pillars113′ disposed in the first direction. According to at least one example embodiment, the insulation materials120may extend in the second direction to be connected with a substrate111a. The insulation materials120may extend in the first direction at the remaining area other than an area where the pillars113′ may be provided. Conductive materials211-291,212-292, and213-293extending in the first direction described inFIG. 2may be divided into two portions211a-291a,211b-291b,212a-292a,212b-292b,213a-293a, and213b-293bby the insulation materials120, respectively. The separated portions211a-291a,211b-291b,212a-292a,212b-292b,213a-293aand213b-293bmay be isolated electrically.

At a region on the first and second doping regions311and312, each pillar113′ may form one string ST with an insulation film116and the portions211a-291aof the conductive material extending in the first direction, and may form another string ST with the insulation film116and the portions211b-291bof the conductive material extending in the first direction. At a region on the third and fourth doping regions313and314, each pillar113′ may form one string ST with the insulation film116and the portions213a-293aof the conductive material extending in the first direction, and may form another string ST with the insulation film116and the portions213b-293bof the conductive material extending in the first direction. Each pillar113′ may form two strings ST by electrically isolating, for example, conductive materials211a-291aand211b-291b, extending in the first direction, provided at both sides of each pillar113′ using the insulation film120.

FIG. 19is a perspective view of one of the memory blocks illustrated inFIG. 1according to still other example embodiments of the inventive concepts.FIG. 20is a cross-sectional view taken along line XX-XX′ of the memory block illustrated inFIG. 19. Referring toFIGS. 19 and 20, a memory block BLKj may be implemented the same or similar as described inFIGS. 2-18except that the second type doping region315may be provided under pillars113in a plate shape. An equivalent circuit of the memory block BLKj may be identical or similar to those described inFIGS. 15-18.

FIG. 21is a perspective view of one of the memory blocks illustrated inFIG. 1according to yet still other example embodiments of the inventive concepts.FIG. 22is a cross-sectional view taken along line XXII-XXII′ of the memory block illustrated inFIG. 21. Referring toFIGS. 21 and 22, a memory block BLKp may include a second doping region315provided on a substrate101in a plate shape. Conductive materials221′ to281′ may be formed in a plate shape. An insulation film116′ may be on a surface layer116′ of a pillar113′. An intermediate layer114′ of the pillar113′ may include, for example, p-type silicon. The intermediate layer114′ of the pillar113′ may act as a body114′ of the second direction. An inner layer115′ of the pillar113′ may include, for example, an insulation material.

FIG. 23is a perspective view of one of the memory blocks illustrated inFIG. 1according to still further example embodiments of the inventive concepts.FIG. 24is a cross-sectional view taken along line XXIV-XXIV′ of the memory block illustrated inFIG. 23. Referring toFIGS. 23 and 24, on a substrate111of a memory block BLKq, the first to fourth upper word lines UW1-UW4extending in the first direction may be sequentially provided along the second direction. First to fourth upper word lines UW1-UW4may be provided to be spaced apart along the second direction. First upper pillars UP1may be disposed sequentially along the first direction to penetrate the first to fourth upper word lines UW1-UW4.

On the substrate111, the first to fourth lower word lines DW1-DW4extending in the first direction may be provided sequentially in the second direction. The first to fourth lower word lines DW1-DW4may be provided to be spaced apart in the second direction. The first lower pillars DP1may be disposed sequentially in the first direction to penetrate the first to fourth lower word lines DW1-DW4in the second direction. The second lower pillars DP2may be disposed sequentially in the first direction to penetrate the first to fourth lower word lines DW1-DW4in the second direction. According to at least one example embodiment, the first lower pillars DP1and the second lower pillars DP2may be disposed in parallel along the second direction.

On a substrate111, the fifth to eight upper word lines UW5-UW8extending along the first direction may be sequentially provided along the second direction. The fifth to eight upper word lines UW5-UW8may be provided to be spaced apart along the second direction. The second upper pillars UP2may be disposed sequentially along the first direction to penetrate the fifth to eight upper word lines UW5-UW8. A common source line CSL extending in the first direction may be provided on the first and second lower pillars DP1and DP2. According to at least one example embodiment, the common source line CSL may be n-type silicon. According to at least one example embodiment, in the event that the common source line CSL is metal or a non-polar conductive material such as polysilicon, n-type sources may be provided between the common source line CSL and the first and second lower pillars DP1and DP2.

According to at least one example embodiment, the common source line CSL and the first and second lower pillars DP1and DP2may be connected via contact plugs (not shown), respectively. Drains320may be on the first and second upper pillars UP1and UP2, respectively. According to at least one example embodiment, the drains320may be, for example, n-type silicon. On the drains320, a plurality of bit lines BL1-BL3extending along the third direction may be provided sequentially in the first direction. According to at least one example embodiment, the bit lines BL1-BL3and the drains320may be connected via contact plugs (not shown).

Each of the first and second upper pillars UP1and UP2may include a surface layer116″ and an inner layer114″. Each of the first and second lower pillars DP1and DP2may include a surface layer116″ and an inner layer114″. The surface layers116″ of the first and second upper pillars UP1and UP2and the first and second lower pillars DP1and DP2may include, for example, a blocking insulation film, a charge storage film, and a tunneling insulation film, respectively.

The tunnel insulation film may include, for example, a thermal oxide film. The charge storage film may include a nitride layer and/or metal oxide layer (e.g., an aluminum oxide layer and/or a hafnium oxide layer). The blocking insulation film may be formed as a single layer or a multi-layer. The blocking insulation film may be a high dielectric layer (e.g., an aluminum oxide layer and/or a hafnium oxide layer) having a higher dielectric constant than the tunnel insulation film and charge storage film. The tunnel insulation, charge storage film and block insulation film may form oxide-nitride-oxide (ONO). The inner layers114″ of the first and second upper pillars UP1and UP2and the first and second lower pillars DP1and DP2may be, for example, p-type silicon, respectively. The inner layers114″ of the first and second upper pillars UP1and UP2and the first and second lower pillars DP1and DP2may act as a body.

The first upper pillars UP1may be connected with the first lower pillars DP1via the first pipeline contacts PC1, respectively. According to at least one example embodiment, surface layers116″ of the first upper pillars UP1may be connected with those of the first lower pillars DP1via the first pipeline contacts PC1, respectively. Surface layers of the first pipeline contacts PC1may be of the same material as the surface layers116″ of the pillars UP1and DP1. According to at least one example embodiment, inner layers114″ of the first upper pillars UP1may be connected with those of the first lower pillars DP1via inner layers of the first pipeline contacts PC1, respectively. The inner layers of the first pipeline contacts PC1may be of the same material as the inner layers114″ of the pillars UP1and DP1.

The first upper pillars UP1and the first to fourth upper word lines UW1-UW4may form the first upper strings, and the first lower pillars DP1and the first to fourth lower word lines DW1-DW4may form the first lower strings. The first upper strings may be connected with the first lower strings via the first pipeline contacts PC1, respectively. The drains320and the bit lines BL1-BL3may be connected with one ends of the first upper strings. A common source line CSL may be connected with one ends of the first lower strings. The first upper strings and the first lower strings may form a plurality of strings connected between the bit lines BL1-BL3and the common source line CSL.

Likewise, the second upper pillars UP2and the fifth to eight upper word lines UW5-UW8may form the second upper strings, and the second lower pillars DP2and the first to fourth lower word lines DW1-DW4may form the second lower strings. The second upper strings may be connected with the second lower strings via the second pipeline contacts PC2, respectively. The drains320and the bit lines BL1-BL3may be connected with one end of the second upper strings. The common source line CSL may be connected with one end of the second lower strings. The second upper strings and the second lower strings may be a plurality of strings connected between the bit lines BL1-BL3and the common source line CSL.

An equivalent circuit of a memory block BLKq may be identical to that inFIG. 2except that one string includes eight transistors and two strings are connected with each of the first to third bit lines BL1-BL3. Word lines, bit lines and strings in the memory block BLKq may be not limited in number to this disclosure. According to at least one example embodiment, the first and second pipeline contact gates (not shown) may be provided to form a channel at bodies114″ within the first and second pipeline contacts PC1and PC2. The first and second pipeline contact gates (not shown) may be provided on the first and second pipeline contacts PC1and PC2. According to at least one example embodiment, there may be described an example that lower word lines DW1-DW4may be shared at adjacent lower pillars DP1-DP2. If upper pillars adjacent to the upper pillars UP1or UP2may be added, the adjacent upper pillars may be formed to share upper word lines UW1-UW4or UW5-UW8.

FIG. 25is a block diagram illustrating memory systems according to example embodiments of the inventive concepts. Referring toFIG. 25, a memory system1000may include a nonvolatile memory device1100and a memory controller1200. The nonvolatile memory device1100may be configured to perform a channel boosting operation after inhibit strings are set to the same initial channel voltage at programming. The nonvolatile memory device1100may be implemented in the same manner as one of the nonvolatile memory devices100ofFIG. 1.

The memory controller1200may control the nonvolatile memory device1100according to a request of an external device (e.g., a host). For example, the memory controller1200may control read/write/erase operations of the nonvolatile memory device1100. The memory controller1200may provide an interface between the nonvolatile memory device1100and the host. The memory controller1200may drive a firmware for controlling the nonvolatile memory device1100. The memory controller1200may include at least one Central Processing Unit (CPU)1210, a buffer1220, an Error Correction Circuit (ECC)1230, a Read-Only Memory (ROM)1240, a host interface1250, and a memory interface1260.

The CPU1210may control overall operations of the memory controller1200. The buffer1220may be used as a working memory of the CPU1210. Upon write request of the host, data received from the host may be temporarily stored in the buffer1220. Upon read request of the host, data read from the nonvolatile memory device1100may be temporarily stored in the buffer1220. Upon the write request, the ECC1230may use an error correction code to decode data stored in the buffer1220. The decoded data and the error correction code value may be stored in the nonvolatile memory device1100. Upon the read request, the ECC1230may use an error correction code value to restore data read from the nonvolatile memory device1100. The error correction code value may be included in the read data. The ROM1240may store data used to drive the memory controller1200.

The host interface1250may include a protocol for data exchange between the host and the memory controller1200. For example, the memory controller1200may be configured to communicate with an external device (host) via one of various interface protocols, for example, Universal Serial Bus (USB) protocols, Multimedia Card (MMC) protocols, Peripheral Component Interconnection (PCI) protocols, PCI-Express (PCI-E) protocols, Advanced Technology Attachment (ATA) protocols, serial-ATA protocols, parallel-ATA protocols, Small Computer Small Interface (SCSI) protocols, Enhanced Small Disk Interface (ESDI) protocols, and Integrated Drive Electronics (IDE) protocols.

The memory interface1260may interface between the nonvolatile memory device1100and the memory controller1200. The memory system1000according to example embodiments of the inventive concepts may determine (e.g., easily) a pass voltage by setting inhibit strings to the same initial channel voltage at programming as described above with respect toFIGS. 1-24. The memory system1000may reduce program disturbance as compared with a typical memory system which does not provide the same initial channel voltage.

FIG. 26is a block diagram illustrating memory cards according to example embodiments of the inventive concepts. Referring toFIG. 26, a memory card2000may include a flash memory2100, a buffer memory2200and a memory controller2300for controlling the flash memory2100and the buffer memory2200. The flash memory device2100may be configured to perform a channel boosting operation after inhibit strings may be set to the same initial channel voltage at programming as described above with respect toFIGS. 1-24. The flash memory2100may be implemented in the same or similar manner to one of the nonvolatile memory devices100ofFIG. 1.

The buffer memory2200may be used to temporarily store data generated during the operation of the memory card2000. The buffer memory2200may be implemented using, for example, a DRAM and/or an SRAM. The memory controller2300may be connected between a host and the flash memory2100. The memory controller2300may be configured to access the flash memory2100in response to a request from the host. The memory controller2300may include at least one microprocessor2310, a host interface2320, and a flash interface2330.

The micro processor2310may be configured to drive a firmware for controlling the flash memory2100. The host interface2320may interface with the host via a card (e.g., MMC) protocol for data exchanges between the host and the memory interface2330. The memory card2000may be applicable to Multimedia Cards (MMCs), Security Digitals (SDs), miniSDs, memory sticks, smartmedia, and/or transflash cards. The memory card2000according to example embodiments of the inventive concepts may be suitable for optimizing and/or improving a pass voltage because channels of strings are boosted from the same initial channel voltage. The optimizing and/or improving of the pass voltage may enable program disturbance reduction, resulting in improvement of data reliability. The memory card2000according to example embodiments of the inventive concepts may store data stably and quickly by performing a bit line setup operation together with channel boosting.

FIG. 27is a block diagram illustrating moviNANDs according to example embodiments of the inventive concepts. Referring toFIG. 27, a moviNAND device3000may include a NAND flash memory device3100and a controller3200. The NAND flash memory device3100may be configured using a stack of unitary NAND flash memories in a package (e.g., Fine-pitch Ball Grid Array (FBGA)). The unitary NAND flash memory device may be configured to perform a channel boosting operation after inhibit strings are set to the same initial channel voltage at programming as described above with respect toFIGS. 1-24. Each of the unitary NAND flash memories may be implemented in the same manner as one of the nonvolatile memory devices100ofFIG. 1.

The controller34may include at least one controller core3210, a host interface3220, and a NAND interface3230. The controller core3210may control overall operations of the moviNAND device3000. The host interface3220may be configured to interface between the controller34and an MMC of a host. The NAND interface3230may be configured to interface between the NAND flash memory device3100and the controller3200. If a unitary NAND flash memory device of the NAND flash memory device3100may be formed of a non-volatile memory device inFIG. 21, the controller3200may be identical to that inFIG. 21.

The moviNAND device30may receive power supply voltages Vcc and Vccq from the host. The power supply voltage Vcc (e.g., about 3.3V) may be supplied to the NAND flash memory device3100and the NAND interface3230, while the power supply voltage Vccq (e.g., about 1.8V/3.3V) may be supplied to the controller3200. The moviNAND device3000may reduce a program time by performing a bit line setup operation together with channel boosting. The moviNAND device3000may be advantageous to store a large amount of data. The moviNAND3000may include a NAND flash memory device3100configured with three mats in a sub-30 nm process, thereby considerably expanding data storage capacity within a limited chip size. Example embodiments of the inventive concepts may be applicable to a solid state drive (SSD).

FIG. 28is a block diagram illustrating SSDs according to example embodiments of the inventive concepts. Referring toFIG. 28, an SSD4000may include a plurality of flash memory devices4100and an SSD controller4200. The flash memory devices4100may be configured to perform a channel boosting operation after inhibit strings are set to the same initial channel voltage at programming as described above with respect toFIGS. 1-24. Each of the flash memory devices4100may be implemented in the same manner as one of the nonvolatile memory devices100ofFIG. 1.

The SSD controller4200may control the plurality of flash memory devices4100. The SSD controller4200may include at least one CPU4210, a host interface4220, a cache buffer4230, and a flash interface4240. Under the control of the CPU4210, the host interface4220may exchange data with a host through ATA protocol. The host interface4220may be at least one of a Serial Advanced Technology Attachment (SATA) interface, a Parallel Advanced Technology Attachment (PATA) interface, and an External SATA (ESATA) interface.

Data to be received or transmitted from or to the host through the host interface4220may be delivered to the cache buffer4230without passing through a CPU bus, under the control of the CPU4210. The cache buffer4230may temporarily store data transferred between external devices and the flash memory devices4100. The cache buffer4230may also be used to store programs to be executed by the CPU4210. The cache buffer4230may be regarded as a kind of buffer memory, and may be implemented using an SRAM.

The flash interface4240may be configured to interface between the SSD controller4200and the flash memory devices4100that are used as storage devices. The flash interface4240may be configured to support NAND flash memories, One-NAND flash memories, multi-level flash memories, and/or single-level flash memories. The SSD4000may optimize and/or improve a pass voltage for reducing the program disturbance by performing a channel boosting operation so that inhibit strings have the same channel voltage. According to the SSD4000, it may be possible to improve data reliability.

FIG. 29is a block diagram of computing systems according to example embodiments of the inventive concepts. Referring toFIG. 29, a computing system5000may include at least one CPU5100, a ROM5200, a RAM5300, an input/output (I/O) device5400, and an SSD5500. The CPU5100may be connected to a system bus. The ROM5200may store data used to drive the computing system5000. The data may include a start command sequence and/or a basic I/O system (BIOS) sequence. The RAM5300may temporarily store data generated during the execution of the CPU5100. The I/O device5400may be connected to the system bus through an I/O device interface. Examples of the I/O device5400may include keyboards, pointing devices (e.g., mouse), monitors, and/or modems. The SSD5500may be a readable storage device and may be implemented in the same manner as the SSD4000ofFIG. 28.

FIG. 30is a block diagram of electronic devices according to example embodiments of the inventive concepts. Referring toFIG. 30, an electronic device6000may include at least one processor6100, a ROM6200, a RAM6300, a host interface (I/F)6400, and an SSD6500. The processor6100may access the RAM6300to execute firmware codes and/or other necessary codes. The processor6100may access the ROM6200to execute various command sequences such as a start command sequence and a basic I/O system (BIOS) sequence. The host interface6400may be configured to interface between the electronic device6000and the SSD6500. The SSD6500may be detachable from the electronic device6000. The SSD6500may be implemented in the same manner as the SSD4000ofFIG. 28. Examples of the electronic device6000may include cellular phones, personal digital assistants (PDAs), digital cameras, camcorders, portable audio players (e.g., MP3), and portable media players (PMPs).

FIG. 31is a block diagram of server systems according to example embodiments of the inventive concepts. Referring toFIG. 31, a server system7000may include a server7100and an SSD7200that stores data used to drive the server7100. The SSD7200may be configured in the same manner as the SSD4000ofFIG. 28. The server7100may include an application communication module7110, a data processing module7120, an upgrade module7130, a scheduling center7140, a local resource module7150, and a repair information module7160.

The application communication module7110may be configured to communicate with a computing system connected to a network and the server7100, or to allow the server7100to communicate with the SSD7200. The application communication module7110may transmit data or information, provided through a user interface, to the data processing module7120. The data processing module7120may be linked to the local resource module7150. The local resource module7150may provide a list of repair shops/dealers/technical information to a user on the basis of information or data inputted to the server7100.

The upgrade module7130may interface with the data processing module7120. Based on information or data received from the SSD7200, the upgrade module7130may perform upgrades of a firmware, a reset code, a diagnosis system, and/or other information on electronic appliances. The scheduling center7140may provide real-time options to the user based on the information or data inputted to the server7100. The repair information module7160may interface with the data processing module7120. The repair information module7160may be used to provide repair-related information (e.g., audio, video and/or document files) to the user. The data processing module7120may package information related to the information received from the SSD7200. The packaged information may be transmitted to the SSD7200and/or may be displayed to the user.

The memory systems and/or the storage devices according to example embodiments of the inventive concepts may be mounted in various types of packages. Examples of the packages of the memory system and/or the storage device according to example embodiments of the inventive concepts may include Package on Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDJP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), and/or Wafer-level Processed Stack Package (WSP).

Channels of strings may be set up by the same initial channel voltage at programming. This may make it possible to easily determine an optimum and/or improved pass voltage. It may be possible to reduce a program time.