Semiconductor package device and method of manufacturing the same

A semiconductor package device includes a substrate, a die, a package body, a shielding layer, a solder mask layer, an insulating film and an interconnection element. The die is disposed on a top surface of the substrate. The package body is disposed on the top surface of the substrate to cover the die. The shielding layer is disposed on the package body and is electrically connected to a grounding element of the substrate. The solder mask layer is disposed on a bottom surface of the substrate. The insulating film is disposed on the solder mask layer. The interconnection element is disposed on the bottom surface of the substrate. A first portion of the interconnection element is covered by the insulating film, and a second portion of the interconnection element is exposed from the insulating film.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor package device and a method of manufacturing the same, and more particularly to a semiconductor package device with a shielding layer and a manufacturing method thereof.

2. Description of the Related Art

Semiconductor devices have become progressively more complex, driven at least in part by the demand for enhanced processing speeds and smaller sizes. Enhanced processing speeds tend to involve higher clock speeds, which can involve more frequent transitions between signal levels, which, in turn, can lead to a higher level of electromagnetic emissions at higher frequencies or shorter wavelengths. Electromagnetic emissions can radiate from a source semiconductor device, and can be incident upon neighboring semiconductor devices. If the level of electromagnetic emissions at a neighboring semiconductor device is sufficiently high, these emissions can adversely affect the operation of the neighboring semiconductor device. This phenomenon is sometimes referred to as electromagnetic interference (EMI). Smaller sized semiconductor devices can exacerbate EMI by providing a higher density of semiconductor devices within an overall electronic system, and, thus, a higher level of undesired electromagnetic emissions at neighboring semiconductor devices.

One way to reduce EMI is to shield a set of semiconductor devices within a semiconductor package device. In particular, shielding can be accomplished by including an electrically conductive casing or housing that is electrically grounded and is secured to an exterior of the package. When electromagnetic emissions from an interior of the package strike an inner surface of the casing, at least a portion of these emissions can be electrically shorted, thereby reducing the level of emissions that can pass through the casing and adversely affect neighboring semiconductor devices. Similarly, when electromagnetic emissions from a neighboring semiconductor device strike an outer surface of the casing, a similar electrical shorting can occur to reduce EMI of semiconductor devices within the package.

SUMMARY

In accordance with some embodiments of the present disclosure, a semiconductor package device comprises a substrate, a die, a package body, a shielding layer, a solder mask layer, an insulating film and an interconnection element. The substrate comprises a grounding element, a top surface, a bottom surface opposite to the top surface, and a lateral surface between the top surface and the bottom surface. The die is disposed on the top surface of the substrate. The package body is disposed on the top surface of the substrate to cover the die. The shielding layer is disposed on the package body and is electrically connected to the grounding element of the substrate. The solder mask layer is disposed on the bottom surface of the substrate. The insulating film is disposed on the solder mask layer. The interconnection element is disposed on the bottom surface of the substrate. A first portion of the interconnection element is covered by the insulating film, and a second portion of the interconnection element is exposed from the insulating film.

In accordance with some embodiments of the present disclosure, a method of manufacturing a semiconductor package device comprises: providing a substrate comprising a grounding element; disposing a die on a top surface of the substrate; forming a package body on the top surface of the substrate to cover the die; forming an interconnection element on a bottom surface of the substrate; forming an insulating film on the bottom surface of the substrate and the interconnection element, wherein the insulating film covers the interconnection element and is conformal to the interconnection element; forming a shielding layer on an external surface of the package body and a lateral surface of the substrate; and removing at least a portion of the insulating film. The shielding layer is connected to the grounding element.

In accordance with some embodiments of the present disclosure, a method of manufacturing a semiconductor package device comprises: providing a substrate comprising a grounding element; disposing a die on a top surface of the substrate; forming a package body on the top surface of the substrate to cover the die; forming an interconnection element on a bottom surface of the substrate; disposing a first insulating film on the bottom surface of the substrate, wherein the first insulating film covers a first portion of the interconnection element and exposes a second portion of the interconnection element; forming a second insulating film on the first insulating film and the second portion of the interconnection element, wherein the second insulating film is conformal to the interconnection element; forming a shielding layer on an external surface of the package body and a lateral surface of the substrate, wherein the shielding layer is connected to the grounding element; and removing the second insulating film.

DETAILED DESCRIPTION

FIG. 1illustrates a cross-sectional view of a semiconductor package device1in accordance with some embodiments of the present disclosure. The semiconductor package device1includes a substrate11, electrical components12a,12b, a package body13, a shielding layer14, interconnection elements15, a dielectric layer16and an insulating film17.

The substrate11may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. The substrate11may include an interconnection structure, such as a redistribution layer (RDL) or a grounding element11g. In some embodiments, the grounding element11gis a via exposed from a lateral surface113of the substrate11. In some embodiments, the grounding element11gis a metal layer exposed from the lateral surface113of the substrate11. In some embodiments, the grounding element11gis a metal trace exposed from the lateral surface113of the substrate11.

The electrical components12a,12bare disposed on a top surface111of the substrate11. The electrical component12amay be an active component, such as an integrated circuit (IC) chip or a die. The electrical component12bmay be a passive electrical component, such as a capacitor, a resistor or an inductor. Each electrical component12a,12bmay be electrically connected to one or more of another electrical component12a,12band to the substrate11(e.g., to the RDL), and electrical connection may be attained by way of flip-chip or wire-bond techniques.

The package body13is disposed on the top surface111of the substrate11and encapsulates a part of the top surface111of the substrate11and the electrical components12a,12b. In some embodiments, the package body13includes an epoxy resin having fillers dispersed therein.

The shielding layer14is disposed on an external surface of the package body13and covers the package body13, electrical components12a,12band lateral surfaces113of the substrate11. The shielding layer14is electrically connected to the grounding element11gof the substrate11. In some embodiments, the shielding layer14directly contacts the grounding element11gof the substrate11. In some embodiments, the shielding layer14is a conformal shield. The shielding layer14is aligned with a bottom surface112of the substrate11; for example, a bottom of the shielding layer14is substantially coplanar with the bottom surface112of the substrate. In some embodiments, the shielding layer14is a conductive thin film, and may include, for example, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni) or stainless steel, or a mixture, an alloy, or other combination thereof. The shielding layer14may include a single conductive layer or multiple conductive layers. In some embodiments, the shielding layer14includes multiple conductive layers, and the multiple conductive layers may include a same material, or ones of the multiple conductive layers may include different materials, or each of the multiple conductive layers may include different materials from others of the multiple conductive layers. In some embodiments, each conductive layer of the shielding layer14has a thickness of up to about 200 micrometers (μm), such as up to about 150 μm, up to about 100 μm, up to about 50 μm, up to about 10 μm, up to about 5 μm, up to about 1 μm, or up to about 500 nanometers (nm), and down to about 100 nm or less, down to about 50 nm or less, or down to about 10 nm or less. In some embodiments, the shielding layer14includes multiple conductive layers, and different conductive layers may have different thicknesses.

The interconnection elements15are disposed on the bottom surface112of the substrate11. In some embodiments, the interconnection elements15may be, for example, solder balls or conductive pads. The interconnection elements15provide input and output electrical connections for the semiconductor package device1. In some embodiments, one or more of the interconnection elements15are electrically connected to the electrical components12a,12bby way of the interconnection structure included in the substrate11. In some embodiments, at least one interconnection element15is a ground electrical interconnection element and is electrically connected to the grounding element11gthrough the interconnection structure included in the substrate11.

The dielectric layer16is disposed on the bottom surface112of the substrate11. The dielectric layer16may be a solder mask layer, although other dielectric materials having adequate insulation ability may also be used. A side surface of the dielectric layer16is aligned with the lateral surface113of the substrate11; for example, the side surface of the dielectric layer16is substantially coplanar with the lateral surface113of the substrate11.

The insulating film17is disposed on the dielectric layer16. The insulating film17covers a first portion of each of the interconnection elements15and exposes a second portion of each of the interconnection elements15. That is, the insulating film17covers a part of a side portion of each of the interconnection elements15and exposes a bottom portion of each of the interconnection elements15. A side surface of the insulating film17is aligned with the lateral surface113of the substrate11and the side surface of the dielectric layer16; for example, the side surface of the insulating film17is substantially coplanar with the lateral surface113of the substrate11and the side surface of the dielectric layer16. As depicted inFIG. 1, the side surface of the dielectric layer16and the side surface of the insulating film17are exposed from the shielding layer14. In some embodiments, top and bottom surfaces of the insulating film17are substantially planar. In other words, a thickness of the insulating film17is substantially uniform. In some embodiments, the insulating film17extends continuously on the dielectric layer16, so that a portion of the insulating film17covering one interconnection element15is connected to another portion of the insulating film17covering another interconnection element15. In some embodiments, the insulating film17is selected from, or formed from, a thermal curing material (e.g., a thermal curing resin) or an optically sensitive material (e.g., an ultraviolet (UV) curing resin).

Since the insulating film17is formed over the bottom surface112of the substrate11and covers parts of the interconnection elements15, the insulating film17can release a stress on the substrate11, which can, in turn, improve a solder joint reliability of the interconnection elements15to an underlying package device carrier. In addition, the insulating film17disposed over the bottom surface112of the substrate11can operate together with the shielding layer14to further improve the effectiveness of EMI shielding, for example, with respect to electromagnetic emissions through a bottom of the semiconductor package device1or by preventing an undesired short circuit between the interconnection elements15and the shielding layer14.

FIG. 2illustrates a cross-sectional view of a semiconductor package device2in accordance with some embodiments of the present disclosure. The semiconductor package device2is similar to the semiconductor package device1shown inFIG. 1, with a difference being that side surfaces of a dielectric layer26and an insulating film27are not aligned with the lateral surface113of the substrate11. In other words, a space is formed between the side surface of the dielectric layer26and the lateral surface113of the substrate11, and between the side surface of the insulating film27and the lateral surface113of the substrate11, and the side surfaces of the dielectric layer26and the insulating film27are inwardly recessed relative to the lateral surface113of the substrate11. In some embodiments, the side surface of the dielectric layer26is aligned with the side surface of the insulating film27; for example, the side surface of the dielectric layer26is substantially coplanar with the side surface of the insulating film27.

As illustrated inFIG. 2, a portion of a shielding layer24extends on a portion of the bottom surface112of the substrate11, but does not contact the interconnection elements15. In other words, the shielding layer24is electrically isolated from the interconnection elements15by the insulating film27, with a gap between the shielding layer24and the insulating film27(although the gap can be omitted in other embodiments). Since a portion of the shielding layer24is formed on the bottom surface112of the substrate11to protect the interconnection elements15from EMI, the effectiveness of EMI shielding is further enhanced.

FIGS. 3A-3Eillustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure.

Referring toFIG. 3A, a substrate strip including multiple substrates31is provided, and the provision of the multiple substrates31allows multiple semiconductor package devices to be manufactured concurrently. The substrate31may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. The substrate31may include an interconnection structure, such as a RDL or a grounding element31g. In some embodiments, the grounding element31gis a via to be subsequently exposed from a lateral surface313of the substrate31. In some embodiments, the grounding element31gis a metal layer to be subsequently exposed from the lateral surface313of the substrate31. In some embodiments, the grounding element31gis a metal trace to be subsequently exposed from the lateral surface313of the substrate31.

Electrical components32a,32bare mounted on a top surface311of each substrate31. The electrical component32amay be an active component, such as an IC chip or a die. The electrical component32bmay be a passive electrical component, such as a capacitor, a resistor or an inductor. Each electrical component32a,32bmay be electrically connected to one or more of another electrical component32a,32band to the substrate31(e.g., to the RDL), and electrical connection may be attained by way of flip-chip or wire-bond techniques.

A package body33is formed on the top surface311of each substrate31to encapsulate a part of the top surface311of the substrate31and the electrical components32a,32b. In some embodiments, the package body33includes an epoxy resin having fillers dispersed therein. The package body33may be formed by a molding technique, such as transfer molding or compression molding.

Referring toFIG. 3B, multiple interconnection elements35are formed on a bottom surface312of each substrate31. In some embodiments, the interconnection elements35may be, for example, solder balls or conductive pads. The interconnection elements35provide input and output electrical connections for a resulting semiconductor package device. In some embodiments, one or more of the interconnection elements35are electrically connected to the electrical components32a,32bby way of the interconnection structure included in the substrate31. In some embodiments, at least one interconnection element35is a ground electrical interconnection element and is electrically connected to the grounding element31gthrough the interconnection structure included in the substrate31.

An insulating film37is formed on the bottom surface312of each substrate31to substantially fully cover the bottom surface312of the substrate31and the interconnection elements35. In other words, the insulating film37is conformal to the interconnection elements35. In some embodiments, the insulating film37is formed by the following operations: (a) mixing a diluent and an insulating ink to form a material of the insulating film37; (b) coating the material of the insulating film37on the bottom surface312of the substrate31and the interconnection elements35; and (c) curing the material to form the insulating film37. In operation (b), the coating can be accomplished by spraying. In some embodiments, the insulating film37is selected from, or formed from, a thermal curing resin or an UV curing resin, and, in operation (c), the curing can be accomplished by thermal curing or UV curing.

Referring toFIG. 3C, singulation is performed to separate out individual semiconductor package devices. That is, the singulation is performed through the package body33and the substrate strip including the substrates31. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique. As depicted inFIG. 3C, a side surface of the insulating film37is aligned with a lateral surface313of each substrate31.

Referring toFIG. 3D, a shielding layer34is formed to cover an external surface of the package body33and the lateral surface313of the substrate31. The shielding layer34directly contacts and is electrically connected to the grounding element31gof the substrate31. In some embodiments, the shielding layer34is a conformal shield. The shielding layer34is aligned with the bottom surface312of the substrate31. In some embodiments, the shielding layer34can be formed by sputtering or other appropriate deposition technique. In some embodiments, the shielding layer34is a conductive thin film, and may include, for example, Al, Cu, Cr, Sn, Au, Ag, Ni or stainless steel, or a mixture, an alloy, or other combination thereof.

The shielding layer34may include a single conductive layer or multiple conductive layers. In some embodiments, the shielding layer34includes multiple conductive layers, and the multiple conductive layers may include a same material, or ones of the multiple conductive layers may include different materials, or each of the multiple conductive layers may include different materials from others of the multiple conductive layers. In some embodiments, each conductive layer of the shielding layer34has a thickness of up to about 200 μm, such as up to about 150 μm, up to about 100 μm, up to about 50 μm, up to about 10 μm, up to about 5 μm, up to about 1 μm, or up to about 500 nm, and down to about 100 nm or less, down to about 50 nm or less, or down to about 10 nm or less. In some embodiments, the shielding layer34includes multiple conductive layers, and different conductive layers may have different thicknesses.

Referring toFIG. 3E, the insulating film37is removed from the bottom surface312of the substrate31and the interconnection elements35to form a semiconductor package device3. In some embodiments, the insulating film37can be removed by the following operations: (a) dipping the insulating film37in a chemical bath of a liquid, such as sodium hydroxide (NaOH); and (b) removing the insulating film37by using a water jet. In other embodiments, a portion of the insulating film37remains on the bottom surface312of the substrate31to form the semiconductor package device1depicted inFIG. 1. In some embodiments, a solder mask layer (not shown inFIGS. 3A-3E) is formed on the bottom surface312of the substrate31prior to forming the insulating film37, and the insulating film37is formed on the solder mask layer.

In the absence of an insulating film which is formed to cover interconnection elements before forming a shielding layer, when sputtering a metal to form the shielding layer, the shielding layer is likely to be electrically connected to the interconnection elements to cause an undesired short circuit. As shown inFIGS. 3A-3E, by forming the insulating film37to cover the interconnection elements35before forming the shielding layer34, the insulating film37can prevent an undesired short circuit between the interconnection elements35and the shielding layer34, which can, in turn, increase a reliability of the semiconductor package device3and reduce a manufacturing cost.

FIGS. 4A-4Dillustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure. The operations shown inFIGS. 4A-4Dare performed subsequent to the operations of forming the interconnection elements35shown inFIG. 3B.

Referring toFIG. 4A, after forming the interconnection elements35, a mask frame47mis disposed or formed on the bottom surfaces312of the substrates31. An insulating film47may be formed on the bottom surface312of each substrate31by, for example, a spray coating technique. The insulating film47covers the bottom surface312of the substrate31that is exposed by the mask frame47m. The insulating film47covers the interconnection elements35. The mask frame47mis removed subsequent to the formation of the insulating film47. In some embodiments, the insulating film47is formed by the following operations: (a) mixing a diluent and an insulating ink to form a material of the insulating film47; (b) coating the material of the insulating film47on the interconnection elements35and the bottom surface312of the substrate31that is exposed by the mask frame47m; and (c) curing the material to form the insulating film47. In operation (b), the coating can be accomplished by spraying. In some embodiments, the insulating film47is selected from, or formed from, a thermal curing resin or an UV curing resin.

Referring toFIG. 4B, singulation may be performed to separate out individual semiconductor package devices. That is, the singulation is performed through the package body33and the substrate strip including the substrates31. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique. As depicted inFIG. 4B, a side surface of the insulating film47is not aligned with the lateral surface313of the substrate31, and a space is formed between the side surface of the insulating film47and the lateral surface313of the substrate31after removing the mask frame47m.

Referring toFIG. 4C, a shielding layer44is formed to cover the external surface of the package body33, the lateral surface313of the substrate31and a portion of the bottom surface312of the substrate31. The shielding layer44is electrically isolated from the interconnection elements35by the insulating film47. The shielding layer44directly contacts and is electrically connected to the grounding element31gof the substrate31. In some embodiments, the shielding layer44is a conformal shield. In some embodiments, the shielding layer44can be formed by sputtering or other appropriate deposition technique. In some embodiments, the shielding layer44is a conductive thin film, and may include, for example, Al, Cu, Cr, Sn, Au, Ag, Ni or stainless steel, or a mixture, an alloy, or other combination thereof.

The shielding layer44may include a single conductive layer or multiple conductive layers. In some embodiments, the shielding layer44includes multiple conductive layers, and the multiple conductive layers may include a same material, or ones of the multiple conductive layers may include different materials, or each of the multiple conductive layers may include different materials from others of the multiple conductive layers. In some embodiments, each conductive layer of the shielding layer44has a thickness of up to about 200 μm, such as up to about 150 μm, up to about 100 μm, up to about 50 μm, up to about 10 μm, up to about 5 μm, up to about 1 μm, or up to about 500 nm, and down to about 100 nm or less, down to about 50 nm or less, or down to about 10 nm or less. In some embodiments, the shielding layer44includes multiple conductive layers, and different conductive layers may have different thicknesses.

Referring toFIG. 4D, the insulating film47is removed from the bottom surface312of the substrate31and the interconnection elements35to form a semiconductor package device4. In some embodiments, the insulating film47can be removed by the following operations: (a) dipping the insulating film47in a chemical bath of a liquid, such as NaOH; and (b) removing the insulating film47by using a water jet. In other embodiments, a portion of the insulating film47remains on the bottom surface312of the substrate31to form the semiconductor package device2depicted inFIG. 2. In some embodiments, a solder mask layer (not shown inFIGS. 4A-4D) is formed on the bottom surface312of the substrate31prior to forming the insulating film47, and the insulating film47is formed on the solder mask layer.

As mentioned above, by forming the insulating film47to cover the interconnection elements35before forming the shielding layer44, the insulating film47can prevent an undesired short circuit between the interconnection elements35and the shielding layer44, which can, in turn, increase the reliability of the semiconductor package device4and reduce a manufacturing cost.

FIGS. 5A-5Dillustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure. The operations shown inFIGS. 5A-5Dare performed subsequent to the operations of forming the interconnection elements35shown inFIG. 3B.

Referring toFIG. 5A, after forming the interconnection elements35, a first insulating film56is disposed or formed on the bottom surface312of each substrate31to cover the bottom surface312of the substrate31and a portion of the interconnection elements35. In some embodiments, the first insulating film56is formed by the following operations: (a) mixing a diluent and an insulating ink to form a material of the first insulating film56; (b) coating the material of the first insulating film56on the bottom surface312of the substrate31and a portion of the interconnection elements35; and (c) curing the material to form the first insulating film56. In operation (b), the coating can be accomplished by spraying. In some embodiments, the first insulating film56is selected from, or formed from, a thermal curing resin or an UV curing resin. In some embodiments, the first insulating film56is disposed on the bottom surface312of the substrate31by attaching the first insulating film56having holes on the bottom surface312of the substrate31to expose a portion of the interconnection elements35through the holes.

A second insulating film57is formed on the first insulating film56to cover the first insulating film56and a remaining portion of the interconnection elements35that is exposed from the first insulating film56. In some embodiments, the second insulating film57is formed by the following operations: (a) mixing a diluent and an insulating ink to form a material of the second insulating film57; (b) coating the material of the second insulating film57on the bottom surface312of the substrate31and the remaining portion of the interconnection elements35; and (c) curing the second insulating film57. In operation (b), the coating can be accomplished by spraying. In some embodiments, the second insulating film57is selected from, or formed from, a thermal curing resin or an UV curing resin. In some embodiments, the first insulating film56and the second insulating film57are formed of a same material. Alternatively, the first insulating film56and the second insulating film57are formed of different materials.

Referring toFIG. 5B, singulation may be performed to separate out individual semiconductor package devices. That is, the singulation is performed through the package body33and the substrate strip including the substrates31. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique. As depicted inFIG. 5B, a side surface of the first insulating film56is aligned with the lateral surface313of the substrate31, and a side surface of the second insulating film57is aligned with the side surface of the first insulating film56.

Referring toFIG. 5C, a shielding layer34is formed to cover the external surface of the package body33and the lateral surface313of the substrate31. The shielding layer34directly contacts and is electrically to the grounding element31gof the substrate31. In some embodiments, the shielding layer34is a conformal shield. The shielding layer34is aligned with the bottom surface312of the substrate31. In some embodiments, the shielding layer34can be formed by sputtering or other appropriate deposition technique. In some embodiments, the shielding layer34is a conductive thin film, and may include, for example, Al, Cu, Cr, Sn, Au, Ag, Ni or stainless steel, or a mixture, an alloy, or other combination thereof.

The shielding layer34may include a single conductive layer or multiple conductive layers. In embodiments, the shielding layer34includes multiple conductive layers, and the multiple conductive layers may include a same material, or ones of the multiple conductive layers may include different materials, or each of the multiple conductive layers may include different materials from others of the multiple conductive layers. In some embodiments, each conductive layer of the shielding layer34has a thickness of up to about 200 μm, such as up to about 150 μm, up to about 100 μm, up to about 50 μm, up to about 10 μm, up to about 5 μm, up to about 1 μm, or up to about 500 nm, and down to about 100 nm or less, down to about 50 nm or less, or down to about 10 nm or less. In some embodiments, the shielding layer34includes multiple conductive layers, and different conductive layers may have different thicknesses.

Referring toFIG. 5D, the second insulating film57is removed from the interconnection elements35to form a semiconductor package device5similar to the semiconductor package device1as shown inFIG. 1. In some embodiments, a portion of the first insulating film56covering the interconnection elements35is also removed from the interconnection elements35. In some embodiments, the second insulating film57can be removed by the following operations: (a) dipping the second insulating film57in a chemical bath of a liquid, such as NaOH; and (b) removing the second insulating film57by using a water jet. In some embodiments, a portion of the first insulating film56covering the interconnection elements35can be removed in conjunction or sequentially with the second insulating film57by similar operations. In some embodiments, a solder mask layer (not shown inFIGS. 5A-5D) is formed on the bottom surface312of the substrate31prior to forming the first insulating film56, and the first insulating film56is formed on the solder mask layer. In some embodiments, an adhesiveness of the first insulating film56is greater than that of the second insulating film57, such that the second insulating film57can be removed while retaining the first insulating film56on the bottom surface312of the substrate31.

As mentioned above, by forming the first insulating film56and the second insulating film57to cover the interconnection elements35before forming the shielding layer34, the first insulating film56and the second insulating film57can prevent an undesired short circuit between the interconnection elements35and the shielding layer34, which can, in turn, increase the reliability of the semiconductor package device and reduce a manufacturing cost.

FIGS. 6A and 6Billustrate a semiconductor manufacturing method in accordance with some embodiments of the present disclosure. The operations shown inFIGS. 6A and 6Bare additional embodiments of forming the insulating film47as shown inFIG. 4A. That is, the operations shown inFIGS. 6A and 6Bare performed subsequent to the operations of forming the interconnection elements35shown inFIG. 3Band prior to the operations of singulation shown inFIG. 4B.

Referring toFIG. 6A, after forming the interconnection elements35, an insulating film67is formed to substantially fully cover the bottom surface312of each substrate31and the interconnection elements35. The insulating film67may include, or may be formed from, an UV curing resin. A mask film69is disposed above the bottom surface312of the substrate31. In some embodiments, the mask film69is a photo-imagable mask film. The mask film69is patterned to include at least two portions, which include a first portion69athat is transmissive to UV light and a second portion69bto block UV light. A photolithography technique is applied to the patterned mask film69. After the operation of the photolithography technique, a portion of the insulating film67that is under the second portion69bof the mask film69and not radiated by UV light is removed, to form the insulating film67as shown inFIG. 6B.

As shown inFIG. 6B, a side surface of the insulating film67is not aligned with the lateral surface313of the substrate31. A space is formed between the side surface of the insulating film67and the lateral surface313of the substrate31.

As used herein, the terms “substantially,” “substantial,” “approximately,” and “about” are used to denote and account for small variations. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a thickness of a film or a layer being “substantially uniform” can refer to a standard deviation of less than or equal to ±10% of an average thickness of the film or the layer, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along a same plane, such as within 100 μm, within 80 μm, within 60 μm, within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane. Two surfaces or components can be deemed to be “substantially perpendicular” if an angle therebetween is, for example, 90°±10°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°. When used in conjunction with an event or circumstance, the terms “substantially,” “substantial,” “approximately,” and “about” can refer to instances in which the event or circumstance occurs precisely, as well as instances in which the event or circumstance occurs to a close approximation.

In the description of some embodiments, a component provided “on” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It can be understood that such range formats are used for convenience and brevity, and should be understood flexibly to include not only numerical values explicitly specified as limits of a range, but also all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.