Method for regulating temperature and circuit therefor

A method and circuit for managing thermal performance of an integrated circuit. In accordance with an embodiment, a thermal limit circuit and a semiconductor device are manufactured from a semiconductor material, wherein the thermal limit circuit is configured to operate at a temperature level that is different from a threshold temperature in response to the thermal sensing element sensing a temperature at least equal to the threshold temperature.

BACKGROUND

The present invention relates, in general, to electronics and, more particularly, to methods of forming semiconductor devices and structure.

High power semiconductor components typically include circuitry to protect them from thermal failure. For example, an integrated voltage regulator that dissipates a large amount of heat often includes a thermal shutdown circuit that shuts down or turns off the integrated circuit when the temperature reaches a critical level. Once the substrate cools down, the thermal shutdown circuit turns the voltage regulator back on. A drawback with including thermal shutdown circuits is that they completely remove power from their load and cause the system to shut down.

Another common way to protect power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) against thermal failure is to decrease the current conducted through them by coupling together a plurality of output devices in parallel. For example, a plurality of insulated gate field effect transistors can be configured to have their drain terminals coupled to each other, their gate terminals coupled to each other, and their source terminals coupled to each other. In this configuration, the output current is shared by several insulated gate field effect transistors such that the total output current is the sum of the currents flowing through each insulated gate field effect transistor. A drawback with this approach is that differences in their on-resistance (Rdson) may lead to an imbalance in the currents that flow through each insulated gate field effect transistor causing one or more of the field effect transistors to overheat and suffer thermal failure. Integrated circuit manufacturers have included active circuits that measure the current flowing in the parallel connected insulated gate field effect transistors to overcome this problem. In this configuration, the gate terminals are not connected to each other but are coupled to receive independent control signals. A control circuit uses the measured current to adjust the gate drive of the individual insulated gate field effect transistors to maintain substantially the same current in each insulated gate field effect transistor. Drawbacks with this approach include the need for complicated circuitry to monitor the current flowing through each insulated gate field effect transistor and the complexity of the interconnections to route the data to the control circuit.

Accordingly, it would be advantageous to have methods and circuits that lower the operating temperature of a transistor and that maintain current conduction through the transistor. It would be advantageous for the methods and circuits to be cost efficient.

For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, or certain N-type or P-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action. The use of the word approximately or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of exactly as described.

It should be noted that a logic zero voltage level (VL) is also referred to as a logic low voltage and that the voltage level of a logic zero voltage is a function of the power supply voltage and the type of logic family. For example, in a Complementary Metal Oxide Semiconductor (CMOS) logic family a logic low voltage may be thirty percent of the power supply voltage level. In a five volt Translator-Translator Logic (TTL) system a logic low voltage level may be about 0.8 volts, whereas for a five volt CMOS system, the logic zero voltage level may be about 1.5 volts. A logic one voltage level (VH) is also referred to as a logic high voltage level and, like the logic zero voltage level, the logic high voltage level also may be a function of the power supply and the type of logic family. For example, in a CMOS system a logic one voltage may be about seventy percent of the power supply voltage level. In a five volt TTL system a logic one voltage may be about 2.4 volts, whereas for a five volt CMOS system, the logic one voltage may be about 3.5 volts.

DETAILED DESCRIPTION

Generally, the present invention provides methods and circuitry for performing thermal management of devices manufactured from a semiconductor material including integrated circuits, power MOSFETs with internal temperature sense circuitry, and the like. In accordance with an embodiment of the present invention, the integrated circuit comprises one or more power semiconductor devices such as, for example, one or more power Field Effect Transistors (FETs). Each power FET is connected to a thermal limit circuit and a signal regulator. The thermal limit circuit may be referred to as a linear thermal limit circuit or a temperature regulator. The signal regulator may be a voltage regulator, a current regulator, or the like. The thermal limit circuit operates in an idle or standby mode in response to heat generated by the power FET being sufficiently low that the temperature of the semiconductor material is below a predetermined value or level. The predetermined temperature value or level is also referred to as a predefined temperature, a threshold temperature value or level, or a threshold value or level. In response to at least one power FET generating sufficient heat to raise the temperature of the semiconductor material to the threshold level, the thermal limit circuit enters an active mode and the signal regulator enters the standby mode. The active operating mode of the thermal limit circuit is also referred to as a temperature mode. In the active mode or temperature mode, the thermal limit circuit generates a drive signal for the power FET that maintains a drain-to-source current flowing through the power FET but at a level that is substantially constant and below its level when the power FET operates in its normal operating mode, i.e., in response to the signal regulator operating in the active mode and the thermal limit circuit operating in the standby mode.

In accordance with an embodiment of the present invention and in response to the temperature of the semiconductor device or the temperature sensed by a thermal sensing element equaling or exceeding a threshold temperature, the thermal limit circuit is configured to operate in the active or temperature mode and generates a gate drive signal that results in the power FET having a constant current that is less than a nominal operating current. Accordingly, the thermal limit circuit is configured to operate at a temperature level that is substantially constant and less than the threshold temperature.

In accordance with an embodiment of the present invention and in response to the temperature equaling or exceeding a threshold level, the thermal limit circuit operates in the active or temperature mode and generates a gate drive signal that results in the power FET having an oscillating drain-to-source current. Accordingly, the thermal limit circuit is configured to operate at a temperature that oscillates through a range of temperatures, i.e., the operating temperature of the thermal limit circuit is variable, wherein the average temperature of the range is less than the threshold temperature. The lower temperature level of the oscillating temperature is below the threshold level and the upper temperature level may be below, above, or equal to the threshold level.

FIG. 1is a circuit schematic of an integrated circuit10that includes a thermal limit circuit12and a signal regulator14coupled to a semiconductor device60in accordance with an embodiment of the present invention. Thermal limit circuit12includes a thermal regulator amplifier18connected to a thermal hysteresis comparator22, a delay element24, a voltage adjustment element26, and a voltage divider network28. More particularly, thermal regulator amplifier18has an inverting input terminal, a noninverting input terminal, and an output terminal, wherein the output terminal of thermal regulator amplifier18is connected to its inverting input terminal by a feedback network20. Thus, thermal regulator amplifier18is connected in a negative feedback configuration.

Thermal hysteresis comparator22has a noninverting input terminal connected to the output terminal of thermal regulator amplifier18and an inverting input terminal coupled for receiving a reference voltage VREF1. The output terminal of thermal hysteresis comparator22is connected to voltage adjustment element26through a delay element24. By way of example, voltage adjustment element26is a field effect transistor having a control terminal and current carrying electrodes27and29. The control terminal of field effect transistor26is connected to an output terminal25of delay element24, current carrying electrode27is coupled for receiving a source of operating potential such as, for example, VSS, and current carrying electrode29is connected to voltage divider network28. By way of example, voltage divider network28is comprised of a resistor30having terminals32and34and a resistor36having terminals38and40and voltage or potential VSSis at ground. Terminal32of resistor30may be coupled for receiving a source of operating potential such as, for example, VSS, and terminal34is commonly connected to current carrying electrode29of field effect transistor26and to terminal38of resistor36. Terminal40of resistor36is commonly connected to the inverting input terminal of thermal regulator amplifier18, feedback network20, and for receiving a reference voltage VREF2through a resistor42. Hysteresis comparator22, delay element24, transistor26, and voltage divider network28are configured to adjust the voltage at the noninverting input terminal of thermal regulator amplifier18and form a reference voltage adjustment circuit.

A diode45having an anode terminal and a cathode terminal is commonly connected to the output terminal of thermal regulator amplifier18and to the noninverting input terminal of thermal hysteresis comparator22. More particularly, the cathode terminal of diode45is commonly connected to the output terminal of thermal regulator amplifier18and to the noninverting input terminal of thermal hysteresis comparator22.

The thermal limit circuit further includes a current source46connected between the noninverting input terminal of thermal regulator amplifier18and a source of operating potential VDD, and a temperature sensing diode48is connected between the inverting input terminal of thermal regulator amplifier18and a source of operating potential such as, for example, VSS. It should be noted that thermal sensing diode48is thermally coupled to transistor60and may be positioned to be close to the semiconductor device from which it is sensing the temperature. Thus, thermal sensing diode48may be positioned close to transistor60so that it can sense the heat generated by transistor60. In accordance with embodiments in which transistor60is a power Field Effect Transistor (FET) temperature sensing diode48may be placed on the semiconductor die or chip from which the power FET is fabricated.

In accordance with an embodiment of the present invention, signal regulator14is a voltage regulator comprising an error amplifier50having a noninverting input terminal coupled for receiving a reference voltage VREF3, an inverting input terminal coupled to a source of operating potential such as, for example, VSS, through a resistor52, and an output terminal coupled to the cathode of diode45through a resistor54. A feedback circuit56is commonly connected to the inverting input terminal of error amplifier50and to resistor52.

Thermal limit circuit12and a signal regulator14are connected to transistor60which may be, for example, a power field effect transistor. Transistor60has a control electrode and current carrying electrodes62and64, wherein the control electrode is connected to the cathode terminal of diode45, current carrying electrode62is connected to a bus line, and current carrying electrode64is connected to the inverting input terminal of error amplifier50through feedback network56and to a load68. It should be noted that load68is connected between current carrying electrode64and a source of operating potential such as, for example, VSS.

In operation, thermal limit circuit12and signal regulator14cooperate to maintain field effect transistor60in an operating mode in which its operating temperature is maintained at a level that is below a threshold level TTHRin response to the temperature near field effect transistor60equaling or exceeding threshold level TTHR.FIG. 2is a plot illustrating the temperature sensed by temperature sensing diode48versus time. At time t0to a time just before time t1, the temperature sensed by temperature sensing diode48is less than a threshold temperature TTHR. In response to the temperature sensed by temperature sensing diode48being less than threshold temperature TTHR, transistor60operates in a normal operating mode where thermal limit circuit12operates in a standby mode, diode45is reverse biased, and signal regulator14maintains a voltage VOUTat output terminal70. During this period, output current IOUTis at a nominal level INOM. At time t1, the operating temperature TOPis substantially equal to threshold temperature TTHR. In response to the operating temperature TOPbeing equal to threshold temperature TTHR, thermal limit circuit12enters an active mode, which forward biases diode45and enables thermal limit circuit12to control the voltage at the gate terminal of transistor60, and signal regulator14enters a standby mode to bring the current to level IREGand the operating temperature to temperature TREG.

Referring again toFIG. 1, in a normal operating mode error amplifier50generates an error signal that controls the gate voltage of field effect transistor60, which regulates output voltage VOUT. In addition, temperature sensing diode48is configured such that, in the normal operating mode, the voltage across temperature sensing diode48is greater than reference voltage VREF2. In response to the voltage across temperature sensing diode48being greater than reference voltage VREF2, thermal regulator amplifier18generates an output signal that is sufficiently high that ORing diode45is reverse biased. Accordingly, thermal limit circuit12has substantially no impact on the operation of field effect transistor60. In the standby operating mode, thermal hysteresis comparator22is configured to generate a logic low voltage level at output terminal23. After a delay introduced by delay element24, the logic high voltage level appears at the control electrode of field effect transistor26. The logic high voltage appearing at the control electrode of field effect transistor26turns it on. A drain-to-source current flows in field effect transistor in the on state. Thus, in the standby operating mode the voltage at the inverting input terminal of thermal regulator amplifier18is approximately equal to (VREF2*(R36))/(R36+R42) where R36is the resistance value of resistor36, R42is the resistance value of resistor42, and voltage source VSSis at ground potential.

In response to the temperature sensed by temperature sensing diode48equaling or exceeding threshold temperature TTHR, the voltage across temperature sensing diode48becomes less than the voltage appearing at the inverting input terminal to thermal regulator amplifier18, and thermal limit circuit12enters an active operating mode and signal regulator14enters a standby operating mode. As discussed above, the voltage appearing at the inverting input terminal to thermal regulator amplifier18is approximately equal to (VREF2*(R36))/(R36+R42). Accordingly, thermal regulator amplifier20generates an output signal that becomes sufficiently low that ORing diode45turns on and reduces the voltage at the gate terminal of field effect transistor60. In response to the decreased gate voltage, the drain-to-source current of field effect transistor60decreases which lowers its operating temperature.

In addition, decreasing the output voltage of thermal regulator amplifier18configures the input signals at the inputs of thermal hysteresis comparator22such that its output voltage becomes a logic low voltage level. At this transition there is substantially zero delay introduced by delay element24, thus the logic high voltage level substantially immediately appears at the control electrode of field effect transistor26. Because of the logic high voltage appearing at its control electrode, field effect transistor26is on. In the active operating mode the voltage at the inverting input terminal of thermal regulator amplifier18is approximately equal to (VREF2*(R30+R36)/(R30+R36+R42) where R30is the resistance value of resistor30, R36is the resistance value of resistor36, R42is the resistance value of resistor42, and voltage source VSSis at ground potential. Thus, when thermal limit circuit12is in the active operating mode, the voltage at the inverting input terminal of thermal regulator amplifier18is greater than it is when thermal limit circuit12is in the standby operating mode. In response to the higher reference voltage at the inverting input terminal of thermal regulator amplifier18, temperature regular12adjusts the steady-state thermal regulation point. Delay element24maintains the new thermal reference voltage level until thermal limit circuit12adjusts to the new thermal regulation point. In accordance with an embodiment of the present invention, the delay time for delay element24is at least one thermal time constant of integrated circuit10. By way of example the delay of delay element24is 50 milliseconds.

Decreasing the voltage at the gate of field effect transistor60reduces the drain-to-source current which decreases the operating temperature of field effect transistor60as illustrated inFIG. 2. In response to the decreased operating temperature, the voltage across temperature sensing diode48increases. When the voltage across temperature sensing diode48is greater than the voltage at the inverting input terminal of the thermal regulator amplifier18, thermal regulator amplifier18generates an output signal that is sufficiently high that ORing diode45is reverse biased. Accordingly, thermal limit circuit12enters a standby operating mode and signal regulator14enters the normal operating mode.

FIG. 3is a circuit schematic of an integrated circuit100that includes a thermal limit circuit102and signal regulator14coupled to a semiconductor device60in accordance with an embodiment of the present invention. Signal regulator14has been described with reference toFIG. 1. Thermal limit circuit102is similar to thermal limit circuit12except that delay element24and field effect transistor26are replaced by a low frequency oscillator and RS latch104, a comparator106, and a voltage source108. More particularly, low frequency oscillator and RS latch104has input terminals110and112and output terminals114and116. The output terminal of thermal hysteresis comparator22is connected to input terminal110of low frequency oscillator and RS latch104and output terminal114of low frequency oscillator and RS latch104is commonly connected to terminals34and38of resistors30and36, respectively. Output terminal116of low frequency oscillator and RS latch104is coupled for receiving a source of operating potential such as, for example, VSS, which may be at, for example, ground potential. Comparator106has an inverting input terminal commonly connected to the inverting input terminal of thermal regulator amplifier18and to resistors36and42. The noninverting input terminal of comparator106is connected to the noninverting input terminal of thermal regulator18through voltage source108. By way of example, voltage source108may be implemented as an offset voltage of comparator106. The output terminal of comparator106is connected to input terminal112of low frequency oscillator104. Hysteresis comparator22, low frequency oscillator and RS latch104, voltage divider network28, comparator106, and voltage source108are configured to adjust the voltage at the noninverting input terminal of thermal regulator amplifier18and form a reference voltage adjustment circuit.

In operation, thermal limit circuit102and signal regulator14cooperate to maintain field effect transistor60in an operating mode in which its average operating temperature TOPis maintained at a level that is below threshold level TTHRin response to the temperature near field effect transistor60equaling or exceeding threshold level TTHR.FIG. 4is a plot illustrating the temperature sensed by temperature sensing diode48versus time. From times t0to about time t1, the temperature sensed by temperature sensing diode48is less than a threshold temperature TTHR. In response to the temperature sensed by temperature sensing diode48being less than threshold temperature TTHR, transistor60operates in a normal operating mode where thermal limit circuit102operates in a standby mode and signal regulator14maintains a voltage VOUTat output terminal70. During this period, output current IOUTis at a nominal level INOM. At time t1, the operating temperature TOPis substantially equal to threshold temperature TTHR. In response to the operating temperature TOPbeing equal to threshold temperature TTHR, thermal limit circuit102enters an active operating mode and signal regulator14enters a standby operating mode.

Referring again toFIG. 3, in a normal operating mode error amplifier50generates an error signal that controls the gate voltage of field effect transistor60, which regulates output voltage VOUT. In addition, temperature sensing diode48is configured such that, in the normal operating mode, the voltage across temperature sensing diode48is greater than reference voltage VREF2. In response to the voltage across temperature sensing diode48being greater than the reference voltage at the inverting input terminal to thermal regulator amplifier18, thermal regulator amplifier18generates an output signal that is sufficiently high that ORing diode45is reverse biased. Accordingly, thermal limit circuit102has substantially no impact on the operation of field effect transistor60. In the standby operating mode, thermal hysteresis comparator22is configured to generate a logic low voltage level at output terminal23. Comparator106generates a logic high voltage level at input112of low frequency oscillator and RS latch104. In response to the logic high voltage level that appears at input terminal112, low frequency oscillator and RS latch104is set to sink current from output terminal114. Thus, in the standby mode of operation the voltage at the inverting input terminal of thermal regulator amplifier18is approximately equal to (VREF2*(R36)/(R36+R42) where R36is the resistance value of resistor28, R42is the resistance value of resistor42, and voltage source VSSis at ground potential.

In response to the temperature sensed by temperature sensing diode48, equaling or exceeding threshold temperature TTHR, the voltage across temperature sensing diode48becomes less than reference voltage VREF2, thermal limit circuit102enters an active operating mode, and signal regulator14enters a standby operating mode. Accordingly, thermal regulator amplifier20generates an output signal that becomes sufficiently low that ORing diode45turns on and reduces the voltage at the gate terminal of field effect transistor60. In response to the decreased gate voltage, the drain-to-source current of field effect transistor60decreases which lowers the operating temperature of field effect transistor60.

In addition, decreasing the output voltage of thermal regulator amplifier18configures the input signal at the noninverting input terminal of thermal hysteresis comparator22such that its output voltage becomes a logic high voltage level, which is transmitted to set input terminal110of a latching portion of low frequency oscillator104. The logic high voltage at set input terminal110enables low frequency oscillator104which provides a varying reference voltage for the thermal regulation loop to follow. Comparator106in cooperation with voltage108tracks the input voltage to thermal regulator amplifier18. The input signal to thermal regulator amplifier18follows or is substantially the same as the frequency of oscillator104if the frequency of oscillator104is set at a level of two thermal time constants or more. In response to temperature sensing diode48being more than about 20 millivolts above the thermal reference voltage, (about 10 degrees Celsius), the output of comparator106becomes a logic high voltage, causing the output of thermal hysteresis comparator22to transition to a logic low voltage level, which resets the latch of low frequency oscillator104and places thermal limit circuit102in the standby operating mode and signal regulator14in the normal operating mode.

FIG. 4illustrates that decreasing the voltage at the control electrode of field effect transistor60so that the gate drive voltage level is reduced and time varying, or oscillatory, generates a drain-to-source current that oscillates and has an average level that is lower than the nominal current level in response to signal regulator14operating in the active mode. In response to the decreased oscillating drain-to-source current, the operating temperature also decreases and oscillates, i.e., varies over time. Decreasing the operating temperature, increases the voltage across temperature sensing diode48. As discussed above, in response to temperature sensing diode48being more than about 20 millivolts above the thermal reference voltage, (about 10 degrees Celsius), the output of comparator106becomes a logic high voltage, which causes the output of thermal hysteresis comparator22to transition to a logic low voltage level and places thermal limit circuit102in the standby operating mode.

By now it should be appreciated that circuitry and methods have been provided for performing thermal management in an integrated circuit. Rather than managing temperature constraints by shutting down the power FET, the operating temperature may be held at a constant value below a threshold value or the operating temperature may be made time varying. In these embodiments, the thermal control circuitry may include a thermal limit circuit and a signal regulator and may operate such that in the normal operating mode the signal regulator controls the drain-to-source current of the power FET or in temperature regulation mode the thermal limit circuit controls the drain-to-source current of the power FET.

Although specific embodiments have been disclosed herein, it is not intended that the invention be limited to the disclosed embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. It is intended that the invention encompass all such modifications and variations as fall within the scope of the appended claims.