Carrier warpage control for three dimensional integrated circuit (3DIC) stacking

An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

BACKGROUND

As the demand for smaller electronic products grows, manufacturers and others in the electronics industry continually seek ways to reduce the size of integrated circuits used in the electronic products. In that regard, three-dimensional type integrated circuit packaging techniques have been developed and used.

One packaging technique that has been developed is Package-on-Package (PoP). As the name implies, PoP is a semiconductor packaging innovation that involves stacking one package on top of another package. A PoP device may combine vertically discrete memory and logic packages.

Unfortunately, conventional processes used to fabricate the PoP devices may not be able to sufficiently prevent the packages from warping. This is particularly true when relatively thin dies or integrated circuits are being stacked.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

The present disclosure will be described with respect to present embodiments in a specific context, namely a package-on-package (PoP) semiconductor device. The concepts in the disclosure may also apply, however, to other semiconductor structures or circuits.

Referring now toFIGS. 1A-1I, an embodiment method of forming a PoP device10(FIGS. 2-4) is collectively illustrated. As shown inFIG. 1A, glue12or another suitable bonding material is deposited or formed on a carrier14. In an embodiment, the carrier14is formed from glass, silicon, a material having a low coefficient of thermal expansion, or another suitable carrier material. Indeed, the carrier14is generally a higher modulus material with good stiffness.

Referring now toFIG. 1B, a substrate16is temporarily mounted on the carrier14using the glue12or other suitable bonding material. In an embodiment, the substrate16is an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, or a laminate substrate having or supporting metal interconnects18or metallization. In an embodiment, the substrate16is formed from an epoxy, a resin, or another material.

Referring now toFIG. 1C, in an embodiment a pressure anneal is performed after the substrate16has been temporarily mounted on the carrier14as shown inFIG. 1B. The pressure anneal generally biases the substrate16toward the carrier14. This ensures that the substrate16is securely mounted, albeit temporarily, on the carrier14. In an embodiment, the pressure anneal ofFIG. 1Cis performed using a pressure anneal cap20along with heating. In an embodiment, pressure anneal may be performed later in the embodiment method illustrated inFIGS. 1A-1I. For example, the pressure anneal may be performed on a wafer, on a panel, on a single unit, or on multiple units. In addition, in an embodiment the pressure anneal includes pressure only without the application of heat.

Referring now toFIG. 1D, after the pressure anneal cap20ofFIG. 1Chas been removed, a first die22is attached to the substrate16using, for example, solder balls and corresponding contact pads. The first die22may include logic components (a logic integrated circuit, analog circuit, etc.), a memory component, and so on. The substrate16and/or the die22generally have a material coefficient of thermal expansion mismatch relative to the carrier14. As will be more fully explained below, any warping of, for example, dies or other semiconductor structures stacked on or over the substrate16is inhibited or prevented.

After placing the first die22, an underfill material24may be flowed between the first die22and the substrate16. In an embodiment, the underfill material24is omitted between the first die22and the substrate16.

Referring now toFIG. 1E, after the first die22has been mounted, a second die26is attached over the first die22using, for example, solder balls and corresponding contact pads. The second die26may include logic components (a logic integrated circuit, analog circuit, etc.), a memory component, and so on. Notably, the stacking of the second die26upon the first die22generally forms the PoP devices10.

After placing the second die26as shown inFIG. 1E, an underfill material24may be flowed between the second die26and the first die22. In an embodiment, the underfill material24is omitted. As will be more fully explained below, in an embodiment the second die26may be horizontally offset relative to the first die22to provide the second die26with an overhang.

Referring now toFIG. 1F, after the second die26has been mounted, a molding material28is formed over, for example, exposed portions of the substrate16, the first die22, and the second die26. In an embodiment, the molding material28is also formed over the glue12disposed on the carrier14and adjacent to the substrate16. In an embodiment, the molding material28generally encapsulates the first and second dies22,26.

Referring now toFIG. 1G, after the molding material28has been formed over the first and second dies22,26, a grinding process is performed to remove an upper portion of the molding material28. As shown, the grinding process may expose a top surface of the second die26. However, in an embodiment, the grinding process may leave a portion or thin layer of the molding material28disposed over the second die26.

Referring now toFIG. 1H, after the grinding process has been performed, the assembly is flipped over and a de-bonding process is performed to remove the carrier14from the substrate16. In addition, a cleaning process is performed to remove the glue12from the substrate16and the molding material28. Once the de-bonding and cleaning processes have been performed, contact pads from the metal interconnects18of the substrate16are exposed.

Referring now toFIG. 1I, after the de-bonding and cleaning processes have been performed, a ball mount process is performed to form an array of solder balls30on the contact pads from the metal interconnects18of the substrate16. In addition, a wafer saw process is performed to separate the PoP devices10from each other. As shown inFIG. 1I, after the wafer saw process a portion of the molding material28still covers the sidewalls32of the substrate16. However, in an embodiment the wafer saw process removes the molding material28from the sidewalls32of the substrate16.

Referring toFIG. 2, an embodiment PoP device10formed using an embodiment method is illustrated. As shown, the PoP device10includes a first die22stacked on the substrate16and a second die26stacked on the first die22. In an embodiment, the second die26is horizontally offset relative to the first die22to provide the second die26with the overhang34noted above.

In an embodiment, the underfill material24is disposed between the substrate16and the first die22as well as between the first die22and the second die26. In an embodiment, the underfill material24is disposed between the substrate16and the first die22only. In an embodiment, the underfill material24is disposed between the first die22and the second die26only. In addition, the molding material28of the PoP device10has been formed around portions of the substrate16, the first die22, and the second die26. In an embodiment, the molding material28is omitted.

Still referring toFIG. 2, the substrate16of the PoP device10supports metal interconnects18and/or other connection structures (e.g., under bump metallization) used to electrically couple the solder balls30(i.e., the ball grid array) to the first die22. The PoP device10may also include other structures, layers, or materials such as, for example, passivation layers, through silicon vias (TSVs), aluminum pads, solder, and so on.

Referring now toFIG. 3, in an embodiment the underfill material24ofFIG. 2has been omitted from the PoP device10and replaced by the molding material28. In other words, the molding material28functions or preforms as an underfill in the embodiment PoP device10ofFIG. 3.

Referring now toFIG. 4, in an embodiment the molding material28is left off or removed from sidewalls32of the substrate16. By way of example, the molding material28may not be formed on the sidewalls32when the molding material28is deposited during the molding process ofFIG. 1F. In other words, the molding material28is prevented from forming on the sidewalls32. In another example, the molding material28may be removed from the sidewalls32of the substrate16using the wafer saw process ofFIG. 1I. In other words, the wafer saw removes the molding material28from the sidewalls32.

It should be recognized that the embodiment methods and PoP device10provide numerous advantages. Indeed, by using the carrier14during the stacking of dies22,26warping is inhibited or prevented, even when relatively thin dies are stacked. In addition, multiple dies may be stacked, either with or without an overhang.

An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die.

An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a plurality of dies over the substrate, at least one of the plurality of dies and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and removing the carrier after the plurality of dies have been stacked.

A embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the first die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, stacking a second die on the first die, the second die horizontally offset relative to the first die to provide the second die with an overhang, and flowing an underfill material between the first die and the substrate and between the first die and the second die.