STRUCTURES AND METHODS FOR LARGE INTEGRATED CIRCUIT DIES

Disclosed herein are structures and methods for large integrated circuit (IC) dies, as well as related assemblies and devices. For example, in some embodiments, an IC die may include: a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die; a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die; and a third subvolume including electrical pathways between the first subvolume and the second subvolume; wherein the IC die has an area greater than 750 square millimeters.

BACKGROUND

Integrated circuit (IC) dies are typically formed in an array on a semiconductor wafer, then separated by singulation.

DETAILED DESCRIPTION

Disclosed herein are structures and methods for large integrated circuit (IC) dies, as well as related assemblies and devices. For example, in some embodiments, an IC die may include: a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die; a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die; and a third subvolume including electrical pathways between the first subvolume and the second subvolume; wherein the IC die has an area greater than 750 square millimeters.

Complex computing devices may require a large number of different computing components, such as processing devices, memory, sensors, and controllers. Conventionally, each of these components is manufactured and packaged separately, then the separate components are coupled together to form the computing device. However, utilizing separately packaged components may limit how close interacting components may be positioned to each other, and thus limit the speed with which the components can interact. Further, a manufacturer of one component may need to utilize a packaged component from another manufacturer, and thus there may be a limit on how tightly the design and operation of the components may be coupled (and thus an associated limit on performance).

Integrating multiple different ones of such computing components into a single die may reduce latency and allow for tighter coupling during the design phase, but existing photolithographic techniques and related fabrication processes have been limited in the size of dies that can be reliably fabricated. For example, existing photolithographic techniques that are suitable for high volume manufacturing (HVM) utilize photomasks (also called “reticles”) that can pattern an area having lateral dimensions no greater than 22 millimeters by 33 millimeters, the limit of currently commonly available lithography tools. This has meant that an IC die fabricated using such techniques may have lateral dimensions no greater than 22 millimeters by 33 millimeters. This limitation in the area of an IC die also limits the number and type of circuits that can be included in a single IC die. Conventionally, an array of such dies are formed on a semiconductor wafer, then separated into individual dies by cutting the wafer along scribe streets between adjacent dies.

Disclosed herein are structures and methods for forming IC dies larger than those conventionally achievable using HVM lithography techniques (referred to herein as “large IC dies”). Such large IC dies may include subvolumes having different functionality and/or structure, reducing latency relative to conventional assemblies of separately packaged dies, and/or providing more computing power in a single die. The large IC dies disclosed herein may be stacked with other dies to form IC die assemblies, further increasing functionality.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a “package” and an “IC package” are synonymous. When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. For convenience, the phrase “FIG. 1” may be used to refer to the collection of drawings ofFIGS. 1A-1C, the phrase “FIG. 4” may be used to refer to the collection of drawings ofFIGS. 4A-4B, etc.

FIG. 1illustrates an example large IC die100. In particular,FIG. 1Ais a top view of the large IC die100, andFIG. 1Bis a side, cross-sectional view through the section A-A ofFIG. 1A. The large IC die100includes a subvolume102-1and a subvolume102-2spaced laterally apart from the subvolume102-1. The subvolume102-1may be formed using a first set of photomasks, and the lateral dimensions120and122of the subvolume102-1may be limited to the lateral dimensions achievable using conventional HVM photolithography. For example, the lateral dimension120may be 22 millimeters or less and the lateral dimension122may be 33 millimeters or less (or vice versa). The lateral dimensions of the subvolume102-2may be similarly constrained.

As shown inFIG. 1B, the subvolume102-1and the subvolume102-2may extend through various regions of the large IC die100. In particular, the large IC die100may include top conductive contacts110, a top metallization stack108, a device layer106, a bottom metallization stack112, and bottom conductive contacts114. As used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket). The subvolume102-1(second subvolume102-2) may include a first portion110-1(second portion110-2) of the top conductive contacts110, a first portion108-1(second portion108-2) of the top metallization stack108, a first portion106-1(second portion106-2) of the device layer106, a first portion112-1(second portion112-2) of the bottom metallization stack112, and a first portion114-1(second portion114-2) of the bottom conductive contacts114.

The large IC die100may include one or more device layers106. Although only a single device layer106is depicted inFIG. 1(andFIG. 2, discussed below), this is simply for ease of illustration, and the large IC die100may include more than one device layer106. The device layer106may include features of one or more transistors (e.g., the transistors1640discussed below with reference toFIG. 2) or other devices. Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices of the device layer106and/or other devices embedded in the large IC die100through the metallization stacks108and112disposed on the device layer106. As discussed further below with reference toFIG. 2, the metallization stacks108and112may include conductive material arranged (e.g., in conductive vias and lines) to act as electrical pathways through the large IC die100. The top conductive contacts110and the bottom conductive contacts114may provide contact points for electrical connections to be made between the large IC die100and other components (e.g., other dies, interposers, package substrates, etc.), as discussed further herein.

The large IC die100may also include a stitching subvolume104. The stitching subvolume104may include electrical pathways between the subvolume102-1and the subvolume102-2, and thus may electrically “stitch” circuitry of the subvolume102-1with circuitry of the subvolume102-2. As illustrated inFIG. 1B, the stitching subvolume104may include a third portion110-3of the top conductive contacts110, a third portion108-3of the top metallization stack108, a third portion106-3of the device layer106, a third portion112-3of the bottom metallization stack112, and a third portion114-3of the bottom conductive contacts114. In some embodiments, the third portion106-3of the device layer106(part of the stitching subvolume104) may not include any active devices (e.g., may not include any transistors); in such embodiments, the stitching subvolume104may principally provide electrical pathways between the subvolume102-1and the subvolume102-2via the third portion108-3of the top metallization stack108and/or the third portion112-3of the bottom metallization stack112. In other embodiments, the third portion106-3of the device layer106may include active devices. In some embodiments, the stitching subvolume104may not include any top conductive contacts110and/or bottom conductive contacts114.

In some embodiments, layers of the metallization stack108closest to the device layer106may include electrical pathways (e.g., conductive vias and lines) in the first portion108-1and the third portion108-3, but may not include electrical pathways in the second portion108-2(the portion of the metallization stack108in the stitching subvolume104); the electrical pathways in the layers of the metallization stack108closest to the device layer106(in the first portion108-1and the third portion108-3) may be electrical coupled by electrical pathways in the second portion108-2in layers “higher up” in the metallization stack108. For example,FIG. 1Cis a side view of an embodiment in which the portions of the top metallization stack108are shown as having “upper” and “lower” regions; the first portion108-1of the metallization stack108has an upper region108-11and a lower region108-12, the second portion108-2of the metallization stack108has an upper region108-21and a lower region108-22, and the third portion108-3of the metallization stack108has an upper region108-31and a lower region108-32. The lower regions108-x2may include one or more layers of the metallization stack108, and these one or more layers may be between the device layer106and one or more layers of the layers of the metallization stack in the corresponding upper regions108-x1. In some embodiments, the lower regions108-12and108-32may include electrical pathways, while the lower region108-22(of the stitching subvolume104) may not include any electrical pathways; electrical pathways between the subvolume102-1and the subvolume102-2through the stitching subvolume104may be made through the upper region108-21of the second portion108-2of the metallization stack108. In some such embodiments, the second portion106-2of the device layer106may not include any devices. Such embodiments may be fabricated by first fabricating the device layer106, then fabricating the electrical pathways in the lower regions108-12and108-32, then fabricating the electrical pathways in the upper region108-21(and in the upper regions108-11and108-31, as appropriate).

While the subvolume102-1and the subvolume102-2may have lateral dimensions that are achievable with conventional lithography (e.g., less than or equal to 22 millimeters by 33 millimeters), the subvolume102-1, the subvolume102-2, and the stitching subvolume104may together form a large IC die100whose lateral dimensions are larger than those achievable using conventional lithography. For example, in some embodiments, a large IC die100may have a lateral area (i.e., the product of the lateral dimensions116and118) that is greater than 750 square millimeters (e.g., greater than 1500 square millimeters, greater than 3000 square millimeters, or greater than 6000 square millimeters). In some embodiments, the large IC die100may have at least one lateral dimension116or118that is greater than 33 millimeters (e.g., greater than 66 millimeters, greater than 99 millimeters, or greater than 132 millimeters).

Different ones of the subvolumes102in a large IC die100may include different types and/or arrangements of electrical structures. In some embodiments, the subvolume102-1may include transistors (e.g., the transistors1640discussed below with reference toFIG. 2) having a first structure and the subvolume102-2may include transistors having a second structure different from the first structure. For example, the subvolume102-1may include planar transistors in the device layer (e.g., the device layer106or another device layer) and the subvolume102-2may include non-planar transistors in the device layer. Examples of non-planar transistors may include dual-gate transistors, tri-gate transistors, or all-around gate transistors (e.g., nanoribbon transistors or nanowire transistors). Utilizing two different types of transistors in different ones of the subvolumes102of a large IC die may allow the transistor type to be tailored to the functional circuitry of which it is a part. For example, planar transistors may be particularly useful for high voltage I/O or logic circuitry, while non-planar transistors (e.g., dual-gate or tri-gate transistors) may be particularly useful for processing unit logic circuitry (e.g., in a central processing unit (CPU)). In another example, the subvolume102-1may include dual-gate transistors and the subvolume102-2may include tri-gate transistors.

In another example, the transistors in the subvolume102-1and the transistors in the subvolume102-2may be of the same type (e.g., planar, dual-gate, tri-gate, etc.) but parameters of those transistors may differ between the subvolumes102. For example, the transistors (e.g., the transistors1640discussed below with reference toFIG. 2) in the subvolume102-1and the transistors in the subvolume102-2may be planar transistors, but the transistors in the subvolume102-1may have a different channel thickness and/or gate length than the transistors in the subvolume102-2. In another example, the transistors in the subvolume102-1and the transistors in the subvolume102-2may be dual-gate transistors (or tri-gate transistors), but the transistors in the subvolume102-1may have a different gate length, fin height, and/or fin width than the transistors in the subvolume102-2. Utilizing the same type of transistors, but with different dimensions, in different ones of the subvolumes102of a large IC die may allow the transistor characteristics to be tailored to the functional circuitry of which it is a part. For example, FinFETs having a lower fin height may be well-suited for lower power circuitry (e.g., logic with lower performance) and FinFETS having a higher fin height may be well-suited for higher power circuitry (e.g., logic with higher performance).

In some embodiments, different processing operations may be performed to electrical structures in different ones of the subvolumes102. For example, in some embodiments, the devices (e.g., the transistors1640discussed below with reference toFIG. 2) in the first portion106-1of the device layer106may be subjected to different local processing conditions (e.g., laser annealing or ion implantation) than the devices in the second portion106-2. Different types of processing may confer advantages to certain devices (e.g., may modify transistor performance or leakage properties), but may also incur significant process costs; selectively performing such processing in subvolumes102in which its advantages may be more fully realized may improve performance without incurring excessive cost.

In some embodiments, different ones of the subvolumes102of a large IC die100may include different functional circuitry. For example, the subvolume102-1may provide a processing unit (e.g., general logic for a CPU, such as a control unit, an arithmetic/logic unit, and/or a register storage area), while the subvolume102-2may provide a memory device (e.g., a dynamic random access memory (DRAM) array, including storage cells, sense amplifiers, and word lines, or a static random access memory (SRAM) array).

In some embodiments, the structures of the electrical pathways in the metallization stacks108and/or112in different ones of the subvolumes102of a large IC die100may be different. For example, different materials may be used in some of the conductive vias and/or lines (e.g., the conductive lines1628aand the conductive vias1628bdiscussed below with reference toFIG. 2) of the first portion108-1of the metallization stack108(first portion112-1of the metallization stack112) relative to some of the conductive vias and/or lines of the second portion108-2of the metallization stack108(second portion112-2of the metallization stack112). In one particular example, some or all conductive vias of the first portion108-1(first portion112-1) may include tungsten (e.g., as a fill material) and some or all conductive vias of the second portion108-2(second portion112-2) may include copper (e.g., as a fill material). In another example, the conductive vias and/or lines in different ones of the subvolumes102of a large IC die100may have different dimensions; for example, some of the conductive lines in the subvolume102-1may be thicker than conductive lines in the corresponding layer of the subvolume102-2.

In some embodiments, different ones of the subvolumes102in a large IC die100may share a number of layers having the same structure, and then may have a set of layers that differ. For example, the subvolumes102-1and102-2may have a first set of layers in the metallization stack108(the metallization stack112) that have the same structure between the subvolumes102-1and102-2(e.g., the first ten layers) and a second set of layers in the metallization stack10(the metallization stack112) that are different. In such embodiments, a same set of photomasks may be used to pattern the first set of layers of the subvolume102-1and the first set of layers of the subvolume102-2, and different sets of photomasks may be used to pattern the second set of layers of the subvolume102-1and the second set of layers of the subvolume102-2. In some embodiments, the different second set of layers of the subvolume102-1and the subvolume102-2may be used to pattern special electrical structures, such as a capacitor (e.g., a metal-insulator-metal capacitor), copper bumps, or a magnetic material (e.g., in an inductor). In some embodiments, the different second set of layers of the subvolume102-1and the subvolume102-2may be used to achieve different dimensions of the conductive lines and/or vias in the subvolume102-1and the subvolume102-2(e.g., to form thicker conductive lines in the subvolume102-1or the subvolume102-2, as discussed above).

Although only two subvolumes102and one stitching subvolume104are depicted inFIG. 1, this is simply for ease of illustration, and the techniques and structures disclosed herein may be used to “stitch” together any desired number and arrangement of subvolumes102with stitching subvolumes104to form a large IC die100. Different ones of the subvolumes102in a large IC die100may have the same structure or different structures (e.g., in accordance with any of the embodiments discussed herein). A number of example large IC dies100with various arrangements of subvolumes102and stitching subvolumes104are illustrated herein. In some embodiments, the techniques and structures disclosed herein may be used to form a large IC die100whose lateral dimensions are equal or approximately equal to the lateral dimensions of the semiconductor wafer underlying the large IC die100.

The large IC die100illustrated inFIG. 1Bis a “double-sided” die in that the large IC die100includes top conductive contacts110at one face and bottom conductive contacts114at the opposite face, allowing electrical connections to the large IC die100to be made at both faces. In some embodiments, the large IC dies100disclosed herein may only be “single-sided,” having only a set of conductive contacts at a single face (e.g., the conductive contacts110or the conductive contacts114). Double-sided large IC dies100may be depicted in various ones of the accompanying drawings for illustrative purposes, but any suitable ones of the large IC dies100disclosed herein may be single-sided.

FIG. 2is a side, cross-sectional view showing example details of a large IC die100. The elements illustrated in and discussed below with reference toFIG. 2may be embodiments of any of the corresponding elements discussed above with reference toFIG. 1(or others of the accompanying figures).FIG. 2also illustrates a subvolume102-1, a subvolume102-2, and a stitching subvolume104that provides conductive pathways between the subvolume102-1and the subvolume102-2. In the embodiment ofFIG. 2, no transistors1640are illustrated in the stitching subvolume104; in various embodiments, the stitching subvolume104may or may not include transistors1640or other active devices.

The large IC die100may include a substrate1602(e.g., the wafer1500ofFIG. 11). The substrate1602may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The substrate1602may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate1602may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the substrate1602. Although a few examples of materials from which the substrate1602may be formed are described here, any material that may serve as a foundation for the large IC die100may be used. In some embodiments, the substrate1602may be glass. The substrate1602may be part of a singulated die (e.g., the dies1502ofFIG. 11) or a wafer (e.g., the wafer1500ofFIG. 11).

The device layer106may include features of one or more transistors1640(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on an/or in the substrate1602. The device layer106may include, for example, one or more source and/or drain (S/D) regions1620, a gate1622to control current flow in the transistors1640between the S/D regions1620, and one or more S/D contacts1624to route electrical signals to/from the S/D regions1620. The transistors1640may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors1640are not limited to the type and configuration depicted inFIG. 2and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Planar transistors may include bipolar junction transistors (BJT), heterojunction bipolar transistors (HBT), or high-electron-mobility transistors (HEMT). Non-planar transistors may include FinFET transistors, such as dual-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon transistors or nanowire transistors.

The S/D regions1620may be formed within the substrate1602adjacent to the gate1622of each transistor1640. The S/D regions1620may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate1602to form the S/D regions1620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate1602may follow the ion-implantation process. In the latter process, the substrate1602may first be etched to form recesses at the locations of the S/D regions1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions1620. In some implementations, the S/D regions1620may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions1620may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions1620.

As noted above, electrical signals may be routed to and/or from the devices (e.g., the transistors1640) of the device layer106, or other electrical components included in the large IC die100, through electrically conductive structures1628in the metallization stacks108and112. The electrically conductive structures1628may be arranged within the metallization stacks108and112to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of electrically conductive structures1628depicted inFIG. 2). Although a particular number of layers is depicted in each of the metallization stacks108and112ofFIG. 2, embodiments of the present disclosure include large IC dies100having more or fewer metallization stack layers than depicted.

In some embodiments, the electrically conductive structures1628may include lines1628aand/or vias1628bfilled with an electrically conductive material such as a metal. The lines1628amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate1602upon which the device layer106is formed. For example, the lines1628amay route electrical signals in a direction in and out of the page from the perspective ofFIG. 2. The vias1628bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate1602upon which the device layer106is formed. In some embodiments, the vias1628bmay electrically couple lines1628aof different layers in a metallization stack together. Although the lines1628aand the vias1628bare structurally delineated with a line within a layer for the sake of clarity, the lines1628aand the vias1628bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments. In some embodiments, the metallization stack layers that are “higher up” (i.e., farther away from the device layer106) may be thicker. In some embodiments, a through-substrate via1628bmay extend through the substrate1602to connect the device layer106and/or the top metallization stack108with the bottom metallization stack112in embodiments in which the large IC die100is double-sided.

The metallization stacks108and112may include a dielectric material1626disposed between the electrically conductive structures1628, as shown inFIG. 2. In some embodiments, the dielectric material1626disposed between the electrically conductive structures1628in different ones of the layers of the metallization stacks108and112may have different compositions; in other embodiments, the composition of the dielectric material1626between different layers of the metallization stacks108and112may be the same.

The top conductive contacts110and the bottom conductive contacts114may be conductive contacts formed on the metallization stacks108and112, respectively, and spaced apart by a solder resist material1634(e.g., polyimide or similar material). InFIG. 10, the conductive contacts are illustrated as taking the form of bond pads. The conductive contacts110and/or114may be electrically coupled with the electrically conductive structures1628and configured to route the electrical signals of the transistor(s)1640or other electrical elements of the large IC die100to other external devices. For example, solder bonds may be formed on the one or more conductive contacts110and/or114to mechanically and/or electrically couple the large IC die100with another component (e.g., another die or a package substrate, as discussed further below). The large IC die100may include additional or alternate structures to route the electrical signals from the metallization stacks108or112; for example, the conductive contacts110or114may include other analogous features (e.g., posts) that route the electrical signals to external components.

As noted above, in embodiments in which a large IC die100is double-sided, one or more other IC dies may be coupled to the top conductive contacts110and/or the bottom conductive contacts114. For example,FIG. 3is a side, cross-sectional view of an IC assembly200including a large IC die100and two other IC dies150coupled to the top conductive contacts110of the large IC die100. Although the large IC die100ofFIG. 3is illustrated as including two subvolumes102and a stitching subvolume104, the large IC die100may take the form of any of the large IC dies100disclosed herein.

Conductive contacts1654of the IC dies150may be coupled to the large IC die100by first-level interconnects1658. The first-level interconnects1658illustrated inFIG. 3are solder bumps, but any suitable first-level interconnects1658may be used. First-level interconnects1665may be present on the conductive contacts114of the large IC die100; the first-level interconnects1665may be used to couple the large IC die100to a package substrate (e.g., as discussed further below with reference toFIG. 12), to an interposer, or to another IC die.

Although the IC dies150are depicted in various ones of the accompanying figures as coupled to conductive contacts110of the subvolumes102of the large IC die100, this is simply illustrative, and IC dies150may be coupled to conductive contacts110of a stitching subvolume104, as suitable. Further, although the large IC die100is depicted in various ones of the accompanying figures as having the IC dies150coupled to the conductive contacts110, this is simply illustrative, and IC dies150may be coupled to the conductive contacts114instead of or in addition to the conductive contacts110(and the conductive contacts110may be coupled to a package substrate or an interposer, as desired).

In some embodiments, an IC assembly200may include the more complex (and therefore lower yield) structures in the smaller IC dies150while locating the less complex (and therefore higher yield) structures in the large IC die100. The size of a large IC die100may mean that it is costly to manufacture, and thus a loss of such a die may be expensive; fabricating the large IC die100with more reliably manufactured electrical structures may reduce the likelihood that the large IC die100will fail to meet performance requirements and will be counted as a loss. Examples of electrical structures that may be suitable for inclusion in the large IC die100of an IC assembly200may include power delivery structures, DRAM, SRAM, camera sensors, and high yield, low density logic.

FIGS. 4-6illustrate various arrangements of the large IC die100and the other IC dies150in example IC assemblies200. For example,FIG. 4illustrates an IC assembly200having multiple IC dies150coupled to a large IC die100;FIG. 4Ais a top view, andFIG. 4Bis a side, cross-sectional view through the section A-A ofFIG. 4A. In the IC assembly200ofFIG. 4, the large IC die100has four subvolumes102-1,102-2,102-3, and102-4arranged in an array and “stitched” together by intervening stitching subvolumes104-1,104-2, and104-3, as shown. The IC dies150-1,150-2,150-3, and150-4are coupled to conductive contacts110of the subvolumes102-1,102-2,102-3, and102-4, respectively. Elements of the IC assembly200may take the form of corresponding elements ofFIG. 2, for example.

In some embodiments of the IC assembly200ofFIG. 4, the subvolumes102of the large IC die100may include memory devices, such as SRAM. In some embodiments, one or more of the subvolumes102of the large IC die100may also include router circuitry. The IC die150-1may be a logic die, and the IC dies150-2may be artificial intelligence (AI) dies, such as deep neural network (DNN) dies. The IC dies150-3may be high bandwidth memory (HBM) dies (e.g., dies in accordance with the HBM or HBM2 standard). Such an embodiment of the IC assembly200may provide an AI processing assembly, and may be packaged into an IC package (e.g., as discussed below with reference to the IC package1650ofFIG. 12). In some embodiments, the lateral dimension118of the large IC die100ofFIG. 4may be between 40 millimeters and 60 millimeters (e.g., between 44 millimeters and 58 millimeters). In some embodiments, the lateral dimension116of the large IC die100ofFIG. 4may be between 30 millimeters and 40 millimeters (e.g., between 32 millimeters and 35 millimeters). The area of the IC dies150-1and150-2may be between 200 square millimeters and 250 square millimeters, and the area of the IC dies150-3may be between 80 square millimeters and 100 square millimeters.

FIG. 5illustrates an IC assembly200having multiple IC dies150coupled to a large IC die100;FIG. 5Ais a top view of the IC assembly, omitting details of the large IC die100, andFIG. 5Bis a top view of the large IC die100. In the IC assembly200ofFIG. 5, the large IC die100has many subvolumes102“stitched” together by intervening stitching subvolumes104, as shown. The IC dies150are coupled to conductive contacts (not shown) of the large IC die100(e.g., as discussed above with reference toFIG. 3). Elements of the IC assembly200ofFIG. 5may take the form of corresponding elements ofFIG. 2, for example.

In some embodiments of the IC assembly200ofFIG. 5, the IC dies150may be HBM dies, the subvolumes102-1may be computing clusters, the subvolumes102-2may be serializer/deserializer (SERDES) circuitry, the subvolumes102-3may be HBM controller circuitry (e.g., I/O circuitry for the HBM IC dies150), and the subvolume102-4may be bus circuitry (e.g., Peripheral Component Interconnect Express (PCIe) circuitry). Stitching subvolumes104may be arranged in any suitable manner between the subvolumes102of the large IC die100to achieve a desired pattern of connectivity between the subvolumes102. In some embodiments, the lateral dimension of the subvolumes102-1may be between 4 square millimeters and 6 square millimeters. Although a particular number of subvolumes102-1and IC dies150are illustrated inFIG. 5, an IC assembly200may include more or fewer components (e.g., more than 64 subvolumes102-1). Such an embodiment of the IC assembly200may provide an AI processing assembly, and may be packaged into an IC package (e.g., as discussed below with reference to the IC package1650ofFIG. 12).

FIG. 6is a top view of an IC assembly having multiple IC dies150coupled to a large IC die100. In the IC assembly200ofFIG. 6, the large IC die100has many subvolumes102“stitched” together by intervening stitching subvolumes104, as shown. The IC dies150are coupled to conductive contacts (not shown) of the large IC die100(e.g., as discussed above with reference toFIG. 3). Elements of the IC assembly200ofFIG. 6may take the form of corresponding elements ofFIG. 2, for example. In some embodiments of the IC assembly200ofFIG. 6, the IC dies150may be HBM dies, the subvolumes102-1may be logic circuitry, the subvolumes102-2may be memory devices (e.g., SRAM), and the subvolumes102-3may include HBM controller circuitry.

As noted above, although particular types and arrangements of subvolumes102and stitching subvolumes104are illustrated herein, a large IC die100may include any suitable types and arrangements of subvolumes102and stitching subvolumes104. For example,FIG. 7is a top view of another example large IC die100, including a number of different subvolumes102and stitching subvolumes104. One or more of the subvolumes102(and/or stitching subvolumes104) may be patterned using the same photomask sets or different photomask sets, as discussed herein.

Any suitable manufacturing process may be used to fabricate the large IC dies100disclosed herein. For example,FIGS. 8A-8Cillustrate stages in an example process of manufacturing a large IC die100, in accordance with various embodiments.FIG. 8Ais a top view of an assembly500subsequent to forming features260in a first region160of an assembly170using a first set of photomasks (and any suitable associated processes, such as deposition, polishing, desmear, etc.). The assembly170may be the substrate1602(e.g., when forming the device layer106) or any other stage during the fabrication of the large IC die100.

FIG. 8Bis a top view of an assembly502subsequent to forming features262in a second region162of the assembly502(FIG. 8A) using a second set of photomasks (and any suitable associated processes). In some embodiments, the first set of photomasks may be the same as the second set of photomasks (and thus the features260may be the same as the features262), while in other embodiments, the first set of photomasks may be different than the second set of photomasks (and thus the features260may be different than the features262).

FIG. 8Cis a top view of an assembly504subsequent to forming features264in a third region164of the assembly502(FIG. 8B) using a third set of photomasks (and any suitable associated processes). The features264may electrically “stitch” some of the features260of the first region160with some of the features262of the second region162. The operations ofFIGS. 8A-8Cmay be repeated so that the features formed in the first region160provide the subvolume102-1, the features formed in the second region162provide the subvolume102-2, and the features formed in the third region164provide the stitching subvolume104of a large IC die100.

FIGS. 9A-9Cillustrate stages in an example process of manufacturing a large IC die100, in accordance with various embodiments.FIG. 9Ais a top view of an assembly510subsequent to forming features266in a first region160and in a second region162of an assembly170using a first set of photomasks (and any suitable associated processes, such as deposition, polishing, desmear, etc.), and forming features265in a third region164of the assembly170using a second set of photomasks (and any suitable associated processes). The features265may electrically “stitch” some of the features266of the first region160with some of the features266of the second region162. The features266may be formed in the first region160and in the second region162in parallel, or in series, as suitable. The assembly170may take any of the forms discussed above with reference toFIG. 9A.

FIG. 9Bis a top view of an assembly512subsequent to forming features268in the first region160of the assembly510(FIG. 9A) using a third set of photomasks (and any suitable associated processes), and forming features270in the second region162of the assembly510(FIG. 9A) using a fourth set of photomasks (and any suitable associated processes). The third set of photomasks may be different than the fourth set of photomasks (and thus the features268may be different than the features270).

FIG. 9Cis a top view of an assembly514subsequent to forming features272in the third region164of the assembly512(FIG. 9B) using a fifth set of photomasks (and any suitable associated processes). The features272may electrically “stitch” some of the features268of the first region160with some of the features270of the second region162. The operations ofFIGS. 9A-9Cmay be repeated (and modified as suitable) so that the features in the first region160provide the subvolume102-1, the features formed in the second region162provide the second subvolume102-2, and the features formed in the third region164provide the stitching subvolume104of a large IC die100.

FIG. 10is a flow diagram of an example method1000of manufacturing a large IC die, in accordance with various embodiments. Although the operations of the method1000may be illustrated with reference to particular embodiments of the large IC dies100disclosed herein, the method1000may be used to form any suitable large IC die. Operations are illustrated once each and in a particular order inFIG. 10, but the operations may be reordered and/or repeated as desired (e.g., with different operations performed in parallel when manufacturing multiple electronic components simultaneously). For example, the operations of1002,1004, and1006may be performed in an interleaved manner, with portions of the first die subvolume, the second die subvolume, and the third die subvolume being fabricated alternatingly.

At1002, a first die subvolume may be formed. The first die subvolume may take the form of any of the subvolumes102disclosed herein, and may be formed using any of the techniques disclosed herein.

At1004, a second die subvolume may be formed. The second die subvolume may take the form of any of the subvolumes102disclosed herein, and may be formed using any of the techniques disclosed herein.

At1006, a third die subvolume may be formed. The third die subvolume may include electrical pathways that electrically couple devices in the first die subvolume with devices in the second die subvolume to form a large die. The third die subvolume may take the form of any of the stitching subvolumes104disclosed herein, and may be formed using any of the techniques disclosed herein. The large die may take the form of any of the large IC dies100disclosed herein, for example.

The large IC dies100disclosed herein may be included in any suitable electronic component.FIGS. 11-14illustrate various examples of apparatuses that may include any of the large IC dies100disclosed herein.

FIG. 11is a top view of a wafer1500and dies1502that may include one or more large IC dies100, or may be included in an IC package including one or more large IC dies100(e.g., as discussed below with reference toFIG. 12) in accordance with any of the embodiments disclosed herein. The wafer1500may be composed of semiconductor material or a non-semiconductor material, such as glass, and may include one or more dies1502having IC structures formed on a surface of the wafer1500. Each of the dies1502may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer1500may undergo a singulation process in which the dies1502are separated from one another to provide discrete “chips” of the semiconductor product. In some embodiments, the die1502may be the size of the entire wafer (e.g., when the die1502is a large IC die100), and thus no singulation may be required. The die1502may take the form of any of the large IC dies100or IC dies150disclosed herein. In some embodiments, the wafer1500or the die1502may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die1502. For example, a memory array formed by multiple memory devices may be formed on a same die1502as a processing device (e.g., the processing device1802ofFIG. 14) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG. 12is a side, cross-sectional view of an example IC package1650that may include one or more large IC dies100. In particular,FIG. 12illustrates an IC package1650including the IC assembly200ofFIG. 3; other elements (not shown) may also be included in the IC package1650. In some embodiments, the IC package1650may be a system-in-package (SiP).

The package substrate1652may be formed of an organic dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the dielectric material between the face1672and the face1674, or between different locations on the face1672, and/or between different locations on the face1674. These conductive pathways may take the form of any of the electrically conductive structures1628discussed above with reference toFIG. 2. In some embodiments, the package substrate1652may be formed as a printed circuit board (PCB), as discussed below with reference toFIG. 13.

The package substrate1652may include conductive contacts1663that are coupled to conductive pathways1662through the package substrate1652, allowing circuitry within the IC dies150and/or the large IC die100to electrically couple to various ones of the conductive contacts1664. The large IC die100may be coupled to the conductive contacts1663of the package substrate1652by first-level interconnects1665. The first-level interconnects1665illustrated inFIG. 12are solder bumps, but any suitable first-level interconnects1665may be used.

In some embodiments, an underfill material1666may be disposed between the package substrate1652and the large IC die100around the first-level interconnects1665, and a mold compound1668may be disposed around the IC dies150and the large IC die100and in contact with the package substrate1652. In some embodiments, the underfill material1666may be the same as the mold compound1668. Example materials that may be used for the underfill material1666and the mold compound1668are epoxy mold materials, as suitable. Second-level interconnects1670may be coupled to the conductive contacts1664. The second-level interconnects1670illustrated inFIG. 12are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects16770may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects1670may be used to couple the IC package1650to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference toFIG. 13.

In embodiments in which the IC package1650includes multiple dies100/150, the IC package1650may be referred to as a multi-chip package (MCP). Although the IC package1650illustrated inFIG. 12is a flip chip package, other package architectures may be used. For example, the IC package1650may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package1650may be a wafer-level chip scale package (WLCSP) or a panel fanout (FO) package. Although a particular number of IC dies100/150are illustrated in the IC package1650ofFIG. 12, an IC package1650may include any desired number of dies100/150. An IC package1650may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face1672or the second face1674of the package substrate1652, or on either face of the large IC die100. More generally, an IC package1650may include any other active or passive components known in the art.

FIG. 13is a side, cross-sectional view of an IC device assembly1700that may include one or more IC packages including one or more large IC dies100, in accordance with any of the embodiments disclosed herein. The IC device assembly1700includes a number of components disposed on a circuit board1702(which may be, e.g., a motherboard). The IC device assembly1700includes components disposed on a first face1740of the circuit board1702and an opposing second face1742of the circuit board1702; generally, components may be disposed on one or both faces1740and1742. Any of the IC packages discussed below with reference to the IC device assembly1700may take the form of any of the embodiments of the IC package1650discussed above with reference toFIG. 12(e.g., may include one or more large IC dies100).

The IC device assembly1700illustrated inFIG. 13includes a package-on-interposer structure1736coupled to the first face1740of the circuit board1702by coupling components1716. The coupling components1716may electrically and mechanically couple the package-on-interposer structure1736to the circuit board1702, and may include solder balls (as shown inFIG. 13), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure1736may include an IC package1720coupled to a package interposer1704by coupling components1718. The coupling components1718may take any suitable form for the application, such as the forms discussed above with reference to the coupling components1716. Although a single IC package1720is shown inFIG. 13, multiple IC packages may be coupled to the package interposer1704; indeed, additional interposers may be coupled to the package interposer1704. The package interposer1704may provide an intervening substrate used to bridge the circuit board1702and the IC package1720. The IC package1720may be or include, for example, any of the dies disclosed herein. Generally, the package interposer1704may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the package interposer1704may couple the IC package1720(e.g., a die) to a set of BGA conductive contacts of the coupling components1716for coupling to the circuit board1702. In the embodiment illustrated inFIG. 13, the IC package1720and the circuit board1702are attached to opposing sides of the package interposer1704; in other embodiments, the IC package1720and the circuit board1702may be attached to a same side of the package interposer1704. In some embodiments, three or more components may be interconnected by way of the package interposer1704.

The IC device assembly1700may include an IC package1724coupled to the first face1740of the circuit board1702by coupling components1722. The coupling components1722may take the form of any of the embodiments discussed above with reference to the coupling components1716, and the IC package1724may take the form of any of the embodiments discussed above with reference to the IC package1720.

The IC device assembly1700illustrated inFIG. 13includes a package-on-package structure1734coupled to the second face1742of the circuit board1702by coupling components1728. The package-on-package structure1734may include an IC package1726and an IC package1732coupled together by coupling components1730such that the IC package1726is disposed between the circuit board1702and the IC package1732. The coupling components1728and1730may take the form of any of the embodiments of the coupling components1716discussed above, and the IC packages1726and1732may take the form of any of the embodiments of the IC package1720discussed above. The package-on-package structure1734may be configured in accordance with any of the package-on-package structures known in the art.

FIG. 14is a block diagram of an example electrical device1800that may include one or more large IC dies100, in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the electrical device1800may include one or more of the IC device assemblies1700, IC packages1650, or large IC dies100disclosed herein. A number of components are illustrated inFIG. 14as included in the electrical device1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device1800may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device1800may not include one or more of the components illustrated inFIG. 14, but the electrical device1800may include interface circuitry for coupling to the one or more components. For example, the electrical device1800may not include a display device1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device1806may be coupled. In another set of examples, the electrical device1800may not include an audio input device1824or an audio output device1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device1824or audio output device1808may be coupled. A housing (not shown) may be disposed around one or more components of the electrical device1800.

The electrical device1800may include battery/power circuitry1814. The battery/power circuitry1814may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device1800to an energy source separate from the electrical device1800(e.g., AC line power).

The electrical device1800may include a display device1806(or corresponding interface circuitry, as discussed above). The display device1806may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device1800may include an audio output device1808(or corresponding interface circuitry, as discussed above). The audio output device1808may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.

The electrical device1800may include an audio input device1824(or corresponding interface circuitry, as discussed above). The audio input device1824may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The electrical device1800may include a GPS device1818(or corresponding interface circuitry, as discussed above). The GPS device1818may be in communication with a satellite-based system and may receive a location of the electrical device1800, as known in the art.

The electrical device1800may include an other output device1810(or corresponding interface circuitry, as discussed above). Examples of the other output device1810may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

Example 1 is an integrated circuit (IC) die, including: a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die; a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die; and a third subvolume including electrical pathways between the first subvolume and the second subvolume; wherein the IC die has an area greater than 750 square millimeters.

Example 2 includes the subject matter of Example 1, and further specifies that the IC die has a lateral dimension greater than 33 millimeters.

Example 3 includes the subject matter of Example 2, and further specifies that the lateral dimension is a first lateral dimension, and the IC die also has a second lateral dimension greater than 22 millimeters.

Example 4 includes the subject matter of any of Examples 1-3, and further specifies that the IC die has a lateral dimension greater than 66 millimeters.

Example 5 includes the subject matter of any of Examples 1-4, and further specifies that the IC die has a lateral dimension greater than 99 millimeters.

Example 6 includes the subject matter of any of Examples 1-5, and further specifies that the IC die has an area greater than 1500 square millimeters.

Example 7 includes the subject matter of any of Examples 1-6, and further specifies that the IC die has an area greater than 3000 square millimeters.

Example 8 includes the subject matter of any of Examples 1-7, and further specifies that the devices in the first portion of the device layer of the IC die include planar transistors, and the devices in the second portion of the device layer of the IC die include non-planar transistors.

Example 9 includes the subject matter of Example 8, and further specifies that the devices in the second portion of the device layer of the IC die include tri-gate transistors.

Example 10 includes the subject matter of any of Examples 1-9, and further specifies that the devices in the first portion of the device layer of the IC die include dual-gate transistors, and the devices in the second portion of the device layer of the IC die include tri-gate transistors.

Example 11 includes the subject matter of any of Examples 1-10, and further specifies that the devices in the first portion of the device layer of the IC die include tri-gate transistors having a first fin height, the devices in the second portion of the device layer of the IC die include tri-gate transistors having a second fin height, and the first fin height is different than the second fin height.

Example 12 includes the subject matter of any of Examples 1-11, and further specifies that the devices in the first portion of the device layer of the IC die include transistors having a first structure, the devices in the second portion of the device layer of the IC die include transistors having a second structure, and the first structure is different than the second structure.

Example 13 includes the subject matter of any of Examples 1-12, and further specifies that the third subvolume includes a first set of metallization layers and a second set of metallization layers, the first set of metallization layers is between the second set of metallization layers and the device layer, and the first set of metallization layers does not include any electrical pathways.

Example 14 includes the subject matter of any of Examples 1-13, and further specifies that the first electrical structures provide a processing unit and the second electrical structures provide a memory device.

Example 15 includes the subject matter of Example 14, and further specifies that the memory device includes static random access memory (SRAM) devices.

Example 16 includes the subject matter of Example 14, and further specifies that the memory device includes dynamic random access memory (DRAM) devices.

Example 17 includes the subject matter of any of Examples 1-15, and further specifies that the first electrical structures include first conductive vias, the second electrical structures include second conductive vias, and the first conductive vias have a material composition different than a material composition of the second conductive vias.

Example 18 includes the subject matter of Example 17, and further specifies that the first conductive vias include tungsten.

Example 19 includes the subject matter of Example 18, and further specifies that the second conductive vias include copper.

Example 20 includes the subject matter of any of Examples 1-19, and further specifies that metallization of the first subvolume includes a first set of layers and a second set of layers, metallization of the second subvolume includes a first set of layers and a second set of layers, the first set of layers of the metallization of the first subvolume has a same structure as the first set of layers of the metallization of the second subvolume, and the second set of layers of the metallization of the first subvolume has a different structure than the second set of layers of the metallization of the second subvolume.

Example 21 includes the subject matter of Example 20, and further specifies that the first set of layers of the metallization of the first subvolume is between the second set of layers of the metallization of the first subvolume and the device layer, and the first set of layers of the metallization of the second subvolume is between the second set of layers of the metallization of the second subvolume and the device layer.

Example 22 includes the subject matter of any of Examples 20-21, and further specifies that the second set of layers of the metallization of the first subvolume includes a capacitor.

Example 23 includes the subject matter of Example 20, and further specifies that the second set of layers of the metallization of the first subvolume includes a magnetic material.

Example 24 includes the subject matter of any of Examples 1-23, and further specifies that at least some of the first electrical structures are laser annealed.

Example 25 includes the subject matter of Example 24, and further specifies that none of the second electrical structures are laser annealed.

Example 26 includes the subject matter of Example 24, and further specifies that the at least some of the first electrical structures have corresponding electrical structures in the second electrical structures, and the corresponding ones of the second electrical structures are not laser annealed.

Example 27 includes the subject matter of any of Examples 1-26, and further specifies that the IC die is an artificial intelligence (AI) die.

Example 28 includes the subject matter of any of Examples 1-27, and further specifies that the third subvolume is between the first subvolume and the second subvolume.

Example 29 includes the subject matter of any of Examples 1-28, and further specifies that the third subvolume includes metallization, a third portion of the device layer of the IC die is below the metallization of the third subvolume, and the third portion of the device layer of the IC die does not include any devices.

Example 30 includes the subject matter of any of Examples 1-29, and further specifies that metallization of the third subvolume connects metallization of the first subvolume with metallization of the second subvolume.

Example 31 includes the subject matter of any of Examples 1-30, and further includes: conductive contacts at a face of the IC die.

Example 32 includes the subject matter of Example 31, and further specifies that the face of the IC die is a first face, the IC die has a second face opposite the first face, and the IC die further includes: conductive contacts at the second face of the IC die.

Example 33 includes the subject matter of Example 32, and further specifies that the IC die includes electrical pathways between the device layer of the IC die and the conductive contacts at the first face of the IC die, and the IC die includes electrical pathways between the device layer of the IC die and the conductive contacts at the second face of the IC die.

Example 34 includes the subject matter of any of Examples 32-33, and further specifies that a pitch of the conductive contacts at the first face of the IC die is different from a pitch of the conductive contacts at the second face of the IC die.

Example 35 includes the subject matter of any of Examples 1-34, and further specifies that the IC die includes dynamic random access memory (DRAM) devices.

Example 36 includes the subject matter of any of Examples 1-35, and further specifies that the IC die includes static random access memory (SRAM) devices.

Example 37 includes the subject matter of any of Examples 1-36, and further specifies that the IC die includes power delivery devices.

Example 38 includes the subject matter of any of Examples 1-37, and further specifies that the IC die includes high bandwidth memory (HBM) controller circuitry.

Example 39 includes the subject matter of Example 38, and further specifies that the HBM controller circuitry is included in the first subvolume, and the second subvolume includes static random access memory (SRAM) devices.

Example 40 is an integrated circuit (IC) die assembly, including: a first IC die, including a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the first IC die, a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the first IC die, a third subvolume including electrical pathways between the first subvolume and the second subvolume, and conductive contacts at a top face of the first IC die; and a second IC die electrically coupled to the conductive contacts at the top face of the first IC die.

Example 41 includes the subject matter of Example 40, and further specifies that the first IC die has a lateral dimension greater than 33 millimeters.

Example 42 includes the subject matter of Example 41, and further specifies that the lateral dimension is a first lateral dimension, and the first IC die also has a second lateral dimension greater than 22 millimeters.

Example 43 includes the subject matter of any of Examples 40-42, and further specifies that the first IC die has a lateral dimension greater than 66 millimeters.

Example 44 includes the subject matter of any of Examples 40-43, and further specifies that the first IC die has a lateral dimension greater than 99 millimeters.

Example 45 includes the subject matter of any of Examples 40-44, and further specifies that the first IC die has an area greater than 1500 square millimeters.

Example 46 includes the subject matter of any of Examples 40-45, and further specifies that the first IC die has an area greater than 3000 square millimeters.

Example 47 includes the subject matter of any of Examples 40-46, and further specifies that the devices in the first portion of the device layer of the first IC die include planar transistors, and the devices in the second portion of the device layer of the first IC die include non-planar transistors.

Example 48 includes the subject matter of Example 47, and further specifies that the devices in the second portion of the device layer of the first IC die include tri-gate transistors.

Example 49 includes the subject matter of any of Examples 40-47, and further specifies that the devices in the first portion of the device layer of the first IC die include dual-gate transistors, and the devices in the second portion of the device layer of the first IC die include tri-gate transistors.

Example 50 includes the subject matter of any of Examples 40-48, and further specifies that the devices in the first portion of the device layer of the first IC die include tri-gate transistors having a first fin height, the devices in the second portion of the device layer of the first IC die include tri-gate transistors having a second fin height, and the first fin height is different than the second fin height.

Example 51 includes the subject matter of any of Examples 40-50, and further specifies that the devices in the first portion of the device layer of the first IC die include transistors having a first structure, the devices in the second portion of the device layer of the first IC die include transistors having a second structure, and the first structure is different than the second structure.

Example 52 includes the subject matter of any of Examples 40-51, and further specifies that the third subvolume includes a first set of metallization layers and a second set of metallization layers, the first set of metallization layers is between the second set of metallization layers and the device layer, and the first set of metallization layers does not include any electrical pathways.

Example 53 includes the subject matter of any of Examples 40-47, and further specifies that the first electrical structures provide a processing unit and the second electrical structures provide a memory device.

Example 54 includes the subject matter of Example 53, and further specifies that the memory device includes static random access memory (SRAM) devices.

Example 55 includes the subject matter of Example 53, and further specifies that the memory device includes dynamic random access memory (DRAM) devices.

Example 56 includes the subject matter of any of Examples 40-55, and further specifies that the first electrical structures include first conductive vias, the second electrical structures include second conductive vias, and the first conductive vias have a material composition different than a material composition of the second conductive vias.

Example 57 includes the subject matter of Example 56, and further specifies that the first conductive vias include tungsten.

Example 58 includes the subject matter of Example 57, and further specifies that the second conductive vias include copper.

Example 59 includes the subject matter of any of Examples 40-58, and further specifies that metallization of the first subvolume includes a first set of layers and a second set of layers, metallization of the second subvolume includes a first set of layers and a second set of layers, the first set of layers of the metallization of the first subvolume has a same structure as the first set of layers of the metallization of the second subvolume, and the second set of layers of the metallization of the first subvolume has a different structure than the second set of layers of the metallization of the second subvolume.

Example 60 includes the subject matter of Example 59, and further specifies that the first set of layers of the metallization of the first subvolume is between the second set of layers of the metallization of the first subvolume and the device layer, and the first set of layers of the metallization of the second subvolume is between the second set of layers of the metallization of the second subvolume and the device layer.

Example 61 includes the subject matter of any of Examples 59-60, and further specifies that the second set of layers of the metallization of the first subvolume includes a capacitor.

Example 62 includes the subject matter of any of Examples 59-61, and further specifies that the second set of layers of the metallization of the first subvolume includes a magnetic material.

Example 63 includes the subject matter of any of Examples 40-62, and further specifies that at least some of the first electrical structures are laser annealed.

Example 64 includes the subject matter of Example 63, and further specifies that none of the second electrical structures are laser annealed.

Example 65 includes the subject matter of any of Examples 63-64, and further specifies that the at least some of the first electrical structures have corresponding electrical structures in the second electrical structures, and the corresponding ones of the second electrical structures are not laser annealed.

Example 66 includes the subject matter of any of Examples 40-65, and further specifies that the first IC die is an artificial intelligence (AI) die.

Example 67 includes the subject matter of any of Examples 40-66, and further specifies that the third subvolume is between the first subvolume and the second subvolume.

Example 68 includes the subject matter of any of Examples 40-67, and further specifies that the third subvolume includes metallization, a third portion of the device layer of the first IC die is below the metallization of the third subvolume, and the third portion of the device layer of the first IC die does not include any devices.

Example 69 includes the subject matter of any of Examples 40-68, and further specifies that metallization of the third subvolume connects metallization of the first subvolume with metallization of the second subvolume.

Example 70 includes the subject matter of any of Examples 40-69, and further specifies that the first IC die has a bottom face opposite the top face, and the first IC die further includes: conductive contacts at the bottom face of the first IC die.

Example 71 includes the subject matter of Example 70, and further specifies that a pitch of the conductive contacts at the top face of the first IC die is different from a pitch of the conductive contacts at the bottom face of the first IC die.

Example 72 includes the subject matter of any of Examples 40-71, and further specifies that the first IC die includes dynamic random access memory (DRAM) devices.

Example 73 includes the subject matter of any of Examples 40-72, and further specifies that the first IC die includes static random access memory (SRAM) devices.

Example 74 includes the subject matter of any of Examples 40-73, and further specifies that the first IC die includes power delivery devices.

Example 75 includes the subject matter of any of Examples 40-74, and further specifies that the first IC die includes high bandwidth memory (HBM) controller circuitry.

Example 76 includes the subject matter of Example 75, and further specifies that the HBM controller circuitry is included in the first subvolume, and the second subvolume includes static random access memory (SRAM) devices.

Example 77 includes the subject matter of any of Examples 75-76, and further specifies that the second IC die includes HBM.

Example 78 includes the subject matter of Example 77, and further specifies that the first IC die and the second IC die are electrically coupled so that the HBM controller circuitry is to control the HBM.

Example 79 includes the subject matter of any of Examples 40-78, and further specifies that the second IC die is a deep neural network (DNN) die.

Example 80 includes the subject matter of any of Examples 40-79, and further specifies that the first IC die is electrically coupled to the second IC die by solder interconnects.

Example 81 includes the subject matter of any of Examples 40-80, and further specifies that the second IC die is one of a plurality of IC dies electrically coupled to the conductive contacts at the top face of the first IC die.

Example 82 includes the subject matter of Example 81, and further specifies that at least one of the plurality of IC dies is an artificial intelligence (AI) die and at least one of the plurality of IC dies is a high bandwidth memory (HB) die.

Example 83 is an integrated circuit (IC) package, including: an IC die, including a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die, a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die, and a third subvolume including electrical pathways between the first subvolume and the second subvolume, wherein the IC die has lateral dimensions greater than 22 millimeters by 33 millimeters; and a package substrate coupled to the IC die.

Example 84 includes the subject matter of Example 83, and further specifies that the IC die has an area greater than 750 square millimeters.

Example 85 includes the subject matter of Example 84, and further specifies that the IC die has a lateral dimension greater than 66 millimeters.

Example 86 includes the subject matter of any of Examples 83-85, and further specifies that the IC die has a lateral dimension greater than 99 millimeters.

Example 87 includes the subject matter of any of Examples 83-86, and further specifies that the IC die has a lateral dimension greater than 132 millimeters.

Example 88 includes the subject matter of any of Examples 83-87, and further specifies that the IC die has an area greater than 1500 square millimeters.

Example 89 includes the subject matter of any of Examples 83-88, and further specifies that the IC die has an area greater than 3000 square millimeters.

Example 90 includes the subject matter of any of Examples 83-89, and further specifies that the devices in the first portion of the device layer of the IC die include planar transistors, and the devices in the second portion of the device layer of the IC die include non-planar transistors.

Example 91 includes the subject matter of Example 90, and further specifies that the devices in the second portion of the device layer of the IC die include tri-gate transistors.

Example 92 includes the subject matter of any of Examples 83-91, and further specifies that the devices in the first portion of the device layer of the IC die include dual-gate transistors, and the devices in the second portion of the device layer of the IC die include tri-gate transistors.

Example 93 includes the subject matter of any of Examples 83-92, and further specifies that the devices in the first portion of the device layer of the IC die include tri-gate transistors having a first fin height, the devices in the second portion of the device layer of the IC die include tri-gate transistors having a second fin height, and the first fin height is different than the second fin height.

Example 94 includes the subject matter of any of Examples 83-93, and further specifies that the devices in the first portion of the device layer of the IC die include transistors having a first structure, the devices in the second portion of the device layer of the IC die include transistors having a second structure, and the first structure is different than the second structure.

Example 95 includes the subject matter of any of Examples 83-94, and further specifies that the third subvolume includes a first set of metallization layers and a second set of metallization layers, the first set of metallization layers is between the second set of metallization layers and the device layer, and the first set of metallization layers does not include any electrical pathways.

Example 96 includes the subject matter of any of Examples 83-95, and further specifies that the first electrical structures provide a processing unit and the second electrical structures provide a memory device.

Example 97 includes the subject matter of Example 96, and further specifies that the memory device includes static random access memory (SRAM) devices.

Example 98 includes the subject matter of any of Examples 96-97, and further specifies that the memory device includes dynamic random access memory (DRAM) devices.

Example 99 includes the subject matter of any of Examples 83-98, and further specifies that the first electrical structures include first conductive vias, the second electrical structures include second conductive vias, and the first conductive vias have a material composition different than a material composition of the second conductive vias.

Example 100 includes the subject matter of Example 99, and further specifies that the first conductive vias include tungsten.

Example 101 includes the subject matter of Example 100, and further specifies that the second conductive vias include copper.

Example 102 includes the subject matter of any of Examples 83-101, and further specifies that metallization of the first subvolume includes a first set of layers and a second set of layers, metallization of the second subvolume includes a first set of layers and a second set of layers, the first set of layers of the metallization of the first subvolume has a same structure as the first set of layers of the metallization of the second subvolume, and the second set of layers of the metallization of the first subvolume has a different structure than the second set of layers of the metallization of the second subvolume.

Example 103 includes the subject matter of Example 102, and further specifies that the first set of layers of the metallization of the first subvolume is between the second set of layers of the metallization of the first subvolume and the device layer, and the first set of layers of the metallization of the second subvolume is between the second set of layers of the metallization of the second subvolume and the device layer.

Example 104 includes the subject matter of any of Examples 102-103, and further specifies that the second set of layers of the metallization of the first subvolume includes a capacitor.

Example 105 includes the subject matter of any of Examples 102-104, and further specifies that the second set of layers of the metallization of the first subvolume includes a magnetic material.

Example 106 includes the subject matter of any of Examples 83-105, and further specifies that at least some of the first electrical structures are laser annealed.

Example 107 includes the subject matter of Example 106, and further specifies that none of the second electrical structures are laser annealed.

Example 108 includes the subject matter of any of Examples 106-107, and further specifies that the at least some of the first electrical structures have corresponding electrical structures in the second electrical structures, and the corresponding ones of the second electrical structures are not laser annealed.

Example 109 includes the subject matter of any of Examples 83-108, and further specifies that the IC die is an artificial intelligence (AI) die.

Example 110 includes the subject matter of any of Examples 83-109, and further specifies that the third subvolume is between the first subvolume and the second subvolume.

Example 111 includes the subject matter of any of Examples 83-110, and further specifies that the third subvolume includes metallization, a third portion of the device layer of the IC die is below the metallization of the third subvolume, and the third portion of the device layer of the IC die does not include any devices.

Example 112 includes the subject matter of any of Examples 83-111, and further specifies that metallization of the third subvolume connects metallization of the first subvolume with metallization of the second subvolume.

Example 113 includes the subject matter of any of Examples 83-112, and further includes: conductive contacts at a face of the IC die, wherein the conductive contacts at the face of the IC die are coupled to conductive contacts on the package substrate.

Example 114 includes the subject matter of Example 113, and further specifies that the conductive contacts at the face of the IC die are coupled to conductive contacts on the package substrate by solder interconnects.

Example 115 includes the subject matter of Example 114, and further includes: an underfill material around the solder interconnects.

Example 116 includes the subject matter of any of Examples 113-115, and further specifies that the face of the IC die is a first face, the IC die has a second face opposite the first face, and the IC die further includes: conductive contacts at the second face of the IC die.

Example 117 includes the subject matter of Example 116, and further specifies that the IC die is a first IC die, and the IC package further includes: a second IC die coupled to the conductive contacts at the second face of the IC die.

Example 118 includes the subject matter of Example 117, and further specifies that the first IC die includes high bandwidth memory (HBM) controller circuitry and the second IC die includes HBM.

Example 119 includes the subject matter of Example 118, and further specifies that the first IC die and the second IC die are electrically coupled so that the HBM controller circuitry is to control the HBM.

Example 120 includes the subject matter of any of Examples 117-119, and further specifies that the second IC die is a deep neural network (DNN) die.

Example 121 includes the subject matter of any of Examples 117-120, and further includes: an underfill material between the first IC die and the second IC die.

Example 122 includes the subject matter of any of Examples 117-121, and further specifies that the first IC die is electrically coupled to the second IC die by solder interconnects.

Example 123 includes the subject matter of any of Examples 117-122, and further specifies that the second IC die is one of a plurality of IC dies electrically coupled to the conductive contacts at the second face of the first IC die.

Example 124 includes the subject matter of Example 123, and further specifies that at least one of the plurality of IC dies is an artificial intelligence (AI) die and at least one of the plurality of IC dies is a high bandwidth memory (HB) die.

Example 125 includes the subject matter of any of Examples 83-124, and further specifies that the IC die includes dynamic random access memory (DRAM) devices.

Example 126 includes the subject matter of any of Examples 83-125, and further specifies that the IC die includes static random access memory (SRAM) devices.

Example 127 includes the subject matter of any of Examples 83-126, and further specifies that the IC die includes power delivery devices.

Example 128 includes the subject matter of any of Examples 83-127, and further specifies that the package substrate includes an organic material.

Example 129 includes the subject matter of any of Examples 83-128, and further specifies that the package substrate is a printed circuit board (PCB).

Example 130 is a computing device, including: an integrated circuit (IC) die, including a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die, a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die, and a third subvolume including electrical pathways between the first subvolume and the second subvolume, wherein the IC die has an area greater than 1000 square millimeters; and a motherboard communicatively coupled to the IC die.

Example 131 includes the subject matter of Example 130, and further specifies that the IC die has a lateral dimension greater than 33 millimeters.

Example 132 includes the subject matter of Example 131, and further specifies that the lateral dimension is a first lateral dimension, and the IC die also has a second lateral dimension greater than 22 millimeters.

Example 133 includes the subject matter of any of Examples 130-132, and further specifies that the IC die has a lateral dimension greater than 66 millimeters.

Example 134 includes the subject matter of any of Examples 130-133, and further specifies that the IC die has a lateral dimension greater than 99 millimeters.

Example 135 includes the subject matter of any of Examples 130-134, and further specifies that the IC die has an area greater than 1500 square millimeters.

Example 136 includes the subject matter of any of Examples 130-135, and further specifies that the IC die has an area greater than 3000 square millimeters.

Example 137 includes the subject matter of any of Examples 130-136, and further specifies that the devices in the first portion of the device layer of the IC die include planar transistors, and the devices in the second portion of the device layer of the IC die include non-planar transistors.

Example 138 includes the subject matter of Example 137, and further specifies that the devices in the second portion of the device layer of the IC die include tri-gate transistors.

Example 139 includes the subject matter of any of Examples 130-138, and further specifies that the devices in the first portion of the device layer of the IC die include dual-gate transistors, and the devices in the second portion of the device layer of the IC die include tri-gate transistors.

Example 140 includes the subject matter of any of Examples 130-139, and further specifies that the devices in the first portion of the device layer of the IC die include tri-gate transistors having a first fin height, the devices in the second portion of the device layer of the IC die include tri-gate transistors having a second fin height, and the first fin height is different than the second fin height.

Example 141 includes the subject matter of any of Examples 130-140, and further specifies that the devices in the first portion of the device layer of the IC die include transistors having a first structure, the devices in the second portion of the device layer of the IC die include transistors having a second structure, and the first structure is different than the second structure.

Example 142 includes the subject matter of any of Examples 130-141, and further specifies that the third subvolume includes a first set of metallization layers and a second set of metallization layers, the first set of metallization layers is between the second set of metallization layers and the device layer, and the first set of metallization layers does not include any electrical pathways.

Example 143 includes the subject matter of any of Examples 130-142, and further specifies that the first electrical structures provide a processing unit and the second electrical structures provide a memory device.

Example 144 includes the subject matter of Example 143, and further specifies that the memory device includes static random access memory (SRAM) devices.

Example 145 includes the subject matter of any of Examples 143-144, and further specifies that the memory device includes dynamic random access memory (DRAM) devices.

Example 146 includes the subject matter of any of Examples 130-145, and further specifies that the first electrical structures include first conductive vias, the second electrical structures include second conductive vias, and the first conductive vias have a material composition different than a material composition of the second conductive vias.

Example 147 includes the subject matter of Example 146, and further specifies that the first conductive vias include tungsten.

Example 148 includes the subject matter of Example 147, and further specifies that the second conductive vias include copper.

Example 149 includes the subject matter of any of Examples 130-148, and further specifies that metallization of the first subvolume includes a first set of layers and a second set of layers, metallization of the second subvolume includes a first set of layers and a second set of layers, the first set of layers of the metallization of the first subvolume has a same structure as the first set of layers of the metallization of the second subvolume, and the second set of layers of the metallization of the first subvolume has a different structure than the second set of layers of the metallization of the second subvolume.

Example 150 includes the subject matter of Example 149, and further specifies that the first set of layers of the metallization of the first subvolume is between the second set of layers of the metallization of the first subvolume and the device layer, and the first set of layers of the metallization of the second subvolume is between the second set of layers of the metallization of the second subvolume and the device layer.

Example 151 includes the subject matter of any of Examples 149-150, and further specifies that the second set of layers of the metallization of the first subvolume includes a capacitor.

Example 152 includes the subject matter of any of Examples 149-151, and further specifies that the second set of layers of the metallization of the first subvolume includes a magnetic material.

Example 153 includes the subject matter of any of Examples 130-152, and further specifies that at least some of the first electrical structures are laser annealed.

Example 154 includes the subject matter of any of Examples 153-153, and further specifies that none of the second electrical structures are laser annealed.

Example 155 includes the subject matter of Example 153, and further specifies that the at least some of the first electrical structures have corresponding electrical structures in the second electrical structures, and the corresponding ones of the second electrical structures are not laser annealed.

Example 156 includes the subject matter of any of Examples 130-155, and further specifies that the IC die is an artificial intelligence (AI) die.

Example 157 includes the subject matter of any of Examples 130-156, and further specifies that the third subvolume is between the first subvolume and the second subvolume.

Example 158 includes the subject matter of any of Examples 130-157, and further specifies that the third subvolume includes metallization, a third portion of the device layer of the IC die is below the metallization of the third subvolume, and the third portion of the device layer of the IC die does not include any devices.

Example 159 includes the subject matter of any of Examples 130-158, and further specifies that metallization of the third subvolume connects metallization of the first subvolume with metallization of the second subvolume.

Example 160 includes the subject matter of any of Examples 130-159, and further includes: conductive contacts at a face of the IC die.

Example 161 includes the subject matter of Example 160, and further specifies that the face of the IC die is a first face, the IC die has a second face opposite the first face, and the IC die further includes: conductive contacts at the second face of the IC die.

Example 162 includes the subject matter of Example 161, and further specifies that the IC die includes electrical pathways between the device layer of the IC die and the conductive contacts at the first face of the IC die, and the IC die includes electrical pathways between the device layer of the IC die and the conductive contacts at the second face of the IC die.

Example 163 includes the subject matter of any of Examples 161-162, and further specifies that a pitch of the conductive contacts at the first face of the IC die is different from a pitch of the conductive contacts at the second face of the IC die.

Example 164 includes the subject matter of any of Examples 130-163, and further specifies that the IC die includes dynamic random access memory (DRAM) devices.

Example 165 includes the subject matter of any of Examples 130-164, and further specifies that the IC die includes static random access memory (SRAM) devices.

Example 166 includes the subject matter of any of Examples 130-165, and further specifies that the IC die includes power delivery devices.

Example 167 includes the subject matter of any of Examples 130-166, and further specifies that the IC die includes high bandwidth memory (HBM) controller circuitry.

Example 168 includes the subject matter of Example 167, and further specifies that the HBM controller circuitry is included in the first subvolume, and the second subvolume includes static random access memory (SRAM) devices.

Example 169 includes the subject matter of any of Examples 130-168, and further specifies that the IC die is included in an IC package, and the IC package is coupled to the motherboard.

Example 170 includes the subject matter of any of Examples 130-169, and further specifies that the IC die is a first IC die, the computing device further includes a second IC die coupled to the first IC die, and the first IC die is between the second IC die and the motherboard.

Example 171 includes the subject matter of Example 170, and further includes: a mold compound around the first IC die and the second IC die.

Example 172 includes the subject matter of any of Examples 170-171, and further specifies that the second IC die is one of a plurality of IC dies coupled to the first IC die so that the first IC die is between individual IC dies of the plurality of IC dies and the motherboard.

Example 173 includes the subject matter of any of Examples 130-172, and further includes: a display device coupled to the motherboard.

Example 174 includes the subject matter of any of Examples 130-173, and further includes: wireless communication circuitry coupled to the motherboard.

Example 175 includes the subject matter of any of Examples 130-174, and further includes: a housing around the motherboard and the IC die.

Example 176 is a method of manufacturing an integrated circuit (IC) die, including: forming a first die subvolume in a wafer; forming a second die subvolume in the wafer, wherein the second die subvolume is spaced apart laterally from the first die subvolume; and forming a third die subvolume in the wafer, wherein the third die subvolume includes electrical pathways that electrically couple devices in the first die subvolume with devices in the second die subvolume; wherein a lateral area of the first die subvolume, the second die subvolume, and the third die subvolume together is greater than 800 square millimeters.

Example 177 includes the subject matter of Example 176, and further specifies that forming the first die subvolume includes performing lithographic patterning with a first photomask set, forming the second die subvolume includes performing lithographic patterning with a second photomask set, and forming the third die subvolume includes performing lithographic patterning with a third photomask set.

Example 178 includes the subject matter of Example 177, and further specifies that the first photomask set and the second photomask set are a same photomask set.

Example 179 includes the subject matter of Example 177, and further specifies that the first photomask set shares some, but not all, masks with the second photomask set.

Example 180 includes the subject matter of any of Examples 176-179, and further specifies that the third die subvolume is laterally between the first die subvolume and the second die subvolume.

Example 181 includes the subject matter of any of Examples 176-180, and further specifies that forming the first die subvolume includes performing a laser anneal.

Example 182 includes the subject matter of Example 181, and further specifies that forming the second die subvolume does not include performing a laser anneal.

Example 183 includes the subject matter of any of Examples 176-182, and further specifies that lateral dimensions of the first die subvolume, the second die subvolume, and the third die subvolume together are greater than 22 millimeters by 33 millimeters.

Example 184 includes the subject matter of any of Examples 176-183, and further includes: singulating the wafer into dies, wherein an individual die includes the first die subvolume, the second die subvolume, and the third die subvolume.