Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.

BACKGROUND

The following relates generally to one or more memory systems and more specifically to interconnected command/address (CA) resources.

Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, and others. Memory cells may be volatile or non-volatile. Non-volatile memory, e.g., FeRAM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state when disconnected from an external power source.

DETAILED DESCRIPTION

Multiple memory devices may be manufactured at one time on a single wafer. Later, the wafer may be divided into smaller parts that may be used in memory systems. A memory apparatus, such as a wafer, may be tested, among other examples, to determine whether one or more portions of the apparatus function according to a specified configuration. In some cases, an entire wafer may be tested before the wafer is separated into component parts (e.g., separated into memory dies or other memory devices), which may result in increased test performance and increased testing costs. For example, testing at the wafer level may result in higher costs when compared with testing at a memory die level or other memory device level. One example of how testing at the wafer level may increase some costs may include increase a pin count of a probe card used during the testing. Testing at the wafer level may include coupling a probe card with the wafer to provide power to the wafer for one or more testing procedures and to provide an interface for coupling the wafer with a testing apparatus (e.g., a tester). In some cases, a cost of a probe card may be associated with a pin count of the probe card. For example, a probe card with a higher quantity of pins (e.g., a higher pin count) may be associated with a higher cost than a probe card with a lower quantity of pins.

Accordingly, techniques and apparatuses are described herein to support a reduced quantity of pins for a probe card while also testing multiple memory dies of a wafer at one time. For example, a wafer may be configured such that a signal (e.g., a test signal) from the probe card may be received at a first command/address (CA) pad associated with a first memory die of the wafer and may be routed to one or more other CA pads associated with one or more other memory dies of the wafer. The probe card may thus perform a testing procedure for multiple memory dies using one or more pins of the probe card coupled with one or more pads associated with a subset of memory dies being tested (e.g., coupled with a single memory die). In such cases, the probe card may be configured with a reduced quantity of pins in order to test the wafer. Such techniques and apparatuses may reduce a cost of a probe card used to test the wafer, which may reduce overall costs for testing procedures at the wafer level.

The CA pads of the wafer may be included in a redistribution layer (RDL) of the wafer and may be coupled with one or more logic circuits in another region of the wafer via one or more corresponding CA conductive paths (e.g., located in the RDL). A CA pad of a first memory die may be coupled with a repeater logic circuit in a scribe region of the wafer, and the repeater logic circuit may be coupled with a corresponding control logic circuit in the scribe region. Such logic circuits may support transmission or repetition of a signal from the probe card to one or more other CA pads of one or more other memory dies. For example, the repeater logic circuit may receive a test signal from the CA pad (e.g., which may be coupled with the probe card) and may transmit (e.g., forward or repeat) the test signal to another CA pad of another memory die based on a configuration of the control logic circuit. The control logic circuit may control the repeater logic circuit to transmit the test signal to another memory die or to not transmit the test signal, and may further control a direction in which the test signal is transmitted by the repeater logic circuit.

Features of the disclosure are initially described in the context of memory systems and dies as described with reference toFIG. 1. Features of the disclosure are described in the context of a testing configuration, a signaling configuration, memory structures, and logic circuits as described with reference toFIGS. 2-5. These and other features of the disclosure are further illustrated by and described with reference to a flowchart that relate to interconnected CA resources as described with references toFIG. 6.

FIG. 1illustrates an example of a system100that supports interconnected CA resources in accordance with examples as disclosed herein. The system100may include a host device105, a memory device110, and a plurality of channels115coupling the host device105with the memory device110. The system100may include one or more memory devices110, but aspects of the one or more memory devices110may be described in the context of a single memory device (e.g., memory device110). In some cases, the system100may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other systems. For example, the system100may illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, or the like. The memory device110may be a component of the system operable to store data for one or more other components of the system100.

At least portions of the system100may be examples of the host device105. The host device105may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, or some other stationary or portable electronic device, among other examples. In some examples, the host device105may be an example of a probe card or testing apparatus (e.g., a tester). For example, the host device105may represent a tester, and may be coupled with the memory device110via a probe card.

In some examples, the host device105may refer to the hardware, firmware, software, or a combination thereof that implements the functions of an external memory controller120. In some examples, the external memory controller120may be referred to as a host or a host device105. If the host device105represents a probe card or a tester, the host device105may indicate for the memory device110to perform one or more testing functions (e.g., perform read, write, or other commands based on received CA information). For example, the host device105may control or run the memory device110to execute one or more testing protocols or methods within the memory device110, and in some cases, the host device105may request, from the memory device110, feedback associated with the testing protocols (e.g., results from the testing protocols).

Signaling between the host device105and the memory device110may be operable to support one or more of: modulation schemes to modulate the signals, various pin configurations for communicating the signals, various form factors for physical packaging of the host device105and the memory device110, clock signaling and synchronization between the host device105and the memory device110, timing, or other factors. The memory device110may be operable to store data for the components of the host device105. In some examples, the memory device110may act as a slave-type device to the host device105(e.g., responding to and executing commands provided by the host device105through the external memory controller120). In some cases, the commands provided by the host device may include one or more testing commands or protocols. Commands from the host device105(e.g., test commands) may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

The host device105may include one or more of an external memory controller120, a processor125, a basic input/output system (BIOS) component130, or other components such as one or more peripheral components or one or more input/output controllers. The components of host device may be coupled with one another using a bus135. The processor125may be operable to provide control or other functionality for at least portions of the system100or at least portions of the host device105. The processor125may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor125may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a system on a chip (SoC), among other examples. In some examples, the external memory controller120may be implemented by or be a part of the processor125.

In some examples, the system100or the host device105may include various peripheral components. The peripheral components may be any input device or output device, or an interface for such devices, that may be integrated into or with the system100or the host device105. Examples may include one or more of: a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a universal serial bus (USB) controller, a serial or parallel port, or a peripheral card slot such as peripheral component interconnect (PCI) or specialized graphics ports. In some examples, the peripheral components may represent or include a probe card or pins on a probe card. In some cases, the probe card may represent the host device105or may be coupled with the host device105(e.g., coupled with a tester). The peripheral component(s) may be other components understood by a person having ordinary skill in the art as a peripheral.

In some examples, the system100or the host device105may include an I/O controller. An I/O controller may manage data communication between the processor125and the peripheral component(s), input devices, or output devices. The I/O controller may manage peripherals that are not integrated into or with the system100or the host device105. In some examples, the I/O controller may represent a physical connection or port to external peripheral components.

In some examples, the system100or the host device105may include an input component, an output component, or both. An input component may represent a device or signal external to the system100that provides information, signals, or data to the system100or its components. In some examples, and input component may include a user interface or interface with or between other devices. In some examples, an input component may be a peripheral that interfaces with system100via one or more peripheral components or may be managed by an I/O controller. An output component may represent a device or signal external to the system100operable to receive an output from the system100or any of its components. Examples of an output component may include a display, audio speakers, a printing device, another processor on a printed circuit board, and others. In some examples, an output may be a peripheral that interfaces with the system100via one or more peripheral components or may be managed by an I/O controller.

The memory device110may include a device memory controller155and one or more memory dies160(e.g., memory chips) to support a desired capacity or a specified capacity for data storage. For example, the memory device110may represent a wafer of memory dies160and may include a quantity of memory dies160(e.g., one thousand memory dies). Each memory die160may include a local memory controller165(e.g., local memory controller165-a, local memory controller165-b, local memory controller165-N) and a memory array170(e.g., memory array170-a, memory array170-b, memory array170-N). A memory array170may be a collection (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) of memory cells, with each memory cell being operable to store at least one bit of data. A memory device110including two or more memory dies may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package. The device memory controller155may include circuits, logic, or components operable to control operation of the memory device110. The device memory controller155may include the hardware, the firmware, or the instructions that enable the memory device110to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device110. The device memory controller155may be operable to communicate with one or more of the external memory controller120, the one or more memory dies160, or the processor125. In some examples, the device memory controller155may control operation of the memory device110described herein in conjunction with the local memory controller165of the memory die160.

A local memory controller165(e.g., local to a memory die160) may be operable to control operation of the memory die160. In some examples, a local memory controller165may be operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller155. In some examples, a memory device110may not include a device memory controller155, and a local memory controller165, or the external memory controller120may perform various functions described herein. As such, a local memory controller165may be operable to communicate with the device memory controller155, with other local memory controllers165, or directly with the external memory controller120, or the processor125, or a combination thereof.

Examples of components that may be included in the device memory controller155or the local memory controllers165, or both, may include receivers for receiving signals (e.g., from the external memory controller120), transmitters for transmitting signals (e.g., to the external memory controller120), decoders for decoding or demodulating received signals, encoders for encoding or modulating signals to be transmitted, or various other circuits or controllers operable for supporting described operations of the device memory controller155or local memory controller165or both.

The external memory controller120may be operable to enable communication of one or more of information, data, or commands between components of the system100or the host device105or the processor125(e.g., a tester or a probe card) and the memory device110. The external memory controller120may convert or translate communications exchanged between the components of the host device105and the memory device110. In some examples, the external memory controller120or other component of the system100or the host device105, or its functions described herein, may be implemented by the processor125. For example, the external memory controller120may be hardware, firmware, or software, or some combination thereof implemented by the processor125or other component of the system100or the host device105. Although the external memory controller120is depicted as being external to the memory device110, in some examples, the external memory controller120, or its functions described herein, may be implemented by one or more components of a memory device110(e.g., a device memory controller155, a local memory controller165) or vice versa.

The components of the host device105may exchange information with the memory device110using one or more channels115. The channels115may be operable to support communications between the external memory controller120(e.g., a tester or a probe card) and the memory device110. Each channel115may be examples of transmission mediums that carry information between the host device105and the memory device. Each channel115may include one or more signal paths or transmission mediums (e.g., conductors) between terminals associated with the components of system100. A signal path may be an example of a conductive path operable to carry a signal. For example, a channel115may include a first terminal including one or more pins or pads at the host device105(e.g., one or more probe card pins or pads) and one or more pins or pads at the memory device110. A pin (e.g., pad) may be an example of a conductive input or output point of a device of the system100, and a pin may be operable to act as part of a channel.

Channels115(and associated signal paths and terminals) may be dedicated to communicating one or more types of information. For example, the channels115may include one or more CA channels186, one or more clock signal (CK) channels188, one or more data (DQ) channels190, one or more other channels192, or a combination thereof. In some examples, signaling may be communicated over the channels115using single data rate (SDR) signaling or double data rate (DDR) signaling.

In some examples, CA channels186may be operable to communicate commands between the host device105(e.g., the tester or probe card) and the memory device110including control information associated with the commands (e.g., address information). For example, the CA channel186may include a read command with an address of the desired data. In some examples, a CA channel186may include any quantity of signal paths to decode one or more of address or command data (e.g., eight or nine signal paths). In some examples, data channels190may be operable to communicate one or more of data or control information between the host device105and the memory device110. For example, the data channels190may communicate information (e.g., bi-directional) to be written to the memory device110or information read from the memory device110. In some examples, the one or more other channels192may include one or more error detection code (EDC) channels. The EDC channels may be operable to communicate error detection signals, such as checksums, to improve system reliability. An EDC channel may include any quantity of signal paths.

Some CA pads of a wafer may be coupled with one or more logic circuits of the wafer that may support transmission of a test signal between CA pads of different memory dies. For example, a CA pad of a first memory die may be coupled with a repeater logic circuit in a scribe region of the wafer, and the repeater logic circuit may be coupled with a corresponding control logic circuit in the scribe region. Such logic circuits may support transmission or repetition of a signal from a probe card to one or more other CA pads of one or more other memory dies. For example, the repeater logic circuit may receive a test signal from the CA pad (e.g., which may be coupled with the probe card) and may transmit (e.g., forward or repeat) the test signal to another CA pad of another memory die based on a configuration of the control logic circuit.

FIG. 2illustrates an example of a testing configuration200that supports interconnected CA resources in accordance with examples as disclosed herein. Testing configuration200may include a memory wafer205that is coupled with a probe card210, where the probe card210may, in turn, be coupled with a tester215(e.g., a testing apparatus). A wafer205may represent a block or group of memory devices that may be fabricated on a same substrate or platform, where the wafer may be separated into component memory devices by one or more additional fabrication steps. For example, the wafer205may include multiple memory dies220, which may each be an example of a respective memory die160described with reference toFIG. 1. In some cases, the wafer205may represent a largest manufactured unit of memory devices.

Although the testing configuration200is described with reference to memory dies220, the apparatuses, techniques, and configurations described herein may also apply to any memory device included in a wafer205. Some methods described herein may be occur during a testing operation (e.g., one or more testing procedures) performed on the wafer205. For example, the wafer205may be configured such that a group of memory dies220may be tested by the tester215and the probe card210, where a first subset of the group of memory dies220may be coupled with the probe card210and a second subset of the group of memory dies220may not be directly coupled with the probe card210.

The memory dies220of the wafer205may each include or be associated with one or more CA pads225(e.g., communication pads or pins). A CA pad225illustrated inFIG. 2may represent a single CA pad225or multiple CA pads225associated with a respective memory die220. A CA pad225may interface with the probe card210(e.g., a host device as described with reference toFIG. 1). For example, a CA pad225, or multiple CA pads225, associated with a memory die220may be coupled with or otherwise interface with one or more portions (e.g., pads or pins) of the probe card210. A CA pad225(e.g., or a group of CA pads225) associated with a first memory die220may also be selectively couplable with a CA pad225(e.g., or a group of CA pads225) associated with one or more second memory dies220. For example, one or more logic circuits230in a scribe region (e.g., a removable region) of the wafer205may be configured to selectively couple the CA pad225(e.g., or group of CA pads225) of the first memory die220with the CA pad225(e.g., or group of CA pads225) of the one or more second memory dies220.

In some examples, a CA pad225-aof memory die220-aand a CA pad225-bof memory die220-bvia may be selectively couplable via one or more logic circuits230-a. Similarly, a CA pad225-cof memory die220-cmay be selectively couplable with CA pad225-band with a CA pad225-dof memory die220-dvia one or more logic circuits230-band230-c, respectively. The example illustrated inFIG. 2shows four memory dies220, however, the wafer205may include any quantity of memory dies220and corresponding CA pads225, where a CA pad225of a memory die220may be selectively couplable with one or more CA pads225of other memory dies220.

The probe card210may include multiple pins235(e.g., pads, balls, or other means for coupling) that may interface with (e.g., couple with) one or more corresponding CA pads225on the wafer205(e.g., CA pads225-band225-c). The probe card may further be coupled with or interface with a testing device or apparatus (e.g., tester215). The tester215may represent a computer, a processor, a general-purpose testing device, a special-purpose testing device, or any other testing device or apparatus. In some cases, the tester215may control the probe card210or may include the probe card210.

The probe card210may configure the wafer205for testing, for example, by transmitting a test configuration to the wafer205as indicated by the tester215(e.g., a test configuration determined by the tester215or input into the tester215, such as by a user). The probe card210may transmit a test signal to the wafer205(e.g., to one or more memory dies220of the wafer205) via one or more CA pads225(e.g., CA pads225-band225-c), and the one or more memory dies220of the wafer205may perform a command indicated by the signal (e.g., a read command, write command, or other command). In some cases, data may be generated by the wafer205(e.g., or components of the wafer205) during the testing operation and in response to a test signal, and may be transmitted (e.g., via one or more DQ pads or other pads) back to the probe card210(e.g., and corresponding tester215).

In some cases, the test configuration may indicate that a first memory die220and associated CA pad225are to repeat a signal received from the probe card210to a second CA pad225associated with a second memory die220that may not be coupled (e.g., directly coupled) with the probe card210. For example, the test configuration may indicate for CA pad225-b(e.g., associated with memory die220-b) to forward or repeat a test signal to CA pad225-a(e.g., associated with memory die220-a). Similarly, the test configuration may indicate for CA pad225-c(e.g., associated with memory die220-c) to forward or repeat a test signal to CA pad225-d(e.g., associated with memory die220-d). The test signal may be repeated via one or more logic circuits230as described herein.

A probe card210may test (e.g., transmit test signals or commands to) one or more memory dies220or associated CA pads225that may not be directly coupled with the probe card210. Accordingly, a quantity of pins235on the probe card210may be less than a total quantity of CA pads225that may be tested using the quantity of pins235on the probe card210. For example, pins235-aand235-bof the probe card may be respectively coupled with CA pads225-band225-cof the wafer. The probe card210(e.g., as indicated by the tester215) may transmit a signal via CA pads225-band225-c, and the one or more logic circuits230-aand230-cmay forward the signal to CA pads225-aand225-d, respectively. Thus a test signal may be received by one or more CA pads225(e.g., and one or more associated memory dies220) that are not directly coupled with the probe card210.

FIG. 3illustrates an example of a signaling configuration300that supports interconnected CA resources in accordance with examples as disclosed herein. Signaling configuration300may represent a configuration of a wafer305, such as a wafer described with reference toFIGS. 1 and 2. The wafer305may include multiple memory dies310and associated circuitry. Although the signaling configuration300is described with reference to memory dies310, the apparatuses, techniques, and configurations described herein may also apply to any memory device included in a wafer305. The wafer305may be configured such that a pin of a probe card may interface or couple with (e.g., during a testing procedure) a first CA pad325associated with a first memory die310and may transmit a signal, via the first CA pad325, to one or more other CA pads325that may not be directly coupled with the probe card and that may be associated with one or more other memory dies310.

A memory apparatus, such as the wafer305, may be tested for quality control, for example, to determine whether one or more portions of the wafer305function according to a specified configuration. In some cases, the wafer305may be tested for other purposes. Testing of the wafer305(e.g., performing one or more testing procedures) may occur at a specific time in a manufacturing process of the wafer305. For example, a testing time may be chosen such that certain testing results or cost characteristics may be achieved when performing a testing procedure. In some cases, testing of the wafer305may occur before the wafer305is separated into component parts (e.g., separated into memory dies310, groups of memory dies310, or other memory devices). Such testing may support improved testing results and testing processes, among other examples.

In some cases, performing the one or more testing procedures at a wafer level (e.g., before separating the wafer305) may result in increased testing costs. For example, testing at the wafer level may result in a probe card having a higher quantity of pins, which may increase the cost of performing the tests. For example, testing at the wafer level may include coupling a probe card with the wafer305or with a portion of the wafer305to test the wafer305(e.g., or to test a portion of the wafer305). The probe card may provide power to the wafer305for the one or more testing procedures and may also provide an interface for coupling the wafer305with a testing apparatus (e.g., a tester). In some cases, each different design of a memory device or wafer305may correspond to a respective, different probe card design. The probe card may result in increased testing costs at the wafer level due to a complexity of the probe card and associated cost of manufacturing the probe card, among other examples. In some cases, a cost of a probe card may be associated with a pin count of the probe card. For example, a probe card with a higher quantity of pins (e.g., a higher pin count) may be associated with a higher cost than a probe card with a lower quantity of pins.

Accordingly, techniques and apparatuses are described herein to support a reduced quantity of pins for a probe card. For example, the wafer305may be configured such that a signal from the probe card (e.g., transmitted from the tester via the probe card) may be received by a first CA pad325associated with a first memory die310of the wafer305and may be routed to one or more other CA pads325(e.g., associated with one or more other memory dies310) of the wafer305. Such techniques may share CA resources for test signal transmission, which may support a higher quantity of parallel operations for testing procedures and a corresponding reduction in tester resources (e.g., probe card pins and/or tester protocols).

The probe card may thus perform a testing procedure for multiple CA pads325(e.g., and associated multiple memory dies310) using one pin of the probe card (e.g., coupled with one CA pad325on the wafer305). Accordingly, a quantity of probe card pins used to test CA resources (e.g., CA pads325) may be lower than an associated quantity of tested CA pads325(e.g., a quantity or count of CA pads325on the wafer305). The probe card may therefore be configured with a reduced quantity of pins in order to test the wafer305(e.g., compared to examples where signals may not be routed between CA pads325on different memory dies310). For example, an average quantity of probe card pins associated with a memory die310on the wafer305may be reduced from14pins on average to five pins, three pins, or two pins on average. Such techniques and apparatuses may reduce a cost of a probe card used to test the wafer305, which may reduce overall costs for performing testing procedures at the wafer level.

The wafer305may include different regions (e.g., units) of memory dies310and associated circuitry. For example, the wafer305may include one or more regions that include the memory dies310(e.g., or memory devices) of the wafer305and may include one or more regions that include other circuitry. The one or more regions may include scribe regions315, where a scribe region315may represent a portion of the wafer305that may be removed when the wafer305is separated into memory dies310or memory devices. A scribe region315may include circuitry that may be used to repeat a test signal (e.g., a signal or command associated with a testing procedure) from a first CA pad325of a first memory die310to a second CA pad325of a second memory die310.

Each memory die310may include one or more respective CA pads325and one or more respective signal pads320. A CA pad325or a signal pad320may, in some cases, be coupled with the probe card when performing a testing procedure. In some cases, a CA pad325may receive a test signal from the probe card, and a signal pad320may receive a testing configuration signal from the probe card. A CA pad325or a signal pad320may be coupled with circuitry in a scribe region315that may support transmitting (e.g., repeating or forwarding) a signal to one or more other CA pads325of one or more other memory dies310. The CA pads325and the signal pads320may be included in an RDL of the wafer305that may be coupled with each of the memory dies310of the wafer305. The RDL may represent a highest metal layer of the wafer305and may redistribute signals to other resources located in or coupled with the RDL. The RDL is further described herein with reference toFIG. 4.

A scribe region315may include a logic circuit for repeating or forwarding a signal to one or more other CA pads325on one or more memory dies310. The logic circuit may include a control circuit330(e.g., a first subset or a first circuit) and a repeater circuit335(e.g., a second subset or a second circuit). In some cases, the repeater circuit335may be included in non-scribe regions of the wafer305(e.g., may be included on-chip). The control circuit330may represent a circuit used to indicate a direction a test signal is to be forwarded or repeated. In some cases, the control circuit330may indicate that a test signal is not to be forwarded or repeated (e.g., is to be isolated). The control circuit330may be hardwired with such signal control information or may be configured with signal control information by the testing configuration signal.

The repeater circuit335may receive a test signal from a CA pad325of a memory die310(e.g., a CA pad325coupled with the probe card) and may transmit (e.g., forward or repeat) the test signal to another CA pad325(e.g., of another memory die310), for example, based on the configuration of a control circuit330associated with the repeater circuit335. For example, the associated control circuit330may, in some cases, control the repeater circuit335to repeat the test signal to another memory die310(e.g., a memory die310located to the left or right of the memory die310) or to suppress retransmission of the test signal. In some cases, a memory die310of the wafer305may be configured such that each CA pad325of the memory die310is coupled with a corresponding control circuit330and repeater circuit335for each associated neighboring memory die310. For example, a memory die310may be associated with 14 CA pads325, and each of the 14 CA pads may be respectively coupled with one control circuit330and one repeater circuit335for driving left and one control circuit330and one repeater circuit335for driving right (e.g., each memory die may be associated with 28 control circuits330and28repeater circuits335).

In one example, a CA pad325-b(e.g., associated with memory die310-b) may be coupled with the probe card. The CA pad325-bmay be coupled with repeater circuits335-aand335-bin scribe regions315-aand315-b, respectively, via CA conductive paths340-band340-c, respectively. In some cases, signal pads320-cand320-dof memory die310-bmay be coupled with the probe card. Signal pads320-cand320-dmay, in some cases, receive a testing configuration from the probe card indicating a configuration or a portion of a configuration for control circuits330-aand330-b. In some cases, signal pads320-band320-emay also receive a testing configuration from the probe card indicating a configuration or a portion of a configuration for control circuits330-aand330-b. In some cases, control circuits330-aand330-bmay be hardwired with a configuration indicating a signal direction.

Control circuits330-aand330-bmay be configured (e.g., according to the received testing configuration or hardwired) with a direction for respective repeater circuits335-aand335-bto repeat or forward a test signal. For example, control circuit330-amay be configured to support repetition of the test signal from memory die310-bto memory die310-a(e.g., drive the test signal left), but may not be configured to support repetition from memory die310-ato310-b(e.g., drive the test signal right). Similarly, control circuit330-bmay be configured to support repetition of the test signal from memory die310-bto memory die310-c(e.g., drive the test signal right), but not from memory die310-cto310-b(e.g., drive the test signal left). For example, this configuration may include control circuit330-abeing configured with drive left “on” and drive right “off,” as well as control circuit330-bbeing configured with drive left “off” and drive right “on.”

Accordingly, CA pad325-bmay receive a test signal from the probe card and the signal may be routed from CA pad325-bto repeater circuits335-aand335-b(e.g., via CA conductive paths340-band340-c, respectively). Control circuit330-a, based on the described control configuration, may control the repeater circuit335-a(e.g., via one or more control signals) to repeat the test signal to the left (e.g., to memory die310-a), but not to the right. Similarly, control circuit330-bmay control the repeater circuit335-b(e.g., via one or more control signals) to repeat the test signal to the right (e.g., to memory die310-c), but not to the left. Accordingly, repeater circuit335-amay repeat the test signal to CA conductive path340-aand CA pad325-aand repeater circuit335-bmay repeat the test signal to CA conductive path340-dand CA pad325-c. In some cases, other control circuits330and repeater circuits335associated with memory dies310-aand310-cmay be configured to stop repetition of the test signal beyond memory dies310-aand310-c(e.g., the other associated control circuits330may be configured with drive left or drive right as “off”). For example, the test signal may be shared among three memory dies310(e.g., memory dies310-a,310-b, and310-c) and may not be transmitted to other memory dies310.

In some cases, one or more control circuits330and repeater circuits335may be used to isolate a memory die310from a test signal. As such, the one or more control circuits330may be configured to control the corresponding one or more repeater circuits335to be in an isolation state, or to not repeat the test signal. In some cases, the isolation configuration may be used to exclude a memory die310from testing procedures when the memory die310is known to be a bad die.

While the example illustrated inFIG. 3shows three memory dies310included in the wafer305, it is to be understood that any quantity of memory dies310may be included in the wafer. For example, the wafer305may include one thousand or more memory dies310. Similarly, the example of selectively coupling CA resources (e.g., CA pads325, signal pads320, and CA conductive paths340) for test signal transmission between three memory dies310-a,310-b, and310-cmay be extended to sharing (e.g., selectively coupling) CA resources for test signal propagation between any quantity of memory dies310. For example, five memory dies310or seven memory dies310may share CA resources for test signal propagation (e.g., test signal repetition, forwarding, or transmission to other memory dies310). In some cases, all the memory dies310included in the wafer305may share CA resources. In the example of three memory dies310sharing CA resources for test signal propagation, a quantity of probe card pins per memory die310may be five pins. In the example of five memory dies310sharing CA resources, a quantity of probe card pins per memory die310may be three pins, and in the example of seven memory dies310sharing CA resources, a quantity of probe card pins per memory die may be two pins. Accordingly, a quantity of probe card pins may be reduced compared with other configurations that do not share CA resources.

In some cases, a larger quantity of memory dies310with shared CA resources may result in greater signal propagation delay. As such, a quantity of memory dies310with shared CA resources may be based on a desired pin count for the probe card and a desired propagation delay or propagation speed for the test signal.

In some cases, CA resources (e.g., CA pads325, signal pads320, and CA conductive paths340) may be shared among memory dies310by coupling multiple CA pads325and/or signal pads320of one memory die310to the probe card. The wafer305may be configured to repeat test signals from the multiple CA pads325to one or more other CA pads325on other memory dies310. In some cases, CA pads325and/or signal pads320of multiple memory dies310may be coupled with the probe card to support distribution of pin density across the wafer305and the probe card. In such cases, the wafer305may similarly be configured to repeat test signals from the CA pads325to one or more other CA pads325on other memory dies310.

In some cases, one or more test signals may be multiplexed (e.g., via address skipping) when transmitted to the wafer305(e.g., via one or more CA pads325). The multiplexing may support an even lower pin count on the probe card because a larger quantity of information may be transmitted via a multiplexed test signal. In some cases, multiplexing the one or more test signals may increase complexity of addressing circuitry on the memory dies310of the wafer305or may increase a time duration for testing procedures. As such, a quantity of multiplexed test signals may be based on a desired pin count for the probe card and a desired complexity or cost associated with the wafer305.

FIGS. 4A and 4Billustrate respective examples of memory structures401and402that support interconnected CA resources in accordance with examples as disclosed herein. Memory structures401and402may represent structures included in a wafer, which may represent a wafer described with reference toFIGS. 1-3. As described with reference toFIGS. 1-3, the wafer may be configured such that a pin of a probe card may interface or couple with a first CA pad425of a first memory die (e.g., during a testing procedure) and may transmit a signal, via the first CA pad425, to one or more other CA pads425(e.g., associated with one or more other memory dies) that may not be directly coupled with the probe card. Although the memory structures401and402are described with reference to memory dies, the apparatuses, techniques, and configurations described herein may also apply to any memory device included in a wafer.

The structures on the wafer may include different regions (e.g., units) associated with memory dies or with other circuitry. For example, the wafer may include memory die regions410that include structures associated with memory dies (e.g., or memory devices) of the wafer. The wafer may also include scribe regions415that include circuitry associated with testing the memory dies (e.g., or memory devices). The scribe regions415may be removed when the wafer is separated into memory dies or memory devices and may include circuitry for transmitting a test signal between CA pads425of different memory dies. The scribe regions415may, in some cases, include all of the materials or layers within a corresponding region of the wafer.

A memory die region410may include one or more respective CA pads425and one or more respective signal pads420. A CA pad425or a signal pad420may, in some cases, be coupled with the probe card when performing a testing procedure. In some cases, a CA pad425may receive a testing signal from the probe card, and a signal pad420may receive a testing configuration signal from the probe card. The CA pads425and the signal pads420may be included in an RDL405that may form part of the wafer and may be coupled with each of the memory dies of the wafer. The RDL405may represent a highest or top metal material of the wafer, and conductive lines and/or traces in the RDL405may redistribute signals to other resources located in or coupled with the RDL405. In some cases, the RDL405may reduce drops in signal power, for example, compared to transmitting signals via one or more other portions of the wafer. For example, the RDL405may include larger features or components (e.g., compared to other materials) and the larger features or components may drive a higher current without a corresponding higher power drop (e.g., compared to other materials). A CA pad425or a signal pad420in the RDL405may be coupled with circuitry within a scribe region415that may support transmitting a test signal between CA pads425or signal pads420of different memory dies.

For example, the RDL405may include a CA conductive path440that may couple a CA pad425with circuitry in a scribe region415. In some cases, a CA conductive path440may also couple a CA pad425with a buffer445. A CA conductive path440may additionally couple a signal pad420with circuitry in a scribe region415. The circuitry in the scribe region415may be positioned below the RDL405, such as in a lower material in the stack of materials of the wafer, and may be coupled with the RDL405, such as via a respective CA conductive path440.

The circuitry in the scribe region415may include a logic circuit for transmitting a signal between CA pads425on different memory dies. The logic circuit may include a control circuit430(e.g., a first subset or a first circuit) and a repeater circuit435(e.g., a second subset or a second circuit). The control circuit430may represent a circuit used to indicate a direction a test signal is to be transmitted, or used to indicate that a test signal is not to be transmitted to another memory die (e.g., is to be isolated). The repeater circuit435may receive a test signal from a CA pad425(e.g., a CA pad425in a first memory die region410, that is coupled with the probe card) via a CA conductive path440. The repeater circuit435may forward or repeat the test signal to another CA pad425and CA conductive path440(e.g., in another memory die region410), for example, based on the configuration of a control circuit430associated with the repeater circuit435.

The CA pads425, signal pads420, control circuits430, and repeater circuits435may be examples of the corresponding structures described with reference toFIG. 3. For example, the CA pads425, signal pads420, control circuits430, and repeater circuits435described with reference toFIG. 4may be configured or otherwise constructed to perform one or more of the methods for transmitting (e.g., repeating or forwarding) a test signal or other signal between memory dies (e.g., between memory die regions410).

In one example, a CA pad425-bin a memory die region410-bmay be coupled with multiple repeater circuits435. For example, CA pad425-bmay be coupled with repeater circuits435associated with neighboring memory die regions410, such as repeater circuits435-aand435-b, which may selectively couple the memory die region410-bwith memory die regions410-aand410-c, respectively. The CA pad425-bmay be coupled with repeater circuits435-aand435-bvia CA conductive paths440-band440-c, respectively. In some cases, CA pad425-band CA conductive paths440-band440-cmay be included in the RDL405. Similar configurations may exist for other CA pads425, corresponding memory die regions410, and scribe regions415. For example, a memory die region410-amay include a CA pad425-a, which may be coupled with one or more repeater circuits435(e.g., repeater circuit435-a) via one or more CA conductive paths440(e.g., CA conductive path440-a). Similarly, a memory die region410-cmay include a CA pad425-c, which may be coupled with one or more repeater circuits435(e.g., repeater circuit435-b) via one or more CA conductive paths440(e.g., CA conductive path440-d).

A control circuit430may be coupled with multiple signal pads420in a memory die region410-e. For example, control circuit430-bmay be coupled with signal pads420associated with neighboring memory die regions410, such as signal pads420-cand420-d, where the control circuit430-bmay selectively couple the memory die region410-ewith memory die region410-f. Signal pads420-cand420-dmay be coupled with control circuit430-bvia respective control signal conductive paths460-cand460-d. In some cases, the signal pads420and the control signal conductive paths460may be included in the RDL405. Similar configurations may exist for other signal pads420, corresponding memory die regions410, and scribe regions415. For example, a memory die region410-dmay include a signal pad420-a, which may be coupled with a control circuit430-avia control signal conductive path460-a. Similarly, memory die region410-emay include a signal pad420-b, which may be coupled with control circuit430-bvia control signal conductive path460-b.

A CA pad425may also be coupled with a buffer445that may, in some cases, be located in the RDL405. For example, CA pad425-amay be coupled with a buffer445-a, CA pad425-bmay be coupled with a buffer445-b, and CA pad425-cmay be coupled with a buffer445-c. A buffer445may couple the CA pad425in the RDL405with one or more internal CA resources. In some cases, buffering may be configurable to use hard or soft ties to control a buffer445, for example, based on available resources. After wafer processing is finished (e.g., the wafer is separated into component parts), a buffer445and an associated CA pad425may be in a disabled or inert state. For example, during testing, a buffer may receive a signal455(e.g., asserted as a part of the testing) that may activate the buffer445and may couple the associated CA pad425with internal CA resources. After testing is completed, the signal455may be de-asserted, which may render the buffer445and corresponding CA pad425inert and may decouple the buffer445and the CA pad425from the internal CA resources.

In some cases, a memory die region410or scribe region415illustrated byFIG. 4Amay correspond to a memory die region410or scribe region415illustrated byFIG. 4B. For example, memory die regions410-a,410-b, and410-cmay respectively correspond to memory die regions410-d,410-e, and410-f, and in some cases may represent a different portion or subset of a same memory die region410. For example, corresponding memory die regions410may each represent a subset of the same memory die region410, but at a different location within a plane of the memory die region410(e.g., a different location within a plane of the RDL405or another material). Similarly, scribe regions415-aand415-bmay respectively correspond to scribe regions415-cand415-d, and in some cases may represent a different portion or subset of a same scribe region415. For example, corresponding scribe regions415may each represent a subset of the same scribe region415, but at a different location within a plane of the scribe region415(e.g., a different location within a plane of the RDL405or another material).

A control circuit430and a repeater circuit435corresponding to a same scribe region415may be coupled via one or more conductive paths450. For example, control circuit430-aand repeater circuit435-amay be coupled via one or more conductive paths450-aor450-c. Similarly, control circuit430-band repeater circuit435-bmay be coupled via one or more conductive paths450-bor450-d. In some cases, an associated control circuit430and repeater circuit435may be included in a same material of the wafer (e.g., same layer). For example, in some cases, an associated control circuit430and repeater circuit435may be included in one or more active silicon materials of the wafer (e.g., active silicon layers).

In some cases, after the scribe regions415are removed (e.g., for further processing of the wafer), the CA conductive paths440previously coupled with the repeater circuits435and control circuits430(e.g., removed with the scribe regions415) may be left floating or may be coupled with a buffer, among other examples. In some cases, the repeater circuits435and control circuits430may be located in non-scribe regions of the wafer (e.g., memory die regions410), for example, based on available area in one or more other active regions of the wafer. In such cases, the repeater circuits435and control circuits430may remain after removing the scribe regions415from the wafer.

FIGS. 5A and 5Billustrates respective examples of logic circuits501and502that support interconnected CA resources in accordance with examples as disclosed herein. In some cases, as described with reference toFIGS. 3 and 4, logic circuits501and502may be located between two neighboring memory dies. For example, logic circuits501and502may be included in a scribe region of a wafer that is coupled with two neighboring memory dies. Logic circuits501and502may occupy one or more active materials (e.g., layers) of silicon within the scribe region and may be removed from the wafer with the scribe region (e.g., during dicing that may occur after testing). In some cases, as described with reference toFIGS. 3 and 4, logic circuits501and502may be included within the circuitry of a memory die.

As illustrated inFIG. 5A, logic circuit501may include control conductive paths505-aand505-b, CA conductive paths510-aand510-b, and logic sub-circuitry515-a, where logic sub-circuitry515-amay be coupled with control conductive paths505-aand505-band CA conductive paths510-aand510-b. Logic circuit501may represent a repeater circuit described with reference toFIGS. 3 and 4. For example, logic circuit501may be configured to repeat or transmit a signal from a first CA pad associated with a first memory die to a second CA pad associated with a second memory die by selectively coupling the first and second CA pads and associated CA conductive paths510. In some cases, logic sub-circuitry515-amay include one or more conductive paths and one or more amplifiers (e.g., as illustrated inFIG. 5A), among other components.

Logic circuit501may receive a control signal from logic circuit502via control conductive path505-aor505-b, or both, where the control signal may configure the logic circuit501to repeat or suppress repetition of a test signal from a first CA pad associated with a first memory die to a second CA pad associated with a second memory die. The first CA pad may be coupled with a pin of a probe card and may receive a test signal from the probe card (e.g., via the pin). Logic circuit501may receive the test signal from the first CA pad via a first CA conductive path510that couples the first CA pad with logic circuit501(e.g., CA conductive path510-aor510-b). In some cases, logic circuit501may forward or transmit the test signal to the second CA pad via a second CA conductive path510that couples the logic circuit501with the second CA pad (e.g., CA conductive path510-aor510-b), based on the received control signal.

For example, if the control signal is received via control conductive path505-a, the test signal may be forwarded to the second CA pad via CA conductive path510-a(e.g., to the left of the first memory die and first CA pad). Similarly, if the control signal is received via control conductive path505-b, the test signal may be forwarded to the second CA pad via CA conductive path510-b(e.g., to the right of the first memory die and the first CA pad). In some cases, if the control signal is received via both control conductive paths505-aand505-b(e.g., if the control signal drives both control conductive paths505-aand505-bto a low voltage), the test signal may be suppressed from being transmitted (e.g., repeated or forwarded) to the second CA pad and memory die. Similarly, if no control signal is received via either control conductive path505-aor505-b, the test signal may be suppressed from being transmitted (e.g., repeated or forwarded) to the second CA pad.

In some cases, the control signal may include a voltage pulse or a voltage level and may configure the logic sub-circuitry515-ato propagate or suppress propagation of the test signal to the second CA pad. For example, a voltage pulse transmitted via control conductive path505-amay configure the logic sub-circuitry515-ato open current flow from right to left (e.g., may activate an amplifier or other component of logic sub-circuitry515-a). Accordingly, the test signal may travel from the first CA pad (e.g., the CA pad interacting directly with the probe) to the second CA pad located to the right of the first memory die and CA pad. Similarly, a voltage pulse transmitted via control conductive path505-bmay configure the logic sub-circuitry515-ato open current flow from left to right (e.g., may activate an amplifier or other component of logic sub-circuitry515-a), such that the test signal may travel from the first CA pad to the second CA pad located to the left of the first memory die and CA pad.

As illustrated inFIG. 5B, logic circuit502may include control conductive paths505-cand505-d, control signal conductive paths520-aand520-b, and logic sub-circuitry515-b, where logic sub-circuitry515-bmay be coupled with control conductive paths505-cand505-dand control signal conductive paths520-aand520-b. Logic circuit502may represent a control circuit described with reference toFIGS. 3 and 4and may be configured to transmit a control signal to logic circuit501to control signal transmission between CA pads of neighboring memory dies. In some cases, logic circuit502may receive control information indicating a signal propagation configuration and in some cases, logic circuit502may be hardwired with a configuration for propagating a signal.

Control conductive paths505-cand505-dmay be coupled with or represent a portion of control conductive paths505-aand505-b, such that logic circuit502may be coupled with logic circuit501via respective control conductive paths505. The control signal conductive paths520-aand520-bmay be coupled with respective signal pads on the first and second memory dies. In some cases, logic sub-circuitry515-bmay include one or more conductive paths, one or more AND gates, one or more not or (NOR) gates, and one or more inverters, among other components (e.g., as illustrated inFIG. 5B). In some cases, the one or more components of logic sub-circuitry515-bmay be configured to receive a test configuration (e.g., including control information) and use the test configuration to generate a control signal for logic circuit501. In some cases, the one or more components of logic sub-circuitry515-bmay be configured (e.g., hardwired) with a specific configuration for generating a control signal for logic circuit501.

In some examples, as described herein, logic circuit502may receive control information from a tester (e.g., via a probe card). For example, the tester may transmit a testing configuration to logic circuit502via CA resources, such as one or more signal pads and control signal conductive paths520(e.g., control signal conductive paths520-aand/or520-b). In some examples, as described with reference toFIGS. 3 and 4, there may be two signal pads coupled with each logic circuit502. The first signal pad may be associated with the first memory die and may be coupled with logic circuit502via a first control signal conductive path520(e.g., control signal conductive path520-aor520-b). The second signal pad may be associated with the second memory die and may be coupled with logic circuit502via a second control signal conductive path520(e.g., control signal conductive path520-aor520-b). Logic circuit502may receive a testing configuration (e.g., including control information), or portions thereof, via either or both of the first signal pad and the second signal pad.

The control information (e.g., testing configuration) received by logic circuit502may include drive control inputs. For example, logic circuit502may receive drive control inputs via control signal conductive paths520-aand520-band may generate a control signal to transmit via control conductive path505-cor505-d, or both (e.g., using logic sub-circuitry515-b). The control conductive path505used for control signaling may be based on drive control inputs received via control signal conductive paths520-aand520-b. For example, logic circuit502may receive a drive control input via control signal conductive path520-aassociated with forwarding the test signal to the left (e.g., DriveLeft). Additionally or alternatively, logic circuit502may receive a drive control input via control signal conductive path520-bassociated with forwarding the test signal to the right (e.g., DriveRight). In some examples, drive control inputs may be represented by one or more logic values, such as a “0” or “1”. In some cases, a logic value of “0” may indication an “off” state for a particular signaling direction, whereas a logic value of “1” may indicate an “on” state for the signaling direction.

For example, a DriveLeft input logic value of “1” and a DriveRight input logic value of “0” may indicate for logic circuit502to transmit a control signal configuring the logic circuit501to forward the test signal to the left (e.g., transmit a signal via control conductive path505-a). Similarly, a DriveLeft input logic value of “0” and a DriveRight input logic value of “1” may indicate for logic circuit502to transmit a control signal configuring the logic circuit501to transmit the test signal to the right (e.g., transmit a signal via control conductive path505-b). In some cases, if DriveRight and DriveLeft inputs both indicate a logic value “0” or “1,” logic circuit502may suppress transmission of a control signal to logic circuit501and the test signal may be isolated. In some cases, if DriveRight and DriveLeft inputs both indicate a logic value “0” or “1” logic circuit502may transmit of a control signal to logic circuit501to configure logic circuit501to suppress transmission of the test signal (e.g., transmit a signal via control conductive paths505-aand505-b), such that the test signal may be isolated.

In some cases, logic circuit502may receive control information (e.g., via a testing configuration) from a neighboring memory die and one or more DQ pads associated with the neighboring memory die. For example, the first or second signal pad may transmit control information (e.g., as a portion of a testing configuration) forwarded from one or more DQ pads. The control information from a DQ pad may, for example, indicate a final memory die to receive a test signal (e.g., the test signal is to be isolated after propagation to the final memory die, or the memory die associated with the DQ pad), among other examples. Logic circuit502may receive such control information via control signal conductive path520-aor520-b, which may indicate logic values associated with DriveLeft or DriveRight, respectively.

In some examples, drive control inputs may be fixed by hardwiring the logic circuit502during manufacturing. For example, logic circuit502may be hardwired to route the test signal to the right of the first memory die, route the test signal to the left of the first memory die, or suppress transmission of the test signal, and may generate a corresponding control signal for logic circuit501.

FIG. 6shows a flowchart illustrating a method or methods600that supports interconnected CA resources in accordance with examples as disclosed herein. The operations of method600may be implemented by a wafer that includes one or more memory devices or its components as described herein. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, a memory device may perform aspects of the described functions using special-purpose hardware.

At605, the wafer may receive, at a wafer that includes a set of memory dies, a first signal indicating a test configuration of the wafer. The operations of605may be performed according to the methods described herein.

At610, the wafer may receive, from a probe card, a second signal at a first CA conductive path of a first memory die of the set of memory dies. The operations of610may be performed according to the methods described herein.

At615, the wafer may determine, at a first logic circuit of the wafer, to communicate the second signal to a second CA conductive path of a second memory die of the set of memory dies based on the test configuration. The operations of615may be performed according to the methods described herein.

At620, the wafer may communicate, using the first logic circuit, the second signal to the second CA conductive path of the second memory die based on determining to communicate the second signal to the second memory die. The operations of620may be performed according to the methods described herein.

In some examples, an apparatus as described herein may perform a method or methods, such as the method600. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving, at a wafer that includes a set of memory dies, a first signal indicating a test configuration of the wafer, receiving, from a probe card, a second signal at a first CA conductive path of a first memory die of the set of memory dies, determining, at a first logic circuit of the wafer, to communicate the second signal to a second CA conductive path of a second memory die of the set of memory dies based on the test configuration, and communicating, using the first logic circuit, the second signal to the second CA conductive path of the second memory die based on determining to communicate the second signal to the second memory die.

Some examples of the method600and the apparatus described herein may further include operations, features, means, or instructions for determining, at a second logic circuit of the wafer, to communicate the second signal to a third CA conductive path of a third memory die of the set of memory dies based on the test configuration, and communicating, using the second logic circuit, the second signal to the third CA conductive path of the third memory die based on determining to communicate the second signal to the third memory die.

In some examples of the method600and the apparatus described herein, communicating the second signal to the second CA conductive path may include operations, features, means, or instructions for communicating the second signal via a first subset of the first logic circuit, the first subset of the first logic circuit coupled with the first CA conductive path and the second CA conductive path.

Some examples of the method600and the apparatus described herein may further include operations, features, means, or instructions for generating, at a second subset of the first logic circuit and based on determining to communicate the second signal to the second CA conductive path, a control signal for the first subset of the first logic circuit to transmit the second signal to the second CA conductive path, and communicating the control signal with the first subset of the first logic circuit, where communicating the second signal via the first subset of the first logic circuit may be based on communicating the control signal with the first subset of the first logic circuit.

Some examples of the method600and the apparatus described herein may further include operations, features, means, or instructions for determining, at a second logic circuit of the wafer, to suppress communication of the second signal to a third CA conductive path of a third memory die of the set of memory dies based on the test configuration, and suppressing communication of the second signal from the second CA conductive path to the third CA conductive path using the second logic circuit and based on determining to suppress communication of the second signal to the third memory die.

In some examples of the method600and the apparatus described herein, determining to suppress communication of the second signal to the third CA conductive path may include operations, features, means, or instructions for determining, at a second subset of the second logic circuit, that the third CA conductive path may be isolated from the second CA conductive path based on the test configuration, where suppressing communication of the second signal from the second CA conductive path to the third CA conductive path may be based on determining that the third CA conductive path may be isolated from the second CA conductive path. In some examples of the method600and the apparatus described herein, the second memory die may be free of physical contact from the probe card.

Some examples of the method600and the apparatus described herein may further include operations, features, means, or instructions for generating, at the second subset of the first logic circuit and based on determining to communicate the second signal to the second CA conductive path, a control signal for the first subset of the first logic circuit to suppress communication of the second signal from the second CA conductive path to the first CA conductive path and communicating the control signal with the first subset of the first logic circuit, where communicating the second signal via the first subset of the first logic circuit is based on communicating the control signal with the first subset of the first logic circuit.

Some examples of the method600and the apparatus described herein may further include operations, features, means, or instructions for communicating the second signal to a third memory die separated from the first memory die and the second memory die by one or more other memory dies, wherein the second signal is communicated via a plurality of logic circuits that comprises the first logic circuit and via multiple CA conductive paths that include the first CA conductive path and the second CA conductive path.

An apparatus is described. The apparatus may include a first memory die including a first CA pad for receiving a signal from a probe card and a first CA conductive path coupled with the first CA pad, a second memory die including a second CA conductive path, and a logic circuit in a region positioned between the first memory die and the second memory die, where the logic circuit may be configured to selectively couple the first CA conductive path of the first memory die with the second CA conductive path of the second memory die.

In some examples, the logic circuit may include a first circuit coupled with and configured to selectively communicate the signal between the first CA conductive path and the second CA conductive path. In some examples, the logic circuit further may include a second circuit coupled with the first circuit, the first CA conductive path, and the second CA conductive path, the second circuit configured to control the first circuit to selectively communicate the signal. In some examples, the first memory die further may include a first signal pad for receiving a second signal from the probe card, the first signal pad coupled with the second circuit, and the second memory die further may include a second signal pad for receiving a third signal from the probe card, the second signal pad coupled with the second circuit.

Some examples of the apparatus may include a layer of material for routing signals to a set of memory dies that includes the first memory die and the second memory die, where the layer of material may be coupled with the set of memory dies. Some examples of the apparatus may include a set of CA pads located in the layer of material, the set of CA pads including the first CA pad, and a set of CA conductive paths located in the layer of material, the set of CA conductive paths including the first CA conductive path and the second CA conductive path.

Some examples of the apparatus may include a third memory die including a third CA conductive path, and a second logic circuit in a second region positioned between the second memory die and the third memory die, where the second logic circuit may be configured to selectively couple the second CA conductive path of the second memory die with the third CA conductive path of the third memory die. In some examples, the apparatus may include a third circuit coupled with and configured to selectively communicate the signal between the second CA conductive path and the third CA conductive path. In some examples, the first CA conductive path, the logic circuit, the second CA conductive path, and the second logic circuit may be configured to selectively communicate the signal between the first CA conductive path and the third CA conductive path.

An apparatus is described. The apparatus may include a memory die, a layer of material for routing signals to the memory die, where the layer of material may be coupled with the memory die. The layer of material may include a first CA conductive path associated with the memory die and having a first end that is coupled with the first CA pad and a second end that terminates at an edge of the layer of material and a second CA conductive path associated with the memory die and having a third end that is coupled with the first CA pad and a fourth end that terminates at the edge of the layer of material.

Some examples of the apparatus may include a gap in the layer of material that begins at the edge of the layer of material and terminates at a second edge of the layer of material. Some examples of the apparatus may include a second memory die coupled with the layer of material, where the layer of material further may further include a third CA conductive path associated with the second memory die and having an end that terminates at the second edge of the layer of material and a fourth CA conductive path associated with the second memory die and having an end that terminates at the second edge of the layer of material.

The term “layer” or “level” used herein refers to a stratum or sheet of a geometrical structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers or levels may include different elements, components, and/or materials. In some examples, one layer or level may be composed of two or more sublayers or sublevels.