Self-aligned thin film transistor and fabrication method thereof

Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims priority from Korean Patent Application No. 10-2012-0133471, filed on Nov. 23, 2012, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

TECHNICAL FIELD

The present disclosure relates to a self-aligned thin film transistor, and a fabrication method thereof, and more particularly, to a technology of forming source and drain electrodes of a thin film transistor with a separate electrode material, not by doping for an oxide semiconductor.

BACKGROUND

A thin film transistor employing an oxide semiconductor as an active layer may be processed at a low temperature and with low costs, and also obtain a high mobility characteristic, thereby attracting attentions as a backplane device of an active drive-type display. Recently, technologies of forming source and drain electrodes so as to be self-aligned by using a gate electrode as a mask in manufacturing an oxide semiconductor thin film transistor have been suggested.

FIG. 1is a configuration diagram of a thin film transistor in the related art.

In the related arts, source and drain electrodes are formed by doping hydrogen in source and drain regions or performing a plasma treatment on the source and drain regions. However, in a case where the aforementioned methods are performed, as a subsequent process, such as a heat treatment, is performed, a doping effect gradually deteriorates, so that there is a possibility in that an operation characteristic of a transistor will deteriorate. In a case where an element, other than hydrogen, is doped, an activation temperature of a dopant is high, so that a problem may occur in that it is difficult to apply the method to a substrate, such as glass or plastic, having a poor heat resistance characteristic.

In order to implement a high resolution display, a region occupied by a thin film transistor within one pixel may be decreased by minimizing a size of the thin film transistor, and according to the related art, it is necessary to form the source and drain electrodes through the doping and then connect a separate wiring electrode to source and drain electrodes of the thin film transistor for an electronic circuit configuration. In this case, as illustrated inFIG. 1, in order to form an electrode connected to the source and drain regions, a margin necessary for mask alignment and a margin for a length and a width of a contact hole are generated, and as a result, there is a problem in that widths of the source and drain regions are increased.

SUMMARY

The present disclosure has been made in an effort to provide a thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned by using a separate electrode material, not by doping, and a fabrication method thereof.

An exemplary embodiment of the present disclosure provides a method of fabricating a self-aligned thin film transistor, including: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.

In the etching, the gate layer may be etched so that a width of the gate electrode is smaller than a shape of the photoresist layer pattern. The active layer may be etched by adjusting an etching depth so that a part of a bottom portion of the active layer is left on the substrate.

The method may further include, when parts of the formed source electrode and drain electrode are formed on side walls of the etched active layer and gate insulator to be in contact with the gate electrode, oxidizing the parts of the source electrode and the drain electrode through a heat or plasma treatment.

Another exemplary embodiment of the present disclosure provides a method of fabricating a thin film transistor, including: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a first photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the first photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; forming a second photoresist layer pattern for defining a shape of a source electrode and a drain electrode on the source and drain layer; etching the source and drain layer by using the second photoresist layer pattern; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the first and second photoresist layer patterns.

Yet another exemplary embodiment of the present disclosure provides a self-aligned thin film transistor, including: a substrate; an active layer formed on the substrate; a source electrode and a drain electrode formed on the substrate and self-aligned in both side surfaces of the active layer; a gate insulator formed on the active layer; and a gate electrode formed on the gate insulator.

According to the exemplary embodiments of the present disclosure, it is possible to provide a thin film transistor capable of minimizing parastic capacitor generation between a gate electrode and source and drain electrodes to achieve a high-speed operation, guaranteeing operation stability, and having a smaller size.

According to the exemplary embodiments of the present disclosure, a gate insulator and a gate electrode are deposited right after deposition of an oxide semiconductor layer (active layer), so that the insulator and the electrode may serve as a passivation layer, thereby preventing damage that may occur during various processes. Accordingly, it is possible to improve performance and reliability of a device, and an operation characteristic of the thin film transistor does not deteriorate even though a subsequent process including heat treatment is performed.

A high-temperature process for activating a dopant is not required when the thin film transistor is fabricated, so that the present disclosure may be applied to a substrate, such as glass or plastic.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawing, which form a part hereof. The illustrative embodiments described in the detailed description, and drawings are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the scope of the invention.

FIGS. 2A to 2Fare views for describing a method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure.

Referring toFIGS. 2A to 2F, a method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes sequentially forming an active layer203, a gate insulator205, and a gate layer207on a substrate201, forming a photoresist layer pattern209for defining a shape of a gate electrode on the gate layer207, sequentially etching the gate layer207, the gate insulator205, and the active layer203by using the photoresist layer pattern209, depositing a source and drain layer211on the etched substrate201by a deposition method having directionality, and forming a gate electrode207a, and self-aligned source electrode211aand drain electrode211bby removing the photoresist layer pattern209.

First, as illustrated inFIG. 2A, the active layer203, the gate insulator205, and the gate layer207are sequentially deposited on the substrate201, such as glass or plastic.

The active layer203may be formed of an oxide semiconductor, and the oxide semiconductor may be formed of zinc oxide (ZnO), indium oxide (InO), indium gallium zinc oxide (In—Ga—Zn—O), and zinc tin oxide (Zn—Sn—O), or oxide containing at least two elements among zinc (Zn), indium (In), gallium (Ga), tin (Sn), and aluminum (Al). Otherwise, the oxide semiconductor may be formed by doping various elements, for example, Zr, Hf, B, and Ni, on the oxide, or adding the various elements to the oxide in a form of a compound.

The gate layer may be formed of a material containing at least one of aluminum (Al), an aluminum alloy (Al alloy), tungsten (W), copper (Cu), nickel (Ni), chrome (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), indium tin oxide (ITO), and indium zinc oxide (IZO).

Next, as illustrated inFIGS. 2B and 2C, the photoresist layer pattern209having the shape of the gate electrode is formed on the gate layer207, and then the gate layer207, the gate insulator205, and the active layer203are sequentially etched by using the photoresist layer pattern209as an etching mask. Through this, the gate electrode207ais formed on the etched active layer203aand gate insulator205a.

Next, as illustrated inFIGS. 2D and 2E, the source and drain layer211is deposited by the deposition method having directionality and then the photoresist layer pattern209is removed. Through this, the source and drain layer present on the gate electrode207ais removed, so that the self-aligned source electrode211aand drain electrode211bare formed on the gate electrode207a.

Subsequently, as illustrated inFIG. 2F, electrodes215,215a, and215b, and a passivation layer213for transceiving data may be further formed while being in contact with the gate electrode207a, the source electrode211a, and the drain electrode211b, respectively.

FIGS. 3A and 3Eare views for describing a method of fabricating a thin film transistor according to another exemplary embodiment of the present disclosure.

First, as illustrated inFIGS. 3A and 3B, an active layer303, a gate insulator305, and a gate layer307are sequentially deposited on a substrate301, and then a photoresist layer pattern309is formed. In this case, a slope of a side wall of the photoresist layer pattern309may be negative.

Next, as illustrated inFIGS. 3C and 3D, the gate layer307, the gate insulator305, and the active layer303are sequentially etched by using the photoresist layer pattern309as an etching mask, and a source and drain layer311is deposited thereon by a deposition method having directionality. In this case, as illustrated inFIG. 3C, the active layer303is not totally etched, but may be partially left, and through this, a better contact between a source electrode311aand a drain electrode311b, and an active layer303ato be subsequently formed may be achieved. A side wall of the etched active layer303amay have a positive slope, so that it is possible to prevent void from being generated between the active layers303awhen the source and drain layer311is deposited.

Next, as illustrated inFIG. 3E, the self-aligned source electrode311aand drain electrode311bare formed on a gate electrode307aby removing the photoresist layer pattern309.

In the meantime, in the exemplary embodiment ofFIGS. 3A to 3E, there may occur a case where a source and drain layer411completely covers the etching shape of the gate electrode307abecause directionality of the deposition method is weak when the source and drain layer411is formed as illustrated inFIG. 4, so that in this case, it is not easy to remove the photoresist layer pattern309. In order to prevent the aforementioned case, a gate electrode507may be formed in a form having a narrower width than a shape of the photoresist layer pattern309by etching the gate layer307more deeply as illustrated inFIGS. 5A and 5B. In this case, a shading region is generated under the photoresist layer pattern309, so that a source and drain layer511is not deposited on a side wall of the gate electrode507, and through this, a short phenomenon due to a contact between the gate electrode507and the source and drain layer511may be prevented.

In a case where the gate electrode507is in contact with a source and drain layer611as illustrated inFIG. 6even though the method illustrated inFIGS. 5A and 5Bis used, a insulator may be formed by oxidizing a part of the source and drain layer611through a heat or plasma treatment as illustrated inFIG. 7. In this case, a part of the deposited source and drain layer611deposited on the side wall portions of the gate electrode507and a gate insulator305ato meet the gate electrode507may be oxidized to be a nonconductor, and parts of a source electrode311aand a drain electrode311bmeeting the active layer303amay not be oxidized.

In the meantime, as illustrated inFIG. 8, a photoresist layer pattern801may be additionally formed in order to define a shape of the source electrode211aand the drain electrode211bin the exemplary embodiment ofFIGS. 2A to 2F. In this case, source and drain regions are defined by forming the photoresist layer pattern801having the shape of the source and drain electrodes211aand211bbefore removing the photoresist layer pattern209having the shape of the gate electrode207a, and the two photoresist layer patterns209and801may be removed at the same time. In another case, source and drain electrodes211aand211bare defined by forming the photoresist layer pattern801after having removed the photoresist layer pattern209.

FIG. 9is a graph illustrating drain current Idaccording to a gate voltage Vgof the thin film transistor actually fabricated according to the exemplary embodiments of the present disclosure, and it can be seen that a general switching operation of the thin film transistor is smoothly performed.