Display panel

A display panel includes: a base substrate; a peripheral circuit located on the base substrate, the peripheral circuit including a first circuit, a second circuit and a third circuit, and the first circuit, the second circuit and the third circuit respectively including a first electrode pattern, a second electrode pattern and a third electrode pattern; and a protection structure, located in at least one circuit of the first circuit, the second circuit and the third circuit and configured for preventing an electrode pattern from being disconnected.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Chinese Patent Application No. 201710332764.4 filed on May 12, 2017, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Embodiments of the present disclosure relate to a display panel.

BACKGROUND

A fabrication procedure of a display device comprises a bonding process of bonding a circuit structure of a peripheral region of a display panel to an external circuit. However, while the above-described circuit structure of the peripheral region is bonded, an electrode pattern located on a surface of the circuit may be scratched, which further results in a problem such as electrode disconnection.

SUMMARY

Embodiments of the present disclosure provide a display panel, wherein, one objective is to prevent a peripheral circuit of the display panel from being scratched.

According to an embodiment of the present disclosure, it is provided a display panel, comprising: a base substrate; a peripheral circuit located on the base substrate, the peripheral circuit comprising a first circuit, a second circuit and a third circuit, and the first circuit, the second circuit and the third circuit respectively comprising a first electrode pattern, a second electrode pattern and a third electrode pattern; and a protection structure, located in at least one circuit of the first circuit, the second circuit and the third circuit and configured for preventing an electrode pattern located in the at least one circuit from being disconnected.

DETAILED DESCRIPTION

FIG. 1is a structural schematic diagram of a display panel related to the present disclosure. As illustrated inFIG. 1, it is a structural schematic diagram of a flexible printed circuit (FPC), a contact electrode02is provided on a substrate structure01, and a planarization layer03is formed on the substrate structure01on which the contact electrode02is formed. When the FPC is bonded to an external circuit board, an electrode in the external circuit board may be electrically connected with the contact electrode02.

FIG. 2-1is a structural schematic diagram of various circuits according to an embodiment of the present disclosure. A display panel10comprises: an active region A (i.e., a display region) and a peripheral region B, the peripheral region B is provided therein with a peripheral circuit12, and the peripheral circuit12may comprise a Chip On Glass (COG) circuit12A, a FanOut circuit12B and an FPC12C. A structure of the FPC12C may be as illustrated inFIG. 1. The COG circuit12A is configured for bonding to an integrated circuit (IC), the FanOut circuit12B is configured for connecting with the bonded IC, and the FPC12C is configured for connecting with an external circuit board.

FIG. 2-2is a structural schematic diagram of the COG circuit12A according to the present disclosure. A source-drain contact electrode1211is formed on a substrate structure51, and is easily scratched and disconnected.FIG. 2-3is a structural schematic diagram of the FanOut circuit12B according to the present disclosure. The source-drain contact electrode1211is formed on the substrate structure51, and a planarization layer126and a Pixel definition layer (PDL)52are formed above the source-drain contact electrode1211. The PDL52may be made of polyimide (PI), and the planarization layer126and the pixel definition layer52are both soft in material, so it is difficult to protect the source-drain contact electrode1211from being scratched.

An embodiment of the present disclosure provides a display panel, comprising: a base substrate; a peripheral circuit located on the base substrate; the peripheral circuit comprising a first circuit, a second circuit and a third circuit, the first circuit, the second circuit and the third circuit respectively comprising a first electrode pattern, a second electrode pattern and a third electrode pattern; and a protection structure, located in at least one circuit of the first circuit, the second circuit and the third circuit, the protection structure comprises at least one of the first electrode pattern, the second electrode pattern and the third electrode pattern, for preventing an electrode pattern located in the at least one circuit from being disconnected.

In at least some embodiments, the first circuit is a Chip On Glass circuit, the second circuit is a flexible printed circuit, and the third circuit is a FanOut circuit.

In at least some embodiments, the protection structure is located in at least two circuits of a Chip On Glass circuit, a flexible printed circuit and a FanOut circuit, or located in each of the above-described circuits.

In at least some embodiments, the first electrode pattern, the second electrode pattern and the third electrode pattern respectively comprise a plurality of source-drain contact electrodes.

In the display panel provided by the embodiments of the present disclosure, by providing the protection structure, the source-drain contact electrode pattern is prevented from being scratched and disconnected, which solves the problem in the related art that the source-drain contact electrode pattern may be scratched and even disconnected while the circuit structure of the peripheral region is bonded, and achieves an effect that the source-drain contact electrode pattern is not easily scratched.

For example,FIG. 3is a cross-sectional view of a peripheral circuit of a display panel according to an embodiment of the present disclosure. The display panel10may comprise: a base substrate11; a peripheral circuit12is provided on the base substrate11, and a source-drain contact electrode pattern121is provided in the peripheral circuit12. A protective layer20is provided on the base substrate11which is provided with the peripheral circuit12, and the protective layer20is configured for preventing the source-drain contact electrode pattern121from being disconnected.

Hereinafter, the protection structure in each of three circuits comprising a Chip On Glass circuit, a flexible printed circuit and a FanOut circuit will be described in the embodiments of the present disclosure.

For convenience of description,FIG. 4-1,FIG. 4-2andFIG. 4-3only illustrate a Chip On Glass circuit12A in the peripheral circuit of the display panel, and a structure of the display region of the display panel will not be discussed here.

With reference toFIG. 4-1, in at least some embodiments, a peripheral circuit comprises a Chip On Glass circuit12A, and a protection structure in the Chip On Glass circuit12A comprises a dielectric layer34, an electrode pattern and a protective layer20sequentially provided on a base substrate11. The dielectric layer34comprises at least one first via hole K1, and at least a portion of the electrode pattern is in contact with and overlays a peripheral edge of the at least one first via hole K1. The protective layer20is in contact with and overlays the at least one portion of the electrode pattern.

In at least some embodiments, an electrode pattern comprises a source-drain contact electrode pattern121, and the source-drain contact electrode pattern121comprises a plurality of source-drain contact electrodes1211.FIG. 4-1shows one of the source-drain contact electrodes1211, and the source-drain contact electrode pattern121may further comprise more than one source-drain contact electrode1211, which will not be specifically illustrated in the embodiments of the present disclosure.

As illustrated inFIG. 4-1, at least a portion of the source-drain contact electrode pattern121is in contact with and overlays the peripheral edge of the at least one first via hole K1; in other words, the source-drain contact electrode pattern121surrounds the periphery of the first via hole K1. The first protective layer20overlays a peripheral edge of each of the plurality of source-drain contact electrodes1211. The protective layer20may be simultaneously formed with a pixel electrode of the display panel by a single patterning process, without increasing the number of patterning processes. Here, “single patterning process” refers to patterning performed with a same mask, and the “patterning process” refers to, for example, coating a layer of photoresist, exposing and developing with a mask, then etching, and other processes. The protective layer20is made of a transparent conductive material, which may comprise, for example, Indium tin oxide (ITO). ITO has higher hardness, and is capable of effectively protecting the source-drain contact electrode.

The base substrate11may be further provided thereon with a buffer layer31, a gate insulating layer32is provided on the base substrate11having the buffer layer31formed thereon, a gate electrode33is provided on the base substrate11having the gate insulating layer32formed thereon, a dielectric layer34is provided on the base substrate11having the gate electrode33formed thereon, the first via holes K1in one to one correspondence with the plurality of source-drain contact electrodes1211may be provided on the dielectric layer34, and each source-drain contact electrode1211may be in contact with the gate electrode33through one of the first via holes K1therein. At least a portion of the source-drain contact electrode1211overlays an inner wall of the first via hole K1, and the protective layer20further extends into the first via hole K1. That is to say, the protective layer20is in contact with and overlays all surfaces of the source-drain contact electrode1211which protrudes from a surface of the dielectric layer34.

The Chip On Glass circuit12A illustrated inFIG. 4-1protects the source-drain contact electrode1211through the protective layer20which overlays the peripheral edge of the electrode pattern, so that the source-drain contact electrode1211is not easily scratched, which reduces possibility of disconnection. At the same time, the source-drain contact electrode1211has other regions exposed, in addition to edges overlaid by the protection structure, as a result, while the source-drain contact electrode is bonded, a resistance will not be too large, which reduces impact caused by an IR Drop phenomenon.

As illustrated inFIG. 4-2, a Chip On Glass circuit12A according to another embodiment of the present disclosure comprises a source-drain contact electrode pattern121, a dielectric layer34and a gate electrode33. The dielectric layer34comprises a plurality of first via holes K1, and the source-drain contact electrode pattern121comprises a plurality of source-drain contact electrodes1211. The dielectric layer34may be an inter-layer Dielectric (ILD). Other reference numerals inFIG. 4-2may be referred to those inFIG. 4-1, which will not be repeated here.

The gate electrode33is provided on a base substrate11. The dielectric layer34is provided on the base substrate11having the gate electrode33formed thereon. The source-drain contact electrode pattern121is provided on the base substrate11having the dielectric layer34formed thereon, and is in contact with the gate electrode33through the plurality of first via holes K1; and the plurality of source-drain contact electrodes1211corresponds to the plurality of first via holes K1one by one.

The source-drain contact electrode1211comprises a plurality of second via holes K2, the second via hole K2is, for example, located at the bottom of the first via hole K1, the gate electrode33is exposed at the second via hole K2, and the source-drain contact electrode1211is in contact with the gate electrode33through the first via hole K1. In this way, the gate electrode33may be taken as a contact electrode during bonding, and the source-drain contact electrode1211may be configured for protecting the gate electrode33, to prevent the gate electrode33from being scratched.

In at least some embodiments, a protection structure inFIG. 4-2further comprises a protective layer20, which overlays an edge of each of a plurality of source-drain contact electrodes1211. The protective layer20may be simultaneously formed with a pixel electrode by using same patterning process, and is made of ITO. The protective layer20may further enhance a scratch-resistant ability of the source-drain contact electrode1211.

As illustrated inFIG. 4-3, in at least some embodiments, a source-drain contact electrode pattern121is a laminated structure, the laminated structure comprises a first metal layer C1in contact with a gate electrode33, a second metal layer C2in contact with the first metal layer C1, and a third metal layer C3in contact with the second metal layer C2, and a thickness of the third metal layer C3is greater than a thickness of the first metal layer C1. In the related art, the thickness of the third metal layer C3is generally equal to the thickness of the first metal layer C1; and in the embodiment of the present disclosure, the thickness of the top third metal layer C3is increased, so as to increase a scratch-resistant ability of the source-drain contact electrode pattern121.

In at least some embodiments, the first metal layer C1and the third metal layer C3are titanium metal layers, and the titanium metal layer has a relatively strong scratch-resistant ability; the metal layer is an aluminum metal layer, and the aluminum metal layer has a relatively high electrical conductivity.

For convenience of description,FIG. 5-1,FIG. 5-2andFIG. 5-3only illustrate the flexible printed circuit12C in the peripheral circuit of the display panel, and a structure of the display region of the display panel will not be discussed here.

For convenience of description,FIG. 4-1,FIG. 4-2andFIG. 4-3only illustrate the Chip On Glass circuit12A in the peripheral circuit of the display panel, and the related art may be referred to for other structures of the display panel, which will not be repeated here.

In the display panel provided by the above-described embodiments of the present disclosure, by providing the protection structure, the source-drain contact electrode pattern is prevented from being scratched, which solves the problem in the related art that the source-drain contact electrode pattern may be scratched and even disconnected, when the circuit structure of the peripheral region is bonded, and achieves an effect that the source-drain contact electrode pattern is not easily scratched.

As illustrated inFIG. 5-1, the peripheral circuit comprises a flexible printed circuit12C, the protection structure in the flexible printed circuit12C comprises a source-drain contact electrode pattern121, a planarization layer124and a protective layer20; and a thickness of the planarization layer124is greater than a thickness of the source-drain contact electrode pattern121.

In at least some embodiments, a base substrate11is provided thereon with a source-drain contact electrode pattern121, and the source-drain contact electrode pattern121comprises a plurality of source-drain contact electrodes1211. A planarization layer124is provided on the base substrate11having the source-drain contact electrode pattern121formed thereon, the planarization layer124comprises a plurality of third via holes K3, and the plurality of third via holes K3correspond to the plurality of source-drain contact electrodes1211one by one. The source-drain contact electrode1211is provided in the third via hole K3.

A protective layer20overlays the planarization layer124and extends to the bottom of the third via hole K3, so as to be in contact with the source-drain contact electrode1211. Since the planarization layer124is generally soft and easy to be scratched, the planarization layer124may be covered with the protective layer20, to enhance a scratch-resistant ability of the planarization layer124; under protection of the planarization layer124, the source-drain contact electrode pattern121is also not easily scratched. The protective layer20overlays an entire outer surface of the planarization layer124and acts as an outermost layer. For a material of the protective layer20, the foregoing embodiments may be referred to.

A buffer layer31may be further provided on the base substrate11, a gate insulating layer32is provided on the base substrate11having the buffer layer31formed thereon, and a dielectric layer34is provided on the base substrate11having the gate insulating layer32formed thereon.

As illustrated inFIG. 5-2, in at least some embodiments, a protective layer20may also be provided only on a side surface of a planarization layer124, and the side surface is adjacent to a third via hole K3, which may also achieve an effect of enhancing a scratch-resistant ability of the planarization layer124. Other reference numerals inFIG. 5-2may be referred to those inFIG. 5-1, which will not be repeated here.

As illustrated inFIG. 5-3, in at least some embodiments, a protection structure of a flexible printed circuit12C comprises a source-drain contact electrode pattern121and an interlayer insulating layer122; and the interlayer insulating layer122is provided with a plurality of fourth via holes K4. The interlayer insulating layer122may be an inter-layer dielectric.

A source-drain contact electrode pattern121is provided on a base substrate11having the interlayer insulating layer122formed thereon, the source-drain contact electrode pattern121comprises a plurality of source-drain contact electrodes1211, the plurality of source-drain contact electrodes1211are provided in the plurality of fourth via holes K4, and the plurality of source-drain contact electrodes1211correspond to the plurality of fourth via holes K4one by one.

A planarization layer124is provided on the base substrate11having the source-drain contact electrode pattern121formed thereon, the planarization layer124comprises a plurality of third via holes K3, and the plurality of third via holes K3correspond to the plurality of source-drain contact electrodes1211one by one, so that each source-drain contact electrode1211may be exposed from the third via hole K3. The source-drain contact electrode pattern121is in contact with and overlays a peripheral edge of the fourth via hole, and the source-drain contact electrode pattern121extends into a contact region between the planarization layer124and the interlayer insulating layer122.

As illustrated inFIG. 5-3, because the source-drain contact electrode pattern121is buried in the interlayer insulating layer122, the source-drain contact electrode pattern121is not easily scratched.

In addition, a protective layer20as illustrated inFIG. 5-1may also be formed on the planarization layer124inFIG. 5-3, to further protect the source-drain contact electrode pattern121.

Other reference numerals inFIG. 5-3may be referred to those inFIG. 5-1, which will not be repeated here.

In the display panel provided by the above-described embodiments of the present disclosure, by providing the protection structure, the source-drain contact electrode pattern is prevented from being scratched, which solves the problem in the related art that the source-drain contact electrode pattern may be scratched and even disconnected, when the circuit structure of the peripheral region is bonded, and achieves an effect that the source-drain contact electrode pattern is not easily scratched.

For convenience of description,FIG. 6-1andFIG. 6-2only show the FanOut circuit12B in the peripheral circuit of the display panel, and a structure of the display region of the display panel will not be discussed here.

In at least some embodiments, a peripheral circuit comprises a FanOut circuit12B, and a protection structure in the FanOut circuit12B comprises a source-drain contact electrode pattern121, a planarization layer126and a protective layer20.

For example, a source-drain contact electrode pattern121is provided on a base substrate11, and a planarization layer126is provided on the base substrate11having the source-drain contact electrode pattern121formed thereon. A protective layer20is provided on the base substrate11having the planarization layer126formed thereon, an orthographical projection of the source-drain contact electrode pattern121on the base substrate11overlaps with an orthographical projection of the protective layer20on the base substrate11, that is, the protective layer20overlays right above the source-drain contact electrode pattern121to protect the source-drain contact electrode pattern121.

In addition, a pixel definition layer may also be formed on the base substrate having the protective layer20formed thereon, which will not be limited in the embodiment of the present disclosure.

In at least some embodiments, as illustrated inFIG. 6-2, it is a top view of a FanOut circuit12B in the display panel illustrated inFIG. 6-1. A protective layer20is composed of a plurality of blocky structures arranged at intervals. A source-drain contact electrode may exist below each blocky structure inFIG. 6-2. The spaced blocky structures may reduce material costs, and will not cause a problem such as disconnection, when the protective layer20is made of an electrically conductive material.

In at least some embodiments, a display panel comprises a pixel electrode pattern in a display region, and a protective layer20is provided in a same layer as the pixel electrode pattern. In this way, a protection structure may be provided without increasing the number of patterning processes.

In at least some embodiments, a protective layer20is made of, for example, indium tin oxide. Indium tin oxide is a harder material and may play a role in scratch resistance.

In the display panel provided by the above-described embodiments of the present disclosure, by providing the protection structure, the source-drain contact electrode pattern is prevented from being scratched and disconnected, which solves the problem in the related art that the source-drain contact electrode pattern may be scratched and even disconnected, when the circuit structure of the peripheral region is bonded, and achieves an effect that the source-drain contact electrode pattern is not easily scratched.

As illustrated inFIG. 7-1, it is a flow chart of a bonding method of a display panel provided by an embodiment of the present disclosure, which may be applied to the display panel illustrated in the above-described respective embodiments, and the bonding method of the display panel comprises:

Step701: providing a display panel and an external circuit.

The external circuit comprises an integrated circuit and an external circuit board.

Step702: bonding the external circuit to a peripheral circuit of the display panel.

The peripheral circuit may comprise a Chip On Glass circuit and a flexible printed circuit.

In the embodiment of the present disclosure, the Chip On Glass circuit and the flexible printed circuit may be separately bonded.

As illustrated inFIG. 7-2, the step may comprise two sub-steps below:

Sub-step7021: bonding the integrated circuit to the Chip On Glass circuit.

The bonding may be performed with an anisotropic conductive adhesive film.

Sub-step7022: bonding the external circuit board to the flexible printed circuit.

The bonding may be performed with an anisotropic conductive adhesive film.

In the bonding method of the display panel provided by the above-described embodiment of the present disclosure, by providing the protection structure, the source-drain contact electrode pattern during bonding is prevented from being scratched and disconnected, which solves the problem in the related art that the source-drain contact electrode pattern may be scratched and even disconnected, when the circuit structure of the peripheral region is bonded, and achieves an effect that the source-drain contact electrode pattern is not easily scratched.

In this disclosure, several points below need to be explained:

(1) The drawings of the embodiments of the present disclosure relate only to the structures involved in the embodiments of the present disclosure, and normal designs may be referred to for other structures.

(2) For the sake of clarity, in the drawings configured for describing the embodiments of the present disclosure, thicknesses of layers or regions are enlarged or reduced, that is, these drawings are not drawn in an actual scale.

(3) In case of no conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain a new embodiment.