Multi-level memory repurposing technology to process a request to modify a configuration of a persistent storage media

An embodiment of a semiconductor apparatus may include technology to receive a request to modify a configuration of a persistent storage media, and repurpose a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request. Other embodiments are disclosed and claimed.

TECHNICAL FIELD

Embodiments generally relate to memory and storage systems. More particularly, embodiments relate to multi-level memory repurposing.

BACKGROUND

A multi-level non-volatile memory stores more than one bit per cell. Multi-level NAND memory having four (4) possible voltage levels per cell may be referred to as multi-level cell (MLC) memory and may represent two (2) bits of data per cell. NAND memory having eight (8) voltage levels per cell may be referred to as triple-level cell (TLC) memory and may represent three (3) bits of data per cell. NAND memory having sixteen (16) voltage levels per cell may be referred to as quad-level cell (QLC) memory and may represent four (4) bits of data per cell.

DESCRIPTION OF EMBODIMENTS

NVM may be a storage medium that does not require power to maintain the state of data stored by the medium. In one embodiment, the memory device may include a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional (3D) crosspoint memory device, or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor RAM (FeTRAM), anti-ferroelectric memory, magnetoresistive RAM (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge RAM (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In particular embodiments, a memory component with non-volatile memory may comply with one or more standards promulgated by the JEDEC, such as JESD218, JESD219, JESD220-1, JESD223B, JESD223-1, or other suitable standard (the JEDEC standards cited herein are available at jedec.org).

Turning now toFIG. 1, an embodiment of a storage system10may include persistent storage media11including multiple bits per cell, a controller12communicatively coupled to the persistent storage media11, and logic13communicatively coupled to the controller12and the persistent storage media11to receive a request to modify a configuration of the persistent storage media11, and repurpose a region of the persistent storage media11from a first number of bits per cell to a second number of bits per cell in response to the request. In some embodiments, the logic13may be further configured to change a configuration of the region of the persistent storage media11from a higher number of bits per cell to a lower number of bits per cell. Additionally, or alternatively, the logic13may be configured to identify a defective region of the persistent storage media11, and switch a sense mode for the defective region to contain less bits per cell. For example, the logic13may be configured to determine if the defective region is non-defective with the switched sense mode, and repurpose the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode. In some embodiments, the logic13may be further configured to evaluate blocks of the persistent storage media11to identify blocks near cell failure, pool one or more sets of blocks identified to be near cell failure based on the number of bits per cell, and repurpose the region of persistent storage media11after a set of blocks has pooled a threshold number of blocks. For example, the logic13may also be configured to provide estimated performance capability information, wherein the estimated performance capability information may relate to one or more performance capabilities as would be understood to one of ordinary skill in the art. In such an example, the logic13may also be configured to provide estimated performance capability information based on the evaluation to identify blocks near cell failure to a host. In such an example, the logic13may also be configured to repurpose the region of persistent storage media11based on information received from the host in response to the provided estimated performance capability information. In any of the embodiments herein, the persistent storage media11may include a solid state drive (SSD). In some embodiments, the logic13may be located in, or co-located with, various components, including the controller12(e.g., on a same die).

Embodiments of each of the above persistent storage media11, controller12, logic13, and other system components may be implemented in hardware, software, or any suitable combination thereof. For example, hardware implementations may include configurable logic such as, for example, programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), or fixed-functionality logic hardware using circuit technology such as, for example, application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof. Embodiments of the controller12may include a general purpose controller, a special purpose controller, a memory controller, a storage controller, a storage manager, a processor, a central processor unit (CPU), a micro-controller, etc.

Alternatively, or additionally, all or portions of these components may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., to be executed by a processor or computing device. For example, computer program code to carry out the operations of the components may be written in any combination of one or more operating system (OS) applicable/appropriate programming languages, including an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C# or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. For example, the persistent storage media11, or other system memory may store a set of instructions which when executed by the controller12cause the system10to implement one or more components, features, or aspects of the system10(e.g., the logic13, receiving the request to modify the configuration of the persistent storage media, repurposing the region of the persistent storage media in response to the request, etc.).

Turning now toFIG. 2, an embodiment of a semiconductor apparatus20may include one or more substrates21, and logic22coupled to the one or more substrates21, wherein the logic22is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic. The logic22coupled to the one or more substrates21may be configured to receive a request to modify a configuration of a persistent storage media, and repurpose a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request. In some embodiments, the logic22may be further configured to change a configuration of the region of the persistent storage media from a higher number of bits per cell to a lower number of bits per cell. Additionally, or alternatively, the logic22may be configured to identify a defective region of the persistent storage media, and switch a sense mode for the defective region to contain less bits per cell. For example, the logic22may be configured to determine if the defective region is non-defective with the switched sense mode, and repurpose the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode. In some embodiments, the logic22may be further configured to evaluate blocks of the persistent storage media to identify blocks near cell failure, pool one or more sets of blocks identified to be near cell failure based on the number of bits per cell, and repurpose the region of persistent storage media after a set of blocks has pooled a threshold number of blocks. For example, the logic22may also be configured to provide estimated performance capability information based on the evaluation to a host, and repurpose the region of persistent storage media based on information received from the host in response to the provided estimated performance capability information. In any of the embodiments herein, the persistent storage media may include a SSD. In some embodiments, the logic22coupled to the one or more substrates21may include transistor channel regions that are positioned within the one or more substrates21.

Embodiments of logic22, and other components of the apparatus20, may be implemented in hardware, software, or any combination thereof including at least a partial implementation in hardware. For example, hardware implementations may include configurable logic such as, for example, PLAs, FPGAs, CPLDs, or fixed-functionality logic hardware using circuit technology such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof. Additionally, portions of these components may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., to be executed by a processor or computing device. For example, computer program code to carry out the operations of the components may be written in any combination of one or more OS applicable/appropriate programming languages, including an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C# or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages.

The apparatus20may implement one or more aspects of the method30(FIGS. 3A to 3C), or any of the embodiments discussed herein. In some embodiments, the illustrated apparatus20may include the one or more substrates21(e.g., silicon, sapphire, gallium arsenide) and the logic22(e.g., transistor array and other integrated circuit/IC components) coupled to the substrate(s)21. The logic22may be implemented at least partly in configurable logic or fixed-functionality logic hardware. In one example, the logic22may include transistor channel regions that are positioned (e.g., embedded) within the substrate(s)21. Thus, the interface between the logic22and the substrate(s)21may not be an abrupt junction. The logic22may also be considered to include an epitaxial layer that is grown on an initial wafer of the substrate(s)21.

Turning now toFIGS. 3A to 3C, an embodiment of a method30of managing storage may include receiving a request to modify a configuration of a persistent storage media at block31, and repurposing a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request at block32. Some embodiments of the method30may further include changing a configuration of the region of the persistent storage media from a higher number of bits per cell to a lower number of bits per cell at block33. Additionally, or alternatively, some embodiments of the method30may include identifying a defective region of the persistent storage media at block34, and switching a sense mode for the defective region to contain less bits per cell at block35. For example, the method30may further include determining if the defective region is non-defective with the switched sense mode at block36, and repurposing the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode at block37. Some embodiments of the method30may further include evaluating blocks of the persistent storage media to identify blocks near cell failure at block38, pooling one or more sets of blocks identified to be near cell failure based on the number of bits per cell at block39, and repurposing the region of persistent storage media after a set of blocks has pooled a threshold number of blocks at block40. For example, the method30may further include providing estimated performance capability information based on the evaluation to a host at block41, and repurposing the region of persistent storage media based on information received from the host in response to the provided estimated performance capability information at block42. In any of the embodiments herein, the persistent storage media may include a SSD at block43.

Embodiments of the method30may be implemented in a system, apparatus, computer, device, etc., for example, such as those described herein. More particularly, hardware implementations of the method30may include configurable logic such as, for example, PLAs, FPGAs, CPLDs, or in fixed-functionality logic hardware using circuit technology such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively, or additionally, the method30may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., to be executed by a processor or computing device. For example, computer program code to carry out the operations of the components may be written in any combination of one or more OS applicable/appropriate programming languages, including an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C# or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages.

For example, the method30may be implemented on a computer readable medium as described in connection with Examples 23 to 29 below. Embodiments or portions of the method30may be implemented in firmware, applications (e.g., through an application programming interface (API)), or driver software running on an operating system (OS). Additionally, logic instructions might include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, state-setting data, configuration data for integrated circuitry, state information that personalizes electronic circuitry and/or other structural components that are native to hardware (e.g., host processor, central processing unit/CPU, microcontroller, etc.).

Some embodiments may advantageously provide technology for just-in-time (JIT) memory block repurposing in solid state drives (SSDs) for extended life and/or increased performance (e.g., at the cost of user space). For example, such repurposing may be useful to reclaim blocks of multi-level memory cells which previously were identified as non-defective, but which may no longer meet performance or reliability requirements at a higher level (e.g., became defective at the higher level for whatever reason). Some embodiments may advantageously evaluate such defective blocks to determine if they are able to meet performance or reliability requirements at a lower level and, if so, repurpose the blocks at the lower level such they may be made available for storage utilization.

Another example of a useful application for JIT memory block repurposing may include datacenter applications, cloud services, function as a service (FaaS), etc., where a service provider needs to manage resources to meet workload or customer needs/requirements. As described in more detail below, multi-level memory technology provides some trade-offs between storage space, speed, and endurance. By providing the flexibility to dynamically provision storage space for individual SDD devices, some embodiments may advantageously support JIT or on-demand reconfiguration of a storage solution based on current workload, predicted workload, customer requests, etc. For example, a cloud service provider may reconfigure a SSD from higher capacity and slower speeds to lower capacity and higher speeds for a workload that requires higher bandwidth, but not as much storage capacity (e.g., from QLC to TLC, or MLC). Conversely, a cloud service provider may reconfigure the SSD from lower capacity to higher capacity for a workload that requires more storage capacity (e.g., from TLC to QLC).

Turning now toFIG. 4, an illustrative diagram of a persistent storage media46may include storage structure including one or more media die48. The media die48may include storage device technology derived from a silicon wafer (e.g. NAND flash technology). A SSD may include one or more such media die48(e.g., more than one die may be packaged into a physical device). Examples of the packaging may include single die package (SDP, one (1) media die per physical device), dual die package (DDP, two (2) media die per physical device), octal die package (ODP, eight (8) media die per physical device), etc. (e.g., to the technology limitation). Each media die48may include multiple erase blocks (EBs), which may refer to the smallest element at which a block can be erased. Each EB may include multiple page blocks (PBs), which may refer to the smallest element for programming. Each of the PBs may include a collection of sub-blocks (SBs), which may refer to the smallest read granularity for density purposes. Each SB may include multiple cells or cell blocks (CBs).

As a media technology advances, more information may be packed into the fundamental CBs. For example, a CB may represent anywhere from 1 bit per cell (single level cell (SLC) to N bits per cell. The current N for some technology media set is four (4), such that a tier stepping of 1 (SLC), 2 (MLC), 3 (TLC), and 4 (QLC) may be provided for that media technology. Each of these tiers may also be referred to as programming modes (PM). Table 1 shows example illustrative performance information for each tier:

TABLE 1SLCMLCTLCQLCErase Cycles100,00030,00010,0005,000Bits Per Cell1234Write Speed (μs)362139120872782Read Speed (μs)32-5557-6365-12386-163Erase Speed (ms)15151515
As shown in Table 1, the write and read speeds are reduced between each tier, indicating that operations one mode below may provide better performance. With each tier, the endurance of the cell differs so the decreasing mode will have much more endurance. Conventionally, a SSD is initially characterized/configured to meet device requirements (e.g., multiple types of memory (e.g., some SLC, some QLC, etc.), capacity, etc.) and the initial characterization remains unchanged (e.g., except for removing blocks which later become defective from the available storage capacity). Technologically, however, a CB may support all of the tiers/PMs up to the highest supported by the media (e.g., a QLC cell may support programming modes for SLC, MLC, TLC, and QLC). Some embodiments may advantageously re-characterize the CBs to switch the number of bits-per-block (e.g., to meet a different performance capability requirement, to reclaim defective blocks, etc.).

Due to the inherent imperfections of media, the potential of blocks may be reduced based on a conditional state change. For example, the state changes may occur at the factory, during manufacturing, in the field, etc., and may involve moving a previously good block to a defective block. For example, the state of no ability to use a PB may be referred to as a defective block (DB). The removal of the block decreases the potential user space based on the locality or sparse nature of the defects.

Turning now toFIG. 5, an illustrative diagram shows how SSD total physical space may be allocated between host space51and spare space52(not to scale). From a system perspective the SSD operation may require functionality spare space for run time operations, meta/system space for system details, spare space for write amplification (WA) reduction for garbage collection, and host data space. The WA space may be important to drive endurance. Considerations of drive critical spare space for operation, end of life effective spare, etc., all contribute to an absolute minimum spare space. As the physical spare space is modified, the WA may also be directly affected and change drive endurance based on cycling capability. Increasing the efficacy of writing to the physical spare will decrease the WA, increasing longevity due to the NP-Complete nature of algorithms. The algorithm complexity may be alleviated by adding spare to the total physical spare allowing more endurance. Some embodiments may provide logical re-enablement for repurposed memory blocks and may advantageously introduce system spare that may otherwise have been considered lost.

Turning now toFIG. 6, an illustrative diagram of a persistent storage media60may include multiple media die (e.g., Die1. . . Die K . . . Die M) with a storage structure which spans the media die. For example, the granularity of the elements may be of disjoint size so the interaction between the blocks are staged such that the greatest common denomination may correspond to a transitioning set (TS) referred to as a band. For example, a unique feature of a band is that the set consists of concurrent EBs for the media technology to ease meta tracking. To maintain the table, some implementations may use an indirection table to ensure band collections are optimized based on media rules for data integrity. Conventional SSD technology throws away sets of blocks of media as a preventative measure to ensure product performance. Static assignment of blocks out of the factory are mapped to help mitigate low performing sets of blocks. This initial assignment may occur one-time at the factory prior to deploying the SSD in any storage solution or application. As the SSD is used over time, defects may be encountered within the internal memory blocks. Conventional SSDs may retire these blocks, removing system space until the SSD reaches a critical point for drive failure. After the retired memory blocks exceed a threshold amount (e.g., based on a specified product performance requirement), the reduced storage space may impact performance and uniformity consistency. At the failure mode, the SSD may no longer usable at the customer so they are discarded.

In contrast to conventional SSDs, some embodiments may dynamically repurpose memory blocks to reclaim defective blocks (e.g., in the field, after initial deployment). Repurposing the memory blocks may advantageously increase storage capacity (e.g., as compared to retiring the defective block), increase performance (e.g., going from a higher level of bits to a lower level of bits), and increase endurance (e.g., going from a higher level of bits to a lower level of bits). In some embodiments, an SSD with multi-level cell programming capability may ratchet down from higher bits per cell configurations to lower level bits per cell configurations (e.g., from QLC to TLC to MLC to SLC) rather than retiring entire blocks of storage, thereby increasing lifespan (e.g., durability) and performance at the cost of reduction in user space (e.g., from non-defective blocks, but increasing user space as compared to retiring defective blocks). Some embodiments may advantageously provide dynamic speeds in response to host requests for fast, medium, and slow bands (e.g., to satisfy the NVM EXPRESS (NVMe) 1.3 specification (nvmexpress.org)). For example, some embodiments may repurpose broken areas to give more performance, or switch based on event needs. Some embodiments may advantageously provide more adaptable and robust SSDs. Some features/aspects of various embodiments may be built-in to the SSD device itself. Advantageously, some embodiments may be applied to legacy SSD devices with aftermarket technology to repurpose the SSD (e.g., through an interface or external controller). For example, a failed or failing SSD may have its logical capacity resized to address failures. The failure may occur due to a number of reasons including, for example, high defect counts. Advantageously, some embodiments may physically repurpose defective blocks by switching the sensing mode to contain less bits per cell. The switching of the sensing mode will decrease the bit density per cell resulting in lower physical capacity, but may overcome the problem with the block such that the block becomes usable with the new sensing mode. The benefit of switching to a lower bit density is that the sensing can occur faster resulting in faster program and read times with more endurance (e.g., see Table 1).

Turning now toFIG. 7, an embodiment of a persistent storage media70may include multiple EBs. For example, a SSD may allocate a set of erase blocks to meet a product requirement document (PRD) based on one media type. Over time a fraction of these blocks may no longer be operable at their current mode, so they can no longer be used in the system for the desired performance level. Once the unusable blocks reach a threshold, PRD specifications may no longer be met and the entire set of blocks may be retired (e.g., marked as defective). A failing block may not be marked as defective immediately, and may instead be marked as provisional. Some embodiments may track set of defective blocks71, provisional blocks72, and usable blocks73(e.g., on a per-mode basis). The marking may help support parity protection for the band and may allow an amount of defects for runtime operations. In the event the protection range is exceeded, the current band may be aborted and a next, ready band may be allocated. In some embodiments, the sets of blocks may be based on a logical grouping of one EB per media die for the entire whole set of erase blocks. Advantageously, some embodiments may regroup and repurpose the EBs to form a new set if the set is large enough to meet the PRD.

Turning now toFIG. 8, an electronic processing system80may include a host81(e.g., CPU, OS, agent, etc.) communicatively coupled (e.g., wired or wirelessly) to a storage device82(e.g., a SSD). The storage device82may include a controller83(e.g., which may be implemented on a SoC) which includes a host IP block84(e.g., interface, protocol, NVMe, etc.), a transfer buffer85, and one or more channels86. The channels86may be coupled to persistent storage media87(e.g., Die0through Die N). A host access request (e.g., directed to Location1, Location32, etc.) may go through the transfer buffer85to the media87based on entries in an indirection table88. Some transfers X may go directly from the transfer buffer85to the media87through the channels86. The transfer buffer85may include a persistent and/or non-persistent storage. The level of indirection (e.g., the indirection table88) may include a multiple level cascading system where host address space is one level, another level may include internal to physical media mapping, and an additional level of media external scope to internal media extra block re-mapping. Each media level may also consist of the similar type to disjoint media technologies to mask the external latency. The host protocol may include any suitable technology including current or future protocols (e.g., NVMe, small computer system interface (SCSI), serial attached SCSI (SAS), serial ATA (SATA), parallel ATA (PATA), etc.).

In accordance with some embodiments, the controller83and/or the host81may further include logic89aand89bto manage the storage device82. For example, the logic89amay be configured to receive a request (e.g., from the host81) to modify a configuration of the media87, and to repurpose a region of the media87from a first number of bits per cell to a second number of bits per cell in response to the request. In some embodiments, the logic89amay be further configured to change a configuration of the region of the media87from a higher number of bits per cell to a lower number of bits per cell (e.g., from QLC to TLC). Additionally, or alternatively, the logic89amay be configured to identify a defective region of the media87, and switch a sense mode for the defective region to contain less bits per cell. For example, the logic89amay be configured to determine if the defective region is non-defective with the switched sense mode, and repurpose the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode. In some embodiments, the logic89amay be further configured to evaluate blocks of the media87to identify blocks near cell failure, pool one or more sets of blocks identified to be near cell failure based on the number of bits per cell, and repurpose the region of media87after a set of blocks has pooled a threshold number of blocks. For example, the logic89amay also be configured to provide estimated performance capability information based on the evaluation to the host81, and repurpose the region of persistent storage media based on information received from the host81in response to the provided estimated performance capability information.

In the event that a set of blocks can no longer be created at the PRD operating mode, the logic89amay notify the host81that the device82is approaching failure and will re-enter read only mode (e.g., via a Self-Monitoring, Analysis, and Reporting Technology (SMART) feature command. In the read-only mode, the device82may notify the host81about the amount of data required for moving the data to another drive to maintain operation. After the data is moved and verified, the host81may notify the device82, and the device82may then repurpose a defective region of one or more defective blocks, logically resize the user capacity, and report the expected performance to the host81. In some embodiments, the logic89aand/or89bmay be further configured provide a training and learning mode to re-evaluate all blocks, and repurpose blocks as needed/requested (e.g., see the method90(FIG. 9)). In the internal mode, several operations may be performed. At the start, all of the defective blocks may be evaluated, where each may be tested for a stable programing mode. Such testing may not need to occur solely at this stage, but at the learning phase the operation may need to be completed if not previously done. The expectation is as defects are promoted each of these blocks in the pool will be evaluated in cycles when a die is not used. Over time, as the critical event approaches, most or all blocks may be marked for a highest level stable programing mode.

Turning now toFIG. 9, an embodiment of a method90of managing storage may include detecting a critical failure at block91, notifying the host at block92, and marking the system as read-only and waiting for the host data relocation at block93. After the host data relocation, the method90may include beginning a training and learning mode at block94, where all blocks can be re-evaluated. An unknown capability defect pool may be emptied at block95. Next, all user data/content will be marked for relocation at block96, and the bands may be evaluated during the relocation process at block97.

In the relocation process, each of the emptied blocks may walk through the possible operating modes to find the next stable operating mode. For example, if the block is near cell failure at the current mode then the block may be marked as the mode below with less bits. These blocks may then be placed into allocation pools for re-logical enablement, based on the number of bits of the programming mode for each block. The logical re-enablement may advantageously introduce system spare that may otherwise have been considered lost.

After all of the blocks are evaluated at block98, the method90may then include evaluating storage space performance statistics at block100(e.g., computing the capabilities of performance). For example, the evaluation may be done based on the next lower density mode including a mixed mode at which each band has separate capabilities. The projection calculations may attempt cases based on the initial configuration. In the event the capabilities cannot be met, the method90may attempt to do a search for possibilities. The method90may then include notifying the host of a capabilities table at block101(e.g., including the determined capabilities and the search possibilities). If the host accepts the capabilities at block102, the storage system may be ready at block103. Otherwise, the host may request different capabilities at block104and the system may be marked as read only and may then wait for host data relocation at block105. The method90may then include notifying the mode change and relocate user data at block106, after which the storage system may be ready at block103.

Turning now toFIG. 10, an illustrative graph of logical capacity size versus performance bandwidth shows how a SSD in accordance with some embodiments may repurpose memory blocks based on a desired configuration, and/or to reclaim defective blocks. The expectation is that as the SSD repurposes the sets of blocks, performance potential will increase as the media operation mode is reduced in density. Repurposing the storage memory to the lower density mode may advantageously extend the timeline to complete failure and the performance may also increase as the drive decreases to the minimum meta operation mode. After the minimum mode is reached, the expectation is that performance and capacity may decrease until minimum operation failure. As the SSD approaches the minimum operation failure point, some embodiments may utilize a SMART command to notify the host of read only mode, wait for all data to be relocated, and then a light emitting diode (LED) may illuminate to indicate the failure sequence for technician replacement.

Turning now toFIG. 11, an embodiment of a computing system110may include one or more processors112-1through112-N (generally referred to herein as “processors112” or “processor112”). The processors112may communicate via an interconnection or bus115. Each processor112may include various components some of which are only discussed with reference to processor112-1for clarity. Accordingly, each of the remaining processors112-2through112-N may include the same or similar components discussed with reference to the processor112-1.

In some embodiments, the processor112-1may include one or more processor cores114-1through114-M (referred to herein as “cores114,” or more generally as “core114”), a cache118(which may be a shared cache or a private cache in various embodiments), and/or a router119. The processor cores114may be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and/or private caches (such as cache118), buses or interconnections (such as a bus or interconnection112), logic160, memory controllers, or other components.

In some embodiments, the router119may be used to communicate between various components of the processor112-1and/or system110. Moreover, the processor112-1may include more than one router119. Furthermore, the multitude of routers119may be in communication to enable data routing between various components inside or outside of the processor112-1.

The cache118may store data (e.g., including instructions) that are utilized by one or more components of the processor112-1, such as the cores114. For example, the cache118may locally cache data stored in a memory124for faster access by the components of the processor112. As shown inFIG. 11, the memory124may be in communication with the processors112via the interconnection115. In some embodiments, the cache118(that may be shared) may have various levels, for example, the cache118may be a mid-level cache and/or a last-level cache (LLC). Also, each of the cores114may include a level 1 (L1) cache (116-1) (generally referred to herein as “L1 cache116”). Various components of the processor112-1may communicate with the cache118directly, through a bus (e.g., the bus112), and/or a memory controller or hub.

As shown inFIG. 11, memory124may be coupled to other components of system110through a memory controller120. Memory124includes volatile memory and may be interchangeably referred to as main memory. Even though the memory controller120is shown to be coupled between the interconnection115and the memory124, the memory controller120may be located elsewhere in system110. For example, memory controller120or portions of it may be provided within one of the processors112in some embodiments.

The system110may communicate with other devices/systems/networks via a network interface128(e.g., which is in communication with a computer network and/or the cloud129via a wired or wireless interface). For example, the network interface128may include an antenna (not shown) to wirelessly (e.g., via an Institute of Electrical and Electronics Engineers (IEEE) 802.11 interface (including IEEE 802.11a/b/g/n/ac, etc.), cellular interface, 3G, 4G, LTE, BLUETOOTH, etc.) communicate with the network/cloud129.

System110may also include Non-Volatile (NV) storage device such as a SSD130coupled to the interconnect115via SSD controller logic125. Hence, logic125may control access by various components of system110to the SSD130. In some embodiments, the SSD130may include similar technology as discussed in connection with the SSD30(FIG. 3). Furthermore, even though logic125is shown to be directly coupled to the interconnection115inFIG. 11, logic125can alternatively communicate via a storage bus/interconnect (such as the SATA (Serial Advanced Technology Attachment) bus, Peripheral Component Interconnect (PCI) (or PCI EXPRESS (PCIe) interface), NVM EXPRESS (NVMe), etc.) with one or more other components of system110(for example where the storage bus is coupled to interconnect115via some other logic like a bus bridge, chipset, etc. Additionally, logic125may be incorporated into memory controller logic (such as those discussed with reference toFIG. 3) or provided on a same integrated circuit (IC) device in various embodiments (e.g., on the same IC device as the SSD130or in the same enclosure as the SSD130).

Furthermore, logic125and/or SSD130may be coupled to one or more sensors (not shown) to receive information (e.g., in the form of one or more bits or signals) to indicate the status of or values detected by the one or more sensors. As discussed below, the logic160may be configured to identify a defective region of the SSD130, and switch a sense mode from a first sense mode to a second different sense mode for the defective region to contain less bits per cell. These sensor(s) associated with the first sense mode or the second different sense mode may be provided proximate to components of system110(or other computing systems discussed herein such as those discussed with reference to other figures includingFIGS. 1-10, for example), including the cores114, interconnections115or112, components outside of the processor112, SSD130, SSD bus, SATA bus, logic125, logic160, etc., to sense variations in various factors affecting power/thermal behavior of the system/platform, such as temperature, operating frequency, operating voltage, power consumption, and/or inter-core communication activity, etc. As shown inFIG. 11, features or aspects of the logic125, and/or the logic160may be distributed throughout the system110, and/or co-located/integrated with various components of the system110(including the memory controller120, network interface128, cloud129, etc.).

As illustrated inFIG. 11, the system110may include logic160, some of which may be in the same enclosure as the SSD130and/or fully integrated on a printed circuit board (PCB) of the SSD130. Logic160advantageously provides technology to dynamically repurpose memory blocks of the SSD130. For example, the logic160may implement one or more aspects of the method30(FIGS. 3A to 3C), and/or the method90(FIG. 9). For example, the logic160may include technology to receive a request (e.g., from the processors112, the SSD controller logic125, the network interface128, etc.) to modify a configuration of the SSD130, and to repurpose a region of the SSD130from a first number of bits per cell to a second number of bits per cell in response to the request. In some embodiments, the logic160may be further configured to change a configuration of the region of the SSD130from a higher number of bits per cell to a lower number of bits per cell (e.g., from TLC to MLC or SLC). Additionally, or alternatively, the logic160may be configured to identify a defective region of the SSD130, and switch a sense mode for the defective region to contain less bits per cell. For example, the logic160may be configured to determine if the defective region is non-defective with the switched sense mode, and repurpose the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode. In some embodiments, the logic160may be further configured to evaluate blocks of the SSD130to identify blocks near cell failure, pool one or more sets of blocks identified to be near cell failure based on the number of bits per cell, and repurpose the region of SSD130after a set of blocks has pooled a threshold number of blocks. For example, the logic160may also be configured to provide estimated performance capability information based on the evaluation to a host (e.g., the processors112, the SSD controller logic125, an application, a network agent, etc.), and repurpose the region of persistent storage media based on information received from the host in response to the provided estimated performance capability information. In other embodiments, the SSD130may be replaced with any suitable persistent storage technology/media. In some embodiments, the logic160may be coupled to one or more substrates (e.g., silicon, sapphire, gallium arsenide, PCB, etc.), and may include transistor channel regions that are positioned within the one or more substrates.

ADDITIONAL NOTES AND EXAMPLES

Example 1 may include a storage system, comprising persistent storage media including multiple bits per cell, a controller communicatively coupled to the persistent storage media, and logic communicatively coupled to the controller and the persistent storage media to receive a request to modify a configuration of the persistent storage media, and repurpose a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request.

Example 2 may include the system of Example 1, wherein the logic is further to change a configuration of the region of the persistent storage media from a higher number of bits per cell to a lower number of bits per cell.

Example 3 may include the system of Example 1, wherein the logic is further to identify a defective region of the persistent storage media, and switch a sense mode for the defective region to contain less bits per cell.

Example 4 may include the system of Example 3, wherein the logic is further to determine if the defective region is non-defective with the switched sense mode, and repurpose the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode.

Example 5 may include the system of Example 1, wherein the logic is further to evaluate blocks of the persistent storage media to identify blocks near cell failure, pool one or more sets of blocks identified to be near cell failure based on the number of bits per cell, and repurpose the region of persistent storage media after a set of blocks has pooled a threshold number of blocks.

Example 6 may include the system of Example 5, wherein the logic is further to provide estimated performance capability information based on the evaluation to a host, and repurpose the region of persistent storage media based on information received from the host in response to the provided estimated performance capability information.

Example 7 may include the system of any of Examples 1 to 6, wherein the persistent storage media comprises a solid state drive.

Example 8 may include a semiconductor apparatus, comprising one or more substrates, and logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to receive a request to modify a configuration of a persistent storage media, and repurpose a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request.

Example 9 may include the apparatus of Example 8, wherein the logic is further to change a configuration of the region of the persistent storage media from a higher number of bits per cell to a lower number of bits per cell.

Example 10 may include the apparatus of Example 8, wherein the logic is further to identify a defective region of the persistent storage media, and switch a sense mode for the defective region to contain less bits per cell.

Example 11 may include the apparatus of Example 10, wherein the logic is further to determine if the defective region is non-defective with the switched sense mode, and repurpose the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode.

Example 12 may include the apparatus of Example 8, wherein the logic is further to evaluate blocks of the persistent storage media to identify blocks near cell failure, pool one or more sets of blocks identified to be near cell failure based on the number of bits per cell, and repurpose the region of persistent storage media after a set of blocks has pooled a threshold number of blocks.

Example 13 may include the apparatus of Example 12, wherein the logic is further to provide estimated performance capability information based on the evaluation to a host, and repurpose the region of persistent storage media based on information received from the host in response to the provided estimated performance capability information.

Example 14 may include the apparatus of any of Examples 8 to 13, wherein the persistent storage media comprises a solid state drive.

Example 15 may include the apparatus of any of Examples 8 to 14, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

Example 16 may include a method of managing storage, comprising receiving a request to modify a configuration of a persistent storage media, and repurposing a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request.

Example 17 may include the method of Example 16, further comprising changing a configuration of the region of the persistent storage media from a higher number of bits per cell to a lower number of bits per cell.

Example 18 may include the method of Example 16, further comprising identifying a defective region of the persistent storage media, and switching a sense mode for the defective region to contain less bits per cell.

Example 19 may include the method of Example 18, further comprising determining if the defective region is non-defective with the switched sense mode, and repurposing the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode.

Example 20 may include the method of Example 16, further comprising evaluating blocks of the persistent storage media to identify blocks near cell failure, pooling one or more sets of blocks identified to be near cell failure based on the number of bits per cell, and repurposing the region of persistent storage media after a set of blocks has pooled a threshold number of blocks.

Example 21 may include the method of Example 20, further comprising providing estimated performance capability information based on the evaluation to a host, and repurposing the region of persistent storage media based on information received from the host in response to the provided estimated performance capability information.

Example 22 may include the method of any of Examples 16 to 21, wherein the persistent storage media comprises a solid state drive.

Example 23 may include at least one computer readable storage medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to receive a request to modify a configuration of a persistent storage media, and repurpose a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request.

Example 24 may include the at least one computer readable storage medium of Example 23, comprising a further set of instructions, which when executed by the computing device, cause the computing device to change a configuration of the region of the persistent storage media from a higher number of bits per cell to a lower number of bits per cell.

Example 25 may include the at least one computer readable storage medium of Example 23, comprising a further set of instructions, which when executed by the computing device, cause the computing device to identify a defective region of the persistent storage media, and switch a sense mode for the defective region to contain less bits per cell.

Example 26 may include the at least one computer readable storage medium of Example 25, comprising a further set of instructions, which when executed by the computing device, cause the computing device to determine if the defective region is non-defective with the switched sense mode, and repurpose the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode.

Example 27 may include the at least one computer readable storage medium of Example 23, comprising a further set of instructions, which when executed by the computing device, cause the computing device to evaluate blocks of the persistent storage media to identify blocks near cell failure, pool one or more sets of blocks identified to be near cell failure based on the number of bits per cell, and repurpose the region of persistent storage media after a set of blocks has pooled a threshold number of blocks.

Example 28 may include the at least one computer readable storage medium of Example 27, comprising a further set of instructions, which when executed by the computing device, cause the computing device to provide estimated performance capability information based on the evaluation to a host, and repurpose the region of persistent storage media based on information received from the host in response to the provided estimated performance capability information.

Example 29 may include the at least one computer readable storage medium of any of Examples 23 to 28, wherein the persistent storage media comprises a solid state drive.

Example 30 may include a storage manager apparatus, comprising means for receiving a request to modify a configuration of a persistent storage media, and means for repurposing a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request.

Example 31 may include the apparatus of Example 30, further comprising means for changing a configuration of the region of the persistent storage media from a higher number of bits per cell to a lower number of bits per cell.

Example 32 may include the apparatus of Example 30, further comprising means for identifying a defective region of the persistent storage media, and means for switching a sense mode for the defective region to contain less bits per cell.

Example 33 may include the apparatus of Example 32, further comprising means for determining if the defective region is non-defective with the switched sense mode, and means for repurposing the defective region as an available region if the defective region is determined to be non-defective with the switched sense mode.

Example 34 may include the apparatus of Example 30, further comprising means for evaluating blocks of the persistent storage media to identify blocks near cell failure, means for pooling one or more sets of blocks identified to be near cell failure based on the number of bits per cell, and means for repurposing the region of persistent storage media after a set of blocks has pooled a threshold number of blocks.

Example 35 may include the apparatus of Example 34, further comprising means for providing estimated performance capability information based on the evaluation to a host, and means for repurposing the region of persistent storage media based on information received from the host in response to the provided estimated performance capability information.

Example 36 may include the apparatus of any of Examples 30 to 35, wherein the persistent storage media comprises a solid state drive.

As used in this application and in the claims, a list of items joined by the term “one or more of” may mean any combination of the listed terms. For example, the phrase “one or more of A, B, and C” and the phrase “one or more of A, B, or C” both may mean A; B; C; A and B; A and C; B and C; or A, B and C.