Self-aligned non-mandrel cut formation for tone inversion

Methods of forming self-aligned non-mandrel cuts during the fabrication of an interconnect structure. A first dielectric hardmask layer is formed on a metal hardmask layer. A plurality of mandrels are formed on the first dielectric hardmask layer, and a plurality of spacers are formed on the first dielectric hardmask layer. The spacers are located adjacent to the mandrels. A first sacrificial layer is formed that fills spaces between the spacers, and a second dielectric hardmask layer is formed on the first sacrificial layer, the spacers, and the mandrels. A plurality of sections of a second sacrificial layer are formed on the second dielectric hardmask layer and cover the second dielectric hardmask layer over a plurality of areas that are used to form the non-mandrel cuts.

BACKGROUND

The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to methods for forming self-aligned non-mandrel cuts during the fabrication of an interconnect structure.

A back-end-of-line (BEOL) interconnect structure may be used to connect device structures fabricated on a substrate during front-end-of-line (FEOL) processing with each other and with the environment external to the chip. Self-aligned patterning processes used to form a BEOL interconnect structure involve mandrels as sacrificial features that establish a feature pitch. Sidewall spacers, which have a smaller thickness than permitted by the current ground rules for optical lithography, are formed adjacent to the vertical sidewalls of the mandrels. After selective removal of the mandrels, the sidewall spacers are used as an etch mask to etch an underlying hardmask, for example, with a directional reactive ion etch (RIE) process. Unmasked features in the pattern are transferred from the hardmask to an interlayer dielectric layer to define trenches in which the wires of the BEOL interconnect are formed.

Cuts may be formed in mandrels with a cut mask and etching in order to section the mandrels and define gaps that may be subsequently used to produce wires that are spaced apart at their tips with a tip-to-tip spacing. A pattern reflecting the cut mandrels may be transferred to the hardmask and subsequently from the hardmask to the patterned interlayer dielectric layer. Non-mandrel cuts may also be formed in the hardmask itself and define gaps that may be filled by dielectric material when the sidewall spacers are formed. The filled gaps may be subsequently used to produce wires that are spaced apart at their tips with a tip-to-tip spacing. A pattern reflecting the non-mandrel cuts may also be transferred to the hardmask and subsequently from the hardmask to the patterned interlayer dielectric layer.

Improved methods of forming self-aligned non-mandrel cuts during the fabrication of an interconnect structure are needed.

SUMMARY

In an embodiment of the invention, a method includes forming a first dielectric hardmask layer on a metal hardmask layer, forming a plurality of mandrels on the first dielectric hardmask layer, and forming a plurality of spacers on the first dielectric hardmask layer that are located adjacent to the mandrels. A first sacrificial layer is formed that fills spaces between the spacers, and a second dielectric hardmask layer is formed on the first sacrificial layer, the spacers, and the mandrels. A plurality of sections of a second sacrificial layer are formed on the second dielectric hardmask layer and cover the second dielectric hardmask layer over a plurality of areas that are used to form a plurality of non-mandrel cuts.

DETAILED DESCRIPTION

With reference toFIG. 1and in accordance with embodiments of the invention, an interlayer dielectric layer10may be comprised of an electrically-insulating dielectric material, such as hydrogen-enriched silicon oxycarbide (SiCOH) produced from an octamethylcyclotetrasiloxane (OMCTS) precursor or another type of low-k dielectric material. The interlayer dielectric layer10may be located on a substrate that includes device structures fabricated by front-end-of-line (FEOL) processing to form an integrated circuit.

A hardmask layer12is located on the top surface of the interlayer dielectric layer10. The hardmask layer12may be comprised of a metal, such as titanium nitride (TiN), deposited by physical vapor deposition (PVD). The hardmask layer12is removable from the interlayer dielectric layer10selective to the material of the interlayer dielectric layer10. As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that the material removal rate (i.e., etch rate) for the targeted material is higher than the material removal rate (i.e., etch rate) for at least another material exposed to the material removal process.

A dielectric hardmask layer14is formed with a given thickness, t0, on the hardmask layer12. The dielectric hardmask layer14may be comprised of a dielectric material, such as silicon nitride (Si3N4), deposited by chemical vapor deposition (CVD). In an alternative embodiment, the dielectric hardmask layer14may be comprised of a different dielectric material, such as silicon dioxide (SiO2). The material constituting the dielectric hardmask layer14is chosen to be removable from the hardmask layer12selective to the material of the hardmask layer12.

Mandrels16,18are formed on a top surface of the dielectric hardmask layer14. The mandrels16,18may be concurrently formed by depositing a blanket layer of a sacrificial material on the entire top surface of the dielectric hardmask layer14and patterning the blanket layer by lithography and etching using a lithography stack. For example, a sidewall image transfer (SIT) process or a self-aligned double patterning (SADP) process may be used to pattern the mandrels16,18. At least one of the dimensions of mandrel18, e.g., the width, may be greater than the corresponding dimension of mandrels16.

Sidewall spacers20are formed at locations on the top surface of the dielectric hardmask layer14adjacent to the vertical sidewalls of the mandrels16and at locations on the top surface of the dielectric hardmask layer14adjacent to the vertical sidewalls of the mandrel18. The sidewall spacers20and the mandrels16,18are arranged lengthwise in parallel rows on the top surface of the dielectric hardmask layer14. The sidewall spacers20may be formed by depositing a conformal layer comprised of a dielectric material with atomic layer deposition (ALD) and shaping the conformal layer with an anisotropic etching process, such as reactive ion etching (RIE). The anisotropic etching process preferentially removes the dielectric material from horizontal surfaces, such as the top surfaces of the dielectric hardmask layer14and the mandrels16,18in deference to the dielectric material adjacent to the sidewalls of the mandrels16,18.

The material constituting the sidewall spacers20may be chosen so as to be removed by a given etch chemistry selective to the material of the mandrels16,18. For example, the dielectric material constituting the sidewall spacers20may be silicon dioxide (SiO2), and the material constituting the mandrels16,18may be silicon, which may be removed selective to silicon dioxide so that the mandrels16,18can be pulled without removing the spacers20. In alternative embodiments, the sidewall spacers20may be comprised of a different material, such as a metal oxide, with a similar etch selectivity relative to the mandrels16,18.

A sacrificial layer22may be applied by spin-coating to fill the gaps between the sidewall spacers20on the adjacent mandrels16,18. The sacrificial layer22may be comprised of, for example, an organic planarization layer (OPL) material or another spin-on material such as a spin-on metal (e.g., titanium dioxide (TiO2) or hafnium dioxide (HfO2)) or a spin-on glass (SOG). The sacrificial layer22is etched back to be coplanar with the mandrels16,18, which exposes the respective top surfaces of the mandrels16,18. After planarization, the mandrels16,18and the sacrificial layer22have the same thickness, t1.

A dielectric hardmask layer24is applied on a top surface of the mandrels16,18and the sacrificial layer22. The dielectric hardmask layer24may be comprised of a dielectric material, such as silicon nitride (Si3N4), deposited by CVD. In an alternative embodiment, the dielectric hardmask layer24may be comprised of a different dielectric material, such as silicon dioxide (SiO2). The dielectric hardmask layer14and the dielectric hardmask layer24may be comprised of the same dielectric material. The identity of the materials for the dielectric hardmask layers14,24provides, among other shared physical and chemical properties, the same etch selectivity to other materials. In an embodiment, the thickness, t2, of the dielectric hardmask layer24is less than the thickness of the dielectric hardmask layer14.

A mandrel layer26is deposited on the top surface of the dielectric hardmask layer24. The material for the mandrel layer26is chosen to be removed selective to the material of the dielectric hardmask layer24. The mandrel layer26may be comprised of silicon (Si), such as amorphous silicon, or carbon (C), such as amorphous carbon, deposited at a low temperature by CVD. In an embodiment, the mandrel layer26and the mandrels16,18may be comprised of the same material. The identity of the materials for the mandrel layer26and the mandrels16,18provides, among other shared physical and chemical properties, the same etch selectivity to other materials. In an embodiment, the thickness, t3, of the mandrel layer26may be less than the thickness (i.e., vertical height) of the mandrels16,18.

With reference toFIG. 2in which like reference numerals refer to like features inFIG. 1and at a subsequent fabrication stage of the processing method, the mandrel layer26is patterned to define sections that are horizontally separated by open spaces. To pattern the mandrel layer26, a lithography stack28is applied to the top surface of the mandrel layer26and patterned to define openings30that are aligned with different areas of the mandrel layer26. The lithography stack28may include, for example, an organic planarization layer, an anti-reflective coating, and a layer of photoresist. An etching process is used to transfer the openings30from the lithography stack28into the mandrel layer26in order to pattern the mandrel layer26.

With reference toFIG. 3in which like reference numerals refer to like features inFIG. 2and at a subsequent fabrication stage of the processing method, the lithography stack28is stripped from the mandrel layer26. A sacrificial layer32, which operates as a tone inversion layer, may be applied by spin-coating as a gap-fill material with sections that fill the openings30in the mandrel layer26. The top surface of the sacrificial layer32is etched back to be coplanar with the top surface of the mandrel layer26.

The sacrificial layer32may have a thickness that is less than the thickness of the sacrificial layer22. The thickness of the mandrels16,18establishes the thickness of the sacrificial layer22, and the thickness of the mandrel layer26establishes the thickness of the sacrificial layer32. Because the thickness of the mandrels16,18is greater than the thickness of the mandrel layer26, the sacrificial layer22is likewise thicker than the sacrificial layer32.

The sacrificial layer32may be comprised of, for example, an organic planarization layer (OPL) material. Alternatively, the sacrificial layer32may be comprised of another type of spin-on material, such as a spin-on metal (e.g., titanium dioxide (TiO2) or hafnium dioxide (HfO2)) or a spin-on glass (SOG). The sacrificial layer32may be comprised of the same material as the sacrificial layer22. The identity of the materials for the sacrificial layers22,32provides, among other shared physical and chemical properties, identical etch selectivities to other materials.

The mandrel layer26and the sacrificial layer32may be comprised of various combinations of materials with etch properties and gap-fill properties that provide the requisite functionality for tone inversion. The material of the mandrel layer26is removable selective to the material of the sacrificial layer32so that an inverted pattern (i.e., a complementary pattern) can be transferred from the patterned mandrel layer26to the sacrificial layer32.

In an embodiment, the mandrel layer26may be comprised of amorphous silicon and the sacrificial layer32may be comprised of OPL material or spin-on carbon (SOC). In an embodiment, the mandrel layer26may be comprised of amorphous silicon and the sacrificial layer32may be comprised of a spin-on metal (e.g., titanium dioxide (TiO2) or hafnium dioxide (HfO2)), a spin-on glass (SOG), or another type of spin-on material with the requisite etch selectivity to amorphous silicon and acceptable gap-fill properties. In an embodiment, the mandrel layer26may be comprised of amorphous carbon and the sacrificial layer32may be comprised of titanium dioxide (TiO2), spin-on glass (SOG), or another type of spin-on material with the requisite etch selectivity to amorphous carbon and acceptable gap-fill properties.

With reference toFIG. 4in which like reference numerals refer to like features inFIG. 3and at a subsequent fabrication stage of the processing method, the patterned mandrel layer26is removed selective to the material of the dielectric hardmask layer24with an etching process having a suitable etch chemistry. The top surface of the dielectric hardmask layer24is revealed over areas from which the mandrel layer26is pulled to complete the tone inversion. Discrete sections of the sacrificial layer32, which were arranged in the spaces between the sections of the mandrel layer26, remain on the top surface of the dielectric hardmask layer24.

The dielectric hardmask layer24is then opened over areas that are not masked by the portions of sacrificial layer32. To that end, the unmasked areas of the dielectric hardmask layer24are removed selective to the materials of the mandrels16,18, the spacers20, and sacrificial layer22with an etching process having a suitable etch chemistry. Portions of the sacrificial layer22are covered by the sacrificial layer32and dielectric hardmask layer24. Other portions of the sacrificial layer22are exposed through the openings formed in the sacrificial layer32and dielectric hardmask layer24.

With reference toFIG. 5in which like reference numerals refer to like features inFIG. 4and at a subsequent fabrication stage of the processing method, portions of the sacrificial layer22in the spaces between spacers20and in the space between mandrels16and mandrel18are removed with, for example, an etching process. These portions of the sacrificial layer22are not masked by the dielectric hardmask layer24. The etching process is chosen to remove the sacrificial layer22selective to dielectric hardmask layer24. The discrete portions of the sacrificial layer32remaining on the top surface of the dielectric hardmask layer24are also removed by the etching process. The larger thickness of the sacrificial layer22, in comparison with the thickness of the sacrificial layer32, ensures that the sacrificial layer32is completely removed from the dielectric hardmask layer24when opening the sacrificial layer22over areas that are not masked by the dielectric hardmask layer24.

Over areas masked by the dielectric hardmask layer24, sections of the sacrificial layer22are preserved. Some of these sections of the sacrificial layer22are located in the spaces between adjacent sidewall spacers20, and eventually provide non-mandrel cuts defining tip-to-tip or end-to-end spaces between adjacent conductive features formed in the interlayer dielectric layer10.

With reference toFIG. 6in which like reference numerals refer to like features inFIG. 5and at a subsequent fabrication stage of the processing method, the dielectric hardmask layer14is etched with an etching process that removes the dielectric hardmask layer14selective to the hardmask layer12, as well as the spacers20, mandrels16,18, and the sacrificial layer22. The remaining sections of the dielectric hardmask layer24are removed when the dielectric hardmask layer14is opened. The larger thickness of the dielectric hardmask layer14, in comparison with the thickness of the dielectric hardmask layer24, ensures that the remaining sections of the dielectric hardmask layer24are completely removed when opening the dielectric hardmask layer14over areas of the dielectric hardmask layer14that are not masked. The preserved sections of the sacrificial layer22, which are located between adjacent sidewall spacers20, are initially covered by corresponding sections of the dielectric hardmask layer24and are intact after the dielectric hardmask layer14is opened. A preserved section of the sacrificial layer22, which is located between the mandrels16and the mandrel18, is initially covered by a corresponding section of the dielectric hardmask layer24and is also intact after the dielectric hardmask layer14is opened.

With reference toFIG. 7in which like reference numerals refer to like features inFIG. 6and at a subsequent fabrication stage of the processing method, a sacrificial layer36comprised of, for example, an organic planarization layer (OPL) material may be applied by spin-coating and etched back, along with sacrificial layer22, to expose the top surfaces of the mandrels16,18. The mandrels16,18are subsequently removed selective to the sidewall spacers20with an etching process having a suitable etch chemistry. The top surface of the dielectric hardmask layer14is revealed over areas on its top surface that are exposed when the mandrels16,18are pulled. Sections of the sacrificial layer36fill the openings in the dielectric hardmask layer14that are opened in the dielectric hardmask layer14when the dielectric hardmask layer24is removed.

With reference toFIG. 8in which like reference numerals refer to like features inFIG. 7and at a subsequent fabrication stage, the dielectric hardmask layer14is subsequently patterned by an etching process with the sidewall spacers20and the sections of the sacrificial layers22,36operating as an etch mask. The etching process that opens the dielectric hardmask layer14may employ an etch chemistry that removes the material of the dielectric hardmask layer14that is not covered by the sidewall spacers20and sections of the sacrificial layers22,36. At the conclusion of the etching process, intact sections of the dielectric hardmask layer14are located vertically between the sidewall spacers20and the hardmask layer12, as well as laterally between some of the sidewall spacers20and in the open area.

With reference toFIG. 9in which like reference numerals refer to like features inFIG. 8and at a subsequent fabrication stage, the sections of the sacrificial layers22,36are stripped by a cleaning process after the mandrels16,18are pulled. The hardmask layer12is then patterned by an etching process with the sidewall spacers20and the sections of the dielectric hardmask layer14operating as an etch mask. The etching process may employ an etch chemistry that removes the material of the hardmask layer12selective to the materials of the sidewall spacers20and the dielectric hardmask layer14, as well as selective to the material of the interlayer dielectric layer10.

The sidewall spacers20mask the hardmask layer12and the intervening sections of the dielectric hardmask layer14over areas on the top surface of the hardmask layer having the same shape and area. Sections of the hardmask layer12are preserved and retained during its etching in elongated strips over these areas that are covered by the sidewall spacers20and the intervening sections of the dielectric hardmask layer14. Between some of the sidewall spacers20and over a given area on the top surface of the hardmask layer12, sections of the dielectric hardmask layer14mask the hardmask layer12. Sections of the hardmask layer12are likewise preserved and retained during its etching over the areas covered by these sections of the dielectric hardmask layer14.

With reference toFIGS. 10 and 11in which like reference numerals refer to like features inFIG. 9and at a subsequent fabrication stage, the sidewall spacers20and sections of the dielectric hardmask layer14beneath the sidewall spacers20may be removed by one or more etching processes. The interlayer dielectric layer10is etched using the hardmask layer12as a patterned etch mask to remove the interlayer dielectric layer10in unmasked areas and thereby form trenches in the interlayer dielectric layer10. Those masked areas in which the interlayer dielectric layer10is not etched, and therefore retained, are determined by the areas of the hardmask layer12that are covered by the dielectric hardmask layer14and the sidewall spacers20when the hardmask layer12is patterned. After the interlayer dielectric layer10is etched, the hardmask layer12may be selectively removed by an etching or cleaning process.

The trenches in the interlayer dielectric layer10are filled with a conductor to form wires38of different dimensions. A liner (not shown) comprised of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a layered combination of these materials (e.g., a bilayer of Ti/TiN) may be applied to the trenches before filling with the metal. The wires38may be comprised of a low-resistivity conductor formed using a deposition process, such as a metal like copper (Cu) formed by electroplating or electroless deposition.

The shapes and geometries of the wires38reproduce the shapes and geometries of the patterned features in the hardmask layer12. Adjacent pairs of wires38are separated from each other in one lateral direction by strips44of the electrical insulator of the interlayer dielectric layer10. At the locations of non-mandrel cuts, a section46of the interlayer dielectric layer10is located between some of the pairs of wires38and, in particular, between the end40of one of the wires38and an end42of another of the wires38in end-to-end linear alignment with the other wire38. The dielectric material of each section46bridges and joins the dielectric material of the adjacent strips44flanking these linearly-aligned wires38such that the wires38are electrically isolated from each other. When the interlayer dielectric layer10is etched, these strips44and sections46are masked by areas of the hardmask layer12.

With reference toFIG. 12in which like reference numerals refer to like features inFIG. 1and in accordance with embodiments of the invention, the sacrificial layer22may be applied with a thickness that is greater than the thickness (i.e., height) of the mandrels16,18. For example, the sacrificial layer22may be applied with spin-coating to fill the gaps between the sidewall spacers20and with the enhanced thickness, but the etch back may not be performed. The enhanced thickness of the sacrificial layer22may be effective to lessen or eliminate topography in the sacrificial layer22originating from the topography of the underlying mandrels16,18and spacers20, which in turn may reduce critical dimension variations of the mandrel layer26and the sacrificial layer32.

References herein to terms such as “vertical”, “horizontal”, “lateral”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. Terms such as “horizontal” and “lateral” refer to a directions in a plane parallel to a top surface of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. Terms such as “vertical” and “normal” refer to a direction perpendicular to the “horizontal” and “lateral” direction. Terms such as “above” and “below” indicate positioning of elements or structures relative to each other and/or to the top surface of the semiconductor substrate as opposed to relative elevation.

A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.