Enhanced performance memory systems and methods

Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.

BACKGROUND

Various digital systems, such as general-purpose computational devices, digital signal processors, video devices, and the like, generally include a processor configured to interpret and process encoded instructions, an attached high-speed memory system. The encoded instructions control the various processing operations of the processor, and are generally stored in selected portions of the memory system, which usually also contains at least a portion of the data to be processed. A memory bus is sometimes present, which serves as a communications channel between the processor and the memory system, so that the encoded instructions and the data may be communicated between the processor and the memory system.

The performance of a digital system may be defined by its speed and efficiency in processing the data. The performance of the digital system therefore includes the speed of the processor in performing arithmetic operations, the adaptability of the digital system to changing user requirements, and other contributing factors. Among these factors is the operating speed of the memory, as well as the availability of the memory for access by the processor.

Another significant performance factor can be the bandwidth supported by the memory bus. The theoretical bandwidth of the bus may be simply estimated by forming the product of the clock rate and the data delivered per clock cycle. For example, if eight bytes are communicated per clock cycle, and the clock rate is 100 MHz, then the theoretical bandwidth of the bus is 0.80 Gigabytes/second. This estimate is based upon full utilization of the bus (e.g., the falling edge of the clock cycle always communicates eight bytes), with no memory latency effects present to decrease the theoretical bandwidth to a somewhat lower sustained bandwidth.

Due to increasing system speeds, bandwidth limitations have become a significant problem. In one known method, the bandwidth of the bus may be increased by increasing the physical width of the bus. As the physical dimensions of integrated circuit devices steadily decrease, however, competition for available “real estate”, or layout space on the device may be strictly limited. In another known method, the bandwidth of the memory bus may be increased by increasing the clock speed of the bus. It is generally understood, however, that limitations also presently exist with regard to increasing the speed of the bus. For example, impedance differences may cause undesired signal reflections within the bus, which adversely affect the overall performance of the system. Further, signal isolation problems may also arise as operational frequencies are further increased.

DETAILED DESCRIPTION

Various embodiments of the invention include digital memory devices and systems, such as memory systems and methods for operating memory systems in conjunction with high speed processing systems. Many specific details of various embodiments of the invention are set forth in the following description and inFIGS. 1 through 16to provide a thorough understanding of such embodiments. One of ordinary skill in the art, however, will understand that additional embodiments are possible, and that many embodiments may be practiced without several of the details disclosed in the following description.

FIG. 1is a diagrammatic block view of a memory system10, according to one or more embodiments. The memory system10includes a central processing unit (CPU)12that is coupled to a memory controller14by a local bus16. The CPU12may generally include any digital device configured to receive programmed instructions and data, and to process the data according to the programmed instructions. The memory controller14may include various digital circuits that are operable to manage information that is transferred to and from the CPU12along the local bus16. AlthoughFIG. 1shows the CPU12and the memory controller14as distinct functional blocks, it is understood that various alternative physical arrangements are possible. For example, the memory controller14may be physically positioned on a die that also includes the CPU12, so that memory latency effects are minimized. Alternatively, the CPU12and the memory controller14may be implemented on separate dice that are operably coupled and positioned on a common circuit assembly, such as a “motherboard”, or other similar circuit assemblies.

The memory controller14may also be implemented in still other arrangements. For example, the memory controller14may be incorporated as a chipset positioned on a motherboard, perhaps including one or more memory controller hubs, such as a “northbridge”, and one or more input/output (I/O) controller hubs, such as a “southbridge”, so that the memory controller14is incorporated at least in part, in the northbridge that is configured to handle information communicated between the CPU12and various memory devices (to be discussed subsequently), as well as communications functions between the CPU12and other devices, such as a graphics card.

The local bus16may include a plurality of parallel signal lines, which are operable to provide generally bidirectional point-to-point communications between the CPU12and the memory controller14, but may also include other alternative arrangements that provide a similar logical functionality. Accordingly, the local bus16may include a “front-side” bus that couples the CPU12to the northbridge portion of a chipset.

The memory system10may also include a memory bus18that includes a plurality of generally parallel signal lines that provide bidirectional signal communication between the memory controller14and a first memory unit20and a second memory unit22. Serial and other communication may also be used. Accordingly, the memory bus may be operably configured to communicate a variety of signals between the CPU12and the first memory unit20and the second memory unit22. For example, the memory bus18may include lines configured to communicate data signals corresponding to actual data that is to be written to, or read from the first memory unit20. Other lines within the memory bus18may be similarly configured to communicate still other signals, such address signals, which specify a location within one of the first memory unit20and the second memory unit22where data is to be written to, or read from. Command signals may also be communicated along selected lines in the memory bus18, which may provide specific instructions to at least one of the first memory unit20and the second memory unit22concerning the type of operation that is to be performed (e.g., a read operation, a write operation, a refresh operation, or other various and known operations). Selected lines in the memory bus18may also be suitably configured to communicate control and clock signals so that other signals passing between the memory controller14and the first memory unit20and the second memory unit22are properly controlled and synchronized. Although the memory bus18may include separate signal lines for each signal, it is nevertheless understood that other alternative arrangements that provide a similar logical functionality may also be used.

The first memory unit20and the second memory unit22may include discrete memory devices, such as a static memory, a dynamic random access memory (DRAM), an extended data out dynamic random access memory (EDO DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a synchronous link dynamic random access memory (SLDRAM), a video random access memory (VRAM), a rambus dynamic random access memory (RDRAM), a static random access memory (SRAM), a flash memory, as well as other known memory devices.

Additionally, the first memory unit20and the second memory unit22may also include memory modules having a plurality of discrete memory devices that are mounted on a common and generally removable circuit assembly. For example, the first memory unit20and the second memory unit22may include a dual in line memory module (DIMM) having a plurality of memory devices that are generally configured to operate in parallel.

When the first memory unit20and the second memory unit22include memory modules, still other physical arrangements are possible. For example, the first memory unit20and the second memory unit22may include other memory modules, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a double data rate two synchronous dynamic random access memory (DDR2 SDRAM), a double data rate three synchronous dynamic random access memory (DDR3 SDRAM), as well as other suitable memory modules.

Still referring toFIG. 1, the memory system10may include a divider unit24coupled to the memory bus18and the memory unit20and the memory unit22. The divider unit24is interposed between the memory bus18and the memory unit20and the memory unit22, and thus controls signal communication between the bus18and the memory unit20and the memory unit22. In addition, the divider unit24is configured to divide a signal level supplied to the first memory unit20and the second memory unit22so that approximately equivalent signal levels are transferred to the first memory unit20and the second memory unit22. In addition, the divider unit24provides isolation between the divided and approximately equivalent signal levels. Accordingly, the divider unit24may include various passive circuit elements, or a combination of active and passive elements. Since the divider unit24may be configured to divide and/or to combine signals, it is generally a bidirectional device. The divider unit24, according to various embodiments, will be discussed in greater detail below.

FIG. 2is a diagrammatic block view of a memory system30, according to one or more embodiments. Many of the various elements of the memory system30have been previously described in detail, and in the interest of brevity, such elements will not be described further. The memory system30may include at least a first secondary divider unit32and a second secondary divider unit34that are coupled to the divider unit24. Accordingly, a signal level received from the bus18is approximately first equally divided by the divider unit24, and each divided signal level may then be supplied to the first secondary divider unit32and a second secondary divider unit34, each of which further approximately equally divides the previously divided signal level. The divided (and approximately equivalent) signal levels generated by the first secondary divider unit32and a second secondary divider unit34may then be supplied to memory units36-42. The arrangement of divider units in discrete stages, as shown inFIG. 2, may provide enhanced bandwidth performance to the memory system30. AlthoughFIG. 2shows the divider unit24, and the first secondary divider unit32and a second secondary divider unit34as separate functional elements, it is nevertheless understood that the divider unit24, and the first secondary divider unit32and a second secondary divider unit34may be physically combined into a common assembly, which may in turn, be combined into other physical structures within the memory system30. Further, it is understood that it is within the scope of the various embodiments to combine still other divider units to couple still other additional memory units to the memory bus18. Although the various divider units shown inFIG. 2may embody a common functionality, it is understood that the various divider units in each stage may include internal components (to be discussed in greater detail below) having different component values, so that the various divider units may be configured to provide a suitable impedance match at each of the various stages.

FIG. 3is a diagrammatic block view of a memory system50, according to one or more embodiments. Again, many of the various elements of the memory system50, which are similar to or identical to the components in memory systems10and30ofFIGS. 1 and 2, respectively, have been previously described, and will not be described further. Here it can be seen that the memory system50may include an n-way divider unit52configured to receive a signal level on the memory bus18, and to divide the received signal level into n-approximately equivalent divided signal levels, which may then be communicated to memory units54a-54n. The n-way divider unit52will be described in greater detail below.

FIG. 4is a diagrammatic block view of a memory system60, according to one or more embodiments. Yet again, many of the various elements of the memory system60have been previously described, and will not be described further. The memory system60may include the n-way divider unit52, as previously described. Since one or more of the divided signal levels generated within the n-way divider unit52may be significantly attenuated by the n-way divider unit52, one or more signal boosting units62may be coupled to selected outputs from the n-way divider unit52and to selected inputs to the memory units54a-54n, so that a suitable signal level may be communicated to the selected memory units54a-54n. The one or more signal boosting units62may include, for example, one or more low-noise amplification stages that provide reasonable amplification and bandwidth. Accordingly, the amplification stages may include various semiconductor devices, such as field effect transistor devices (e.g., FETs, JFETs, MOSFETS) or even bipolar transistor devices. AlthoughFIG. 4shows the signal boosting units62separate from the n-way divider unit52, it is understood that the signal boosting units62may be physically incorporated into the n-way divider unit52.

With reference nowFIG. 5, a divider unit70may include a first impedance72that is serially coupled to a first port74, which may, in turn, be coupled to the memory bus18(as shown inFIGS. 1-4). The divider unit70may also include a second impedance76and a third impedance78that are coupled to the first impedance72. The second impedance76may be coupled to a second port80, while the third impedance78may be coupled to a third port82. The second port80and the third port82may, in turn, be coupled to memory units, such as, for example, the first memory unit20(as shown inFIG. 1) and the second memory unit22(as also shown inFIG. 1). In accordance with conventional terminology, it is therefore noted that the first impedance72, the second impedance76and the third impedance78are arranged in a wye-coupled configuration. Since it is desired that the divider unit70comprise a matched network, with all of the ports matched to an impedance Z0(e.g., a characteristic impedance of the memory bus18ofFIG. 1), each of the first impedance72, the second impedance76and the third impedance78includes a value that is approximately one-third of the impedance Z0.

FIG. 6is a schematic view of a divider unit90that also includes a first port74that may be coupled to the memory bus18(as shown inFIGS. 1-4), and a second port80and a third port82that may be coupled to memory units, such as the first memory unit20(as shown inFIG. 1) and the second memory unit22(as also shown inFIG. 1). The divider unit90therefore constitutes a delta-coupled arrangement that includes the first impedance72, the second impedance76and the third impedance78. Again, since it is desired that the divider unit90be a matched network, each of the first impedance72, the second impedance76and the third impedance78includes a value that is approximately equal to the impedance Z0.

With reference now specifically toFIG. 5andFIG. 6, it is understood that the first impedance72, the second impedance76and the third impedance78may be pure resistances, so that the divider unit70and the divider unit90may be substantially resistive networks. Although resistive networks advantageously provide wide bandwidth, and are relatively inexpensive to fabricate, signal attenuation values may be elevated (e.g., approximately about −6 dB) in comparison with subsequently discussed embodiments.

FIG. 7is a schematic view of a divider unit100that also includes a first port74that may be coupled to the memory bus18(as shown inFIGS. 1-4), and a second port80and a third port82that may be coupled to respective memory units, such as the first memory unit20(as shown inFIG. 1) and the second memory unit22(as also shown inFIG. 1).

The divider unit100may include a first transmission line transformer102and a second transmission line transformer104that are arranged in a mutually parallel arrangement. The first transmission line transformer102and the second transmission line transformer104are generally configured to be tuned to one-quarter of an operational wavelength λ and may be formed using an appropriately configured stripline, or micro-stripline transmission line, or by using other appropriately configured transmission lines.

The divider unit100may also include an impedance106, which may be coupled to the second port80and a third port82. In the various embodiments, the impedance106may comprise a selected resistance. In order to match the first port74, the second port80and the third port82to the impedance Z0, the first transmission line transformer102and the second transmission line transformer104may be configured or selected to provide an impedance of approximately √{square root over (2)}Z0, while the impedance106may be configured or selected to provide an impedance of approximately 2Z0. The various embodiments, which include transmission line transformers are recognized as exhibiting less signal attenuation than others of the various embodiments that employ resistive elements only.

FIG. 8is a schematic view of a divider unit110that also includes a first port74that may be coupled to the memory bus18(as shown inFIGS. 1-4), and a second port80and a third port82that may be coupled to respective memory units, such as the first memory unit20(as shown inFIG. 1) and the second memory unit22(as also shown inFIG. 1).

The divider unit110may also include a third transmission line transformer112and a fourth transmission line transformer114that are tuned to one-quarter of an operational wavelength λ. The third transmission line transformer112and the fourth transmission line transformer114may be serially coupled to the first transmission line transformer102and the second transmission line transformer104, respectively, as well as to the second port80and the third port82, respectively. An impedance116, which may include a selected resistance, may also be coupled to the second port80and the third port82. In order to match the first port74, the second port80, and the third port82to the impedance Z0, the third transmission line transformer112and the fourth transmission line transformer114may be configured to provide a desired impedance, while the impedance116may appropriately selected based upon the impedance of the third transmission line transformer112and the fourth transmission line transformer114to appropriately adjust the impedance match provided by the divider unit110. One skilled in the art will understand that suitable values for the foregoing elements may be readily determined by routine calculation.

FIG. 9is a schematic view of a divider unit that is also configured to be coupled to a first port74, that may be coupled to the memory bus18(FIGS. 1-4). The second port80and the third port82may be configured to be coupled to respective memory units, such as the first memory unit20(as shown inFIG. 1) and the second memory unit22(as also shown inFIG. 1). The divider unit120may also include the first transmission line transformer102and the second transmission line transformer104, which are serially coupled to the second port80and the third port82, respectively. The second transmission line transformer104may also be serially coupled to an impedance122, that is in turn coupled to a ground potential, perhaps provided by a ground plane. In this configuration, the third transmission line transformer112may shunt the first port74to the impedance122, while the fourth transmission line transformer114may shunt the second port80to the third port82. In order to achieve matched operation, the first transmission line transformer102and the second transmission line transformer104may be tuned to have an impedance of approximately 1/(√{square root over (2)}Z0), while the third transmission line transformer112and the fourth transmission line transformer may be tuned to have an impedance of Z0. The impedance122, which may be a pure resistance, may be selected to present an impedance of approximately Z0.

FIG. 10is a schematic view of another divider unit130that is also configured to be coupled to a first port74, that may be coupled to the memory bus18(FIGS. 1-4). The second port80and the third port82may be configured to be coupled to respective memory units, such as the first memory unit20(as shown inFIG. 1) and the second memory unit22(as also shown inFIG. 1). The divider unit130may also includes the first transmission line transformer102and the second transmission line transformer104, which are serially coupled to the second port80and the third port82, respectively. The first transmission line transformer102may be further coupled to the first port72, while the second transmission line transformer104may be further coupled to an impedance132, which may be further coupled to a ground potential, such as that provided by a ground plane. The impedance132may include a pure resistance.

FIG. 11is a schematic view of another divider unit140that may include a network of transmission line transformers142, which may be arranged in a wye-coupled configuration. The network142may include transmission line transformers that are tuned to one quarter of an operational wavelength λ. A first port74of the divider unit140may be coupled to the memory bus18(FIGS. 1-4), while the second port80and the third port82may also be coupled to the network142, and may also be shunted by an impedance144, which may include a pure resistance. The second port80and the third port82may accordingly be coupled to separate memory units, as previously described.

FIG. 12is a schematic view of still another divider unit150that may include a transmission line transformer network152that may further include a star-coupled network of transmission line transformers, or still other configurations, which may be coupled to the memory bus18(FIGS. 1-4) at a first port74. The opposing ends of the network152may be coupled to each of the nodes of a wye-coupled impedance network154, which may include an arrangement of one or more pure resistances. Accordingly, the divider unit150may include a second port80, a third port82and a fourth port156extending from each of the nodes of the impedance network154, which may be coupled to separate memory units.

FIG. 13is a schematic view of another divider unit160. The unit160may include the transmission line transformer network152ofFIG. 12that is configured to be coupled to the memory bus18(FIGS. 1-4), with the opposing ends of the network152coupled to each of the nodes of a delta-coupled impedance network162, which may include an arrangement of one or more pure resistances. Accordingly, the divider unit160may include the second port80, the third port82and the fourth port156extending from each of the nodes of the impedance network154, which may be further coupled to separate memory units. Although the various embodiments shown inFIG. 12andFIG. 13show three output nodes (e.g., the second port80, the third port82and the fourth port156), it is understood that the various embodiments shown inFIG. 12andFIG. 13may conveniently be extended to provide n output nodes, which may be individually coupled to separate memory units. For example, one (or two) resistors could be added to mirror the wye (or delta) coupled impedance networks inFIG. 12(orFIG. 13), and another transformer could be added to the network152to provide a four output nodes, and so on.

FIG. 14is a schematic view of another divider unit170that may be configured to be coupled to the memory bus18(FIGS. 1-4) through the first port74. The first transmission line transformer102and the second transmission line transformer104may be serially coupled to the second port80, while the third transmission line transformer112and the fourth transmission line transformer114may be serially coupled to the third port82. An impedance network172may be coupled to the second port80and the third port82so that the impedance network172shunts the second port80and the third port82. The impedance network172may include a parallel combination of a selected pure resistance and capacitance. Alternatively, the impedance network172may include a selected pure resistance in series with a capacitor.

FIG. 15is a flowchart that will be used to describe a method180of configuring a memory system. At block182, a memory controller is provided that is operable to control communications between a processing unit and a plurality of memory units. At block184, a memory bus is coupled to the memory controller. At block186, a plurality of memory units are provided, which may include individual memory devices, such as a DRAM, an SRAM, an SDRAM, a DDR SDRAM, and a flash memory device, as well as other suitable memory devices. The memory units may also include memory modules having a plurality of discrete memory devices, such as a DIMM, a DDR SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, or other suitable memory modules. At block188, a divider unit may be interposed between the memory bus and the memory units. The divider unit is operable to match an impedance of the memory units to an impedance of the bus, while providing for signal isolation between the memory modules.

FIG. 16is a flowchart that will be used to describe a method190of operating a memory system. At block192, signals are communicated along a memory bus that is coupled between a memory controller and a plurality of memory units. As previously discussed, the memory units may include individual memory devices, or they may include memory modules. At block194, the signal levels communicated along the memory bus are divided by at least one divider unit that is coupled to the bus and the memory units. At block196, a substantially matched impedance between the memory units and the memory bus is provided by at least one divider unit. The divider unit may also provide signal isolation for the memory units. Since it is understood that the memory bus is bidirectional, the signals may also be combined by the divider unit as signals are communicated from the memory units to the memory bus.

Implementing the systems and methods disclosed herein may provide memory systems having improved bandwidth characteristics. The various embodiments may be conveniently provided using passive electrical elements, or a combination of passive and active elements.

Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Furthermore, although the various embodiments been described with reference to memory systems and devices, it is understood that the various embodiments may be employed in a variety of known electronic systems and devices without modification of any kind. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of ordinary skill in the art upon reviewing the above description.

The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features may be grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.