Synchronizing circuit for offset quaternary phase shift keying

A synchronizing circuit for offset quaternary phase shift keying, comprises: a four-phase demodulator 10; a processing module (11, 12); and a phase error calculating circuit (15) followed by a phase correcting circuit (16) which delivers a phase error correction signal. The invention is applicable to telecommunications by microwave beams.

The invention relates to a synchronizing circuit for offset quaternary 
phase shift keying. 
BACKGROUND OF THE INVENTION 
The invention relates to coherent demodulation of signals which have been 
modulated using offset quaternary phase shift keying (OQPSK), which class 
of keying includes the important case of minimum shift keying (MSK). 
This type of keying is being used more and more for microwave beam 
transmission since it offers important advantages, including the advantage 
of presenting a constant envelope. 
The circuit of the invention makes it possible to obtain the phase 
synchronization required for coherent demodulation in a manner which is 
effective and simple. The quality of such a circuit has an important 
influence on the performance of a receiver in terms of error rate. 
Phase synchronization for OQPSK type systems gives rise to problems that do 
not exist in other comparable keying systems (e.g. QPSK and BPSK=Binary 
Phase Shift Keying). 
There are several types of circuit for achieving phase synchronization with 
this OQPSK class of keying. 
The most closely-related types are referred to as follows: 
DD: "Decision Directed" 
In which decisions concerning the symbols are used when calculating the 
error signal for servo-controlling the loop; and 
NDD: "Non-decision Directed" 
In which such decisions are not used. 
An NDD circuit provides performance which is less good than a DD circuit 
(using the criterion of residual variance in phase error). 
The circuit of the invention makes use of decisions and is therefore 
designated below as: 
MDD: "Modified Decision Directed". 
In DD and in NDD circuits, there remains a degree of residual phase error 
noise of non-thermal origin which cannot be reduced for given loop 
bandwidth. In other words, when the signal-to-noise ratio tends towards 
infinity, there remains non-zero fluctuation in the phase error which 
gives rise to a residual error rate. 
This residual noise can be reduced to an arbitrary extent by reducing the 
loop bandwidth, but that prevents the system from tracking random keying 
which is mostly due to the local oscillators at the transmission end and 
at the reception end, and which justifies the use of a wide loop bandwidth 
which may optionally be adaptive as a function of the signal/noise ratio. 
The invention serves to reduce this residual noise very considerably and to 
eliminate it completely in the special case of MSK. 
SUMMARY OF THE INVENTION 
The invention thus provides a synchronizing circuit for offset quaternary 
phase shift keying, and comprising: 
a four-phase demodulator; 
a processing module; and 
a phase error calculating circuit followed by a phase correcting circuit 
which delivers a phase error correction signal. 
Advantageously, the phase loop error voltage is equal to: 
EQU e.sup.p.sub.k =g1(d.sub.-2 -d.sub.k)y.sup.c.sub.k-1 +d.sub.k-1 
.multidot.y.sup.s.sub.k-1 
where y.sub.k-1 is equal to y.sub.k shifted by one bit time, with y.sub.k 
=(-j).sup.k .multidot.x.sub.k =y.sub.k.sup.c +jy.sup.s.sub.k-1, where 
x.sub.k is the output signal from the demodulator and d.sub.k-2 and 
d.sub.k-1 are the signal d.sub.k shifted by two bit periods and by one bit 
period respectively, with d.sub.k being the sign of the real path of 
y.sub.k, and g1=g(T) where T is the bit period and g(t) is the overall 
impulse response of the filtering to which the signal is subjected. 
In a first embodiment of the circuit of the invention, the phase loop error 
voltage is applied to a VCO via a filter in order to provide analog 
control to the demodulator. 
In a second embodiment, the phase loop error voltage is applied to a 
multiplier via a filter, a digital integrator delivering a signal .phi., 
and a circuit for calculating e.sup.-j.phi.. 
Thus, in particular, the invention provides a phase estimator. 
Advantageously, multiplication by (-j).sup.k provides a considerable 
simplification of this estimator, but that is by no means essential for it 
to operate properly. In addition, an independent clock recovery loop may 
be integrated simply in a circuit of the invention. 
Thus, and advantageously, the processor module includes a module for 
multiplying by (-j).sup.k. The clock loop error voltage is equal to: 
e.sub.k.sup.r =-y.sup.s.sub.k-1 .multidot.(d.sub.k +d.sub.k-2) where 
y.sup.s.sub.k-1 is the imaginary part of y.sub.k-1, y.sub.k-1 is the 
signal y.sub.k shifted by one bit period, y.sub.k =(-j).sup.k 
.multidot.x.sub.k, where x.sub.k is the output signal from the 
demodulator, and d.sub.k-2 is the signal d.sub.k shifted by two bit 
periods and d.sub.k is the sign of the real portion of y.sub.k.

DETAILED DESCRIPTION 
As shown in FIG. 1, a circuit in accordance with the invention comprises: 
a demodulator 10 which is a four-phase demodulator; 
a processor module comprising a module 11 for multiplying by (-j).sup.k, 
where k is the sample number, and a decision circuit 12 for obtaining the 
sign of the real portion of the signal y.sub.k delivered by the preceding 
module 11; 
a clock rate error calculation circuit 13 followed by a correction circuit 
14 which delivers a controlling clock signal H; and 
a phase error calculation circuit 15 followed by a correction circuit 16 
which delivers a phase error correction signal. 
The demodulator 10 is a conventional four phase state demodulator in which 
the intermediate frequency signal x(t) or the microwave signal itself is 
directly demodulated, is split into two signals, one using a real path and 
the other an imaginary path, each path respectively comprising a ring 
modulator 30 (31), a filter 32 (33), and a sampling circuit 34 (35) which 
is an analog-to-digital converter. 
The output from this demodulator provides a signal x.sub.k having a real 
component x.sub.k.sup.c and an imaginary component x.sub.k.sup.s, such 
that x.sub.k +x.sub.k.sup.c +jx.sub.k.sup.s. 
This four-phase demodulator 10 is shown in order to situate the 
synchronizing circuit within the reception chain. 
The signals on the real and imaginary paths are digitized at the bit rate 
H, and the resulting samples are considered as being complex numbers. 
The processor module comprises a modulo-4 counter 36 followed by a 
multiplier 37 for obtaining the value (-j).sup.k which is applied to the 
complex multiplier 38 such that its output provides y.sub.k =(-j).sup.k 
.multidot.x.sub.k.sup.c +jy.sub.k.sup.s. 
Thus, the processor module receives samples x.sub.k of interest which 
alternate on two paths and it derives therefrom: 
a sequence of useful samples (y.sub.k.sup.c) on the real path and 
constituting decision variables; and 
a sequence of samples (y.sub.k.sup.s) on the imaginary path and useful for 
phase and clock synchronization purposes. 
The samples x.sub.k are thus multiplied by (-j).sup.k where k is generated 
by the modulo-4 counter which increments at the bit rate. The 
multiplication is performed by a multiplier 38 constituted by a set of 
logic circuits. 
The decision circuit 12 is used to obtain a signal d.sub.k which is the 
sign of the real portion of y.sub.k, which sign constitutes the decision 
concerning the transmitted signals (to within the error due to 
differential decoding). 
Circuits 20, (21), 22, 23, and 24 are delay circuits each providing a delay 
of 1 bit period for deriving the signals y.sup.s k.sub.k-1, 
y.sup.c.sub.k-1, d.sub.k-1, and d.sub.k-2 from the signals y.sub.k.sup.s, 
y.sub.k.sup.c, d.sub.k, and d.sub.k-1, respectively. 
The delay circuits 23 and 24 and the decision circuit 12 may each be 
constituted by a respective D-type bistable, for example. 
However, the delay circuits 20, 21, and 22 for obtaining y.sup.s.sub.k-1, 
y.sup.s.sub.k-1, and y.sup.c.sub.k-1 respectively may be constituted by n 
D-type bistables in parallel (where n is a number depending on the number 
of output bits delivered by the converters 34 and 35). 
The clock rate error calculating circuit 13 comprises an adder 34 and a 
multiplier 40 and serves to calculate the error voltage of the clock loop 
as follows: e.sup.r.sub.k =-y.sup.s.sub.k-1 .multidot.(d.sub.k 
+d.sub.k-2), which voltage is applied to the correction circuit 14 which 
is constituted by a filter 41 followed by a voltage controlled oscillator 
42 (VCO) which delivers a controlling clock signal H, used, in particular, 
in all of the synchronous circuits. 
In the module 11 for performing complex multiplication by (-j).sup.k, k is 
incremented for each period of the bit frequency clock. This operation 
serves to put all of the decision variables onto the real path (as in 
BPSK) even though these variables, prior to multiplication, are spread 
over the real path at instants 2kT and the imaginary path at instants 
2(k+1)T, where T is the bit time. 
This operation considerably reduces the complexity of the circuits 
downstream therefrom, and in particular it simplifies the phase and clock 
synchronizing circuits. 
The clock servo-control loop operates using the known "advance/retard" 
principle. However, this circuit is particularly simple by virtue of the 
multiplication by (-j).sup.k. 
The phase error calculating circuit 15 comprises an adder 44, a subtractor 
45, and two multipliers 46 and 47 for calculating the phase loop error 
voltage as follows: 
EQU e.sup.p.sub.k =g1(d.sub.k-2 -d.sub.k)y.sup.c.sub.k-1 +d.sub.k-1 
.multidot.y.sup.s.sub.k-1 
which voltage is applied to the correction circuit 16 which comprises a 
filter 48 followed by a VCO 49 that delivers an analog control voltage to 
the demodulator 10. 
g1=g(T), where T represents the bit time, and g(t) is the overall impulse 
response of the filtering to which the signal is subjected. g(t) is 
assumed to be even and to satisfy the Nyquist criterion (i.e. g(2kT)=0 for 
k=0 and g(0)=1). 
For OQPSK, g1.apprxeq.0.5, thereby making it possible to simplify the value 
of e.sub.k.sup.p which is reduced to mere addition. For MSK, 
g1.apprxeq.0.13. 
In FIG. 2, items which are identical to items in FIG. 1 have the same 
reference numerals. 
In this variant circuit of the invention, phase loop correction is 
performed on the sampled signals. 
Thus, the phase error voltage e.sub.k.sup.p is applied to the filter 48 as 
before, but its output is now connected to a digital integrator 50 which 
delivers a value .phi. to a circuit 51 for calculating e.sup.-j.phi. 
which is applied to a second complex multiplier 52 connected to the output 
of the first complex multiplier 38 described above. 
The oscillator circuit 49 is no longer connected to the filter 48 and is 
therefore no longer voltage controlled, and thus constitutes a synthesizer 
connected to the demodulator 10. 
Naturally, the present invention has been described and shown merely by way 
of preferred example and its various component parts could be replaced by 
equivalents without thereby going beyond the scope of the invention.