Conservative rasterization

Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for each corner of each pixel in a microtile. Outer coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an OR gate. Inner coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an AND gate. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.

BACKGROUND

In computer graphics, a set of surfaces representing objects in a scene is divided up into a number of smaller and simpler pieces, (referred to as primitives), typically triangles, which are more amenable to rendering. The resulting divided surface is generally an approximation to the original surface, but the accuracy of this approximation can be improved by increasing the number of generated primitives, which in turn usually results in the primitives being smaller. The amount of sub-division is usually determined by a level of detail (LOD). An increased number of primitives is therefore typically used where a higher level of detail is required, e.g. because an object is closer to the viewer and/or the object has a more intricate shape. However, use of larger numbers of triangles increases the processing effort required to render the scene and hence increases the size of the hardware that performs the processing. Furthermore, as the average triangle size reduces, aliasing (e.g. when angled lines appear jagged) occurs more often and hence graphics processing systems employ anti-aliasing techniques which often involve taking several samples per pixel and subsequently filtering the data.

As both the number of primitives that are generated increases, the ability of a graphics processing system to process the primitives becomes more important. One known way of improving the efficiency of a graphics processing system is to render an image in a tile-based manner. In this way, the rendering space into which primitives are to be rendered is divided into a plurality of tiles, which can then be rendered independently from each other. A tile-based graphics system includes a tiling unit to tile the primitives, i.e. to determine, for a primitive, which of the tiles of a rendering space the primitive is in. Then, when a rendering unit renders the tile, it can be given information (e.g. a per-tile list) indicating which primitives should be used to render the tile.

An alternative to tile-based rendering is immediate-mode rendering. In such systems there is no tiling unit generating per-tile lists and each primitive appears to be rendered immediately; however, even in such systems, the rendering space may still be divided into tiles of pixels and rendering of each primitive may still be done on a tile by tile basis with each pixel in a tile being processed before progressing to the next tile. This is done to improve locality of memory references.

The embodiments described below are provided by way of example only and are not limiting of implementations which solve any or all of the disadvantages of known graphics processing pipelines.

SUMMARY

A graphics processing pipeline is described which comprises conservative rasterization hardware. The conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for each corner of each pixel in a microtile in parallel. Inner and outer coverage results for each pixel are then calculated. Outer coverage results are determined, for a particular pixel and particular edge, by combining the edge test results for the four corners of the pixel and the particular edge in an OR gate. Inner coverage results are determined, for a particular pixel and particular edge, by combining the edge test results for the four corners of the pixel and the particular edge in an AND gate. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner. This hardware performs the coverage test precisely.

A first aspect provides graphics processing pipeline arranged to render in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, each tile is sub-divided into a plurality of microtiles, each microtile comprising an identical arrangement of pixels, the graphics processing pipeline comprising conservative rasterization hardware and wherein the conservative rasterization hardware comprises: a plurality of first hardware sub-units each arranged to calculate, for a different edge of a primitive, an outer coverage result for the edge and an inner coverage result for the edge for each pixel in a microtile; and a plurality of second hardware sub-units each arranged to calculate, for a different pixel in a microtile, an outer coverage result for the primitive and an inner coverage result for the primitive, wherein each first hardware sub-unit comprises: edge test calculation hardware arranged to calculate, for each corner of the pixels in the microtile a value indicating whether the pixel corner is to the left of the edge; a plurality of OR logic blocks each configured to perform an OR operation, one for each pixel in the microtile, and each arranged to receive as inputs four values from the edge test calculation hardware, one for each corner of the pixel, and wherein an output of the OR logic block is the outer coverage result for the pixel and the edge; and a first plurality of AND logic blocks each configured to perform an AND operation, one for each pixel in the microtile, and each arranged to receive as inputs four values from the edge test calculation hardware, one for each corner of the pixel and wherein an output of the AND logic block is the inner coverage result for the pixel and the edge; and wherein each second hardware sub-unit comprises: a second plurality of AND logic blocks, one for each pixel in the microtile, and each arranged to receive as inputs an outer coverage result for the pixel and each of the edges, one from each of the first hardware sub-units and wherein an output of the AND logic block is the outer coverage result for the pixel and the primitive; and a third plurality of AND logic blocks, one for each pixel in the microtile, and each arranged to receive as inputs an inner coverage result for the pixel and each of the edges, one from each of the first hardware sub-units and wherein an output of the AND logic block is the inner coverage result for the pixel and the primitive.

A second aspect provides a method of performing conservative rasterization in a graphics pipeline arranged to render in a rendering space, wherein the rendering space is sub-divided into a plurality of tiles, each tile is sub-divided into a plurality of microtiles, each microtile comprising an identical arrangement of pixels, the method comprising: for each edge of a primitive and for each corner of a pixel in the microtile, calculating a value indicating whether the pixel corner is to the left of the edge; and for each pixel, the pixel having four corners: for each edge, combining the four calculated values in an OR logic block to generate and output an outer coverage result for the pixel and the edge; for each edge, combining the four calculated values in an AND logic block to generate and output an inner coverage result for the pixel and the edge; combining outer coverage results for the pixel for each edge of the primitive in an AND logic block to generate and output an outer coverage result for the pixel and the primitive; and combining inner coverage results for the pixel for each edge of the primitive in an AND logic block to generate and output an inner coverage result for the pixel and the primitive.

The graphics processing pipeline comprising conservative rasterization hardware may be embodied in hardware on an integrated circuit. There may be provided a method of manufacturing, at an integrated circuit manufacturing system, a graphics processing pipeline comprising conservative rasterization hardware. There may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the system to manufacture a graphics processing pipeline comprising conservative rasterization hardware. There may be provided a non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed, causes a layout processing system to generate a circuit layout description used in an integrated circuit manufacturing system to manufacture a graphics processing pipeline comprising conservative rasterization hardware.

There may be provided an integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable integrated circuit description that describes the graphics processing pipeline comprising conservative rasterization hardware; a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the graphics processing pipeline comprising conservative rasterization hardware; and an integrated circuit generation system configured to manufacture the graphics processing pipeline comprising conservative rasterization hardware according to the circuit layout description.

There may be provided computer program code for performing any of the methods described herein. There may be provided non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform any of the methods described herein.

DETAILED DESCRIPTION

Embodiments will now be described by way of example only.

Described herein is hardware that performs conservative rasterization. This hardware may be implemented within the rasterization phase of a graphics processing pipeline (e.g. within a graphics processing unit, GPU). Conservative rasterization involves determining whether a square pixel area is fully overlapped by a primitive (this is referred to as ‘inner coverage’), partially overlapped by the primitive (this is referred to as ‘outer coverage’) or not overlapped at all by the primitive. The conservative rasterization hardware described herein provides an efficient way (e.g. in terms of physical size and power consumption) to obtain both outer and inner coverage results.

The hardware described herein relies on the regular sub-division of the rendering space, as can be described with reference toFIGS. 1A and 1B. The rendering space100is divided into a plurality of tiles102(which may, for example, be square or rectangular) and each tile is further divided into a regular arrangement of smaller areas104, referred to as ‘microtiles’. Within each tile102there is a pre-defined arrangement of microtiles104and in various examples, all of the microtiles104are the same size. WhilstFIG. 1Ashows an arrangement of 5×4 microtiles104within a tile102, in other examples there may be a different number of microtiles104in each tile102. Each microtile104comprises the same number (and arrangement) of pixels106. In the example shown inFIGS. 1A and 1B, each microtile104comprises a 4×4 arrangement of 16 pixels106.

As described in detail below, the conservative rasterization hardware described herein calculates an edge test result for the top left corner of each pixel in a microtile (as indicated by the black circles120inFIG. 1B) and additionally calculates an edge test result for the remaining corners of the pixels in the microtile (as indicated by the white circles122inFIG. 1B). For any pixel, the outer coverage result for a single edge of a primitive is obtained by combining in hardware logic (e.g. using an OR gate), the results from all four corners of the pixel and the inner coverage result for the single edge of the primitive is obtained by combining in different hardware logic (e.g. using an AND gate), the results from all four corners of the pixel. In this way, having determined the one coverage result (e.g. the outer coverage result), the other coverage result (e.g. the inner coverage result) can be obtained with minimal added cost (e.g. in terms of size and power consumption). The outer and inner coverage results for the entire primitive (rather than just a single edge of the primitive) for a particular pixel is obtained by combining in hardware logic (e.g. using an AND gate), corresponding results for the pixel for each individual edge. Using the hardware described here, the coverage test is performed precisely (i.e. without any uncertainty margin), although as described below it may create false positives.

FIG. 2Ashows a schematic diagram of an example graphics processing unit (GPU) pipeline200which may be implemented in hardware within a GPU and which uses a tile-based rendering approach. The hardware described herein may also be used in a GPU that instead uses alternative rendering approaches where the rendering processes groups of pixels (e.g. where immediate mode rendering is used). As shown inFIG. 2, the pipeline200comprises a geometry processing phase202and a rasterization phase204. Data generated by the geometry processing phase202may pass directly to the rasterization phase204and/or some of the data may be written to memory (e.g. parameter memory205) by the geometry processing phase202and then read from memory by the rasterization phase204.

The geometry processing phase202comprises a vertex shader206, tessellation unit208and tiling unit210. Between the vertex shader206and the tessellation unit (or tessellator)208there may be one or more optional hull shaders, not shown inFIG. 2. The geometry processing phase202may also comprise other elements not shown inFIG. 2, such as a memory and/or other elements.

The vertex shader206is responsible for performing per-vertex calculations. Unlike the vertex shader, the hardware tessellation unit208(and any optional hull Shaders) operates per-patch and not per-vertex. The tessellation unit208outputs primitives and in systems which use vertex indexing, an output primitive takes the form of three vertex indices and a buffer of vertex data (e.g. for each vertex, a UV coordinate and in various examples, other parameters such as a displacement factor and optionally parent UV coordinates). Where indexing is not used, an output primitive takes the form of three domain vertices, where a domain vertex may comprise only a UV coordinate or may comprise a UV coordinate plus other parameters (e.g. a displacement factor and optionally, parent UV coordinates).

The rasterization phase204renders some or all of the primitives generated by the geometry processing phase202. The rasterization phase204comprises the conservative rasterization hardware212, a coefficient generation hardware block214and may comprise other elements not shown inFIG. 2. The coarse microtile mask and coefficient generation hardware block214generates the coefficients that are used in the conservative rasterization hardware212(e.g. A, B, and C, as defined below).

The conservative rasterization hardware212in the rasterization phase204determines, for each pixel and for each of a plurality of primitives (e.g. each primitive on a per-tile display list), whether the pixel (i.e. the square pixel area, rather than a single sample position within the pixel) is partially or fully overlapped by the primitive. This is referred to as outer and inner coverage respectively. The rasterization hardware212is shown in more detail inFIGS. 3A and 3Band its operation can be described with reference to the flow diagram inFIG. 4.

As described above and shown inFIG. 2B, each primitive21,22,23has a plurality of edges (e.g. three edges for a triangular primitive21). Each edge is defined by an edge equation which is a vector of the form:
ƒ(x,y)=Ax+By+C
where A, B and C are constant coefficients specific to the polygon edge (and hence may be pre-calculated) and C has been pre-adjusted such that the scene origin is translated to the tile origin. The conservative rasterization hardware212determines for each edge of a primitive and for each pixel corner120,122in a microtile104, whether the pixel corner (having coordinates x,y) lies to the left or right or on the edge by calculating the value, or the sign, of ƒ(x, y) for the edge. The calculation is a sum-of-products (SOP).

FIG. 3Ashows a first part300of the conservative rasterization hardware212that relates to a single pixel for a single edge. Each of the edge test hardware elements302calculates, for a different one of the pixel corner120,122, whether the pixel corner lies on the edge or to the left or right of the edge by calculating the value, or the sign, of ƒ(x,y) for the edge (block402). This is because:If ƒ(x,y) is calculated to be positive (i.e. greater than zero), then the pixel corner is to the right of the edge If ƒ(x,y) is calculated to be negative (i.e. less than zero), then the pixel corner is to the left of the edge If ƒ(x,y) is calculated to be exactly zero, then the pixel corner is precisely on the edge

WhilstFIG. 3Aonly shows 5 discrete edge test hardware elements302, it will be appreciated that there may be many more of these and the number will be dependent upon the number of pixels within a microtile (i.e. there may be one edge test hardware element302for each pixel corner in the microtile). If, for example, a microtile comprises a 4×4 arrangement of pixels (as shown inFIG. 1B), there may be 25 edge test hardware elements302, one for each of the pixel corners120,122in the microtile104. Alternatively, the edge test hardware elements302may be combined into edge test hardware logic arranged to calculate multiple edge test results in parallel, e.g. to calculate the edge test results for each of the pixel corners120,122in the microtile104in parallel. By combining the edge test hardware logic, efficiencies may be achieved as hardware and/or intermediate results may be reused, i.e. used in the calculation of more than one edge test result. An example of such combined hardware is described in co-pending UK application no. 1805608.5 and this is also shown inFIGS. 5A, 5B, 5C and 6and described below.

Having calculated the sign (or value) of ƒ(x, y) for each of the pixel corners in a microtile (in hardware elements302and block402), there are four results (i.e. four calculated signs or values) that relate to each square pixel area106(one for each corner of the square pixel area), with most of the results relating to two or more square pixel areas (i.e. where a pixel corner is the corner of two or more adjacent square pixel areas) and hence the results are reused when assessing outer and inner coverage for different pixels (i.e. different square pixel areas).

To generate an outer coverage result, On,i, for a pixel i and edge n, (where both i and n are integers and in the example ofFIG. 1B, i=[0,24]), the negated signs of the four corner results (i.e. negated versions of all of the four calculated signs or the signs of all four calculated values from block402) are combined using an OR gate306(block404). In the example shown inFIG. 3A, the negation is performed using NOT gates305; however, in other examples this be implemented using alternative hardware arrangements.

The outer coverage result, On,i, for a pixel i and edge n, is a single bit and if it is zero it indicates that the edge does not intersect any part of the square pixel area and the entire square pixel area is to the left of the edge vector.

To generate an inner coverage result, In,i, for a pixel i and edge n, the negated signs of the four corner results (i.e. negated versions of all of the four calculated signs or the signs of all four calculated values from block402) are combined using an AND gate306(block406). The inner coverage result, In,i, for a pixel i and edge n, is a single bit and if it is one it indicates that none of the corners of the square pixel area are to the left of the edge vector.

AlthoughFIG. 3Ashows a single OR gate304and a single AND gate306, this is only to reduce the complexity of the diagram. The conservative rasterization hardware212comprises, for each edge, an OR gate304for each pixel in the microtile (i.e. i OR gates) and an AND gate306for each pixel in the microtile (i.e. i AND gates). The hardware arrangement shown inFIG. 3Amay also be replicated for each edge such that in total the conservative rasterization hardware212comprises i×n multiplexers304and an i×n AND gates306. The conservative rasterization hardware212further comprises n hardware elements, one for each edge, arranged to determine the gradient of the edge and generate the select signal for the i multiplexers relating to that edge. Furthermore, the OR gate304(and any other OR gates described herein) may alternatively be replaced by any logic block configured to perform an OR operation (e.g. not-AND-not or adding and comparing, etc.). Such a logic block that is configured to perform an OR operation may be referred to as an OR logic block. Similarly, the AND gate306(and any other AND gates described herein) may alternatively be replaced by any logic block configured to perform an AND operation. Such a logic block that is configured to perform an AND operation may be referred to as an AND logic block.

Having calculated outer coverage results, On,i, for a pixel i and each edge n, the results for the different edges are combined using an AND gate308(block408) as shown inFIG. 3B, which shows a second part320of the conservative rasterization hardware212. This generates a single outer coverage result Oifor the pixel i and if it is zero it indicates that the primitive does not intersect any part of the square pixel area. Conservative rasterization does not permit false negatives for outer coverage results, although a small number of false positives for outer coverage results are permitted. The false positives that are obtained may be removed using a bounding box, as described below.

Having calculated inner coverage results, In,i, for a pixel i and each edge n, the results for the different edges are combined using an AND gate310(block410) as shown inFIG. 3B. This generates a single inner coverage result Iifor the pixel i and if it is zero it indicates that the primitive does not fully cover the square pixel area. The inner coverage is performed precisely and there are no inherent false positives.

As noted above, the outer coverage results obtained using the methods described above includes a number of false positives. The false positives may be removed by applying a bounding box and excluding from the outer coverage positive results, any pixels that are outside the bounding box. The bounding box is generated such that it contains the primitive and may, for example, be computed such that the vertex coordinates of the bounding box are given by the maximum and minimum x and y values of the vertices of the primitive (i.e. top left vertex=(min x, max y,), top right vertex=(max x, max y), bottom right vertex=(max x, min y), bottom left vertex=(min x, min y)). The application of the bounding box may, for example, be implemented by calculating (e.g. in advance) a mask corresponding to the bounding box for a primitive, with all those pixels which are inside the bounding box having a mask bit of one and all those pixels which are outside the bounding box having a mask bit of zero. An AND logic block can then be used to combine the single outer coverage result Oifor the pixel i and the mask bit for the pixel i to generate the final outer coverage result Oi′ for the pixel i. The final outer coverage results for the pixels have fewer false positives than if the bounding box was not applied.

FIGS. 5A and 5Bshow two different example implementations of the edge test hardware302shown inFIG. 3A. As described above, the implementations shown inFIGS. 5A and 5Bmay correspond to multiple edge test hardware elements302and this results in a more efficient hardware implementation (e.g. in terms of physical size and power consumption).

The first example hardware arrangement500, shown inFIG. 5A, comprises a single microtile component hardware element502, a plurality (e.g. one for each corner of a pixel in a microtile, so25for the example shown inFIG. 1B) of pixel component hardware elements504and a plurality (e.g. at least one for each corner of a pixel in a microtile, so at least 25 for the example shown inFIG. 1B) of addition and comparison elements (which may, for example, be implemented as a plurality of adders)508, with each addition and comparison element508generating an output result for a different pixel corner within the same microtile. The hardware arrangement500may additionally comprise one or more multiplexers510that connect the pixel component hardware elements504and optionally the microtile component hardware element(s)502to the addition and comparison elements508. In examples that include multiplexers510, one or more select signals (which may also be referred to as ‘mode signals’ and may comprise a one-hot signal that encodes a particular mode of operation of the hardware) control the operation of the multiplexers510and in particular control which combination of the hardware elements502,504are connected to each particular addition and comparison element508(e.g. for each addition and comparison element508, which one of the plurality pixel component hardware elements504is connected to the addition and comparison element508, with each addition and comparison element508also being connected to the single microtile component hardware element502).

In various examples, the hardware arrangement500may additionally comprise a subsample component element506, but in such cases the output of that element may be set to zero such that it does not affect the output in any way. A subsample component element506may, for example, be provided where the hardware arrangement is also used for other computations, e.g. computations where there is more than one sample per pixel and/or where the output is not a fixed value.

If, as described above, the edge test hardware302evaluates a SOP of the form:
ƒ(x,y)=Ax+By+C
where the values of the coefficients A, B, C may be different for each SOP evaluated, then the microtile component hardware element502evaluates:
ƒUT(xUT,yUT)=AxUT+ByUT+C
where the values of xUTand yUT(the microtile coordinates relative to the tile origin110), differ for different microtiles. The microtile component hardware element502may receive, as inputs, the values of A, B, C, xUTand yUTand the element outputs a single result ƒUT.

The pixel component hardware elements504evaluate:
ƒP(xP,yP)=AxP+ByP
for different values of xPand yP(where these values differ for different pixel corners within a microtile). The set of values of xPand yP(i.e. the values of xPand yPfor all pixel corners within a microtile, as defined relative to the microtile origin) is the same for all microtiles and they may, for example, be calculated by the edge test hardware302or may be accessed from a look-up table (LUT). In various examples, the origin of a microtile may be defined as the top left corner of each microtile and the values of xPand yPmay be integers and so the determination of the values requires little or no computation (and hence this provides an efficient implementation). Referring back to the example shown inFIG. 1A, where each microtile comprises four rows of four pixels and hence there are five rows of five pixel corners as shown inFIG. 1B, then the set of values of xPis {0, 1, 2, 3, 4} (which may also be written as [0,4]) and the set values of yPis {0, 1, 2, 3, 4} (which may also be written [0,4]). Each pixel component hardware element504receives as input A and B and may also receive the set of values of xPand yP(e.g. in examples where these are not integers). Each element504outputs a single result ƒPand consequently the calculation of ƒPmay be merged with any calculations that are performed to determine xPand/or yP.

The subsample component hardware element506, where provided, evaluates:
ƒS(xS,yS)=AxS+ByS
and as there is only a single subsample position per pixel and there is only a single value of xSand yS. Consequently, there is only one value of ƒSand as described above, in various examples, the value of ƒSmay be set to zero.

The addition and comparison elements508evaluate:
ƒ(x,y)=ƒUT+ƒP
or, where there is a subsample component hardware element506:
ƒ(x,y)=ƒUT+ƒP+ƒS
and each addition and comparison element508sums a different combination of ƒUTand ƒPvalues (where the particular combination of values are provided as inputs to the addition and comparison unit508) and the combination is either fixed (i.e. hardwired between the elements) or is selected by one or more multiplexers510(where provided). To perform an edge test only the MSB (or sign-bit) of the result (i.e. of ƒ(x,y)) is output and hence the full result does not need to be calculated by the addition and comparison element508and the addition and comparison element508may perform a comparison rather than an addition (which reduces the overall area of the hardware). This MSB indicates the sign of the result (because a>b===sign (b-a)) and, as described above, this indicates whether the pixel corner is to the left or right of the edge.

The second example hardware arrangement520, shown inFIG. 5B, is a variation on the hardware arrangement500shown inFIG. 5A. This second example hardware arrangement520comprises a single microtile component hardware element502, a plurality (e.g. one for each corner of a pixel in a microtile, so at least 25 for the example shown inFIG. 1B) of pixel component hardware elements524(although these operate slightly differently to those shown inFIG. 5Aand described above) and a plurality (e.g.64) of comparison elements (which may, for example, be implemented as a plurality of adders)528(although these operate slightly differently to the addition and comparison elements508shown inFIG. 5Aand described above), with each comparison element528generating an output result. Like the hardware arrangement500shown inFIG. 5A, the hardware arrangement520shown inFIG. 5Bmay additionally comprise one or more multiplexers510controlled by select signals. Furthermore, in various examples, the hardware arrangement520may additionally comprise a subsample component element506, but in such cases the output of that element may be set to zero such that it does not affect the output in any way.

If, as described above, the edge test hardware302evaluates a SOP of the form:
ƒ(x,y)=Ax+By+C
where the values of the coefficients A, B, C may be different for each SOP evaluated, then the microtile component hardware element502operates as described above with reference toFIG. 5A; however, instead of the output being fed directly into the comparison element528(as shown inFIG. 5A), in the arrangement520ofFIG. 5B, the output of the microtile component hardware element502is input to each of the plurality of pixel component hardware elements524.

The pixel component hardware elements524in the arrangement520ofFIG. 5Bdo not operate in the same way as those shown inFIG. 5A. They receive as input (in addition to A and B) the output from the microtile component hardware element502, ƒUT, and evaluate:
ƒUT(xUT,yUT)+ƒP(xP,yP)=ƒUT(xUT,yUT)+AxP+ByP
for different values of xPand yP(where these values differ for different pixel corners within a microtile). As described above (with reference toFIG. 5A) the values of xPand yP(i.e. the values of xPand yPfor all pixel corners within a microtile, as defined relative to the microtile origin) may be integers and hence the pixel component hardware elements524may comprise an arrangement of adders to add the appropriate multiples of A and/or B to the input value generated by the microtile component hardware element, ƒUT,502and this may be implemented without using any multipliers and this reduces the size and/or power consumption of the comparison unit528. Each element524outputs a single result ƒUT+ƒPand as described above, the calculation of ƒPand hence the calculation of the single result may be merged with any calculations that are performed to determine xPand/or yP.

The comparison elements528evaluate:
ƒ(x,y)=ƒUT+ƒP+ƒS
in a similar manner to the addition and comparison elements408described above; however the inputs are different since the values of ƒUTand ƒPhave already been combined in the pixel component hardware elements424. Each comparison element528sums a different combination of (ƒUT+ƒP) and ƒSvalues (where the particular combinations of values are provided as inputs to the comparison units528) and the combination is either fixed (i.e. hardwired) or is selected by one or more multiplexers510(where provided). To perform an edge test only the MSB (or sign-bit) of the result (i.e. of ƒ(x,y)) is output and hence the full result does not need to be calculated by the comparison elements528. This MSB indicates the sign of the result and, as described above, this indicates whether the subsample position is to the left or right of the edge.

The hardware arrangement520shown inFIG. 5Bmay utilize the fact that the value of ƒPcan be calculated quickly or alternatively the UTC calculation may be performed in the previous pipeline stage. By using this arrangement520the overall area of the hardware arrangement520may be reduced compared to the arrangement500shown inFIG. 5A(e.g. the comparison elements528may be smaller than addition and comparison elements408); however, each of the results output by the pixel component hardware elements524comprises more bits (e.g. approximately 15 more bits) than in the arrangement500shown inFIG. 5A.

As detailed above, in various examples there may be no subsample component hardware element506and in this case, the hardware arrangement540shown inFIG. 5Cmay be used. This hardware arrangement540is a variation on the hardware arrangement520shown inFIG. 5B. As shown inFIG. 5C, the comparison operation (performed by the comparison unit528inFIG. 5B) is combined into the addition operation (performed by the pixel component hardware elements524inFIG. 5B) and implemented in a single pixel component and comparison element544. As in the hardware arrangement shown inFIG. 5B, in the hardware arrangement540shown inFIG. 5C, the output may be fixed (i.e. hardwired) or selected by one or more optional multiplexers510.

AlthoughFIGS. 5A and 5Bshow the hardware elements502,504,506,524being connected to a single addition and comparison element508,528(optionally via multiplexers510), this is to reduce the complexity of the diagram only. As described above, each addition and comparison element508,528generates an output result and the hardware arrangement500,520is, in all examples, arranged to calculate a plurality of results (e.g. one for each pixel corner in a microtile, so25results for the example shown inFIG. 1B) in parallel and hence comprises a plurality of addition and comparison elements508,528(e.g. at least 25 addition and comparison elements).

AlthoughFIGS. 5A, 5B and 5Call show only a single microtile component element502, such that all the results generated in parallel by the hardware arrangement500,520,540relate to pixel corners within the same microtile, in other examples the hardware arrangement may comprise a plurality of microtile component elements502and in such examples, the results generated in parallel by the hardware arrangement may relate to pixel corners within more than one microtile.

In various examples, the hardware arrangement500,520,540may further comprise a plurality of fast decision units530(which may also be referred to as fast fail/pass logic elements), one for each microtile and the condition is then applied to all outputs (e.g. the outputs from all of the plurality of addition and comparison elements508,528,544). The fast decision unit530receives the output generated by the microtile component hardware element502and determines whether, based on the output received, any possible contributions from a pixel component hardware element504,524,544could change the value of the MSB of the value output by the microtile component hardware element502.

If the value output by the microtile component hardware element502, ƒUT, is sufficiently positive that no pixel contribution could make the resultant ƒ(x,y) negative (after taking into consideration any edge rule adjustment), i.e. if:
ƒUT>|ƒPmin|
where ƒPminis the minimum, i.e. most negative, possible value of ƒP, then the hardware arrangement500,520can determine whether the edge test passes or fails without evaluating the outputs generated by the pixel component hardware elements504,524,544(i.e. without completely evaluating the final sum).

Similarly, if the value output by the microtile component hardware element502, ƒUT, is sufficiently negative that no pixel could make the resultant ƒ(x, y) positive or zero, i.e. if:
|ƒUT|>ƒPmax
where ƒPmaxis the maximum, i.e. most positive, possible value of ƒP, then the hardware arrangement500,520,540can determine whether the edge test passes or fails without evaluating the outputs generated by the pixel component hardware elements504,524,544(i.e. without completely evaluating the final sum).

The implementation of the fast decision unit530reduces the width of the addition that is performed by each addition and comparison element508,528as a number of (e.g. three) MSBs from the output generated by the microtile component hardware element502can be omitted from the addition. The precise number of MSBs that can be omitted is determined by the number of microtiles in a tile (i.e. how many XUTbits there are) and the precise constrains on coefficient C.

As described above the hardware arrangements500,520,540are all suitable for use in GPUs which use any rendering approach in which groups of pixels are processed together and this includes both tile-based rendering and immediate-mode rendering. In various examples, the hardware520as shown inFIG. 5Bwith the inclusion of a fast decision unit530may be particularly suited to GPUs which use immediate-mode rendering. This is because immediate-mode rendering results in a larger UTC element502than for tile-based rendering (because the range of coordinates may now cover the entire screen area).

The selection of which hardware arrangement500,520,540to use in any implementation will be dependent upon various factors, including but not limited to the rendering approach used by the GPU. The hardware arrangement500shown inFIG. 5Ahas less delay and fewer registers before the multiplexers510for the PPC elements504, compared to the arrangement in the hardware520shown inFIG. 5B; however, the addition and comparison element508inFIG. 5Ais larger and uses more power than the comparison unit528inFIG. 5B. Consequently, where there are a large number of addition and comparison elements508(e.g. 64 or more), then use of the hardware arrangement520shown inFIG. 5Bmay be more suitable. However, in the hardware arrangement520shown inFIG. 5Bit is not possible to gate out the PPC elements524if only the microtile index changes, but for 64 or more outputs, the reduced complexity of the comparison unit528may provide a dominant effect with respect to power consumption of the hardware.

FIG. 6is a flow diagram of an example method of performing edge detection and/or depth calculation in an efficient manner (i.e. in terms of size of hardware and power consumption) for a rendering space divided into tiles and wherein each tile is subdivided into a plurality of microtiles, each microtile comprising an identical arrangement of pixels. This method uses the hardware described above and shown inFIGS. 5A, 5B and 5Cand may be part of a method of rendering in a graphics processing pipeline.

The method comprises, in a first hardware element502, calculating a first output based on coordinates of a microtile (block602). The method further comprises, in each of a plurality of second hardware elements504,524,544, calculating one of a plurality of second outputs based on coordinates of one of a plurality of pixels within the microtile, (block604) wherein each of the plurality of second hardware elements and each of the plurality of second outputs relates to a different one of the plurality of pixel corners in the microtile. The method further comprises generating a plurality of output values by combining different combinations of the first output and one of the second outputs using one or more addition and/or comparison units (block608), wherein each output value is an edge test output.

In the methods described above, all edges of a primitive are treated in the same way; however, if a pixel is exactly on the edge of an object, an edge rule may be applied so that the pixel is determined to be within (and hence made visible) on only one of the primitives. In various examples, the edge rule may determine that a pixel that lies on the top or left edge lies within the primitive, whereas if the pixel lies on another edge, it is considered to be outside the primitive. These edges may be defined in terms of their A and B coefficients and an example is shown for a triangular primitive in the table below:

The edge rule may, for example, be implemented by subtracting one LSB (least significant bit) in the final summations (e.g. as performed in blocks508,528,544) for right or horizontal bottom edges and this LSB may be subtracted by subtracting one LSB from the output from the microtile component hardware element502. This results in an efficient hardware implementation as it avoids any need for the comparison elements to identify situations where f(x,y) is equal to zero but instead the comparison elements only need to determine the sign of f(x,y) and hence whether f(x,y)≥0.

Using the hardware arrangement and method described above to determine the outer and inner coverage for each pixel in a microtile results in a hardware logic implementation of conservative rasterization that has good utilization (e.g. because it only requires a few additional SOPs to be calculated and because the computation is performed in parallel for all of the pixels in a microtile, results for common pixel corners can be reused instead of being separately calculated and, in various examples, existing hardware in the rasterization phase204can be reused), high performance (e.g. because it does not require any adjustment of edge coefficients or sample positions—adjustment of edge coefficients is complex to implement precisely and any adjustment introduces a delay that is worse for edge adjustments than sample position adjustments) and is both compact (in terms of physical size) and power efficient (e.g. because only a small amount of addition logic is required to calculate inner coverage once the outer coverage has been calculated and it does not require any adjustment of edge coefficients and because the computation is performed in parallel for all of the pixels in a microtile, results for common pixel corners can be reused instead of being separately calculated). Whilst in the example shown inFIG. 1B, in which a microtile comprises a 4×4 array of pixels, there are utilization benefits due to reuse of computed results, for larger arrays of pixels, the increase in utilization achieved using the methods and hardware described herein are more significant.

FIG. 7shows a computer system700in which the graphics processing systems described herein may be implemented. The computer system700comprises a CPU702, a GPU704, a memory706and other devices714, such as a display716, speakers718and a camera720. The graphics processing pipeline, described above, and in particular the conservative rasterization hardware212may be implemented within the GPU704. The components of the computer system can communicate with each other via a communications bus722.

The hardware arrangements shown inFIGS. 2, 3A and 3Band described above are shown as comprising a number of functional blocks. This is schematic only and is not intended to define a strict division between different logic elements of such entities. Each functional block may be provided in any suitable manner. It is to be understood that intermediate values described herein as being formed by any of the elements (e.g. any of the elements inFIGS. 3A and 3B) need not be physically generated by the hardware arrangement at any point and may merely represent logical values which conveniently describe the processing performed by the hardware (e.g. the graphics processing pipeline) between its input and output.

A processor, computer, or computer system may be any kind of device, machine or dedicated circuit, or collection or portion thereof, with processing capability such that it can execute instructions. A processor may be any kind of general purpose or dedicated processor, such as a CPU, GPU, System-on-chip, state machine, media processor, an application-specific integrated circuit (ASIC), a programmable logic array, a field-programmable gate array (FPGA), physics processing units (PPUs), radio processing units (RPUs), digital signal processors (DSPs), general purpose processors (e.g. a general purpose GPU), microprocessors, any processing unit which is designed to accelerate tasks outside of a CPU, etc. A computer or computer system may comprise one or more processors. Those skilled in the art will realize that such processing capabilities are incorporated into many different devices and therefore the term ‘computer’ includes set top boxes, media players, digital radios, PCs, servers, mobile telephones, personal digital assistants and many other devices.

It is also intended to encompass software which defines a configuration of hardware as described herein, such as HDL (hardware description language) software, as is used for designing integrated circuits, or for configuring programmable chips, to carry out desired functions. That is, there may be provided a computer readable storage medium having encoded thereon computer readable program code in the form of an integrated circuit definition dataset that when processed (i.e. run) in an integrated circuit manufacturing system configures the system to manufacture a graphics processing pipeline configured to perform any of the methods described herein, or to manufacture a graphics processing pipeline comprising conservative rasterization hardware described herein. An integrated circuit definition dataset may be, for example, an integrated circuit description.

Therefore, there may be provided a method of manufacturing, at an integrated circuit manufacturing system, a graphics processing pipeline comprising conservative rasterization hardware as described herein. Furthermore, there may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, causes the method of manufacturing a graphics processing pipeline comprising conservative rasterization hardware to be performed.

An integrated circuit definition dataset may be in the form of computer code, for example as a netlist, code for configuring a programmable chip, as a hardware description language defining an integrated circuit at any level, including as register transfer level (RTL) code, as high-level circuit representations such as Verilog or VHDL, and as low-level circuit representations such as OASIS® and GDSII. Higher level representations which logically define an integrated circuit (such as RTL) may be processed at a computer system configured for generating a manufacturing definition of an integrated circuit in the context of a software environment comprising definitions of circuit elements and rules for combining those elements in order to generate the manufacturing definition of an integrated circuit so defined by the representation. As is typically the case with software executing at a computer system so as to define a machine, one or more intermediate user steps (e.g. providing commands, variables etc.) may be required in order for a computer system configured for generating a manufacturing definition of an integrated circuit to execute code defining an integrated circuit so as to generate the manufacturing definition of that integrated circuit.

An example of processing an integrated circuit definition dataset at an integrated circuit manufacturing system so as to configure the system to manufacture a graphics processing pipeline will now be described with respect toFIG. 8.

FIG. 8shows an example of an integrated circuit (IC) manufacturing system802which is configured to manufacture a graphics processing pipeline comprising conservative rasterization hardware as described in any of the examples herein. In particular, the IC manufacturing system802comprises a layout processing system804and an integrated circuit generation system806. The IC manufacturing system802is configured to receive an IC definition dataset (e.g. defining a graphics processing pipeline comprising conservative rasterization hardware as described in any of the examples herein), process the IC definition dataset, and generate an IC according to the IC definition dataset (e.g. which embodies a graphics processing pipeline comprising conservative rasterization hardware as described in any of the examples herein). The processing of the IC definition dataset configures the IC manufacturing system802to manufacture an integrated circuit embodying a graphics processing pipeline comprising conservative rasterization hardware as described in any of the examples herein.

The methods described herein may be performed by a computer configured with software in machine readable form stored on a tangible storage medium e.g. in the form of a computer program comprising computer readable program code for configuring a computer to perform the constituent portions of described methods or in the form of a computer program comprising computer program code means adapted to perform all the steps of any of the methods described herein when the program is run on a computer and where the computer program may be embodied on a computer readable storage medium. Examples of tangible (or non-transitory) storage media include disks, thumb drives, memory cards etc. and do not include propagated signals. The software can be suitable for execution on a parallel processor or a serial processor such that the method steps may be carried out in any suitable order, or simultaneously.

The hardware components described herein may be generated by a non-transitory computer readable storage medium having encoded thereon computer readable program code.

Memories storing machine executable data for use in implementing disclosed aspects can be non-transitory media. Non-transitory media can be volatile or non-volatile. Examples of volatile non-transitory media include semiconductor-based memory, such as SRAM or DRAM. Examples of technologies that can be used to implement non-volatile memory include optical and magnetic memory technologies, flash memory, phase change memory, resistive RAM.

A particular reference to “logic” refers to structure that performs a function or functions. An example of logic includes circuitry that is arranged to perform those function(s). For example, such circuitry may include transistors and/or other hardware elements available in a manufacturing process. Such transistors and/or other elements may be used to form circuitry or structures that implement and/or contain memory, such as registers, flip flops, or latches, logical operators, such as Boolean operations, mathematical operators, such as adders, multipliers, or shifters, and interconnect, by way of example. Such elements may be provided as custom circuits or standard cell libraries, macros, or at other levels of abstraction. Such elements may be interconnected in a specific arrangement. Logic may include circuitry that is fixed function and circuitry can be programmed to perform a function or functions; such programming may be provided from a firmware or software update or control mechanism. Logic identified to perform one function may also include logic that implements a constituent function or sub-process. In an example, hardware logic has circuitry that implements a fixed function operation, or operations, state machine or process.

Any reference to ‘an’ item refers to one or more of those items. The term ‘comprising’ is used herein to mean including the method blocks or elements identified, but that such blocks or elements do not comprise an exclusive list and an apparatus may contain additional blocks or elements and a method may contain additional operations or elements. Furthermore, the blocks, elements and operations are themselves not impliedly closed.

The steps of the methods described herein may be carried out in any suitable order, or simultaneously where appropriate. The arrows between boxes in the figures show one example sequence of method steps but are not intended to exclude other sequences or the performance of multiple steps in parallel. Additionally, individual blocks may be deleted from any of the methods without departing from the spirit and scope of the subject matter described herein. Aspects of any of the examples described above may be combined with aspects of any of the other examples described to form further examples without losing the effect sought. Where elements of the figures are shown connected by arrows, it will be appreciated that these arrows show just one example flow of communications (including data and control messages) between elements. The flow between elements may be in either direction or in both directions.