SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of semiconductor technology, in particular to a semiconductor structure and a manufacturing method thereof.

2. Description of the Prior Art

The development of semiconductor integrated circuit technology progresses continuously and circuit designs in products of the new generation become smaller and more complicated than those of the former generation. In some products, semiconductor devices having different threshold voltages and/or operation voltages are required in the integrated circuits, and the structures of the semiconductor devices may be different from one another for realizing different threshold voltages and/or operation voltages. For example, a relatively thicker gate oxide layer may be used to enhance the operation voltage of a semiconductor device in the relatively higher voltage area, and height differences between parts in the relatively higher voltage area and parts in the relatively lower voltage area may be generated accordingly. The height differences may cause problems in the related manufacturing processes and have negative influence on the manufacturing yield.

SUMMARY OF THE INVENTION

It is one object of the present invention to provide an improved semiconductor structure and a fabrication method thereof to solve the above-mentioned shortcomings or deficiencies of the prior art.

One aspect of the invention provides a semiconductor structure including a substrate comprising a first device region and a second device region in proximity to the first device region, and a trench isolation structure in the substrate between the first device region and the second device region. The trench isolation structure comprises a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

According to some embodiments, the trench isolation structure comprises a first top surface within the first device region and a second top surface within the second device region, wherein the first top surface is coplanar with the second top surface.

According to some embodiments, the first device region is a medium-voltage device region and the second device region is a low-voltage device region.

According to some embodiments, a top surface of the substrate within the first device region is lower than a top surface of the substrate within the second device region.

According to some embodiments, the semiconductor structure further includes a first gate oxide layer on the top surface of the substrate within the first device region, and a second gate oxide layer on the top surface of the substrate within the second device region, wherein the first gate oxide layer is thicker than the second gate oxide layer.

According to some embodiments, the semiconductor structure further includes a first gate disposed on the first gate oxide layer within the first device region, and a second gate disposed on the second gate oxide layer within the second device region.

According to some embodiments, the first gate and the second gate are metal gates.

Another aspect of the invention provides a method for fabricating a semiconductor structure. A substrate is provided, which includes a first device region and a second device region in proximity to the first device region. A trench isolation structure is formed in the substrate between the first device region and the second device region. A mask layer is conformally deposited on the substrate to cover the first device region, the second device region, and the trench isolation structure. A first resist pattern is formed on the mask layer. The first resist pattern covers the trench isolation structure and the second device region. The mask layer and a pad oxide layer which are not covered by the first resist pattern are then removed from the first device region, thereby exposing a top surface of the substrate in the first device region. The first resist pattern is then removed. The top surface of the substrate in the first device region is oxidized to form a sacrificial oxide layer. The sacrificial oxide layer is then removed to expose the top surface of the substrate in the first device region. The mask layer is removed to expose a top surface of the trench isolation structure.

According to some embodiments, the mask layer is a silicon nitride layer.

According to some embodiments, the mask layer has a thickness of about 200-220 angstroms.

According to some embodiments, the pad oxide layer has a thickness of about 100-110 angstroms.

According to some embodiments, the method further includes the step of growing a first gate oxide layer on the top surface of the substrate in the first device region after removing the mask layer.

According to some embodiments, the first gate oxide layer has a thickness of about 200-220 angstroms.

According to some embodiments, a thickness of the top surface of the substrate in the first device region consumed by forming the sacrificial oxide layer is about 190-210 angstroms.

According to some embodiments, a second resist pattern is formed on the substrate. The second resist pattern covers the first gate oxide layer within the first device region, but does not cover the trench isolation structure and the second device region. The trench isolation structure and the second device region are then etched, thereby exposing a top surface of the substrate in the second device region. The second resist pattern is then removed.

According to some embodiments, the method further includes the step of growing a second gate oxide layer on the top surface of the substrate in the second device region.

According to some embodiments, the trench isolation structure comprises a first top surface within the first device region and a second top surface within the second device region, wherein the first top surface is coplanar with the second top surface.

According to some embodiments, the top surface of the substrate in the first device region is lower than the top surface of the substrate in the second device region.

According to some embodiments, the trench isolation structure comprises a first bottom surface within the first device region and a second bottom surface within the second device region, wherein the first bottom surface is coplanar with the second bottom surface.

According to some embodiments, the first device region is a medium-voltage device region and the second device region is a low-voltage device region.

DETAILED DESCRIPTION

In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

Please refer toFIG.1toFIG.10, which are schematic cross-sectional diagrams of a method for fabricating a semiconductor structure according to an embodiment of the present invention. As shown inFIG.1, first, a substrate100is provided, for example, a semiconductor substrate such as a silicon substrate. According to an embodiment of the present invention, the substrate100includes a first device region RM and a second device region RL in proximity to the first device region RM. According to an embodiment of the present invention, the first device region RM is a medium-voltage device region, and the second device region RL is a low-voltage device region. A trench isolation structure200, for example, shallow trench isolation (STI) structure, is formed in the substrate100between the first device region RM and the second device region RL.

According to an embodiment of the present invention, for example, to form the trench isolation structure200, a pad oxide layer102and a pad nitride layer104are first deposited on the top surface100aof the substrate100. The pad nitride layer104is then patterned by a lithography process and an etching process. An etching process is then performed to form a trench201in the substrate100. An insulating layer is then deposited in the trench201, and is planarized by a chemical mechanical polishing (CMP) process to complete the trench isolation structure200. At this point, the top surface200aof the trench isolation structure200and the top surface104aof the pad nitride layer104are coplanar.

As shown inFIG.2, subsequently, the pad nitride layer104is selectively removed, and the pad oxide layer102is exposed. At this point, the top of the trench isolation structure200may protrude from the pad oxide layer102. Threshold voltage (Vt) implantation processes may be performed to adjust the dopant concentration of the first device region RM and the second device region RL respectively.

Subsequently, a mask layer214is conformally deposited on the substrate100to cover the first device region RM, the second device region RL, and the trench isolation structure200. According to an embodiment of the present invention, the mask layer214is a silicon nitride layer. According to an embodiment of the present invention, the thickness of the mask layer214is about 200-220 angstroms. According to an embodiment of the present invention, the thickness of the pad oxide layer102is about 100-110 angstroms.

As shown inFIG.3, a first photoresist pattern PR1is formed on the mask layer214. The first photoresist pattern PR1covers the trench isolation structure200and the second device region RL. According to an embodiment of the present invention, the formation of the first photoresist pattern PR1involves multiple steps such as photoresist coating, exposure, development, and baking. Since the formation of the photoresist pattern is a well-known technology, the details will not be repeated.

As shown inFIG.4, subsequently, the mask layer214and the pad oxide layer102that are not covered by the first photoresist pattern PR1are removed from the first device region RL, thereby exposing the top surface100aof the substrate100in the first device region RL. According to an embodiment of the present invention, the method for removing the mask layer214may include dry etching and wet etching. For example, an anisotropic dry etching process is first performed to etch the mask layer214not covered by the first photoresist pattern PR1, and the pad oxide layer102is then selectively removed by a wet etching process. At this point, an undercut structure214cmay be formed near the trench isolation structure200and under the mask layer214on the sidewall200sof the trench isolation structure200. Subsequently, the first photoresist pattern PR1is removed.

As shown inFIG.5, an oxidation process is then performed to oxidize the top surface100aof the substrate100in the first device region RM to form a sacrificial oxide layer230. According to an embodiment of the present invention, the thickness of the sacrificial oxide layer230is about 420-450 angstroms, for example, 440 angstroms. According to an embodiment of the present invention, when the sacrificial oxide layer230is formed, the consumed thickness of the top surface100aof the substrate100of the first device region RM is about 190-210 angstroms. According to an embodiment of the present invention, the undercut structure214cmay be filled with the sacrificial oxide layer230.

As shown inFIG.6, subsequently, the sacrificial oxide layer230is selectively removed to expose the top surface100aof the substrate100in the first device region RM. According to an embodiment of the present invention, the method of selectively removing the sacrificial oxide layer230may be implemented by using a diluted hydrofluoric acid (DHF) solution. Subsequently, the remaining mask layer214is removed to expose the top surface200aof the trench isolation structure200and the pad oxide layer102in the second device region RL.

As shown inFIG.7, after the mask layer214is removed, a first gate oxide layer310is grown on the top surface100aof the substrate100in the first device region RM by using an oxidation process. According to an embodiment of the present invention, the thickness of the first gate oxide layer310is about 200-220 angstroms.

As shown inFIG.8, next, a second photoresist pattern PR2is formed on the substrate100. The second photoresist pattern PR2covers the first gate oxide layer310in the first device region RM, but does not cover the trench isolation structure200and the second device region RL. According to an embodiment of the present invention, the opening PRO of the second photoresist pattern PR2exposes the trench isolation structure200and the pad oxide layer102in the second device region RL.

As shown inFIG.9, an etching process is performed to etch the trench isolation structure200and the pad oxide layer102in the second device region RL through the opening PRO of the second photoresist pattern PR2, thereby exposing the top surface100bof the substrate100in the second device region RL. Then, the second photoresist pattern PR2is removed. At this point, the top surface310aof the first gate oxide layer310in the first device region RM is approximately flush with the top surface200aof the trench isolation structure200and the top surface100bof the substrate100in the second device region RL.

According to an embodiment of the present invention, the top surface200aof the trench isolation structure200includes a first top surface TS1in the first device region RM and a second top surface TS2in the second device region RL. The first top surface TS1is flush with the second top surface TS2. According to an embodiment of the present invention, the trench isolation structure200includes a first bottom surface BS1in the first device region RM and a second bottom surface BS2in the second device region RL. The first bottom surface BS1is flush with the second bottom surface BS2. According to an embodiment of the present invention, the top surface100aof the substrate100in the first device region RM is lower than the top surface100bof the substrate100in the second device region RL.

As shown inFIG.10, next, a second gate oxide layer320is grown on the top surface100bof the substrate100in the second device region RL by using an oxidation process. According to an embodiment of the present invention, for example, the thickness of the second gate oxide layer320is about 10 angstroms, but it is not limited thereto. Subsequently, a first gate410and a second gate420are formed on the first gate oxide layer310in the first device region RM and the second gate oxide layer320in the second device region RL, respectively. According to an embodiment of the present invention, the first gate410and the second gate420may be surrounded by the dielectric layer IL. According to an embodiment of the present invention, for example, the first gate410and the second gate420may be metal gates.

The structural features of the present invention can be seen fromFIG.10. The semiconductor structure1includes a substrate100having thereon a first device region RM and a second device region RL in proximity to the first device region RM. The trench isolation structure200is provided in the substrate100between the first device region RM and the second device region RL. The trench isolation structure200includes the first bottom surface BS1in the first device region RM and the second bottom surface BS2in the second device region RL. The first bottom surface BS1is coplanar with the second bottom surface BS2.

According to an embodiment of the present invention, the trench isolation structure200includes a first top surface TS1in the first device region RM and a second top surface TS2in the second device region RL. The first top surface TS1and the second top surface TS2are coplanar.

According to an embodiment of the present invention, the first device region RM is a medium-voltage device region, and the second device region RL is a low-voltage device region.

According to an embodiment of the present invention, the top surface100aof the substrate100in the first device region RM is lower than the top surface100bof the substrate100in the second device region RL.

According to an embodiment of the present invention, the semiconductor structure1further includes a first gate oxide layer310located on the top surface100aof the substrate100in the first device region RM, and a second gate oxide layer320located on the top surface100bof the substrate100in the second device region RL. According to an embodiment of the present invention, the first gate oxide layer310is thicker than the second gate oxide layer320.

According to an embodiment of the present invention, the semiconductor structure1further includes a first gate410disposed on the first gate oxide layer310in the first device region RM, and a second gate420disposed on the second gate oxide layer320in the second device region RL. According to an embodiment of the present invention, for example, the first gate410and the second gate420may be metal gates.