Germanium lateral bipolar junction transistor

A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.

BACKGROUND

The present disclosure relates to a lateral bipolar junction transistor (BJT) structure, and particularly to a germanium lateral bipolar junction transistor and methods of manufacturing the same.

Germanium has a narrower band gap than silicon, and provides a great potential for providing a fast bipolar junction transistor that operates at low voltages. A silicon BJT typically operates at about 1 V while a germanium BJT typically operates at about 0.6 V. However, manufacture of a germanium-based device has been a challenge because germanium oxide is soluble in water. Thus, the advantageous properties of germanium derived from the narrower band gap has been only partly utilized through use of a silicon-germanium alloy, which has a band gap that is narrower than the band gap of silicon, and is wider than the band gap of germanium.

SUMMARY

A germanium lateral bipolar transistor is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap base contact for minority carriers is provided between the silicon base region and the germanium base region, resulting in reduced minority carriers injection into the base contact, and a wide gap emitter contact for minority carriers is provided between the silicon emitter region and the germanium emitter region, resulting in reduced minority carriers injection into the emitter contact, so as to provide a greater amplification ratio between the base current and the emitter current.

According to an aspect of the present disclosure, a semiconductor structure including a bipolar junction transistor (BJT) is provided. The BJT comprises a doped germanium layer in contact with an insulator layer and including a germanium base region including dopants of a first conductivity type, a germanium emitter region in contact with the germanium base region and including dopants of a second conductivity type that is the opposite type of the first conductivity type, and a germanium collector region in contact with the germanium base region and including dopants of the second conductivity type. The BJT further comprises a silicon passivation layer in contact with the doped germanium layer and including a silicon base region, a silicon emitter region in contact with the silicon base region, and a silicon collector region in contact with the silicon base region. The silicon base region includes dopants of the first conductivity type and contacts the germanium base region, the silicon emitter region includes dopants of the second conductivity type and contacts the germanium emitter region, and the silicon collector region includes dopants of the second conductivity type and contacts the germanium collector region. In addition, the BJT includes an extrinsic base region in contact with the silicon base region.

According to another aspect of the present disclosure, a method of forming a semiconductor structure including a bipolar junction transistor (BJT) is provided. A substrate is provided, which includes a vertical stack of an insulator layer and a germanium layer having a doping of a first conductivity type. A silicon passivation layer is formed on the germanium layer. An extrinsic base region is formed on the silicon passivation layer. Regions having a doping of a second conductivity type that is the opposite of the first conductivity type are formed in the germanium layer and in the silicon passivation layer by ion implantation of dopants of the second conductivity type. A germanium emitter region and a germanium collector region are formed in the germanium layer, and a silicon emitter region and a silicon collector region are formed in the silicon passivation layer.

DETAILED DESCRIPTION

As stated above, the present disclosure relates to a germanium lateral bipolar junction transistor and methods of manufacturing the same, which are now described in detail with accompanying figures. It is noted that like and corresponding elements mentioned herein and illustrated in the drawings are referred to by like reference numerals.

Referring toFIG. 1, an exemplary semiconductor structure according to an embodiment of the present disclosure can be formed by providing a germanium-on-insulator (GOI) substrate. The GOI substrate can include a stack, from bottom to top, of a handle substrate10, a buried insulator layer20contacting a top surface of the handle substrate10, and a germanium layer52L contacting the top surface of the buried insulator layer20. The germanium layer52L as provided can include a single crystalline germanium material that extends across the entirety of the buried insulator layer20.

The handle substrate10can include a semiconductor material, an insulator material, a conductor material, or a combination thereof. In one example, the handle substrate10can include a semiconductor material such as silicon. If the handle substrate10includes a semiconductor material, the handle substrate10can be undoped or have a p-type doping or an n-type doping.

The buried insulator layer20includes a dielectric material such as silicon oxide and/or silicon nitride. For example, the buried insulator layer20can include thermal silicon oxide. The thickness of the buried insulator layer20can be from 5 nm to 1000 nm, and typically from 100 nm to 200 nm, although lesser and greater thicknesses can also be employed. The buried insulator layer20may, or may not, include multiple dielectric layers, e.g., a stack including at least a silicon oxide layer and a silicon nitride layer.

In one embodiment, the top surface of the buried insulator layer20can include a silicon nitride layer or a silicon oxynitride layer in order to prevent oxidation of the bottom portion of the germanium layer52L. The handle substrate10in the GOI substrate (10,20,52L) contacts a planar bottom surface of the buried insulator layer20.

The germanium layer52L as provided in the GOI substrate can be a planar semiconductor material layer having a first thickness. The first thickness can be, for example, from 5 nm to 1,000 nm, although lesser and greater thicknesses can also be employed. The germanium layer52L is a single crystalline germanium layer. The germanium layer52L can be doped with electrical dopants, which can be p-type dopants or n-type dopants. The type of dopants in the germanium layer52L is herein referred to as a first conductivity type. The germanium layer52L can consist essentially of germanium and the dopants of the first conductivity type.

If the first conductivity type is p-type, the electrical dopants in the germanium layer52L can be, for example, B, Al, Ga, In, and/or Tl. If the first conductivity type is n-type, the electrical dopants can be, for example, P, As, and/or Sb. The dopant concentration in the germanium layer52L can be from 1.0×1015/cm3to 3.0×1019/cm3, although lesser and greater dopant concentrations can also be employed.

A silicon passivation layer54L is formed upon the germanium layer52L. The silicon passivation layer54L includes silicon and optionally dopants of the first conductivity type. The silicon passivation layer54L can be formed as a polycrystalline layer or an amorphous layer. As used herein, a “polycrystalline” layer refers to a layer having any type of polycrystalline structure including microcrystalline and nanocrystalline structures. In one embodiment, the silicon passivation layer54L can be formed as a polycrystalline layer. In another embodiment, the silicon passivation layer54L can be formed as an amorphous layer and then annealed to be converted into a polycrystalline layer. In yet another embodiment, silicon passivation layer54L can be formed as an amorphous layer and conversion into a polycrystalline layer may be postponed until after a subsequent processing step such as formation of an extrinsic base region, formation of a dielectric spacer, implantation of dopants to form emitter and collector regions, or formation of emitter contact regions and collector contact regions.

The silicon passivation layer54L passivates the surface of the germanium layer52L, thereby preventing oxidation of the germanium layer52L. The silicon passivation layer54L can be formed by chemical vapor deposition (CVD), vacuum evaporation, molecular beam deposition, atomic layer deposition (ALD), and/or physical vapor deposition (PVD). The silicon passivation layer54L conformally covers the entirety of the top surface of the germanium layer52L. The thickness of the silicon passivation layer54L is selected so as to enable complete coverage of the surface of the germanium layer52L. Due to the lattice mismatch between the germanium lattice constant and the silicon lattice constant, the silicon passivation layer54L cannot be deposited with epitaxial alignment to the germanium layer52L, and is deposited in Stranski-Krastanov growth mode. Thus, the thickness of the silicon passivation layer54L is herein referred to as a second thickness, and is greater than 1 monolayer of silicon. In one embodiment, the second thickness of the silicon passivation layer54L can be from 2 nm to 50 nm, although lesser and greater thicknesses can also be employed. The first thickness can be at least twice the second thickness.

The silicon passivation layer54L can be in-situ doped or ex-situ doped (for example, by ion implantation after deposition of an intrinsic silicon material) with dopants of the first conductivity type. The concentration of the first conductivity type dopants in the silicon passivation layer54L can be comparable to the concentration of the first conductivity type dopants in the germanium layer52L. Alternately, the silicon passivation layer54L can be deposited as an intrinsic layer, which can be subsequently doped during a thermal anneal to be doped with some of the dopants of the first conductivity type in the germanium layer20. The vertical stack of the germanium layer and the silicon passivation layer54L is herein referred to a semiconductor layer stack50L. Upon formation of the silicon passivation layer54L, the GOI substrate8includes a stack, from bottom to top, of the handle substrate10, the buried insulator layer20, and the semiconductor layer stack50L.

Referring toFIG. 2, at least one shallow trench extending at least to the top surface of the buried insulator layer20is formed through the semiconductor layer stack50L, and is subsequently filled with a dielectric material such as silicon oxide, silicon nitride, and/or silicon oxynitride. The at least one shallow trench can be formed to laterally enclose an unetched region of the semiconductor layer stack50L. The dielectric material can be deposited, for example, by chemical vapor deposition (CVD).

Excess portions of the dielectric material is removed from above the top surface of the top semiconductor portion, for example, by a recess etch or chemical mechanical planarization (CMP). A remaining portion of the dielectric material that fills the at least one shallow trench constitutes at least one shallow trench isolation structure32. One of the at least one shallow trench isolation structure laterally encloses, and contacts all sidewalls of, a remaining portion of the semiconductor layer stack50L, i.e., a remaining portion of the vertical stack of the germanium layer52L and the silicon passivation layer54L. The top surface of the shallow trench isolation structure32can be coplanar with, raised above, or recessed below, the top surface of the semiconductor layer stack50L.

Referring toFIG. 3, an extrinsic base layer58L and a base cap layer59L are sequentially deposited over semiconductor layer stack50L. The extrinsic base layer58L can be a doped semiconductor material layer having a doping of the first conductivity type. The doped semiconductor material of the extrinsic base layer58L is herein referred to as an extrinsic base region semiconductor material. In one embodiment, the extrinsic base layer58L includes a different semiconductor material than the silicon passivation layer54L. In another embodiment, the extrinsic base layer58L includes a same semiconductor material as the silicon passivation layer54L. In one embodiment, the extrinsic base layer58L can be polycrystalline or amorphous as deposited. The extrinsic base layer58L is polycrystalline as deposited, or is amorphous as deposited and is converted into a polycrystalline material in a subsequent thermal processing step (such as an activation anneal after formation of emitter regions and collector regions).

The extrinsic base layer58L has a doping of the first conductivity type. The extrinsic base layer58L can be in-situ doped during deposition, or can be deposited as an intrinsic semiconductor material layer and subsequently doped by ion implantation, gas phase doping, plasma doping, or diffusion of electrical dopants from a disposable dopant source layer (such as a phosphosilicate glass layer, a borosilicate glass layer, or an arsenosilicate glass layer). For example, the extrinsic base layer58L includes dopants of the first conductivity type at a dopant concentration from 1.0×1018/cm3to 3.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. In one embodiment, the extrinsic base layer58L can include a doped polycrystalline material having a doping of the first conductivity type. The extrinsic base layer58L can be deposited, for example, by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The thickness of the extrinsic base layer58L can be from 10 nm to 1,000 nm, although lesser and greater thicknesses can also be employed.

The base cap layer59L includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a dielectric metal oxide, or a combination thereof. The base cap layer59L can be deposited, for example, by chemical vapor deposition (CVD). The thickness of the base cap layer59L can be from 10 nm to 1,000 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the thickness of the base cap layer59L can be selected to have the same stopping power as, or a greater stopping power than, the semiconductor layer stack50L for ion implantation, to be subsequently performed, of dopants of a second conductivity type that is the opposite of the first conductivity type. In one embodiment, a dielectric material different from the dielectric materials of the shallow trench isolation structure32is employed for the base cap layer59L so that the material of the base cap layer59L can be subsequently removed selective to the material of the shallow trench isolation structure.

Referring toFIG. 4, the stack of the base cap layer59L and the extrinsic base layer58L is patterned, for example, by applying and lithographically patterning a photoresist layer (not shown) and transferring the pattern in the patterned photoresist layer through the stack of the base cap layer59L and the extrinsic base layer58L. A remaining portion of the base cap layer59L is herein referred to as a base cap59, and a remaining portion of the extrinsic base layer58L is herein referred to as an extrinsic base region58. The transfer of the pattern from the patterned photoresist layer to the stack of the base cap layer59L and the extrinsic base layer58L can be effected by an anisotropic etch. In this case, the sidewalls of the extrinsic base region58can be substantially vertically coincident with sidewalls of the base cap59. As used herein, a first surface is vertically coincident with a second surface if the first and second surfaces are within a same two-dimensional vertical plane. As used herein, a first surface is substantially vertically coincident with a second surface if a first two-dimensional vertical plane including the first surface and a second two-dimensional vertical plane including the second surface are either vertically coincident, or parallel to each other and laterally separated from each other by no more than the sum of the root-mean-square surface roughness of the first surface and the root-mean-square surface roughness of the second surface.

The horizontal cross-sectional shape of the base cap59and the extrinsic base region58is selected such that the stack of the extrinsic base region58and the base cap59straddles over a middle portion of the semiconductor layer stack50L that is laterally surrounded by the shallow trench isolation structure32. The stack of the extrinsic base region58and the base cap59can extend across the semiconductor layer stack50L, and two end portions of the stack of the extrinsic base region58and the base cap59can overlie the shallow trench isolation structure32. Thus, the top surface of a first peripheral portion of the silicon passivation layer54L is physically exposed on one side of the stack of the extrinsic base region58and the base cap59, and the top surface of a second peripheral portion of the silicon passivation layer54L is physically exposed on another side of the stack of the extrinsic base region58and the base cap59after formation of the stack of the extrinsic base region58and the base cap59.

The endpointing of the anisotropic etch that forms the stack of the extrinsic base region58and the base cap59can be effected by detecting physical exposure of the top surface of the shallow trench isolation structure32through optical means or through detection of change of radical composition in the plasma of the anisotropic etch. Alternately or additionally, if the extrinsic base region semiconductor material is different from silicon, the endpointing of the anisotropic etch can be effected by detecting physical exposure of the top surface of the silicon passivation layer54L through optical means or through detection of change of radical composition in the plasma of the anisotropic etch. Yet alternately or additionally, if there exists an interfacial layer such as a native oxide layer (having a thickness on the order of one atomic layer of a semiconductor oxide) at the interface between the silicon passivation layer54L and the extrinsic base layer58L, an etch chemistry that is highly selective to a semiconductor oxide can be employed to minimize an overetch into the silicon passivation layer54L.

In one embodiment, physically exposed surfaces of the silicon passivation layer54L after the anisotropic etch can be coplanar with the interface between the silicon passivation layer54L and the extrinsic base region58. In another embodiment, physically exposed surfaces of the silicon passivation layer54L after the anisotropic etch can be recessed relative to the interface between the silicon passivation layer54L and the extrinsic base region58. While the present disclosure is described employing an anisotropic etch, embodiment in which an isotropic etch such as a wet etch is employed to transfer the pattern in the patterned photoresist layer through the stack of the extrinsic base region58and the base cap59are also contemplated. Use of an isotropic etch may be suitable if the lateral dimension of the extrinsic base region58is not critical for the purposes of application of a bipolar junction transistor to be formed. The patterned photoresist layer can be subsequently removed, for example, by ashing. The extrinsic base region58includes the extrinsic base region semiconductor material, has a doping of the first conductivity type, and provides an electrical contact to the portion of the silicon passivation layer54L that is in contact with the extrinsic base region58.

A dielectric spacer70can be formed on sidewalls of the extrinsic base region58and on portions of the top surface of the silicon passivation layer54L that are proximal to the sidewalls of the extrinsic base region58. The dielectric spacer70includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, organosilicate glass, or any dielectric material that can be employed to form a spacer as known in the art. In one embodiment, the material of the dielectric spacer70is selected to be different from the dielectric material of the base cap59so that the material of the base cap59can be subsequently removed selective to the material of the dielectric spacer70.

The dielectric spacer70can be formed, for example, by conformal deposition of a dielectric material layer and subsequent anisotropic etch that removes the horizontal portions of the deposited dielectric material layer. The dielectric material layer can be deposited on sidewalls of the extrinsic base region58and on physically exposed top surfaces of the silicon passivation layer54L. The conformal deposition of the dielectric material layer can be performed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof. The horizontal portions of the dielectric material layer can be removed by an anisotropic etch. A remaining portion of the dielectric material layer is the dielectric spacer70. The thickness of the dielectric spacer70, as measured at the base that contact the silicon passivation layer54L, can be from 10 nm to 300 nm, although lesser and greater thicknesses can also be employed. The dielectric spacer70is of unitary construction (in a single piece), and laterally contacts the sidewalls of the extrinsic base region58and the base cap59.

Referring toFIG. 5, regions having a doping of a second conductivity type are formed in the germanium layer52L and in the silicon passivation layer54L, for example, by ion implantation of dopants of the second conductivity type. Specifically, dopants of the second conductivity type are introduced into regions of the silicon passivation layer54L and the germanium layer52L that are not covered by the dielectric spacer70and the stack of the extrinsic base region58and the base cap59. The second conductivity type is the opposite of the first conductivity type. If the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopants of the second conductivity type can be introduced, for example, by ion implantation employing the combination of the dielectric spacer70and the stack of the extrinsic base region58and the base cap59as an implantation mask. An additional implantation mask (not shown) such as a patterned photoresist layer can also be employed if multiple devices (not shown) are present on the substrate8.

A germanium emitter region52E and a germanium collector region52C are formed in the implanted regions of the germanium layer52L, and a silicon emitter region54E and a silicon collector region54C are formed in the implanted regions of the silicon passivation layer54L. Specifically, introduction of dopants of the second conductivity type converts a first region of the germanium layer52L into a germanium emitter region52E and a second region of the germanium layer52L into a germanium collector layer52C. Further, introduction of dopants of the second conductivity type converts a first region of the silicon passivation layer54L into a silicon emitter region54E and a second region of the silicon passivation layer into a silicon collector region54C.

A remaining region of the germanium layer52L that is not implanted with dopants of the second conductivity constitutes a germanium base region52B that laterally contacts the germanium emitter region52E and the germanium collector region52C. A remaining region of the silicon passivation layer54L that is not implanted with dopants of the second conductivity type constitutes a silicon base region54B that laterally contacts the silicon emitter region54E and the silicon collector region54C and vertically contacts the germanium base region52B and the extrinsic base region58. The germanium emitter region52E, the germanium collector layer52C, the silicon emitter region54E, and the silicon collector region54C can be formed simultaneously, for example, by the ion implantation. The extrinsic base region58vertically contacts the silicon base region54B, and has a doping of the first conductivity type.

In one embodiment, the germanium emitter region52E and the germanium collector region52C can have a same dopant concentration of dopants of the second conductivity type. The net dopant concentration of dopants of the second conductivity type, i.e., the concentration of the dopants of the second conductivity type less the concentration of dopants of the first conductivity type, in the germanium emitter region52E and the germanium collector region52C can be, for example, from 1.0×1017/cm3to 3.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. In another embodiment, a masking layer (not shown) can be employed to provide asymmetric net dopant concentration of dopants of the second conductivity type across the germanium emitter region52E and the germanium collector region52C, and across the silicon emitter region54E and the silicon collector region54C. As used herein, the type of doping in any semiconductor region is determined by the conductivity type of the net dopant concentration.

In one embodiment, the germanium emitter region52E and the germanium collector region52C can include implanted dopants of the second conductivity type at a same first atomic concentration after the ion implantation. In one embodiment, the silicon emitter region54E and the silicon collector region54C can include implanted dopants of the second conductivity type at a same second atomic concentration. In one embodiment, the first and second atomic concentrations can be substantially the same, and may differ only by the differences in the lattice constants and stopping power for implanted ions between silicon atoms and germanium atoms. In one embodiment, the thickness of the base cap59can be selected that the dopants of the second conductivity type are stopped within the base cap59during the ion implantation, and do not penetrate into the extrinsic base region58.

If the ion implantation is performed along a surface normal of the silicon passivation layer54L, the lateral offset of the boundary between the germanium base region52B and the germanium emitter region52E from the extrinsic base region58can be the same as the lateral offset of the boundary between the germanium base region52B and the germanium collector region52C from the extrinsic base region58. In one embodiment, if the base cap59has the same stopping power as, or a greater stopping power than, the vertical stack of the doped silicon passivation layer (54E,54B,54C) and the doped germanium layer (52E,52B,52C) for ion implantation of dopants of the second conductivity type, the energy of the ion implantation can be selected that dopants of the second conductivity type reaches the bottommost region of the germanium emitter region52E and the germanium collector region52C, while not penetrating into the extrinsic base region58.

The bottom surface of the dielectric spacer70is in contact with a peripheral portion of the top surface of the silicon emitter region54E, a peripheral portion of the top surface of the silicon collector region54C, and two disjoined peripheral portions of the top surface of the silicon base region54B. The buried insulator layer20has a planar top surface that contacts the germanium base region52B, the germanium emitter region52E, and the germanium collector region52C.

In one embodiment, the interface between the germanium emitter region52E and the germanium base region52B can be substantially vertically coincident with the interface between the silicon emitter region54E and the silicon base region54B after the ion implantation. Further, the interface between the germanium collector region52C and the germanium base region52B can be substantially vertically coincident with the interface between the silicon collector region54C and the silicon base region54B after the ion implantation.

In one embodiment, the entirety of the germanium layer (52E,52B,52C) can have the first thickness throughout, and the entirety of the silicon passivation layer (54E,54B,54C) can have the second thickness throughout. As discussed above, the first thickness can be at least twice the second thickness. The ratio of the first thickness to the second thickness can be kept such that the germanium bipolar junction transistor including the germanium emitter region52E, the germanium base region52B, and the germanium collector region52C dominates the device characteristics of the bipolar junction transistor including the germanium bipolar junction transistor and a parasitic bipolar junction transistor including the silicon emitter region54E, the silicon base region54B, and the silicon collector region54C.

The exemplary semiconductor structure thus includes a bipolar junction transistor (BJT), which includes a doped germanium layer (52E,52B,52C) in contact with an insulator layer (i.e., the buried insulator layer20) and including the germanium base region52B, the germanium emitter region52E, and the germanium collector region52C. The germanium base region52B includes dopants of the first conductivity type. The germanium emitter region52E is in contact with the germanium base region52B and includes dopants of a second conductivity type that is the opposite type of the first conductivity type. The germanium collector region52C is in contact with the germanium base region52B and includes dopants of the second conductivity type. The BJT includes the silicon passivation layer (54E,54B,54C) that is in contact with the doped germanium layer (52E,52B,52C). The silicon passivation layer (54E,54B,54C) includes a silicon base region54B, a silicon emitter region54E, and a silicon collector region54C. The silicon emitter region54E is in contact with the silicon base region54B. The silicon collector region54C is in contact with the silicon base region54B. The silicon base region54B includes dopants of the first conductivity type and contacts the germanium base region52B. The silicon emitter region54E includes dopants of the second conductivity type and contacts the germanium emitter region52E. The silicon collector region54C includes dopants of the second conductivity type and contacts the germanium collector region52C. The extrinsic base region58is in contact with the silicon base region54B.

The silicon passivation layer (54E,54B,54C) can be polycrystalline. The top surfaces of the germanium base region52B, the germanium emitter region52E, and the germanium collector region52C are coplanar among one another. In one embodiment, the top surfaces of the silicon base region54B, the silicon emitter region54E, and the silicon collector region54C are coplanar among one another. The bottom surface of the dielectric spacer70is in contact with the top surfaces of the silicon base region54B, the silicon emitter region54E, and the silicon collector region54C.

Referring toFIG. 6, a semiconductor material can be optionally selectively deposited on the semiconductor surfaces of the silicon emitter region54E and the silicon collector region54C, while not growing from dielectric surfaces of the exemplary structure. The semiconductor material can be any polycrystalline semiconductor material known in the art. In one embodiment, the semiconductor material can be polycrystalline silicon.

The semiconductor material can be deposited employing a selective deposition process, in which the semiconductor material grows from semiconductor surfaces and does not grow from dielectric surfaces. An emitter contact region60E having a doping of the second conductivity type is formed on the silicon emitter region54E and an outer sidewall of the dielectric spacer70. A collector contact region60C having a doping of the second conductivity type is formed on the silicon collector region54C and another outer sidewall of the dielectric spacer70. The semiconductor material that grows on, and from, the silicon emitter region54E constitutes the emitter contact region60E, and the semiconductor material that grows on, and from, the silicon collector region54C constitutes the collector contact region60C. In other words, the semiconductor material is selectively deposited on the physically exposed surface of the silicon emitter region54E and the physically exposed surface of the silicon collector region54C, while the semiconductor material does not grow from surfaces of the dielectric spacer70, the base cap59, or the shallow trench isolation structure32.

As the emitter contact region60E grows with continued deposition of the semiconductor material during the selective deposition process, the emitter contact region60E comes into contact with a lower portion of an outer sidewall of the dielectric spacer70and a peripheral top surface of the shallow trench isolation structure32. Likewise, as the collector contact region60C grows with continued deposition of the semiconductor material during the selective deposition process, the collector contact region60C comes into contact with a lower portion of another outer sidewall of the dielectric spacer70and another peripheral top surface of the shallow trench isolation structure32. The thickness of the emitter contact region60E and the collector contact region60C is less than the height of the dielectric spacer70, and can be from 1 nm to 1,000 nm, although lesser and greater thicknesses can also be employed.

During the selective deposition process, at least one semiconductor precursor gas and at least one etchant gas are flowed into a process chamber to deposit the semiconductor material on physically exposed semiconductor surfaces of the silicon emitter region54E and the silicon collector region54C. The at least one semiconductor precursor gas and the at least one etchant gas can be any combination that enable selective deposition of the semiconductor material as known in the art. Non-limiting examples of the at least one semiconductor precursor gas include SiH4, SiH2Cl2, SiHCl3, SiCl4, Si2H6, GeH4, Ge2H6, and other precursor gases for depositing the selected semiconductor material. Non-limiting examples of the at least one etchant gas include HCl.

In one embodiment, the emitter contact region60E and the collector contact region60C can be doped in-situ during the selective deposition of the semiconductor material. Formation of the emitter contact region60E and the collector contact region60C with in-situ doping can be effected by flowing a dopant gas including a dopant atom of the second conductivity type concurrently with, or alternately with, the at least one semiconductor precursor gas and the at least one etchant gas. If the second conductivity type is n-type, the dopant gas can be, for example, PH3, AsH3, SbH3, or a combination thereof. If the second conductivity type is p-type, the dopant gas can be, for example, B2H6. In this case, the emitter contact region60E and the collector contact region60C can be formed as doped polycrystalline semiconductor regions having a doping of the second conductivity type.

In another embodiment, the emitter contact region60E and the collector contact region60C can be deposited as intrinsic semiconductor material portions by selective deposition of an intrinsic semiconductor material, and can be subsequently doped by implanting dopants of the second conductivity type. Upon implantation of the dopants of the second conductivity type, the emitter contact region60E has a doping of the second conductivity type and contacts the silicon emitter region54E, and the collector contact region60C has a doping of the second conductivity type and contacts the silicon collector region54C.

The emitter contact region60E and the collector contact region60C can have a concentration of dopants of the second conductivity type, for example, from 1.0×1019/cm3to 3.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. In one embodiment, the concentration of dopants of the second conductivity type in the emitter contact region60E and the collector contact region60C can be greater than the net dopant concentration of dopants of the second conductivity type in the silicon emitter region54E and the silicon collector region54C.

In one embodiment, the semiconductor material in the emitter contact region60E and the collector contact region60C can have a smaller band gap than silicon. For example, the semiconductor material in the emitter contact region60E and the collector contact region60C can be a silicon germanium alloy or germanium. In this case, the contact resistance of the emitter contact region60E and the collector contact region60C can be reduced relative to a structure in which the emitter contact region60E and the collector contact region60C include silicon.

The semiconductor material deposited in the emitter contact region60E is polycrystalline because the silicon emitter region54E is polycrystalline, and the semiconductor material deposited in the collector contact region60C is polycrystalline because the silicon collector region54C is polycrystalline.

The dielectric spacer70is in contact with the silicon base region54B, the silicon emitter region54E that laterally contacts the silicon base region54B, the emitter contact region60E, the silicon collector region54C that contacts the silicon base region54B, and the collector contact region60C. The bottom surfaces of the emitter contact region60E and the collector contact region60C can be coplanar with the bottom surface of the extrinsic base region58. The emitter contact region60E is vertically spaced from the doped germanium layer (52E,52B,52C) by the silicon emitter region54E, and the collector contact region60C is vertically spaced from the doped germanium layer (52E,52B,52C) by the silicon collector region54C.

Referring toFIG. 7, the base cap59can be removed, for example, by a wet etch. The chemistry of the wet etch can be selected such that the base cap59can be etched without etching the semiconductor materials of the emitter contact region60E, the collector contact region60C, and the extrinsic base region58or the dielectric materials of the shallow trench isolation structure32and the dielectric spacer70. For example, if the base cap59includes silicon nitride, and the shallow trench isolation structure32and the dielectric spacer70include silicon oxide, a wet etch employing hot phosphoric acid can be employed to remove the base cap59selective to the semiconductor materials of the emitter contact region60E, the collector contact region60C, and the extrinsic base region58or the dielectric materials of the shallow trench isolation structure32and the dielectric spacer70.

A contact-level dielectric layer80can be deposited over the extrinsic base cap58, the dielectric spacer70, the emitter contact region60E, the collector contact region60C, and the shallow trench isolation structure32. The contact-level dielectric layer80can include undoped silicate glass (i.e., silicon oxide), doped silicate glass, organosilicate glass, or any other dielectric material known in the art that can be employed for forming interconnect structures. The contact-level dielectric layer80can be formed, for example, by chemical vapor deposition (CVD) and/or spin-coating. The top surface of the contact-level dielectric layer80can be planarized, for example, by chemical mechanical planarization (CMP).

Various contact via structures can be formed through the contact-level dielectric layer80to provide electrical contact to the germanium emitter region52E, the germanium collector region52C, and the germanium base region52B through the stack of the silicon emitter region54E and the emitter contact region60E, through the stack of the silicon base region54B and the extrinsic base region58, and through the stack of the silicon collector region54C and the collector contact region60C, respectively. The various contact via structures can include for example, an emitter contact via structure84electrically connected to the emitter contact region60E, a collector contact structure86electrically connected to the collector contact region60C, and a base contact structure85electrically connected to the extrinsic base region58. The various contact structures (84,85,86) can be formed, for example, by forming via trenches and filling the via trenches with at least one conductive material. The excess conductive material above the top surface of the contact-level dielectric layer80can be removed, for example, by chemical mechanical planarization.

Optionally, an emitter metal semiconductor alloy region74, a collector metal semiconductor alloy region76, and a base metal semiconductor alloy region75can be formed at the bottom of the via trenches by reacting a metal with physically exposed portions of the emitter contact region60E, the collector contact region60C, and the extrinsic base region58, respectively.

Referring toFIG. 8, a variation of the exemplary structure can be derived from the exemplary structure ofFIG. 5by omitting formation of the emitter contact region60E (SeeFIG. 6) and the collector contact region60C. An emitter metal semiconductor alloy region74, a collector metal semiconductor alloy region76, and a base metal semiconductor alloy region72can be formed at the bottom of the via trenches by reacting a metal with physically exposed portions of the silicon emitter region54E, the silicon collector region54C, and the extrinsic base region58, respectively. In this case, the second thickness of the silicon passivation layer (54E,54B,54C) can be selected so as to prevent a physical contact between the emitter metal semiconductor alloy region74and the germanium emitter region52E or between the collector metal semiconductor alloy region76and the germanium collector region52C. For example, the second thickness can be greater than 15 nm.

Alternatively, the metal semiconductor alloy regions on the emitter contact region60E, the collector contact region60C, and the extrinsic base region58can be formed prior to deposition of the contact-level dielectric layer80. This can be accomplished by depositing a metal on the semiconductor in the emitter contact region60E, the collector contact region60C, and the extrinsic base region58, and subsequently reacting the metal with the respective underlying semiconductor material to form the various metal semiconductor alloy regions that extend across the entire upper and outer surfaces of the emitter contact region60E, the collector contact region60C, and the extrinsic base region58. The unreacted metal portions are then selectively etched away, for example, by a wet etch.

The silicon passivation layer (54E,54B,54C) of the present disclosure prevents physical exposure of the germanium layer52L prior to ion implantation of dopants of the second conductivity type, and physical exposure of the doped germanium layer (52E,52B,52C) after ion implantation of dopants of the second conductivity type. The silicon passivation layer (54E,54B,54C) is polycrystalline, and therefore, does not induce any strain on the doped germanium layer (54E,54B,54C).

The structure of the present disclosure includes a parasitic lateral bipolar junction transistor within the passivation silicon layer (54E,54B,54C). Since the bandgap of germanium is only 0.66 eV and the band gap of polysilicon is about 1.12 eV, the bipolar junction transistor including the doped germanium layer (52E,52B,52C) provides an electrical current many orders of magnitude larger than any electrical current from the parasitic lateral bipolar junction transistor within the passivation silicon layer (54E,54B,54C).

Further, the silicon emitter region54E on the germanium emitter region52E provides a wide band gap contact to the germanium emitter region52E, i.e., an electrical contact to the germanium emitter region52E provided by a semiconductor material having a greater band gap than the band gap of the germanium emitter region52E. The wide band gap contact to the germanium emitter region52E suppresses minority carrier current through the silicon emitter region54E, and thus, increases the gain of the bipolar junction transistor including the doped germanium layer (52E,52B,52C).

In addition, the silicon base region54B on the germanium base region52B provides a wide band gap contact to the germanium base region52B, i.e., an electrical contact to the germanium base region52B provided by a semiconductor material having a greater band gap than the band gap of the germanium base region52B. The wide band gap contact to the germanium base region52B suppresses minority carrier current through the silicon base region54B, and thus, increases the gain of the bipolar junction transistor including the doped germanium layer (52E,52B,52C).