Graphene transistor having tunable barrier

Provided are graphene transistors having a tunable barrier. The graphene transistor includes a semiconductor substrate, an insulating thin film disposed on the semiconductor substrate, a graphene layer on the insulating thin film, a first electrode connected to an end of the graphene layer, a second electrode that is separate from an other end of the graphene layer and contacts the semiconductor substrate, a gate insulating layer covering the graphene layer, and a gate electrode on the gate insulating layer, wherein an energy barrier is formed between the semiconductor substrate and the graphene layer.

RELATED APPLICATIONS

This application claims priority from Korean Patent Application No. 10-2014-0010721, filed on Jan. 28, 2014, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

Example embodiments relate to transistors having a tunable semiconductor barrier in which an insulating film is interposed between a graphene layer and a semiconductor.

2. Description of the Related Art

Graphene having a 2-dimensional hexagonal carbon structure is a new material that can replace semiconductor, and studies have been actively conducted on graphene. In particular, graphene is a zero gap semiconductor, and when a graphene nanoribbon (GNR) has a channel width of 10 nm or less, a band gap is formed due to a size effect, and thus, a field effect transistor that can be operated at room temperature can be manufactured.

Recently, a graphene transistor that uses a Schottky barrier that is generated by a junction of graphene and a semiconductor.

However, a graphene transistor typically has a low ON-current and a low OFF-current due to Fermi level pinning that is generated at the junction of the graphene and the semiconductor. Accordingly, an operation voltage of the graphene transistor may increase.

SUMMARY

Example embodiments relate to graphene transistors having a tunable barrier, that is, an insulating thin film is disposed between a graphene layer and a semiconductor.

According to at least one example embodiment, a graphene transistor having a tunable barrier includes a semiconductor substrate, an insulating thin film disposed on the semiconductor substrate, a graphene layer on the insulating thin film, a first electrode connected to an end of the graphene layer, a second electrode that is separated from an other end of the graphene layer and contacts the semiconductor substrate, a gate insulating layer covering the graphene layer, and a gate electrode on the gate insulating layer, wherein an energy barrier is formed between the semiconductor substrate and the graphene layer.

The insulating thin film may have a thickness in a range of about 1 nm to about 4 nm.

The insulating thin film may include at least one of Al2O3, HfO2, TiO2, and Si3N4.

The semiconductor substrate may include one of silicon, germanium, silicon-germanium, a group III-V semiconductor, and a group II-VI semiconductor.

A gap between the graphene layer and the second electrode may be in a range of about 1 nm to about 30 nm.

The graphene transistor may further include an insulating layer between the graphene layer and the insulating thin film at a location corresponding to the first electrode.

The graphene transistor may be a unipolar transistor having a same polarity as the polarity of an impurity of the semiconductor substrate.

The energy barrier may vary according to a gate voltage applied to the gate electrode.

The graphene layer may include between 1 layer and 4 layers of graphene.

According to another example embodiment, a graphene transistor having a tunable barrier includes a back gate substrate, a gate insulating layer on the back gate substrate, a graphene layer on the gate insulating layer, a first electrode formed on a first region of the graphene layer, and a semiconductor layer, an insulating thin film, a second electrode sequentially stacked on a second region of the graphene layer in this order, the second region of the graphene layer being separated from the first region of the graphene layer, and wherein an energy barrier is formed between the semiconductor layer and the graphene layer.

DETAILED DESCRIPTION

Hereinafter, example embodiments will be described more fully with reference to the accompanying drawings. In the drawings, thicknesses of layers and regions may be exaggerated for clarity of the specification. Also, like reference numerals are used for elements that are substantially identical to each other throughout the specification, and the descriptions thereof will not be repeated.

It will be understood that when an element is referred to as being “on,” “connected” or “coupled” to another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under or one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

FIG. 1is a schematic cross-sectional view of a graphene transistor100having a tunable barrier according to example embodiments.

Referring toFIG. 1, an insulating thin film120is formed on a substrate110. An insulating layer130is formed on a region of the insulating thin film120. A graphene layer140is formed on the insulating layer130. The graphene layer140extends onto the insulating thin film120to directly contact the insulating thin film120. A first electrode151is formed on the graphene layer140to face the insulating layer130. The first electrode151is connected to an end of the graphene layer. A second electrode152is disposed on the substrate110and is separate from the first electrode151. The second electrode152may contact the substrate110. The second electrode152is also separate from an other end of the graphene layer140. A distance d between the graphene layer140and the second electrode152may be in a range of about 1 nm to about 30 nm. A gate insulating layer160is formed on the substrate110and covers at least a portion of the graphene layer140. A gate electrode170is formed on the gate insulating layer160.

The substrate110may be a semiconductor substrate. The semiconductor substrate110may be formed of, or include, silicon, germanium, silicon-germanium, a group III-V semiconductor, or a group II-VI semiconductor. The semiconductor substrate110may be doped with one of an n-type impurity and a p-type impurity. The semiconductor substrate110may face the gate electrode170with the graphene layer140therebetween.

The insulating thin film120may be formed of a material having a band gap that is smaller than the band gap of silicon oxide. For example, the insulating thin film120may be formed of, or include, Al2O3, HfO2, TiO2, or Si3N4. The insulating thin film120may be formed via, for example, a chemical vapor deposition (CVD) method, a thermal evaporation method, an e-beam evaporation method, an atomic layer deposition (ALD) method, or a sputtering method. The insulating thin film120may have a thickness in a range from about 1 nm to about 4 nm. When the thickness of the insulating thin film120is smaller than 1 nm, holes may be formed in the insulating thin film120, and at this point, the graphene layer140may directly contact the semiconductor substrate110.

When the thickness of the insulating thin film120is greater than 4 nm, a tunneling resistance of the insulating thin film120is increased, and accordingly, a current that passes through the insulating thin film120may be reduced, which will be described below.

According to at least one example embodiment, the insulating layer130prevents the first electrode151, and the graphene layer140under the first electrode151, from contacting the semiconductor substrate110. The insulating layer130minimizes an effect of a drain voltage on the semiconductor substrate110. The insulating layer130may be optionally omitted. The insulating layer130may be formed of the same material used to form the insulating thin film120, or may be formed of silicon oxide or silicon nitride.

The graphene layer140may be formed by transferring and patterning graphene after the graphene is formed by using a CVD method. The graphene layer140may include a single layer through 4 layers of graphene. The graphene layer140is a pathway for moving carriers, and may have a zero band gap.

The first electrode151may be one of a source electrode or a drain electrode and the second electrode152may be another of the source electrode or the drain electrode, and may be formed of metal or polysilicon.

The gate insulating layer160may be formed of, or include, silicon oxide or silicon nitride.

The graphene transistor100having a tunable barrier may be a unipolar transistor, that is, the transistor100may be an n-type transistor or a p-type transistor according to the polarity of the semiconductor substrate110which is a semiconductor barrier. That is, when the semiconductor substrate110is doped with an n-type impurity, the graphene transistor100having a tunable barrier is an n-type transistor, and when the semiconductor substrate110is doped with a p-type impurity, the graphene transistor100having a tunable barrier is a p-type transistor.

FIG. 2is an energy band diagram of an n-type graphene transistor without an insulating thin film120of the structure ofFIG. 1. Like numerals are used to indicate elements that are substantially identical to elements ofFIG. 1.

Referring toFIG. 2, in a state when a gate voltage is not applied to the gate electrode170, an energy band structure is formed corresponding to respective work functions of the semiconductor substrate110and the graphene layer140. Since the graphene transistor100includes the n-type semiconductor substrate110, the main carriers are electrons. An energy barrier Eb1is formed between the graphene layer140and the semiconductor substrate110, and the moving of the carriers is restricted by the energy barrier Eb1. The energy barrier Eb1is relatively large due to a Fermi level pinning phenomenon due to graphene, and accordingly, a driving current of the graphene switching device is reduced.

FIGS. 3A and 3Bare energy band diagrams for explaining an operation of the n-type graphene transistor100of the example embodiment illustrated inFIG. 1.

FIG. 3Ashows a band diagram prior to applying a drain voltage and a gate voltage. Due to the insulating thin film120in the graphene transistor100, the Fermi level pinning of the graphene layer140does not occur or is substantially reduced. Accordingly, the Fermi level of the graphene layer140has an energy barrier Eb2that is relatively lower than the Fermi level of the energy barrier Eb1inFIG. 2.

Referring toFIG. 3B, in a state where a predetermined, or alternatively desired positive drain voltage is applied between the first electrode151and the second electrode152, when a predetermined, or alternatively desired positive gate voltage +Vg is applied to the gate electrode170, the Fermi level of the graphene layer140becomes higher in a direction indicated by an arrow A, and as a result an energy barrier Eb3is further lowered. Accordingly, electrons can move toward the semiconductor substrate110by tunneling through the insulating thin film120. This denotes that a current flows in the graphene transistor100by application of the gate voltage +Vg, and accordingly, the graphene transistor100performs as a field effect transistor. The graphene layer140is a pathway of carriers, and is distinguished from a channel of a conventional field effect transistor.

A driving current is increased due to the insulating thin film120, and accordingly, the driving voltage of the graphene transistor100is reduced.

As the gate voltage +Vg increases, the energy barrier Eb3of the semiconductor substrate110is further lowered. Accordingly, the energy barrier of the graphene transistor100may be tunable. Also, the graphene transistor100is referred to as a graphene transistor having a tunable barrier.

When a negative drain voltage is applied between the first electrode151and the second electrode152, a drain current is increased as the Fermi level of the semiconductor substrate110becomes high, and when a positive drain voltage is applied between the first electrode151and the second electrode152, the drain current is lowered by lowering the Fermi level of the semiconductor substrate110. Accordingly, the graphene transistor100may have a diode characteristic.

FIG. 4is an energy band diagram of a p-type graphene transistor without an insulating thin film. Like numerals are used to indicate elements that are substantially identical to elements ofFIG. 1.

Referring toFIG. 4, in a state when a gate voltage is not applied to the gate electrode170, an energy band structure corresponding to each work function of the semiconductor substrate110and the graphene layer140is formed. The graphene transistor includes a p-type semiconductor substrate110, thus, the main carriers are holes. An energy barrier Eb1is formed between the graphene layer140and the semiconductor substrate110. Movement of the carriers is restricted by the energy barrier Eb1. The energy barrier Eb1is relatively large due to a Fermi level pinning phenomenon, and accordingly, a driving current of a graphene switching device is reduced.

FIGS. 5A and 5Bare energy band diagrams for explaining an operation of the p-type graphene transistor100of the example embodiment illustrated inFIG. 1.

FIG. 5Ashows a band diagram prior to applying a drain voltage and a gate voltage. Due to the insulating thin film120, the Fermi level pinning phenomenon does not occur. Accordingly, the graphene transistor100has a relatively low energy barrier Eb2.

Referring toFIG. 5B, in a state when a predetermined, or alternatively desired negative drain voltage is applied between the first electrode151and the second electrode152, when a predetermined, or alternatively desired negative gate voltage −Vg is applied to the gate electrode170, the Fermi level of the graphene layer140is lowered in a direction as indicated by arrow B and the energy barrier Eb3is further lowered, and thus, holes can move towards the semiconductor substrate110by tunneling through the insulating thin film120. This denotes that a current flows in the graphene transistor100by the gate voltage, and accordingly, the graphene transistor100operates as a field effect transistor. The graphene layer140is a pathway of the carriers, and is distinguished from a channel of a conventional field effect transistor.

Also, a driving current is increased due to the insulating thin film120, and accordingly, the driving voltage of the graphene transistor100is reduced.

As the gate voltage increases, the energy barrier Eb3of the semiconductor substrate110is further reduced. Accordingly, the energy barrier Eb3of the graphene transistor100may be tunable.

When a negative drain voltage is applied, a drain current is lowered while the Fermi level of the semiconductor substrate110becomes high. When a positive drain voltage is applied, the drain current increases while the Fermi level of the semiconductor substrate110is lowered. Accordingly, the graphene transistor100may have a diode characteristic.

FIG. 6is a schematic cross-sectional view of a graphene transistor200having a tunable barrier according to example embodiments.

Referring toFIG. 6, a gate insulating layer220is formed on a substrate210. A graphene layer230is formed on the gate insulating layer220. An insulating thin film240, a semiconductor layer250, and a first electrode261are sequentially formed on a first region231of the graphene layer230. A second electrode262is formed on a second region232of the graphene layer230, the second electrode262being separate from the first region231of the graphene layer230.

The first electrode261is one of a source electrode and a drain electrode, and the second electrode262is another of the source electrode and the drain electrode. The first electrode261and the second electrode262may be formed of, or include, metal or polysilicon.

The substrate210is configured to operate as a back gate, and may be formed of a semiconductor doped with an impurity or a metal.

The gate insulating layer220may be formed of, or include, silicon oxide or silicon nitride.

The graphene layer230may be formed by patterning graphene after transferring the graphene manufactured by using, for example, a CVD method. The graphene layer230may include 1 layer through 4 layers of graphene. The graphene layer230may be a pathway of carriers and may have a zero band gap.

The insulating thin film240may be formed of a material having a band gap smaller than the band gap of silicon oxide. For example, the insulating thin film may be formed of, or include, Al2O3, HfO2, TiO2, Si3N4, and the like. The insulating thin film240may be formed by using a CVD method, an e-beam evaporator, an ALD method, or a sputtering method. The insulating thin film240may have a thickness in a range of about 1 nm to about 4 nm. When the insulating thin film240has a thickness smaller than 1 nm, holes may be formed in the insulating thin film240, and thus, the graphene layer230may directly contact the semiconductor layer250.

When the insulating thin film240has a thickness greater than 4 nm, a tunneling resistance of the insulating thin film240may be increased, and accordingly, a current tunneling through the insulating thin film240may be reduced.

The semiconductor layer250may be formed of, or include, silicon, germanium, silicon-germanium, a group III-V semiconductor, or a group II-VI semiconductor. The semiconductor layer250may have a thickness through which tunneling of carriers is possible. The thickness of the semiconductor layer250may vary according to materials of the semiconductor layer250, and may have a thickness in a range of about 1 nm to about 10 nm. The semiconductor layer250is doped with one of an n-type impurity or a p-type impurity.

The graphene transistor200having a tunable barrier may be a unipolar transistor, that is, may be an n-type transistor or a p-type transistor according to the polarity of the semiconductor layer250. Accordingly, when the semiconductor layer250is doped with an n-type impurity, the graphene transistor200having a tunable barrier is an n-type transistor, and when the semiconductor layer250is doped with a p-type impurity, the graphene transistor200having a tunable barrier is a p-type transistor.

Operation of the graphene transistor200having a tunable barrier may be well understood from the operation of the graphene transistor100, and thus, a detailed description thereof will be omitted.

As described above, according to example embodiments, a graphene transistor having a tunable barrier prevents or reduces a pinning phenomenon of graphene by disposing an insulating thin film between a graphene and a semiconductor, and thus, a height of an energy barrier between the graphene and the semiconductor is reduced. Thus, a driving voltage of the graphene transistor can be reduced.