Driving circuit slew rate compensation method

An apparatus for compensating slew rate of a driving circuit includes: a first circuit, for receiving an edge transition from the driving circuit and generating a first pulse proportional to an actual slope of the edge transition; a second circuit, for receiving an ideal edge transition of the driving circuit and generating a second pulse proportional to an ideal slope of the ideal edge transition; a comparison circuit, coupled to the first circuit and the second circuit, for comparing an extreme value of amplitude of the first pulse with an extreme value of amplitude of the second pulse to produce a comparison signal; and a control circuit, coupled to the comparison circuit, for increasing or decreasing the slew rate of the driving circuit according to the comparison signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to driver circuits, and more particularly, to a method and system for compensating the slew rate of a driver circuit.

2. Description of the Prior Art

The invention of Integrated circuits (ICs) had a significant impact on the field of electrical engineering. Incorporating all circuits into a single chip has enabled miniscule devices such as the modern laptop computer and cell phones to be developed. Many ICs comprise off-chip driver circuits (OCDs) utilized for driving logic levels related to supply voltages for the IC off-chip. The OCD also functions as a protection against high voltages. A problem associated with off-chip drivers, however, is that the output slew rate has a wide variation caused by tolerances in process, voltage, temperature and output load.

In order to combat this problem, circuits for controlling an output slew rate have been developed. These systems aim to control the slew rate by enabling or disabling pre-driver devices. For example, certain control pins can be enabled or disabled so the gates of the output stage become correspondingly faster or slower. For a faster transition all pre-drivers must be turned on, whereas for a slower transition only one pre-driver needs to be turned on. Enable signals for pre-drivers are utilized to enable the pre-drivers. Calibration must be manual, however, as it is not known how many pre-drivers initially need to be enabled. This method is costly to implement, and a user will have to use a trial and error approach when determining certain parameters to configure the pre-driver circuit.

In order to provide a more automated approach to the slew rate control, other systems were developed. Please refer toFIG. 1.FIG. 1is a diagram of a system100for controlling slew rate variation of an off-chip driver160. As can be seen from the diagram, the system100comprises a delay locked loop (DLL)110consisting of a series of delay elements112, a frequency divider (not shown) and a phase comparator (not shown). The output of the DLL110is coupled to a first XOR gate120, which generates an ideal slew pulse. A rising (or falling) edge of the off-chip driver circuit160is input to a first comparator152and a second comparator154where the first comparator152switches at a high point and the second comparator154switches at a low point. The outputs of the first and second comparators152,154are coupled to a second XOR gate140, which generates a pulse that is proportional to an actual rise (or fall) time of the off-chip driver160. The pulse from the first XOR gate120and the pulse from the second XOR gate140are then fed into a phase comparator130which generates a signal that determines whether or not to increase the strength of the pre-driver165in the off-chip driver160.

Although this method is effective, the system100requires many elements, and the DLL110must also be set at the start of a slew rate compensation operation.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide a method and apparatus for slew rate compensation of an off-chip driver that simplifies the conventional art.

With this in mind, an apparatus for compensating slew rate of a driving circuit is provided. The apparatus comprises: a first circuit, for receiving an edge transition from the driving circuit and generating a first pulse proportional to an actual slope of the edge transition; a second circuit, for receiving an ideal edge transition of the driving circuit and generating a second pulse proportional to an ideal slope of the ideal edge transition; a comparison circuit, coupled to the first circuit and the second circuit, for comparing a peak magnitude value of amplitude of the first pulse with a peak magnitude value of amplitude of the second pulse to produce a comparison signal; and a control circuit, coupled to the comparison circuit, for increasing or decreasing the slew rate of the driving circuit according to the comparison signal.

A method for controlling slew rate of a driving circuit is also disclosed. The method comprises: utilizing an edge transition time of a driving circuit to generate a first pulse proportional to a slope of the edge transition; capturing a peak magnitude value of amplitude of the first pulse; utilizing an ideal edge transition time to generate a second pulse proportional to a slope of the ideal edge transition; capturing a peak magnitude of amplitude of the second pulse; comparing the peak magnitude value of amplitude of the first pulse with the peak magnitude value of amplitude of the second pulse; and utilizing the comparison result to increase or decrease the slew rate of the driving circuit.

DETAILED DESCRIPTION

Please refer toFIG. 2.FIG. 2is a diagram of an apparatus200according to an exemplary embodiment of the present invention. The apparatus comprises a first circuit220comprising an RC filter222, a maximum voltage rectifier224and a minimum voltage rectifier226. The input of the first circuit220is an edge transition from the off-chip driver. The apparatus200further comprises a second circuit230comprising an RC filter232, a maximum voltage rectifier234and a minimum voltage rectifier236. The input of the second circuit230is an ideal edge transition, which can be generated off-chip. The edge transition and ideal edge transition can be rising edges or falling edges.

The first circuit220and second circuit230are coupled to a comparison circuit240. The comparison circuit240comprises a first comparator242and a second comparator244. Specifically, the outputs of the minimum voltage rectifiers226,236are coupled to the first comparison circuit242and the outputs of the maximum voltage rectifiers224,234are coupled to the second comparator244. The comparison circuit240is coupled to a bitstate counter250. The bitstate counter250comprises a falling edge counter252and a rising edge counter254. Specifically, the output of the first comparator242is coupled to the falling edge counter252and the output of the second comparator244is coupled to the rising edge counter254.

As mentioned above, the edge transition and ideal edge transition can be falling or rising edges. In the following description, an operation of the apparatus200when rising edge transitions are utilized will be described. Please note that the operation of the system is substantially the same for falling edge transitions except that the minimum voltage rectifiers226,236and the falling edge counter252will be utilized.

A rise transition from the off-chip driver arrives at the first circuit220. At the same time, an ideal rising edge transition arrives at the second circuit230. The RC filter222will generate a rising pulse, where the magnitude of the pulse is proportional to a slope of the rising edge. The maximum voltage rectifier224then captures a maximum magnitude of the rising pulse. As mentioned above, when the pulse is a falling pulse, the minimum voltage rectifier226will be utilized, and will capture a minimum magnitude of the falling pulse. The RC filter232of the second circuit230generates a rising pulse according to the ideal rising edge transition. The maximum voltage rectifier234then captures a maximum magnitude of the ideal rising pulse.

The maximum magnitude of the rising pulse and the maximum magnitude of the ideal rising pulse are then input to the comparison circuit240, into the second comparator244. The comparison circuit240operates to determine if an output stage transition of the off-chip driver needs to be faster or slower in order to match the ideal rising edge transition. The second comparator244compares the two values and then outputs a comparison result, which will be input to the bitstate counter250; specifically, the rising edge counter254.

The rising edge counter254utilizes the comparison result to selectively increment or decrement. If the ideal rising edge transition is faster than the rising edge transition from the off-chip driver, then the output stage transition can be pushed to go faster. In this case, the rising edge counter254will increment. In general, the bitstate counter250is digital so it will increment (or decrement) by one bit at a time. Please note that this is not a limitation of the invention, and that the bitstate counter can also be implemented by an analog counter.

The above stages will be repeatedly performed until the rising edge transition from the off-chip driver and the ideal rising edge transition match. The comparison of the two values, and the generation of bus signals according to the comparison step push the pre-drive of the off-chip driver in a direction to control the output slew rate.

Please refer toFIG. 3.FIG. 3is a flowchart showing an operation of the apparatus200shown inFIG. 2. The steps are as follows:

Step300: Utilize an edge transition of the off-chip driver to generate a first pulse proportional to a slope of the edge transition;

Step302: Capture an extreme value of amplitude of the first pulse;

Step304: Utilize an ideal edge transition to generate a second pulse proportional to a slope of the ideal edge transition;

Step306: Capture an extreme value of amplitude of the second pulse;

Step308: Compare the amplitudes of the first pulse and the second pulse;

Step310: Utilize the comparison result to increment or decrement a bitstate counter in order to push the pre-driver circuit of the off-chip driver in a direction to minimize the amplitude difference.

An edge transition from an off-chip driver is input to the RC filter222to generate a first pulse (Step300). The first pulse is then input to the maximum voltage rectifier224or minimum voltage rectifier226to capture an extreme value of amplitude of the first pulse (Step302). An ideal edge transition is input to the RC filter232to generate a second pulse (Step304) and then input to the maximum voltage rectifier234or minimum voltage rectifier236to capture an extreme value of amplitude of the second pulse (Step306). The extreme value of amplitude of the first pulse and the extreme value of amplitude of the second pulse are input to the comparison circuit240(the first comparator242when edge transitions are falling edge transitions, and the second comparator244when edge transitions are rising edge transitions) and the amplitudes are compared (Step308). Finally, the comparison result is input to the bitstate counter250, and the falling edge counter252or rising edge counter254is selectively incremented or decremented according to the comparison signal in order to push the pre-driver circuit of the off-chip driver in a direction to minimize the amplitude difference (Step310).

By utilizing an ideal edge transition and comparing the ideal edge transition with an actual edge transition from an off-chip driver, the apparatus200can function as a calibration circuit, by utilizing the bitstate counter250to produce digital bus signals that can be utilized for a plurality of off-chip drivers for an IC.