ELECTRONIC DEVICE WITH AUTO ALIGNED CSL AND EDGE TERMINATION STRUCTURE, AND MANUFACTURING METHOD THEREOF

Method of manufacturing an electronic device, comprising the steps of: arranging a semiconductor body of N-type, having a lattice structure with spatial symmetry, comprising an active area an edge region surrounding the active area; forming, in the edge region, an intentionally damaged region wherein the lattice structure has no spatial symmetry; forming an edge termination region of P-type at the damaged region, by random implant; forming a current spreading layer, CSL, in the edge region at and lateral to the damaged region, by channeled implant. The CSL has, at the damaged region, a minimum thickness and, laterally to the damaged region, a maximum thickness. The minimum thickness is lower than the thickness of the edge termination region.

BACKGROUND

Technical Field

The disclosure relates to an electronic device and a manufacturing method thereof, in particular an electronic device with a current spreading layer (CSL) with variable thickness.

Description of the Related Art

Ion implant is nowadays a well-established technique for introducing dopants into Silicon Carbide, SiC, since dopant spreading is not an applicable technique due to the low diffusivity of SiC compared to other semiconductor materials (such as, for example, Silicon), and epitaxial growth might not be a useful alternative, particularly for locally confined volumes.

As known, the crystalline structure of SiC affects, during implant, the depth distribution obtained. In fact, the so-called channeling may considerably increase the penetration depth of the ions into the crystalline material with respect to an amorphous target. This phenomenon may occur if the direction of the impinging ion beam is nearly parallel to the main crystallographic axes or planes. In these directions, the reduction in energy loss per ion pathlength is smaller and thus the ions move deeper into the target.

In order to theoretically describe the probability of channeling, the concept of “critical channeling angle” has been introduced. In this case, the critical angle is considered as the maximum angle between the axial rows of atoms and the incoming beam at which the ions will still be guided along that axis. To investigate and predict the channeling phenomena during ion implant, nowadays there exists different software for Monte Carlo simulation in crystalline targets, for example using the binary collision approximation (MC-BCA).

Channeling is often an undesired effect, and generally, the SiC wafer is tilted in a random, non-channeling direction to minimize the channeling effects during implant. Doping profiles more or less Gaussian with respect to depth are thus obtained, where the depth is determined by the energy, the ions used and the target atomic structure. On the other hand, if the implant is performed along a crystallographic axis, a completely different profile will be obtained wherein the ions follow the direction of the crystal in depth into the target. In SiC, it has been demonstrated that the deepest channeled ions may penetrate the expected action range many times for the corresponding random implant.

In order to form locally confined implanted regions, it is known to use hard masks, for example of silicon oxide (SiO2), configured to locally shield the SiC wafer during the implant step. However, the Applicant has verified that using hard masks of the aforementioned type may cause planarity problems of the layer having the mask applied thereto, after removing the same mask, due to the lattice stress effect generated on the SiC substrate by the presence of this hard mask.

With reference toFIG.1, a portion of an electronic device1is illustrated, for example a power MOSFET, limitedly to an edge region thereof which surrounds an active area. The electronic device1includes: a semiconductor body10of SiC having a first electrical conductivity of N-type, delimited by a front side10aand a rear side10bopposite to each other; a current spreading layer (CSL)12of N-type and greater doping than the doping of the semiconductor body10, which extends into the semiconductor body10starting from the front side for a depth, for example, of 1 μm; a body region14, having a second electrical conductivity (P-type) opposite to the first electrical conductivity (N-type), extending into the CSL12at a maximum depth lower than the depth of the CSL12; a source region17in the body region14; a first edge termination region16, having the second electrical conductivity with a greater doping value than the doping value of the body region14, which extends facing the front side10ain electrical contact with the body region14, extending into the CSL12at a maximum depth lower than the depth of the CSL12; a second edge termination region18, having the second electrical conductivity and doping value lower than the doping of the first edge termination region16; a dielectric layer20on the front side10a; a conductive layer22on the dielectric layer20, forming an edge field plate of the electronic device10; a first metallization24ain electrical contact with the conductive layer22and a second metallization24bin electrical contact with the first edge termination region16and with the source17, in order to apply a predetermined bias voltage (typically in a voltage range 10-20 V) between the first and the second metallizations24a,24b.

The second edge termination region18extends into the semiconductor body10throughout a depth greater than the depth of the CSL12.

The first and the second edge termination regions16,18have the function of preventing or inhibiting the generation of an electric field of such a value as to damage the electronic device1. In particular, the Applicant has verified that an edge termination region (here in particular the edge termination region18) which extends to a greater depth than the CSL12locally interrupts the CSL12and allows the electric field to be reduced, distributing the field lines in the edge region, below the critical breakdown values of the semiconductor material and the field oxide used.

Since forming the CSL12provides for epitaxial growth or channeled deep ion implant, forming the second edge termination region18within the CSL12needs to provide a corresponding high-energy and high-dose ion implant to reach the desired depth while locally inverting the electrical conductivity (from N-type to P-type), and up to obtaining the desired doping value. It is clear that such a process step relating to the high-energy and high-dose ion implant may, in some situations, be undesired.

The need to overcome the drawbacks discussed above is therefore felt.

BRIEF SUMMARY

This present disclosure is directed to an electronic device and a manufacturing method thereof. For example, in at least one embodiment, the electronic device may be summarized as including a semiconductor body having a first electrical conductivity, a first doping value, and a front side; an active area configured to accommodate, in use, a conductive channel of the electronic device; an edge region surrounding the active area and in structural continuity with the active area, the edge region accommodating at least in part an edge termination region having a second electrical conductivity opposite to the first electrical conductivity, and the edge termination region extends into the semiconductor body starting from the front side up to a maximum depth having a first value along a direction orthogonal to the front side; a current spreading layer extending in the active area and in part in the edge region facing the front side, wherein the current spreading layer has the first electrical conductivity and a second doping value greater than the first doping value, wherein the current spreading layer has a depth in the edge region starting from the front side that is variable between a second depth value and a third depth value, the second depth value being greater than the first depth value of the edge termination region, and the third depth value being smaller than the first depth value of the edge termination region, and wherein the current spreading layer has the third depth value at at least one part of the edge termination region.

DETAILED DESCRIPTION

Preferred embodiments of the present disclosure are described hereinbelow, by way of non-limiting example.

With reference toFIG.2, a die, or chip,30, or part thereof, is illustrated in a triaxial reference system of orthogonal axes X, Y, Z. The die30is obtained after a step of dicing a semiconductor wafer, not illustrated. The die30is shown in top view on the plane XY.

The die30comprises an outer edge32which physically delimits the die30. The die30accommodates at least one electronic device40, illustrated in part inFIG.3, such as for example a MOSFET, in particular a power MOSFET, even more in particular a vertical conduction MOSFET. In the following description, the wording “electronic device” and “MOSFET” are used interchangeably and without loss of generality.

The die30includes at least two functional regions: an active area34, typically extending into a central portion of the die30, and an edge region, or peripheral region,36, which completely surrounds the active area34. The edge region extends in practice between the active area34and the outer edge32and is externally delimited by the outer edge32. The active area34includes the conductive channel region in use of the MOSFET40. The edge region36is instead a region which does not have in use the conductive channel. The edge region36comprises functional elements for reducing or preventing the crowding of the electric field lines outside the active area, such as for example one or more edge termination regions, also called guard rings, as better described and illustrated with reference toFIG.3.

FIG.3is a cross-sectional view on the plane XZ of a portion of the die30along scribe line III-III ofFIG.2. The dashed line inFIG.3, which discriminates between the active area34and the edge region36, is to be understood as qualitative.

The MOSFET40includes: a semiconductor body50, in particular of silicon carbide (SiC), even more in particular of the 4H—SiC polytype. Alternatively, the semiconductor body50may be of 3C—SiC or 6H—SiC.

In general, the semiconductor body50is of a material having a crystalline structure or lattice configured so as to allow the ion implant by exploiting the channeling. Such a crystal lattice may be described through a periodic distribution of atom (or ion/molecule) groups. Ideally, considering a crystal which extends endlessly in spatial coordinates, the periodicity results in a translation invariance (or translation symmetry). The entire crystal is therefore generated by the periodic repetition of a fundamental unit, called unit cell, which may contain atom and/or ion and/or molecule groups. The translation symmetry implies that a generic point belonging to an elementary cell is in one-to-one correspondence with a point of the elementary cell obtained with a suitable translation from the first one.

The semiconductor body50has a first electrical conductivity (for example of N-type) and doping of the order of 1·1015-1·1020atoms/cm3. In one embodiment (not illustrated in the Figures), the semiconductor body50comprises a substrate having a drift layer formed (e.g., epitaxially grown) thereon. In this case, the substrate has a doping, for example, of the order of 1·1018-1·1020atoms/cm3and the drift layer has a doping, for example, of the order of 1·1015-1·1017atoms/cm3. The drift layer has, for example, a thickness comprised between 3 and 100 μm (boundaries included).

The semiconductor body50is delimited upwardly by a front side50aand downwardly by a rear side50b, opposite to each other along the direction of the axis Z. At the front side50aa body region51is present, having a second electrical conductivity (of P-type) opposite to the first electrical conductivity. A source region52extends at the front side50ainto the body region51. A drain region54extends at the rear side50b. A gate region56extends, in a per se known manner, on the front side50aand includes a gate dielectric56aand a gate conductive region56bon the gate dielectric56a.

FIG.3illustrates, for simplicity of representation, a single body region51, a single source region52and a single gate region56. However, it is evident that the MOSFET40may comprise any plurality of said body51, source52and gate regions56. In particular, the illustrated body51, source52and gate regions56extend in proximity of the end of the active area34.

The MOSFET40also comprises, within the semiconductor body50, a first edge termination region58, implanted at the front side50aand facing the front side50a. The first edge termination region58has the second electrical conductivity and doping (P+) greater than that of the body region51. The first edge termination region58extends within the edge region36(and optionally in part also into the region of active area34) in electrical contact with the body region51. The first edge termination region58has, when biased to the body and source voltage, the function of shielding the structures of the device, which extend above the edge termination region58(in particular, the portion62aof the conductive layer62described hereinbelow), from high electric fields.

A field dielectric layer (“field oxide”)60extends above the first edge termination region58(on the front side50a) and a conductive layer62(for example a metal layer or N-type doped polysilicon) extends on the dielectric layer60. Layer62is configured to distribute the gate bias to the device (the gate conductive region56bis in electrical connection with the layer62).

The conductive layer62includes: a first portion62awhich extends over the first edge termination region58and is electrically insulated from the latter by a dielectric or oxide (e.g., SiO2) layer; and a second portion62bwhich extends above the dielectric layer60. The first and the second portions62a,62bare in mutual structural and electrical continuity. The second portion62bforms an edge field plate, of the MOSFET40, as it takes the gate potential to the edge termination region36.

The conductive layer62is (in a manner not illustrated in Figure) in electrical connection with the gate conductive region56band, in particular, it is formed during the same step of forming the gate conductive region56b. A passivation layer64extends over the conductive layer62, to protect and insulate the conductive layer62. The passivation layer64is interrupted where the metallization63is in electrical contact with the conductive layer62.

Optionally, the MOSFET40comprises a second edge termination region68having the second electrical conductivity (of P-type) and doping lower than the doping of the first edge termination region58. The second edge termination region68extends at an end portion (or end region) of the first edge termination region58, opposite the end portion (or end region) of the first edge termination region58which is in contact with the body region51. The second edge termination region68therefore extends as an extension of the first edge termination region58within the edge region36. The second edge termination region68has the function of distributing or thinning the field lines of the electric potential in such a way as to avoid a thickening of the field lines on the curvature radius of the first edge termination region58, and thus maximizing the value of the edge breakdown voltage.

The doping density of the first edge termination region58is of the order of 1·1018-1·1020atoms/cm3. The doping density of the second edge termination region68is of the order of 1·1016-1·1018atoms/cm3.

The thickness of the first edge termination region58, along the direction Z starting from the front side50a, is for example comprised between 0.3 and 1 μm (boundaries included). The thickness of the second edge termination region68, along the direction Z starting from the front side50a, is for example comprised between 0.5 and 2 μm (boundaries included).

The MOSFET40further comprises a Current Spreading Layer (CSL)70, which extends into the semiconductor body50facing the front side50a. The CSL70has a maximum thickness TCSL_MAX, starting from the front side50a, comprised between 0.3 and 2 μm along the axis Z (boundaries included). In general, the CSL70has a depth equal to that of the body51, or extends below the body51by a value up to 1μ. In one embodiment, the maximum depth reached by the CSL70is greater than the maximum depth reached by the body region51. Thus, in this case, the body region51is completely contained in the CSL70.

The CSL70forms an enrichment layer having the function of improving the value of on-state resistance Ron of the MOSFET40. The doping of the CSL70is greater than the doping of the semiconductor body50. The CSL70has, for example, doping of the order of 1017atoms/cm3or comprised between 2 and 20 times the doping of the portion of the semiconductor body50accommodating it.

According to one aspect of the present disclosure, the CSL70has a thickness, along the axis Z starting from the front side50a, that is not uniform. In particular, the CSL70has the maximum thickness TCSL_MAXat the active area34(where it performs its function of reducing Ron) and a different thickness TCSL_MINat a portion of the first edge termination region58(in particular, at least, at the end portion (or end region) of the first edge termination region58which is opposite to that in contact with the body region51). In the embodiment wherein the MOSFET40has the second edge termination region68, the CSL70has the thickness TCSL_MINalso at the second edge termination region68(in particular at least throughout the entire extension of the second edge termination region68). The value of TCSL_MINis lower than the value of TCSL_MAX, in particular comprised between 0 and 0.3μ. The value TCSL_MINis equal to zero where the P-dopant dose of the edge termination region58(and if any, region68) is greater than the respective N-dopant dose of the CSL70, due to the local inversion of the electrical conductivity type (from N to P).

The thickness TCSL_MAXof the CSL70is greater than the maximum thickness of the first edge termination region58and also than the maximum thickness of the second edge termination region68, when present.

According to one aspect of the present disclosure, the CSL70is formed by a channeled ion implant.

The channeled implant occurs when the ion beam during implant is aligned with the channeling directions. For example, in SiC, the direction 000-1 or the direction 11-23. Typically the substrates are cut from ingots grown in the 000-1 direction with a surface inclined (for dicing wafers) by 4° for substrates having a diameter of 150 mm or 200 mm. This entails that to implant with channeling on a 000-1 wafer it is necessary to tilt the ion beam during the implant with tilt of 4°, and for a 11-23 wafer of 13° or 21°.

The Applicant has verified that the channeling effect is altered by the presence of a masking surface layer arranged over the front side50aof the semiconductor body50, such as for example one or more natural or intentionally added oxide layers. In the case of using said masking surface layer, the thickness TCSL_MINof the CSL70may be equal to zero, or in the regions of the semiconductor body50at the masking surface layer the CSL70may be absent. The thickness value TCSL_MINof the CSL70is a function of the thickness of said masking surface layer and, for sufficiently high thicknesses of the masking surface layer, the CSL70does not extend below said masking surface layer.

The Applicant has also verified that the channeling effect is altered by an intentional damage to a region of the surface of the semiconductor body50, at the front side50a, i.e., whereat the channeled implant for forming the CSL70occurs. This damage may be obtained, for example, by ion implant of non-reactive or non-doping species, i.e., such as to cause damage to the crystal lattice of the semiconductor body50, without locally altering the conductive characteristics thereof. Chemical species suitable for this purpose include for example ions of Si, Ar, Ge, He.

Therefore, according to one aspect of the present disclosure, a damaged region80is formed at the front side50a, in order to alter or inhibit the channeling while forming the CSL70.

The damaged region80extends to a maximum depth, in the semiconductor body50starting from the front side50a, comprised for example between 0.1 and 0.6 μm (boundaries included). In one embodiment, the thickness of the damaged region80is uniform; in a further embodiment, the thickness of the damaged region80is not uniform but varies between a maximum value of 0.6 μm and a minimum value of 0.1 μm.

The damaged region80extends into the edge region36of the MOSFET40, in particular at the portions of the semiconductor body50wherein it is desired to form the CSL70with the thickness TCSL_MIN.

Forming the damaged region80comprises using implant doses greater than 1013atoms/cm2and energies sufficient to cause the atoms to shift from the crystal structure throughout the necessary depth (e.g., energy in the range 30-300 keV, boundaries included). The implant that introduces the damage is not performed in channeling conditions and the annealing of the wafer during the process is avoided not to remove the damage produced.

According to a further embodiment, the damaged region80is formed by one or more steps of etching the front side50aof the semiconductor body50, for example a RIE (Reactive Ion Etching) process with physical etching characteristics (ion bombardment).

In order to damage by etching only the desired surface portion (i.e., the one whereat it is desired to have the CSL70with thickness TCSL_MIN) an etching mask is used which exposes only the desired surface portion.

As a result of the two possible damaging steps mentioned above, the semiconductor body50does not have, at the damaged region80, the same lattice structure as the semiconductor body50which extends laterally to the damaged region80. In particular, the semiconductor body50, where damaged, has an amorphous structure or a disordered crystalline structure or lattice structure with no spatial symmetry of the unintentionally damaged portions of the semiconductor body50. The Applicant has verified that by carrying out an unmasked implant for forming the CSL70, it is formed, however, at the damaged region80, a thin implanted layer of thickness TCSL_MIN. Since, as said, the region of CSL70, having thickness TCSL_MIN, has a thickness lower than the thickness of the first and the second edge termination regions58,68, the presence of the CSL70with thickness TCSL_MIN, does not affect the operation of the MOSFET40.

The value TCSL_MINis equal to zero where the P-dopant dose of the edge termination region58(and if any, region68) is greater than the respective N-dopant dose of the CSL70, due to the local inversion of the electrical conductivity type (from N to P). The thickness value of the CSL70is greater than zero, but smaller than TCSL_MAX, at the damaged region80laterally to the first edge termination region58and to the second edge termination region68(when present).

FIG.3further illustrates a channel stop region90, optional, which extends laterally to the damaged region80, at and facing the front side50a. The channel stop region90extends in particular between the damaged region80and the edge32of the die30. The channel stop region90is formed by implant of doping species having the first conductivity (N-type, for example obtained by doping with phosphorus) and dopant dose comprised between 1·1019and 5·1020atoms/cm3. The channel stop region90has the function of forming an equipotential ring with the drain on the die edge.

It is also noted that, between the damaged region80and the edge32of the die30there is also present, optionally, a portion of CSL70having the depth value TCSL_MAX, the channel stop region90extending within this portion of CSL70and having a respective depth value, in the semiconductor body50, smaller than TCSL_MAX.

FIG.4illustrates, by a flowchart, steps of a manufacturing process of the MOSFET40, limitedly to the elements useful to understand the present disclosure.

With reference toFIG.4, step S1, the semiconductor body50is provided and, step S2, the damaged region80is formed according to any of the techniques described above. Then, step S3, the CSL70is formed by channeled ion implant. As previously described, the CSL70has different thicknesses TCSL_MINand TCSL_MAXrespectively at the damaged region80and laterally to the damaged region80, as a result of the presence and the absence of the damaged region80, even in the absence of an implant mask. Finally, step S4, the edge termination regions58,68are formed by traditional or random ion implant (channeled).

Step S2may be replaced by forming the masking surface layer, as previously described. However, forming the damaged region80through an implant has the advantage of not requiring, with respect to forming the masking surface layer, a further step of selectively removing the masking surface layer.

Following the steps S1-S4described, the structure of the MOSFET40is completed, as regards the edge region36, with the formation of the field dielectric layer60, the conductive layer62, the metallization63and the passivation layer64.

The advantages of the present disclosure are evident from what has been previously described. In particular, according to the present disclosure, using a hard mask in step S3inFIG.4is not necessary. Furthermore, forming the edge termination regions58,68does not require using a high-energy and high-dose ion implant to reach the desired depth and electrical conductivity.

Finally, it is clear that modifications and variations may be made to what is described and illustrated herein without thereby departing from the scope of the present disclosure, as defined in the attached claims.

For example, the present disclosure applies to an electronic device other than a vertical channel MOSFET, such as for example a horizontal channel MOSFET, a trenchFET, a diode, a triristor, a MESFET, a MISFET, an IGBT.

Furthermore, the semiconductor body50may be a material other than SiC, such as for example GaN.

Furthermore, the semiconductor body50may comprise a substrate of semiconductor material (SiC, GaN, etc.) and optionally one or more epitaxial surface layers grown on the substrate.

Furthermore, in one embodiment, the body region51shown inFIGS.3and5, i.e., the body region in direct electrical connection with the first edge termination region58, does not accommodate the source region52. In fact, in this embodiment, the illustrated body region51extends up to the edge region36, i.e., in proximity of an area of the device40designed not to participate in the electrical conduction; the absence of the source region prevents the flow of charge carriers (conduction current) towards the edge region36.

In summary, therefore, the present disclosure relates to an electronic device40, comprising:the semiconductor body50, having a first electrical conductivity (e.g., N) and a first doping value, and provided with the front side50aand the rear side50bopposite to each other along the direction Z;the active area34configured to accommodate, in use, the conductive channel of the electronic device;the edge region36, surrounding the active area34and in structural continuity with the active area34, and accommodating at least in part the edge termination region (only the region58or both the regions58and68, previously described) having a second electrical conductivity (e.g., P) opposite to the first electrical conductivity (N) and which extends into the semiconductor body50starting from the front side50aup to a maximum depth, along the direction Z, having a first value (the first depth value is the value of the edge termination region58or the greater of the depth values of the edge termination region58and of the edge termination region68when the latter is present).

The edge region36also accommodates the current spreading layer, CSL,70extending into the active area34and in part into the edge region36, facing the front side50a, wherein the CSL70has the electrical conductivity N and a second doping value greater than the first doping value. The CSL70is at least absent at at least part of the edge termination region (i.e., at part of the region58and, if any, of the region68). In other words, the CSL70has, at at least one part of the edge termination region (i.e., at part of the region58and, if any, of the region68), the minimum depth value TCSL_MIN, where the value TCSL_MINis equal to zero where the P-dopant dose of the edge termination region is greater than the respective N-dopant dose of the CSL70. The CSL70also has depth, in the semiconductor body50, starting from the front side50a, variable between a maximum value TCSL_MAXand the minimum value TCSL_MIN, the maximum depth value TCSL_MAXbeing greater than the first depth value and the minimum depth value TCSL_MINbeing smaller than the first depth value.

In a further embodiment, the electronic device40(here, a MOSFET) has, in the edge region36, the damaged region80which extends throughout the entire extension of the edge region36. Therefore, in the edge region36, the CSL70never reaches the depth value TCSL_MAX. The first edge termination region58and, if any, the second edge termination region68alternately extend throughout a portion of the damaged region80or throughout the entire extension of the damaged region80.

With reference toFIG.5, in case both the damaged80and edge termination regions58(and optionally region68) extend throughout the entire extension of the edge region36, the CSL70is absent in the edge region36. Elements ofFIG.5which correspond to elements ofFIG.3are illustrated with the same reference numerals and are not further described.

An electronic device (40), may be summarized as including: a semiconductor body (50), having a first electrical conductivity (N) and a first doping value, and provided with a front side (50a); an active area (34) configured to accommodate, in use, a conductive channel of the electronic device; an edge region (36), surrounding the active area (34) and in structural continuity with the active area (34), and accommodating at least in part an edge termination region (58;58,68) having a second electrical conductivity (P) opposite to the first electrical conductivity (N) and which extends into the semiconductor body (50) starting from the front side (50a) up to a maximum depth having a first value along a direction (Z) orthogonal to the front side (50a); a current spreading layer, CSL, (70) extending in said active area (34) and in part in said edge region (36) facing the front side (50a), wherein the CSL (70) has the first electrical conductivity (N) and a second doping value greater than the first doping value, characterized in that the CSL (70) has depth, in the edge region (36) starting from the front side (50a), variable between a second depth value (TCSL_MAX) and a third depth value (TCSL_MIN), said second depth value (TCSL_MAX) being greater than the first depth value of the edge termination region, and said third depth value (TCSL_MIN) being smaller than the first depth value of the edge termination region, and wherein the CSL (70) has the third depth value (TCSL_MIN) at at least one part of the edge termination region (58;58,68).

The semiconductor body (50) may be of a material having a lattice structure with spatial symmetry, the electronic device (40) may further include a damaged region (80) extending for a part of the edge region (36) at the front side (50a) and the semiconductor body (50) may have an amorphous lattice structure or lattice structure with no spatial symmetry.

The edge termination region (58;58,68) may extend at least in part at said damaged region (80), completely superimposed on said damaged region (80) where it may be at said damaged region (80) thus forming a superimposition area, and also may extend below the damaged region (80) up to said first depth value of the edge termination region (58;58,68).

The third depth value (TCSL_MIN) may be zero, wherein the CSL (70) may have the third depth value (TCSL_MIN) at the superimposition zone between the edge termination region (58;58,68) and the damaged region (80), and the damaged region (80) may further extend laterally to the superimposition zone, the CSL (70) having a fourth depth value, greater than zero and smaller than the second depth value (TCSL_MAX), at the damaged region (80) laterally and adjacent to the superimposition zone.

Said damaged region (80) may accommodate non-reactive or non-doping ion species, such as for example Si, Ar, Ge, He.

Said damaged region (80) may extend into the semiconductor body (50), starting from the front side (50a), throughout a maximum depth having a fifth value which may be smaller than the first and the second depth values (TCSL_MAX).

The fifth depth value of the damaged region (80) may be between 0.1 and 0.6 μm.

The active area (34) may include at least one body region (51) having the second electrical conductivity (P), and at least one source region (52) having the first electrical conductivity (N) in the body region, wherein the body region may extend into the semiconductor body (50), starting from the front side (50a), up to a maximum depth having a sixth value which may be smaller than the second depth value (TCSL_MAX).

The edge termination region (58;58,68) may be in electrical contact with the body region and may have a greater doping than the respective doping of the body region.

The edge termination region (58;58,68) may include a first guard ring (58) and a second guard ring (68) in mutual electrical continuity, the first guard ring having a greater doping than the doping of the second guard ring and being in direct electrical connection to the body region through a first end portion, the second guard ring being in direct electrical connection to the first guard ring at a second end portion of the first guard ring.

The semiconductor body (50) may be of Silicon Carbide, in particular of 3C—SiC, 4H—SiC, 6H—SiC.

Said device may be one of: a vertical conduction transistor may further include a drain region (54) extending at a rear side (50b), opposite to the front side (50a) along said direction (Z), of the semiconductor body (50); a horizontal conduction transistor may further include a drain region extending at the front side (50a) of the semiconductor body (50).

An electronic device (40), may be summarized as including: a semiconductor body (50), having a first electrical conductivity (N) and a first doping value, and provided with a front side (50a); an active area (34) configured to accommodate, in use, a conductive channel of the electronic device; an edge region (36), surrounding the active area (34) and in structural continuity with the active area (34), and accommodating at least in part an edge termination region (58;58,68) having a second electrical conductivity (P) opposite to the first electrical conductivity (N) and which extends into the semiconductor body (50) starting from the front side (50a) up to a maximum depth having a first value along a direction (Z) orthogonal to the front side (50a); a current spreading layer, CSL, (70), extending into said active area (34) and having the first electrical conductivity (N) and a second doping value greater than the first doping value, characterized in that the CSL (70) is absent at the edge region (36).

A method of manufacturing an electronic device (40), may be summarized as including the steps of: arranging (S1) a semiconductor body (50), having a first electrical conductivity (N) and a first doping value, and provided with a front side (50a), the semiconductor body (50) including an active area (34) configured to accommodate, in use, a conductive channel of the electronic device and an edge region (36), surrounding the active area (34) and in structural continuity with the active area (34); forming, at least in part in the edge region (36), an edge termination region (58;58,68) having a second electrical conductivity (P) opposite to the first electrical conductivity (N) and which extends into the semiconductor body (50) starting from the front side (50a) up to a maximum depth having a first value along a direction (Z) orthogonal to the front side (50a); forming (S3) a current spreading layer, CSL, (70) in said active area (34) and in part in said edge region (36), facing the front side (50a), wherein the CSL (70) has the first electrical conductivity (N) and a second doping value greater than the first doping value, characterized in that the step of forming (S3) the CSL (70) includes forming the CSL (70) with a depth, in the edge region (36) starting from the front side (50a), variable between a second depth value (TCSL_MAX) and a third depth value (TCSL_MIN), said second depth value (TCSL_MAX) being greater than the first depth value and said third depth value (TCSL_MIN) being smaller than the first depth value, and wherein the CSL (70) has the third depth value (TCSL_MIN) at at least one part of the edge termination region (58;58,68).

The semiconductor body (50) may be of a material having a lattice structure with spatial symmetry, may further include the step of altering, in a selective portion of the edge region (36) at the front side (50a), said spatial symmetry thus forming a damaged region (80) with an amorphous lattice structure or lattice structure with no spatial symmetry, said step of forming the damaged region (80) being performed before the steps of forming the CSL (70) and the edge termination region (58;58,68).

The step of forming the damaged region (80) may include performing an implant of non-reactive or non-doping ion species, such as for example Si, Ar, Ge, He.

The step of forming the damaged region (80) may include performing an etching.

The step of forming the CSL (70) may be performed before the step of forming the edge termination region (58;58,68), and may include performing a channeled ion implant in the semiconductor body (50), at both the damaged region (80) and laterally to the damaged region (80), the CSL (70) having the second depth value (TCSL_MAX) laterally to the damaged region (80) and the third depth value (TCSL_MIN) at the damaged region (80).

Forming the edge termination region (58;58,68) may include performing an implant of ion species having the second electrical conductivity (P) at least in part at said damaged region (80).

The step of forming the damaged region (80) may include performing said implant of non-reactive or non-doping ion species using the following parameters: implant energy comprised between 30 keV and 300 keV; implant dose of the order of 1013atoms/cm2.