Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform

A method is described. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes any of: recognizing there are a different number of kernels in the program code than stencil processors in the image processor; recognizing that at least one of the kernels is more computationally intensive than another one of the kernels; and, recognizing that the program code has resource requirements that exceed the image processor's memory capacity. The compiling further includes in response to any of the recognizing above performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; splitting the directed acyclic graph into smaller graphs.

FIELD OF INVENTION

The field of invention pertains generally to image processing, and, more specifically, to compiler techniques for mapping program code to a programmable image processing hardware platform, such as a high performance, power efficient programmable image processing hardware platform.

BACKGROUND

Image processing typically involves the processing of pixel values that are organized into an array. Here, a spatially organized two dimensional array captures the two dimensional nature of images (additional dimensions may include time (e.g., a sequence of two dimensional images) and data type (e.g., colors). In a typical scenario, the arrayed pixel values are provided by a camera that has generated a still image or a sequence of frames to capture images of motion. Traditional image processors typically fall on either side of two extremes.

A first extreme performs image processing tasks as software programs executing on a general purpose processor or general purpose-like processor (e.g., a general purpose processor with vector instruction enhancements). Although the first extreme typically provides a highly versatile application software development platform, its use of finer grained data structures combined with the associated overhead (e.g., instruction fetch and decode, handling of on-chip and off-chip data, speculative execution) ultimately results in larger amounts of energy being consumed per unit of data during execution of the program code.

A second, opposite extreme applies fixed function hardwired circuitry to much larger blocks of data. The use of larger (as opposed to finer grained) blocks of data applied directly to custom designed circuits greatly reduces power consumption per unit of data. However, the use of custom designed fixed function circuitry generally results in a limited set of tasks that the processor is able to perform. As such, the widely versatile programming environment (that is associated with the first extreme) is lacking in the second extreme.

A technology platform that provides for both highly versatile application software development opportunities combined with improved power efficiency per unit of data remains a desirable yet missing solution.

SUMMARY

A method is described. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes any of: recognizing there are a different number of kernels in the program code than stencil processors in the image processor; recognizing that at least one of the kernels is more computationally intensive than another one of the kernels; and, recognizing that the program code has resource requirements that exceed the image processor's memory capacity. The compiling further includes in response to any of the recognizing above performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; splitting the directed acyclic graph into smaller graphs.

An apparatus is described. The apparatus includes means for compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the means for compiling includes means for any of: recognizing there are a different number of kernels in the program code than stencil processors in the image processor; recognizing that at least one of the kernels is more computationally intensive than another one of the kernels; and, recognizing that the program code has resource requirements that exceed the image processor's memory capacity. The means for compiling further includes means for, in response to any of the recognizing above, performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; splitting the directed acyclic graph into smaller graphs.

DETAILED DESCRIPTION

a. Image Processor Hardware Architecture and Operation

FIG. 1shows an embodiment of an architecture100for an image processor implemented in hardware. The image processor may be targeted, for example, by a compiler that converts program code written for a virtual processor within a simulated environment into program code that is actually executed by the hardware processor. As observed inFIG. 1, the architecture100includes a plurality of line buffer units101_1through101_M interconnected to a plurality of stencil processor units102_1through102_N and corresponding sheet generator units103_1through103_N through a network104(e.g., a network on chip (NOC) including an on chip switch network, an on chip ring network or other kind of network). In an embodiment, any line buffer unit may connect to any sheet generator and corresponding stencil processor through the network104.

In an embodiment, program code is compiled and loaded onto a corresponding stencil processor102to perform the image processing operations earlier defined by a software developer (program code may also be loaded onto the stencil processor's associated sheet generator103, e.g., depending on design and implementation). In at least some instances an image processing pipeline may be realized by loading a first kernel program for a first pipeline stage into a first stencil processor102_1, loading a second kernel program for a second pipeline stage into a second stencil processor102_2, etc. where the first kernel performs the functions of the first stage of the pipeline, the second kernel performs the functions of the second stage of the pipeline, etc. and additional control flow methods are installed to pass output image data from one stage of the pipeline to the next stage of the pipeline.

In other configurations, the image processor may be realized as a parallel machine having two or more stencil processors102_1,102_2operating the same kernel program code. For example, a highly dense and high data rate stream of image data may be processed by spreading frames across multiple stencil processors each of which perform the same function.

In yet other configurations, essentially any DAG of kernels may be loaded onto the hardware processor by configuring respective stencil processors with their own respective kernel of program code and configuring appropriate control flow hooks into the hardware to direct output images from one kernel to the input of a next kernel in the DAG design.

As a general flow, frames of image data are received by a macro I/O unit105and passed to one or more of the line buffer units101on a frame by frame basis. A particular line buffer unit parses its frame of image data into a smaller region of image data, referred to as a “a line group”, and then passes the line group through the network104to a particular sheet generator. A complete or “full” singular line group may be composed, for example, with the data of multiple contiguous complete rows or columns of a frame (for simplicity the present specification will mainly refer to contiguous rows). The sheet generator further parses the line group of image data into a smaller region of image data, referred to as a “sheet”, and presents the sheet to its corresponding stencil processor.

In the case of an image processing pipeline or a DAG flow having a single input, generally, input frames are directed to the same line buffer unit101_1which parses the image data into line groups and directs the line groups to the sheet generator103_1whose corresponding stencil processor102_1is executing the code of the first kernel in the pipeline/DAG. Upon completion of operations by the stencil processor102_1on the line groups it processes, the sheet generator103_1sends output line groups to a “downstream” line buffer unit101_2(in some use cases the output line group may be sent back to the same line buffer unit101_1that earlier had sent the input line groups).

One or more “consumer” kernels that represent the next stage/operation in the pipeline/DAG executing on their own respective other sheet generator and stencil processor (e.g., sheet generator103_2and stencil processor102_2) then receive from the downstream line buffer unit101_2the image data generated by the first stencil processor102_1. In this manner, a “producer” kernel operating on a first stencil processor has its output data forwarded to a “consumer” kernel operating on a second stencil processor where the consumer kernel performs the next set of tasks after the producer kernel consistent with the design of the overall pipeline or DAG.

A stencil processor102is designed to simultaneously operate on multiple overlapping stencils of image data. The multiple overlapping stencils and internal hardware processing capacity of the stencil processor effectively determines the size of a sheet. Here, within a stencil processor102, arrays of execution lanes operate in unison to simultaneously process the image data surface area covered by the multiple overlapping stencils.

As will be described in more detail below, in various embodiments, sheets of image data are loaded into a two-dimensional register array structure within the stencil processor102. The use of sheets and the two-dimensional register array structure is believed to effectively provide for power consumption improvements by moving a large amount of data into a large amount of register space as, e.g., a single load operation with processing tasks performed directly on the data immediately thereafter by an execution lane array. Additionally, the use of an execution lane array and corresponding register array provide for different stencil sizes that are easily programmable/configurable.

FIGS. 2athrough 2eillustrate at a high level embodiments of both the parsing activity of a line buffer unit101, the finer grained parsing activity of a sheet generator unit103as well as the stencil processing activity of the stencil processor102that is coupled to the sheet generator unit103.

FIG. 2adepicts an embodiment of an input frame of image data201.FIG. 2aalso depicts an outline of three overlapping stencils202(each having a dimension of 3 pixels×3 pixels) that a stencil processor is designed to operate over. The output pixel that each stencil respectively generates output image data for is highlighted in solid black. For simplicity, the three overlapping stencils202are depicted as overlapping only in the vertical direction. It is pertinent to recognize that in actuality a stencil processor may be designed to have overlapping stencils in both the vertical and horizontal directions.

Because of the vertical overlapping stencils202within the stencil processor, as observed inFIG. 2a, there exists a wide band of image data within the frame that a single stencil processor can operate over. As will be discussed in more detail below, in an embodiment, the stencil processors process data within their overlapping stencils in a left to right fashion across the image data (and then repeat for the next set of lines, in top to bottom order). Thus, as the stencil processors continue forward with their operation, the number of solid black output pixel blocks will grow right-wise horizontally. As discussed above, a line buffer unit101is responsible for parsing a line group of input image data from an incoming frame that is sufficient for the stencil processors to operate over for an extended number of upcoming cycles. An exemplary depiction of a line group is illustrated as a shaded region203. In an embodiment, the line buffer unit101can comprehend different dynamics for sending/receiving a line group to/from a sheet generator. For example, according to one mode, referred to as “full group”, the complete full width lines of image data are passed between a line buffer unit and a sheet generator. According to a second mode, referred to as “virtually tall”, a line group is passed initially with a subset of full width rows. The remaining rows are then passed sequentially in smaller (less than full width) pieces.

With the line group203of the input image data having been defined by the line buffer unit and passed to the sheet generator unit, the sheet generator unit further parses the line group into finer sheets that are more precisely fitted to the hardware limitations of the stencil processor. More specifically, as will be described in more detail further below, in an embodiment, each stencil processor consists of a two dimensional shift register array. The two dimensional shift register array essentially shifts image data “beneath” an array of execution lanes where the pattern of the shifting causes each execution lane to operate on data within its own respective stencil (that is, each execution lane processes on its own stencil of information to generate an output for that stencil). In an embodiment, sheets are surface areas of input image data that “fill” or are otherwise loaded into the two dimensional shift register array.

As will be described in more detail below, in various embodiments, there are actually multiple layers of two dimensional register data that can be shifted on any cycle. For convenience, much of the present description will simply use the term “two-dimensional shift register” and the like to refer to structures that have one or more such layers of two-dimensional register data that can be shifted.

Thus, as observed inFIG. 2b, the sheet generator parses an initial sheet204from the line group203and provides it to the stencil processor (here, the sheet of data corresponds to the shaded region that is generally identified by reference number204). As observed inFIGS. 2cand 2d, the stencil processor operates on the sheet of input image data by effectively moving the overlapping stencils202in a left to right fashion over the sheet. As ofFIG. 2d, the number of pixels for which an output value could be calculated from the data within the sheet is exhausted (no other pixel positions can have an output value determined from the information within the sheet). For simplicity the border regions of the image have been ignored.

As observed inFIG. 2ethe sheet generator then provides a next sheet205for the stencil processor to continue operations on. Note that the initial positions of the stencils as they begin operation on the next sheet is the next progression to the right from the point of exhaustion on the first sheet (as depicted previously inFIG. 2d). With the new sheet205, the stencils will simply continue moving to the right as the stencil processor operates on the new sheet in the same manner as with the processing of the first sheet.

Note that there is some overlap between the data of the first sheet204and the data of the second sheet205owing to the border regions of stencils that surround an output pixel location. The overlap could be handled simply by the sheet generator re-transmitting the overlapping data twice. In alternate implementations, to feed a next sheet to the stencil processor, the sheet generator may proceed to only send new data to the stencil processor and the stencil processor reuses the overlapping data from the previous sheet.

b. Stencil Processor Design and Operation

FIG. 3shows an embodiment of a stencil processor architecture300. As observed inFIG. 3, the stencil processor includes a data computation unit301, a scalar processor302and associated memory303and an I/O unit304. The data computation unit301includes an array of execution lanes305, a two-dimensional shift array structure306and separate random access memories307associated with specific rows or columns of the array.

The I/O unit304is responsible for loading “input” sheets of data received from the sheet generator into the data computation unit301and storing “output” sheets of data from the stencil processor into the sheet generator. In an embodiment the loading of sheet data into the data computation unit301entails parsing a received sheet into rows/columns of image data and loading the rows/columns of image data into the two dimensional shift register structure306or respective random access memories307of the rows/columns of the execution lane array (described in more detail below). If the sheet is initially loaded into memories307, the individual execution lanes within the execution lane array305may then load sheet data into the two-dimensional shift register structure306from the random access memories307when appropriate (e.g., as a load instruction just prior to operation on the sheet's data). Upon completion of the loading of a sheet of data into the register structure306(whether directly from a sheet generator or from memories307), the execution lanes of the execution lane array305operate on the data and eventually “write back” finished data as a sheet directly back to the sheet generator, or, into the random access memories307. If the later the I/O unit304fetches the data from the random access memories307to form an output sheet which is then forwarded to the sheet generator.

The scalar processor302includes a program controller309that reads the instructions of the stencil processor's program code from scalar memory303and issues the instructions to the execution lanes in the execution lane array305. In an embodiment, a single same instruction is broadcast to all execution lanes within the array305to effect a SIMD-like behavior from the data computation unit301. In an embodiment, the instruction format of the instructions read from scalar memory303and issued to the execution lanes of the execution lane array305includes a very-long-instruction-word (VLIW) type format that includes more than one opcode per instruction. In a further embodiment, the VLIW format includes both an ALU opcode that directs a mathematical function performed by each execution lane's ALU (which, as described below, in an embodiment may specify more than one traditional ALU operation) and a memory opcode (that directs a memory operation for a specific execution lane or set of execution lanes).

The term “execution lane” refers to a set of one or more execution units capable of executing an instruction (e.g., logic circuitry that can execute an instruction). An execution lane can, in various embodiments, include more processor-like functionality beyond just execution units, however. For example, besides one or more execution units, an execution lane may also include logic circuitry that decodes a received instruction, or, in the case of more MIMD-like designs, logic circuitry that fetches and decodes an instruction. With respect to MIMD-like approaches, although a centralized program control approach has largely been described herein, a more distributed approach may be implemented in various alternative embodiments (e.g., including program code and a program controller within each execution lane of the array305).

The combination of an execution lane array305, program controller309and two dimensional shift register structure306provides a widely adaptable/configurable hardware platform for a broad range of programmable functions. For example, application software developers are able to program kernels having a wide range of different functional capability as well as dimension (e.g., stencil size) given that the individual execution lanes are able to perform a wide variety of functions and are able to readily access input image data proximate to any output array location.

Apart from acting as a data store for image data being operated on by the execution lane array305, the random access memories307may also keep one or more look-up tables. In various embodiments one or more scalar look-up tables may also be instantiated within the scalar memory303.

A scalar look-up involves passing the same data value from the same look-up table from the same index to each of the execution lanes within the execution lane array305. In various embodiments, the VLIW instruction format described above is expanded to also include a scalar opcode that directs a look-up operation performed by the scalar processor into a scalar look-up table. The index that is specified for use with the opcode may be an immediate operand or fetched from some other data storage location. Regardless, in an embodiment, a look-up from a scalar look-up table within scalar memory essentially involves broadcasting the same data value to all execution lanes within the execution lane array305during the same clock cycle. Additional details concerning use and operation of look-up tables is provided further below.

FIG. 3bsummarizes the VLIW instruction word embodiments(s) discussed above. As observed inFIG. 3b, the VLIW instruction word format includes fields for three separate instructions: 1) a scalar instruction351that is executed by the scalar processor; 2) an ALU instruction352that is broadcasted and executed in SIMD fashion by the respective ALUs within the execution lane array; and, 3) a memory instruction353that is broadcasted and executed in a partial SIMD fashion (e.g., if execution lanes along a same row in the execution lane array share a same random access memory, then one execution lane from each of the different rows actually execute the instruction (the format of the memory instruction353may include an operand that identifies which execution lane from each row executes the instruction)

A field354for one or more immediate operands is also included. Which of the instructions351,352,353use which immediate operand information may be identified in the instruction format. Each of instructions351,352,353also include their own respective input operand and resultant information (e.g., local registers for ALU operations and a local register and a memory address for memory access instructions). In an embodiment, the scalar instruction351is executed by the scalar processor before the execution lanes within the execution lane array execute either of the other to instructions352,353. That is, the execution of the VLIW word includes a first cycle upon which the scalar instruction351is executed followed by a second cycle upon with the other instructions352,353may be executed (note that in various embodiments instructions352and353may be executed in parallel).

In an embodiment, the scalar instructions executed by the scalar processor include commands issued to the sheet generator to load/store sheets from/into the memories or 2D shift register of the data computation unit. Here, the sheet generator's operation can be dependent on the operation of the line buffer unit or other variables that prevent pre-runtime comprehension of the number of cycles it will take the sheet generator to complete any command issued by the scalar processor. As such, in an embodiment, any VLIW word whose scalar instruction351corresponds to or otherwise causes a command to be issued to the sheet generator also includes no-operation (NOOP) instructions in the other two instruction field352,353. The program code then enters a loop of NOOP instructions for instruction fields352,353until the sheet generator completes its load/store to/from the data computation unit. Here, upon issuing a command to the sheet generator, the scalar processor may set a bit of an interlock register that the sheet generator resets upon completion of the command. During the NOOP loop the scalar processor monitors the bit of the interlock bit. When the scalar processor detects that the sheet generator has completed its command normal execution begins again.

FIG. 4shows an embodiment of a data computation component401. As observed inFIG. 4, the data computation component401includes an array of execution lanes405that are logically positioned “above” a two-dimensional shift register array structure406. As discussed above, in various embodiments, a sheet of image data provided by a sheet generator is loaded into the two-dimensional shift register406. The execution lanes then operate on the sheet data from the register structure406.

The execution lane array405and shift register structure406are fixed in position relative to one another. However, the data within the shift register array406shifts in a strategic and coordinated fashion to cause each execution lane in the execution lane array to process a different stencil within the data. As such, each execution lane determines the output image value for a different pixel in the output sheet being generated. From the architecture ofFIG. 4it should be clear that overlapping stencils are not only arranged vertically but also horizontally as the execution lane array405includes vertically adjacent execution lanes as well as horizontally adjacent execution lanes.

Some notable architectural features of the data computation unit401include the shift register structure406having wider dimensions than the execution lane array405. That is, there is a “halo” of registers409outside the execution lane array405. Although the halo409is shown to exist on two sides of the execution lane array, depending on implementation, the halo may exist on less (one) or more (three or four) sides of the execution lane array405. The halo405serves to provide “spill-over” space for data that spills outside the bounds of the execution lane array405as the data is shifting “beneath” the execution lanes405. As a simple case, a 5×5 stencil centered on the right edge of the execution lane array405will need four halo register locations further to the right when the stencil's leftmost pixels are processed. For ease of drawing,FIG. 4shows the registers of the right side of the halo as only having horizontal shift connections and registers of the bottom side of the halo as only having vertical shift connections when, in a nominal embodiment, registers on either side (right, bottom) would have both horizontal and vertical connections. In various embodiments, the halo region does not include corresponding execution lane logic to execute image processing instructions (e.g., no ALU is present). However, individual memory access units (M) are present in each of the halo region locations so that the individual halo register locations can individually load data from memory and store data to memory.

Additional spill-over room is provided by random access memories407that are coupled to each row and/or each column in the array, or portions thereof (E.g., a random access memory may be assigned to a “region” of the execution lane array that spans 4 execution lanes row wise and 2 execution lanes column wise. For simplicity the remainder of the application will refer mainly to row and/or column based allocation schemes). Here, if a execution lane's kernel operations require it to process pixel values outside of the two-dimensional shift register array406(which some image processing routines may require) the plane of image data is able to further spill-over, e.g., from the halo region409into random access memory407. For example, consider a 6×6 stencil where the hardware includes a halo region of only four storage elements to the right of a execution lane on the right edge of the execution lane array. In this case, the data would need to be shifted further to the right off the right edge of the halo409to fully process the stencil. Data that is shifted outside the halo region409would then spill-over to random access memory407. Other applications of the random access memories407and the stencil processor ofFIG. 3are provided further below.

FIGS. 5athrough 5kdemonstrate a working example of the manner in which image data is shifted within the two dimensional shift register array “beneath” the execution lane array as alluded to above. As observed inFIG. 5a, the data contents of the two dimensional shift array are depicted in a first array507and the execution lane array is depicted by a frame505. Also, two neighboring execution lanes510within the execution lane array are simplistically depicted. In this simplistic depiction510, each execution lane includes a register R1that can accept data from the shift register, accept data from an ALU output (e.g., to behave as an accumulator across cycles), or write output data into an output destination.

Each execution lane also has available, in a local register R2, the contents “beneath” it in the two dimensional shift array. Thus, R1is a physical register of the execution lane while R2is a physical register of the two dimensional shift register array. The execution lane includes an ALU that can operate on operands provided by R1and/or R2. As will be described in more detail further below, in an embodiment the shift register is actually implemented with multiple (a “depth” of) storage/register elements per array location but the shifting activity is limited to one plane of storage elements (e.g., only one plane of storage elements can shift per cycle).FIGS. 5athrough 5kdepict one of these deeper register locations as being used to store the resultant X from the respective execution lanes. For illustrative ease the deeper resultant register is drawn alongside rather than beneath its counterpart register R2.

FIGS. 5athrough 5kfocus on the calculation of two stencils whose central position is aligned with the pair of execution lane positions511depicted within the execution lane array. For ease of illustration, the pair of execution lanes510are drawn as horizontal neighbors when in fact, according to the following example, they are vertical neighbors.

As observed initially inFIG. 5a, the execution lanes are centered on their central stencil locations.FIG. 5bshows the object code executed by both execution lanes. As observed inFIG. 5bthe program code of both execution lanes causes the data within the shift register array to shift down one position and shift right one position. This aligns both execution lanes to the upper left hand corner of their respective stencils. The program code then causes the data that is located (in R2) in their respective locations to be loaded into R1.

As observed inFIG. 5cthe program code next causes the pair of execution lanes to shift the data within the shift register array one unit to the left which causes the value to the right of each execution lane's respective position to be shifted into each execution lane’ position. The value in R1(previous value) is then added with the new value that has shifted into the execution lane's position (in R2). The resultant is written into R1. As observed inFIG. 5dthe same process as described above forFIG. 5cis repeated which causes the resultant R1to now include the value A+B+C in the upper execution lane and F+G+H in the lower execution lane. At this point both execution lanes have processed the upper row of their respective stencils. Note the spill-over into a halo region on the left side of the execution lane array (if one exists on the left hand side) or into random access memory if a halo region does not exist on the left hand side of the execution lane array.

As observed inFIG. 5e, the program code next causes the data within the shift register array to shift one unit up which causes both execution lanes to be aligned with the right edge of the middle row of their respective stencils. Register R1of both execution lanes currently includes the summation of the stencil's top row and the middle row's rightmost value.FIGS. 5fand 5gdemonstrate continued progress moving leftwise across the middle row of both execution lane's stencils. The accumulative addition continues such that at the end of processing ofFIG. 5gboth execution lanes include the summation of the values of the top row and the middle row of their respective stencils.

FIG. 5hshows another shift to align each execution lane with its corresponding stencil's lowest row.FIGS. 5iand 5jshow continued shifting to complete processing over the course of both execution lanes' stencils.FIG. 5kshows additional shifting to align each execution lane with its correct position in the data array and write the resultant thereto.

In the example ofFIGS. 5a-5knote that the object code for the shift operations may include an instruction format that identifies the direction and magnitude of the shift expressed in (X, Y) coordinates. For example, the object code for a shift up by one location may be expressed in object code as SHIFT 0, +1. As another example, a shift to the right by one location may expressed in object code as SHIFT +1, 0. In various embodiments shifts of larger magnitude may also be specified in object code (e.g., SHIFT 0, +2). Here, if the 2D shift register hardware only supports shifts by one location per cycle, the instruction may be interpreted by the machine to require multiple cycle execution, or, the 2D shift register hardware may be designed to support shifts by more than one location per cycle. Embodiments of the later are described in more detail further below.

FIG. 6shows another, more detailed depiction of the unit cell for the array execution lane and shift register structure (registers in the halo region do not include a corresponding execution lane). The execution lane and the register space associated with each location in the execution lane array is, in an embodiment, implemented by instantiating the circuitry observed inFIG. 6at each node of the execution lane array. As observed inFIG. 6, the unit cell includes a execution lane601coupled to a register file602consisting of four registers R2through R5. During any cycle, the execution lane601may read from or write to any of registers R1through R5. For instructions requiring two input operands the execution lane may retrieve both of operands from any of R1through R5.

In an embodiment, the two dimensional shift register structure is implemented by permitting, during a single cycle, the contents of any of (only) one of registers R2through R4to be shifted “out” to one of its neighbor's register files through output multiplexer603, and, having the contents of any of (only) one of registers R2through R4replaced with content that is shifted “in” from a corresponding one if its neighbors through input multiplexers604such that shifts between neighbors are in a same direction (e.g., all execution lanes shift left, all execution lanes shift right, etc.). Although it may be common for a same register to have its contents shifted out and replaced with content that is shifted in on a same cycle, the multiplexer arrangement603,604permits for different shift source and shift target registers within a same register file during a same cycle.

As depicted inFIG. 6note that during a shift sequence a execution lane will shift content out from its register file602to each of its left, right, top and bottom neighbors. In conjunction with the same shift sequence, the execution lane will also shift content into its register file from a particular one of its left, right, top and bottom neighbors. Again, the shift out target and shift in source should be consistent with a same shift direction for all execution lanes (e.g., if the shift out is to the right neighbor, the shift in should be from the left neighbor).

Although in one embodiment the content of only one register is permitted to be shifted per execution lane per cycle, other embodiments may permit the content of more than one register to be shifted in/out. For example, the content of two registers may be shifted out/in during a same cycle if a second instance of the multiplexer circuitry603,604observed inFIG. 6is incorporated into the design ofFIG. 6. Of course, in embodiments where the content of only one register is permitted to be shifted per cycle, shifts from multiple registers may take place between mathematical operations by consuming more clock cycles for shifts between mathematical operations (e.g., the contents of two registers may be shifted between math ops by consuming two shift ops between the math ops).

If less than all the content of a execution lane's register files are shifted out during a shift sequence note that the content of the non shifted out registers of each execution lane remain in place (do not shift). As such, any non shifted content that is not replaced with shifted in content persists local to the execution lane across the shifting cycle. The memory unit (“M”) observed in each execution lane is used to load/store data from/to the random access memory space that is associated with the execution lane's row and/or column within the execution lane array. Here, the M unit acts as a standard M unit in that it is often used to load/store data that cannot be loaded/stored from/to the execution lane's own register space. In various embodiments, the primary operation of the M unit is to write data from a local register into memory, and, read data from memory and write it into a local register.

With respect to the ISA opcodes supported by the ALU unit of the hardware execution lane601, in various embodiments, the mathematical opcodes supported by the hardware ALU are integrally tied with (e.g., substantially the same as) the mathematical opcodes supported by a virtual execution lane (e.g., ADD, SUB, MOV, MUL, MAD, ABS, DIV, SHL, SHR, MIN/MAX, SEL, AND, OR, XOR, NOT). As described just above, memory access instructions can be executed by the execution lane601to fetch/store data from/to their associated random access memory. Additionally the hardware execution lane601supports shift op instructions (right, left, up, down) to shift data within the two dimensional shift register structure. As described above, program control instructions are largely executed by the scalar processor of the stencil processor.

c. Configuration of Image Processor and Line Buffer Unit Operation

FIG. 7shows a high level view of an image processor technology platform that includes a virtual image processing environment701, the actual image processing hardware703and a compiler702for translating higher level code written for the virtual processing environment701to object code that the actual hardware703physically executes. As described in more detail below, the virtual processing environment701is widely versatile in terms of the applications that can be developed and is tailored for easy visualization of an application's constituent processes. Upon completion of the program code development effort by the developer704, the compiler702translates the code that was written within the virtual processing environment701into object code that is targeted for the actual hardware703.

In various embodiments, program code that is written for the hardware platform is written with a unique virtual code that includes an instruction set having load and store instructions whose instruction format identifies input and output array locations as, e.g., X,Y coordinates. In various implementations, the X,Y coordinate information may actually be programmed into the hardware platform and recognized/understood by various ones of its components. This stands apart from, for example, translating the X,Y coordination (e.g., within the compiler) into different information. For example, in the case of the two-dimensional shift register structure within the stencil processor, the X,Y coordinate information is translated into register shift movements. By contrast, other parts of the hardware platform may specifically receive and comprehend the X,Y coordinate information originally expressed at the higher, virtual code level.

As observed inFIG. 8, a program code developer expresses data locations as X,Y coordinates with the special instruction format at the virtual code level801. During the compilation stage, the virtual code is translated into program code that is actually processed by the hardware (object code) and corresponding configuration information that is loaded into the hardware's configuration (e.g., register) space. As observed inFIG. 8, in an embodiment, the object code for a particular kernel is loaded into the program space of the stencil processor's scalar processor805.

As part of the configuration process, configuration software executing on the scalar processor805loads the appropriate configuration information811,812into both the sheet generator unit803that is coupled to the stencil processor802, and, the line buffer unit801that will generate new sheets for the stencil processor802to operate on, or, receive processed sheets generated by the stencil processor802. Here, generally, sheets can still be contemplated in terms of X,Y coordinates of an overall image. That is, once an image or frame is defined (e.g., in terms of number of pixels per row, number of rows, number of pixels per column and number of columns), any portion or position of the image can still be referred to with X,Y coordinates.

As such, in various embodiments, either or both of the sheet generator unit803and line buffer unit801are configured with information811,812within their respective configuration space806,807that establishes an informational platform from which specific locations and/or regions (e.g., line groups, sheets) of an image or frame are identified in X,Y coordinates. In various implementations/uses, the X,Y coordinates may be the same X,Y coordinates expressed at the virtual code level.

Examples of such information include, e.g., the number of active line groups in the line buffer unit, the image size for each line group (e.g., as a set of four X, Y coordinates (one for each corner) or a pair of X, Y coordinates (one for a lower nearer corner and one for an upper farther corner) or absolute image width and image height, stencil size (expressed as X, Y values that define the size of a single stencil and/or the area of the overlapping stencils of the stencil processor), sheet and/or line group size (e.g., specified in same terms as an image size but having smaller dimensions), etc. Additionally, the line buffer unit701at least may be programmed with additional configuration information such as the number of producer kernels writing and the number of consumer kernels reading the line groups that are managed by the line buffer unit801. The number of channels and/or the dimensions associated with the image data are also typically included as configuration information.

FIG. 9adepicts the use of X,Y coordinates to define, as just one example, line groups within an image. Here, N line groups901_1,901_2, . . .901_N are observable within an image901. As can be seen fromFIG. 9a, each line group can be readily defined by reference to X, Y coordinates within the image that define, e.g., one or more of a line group's corner points. As such, in various embodiments, a line group's name or other data structure used to define a particular line group may include X, Y coordinate locations associated with the line group in order to particularly identify it.

Referring briefly back toFIG. 8, note thatFIG. 8shows that during runtime, a sheet generator803may request a “next” line group (or portion of a line group) from the line buffer unit801by, e.g., including X, Y coordinate information that defines the desired data region.FIG. 9ashows nominal “full width” line groups composed only of complete rows of image data. In an alternative configuration referred to as “virtually-tall”, the line buffer unit801initially passes only a first upper portion of a line group as full width rows of image data. The subsequent lower rows of the line group are then specifically requested for by the sheet generator in contiguous chunks that are less than a full width row and are separately requested for. As such, multiple requests are made by the sheet generator in order to obtain the full line group. Here, each such request may define a next portion by X, Y coordinates that are attributable to the next portion.

As observed inFIG. 9b, a line buffer unit includes memory901in which line groups902_1through902_N are stored (e.g., static or dynamic random access memory (SRAM or DRAM)). The memory901may be implemented on chip along with the same circuitry that implements the line buffer unit (and, e.g., the sheet generators and stencil processors), or, off chip.FIG. 9bshows the activity between the various kernels that produce and consume the line groups902_1through902_N for a particular image/frame within the memory901.

As observed inFIG. 9b, a producer kernel K1sends new line groups to the line buffer unit901for storage in memory901over separate time instances P1, P2through PN. The producer kernel K1executes on a stencil processor that generates new sheets of data. The sheet generator that is coupled to the stencil processor accumulates sheets to form line groups and forwards the line groups to the line buffer unit which stores them in memory.

Also as depicted inFIG. 9b, there are two consumer kernels K2, K3that operate on the line groups902_1through902_N generated by producer kernel K1. Here, consumer kernels K2and K3receive the first line group902_1at times C21and C31, respectively. Obviously, times C21and C31occur after time P1. Other restrictions may not exist. For example times C21and/or C31may occur before or after any of times P2through PN. Here, the respective sheet generators for kernels K2and K3request a next line group at a time that is appropriate for their respective kernel. If any of kernels K2, K3request line group902_1before time P1, the request idles until after line group902_1is actually written into memory901.

Conceivably, requests from either or both of kernels K2and K3for all of line groups902_1through902_N may arrive prior to time P1. Thus, line groups may be requested by consumer kernels at any time. The line groups are forwarded to the consumer kernels as they request them subject, however, to the rate at which the producer kernel K1can produce them. In various embodiments, consumer kernels request line groups in sequence and likewise receive them in sequence (kernel K2receives line groups902_2through902_N at times C22through C2N in sequence). For simplicity only one producer kernel is depicted for a particular line group. It is conceivable that various embodiments may be designed to permit different producers to write to a same line group (e.g., where consumers are not permitted to be serviced until after all producers have written to the line group).

In cases where there is no producer kernel (because the consumer kernel(s) is/are the first kernels in the processor's DAG processing flow), frames of image data may be transferred into memory901(e.g., via direct memory access (DMA) or from a camera) and parsed into line groups. In cases where there are no consumer kernel(s) (because the producer kernel is the last kernel in the processor's overall program flow), resultant line groups may be combined to form output frames.

d. Application and Structure of Kernels

FIG. 10ashows an example of the structure and form that application software written within the virtual environment may take. As observed inFIG. 10a, the program code may be expected to process one or more frames of input image data1001to effect some overall transformation on the input image data1001. The transformation is realized with the operation of one or more kernels of program code1002that operate on the input image data in an orchestrated sequence articulated by the developer.

For example, as observed inFIG. 10a, the overall transformation is effected by first processing each input image with a first kernel K1. The output images produced by kernel K1are then operated on by kernel K2. Each of the output images produced by kernel K2are then operated on by kernel K3_1or K3_2, The output images produced by kernel(s) K3_1/K3_2are then operated on by kernel K4. Kernels K3_1and K3_2may be identical kernels designed to speed-up the overall processing by imposing parallel processing at the K3stage, or, may be different kernels (e.g., kernel K3_1operates on input images of a first specific type and kernel K3_2operates on input images of a second, different type).

As such, the larger overall image processing sequence may take the form of a image processing pipeline or a directed acyclic graph (DAG) and the development environment may be equipped to actually present the developer with a representation of the program code being developed as such (here, a pipeline is understood to be a form of a DAG). Kernels may be developed by a developer individually and/or may be provided by an entity that supplies any underlying technology (such as the actual signal processor hardware and/or a design thereof) and/or by a third party (e.g., a vendor of kernel software written for the development environment). As such, it is expected that a nominal development environment will include a “library” of kernels that developers are free to “hook-up” in various ways to affect the overall flow of their larger development effort. Some basic kernels that are expected to be part of such a library may include kernels to provide any one or more of the following basic image processing tasks: convolutions, denoising, color space conversions, edge and corner detection, sharpening, white balance, gamma correction, tone mapping, matrix multiply, image registration, pyramid construction, wavelet transformation, block-wise discrete cosine and Fourier transformations.

As discussed above, in various embodiments, each kernel runs on its own stencil processor. For example, referring toFIG. 10a, kernel K1runs on a first stencil processor, kernel K2runs on a second stencil processor, etc. Additionally, as discussed above, producing and consuming kernels interface through line buffer units.

FIG. 10bdepicts how the image processor could be configured to implement the DAG flow ofFIG. 10a. As observed inFIG. 10bline buffer unit1001_1(LBU_1) receives the input image stream and parses the received frames into line groups. The switching network is configured to route line groups from LBU_1to a first stencil processor1002_1upon which kernel K1executes. Output images from kernel K1are formatted into line groups and forwarded to a second line buffer unit1001_2(LBU_2). These line groups are then forwarded to a second stencil processor upon which kernel K2executes.

FromFIG. 10a, image information can be “split” from kernel K2into either of kernels K3_1or K3_2. Here, for instance, kernels K3_1and K3_2may process different channels associated with the overall image being processed. For example, kernel K3_1may process red (R) images while kernel K3_2may process green (G) and blue (B) images. Alternatively, K3_1may process visual images while kernel K3_2may process depth images (e.g., taken from a time-of-flight depth imaging camera along with the visual images). Regardless, all channels of the image are processed by kernels K1and K2but different channels of the image are processed with different kernels K3_1and K3_2. Further still, kernels K3_1and K3_2may be separate instances of the same (e.g., extremely numerically intensive) program code and two stencil processors are used to speed-up the processing of the K3function by executing it in parallel.

Regardless, the aforementioned “split” causes some line group image information from kernel K2to be buffered into a third line buffer unit1001_3(LBU_3) and other line group image information from kernel K2to be buffered into a fourth line buffer unit1001_4(LBU_4). The line groups that are buffered in the LBU_3line buffer unit are forwarded to a third stencil processor1002_3on which kernel K3_1executes. The line groups that are buffered in the LBU_4line buffer unit are forwarded to a fourth stencil processor1002_4on which kernel K3_2executes. Output line groups from kernels K3_1and K3_2are respectively buffered in fifth and sixth line buffer units1001_4(LBU_5),1001_5(LBU_6). The line groups from the LBU_5and LBU_6line buffer units are then passed to a fifth stencil processor1002_5that executes kernel K4. Note that the split line groups merge again at the fifth stencil processor1002_5.

FIGS. 11aand 11bpertain to a more straightforward pipelined approach where each stencil processor receives a line group from an immediately preceding stage and provides a for an immediately following stage. Specifically, line buffer units1101_1(LBU_1),1101_2(LBU_2),1101_3(LBU_3),1101_4(LBU_4) respectively feed stencil processors1102_1,1102_2,1102_3,1102_4that respectively execute kernels K1, K2, K3and K4. Stencil processors1102_1,1102_2,1102_3,1102_4also respectively feed line buffer units1101_2(LBU_2),1101_3(LBU_3),1101_4(LBU_4),1101_5(LBU_5).

FIG. 11cshows another pipelined approach that essentially executes two pipelines in parallel (K1-K3- . . . ) and (K2-K4- . . . ). This configuration can be used to speed up a pipeline through parallel execution (e.g., kernels K1and K2are the same, and, kernels K3and K4are the same), or, two different pipelines are used depending on image data context (e.g., one pipeline processes one kind of channel and the other pipeline processes the other kind of channel).

In each ofFIGS. 11a, 11band 11cnote the different configurations that will need to be made to the connection network1004/1104to connect the stencil processors to the source and sink line groups in the appropriate manner.

In various embodiments, the image processor includes appropriate configuration space (e.g., implemented with configuration registers and/or random access memory (such as the scalar processor's scalar memory)) in which to keep configuration information to implement any of a myriad of various configurations (e.g., DAG, image processing pipeline). Some exemplary configuration parameters include: 1) Number of Source Images (the number of source image frames that are streamed into the system, from e.g., either a camera or a larger computer system's main memory); 2) Number of Line groups (the total number of line groups configured for within the line buffer units in the system); 3) Number of Active Stencil Processors (the total number of active stencil processors in the system); 4) Number of Input Line Groups Per Stencil Processor (one stencil processor can handle more than one input image frame, Num_Input_LGs_perStencil essentially indicates how many different input image frames the stencil processor will handle); 5) Number of Output Line Groups Per Stencil Processor (one stencil processor can handle more than one output image frame, Num_Output_LGs_perStencil essentially indicates how many different output image frames the stencil processor will handle); 6) Number of Consumers Per Line Group (for each line group configured for in each line buffer unit, Num_Cons_per_LG indicates how many consumers the line group has). Other types of configuration information may be accepted by the system based on any of the features, structures or operations of the system described above.

e. Automated DAG/Pipeline Code Restructuring Processes

With the aforementioned basic principles of image processor configuration and operation being described in the preceding sections, the present section describes certain restructuring processes that a compiler may perform to a DAG of kernels to effect more efficient overall implementation of the DAG. As alluded to above, a pipeline is understood to be a form of DAG.

Here, the compiler may be programmed to recognize certain inefficient or otherwise problematic DAG structures and automatically re-structure the DAG to reduce the inefficiency and/or eliminate the problem. In various embodiments, a software program development tool may permit a program developer to provide hints that a compiler can use to perform one or more transformations to the program code, described further below, to address the inefficiencies.

Examples of inefficiencies or problems in a DAG that may be detected and responded to by the compiler include (but are not limited to): 1) a kernel that is particularly more computationally complex as compared to other kernels in the DAG; 2) a DAG that contains more or fewer kernels than stencil processors in the image processor; 3) limited line buffer unit memory space and/or limited instruction memory space.FIGS. 12a/b/cthroughFIG. 16describe some of the possible restructurings that a compiler may be designed to implement in response to these inefficiencies/problems.

FIGS. 12aand 12bare directed to “horizontal fusion” code restructuring. In the case of horizontal fusion, as observed inFIG. 12amultiple kernels of a DAG, e.g., that each flow from a same kernel, are merged into a single kernel. Here,FIG. 12ashows an original code sequence1201having separate K2and K3kernels. After restructuring by the compiler, a new code sequence1202is created in which kernels K2and K3are combined into a single kernel K2/K3.

Horizontal fusion may be performed by a compiler in response to, e.g., the existence of smaller kernels in the DAG/pipeline as compared to other kernels. Here, the fusion of the kernels will produce a larger kernel that is more comparable in size/computational intensity to the other kernels. Alternatively or in combination the compiler may perform horizontal fusion in response to there being more kernels in the original DAG than stencil processors. Here, the fusion will reduce the total number of kernels in the DAG (ideally, so as to no longer exceed the number of stencil processors in the image processor).

In various embodiments, horizontal fusion merges the program code of multiple kernels that are independent of one another (e.g., of two kernels being merged, a first kernel does not accept as an input information generated by a second kernel). Additionally, horizontally fused kernels may accept input information from a same kernel and/or provide output information that is consumed by a same kernel. The former is illustrated inFIG. 12awhere fused kernels K2and K3both accept input information from kernel K1.

FIG. 12bshows an embodiment of the implementation of horizontal fusion. Here, the newly constructed K2/K3kernel is designed as a concatenation of the kernels being fused. That is, in the embodiment ofFIG. 12b, new kernel K2/K3is composed of the program code for kernel K3which begins execution just after the program code for kernel K2executes1203. Notably, new kernel K2/K3accepts the same input information as the combination of kernels K2and K3and provides the same output information as the combination of kernels K2and K3. Again, the inputs may be received from same or different line buffer units and the outputs may provide their respective outputs to same or different line buffer units.

Here, referring toFIG. 12aif kernel K1generates line buffer data for two different line buffer units (a first line buffer unit that feeds K2and a second line buffer unit that feeds K3) no change in the program flow is needed (the K2portion of kernel K2/K3reads from the line buffer unit that produces for K2, and, the K3portion of kernel K2/K3reads from the line buffer that produces for K3). If both kernels K2and K3are consumers of the same data from kernel K1(i.e., kernel K1only writes to one line buffer unit and both K2and K3read from that line buffer unit), again no change in the program's data flow is needed. In this case both the K2and K3portions of kernel K2/K3consume from the same line buffer unit. A similar analogy applies for the output line buffer unit(s) of kernel K2/K3.

In various embodiments the compiler should be conscious of the spatial rates (pixels processed per kernel invocation) that fused kernels operate according to. Here, the kernels being fused may not necessarily operate at the same rate as originally written. For example, owing to differences in image resolution, they may not consume the same number of cycles in performing their respective algorithms. For instance, a down sampling kernel may have to operate over a wider image area requiring more two-dimensional shift register shift operations than another kernel that does not down sample.

As a consequence the down sampling kernel consumes more invocations before it completes than the kernel that does not down sample. For instance the down sampling kernel may consume 16 cycles before it completes while the non down sampling kernel may only consume 4 cycles before it completes. The difference in completion rates can cause timing problems with the line buffer unit which expects cycles per completion to be constant over the run length of an entire kernel. The compiler therefore modifies the code of the kernel(s) so that they consume approximately a same number of cycles to fully execute their respective algorithms. By so-doing, the line buffer is spared having to adjust to a dramatically different kernel algorithm completion rate during mid-kernel execution.

Therefore, in an embodiment, the compiler adds one or more loops to a kernel that consumes fewer cycles per completion to cause the kernel to, e.g., consume a same number of cycles per completion as a kernel that consumes more cycles per completion. For instance, in the aforementioned example, the non-downsampling kernel will be modified to run through four loops of its algorithm before it completes. Although four times the data is created by the modified kernel as compared to its original version for one execution run, the modified kernel will consume 16 cycles before it completes which is the same as the downsampling kernel. Conceivably the compiler may modify the rates of more than one kernel to reach a common dominator of cycles that all kernels can match rates to.

FIGS. 13athrough 13cpertain to vertical fusion. In the case of vertical fusion, as observed inFIG. 13a, a producer/consumer relationship exists between kernels being fused. For example, as observed inFIG. 13a, kernel K1is a producer for kernel K2(kernel K2is a consumer of kernel K1). After restructuring by the kernel, a new kernel K1/K2is generated that performs the function of fused kernels K1and K2.

FIG. 13bshows the construction of the new kernel. Here, the consuming kernel K2is concatenated after kernel K1to effect the correct producer/consumer relationship. The input for new kernel K1/K2corresponds to the input for kernel K1and the output of new kernel K1/K2corresponds to the output of kernel K2. The compiler may decide to impose vertical fusion, e.g., in response to the kernels being fused being less computationally complex than other kernels in the DAG and/or there being more kernels in the DAG than stencil processors within the image processor.

An issue may arise in the case of vertical fusion if a consuming kernel portion of a vertically fused kernel needs the halo region to perform its task(s). Recall from the discussion ofFIG. 4above that in various embodiments the dimensions of the two dimensional shift register within a stencil processor may accommodate a halo region409that extends outside the area where output pixel values are stored.

Here, if the consuming kernel portion of a vertically fused kernel needs content in the halo region it cannot immediately operate on the output of the producing kernel portion. That is, the output data generated by a producer will keep “beneath” the execution lanes and will not extend into the halo region. If the consuming kernel portion needs image data in the halo region, the halo data will not be available if the consuming kernel portion begins operation on an output resultant from the producer portion immediately after it is generated.

A solution is to delay the start of the consuming kernel portion to ensure that the halo region data has been generated by the producer kernel portion by the time the consuming kernel begins operation.FIG. 13cshows an exemplary depiction of the solution. Here, bordered region1301corresponds to the execution lane area of the producer kernel portion and bordered region1302corresponds to the halo region that resides outside the producer kernel portion's execution lane area1301.

By contrast, bordered region1303corresponds to the execution lane area that the consuming kernel portion is operating on after the producer kernel portion has generated the output within region1301. Bordered region1304corresponds to the halo region that resides around the execution lane area1303of the consumer kernel portion.FIG. 13cassumes stencil processing operates on sheets in a left to right fashion along a same row of sheets until processing for the row of sheets is complete at which time processing will commence for the next row of sheets.

The offset or phase difference that exists between regions1301and1303can be deliberately imposed by delaying the start of the consuming kernel portion until output is produced by the producing kernel portion that is available to the consuming kernel portion and has the relative positioning offset observed inFIG. 13c. Notably, with this offset, the image data output that has been generated by the producer kernel and is available to the consuming kernel portion “fills” not only the execution lane area1303of the consuming kernel portion but also its halo region1304as well. As such, the consuming kernel portion has the data it needs to properly calculate output values for region1303and concatenated operation of K1followed by K2before a next run of K1is attempted is permissible.

In a nominal embodiment, a producer kernel writes its output data to a line buffer unit and the consuming kernel reads the data from the same line buffer unit. However, as a consequence of the producing and consuming kernel portions now being fused and executed on the same stencil processor, output data generated by the producing kernel portion may remain local to the stencil processor (e.g., within stencil processor RAM407and/or sheet generator memory) rather than being written back to the line buffer unit. As such, rather than read data from a line buffer unit, the consuming kernel portion instead reads the output data from the memory that is local to the stencil processor.

Thus, entire write/read sequences between a stencil processor and a line buffer unit can be avoided. In embodiments where there are other consumers of the producing kernel portion's output that were not fused with the producing kernel portion, the producing kernel portion's output is externally written to a line buffer unit so the external consuming kernels can receive the producer's data.

FIG. 13calso show that, for similar reasons, the dimensions of the image data that are actually processed by the stencil processor exceed the dimensions of the image being processed. Specifically, additional spatial regions1305,1306are processed over by the producer kernel portion so that the producer kernel portion can generate halo data needed by the consumer kernel portion.

FIG. 14depicts another restricting that may be referred to as a “fission split”. In the case of a fission split, a larger kernel is broken down into multiple smaller kernels. For example, as observed inFIG. 14, a large initial kernel K having sub-graphs A through F is broken down into two kernels K1and K2where new kernel K1includes sub-graphs A through D and new kernel K2contains sub graphs E and F. A fission split may be imposed by a compiler, e.g., if the kernel being split K is more computationally intense than the other kernels in the DAG and/or its instruction footprint is too large to fit into stencil processor instruction memory.

As part of the restructuring, note that “store_sheet” commands/instructions and “load_sheet” commands/instructions are newly inserted into the overall code at the juncture where the larger kernel code was split. Specifically, observing from the example ofFIG. 14that the larger kernel K is split at juncture1401, note that the output of sub graph D is modified to store a sheet of information and the input of sub graph E is modified to load a sheet of information.

As discussed at length above, owing to the existence of the two-dimensional shift register array within a stencil processor, a sheet of image data is the basic input data structure and output data structure for a kernel. As such, before a kernel can operate on a sheet of data it must first load the sheet of data into the two-dimensional register space of the stencil processor. Likewise, when a kernel has finished one execution of its core algorithm it writes its output sheet of data from the two dimensional shift register into stencil processor RAM and/or sheet generator RAM.

Consistent with these basic data structure requirements, part of imposing a fission split is a newly created kernel output (output of sub graph D inFIG. 14) and a newly created kernel input (input of sub graph E inFIG. 14). The former requires a store sheet command to write a sheet of output data from the two-dimensional shift register array while the former requires a load sheet command to read a sheet of input data into the two-dimensional shift register array. Note that the Store_Sheet and Load_Sheet commands also correspond to communication between a kernel and a line buffer unit (line buffers are composed of multiple sheets). As such whereas before fission sub graph D did not directly feed a line buffer unit, after fission it does. Likewise, whereas before fission sub graph E did not directly receive from a line buffer unit, after fusion it will.

In an embodiment, the compiler is designed to impose the split juncture1401in a region or the larger kernel K such that the newly created separate kernels K1, K2will be approximately equal in size/computational intensity. In some instances this may cause the compiler to impose the split juncture1401through an iterative loop. For example, sub graphs D and E may implement a loop where program flow flows from sub graph E back to sub graph D until the loop completes.

In the case where the split juncture1401cuts through a loop, the compiler additionally modifies program code so that the loop itself is split. Here, note that the fission split1401observed inFIG. 14essentially creates new kernels having a producer/consumer relationship. That is, newly created kernel K2reads line buffers created by kernel K1from a line buffer unit that kernel K1writes it output line buffers into. As such, the leading iterations of the loop are performed by K1and the trailing iterations of the loop are performed by K2.

In another embodiment, the compiler does not attempt to split loops that have a data dependency between previous iterations and next iterations and instead keeps the entirety of a loop within a same kernel. As such, the presence of loops can affect where the compiler chooses to impose the split juncture1401(around them instead of through them).

FIG. 15depicts another compiler restructuring process referred to as “spatial partitioning”. As observed inFIG. 15, spatial partitioning entails duplicating a kernel that was originally designed to operate on a larger image into multiple kernels of same core algorithm that are designed to operate on only a portion of the image.

Here, in the exemplary depiction ofFIG. 15, original kernel K1is designed to operate on entire image1501. The compiler essentially duplicates kernel K1so that the DAG includes two instances of K1's code K1_1and K1_2. The compiler further modifies the base K1code of the newly created kernels to only refer to the portion of the image that they are supposed to process. In the example ofFIG. 15, kernel K1_1only operates on the left half1501_1of image1501and kernel K1_2only operates on the right half1501_2of image1501.

As such, the compiler will reconstruct the kernel code of kernel K1_1to only request line buffer data that resides within the left half1501_1of image1501and will reconstruct the code of kernel K1_2to only request line buffer data that resides within the right half1501_2of image1501. Recalling that kernel software can request a line buffer by referring to it by its X, Y coordinates, in various embodiments the compiler's reconstructions of kernels K1and K2entail reformatting the line buffer requests to specify coordinates that correspond to the portion of the image that the kernel is supposed to process.

For example, kernel K1_1will avoid requesting coordinates that span across the width of the entire image and instead request a next lower row of image data once the input line buffer data has been received that is sufficient to process the left half1501_1of the image. Likewise, when starting a next lower row of line buffer data to process, kernel K1_2will have an X axis offset that corresponds to half the image (e.g., instead of asking for a next lower line buffer at coordinate 0,Y the kernel will request a next lower line buffer at coordinate W/2,Y where W is the width of the entire image1501along the X axis).

Other image partition arrangements are possible according to the aforementioned principles of tweaking the coordinate values of the requested line buffer data.

In a typical embodiment, the original kernel K1was designed to read the entire image from a single line buffer unit and write its output data into another single line buffer unit. After the spatial partitioning, both of kernels K1_1and K1_2may refer to the single source line buffer unit where the image data resides (or the producer kernel of the input image for kernels K1_1, K1_2may be reconfigured to write two copies of the image in two separate line buffer units that kernels K1_1and K1_2read from separately). As observed inFIG. 15, however, in an embodiment, each of kernels K1_1and K1_2write their output data to two separate line buffer units LB_1and LB_2.

In an embodiment this restriction is imposed because, as mentioned above with respect toFIGS. 9aand 9b, a line buffer unit can serve multiple consumers but can only handle one producer. A such, a single line buffer unit cannot handle the output from both of kernels K1_1and K1_2(each kernel must write to its own line buffer unit). Thus, as observed inFIG. 15, consuming kernel K2is also reconfigured as part of the spatial partitioning restructure to read the image data it desires for the two different halves of the image from two different line buffer units (LB_1keeps left hand side image data and LB_2keeps right hand side image data). That is, kernel K2is restructured to issue a request to LB_1if it desires left hand side image and issue a request to LB_2if ti desires right hand side image data. K2may also be restructured to merge image halves into a single image if, e.g., the algorithm of K2operates on a whole image.

FIG. 16pertains to another code restructuring process referred to as “graph splitting”. In the case of graph splitting, the amount of data that is processed by the DAG exceeds the internal memory requirements of the image processor. As such, the DAG has to be split into multiple DAGs each of which process an amount of data that is within the internal storage space limits of the image processor. Here, in various embodiments, the line buffer units, the sheet generators and the stencil processors each have associated memory. If the storage requirements of a single DAG exceed the capacity of one or more of these memories, multiple DAGs are created.

An example is observed inFIG. 16in which a DAG1608is created whose purpose is to repeatedly down sample a very large input image1601into a much smaller lower density output image1607. The DAG/pipeline1608is composed of six kernels K1through K6each of which down sample a larger input image into a smaller output image (e.g., kernel K1down samples larger input image1601into smaller image1602, kernel K2down samples image1602into smaller image1603, kernel K3down samples image1603into smaller image1604, etc.

In an implementation where, e.g., the initial input image1601is extremely large it may not be possible to fit all the data/instructions/context into the internal memory space of the image processor. As such, in response, the compiler will analyze the memory resource demands of kernels K1through K6and parse the initial larger DAG/pipeline1608into a group of smaller DAGs/pipelines1609,1610,1611that are to operate in sequence and each of which do not require more internal memory resources than is available within the image processor.

Recall from the discussion ofFIG. 1that a DAG commences with the loading of input data from external memory into the line buffer unit(s) and closes with the writing of output data from the line buffer unit(s) into external memory. The initial DAG/pipeline1608ofFIG. 16therefore included commands/instructions to transfer input data from external memory into the line buffer unit(s) at the input to kernel K1and also included commands/instructions to transfer output data from the line buffer unit(s) to external memory at the output of kernel K6.

After the compiler parses the original larger DAG/pipeline1608into smaller DAG/pipelines1609,1610,1611, the compiler will additionally insert commands/instructions to load input data from external memory into the line buffer unit(s) at the inputs of kernels K2and K4(i.e., at the input of new smaller DAG/pipelines1610and1611). The compiler will also insert commands/instructions to load output data from the line buffer unit(s) into external memory at the outputs of kernels K1and K3(i.e., at the output of new smaller DAG/pipelines1609and1610). Note that where these insertions of new commands/instructions are located, the original DAG/pipeline1608specified the writing/reading of data to/from a line buffer unit rather than external memory (because kernels within a same DAG/pipeline feed/source one another through the line buffer units). As such these original commands/instructions will be removed by the compiler.

Note that various ones of the restructurings described may ultimately be performed in response to any of the inefficiencies discussed above. For instance, after a series of fusions the compiler may ultimately perform graph splitting.

In the aforementioned discussions note that kernels themselves may be large complex software routines composed of many branches and associated basic blocks of code when ultimately compiled into object code. As such, the sub-graphs within the kernels may also themselves be composed of multiple branches and basic blocks of object code when ultimately compiled into object code.

FIG. 17ashows a method performed, e.g., by a compiler, as discussed above. As observed inFIG. 17athe method includes1701compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures, the program code to implement a directed acyclic graph and being composed of multiple kernels that are to execute on respective ones of said stencil processors, wherein the compiling comprises any of: recognizing there are a different number of kernels in the program code than stencil processors in the image processor; recognizing that at least one of the kernels is more computationally intensive than another one of the kernels; recognizing that the program code has resource requirements that exceed the image processor's memory capacity. The method also includes1702in response to any of the aforementioned recognizing performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; splitting the directed acyclic graph into smaller graphs.

FIG. 17bdepicts an application software development and simulation environment1721that may be used with any of the aforementioned compiler processes when compiling program code for execution on an image processor such as an image processor having any of the hardware features discussed above. Here, a developer may develop a comprehensive image processing function (e.g., an image processing pipeline where each stage in the pipeline performs a dedicated image processing task, some other DAG prescribed set of routines, etc.) by arranging kernels in a strategic sequence that is consistent with the overall intended image transformation. Kernels may be called up from a library1722and/or the developer may develop one or more custom kernels.

Kernels within the library1722may be provided by a third party vendor of kernels and/or a provider of any underlying technology (e.g., a vendor of a hardware platform that includes the targeted hardware image processor or a vendor of the targeted hardware image processor (e.g., provided as a design thereof or as actual hardware)).

In the case of custom developed kernels, in many situations the developer need only write the program code for a single thread1723. That is, the developer need only write program code that determines a single output pixel value by referencing input pixel values relative to the output pixel location (e.g., with the aforementioned position relative memory access instruction format). Upon satisfaction of the operation of the single thread1723, the development environment may then automatically instantiate multiple instances of the thread code on a respective virtual processor to effect a kernel on an array of processors that operate on an image surface area. The image surface area may be a section of an image frame (such as a line group).

In various embodiments, the custom thread program code is written in the object code of the virtual processor ISA (or a higher level language that is compiled down to the virtual processor ISA object code). Simulation of execution of the custom kernel's program code may be performed in a simulated runtime environment that includes a virtual processor accessing a memory organized according to the memory model. Here, software models (object oriented or otherwise) of a virtual processor1724and a memory1725that incorporates the model are instantiated.

The virtual processor model1724then simulates execution of the thread code1723. Upon satisfaction of the performance of a thread, its larger kernel and any larger function that the kernel belongs to, the whole is compiled into the actual object code of the underlying hardware. The entirety of the simulation environment1721may be implemented as software that runs on a computer system (e.g., a workstation)1726.

It is pertinent to point out that the various image processor architecture features described above are not necessarily limited to image processing in the traditional sense and therefore may be applied to other applications that may (or may not) cause the image processor to be re-characterized. For example, if any of the various image processor architecture features described above were to be used in the creation and/or generation and/or rendering of animation as opposed to the processing of actual camera images, the image processor may be characterized as a graphics processing unit. Additionally, the image processor architectural features described above may be applied to other technical applications such as video processing, vision processing, image recognition and/or machine learning. Applied in this manner, the image processor may be integrated with (e.g., as a co-processor to) a more general purpose processor (e.g., that is or is part of a CPU of computing system), or, may be a stand alone processor within a computing system.

The hardware design embodiments discussed above may be embodied within a semiconductor chip and/or as a description of a circuit design for eventual targeting toward a semiconductor manufacturing process. In the case of the later, such circuit descriptions may take of the form of a (e.g., VHDL or Verilog) register transfer level (RTL) circuit description, a gate level circuit description, a transistor level circuit description or mask description or various combinations thereof. Circuit descriptions are typically embodied on a computer readable storage medium (such as a CD-ROM or other type of storage technology).

From the preceding sections is pertinent to recognize that an image processor as described above may be embodied in hardware on a computer system (e.g., as part of a handheld device's System on Chip (SOC) that processes data from the handheld device's camera). In cases where the image processor is embodied as a hardware circuit, note that the image data that is processed by the image processor may be received directly from a camera. Here, the image processor may be part of a discrete camera, or, part of a computing system having an integrated camera. In the case of the later the image data may be received directly from the camera or from the computing system's system memory (e.g., the camera sends its image data to system memory rather than the image processor). Note also that many of the features described in the preceding sections may be applicable to a graphics processor unit (which renders animation).

FIG. 18provides an exemplary depiction of a computing system. Many of the components of the computing system described below are applicable to a computing system having an integrated camera and associated image processor (e.g., a handheld device such as a smartphone or tablet computer). Those of ordinary skill will be able to easily delineate between the two. Additionally, the computing system ofFIG. 18also includes many features of a high performance computing system, such as a workstation used to implement the development environment discussed above with respect toFIG. 17c.

As observed inFIG. 18, the basic computing system may include a central processing unit1801(which may include, e.g., a plurality of general purpose processing cores1815_1through1215_N and a main memory controller1817disposed on a multi-core processor or applications processor), system memory1802, a display1803(e.g., touchscreen, flat-panel), a local wired point-to-point link (e.g., USB) interface1804, various network I/O functions1805(such as an Ethernet interface and/or cellular modem subsystem), a wireless local area network (e.g., WiFi) interface1806, a wireless point-to-point link (e.g., Bluetooth) interface1807and a Global Positioning System interface1808, various sensors1209_1through1809_N, one or more cameras1810, a battery1811, a power management control unit1812, a speaker and microphone1813and an audio coder/decoder1814.

An applications processor or multi-core processor1850may include one or more general purpose processing cores1815within its CPU1201, one or more graphical processing units1816, a memory management function1817(e.g., a memory controller), an I/O control function1818and an image processing unit1819. The general purpose processing cores1815typically execute the operating system and application software of the computing system. The graphics processing units1816typically execute graphics intensive functions to, e.g., generate graphics information that is presented on the display1803. The memory control function1817interfaces with the system memory1802to write/read data to/from system memory1802. The power management control unit1812generally controls the power consumption of the system1800.

The image processing unit1819may be implemented according to any of the image processing unit embodiments described at length above in the preceding sections. Alternatively or in combination, the IPU1819may be coupled to either or both of the GPU1816and CPU1801as a co-processor thereof. Additionally, in various embodiments, the GPU1816may be implemented with any of the image processor features described at length above.

Each of the touchscreen display1803, the communication interfaces1804-1807, the GPS interface1808, the sensors1809, the camera1810, and the speaker/microphone codec1813,1814all can be viewed as various forms of I/O (input and/or output) relative to the overall computing system including, where appropriate, an integrated peripheral device as well (e.g., the one or more cameras1810). Depending on implementation, various ones of these I/O components may be integrated on the applications processor/multi-core processor1850or may be located off the die or outside the package of the applications processor/multi-core processor1850.

In an embodiment one or more cameras1810includes a depth camera capable of measuring depth between the camera and an object in its field of view. Application software, operating system software, device driver software and/or firmware executing on a general purpose CPU core (or other functional block having an instruction execution pipeline to execute program code) of an applications processor or other processor may perform any of the functions described above.

Embodiments of the invention may include various processes as set forth above. The processes may be embodied in machine-executable instructions. The instructions can be used to cause a general-purpose or special-purpose processor to perform certain processes. Alternatively, these processes may be performed by specific hardware components that contain hardwired and/or programmable logic for performing the processes, or by any combination of programmed computer components and custom hardware components.