Integrated circuit including semiconductor power device and electrically isolated thermal sensor

An integrated circuit (10) includes a thermal sensing device (20) and a power-switching device (12) such as an IGBT. The power device (12) is fabricated in a conventional manner on a semiconductor substrate, and the thermal sensing device (20) is fabricated on an electrical insulation layer (74) formed over the substrate. The thermal sensing device (20) may be provided in the form of a number of series-connected polysilicon diodes (D1-D3) positioned adjacent to the power device (12) such that the operating temperature of the thermal sensing device (20) is near that of the power device (12). In response to an input current IC, the thermal sensing device (20) produces an output voltage (VD) that is substantially linear with surface die temperature, and which reacts rapidly to changes in surface die temperature. The thermal sensing device (20) is completely electrically isolated from the power device, thereby eliminating any electrical interaction therebetween.

TECHNICAL FIELD

The present invention relates generally to semiconductor power devices, and more specifically to semiconductor power devices including a thermal sensing device operable to sense the power device operating temperature.

BACKGROUND OF THE INVENTION

Thermal considerations are invariably part of the design of any system using a power silicon switch, including DMOS (power MOSFET), insulated gate bipolar transistor (IGBT) or other power switches. Such devices are designed to sink or source large currents that generate electrical power resulting in elevated device temperatures. However, most silicon-based power devices have a limited maximum allowable operating temperature for reliable operation. It is therefore desirable to be able to accurately determine the operating temperature of such power devices so that suitable control circuitry can be employed to control power device operation in a manner that limits the maximum power device operating temperature to within safe operating limits.

SUMMARY OF THE INVENTION

The present invention comprises one or more of the following features or combinations thereof. A semiconductor integrated circuit including a power device fabricated on a semiconductor substrate, an electrical insulation layer formed over the semiconductor substrate, and a thermal sensing device fabricated on the electrical insulation layer and thereby electrically insulated from the power device, wherein the thermal sensing device is positioned adjacent to the power device and configured to produce a signal indicative of an operating temperature of the power device.

The thermal sensing device may include a diode structure responsive to an input current to produce the signal in the form of a voltage across the thermal sensing device having a substantially linear relationship to the operating temperature of the power device. For example, the voltage across the diode structure may decrease, substantially linearly, with increasing temperature. The diode structure may include a number of series-connected diodes each formed of polysilicon. Each of the number of series-connected polysilicon diodes may include a p-type polysilicon region forming a PN junction with an n-type polysilicon region.

The integrated circuit may include a transient-blocking semiconductor layer fabricated on the semiconductor substrate and positioned directly beneath the thermal sensing device, wherein the transient-blocking semiconductor layer is operable to shield the thermal sensing device from voltage transients occurring in the substrate.

The number of series-connected diodes may be arranged along a common axis to form an elongated diode row structure having a bottom surface in contact with the electrical insulation layer and four surrounding sides including a pair of elongated sides and a pair of short sides. Such a diode row structure may be arranged relative to the power device such that at least one of the pair of long sides is positioned adjacent to a heat-generating portion of the power device. The diode row structure may alternatively be arranged relative to the power device such that both of the pair of long sides are positioned adjacent to the heat-generating portion of the power device.

The power device may be an insulated gate bipolar transistor, MOS power transistor, or other power device.

These and other features of the present invention will become more apparent from the following description of the illustrative embodiments.

DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENTS

Referring now toFIG. 1, a schematic diagram is shown illustrating one embodiment of an integrated circuit10including a semiconductor power device12and a thermal sensing device20fabricated thereon. In the embodiment shown, the semiconductor power device12is illustrated as an insulated gate bipolar transistor (IGBT) of known construction and having a gate14defining a gate input, G, of circuit10, a collector16defining a collector input, C, of circuit10and an emitter18defining an emitter output, E, of circuit10. In one embodiment, the gate, G, and emitter, E, outputs of the IGBT are defined in a conventional manner on the top side of integrated circuit10, while the collector, C, output is defined as the substrate of integrated circuit10. In this embodiment, electrical contact to the collector, C, of the IGBT may accordingly be made to the backside of the integrated circuit10, as is known in the art. It is to be understood, however, that other output configurations for the gate, G, emitter, E, and collector, C, terminals of the IGBT are contemplated. Those skilled in the art will recognize that the semiconductor power device12may alternatively be, or include, other known semiconductor power switching devices. Examples of such alternative semiconductor power switching devices include, but are not limited to, metal oxide semiconductor (MOS) devices, including CMOS, DMOS and/or other known MOS variants, one or more bipolar power transistors, including Darlington transistor pairs, and the like.

The thermal sensing device20is configured to produce a signal indicative of the operating temperature of the power device12. Control circuitry (not shown) is responsive to the signal produced by the thermal sensing device20to monitor the operating temperature of the power device12, and to control the operation of the power device12as a function of this signal in a manner that limits its maximum operating temperature. While it is recognized that such control circuitry may take many forms, one embodiment of such control circuitry that is particularly suited for use with integrated circuit10is illustrated and described in co-pending U.S. patent application Ser. No. 10/287,033, entitled THERMAL OVERLOAD PROTECTION CIRCUIT FOR AN AUTOMOTIVE IGNITION SYSTEM, filed concurrently on Nov. 4, 2002, which is assigned to the assignee of the present invention, and the disclosure of which is expressly incorporated herein by reference.

In the embodiment illustrated inFIG. 1, the thermal sensing device20includes three series-connected diodes D1-D3, wherein an anode of D1is connected to a positive thermal voltage output, T+, and the cathode of D3is connected to a reference thermal voltage output, T−, of the integrated circuit10. Those skilled in the art will recognize that more or fewer diodes may be included in the diode string20illustrated inFIG. 1, and that the actual number of diodes used will typically result from one or more design considerations relating to the particular application of integrated circuit10. In any case, a current source, IC, external to integrated circuit10supplies an input current to the T+ input of integrated circuit10, such that a diode voltage, VD, is developed across the diode string between T+ and T−. The external current source, IC, may or may not be included with the control circuitry (not shown) operable to control the power device12as a function of the signal produced by the thermal sensing device20in a manner that limits its maximum operating temperature.

Polysilicon is a common material used for the internal gate layer of MOS devices, including, for example, power DMOS and IGBTs. It is also known that electrically functional diodes can be fabricated with polysilicon, and in one embodiment the thermal sensing device20is constructed from a string of polysilicon diodes formed on a dielectric layer disposed over, and electrically insulated from, the semiconductor power device12. Referring toFIG. 2, for example, a cross-sectional view of one embodiment of the integrated circuit10ofFIG. 1is shown illustrating construction of a portion of the semiconductor power device12in the form of an IGBT, and of the thermal sensing device20in the form of three series-connected polysilicon diodes. Integrated circuit10includes a P+ semiconductor substrate60upon which an N+ buffer layer62is grown or otherwise formed. An N-type epitaxial layer64is then grown or otherwise formed on the buffer layer60.

An electrical insulation layer74, e.g., SiO2, silicon nitride (Si3N4), polyimide, or the like, is grown or otherwise formed on the N-epitaxial layer64. Electrical insulation layer74, sometimes referred to as a “field oxide” layer, is selectively removed in areas that will contain active cells of the IGBT12, and gate oxide73is grown or otherwise formed in these areas. A layer of conductive gate material72, e.g., polysilicon, is deposited or otherwise formed on top of the gate oxide layer73, and layers72and73are then patterned to form the gate14of IGBT12, as shown in FIG.1.

A series of equally spaced apart P+ wells66(only one shown inFIG. 2for ease of illustration) are then diffused or implanted into the N-epitaxial layer64such that a portion of gate72and gate oxide73overlaps adjacent P+ wells66. During the P+ diffusion or implantation process, a P+ region70is diffused or implanted in a region of the N-epitaxial layer64under which the thermal sensing device20will be formed, and adjacent to the IGBT12. In one embodiment, as illustrated inFIG. 2, the P+ region70is merged into one or more of the P+ wells66forming part of the IGBT12. Within each of the P+ wells66, a pair of equally spaced-apart N+ wells68are diffused or implanted therein. The P+ well66and N+ well68pairs thus define a series of IGBT “cells” within the N-epitaxial layer64. In comparison withFIG. 1, collector16of IGBT12corresponds to P+ substrate60, gate14corresponds to gate areas72, and emitter18corresponds to the combination of P+ wells66and N+ wells68. With the exception of P+ well70, the foregoing IGBT structure has been described as being constructed in accordance with a known self-aligned gate process, although it should be understood that IGBT12may alternatively be constructed in accordance with any known semiconductor fabrication techniques.

On top of electrical insulation layer74above P+ well70, and therefore completely dielectrically isolated from IGBT12, thermal sensing device20is formed. Diodes D1, D2and D3are formed at the same time that the polysilicon gates72are formed by growing or otherwise forming three polysilicon regions above P+ well70. These polysilicon regions are then selectively masked and doped using conventional integrated circuit processes to form diodes each consisting of a P-type region76and an N-type region78. With the process illustrated and described with respect toFIG. 2, formation of diodes D1-D3requires no additional process steps or cost, as same the P+ diffusion or implant process used to form P+ wells66is also used to form the P-type polysilicon regions76of diodes D1-D2, and the same N+ diffusion or implant process used to form N+ wells68is used to form the N+ polysilicon regions78of diodes D1-D3. This combination creates PN junction polysilicon diodes that may be connected in series to form the thermal sensing device20.

An electrical insulation layer80, e.g., SiO2, is formed on all of the foregoing layers, such as in accordance with a known low temperature oxide (LTO) forming process. Contact holes are then selectively etched or otherwise formed in electrical insulation layer80, and a metalization layer is deposited onto the electrical insulation layer. The metalization layer is then selectively etched to form an emitter region84in contact with each of the emitter regions66,68of the IGBT12, a gate region82in contact with each of the gates72of the IGBT12, a T+ diode output region86in contact with the P+ end76of diode D1, a T− diode output region92in contact with the N− end78of diode D3and regions88and90connecting in series diodes D1and D2, and D2and D3respectively.

The polysilicon diodes D1-D3are electrically isolated from all three terminals of the power switch by the field oxide dielectric layer74, thereby preventing any electrical interaction therebetween. Additionally, the polysilicon diodes are field plated by the P+ region70positioned directly beneath diodes D1-D3, so that region70acts as a transient-blocking layer operable to shield the diodes D1-D3from collector voltage transients. It is desirable to position the thermal sensing device20, formed as a series-connection of three diodes D1-D3, adjacent to the power device12such that its operating temperature is substantially the same as that of the power device12. Alternatively, the thermal sensing device20may be positioned relative to the power device12such that while its operating temperature may not be the same as that of the power device12, it closely tracks that of the power device12. In either case, the diode voltage, VD, produced by the thermal sensing device20in response to the constant current supplied by current source ICwill be representative of the operating temperature of the power device12. Referring toFIG. 3, this diode voltage, VD, is plotted against temperature (° C.) for three different values of constant current, IC. Data sets30,40and50correspond to current values, IC, of 10, 40 and 100 microamperes, respectively. As is evident from regression lines32,42and52, the three-diode stack D1-D3produces a substantially linear voltage response, VD, to each of the three current values, IC, over temperature.

It has been determined that a single polysilicon diode of the type illustrated and described with respect toFIG. 2will change at approximately −2 mV/° C., a series-connected row or stack of three diodes will have a slope of approximately −6 mV/° C., and a series-connected stack of five diodes will have a slope of approximately −10 mV/° C. The actual slope of the three-diode row or stack illustrated inFIG. 3is −4.68 mV/° C. As described hereinabove, the actual number of diodes used to form the thermal sensing device20may vary to suit the particular application, and the output voltage sensitivity of the resulting device20represents one example consideration in the design of device20.

In one embodiment, as at least partially illustrated inFIG. 2, the series-connected diodes D1-D3are arranged along a common axis to form an elongated diode row structure having a bottom surface in contact with the electrical insulation layer74and four surrounding sides including a pair of elongated sides and a pair of short sides. In general, the diode structure comprising diodes D1-D3may be arranged in a number of configurations and orientations relative to the IGBT12, and one such orientation of the thermal sensing device20relative to the IGBT12is illustrated in FIG.4. Referring toFIG. 4, a top plan view of the integrated circuit10is shown illustrating one configuration of a layout of the IGBT12and thermal sensing device20. InFIG. 4, the metal layer84forming the emitter of the IGBT12covers a substantial portion of circuit10as is conventional, and a conventional bond pad for making an electrical connection to the IGBT emitter is typically defined on metal layer84. A bond pad100for making an electrical connection to the gate of the IGBT12is formed adjacent to metal layer84, and in the embodiment illustrated inFIG. 4the thermal sensing device20is arranged relative to the IGBT12such that one of its long sides is positioned adjacent to the heat generating portion; i.e., the emitter, of the IGBT12. Conventional bond pads102and104are formed adjacent to device20for making electrical connections to the T+ and T− terminals illustrated in FIG.1.

Referring toFIG. 5, a top plan view of the integrated circuit10is shown illustrating an alternative configuration of a layout of IGBT12and thermal sensing device20. The layout ofFIG. 5is similar to that ofFIG. 4with the exception that the thermal sensing device20is arranged relative to the IGBT12such that both of its long sides are positioned adjacent to the heat generating portion of the IGBT12.

Those skilled in the art will recognize that while the one-sided layout ofFIG. 4may be easier to integrate relative to the power device12, the two-sided layout ofFIG. 5will have better accuracy and thermal transient response. Other configurations and orientations of the thermal sensing device20relative to the power device12will occur to those skilled in the art, and any such configuration is intended to fall within the scope of the present invention.