Insulation-type DC/DC converter, AC/DC converter, power adapter and electrical apparatus for enhancing synchronization between primary side and secondary side

The task of the present invention is to enhance safety of an insulation-type DC/DC converter.The present invention relates to an insulation-type DC/DC converter, an AC/DC converter, a power adapter and an electronic device. A switch transistor is disposed on a primary side of a transformer, and a synchronous rectification transistor is disposed on a secondary side of the transformer. A primary-side control portion performs switch-driving of the switch transistor, and a secondary-side control portion controls turn-on and turn-off of the synchronous rectification transistor. A pulse transformer portion for implementing bi-directional communication between the primary-side control portion and the secondary-side control portion is disposed between the primary side and the secondary side. For example, signals associated with turn-on and turn-off of the switch transistor are transceived between the primary-side control portion and the secondary-side control portion by a pulse transformer portion.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a direct-current/direct-current (DC/DC) converter, an alternating-current/direct-current (AC/DC) converter, a power adapter and an electronic device.

Description of the Prior Art

In an insulation-type direct-current/direct-current (DC/DC) converter using a transformer, a feedback signal corresponding to a secondary-side voltage is transmitted to a primary side by such an optocoupler, and switch-driving of a switch transistor connected to a primary-side winding of a transformer is performed, thereby achieving stabilization of the secondary-side voltage.

Prior Art Document

Patent Publication

Patent publication 1: Japan Patent Publication No. 2006-197688

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

In this type of insulation-type DC/DC converter, information of a secondary-side voltage is unidirectionally transmitted to a primary side, and a primary-side circuit has no way of learning other information in a secondary-side circuit, and the secondary-side circuit likewise has no way of learning information in the primary-side circuit. Thus, even if issues are occurred in the secondary-side circuit, the primary-side circuit would still continue to drive a switch transistor; similarly, even if issues are occurred in the primary-side circuit, the secondary-side circuit would still continue to perform actions in the secondary-side circuit (for example, controlling turn-on and turn-off of a synchronous rectification transistor). Although a structure, which a DC/DC converter can be safely inactivated in the event of the above situations, may be assembled in most cases, the issues mentioned above may aggravate due to a lengthy period needed before the DC/DC converter is inactivated.

Further, when synchronous rectification is performed by a synchronous rectification transistor disposed on a primary side, control of time points for turn-on and turn-off of the synchronous rectification transistor becomes critical. The switch transistor of the primary side and the synchronous rectification transistor of the secondary-side should be prevented from being turned on simultaneously, so as to prevent system damage. In regard to the aspect mentioned above, there is a method in which information of the primary side is inferred at the secondary side by monitoring the voltage in a secondary-side winding of the transformer, so as to control the synchronous rectification transistor. However, there is still a need to develop a technique capable of more reliably or more stably preventing internal transistors from being turned on simultaneously while synchronous rectification is performed. Further, although a situation associated with synchronous rectification is described, it should be noted that the situation is merely a example for illustration purposes, and the present invention is not limited to a synchronous rectification-type DC/DC converter.

It is an object of the present invention to provide an insulation-type DC/DC converter, an AC/DC converter, a power adapter and an electronic device which are beneficial for enhancing safety of actions of a primary side and a secondary side.

Technical Means for Solving the Problems

The insulation-type DC/DC converter of the present invention is configured to mutually insulate a primary-side circuit disposed on a primary side and a secondary-side circuit disposed on a secondary side of a power transformer, and to perform switch-driving of a switch transistor of a primary-side winding of the power transformer, such that the secondary-side circuit obtains a secondary-side voltage from a primary-side voltage in the primary-side circuit. The insulation-type DC/DC converter includes: a primary-side control portion, disposed on the primary side and performs switch-driving of the switch transistor; a secondary-side control portion, disposed on the secondary-side; and a communication transformer, implementing bi-directional communication between the primary-side control portion and the secondary-side control portion.

Specifically, for example, the insulation-type DC/DC converter may be an insulation synchronous rectification-type DC/DC converter, in which a synchronous rectification transistor is controlled by the secondary-side control portion. The synchronous rectification transistor is disposed on the secondary side so as to implement synchronous rectification. Signals associated with turn-on and turn-off of the switch transistor are transceived between the primary-side control portion and the secondary-side control portion through the communication transformer.

More specifically, for example, in the insulation-type DC/DC converter, the primary-side control portion may also send a predetermined first signal to the secondary-side control portion through the communication transformer when the switch transistor is turned on, and send a predetermined second signal to the secondary-side control portion through the communication transformer when the switch transistor is turned off. The secondary-side control portion controls turn-on and turn-off of the synchronous rectification transistor according to the predetermined first signal and the predetermined second signal received.

At this point, for example, in the insulation-type DC/DC converter, the secondary-side control portion is configured to send a predetermined first response signal to the primary-side control portion through the communication transformer in response to the predetermined first signal received, and to send a predetermined second response signal to the primary-side control portion through the communication transformer in response to the predetermined second signal received. The primary-side control portion may perform, upon not receiving the predetermined first response signal after having sent the predetermined first signal, or upon not receiving the predetermined second response signal after having sent the predetermined second signal, a predetermined communication error process, which includes a process of prohibiting setting the switch transistor to a turned-on state.

Alternatively, for example, in the insulation-type DC/DC converter, the secondary-side control portion may send the predetermined first signal and the predetermined second signal to the primary-side control portion through the communication transformer, wherein the first predetermined signal provides an instruction for turning on the switch transistor and the predetermined second signal provides an instruction for turning off the switch transistor. The primary-side control portion may also turn on the switch transistor in response to the predetermined first signal received, and turn off the switch transistor in response to the predetermined second signal received.

At this point, for example, in the insulation-type DC/DC converter, the primary-side control portion is configured to send the predetermined first response signal to the secondary-side control portion through the communication transformer in response to the predetermined first signal received, and to send the predetermined second response signal to the secondary-side control portion through the communication transformer in response to the predetermined second signal received. The secondary-side control portion may perform, upon not receiving the predetermined first response signal after having sent the predetermined first signal, or upon not receiving the predetermined second response signal after having sent the predetermined second signal, a predetermined communication error process, which includes a process of prohibiting setting the synchronous rectification transistor to a turned-on state.

Further, for example, in the insulation-type DC/DC converter, upon starting to power the primary-side control portion and activation of the primary-side control portion, an initial action is performed regardless of a value of the primary-side voltage, such that switch-driving of the switch transistor is performed. When the secondary-side voltage becomes a predetermined voltage or more and the secondary-side control portion is activated after the initial action is undertaken, predetermined handshake communication is performed between the primary-side control portion and the secondary-side control portion through the communication transformer. A normal action is performed after the handshake communication is correctly completed, and switch-driving of the switch transistor is performed according to the secondary-side voltage.

Further, for example, in the insulation-type DC/DC converter, the primary-side control portion includes a primary-side abnormality detection portion for detecting whether predetermined abnormality exists in the primary-side circuit. If the abnormality is detected in the primary-side circuit, switch-driving of the switch transistor is stopped, and a predetermined primary-side abnormality detection signal is sent to the secondary-side control portion through the communication transformer.

Further, for example, in the insulation-type DC/DC converter, the secondary-side control portion comprises a secondary-side abnormality detection portion for detecting whether predetermined abnormality exists in the secondary-side circuit. If the abnormality is detected in the secondary-side circuit, a predetermined secondary-side abnormality detection signal is sent to the primary-side control portion through the communication transformer, and the primary-side control portion may stop switch-driving of the switch transistor upon receiving the secondary-side abnormality detection signal.

Further, for example, in the insulation-type DC/DC converter, when one control portion of the primary-side control portion and the secondary-side control portion sends a predetermined signal to the other control portion through the communication transformer and the other control portion receives the predetermined signal, the other control portion sends a signal to the one control portion through the communication transformer in response to the predetermined signal received.

An AC/DC converter of the present invention includes: a rectification circuit, performing full-wave rectification on an AC voltage; a smoothing capacitor, smoothing the voltage having undergone full-wave rectification to generate a DC voltage; and the insulation-type DC/DC converter, thereby generating a DC secondary-side voltage from a primary-side voltage of the DC voltage as an output voltage.

A power adapter of the present invention includes: a plug, receiving an AC voltage; the AC/DC converter; and a housing, accommodating the AC/DC converter.

An electronic device of the present invention includes: the AC/DC converter; and a load device, driven by an output voltage of the AC/DC converter.

Effects of the Invention

According to the present invention, an insulation-type DC/DC converter, an AC/DC converter, a power adapter and an electronic device beneficial for enhancing safety of actions of a primary side and a secondary side are provided.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Example of embodiments of the present invention are specifically described with the accompanying drawings below. In the reference drawings, the same symbols and numerals are denoted for the same components, and repeated description of the same components is in principle omitted. Further, in the description, for brevity, numerals or symbols of reference information, signals, physical quantities, elements or components are given in order to omit or abbreviate the names of the reference information, signals, physical quantities, elements or components. For example, a switch transistor (referring toFIG. 1) denoted as “M1” is sometimes expressed as a switch transistor M1and is sometimes expressed as a transistor M1for short, both however referring to the same component.

First of all, several terms used in the description of the embodiments are explained below. A so-called “level” refers to a level of potential, and is associated with any signal or voltage, and a high level has a potential higher than that of a low level. For any signal or voltage having a level periodically switching between a low level and a high level, the ratio of a time period in which the level of the signal or voltage is at a high level to a time period of one cycle of the signal or voltage is referred to as a duty cycle.

For any transistor having a structure of a field-effect transistor (FET), a turned-on state thereof refers to a turned-on state between the drain and the source of the transistor; and a so-called turned-off state refers to a non-turned-on state (interrupted state) between the drain and the source of the transistor. The same applies to a transistor that is not an FET. In the description below, a turned-on state or a turned-off state may be expressed as turned on and turned off. For any transistor, switching from a turned-off state to a turned-on state is expressed as turning on, and switching from a turned-on state to a turned-off state is expressed as turning off. Further, for any transistor, a period of a turned-on state of the transistor is sometimes referred to as a turned-on period, and a period of a turned-off state of the transistor is sometimes referred to as a turned-off period.

First Embodiment

The first embodiment of the present invention is described below.FIG. 1shows an overall structural diagram of an insulation synchronous rectification-type DC/DC converter1(to be referred to as the DC/DC converter1for short hereafter) according to a first embodiment of the present invention. The DC/DC converter1is a flyback DC/DC converter, and generates and stabilizes a DC primary-side voltage VPinto a DC secondary-side voltage VSof a predetermined target voltage VTG.

The DC/DC converter1includes a primary-side circuit disposed on the primary side of the DC/DC converter1and a secondary-side circuit disposed on the secondary side of the DC/DC converter1, and the primary-side circuit and the secondary-side circuit are mutually insulated. The ground terminal in the primary-side circuit is referenced as “GND1”, and the ground terminal in the secondary-side circuit is referenced as “GND2”. The primary-side voltage VPis a voltage regarding the ground terminal GND1as a reference, and the primary-side voltage VSis a voltage regarding the ground terminal GND2as a reference. In each of the primary-side circuit and the secondary-side circuit, the ground terminal refers to a conductive portion (a predetermined potential point) having a reference potential of 0 V or a reference potential itself. However, because the ground terminal GND1and the ground terminal GND2are mutually insulated, they may have potentials different from each other.

Between a pair of input terminals TM1Aand TM1Bin the DC/DC converter1, the input terminal TM1Bis connected to the ground terminal GND1, and applies the primary-side voltage VPto the input terminal TM1Aby using the potential of the input terminal TM1Bas a reference. Between a pair of output terminals TM2Aand TM2Bin the DC/DC converter1, the output terminal TM2Bis connected to the ground terminal GND2, and applies the secondary-side voltage VSto the output terminal TM2Aby using the potential of the output terminal TM2Bas a reference. The DC/DC converter1is capable of supplying the secondary-side voltage VSto any load device (not shown) connected between the output terminals TM2Aand TM2B.

The DC/DC converter1includes a power transformer having a primary-side winding W1and a secondary-side winding W2, i.e., a transformer TR. In the transformer TR, the primary-side winding W1and the secondary-side winding W2are mutually electrically insulated and are magnetically coupled by opposite polarities.

In the DC/DC converter1, a communication transformer, as a characteristic element, i.e., a pulse transformer portion30, is provided, and the pulse transformer portion30may be used to implement various actions. Elements other than the pulse transformer portion30are described below. Further, by using the pulse transformer portion30, a feedback circuit40and an optocoupler41may also be omitted. The above case is described in other embodiments below. In principle, the feedback circuit40and the optocoupler41are provided in the DC/DC converter1.

In the primary-side circuit of the DC/DC converter1, apart from the primary-side winding S1, a primary-side control portion10, a primary-side power circuit11, a capacitor C1equivalent to an input capacitor, a switch transistor M1and a sensing resistor RCSare further provided. The switch transistor M1is structured as an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET). One end of the primary-side winding W1is connected to the input terminal TM1Ato receive the DC primary-side voltage VP. The other end of the primary-side winding W1is connected to the drain of the switch transistor M1, and the source of the switch transistor M1is connected to the ground terminal GND1through the sensing resistor RCS. The capacitor C1is disposed between the input terminals TM1Aand TM1B, and the primary-side voltage VPis applied between two terminals of the capacitor C1. The primary-side power circuit11performs DC-DC conversion on the primary-side voltage VPto generate and provide a power voltage VCC having an expected voltage value to the primary-side control portion10. The primary-side control portion10performs driving based on the power voltage VCC.

The secondary-side circuit of the DC/DC converter1further includes, in addition to the secondary-side winding W2, a secondary-side control portion20, a feedback circuit40, a synchronous rectification transistor M2, a diode D2, voltage dividing resistors R1to R4, and a capacitor R2equivalent to an output capacitor. The synchronous rectification transistor M2(to be referred to as an SR transistor M2hereafter) is structured as an N-type MOSFET. The diode D2is a parasitic diode of the SR transistor M2. Thus, a direction from the source to the drain of the SR transistor M2is set as a forward direction, and the diode D2is connected in parallel to the SR transistor M2. The diode D2may also be a diode separately provided from the parasitic diode.

One end of the secondary-side winding W2is connected to the output terminal TM2A, and thus the secondary-side voltage VSis applied to one end of the secondary-side winding W2. The other end of the secondary-side winding W2is connected to the drain of the SR transistor M2. The voltage of the other end of the secondary-side winding W2(in other words, the drain voltage of the SR transistor M2) is represented by “VDR”. A connecting node between the other end of the secondary-side winding W2and the drain of the SR transistor M2is connected to one terminal of the voltage dividing resistor R1, and the other terminal of the voltage dividing resistor R1is connected to the ground terminal GND2through the voltage dividing resistor R2. Thus, a divided voltage of the voltage VDR, i.e., the voltage VA, is applied to a connecting node between the voltage dividing resistors R1and R2. On the other hand, the output terminal TM2Aapplied with the secondary-side voltage VSis connected to one terminal of the voltage dividing resistor R3, and the other terminal of the voltage dividing resistor R3is connected to the ground terminal GND2through the voltage dividing resistor R4. Thus, the divided voltage of the secondary-side voltage VSapplied to a connecting node between the voltage dividing resistors R3and R4is a voltage VB.

The source of the SR transistor M2is connected to the ground terminal GND2. Further, a capacitor C2is disposed between the output terminals TM2Aand TM2B, and thus the secondary-side voltage VSis applied to two terminals of the capacitor C2. A resistor for detecting any over-current generated may also be disposed between the capacitor C2and the load device (not shown) of the DC/DC converter1.

The secondary-side control portion20uses the secondary-side voltage VSas a power voltage to perform driving. The secondary-side control portion20controls turn-on and turn-off of the SR transistor M2by controlling the gate voltage of the SR transistor M2. The secondary-side control portion20may also perform the control according to the voltage VAor according to the voltages VAand VB, and at this point, the gate voltage of the SR transistor M2may be controlled while the transistors M1and M2are not simultaneously turned on. Means for controlling the SR transistor M2may include any means of any known method, for example, a means of using a comparator as below may be used. When a turned-off state of the SR transistor M2is considered as a starting point, in the means of using a comparator, the secondary-side control portion20turns on the SR transistor M2when the voltage VAreceived becomes lower than a predetermined negative turn-on determination voltage (e.g., −100 mV), and turns off the SR transistor M2when the voltage VAreceived becomes higher than a predetermined negative turn-off determination voltage (e.g., −10 mV). The potential of the turn-off determination voltage is higher than the potential of the turn-on determination voltage.

In the DC/DC converter1, the optocoupler41is disposed throughout the primary-side circuit and the secondary-side circuit. The optocoupler41includes a light emitting element disposed at the secondary-side circuit and a light receiving element disposed at the primary-side circuit. A light emitting element of the optocoupler41is biased by the secondary-side voltage VSor by a divided voltage of the secondary-side voltage VS, and the feedback circuit40cooperates with the primary-side control portion10to drive the light emitting element of the optocoupler41by means of having the secondary-side voltage VSfollow the target voltage VTG(that is, by means of having a difference between the voltages VSand VTGbe zero). For example, the feedback circuit40, as shown inFIG. 1, is connected to the connecting node between the voltage dividing resistors R3and R4, and supplies a current corresponding to an error between the secondary-side voltage VSand the target voltage VTGto the light emitting element of the optocoupler41according to the voltage VBcorresponding to the secondary-side voltage VS. The feedback resistor40is formed by a shunt regulator or an error amplifier.

The primary-side control portion10is connected to the light receiving element of the optocoupler41, and inputs a feedback signal VFBcorresponding to a feedback current IFBflowing in the light receiving element of the optocoupler41to the primary-side control portion10. Further, the primary-side control portion10inputs a current detection signal VCSequivalent to a voltage drop in the sensing resistor RCSto the primary-side control portion10.

The primary-side control portion10is connected to the gate of the switch transistor M1, and performs switch-driving of the switch transistor M1by supplying a pulse signal to the gate of the switch transistor M1. The pulse signal is a signal of a rectangular waveform having a signal level switching between a low level and a high level. When signals respectively having a low level and a high level are supplied to the gate of the transistor M1, the transistor M1becomes a turned-off state and a turned-on state, respectively. The structure and control means of the primary-side control portion10are not specifically limited. For example, the primary-side control portion10may also employ pulse width modulation (PWM) to supply a pulse signal having a duty cycle corresponding to the feedback signal VFBto the gate of the switch transistor M1, or may employ pulse frequency modulation (PFM) to supply a pulse signal having a frequency corresponding to the feedback signal VFBto the gate of the switch transistor M1. Further, for example, the primary-side control portion10may also adjust the duty cycle of the pulse signal according to the current detection signal VCS(that is, according to the current flowing in the switch transistor M1).

A plurality of terminals are provided at the primary-side control portion10. The plurality of terminals provided at the primary-side control portion10include a terminal TM11connected to the gate of the switch transistor M1, a terminal TM12for receiving the power voltage VCC, a terminal TM13connected to the ground terminal GND1, a terminal TM14for receiving the feedback signal VFB, a terminal TM15for receiving the current detection signal VCS, and terminals TM16and TM17connected to the pulse transformer portion30. The terminal TM16is an output terminal for sending a signal S1mentioned below, and the terminal TM17is an input terminal for receiving a signal S2mentioned below.

A plurality of terminals are provided at the secondary-side control portion20. The plurality of terminals provided at the secondary-side control portion20include a terminal TM21connected to the gate of the SR transistor M2, a terminal TM22for receiving the secondary-side voltage VS, a terminal TM23connected to the ground terminal GND2, a terminal TM24for receiving the voltage VA, a terminal TM25for receiving the voltage VB, and terminals TM26and TM27connected to the pulse transformer portion30. The terminal TM26is an input terminal for receiving the signal S1mentioned below, and the terminal TM27is an output terminal for sending the signal S2mentioned below.

In the DC/DC converter1of the above structure, the secondary-side voltage VSmay be obtained from the primary-side voltage VPby performing switch-driving of the switch transistor M1. That is to say, energy is accumulated in the primary-side winding W1during a turned-on period of the switch transistor M1, and the energy accumulated is released from the secondary-side winding W2during a turned-off period of the switch transistor M1, thereby charging the capacitor C2to obtain the secondary-side voltage VS. The SR transistor M2is turned on while the energy is released from the secondary-side winding W2in order to reduce loss.

In addition, an auxiliary winding may also be disposed at the transformer TR as a substitution for the primary-side power circuit11, and an innate power circuit is thus formed by the auxiliary circuit included to generate the power voltage VCC of the primary-side control portion10. Moreover, in the primary-side circuit, the current flowing from the input terminal TM1Athrough the primary-side winding W1to the ground terminal GND1is referred to as a primary-side current, and is denoted as “IP”. In the secondary-side circuit, the current flowing from ground terminal GND2through the secondary-side winding W2to the output terminal TM2Ais referred to as a secondary-side current, and is denoted as “IS”.

The pulse transformer portion30is described below. The pulse transformer portion30is a communication transformer for implementing bi-directional communication between the primary-side control portion10and the secondary-side control portion20, and is formed by more than one pulse transformer. In the description below, the so-called bi-directional communication, unless otherwise specified, refers to bi-directional communication between the primary-side control portion10and the secondary-side control portion20.

The signal sent by the primary-side control portion10to the secondary-side control portion20through the pulse transformer portion30is referenced by the denotation “S1”. With regard to the signal S1, the signal transmitted in the primary-side circuit is referenced by the denotation “S1a”, and the signal transmitted in the secondary-side circuit is referenced by the denotation “S1b”. The signals S1aand S1bmay be in any forms, and may also be digital signals such as pulse signals.

The signal sent by the secondary-control portion20to the primary-side control portion10through the pulse transformer portion30is referenced by the denotation “S2”. With regard to the signal S2, the signal transmitted in the primary-side circuit is referenced by the denotation “S2a”, and the signal transmitted in the secondary-side circuit is referenced by the denotation “S2b”. The signals S2aand S2bmay be in any forms, and may also be digital signals such as pulse signals.

A plurality of terminals are provided at the pulse transformer portion30. The plurality of terminals provided at the pulse transformer portion30include a terminal TM31for receiving the signal S1afrom the primary-side control portion10, a terminal TM32for sending the signal S1bto the secondary-side control portion20, a terminal TM33for receiving the signal S2bfrom the secondary-side control portion20, and a terminal TM34for sending the signal S2ato the primary-side control portion10.

FIG. 2shows a diagram of an exemplary structure of the pulse transformer portion30. In the exemplary structure inFIG. 2, the pulse transformer portion30includes pulse transformers31and32, a primary-side sending portion33, a primary-side receiving portion34, a secondary-side sending portion35and a secondary-side receiving portion36. Each of the pulse transformers31and32includes a primary-side winding disposed in the primary-side circuit and a secondary-side winding disposed in the secondary-side circuit.

In the primary-side control portion10and the secondary-side control portion20, an embodiment in which the primary-side control portion10sends the signal (S1) is referred to as a primary-side sending embodiment. In the primary-side sending embodiment, the primary-side sending portion33generates a pulse signal based on the signal S1afrom the primary-side control portion10, and applies the pulse signal generated to the primary-side winding of the pulse transformer31. The secondary-side receiving portion36generates the signal S1bbased on the voltage of the secondary-side winding of the pulse transformer31generated based on the pulse signal applied above. It may be regarded that information included in the signal S1ais also included in the signal S1b, and the signal S1aand the signal S1bare mutually equivalent. The sending of the signal S1strictly speaking refers to sending of the signal S1a, and the receiving of the signal S1strictly speaking refers to receiving of the signal S1b. Unless otherwise required below, the signals S1aand S1bare collectively referred to as the signal S1.

In the primary-side control portion10and the secondary-side control portion20, first of all, an embodiment in which the secondary-side control portion20sends the signal (S2) is referred to as a secondary-side sending embodiment. In the secondary-side sending embodiment, the secondary-side sending portion35generates a pulse signal based on the signal S2bfrom the secondary-side control portion20, and the pulse signal generated is applied to the secondary-side winding of the pulse transformer32. The primary-side receiving portion34generates the signal S2abased on the voltage of the primary-side winding of the pulse transformer32generated based on the pulse signal applied above. It may be regarded that information included in the signal S2bis also included in the signal S2a, and the signal S2aand the signal S2bare mutually equivalent. The sending of the signal S2strictly speaking refers to sending of the signal S2b, and the receiving of the signal S2strictly speaking refers to receiving of the signal S2a. Unless otherwise required below, the signals S2aand S2bare collectively referred to as the signal S2.

Further, the primary-side sending portion33, the primary-side receiving portion34, the secondary-side sending portion35and the secondary-side receiving portion36may be provided in the pulse transformer portion30; alternatively, at least one of the primary-side sending portion33and the primary-side receiving portion34may be provided in the primary-side control portion10, or at least one of the secondary-side sending portion35and the secondary-side receiving portion36may be provided in the secondary-side control portion20.

The pulse transformer portion30configured as above enables information of the primary side and information of the secondary side to be shared between the primary-side control portion10and the secondary-side control portion20. Thus, for example, when abnormality occurs in any one between the control portions10and20, actions of the primary-side circuit and the secondary-side circuit may be immediately stopped to ensure safety. Further, various other advantages may be achieved, such as appropriately controlling time points for turning on/off the transistors M1and M2by using the bi-directional communication of the pulse transformer portion30.

As shown inFIG. 3(a), in the primary-side sending embodiment, the predetermined signal S1sent from the primary-side control portion10may be specifically referred to as a reference signal CMD1(or the reference signal may be referred to as an instruction signal). In the primary-side sending embodiment, the secondary-side control portion20may send the predetermined signal S2without any delay upon receiving the reference signal CMD1, wherein the predetermined signal S2is for responding to the reference signal CMD1received. The signal S2in response to the reference signal CMD1received is specifically referred to as a response signal ACK2. Sending the response signal ACK2is equivalent to responding to the reference signal CMD1. The primary-side control portion10may determine, by receiving the response signal ACK2, that the secondary-side control portion20correctly receives the reference signal CMD1.

In the primary-side sending embodiment, if the primary-side control portion10does not receive the response signal ACK2(S2) after a predetermined time period subsequent having sent the reference signal CMD1(S1), the primary-side control portion10may perform a predetermined communication error process. The communication error process performed by the primary-side control portion10includes a process of setting a communication flag FLG1to “1”, and may further include a communication error report process.

The communication error flag FLG1is stored by the primary-side control portion10, and has a value of “O” or “I”. The initial value of the communication error flag FLG1is “1”, and the communication error flag FLG1is set to “0” upon correctly completing handshake communication. In the primary-side control portion10, when the flag FLG1is set to “1”, the switch transistor M1is prohibited from being set to a turned-on state (thus, the transistor M1is kept in a turned-off state), and the switch transistor M1is set to a turned-on state only when the flag FLG1is set to “0” (except for when a burst charge action below is performed). Thus, it may be said that the error communication error process of the primary-side control portion10includes a process of prohibiting setting the switch transistor M to a turned-on state (in other words, a process of turning off the switch transistor M1or keeping the switch transistor M1in a turned-off state), and the transistor M1is immediately turned off if the communication error process is performed while the transistor M1is turned on.

As shown inFIG. 3(b), in the secondary-side sending embodiment, sometimes the predetermined signal S2sent from the secondary-side control portion20is specifically referred to as a reference signal CMD2(or the reference signal is referred to as an instruction signal). In the secondary-side sending embodiment, the primary-side control portion10may send the predetermined signal S1without any delay upon receiving the reference signal CMD2, wherein the predetermined signal St is for responding to the reference signal CMD2received. The signal S1in response to the reference signal CMD2received is specifically referred to as a response signal ACK1. Sending the response signal ACK1is equivalent to responding to the reference signal CMD2. The secondary-side control portion20may determine, by receiving the response signal ACK1, that the primary-side control portion10correctly receives the reference signal CMD2.

In the secondary-side sending embodiment, if the secondary-side control portion20does not receive the response signal ACK1(S1) after a predetermined time period subsequent to having sent the reference signal CMD2(S2), the secondary-side control portion20may perform a predetermined communication error process. The communication error process performed by the secondary-side control portion20includes a process of setting a communication error flag FLG2to “1”, and may further include a communication error report process.

The communication error flag FLG2is stored by the secondary-side control portion20, and has a value of “0” or “I”. The initial value of the communication error flag FLG2is “1”, and the communication error flag FLG2is set to “O” upon correctly completing handshake communication. In the secondary-side control portion20, when the flag FLG2is set to “1”, the SR transistor M2is prohibited from being set to a turned-on state (thus, the transistor M2is kept in a turned-off state), and the secondary-side control portion20only allows the SR transistor M2to be set to a turned-on state when the flag FLG2is set to “0”. Thus, it can be said that the error communication error process of the secondary-side control portion20includes a process of prohibiting setting the SR transistor M2to a turned-on state (in other words, a process of turning off the SR transistor M2or keeping the SR transistor M2in a turned-off state), and the transistor M2is immediately turned off if the communication error process is performed while the transistor M2is turned on.

The communication error report process may be a process such as below: using a predetermined report portion (e.g., a light emitting element, an image display portion or a speaker) to report a predetermined communication error to an external terminal of the DC/DC converter1, wherein the predetermined report portion is built-in the DC/DC converter1or is connected to the DC/DC converter1. The communication error report may also be a visual or audio report for indicating that abnormality has occurred in the bi-directional communication.

Specific actions and control methods of using the pulse transformer portion30are described in the embodiments below. Further, when the primary-side control portion10and the secondary-side control portion20cooperate through bi-directional communication, a so-called master/slave method may be used, wherein any one of the primary-side control portion10and the secondary-side control portion20is the master and the other is the slave.

Second Embodiment

The second embodiment of the present invention is described below. The second embodiment as well as third to seventh embodiments below are embodiments based on the first embodiment. Regarding items that are not specified in the second to seventh embodiments, the details of the description associated with the first embodiment are also applicable to the second to seventh embodiments, given that there is no contradiction. In the description explaining the second embodiment, the items that are contradictory, if any, between the first and second embodiments, the description of the second embodiment prevails (the same applies to the third to seventh embodiments below). Given that there is no contradiction, any multiple embodiments among the first to seventh embodiments may be combined.

The second embodiment includes embodiments EX2_1 to EX2_3 below. For signals that may be transceived by the pulse transformer portion30and associated with turn-on and turn-off control of the transistors M1and M2, an example of such transceiving is described in the embodiments EX2_1 to EX2_3 below. Further, the actions illustrated in the second embodiment are actions after a handshake action is correctly completed, and are actions in a situation where the communication error flags FLG1and FLG2are set to “0”, unless otherwise specified.

The embodiment EX2_1 is described below. In the embodiment EX2_1, the primary-side control portion10is the master, and the secondary-side control portion20is the slave. The primary-side control portion10of the embodiment EX2_1 may control turn-on and turn-off of the switch transistor M1according to the method of using the feedback signal FVBor the current detection signal VCSas described in the first embodiment. Further, in the embodiment EX2_1, it is assumed that the secondary-side control portion20uses the means of a comparator. The means of a comparator determines a method for time points of turn-on and turn-off of the SR transistor M2according to the voltage VDR(more specifically, according to a comparison result between the voltage VAcorresponding to the voltage VDRand the turn-on determination voltage and the turn-off determination voltage).

Refer toFIG. 4for specific description of the means of a comparator.FIG. 4shows a timing diagram of assuming that the DC/DC converter1is in a discontinuous mode according to the embodiment EX2_1. The switch transistor M1is in a turned-on state in a period between time points tA1and tA2under the control of the primary-side control portion10, and then the switch transistor M1is in a turned-off state in a period up to a time point tA5. The transistors M1and M2are controlled by means of having the SR transistor M2be in a turned-off state during a turned-on period of the switch transistor M1, and having the switch transistor M1be in a turned-off state during a turned-on period of the SR transistor M2.

In the turn-on period of the switch transistor M1, the current IPflows in the primary-side winding W2, and the voltage VDRis higher than the secondary-side voltage VSby only a voltage VOR2. The voltage VOR2is a sensing voltage generated at the secondary-side winding W2during the turn-on period of the switch transistor M1. The sensing voltage VOR2uses a turn ratio n of the primary-side voltage VPto the transformer TR, and is represented as “VOR2=VP/n”. Further, the turn ratio n is represented as “n=NP/NS”, wherein NPis the number of turns of the primary-side winding W1and NSis the number of turns of the secondary-side winding W2.

When the switch transistor M1is turned off at the time point tA2, the voltages VDRand VAcontinue to drop, and the secondary-side current ISflows through the diode D2. As a result, when the secondary-side control portion20detects that the voltage VAis lower than the predetermined negative turn-on determination voltage (e.g., −100 mA), the secondary-side control portion20turns on the SR transistor M2. The time point tA3represents a turn-on time point of the SR transistor M2.

After the SR transistor M2is turned on, the secondary-side current is flows through the channel of the SR transistor M2, and the size of the secondary-side current ISand the energy stored in the transformer TR are together reduced. At the time point tA4subsequent to the time point tA3, the secondary-side control portion20turns off the SR transistor M2. For example, the secondary-side control portion20turns off the SR transistor M2when the voltage VAreceived becomes higher than a predetermined negative turn-off determination voltage (e.g., −10 mA). The potential of the turn-off determination voltage is higher than the potential of the turn-on determination voltage. The turn-off time point tA4of the SR transistor M2may also be a time point determined with reference to the voltage VB. Next, under the control of the primary-side control portion10, the switch transistor M1is turned on at the time point tA5. Then, the same actions are repeated.

By using the means of a comparator for controlling the SR transistor M2as a premise, bi-directional communication of using the pulse transformer portion30is performed as below.

FIG. 5shows a timing diagram near the time points tA1and tA2. When the primary-side control portion10turns on the switch transistor M1at the time point tA1, it synchronously sends the reference signal CMD1serving as the signal S1(the reference signal CMD1is referred to as a reference signal211). The reference signal211is for providing an instruction for turning on the transistor M1. The secondary-side control portion20receiving the reference signal211(CMD1) sends the response signal ACK2serving as the signal S2without any delay (the response signal ACK2is referred to as a response signal212). The time point for sending the reference signal211may coincide with the time point tA1, or may be slightly shifted from the time point tA2. The secondary-side control portion20in principle may use the means of a comparator to determine turn-on and turn-off time points of the SR transistor M2. However, when the reference signal211is received while the SR transistor M2is in a turned-on state, the SR transistor M2is immediately turned off without relying on the voltage VA. That is to say, the secondary-side control portion20receiving the reference signal211(CMD1) ensures a turned-off state of the SR transistor M2. The so-called ensuring of turn-off state of the SR transistor M2refers to turning off the SR transistor M2if the SR transistor M2is in a turned-on state, and keeping the SR transistor M2in a turned-off state if the SR transistor M2is already in a turned-off state. According to conditions, the switch transistor M1may also be turned on before the detection voltage VAbecomes higher than the turn-off determination voltage; however, an undesirable situation caused by simultaneously turned on transistors M1and M2may be suppressed according to the method above.

Further, when the primary-side control portion10turns off the switch transistor M1at the time point tA2, it synchronously sends the reference signal CMD1serving as the signal S1(the reference signal CMD1is referred to as a reference signal213). The reference signal213is for providing an instruction for turning off the transistor M1. The secondary-side control portion20receiving the reference signal213(CMD1) sends the response signal ACK2serving as the signal S2without any delay (the response signal ACK2is referred to as a response signal214). The time point for sending the reference signal213may coincide with the time point tA2, or may be slightly shifted from the timing point tA2. The secondary-side control portion20in principle may use the means of a comparator to determine turn-on and turn-off time points of the SR transistor M2. However, when the reference signal213is received while the SR transistor M2is in a turned-off state, the SR transistor M2is immediately turned on without relying on the voltage VA. Thus, loss in the secondary-side circuit may be further reduced.

Further, as described in the first embodiment, if the response signal ACK2(212and214inFIG. 5) is not received after having sent the reference signal CMD1(211and213inFIG. 5), the primary-side control portion10may perform a communication error process.

However, in the method inFIG. 5, a situation where the transistors M1and M2are simultaneously turned on may exist even within a short time. If the length of a period in which the transistors M1and M2are simultaneously turned on is short enough, no substantial problem would be incurred. However, in order to reliably prevent the transistors M1and M2from being turned on simultaneously, an improving method as shown inFIG. 6may be used.

FIG. 6is a timing diagram near the time point tA1of the improving method. In the improving method, before the primary-side control portion10turns on the switch transistor M1, it sends the reference signal CMD1serving as the signal S1at the time point tA0(the reference signal CMD1is referred to as a reference signal211a). The reference signal211ais for providing a notification for turning on the switch transistor M1, and is for providing an instruction for ensuring a turn-off state of the SR transistor M2. The secondary-side control portion20receiving the reference signal211a(CMD1) ensures a turned-off state of the SR transistor M2, and sends a response signal ACK2serving as the signal S2(the response signal ACK2is referred to as a response signal212a). The primary-side control portion10turns on the switch transistor M1at the time point tA1upon receiving the response signal212a. The primary-side control portion10does not turn on the switch transistor M1but keeps it in a turned-off state, given that the response signal212ais not received. Thus, the transistors M1and M2are prevented from being turned on simultaneously, thereby enhancing the safety of the DC/DC converter1.

According to the method of the embodiment EX2_1 based on the means of a comparator, loss may be reduced or safety may be enhanced similarly by using bi-directional communication. In the means of a comparator, in most cases, the responding ability of a circuit for determining turn-on and turn off time points of the SR transistor M2becomes critical, and according to the method of the embodiment EX2_1, turn-on and turn-off time points of the SR transistor M2may also be determined by using the signal S1(CMD1) from the primary-side control portion10. Therefore, the requirements on the responding ability of the circuit may be alleviated, and power consumption associated with the means of a comparator may also be reduced.

The embodiment EX2_2 is described below. In the embodiment EX2_2, similar to the embodiment EX2_1, the primary-side control portion10is the master, and the secondary-side control portion20is the slave. The primary-side control portion10of the embodiment EX2_2 may control turn-on and turn-off of the switch transistor M1by using the method based on the feedback signal VFBor the current detection signal VCSas described in the first embodiment. In the embodiment EX2_2, the means of a comparator is not used in the secondary-side control portion20, but the SR transistor M2is controlled under an instruction from the primary-side control portion10. The above is specifically described below with reference toFIG. 7.

FIG. 7shows a timing diagram of a DC/DC converter1according to the embodiment EX2_2. In the example inFIG. 7, the transistors M1and M2are respectively in a turned-off state and a turned-on state at a time point tB0, and the primary-side control portion10turns on the switch transistor M1at the subsequent time point tB1.

When the primary-side control portion10turns on the switch transistor M1at the time point tB1, it synchronously sends the reference signal CMD1serving as the signal S1(the reference signal CMD1is referred to as a reference signal221). The reference signal211is for providing a notification for turning on the transistor M1, and is for providing an instruction for turning off the SR transistor M2. The secondary-side control portion20receiving the reference signal221(CMD1) turns off the SR transistor M2without any delay, and sends a response signal ACK2serving as the signal S2(the response signal ACK2is referred to as a response signal222). Further, in the example inFIG. 7, the SR transistor M2is turned off in response to the reference signal221received; however, under the control of the secondary-side control portion20, the SR transistor M2may also be turned off according to the voltage VAbefore the time point tB1.

When the primary-side control portion10turns off the switch transistor M1at a time point tB2subsequent to the time point tB1, it synchronously sends the reference signal CMD1serving as the signal S1(the reference signal CMD1is referred to as a reference signal223). The reference signal223is for providing a notification for turning off the transistor M1, and is for providing an instruction for turning on the SR transistor M2. The secondary-side control portion20receiving the reference signal223(CMD1) turns on the SR transistor M2without any delay, and sends a response signal ACK2serving as the signal S2(the response signal ACK2is referred to as a response signal224).

Later, upon arriving at a time point for turning on and a time point for turning off the switch transistor M1, the same actions are repeated. Further, as described in the first embodiment, if the response signal ACK2(222and224inFIG. 7) is not received after having sent the reference signal CMD1(221and223inFIG. 7), the primary-side control portion10may perform a communication error process.

According to the method of the embodiment EX2_2, similar to the embodiment EX2_1, appropriate synchronous rectification that ensures safety may be performed, such that circuit needed for implementing the means of a comparator may be omitted, thereby decreasing the scale of circuits in the secondary-side circuit and reducing power consumption associated with the means of a comparator.

However, in the method inFIG. 7, a situation where the transistors M1and M2are simultaneously turned on may exist even within a short time. If the length of a period in which the transistors M1and M2are simultaneously turned on is short enough, no substantial problem would be incurred. However, in order to reliably prevent the transistors M1and M2from being turned on simultaneously, an improving method as shown inFIG. 8may be used.

FIG. 8is a timing diagram near the time point tB1of the improving method. In the improving method, before the primary-side control portion10turns on the switch transistor M1, it sends the reference signal CMD1serving as the signal S1at the time point tB0(the reference signal CMD1is referred to as a reference signal221a). The reference signal221ais for providing a notification for turning on the switch transistor M1, and is for providing an instruction for turning off the SR transistor M2(or for providing an instruction for ensuring a turned-off state of the SR transistor M2). In the example inFIG. 8, at the time point tB0, the transistors M1and M2are respectively in a turned-off state and a turned-on state; however, under the control of the secondary-side control portion20, the SR transistor M2may also be turned off according to the voltage VAbefore the time point tB0. The secondary-side control portion20receiving the reference signal221a(CMD1) ensures a turned-off state of the SR transistor M2, and sends a response signal ACK2serving as the signal S2(the response signal ACK2is referred to as a response signal222a). The primary-side control portion10turns on the switch transistor M1at the time point tB1in response to the response signal222areceived. The primary-side control portion10does not turn on the switch transistor M1but keeps it in a turned-off state, given that the response signal222ais not received. Thus, the transistors M1and M2are prevented from being turned on simultaneously, thereby enhancing the safety of the DC/DC converter1.

The embodiment EX2_3 is described below. In the embodiment EX2_3, it is assumed that the secondary-side control portion20is the master, and the primary-side control portion10is the slave. Further, the secondary-side control portion20of the embodiment EX2_3 instructs, according to the secondary-side voltage VS(according to the voltage VBin the structure inFIG. 1) the primary-side control portion10by sending a reference signal CMD2, to turn on and turn off the switch transistor M1, hence controlling turn-on and turn-off of the switch transistor M1. For example, the secondary-side control portion20may use PWM (pulse width modulation) to send the reference signal CMD2so as to supply a pulse signal having a duty cycle corresponding to the secondary-side voltage VSto the gate of the switch transistor M1, or may use PFM (pulse frequency modulation) to send the reference signal CMD2so as to supply a pulse signal having a frequency corresponding to the secondary-side voltage VSto the gate of the switch transistor M1. At this point, the secondary-side control portion20may control turn-on and turn-off of the switch transistor M1by sending the reference signal CMD2and by means of having the secondary-side voltage VSfollow the target voltage VTG(that is, by means of having a difference between the voltages VSand VTGbe zero) according to the voltage Vu corresponding to the secondary-side voltage VS.

In the embodiment EX2_3, without sending the feedback signal VFBto the primary-side control portion10, the secondary-side control portion20is used as the master to control the switch transistor M1corresponding to the secondary-side voltage VS, and thus the feedback circuit40and the optocoupler41may be omitted from the DC/DC converter1.

FIG. 9shows a timing diagram of the DC/DC converter1according to the embodiment EX2_3. In the example inFIG. 9, before arriving at a time point tC0, the transistors M1and M2are respectively in a turned-off state and a turned-on state. Under the control of PWM or PFM used, upon arriving at the time point for turning on the switch transistor M1, the secondary-side control portion20ensures at the time point tee that the transistor M2is in a turned-off state, and sends a reference signal CMD2serving as the signal S2(the reference signal CMD2is referred to as a reference signal231). In the example inFIG. 9, the SR transistor M2is turned off at the time point tC0; however, under the control of the secondary-side control portion20, the SR transistor M2may also be turned off according to voltage VAbefore the time point tC0. The reference signal231is for providing an instruction for turning on the switch transistor M1. The primary-side control portion10immediately turns on the switch transistor M1upon receiving the reference signal231(CMD2), and sends a response signal ACK1serving as the signal S1(the response signal ACK1is to be referred to as a response signal232). A time point tC1subsequent to the time point tC0represents a time point for turning on the switch transistor M1.

Then, under the control of PWM or PFM used, upon arriving at the time point for turning off the switch transistor M1, the secondary-side control portion20sends a reference signal CMD2serving as the signal S2(the reference signal CMD2is referred to as a reference signal233) at a time point tC2. The reference signal233is for providing an instruction for turning off the switch transistor M1. The primary-side control portion10immediately turns off the switch transistor M1upon receiving the reference signal233(CMD2), and sends a response signal ACK1serving as the signal S1(the response signal ACK1is referred to as a response signal234). A time point tC3subsequent to the time point tC2represents a time point for turning off the switch transistor M1.

The secondary-side control portion20turns on the SR transistor M2in response to the response signal234received. The secondary-side control portion20does not turn on the SR transistor M2but keeps the SR transistor M2in a turned-off state, given that the response signal234is not received. The secondary-side control portion20may also turn on the SR transistor M2only when the response signal234is received and upon detecting that the voltage VAis lower than the predetermined negative turn-on determination voltage (e.g., −100 mV). Later, upon arriving at the time point for turning on and the time point for turning off the switch transistor M1, the same actions are repeated.

Further, as described in the first embodiment, if the response signal ACK1(232and234inFIG. 9) is not received after having sent the reference signals CMD2(231and233inFIG. 9), the secondary-side control portion20may also perform a communication error process.

According to the embodiment EX2_3, the transistors M1and M2are reliably prevented from being turned on simultaneously, thereby enhancing safety of the DC/DC converter1. Further, because the secondary-side control portion20capable of directly observing the secondary-side voltage VSis capable of controlling turn-on and turn-off of the switch transistor M1, compared to the method in which the primary-side control portion10controls turn-on and turn-off of the switch transistor M1according to the feedback signal VFB, the stability of the secondary-side voltage VSand the responding ability of a load device may be enhanced.

Third Embodiment

The third embodiment of the present invention is described below. The actions of the DC/DC converter1in the description associated with the first and second embodiments are fundamentally equivalent to the actions after the DC/DC converter1is activated normally (the normal actions mentioned below). In the third embodiment, actions of the DC/DC converter1after activation are described below.

FIG. 10shows a flowchart of a process of actions of activation of the DC/DC converter1. A state in which no voltage is inputted to the DC/DC converter1and the primary-side voltage VPand the secondary-side voltage VSare 0 V is regarded as a starting point. When a required voltage is inputted to the DC/DC converter1in step STP11(that is to say, when the primary-side voltage VPrises up to a predetermined positive voltage), a power voltage VCC required is inputted to the primary-side control portion10after the activation of the primary-side power circuit11, and the primary-side control portion10is thus activated. Soon after the primary-side control portion10is activated, the communication error flag FLG1(referring toFIG. 3(a)) is set to “1”.

Upon activation of the primary-side control portion10, a surge charge action (an initialization action) of the primary-side control portion10may be performed in step STP12. In the surge charge action, the primary-side control portion10performs switch-driving of the switch transistor M1regardless of the value of the secondary-side voltage VS. That is to say, for example, in a structure in which turn-on and turn-off of the switch transistor M1are controlled according to the feedback signal VFBin the normal actions as in the embodiment EX2_1 or EX2_2, switch-driving of the switch transistor M1is performed regardless of the value of the feedback signal VFBin the surge charge action. Further, for example, in a structure in which turn-on and turn-off of the switch transistor M are controlled according to the reference signal CMD2(the reference signal CMD2based on the secondary-side voltage VS) from the secondary-side control portion20in the normal actions as in the embodiment EX2_3, switch-driving of the switch transistor M1is performed regardless of the value of the reference signal CMD2in the surge charge action.

In the surge charge action, the signal corresponding to the current, i.e., the current detection signal VCS, flowing in the switch transistor M1may be used. That is to say, for example, in the surge charge action, at a time point at which the voltage value of the current detection signal VCSreaches a predetermined value after the primary-side control portion10turns on the switch transistor M1, a unit action of turning off the switch transistor M1may be periodically and repeatedly performed. Upon having performed the unit action for a predetermined number of times or having repeatedly performed the unit action for a predetermined surge charge period, the surge charge action ends. Alternatively, the surge charge action may also be ended when the primary-side control portion10receives a secondary-side activation signal below.

When the secondary-side voltage VSrises to higher than a predetermined voltage by having performed the surge charge action, the secondary-side control portion20is activated in step STP13. Soon after the activation of the secondary-side control portion20, the communication error flag FLG2(referring toFIG. 3(b)) is set to “1”. When the secondary-side control portion20is activated, the secondary-side control portion20may also send a predetermined secondary-side activation signal serving as the signal S2to the primary-side control portion10.

After the secondary-side control portion20is activated, handshake communication is performed in step STP14. The handshake communication may begin after the surge charge action ends, or may begin during the execution process of the surge charge action. In a structure in which the secondary-side activation signal is sent in conjunction with the activation of the secondary-side control portion20, handshake communication may be performed as the secondary-side control portion20sends the secondary-side activation signal, or as the primary-side control portion10receives the secondary-side activation signal. Further, for example, handshake communication may also be performed by using a condition that the surge charge action is performed only at a fixed time point (in this case, a sending entity of the initial signal in the handshake communication is the primary-side control portion10).

The handshake communication is formed by exchanging of more than one reciprocating signal between the primary-side control portion10and the secondary-side control portion20through the pulse transformer portion30.

FIG. 11shows a process of handshake communication HS1as an example of handshake communication. The handshake communication HS1is used when the primary-side control portion10is the master and the secondary-side control portion20is the slave (however, the handshake communication HS1may also be performed when the secondary-side control portion20is the master).

In the handshake communication HS1inFIG. 11, first, the primary-side control portion10sends a signal311as the signal S1to the secondary-side control portion20, the secondary-side control portion20receiving the signal311sends a signal312as the signal S2to the primary-side control portion10, the primary-side control portion10receiving the signal312sends a signal313as the signal S1to the secondary-side control portion20, and the secondary-side control portion20receiving the signal313sends a signal314as the signal S2to the primary-side control portion10. The signals311and313serve as the reference signal CMD1to exercise a due function, and the signals312and314serve as the response signal ACK2to exercise a due function. The handshake communication HS1is correctly completed after the primary-side control portion10receives the signal314. In a structure in which the secondary-side activation signal is sent in conjunction with the activation of the secondary-side control portion20, the signal311may also be sent as the primary-side control portion10receives the secondary-side activation signal.

The signals311to313are check signals for determining whether bi-directional communication may be performed between the control portions10and20. The primary-side control portion10may determine the bi-directional communication performed between the control portions10and20by receiving the signal312. The secondary-side control portion20may determine the bi-directional communication performed between the control portions10and20by receiving the signals311and313. The secondary-side control portion20sets the communication error flag FLG2stored therein to “0” when it sends the signal314, and the primary-side control portion10sets the communication error flag FLG1stored therein to “0” when it receives the signal314. Thus, the flags FLG1and FLG2are respectively set to “0” in a phase in which the handshake communication HS1is correctly completed. The two parties having the flags FLG1and FLG2set to “0” indicate that the bi-directional communication between the control portions10and20may be normally performed.

FIG. 12shows a process of handshake communication HS2as another example of handshake communication. The handshake communication HS2is used when the secondary-side control portion20is the master and the primary-side control portion10is the slave (however, the handshake communication HS2may also be performed when the primary-side control portion10is the master).

In the handshake communication HS2inFIG. 12, first, first, the secondary-side control portion20sends a signal321as the signal S2to the primary-side control portion10, the primary-side control portion10receiving the signal321sends a signal322as the signal S to the secondary-side control portion20, the secondary-side control portion20receiving the signal322sends a signal323as the signal S2to the primary-side control portion10, and the primary-side control portion10receiving the signal323sends a signal324as the signal S1to the secondary-side control portion20. The signals321and323serve as the reference signal CMD2to exercise a due function, and the signals322and324serve as the response signal ACK1to exercise a due function. The handshake communication HS2is correctly completed after the secondary-side control portion20receives the signal324. In a structure in which the secondary-side activation signal is sent in conjunction with the activation of the secondary-side control portion20, the secondary-side activation signal may also serve as the signal321to exercise a due function.

The signals321to323are check signals for determining whether bi-directional communication may be performed between the control portions10and20. The secondary-side control portion20may determine the bi-directional communication performed between the control portions10and20by receiving the signal322. The primary-side control portion10may determine the bi-directional communication performed between the control portions10and20by receiving the signals321and323. The primary-side control portion10sets the communication error flag FLG1stored therein to “0” when it sends the signal324, and the secondary-side control portion20sets the communication error flag FLG2stored therein to “0” when it receives the signal324. Thus, the flags FLG1and FLG2are respectively set to “0” in a phase in which the handshake communication HS2is correctly completed.

Further description is given again with reference toFIG. 10. Step STP16is performed after the handshake communication (e.g., HS1or HS2) is correctly completed, and normal actions begin. That is to say, switch-driving of the switch transistor M1for stabilizing the secondary-side voltage VStoward the target voltage VTGwith reference to the secondary-side voltage VSas described in the first or second embodiment begins. For example, actions for controlling turn-on and turn-off of the transistors M1and M2included in the embodiment EX2_1, EX2_2 or EX2_3 are regarded normal actions and are begun. Further, before the normal actions begin in step STP16, the SR transistor M2is kept turned off.

On the other hand, before the handshake communication is correctly completed, the normal actions do not begin and step STP17is performed from step STP15. In step STP17, the switch transistor M1is kept in a turned-off state for a predetermined period by using the primary-side control portion10, and then the process returns to step STP12to again perform the surge charge action. Further, step STP12may not be repeated after step STP17is performed, and the power voltage VCC supplied to the primary-side control portion10may be interrupted to maintain the turned-off state of the transistor M1(in this case, plugging/unplugging of a plug of the DC/DC converter1needs to be again activated if the primary-side voltage VPis generated according to a commercial AC voltage supplied by the plug).

For example, when the handshake communication HS1inFIG. 11is performed, if the primary-side control portion10does not receive the signal312after a predetermined period subsequent to having sent the signal311, or if the primary-side control portion10does not receive the signal314after a predetermined period subsequent to having sent the signal313, it is determined that the handshake communication is not correctly completed, and step STP17is performed from step STP15.

Alternatively, for example, when the handshake communication HS2inFIG. 12is performed, if the primary-side control portion10does not receive the signal323after a predetermined period subsequent to having sent the signal322, it is determined that the handshake communication is not correctly completed, and step STP17is performed from step STP15.

Further, for example, when the handshake communication HS2inFIG. 12is performed, if the secondary-side control portion20does not receive the signal322after a predetermined period subsequent to having sent the signal321, or if the secondary-side control portion20does not receive the signal324after a predetermined period subsequent to having sent the signal323, the bi-directional communication cannot correctly exercise a due function, and the secondary-side control portion20cannot learn the state of the primary-side circuit. At this point, the communication error flag FLG2is set to “1”, and thus the SR transistor M2does not become a turned-on state so as to prevent the transistors M1and M2from being turned on simultaneously. Further, at this point, if the secondary-side control portion20is the master, the switch transistor M1is not turned on when the method of the embodiment EX2_3 is used, such that the communication error process is promptly performed to ensure that the transistors M1and M2are in a turned-off state, even when the primary-side control portion10is the master.

Using the method described above, normal actions may begin while guaranteeing the normal state of bi-directional communication. That is to say, normal actions are prohibited in a condition where bi-directional communication is incomplete, thus preventing unexpected situations associated with safety.

Further, after the primary-side control portion10is activated, if certain abnormality is detected in the primary-side control portion10, the primary-control portion10may send a signal indicating the subject in the handshake communication to the secondary-side control portion10, and then step STP17may then be performed in this case. Similarly, for example, after the secondary-side control portion20is activated, if certain abnormality is detected in the secondary-side control portion20, the secondary-control portion20may send a signal indicating the subject in the handshake communication to the primary-side control portion10, and then step STP17may similarly be performed in this case. Further, the abnormality is described in other embodiments below.

When abnormality occurs in one of the control portions10and20, normal actions (e.g., switch-driving of the switch transistor M1, or controlling turn-on and turn-off of the SR transistor M2) whether the abnormality occurs in the other are preferably not performed, because the DC/DC converter1or a load device thereof may be degraded or damaged as a result of the content of the abnormality. Such undesirable situation may be prevented according to the method above.

Fourth Embodiment

The fourth embodiment of the present invention is described below. In the fourth embodiment, reactive measures for handling abnormality occurring in the primary-side control portion10or the secondary-side control portion20are described.

As shown inFIG. 13, a primary-side abnormality detection portion15for detecting whether abnormality exists in the primary-side circuit (particularly, for example, in the primary-side control portion10) is provided in the primary-side control portion10, and a secondary-side abnormality detection portion25for detecting whether abnormality exists in the secondary-side circuit (particularly, for example, in the secondary-side control portion20) is provided in the secondary-side control portion20.

The primary-side abnormality detection portion15may also individually detect multiple types of abnormality. Examples of abnormality detectable to the primary-side abnormality detection portion15include primary-side overheat abnormality, primary-side over-voltage abnormality, primary-side under-voltage abnormality, current sensing abnormality and incomplete turn-off abnormality.

The primary-side overheat abnormality refers to a state in which the temperature of the primary-side control portion10or the temperature of the switch transistor M1becomes higher than a predetermined temperature T1_UL. The abnormality detection portion15may use a temperature sensor to detect whether primary-side overheat abnormality exists, and the temperature sensor outputs a signal corresponding to the temperature of the primary-side control portion15or the temperature of the switch transistor M1.

The primary-side over-voltage abnormality and the primary-side under-voltage abnormality respectively refer to a state in which the primary-side voltage VPbecomes higher than a predetermined upper voltage limit VP_UL and a state in which the primary-side voltage VPbecomes lower than a predetermined lower voltage limit VP_LL. The primary-side control portion10may detect, according to the primary-side voltage VPor a divided voltage of primary-side voltage VP, whether the primary-side over-voltage abnormality or the primary-side under-voltage abnormality exists. Further, considering a transition period of the primary-side voltage VP, after the primary-side control portion10is activated, the primary-side under-voltage abnormality may also be left undetected within a certain time period.

The current sensing abnormality refers to a state in which the value of the current detection signal VCS(that is, the voltage drop of the sensing resistor RCS) becomes lower than a predetermined threshold VCS1(the transistor M1is turned on at this point) after a predetermined period subsequent to having turned on the switch transistor M1. The current sensing abnormality may be detected when the sensing resistor RCSis short-circuited.

The incomplete turn-off abnormality refers to a state in which the value of the current detection signal VCS(i.e., the voltage drop of the sensing resistor RCS) is higher than a predetermined threshold although the switch transistor M1is controlled to be turned off (although the gate voltage of the transistor M1is a low level). The incomplete turn-off abnormality may be detected when the drain-source of the transistor M1is short-circuited.

The secondary-side abnormality detection portion25may also individually detect multiple types of abnormality. Examples of abnormality detectable to the secondary-side abnormality detection portion25include secondary-side overheat abnormality, secondary-side over-voltage abnormality, and secondary-side under-voltage abnormality.

The secondary-side overheat abnormality refers to a state in which the temperature of the secondary-side control portion20or the temperature of the SR transistor M2becomes higher than a predetermined temperature T2_UL. The abnormality detection portion25may use a temperature sensor to detect whether the secondary-side overheat abnormality exists, and the temperature sensor outputs a signal corresponding to the temperature of the secondary-side control portion20or the temperature of the SR transistor M2.

The secondary-side over-voltage abnormality and the secondary-side under-voltage abnormality respectively refer to a state in which the secondary-side voltage VSbecomes higher than a predetermined upper voltage limit VS_UL and a state in which the secondary-side voltage VSbecomes lower than a predetermined lower voltage limit VS_LL. The secondary-side control portion20may detect, according to the secondary-side voltage VS(according to the voltage VBin the structure inFIG. 1), whether the secondary-side over-voltage abnormality or the secondary-side under-voltage abnormality exists. In a stable state, the secondary-side over-voltage abnormality or the secondary-side under-voltage abnormality should not occur, however, such abnormality may occur due to malfunction of certain components. Further, considering a transition period of the secondary-side voltage VS, after the secondary-side control portion20is activated, the secondary-side under-voltage abnormality may also be left undetected within a certain time period.

In the embodiments EX4_1 to EX4_4 included in the fourth embodiment, examples of actions when abnormality is detected by the abnormality detection portion15or25are described. Further, the actions illustrated in the embodiments EX4_1 to EX4_4 may also be understood as actions after the normal actions have begun. Further, the abnormality detected refers to in specifically that abnormality has been detected.

The embodiment EX4_1 is described below. In the embodiment EX4_1, it is assumed that the primary-side control portion10is the master and the secondary-side control portion20is the slave, and the primary-side abnormality detection portion15detects any abnormality (for illustration purposes, the abnormality is referred to as abnormality AB1).

Actions of the primary-side control portion10when the abnormality AB1is detected are described. When the abnormality AB1is detected, the primary-side control portion10stops switch-driving of the switch transistor M1. The so-called stopping of the switch transistor M1refers to immediately keeping the transistor M1in a turned-off state if the transistor M1is in a turned-on state, and directly keeping the transistor M1in a turned-off state if the transistor M1is already in a turned-off state. The stopping of the switch-driving of the transistor M1is continued until the abnormality AB1detected has been eliminated. Further, when the abnormality AB1is detected, the primary-side control portion10sends an abnormality detection signal S1(a primary-side abnormality detection signal) indicating the abnormality AB1detected to the secondary-side control portion20, and sending of the signals for implementing normal actions is stopped. The stopping of the sending of the signals for implementing normal actions refers to not sending the reference signal CMD1(211,213and211ainFIG. 5andFIG. 6) when the embodiment EX2_1 is used, and not sending the reference signal CMD1(221,223and221ainFIG. 7andFIG. 8) when the embodiment EX2_2 is used.

After having detected the abnormality AB1, the abnormality detection portion15is used to monitor whether the abnormality AB1is eliminated, and upon detecting that the abnormality AB1is eliminated, the primary-side control portion10sends a predetermined restoring signal S1to the secondary-side control portion20. Then, after a predetermined time period, if a response signal from the secondary-side control portion20in response to the restoring signal S1is received by the primary-side control portion10, the primary-side control portion10may then again start the normal actions. On the other hand, after the predetermined time period, if the response signal from the secondary-side control portion20in response to the restoring signal S1is not received by the primary-side control portion10, it is considered that the secondary-side voltage VShas dropped to a level at which driving of the secondary-side control portion20is stopped, and thus the primary-side control portion10may perform the process described in the third embodiment from the surge charge action of step STP12inFIG. 10.

Actions of the secondary-side control portion20when the abnormality AB1is detected are described. When the secondary-side control portion20receives the abnormality detection signal S1indicating the abnormality AB1, it sends a response signal in response to the signal received to the primary-side control portion10, ensures a turned-off state of the SR transistor M2, and then waits for the restoring signal sent from the primary-side control portion10. During the process of waiting, driving of the secondary-side control portion20is stopped when the secondary-side voltage VSdrops to lower than a predetermined reset voltage.

The embodiment EX4_2 is described below. In the embodiment EX4_2, it is assumed that the secondary-side control portion20is the master and the primary-side control portion10is the slave, and any abnormality AB1is detected by the primary-side abnormality detection portion15.

Actions of the primary-side control portion10when the abnormality AB1is detected are described below. When the abnormality AB1is detected, the primary-side control portion10stops switch-driving of the switch transistor M1. Switch-driving of the switch transistor M1is stopped until it is detected that the abnormality AB1is eliminated. Further, when the abnormality AB1is detected, the primary-side control portion10sends an abnormality detection signal S1(a primary-side abnormality detection signal) indicating the abnormality AB1to the secondary-side control portion20.

After having detected the abnormality AB1, the abnormality detection portion15is used to monitor whether the abnormality AB1is eliminated, and upon detecting that the abnormality AB1is eliminated, the primary-side control portion10sends a predetermined restoring signal S1to the secondary-side control portion20. Next, after a predetermined time period, if a response signal from the secondary-side control portion20in response to the restoring signal S1is received by the primary-side control portion10, the stopping of the switch-driving of the switch transistor M1is removed, and the switch-driving may again begin under the control of the secondary-side control portion20serving as the master. On the other hand, after the predetermined time period, if the response signal from the secondary-side control portion20in response to the restoring signal S1is not received by the primary-side control portion10, it is considered that the secondary-side voltage VShas dropped to a level at which driving of the secondary-side control portion20is stopped, and thus the primary-side control portion10may perform the process described in the third embodiment from the surge charge action of step STP12inFIG. 10.

Actions of the secondary-side control portion20when the abnormality AB1is detected are described. When the secondary-side control portion20receives the abnormality detection signal S1indicating the abnormality AB1, it sends a response signal in response to the signal received to the primary-side control portion10, ensures a turned-off state of the SR transistor M2, stops sending of signals for implementing normal actions, and then waits for the restoring signal sent from the primary-side control portion10. The so-called stopping of the signals for implementing the normal actions refers to not sending the reference signal CMD2(231and233inFIG. 9) when the embodiment EX2_3 is used. During the process of waiting, driving of the secondary-side control portion20is stopped when the secondary-side voltage VSdrops to lower than a predetermined reset voltage.

The embodiment EX4_3 is described below. In the embodiment EX4_3, it is assumed that the primary-side control portion10is the master and the secondary-side control portion20is the slave, and any abnormality is detected by the secondary-side abnormality detection portion25(for illustration purposes, the abnormality is referred to as abnormality AB2).

Actions of the secondary-side control portion20when the abnormality AB2is detected are described below. When the abnormality AB2is detected, the secondary-side control portion20ensures a turned-off state of the SR transistor M2, and the keeps a turned-off state of the SR transistor M2given that elimination of the abnormality AB2is not detected later. Further, when the abnormality AB2is detected, the secondary-side control portion20sends an abnormality detection signal S2(a secondary-side abnormality detection signal) indicating the abnormality AB2to the primary-side control portion10.

After having detected the abnormality AB2, the abnormality detection portion25is used to monitor whether the abnormality AB2is eliminated, and the secondary-side control portion20sends a predetermined restoring signal S2to the primary-side control portion10upon detecting that the abnormality AB2is eliminated. When no abnormality AB2is detected and the secondary-side voltage VSdrops to lower than a predetermined reset voltage, driving of the secondary-side control portion20is stopped.

Actions of primary-side control portion10when the abnormality AB2is detected are described below. When the primary-side control portion10receives the abnormality detection signal S2from the secondary-side control portion20, it sends a response signal in response to the signal received to the secondary-side control portion20, stops switch-driving of the switch transistor M1, and in conjunction stops sending signals for implementing normal actions. The so-called stopping of the signals for implementing normal actions refers to not sending the reference signal CMD1(211,213and211ainFIG. 5andFIG. 6) when the embodiment EX2_1 is used, and not sending the reference signal CMD1(221,223and221ainFIG. 7andFIG. 8) when the embodiment EX2_2 is used.

The stopping of the switch-driving of the switch transistor M is in principle continued until the restoring signal S2from the secondary-side control portion20is received. However, after receiving the abnormality detection signal S2, even if the restoring signal S2is not received after a predetermined time period, it is considered that the secondary-side voltage VShas dropped to a level at which the driving of the secondary-side control portion20is stopped, and thus the primary-side control portion10may perform the process described in the third embodiment from the surge charge action of step STP12inFIG. 10.

The embodiment EX4_4 is described below. In the embodiment EX4_4, it is assumed that the secondary-side control portion20is the master and the primary-side control portion10is the slave, and any abnormality AB2is detected by the secondary-side abnormality detection portion25.

Actions of the secondary-side control portion20when the abnormality AB2is detected are described below. When the abnormality AB2is detected, the secondary-side control portion20ensures a turned-off state of the SR transistor M2, and the keeps a turned-off state of the SR transistor M2given that elimination of the abnormality AB2is not detected later. Further, upon having detected the abnormality AB2, the secondary-side control portion20sends a predetermined abnormality detection signal S2(a secondary-side abnormality detection signal) indicating the abnormality AB2detected to the primary-side control portion10, and then stops sending signals implementing normal actions. The so-called stopping of the signals for implementing the normal actions refers to not sending the reference signal CMD2(231and233inFIG. 9) when the embodiment EX2_3 is used.

After having detected the abnormality AB2, the abnormality detection portion25is used to monitor whether the abnormality AB2is eliminated, and the secondary-side control portion20sends a predetermined restoring signal S2to the primary-side control portion10upon detecting that the abnormality AB2is eliminated. When no abnormality AB2is detected and the secondary-side voltage VSdrops to lower than a predetermined reset voltage, driving of the secondary-side control portion20is stopped.

Actions of primary-side control portion10when the abnormality AB2is detected are described below. When the primary-side control portion10receives the abnormality detection signal S2from the secondary-side control portion20, it sends a response signal in response to the signal received to the secondary-side control portion20, and stops switch-driving of the switch transistor M1.

The stopping of the switch transistor M1is in principle continued until the primary-side control portion10receives the restoring signal S2from the secondary-side control portion20. However, after receiving the abnormality detection signal S2, even if the restoring signal S2is not received after a predetermined time period, it is considered that the secondary-side voltage VShas dropped to a level at which the driving of the secondary-side control portion20is stopped, and thus the primary-side control portion10may perform the process described in the third embodiment from the surge charge action of step STP12inFIG. 10.

Further, under any situation of the embodiments EX4_1 to EX4_4, after the abnormality AB1or AB2is temporarily detected, a turned-off state of the transistors M1and M2may also be continued until the power voltage VCC supplied to the primary-side control portion10is interrupted (in this case, plugging/unplugging of a plug of the DC/DC converter1needs to be again activated if the primary-side voltage VPis generated according to a commercial AC voltage supplied by the plug).

Fifth Embodiment

The fifth embodiment of the present invention is described below. The structure of an insulation synchronous rectification-type DC/DC converter serving as the DC/DC converter1is described. However, the DC/DC converter1of the present invention may be any insulation-type DC/DC converter in which the primary-side voltage VPapplied to the primary-side winding W1generates the secondary-side voltage VSon the secondary side of the transformer TR.

For example, in the DC/DC converter1shown inFIG. 1, a so-called low-end application is used; however, a high-end application may also be used. In the DC/DC converter1using a high-end application, the SR transistor M2is provided on the side of the output terminal TM2A, and the SR transistor M2is connected in series between the output terminal TM2Aapplied with the secondary-side voltage VSand the secondary-side winding W2of the transformer TR. Further, without compromising the form of the subject matter of the present invention, the position for disposing the SR transistor M2in the secondary-side circuit may be modified.

Further, for example, the DC/DC converter1may also be implemented by a DC/DC converter using a rectification diode (an insulation diode rectification-type DC/DC converter). In this case, in the DC/DC converter1, the rectification diode is disposed at the secondary-side circuit, in substitution for the SR transistor M1and the parasitic diode D2inFIG. 1. The rectification diode placed between the secondary-side winding W2and the capacitor C2, and performs rectification on power transmitted from the primary-side winding W1to the secondary-side winding W2. When the DC/DC converter1is structured as the diode rectification-type DC/DC converter, the description associated with the control for the SR transistor M2in the first to fourth embodiment is omitted.

Further, for example, the DC/DC converter1may also be structured as a forward insulation-type DC/DC converter. In this case, any one of a synchronous rectification type or the diode rectification type may be used.

Sixth Embodiment

The sixth embodiment of the present invention is described below. In the sixth embodiment, the purpose of the insulation-type DC/DC converter is described.

As shown inFIG. 14, the structure of the insulation-type DC/DC converter of the present invention may be used to form an AC/DC converter600. The AC/DC converter600includes a filter601, a rectification circuit602, a smoothing capacitor603and an insulation-type DC/DC converter604. The filter601removes noise from an AC voltage VACinputted to the AC/DC converter600. The AC voltage VACmay also be a commercial AC voltage. The rectification circuit602is a diode bridge circuit that performs full-wave rectification on the AC voltage VACsupplied from the filter601. The smoothing capacitor603smooths the voltage having undergone full-wave rectification to generate a DC voltage. The insulation-type DC/DC converter604receives the DC voltage generated by the smoothing capacitor603as the primary-side voltage VP, and causes the primary-side voltage VPto undergo power conversion (DC-DC conversion) to generate the secondary-side voltage VS. The secondary-side voltage VSis equivalent to the output voltage of the AC/DC converter600. The DC/DC converter1of any one of the first to fifth embodiments may be used as the insulation-type DC/DC converter604. In this case, the capacitor C1inFIG. 1is equivalent to the smoothing capacitor603.

The AC/DC converter600may also be used to form a power adapter.FIG. 15shows a diagram of a power adapter620including the AC/DC converter600. The power adapter620includes the AC/DC converter600, a plug621, a housing622and an output connector623, and the AC/DC converter600is accommodated and disposed in the housing622. The plug621receives the commercial AC voltage VACfrom the plug that is not shown, and the AC/DC converter600generates the DC secondary-side voltage VSfrom the commercial AC voltage VACinputted from the plug. The secondary-side voltage VSis supplied through the output connector623to any electronic device that is not shown in the diagram. For example, the electronic device is a laptop personal computer, an information terminal device, a digital camera, a digital video camera, a mobile phone (including a mobile phone categorized as a smartphone), and a portable audio player.

An electronic device including the AC/DC adapter may also be formed.FIGS. 16(a) and (b)show diagrams of an electronic device640including the AC/DC converter600. The electronic device640shown inFIGS. 16(a) and (b)is a display device; however, the type of the electronic device640is not specifically limited, and may be any machine built-in with an AC/DC converter, such as a video/audio apparatus, a refrigerator, a washing machine or a vacuum cleaner. The electronic device640includes the AC/DC converter600, a plug641, a housing642and a load device643, and the AC/DC converter600and the load device643are accommodated and disposed in the housing642. The plug641receives the commercial AC voltage VACfrom a plug that is not shown, and the AC/DC converter600generates the DC secondary-side voltage VSfrom the commercial AC voltage VACinputted from the plug641. The secondary-side voltage VSgenerated is supplied to the load device643. The load device643may be any load device driven based on the secondary-side voltage VS, for example, a microcomputer, a digital signal processor (DSP), a power circuit, a lighting machine, an analog circuit or a digital circuit.

Seventh Embodiment

The seventh embodiment is described below. In the seventh embodiment, application techniques and variation techniques applicable to the first to sixth embodiments are described.

In the structure inFIG. 1, the function of sending information corresponding to the secondary-side voltage VSto the primary-control side10may be implemented by using the optocoupler41; however, the function may also be implemented by using the pulse transformer portion30. In this case, the feedback circuit40and the optocoupler41may be omitted from the structure inFIG. 1. That is to say, for example, the secondary-side control portion20may also send the signal S2including information corresponding to the secondary-side voltage VSthrough the pulse transformer portion30to the primary-side control portion10.

An exemplary structure of the pulse transformer portion30including two pulse transformers is described (referring toFIG. 2); however, the quantity of pulse transformer provided in the pulse transformer portion30may be one, and bi-directional communication between the control portions10and20may be implemented by one pulse transformer in a time-division manner. The method of achieving bi-directional communication by using one pulse transformer may include any method of known methods (e.g., the method stated in Japan Patent Publication No. 2007-209082).

A semiconductor device SMC1may be formed by integrating the primary-side control portion10, the secondary-side control portion20and the pulse transformer portion30into one chip on a semiconductor substrate. The semiconductor device SMC1is formed by integrating the primary-side control portion10, the secondary-side control portion20and the pulse transformer portion30, and accommodating and sealing the same in a package (housing) formed by resin.

Alternatively, a first chip formed by integrating the primary-side control portion10on a first semiconductor substrate, a second chip formed by integrating the secondary-side control portion20on a second semiconductor substrate, and a third chip formed by integrating the pulse transformer portion30on a third semiconductor substrate may be manufactured, and the first to third chips are accommodated and sealed in a common package (housing) to form a semiconductor device SMC2.

However, the primary-side control portion10and the secondary-side control portion20may also be formed as separate semiconductor devices. That is to say, the first chip formed by integrating the primary-side control portion10on the first semiconductor substrate is accommodated and sealed in a first package to form a semiconductor device SMC3A, and in a separate manner, the second chip formed by integrating the secondary-side control portion20on the second semiconductor substrate is accommodated and sealed in a second package to form a semiconductor device SMC3B. In this case, the pulse transformer portion30may also be a discrete component separately provided from the semiconductor devices SCM3A and SCM3B; however, the pulse transformer portion30may also be integrated as a third chip on a third semiconductor substrate, and be accommodated and sealed in a third package to form a semiconductor device SMC3C. In the semiconductor devices SCM3A. SCM3B and SMC3C, existing integrated circuit processes may be used to form the pulse transformer.

Alternatively, a semiconductor device (SCM3A, SCM3Bor SMC3C) integrating the primary-side control portion10may be integrated to include the switch transistor M1, or be integrated to include the sensing resistor RCS.

Alternatively, a semiconductor device (SCM3A, SCM3Bor SMC3C) integrating the secondary-side control portion20may be integrated to include the SR transistor M2, may be further integrated to include the voltage dividing resistors R1and R2, and may be further integrated to include the voltage dividing resistors R3and R4.

Without compromising the form of the subject matter, the relationship between a high level and a low level of any signal or voltage may be the opposite. Further, without compromising the form of the subject matter, the channel type of the FET may be modified as desired.

Each of the transistors may be any type of transistor. For example, a transistor serving as the MOSFET may be replaced by a junction-type FET, an insulated gate bipolar transistor, or a bipolar transistor. Any transistor may include a first electrode, a second electrode and a control electrode. In an FET, one of the first and second electrodes is a drain and the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector and the other is an emitter, and the control electrode is a gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is a collector and the other is an emitter, and the control electrode is a base.

Various modifications within the scope of the inventive concept demonstrated in the claims may be appropriately made to the embodiments of the present invention. The embodiments above are merely examples of the embodiments of the present invention, and meanings of the terms of the components and elements of the present invention are not limited to the meanings stated in the embodiments above. The specific values given in the description are purely examples, and may be modified to various other values.