SEMICONDUCTOR STRUCTURE WITH TESTLINE AND METHOD OF FABRICATING SAME

A testline structure of a semiconductor device includes a substrate layer, a frontside insulating layer atop the substrate layer, a backside insulating layer under the substrate layer, and a probe pad structure vertically extending through the frontside insulating layer, the substrate layer, and the backside insulating layer. The probe pad structure includes a frontside probe pad in the frontside insulating layer and a backside probe pad in the backside insulating layer.

BACKGROUND

Recently, backside power rails have been introduced in an effort to reduce resistance in IC power routing and reduce voltage drop across power rails. Conventionally, transistor devices (e.g., fin field-effect transistor (FinFET) device and gate-all-around (GAA) device) are built in a stacked-up fashion, having transistors at the lowest level and interconnect (vias and wires) on top of the transistors to provide connectivity to the transistors. Power rails (such as metal lines for voltage sources and ground planes) are also above the transistors and may be part of the interconnect. As the integrated circuits continue to scale down, so do the power rails. This leads to increased voltage drop across the power rails, as well as increased power consumption of the integrated circuits. The implementation of backside power rails increases the number of power rails available in an IC for directly providing power to transistor devices. It also increases the gate density for greater device integration than existing structures without the backside power rails. On the other hand, existing testline structures are still formed on top of the transistors, without fully adopting advantages provided by the backside power rail technology. Therefore, although existing approaches in testline structures have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term encompasses numbers that are within certain variations (such as +/−10% or other variations) of the number described, in accordance with the knowledge of the skilled in the art in view of the specific technology disclosed herein, unless otherwise specified. For example, the term “about 5 nm” may encompass the dimension range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

The present disclosure generally relates to the testing of integrated circuits (ICs), and more particularly to the testline structure on an integrated circuit wafer substrate for wafer acceptance testing (WAT), process control monitoring (PCM), and/or failure analysis (FA) needs.

In integrated circuit manufacturing, a semiconductor wafer typically contains a plurality of testlines in the scribe line area between adjacent wafer dies. Each testline includes a number of devices under test (DUTs), which are structures similar to those that are normally used to form the integrated circuit products in the wafer die area. DUTs are usually formed in the test pattern areas between adjacent probe pads on a testline at the same time as the functional circuitry using the same process steps. Probe pads are usually flat, square metal surfaces on a testline through which test stimuli can be applied to corresponding DUTs. Parametric test results on DUTs are usually utilized to monitor, improve and refine a semiconductor manufacturing process. Yield of test structures on a testline is often used to predict the yield of functional integrated circuitries in the die area.

Following the continuous scale down in device feature sizes in an integrated circuit in order to meet the increasing demand of integrating more complex circuit functions on a single chip, power rails in an integrated circuit need further improvement in order to provide the needed performance boost as well as reducing power consumption. Power rails (or power routings) on a back side (or backside) of a structure, which contains transistors (such as fin field-effect transistors (FinFETs) and/or gate-all-around (GAA) transistors) in addition to an interconnect structure (which may include power rails as well) on a front side (or frontside) of the structure, is also referred to as backside power rails. The implementation of backside power rails in IC manufacturing increases the number of metal tracks available in the structure for directly powering up transistors. It also increases the gate density for greater device integration than existing structures without the backside power rails. The backside power rails may have wider dimension than the first level metal (M0) tracks on the frontside of the structure, which beneficially reduces the power rail resistance.

On the other hand, the implementation of backside power rails has imposed new demands on the existing parametric testline structure. One of these demands is that testlines corresponding to backside power rail technology better provide backside testing structures to meet the test needs for advanced semiconductor devices and complex integrated circuits, such as providing backside probe pads to land probe needles from backside. Further, in view of the trends described above and other issues facing conventional testline structures and the ever-increasing testing tasks demanded by advanced technologies, there is a need for improved testline structures capable of housing more DUTs on a shrunk testline area, such as housing more DUTs on the backside of the structure.

FIG.1schematically illustrates a top view of a semiconductor device including integrated circuit components, seal rings, and testline structures, in accordance with some embodiments of the disclosure. InFIG.1, the semiconductor device may be a semiconductor wafer100including a base110having die regions110A and scribe line regions110B, dies120(including circuit region122and seal rings124), and testline structures (or testlines)130(including probe pads132). The dies120and the testlines130are fabricated on the base110. In some embodiments, each of the dies120may include integrated circuits therein and the integrated circuits may be formed by a plurality of components connected in required connection relationship to construct the specific circuits. In some embodiments, each of the dies120may be sealed with integrated circuits therein surrounded by the seal ring122. The die regions110A may refer to the regions where the dies120are. The scribe line regions110B may be distributed in between the die regions110A and may forms grid-like distribution in the semiconductor wafer100. The testlines130may be disposed on a layout region within the scribe line regions110B and positioned between the dies120. The probe pads132are also disposed on the scribe line regions110B.

In some embodiments, the testlines130may be formed on the semiconductor wafer100by using the processes and steps for forming the integrated circuits in the dies120. Accordingly, the testlines130and the dies120both include multiple components such as transistors and interconnection wiring such as redistribution layers may be formed on the base110for connecting the components based on the required design. After the transistors and the required wirings in the dies120are fabricated on the semiconductor wafer100, a test such as a wafer acceptance test (WAT) may be performed on the testlines130to determine the acceptance rate of the semiconductor wafer100. In some embodiments, the WAT may be performed before the dies120are completed so that the WAT may be an inter-metal WAT. In other words, after passing the inter-metal WAT, further fabrication processes may be performed on the semiconductor wafer100. In some embodiments, the WAT may be performed after the first level metal layer (M1) or the second level metal layer (M2) (the former layers among the metal layers in the interconnect structure) is formed. On the contrary, if the inter-metal WAT is not passed, the semiconductor wafer100may be considered as a failure wafer and no further fabrication process is performed thereon. Accordingly, the inter-metal WAT may facilitate to inspect the failure wafer in the middle stage of the fabrication process. In the wafer acceptance test, the testlines130may be electrically connected to an external circuit or probes of a probe card via the probe pads132to check the quality of the integrated circuit process. Once the semiconductor wafer100passes the test, the subsequent process for fabricating the final product may be performed to form the required final product. For example, the dies120may be packaged and singulated by cutting the semiconductor wafer100along the scribe line regions110B to obtain individual dies120. The cutting the semiconductor wafer100along the scribe line regions110B, the singulation process, may also separate the testlines130from the dies120so that the singulated die120in the final product may not include the testlines130. Alternatively, depending on the scribing width during the singulation process and location of the scribes, partial or full of the testlines130may remain with the singulated die120and is packaged together with the singulated die120.

FIG.2Aschematically illustrates a top view of an exemplary testline130, in accordance with some embodiments of the disclosure. The testline130is formed in a scribe line region110B between adjacent dies120. Each testline is made up by a serial number of aligned probe pads132. Each probe pad132has a square shape and may be made from metal or other electrically conductive materials (e.g., AlCu or NiPdAu—Cu). In some alternative embodiments, the probe pads132from the top view may be shaped as a circular pattern. The disclosure does not construe the shape of the probe pads. Area of a probe pad132may range from about 100 um2to about 10,000 um2. Probe pads132on the testline130are electrically connected to a plurality of DUTs134formed between adjacent probe pads. Pluralities of testlines with different DUTs are formed in scribe line regions across the semiconductor wafer100. The DUTs134are test structures in the form of resistors, capacitors, inductors, diodes, transistors, or the like, designed to measure device parameters, such as MOSFET Vt, contact/via chain resistance, sheet capacitance, gate oxide breakdown voltage, and the like. By studying these parameters, it is possible to monitor, improve and refine a semiconductor production process. In a testline, the number of DUTs may equal to or be less than the number of probe pads. In the illustrated embodiment, the exemplary testline130includes three DUTs134, namely a first DUT in the form of a resistor, a second DUT in the form of a capacitor, and a third DUT in the form of a transistor. On the other hand, the exemplary testline130includes five probe pads132. In some alternative embodiments, a testline may include dummy probe pads (not shown), which is electrically floating and not connected to any DUT.

Following the continuous scale down in device feature sizes in an integrated circuit in order to meet the increasing demand of integrating more complex circuit functions on a single chip, a similar trend has been urged upon the size and structure of a testline. That is the area of a testline must shrink with each technology generation to facilitate more wafer areas for functional integrated circuitries. On the other hand, as the continuing scale-down of device feature sizes and increased circuit complexity in an integrated circuit has imposed new demands on the testline structure such that testlines corresponding to advanced processing technology must include a large amount of DUTs of different types and dimensions to meet the test needs for advanced semiconductor devices and complex integrated circuits.FIG.2Billustrates an alternative layout of the exemplary testline130, which allows more testlines—thus more DUTs—to be accommodated in scribe line regions. Compared with the testline130inFIG.2Awhere the DUTs134and the probe pads132are interleaved along a straight line, inFIG.2Bthe DUTs134are all disposed in a DUT region136, which is aside the probe pads132. That is, inFIG.2B, the DUTs134are gathered in a DUT region136, and the probe pads132are lined up along an edge of the DUT region136and connected to respective DUTs134through metal traces. Such side-by-side arrangement better utilizes a width of a scribe line region, and allows a length of a testline to be reduced, which leads to more testlines accommodated in a scribe line region.FIG.2Bfurther illustrates a scribe line138. The scribe line138marks where the dies120are singulated. The scribe line138may travel through the region between the DUT region136and the probe pads132, such that a singulated die120in the final product may include the probe pads132.

FIG.3Aillustrates a schematic cross-section view of a portion of the exemplary testline130(dashed circle140inFIG.2A or2B), which includes one DUT134and two probe pads132associated with the DUT134. This portion of the testline structure comprises a substrate layer (or semiconductor substrate)150, a frontside insulating layer152formed atop the substrate layer150, a backside insulating layer154formed under the substrate layer150, and a DUT134formed in the frontside insulating layer152. Two probe pads132are electrically coupled to two terminals of the DUT134. Each probe pad132has an opposing backside probe pad132′. Thus, the probe pads132are also referred to as frontside probe pads. The structure extending from the frontside probe pad132to the backside probe pad132′ including interconnect structures therebetween is referred to as probe pad structure156. In a probe pad structure156, the frontside probe pad132is the topmost metal piece, and the backside probe pad132′ is the bottommost metal piece. A probe pad structure156is separated from an adjacent probe pad structure156. Each probe pad structure156includes a stacking via structure underlying the frontside probe pad132. The stacking via structure includes a metal piece (or referred to as metal pad) on each metal layer in the same shape as the probe pads132and coupled to each other through one or more vias. In some embodiments, metallic materials of the frontside probe pad132and the metal pieces in underneath metal layers (M1, M2, . . . Mx−1) of the stacking via structure may be different. For example, the frontside probe pad132may include AlCu or NiPdAu—Cu, and the metal pieces in underneath metal layers may include tungsten (W), aluminum (Al), or copper (Cu).

In the illustrated embodiment, the resistance of a via formed in a first level via layer (denoted as Via1), which is used to make electrical connection between metal layers M1and M2, is measured through the DUT134. To conduct Via1resistance measurement with desired test precision, a via chain comprising a plurality of Via1is first formed between M1and M2. Resistance of the via chain is measured and the resistance of an individual Via1is estimated therefrom. A via chain comprises an M2metal piece extending from an M2metal pad of the first probe pad structure156, a Via1connecting the M2metal piece to an M1metal piece, and another Via1connecting the M1metal piece to another M2metal piece, and repetition of such a zig-zag pattern. The zig-zag pattern continues until an end M2metal piece of the via chain meets an M2metal pad of the second probe pad structure156.

Unlike some conventional probe pad structures that is formed within the frontside insulating layer152only (e.g., with bottommost metal pieces starting from M1), the illustrated probe pad structure156includes a frontside portion formed in the frontside insulating layer152, a backside portion formed in the backside insulating layer154, and a middle portion formed in the substrate layer150. The middle portion electrically connects the frontside portion and the backside portion of the probe pad structure156. The frontside portion of the probe pad structure156includes a square shaped metal piece on each metal layer (e.g., M1, M2, . . . Mx−1, Mx) coupled to each other through one or more vias (e.g., Via1, . . . Via x−1). The frontside probe pad132is formed on the topmost metal layer Mx. The backside portion of the probe pad structure156includes a square shaped metal piece on each backside meta layer (e.g., BM1, BM2) coupled to each other through one or more backside vias (e.g., BVia1). The backside portion further includes the backside probe pad132′ formed on the bottommost backside metal layer (e.g., BM2in the illustrated embodiment). Thus, the probe pad structure156includes the frontside probe pad132and the backside probe pad132′ electrically coupled to each other. In some embodiments, metallic materials of the backside probe pad132′ and the metal pieces in other backside metal layers (e.g., BM1) may be different. For example, the backside probe pad132′ may include AlCu or NiPdAu—Cu, and the metal pieces in BM1may include tungsten (W), aluminum (Al), or copper (Cu).

The number of metal layers in the frontside portion of the probe pad structure156may be more than the number of backside metal layers in the backside portion of the probe pad structure156. In some alternative embodiments, the number of metal layers in the frontside portion of the probe pad structure156may equal to the number of backside metal layers in the backside portion of the probe pad structure156. The frontside portion is also referred to as frontside interconnect structure of the probe pad structure156; the backside portion is also referred to as backside interconnect structure of the probe pad structure156.

The middle portion of the probe pad structure156includes one or more doped epitaxial features158, contact plugs formed atop the doped epitaxial features158, contact vias (denoted as Via0) connecting contact plugs and M1, and backside contact vias (denoted as BVia0) formed under the doped epitaxial features158and connecting the doped epitaxial features158with BM1. The doped epitaxial features158may be source/drain features of transistors formed in a probe pad structure. Since the transistors formed in a probe pad structure do not provide circuit functions and are thus referred to as non-functional transistors. As a comparison, transistors formed as circuit components in the circuit region122of a die are referred to as functional transistors. As used herein, a source/drain feature may refer to a source or a drain of a device. It may also refer to a region that provides a source and/or drain for multiple devices. The combination of contact vias Via0, contact plugs, dope epitaxial features158, and backside contact vias BVia0provides an electrical connection between the frontside interconnect structure and the backside interconnect structure of the probe pad structure156.

Extra to the frontside probe pads132, the backside probe pads132′ provide backside probing capability of a testline structure to also conduct WAT, PCM, and/or FA tests from backside of the semiconductor wafer. During the testing process, the probe pads are electrically coupled to an external terminal through probe needles for testing.FIG.3illustrates four probe needles160probing the frontside probe pads132and the backside probe pads132′ simultaneously. The probe needles160may be a part of a probe card that includes multiple probe needles which, for example, may be connected to testing equipment. Alternatively, a frontside probing process and a backside probing process may be performed individually and separately, such as performing a frontside testing through the frontside probe pads132followed by performing a backside testing through the backside probe pads132, or vice versa. Further, the middle portion of the probe pad structure156can be considered as another DUT134′ providing a test structure of measuring interconnect resistance between frontside power rails and backside power rails. By probing the frontside probe pad132and the backside probe pad132′ of the same probe pad structure156with two probe needles160simultaneously, the interconnect resistance providing by the combination of contact vias Via0, contact plugs, dope epitaxial features158, and backside contact vias of BVia0can be measured.

The backside probe pads132′ also allows extra housing to accommodate more DUTs on a shrunk testline area, such as housing more DUTs on the backside of the structure.FIG.3Billustrates such an example. The exemplary testline130inFIG.3Bis similar to its counterpart inFIG.3A. One difference is that the DUT134is a bulky resistor formed in the backside first level metal layer (BM1) in a test pattern area between two probe pad structures156. The bulky resistor may be made of copper in a rectangular and serpentine configuration, although other suitable metal or non-metal conductive materials, such as aluminum (Al), silver (Ag), tungsten (W), and polysilicon of various conductivities can also be used to form resistors of various shapes.

FIGS.4A and4Billustrate cross-sectional views of the semiconductor wafer100along a cutline A-A as shown inFIG.1in some embodiments. Referring toFIG.4A, the semiconductor wafer100may include a semiconductor substrate150, a frontside insulating layer152formed atop the semiconductor substrate150, and a backside insulating layer154formed under the semiconductor substrate150. The semiconductor wafer100may include dies120(including circuit region122and seal rings124), and testlines130. The seal rings124may encircle the circuit region122. The testlines130may be disposed between the seal rings124.

The circuit region122includes a variety of electrical devices, such as passive components or active components. The electrical devices are formed in and/or on the semiconductor substrate150and are electrically connected by interconnect structures, which are stacked and disposed through the frontside insulating layer152, to each other or to another circuitry. In some embodiments, the interconnect structures include contact plugs, conductive lines, and vias. The interconnect structures include at least one of aluminum, copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, metal silicide, combinations thereof or other suitable materials. The illustrated embodiment depicts an interconnect structure in the circuit region122, which couples a source/drain feature158to a post passivation interconnect (PPI) structure170formed above a contact pad in the top metal layer (Mx). The interconnect structure also provides backside power rails formed in BM1and BM2metal layers in coupling with the source/drain feature158. The illustrated embodiment also depicts another interconnect structure in the circuit region122, which couples a gate stack172of a functional transistor to a post passivation interconnect (PPI) structure170formed above a contact pad in Mx metal layer.

The seal rings124are configured to protect the circuit region122from moisture degradation, ionic contamination and damage during dicing and packaging processes. The seal rings124are formed simultaneously with the construction of the interconnect structures in the circuit region122. The seal rings124include a stacking via structure formed in the frontside insulating layer152and one or more source/drain features158coupled to the stacking via structure through contact vias. The circuit region122and the seal rings124may be covered under a passivation layer174. In some embodiments, the seal rings124also include backside contacts, metal lines and vias formed in BM1and BM2metal layers in coupling with the source/drain features158, such as shown inFIG.4B.

The illustrated embodiments inFIGS.4A and4Balso depict a first testline structure130aand a second testline structure130bas exemplary testline structures130. The first testline structure130ais substantially similar to the testline structure130depicted above with reference toFIG.3and the detail description is omitted for the sake of conciseness. The second testline structure130bis similar to the first testline structure130a. One difference is that the second testline structure130bdoes not include higher metal layers (e.g., M5and above). In the illustrated embodiment, the second testline structure130bis formed of M2and metal layers thereunder. The second testline structure130bis for the purpose of inter-metal WAT. The inter-metal WAT may be performed after the metal layer M1or M2(the former layers among the metal layers in the interconnect structure) is formed. After passing the inter-metal WAT, further fabrication processes may be performed on the semiconductor wafer100, including finishing higher metal layers in the circuit region122, the seal ring124, and the first testline structure130a. The testline structures130aand130bmay be positioned in the same scribe line region, or in two perpendicular scribe line regions adjacent a die, respectively.

FIG.5is a flow chart of a method200for fabricating a testline structure, particularly a probe pad structure in a testline structure, according to various embodiments of the present disclosure. Additional processing is contemplated by the present disclosure. Additional operations can be provided before, during, and after method200, and some of the operations described can be moved, replaced, or eliminated for additional embodiments of method200.

Method200is described below in conjunction withFIGS.6A through16Cthat illustrate various cross-sectional views of a testline structure (or structure)300at various steps of fabrication according to the method200, in accordance with some embodiments.FIGS.6A through16Chave been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in the structure300, and some of the features described below can be replaced, modified, or eliminated in other embodiments of the structure300. In some embodiments, the structure300is substantially similar to the testline structure130depicted above with reference toFIGS.1-4.

Further, the details of the structure300and fabrication methods thereof are described below in conjunction with an exemplary process of making a GAA device, according to some embodiments. A GAA device refers to a device having vertically-stacked horizontally-oriented multi-channel transistors, such as nanowire transistors and nanosheet transistors. GAA devices are promising candidates to take CMOS to the next stage of the roadmap due to their better gate control ability, lower leakage current, and fully FinFET device layout compatibility. For the purposes of simplicity, the present disclosure uses GAA devices as an example. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures (such as FinFET devices) for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein.

At operation202, the method200(FIG.5) provides a structure300having a substrate302and transistors (e.g., non-functional transistors and functional transistors) built on a frontside of the substrate302.FIG.6Aillustrates a cross-sectional view of the structure300along a lengthwise direction of the channel layers of the transistors.FIG.6Billustrates a cross-sectional view of the structure300along a B-B cutline inFIG.6A, which is a cut into the sour/drain regions of the transistors.FIG.6Cillustrates a cross-sectional view of the structure300along a C-C cutline inFIG.6a, which is a cut into gate regions of the transistors. The B-B cutlines and C-C cutlines inFIGS.7A through16Care similarly configured.

Still referring toFIGS.6A-6C, the structure300includes the substrate302at its backside and various elements built on the front surface of the substrate302. These elements include an isolation structure304over the substrate302, semiconductor fins (or fins)306extending from the substrate302and adjacent to the isolation structure304, epitaxial source/drain (S/D) features (or S/D features)308over the fins306, one or more semiconductor channel layers (or channel layers)310suspended over the fins306and connecting two S/D features308, and gate stacks312between two S/D features308and wrapping around each of the channel layers310. The structure300further includes inner spacers314between the S/D features308and the gate stacks312, (outer) gate spacers316over sidewalls of the gate stacks312and over the topmost channel layer310, a first inter-layer dielectric (ILD) layer318adjacent to the gate spacers316and over the S/D features308and the gate stacks212. The structure300may further include a contact etch stop layer (CESL) (not shown) under the first ILD layer318. Over the S/D features308, the structure300further includes S/D contacts320disposed over the S/D features308, a second ILD layer322disposed over the first ILD layer318and the S/D contacts320, and contact vias324disposed over the S/D contacts320. The structure300further includes an interconnect structure330over the second ILD layer322. The interconnect structure330includes a plurality of insulating layers, which may be inter-metal dielectric (IMD) layers. Each of the insulating layers includes conductive features, such as metal pieces (metal pads) and vias formed therein. In the illustrated embodiment, the interconnect structure330includes a metal pad332formed in the first level metal layer (M1) and over the contact vias324, an array of vias334formed in the first level via layer (Via1) and over the metal pad332, and a metal pad336formed in the second level metal layer (M2) and over the vias334. The metal pads may have a square shape, rectangular shape, circular shape, oval shape, or other suitable shapes from a top view. Area of each metal pad may range from about 100 um2to about 10,000 um2. The various elements of the structure300are further described below.

In some embodiments, the fins306may include silicon, silicon germanium, germanium, or other suitable semiconductor, and may be doped n-type or p-type dopants. The fins306may be patterned by any suitable method. For example, the fins306may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used as a masking element for patterning the fins306. For example, the masking element may be used for etching recesses into semiconductor layers over or in the substrate302, leaving the fins306on the substrate302. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBr3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. For example, a wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and/or acetic acid (CH3COOH); or other suitable wet etchant. Numerous other embodiments of methods to form the fins306may be suitable.

The isolation structure304may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material (for example, including silicon, oxygen, nitrogen, carbon, or other suitable isolation constituent), or combinations thereof. The isolation structure304can include different structures, such as shallow trench isolation (STI) features and/or deep trench isolation (DTI) features. In an embodiment, the isolation structure304can be formed by filling the trenches between fins306with insulator material (for example, by using a CVD process or a spin-on glass process), performing a chemical mechanical polishing (CMP) process to remove excessive insulator material and/or planarize a top surface of the insulator material layer, and etching back the insulator material layer to form the isolation structure304. In some embodiments, the isolation structure304include multiple dielectric layers, such as a silicon nitride layer disposed over a thermal oxide liner layer.

The S/D features308include epitaxially grown semiconductor materials such as epitaxially grown silicon, germanium, or silicon germanium. The S/D features308can be formed by any epitaxy processes including chemical vapor deposition (CVD) techniques (for example, vapor phase epitaxy and/or Ultra-High Vacuum CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S/D features308may be doped with n-type dopants and/or p-type dopants. In some embodiments, for n-type transistors, the S/D features308include silicon and can be doped with carbon, phosphorous, arsenic, other n-type dopant, or combinations thereof (for example, forming Si:C epitaxial S/D features, Si:P epitaxial S/D features, or Si:C:P epitaxial S/D features). In some embodiments, for p-type transistors, the S/D features308include silicon germanium or germanium, and can be doped with boron, other p-type dopant, or combinations thereof (for example, forming Si:Ge:B epitaxial S/D features). The S/D features308may include multiple epitaxial semiconductor layers having different levels of dopant density. In some embodiments, annealing processes (e.g., rapid thermal annealing (RTA) and/or laser annealing) are performed to activate dopants in the S/D features308.

In some embodiments, the channel layers310include a semiconductor material suitable for transistor channels, such as silicon, silicon germanium, or other semiconductor material(s). The channel layers310may be in the shape of rods, bars, sheets, or other shapes in various embodiments. In an embodiment, the channel layers310are initially part of a stack of semiconductor layers that include the channel layers310and other sacrificial semiconductor layers alternately stacked layer-by-layer. The sacrificial semiconductor layers and the channel layers310include different material compositions (such as different semiconductor materials, different constituent atomic percentages, and/or different constituent weight percentages) to achieve etching selectivity. During a gate replacement process to form the gate stacks312, the sacrificial semiconductor layers are selectively removed, leaving the channel layers310suspended over the fins306.

In some embodiments, the inner spacers314include a dielectric material that includes silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride). In some embodiments, the inner spacers314include a low-k dielectric material, such as those described herein. The inner spacers314may be formed by deposition and etching processes. For example, after S/D trenches are etched and before the S/D features308are epitaxially grown from the S/D trenches, an etch process may be used to recess the sacrificial semiconductor layers between the adjacent channel layers310to form gaps vertically between the adjacent channel layers310. Then, one or more dielectric materials are deposited (using CVD or ALD for example) to fill the gaps. Another etching process is performed to remove the dielectric materials outside the gaps, thereby forming the inner spacers314.

In some embodiments, the gate stacks312include a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include a high-k dielectric material such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3(BTO), (Ba,Sr)TiO3(BST), Si3N4, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric material, or combinations thereof. High-k dielectric material generally refers to dielectric materials having a high dielectric constant, for example, greater than that of silicon oxide (k≈3.9). The gate dielectric layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable methods. In some embodiments, the gate stacks312further includes an interfacial layer between the gate dielectric layer and the channel layers310. The interfacial layer may include silicon dioxide, silicon oxynitride, or other suitable materials. In some embodiments, the gate electrode layer includes an n-type or a p-type work function layer and a metal fill layer. For example, an n-type work function layer may comprise a metal with sufficiently low effective work function such as titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. For example, a p-type work function layer may comprise a metal with a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. For example, a metal fill layer may include aluminum, tungsten, cobalt, copper, and/or other suitable materials. The gate electrode layer may be formed by CVD, PVD, plating, and/or other suitable processes. Since the gate stacks312includes a high-k dielectric layer and metal layer(s), it is also referred to as a high-k metal gate.

In some embodiments, the gate spacers316include a dielectric material such as a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN)). In embodiments, the gate spacers316may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable material(s). For example, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, can be deposited over a dummy gate stack (which is subsequently replaced by the high-k metal gate312) and subsequently etched (e.g., anisotropically etched) to form the gate spacers316. In some embodiments, the gate spacers316include a multi-layer structure, such as a first dielectric layer that includes silicon nitride and a second dielectric layer that includes silicon oxide. In some embodiments, more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers, are formed adjacent to the gate stacks312. In embodiments, the gate spacers316may have a thickness of about 1 nm to about 40 nm, for example.

In some embodiments, the S/D contacts320may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and/or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the S/D contacts320. In some embodiments, a silicide feature (not shown) may be formed between the S/D contacts320and the S/D features308to reduce contact resistance. The silicide feature, if presented, may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

In some embodiments, the second ILD layer322is a flowable film formed by FCVD. Although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 4.5 (e.g., between about 2.5 and about 4.5) may be utilized. The second ILD layer322may include different material composition from the first ILD layer318. For example, a dielectric constant of the second ILD layer322may be lower than the first ILD layer318. In some embodiments, the second ILD layer322is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like. In some embodiments, the second ILD layer322may comprise silicon oxide (SiO), hafnium silicide (HfSi), silicon oxycarbide (SiOC), aluminum oxide (AlO), zirconium silicide (ZrSi), aluminum oxynitride (AlON), zirconium oxide (ZrO), hafnium oxide (HfO), titanium oxide (TiO), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO), tantalum oxide (TaO), lanthanum oxide (LaO), yttrium oxide (YO), tantalum carbonitride (TaCN), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon (Si), zirconium nitride (ZrN), silicon carbonitride (SiCN), combinations or multiple layers thereof, or the like.

In an embodiment, the S/D contact vias324may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and/or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the S/D contact vias324.

In some embodiments, the insulating layers in the interconnect structure330may be formed from a low-k dielectric material having a k-value between about 2.5 and about 4.5. The insulating layers may be formed from an extra-low-k (ELK) dielectric material having a k-value of less than about 2.5. In some embodiments, the insulating layers may be formed from an oxygen-containing and/or carbon containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), the like, or a combination thereof. In some embodiments, some or all of insulating layers are formed of dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like. In some embodiments, etch stop layers (not shown), which may be formed of silicon carbide, silicon nitride, or the like, are formed between adjacent insulating layers. In some embodiments, the insulating layers are formed from a porous material such as SiOCN, SiCN, SiOC, SiOCH, or the like, and may be formed by spin-on coating or a deposition process such as plasma enhanced chemical vapor deposition (PECVD), CVD, PVD, or the like. In some embodiments, the interconnect structure330may include one or more other types of layers, such as diffusion barrier layers (not shown).

In some embodiments, the metal pads and vias in the interconnect structure330may be formed using a single and/or a dual damascene process, a via-first process, or a metal-first process. In an embodiment, an insulating layer is formed, and openings (not shown) are formed therein using acceptable photolithography and etching techniques. Diffusion barrier layers (not shown) may be formed in the openings and may include a material such as TaN, Ta, TiN, Ti, CoW, or the like, and may be formed in the openings using a deposition process such as CVD, Atomic Layer Deposition (ALD), or the like. A conductive material may be formed in the openings from copper, aluminum, nickel, tungsten, cobalt, silver, combinations thereof, or the like, and may be formed over the diffusion barrier layers in the openings using an electro-chemical plating process, CVD, ALD, PVD, the like, or a combination thereof. After formation of the conductive material, excess conductive material may be removed using, for example, a planarization process such as CMP, thereby leaving conductive features in the openings of the respective insulating layer. The process may then be repeated to form additional insulating layers and conductive features therein. The stacked metal pads in the interconnect structure330are connected to the S/D features308through the contact vias324and the S/D contacts320. As a comparison, not like other gate stacks in a circuit region or gate stacks in a DUT, the gate stacks312in a probe pad structure portion of the structure300are floating without gate contacts bringing electrical connections to any interconnect structure. Therefore, the transistors in the probe pad structure portion of the structure300are non-functional transistors.

At operation204, the method200(FIG.5) may optionally perform an inter-metal wafer acceptance test (WAT) with probe needle(s)340, such as shown inFIGS.7A-7C. The inter-metal WAT is performed before the dies are completed to early determine the acceptance rate of the semiconductor wafer. After passing the inter-metal WAT, further fabrication processes may be performed on the semiconductor wafer. On the contrary, if the inter-metal WAT is not passed, the semiconductor wafer may be considered as a failure wafer and further fabrication process is ceased to avoid unnecessary manufacturing cost. In some embodiments, the inter-metal WAT may be performed after the metal layer M1and/or M2is formed and utilize structures formed in M1and/or M2(e.g., DUT134inFIG.3) as DUTs or other features formed in underneath semiconductor layer (e.g., functional transistors in test pattern areas) as DUTs. Accordingly, the inter-metal WAT may facilitate to inspect the failure wafer in the middle stage of the fabrication process. Probe needle(s)340may land on the topmost metal pad of structure300to stimulate DUTs underneath. The probe needle(s)340may be a part of a probe card that includes multiple probe needles which, for example, may be connected to a testing equipment.

If inter-metal WAT is performed and passed, the method200(FIG.5) proceeds to operation206. Alternatively, the method200may skip operation204and proceed from operation202to operation206. At operation206, the method200further forms metal pieces (metal pads) in higher metal layers and vias therebetween in the interconnect structure330, which are positioned above the metal pads332and336in the lower metal layers, such as shown inFIGS.8A-8C. In some embodiments, there are totally about four (Mx=M4) to about eleven (Mx=M11) metal layers in the interconnect structure330. The metal pads and vias formed at operation206may be substantially similar to the metal pads332,336and via334discussed above. In some embodiments, the topmost insulating layer and the topmost metal pad338formed therein may be formed having a thickness greater than a thickness of the other insulating layers of the interconnect structure330. This may be for enhancing mechanical strength of the topmost metal pad338, as the topmost metal pad338is functioned as a frontside probe pad in further WAT. In some embodiments, metallic materials of the frontside probe pad and the metal pieces in underneath metal layers (M1, M2, . . . Mx−1) may be different. For example, the frontside probe pad may include AlCu or NiPdAu—Cu, and the metal pieces in underneath metal layers may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other suitable metallic material. In some embodiments, one or more of the frontside probe pads are dummy probe pads in a testline structure that are electrically isolated from any DUT. Dummy probe pads may be formed to balance metal density in a testline structure. Dummy probe pads may also be electrically isolated from the S/D features308underneath (e.g., without the array of contact vias324).

At operation208, the method200(FIG.5) attaches the frontside of the structure300to a carrier352, such as shown inFIGS.9A-9C. The carrier352may be a silicon wafer in some embodiments. The operation208may use any suitable attaching processes, such as direct bonding, hybrid bonding, using adhesive, or other bonding methods. In some embodiments, the frontside of the structure300is attached to the carrier352through an adhesive layer350. In some embodiments, the adhesive layer350comprises a die attach film (DAF) such as an epoxy resin, a phenol resin, acrylic rubber, silica filler, or a combination thereof, and is applied using a lamination technique. The operation208may further include alignment, annealing, and/or other processes.

At operation210, the method200(FIG.5) flips the structure300, such as shown inFIGS.10A-10C. This makes the structure300accessible from the backside of the structure300for further processing. InFIGS.10A-15C, the “z” direction points from the backside of the structure300to the frontside of the structure300, while the “−z” direction points from the frontside of the structure300to the backside of the structure300. The method200at the operation210also thins down the substrate302from the backside of the structure300. In the depicted embodiment, the thinned substrate302remains covering the isolation structure304. Alternatively, at the conclusion of the operation210, the fins306and the isolation structure304may be exposed from the backside of the structure300. The thinning process may include a mechanical grinding process and/or a chemical thinning process. A substantial amount of substrate material may be first removed from the substrate302during a mechanical grinding process. Afterwards, a chemical thinning process may apply an etching chemical to the backside of the substrate302to further thin down the substrate302.

At operation212, the method200(FIG.5) deposits a dielectric layer354over the thinned substrate302on the backside of the structure300, such as shown inFIGS.11A-11C. If the isolation structure304is exposed at the conclusion of the operation210, the dielectric layer354is also in contact with the isolation structure304. The dielectric layer354is also referred to as a backside dielectric layer354. The backside dielectric layer354may be formed from a low-k dielectric material having a k-value lower than about 4.5 (e.g., between about 2.5 and about 4.5). Alternatively, the insulating layers may be formed from an extra-low-k (ELK) dielectric material having a k-value of less than 2.5. In some embodiments, the backside dielectric layer354may be formed from an oxygen-containing and/or carbon containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), the like, or a combination thereof. In some embodiments, the backside dielectric layer354may include one or more of La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable material(s), and may be formed by PE-CVD, F-CVD or other suitable methods. At the conclusions of the operation212, the backside dielectric layer354may be planarized by a planarization process, such as a chemical mechanical polishing (CMP) process.

At operation214, the method200(FIG.5) forms an etch mask356over the backside of the structure300, such as shown inFIGS.12A-12C. The etch mask356provides openings358over the backside of the S/D features308that are to be connected to backside contact vias and backside metal pads. In the illustrated embodiment, the openings358are provided over the backside of the S/D features308while the backside of the gate stacks312are covered by the etch mask356.

In various embodiments, the openings358may be provided over the backside of drain features only, source features only, or both source and drain features. In some embodiments, the openings358are formed over each of the S/D features308in a probe pad structure, such that the amount of to-be-formed backside contact vias equals the amount of frontside contact vias324. Alternatively, such as in the depicted embodiment, the openings358are formed on backside of not all but every other S/D features308along the X-direction. As the to-be-formed backside contact vias have larger height and larger aspect ratio than the frontside contact vias324, an increased pitch allows the to-be-formed backside via hole to be opened wider than the frontside contact vias324, which facilitates the metal deposition in forming backside contact vias without causing voids.

The etch mask356includes a material that is different than a material of the backside dielectric layer354to achieve etching selectivity during backside via hole etching. For example, the etch mask356includes a resist material (and thus may be referred to as a patterned resist layer and/or a patterned photoresist layer). In some embodiments, the etch mask356has a multi-layer structure, such as a resist layer disposed over an anti-reflective coating (ARC) layer and/or a hard mask layer comprising silicon nitride or silicon oxide. The present disclosure contemplates other materials for the etch mask356, so long as etching selectivity is achieved during the etching of the backside dielectric layer354. In some embodiments, operation214uses a lithography process that includes forming a resist layer over the backside of the structure300(e.g., by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a developing process. During the exposure process, the resist layer is exposed to radiation energy (e.g., UV light, DUV light, or EUV light), where the mask blocks, transmits, and/or reflects radiation to the resist layer depending on a mask pattern of the mask and/or mask type (e.g., binary mask, phase shift mask, or EUV mask), such that an image is projected onto the resist layer that corresponds with the mask pattern. Since the resist layer is sensitive to radiation energy, exposed portions of the resist layer chemically change, and exposed (or non-exposed) portions of the resist layer are dissolved during the developing process depending on characteristics of the resist layer and characteristics of a developing solution used in the developing process. After development, the patterned resist layer (e.g., the etch mask356) includes a resist pattern that corresponds with the mask. Alternatively, the exposure process can be implemented or replaced by other methods, such as maskless lithography, e-beam writing, ion-beam writing, or combinations thereof.

At operation216, the method200(FIG.5) etches the dielectric layer354through the etch mask356to form backside via holes360. The etch mask356is subsequently removed, for example, by a resist stripping process or other suitable process. The resultant structure is shown inFIGS.13A-13Caccording to an embodiment. The backside via holes368expose the S/D features308. In the illustrated embodiment, the etching process also etches the exposed S/D feature260to recess it to a level that is below the backside surface of an adjacent S/D feature308that remains covered by the backside dielectric layer354. The recessing is for preparing the exposed S/D features308for subsequent silicide formation. In some embodiments, the operation216may apply more than one etching processes. For example, it may apply a first etching process to selectively remove the backside dielectric layer354, and then apply a second etching process to selectively recess the S/D features308to the desired level, where the first and the second etching processes use different etching parameters such as using different etchants. In an embodiment, the first etching process include a dry (plasma) etching process that is tuned to selectively etch the backside dielectric layer354. In alternative embodiments, first etching process may use other types of etching (such as wet etching or reactive ion etching) as long as the etch selectivity between the layers is achieved as discussed above. The second etching process can be dry etching, wet etching, reactive ion etching, or other suitable etching methods, to selectively recess the exposed ones of the S/D features308to the desired level.

At operation218, the method200(FIG.5) forms backside contact vias362in the backside via holes360. The resultant structure is shown inFIGS.14A-14C. In an embodiment, the operation218first forms a silicide feature (not shown) in the backside via holes360by depositing one or more metals into the backside via holes360, performing an annealing process to the structure300to cause reaction between the one or more metals and the exposed S/D features308to produce the silicide feature, and removing un-reacted portions of the one or more metals, leaving the silicide feature on the backside of the exposed S/D features308. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals) and may be deposited using CVD, PVD, ALD, or other suitable methods. The silicide feature may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), a combination thereof, or other suitable compounds. In an embodiment, the operation218then deposits the backside vias362over the silicide feature. The backside vias362may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. At the conclusion of the operation218, the method200performs a CMP process to remove excessive metallic materials from the backside of the structure300.

As discussed above, a pitch of the backside contact vias362along the X-direction (denoted as P) may equal to that of the frontside contact vias324; alternatively, P may be smaller (e.g., about half as depicted inFIG.14A) than that of the frontside contact vias324. In some embodiments, P may be smaller than about 50 nm, and a lateral distance between a backside contact via362and adjacent gate stack312may be less than about 20 nm. As a comparison, a pitch of the backside contact vias362along the Y-direction (denoted as P′) may equal to that of the front side contact visas324. Further, as discussed above, a height and an aspect ratio (height/width) of the backside contact vias362may be larger than those of the frontside contact vias324. In some embodiments, a width of the backside contact vias362is also larger than that of the frontside contact vias324due to a larger pitch, which facilitates metal deposition in high-aspect-ratio holes. In some embodiments, a height of the backside contact vias362is larger than about 35 nm.

At operation220, the method200(FIG.1B) forms a backside interconnect structure370on the backside of the structure300. The resultant structure is shown inFIGS.15A-15Caccording to an embodiment. The backside contact vias362is electrically connected to the metal pad formed in the backside first level metal layer (BM1) of the backside interconnect structure370. In the depicted embodiment, the backside interconnect structure370includes metal pads formed in the backside second level metal layer (BM2) and BM1and backside vias formed therebetween (BVia1). Alternatively, the backside interconnect structure370may have more or less than two backside metal layers. In some embodiments, the frontside interconnect structure330has more metal layers and a larger height than the backside interconnect structure370. In some embodiments, the frontside interconnect structure330has the same number of metal layers and similar height as the backside interconnect structure370.

In some embodiments, the backside interconnect structure370includes insulating layers formed from a low-k dielectric material having a k-value lower than about 4.5 (e.g., between about 2.5 and about 4.5). The insulating layers may be formed from an extra-low-k (ELK) dielectric material having a k-value of less than 2.5. In some embodiments, the insulating layers may be formed from an oxygen-containing and/or carbon containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), the like, or a combination thereof. In some embodiments, some or all of insulating layers are formed of dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like. In some embodiments, the insulating layers are formed from a porous material such as SiOCN, SiCN, SiOC, SiOCH, or the like, and may be formed by spin-on coating or a deposition process such as plasma enhanced chemical vapor deposition (PECVD), CVD, PVD, or the like.

In some embodiments, the metal pads and vias in the backside interconnect structure370may be formed using a single and/or a dual damascene process, a via-first process, or a metal-first process. In an embodiment, an insulating layer is formed, and openings (not shown) are formed therein using acceptable photolithography and etching techniques. Diffusion barrier layers (not shown) may be formed in the openings and may include a material such as TaN, Ta, TiN, Ti, CoW, or the like, and may be formed in the openings using a deposition process such as CVD, Atomic Layer Deposition (ALD), or the like. A conductive material may be formed in the openings from copper, aluminum, nickel, tungsten, cobalt, silver, combinations thereof, or the like, and may be formed over the diffusion barrier layers in the openings using an electro-chemical plating process, CVD, ALD, PVD, the like, or a combination thereof. After formation of the conductive material, excess conductive material may be removed using, for example, a planarization process such as CMP, thereby leaving conductive features in the openings of the respective insulating layer. The process may then be repeated to form additional insulating layers and conductive features therein. The stacked metal pads in the backside interconnect structure370are connected to the S/D features308through the backside contact vias362.

The metal pads in the backside interconnect structure370may have the same shape as the counterparts in the frontside interconnect structure330, such as a square shape, rectangular shape, circular shape, oval shape, or other suitable shapes from a top view. In some embodiments, the bottommost insulating layer and the bottommost metal pad372formed therein may be formed having a thickness greater than a thickness of the other insulating layers of the backside interconnect structure370. This may be for enhancing mechanical strength of the bottommost metal pad372, as the bottommost metal pad372is functioned as a backside probe pad in further WAT. In some embodiments, metallic materials of the backsideside probe pad and the metal pieces in above metal layers (e.g., BM1) may be different. For example, the backside probe pad may include AlCu or NiPdAu—Cu, and the metal pieces in above metal layers may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other suitable metallic material. In some embodiments, one or more of the backside probe pads are dummy probe pads in a testline structure that are electrically isolated from any DUT. Dummy probe pads may be formed to balance metal density in a testline structure. Dummy probe pads may also be electrically isolated from the S/D features308above (e.g., without the array of backside contact vias362).

At operation222, the method200(FIG.5) performs further fabrication processes to the structure300. For example, it may flip the structure300and remove the carrier352, such as shown inFIGS.16A-16C. The method200at the operation222may also perform other back-end-of-line (BEOL) processes including forming passivation layers in the circuit region, perform WAT and/or FA tests from both the frontside and the backside of the structure300, and singulate and package the dies. As discussed above, depending on scribing process, probe pad structures may remain in the dies.

In view of the above, the testline structure in the semiconductor device includes frontside probe pads and backside probe pads, which meets test needs for advanced semiconductor devices having backside power rails. The backside probe pads also provide capability of housing more DUTs on an ever-shrunk testline area, such as housing more DUTs on the backside of the semiconductor devices. Embodiments of the present disclosure can be readily integrated into existing semiconductor manufacturing processes.

In one example aspect, the present disclosure is directed to a testline structure of a semiconductor device. The testline structure includes a substrate layer, a frontside insulating layer atop the substrate layer, a backside insulating layer under the substrate layer, and a probe pad structure vertically extending through the frontside insulating layer, the substrate layer, and the backside insulating layer, the probe pad structure including a frontside probe pad in the frontside insulating layer and a backside probe pad in the backside insulating layer. In some embodiments, the semiconductor device is a wafer, and the testline structure is located in a scribe line region of the wafer. In some embodiments, the semiconductor device is a packaged integrated circuit die, and the testline structure is located aside of a circuit region of the packaged integrated circuit die. In some embodiments, the testline structure further includes a device under test (DUT) in electrical connection with the probe pad structure. In some embodiments, the DUT is formed in the frontside insulating layer. In some embodiments, the DUT is formed in the backside insulating layer. In some embodiments, the probe pad structure also includes a plurality of doped epitaxial features in the substrate layer, frontside contact vias coupling the doped epitaxial features to the frontside probe pad, and backside contact vias coupling the doped epitaxial features to the backside probe pad. In some embodiments, a pitch of the backside contact vias is larger than a pitch of the frontside contact vias. In some embodiments, the probe pad structure also includes gate stacks between adjacent ones of the doped epitaxial features, the gate stacks being electrically floating. In some embodiments, the frontside probe pad and the backside probe pad include metallic compositions different from other metal pieces of the probe pad structure formed in the frontside insulating layer and the backside insulating layer.

In another example aspect, the present disclosure is directed to a semiconductor device. The semiconductor device a circuit region having a frontside power rail in a frontside of the semiconductor device and a backside power rail in a backside of the semiconductor device, a seal ring region surrounding the circuit region, and a testline region aside the seal ring region. The testline region includes a frontside metal pad in the frontside of the semiconductor device, a plurality of epitaxial features under the frontside metal pad, and a plurality of contact vias above the epitaxial features and electrically coupling the epitaxial features to the frontside metal pad. In some embodiments, the circuit region includes functional transistors, and the testline region includes non-functional transistors, and the epitaxial features are source/drain features of the non-functional transistors. In some embodiments, the non-functional transistors include gate stacks between adjacent ones of the epitaxial features, and the gate stacks are electrically floating. In some embodiments, the testline region also includes a backside metal pad formed in the backside of the semiconductor device, and a plurality of backside vias in contact with bottom surfaces of the epitaxial features and electrically coupling the epitaxial features to the backside metal pad. In some embodiments, the backside metal pad and the frontside metal pad have a same shape. In some embodiments, a height of the backside vias is larger than a height of the contact vias.

In yet another example aspect, the present disclosure is directed to a method. The method includes providing a structure having a frontside and a backside, the structure including a substrate, semiconductor channel layers over the substrate, source/drain features abutting the semiconductor channel layers, gate structures wrapping around the semiconductor channel layers, the substrate being at the backside of the structure and the gate structures are at the frontside of the structure, forming source/drain contacts on the source/drain features, forming contact vias on the source/drain contacts, forming a first interconnect structure on the contact vias, the first interconnect structure including a first probe pad at the frontside of the structure, forming backside vias under the source/drain features, and forming a second interconnect structure under the backside vias, the second interconnect structure including a second probe pad at the backside of the structure. In some embodiments, the method further includes after the forming of the first interconnect structure, flipping the structure, and prior to the forming of the backside vias, thinning the substrate from the backside of the structure. In some embodiments, the method further includes prior to the forming of the backside vias, performing an inter-metal wafer acceptance test (WAT) through the first probe pad. In some embodiments, the first interconnect structure also includes a first stacking via structure under the first probe pad, and the second interconnect structure also includes a second stacking via structure above the second probe pad.