Clock gating using a cascaded clock gating control signal

A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.

BACKGROUND

Clock gating involves removing a clock signal provided to portions of a circuit in order to save power. To perform clock gating, the clock signal and a clock gating control signal are provided to logic, with the logic providing output as a function of the clock signal and the clock gating control signal. For a multiphase clock, multiple clock signals each provide output corresponding to a different phase of a clock interval. In order to perform clock gating with a multiphase clock, a clock gating control signal is used to control the output of each clock signal.

DETAILED DESCRIPTION

Clock gating involves removing a clock signal provided to portions of a circuit in order to save power. For example, removing the clock signal provided to flip-flops or other circuitry prevents a state change in the circuits, which consume power. To perform clock gating, the clock signal and a clock gating control signal is provided to some logic, with the logic providing output as a function of the clock signal and the clock gating control signal. As an example, where the clock gating control signal is in a high or active state, the clock signal is output, while some other output (e.g., high or low) will be output while the clock gating control signal is low independent of the clock signal.

For a multiphase clock, multiple clock signals each provide output corresponding to a different phase of a clock interval. As an example, a two-phase clock will include two clock signals, with one clock signal in quadrature (e.g., shifted ninety degrees) relative to the other clock signal. In order to perform clock gating with a multiphase clock, a clock gating control signal is used to control the output of each clock signal. For example, a clock gating control signal routed in parallel to separate logic for each clock signal will allow for clock gating for each control signal. However, such an approach introduces difficulties in ensuring that the clock gating control signal is timed properly relative to each clock signal, thereby introducing the possibility of mistimed or glitched clock signals.

To that end, the present specification sets forth various implementations for clock gating using a cascaded clock gating control signal. In some implementations, a clock circuit for clock gating using a cascaded clock gating control signal includes: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on an output from the first B-latch and the first clock signal, a first gated clock signal; and a second logic outputting, based on an output from the second B-latch and the second clock signal, a second gated clock signal.

In some implementations, the first logic includes a first AND gate accepting, as input, the first clock signal and the output from the first B-latch and outputting the first gated clock signal; and the second logic includes a second AND gate accepting, as input, the second clock signal and the output from the second B-latch and outputting the second gated clock signal. In some implementations, the first clock signal includes a data (DQ) signal and the second clock signal includes a data strobe (DQS) signal. In some implementations, the second clock signal is in quadrature with the first clock signal. In some implementations, the clock circuit further includes: at least one other B-latch accepting, as input, an output from a sequentially preceding B-latch and enabled by a corresponding clock signal of at least one other clock signal; and at least one other logic outputting, based on output from the at least one other B-latch, at least one other gated clock signal. In some implementations, the at least one other logic includes at least one other AND gate each outputting a corresponding gated clock signal of the at least one other gated clock signal and accepting, as input, the corresponding clock signal and an output of a corresponding B-latch of the at least one other B-latch. In some implementations, the first clock signal, the second clock signal, and the at least one other gated clock signal each correspond to a respective phase of a multiphase gated clock.

The present specification also describes various implementations of a method for clock gating using a cascaded clock gating control signal. Such a method includes: providing, as an enable input to each B-latch of a plurality of B-latches, a corresponding clock signal of a plurality of clock signals; providing, as an input to a first B-latch of the plurality of B-latches, a clock gating control signal; providing, as an input to each B-latch of the plurality of B-latches other than the first B-latch, an output of a sequentially preceding B-latch; and outputting, based on an output of each B-latch of the plurality of B-latches and the plurality of clock signals, a plurality of gated clock signals.

In some implementations, outputting the plurality of clock signals includes outputting, by a plurality of AND gates, the plurality of gated clock signals, wherein each AND gate accepts, as input, an output of a corresponding B-latch and the corresponding clock signal provided as the enable input to the corresponding B-latch. In some implementations, the plurality of clock signals include a data (DQ) signal and a data strobe (DQS) signal. In some implementations, the plurality of clock signals include a first signal and a second signal in quadrature with the first signal. In some implementations, the plurality of clock signals includes more than two clock signals. In some implementations, the plurality of gated clock signals corresponds to a respective phase of a multiphase gated clock.

Also described in this specification are various implementations of an apparatus for clock gating using a cascaded clock gating control signal. Such a system includes a clock signal including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; a first logic outputting, based on an output from the first B-latch and the first clock signal, a first gated clock signal; and a second logic outputting, based on an output from the second B-latch and the second clock signal, a second gated clock signal.

In some implementations, wherein the first logic includes a first AND gate accepting, as input, the first clock signal and the output from the first B-latch and outputting the first gated clock signal; and wherein the second logic includes a second AND gate accepting, as input, the second clock signal and the output from the second B-latch and outputting the second gated clock signal. In some implementations, the clock circuit further includes: at least one other B-latch accepting, as input, an output from a sequentially preceding B-latch and enabled by a corresponding clock signal of at least one other clock signal; and at least one other logic outputting, based on output from the at least one other B-latch, at least one other gated clock signal. In some implementations, the at least one other logic includes at least one other AND gate each outputting a corresponding gated clock signal of the at least one other gated clock signal and accepting, as input, the corresponding clock signal and an output of a corresponding B-latch of the at least one other B-latch. In some implementations, the apparatus further includes a serializer/deserializer (SerDes) operatively coupled to the clock circuit. In some implementations, the apparatus further includes a memory module operatively coupled to the clock circuit. In some implementations, the first clock signal includes a data (DQ) signal and the second clock signal includes a data strobe (DQS) signal.

The following disclosure provides many different implementations, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows include implementations in which the first and second features are formed in direct contact, and also include implementations in which additional features be formed between the first and second features, such that the first and second features are not in direct contact. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “back,” “front,” “top,” “bottom,” and the like, are used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Similarly, terms such as “front surface” and “back surface” or “top surface” and “back surface” are used herein to more easily identify various components, and identify that those components are, for example, on opposing sides of another component. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

FIG.1Ais a block diagram of a non-limiting example clock circuit100. The example clock circuit100can be implemented in a variety of computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, and the like. The clock circuit100is a two-phase multiphase clock that accepts a clock signal102aand a clock signal102b. In some implementations, the clock signal102bis in quadrature (e.g., shifted ninety degrees) relative to the clock signal102a. In other words, in some implementations, the clock signal102ais an in-phase signal and the clock signal102bis a quadrature-phase signal. In some implementations, the clock signal102aincludes a data (DQ) signal and the clock signal102bincludes a data strobe (DQS) signal.

The clock circuit100also accepts a clock gating control signal shown as the control signal104. The control signal104is a signal that controls the gated clock output of the clock circuit100. The clock signals102a,bare each provided to corresponding B-latches106a,b. A B-latch106a,bis a type of latch similar to a D-latch in that it accepts an input signal and provides an output signal based on an enable input provided to the B-latch106a,b. Where the enable input is low, the B-latch106a,bis transparent and provides the input signal as the output signal. Where the enable input is high, the B-latch106a,boutputs a latched value (e.g., a high value or a low value).

In this example clock circuit100, the clock signals102a,bserve as the enable inputs for their corresponding B-latch106a,bafter inversion via inverters101a,b. The B-latch106aaccepts, as the input signal, the control signal104(e.g., the clock gating control signal). The B-latch106baccepts, as input, the output from the B-latch106a. Thus, the control signal104effectively cascades through the B-latches106a,bin order to drive clock gating as described below.

In the example clock circuit100, the output of each B-latch106a,bis provided as input to a corresponding AND gate108a,b, with each AND gate108a,bcorresponding to a particular B-latch106a,b. Each AND gate108a,balso accepts, as input, the corresponding clock signal102a,b. Thus, each AND gate108a,baccepts, as input, a corresponding clock signal102a,band a signal based on the control signal104as controlled by the B-latches106a,b. Each AND gate108a,boutputs a corresponding gated clock signal110a,bthat has been gated based on the outputs of the corresponding B-latches106a,b. Thus, as set forth above, the control signal104effectively cascades through the B-latches106a,bin order to gate the clock signals102a,bwithout the need for parallel routing, thereby ensuring proper timing of the control signal104with respect to each clock signal102a,b, preventing glitches. AlthoughFIG.1Ashows the use of AND gates108a,b, it is understood that the use of other combinations of functionally similar or equivalent logic are also contemplated within the scope of the present disclosure. Accordingly, any combination of first logic and second logic that outputs gated clock signals based on the clock signals102a,band the outputs of the B-latches106a,bare also contemplated within the scope of the present disclosure.

FIG.1Bis a block diagram of another non-limiting example clock circuit150. Whereas the clock circuit100shows a two-phase clock circuit100, the clock circuit150shows a multiphase clock circuit150supporting any number of clock phases. Similar to the clock circuit100ofFIG.1A, the clock circuit150accepts a control signal104provided as input to a first B-latch106a. The output of the first B-latch106ais provided as input to a second B-latch106b. The B-latches106a,baccept enable inputs as corresponding clock signals112a,b. The clock signals112a,band the outputs of the B-latches106a,bare each provided to respective AND gates108a,b. The AND gates108a,beach output a respective gated clock signal114a,b.

The clock circuit150ofFIG.1Bdiffers from the clock circuit100ofFIG.1Ain that the clock circuit150ofFIG.1Bsupports n-numbers of clock phases as shown by clock signals112a,b-n. Accordingly, the output of the B-latch106bis cascaded through some number of B-latches, ending with a B-latch106n. The B-latch106naccepts a clock signal112nvia an inverter101nas an enable input and provides output to an AND gate108n. The AND gate108nalso accepts the clock signal112nas input and provides, as output, a gated clock signal114n. Thus, the approaches described herein for cascading a clock gating control signal through B-latches enabled by respective clock signals of different phases are appliable to multiphase clocks of any number of phases.

FIG.2shows a block diagram of an example apparatus200implementing a clock circuit202according to some implementations of the present disclosure. The clock circuit202includes, for example, a clock circuit100ofFIG.1Aor a clock circuit150ofFIG.1B. The clock circuit202accepts, as input, a control signal206such as a control signal104ofFIGS.1A and1B. The clock circuit204also accepts clock signals208. For example, in some implementations, the clock signals208include clock signals102a,bfor a two-phase clock as shown inFIG.1A. As another example, in some implementations, the clock signals208include clock signals112a,b-nof a multiphase clock having n-numbers of phases.

The clock circuit202outputs gated clock signals208. In some implementations, the clock signals208include two-phase gated clock signals110a,bsuch as inFIG.1A. In some implementations, the clock signals208include n-phase gated clock signals114a.b-n. The gated clock signals208drive clocked circuitry210. The clock circuitry210includes any circuitry capable of being driven or timed by a multiphase clock, such as a serializer/deserializer (SerDes), a memory module such as Double Data Rate Random Access Memory (DDR RAM), and other clock-driven circuitry as can be appreciated.

In some implementations, the clock circuits100,150ofFIGS.1A and1Bare implemented in a computer300. In addition to at least one processor302, the computer300ofFIG.3includes random access memory (RAM)304which is connected through a high speed memory bus306and bus adapter308to processor302and to other components of the computer300. Stored in RAM304is an operating system310. The operating system310in the example ofFIG.3is shown in RAM304, but many components of such software typically are stored in non-volatile memory also, such as, for example, on data storage312, such as a disk drive.

The computer300ofFIG.3includes disk drive adapter316coupled through expansion bus318and bus adapter308to processor302and other components of the computer300. Disk drive adapter316connects non-volatile data storage to the computer300in the form of data storage312. Such disk drive adapters include Integrated Drive Electronics (‘IDE’) adapters, Small Computer System Interface (SCSI′) adapters, and others as will occur to those of skill in the art. In some implementations, non-volatile computer memory is implemented as an optical disk drive, electrically erasable programmable read-only memory (so-called ‘EEPROM’ or ‘Flash’ memory), RAM drives, and so on, as will occur to those of skill in the art.

The example computer300ofFIG.3includes one or more input/output (′I/O′) adapters320. I/O adapters implement user-oriented input/output through, for example, software drivers and computer hardware for controlling output to display devices such as computer display screens, as well as user input from user input devices322such as keyboards and mice. The example computer300ofFIG.3includes a video adapter324, which is an example of an I/O adapter specially designed for graphic output to a display device326such as a display screen or computer monitor. Video adapter324is connected to processor302through a high speed video bus328, bus adapter308, and the front side bus330, which is also a high speed bus.

The exemplary computer300ofFIG.3includes a communications adapter332for data communications with other computers and for data communications with a data communications network. Such data communications are carried out serially through RS-232 connections, through external buses such as a Universal Serial Bus (‘USB’), through data communications networks such as IP data communications networks, and/or in other ways as will occur to those of skill in the art. Communications adapters332implement the hardware level of data communications through which one computer sends data communications to another computer, directly or through a data communications network. Such communication adapters332include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.

For further explanation,FIG.4sets forth a flow chart illustrating an example method for clock gating using a cascaded clock gating control signal. The example method ofFIG.4is performed, for example, in a clock circuit400. The clock circuit400includes, for example, a clock circuit100ofFIG.1Aor a clock circuit150ofFIG.1B. The method ofFIG.4includes receiving402, by a B-latch (e.g., of the clock circuit400), a clock signal as an enable input.

A B-latch is a type of latch similar to a D-latch in that it accepts an input signal and provides an output signal based on an enable input provided to the B-latch. Where the enable input is low, the B-latch is transparent and provides the input signal as the output signal. Where the enable input is high, the B-latch outputs a latched value (e.g., a high value or a low value). In the clock circuit400ofFIG.4, there can be any number B-latches. Each of the B-latches receives a corresponding clock signal from a number of different clock signals (e.g., in a multiphase clock driven by multiple clock signals). In some implementations, the plurality of B-latches includes a first B-latch106aand a second B-latch106b. Accordingly, in such an implementation, the plurality of clock signals includes a first clock signal102aand a second clock signal102bof a two-phase clock. As an example, in some implementations, the first clock signal102aincludes an in-phase signal and the second clock signal102bincludes a quadrature-phase signal. In some implementations, the first clock signal102aincludes a data (DQ) signal and the second clock signal102bincludes a data strobe (DQS) signal.

In some implementations, the clock circuit400includes more than two B-latches106a,b-n for an n-phase multiphase clock like that shown inFIG.1B. Accordingly, in such an implementation, the clock signals include clock signals112a,b-nas shown inFIG.1B. The clock signals serve as the enable inputs to the B-latches in that each B-latch will output either a latched value or will be transparent depending on the state of the received clock signal.

The method ofFIG.4also includes receiving404, by a first B-latch106a(e.g., a first B-latch106a), a clock gating control signal. The clock gating control signal includes, for example, a control signal104as shown inFIGS.1A and1B. The clock gating control signal is received by the first B-latch106aas an input signal. The method ofFIG.4also includes receiving406, by each other B-latch (that is, any B-latch other than the ‘first’ B-latch mentioned above), an output of a sequentially preceding B-latch. Each B-latch receives, as an input signal, the output of the sequentially preceding B-latch. For example, the output of the first B-latch106aofFIG.1AorFIG.1Bis provided as input to the second B-latch106bofFIG.1AandFIG.1Band so on for each subsequent B-latch.

The method ofFIG.4also includes outputting408a plurality of gated clock signals (e.g., gated clock signals110a,b, gated clock signals114a,b-n). The gated clock signals are based on the output of each B-latch as the output of the B-latches is based on the clock gating control signal, thereby gating each of the plurality of clock signals. For example, in some implementations, outputting408the plurality of gated clock signals includes outputting, by a plurality of AND gates (e.g., AND gates108a,b, AND gates108a,b-n), the plurality of gated clock signals. In such an implementation, each AND gate accepts, as input, a corresponding clock signal and an output of a corresponding B-latch, thereby allowing the clock gating control signal cascaded through the B-latches to gate the clock signals via the AND gates.

In this example clock circuit100, the clock signals102a,bserve as the enable inputs for their corresponding B-latch106a,b. The B-latch106aaccepts, as the input signal, the control signal104(e.g., the clock gating control signal). The B-latch106baccepts, as input, the output from the B-latch106a. Thus, the control signal104effectively cascades through the B-latches106a,bin order to drive clock gating as described below.

In view of the explanations set forth above, readers will recognize that the benefits of clock gating using a cascaded clock gating control signal include improved performance of a computing system by allowing for glitch-resistant clock gating of multiphase clocks without requiring parallel routing of the clock gating control signal.

It will be understood from the foregoing description that modifications and changes can be made in various implementations of the present disclosure. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.