SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS

A semiconductor integrated circuit includes first and second input terminals, first and second output terminals, a first detection circuit configured to assert a first signal in response to detecting a voltage drop at the first input terminal, a second detection circuit configured to assert a second signal in response to detecting an overvoltage of the first input terminal, a third detection circuit configured to assert a third signal in response to detecting a voltage drop at the second input terminal, a first output circuit configured to monitor the first signal and the second signal, and output a first reset signal from the first output terminal in response to asserting the first signal or the second signal, and a second output circuit configured to monitor the third signal, and output a second reset signal from the second output terminal in response to asserting the third signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims priority to Japanese Patent Application No. 2023-080974, filed on May 16, 2023, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to semiconductor integrated circuits and electronic apparatuses.

BACKGROUND

A known reset semiconductor integrated circuit includes a voltage detection circuit, and outputs a reset signal when a power supply voltage to be monitored becomes lower than a predetermined level, as proposed in Japanese Laid-Open Patent Publication No. 2022-129021, for example.

However, according to the conventional technology, in a case where there are two or more channels of voltages to be monitored, a number of semiconductor integrated circuits that is the same as the number of voltages to be monitored, may be required. Depending on the voltage to be monitored, there are cases where outputting the reset signal is required by detecting a voltage rise, such as an overvoltage or the like, in addition to detecting a voltage drop.

SUMMARY

The present disclosure provides a semiconductor integrated circuit having both a voltage drop detection function for a plurality of channels and a voltage rise detection function for a specific channel, and an electronic apparatus including the semiconductor integrated circuit.

A semiconductor integrated circuit according to an aspect of the present disclosure includes a plurality of terminals including a first input terminal, a second input terminal, a first output terminal, and a second output terminal; a first detection circuit configured to assert a first signal in response to detecting a voltage drop at the first input terminal; a second detection circuit configured to assert a second signal in response to detecting an overvoltage of the first input terminal; a third detection circuit configured to assert a third signal in response to detecting a voltage drop at the second input terminal; a first output circuit configured to monitor the first signal and the second signal, and output a first reset signal from the first output terminal in response to asserting the first signal or the second signal; and a second output circuit configured to monitor the third signal, and output a second reset signal from the second output terminal in response to asserting the third signal.

A semiconductor integrated circuit according to another aspect of the present disclosure includes a plurality of terminals including a first input terminal, a second input terminal, a first output terminal, and a second output terminal; a first detection circuit coupled to the first input terminal; a second detection circuit coupled to the first input terminal; a third detection circuit coupled to the second input terminal; a first output circuit configured to output a first reset signal from the first output terminal when the first detection circuit detects that a voltage of the first input terminal is lower than a first threshold value or when the second detection circuit detects that the voltage of the first input terminal is higher than a second threshold value that is higher than the first threshold value; and a second output circuit configured to output a second reset signal from the second output terminal when the third detection circuit detects that a voltage of the second input terminal is lower than a third threshold value.

DETAILED DESCRIPTION

FIG.1is a diagram illustrating a configuration example of an electronic apparatus including a semiconductor integrated circuit according to a first embodiment. An electronic apparatus201illustrated inFIG.1includes a reset integrated circuit (IC)101. The reset IC101is an example of the semiconductor integrated circuit according to the first embodiment. A reset IC may also be referred to as a voltage detector.

The electronic apparatus201is for a vehicle, for example, and is used in a state installed in the vehicle. Specific examples of the electronic apparatus201include a car navigation apparatus, a drive recorder, an on-vehicle apparatus for an electronic toll collection (ETC) system, a universal serial bus (USB) connector, a camera, a radar, a communication apparatus, and an electronic control unit (ECU). However, the electronic apparatus201is not limited to such apparatuses.

The electronic apparatus201uses an on-vehicle power supply (not illustrated) that is connected to a battery power line63installed in the vehicle, as an operation power supply. The electronic apparatus201operates with a DC power supplied from the on-vehicle power supply (not illustrated) via the battery power line63. The on-vehicle power supply is a 12-volt battery, for example. The battery power line63is a wire harness for a battery power supply, for example.

The electronic apparatus201is activated by an accessory signal (ACC signal) supplied via an accessory (ACC) power line64installed in the vehicle, in a state in which a DC power higher than or equal to a minimum operating voltage of the electronic apparatus201is supplied from the battery power line63. The accessory signal is a seizure signal for turning the activation of the electronic apparatus201on or off. The accessory signal is a binary voltage signal. A high level of the accessory signal indicates that the electronic apparatus201is to be activated, and a low level of the accessory signal indicates that the activation or operation of the electronic apparatus201is to be stopped. The accessory power line64is a wire harness for accessory power supply, for example.

The electronic apparatus201includes a terminal BAT, a first power line (or first power supply line)61, a terminal ACC, a second power line (or second power supply line)62, a regulator60, a third power line (or third power supply line)67, an electronic circuit70, and a reset IC101.

The terminal BAT is a battery terminal connected to a battery power line (or battery power supply line)63of the vehicle. The battery power line63is connected to the first power line61of the electronic apparatus201via the terminal BAT. The DC power supplied from the battery power line63is input to the first power line61of the electronic apparatus201via the terminal BAT. The DC power input from the terminal BAT is supplied to an input terminal of the regulator60and a first input terminal VS1of the reset IC101via the first power line61. The first power line61is a power supply pattern formed on a built-in substrate of the electronic apparatus201, mounted with the reset IC101, for example.

The regulator60is a power supply circuit configured to step down the DC voltage of the first power line61to a constant power supply voltage Vdd. The regulator60steps down a DC voltage of 12 volts to generate the power supply voltage Vdd of 3.3 volts (V), for example. The power supply voltage Vdd generated by the regulator60is supplied to a power terminal VDD of the reset IC101and to a power terminal VDD of the electronic circuit70, via the third power line67. The third power line67is a power supply pattern formed on the built-in substrate of the electronic apparatus201, mounted with the reset IC101, for example.

The terminal ACC is an accessory power terminal connected to the accessory power line64of the vehicle. The accessory power line64is connected to the second power line62of the electronic apparatus201via the terminal ACC. The seizure signal supplied from the accessory power line64is input to the second power line62of the electronic apparatus201via the terminal ACC. The seizure signal input from the terminal ACC is input to a second input terminal VS2of the reset IC101via the second power line62. The second power line62is a power supply pattern formed on the built-in substrate of the electronic apparatus201, mounted with the reset IC101, for example.

The electronic circuit70operates at the power supply voltage Vdd, and is activated by a first reset signal S1and a second reset signal S2supplied from the reset IC101. The electronic apparatus201is activated by the activation of the electronic circuit70. The electronic circuit70controls the operation of the electronic apparatus201. Specific examples of the electronic circuit70include a processor, such as a central processing unit (CPU) or the like, a microcomputer, a system-on-chip (SoC), a large scale integrated (LSI) circuit, or the like.

The electronic apparatus201operates at the power supply voltage Vdd generated based on the DC power supplied from the battery power line63, and the activation of the electronic apparatus201is switched on and off by the seizure signal supplied from the accessory power line64. For this reason, voltage monitoring of a voltage signal (the power supply voltage of the first power line61) supplied from the battery power line63and a voltage signal (the seizure signal transmitted through the second power line62) supplied from the accessory power line64, may be required in the electronic apparatus201. Further, the monitoring the power supply voltage of the first power line61may require detection of an overvoltage in addition to detection of a voltage drop. This is because an overvoltage may occur at the battery power line63and the first power line61due to an erroneous connection or the like of a 24-volt battery for trucks.

In order to meet such requirements, the reset IC101has functions of monitoring the voltages of the first power line61and the second power line62. The reset IC101monitors the voltage of the first power line61, and outputs the first reset signal S1to the electronic circuit70from a first output terminal OUT1based on the monitored result. The reset IC101monitors the voltage of the second power line62, and outputs the second reset signal S2to the electronic circuit70from a second output terminal OUT2based on the monitored result.

The reset IC101includes the power terminal VDD, a ground terminal GND, the first and second input terminals VS1and VS2, the first and second output terminals OUT1and OUT2, a first detection circuit10, a second detection circuit20, a third detection circuit30, a first output circuit40, and a second output circuit50.

The power terminal VDD is connected to the third power line67, and the power supply voltage Vdd is input thereto. The ground terminal GND is connected to a reference potential, such as a ground potential or the like. The reset IC101operates with reference to the potential of the ground terminal GND, and operates at the power supply voltage Vdd applied between the power terminal VDD and the ground terminal GND.

The first input terminal VS1is connected to the first power line61, and receives the voltage of the first power line61. The second input terminal VS2is connected to the second power line62, and receives the seizure signal from the second power line62. The first output terminal OUT1is connected to the first reset terminal of the electronic circuit70, and outputs the first reset signal S1generated by the reset IC101. The second output terminal OUT2is connected to the second reset terminal of the electronic circuit70, and outputs the second reset signal S2generated by the reset IC101.

The first detection circuit10is a voltage detection circuit connected to the first input terminal VS1, and operates at the power supply voltage Vdd applied between the power terminal VDD and the ground terminal GND. The first detection circuit10detects a voltage drop (specifically, an undervoltage) at the first input terminal VS1. The first detection circuit10asserts a first signal V1in response to detecting a decrease in a voltage Vs1(specifically, an undervoltage) at the first input terminal VS1. For example, the first detection circuit10asserts the first signal V1when the first detection circuit10detects a state in which the voltage Vs1is lower than a predetermined first threshold value TH1. On the other hand, the first detection circuit10negates the first signal V1when the first detection circuit10detects a state in which the voltage Vs1exceeds the first threshold value TH1.

The second detection circuit20is a voltage detection circuit connected to the first input terminal VS1, and operates at the power supply voltage Vdd applied between the power terminal VDD and the ground terminal GND. The second detection circuit20detects a voltage rise (specifically, an overvoltage) at the first input terminal VS1. The second detection circuit20asserts a second signal V2in response to detecting a rise in the voltage Vs1(specifically, an overvoltage) at the first input terminal VS1. For example, the second detection circuit20asserts the second signal V2when the second detection circuit20detects a state in which the voltage Vs1exceeds a predetermined second threshold value TH2. On the other hand, the second detection circuit20negates the second signal V2when the second detection circuit20detects a state in which the voltage Vs1is lower than the second threshold value TH2. The second threshold value TH2is set to be higher than the first threshold value TH1.

The third detection circuit30is a voltage detection circuit connected to the second input terminal VS2, and operates at the power supply voltage Vdd applied between the power terminal VDD and the ground terminal GND. The third detection circuit30detects a voltage drop (specifically, an undervoltage) at the second input terminal VS2. The third detection circuit30asserts a third signal V3in response to detecting a decrease (specifically, an undervoltage) in a voltage Vs2of the second input terminal VS2. For example, the third detection circuit30asserts the third signal V3when the third detection circuit30detects a state in which the voltage Vs2is lower than a predetermined third threshold value TH3. On the other hand, the third detection circuit30negates the third signal V3when the third detection circuit30detects a state in which the voltage Vs2exceeds the third threshold value TH3.

The first output circuit40monitors the first signal V1and the second signal V2, and outputs the first reset signal S1from the first output terminal OUT1when the first signal V1or the second signal V2is asserted. More particularly, the first output circuit40outputs the first reset signal S1from the first output terminal OUT1when the first detection circuit10detects that the voltage Vs1is lower than the first threshold value TH1, or when the second detection circuit20detects that the voltage Vs1is higher than the second threshold value TH2.

The first output circuit40monitors the first signal V1and the second signal V2, and stops outputting the first reset signal S1from the first output terminal OUT1when the first signal V1and the second signal V2are negated. More specifically, the first output circuit40cancels outputting the first reset signal S1from the first output terminal OUT1while the first detection circuit10detects that the voltage Vs1is higher than the first threshold value TH1, and the second detection circuit20detects that the voltage Vs1is lower than the second threshold value TH2.

The first output circuit40includes a logic circuit41which receives the first signal V1and the second signal V2, and an output stage42configured to output the first reset signal S1according to an output signal G1of the logic circuit41, for example. The logic circuit41operates at the power supply voltage Vdd applied between the power terminal VDD and the ground terminal GND.

The logic circuit41monitors the first signal V1and the second signal V2, and outputs to the output stage42the output signal G1which causes the output stage42to output a low-level first reset signal S1from the first output terminal OUT1when the first signal V1or the second signal V2is asserted. On the other hand, the logic circuit41monitors the first signal V1and the second signal V2, and stops outputting the output signal G1to the output stage42so that the output stage42stops outputting the first reset signal S1from the first output terminal OUT1when both the first signal V1and the second signal V2are negated. Hence, the outputting of the first reset signal S1from the first output terminal OUT1is canceled, and a high-level signal is output from the first output terminal OUT1.

The output stage42includes a transistor43that outputs the first reset signal S1in an open-drain output format. The transistor43is a metal oxide semiconductor field effect transistor (MOSFET) having a gate which receives the output signal G1, a source connected to the ground terminal GND, and a drain connected to the first output terminal OUT1, for example. The first output terminal OUT1is pull-up connected to the third power line67via an external resistor element65. The resistor element65is externally connected to the reset IC101. Because a pull-up voltage of the resistor element65can be set to an arbitrary voltage from the power terminal VDD, a high-level output voltage value of the first output terminal OUT1can be arbitrarily set by the potential of the power terminal VDD.

The second output circuit50monitors the third signal V3, and outputs the second reset signal S2from the second output terminal OUT2when the third signal V3is asserted. More particularly, the second output circuit50outputs the second reset signal S2from the second output terminal OUT2when the third detection circuit30detects that the voltage Vs2is lower than the third threshold value TH3.

The second output circuit50monitors the third signal V3, and stops outputting the second reset signal S2from the second output terminal OUT2when the third signal V3is negated. More particularly, the second output circuit50cancels outputting the second reset signal S2from the second output terminal OUT2when the third detection circuit30detects that the voltage Vs2is higher than the third threshold value TH3.

The second output circuit50includes a logic circuit51which receives the third signal V3, and an output stage52configured to output the second reset signal S2according to an output signal G2from the logic circuit51. The logic circuit51operates at the power supply voltage Vdd applied between the power terminal VDD and the ground terminal GND.

The logic circuit51monitors the third signal V3, and outputs to the output stage52the output signal G2which causes the output stage52to output a low-level second reset signal S2from the second output terminal OUT2when the third signal V3is asserted. On the other hand, the logic circuit51monitors the third signal V3, and stops outputting the output signal G2to the output stage52so that the output stage52stops outputting the second reset signal S2from the second output terminal OUT2when the third signal V3is negated. Hence, the outputting of the second reset signal S2from the second output terminal OUT2is canceled, and a high-level signal is output from the second output terminal OUT2.

The output stage52includes a transistor53that outputs the second reset signal S2in an open-drain output format. The transistor53is a MOSFET having a gate which receives the output signal G2, a source connected to the ground terminal GND, and a drain connected to the second output terminal OUT2, for example. The second output terminal OUT2is pull-up connected to the third power line67via an external resistor element66. The resistor element66is externally connected to the reset IC101. Because a pull-up voltage of the resistor element66can be set to an arbitrary voltage from the power terminal VDD, a high-level output voltage value of the second output terminal OUT2can be arbitrarily set by the potential of the power terminal VDD.

Accordingly, the reset IC101monitors the voltage Vs1of the first input terminal VS1, so as to monitor the voltage of the first power line61connected to the first input terminal VS1. When the reset IC101detects a state in which the voltage Vs1is lower than the first threshold value TH1, the reset IC101outputs a signal having a level (for example, a low level) indicating an abnormally low voltage state from the first output terminal OUT1as the first reset signal S1. Alternatively, when the reset IC101detects a state in which the voltage Vs1exceeds the second threshold value TH2, the reset IC101outputs a signal having a level (for example, a low level) indicating an abnormally high voltage state from the first output terminal OUT1as the first reset signal S1.

On the other hand, when the reset IC101detects a state in which the voltage Vs1is higher than the first threshold value TH1and lower than the second threshold value TH2, the reset IC101outputs a signal having a level (for example, a high level) indicating a normal voltage state from the first output terminal OUT1(cancels outputting the first reset signal S1).

Similarly, the reset IC101monitors the voltage Vs2of the second input terminal VS2, so as to monitor the voltage of the second power line62connected to the second input terminal VS2. When the reset IC101detects a state in which the voltage Vs2is lower than the third threshold value TH3, the reset IC101outputs a signal having a level (for example, a low level) indicating an abnormally low voltage state from the second output terminal OUT2as the second reset signal S2. On the other hand, when the reset IC101detects a state in which the voltage Vs2exceeds the third threshold value TH3, the reset IC101outputs a signal having a level (for example, a high level) indicating a normal voltage state from the second output terminal OUT2(cancels outputting the second reset signal S2).

Accordingly, the reset IC101according to the first embodiment has both a voltage drop detection function for a plurality of channels (in this example, the first power line61and the second power line62) and a voltage rise detection function for a specific channel (in this example, the first power line61). Because the voltage drop detection function for the plurality of channels and the voltage rise detection function for the specific channel can be implemented within the reset IC101of one chip, a component mounting area (that is, a chip area or footprint) can be reduced when compared to a case where these functions are implemented in a plurality of chips.

FIG.2is a timing chart illustrating an operation example of the semiconductor integrated circuit according to the first embodiment. When the voltage Vs1of the first input terminal VS1rises and becomes higher than a judgment voltage VTHU1, the first detection circuit10switches from asserting the first signal V1to negating the first signal V1. When the voltage Vs1drops and becomes lower than a judgment voltage VTHD1, the first detection circuit10switches from negating the first signal V1to the asserting the signal V1. On the other hand, when the voltage Vs1of the first input terminal VS1rises and becomes higher than a judgment voltage VTHU2, the second detection circuit20switches from negating the second signal V2to asserting the second signal V2. When the voltage Vs1drops and becomes lower than a judgment voltage VTHD2, the second detection circuit20switches from asserting the second signal V2to negating the second signal V2.

Accordingly, when the voltage Vs1rises and becomes higher than the judgment voltage VTHU1, the reset IC101cancels outputting the first reset signal S1from the first output terminal OUT1, and thus, the signal output from the first output terminal OUT1switches from a low level to a high level. When the voltage Vs1rises further and becomes higher than the judgment voltage VTHU2, the reset IC101outputs the first reset signal S1from the first output terminal OUT1, and thus, the signal output from the first output terminal OUT1switches from the high level to the low level. When the voltage Vs1drops and becomes lower than the judgment voltage VTHD2, the reset IC101cancels outputting the first reset signal S1from the first output terminal OUT1, and thus, the signal output from the first output terminal OUT1switches from the low level to the high level. When the voltage Vs1drops further and becomes lower than the judgment voltage VTHD1, the reset IC101outputs the first reset signal S1from the first output terminal OUT1, and thus, the signal output from the first output terminal OUT1switches from the high level to the low level.

The judgment voltage VTHD1corresponds to the first threshold value TH1described above, and is an example of a first level. The judgment voltage VTHU2corresponds to the second threshold value TH2described above, and is an example of a second level that is higher than the first level. The judgment voltage VTHU1is an example of a third level that is higher than the first level and lower than the second level. The judgment voltage VTHD2is an example of a fourth level that is higher than the third level and lower than the second level.

On the other hand, when the voltage Vs2of the second input terminal VS2rises and becomes higher than the judgment voltage VTHU3, the second detection circuit20switches from asserting the second signal V2to negating the second signal V2. When the voltage Vs2drops and becomes lower than the judgment voltage VTHD3, the second detection circuit20switches from negating the second signal V2asserting the second signal V2.

Accordingly, when the voltage Vs2rises and becomes higher than the judgment voltage VTHU3, the reset IC101cancels outputting of the second reset signal S2from the second output terminal OUT2, and thus, the signal output from the second output terminal OUT2switches from a low level to a high level. When the voltage Vs2drops and becomes lower than the judgment voltage VTHD3, the reset IC101outputs the second reset signal S2from the second output terminal OUT2, and thus, the signal output from the second output terminal OUT2switches from the high level to the low level. The judgment voltage VTHU3is set to be higher than the judgment voltage VTHD3.

FIG.3is a diagram illustrating an example of an internal circuit of the semiconductor integrated circuit according to the first embodiment.FIG.3illustrates an example of the internal circuit of the reset IC101. The reset IC101includes the first detection circuit10, the second detection circuit20, the third detection circuit30, the first output circuit40, and the second output circuit50.

The first detection circuit10and the second detection circuit20monitor the voltage Vs1of the first input terminal VS1. The reset IC101includes a diode68having an anode thereof connected to the ground terminal GND and a cathode thereof connected to the first input terminal VS1. The diode68clamps the negative voltage Vs1by a forward voltage of the diode68, and thus, the reset IC101is protected from the input of the negative voltage Vs1. Because the diode68is shared by the first detection circuit10and the second detection circuit20, it is possible to reduce the size and cost of the reset IC101.

The third detection circuit30monitors the voltage Vs2of the second input terminal VS2. The reset IC101includes a diode69having an anode thereof connected to the ground terminal GND and a cathode thereof connected to the second input terminal VS2. The diode69clamps the negative voltage Vs2by a forward voltage of the diode69, and thus, the reset IC101is protected from the input of the negative voltage Vs2.

The first detection circuit10monitors the voltage Vs1of the first input terminal VS1. The first detection circuit10asserts the first signal V1when the voltage drop state of the voltage Vs1is detected, and in this case, outputs a high-level first signal V1. On the other hand, the first detection circuit10negates the first signal V1when the voltage drop state of the voltage Vs1is not detected, and in this case, outputs a low-level first signal V1.

The first detection circuit10includes a resistive voltage divider18(resistors11,12, and13), a comparator17, a transistor14, and a reference voltage generation circuit19(a constant current source15and a reference voltage source16).

The resistive voltage divider18is a monitoring circuit configured to monitor the voltage Vs1of the first input terminal VS1. The resistive voltage divider18is a series circuit, including the resistor11, the resistor12, and the resistor13, and connected between the ground terminal GND and the first input terminal VS1. The resistive voltage divider18outputs a detection voltage Vs11, obtained by dividing the voltage Vs1, from a node between the resistor11and the resistor12. That is, the detection voltage Vs11has a value corresponding to the voltage Vs1.

When an output voltage (first signal V1) of the comparator17has a low level, the transistor14is turned off, and thus, the resistive voltage divider18outputs the detection voltage Vs11obtained by dividing the voltage Vs1by the resistor11and the resistors12and13. When the output voltage (first signal V1) of the comparator17has a high level, the transistor14is turned on, and thus, the resistive voltage divider18outputs the detection voltage Vs11obtained by dividing the voltage Vs1by the resistor11and the resistor12. Accordingly, a magnitude comparison between the detection voltage Vs11generated by the resistive voltage divider18and a reference voltage VREF generated by the reference voltage generation circuit19can exhibit a hysteresis (=“judgment voltage VTHU1”−“judgment voltage VTHD1”).

The comparator17compares magnitudes of the detection voltage Vs11and the reference voltage VREF, and outputs the first signal V1according to the comparison result. The reference voltage VREF has a constant voltage value generated by the reference voltage generation circuit19by performing step-down conversion on the power supply voltage Vdd. The reference voltage VREF is input to a non-inverting input terminal of the comparator17, and the detection voltage Vs11is input to an inverting input terminal of the comparator17. The comparator17outputs a high-level first signal V1when the detection voltage Vs11is lower than the reference voltage VREF, and outputs a low-level first signal V1when the detection voltage Vs11is higher than the reference voltage VREF.

The reference voltage generation circuit19generates a constant reference voltage VREF that is lower than the power supply voltage Vdd, by causing a constant current flowing from the constant current source15to flow to the reference voltage source16, for example. The constant current source15is configured by a depletion type MOSFET having a drain thereof connected to the power supply voltage Vdd and a gate and a source thereof that are short-circuited, for example. The reference voltage source16is configured by a diode-connected depletion type MOSFET, for example.

The second detection circuit20monitors the voltage Vs1of the first input terminal VS1. The second detection circuit20asserts the second signal V2when the voltage rise state of the voltage Vs1is detected, and in this case, outputs a low-level second signal V2. On the other hand, the second detection circuit20negates the second signal V2when the voltage rise state of the voltage Vs1is not detected, and in this case, outputs a high-level second signal V2.

The second detection circuit20includes a resistive voltage divider28(resistors21,22, and23), a comparator27, a transistor24, and a reference voltage generation circuit29(a constant current source25and a reference voltage source26). The second detection circuit20has the same configuration as the first detection circuit10.

The resistive voltage divider28is a monitoring circuit configured to monitor the voltage Vs1of the first input terminal VS1. The resistive voltage divider18is a series circuit, including the resistor21, the resistor22, and the resistor23, and connected between the ground terminal GND and the first input terminal VS1. The resistive voltage divider28outputs a detection voltage Vs12, obtained by dividing the voltage Vs1, from a node between the resistor21and the resistor22. That is, the detection voltage Vs12has a value corresponding to the voltage Vs1.

When an output voltage (second signal V2) of the comparator27has a low level, the transistor24is turned off, and thus, the resistive voltage divider28outputs the detection voltage Vs12obtained by dividing the voltage Vs1by the resistor21and the resistors22and23. When the output voltage (second signal V2) of the comparator27has a high level, the transistor24is turned on, and thus, the resistive voltage divider28outputs the detection voltage Vs12obtained by dividing the voltage Vs1by the resistor21and the resistor22. Accordingly, a magnitude comparison between the detection voltage Vs12generated by the resistive voltage divider28and the reference voltage VREF generated by the reference voltage generation circuit29can exhibit a hysteresis (=“judgment voltage VTHU2”−“judgment voltage VTHD2”).

The comparator27compares magnitudes of the detection voltage Vs12and the reference voltage VREF, and outputs the second signal V2according to the comparison result. The reference voltage VREF has a constant voltage value generated by the reference voltage generation circuit29by performing step-down conversion on the power supply voltage Vdd. The reference voltage VREF is input to a non-inverting input terminal of the comparator27, and the detection voltage Vs12is input to an inverting input terminal of the comparator27. The comparator27outputs a high-level second signal V2when the detection voltage Vs12is lower than the reference voltage VREF, and outputs a low-level second signal V2when the detection voltage Vs12is higher than the reference voltage VREF.

The reference voltage generation circuit29generates a constant reference voltage VREF that is lower than the power supply voltage Vdd, by causing a constant current flowing from the constant current source25to flow to the reference voltage source26, for example. The constant current source25is configured by a depletion type MOSFET having a drain thereof connected to the power supply voltage Vdd and a gate and a source thereof that are short-circuited, for example. The reference voltage source26is configured by a diode-connected depletion type MOSFET, for example.

The third detection circuit30monitors the voltage Vs2of the second input terminal VS2. The third detection circuit30asserts the third signal V3when the voltage drop state of the voltage Vs2is detected, and in this case, outputs a high-level third signal V3. On the other hand, the third detection circuit30negates the third signal V3when the voltage drop state of the voltage Vs2is not detected, and in this case, outputs a low-level third signal V3.

The third detection circuit30includes a resistive voltage divider38(resistors31,32, and33), a comparator37, a transistor34, and a reference voltage generation circuit39(a constant current source35and a reference voltage source36). The third detection circuit30has the same configuration and function as the first detection circuit10, and thus, a description thereof will be omitted by incorporating the above description of the first detection circuit10.

The first output circuit40monitors logic levels of the first signal V1and the second signal V2. The first output circuit40includes a logic circuit41and an output stage42. The logic circuit41includes an inverter circuit46that outputs a signal obtained by inverting the logic of the first signal V1, and a NAND circuit45that outputs the output signal G1that is an inverted logical product (NAND) of an output signal of the inverter circuit46(a logically inverted signal of the first signal V1) and the second signal V2. The output stage42includes a transistor43which receives the output signal G1, and a diode44connected in parallel to the transistor43.

Accordingly, when the first signal V1has a high level and the second signal V2has a high level, the first output circuit40determines that the voltage drop state of the voltage Vs1is detected, and sets the output signal G1to a high level. As a result, the transistor43is turned on, and a low-level signal is output from the first output terminal OUT1(the first reset signal S1is output). When the first signal V1has a low level and the second signal V2has a low level, the first output circuit40determines that the voltage Vs1is in the voltage rise state and sets the output signal G1to a high level. As a result, the transistor43is turned on, and a low-level signal is output from the first output terminal OUT1(the first reset signal S1is output). When the first signal V1has the low level and the second signal V2has the high level, the first output circuit40determines that the voltage Vs1is in a normal voltage state and sets the output signal G1to the low level. As a result, the transistor43is turned off, and a high-level signal is output from the first output terminal OUT1(the first reset signal S1is canceled).

The second output circuit50monitors a logic level of the third signal V3. The second output circuit50includes a logic circuit51and an output stage52. The logic circuit51includes an inverter circuit55that outputs a signal obtained by inverting the logic of the third signal V3, and an inverter circuit56that outputs the output signal G2by inverting the logic of an output signal of the inverter circuit55(the logically inverted signal of the third signal V3). The output stage52includes a transistor53which receives the output signal G2, and a diode54connected in parallel to the transistor53.

Accordingly, when the third signal V3has a high level, the second output circuit50determines that the voltage Vs2is in the voltage drop state, and sets the output signal G2to a high level. As a result, the transistor53is turned on, and a low-level signal is output from the second output terminal OUT2(the second reset signal S2is output). When the third signal V3has a low level, the second output circuit50determines that the voltage Vs2is in the normal voltage state, and sets the output signal G2to a low level. As a result, the transistor53is turned off, and a high-level signal is output from the second output terminal OUT2(the second reset signal S2is canceled).

FIG.4is a diagram illustrating a configuration example of the electronic apparatus including the semiconductor integrated circuit according to a second embodiment. In the second embodiment, a description of the configuration, operation, and effects that are the same as those of the first embodiment will be omitted, by incorporating the above description of the first embodiment. An electronic apparatus202illustrated inFIG.4includes a reset IC102. The reset IC102is an example of the semiconductor integrated circuit according to the second embodiment. The reset IC102according to the second embodiment differs from the reset IC101according to the first embodiment in that the output stages42and52of the reset IC102employ a complementary metal oxide semiconductor (CMOS) output format. The output stage42and52operate at the power supply voltage Vdd applied between the power terminal VDD and the ground terminal GND.

The output stage42includes transistors43and47which output the first reset signal S1with the CMOS output format. The output stage42includes an inverter circuit having a complementary combination of the transistors43and47. Because the output stage42employs the CMOS output format, the resistor element65(refer toFIG.1) can be eliminated, and a current consumption a current flowing to the transistor43via the resistor element65in an on state of the transistor43can be reduced.

The output stage52includes transistors53and57which output the second reset signal S2with the CMOS output format. The output stage52includes an inverter circuit having a complementary combination of the transistors53and57. Because the output stage52employs the CMOS output format, the resistor element66(refer toFIG.1) can be eliminated, and a current consumption of a current flowing to the transistor53via the resistor element66in an on state of the transistor53can be reduced.

FIG.5is a diagram illustrating a configuration example of the electronic apparatus including the semiconductor integrated circuit according to the third embodiment. In the third embodiment, a description of the configuration, operation, and effects that are the same as those of the first embodiment will be omitted, by incorporating the above description of the first embodiment. An electronic apparatus203illustrated inFIG.4includes a reset IC103. The reset IC103is an example of the semiconductor integrated circuit according to the third embodiment. The reset IC103according to the third embodiment differs from the reset IC101according to the first embodiment in that the power terminal VDD is shared with the first input terminal VS1(the power terminal VDD is removed).

Because the power terminal VDD is shared with the first input terminal VS1, it is possible to reduce the number of terminals required for the reset IC. Further, because the power terminal VDD is shared with the first input terminal VS1, the functions of the reset IC can be extended or enhanced using the remaining terminals.

The first detection circuit10, the second detection circuit20, and the third detection circuit30operate at a power supply voltage (in this case, the voltage Vs1) applied between the first input terminal VS1and the ground terminal GND. For example, inFIG.3, the comparators17,27, and37, the reference voltage generation circuits19,29, and39, and the logic circuits41and51operate at the voltage Vs1.

FIG.6is a diagram illustrating a first example of a pin arrangement of the semiconductor integrated circuit.FIG.7is a diagram illustrating a second example of the pin arrangement of the semiconductor integrated circuit.FIG.6andFIG.7are plan views schematically illustrating a reset IC covered with a package80of a 6-terminal small outline transistor (SOT). The package80has two side surfaces81and82and opposing each other. Pins1,2, and3are external connection terminals provided on the side surface81. Pins4,5, and6are external connection terminals provided on the side surface82.

In the case illustrated inFIG.6, the first input terminal VS1is arranged at the pin1, the power terminal VDD is arranged at the pin2, the second input terminal VS2is arranged at the pin3, the second output terminal OUT2is arranged at the pin4, the ground terminal GND is arranged at the pin5, and the first output terminal OUT1is arranged at the pin6.

In the case illustrated inFIG.7, the second input terminal VS2is arranged at the pin1, the second output terminal OUT2is arranged at the pin2, the first input terminal VS1is arranged at the pin3, the power terminal VDD is arranged at the pin4, the ground terminal GND is arranged at the pin5, and the first output terminal OUT1is arranged at the pin6.

In general, after an IC is mounted on a circuit board or printed circuit board (PCB), the IC may often be damaged by a short-circuit between adjacent terminals caused by a foreign substance (solder, dust, water droplet, or the like), a short-circuit caused by a whisker (phenomenon in which a metal single crystal naturally grows on a metal surface), or the like depending on the arrangement of the pins. In the pin arrangements illustrated inFIG.6andFIG.7, the first and second input terminals VS1and VS2are not adjacent to the ground terminal GND. For this reason, a short-circuit is unlikely to occur between the first input terminal VS1and the ground terminal GND, nor between the second input terminal VS2and the ground terminal GND. Accordingly, the possibility of a dead short occurring between the first input terminal VS1and the ground terminal GND, or between the second input terminal VS2and the ground terminal GND, can be reduced to a minimum.

But in the pin arrangement illustrated inFIG.6, the first input terminal VS1which is arranged at the pin1and receives a voltage of 12 volts and the power terminal VDD which is arranged at the pin2and receives a voltage of 3.3 volts are adjacent to each other. If the first input terminal VS1and the power terminal VDD were to cause a short-circuit between the adjacent pins1and2, an overvoltage of 12 volts may be applied to the electronic circuit70which is to be driven at 3.3 volts. Similarly, the second input terminal VS2which is arranged at the pin3and receives a voltage of 12 volts and the power terminal VDD which is arranged at the pin2and receives a voltage of 3.3 volts are adjacent to each other. If the second input terminal VS2and the power terminal VDD were cause a short-circuit between the adjacent pins3and2, an overvoltage of 12 volts may be applied to the electronic circuit70which is to be driven at 3.3 volts.

In the pin arrangement illustrated inFIG.7, the power terminal VDD are provided on the side surface82, and is thus not adjacent to the first input terminal VS1and the second input terminal VS2provided on the side surface81. Thus, a short-circuit between the power terminal VDD and the first input terminal VS1arranged at the pins3and4, and a short-circuit between the power terminal VDD and the second input terminals VS2arranged at the pins4and1, are unlikely to occur. Hence, the possibility of an overvoltage being applied to the electronic circuit70can be reduced to a minimum.

The type of the package80is not limited to the SOT. The package80may be a package for through-hole mounting, such as a single in-line package (SIP), a dual in-line package (DIP), or the like. The package80may be a surface mount package, such as a small outline package (SOP), a small outline non-leaded package (SON), or the like.

The embodiments described above are presented as examples, and the present invention is not limited to the described embodiments. The embodiments described above can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, or the like can be made without departing from the scope and spirit of the invention. These embodiments and modifications thereof are included in the scope and spirit of the invention, and are included in the invention described in the claims and the scope of equivalents thereof.

For example, the semiconductor integrated circuit to which the contents of the present disclosure can be applied is not limited to the reset IC, and may be other semiconductor integrated circuits, such as a power supply IC, a power management IC, or the like.

Further, the signal line for transmitting the seizure signal for activating the electronic apparatus may be an ignition power line for transmitting an ignition signal instead of the accessory power line for transmitting the accessory signal.

The electronic apparatus is not limited to an apparatus for the vehicle, and may be other electronic apparatuses for use other than the use for the vehicle. The first power line61and the second power line62are not limited to the power lines of the battery power supply system and the accessory power supply system, and may be a plurality of different power lines. For example, one of the first power line61and the second power line62may be a 5 volt power line, and the other may be a 3.3 volt power line.

In addition, the first reset signal S1and the second reset signal S2are not limited to the combination of the low active signal and the low active signal, and may be a combination of a low active signal and a high active signal, or a combination of a high active signal and a low active signal, or a combination of a high active signal and a high active signal. The output formats of the first output circuit40and the second output circuit50may be modified, as appropriate.

Moreover, the contents of the present disclosure are not limited to the semiconductor integrated circuit configured to monitor the voltages of two channels, and may be applied to a semiconductor integrated circuit configured to monitor voltages of three or more channels.

Further, the semiconductor integrated circuit to which the present disclosure can be applied may further include a fourth detection circuit configured to detect a voltage rise (more particularly, an overvoltage) of the second input terminal VS2. A configuration of the fourth detection circuit may be the same as that of the second detection circuit20.

The present disclosure can provide a semiconductor integrated circuit having both a voltage drop detection function for a plurality of channels and a voltage rise detection function for a specific channel, and an electronic apparatus including the semiconductor integrated circuit.