Semiconductor device with structured current spread region and method

A semiconductor device with structured current spread region and method is disclosed. One embodiment provides a drift portion of a first conductivity type, a current spread portion of the first conductivity type and first portions of the first conductivity type. The current spread portion and the first portions are arranged in a first plane on the drift portion, wherein the current spread portion surrounds at least partially the first portions. The semiconductor body further includes spaced apart body regions of a second conductivity type which are arranged on the current spread portion. Further, the doping concentration of the current spread portion is higher than the doping concentrations of the drift portion and of the first portions.

BACKGROUND

Electronically-controlled switching devices such as a Metal Oxide Semiconductor Field Effect Transistors (MOSFET) or a Junction Field Effect Transistors (JFET) have been used for various applications.

Particularly with regard to but not limited to power devices, capable of switching large currents, a low resistance in the conducting on-state and a high breakdown voltage in the off-state are desired. This is to minimize losses in the on-state and to avoid possible damage in the off-state at higher voltages that may occur during operation of the device.

DETAILED DESCRIPTION

The term “lateral” as used in this specification intends to describe an orientation parallel to a first surface of a semiconductor substrate or body. This can be for instance the surface of a wafer or a die. The first plane extends substantially parallel to the first surface and thus in a lateral direction.

The term “vertical” as used in this specification intends to describe an orientation which is arranged perpendicular to the first surface and the first plane of the semiconductor substrate or body.

Specific embodiments described in this specification pertain to voltage-controlled semiconductor resistances and to switching semiconductor devices, in one embodiment to field-effect controlled power semiconductor devices such as vertical JFETs and vertical MOSFETs.

Herein described is a semiconductor device, in one embodiment a power switching device, including a structured current spread portion and a manufacturing method therefor. According to one embodiment, a semiconductor device is provided. The semiconductor device includes a drift portion of a first conductivity type, a current spread portion of the first conductivity type and first portions of the first conductivity type. The current spread portion and the first portions, which are at least partially surrounded by the current spread portion, are arranged in a first plane on the drift portion. The semiconductor body further includes spaced apart body regions of a second conductivity type which are arranged on the current spread portion. Further, the doping concentration of the current spread portion is higher than the doping concentrations of the drift portion and of the first portions.

Due to the higher conductivity of the current spread portion, the current can be broader spread in the drift portion, thereby decreasing the on-state resistance of the device. In the off-state the first portions of the drift region reduce the electric field strength in certain areas of the semiconductor body near the body regions, thereby increasing the break-down voltage of the device.

FIG. 1illustrates one embodiment of a semiconductor device in a plan view or projection on a first plane40which runs substantially parallel to a first surface30of a semiconductor substrate or body20as illustrated inFIGS. 2A and 2B. In a vertical cross-section the semiconductor device ofFIG. 1can be structured as presented inFIG. 2A. In particular,FIG. 2Aillustrates a section of the semiconductor device in a plane d between A′ and A as depicted inFIG. 1. The plane d runs substantially perpendicular to the first surface30and the first plane40of the semiconductor body20.

The semiconductor substrate or body20can be for instance a wafer or a die. The semiconductor device includes the semiconductor body20, which can for example be comprised of silicon carbide (SiC). The material of the semiconductor body is, however, not limited to SiC and can also include Si or GaN.

The semiconductor body20includes a first semiconductor region1of a first conductivity type including a first doping concentration. Typically, the first semiconductor region1forms a drift portion1of a drift region21. In the following description, the term “drift portion” is used and includes the term “first semiconductor region”. This should, however, not be considered as a limitation. Typically the drift portion1can have a first doping concentration of about 1*1015/cm3to about some 1016/cm3particularly in case of SiC.

On the drift portion1a second semiconductor region22of the first conductivity type is arranged in the first plane40which extends substantially parallel to the first surface30of the semiconductor body20.

The term “arranged in a plane” intends to describe that the respective semiconductor regions or portions are intersected by the plane. If a semiconductor region or portion includes more than one sub-region, the term “arranged in a plane” intends to describe that all sub-regions are intersected by the plane. Typically, the second semiconductor region or portion22includes a significantly smaller extension in a vertical direction and is substantially orientated parallel to the first plane40. Further, the second semiconductor region or portion22is typically flat and has a layer-like arrangement.

The second semiconductor region22is typically in contact with the drift portion1and forms, as a part of the drift region21, a structured current spread region or portion22. In the following description, the term “structured current spread region” is used and includes the term “second semiconductor region”. This should, however, not be considered as a limitation.

The structured current spread region22includes at least a first portion4having a third doping concentration and at least a second portion2having a second doping concentration which is higher than the third doping concentration. The first portion4and the second portion2are typically arranged in the first plane40. Further, the first portion4and second portion2are of the first conductivity type. Typically, they are part of the drift region21, whereas the second portion2forms a current spread portion2. In the following description, the term “current spread portion” is used and includes the term “second portion”. This should, however, not be considered as a limitation. In other words, the semiconductor device includes a drift region21which includes the drift portion1and the structured current spread region22. The structured current spread region22is arranged in the first plane40on the drift portion1and includes first portions4and the current spread portion2. The current spread portion2includes the second doping concentration which is higher than the doping concentration of the drift portion1. The second doping concentration typically ranges from about 1*1016/cm3to about 1*1017/cm3particularly in case of SiC.

In one or more embodiments, referring to power semiconductor devices, the structured current spread region22includes several or a plurality of first portions4.

Typically, the doping concentration of the drift portion1and of the first portions4are substantially equal. The first portions4are regions of the drift region21, which are for example not doped during formation of the current spread portions2as becomes apparent from the description below. This simplifies manufacturing process and, therefore, reduces overall production time and costs.

According to one or more embodiments, the first portions4are partially surrounded by the current spread portion2. In a projection on the first plane40they are typically completely surrounded by the current spread portion2. The first portions4are usually in contact with the drift portion1. Therefore the first portions4are only partially surrounded by the current spread portion2in a vertical cross-section.

Usually, the lateral extension of the current spread portion2is larger then its vertical extension. The vertical thickness of the current spread portion2ranges typically from about 0.5 μm to about 1.0 μm for SiC. A typical blocking voltage ranges of those devices ranges from about 600V to about 1200V. In other words, the current spread portion2can be formed as a current spread layer. In this case, the structured current spread region22is formed as a structured or composite current spread layer22.

The semiconductor body20further includes at least a third semiconductor region3of a second conductivity type which is arranged on the current spread portion2on a side opposite to the drift portion1. In one or more embodiments, the first and second conductivity types correspond to n dopant type and p dopant type, respectively. It will be appreciated by those skilled in the art that the doping can be reversed. The doping concentration of the third semiconductor regions ranges typically from about 1*1018/cm3to about 1*1020/cm3.

The third semiconductor region3can form a body region3. In the following description, the term “body region” is used and includes the term “third semiconductor region”. This should, however, not be considered as a limitation.

In one or more embodiments, referring to power semiconductor devices, the semiconductor body20includes several or a plurality of body regions3which are spaced apart from each other, thereby forming several or a plurality of semiconductor cells.

Usually, the body regions3are in contact with the current spread portion2. Body regions3are arranged on current spread portion2on a side opposite to drift portion1. Further, the body regions3can be isolated form each other by spacer portions9of the first conductivity type. The spacer portions9can at least partially belong to the drift region21. As such their doping concentrations can be substantially equal to the first doping concentration.

The first portion4and the spacer portion9can further be designed such that they have substantially the same lateral extension in at least a first cross-section perpendicular to the first plane40. The first portion4and the spacer portion9can be designed such, that the first portion4has a larger lateral extension than the spacer portion9, in the first cross-section (perpendicular to the first plane40). In this case, body portions3partially overlaps, in the cross-section, the first portions4which provides even better improvement of the electrical field distribution on critical corner or edge regions of the body regions as it becomes more apparent from the description below (seeFIG. 2A).

In another cross-section (A″-A inFIG. 1), which is perpendicular to the first plane40but not parallel to the first cross-section, the current spread region22is not structured and hence, no first portions4exist. Cross-section A″-A is illustrated inFIG. 2B. In fact, the current spread portion22extends into the spacer portion9so that the spacer portions9will have substantially the same doping concentration as the current spread portion2. Typically, the spacer regions9between portions of adjacent body regions, which run substantially parallel to each other, have the same doping concentration as the current spread portion2. By increasing the doping concentration in those spacer regions9, parasitic JFETs between adjacent body regions3can be prevented. Further, the on-state resistance of the device can be improved.

PN-junctions are typically formed between the body region3and the adjoining regions, especially between the body region3and the current spread portion2and the spacer portion9, respectively.

In operating the semiconductor device, a current path is at least partially formed within the drift region21to provide a substantially vertical current flow. The resistance of the device can be adjusted by controlling the extension of a depletion region at certain pn-junctions. In order to minimize the Ohmic losses in the low resistance on-state the current is spread in the drift portion1by the current spread portion2. Therefore, the doping concentration of the current spread portion2typically exceeds the first doping concentration by a factor of about 2 to about 20.

In one embodiment, a power semiconductor device, several or a plurality of substantially identical semiconductor cells are switched in parallel, thereby increasing the switchable current. For this purpose the body regions3can, in a lateral direction, be evenly distributed or lattice-like arranged in the semiconductor body20. The embodiment illustrated inFIG. 1 and 3pertain to arrangements of the body regions3on a lateral square lattice and on a lateral triangular or hexagonal lattice, respectively. In further embodiments, the body regions3can be arranged on a one-dimensional lattice or a lattice of rhombic or rectangular or hexagonal symmetry or on any other regular lateral lattice.FIGS. 2A and 2Bcan pertain to any of the embodiments having lattice like arranged body regions3, in particular to arrangements of the body regions3on a lateral triangular, hexagonal or square lattice. Further,FIGS. 2A and 2Bcan pertain to embodiments of semiconductor devices having a few or even only two cells.

In one or more embodiments a respective first portion4is arranged, in a plan view from a direction normal to the first plane40, at least between adjacent body regions3in an area defined by at least three adjacent body regions3. This means, that, in the plan view, the contour or outline of the first portion4lies completely within an area spanned by the centres of the at least three adjacent body regions3. An example corresponding to three adjacent body regions3is given inFIG. 3. In case of four adjacent body regions, as for instance illustrated inFIGS. 1 and 4, the contour or outline of respective first portions4lies completely within an area spanned by the centres of four adjacent body regions3.

In other words, the semiconductor body20of the semiconductor device includes the first semiconductor region1of the first conductivity type and the second semiconductor region22of the first conductivity type which is arranged in the first plane40on the first semiconductor region1. The second semiconductor region includes several or a plurality of first portions4of the first doping concentration and at least one second portion2of the second doping concentration which is higher then the first doping concentration. The semiconductor body20further includes several or a plurality of third semiconductor regions3of the second conductivity type which are arranged on the second portion2of the second semiconductor region22. Further, a respective first portion4is arranged at least between adjacent third semiconductor regions3in an area defined by at least two or three, and particularly by at least four adjacent third semiconductor regions3. The location, where the first portions4are arrange, depends on the layout of the body regions. For example, when considering a stripe layer, first portions are arranged between adjacent strips at their ends, since there the stripes have corners or at least curved regions. In a hexagonal layout as illustrated inFIG. 3the first portions are arranged between three adjacent body regions3while the first portions4are arranged between four adjacent body regions in case of the square layout ofFIG. 1.

In a plan view from a direction normal to the first plane40, the outline of the first portion4can touch or cross the outline of at least one of the at least two or three adjacent body regions3or can lie completely between the outlines of the at least two or three adjacent or neighbouring body regions3. Typically, the shape and the position of the outline of the portions4is chosen such, that the average distance and/or overlap with each of the at least three neighbouring body regions3is substantially equal in the plane view. This ensures a uniform current and load distribution between the individual current paths and cells. Further, the first portions4are usually simply connected in a mathematical sense.

In the embodiment illustrated inFIG. 1a respective portion4is located, in a plan view from a direction normal to the first plane40, between four directly neighbouring body regions3adjoining the respective first portion4. Different thereto,FIG. 3illustrates an embodiment in which, in the plane view, the area of the respective first portion4is bounded by the three corner regions of the body regions3next to each other on the lateral hexagonal or triangular lattice.

In the plan view from a direction normal to the first plane40of the embodiments illustrated inFIG. 1 and 3, a respective first portion4is centrally arranged between and adjoins the adjacent body regions3. Further, the first portions4are lattice-like arranged related to the arrangement of the body regions3. Typically, the first portions4are arranged on a lattice which is displaced with respect to the lattice of the body regions3. In other words, the first portions4can be placed, in the plane view, interstitial between the body regions3. Typically, a regular lattice is formed by the centre positions of the body regions3and first portions4. This ensures a uniformly distributed load between the plurality of cells of the power semiconductor device.

In a one or more embodiment the first portions4are arranged at least in an area where, in a projection on the first plane40, the contour of the body region3is at least partially curved.

In other words, the semiconductor body20of the semiconductor device includes the first semiconductor region1of the first conductivity type and the second semiconductor region22of the first conductivity type which is arranged in the first plane40on the first semiconductor region1. The second semiconductor region includes at least one first portion4of the first doping concentration and at least one second portion2of the second doping concentration which is higher then the first doping concentration. The semiconductor body20further includes at least one third semiconductor regions3of the second conductivity type which is arranged on the second portion2of the second semiconductor region22. Further, the third semiconductor region3has, in the plan view from a direction normal to the first plane40, a curved contour at least in the proximity to the first portion4.

The term “curved” related to an outline or contour as used in this description intends to describe points of an outline or contour including a finite curvature or being a corner. In other words, an outline or contour is considered to be curved in any point in which the outline or contour deviates from a straight line. Accordingly,FIG. 1 and 3correspond to embodiments in which the first portions4are placed, in the projection on the first plane40, in areas proximate and adjoining the areas where the outline of the body regions3have a finite curvature and a corner, respectively.

Further, the first portions4can cover or overlap, in the plan view from a direction normal to the first plane, areas where the third semiconductor regions include a curved contour.

With respect toFIG. 4, another embodiment will be described. In addition to the embodiments illustrated inFIGS. 1 to 3a fifth semiconductor region5of the first conductivity type is arranged on each of the body regions3. Typically, the fifth semiconductor region5forms a source region. Therefore, it has a higher doping concentration than a channel region10as explained below. In the following description, the term “source region” is used and includes the term “fifth semiconductor region”. This should, however, not be considered as a limitation. The doping concentration of the source region5typically ranges from about 1*1019/cm3to about 1*1020/cm3.

In one or more embodiments the source region5is, in the plan view from a direction normal to the first plane40, enclosed by the body region3.

With reference toFIG. 5A, further embodiments will be described. The structure of the embodiment illustrated inFIG. 5Acan be based on any of the above described embodiments including the advantages mentioned. Similar to the above described embodiments,FIG. 5Aillustrates a semiconductor body20which includes a drift region21. The drift region21includes the drift portion1of the first conductivity type and the structured current spread region or layer22which is arranged in the first plane40on the drift portion1. The structured current spread region or layer22includes, in a cross-section perpendicular to the first plane40, at least two current spread portions2of the first conductivity type which have a higher doping concentration than the drift portion1, and at least one first portion4of the first conductivity type which is arranged between the two current spread portions2and includes a lower doping concentration than the current spread portions2. The semiconductor body20further includes, in the cross-section perpendicular to the first plane40, at least two body regions3which are arranged on the current spread portions2on a side opposite to the drift portion1, and at least two source regions5of the second conductivity type. The source regions5are arranged on the body regions3which are spaced apart by at least one spacer portion9of the first conductivity type which is arranged on the first portion4of the structured current spread layer22.

A front electrode51can be arranged on the first surface30of the semiconductor body20and in contact with the source region5. Typically, a pn-junction between the body region3and the adjoining source region5is formed. To avoid biasing this pn-junction an electrical contact between the front electrode51and the body region3can additionally be provided. Further, several or a plurality of body regions3and/or source regions5can be contacted to one front electrode51.

For exemplification,FIG. 5contains symbols corresponding to typical doping relations. In this case n and p refer to n-doping and p-doping, respectively. It will be appreciated by those skilled in the art that the doping can be reversed. Doping concentrations that are higher and lower than certain concentrations are indicated by the superscripts “+” and “−”, respectively.

Additionally, a drain region8of the first conductivity type can be arranged below the drift portion1of the drift region21. The drain region8has usually a comparatively high doping concentration n+typically ranging from about 1*1018/cm3to about 1*1020/cm3and can adjoin the drift portion1of the drift region21. Further, a field stop portion7of the first conductivity type can be arranged between the drift portion1and drain region8. The field stop portion7has a doping concentration n, that is lower then the doping concentration n+of the drain region8but higher than the doping concentration n−of the drift portion1.

In one or more embodiments the drain region8is contacted to a back metallisation or back electrode81. The back electrode81is typically formed on a second surface31opposite to the first surface30. Further, several or a plurality of cells can be contacted to one back electrode. This is especially useful for power semiconductor devices.

The semiconductor body20can further include a fourth semiconductor region10of the first conductivity type which is arranged on and in contact with the body regions3, thereby forming pn-junctions. The fourth semiconductor region10typically forms a channel region10. In the following description, the term “channel region” is used and includes the term “fourth semiconductor region”. This should, however, not be considered as a limitation.

Typically, the source region5is also in contact with the channel region10for providing a low-resistance contact of the channel region10. In other words, the source region5adjoins a respective channel region10.

In one or more embodiments the doping concentration of the channel region10is higher than the doping concentration n−of the drift portion1. The doping concentration of the channel region10defines the pinch-off voltage and should therefore appropriately adjusted. Further, the channel region10can be in contact with the spacer region9which has typically also a doping concentration that is substantially equal to the doping concentration n−of the drift portion1. Thus a unipolar current path between the drift region1and the source regions5is provided by the first portion4, the spacer portion9, and the channel region9. Since the spacer portions9are higher doped in regions where two adjacent body regions9run substantially parallel to each other (seeFIGS. 1 and 2B) those regions significantly contribute to the current path in the on-state due to their reduced resistance in comparison with low doped spacer portions9(FIG. 2A). The channel region10can be in contact with several body regions3and source regions5. Thereby, the respective source regions5of several or a plurality of cells of e.g., a power semiconductor device can be connected by a unipolar current path with the drift portion1.

Typically, the lateral extension of the channel region10is larger then its vertical extension. In other words, the channel region10substantially extends along a lateral plane. Further, the channel region10can at least partially extend into the spacer portion9or partially be arranged on and be in contact with the spacer portion9. The vertical thickness of channel region10ranges typically from about 500 nm to about 3 μm.

In one or more embodiments at least a sixth semiconductor region6of the second conductivity type is arranged on and in contact with the channel region10, thereby forming a pn-junction. Typically, the sixth semiconductor region6forms a gate region. In the following description, the term “gate region” is used and includes the term “sixth semiconductor region”. This should, however, not be considered as a limitation. The gate region6is typically arranged on the channel region10, such that the channel region10is arranged between the body regions3and the gate region6. The doping concentration of the gate region6(p+) is typically higher than the doping concentration of the body region3.

The semiconductor body20can further include a gate electrode61in contact with the gate region6. Further, several or a plurality of gate regions6can be contacted to a common gate electrode61.

The embodiment illustrated inFIG. 5Arefers to a JFET, more particular to a vertical JFET. If the dopants are distributed as indicated inFIG. 5Athe illustrated embodiment refers to an n-channel JFET. If a voltage difference between the source electrode51and the back electrode81is applied, an electric current between the two electrodes can flow through the n-dopant type areas ofFIG. 5A(on-state). The source electrode51can be at ground while a positive voltage, for instance of about few V or higher, is applied to the back electrode81. The device has a comparatively low resistance because the current is laterally spread wider in the drift portion1by the current spread portion2. The current flow or the resistance of the device can now be controlled by a typically negative gate voltage of the gate electrode61, which can be typically in the range from about −10V to about −30V. This is because the extension of the depletion region around the pn-junctions can be controlled by the gate voltage. Since the doping concentration of the p-dopant type regions p+(body regions3, gate regions6) is typically higher then the doping concentration of the channel region n, the depletion region has a larger extension in the channel region10. Higher negative gate voltages correspond to larger depletion regions and hence to higher resistances. At a high negative threshold gate voltage the device is switched off (off-state). Note, that in case of a p-channel JFET, in which the doping is reversed, a high positive gate-source voltage is required to switch off the device.

In one or more embodiments a plurality of cells is connected to a common front electrode51and a common back electrode81. In other words, the semiconductor device is a power JFET including the drift region21which includes the drift portion1and the structured current spread layer22. The structured current spread layer22includes regions of different doping concentrations: the current spread portion2having a doping concentration which is higher then the doping concentration of the drift portion1and of the first portions4. Further, the power JFET can be formed as vertical semiconductor device.

In the off-state, high electric field strength can occur at or close to certain pn-junctions of the semiconductor device. At sufficiently high voltages an electrical breakdown e.g., by an avalanche process can occur. This limits the switching ability of the semiconductor device. As can be seen in theFIGS. 6 to 9, the highest electric fields usually occur at or close to the edges and corners of pn-junctions and depend on their spatial curvature. In particular, close to the pn-junction between body region3and the drift portion1high electric field strength can be expected. The absolute value of the field strength at given voltage drop depends further on the distances e.g., between neighbouring body regions3and doping concentrations.FIGS. 6 to 9illustrate two-dimensional simulations of semiconductor devices, which do not include a current spread portion2or current spread layer2. Besides, the structure of the devices used for the simulations is substantially similar to the structure illustrated inFIGS. 5A and 5B. The different structure of the source region5and the front electrode51inFIGS. 6 and 7does not influence the simulation.

FIGS. 6 and 7correspond to vertical cross-sections through semiconductor devices. SinceFIGS. 6 and 7are two-dimensional simulation, the structures illustrated would mainly correspond to a stripe layout but is also a sufficiently good approximation of the electrical field distribution of comparable layouts. Compared toFIGS. 5A and 5Bonly the electric field distribution of the left half of the device is presented. In the off-state the highest absolute electric field strength is observed, in the vertical cross-section, below the corner of the body region3facing to a not illustrated neighbouring right body region3. The lateral distance of two neighbouring body regions3is about 2.4 times higher inFIG. 7compared toFIG. 6. This yields an about 7% higher maximum electric field strength in the device. Therefore, the breakdown voltage of the device decreases with increasing lateral distance between two body regions3. Consequently, if several body regions3are e.g., arranged on a lattice such as the square lattice illustrated inFIG. 1, the breakdown is expected to occur close to the body regions3and in areas between more than two neighbouring, i.e. four neighbouring body regions3in case of the square lattice. This is because the distance b (seeFIG. 1) between diagonally neighbouring body regions3is about 1.4 times higher (for square shaped body regions3orientated in parallel to the lattice as inFIG. 1) then between neighbouring body regions3in a lattice direction.

Taking into account typical corner rounding of the body regions3, the distance b between diagonally neighbouring body regions3is about 2.5 times higher compared to the distance a in a lattice direction (FIG. 1). If a current spread region2having a larger conductivity or doping concentration is provided additionally on the drift region1, the electric field distribution close to body regions3of such a device is more homogeneous if first portions4of a lower conductivity are arranged close to the critical regions. This is because the electric field strength will be lower in depleted regions of lower conductivity.

In addition, the electric field strength in the off-state is higher below the pn-junction of the gate region6if the spacing between the neighbouring body regions3is larger. This is illustrated quantitatively inFIG. 8. The curves11and12correspond to the electric field strength at the right border ofFIG. 7 and 8, respectively. The coordinate y gives the distance from the top surface (first surface30) in relative units. Clearly, close to the gate region6the electric field is higher in case of the larger spaced body regions3ofFIG. 7(curve11) than for less spaced body regions3(curve12) ofFIG. 6. The electrical field strength would be even more pronounced in case of a continuous current spread region.

Further, the electric field distribution close to the body regions3is influenced by the curvature of the pn-junctions. This is explained qualitatively inFIG. 9showing current-voltage characteristics of JFETs in the off-state. In doing so, the full lines13and14correspond to semiconductor devices as illustrated inFIG. 7 and 6, respectively, having straight pn-junctions between body regions3and spacer portions9, wherein line14illustrates the characteristic of a device having a larger lateral spacing between adjacent body regions. At moderate voltages, only comparatively small currents flow. Note that the current is plotted on a logarithmic scale. Above a certain threshold the current increases sharply with voltage, i.e. an avalanche breakdown occurs. As to be expected from the electric field distributions ofFIGS. 6 and 7, the breakdown voltage is lower for higher distances between neighbouring body regions3(FIG. 7).

The dashed lines15and16relate to similar simulations in cylinder symmetry. In other words, the body regions3are formed as thin cylinders and having thus, in projection on the first plane40, a round or curved contour. The distance between neighbouring body regions3is equal for the two curves13and15on the one hand and for the two curves14and16on the other hand. The full lines13and14correspond to a semiconductor device with body regions3running parallel to each other without any lateral curvature, e.g., arranged on a one-dimensional lattice. As can be appreciated from comparing the dashed and full lines, any deviation from the straight shape of the body regions3like a curvature will decrease the breakdown voltage. The decrease of breakdown voltage strongly depends on curvature and doping. It can amount up to a several 100 V in case of power semiconductor devices.

To improve the overall device performance, the critical regions of the body regions3near the corners or where the shape of the body region3is laterally curved can be defused in the off-state by a structured current spread layer22. In other words, the current spread layer22is not formed in areas where the body regions have a curved outer boundary. For this purpose first portion4having a lower doping concentration can be arranged on the drift portion1and close to the critical regions of high field strength.

It should be noted, that a higher doping concentration of the drift region21close to the body regions typically increases the field load in the off-state. Therefore, arranging a homogeneous current spread layer, which has a higher doping concentration than the drift portion1, between the drift portion1and the body regions3results typically in a decrease of the breakdown voltage. Using a structured current spread region or layer22, the increased field load is at least partially compensated in critical regions of high electric field strength by the first portions4. At the same time the on-state resistance can be reduced remarkably. Typically, the on-state resistance is reduced by up to a few 10 percent. Depending on the task of the device, the trade-off between breakdown voltage and on-state resistance can be adjusted e.g., by the doping concentration of the current spread portion2, the vertical thickness of the structured current spread region or layer22and the position and lateral shape, i.e. the outline in a plan view, of the first portions4.

The concept of a structured or composite current spread layer2can also be applied to other semiconductor devices such as IGBT's (insulated gate bipolar transistor) or MOSFET's, especially vertical power MOSFET's. In the latter case the structured current spread layer2can e.g., be used to reduce the resistance in forward bias and to protect critical regions close to pn-junctions in reversed bias that may occur during operation of the device.

An example of a MOSFET is illustrated inFIG. 5B. Different to the JFET illustrated inFIG. 5A, no channel region10is formed on the body regions3. In fact, a gate electrode100is arranged close to the body regions3to cause in inversion channel between the source regions5and the spacer portion9. The current spread region22can be structured as described above.

In case of an IGBT, an emitter region8of the first conductivity type (typically p+) would be formed instead of the drain region8at the second surface31. Back electrode81would than contact emitter region8.

In a further embodiment a method for producing a semiconductor device is provided. It includes the process of providing a semiconductor body20of a first conductivity type which has the first doping concentration. Further, a process of forming a current spread portion2of the second conductivity type and including the second doping concentration which is higher then the first doping concentration is included. It is carried out such that the current spread portion is arranged in the first plane40on a drift portion1of the drift region21, wherein the drift region21further includes first portions4of the first conductivity type, which have lower doping concentration than the current spread portion2and that are partially surrounded by the current spread portion2.

In one or more embodiments the method for producing a semiconductor device includes a process of forming source regions5of the first conductivity type on each of the body regions3.

Forming of the different semiconductor regions and portions can include deposing a semiconductor material such as the production of epitaxial layers on the semiconductor body20or substrate. Ion implantation can be used to form the different semiconductor regions and portions.

Typically, the structured current spread region22is formed after the formation the body and source regions.

In one or more embodiments the body regions3and the source regions5are formed in a self adjusting way by isotropic wet chemical etching of a first implantation mask. Typically, an oxide mask is used. Openings are formed in the first implantation mask to define the location of the source regions. After implanting an appropriate dopant in the semiconductor body to form the source regions5, the first implantation mask is isotropically etched to widen the mask openings. The etched first implantation mask can then be used for implanting the body regions3. In doing so, the body region3and source regions5are self adjusted to each other. In case of a mask with square openings for implantation of the source regions5, a mask including rounded squares is produced by the etching process. This can results in a semiconductor device as illustrated inFIG. 1.

The first mask can further be used to form alignment marks in the first semiconductor which are used for aligning subsequent lithographic masks.

The structured current spread region22can be formed by one ion implantation process using a second implantation mask, which covers the regions of the first portions4. Typically, a resist mask is used as second implantation mask. In this way the drift portion1and the first portions4are formed such that they have substantially the same doping concentration. The implantation is performed such that, in a vertical direction, the implantation region extends from below the body regions (including the current spread region) up to the surface of the semiconductor body. By doing so, the spacer portions9between parallel running body regions are also doped. Although dopant may be implanted into the body regions too, this does not significantly effect the doping concentration of the body regions since they have a higher doping concentration than the doping concentration of the current spread region.

The written description above uses specific embodiments to disclose the invention, including the best mode, and also to enable any person skilled in the art to make and use the invention. While the invention has been described in terms of various specific embodiments, those skilled in the art will recognise that the invention can be practiced with modification within the spirit and scope of the claims. Especially, mutually non-exclusive features of the embodiments described above may be combined with each other. The patentable scope is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.