Solid state imaging device and method of controlling solid state imaging device

Provided is a solid state imaging device including: a pixel array in which pixels are disposed on a matrix; an iris authenticator that extracts iris information to be used in an iris authentication process, from image data obtained from the pixel array through photoelectric conversion; and an imaging condition controller that performs control to set an imaging condition in obtaining the image data for the iris authentication process, by using information obtained in a process of extracting the iris information.

TECHNICAL FIELD

The present disclosure relates to solid state imaging devices and methods of controlling the solid state imaging devices.

BACKGROUND ART

Biometric authentication technologies of identifying individuals from bodily characteristics of people have been proposed. For example, the biometric authentication uses fingerprints, hand shapes, retinas, faces, voices, or the like. In addition, for example, PTL 1 proposes an iris authentication system that uses features of irises because irises of eyeballs of people are different between individuals.

CITATION LIST

Patent Literature

SUMMARY OF THE INVENTION

Problem to be Solved by the Invention

The iris authentication system captures an image of an eyeball of a person and acquires information of an iris of the eyeball from the captured image. However, to quickly perform the iris authentication, it is necessary to quickly set imaging conditions such as exposure and shutter speed that are appropriate for iris authentication.

Therefore, the present disclosure proposes novel and improved solid state imaging devices and control methods that make it possible to quickly set optimal imaging conditions for the iris authentication.

Means for Solving the Problem

According to the present disclosure, there is provided a solid state imaging device including: a pixel array in which pixels are disposed on a matrix; an iris authenticator that extracts iris information to be used in an iris authentication process, from image data obtained from the pixel array through photoelectric conversion; and an imaging condition controller that performs control to set an imaging condition in obtaining the image data for the iris authentication process, by using information obtained in a process of extracting the iris information.

In addition, according to the present disclosure, there is provided a solid state imaging device including: a first semiconductor substrate on which at least a pixel array is formed; and a second semiconductor substrate on which at least a logic circuit is formed, the second semiconductor substrate being joined to the first semiconductor substrate, the pixel array including pixels disposed on a matrix, the pixel array outputting image data, the logic circuit including an iris authenticator that extracts iris information from the image data, and an imaging condition controller that controls exposure or a focus on a basis of a result obtained by the iris authenticator.

In addition, according to the present disclosure, there is provided a method of controlling a solid state imaging device, the method including: extracting iris information to be used in an iris authentication process, from image data obtained from a pixel array through photoelectric conversion, the pixel array including pixels disposed on a matrix; and performing control to set an imaging condition in obtaining the image data for the iris authentication process, by using information obtained in a process of extracting the iris information.

Effects of the Invention

As described above, according to the present disclosure, it is possible to provide novel and improved solid state imaging devices and methods of controlling the solid state imaging devices that make it possible to quickly set optimal imaging conditions for the iris authentication.

Note that, the effects described above are not necessarily limited, and along with or instead of the effects, any effect that is described in the present specification or other effects that may be grasped from the present specification may be exhibited.

MODES FOR CARRYING OUT THE INVENTION

1. Configuration Example of Solid State Imaging Device

1.2. Functional Configuration

1.3. Circuit Configuration of Unit Pixel

1.4. Encryption Process

1.4.1. Configuration Example

1.4.2. Operation Example

1.5. Biometric Authentication Process

1.5.1. Comparative Example

1.5.2. Configuration Example

1.5.3. Operation Example

1.5.4. Application Example

1. Configuration Example of Solid State Imaging Device

A configuration example of a solid state imaging device according to the present embodiment will be described below.

FIG. 1illustrates a schematic configuration of a CMOS solid state imaging device as an example of a configuration of a solid state imaging device according to an embodiment of the present disclosure. The CMOS solid state imaging device is applied to solid state imaging devices of each embodiment. As illustrated inFIG. 1, a solid state imaging device1of this example includes a pixel array (so-called pixel region)3in which pixels2including a plurality of photoelectric conversion sections are regularly disposed in a two-dimensional array form on a semiconductor substrate11, for example, a silicon substrate, and a peripheral circuit section. The pixel2includes, for example, a photodiode serving as the photoelectric conversion section and a plurality of pixel transistors (so-called MOS transistors). The plurality of pixel transistors is able to include three transistors, for example, a transfer transistor, a reset transistor, and an amplification transistor. In addition, it is possible for the plurality of pixel transistors to include four transistors by adding a selection transistor thereto. Note that, an example of an equivalent circuit of a unit pixel will be described later. It is possible for the pixel2to be configured as one unit pixel. In addition, the pixel2is also able to have a shared pixel structure. The shared pixel structure is constituted by a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and each one of other shared pixel transistors. In other words, in the shared pixel, the photodiodes and the transfer transistors constituting a plurality of unit pixels are configured to share each one of other pixel transistors.

The peripheral circuit section includes a vertical driving circuit4, column signal processing circuits5, a horizontal driving circuit6, an output circuit7, a control circuit8, and the like.

The control circuit8receives input clocks and data for instructing on an operation mode and the like, and outputs data of internal information of the solid state imaging device and the like. In other words, the control circuit8generates clock signals and control signals which serve as a reference of operations of the vertical driving circuit4, the column signal processing circuit5, the horizontal driving circuit6, and the like, on the basis of vertical synchronization signals, horizontal synchronization signals, and master clocks. In addition, the control circuit8inputs these signals to the vertical driving circuit4, the column signal processing circuit5, the horizontal driving circuit6, and the like.

The vertical driving circuit4includes, for example, a shift register, selects a pixel driving wiring line, supplies a pulse for driving a pixel to the selected pixel driving wiring line, and drives pixels in units of rows. In other words, the vertical driving circuit4sequentially selects and scans each pixel2of the pixel array3in units of rows in a vertical direction, and supplies a pixel signal based on signal electric charges generated according to the amount of received light in, for example, the photodiode serving as the photoelectric conversion section of each pixel2to the column signal processing circuit5through a vertical signal line9.

The column signal processing circuit5is disposed for, for example, each column of the pixels2, and performs a signal process such as removing noise of signals output from pixels2in one row for each pixel column. In other words, the column signal processing circuit5performs a signal process such as a CDS for removing fixed pattern noise specific to the pixel2, signal amplification, AD conversion, or the like. In the output stage of the column signal processing circuit5, a horizontal selection switch (not illustrated in the drawings) is provided by being coupled to a horizontal signal line10.

The horizontal driving circuit6includes, for example a shift register, sequentially selects each of the column signal processing circuits5by sequentially outputting horizontal scanning pulses, and causes pixel signals to be outputted from each of the column signal processing circuits5to the horizontal signal line10.

The output circuit7performs a signal process on the signal sequentially supplied from each of the column signal processing circuits5through the horizontal signal line10, and outputs the processed signals. For example, sometimes only buffering is performed, or sometimes adjustment of black level, correction of column variation, various digital signal processing, or the like is performed. An input/output terminal12exchanges signals with an outside.

In addition,FIG. 2illustrates an overview of a configuration example of a multi-layer solid state imaging device to which a technology according to the present disclosure may be applied.

A ofFIG. 2illustrates a schematic configuration example of a single-layer solid state imaging device. As illustrated in A ofFIG. 2, a solid state imaging device23010includes a single die (semiconductor substrate)23011. Mounted on the die23011are a pixel region23012, a control circuit23013, and a logic circuit23014. In the pixel region23012, pixels are disposed in an array form. The control circuit23013performs various kinds of control including control of driving the pixels. The logic circuit23014performs a signal process.

B and C ofFIG. 2illustrate schematic configuration examples of multi-layer solid state imaging devices. As illustrated in B and C ofFIG. 2, two dies, namely a sensor die23021and a logic die23024, are stacked in a solid state imaging device23020. These dies are electrically coupled to form a single semiconductor chip.

With reference to B ofFIG. 2, the pixel region23012and the control circuit23013are mounted on the sensor die23021, and the logic circuit23014is mounted on the logic die23024. The logic circuit23014includes a signal processing circuit that processes signals.

With reference to C ofFIG. 2, the pixel region23012is mounted on the sensor die23021, and the control circuit23013and the logic circuit23014are mounted on the logic die23024.

FIG. 3is a cross-sectional view illustrating a first configuration example of the multi-layer solid state imaging device23020.

A photodiode (PD), a floating diffusion (FD), and a Tr (MOS FET) that constitute a pixel serving as the pixel region23012, and a Tr or the like serving as the control circuit23013are formed in the sensor die23021. In addition, a wiring layer23101including a plurality of layers, that is, in this example, three layers of wiring lines23110is formed in the sensor die23021. Note that, it is possible to form (the Tr serving as) the control circuit23013not in the sensor die23021but in the logic die23024.

A Tr constituting the logic circuit23014is formed in the logic die23024. In addition, a wiring layer23161including a plurality of layers, that is, in this example, three layers of wiring lines23170is formed in the logic die23024. In addition, a contact hole23171is formed in the logic die23024. An insulating film23172is formed on an inner wall of the contact hole23171. A connection conductor23173to be coupled to the wiring line23170and the like is embedded in the contact hole23171.

The sensor die23021and the logic die23024are bonded in a manner that the wiring layer23101of the sensor die23021and the wiring layer23161of the logic die23024face each other. This makes it possible to form the multi-layer solid state imaging device23020in which the sensor die23021and the logic die23024are stacked. A film23191such as a protective film is formed on a surface through which the sensor die23021and the logic die23024are bonded.

A contact hole23111is formed in the sensor die23021. The contact hole23111penetrates the sensor die23021from a back surface side (a side from which light is incident on the PD) (an upper side) of the sensor die23021and reaches the wiring line23170of an uppermost layer of the logic die23024. In addition, a contact hole23121is formed in the vicinity of the contact hole23111in the sensor die23021. The contact hole23121reaches the wiring line23110of a first layer from the back surface side of the sensor die23021. An insulating film23112is formed on an inner wall of the contact hole23111, and an insulating film23122is formed on an inner wall of the contact hole23121. In addition, connection conductors23113and23123are respectively embedded in the contact holes23111and23121. The connection conductor23113and the connection conductor23123are electrically coupled to each other on the back surface side of the sensor die23021. This makes it possible to electrically couple the sensor die23021and the logic die23024via the wiring layer23101, the contact hole23121, the contact hole23111, and the wiring layer23161.

FIG. 4is a cross-sectional view illustrating a second configuration example of the multi-layer solid state imaging device23020.

According to the second configuration example of the solid state imaging device23020, ((the wiring line23110) of the wiring layer23101of) the sensor die23021and ((the wiring line23170) of the wiring layer23161of) the logic die23024are electrically coupled via one contact hole23211formed in the sensor die23021.

In other words, with reference toFIG. 4, the contact hole23211is formed to penetrate the sensor die23021from the back surface side of the sensor die23021to reach the wiring line23170of the uppermost layer of the logic die23024and reach the wiring line23110of the uppermost layer of the sensor die23021. An insulating film23212is formed on an inner wall of the contact hole23211, and a connection conductor23213is embedded in the contact hole23211. With reference toFIG. 3described above, the sensor die23021and the logic die23024are electrically coupled via the two contact holes23111and23121. However, with reference toFIG. 4, the sensor die23021and the logic die23024are electrically coupled via the one contact hole23211.

FIG. 5is a cross-sectional view illustrating a third configuration example of the multi-layer solid state imaging device23020.

The solid state imaging device23020illustrated inFIG. 5in which the film23191such as the protective film is not formed on a surface through which the sensor die23021and the logic die23024are bonded is different from the solid state imaging device23020illustrated inFIG. 3in which the film23191such as the protective film is formed on the surface through which the sensor die23021and the logic die23024are bonded.

The solid state imaging device23020illustrated inFIG. 5is configured by stacking the sensor die23021and the logic die23024together in a manner that the wiring line23110and the wiring line23170directly contact each other, heating them while subjecting them to necessary weight bearing, and directly joining the wiring line23110and the wiring line23170.

FIG. 6is a cross-sectional view illustrating another configuration example of the multi-layer solid state imaging device to which a technology according to the present disclosure may be applied.

With reference toFIG. 6, a solid state imaging device23401has a three-layer stacked structure in which three dies are stacked. The three dies are a sensor die23411, a logic die23412, and a memory die23413.

For example, the memory die23413includes a memory circuit that stores data which is temporarily necessary for a signal process performed by the logic die23412.

With reference toFIG. 6, the logic die23412and the memory die23413are stacked in this order under the sensor die23411. However, the logic die23412and the memory die23413may be stacked in the opposite order. In other words, the memory die23413and the logic die23412may be stacked in this order under the sensor die23411.

Note that, with reference toFIG. 6, a PD serving as the photoelectric conversion section of a pixel and source/drain regions of the pixel transistors Tr are formed in the sensor die23411.

A gate electrode is formed via a gate insulating film around the PD, and a pixel Tr23421and a pixel Tr23422are formed by the gate electrode and the pair of source/drain regions.

The pixel Tr23421adjacent to the PD is a transfer Tr, and one of the pair of source/drain regions constituting the pixel Tr23421is FD.

In addition, an interlayer insulating film is formed in the sensor die23411, and contact holes are formed in the interlayer insulating film. In the contact holes, connection conductors23431are formed. The connection conductors23431are coupled to the pixel Tr23421and the pixel Tr23422.

In addition, a wiring layer23433including a plurality of layers of wiring lines23432to be coupled to the connection conductors23431is formed in the sensor die23411.

In addition, an aluminum pad23434serving as an electrode for external coupling is formed in a lowermost layer of the wiring layer23433in the sensor die23411. In other words, in the sensor die23411, the aluminum pad23434is formed at a position closer to a bonding surface23440with the logic die23412than the wiring line23432is. The aluminum pad23434is used as one end of a wiring line related to input and output of signals to/from an outside.

In addition, a contact23441is formed in the sensor die23411. The contact23441is used for electrical coupling to the logic die23412. The contact23441is coupled to a contact23451of the logic die23412, and is also coupled to an aluminum pad23442of the sensor die23411.

In addition, a pad hole23443is formed in the sensor die23411. The pad hole23443reaches the aluminum pad23442from the back surface side (the upper side) of the sensor die23411.

The technology according to the present disclosure is applicable to the above-described solid state imaging devices.

Note that, in the examples described with reference toFIG. 3toFIG. 6, for example, copper (Cu) wiring lines are used as the various kinds of wiring lines. In addition, hereinafter, as illustrated inFIG. 5, a configuration of directly joining the wiring lines (for example, the wiring line23110and the wiring line23170illustrated inFIG. 5) of the sensor dies stacked on each other is also referred to as “Cu—Cu bonding”.

1.2. Functional Configuration

Next, with reference toFIG. 7, an example of a functional configuration of the solid state imaging device according to the embodiment of the present disclosure will be described.FIG. 7is a block diagram illustrating an example of a functional configuration of a portion of the solid state imaging device according to the embodiment of the present disclosure. The solid state imaging device1inFIG. 7is an image sensor such as, for example, a complementary metal oxide semiconductor (CMOS) image sensor and a charge coupled device (CCD) image sensor, which captures an image of a subject and obtains digital data of the captured image.

As illustrated inFIG. 7, the solid state imaging device1includes a controller101, a pixel array section111, a selector112, an A/D converter (ADC (analog digital converter))113, and a constant current circuit section114.

The controller101controls each structural element of the solid state imaging device1and causes the structural element to perform a process related to readout of image data (pixel signal) and the like.

The pixel array section111is a pixel region in which pixel structures including photoelectric conversion elements such as photodiodes are disposed in a matrix (array) form. The pixel array section111is controlled by the controller101, receives light of a subject at each pixel, performs photoelectric conversion of the incident light to accumulate electric charges, and outputs the electric charges accumulated in each pixel as a pixel signal at a predetermined timing.

A pixel121and a pixel122represent two pixels adjacent to each other in an up-down direction in a pixel group disposed in the pixel array section111. The pixel121and the pixel122are pixels in successive rows in a same column. In a case of the example inFIG. 7, as represented by the pixel121and the pixel122, a photoelectric conversion element and four transistors are used in a circuit of each pixel. Note that, the configuration of the circuit of each pixel is optional, and it is possible to use a configuration other than the example illustrated inFIG. 7.

In a general pixel array, an output line of the pixel signal is provided for each column. In a case of the pixel array section111, two (two-path) output lines are provided for each column. The circuits of pixels in one column are alternately coupled to the two output lines every other row. For example, a circuit of a pixel in an odd-numbered row from the top is coupled to one output line and a circuit of a pixel in an even-numbered row is coupled to the other output line. In the case of the example inFIG. 7, the circuit of the pixel121is coupled to a first output line (VSL1) and the circuit of the pixel122is coupled to a second output line (VSL2).

Note that, inFIG. 7, for convenience of description, only the output lines for one column are illustrated. However, in practice, two output lines are provided to each column in a similar manner. The circuits of the pixels in the column are coupled to each output line every other row.

The selector112includes switches that couples each output line of the pixel array section111to inputs of the ADC113. The selector112is controlled by the controller101and controls coupling between the pixel array section111and the ADC113. In other words, the pixel signals read from the pixel array section111are supplied to the ADC113through the selector112.

The selector112includes a switch131, a switch132, and a switch133. The switch131(selection SW) controls coupling of two output lines corresponding to a same column. For example, when the switch131becomes ON state, the first output line (VSL1) and the second output line (VSL2) are coupled. When the switch131becomes OFF state, the first output line (VSL1) and the second output line (VSL2) are decoupled.

Although the details are described later, in the solid state imaging device1, one ADC (column ADC) is provided to each output line. Therefore, if both the switches132and133are in ON state, when the switch131becomes ON state, two output lines of the same column are coupled, and the circuit of one pixel is coupled to two ADCs. On the other hand, when the switch131becomes OFF state, two output lines of the same column are decoupled, and the circuit of one pixel is coupled to one ADC. In other words, the switch131selects the number of ADCs (column ADCs) to which a signal of one pixel is to be outputted.

Although details are described later, the switch131thus controls the number of ADCs to which the pixel signal is to be outputted, which enables the solid state imaging device1to output more various pixel signals in accordance with the number of ADCs. In other words, the solid state imaging device1is able to implement more various data outputs.

The switch132controls coupling between the first output line (VSL1) corresponding to the pixel121and the ADC corresponding to the output line. When the switch132becomes ON state, the first output line is coupled to one input of a comparator of the corresponding ADC. When the switch132becomes OFF state, these are decoupled.

The switch133controls coupling between the second output line (VSL2) corresponding to the pixel122and the ADC corresponding to the output line. When the switch133becomes ON state, the second output line is coupled to one input of a comparator of the corresponding ADC. When the switch133becomes OFF state, these are decoupled.

The selector112is able to control the number of ADCs (column ADCs) to which the signal of one pixel is to be outputted, by switching the states of the switch131to the switch133under the control of the controller101.

Note that, it is possible to omit the switch132and/or the switch133(either one or both of them) and couple each output line and the ADC corresponding to the output line at all times. Note that, enabling these coupling/decoupling to be controlled by these switches makes it possible to have a wide selection range of the number of ADCs (column ADCs) to which the signal of one pixel is to be outputted. In other words, it is possible for the solid state imaging device1to output more various pixel signals by installing these switches.

Note that, inFIG. 7, only the structural elements corresponding to the output lines for one column are illustrated. However, in practice, the selector112has a similar configuration to that illustrated inFIG. 7(switches131to133) for each column. In other words, the selector112performs similar coupling control to that described above under the control of the controller101for each column.

The ADC113performs A/D-conversion of the pixel signals supplied from the pixel array section111via the respective output lines and outputs the pixel signals as digital data. The ADC113includes the ADC (column ADC) for each output line from the pixel array section111. In other words, the ADC113includes a plurality of column ADCs. The column ADC corresponding to one output line is a single-slope ADC including a comparator, a D/A converter (DAC), and a counter.

The comparator compares its DAC output and a signal value of the pixel signal. The counter increments a count value (digital value) until the pixel signal and the DAC output become equal. The comparator stops the counter when the DAC output reaches the signal value. Thereafter, signals digitalized by counters1and2are outputted to the outside of the solid state imaging device1from DATA1and DATA2.

The counters return the count value to an initial value (for example, 0) after outputting data for next A/D conversion.

The ADC113includes two-path column ADCs for each column. For example, a comparator141(COMP1), a DAC142(DAC1), and a counter143(counter1) are provided for the first output line (VSL1), and a comparator151(COMP2), a DAC152(DAC2), and a counter153(counter2) are provided for the second output line (VSL2). Although not illustrated in the drawings, the ADC113has a similar configuration for the output lines of the other columns.

However, of these structural elements, it is possible to share the DAC. The DAC is shared for each path. In other words, the DAC of the same path of each column is shared. In the case of the example inFIG. 7, the DAC corresponding to the first output line (VSL1) of each column is shared as the DAC142and the DAC corresponding to the second output line (VSL2) of each column is shared as the DAC152. Note that, the comparator and the counter are provided for each path of output lines.

The constant current circuit section114is a constant current circuit coupled to each output line and driven under the control of the controller101. The circuit of the constant current circuit section114includes, for example, a metal oxide semiconductor (MOS) transistor or the like. Although the configuration of the circuit is optional, inFIG. 7, for convenience of description, a MOS transistor161(LOAD1) is provided for the first output line (VSL1) and a MOS transistor162(LOAD2) is provided for the second output line (VSL2).

The controller101selects a readout mode by receiving a request from an outside such as, for example, a user, controls the selector112, and controls coupling of the output lines. Further, the controller101controls drive of the column ADCs in accordance with the selected readout mode. Further, the controller101controls drive of the constant current circuit section114and controls drive of the pixel array section111such as, for example, a rate and timing of the readout, as needed in addition to the drive of the column ADCs.

In other words, the controller101is able to not only control the selector112but also cause respective structural elements other than the selector112to operate in more various modes. Therefore, the solid state imaging device1is able to output more various pixel signals.

Note that, the number of structural elements illustrated inFIG. 7is optional unless it is insufficient. For example, three or more paths of output lines may be provided for each column. In addition, it is possible to increase the number of pixel signals outputted in parallel to the outside by increasing the number of pixel signals outputted in parallel from the ADC132or the number of ADCs132themselves inFIG. 7.

With reference toFIG. 7, the example of the functional configuration of the solid state imaging device according to the embodiment of the present disclosure has been described above.

1.3. Circuit Configuration of Unit Pixel

Next, with reference toFIG. 8, an example of a circuit configuration of a unit pixel will be described.FIG. 8illustrates an example of the circuit configuration of the unit pixel according to an embodiment of the present disclosure. As illustrated inFIG. 8, a unit pixel121according to the embodiment of the present disclosure includes a photoelectric conversion section such as a photodiode (PD) and four pixel transistors. The four pixel transistors include, for example, a transfer transistor Tr11, a reset transistor Tr12, an amplification transistor Tr13, and a selection transistor Tr14. Such pixel transistors include, for example, an n-channel MOS transistor.

The transfer transistor Tr11is coupled between a cathode of the photodiode PD and a floating diffusion section FD. Signal charges (in this case, electrons) accumulated here through photoelectric conversion in the photodiode PD are transferred to the floating diffusion section FD by applying a transfer pulse φTRG to the gate. Note that, a reference sign Cfd schematically represents parasitic capacitance of the floating diffusion section FD.

In the reset transistor Tr12, a drain is coupled to a power source VDD, and a source is coupled to the floating diffusion section FD. In addition, before transferring the signal charge from the photodiode PD to the floating diffusion section FD, an electric potential of the floating diffusion section FD is reset by applying a reset pulse φRST to the gate.

In the amplification transistor Tr13, a gate is coupled to a floating diffusion section FD, a drain is coupled to the power source VDD, and a source is coupled to a drain of the selection transistor Tr14. The amplification transistor Tr13outputs an electric potential of the floating diffusion section FD to the selection transistor Tr14as a reset level after being reset by the reset transistor Tr12. Furthermore, the amplification transistor Tr13outputs an electric potential of the floating diffusion section FD as a signal level to the selection transistor Tr14after the signal charge is transferred by the transfer transistor Tr11.

In the selection transistor Tr14, for example, a drain is coupled to the source of the amplification transistor Tr13, and a source is coupled to a vertical signal line9. In addition, the selection transistor Tr14is turned on by applying a selection pulse φSEL to the gate, and outputs a signal outputted from the amplification transistor Tr13to the vertical signal line9. Note that, the selection transistor Tr14may be configured to be coupled between the power source VDD and the drain of the amplification transistor Tr13.

Note that, in a case where the solid state imaging device1according to the present embodiment is configured as the multi-layer solid state imaging device, for example, elements such as the plurality of MOS transistors, the photodiode, and the like are formed in the sensor die23021illustrated in B or C ofFIG. 2. In addition, the transfer pulse, the reset pulse, the selection pulse, and the power source voltage are supplied from the logic die23024illustrated in B or C ofFIG. 2. In addition, the elements disposed in a rear stage from the vertical signal line9coupled to the drain of the selection transistor, the elements disposed in a rear stage from the vertical signal line9coupled to the drain of the selection transistor are included in the logic circuit23014and formed in the logic die23024.

With reference toFIG. 8, the example of the circuit configuration of the unit pixel has been described above.

1.4. Encryption Process

Next, a solid state image sensor that internally completes an encryption process will be described. There has been technologies of generating an encryption key in an imaging device on the basis of unique information that is specific to a solid state image sensor. However, there is a possibility that the unique information used for the encryption will be leaked if the unique information is outputted from the solid state image sensor and encryption is performed by a functional block different from the solid state image sensor.

Therefore, the solid state imaging device1according to the present embodiment internally completes an encryption process using unique information without outputting the unique information to the outside.

1.4.1. Configuration Example

FIG. 9is an explanatory diagram illustrating a functional configuration example of a solid state image sensor according to a first embodiment of the present disclosure.FIG. 9illustrates a functional configuration example of the solid state imaging device1that internally completes the encryption process using unique information. Next, with reference toFIG. 9, the functional configuration example of the solid state image sensor according to the first embodiment of the present disclosure will be described.

As illustrated inFIG. 9, the solid state imaging device1according to the first embodiment of the present disclosure includes a drive controller210, a pixel array section211, a clip circuit215, a reference signal generator216, a current source217, a detector218, a unique value calculator220, an encryptor222, and a communication controller224. The pixel array section211includes an imager212and a unique information generator214, and includes predetermined rows and columns.

The drive controller210generates a signal for driving the imager212and the unique information generator214(to be described later) on the basis of a predetermined input clock and data, and drives the imager212and the unique information generator214. The drive controller210may include, for example, the control circuit8, the vertical driving circuit4, and the horizontal driving circuit6included in the solid state imaging device1described with reference toFIG. 1. In addition, the drive controller210may be installed in the control circuit23013illustrated inFIG. 2.

The drive controller210may have a function of switching between driving of the imager212and driving of the unique information generator214when driving the pixel array section211. The drive controller210having the function of switching between driving of the imager212and driving of the unique information generator214makes it possible to share circuits of the imager212and the unique information generator214. In addition, because the drive controller210has the function of switching between driving of the imager212and driving of the unique information generator214, a special element for generating the unique information is not necessary, and this makes it difficult to analyze a unique value.

In addition, it is also possible for the drive controller210to have a function of separating an element to be driven to output an image from an element to be driven to detect element-specific information in the pixel array section211. The drive controller210having the function of separating the element to be driven to output an image from the element to be driven to detect element-specific information prevents leakage of the element-specific information.

In addition, in driving to detect the element-specific information, it is also possible for the drive controller210to perform control for driving by using bias current different from current used for driving to output an image. It is possible to perform driving appropriately for stable acquisition of a unique value when the drive controller210performs control for driving to detect the element-specific information by using bias current different from current used for driving to output an image. Specifically, for example, driving of the MOS transistor161(LOAD1) and the MOS transistor162(LOAD2) in the circuit illustrated inFIG. 7is differentiated, between the time of driving for detecting the element-specific information and the time of driving for outputting an image. By changing driving of the MOS transistor161(LOAD1) and the MOS transistor162(LOAD2), it is possible to change characteristics of an amplification transistor AMP. By the drive controller210performing control for driving to detect the element-specific information by using bias current corresponding to a temperature, it is possible to perform driving appropriately for more stable acquisition of a unique value.

It is also possible for the drive controller210to perform control for driving by using bias current corresponding to a chip temperature of the solid state imaging device1in driving to detect the element-specific information by using bias current different from current used for driving to output an image.

In the pixel array section211, unit pixels including predetermined rows and columns are arrayed. The pixel array section211is configured to output data by using a source follower circuit.

The imager212includes a pixel array in which pixels including a plurality of photoelectric conversion sections are arrayed in a two-dimensional array form. The imager212is driven by the drive controller210and outputs an analog signal. A circuit configuration of each pixel in the imager212is the circuit configuration illustrated inFIG. 8, for example.

In the unique information generator214, circuits having the same configuration as the pixel installed in, for example, the imager212are unidimensionally arrayed. The unique information generator214is driven by the drive controller210and outputs an analog signal. The circuit formed as the unique information generator214may be created through a production process that is substantially same as a production process of the pixel installed in the imager212. In addition, the drive controller210may switch between driving of the imager212and driving of the unique information generator214.

The unique information generator214may be a pixel installed in an optical black (OPB) region in the pixel array. Respective elements in the circuit configured as the unique information generator214have physical production variations. The solid state imaging device1according to the first embodiment of the present disclosure uses an analog signal outputted from the unique information generator214as a basis of uncopiable unique information (element-specific information).

An example of a generation source of the analog signal outputted from the unique information generator214will be described. Next, the description will be given on the assumption that the unique information generator214has a similar configuration to the pixel121illustrated inFIG. 7orFIG. 8.

The photodiode PD includes a noise component caused by crystal defects that occur through production. The crystal defects cause variations of dark current. The crystal defects appear as fixed pattern noise.

A selection transistor SEL includes a noise component caused by variation of threshold voltage Vth. The variation of the threshold voltage Vth is caused by its structure such as an oxide film, a channel width, a channel length, or impurities. The variation of the threshold voltage Vth appears as fixed pattern noise.

A reset transistor RST also includes a noise component caused by variation of threshold voltage Vth. The variation of the threshold voltage Vth is caused by its structure such as an oxide film, a channel width, a channel length, or impurities. The variation of the threshold voltage Vth appears as fixed pattern noise.

The floating diffusion section FD includes a noise component caused by crystal defects that occur through production. The crystal defects cause variations of dark current. The crystal defects appear as fixed pattern noise. When the reset transistor RST is switched from ON to OFF, kTC noise (reset noise) appears in the floating diffusion section FD. The kTC noise occurs temporarily. When the reset transistor RST is switched from ON to OFF, feedthrough appears in the floating diffusion section FD. The feedthrough is caused by variation of parasitic capacitance or a threshold value, and the feedthrough appears as fixed pattern noise.

The amplification transistor AMP also includes a noise component caused by variation of threshold voltage Vth. The variation of the threshold voltage Vth is caused by its structure such as an oxide film, a channel width, a channel length, or impurities. The variation of the threshold voltage Vth appears as fixed pattern noise. In addition, the amplification transistor AMP also includes a noise component caused by overdrive voltage, a noise component caused by thermal noise, a noise component caused by 1/f noise, and a noise component caused by random telegraph noise (RTN). It is considered that the RTN is caused by electric charge trapping/detrapping due to defects in an oxide film. Whether or not the oxide film includes a defect is unique variation. However, what is observed is binary or multivalued temporal signal level fluctuation.

Such a noise component is transmitted to the detector218in a rear stage via a signal line (VSL). In normal driving, among such noise components, a noise component that is not changed between before and after transfer of the signal is removed through a CDS process. In the present embodiment, when generating a unique value, the solid state imaging device1does not remove such a noise component, but uses such a noise component as element-specific information serving as a basis of the unique value. It is possible for the solid state imaging device1to generate a unique value that is less easily analyzed, because the noise component included in the analog signal outputted from the unique information generator214is used as the basis of the unique value.

The unique information generator214may be installed at a position (light shielded position) out of reach of light from the outside, for example. It is possible for the solid state imaging device1to stably generate the unique information without being affected by outside light because the unique information generator214is installed at a light shielded position. In addition, it is also possible for the unique information generator214to include one or a plurality of rows of circuits. The number of the circuits is the same as the number of columns of the pixel array of the imager212. In addition, the unique information generator214may include a row selection switch to be operated by a control signal from the drive controller210.

The clip circuit215is a circuit that is arrayed in n-number of columns. The n-number is the same as the number of columns of the pixel array section211. The clip circuit215is a source follower circuit coupled to a source follower circuit of the pixel array section211in parallel. The clip circuit215has a clip function that allows voltage (VSL voltage) of an output line for each column to fall within a predetermined range.

FIG. 10Ais an explanatory diagram illustrating a circuit configuration example of the clip circuit215. The clip circuit215is a source follower circuit that is able to select a row. The source follower circuit is coupled to output lines VSL in parallel with the pixels. The clip circuit215includes transistors CLPSEL and CLPAMP corresponding to respective output lines VSL. The transistor CLPSEL is a transistor that operates linearly, and performs control to couple a source of the transistor CLPAMP to the output line VSL. The control is performed by a clip selection pulse. The transistor CLPAMP is a transistor that operates in a saturation state. In a way similar to the amplification transistor AMP of the pixel, the transistor CLPAMP outputs a signal corresponding to input when the current source applies bias current. Input is provided by clip voltage. In general, the input is an intermediate electric potential of about 1 V to about 2 V.

In a selected state, the bias current is preferentially applied to the clip circuit215when output voltage of a source follower (pixels in a selected row) coupled to the output line VSL becomes lower than voltage outputted depending on clip voltage. As a result, the source follower output of the pixels of the selected row does not function, and voltage of the output line VSL is clipped to an output level corresponding to the clip voltage. With regard to the clip voltage, DC voltage common to unit clip circuits for respective columns is supplied. At this time, in a way similar to the pixel source follower, a threshold value or overdrive voltage varies individually.

The reference signal generator216averages VSL voltages outputted by the clip circuit215for respective columns and outputs the averaged voltage. The current source217is a circuit for applying constant current and outputting VSL voltage, and is driven by a current control voltage generator219. The current sources217are arrayed in n number of columns, and forms the amplification transistor and the source follower circuit in the unit pixel. The current control voltage generator219generates current control voltage by using a band-gap reference circuit in a manner that current values of the current sources217do not depend on a temperature.

The detector218performs a signal process for converting an analog signal outputted from the unique information generator214into a digital signal. The detector218includes a comparator231, a DA converter232, and a counter233. The comparator231compares VSL voltage outputted from the current source217with a reference waveform outputted from the DA converter232, and converts the voltage into time. The comparator231includes an input capacitance installed at an input side and a switch that shorts input and output of the comparator231. The DA converter232generates a reference waveform to be supplied to the comparator231. The counter233has a function of counting until output of the comparator231is inverted, and converting time into the number of counts.

The detector218outputs the digital signal obtained through the conversion to the unique value calculator220. In addition to the function of converting an analog signal into a digital signal, the detector218may have a function of performing a differencing process on two input signals, and a function of removing variation that has occurred by the detector218itself. Because the detector218has the function of removing variation that has occurred by the detector218itself, excessive variation does not occur in a signal from the unique information generator214. This makes it possible to improve quality of a signal serving as a basis of a unique value. In addition, it is also possible for the detector218to perform a column parallelism process on an analog signal outputted from the unique information generator214, or perform a pixel parallelism process.

The detector218may include a capacitance that clamps an electric potential of a signal line and a switch for setting an end of the capacitance to a reference electric potential. Specifically, the detector218may include a switch that couples ends of capacitive elements installed on input sides of the comparators141and151in the ADC113illustrated inFIG. 7, to output sides of the comparators141and151. Because the switch couples the ends of the capacitive elements to the output sides of the comparators141and151, a diode-coupled transistor is generated among transistors included in the comparators141and151. This makes it possible to set the end of the capacitance that clamps the electric potential of the signal line to a predetermined reference electric potential. Therefore, it is possible to remove the variation in an analog region. In addition, it is possible for the detector218to perform a differencing process on a digital value after the AD conversion. Through the differencing process of the digital value after the AD conversion, it is possible for the detector218to remove variation in a digital region.

In addition, the detector218may have a function of shifting a level of clamp as described later. By shifting the level of clamp, it is possible for the detector218to optimize distribution of analog values around a predetermined reference when converting an analog value to a digital value. By optimizing the distribution of analog values, it is possible to losslessly obtain unique information outputted from the unique information generator214.

In a case where a plurality of the detectors218is arrayed, each of the detectors218may have a function of getting a difference between a signal inputted to each of the detector218and a reference signal that is common to the plurality of detectors218. In this case, the reference signal common to the plurality of detectors218may be substantially the same as an average of the signals inputted to the respective detectors218.

Memory for temporarily holding unique information outputted from the unique information generator214, especially, analog memory may be interposed between the unique information generator214and the detector218. The analog memory may be parasitic capacitance of the signal line as described later. In addition, in a case where the analog memory is interposed between the unique information generator214and each of the plurality of detectors218, it is possible to provide a switch that shorts the analog memories. It becomes easy to generate the unique information, and because the analog memories are shorted and averaged, the unique information held by each analog memory is deleted.

FIG. 10Bis an explanatory diagram illustrating a circuit configuration example of the reference signal generator216, the current source217, and the comparator231.FIG. 10Billustrates an (n−1)-th output line VSL(n−1), an n-th output line VSL(n), and an (n+1)-th output line VSL(n+1).

On the output line VSL(n−1), switches251aand252aare provided as the reference signal generator216. In addition, parasitic capacitance253ais provided on the output line VSL(n−1). On the output line VSL(n), switches251band252bare provided as the reference signal generator216. In addition, parasitic capacitance253bis provided on the output line VSL(n). On the output line VSL(n+1), switches251cand252care provided as the reference signal generator216. In addition, parasitic capacitance253cis provided on the output line VSL(n+1).

As the current source217, a transistor261ais coupled to an end of the switch252a, a transistor261bis coupled to an end of the switch252b, and a transistor261cis coupled to an end of the switch252c.

On the output line VSL(n−1), input capacitances271aand272a, switches273aand274a, and a comparator275aare provided as the comparator231. On the output line VSL(n), input capacitances271band272b, switches273band274b, and a comparator275bare provided as the comparator231. On the output line VSL(n+1), input capacitances271cand272c, switches273cand274c, and a comparator275care provided as the comparator231.

FIG. 11is an explanatory diagram illustrating a timing chart of operations of the reference signal generator216, the current source217, and the comparator231for generating unique information. Next, operations of respective elements provided on or along the output line VSL(n−1) will be described. Note that, the operations performed by the reference signal generator216, the current source217, and the comparator231to generate the unique information are not limited to the operations illustrated inFIG. 11.

At a time t1, a horizontal readout period starts. At this time, a row selection signal φSEL becomes high, and row selection starts. At this time, the reset transistor RST is in the ON state. Therefore, voltage of the floating diffusion section FD is fixed to VDD. This makes it possible to remove variation of the floating diffusion section FD. In addition, a transfer pulse φTRG is fixed to a low state when generating unique information. The transfer pulse φTRG fixed to the low state makes it possible to turn off the transfer transistor TRG, and this makes it possible to remove variation of the photodiodes PD.

In addition, at the time t1, a current source separation pulse for separating the current source217is high, and the switch252ais in the ON state. In addition, at the time t1, a VSL averaging pulse for averaging VSL voltage is low, and the switch251ais in the OFF state. This makes it possible to output variation information for each source follower to the output lines VSL even during source follower operation.

At a time t2, the row selection signal (selection pulse) φSEL and the current source separation pulse become low at the same time, and the parasitic capacitance253aof VSL holds VSL voltages of respective columns. In addition, at the time t2, a VSL averaging pulse becomes high, and the VSL voltages of the respective columns are averaged. The averaged VSL voltage is a reference signal.

At a time t3, the input capacitance272ais charged by an internal offset of the comparator275aand a difference between VSL voltage and a reference waveform, and an operating point of the comparator275ais initialized.

At a time t4, a shorting pulse becomes low, and the switches273aand274aare turned off. Accordingly, the kTC noise and feedthrough variation occur in the switches273aand274a.

A period between a time t5and a time t6is a first AD conversion period (ADC period1). In this period, the DA converter232linearly changes the reference waveform at a predetermined gradient. Next, the comparator275aperforms AD conversion on the reference signal by using the reference waveform. The DA converter232may have a function of shifting the reference waveform. In other words, the DA converter232may have a function of shifting a clamp level. By shifting the reference waveform, it is possible for the DA converter232to provide an offset to the output of the counter233. In the ADC period1, inverting delay of the comparator275a, delay of the reference waveform, and clock delay of the counter occur. Note that, inFIG. 11, a triangle indicates an inversion timing of the comparator275a.

When the ADC period1ends at the time t6, the row selection signal φSEL becomes high, and the current source separation pulse becomes high, and the VSL averaging pulse becomes low. In other words, the switch251ais turned off, and the switch252ais turned on. This makes it possible to output variation information for each source follower (variation of output of the amplification transistor) to the output lines VSL even during source follower operation.

A period between a time t7and a time t8is a second AD conversion period (ADC period2). Also in this period, the DA converter232linearly changes the reference waveform at a predetermined gradient. Next, the comparator275aperforms AD conversion on the reference signal by using the reference waveform. Here, in a similar way, a digital value obtained after conversion includes kTC noise and feedthrough variation that occurred in the switches273aand274aat the time t4, and includes inverting delay of the comparator275a, delay of the reference waveform, and clock delay of the counter that occurred in the ADC period1. Note that, inFIG. 11, a triangle indicates an inversion timing of the comparator275a.

Then, when the ADC period2ends, a differencing process of a count value of the counter233obtained in the ADC period1and a count value of the counter233obtained in the ADC period2is performed. The differencing process makes it possible to remove variation that has occurred in the detector218. Therefore, it is possible to prevent element-specific information from including variation that has occurred in the detector218.

In addition, in the ADC period1, because the output of the counter233is provided with the offset, the variation caused by the unique information generator214is not lost even if the above-described differencing process is performed. The variations caused by the unique information generator214are normally distributed around the reference signal. Therefore, if there is no offset, a negative value appears in the variations caused by the unique information generator214, and all the values equal to or less than 0 are treated as 0.

At the time of AD conversion, it is desirable to adjust the gradient of the reference waveform (analog gain adjustment) to obtain a desired digital value. In addition, to read out the element-specific information, it is possible to make a current (drain current Id) of the current source smaller than a current used for usual readout. The overdrive voltage is able to be calculated by 2×Id/gm. However, the variations are also proportional to the overdrive voltage. Therefore, when the drain current Id gets smaller, a variation component of the overdrive voltage included in the source follower relatively decreases. In other words, it is possible to mainly detect information of variations of a threshold value of the amplification transistor AMP. In addition, to read out the element-specific information, it is possible to make a current (drain current Id) of the current source larger than a current used for usual readout. By making the current of the current source larger, it is also possible to make the variation component of the overdrive voltage relatively larger among variation information included in the source follower.

Thermal noise of the amplification transistor AMP, 1/f noise, RTN, and thermal noise of peripheral circuits are included as temporal noise. However, it is possible to suppress them by performing readout more than once and doing addition (averaging).

To suppress time degradation, it is desirable for the solid state imaging device1to control driving under the following conditions. Small current is desirable at the time of operation in view of hot carrier injection. In other words, it is desirable to perform control in a manner that the bias current gets smaller. In a similar way, short operation time is desirable in view of hot carrier injection. For example, it is desirable to perform control for driving only at a time of activation or when requested. In addition, in a similar way, it is desirable to apply no current while being unused in view of hot carrier injection. In other words, it is desirable to turn off the selection transistor SEL while being unused. In addition, in view of a breakdown of an oxide film, it is desirable to reduce voltage difference between a gate and a source or a drain of a target element while being unused. In other words, it is desirable to turn on the reset transistor RST while being unused. In addition, in view of substrate hot carrier injection, it is desirable to block light incident on the unique information generator214.

A high-level electric potential of the selection pulse φSEL may be substantially VDD (2.7 V). Alternatively, the high-level electric potential of the selection pulse φSEL may be an intermediate electric potential (about 1 V to about 1.5 V). The source follower is obtained by using an electric potential difference (VDS) between the drain and the source of the selection transistor SEL and operating in a saturation state. For example, assuming that the drain voltage of the selection transistor SEL is 2.7 V, in general, a drain side of the selection transistor SEL (source side of the amplification transistor AMP) has about 2.2 V. On the other hand, it is possible to operate in the saturation state by using a sufficient VDS of the selection transistor SEL (at least a difference of about several hundreds to about 700 mV). This makes it possible to transmit output corresponding to the gate voltage of the selection transistor SEL to the output line VSL. In a way similar to the amplification transistor AMP, threshold values and overdrive voltage of the selection transistor SEL vary between respective elements when operating in the saturated state. Therefore, it is possible to detect the variation of the threshold value and the overdrive voltage of the selection transistor SEL. In this case, the selection switches are turned off with regard to the clip circuit215and the pixels in non-selected rows. Therefore, they are not involved in the readout.

The unique value calculator220calculates a value (unique value) specific to the solid state imaging device1on the basis of the digital signal sent from the detector218. The unique value calculator220generates a value having a predetermined bit length as the unique value. An example of a method for calculating the unique value of the solid state imaging device1by the unique value calculator220will be described later. When the unique value of the solid state imaging device1is calculated, the unique value calculator220sends the unique value to the encryptor222. The unique value generated by the unique value calculator220may be used as a key itself or a seed to be used in the encryption process performed by the encryptor222.

Among a plurality of pieces of element-specific information, the unique value calculator220may select which piece of element-specific information to use. When selecting a piece of element-specific information, the unique value calculator220may select which piece of element-specific information to use through computation based on the element-specific information, or may select which piece of element-specific information to use by using a random number. In addition, non-volatile memory may store a selection condition for selecting a piece of element-specific information. The selection condition may be written into the non-volatile memory only once. Examples of a timing of writing the selection condition into the non-volatile memory include an inspection timing, a shipment timing, a first usage timing, and the like. The unique value calculator220is able to repeatedly calculate unique values by using element-specific information based on any production variation that occurs in a chip of the solid state imaging device1, including element-specific information having relatively small amount of information. In other words, it is possible to increase amount of information of the element-specific information.

Alternatively, it is also possible for the unique value calculator220to calculate a unique value by combining a plurality of pieces of element-specific information among pieces of element-specific information generated by the unique information generator214. It becomes difficult to analyze how the unique value has been calculated, by calculating the unique value by combining the plurality of pieces of element-specific information.

In addition, it is also possible for memory to temporarily store the unique value generated by the unique value calculator220. Because the memory stores the unique value generated by the unique value calculator220, a calculation timing of the unique value becomes less likely to be analyzed. In other words, instead of generating the unique value at an encryption request timing, the solid state imaging device1may use a unique value that has been generated in advance, in response to an encryption request. The solid state imaging device1may calculate a unique value after a predetermined period of time has elapsed since driving performed at a time of usual image capturing, for example. In addition, the solid state imaging device1may generate the unique value not at the encryption request timing but at a timing at which a unique value generation request is received.

In addition, the unique value calculator220may average unique values obtained under a same driving condition. By averaging the unique values obtained under the same driving condition, it is possible to suppress noise in a temporal direction.

The encryptor222performs an encryption process of data by using the unique value generated by the unique value calculator220. The encryptor222may be provided in the logic circuit23014illustrated inFIG. 2, for example. Specifically, the encryptor222performs the encryption process of data by using the unique value generated by the unique value calculator220as the seed or the key itself. Examples of a target of the encryption include the unique value itself, image information, a feature amount based on the image information, and the like. It is possible for the solid state imaging device1to very securely encrypt data by performing the encryption process using the unique value generated by the unique value calculator220.

The communication controller224transmits the data to an outside of the solid state imaging device1. The communication controller224may perform different processes in a case of outputting the imaging data and in a case of outputting data encrypted by the encryptor222.

Among the structural elements of the solid state imaging device1illustrated inFIG. 9, at least paths for processing unique information are formed to be hidden from the surface of the solid state imaging device1. For example, the paths for processing unique information are disposed to be covered with metal in an upper layer including an uppermost layer. The paths for processing unique information may be covered with a predetermined shield layer, or may be covered with a wiring line of VSS or VDD. Examples of the paths for processing unique information may include the unique information generator214, the detector218, the unique value calculator220, and the encryptor222. In addition, the solid state imaging device1is formed in a manner that a pad for monitoring unique information is not provided in the paths for processing unique information. Because the solid state imaging device1is formed as described above, it is possible to prevent leakage of the unique information of the solid state imaging device1to the outside, the unique information being used for the encryption process. In addition, if someone tries to analyze the unique information, he/she has to destroy the solid state imaging device1. As a result, it is not possible to analyze the unique information. In addition, the solid state imaging device1according to the present embodiment does not hold the unique information therein. The solid state imaging device1generates unique information in each case, and performs the encryption process using a unique value based on the generated unique information. Therefore, the solid state imaging device1according to the present embodiment is able to perform a very secure encryption process.

The solid state imaging device1according to the present embodiment does not hold unique information therein. Therefore, it is not possible to decrypt the encrypted data if the unique value changes each time the unique value is generated on the basis of the unique information. Therefore, it is necessary for the unique value to be the same value no matter when the unique value is calculated. Therefore, it is also possible for the solid state imaging device1according to the present embodiment to have a function of correcting a unique value calculated by the unique value calculator220on the basis of a signal outputted from the unique information generator214in accordance with a temperature of a chip in which the unique information generator214is installed. In addition, it is also possible for the solid state imaging device1according to the present embodiment to have a function of detecting the temperature of the chip in which the unique information generator214is installed.

FIG. 12is an explanatory diagram illustrating another functional configuration example of the solid state imaging device1according to the present embodiment.FIG. 12illustrates a configuration including a chip temperature detector226and a signal corrector228in addition to the structural elements of the solid state imaging device1illustrated inFIG. 9.

The chip temperature detector226detects a temperature of a chip in which the unique information generator214is installed. The chip temperature detector226sends information of the detected temperature of the chip to the signal corrector228. The signal corrector228corrects a unique value calculated by the unique value calculator220on the basis of the temperature of the chip in which the unique information generator214is installed. The temperature has been detected by the chip temperature detector226. The signal corrector228may hold a table in which correction values corresponding to temperatures are stored, and may decide a correction value on the basis of the temperature detected by the chip temperature detector226.

1.4.2. Operation Example

Next, an operation example of the solid state imaging device according to the present embodiment will be described.FIG. 13is a flowchart illustrating an operation example of the solid state imaging device according to the present embodiment.FIG. 13illustrates an example of operation performed when the solid state imaging device1calculates a unique value and performs the encryption process by using the unique value.

First, the solid state imaging device1generates analog unique information that is a basis of a unique value (Step S201). The analog unique information is generated by the drive controller210driving the unique information generator214.

After the analog unique information is generated, the solid state imaging device1subsequently converts the analog unique information into a digital value (Step S202). The detector218converts the analog unique information into the digital value. The detector218performs the process of converting the analog unique information into the digital value as described above.

After the analog unique information is converted into the digital value, the solid state imaging device1subsequently calculates a unique value of the solid state imaging device1by using the digital value obtained after the conversion (Step S203). The unique value calculator220calculates the unique value of the solid state imaging device1.

After the unique value of the solid state imaging device1is calculated, the solid state imaging device1subsequently performs an encryption process of data by using the unique value (Step S204). The encryptor222performs the encryption process of the data by using the unique value.

By performing the series of operations described above, it is possible for the solid state imaging device1according to the present embodiment to internally complete the encryption process by using unique information without outputting the unique information to the outside. The solid state imaging device1according to the present embodiment performs the encryption process by using the unique information that is not leaked to the outside. This makes it possible to output important information that has been encrypted in a highly secure way.

1.5. Biometric Authentication Process

Next, a biometric authentication process using the solid state imaging device1according to the present embodiment and control of the solid state imaging device1will be described. Before details of the biometric authentication process using the solid state imaging device1according to the present embodiment and control of the solid state imaging device1will be described, a comparative example will be described first for understanding of the present embodiment.

1.5.1. Comparative Example

FIG. 14is an explanatory diagram illustrating the comparative example of the present embodiment.FIG. 14illustrates an information processing apparatus1000including a lens module1001, a solid state imaging device1002, and an application processor1003. The solid state imaging device1002converts light passed through the lens module1001into an electrical signal. The application processor1003performs an image process using the electrical signal outputted from the solid state imaging device1002, especially, a biometric authentication process. The biometric authentication process includes a living body detection process of determining whether or not a captured image includes a living body, an iris authentication process of recognizing an iris of a person and determining whether the recognized iris matches iris information registered in advance, and the like. The description will be given on the assumption that the information processing apparatus1000performs the iris authentication process as the biometric authentication process.

The application processor1003includes an iris authenticator1010, an iris information storage1020, and an imaging condition controller1030. The iris authenticator1010uses the electrical signal outputted from the solid state imaging device1002. The iris information storage1020stores iris information of an authentication target in advance. The imaging condition controller1030controls imaging conditions such as a focus and exposure to improve accuracy of the iris authentication process performed by the iris authenticator1010. In addition, the iris authenticator1010includes a region detector1011, an iris extractor1012, and an iris matching section1013. The region detector1011detects a region of an eye of a person, especially, a region of an eyeball from an electrical signal outputted from the solid state imaging device1002. The iris extractor1012extracts iris information of the person from the region of the eye of the person detected by the region detector1011. The iris matching section1013checks the iris information extracted by the iris extractor1012against the iris information stored in the iris information storage1020. For example, Inter-Integrated Circuit (I2C) communication may be used as communication from the application processor1003to the lens module1001and the solid state imaging device1002.

To improve the accuracy of the iris authentication process performed by the iris authenticator1010, it is necessary to accurately extract iris information from the electrical signal outputted from the solid state imaging device1002. In a case where the region detector1011has not detected a position of an eye of a person or in a case where the iris extractor1012has not extracted iris information, the imaging condition controller1030performs control to focus on the eye, lengthen exposure time, or improve gain at a time of capturing an image. At this time, if the control is performed to set appropriate exposure for a target by averaging luminance in the whole region of electrical signals outputted from, for example, the solid state imaging device1002as an evaluation value, there is a possibility that the appropriate exposure is not applied to the iris itself because it depends on factors such as a color of skin, presence/absence of glasses, eyelashes, use or nonuse of makeup, other than the iris. Therefore, the imaging condition controller1030is able to focus on a region of an eyeball by using information of the region of the eyeball of the person detected by the region detector1011, and is able to set exposure for acquiring iris information by performing control to set appropriate exposure for a target by averaging luminance of only the iris region as an evaluation value.

However, as illustrated inFIG. 14, it takes time before completion of control for preparing the imaging conditions appropriate for the iris authentication process in a case where the application processor1003controls the imaging conditions of the lens module1001and the solid state imaging device1002. One reason for this is that a communication speed between the solid state imaging device1002and the application processor1003and communication traffic of the electrical signals from the solid state imaging device1002to the application processor1003are limited.

Therefore, in the present embodiment, control is performed to prepare appropriate imaging conditions for the iris authentication process in the solid state imaging device1. It is possible to shorten time it takes to complete control to prepare the appropriate imaging conditions for the iris authentication process, by performing the control to prepare appropriate imaging conditions for the iris authentication process in the solid state imaging device1.

1.5.2. Configuration Example

FIG. 15is an explanatory diagram illustrating a configuration example of an information processing apparatus300including the solid state imaging device1according to the present embodiment. Next, the configuration example of the information processing apparatus300according to the present embodiment will be described with reference toFIG. 15.

The information processing apparatus300according to the present embodiment is an apparatus that authenticates a person by using iris information of the person. The information processing apparatus300may be a mobile terminal such as a smartphone or a tablet terminal, for example, an authentication apparatus included in an immigration system installed in an airport or the like, or an unlocking apparatus for unlocking a door or a steering wheel of a vehicle. As illustrated inFIG. 15, the information processing apparatus300according to the present embodiment includes the lens module1001and the solid state imaging device1that converts light passed through the lens module1001into an electrical signal.

The solid state imaging device1includes an imaging controller301, an iris authenticator310, an iris information storage320, an imaging condition controller330, an application processor370, and a display380.

The imaging controller301controls respective structural elements of the solid state imaging device1and causes them to perform processes related to readout of image data (pixel signal) and the like. The imaging controller301controls time (that is, exposure time or shutter speed) it takes to read out an electrical signal from pixels (for example, the pixel array3illustrated inFIG. 1). The electrical signal is obtained through conversion of light passed through the lens module1001. Note that, the imaging condition controller330performs control related to automatic exposure (AE) for automatically obtaining exposure corresponding to brightness of a subject. Information of exposure time decided by the imaging condition controller330is reflected in the imaging controller301. In addition, to focus on the subject, the imaging condition controller330also controls driving (AF) of an actuator (not illustrated) that drives lenses included in the lens module1001. Information related to positions of the lenses decided by the imaging condition controller330is reflected in the lens module1001.

The iris authenticator310performs an iris authentication process using image data generated by the solid state imaging device1. The iris authenticator310includes a region detector311, an iris extractor312, and an iris matching section313. The region detector311detects a region of an eye of a person, especially, a region of an eyeball from the image data. The iris extractor312extracts iris information of the person from the region of the eye of the person detected by the region detector311. The iris matching section313checks the iris information extracted by the iris extractor312against the iris information stored in advance in the iris information storage320.

The region detector311detects a region of an eye of the person, especially, a region of an iris or a pupil of an eyeball from the image data generated by the solid state imaging device1. The region detector311detects the region of the eyeball through pattern matching or the like, for example.

The iris extractor312extracts iris information of the person from the region of the eye of the person detected by the region detector311. The iris extractor312extracts the iris information through a filter process such as a Gabor filter, for example. The iris matching section313checks the iris information extracted by the iris extractor312against the iris information stored in advance in the iris information storage320.

The information processing apparatus300according to the present embodiment is able to complete the iris authentication process in the solid state imaging device1. Therefore, although it is possible for the iris authenticator310to output the image data to the application processor370in a rear stage, the iris authenticator310may output only a result of the iris authentication to the application processor370. By outputting only the result of the iris authentication to the application processor370, it is possible for the information processing apparatus300according to the present embodiment to perform the iris authentication process without leaking the image data including images of faces of people to the outside of the solid state imaging device1.

The imaging condition controller330controls imaging conditions such as a focus and exposure by using information obtained through the iris authentication process performed by the iris authenticator310. For example, if the eyeball is not focused on when the region detector311detects a region of an eyeball from image data, the imaging condition controller330receives information from the region detector311, the information indicating that the eyeball is not focused on. Next, the imaging condition controller330instructs the lens module1001to drive an actuator (not illustrated) that drives lenses (not illustrated) included in the lens module1001in a manner that the eyeball is focused on. In addition, for example, in a case where it is not possible to extract the iris information because of overexposure or lack of exposure when the iris extractor312extracts the iris information, the imaging condition controller330receives information indicating overexposure or underexposure from the iris extractor312. Next, the imaging condition controller330instructs the imaging controller301to perform control to slow the shutter speed to lengthen the exposure time, or increase gain to obtain exposure sufficient to extract the iris information.

To extract the iris information, the iris extractor312uses the Gabor filter, for example. In addition, it is possible to recognize whether the eyeball is focused on, from a magnitude of an absolute value of an output value of the filter. It is possible for the iris extractor312to determine that the eyeball is not focused on if the absolute value of the output value of the filter is small. Therefore, it is possible for the imaging condition controller330to acquire information of the absolute value of the output value of the Gabor filter from the iris extractor312. The imaging condition controller330instructs the lens module1001to drive the actuator (not illustrated) that drives the lenses (not illustrated) included in the lens module1001in a manner that a large output value of the Gabor filter is obtained, that is, in a manner that the eyeball is focused on.

The information processing apparatus300according to the present embodiment completes the control related to the focus and exposure in the solid state imaging device1. This enables control by an interruption or data access by using internal memory of the solid state imaging device1. In addition, the information processing apparatus300according to the present embodiment is able to avoid delay in communication between chips such as I2C. As described above, by completing the control related to the focus and exposure in the solid state imaging device1, it is possible for the information processing apparatus300according to the present embodiment to shorten time it takes to complete the control to prepare the appropriate imaging conditions for the iris authentication process, in comparison with the above-described comparative example. In addition, the information processing apparatus300according to the present embodiment is able to improve accuracy of the iris authentication process by capturing an image under the appropriate imaging conditions for the iris authentication process.

It is also possible for the information processing apparatus300according to the present embodiment to display a guide on the display380when performing the iris authentication process. The guide is for alignment of the eyes of a person to be authenticated.FIG. 16is an explanatory diagram illustrating an example of a screen displayed on the display380of the information processing apparatus300.FIG. 16illustrates the display380, the lens module1001, and a light source390that emits light to a subject. For example, the application processor370causes the display380to display guides381for the alignment of the eyes. The person to be authenticated moves his/her face or the information processing apparatus300in a manner that the both eyes are included in the guides381. Because the display380displays the guides381as described above, the solid state imaging device1only has to detect a region of an eyeball and perform a process of extracting an iris only with regard to the regions of the guides381when performing the iris authentication process.

In preparation for the iris authentication process, the person to be authenticated has to register iris information in advance. Needless to say, the information processing apparatus300according to the present embodiment is also usable for registration of the iris information. Also in a case of registering the iris information, it is possible for the information processing apparatus300according to the present embodiment to set the imaging conditions in the solid state imaging device1to obtain exposure and a focus that are suitable for extraction of the iris information.

The iris authentication process has been described above as the example of the biometric authentication process. However, the present disclosure is not limited thereto. Next, an example of an information processing apparatus including a solid state imaging device for performing a living body detection process as the biometric authentication process will be described. In the living body detection process, it is determined whether or not what is captured in an image is a living body, in other words, an actual human being, a person wearing a mask, a doll, or a photograph.

FIG. 17is an explanatory diagram illustrating a configuration example of the information processing apparatus300including the solid state imaging device1according to the present embodiment. Next, the configuration example of the information processing apparatus300according to the present embodiment will be described with reference toFIG. 17.

The information processing apparatus300according to the present embodiment is an apparatus that performs biometric authentication by using image data. The information processing apparatus300may be a mobile terminal such as a smartphone or a tablet terminal, for example, an authentication apparatus included in an immigration system installed in an airport, or the like. As illustrated inFIG. 17, the information processing apparatus300according to the present embodiment includes the lens module1001and the solid state imaging device1that converts light passed through the lens module1001into an electrical signal.

The solid state imaging device1includes the imaging controller301, a living body detector340, the imaging condition controller330, the application processor370, and the display380. Here, the living body detector340will be described, the living body detector340being a structural element different from the information processing apparatus300illustrated inFIG. 15.

The living body detector340performs a living body detection process using image data generated by the solid state imaging device1. Here, the living body detection process performed by the living body detector340will be described.

For example, the living body detector340analyzes a Purkinje image by using the image data generated by the solid state imaging device1. The Purkinje image is a corneal reflection image obtained when light from a light source is reflected on a cornea. The Purkinje image appears in the eye as long as the eye is an eye of a living person. The living body detector340performs the living body detection process by using luminance information or a positional relation of the Purkinje image. In a case where the living body detection process is performed by using the luminance information or the positional relation of the Purkinje image, it is desirable to control AE to obtain luminance that allows easy detection of the Purkinje image, or shorten the shutter speed to suppress a blur. Therefore, the imaging condition controller330instructs the imaging controller301to use exposure that allows easy detection of the Purkinje image when the living body detector340analyzes the Purkinje image in the image data.

For example, the living body detector340analyzes whether or not pupillary hippus has occurred by using the image data generated by the solid state imaging device1. The pupillary hippus is repetition of slight contraction and dilatation of a pupil that occurs in an eye of a living person even in a case where ambient brightness is constant. The living body detector340uses information of temporal change in a radius ratio of the pupil to the iris to detect the pupillary hippus. Therefore, in a case where the living body detection process is performed by detecting the pupillary hippus, it is desirable to control AE to obtain luminance that allows easy detection of circumferences of the pupil and the iris, or shorten the shutter speed to suppress a blur. Therefore, the imaging condition controller330instructs the imaging controller301to use exposure that allows easy detection of the circumferences of the pupil and the iris when the living body detector340analyzes whether or not pupillary hippus has occurred from the image data.

For example, the living body detector340analyzes whether or not a saccade has occurred by using the image data generated by the solid state imaging device1. The saccade is a quick movement of the eyeball. The living body detector340is able to analyze whether or not the saccade has occurred depending on whether a movement of a center of the eyeball, for example, a pupil has drastically changed. In other words, it is possible to determine that an eye is an eye of a living person as long as a saccade is detected. Therefore, in a case where the living body detection process is performed by detecting the saccade, it is desirable to control AE to obtain luminance that allows easy detection of the center of the pupil, or shorten the shutter speed to suppress a blur. Therefore, the imaging condition controller330instructs the imaging controller301to use exposure that allows easy detection of the center of the pupil when the living body detector340analyzes whether or not a saccade has occurred from the image data.

For example, the living body detector340analyzes whether or not a blinking has occurred by using the image data generated by the solid state imaging device1. In other words, it is possible to determine that an eye is an eye of a living person as long as a blinking is detected. The living body detector340is able to analyze whether or not blinking has occurred by detecting temporal change in the number of pixels of an edge point of an eyelid or a pupil. Therefore, in a case where the living body detection process is performed by detecting the blinking, it is desirable to control AE to obtain luminance that allows easy detection of the edge of the eyelid or the pupil, or shorten the shutter speed to suppress a blur. Therefore, the imaging condition controller330instructs the imaging controller301to use exposure that allows easy detection of the edge of the eyelid or the pupil when the living body detector340analyzes whether or not blinking has occurred from the image data.

For example, the living body detector340performs eye tracking by using the image data generated by the solid state imaging device1. When performing the eye tracking, the living body detector340uses a positional relation between an inner corner of an eye or a Purkinje image and a pupil. For example, the information processing apparatus300instructs a person to be subjected to living body detection to move his/her gaze, and determines whether or not the person is a living person by detecting whether the person has moved his/her gaze. In a case where the living body detection process is performed through the eye tracking, it is desirable to control AE to obtain luminance that allows easy detection of the Purkinje image or the pupil, or shorten the shutter speed to suppress a blur. Therefore, the imaging condition controller330instructs the imaging controller301to use exposure that allows easy detection of the Purkinje image or the pupil when the living body detector340performs the eye tracking by using the image data.

For example, the living body detector340analyzes unevenness of a face by using the image data generated by the solid state imaging device1. When detecting the unevenness of the face, the living body detector340captures images while changing focus. For example, a method of measuring a three-dimensional shape by a method called a shape-from-focus/defocus method has been known. The living body detector340detects the unevenness of the face in the image data by using such a method. In a case of detecting the unevenness of the face, it is desirable to control the focus to capture the unevenness of the face in a short time. Therefore, when the living body detector340detects the unevenness of the face from the image data, the imaging condition controller330instructs the lens module1001to control its focus to capture the unevenness of the face in a short time.

The living body detector340determines whether a subject included in image data is a living body by using one of the living body detection processes described above or by combining two or more living body detection processes described above. In a case of determining whether the subject is a living body by combining two or more living body detection processes described above, it is also possible for the living body detector340to parallelly perform determination processes that use similar imaging conditions. For example, in a case where the living body detector340determines whether the subject is a living body from pupillary hippus and a saccade, it is possible to parallelly perform a living body detection process using the pupillary hippus and a living body detection process using the saccade if it is possible to accurately detect centers or positions of pupils under the same imaging conditions.

The information processing apparatus300according to the present embodiment completes the control related to the focus and exposure in the solid state imaging device1. This enables control by an interruption or data access by using internal memory of the solid state imaging device1. In addition, the information processing apparatus300according to the present embodiment is able to avoid delay in communication between chips such as I2C. As described above, by completing the control related to the focus and exposure in the solid state imaging device1, it is possible for the information processing apparatus300according to the present embodiment to shorten time it takes to complete the control to prepare the appropriate imaging conditions for the living body detection processes, in a way similar to the above-described iris authentication process. In addition, the information processing apparatus300according to the present embodiment is able to improve accuracy of the living body detection process by capturing an image under the appropriate imaging conditions for the living body detection process.

It is also possible for the information processing apparatus300according to the present embodiment to perform both the iris authentication process and the living body detection process. By sequentially performing the iris authentication process and the living body detection process, it is possible for the information processing apparatus300to determine whether a subject is a living body and whether iris information of the living body is identical to pre-registered information. The information processing apparatus300may perform the iris authentication process and the living body detection process in this order, or may perform the living body detection process and the iris authentication process in this order. Because it takes time to perform the matching process of checking against the pre-registered information in the iris authentication process, it is possible for the information processing apparatus300to shorten the process time in a case where the subject is not a living body, by performing the living body detection process first, and then canceling the iris authentication process if the subject is not a living body.

FIG. 18is an explanatory diagram illustrating a configuration example of the information processing apparatus300according to the present embodiment.FIG. 18illustrates an example in which the information processing apparatus300is configured to perform both the living body detection process and the iris authentication process. Note that, the application processor370and the display380are omitted inFIG. 18.

The solid state imaging device1included in the information processing apparatus300illustrated inFIG. 18includes both the iris authenticator310described with reference toFIG. 15and the living body detector340described with reference toFIG. 17. As described above, of course, it is possible for the solid state imaging device1to perform both the living body detection process and the iris authentication process.

The solid state imaging device1may perform the living body detection process and the iris authentication process on an image of a same frame, or may perform the living body detection process and the iris authentication process on images of different frames. To improve security strength, it is desirable for the solid state imaging device1to perform the living body detection process and the iris authentication process on images of, for example, successive frames or images of frames obtained at a short time interval in a case of performing the living body detection process and the iris authentication process on images of different frames. In addition, the solid state imaging device1may perform the living body detection process and the iris authentication process under the same imaging conditions. Alternatively, the solid state imaging device1may perform the living body detection process and the iris authentication process under different imaging conditions because optimal image data is not necessarily obtained in the living body detection process and the iris authentication process under the same imaging conditions.

In a case of the iris authentication process, a near-infrared image is captured by using a visible light cut filter that blocks visible light, an infrared LED that emits infrared light, and the like. On the other hand, when a normal image is captured, an image of visible light is captured by using an IR cut filter that blocks infrared light. Therefore, in a case where a smartphone or the like performs the iris authentication process, the smartphone often includes two solid state imaging devices, which are a solid state imaging device for capturing normal images and a solid state imaging device for capturing images for the iris authentication process, to capture both the normal images and the images for the iris authentication process.

On the other hand, there are technologies of capturing both normal images and near-infrared images by using a single solid state imaging device. Specifically, such technologies include a technology of mechanically switching between a visible light cut filter and an IR filter to capture both normal images and near-infrared images, and a technology of including both normal RGB pixels for capturing an image of a visible light region and pixels using color filters that transmit a near-infrared region, to form a pixel array that captures both normal images and near-infrared images. In addition, such technologies also include a technology of applying voltage to an organic thin film and changing a sensitive wavelength range. Therefore, as described above, it is possible for the solid state imaging device to operate in both an optimal control mode for the iris authentication process and an optimal control mode for capturing normal images as long as the solid state imaging device is the solid state imaging device that is able to capture both normal images and near-infrared images.

FIG. 19is an explanatory diagram illustrating a configuration example of the information processing apparatus300including the solid state imaging device1according to the present embodiment.FIG. 19illustrates the configuration example of the information processing apparatus300including the solid state imaging device1that is able to operate in both the optimal control mode for the iris authentication process and the optimal control mode for capturing normal images. Next, the configuration example of the information processing apparatus300according to the present embodiment will be described with reference toFIG. 19.

As illustrated inFIG. 19, the information processing apparatus300according to the present embodiment includes the lens module1001and the solid state imaging device1that converts light passed through the lens module1001into an electrical signal.

The solid state imaging device1includes the imaging controller301, the iris authenticator310, the iris information storage320, the imaging condition controller330, and an analyzer350. Here, the analyzer350that is not included in the solid state imaging device1illustrated inFIG. 15will be described.

The analyzer350analyzes image data obtained by the solid state imaging device1when a normal image is captured. Specifically, the analyzer350measures luminance and contrast of the image data obtained by the solid state imaging device1. Next, the analyzer350sends an analysis result of the image data to the imaging condition controller330. The imaging condition controller330uses the analysis result sent from the analyzer350and performs control to cause the lens module1001to drive the actuator and to adjust a shutter speed, gain, and the like of the imaging controller301to obtain appropriate exposure.

As described above, it is possible to quickly set imaging conditions appropriate in a case of capturing a normal image and imaging conditions appropriate in a case of performing the iris authentication process, by image data obtained by the solid state imaging device1being analyzed by the solid state imaging device1that is able to operate in both the optimal control mode for the iris authentication process and the optimal control mode for capturing normal images.

The example in which the iris authentication process is performed in the solid state imaging device1has been described above. However, it is also possible to perform extraction of iris information and processes before extraction of iris information in the solid state imaging device1, and perform the matching process of checking the extracted iris information against pre-registered iris information in the application processor in a rear stage or in a server coupled via a network. Examples of cases suitable for the matching process performed outside the solid state imaging device1include a case where a data size of feature amount extracted by combining facial recognition and the like is large, a case where a large amount of calculation is necessary for a matching process because of an algorithm, a case of a system that searches for corresponding information in a database that stores large amounts of data, and the like. In a case where the matching process of checking against the extracted iris information against pre-registered iris information is performed in the application processor in the rear stage or in the server coupled via the network, there is a possibility that the iris information is leaked if the solid state imaging device1outputs the iris information as it is.

Here, as described above, the solid state imaging device1is able to perform the encryption process by using information generated therein as a key. Therefore, in a case where the matching process is performed outside the solid state imaging device1, it is possible for the solid state imaging device1to safely exchange the iris information by outputting encrypted iris information.

FIG. 20is an explanatory diagram illustrating a configuration example of an iris authentication system.FIG. 20illustrates the iris authentication system in which the information processing apparatus300and a server800are coupled via a network900. The information processing apparatus300performs the extraction of iris information and the processes before the extraction of iris information. The server800performs the matching process of the iris information. The solid state imaging device1illustrated inFIG. 20includes the imaging controller301, an iris processor302, an encryption processor315, and the imaging condition controller330. The iris processor302includes the region detector311and the iris extractor312. In other words, the iris processor302performs the extraction of iris information and the processes before the extraction of iris information.

The encryption processor315performs an encryption process on iris information outputted from the iris processor302. The encryption processor315performs the encryption process by using unique information specific to the solid state imaging device1as described above. It is possible for the encryption processor315to very securely exchange information with an outside by performing the encryption process using unique information specific to the solid state imaging device1.

The server800includes a decryption processor810, an iris matching section820, and an iris information storage830.

The decryption processor810decrypts iris information encrypted by the encryption processor315. The server800previously acquires unique information specific to the solid state imaging device1from the information processing apparatus300through any method. The decryption processor810decrypts the encrypted iris information by using the unique information acquired from the information processing apparatus300.

In a way similar to the above-described iris matching section313, the iris matching section820checks the iris information acquired from the information processing apparatus300against the iris information stored in advance in the iris information storage830.

As described above, even in a case where the information processing apparatus300transmits iris information to the server800and the server800performs the iris authentication process, it is possible to control the focus and exposure in the solid state imaging device1by using information obtained through the process of extracting iris information in the solid state imaging device1.

Here, a specific circuit configuration example of the above-described solid state imaging device1will be described.FIG. 21is an explanatory diagram illustrating a configuration example of a circuit formed in the logic die23024included in the solid state imaging device1according to the present embodiment.

The logic die23024includes a communication section23201, a CPU23202, ROM23203, RAM23204, an image processor23205, and the above-described imaging controller301. In addition, the logic die23024includes a secure region23300. The communication section23201communicates with another element, e.g., the application processor, via I2C communication, for example. In addition, pixel data is sent from, for example, a pixel region23102to the image processor23205, for example.

Of course, needless to say, the circuit configuration example illustrated inFIG. 21is for illustrative purposes. It is possible for the logic die23024included in the solid state imaging device1to have various kinds of layouts.

1.5.3. Operation Example

Next, an operation example of the solid state imaging device1according to the embodiment of the present disclosure will be described. Hereinafter, an operation example of the solid state imaging device1will be described. In the operation example, the solid state imaging device1first operates in a living body detection mode and then operates in an iris authentication mode when identifying an individual by using image data obtained through image capturing. In the living body detection mode, the living body detection process is performed. In the iris authentication mode, the iris authentication process is performed in a case where the living body is detected through the living body detection process.

FIG. 22is a flowchart illustrating an operation example of the solid state imaging device1according to the present embodiment.FIG. 22illustrates an operation example of the solid state imaging device1operating in the living body detection mode.

When the solid state imaging device1operates in the living body detection mode, the solid state imaging device1first controls image capturing appropriately for living body detection by using image data that has been obtained. In other words, the solid state imaging device1sets exposure, gain, and the like appropriately for living body detection (Step S301).

If image capturing is controlled appropriately for living body detection and imaging conditions appropriate for the living body detection are obtained (YES in Step S302), the solid state imaging device1performs the living body detection process by using the image data that has been obtained, and determines whether a subject is a living body (Step S303). If the subject in the image is the living body as a result of the living body detection (YES in Step S303), the solid state imaging device1subsequently shifts to the iris authentication mode. On the other hand, if the subject in the image is not the living body as a result of the living body detection (NO in Step S303), the solid state imaging device1waits for time-out (Step S304). In a case where the time-out occurs (YES in Step S304), the solid state imaging device1determines that the individual identification through the living body detection has failed, and ends the process (Step S305). Note that, if the imaging conditions are not appropriate for the living body detection as a result of the determination in Step S302(NO in Step S302), the solid state imaging device1waits for the time-out (Step S306). In a case where the time-out occurs (YES in Step S306), the solid state imaging device1determines that the individual identification through the living body detection has failed, and ends the process (Step S305).

Here, in the time-out process in Steps S304and S306, it is possible to install a timer in the solid state imaging device1and end the living body detection process when the process is interrupted by the timer that has finished counting a predetermined time-out period, or it is possible to install the timer in the application processor370and end the living body detection process when the timer finishes counting the predetermined time-out period and the application processor370notifies the solid state imaging device1of the time-out.

FIG. 23is a flowchart illustrating an operation example of the solid state imaging device1according to the present embodiment.FIG. 23illustrates an operation example of the solid state imaging device1operating in the iris authentication mode.

When the solid state imaging device1operates in the iris authentication mode, the solid state imaging device1first controls image capturing appropriately for the iris authentication by using image data that has been obtained. In other words, the solid state imaging device1sets exposure, gain, and the like appropriately for the iris authentication (Step S311).

If image capturing is controlled appropriately for the iris authentication and imaging conditions appropriate for the iris authentication are obtained (YES in Step S312), the solid state imaging device1performs the iris authentication process by using the image data that has been obtained, and determines whether iris information of a subject is identical to the pre-registered iris information (Step S313). If the iris information of the subject is identical to the pre-registered iris information as a result of the iris authentication (YES in Step S313), the solid state imaging device1recognizes the subject as the person to be authenticated, and ends the process (Step S314). On the other hand, if the iris information of the subject is not identical to the pre-registered iris information as a result of the iris authentication (NO in Step S313), the solid state imaging device1waits for time-out (Step S315). In a case where the time-out occurs (YES in Step S315), the solid state imaging device1determines that the individual identification through the iris authentication has failed, and ends the process (Step S316). Note that, if the imaging conditions are not appropriate for the iris authentication as a result of the determination in Step S312(NO in Step S312), the solid state imaging device1waits for the time-out (Step S317). In a case where the time-out occurs (YES in Step S317), the solid state imaging device1determines that the individual identification through the iris authentication has failed, and ends the process (Step S316).

Here, in the time-out process in Steps S315and S317, it is possible to install a timer in the solid state imaging device1and end the iris authentication process when the process is interrupted by the timer that has finished counting a predetermined time-out period, or it is possible to install the timer in the application processor370and end the iris authentication process when the timer finishes counting the predetermined time-out period and the application processor370notifies the solid state imaging device1of the time-out.

As described above, the embodiment of the present disclosure provides the solid state imaging device1that is able to shorten time it takes to complete the control to prepare the appropriate imaging conditions for the iris authentication process, by setting appropriate imaging conditions for the iris authentication process and the biometric authentication process in the solid state imaging device1.

It may not be necessary for each step in the processes executed by each apparatus or device in the present specification to be performed in a time series process, in accordance with the order described in the sequence diagrams or flow charts. For example, each step in the processes executed by each apparatus or device may be performed in an order different from the order described by the flow charts or may be performed in parallel.

Further, it is possible to create a computer program for causing hardware, such as a CPU, ROM and RAM built-into each apparatus or device, to exhibit functions similar to the configurations of each of the above described apparatuses or devices. Further, it is also possible to provide a storage medium storing this computer program. Further, a series of processes is able to be executed with the hardware, by configuring each of the functional blocks illustrated by the functional block diagrams with the hardware.

In addition, the effects described in the present specification are merely illustrative and demonstrative, and not limitative. In other words, the technology according to the present disclosure may exhibit other effects that are evident to those skilled in the art from the present specification, along with or instead of the above effects.

Note that the technical scope of the present disclosure also includes the following configurations.

A solid state imaging device including:

a pixel array in which pixels are disposed on a matrix;

an iris authenticator that extracts iris information to be used in an iris authentication process, from image data obtained from the pixel array through photoelectric conversion; and

an imaging condition controller that performs control to set an imaging condition in obtaining the image data for the iris authentication process, by using information obtained in a process of extracting the iris information.

The solid state imaging device according to (1), in which the imaging condition controller performs control to set exposure in obtaining the image data, as the imaging condition.

The solid state imaging device according to (1), in which the imaging condition controller controls a focus in obtaining the image data, as the imaging condition.

The solid state imaging device according to any one of (1) to (3), in which the iris authenticator includes an iris extractor that extracts iris information from the image data.

The solid state imaging device according to (4), in which the iris authenticator includes a region detector that detects a region including iris information, from the image data, and the iris extractor extracts iris information from the region detected by the region detector.

The solid state imaging device according to (4) or (5), in which the iris authenticator further includes an iris matching section that executes an iris authentication process using iris information extracted by the iris extractor.

The solid state imaging device according to any one of (1) to (6), further including an encryption processor that encrypts iris information extracted by the iris authenticator.

The solid state imaging device according to (7), in which the encryption processor performs encryption by using unique information acquired from the pixel array.

The solid state imaging device according to any one of (1) to (8), in which two or more semiconductor substrates are joined.

The solid state imaging device according to (9), in which the semiconductor substrates include a first semiconductor substrate on which at least the pixel array is formed, and a second semiconductor substrate on which at least a logic circuit is formed.

The solid state imaging device according to (10), in which the iris authenticator and the imaging condition controller are formed in the logic circuit.

The solid state imaging device according to (10) or (11), in which a wiring line of the first semiconductor substrate and a wiring line of the second semiconductor substrate are directly joined.

A solid state imaging device including:

a first semiconductor substrate on which at least a pixel array is formed; and

a second semiconductor substrate on which at least a logic circuit is formed, the second semiconductor substrate being joined to the first semiconductor substrate,

the pixel array including pixels disposed on a matrix, the pixel array outputting image data,

the logic circuit includingan iris authenticator that extracts iris information from the image data, andan imaging condition controller that controls exposure or a focus on a basis of a result obtained by the iris authenticator.
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A method of controlling a solid state imaging device, the method including:

extracting iris information to be used in an iris authentication process, from image data obtained from a pixel array through photoelectric conversion, the pixel array including pixels disposed on a matrix; and

performing control to set an imaging condition in obtaining the image data for the iris authentication process, by using information obtained in a process of extracting the iris information.

REFERENCE SIGNS LIST