Method for fabricating handling wafer

A method for fabricating handling wafer includes providing a substrate, having a front side and a back side. The front side of the substrate is disposed on a supporting pin. A first oxide layer is formed surrounding the substrate. A portion of the first oxide layer is removed to expose the front side of the substrate. An alignment mark is formed on the front side of the substrate.

BACKGROUND

1. Field of the Invention

The present invention generally relates to semiconductor fabrication, and particularly to a method for fabricating handling wafer.

2. Description of Related Art

As usually known, an integrated circuit as a semiconductor device is fabricated by semiconductor fabrication processes. The integrated circuit get more complicate if the integrated circuit is more powerful, in which a large number of circuit elements with proper interconnect structure are integrated.

To fabricate the semiconductor device of the integrated circuit, the semiconductor device can be divided into two parts. A first part of the semiconductor device is fabricated beforehand separately. After then, the first part of semiconductor device is attached to a handling wafer, which serves as the actual substrate of the semiconductor device. The second part of the semiconductor device can then be fabricated on the first part over the handling wafer, according to the subsequent fabrication processes.

In the above two-stage fabrication manner, the handling wafer needs to be processed to form the protection structure on the back side and an alignment mark on the front side of the handling wafer. The front side would adapt the semiconductor device.

As can be observed, if the handling wafer is not protected well at the back side, the handling wafer would be damaged, particular to the supporting pin region. This would cause malfunction of the circuit elements at this damage area. The back side of the handling wafer need to be carefully protected to maintain the circuit function.

SUMMARY OF THE INVENTION

The invention provides a method for fabricating handling wafer, of which the back side of the handling wafer can be protected in better condition.

In an embodiment, the invention provides a method for fabricating handling wafer including providing a substrate, having a front side and a back side. The front side of the substrate is disposed on a supporting pin. A first oxide layer is formed surrounding the substrate. A portion of the first oxide layer is removed to expose the front side of the substrate. An alignment mark is formed on the front side of the substrate.

In an embodiment, as to the method for fabricating handling wafer, in the step of disposing the front side of the substrate on the supporting pin, the substrate is flipped up-side-down at a first time.

In an embodiment, as to the method for fabricating handling wafer, the method further comprises forming a nitride layer on the first oxide layer at the back side of the substrate.

In an embodiment, as to the method for fabricating handling wafer, in the step of removing the portion of the first oxide layer, the substrate is flipped up-side-down at a second time with respect to the first time.

In an embodiment, as to the method for fabricating handling wafer, the step of removing the portion of the first oxide layer comprises a wet cleaning process.

In an embodiment, as to the method for fabricating handling wafer, the first oxide layer is formed by a thermal oxidation process.

In an embodiment, as to the method for fabricating handling wafer, the substrate is a silicon on insulator (SOI) substrate.

In an embodiment, as to the method for fabricating handling wafer, after performing the cleaning process to forming the alignment mark, the method further comprises: performing an implantation process on the front side of the substrate, forming a photoresist layer with an alignment opening to expose the substrate at the front side, and etching the substrate at the front side through the alignment opening, to form the alignment mark.

In an embodiment, as to the method for fabricating handling wafer, the method further comprises forming a second oxide layer at least on the front side of the substrate before performing the implantation process, and removing the second oxide layer at the front side of the substrate after performing the implantation process.

In an embodiment, as to the method for fabricating handling wafer, the second oxide layer is surrounding over the front side and the back side of the substrate.

In an embodiment, as to the method for fabricating handling wafer, the method further comprises forming a nitride layer on the first oxide layer at the back side of the substrate.

In an embodiment, as to the method for fabricating handling wafer, after performing the cleaning process to forming the alignment mark, the method further comprises performing an implantation process on the front side of the substrate, forming a photoresist layer with an alignment opening to expose the substrate at the front side, and etching the substrate at the front side through the alignment opening, to form the alignment mark.

In an embodiment, as to the method for fabricating handling wafer, the method further comprises forming a second oxide layer on the front side of the substrate before performing the implantation process, and removing the second oxide layer at the front side of the substrate after performing the implantation process.

DESCRIPTION OF THE EMBODIMENTS

The invention is directed to a method for fabricating a handling wafer, involved in a semiconductor device.

Several embodiments are provided to describe the invention with the motivation, but not for limiting the invention.

FIG. 1is a drawing, schematically illustrating a stacked structure of a semiconductor device, according to the invention. Referring toFIG. 1, generally, the handling wafer100has a front side100aand a back side100b. The semiconductor device including the first routing structure layer102, a device layer104and a second routing structure layer106are sequentially disposed on the front side100aof the handling wafer100.

However, the first routing structure layer102is separately pre-fabricated on another temporary substrate but not directly fabricated on the handling wafer100. As to be described later, after the first routing structure layer102is formed, the first routing structure layer102would be disposed onto the handling wafer100with proper alignment. The handling wafer in an example is a silicon-on-insulator (SOI) substrate.

FIG. 2is a drawing, schematically illustrating a structure of handling wafer, according to an embodiment of the invention. Referring toFIG. 2, in order to adapt the first routing structure layer102, with proper alignment, an alignment mark120needs to be formed on the handling wafer100before stacking the first routing structure layer102. In other words, the handling wafer100needs to be firstly processed to form the protection layer at the back side100band an alignment mark on the front side100ato adapt the first routing structure layer102with alignment.

FIG. 3is a drawing, schematically illustrating an assembly process for the handling wafer to adapt the semiconductor device, according to an embodiment of the invention. Referring toFIG. 3, as stated above, the first routing structure layer102, having an interconnect structure having be formed inside, is fabricated on the temporary substrate110. And then, the first routing structure layer102with the temporary substrate110is attached to the handling wafer100at the front side100a. As to the handling wafer100, an oxide layer101has been formed on the backs side100bof the handling wafer100for protection. However, a defect130usually exists in the oxide layer101when formation to be described in detail later. The defect130may almost or actually expose the handling wafer100corresponding to the locations of supporting pins.

FIG. 4is a drawing, schematically illustrating a preliminary semiconductor device adapted by the handling wafer, according to an embodiment of the invention. Referring toFIG. 4, after the first routing structure layer102is firmly stacked on the handling wafer100at the front side100a, the temporary substrate110is removed.

Typically, the temporary substrate110and the handling wafer100are both made of silicon. During removing the temporary substrate110by wet etchant such as TMAH (tetra-methyl ammonium hydroxide) solution, if the back side100bof the handling wafer100is not well protected by the oxide layer, the defect130as currently existing in the oxide layer101may even further punch through the handling wafer100and reach to the first routing structure layer102. After then, the device layer104and the second routing structure layer106as shown inFIG. 1may be subsequently disposed on.

The invention has looked into the semiconductor device inFIG. 1and found at least an issue, which may cause the malfunction of the semiconductor device.FIG. 5is a drawing, schematically illustrating a defect occurring on the handling wafer of the semiconductor device, according to an embodiment of the invention. Referring toFIG. 5, in fabrication process on the handling wafer100, the handling wafer usually needs to be processed to form the alignment mark and the implantation on the front side100aand the protection layer at the back side100bof the handling wafer100. Due to the supporting pins at the back side100bas taken in usual way to hold the handling wafer100, the supporting pins may cause the defects130from the back side100bof the handling wafer100. In the even worse case, the defect130may punch through the handling wafer100and reach to the first routing structure layer102.

Due to the defect130possibly exposing the first routing structure layer102, the first routing structure layer102may be damaged in the subsequent process. As a result, it causes malfunction of the whole semiconductor device.

The invention has looked into the issue in better detail as follows.FIG. 6is a drawing, schematically illustrating the mechanism causing the defect of the handling wafer, according to an embodiment of the invention.FIG. 7is a drawing, schematically illustrating the supporting pin to support the handling wafer, according to an embodiment of the invention.

Referring toFIG. 6andFIG. 7, as the usual way, the handling wafer200in beginning stage of processing is supported by supporting pins204at the back side200bso to perform a thermal oxidation and then thereby form the oxide layer202surrounding the handling wafer200. This thermal oxidation process is performed in a furnace. Wafers are placed in a wafer boat including wafer slots for accommodating wafers, and supporting pins are provided in each wafer slots to ensure wafers are placed in a proper position. As noted, the supporting pins204support the handling wafer200at the back side200bwith directly contact to the handling wafer200. As a result, the thermal oxidation has poor effect at the contact surface between the supporting pins204and the handling wafer200and also the space occupied by the supporting pins204themselves. In other words, the oxide layer202cannot fully cover over the handling wafer200at the back side200b.This issue would cause the defect on the handling wafer200in the subsequent fabrication process to accomplish the semiconductor device.

FIG. 8is a drawing, schematically illustrating the defect of the handling wafer, according to an embodiment of the invention. Referring toFIG. 8, in the subsequent fabrication processes, after the handling wafer200is taken out from the supporting pins204. In the subsequent fabrication processes, the additional thermal oxidation may be performed to form the protection layer210at the back side200of the handing wafer or a screen oxide layer210aon the front side200afor implantation. The defects212corresponding to the pin areas may remain at the back side200bof the handling wafer200, causing the malfunction of the semiconductor device.

The invention has at least looked into the issues stated above, and then proposes to flip the handling wafer200when the thermal oxidation process is performed on the handling wafer at the beginning stage. After then, the handling wafer200is flipped back for wet cleaning process on the front side of the handling wafer.

FIG. 9is a drawing, schematically illustrating the method for fabricating the handling wafer, according to an embodiment of the invention. Referring toFIG. 9, in step S100, a substrate300is provided. The substrate300has a front side300aand a back side300b.However, the substrate300is flipped, so that the front side300ais disposed on the supporting pins204. At this beginning stage, a thermal oxidation process is performed to form the oxide layer302to surround the substrate300. The thickness of the oxide layer302is for example 4000 A or less but not limited to this thickness. However, in general, the oxide layer302is fully surround substrate300.

Remarkably in this stage, the supporting pins204contact on the front side300a. The front side300aof the substrate300, serving as the handling wafer, is to adapt the routing structure layer later.

In step S102, the substrate300is flipped back, so the front side300ain this stage as drawn is at the top side. The back side300bis the bottom side. A portion of the oxide layer302on the front side300aof the substrate300is removed, such as wet cleaning, or other proper process, without limiting to the example. The front side300aof the substrate300is then exposed.

Remarkably, the pin effect occurring on the front side300aof the handling wafer is effectively excluded. However, the back side300bof the substrate300can be well protected by the oxide layer302without pin effect.

In step S104, additional oxide layer302ais formed on the exposed surface of the substrate300at the front side300a. The oxide layer302acan be formed by another thermal oxidation process, so the oxide layer302at the back side300bget thicker. The oxide layer302ain function can be also realized as the screen layer, which is in association with implantation process304later on the substrate300in step S106.

Actually, the oxide layer302ais optionally formed and therefore can be omitted. However, in the embodiment, the oxide layer302ais formed as an example. As to the thickness of the oxide layer302a, it can be in a range between 0 A and 500 A, in which 0 A indicates the oxide layer302ais omitted. Also, the impurity in the implantation process is Ge, for example. However, the implantation process is also an embodiment, not absolutely required in processing the handling wafer.

In step S108, after the implantation process304, the oxide layer302ais removed again to expose the front side300aof the substrate300.

In step S110, a photoresist layer306with an alignment opening308, as an example, is formed on the substrate300at the front side300a.

In step S112, the photoresist layer306serves as an etching mask and an etching process is performed to form the alignment mark310on the substrate. And then, the photoresist layer306is removed. The alignment mark310is used for alignment when the routing structure layer is attached to the substrate300as shown inFIG. 3.

Alternatively in another embodiment,FIG. 10is a drawing, schematically illustrating the method for fabricating the handling wafer, according to an embodiment of the invention. Referring toFIG. 10, in step S200, a substrate400is provided, likewise toFIG. 9. The substrate400has a front side400aand a back side400b. However, the substrate400is flipped, so that the front side400ais disposed on the supporting pins204. At this beginning stage, a thermal oxidation process is performed to form the oxide layer402to surround the substrate400. The thickness of the oxide layer302is for example 4000 A or less but not limited to this thickness. However, in general, the oxide layer302is fully surround substrate300.

In step S202, the substrate400keeps at the flipped state, in which a nitride layer404can be additionally formed on the oxide layer402over the back side400b. The nitride layer404is formed by a single wafer deposition tool, such as a plasma enhanced chemical vapour deposition tool, which only deposits films on one side of the wafer. The nitride layer404serves as a part of the protection layer at the back side400bof the substrate400.

In step204, the substrate400now is flipped back, so the front side400ais the top side and the back side400bis the bottom side. A portion of the oxide layer402at the front side400aof the substrate400is removed by a process, such as wet clean, but not limiting to wet clean.

In step S206, the oxide layer402ais formed to serve as the screen layer similarly to the step S104inFIG. 9. In step S208, the implantation process406with the impurity of Ge is performed. This is similar to the step S106inFIG. 9.

After then, the alignment mark is to be formed on the substrate400at the front side400a. The processes can be referred to the steps S108, S110and S112inFIG. 9without further descriptions.

As to the foregoing descriptions, the back side of the handling wafer has not suffering the pin effect. The pin effect actually occurs on the front side of the handling wafer. However, the pin effect on the front side of the handling wafer can be removed due to the wet cleaning process at the next stage. As a result, the front side of the handling wafer can keep the quality as usual. The back side of the handling wafer has no pin effect at the beginning stage of thermal oxidation process.