Testing printed circuit board assembly

Embodiments of the present invention provide systems and methods for destructive testing of a printed circuit board assembly (PCBA). The PCBA contains embedded components on a printed circuit board within a non-functional area. At least one of these embedded components is susceptible to defects and exposed to conditions that facilitate destructive testing which leads to accelerated measurements. The accelerated measurements on the non-functional area are more representative of variability than measurements on a functional module while providing insights into potential future defects.

BACKGROUND

The present invention relates generally to the field of manufacturing technology, and more particularly to reliability testing of power package materials.

Printed circuit boards (PCBs) may be exposed to extreme environment (e.g., high temperatures). A conformal coating is a thin polymeric film applied on the surface of PCBs, wherein the conformal coating prevents corrosion, leakage currents, and electric shorting due to condensation. Assembled PCBs (PCBAs) contain embedded electronic components (e.g., capacitors, and resistors) which are typically soldered onto a surface of the PCB. PCB mechanically supports and electrically connects electronic components using conductive tracks, pads, and other features which are etched from copper sheets laminated onto a non-conductive substrate. PCBs may be single sided (e.g., one copper layer), double sided (e.g., two copper layers), or multi-layered (e.g., outer and inner layers).

PCBs are designed via layout software. The designing process takes into account: (i) the schematic capture (i.e., circuit design); (ii) the card dimensions and template based on the required circuitry and properties of the PCB; (iii) the positions of the electronic components and heat sinks to be embedded on the PCB or attached to the PCB; (iv) the layer stacks (e.g., ground and power planes within the PCB); (v) the line impedance matching (i.e., the maximization of electric power transfer/minimization of signal reflection from an electric lead) based on dielectric layer thickness, routing copper thickness, and trace-width; (vi) the placement of electronic components based on thermal and geometric considerations; (vii) the routing of signal traces; and (viii) the generated Gerber files for manufacturing. The manufacturing of PCBAs involves many steps such as: inputting Gerber files into Computer Aided Manufacturing (CAM) software; panelization (e.g., grouping PCBs for manufacturing onto a panel); copper patterning (e.g., subtractive, additive, and semi-additive processes); chemical etching (e.g., removing materials to create an object with the desired shape via etching chemicals); automated optical inspection (e.g., scanning the PCB and comparing the scanned PCB with the digital image deriving from the Gerber files); laminating materials to yield trace layers inside a PCB; drilling holes through a PCB; plating PCBs with solder, tin, or gold over nickel as a resist for etching away the unneeded underlying copper; coating PCBs with solder or some other anti-corrosion coating; applying solder resists on select areas of the PCBs; printing a legend on one or both sides of PCBs; and populating the PCB with electronic components in order to yield the PCBA. Assembly and component defects may occur during the production of PCBAs.

SUMMARY

According to one embodiment of the present invention, a method is provided. The method comprises: integrating a printed circuit board assembly (PCBA) and a computing device, wherein the PCBA contains a plurality of functional areas and a plurality of non-functional areas on a printed circuit board (PCB); stressing a non-functional area of the plurality of non-functional areas of the PCBA that is susceptible to defects, wherein the non-functional area contains an embedded component susceptible to defect; applying destructive testing to failure of the embedded component susceptible to defect; and responsive to applying the destructive testing, deriving information from the applied destructive testing.

Another embodiment of the present invention provides a computer program product, based on the method described above.

Another embodiment of the present invention provides a computer system, based on the method described above.

DETAILED DESCRIPTION

By virtue of PCBAs being incorporated into other devices (e.g., products sold in the market place), these defects may result in latent field defects and product reliability problems. Thus, PCBAs need to be tested in order to determine if defects are present. Subsequent to populating the PCB with electronic components, the PCBA can be tested using automated optical inspection, analog signature analysis (e.g., power-off testing), in-circuit testing (e.g., performing physical measurements while the power is on such as voltage), and functional testing. For example, subsequent machine operation, temperature variations due to power cycling, and variability could cause degradation/deterioration the PCBA (e.g., solder joint cracks) due to the forces brought to bear by differences in material coefficients of thermal expansion. Components which fail in a PCB or PCBA are typically composed of soldered connections, laminates, copper-clad laminates, resin impregnated B-stage cloth, and/or copper foil. These defect modes are often characterized in a lab setting on a small sample of production builds that are destructively tested. This destructive testing is costly. Furthermore, the smaller sample sizes used for destructive testing may not be indicative of products manufactured through the life of the product or during the manufacturing of the product (i.e., non-representative results may be obtained). This disclosure remedies these issues and improves the art by the following functions: (i) performing an accelerated destructive testing to failure in a small non-functional area of each PCBA which is accomplished by connecting an apparatus to the non-functional area; and (ii) sending data from the destructive testing to a computer. In turn, these functions characterize the entire PCB of the PCBA and like electronic components that are not destroyed used for client operations. During the production of each PCB and corresponding PCBA, and during use in the field, accelerated destructive testing is applied to fail in a non-functional area of the PCB. Real time measurements and accelerated measurements of each PCB may occur and thus, the testing of certain areas of the PCB is accelerated beyond the normal functional areas. These measurements provide insight into potential failures and replicates the structure of the functional areas of the PCB.

The present invention will now be described in detail by referencing the Figures.FIG. 1Ais a diagram illustrating a data processing environment, generally designated100A, in accordance with one embodiment of the present invention.FIG. 1Aprovides only an illustration of implementation and does not imply any limitations regarding the environments in which different embodiments may be implemented. Modifications to data processing environment100A may be made by those skilled in the art without departing from the scope of the invention as recited by the claims. In this exemplary embodiment, data processing environment100A includes a PCBA125, device115, computer110, and stressor120all interconnected by network114.

Network114can be, for example, a local area network (LAN), a wide area network (WAN) such as the Internet, or a combination of the two, and can include wired, wireless, or fiber optic connections. In general, network114can be any combination of connections and protocols that will support communication between PCBA125, device115, computer110, and stressor120.

The notation of “pad130-A” through “pad130-H” is used to differentiate different units of pad130, wherein pad130represents a pad (e.g., a copper surface which has electronic components soldered onto the copper surface).

The notation of “via145A” through “via145H” is used to differentiate different units of via145, wherein via145represents a via (i.e., a plated hole) which connects two different layers within a PCB or PCBA and facilitates conduction within a PCB/PCBA. A PCBA is a system which has embedded electronic components on the surface of the PCB.

The notation of “path135-A” through “path135-H” is used to differentiate different units of path135, wherein path135are conductive tracks that connect two or more pads (e.g., pad130); two or more vias (e.g., via145); and at least one pad (e.g., pad130) and at least one via (e.g., via145). Varying the width of path135controls the amount electric current transferred to pads and vias.

Pad130-A through pad130-H are copper surfaces in a printed circuit board (PCB) on which a component, such as component105or component106, can be soldered on. Component105and component106may be a resistor, transistor, capacitor, or other electronic components that are compatible with printed circuit board technology. Component105and component106may be: (i) mounted or placed directly onto the surface of a printed circuit board (e.g., surface140A) via surface-mount technology or (ii) by inserting leads of component105or component106into holes drilled onto the surface of a printed circuit board and soldered to pad130. In an exemplary embodiment, component105is soldered on surface140A while component106is soldered onto surface140D. Units of component106, as soldered onto surface140D, are not contained within a non-functional area while units of component105, as soldered onto surface140A, are contained with a non-functional area.

PCBA125is an example of a multi-layered printed circuit board assembly, wherein multiple units of component105are embedded onto the surface of the PCBA125. There are three layers in PCBA125—layer150A, layer150B, and layer150C. The surfaces of layer150A, layer150B, and layer150C may be also referred to as planes. In an exemplary embodiment, a single unit of component105has been soldered onto pads130-A,130-B,130-C, and130-D for a total of four units of component105embedded on surface140A. Surface140A contains a non-functional pad contained within stressor120, wherein stressor120is connected to device115and a unit of component105soldered into pad130-C. The unit of component105soldered into pad130-C is connected to computer110. While not connected to computer110, another unit of component105is soldered into pad130-D and contained within stressor120. In an exemplary embodiment, the non-functional pads, as contained within stressor120, have a soldered unit of component105that has been deemed to be the biggest contributor to early life solder cracks (i.e., deterioration of components) due to thermally induced coefficient of thermal expansion (CTE) mismatch characteristics. Furthermore, sensing circuitry is contained within the soldered unit of component105that has been deemed to be the biggest contributor to solder cracks in order to obtain data/information relevant for detecting a solder crack failure mechanism.

The top surface of layer150A is surface140A, wherein surface140A also contains a unit of component105soldered onto pad130-C; another unit of component105soldered onto pad130-D; path135-A connects pad130-A to via145A; path135-B connects pad130-B to via145B; path135-C connects pad130-C to via145A; and path135-D connects pad130-D to via145B. The top surface of layer150B is surface140B, wherein surface140B does not contain soldered units of component105, units of path135, or units of pad130. However, surface140B contains via145C and via145D. In various embodiments, the top surface of layer150C is surface140C does not contain soldered units of105, units of paths135, or units of pad130. However, surface140C contains via145E and via145F. In an exemplary embodiment, the bottom surface of layer150D is surface140D, wherein surface140D contains soldered units of component106in pad130-E, pad130-F, pad130-G, and pad130-H. Furthermore, surface140D contains: path135-E which connects pad130-E to via145G; path135-F which connects pad130-F to via145H; path135-G which connects pad130-G to via145G; and path135-H which connects pad130-H to via145H. A single layer within the multiple layers of PCBA125may be nonconductive (e.g., silkscreen layer and soldermask layers) or conductive (e.g., isolated voltage supply or ground layer). In other embodiments, a different number of layers may be incorporated into PCBA125without departing from the scope of the invention as recited in the claims. In this exemplary embodiment, surface140A and surface140D are equally populated/de-populated with components, while compatible with stressor120in order to conduct destructive testing of non-functional pads. In another exemplary embodiment, surface140A and surface140D are not equally populated/de-populated with components while compatible with stressor120in order to conductive destructive testing of non-functional pads.

Via145A is directly above via145C, wherein via145C is directly above via145E, and wherein via145E is directly above via145G. Via145B is directly above via145D, wherein via145D is directly above via145F, and wherein via145F is directly above via145H. Pad130-A is directly above pad130-E. Pad130-B is directly above pad130-F. Pad130-C is directly above pad130-G. Pad130-D is directly above pad130-H. Path135-A is directly above path135-E. Path135-B is directly above path135-F. Path135-C is directly above path135-G. Path135-D is directly above path135-H.

In various embodiments, stressor120is an apparatus which simulates voltage, temperature, and frequency cycling. In some embodiments, stressor120can be directly connected to device115. Device115may be an additional device or setup which is able to control the amount of voltage, temperature, and frequency cycling applied onto a non-functional area of PCBA125. By controlling the amount of voltage, temperature, and frequency cycling, stressor120is able to perturb the non-functional pad of PCBA125to destructive fail in an accelerated manner. Isolated voltage and ground layers of PCBA125aid in simulating voltage regulation. This serves as a controller feature. In an exemplary embodiment, device115is a Josephson junction (JJ)-type device which produces a super current (i.e., a current that flows indefinitely long without applying any voltage). For example, device115cycles the power on stressor120in an accelerated manner in order to facilitate the destructive fail of a unit of component105soldered onto pad130-C, wherein device115is a JJ-type device. In another embodiment, device115is a cooling device which is able to expose the non-functional pad within stressor120to extreme cold temperatures.

Where the setup as depicted inFIG. 1Ais not used, in various embodiments, 18000 mini-cycles can be used to facilitate the destructive fail of a unit of component105soldered onto pad130-C. Where the setup as depicted inFIG. 1Ais used, 2000 to 4000 mini-cycles are required to facilitate the destructive fail of a unit of component105soldered onto pad130-C. Fewer mini-cycles (e.g., 2000 mini-cycles as opposed to 18000 mini-cycles) proves to be less costly as less electric energy and resources are consumed in order to ascertain the strength and reliability of the solder joint strength of the unit of component105soldered onto pad130-C. Furthermore, this type of destructive testing to fail of a non-functional area is more representative of failed components embedded onto PCBA125as opposed to testing a functional area. Suspect components (e.g., units of component105), which are prone to performance defects and interact with the functional module frequently, pass quality control tests due to the interactions with the functional area despite the suspect component exhibiting poor performance parameters (e.g., weak solder joint strength or degradation to mild conditions). These type of interactions with the suspect component do not necessarily improve the quality of the suspect component. Instead, these type of interactions influence the quality control testing process and skews the result towards passing despite the performance issues exhibited by the suspect component. By utilizing stressor120-type setup on a non-functional area of PCBA125for destructive testing, quality assurance testing would be more representative of PCBA125by accounting for the poor performance of the suspect component.

In various embodiments, application113is an application that the user (through a graphic user interface) runs on computer110. Application113can behave as a computer program designed to perform a group of coordinated functions, tasks, or activities for the benefit of the user. Some of these functions, tasks, or activities include: controlling/interfacing with device115(e.g., modifying the settings that subsequently control stressor120in order to perform an accelerated thermal cycle (ATC)); applying destructive testing of a non-functional pad within PCBA125using stressor120and device115; monitoring changes in properties of component105soldered onto pad130-C (e.g., monitoring CTE of PCBA125in real-time); obtaining information (i.e., data) which corresponds to the changes in the properties of component105soldered onto pad130-C; storing the obtained information into a database (or repository-type structure); and sending the obtained information to graphical user interface or outputting the obtained information to a monitor. In an exemplary embodiment, stressor120is instructed by application113to apply destructive testing cycle on a component contained within a non-functional pad/area until the component or stressor120fails. For example, the component (e.g., a unit of component105soldered onto pad130-C) that fails typically experiences solder cracks at 500 forced temperature cycles. By applying application113, stressor120, and device115in conjunction with each other, 250 forced temperature cycles lead to solder cracks as opposed to the typical 500 forced temperature cycles when application113, stressor120, and device115do not work in conjunction with each other. In other words, in various embodiments, the combination of application113, stressor120, and device115work in unison with each other in order to modulate (i.e., control) the accelerated stressor conditions that are applied on non-functional areas. By modulating the accelerated stressor conditions, some of the components (e.g., a unit of component105) within the non-functional area reach the point of failure at an accelerated pace. By virtue of: (i) modulating the accelerated stressor conditions and (ii) reaching failure at the accelerated pace, application113is able to detect/observe the data and the data trends which correspond to the accelerated destructive testing to failure of the component. These components, which experience the accelerated destructive testing to failure in response to the applied accelerated stressor conditions within the non-functional area, are indicative of potential future defects in a product. Detected/observed data and data trends, as obtained by application113, may further aid in the description/understanding of what the potential future defects may be (e.g., metal surfaces of solder joints which are prone to overheating that melt plastic surfaces) and/or the variables which effect the defects (e.g., temperature or voltages). The range of cycles, in which stressor120and component105soldered onto pad130-C fail, is reflective of an expected field life of PCBA125. In various embodiments, the connection of stressor120to device115and the connection of the unit of component105soldered onto pad130-C to application113represents a call home feature. The call home feature is able to send obtained information to a database in order to gather and analyze field reliability metrics. The database, which is not depicted inFIG. 1A, resides in computer110. Application113utilizes a programmable setup in which destructive testing is applied on a non-functional pad contained within stressor120while running parallel tests and obtaining information during voltage, temperature, and frequency cycling. In an exemplary embodiment, upon applying the destructive testing to fail on the non-functional pad contained within stressor120, application113obtains temperature difference data to calculate the acceleration factor of the Coffin-Manson equation. The degradation of the non-functional pad contained within stressor120until fail may be monitored in real time while obtaining data which corresponds to degradation events. For example, application113is connected to stressor120, wherein stressor120is connected to device115. Stressor120and device115work in unison to increase the voltage applied to component105soldered onto pad130-C and component105soldered onto pad130-D over a period time. The voltage is applied until the soldered components within stressor120fail. The setup as depicted inFIG. 1Aallow an end-user to observe the initial onset of component degradation upon increasing voltages.

Computer110houses application113, graphical user interface (GUI), and a database, wherein application113, the GUI, and the database are connected to each other. Computer110may be a laptop computer, a tablet computer, a netbook computer, a personal computer (PC), a desktop computer, a personal digital assistant (PDA), a smart phone, a thin client, or any programmable electronic device capable of communicating with stressor120and device115via network114. Computer110may include internal and external hardware components, as depicted and described in further detail with respect toFIG. 4.

FIG. 1Bis a diagram of a section of a PCBA, in accordance with an embodiment of the present invention.

PCBA100B is a section of a printed circuit board assembly which contains a non-functional pad to be exposed to accelerated stressing conditions which lead to the failure of components within cover185. Printed circuit assemblies may prove to be very complex structures with many components, functional modules, and non-functional pads. The interplay of these components, functional modules, and non-functional pads may lead to variability in performance of PCBAs. Sections of PCBAs may meet quality assurance standards while other sections of PCBAs contain non-functional pads and/or components prone to defects, which may not meet quality assurance standards. Thus, the obtained quality assurance data for the complex PCBAs may prove to be non-representative and even misleading. In an exemplary embodiment, PCBA100B contains non-functional pads exposed to accelerated stressing conditions in order to obtain a more representative result of a PCBA. Thus, insights into components prone to defects at a future point in time of the product's lifetime are obtained on the PCBA and the PCB associated with PCBA100B.

Surface190is the plane/surface of the PCBA (e.g., PCBA125) on which components have been soldered onto a non-functional pad region. For the purpose of clarity, pathways, pads, and other PCBA structures are not depicted on surface190. When pathways and pads are depicted, the PCBA may resemble a structure as depicted inFIG. 1A. In an exemplary embodiment, cover185is a heat cover which serves as an apparatus similar or equivalent to stressor120. Cover185retains heat in order to simulate temperature cycling. In this exemplary embodiment, the solder components are 34 units of resistor160, 18 units of capacitor155, 27 stitching fence units (e.g., via145), quad flat no-leads (QFN) QFN170, QFN175, and inductor180. Resistor160is a device which resists/impedes the passage of an electric current. Capacitor155is a device which stores electric charge. Inductor180is a device that stores electrical energy in a magnetic field when electric current is flowing through inductor180.

QFN170and QFN175are quad-flat no-lead packages which physically and electrically connect integrated circuits to printed circuit boards (and printed circuit board assemblies). QFN170is a general type quad-flat no-lead package that modulates/controls signaling, clocking, and detection functions whereas QFN175controls the on/off functions of a quad-flat no-lead package that modulates/control voltage regulation. QFN170and QFN175are a surface-mount technology which connects integrated circuits to the surface190without having to use through-hole technology. Flat no-lead is a near chip scale (according to IPC™-Association Connecting Electronic Industries conventions) plastic encapsulated package made with a planar copper lead frame substrate. (Note: the term(s) “IPC” may be subject to trademark rights in various jurisdictions throughout the world and are used here only in reference to the products or services properly denominated by the marks to the extent that such trademark rights may exist.) As depicted inFIG. 1B, QFN170is physically larger in area as QFN175. In other embodiments, QFN175is physically larger in area than QFN170. QFN170and QFN175can be made to any specification for enabling/performing the disclosure, as recited in the claims. Furthermore, in other embodiments, there may be other components aside from QFN170and QFN175soldered onto surface190, as contained within non-functional areas. These other components may be exposed to the applied stressor conditions and undergo destructive testing to fail. QFN170contains different perimeter lands and exposed thermal pads than QFN175. These differences are described in more detail with respect toFIG. 2AandFIG. 2B, respectively. QFN170and QFN175may often experience CFE mismatches and experience solder joint cracks. The multiple units of resistor160and capacitor155and QFN170contain the circuitry for detecting the solder joints cracks. The call home feature (as described above with respect to application113) and the controller feature (as described above with respect to stressor120and device115) reside within QFN170.

FIG. 1Cis a circuit schematic diagram of a PCBA, in accordance with an embodiment of the present invention.

Schematic100C is a circuit schematic consistent with the components which have been soldered onto surface190ofFIG. 1B. R1to R32correspond with the multiple units of resistor160; C1to C14correspond with the multiple units of capacitor155; QFN170is connected to QFN175; QFN175is connected to voltage source V++; inductor180is connected to QFN175and voltage source V+. The notation V+ implies a different voltage from V++. For example, inductor180connects to a different voltage source (i.e., V+) than QFN175(i.e., V++). Voltage source V+ is also connected to QFN170and R17to R32. C1to C4; QFN170; R17to R32; and QFN175are connected to a grounding device (GND).

FIG. 2Ais a screen shot of different views of a type of quad flat no-leads (QFN) package, in accordance with an embodiment of the present invention.

Screen shot200A contains a bottom view of QFN170, an isometric view of QFN170, and a top view of QFN170depicted as170-B,170-ISO,170-T, respectively. QFN170is a typically square shaped device. On the perimeter of170-B, the perimeter lands are labelled with a “PL” and the single thermal pad is labelled with a “TP” as depicted inFIG. 2A. Perimeter lands on the bottom of QFN170provide electric connections to the printed circuit board. The thermal pad improves heat transfer out of the integrated circuit into the printed circuit board.

FIG. 2Bis a screen shot of different views of another type quad flat no-leads (QFN) package, in accordance with an embodiment of the present invention.

Screen shot200B contains a bottom view of QFN175, an isometric view of QFN175, and a top view of QFN175depicted as175-B,175-ISO,175-T, respectively. In this embodiment, QFN175is a typically square shaped device. However, in other embodiments, QFN175may be made to any optimal shape required. On the perimeter of175-B, the perimeter lands are labelled with a “PL” and the three different types of thermal pads are each labelled as “TP1”; “TP2”; and “TP3”, as depicted inFIG. 2B. PLs connect to the two wires which directly connect QFN170and QFN175. TP1connects to an outputting set of components (e.g., inductor180inFIG. 1C); TP2connects to an inputting set of components (e.g., voltage source V++ inFIG. 1C); and TP3connects to grounding set of components (e.g., grounding device GND inFIG. 1C). Perimeter lands on the bottom of QFN175provide electric connections to the printed circuit board. The thermal pad improves heat transfer out of the integrated circuit into the printed circuit board.

FIG. 3is a flowchart depicting the steps to test a PCBA, in accordance with an embodiment of the present invention.

Flowchart300depicts the steps performed by application113(e.g., steps305,310,315, and320).

In step305, application113integrates a PCBA and computing device(s). In an exemplary embodiment, application113integrates a PCBA and computing devices (e.g., computer110) by physically attaching an apparatus such as stressor120to the surface of a PCBA (e.g., surface140A of PCBA125). Stressor120is operatively connected to computer110and device115. Device115is described above in further detail with respect toFIG. 1A. Application113resides within a computing device, such as computer110. In various embodiments, Application113contains a graphical user interface and a database/or access to a database associated with a different computer program

In an exemplary embodiment, application113integrates a PCBA and computing devices (e.g., computer110) by controlling the functioning of device115and stressor120while detecting changes/modifications of a component contained within stressor120. As mentioned above, stressor120is physically attached to or physically placed over a non-functional area of surface of the PCBA, wherein the non-functional area contains a component susceptible to defects. Thus, the component susceptible to defects is: (i) contained within stressor120; and (ii) capable of communicating with application113. By virtue of being capable of communicating with application113, detected modifications to the component susceptible to defects are obtained by application113. In an exemplary embodiment, a database in computer110stores any obtained information/data from destructive tests. This information/data can then be analyzed and further manipulated by an end-user in order to understand trends during destructive testing to fail.

In step310, application113simulates voltage, temperature, and frequency cycling. In this embodiment, application113simulates voltage, temperature, and frequency cycling by transmitting a set of instructions to stressor120to simulate voltage, temperature, and frequency cycling. In this embodiment, application113transmits instructions to stressor120according to a user request. In other embodiments, application113transmits instructions to stressor120to simulate voltage, temperature, and frequency cycling according to a pre-defined schedule.

In an exemplary embodiment, stressor120is designed to act upon a non-functional area which contains an embedded component of interest as opposed to a functional module which contains the embedded component of interest. In an exemplary embodiment, the component of interest is susceptible (i.e., a suspect component) to solder cracking as in the case of QFN170. Simulating voltage, temperature, and frequency accelerates the destructive testing conditions within the non-functional area corresponding with stressor120. Simulating voltage, temperature, and frequency cycling on a non-functional area using stressor120leads to measurements that more representative of the entire PCBA. A more representative measurement is in turn a more accurate measure by taking into account suspect components and non-suspect components and different types of area of the PCBA.

Destructive testing of functional modules as opposed to destructive testing of non-functional areas of PCBAs tend to have significant costs. Destructive testing to fail of functional modules may involve the following scenarios: (i) sampling at the start of production of PCBAs which does not capture drifts in process parameters; (ii) cross section analysis of a high performing section/part of the PCBA which does not capture variability within the high performing section/part deemed to pass a quality assurance test (e.g., a high CTE known to cause separations across a range of connections is overlooked within the section that passes a quality assurance test); (iii) electrical testing of the PCBA which may overlook electric connections of separations operatively connected to each other without accounting for suspect components; and (iv) utilizing digital imaging correlation to evaluate CTE of PCBs corresponding to the respective PCBAs by measuring in-plane and out-of-plane displacements of an object surface. Thus, obtaining data on non-representative samples of a PCB or a PCBA, scenarios (i), (ii), (iii), and (iv) are not as conducive for making accurate measurements with respect to component, sub-components, etc. of a PCBA susceptible to: (a) poor performance; and/or (b) undesired properties (e.g., a tendency of solder joint cracking of QFN170upon exposure to temperature fluctuations).

In step315, application113applies destructive tests until fail. In this embodiment, application applies destructive tests until fail by transmitting a set of instructions to stressor120to apply destructive tests until fail. In this embodiment, stressor120may be connected to device115. In this instance, device115is able to control the conditions which stressor120applies onto soldered components on a non-functional area of a surface of the PCBA. An example of a “destructive test until fail” are “destructive cycling tests.” In destructive cycling tests, the soldered component on a non-functional area of a surface of the PCBA is exposed to accelerated stressor conditions to the point of soldered component failure.

In an exemplary embodiment, stressor120and device115are connected to each other to control by varying the amount of heat applied to the non-functional area. Over a period of time, there is an initial large increase in temperature followed by an even larger increase in temperature, and a concluding small increase in temperature causing a soldered component within the non-functional area to fail (e.g., cracking a solder joint of QFN170). As stated above, this is an example of accelerated testing conditions. Other types of destructive tests that may be applied include: (i) higher than typical heat exposure to non-functional areas of the PCBA in a controlled fashion; (ii) higher than typical strain exposure to non-functional areas of the PCBA in a controlled fashion; (iii) higher than typical humidity exposure to non-functional areas of the PCBA in a controlled fashion; and (iv) higher than typical flux to non-functional areas of the PCBA in a controlled fashion. The “typical” heat, strain, humidity, and flux exposures are conditions that are most frequently used by a tester in the field. The PCBA structures amenable to this type of destructive testing include: (i) high CTE components susceptible to solder cracks; (ii) thermally sensitive components susceptible to structural defects due to heat; and (iii) vias, traces, pads and other PCB structures susceptible to defects due to heat, strain, flux, etc. The application of this type of destructive test to fail on each PCB (or PCBA) during production on a non-functional area occurs in an accelerated manner. Certain areas have thus, experienced accelerated destruction to fail beyond the typically analyzed functional module areas. The functional area meeting quality assurance standards may mask/hide that there are potentially defective components in a non-functional area. In various embodiments, the accelerated destructive testing until fail within the non-functional area does not interfere with the functional areas and only modifies components within the non-functional area. Subsequently, application113is able to compare the area exposed to accelerated destruction to the area not exposed to accelerated destruction by outputting a generated interactive graph displayed in the graphic user interface of application113. This comparison is then a way of: (i) providing future insights into potential failures; and (ii) replicating the structure of the functional board. For example, a solder joint of QFN170rapidly disintegrates upon extreme voltage fluctuations in the non-functional area as opposed to QFN170remaining intact upon extreme voltage in the functional area. This is indicative of QFN170of being a potential source of product failures despite the functional area meeting quality assurance standards.

In various embodiments, the generated interactive graph display in the graphical user interface of application113shows/outputs data obtained by stressing a non-functional area. The obtained data can be further refined as a function of analysis, as performed by application113. Furthermore, there may be a voluminous amount of obtained data upon stressing the non-functional area. In such instances, the obtained data needs to be further refined or analyzed in order to: (i) ascertain trends or (ii) output visualizations which associate a variable (e.g., temperature) with a suspect component prone to defects under accelerated destructive testing conditions to fail. For example, the obtained data may be temperature and viscosity measurements as a function of time. Application113has selectable “buttons” in the graphical user interface of application113for performing further analysis. There is one button for fitting the data to the Coffin-Manson equation (which incorporates temperature as a parameter to calculate acceleration factors) and another button for fitting the data to the Mark-Houwink-Sakurda equation (which incorporates viscosity as a parameter to calculate molecular weight distribution of polymers). In response to selecting the buttons for the Coffin-Manson equation and the Mark-Houwink-Sakurda equation, trends may be spotted which correspond to the failure of a component prone to defects contained within the non-functional area of the PCBA under accelerated stressor conditions. In this example, the obtained data fits the Coffin-Manson equation but does not fit the Mark-Houwink-Sakurda equation. This is indicative of: (i) temperature, as obtained by measurements from the accelerated destructive testing to fail, effects the failure of the suspect component suspect component; and (ii) viscosity, as obtained by measurements from the accelerated destructive testing to fail, does not effect the failure of the suspect component. Thus, analysis by further refining obtained data, as performed by application113, aids in examining/testing the effect of a variable (e.g., temperature or viscosity) on the failure of a unit of component105soldered in the non-functional area of PCBA125. More specifically, application113may determine: (i) which components within a non-functional area are prone to defects; and (ii) whether a variable of interest may or may not have an effect on the suspect component to failure. In other embodiments, visualizations from the obtained data in response to applying accelerated stressor conditions may be used for in-situ and real-time monitoring of the non-functional area and suspect components in the non-functional area. New tests or quality assurance measures, in addition to known or established tests, may be devised which quantify and qualify events that correlate with the suspect component in the non-functional area, in response to accelerated destructive testing to fail.

In step320, application113sends information to a database. In this embodiment, application113sends the information gathered from the applied destructive tests to a database via network114, wherein the database resides in computer110. In other embodiments, application113can send the information gathered from the applied destructive tests to one or more other components of data processing environment100A. In an exemplary embodiment, from the obtained/gathered information, application113can further manipulate the obtained/gathered information in order to find variables that contribute to the failure and/or defects of components contained within stressor120, wherein stressor120communicates with application113.

In this embodiment, the information/data sent to the database has been obtained from steps310and315. In an exemplary embodiment, the information/data obtained can include temperatures that are monitored during cycling and the application of the destructive cycling tests until fail. These temperatures are recorded/obtained by application113and sent to a database. This temperature data is further analyzed and refined by application113. For example, refining temperature data involves computing temperature differences in order to calculate the acceleration factor of the Coffin-Manson equation.

The obtained information/data may also be used to correlate degradation events during the destructive testing to fail within a non-functional area. For example, major temperature increases for a prolonged period of time lead to simultaneous solder joint cracking of QFN170and soldered units of resistor160cracking. In the instance of a major temperature increase, the solder joint cracking of QFN170and the cracking of soldered units of resistor160are the only events corresponding with components that experience destruction to fail. In contrast, minor temperature increases for a prolonged period of time lead to initial cracking of soldered units of resistor160followed by solder joint cracking of QFN170. In the instance of a minor temperature increase, the solder joint cracking of QFN170and the cracking of soldered units of resistor160are the only events corresponding with components that experience destruction to fail. These results are indicative of: (i) QFN170of a PCBA being more sensitive to temperature increases than resistor160; and (ii) the amount of temperature increase (major increase as opposed to minor increase) influences how/when the components fail (simultaneous failure as opposed to non-simultaneous failure).

Memory406and persistent storage408are computer readable storage media. In this embodiment, memory406includes random access memory (RAM)414and cache memory416. In general, memory406can include any suitable volatile or non-volatile computer readable storage media.

Communications unit410, in these examples, provides for communications with other data processing systems or devices. In these examples, communications unit410includes one or more network interface cards. Communications unit410may provide communications through the use of either or both physical and wireless communications links. Program instructions and data used to practice embodiments of the present invention may be downloaded to persistent storage408through communications unit410.

I/O interface(s)412allows for input and output of data with other devices that may be connected to computing device400. For example, I/O interface412may provide a connection to external devices418such as a keyboard, keypad, a touch screen, and/or some other suitable input device. External devices418can also include portable computer readable storage media such as, for example, thumb drives, portable optical or magnetic disks, and memory cards. Software and data used to practice embodiments of the present invention, e.g., software and data, can be stored on such portable computer readable storage media and can be loaded onto persistent storage408via I/O interface(s)412. I/O interface(s)412also connect to a display420.