PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF

A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, at least one bridge chip, a photosensitive encapsulation layer, a redistribution layer, and at least two active chips. The conductive pillars and the bridge chip are disposed on the substrate. The photosensitive encapsulation layer surrounds the bridge chip and the conductive pillars, in which a distance between a top surface of the bridge chip and a top surface of the photosensitive encapsulation layer is less than a distance between a top surface of one of the conductive pillars and the top surface of the photosensitive encapsulation layer. The redistribution layer is disposed on the photosensitive encapsulation layer, the active chips are disposed on the redistribution layer, and the bridge chip is coupled between the active chips.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a package device and a manufacturing method thereof and particularly to a package device with a bridge chip coupled to active chips and a manufacturing method thereof.

2. Description of the Prior Art

Recently, in order to integrate various functions to meet usage requirements, it has been developed to encapsulate multiple active chips in the same package device. However, as the active chips need to have more functions or higher computing power, efficiency requirements of an interconnection structure coupled between the active chips become higher. Accordingly, how to improve the interconnection efficiency between active chips and reduce manufacturing cost and process complexity of the package device is an important issue in this field.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a package device is provided and includes a substrate, a plurality of conductive pillars, at least one bridge chip, a photosensitive encapsulation layer, a redistribution layer, at least two active chips, and an encapsulant. The conductive pillars are disposed on the substrate side by side. The bridge chip is disposed on the substrate. The photosensitive encapsulation layer surrounds the bridge chip and the conductive pillars, in which a distance between a top surface of the bridge chip and a top surface of the photosensitive encapsulation layer is less than a distance between a top surface of one of the conductive pillars and the top surface of the photosensitive encapsulation layer. The redistribution layer is disposed on the photosensitive encapsulation layer. The active chips are disposed on the redistribution layer, and the bridge chip is coupled between the active chips. The encapsulant is disposed on the redistribution layer and surrounds the active chips.

According to another embodiment of the present invention, a manufacturing method of a package device is provided. First, a plurality of conductive pillars are formed on a carrier, and at least one bridge chip is disposed on the carrier. Then, a photosensitive encapsulation layer is formed on the conductive pillars and the bridge chip, in which the photosensitive encapsulation layer surrounds the bridge chip and the conductive pillars, and a distance between a top surface of the bridge chip and a top surface of the photosensitive encapsulation layer is less than a distance between a top surface of one of the conductive pillars and the top surface of the photosensitive encapsulation layer. Subsequently, a redistribution layer is formed on the photosensitive encapsulation layer. Then, at least two active chips are disposed on the redistribution layer, and an encapsulant is formed on the redistribution layer, in which the encapsulant surrounds the active chips. Thereafter, the carrier is removed.

DETAILED DESCRIPTION

The contents of the present disclosure will be described in detail with reference to specific embodiments and drawings. In order to make the contents clearer and easier to understand, the following drawings may be simplified schematic diagrams, and elements therein may not be drawn to scale. The numbers and sizes of the elements in the drawings are just illustrative and are not intended to limit the scope of the present disclosure.

Spatially relative terms, such as “above”, “on”, “beneath”, “below”, “under”, “left”, “right”, “before”, “front”, “after”, “behind” and the like, used in the following embodiments just refer to the directions in the drawings and are not intended to limit the present disclosure. It should be understood that the elements in the drawings may be disposed in any kind of formation known by one skilled in the related art to describe the elements in a certain way.

When one element or layer is referred to as “on” or “above” another element or another layer, it may be understood that the element or layer is “directly on” the another element or the another layer, or other element or other layer may be between them. On the contrary, when one element or layer is “directly on” another element or another layer, it may be understood that there is no element or layer between them.

When an element is referred to as being “electrically connected to” or “coupled to” another element, it may be understood that “other element maybe between the element and the another element and electrically connects them to each other”, or “there are no intervening elements present between the element and the another element, and the element and the another element are directly electrically connected to each other”. When an element is referred to as being “directly electrically connected to” or “directly coupled to” another element, there are no intervening elements present between the element and the another element, and the element and the another element are directly electrically connected to each other.

Please refer toFIG.1toFIG.9.FIG.1toFIG.9schematically illustrate a manufacturing method of a package device according to an embodiment of the present invention, in whichFIG.5is a schematic enlarged view of a region R inFIG.4, andFIG.9schematically illustrates a cross-sectional view of the package device according to an embodiment of the present invention. The structures shown inFIG.1toFIG.9may be partial structures in different steps during manufacturing the package device, and some layers or elements may be omitted, but not limited thereto. As shown inFIG.1, a carrier12is provided first, in which the carrier12may for example have a release layer14thereon. The carrier12may be used to carry films or elements formed thereon, and the carrier12may include for example glass, wafer substrate, metal, or other suitable supporting materials, but not limited thereto. The release layer14may be used to separate the carrier12from the elements formed thereon (e.g., a package structure52shown inFIG.7) after subsequent steps are completed. The releasing method of the release layer14may include for example photo dissociation or other suitable methods. The release layer14may, for example, include polyethylene (PE), polyethylene terephthalate (PET), epoxy, oriented polypropylene (OPP) or other materials suitable material, but not limited thereto.

As shown inFIG.1, a plurality of conductive pillars16disposed side by side may be formed on a carrier12. The conductive pillars16may be formed by, for example, a deposition process combined with a photolithography process and an etching process, an electroplating process combined with an etching process, or other suitable processes. In the embodiment ofFIG.1, the conductive pillars16may be, for example, a single-layer structure or a multi-layer structure. The conductive pillars16may, for example, be formed of copper, but not limited thereto. In some embodiments, as shown inFIG.1, a dielectric layer18may be optionally formed on the release layer14before the conductive pillars16are formed. In this case, the conductive pillars16may be formed on the dielectric layer18, and as compared with being formed on the release layer14, bonding between the conductive pillars16and the dielectric layer18may be better. Accordingly, the bonding between the conductive pillars16and the carrier12may be improved by the dielectric layer18, and falling or toppling of the conductive pillars16from the carrier12may be reduced when the conductive pillars16is uprightly disposed on the carrier12. The dielectric layer18may include, for example, polyimide (PI) or other suitable organic materials, but not limited thereto. In some embodiments, the dielectric layer18may have openings, and the conductive pillars16are partially formed in the openings, respectively, such that a part of each conductive pillar16is embedded in the dielectric layer18just like an anchor point, thereby reducing the toppling risk of the conductive pillars16.

As shown inFIG.2, after the conductive pillars16are formed, at least one bridge chip20may be disposed on the carrier12in a face-up manner. In other words, the bridge chip20may have a plurality of pads20pfacing upward, and a back surface20bof the bridge chip20faces toward the carrier12. For example, the step of disposing the bridge chip20may utilize an adhesive layer22to bond the bridge chip20to the release layer14(or the dielectric layer18) through a die attach process. The adhesive layer22may include, for example, a die attach film (DAF), double-sided tape, or other suitable materials. The bridge chip20may include, for example, a plurality of traces for coupling active chips (e.g., active chips44shown inFIG.6) formed in a subsequent process to each other. A trace pitch (e.g., fine pitch) in the bridge chip20may be, for example, 1 micrometer (μm) to 2 micrometers or on sub-micron scale, but not limited thereto. The number of bridge chip20shown inFIG.2may be plural, but not limited thereto. The number of bridge chip20may, for example, depend on the number of active chips in a chip group or the number of chip groups (e.g., chip groups CG shown inFIG.6). In some embodiments, the bridge chip20may optionally further include a passive element, such as a resistor, a capacitor, an inductor, or other similar elements. In some embodiments, the bridge chip20may optionally further include an active element. In some embodiments, a thickness of the bridge chip20in a normal direction ND perpendicular to a top surface12sof the carrier12may be, for example, about 10 micrometers to 100 micrometers or more. The chip mentioned herein may also be referred to as a die but is not limited thereto. The term “coupling” mentioned herein may also be referred to as “electrical connecting”, but not limited thereto.

In the embodiment ofFIG.2, the bridge chip20may have no bump on the pads20p, so that the pads20pmay be exposed. Since it is not necessary to form bumps on the pads20pof the bridge chip20, the manufacturing cost may be reduced. For example, the bridge chip20may include a body portion20mand an insulating layer20n, in which the pads20pmay be disposed on the body portion20m, and the insulating layer20nmay be disposed on the pads20pand has openings OP respectively exposing corresponding pads20p. The pads20pmay, for example, be aluminum pads, but not limited thereto.

In the embodiment shown inFIG.2, a height H1 of one of the conductive pillars16may be, for example, lower than a height H2 of a top surface20sof the bridge chip20opposite to the carrier12(e.g., the height H2 may be a distance between the top surface20sand a surface of the dielectric layer18opposite to the release layer14, or a sum of a thickness of the bridge chip20and a thickness of the adhesive layer22). Accordingly, time and cost for manufacturing the conductive pillars16may be reduced. The top surface20sof the bridge chip20may be formed by, for example, a top surface of the insulating layer20nand top surfaces of the pads20pshown inFIG.2, but not limited thereto. In some embodiments, a distance between two adjacent conductive pillars16may be, for example, greater than a distance between two adjacent pads20p, but not limited thereto.

As shown inFIG.3, a photosensitive encapsulation layer28may then be formed on the conductive pillars16and the bridge chip20. For example, the photosensitive encapsulation layer28may be a dry film and is disposed on the conductive pillars16and the bridge chip20through a lamination process, in which the photosensitive encapsulation layer28may surround the conductive pillars16and the bridge chip20. Then, a plurality of through holes28aand a plurality of through holes28bmay be formed in the photosensitive encapsulation layer28through a photolithography process (i.e., an exposure process and a development process), in which the through holes28amay expose the corresponding conductive pillars16, and the through holes28bmay expose the corresponding pads20pof the bridge chip20. Since the photosensitive encapsulation layer28may extend to tops of the conductive pillars16and a top of the bridge chip20, a distance D3 between the top surface20sof the bridge chip20and a top surface28sof the photosensitive encapsulation layer28opposite to the carrier12may be less than a distance D1 between a top surface16sof one of the conductive pillars16and the top surface28sof the photosensitive encapsulation layer28.

It should be noted that, as compared with general photoresist materials, the photosensitive encapsulation layer28may have a greater thickness. Therefore, when the bridge chip20has a certain thickness (e.g., 10 μm to 100 μm), a thickness T of the photosensitive encapsulation layer28may still be greater than the height H1 of one of the conductive pillars16and the height H2 of the top surface20sof the bridge chip20, such that the top surface28sof the photosensitive encapsulation layer28may be higher than the top surface16sof one of the conductive pillars16and the top surface20sof the bridge chip20. In some embodiments, a depth of one of the through holes28a(i.e., the distance D1 between the top surface16sof one of the conductive pillars16and the top surface28sof the photosensitive encapsulation layer28) may be, for example, greater than a depth D2 of one of the through holes28b(i.e., the distance between the top surface of one of the pads20pand the top surface28sof the photosensitive encapsulation layer28). In some embodiments, a width W1 of one of the through holes28amay be greater than a width W2 of one of the through holes28b, for example. It should be noted that, since the through holes28aexposing the conductive pillars16and the through holes28bexposing the bridge chip20may be formed in the photosensitive encapsulation layer28through the photolithography process, the height H1 of one of the conductive pillars16may be designed to be less than the height H2 of the top surface20sof the bridge chip20, thereby reducing the manufacturing cost.

In addition, the photosensitive encapsulation layer28may not only have the photosensitive property, but also have filling and sealing properties, so that it may be disposed between the conductive pillars16and between the conductive pillars16and the bridge chip20to protect the conductive pillars16and the bridge chip20. For example, the photosensitive encapsulation layer28may include a siloxane polymer (e.g., SINR produced from Shin-Etsu Chemical), or other suitable organic materials. It should be noted that the photosensitive encapsulation layer28may have a lower Young's modulus compared to conventional packaging materials (e.g., epoxy resin or molding material). In other words, the photosensitive encapsulation layer28does not cause significant stress on the conductive pillars16, the bridge chip20and the carrier12, so that warpage of the carrier12may be reduced in the subsequent process. Accordingly, affection to positions of the conductive pillars16and the pads20pof the bridge chip20and relative positions of the subsequently formed elements (e.g., the redistribution layer30shown inFIG.4andFIG.5) by the photosensitive encapsulation layer28maybe mitigated, and the process complexity of the package device may be reduced.

As shown inFIG.4andFIG.5, a redistribution layer30may be formed on the photosensitive encapsulation layer28, so that a part of the photosensitive encapsulation layer28may be disposed between the conductive pillars16and the redistribution layer30and between the bridge chip20and the redistribution layer30. The redistribution layer30may include at least two conductive layers and at least one dielectric layer. In the embodiment ofFIG.5, the conductive layers of the redistribution layer30may include a conductive layer32, a conductive layer34and a conductive layer36, and the dielectric layer of the redistribution layer30may include a dielectric layer38and a dielectric layer40as an example, but not limited thereto. In some embodiments, the number of conductive layers and the number of dielectric layers maybe adjusted according to requirements.

In the embodiment ofFIG.5, the conductive layer32may be disposed on the photosensitive encapsulation layer28and include a plurality of traces32aand a plurality of traces32b, in which the traces32aare respectively coupled to the corresponding conductive pillars16through the corresponding through holes28a, and the traces32bare respectively coupled to the corresponding pads20pof the bridge chip20through the corresponding through holes28b. For example, since the conductive pillars16and the pads20pmay be respectively exposed by the through holes28aand28b, one of the traces32aof the conductive layer32may extend into the corresponding through hole28aand directly contact the corresponding conductive pillar16, and one of the traces32bmay extend into the corresponding through hole28band directly contact the corresponding pad20pof the bridge chip20. For this reason, there is no need to fabricate extra bumps on the pads20pof the bridge chip20for bonding, thereby reducing the thickness of the bridge chip20and the thicknesses of the conductive pillars16. The dielectric layer38may be disposed on the conductive layer32and have a plurality of through holes38aand a plurality of through holes38brespectively exposing parts of the corresponding traces32aand the corresponding traces32b. The conductive layer34maybe disposed on the dielectric layer38and include a plurality of traces34aand a plurality of traces34b. The traces34amay be respectively coupled to the corresponding traces32athrough the corresponding through holes38a, and the traces34bmay be respectively coupled to the corresponding traces32bthrough the corresponding through holes38b. The dielectric layer40may be disposed on the conductive layer34and the dielectric layer38and have a plurality of through holes40aand a plurality of through holes40brespectively exposing parts of the corresponding traces34aand the corresponding traces34b. The conductive layer36may include a plurality of blocks36aand a plurality of blocks36brespectively disposed in the through holes40aand the through holes40b. In some embodiments, the redistribution layer30may optionally further include conductive bumps42aand conductive bumps42brespectively disposed on the corresponding blocks36aand the corresponding blocks36b, so as to facilitate bonding of the redistribution layer36to an element (e.g., the active chip) formed in subsequent process. One of the conductive bumps42aand the conductive bumps42bmay optionally be, for example, a multi-layered structure. The multi-layer structure may include, for example, copper, nickel, gold, other suitable materials, an alloy of at least two thereof, or a combination thereof, but not limited thereto. In some embodiments, the trace pitch (e.g., fine pitch) of the same conductive layer in the redistribution layer30may be, for example, 2 μm to 10 μm.

As shown inFIG.6, at least two active chips44maybe disposed on the redistribution layer30, so that the active chips44may be coupled to the bridge chip20through the redistribution layer30, thereby being coupled to each other. In the embodiment shown inFIG.6, the number of active chips44may be plural, and the active chips44may be divided into at least two chip groups CG respectively corresponding to the package devices to be formed (e.g., the package device shown inFIG.9), but not limited thereto.

In the embodiment ofFIG.6, one of the active chips44may, for example, include a plurality of conductive bumps46to facilitate bonding with the redistribution layer30, but not limited thereto. The conductive bumps46of the active chip44may be bonded to the conductive bumps42aand the conductive bumps42bof the redistribution layer30, for example, in a face-down manner through a flip chip bonding process. Metal solders (not shown), such as tin alloy solders, may be disposed between the conductive bumps46and the conductive bumps42aand between the conductive bumps46and the conductive bumps42b, but not limited thereto. For example, one of the active chips44may further include a body portion44m, a plurality of input/output pads44p, and an insulating layer44n, in which the input/output pads44pmay be disposed between the body portion44mand the insulating layer44n, and the insulating layer44nhas a plurality of openings exposing the corresponding input/output pads44p, respectively. The conductive bumps46may be formed on the corresponding input/output pads44p, respectively. In some embodiments, when the active chip44has a fine pitch of the conductive bumps, a thermal compression bonding may be used to bond the active chips44to the redistribution layer30.

In some embodiments, a distance between two adjacent conductive bumps46of one of the active chips44may be less than or equal to a distance between two adjacent pads (e.g., the pads20pshown inFIG.5) of the bridge chip20. When the distance between the conductive bumps46is equal to the distance between the pads20p, the traces (e.g., the trace32band the trace34bas shown inFIG.5), the block (e.g., one of the blocks36bshown inFIG.5) and one of the conductive bumps42bin the redistribution layer30for coupling one of the conductive bumps46to the corresponding pad20pmay be aligned with each other in the normal direction ND perpendicular to a top surface12sof the carrier12, but not limited thereto. In some embodiments, the distance between two adjacent conductive bumps46maybe less than the distance between two adjacent conductive pillars16.

One of the active chips44may include, for example, a power management integrated circuit (PMIC), a micro-electro-mechanical-system (MEMS) chip, an application-specific integrated circuit (ASIC), a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a high bandwidth memory (HBM) chip, a system on chip (SoC), a high performance computing (HPC) chip or other similar active chips, but not limited thereto. One of the conductive bumps46may, for example, include a multi-layer structure. One of the conductive bumps46may, for example, include copper, nickel, tin, silver, other suitable materials, an alloy of at least two thereof, or a combination thereof, but not limited thereto.

In the embodiment ofFIG.6, the chip group CG may include homogeneous or heterogeneous active chips44aand44b. When the active chip44aand the active chip44bare heterogeneous, the active chip44aand the active chip44bmay be, for example, a system on chip and a high-bandwidth memory chip, respectively, but not limited thereto. For example, one chip group CG may include one active chip44aand four active chips44b, but not limited thereto. As mentioned herein, the active chip44may refer to a chip including an active element, in which the active element may include a transistor, a diode, an integrated circuit, an optoelectronic element, or other suitable elements with gain, but not limited thereto. In some embodiments, when the bridge chip20includes the active elements, the active elements in the bridge chip20and the active elements in the active chip44may be fabricated from different semiconductor process technology nodes, for example, a density of the active elements in the bridge chip20may be less than a density of the active elements in the active chip44, but not limited thereto.

In some embodiments, since the redistribution layer30may be formed before the active chips44is disposed, an automated optical inspection (AOI) and/or an open/short test (O/S test) may be optionally performed on the redistribution layer30before the active chips44are disposed to ensure the quality of the redistribution layer30, so that chip loss or waste caused by defect of the redistribution layer30may be avoided. In some embodiments, the automated optical inspection and/or the open/short test may be performed after the redistribution layer30is completed or may be repeated multiple times during the step of forming the redistribution layer30.

In some embodiments, as shown inFIG.6, after the active chips44are disposed on the redistribution layer30, an underfill layer48may be optionally filled between the active chips44and the redistribution layer30to strengthen the bonding between the active chips44and the redistribution layer30, thereby reducing breaks between the conductive bumps42aand the conductive bumps46and between the conductive bumps42band the conductive bumps46. The underfill layer48may include, for example, capillary underfill (CUF) or other suitable filling materials, but not limited thereto. The underfill layer48maybe formed by, for example, a dispensing process, but not limited thereto.

As shown inFIG.7, after the active chips44are disposed, an encapsulant50may be formed on the redistribution layer30, and the encapsulant50may surround the active chips44for protecting the active chips44. Specifically, the encapsulant50may be formed between the active chips44and on back surfaces of the active chips44, for example, through a molding process. The encapsulant50may include, for example, a molding compound or other suitable encapsulating material, but not limited thereto. A Young's modulus of the encapsulant50may be greater than a Young's modulus of the photosensitive encapsulation layer28.

In the embodiment shown inFIG.7, a thinning process may be optionally performed on the encapsulant50to remove a part of the encapsulant50located on the active chips44, so as to expose the back surfaces of the active chips44, thereby facilitating heat dissipation of the active chips44. The thinning process may include, for example, a chemical mechanical polishing (CMP) process, a mechanical grinding process, an etching process or other suitable processes, but not limited thereto.

As shown inFIG.8, after the encapsulant50is formed, the carrier12maybe removed from the conductive pillars16, the adhesive layer22and the photosensitive encapsulation layer28to expose surfaces of the conductive pillars16, the adhesive layer22and the photosensitive encapsulation layer28opposite to the redistribution layer30. The method of removing the carrier12may include, for example, irradiating the release layer14with light to reduce the adhesion of the release layer14, thereby removing the carrier12, but not limited thereto. Then, a semi-finished structure52including the encapsulant50, the active chips44, the redistribution layer30, the conductive pillars16, the photosensitive encapsulation layer28and the bridge chip20may be turned upside down, so that the back surface20bof the bridge chip20faces upward, and the back surfaces of the active chips44face downward. Subsequently, a conductive terminal54is formed on each of the conductive pillars16. The conductive terminals54may be formed, for example, by electroplating, deposition, ball mounting, reflow, and/or other suitable processes. The conductive terminal54may include, for example, a solder ball, a conductive bump, or other suitable conductive terminals. The solder ball may include tin ball, for example. The conductive bump may, for example, include a multi-layer structure. The conductive bump may include, for example, copper, nickel, tin, silver, other suitable materials, an alloy of at least two thereof, or a combination thereof, but not limited thereto.

As shown inFIG.8, a singulation process may be performed on the semi-finished structure52to form at least one package structure56. In the embodiment ofFIG.8, the semi-finished structure52may include at least two chip groups CG, so the singulation process may separate different chip groups CG from each other and separate bridge chips20and the conductive pillars16corresponding to different chip groups CG from each other to format least two package structures56. The singulation process may, for example, include a cutting process or other suitable processes. In some embodiments, order of the step of forming the conductive terminals54and the step of performing the singulation process may be interchanged with each other.

As shown inFIG.9, after the conductive terminals54are formed, the package structure56may be turned upside down, and the conductive terminals54of the package structure56may be disposed on a substrate58. The conductive pillars16of the package structure56may be bonded and coupled to the substrate58through the conductive terminals54. Then, an underfill layer60may be formed between the photosensitive encapsulation layer28of the packaging structure56and the substrate58to form a package device1. The substrate58may include, for example, a package substrate, a circuit board, or other suitable substrate. The package structure56may be bonded and coupled to the substrate58through the conductive terminals54. The underfill layer60may extend to sidewalls of the photosensitive encapsulation layer28and the encapsulant50of the package structure56, thereby strengthening the bonding between the package structure56and the substrate58. The material and forming method of the underfill layer60may be, for example, the same as or similar to those of the underfill layer48and will not be detailed redundantly.

In some embodiments, a stiffener62may be disposed on the substrate58, and the stiffener62may, for example, surround the package structure56and be spaced apart from the underfill layer60. The stiffener62may, for example, include metal. In some embodiments, solder balls64may be optionally disposed under the substrate58to facilitate coupling and bonding of the package device1with other elements, but not limited thereto.

In the package device1shown inFIG.9, since the trace pitch of the bridge chip20may be less than the trace pitch of the redistribution layer30, the interconnection density between the active chips44may be improved by the bridge chip20coupled to different active chips44. Accordingly, signal transmission path or time between the active chips44maybe decreased, thereby improving signal transmission efficiency. In this case, the trace pitch of the redistribution layer30does not need to reach a fine pitch, so as to simplify the process complexity and reduce the manufacturing cost. In addition, the number of layers of the redistribution layer30may be reduced by the bridge chip20with less trace pitch, thereby reducing the warpage of the package structure56and increasing bonding yield of the package structure56to the pads of the substrate58.

Furthermore, since the adhesive layer22is disposed on the back surface20bof the bridge chip20, when the package structure56is disposed on the substrate58, the adhesive layer22may protect the bridge chip20and reduce crack or disconnection in the bridge chip20. Through the protection of the adhesive layer22, the thickness of the bridge chip20in the normal direction (e.g., the normal direction ND perpendicular to a top surface of the substrate58) may be further thinned without crack or disconnection, thereby reducing overall thickness of the package device1in the normal direction ND. In this case, the height of the conductive pillar16(e.g., the height H1 shown inFIG.2) may be further decreased, thereby reducing the manufacturing time and cost. In addition, the pitch of the conductive pillars16may be reduced to provide higher signal output density and/or reduce a size of the package device1.

It should be noted that, in the package device1, since the redistribution layer30is disposed between the active chips44and the conductive pillars16and between the active chips44and the bridge chip20, the active chips44may be coupled to the conductive pillars and the pads (e.g., the pads20pshown inFIG.5) of the bridge chip20with different pitches through the redistribution layer30. In addition, the active chips44may be coupled to the substrate58through the redistribution layer30and the conductive pillars16, and as compared with being coupled to the substrate58through a silicon interposer, the manufacturing cost of the conductive pillars16may be significantly lower than that of the silicon interposer. Therefore, the manufacturing cost of the package device1may be effectively reduced.

FIG.10schematically illustrates a cross-sectional view of a package device according to another embodiment of the present invention. As shown inFIG.10, the package device2of this embodiment differs from the package device1shown inFIG.9in that the package device2may further include a metal cover66instead of the stiffener62inFIG.9, and the metal cover66is disposed on the package structure56and the substrate58. The metal cover66may, for example, cover and surround the package structure56to protect the package structure56. The metal cover66may be, for example, an integrally formed structure, but not limited thereto. In some embodiments, the package device2may optionally further include a thermal grease68disposed on the back surfaces of the active chips44. The thermal grease68may, for example, directly contact the active chips44and the metal cover66to facilitate heat dissipation of the active chips44. The thermal grease68may be coated on the back surfaces of the active chips44, for example, before disposing the metal cover66, but not limited thereto.

In summary, in the package device of the present invention, the bridge chip that coupled to different active chips may improve the interconnection density between the active chips, thereby increasing the signal transmission efficiency. In addition, since the adhesive layer may be disposed on the back surface of the bridge chip, when the bridge chip is disposed on the substrate, the adhesive layer may protect the bridge chip to reduce crack or disconnection of the bridge chip. In addition, the redistribution layer may be disposed between the active chips and the conductive pillars and between the active chips and the bridge chip, so that the active chips may be coupled to the conductive pillars and the pads of the bridge chip with different pitches through the redistribution layer and may be coupled to the substrate through the conductive pillars, thereby reducing the manufacturing cost of the package device.