Enabling thermal efficiency on a silicon-on-insulator (SOI) platform

A method for fabricating a photonic integrated circuit (PIC) comprises providing a silicon-on-insulator (SOI) wafer comprising an insulator layer disposed between a base semiconductor layer and a SOI layer, wherein the SOI layer comprises a waveguide, providing at least one slot within the SOI layer, wherein the at least one slot is positioned on the same or opposite sides of the waveguide, and wherein the at least one slot is positioned at a predetermined distance away from the waveguide, and removing a portion of the insulator layer to form an etched-out portion of the insulator layer, wherein the etched-out portion is positioned directly beneath the waveguide, and wherein a width of the etched-out portion is at least the width of the waveguide.

CROSS-REFERENCE TO RELATED APPLICATIONS

Not applicable.

Not applicable.

REFERENCE TO A MICROFICHE APPENDIX

Not applicable.

BACKGROUND

Optical fibers have been widely used for the propagation of optical signals, especially to provide high-speed communication links. Optical links using fiber optics comprise various advantages over electrical links, for example, comparatively large bandwidths, high noise immunity, reduced power dissipation, and minimal crosstalk. Optical signals carried by optical fibers may be processed by a wide variety of optical and/or optoelectronic devices, including integrated circuits.

Photonic integrated circuits (PICs) comprising waveguides are used as optical components in constructing an optical system. In order for a PIC to function as an optical component in an optical system, optical fibers are connected to waveguides formed on the PIC. Thus, photonic integration, or light coupling between optical fibers and waveguides formed on PICs, is becoming increasingly important in optical systems.

SUMMARY

According to one aspect of the present disclosure, there is provided a method for fabricating a photonic integrated circuit (PIC). The method comprises providing a silicon-on-insulator (SOI) wafer comprising an insulator layer disposed between a base semiconductor layer and a SOI layer, wherein the SOI layer comprises a waveguide, providing at least one slot within the SOI layer, wherein the at least one slot is positioned proximate to the waveguide, and wherein the at least one slot is positioned at a predetermined distance away from the waveguide, and removing a portion of the insulator layer to form an etched-out portion of the insulator layer, wherein the etched-out portion is positioned directly beneath the waveguide, and wherein a width of the etched-out portion is at least the width of the waveguide.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the at least one slot is parallel to the waveguide.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the method further comprises providing two outer slots into the SOI layer and the insulator layer, and wherein a first outer slot and a second outer slot are positioned at a second predetermined distance away from the waveguide.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the method further comprises depositing a polysilicon layer on top of the SOI layer and into a first outer slot and a second outer slot, wherein a cladding layer is disposed between the waveguide and the polysilicon layer.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the method further comprises etching out portions of the SOI layer around the waveguide.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the method further comprises depositing a cladding layer on top of the SOI layer, and depositing a polysilicon layer on top of the cladding layer.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that wherein the portion of the insulator layer is removed to form the etched-out portion using a buffered oxide etch (BOE).

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the at least one slot extends vertically from a top surface of the SOI wafer to a top surface of the insulator layer.

According to one aspect of the present disclosure, there is provided a PIC prepared by a process comprising the steps of providing a silicon-on-insulator (SOI) wafer comprising an insulator layer disposed between a base semiconductor layer and a SOI layer, wherein the SOI layer comprises a waveguide, providing at least one slot within the SOI layer, wherein the at least one slot is positioned proximate to the waveguide, and wherein the at least one slot is positioned at a predetermined distance away from the waveguide, and removing a portion of the insulator layer to form an etched-out portion of the insulator layer, wherein the etched-out portion is positioned directly beneath the waveguide, and wherein a width of the etched-out portion is at least the width of the waveguide.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the at least one slot is formed by reactive-ion etching (RIE).

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the process further comprises providing two outer slots into the SOI layer and the insulator layer, and wherein a first outer slot and a second outer slot are positioned at a second predetermined distance away from the waveguide.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the process further comprises depositing a polysilicon layer on top of the SOI layer and into the first outer slot and the second outer slot, wherein a cladding layer is disposed between the waveguide and the polysilicon layer.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the portion of the insulator layer is removed to form the etched-out portion using a buffered oxide etchant (BOE).

Optionally, in any of the preceding aspects, another implementation of the aspect provides that wherein the etched-out portion comprises a vacuum by which heat is unable to pass.

According to one aspect of the present disclosure, there is provided a PIC to be used in an optical device, comprising a base semiconductor layer, an insulator layer disposed on top of the base semiconductor layer, a silicon-on-insulator (SOI) layer comprising a waveguide and disposed on top of the insulator layer, wherein a waveguide is disposed on the SOI layer, and wherein the insulator layer comprises an etched-out portion, wherein the etched-out portion is positioned directly beneath the waveguide, and wherein a width of the etched-out portion is at least the width of the waveguide.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the PIC further comprises a cladding layer disposed on top of the SOI layer, and a heater disposed on top of the cladding layer, wherein a current is passed through the heater to provide heat to the waveguide.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the SOI layer comprises a slot proximate to the waveguide.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the SOI layer comprises two slots on either side of the waveguide.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the etched-out portion comprises a vacuum by which heat is unable to pass.

Optionally, in any of the preceding aspects, another implementation of the aspect provides that the PIC further comprises two outer slots into the SOI layer and the insulator layer, wherein a first outer slot and a second outer slot are positioned outside the first outer slot and the second outer slot relative to the waveguide, and wherein the first outer slot and the second outer slot are positioned at a second predetermined distance away from the waveguide.

DETAILED DESCRIPTION

A PIC may be part of an optical modulator that receives light via an optical fiber. Typical PICs include a SOI wafer comprising a buried oxide (BOX) layer disposed between a SOI layer and a base silicon layer. The SOI layer may include two parallel waveguides disposed a distance from each other, where each parallel waveguide carries a part of the light received. In PICs, there is a need to adjust the phase of the light propagating on one waveguide relative to the phase of the light propagating on the other waveguide. The phase may be adjusted by heating one of the waveguides locally using an on-chip resistive heater.

However, generating the amount of heat necessary to adjust the phase of the light propagating on one of the waveguides requires an excessive amount of power, about 10s-100s of milliwatts. In addition, the heat generated by the resistive heater typically dissipates down through all layers of the PIC relatively quickly and easily, instead of staying within the waveguide for a sufficient amount of time to change the phase of the light. Therefore, embodiments of the present disclosure enable PICs to increase thermal resistance within the waveguide by removing a portion of the BOX layer directly under the waveguide being heated.

FIG. 1is a cross sectional view of a portion of a SOI wafer100included in a PIC. As defined by the legend150, the z-axis is along an optical propagation axis of the waveguide114. The x-axis is substantially parallel to a plane of the SOI wafer100. The y-axis is substantially perpendicular to the plane of the SOI wafer100.

The SOI wafer100comprises a base semiconductor layer103, an insulator layer106, a SOI layer109, and a cladding layer111. The insulator layer106is disposed between the SOI layer109and the base semiconductor layer103. The cladding layer111is disposed on top of the SOI layer109.

The base semiconductor layer103may be a semiconductor substrate formed from silicon, a silicon-containing material, or another suitable substrate material. The bottom portion129of the SOI wafer100may be the bottom edge of the base semiconductor layer103. The insulator layer106, also referred to as the BOX layer, may be formed from silicon dioxide or another suitable insulator. In an embodiment, the insulator layer106may have a height of about 2-3 micrometers (μm).

The SOI layer109may be formed from silicon or another suitable semiconductor material. In an embodiment, the SOI layer109may have a height of 0.2 μm. The SOI layer109is used for forming waveguides and any other optical functions. For example, the SOI layer109includes a waveguide114. The waveguide114may be formed by, for example, etching away portions117A and117B of the SOI layer109. In an embodiment, the waveguide114defines sidewalls120. While the sidewalls120of the SOI layer109are depicted as vertical inFIG. 1, it should be appreciated that the sidewalls120may be slightly rounded or sloped due to the semiconductor fabrication process.

The SOI layer109may be patterned using photolithography and etched using a dry etching process such as reactive-ion etching (RIE). Photolithography is a process that uses light to transfer a geometric pattern from a photo mask to a light-sensitive chemical photoresist (PR) coating on a substrate, such as the SOI layer109. RIE is a type of dry etching that uses chemically reactive plasma to remove material deposited on a wafer substrate such as the SOI layer109. For example, a first photo mask (not shown) is generated with a first pattern that defines the waveguide114aligning to the z-axis. The photolithography process transfers the first pattern onto the SOI layer109. The RIE process removes the portions117A and117B of the SOI layer109according to the transferred first pattern to form the waveguide114.

The cladding layer111may be formed of a material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) or another suitable material. The cladding layer111is disposed over the SOI layer109and the waveguide114. The deposition of the cladding layer111is performed in one or more steps to provide a flat surface for the SOI wafer100. The cladding layer111may be disposed only over a portion of the SOI layer109such that the waveguide114is covered by the cladding layer111.

Other functional layers may be formed on top of the cladding layer111. As shown inFIG. 1, a resistive heater123may be disposed on top of the cladding layer111. The resistive heater123may be a resistor formed of low resistive material, such as, for example, metal (such as a Titanium Tungsten (TiW) alloy), conductive ceramic (such as a Titanium Nitride (TiN) or a Tantalum Nitride (TaN)) or doped silicon material. While the resistive heater123is disposed on top of the cladding layer111inFIG. 1, it should be appreciated that the resistive heater123may also be placed on the side of the SOI wafer100.

In operation, the PIC including the SOI wafer100may receive light from an external optical fiber (not shown) and split the light into at least two light beams. One of these light beams may pass along waveguide114and the other light beam may pass along another reference waveguide (not shown) disposed on the SOI wafer100. In optical modulation, the phase of one of these light beams needs to be adjusted relative to the phase of the other light beam before both of these light beams can be recombined.

The resistive heater123may be used to adjust the phase of the light beam propagating along waveguide114by providing heat to the SOI wafer100. For example, a current may be applied to the resistive heater123to generate heat which is passed through the cladding layer111and then to the waveguide114.

However, in typical PICS including SOI wafers100, the heat does not remain in the waveguide114long enough to change the phase of the light beam propagating on waveguide114without requiring a large amount of power being applied to the resistive heater123. This may be because the heat generated by the resistive heater123dissipates from the waveguide114vertically downwards in the y-axis through the insulator layer106and the base semiconductor layer103to the bottom portion129, as shown by arrow126. Embodiments of the present disclosure provide a SOI wafer100that is configured to provide thermal efficiency at the waveguide114by removing a portion of the insulator layer106below the waveguide114.

FIG. 2is a cross sectional view of a portion of a SOI wafer200that enables thermal efficiency according to an embodiment of the disclosure. As shown inFIG. 2, SOI wafer200is similar to SOI wafer100, except that SOI wafer200includes an etched-out portion203, slots206and207, and a polysilicon layer215. Otherwise, SOI wafer200also includes a base semiconductor layer103, an insulator layer106, a SOI layer109, and one or more cladding layers111. For example, SOI wafer200is a cross sectional view of a portion of the SOI wafer100after patterning and etching to remove the etched-out portion203and the slots206and207.

The polysilicon layer215is disposed on top of the SOI layer109or the cladding layer111. The cladding layer111acts as a buffer between the SOI layer109and the polysilicon layer215, and the cladding layer111sits between various sections of the polysilicon layer215. In this way, the cladding layer111may be deposited on top of the SOI layer109, and the polysilicon layer215may be deposited on top of the cladding layer111. The polysilicon layer215may be configured to further minimize optical absorption and may be formed of a polysilicon or Silicon Nitride.

In an embodiment, the slots206and207may be holes or apertures that are patterned into the polysilicon layer215, the SOI layer109, and slightly into the insulator layer106to facilitate removing a portion of the insulator layer106. The slots206and207extend vertically along the y-axis from the top surface of the SOI wafer200to the top surface of the insulator layer106. The slots206and207may be positioned within the polysilicon layer215and the SOI layer109on either side of the waveguide114. The slots206and207may comprise vertical sidewalls213, respectively, along the y-axis that are perpendicular to the plane of the SOI wafer200.

As shown inFIG. 2, the slots206and207are positioned a predefined distance from the waveguide114and do not abut against the waveguide114. In an embodiment, the slots206and207are placed an equal distance from the waveguide114and on either side of the waveguide114. In an embodiment, the slots206and207may be placed at different distances from the waveguide114. In an embodiment, the slots206and207are positioned in a manner to facilitate etching out the portion of the insulator layer106from directly under the waveguide114.

WhileFIG. 2shows that slots206and207are positioned on either side of the waveguide114, slots206and206may be patterned anywhere proximate to the waveguide114. For example, slots206and207do not need to placed equidistance from the waveguide114. In some embodiments, slots206and207may be positioned at different distances from the waveguide114. In some embodiments, slots207and207may both be positioned on the same side of the waveguide114.

In some embodiments, only a single slot206or207may be patterned into the polysilicon layer215, the SOI layer109, and slightly into the insulator layer106. This single slot206or207may be proximate to the waveguide114such that the slot206or207may be used to remove a portion of the insulator layer106. In one embodiment, the slots206or207may propagate, or extend, parallel and in the same direction as the waveguide114.

In some embodiments, the diameter260of the slots206and207may be wide enough so that dry etch radicals may reach the insulator layer106and so that the reaction by-product may leave through the slots206and207. The diameter260of the slots206and207may also be wide enough so that the slots206and207may be resealed by an oxide deposition. For example, the diameter260of the slots206and207in the x-axis is about 500 nanometers (nm). In some embodiments, the height261of the slots206and207may be substantially equivalent to the height of the polysilicon layer215and the SOI layer109.

In an embodiment, a portion of the insulator layer106is removed from the SOI wafer200to create the etched-out portion203. In an embodiment, the portion of the insulator layer106that is removed is directly below the waveguide114. The etched-out portion203is a void, aperture, or vacuum within the insulator layer106. For example, the portion of the insulator layer106is removed using, for example, a buffered oxide etch (BOE), which is applied through the slots206and207. BOE is a wet etchant used in microfabrication to etch the oxide within the portion of the insulator layer106below the waveguide114.

In an embodiment, a height219of the portion of the insulator layer106that is removed in the y-axis, and thus the height219of the etched-out portion203, is equal to the height of the insulator layer106. The height219of the etched-out portion203extends from the bottom edge of the SOI layer109to the top edge of the base semiconductor layer103. The depth218of the portion of the insulator layer106that is removed in the z-axis, and thus the depth218of the etched-out portion203, may be greater than or equal to the depth of the waveguide114. In an embodiment, a width220of portion of the insulator layer106that is removed along the x-axis, and thus the width220of the etched-out portion203, may be greater than or equal to the width225of the waveguide114.

As shown inFIG. 2, the width220of the etched-out portion203, and thus also the portion of the insulator layer106that is removed, may be slightly wider than the width225of the waveguide114. Similarly, the depth218of the etched-out portion203, and thus also the portion of the insulator layer106that is removed, may also be slightly larger than the depth of the waveguide114. The height219of the etched-out portion203, and thus also the portion of the insulator layer106that is removed, may be substantially equal to the height of the insulator layer106. In some embodiments, the width220and the depth218of the etched-out portion203may be any width and depth, respectively, as long as the etched-out portion203is disposed below the waveguide114such that the waveguide114is positioned in the center of the etched-out portion203. In some embodiments, the width220of the etched-out portion203may not be wide enough to extend below another waveguide disposed on the SOI layer109. Similarly, the depth218of the etched-out portion203may not be deep enough to extend below another waveguide disposed on the SOI layer109.

The etched-out portion203may create a vacuum which is substantially gasless. Therefore, heat is substantially incapable of passing through the etched-out portion203of the SOI wafer200or resistance to the heat passage through the etched-out portion203is significantly increased. In one embodiment, the vacuum may be a reduced pressure gas environment such as a nitrogen environment. The SOI wafer200including the etched-out portion203is thermally efficient relative to the waveguide114. This is because when the resistive heater123applies heat to the SOI wafer200and the heat travels vertically downwards in the y-axis, the heat that would normally transfer from the waveguide114into the insulator layer106can no longer do so because of the positioning of the etched-out portion203. That is, heat cannot easily dissipate from the waveguide114into the insulator layer106in the SOI wafer200because the etched-out portion203is positioned directly below the waveguide114and the etched-out portion203may not receive heat. In this way, the waveguide114in SOI wafer200may retain more heat without the need to use as much power to initiate the resistive heater123.

FIGS. 3A-3Ccollectively illustrate an embodiment of a method of fabricating of a portion of a SOI wafer300included in a PIC according to an embodiment of the disclosure. For illustration purposes, the method shown inFIGS. 3A-3Cillustrates the fabrication of a single etched-out portion203under a single waveguide114. However, the method shown inFIGS. 3A-3Cis suitable for fabricating any number of etched-out portions203under different waveguides114.

FIG. 3Ais a cross sectional view of a portion of the SOI wafer300according to an embodiment of the disclosure that shows the first step of fabricating of a portion of a SOI wafer300. SOI wafer300is similar to SOI wafer200, except that SOI300additionally includes a PR coating303. The PR coating303is disposed on top of the polysilicon layer215to include a pattern that defines the waveguide114and the slots206and207. As shown inFIG. 3A, the slots206and207are also positioned within the PR coating303. The slots206and207shown inFIG. 3Aare formed using, for example, a dry etch process, such as RIE, that etches the slots206and207through the bottom edge306of the PR coating303.

FIG. 3Bis the cross sectional view of the portion of a SOI wafer300according to an embodiment of the disclosure after the slots206and207are formed through the PR coating303. InFIG. 3B, the slots206and207are extended down into the polysilicon layer215and the SOI layer109. For example, the slots206and207shown inFIG. 3Bare extended downward in the y-axis using a dry etch process, such as RIE, that etches the slots206and207through the polysilicon layer215and the SOI layer109. In an embodiment, the slots206and207are extended down to the top edge309of the insulator layer106to facilitate removal of the portion of the insulator layer106.

FIG. 3Cis the cross sectional view of the portion of a SOI wafer300according to an embodiment of the disclosure after the slots206and207are formed through the PR coating303, polysilicon layer215, and SOI layer109. InFIG. 3C, a bottom edge330of the slot206and a bottom edge330of the slot207may abut against the top edge309of the insulator layer106to facilitate removal of the etched-out portion203. For example, the portion of the insulator layer106may be removed via the slots206and207using a wet etching process, such as BOE. It should be appreciated that any etchant may be used to remove the portion of the insulator layer106to create the etched-out portion203so long as the etchant does not remove any portion of the base semiconductor layer103or the SOI layer109.

FIG. 4is a cross sectional view of a portion of a SOI wafer400that enables thermal efficiency according to another embodiment of the disclosure. For example, SOI wafer400is a cross sectional view of a portion of the SOI wafer100after patterning and etching to remove the etched-out portion203, the slots206and207, and the outer slots406and407. The SOI wafer400is similar to SOI wafer200in that SOI wafer400includes the base semiconductor layer103, the insulator layer106, the SOI layer109, the polysilicon layer215, and various cladding layers111. The SOI wafer400also includes the etched-out portion203. For example, the waveguide114is covered by a cladding layer111of a certain thickness such that the optical mode residing in the waveguide114is not disturbed by the polysilicon layer215. Unlike SOI wafer200, the SOI wafer400includes an enclosure403, which may be formed using the outer slots406and407.

In an embodiment, the outer slots406and407are similar to the slots206and207in that the outer slots406and407are holes or apertures that are patterned into the SOI layer109. However, unlike the slots206and207, the outer slots406and407are etched all the way down to the bottom edge of the insulator layer106or a top edge450of the base semiconductor layer103. As shown inFIG. 4, outer slots406and407have sidewalls408which extend vertically along the y-axis from the top surface of the SOI wafer400to the bottom surface of the insulator layer106or a top edge450of the base semiconductor layer103. The bottom edge409of outer slot406abuts a top edge450of the base semiconductor layer103. Similarly, the bottom edge409of the outer slot407abuts a top edge450of the base semiconductor layer103.

As shown inFIG. 4, the outer slots406and407are positioned a predefined distance from the waveguide114and the slots206and207. In an embodiment, the outer slots406and407are placed an equal distance from the waveguide114and on either side of the waveguide114. In this embodiment, the outer slot406may be placed a predefined distance from the slot206away from the waveguide114. Similarly, the outer slot407may be placed a predefined distance from the slot207away from the waveguide114. In an embodiment, the slots206and207are positioned in a manner to facilitate enclosing the etched-out portion203such that a wet etchant used to etch out the portion of the insulator layer106does not etch out any portion of the insulator layer106that extends beyond the outer slots406and407.

In some embodiments, the diameter460of the outer slots406and407may be wide enough so that dry etch radicals may reach the base semiconductor layer103and so that the reaction by-product may leave through the outer slots406and407. The diameter460of the outer slots406and407may also be wide enough so that the outer slots406and407may be resealed by an oxide deposition. For example, the diameter460of the outer slots406and407in the x-axis is about 500 nm. In some embodiments, the height465of the outer slots406and407may be substantially equivalent to the height of the polysilicon layer215, the SOI layer109, and the insulator layer106.

In an embodiment, the outer slots406and407are formed of the polysilicon layer215. For example, the polysilicon material forming the polysilicon layer215may be deposited into the outer slots406and407after the outer slots406and407have been etched-out of the SOI layer109and the insulator layer106. As shown inFIG. 4, a thin cladding layer111may also be present in between two polysilicon layers215in the outer slots406and407.

In an embodiment, the enclosure403includes the etched-out portion203, which is enclosed by the polysilicon layer215present in the outer slots406and407. In this way, the enclosure403at least partially encloses the area of the insulator layer106directly under the waveguide114. In an embodiment, the enclosure403is provided using the outer slots406and407before removing the portion of the insulator layer106to create the etched-out portion203. This is because the enclosure403creates a boundary that may be used by the wet etchant to remove the portion of the insulator layer106under the waveguide114to create the etched-out portion203. In this way, the wet etchant may be prevented by the enclosure403, or the polysilicon layer215filled outer slots406and407, from spilling over into outer areas of the insulator layer106and removing unnecessary portions of the insulator layer106. For example, the insulator layer106should be etched-out carefully to ensure that portions of the insulator layer106that are under other waveguides should not be removed. In this case, it may be beneficial to use the SOI wafer400to facilitate blocking the wet etchant from removing those portions of the insulator layer106that are used for other components of the PIC.

FIGS. 5A-5Ccollectively illustrate another method for fabricating a PIC with an SOI wafer400. For illustration purposes, the method shown inFIGS. 5A-5Cillustrates the fabrication of a single etched-out portion203under a single waveguide114having a single enclosure403. However, the method shown inFIGS. 5A-5Cis suitable for fabricating any number of etched-out portions203under different waveguides114, each having a different enclosure403.

FIG. 5Ais a cross-sectional view of a portion of the SOI wafer400according to an embodiment of the disclosure showing the first step of fabricating a PIC with an SOI wafer400. As shown inFIG. 5A, the outer slots406and407are positioned within the SOI layer109and the insulator layer106. For example, the outer slots406and407may be formed using a dry etch process, such as RIE, that etches the outer slots406and407through the SOI layer109and the insulator layer106. Unlike the slots206and207, the outer slots406and407extend down to the bottom edge of the insulator layer106to reach a top edge450of the base semiconductor layer103.

FIG. 5Bis a cross-sectional view of a portion of the SOI wafer400according to an embodiment of the disclosure after etching the outer slots406and407into the SOI wafer400. As shown in FIB.5B, the polysilicon layer215is deposited on top of the SOI layer109and cladding layers111. In an embodiment, the cladding layer111may separate the waveguide114from the polysilicon layer215. As shown inFIG. 5B, the polysilicon layer215is also deposited into the outer slots406and407. After the polysilicon layer215is deposited into the outer slots406and407, the enclosure403is formed.

FIG. 5Cis a cross-sectional view of a portion of the SOI wafer400according to an embodiment of the disclosure after etching the enclosure403is formed in the SOI wafer400. The slots206and207are also formed into the polysilicon layer215and SOI layer109. For example, the slots206and207may be formed using a dry etch process, such as RIE, that etches the slots206and207through the polysilicon layer215and the SOI layer109. In an embodiment, the slots206and207are extended down to the surface of the insulator layer106to facilitate removal of the portion of the insulator layer106.

As shown inFIG. 5C, the portion of the insulator layer106that is enclosed within the enclosure403is removed to form the etched-out portion of the SOI wafer400. For example, the portion of the insulator layer106may be removed via the slots206and207using a wet etching process, such as BOE. In this embodiment, the wet etching process is performed more accurately due to the enclosure403, which prevents the wet etchant from removing any part of the insulator layer106that extends outside of the enclosure403or beyond the outer slots406and407. This is because the wet etchant, such as BOE, has a high selectivity and may only etch oxides present in the insulator layer106. That is, the wet etchant may not be able to etch the polysilicon material in the polysilicon layer215present in the outer slots406and407. It should be appreciated that any etchant may be used to remove the portion of the insulator layer106to create the etched-out portion203so long as the etchant does not remove any portion of the base semiconductor layer103or the SOI layer109.

FIG. 6is a flowchart of a method600for fabricating an SOI wafer on a PIC according to various embodiments of the disclosure. The SOI wafer may be any one of SOI wafers200or400. The method600may be implemented by a semiconductor manufacturer that is capable of manufacturing SOI PICs. The method600is implemented during fabrication of the SOI wafers disclosed herein.

At step603, an SOI wafer is provided for fabrication. The SOI wafer may include an insulator layer106positioned between a base semiconductor layer103and a SOI layer109. In an embodiment, the SOI layer109may comprise a waveguide114, which is formed by etching out portions117A and117B of the SOI layer109around the waveguide114.

At step606, two slots206and207are provided within the SOI layer109. For example, the slots206and207may be provided using the dry etching process, as described above with reference toFIGS. 3A-3C. In an embodiment, the first slot206and the second slot207are positioned on opposite sides of the waveguide114. In an embodiment, the first slot206and second slot207are posited at a predetermined distance away from the waveguide114. In an embodiment, the first slot and the second slot extend vertically from a top surface of the SOI wafer to a top surface of the insulator layer106.

At step609, a portion of the insulator layer106is removed to form the etched-out portion203of the insulator layer106. In an embodiment, the portion of the insulator layer106is removed using a wet etching process, as described above with reference toFIGS. 3A-3C. In an embodiment, the etched-out portion203is positioned directly beneath the waveguide114. In an embodiment, a width of the etched-out portion203is at least the width of the waveguide114.

In some embodiments, the method600may further include a step between step606and step609in which two outer slots406and407are provided into the SOI layer109and the insulator layer106. As described above with reference toFIGS. 4A-4C, the two outer slots406and407may be formed using a dry etching process. In an embodiment, the two outer slots406and407may be positioned outside the slots206and207relative to the waveguide114. In an embodiment, a polysilicon layer215may be deposited on top of the SOI layer109and the polysilicon layer215may be deposited into the outer slots406and407to form the enclosure403.

FIG. 7is a top view of a portion of a SOI wafer700that enables thermal efficiency according to an embodiment of the disclosure. As defined by the legend150, the z-axis is along an optical propagation axis of the waveguide114. The x-axis is substantially parallel to a plane of the SOI wafer700. The y-axis is substantially perpendicular to the plane of the SOI wafer700. The SOI wafer700may be the SOI wafer200or the SOI wafer400according to various embodiments of the disclosure.

As shown inFIG. 7, the slots206and207are not continuous along the z-axis, while the waveguide114is continuous along the z-axis. For example, portion703of the SOI wafer700may not include a slot, and therefore, the insulator layer106underneath portion703may not be etched-out. In this way, the etched-out portion203may be subdivided into various sections based on where the slots206and207are positioned. For example, the etched-out portion203may be subdivided into two sections in the portion of the SOI wafer700, the first section corresponding to the first set of slots706, and the second section corresponding to the second set of slots709. The portion703of the SOI wafer700without the slots may provide a mechanical support to the suspended structure.

FIG. 8is a top view of a portion of a SOI wafer800that enables thermal efficiency according to an embodiment of the disclosure. The SOI wafer800is similar to the SOI wafer200,400, and700, except that the SOI wafer800includes a curved waveguide114. In the embodiment in which the waveguide114is curved, each of the layers of the SOI wafer700may also be curved. For example, the PR coating303, the polysilicon layer215, the SOI layer109, and/or the insulator layer106may also be curved to align with the curved waveguide114. The cladding layer111that is deposited above the waveguide114may be curved at least on one edge to accommodate the curved waveguide114.

As shown inFIG. 8, the slots207and206may also be curved to align with the curved waveguide114. In this embodiment, the portion of the insulator layer106that is removed may be curved at least on the edge that faces the curved waveguide114. In this way, the etched-out portion203may also be curved at least on the edge that faces the curved waveguide114. In one embodiment, only the edge of the etched-out portion203that faces the curved waveguide114may be curved. In one embodiment, any edge of the etched-out portion203may be curved.

In some embodiments, the inclusion of the etched-out portion203and the enclosure403may not have any negative effects on the propagation of light throughout the PIC comprising any of the SOI wafers200or400disclosed herein. The embodiments disclosed herein provide a simple and controllable mechanism to provide thermal efficiency to SOI wafers. The etched-out portion203, or the removal of the portion of the insulator layer106, reduces the buckling chance of the SOI wafer.

The use of the term “substantially” means a range including ±10% of the subsequent modifier, unless otherwise stated. While several embodiments have been provided in the present disclosure, it may be understood that the disclosed systems and methods might be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented.