Electronic circuit

The invention provides an electronic circuit capable of reducing surge voltage while reducing switching loss when a MOSFET is turned off. A capacitor (91) is connected between apart closer to a first power source terminal (31) of a U-phase module (3) in a bus bar (61a) and a part closer to a second power source terminal (32) of the U-phase module (3) in a bus bar (64a). A capacitor (92) is connected between apart closer to a first power source terminal (41) of a V-phase module (4) in a bus bar (62) and a part closer to a second power source terminal (42) of the V-phase module (4) in a bus bar (65). A capacitor (93) is connected between a part closer to a first power source terminal (51) of a W-phase module (5) in a bus bar (63) and a part closer to a second power source terminal (52) of the W-phase module (5) in a bus bar (66).

TECHNICAL FIELD

The present invention relates to an electronic circuit, such as a three-phase inverter circuit or an H bridge circuit.

BACKGROUND ART

A MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), such as a DMOSFET (Double Diffused MOSFET), or an IGBT (Insulated Gate Bipolar Transistor) is used as a switching element of an electronic circuit, such as a three-phase inverter circuit or an H bridge circuit. A gate drive signal is supplied to a gate terminal of the MOSFET or of the IGBT through a gate resistor.

FIG. 5is a graph showing a relationship among gate resistance, switching loss (DMOS Eoff) caused when a DMOSFET is turned off, and surge voltage and showing a relationship among gate resistance, switching loss (IGBT Eoff) caused when an IGBT is turned off, and surge voltage.

In the IGBT, the gate resistance dependency of switching loss at the turn-off time is low. Additionally, in the IGBT, the amount of increase of the surge voltage is small with respect to an increase of the gate resistance. On the other hand, in the DMOSFET, the switching loss at the turn-off time can be made much smaller by reducing the gate resistance than in the IGBT. However, in the DMOSFET, if the gate resistance is reduced, the rate of change di/dt of a drain current at the turn-off time will become great, and therefore a great surge voltage will be generated.

As shown inFIG. 4, Patent Literature 1 discloses an arrangement in which, in a three-phase inverter circuit including six IGBTs, a snubber circuit is connected between a single DC input terminal P to which a collector of high-side IGBTs equivalent to three phases is connected and a single DC input terminal N to which an emitter of low-side IGBTs equivalent to three phases is connected, in order to restrain a surge voltage.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

An object of the present invention is to provide an electronic circuit capable of reducing the switching loss and capable of reducing the surge voltage when a MOSFET is turned off.

Solution to Problem

The electronic circuit of the present invention is an electronic circuit having a plurality of series circuits each of which has two MOSFETs connected in series in which a first power supply terminal is connected to one end of each of the series circuits and in which a second power supply terminal is connected to an opposite end of each of the series circuits, and the electronic circuit is composed of a first bus bar one end of which is connected to each of the first power supply terminals and that forms a part of an external electric wire to connect the first power supply terminal to one terminal of a power source, a second bus bar one end of which is connected to each of the second power supply terminals and that forms apart of an external electric wire to connect the second power supply terminal to an opposite terminal of the power source, and a snubber circuit that is provided in each of the series circuits and that is connected between the first bus bar connected to the series circuit through the first power supply terminal and the second bus bar connected to the series circuit through the second power supply terminal. In the electronic circuit, one end of each of the snubber circuits is connected to a part of the corresponding first bus bar closer to the first power supply terminal, whereas an opposite end of each of the snubber circuits is connected to a part of the corresponding second bus bar closer to the second power supply terminal.

The present invention includes a snubber circuit that is provided in each series circuit and that is connected between the first bus bar connected to the series circuit through the first power supply terminal and the second bus bar connected to the series circuit through the second power supply terminal, and therefore the surge voltage applied to a MOSFET when the MOSFET is turned off can be reduced.

Additionally, one end of each snubber circuit is connected to a part of the corresponding first bus bar closer to the first power supply terminal, and therefore the inductance of an interval part between the connection position of the snubber circuit and the first power supply terminal in the first bus bar can be reduced. Additionally, an opposite end of each snubber circuit is connected to a part of the corresponding second bus bar closer to the second power supply terminal, and therefore the inductance of an interval part between the connection position of the snubber circuit and the second power supply terminal in the second bus bar can be reduced. As a result, when the MOSFET is turned off, an inductance (excluding inductances by which energy stored by the snubber circuits is absorbed) that causes the generation of the surge voltage applied to the MOSFET can be reduced.

When the connection position of each snubber circuit with respect to a bus bar is changed and when gate resistance is changed so that the surge voltage applied to a MOSFET that has been turned off becomes constant, switching loss caused when the MOSFET is turned off becomes smaller in proportion to a reduction of the inductance that causes the generation of the surge voltage applied to the MOSFET. In the present invention, the inductance can be reduced, and therefore the switching loss at the turn-off time of the MOSFET can be reduced, and the surge voltage can be reduced.

In one embodiment of the present invention, in a combination of an arbitrary one of the series circuits, the first and second power supply terminals connected to both ends of the arbitrary one, the first and second bus bars connected thereto, and the snubber circuit connected therebetween, a sum of an inductance of an interval part between a connection point with one end of the snubber circuit and the first power supply terminal in the first bus bar, an inductance of an interval part between a connection point with an opposite end of the snubber circuit and the second power supply terminal in the second bus bar, and an inductance of the series circuit between the first power supply terminal and the second power supply terminal is 40 nH or less.

In this arrangement, when either one of the two MOSFETs included in the series circuit in the combination is turned off, the inductance that causes the generation of the surge voltage applied to the MOSFET that has been turned off can be reduced to be 40 nH or less, and therefore the switching loss at the turn-off time of the MOSFET can be reduced, and the surge voltage can be reduced.

In one embodiment of the present invention, one end of the snubber circuit is connected between one end of the first bus bar closer to the first power supply terminal and a second position of the first bus bar located at a first predetermined distance with respect to a first position of the first bus bar nearest to an outer end of the first power supply terminal in a direction receding from the first power supply terminal. The first predetermined distance is set so that an inductance of a part of the first bus bar from the first position to the second position becomes equal to 6.25 nH or less. An opposite end of the snubber circuit is connected between one end of the second bus bar closer to the second power supply terminal and a fourth position located at a second predetermined distance with respect to a third position nearest to an outer end of the second power supply terminal in a direction receding from the second power supply terminal. The second predetermined distance is set so that an inductance of a part of the second bus bar from the third position to the fourth position becomes equal to 6.25 nH or less.

In this arrangement, the inductance that causes the generation of the surge voltage applied to the MOSFET that has been turned off can be reduced, and therefore the switching loss at the turn-off time of the MOSFET can be reduced, and the surge voltage can be reduced.

In one embodiment of the present invention, each of the MOSFETs is a SiC-MOSFET made of a semiconductor material composed chiefly of SiC.

DESCRIPTION OF EMBODIMENTS

An embodiment of the present invention will be hereinafter described in detail with reference to the accompanying drawings.

FIG. 1is an electric circuit diagram showing a three-phase inverter circuit1according to an embodiment of the present invention.

This three-phase inverter circuit1is a circuit to drive a three-phase brushless motor8(hereinafter, referred to as an “electric motor”). The electric motor8is composed of a stator that has a U-phase field coil8U, a V-phase field coil8V, and a W-phase field coil8W and a rotor to which a permanent magnet is fixed.

The three-phase inverter circuit1includes a U-phase module3that is used for a U phase, a V-phase module4that is used for a V phase, and a W-phase module5that is used for a W phase. The U-phase module3is composed of a first power supply terminal (P terminal)31, a second power supply terminal (N terminal)32, an output terminal (OUT terminal)33, two gate terminals34and37, two source terminals35and38, and two source sense terminals36and39.

The V-phase module4is composed of a first power supply terminal (P terminal)41, a second power supply terminal (N terminal)42, an output terminal (OUT terminal)43, two gate terminals44and47, two source terminals45and48, and two source sense terminals46and49. The W-phase module5is composed of a first power supply terminal (P terminal)51, a second power supply terminal (N terminal)52, an output terminal (OUT terminal)53, two gate terminals54and57, two source terminals55and58, and two source sense terminals56and59.

Each of the first power supply terminals31,41, and51of the modules3,4, and5is connected to a positive terminal of a power source (DC power source)6through an external electric wire. More specifically, the first power supply terminal31of the U-phase module3is connected to the positive terminal of the power source6through a first external electric wire61. The first power supply terminal41of the V-phase module4is connected to an intermediate part of the first external electric wire61through a second external electric wire62. The first power supply terminal51of the W-phase module5is connected to the intermediate part of the first external electric wire61through a third external electric wire63.

Each of the second power supply terminals32,42, and52of the modules3,4, and5is connected to a negative terminal of the power source6through an external electric wire. More specifically, the second power supply terminal32of the U-phase module3is connected to the negative terminal of the power source6through a fourth external electric wire64. The second power supply terminal42of the V-phase module4is connected to an intermediate part of the fourth external electric wire64through a fifth external electric wire65. The second power supply terminal52of the W-phase module5is connected to the intermediate part of the fourth external electric wire64through a sixth external electric wire66. An inductance parasitizes each of the external electric wires61to66.

A smoothing capacitor7is connected to the power source6in parallel. The output terminals33,43, and53of the modules3,4, and5are connected to a U-phase field winding8U, a V-phase field winding8V, and a W-phase field winding8W of the electric motor8through seventh, eighth, and ninth external electric wires67,68, and69, respectively. A control unit (not shown) is connected to each of the gate terminals34,37,44,47,54,57and to each of the source sense terminals36,39,46,49,56, and59of the modules3,4, and5. The control unit allows a gate drive signal to be supplied to each of the gate terminals34,37,44,47,54, and57of the modules3,4, and5through gate resistors (not shown).

The U-phase module3includes a high-side first MOSFET11and a low-side second MOSFET12connected in series thereto. The MOSFETs11and12have a built-in first PN junction diode (body diode)11aand a built-in second PN junction diode12a, respectively. Anodes of the PN junction diodes11aand12aare electrically connected to corresponding sources of the MOSFETs11and12, respectively, and cathodes thereof are electrically connected to corresponding drains of the MOSFETs11and12, respectively. The MOSFETs11and12are provided with current detecting portions11band12b, respectively.

The drain of the first MOSFET11is connected to the first power supply terminal31of the U-phase module3through a connection metal member71. The source of the first MOSFET11is connected to the output terminal33of the U-phase module3through a connection metal member72. Inductances L11and L12parasitize the connection metal members71and72, respectively. The source of the first MOSFET11is further connected to the source terminal35of the U-phase module3. The current detecting portion11bis connected to the source sense terminal36of the U-phase module3. The gate of the first MOSFET11is connected to the gate terminal34of the U-phase module3.

The drain of the second MOSFET12is connected to the output terminal33of the U-phase module3through a connection metal member73. The source of the second MOSFET12is connected to the second power supply terminal32of the U-phase module3through a connection metal member74. Inductances L13and L14parasitize the connection metal members73and74, respectively. The source of the second MOSFET12is further connected to the source terminal38of the U-phase module3. The current detecting portion12bis connected to the source sense terminal39of the U-phase module3. The gate of the second MOSFET12is connected to the gate terminal37of the U-phase module3.

The V-phase module4includes a high-side third MOSFET13and a low-side fourth MOSFET14connected in series thereto. The MOSFETs13and14have built-in third and fourth PN junction diodes (body diodes)13aand14a, respectively. Anodes of the PN junction diodes13aand14aare electrically connected to corresponding sources of the MOSFETs13and14, respectively, and cathodes thereof are electrically connected to corresponding drains of the MOSFETs13and14, respectively. The MOSFETs13and14are provided with current detecting portions13band14b, respectively.

The drain of the third MOSFET13is connected to the first power supply terminal41of the V-phase module4through a connection metal member75. The source of the third MOSFET13is connected to the output terminal43of the V-phase module4through a connection metal member76. Inductances L15and L16parasitize the connection metal members75and76, respectively. The source of the third MOSFET13is further connected to the source terminal45of the V-phase module4. The current detecting portion13bis connected to the source sense terminal46of the V-phase module4. The gate of the third MOSFET13is connected to the gate terminal44of the V-phase module4.

The drain of the fourth MOSFET14is connected to the output terminal43of the V-phase module4through a connection metal member77. The source of the fourth MOSFET14is connected to the second power supply terminal42of the V-phase module4through a connection metal member78. Inductances L17and L18parasitize the connection metal members77and78, respectively. The source of the fourth MOSFET14is further connected to the source terminal48of the V-phase module4. The current detecting portion14bis connected to the source sense terminal49of the V-phase module4. The gate of the fourth MOSFET14is connected to the gate terminal47of the V-phase module4.

The W-phase module5includes a high-side fifth MOSFET15and a low-side sixth MOSFET16connected in series thereto. The MOSFETs15and16have built-in fifth and sixth PN junction diodes (body diodes)15aand16a, respectively. Anodes of the PN junction diodes15aand16aare electrically connected to corresponding sources of the MOSFETs15and16, respectively, and cathodes thereof are electrically connected to corresponding drains of the MOSFETs15and16, respectively. The MOSFETs15and16are provided with current detecting portions15band16b, respectively.

The drain of the fifth MOSFET15is connected to the first power supply terminal51of the W-phase module5through a connection metal member79. The source of the fifth MOSFET15is connected to the output terminal53of the W-phase module5through a connection metal member80. Inductances L19and L20parasitize the connection metal members79and80, respectively. The source of the fifth MOSFET15is further connected to the source terminal55of the W-phase module5. The current detecting portion15bis connected to the source sense terminal56of the W-phase module5. The gate of the fifth MOSFET15is connected to the gate terminal54of the W-phase module5.

The drain of the sixth MOSFET16is connected to the output terminal53of the W-phase module5through a connection metal member81. The source of the sixth MOSFET16is connected to the second power supply terminal52of the W-phase module5through a connection metal member82. Inductances L21and L22parasitize the connection metal members81and82, respectively. The source of the sixth MOSFET16is further connected to the source terminal58of the W-phase module5. The current detecting portion16bis connected to the source sense terminal59of the W-phase module5. The gate of the sixth MOSFET16is connected to the gate terminal57of the W-phase module5.

For example, each of the first to sixth MOSFETs11to16is a SiC-MOSFET, such as a SiC-DMOSFET, that uses SiC (silicon carbide) as a semiconductor material, which is one example of a compound semiconductor.

A snubber circuit composed of a capacitor91is connected between a part of the first external electric wire61closer to the first power supply terminal31of the U-phase module3and a part of the fourth external electric wire64closer to the second power supply terminal32of the U-phase module3.

Let the connection point between the first external electric wire61and the capacitor91be a connection point A1. An inductance L1aparasitizes an interval part between a positive terminal of the power source6and the connection point A1in the first external electric wire61, and an inductance L1bparasitizes an interval part between the connection point A1and the first power supply terminal31in the first external electric wire61. Let the connection point between the fourth external electric wire64and the capacitor91be a connection point A4. An inductance L4aparasitizes an interval part between a negative terminal of the power source6and the connection point A4in the fourth external electric wire64, and an inductance L4bparasitizes an interval part between the connection point A4and the second power supply terminal32in the fourth external electric wire64.

A snubber circuit composed of a capacitor92is connected between a part of the second external electric wire62closer to the first power supply terminal41of the V-phase module4and a part of the fifth external electric wire65closer to the second power supply terminal42of the V-phase module4.

Let the connection point between the second external electric wire62and the capacitor92be a connection point A2. An inductance L2bparasitizes an interval part between the connection point A2and the first power supply terminal41in the second external electric wire62, and an inductance L2aparasitizes the remaining part. Let the connection point between the fifth external electric wire65and the capacitor92be a connection point A5. An inductance L5bparasitizes an interval part between the connection point A5and the second power supply terminal42in the fifth external electric wire65, and an inductance L5aparasitizes the remaining part.

A snubber circuit composed of a capacitor93is connected between a part of the third external electric wire63closer to the first power supply terminal51of the W-phase module5and a part of the sixth external electric wire66closer to the second power supply terminal52of the W-phase module5.

Let the connection point between the third external electric wire63and the capacitor93be a connection point A3. An inductance L3bparasitizes an interval part between the connection point A3and the first power supply terminal51in the third external electric wire63, and an inductance L1aparasitizes the remaining part. Let the connection point between the sixth external electric wire66and the capacitor93be a connection point A6. An inductance L6bparasitizes an interval part between the connection point A6and the second power supply terminal52in the sixth external electric wire66, and an inductance L6aparasitizes the remaining part. The capacitors (snubber circuits)91to93are provided to restrain the surge voltage.

FIG. 2is a pictorial perspective view showing the exterior of the U-phase module3ofFIG. 1.

The U-phase module3includes a heat dissipation plate21, a substrate (not shown) that is fixed to the heat dissipation plate21and to which the MOSFETs11and12, base ends of the terminals31to39, etc., are fixed, and a case22that is fixed to one surface of the heat dissipation plate21and that contains the substrate. The case22is formed in a substantially rectangular shape when viewed planarly. The output terminal33of the module3forks in two directions within the case22, and has two flat branch portions. Forward ends33aand33bof the branch portions pass through the upper surface of the case22, and are exposed outwardly from the case22. These forward ends33aand33bare disposed in a state along the upper surface of the case22at both sides of one end of the upper surface of the case22, respectively. The first power supply terminal31and the second power supply terminal32of the module3are flat, and their forward ends31aand32apass through the upper surface of the case22, and are exposed outwardly from the case22. These forward ends31aand32aare disposed in a state along the upper surface of the case22at both sides of the other end of the upper surface of the case22, respectively.

The gate terminal34, which is one of the two gate terminals, the source terminal35, which is one of the two source terminals, and the source sense terminal36, which is one of the two source sense terminals, of the module3are rod-shaped terminals, and their forward ends34a,35a, and36apass through the upper surface of the case22, and protrude outwardly from the case22. These forward ends34a,35a, and36aare disposed adjacently to the forward end31aof the first power supply terminal31in the upper surface of the case22. The other gate terminal37, the other source terminal38, and the other source sense terminal39of the module3are rod-shaped terminals, and their forward ends37a,38a, and39apass through the upper surface of the case22, and protrude outwardly from the case22. These forward ends37a,38a, and39aare disposed adjacently to the forward end33b, which is one of the two forward ends, of the output terminal33in the upper surface of the case22.

The V-phase module4and the W-phase module5have the same exterior and the same structure as those of the U-phase module3, and therefore a description of these exterior and structure is omitted.

FIG. 3is a plan view chiefly showing external electric wires connected to the power supply terminals31,32,41,42,51, and52of the modules2,3, and4and showing snubber circuits connected thereto.

Each of the modules3,4, and5is attached to a cooling plate201. The output terminal33of the U-phase module3is connected to the U-phase field winding8U of the electric motor8through the external electric wire67. The output terminal43of the V-phase module4is connected to the V-phase field winding8V of the electric motor8through the external electric wire68. The output terminal53of the W-phase module5is connected to the W-phase field winding8W of the electric motor8through the external electric wire69.

One end of a bus bar61ais screwed to the first power supply terminal31of the U-phase module3. The other end of the bus bar61ais connected to the positive terminal of the power source6through a connection line61b. The first external electric wire61ofFIG. 1consists of the bus bar61aand the connection line61b. One end of a bus bar64ais screwed to the second power supply terminal32of the U-phase module3. The other end of the bus bar64ais connected to the negative terminal of the power source6through a connection line64b. The fourth external electric wire64ofFIG. 1consists of the bus bar64aand the connection line64b. The smoothing capacitor7is connected to the power source6in parallel.

One end of a bus bar62(corresponding to the second external electric wire62ofFIG. 1) is screwed to the first power supply terminal41of the V-phase module4. The other end of the bus bar62is connected to an intermediate part of the bus bar61a. One end of a bus bar65(corresponding to the fifth external electric wire65ofFIG. 1) is screwed to the second power supply terminal42of the V-phase module4. The other end of the bus bar65is connected to an intermediate part of the bus bar64a.

One end of a bus bar63(corresponding to the third external electric wire63ofFIG. 1) is screwed to the first power supply terminal51of the W-phase module5. The other end of the bus bar63is connected to the intermediate part of the bus bar61a. One end of a bus bar66(corresponding to the sixth external electric wire66ofFIG. 1) is screwed to the second power supply terminal52of the W-phase module5. The other end of the bus bar66is connected to the intermediate part of the bus bar64a.

A capacitor91is connected between a part of the bus bar61acloser to the first power supply terminal31and a part of the bus bar64acloser to the second power supply terminal32. A capacitor92is connected between a part of the bus bar62closer to the first power supply terminal41and a part of the bus bar65closer to the second power supply terminal42. A capacitor93is connected between a part of the bus bar63closer to the first power supply terminal51and a part of the bus bar66closer to the second power supply terminal52.

Preferably, one end of each of the capacitors91,92, and93is connected (to an A-to-C area S) between one end (position A) of each of the corresponding bus bars61a,62, and63closer to the first power supply terminals31,41, and51and a position (position C) located at a predetermined distance x in a direction receding from the first power supply terminals31,41, and51with respect to a position (position B) of each of the corresponding bus bars61a,62, and63nearest to an outer end of each of the first power supply terminals31,41, and51.

Likewise, preferably, the other end of each of the capacitors91,92, and93is connected (to an A-to-C area S) between one end (position A) of each of the corresponding bus bars64a,65, and66closer to the second power supply terminals32,42, and52and a position (position C) located at a predetermined distance x in a direction receding from the second power supply terminals32,42, and52with respect to a position (position B) of each of the corresponding bus bars64a,65, and66nearest to an outer end of each of the second power supply terminals32,42, and52.

Preferably, the predetermined distance x is set so that the inductance of the part from position B to position C in each of the bus bars61a,62,63,64a,65, and66is 6.25 (nH) or less. This predetermination of the distance x makes it possible to reduce both the switching loss caused when a MOSFET is turned off and the surge voltage applied to this MOSFET as described later.

Preferably, the two bus bars61aand64aconnected to the two power supply terminals31and32of the module3are disposed such that their intermediate parts coincide with each other in the up-down direction when viewed planarly so that their inductance components are offset. Likewise, preferably, the two bus bars62and65connected to the two power supply terminals41and42of the module4are disposed such that their intermediate parts coincide with each other in the up-down direction when viewed planarly. Likewise, preferably, the two bus bars63and66connected to the two power supply terminals51and52of the module5are disposed such that their intermediate parts coincide with each other in the up-down direction when viewed planarly.

Referring again toFIG. 1, for example, when the high-side MOSFET11in the U-phase module3and the low-side MOSFET14in the V-phase module4are turned on among the MOSFETs11to16, an electric current flows from the positive terminal of the power source6to the negative terminal of the power source6through the first external electric wire61, the first power supply terminal31, the connection metal member71, the MOSFET11, the connection metal member72, the output terminal33, the seventh external electric wire67, the U-phase field winding8U and the V-phase field winding8V of the electric motor8, the eighth external electric wire68, the output terminal43, the connection metal member77, the MOSFET14, the connection metal member78, the second power supply terminal42, the fifth external electric wire65, and the fourth external electric wire64.

When the high-side MOSFET11in the U-phase module3is turned off from this state, a load current flows back through a closed circuit that includes the output terminal33, the seventh external electric wire67, the U-phase field winding8U and the V-phase field winding8V of the electric motor8, the eighth external electric wire68, the output terminal43, the connection metal member77, the MOSFET14, the connection metal member78, the second power supply terminal42, the fifth external electric wire65, the interval part between a connection point with the fifth external electric wire65and the second output terminal32in the fourth external electric wire64, the second output terminal32, the connection metal member74, the PN junction diode12a, and the connection metal member73.

In this example, a surge voltage (Ls·di/dt) depending on the electric current rate of change (di/dt) of the drain current of the MOSFET11and depending on the predetermined parasitic inductance Ls of the circuit wiring is applied to the MOSFET11.

If the snubber circuits91to93are not provided, the inductance Lst that causes the generation of the surge voltage applied to the MOSFET11becomes equal to the sum of an inductance (part of L4a) between the connection point with the fifth wiring line65and the negative terminal of the power source6in the fourth external electric wire64, an inductance (L1a+L1b) of the first external electric wire61, inductances L11and L12of the connection metal members71and72, an inductance (sum of L4band part of L4a) of an interval part between the connection point with the fifth wiring line65and the second power supply terminal32in the fourth external electric wire64, and inductances L13and L14of the connection metal members73and74.

In the present embodiment, the snubber circuits91to93are provided, and therefore energy stored in the inductance L4aof the interval part between the connection point A4and the negative terminal of the power source6in the fourth external electric wire64and stored in the inductance L1aof the interval part between the positive terminal of the power source6and the connection point A1in the first external electric wire61is absorbed by the capacitor91. As a result, the inductance Lsn that causes the generation of the surge voltage applied to the MOSFET11becomes equal to the sum of the inductance L1bof the interval part between the connection point A1and the first power supply terminal31in the first external electric wire61, the inductances L11, L12, L13, and L14of the connection metal members71,72,73, and74, and the inductance L4bof the interval part between the connection point A4and the second power supply terminal31in the fourth external electric wire64. In other words, the inductance Lsn that causes the generation of the surge voltage applied to the MOSFET11is made much smaller than the inductance Lst caused when the snubber circuits91to93are not provided. Therefore, the surge voltage applied to the MOSFET11is made much smaller than when the snubber circuits91to93are not provided.

For example, when the low-side MOSFET14in the V-phase module4is turned off from a state in which the MOSFET11and the MOSFET14have been turned on, a load current flows back through a closed circuit that includes the first power supply terminal31, the connection metal member71, the MOSFET11, the connection metal member72, the output terminal33, the seventh external electric wire67, the U-phase field winding8U and the V-phase field winding8V of the electric motor8, the eighth external electric wire68, the output terminal43, the connection metal member76, the PN junction diode13a, the connection metal member75, the first power supply terminal41, the second external electric wire62, and an interval part between a connection point with the second external electric wire62and the first power supply terminal31in the first external electric wire61.

In this example, a surge voltage (Ls·di/dt) depending on the electric current rate of change (di/dt) of the drain current of the MOSFET14and depending on the predetermined parasitic inductance Ls of the circuit wiring is applied to the MOSFET14.

If the snubber circuits91to93are not provided, the inductance Lst that causes the generation of the surge voltage applied to the MOSFET14becomes equal to the sum of an inductance (part of L1a) between the positive terminal of the power source6and a connection point with the second wiring line62in the first external electric wire61, inductances L17and L18of the connection metal members77and78, an inductance (L5a+L5b) of the fifth external electric wire65, an inductance of an interval part (part of L4a) between a connection point with the fifth external electric wire65and the negative terminal of the power source6in the fourth external electric wire64, an inductance (L2a+L2b) of the second external electric wire member62, and inductances L15and L16of the connection metal members75and76.

In the present embodiment, the snubber circuits91to93are provided, and therefore energy stored in the inductance of an interval part (part of L1a) between the positive terminal of the power source6and a connection point with the second wiring line62in the first external electric wire61, the inductance L5aof an interval part between the connection point A5and a connection point with the fourth external electric wire64in the fifth external electric wire65, the inductance of an interval part (part of L4a) between a connection point with the fifth external electric wire65and the negative terminal of the power source6in the fourth external electric wire64, and the inductance L2aof an interval part between a connection point with the first external electric wire61and the connection point A2in the second external electric wire62is absorbed by the capacitor92. As a result, the inductance Lsn that causes the generation of the surge voltage applied to the MOSFET14becomes equal to the sum of the inductance L2bof an interval part between the connection point A2and the first power supply terminal41in the second external electric wire62, the inductances L15, L16, L17, and L18of the connection metal members75,76,77, and78, and the inductance L5bof an interval part between the second power supply terminal42and the connection point A5in the fifth external electric wire65. In other words, the inductance Lsn that causes the generation of the surge voltage applied to the MOSFET14is made much smaller than the inductance Lst caused when the snubber circuits91to93are not provided. Therefore, the surge voltage applied to the MOSFET14is made much smaller than when the snubber circuits91to93are not provided.

When both the MOSFET11and the MOSFET14are simultaneously turned off from a state in which the MOSFET11and the MOSFET14have been turned on, a load current flows in a direction from the fourth external electric wire64toward the first external electric wire61through the fourth external electric wire64, the second power supply terminal32, the connection metal member74, the PN junction diode12a, the connection metal member73, the output terminal33, the seventh external electric wire67, the U-phase field winding8U and the V-phase field winding8V of the electric motor8, the eighth external electric wire68, the output terminal43, the connection metal member76, the PN junction diode13a, the connection metal member75, the first power supply terminal41, the second external electric wire62, and an interval part between a connection point with the second external electric wire62and the positive terminal of the power source6in the first external electric wire61.

In this example, most of the energy stored in the inductances parasitizing the external electric wires is absorbed by the capacitors91and92. Therefore, the inductance Lsn that causes the generation of the surge voltage applied to the MOSFET11becomes equal to the sum of the inductance L1b, the inductances L11to L14(internal inductances in the U-phase module3), and the inductance L4b. On the other hand, the inductance Lsn that causes the generation of the surge voltage applied to the MOSFET14becomes equal to the sum of the inductance L2b, the inductances L15to L18(internal inductances in the V-phase module4), and the inductance L5b.

In other words, when either one of the MOSFETs11and12in the U-phase module3is turned off, the inductance Lsn (hereinafter, referred to as the inductance “LsnU” when necessary) that causes the generation of the surge voltage applied to this one becomes equal to the sum of the inductance L1b, the inductances L11to L14(internal inductances in the U-phase module3), and the inductance L4b.

When either one of the MOSFETs13and14in the V-phase module4is turned off, the inductance Lsn (hereinafter, referred to as the inductance “LsnV” when necessary) that causes the generation of the surge voltage applied to this one becomes equal to the sum of the inductance L2b, the inductances L15to L18(internal inductances in the V-phase module4), and the inductance L5b.

When either one of the MOSFETs15and16in the W-phase module5is turned off, the inductance Lsn (hereinafter, referred to as the inductance “LsnW” when necessary) that causes the generation of the surge voltage applied to this one becomes equal to the sum of the inductance L3b, the inductances L19to L22(internal inductances in the W-phase module5), and the inductance L6b. In the present embodiment, the inductances LsnU, LsnV, and LsnWare substantially equal to each other. Preferably, the inductances LsnU, LsnV, and LsnWare 40 (nH) or less as described later.

In the three-phase inverter circuit1, when the connection positions of the capacitors91to93with respect to corresponding bus bars are changed, and when the gate resistance with respect to a MOSFET is changed so that a surge voltage applied to the MOSFET that has been turned off becomes constant, the rate of change di/dt of the drain current of the MOSFET becomes greater (i.e., the falling of “di” becomes earlier) in proportion to a reduction of the inductance Lsn that causes the generation of the surge voltage applied to the MOSFET (excluding inductances by which energy stored by the snubber circuits91to93is absorbed), and therefore the switching loss caused when the MOSFET is turned off becomes smaller. Therefore, the switching loss caused when the MOSFET is turned off can be reduced by reducing the inductance Lsn that causes the generation of a surge voltage, and the surge voltage can be reduced.

In the aforementioned embodiment, one end of each of the capacitors91,92, and93is connected to the position of each of the external electric wires61,62, and63closer to the first power supply terminals31,41, and51, respectively, and therefore the inductances L1b, L2b, and L3bof external electric wire parts between respective ends of the snubber circuits91,92, and93and the first power supply terminals31,41, and51can be reduced. Additionally, the other end of each of the capacitors91,92, and93is connected to the position of each of the external electric wires64,65, and66closer to the second power supply terminals32,42, and52, respectively, and therefore the inductances L4b, L5b, and L6bof external electric wire parts between the respective other ends of the snubber circuits91,92, and93and the second power supply terminals32,42, and52can be reduced.

Therefore, when an arbitrary MOSFET is turned off, the inductance Lsn that causes the generation of a surge voltage applied to this MOSFET can be reduced. As a result, the switching loss at the turn-off time of the MOSFET can be reduced, and the surge voltage can be reduced.

Next, a description will be given of a relationship among the inductance Lsn that causes the generation of a surge voltage applied to a MOSFET that has been turned off, the switching loss at the turn-off time of the MOSFET, and the rate of change di/dt of a drain current.

A plurality of samples “a” to “g” having mutually different inductances Lsn were prepared. More specifically, a plurality of samples a to g having mutually different inductances Lsn were prepared by changing the distance from one end of each of the bus bars61a,64a,62,65,63, and66closer to the power supply terminals31,32,41,42,51, and52to the connection positions of the capacitors91to93.

The distance from one end of each of the bus bars61a,64a,62,65,63, and66closer to the power supply terminals31,32,41,42,51, and52to the connection positions of the capacitors91to93is set so as to become longer in order of samples a, b, c, d, e, f, and g, sample “a” having the shortest distance.

With regard to sample “a,” as shown inFIG. 3, both ends of each of the capacitors91to93are connected (to an A-to-B area) between one end (position A) of each of the corresponding bus bars61a,64a,62,65,63, and66closer to the power supply terminals31,32,41,42,51, and52and the position (position B) corresponding to the outer end of each of the power supply terminals31,32,41,42,51, and52. With regard to samples b to g, both ends of each of the capacitors91to93are connected to a position fixed more apart from each of the power supply terminals31,32,41,42,51, and52than the position (position B) corresponding to the outer end of each of the power supply terminals31,32,41,42,51, and52in the corresponding bus bars61a,64a,62,65,63, and66.

Therefore, the inductances L1b, L4b, L2b, L5b, L3b, and L6bbecome greater in order of samples a, b, c, d, e, f, and g. Therefore, the inductance Lsn that causes the generation of a surge voltage applied to a MOSFET that has been turned off becomes greater in order of samples a, b, c, d, e, f, and g.

In samples a to g, the gate resistance was adjusted so that the MOSFET11is turned off from a state in which the MOSFET11and the MOSFET14have been turned on and so that the surge voltage (Lsn·di/dt) applied to the MOSFET11reaches a predetermined value when the MOSFET11is turned off. After adjusting the gate resistance so that the surge voltage reaches the predetermined value, the MOSFET11was turned off from a state in which the MOSFET11and the MOSFET14have been turned on, and then the switching loss (mJ) at the turn-off time of the MOSFET11and the rate of change di/dt (A/ns) of the drain current of the MOSFET11were measured. In this example, the inductance Lsn that causes the generation of the surge voltage applied to the MOSFET11becomes equal to LsnU(=L1b+L4b+L11+L12+L13+L14).

The power-supply voltage V was set at 600(V), and the power source electric current I was set at 100 (A). Additionally, the gate resistance was adjusted so that the surge voltage reaches 156(V).

InFIG. 4, the black triangle (▴) represents switching loss, and the white triangle (Δ) represents di/dt.

From Table 1 andFIG. 4, it is understood that, when the gate resistance is changed so that a surge voltage applied to a MOSFET that has been turned off becomes constant, the switching loss of the MOSFET at the turn-off time can be restricted to a low level if the inductance Lsn (in this example, LsnU) is about 40 (nH) or less.

The inductance Lsn of sample “a” is 27.5 (nH), and therefore, what is needed for setting the inductance Lsn at about 40 (nH) or less is to allow the amount of increase in the inductance Lsn to reach (40−27.5)=12.5 (nH) or less with respect to sample “a.” In this example, the inductances L1band L4bare included in the inductance LsnU, and therefore what is needed is to allow the amount of increase in L1band in L4bto reach 6.25 (nH), which is half of 12.5 (nH), or less with respect to sample “a.”

Let it be supposed that, when the capacitor91is connected between one end (position A) of each of the bus bars61aand64acloser to the power supply terminals31and32and a position (position B) nearest to the outer end of each of the power supply terminals31and32, the inductances L1band L4bof an interval part between the connection points of the capacitor91in the bus bars61aand64aand the power supply terminals31and32are constant regardless of the connection position. Additionally, let it be supposed that the inductances L1band L4bare small in sample “a,” and the inductance (L11+L12+L13+L14) in the module3is substantially equal to the inductance Lsn with respect to sample “a.” If so, when the inductance in the module3is about 27.5 (nH), what is needed for setting the inductance Lsn at about 40 (nH) or less will be to set x, which determines a preferred connection range (A-to-C area S ofFIG. 3) of the capacitor91with respect to the bus bars61aand64a, at 6.25 (nH) or less.

For the same reason, preferably, when the inductance in the module4and the inductance in the module5are about 27.5 (nH), the inductance LsnVand the inductance LsnWare set at about 40 (nH) or less. Therefore, what is needed is to set both x, which determines a preferred connection range (A-to-C area S ofFIG. 3) of the capacitor92with respect to the bus bars62and65, and x, which determines a preferred connection range (A-to-C area S ofFIG. 3) of the capacitor93with respect to the bus bars63and66, at 6.25 (nH) or less.

The present invention can be embodied in other modes although one embodiment of the present invention has been described as above. For example, each of the MOSFETs11,12,13, and14may be a Si device that uses Si (silicon) as a semiconductor material although each is a SiC device in the aforementioned embodiment.

Additionally, the present invention can be applied also to electronic circuits other than a three-phase inverter circuit, such as an H bridge circuit although the present invention is applied to the three-phase inverter circuit as described in the aforementioned embodiment.

Besides the foregoing, various design changes can be made within the scope of the appended claims.

REFERENCE SIGNS LIST