SIP semiconductor system

A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2011-0015176 filed on Feb. 21, 2011 and Korean application number 10-2011-0060826, filed on Jun. 22, 2011 in the Korean Intellectual Property Office, which is incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor system, and more particularly, to a system in package (SIP) semiconductor system in which a memory device and a controller are in one package.

2. Related Art

As semiconductor devices are integrated, a system in package (SIP) technology is used, in which a memory device and a controller are configured in one package.

A SIP semiconductor system configured using the SIP technology can have superior characteristics in terms of noise and operation stability compared to a semiconductor device configured using a heterogeneous package technology.

In the SIP semiconductor system configured using the SIP technology, all input/output terminals accessing a memory device from the outside of a package are generally connected to a controller in the package, and hence there exists no terminal capable of directly accessing the memory device from the outside of the package. Therefore, the SIP semiconductor system cannot perform a probe test and repair operation performed in the semiconductor device using the heterogeneous package technology.

In order to solve such a problem, the SIP semiconductor system performs a test of an internal memory device through an internal controller, and a design for test (DFT) such as a memory built-in self test (MBIST) or scan test is used to perform the test.

In order to repair the memory device of the SIP semiconductor system based on a test result obtained through the DFT, a redundancy analysis (RA) is required to allow optimal repair to be performed by analyzing the test result. The RA has a relatively complicated configuration, and the area and cost of the package or memory device is increased by implementing the configuration as an internal logic circuit.

SUMMARY

A SIP semiconductor system capable of testing an internal memory device using less area and cost is described.

In one embodiment of the present invention, a SIP semiconductor system includes a memory device, a controller configured to communicate with the memory device, a first input/output terminal configured to perform communication between the controller and a device external to the SIP semiconductor system, a test control unit configured to control a predetermined test mode of the memory device, and a second input/output terminal configured to perform communication between the test control unit and at least the device external to the SIP semiconductor system.

In another embodiment of the present invention, a SIP semiconductor system includes a memory device configured to include electrical fuses for restoring a defective storage element, a test control unit configured to control a predetermined test mode of the memory device, and an input/output terminal configured to perform communication between the test control unit and a device external to the SIP semiconductor system. In the SIP semiconductor system the test control unit may use an IEEE standard interface, store a code with a plurality of bits in an internal register according to an input signal received through the input/output terminal, and store a test result received from the memory device in the internal register. The memory device may perform the predetermined test mode according to values stored in the internal register.

In still another embodiment of the present invention, a SIP semiconductor system includes a test access port, a register configured to be connected to the test access port, and output a rupture start signal and a rupture object fuse information signal during a repair operation, and a fuse unit configured to rupture a fuse corresponding to the rupture object fuse information signal in response to the rupture start signal and the rupture object fuse information signal.

DETAILED DESCRIPTION

A SIP semiconductor system according to the present invention will be described below with reference to the accompanying drawings through exemplary embodiments.

The SIP semiconductor system according to an embodiment of the present invention includes an input/output terminal for directly testing a memory device of the SIP semiconductor system so that it may be possible to test and repair the memory device of the SIP semiconductor system.

Furthermore, in the SIP semiconductor system according to an embodiment of the present invention, the input/output terminal is configured according to the IEEE 1149.1 Standard so that it is possible to facilitate implementing a test operation of the SIP semiconductor system and loading test equipment of the SIP semiconductor system.

FIG. 1is an exemplary block diagram of a SIP semiconductor system according to one embodiment of the invention.

As illustrated inFIG. 1, the SIP semiconductor system can be configured to include a memory device100, a controller200, a first input/output terminal300, a test control unit400, and a second input/output terminal500.

The memory device100includes a plurality of storage elements for storing data. The configuration of the memory device100is not particularly limited. As an example, the memory device100can be configured to include a single memory chip or can be configured to include a plurality of memory chips stacked using through silicon via (TSV). As another example, the memory device100can be configured as a volatile memory device such as a DRAM or can be configured as a non-volatile memory device such as a flash memory.

The controller200controls the memory device100. The controller200can be configured to include a processor such as a general central processing unit (CPU) or graphic processing unit (GPU).

The first input/output terminal300is an input/output terminal for communication between the outside of the SIP semiconductor system and the controller200. The first input/output terminal300can be configured to include an input/output terminal of a general SIP semiconductor system.

The controller200communicates with devices external to the SIP semiconductor system through the first input/output terminal300, and controls the memory device100.

The test control unit400controls a predetermined test mode of the memory device100.

The test control unit400controls the memory device100to perform various predetermined test modes (e.g., a repair operation). The predetermined test mode of the test control unit400includes a variety of tests. The test control unit400can include a plurality of algorithms for performing the predetermined test mode. The test of the memory device100, performed by the test control unit400includes a voltage test (AC or DC test), a functional test of semiconductor logic, a memory cell test, and the like. However, the present invention is not limited thereto. Particularly, since memory devices such as DRAMs or flash memories include a large number of memory cells, much time may be taken to perform the memory cell test for finding a defective memory cell. Thus, the memory cell test performed through the test control unit400can decrease test time and increase test efficiency as compared with that performed through external test equipment.

The test control unit400directly controls the memory device100, and can communicate with devices external to the SIP semiconductor system through the second input/output terminal500. Thus, the test control unit400may not need to communicate with the controller200for some of its functionality.

For example, when the predetermined test mode is a repair operation, the SIP semiconductor system according to this embodiment can repair a defective storage element of the memory device100. Alternatively, the SIP semiconductor system according to this embodiment can repair a defective TSV in the memory device100including the plurality of memory chips stacked using the TSV.

More specifically, the memory device100further includes a fuse unit110having an electrical fuse (E-fuse) for restoring a defective storage element or defective TSV. The memory device100can be configured to perform a rupture operation on the E-fuse by performing the predetermined test mode.

The test control unit400can be configured separately from the memory device in the inside of the SIP semiconductor system. The test control unit400can be configured to be included in the memory device100. It will be apparent that the present invention is not limited to where the test control unit400is positioned in the SIP semiconductor system.

As an example, when the memory device100is configured to include a plurality of memory chips, the test control unit400can be included in each of the plurality of memory chips. The memory device100configured so that the test control unit400included in each of the plurality of memory chips can perform the predetermined test mode in the state where the memory device100is connected in parallel to the plurality of memory chips.

As another example, when the memory device100is configured to include a plurality of memory chips stacked using the TSV, the test control unit400can be included in one of the plurality of memory chips. Among the plurality of memory chips, the memory chip with the test control unit400may be a memory chip (e.g., a master chip) communicating with the controller200.

The second input/output terminal500is an input/output terminal for communication between the test control unit400and the outside of the SIP semiconductor system.

The SIP semiconductor system configured as described above can control the memory device by communicating with the controller200through the first input/output terminal300. The SIP semiconductor system can control the memory device100to perform the predetermined test mode by communicating with the test control unit400through the second input/output terminal500.

Thus, the SIP semiconductor system can perform the test of the memory device100without passing through the controller200.

The test control unit400can be configured using IEEE 1149.1.

The IEEE 1149.1 (JTAG Boundary Scan test) is a serial standard interface used as a standard in communication between a SIP semiconductor system and a device external (e.g., a system board) to the SIP semiconductor system.

The test control unit400configured using the IEEE 1149.1 has advantages as follows.

The IEEE 1149.1 is a standardized interface, and its configuration is relatively simple. Thus, it is easy to design the test control unit400. Further, it is unnecessary to have a complicated configuration like the related art DFT using an RA algorithm.

The IEEE 1149.1 is an interface used as a standard in communication between the related art SIP semiconductor system and the system board. Thus, the test can be performed by loading the SIP semiconductor system according to an embodiment of the present invention onto the system board without configuring a separate logic on the system board.

The SIP semiconductor system according to this embodiment is configured using the IEEE 1149.1 so as to have characteristics suitable for communication with the system board.

The IEEE 1149.1 is frequently used in current test communication between the system board and the SIP semiconductor system, but the test control unit400can be differently configured depending on a change in IEEE standard interface. That is, the test control unit400can be configured not only using the IEEE 1149.1 but also using the IEEE standard interface. When the test control unit400is configured using the IEEE 1149.1, the second input/output terminal500is preferably configured as a test access port for supporting the IEEE 1149.1.

The test access port of the IEEE 1149.1 can be configured to include TDI, TDO, TMS, TCK, and TRST.

The TDI is a test data input terminal, and the TDO is a test data output terminal. The TMS is a test mode select terminal, and the TCK is a test clock-signal terminal. The TRST is a test reset terminal.

The IEEE 1149.1 is configured to perform a recording operation for an internal register under communication of the test access port. One embodiment for setting the internal register will be described later.

FIG. 2is a detailed block diagram of the test control unit400illustrated inFIG. 1.

The test control unit400can be configured to include a test register unit410and a test logic unit420.

The test register unit410generates a test code tcode<0:5> in an internal register411according to an input signal TDI, TCK, TMS or TRST received from the second input/output terminal500.

The test register unit410can be configured using, for example, the IEEE 1149.1.

The test code tcode<0:5> can be recorded in the internal register411by the input signal TDI, TCK, TMS or TRST received from the second input/output terminal500. In addition, the test code tcode<0:5> can be recorded in the internal register411by a test result tres<0:5> generated as the memory device100performs a test mode. The embodiment for setting the internal register will be described later.

The test logic unit420generates test control signals MRSCMD and FADD<0:3> according to the test code tcode<0:5> stored in the internal register411, and provides the generated test control signals to the memory device100.

For example, the test logic unit420can generate the test control signal MRSCMD so that the memory device100starts a repair operation in response to the test code tcode<1>. In this case, the test control signal MRSCMD can be configured to include a mode register setting signal.

The test logic unit420can also generate the test control signal FADD<0:3> so that the semiconductor device100performs the repair operation in response to the test code tcode<2:5> stored in the internal register411. In this case, the test control signal FADD<0:3> can be configured to include a fuse address signal.

The memory device100can perform the predetermined test mode (e.g., a repair operation such as an available fuse search operation or rupture operation) in response to the test control signals MRSCMD and FADD<0:3>.

The test logic unit420can be configured to receive the test result tres<0:5> from the memory device100and provide the received test result to the test register unit410. In this case, the test register unit410can be configured to record the test result tres<0:5> in the internal register411and output the test result tres<0:5> recorded in the internal register411to the outside through the second input/output terminal via TDO using the IEEE 1149.1.

Although it has been illustrated inFIG. 2that the test code tcode<0:5> and the test result tres<0:5> are 6-bit signals, the present invention is not limited thereto.

FIG. 3illustrates one embodiment of the predetermined test mode operation based on settings of the internal register411illustrated inFIG. 2.

It is assumed that the memory device100has an electrical fuse for restoring a defective storage element.

The predetermined test mode operation can be configured to include a repair operation such as an available fuse search operation or rupture operation.

The available fuse search operation is an operation of searching for an available electrical fuse among electrical fuses provided to the memory device100.

The rupture operation is an operation of rupturing the available electrical fuse according to a test code.

In order to perform the available fuse search operation, the internal register411can include, for example, a fuse search start register r1, available fuse information registers r2to r5, and a fuse search end register r6.

The fuse search start register r1determines whether the operation of searching the available electrical fuse is to start for the purpose of repair. Thus, the fuse search start register r1can be configured to have a single bit. A value of the fuse search start register r1is recorded by the input signal inputted from the second input/output terminal500.

The test logic unit420illustrated inFIG. 2receives the value of the fuse search start register r1as the test code tcode<0>. Accordingly, the test control signal MRSCMD can be generated so that the memory device100performs the available fuse search operation. For example, when the value of the fuse search start register r1is 1, the test logic unit420can generate the test control signal MRSCMD so that the memory device100performs the available fuse search operation.

The available fuse information registers r2to r5are registers in which information on available electrical fuses is recorded. Values of the available fuse information registers r2to r5are recorded according to the test result tres<0:4> inputted from the memory device100. In the available fuse search operation, the test result tres<0:4> can include information on available electrical fuses and a fuse search end signal.

The available fuse information registers r2to r5are preferably configured to have a storage space of bits (4 bits) respectively corresponding to electrical fuses (e.g., 4) included in the memory device100. For example, the available fuse information registers r2to r5can be configured to have a storage space of 4 bits respectively corresponding to four electrical fuses.

If the memory device100outputs the information on available electrical fuses as the test result tres<1:4> through the available fuse search operation, the values of the available fuse information registers r2to r5, respectively corresponding to the available electrical fuses are recorded as 1. For unavailable fuses, the values of the available fuse information registers r2to r5respectively corresponding to unavailable electrical fuses are recorded as 0.

The fuse search end register r6is a register in which the end of the available fuse search operation is recorded. Thus, the fuse search end register r6can be configured to have a single bit. A value of the fuse search end register r6is recorded by the search result inputted from the memory device100.

For example, if the memory device100outputs an available search operation end signal as the test result tres<0> through the available fuse search operation, the value of the fuse search end register r6is changed from 0 to 1. If the value of the fuse search start register r1is set to 1, the value of the fuse search end register r6is reset to 0.

In order to perform the rupture operation, the internal register411can include a rupture start register r7, rupture object fuse information registers r8to r11, and a rupture end register r12.

The rupture start register r7determines whether the operation of rupturing the electrical fuse is started for the purpose of repair. Thus, the rupture start register r7can be configured to have a single bit. A value of the rupture start register r7is recorded by the input signal TDI, TMS, TCK, or TRST inputted from the second input/output terminal500.

The test logic unit420illustrated inFIG. 2receives the value of the rupture register r7as the test code tcode<1>. Accordingly, the test control signal MRSCMD can be generated so that the memory device100starts the operation of rupturing a corresponding electrical fuse. For example, when the value of the rupture register value r7is 1, the test logic unit420can generate the test control signal MRSCMD so that the memory device100performs the operation of rupturing the corresponding electrical fuse.

The rupture object fuse information registers r8to r11are registers in which addresses of electrical fuses subjected to the rupture operation are recorded. Values of the rupture object fuse information registers r8to r11are recorded by the input signal TDI, TMS, TCK, or TRST inputted from the second input/output terminal500.

The rupture object fuse information registers r8to r11is preferably configured to have a storage space of bits (4 bits) respectively corresponding to electrical fuses (e.g., 4) included in the memory device100. For example, the rupture object fuse information registers r8to r11can be configured to have a storage space of 4 bits respectively corresponding to four electrical fuses.

The values of the rupture object fuse information registers r8to r11, respectively corresponding to electrical fuses subjected to the rupture operation, are recorded as 1. On the contrary, the values of the rupture object fuse information registers r8to r11, respectively corresponding to electrical fuses not subjected to the rupture operation, are recorded as 0.

The test logic unit420receives the values of the fuse information registers r8to r11as the test code tcode<2:5>. Accordingly, the test control signal FADD<0:3> can be generated so that the memory device100ruptures a corresponding electrical fuse.

The rupture end register r12is a register in which the end of the rupture operation is recorded. Thus, the rupture end register r12can be configured to have a single bit. A value of the rupture end register r12is recorded by the search result inputted from the memory device100.

For example, if the memory device100outputs an available fuse search operation end signal as the test result tres<5> through the available fuse search operation, the value of the rupture end register r12is changed from 0 to 1. If the value of the rupture register r7is set to 1, the value of the rupture end register r12is reset to 0.