Liquid crystal display with plural gate lines and pairs of pixels

A liquid crystal display (LCD) includes a substrate; first and second pixel rows formed on the substrate and including a plurality of pixels; a first gate line extending in a row direction on the substrate and connected with the first pixel row; a second gate line extending in the row direction on the substrate, connected with the first pixel row; a third gate line extending in the row direction on the substrate, connected with the second pixel row, and adjacent to the second gate line; a fourth gate line extending in the row direction on the substrate, connected with the second pixel row; a plurality of data lines extending in a column direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first and fourth gate lines and applying gate signals to the first and fourth gate lines; and a second gate driver connected with the second and third gate lines and applying gate signals to the second and third gate lines.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims priority to Korean Patent Application No. 10-2005-0104176, filed in the Korean Intellectual Property Office, on Nov. 2, 2005, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

(a) Technical Field

The present disclosure relates to a liquid crystal display (LCD), and more particularly to a device and method that reduces flickers and blurs in the LCD during display.

(b) Discussion of the Related Art

The LCD, one of the most commonly used flat panel displays, includes two display panels with field generating electrodes such as a pixel electrode and a common electrode formed thereon, and a liquid crystal layer formed therebetween. In the LCD, a voltage is applied to the field generating electrodes to generate an electric field on the liquid crystal layer to determine alignment of liquid crystal molecules of the liquid crystal layer and control polarization of incident light, thereby allowing display of images.

The LCD also includes switching elements connected with pixel electrodes and a plurality of signal lines such as gate lines and data lines for controlling the switching elements to apply a voltage to the pixel electrodes. The gate lines transfer gate signals generated by a gate driving circuit, the data lines transfer data voltages generated by a data driving circuit, and the switching elements transfer data voltages to the pixel electrodes according to the gate signals.

A gate driving circuit and a data driving circuit may be directly mounted as a plurality of IC chips on a display panel or mounted on a flexible circuit film attached to a display panel. The IC chips represent a high percentage of the fabrication cost of the LCD. For a large-scale LCD with a high resolution, because the data driver IC chips are expensive as compared to the gate driving circuit chips, the number of data driver ICs needs to be reduced

The cost of the gate driving circuit can be reduced by integrating it together with the gate line, the data line, and the switching element. However, the complex structure of the data driving circuit makes it difficult to integrate the data driving circuit with the display panel, so it is important to reduce the number of data driving circuits.

Pixels of an LCD include parasitic capacitance when the signal lines overlap. The parasitic capacitance causes a kickback voltage when a gate-on voltage becomes a gate-off voltage, after a data voltage is applied. The kickback voltage causes a slight reduction in the level of the data voltage. When the next gate-on voltage is changed to the gate-off voltage, the data voltage is further reduced due to the kickback voltage. This causes a difference between a positive polarity pixel voltage and a negative polarity pixel voltage to occur, causing a screen to flicker and display blurs. Thus, there is a need for an LCD with less flickering and blurring.

SUMMARY OF THE INVENTION

An exemplary embodiment of the present invention provides a liquid crystal display (LCD) including: a substrate; first and second pixel rows formed on the substrate and including a plurality of pixels; a first gate line extending in a row direction on the substrate and connected with the first pixel row; a second gate line extending in the row direction on the substrate, connected with the first pixel row; a third gate line extending in the row direction on the substrate, connected with the second pixel row, and being adjacent to the second gate line; a fourth gate line extending in the row direction on the substrate, connected with the second pixel row; a plurality of data lines extending in a column direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first and fourth gate lines and applying gate signals to the first and fourth gate lines; and a second gate driver connected with the second and third gate lines and applying gate signals to the second and third gate lines.

The first and second gate lines may be arranged with the first pixel row interposed therebetween, and the third and fourth gate lines may be arranged with the second pixel row interposed therebetween.

The first and second gate drivers may be integrated on the substrate.

The first and second gate drivers may be positioned at mutually opposite sides in the row direction.

An exemplary embodiment of the present invention provides an LCD including: a substrate; a plurality of first and second pixel rows formed on the substrate and including a plurality of pixels; a group of first gate lines connected with the first pixel row and including a first upper gate line and a first lower gate line; a group of second gate lines connected with the second pixel row and including a second upper gate line and a second lower gate line; a plurality of data lines extending in a row direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first upper gate line and the second lower gate line; and a second gate driver connected with the first lower gate line and the second upper gate line.

The first and second gate drivers may be integrated on the substrate.

The first and second gate drivers may be positioned at mutually opposite sides in the row direction.

The group of first gate lines may be repeated every one or more rows, and the group of second gate lines may be subsequently repeated every one or more rows.

The group of first gate lines and the group of second gate lines may be alternately adjacent.

Two of the pixels arranged adjacent in the row direction between two adjacent data lines may each be connected to the same one of the data lines.

Two of the pixels that are adjacent in a column direction may each be connected to a different one of the data lines.

A switching element for two of the pixels arranged adjacent in the row direction between two data lines may be connected with the first and second gate lines.

Positions of switching elements for two of the pixels arranged adjacent in the row direction between two adjacent data lines may be substantially the same.

An exemplary embodiment of the present invention provides a method of forming an LCD panel comprising the steps of forming a substrate, forming a first row of pixels on the substrate, forming a first gate line above the first row of pixels and a second gate line below the first row of pixels, wherein the first gate line and the second gate line are each connected to the first row of pixels, forming a second row of pixels on the substrate, forming a third gate line above the second row of pixels and a fourth gate line below the second row of pixels, wherein the third gate line and the fourth gate line are each connected to the second row of pixels, forming a plurality of date lines on the substrate in columns, wherein each of the data lines is disposed every two pixels of the first row of pixels, forming a first gate driver connected with the first and fourth gate lines, and forming a second gate driver connected with the second and third gate lines.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

An LCD according to an exemplary embodiment of the present invention will be described with reference toFIGS. 1,2, and3A.

FIG. 1is a block diagram showing a liquid crystal display (LCD) according to an exemplary embodiment of the present invention,FIG. 2is an equivalent circuit diagram of the LCD according to an exemplary embodiment of the present invention, andFIG. 3Ais a view showing a spatial arrangement of pixels and signal lines of the LCD according to an exemplary embodiment of the present invention.

With reference toFIGS. 1 and 2, the LCD includes a liquid crystal panel assembly300, a pair of gate drivers400R and400L and a data driver500connected with the liquid crystal panel assembly300, a gray voltage generator800connected with the data driver500, and a signal controller600for controlling them.

The liquid crystal panel assembly300includes a plurality of signal lines G1-G2nand D1-Dm, and a plurality of pixels PX connected with the signal lines and arranged substantially in a matrix. Referring toFIG. 2, the liquid crystal panel assembly300includes lower and upper panels100and200and a liquid crystal layer3.

The signal lines include a plurality of gate lines G1-G2nfor transferring gate signals (also called scanning signals) and a plurality of data lines D1-Dmfor transferring data signals. The gate lines G1-Gnextend substantially in a row direction and are almost parallel with each other, and the data lines D1-Dmextend substantially in a column direction and also almost parallel with each other.

Each pixel PX includes a switching element Q connected with the signal lines, and a liquid crystal capacitor Clc and storage capacitor Cst connected thereto. The storage capacitor Cst is optional.

The switching element Q is a three-terminal element such as a thin film transistor provided in the lower panel100. To the switching element Q, a control terminal is connected with the gate line G1, an input terminal is connected with the data line Dj, and an output terminal is connected with the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc includes a pixel electrode191of the lower panel100and a common electrode270of the upper panel200as two terminals, and the liquid crystal layer3between the two electrodes191and270serves as a dielectric. The pixel electrode191is connected with the switching element Q, and the common electrode270is formed on the entire surface of the upper panel200and receives a common voltage Vcom. Although not illustrated inFIG. 2, the common electrode270may be provided on the lower panel100, and at least one of the two electrodes191and270may have a linear or bar shape.

The storage capacitor Cst, serving as an assistant to the liquid crystal capacitor Clc, is formed as a separate signal line (not shown) provided on the lower panel100. The storage capacitor Cst and the pixel electrode191overlap with an insulator interposed therebetween. A predetermined voltage such as a common voltage Vcom is applied to the separate signal line. The storage capacitor Cst can be formed as the pixel electrode191overlaps with an immediately previous gate line at the medium of the insulator.

As shown inFIG. 3A, each pair of gate lines Giand Gi+1, Gi+2and Gi+3, . . . is disposed above and below one row of pixel electrodes191. Each of data lines Dj, Dj+1, . . . , Dj+6is disposed between two columns of the pixel electrodes191. One data line is disposed between a pair of pixel arrays. Two pixels disposed between two adjacent data lines is called a pair of unit pixels.

The pairs of gate lines Giand Gi+1, . . . , G6and Gi+7positioned above and below the pixel electrodes191are connected with corresponding pixel electrodes191through switching elements Q disposed above or below the pixel electrodes191.

In the odd-numbered rows of pixels PXr1and PXr3, centering on each of the data lines Dj, Dj+1, . . . , Dj+6, the left switching elements Q are connected with the upper gate lines Gi, Gi+4and the right switching elements Q are connected with the lower gate lines Gi+1, Gi+5. In the even-numbered rows of pixels PXr2and PXr4, the upper gate lines Gi+2, Gi+6and the lower gate lines Gi+3, Gi+7are connected with the switching elements Q in the opposite manner to those of the odd-numbered rows of pixels. While centering on each of the data lines Dj, Dj+1, . . . , Dj+6, the right switching elements Q are connected with the upper gate lines Gi+2, Gi+6and the left switching elements Q are connected with the lower gate lines Gi+3, Gi+7.

In the odd-numbered rows of pixels PXr1and PXr3, centering on the data lines Dj, Dj+1, . . . , Dj+6, the pixel electrodes191positioned at the left side of each data line are connected with immediately adjacent data lines through the switching elements Q and the pixel electrodes191positioned at the right side of each data line are connected with adjacent data lines through the switching elements Q. In the even-numbered rows of pixels PXr2and PXr4, centering on the data lines Dj, Dj+1, . . . , Dj+6, the pixel electrodes191positioned at the left side of each data line are connected with immediately previous data lines through the switching elements Q and the pixel electrodes191positioned at the right side of each data line are connected with immediately adjacent data lines through the switching elements Q.

Referring toFIG. 3A, the positions of the switching elements Q are changed at each pixel row. In the odd-numbered rows of pixels PXr1and PXr3, as for the pixels positioned at the left side of each of the data lines Dj, Dj+1, . . . , Dj+6, the switching elements Q are formed at an upper end portion of the right side, and as for the pixels positioned at the right side of each of the data lines Dj, Dj+1, . . . , Dj+6, the switching elements Q are formed at a lower end portion of the right side.

In the even-numbered rows of pixels PXr2and PXr4, the positions of the switching elements Q of the pixels are opposite to those of the adjacent odd-numbered rows of pixels. In the even-numbered rows of pixels PXr2and PXr4, the switching elements Q are formed at the lower end portion of the left side of the pixels positioned at the left side of each of the data lines Dj, Dj+1, . . . , Dj+6, and the switching elements Q are formed at the upper end portion of the left side of the pixels positioned at the right side of each of the data lines Dj, Dj+1, . . . , Dj+6.

The positions of the switching elements Q are changed at every row of pixels PXr1-4to shorten the length of connections between the switching elements Q formed at the pixels and the data lines Dj, Dj+1, . . . , Dj+6as much as possible.

With respect to the connections between the pixel electrodes191and the data lines Dj, Dj+1, . . . , Dj+6as shown inFIG. 3A, the switching elements Q of the pair of unit pixels are connected with the same data lines in each row of pixels. In the odd-numbered rows of pixels, the switching elements Q of the pair of unit pixels are connected with the data lines positioned at the right side, and in the even-numbered rows of pixels, the switching elements Q of the pair of unit pixels are connected with the data lines positioned at the left side.

The arrangement shown inFIG. 3Ais merely an example. The connections between the pixel electrodes191in the odd-numbered rows and the even-numbered rows and the data lines can be changed, and other connection relationships therebetween are possible.

For a color display, each pixel PX displays one of the primary colors (spatial division) or pixels PX alternately display the primary colors over time (temporal division), so that a desired color can be generated by the spatial or temporal sum of the primary colors. The primary colors can be, for example, red, green, and blue.FIG. 2shows an example of spatial division in which each pixel PX includes a color filter230that displays one of the primary colors at a region of the upper panel200corresponding to the pixel electrode191. Although not illustrated inFIG. 2, a color filter can be formed above or below the pixel electrode191of the lower panel.

In addition, at least one polarizer (not shown) for polarizing light is attached on an outer surface of the liquid crystal panel assembly300.

Referring back toFIG. 1, the gray voltage generator800generates two pairs of gray voltages (or a set of reference gray voltages) related to transmittance of the pixels PX. One pair of gray voltages has a positive value with respect to the common voltage Vcom and the other pair of gray voltages has a negative value.

The gate drivers400L and400R are first and second gate drivers400L and400R respectively disposed at the right and left sides of the liquid crystal panel300. The gate drivers400L and400R are connected with the gate lines G1-G2nand apply gate signals including a combination of the gate-on voltage Von and the gate-off voltage Voff to the gate lines G1-G2n.

Referring toFIG. 3A, the gate line Gipositioned above the first row of pixels PXr1is connected with the first gate driver400L, and the gate line Gi+1positioned below the first row of pixels PXr1is connected with the second gate driver400R. Connections between the gate lines Gi+2, Gi+3of the second row of pixels PXr2and the first and second gate drivers400L and400R are the same as those of the first row of pixels PXr1.

Connections between the gate lines Gi+4, Gi+5, Gi+6, Gi+7of the third and fourth rows of pixels PXr3and PXr4are the opposite to those of the first and second rows of pixels PXr1and PXr2. The gate lines Gi+4and Gi+6positioned above the third and fourth rows of pixels PXr3and PXr4are connected with the second gate driver400R, and the gate lines Gi+5and Gi+7positioned below the third and fourth rows of pixels PXr3and PXr4are connected with the first gate driver400L.

Referring toFIG. 3A, the first and second rows of pixels PXr1and PXr2and the first and second gate drivers400L and400R are called a first group pixel row, and the third and fourth rows of pixels PXr3and PXr4and the gate drivers400L and400R are called a second group pixel row.

The liquid crystal panel inFIG. 3Ahas a structure such that the two rows of pixels of the first group are repeated, and successively, the two rows of pixels of the second group are repeated. Although not shown inFIG. 3A, the structure is repeated in the rows of pixels starting from the fifth row of pixels.

InFIG. 3A, the pixel rows of the first group and the pixel rows of the second group are repeated twice, but the present invention is not limited thereto, for example, the pixel rows of the first group and the pixel rows of the second group can be repeated three or four times. When the overall number of gate lines is 2n (n=1, 2, 3, 4 . . . ), the pixel rows of the first group can be continuously repeated a maximum of ‘n’ times, and subsequently, the pixel rows of the second group can be repeated a maximum of ‘n’ times.

The gate drivers400L and400R are integrated together with the signal lines G1-G2nand D1-Dmand a TFT switching element Q, or the like, on the liquid crystal panel assembly300. The gate drivers400L and400R can be directly mounted as an integrated circuit (IC) chip on the panel assembly300, can be mounted on a flexible printed circuit film (not shown) so as to be attached as a TCP (Tape Carrier Package) on the liquid crystal panel assembly300, or can be mounted on a printed circuit board (not shown).

The data driver500is connected with the data lines D1-Dmof the liquid crystal panel assembly300, selects a gray voltage from the gray voltage generator800, and applies the selected gray voltage as a data signal to the data lines D1-Dm. When the gray voltage generator800does not provide all the voltages with respect to every gray level, but only provides a predetermined number of reference gray voltages, the data driver500generates gray voltages with respect to all gray levels by dividing the reference gray voltages, and selecting a data signal among them.

The signal controller600controls the gate drivers400L and400R and the data driver500.

The drivers, i.e., the data driver500, the signal controller600and the gray voltage generator800, can be directly mounted as at least one IC chip on the liquid crystal panel assembly300, can be mounted on the flexible printed circuit film (not shown) so as to be attached as the TCP on the liquid crystal panel assembly300, or can be mounted on the PCB (not shown), respectively. Alternatively, the drivers500,600, and800can be integrated together with the signal lines G1-G2nand D1-Dmand the TFT switching elements Q on the liquid crystal panel assembly300. In addition, the drivers400,500,600, and800can be integrated as a single IC chip, and at least one of these circuits can be positioned outside the single IC chip.

The signal controller600receives input image signals R, G, and B and input control signals for controlling display of the input image signals from an external graphics controller (not shown). The input control signals may include, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, or a data enable signal DE.

The signal controller600appropriately processes the input image signals R, G, and B according to operational conditions of the liquid crystal panel assembly300based on the input image signals R, G, and B and the input control signals, generates a gate control signal CONT1and a data control signal CONT2, and transmits the gate control signal CONT1to the gate drivers400L and400R and the data control signal CONT2and the processed image signal DAT to the data driver500.

The gate control signal CONT1includes a scanning start signal STV for instructing start of scanning, and at least one clock signal for controlling an output period of the gate-on voltage Von. The gate control signal CONT1may additionally include an output enable signal OE for limiting a duration of the gate-on voltage Von.

The data control signal CONT2includes a horizontal synchronization start signal STH for indicating that image data has begun transmission to one row of pixels PX, and a load signal LOAD for indicating application of data signals to the data lines D1-Dm, and a data clock signal HCLK. The data control signal CONT2may additionally include an inversion signal RVS for inverting polarity of a voltage of a data signal with respect to the common voltage Vcom (which is called ‘polarity of a data signal’).

The data driver500receives the digital image signal DAT with respect to one row of pixels PX according to the data control signal CONT2received from the signal controller600, selects a gray voltage corresponding to each digital image signal DAT, converts the digital image signal DAT into an analog data signal, and applies it to a corresponding data line D1-Dm.

The gate drivers400L and400R apply the gate-on voltage Von to the gate lines G1-G2naccording to the gate control signal CONT1received from the signal controller600, to turn on switching elements Q connected with the gate lines G1-G2n. Then, the data signal that has been applied to the data lines D1-Dmis applied to the corresponding pixels PX through the switching elements Q that have been turned on.

The difference between a voltage of the data signal applied to the pixels PX and the common voltage Vcom appears as a charge voltage of the liquid crystal capacitor Clc, namely, as a pixel voltage. Arrangement of liquid crystal molecules is changed according to the size of the pixel voltage, and polarization of light that passes through the liquid crystal layer3is changed accordingly. The change in the polarization appears as a change in transmittance of light by a polarizer attached on the display panel assembly300.

This process is repeatedly performed by units of one horizontal period (namely, ‘1H’ which is equivalent to one period of the horizontal synchronization signal Hsync and the data enable signal DE), whereby the gate-on voltage Von can be sequentially applied to all the gate lines G1-G2nto apply the data signals to all the pixels PX, thereby displaying an image of one frame.

When one frame is finished, the next frame is started and a state of the inversion signal RVS applied to the data driver500is controlled (‘frame inversion’) so that polarity of the data signals applied to each pixel PX can be opposite to the polarity of a previous frame. Even in one frame, the polarity of a data signal flowing through one data line can be changed according to characteristics of the inversion signal RVS (e.g., row inversion, dot inversion), or the polarity of a data signal applied to one row of pixels can be different (e.g., column inversion, dot inversion).

The driving operation of the LCD according to an exemplary embodiment of the present invention will be described in detail with reference toFIGS. 3B and 3C.

FIGS. 3B and 3Cshow mutually inverted operations of the LCD ofFIG. 3A.

In the LCD inFIGS. 3B and 3C, units of pixels ofFIG. 3Aare disposed 2×2.

When the gate-on voltage Von is applied to the gate drivers400L and400R according to the gate control signal CONT1received from the signal controller600, the gate-on voltage Von is applied to one of a pair of the gate lines G1-G2nand switching elements Q connected thereto are turned on. Subsequently, the gate-on voltage Von is also applied to the other pair of gate lines G1-G2nand switching elements Q connected to the gate line are also turned on. Then, the data signals that have been applied to the data lines D1-Dmare applied to the corresponding pixels PX through the turned-on switching elements Q.

However, due to parasitic capacitance existing between the gate lines G1-G2nand the pixel electrode191, when the gate-on voltage is lowered to the gate-off voltage, the data voltage is slightly reduced, generating a first kickback voltage Vkb.

Subsequently, when the next gate-on voltage is lowered to the gate-off voltage, a second kickback voltage Vkb is generated.

At the pixel electrode191where the second kickback voltage Vkb is generated, a pixel electrode voltage is adjusted closer to the common voltage Vcom at a portion that is inverted from negative (−) polarity to positive (+) polarity, so that the corresponding pixels PX become brighter than a normal state.

At the pixel electrode191where the second kickback voltage Vkb is generated, a pixel electrode voltage is adjusted away from the common voltage Vcom at a portion that is inverted from positive (+) polarity to negative (−) polarity, so that the corresponding pixels PX become darker than the normal state.

With reference toFIG. 3B, among pixels where the second kickback voltage is generated, pixels PX1indicated by the dotted lines are inverted from negative (−) polarity to positive (+) polarity and thus become brighter than the normal state, while pixels PXb indicated by the solid lines are inverted from the positive (+) polarity to negative (−) polarity and thus become darker than the normal state. When a frame is inverted, the state shown inFIG. 3Bis changed to a state shown inFIG. 3C. The pixels PX1that were bright inFIG. 3Bbecome dark inFIG. 3C, and the pixels PXb that were dark inFIG. 3Bbecome bright inFIG. 3C. As the frames are repeated, the LCD ofFIG. 3Aundergoes the change in states as shown inFIGS. 3B and 3C.

If the pixels PX1that are brighter than the normal state and the pixels PXb that are darker than the normal state are present continuously in a row direction, vertical line blurs with different luminances appear. In addition, although the frames are inverted, if a user changes their head position or moves their eyes, vertical blurs appear such that vertical lines appear to be moving. In comparison, in the LCD according to the present exemplary embodiment, the pixels PX1and PXb, which have different luminances as they become brighter or darker than the normal state as shown inFIGS. 3B and 3C, are suitably mixed to be displayed in the display panel. Thus, no display blur occurs in the horizontal or vertical direction.

FIG. 4is a view showing a spatial arrangement of pixels and signal lines of the LCD according to an exemplary embodiment of the present invention.

With reference toFIG. 4, in the LCD, pairs of gate lines Giand Gi+1, Gi+2and Gi+3, . . . , Gi+6and Gi+7are arranged above and below one row of pixel electrodes191. Each of the data lines Dj, Dj+1, . . . , Dj+6is arranged between two columns of pixel electrodes191. The pairs of gate lines Giand Gi+1, . . . , G6and Gi+7positioned above and below the pixel electrodes191are connected with corresponding pixel electrodes191through the switching elements Q disposed above or below the pixel electrodes191. In the odd-numbered rows of pixels PXr1and PXr3, centering on each of the data lines Dj, Dj+1, . . . , Dj+6, the left switching elements Q are connected with the upper gate lines Gi, Gi+4and the right switching elements Q are connected with the lower gate lines Gi+1, Gi+5. In the even-numbered rows of pixels PXr2and PXr4, the upper gate lines Gi+2, Gi+6and the lower gate lines Gi+3, Gi+7are connected with the switching elements Q in the opposite manner to those of the odd-numbered rows of pixels. In the odd-numbered rows of pixel electrodes191, centering on the data lines Dj, Dj+1, . . . , Dj+6, the pixel electrodes191positioned at the left side of each data line are connected with immediately adjacent data lines through the switching elements Q and the pixel electrodes191positioned at the right side of each data line are connected with adjacent data lines through the switching elements Q. In the even-numbered rows of pixel electrodes191, centering on the data lines Dj, Dj+1, . . . , Dj+6, the pixel electrodes191positioned at the left side of each data line are connected with immediately previous data lines through the switching elements Q and the pixel electrodes191positioned at the right side of each data line are connected with the immediately adjacent data lines through the switching elements Q. In each row of pixels, switching elements Q of the pair of unit pixels are connected with the same data lines.

However, unlike the LCD shown inFIG. 3A, in the LCD shown inFIG. 4, a first group pixel row, in which the gate line positioned above one row of pixels is connected with the first gate driver400L and the gate line positioned below one row of pixels is connected with the second gate driver400R, and a second group pixel row, in which the gate line positioned above one row of pixels is connected with the second gate driver400R and the gate line positioned below one row of pixels is connected with the first gate driver400L, are disposed adjacent to one another. Another second group pixel row is disposed to adjacent to the second group pixel row, and subsequently, two different types of rows of pixels among the first group or second group pixel rows are repeatedly disposed.

InFIG. 4, the first group pixel row is disposed at an uppermost position, but the second group pixel row can also be disposed at the uppermost position, or the positions of the first group pixel row and the second group pixel row can be changed on the entire display panel. In addition, the first group pixel row and the second group pixel row are repeated by units of two pixel rows, but the present invention is not limited thereto, for example, the first group pixel row and the second group pixel row can be repeated by units of more pixel rows within the total number of gate lines.

FIG. 5Ais a view showing a spatial arrangement of pixels and signal lines of an LCD according to an exemplary embodiment of the present invention, andFIGS. 5B and 5Cshow how the LCD ofFIG. 5Ais driven.

In the LCD as shown inFIG. 5, each pair of gate lines Giand Gi+1, Gi+2and Gi+3, . . . are disposed above and below one row of pixel electrodes191.

Each of data lines Dj, Dj+1, . . . , Dj+6is disposed between two columns of pixel electrodes191.

The pairs of gate lines Giand Gi+1, . . . , G6and Gi+7positioned above and below the pixel electrodes191are connected with corresponding pixel electrodes191through the switching elements Q disposed above or below the pixel electrodes191.

In the odd-numbered rows of pixels PXr1and PXr3, centering on each of the data lines Dj, Dj+1, . . . , Dj+6, the left switching elements Q are connected with the upper gate lines Gi, Gi+4and the right switching elements Q are connected with the lower gate lines Gi+1, Gi+5.

In the even-number rows of pixels PXr2and PXr4, the upper gate lines Gi+2, Gi+6and the lower gate lines Gi+3, Gi+7are connected with the switching elements Q in the opposite manner to those of the odd-numbered rows of pixels.

In the odd-numbered rows of pixel electrodes191, centering on the data lines Dj, Dj+1, . . . , Dj+6, the pixel electrodes191positioned at the left side of each data line are connected with immediately adjacent data lines through the switching elements Q and the pixel electrodes191positioned at the right side of each data line are connected with adjacent data lines through the switching elements Q.

In the even-numbered rows of pixel electrodes191, centering on the data lines Dj, Dj+, . . . , Dj+6, the pixel electrodes191positioned at the left side of each data line are connected with immediately previous data lines through the switching elements Q and the pixel electrodes191positioned at the right side of each data line are connected with the immediately adjacent data lines through the switching elements Q.

In each row of pixels, switching elements Q of the pair of unit pixels are connected with the same data lines.

However, unlike the LCDs shown inFIG. 3AandFIG. 4, in the LCD shown inFIG. 5A, a first group pixel row, in which the gate line positioned above one row of pixels is connected with the first gate driver400L and the gate line positioned below one row of pixels is connected with the second gate driver400R, and a second group pixel row, in which the gate line positioned above one row of pixels is connected with the second gate driver400R and the gate line positioned below one row of pixels is connected with the first gate driver400L, are disposed adjacent to one another.

With reference toFIGS. 5B and 5C, among pixels where the second kickback voltage is generated, pixels PX1indicated by the dotted lines are inverted from negative (−) polarity to positive (+) polarity and thus become brighter than the normal state, while pixels PXb indicated by the solid lines are inverted from the positive (+) polarity to negative (−) polarity and thus become darker than the normal state.

InFIG. 5B, the pixels PX1that are brighter than the normal state and the pixels PXb that are darker than the normal state are adjacently repeated in one row.

When the frame is inverted, the state as shown inFIG. 5Bis changed to a state as shown inFIG. 5C.

The pixels PX1that were bright inFIG. 5Bbecome dark inFIG. 5C, and the pixels PXb that were dark inFIG. 5Bbecome bright inFIG. 5C.

As the frames are repeated, the LCD ofFIG. 5Aundergoes the change in the states as shown inFIGS. 5B and 5C.

Since the pixels each with a different luminance are adjacently disposed in one pixel array, the difference in luminance is appropriately canceled out to prevent generation of vertical or horizontal blur.

FIG. 6is a layout view showing an LCD according to an exemplary embodiment of the present invention, andFIGS. 7 to 9are cross-sectional views taken along lines VII-VII, VIII-VIII, and IX-IX of the LCD ofFIG. 6.

With reference toFIGS. 6 to 9, a liquid crystal panel assembly according to the exemplary embodiment of the present invention includes a TFT array panel100, a common electrode panel200, and a liquid crystal layer3interposed between the two panels100and200.

A plurality of gate conductors including pairs of first and second gate lines121aand121band a plurality of storage electrode lines131are formed on an insulation substrate110which is made of, for example, transparent glass or plastic.

The first and second gate lines121aand121btransfer gate signals and extend mainly in a horizontal direction. The first gate lines121aare positioned above the second gate lines121b

The first gate lines121ainclude a plurality of first gate electrodes124athat protrude downward and a large end portion129for connection with a different layer or the gate drivers400L and400R.

The second gate lines121binclude a plurality of second gate electrodes124bthat protrude upward and a large end portion129for a connection with a different layer or the gate drivers400L and400R.

When the gate drivers400L and400R are integrated on the substrate100, the gate lines121aand121bcan be extended to be directly connected thereto.

The storage electrode lines131receive a predetermined voltage such as the common voltage Vcom, and are separated from the gate lines121aand121b.

Each of the storage electrode lines131includes a set of a plurality of storage electrodes133a,133b,133c, and133dthat are connected with each other to form a pair of rectangular shapes, and a pair of storage electrode connection portions135aand135b.

A set of storage electrodes133a-133dincludes a pair of first and second storage electrodes133aand133bthat extend mainly in the horizontal direction, and a pair of third storage electrodes133cthat extend mainly in the vertical direction with the fourth storage electrode133dpositioned therebetween and extending in a vertical direction.

Centering on the fourth storage electrode133d, the first to third storage electrodes133a-133care disposed at both sides of the fourth storage electrode133d, forming the rectangular shapes by sharing the fourth storage electrode133d. The two rectangular shapes have a 180 degree rotation symmetrical relation based on the center of the fourth storage electrode133d.

The storage electrode connection portions135aand135bconnect the adjacent storage electrodes133cof the two adjacent sets of the storage electrodes133a-133d, and the storage electrode133ais bent near the first gate electrode124a.

The shapes and dispositions of the storage electrodes133aand133band the storage electrode lines131can be modified to various forms.

The gate conductors121a,121b, and131can be made of, for example, a metal such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), and alloys thereof.

The gate conductors121a,121b, and131may also have a multi-layered structure including two or three conductive layers (not shown) each having different physical properties.

One of the conductive layers can be made of a material with low resistivity, such as Al, Ag, Cu, or alloys thereof to reduce a signal delay or a voltage drop.

Another one of the conductive layers can be made of, for example, a material such as Mo, Cr, Ta, Ti, and alloys thereof that have good physical, chemical, and electrical contact characteristics with a different material, for example, ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).

Examples of such combinations may include a combination of a lower chromium layer and an upper aluminum (alloy) layer, and a combination of a lower aluminum (alloy) layer and an upper molybdenum (alloy) layer, and a combination of a lower molybdenum (alloy) layer and a middle aluminum (alloy) layer and an upper molybdenum (alloy) layer.

In addition, the gate conductors121a,121b, and131can be made of various other metals or conductors.

The sides of the gate conductors121a,121b, and131are sloped to the surface of the substrate110, and the slope angle may be within the range of about 30° to about 80°.

A gate insulating layer140made of silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride(SiONx) is formed on the gate conductors121a,121b, and131.

A plurality of semiconductor islands152,154a, and154bmade of, for example, hydrogenated amorphous silicon (a-Si:H) or polycrystalline silicon, are formed on the gate insulating layer140.

The semiconductor islands154aand154bare positioned on the gate electrodes124aand124b, respectively, to cover them, and extend to also cover the gate lines121aand the storage electrode connection portion135a.

In addition, the semiconductor island152covers the storage electrode connection portion135b.

A plurality of ohmic contact islands163a, and165aare formed on the first semiconductor island154a.

The ohmic contact islands163aand165acan be made of a material such as n+ hydrogenated amorphous silicon in which an n-type impurity such as phosphor is doped with a high density, or silicide.

The ohmic contact islands163aand165aare disposed as pairs on the semiconductor island154a, and other ohmic contact islands (not shown) are disposed as pairs on the semiconductor island154b.

The sides of the semiconductor islands154aand154band the ohmic contact islands163aand165aare also sloped to the surface of the substrate110, and the slope angle may be within the range of about 30° to about 80°.

Data conductors including a plurality of data lines171and a pair of first and second drain electrodes175aand175bare formed on the ohmic contact islands163aand165aand the gate insulating layer140.

The data lines171transfer data signals and extend mainly in the vertical direction to cross the gate lines121aand121band the storage electrode line131. The data lines171include a pair of first and second ‘C’-shaped source electrodes173aand173bthat extend toward the first and second gate electrodes124aand124b, and a large end portion179for connection with a different layer or the data driver500.

The first and second drain electrodes175aand175bare separated from each other and are also separated from the data lines171. The first and second drain electrodes175aand175bface the first and second source electrodes173aand173bcentering on the first and second gate electrodes124aand124b. The first and second drain electrodes175aand175beach include one end portion in a bar shape.

The extending portions177aand177boverlap with the storage electrodes133aand133b, respectively.

The bar-type end portions of the drain electrodes175aand175bare partially surrounded by source electrodes173aand173b.

The first and second gate electrodes124aand124b, the first and second source electrodes173aand173b, and the first and second drain electrodes175aand175bconstitute first and second TFTs together with the first and second semiconductor islands154aand154b. A channel of the first and second TFTs is formed at the first and second semiconductor islands154aand154bbetween the source electrodes173aand173band the first and second drain electrodes175aand175b.

The data conductors171,175a, and175bmay be made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, and their alloys, and can have a multi-layered structure including a refractory metal layer (not shown) and a low-resistance conductive layer (not shown).

Examples of the multi-layered structure may include a dual-layer of a lower chromium or molybdenum (alloy) layer and an upper aluminum (alloy) layer, and a triple-layer of a lower molybdenum (alloy) layer, an intermediate aluminum (alloy) layer, and an upper molybdenum (alloy) layer.

The data conductors171,175a, and175bcan also be made of various other metals or conductors.

The sides of the data conductors171,175a, and175bmay be sloped to the surface of the substrate110at a slope angle within the range of about 30° to about 80°.

The ohmic contact islands163aand165aare present between the lower semiconductor islands154aand154band the upper data conductors171,175a, and175bto lower contact resistance therebetween.

Some portions of the semiconductor islands154aand154b, including a portion between the source electrodes173aand173band the drain electrodes175aand175b, are exposed without being covered by the data conductors171,175a, and175b.

A passivation layer180is formed on the data conductors171,175a, and175b, and on the exposed portions of the semiconductor islands154aand154b.

The passivation layer180may be made of, for example, an inorganic insulator or an organic insulator, and may have a planarized surface.

The organic insulator may have a dielectric constant of 4.0 or less, and may have photosensitivity.

The passivation layer180may also have a dual-layer structure of a lower inorganic layer and an upper organic layer so that it may not do harm to the exposed portions of the semiconductor islands154aand154b, while sustaining the insulation characteristics of the organic layer.

At the passivation layer180, there are formed a plurality of contact holes182exposing the end portions179of the data lines171, and pairs of contact holes185aand185bexposing the extending portions177aand177bof the first and second drain electrodes175aand175b.

At the passivation layer180and the gate insulating layer140, there are formed a plurality of contact holes181exposing the end portions129of the gate lines121aand121b.

A plurality of pixel electrodes191and a plurality of contact assistant81and82are formed on the passivation layer180, and can be made of a transparent conductive material such as ITO or IZO, or a reflective material such as aluminum, silver, chromium or their alloys.

The pixel electrode191is physically and electrically connected with the drain electrodes175aand175bthrough the contact hole185, and receives a data voltage from the drain electrodes175aand175b.

The pixel electrode191to which the data voltage has been applied, generates an electric field together with a common electrode270of the common electrode panel200, which receives a common voltage, thereby determining a direction of liquid crystal molecules of the liquid crystal layer3interposed between the two electrodes191and270.

Polarization of light that passes through the liquid crystal layer3differs depending on the determined direction of the liquid crystal molecules.

The pixel electrode191and the common electrode270form a capacitor (referred to hereinafter as ‘liquid crystal capacitor’) to sustain the applied voltage even after the TFT is turned off.

The pixel electrode191overlaps with the storage electrode line131including the storage electrodes133a˜133d. A capacitor connected with the pixel electrode191and overlapping with the storage electrode line131is called a storage capacitor, which strengthens voltage storage capability of the liquid crystal capacitor.

The pixel electrode191covers the end portion elongated from the drain electrodes175aand175band the storage electrode133a, and partially overlaps with the storage electrodes133b,133c, and133dsuch that a boundary line of the pixel electrode191is positioned on the storage electrodes133b,133c, and133d.

The storage electrode133bis exposed between the gate lines121aand121band the boundary line of the pixel electrode191, and a voltage change of the pixel electrode191due to parasitic capacitance present between the pixel electrode191and the gate line121acan be reduced.

The contact assistants81and82are connected with the end portions129of the gate lines121aand121band the end portions179of the data line171through the contact holes181and182, respectively.

The contact assistant81and82support adhesion of the end portions129of the gate lines121aand121band the end portions179of the data line171with an external device, and protect them.

A light blocking member220is formed on an insulation substrate210and may be made of a material such as transparent glass or plastic.

The light blocking member220may include a bent portion (not shown) corresponding to a bent side of the pixel electrode191and a rectangular portion (not shown) corresponding to TFTs. The light blocking member220prevents light leakage between pixel electrodes191and defines an opening that faces the pixel electrodes191.

A plurality of color filters230are formed on the substrate210and the light blocking member220.

The color filters230are mostly present within regions surrounded by the light blocking members230, and may extend along the rows of the pixel electrodes191. Each of the color filters230may display one of the three primary colors of red, green, and blue.

An overcoat250is formed on the color filters230and the light blocking member220. The overcoat250can be made of an (organic) insulator, prevents exposure of the color filters230, and provides a smooth surface. The overcoat250is optional. A common electrode270is formed on the overcoat250.

Alignment layers11and21are formed on an inner surface of the display panels100and200, respectively, and can be vertical alignment layers. Polarizers12and22are provided on an outer surface of the display panels100and200, respectively.

The LCD may include a backlight unit (not shown) for providing light to the polarizers12and22, a phase delay layer, display panels100and200, and the liquid crystal layer3.

The liquid crystal layer has negative dielectric anisotropy, and liquid crystal molecules of the liquid crystal layer3are aligned such that their longer axes are perpendicular to the surfaces of the two display panels100and200when there is no electric field.

FIG. 10is a cross-sectional view of an LCD according to an exemplary embodiment of the invention.

As shown inFIG. 10, a liquid crystal panel assembly according to the present exemplary embodiment also includes a lower panel100and an upper panel200that face each other, and a liquid crystal layer3interposed between the two panels.

Referring to the lower panel100, a plurality of gate conductors including a pair of first and second gate lines (not shown) and a plurality of storage electrode lines (not shown) are formed on the insulation substrate110.

Each of the gate lines includes a gate electrode124aand an end portion (not shown), and each storage electrode line includes storage electrodes133aand133b.

A gate insulating layer140is formed on the gate conductors.

A plurality of semiconductor islands154aare formed on the gate insulating layer140, and a plurality of ohmic contact islands163aand165aare formed on the semiconductor islands154a.

Data conductors including a plurality of data lines (not shown) and first drain electrodes175aand second drain electrodes (not shown) are formed on the ohmic contact islands163aand165aand the gate insulating layer140.

The data lines include a plurality of source electrodes173aand end portions (not shown), and the drain electrodes175ainclude a large end portion (not shown).

A passivation layer180is formed on the data conductors175aand an exposed portion of the semiconductor island154a, and a plurality of contact holes185are formed on the passivation layer180and the gate insulating layer140.

A plurality of pixel electrodes191and a plurality of contact assistants (not shown) are formed on the passivation layer180.

An alignment layer11is formed on the pixel electrodes191, the contact assistants, and the passivation layer180.

Referring to the upper panel200, a light blocking member220, a plurality of color filters230, an overcoat250, a common electrode270, and an alignment layer21are formed at a lower portion of an insulation substrate210.

The liquid crystal panel assembly as shown inFIG. 10is different from the liquid crystal panel assembly as shown inFIGS. 6 to 9in that the LCD according to the present exemplary embodiment is constructed such that the common electrode panel200does not have the color filters230but the plurality of color filters230are formed at the lower portion of the passivation layer180of the TFT array panel100.

The color filter230extends in a band along the columns of the pixel electrodes191, and two adjacent color filters230overlap at an upper portion of the data lines.

The overlapping color filters230are formed of an organic layer to insulate the pixel electrodes191and the data lines.

Although the insulating layer180is not formed of an organic layer, no parasitic capacitance is generated at the portion where the pixel electrodes191and the data lines171overlap.

The color filters230can also serve as a light blocking member for preventing light leakage between pixel electrodes191. When the colors filters230are used as the light blocking member, formation of the light blocking member on the common electrode panel200is not necessary, thus simplifying a process of constructing an LCD.

Each of the color filters230include a through hole235for allowing the contact hole185to pass therethrough, and the through hole235is larger than the contact hole185.

The color filters230do not exist at a peripheral area where the end portion129of the gate line121and an end portion of the data line are positioned.

A passivation layer (not shown) may be formed at a lower portion of the color filters230.