Image processing controller and image processing device

A first interface receives image information and an output destination address from a first external device. A second interface transmits image information to a second external device at a lower communication speed than the first interface. A communication path connects the first interface and the second interface to exchange data, on which a first-in first-out memory is provided. Upon the first interface receiving the address, when the second interface is specified as a transmission destination based on the address, a transmitting unit transmits the image information to the second interface through the communication path and the first-in first-out memory.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to and incorporates by reference the entire contents of Japanese priority documents, 2007-102773 filed in Japan on Apr. 10, 2007, 2007-139577 filed in Japan on May 25, 2007, 2008-040259 filed in Japan on Feb. 21, 2008.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image processing controller that includes a plurality of interfaces having different specifications and an image processing device.

2. Description of the Related Art

Conventional image forming apparatuses transfer image data through an engine interface (I/F), mounted on an image processing controller, which is a comparatively low-speed interface such as Peripheral Component Interconnect (PCI). If the PCI is used as an interface between the image processing controller and a chipset of a central processing unit (CPU) in the image forming apparatus, the capacity of the PCI is insufficient to transfer data. Therefore, Accelerated Graphics Port (AGP) is conventionally used. The AGP is an interface specification for a data transfer path between a video card and a main memory, developed by Intel Corporation.

As explained above, a plurality of interfaces such as PCI and AGP are often used for the image forming apparatus. Therefore, a technology for switching the interfaces is proposed as disclosed in Japanese Patent Application Laid-open No. 2003-333232. By using the technology, high-speed transfer becomes possible in a communication path through which a large amount of data is transferred.

Recently, PCI Express (hereinafter, “PCIe”) has been proposed in the computer industry. The PCIe is an interface specification for data transfer at a higher speed than that of the PCI, and is compatible with the PCI at software level.

On the other hand, a request to mount-the high-speed engine I/F such as the PCIe also on an image processing controller tends to be made to improve throughput of data communication.

Moreover, even if a PCIe I/F is mounted on the image processing controller of the image forming apparatus, a PCI I/F is also required depending on a device to be mounted on the image forming apparatus.

The PCIe is capable of data transfer at a higher speed than that of the AGP. Therefore, when the PCIe I/F is mounted on the image processing controller, the AGP can be replaced with the PCIe. This allows the interfaces to be unified so as to be compatible with PCI at software level.

However, in the technology described in Japanese Patent Application Laid-open No. 2003-333232, it is not considered that the interfaces are unified so as to be compatible with the PCI or the PCIe at the software level.

Furthermore, when the PCI and the PCIe are mounted on the image forming apparatus in a simple manner, that is, when only the PCI and the PCIe are mounted thereon, a component such as a switch or a bridge is required to convert data between the PCI and the PCIe, which causes an increase in cost thereof.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided an image processing controller including a first interface that receives image information and an address indicating an output destination of the image information from a first external device; a second interface that transmits image information to a second external device at a communication speed lower than that of the first interface; a communication path that connects the first interface and the second interface to exchange data; a first-in first-out memory provided on the communication path; a third interface that transmits image information to a third external device; a specifying unit that specifies, upon the first interface receiving the address, either one of the second interface and the third interface as a transmission destination of the image information received by the first interface based on the address; and a transmitting unit that transmits, when the second interface is specified as the transmission destination, the image information to the second interface through the communication path and the first-in first-out memory.

Furthermore, according to another aspect of the present invention, there is provided an image processing device including an image processing engine that performs an image processing; an image processing unit that has image processing capability lower than that of the image processing engine; an image storage unit that stores therein image data; and an image processing controller that includes a first interface that receives image information and an address indicating an output destination of the image information from a first external device, a second interface that transmits image information to a second external device at a communication speed lower than that of the first interface, a communication path that connects the first interface and the second interface to exchange data, a first-in first-out memory provided on the communication path, a third interface that transmits image information to a third external device, a specifying unit that specifies, upon the first interface receiving the address, either one of the second interface and the third interface as a transmission destination of the image information received by the first interface based on the address, and a transmitting unit that transmits, when the second interface is specified as the transmission destination, the image information to the second interface through the communication path and the first-in first-out memory.

Moreover, according to still another aspect of the present invention, there is provided an image processing method including first interfacing including receiving image information and an address indicating an output destination of the image information from a first external device; second interfacing including transmitting image information to a second external device at a communication speed lower than that of the first interfacing; connecting the first interfacing and the second interfacing to exchange data through a communication path on which a first-in first-out memory is provided; third interfacing including transmitting image information to a third external device; specifying, upon receiving the address, either one of the second interfacing and the third interfacing as a transmission destination of the image information received at the first interfacing based on the address; and transmitting, when the second interfacing is specified as the transmission destination, the image information to the second interfacing through the communication path and the first-in first-out memory.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Exemplary embodiments of the present invention are explained in detail below with reference to the accompanying drawings. It is noted that the following embodiments are not limited to a case where an image processing controller is mounted on an image forming apparatus, and thus the image processing controller can be mounted on various devices that perform image processing.

FIG. 1is a schematic block diagram of an image processing controller according to a first embodiment and its peripheral devices. An image processing controller100includes a first interface (I/F)101connected to an engine including scanner/plotter, a second interface102connected to option devices in addition to other engine and image processing controller as option, a third interface103connected to a memory, and an interface connected to a hard disk drive (HDD) in an HDD I/F module104(or HDD I/F104). In the image processing controller100, the first I/F101and the second I/F102directly communicate each other through a first-in first-out (FIFO) memory (or FIFO)105and an address converter (or Address Conv.)106. Further, in the image processing controller100, a signal line107ais connected between the first I/F101and an arbiter110, and a signal line107bis connected between the second I/F102and the arbiter110.

As shown inFIG. 1, the image processing controller100allows the third I/F103to perform communication with a ChipSet151, a CPU152, and a memory153. Moreover, the image processing controller100allows the HDD I/F module104to perform communication with an HDD154.

FIG. 2is a diagram of a hardware configuration of an image forming apparatus300that includes the image processing controller. Referring toFIG. 2, an image processing engine301includes the first I/F, while an option controller303as an external controller and an option board304include the second I/F. When these components are connected to the image processing controller100, because the image processing controller100is provided with both the first and the second I/Fs and also with the FIFO memory that accommodates a difference in speed between the interfaces as shown inFIG. 1, there is no need to provide a switch or a bridge to switch between the interfaces.

The image processing engine (or ENGINE)301includes two functions (Scanner/Plotter) such as a scanner engine function and a plotter output engine function.

The scanner engine function of the image processing engine301subjects RGB-color image data read by a charge-coupled device (CCD) sensor to image processing, generates CMYK images of 8 bits for each color, and outputs the CMYK images to the image processing controller100. The image processing performed by the scanner engine function includes edge enhancement of a text area of image data or a smoothing process of a non-text area (picture area).

The plotter output engine function of the image processing engine301subjects the image data received from the image processing controller100to a binarizing process, and outputs the binarized image data to the plotter.

How the image processing controller100is developed to obtain the configuration as shown inFIG. 1is explained below with reference toFIGS. 10 and 11. The configuration for a conventional image processing controller is explained first. Conventionally, image data is transferred using a comparatively low-speed interface such as PCI as an engine I/F mounted on the image processing controller.FIG. 10is a diagram for explaining an image processing controller and its peripheral devices in which image data is transferred through a PCI I/F. As shown inFIG. 10, an image processing engine (or ENGINE)1202and an image processing controller1201are connected to each other through a PCI bus I/F module1211, while the image processing controller1201and a memory1203are connected to each other through an Accelerated Graphics Port (AGP) bus I/F module1212. The reason why the AGP is used is because a path using the AGP between a ChipSet and a memory is an access path from a CPU to a main memory and the capacity of the access path based on the PCI is not large enough to transfer data. The image data follows communication paths1251to1253including the PCI bus and the AGP bus.

Because of this, an image processing controller including a higher-speed engine I/F such as the PCIe is required to improve the throughput of data communication.

FIG. 11is a diagram for explaining an image processing controller that includes a PCIe I/F and a switch device, and its peripheral devices. In the configuration shown inFIG. 11, an interface between an image processing controller1301and an image processing engine (or ENGINE)1302is changed from the PCI to the PCIe. Specifically, both are connected to each other through a PCIe bus I/F module1312. Moreover, because the PCIe can perform data transfer at a speed higher than that of the AGP, by providing a PCIe end point1311, the AGP between ChipSet1304and a memory1303can be changed to the PCIe. Accordingly, specifications can be unified to a specification having compatibility with software for the PCI. As a result, the image data follows communication paths1351to1353according to switching by a PCIe-PCI switch device1305.

As explained above, the PCIe-PCI switch device1305is required to connect to a device such as a facsimile (fax) control unit using the PCI bus, and this causes an increase in manufacturing costs.

Moreover, there may be a case where manufacturers of image forming apparatuses manufacture two types of image forming apparatuses such as ones requiring high manufacturing costs yet capable of high-speed transfer and ones requiring low manufacturing costs yet capable of only low-speed transfer. In this case, another image processing controller for low-speed transfer which does not use the PCIe is also required in addition to the image processing controller capable of high-speed transfer as shown inFIG. 11. In this case, the manufactures have to develop two types of image processing controllers such as the image processing controller for high-speed transfer and the image processing controller for low-speed transfer even if their functions are common. Thus, the development burden is increased, and the development cost thereby tends to be increased.

The image processing controller according to the first embodiment is therefore configured as shown inFIG. 1. The configuration is specifically explained below with reference toFIG. 3that details the configuration shown inFIG. 1. In the example shown inFIG. 3, the image processing controller100is configured so that the image processing engine301is connected to the first I/F101and the option board304is connected to the second I/F102. The option board304may be any device such as a fax control unit.

FIG. 3is a detailed block diagram of the image processing controller according to the first embodiment and its peripheral devices.

The image processing controller100shown inFIG. 3includes a PCIe bus I/F module201, a PCI bus I/F module202, the FIFO memory105, the address converter106, a selector108, the arbiter110, a PCIe end point203, the HDD I/F module104, a direct memory access controller (DMAC)204, a video output module109, DMACs232ato232d, and FIFO memories231ato231d.

As shown inFIG. 3, the image processing controller100includes a first PCIe bus I/F101as the first I/F101provided on the engine side, and a PCI bus I/F102as the second I/F102.

The image processing controller100also includes a second PCIe bus I/F103as the third I/F103provided on the ChipSet side. In the image processing controller100, the second PCIe bus I/F103can be connected to the memory153and the CPU152.

The PCIe bus I/F module201and the PCI bus I/F module202are connected to each other through a first signal line210via the FIFO memory105and the address converter106.

Further, the PCIe bus I/F module201and the arbiter110are connected to each other through a second signal line107aas the signal line107a, and the PCI bus I/F module202and the arbiter110are connected to each other through a third signal line107bas the signal line107b.

The PCIe bus I/F module201includes the first PCIe bus I/F101, a specifying unit211, a first instructing unit212, a first transmitter/receiver213, and a storage unit214, and functions as a tree-structured Root Complex (ROOT) including the PCIe end point203. Furthermore, the PCIe bus I/F module201transmits or receives data between the image processing engine301, the PCI bus I/F module202, and the PCIe end point203.

The first PCIe bus I/F101is controlled by the PCIe bus I/F module201to enable data transmission or data reception to or from the image processing engine301connected thereto through the PCIe bus. The data to be transmitted or received includes image data and commands containing address information.

The specifying unit211detects an address attached to a received command (write or read) when the first PCIe bus I/F101receives the command from the image processing engine301or the like, and specifies an access destination of the command based on the detected address.

The specified access destination in a case of write command is set to the second PCIe bus I/F103connected to the memory153or the like and to the PCI bus I/F102in the PCI bus I/F module202. In a case of read command, the access destination includes the video output module109in addition to the two access destinations.

If the command is the write command of image data, the specifying unit211specifies a write destination (transmission destination) of the image data received from the image processing engine301.

The storage unit214stores therein an address contained in a command in association with-an access destination based on the command. A relationship between the address and the access destination may be previously incorporated into a program that forms the PCIe bus I/F module201.

Accordingly, when the PCIe bus I/F module201receives a command from the image processing engine301, the specifying unit211can specify an access destination of the command from the address in the command by referring to the storage unit214.

The first instructing unit212is arranged inside of the PCIe bus I/F module201(on the first PCIe bus I/F101side through the first signal line210), and issues instructions such as data write and data read to components connected thereto such as the FIFO memory105, the PCI bus I/F module202, the video output module109, the PCIe end point203(the second PCIe bus I/F103), and the first transmitter/receiver213or the like. The first instructing unit212may also issue instructions to the memory153connected thereto through the PCIe end point203to write data and read data.

For example, when the command received from the image processing engine301is the read command of image data to the PCI bus I/F102, the first instructing unit212instructs the PCI bus I/F module202to write the image data received by the PCI bus I/F102onto the FIFO memory105, and then instructs the first transmitter/receiver213to read image data from the FIFO memory105for each predetermined amount of data used by the image processing engine301. It is noted that the predetermined amount of data can be, for example, a PCIe packet size. However, the predetermined amount of data is not limited to the PCIe packet size, and thus the predetermined amount of data may be a data amount required for transfer at a time, that is, the predetermined amount of data is simply a data amount transmittable at a time specified by communication specifications.

The first transmitter/receiver213transmits or receives data to or from the PCI bus I/F module202connected thereto through the FIFO memory105, the address converter106, and the first signal line210.

The first signal line210functions as a communication path that connects between the PCIe bus I/F module201and the PCI bus I/F module202and transmits or receives data therethrough.

The FIFO memory105is provided on the first signal line210, and temporarily stores therein data to be transferred when the data is transferred between the PCIe bus I/F module201and the PCI bus I/F module202connected to each other through the first signal line210.

More specifically, when the specifying unit211specifies the PCI bus I/F102as the write destination of the write command, the first transmitter/receiver213transmits the image data as an object to be written of the write command to the first signal line210. In this case, the image data transferred to the first signal line210is temporarily stored in the FIFO memory105, and then received by the PCI bus I/F module202.

A storage amount that can be stored in the FIFO memory105is determined based on a difference in speed between the PCIe and the PCI and also based on the amount of image data transferred or received between the PCIe bus I/F module201and the PCI bus I/F module202.

As a specific example, the option board304connected to the PCI bus I/F102performs processing only on image data such as fax data for use in transfer which is a comparatively small amount of data. The scanner engine function of the image processing engine301reads the image data, and the image processing engine301sequentially transmits data packet by packet of PCIe from the read image data. The transmitted image data is stored in the FIFO memory105. In other words, the FIFO memory105has to ensure a storage capacity for the PCIe packet size as a minimum limit.

If the PCI bus I/F102can transmit the image data stored in the FIFO memory105to the option board304by the time the image processing engine301transmits the next image data, the capacity for the PCIe packet size is sufficient enough for the storage capacity of the FIFO memory105. And data can thereby be transmitted or received between the PCIe and the PCI whose speeds are different from each other. If the PCI bus I/F102cannot transmit the image data to the option board304by the time the image processing engine301transmits the next image data, the storage capacity of the FIFO memory105has to be increased according to the difference in speed. However, in the case of fax, data transfer speed is not necessarily as high as other transfer speed, and thus, as the minimum limit, only the capacity for the packet size is enough for the capacity of the FIFO memory105.

As a transmission interval of image data transmitted from the image processing engine301, a read interval or the like can be thought of. The read interval is an interval at which the scanner engine function of the image processing engine301mechanically reads image data. In this case, the image processing controller100can transfer image data directly from the PCIe bus I/F module201to the PCI bus I/F module202without allowing for the difference in speed between the PCIe and the PCI.

The PCI bus I/F module202transfers the image data received from the video output module109through the PCIe bus I/F module201, the PCIe end point203, and the selector108, to options such as the option board304connected to the PCI bus. To transfer the image data, a PCI address needs to be generated according to an option which is the transfer destination of data. The first embodiment is, therefore, provided with the address converter106.

The address converter106converts between an address space used by the PCIe bus I/F module201and an address space used by the PCI bus I/F module202. Based on the converting process, for example, an address of a write destination that is transferred from the PCIe bus I/F module201can be converted to an address used by the PCI bus I/F module202as the write destination.

An example of the address converter106includes a direct memory access (DMA) controller. The DMA controller generates a PCI address according to an option of an access destination, and the PCI bus I/F module202controls the access according to the generated PCI address. An arrangement of an address map to respective options can be set by using a register.

Moreover, the address converter106includes a function of detecting an address contained in a command transferred from each option connected to the PCI bus and of specifying an access destination based on the command from the detected address. The function allows the PCI bus I/F module202, explained later, to access the access destination based on the command transferred from the option.

The PCI bus I/F module202includes a second transmitter/receiver222, the PCI bus I/F102, and a second instructing unit221in addition to the address converter106. Further, the PCI bus I/F module202transmits or receives data between peripheral devices such as the option board304connected thereto through the PCI bus, the PCIe bus I/F module201, and the PCIe end point203.

The second transmitter/receiver222transmits or receives data to or from the PCIe bus I/F module201through the FIFO memory105, the address converter106, and the first signal line210.

The PCI bus I/F102is controlled by the PCI bus I/F module202to transmit or receive data to or from the peripheral devices such as the option board304. The data to be transmitted or received includes image data and commands containing addresses. The PCI bus I/F102also performs data transmission or reception at a transmission speed lower than that of the first PCIe bus I/F101.

The second instructing unit221is disposed inside the PCI bus I/F module202or on the PCI bus I/F102side through the first signal line210, and issues an instruction to the peripheral device to read data or write data, the peripheral device being connected thereto through the video output module109, the PCIe end point203, and the PCI bus. The second instructing unit221may also issue an instruction to the memory153connected thereto through the PCIe end point203to perform read or write operations.

The PCIe bus I/F module201and the PCI bus I/F module202are connected to each other through the first signal line210, and this allows direct transfer of data therebetween. A data transfer method therebetween may be any method, and thus, for example, the DMA may be used to perform data transfer.

More specifically, the conventional image processing controller has to once store the image data received from the PCIe bus I/F module in the memory and then transfer the image data from the memory to the PCI bus I/F module. Because of this, bandwidths between the PCIe bus I/F module and the memory and between the memory and the PCI bus I/F module have to be used, and this prevents transfer of other data.

On the other hand, the image processing controller100according to the first embodiment transfers data directly from the PCIe bus I/F module201to the PCI bus I/F module202. Therefore, the bandwidths between the PCIe bus I/F module201or the PCI bus I/F module202and the memory153are not used, and this facilitates the transfer of other data by using these bandwidths. Namely, the processing speed in the image processing controller100is improved.

The arbiter110arbitrates the usage of the bus.

The PCIe end point203includes the second PCIe bus I/F103, and transmits and receives data between the peripheral devices, the PCIe bus I/F module201, and the PCI bus I/F module202. In this case, the peripheral devices include the memory153and the CPU152connected to the second PCIe bus I/F103through the PCIe bus.

The second PCIe bus I/F103is controlled by the PCIe end point203to transmit or receive data with the device such as the memory153or the CPU152connected thereto through the PCIe bus. The data to be transmitted or received includes image data and commands containing addresses.

The HDD I/F module104includes the interface connected to the HDD154, and controls the interface to transmit or receive data to or from the HDD154.

The DMAC204is a controller that transfers data using a DMA transfer method between the PCI bus I/F module202, the video output module109, and the PCIe bus I/F module201.

The DMACs232ato232dtransfer image data on the memory153to the video output module109.

The video output module109outputs the image data transferred from the DMACs232ato232dto the image processing engine301through the FIFO memories231ato231dfor each color of cyan (C) version, magenta (M) version, yellow (Y) version, and black (K) version, respectively. The output image data are transferred to the plotter output engine function mounted on the image processing engine301.

The FIFO memories231ato231dtemporarily store therein the image data output from the video output module109for each of the colors respectively. Thereafter, the image data are transmitted to an output destination selected by the selector108.

The selector108receives a selection of either the PCIe bus I/F module201or the PCI bus I/F module202as the output destination of the image data output from the video output module109, based on register setting. Then, the selector108outputs the image data to either the PCIe bus I/F module201or the PCI bus I/F module202according to the received selection.

As explained above, the image processing controller100is provided with the selector108, and can thereby select either one of the first and the second I/Fs such as the PCIe and the PCI whose speed is different, as an output destination. Consequently, the image processing controller100can appropriately output the image data to the image processing engine regardless of on which side of the first and the second I/Fs the image processing engine is provided.

More specifically, the image processing controller100according to the first embodiment has both functions of an image processing controller for an image processing engine connectable to the first I/F such as PCIe and an image processing controller for an image processing engine connectable to the second I/F such as PCI. In this manner, the image processing controller100according to the first embodiment can play a role as two types of image processing controllers whose speed is different from each other. Thus, there is no need to provide the image processing controllers for the first I/F and the second I/F, which enables to ease the development burden and to reduce the development cost.

The image processing controller100according to the first embodiment includes the FIFO memory105that is connected between the first I/F101and the second I/F102to accommodate the difference in speed therebetween, which enables to directly transmit or receive data therebetween.

The PCIe bus I/F module201of the image processing controller100can select the second I/F102or the memory153as the access destination based on the address in the command transferred from the image processing engine301. Therefore, by using the image processing controller100, there is no need to provide the switch device for use in connection between different interfaces such as the PCIe and the PCI. Accordingly, it is possible to facilitate manufacture of the image forming apparatus using the image processing controller100and to reduce manufacturing costs.

Moreover, the image processing controller100can perform data transfer between the first I/F101and the second I/F102without using the memory153. Thus, it becomes easier to ensure the bandwidths between the first I/F101or the second I/F102and the memory153, which enables to speed up the processing using the bandwidths.

The image forming apparatus300according to the first embodiment performs both communications of scanner data from the image processing engine301and of plotter data from the option controller303through the FIFO memory105and the address converter106. The image forming apparatus300can also use a method of temporarily storing the scanner data sent from the image processing engine301in the memory153through the memory arbiter (arbiter110) depending on the situations of the FIFO memory105and the address converter106and then transferring the scanner data to the option controller303. The option board304performs communication with the memory153through the memory arbiter (arbiter110).

The case where the selector108sets the output destination to the first PCIe bus I/F101in the image processing controller100is explained below.FIG. 4is a conceptual diagram of the image processing controller100and the peripheral devices when the selector108sets an output destination to the first PCIe bus I/F101.

In the concept as shown inFIG. 4, the scanner data sent from the image processing engine301is stored in the memory153through the arbiter110. The plotter data formed in the image processing controller100is output to the first I/F side or to the first PCIe bus I/F101side. The option board304performs communications with the memory153through the arbiter110.

The communication path of data when the configuration is provided as shown inFIG. 4is explained below.FIG. 5is a diagram of transfer paths for transferring image data from the scanner engine function of the image processing engine301to the memory153, from the memory153to the HDD154, and from the memory153to the plotter output engine function of the image processing engine301.

A transfer path (1) shown inFIG. 5is a path for transferring image data from the scanner engine function of the image processing engine301to the memory153. The image processing engine301issues a write command of image data to a predetermined address. When the first PCIe bus I/F101receives the write command, the specifying unit211specifies a write destination based on the address contained in the write command. In the example shown in the communication path (1) shown inFIG. 5, the write destination is specified as the memory153. The first instructing unit212of the PCIe bus I/F module201outputs the write command to the memory153through the PCIe end point203(third I/F). Thereafter, the image data is stored in the memory153according to the write command.

A transfer path (2) shown inFIG. 5is a transfer path for image data transmitted or received between the memory153and the HDD154. The image processing controller100uses the DMAC204provided in the HDD I/F module104to store the image data on the memory153in the HDD154. Moreover, the image processing controller100uses the DMAC204to expand the image data stored in the HDD154, in the memory153.

Functions (not shown) for performing image processing in the image processing controller100can perform processes, such as rotation, compression, decompression, and editing, on the image data on the memory153by using each DMA for each of the functions.

A transfer path (3) shown inFIG. 5is a path for transferring image data from the memory153to the plotter output engine function of the image processing engine301. The image processing engine301issues a read command of image data to a predetermined address. When the first PCIe bus I/F101receives the read command, the specifying unit211specifies a read destination based on the address contained in the read command. In the example shown inFIG. 5, the video output module109is specified as the read destination. The first instructing unit212of the PCIe bus I/F module201outputs the read command to the video output module109. The video output module109receives, in response to the read command, image data for the colors from the memory153through the PCIe end point203, and transfers the image data to the PCIe bus I/F module201through the FIFO memories231ato231drespectively. The PCIe bus I/F module201outputs the received image data for the colors to the plotter output engine function of the image processing engine301.

FIG. 6is a diagram of transfer paths for transfer of image data between the image processing engine301and the option board304and between the option board304and the memory153.

A transfer path (4) shown inFIG. 6is a path for directly transferring image data from the scanner engine function of the image processing engine301to the option board304(fax control unit). The image processing engine301operates as a master based on a master (main)-slave (dependent on the master) relationship.

More specifically, the image processing engine301issues a write command of image data for a predetermined address to the image processing controller100. When the first PCIe bus I/F101of the PCIe bus I/F module201receives the write command, the specifying unit211specifies the option board304(fax control unit) as the write destination based on the address contained in the write command. The first transmitter/receiver213outputs the write command to the PCI bus I/F module202through the first signal line210.

When the PCI bus I/F module202receives the write command, the address converter106converts the address contained in the write command to a specified address. The second instructing unit221outputs the write command to the option board304through the PCI bus I/F102according to the converted address. As a result, the transfer of the image data from the image processing engine301to the option board304and the write operation thereof are performed.

As explained above, the deference in speed between the PCIe and the PCI can be accommodated by passing the image data through the FIFO memory105during the transfer process. If the image processing engine301operates as the master, the option board (fax control unit)304operates as the slave.

A transfer path (5) shown inFIG. 6is a path for transferring image data input in the option board (fax control unit)304to the plotter output engine function of the image processing engine301. The image processing engine301also operates as the master during the transfer process using the transfer path (5).

More specifically, the image processing engine301issues a read command of image data for a predetermined address to the image processing controller100. When the first PCIe bus I/F101of the PCIe bus I/F module201receives the read command, the specifying unit211specifies the option board (fax control unit)304as a read destination based on the address contained in the read command. The first transmitter/receiver213outputs the read command to the PCI bus I/F module202through the first signal line210.

When the PCI bus I/F module202receives the read command, the address converter106converts the address contained in the read command to a specified address. The second instructing unit221outputs the read command to the option board304through the PCI bus I/F102according to the converted address. As a result, the image data is transferred from the option board304to the image processing engine301. In the process shown by the transfer path (5), the image processing engine301also operates as the master, and the option board (fax control unit)304operates as the slave.

In the process shown by the transfer path (5), the data transfer from the option board (fax control unit)304to the image processing engine301can be performed without passing through the ChipSet151and the memory153. This process can be implemented by providing the FIFO memory105between the PCIe bus I/F module201and the PCI bus I/F module202.

When copying is operated, the image processing engine301as the master outputs the read command of image data to the memory153on the ChipSet151side, to perform the process.

In the transfer path (5), the image processing engine301as the master requests an operation from the fax control unit304. The image processing engine301can process color image data (multivalued image data) upon copying, while monochrome image data (binary image data) is transferred from the fax control unit304. Because of this, the transmission speed of the image processing engine301is provided sufficiently high enough to correspond to the transfer speed of the fax control unit304.

The PCI bus I/F module202temporarily stores the monochrome image data transferred from the fax control unit304in the FIFO memory105based on the read command. Thereafter, the image processing engine301outputs the read command to the PCIe bus I/F module201, and the PCIe bus I/F module201transfers the monochrome image data stored in the FIFO memory105to the image processing engine301based on the read command.

With these processes, the image data more than a data amount required for printing by the plotter output engine function of the image processing engine301is temporarily stored in the FIFO memory105, and the PCIe bus I/F module201can acquire the image data by the data amount from the FIFO memory105. Consequently, the PCIe bus I/F module201can reliably transfer the image data to the image processing engine301without being affected by delay of the process in the PCI bus I/F module202. It is noted that the FIFO memory105may have a storage capacity for one PCIe packet or more as the data amount required for printing, or may store therein image data for one line in a main scanning direction upon printing or the like.

Moreover, if the read destination is the FIFO memory105, the PCIe bus I/F module201can reduce a read time because the transfer path to the FIFO memory105is shorter than the case where the read destination is the fax control unit304.

A transfer path (6) shown inFIG. 6is a path for transferring image data input in the option board (fax control unit)304to the memory153. The fax control unit304operates as the master during the transfer process using the transfer path (6).

The fax control unit304outputs a write command of image data for a predetermined memory address. The address converter106of the PCI bus I/F module202specifies an access destination from the memory address contained in the write command. The specified access destination is assumed as the memory153. In this case, the second instructing unit221outputs the write command to the memory153as the access destination through the second transmitter/receiver222. Thereafter, the image data is written onto the memory153based on the write command.

Moreover, if the fax control unit304as the master outputs a read command of image data for a predetermined memory address, the address converter106specifies an access destination from the memory address contained in the read command. If the specified access destination is the memory153, the second instructing unit221outputs the read command to the memory153as the access destination through the second transmitter/receiver222. Thus, the image data is read from the memory153based on the read command.

As explained above, in the transmission path (6) shown inFIG. 6, data can be bidirectionally transferred between the fax control unit304and the memory153.

In the image forming apparatus300according to the first embodiment, the example in which the image processing engine301is connected to the image processing controller100through the PCIe bus is explained. However, the image processing controller100can connect the image processing engine to the PCI bus side by changing an output destination of the selector108. In an image processing device according to a second embodiment, an example in which an image processing engine is connected to the PCI bus side of the image processing controller100is explained below. In the following explanation, the same reference numerals are assigned to those corresponding to the components according to the first embodiment, and explanation thereof is omitted.

FIG. 7is a block diagram of an image forming apparatus700according to the second embodiment. In the image forming apparatus700, an image processing engine (or ENGINE)701and an option controller702are arranged on the PCI bus side of the image processing controller100.

FIG. 8is a diagram for explaining a functional concept of the image processing controller100according to the second embodiment. As shown inFIG. 8, the selector108sets an output destination to the PCI bus I/F102, and the first PCIe bus I/F101is not therefore used. Thus, it can be seen that the image processing controller100functions as one to perform image processing at a low speed.

In the concept shown inFIG. 8, scanner data sent from the image processing engine701is stored in the memory153through the arbiter110. Plotter data formed in the image processing controller100is output to the PCI side by the selector108. Moreover, the option board304also performs communication with the memory153through the arbiter110in the same manner as the scanner data.

Furthermore, in the concept shown inFIG. 8, communications of the scanner data from the image processing engine701and of the plotter data from the option controller702with the image processing controller100are performed through the PCI bus. The option controller702accesses the HDD154through the arbiter110and the memory153. Further, the option board304performs communication with the memory153through the arbiter110.

FIG. 9is a diagram of transfer paths for image data transferred by using the image processing controller100when the image processing engine701is connected to the PCI side.

A transfer path (7) shown inFIG. 9is a path for transferring image data input from the scanner engine function of the image processing engine701to the memory153. In this case, the image processing engine701operates as the master, and outputs a write command of image data to a predetermined address. The address converter106of the PCI bus I/F module202specifies an access destination from the memory address contained in the write command. The specified access destination is set to the memory153. In this case, the second instructing unit221outputs the write command to the memory153as the access destination through the second transmitter/receiver222. Thus, the input image data is written onto the memory153based on the write command.

A transfer path (8) shown inFIG. 9is a transfer path for image data transmitted or received between the memory153and the HDD154, and the process is performed in the same manner as that of the transfer path (2) shown inFIG. 5, and thus explanation thereof is omitted.

A transfer path (9) shown inFIG. 9is a path for transferring image data stored in the memory153to the plotter output engine function (or Plotter) of the image processing engine701. In this case, the image processing engine701operates as the master, and outputs a read command of image data to a predetermined address. The address converter106of the PCI bus I/F module202specifies an access destination from the memory address contained in the read command. The specified access destination is set to the video output module109. The second instructing unit221outputs the read command to the video output module109. The video output module109receives the image data for the colors from the memory153through the PCIe end point203in response to the read command. The video output module109outputs the received image data to the selector108. In the second embodiment, the PCI bus I/F module202is selected as an output destination of the selector108, and thus, the image data is transferred to the PCI bus I/F module202. The PCI bus I/F module202outputs the received image data for the colors to the plotter output engine function of the image processing engine701.

By using the image processing controller100according to the second embodiment, the image processing device that includes an image processing engine with the PCIe I/F and an option controller and an option board with the conventional PCI I/F can be implemented without using a switch or a PCIe-PCI bridge, which leads to cost reduction.

The image processing controller100includes the PCI I/F in addition to the PCIe I/F, and thus a conventional PCI board can be made effective use of, which leads to cost reduction.

In the image processing controller100according to the second embodiment that includes the PCI bus I/F102and the first PCIe bus I/F101, the selector108can select an output destination of image data sent from the video output module109. Therefore, the selection of an output destination by the selector108allows the image processing controller100to play a role of two types of image processing controllers.

Moreover, the image processing controller100can be used for an image processing device using the image processing engine with the PCIe I/F and for an image processing device using the image processing engine with the PCI I/F. More specifically, if the configuration is based on the conventional technology, the image processing controller needs to be developed for each of the two types of high-speed and low-speed engine I/Fs even if the functions are common, which causes unnecessary cost such as the cost for development. On the other hand, by using the image processing controller100according to the second embodiment, there is no need to manufacture the image processing controllers for the respective interfaces, which leads to cost reduction.

The embodiments explained above are exemplary embodiments of the present invention, and thus various changes may be made without departing from the scope of the invention. For example, a program to implement the functions of the image processing controller may be loaded into a device, and the functions of the device may be implemented by causing the device to execute the program.

Furthermore, the program may be provided by using a flexible disk (FD) or a magneto-optical disc such as a compact-disk read only memory (CD-ROM) and a digital versatile disk (DVD), which are computer-readable recording media. Alternatively, the program may be transmitted to other computer systems using transmission wave through the Internet and a telephone line which are transmission media. Moreover, an image processing program executed by the image processing controller100according to the embodiments may be stored on a computer connected to a network such as the Internet and provided by being downloaded through the network.

The image processing program executed by the image processing controller100according to the embodiments is formed of modules including the configurations for performing the processes. Therefore, as actual hardware, the CPU (processor) reads the image processing program from the ROM and executes it, to thereby load the units on a main storage unit and generate the configurations on the main storage unit.

As describe above, according to an aspect of the present invention, the image processing controller includes the first I/F and the second I/F connected to each other through a communication path and also includes the FIFO memory that accommodates the difference in speed between the interfaces. Thus, there is no need to provide a switch or a bridge to change specifications of buses, which allows reduction in manufacturing costs.

Furthermore, an output destination of image data can be switched by the selector, and this configuration enables the image processing controller to play a role of the two types of image processing controllers.