Logic circuit and semiconductor device

A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

TECHNICAL FIELD

One aspect of the present invention relates to a logic circuit including a field-effect transistor formed using an oxide semiconductor. Further, one aspect of the present invention relates to a semiconductor device including the logic circuit.

Note that a semiconductor device in this specification indicates all the devices that can operate by using semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic appliances are all included in the category of the semiconductor devices.

BACKGROUND ART

Much attention has been paid to a technology of forming a thin film transistor (TFT), by using a thin semiconductor film that is formed over a substrate having an insulating surface. A thin film transistor is used for a display device typified by a liquid crystal television. A silicon-based semiconductor material is known as a material for a thin semiconductor film applicable to a thin film transistor. Other than a silicon-based semiconductor material, an oxide semiconductor has attracted attention.

As a material for the oxide semiconductor, zinc oxide and a material containing zinc oxide as its component are known. Further, a thin film transistor formed using an amorphous oxide (oxide semiconductor) having an electron carrier density of less than 1018/cm3is disclosed (Patent Documents 1 to 3).

[Patent Document 1] Japanese Published Patent Application No. 2006-165527[Patent Document 2] Japanese Published Patent Application No. 2006-165528[Patent Document 3] Japanese Published Patent Application No. 2006-165529

DISCLOSURE OF INVENTION

However, a difference from the stoichiometric composition in the oxide semiconductor arises in a thin film formation process. For example, electrical conductivity of the oxide semiconductor changes due to the excess or deficiency of oxygen. Further, hydrogen that enters the thin oxide semiconductor film during the formation of the thin film forms an oxygen (O)-hydrogen (H) bond and serves as an electron donor, which is a factor of changing electrical conductivity. Furthermore, since the O—H bond is a polar molecule, it serves as a factor of varying characteristics of an active device such as a thin film transistor manufactured using an oxide semiconductor.

Even when having an electron carrier density of less than 1018/cm3, an oxide semiconductor is a substantially n-type oxide semiconductor. Therefore, an on-off ratio of about 103of the thin film transistor disclosed in the Patent Document has been obtained. Such a low on-off ratio of the thin film transistor is due to large off-state current.

The on-off ratio is a measure of characteristics of a switch. Operation of a circuit including a thin film transistor with a low on-off ratio becomes unstable. Further, current flows excessively due to large off-state current; thus, power consumption is increased.

In view of the foregoing problems, an object of an embodiment of the present invention is to suppress a malfunction of a logic circuit including a thin film transistor formed using an oxide semiconductor.

Further, an object of an embodiment of the present invention is to reduce power consumption of a logic circuit including a thin film transistor formed using an oxide semiconductor.

According to an embodiment of the present invention, a logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor which is made intrinsic or substantially intrinsic by removing impurities (e.g., hydrogen and water) having possibilities of being electron donors (or donors), and has an energy gap larger than that of a silicon semiconductor.

Specifically, a logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor in which the concentration of hydrogen is set to 5×1019/cm3or less, preferably 5×1018/cm3or less, still preferably 5×1017/cm3or less to remove hydrogen or an O—H bond included in the oxide semiconductor, and the carrier density is set to 5×1014/cm3or less, preferably 5×1012/cm3or less.

The energy gap of the oxide semiconductor is set to 2 eV or more, preferably 2.5 eV or more, still preferably 3 eV or more to reduce as much impurities (e.g., hydrogen), which form donors, as possible. Further, the carrier density of the oxide semiconductor is set to 1×1014/cm3or less, preferably 1×1012/cm3or less.

The thus purified oxide semiconductor is used for a channel formation region of a thin film transistor. Accordingly, even in the case where the channel width is 10 mm, the drain current of 1×10−13[A] or less is obtained at drain voltages of 1 V and 10 V and gate voltages in the range of −5 V to −20 V.

That is, an embodiment of the present invention is a logic circuit including a thin film transistor and a capacitor having terminals one of which is electrically connected to a node which is brought into a floating state by turning off the thin film transistor. A channel formation region of the thin film transistor is formed using an oxide semiconductor with a hydrogen concentration of 5×1019(atoms/cm3).

Note that in this specification, the concentration is measured by secondary ion mass spectrometry (hereinafter referred to as SIMS). However, there is no limitation particularly when descriptions of other measurement methods are made.

Further, a semiconductor device including the logic circuit is also an embodiment of the present invention.

In accordance with an embodiment of the present invention, a logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor; and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor is an oxide semiconductor with reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019(atoms/cm3) or less, and when there is no electric field, the oxide semiconductor serves as an insulator or a semiconductor which is close to an insulator (the semiconductor which is close to an insulator is substantially an insulator). Therefore, off-state current of the thin film transistor can be reduced. Thus, the leakage of electric charge stored in the capacitor, through the thin film transistor, can be suppressed. Thus, a malfunction of the logic circuit can be prevented. Further, a period where the one terminal of the capacitor is in a floating state can be made long. In other words, the number of times of data rewriting to the capacitor (also referred to as refreshing) can be reduced.

Furthermore, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor. Thus, power consumption of the logic circuit can be reduced.

BEST MODE FOR CARRYING OUT THE INVENTION

Note that since a source terminal and a drain terminal of a transistor change depending on the structure, the operating condition, and the like of the transistor, it is difficult to define which is a source terminal or a drain terminal. Therefore, in this specification, one of a source terminal and a drain terminal is referred to as a first terminal and the other thereof is referred to as a second terminal for distinction, hereinafter.

Note that the size, the thickness of a layer, or a region of each structure illustrated in drawings or the like in embodiments is exaggerated for simplicity in some cases. Therefore, embodiments of the present invention are not limited to such scales. Further, in this specification, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the components numerically.

In this embodiment, examples of logic circuits are described. Specifically, examples of inverters each including a thin film transistor having a channel formation region which is formed using an oxide semiconductor are described with reference toFIGS. 1A to 1DandFIGS. 2A to 2D.

FIG. 1Ais a circuit diagram illustrating an example of an inverter of this embodiment. The inverter illustrated inFIG. 1Aincludes thin film transistors11to14and a capacitor15. Here, the thin film transistor11is a depletion type transistor and the thin film transistors12to14are enhancement type transistors. Note that in this specification, an n-channel transistor whose threshold voltage is positive is referred to as an enhancement type transistor, and an n-channel transistor whose threshold voltage is negative is referred to as a depletion type transistor.

A first terminal of the thin film transistor11is electrically connected to a wiring for supplying a high power supply potential (VDD) (hereinafter, such a wiring is also referred to as a high power supply potential line).

A gate terminal of the thin film transistor12is electrically connected to a wiring for supplying an input signal (IN) (hereinafter, such a wiring is also referred to as an input signal line), and a first terminal of the thin film transistor12is electrically connected to a gate terminal and a second terminal of the thin film transistor11.

A gate terminal of the thin film transistor13is electrically connected to a wiring for supplying a pulse signal (PS) (hereinafter, such a wiring is also referred to as a pulse signal line), a first terminal of the thin film transistor13is electrically connected to a second terminal of the thin film transistor12, and a second terminal of the thin film transistor13is electrically connected to a wiring for supplying a low power supply potential (VSS) (hereinafter, such a wiring is also referred to as a low power supply potential line).

A gate terminal of the thin film transistor14is electrically connected to a pulse signal line, a first terminal of the thin film transistor14is electrically connected to the gate terminal and the second terminal of the thin film transistor11and the first terminal of the thin film transistor12, and a second terminal of the thin film transistor14is electrically connected to a wiring for outputting an output signal (hereinafter, such a wiring is also referred to as an output signal line).

One terminal of the capacitor15is electrically connected to the second terminal of the thin film transistor14and the output signal line, and the other terminal of the capacitor15is electrically connected to a low power supply potential line.

Note that the thin film transistor11is a depletion type transistor in which the first terminal is electrically connected to the high power supply potential line and the gate terminal is electrically connected to the second terminal. That is, the thin film transistor11is maintained in an on state in any period. In other words, the thin film transistor11is used as a resistor.

Further, in this specification, the high power supply potential (VDD) and the low power supply potential (VSS) may be any potentials as long as the high power supply potential (VDD) is higher than the low power supply potential (VSS). For example, a ground potential, 0 V, or the like can be used as the low power supply potential (VSS), and a given positive potential or the like can be used as the high power supply potential (VDD).

Next, an operation of the circuit illustrated inFIG. 1Ais described with reference to a timing chart inFIG. 1B. Note thatFIG. 1Bis illustrated while a node where the gate terminal and the second terminal of the thin film transistor11, the first terminal of the thin film transistor12, and the first terminal of the thin film transistor14are electrically connected to each other is regarded as a node A.

In a period T1, the potentials of the input signal (IN) and the pulse signal (PS) are increased to a high level. Therefore, the thin film transistors12to14are turned on. Thus, the node A and the one terminal of the capacitor are electrically connected to the low power supply potential line; i.e., the potential of the node A and an output signal (OUT) of the inverter are decreased to a low level. Electric charge is not stored in the capacitor15.

In a period T2, the potential of the pulse signal (PS) is decreased to a low level. Therefore, the thin film transistors13and14are turned off. When the thin film transistor13is turned off, the potential of the node A is increased to a high level. When the thin film transistor14is turned off, the one terminal of the capacitor15is brought into a floating state. Therefore, the output signal (OUT) of the inverter is maintained at a low level.

In a period T3, the potential of the input signal (IN) is decreased to a low level, and the potential of the pulse signal (PS) is increased to a high level. Therefore, the thin film transistor12is turned off, and the thin film transistors13and14are turned on. Thus, the node A and the one terminal of the capacitor15are electrically connected to the high power supply potential line through the thin film transistor11; i.e., the potential of the node A and the output signal (OUT) of the inverter are increased to a high level. Positive electric charge is stored in the one terminal of the capacitor15.

In each of the plurality of thin film transistors included in the inverter of this embodiment, a channel formation region is formed using an oxide semiconductor. The oxide semiconductor is an oxide semiconductor with reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019(atoms/cm3) or less, and when there is no electric field, the oxide semiconductor serves as an insulator or a semiconductor which is close to an insulator (the semiconductor which is close to an insulator is substantially an insulator). Therefore, off-state current of the thin film transistor having the channel formation region formed using the oxide semiconductor can be reduced. Thus, the leakage of electric charge through the thin film transistor can be suppressed.

For example, with a channel formation region of the thin film transistor14, which is formed using the oxide semiconductor, the level of change in potential in a period where the one terminal of the capacitor15is in a floating state (i.e., the period T2), such as increase in potential in the period T2, can be suppressed. Thus, a malfunction of the inverter can be prevented. Further, the period where the one terminal of the capacitor15is in a floating state can be made long. In other words, the number of times of data rewriting to the capacitor15(also referred to as refreshing) can be reduced.

Further, a channel formation region of the thin film transistor13which is formed using the oxide semiconductor can reduce a through current which flows from the high power supply potential line to the low power supply potential line in a period where the potential of the input signal (IN) is at a high level and the potential of the pulse signal (PS) is at a low level (i.e., the period T2). Thus, power consumption of the inverter can be reduced.

Note that the inverter of this embodiment is not limited to the inverter illustrated inFIG. 1A. An example of the inverter which is different from the inverter illustrated inFIG. 1Ais described below with reference toFIG. 1C.

The inverter illustrated inFIG. 1Cincludes thin film transistors21to24and a capacitor25. Here, the thin film transistor21is a depletion type transistor and the thin film transistors22to24are enhancement type transistors.

A first terminal of the thin film transistor21is electrically connected to a high power supply potential line.

A gate terminal of the thin film transistor22is electrically connected to a pulse signal line, and a first terminal of the thin film transistor22is electrically connected to a gate terminal and a second terminal of the thin film transistor21.

A gate terminal of the thin film transistor23is electrically connected to an input signal line, a first terminal of the thin film transistor23is electrically connected to a second terminal of the thin film transistor22, and a second terminal of the thin film transistor23is electrically connected to a low power supply potential line.

A gate terminal of the thin film transistor24is electrically connected to a pulse signal line, a first terminal of the thin film transistor24is electrically connected to the second terminal of the thin film transistor22and the first terminal of the thin film transistor23, and a second terminal of the thin film transistor24is electrically connected to an output signal line.

One terminal of the capacitor25is electrically connected to the second terminal of the thin film transistor24and the output signal line, and the other terminal of the capacitor25is electrically connected to a low power supply potential line.

To put it simply, the inverter illustrated inFIG. 1Cis a circuit in which the thin film transistor13inFIG. 1Ais replaced with the thin film transistor22.

Next, an operation of the circuit illustrated inFIG. 1Cis described with reference to a timing chart inFIG. 1D. Note thatFIG. 1Dis illustrated while a node where the second terminal of the thin film transistor22, the first terminal of the thin film transistor23, and the first terminal of the thin film transistor24are electrically connected to each other is regarded as a node B.

In a period T4, the potentials of the input signal (IN) and the pulse signal (PS) are increased to a high level. Therefore, the thin film transistors22to24are turned on. Thus, the node B and the one terminal of the capacitor25are electrically connected to the low power supply potential line; i.e., the potential of the node B and the output signal (OUT) of the inverter are decreased to a low level. Electric charge is not stored in the capacitor25.

In a period T5, the potential of the pulse signal (PS) is decreased to a low level. Therefore, the thin film transistors22and24are turned off. When the thin film transistor24is turned off, the one terminal of the capacitor25is brought into a floating state. Thus, the output signal (OUT) of the inverter is maintained at a low level. Note that the potential of the node B is at a low level.

In a period T6, the potential of the input signal (IN) is decreased to a low level, and the potential of the pulse signal (PS) is increased to a high level. Therefore, the thin film transistor23is turned off, and the thin film transistors22and24are turned on. Thus, the node B and the one terminal of the capacitor25are electrically connected to the high power supply potential line through the thin film transistor21; i.e., the potential of the node B and the output signal (OUT) of the inverter are increased to a high level. Positive electric charge is accumulated in the one terminal of the capacitor25.

In each of the plurality of thin film transistors included in the inverter illustrated inFIG. 1C, a channel formation region is formed using an oxide semiconductor. The oxide semiconductor is an oxide semiconductor with reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019(atoms/cm3) or less, and when there is no electric field, the oxide semiconductor serves as an insulator or a semiconductor which is close to an insulator (the semiconductor which is close to an insulator is substantially an insulator). Therefore, off-state current of the thin film transistor having the channel formation region formed using the oxide semiconductor can be reduced. Thus, the leakage of electric charge through the thin film transistor can be suppressed.

For example, with a channel formation region of the thin film transistor24, which is formed using the oxide semiconductor, the level of change in potential in a period where the one terminal of the capacitor25is in a floating state can be suppressed. Thus, a malfunction of the inverter can be prevented. Further, the period where the node B is in a floating state can be made long. In other words, the number of times of data rewriting to the capacitor25(also referred to as refreshing) can be reduced.

Further, a channel formation region of the thin film transistor22which is formed using the oxide semiconductor can reduce a through current which flows from the high power supply potential line to the low power supply potential line in a period where the potential of the input signal (IN) is at a high level and the potential of the pulse signal (PS) is at a low level (i.e., the period T5). Thus, power consumption of the inverter can be reduced.

Although a depletion type transistor is used for a thin film transistor which is electrically connected to the high power supply potential line in the inverter, an enhancement type transistor can be used for the thin film transistor.FIG. 2Ais a circuit diagram in which the thin film transistor11included in the inverter illustrated inFIG. 1Ais replaced with a thin film transistor31which is an enhancement type transistor. Similarly,FIG. 2Bis a circuit diagram in which the thin film transistor21included in the inverter illustrated inFIG. 1Cis replaced with a thin film transistor41which is an enhancement type transistor. Note that a gate terminal and a first terminal of each of the thin film transistors31and41are electrically connected to a high power supply potential line.

Although a capacitor is included in each of the inverters, each of the inverters can be operated without the capacitor.FIG. 2Cillustrates a circuit diagram in which the capacitor15is removed from the inverter illustrated inFIG. 2A. Similarly,FIG. 2Dillustrates a circuit diagram in which the capacitor25is removed from the inverter illustrated inFIG. 2B.

In this embodiment, examples of logic circuits are described. Specifically, examples of shift registers each including the inverter in Embodiment 1 are described with reference toFIGS. 3A and 3BandFIGS. 4A and 4B.

A shift register of this embodiment includes a plurality of pulse output circuits; a wiring for supplying a first clock signal (CK1), which is electrically connected to odd-numbered pulse output circuits of the plurality of pulse output circuits (hereinafter, such a wiring is also referred to as a first clock signal line); and a wiring for supplying a second clock signal (CK2), which is electrically connected to even-numbered pulse output circuits of the plurality of pulse output circuits (hereinafter, such a wiring is also referred to as a second clock signal line). Further, an input terminal of each pulse output circuit is electrically connected to a wiring for supplying a start pulse signal (SP) (hereinafter, such a wiring is also referred to as a start pulse line) or an output terminal of a pulse output circuit of a prior stage.

A specific example of a circuit configuration of a pulse output circuit is described with reference toFIG. 3A. Note that pulse output circuits110,120, and130are illustrated inFIG. 3A.

The pulse output circuit110includes thin film transistors101to104and a capacitor105. Here, the thin film transistor101is a depletion type transistor, and the thin film transistors102to104are enhancement type transistors.

A first terminal of the thin film transistor101is electrically connected to a high power supply potential line.

A gate terminal of the thin film transistor102is electrically connected to a start pulse line, and a first terminal of the thin film transistor102is electrically connected to a gate terminal and a second terminal of the thin film transistor101.

A gate terminal of the thin film transistor103is electrically connected to a first clock signal line, a first terminal of the thin film transistor103is electrically connected to a second terminal of the thin film transistor102, and a second terminal of the thin film transistor103is electrically connected to a low power supply potential line.

A gate terminal of the thin film transistor104is electrically connected to a first clock signal line, and a first terminal of the thin film transistor104is electrically connected to the gate terminal and the second terminal of the thin film transistor101and the first terminal of the thin film transistor102.

One terminal of the capacitor105is electrically connected to a second terminal of the thin film transistor104, and the other terminal of the capacitor105is electrically connected to a low power supply potential line.

That is, the pulse output circuit110illustrated inFIG. 3Ais formed using the inverter illustrated inFIG. 1A.

Note that “input terminal of the pulse output circuit110” refers to a terminal to which a start pulse signal (SP) or an output signal of a pulse output circuit of a prior stage is input, and “output terminal of the pulse output circuit110” refers to a terminal from which a signal is output to a pulse input terminal of a subsequent stage. That is, here, the gate terminal of the thin film transistor102is electrically connected to the input terminal of the pulse output circuit, and the second terminal of the thin film transistor104and the one terminal of the capacitor105are electrically connected to the output terminal In the case where components corresponding to the output terminal and the input terminal are not given, the gate terminal of the thin film transistor102can be referred to as the input terminal of the pulse output circuit, and the second terminal of the thin film transistor104and the one terminal of the capacitor105can be referred to as the output terminals of the pulse output circuit.

A specific circuit configuration of the pulse output circuit120is similar to that of the pulse output circuit110; thus, the description is to be referred to here. Note that the pulse output circuit120is different from the pulse output circuit110in that an input terminal of the pulse output circuit120is electrically connected to the output terminal of the pulse output circuit110and that the second clock signal (CK2) is input to a terminal corresponding to the terminal to which the first clock signal (CK1) is input in the pulse output circuit110.

The circuit configurations of pulse output circuits which are subsequent to the pulse output circuit120are the same as those of the pulse output circuits110and120. Therefore, the description is to be referred to here. Further, as described above, the odd-numbered pulse output circuits are electrically connected to the first clock signal line and the even-numbered pulse output circuits are electrically connected to the second clock signal line.

Next, an operation of the circuit illustrated inFIG. 3Ais described with reference to a timing chart ofFIG. 3B. Note that specific nodes of the circuit inFIG. 3Aare denoted by C to G for convenience, and the change in potential of each node is referred to in order to describe the timing chart ofFIG. 3B.

In a period t1, the potential of the start pulse signal (SP) is increased to a high level. Therefore, the thin film transistor102is turned on. The thin film transistor101is a depletion type transistor in which the gate terminal is electrically connected to the second terminal. That is, the thin film transistor101is maintained in an on state in any period. In other words, the thin film transistor101is used as a resistor.

In a period t2, the potential of the start pulse signal (SP) is maintained at a high level. Therefore, the thin film transistor102is maintained in an on state.

In a period t3, the potential of the first clock signal (CK1) is increased to a high level. Therefore, the thin film transistors103and104are turned on. Further, the potential of the start pulse signal (SP) is maintained at a high level. Therefore, the thin film transistor102is maintained in an on state. Thus, the nodes C and D are electrically connected to the low power supply potential line; i.e., the potentials of the nodes C and D are decreased to a low level.

In a period t4, the potential of the first clock signal (CK1) is decreased to a low level. Therefore, the thin film transistors103and104are turned off. Thus, the node C is electrically connected to the high power supply potential line through the thin film transistor101, and the node D is brought into a floating state. That is, the potential of the node C is increased to a high level, and the potential of the node D is maintained at a low level.

In a period t5, the potential of the start pulse signal (SP) is decreased to a low level. Therefore, the thin film transistor102is turned off. Further, the potential of the second clock signal (CK2) is increased to a high level. Therefore, the thin film transistors113and114are turned on. Thus, the node F is electrically connected to the high power supply potential line through the thin film transistor111; i.e., the potential of the node F is increased to a high level. Therefore, the thin film transistor122is turned on.

In a period t6, the potential of the second clock signal (CK2) is decreased to a low level. Therefore, the thin film transistors113and114are turned off. Thus, the node F is brought into a floating state; i.e., the potentials of the nodes E and F are maintained at a high level.

In a period t7, the potential of the first clock signal (CK1) is increased to a high level. Therefore, the thin film transistors103,104,123, and124are turned on. When the thin film transistor104is turned on, the node D is electrically connected to the high power supply potential line through the thin film transistor101; i.e., the potential of the node D is increased to a high level. Therefore, the thin film transistor112is turned on. The potential of the node F is maintained at a high level; therefore, the thin film transistor122is maintained in an on state. Thus, the node G is electrically connected to the low power supply potential line; i.e., the potential of the node G is decreased to a low level.

In a period t8, the potential of the first clock signal (CK1) is decreased to a low level. Therefore, the thin film transistors103,104,123, and124are turned off. When the thin film transistor104is turned off, the node C is electrically connected to the high power supply potential line through the thin film transistor101, and the node D is brought into the floating state. Thus, the nodes C and D are maintained at a high level. When the thin film transistor123is turned off, the node G is electrically connected to the high power supply potential line through the thin film transistor121; i.e., the potential of the node G is increased to a high level.

In a period t9, the potential of the second clock signal (CK2) is increased to a high level. Therefore, the thin film transistors113and114are turned on. The potential of the node D is maintained at a high level, so that the thin film transistor112is maintained in an on state. Thus, the nodes E and F are electrically connected to the low power supply potential line: i.e., the potentials of the nodes E and F are decreased to a low level. Therefore, the thin film transistor122is turned off. Further, the potential of the start pulse (SP) is increased to a high level again. Note that the operation accompanying the increase in potential of the start pulse (SP) in periods subsequent to the period is the same as the operation in periods subsequent to the period t1. Therefore, the description is to be referred to here.

In a period t10, the potential of the second clock signal (CK2) is decreased to a low level. Therefore, the thin film transistors113and114are turned off. Thus, the node F is brought into a floating state; i.e., the potential of the node F is maintained at a low level. Further, the node E is electrically connected to the high power supply potential line through the thin film transistor111; i.e., the potential of the node E is increased to a high level.

Regarding the operation in periods subsequent to the period t10, the aforementioned operation is repeated. Therefore, the description is to be referred to here.

Note that the capacitors (e.g., capacitor105,115, and125) included in the pulse output circuits are provided in order to maintain an output signal of each pulse output circuit.

In each of the plurality of thin film transistors included in the shift register of this embodiment, a channel formation region is formed using an oxide semiconductor. The oxide semiconductor is an oxide semiconductor with reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019(atoms/cm3) or less, and when there is no electric field, the oxide semiconductor serves as an insulator or a semiconductor which is close to an insulator (the semiconductor which is close to an insulator is substantially an insulator). Therefore, off-state current of the thin film transistor having the channel formation region formed using the oxide semiconductor can be reduced. Thus, the leakage of electric charge through the thin film transistor can be suppressed.

For example, with a channel formation region of the thin film transistor104, which is formed using the oxide semiconductor, the level of change in potential of the node D in a period where the node D is in a floating state (e.g., the periods t4to t6), such as increase in potential in the periods t4to t6, can be suppressed. Thus, a malfunction of the shift register can be prevented. Further, the period where the node D is in a floating state can be made long. In other words, the number of times of data rewriting to the capacitor105(also referred to as refreshing) can be reduced.

Further, a channel formation region of the thin film transistor103which is formed using the oxide semiconductor can reduce a through current which flows from the high power supply potential line to the low power supply potential line in a period where the potential of the start pulse (SP) is at a high level and the potential of the first clock signal (CK1) is at a low level (e.g., the periods t1, t2, and t4). Thus, power consumption of the shift register can be reduced.

Note that the shift register of this embodiment is not limited to the shift register illustrated inFIG. 3A. An example of the shift register which is different from the shift register illustrated inFIGS. 3A and 3Bis described with reference toFIGS. 4A and 4B.

The shift register illustrated inFIG. 4Aincludes pulse output circuits210,220, and230. The pulse output circuit210includes thin film transistors201to204and a capacitor205. Here, the thin film transistor201is a depletion type transistor, and the thin film transistors202to204are enhancement type transistors.

A first terminal of the thin film transistor201is electrically connected to a high power supply potential line.

A gate terminal of the thin film transistor202is electrically connected to a first clock signal line, and a first terminal of the thin film transistor202is electrically connected to a gate terminal and a second terminal of the thin film transistor201.

A gate terminal of the thin film transistor203is electrically connected to a start pulse line, a first terminal of the thin film transistor203is electrically connected to a second terminal of the thin film transistor202, and a second terminal of the thin film transistor203is electrically connected to a low power supply potential line.

A gate terminal of the thin film transistor204is electrically connected to a first clock signal line, and a first terminal of the thin film transistor204is electrically connected to the second terminal of the thin film transistor202and the first terminal of the thin film transistor203.

One terminal of the capacitor205is electrically connected to a second terminal of the thin film transistor204, and the other terminal of the capacitor205is electrically connected to a low power supply potential line.

To put it simply, the pulse output circuit210illustrated inFIG. 4Ais a circuit in which the thin film transistor103included in the pulse output circuit110inFIG. 3Ais replaced with the thin film transistor202.

FIG. 4Bis a timing chart illustrating an operation of the circuit inFIG. 4A. Note that specific nodes of the circuit inFIG. 4Aare denoted by H to L for convenience, and the change in potential of each node is referred to in order to describe the timing chart with reference toFIG. 4B.

In a period t11, the potential of the start pulse signal (SP) is increased to a high level. Therefore, the thin film transistor203is turned on. Thus, the node H is electrically connected to the low power supply potential line; i.e., the potential of the node H is decreased to a low level.

In a period t12, the potential of the start pulse signal (SP) is maintained at a high level. That is, the potential of the node H is maintained at a low level.

In a period t13, the potential of the first clock signal (CK1) is increased to a high level. Therefore, the thin film transistors202and204are turned on. Further, the potential of the start pulse signal (SP) is maintained at a high level, so that the thin film transistor203is maintained in an on state. Thus, the node I is electrically connected to the low power supply potential line; i.e., the potential of the node I is decreased to a low level.

In a period t14, the potential of the first clock signal (CK1) is decreased to a low level. Therefore, the thin film transistors202and204are turned off. Thus, the node I is brought into a floating state, so that the potential of the node I is maintained at a low level.

In a period t15, the potential of the start pulse signal (SP) is decreased to a low level. Therefore, the thin film transistor203is turned off. Thus, the node H is brought into a floating state, so that the potential of the node H is maintained at a low level. Further, the potential of the second clock signal (CK2) is increased to a high level. Therefore, the thin film transistors212and214are turned on. Thus, the nodes J and K are electrically connected to the high power supply potential line through the thin film transistor211; i.e., the potentials of the nodes J and K are increased to a high level. Therefore, the thin film transistor223is turned on. Thus, the node L is electrically connected to the low power supply potential line; i.e., the potential of the node L is decreased to a low level.

In a period t16, the potential of the second clock signal (CK2) is decreased to a low level. Therefore, the thin film transistors212and214are turned off, so that the nodes J and K are brought into a floating state. Thus, the potentials of the nodes J and K are maintained at a high level, and the potential of the node L is maintained at a low level.

In a period t17, the potential of the first clock signal (CK1) is increased to a high level. Therefore, the thin film transistors202,204,222, and224are turned on. When the thin film transistors202and204are turned on, the nodes H and I are electrically connected to the high power supply potential line through the thin film transistor201; i.e., the potentials of the nodes H and I are increased to a high level. Therefore, the thin film transistor213is turned on. Thus, the node J is electrically connected to the low power supply potential line; i.e., the potential of the node J is decreased to a low level.

In a period t18, the potential of the first clock signal (CK1) is decreased to a low level. Therefore, the thin film transistors202,204,222, and224are turned off. When the thin film transistors202and204are turned off, the nodes H and I are brought into a floating state. Thus, the potentials of the nodes H and I are maintained at a high level.

In a period t19, the potential of the second clock signal (CK2) is increased to a high level. Therefore, the thin film transistors212and214are turned on. Further, the potential of the node I is maintained at a high level, so that the thin film transistor213is maintained in an on state. Thus, the nodes J and K are electrically connected to the low power supply potential line; i.e., the potential of the node J is maintained at a low level, and the potential of the node K is decreased to a low level. Therefore, the thin film transistor223is turned off. Thus, the node L is electrically connected to the low power supply potential line; i.e., the potential of the node L is maintained at a low level. Further, the potential of the start pulse (SP) is increased to a high level again. Note that the operation accompanying the increase in potential of the start pulse (SP) in periods subsequent to the period is the same as the operation in periods subsequent to the period t11. Therefore, the description is to be referred to here.

In a period t20, the potential of the second clock signal (CK2) is decreased to a low level. Therefore, the thin film transistors212and214are turned off. Thus, the nodes J and K are brought into a floating state. As a result, the potentials of the nodes J and K are maintained at a low level.

Regarding the operation in periods subsequent to the period t20, the aforementioned operation is repeated. Therefore, the description is to be referred to here.

Note that the capacitors (e.g., capacitors205,215, and225) included in the pulse output circuits are provided in order to maintain an output signal of each pulse output circuit.

In each of the plurality of thin film transistors included in the shift register illustrated inFIG. 4A, a channel formation region is formed using an oxide semiconductor. The oxide semiconductor is an oxide semiconductor with reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019(atoms/cm3) or less, and when there is no electric field, the oxide semiconductor serves as an insulator or a semiconductor which is close to an insulator (the semiconductor which is close to an insulator is substantially an insulator). Therefore, off-state current of the thin film transistor having the channel formation region formed using the oxide semiconductor can be reduced. Thus, the leakage of electric charge through the thin film transistor can be suppressed.

For example, with a channel formation region of the thin film transistor204, which is formed using the oxide semiconductor, the level of change in potential in a period where the node I is in a floating state (e.g., the periods t11, t12, t14to t16, and t18to t20), such as decrease of potential in the periods t11, t12, t19, t20, etc., can be suppressed. Thus, a malfunction of the shift register can be prevented. Further, the period where the node I is in a floating state can be made long. In other words, the number of times of data rewriting to the capacitor205(also referred to as refreshing) can be reduced.

Further, a channel formation region of the thin film transistor202which is formed using the oxide semiconductor can reduce a through current which flows from the high power supply potential line to the low power supply potential line in a period where the potential of the start pulse (SP) is at a high level and the potential of the first clock signal (CK1) is at a low level (e.g., the periods t11, t12, t14to t16, and t18to t20). Thus, power consumption of the shift register can be reduced.

Although a depletion type transistor is used for a thin film transistor which is electrically connected to the high power supply potential line in the above-described shift register, an enhancement type transistor can alternatively be used for the thin film transistor. That is, the inverters illustrated inFIGS. 2A and 2Bcan be used for the pulse output circuits of this embodiment.

Although a capacitor is included in each of the pulse output circuits of the shift registers, each of the shift registers can be operated without the capacitor. That is, the inverters illustrated inFIGS. 2C and 2Dcan be used for the pulse output circuits of this embodiment.

In this embodiment, an example of thin film transistors included in the logic circuit in Embodiment 1 or Embodiment 2 is described.

One embodiment of a thin film transistor and a manufacturing method of the thin film transistor of this embodiment is described with reference toFIGS. 5A and 5BandFIGS. 6A to 6E.

FIGS. 5A and 5Billustrate an example of a planar structure and a cross-sectional structure of a thin film transistor. A thin film transistor410illustrated inFIGS. 5A and 5Bis one of top gate thin film transistors.

FIG. 5Ais a plan view of the thin film transistor410having a top-gate structure andFIG. 5Bis a cross-sectional view taken along a line C1-C2inFIG. 5A.

The thin film transistor410includes, over a substrate400having an insulating surface, an insulating layer407, an oxide semiconductor layer412, a source or drain electrode layer415a, a source or drain electrode layer415b, a gate insulating layer402, and a gate electrode layer411. A wiring layer414aand a wiring layer414bare provided so as to be in contact with and electrically connected to the source or drain electrode layer415aand the source or drain electrode layer415b, respectively.

Although description is given using a single-gate thin film transistor as the thin film transistor410, a multi-gate thin film transistor including a plurality of channel formation regions may be formed as needed.

A process of manufacturing the thin film transistor410over the substrate400is described below with reference toFIGS. 6A to 6E.

There is no particular limitation on a substrate that can be used as the substrate400having an insulating surface as long as it has at least heat resistance to withstand heat treatment performed later. A glass substrate formed using barium borosilicate glass, aluminoborosilicate glass, or the like can be used.

When the temperature of the heat treatment performed later is high, a substrate having a strain point of 730° C. or higher is preferably used as the glass substrate. As a material of the glass substrate, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used, for example. Note that by containing barium oxide (BaO) and boron oxide (B2O3) so that the amount of BaO is larger than that of B2O3, a glass substrate is heat-resistant and of more practical use. Therefore, a glass substrate containing BaO than B2O3so that the amount of BaO is larger than that of B2O3is preferably used.

Note that, instead of the glass substrate described above, a substrate formed using an insulator, such as a ceramic substrate, a quartz substrate, or a sapphire substrate, may be used as the substrate. Alternatively, a crystallized glass or the like may be used. Still alternatively, a plastic substrate or the like can be used as appropriate.

First, the insulating layer407which serves as a base film is formed over the substrate400having an insulating surface. As the insulating layer407in contact with the oxide semiconductor layer, an oxide insulating layer such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer is preferably used. Although a plasma CVD method, a sputtering method, or the like can be employed as a method for forming the insulating layer407, the insulating layer407is preferably formed with a sputtering method so that hydrogen is contained in the insulating layer407as little as possible.

In this embodiment, a silicon oxide layer is formed as the insulating layer407with a sputtering method. The substrate400is transferred to a treatment chamber and a sputtering gas from which hydrogen and moisture is removed and which contains high-purity oxygen is introduced, whereby a silicon oxide layer is formed as the insulating layer407over the substrate400with the use of a silicon semiconductor target. The substrate400may be at a room temperature or may be heated.

For example, a silicon oxide layer is formed with an RF sputtering method under the following condition: quartz (preferably, synthetic quartz) is used as a target; the substrate temperature is 108° C.; the distance between the substrate and the target (the T-S distance) is 60 mm; the pressure is 0.4 Pa; the electric power of the high frequency power source is 1.5 kW; and the atmosphere is an atmosphere containing oxygen and argon (the flow ratio of oxygen to argon is 1:1 (each flow rate is 25 sccm). The thickness of the silicon oxide layer is 100 nm. Note that instead of quartz (preferably, synthetic quartz), a silicon target can be used as a target used when the silicon oxide layer is formed. As a sputtering gas, oxygen or a mixed gas of oxygen and argon is used.

In that case, the insulating layer407is preferably formed while removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the insulating layer407.

In order to remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), and the like are evacuated, whereby the concentration of an impurity in the insulating layer407formed in the deposition chamber can be reduced.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the insulating layer407is formed.

Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method in which a DC power source is used, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. An RF sputtering method is mainly used in the case where an insulating film is formed, and a DC sputtering method is mainly used in the case where a metal film is formed.

In addition, there is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be set. With the multi-source sputtering apparatus, films of different materials can be formed to be stacked in the same chamber, or plural kinds of materials can be discharged for film formation at the same time in the same chamber.

In addition, there are a sputtering apparatus provided with a magnet system inside the chamber, which is for a magnetron sputtering method, and a sputtering apparatus which is used for an ECR sputtering method in which plasma produced with the use of microwaves is used without using glow discharge.

Furthermore, as a deposition method using a sputtering method, there are also a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during deposition to form a thin compound film thereof, and a bias sputtering method in which voltage is also applied to a substrate during deposition.

Further, the insulating layer407may have a layered structure in which for example, a nitride insulating layer such as a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer and an oxide insulating layer are stacked in this order from the substrate400side.

For example, a sputtering gas from which hydrogen and moisture are removed and which contains high-purity nitrogen is introduced and a silicon target is used, whereby a silicon nitride layer is formed between a silicon oxide layer and a substrate. In this case, the silicon nitride layer is preferably formed while removing moisture remaining in a treatment chamber, similarly to the silicon oxide layer.

In the case of forming the silicon nitride layer, a substrate may be heated in film formation.

In the case where the stack of the silicon nitride layer and the silicon oxide layer is provided as the insulating layer407, the silicon nitride layer and the silicon oxide layer can be formed with the use of a common silicon target in the same treatment chamber. After a sputtering gas containing nitrogen is introduced first, a silicon nitride layer is formed using a silicon target mounted in the treatment chamber, and then, the sputtering gas is switched to a sputtering gas containing oxygen and the same silicon target is used to form a silicon oxide layer. Since the silicon nitride layer and the silicon oxide layer can be formed successively without being exposed to the air, impurities such as hydrogen and moisture can be prevented from adsorbing onto a surface of the silicon nitride layer.

Then, an oxide semiconductor film is formed to a thickness of 2 nm to 200 nm inclusive over the gate insulating layer407.

Further, in order that hydrogen, a hydroxyl group, and moisture be contained in the oxide semiconductor layer as little as possible, it is preferable that the substrate400over which the insulating layer407is formed be preheated in a preheating chamber of a sputtering apparatus as pretreatment for film formation so that impurities such as hydrogen and moisture adsorbed to the substrate400are eliminated and evacuated. Note that a cryopump is preferable as an evacuation unit provided in the preheating chamber. Note that this preheating treatment may be omitted. Further, this preheating may be similarly performed on the substrate400over which the gate insulating layer402has not been formed and the substrate400over which layers up to the source or drain electrode layer415aand the source or drain electrode layer415bhave been formed.

Note that before the oxide semiconductor layer is formed with a sputtering method, dust attached to a surface of the insulating layer407is preferably removed with reverse sputtering in which an argon gas is introduced and plasma is generated. The reverse sputtering refers to a method in which without application of a voltage to the target side, a high frequency power source is used for application of a voltage to the substrate side in an argon atmosphere so that plasma is generated to modify a surface of the substrate. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used.

The oxide semiconductor layer is formed with a sputtering method. The oxide semiconductor layer is formed using an In—Ga—Zn—O-based oxide semiconductor layer, an In—Sn—Zn—O-based oxide semiconductor layer, an In—Al—Zn—O-based oxide semiconductor layer, a Sn—Ga—Zn—O-based oxide semiconductor layer, an Al—Ga—Zn—O-based oxide semiconductor layer, a Sn—Al—Zn—O-based oxide semiconductor layer, an In—Zn—O-based oxide semiconductor layer, a Sn—Zn—O-based oxide semiconductor layer, an Al—Zn—O-based oxide semiconductor layer, an In—O-based oxide semiconductor layer, a Sn—O-based oxide semiconductor layer, or a Zn—O-based oxide semiconductor layer. In this embodiment, the oxide semiconductor layer is formed with a sputtering method with the use of an In—Ga—Zn—O-based metal oxide target. Further, the oxide semiconductor layer can be formed with a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically, argon) and oxygen. In the case of employing a sputtering method, a target containing SiO2at 2 wt % to 10 wt % inclusive may be used for film formation.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the oxide semiconductor layer is formed.

As a target for forming the oxide semiconductor layer with a sputtering method, a metal oxide target containing zinc oxide as its main component can be used. As another example of a metal oxide target, a metal oxide target containing In, Ga, and Zn (in a composition ratio, In2O3:Ga2O3:ZnO=1:1:1 [mol], In:Ga:Zn=1:1:0.5 [atom]) can be used. Alternatively, a metal oxide target containing In, Ga, and Zn (the composition ratio of In:Ga:Zn=1:1:1 or 1:1:2 [atom]) may be used. The proportion of the volume of a portion except for an area occupied by a space and the like with respect to the total volume of the metal oxide target formed (also referred to as the fill rate of the metal oxide target) is 90% to 100% inclusive, preferably, 95% to 99.9% inclusive. With the use of the metal oxide target with high fill rate, a dense oxide semiconductor layer is formed.

The substrate is held in a treatment chamber kept under reduced pressure, a sputtering gas from which hydrogen and moisture are removed is introduced into the treatment chamber from which remaining moisture is being removed, and the oxide semiconductor layer is formed over the substrate400with the use of a metal oxide as a target. To remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), (more preferably, also a compound containing a carbon atom), and the like are evacuated, whereby the concentration of an impurity in the oxide semiconductor layer formed in the deposition chamber can be reduced. The substrate may be heated when the oxide semiconductor layer is formed.

An example of the deposition condition is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, the electric power of the DC power source is 0.5 kW, and the atmosphere is an atmosphere containing oxygen and argon (the flow ratio of oxygen to argon is 15 sccm:30 sccm). It is preferable that a pulsed DC power source be used because powder substances (also referred to as particles or dust) generated in film formation can be reduced and the film thickness can be uniform. The oxide semiconductor layer preferably has a thickness of 5 nm to 30 nm inclusive. Note that the appropriate thickness depends on an oxide semiconductor material used and the thickness may be selected in accordance with a material.

Then, in a first photolithography process, the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer412(seeFIG. 6A). A resist mask for forming the island-shaped oxide semiconductor layer412may be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

Note that the etching of the oxide semiconductor layer may be dry etching, wet etching, or both dry etching and wet etching.

As the etching gas for dry etching, a gas containing chlorine (chlorine-based gas such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), or carbon tetrachloride (CCl4)) is preferably used.

Alternatively, a gas containing fluorine (fluorine-based gas such as carbon tetrafluoride (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), or trifluoromethane (CHF3)); hydrogen bromide (HBr); oxygen (O2); any of these gases to which a rare gas such as helium (He) or argon (Ar) is added; or the like can be used.

As the dry etching method, a parallel plate RIE (reactive ion etching) method or an ICP (inductively coupled plasma) etching method can be used. In order to etch the film into a desired shape, the etching condition (the amount of electric power applied to a coil-shaped electrode, the amount of electric power applied to an electrode on the substrate side, the temperature of the electrode on the substrate side, or the like) is adjusted as appropriate.

As an etchant used for wet etching, a mixed solution of phosphoric acid, acetic acid, and nitric acid, or the like can be used. Alternatively, ITO07N (produced by KANTO CHEMICAL CO., INC.) may be used.

The etchant used in the wet etching is removed by cleaning together with the material which is etched off. The waste liquid including the etchant and the material etched off may be purified and the material may be reused. When a material such as indium included in the oxide semiconductor layer is collected from the waste liquid after the etching and reused, the resources can be efficiently used and the cost can be reduced.

The etching conditions (such as an etchant, etching time, and temperature) are appropriately adjusted depending on the material so that the oxide semiconductor layer can be etched to have a desired shape.

In this embodiment, the oxide semiconductor layer is processed into the island-shaped oxide semiconductor layer412with a wet etching method with a mixed solution of phosphoric acid, acetic acid, and nitric acid as an etchant.

In this embodiment, the oxide semiconductor layer412is subjected to first heat treatment. The temperature of the first heat treatment is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450° C. for one hour, and then, the oxide semiconductor layer is not exposed to the air so that entry of water and hydrogen into the oxide semiconductor layer is prevented; thus, the oxide semiconductor layer is obtained. Through the first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer412can be conducted.

The apparatus for the heat treatment is not limited to the electric furnace and may be the one provided with a device for heating an object to be processed, using heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermal anneal) apparatus can be used. An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for heat treatment using a high-temperature gas. As the gas, an inert gas which hardly reacts with an object to be processed due to heat treatment, such as nitrogen or a rare gas such as argon is used.

For example, as the first heat treatment, GRTA may be performed as follows. The substrate is transferred and put in an inert gas which has been heated to a high temperature of 650° C. to 700° C., heated for several minutes, and transferred and taken out of the inert gas which has been heated to a high temperature. GRTA enables high-temperature heat treatment in a short time.

Note that in the first heat treatment, it is preferable that water, hydrogen, and the like be not included in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, it is preferable that nitrogen or a rare gas such as helium, neon, or argon introduced into an apparatus for the heat treatment have a purity of 6N (99.9999%) or more, preferably, 7N (99.99999%) or more (that is, an impurity concentration is set to 1 ppm or lower, preferably, 0.1 ppm or lower).

Further, the oxide semiconductor layer might be crystallized to be a microcrystalline film or a polycrystalline film depending on a condition of the first heat treatment or a material of the oxide semiconductor layer412. For example, the oxide semiconductor layer may be crystallized to become a microcrystalline oxide semiconductor layer having a degree of crystallization of 90% or more, or 80% or more. Further, depending on the condition of the first heat treatment and the material of the oxide semiconductor layer412, the oxide semiconductor layer may become an amorphous oxide semiconductor layer containing no crystalline component. The oxide semiconductor layer might become an oxide semiconductor layer in which a microcrystalline portion (with a grain diameter greater than or equal to 1 nm and less than or equal to 20 nm, typically greater than or equal to 2 nm and less than or equal to 4 nm) is mixed into an amorphous oxide semiconductor.

Alternatively, the first heat treatment may be performed on the oxide semiconductor layer which has not yet been processed into the island-shaped oxide semiconductor layer412. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography process is performed.

The heat treatment having an effect of dehydration or dehydrogenation on the oxide semiconductor layer may be performed at any of the following timings: after the oxide semiconductor layer is formed; after a source electrode layer and a drain electrode layer are formed over the oxide semiconductor layer412; and after a gate insulating layer is formed over the source electrode layer and the drain electrode layer.

Next, a conductive layer is formed over the insulating layer407and the oxide semiconductor layer412. The conductive layer may be formed with, for example, a sputtering method or a vacuum evaporation method. As the material of the conductive layer, there are an element selected from Al, Cr, Cu, Ta, Ti, Mo, or W; an alloy including any of the above elements; and the like. Further, one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium may be used. The conductive layer may have a single-layer structure or a layered structure of two or more layers. For example, a single-layer structure of an aluminum layer including silicon, a two-layer structure in which a titanium layer is stacked over an aluminum layer, a three-layer structure in which a Ti layer, an aluminum layer, and a Ti layer are stacked in the order presented, and the like can be given. Alternatively, a layer, an alloy layer, or a nitride layer of a combination of Al and one or plurality of elements selected from the followings may be used: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc).

A second photolithography process is performed. A resist mask is formed over the conductive layer and selective etching is performed, so that the source or drain electrode layer415aand the source or drain electrode layer415bare formed. Then, the resist mask is removed (seeFIG. 6B). Note that the source electrode layer and the drain electrode layer preferably have tapered shapes because coverage with the gate insulating layer stacked thereover can be improved.

In this embodiment, a titanium layer is formed to a thickness of 150 nm with a sputtering method for the source or drain electrode layer415aand the source or drain electrode layer415b.

Note that materials and etching conditions are adjusted as appropriate so that the oxide semiconductor layer412is not removed and the insulating layer407under the oxide semiconductor layer412is not exposed when the conductive layer is etched.

In this embodiment, a Ti layer is used as the conductive film, an In—Ga—Zn—O-based oxide semiconductor is used as the oxide semiconductor layer412, and an ammonia hydrogen peroxide solution (a mixture of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.

Note that in the second photolithography process, only part of the oxide semiconductor layer412is etched, whereby an oxide semiconductor layer having a groove (a depressed portion) might be formed. The resist mask used for forming the source or drain electrode layer415aand the source or drain electrode layer415bmay be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

Ultraviolet, a KrF laser beam, or an ArF laser beam is used for light exposure for forming the resist mask in the second photolithography process. A channel length L of the thin film transistor to be formed later depends on a width of an interval between a bottom portion of the source electrode layer and a bottom portion of the drain electrode layer which are adjacent to each other over the oxide semiconductor layer412. Note that when light exposure is performed in the case where the channel length L is shorter than 25 nm, extreme ultraviolet with extremely short wavelengths of several nanometers to several tens of nanometers is used for light exposure for forming the resist mask in the second photolithography process. Light exposure with extreme ultraviolet leads to a high resolution and a large focal depth. Accordingly, the channel length L of the thin film transistor to be formed later can be set to 10 nm to 1000 nm inclusive. Thus, the operation speed of a circuit can be increased, and further, an off-state current can be significantly small so that low power consumption can be achieved.

Next, a gate insulating layer402is formed over the insulating layer407, the oxide semiconductor layer412, the source or drain electrode layer415a, and the source or drain electrode layer415b(seeFIG. 6C).

The gate insulating layer402can be formed with a single-layer structure or a layered structure using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer with a plasma CVD method, a sputtering method, or the like. Note that the gate insulating layer402is preferably formed with a sputtering method so that the gate insulating layer402contains hydrogen as little as possible. In the case where a silicon oxide layer is formed with a sputtering method, a silicon target or a quartz target is used as a target and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

The gate insulating layer402may have a structure where a silicon oxide layer and a silicon nitride layer are stacked from the side of the source or drain electrode layer415aand the source or drain electrode layer415b. For example, a silicon oxide layer (SiOx(x>0)) with a thickness of 5 nm to 300 nm inclusive is formed as a first gate insulating layer and a silicon nitride layer (SiNy(y>0)) with a thickness of 50 nm to 200 nm inclusive is stacked as a second gate insulating layer over the first gate insulating layer; thus, the gate insulating layer with a thickness of 100 nm may be formed. In this embodiment, a silicon oxide layer is formed to a thickness of 100 nm with an RF sputtering method under the following condition: the pressure is 0.4 Pa; the electric power of the high frequency power source is 1.5 kW; and the atmosphere is an atmosphere containing oxygen and argon (the flow ratio of oxygen to argon is 1:1 (each flow rate is 25 sccm).

Then, a third photolithography process is performed. A resist mask is formed and selective etching is performed to remove parts of the gate insulating layer402, so that openings421aand421breaching the source or drain electrode layer415aand the source or drain electrode layer415b, respectively, are formed (seeFIG. 6D).

Then, after a conductive layer is formed over the gate insulating layer402and in the openings421aand421b, the gate electrode layer411and the wiring layers414aand414bare formed in a fourth photolithography process. Note that a resist mask may be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

Further, the gate electrode layer411and the wiring layers414aand414bcan be formed with a single-layer structure or a layered structure using any of metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, and an alloy material including any of these materials as a main component.

As a two-layer structure of each of the gate electrode layer411and the wiring layers414aand414b, for example, a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked is preferable. As a three-layer structure, a stack of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer is preferable. Note that the gate electrode layer may be formed using a light-transmitting conductive layer. A light-transmitting conductive oxide can be given as an example of the light-transmitting conductive layer.

In this embodiment, a titanium layer is formed to a thickness of 150 nm with a sputtering method for the gate electrode layer411and the wiring layers414aand414b.

Next, second heat treatment (preferably 200° C. to 400° C. inclusive, for example, from 250° C. to 350° C. inclusive) is performed in an inert gas atmosphere or an oxygen gas atmosphere. In this embodiment, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour. The second heat treatment may be performed after a protective insulating layer or a planarization insulating layer is formed over the thin film transistor410.

Further, heat treatment may be performed at 100° C. to 200° C. inclusive for one hour to 30 hours inclusive in the air. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100° C. to 200° C. inclusive and then decreased to a room temperature. Further, this heat treatment may be performed under a reduced pressure. Under a reduced pressure, the heating time can be shortened.

Through the above steps, the thin film transistor410including the oxide semiconductor layer412in which the concentration of hydrogen, moisture, hydride, or hydroxide is reduced can be formed (seeFIG. 6E). The thin film transistor410can be used as the thin film transistor included in the logic circuit in Embodiment 1 or Embodiment 2.

A protective insulating layer or a planarization insulating layer for planarization may be provided over the thin film transistor410. For example, the protective insulating layer may be formed with a single-layer structure or a layered structure using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer.

Although not illustrated, the planarization insulating layer can be formed using a heat-resistant organic material such as polyimide, an acrylic resin, a benzocyclobutene resin, polyamide, or an epoxy resin. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. Note that the planarization insulating layer may be formed by stacking a plurality of insulating layers formed using any of these materials.

Note that a siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may include an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. Moreover, the organic group may include a fluoro group.

There is no particular limitation on the method of forming the planarization insulating layer, and the following method or means can be employed depending on the material: a method such as a sputtering method, an SOG method, a spin coating method, a dipping method, a spray coating method, or a droplet discharge method (e.g., an inkjet method, screen printing, or offset printing), or a tool such as a doctor knife, a roll coater, a curtain coater, or a knife coater.

Moisture remaining in a reaction atmosphere is removed as described above in forming the oxide semiconductor layer, whereby the concentration of hydrogen and hydride in the oxide semiconductor layer can be reduced. Accordingly, the oxide semiconductor layer can be stable.

The logic circuits in Embodiments 1 and 2 including the above-described thin film transistors can have stable electric characteristics and high reliability.

In this embodiment, another example of thin film transistors included in the logic circuit in Embodiment 1 or Embodiment 2 is described. The same portions as those in Embodiment 3 and portions having functions similar to those of the portions in Embodiment 3 and steps similar to those in Embodiment 3 may be handled as in Embodiment 3, and repeated description is omitted. In addition, detailed description of the same portions is also omitted.

One embodiment of a thin film transistor and a manufacturing method of the thin film transistor of this embodiment is described with reference toFIGS. 7A and 7BandFIGS. 8A to 8E.

FIGS. 7A and 7Billustrate an example of a planar structure and a cross-sectional structure of a thin film transistor. A thin film transistor460illustrated inFIGS. 7A and 7Bis one of top gate thin film transistors.

FIG. 7Ais a plan view of the thin film transistor460having a top-gate structure andFIG. 7Bis a cross-sectional view taken along a line D1-D2inFIG. 7A.

The thin film transistor460includes, over a substrate450having an insulating surface, an insulating layer457, a source or drain electrode layer465a(465a1and465a2), an oxide semiconductor layer462, a source or drain electrode layer465b, a wiring layer468, a gate insulating layer452, and a gate electrode layer461(461aand461b). The source or drain electrode layer465a(465a1and465a2) is electrically connected to a wiring layer464through the wiring layer468. Although not illustrated, the source or drain electrode layer465bis electrically connected to a wiring layer through an opening formed in the gate insulating layer452.

A process of manufacturing the thin film transistor460over the substrate450is described below with reference toFIGS. 8A to 8E.

First, the insulating layer457which serves as a base film is formed over the substrate450having an insulating surface.

In this embodiment, a silicon oxide layer is formed as the insulating layer457with a sputtering method. The substrate450is transferred to a treatment chamber and a sputtering gas from which hydrogen and moisture is removed and which contains high-purity oxygen is introduced, whereby a silicon oxide layer is formed as the insulating layer457over the substrate450with the use of a silicon target or a quartz (preferably synthetic quartz). As a sputtering gas, oxygen or a mixed gas of oxygen and argon is used.

For example, a silicon oxide layer is formed with an RF sputtering method under the following condition: the purity of a sputtering gas is 6N; quartz (preferably, synthetic quartz) is used; the substrate temperature is 108° C.; the distance between the substrate and the target (the T-S distance) is 60 mm; the pressure is 0.4 Pa; the electric power of the high frequency power source is 1.5 kW; and the atmosphere is an atmosphere containing oxygen and argon (the flow ratio of oxygen to argon is 1:1 (each flow rate is 25 sccm). The thickness of the silicon oxide layer is 100 nm Note that instead of quartz (preferably, synthetic quartz), a silicon target can be used as a target used when the silicon oxide layer is formed.

In that case, the insulating layer457is preferably formed while removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the insulating layer457. In the deposition chamber which is evacuated with a cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), and the like are evacuated, whereby the concentration of an impurity in the insulating layer457formed in the deposition chamber can be reduced.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the insulating layer457is formed.

Further, the insulating layer457may have a layered structure in which for example, a nitride insulating layer such as a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer and an oxide insulating layer are stacked in this order from the substrate450side.

For example, a sputtering gas from which hydrogen and moisture are removed and which contains high-purity nitrogen is introduced and a silicon target is used, whereby a silicon nitride layer is formed between a silicon oxide layer and a substrate. In this case, the silicon nitride layer is preferably formed while removing remaining moisture in a treatment chamber, similarly to the silicon oxide layer.

Next, a conductive layer is formed over the insulating layer457and a first photolithography process is performed. A resist mask is formed over the conductive layer and selective etching is performed, so that the source or drain electrode layer465a1and465a2is formed. Then, the resist mask is removed (seeFIG. 8A). It seems in cross section as if the source or drain electrode layer465a1and465a2is divided; however, the source or drain electrode layer465a1and465a2is a continuous layer. Note that the source electrode layer and the drain electrode layer preferably have tapered shapes because coverage with the gate insulating layer stacked thereover can be improved.

As the material of the source or drain electrode layer465a1and465a2, there are an element selected from Al, Cr, Cu, Ta, Ti, Mo, or W; an alloy including any of the above elements; and the like. Further, one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium may be used. The conductive layer may have a single-layer structure or a layered structure of two or more layers. For example, a single-layer structure of an aluminum layer including silicon, a two-layer structure in which a titanium layer is stacked over an aluminum layer, a three-layer structure in which a Ti layer, an aluminum layer, and a Ti layer are stacked in the order presented, and the like can be given. Alternatively, a layer, an alloy layer, or a nitride layer of a combination of Al and one or plurality of elements selected from the followings may be used: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc).

In this embodiment, a titanium layer is formed to a thickness of 150 nm with a sputtering method for the source or drain electrode layer465a1and465a2.

Then, an oxide semiconductor layer is formed to a thickness of 2 nm to 200 nm inclusive over the gate insulating layer457and the source or drain electrode layer465a1and465a2.

Then, an oxide semiconductor layer is formed and in a second photolithography process, the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer462(seeFIG. 8B). In this embodiment, the oxide semiconductor layer is formed with a sputtering method with the use of an In—Ga—Zn—O-based metal oxide target.

The substrate is held in a treatment chamber kept under reduced pressure, a sputtering gas from which hydrogen and moisture are removed is introduced into the treatment chamber from which remaining moisture is being removed, and the oxide semiconductor layer is deposited over the substrate450with the use of a metal oxide as a target. To remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), (more preferably, also a compound containing a carbon atom), and the like are evacuated, whereby the concentration of an impurity in the oxide semiconductor layer formed in the deposition chamber can be reduced. The substrate may be heated when the oxide semiconductor layer is formed.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the oxide semiconductor layer is formed.

An example of the deposition condition is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, the electric power of the DC power source is 0.5 kW, and the atmosphere is an atmosphere containing oxygen and argon (the flow ratio of oxygen to argon is 15 sccm:30 sccm). It is preferable that a pulsed DC power source be used because powder substances (also referred to as particles or dust) generated in film formation can be reduced and the film thickness can be uniform. The oxide semiconductor layer preferably has a thickness of 5 nm to 30 nm inclusive. Note that the appropriate thickness depends on an oxide semiconductor material used and the thickness may be selected in accordance with a material.

In this embodiment, the oxide semiconductor layer is processed into the island-shaped oxide semiconductor layer462with a wet etching method with a mixed solution of phosphoric acid, acetic acid, and nitric acid as an etchant.

Next, the oxide semiconductor layer462is subjected to first heat treatment. The temperature of first heat treatment for the first heat treatment is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450° C. for one hour, and then, the oxide semiconductor layer is not exposed to the air so that entry of water and hydrogen into the oxide semiconductor layer is prevented; thus, the oxide semiconductor layer is obtained. Through the first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer462can be conducted.

The apparatus for the heat treatment is not limited to the electric furnace and may be the one provided with a device for heating an object to be processed, using heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermal anneal) apparatus can be used. For example, as the first heat treatment, GRTA may be performed as follows. The substrate is transferred and put in an inert gas which has been heated to a high temperature of 650° C. to 700° C., heated for several minutes, and transferred and taken out of the inert gas which has been heated to a high temperature. GRTA enables high-temperature heat treatment in a short time.

Note that in the first heat treatment, it is preferable that water, hydrogen, and the like be not included in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, it is preferable that nitrogen or a rare gas such as helium, neon, or argon introduced into an apparatus for the heat treatment have a purity of 6N (99.9999%) or more, preferably, 7N (99.99999%) or more (that is, an impurity concentration is set to 1 ppm or lower, preferably, 0.1 ppm or lower).

Further, the oxide semiconductor layer might be crystallized to be a microcrystalline layer or a polycrystalline layer depending on a condition of the first heat treatment or a material of the oxide semiconductor layer.

Alternatively, the first heat treatment of the oxide semiconductor layer may be performed on the oxide semiconductor layer which has not yet been processed into the island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography process is performed.

The heat treatment has an effect of dehydration or dehydrogenation on the oxide semiconductor layer may be performed at any of the following timings: after the oxide semiconductor layer is formed; after a source electrode layer and a drain electrode layer are formed over the oxide semiconductor layer; and after a gate insulating layer is formed over the source electrode layer and the drain electrode layer.

Next, a conductive layer is formed over the insulating layer457and the oxide semiconductor layer462and a third photolithography process is performed. A resist mask is formed over the conductive layer and selective etching is performed, so that the source or drain electrode layer465band the wiring layer468are formed. Then, the resist mask is removed (seeFIG. 8C). The source or drain electrode layer465band the wiring layer468may be formed using a material and steps similar to those of the source or drain electrode layer465a1and465a2.

In this embodiment, a titanium layer is formed to a thickness of 150 nm with a sputtering method for the source or drain electrode layer465band the wiring layer468. In this embodiment, the same titanium layer is used for the source or drain electrode layer465a1and465a2and the source or drain electrode layer465b, so that the etching selectivity of the source or drain electrode layer465a1and465a2is the same as or substantially the same as that of the source or drain electrode layer465b. Therefore, the wiring layer468is provided over a portion of the source or drain electrode layer465a2, which is not covered with the oxide semiconductor layer462, to prevent the source or drain electrode layer465a1and465a2from being etched when the source or drain electrode layer465bis etched. In the case of using different materials which provide high selectivity ratio of the source or drain electrode layer465bto the source or drain electrode layer465a1and465a2in the etching step, the wiring layer468which protects the source or drain electrode layer465a2in etching is not necessarily provided.

Note that materials and etching conditions are adjusted as appropriate so that the oxide semiconductor layer462is not removed when the conductive layer is etched.

In this embodiment, a Ti layer is used as the conductive film, an In—Ga—Zn—O-based oxide semiconductor is used as the oxide semiconductor layer462, and an ammonia hydrogen peroxide solution (a mixture of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.

Note that in the third photolithography process, part of the oxide semiconductor layer462is etched, whereby an oxide semiconductor layer having a groove (a depressed portion) might be formed. The resist mask used for forming the source or drain electrode layer465band the wiring layer468may be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

Next, a gate insulating layer452is formed over the insulating layer457, the oxide semiconductor layer462, the source or drain electrode layer465a1and465a2, the source or drain electrode layer465b, and the wiring layer468.

The gate insulating layer452can be formed with a single-layer structure or a layered structure using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer with a plasma CVD method, a sputtering method, or the like. Note that the gate insulating layer452is preferably formed with a sputtering method so that the gate insulating layer452contains hydrogen as little as possible. In the case where a silicon oxide film is formed with a sputtering method, a silicon target or a quartz target is used as a target and a mixed gas of oxygen and argon is used as a sputtering target.

The gate insulating layer452may have a structure where a silicon oxide layer and a silicon nitride layer are stacked from the side of the source or drain electrode layer465a1and465a2and the source or drain electrode layer465b. In this embodiment, a silicon oxide layer is formed to a thickness of 100 nm with an RF sputtering method under the following condition: the pressure is 0.4 Pa; the electric power of the high frequency power source is 1.5 kW; and the atmosphere is an atmosphere containing oxygen and argon (the flow ratio of oxygen to argon is 1:1 (each flow rate is 25 sccm).

Next, a fourth photolithography process is performed. A resist mask is formed and selective etching is performed to remove part of the gate insulating layer452, so that an opening423reaching the wiring layer468is formed (seeFIG. 8D). Although not illustrated, in forming the opening423, an opening reaching the source or drain electrode layer465bmay be formed. In this embodiment, the opening reaching the source or drain electrode layer465bis formed after an interlayer insulating layer is further stacked, and a wiring layer for electrical connection is formed in the opening.

Then, after a conductive layer is formed over the gate insulating layer452and in the opening423, the gate electrode layer461(461aand461b) and the wiring layer464are formed in a fifth photolithography process. Note that a resist mask may be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

Further, the gate electrode layer461(461aand461b) and the wiring layer464can be formed with a single-layer structure or a layered structure using any of metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, and an alloy material including any of these materials as a main component.

In this embodiment, a titanium layer is formed to a thickness of 150 nm with a sputtering method for the gate electrode layer461(461aand461b) and the wiring layer464.

Next, second heat treatment (preferably 200° C. to 400° C. inclusive, for example, from 250° C. to 350° C. inclusive) is performed in an inert gas atmosphere or an oxygen gas atmosphere. In this embodiment, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour. The second heat treatment may be performed after a protective insulating layer or a planarization insulating layer is formed over the thin film transistor460.

Further, heat treatment may be performed at 100° C. to 200° C. inclusive for one hour to 30 hours inclusive in the air. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100° C. to 200° C. inclusive and then decreased to a room temperature. Further, this heat treatment may be performed under a reduced pressure. Under a reduced pressure, the heating time can be shortened.

Through the above steps, the thin film transistor460including the oxide semiconductor layer462in which the concentration of hydrogen, moisture, hydride, or hydroxide is reduced can be formed (seeFIG. 8E).

A protective insulating layer or a planarization insulating layer for planarization may be provided over the thin film transistor460. Although not illustrated, an opening reaching the source or drain electrode layer465bmay be formed. In this embodiment, the opening reaching the source or drain electrode layer465bis formed in the gate insulating layer452, the protective insulating layer, and the planarization layer, and a wiring layer for electrical connection to the source or drain electrode layer465bis formed in the opening.

Moisture remaining in a reaction atmosphere is removed as described above in forming the oxide semiconductor film, whereby the concentration of hydrogen and hydride in the oxide semiconductor film can be reduced. Accordingly, the oxide semiconductor film can be stable.

The logic circuits in Embodiments 1 and 2 including the above-described thin film transistors can have stable electric characteristics and high reliability.

In this embodiment, another example of thin film transistors included in the logic circuit in Embodiment 1 or Embodiment 2 is described. The same portions as those in Embodiment 3 or Embodiment 4 and portions having functions similar to those of the portions in Embodiment 3 or Embodiment 4 and steps similar to those in Embodiment 3 or Embodiment 4 may be handled as in Embodiment 3 or Embodiment 4, and repeated description is omitted. In addition, detailed description of the same portions is also omitted.

The thin film transistors of this embodiment are described with reference toFIGS. 9A and 9B.

FIGS. 9A and 9Billustrate examples of cross-sectional structures of the thin film transistors. The thin film transistors425and426inFIGS. 9A and 9Bare each one of thin film transistors where an oxide semiconductor layer is sandwiched between a conductive layer and a gate electrode layer.

In addition, inFIGS. 9A and 9B, a silicon substrate is used as a substrate and the thin film transistors425and426are provided over an insulating layer422which is formed over a silicon substrate420.

InFIG. 9A, a conductive layer427is formed between the insulating layer422and the insulating layer407over the silicon substrate420so as to overlap with at least the whole oxide semiconductor layer412.

Note thatFIG. 9Billustrates an example where the conductive layer between the insulating layer422and the insulating layer407is processed like the conductive layer424by etching and overlaps with part of the oxide semiconductor layer412, which includes at least a channel formation region.

The conductive layers427and424may each be formed using a metal material which can resist temperature for heat treatment to be performed in a later step: an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy film containing a combination of any of these elements, a nitride containing any of the above elements as its component, or the like. Further, the conductive layers427and424may each have either a single-layer structure or a layered structure, and for example, a single layer of a tungsten layer or a stack of a tungsten nitride layer and a tungsten layer can be used.

A potential of the conductive layers427and424may be the same as or different from that of the gate electrode layer411of the thin film transistors425and426. The conductive layers427and424can each also function as a second gate electrode layer. The potential of the conductive layers427and424may be a fixed potential such as GND or 0 V.

Electric characteristics of the thin film transistors425and426can be controlled by the conductive layers427and424.

In this embodiment, an example of thin film transistors included in the logic circuit in Embodiment 1 or Embodiment 2 is described.

One embodiment of a thin film transistor and a manufacturing method of the thin film transistor of this embodiment is described with reference toFIGS. 10A to 10E.

FIG. 10Eillustrate an example of a cross-sectional structure of a thin film transistor. A thin film transistor390illustrated inFIG. 10Eis one of bottom gate thin film transistors and is also referred to as an inverted staggered thin film transistor.

Although description is given using a single-gate thin film transistor as the thin film transistor390, a multi-gate thin film transistor including a plurality of channel formation regions may be formed as needed.

A process of manufacturing the thin film transistor390over a substrate394is described below with reference toFIGS. 10A to 10E.

First, after a conductive layer is formed over the substrate394having an insulating surface, a gate electrode layer391is formed in a first photolithography process. The gate electrode layer preferably has a tapered shape because coverage with a gate insulating layer stacked thereover can be improved. Note that a resist mask may be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

There is no particular limitation on a substrate that can be used as the substrate394having an insulating surface as long as it has at least heat resistance to withstand heat treatment performed later. A glass substrate formed using barium borosilicate glass, aluminoborosilicate glass, or the like can be used.

When the temperature of the heat treatment performed later is high, a substrate having a strain point of 730° C. or higher is preferably used as the glass substrate. As a material of the glass substrate, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used, for example. Note that in general, by containing a larger amount of barium oxide (BaO) than boron oxide (B2O3), a glass substrate is heat-resistant and of more practical use. Therefore, a glass substrate containing a larger amount of BaO than B2O3is preferably used.

Note that, instead of the glass substrate described above, a substrate formed using an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used as the substrate394. Alternatively, a crystallized glass substrate or the like may be used. Still alternatively, a plastic substrate or the like can be used as appropriate.

An insulating layer serving as a base layer may be provided between the substrate394and the gate electrode layer391. The base layer has a function of preventing diffusion of an impurity element from the substrate394, and can be formed with a single-layer structure or a layered structure using any of a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, and a silicon oxynitride layer.

Further, the gate electrode layer391can be formed with a single-layer structure or a layered structure using any of metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, and an alloy material including any of these materials as a main component.

As a two-layer structure of the gate electrode layer391, for example, a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked is preferable. As a three-layer structure, a stack of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer is preferable. Note that the gate electrode layer may be formed using a light-transmitting conductive layer. A light-transmitting conductive oxide can be given as an example of the light-transmitting conductive layer.

Then, the gate insulating layer397is formed over the gate electrode layer391.

The gate insulating layer397can be formed with a single-layer structure or a layered structure using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer with a plasma CVD method, a sputtering method, or the like. Note that the gate insulating layer397is preferably formed with a sputtering method so that the gate insulating layer397contains hydrogen as little as possible. In the case where a silicon oxide layer is formed with a sputtering method, a silicon target or a quartz target is used as a target and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

The gate insulating layer397may have a structure where a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer391side. For example, a silicon nitride layer (SiNy(y>0)) with a thickness of 50 nm to 200 nm inclusive is formed with a sputtering method as a first gate insulating layer and a silicon oxide layer (SiOx(x>0)) with a thickness of 5 nm to 300 nm inclusive is stacked as a second gate insulating layer over the first gate insulating layer; thus, the gate insulating layer with a thickness of 100 nm may be formed.

Further, in order that hydrogen, a hydroxyl group, and moisture might be contained in the gate insulating layer397and an oxide semiconductor layer393to be formed later as little as possible, it is preferable that the substrate394over which the gate electrode layer391is formed or the substrate394over which layers up to the gate insulating layer397are formed be preheated in a preheating chamber of a sputtering apparatus as pretreatment for film formation so that impurities such as hydrogen and moisture adsorbed to the substrate394is eliminated and evacuated. The temperature for the preheating is 100° C. to 400° C. inclusive, preferably 150° C. to 300° C. inclusive. Note that a cryopump is preferable as an evacuation unit provided in the preheating chamber. Note that this preheating treatment may be omitted. Further, this preheating may be similarly performed on the substrate394over which an oxide insulating layer396has not been formed and the substrate394over which layers up to a source electrode layer395aand a drain electrode layer395bhave been formed.

Then, the oxide semiconductor layer393is formed to a thickness of 2 nm to 200 nm inclusive over the gate insulating layer397(seeFIG. 10A).

Note that before the oxide semiconductor layer393is formed with a sputtering method, dust attached to a surface of the gate insulating layer397is preferably removed with reverse sputtering in which an argon gas is introduced and plasma is generated. The reverse sputtering refers to a method in which, without application of a voltage to a target side, an RF power source is used for application of a voltage to a substrate side in an argon atmosphere to modify a surface. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used.

The oxide semiconductor layer393is formed with a sputtering method. The oxide semiconductor layer393is formed using an In—Ga—Zn—O-based oxide semiconductor layer, an In—Sn—Zn—O-based oxide semiconductor layer, an In—Al—Zn—O-based oxide semiconductor layer, a Sn—Ga—Zn—O-based oxide semiconductor layer, an Al—Ga—Zn—O-based oxide semiconductor layer, a Sn—Al—Zn—O-based oxide semiconductor layer, an In—Zn—O-based oxide semiconductor layer, a Sn—Zn—O-based oxide semiconductor layer, an Al—Zn—O-based oxide semiconductor layer, an In—O-based oxide semiconductor layer, a Sn—O-based oxide semiconductor layer, or a Zn—O-based oxide semiconductor layer. In this embodiment, the oxide semiconductor layer393is formed with a sputtering method with the use of an In—Ga—Zn—O-based metal oxide target. Further, the oxide semiconductor layer393can be formed with a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically, argon) and oxygen. In the case of employing a sputtering method, a target containing SiO2at 2 wt % to 10 wt % inclusive may be used for film formation.

As a target for forming the oxide semiconductor layer393with a sputtering method, a metal oxide target containing zinc oxide as its main component can be used. As another example of a metal oxide target, an oxide semiconductor film formation target containing In, Ga, and Zn (in a composition ratio, In2O3:Ga2O3:ZnO=1:1:1 [mol], In:Ga:Zn=1:1:0.5 [atom]) can be used. Alternatively, a metal oxide target containing In, Ga, and Zn (the composition ratio of In:Ga:Zn=1:1:1 or 1:1:2 [atom]) may be used. The fill rate of the metal oxide target is 90% to 100% inclusive, preferably, 95% to 99.9% inclusive. With the use of the metal oxide target with high fill rate, a dense oxide semiconductor layer is formed.

The substrate is held in a treatment chamber kept under reduced pressure, and the substrate is heated to room temperature or a temperature of lower than 400° C. Then, a sputtering gas from which hydrogen and moisture are removed is introduced into the treatment chamber from which remaining moisture is being removed, and the oxide semiconductor layer393is formed over the substrate394with the use of a metal oxide as a target. To remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), (more preferably, also a compound containing a carbon atom), and the like are evacuated, whereby the concentration of an impurity in the oxide semiconductor film formed in the deposition chamber can be reduced. By performing deposition by sputtering while removing moisture remaining in the treatment chamber using a cryopump, a substrate temperature when the oxide semiconductor layer393is formed can be higher than or equal to room temperature and lower than 400° C.

An example of the deposition condition is as follows: the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the electric power of the DC power source is 0.5 kW, and the atmosphere is an oxygen atmosphere (the flow rate of oxygen is 100%). It is preferable that a pulsed DC power source be used because powder substances generated in film formation can be reduced and the film thickness can be uniform. The oxide semiconductor layer preferably has a thickness of 5 nm to 30 nm inclusive. Note that the appropriate thickness depends on an oxide semiconductor material used and the thickness may be selected in accordance with a material.

Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method in which a DC power source is used, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. An RF sputtering method is mainly used in the case where an insulating film is formed, and a DC sputtering method is mainly used in the case where a metal film is formed.

In addition, there is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be set. With the multi-source sputtering apparatus, films of different materials can be formed to be stacked in the same chamber, or plural kinds of materials can be discharged for film formation at the same time in the same chamber.

In addition, there are a sputtering apparatus provided with a magnet system inside the chamber, which is for a magnetron sputtering method, and a sputtering apparatus which is used for an ECR sputtering method in which plasma produced with the use of microwaves is used without using glow discharge.

Furthermore, as a deposition method using a sputtering method, there are also a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during deposition to form a thin compound film thereof, and a bias sputtering method in which voltage is also applied to a substrate during deposition.

Then, in a second photolithography process, the oxide semiconductor layer393is processed into an island-shaped oxide semiconductor layer399(seeFIG. 10B). A resist mask for forming the island-shaped oxide semiconductor layer399may be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

In the case of forming a contact hole in the gate insulating layer397, the step may be performed in forming the oxide semiconductor layer399.

Note that the etching of the oxide semiconductor layer393may be dry etching, wet etching, or both dry etching and wet etching.

As the etching gas for dry etching, a gas containing chlorine (chlorine-based gas such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), or carbon tetrachloride (CCl4)) is preferably used.

Alternatively, a gas containing fluorine (fluorine-based gas such as carbon tetrafluoride (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), or trifluoromethane (CHF3)); hydrogen bromide (HBr); oxygen (O2); any of these gases to which a rare gas such as helium (He) or argon (Ar) is added; or the like can be used.

As the dry etching method, a parallel plate RIE (reactive ion etching) method or an ICP (inductively coupled plasma) etching method can be used. In order to etch the layer into a desired shape, the etching condition (the amount of electric power applied to a coil-shaped electrode, the amount of electric power applied to an electrode on the substrate side, the temperature of the electrode on the substrate side, or the like) is adjusted as appropriate.

As an etchant used for wet etching, a mixed solution of phosphoric acid, acetic acid, and nitric acid, or the like can be used. Alternatively, ITO07N (produced by KANTO CHEMICAL CO., INC.) may be used.

The etchant used in the wet etching is removed by cleaning together with the material which is etched off. The waste liquid including the etchant and the material etched off may be purified and the material may be reused. When a material such as indium included in the oxide semiconductor layer is collected from the waste liquid after the etching and reused, the resources can be efficiently used and the cost can be reduced.

The etching conditions (such as an etchant, etching time, and temperature) are appropriately adjusted depending on the material so that the oxide semiconductor layer can be etched to have a desired shape.

Note that it is preferable to perform reverse sputtering before formation of a conductive layer in the following step so that a resist residue and the like attached to surfaces of the oxide semiconductor layer399and the gate insulating layer397can be removed.

Next, a conductive layer is formed over the gate insulating layer397and the oxide semiconductor layer399. The conductive layer may be formed with a sputtering method or a vacuum evaporation method. As the material of the conductive layer, there are an element selected from Al, Cr, Cu, Ta, Ti, Mo, or W; an alloy layer containing a combination of any of these elements; and the like. Further, one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium may be used. The metal conductive layer may have a single-layer structure or a layered structure of two or more layers. For example, a single-layer structure of an aluminum film including silicon, a two-layer structure in which a titanium layer is stacked over an aluminum layer, a three-layer structure in which a Ti layer, an aluminum layer, and a Ti layer are stacked in the order presented, and the like can be given. Alternatively, a layer, an alloy layer, or a nitride layer of a combination of Al and one or plurality of elements selected from the followings may be used: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc).

A third photolithography process is performed. A resist mask is formed over the conductive layer and selective etching is performed, so that the source electrode layer395aand the drain electrode layer395bare formed. Then, the resist mask is removed (seeFIG. 10C).

Ultraviolet, a KrF laser beam, or an ArF laser beam is used for light exposure for forming the resist mask in the third photolithography process. A channel length L of the thin film transistor to be formed later depends on a width of an interval between a bottom portion of the source electrode layer and a bottom portion of the drain electrode layer which are adjacent to each other over the oxide semiconductor layer399. Note that when light exposure is performed in the case where the channel length L is shorter than 25 nm, extreme ultraviolet with extremely short wavelengths of several nanometers to several tens of nanometers is used for light exposure for forming the resist mask in the third photolithography process. Light exposure with extreme ultraviolet leads to a high resolution and a large focal depth. Accordingly, the channel length L of the thin film transistor to be formed later can be set to 10 nm to 1000 nm inclusive. Thus, the operation speed of a circuit can be increased, and further, an off-state current is significantly small, so that low power consumption can be achieved.

Note that materials and etching conditions are adjusted as appropriate so that the oxide semiconductor layer399is not removed when the conductive layer is etched.

In this embodiment, a Ti layer is used as the metal conductive film, an In—Ga—Zn—O-based oxide semiconductor is used as the oxide semiconductor layer399, and an ammonia hydrogen peroxide solution (a mixture of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.

Note that in the third photolithography process, only part of the oxide semiconductor layer399is etched, whereby an oxide semiconductor layer having a groove (a depressed portion) might be formed. The resist mask used for forming the source electrode layer395aand the drain electrode layer395bmay be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

To reduce the number of photomasks and steps in a photolithography step, etching may be performed with the use of a resist mask formed using a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. Since a resist mask formed using a multi-tone mask has a plurality of thicknesses and can be further changed in shape by performing etching, the resist mask can be used in a plurality of etching steps to provide different patterns. Thus, a resist mask corresponding to at least two kinds of different patterns can be formed by using a multi-tone mask. Accordingly, the number of light-exposure masks can be reduced and the number of corresponding photolithography steps can be also reduced, whereby simplification of a process can be realized.

With plasma treatment with a gas such as N2O, N2, or Ar, water adsorbed to a surface of an exposed portion of the oxide semiconductor layer may be removed. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

In the case of performing the plasma treatment, the oxide insulating layer396is formed without exposure to the air as an oxide insulating layer which serves as a protective insulating layer and is in contact with part of the oxide semiconductor layer396(seeFIG. 10D). In this embodiment, the oxide insulating layer396is formed in contact with the oxide semiconductor layer399in a region where the oxide semiconductor layer399does not overlap with the source electrode layer395aand the drain electrode layer395b.

In this embodiment, the substrate394over which layers up to the island-shaped oxide semiconductor layer399, the source electrode layer395a, the drain electrode layer395bhave been formed is heated to room temperature or a temperature of lower than 100° C. and a sputtering gas from which hydrogen and moisture are removed and which contains high-purity oxygen is introduced, and a silicon target is used, whereby a silicon oxide layer having a defect is formed as the oxide insulating layer396.

For example, the silicon oxide layer is formed with a pulsed DC sputtering method in which the purity of a sputtering gas is 6N, a boron-doped silicon target (the resistivity is 0.01 Ω·cm) is used, the distance between the substrate and the target (T-S distance) is 89 mm, the pressure is 0.4 Pa, the electric power of the DC power source is 6 kW, and the atmosphere is an oxygen atmosphere (the oxygen flow rate is 100%). The thickness of the silicon oxide layer is 300 nm. Note that instead of a silicon target, quartz (preferably, synthetic quartz) can be used as a target used when the silicon oxide layer is formed. As a sputtering gas, oxygen or a mixed gas of oxygen and argon is used.

In that case, the oxide insulating layer396is preferably formed while removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor layer399and the oxide insulating layer396.

In order to remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), and the like are evacuated, whereby the concentration of an impurity in the oxide insulating layer396formed in the deposition chamber can be reduced.

Note that as the oxide insulating layer396, a silicon oxynitride layer, an aluminum oxide layer, an aluminum oxynitride layer, or the like may be used instead of the silicon oxide layer.

Further, heat treatment may be performed at 100° C. to 400° C. while the oxide insulating layer396and the oxide semiconductor layer399are in contact with each other. Since the oxide insulating layer396in this embodiment has a lot of defects, with this heat treatment, an impurity such as hydrogen, moisture, a hydroxyl group, or hydride contained in the oxide semiconductor layer399can be diffused to the oxide insulating layer396so that the impurity in the oxide semiconductor layer399can be further reduced.

Through the above steps, the thin film transistor390including the oxide semiconductor layer392in which the concentration of hydrogen, moisture, hydride, or hydroxide is reduced can be formed (seeFIG. 10E).

Moisture remaining in a reaction atmosphere is removed as described above in forming the oxide semiconductor layer, whereby the concentration of hydrogen and hydride in the oxide semiconductor layer can be reduced. Accordingly, the oxide semiconductor layer can be stable.

A protective insulating layer may be provided over the oxide insulating layer. In this embodiment, the protective insulating layer398is formed over the oxide insulating layer396. As the protective insulating layer398, a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, an aluminum nitride oxide layer, or the like is used.

The substrate394over which layers up to the oxide insulating layer396have been formed is heated to a temperature of 100° C. to 400° C., a sputtering gas from which hydrogen and moisture are removed and which contains high-purity nitrogen is introduced, and a silicon semiconductor target is used, whereby a silicon nitride layer is formed as the protective insulating layer398. In this case, the protective insulating layer398is preferably formed while removing moisture remaining in a treatment chamber, similarly to the oxide insulating layer396.

In the case where the protective insulating layer398is formed, the substrate394is heated to 100° C. to 400° C. in forming the protective insulating layer398, whereby hydrogen or water contained in the oxide semiconductor layer can be diffused to the oxide insulating layer. In that case, heat treatment is not necessarily performed after formation of the oxide insulating layer396.

In the case where the silicon oxide layer is formed as the oxide insulating layer396and the silicon nitride layer is stacked thereover as the protective insulating layer398, the silicon oxide layer and the silicon nitride layer can be formed with the use of a common silicon target in the same treatment chamber. After a sputtering gas containing oxygen is introduced first, a silicon oxide layer is formed using a silicon target mounted in the treatment chamber, and then, the sputtering gas is switched to a sputtering gas containing nitrogen and the same silicon target is used to form a silicon nitride layer. Since the silicon oxide layer and the silicon nitride layer can be formed successively without being exposed to the air, impurities such as hydrogen and moisture can be prevented from adsorbing onto a surface of the silicon oxide layer. In that case, after the silicon oxide layer is formed as the oxide insulating layer396and the silicon nitride layer is stacked thereover as the protective insulating layer398, heat treatment (at a temperature of 100° C. to 400° C.) for diffusing hydrogen or moisture contained in the oxide semiconductor layer to the oxide insulating layer is preferably performed.

After the protective insulating layer is formed, heat treatment may be further performed at 100° C. to 200° C. inclusive for one hour to 30 hours inclusive in the air. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100° C. to 200° C. inclusive and then decreased to a room temperature. Further, this heat treatment may be performed under a reduced pressure before formation of the oxide insulating layer. Under a reduced pressure, the heating time can be shortened. With this heat treatment, the thin film transistor can be normally off. Therefore, reliability of the thin film transistor can be improved.

Moisture remaining in a reaction atmosphere is removed in forming the oxide semiconductor layer including a channel formation region over the gate insulating layer, whereby the concentration of hydrogen and hydride in the oxide semiconductor layer can be reduced.

The above steps can be used for manufacture of backplanes (substrates over which thin film transistors are formed) of liquid crystal display panels, electroluminescent display panels, display devices using electronic ink, or the like. Since the above steps can be performed at a temperature of 400° C. or lower, they can also be applied to manufacturing steps where a glass substrate with a thickness of 1 mm or smaller and a side of longer than 1 m is used. In addition, since all of the above steps can be performed at a treatment temperature of 400° C. or lower, display panels can be manufactured without consuming much energy.

The logic circuits in Embodiments 1 and 2 including the above-described thin film transistors can have stable electric characteristics and high reliability.

In this embodiment, an example of thin film transistors included in the logic circuit in Embodiment 1 or Embodiment 2 is described.

One embodiment of a thin film transistor and a manufacturing method of the thin film transistor of this embodiment is described with reference toFIGS. 11A to 11E.

FIGS. 11A to 11Eillustrate an example of a cross-sectional structure of a thin film transistor. A thin film transistor310illustrated inFIG. 11Dis one of bottom gate thin film transistors and is also referred to as an inverted staggered thin film transistor.

Although description is given using a single-gate thin film transistor as the thin film transistor310, a multi-gate thin film transistor including a plurality of channel formation regions may be formed as needed.

A process of manufacturing the thin film transistor310over a substrate300is described below with reference toFIGS. 11A to 11E.

First, after a conductive layer is formed over the substrate300having an insulating surface, a gate electrode layer311is formed in a first photolithography process. Note that a resist mask may be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

There is no particular limitation on a substrate that can be used as the substrate300having an insulating surface as long as it has at least heat resistance enough to withstand heat treatment performed later. A glass substrate formed using barium borosilicate glass, aluminoborosilicate glass, or the like can be used.

When the temperature of the heat treatment performed later is high, a substrate having a strain point of 730° C. or higher is preferably used as the glass substrate. As a material of the glass substrate, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used, for example. Note that by containing a larger amount of barium oxide (BaO) than boron oxide (B2O3), a glass substrate is heat-resistant and of more practical use. Therefore, a glass substrate containing a larger amount of BaO than B2O3is preferably used.

Note that, instead of the glass substrate described above, a substrate formed using an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used as the substrate. Alternatively, a crystallized glass substrate or the like may be used.

An insulating layer serving as a base layer may be provided between the substrate300and the gate electrode layer311. The base layer has a function of preventing diffusion of an impurity element from the substrate300, and can be formed with a single-layer structure or a layered structure using any of a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, and a silicon oxynitride layer.

Further, the gate electrode layer311can be formed with a single-layer structure or a layered structure using any of metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, and an alloy material including any of these materials as a main component.

As a two-layer structure of the gate electrode layer311, for example, a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked is preferable. As a three-layer structure, a stack of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer is preferable.

Then, the gate insulating layer302is formed over the gate electrode layer311.

The gate insulating layer302can be formed with a single-layer structure or a layered structure using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer with a plasma CVD method, a sputtering method, or the like. For example, a silicon oxynitride layer may be formed with a plasma CVD method with SiH4, oxygen, and nitrogen for a deposition gas. For example, the thickness of the gate insulating layer302is 100 nm to 500 nm inclusive, and in the case where the gate insulating layer302has a layered structure, a second gate insulating layer with a thickness of 5 nm to 300 nm inclusive is stacked over a first gate insulating layer with a thickness of 50 nm to 200 nm inclusive, for example.

In this embodiment, a silicon oxynitride layer having a thickness of smaller than or equal to 100 nm is formed as the gate insulating layer302with a plasma CVD method.

Then, an oxide semiconductor layer330is formed to a thickness of 2 nm to 200 nm inclusive over the gate insulating layer302.

Note that before the oxide semiconductor layer330is formed with a sputtering method, dust attached to a surface of the gate insulating layer302is preferably removed with reverse sputtering in which an argon gas is introduced and plasma is generated. Note that instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used.

The oxide semiconductor layer330is formed using an In—Ga—Zn—O-based oxide semiconductor layer, an In—Sn—Zn—O-based oxide semiconductor layer, an In—Al—Zn—O-based oxide semiconductor layer, a Sn—Ga—Zn—O-based oxide semiconductor layer, an Al—Ga—Zn—O-based oxide semiconductor layer, a Sn—Al—Zn—O-based oxide semiconductor layer, an In—Zn—O-based oxide semiconductor layer, a Sn—Zn—O-based oxide semiconductor layer, an Al—Zn—O-based oxide semiconductor layer, an In—O-based oxide semiconductor layer, a Sn—O-based oxide semiconductor layer, or a Zn—O-based oxide semiconductor layer. In this embodiment, the oxide semiconductor layer330is formed with a sputtering method with the use of an In—Ga—Zn—O-based oxide semiconductor target.FIG. 11Acorresponds to a cross-sectional view at this stage. Further, the oxide semiconductor layer330can be formed with a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere containing a rare gas (typically, argon) and oxygen. In the case of employing a sputtering method, a target containing SiO2at 2 wt % to 10 wt % inclusive may be used for film formation.

As a target for forming the oxide semiconductor layer330with a sputtering method, a metal oxide target containing zinc oxide as its main component can be used. As another example of a metal oxide target, a metal oxide target containing In, Ga, and Zn (in a composition ratio, In2O3:Ga2O3:ZnO=1:1:1 [mol], In:Ga:Zn=1:1:0.5 [atom]) can be used. Alternatively, a metal oxide target containing In, Ga, and Zn (the composition ratio of In:Ga:Zn=1:1:1 or 1:1:2 [atom]) may be used. The fill rate of the metal oxide target is 90% to 100% inclusive, preferably, 95% to 99.9% inclusive. With the use of the metal oxide target with high fill rate, a dense oxide semiconductor layer is formed.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the oxide semiconductor layer330is formed.

The substrate is held in a treatment chamber kept under reduced pressure, and the substrate temperature is set to 100° C. to 600° C., preferably 200° C. to 400° C. Film formation is performed while the substrate is heated, whereby the concentration of an impurity contained in the oxide semiconductor layer formed can be reduced. Further, damages due to sputtering can be reduced. Then, a sputtering gas from which hydrogen and moisture are removed is introduced into the treatment chamber from which remaining moisture is being removed, and the oxide semiconductor layer330is formed over the substrate300with the use of a metal oxide as a target. To remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), (more preferably, also a compound containing a carbon atom), and the like are evacuated, whereby the concentration of an impurity in the oxide semiconductor layer formed in the deposition chamber can be reduced.

An example of the deposition condition is as follows: the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the electric power of the DC power source is 0.5 kW, and the atmosphere is an oxygen atmosphere (the flow rate of oxygen is 100%). It is preferable that a pulsed DC power source be used because powder substances generated in film formation can be reduced and the film thickness can be uniform. The oxide semiconductor layer preferably has a thickness of 5 nm to 30 nm inclusive. Note that the appropriate thickness depends on an oxide semiconductor material used and the thickness may be selected in accordance with a material.

Then, in a second photolithography process, the oxide semiconductor layer330is processed into an island-shaped oxide semiconductor layer. A resist mask for forming the island-shaped oxide semiconductor layer may be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

Next, the oxide semiconductor layer is subjected to first heat treatment. With the first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be conducted. The temperature of the first heat treatment is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450° C. for one hour, and then, the oxide semiconductor layer is not exposed to the air so that entry of water and hydrogen into the oxide semiconductor layer is prevented; thus, an oxide semiconductor layer331is obtained (seeFIG. 11B).

The apparatus for the heat treatment is not limited to the electric furnace and may be the one provided with a device for heating an object to be processed, using heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermal anneal) apparatus can be used. An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus is an apparatus for heat treatment using a high-temperature gas. As the gas, an inert gas which does not react with an object to be processed due to heat treatment, such as nitrogen or a rare gas such as argon is used.

For example, as the first heat treatment, GRTA may be performed as follows. The substrate is transferred and put in an inert gas which has been heated to a high temperature of 650° C. to 700° C., heated for several minutes, and transferred and taken out of the inert gas which has been heated to a high temperature. GRTA enables high-temperature heat treatment in a short time.

Note that in the first heat treatment, it is preferable that water, hydrogen, and the like be not included in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, it is preferable that nitrogen or a rare gas such as helium, neon, or argon introduced into an apparatus for the heat treatment have a purity of 6N (99.9999%) or more, preferably, 7N (99.99999%) or more (that is, an impurity concentration is set to 1 ppm or lower, preferably, 0.1 ppm or lower).

Further, the oxide semiconductor layer might be crystallized to be a microcrystalline layer or a polycrystalline layer depending on a condition of the first heat treatment or a material of the oxide semiconductor layer. For example, the oxide semiconductor layer may be crystallized to become a microcrystalline oxide semiconductor layer having a degree of crystallization of 90% or more, or 80% or more. Further, depending on the condition of the first heat treatment and the material of the oxide semiconductor layer, the oxide semiconductor layer may become an amorphous oxide semiconductor layer containing no crystalline component. The oxide semiconductor layer might become an oxide semiconductor layer in which a microcrystalline portion (with a grain diameter greater than or equal to 1 nm and less than or equal to 20 nm, typically greater than or equal to 2 nm and less than or equal to 4 nm) is mixed into an amorphous oxide semiconductor.

Alternatively, the first heat treatment of the oxide semiconductor layer may be performed on the oxide semiconductor layer330which has not yet been processed into the island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography process is performed.

The heat treatment having an effect of dehydration or dehydrogenation on the oxide semiconductor layer may be performed at any of the following timings: after the oxide semiconductor layer is formed; after a source electrode layer and a drain electrode layer are formed over the oxide semiconductor layer; and after a protective insulating layer is formed over the source electrode layer and the drain electrode layer.

In the case of forming a contact hole in the gate insulating layer302, the step may be performed either before or after dehydration or dehydrogenation of the oxide semiconductor layer.

Note that the etching of the oxide semiconductor film is not limited to wet etching and may be dry etching.

The etching conditions (such as an etchant, etching time, and temperature) are appropriately adjusted depending on the material so that the material can be etched into a desired shape.

Next, a conductive layer is formed over the gate insulating layer302and the oxide semiconductor layer331. The conductive layer may be formed with a sputtering method or a vacuum evaporation method. As the material of the conductive layer, there are an element selected from Al, Cr, Cu, Ta, Ti, Mo, or W; an alloy layer containing a combination of any of these elements; and the like. Further, one or more materials selected from manganese, magnesium, zirconium, beryllium, and thorium may be used. The conductive film may have a single-layer structure or a layered structure of two or more layers. For example, a single-layer structure of an aluminum layer including silicon, a two-layer structure in which a titanium layer is stacked over an aluminum layer, a three-layer structure in which a Ti layer, an aluminum layer, and a Ti layer are stacked in the order presented, and the like can be given. Alternatively, a layer, an alloy layer, or a nitride layer of a combination of Al and one or plurality of elements selected from the followings may be used: titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc).

If heat treatment is performed after formation of the conductive layer, it is preferable that the conductive layer have heat resistance enough to withstand the heat treatment.

A third photolithography process is performed. A resist mask is formed over the conductive layer and selective etching is performed, so that a source electrode layer315aand a drain electrode layer315bare formed. Then, the resist mask is removed (seeFIG. 11C).

Ultraviolet, a KrF laser beam, or an ArF laser beam is used for light exposure for forming the resist mask in the third photolithography process. A channel length L of the thin film transistor to be formed later depends on a width of an interval between a bottom portion of the source electrode layer and a bottom portion of the drain electrode layer which are adjacent to each other over the oxide semiconductor layer331. Note that when light exposure is performed in the case where the channel length L is shorter than 25 nm, extreme ultraviolet with extremely short wavelengths of several nanometers to several tens of nanometers is used for light exposure for forming the resist mask in the third photolithography process. Light exposure with extreme ultraviolet leads to a high resolution and a large focal depth. Accordingly, the channel length L of the thin film transistor to be formed later can be set to 10 nm to 1000 nm inclusive. Thus, the operation speed of a circuit can be increased, and further, an off-state current is significantly small, so that low power consumption can be achieved.

Note that materials and etching conditions are adjusted as appropriate so that the oxide semiconductor layer331is not removed when the conductive layer is etched.

In this embodiment, a Ti layer is used as the conductive layer, an In—Ga—Zn—O-based oxide semiconductor is used as the oxide semiconductor layer331, and an ammonia hydrogen peroxide solution (a mixture of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.

Note that in the third photolithography process, only part of the oxide semiconductor layer331is etched, whereby an oxide semiconductor layer having a groove (a depressed portion) might be formed. The resist mask used for forming the source electrode layer315aand the drain electrode layer315bmay be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

Further, an oxide conductive layer may be formed between the oxide semiconductor layer and the source and drain electrode layers. The oxide conductive layer and a metal layer for forming the source and drain electrode layers can be formed successively. The oxide conductive layer can function as a source region and a drain region.

When the oxide conductive layer is provided as the source region and the drain region between the oxide semiconductor layer and the source and drain electrode layers, the source region and the drain region can have lower resistance and the transistor can operate at high speed.

To reduce the number of photomasks and steps in a photolithography step, etching may be performed with the use of a resist mask formed using a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. Since a resist mask formed using a multi-tone mask has a plurality of thicknesses and can be further changed in shape by performing etching, the resist mask can be used in a plurality of etching steps to provide different patterns. Thus, a resist mask corresponding to at least two kinds of different patterns can be formed by using a single multi-tone mask. Accordingly, the number of light-exposure masks can be reduced and the number of corresponding photolithography steps can be also reduced, whereby simplification of a process can be realized.

Next, plasma treatment with a gas such as N2O, N2, or Ar is performed. With this plasma treatment, water adsorbed to a surface of an exposed portion of the oxide semiconductor layer is removed. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

After the plasma treatment is performed, an oxide insulating layer316which serves as a protective insulating layer and is in contact with part of the oxide semiconductor layer is formed without exposure to the air.

The oxide insulating layer316can be formed to a thickness of longer than or equal to 1 nm with a sputtering method or the like as appropriate, which is a method with which an impurity such as water or hydrogen does not enter the oxide insulating layer316. When hydrogen is contained in the oxide insulating layer316, entry of the hydrogen to the oxide semiconductor layer or extraction of oxygen in the oxide semiconductor layer by the hydrogen is caused, whereby a backchannel of the oxide semiconductor layer comes to be n-type (to have a lower resistance) and thus a parasitic channel might be formed. Therefore, it is important that a formation method in which hydrogen is not used is employed so that the oxide insulating layer316is formed containing as little hydrogen as possible.

In this embodiment, a silicon oxide layer is formed to a thickness of 200 nm as the oxide insulating layer316with a sputtering method. The substrate temperature in film formation may be higher than or equal to room temperature and lower than or equal to 300° C. and in this embodiment, is 100° C. The silicon oxide layer can be formed with a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically, argon) and oxygen. Further, a silicon oxide target or a silicon target can be used as a target. For example, the silicon oxide layer can be formed using a silicon target with a sputtering method in an atmosphere containing oxygen and nitrogen. The oxide insulating layer316which is formed in contact with the oxide semiconductor layer in a region which is in an oxygen-deficient state and thus is n-type, that is, has a lower resistance is formed using an inorganic insulating layer that does not contain impurities such as moisture, a hydrogen ion, and OH−and blocks entry of such impurities from the outside, typically, a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer.

In that case, the oxide insulating layer316is preferably formed while removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor layer331and the oxide insulating layer316.

In order to remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), and the like are evacuated, whereby the concentration of an impurity in the oxide insulating layer316formed in the deposition chamber can be reduced.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the oxide insulating layer316is formed.

Next, second heat treatment (preferably 200° C. to 400° C. inclusive, for example, from 250° C. to 350° C. inclusive) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour. With the second heat treatment, heat is applied while part of the oxide semiconductor layer (a channel formation region) is in contact with the oxide insulating layer316.

Through the above steps, the oxide semiconductor layer has a lower resistance, that is, comes to be n-type when heat treatment for dehydration or dehydrogenation is performed on the formed oxide semiconductor layer. Then, the oxide insulating layer is formed in contact with the oxide semiconductor layer. Accordingly, part of the oxide semiconductor layer is selectively in an oxygen excess state. As a result, the channel formation region313overlapping with the gate electrode layer311becomes i-type. At that time, a high-resistance source region314awhich has higher carrier concentration than at least the channel formation region313and overlaps with the source electrode layer315aand a high-resistance drain region314bwhich has higher carrier concentration than at least the channel formation region313and overlaps with the drain electrode layer315bare formed in a self-aligned manner. Through the above steps, the thin film transistor310is formed (seeFIG. 11D).

Further, heat treatment may be performed at 100° C. to 200° C. inclusive for one hour to 30 hours inclusive in the air. In this embodiment, heat treatment is performed at 150° C. for 10 hours. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100° C. to 200° C. inclusive and then decreased to a room temperature. Further, this heat treatment may be performed under a reduced pressure before formation of the oxide insulating layer. Under a reduced pressure, the heating time can be shortened. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer; thus, the thin film transistor can be normally off. Therefore, reliability of the thin film transistor can be improved. When a silicon oxide layer having a lot of defects is used as the oxide insulating layer, with this heat treatment, an impurity such as hydrogen, moisture, a hydroxyl group, or hydride contained in the oxide semiconductor layer can be diffused to the oxide insulating layer so that the impurity in the oxide semiconductor layer can be further reduced.

Note that by forming the high-resistance drain region314b(and the high-resistance source region314a) in the oxide semiconductor layer overlapping with the drain electrode layer315b(and the source electrode layer315a), reliability of the thin film transistor can be improved. Specifically, by forming the high-resistance drain region314b, the structure can be obtained in which conductivities of the drain electrode layer315b, the high-resistance drain region314b, and the channel formation region313vary in a stepwise fashion. Therefore, in the case where the thin film transistor operates with the drain electrode layer315bconnected to a wiring for supplying a high power supply potential VDD, the high-resistance drain region serves as a buffer and an electric field is not applied locally even if a high voltage is applied between the gate electrode layer311and the drain electrode layer315b; thus, the withstand voltage of the thin film transistor can be increased.

Further, the high-resistance source region or the high-resistance drain region in the oxide semiconductor layer is formed in the entire thickness direction in the case where the thickness of the oxide semiconductor layer is 15 nm or smaller. In the case where the thickness of the oxide semiconductor layer is 30 nm or larger and 50 nm or smaller, in part of the oxide semiconductor layer, that is, in a region in the oxide semiconductor layer, which is in contact with the source electrode layer or the drain electrode layer, and the vicinity thereof, resistance is reduced and the high-resistance source region or the high-resistance drain region is formed, while a region in the oxide semiconductor layer, which is close to the gate insulating film, can be made to be i-type.

A protective insulating layer may be additionally formed over the oxide insulating layer316. For example, a silicon nitride layer is formed with an RF sputtering method. An RF sputtering method is preferable as a formation method of the protective insulating layer because of high productivity. The protective insulating layer is formed using an inorganic insulating layer which does not contain impurities such as moisture, a hydrogen ion, and OH−and blocks entry of these from the outside: for example, a silicon nitride layer, an aluminum nitride layer, a silicon nitride oxide layer, an aluminum nitride oxide layer, or the like is used. In this embodiment, as the protective insulating layer, a protective insulating layer303is formed using a silicon nitride layer (seeFIG. 11E).

In this embodiment, the substrate300over which layers up to the oxide insulating layer316have been formed is heated to a temperature of 100° C. to 400° C., a sputtering gas from which hydrogen and moisture are removed and which contains high-purity nitrogen is introduced, and a silicon target is used, whereby a silicon nitride layer is formed as the protective insulating layer303. In this case, the protective insulating layer303is preferably formed while removing moisture remaining in a treatment chamber, similarly to the oxide insulating layer316.

Although not illustrated, a planarization insulating layer for planarization may be provided over the protective insulating layer303.

The logic circuits in Embodiments 1 and 2 including the above-described thin film transistors can have stable electric characteristics and high reliability.

In this embodiment, an example of thin film transistors included in the logic circuit in Embodiment 1 or Embodiment 2 is described.

One embodiment of a thin film transistor and a manufacturing method of the thin film transistor of this embodiment is described with reference toFIGS. 12A to 12D.

FIG. 12Dillustrates an example of a cross-sectional structure of a thin film transistor. A thin film transistor360illustrated inFIG. 12Dis one of bottom gate thin film transistors, which is called a channel protective thin film transistor (also referred to as a channel-stop thin film transistor), and is also referred to as an inverted staggered thin film transistor.

Although description is given using a single-gate thin film transistor as the thin film transistor360, a multi-gate thin film transistor including a plurality of channel formation regions may be formed as needed.

A process of manufacturing the thin film transistor360over a substrate320is described below with reference toFIGS. 12A to 12D.

First, after a conductive layer is formed over the substrate320having an insulating surface, the gate electrode layer361is formed in a first photolithography process. Note that a resist mask may be formed with an inkjet method. When the resist mask is formed with an inkjet method, a photomask is not used; therefore, manufacturing costs can be reduced.

Further, the gate electrode layer361can be formed with a single-layer structure or a layered structure using any of metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, and an alloy material including any of these materials as a main component.

Then, the gate insulating layer322is formed over the gate electrode layer361.

In this embodiment, a silicon oxynitride layer having a thickness of smaller than or equal to 100 nm is formed as the gate insulating layer322with a plasma CVD method.

Then, an oxide semiconductor layer is formed to a thickness of 2 nm to 200 nm inclusive over the gate insulating layer322and processed into an island-shaped oxide semiconductor layer in a second photolithography process. In this embodiment, the oxide semiconductor layer is formed with a sputtering method with the use of an In—Ga—Zn—O-based metal oxide target.

In that case, the oxide semiconductor layer is preferably formed while removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor layer.

In order to remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), and the like are evacuated, whereby the concentration of an impurity in the oxide semiconductor layer formed in the deposition chamber can be reduced.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the oxide semiconductor layer is formed.

Next, the oxide semiconductor layer is subjected to dehydration or dehydrogenation. The temperature of first heat treatment for dehydration or dehydrogenation is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450° C. for one hour, and then, the oxide semiconductor layer is not exposed to the air so that entry of water and hydrogen into the oxide semiconductor layer is prevented; thus, an oxide semiconductor layer332is obtained (seeFIG. 12A).

Next, plasma treatment with a gas such as N2O, N2, or Ar is performed. With this plasma treatment, water adsorbed to a surface of an exposed portion of the oxide semiconductor layer is removed. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

Next, after an oxide insulating layer is formed over the gate insulating layer322and the oxide semiconductor layer332, a resist mask is formed in a third photolithography process. Selective etching is performed, so that the oxide insulating layer366is formed. Then, the resist mask is removed.

In this embodiment, a silicon oxide layer is formed to a thickness of 200 nm as the oxide insulating layer366with a sputtering method. The substrate temperature in film formation may be higher than or equal to room temperature and lower than or equal to 300° C. and in this embodiment, is 100° C. The silicon oxide layer can be formed with a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically, argon) and oxygen. Further, a silicon oxide target or a silicon target can be used as a target. For example, the silicon oxide layer can be formed using a silicon target with a sputtering method in an atmosphere containing oxygen and nitrogen.

In that case, the oxide insulating layer366is preferably formed while removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor layer332and the oxide insulating layer366.

In order to remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), and the like are evacuated, whereby the concentration of an impurity in the oxide insulating layer366formed in the deposition chamber can be reduced.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the oxide insulating layer366is formed.

Next, second heat treatment (preferably 200° C. to 400° C. inclusive, for example, from 250° C. to 350° C. inclusive) may be performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour. With the second heat treatment, heat is applied while part of the oxide semiconductor layer (a channel formation region) is in contact with the oxide insulating layer366.

In this embodiment, heat treatment is further performed on the oxide semiconductor layer332over which the oxide insulating layers366is provided and thus part of the oxide semiconductor layer332is exposed, in a nitrogen atmosphere, an inert gas atmosphere or under reduced pressure. By performing heat treatment in a nitrogen atmosphere, an inert gas atmosphere or under reduced pressure, the resistance of regions of the oxide semiconductor layers332, which are not covered with the oxide insulating layer366and are thus exposed, can be increased. For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour.

With the heat treatment for the oxide semiconductor layer332provided with the oxide insulating layer366in a nitrogen atmosphere, the resistance of the exposed regions of the oxide semiconductor layer332is decreased. Thus, an oxide semiconductor layer362including regions with different resistances (indicated as shaded regions and white regions inFIG. 12B) are formed.

Next, after a conductive layer is formed over the gate insulating layer322, the oxide semiconductor layer362, and the oxide insulating layer366, a resist mask is formed in a fourth photolithography process. Selective etching is performed, so that a source electrode layer365aand a drain electrode layer365bare formed. Then, the resist mask is removed (seeFIG. 12C).

As the material of the source electrode layer365aand the drain electrode layer365b, there are an element selected from Al, Cr, Cu, Ta, Ti, Mo, or W; an alloy layer containing a combination of any of these elements; and the like. The metal conductive layer may have a single-layer structure or a layered structure of two or more layers.

Through the above steps, the oxide semiconductor layer comes to be in an oxygen-deficient state, accordingly the resistance thereof is reduced, that is, comes to be n-type when heat treatment for dehydration or dehydrogenation is performed on the formed oxide semiconductor layer. Then, the oxide insulating layer is formed in contact with the oxide semiconductor layer. Accordingly, part of the oxide semiconductor layer is selectively in an oxygen excess state. As a result, the channel formation region363overlapping with the gate electrode layer361becomes i-type. At that time, a high-resistance source region364awhich has higher carrier concentration than at least the channel formation region363and overlaps with the source electrode layer365aand a high-resistance drain region364bwhich has higher carrier concentration than at least the channel formation region363and overlaps with the drain electrode layer365bare formed in a self-aligned manner. Through the above steps, the thin film transistor360is formed.

Further, heat treatment may be performed at 100° C. to 200° C. inclusive for one hour to 30 hours inclusive in the air. In this embodiment, heat treatment is performed at 150° C. for 10 hours. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100° C. to 200° C. inclusive and then decreased to a room temperature. Further, this heat treatment may be performed under a reduced pressure before formation of the oxide insulating layer. Under a reduced pressure, the heating time can be shortened. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer; thus, the thin film transistor can be normally off. Therefore, reliability of the thin film transistor can be improved.

Note that by forming the high-resistance drain region364b(and the high-resistance source region364a) in the oxide semiconductor layer overlapping with the drain electrode layer365b(and the source electrode layer365a), reliability of the thin film transistor can be improved. Specifically, by forming the high-resistance drain region364b, the structure can be obtained in which conductivities of the drain electrode layer365b, the high-resistance drain region364b, and the channel formation region363vary in a stepwise fashion. Therefore, in the case where the thin film transistor operates with the drain electrode layer365bconnected to a wiring for supplying a high power supply potential VDD, the high-resistance drain region serves as a buffer and an electric field is not applied locally even if a high voltage is applied between the gate electrode layer361and the drain electrode layer365b; thus, the withstand voltage of the thin film transistor can be increased.

A protective insulating layer323is formed over the source electrode layer365a, the drain electrode layer365b, and the oxide insulating layer366. In this embodiment, the protective insulating layer323is formed using a silicon nitride layer (seeFIG. 12D).

Note that an oxide insulating layer may be further formed over the source electrode layer365a, the drain electrode layer365b, and the oxide insulating layer366, and the protective insulating layer323may be stacked over the oxide insulating layer.

The logic circuits in Embodiments 1 and 2 including the above-described thin film transistors can have stable electric characteristics and high reliability.

In this embodiment, an example of thin film transistors included in the logic circuit in Embodiment 1 or Embodiment 2 is described.

One embodiment of a thin film transistor and a manufacturing method of the thin film transistor of this embodiment is described with reference toFIGS. 13A to 13D.

Although description is given using a single-gate thin film transistor as the thin film transistor350inFIG. 13D, a multi-gate thin film transistor including a plurality of channel formation regions may be formed as needed.

A process of manufacturing the thin film transistor350over a substrate340is described below with reference toFIGS. 13A to 13D.

First, after a conductive layer is formed over the substrate340having an insulating surface, a gate electrode layer351is formed in a first photolithography process. In this embodiment, a tungsten layer is formed as the gate electrode layer351to a thickness of 150 nm.

Then, a gate insulating layer342is formed over the gate electrode layer351. In this embodiment, a silicon oxynitride layer is formed as the gate insulating layer342to a thickness of smaller than or equal to 100 nm with a plasma CVD method.

Next, after a conductive layer is formed over the gate insulating layer342, a resist mask is formed in a second photolithography process. Selective etching is performed, so that a source electrode layer355aand a drain electrode layer355bare formed. Then, the resist mask is removed (seeFIG. 13A).

Then, an oxide semiconductor layer345is formed (seeFIG. 13B). In this embodiment, the oxide semiconductor layer345is formed with a sputtering method with the use of an In—Ga—Zn—O-based metal oxide target. The oxide semiconductor layer345is processed into an island-shaped oxide semiconductor layer in a third photolithography process.

In that case, the oxide semiconductor layer345is preferably formed while removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor layer345.

In order to remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), and the like are evacuated, whereby the concentration of an impurity in the oxide semiconductor layer345formed in the deposition chamber can be reduced.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the oxide semiconductor layer345is formed.

Next, the oxide semiconductor layer is subjected to dehydration or dehydrogenation. The temperature of first heat treatment for dehydration or dehydrogenation is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450° C. for one hour, and then, the oxide semiconductor layer is not exposed to the air so that entry of water and hydrogen into the oxide semiconductor layer is prevented; thus, an oxide semiconductor layer346is obtained (seeFIG. 13C).

As the first heat treatment, GRTA may be performed as follows. The substrate is transferred and put in an inert gas which has been heated to a high temperature of 650° C. to 700° C., heated for several minutes, and transferred and taken out of the inert gas which has been heated to a high temperature. GRTA enables high-temperature heat treatment in a short time.

An oxide insulating layer356which serves as a protective insulating layer and is in contact with the oxide semiconductor layer346is formed.

The oxide insulating layer356can be formed to a thickness of longer than or equal to 1 nm with a sputtering method or the like as appropriate, which is a method with which an impurity such as water or hydrogen does not enter the oxide insulating layer356. When hydrogen is contained in the oxide insulating layer356, entry of the hydrogen to the oxide semiconductor layer or extraction of oxygen in the oxide semiconductor layer by the hydrogen is caused, whereby a backchannel of the oxide semiconductor layer comes to have a lower resistance (to be n-type) and thus a parasitic channel might be formed. Therefore, it is important that a formation method in which hydrogen is not used is employed so that the oxide insulating layer356is formed containing as little hydrogen as possible.

In this embodiment, a silicon oxide layer is formed to a thickness of 200 nm as the oxide insulating layer356with a sputtering method. The substrate temperature in film formation may be higher than or equal to room temperature and lower than or equal to 300° C. and in this embodiment, is 100° C. The silicon oxide layer can be formed with a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically, argon) and oxygen. Further, a silicon oxide target or a silicon target can be used as a target. For example, the silicon oxide layer can be formed using a silicon target with a sputtering method in an atmosphere containing oxygen and nitrogen. The oxide insulating layer356which is formed in contact with the oxide semiconductor layer in a region which is in an oxygen-deficient state and thus has a lower resistance is formed using an inorganic insulating layer that does not contain impurities such as moisture, a hydrogen ion, and OH−and blocks entry of such impurities from the outside, typically, a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer.

In that case, the oxide insulating layer356is preferably formed while removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor layer346and the oxide insulating layer356.

In order to remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), and the like are evacuated, whereby the concentration of an impurity in the oxide insulating layer356formed in the deposition chamber can be reduced.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the oxide insulating layer356is formed.

Next, second heat treatment (preferably 200° C. to 400° C. inclusive, for example, from 250° C. to 350° C. inclusive) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour. With the second heat treatment, heat is applied while part of the oxide semiconductor layer (a channel formation region) is in contact with the oxide insulating layer356.

Through the above steps, the oxide semiconductor layer which is in an oxygen-deficient state and thus has a lower resistance through dehydration or dehydrogenation is brought into an oxygen-excess state. As a result, an i-type oxide semiconductor layer352having a high resistance is formed. Through the above steps, the thin film transistor350is formed.

Further, heat treatment may be performed at 100° C. to 200° C. inclusive for one hour to 30 hours inclusive in the air. In this embodiment, heat treatment is performed at 150° C. for 10 hours. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100° C. to 200° C. inclusive and then decreased to a room temperature. Further, this heat treatment may be performed under a reduced pressure. Under a reduced pressure, the heating time can be shortened. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer; thus, the thin film transistor can be normally off. Therefore, reliability of the semiconductor device can be improved.

A protective insulating layer343may be additionally formed over the oxide insulating layer356. For example, a silicon nitride layer is formed with an RF sputtering method. In this embodiment, as the protective insulating layer, the protective insulating layer343is formed using a silicon nitride layer (seeFIG. 13D).

Note that a planarization insulating layer for planarization may be provided over the protective insulating layer343.

The logic circuits in Embodiments 1 and 2 including the above-described thin film transistors can have stable electric characteristics and high reliability

In this embodiment, an example of thin film transistors included in the logic circuit in Embodiment 1 or Embodiment 2 is described.

In this embodiment, an example which is partly different from Embodiment 7 in the manufacturing process of a thin film transistor will be described with reference toFIG. 14. SinceFIG. 14is the same asFIGS. 11A to 11Eexcept for part of the steps, common reference numerals are used for the same portions, and detailed description of the same portions is omitted.

First, a gate electrode layer381is formed over a substrate370, and a first gate insulating layer372aand a second gate insulating layer372bare stacked thereover in accordance with Embodiment 7. In this embodiment, a gate insulating layer has a two layer structure in which a nitride insulating layer and an oxide insulating layer are used as the first gate insulating layer372aand the second gate insulating layer372b, respectively.

As the oxide insulating layer, a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, an aluminum oxynitride layer, or the like may be used. As the nitride insulating layer, a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, an aluminum nitride oxide layer, or the like may be used.

In this embodiment, the gate insulating layer may have a structure where a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer381side. A silicon nitride layer (SiNy(y>0)) with a thickness of 50 nm to 200 nm inclusive (50 nm in this embodiment) is formed with a sputtering method as a first gate insulating layer372aand a silicon oxide layer (SiOx(x>0)) with a thickness of 5 nm to 300 nm inclusive (100 nm in this embodiment) is stacked as a second gate insulating layer372bover the first gate insulating layer372a; thus, the gate insulating layer is formed.

Next, the oxide semiconductor layer is formed and then processed into an island-shaped oxide semiconductor layer in a photolithography process. In this embodiment, the oxide semiconductor layer is formed with a sputtering method with the use of an In—Ga—Zn—O-based metal oxide target.

In that case, the oxide semiconductor layer is preferably formed while removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor layer.

In order to remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), and the like are evacuated, whereby the concentration of an impurity in the oxide semiconductor layer formed in the deposition chamber can be reduced.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the oxide semiconductor layer is formed.

Next, the oxide semiconductor layer is subjected to dehydration or dehydrogenation. The temperature of first heat treatment for dehydration or dehydrogenation is higher than or equal to 400° C. and lower than or equal to 750° C., preferably higher than or equal to 425° C. Note that in the case of the temperature that is 425° C. or more, the heat treatment time may be one hour or less, whereas in the case of the temperature less than 425° C., the heat treatment time is longer than one hour. Here, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere, and then, the oxide semiconductor layer is not exposed to the air so that entry of water and hydrogen into the oxide semiconductor layer is prevented. Thus, the oxide semiconductor layer is obtained. After that, a high-purity oxygen gas, a high-purity N2O gas, or an ultra-dry air (with a dew point of −40° C. or less, preferably −60° C. or less) is introduced into the same furnace and cooling is performed. It is preferable that water, hydrogen, and the like be not contained in the oxygen gas or the N2O gas. Alternatively, the purity of the oxygen gas or the N2O gas which is introduced into the heat treatment apparatus is preferably 6N (99.9999%) or more, more preferably 7N (99.99999%) or more (i.e., the impurity concentration of the oxygen gas or the N2O gas is preferably 1 ppm or lower, more preferably 0.1 ppm or lower).

Note that the heat treatment apparatus is not limited to the electric furnace, and for example, may be an RTA (rapid thermal annealing) apparatus such as a GRTA (gas rapid thermal annealing) apparatus or an LRTA (lamp rapid thermal annealing) apparatus. An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. An LRTA apparatus may be provided with not only a lamp but also a device for heating an object to be processed by heat conduction or heat radiation from a heater such as a resistance heater. GRTA is a method for performing heat treatment using a high-temperature gas. As the gas, an inert gas which does not react with an object to be processed with heat treatment, such as nitrogen or a rare gas such as argon is used. Alternatively, the heat treatment may be performed at 600° C. to 750° C. for several minutes by an RTA method.

Moreover, after the first heat treatment for dehydration or dehydrogenation, heat treatment may be performed at from 200° C. to 400° C. inclusive, preferably from 200° C. to 300° C. inclusive, in an oxygen gas atmosphere or a N2O gas atmosphere.

The first heat treatment of the oxide semiconductor layer may be performed before processing the oxide semiconductor layer into the island-like oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography step is performed.

Through the above process, an entire region of the oxide semiconductor layer is made to be in an oxygen excess state; thus, the oxide semiconductor layer has higher resistance, that is, the oxide semiconductor layer becomes i-type. Accordingly, an oxide semiconductor layer382whose entire region is i-type is obtained.

Next, a conductive layer is formed over the oxide semiconductor layer382. A resist mask is formed in a photolithography process. Etching is performed selectively, whereby a source electrode layer385aand a drain electrode layer385bare formed. Then, an oxide insulating layer386is formed with a sputtering method.

In that case, the oxide insulating layer386is preferably formed while removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor layer382and the oxide insulating layer386.

In order to remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used. For example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used. Further, an evacuation unit may be a turbo pump provided with a cold trap. In the deposition chamber which is evacuated with the cryopump, a hydrogen atom, a compound containing a hydrogen atom, such as water (H2O), and the like are evacuated, whereby the concentration of an impurity in the oxide insulating layer386formed in the deposition chamber can be reduced.

It is preferable to use a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration expressed by a level of ppm or ppb, as a sputtering gas used when the oxide insulating layer386is formed.

Through the above steps, a thin film transistor380can be formed.

Next, in order to reduce variation in electric characteristics of the thin film transistors, heat treatment (preferably at 150° C. or higher and lower than 350° C.) may be performed in an inert gas atmosphere or a nitrogen gas atmosphere. For example, the heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour.

Further, heat treatment may be performed at 100° C. to 200° C. inclusive for one hour to 30 hours inclusive in the air. In this embodiment, heat treatment is performed at 150° C. for 10 hours. This heat treatment may be performed at a fixed heating temperature. Alternatively, the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100° C. to 200° C. inclusive and then decreased to a room temperature. Under a reduced pressure, the heating time can be shortened. With this heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer; thus, the thin film transistor can be normally off. Therefore, reliability of the thin film transistor can be improved.

A protective insulating layer373is formed over the oxide insulating layer386. In this embodiment, the protective insulating layer373is formed to a thickness of 100 nm with the use of a silicon nitride layer with a sputtering method.

The protective insulating layer373and the first gate insulating layer372aeach formed using a nitride insulating layer do not contain impurities such as moisture, hydrogen, hydride, and hydroxide and has an effect of blocking entry of these from the outside.

Therefore, in a manufacturing process after formation of the protective insulating layer373, entry of an impurity such as moisture from the outside can be prevented. Further, even after a device is completed as a semiconductor device such as a liquid crystal display device, entry of an impurity such as moisture from the outside can be prevented in the long term; therefore, long-term reliability of the device can be achieved.

Further, part of the insulating layers between the protective insulating layer373formed using a nitride insulating layer and the first gate insulating layer372amay be removed so that the protective insulating layer373and the first gate insulating layer372aare in contact with each other.

Accordingly, impurities such as moisture, hydrogen, hydride, and hydroxide in the oxide semiconductor layer are reduced as much as possible and entry of such impurities is prevented, so that the concentration of impurities in the oxide semiconductor layer can be maintained to be low.

Although not illustrated, a planarization insulating layer for planarization may be provided over the protective insulating layer373.

The logic circuits in Embodiments 1 and 2 including the above-described thin film transistors can have stable electric characteristics and high reliability

In this embodiment, examples of semiconductor devices each including the logic circuit in Embodiment 1 or Embodiment 2 are described. Specifically, appearances and a cross section of liquid crystal display panels in each of which a driver circuit includes the logic circuit in Embodiment 1 or Embodiment 2 are described with reference toFIGS. 15A to 15C.FIGS. 15A and 15Care plan views of panels in each of which thin film transistors4010and4011and a liquid crystal element4013are sealed between a first substrate4001and a second substrate4006with a sealant4005.FIG. 15Bis a cross-sectional view taken along a line M-N inFIG. 15Aor15C.

The sealant4005is provided so as to surround a pixel portion4002and a scan line driver circuit4004which are provided over the first substrate4001. The second substrate4006is provided over the pixel portion4002and the scan line driver circuit4004. Consequently, the pixel portion4002and the scan line driver circuit4004are sealed together with a liquid crystal layer4008, by the first substrate4001, the sealant4005, and the second substrate4006. A signal line driver circuit4003that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared is mounted in a region that is different from the region surrounded by the sealant4005over the first substrate4001.

Note that there is no particular limitation on the connection method of the driver circuit which is separately formed, and a COG method, a wire bonding method, a TAB method, or the like can be used.FIG. 15Aillustrates an example in which the signal line driver circuit4003is mounted by a COG method.FIG. 15Cillustrates an example in which the signal line driver circuit4003is mounted by a TAB method.

The pixel portion4002and the scan line driver circuit4004provided over the first substrate4001include a plurality of thin film transistors.FIG. 15Billustrates the thin film transistor4010included in the pixel portion4002and the thin film transistor4011included in the scan line driver circuit4004, as an example. Insulating layers4041,4042, and4021are provided over the thin film transistors4010and4011.

Any of the thin film transistors of Embodiments 3 to 10 can be used as appropriate as the thin film transistors4010and4011, and they can be formed using steps and materials similar to those for the thin film transistors of Embodiments 3 to 10. Hydrogen or water is reduced in the oxide semiconductor layers of the thin film transistors4010and4011. Thus, the thin film transistors4010and4011are highly reliable thin film transistors. In this embodiment, the thin film transistors4010and4011are n-channel thin film transistors.

A conductive layer4040is provided over part of the insulating layer4021, which overlaps with a channel formation region of an oxide semiconductor layer in the thin film transistor4011. The conductive layer4040is provided in the position overlapping with the channel formation region of the oxide semiconductor layer, whereby the amount of change in threshold voltage of the thin film transistor4011before and after the BT test can be reduced. A potential of the conductive layer4040may be the same or different from that of a gate electrode layer of the thin film transistor4011. The conductive layer4040can also function as a second gate electrode layer. Further, the potential of the conductive layer4040may be GND, 0 V, or the conductive layer4040may be in a floating state. Note that the conductive layer4040is not necessarily provided.

A pixel electrode layer4030included in the liquid crystal element4013is electrically connected to a source or drain electrode layer of the thin film transistor4010. A counter electrode layer4031of the liquid crystal element4013is formed on the second substrate4006. A portion where the pixel electrode layer4030, the counter electrode layer4031, and the liquid crystal layer4008overlap with one another corresponds to the liquid crystal element4013. Note that the pixel electrode layer4030and the counter electrode layer4031are provided with an insulating layer4032and an insulating layer4033functioning as alignment films, respectively, and the liquid crystal layer4008is sandwiched between the electrode layers with the insulating layers4032and4033therebetween.

Note that a light-transmitting substrate can be used as the first substrate4001and the second substrate4006; glass, ceramics, or plastics can be used. The plastic may be a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film.

Reference numeral4035denotes a columnar spacer obtained by selective etching of an insulating film, and the columnar spacer is provided in order to control the distance (a cell gap) between the pixel electrode layer4030and the counter electrode layer4031. Alternatively, a spherical spacer may be used as the spacer4035. The counter electrode layer4031is electrically connected to a common potential line formed over the substrate where the thin film transistor4010is formed. The counter electrode layer4031and the common potential line can be electrically connected to each other through conductive particles provided between the pair of substrates using the common connection portion. Note that the conductive particles are included in the sealant4005.

Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while the temperature of cholesteric liquid crystal is increased. Since the blue phase is only generated within a narrow temperature range, a liquid crystal composition containing a chiral agent at 5 wt % or more is used for the liquid crystal layer4008in order to improve the temperature range. The liquid crystal composition including liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less and is optically isotropic; therefore, alignment treatment is not necessary and viewing angle dependence is small. In addition, since an alignment film does not need to be provided and rubbing treatment is unnecessary, electrostatic breakdown caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device can be reduced in the manufacturing process. Thus, productivity of the liquid crystal display device can be increased. A thin film transistor formed using an oxide semiconductor layer particularly has a possibility that electric characteristics of the thin film transistor may fluctuate significantly by the influence of static electricity and deviate from the designed range. Therefore, it is more effective to use a blue phase liquid crystal material for a liquid crystal display device including a thin film transistor formed using an oxide semiconductor layer.

Note that this embodiment can also be applied to a transflective liquid crystal display device in addition to a transmissive liquid crystal display device.

Although a polarizing plate is provided on the outer surface of the substrate (on the viewer side) and a coloring layer and an electrode layer used for a display element are sequentially provided on the inner surface of the substrate in the example of the liquid crystal display device, the polarizing plate may be provided on the inner surface of the substrate. The stacked structure of the polarizing plate and the coloring layer is not limited to that in this embodiment and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of the manufacturing process. Further, a light-blocking film serving as a black matrix may be provided in a portion other than the display portion.

Over the thin film transistors4011and4010, the insulating layer4041is formed in contact with the oxide semiconductor layers. The insulating layer4041can be formed using a material and a method which are similar to those of the oxide insulating layer described in any of the embodiments. Here, as the insulating layer4041, a silicon oxide layer is formed by a sputtering method. Further, the protective insulating layer4042is formed on and in contact with the insulating layer4041. The protective insulating layer4042can be formed using a silicon nitride layer, for example. In order to reduce the surface roughness caused by the thin film transistors, the insulating layer4021serving as a planarization insulating layer is formed.

The insulating layer4021is formed as a planarization insulating layer. As the insulating layer4021, an organic material having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. Other than such organic materials, it is possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like. Note that the insulating layer4021may be formed by stacking a plurality of insulating layers formed of these materials.

There is no particular limitation on the method for forming the insulating layer4021. The insulating layer4021can be formed, depending on the material, by a method such as a sputtering method, an SOG method, a spin coating method, a dipping method, a spray coating method, or a droplet discharge method (e.g., an inkjet method, screen printing, or offset printing), or a tool (equipment) such as a doctor knife, a roll coater, a curtain coater, or a knife coater. A baking step of the insulating layer4021also serves as annealing of the semiconductor layer, whereby a semiconductor device can be manufactured efficiently.

The pixel electrode layer4030and the counter electrode layer4031can be formed using a light-transmitting conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO) in which zinc oxide (ZnO) is mixed in indium oxide, a conductive material in which silicon oxide (SiO2) is mixed in indium oxide, organic indium, organotin, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like. Further, in the case where a light-transmitting property is not needed or a reflecting property is needed in a reflective liquid crystal display device, the pixel electrode layer4030and the counter electrode layer4031can be formed using one or more kinds of materials selected from a metal such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag); an alloy of these metals; and a nitride of these metals.

A conductive composition containing a conductive high molecule (also referred to as a conductive polymer) can be used for the pixel electrode layer4030and the counter electrode layer4031. The pixel electrode formed using the conductive composition preferably has a sheet resistance of less than or equal to 10000 ohms per square and a transmittance of greater than or equal to 70% at a wavelength of 550 nm Further, the resistivity of the conductive high molecule contained in the conductive composition is preferably less than or equal to 0.1 Ω·cm.

As the conductive high molecule, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more kinds of them, and the like can be given.

Further, a variety of signals and potentials are supplied to the signal line driver circuit4003which is formed separately, the scan line driver circuit4004, or the pixel portion4002from an FPC4018.

A connection terminal electrode4015is formed using the same conductive film as the pixel electrode layer4030included in the liquid crystal element4013, and a terminal electrode4016is formed using the same conductive film as source and drain electrode layers of the thin film transistors4010and4011.

The connection terminal electrode4015is electrically connected to a terminal included in the FPC4018through an anisotropic conductive film4019.

Note thatFIGS. 15A to 15Cillustrate examples in each of which the signal line driver circuit4003is formed separately and mounted on the first substrate4001; however, the present invention is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

A black matrix (a light-blocking layer), an optical member (an optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member, and the like are provided as appropriate. For example, circular polarization may be employed by using a polarizing substrate and a retardation substrate. In addition, a backlight, a sidelight, or the like may be used as a light source.

In an active matrix liquid crystal display device, display patterns are formed on a screen by driving of pixel electrodes that are arranged in matrix. Specifically, voltage is applied between a selected pixel electrode and a counter electrode corresponding to the pixel electrode, and thus, a liquid crystal layer disposed between the pixel electrode and the counter electrode is optically modulated. This optical modulation is recognized as a display pattern by a viewer.

A liquid crystal display device has a problem in that, when displaying a moving image, image sticking occurs or the moving image is blurred because the response speed of liquid crystal molecules themselves is low. As a technique for improving moving image characteristics of a liquid crystal display device, there is a driving technique so-called black insertion by which an entirely black image is displayed every other frame.

Alternatively, a driving method called double-frame rate driving may be employed in which a vertical synchronizing frequency is 1.5 times or more, preferably 2 times or more as high as a normal vertical synchronizing frequency, whereby response speed is improved.

Furthermore, as a technique for improving moving image characteristics of a liquid crystal display device, there is another driving technique in which, as a backlight, a surface light source including a plurality of LED (light-emitting diode) light sources or a plurality of EL light sources is used, and each light source included in the surface light source is independently driven so as to perform intermittent lighting in one frame period. As the surface light source, three or more kinds of LEDs may be used, or a white-light-emitting LED may be used. Since a plurality of LEDs can be controlled independently, the timing at which the LEDs emit light can be synchronized with the timing at which optical modulation of a liquid crystal layer is switched. In this driving technique, part of LEDs can be turned off. Therefore, especially in the case of displaying an image in which the proportion of a black image area in one screen is high, a liquid crystal display device can be driven with low power consumption.

When combined with any of these driving techniques, a liquid crystal display device can have better display characteristics such as moving image characteristics than conventional liquid crystal display devices.

Since the thin film transistor is easily broken due to static electricity or the like, the protective circuit is preferably provided over the same substrate as the pixel portion and the driver circuit portion. The protective circuit is preferably formed using a non-linear element including an oxide semiconductor layer. For example, a protective circuit is provided between the pixel portion, and a scan line input terminal and a signal line input terminal. In this embodiment, a plurality of protective circuits are provided so that the pixel transistor and the like are not broken when surge voltage due to static electricity or the like is applied to the scan line, the signal line, or a capacitor bus line. Accordingly, the protective circuit has a structure for releasing electric charge to a common wiring when surge voltage is applied to the protective circuit. The protective circuit includes non-linear elements which are arranged in parallel with the scan line. Each of the non-linear elements includes a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, the non-linear element can be formed through the same steps as the thin film transistor of the pixel portion. For example, characteristics similar to those of a diode can be achieved by connecting a gate terminal to a drain terminal.

There is no particular limitation in the semiconductor device disclosed in this specification, and a liquid crystal display device including a TN liquid crystal, an OCB liquid crystal, an STN liquid crystal, a VA liquid crystal, an ECB liquid crystal, a GH liquid crystal, a polymer dispersed liquid crystal, a discotic liquid crystal, or the like can be used. In particular, a normally black liquid crystal panel such as a transmissive liquid crystal display device utilizing a vertical alignment (VA) mode is preferable. Some examples are given as a vertical alignment mode. For example, an MVA (multi-domain vertical alignment) mode, a PVA (patterned vertical alignment) mode, an ASV mode, or the like can be employed.

Further, this embodiment can also be applied to a VA liquid crystal display device. The VA liquid crystal display device has a kind of form in which alignment of liquid crystal molecules in a liquid crystal display panel is controlled. In the VA liquid crystal display device, liquid crystal molecules are aligned in a vertical direction with respect to a panel surface when no voltage is applied. Further, a method called multi-domain or multi-domain design, by which a pixel is divided into some regions (subpixels), and liquid crystal molecules are aligned in different directions in their respective regions, can be used.

In this embodiment, examples of semiconductor devices each including the logic circuit in Embodiment 1 or Embodiment 2 are described. Specifically, examples of manufacturing active-matrix light-emitting display devices in each of which a driver circuit includes the logic circuit in Embodiment 1 or Embodiment 2 are described. Note that in this embodiment, examples of light-emitting display devices including light-emitting elements utilizing electroluminescence will be described.

Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. Then, the carriers (electrons and holes) recombine, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.

FIG. 16illustrates an example of a pixel structure to which digital time grayscale driving can be applied, as an example of a semiconductor device.

A structure and operation of a pixel to which digital time grayscale driving can be applied are described. Here, one pixel includes two n-channel transistors each of which includes an oxide semiconductor layer as a channel formation region.

A pixel6400includes a switching transistor6401, a driving transistor6402, a light-emitting element6404, and a capacitor6403. A gate of the switching transistor6401is connected to a scan line6406, a first electrode (one of a source electrode and a drain electrode) of the switching transistor6401is connected to a signal line6405, and a second electrode (the other of the source electrode and the drain electrode) of the switching transistor6401is connected to a gate of the driving transistor6402. The gate of the driving transistor6402is connected to a power supply line6407through the capacitor6403, a first electrode of the driving transistor6402is connected to the power supply line6407, and a second electrode of the driving transistor6402is connected to a first electrode (pixel electrode) of the light-emitting element6404. A second electrode of the light-emitting element6404corresponds to a common electrode. The common electrode is electrically connected to a common potential line6408provided over the same substrate as the common electrode.

The second electrode (common electrode) of the light-emitting element6404is set to a low power supply potential. Note that the low power supply potential is a potential satisfying the low power supply potential <a high power supply potential with reference to the high power supply potential that is set to the power supply line6407. As the low power supply potential, GND, 0 V, or the like may be employed, for example. A potential difference between the high power supply potential and the low power supply potential is applied to the light-emitting element6404and current is supplied to the light-emitting element6404, so that the light-emitting element6404emits light. Here, in order to make the light-emitting element6404emit light, each potential is set so that the potential difference between the high power supply potential and the low power supply potential is higher than a forward voltage drop of the light-emitting element6404.

When the gate capacitance of the driving transistor6402is used as a substitute for the capacitor6403, the capacitor6403can be omitted. The gate capacitance of the driving transistor6402may be formed between a channel formation region and a gate electrode.

Here, in the case of using a voltage-input voltage driving method, a video signal to enable the driving transistor6402to completely turn on or off, is input to the gate of the driving transistor6402. That is, the driving transistor6402operates in a linear region. Since the driving transistor6402operates in a linear region, voltage higher than the voltage of the power supply line6407is applied to the gate of the driving transistor6402. Note that a voltage greater than or equal to (power supply line voltage+Vthof the driving transistor6402) is applied to the signal line6405.

Further, in the case of using analog grayscale driving instead of the digital time ratio grayscale driving, the pixel structure the same as that ofFIG. 16can be employed by inputting signals in a different way.

In the case of using the analog grayscale method, a voltage greater than or equal to forward voltage of the light-emitting element6404+Vthof the driving transistor6402is applied to the gate of the driving transistor6402. The forward voltage of the light-emitting element6404indicates voltage at which a desired luminance is obtained. By inputting a video signal to enable the driving transistor6402to operate in a saturation region, current can be supplied to the light-emitting element6404. In order that the driving transistor6402can operate in the saturation region, the potential of the power supply line6407is made higher than a gate potential of the driving transistor6402. When an analog video signal is used, it is possible to feed current to the light-emitting element6404in accordance with the video signal and perform analog grayscale driving.

Note that the pixel structure illustrated inFIG. 16is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added to the pixel shown inFIG. 16.

Next, structures of the light-emitting element will be described with reference toFIGS. 17A to 17C. Here, a cross-sectional structure of a pixel will be described by taking an n-channel driving TFT as an example. Driving TFTs7011,7021, and7001used for semiconductor devices illustrated inFIGS. 17A,17B, and17C can be manufactured in a manner similar to that of the thin film transistor described in any of the embodiments and are thin film transistors each including an oxide semiconductor layer, as examples.

In order to extract light emission from the light-emitting element, at least one of an anode and a cathode is required to be transparent. A thin film transistor and a light-emitting element are formed over a substrate. The light-emitting element can have a top emission structure in which light emission is extracted through a surface opposite to the substrate; a bottom emission structure in which light emission is extracted through a surface on the substrate side; or a dual emission structure in which light emission is extracted through the surface opposite to the substrate and the surface on the substrate side. The pixel structure can be applied to a light-emitting element having any of these emission structures.

Next, a light-emitting element having a bottom emission structure is described with reference toFIG. 17A.

FIG. 17Ais a cross-sectional view of a pixel of the case where a driving TFT7011is of an n-type and light is emitted from a light-emitting element7012to a first electrode7013side. InFIG. 17A, the first electrode7013of the light-emitting element7012is formed over a light-transmitting conductive layer7017which is electrically connected to a drain electrode layer of the driving TFT7011, and an EL layer7014and a second electrode7015are stacked in the order presented, over the first electrode7013.

As the light-transmitting conductive layer7017, a light-transmitting conductive layer of indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like can be used.

A variety of materials can be used for the first electrode7013of the light-emitting element. For example, in the case where the first electrode7013is used as a cathode, the first electrode7013is preferably formed using, for example, a material having a low work function such as an alkali metal such as Li or Cs; an alkaline earth metal such as Mg, Ca, or Sr; an alloy containing any of these metals (e.g., Mg:Ag or Al:Li); or a rare earth metal such as Yb or Er. InFIG. 17A, the first electrode7013is approximately formed to a thickness such that light is transmitted (preferably, approximately 5 nm to 30 nm). For example, an aluminum layer having a thickness of 20 nm is used for the first electrode7013.

Note that the light-transmitting conductive layer7017and the first electrode7013may be formed by stacking a light-transmitting conductive layer and an aluminum layer and then performing selective etching. In this case, the etching can be performed using the same mask, which is preferable.

Further, the periphery of the first electrode7013is covered with a partition wall7019. The partition wall7019is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like; an inorganic insulating film; or organic polysiloxane. It is particularly preferable that the partition wall7019be formed using a photosensitive resin material to have an opening over the first electrode7013so that a sidewall of the opening is formed to have an inclined surface with continuous curvature. In the case where a photosensitive resin material is used for the partition wall7019, a step of forming a resist mask can be omitted.

As the EL layer7014formed over the first electrode7013and the partition wall7019, an EL layer including at least a light-emitting layer is acceptable. Further, the EL layer7014may be formed to have either a single-layer structure or a stacked-layer structure. When the EL layer7014is formed using a plurality of layers, an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer are stacked in the order presented over the first electrode7013functioning as a cathode. Note that not all of these layers need to be provided except for the light-emitting layer.

The stacking order is not limited to the order presented above. The first electrode7013may serve as an anode, and a hole-injection layer, a hole-transport layer, a light-emitting layer, an electron-transport layer, and an electron-injection layer may be stacked in the order presented over the first electrode7013. However, considering power consumption, it is preferable that the first electrode7013serve as a cathode and an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer be stacked in the order presented over the first electrode7013because an increase in voltage of a driver circuit portion can be prevented and power consumption can be reduced more effectively than in the case of using the first electrode7013as the anode.

Further, any of a variety of materials can be used for the second electrode7015formed over the EL layer7014. For example, in the case where the second electrode7015is used as an anode, a material having a high work function, for example, ZrN, Ti, W, Ni, Pt, Cr, or the like; or a transparent conductive material such as ITO, IZO, or ZnO is preferable. Further, a shielding film7016, for example, a metal which blocks light, a metal which reflects light, or the like is provided over the second electrode7015. In this embodiment, an ITO film is used as the second electrode7015, and a Ti layer is used as the shielding film7016.

The light-emitting element7012corresponds to a region where the EL layer7014including the light-emitting layer is sandwiched between the first electrode7013and the second electrode7015. In the case of the element structure illustrated inFIG. 17A, light emitted from the light-emitting element7012is ejected to the first electrode7013side as indicated by an arrow.

Note that in the example illustrated inFIG. 17A, a light-transmitting conductive layer is used as a gate electrode layer and a thin light-transmitting film is used as source and drain electrode layers. Light emitted from the light-emitting element7012passes through a color filter layer7033, and can be ejected through the substrate.

The color filter layer7033is formed by a droplet discharge method such as an inkjet method, a printing method, an etching method with the use of a photolithography technique, or the like.

The color filter layer7033is covered with the overcoat layer7034, and also covered with the protective insulating layer7035. Note that although the overcoat layer7034with a small thickness is illustrated inFIG. 17A, the overcoat layer7034has a function to planarize roughness due to the color filter layer7033.

A contact hole which is formed in a planarization insulating layer7036, the insulating layer7032, and the insulating layer7031, and which reaches the drain electrode layer is provided in a portion which overlaps with the partition wall7019.

A light-emitting element having a dual emission structure is described with reference toFIG. 17B.

InFIG. 17B, a first electrode7023of a light-emitting element7022is formed over a light-transmitting conductive layer7027which is electrically connected to a drain electrode layer of the driving TFT7021, and an EL layer7024and a second electrode7025are stacked in the order presented over the first electrode7023.

As the light-transmitting conductive layer7027, a light-transmitting conductive layer of indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like can be used.

A variety of materials can be used for the first electrode7023. For example, in the case where the first electrode7023is used as a cathode, the first electrode7023is preferably formed using, for example, a material having a low work function such as an alkali metal such as Li or Cs; an alkaline earth metal such as Mg, Ca, or Sr; an alloy containing any of these metals (e.g., Mg:Ag or Al:Li); or a rare earth metal such as Yb or Er. In this embodiment, the first electrode7023is used as a cathode, and the first electrode7023is approximately formed to a thickness such that light is transmitted (preferably, approximately 5 nm to 30 nm). For example, an aluminum layer having a thickness of 20 nm is used as the cathode.

Note that the light-transmitting conductive layer7027and the first electrode7023may be formed by stacking the light-transmitting conductive layer and the aluminum layer and then performing selective etching. In this case, the etching can be performed using the same mask, which is preferable.

Further, the periphery of the first electrode7023is covered with a partition wall7029. The partition wall7029is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like; an inorganic insulating film; or organic polysiloxane. It is particularly preferable that the partition wall7029be formed using a photosensitive resin material to have an opening over the first electrode7023so that a sidewall of the opening is formed to have an inclined surface with continuous curvature. In the case where a photosensitive resin material is used for the partition wall7029, a step of forming a resist mask can be omitted.

As the EL layer7024formed over the first electrode7023and the partition wall7029, an EL layer including a light-emitting layer is acceptable. Further, the EL layer7024may be formed to have either a single-layer structure or a stacked-layer structure. When the EL layer7024is formed using a plurality of layers, an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer are stacked in the order presented over the first electrode7023functioning as a cathode. Note that not all of these layers need to be provided except for the light-emitting layer.

The stacking order is not limited to the order presented above. The first electrode7023may serve as an anode and a hole-injection layer, a hole-transport layer, a light-emitting layer, an electron-transport layer, and an electron-injection layer may be stacked in the order presented over the first electrode7023. However, considering power consumption, it is preferable that the first electrode7023is used as a cathode and an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer be stacked in the order presented over the cathode because power consumption can be reduced more effectively than in the case of using the first electrode7023as the anode.

Further, a variety of materials can be used for the second electrode7025formed over the EL layer7024. For example, in the case where the second electrode7025is used as an anode, a material having a high work function, for example, a transparent conductive material such as ITO, IZO, or ZnO is preferable. In this embodiment, the second electrode7025is formed using an ITO layer including silicon oxide and is used as an anode.

The light-emitting element7022corresponds to a region where the EL layer7024including the light-emitting layer is sandwiched between the first electrode7023and the second electrode7025. In the case of the element structure illustrated in FIG.17B, light emitted from the light-emitting element7022is ejected to both the second electrode7025side and the first electrode7023side as indicated by arrows.

Note that in the example illustrated inFIG. 17B, a light-transmitting conductive layer is used as a gate electrode layer and a thin light-transmitting film is used as source and drain electrode layers. Light emitted from the light-emitting element7022to the first electrode7023side passes through a color filter layer7043, and can be ejected through the substrate.

The color filter layer7043is formed by a droplet discharge method such as an inkjet method, a printing method, an etching method with the use of a photolithography technique, or the like.

The color filter layer7043is covered with the overcoat layer7044, and also covered with the protective insulating layer7045.

A contact hole which is formed in a planarization insulating layer7046, the insulating layer7042, and the insulating layer7041, and which reaches the drain electrode layer is provided in a portion which overlaps with the partition wall7029.

Note that in the case where full-color display is realized on both display surfaces by using a light-emitting element having a dual emission structure, light emitted from the second electrode7025side does not pass through the color filter layer7043; therefore, it is preferable that a sealing substrate having a color filter layer be further provided over the second electrode7025.

Next, a light-emitting element having a top emission structure is described with reference toFIG. 17C.

FIG. 17Cis a cross-sectional view of a pixel of the case where a driving TFT7001is of an n-type and light emitted from a light-emitting element7002passes through a second electrode7005. InFIG. 17C, a drain electrode layer of the driving TFT7001and a first electrode7003are in contact with each other, and the driving TFT7001and the first electrode7003of the light-emitting element7002are electrically connected to each other. An EL layer7004and the second electrode7005are stacked over the first electrode7003in the order presented.

Further, a variety of materials can be used for the first electrode7003. For example, in the case where the first electrode7003is used as a cathode, the first electrode7003is preferably formed using a material having a low work function such as an alkali metal such as Li or Cs; an alkaline earth metal such as Mg, Ca, or Sr; an alloy containing any of these metals (e.g., Mg:Ag or Al:Li); or a rare earth metal such as Yb or Er.

Further, the periphery of the first electrode7003is covered with a partition wall7009. The partition wall7009is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like; an inorganic insulating film; or organic polysiloxane. It is particularly preferable that the partition wall7009be formed using a photosensitive resin material to have an opening over the first electrode7003so that a sidewall of the opening is formed to have an inclined surface with continuous curvature. In the case where a photosensitive resin material is used for the partition wall7009, a step of forming a resist mask can be omitted.

As the EL layer7004formed over the first electrode7003and the partition wall7009, an EL layer including at least a light-emitting layer is acceptable. Further, the EL layer7004may be formed to have either a single-layer structure or a stacked-layer structure. When the EL layer7004is formed using a plurality of layers, an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer are stacked in the order presented over the first electrode7003used as a cathode. Note that not all of these layers need to be provided except for the light-emitting layer.

The stacking order is not limited to the order presented above, and a hole-injection layer, a hole-transport layer, a light-emitting layer, an electron-transport layer, and an electron-injection layer may be stacked in the order presented over the first electrode7003used as an anode.

InFIG. 17C, a hole-injection layer, a hole-transport layer, a light-emitting layer, an electron-transport layer, and an electron-injection layer are stacked in the order presented over a stacked-layer film in which a Ti layer, an aluminum layer, and a Ti layer are stacked in the order presented, and thereover, a stacked layer of a thin Mg:Ag alloy film and ITO is formed.

However, in the case where the driving TFT7001is of an n-type, it is preferable that an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer be stacked in the order presented over the first electrode7003because an increase in voltage of a driver circuit can be prevented and power consumption can be reduced more effectively than in the case of using the layers stacked in the above order.

The second electrode7005is formed using a light-transmitting conductive material. For example, a light-transmitting conductive layer of indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added, or the like can be used.

The light-emitting element7002corresponds to a region where the EL layer7004including the light-emitting layer is sandwiched between the first electrode7003and the second electrode7005. In the case of the pixel illustrated inFIG. 17C, light emitted from the light-emitting element7002is ejected to the second electrode7005side as indicated by an arrow.

InFIG. 17C, the drain electrode layer of the driving TFT7001is electrically connected to the first electrode7003through a contact hole formed in a silicon oxide layer7051, a protective insulating layer7052, a planarization insulating layer7056, a planarization insulating layer7053, and an insulating layer7055. The planarization insulating layers7036,7046,7053, and7056can be formed using a resin material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. Other than such resin materials, it is also possible to use a low-dielectric constant material (low-k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. Note that the planarization insulating layers7036,7046,7053, and7056may be formed by stacking a plurality of insulating layers formed using these materials. The planarization insulating layers7036,7046,7053, and7056can be formed, depending on the material, with a method such as a sputtering method, an SOG method, a spin coating method, a dipping method, a spray coating method, or a droplet discharge method (e.g., an inkjet method, screen printing, or offset printing), or a tool (equipment) such as a doctor knife, a roll coater, a curtain coater, or a knife coater.

The partition wall7009is provided in order to insulate the first electrode7003from a first electrode of an adjacent pixel. The partition wall7009is formed using an organic resin film of polyimide, acrylic, polyamide, epoxy, or the like; an inorganic insulating film; or organic polysiloxane. It is particularly preferable that the partition wall7009be formed using a photosensitive resin material to have an opening over the first electrode7003so that a sidewall of the opening is formed as an inclined surface with continuous curvature. In the case where a photosensitive resin material is used for the partition wall7009, a step of forming a resist mask can be omitted.

In the structure illustrated inFIG. 17C, for performing full-color display, the light-emitting element7002, one of adjacent light-emitting elements, and the other of the adjacent light-emitting elements are, for example, a green emissive light-emitting element, a red emissive light-emitting element, and a blue emissive light-emitting element, respectively. Alternatively, a light-emitting display device capable of full color display may be manufactured using four kinds of light-emitting elements which include a white light-emitting element in addition to three kinds of light-emitting elements.

In the structure ofFIG. 17C, a light-emitting display device capable of full color display may be manufactured in such a way that all of a plurality of light-emitting elements which is arranged is white light-emitting elements and a sealing substrate having a color filter or the like is arranged over the light-emitting element7002. A material which exhibits a single color such as white is formed and combined with a color filter or a color conversion layer, whereby full color display can be performed.

Any of the thin film transistors of the embodiments can be used as appropriate as the driving TFTs7001,7011, and7021used for semiconductor devices, and they can be formed using steps and materials similar to those for the TFTs of the embodiments. Hydrogen or water is reduced in the oxide semiconductor layers of the driving TFTs7001,7011, and7021. Thus, the driving TFTs7001,7011, and7021are highly reliable thin film transistors.

Needless to say, display of monochromatic light can also be performed. For example, a lighting system may be formed with the use of white light emission, or an area-color light-emitting device may be formed with the use of a single color light emission.

If necessary, an optical film such as a polarizing film including a circularly polarizing plate may be provided.

Note that, although the organic EL elements are described here as the light-emitting elements, an inorganic EL element can also be provided as a light-emitting element.

Note that the example is described in which a thin film transistor (a driving TFT) which controls the driving of a light-emitting element is electrically connected to the light-emitting element; however, a structure may be employed in which a TFT for current control is connected between the driving TFT and the light-emitting element.

FIGS. 18A and 18Billustrate an appearance and a cross section of a light-emitting display panel (also referred to as a light-emitting panel).FIG. 18Ais a plan view of a panel in which a thin film transistor and a light-emitting element that are formed over a first substrate are sealed between the first substrate and a second substrate with a sealant.FIG. 18Bis a cross-sectional view taken along a line H-I inFIG. 18A.

A sealant4505is provided to surround a pixel portion4502, signal line driver circuits4503aand4503b, and scan line driver circuits4504aand4504bwhich are provided over a first substrate4501. In addition, a second substrate4506is provided over the pixel portion4502, the signal line driver circuits4503aand4503b, and the scan line driver circuits4504aand4504b. Accordingly, the pixel portion4502, the signal line driver circuits4503aand4503b, and the scan line driver circuits4504aand4504bare sealed together with a filler4507, by the first substrate4501, the sealant4505, and the second substrate4506. It is preferable that a panel be packaged (sealed) with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the panel is not exposed to the outside air, in this manner.

The pixel portion4502, the signal line driver circuits4503aand4503b, and the scan line driver circuits4504aand4504b, which are formed over the first substrate4501, each include a plurality of thin film transistors. A thin film transistor4510included in the pixel portion4502and a thin film transistor4509included in the signal line driver circuit4503aare illustrated as an example inFIG. 18B.

Any of the thin film transistors of the embodiments can be used as appropriate as the thin film transistors4509and4510, and they can be formed using steps and materials similar to those for the thin film transistors of the embodiments. Hydrogen or water is reduced in the oxide semiconductor layers of the thin film transistors4509and4510. Thus, the thin film transistors4509and4510are highly reliable thin film transistors.

A conductive layer is provided over a portion overlapping with the channel formation region of the oxide semiconductor layer in the thin film transistor4509. In this embodiment, the thin film transistors4509and4510are n-channel thin film transistors.

The conductive layer4540is provided over part of an oxide silicon layer4542, which overlaps with the channel formation region of the oxide semiconductor layer in the thin film transistor4509. The conductive layer4540is provided at the position overlapping with the channel formation region of the oxide semiconductor layer, whereby the amount of change in threshold voltage of the thin film transistor4509before and after the BT test can be reduced. A potential of the conductive layer4540may be the same or different from that of a gate electrode layer in the thin film transistor4509. The conductive layer4540can also function as a second gate electrode layer. Alternatively, the potential of the conductive layer4540may be GND, 0 V, or the conductive layer4540may be in a floating state.

Further, the silicon oxide layer4542is formed to cover the oxide semiconductor layer of the thin film transistor4510. The source or drain electrode layer of the thin film transistor4510is electrically connected to a wiring layer4550in an opening formed in the silicon oxide layer4542and an insulating layer4551which are formed over the thin film transistor. The wiring layer4550is formed in contact with a first electrode4517, and the thin film transistor4510is electrically connected to the first electrode4517through the wiring layer4550.

A color filter layer4545is formed over the insulating layer4551so as to overlap with a light-emitting region of a light-emitting element4511.

Further, in order to reduce the surface roughness of the color filter layer4545, the color filter layer4545is covered with an overcoat layer4543functioning as a planarization insulating film.

An insulating layer4544is formed over the overcoat layer4543. As the insulating layer4544, a silicon nitride layer may be formed by a sputtering method, for example.

Reference numeral4511denotes a light-emitting element. The first electrode4517which is a pixel electrode included in the light-emitting element4511is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor4510, through the wiring layer4550. Note that the light-emitting element4511has a stacked-layer structure of the first electrode4517, an electroluminescent layer4512, and a second electrode4513, and there is no particular limitation on the structure. The structure of the light-emitting element4511can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element4511, or the like.

A partition wall4520is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition wall4520be formed using a photosensitive material to have an opening portion over the first electrode4517so that a sidewall of the opening portion is formed as a tilted surface with continuous curvature.

The electroluminescent layer4512may be formed to have either a single-layer structure or a stacked-layer structure.

In order to prevent entry of oxygen, hydrogen, moisture, carbon dioxide, or the like into the light-emitting element4511, a protective layer may be formed over the second electrode4513and the partition wall4520. As the protective layer, a silicon nitride layer, a silicon nitride oxide layer, a DLC layer, or the like can be formed.

In addition, a variety of signals and potentials are supplied to the signal line driver circuits4503aand4503b, the scan line driver circuits4504aand4504b, or the pixel portion4502from FPCs4518aand4518b.

A connection terminal electrode4515is formed using the same conductive layer as the first electrode4517included in the light-emitting element4511, and a terminal electrode4516is formed using the same conductive layer as the source and drain electrode layers included in the thin film transistor4509.

The connection terminal electrode4515is electrically connected to a terminal included in the FPC4518athrough an anisotropic conductive layer4519.

The second substrate located in the direction in which light is extracted from the light-emitting element4511should have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used for the second substrate4506.

As the filler4507, an ultraviolet curable resin or a thermosetting resin can be used, as well as an inert gas such as nitrogen or argon. For example, PVC (polyvinyl chloride), acrylic, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen is used for the filler.

The sealant can be formed using a screen printing method, an inkjet apparatus, or a dispensing apparatus. As the sealant, typically, a material containing a visible light curable resin, an ultraviolet curable resin, or a thermosetting resin can be used. Further, a filler may be contained.

As the signal line driver circuits4503aand4503band the scan line driver circuits4504aand4504b, driver circuits formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared may be used and mounted. Alternatively, only the signal line driver circuits or a part thereof, or only the scan line driver circuits or a part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated inFIGS. 18A and 18B.

Through the above process, a highly reliable light-emitting display device (display panel) as a semiconductor device can be manufactured.

In this embodiment, an example of a semiconductor device including the logic circuit in Embodiment 1 or Embodiment 2 is described. Specifically, an example of electronic paper in which a driver circuit includes the logic circuit in Embodiment 1 or Embodiment 2 is described.

FIG. 19is a cross-sectional view illustrating active matrix electronic paper. Any of the thin film transistors of the embodiments can be used as appropriate as a thin film transistor581used for electronic paper, and it can be formed using steps and materials similar to those for the thin film transistors of the embodiments. In this embodiment, the thin film transistor described in Embodiment 6 is used as the thin film transistor581, for example. Hydrogen or water is reduced in the oxide semiconductor layer of the thin film transistor581. Thus, the thin film transistor581is a highly reliable thin film transistor.

The electronic paper inFIG. 19is an example of a display device using a twisting ball display system. The twisting ball display system refers to a system in which spherical particles each colored in black and white are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and a potential difference is generated between the first electrode layer and the second electrode layer to control orientation of the spherical particles, so that display is performed.

The thin film transistor581formed over a substrate580has a bottom-gate structure in which source and drain electrode layers are electrically connected to a first electrode layer587through an opening formed in a silicon oxide layer583, a protective insulating layer584and an insulating layer585.

Between the first electrode layer587and the second electrode layer588, spherical particles are provided. Each spherical particle includes a black region590aand a white region590b, and a cavity594filled with liquid around the black region590aand the white region590b. The circumference of the spherical particle is filled with a filler595such as a resin (seeFIG. 19). In this embodiment, the first electrode layer587corresponds to a pixel electrode and the second electrode layer588provided on a counter substrate596corresponds to a common electrode.

Further, instead of the twisting ball, an electrophoretic element can also be used. A microcapsule having a diameter of about 10 μm to 200 μm in which transparent liquid, positively or negatively charged white microparticles, and black microparticles charged with the polarity opposite to that of the white microparticles are encapsulated, is used. In the microcapsule provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white microparticles and the black microparticles move in opposite directions to each other, so that white or black can be displayed. A display element using this principle is an electrophoretic display element, and is called electronic paper in general. The electrophoretic display element has higher reflectance than a liquid crystal display element, and thus, an auxiliary light is unnecessary, power consumption is low, and a display portion can be recognized in a dim place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which may be referred to simply as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source.

The electronic paper of this embodiment is a reflective display device, in which display is performed by controlling voltage applied to the twisting ball with a driver circuit.

In this embodiment, examples of semiconductor devices each including the logic circuit in Embodiment 1 or Embodiment 2 are described. Specifically, examples of electronic devices (including an amusement machine in its category) in which a driver circuit includes the logic circuit in Embodiment 1 or Embodiment 2 are described. Examples of electronic devices include a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone device), a portable game machine, a portable information terminal, an audio reproducing device, a large game machine such as a pinball machine, and the like.

FIG. 20Aillustrates an example of a mobile phone. A mobile phone1600is provided with a display portion1602incorporated in a housing1601, operation buttons1603aand1603b, an external connection port1604, a speaker1605, a microphone1606, and the like.

When the display portion1602of the mobile phone1600illustrated inFIG. 20Ais touched with a finger or the like, data can be input into the mobile phone1600. Further, operations such as making a call and composing a mail can be performed by touching the display portion1602with a finger or the like.

There are mainly three screen modes of the display portion1602. The first mode is a display mode mainly for displaying an image. The second mode is an input mode mainly for inputting data such as text. The third mode is a display-and-input mode in which two modes of the display mode and the input mode are combined.

For example, in the case of making a call or composing a mail, a text input mode mainly for inputting text is selected for the display portion1602so that text displayed on a screen can be input. In this case, it is preferable to display a keyboard or number buttons on almost all area of the screen of the display portion1602.

When a detection device including a sensor for detecting inclination, such as a gyroscope or an acceleration sensor, is provided inside the mobile phone1600, display of the screen on the display portion1602can be automatically switched by determining the direction of the mobile phone1600(whether the mobile phone1600is placed horizontally or vertically for a landscape mode or a portrait mode).

The screen modes are switched by touching the display portion1602or operating the operation buttons1603aand1603bof the housing1601. Alternatively, the screen modes may be switched depending on the kind of the image displayed on the display portion1602. For example, when a signal for an image displayed in the display portion is data of moving images, the screen mode is switched to the display mode. When the signal is text data, the screen mode is switched to the input mode.

Further, in the input mode, when input by touching the display portion1602is not performed for a certain period while a signal detected by the optical sensor in the display portion1602is detected, the screen mode may be controlled so as to be switched from the input mode to the display mode.

The display portion1602may function as an image sensor. For example, an image of the palm print, the fingerprint, or the like is taken by touching the display portion1602with the palm or the finger, whereby personal authentication can be performed. Further, by providing a backlight or sensing light source emitting a near-infrared light for the display portion, an image of a finger vein, a palm vein, or the like can be taken.

Any of the semiconductor devices described in the embodiments can be applied to the display portion1602. For example, a plurality of thin film transistors described in the embodiments can be disposed as switching elements in pixels.

FIG. 20Balso illustrates an example of a mobile phone. A portable information terminal whose example is illustrated inFIG. 20Bcan have a plurality of functions. For example, in addition to a telephone function, such a portable information terminal can have a function of processing a variety of pieces of data by incorporating a computer.

The portable information terminal illustrated inFIG. 20Bhas a housing1800and a housing1801. The housing1801includes a display panel1802, a speaker1803, a microphone1804, a pointing device1806, a camera lens1807, an external connection terminal1808, and the like. The housing1800includes a keyboard1810, an external memory slot1811, and the like. In addition, an antenna is incorporated in the housing1801.

The display panel1802is provided with a touch panel. A plurality of operation keys1805displayed as images is indicated by dashed lines inFIG. 20B.

Further, in addition to the above structure, a contactless IC chip, a small memory device, or the like may be incorporated.

In the display panel1802, the direction of display is changed appropriately depending on an application mode. Further, the portable information terminal is provided with the camera lens1807on the same surface as the display panel1802, and thus it can be used as a video phone. The speaker1803and the microphone1804can be used for videophone calls, recording, playing sound, etc. as well as voice calls. Moreover, the housings1800and1801in a state where they are developed as illustrated inFIG. 20Bcan be slid so that one is lapped over the other; therefore, the size of the portable information terminal can be reduced, which makes the portable information terminal suitable for being carried.

The external connection terminal1808can be connected to an AC adapter and various types of cables such as a USB cable, and charging and data communication with a personal computer are possible. Moreover, a storage medium can be inserted into the external memory slot1811so that a large amount of data can be stored and can be moved.

Further, in addition to the above functions, an infrared communication function, a television reception function, or the like may be provided.

FIG. 21Aillustrates an example of a television set. In a television set9600, a display portion9603is incorporated in a housing9601. The display portion9603can display images. Here, the housing9601is supported by a stand9605.

The television set9600can be operated with an operation switch of the housing9601or a separate remote controller9610. Channels can be switched and volume can be controlled with operation keys9609of the remote controller9610, whereby an image displayed on the display portion9603can be controlled. Moreover, the remote controller9610may be provided with a display portion9607for displaying data outputted from the remote controller9610.

In the display portion9603, the plurality of thin film transistors described in any of the embodiments can be provided as switching elements of pixels.

FIG. 21Billustrates an example of a digital photo frame. For example, in a digital photo frame9700, a display portion9703is incorporated in a housing9701. The display portion9703can display a variety of images. For example, the display portion9703can display data of an image taken with a digital camera or the like and function as a normal photo frame.

In the display portion9703, the plurality of thin film transistors described in any of the embodiments can be provided as switching elements of pixels.

Note that the digital photo frame9700is provided with an operation portion, an external connection terminal (a USB terminal, a terminal connectable to a variety of cables such as a USB cable, or the like), a recording medium insertion portion, and the like. Although these components may be provided on the same surface as the display portion, it is preferable to provide them on the side surface or the back surface for design aesthetics. For example, a memory storing data of an image taken with a digital camera is inserted in the recording medium insertion portion of the digital photo frame and the data is loaded, whereby the image can be displayed on the display portion9703.

The digital photo frame9700may be configured to transmit and receive data wirelessly. Through wireless communication, desired image data can be loaded to be displayed.

FIG. 22is a portable game machine and is constituted by two housings of a housing9881and a housing9891which are connected with a joint portion9893so that the portable game machine can be opened or folded. A display portion9882and a display portion9883are incorporated in the housing9881and the housing9891, respectively.

In the display portion9883, the plurality of thin film transistors described in any of the embodiments can be provided as switching elements of pixels.

In addition, the portable game machine illustrated inFIG. 22is provided with a speaker portion9884, a recording medium insertion portion9886, an LED lamp9890, input means (operation keys9885, a connection terminal9887, a sensor9888(having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radial ray, flow rate, humidity, gradient, vibration, smell, or infrared ray), and a microphone9889), and the like. Needless to say, the structure of the portable game machine is not limited to the above and other structures provided with at least the thin film transistor disclosed in this specification can be employed. The portable game machine may include an additional accessory as appropriate. The portable game machine illustrated inFIG. 22has a function of reading a program or data stored in the recording medium to display it on the display portion, and a function of sharing data with another portable game machine by wireless communication. Note that a function of the portable game machine illustrated inFIG. 22is not limited to these, and the portable game machine can have a variety of functions.

As described above, the logic circuit in Embodiment 1 or Embodiment 2 can be applied to display panels of various electronic devices and thus, electronic devices having high reliability can be provided.

In this embodiment, an example of a semiconductor device including the logic circuit in Embodiment 1 or Embodiment 2 is described. Specifically, an electronic paper in which a driver circuit includes the logic circuit in Embodiment 1 or Embodiment 2 can be used in electronic devices in all fields as long as they display information. For example, electronic paper can be applied to an e-book reader (an electronic book), a poster, an advertisement in a vehicle such as a train, or displays of various cards such as a credit card. An example of such electronic devices is illustrated inFIG. 23.

FIG. 23illustrates an example of an e-book reader. For example, an e-book reader2700includes two housings of a housing2701and a housing2703. The housing2701and the housing2703are combined with a hinge2711so that the e-book reader2700can be opened and closed with the hinge2711as an axis. Such a structure enables the e-book reader2700to operate like a paper book.

A display portion2705and a display portion2707are incorporated in the housing2701and the housing2703, respectively. The display portion2705and the display portion2707may display one image or different images. In the case where the display portion2705and the display portion2707display different images, for example, a display portion on the right side (the display portion2705inFIG. 23) can display text and a display portion on the left side (the display portion2707inFIG. 23) can display graphics.

FIG. 23illustrates an example in which the housing2701is provided with an operation portion and the like. For example, the housing2701is provided with a power switch2721, an operation key2723, a speaker2725, and the like. With the operation key2723, pages can be turned. Note that a keyboard, a pointing device, or the like may also be provided on the surface of the housing, on which the display portion is provided. Furthermore, an external connection terminal (an earphone terminal, a USB terminal, a terminal that can be connected to various cables such as an AC adapter and a USB cable, or the like), a recording medium insertion portion, and the like may be provided on the back surface or the side surface of the housing. Moreover, the e-book reader2700may have a function of an electronic dictionary.

The e-book reader2700may have a configuration capable of wirelessly transmitting and receiving data. Through wireless communication, desired book data or the like can be purchased and downloaded from an electronic book server.

In accordance with an embodiment of the present invention, impurities to be suppliers of carriers (donors or acceptors) in an oxide semiconductor are reduced to a very low level, whereby an intrinsic or substantially intrinsic oxide semiconductor is formed, and the oxide semiconductor is used for a thin film transistor.

FIG. 24is a band structure of a portion between a source and a drain of such a transistor. For a highly purified oxide semiconductor, the Fermi level is located in the middle of the forbidden band under an ideal condition.

In this case, at a junction surface, the Fermi level of metal for an electrode is the same as the level of the conduction band of an oxide semiconductor if the equation φm=χ is satisfied, where φmis a work function and χ is an electron affinity of the oxide semiconductor. When the right side of the equation is greater than the left side, an ohmic contact is provided. It is assumed that an oxide semiconductor has a band gap of 3.15 eV and an electron affinity of 4.3 eV and is in an intrinsic state (the carrier density: approximately 1×10−7/cm3), and a source electrode and a drain electrode are formed using titanium (Ti) having a work function of 4.3 eV. Under these conditions, a Shottky barrier with respect to electrons is not formed as illustrated inFIG. 24.

FIG. 25illustrates a state where positive voltage is applied to the drain side in a transistor formed using an oxide semiconductor. Since the band gap of an oxide semiconductor is wide, the intrinsic carrier density of a highly purified oxide semiconductor which is intrinsic or substantially intrinsic is zero or as close as zero. However, when voltage is applied between a source and a drain, carriers (electrons) might be injected from the source side and flow into the drain side.

FIG. 26Ais an energy band diagram of a MOS transistor formed using an oxide semiconductor, to which a positive gate voltage is applied. In this case, almost no thermally excited carriers exist in a highly purified oxide semiconductor. Thus, carriers are not accumulated even in the vicinity of a gate insulating film. However, as illustrated inFIG. 25, transmission of carriers (electrons) injected from the source side is possible.

FIG. 26Bis an energy band diagram of a MOS transistor formed using an oxide semiconductor, to which a negative gate voltage is applied. There are almost no minority carriers (holes) in an oxide semiconductor; therefore, carriers are not accumulated even in the vicinity of a gate insulating film. This means that off-state current is small.

FIG. 27is a band diagram of a transistor formed using a silicon semiconductor. For a silicon semiconductor, the band gap is 1.12 eV and the intrinsic carrier density is 1.45×1010/cm3(300 K). The thermally excited carriers are not negligible even at room temperatures. Thus, off-state current is greatly varied depending on a temperature.

In such a manner, not only by simply using an oxide semiconductor with a wide band gap for a transistor, but also by reducing impurities to be donors, such as hydrogen, and thus setting the carrier density to 1×1014/cm3or less, preferably 1×1012/cm3or less, thermally excited carriers at practical operation temperatures can be removed, so that a transistor can be operated by only carriers injected from the source side. Accordingly, it is possible to obtain a transistor whose off-state current is reduced to 1×10−13[A] or less and is hardly changed due to temperature change, whereby the transistor can be operated in an extremely stable manner.

In this embodiment, measured values of off-state current using a test element group (also referred to as a TEG) will be described below.

FIG. 28shows initial characteristics of a thin film transistor with effectively L/W=3 μm/10000 μm, in which 200 thin film transistors each with L/W=3 μm/50 μm are connected in parallel. In addition, a top view is shown inFIG. 29Aand a partially enlarged top view thereof is show inFIG. 29B. The region enclosed by a dotted line inFIG. 29Bis a thin film transistor of one stage with L/W=3 μm/50 μm and Lov=1.5 μm. In order to measure initial characteristics of the thin film transistor, the transfer characteristics of the source-drain current (hereinafter referred to as a drain current or Id), i.e., Vg-Id characteristics, were measured, under the conditions where the substrate temperature was set to room temperature, the voltage between source and drain (hereinafter, a drain voltage or Vd) was set to 10 V, and the voltage between source and gate (hereinafter, a gate voltage or Vg) was changed from −20 V to +20 V. Note thatFIG. 28shows Vg in the range of from −20 V to +5 V.

As shown inFIG. 28, the thin film transistor having a channel width W of 10000 μm has an off-state current of 1×10−13A or less at Vd of 1 V and 10 V, which is less than or equal to the resolution (100 fA) of a measurement device (a semiconductor parameter analyzer, Agilent 4156C manufactured by Agilent Technologies Inc.).

A method for manufacturing the thin film transistor used for the measurement is described.

First, a silicon nitride layer was formed as a base layer over a glass substrate by a CVD method, and a silicon oxynitride layer was formed over the silicon nitride layer. A tungsten layer was formed as a gate electrode layer over the silicon oxynitride layer by a sputtering method. Here, the gate electrode layer was formed by selectively etching the tungsten layer.

Then, a silicon oxynitride layer having a thickness of 100 nm was formed as a gate insulating layer over the gate electrode layer by a CVD method.

Then, an oxide semiconductor layer having a thickness of 50 nm was formed over the gate insulating layer by a sputtering method using an In—Ga—Zn—O-based metal oxide target (at a molar ratio of In2O3:Ga2O3:ZnO=1:1:2). Here, an island-shaped oxide semiconductor layer was formed by selectively etching the oxide semiconductor layer.

Then, first heat treatment was performed on the oxide semiconductor layer in a nitrogen atmosphere in a clean oven at 450° C. for 1 hour.

Then, a titanium layer (having a thickness of 150 nm) was formed as a source electrode layer and a drain electrode layer over the oxide semiconductor layer by a sputtering method. Here, the source electrode layer and the drain electrode layer were formed by selective etching such that 200 thin film transistors each having a channel length L of 3 μm and a channel width W of 50 μm were connected in parallel to obtain a thin film transistor effectively with L/W=3 μm/10000 μm.

Then, a silicon oxide layer having a thickness of 300 nm was formed as a protective insulating layer in contact with the oxide semiconductor layer by a reactive sputtering method. Here, opening portions were formed over the gate electrode layer, the source electrode layer, and the drain electrode layer by selectively etching the silicon oxide layer which is a protective layer. After that, second heat treatment was performed in a nitrogen atmosphere at 250° C. for 1 hour.

Then, heat treatment was performed at 150° C. for 10 hours before the measurement of Vg-Id characteristics.

Through the above process, a bottom-gate thin film transistor was manufactured.

The reason why the thin film transistor has an off-state current of approximately 1×10−13A as shown inFIG. 28is that the concentration of hydrogen in the oxide semiconductor layer could be sufficiently reduced in the above manufacturing process. The concentration of hydrogen in the oxide semiconductor layer is 5×1019/cm3or less, preferably 5×1018/cm3or less, still preferably 5×1017/cm3or less. Note that the concentration of hydrogen in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS).

Although the example of using an In—Ga—Zn—O-based oxide semiconductor is described, this embodiment is not particularly limited thereto. Another oxide semiconductor material, such as an In—Sn—Zn—O-based oxide semiconductor, a Sn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxide semiconductor, a Sn—Al—Zn—O-based oxide semiconductor, an In—Zn—O-based oxide semiconductor, an In—Sn—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxide semiconductor, an In—O-based oxide semiconductor, a Sn—O-based oxide semiconductor, or a Zn—O-based oxide semiconductor, can also be used. Furthermore, as an oxide semiconductor material, an In—Al—Zn—O-based oxide semiconductor mixed with AlOxof 2.5 wt % to 10 wt % or an In—Zn—O-based oxide semiconductor mixed with SiOxof 2.5 wt % to 10 wt % can be used.

The carrier concentration of the oxide semiconductor layer which is measured by a carrier measurement device is preferably less than or equal to 1.45×1010/cm3, which is intrinsic carrier density of silicon. Specifically, the carrier concentration is 5×1014/cm3, preferably 5×1012/cm3. In other words, the carrier concentration of the oxide semiconductor layer can be made as close to zero as possible.

The thin film transistor can also have a channel length L of 10 nm to 1000 nm inclusive, which enables an increase in circuit operation speed, and the off-state current is extremely small, which enables a further reduction in power consumption.

In addition, in circuit design, the oxide semiconductor layer can be regarded as an insulator when the thin film transistor is in an off state.

After that, the temperature characteristics of off-state current of the thin film transistor manufactured in this embodiment were evaluated. Temperature characteristics are important in considering the environmental resistance, maintenance of performance, or the like of an end product in which the thin film transistor is used. It is to be understood that a smaller amount of change is more preferable, which increases the degree of freedom for product designing.

For the temperature characteristics, the Vg-Id characteristics were obtained using a constant-temperature chamber under the conditions where substrates provided with thin film transistors were kept at respective constant temperatures of −30° C., 0° C., 25° C., 40° C., 60° C., 80° C., 100° C., and 120° C., the drain voltage was set to 6 V, and the gate voltage was changed from −20 V to +20V.

FIG. 30Ashows Vg-Id characteristics measured at the above temperatures and superimposed on one another, andFIG. 30Bshows an enlarged view of a range of off-state current enclosed by a dotted line inFIG. 30A. The rightmost curve indicated by an arrow in the diagram is a curve obtained at −30° C.; the leftmost curve is a curve obtained at 120° C.; and curves obtained at the other temperatures are located therebetween. The temperature dependence of on-state currents can hardly be observed. On the other hand, as clearly shown also in the enlarged view ofFIG. 30B, the off-state currents are less than or equal to 1×10−12A, which is near the resolution of the measurement device, at all temperatures except in the vicinity of a gate voltage of −20 V, and the temperature dependence thereof is not observed. In other words, even at a high temperature of 120° C., the off-state current is kept less than or equal to 1×10−12A, and further in consideration that the effective channel width W is 10000 μm, it can be seen that the off-state current is significantly small.

A thin film transistor including a purified oxide semiconductor (purified OS) as described above shows almost no dependence of off-state current on temperature. This also results from the fact that the oxide semiconductor has an energy gap of 3 eV or more and includes very few intrinsic carriers. In addition, the source region and the drain region are in a degenerated state, which is also a factor for showing no temperature dependence. The thin film transistor is mainly operated with carriers which are injected from the degenerated source region to the oxide semiconductor, and the above characteristics (independence of off-state current on temperature) can be explained by independence of carrier density on temperature.

In the case where a memory circuit (memory element) or the like is manufactured using a thin film transistor having such an extremely small off-state current, there is very little leakage due to the small off-state current. Therefore, memory data can be held for a longer period of time.

This application is based on Japanese Patent Application serial no. 2009-238914 filed with Japan Patent Office on Oct. 16, 2009, the entire contents of which are hereby incorporated by reference.

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