TRANSISTOR COUPLED TO TERMINALS FOR INJECTING CHARGE CARRIERS INTO PAIR OF SPACERS

The disclosure provides a structure including a transistor coupled to terminals for injecting charge carriers into a pair of spacers. The structure includes a gate structure over a substrate and having a pair of spacers on opposite horizontal ends of the gate structure. A pair of source/drain (S/D) regions is within the substrate, and each S/D region is below a respective one of the pair of spacers. Each of the pair of S/D regions is coupled to one of a pair of terminals configured to inject charge carriers into either of the pair of spacers.

BACKGROUND

1. Technical Field

The present disclosure provides integrated circuit structures with a transistor coupled to terminals for injecting charge carriers into a pair of spacers, and methods for operating such structures.

2. Background Art

Non-volatile memory (NVM) devices that employ charge-trapping layers to store data have been developed. Once such NVM device is a charge-trapping sidewall spacer-type NVM (CTSS-NVM) device, which is configured similarly to a field effect transistor (FET) and employs a charge-trapping gate sidewall spacer for storing a data bit. Depending upon the biasing conditions applied to a gate structure of the device and its source/drain (S/D) regions, a charge can be forced into one charge-trapping dielectric layer of the data storage node (i.e., the CTSS-NVM device is programmed or, more particularly, stores a “one” data bit), a charge can be removed from the charge-trapping dielectric layer of the data storage node (i.e., the CTSS-NVM device is erased or, more particularly, stores a “zero” data bit), or the state of the CTSS-NVM device, as programmed or erased, can be read. Unfortunately, with technology scaling, the high voltage magnitudes needed to program and reset CTSS-NVM devices have become problematic.

SUMMARY

Embodiments of the disclosure provide a structure including: a gate structure over a substrate and having a pair of spacers on opposite horizontal ends of the gate structure; and a pair of source/drain (S/D) regions within the substrate and each below a respective one of the pair of spacers, wherein each of the pair of S/D regions is coupled to one of a pair of terminals configured to inject charge carriers into either of the pair of spacers.

Further embodiments of the disclosure provide a structure including: a substrate; a pair of source/drain (S/D) terminals within the substrate, wherein a channel region of the substrate separates the pair of S/D terminals from each other; a gate structure over the channel region of the substrate and extending horizontally between a first end and a second end; a first spacer adjacent the first end of the gate structure and over one of the pair of S/D terminals; and a second spacer adjacent the second end of the gate structure and over the other of the pair of S/D terminals; wherein each of the pair of S/D regions is coupled to a respective terminal configured to inject charge carriers into either of the pair of spacers.

Additional embodiments of the disclosure provide a method for operating a structure, the method including: applying a voltage to one of a pair of source/drain (S/D) regions of a transistor, the transistor including: a gate structure over a substrate and having a pair of spacers on opposite horizontal ends of the gate structure; and the pair of source/drain (S/D) regions within the substrate and each below a respective one of the pair of spacers, wherein the voltage injects charge carriers into one of the pair of spacers; and applying the voltage to the other of the pair of S/D regions of the transistor to inject charge carriers into the other of the pair of spacers.

DETAILED DESCRIPTION

Non-volatile memory (NVM) devices that employ charge-trapping layers to store data have been developed. Once such NVM device is a charge-trapping sidewall spacer-type NVM (CTSS-NVM) device, which is configured similarly to a field effect transistor (FET) and employs a charge-trapping gate sidewall spacer for storing a data bit. An example CTSS-NVM device may include a channel region within a semiconductor layer and positioned laterally between a first source/drain (S/D) region and a second (S/D) region. A gate structure may be on the semiconductor layer above the channel region, and first and second gate spacers may be on opposing sidewalls of the gate structure (e.g., adjacent to the first and second S/D regions, respectively). In a structure according to the disclosure, each of two S/D regions within a substrate may be located below a respective one of two spacers positioned on opposite horizontal ends of a gate structure. Each S/D region is coupled to one of two terminals configured to inject charge carriers into either of the pair of spacers, e.g., by applying the voltage to one of the two S/D regions.

Referring toFIG.1, disclosed herein are embodiments of a semiconductor structure100(simply “structure” hereafter) for providing, e.g., a charge-trapping sidewall spacer-type non-volatile memory (CTSS-NVM) transistor in which charge carriers may be injected into either or both of two spacers by electrically controlling two terminals. Structure100can include a semiconductor substrate102(e.g., a silicon substrate) including, e.g., one or more bulk semiconductor area(s) (e.g., bulk silicon area(s)) and/or one or more semiconductor-on-insulator areas (e.g., silicon-on-insulator (SOI) area(s)) adjacent to the bulk semiconductor area(s). Substrate102is illustrated as a bulk semiconductor layer, but this is not required in all implementations. Various portions of a transistor104may be formed on and within upper portions of substrate102.

Substrate102may include a channel region106, extending to a predetermined depth below its upper surface. Channel region106can be either undoped or doped so as to have a first-type conductivity at a relatively low conductivity level. Transistor104further may include a gate structure108on channel region106of substrate102. Gate structure108may include one or more gate dielectric layers110and one or more gate conductor layers112on the gate dielectric layer(s)110.

Gate dielectric layer(s)110may include, e.g., a thin silicon dioxide (SiO2) layer above and immediately adjacent to the top surface of the semiconductor substrate102and a thin high-K dielectric layer on the SiO2layer. Gate dielectric layer110may be a hafnium (Hf)-based dielectric (e.g., hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium aluminum oxide, etc.) or some other suitable high-K dielectric (e.g., aluminum oxide, tantalum oxide, zirconium oxide, etc.). Gate conductor layer(s)112can include a thin titanium nitride (TiN) layer on gate dielectric layer110, and an amorphous silicon (A-Si) layer on the TiN layer. It should be understood that gate dielectric layer110and gate conductor layer(s)112are discussed for the sake of example and are not intended to be limiting. Alternatively, any other suitable gate dielectric and conductor material layer compositions could be incorporated into gate structure108of the transistor104. Gate structure108moreover may include a set of gate spacers114horizontally adjacent gate conductor layer(s)112. Gate spacers114, where included, may include the same material and/or similar materials to those of gate dielectric layer110.

In any case, gate structure108can further have opposing sidewalls (i.e., a first sidewall E1and a second sidewall E2opposite first sidewall E1). The opposing sidewalls E1, E2of gate structure108can extend vertically away from the upper surface of semiconductor substrate102in such that they are essentially parallel to each other and essentially perpendicular to the upper surface of semiconductor substrate102. The terms “essentially parallel” and “essentially perpendicular” are used to account for processing variations that: (a) may result in sidewalls E1, E2being somewhat angled relative to the top surface of substrate102(e.g., at 90 degrees plus or minus 0-20 degrees) as opposed to exactly perpendicular; (b) may result in sidewalls E1, E2being somewhat curved as opposed to being exactly planar; and/or (c) may result in the top surface of substrate102not being exactly planar.

Transistor104can further include a set of spacers120,122each adjacent one of the sidewalls E1, E2of gate structure108. Specifically, a first spacer120may be positioned laterally immediately adjacent to first sidewall E1of gate structure108, and a second spacer122may be positioned laterally immediately adjacent to second sidewall E2of gate structure108. Each spacer120,122may be formed of a charge trapping material, e.g., silicon nitride (SiN), polysilicon, hafnium-based oxides (e.g., HfO2, HfAlO, etc.), and/or other charge trapping materials currently known or later developed. In some embodiments, spacers120,122may have a same material composition. Spacers120,122may be similarly or substantially identically sized (e.g., they may be substantially symmetric), although this is not required in all implementations. Spacers120,122, however embodied, may be programmed independently of each other by way of circuitry connected to transistor104according to various methods discussed herein.

Each spacer120,122can include one or more layers of material, including one or more layers of charge trapping material as discussed above, positioned laterally immediately adjacent to a respective sidewall E1, E2of gate structure108. This layer of spacer material may extend upward away from semiconductor substrate102such that it covers its adjacent sidewall E1, E2. Each spacer material may include one or more dielectric materials, e.g., a high-K dielectric material. For purposes of this disclosure, a “high-K dielectric material” refers to a dielectric material with a dielectric constant that is at least equal to that of silicon nitride (e.g., 7.0 or more). In any case, the spacer(s)120,122can, in total, be relatively thin such that the maximum width of each spacer120,122is, e.g., between approximately two nanometers (nm) and approximately twenty nm.

Transistor104further may include a first S/D region124and a second S/D region126within substrate102. Each S/D region124,126can be a doped portion of semiconductor material within substrate102, or in further implementations may include an epitaxial semiconductor layer formed on underlying portions of substrate102. S/D regions124,126in any case may be adjacent channel region106. S/D regions124,126may have an opposite doping type with respect to other portions of substrate102. For instance, S/D regions124,126may be doped with a N-type dopant so as to have a N-type conductivity at a relatively high conductivity level. Substrate102by contrast, particularly in channel region106, can be either undoped or doped with a P-Type dopant so as to have an P-type conductivity at a relatively low conductivity level, thus defining a n-type or “NFET” structure. It is understood that these doping types may be reversed in other implementations (e.g., to provide an p-type or “PFET” structure). To provide stronger electrical contact between S/D regions124,126and any conductive contacts formed thereto, S/D regions124,126each may include a silicide region128formed by depositing a layer of metal on S/D region(s)124,126, annealing the deposited metal such that it reacts with the underlying semiconductor material to form conductive metal silicide regions, and removing any unreacted metal after the annealing concludes.

Gate structure108, however embodied, may have dimensions of a sufficient size for spacers120,122adjacent thereto to be programmed independently of each other. Such dimensions may be any width and length of sufficient size to prevent charge carriers injected from only one S/D region124,126from passing into both spacers120,122. For example, gate structure108may have a width-to-length ratio of between approximately 1.3 and approximately 1.5. In further implementations, gate structure108may have a width (e.g., a horizontal thickness within the plane of the page) of approximately 270 nanometers (nm) and a length (e.g., a horizontal thickness extending into and/or out of the plane of the page) of approximately 200 nm.

Each S/D region124,126may be electrically coupled (e.g., through silicide regions128) to a circuit130, e.g., through a combination of metal wires, vias, and/or a combination of other electrical connections. Circuit(s)130coupled to each S/D region124,126may be individual assemblies and/or components, or may be respective portions of one circuit130. Circuits130in some cases may take the form of a charge pump132, i.e., a circuit configuration that converts a direct current (DC) input voltage to an output DC voltage having a higher or lower magnitude than the input. Circuit(s)130and/or charge pump(s)132may be coupled to other components for operating a memory array, e.g., circuit(s)130may couple first S/D region124to a bit line (BL) and circuit(s)130may couple second S/D region126to a source line (SL). In conventional one-transistor memory assemblies, SL may directly couple a source or drain of the transistor to ground. In embodiments of the disclosure, however, either S/D region124,126may be set to a predetermined voltage or ground to enable charge trapping in either or both of spacers120,122.

In the case of a charge pump132, circuit130may include an array of capacitors, amplifiers, etc., for coupling an input terminal Vin to a set of output terminals Vout1, Vout2. The internal components of charge pump132, are not specifically shown inFIG.1as they are generally understood in the art. Output terminals Vout1, Vout2, regardless of the composition of circuit130, can be set to a relatively high “memory voltage” relative to the operating voltage(s) of other portions of circuit130and/or portions of a device coupled thereto. The voltage of each output terminal Vout1, Vout2can be independently controlled, such that their voltage levels may be the same or different. Circuit130and/or charge pump132, in various examples, may be capable of yielding a memory voltage at terminals Vout1, Vout2of a magnitude of, e.g., approximately five volts (V) or similar amounts that exceed the operating voltage of other devices and/or components on substrate102. Circuit130and/or charge pump132may have an additional node VGwhich may be coupled to a word line (WL) of the memory array. Word line WL may be operated to selectively apply a voltage for operating gate structure108of transistor104at additional node VGto enable or disable current flow through channel region106. Additional node VGis depicted as being separate from or not coupled to circuit130and/or charge pump132, but it may be coupled to circuit(s)130and/or charge pump(s)132in other implementations. The voltage for operating transistor104applied at additional node VGmay be of higher magnitude than the memory voltage applied output terminals Vout1, Vout2, e.g., it may be approximately seven V in the case where output terminals Vout1, Vout2are programmed using voltage magnitudes of approximately three V or five V.

Turning toFIG.2, circuit130of structure100may operate to program one spacer120,122of transistor104independently of the other as discussed herein. This feature is a contrast to conventional one-transistor memory devices, as such device conventionally allow charge carriers to only be stored within one spacer while not permitting data to be stored in the other spacer. To program only second spacer122, an operator of structure100, including circuit130and/or charge pump132, may set first output terminal Vout2to a predetermined voltage (e.g., five V or other amount), simultaneously setting second output terminal Vout1to zero V and additional node VGto a predetermined amount (e.g., seven V) to enable current flow between S/D regions124,126. In this case, the high voltage being applied to first S/D region126(e.g., the drain side of transistor104) will cause charge carriers to pass through channel region106and induce “hot carrier injection” into second spacer122.

Hot carrier injection is shown inFIG.2via the black dots indicating charge carriers and corresponding white dots indicating holes. Hot carrier injection refers to an instance where a charge carrier (e.g., an electron) attains sufficient energy to overcome a potential barrier, and thus break an interface state for the particle to donate the charge carrier. The term “hot” refers to the high temperatures needed to model carrier density, and not to the operating temperature of a material undergoing hot carrier injection. In the case of a transistor, charge carriers becoming trapped gate dielectric material ordinarily may permanently affect and damage the operation affect the switching characteristics of a transistor. By including spacer(s)120,122, hot carrier injection can instead be used to store and retrieve a charge via the spacer120,122material. Thus, embodiments of structure100allow transistor104to function as a memory device by enabling charge capture and removal in either or both spacers120,122.

FIG.3depicts an example for further programming of transistor104in the case where charge carriers have already been injected into second spacer122. Although the programming of first spacer120may occur after the programming of second spacer122, the order of these operations may be reversed, and/or one programming operation may be performed without the other. Here, first spacer120is programmable independent of second spacer122by using circuit130and/or charge pump132to set first output terminal Vout2to zero V while setting second output terminal Vout1to a predetermined voltage (e.g., five V or other amount). Additional node VGsimultaneously may be set to another voltage (e.g., seven V as discussed herein) to enable current flow between S/D regions124,126. Unlike the programming of second spacer122, the memory voltage being applied to second S/D region126(e.g., the drain side of transistor104) will cause charge carriers to pass through channel region106and induce “hot carrier injection” into only first spacer120at the opposite horizontal end from S/D region126.FIG.3depicts electrons being injected into first spacer120while previously injected charge carriers of second spacer122remain within second spacer122. Regardless of which spacer(s)120,122hold charge carriers therein, the memory state of transistor104is readable by applying a voltage to node VGand simultaneously to124and126. During a read operation, the voltage applied to S/D region126may be a low voltage (e.g., approximately 1.2 V) to avoid causing further hot carrier injection and voltage on S/D region124when it is set to ground, or vice versa.

FIG.4depicts an example of an erase operation, e.g., to remove stored charge carriers from either or both of spacers120,122. Although the erase operation may remove charge carriers from spacers120,122simultaneously, it is possible for the same operation to remove charge carriers from only one spacer120,122. According to embodiments, circuit130and/or charge pump132may set additional node VGto an inverted voltage (e.g., negative seven V) and simultaneously setting output terminals Vout1, Vout2to a predetermined “erase voltage,” which may be of lesser magnitude than the memory voltage. According to one example, the erase operation may include setting output terminals Vout1, Vout2to an erase voltage of approximately three V. The positive-to-negative voltage differential between spacers120,122and channel region106induced by these applied voltages may cause holes to be injected into spacers120,122, thus neutralizing the accumulated charge carriers stored therein. These programming and erasing features of structure100may produce a memory element having substantially reduced programming time as compared to conventional one-sided programmable transistors. In various examples, transistor104may be programmable within a time span of approximately ten microseconds, as compared to one millisecond for conventional programmable transistors.

Referring toFIG.5with reference toFIG.1, an example flow diagram for implementing a method according to embodiments of the disclosure is provided. In process P1, methods of the disclosure include operating circuit130and/or charge pump132, e.g., by placing circuit130and/or charge pump132into an ON state. During such operation, internal logic of circuit130and/or devices coupled to charge pump132may determine at decision D1whether to perform a write operation or an erase operation on transistor104. In the case of a write operation (i.e., “Write” at decision D1), the method may proceed to process P2of applying a voltage to gate structure108of transistor104, e.g., using additional node VGas discussed herein. Either or both of processes P3and P4then may be used to inject charge carriers into (and thus program) first spacer122or second spacer122, by applying the memory voltage to the opposite S/D region124,126discussed herein. Hence, process P3may include applying the memory voltage to first S/D region124to inject charge carriers into second spacer122whereas process P4may include applying the memory voltage to second S/D region126to inject charge carriers into first spacer122. As indicated by dashed lines, some implementations may omit process P2, e.g., where a voltage is applied to transistor104independently of any action by circuit130and/or charge pump132. The method then may conclude (“Done”) or return to process P1to continue operating circuit130and/or charge pump132until another write or erase operation is implemented.

In the case of an erase operation (i.e., “Erase” at decision D2), the method may continue to process P5of applying the inverted voltage to gate structure108of transistor104. In some implementations, process P5may be omitted because components other than circuit130and/or charge pump132apply the inverted voltage to gate structure108. In any case, the method may continue to process P6of applying the erase voltage simultaneously to first S/D region124and second S/D region126to inject holes into spacer(s)120,122, thus neutralizing any accumulated charge therein. The method then may conclude (“Done”) or return to process P1until another write or erase operation is implemented. Thus, embodiments of the disclosure are operable to use source line SL/bit line BL for programming by applying a positive or grounding voltage to transistor104using via source line SL. The program and erase voltages may be applied to selected transistor(s)104, which may be connected to a row control block that includes word line drivers. Similarly, source line SL and bit line BL may be connected to a column control block that includes drivers for each line SL, BL.

Embodiments of the disclosure provide various technical and commercial advantages, examples of which are discussed herein. By allowing spacers120,122of transistor104to be injected with charge carriers independently of each other, the memory voltage(s) needed to program transistor104may be lower or the time needed to program transistor104may be shorter than what is needed to program conventional CTSS-NVM devices. These lower voltages or shorter program time may also allow an operator of structure100to tune the programming and erase voltages of transistor104to suit a wide variety of applications. Transistor104, in some cases, optionally may be implemented by causing only one of two spacers120,122to have charge carriers injected therein, even though programming of both spacers120,122remains possible.