Gallium nitride material devices and methods of forming the same

The invention provides gallium nitride material devices, structures and methods of forming the same. The devices include a gallium nitride material formed over a substrate, such as silicon. Exemplary devices include light emitting devices (e.g., LED's, lasers), light detecting devices (such as detectors and sensors), power rectifier diodes and FETs (e.g., HFETs), amongst others.

FIELD OF INVENTION

The invention relates generally to semiconductor materials and, more particularly, to gallium nitride materials and methods of producing gallium nitride materials.

BACKGROUND OF INVENTION

Gallium nitride materials include gallium nitride (GaN) and its alloys such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). These materials are semiconductor compounds that have a relatively wide, direct bandgap which permits highly energetic electronic transitions to occur. Such electronic transitions can result in gallium nitride materials having a number of attractive properties including the ability to efficiently emit visible (e.g., blue, green) or UV light, the ability to transmit signals at high frequency, and others. Accordingly, gallium nitride materials are being widely investigated in many semiconductor device applications such as transistors, field emitters, and optoelectronic devices.

Gallium nitride materials have been formed on a number of different substrates including silicon carbide (SiC), sapphire, and silicon. Silicon substrates are readily available and relatively inexpensive, and silicon processing technology has been well developed. However, forming gallium nitride materials on silicon substrates to produce semiconductor devices presents challenges which arise from differences in the lattice constant, thermal expansion, and band gap between silicon and gallium nitride.

SUMMARY OF INVENTION

The invention includes providing gallium nitride material structures, devices and methods of forming the structures and devices.

In one aspect, a semiconductor device is provided. The device comprises a substrate, and a gallium nitride material region formed over the substrate. The semiconductor device has at least one via extending from a first side of the semiconductor device, wherein the via is free of an electrical contact formed therein.

In another aspect, a method of forming a semiconductor device is provided. The method comprises forming a gallium nitride material region over a substrate, and forming a via extending from a first side of the semiconductor device. The via is free of an electrical contact formed therein.

In another aspect, a semiconductor device is provided. The semiconductor device comprises a silicon substrate and a gallium nitride material region formed over the silicon substrate. The device further comprises a first electrical contact formed over a portion of the gallium nitride material region, and a second electrical contact formed over a portion of the gallium nitride material region. The semiconductor device has at least one via extending from a backside of the semiconductor device.

In another aspect, a method of forming a semiconductor device is provided. The method comprises forming a gallium nitride material region over a silicon substrate, forming a first electrical contact over the gallium nitride material region, and forming a second electrical contact over the gallium nitride material region. The method further comprises forming a via extending from a backside of the semiconductor device.

In another aspect, an opto-electronic device is provided. The opto-electronic device comprises a silicon substrate, a compositionally-graded transition layer formed over the silicon substrate, and a gallium nitride material region formed over the compositionally-graded transition layer. The gallium nitride material region includes an active region.

In another aspect, a method of forming a opto-electronic device is provided. The method comprises forming a compositionally-graded transition layer formed over a silicon substrate, and forming a gallium nitride material region over the compositionally-graded transition layer. The gallium nitride material region includes an active region.

In another aspect, a method of forming a semiconductor structure is provided. The method comprises forming a first transition layer over a silicon substrate, forming a gallium nitride material region over the first transition layer, and removing the silicon substrate to expose a backside of the transition layer.

In another aspect, an opto-electronic device is provided. The opto-electronic device comprises a transition layer comprising a gallium nitride alloy, aluminum nitride, or an aluminum nitride alloy. The transition layer has an exposed back surface. The device further comprises a gallium nitride material region formed over a front surface of the transition layer. The gallium nitride material region includes an active region.

In another aspect, an opto-electronic device is provided. The opto-electronic device comprises a transition layer comprising a gallium nitride alloy, aluminum nitride, or an aluminum nitride alloy. The device further comprises an electrical contact formed directly on a back surface of the transition layer, and a gallium nitride material region formed over a front surface of the transition layer. The gallium nitride material region includes an active region.

In another aspect, an opto-electronic device is provided. The opto-electronic device comprises a silicon substrate, a gallium nitride material region formed over the substrate. The gallium nitride material region includes an active region, wherein the active region has a non-rectangular plane-view cross-section.

In another aspect, an opto-electronic device is provided. The opto-electronic device comprises a substrate, a gallium nitride material region formed over the substrate. The gallium nitride material region includes an active region, wherein the active region has a non-rectangular plane-view cross-section. A non-active region of the opto-electronic device has a non-rectangular plane-view cross-section.

In another aspect, a method is provided. The method comprises forming an active region having a non-rectangular plane-view cross-section. The active region is a portion of a gallium nitride material region formed on a silicon substrate.

In another aspect, a method is provided. The method comprises forming an active region having a non-rectangular plane-view cross-section. The active region is a portion of a gallium nitride material region formed on a substrate. The method further comprises forming a non-active region having a non-rectangular plane-view cross-section.

Other aspects, embodiments and features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings. The accompanying figures are schematic and are not intended to be drawn to scale. In the figures, each identical, or substantially similar component that is illustrated in various figures is represented by a single numeral or notation. For purposes of clarity, not every component is labeled in every figure. Nor is every component of each embodiment of the invention shown where illustration is not necessary to allow those of ordinary skill in the art to understand the invention. All patent applications and patents incorporated herein by reference are incorporated by reference in their entirety. In case of conflict, the present specification, including definitions, will control.

DETAILED DESCRIPTION OF THE INVENTION

The invention provides gallium nitride material structures, devices and methods of forming the structures and devices.

Referring toFIG. 1, a semiconductor device10according to one embodiment of the invention is shown. Semiconductor device10includes a substrate12and a gallium nitride material device region14formed over the substrate. As described further below, device structures are typically formed, at least in part, within gallium nitride material region14. Device10further includes a transition layer15formed on substrate12, for example, to facilitate the subsequent deposition of gallium nitride material device region14. In some cases, the transition layer (or, at least a portion of the transition layer) may be non-conducting. A topside electrical contact16(on a topside18of the device) and a backside electrical contact20(on a backside22of the device) are provided for connection to an external power supply that powers the device. Backside contact20is deposited within a via24that extends from backside22of the device. Via24extends through transition layer15and into a conducting region (e.g., device region14) within device10. As a result of the deposition of backside contact20within via24, current can flow between the backside contact and topside contact16through device region14without being blocked by transition layer15, when the transition layer is non-conducting. Thus, vertical conduction through device10between backside contact20and topside contact16may be achieved despite the presence of a non-conducting transition layer15.

As used herein, “non-conducting” refers to a layer that prevents current flow or limits current flow to negligible amounts in one or more directions. “Non-conducting” layers, for example, may be formed of non-conductor materials, or may be formed of semiconductor materials which have a band sufficiently offset from the layer adjacent the “non-conducting” layer. A “non-conducting” layer may be conductive in and of itself, but may still be non-conducting (e.g., in a vertical direction) as a result of a band offset or discontinuity with an adjacent layer. As used herein, “vertical conduction” refers to electrical current flow in a vertical direction within a device. “Vertical conduction” may be between backside contact and topside contact or may be between different layers within the device that are separated vertically.

It should be understood that when a layer is referred to as being “on” or “over” another layer or substrate, it can be directly on the layer or substrate, or an intervening layer also may be present. A layer that is “directly on” another layer or substrate means that no intervening layer is present. It should also be understood that when a layer is referred to as being “on” or “over” another layer or substrate, it may cover the entire layer or substrate, or a portion of the layer or substrate.

As shown in the figures, the term “topside” refers to the upper surface of a structure or device and the term “backside” refers to the bottom surface of a structure or device. It should be understood that the substrate also has a “topside” and a “backside.” When processing a typical structure, layer(s) are grown from the topside of the substrate and the resulting upper growth surface defines the topside of the structure or device. In some cases, during use, a device may be flipped so that its backside faces upward and its topside faces downward (e.g., SeeFIG. 20). In these “flip chip” embodiments, the topside of the device may be mounted to another surface (e.g., to provide a source of power to electrodes on the topside).

In certain preferred embodiments, substrate12is a silicon substrate. As used herein, silicon substrate14refers to any substrate that includes a silicon layer. Examples of suitable silicon substrates include substrates that are composed entirely of silicon (e.g., bulk silicon wafers), silicon-on-insulator (SOI) substrates, silicon-on-sapphire substrate (SOS), and SIMOX substrates, amongst others. Suitable silicon substrates also include substrates that have a silicon wafer bonded to another material such as diamond, AIN, or other polycrystalline materials. Silicon substrates having different crystallographic orientations may be used. In some cases, silicon (111) substrates are preferred. In other cases, silicon (100) substrates are preferred.

It should be understood that in other embodiments, substrates other than silicon substrates may be used such as sapphire and silicon carbide substrates.

Substrate12may have any suitable dimensions and its particular dimensions are dictated by the application. Suitable diameters include, but are not limited to, 2 inches (50 mm), 4 inches (100 mm), 6 inches (150 mm), and 8 inches (200 mm). In some embodiments, silicon substrate12is relatively thick, for example, greater than 250 microns. Thicker substrates are generally able to resist bending which can occur, in some cases, in thinner substrates. In some embodiments, silicon substrate12is preferably thin, for example less than 250 microns, or less than 100 microns, to facilitate the formation of via24therethrough.

Transition layer15may be formed on substrate12prior to the deposition of gallium nitride material device region14, for example, to accomplish one or more of the following: reducing crack formation in gallium nitride material device region14by lowering thermal stresses arising from differences between the thermal expansion rates of gallium nitride materials and the substrate; reducing defect formation in gallium nitride material device region14by lowering lattice stresses arising from differences between the lattice constants of gallium nitride materials and the substrate; and, increasing conduction between substrate12and gallium nitride material device region14by reducing differences between the band gaps of substrate12and gallium nitride materials. The presence of transition layer15may be particularly preferred when utilizing silicon substrates because of the large differences in thermal expansion rates and lattice constant between gallium nitride materials and silicon. It should be understood that transition layer15also may be formed between substrate12and gallium nitride material device region for a variety of other reasons. As noted above, transition layer15may be non-conducting, although, in some cases, transition layer15may be conducting.

The composition of transition layer15depends, at least in part, upon the type of substrate and the composition of gallium nitride material device region14. In some embodiments which utilize a silicon substrate, transition layer15may preferably comprise a compositionally-graded transition layer having a composition that is varied across at least a portion of the layer. Suitable compositionally-graded transition layers, for example, have been described in commonly-owned, U.S. Pat. No. 6.649,287, entitled “Gallium Nitride Materials and Methods,” filed on Dec. 14, 2000, which is incorporated herein by reference.

Compositionally-graded transition layers are particularly effective in reducing crack formation in gallium nitride material device region14by lowering thermal stresses that result from differences in thermal expansion rates between the gallium nitride material and substrate12(e.g., silicon). In some embodiments, when compositionally-graded, transition layer15is formed of an alloy of gallium nitride such as AlxInyGa(1−x−y)N, AlxGa(1−x)N, or InyGa(1−y)N. In these embodiments, the concentration of at least one of the elements (e.g., Ga, Al, In) of the alloy is typically varied across at least a portion of the cross-sectional thickness of the layer.

In other embodiments, transition layer15has a constant (i.e., non-varying) composition across its thickness. Such layers may be referred to as buffer layers and/or intermediate layers. Suitable intermediate layers, for example, have been described in U.S. Pat. No. 6,649,287, referenced above. In some embodiments, transition layer15has a constant composition of a gallium nitride alloy (such as AlxInyGa(1−x−y)N, AlxGa(1−x)N, or InyGa(1−y)N), aluminum nitride, or an aluminum nitride alloy.

In the illustrative embodiment ofFIG. 1, a single transition layer15is shown between substrate12and gallium nitride material device region14. Other embodiments may include more than one transition layer. For example, as shown inFIG. 2, device10amay include a compositionally-graded transition layer15aformed on (in some cases, directly on) a transition layer15bhaving a constant composition (e.g., an intermediate layer of a gallium nitride alloy, aluminum nitride, or an aluminum nitride alloy). It should also be understood that constant composition transition layer15bmay be formed on (in some cases, directly on) compositionally-graded transition layer15a. In some cases, the device may include two constant composition transition layers—for example, a first formed on the compositionally-graded transition layer and a second formed on the substrate under the compositionally-graded transition layer.

It also should be understood that in some embodiments, one or more other types of layers (including conducting layers) may be present between substrate12and gallium nitride material device region14which may accomplish one or more of the above-described features of the transition layer. In some cases, the transition layer is the sole layer between the substrate and the gallium nitride material device region. In embodiments, that include one or more conducting layer, the structure may not include any non-conducting layers.

In the embodiment ofFIG. 1, via24extends through transition layer15of substrate12so that vertical conduction can occur in device10even when the transition layer is non-conducting. Thus, in these embodiments, at a minimum, via24has a length (L) sufficient to create a conducting vertical path between topside contact16and backside contact20. Via24, for example, may extend to a position within gallium nitride material device region14to form such a conducting path. In some cases, it may be preferable to have via24extend to an etch-stop layer (e.g., See46,FIG. 5) within gallium nitride material device region14, to facilitate processing as described further below. In certain embodiments, via24may extend to a position below gallium nitride material device layer—for example, within an upper portion of a doped, conductive transition layer and, thus, a vertical conducting path is formed. In some cases, via24may extend to a source region or a drain region formed within device10.

The exact dimensions and shape of via24depend upon the application. A typical cross-sectional area of via is about 100 microns by about 100 microns at backside22. The cross-sectional area of the via may be square (as shown inFIG. 22), circular or another shape. It may be preferable for via24to be tapered inward, as shown, thus giving the via a cone shape (i.e., a truncated pyramid shape). The inward taper (i.e., a cross-sectional area that decreases in a direction away from the backside) can facilitate deposition of backside contact20on side walls28of via24and may also, in some cases, be beneficial for enhancing light extraction. In other cases, as described further below and shown inFIG. 10, it may be preferable for the via to be tapered outward (i.e., a cross-sectional area that increases in a direction away from the backside). An outwardly tapered via may enhance internal light reflection which can improve light extraction in certain embodiments. In some cases, it may be preferable to have via24positioned away from sides29of the device. That is, the via does not intersect with a side of the device.

InFIG. 1, device10includes a single via24. Other embodiments, however, as described further below and shown inFIGS. 2-3, may include more than one via.

As used herein, the phrase “electrical contact” or “contact” refers to any conducting structure on a semiconductor device that is designed to be contacted by a power source. “Contacts” may also be referred to as electrodes, terminals, contact pads, contact areas, contact regions and the like. It should be understood that certain types of conducting structures that are on, or part of, a semiconductor device are not electrical contacts, as used herein. For example, conducting regions or layers (e.g., reflector layer120in some cases) that are not contacted by a power source during use are not electrical contacts as defined herein.

Backside contact20and topside contact16are formed of conducting materials including certain metals. Any suitable conducting material known in the art may be used. The composition of contacts16,20may depend upon the type of contact. For example, contacts16,20may contact n-type material or p-type material. Suitable metals for n-type contacts include titanium, nickel, aluminum, gold, copper, and alloys thereof. Suitable metals for p-type contacts include nickel, gold, and titanium, and alloys thereof.

Contacts16,20have a thickness sufficient to ensure that the contact is electrically conductive across its entire physical area. Suitable thicknesses for contacts16,20, for example, are between about 0.05 microns and about 10 microns. In some cases, the thickness of backside contact20may vary over its area because of uneven deposition on side walls28of via24. The surface areas of backside contact20and topside contact16are generally sufficient so that the contacts can be contacted by terminals of an appropriate power source through wire bonding, air bridging and the like. In certain preferred embodiments, backside contact20substantially extends only over backside and does not, for example, extend over sides30of device10. Thus, in these preferred embodiments, sides30are substantially free of backside contact20.

In some embodiments, as described further below, semiconductor structure may include one or more backside contact and no topside contact (e.g.,FIG. 3), or one or more topside contact (e.g., two for light emitting devices or three for FETs) and no backside contact (e.g.,FIGS. 13-16).

In some embodiments, contacts16,20also may function as an effective heat sink. In these embodiments, contacts16,20remove thermal energy generated during the operation of the device. This may enable device10to operate under conditions which generate amounts of heat that would otherwise damage the device. In particular, laser diodes that operate at high current densities may utilize contacts16,20as a heat sink. Contacts16,20may be specifically designed to enhance thermal energy removal. For example, contacts16,20may be composed of materials such as copper and gold, which are particularly effective at removing heat. Also, contacts16,20may be designed so that a large surface area is in contact with device region14—for example, by including multiple vias and/or vias that extend significantly into device region14.

In some embodiments, such as when device10is an opto-electronic device, contacts16,20can function as a reflector region (e.g.,120a,FIG. 19), as described further below. By reflecting light generated by the device, contacts16,20can direct the light in a desired direction, for example, out of topside18, backside22, and/or sides30of device10depending on the design of the device. Thus, the output efficiency of the device may be enhanced. In particular, laser diodes and light emitting diodes can benefit from utilizing the reflective properties of contacts16,20. To enhance the ability of backside contact20to reflect light, for example, via24is formed such that the backside contact extends proximate an active region (e.g.,38,FIG. 4;50,FIG. 5).

As used herein, the term “active region,” when used in connection with a light emitting device, refers to a light generating region, and when used in connection with a light detecting device refers to a light collecting region.

In certain embodiments, and as described further below in connection withFIGS. 9-11,13-14, and16-18, it may be preferable for via24to be free of a contact. That is, a contact is not formed within the via. In some cases, the via may be free of a contact but may have one or more other region(s) or layer(s) formed therein (e.g., a reflective layer), as described further below. In some cases, the via may be free of any material formed therein. When free of material, the via may function as a window that exposes internal layers of the device (e.g., transition layer15or gallium nitride material device region14) to the outside. This exposure may enhance the extraction of light from the device which can be particularly useful in light-emitting devices such as LEDs or lasers. In embodiments in which via24is free of an electrical contact, it should be understood that contacts are formed on other parts of the device including other (non-via) areas of backside22or areas of topside18.

In some cases, to maximize exposure of the internal device layers, substrate12may be entirely removed, for example, by etching (wet or dry) or grinding. Such a device is shown inFIGS. 12,15and25, and described further below. When the substrate is entirely removed, it may be desirable to mount, or bond, the structure to a carrier which may be a wafer (e.g., silicon or GaAs) that provides rigidity and/or support during further processing, handling, or use. The rigidity and/or support provided by the carrier result from its relatively large thickness compared to the thickness of the remaining structure. In some cases, carriers may also function as a reflector region.

Gallium nitride material device region14comprises at least one gallium nitride material layer. In some cases, gallium nitride material device region14includes only one gallium nitride material layer. In other cases, as described further below and shown inFIGS. 4-8, gallium nitride material device region14includes more than one gallium nitride material layer. The different layers can form different regions of the semiconductor structure. Gallium nitride material region14also may include one or more layers that do not have a gallium nitride material composition such as other III-V compounds or alloys, oxide layers, and metallic layers.

As used herein, the phrase “gallium nitride material” refers to gallium nitride (GaN) and any of its alloys, such as aluminum gallium nitride (AlxGa(1−x)N), indium gallium nitride (InyGa(1−y)N), aluminum indium gallium nitride (AlxInyGa(1−x−y)N), gallium arsenide phosporide nitride (GaAsaPbN(1−a−b)), aluminum indium gallium arsenide phosporide nitride (AlxInyGa(1−x−y)AsaPb N(1−a−b)), amongst others. Typically, when present, arsenic and/or phosphorous are at low concentrations (i.e., less than 5 weight percent). In certain preferred embodiments, the gallium nitride material has a high concentration of gallium and includes little or no amounts of aluminum and/or indium. In high gallium concentration embodiments, the sum of (x+y) may be less than 0.4, less than 0.2, less than 0.1, or even less. In some cases, it is preferable for the gallium nitride material layer to have a composition of GaN (i.e., x+y =0). Gallium nitride materials may be doped n-type or p-type, or may be intrinsic. Suitable gallium nitride materials have been described in U.S. Pat No. 6,649,287, incorporated herein.

Gallium nitride material region14is of high enough quality so as to permit the formation of devices therein. Preferably, gallium nitride material region14has a low crack level and a low defect level. As described above, transition layer15may reduce crack and/or defect formation. In some embodiments, gallium nitride material region14has about 109defects/cm2. Gallium nitride materials having low crack levels have been described in U.S. Pat. No. 6,649,287, referenced above. In some cases, gallium nitride material region14has a crack level of less than 0.005 μm/μm2. In some cases, gallium nitride material has a very low crack level of less than 0.001 μm/μm2. In certain cases, it may be preferable for gallium nitride material region14to be substantially crack-free as defined by a crack level of less than 0.0001 μm/μm2.

In certain cases, gallium nitride material region14includes a layer or layers which have a monocrystalline structure. In some preferred cases, gallium nitride material region14includes one or more layers having a Wurtzite (hexagonal) structure.

The thickness of gallium nitride material device region14and the number of different layers are dictated, at least in part, by the requirements of the specific application. At a minimum, the thickness of gallium nitride material device region14is sufficient to permit formation of the desired device. Gallium nitride material device region14generally has a thickness of greater than 0.1 micron, though not always. In other cases, gallium nitride material region14has a thickness of greater than 0.5 micron, greater than 0.75 micron, greater than 1.0 microns, greater than 2.0 microns, or even greater than 5.0 microns.

When device10is a light-emitting device, it may also include a reflector region120(SeeFIG. 16). Reflector region120increases the reflectivity of an interface and typically directs or steers the light in a desired location or direction within a light-emitting device. The composition and structural characteristics (e.g., thickness) of the reflector region may be selected to reflect the desired wavelength (or range or wavelengths) of light.

Reflector region120may be a single layer or a series of layers. In some cases, reflector region120comprises a metal. In other cases, reflector region120may comprise a dielectric or semiconductor material. In these cases, typically, multiple dielectric or semiconductor material layers are stacked to form the reflector region. One example of a multi-layer reflector region is a Distributed Bragg Reflector (DBR). A DBR has at least two layers of different compositions (e.g., gallium nitride alloys or oxide-based compounds).

The location of the reflector region in the device is selected so as to reflect light in the desired direction. Typically, the position of the reflector region is selected relative to the light emitting region(s) of the device. For example, if it is desired to reflect light in the direction of the backside of the device, reflector region120is preferably located above an active region (e.g.,97,FIG. 17) in which light is generated. If it is desired to reflect light in the direction of the topside of the device, reflector region120is preferably located below the active region (e.g.,97,FIG. 16). In some cases, such as when the device is a laser, reflector region120may located both above and below an active region. Depending on the device design, reflector region120may be a portion of the gallium nitride material region14, or may be located above or below the gallium nitride material region. As noted above, in some cases, reflector region120may be an electrical contact, though other types of electrical contacts are not reflector regions. In embodiments in which the reflector region also functions as an electrical contact, the reflector region, for example, may be formed of aluminum, silver or rhodium.

Device10may be formed using known processing techniques. Transition layer15and gallium nitride material device region14may be deposited on substrate12, for example, using metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE), amongst other techniques. In some cases, an MOCVD process may be preferred. A suitable MOCVD process to form a compositionally-graded transition layer15and gallium nitride material device region14over a silicon substrate12has been described in U.S. Pat. No. 6,649,287, referenced above. When gallium nitride material device region14has different layers, in some cases it is preferable to use a single deposition step (e.g., an MOCVD step) to form the entire device region14. When using the single deposition step, the processing parameters are suitably changed at the appropriate time to form the different layers. In certain preferred cases, a single growth step may be used to form transition layer15and gallium nitride material device region14.

When present, reflector region120may also be formed using known processing techniques. For example, when the reflector region comprises a metal, the metal may be sputtered or evaporated. When the reflector region comprises a series of semiconductor material layers, the layers may be deposited using metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE), amongst other techniques. When the reflector region comprises a series of dielectric material layers, the layers may be deposited by chemical vapor deposition (CVD) or sputtering.

In some cases, it may be preferable to grow device region14using a lateral epitaxial overgrowth (LEO) technique that involves growing an underlying gallium nitride layer through mask openings and then laterally over the mask to form the gallium nitride material device region, for example, as described in U.S. Pat. No. 6,051,849, which is incorporated herein by reference. In some cases, it may be preferable to grow device region14using a pendeoepitaxial technique that involves growing sidewalls of gallium nitride material posts into trenches until growth from adjacent sidewalls coalesces to form a gallium nitride material region, for example, as described in U.S. Pat. No. 6,177,688, which is incorporated herein by reference. In these lateral growth techniques, gallium nitride material regions with very low defect densities are achievable. For example, at least a portion of gallium nitride material region14may have a defect density of less than about 105defects/cm2.

Conventional etching techniques may be used to form via24. Suitable techniques include wet chemical etching and plasma etching (i.e., RIE, ICP etching, amongst others). Different etching techniques may be utilized when etching through different layers of device10. For example, a fluorine-based RIE process may be used to etch through substrate12and a chlorine-based RIE process may be used to etch through gallium nitride device region14and/or transition layer15. A pre-determined etching time may be used to form via24with the desired dimensions. In other cases, an etch stop layer (e.g., See46,FIG. 5), which has a composition that is not readily etched by the technique being used, may be provided within device10to stop etching so that precise control over the etching time is not required to form via24with desired dimensions.

Backside contact20and topside contact16may be deposited using known techniques suitable for depositing conducting materials such as metals. Such techniques include sputtering, electron beam deposition, and evaporation, amongst others. In some cases, a series of layers having different metallic compositions are deposited successively to form contacts16,20. In some of these cases, an annealing technique is used to yield equilibration of the contact composition. Because backside contact20is deposited within via24, the deposition technique should be performed in a manner that provides sufficient coverage within via24.

As known in the semiconductor art, multiple device structures may be formed on the same wafer of substrate material. A dicing operation, which utilizes a saw, may be used to separate individual devices from one another. In embodiments using silicon substrates, devices may be separated in an etching process (e.g., wet or dry) which etches through the substrate and layers. This etching process may use different etch chemistries when etching through different layers of the structure and substrate. For example, a fluorine-based gas may be used to etch through the silicon substrate and a chlorine-based gas may be used to etch through gallium nitride device region14and/or transition layer15. Separation using an etching process can enable formation of devices having non-rectangular die shapes (SeeFIGS. 23C-23K) which may be advantageous in certain light emitting applications, as described further below.

FIG. 2illustrates device10awhich includes multiple vias24a,24baccording to another embodiment of the present invention. A single backside contact20is formed in and across both vias24a,24b. Using multiple vias24a,24bas shown inFIG. 2may enhance heat removal, improve light reflection, and increase vertical conduction. As noted above, device10aalso includes a compositionally-graded transition layer15aformed on a constant composition transition layer15b. It should be understood that device10ais not limited to this transition layer arrangement and that other transition layer(s) described herein are possible including a single transition layer.

FIG. 3illustrates device10bincluding multiple vias24a,24baccording to another embodiment of the present invention. A first backside contact20ais formed in via24aand a second backside contact20bis formed in via24b. A dielectric layer31may be used, for example, to electrically isolate portions of backside contact20bto prevent shorting of device10. Suitable compositions for dielectric layer31include silicon oxide and silicon nitride. The embodiment ofFIG. 3does not have a topside contact (16inFIG. 1). The embodiment ofFIG. 3may be utilized in cases when it is not desirable to have a topside contact such as for surface mounted devices.

It should be understood that the invention also includes devices having backside vias and backside contacts with other configurations than those illustrated herein. For example, backside contact20may extend to an active region within gallium nitride material device region14, such as a source region or a drain region. Also, backside contact20may extend substantially through the thickness of the device so that the backside contact also forms a contact on topside18of the device.

It should also be understood that certain embodiments of the invention do not include a backside contact20as shown inFIG. 13. Device110includes a first topside contact16dand a second topside contact16e. As shown, first topside contact16dis formed on a first topside portion18aof gallium nitride material region14and second topside contact16eis formed on a second topside portion18bof the gallium nitride material region, wherein the first topside portion and the second topside portion are on different planes. In other cases, first and second topside contacts are formed on the same plane. It may be advantageous to include multiple topside contacts and no backside contacts, for example, when the topside of the device is mounted to a surface (e.g., in flip-chip embodiments). Also, it may be advantageous to include multiple topside contacts and no backside contacts in certain light emitting devices (e.g., LEDs, lasers) when it is desired to emit light out of the backside of the device. The absence of a backside contact, and/or any other material, in backside via24of device110can enhance light emission, amongst other advantages.

It should be understood that devices of the invention may include more than two (e.g., three contacts) topside contacts in certain device configurations (e.g., FETs)

FIG. 18illustrates a light-emitting device124that includes a medium126comprising phosphor. The medium, for example, may include phosphor dispersed in epoxy. The phosphor may convert light generated within the device to light of a different wavelength. For example, phosphor may be used to convert blue or UV-light generated within the device to white light. It should be understood that light emitting device124may have any suitable layer arrangement including layer arrangements of the LED embodiments described herein

Any suitable semiconductor device known in the art including electronic and opto-electronic devices may utilize features of the invention. In many cases, the device may be formed entirely within gallium nitride material region14(i.e., the only active device regions are within gallium nitride material region14). In other cases, the device is formed only in part within gallium nitride material region14and is also formed in other regions such as substrate12.

Exemplary devices include light emitting devices (such as laser diodes (LDs) and light emitting diodes (LEDs)), light detecting devices (such as detectors and sensors), power rectifier diodes, FETs (e.g., HFETs), Gunn-effect diodes, varactor diodes, amongst others. Light-emitting devices of the invention may be designed to emit the desired wavelength of light including visible light (e.g., blue) and UV-light. As described above, the device may also include one or more types of phosphor that converts the light generated within the device to white light. Although certain figures may illustrate certain types of devices, it should be understood that the features of these figures may also be used in other types of devices of the present invention. For example, thoughFIGS. 13-20illustrate light emitting devices, it should be understood that features of these figures may also be used in light detecting devices. In such light detecting devices, active region97is a light collector region, in contrast to the light generating region shown in some of these figures.

FIGS. 4-8illustrate examples of gallium nitride material devices according to the invention. It should be understood, however, that devices having other structures are also within the scope of the invention.

FIG. 4illustrates an exemplary LED32according to one embodiment of the present invention. LED32includes gallium nitride material device region14formed on transition layer15. Transition layer15may be compositionally-graded and is formed on silicon substrate12. In the illustrative embodiment, the following layers comprise gallium nitride material device region14in succession: a silicon-doped GaN layer34, a silicon-doped AlxGa(1−x)N layer36(e.g., containing 0-20% by weight Al), a GaN/InGaN single or multiple quantum well38, a magnesium-doped AlxGa(1−x)N layer40(e.g., containing 10-20% by weight Al), and a magnesium-doped GaN layer41. Via24extends from backside22to a position within GaN layer34. Topside contact16is formed of a metal on a p-type region and backside contact20is formed of a metal on an n-type region. LED32may be provided as a variety of different structures including: a double heterostructure (e.g., Al>0% in layer36), a single heterostructure (e.g., Al=0% in layer36), a symmetric structure, or an asymmetric structure. The LED illustrated in this embodiment is designed to emit visible light (e.g., blue light). It should be understood that LEDs having a variety of different structures may also be provided according to the invention including LEDs that emit UV light (SeeFIG. 21).

FIG. 5illustrates an exemplary laser diode42according to one embodiment of the present invention. Laser diode42includes gallium nitride material device region14formed on transition layer15. Transition layer15may be compositionally-graded and is formed on silicon substrate12. In the illustrative embodiment, the following layers comprise gallium nitride material device region14in succession: a silicon-doped GaN layer44, a silicon-doped AlxGa(1−x)N layer46(e.g., containing 5-30% by weight Al), a silicon-doped AlxGa(1−x)N layer48(e.g., containing 0-20% by weight Al), a GaN/InGaN single or multiple quantum well50, a magnesium-doped AlxGa(1−x)N layer52(e.g., containing 5-20% by weight Al), a magnesium-doped AlxGa(1−x)N layer54(e.g., containing 5-30% by weight Al), and a magnesium-doped GaN layer55. Via24extends from backside22to AlxGa(1−x)N layer46which functions as an etch-stop layer. Topside contact16is formed of a p-type metal and backside contact20is formed of an n-type metal. It should be understood that laser diodes having a variety of different structures may also be provided.

FIG. 6illustrates a power rectifier diode56according to one embodiment of the present invention. Diode56includes gallium nitride material device region14formed on transition layer15. Transition layer15may be compositionally-graded and is formed on silicon substrate12. In the illustrative embodiment, the following layers comprise gallium nitride material device region14in succession: a silicon-doped GaN layer58and an intrinsic GaN layer60. Via24extends from backside22to a position within GaN layer58. Topside contact16is formed of a rectifying metal and backside contact20is formed of an n-type metal. It should be understood that diodes having a variety of different structures may also be provided.

FIG. 7illustrates a double-gated HFET64according to one embodiment of the present invention. HFET64includes gallium nitride material device region14formed on transition layer15. Transition layer15may be compositionally-graded and is formed on silicon substrate12. In the illustrative embodiment, the following layers comprise gallium nitride material device region14in succession: an intrinsic GaN layer66and an intrinsic AlGaN region68. Via24extends from backside22to a position within GaN layer66. HFET64includes a source topside contact16a, a gate topside contact16b, and a drain topside contact16c. A backside gate contact20is formed within via24. It should be understood that HFETs having a variety of different structures may also be provided including HFETs having a plurality of gates.

FIG. 8illustrates an LED70including multiple backside vias24a,24baccording to another embodiment of the present invention. LED70includes gallium nitride material device region14formed on transition layer15. Transition layer15may be compositionally-graded and is formed on silicon substrate12. In the illustrative embodiment, the following layers comprise gallium nitride material device region14in succession: a silicon-doped GaN layer72, a silicon-doped AlxGa(1-x)N layer74(e.g., containing 0-20% by weight Al), a GaN/InGaN single or multiple quantum well76, a magnesium-doped AlxGa(1−x)N layer78(e.g., containing 10-20% by weight Al), and a magnesium-doped GaN layer80. Via24aextends from backside22to a position within GaN layer72and via24bextends from backside22to a position within GaN layer80. An n-type backside contact20ais formed within via24aand a p-type backside contact20bis formed within via24b. A dielectric layer31isolates portions of p-type backside contact20bto prevent shorting. It should be understood that LEDs having a variety of different structures may also be provided.

FIG. 9illustrates a device82including backside via24that is free of an electrical contact according to another embodiment of the present invention. Device82includes gallium nitride material device region14formed on a transition layer15. Device may have any suitable layer arrangement including the layer arrangements (or a portion thereof) of the LED embodiments described herein. Transition layer15can be compositionally-graded, as described above. Via24extends from backside22to transition layer15, thus, exposing the transition layer to the environment. An n-type contact20is formed on backside22.

FIG. 10illustrates a device96including a backside via24having a cross-sectional area that increases in a direction away from backside22. Device96may have any suitable layer arrangement including the layer arrangements (or a portion thereof) of the LED embodiments described herein. In the illustrative embodiment, device96is a light emitting device that includes an active region97in which light is generated, though other devices of the invention may also include a backside via having this shape. This via shape may enhance internal light reflections (as indicated by the arrows) and external light extraction from the topside of the device. In some cases, and as shown, device96may be mounted on a reflective surface98to further enhance light reflection and/or a reflector region120may be formed on walls of the via. Reflective surface98, for example, may be the surface of a packaging material or a carrier.

FIG. 11illustrates a device100according to another embodiment of the invention. Device100includes a number of contacts102formed on the front and back of substrate12. As shown, device100includes the same layer arrangement as the LED ofFIG. 8, though other suitable layer arrangements are also possible. LED100also includes an n-type contact104and a p-type contact106. A dielectric layer31isolates portions of the n-type and p-type contacts to prevent shorting.

FIG. 12illustrates a device108according to another embodiment of the present invention. Device108has the same layer arrangement as the device ofFIG. 11except that, during processing, the entire substrate has been removed using an etching step. Other layer arrangements may be used. The entire backside of transition layer15, which may be compositionally-graded or have a constant composition, is exposed to the environment. This embodiment may be particular useful in order to maximize light extraction from the device. It should be understood that other devices of the present invention, including non-light emitting devices, may also be processed by removing the entire substrate. It should also be understood that devices which include an exposed transition layer (e.g., a compositionally-graded transition layer) may also be used in devices that include two topside contacts, for example, as shown inFIG. 13. A topside or a backside of device108may be mounted on, or bonded to, a carrier (not shown). The carrier, which may be a wafer (e.g., silicon or GaAs), can provide support and rigidity for the device that may be desirable in the absence of the original substrate.

FIG. 14illustrates a light emitting device112according to another embodiment of the invention. Device112includes an active region97and may have any suitable layer arrangement including the layer arrangements (or a portion thereof) of the LED embodiments described herein. Device112has two topside contacts114a,114band no backside contacts. Arrows indicate the direction of light. The topside contacts also function as reflector regions which reflect, at least a portion of the light generated in layer97. In this embodiment, light is emitted out of the backside of the device.

FIG. 15illustrates a light emitting device116according to another embodiment of the invention. During processing of device, the substrate has been removed, for example, by an etching step. A topside or a backside of device116may be mounted on, or bonded to, a carrier (not shown, SeeFIG. 24) which provides support and rigidity for the device. In this illustrative embodiment, the entire backside of a transition layer15bhaving a constant composition (e.g., an intermediate layer of a gallium nitride alloy, aluminum nitride, or an aluminum nitride alloy) is exposed. A compositionally-graded transition layer15ais formed on constant composition transition layer15b. It should also be understood that, in some embodiments, constant composition transition layer15bis absent (or otherwise positioned) and compositionally-graded transition layer15ais exposed. In some cases, a passivating layer may be formed on transition layer15b; or, transition layer15bmay be mounted on the surface of a packaging material. The illustrative embodiment may be particular useful in order to maximize light extraction from the device. Device116also has two topside contacts114a,114band no backside contacts. The absence of backside contacts also enhances light emission. It should be understood that light emitting device116may have any suitable layer arrangement including the layer arrangements (or a portion thereof) of the LED embodiments described herein.

FIG. 16illustrates a light emitting device118according to another embodiment of the invention that includes reflector region120located below the active region97. Reflector region120reflects a substantial portion of the light (indicated by arrows) emitted from the active region in the direction of the topside of the device. Therefore, this structure enhances light emission out of the topside of the device. It should be understood that light emitting device116may have any suitable layer arrangement including the layer arrangements (or a portion thereof) of the LED embodiments described herein.

FIG. 17illustrates a light emitting device122according to another embodiment of the invention that includes reflector region120located above the active region97. Reflector region120reflects a substantial portion of the light (indicated by arrows) emitted from the light emitting region in the direction of the backside of the device. Therefore, this structure enhances light emission out of the backside of the device. It should be understood that light emitting device122may have any suitable layer arrangement including the layer arrangements (or a portion thereof) of the LED embodiments described herein.

FIG. 19illustrates a light emitting device130according to another embodiment of the invention that includes a first reflector region120aformed within via24. Device130has two topside contacts114a,114b. Reflector region120amay be, for example, a reflective metal layer. It should be understood that reflector region120ais not an electrical contact even when it comprises a conductive metal because it is not designed to be contacted by a power source. In the illustrative embodiment, device130may include a second reflector region120bformed over the via which may be a Distributed Bragg Reflector (DBR) that includes a number of semiconductor or dielectric layers. Device130includes two reflector regions to increase the ability of the device to reflect generated light in the desired direction. It should be understood, however, that other devices may include only one reflector region which may be formed within the via or may be formed over the via. It should be understood that light emitting device130may have any suitable layer arrangement including the layer arrangements (or a portion thereof) of the LED embodiments described herein.

FIG. 20illustrates a light emitting device136that has been flipped during use so that backside22faces upward and topside18faces downward. Topside contact114balso functions as a reflector region that can upwardly reflect light generated in region97. The device also includes a second reflector region120bwhich may be a Distributed Bragg Reflector (DBR) that includes a number of semiconductor or dielectric layers. Device136includes two reflector regions to increase the ability of the device to reflect generated light in the desired direction. It should be understood, however, that other devices may include only one reflector region which may be an electrical contact (e.g., topside contact114b) or a layer(s) within the structure of the device. It should be understood that light emitting device136may have any suitable layer arrangement including the layer arrangements (or a portion thereof) of the LED embodiments described herein.

FIG. 21illustrates an LED132designed to emit ultra-violet light, for example, having a wavelength between about 200 nm and about 410 nm. LED132includes gallium nitride material device region14formed on transition layer15. Transition layer15may be compositionally-graded and is formed on silicon substrate12. In the illustrative embodiment, the following layers comprise gallium nitride material device region14in succession: a silicon-doped AlxGa(1−x)N layer134(e.g., containing 0-100% Al), a silicon-doped AlxGa(1−x)N layer136(e.g., containing 20-80% by weight Al), an active region138, a magnesium-doped AlxGa(1−x)N layer140(e.g., containing 20-80% by weight Al), and a magnesium-doped AlxGa(1−x)N layer141(e.g., containing 0-80% by weight Al). Active region138may be a single or multiple quantum well (e.g., AlxGa(1−x)N/GaN, AlxGa(1−x)N/AlyGa(1−y)N, AlxGa(1−x)N/AlyIn(1−y)N, or AlxInyGa(1−x−y)N/AlaInbGa(1−a−b)N). In some cases, layers134,136,140,141may be superlattices and may include delta-doped regions to enhance conductivity. Topside contact16is formed of a metal on a p-type region and backside contact20is formed of a metal on an n-type region. It should be understood that LEDs having a variety of different structures may also be provided according to the invention including other types of LEDs that emit UV light and LEDs that emit visible light.

FIGS. 23A-23Kshow a series of plane-view cross-sections of the active regions97of a series of opto-electronic devices according to additional embodiments of the present invention. A plane-view cross-section is the cross-section of the active region taken in the plane of the active region (SeeFIG. 24). ThoughFIGS. 23A-23Kare taken with respect to the active region97shown inFIG. 24, it should be understood that active regions having the illustrated plane-view cross-sections also may be formed in any other suitable device structure including the other device structures described herein.

As seen in the figures, the devices of the invention may include active regions having a variety of plane-view cross-sections that may be designed for specific applications. In some cases, the plane-view cross-sections are rectangular or square (FIGS. 23A and 23B). Advantageously, certain embodiments of the invention, also enables formation of non-rectangular plane-view cross-sections including circular (FIG. 23C), star-shaped (FIG. 23D), hexagon (FIG. 23E), pentagon (FIG. 23F), octagon (FIG. 23G), triangular (FIG. 23H), trapezoid (FIG. 231), diamond (FIG. 23J) and H-shaped (FIG. 23K), amongst others.

Active regions having non-rectangular plane-view cross-sections may improve light extraction over conventional square or rectangular cross-sections by reducing internal reflective losses. Advantageously, the shape of the cross-sections may be tailored for the specific device to optimize light extraction efficiency. In some embodiments, it may be preferred to enhance light extraction for the active region to have a non-rectangular, non-circular plane view cross-section. A variety of other active region cross-sections may also be utilized in accordance with the present invention.

Active regions having non-rectangular plane-view cross-sections may be formed using an etching process. In some cases, the etching process used to form the active regions may be the same etching process used to separate individual devices processed on the same wafer from one another, as described above. This etching process may be used to form the active region and separate devices, for example, when the substrate is silicon because silicon may be readily etched, in contrast to other types of substrates (e.g., sapphire and silicon carbide) which typically require the use of a dicing operation to separate devices. In cases when the etching process used to form the active region is the same as the etching process used to separate individual devices processed on the same wafer, the active region may have the same plane-view cross-section as other non-active regions on the device (including other layers and the substrate), as well as the overall die shape. It should be understood that though the same etching process is used to form the active region and to separate individual devices processed on the same wafer, different etching chemistries may be used at various stages during this process, for example, to etch through different layers.

It should be understood that active regions having non-rectangular plane-view cross-sections may be formed in an etching process that does not separate individual devices processed on the same wafer from one another. In these cases, the individual devices may be separated using conventional dicing steps, for example, to form devices having a rectangular die shape. In these cases, the active region may have a non-rectangular plane-view cross-section, while non-active regions may have a different plane-view cross-section (including a rectangular plane-view cross-section).

FIG. 25shows a light emitting device160according to another embodiment of the present invention. During processing of device160, the substrate has been removed, for example, by an etching step. In this illustrative embodiment, device160includes a topside contact16and a backside contact20. Topside contact16also functions as a reflector region. Backside contact20is formed on a transition layer15bhaving a constant composition. A compositionally-graded transition layer15ais formed on constant composition transition layer15b. Transition layers15a,15bare sufficiently conductive to enable conduction between topside contact16and backside contact20. In some cases, transition layers15a,15bmay be doped to achieve sufficient conductivity. It should also be understood that, in some embodiments, other transition layer arrangements are possible including those described above. In the illustrative embodiment, a topside of the device is mounted to a carrier162. Carrier162, for example, may be a wafer (e.g., silicon or GaAs). Carrier162provides support and rigidity for the device. It should be understood that in other embodiments carrier162may be mounted on a bottom side of the device. In other cases, a contact may be formed on the carrier.

It should be understood that light emitting device160may have any suitable layer arrangement including the layer arrangements (or a portion thereof) of the LED embodiments described herein.

Those skilled in the art would readily appreciate that all parameters listed herein are meant to be exemplary and that the actual parameters would depend upon the specific application for which the semiconductor materials and methods of the invention are used. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto the invention may be practiced otherwise than as specifically described.