Semiconductor device

Disclosed is a semiconductor device including a plurality of conductive patterns formed on a semiconductor substrate while being spaced apart from one another at a preset interval and extending in a first direction, and a plurality of junction areas formed by doping impurities in the semiconductor substrate and provided between the conductive patterns. The plurality of junction areas includes transistor junction areas and dummy junction areas. Each of the transistor junction areas is connected through a contact to a source/drain electrode, and the contact is formed at a higher level than the transistor junction areas. Each of the dummy junction areas is connected to a bias contact formed at higher level than the dummy junction areas. A well bias voltage is applied to the dummy junction areas through the bias contact.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2015-0120033, filed on Aug. 26, 2015 which is herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor device.

2. Related Art

A semiconductor device may be realized by configuring a circuit by connecting transistors to one another. When the semiconductor device is formed on a semiconductor substrate, a plurality of transistors, interconnections for connecting them to one another, and the like may be formed in repetitive patterns. The interconnections for a predetermined function are arranged and a dummy pattern is formed in a remaining area.

SUMMARY

Various embodiments are directed to a semiconductor device having improved operational stability for its transistors. The semiconductor device comprises a dummy pattern formed on a semiconductor substrate. A well bias voltage may also be provided through the dummy pattern. The invention allows further reductions in the size of semiconductor devices to be obtained.

In an embodiment, a semiconductor device may include a plurality of conductive patterns formed on a semiconductor substrate, spaced apart from one another at a preset interval and extending in a first direction, and a plurality of junction areas formed by doping impurities in the semiconductor substrate and provided between the conductive patterns. The plurality of junction areas includes transistor junction areas and dummy junction areas. Each of the transistor junction areas is connected through a contact to a source/drain electrode. The contact is formed at a higher level than the transistor junction areas. Each of the dummy junction areas is connected to a bias contact. The bias contact is formed at a higher level than the dummy junction areas. A well bias voltage is applied to the dummy junction areas through the dummy bias contact.

In an embodiment, a semiconductor device may include logic array areas including a transistors and a dummy area including a dummy active area and gate dummy patterns. Each of the transistors has an active area, a gate pattern, and a source and a drain. The gate pattern is formed over the active area, and each of the source and the drain is adjacent to the gate pattern. The dummy active area is formed between the logic array areas, and the gate dummy patterns are formed over the dummy active area. Each of the gate dummy patterns extends in a first direction, and the first direction is substantially the same as a direction in which the gate pattern extends. A well bias voltage is applied to the dummy active area.

According to the embodiments, since the semiconductor device does not include a separate guard ring in order to provide a well bias voltage and utilizes an existing dummy pattern for the purpose of the stabilization of patterns, it is possible to minimize an area required for realizing an entire circuit.

According to the embodiments, the semiconductor device utilizes an existing dummy pattern in order to apply a well bias voltage to transistors, and thus it is possible to easily ensure a space for interconnections for configuring a circuit through connections among the transistors.

DETAILED DESCRIPTION

Hereinafter, a semiconductor device will be described with reference to the accompanying drawings, according to various embodiments of the invention.

Referring toFIG. 1, the semiconductor device may include a plurality of conductive patterns111to117and121to129, respectively. The semiconductor device may also include a plurality of active areas131to133and135,141to143extending between the plurality of conductive patterns111to117and121to129. The plurality of active areas131to133,141to143may include junction areas located between the plurality of conductive patterns111to117and121to129. The junction areas may be doped with specific conductive impurities.

The plurality of conductive patterns111to117and121to129may be formed as elongated stripes or lines on a semiconductor substrate200, spaced apart from one another at a preset interval in a first direction X, and extending in a second direction Y that is perpendicular to the first direction X. The plurality of conductive patterns111to117and121to129may include first conductive patterns111to117and second conductive patterns121to129. The plurality of conductive patterns111to117and121to129may be formed with a polysilicon pattern or a metallic pattern, or by stacking polysilicon and a metal layer.

The plurality of first conductive patterns111to117may form gate patterns111to117which may be connected to gate electrodes.

The plurality of active areas131to133and135,141to143includes dummy active areas131to133and135and active areas141to143. In the active areas141to143where the gate patterns111to117are formed, transistor junction areas may be formed between the gate patterns111to117. The transistor junction areas may be connected to at least a source or a drain electrode through contacts171and172formed at the upper portions thereof, thereby defining a plurality of transistors together with the gate patterns111to117. Since the transistor may comprise various logic circuits, the gate patterns111to117and the transistor junction areas (that is, areas connected to at least a source or a drain electrode serving as sources and/or drains) adjacent to the gate patterns111to117may also be referred to hereinafter as logic array areas TR. For example, the transistor junction regions formed within the active areas141to143and located between the gate patterns111to117. (SeeFIGS. 2 and 3)

Some of the conductive patterns, for example the second conductive patterns may define gate dummy patterns121to129. Active areas formed below the gate dummy patterns121to129may be referred to as dummy active areas131to133and135. The dummy active areas131to133and135may include dummy junction areas doped with specific conductive impurities. According to an embodiment, the dummy junction areas may be doped with impurities having different conductivity from the impurities used for the transistor junction areas. For example, the dummy junction areas may be formed within the dummy active areas131to133and135and located between the gate dummy patterns121to129.

Areas of the semiconductor substrate200other than logic array areas TR may be filled with the gate dummy patterns121to129and the dummy active areas131to133and135. In this way stability of the pattern including structural and/or functional stability may be improved. Hereinafter, an area where a gate dummy pattern121to129and/or a dummy active area131to133and135is formed may also be referred to as a dummy area D.

A gate dummy pattern121to129and/or a dummy active area131to133and135may be a cell-like pattern.

A plurality of Dummy areas D may be formed between the logic array areas TR. Because the dummy areas D fills remained region of the logic array areas TR, the dummy areas D may provide stability to the entire semiconductor device. For example, the dummy areas D may support adjacent logic array areas TR. The entire semiconductor memory device may be designed with regularity by including the dummy areas D and the logic array areas TR which has substantially the same conductive patterns111to117and121to129. This is advantageous and may allow further reductions in the size of semiconductor devices. Reducing the size of existing semiconductor devices including only conductive patterns and not dummy patterns is limited by the need to space apart the conductive areas at a predetermined interval due to limitations in related exposure equipment employed for the fabrication of semiconductor devices. The present invention may overcome this limitation by adding a plurality of dummy areas D between the logic areas TR.

The dummy junction areas included in the semiconductor device according to an embodiment of the invention may receive a well bias voltage, for example through bias contacts161and162formed at the upper portions of the dummy junction areas.

For example, the well bias voltage may be applied through a dummy junction area included in the dummy area D. The gate dummy patterns121to129may be floated. It is noted, however, that the invention may not be limited in this way, For example, the gate dummy patterns121to129may not be floated that is, and any voltage is applied to the gate dummy patterns121to129.

Referring toFIG. 1, on the semiconductor substrate200, a PMOS area and a NMOS area are separately illustrated. For example, when the semiconductor substrate200is a P type substrate, the PMOS area may be formed on an N-WELL. A well bias voltage may be applied to all N-WELL areas through the well bias voltage provided through a bias contact161of the PMOS area. The well bias voltage may be applied to the entire semiconductor substrate200through the bias contact162of the NMOS area.

Accordingly, the logic array areas TR formed in the PMOS and NMOS areas may stably operate through a well bias voltage. Moreover, it is noted that additional elements are not required to provide the well bias voltage, and since it is possible to apply the well bias voltage through the dummy area D required for stabilizing patterns between the logic array areas TR, further reductions in the size of semiconductor devices may obtained.

The semiconductor substrate200may be or include any suitable material. For example, the semiconductor substrate200may include a silicon substrate, a SOI (Silicon on Insulator) substrate, a GaAs substrate, a SiGe substrate, a ceramic substrate, a quartz substrate, a glass substrate for display, and the like.

For example, when an N-WELL is formed by implanting n type impurities such as phosphorous (P) or arsenic (As) into the PMOS area of the semiconductor substrate200, the transistor junction areas included in the active areas141to143may be formed by implanting p type impurities. The dummy junction areas included in the dummy active areas131to133and135may be formed by implanting n type impurities.

The semiconductor device may include dummy connection patterns151to154which are formed in a direction crossing an extension direction of the gate dummy patterns121to129and connect the gate dummy patterns121to129to one another.

FIG. 2is a sectional view of the semiconductor device ofFIG. 1taken along line A-A′. Referring toFIG. 2, the dummy active area133, the active areas141and142, the gate patterns113to115, the gate dummy patterns127and128, the bias contact161, and a bias voltage pattern181are formed on the semiconductor substrate200.

The bias voltage pattern181is a pattern for providing a well bias voltage and may be formed at a position higher than the gate patterns113to115and the gate dummy patterns127and128.

A well bias voltage may be applied to the N-WELL through a dummy junction area1311formed in the dummy active area133via the bias voltage pattern181and bias contact161.

The transistor junction areas1411may be formed within the active area141and the transistor junction areas1421may be formed within the active area142.

According to various embodiments, the dummy junction area1331may not be formed in the dummy active area133, and the well bias voltage may be directly applied to the dummy active area133. Alternatively, the dummy active area133may correspond to the dummy isolation area.

FIG. 3is a sectional view of the semiconductor device ofFIG. 1, which is taken along line B-B′. Referring toFIG. 3, the dummy active area135, the active area143, the gate pattern117, the gate dummy patterns129, the bias contact162, and a bias voltage pattern182are formed on the semiconductor substrate200.

The well bias voltage applied through the bias voltage pattern182may be provided to the semiconductor substrate200through the bias contact162. More specifically, the well bias voltage may be applied through dummy junction area1351formed within the dummy active area135. The well bias voltage applied to the bias voltage pattern182may have a value different from that of the well bias voltage applied through the bias voltage pattern181ofFIG. 2.

According to various embodiments, the dummy junction area1351may not be formed in the dummy active area135, and thus the well bias voltage may be directly provided to the dummy active area135. For example, the transistor junction areas1431may be formed within the active area143.

The bias voltage pattern182may be formed at a position higher than the gate pattern117and the gate dummy patterns129.

FIG. 4is a plan view illustrating a semiconductor device according to an embodiment of the present invention.FIG. 4illustrates an embodiment in which a logic circuit is configured by connecting transistors of the transistor area TR formed inFIG. 3to one another.

The semiconductor device illustrated inFIG. 4includes additional elements compared with the semiconductor device illustrated inFIG. 3. Hereinafter, a detailed description of the configuration regarding the same elements as described inFIG. 3will be omitted.

The semiconductor device may include a plurality of conductive patterns111to117and121to129, respectively. The semiconductor device may also include a plurality of active areas131to133and135,141to143extending between the plurality of conductive patterns111to117and121to129. The plurality of active areas131to133and135,141to143may include junction areas located between the plurality of conductive patterns111to117and121to129. The junction areas may be doped with specific conductive impurities.

The semiconductor device may include dummy connection patterns151to154which are formed in a direction crossing an extension direction of the gate dummy patterns121to129and connect the gate dummy patterns121to129to one another.

The semiconductor device may include bias contacts161and162formed at the upper portions of the dummy junction regions formed within the dummy active areas131to133and135and located between the gate dummy patterns121to129. The semiconductor device may include contacts171and172which connect at least a source or drain electrodes formed in the transistor junction areas.

Referring toFIG. 4, a first connection pattern310is formed above the plurality of conductive patterns111to117and121to129shown inFIG. 3, and a second connection pattern190for connecting the gate patterns111to117to one another is formed.

The gate patterns111to117formed in the transistor area TR are connected to one another through the second connection pattern190, and the transistors formed in the NMOS area and the transistors formed in the PMOS area are connected to one another through the first connection pattern310, so that various logic circuits may be configured.

For example, the transistors may be connected to one another as illustrated inFIG. 4so that various logic circuits such as an inverter, a NAND, and a NOR may be configured.

While various embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the invention should not be limited based on the described embodiments and many more variations and embodiments may become apparent to those skilled in this art after having read the present disclosure without departing from the spirit and scope of the invention as defined by the appended claims.