Semiconductor device

A semiconductor device includes a semiconductor layer which has a first device formation region and a second device formation region, a first HEMT which is formed in the first device formation region and has a first two-dimensional electron gas region as a channel, a second HEMT which is formed in the second device formation region and has a second two-dimensional electron gas region as a channel, and a region separation structure which is formed in the semiconductor layer and defines the first device formation region and the second device formation region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Japanese Patent Application No. 2018-030901 filed on Feb. 23, 2018. The entire contents of the application are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device that includes a High Electron Mobility Transistor (HEMT).

2. Description of the Related Art

JP2011-192834A discloses a semiconductor device that includes a High Electron Mobility Transistor (HEMT). The semiconductor device includes a silicon substrate. A buffer layer is formed on the silicon substrate. A GaN layer is formed on the buffer layer. A gate electrode layer is formed on the GaN layer with a gate insulating layer interposed therebetween. A source electrode layer and a drain electrode layer are formed on the GaN layer with an AlGaN layer interposed therebetween.

SUMMARY OF THE INVENTION

A preferred embodiment of the present invention provides a semiconductor device that includes a semiconductor layer which has a first device formation region and a second device formation region, a first HEMT which is formed in the first device formation region and has a first two-dimensional electron gas region as a channel, a second HEMT which is formed in the second device formation region and has a second two-dimensional electron gas region as a channel, and a region separation structure which is formed in the semiconductor layer and defines the first device formation region and the second device formation region.

A preferred embodiment of the present invention provides a semiconductor device that includes a semiconductor layer which includes an electron transit layer, and an electron supply layer formed on the electron transit layer, a region separation structure which includes a trench penetrating the electron supply layer, and an embedded insulator embedded in the trench, the region separation structure separating the semiconductor layer into a first device formation region and a second device formation region, a first HEMT that is formed in the first device formation region and has a first two-dimensional electron gas region as a channel, and a second HEMT that is formed in the second device formation region and has a second two-dimensional electron gas region as a channel.

The aforementioned or other objects, features, and effects of the present invention will be clarified by the following description of preferred embodiments given below with reference to the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The semiconductor device according to JP2011-192834A may be formed as one HEMT chip. In a case in which a plurality of HEMT chips mount onto a connection object such as a mounting board, the plurality of HEMT chips must be arranged side by side. As a result, a total area occupied in the connection object by the HEMT chips is increased. In addition, in a case in which the HEMT chips are electrically connected together, a wiring distance between the HEMT chips is increased. This leads to problems such as increases in wiring resistance and wiring inductance.

A preferred embodiment of the present invention therefore provides a semiconductor device which has a plurality of HEMTs that can be independently controlled and which can be reduced in size and improved in performance.

A preferred embodiment of the present invention provides a semiconductor device that includes a semiconductor layer which has a first device formation region and a second device formation region, a first HEMT which is formed in the first device formation region and has a first two-dimensional electron gas region as a channel, a second HEMT which is formed in the second device formation region and has a second two-dimensional electron gas region as a channel, and a region separation structure which is formed in the semiconductor layer and defines the first device formation region and the second device formation region.

According to the semiconductor device, the first HEMT and the second HEMT that can be controlled independently each other have been incorporated into the single semiconductor layer. This enables the first HEMT and the second HEMT to be confined in a limited region of the semiconductor layer, thus making it possible to reduce the device in size.

Furthermore, in a case in which the first HEMT and the second HEMT are electrically connected to each other in the semiconductor device, a wiring to be connected to the first HEMT and the second HEMT can be confined in the limited region of the semiconductor layer. Since this enables shortening a wiring distance, a wiring resistance and a wiring inductance can be reduced. It is thus possible to provide a semiconductor device that can be improved in performance by taking advantage of the size reduction.

A preferred embodiment of the present invention provides a semiconductor device that includes a semiconductor layer which includes an electron transit layer, and an electron supply layer formed on the electron transit layer, a region separation structure which includes a trench penetrating the electron supply layer, and an embedded insulator embedded in the trench, the region separation structure separating the semiconductor layer into a first device formation region and a second device formation region, a first HEMT that is formed in the first device formation region and has a first two-dimensional electron gas region as a channel, and a second HEMT that is formed in the second device formation region and has a second two-dimensional electron gas region as a channel.

According to the semiconductor device, the first HEMT and the second HEMT that can be controlled independently each other have been incorporated into the single semiconductor layer. This enables the first HEMT and the second HEMT to be confined in a limited region of the semiconductor layer, thus making it possible to reduce the device in size.

Furthermore, in a case in which the first HEMT and the second HEMT are electrically connected to each other in the semiconductor device, a wiring to be connected to the first HEMT and the second HEMT can be confined in the limited region of the semiconductor layer. Since this enables shortening a wiring distance, a wiring resistance and a wiring inductance can be reduced. It is thus possible to provide a semiconductor device that can be improved in performance by taking advantage of the size reduction.

FIG. 1is a plan view showing a semiconductor device1according to a first preferred embodiment of the present invention.

Referring toFIG. 1, the semiconductor device1includes a chip body2that is formed in a rectangular parallelepiped shape. The chip body2includes a first chip main surface3on one side, a second chip main surface4on the other side, and four chip side surfaces5A,5B,5C, and5D which connect the first chip main surface3and the second chip main surface4. The first chip main surface3and the second chip main surface4are formed in a quadrangular shape (more specifically, in a rectangular shape) in plan view when viewed in a normal direction Z of the chip main surfaces (hereafter, simply referred to as “in plan view”).

The chip side surfaces5A and5C extend in a first direction X and oppose each other along a second direction Y that intersects the first direction X. The chip side surfaces5B and5D extend in the second direction Y and oppose each other along the first direction X. The first direction X is set to the longitudinal direction of the chip body2, in this preferred embodiment. The second direction Y is set to a direction orthogonal to the first direction X, that is, the transverse direction of the chip body2, in this preferred embodiment.

A plurality of external terminals to be externally connected are formed on the first chip main surface3of the chip body2. The plurality of external terminals include a source-drain external terminal6, a first gate external terminal7, a drain external terminal8, a second gate external terminal9, and a source external terminal10.

The source-drain external terminal6is formed in a central portion of the first chip main surface3, in this preferred embodiment. The source-drain external terminal6is formed in a band shape that extends along the second direction Y in plan view.

The first gate external terminal7is formed in a region along a corner portion in the first chip main surface3, in this preferred embodiment. More specifically, the first gate external terminal7is formed at a region along a corner portion that connects the chip side surface5A and the chip side surface5B in the first chip main surface3.

The first gate external terminal7is formed in a quadrangular shape (more specifically, in a square shape) in plan view. The first gate external terminal7may be formed in a band shape that extends along the second direction Y in plan view.

The drain external terminal8is formed in a region at one end portion side of the first chip main surface3in regard to the first direction X, in this preferred embodiment. More specifically, the drain external terminal8is formed in a region at the chip side surface5B side in the first chip main surface3. The drain external terminal8is formed in a band shape that extends along the second direction Y in plan view.

The second gate external terminal9is formed in a region along a corner portion in the first chip main surface3, in this preferred embodiment. More specifically, the second gate external terminal9is formed in a region along a corner portion that connects the chip side surface5C and the chip side surface5D in the first chip main surface3. The second gate external terminal9opposes the first gate external terminal7along a diagonal direction of the first chip main surface3.

The second gate external terminal9is formed in a quadrangular shape (more specifically, in a square shape) in plan view. The second gate external terminal9may be formed in a band shape that extends along the second direction Y in plan view.

The source external terminal10is formed in a region at the other end portion side of the first chip main surface3in regard to the first direction X, in this preferred embodiment. More specifically, the source external terminal10is formed in a region at the chip side surface5D side of the first chip main surface3. The source external terminal10is formed in a band shape that extends along the second direction Y in plan view.

The source external terminal10opposes the drain external terminal8in the first direction X with the source-drain external terminal6interposed between the source external terminal10and the drain external terminal8. The source-drain external terminal6, the drain external terminal8, and the source external terminal10are formed in a stripe shape that extends along the second direction Y in plan view.

FIG. 2is a cross-sectional view taken along line II-II shown inFIG. 1.FIG. 3is a cross-sectional view taken along line shown inFIG. 1.FIG. 4is a cross-sectional view taken along line IV-IV shown inFIG. 1.FIG. 5is a cross-sectional view taken along line V-V shown inFIG. 1.FIG. 6is a cross-sectional view taken along line VI-VI shown inFIG. 1.FIG. 7is an enlarged view of region VII shown inFIG. 2.FIG. 8is an enlarged view of region VIII shown inFIG. 2.

Referring toFIG. 2toFIG. 6, the chip body2includes a substrate11, and a laminated structure portion12formed on the substrate11. The substrate11may be a Si substrate, a SiC substrate, a sapphire substrate, a GaN substrate, or the like. The substrate11consists of the Si substrate, in this preferred embodiment.

The substrate11includes a first main surface13on one side, a second main surface14on the other side, and four side surfaces15A,15B,15C, and15D that connect the first main surface13and the second main surface14. The normal direction of the first main surface13and the second main surface14coincides with the normal direction Z. Thus, the plan view aforementioned is also a plan view when viewed in the normal direction Z to the first main surface13and the second main surface14.

The first main surface13and the second main surface14have a planar shape that is aligned with the planar shape of the chip body2in plan view. The second main surface14of the substrate11forms the second chip main surface4. The side surfaces15A to15D form parts of the chip side surfaces5A to5D, respectively.

The laminated structure portion12includes a core formation layer21, a buffer layer22, an electron transit layer23, an electron supply layer24, and a top insulating layer25, which are formed in that order from the first main surface13of the substrate11. The laminated structure portion12is formed by an epitaxial layer that is formed on the first main surface13by an epitaxial growth method. The core formation layer21, the buffer layer22, the electron transit layer23, and the electron supply layer24in the laminated structure portion12define a semiconductor laminated structure portion26(semiconductor layer).

The core formation layer21is formed on the first main surface13. The core formation layer21includes an AlN layer. The core formation layer21may have a thickness of 100 nm or more and 300 nm or less. The core formation layer21may have a thickness of 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, or 250 nm or more and 300 nm or less. The core formation layer21has a thickness of approximately 200 nm, in this preferred embodiment.

The buffer layer22is formed on the core formation layer21. The buffer layer22includes an AlGaN layer. The buffer layer22may have a thickness of 100 nm or more and 300 nm or less. The buffer layer22may have a thickness of 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, or 250 nm or more and 300 nm or less. The buffer layer22has a thickness of approximately 200 nm, in this preferred embodiment.

The buffer layer22may have a laminated structure in which a plurality of (two or more) AlGaN layers having different Al composition ratios are laminated. The buffer layer22may have a plurality of (two or more) AlGaN layers that are laminated on the core formation layer21in an order in which the Al composition ratios gradually decrease toward a laminating direction.

The electron transit layer23includes AlxInyGa(1−x−y)N (0≤x+y≤1). The electron transit layer23consists of GaN, in this preferred embodiment. The electron transit layer23may have a thickness of 50 nm or more and 300 nm or less. The electron transit layer23may have a thickness of 50 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, or 250 nm or more and 300 nm or less. The electron transit layer23has a thickness of approximately 200 nm, in this preferred embodiment.

The electron transit layer23may include an undoped AlxInyGa(1−x−y)N (GaN in this preferred embodiment). The electron transit layer23may include AlxInyGa (1−x−y)N (GaN in this preferred embodiment) doped with carbon as an impurity.

The electron supply layer24is formed on the electron transit layer23. The electron supply layer24includes a nitride semiconductor having an Al composition ratio z that is different from the Al composition ratio x of the electron transit layer23. The electron supply layer24has the Al composition ratio z that is greater than the Al composition ratio x of the electron transit layer23.

More specifically, the electron supply layer24includes a barrier layer27and a cap layer28. The barrier layer27includes AlzGa(1−z)N (0<z≤1). The barrier layer27consists of AlN, in this preferred embodiment. The barrier layer27may have a thickness of 1 nm or more and 5 nm or less. The barrier layer27may have a thickness of 1 nm or more and 2 nm or less, 2 nm or more and 3 nm or less, 3 nm or more and 4 nm or less, or 4 nm or more and 5 nm or less. The barrier layer27has a thickness of approximately 2 nm, in this preferred embodiment.

The cap layer28is formed on the barrier layer27. The cap layer28is formed to improve the flatness of a region on the barrier layer27. The cap layer28may include GaN.

The cap layer28may have a thickness of 0.5 nm or more and 5 nm or less. The cap layer28may have a thickness of 0.5 nm or more and 1 nm or less, 1 nm or more and 2 nm or less, 2 nm or more and 3 nm or less, 3 nm or more and 4 nm or less, or 4 nm or more and 5 nm or less. The cap layer28has a thickness of approximately 1 nm, in this preferred embodiment. The cap layer28may have a thickness that is equal to or less than the thickness of the barrier layer27.

The electron supply layer24has the Al composition ratio z that is greater than the Al composition ratio x of the electron transit layer23. A lattice constant of the electron supply layer24is less than a lattice constant of the electron transit layer23. This causes a lattice mismatch between the electron supply layer24and the electron transit layer23. Furthermore, the electron supply layer24has a tensile strain occurring along a direction parallel to a growth surface of the electron supply layer24.

In a boundary region between the electron transit layer23and the electron supply layer24, an energy level of a conduction band of the electron transit layer23is equal to or less than a Fermi level due to a spontaneous polarization of the electron transit layer23and the electron supply layer24and due to a piezo polarization caused by the lattice mismatch between the electron transit layer23and the electron supply layer24. Thus, a two-dimensional electron gas region29is formed in a surface layer portion of the electron transit layer23in the boundary region between the electron transit layer23and the electron supply layer24. InFIG. 2toFIG. 6, the two-dimensional electron gas region29is shown by a broken line.

The top insulating layer25is formed on the electron supply layer24. The top insulating layer25includes an SiN layer. The top insulating layer25is also referred to as a passivation layer. The top insulating layer25may have a thickness of 1 nm or more and 30 nm or less. The top insulating layer25may have a thickness of 1 nm or more and 10 nm or less, 10 nm or more and 20 nm or less, or 20 nm or more and 30 nm or less. The top insulating layer25has a thickness of approximately 10 nm, in this preferred embodiment.

A first device formation region31and a second device formation region32are defined in the laminated structure portion12. A first HEMT (High Electron Mobility Transistor)33is formed in the first device formation region31. A second HEMT34is formed in the second device formation region32.

The first device formation region31is defined in a region at one end portion side of the laminated structure portion12in regard to the first direction X, in this preferred embodiment. More specifically, the first device formation region31is defined in a region at the side surface15B side in the laminated structure portion12.

The first device formation region31is formed in a quadrangular shape (a square shape in this preferred embodiment) having four sides parallel to the side surfaces15A to15D in plan view. The planar shape of the first device formation region31is arbitrary and not limited to the quadrangular shape. The first device formation region31may be defined in a polygonal shape, circular shape, elliptical shape, or the like in plan view.

The second device formation region32is defined in a region at the other end portion side of the laminated structure portion12in regard to the first direction X, in this preferred embodiment. More specifically, the second device formation region32is defined in a region at the side surface15D side in the laminated structure portion12.

The second device formation region32is defined in a quadrangular shape (a square shape in this preferred embodiment) having four sides parallel to the side surfaces15A to15D in plan view. The planar shape of the second device formation region32is arbitrary and not limited to the quadrangular shape. The second device formation region32may be defined in a polygonal shape, circular shape, elliptical shape, or the like in plan view.

A region separation structure35that defines the first device formation region31and the second device formation region32is formed in the laminated structure portion12. Hereinafter, referring also toFIG. 9, a mode of the region separation structure35shall be described.FIG. 9is a plan view for explaining the mode of the laminated structure portion12with structures above the laminated structure portion12being removed.

Referring toFIG. 2toFIG. 9, the region separation structure35is formed in a region between the first device formation region31and the second device formation region32, and separates the first device formation region31and the second device formation region32from each other.

More specifically, the region separation structure35includes a first region separation structure35A and a second region separation structure35B. The first region separation structure35A is formed in an endless shape (an annular quadrangular shape in this preferred embodiment) surrounding the first device formation region31in plan view. The second region separation structure35B is formed in an endless shape (an annular quadrangular shape in this preferred embodiment) surrounding the second device formation region32in plan view. The first region separation structure35A and the second region separation structure35B communicate with each other in a region between the first device formation region31and the second device formation region32.

The region separation structure35includes a region separation trench36, and an embedded insulator37embedded in the region separation trench36. The region separation trench36penetrates the electron supply layer24from the main surface of the laminated structure portion12and exposes the electron transit layer23.

The region separation trench36has sidewalls and a bottom wall. The top insulating layer25, the electron supply layer24and the electron transit layer23are exposed from the sidewalls of the region separation trench36. The electron transit layer23is exposed from the bottom wall of the region separation trench36.

The region separation trench36divides the two-dimensional electron gas region29into a first two-dimensional electron gas region29A of the first device formation region31side and a second two-dimensional electron gas region29B of the second device formation region32side. The first HEMT33operates with the first two-dimensional electron gas region29A as a channel. The second HEMT34operates with the second two-dimensional electron gas region29B as a channel.

The region separation trench36is formed in a tapered shape that has an opening area greater than a bottom area. A portion along the peripheral edge of the substrate11in the bottom wall of the region separation trench36communicates with the side surfaces15A to15D, in this preferred embodiment.

The region separation trench36may have a depth of 3 nm or more and 100 nm or less. The depth of the region separation trench36is the distance along the normal direction Z between the main surface of the laminated structure portion12and the bottom wall of the region separation trench36. The region separation trench36may have a depth of 3 nm or more and 20 nm or less, 20 nm or more and 40 nm or less, 40 nm or more and 60 nm or less, 60 nm or more and 80 nm or less, or 80 nm or more and 100 nm or less. The region separation trench36has a depth of approximately 60 nm, in this preferred embodiment.

The first device formation region31has an inclined surface that is downwardly inclined from the main surface of the laminated structure portion12toward the bottom wall of the region separation trench36. Thus, the first device formation region31is formed in a frustum shape (a truncated square pyramidal shape in this preferred embodiment). The second device formation region32has an inclined surface that is downwardly inclined from the main surface of the laminated structure portion12toward the bottom wall of the region separation trench36. Thus, the second device formation region32is formed in a frustum shape (a truncated square pyramidal shape in this preferred embodiment).

The embedded insulator37enhances insulation properties of the first two-dimensional electron gas region29A and the second two-dimensional electron gas region29B. The embedded insulator37has a laminated structure in which a plurality of insulating layers are laminated. The specific structure of the embedded insulator37will be described later.

Referring toFIG. 2toFIG. 8, a protection layer40made of an insulator is formed on the laminated structure portion12. The protection layer40is formed in a film shape along the main surface of the laminated structure portion12and an inner wall of the region separation trench36. The protection layer40defines a recessed space in the region separation trench36.

The protection layer40has a laminated structure that includes a first protection layer41and a second protection layer42, in this preferred embodiment. The first protection layer41is formed in a film shape along the main surface of the laminated structure portion12and the inner wall of the region separation trench36. The second protection layer42is formed in a film shape along the main surface of the first protection layer41.

The first protection layer41may have a thickness of 10 nm or more and 100 nm or less. The first protection layer41may have a thickness of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, or 75 nm or more and 100 nm or less. The first protection layer41has a thickness of approximately 40 nm, in this preferred embodiment.

The second protection layer42may have a thickness of 50 nm or more and 200 nm or less. The second protection layer42may have a thickness of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, or 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, or 175 nm or more and 200 nm or less. The thickness of the second protection layer42may be equal to or greater than the thickness of the first protection layer41. The second protection layer42has a thickness of approximately 100 nm, in this preferred embodiment.

The first protection layer41may include at least one of SiO2 and SiN. The second protection layer42may include at least one of SiO2 and SiN.

The second protection layer42may have an insulation material having a property that is different from a property of the first protection layer41. For example, the first protection layer41may include CVD-SiO2 formed by a CVD method, while the second protection layer42may include TEOS-SiO2 formed by a plasma CVD method.

A first source opening45, a first drain opening46, a second source opening47, and a second drain opening48are formed in the protection layer40and the top insulating layer25.

The first source opening45and the first drain opening46are formed in the first device formation region31. The first source opening45and the first drain opening46are formed to be spaced apart from each other along the first direction X. The first source opening45and the first drain opening46extend in band shapes along the second direction Y. The first source opening45and the first drain opening46penetrate the protection layer40and the top insulating layer25such as to expose the electron supply layer24.

The second source opening47and the second drain opening48are formed in the second device formation region32. The second source opening47and the second drain opening48are formed to be spaced apart from each other along the first direction X. The second source opening47and the second drain opening48extend in band shapes along the second direction Y. The second source opening47and the second drain opening48penetrate the protection layer40and the top insulating layer25such as to expose the electron supply layer24.

A first source electrode51and a first drain electrode52are formed in the first device formation region31. The first source electrode51is embedded in the first source opening45, and the first drain electrode52is embedded in the first drain opening46.

A second source electrode53and a second drain electrode54are formed in the second device formation region32. The second source electrode53is embedded in the second source opening47, and the second drain electrode54is embedded in the second drain opening48.

Hereinafter, referring also toFIG. 10, modes of the first source electrode51, the first drain electrode52, the second source electrode53, and the second drain electrode54shall be described.FIG. 10is a plan view with structures above the first source electrode51, the first drain electrode52, the second source electrode53, and the second drain electrode54being removed.

Referring toFIG. 10, the first source electrode51and the first drain electrode52are formed to be spaced apart from each other along the first direction X, in this preferred embodiment. The first source electrode51and the first drain electrode52extend in band shapes along the second direction Y.

The second source electrode53and the second drain electrode54are formed to be spaced apart from each other along the first direction X, in this preferred embodiment. The second source electrode53and the second drain electrode54extend in band shapes along the second direction Y.

Referring toFIG. 2toFIG. 8(particularly,FIG. 7), the first source electrode51includes an embedded electrode layer61and a cover electrode layer62. The embedded electrode layer61is embedded in the first source opening45. The cover electrode layer62covers the embedded electrode layer61. The embedded electrode layer61has a laminated structure that includes a first embedded electrode layer63and a second embedded electrode layer64, in this preferred embodiment.

The first embedded electrode layer63is formed in a film shape along an inner wall of the first source opening45. The first embedded electrode layer63defines a recessed space in the first source opening45. The first embedded electrode layer63is formed as a barrier electrode layer, in this preferred embodiment. The first embedded electrode layer63may include at least one of Ti and TiN. The first embedded electrode layer63consists of a Ti layer, in this preferred embodiment.

The first embedded electrode layer63may have a thickness of 10 nm or more and 30 nm or less. The first embedded electrode layer63may have a thickness of 10 nm or more and 15 nm or less, 15 nm or more and 20 nm or less, 20 nm or more and 25 nm or less, or 25 nm or more and 30 nm or less. The first embedded electrode layer63has a thickness of approximately 20 nm, in this preferred embodiment.

The second embedded electrode layer64is embedded in the first source opening45with the first embedded electrode layer63interposed between the second embedded electrode layer64and the first source opening45. The second embedded electrode layer64may include at least one of Al, Si and Cu. The second embedded electrode layer64may include at least one of a conductive poly-Si layer, an AlSiCu alloy layer, and an AlCu alloy layer. The second embedded electrode layer64consists of the AlCu alloy layer, in this preferred embodiment.

The second embedded electrode layer64may have a thickness of 1500 nm or more and 2500 nm or less. The second embedded electrode layer64may have a thickness of 1500 nm or more and 1750 nm or less, 1750 nm or more and 2000 nm or less, 2000 nm or more and 2250 nm or less, or 2250 nm or more and 2500 nm or less. The thickness of the second embedded electrode layer64is equal to or greater than the thickness of the first embedded electrode layer63. The second embedded electrode layer64has a thickness of approximately 2000 nm, in this preferred embodiment.

The cover electrode layer62covers the embedded electrode layer61on the protection layer40. The cover electrode layer62overlaps an opening edge portion of the first source opening45. More specifically, the cover electrode layer62overlaps the protection layer40. The cover electrode layer62is formed as a barrier electrode layer, in this preferred embodiment.

The cover electrode layer62has a laminated structure that includes a first cover electrode layer65and a second cover electrode layer66laminated in that order from the embedded electrode layer61side, in this preferred embodiment. The cover electrode layer62may have a single-layer structure that includes only either one of the first cover electrode layer65and the second cover electrode layer66.

The first cover electrode layer65includes a Ti layer, in this preferred embodiment. The first cover electrode layer65may have a thickness of 10 nm or more and 30 nm or less. The first cover electrode layer65may have a thickness of 10 nm or more and 15 nm or less, 15 nm or more and 20 nm or less, 20 nm or more and 25 nm or less, or 25 nm or more and 30 nm or less. The first cover electrode layer65has a thickness of approximately 20 nm, in this preferred embodiment.

The second cover electrode layer66includes a TiN layer, in this preferred embodiment. The second cover electrode layer66may have a thickness of 10 nm or more and 100 nm or less. The second cover electrode layer66may have a thickness of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, or 75 nm or more and 100 nm or less. The thickness of the second cover electrode layer66may be equal to or greater than the thickness of the first cover electrode layer65. The second cover electrode layer66has a thickness of approximately 50 nm, in this preferred embodiment.

The first drain electrode52, the second source electrode53, and the second drain electrode54each have a structure similar to the structure of the first source electrode51. The description for the first source electrode51is applied mutatis mutandis to the descriptions for the first drain electrode52, the second source electrode53, and the second drain electrode54, respectively. The structures corresponding to the structure of the first source electrode51in the first drain electrode52, the second source electrode53, and the second drain electrode54will be given the same reference symbols and descriptions thereof will be omitted.

Referring toFIG. 2toFIG. 8, a first interlayer insulating layer71is formed on the protection layer40. A main surface of the first interlayer insulating layer71may be a ground surface. The first interlayer insulating layer71may include at least one of SiO2 and SiN.

The first interlayer insulating layer71may have a thickness of 200 nm or more and 1000 nm or less. The first interlayer insulating layer71may have a thickness of 200 nm or more and 500 nm or less, 500 nm or more and 750 nm or less, or 750 nm or more and 1000 nm or less. The first interlayer insulating layer71has a thickness of approximately 500 nm, in this preferred embodiment.

The first interlayer insulating layer71is formed in a film shape along a main surface of the protection layer40. The first interlayer insulating layer71enters the recessed space defined by the protection layer40in the region separation trench36.

An insulation laminated structure that includes the protection layer40and the first interlayer insulating layer71laminated in that order from the bottom wall side of the region separation trench36is thus formed in the region separation trench36. The embedded insulator37is formed by the insulation laminated structure.

That is, the embedded insulator37has an insulation laminated structure in which a plurality of insulating layers are laminated. The first device formation region31and the second device formation region32are insulated from each other by the embedded insulator37that includes the insulation laminated structure.

A first gate opening72and a second gate opening73are formed in the first interlayer insulating layer71, the protection layer40, the top insulating layer25, and the electron supply layer24.

The first gate opening72is formed in the first device formation region31. The first gate opening72is formed in a region between the first source opening45and the first drain opening46. The first gate opening72is formed to be spaced apart from the first source opening45and the first drain opening46along the first direction X, in this preferred embodiment.

In regard to the first direction X, a distance between the first gate opening72and the first source opening45is less than a distance between the first gate opening72and the first drain opening46. The first gate opening72may be formed in a band shape that extends along the second direction Y in plan view.

The first gate opening72penetrates the first interlayer insulating layer71, the protection layer40, the top insulating layer25, and the electron supply layer24such as to expose the electron transit layer23. A formation of the first two-dimensional electron gas region29A is suppressed at a portion exposed from the bottom wall of the first gate opening72in the electron transit layer23. The first HEMT33is thus formed as a normally OFF type device.

The first gate opening72, more specifically, includes a first gate contact hole74and a first through hole75. The first gate contact hole74is formed in the electron supply layer24such as to expose the electron transit layer23. The first through hole75is formed in the first interlayer insulating layer71, the protection layer40, and the top insulating layer25such as to communicate with the first gate contact hole74.

The second gate opening73is formed in the second device formation region32. The second gate opening73is formed in a region between the second source opening47and the second drain opening48. The second gate opening73is formed to be spaced apart from the second source opening47and the second drain opening48along the first direction X, in this preferred embodiment.

In the first direction X, a distance between the second gate opening73and the second source opening47is less than a distance between the second gate opening73and the second drain opening48. The second gate opening73may be formed in a band shape that extends along the second direction Y in plan view.

The second gate opening73penetrates the first interlayer insulating layer71, the protection layer40, the top insulating layer25, and the electron supply layer24such as to expose the electron transit layer23. A formation of the second two-dimensional electron gas region29B is suppressed at a portion exposed from the bottom wall of the second gate opening73in the electron transit layer23. The second HEMT34is thus formed as a normally OFF type device.

The second gate opening73, more specifically, includes a second gate contact hole76and a second through hole77. The second gate contact hole76is formed in the electron supply layer24such as to expose the electron transit layer23. The second through hole77is formed in the first interlayer insulating layer71, the protection layer40, and the top insulating layer25such as to communicate with the second gate contact hole76.

A first gate insulating layer81and a first gate electrode82is formed in the first device formation region31. The first gate insulating layer81is formed in a film shape along an inner wall of the first gate opening72. The first gate insulating layer81defines a recessed space in the first gate opening72. The first gate electrode82is embedded in the first gate opening72with the first gate insulating layer81interposed between the first gate electrode82and the first gate opening72. The first gate electrode82is embedded in the recessed space defined by the first gate insulating layer81in the first gate opening72.

A second gate insulating layer83and a second gate electrode84are formed in the second device formation region32. The second gate insulating layer83is formed in a film shape along an inner wall of the second gate opening73. The second gate insulating layer83defines a recessed space in the second gate opening73. The second gate electrode84is embedded in the second gate opening73with the second gate insulating layer83interposed between the second gate electrode84and the second gate opening73. The second gate electrode84is embedded in the recessed space defined by the second gate insulating layer83in the second gate opening73.

Hereinafter, modes of the first gate electrode82and the second gate electrode84will be described.FIG. 11is a plan view with structures above the first gate electrode82and the second gate electrode84being removed.

Referring toFIG. 11, the first gate electrode82is formed in a region between the first source electrode51and the first drain electrode52. The first gate electrode82is formed to be spaced apart from the first source electrode51and the first drain electrode52along the first direction X.

In the first direction X, a distance between the first gate electrode82and the first source electrode51is less than a distance between the first gate electrode82and the first drain electrode52. The first gate electrode82extends in a band shape along the second direction Y.

The second gate electrode84is formed in a region between the second source electrode53and the second drain electrode54. The second gate electrode84is formed to be spaced apart from the second source electrode53and the second drain electrode54along the first direction X.

In the first direction X, a distance between the second gate electrode84and the second source electrode53is less than a distance between the second gate electrode84and the second drain electrode54. The second gate electrode84extends in a band shape along the second direction Y.

Referring toFIG. 2toFIG. 8(particularly,FIG. 8), a main surface insulating layer85is formed on a main surface of the first interlayer insulating layer71. The main surface insulating layer85covers the main surface of the first interlayer insulating layer71. The main surface insulating layer85communicates with the first gate insulating layer81and the second gate insulating layer83.

That is, an insulating layer86that integrally includes the first gate insulating layer81, the second gate insulating layer83, and the main surface insulating layer85is formed on the first interlayer insulating layer71. The first gate insulating layer81, the second gate insulating layer83, and the main surface insulating layer85may each include at least one of SiO2 and SiN.

The first gate insulating layer81, the second gate insulating layer83, and the main surface insulating layer85may each have a thickness of 1 nm or more and 100 nm or less. The first gate insulating layer81, the second gate insulating layer83, and the main surface insulating layer85may each have a thickness of 1 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, or 75 nm or more and 100 nm or less. The first gate insulating layer81, the second gate insulating layer83and the main surface insulating layer85have a thickness of approximately 20 nm, in this preferred embodiment.

The first gate electrode82includes an embedded electrode layer91and a cover electrode layer92. The embedded electrode layer91is embedded in the first gate opening72. The cover electrode layer92covers the embedded electrode layer91.

The embedded electrode layer91has a laminated structure that includes a first embedded electrode layer93and a second embedded electrode layer94, in this preferred embodiment. The first embedded electrode layer93is formed in a film shape along the inner wall of the first gate opening72. The first embedded electrode layer93defines a recessed space in the first gate opening72.

The first embedded electrode layer93is formed as a barrier electrode layer, in this preferred embodiment. The first embedded electrode layer93may include at least one of Ti and TiN. The first embedded electrode layer93consists of a TiN layer, in this preferred embodiment.

The first embedded electrode layer93may have a thickness of 50 nm or more and 200 nm or less. The first embedded electrode layer93may have a thickness of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, or 175 nm or more and 200 nm or less. The first embedded electrode layer93has a thickness of approximately 100 nm, in this preferred embodiment.

The second embedded electrode layer94is embedded in the first gate opening72with the first embedded electrode layer93interposed between the second embedded electrode layer94and the first gate opening72. The second embedded electrode layer94is embedded in the recessed space defined by the first embedded electrode layer93in the first gate opening72. The second embedded electrode layer94includes a W (tungsten) layer, in this preferred embodiment.

The second embedded electrode layer94may have a thickness of 100 nm or more and 1000 nm or less. The second embedded electrode layer94may have a thickness of 100 nm or more and 250 nm or less, 250 nm or more and 500 nm or less, 500 nm or more and 750 nm or less, or 750 nm or more and 1000 nm or less. The thickness of the second embedded electrode layer94may be equal to or greater than the thickness of the first embedded electrode layer93. The second embedded electrode layer94has a thickness of approximately 500 nm, in this preferred embodiment.

The cover electrode layer92covers the embedded electrode layer91on the main surface insulating layer85. The cover electrode layer92overlaps an opening edge portion of the first gate opening72. More specifically, the cover electrode layer92overlaps the main surface insulating layer85.

The cover electrode layer92has a laminated structure that includes a first cover electrode layer95and a second cover electrode layer96laminated in that order from the embedded electrode layer91side, in this preferred embodiment. The cover electrode layer92may include only either one of the first cover electrode layer95and the second cover electrode layer96.

The first cover electrode layer95may include at least one of Al, Si, and Cu. The first cover electrode layer95may include at least one of a conductive Poly-Si layer, an AlSiCu alloy layer, and an AlCu alloy layer. The first cover electrode layer95consists of the AlCu alloy layer, in this preferred embodiment.

The first cover electrode layer95may have a thickness of 100 nm or more and 1000 nm or less. The first cover electrode layer95may have a thickness of 100 nm or more and 250 nm or less, 250 nm or more and 500 nm or less, 500 nm or more and 750 nm or less, or 750 nm or more and 1000 nm or less. The first cover electrode layer95has a thickness of approximately 500 nm, in this preferred embodiment.

The second cover electrode layer96is formed as a barrier electrode layer, in this preferred embodiment. The second cover electrode layer96may include at least one of Ti and TiN. The second cover electrode layer96consists of a TiN layer, in this preferred embodiment.

The second cover electrode layer96may have a thickness of 10 nm or more and 100 nm or less. The second cover electrode layer96may have a thickness of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, or 75 nm or more and 100 nm or less. The thickness of the second cover electrode layer96may be equal to or less than the thickness of the first cover electrode layer95. The second cover electrode layer96has a thickness of approximately 50 nm, in this preferred embodiment.

The second gate electrode84has a structure similar to the structure of the first gate electrode82. The description for the first gate electrode82is applied mutatis mutandis to the description for the second gate electrode84. The structures corresponding to the structure of the first gate electrode82in the second gate electrode84will be given the same reference symbols and descriptions thereof will be omitted.

Referring toFIG. 2toFIG. 8, a first source field electrode layer101and a first floating electrode layer102is formed in the first device formation region31. The first source field electrode layer101and the first floating electrode layer102relieve an electric field with respect to the first gate electrode82.

The first source field electrode layer101is formed in a region between the first source electrode51and the first gate electrode82. The first source field electrode layer101is formed to be spaced apart from the first source electrode51and the first gate electrode82along the first direction X. The first source field electrode layer101is formed closer to the first gate electrode82than the first source electrode51. The first source field electrode layer101may extend in a band shape along the second direction Y. A reference voltage (e.g., a source voltage or a ground voltage) is applied to the first source field electrode layer101.

The first floating electrode layer102is formed in a region between the first drain electrode52and the first gate electrode82. The first source field electrode layer101is formed to be spaced apart from the first drain electrode52and the first gate electrode82along the first direction X. The first floating electrode layer102is formed closer to the first gate electrode82than the first drain electrode52. The first floating electrode layer102may extend in a band shape along the second direction Y. The first floating electrode layer102is formed in an electrically floating state.

The first source field electrode layer101and the first floating electrode layer102oppose each other along the first direction X with the first gate electrode82interposed between the source field electrode layer101and the first floating electrode layer102. The first source field electrode layer101and the first floating electrode layer102are formed in the protection layer40, in this preferred embodiment. More specifically, the first source field electrode layer101and the first floating electrode layer102are interposed in a region between the first protection layer41and the second protection layer42.

A second source field electrode layer103and a second floating electrode layer104are formed in the second device formation region32. The second source field electrode layer103and the second floating electrode layer104relieve an electric field with respect to the second gate electrode84.

The second source field electrode layer103is formed in a region between the second source electrode53and the second gate electrode84. The second source field electrode layer103is formed to be spaced apart from the second source electrode53and the second gate electrode84in the first direction X. The second source field electrode layer103is formed closer to the second gate electrode84than the second source electrode53. The second source field electrode layer103may extend in a band shape along the second direction Y. A reference voltage (e.g., a source voltage or a ground voltage) is applied to the second source field electrode layer103.

The second floating electrode layer104is formed in a region between the second drain electrode54and the second gate electrode84. The second floating electrode layer104is formed to be spaced apart from the second drain electrode54and the second gate electrode84in the first direction X. The second floating electrode layer104is formed closer to the second gate electrode84than the second drain electrode54. The second floating electrode layer104may extend in a band shape along the second direction Y. The second floating electrode layer104is formed in an electrically floating state.

The second source field electrode layer103and the second floating electrode layer104oppose each other in the first direction X with the second gate electrode84interposed between the second source field electrode layer103and the second floating electrode layer104. The second source field electrode layer103and the second floating electrode layer104are formed in the protection layer40, in this preferred embodiment. More specifically, the second source field electrode layer103and the second floating electrode layer104are interposed in a region between the first protection layer41and the second protection layer42.

The first source field electrode layer101, the first floating electrode layer102, the second source field electrode layer103, and the second floating electrode layer104may include a conductive material of the same type.

The first source field electrode layer101, the first floating electrode layer102, the second source field electrode layer103, and the second floating electrode layer104may include at least one of Ti and TiN. The first source field electrode layer101, the first floating electrode layer102, the second source field electrode layer103, and the second floating electrode layer104respectively consists of a TiN layer, in this preferred embodiment.

The first floating electrode layer102, the first source field electrode layer101, the second floating electrode layer104, and the second source field electrode layer103may have a thickness of 50 nm or more and 200 nm or less.

The first floating electrode layer102, the first source field electrode layer101, the second floating electrode layer104, and the second source field electrode layer103may have a thickness of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, or 175 nm or more and 200 nm or less.

The first floating electrode layer102, the first source field electrode layer101, the second floating electrode layer104, and the second source field electrode layer103have a thickness of approximately 100 nm, in this preferred embodiment.

The first floating electrode layer102, the first source field electrode layer101, the second floating electrode layer104, and the second source field electrode layer103may be the substantially same in thickness.

Referring toFIG. 2toFIG. 8(particularly,FIG. 8), an opening portion of the first gate opening72is defined by a first sidewall insulating layer105in the first device formation region31. The first sidewall insulating layer105defines an inner wall of the first through hole75. The first sidewall insulating layer105extends from the opening portion of the first gate opening72toward the bottom wall of the first gate opening72.

The first sidewall insulating layer105is interposed in a region between the first gate insulating layer81and the first source field electrode layer101and in a region between the first gate insulating layer81and the first floating electrode layer102such as to be connected to the protection layer40(the first protection layer41). The first sidewall insulating layer105may penetrate the first protection layer41such as to be connected to the electron supply layer24.

An upper end portion of the first sidewall insulating layer105is R-chamfered. The upper end portion of the first sidewall insulating layer105is formed in a convexly curved shape toward an inner side of the first gate opening72. The upper end portion of the first sidewall insulating layer105is a portion located at the opening portion side of the first gate opening72in the first sidewall insulating layer105.

An opening area of the first gate opening72is greater than a bottom area of the first gate opening72. The first gate insulating layer81and the first gate electrode82enter the first gate opening72along a curved surface of the first sidewall insulating layer105.

An opening portion of the second gate opening73is defined by a second sidewall insulating layer106in the second device formation region32. The second sidewall insulating layer106defines an inner wall of the second through hole77. The second sidewall insulating layer106extends from the opening portion of the second gate opening73toward the bottom wall of the second gate opening73.

The second sidewall insulating layer106is interposed in a region between the second gate insulating layer83and the second source field electrode layer103and in a region between the second gate insulating layer83and the second floating electrode layer104such as to be connected to the protection layer40(the first protection layer41). The second sidewall insulating layer106may penetrate the first protection layer41such as to be connected to the electron supply layer24.

An upper end portion of the second sidewall insulating layer106is R-chamfered. The upper end portion of the second sidewall insulating layer106is formed in a convexly curved shape toward an inner side of the second gate opening73. The upper end portion of the second sidewall insulating layer106is a portion located at the opening portion side of the second gate opening73in the second sidewall insulating layer106.

An opening area of the second gate opening73is greater than a bottom area of the second gate opening73. The second gate insulating layer83and the second gate electrode84enter the second gate opening73along a curved surface of the second sidewall insulating layer106.

Referring toFIG. 2toFIG. 8, a second interlayer insulating layer111is formed on the main surface insulating layer85. A main surface of the second interlayer insulating layer111may be a ground surface. The second interlayer insulating layer111is formed in a film shape along a main surface of the main surface insulating layer85. The second interlayer insulating layer111covers the first gate electrode82and the second gate electrode84.

The second interlayer insulating layer111may include at least one of SiO2 and SiN. The second interlayer insulating layer111may have a thickness of 50 nm or more and 500 nm or less. The second interlayer insulating layer111may have a thickness of 50 nm or more and 100 nm or less, 100 nm or more and 200 nm or less, 200 nm or more and 300 nm or less, 300 nm or more and 400 nm or less, or 400 nm or more and 500 nm or less. The second interlayer insulating layer111has a thickness of approximately 200 nm, in this preferred embodiment.

A first source contact opening112, a first drain contact opening113, a second source contact opening114, and a second drain contact opening115are formed in the second interlayer insulating layer111, the main surface insulating layer85, and the first interlayer insulating layer71.

The first source contact opening112and the first drain contact opening113are formed in the first device formation region31. The first source contact opening112and the first drain contact opening113are formed to be spaced apart from each other along the first direction X. The first source contact opening112and the first drain contact opening113extend in band shapes along the second direction Y.

The first source contact opening112penetrates the second interlayer insulating layer111, the main surface insulating layer85, and the first interlayer insulating layer71such as to expose the first source electrode51. The first drain contact opening113penetrates the second interlayer insulating layer111, the main surface insulating layer85, and the first interlayer insulating layer71such as to expose the first drain electrode52.

The second source contact opening114and the second drain contact opening115are formed in the second device formation region32. The second source contact opening114and the second drain contact opening115are formed to be spaced apart from each other along the first direction X. The second source contact opening114and the second drain contact opening115extend in band shapes along the second direction Y.

The second source contact opening114penetrates the second interlayer insulating layer111, the main surface insulating layer85, and the first interlayer insulating layer71such as to expose the second source electrode53. The second drain contact opening115penetrates the second interlayer insulating layer111, the main surface insulating layer85, and the first interlayer insulating layer71such as to expose the second drain electrode54.

A first source contact electrode121and a first drain contact electrode122are formed in the first device formation region31. The first source contact electrode121is embedded in the first source contact opening112. The first drain contact electrode122is embedded in the first drain contact opening113.

A second source contact electrode123and a second drain contact electrode124are formed in the second device formation region32. The second source contact electrode123is embedded in the second source contact opening114. The second drain contact electrode124is embedded in the second drain contact opening115.

Hereinafter, referring also toFIG. 12, modes of the first source contact electrode121, the first drain contact electrode122, the second source contact electrode123, and the second drain contact electrode124will be described.FIG. 12is a plan view with structures above the first source contact electrode121, the first drain contact electrode122, the second source contact electrode123, and the second drain contact electrode124being removed.

Referring toFIG. 12, the first source contact electrode121and the first drain contact electrode122are formed to be spaced apart from each other along the first direction X. The first source contact electrode121and the first drain contact electrode122extend in band shapes along the second direction Y.

The second source contact electrode123and the second drain contact electrode124are formed to be spaced apart from each other along the first direction X. The second source contact electrode123and the second drain contact electrode124extend in band shapes along the second direction Y.

Referring toFIG. 2toFIG. 8(particularly,FIG. 7), the first source contact electrode121includes an embedded electrode layer131and a cover electrode layer132. The embedded electrode layer131is embedded in the first source contact opening112. The cover electrode layer132covers the embedded electrode layer131.

The embedded electrode layer131has a laminated structure that includes a first embedded electrode layer133and a second embedded electrode layer134, in this preferred embodiment. The first embedded electrode layer133is formed in a film shape along an inner wall of the first source contact opening112. The first embedded electrode layer133defines a recessed space in the first source contact opening112.

The first embedded electrode layer133is formed as a barrier electrode layer, in this preferred embodiment. The first embedded electrode layer133may include at least one of Ti and TiN. The first embedded electrode layer133consists of a TiN layer, in this preferred embodiment.

The first embedded electrode layer133may have a thickness of 10 nm or more and 200 nm or less. The first embedded electrode layer133may have a thickness of 10 nm or more and 50 nm or less, 50 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, or 150 nm or more and 200 nm or less. The first embedded electrode layer133has a thickness of approximately 100 nm, in this preferred embodiment.

The second embedded electrode layer134is embedded in the first source contact opening112with the first embedded electrode layer133interposed between the second embedded electrode layer134and the first source contact opening112. The second embedded electrode layer134is embedded in the recessed space defined by the first embedded electrode layer133in the first source contact opening112. The second embedded electrode layer134includes a W (tungsten) layer, in this preferred embodiment.

The second embedded electrode layer134may have a thickness of 100 nm or more and 1000 nm or less. The second embedded electrode layer134may have a thickness of 100 nm or more and 250 nm or less, 250 nm or more and 500 nm or less, 500 nm or more and 750 nm or less, or 750 nm or more and 1000 nm or less. The thickness of the second embedded electrode layer134may be equal to or greater than the thickness of the first embedded electrode layer133. The second embedded electrode layer134has a thickness of approximately 500 nm, in this preferred embodiment.

The cover electrode layer132covers the embedded electrode layer131on the second interlayer insulating layer111. The cover electrode layer132overlaps an opening edge portion of the first source contact opening112. More specifically, the cover electrode layer132overlaps the second interlayer insulating layer111.

The cover electrode layer132has a laminated structure that includes a first cover electrode layer135and a second cover electrode layer136laminated in that order from the embedded electrode layer131side, in this preferred embodiment. The cover electrode layer132may include only either one of the first cover electrode layer135and the second cover electrode layer136.

The first cover electrode layer135may include at least one of Al, Si, and Cu. The first cover electrode layer135may include at least one of a conductive Poly-Si layer, an AlSiCu alloy layer, and an AlCu alloy layer. The first cover electrode layer135consists of the AlCu alloy layer, in this preferred embodiment.

The first cover electrode layer135may have a thickness of 100 nm or more and 1000 nm or less. The first cover electrode layer135may have a thickness of 100 nm or more and 250 nm or less, 250 nm or more and 500 nm or less, 500 nm or more and 750 nm or less, or 750 nm or more and 1000 nm or less. The first cover electrode layer135has a thickness of approximately 500 nm, in this preferred embodiment.

The second cover electrode layer136is formed as a barrier electrode layer, in this preferred embodiment. The second cover electrode layer136may include at least one of Ti and TiN. The second cover electrode layer136consists of a TiN layer, in this preferred embodiment.

The second cover electrode layer136may have a thickness of 10 nm or more and 200 nm or less. The second cover electrode layer136may have a thickness of 10 nm or more and 50 nm or less, 50 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, or 150 nm or more and 200 nm or less. The thickness of the second cover electrode layer136may be equal to or less than the thickness of the first cover electrode layer135. The second cover electrode layer136has a thickness of approximately 100 nm, in this preferred embodiment.

The first drain contact electrode122, the second source contact electrode123, and the second drain contact electrode124each have a structure similar to the structure of the first source contact electrode121. The description for the first source contact electrode121is applied mutatis mutandis to the descriptions for the first drain contact electrode122, the second source contact electrode123, and the second drain contact electrode124, respectively. The structures corresponding to the first source contact electrode121in the structure of the first drain contact electrode122, the second source contact electrode123, and the second drain contact electrode124will be given the same reference symbols and descriptions thereof will be omitted.

Referring toFIG. 2toFIG. 8, a third interlayer insulating layer141is formed on the second interlayer insulating layer111. A main surface of the third interlayer insulating layer141may be a ground surface. The third interlayer insulating layer141is formed in a film shape along the main surface of the second interlayer insulating layer111.

The third interlayer insulating layer141covers the first source contact electrode121, the first drain contact electrode122, the second source contact electrode123, and the second drain contact electrode124. The third interlayer insulating layer141may include at least one of SiO2 and SiN.

The third interlayer insulating layer141may have a thickness of 100 nm or more and 1000 nm or less. The third interlayer insulating layer141may have a thickness of 100 nm or more and 250 nm or less, 250 nm or more and 500 nm or less, 500 nm or more and 750 nm or less, or 750 nm or more and 1000 nm or less. The third interlayer insulating layer141has a thickness of approximately 500 nm, in this preferred embodiment.

Referring toFIG. 2toFIG. 6, a first gate contact hole142, a first source contact hole143, a first drain contact hole144, a second gate contact hole145, a second source contact hole146, and a second drain contact hole147are formed in the third interlayer insulating layer141and the second interlayer insulating layer111.

The first gate contact hole142, the first source contact hole143, and the first drain contact hole144are formed in the first device formation region31. The second gate contact hole145, the second source contact hole146, and the second drain contact hole147are formed in the second device formation region32.

The first gate contact hole142penetrates the third interlayer insulating layer141and the second interlayer insulating layer111such as to expose the first gate electrode82. The first source contact hole143penetrates the third interlayer insulating layer141such as to expose the first source contact electrode121. The first drain contact hole144penetrates the third interlayer insulating layer141such as to expose the first drain contact electrode122.

The second gate contact hole145penetrates the third interlayer insulating layer141and the second interlayer insulating layer111such as to expose the second gate electrode84. The second source contact hole146penetrates the third interlayer insulating layer141such as to expose the second source contact electrode123. The second drain contact hole147penetrates the third interlayer insulating layer141such as to expose the second drain contact electrode124.

The first source contact hole143and the second drain contact hole147oppose each other along the first direction X. The first gate contact hole142, the first drain contact hole144, the second gate contact hole145, and the second source contact hole146are formed to be spaced apart from each other along the second direction Y such as not to oppose each other along the first direction X, in this preferred embodiment.

A source-drain wiring layer151, a first gate wiring layer152, a drain wiring layer153, a second gate wiring layer154, and a source wiring layer155are formed on the third interlayer insulating layer141. The source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155are all formed above the first source electrode51, the first drain electrode52, the second source electrode53, the second drain electrode54, the first gate electrode82, and the second gate electrode84.

Hereinafter, referring also toFIG. 13, modes of the source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155will be described.FIG. 13is a plan view with structures above the source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155being removed.

The source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155are formed to be spaced apart from each other along the second direction Y in plan view.

The source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155are formed in band shapes that extends along the first direction X in plan view. The source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155are thus formed in a stripe shape that extends along the first direction X in plan view.

The arrangement orders of the source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155is arbitrary and thus not limited to the order shown inFIG. 13and the like.

Referring toFIG. 2andFIG. 13, the source-drain wiring layer151intersects the first source electrode51(the first source contact electrode121) and the second drain electrode54(the second drain contact electrode124) in plan view. The source-drain wiring layer151extends along a direction in which the first source electrode51(the first source contact electrode121) and the second drain electrode54(the second drain contact electrode124) oppose each other in plan view.

The source-drain wiring layer151linearly connects between the first source electrode51(the first source contact electrode121) and the second drain electrode54(the second drain contact electrode124) in plan view. The source-drain wiring layer151connects the first source electrode51(the first source contact electrode121) and the second drain electrode54(the second drain contact electrode124) with the shortest distance.

The source-drain wiring layer151enters the first source contact hole143from on the third interlayer insulating layer141. The source-drain wiring layer151is electrically connected to the first source contact electrode121in the first source contact hole143. The source-drain wiring layer151is thereby electrically connected to the first source electrode51via the first source contact electrode121.

The source-drain wiring layer151enters the second drain contact hole147from on the third interlayer insulating layer141. The source-drain wiring layer151is electrically connected to the second drain contact electrode124in the second drain contact hole147. The source-drain wiring layer151is thereby electrically connected to the second drain electrode54via the second drain contact electrode124.

Referring toFIG. 3andFIG. 13, the first gate wiring layer152extends in a band shape along the first direction X and intersects the first gate electrode82in plan view. The first gate wiring layer152enters the first gate contact hole142from on the third interlayer insulating layer141. The first gate wiring layer152is electrically connected to the first gate electrode82in the first gate contact hole142.

The first gate wiring layer152has one end portion that is located at one side in the first direction X and the other end portion that is located at the other side in the first direction X. The one end portion of the first gate wiring layer152is an end portion located at the side surface15B side of the substrate11. The other end portion of the first gate wiring layer152is an end portion located at the side surface15D side of the substrate11.

The first gate wiring layer152intersects the first drain electrode52, the second source electrode53, the second gate electrode84, and the second drain electrode54in plan view, in this preferred embodiment. The first gate wiring layer152may have an arbitrary length and may not be always required to intersect all of the first drain electrode52, the second source electrode53, the second gate electrode84, and the second drain electrode54.

Referring toFIG. 4andFIG. 13, the drain wiring layer153extends in a band shape along the first direction X and intersects the first drain electrode52in plan view. The drain wiring layer153enters the first drain contact hole144from on the third interlayer insulating layer141.

The drain wiring layer153is electrically connected to the first drain contact electrode122in the first drain contact hole144. The drain wiring layer153is thereby electrically connected to the first drain electrode52via the first drain contact electrode122.

The drain wiring layer153intersects the first source electrode51, the first gate electrode82, the second source electrode53, the second gate electrode84, and the second drain electrode54in plan view, in this preferred embodiment. The drain wiring layer153may have an arbitrary length and may not be always required to intersect all of the first source electrode51, the first gate electrode82, the second source electrode53, the second gate electrode84, and the second drain electrode54.

Referring toFIG. 5andFIG. 13, the second gate wiring layer154extends in a band shape along the first direction X and intersects the second gate electrode84in plan view. The second gate wiring layer154enters the second gate contact hole145from on the third interlayer insulating layer141. The second gate wiring layer154is electrically connected to the second gate electrode84in the second gate contact hole145.

The second gate wiring layer154has one end portion that is located at one side in the first direction X and the other end portion that is located at the other side in the first direction X. The one end portion of the second gate wiring layer154is a portion located at the side surface15B side of the substrate11. The other end portion of the second gate wiring layer154is a portion located at the side surface15D side of the substrate11.

The second gate wiring layer154intersects the first source electrode51, the first gate electrode82, the first drain electrode52, and the second source electrode53in plan view, in this preferred embodiment. The second gate wiring layer154may have an arbitrary length and may not be always required to intersect all of the first source electrode51, the first gate electrode82, the first drain electrode52, and the second source electrode53.

Referring toFIG. 6andFIG. 13, the source wiring layer155extends in a band shape along the first direction X and intersects the second source electrode53in plan view. The source wiring layer155enters the second source contact hole146from on the third interlayer insulating layer141.

The source wiring layer155is electrically connected to the second source contact electrode123in the second source contact hole146. The source wiring layer155is thereby electrically connected to the second source electrode53via the second source contact electrode123.

The source wiring layer155intersects the first source electrode51, the first gate electrode82, the first drain electrode52, the second gate electrode84, and the second drain electrode54in plan view, in this preferred embodiment. The source wiring layer155may have an arbitrary length and may not be always required to intersect all of the first source electrode51, the first gate electrode82, the first drain electrode52, the second gate electrode84, and the second drain electrode54.

Referring toFIG. 13, a first gate lead wiring layer156is connected to the one end portion of the first gate wiring layer152in this preferred embodiment. The first gate lead wiring layer156is formed as a partial region of the first gate wiring layer152.

The first gate lead wiring layer156is led out from the one end of the first gate wiring layer152toward a corner portion of the substrate11along the second direction Y. The first gate lead wiring layer156is led out toward a corner portion that connects the side surface15A and the side surface15B of the substrate11in plan view, in this preferred embodiment.

A second gate lead wiring layer157is connected to the one end portion of the second gate wiring layer154, in this preferred embodiment. The second gate lead wiring layer157is formed as a partial region of the second gate wiring layer154.

The second gate lead wiring layer157is led out from the one end of the second gate wiring layer154toward a corner portion of the substrate11along the second direction Y. The second gate lead wiring layer157is led out toward a corner portion that connects the side surface15C and the side surface15D of the substrate11in plan view, in this preferred embodiment.

Referring toFIG. 2, more specifically, the source-drain wiring layer151has a laminated structure that includes a first wiring layer161, a second wiring layer162, and a third wiring layer163laminated in that order from the third interlayer insulating layer141.

The first wiring layer161is formed as a barrier electrode layer, in this preferred embodiment. The first wiring layer161includes at least one of Ti and TiN. The first wiring layer161consists of a TiN layer, in this preferred embodiment.

The first wiring layer161may have a thickness of 10 nm or more and 100 nm or less. The first wiring layer161may have a thickness of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, or 75 nm or more and 100 nm or less. The first wiring layer161has a thickness of approximately 40 nm, in this preferred embodiment.

The second wiring layer162may include at least one of Al, Si, and Cu. The second wiring layer162may include at least one of a conductive Poly-Si layer, an AlSiCu alloy layer, and an AlCu alloy layer. The thickness of the second wiring layer162may be equal to or greater than that of the first wiring layer161. The second wiring layer162consists of the AlCu alloy layer, in this preferred embodiment.

The second wiring layer162may have a thickness of 500 nm or more and 1500 nm or less. The second wiring layer162may have a thickness of 500 nm or more and 750 nm or less, 750 nm or more and 1000 nm or less, 1000 nm or more and 1250 nm or less, or 1250 nm or more and 1500 nm or less. The thickness of the second wiring layer162exceeds the thickness of the first wiring layer161. The thickness of the second wiring layer162is approximately 1000 nm, in this preferred embodiment.

The third wiring layer163is formed as a barrier electrode layer, in this preferred embodiment. The third wiring layer163includes at least one Ti and TiN. The third wiring layer163consists of a TiN layer, in this preferred embodiment.

The third wiring layer163may have a thickness of 10 nm or more and 100 nm or less. The third wiring layer163may have a thickness of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, or 75 nm or more and 100 nm or less. The thickness of the third wiring layer163is less than the thickness of the second wiring layer162. The third wiring layer163has a thickness of approximately 40 nm, in this preferred embodiment.

Referring toFIG. 3toFIG. 6, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155each have a structure similar to the structure of the source-drain wiring layer151. The description for the source-drain wiring layer151is applied mutatis mutandis to the descriptions for the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155, respectively. The structures corresponding to the source-drain wiring layer151in the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155will be given the same reference symbols and descriptions thereof will be omitted.

Referring toFIG. 2toFIG. 6, a fourth interlayer insulating layer164is formed on the third interlayer insulating layer141. The fourth interlayer insulating layer164is formed in a film shape along the main surface of the third interlayer insulating layer141. The fourth interlayer insulating layer164covers the source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155. The fourth interlayer insulating layer164may include at least one of SiO2 and SiN.

The fourth interlayer insulating layer164may have a thickness of 500 nm or more and 2500 nm or less. The fourth interlayer insulating layer164may have a thickness of 500 nm or more and 1000 nm or less, 1000 nm or more and 1500 nm or less, or 1500 nm or more and 2000 nm or less. The fourth interlayer insulating layer164has a thickness of approximately 1500 nm, in this preferred embodiment.

A resin layer165is formed on the fourth interlayer insulating layer164. The resin layer165forms the first chip main surface3. The resin layer165is formed in a film shape along a main surface of the fourth interlayer insulating layer164. The resin layer165may include polyimide.

The resin layer165may have a thickness of 1 μm or more and 50 μm or less. The resin layer165may have a thickness of 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less. The resin layer165has a thickness of approximately 10 μm, in this preferred embodiment.

A source-drain pad opening166, a first gate pad opening167, a drain pad opening168, a second gate pad opening169, and a source pad opening170are formed in the fourth interlayer insulating layer164and the resin layer165.

The source-drain pad opening166exposes an arbitrary region of the source-drain wiring layer151as a source-drain pad region. The arbitrary region of the source-drain wiring layer151is a region in which the source-drain external terminal6is to be connected.

The first gate pad opening167exposes an arbitrary region of the first gate wiring layer152as a first gate pad region. The arbitrary region of the first gate wiring layer152is a region in which the first gate external terminal7is to be connected. The first gate pad opening167exposes the first gate lead wiring layer156, in this preferred embodiment.

The drain pad opening168exposes an arbitrary region of the drain wiring layer153as a drain pad region. The arbitrary region of the drain wiring layer153is a region in which the drain external terminal8is to be connected.

The second gate pad opening169exposes an arbitrary region of the second gate wiring layer154as a second gate pad region. The arbitrary region of the second gate wiring layer154is a region in which the second gate external terminal9is to be connected. The second gate pad opening169exposes the second gate lead wiring layer157, in this preferred embodiment.

The source pad opening170exposes an arbitrary region of the source wiring layer155as the source external terminal10. The arbitrary region of the source wiring layer155is a region in which the source external terminal10is to be connected.

Referring toFIG. 2, the source-drain external terminal6is formed in the source-drain pad opening166. More specifically, the source-drain external terminal6enters the source-drain pad opening166from on the resin layer165. The source-drain external terminal6upwardly protrudes from a main surface of the resin layer165.

The source-drain external terminal6is electrically connected to the source-drain wiring layer151in the source-drain pad opening166. The source-drain external terminal6is thereby electrically connected to the first source electrode51and the second drain electrode54via the source-drain wiring layer151.

Referring toFIG. 3, the first gate external terminal7is formed in the first gate pad opening167. More specifically, the first gate external terminal7enters the first gate pad opening167from on the resin layer165. The first gate external terminal7upwardly protrudes from the main surface of the resin layer165.

The first gate external terminal7is electrically connected to the first gate lead wiring layer156in the first gate pad opening167. The first gate external terminal7is thereby electrically connected to the first gate electrode82via the first gate wiring layer152.

Referring toFIG. 4, the drain external terminal8is formed in the drain pad opening168. More specifically, the drain external terminal8enters the drain pad opening168from on the resin layer165. The drain external terminal8upwardly protrudes from the main surface of the resin layer165.

The drain external terminal8is electrically connected to the drain wiring layer153in the drain pad opening168. The drain external terminal8is thereby electrically connected to the first drain electrode52via the drain wiring layer153.

Referring toFIG. 5, the second gate external terminal9is formed in the second gate pad opening169. More specifically, the second gate external terminal9enters the second gate pad opening169from on the resin layer165. The second gate external terminal9upwardly protrudes from the main surface of the resin layer165.

The second gate external terminal9is electrically connected to the second gate lead wiring layer157in the second gate pad opening169. The second gate external terminal9is thereby electrically connected to the second gate electrode84via the second gate wiring layer154.

Referring toFIG. 6, the source external terminal10is formed in the source pad opening170. More specifically, the source external terminal10enters the source pad opening170from on the resin layer165. The source external terminal10upwardly protrudes from the main surface of the resin layer165.

The source external terminal10is electrically connected to the source wiring layer155in the source pad opening170. The source external terminal10is thereby electrically connected to the second source electrode53via the source wiring layer155.

Referring toFIG. 2, more specifically, the source-drain external terminal6has a laminated structure that includes a base electrode layer171and a conductive bonding material layer172. The base electrode layer171enters the source-drain pad opening166from on the resin layer165.

The base electrode layer171is formed in a film shape along the main surface of the resin layer165and an inner wall of the source-drain pad opening166. The base electrode layer171defines a recessed space in the source-drain pad opening166. The base electrode layer171is formed as a barrier electrode layer, in this preferred embodiment. The base electrode layer171may include at least one of Ti and TiN. The base electrode layer171consists of a TiN layer, in this preferred embodiment.

The conductive bonding material layer172is formed on the base electrode layer171. The conductive bonding material layer172is embedded in the source-drain pad opening166with the base electrode layer171interposed between the conductive bonding material layer172and the source-drain pad opening166. The conductive bonding material layer172upwardly protrudes from the main surface of the resin layer165. The conductive bonding material layer172includes a portion that opposes the main surface of the resin layer165with the base electrode layer171interposed between the conductive bonding material layer172and the main surface of the resin layer165. The conductive bonding material layer172may include solder.

Referring toFIG. 3toFIG. 6, the first gate external terminal7, the drain external terminal8, the second gate external terminal9, and the source external terminal10each have a structure similar to the structure of the source-drain external terminal6. The description for the source-drain external terminal6is applied mutatis mutandis to the descriptions for the first gate external terminal7, the drain external terminal8, the second gate external terminal9, and the source external terminal10, respectively. The structures corresponding to the structure of the source-drain external terminal6in the first gate external terminal7, the drain external terminal8, the second gate external terminal9, and the source external terminal10will be given the same reference symbols and descriptions thereof will be omitted.

FIG. 14is a circuit diagram for explaining an electrical structure of the semiconductor device1shown inFIG. 1.

Referring toFIG. 14, the semiconductor device1includes the first HEMT33and the second HEMT34. The first HEMT33includes a first gate G1, a first source S1, and a first drain D1. The second HEMT34includes a second gate G2, a second source S2, and a second drain D2.

The first gate G1of the first HEMT33includes the first gate electrode82. The first source S1of the first HEMT33includes the first source electrode51(the first source contact electrode121). The first drain D1of the first HEMT33includes the first drain electrode52(the first drain contact electrode122).

The second gate G2of the second HEMT34includes the second gate electrode84. The second source S2of the second HEMT34includes the second source electrode53(the second source contact electrode123). The second drain D2of the second HEMT34includes the second drain electrode54(the second drain contact electrode124).

The source-drain external terminal6is connected to the first source S1of the first HEMT33and the second drain D2of the second HEMT34via the source-drain wiring layer151. The first gate external terminal7is connected to the first gate G1of the first HEMT33via the first gate wiring layer152.

The drain external terminal8is connected to the first drain D1of the first HEMT33via the drain wiring layer153. The second gate external terminal9is connected to the second gate G2of the second HEMT34via the second gate wiring layer154. The source external terminal10is connected to the second source S2of the second HEMT34via the source wiring layer155.

The semiconductor device1thus has a half bridge circuit173that includes the first HEMT33and the second HEMT34. The half bridge circuit173may be used in a power conversion circuit such as an inverter circuit or a DC-DC converter circuit.

The half bridge circuit173may be employed in a DC-DC converter circuit for high-frequency operation having an operation frequency of 1 MHz or more among DC-DC converter circuits. In the half bridge circuit173, the first HEMT33may constitute a HEMT of a high-voltage side, while the second HEMT34may constitute a HEMT of a low-voltage.

A first parasitic diode Di1, a first parasitic capacitance C1, and a first parasitic inductance L1are connected to the first HEMT33is connected. The first parasitic diode Di1is connected in parallel between the first source S1and the first drain D1in a direction in which a forward current flows through the first drain D1. The first parasitic capacitance C1is connected in parallel between the first source S1and the first drain D1. The first parasitic inductance L1is connected between the source-drain external terminal6and the first source S1.

A second parasitic diode Di2, a second parasitic capacitance C2, and a second parasitic inductance L2are connected to the second HEMT34. The second parasitic diode Di2is connected in parallel between the second source S2and the second drain D2in a direction in which a forward current flows through the second drain D2. The second parasitic capacitance C2is connected in parallel between the second source S2and the second drain D2. The second parasitic inductance L2is connected between the source-drain external terminal6and the second drain D2.

As described above, the semiconductor device1includes the first HEMT33and the second HEMT34that can be controlled independently each other. The first HEMT33and the second HEMT34are incorporated into the single laminated structure portion12(the semiconductor laminated structure portion26). This enables the first HEMT33and the second HEMT34to be confined in a limited region of the laminated structure portion12(the semiconductor laminated structure portion26), thus making it possible to reduce the semiconductor device1in size.

Furthermore, in a case in which the first HEMT33and the second HEMT34are electrically connected each other, a wiring layer connected to the first HEMT33and the second HEMT34can be confined in the limited region of the laminated structure portion12(the semiconductor laminated structure portion26). More specifically, the source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155can be confined in a region surrounded by a peripheral edge of the laminated structure portion12(the semiconductor laminated structure portion26) in plan view.

This enables a wiring distance between the first HEMT33and the second HEMT34to be shortened and thus the wiring resistance, the first parasitic inductance L1, the second parasitic inductance L2and the like to be reduced. It is thus possible to provide a semiconductor device1that can improve performance by taking advantage of the size reduction.

Particularly, according to the semiconductor device1, the source-drain wiring layer151is formed as a connection wiring layer to be electrically connected to the first source electrode51of the first HEMT33and the second drain electrode54of the second HEMT34. This enables the wiring distance between the first source electrode51of the first HEMT33and the second drain electrode54of the second HEMT34to be appropriately shortened.

This makes it possible to properly reduce the wiring resistance which exist between the first source electrode51of the first HEMT33and the second drain electrode54of the second HEMT34, the first parasitic inductance L1, the second parasitic inductance L2and the like.

In the semiconductor device1, the source-drain wiring layer151especially is formed in a line shape that linearly connects between the first source electrode51of the first HEMT33and the second drain electrode54of the second HEMT34. More specifically, the source-drain wiring layer151extends along the first direction X such as to intersect the first source electrode51and the second drain electrode54that extend along the second direction Y.

This enables the first source electrode51of the first HEMT33and the second drain electrode54of the second HEMT34to be connected with the shortest distance. As a result, since the wiring distance of the source-drain wiring layer151can be effectively shortened, the wiring resistance, the first parasitic inductance L1, the second parasitic inductance L2, and the like can be effectively reduced. It is also effective in reducing the wiring resistance, the first parasitic inductance L1, the second parasitic inductance L2and the like to form the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154and the source wiring layer155in band shapes (linear shapes).

According to the semiconductor device1, it is possible to obtain the effects shown inFIG. 15.FIG. 15is a switching waveform for explaining the switching property of the semiconductor device1shown inFIG. 1.

A first waveform WF1(see the solid line) and a second waveform WF2(see the broken line) are shown inFIG. 15. The first waveform WF1shows a ringing noise when the semiconductor device1operates at high frequencies. The second waveform WF2shows a ringing noise when a source of a semiconductor device having only the first HEMT33and a drain of a semiconductor device having only the second HEMT34are externally connected.

Referring to the first waveform WF1and the second waveform WF2, according to the semiconductor device1, the wiring resistance, the first parasitic inductance L1, and the second parasitic inductance L2can be reduced, thus making it possible to accordingly reduce the ringing noise.

FIG. 16AtoFIG. 16Zare cross-sectional views for explaining an example of a method of manufacturing the semiconductor device1shown inFIG. 1.FIG. 16AtoFIG. 16Zare cross-sectional views showing such portions that correspond toFIG. 2, showing a region in which one semiconductor device1is formed.

Referring toFIG. 16A, a wafer181is prepared. The wafer181has a first wafer main surface182on one side and a second wafer main surface183on the other side. The first wafer main surface182and the second wafer main surface183correspond to the first main surface13and the second main surface14of the substrate11, respectively.

A plurality of semiconductor device regions184in which the semiconductor device1is formed is set to the wafer181. For example, the semiconductor device regions184are set in a matrix shape and defined by dicing lines (not shown).

The first device formation region31in which the first HEMT33is formed, the second device formation region32in which the second HEMT34, and a boundary region185between the first device formation region31and the second device formation region32are further set in each of the semiconductor device regions184. The wafer181is cut along the semiconductor device regions184(the dicing lines) into a plurality of semiconductor devices1after predetermined manufacturing processes are executed toward the wafer181.

Next, referring toFIG. 16B, the laminated structure portion12that includes the core formation layer21, the buffer layer22, the electron transit layer23, the electron supply layer24, and the top insulating layer25is formed on the first wafer main surface182. The core formation layer21, the buffer layer22, the electron transit layer23, the electron supply layer24, and the top insulating layer25are respectively formed by epitaxially grown methods.

Next, referring toFIG. 16C, a mask186having a predetermined pattern is formed on the laminated structure portion12. The mask186has an opening187that exposes a portion along the boundary region185in the laminated structure portion12. That is, the opening187exposes a region in which the region separation trench36is to be formed in the laminated structure portion12.

Next, an unnecessary portion of the laminated structure portion12is removed by an etching method via the mask186. The region separation trench36is thereby formed in the laminated structure portion12. The mask186is removed thereafter.

Next, referring toFIG. 16D, the first protection layer41is formed such as to cover the laminated structure portion12. The first protection layer41may be formed by a CVD (Chemical Vapor Deposition) method. The CVD method may be a low-pressure CVD method. The first protection layer41may include CVD-SiO2.

Next, referring toFIG. 16E, a base electrode layer188served as a base for the first source field electrode layer101, the first floating electrode layer102, the second source field electrode layer103, and the second floating electrode layer104is formed on the first protection layer41.

Next, referring toFIG. 16F, a mask189having a predetermined pattern is formed on the base electrode layer188. The mask189covers regions of the base electrode layer188in which a first base electrode layer190and a second base electrode layer191are to be formed. The first base electrode layer190is served as a base for the first source field electrode layer101and the first floating electrode layer102. The second base electrode layer191is served as a base for the second source field electrode layer103and the second floating electrode layer104.

Next, an unnecessary portion of the base electrode layer188is removed by an etching method via the mask189. The base electrode layer188is thereby divided into the first base electrode layer190and the second base electrode layer191. The mask189is removed thereafter.

Next, referring toFIG. 16G, the second protection layer42is formed on the first protection layer41. The second protection layer42covers the first base electrode layer190and the second base electrode layer191. The second protection layer42may be formed by a CVD method. The CVD method may be a plasma CVD method. The second protection layer42may include TEOS-SiO2. The single protection layer40is formed by the laminated structure having the first protection layer41and the second protection layer42.

Next, referring toFIG. 16H, a mask192having a predetermined pattern is formed on the protection layer40. The mask192has openings193that expose regions in which the first source opening45, the first drain opening46, the second source opening47, and the second drain opening48are to be formed in the protection layer40and the top insulating layer25.

Next, unnecessary portions of the protection layer40and the top insulating layer25are removed by etching methods via the mask192. The first source opening45, the first drain opening46, the second source opening47, and the second drain opening48are thereby formed in the protection layer40and the top insulating layer25. The mask192is removed thereafter.

Next, referring toFIG. 16I, the first source electrode51, the first drain electrode52, the second source electrode53, and the second drain electrode54are embedded in the first source opening45, the first drain opening46, the second source opening47, and the second drain opening48that correspond to those electrodes, respectively. This step includes a step of forming the embedded electrode layer61and a step of forming the cover electrode layer62.

The step of forming the embedded electrode layer61includes a step of embedding the embedded electrode layer61in the first source opening45, the first drain opening46, the second source opening47, and the second drain opening48. In this step, the second embedded electrode layer64is embedded in the first source opening45, the first drain opening46, the second source opening47, and the second drain opening48with the first embedded electrode layer63interposed between the second embedded electrode layer64and the respective opening.

The first embedded electrode layer63and the second embedded electrode layer64may be each formed by a sputtering method. The first embedded electrode layer63may include Ti. The second embedded electrode layer64may include AlSiCu alloy.

After the step of forming the embedded electrode layer61, the step of forming the cover electrode layer62is performed. In this step, the first cover electrode layer65and the second cover electrode layer66are formed in that order on each embedded electrode layer61. The first cover electrode layer65and the second cover electrode layer66may be each formed by a sputtering method. The first cover electrode layer65may include Ti. The second cover electrode layer66may include TiN. The first source electrode51, the first drain electrode52, the second source electrode53, and the second drain electrode54are thereby formed.

Next, referring toFIG. 16J, the first interlayer insulating layer71is formed on the protection layer40. The first interlayer insulating layer71may be formed by a CVD method. The first interlayer insulating layer71may include SiO2. The main surface of the first interlayer insulating layer71may be flattened after forming the first interlayer insulating layer71.

Next, referring toFIG. 16K, a mask194having a predetermined pattern is formed on the first interlayer insulating layer71. The mask194has openings195that expose regions in which the first gate opening72and the second gate opening73are to be formed in the first interlayer insulating layer71, the protection layer40, the first base electrode layer190, and the second base electrode layer191.

Next, unnecessary portions of the first interlayer insulating layer71, the protection layer40, the first base electrode layer190, and the second base electrode layer191are removed by etching methods via the mask194. A first base gate opening196served as a base for the first gate opening72and a second base gate opening197served as a base for the second gate opening73are thereby formed.

Furthermore, in this step, an unnecessary portion of the first base electrode layer190is removed, so that the first base electrode layer190is divided into the first source field electrode layer101and the first floating electrode layer102. Furthermore, in this step, an unnecessary portion of the second base electrode layer191is removed, so that the second base electrode layer191is divided into the second source field electrode layer103and the second floating electrode layer104. The mask192is removed thereafter.

Next, referring toFIG. 16L, a base insulating layer198served as a base for the first sidewall insulating layer105and the second sidewall insulating layer106is formed. The base insulating layer198is formed in a film shape along an inner wall of the first base gate opening196, an inner wall of the second base gate opening197, and the main surface of the first interlayer insulating layer71. The base insulating layer198may be formed by a CVD method. The base insulating layer198may include SiO2.

Next, referring toFIG. 16M, an unnecessary portion of the base insulating layer198is removed such that a portion along the inner wall of the first base gate opening196and a portion along the inner wall of the second base gate opening197remain in the base insulating layer198. The unnecessary portion of the base insulating layer198may be removed by an etching method (e.g., by a dry etching method).

The first sidewall insulating layer105and the second sidewall insulating layer106are thereby be formed in a self-aligned manner with respect to the main surface of the first interlayer insulating layer71. In this case, a corner portion of the upper end portion of the first sidewall insulating layer105and a corner portion of the upper end portion of the second sidewall insulating layer106are rounded (also seeFIG. 8).

Next, an unnecessary portion of the second protection layer42and an unnecessary portion of the top insulating layer25are removed from a bottom wall of the first base gate opening196and a bottom wall of the second base gate opening197. The unnecessary portion of the second protection layer42and the unnecessary portion of the top insulating layer25may be removed by an etching method (e.g., by a dry etching method). The first through hole75of the first gate opening72and the second through hole77of the second gate opening73are thereby formed.

Next, referring toFIG. 16N, unnecessary portions of the electron supply layer24are removed from the bottom wall of the first base gate opening196and the bottom wall of the second base gate opening197. The unnecessary portions of the electron supply layer24may be removed by an etching method (e.g., by a dry etching method).

The first gate contact hole74of the first gate opening72and the second gate contact hole76of the second gate opening73are thereby formed. Furthermore, the first base gate opening196and the second base gate opening197are thereby formed as the first gate opening72and the second gate opening73.

Next, referring toFIG. 16O, the insulating layer86that integrally includes the first gate insulating layer81, the second gate insulating layer83, and the main surface insulating layer85is formed on the first interlayer insulating layer71. The insulating layer86may be formed by a CVD method or an ALD (Atomic Layer Deposition) method. The insulating layer86may include SiO2.

Next, referring toFIG. 16P, the first gate electrode82and the second gate electrode84are embedded in the first gate opening72and the second gate opening73, respectively. This step includes a step of forming the embedded electrode layer91and a step of forming the cover electrode layer92.

The step of forming the embedded electrode layer91includes a step of forming the embedded electrode layer91in the first gate opening72and the second gate opening73. In this step, the second embedded electrode layer94is embedded in the first gate opening72and the second gate opening73with the first embedded electrode layer93interposed between the second embedded electrode layer94and the respective openings. The first embedded electrode layer93and the second embedded electrode layer94may be each formed by a sputtering method. The first embedded electrode layer93may include TiN. The second embedded electrode layer94may include W (tungsten).

The step of forming the cover electrode layer92is performed after the step of forming the embedded electrode layer91. In this step, the first cover electrode layer95and the second cover electrode layer96are formed in that order on each embedded electrode layer91. The first cover electrode layer95and the second cover electrode layer96may be each formed by a sputtering method. The first cover electrode layer95may include AlCu alloy. The second cover electrode layer96may include TiN. The first gate electrode82and the second gate electrode84are thereby formed.

Next, referring toFIG. 16Q, the second interlayer insulating layer111is formed on the insulating layer86. The second interlayer insulating layer111may be formed by a CVD method. The second interlayer insulating layer111may include SiO2. The main surface of the second interlayer insulating layer111may be flattened after forming the second interlayer insulating layer111.

Next, referring toFIG. 16R, a mask199having a predetermined pattern is formed on the second interlayer insulating layer111. The mask199has openings200that expose regions in which the first source contact opening112, the first drain contact opening113, the second source contact opening114, and the second drain contact opening115are to be formed in the second interlayer insulating layer111, the insulating layer86, and the first interlayer insulating layer71.

Next, unnecessary portions of the second interlayer insulating layer111, the insulating layer86, and the first interlayer insulating layer71are removed by etching methods via the mask199. The second source contact opening114and the second drain contact opening115are thereby formed. The mask199is removed thereafter.

Next, referring toFIG. 16S, the first source contact electrode121, the first drain contact electrode122, the second source contact electrode123, and the second drain contact electrode124are embedded in the first source contact opening112, the first drain contact opening113, the second source contact opening114, and the second drain contact opening115that correspond to those electrodes, respectively. This step includes a step of forming the embedded electrode layer131and a step of forming the cover electrode layer132.

The step of forming the embedded electrode layer131includes a step of embedding the embedded electrode layer131in the first source contact opening112, the first drain contact opening113, the second source contact opening114, and the second drain contact opening115that correspond to the embedded electrode layer131. In this step, the second embedded electrode layer134is embedded in the first source contact opening112, the first drain contact opening113, the second source contact opening114, and the second drain contact opening115with the first embedded electrode layer133interposed between the second embedded electrode layer134and each opening.

The first embedded electrode layer133and the second embedded electrode layer134may be each formed by a sputtering method. The first embedded electrode layer133may include TiN. The second embedded electrode layer134may include W (tungsten).

The step of forming the cover electrode layer132is performed after the step of forming the embedded electrode layer131. In this step, the first cover electrode layer135and the second cover electrode layer136are formed in that order on each embedded electrode layer131. The first cover electrode layer135and the second cover electrode layer136may be each formed by a sputtering method. The first cover electrode layer135may include AlCu alloy. The second cover electrode layer136may include TiN. The first source contact electrode121, the first drain contact electrode122, the second source contact electrode123, and the second drain contact electrode124are thereby formed.

Next, referring toFIG. 16T, the third interlayer insulating layer141is formed on the second interlayer insulating layer111. The third interlayer insulating layer141may be formed by a CVD method. The third interlayer insulating layer141may include SiO2. The main surface of the third interlayer insulating layer141may be flattened after forming the third interlayer insulating layer141.

Next, referring toFIG. 16U, a mask201having a predetermined pattern is formed on the third interlayer insulating layer141. The mask201has openings202that expose regions in which the first source contact hole143, the first drain contact hole144, the second source contact hole146, and the second drain contact hole147are to be formed in the third interlayer insulating layer141.

Next, unnecessary portions of the third interlayer insulating layer141are removed by an etching method via the mask201. The first source contact hole143, the first drain contact hole144, the second source contact hole146, and the second drain contact hole147are thereby formed. The mask201is removed thereafter.

Next, referring toFIG. 16V, a base wiring layer203to serve as a base for the source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155is formed on the third interlayer insulating layer141.

The first wiring layer161, the second wiring layer162, and the third wiring layer163are formed in that order on the third interlayer insulating layer141, in the step of forming the base wiring layer203. The first wiring layer161, the second wiring layer162, and the third wiring layer163may be each formed by a sputtering method.

Next, a mask204having a predetermined pattern is formed on the base wiring layer203. The mask204covers regions in which the source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155are to be formed in the base wiring layer203.

Next, unnecessary portions of the base wiring layer203are removed by etching methods via the mask204. The source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155are thereby formed. The mask204is removed thereafter.

Next, referring toFIG. 16W, the fourth interlayer insulating layer164is formed on the third interlayer insulating layer141. The fourth interlayer insulating layer164may be formed by a CVD method. The fourth interlayer insulating layer164may include SiO2. The main surface of the fourth interlayer insulating layer164may be flattened after forming the fourth interlayer insulating layer164.

Next, referring toFIG. 16X, a mask205having a predetermined pattern is formed on the fourth interlayer insulating layer164. The mask205has openings206that expose regions in which the source-drain pad opening166, the first gate pad opening167, the drain pad opening168, the second gate pad opening169, and the source pad opening170are to be formed in the fourth interlayer insulating layer164. Next, unnecessary portions of the fourth interlayer insulating layer164are removed by an etching method via the mask205. The mask205is removed thereafter.

Next, referring toFIG. 16Y, the resin layer165is formed on the fourth interlayer insulating layer164. The resin layer165may be formed by coating the fourth interlayer insulating layer164with a polyimide resin. Next, the resin layer165is selectively exposed to light and developed. The regions in which the source-drain pad opening166, the first gate pad opening167, the drain pad opening168, the second gate pad opening169, and the source pad opening170are to be formed in the resin layer165are removed.

The source-drain pad opening166, the first gate pad opening167, the drain pad opening168, the second gate pad opening169, and the source pad opening170are thereby formed in the fourth interlayer insulating layer164and the resin layer165.

Next, referring toFIG. 16Z, the source-drain external terminal6, the first gate external terminal7, the drain external terminal8, the second gate external terminal9, and the source external terminal10are formed in the source-drain pad opening166, the first gate pad opening167, the drain pad opening168, the second gate pad opening169, and the source pad opening170that correspond to those terminals, respectively.

In this step, first, the base electrode layer171is formed in the source-drain pad opening166, the first gate pad opening167, the drain pad opening168, the second gate pad opening169, and the source pad opening170. The base electrode layer171may be formed by a sputtering method. The base electrode layer171may include TiN.

Next, the conductive bonding material layer172is formed on the base electrode layer171. The conductive bonding material layer172may be formed by a plating method. The conductive bonding material layer172may include solder. The source-drain external terminal6, the first gate external terminal7, the drain external terminal8, the second gate external terminal9, and the source external terminal10are thereby formed.

The wafer181is cut along the semiconductor device regions184(the dicing lines) into a plurality of semiconductor devices1thereafter. Through the steps including the above, the semiconductor device1is manufactured.

FIG. 17is a plan view showing a semiconductor device211according to a second preferred embodiment of the present invention.FIG. 18is a schematic block diagram for explaining a mode of electrical connection of each member in the semiconductor device211shown inFIG. 17. Hereinafter, structures corresponding to the structures described for the semiconductor device1are denoted by the same reference symbols, and the descriptions thereof will be omitted.

InFIG. 18, as shown inFIG. 14aforementioned, the first gate electrode82, the first source electrode51(the first source contact electrode121), and the first drain electrode52(the first drain contact electrode122) are shown in a simplified manner by “G1,” “S1,” and “D1,” respectively. Additionally, inFIG. 18, the second gate electrode84, the second source electrode53(the second source contact electrode123), and the second drain electrode54(the second drain contact electrode124) are shown in a simplified manner by “G2,” “S2,” and “D2,” respectively.

Furthermore, inFIG. 18, the source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155are shown by the respective lines that extend along the first direction X. Furthermore, inFIG. 18, the source-drain external terminal6, the first gate external terminal7, the drain external terminal8, the second gate external terminal9, and the source external terminal10are each shown blocks.

Referring toFIG. 17andFIG. 18, a plurality of first device formation regions31and a plurality of second device formation regions32are set in the single laminated structure portion12in the semiconductor device211. Hereinafter, an example in which two first device formation regions31and two second device formation regions32are set will be described.

The plurality of first device formation regions31and the plurality of second device formation regions32are formed alternately along the first direction X. Each of the first device formation regions31and each of the second device formation regions32are separated from each other by the region separation structure35.

The structure of each first device formation region31is similar to the structure of the first device formation region31of the semiconductor device1. The structure of each second device formation region32is similar to the structure of the second device formation region32of the semiconductor device1.

The source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155are all formed above the laminated structure portion12such as to intersect the plurality of first device formation regions31and the plurality of second device formation regions32.

The source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155all extend in band shapes along the first direction X.

That is, the source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155all intersect (are orthogonal to) the first gate electrode82, the first source electrode51(the first source contact electrode121), the first drain electrode52(the first drain contact electrode122), the second gate electrode84, the second source electrode53(the second source contact electrode123), and the second drain electrode54(the second drain contact electrode124).

The length of the source-drain wiring layer151, the length of the first gate wiring layer152, the length of the drain wiring layer153, the length of the second gate wiring layer154, and the length of the source wiring layer155may be arbitrary as in the case of the semiconductor device1and are not limited to the modes shown inFIG. 17.

The source-drain wiring layer151is electrically connected to the first source electrode51(the first source contact electrode121) that is formed in each first device formation region31and the second drain electrode54(the second drain contact electrode124) that is formed in each second device formation region32.

The first gate wiring layer152is electrically connected to the first gate electrode82that is formed in each first device formation region31. The drain wiring layer153is electrically connected to the first drain electrode52that is formed in each first device formation region31.

The second gate wiring layer154is electrically connected to the second gate electrode84that is formed in each second device formation region32. The source wiring layer155is electrically connected to the second source electrode53that is formed in each second device formation region32.

One or a plurality of source-drain external terminals6is electrically connected to the source-drain wiring layer151. Three source-drain external terminals6are electrically connected to the source-drain wiring layer151, in this preferred embodiment.

The plurality of source-drain external terminals6are formed to be spaced apart from each other along the first direction X on the first chip main surface3. Each source-drain external terminal6extends in a band shape along the second direction Y in plan view. Each source-drain wiring layer151is formed in a region between the first device formation region31and the second device formation region32in plan view, in this preferred embodiment.

One or a plurality of the first gate external terminals7is electrically connected to the first gate wiring layer152. One first gate external terminal7is electrically connected to the first gate wiring layer152, in this preferred embodiment.

The first gate external terminal7is formed in a region along a corner portion on the first chip main surface3. More specifically, the first gate external terminal7is formed a region along a corner portion that connects the chip side surface5A and the chip side surface5B in the first chip main surface3.

One or a plurality of the drain external terminals8is electrically connected to the drain wiring layer153. Two drain external terminals8are electrically connected to the drain wiring layer153, in this preferred embodiment. Each drain external terminal8is arranged immediately above each second device formation region32, in this preferred embodiment. Each drain external terminal8extends in a band shape along the second direction Y in plan view.

One or a plurality of the second gate external terminals9is electrically connected to the second gate wiring layer154. One second gate external terminal9is electrically connected to the second gate wiring layer154, in this preferred embodiment. The second gate external terminal9is formed in a region along a corner portion on the first chip main surface3. More specifically, the second gate external terminal9is formed in a region along a corner portion that connects the chip side surface5C and the chip side surface5D in the first chip main surface3.

One or a plurality of the source external terminals10is electrically connected to the source wiring layer155. Two source external terminals10are electrically connected to the source wiring layer155, in this preferred embodiment. Each source external terminals10is arranged immediately above each first device formation region31, in this preferred embodiment. Each source external terminal10extends in a band shape along the second direction Y in plan view.

As described above, the semiconductor device211is also capable of providing a similar effect as those described regarding the semiconductor device1.

As described above, the preferred embodiments of the present invention were described, however, the present invention may be implemented yet in other preferred embodiments.

In each preferred embodiment described above, an example in which the source-drain wiring layer151to be electrically connected to the first source electrode51and the second drain electrode54is formed has been described. However, the electrical connection between the first HEMT33and the second HEMT34is not limited to the preferred embodiments.

For example, in each preferred embodiment described above, a source-source wiring layer to be electrically connected to the first source electrode51and the second source electrode53may be formed in place of or in addition to the source-drain wiring layer151. In this case, the plurality of external terminals may include an external terminal that is electrically connected to the source-source wiring layer.

In each preferred embodiment described above, a source-gate wiring layer to be electrically connected to the first source electrode51and the second gate electrode84may be formed in place of or in addition to the source-drain wiring layer151. In this case, the plurality of external terminals may include an external terminal that is electrically connected to the source-gate wiring layer.

In each preferred embodiment described above, a drain-source wiring layer to be electrically connected to the first drain electrode52and the second source electrode53may be formed in place of or in addition to the source-drain wiring layer151. In this case, the plurality of external terminals may include an external terminal that is electrically connected to the drain-source wiring layer.

In each preferred embodiment described above, a drain-drain wiring layer to be electrically connected to the first drain electrode52and the second drain electrode54may be formed in place of or in addition to the source-drain wiring layer151. In this case, the plurality of external terminals may include an external terminal that is electrically connected to the drain-drain wiring layer.

In each preferred embodiment described above, a drain-gate wiring layer to be electrically connected to the first drain electrode52and the second gate electrode84may be formed in place of or in addition to the source-drain wiring layer151. In this case, the plurality of external terminals may include an external terminal that is electrically connected to the drain-gate wiring layer.

In each preferred embodiment described above, a gate-source wiring layer to be electrically connected to the first gate electrode82and the second source electrode53may be formed in place of or in addition to the source-drain wiring layer151. In this case, the plurality of external terminals may include an external terminal that is electrically connected to the gate-source wiring layer.

In each preferred embodiment described above, a gate-drain wiring layer to be electrically connected to the first gate electrode82and the second drain electrode54may be formed in place of or in addition to the source-drain wiring layer151. In this case, the plurality of external terminals may include an external terminal that is electrically connected to the gate-drain wiring layer.

In each preferred embodiment described above, a gate-gate wiring layer to be electrically connected to the first gate electrode82and the second gate electrode84may be formed in place of or in addition to the source-drain wiring layer151. In this case, the plurality of external terminals may include an external terminal that is electrically connected to the gate-gate wiring layer.

For example, those modes are formed by modifying the layout of the mask201in the step ofFIG. 16U, and by modifying the layout of the mask205, etc., in the steps ofFIG. 16XandFIG. 16Y.

That is, those modes can be readily achieved by adjusting layouts of the first gate contact hole142, the first source contact hole143, the first drain contact hole144, the second gate contact hole145, the second source contact hole146, and the second drain contact hole147, and layouts of the plurality of external terminals.

In the structure especially in which the plurality of wiring layers (the source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, the second gate wiring layer154, and the source wiring layer155) are formed in the stripe shape extending along the first direction X, there is an advantages in that the layouts of the contact holes142to147and the layouts of the plurality of external terminals can be modified without significantly modifying the layouts of the plurality of wiring layers.

In each preferred embodiment described above, positions of the second source electrode53(the second source contact electrode123) and the second drain electrode54(the second drain contact electrode124) may be interchanged.

In each preferred embodiment described above, positions of the first source electrode51(the first source contact electrode121) and the first drain electrode52(the first drain contact electrode122) may be interchanged.

In each preferred embodiment described above, an example in which the first source electrode51(the first source contact electrode121), the first drain electrode52(the first drain contact electrode122), and the first gate electrode82were formed each singly in the first device formation region31.

However, in each preferred embodiment described above, a plurality of first source electrodes51(first source contact electrodes121), a plurality of first drain electrodes52(first drain contact electrodes122), and a plurality of first gate electrodes82may be formed. That is, the single first HEMT33having the plurality of first source electrodes51(the first source contact electrodes121), the plurality of first drain electrodes52(the first drain contact electrodes122), and the plurality of first gate electrodes82may be formed.

In each preferred embodiment described above, an example in which the second source electrode53(the second source contact electrode123), the second drain electrode54(the second drain contact electrode124), and the second gate electrode84were formed each singly in the second device formation region32.

However, in each preferred embodiment described above, a plurality of second source electrodes53(second source contact electrodes123), a plurality of second drain electrodes54(second drain contact electrodes124), and a plurality of second gate electrodes84may be formed in the second device formation region32. That is, the single second HEMT34having the plurality of second source electrodes53(the second source contact electrodes123), the plurality of second drain electrodes54(the second drain contact electrodes124), and the plurality of second gate electrodes84may be formed.

In the second preferred embodiment described above, three or more first device formation regions31and three or more second device formation regions32may be formed in the single laminated structure portion12. In this case, the three or more first device formation regions31and the three or more second device formation regions32may be alternately arranged along the first direction X.

In the second preferred embodiment described above, an example shown inFIG. 19may be employed.FIG. 19is a schematic block diagram corresponding toFIG. 18and a view for explaining another example of electrical connection of each member. Hereinafter, structures corresponding to the structures described for the semiconductor device211are denoted by the same reference symbols, and the descriptions thereof will be omitted.

Referring toFIG. 19, the source-drain wiring layer151, the first gate wiring layer152, the drain wiring layer153, and the second gate wiring layer154may be each separated at an arbitrary region. InFIG. 19, a mode in which two semiconductor devices1are formed using the single laminated structure portion12is shown.