Novel self-aligned, low contact resistance, via fabrication process

A process for fabricating an upper level, metal interconnect structure, self-aligned to an underlying metal plug structure, which in turn overlays, and contacts a lower level, metal interconnect structure, has been developed. The process features the formation of a recessed metal plug structure, in a via hole, overlying and contacting a portion of the top surface of the lower level, metal interconnect structure. Deposition of a metal layer is followed by a patterning procedure which results in the formation of a metal structure component, located on the surface of an insulator layer, defined by an overlying photoresist shape, with the metal structure component attached to a metal ring component, which is located in a top portion of a via hole, overlying and contacting, portions of the top surface of the recessed metal plug structure, with the metal ring component formed during the same patterning procedure, however unprotected by the photoresist shape. The metal ring structure is comprised of metal spacers, located on the sides of the top portion of the via hole.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of fabricating a metal interconnect structure, comprised with an attached metal ring component, overlaying, contacting, and self-aligned to, a recessed metal plug structure, located in a via hole, will now be described in detail. Lower level, metal interconnect structure 10 , comprised of an aluminum based layer 2 , underlying titanium nitride barrier layer 3 , and overlying titanium nitride barrier layer 1 , is schematically shown in FIG. 1 . The titanium nitride layers are obtained via plasma vapor deposition, (PVD), procedures, each at a thickness between about 100 to 1500 Angstroms. Aluminum based layer 2 , is an aluminum-copper layer, also obtained via PVD procedures, at a thickness between about 2000 to 20000 Angstroms. The aluminum based layer 2 , and both titanium nitride layer 1 , and titanium nitride layer 3 , can all be deposited in situ, in the same PVD tool. Patterning procedures used to define lower level metal interconnect structure 10 , are accomplished via conventional photolithographic and reactive ion etching, (RIE), procedures, using Cl 2 or SF 6 as an etchant for the titanium nitride layers, and for the aluminum based layer. Lower level metal interconnect structure 10 , can be located on an underlying interlevel dielectric, (ILD), layer, with a portion of lower level metal interconnect structure 10 , contacting an underlying conductive region, such as a metal plug or interconnect structure. Lower metal interconnect structure 10 , can also be located on an underlying ILD layer, with a portion of lower level, metal interconnect structure overlying and contacting an active device region, in a semiconductor substrate. This is not shown in the drawings. ILD layer 4 , comprised of silicon oxide, or of borophosphosilicate glass, (BPSG), is next deposited via plasma enhanced chemical vapor deposition, (PECVD), or via low pressure chemical vapor deposition, (LPCVD), procedures, to a thickness between about 5000 to 30000 Angstroms. This is schematically shown in FIG. 1 . A photoresist shape 5 , with opening 6 a, to be used as a mask for defining a via hole opening in ILD layer 4 , is next formed and shown schematically in FIG. 1 . Opening 6 a, in photoresist shape 5 , has a diameter between about 0.10 to 1.0 um. An anisotropic RIE procedure is next performed using photoresist shape 5 , as a mask, and using CF 3 as an etchant for ILD layer 4 , creating via hole 6 b, shown schematically in FIG. 2 . Via hole 6 b, formed using opening 6 a, in photoresist shape 5 , as a mask, features the same diameter as opening 6 a, between about 0.10 to 1.0 um. The anisotropic RIE procedure, is terminated at the appearance of titanium nitride barrier layer 3 , with a top portion of this layer removed at endpoint After removal of photoresist shape 5 , via plasma oxygen ashing and careful wet clean procedures, tungsten layer 7 a, is deposited via LPCVD procedures, using tungsten hexafluoride as a source. Tungsten layer 7 a, schematically shown in FIG. 3 , is deposited at a thickness between about 2000 to 10000 Angstroms, completely filling via hole 6 b. A critical etch back of tungsten layer 7 a, is next performed, via a selective RIE procedure, using Cl 2 or SF 6 as an etchant. The selective RIE procedure removes the region of tungsten layer 7 a, from the top surface of ILD layer 4 , and then is continued to remove a top portion of tungsten layer 7 a, located in via hole 6 b, creating recessed tungsten plug structure 7 b, schematically shown in FIG. 4 . The etch rate selectivity between tungsten, and ILD layer, of between about 10 to 1, using Cl 2 of SF 6 , allows the desired recessing of tungsten to be realized without thinning ILD layer 4 . The height of recessed tungsten plug structure 7 b, or the remaining thickness of tungsten layer 7 a, in via hole 6 b, is between about 3000 to 20000 Angstroms. Metal layer 8 a, comprised of aluminum, or an aluminum-copper layer, is next deposited, via PVD procedures, to a thickness between about 2000 to 20000 Angstroms. This is shown schematically in FIG. 5 . Metal layer 8 a, resides on the top surface of ILD layer 4 , as well as on recessed tungsten plug structure 7 b, in via hole 6 b. Photoresist shape 9 , shown schematically in FIG. 6 , is next formed on metal layer 8 a, with photoresist shape 9 , overlaying a first portion of metal layer 8 a, which resides on ILD layer 4 , and overlaying a second portion of metal layer 8 a, which is located in via hole 6 b. It is imperative that second portion of metal layer 8 a, in via hole 6 b, be overlaid by photoresist shape 9 . A critical anisotropic RIE procedure, using Cl 2 or SF 6 as an etchant, is used to remove regions of metal layer 8 a, not protected by photoresist shape 9 . The anisotropic RIE procedure results in complete removal of unprotected metal layer 8 a, from the top surface of ILD layer 4 , resulting in metal structure 8 b, on ILD layer 4 . The anisotropic RIE procedure, terminated at the appearance of ILD layer 4 , also results partial removal of unprotected regions of metal layer 8 a, located in via hole 6 b, resulting in the formation of metal spacers 8 c, on the sides via hole 6 b. This is schematically shown in FIG. 6 . Metal sidewalls 8 c, form a metal ring, or metal shunt structure, overlying a portion of underlying, recessed tungsten plug structure 7 b. Removal of photoresist shape 9 , via plasma oxygen ashing and careful wet cleans, results in the creation of upper level, metal interconnect structure 20 , shown schematically in FIG. 7B . Upper level, metal interconnect structure 20 , is comprised of metal interconnect component 8 b, and the attached metal ring component, comprised of metal spacers 8 c. The electrical and physical connection between lower level, metal interconnect structure 10 , and upper level, metal interconnect structure 20 , is realized using recessed tungsten plug structure 7 b, wherein upper level, metal interconnect structure 20 , is self-aligned to recessed metal plug structure 7 b, via the metal ring component, or metal spacers 8 c, attached to metal interconnect structure 8 b. This process sequence, requiring only a portion of metal layer residing in via hole 7 a, to be protected during the patterning procedure, allows a greater degree of mis-alignment, between defining photoresist shape 9 , and via hole 6 b, to be tolerated when compared to counterparts fabricated without a recessed tungsten plug, and without metal spacers on the sides of via hole 6 b. The process sequence, described in this invention, can be used to fabricate high density, high speed SRAM cells, as well as other high density memory and logic cells, A top view of the upper level, interconnect structure, featuring the attached metal ring component, is schematically shown in FIG. 7A . While this invention has been particularly shown and described with reference to, the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention