DISPLAY DEVICE

A display device includes a substrate including a display area surrounded by a non-display area, a bank structure disposed on the substrate in the display area and including a plurality of openings, a plurality of light emitting elements disposed in the openings, a first dam disposed on the substrate in the non-display area and spaced apart from the bank structure, and a second dam spaced apart from the first dam in the non-display area, wherein the bank structure includes a first bank layer and a second bank layer disposed on the first bank layer, wherein the first dam includes a first sub-dam structure and a second sub-dam structure disposed on the first sub-dam structure, and the second bank layer includes tips protruding from sidewalls of the first bank layer, and the second sub-dam structure includes tips protruding from sidewalls of the first sub-dam structure.

This application claims priority from Korean Patent Application No. 10-2023-0058243, filed on May 4, 2023, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference.

BACKGROUND

The disclosure relates to a display device.

2. Description of the Related Art

As the information society develops, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smartphones, digital cameras, laptop computers, navigation devices, and smart televisions. The display devices may be flat panel display devices such as liquid crystal display devices, field emission display devices, or organic light emitting display devices. Among such flat panel display devices, a light emitting display device may display an image without a backlight unit providing light to a display panel because each of pixels of the display panel includes light emitting elements that may emit light by themselves.

SUMMARY

Embodiments of the invention provide a display device including structures disposed at the outermost portions of a display area and a non-display area.

However, embodiments of the invention are not restricted to those set forth herein. The above and other aspects of the invention will become more apparent to one of ordinary skill in the art to which the invention pertains by referencing the detailed description of the invention given below.

A display device according to an embodiment may include dams having the same structure as a bank structure disposed in a display area and disposed in a non-display area. In the display device, even though an inorganic material layer disposed in the display area is used, the dams in the non-display area may have a sufficient height.

The effects of the disclosure are not limited to the aforementioned effects, and various other effects are included in the specification.

According to an embodiment of the disclosure, a display device includes a substrate including a display area and a non-display area surrounding the display area, a bank structure disposed on the substrate in the display area and including a plurality of openings, a plurality of light emitting elements disposed in the openings of the bank structure in the display area, a first dam disposed on the substrate in the non-display area and spaced apart from the bank structure, and a second dam spaced apart from the first dam in the non-display area, wherein the bank structure includes a first bank layer and a second bank layer disposed on the first bank layer and including a metal material different from that of the first bank layer, wherein the first dam includes a first sub-dam structure including the same material as the first bank layer and a second sub-dam structure disposed on the first sub-dam structure and including the same material as the second bank layer, and the second bank layer includes tips protruding from sidewalls of the first bank layer, and the second sub-dam structure includes tips protruding from sidewalls of the first sub-dam structure.

In an embodiment, the first dam may further include a first sub-dam, and the first sub-dam structure may be disposed on the first sub-dam.

In an embodiment, the first dam further may include an insulating pattern disposed on the first sub-dam and a spacer disposed on the second sub-dam structure, the insulating pattern may be disposed to surround the first sub-dam, and the spacer may be disposed to cover outer surfaces of the insulating pattern, the first sub-dam structure, and the second sub-dam structure.

In an embodiment, the second dam may include the same layers as the first sub-dam, the first sub-dam structure, and the second sub-dam structure, respectively, and the second dam may further include a second sub-dam disposed below the first sub-dam.

In an embodiment, the display device may further include a first via layer disposed between the bank structure and the substrate in the display area, and a second via layer disposed on the first via layer, wherein the first sub-dam may include the same material as the second via layer, and the second sub-dam may include the same material as the first via layer.

In an embodiment, the display area may include a first display area and a second display area surrounded by the first display area, and the display device may further include a hole dam disposed to surround the second display area.

In an embodiment, the hole dam may be spaced apart from the bank structure and include the first sub-dam structure and the second sub-dam structure.

In an embodiment, the display device may further include a bank connection part connecting the first dam and the bank structure to each other.

In an embodiment, the first dam may further include an insulating pattern, and the first sub-dam structure may be directly disposed on the insulating pattern.

In an embodiment, the display device may further include a third dam disposed to be spaced apart from the second dam, wherein the second dam may include a first sub-dam and a spacer disposed on the first sub-dam, and the third dam may include the first sub-dam, a second sub-dam disposed below the first sub-dam, and a spacer disposed on the first sub-dam.

In an embodiment, the first bank layer and the first sub-dam structure may include aluminum (Al), and the second bank layer and the second sub-dam structure may include titanium (Ti).

In an embodiment, the light emitting element may include an anode electrode disposed to overlap the opening, a light emitting layer disposed on the anode electrode, and a cathode electrode disposed on the light emitting layer, wherein the cathode electrode may be in contact with side surfaces of the first bank layer.

In an embodiment, the display device may further include an organic pattern disposed around the opening on the second bank layer and including the same material as the light emitting layer, an electrode pattern disposed on the organic pattern and including the same material as the cathode electrode, and an inorganic layer disposed to cover the light emitting element and the electrode pattern.

In an embodiment, the display device may further include a first power line disposed in the non-display area, wherein the first dam may be disposed on the first power line, and the bank structure is in contact with the first power line.

According to an embodiment, a display device includes a display area and a non-display area disposed around the display area, a bank structure disposed in the display area and including a plurality of openings in which a plurality of light emitting elements are disposed, a first dam disposed in the non-display area, spaced apart from the bank structure, and disposed to surround the bank structure, and a second dam spaced apart from the first dam in the non-display area and disposed to surround the first dam, wherein the bank structure includes a first bank layer and a second bank layer disposed on the first bank layer and including a metal material that is different from that of the first bank layer, wherein the first dam includes a dam structure including a first sub-dam structure including the same material as the first bank layer and a second sub-dam structure including the same material as the second bank layer and disposed on the first sub-dam structure, wherein the second bank layer includes tips protruding from sidewalls of the first bank layer, and the second sub-dam structure includes tips protruding from sidewalls of the first sub-dam structure.

In an embodiment, the first dam further may include a first sub-dam overlapping the dam structure, and the second dam may include the dam structure and the first sub-dam and may further include a second sub-dam overlapping the first sub-dam.

In an embodiment, each of the first dam and the second dam may further include an insulating pattern overlapping the first sub-dam and a spacer disposed on the dam structure.

In an embodiment, the display area may include a first display area and a second display area surrounded by the first display area, wherein the display device may further include a hole dam surrounding the second display area, disposed to be spaced apart from the bank structure, and including the dam structure.

In an embodiment, the second dam may include a first sub-dam, and the display device may further include a third dam disposed to be spaced apart from the second dam and to surround the second dam, and including the first sub-dam and a second sub-dam overlapping the first sub-dam.

In an embodiment, the first sub-dam of the second dam and the first sub-dam of the third dam may include the same material.

DETAILED DESCRIPTION

It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numbers indicate the same components throughout the specification. In the attached drawing figures, the thickness of layers and regions may be exaggerated for clarity.

It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. For instance, a first element discussed below could be termed a second element without departing from the teachings of the invention. Similarly, the second element could also be termed the first element.

FIG.1is a perspective view of an electronic device, according to an embodiment.

In an embodiment and referring toFIG.1, an electronic device1displays a moving image and/or a still image. The electronic device1may refer to all electronic devices that provide display screens. For example, televisions, laptop computers, monitors, billboards, the Internet of Things (IoT), mobile phones, smartphones, tablet personal computers (PCs), electronic watches, smart watches, watch phones, head mounted displays, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, game machines, digital cameras, camcorders, and the like, which provide display screens, may be included in the electronic device1.

In an embodiment, the electronic device1may include a display device10(seeFIG.2) providing a display screen. Examples of the display device may include an inorganic light emitting diode display device, an organic light emitting display device, a quantum dot light emitting display device, a plasma display device, a field emission display device, and the like. Hereinafter, a case where an inorganic light emitting diode display device is applied as an example of the display device will be described by way of example, but the invention is not limited thereto, and the same technical scope may be applied to other display devices if applicable.

In an embodiment, a shape of the electronic device1may be variously modified. For example, the electronic device1may have a shape such as a rectangular shape with a width greater than a length, a rectangular shape with a length greater than a width, a square shape, a rectangular shape with rounded corners (vertices), other polygonal shapes, or a circular shape. A shape of a display area DA of the electronic device1may also be similar to an overall shape of the electronic device1. InFIG.1, the electronic device1having a rectangular shape with a great length in a second direction DR2has been illustrated.

In an embodiment, the electronic device1may include a display area DA and a non-display area NDA. The display area DA is an area in which a screen may be displayed, and the non-display area NDA is an area in which a screen is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may occupy substantially the center of the electronic device1.

In an embodiment, the display area DA may include a first display area DA1and a second display area DA2. The second display area DA2is an area in which components for adding various functions to the electronic device1are disposed, and may correspond to a component area.

FIG.2is a perspective view illustrating a display device included in the electronic device1, according to an embodiment.

Referring toFIG.2, the electronic device1, according to an embodiment, may include a display device10. The display device10may provide a screen displayed by the electronic device1. The display device10may have a shape similar to that of the electronic device1in a plan view. For example, the display device10may have a shape similar to a rectangular shape having short sides in a first direction DR1and long sides in the second direction DR2. A corner where the short side in the first direction DR1and the long side in the second direction DR2meet may be rounded with a curvature, but is not limited thereto, and may also be right-angled. The shape of the display device10in a plan view is not limited to the rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

In an embodiment, the display device10may include a display panel100, a display driver200, a circuit board300, and a touch driver400.

In an embodiment, the display panel100may include a main area MA and a sub-area SBA.

In an embodiment, the main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may include a first display area DA1and a second display area DA2. The display area DA may emit light from a plurality of emission areas and/or a plurality of opening areas. For example, the display panel100may include pixel circuits including switching elements, a pixel defining film defining the emission areas and/or the opening areas, and self-light emitting elements.

For example, in an embodiment, the self-light emitting elements may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

In an embodiment, the non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of the main area MA of the display panel100. The non-display area NDA may include a gate driver (not illustrated) supplying gate signals to gate lines, and/or fan-out lines (not illustrated) connecting the display driver200and the display area DA to each other.

In an embodiment, the sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material that may be bent, folded, and/or rolled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap the main area MA in a thickness direction (third direction DR3). The sub-area SBA may include the display driver200and pad parts connected to the circuit board300. In another embodiment, the sub-area SBA may be omitted, and the display driver200and the pad parts may be disposed in the non-display area NDA.

In an embodiment, the display driver200may output signals and voltages for driving the display panel100. The display driver200may supply data voltages to data lines. The display driver200may supply source voltages to power lines and supply gate control signals to the gate driver. The display driver200may be formed as an integrated circuit (IC) and may be mounted on the display panel100in a chip on glass (COG) manner, a chip on plastic (COP) manner, or an ultrasonic bonding manner. As an example, the display driver200may be disposed in the sub-area SBA, and may overlap the main area MA in the thickness direction by bending of the sub-area SBA. As another example, the display driver200may be mounted on the circuit board300.

In an embodiment, the circuit board300may be attached onto the pad parts of the display panel100using an anisotropic conductive film (ACF). Lead lines of the circuit board300may be electrically connected to the pad parts of the display panel100. The circuit board300may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

In an embodiment, the touch driver400may be mounted on the circuit board300. The touch driver400may be connected to a touch sensing unit of the display panel100. The touch driver400may supply touch driving signals to a plurality of touch electrodes of the touch sensing unit and may sense change amounts in capacitance between the plurality of touch electrodes. For example, the touch driving signal may be a pulse signal having a predetermined frequency. The touch driver400may decide whether or not an input has occurred and calculate input coordinates, based on the change amounts in capacitance between the plurality of touch electrodes. The touch driver400may be formed as an integrated circuit (IC).

FIG.3is a cross-sectional view of the display device ofFIG.2viewed from the side, according to an embodiment.

In an embodiment and referring toFIG.3, the display panel100may include a display layer DU, a touch sensing layer TSU, and a color filter layer CFL. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and a thin film encapsulation layer TFEL.

In an embodiment, the substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that may be bent, folded, and/or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material and/or a metal material.

In an embodiment, the thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting pixel circuits of pixels. The thin film transistor layer TFTL may further include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver200and the data lines to each other, and lead lines connecting the display driver200and the pad parts to each other. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the gate driver is formed on one side of the non-display area NDA of the display panel100, the gate driver may include thin film transistors.

In an embodiment, the thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors of each of the pixels, the gate lines, the data lines, and the power lines of the thin film transistor layer TFTL may be disposed in the display area DA. The gate control lines and the fan-out lines of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead lines of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

In an embodiment, the light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements each including a first electrode, a second electrode, and a light emitting layer to emit light and a pixel defining film defining the pixels. The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

In an embodiment, the light emitting layer may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transporting layer, an organic light emitting layer, and an electron transporting layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively, and may be combined with each other in the organic light emitting layer to emit light.

In another embodiment, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, and/or a micro light emitting diode.

The display device10according to an embodiment may include a plurality of color filters CF1, CF2, and CF3(seeFIGS.5and6) disposed on the light emitting elements of the light emitting element layer EML. Each of the color filters may selectively transmit light of a specific wavelength therethrough and block and/or absorb light of other wavelengths. The color filters may absorb some of light introduced from the outside of the display device to reduce reflected light by external light. Accordingly, the color filters may prevent distortion of colors due to external light reflection. Since the color filters are disposed on the light emitting elements, the display device10may not require a separate substrate for the color filters. Accordingly, a thickness of the display device10may be relatively small.

In an embodiment, the thin film encapsulation layer TFEL may cover an upper surface and side surfaces of the light emitting element layer EML, and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

In an embodiment, the touch sensing layer TSU may be disposed on the thin film encapsulation layer TFEL. The touch sensing layer TSU may include a plurality of touch electrodes for sensing a user's touch in a capacitance manner and touch lines connecting the plurality of touch electrodes and the touch driver400to each other. For example, the touch sensing layer TSU may sense the user's touch using a mutual capacitance manner or a self-capacitance manner.

In another embodiment, the touch sensing layer TSU may be disposed on a separate substrate disposed on the display layer DU. In this case, the substrate supporting the touch sensing layer TSU may be a base member encapsulating the display layer DU.

In an embodiment, the plurality of touch electrodes of the touch sensing layer TSU may be disposed in a touch sensor area overlapping the display area DA. The touch lines of the touch sensing layer TSU may be disposed in a touch peripheral area overlapping the non-display area NDA.

In some embodiments, the display device10may further include an optical device500. The optical device500may be disposed in the second display area DA2. The optical device500may emit and/or receive light of infrared, ultraviolet, and/or visible light bands. For example, the optical device500may be an optical sensor sensing light incident on the display device10, such as a proximity sensor, an illuminance sensor, and a camera sensor or an image sensor.

In an embodiment, the color filter layer CFL may be disposed on the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters each corresponding to the plurality of emission areas. Each of the color filters may selectively transmit light of a specific wavelength therethrough and block and/or absorb light of other wavelengths. The color filter layer CFL may absorb some of light introduced from the outside of the display device10to reduce reflected light by external light. Accordingly, the color filter layer CFL may prevent distortion of colors due to external light reflection.

In an embodiment, since the color filter layer CFL is directly disposed on the thin film encapsulation layer TFEL, the display device10may not require a separate substrate for the color filter layer CFL. Accordingly, a thickness of the display device10may be relatively small.

FIG.4is a plan view illustrating a display layer of the display device10, according to an embodiment.

In an embodiment and referring toFIG.4, the display layer DU may include a display area DA and a non-display area NDA.

In an embodiment, the display area DA may be disposed at the center of the display panel100(seeFIG.2). A plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and some (e.g., second power lines VL2) of a plurality of power lines may be disposed in the display area DA. Each of the plurality of pixels PX may be defined as a minimum unit emitting light.

In an embodiment, the plurality of gate lines GL may supply gate signals received from a gate driver210to the plurality of pixels PX. The plurality of gate lines GL may extend in the first direction DR1, and may be spaced apart from each other in the second direction DR2crossing the first direction DR1.

In an embodiment, the plurality of data lines DL may supply data voltages received from the display driver200to the plurality of pixels PX. The plurality of data lines DL may extend in the second direction DR2, and may be spaced apart from each other in the first direction DR1.

In an embodiment, the second power lines VL2of the plurality of power lines may supply a source voltage received from the display driver200to the plurality of pixels PX. Here, the source voltage may be at least one of a driving voltage, an initialization voltage, and a reference voltage. A plurality of second power lines VL2may extend in the second direction DR2, and may be spaced apart from each other in the first direction DR1.

In an embodiment, the non-display areas NDA may surround the display area DA. Some (e.g., a first power line VL1) of the plurality of power lines, the gate driver210, fan-out lines FOL, and gate control lines GCL may be disposed in the non-display area NDA. The gate driver210may generate a plurality of gate signals based on gate control signals, and may sequentially supply the plurality of gate signals to the plurality of gate lines GL according to a set order.

In an embodiment, the fan-out lines FOL may extend from the display driver200to the display area DA. The fan-out lines FOL may supply the data voltages received from the display driver200to the plurality of data lines DL.

In an embodiment, the gate control lines GCL may extend from the display driver200to the gate driver210. The gate control lines GCL may supply the gate control signals received from the display driver200to the gate driver210. It has been illustrated inFIG.4that the gate driver210is disposed only in a non-display area NDA and disposed on the left side of the display area DA, but the invention is not limited thereto. In some embodiments, the display device10may include a plurality of gate drivers210disposed respectively on the left side and/or the right side of the display area DA.

In an embodiment, the first power line VL1of the plurality of power lines may be disposed in the non-display area NDA while surrounding the display area DA. The first power line VL1may supply a source voltage received from the display driver200to the plurality of pixels PX. Here, the source voltage may be a low potential source voltage. The first power line VL1may be electrically connected to the display driver200in the non-display area NDA disposed on the lower side of the display area DA, and may be disposed to surround the display area DA by including portions extending in the first direction DR1and the second direction DR2. The first power line VL1may be electrically connected to a bank structure BNS (seeFIG.6) to be described later at left and right outer portions of the display layer DU. The first power line VL1may be electrically connected to the plurality of pixels PX of the display area DA through the bank structure BNS.

In an embodiment, the sub-area SBA may include the display driver200, a pad area PA, and first and second touch pad areas TPA1and TPA2, respectively.

In an embodiment, the display driver200may output signals and voltages for driving the display panel100to the fan-out lines FOL. The display driver200may supply the data voltages to the data lines DL through the fan-out lines FOL. The data voltages may be supplied to the plurality of pixels PX, and may control luminance of the plurality of pixels PX. The display driver200may supply the gate control signals to the gate driver210through the gate control lines GCL.

In an embodiment, the pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2may be disposed at an edge of the sub-area SBA. The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2may be electrically connected to the circuit board300using a material such as an anisotropic conductive film or a self-assembly anisotropic conductive paste (SAP).

In an embodiment, the pad area PA may include a plurality of display pad parts DP. The plurality of display pad parts DP may be connected to a graphic system through the circuit board300. The plurality of display pad parts DP may be connected to the circuit board300to receive digital video data, and may supply the digital video data to the display driver200.

FIG.5is a plan view illustrating arrangements of emission areas and color filters in a display area of the display device10, according to an embodiment.

In an embodiment and referring toFIG.5, the display device10may include a plurality of emission areas EA1, EA2, and EA3disposed in the display area DA. The display area DA illustrated inFIG.5is the first display area DA1, and the plurality of emission areas EA1, EA2, and EA3may be disposed in the first display area DA1.

In an embodiment, the emission areas EA1, EA2, and EA3may include first emission areas EA1, second emission areas EA2, and third emission areas EA3that emit light of different colors. The first to third emission areas EA1, EA2, and EA3, respectively, may emit red, green, or blue light, respectively, and colors of the light emitted from the respective emission areas EA1, EA2, and EA3may be different depending on the types of light emitting element ED1, ED2, and ED3(seeFIG.6) are disposed at a light emitting element layer EML to be described later. In an embodiment, the first emission area EA1may emit first light, which is the red light, the second emission area EA2may emit second light, which is the green light, and the third emission area EA3may emit third light, which is the blue light. However, the invention is not limited thereto.

In an embodiment, the plurality of emission areas EA1, EA2, and EA3may be disposed in a PenTile™ type, for example, a diamond PenTile™ type. For example, the first emission areas EA1and the third emission areas EA3may be disposed to be spaced apart from each other in the first direction DR1, and may be alternately disposed in the first direction DR1and the second direction DR2. In an arrangement of the emission areas EA1, EA2, and EA3, the first emission areas EA1and the third emission areas EA3may be alternately disposed in the first direction DR1in a first row R1and a third row R3. The first emission areas EA1and the third emission areas EA3may be alternately disposed in the second direction DR2in a first column C1and a third column C3.

In an embodiment, the second emission areas EA2may be spaced apart from other adjacent second emission areas EA2in the first direction DR1and the second direction DR2, and may be spaced apart from adjacent first emission areas EA1and third emission areas EA3in a fourth direction DR4or a fifth direction DR5. A plurality of second emission areas EA2may be repeatedly disposed along the first direction DR1and the second direction DR2, and the second emission areas EA2and the first emission areas EA1or the second emission areas EA2and the third emission areas EA3may be alternately disposed along the fourth direction DR4or the fifth direction DR5. In the arrangement of the emission areas EA1, EA2, and EA3, the second emission areas EA2may be repeatedly disposed in the first direction DR1in a second row R2and a fourth row R4, and the second emission areas EA2may be repeatedly disposed in the second direction DR2in a second column C2and a fourth column C4.

In an embodiment, the first to third emission areas EA1, EA2, and EA3, respectively, may be defined, respectively, by a plurality of openings OPE1, OPE2, and OPE3formed in a bank structure BNS (seeFIG.6) of a light emitting element layer EML to be described later. For example, the first emission area EA1may be defined by a first opening OPE1of the pixel defining film, the second emission area EA2may be defined by a second opening OPE2of the pixel defining film, and the third emission area EA3may be defined by a third opening OPE3of the pixel defining film.

In an embodiment, areas of the emission areas EA1, EA2, and EA3may change depending on sizes of the openings OPE1, OPE2, and OPE3of the bank structure. Intensities of the light emitted from the emission areas EA1, EA2, and EA3may change depending on the areas of the emission areas EA1, EA2, and EA3, and a color feeling of a screen displayed on the display device10or the electronic device1may be controlled by adjusting the areas of the emission area EA1, EA2, and EA3. In an embodiment, areas or sizes of the first to third emission areas EA1, EA2, and EA3, respectively, may be the same as each other. In an embodiment ofFIG.5, areas or diameters of the first emission area EA1, the second emission area EA2, and the third emission area EA3may be the same as each other.

However, the invention is not limited thereto. In an embodiment, the areas of the emission areas EA1, EA2, and EA3may be freely adjusted according to a color feeling of the screen required by the display device10and the electronic device1. In addition, the areas of the emission areas EA1, EA2, and EA3may be related to light efficiency, lifespan of light emitting elements ED, and the like, and may have a trade-off relationship with external light reflection. The areas of the emission areas EA1, EA2, and EA3may be adjusted in consideration of the above factors. For example, in the display device10, an area of the third emission area EA3may be greater than areas of the first emission area EA1and the second emission area EA2, and an area of the first emission area EA1may be greater than an area of the second emission area EA2.

In an embodiment, in the display device10having the arrangement of the emission areas EA1, EA2, and EA3as illustrated inFIG.5, one first emission area EA1, two second emission areas EA2, and one third emission area EA3disposed adjacent to each other may form one pixel group. One pixel group may include the emission areas EA1, EA2, and EA3emitting light of different colors to express a white gradation. However, the invention is not limited thereto, and a combination of the emission areas EA1, EA2, and EA3constituting one pixel group may be variously modified depending on an arrangement of the emission areas EA1, EA2, and EA3, colors of the light emitted by the emission areas EA1, EA2, and EA3, and the like.

In an embodiment, the display device10may include a plurality of color filters CF1, CF2, and CF3disposed on the emission areas EA1, EA2, and EA3. The plurality of color filters CF1, CF2, and CF3may be disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3may be disposed in a plurality of opening holes OPT1, OPT2, and OPT3of a light blocking layer BM (seeFIG.6) disposed to correspond to the emission areas EA1, EA2, and EA3or the openings OPE1, OPE2, and OPE3, respectively. The opening holes OPT1, OPT2, and OPT3of the light blocking layer may be formed to overlap the openings OPE1, OPE2, and OPE3, respectively, and may form light emitting areas through which the light emitted from the emission areas EA1, EA2, and EA3is emitted. Each of the color filters CF1, CF2, and CF3may have a greater area than each of the openings OPE1, OPE2, and OPE3, and may completely cover each of the light emitting areas formed by the opening holes OPT1, OPT2, and OPT3of the light blocking layer BM.

In an embodiment, the color filters CF1, CF2, and CF3may include first color filters CF1, second color filters CF2, and third color filters CF3disposed to correspond to different emission areas EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3may include colorants, such as dyes or pigments, absorbing light of wavelength bands other than light of a specific wavelength band, and may be disposed to correspond to the colors of the light emitting from the emission areas EA1, EA2, and EA3. For example, the first color filter CF1may be a red color filter disposed to overlap the first emission area EA1and transmitting only the first light, which is the red light, therethrough. The second color filter CF2may be a green color filter disposed to overlap the second emission area EA2and transmitting only the second light, which is the green light, therethrough, and the third color filter CF3may be a blue color filter disposed to overlap the third emission area EA3and transmitting only the third light, which is the blue light, therethrough.

In an embodiment, similar to the arrangement of the emission areas EA1, EA2, and EA3, the color filters CF1, CF2, and CF3may be disposed in a PenTile™ type, for example, a diamond PenTile™ type. For example, the first color filters CF1and the third color filters CF3may be alternately disposed in the first direction DR1and the second direction DR2. In an arrangement of the color filters CF1, CF2, and CF3, the first color filters CF1and the third color filters CF3may be alternately disposed in the first direction DR1in the first row R1and the third row R3. The first color filters CF1and the third color filters CF3may be alternately disposed in the second direction DR2in the first column C1and the third column C3.

In an embodiment, the second color filters CF2may be spaced apart from other adjacent second color filters CF2in the first direction DR1and the second direction DR2, and may be spaced apart from adjacent first color filters CF1and third color filters CF3in the fourth direction DR4or the fifth direction DR5. A plurality of second color filters CF2may be repeatedly disposed along the first direction DR1and the second direction DR2, and the second color filters CF2and the first color filters CF1or the second color filters CF2and the third color filters CF3may be alternately disposed along the fourth direction DR4or the fifth direction DR5. In the arrangement of the color filters CF1, CF2, and CF3, the second color filters CF2may be repeatedly disposed in the first direction DR1in the second row R2and the fourth row R4, and the second color filters CF2may be repeatedly disposed in the second direction DR2in the second column C2and the fourth column C4.

FIG.6is a cross-sectional view illustrating a portion of the display device10, according to an embodiment.FIG.7is an enlarged view illustrating a first emission area ofFIG.6, according to an embodiment. In an embodiment,FIG.6is a partial cross-sectional view of the display device10, and illustrates cross sections of the substrate SUB, the thin film transistor layer TFTL, the light emitting element layer EML, and the thin film encapsulation layer TFEL of the display layer DU, the touch sensing layer TSU, and the color filter layer CFL.FIG.7illustrates a first light emitting element ED1disposed in a first emission area EA1and a portion of a bank structure BNS around the first light emitting element ED1inFIG.6.

In an embodiment and referring toFIGS.6and7in addition toFIG.5, the display panel100of the display device10(seeFIG.3) may include the display layer DU. The display layer DU may include the substrate SUB, the thin film transistor layer TFTL, the light emitting element layer EML, and the thin film encapsulation layer TFEL. The display panel100may include a light blocking layer BM disposed on the thin film encapsulation layer TFEL, and color filters CF1, CF2, and CF3of the color filter layer CFL may be disposed on the light blocking layer BM.

In an embodiment, the substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that may be bent, folded, and/or rolled. As an example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate SUB may include a glass material or a metal material.

In an embodiment, the thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, first thin film transistors TFT1, a gate insulating layer GI, a first interlayer insulating layer ILD1, capacitor electrodes CPE, a second interlayer insulating layer ILD2, first connection electrodes CNE1, a first via layer VIA1, second connection electrodes CNE2, and a second via layer VIA2.

In an embodiment, the first buffer layer BF1may be disposed on the substrate SUB. The first buffer layer BF1may include an inorganic film capable of preventing permeation of air or moisture. For example, the first buffer layer BF1may include a plurality of inorganic films that are alternately stacked.

In an embodiment, the lower metal layer BML may be disposed on the first buffer layer BF1. For example, the lower metal layer BML may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

In an embodiment, the second buffer layer BF2may cover the first buffer layer BF1and the lower metal layer BML. The second buffer layer BF2may include an inorganic film capable of preventing permeation of air or moisture. For example, the second buffer layer BF2may include a plurality of inorganic films that are alternately stacked.

In an embodiment, the first thin film transistor TFT1may be disposed on the second buffer layer BF2, and may constitute a pixel circuit of each of the plurality of pixels. For example, the first thin film transistor TFT1may be a driving transistor or a switching transistor of the pixel circuit disposed in the display area DA. The first thin film transistor TFT1may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

In an embodiment, the semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction, and may be insulated from the gate electrode GE by the gate insulating layer GI. A material of the semiconductor layer ACT in portions of the semiconductor layer ACT may become conductors to form the source electrode SE and the drain electrode DE.

In an embodiment, the gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer GI interposed therebetween.

In an embodiment, the gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2, and may insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer GI may include contact holes through which the first connection electrodes CNE1penetrate.

In an embodiment, the first interlayer insulating layer ILD1may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1may include contact holes through which the first connection electrodes CNE1penetrate. The contact holes of the first interlayer insulating layer ILD1may be connected to the contact holes of the gate insulating layer GI and contact holes of the second interlayer insulating layer ILD2.

In an embodiment, the capacitor electrodes CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in the thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitance.

In an embodiment, the second interlayer insulating layer ILD2may cover the capacitor electrodes CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2may include contact holes through which the first connection electrodes CNE1penetrate. The contact holes of the second interlayer insulating layer ILD2may be connected to the contact holes of the first interlayer insulating layer ILD1and the contact holes of the gate insulating layer GI.

In an embodiment, the first connection electrodes CNE1may be disposed on the second interlayer insulating layer ILD2. The first connection electrodes CNE1may electrically connect the drain electrodes DE of the first thin film transistors TFT1and the second connection electrodes CNE2to each other. The first connection electrodes CNE1may be inserted into the contact holes formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to be in contact with the drain electrodes DE of the first thin film transistors TFT1.

In an embodiment, the first via layer VIA1may cover the first connection electrodes CNE1and the second interlayer insulating layer ILD2. The first via layer VIA1may protect the first thin film transistors TFT1. The first via layer VIA1may include contact holes through which the second connection electrodes CNE2penetrate.

In an embodiment, the second connection electrodes CNE2may be disposed on the first via layer VIA1. The second connection electrodes CNE2may electrically connect the first connection electrodes CNE1and anode electrodes AE1, AE2, and AE3of light emitting elements ED to each other. The second connection electrodes CNE2may be inserted into the contact holes formed in the first via layer VIA1to be in contact with the first connection electrodes CNE1.

In an embodiment, the second via layer VIA2may cover the second connection electrodes CNE2and the first via layer VIA1. The second via layer VIA2may include contact holes through which the anode electrodes AE1, AE2, and AE3of the light emitting elements ED penetrate.

In an embodiment, the light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include the light emitting elements ED and a plurality of bank structures BNS. The light emitting elements ED may include the anode electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and cathode electrodes CE1, CE2, and CE3.

In an embodiment, the display device10may include a plurality of emission areas EA1, EA2, and EA3disposed in the display area DA. The emission areas EA1, EA2, and EA3may include a first emission area EA1, a second emission area EA2, and a third emission area EA3that emit light of different colors. The first to third emission areas EA1, EA2, and EA3, respectively, may emit red, green, or blue light, respectively, and colors of the light emitted from the emission areas EA1, EA2, and EA3may be different depending on the types of the light emitting elements ED disposed in the light emitting element layer EML. In an embodiment, the first emission area EA1may emit a first light, which is the red light, the second emission area EA2may emit a second light, which is the green light, and the third emission area EA3may emit a third light, which is the blue light. However, the invention is not limited thereto.

In an embodiment, the first to third emission areas EA1, EA2, and EA3, respectively, may be defined, respectively, by a plurality of openings OPE1, OPE2, and OPE3formed in the bank structure BNS of the light emitting element layer EML. For example, the first emission area EA1may be defined by a first opening OPEL of the bank structure BNS, the second emission area EA2may be defined by a second opening OPE2of the bank structure BNS, and the third emission area EA3may be defined by a third opening OPE3of the bank structure BNS.

In an embodiment, areas or sizes of the first to third emission areas EA1, EA2, and EA3, respectively, may be the same as each other. For example, in the display device10, the openings OPE1, OPE2, and OPE3of the bank structures BNS may have the same diameter, and the first emission area EA1, the second emission area EA2, and the third emission area EA3may have the same area. However, the invention is not limited thereto. In the display device10, areas or sizes of the first to third emission areas EA1, EA2, and EA3, respectively, may be different from each other. For example, an area of the second emission area EA2may be greater than areas of the first emission area EA1and the third emission area EA3, and an area of the third emission area EA3may be greater than an area of the first emission area EA1. Intensities of the light emitted from the emission areas EA1, EA2, and EA3may change depending on the areas of the emission areas EA1, EA2, and EA3, and a color feeling of a screen displayed on the display device10or the electronic device1may be controlled by adjusting the areas of the emission area EA1, EA2, and EA3. In an embodiment ofFIG.5, it has been illustrated that the areas of the emission areas EA1, EA2, and EA3are the same as each other, but the invention is not limited thereto. The areas of the emission areas EA1, EA2, and EA3may be freely adjusted according to a color feeling of the screen required by the display device10and the electronic device1. In addition, the areas of the emission areas EA1, EA2, and EA3may be related to light efficiency, lifespan of light emitting elements ED, and the like, and may have a trade-off relationship with external light reflection. The areas of the emission areas EA1, EA2, and EA3may be adjusted in consideration of the above factors.

In an embodiment, in the display device10, one first emission area EA1, one second emission area EA2, and one third emission area EA3disposed adjacent to each other may form one pixel group. One pixel group may include the emission areas EA1, EA2, and EA3emitting light of different colors to express a white gradation. However, the disclosure is not limited thereto, and a combination of the emission areas EA1, EA2, and EA3constituting one pixel group may be variously modified depending on an arrangement of the emission areas EA1, EA2, and EA3, colors of the light emitted by the emission areas EA1, EA2, and EA3, and/or the like.

In an embodiment, the display device10may include a plurality of light emitting elements ED1, ED2, and ED3disposed in different emission areas EA1, EA2, and EA3. The light emitting elements ED1, ED2, and ED3may respectively include a first light emitting element ED1disposed in the first emission area EA1, a second light emitting element ED2disposed in the second emission area EA2, and a third light emitting element ED3disposed in the third emission area EA3. The light emitting elements ED1, ED2, and ED3may include anode electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and cathode electrodes CE1, CE2, and CE3, respectively, and the light emitting elements ED1, ED2, and ED3disposed in the different emission areas EA1, EA2, and EA3, respectively, may emit light of different colors depending on materials of the light emitting layers EL1, EL2, and EL3, respectively. For example, the first light emitting element ED1disposed in the first emission area EA1may emit red light, which is light of a first color, the second light emitting element ED2disposed in the second emission area EA2may emit green light, which is light of a second color, and the third light emitting element ED3disposed in the third emission area EA3may emit blue light, which is light of a third color. The first to third emission areas EA1, EA2, and EA3, respectively, constituting one pixel may include the light emitting elements ED1, ED2, and ED3, respectively, emitting the light of the different colors to express a white gradation.

In an embodiment, the anode electrodes AE1, AE2, and AE3may be disposed on the second via layer VIA2. Each of the anode electrodes AE1, AE2, and AE3may be disposed to overlap any one of the openings OPE1, OPE2, and OPE3of the bank structure BNS. The anode electrodes AE1, AE2, and AE3may be electrically connected to the drain electrodes DE of the first thin film transistors TFT1through the first and second connection electrodes CNE1and CNE2.

In an embodiment, the anode electrodes AE1, AE2, and AE3may be disposed in the plurality of emission areas EA1, EA2, and EA3, respectively. The anode electrodes AE1, AE2, and AE3may include a first anode electrode AE1disposed in the first emission area EA1, a second anode electrode AE2disposed in the second emission area EA2, and a third anode electrode AE3disposed in the third emission area EA3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3may be disposed to be spaced apart from each other on the second via layer VIA2, respectively. The anode electrodes AE1, AE2, and AE3may be disposed in the different emission areas EA1, EA2, and EA3, respectively, to constitute the light emitting elements ED1, ED2, and

ED3emitting the light of the different colors, respectively.

In an embodiment, an inorganic insulating layer ISL may be disposed on the second via layer VIA2and the anode electrodes AE1, AE2, and AE3. The inorganic insulating layer ISL may be entirely disposed on the second via layer VIA2, but may expose portions of upper surfaces of the anode electrodes AE1, AE2, and AE3while partially overlapping the anode electrodes AE1, AE2, and AE3. The inorganic insulating layer ISL may expose the anode electrodes AE1, AE2, and AE3in portions thereof overlapping the openings OPE1, OPE2, and OPE3, respectively, of the bank structure BNS, and the light emitting layers EL1, EL2, and EL3disposed on the anode electrodes AE1, AE2, and AE3, respectively, may be directly disposed on the anode electrodes AE1, AE2, and AE3, respectively. The inorganic insulating layer ISL may include an inorganic insulating material. As an example, the inorganic insulating layer ISL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and/or silicon oxynitride.

According to an embodiment, the inorganic insulating layer ISL may be disposed on the anode electrodes AE1, AE2, and AE3, but may be spaced apart from the upper surfaces of the anode electrodes AE1, AE2, and AE3. The inorganic insulating layer ISL may not be in direct contact with the anode electrodes AE1, AE2, and AE3while partially overlapping the anode electrodes AE1, AE2, and AE3, and portions of the light emitting layers EL1, EL2, and EL3of the light emitting elements ED1, ED2, and ED3, respectively, may be disposed between the inorganic insulating layer ISL and the anode electrodes AE1, AE2, and AE3, respectively. In a manufacturing process of the display device10, a sacrificial layer may be disposed on the anode electrodes AE1, AE2, and AE3before the inorganic insulating layer ISL is formed. The inorganic insulating layer ISL may be disposed to cover portions of the sacrificial layer, and may then be spaced apart from the upper surfaces of the anode electrodes AE1, AE2, and AE3while the sacrificial layer is removed. The inorganic insulating layer ISL may have a shape in which it protrudes from residual patterns RP toward inner sides of the openings OPE1, OPE2, and OPE3. Thereafter, in a deposition process of the light emitting layers EL1, EL2, and EL3, portions of the inorganic insulating layer ISL may be disposed on the light emitting layers EL1, EL2, and EL3while materials forming the light emitting layers EL1, EL2, and EL3fill spaces between the inorganic insulating layer ISL and the anode electrodes AE1, AE2, and AE3, respectively. However, the inorganic insulating layer ISL may be in direct contact with side surfaces of the anode electrodes AE1, AE2, and AE3.

In an embodiment, the display device10may include the plurality of bank structures BNS disposed on the thin film transistor layer TFTL or the substrate SUB and including the plurality of openings OPE1, OPE2, and OPE3. The bank structure BNS may have a structure in which bank layers BN1and BN2including different materials are sequentially stacked, and may include the plurality of openings OPE1, OPE2, and OPE3forming the emission areas EA1, EA2, and EA3, respectively. The light emitting elements ED1, ED2, and ED3of the display device10may be disposed to overlap the openings OPE1, OPE2, and OPE3, respectively, of the bank structure BNS.

In an embodiment, the bank structure BNS may include a first bank layer BN1disposed on the inorganic insulating layer ISL and a second bank layer BN2disposed on the first bank layer BN1.

According to an embodiment, the first bank layer BN1and the second bank layer BN2may include different metal materials, and the second bank layer BN2of the bank structure BNS may include tips TIP protruding from the first bank layer BN1toward the openings OPE1, OPE2, and OPE3. In the bank structure BNS, sides of the first bank layer BN1may have a shape in which they are recessed inward from sides of the second bank layer BN2. In the bank structure BNS, the first bank layer BN1may have a greater thickness than the second bank layer BN2, and the second bank layer BN2may have a relatively small thickness and include the tips TIP formed in a manufacturing process. The second bank layer BN2has a shape in which it protrudes more than the first bank layer BN1toward the openings OPE1, OPE2, and OPE3, and accordingly, inner sidewalls of the openings OPE1, OPE2, and OPE3of the bank structure BNS may have undercuts formed under the tips TIP of the second bank layer BN2.

In an embodiment, a sidewall shape of the bank structure BNS may be a structure formed due to a difference in etch rate between the first bank layer BN1and the second bank layer BN2in an etching process because the first bank layer BN1and the second bank layer BN2include different materials. According to an embodiment, the second bank layer BN2may include a material having an etch rate that is slower than that of the first bank layer BN1, and the first bank layer BN1may be further etched in a process of forming the openings OPE1, OPE2, and OPE3of the bank structure BNS, such that the undercuts may be formed under the tips TIP of the second bank layer BN2. In an embodiment, the first bank layer BN1may include a metal material having high electrical conductivity, and the second bank layer BN2may include a metal material having low reflectivity. As an example, the first bank layer BN1may include aluminum (Al), and the second bank layer BN2may include titanium (Ti). The bank structure BNS may have a structure in which an Al layer and a Ti layer are stacked on the inorganic insulating layer ISL, and the tips TIP may be formed in the Ti layer of the second bank layer BN2.

In an embodiment, the bank structure BNS may include the openings OPE1, OPE2, and OPE3forming the emission areas EA1, EA2, and EA3, respectively, and the light blocking layer BM may be disposed on the bank structure BNS. The uppermost layer of the bank structure BNS may include a material having low reflectivity to reduce external light reflection. In addition, in the bank structure BNS, the first bank layer BN1may be electrically connected to the cathode electrodes CE1, CE2, and CE3of different light emitting elements ED1, ED2, and ED3, respectively. The cathode electrodes CE1, CE2, and CE3of the light emitting elements ED1, ED2, and ED3, respectively, disposed in the different emission areas EA1, EA2, and EA3, respectively, are not directly connected to each other, but may be electrically connected to each other through the first bank layer BN1of the bank structure BNS.

In an embodiment, in order to form the pixel defining film forming the emission areas EA1, EA2, and EA3using an organic material or form the light emitting layers EL1, EL2, and EL3of the light emitting elements ED1, ED2and ED3, respectively, for each of the emission areas EA1, EA2, and EA3, respectively, in the manufacturing process of the display device10, a mask process is required. The display device10may require a structure for mounting a mask in order to perform the mask process or require an unnecessarily great area of the non-display area NDA in order to control dispersion according to the mask process. When such a mask process is minimized, an unnecessary component such as the structure for mounting the mask may be omitted from the display device10, and the area of the non-display area NDA for controlling the dispersion may be minimized.

The display device10according to an embodiment includes the bank structure BNS forming the emission areas EA1, EA2, and EA3, and thus, the light emitting layers EL1, EL2, and EL3may be formed by deposition and etching processes instead of the mask process. In addition, the bank structure BNS includes the first bank layer BN1and the second bank layer BN2including the different metal materials to have a structure in which the inner sidewalls of the openings OPE1, OPE2, and OPE3include the tips TIP, and accordingly, it is possible to individually form different layers in the different emission areas EA1, EA2, and EA3even though the deposition process. For example, even though the light emitting layers EL1, EL2, and EL3and the cathode electrodes CE1, CE2, and CE3of the light emitting elements ED1, ED2, and ED3, respectively, are formed by a deposition process that does not use the mask, deposited materials may be disconnected from each other rather than being connected to each other between the openings OPE1, OPE2, and OPE3by the tips TIP of the second bank layer BN2formed on the inner sidewalls of the openings OPE1, OPE2, and OPE3. It is possible to form individually the different layers in the different emission areas EA1, EA2, and EA3through a process of forming a material for forming a specific layer on the entire surface of the display device10and then etching and removing a layer formed in unwanted areas. In the display device10, through the deposition and etching processes without using the mask process, the different light emitting elements ED1, ED2, and ED3may be formed for each of the emission areas EA1, EA2, and EA3, respectively, the unnecessary component may be omitted from the display device10, and the area of the non-display area NDA may be minimized.

In an embodiment, a first encapsulation layer TFE1of the thin film encapsulation layer TFEL may be disposed on the cathode electrodes CE1, CE2, and CE3of the light emitting elements ED1, ED2, and ED3, respectively. The first encapsulation layer TFE1may include a first inorganic layer TL1disposed on the first light emitting element ED1, a second inorganic layer TL2disposed on the second light emitting element ED2, and a third inorganic layer TL3disposed on the third light emitting element ED3. After the first to third inorganic layers TL1, TL2, and TL3, respectively, are entirely formed on the bank structure BNS, the first to third inorganic layers TL1, TL2, and TL3, respectively, may be disposed to cover only the light emitting elements ED1, ED2, and ED3, respectively, in the respective emission areas EA1, EA2, and EA3and organic patterns ELP1, ELP2, and ELP3and electrode patterns CEP1, CEP2, and CEP3to be described later, but may not be disposed between the emission areas EA1, EA2, and EA3. The inorganic layers TL1, TL2, and TL3may be formed in such a shape by forming the inorganic layers TL1, TL2, and TL3so as to completely cover the bank structure BNS and then partially patterning the inorganic layers TL1, TL2, and TL3.

In an embodiment, the display device10may include patterns that are traces according to a shape and a deposition process of the bank structure BNS. These patterns may be formed simultaneously with the light emitting layers EL1, EL2, and EL3and the cathode electrodes CE1, CE2, and CE3of the light emitting elements ED1, ED2, and ED3, respectively, and may remain on the bank structure BNS. Hereinafter, structures of the light emitting layers EL1, EL2, and EL3and the cathode electrodes CE1, CE2, and CE3, and the patterns will be described.

In an embodiment, the light emitting layers EL1, EL2, and EL3may be disposed on the anode electrodes AE1, AE2, and AE3, respectively. The light emitting layers EL1, EL2, and EL3may be organic light emitting layers made of an organic material, and may be formed on the anode electrodes AE1, AE2, and AE3, respectively, through a deposition process. When the first thin film transistors TFT1apply a predetermined voltage to the anode electrodes AE1, AE2, and AE3of the light emitting elements ED1, ED2, and ED3, respectively, and the cathode electrodes CE1, CE2, and CE3of the light emitting elements ED1, ED2, and ED3, respectively, receives a common voltage or a cathode voltage, holes and electrons may move to the light emitting layers EL1, EL2, and EL3through hole transporting layers and electron transporting layers, respectively, and may be combined with each other in the light emitting layers EL1, EL2, and EL3to emit light.

In an embodiment, the light emitting layers EL1, EL2, and EL3may include a first light emitting layer EL1, a second light emitting layer EL2, and a third light emitting layer EL3disposed in the different emission areas EA1, EA2, and EA3, respectively. The first light emitting layer EL1may be disposed on the first anode electrode AE1in the first emission area EA1, the second light emitting layer EL2may be disposed on the second anode electrode AE2in the second emission area EA2, and the third light emitting layer EL3may be disposed on the third anode electrode AE3in the third emission area EA3. The first to third light emitting layers EL1, EL2, and EL3, respectively, may be light emitting layers of the first to third light emitting elements ED1, ED2and ED3, respectively. The first light emitting layer EL1may be a light emitting layer emitting the red light, which is the light of the first color, the second light emitting layer EL2may be a light emitting layer emitting the green light, which is the light of the second color, and the third light emitting layer EL3may be a light emitting layer emitting the blue light, which is the light of the third color.

According to an embodiment, portions of the light emitting layers EL1, EL2, and EL3of the light emitting elements ED1, ED2, and ED3, respectively, may be disposed between the anode electrodes AE1, AE2, and AE3, respectively, and the inorganic insulating layer ISL. The inorganic insulating layer ISL may be disposed on the anode electrodes AE1, AE2, and AE3, but may be spaced apart from the upper surfaces of the anode electrodes AE1, AE2, and AE3. The deposition process of the light emitting layers EL1, EL2, and EL3may be performed so that materials of the light emitting layers are deposited in a direction inclined with respect to an upper surface of the substrate SUB rather than a direction perpendicular to the upper surface of the substrate SUB. Accordingly, the light emitting layers EL1, EL2, and EL3may be disposed on the upper surfaces of the anode electrodes AE1, AE2, and AE3, respectively, exposed in the openings OPE1, OPE2, and OPE3, respectively, of the bank structure BNS, and may be disposed to fill spaces between the anode electrodes AE1, AE2, and AE3, respectively, and the inorganic insulating layer ISL.

As described above, in an embodiment, in the manufacturing process of the display device10, the sacrificial layer may be disposed between the inorganic insulating layer ISL and the anode electrodes AE1, AE2, and AE3, and the light emitting layers EL1, EL2, and EL3may then be disposed in areas in which the sacrificial layer is partially removed. Accordingly, a lower surface of the inorganic insulating layer ISL may be spaced apart from the anode electrodes AE1, AE2, and AE3. However, the sacrificial layer may remain as partial residual patterns RP in areas between the inorganic insulating layer ISL and the anode electrodes AE1, AE2, and AE3. The areas between the inorganic insulating layer ISL and the anode electrodes AE1, AE2, and AE3may be filled with the partial residual patterns RP and the light emitting layers EL1, EL2, and EL3, respectively.

The display device10according to an embodiment may include a plurality of organic patterns ELP1, ELP2, and ELP3including the same materials as the light emitting layers EL1, EL2, and EL3, respectively, and disposed on the bank structure BNS. Since the light emitting layers EL1, EL2, and EL3are formed through a process of depositing materials on the entire surface of the display device10, the materials forming the light emitting layers EL1, EL2, and EL3may be deposited on the bank structure BNS as well as in the openings OPE1, OPE2, and OPE3, respectively, of the bank structure BNS.

For example, in an embodiment, the display device10may include the organic patterns ELP1, ELP2, and ELP3disposed above the bank structure BNS. The organic patterns ELP1, ELP2, and ELP3may include a first organic pattern ELP1, a second organic pattern ELP2, and a third organic pattern ELP3disposed on the second bank layer BN2of the bank structure BNS.

In an embodiment, the first organic pattern ELP1may include the same material as the first light emitting layer EL1of the first light emitting element ED1. The second organic pattern ELP2may include the same material as the second light emitting layer EL2of the second light emitting element ED2, and the third organic pattern ELP3may include the same material as the third light emitting layer EL3of the third light emitting element ED3. The organic patterns ELP1, ELP2, and ELP3may be formed in the same processes as the light emitting layers EL1, EL2, and EL3, respectively, including the same materials as the organic patterns ELP1, ELP2, and ELP3, respectively.

In an embodiment, the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3may be directly disposed on the second bank layer BN2of the bank structure BNS. The organic patterns ELP1, ELP2, and ELP3may be formed in the same processes as the light emitting layers EL1, EL2, and EL3, respectively, including the same materials as the organic patterns ELP1, ELP2, and ELP3, respectively, and may be disposed adjacent to the emission areas EA1, EA2, and EA3, respectively, in which the respective light emitting layers EL1, EL2, and EL3are disposed. For example, the first organic pattern ELP1may be disposed on the second bank layer BN2while surrounding the first opening OPE1around the first emission area EA1or the first opening OPE1. The second organic pattern ELP2may be disposed on the second bank layer BN2while surrounding the second opening OPE2around the second emission area EA2or the second opening OPE2, and the third organic pattern ELP3may be disposed on the second bank layer BN2while surrounding the third opening OPE3around the third emission area EA3or the third opening OPE3.

In an embodiment, such organic patterns ELP1, ELP2, and ELP3may be traces formed while the deposited materials are disconnected from the light emitting layers EL1, EL2, and EL3, respectively, rather than being connected to the light emitting layers EL1, EL2, and EL3because the bank structure BNS includes the tips TIP. The light emitting layers EL1, EL2, and EL3may be formed in the openings OPE1, OPE2, and OPE3, respectively, and the organic patterns ELP1, ELP2, and ELP3and the light emitting layers EL1, EL2, and EL3may be disconnected from each other by the tips TIP formed on the sidewalls of the openings OPE1, OPE2, and OPE3, respectively. The light emitting layers EL1, EL2, and EL3are formed through the deposition process that does not use the mask, and accordingly, materials of the light emitting layers EL1, EL2, and EL3may be entirely formed on the bank structure BNS, and the organic patterns ELP1, ELP2, and ELP3may be formed by patterning these materials around the emission areas EA1, EA2, and EA3or the openings OPE1, OPE2, and OPE3, respectively.

In an embodiment, the cathode electrodes CE1, CE2, and CE3may be disposed on the light emitting layers EL1, EL2, and EL3, respectively. The cathode electrodes CE1, CE2, and CE3may include a transparent conductive material to emit light generated from the light emitting layers EL1, EL2, and EL3, respectively. The cathode electrodes CE1, CE2, and CE3may receive a common voltage or a low potential voltage. When the anode electrodes AE1, AE2, and AE3receive a voltage corresponding to a data voltage and the cathode electrodes CE1, CE2, and CE3receive the low potential voltage, potential differences are formed between the anode electrodes AE1, AE2, and AE3and the cathode electrodes CE1, CE2, and CE3, respectively, such that the light emitting layers EL1, EL2, and EL3, respectively, may emit light.

In an embodiment, the cathode electrodes CE1, CE2, and CE3may include a first cathode electrode CE1, a second cathode electrode CE2, and a third cathode electrode CE3, respectively, disposed in the different emission areas EA1, EA2, and EA3, respectively. The first cathode electrode CE1may be disposed on the first light emitting layer EL1in the first emission area EA1, the second cathode electrode CE2may be disposed on the second light emitting layer EL2in the second emission area EA2, and the third cathode electrode CE3may be disposed on the third light emitting layer EL3in the third emission area EA3.

According to an embodiment, portions of the cathode electrodes CE1, CE2, and CE3of the light emitting elements ED1, ED2, and ED3, respectively, may be disposed on side surfaces of the first bank layer BN1of the bank structure BNS. Similar to the light emitting layers EL1, EL2, and EL3, the cathode electrodes CE1, CE2, and CE3may also be formed through a deposition process. The deposition process of the cathode electrodes CE1, CE2, and CE3may be performed so that electrode materials are deposited in a direction inclined with respect to the upper surface of the substrate SUB rather than the direction perpendicular to the upper surface of the substrate SUB. Accordingly, the cathode electrodes CE1, CE2, and CE3may be disposed on the side surfaces of the first bank layer BN1under the tips TIP of the second bank layer BN2of the bank structure BNS. The cathode electrodes CE1, CE2, and CE3may be in direct contact with the side surfaces of the first bank layer BN1. The cathode electrodes CE1, CE2, and CE3of the different light emitting elements ED1, ED2, and ED3, respectively, may be in direct contact with the first bank layer BN1of the bank structure BNS, respectively, and the cathode electrodes CE1, CE2, and CE3may be electrically connected to each other. Unlike the anode electrodes AE1, AE2, and AE3, the cathode electrodes CE1, CE2, and CE3are not divided for each of the plurality of pixels, and may be implemented in an electrode form that is electrically common to all pixels.

According to an embodiment, contact areas between the cathode electrodes CE1, CE2, and CE3and the side surfaces of the first bank layer BN1may be greater than contact areas between the light emitting layers EL1, EL2, and EL3and the side surfaces of the first bank layer BN1. Each of the deposition processes of the cathode electrodes CE1, CE2, and CE3and the light emitting layers EL1, EL2, and EL3may be performed so that the materials of the cathode electrodes CE1, CE2, and CE3and the light emitting layers EL1, EL2, and EL3are deposited in the direction inclined with respect to the upper surface of the substrate SUB rather than the direction perpendicular to the upper surface of the substrate SUB, and areas of the cathode electrodes CE1, CE2, and CE3and the light emitting layers EL1, EL2, and EL3disposed on the side surfaces of the first bank layer BN1may change depending on an inclined angle. In an embodiment, the deposition process of the cathode electrodes CE1, CE2, and CE3may be performed in a more inclined direction than the deposition process of the light emitting layers EL1, EL2, and EL3. The cathode electrodes CE1, CE2, and CE3may be disposed to have a greater area than the light emitting layers EL1, EL2, and EL3, respectively, on the sidewalls of the openings OPE1, OPE2, and OPE3, respectively, or may be disposed up to a greater height on the sidewalls of the openings OPE1, OPE2, and OPE3than the light emitting layers EL1, EL2, and EL3, respectively. Since the cathode electrodes CE1, CE2, and CE3of the different light emitting elements ED1, ED2, and ED3, respectively, are electrically connected to each other through the first bank layer BN1, it may be advantageous that the cathode electrodes CE1, CE2, and CE3are in contact with the first bank layer BN1in a greater area.

The display device10according to an embodiment may include a plurality of electrode patterns CEP1, CEP2, and CEP3including the same materials as the cathode electrodes CE1, CE2, and CE3and disposed on the bank structure BNS. Since the cathode electrodes CE1, CE2, and CE3are formed through a process of depositing materials on the entire surface of the display device10, materials forming the cathode electrodes CE1, CE2, and CE3may be deposited on the bank structure BNS as well as in the openings OPE1, OPE2, and OPE3, respectively, of the bank structure BNS.

In an embodiment, the display device10may include electrode patterns CEP1,

CEP2, and CEP3disposed above the bank structure BNS. The electrode patterns CEP1, CEP2, and CEP3may include a first electrode pattern CEP1, a second electrode pattern CEP2, and a third electrode pattern CEP3, respectively, disposed on the second bank layer BN2of the bank structure BNS.

For example, in an embodiment, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3may be directly disposed on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. An arrangement relationship between the electrode patterns CEP1, CEP2, and CEP3and the organic patterns ELP1, ELP2, and ELP3, respectively, may be the same as an arrangement relationship between the light emitting layers EL1, EL2, and EL3and the cathode electrodes CE1, CE2, and CE3, respectively, of the light emitting elements ED1, ED2, and ED3. Such electrode patterns CEP1, CEP2, and CEP3may be traces formed while the deposited materials are disconnected from the cathode electrodes CE1, CE2, and CE3rather than being connected to the cathode electrodes CE1, CE2, and CE3because the bank structure BNS includes the tips TIP. In the display device10, the cathode electrodes CE1, CE2, and CE3may be individually formed in each of the different areas even in the deposition process that does not use the mask by the tips TIP of the bank structure BNS.

In an embodiment, capping layers CPL may be disposed on the cathode electrodes CE1, CE2, and CE3. The capping layers CPL may include an inorganic insulating material and cover the light emitting elements ED1, ED2, and ED3and the patterns disposed on the bank structure BNS. The capping layers CPL may prevent damage to the light emitting elements ED1, ED2, and ED3from external air, and prevent the patterns disposed on the bank structure BNS from being peeled off during the manufacturing process of the display device10. In an embodiment, the capping layer CPL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and/or silicon oxynitride.

In an embodiment, the display device10may include capping patterns CLP disposed above the bank structure BNS. The capping patterns CLP may be directly disposed on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3disposed on the second bank layer BN2of the bank structure BNS. An arrangement relationship between the capping patterns CLP and the electrode patterns CEP1, CEP2, and CEP3may be the same as an arrangement relationship between the cathode electrodes CE1, CE2, and CE3of the light emitting elements ED1, ED2, and ED3, respectively, and the capping layers CPL. Such capping patterns CLP may be traces formed while the deposited materials are disconnected from the capping layers CPL rather than being connected to the capping layers CPL because the bank structure BNS includes the tips TIP.

In an embodiment, the plurality of organic patterns ELP1, ELP2, and ELP3, the electrode patterns CEP1, CEP2, and CEP3, and the capping patterns CLP may be disposed on the bank structure BNS, and may be disposed to surround the emission areas EA1, EA2, and EA3or the openings OPE1, OPE2, and OPE3. Stacked structures of the organic patterns ELP1, ELP2, and ELP3, the electrode patterns CEP1, CEP2, and CEP3, and the capping patterns CLP disposed around the emission areas EA1, EA2, and EA3, respectively, may be partially etched in the manufacturing process of the display device10, such that pattern shapes may be changed. Accordingly, portions of an upper surface of the second bank layer BN2of the bank structure BNS may not be covered by the organic patterns ELP1, ELP2, and ELP3, the electrode patterns CEP1, CEP2, and CEP3, and the capping patterns CLP.

In an embodiment, the thin film encapsulation layer TFEL may be disposed on the light emitting elements ED1, ED2, and ED3and the bank structure BNS, and may cover the plurality of light emitting elements ED1, ED2, and ED3and the bank structure BNS. The thin film encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from permeating into the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic film to protect the light emitting element layer EML from foreign substances such as dust.

In an embodiment, the thin film encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3that are sequentially stacked. The first encapsulation layer TFEL and the third encapsulation layer TFE3may be inorganic encapsulation layers, and the second encapsulation layer TFE2disposed between the first encapsulation layer TFEL and the third encapsulation layer TFE3may be an organic encapsulation layer.

In an embodiment, each of the first encapsulation layer TFEL and the third encapsulation layer TFE3may include one or more inorganic insulating materials. The inorganic insulating material may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and/or silicon oxynitride.

In an embodiment, the second encapsulation layer TFE2may include a polymer-based material. The polymer-based material may include an acrylic resin, an epoxy-based resin, polyimide, polyethylene, and the like. For example, the second encapsulation layer TFE2may include an acrylic resin such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer TFE2may be formed by curing a monomer or applying a polymer.

In an embodiment, the first encapsulation layer TFE1may be disposed on the light emitting elements ED1, ED2, and ED3, a plurality of patterns, and the bank structure BNS. The first encapsulation layer TFE1may include the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3disposed to correspond respectively to the different emission areas EA1, EA2, and EA3, respectively.

In an embodiment, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3may include an inorganic insulating material and cover the light emitting elements ED1, ED2, and ED3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3may prevent damage to the light emitting elements ED1, ED2, and ED3, respectively, from external air and prevent the patterns disposed on the bank structure BNS from being peeled off during the manufacturing process of the display device10. In an embodiment, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and/or silicon oxynitride.

In an embodiment, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3may be disposed to cover the organic patterns ELP1, ELP2, and ELP3, respectively, the electrode patterns CEP1, CEP2, and CEP3, respectively, and the capping patterns CLP. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3may be formed through chemical vapor deposition (CVD), and may thus be formed at a uniform thickness along steps of layers on which they are deposited. For example, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3may form thin films even under the undercuts by the tips TIP of the bank structure BNS.

In an embodiment, the first inorganic layer TL1may be disposed on the first light emitting element ED1and the first electrode pattern CEP1. The first inorganic layer TL1may be disposed along the first light emitting element ED1and an inner sidewall of the first opening OPE1so as to cover the first light emitting element ED1and the inner sidewall of the first opening OPE1, and may also be disposed to cover the first organic pattern ELP1, the first electrode pattern CEP1, and the capping pattern CLP. However, the first inorganic layer TL1may not overlap the second opening OPE2and the third opening OPE3, and may be disposed only in the first opening OPEL and on the bank structure BNS around the first opening OPE1.

In an embodiment, the second inorganic layer TL2may be disposed on the second light emitting element ED2and the second electrode pattern CEP2. The second inorganic layer TL2may be disposed along the second light emitting element ED2and an inner sidewall of the second opening OPE2so as to cover the second light emitting element ED2and the inner sidewall of the second opening OPE2, and may also be disposed to cover the second organic pattern ELP2, the second electrode pattern CEP2, and the capping pattern CLP. However, the second inorganic layer TL2may not overlap the first opening OPE1and the third opening OPE3, and may be disposed only in the second opening OPE2and on the bank structure BNS around the second opening OPE2.

In an embodiment, the third inorganic layer TL3may be disposed on the third light emitting element ED3and the third electrode pattern CEP3. The third inorganic layer TL3may be disposed along the third light emitting element ED3and an inner sidewall of the third opening OPE3so as to cover the third light emitting element ED3and the inner sidewall of the third opening OPE3, and may also be disposed to cover the third organic pattern ELP3, the third electrode pattern CEP3, and the capping pattern CLP. However, the third inorganic layer TL3may not overlap the first opening OPEL and the second opening OPE2, and may be disposed only in the third opening OPE3and on the bank structure BNS around the third opening OPE3.

In an embodiment, the first inorganic layer TL1may be formed after the first cathode electrode CE1is formed, the second inorganic layer TL2may be formed after the second cathode electrode CE2is formed, and the third inorganic layer TL3may be formed after the third cathode electrode CE3is formed. Accordingly, the first to third inorganic layers TL1, TL2, and TL3, respectively, may be disposed to cover different electrode patterns CEP1, CEP2, and CEP3and organic patterns ELP1, ELP2, and ELP3, respectively. Each of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3may have a greater area than each of the openings OPE1, OPE2, and OPE3of the bank structure BNS in a plan view. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3may be disposed to be spaced apart from each other on the bank structure BNS. Accordingly, portions of the second bank layer BN2of the bank structure BNS may not overlap the inorganic layers TL1, TL2, and TL3, and portions of the upper surface of the second bank layer BN2of the bank structure BNS may be exposed without being covered by the inorganic layers TL1, TL2, and TL3. Portions of the second bank layer BN2may be in direct contact with a second encapsulation layer TFE2of a thin film encapsulation layer TFEL to be described later.

In an embodiment, the touch sensing layer TSU may be disposed on the thin film encapsulation layer TFEL. The touch sensing layer TSU may include a first touch insulating layer SIL1, a second touch insulating layer SIL2, touch electrodes TEL, and a third touch insulating layer SIL3.

In an embodiment, the first touch insulating layer SIL1may be disposed on the thin film encapsulation layer TFEL. The first touch insulating layer SIL1may have insulating and optical functions. The first touch insulating layer SIL1may include at least one inorganic film. Optionally, the first touch insulating layer SIL1may be omitted.

In an embodiment, the second touch insulating layer SIL2may cover the first touch insulating layer SIL1. Although not illustrated in the drawings, touch electrodes of another layer may be further disposed on the first touch insulating layer SIL1, and the second touch insulating layer SIL2may cover such touch electrodes TEL. The second touch insulating layer SIL2may have insulating and optical functions. For example, the second touch insulating layer SIL2may be an inorganic film including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

In an embodiment, some of the touch electrodes TEL may be disposed on the second touch insulating layer SIL2. Each of the touch electrodes TEL may not overlap the first to third emission areas EA1, EA2, and EA3, respectively. Each of the touch electrodes TEL may be formed as a single layer made of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO) or be formed as a stacked structure (Ti/Al/Ti) of aluminum and titanium, a stacked structure (ITO/Al/ITO) of aluminum and ITO, an APC alloy, and a stacked structure (ITO/APC/ITO) of an APC alloy and ITO.

In an embodiment, the third touch insulating layer SIL3may cover the touch electrodes TEL and the second touch insulating layer SIL2. The third touch insulating layer SIL3may have insulating and optical functions. The third touch insulating layer SIL3may be made of the material exemplified in the second touch insulating layer SIL2.

In an embodiment, the light blocking layer BM may be disposed on the touch sensing layer TSU. The light blocking layer BM may include the plurality of opening holes OPT1, OPT2, and OPT3disposed to overlap the emission areas EA1, EA2, and EA3, respectively. For example, a first opening hole OPT1may be disposed to overlap the first emission area EA1. A second opening hole OPT2may be disposed to overlap the second emission area EA2, and a third opening hole OPT3may be disposed to overlap the third emission area EA3. An area or a size of each of the opening holes OPT1, OPT2, and OPT3may be greater than the area or the size of each of the emission areas EA1, EA2, and EA3defined by the bank structure BNS. The opening holes OPT1, OPT2, and OPT3of the light blocking layer BM are formed to be greater than the emission areas EA1, EA2, and EA3, respectively, and accordingly, the light emitted from the emission areas EA1, EA2, and EA3may be viewed by a user not only from a front surface but also from side surfaces of the display device10.

In an embodiment, the light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the invention is not limited thereto. The light blocking layer BM may prevent color mixing due to permeation of visible light between the first to third emission areas EA1, EA2, and EA3to improve a color gamut of the display device10.

In an embodiment, the display device10may include a plurality of color filters CF1, CF2, and CF3disposed on the emission areas EA1, EA2, and EA3, respectively. The plurality of color filters CF1, CF2, and CF3may be disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3may be disposed on the light blocking layer BM including the plurality of opening holes OPT1, OPT2, and OPT3disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. The opening holes of the light blocking layer may be formed to overlap the emission areas EA1, EA2, and EA3or the openings of the bank structures BNS, and may form light emitting areas through which the light emitted from the emission areas EA1, EA2, and EA3is emitted. Each of the color filters CF1, CF2, and CF3may have a greater area than each of the opening holes of the light blocking layer BM, and each of the color filters CF1, CF2, and CF3may completely cover the light emitting area formed by each of the opening holes.

In an embodiment, the color filters CF1, CF2, and CF3may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, respectively, disposed to correspond to the different emission areas EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3may include colorants such as dyes or pigments absorbing light of wavelength bands other than light of a specific wavelength band, and may be disposed to correspond to the colors of the light emitting from the emission areas EA1, EA2, and EA3. For example, the first color filter CF1may be a red color filter disposed to overlap the first emission area EA1and transmitting only the first light, which is the red light, therethrough. The second color filter CF2may be a green color filter disposed to overlap the second emission area EA2and transmitting only the second light, which is the green light, therethrough, and the third color filter CF3may be a blue color filter disposed to overlap the third emission area EA3and transmitting only the third light, which is the blue light, therethrough.

In an embodiment, the plurality of color filters CF1, CF2, and CF3may be spaced apart from other adjacent color filters CF1, CF2, and CF3on the light blocking layer BM. The color filters CF1, CF2, and CF3may have greater areas than the opening holes OPT1, OPT2, and OPT3of the light blocking layer BM while covering the opening holes OPT1, OPT2, and OPT3of the light blocking layer BM, respectively, but may have areas enough to be spaced apart from other color filters CF1, CF2, and CF3on the light blocking layer BM. However, the invention is not limited thereto. The plurality of color filters CF1, CF2, and CF3may be disposed to partially overlap other adjacent color filters CF1, CF2, and CF3. Different color filters CF1, CF2, and CF3may overlap each other on a light blocking layer BM to be described later, which is an area that does not overlap the emission areas EA1, EA2, and EA3. In the display device10, the color filters CF1, CF2, and CF3are disposed to overlap each other, and accordingly, an intensity of reflected light by external light may be reduced. Furthermore, a color feeling of the reflected light by the external light may be controlled by adjusting arrangements, shapes, areas, and the like, of the color filters CF1, CF2, and CF3in a plan view.

In an embodiment, the color filters CF1, CF2, and CF3of the color filter layer CFL may be disposed on the light blocking layer BM. The different color filters CF1, CF2, and CF3may be disposed to correspond to the different emission areas EA1, EA2, and EA3or openings OPE1, OPE2, and OPE3and the opening holes OPT1, OPT2, and OPT3of the light blocking layer BM, respectively. For example, the first color filter CF1may be disposed to correspond to the first emission area EA1, the second color filter CF2may be disposed to correspond to the second emission area EA2, and the third color filter CF3may be disposed to correspond to the third emission area EA3. The first color filter CF1may be disposed in the first opening hole OPT1of the light blocking layer BM, the second color filter CF2may be disposed in the second opening hole OPT2of the light blocking layer BM, and the third color filter CF3is disposed in the third opening hole OPT3of the light blocking layer BM. Each of the color filters CF1, CF2, and CF3may be disposed to have a greater area than each of the opening holes OPT1, OPT2, and OPT3of the light blocking layer BM in a plan view, and a portion of each of the color filters CF1, CF2, and CF3may be directly disposed on the light blocking layer BM.

In an embodiment, an overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3to planarize upper ends of the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless light transmitting layer that does not have a color of a visible light band. For example, the overcoat layer OC may include a colorless light transmitting organic material such as an acrylic resin.

In an embodiment, in the display device10, the plurality of light emitting elements ED1, ED2, and ED3disposed in the display area DA may be disposed in the emission areas EA1, EA2, and EA3formed by the bank structures BNS, respectively. As described above, the cathode electrodes CE1, CE2, and CE3of the respective light emitting elements ED1, ED2, and ED3may be electrically connected to each other through the first bank layer BN1of the bank structure BNS. The cathode electrodes CE1, CE2, and CE3of the light emitting elements ED1, ED2, and ED3, respectively, and the first bank layer BN1may form a common electrode in the display area DA.

Meanwhile, in an embodiment, in the display device10, the bank structure BNS may be disposed up to the non-display area NDA beyond the display area DA. The first bank layer BN1of the bank structure BNS may be disposed to extend to the non-display area NDA while forming the common electrode with the cathode electrodes CE1, CE2, and CE3of the light emitting elements ED1, ED2, and ED3, respectively, and may be electrically connected to the first power line VL1disposed in the non-display area NDA. Accordingly, the light emitting elements ED1, ED2, and ED3may be electrically connected to the first power line VL1disposed in the non-display area NDA, and may receive the low potential voltage through the first power line VL1.

FIG.8is a plan view illustrating an arrangement of a dam structure disposed in the display device, according to an embodiment.

In an embodiment and referring toFIG.8, the display layer DU of the display device10may include a display area DA and a non-display area NDA surrounding the display area DA. As described above with reference toFIG.4, the plurality of pixels PX and the plurality of lines, for example, the second power lines VL2, the gate lines GL, and the data lines DL may be disposed in the display area DA. The display driver200, the gate driver210, the plurality of display pad parts DP, and the first power line VL1may be disposed in the non-display area NDA. The first power line VL1may be electrically connected to the plurality of pixels PX of the display area DA through the bank structure BNS.

In an embodiment, the first power line VL1may be electrically connected to the first bank layer BN1of the bank structure BNS, and may be electrically connected to the light emitting elements ED1, ED2, and ED3through the first bank layer BN1(sccFIG.6). The cathode electrodes CE1, CE2, and CE3of the light emitting elements ED1, ED2, and ED3may form the common electrode with the first bank layer BN1of the bank structure BNS, and may receive the low potential voltage transferred through the first power line VL1(seeFIG.6). Although not illustrated inFIG.8, the bank structure BNS may be disposed to extend to the non-display area NDA beyond the display area DA, and may be electrically connect to the first power line VL1in the non-display area NDA. A connection between the first power line VL1and the bank structure BNS will be described later with reference to other drawings.

According to an embodiment, the display device10may include a plurality of dams disposed in the non-display area NDA. The plurality of dams may include a first dam DAM1surrounding the display area DA and spaced apart from the bank structure BNS disposed in the display area DA and a second dam DAM2surrounding the first dam DAM1.

In an embodiment, the first dam DAM1may be disposed to surround the display area DA and to be spaced apart from the bank structure BNS. The first dam DAM1may surround the display area DA and the bank structure BNS by including portions extending in the first direction DR1and the second direction DR2. The second dam DAM2may be disposed to be spaced apart from the first dam DAM1. The second dam DAM2may surround the display area DA and the first dam DAM1by including portions extending in the first direction DR1and the second direction DR2.

In an embodiment, the display device10may have a structure in which a plurality of layers are sequentially stacked on one substrate SUB. Some layers of the display device may be made of an organic material, and may be formed through a process in which the organic material is directly jetted onto the substrate SUB. For example, since the display device10includes the thin film encapsulation layer TFEL (seeFIG.6) and the second encapsulation layer TFE2of the thin film encapsulation layer TFEL may include an organic material to flow with fluidity, the organic material jetted onto the display area DA may overflow into the non-display area NDA. The first dam DAM1and the second dam DAM2may prevent the organic material from overflowing into the outside of the non-display area NDA beyond the non-display area NDA.

In an embodiment, the plurality of dams DAM1and DAM2need to have a structure in which one or more layers are stacked and have a minimum thickness or height. The dams DAM1and DAM2may include a plurality of layers disposed in the display area DA and layers including the same material as the bank structure BNS to have heights enough to prevent the overflow of the organic material.

FIG.9is an enlarged view of portion A ofFIG.8, according to an embodiment.FIG.10is a cross-sectional view taken along line X-X′ ofFIG.9, according to an embodiment. In an embodiment,FIG.9illustrates an arrangement, in a plan view, of the bank structure BNS, the first dam DAM1, and the second dam DAM2disposed adjacent to a corner portion of the display area DA.FIG.10illustrates a cross-section crossing the first dam DAM1, the second dam DAM2, and the emission area disposed in the opening of the bank structure BNS.

In an embodiment and referring toFIGS.9and10, the bank structure BNS may include a plurality of openings disposed in the display area DA. As described above, the emission areas EA1, EA2, and EA3may be formed by disposing the light emitting elements ED1, ED2, and ED3, respectively, in the openings.

According to an embodiment, the bank structure BNS may be disposed to extend from the display area DA to a partial area of the non-display area NDA. The bank structure BNS may overlap the first power line VL1. For example, the bank structure BNS may be directly disposed on and electrically connected to the first power line VL1in the non-display area NDA. The first bank layer BN1may be electrically connected to the first power line VL1by including a metal material. Since the first bank layer BN1forms the common electrode with the cathode electrodes CE of the light emitting elements ED, the first power line VL1may be electrically connected to the light emitting elements ED through the first bank layer BN1.

In an embodiment, the first power line VL1may be disposed in the non-display area NDA. Although not illustrated in the drawings, the first power line VL1may have a predetermined width and extend in the second direction DR2in the non-display area NDA. The first power line VL1may include the same material as the second connection electrode CNE2and may be disposed on the first via layer VIA1. However, an area in which the first via layer VIA1and the second via layer VIA2are not disposed may exist between the second dam DAM2and the display area DA, and the first power line VL1may be directly disposed on the second interlayer insulating layer ILD2.

According to an embodiment, each of the first dam DAM1and the second dam DAM2of the display device10may include a dam structure DMS having the same material and structure as the bank structure BNS. The dam structure DMS may include a first sub-dam structure DBN1including the same material as the first bank layer BN1and a second sub-dam structure DBN2disposed on the first sub-dam structure DBN1and including the same material as the second bank layer BN2. The first sub-dam structure DBN1and the second sub-dam structure DBN2may include aluminum (Al) and titanium (Ti), respectively, and the second sub-dam structure DBN2may include tips protruding from side surfaces of the first sub-dam structure DBN1. A stacked structure of the first sub-dam structure DBN1and the second sub-dam structure DBN2may be substantially the same as a stacked structure of the first bank layer BN1and the second bank layer BN2of the bank structure BNS.

In an embodiment, the first dam DAM1may include a first sub-dam SDAM1and an insulating pattern ISP that are disposed between the dam structure DMS and the substrate SUB and a spacer SPC disposed on the dam structure DMS. The second dam DAM2may include a first sub-dam SDAM1, a second sub-dam SDAM2, and an insulating pattern ISP that are disposed between the dam structure DMS and the substrate SUB and a spacer SPC disposed on the dam structure DMS. In the second dam DAM2, the second sub-dam SDAM2may be positioned at the same height as the first via layer VIA1, and the first sub-dam SDAM1may be positioned at the same height as the second via layer VIA2. In the first dam DAM1, the first sub-dam SDAM1may be positioned at the same height as the first via layer VIA1.

In an embodiment, the first sub-dam SDAM1of the first dam DAM1may be directly disposed on the first power line VL1. The first sub-dam SDAM1of the first dam DAM1may include the same material as the second via layer VIA2, but may be positioned at the same height as the first via layer VIA1. The first sub-dam SDAM1may not be electrically connected to the first power line VL1by including an insulating material.

In an embodiment, the insulating pattern ISP of the first dam DAM1may be disposed on the first sub-dam SDAM1. The insulating pattern ISP may be disposed to surround an outer surface of the first sub-dam SDAM1. The insulating pattern ISP may include the same material as the inorganic insulating layer ISL disposed in the display area DA. The insulating pattern ISP may be in partial contact with the first power line VL1, but may be electrically insulated from the first power line VL1.

In an embodiment, the dam structure DMS of the first dam DAM1may be disposed on the insulating pattern ISP. The first sub-dam structure DBN1of the dam structure DMS may be directly disposed on the insulating pattern ISP, and the second sub-dam structure DBN2may be disposed on the first sub-dam structure DBN1. The first dam DAM1may not include a layer including the same material as the first via layer VIA1, and the dam structure DMS may be positioned at a height similar to that of the second via layer VIA2.

In an embodiment, the spacer SPC of the first dam DAM1may be disposed on the dam structure DMS. The spacer SPC may be disposed to cover outer surfaces of the dam structure DMS and the insulating pattern ISP. The spacer SPC may be disposed to fill lower portions of the tips formed by the second sub-dam structure DBN2of the dam structure DMS.

In an embodiment, the second dam DAM2may further include the second sub-dam SDAM2as compared with the first dam DAM1. The second sub-dam SDAM2of the second dam DAM2may be directly disposed on the second interlayer insulating layer ILD2. The second sub-dam SDAM2may include the same material as the first via layer VIA1and may be positioned at the same height as the first via layer VIA1.

In an embodiment, the first sub-dam SDAM1of the second dam DAM2may be disposed on the second sub-dam SDAM2. The second sub-dam SDAM2of the second dam DAM2may include the same material as the second via layer VIA2and may be positioned at the same height as the second via layer VIA2.

In an embodiment, the insulating pattern ISP of the second dam DAM2may be disposed on the first sub-dam SDAM1. The insulating pattern ISP may be disposed to surround outer surfaces of the first sub-dam SDAM1and the second sub-dam SDAM2. A portion of the insulating pattern ISP may be disposed at the outermost portion of the non-display area NDA, and the insulating pattern ISP may also be disposed on the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the second buffer layer BF2.

In an embodiment, the dam structure DMS of the second dam DAM2may be disposed on the insulating pattern ISP. The first sub-dam structure DBN1of the dam structure DMS may be directly disposed on the insulating pattern ISP, and the second sub-dam structure DBN2may be disposed on the first sub-dam structure DBN1. The dam structure DMS of the second dam DAM2may be positioned at the same height as the bank structure BNS.

In an embodiment, the spacer SPC of the second dam DAM2may be disposed on the dam structure DMS. The spacer SPC may be disposed to cover outer surfaces of the dam structure DMS and the insulating pattern ISP. The spacer SPC may be disposed to fill lower portions of the tips formed by the second sub-dam structure DBN2of the dam structure DMS.

In an embodiment, a height of the first dam DAM1may be lower than a height of the second dam DAM2. The first dam DAM1does not include the second sub-dam SDAM2unlike the second dam DAM2, and may thus have a relatively low height.

In an embodiment, the display device10includes the inorganic insulating layer ISL disposed in the display area DA, and thus, a height of an organic material layer disposed in the non-display area NDA may be low. However, in the display device10, the dam structures DMS including the same material as the bank structure BNS and having the same structure as the bank structure BNS constitute portions of the dams DAM1and DAM2in the non-display area NDA, and thus, the dams DAM1and DAM2may have heights enough to prevent the overflow of the organic material.

In an embodiment, the first encapsulation layer TFEL and the third encapsulation layer TFE3may cover the first dam DAM1and the second dam DAM2disposed at the outermost portion of the display area DA. The first encapsulation layer TFEL and the third encapsulation layer TFE3may extend to the outermost edge of the display panel100beyond the first dam DAM1and the second dam DAM2.

In an embodiment, the second encapsulation layer TFE2may be disposed to cover the first dam DAM1and not to cover an upper surface of the second dam DAM2. However, the Invention is not limited thereto. The second encapsulation layer TFE2may not cover both an upper surface of the first dam DAM1and the upper surface of the second dam DAM2. The second encapsulation layer TFE2may not overflow to an edge of the display panel100due to the first dam DAM1and the second dam DAM2.

In an embodiment, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the first via layer VIA1, and the second via layer VIA2of the thin film transistor layer TFTL may be removed outside the second dam DAM2. Only the buffer layers BF1and BF2of the thin film transistor layer TFTL may be disposed outside the second dam DAM2, and the first encapsulation layer TFE1and the third encapsulation layer TFE3extending to the outermost edge of the display panel100may be directly disposed on the second buffer layer BF2.

FIG.11is an enlarged view of portion B ofFIG.8, according to an embodiment.FIG.12is a cross-sectional view taken along line XII-XII′ ofFIG.11, according to an embodiment. In an embodiment,FIG.11illustrates an arrangement, in a plan view, of the second display area DA2and a hole dam HDAM disposed around the second display area DA2.FIG.12illustrates a cross section crossing the second display area DA2.

Referring toFIGS.11and12, the display device10according to an embodiment may include the hole dam HDAM surrounding the second display area DA2. Emission areas may not be partially formed in the second display area DA2unlike the first display area DA1(seeFIG.8). The second display area DA2is an area in which the optical device500is disposed there below, and may be an area through which light is transmitted. The hole dam HDAM may prevent organic materials disposed in the first display area DA1from overflowing into the second display area DA2while dividing the first display area DA1and the second display area DA2within the display area DA.

According to an embodiment, the display device10may include the hole dam HDAM including a dam structure DMS including the same material as the bank structure BNS and having the same structure as the bank structure BNS. The hole dam HDAM may have the same structure as the first dam DAM1. For example, the hole dam HDAM may include a first sub-dam SDAM1, an insulating pattern ISP, the dam structure DMS, and a spacer SPC. In the second display area DA2, the upper surface of the substrate SUB may be exposed, and the hole dam HDAM may be directly disposed on the substrate SUB. A description of a stacked structure of the hole dam HDAM is the same as that of the stacked structure of the first dam DAM1described above.

In an embodiment, the first encapsulation layer TFE1and the third encapsulation layer TFE3of the thin film encapsulation layer TFEL may also be disposed in the second display area DA2beyond the hole dam HDAM, but the second encapsulation layer TFE2may be disposed so as not to go beyond the hole dam HDAM. The display device10may prevent the organic material from overflowing into the second display area DA2by including the hole dam HDAM dividing the first display area DA1and the second display area DA2.

Hereinafter, various embodiments of the display device10will be described with reference to other drawings.

FIG.13is a plan view illustrating an arrangement of a dam structure disposed in a display device, according to another embodiment.FIG.14is an enlarged view of portion C ofFIG.13, according to another embodiment.FIG.15is a cross-sectional view taken along line XV-XV′ ofFIG.14, according to another embodiment.

Referring toFIGS.13to15, a display device10_1according to another embodiment may include a first dam DAM1_1, a second dam DAM2_1, and a third dam DAM3_1disposed in the non-display area NDA. The first dam DAM1_1may be disposed to surround the display area DA, the second dam DAM2_1may be disposed to surround the first dam DAM1_1, and the third dam DAM3_1may be disposed to surround the second dam DAM2_1. The display device10_1may include a greater number of dams DAM than the display device according to the above-described embodiment.

According to another embodiment, the first dam DAM1_1may include sub-dam structures DBN1and DBN2including the same materials as the bank layers BN1and BN2of the bank structure BNS, while the second dam DAM2_1and the third dam DAM3_1may not include sub-dam structures DBN1and DBN2. For example, the first dam DAM1_1may include a first sub-dam structure DBN1disposed adjacent to the display area DA and disposed on the first power line VL1and a second sub-dam structure DBN2disposed on the first sub-dam structure DBN1. The first sub-dam structure DBN1and the second sub-dam structure DBN2may include the same materials as the first bank layer BN1and the second bank layer BN2of the bank structure BNS, respectively. The first dam DAM1_1may further include an insulating pattern ISP disposed on the first power line VL1, and the first sub-dam structure DBN1and the second sub-dam structure DBN2may be disposed on the insulating pattern ISP. The first dam DAM1_1may include the same material as the bank structure BNS and have the same structure as the bank structure BNS, but may be positioned at the same height as the second via layer VIA2of the display area DA.

In an embodiment, the second dam DAM2_1may include a first sub-dam SDAM1, an insulating pattern ISP, and a spacer SPC. The second dam DAM2_1may have a structure in which the first sub-dam SDAM1is directly disposed on the first power line VL1and an insulation pattern ISP and a spacer SPC are sequentially stacked on the first sub-dam SDAM1. The first sub-dam SDAM1of the second dam DAM2_1may include the same material as the second via layer VIA2as described above, but may be positioned at the same height as the first via layer VIA1of the display area DA.

In an embodiment, the third dam DAM3_1may include a first sub-dam SDAM1, a second sub-dam SDAM2, an insulating pattern ISP, and a spacer SPC. The third dam DAM3_1may have a structure in which the second sub-dam SDAM2is directly disposed on the first power line VL1and the first sub-dam SDAM1, the insulating pattern ISP, and the spacer SPC are sequentially stacked on the second sub-dam SDAM2. As described above, the second sub-dam SDAM2of the third dam DAM3_1may include the same material as the first via layer VIA1, and the first sub-dam SDAM1of the third dam DAM3_1may include the same material as the second via layer VIA2. The second sub-dam SDAM2and the first sub-dam SDAM1of the third dam DAM3_1may be positioned at the same heights as the first via layer VIA1and the second via layer VIA2, respectively.

The display device10_1according to another embodiment may include the first dam DAM1_1having the same structure as the bank structure BNS and disposed so as not to overlap the other sub-dams SDAM1and SDAM2, and may further include the second dam DAM2_1and the third dam DAM3_1in which layers having structures different from those of the bank structure BNS are stacked. The display device10_1according to another embodiment may prevent the overflow of the organic materials by including dams DAM1_1, DAM2_1, and DAM3_1of which heights are lower than heights of the dams of the display device according to an embodiment ofFIG.10, but the number is greater than the number of dams of the display device according to an embodiment ofFIG.10.

FIG.16is a schematic view illustrating portions of a bank structure and a dam structure of a display device, according to another embodiment.

Referring toFIG.16, in a display device10_2according to another embodiment, a first dam DAM1_2and a bank structure BNS_2may be connected to each other through a dam connection part BDM_2. As described above, each of the first dam DAM1_2and the second dam DAM2may include a dam structure DMS having the same structure as the bank structure BNS_2. In the first dam DAM1_2to which the bank structure BNS_2is relatively adjacent, the dam structure DMS may be integrated with the bank structure BNS_2. For example, the dam structure DMS of the first dam DAM1_2may be connected to the bank structure BNS_2through the dam connection part BDM_2. Although not illustrated inFIG.16, the dam structure DMS and the dam connection part BDM_2may include a first sub-dam structure DBN1and a second sub-dam structure DBN2, respectively. The first sub-dam structure DBN1and the second sub-dam structure DBN2may be disposed at the same layers as the first bank layer BN1and the second bank layer BN2, respectively, and may be integrated with the first bank layer BN1and the second bank layer BN2, respectively.

In an embodiment, in the display device10_2, each of the bank structure BNS_2disposed in the display area DA and the dam structure DMS disposed in the non-display area NDA may include a metal material to have electrical conductivity. The dam structure DMS may be covered by the spacer SPC and the thin film encapsulation layer TFEL, but static electricity may be generated due to conductivity of the dam structure DMS. In the display device10_2, the dam structure DMS of the first dam DAM1_2disposed in the non-display area NDA may be connected to the bank structure BNS_2in the display area DA, and the generation of the static electricity may be prevented through electrical connection between the dam structure DMS of the first dam DAM1_2and the bank structure BNS_2.

While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims. The invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art. Moreover, the embodiments or parts of the embodiments may be combined in whole or in part without departing from the scope of the invention.