Distributed ethernet hub

A technique for multiplexing high speed computed data with digitized voice signals onto a fiber optic cable for transfer to a local central office. The data packets of a number of computers are networked by way of a distributed hub that extends to residences, offices, apartments, etc. The data packets are switched outside the switching fabric of a local central office and routed to the internet or elsewhere. Command signals that are for accessing the internet are transmitted and received as 10 MHz Ethernet data packets on the distributed hub.

TECHNICAL FIELD OF THE INVENTION

The present invention relates in general to telecommunication equipment and local area networks, and more particularly to an arrangement for extending an Ethernet network and allowing subscriber access to the internet network, without tying up voice paths in central office switching equipment.

BACKGROUND OF THE INVENTION

The widespread use and advancement of telecommunication equipment and services have facilitated the dispersal of information of all types, including personal, business, governmental, educational, etc. It is not without question that there is a significant benefit to society when information of all types is readily available. While public and institutional libraries have been available for many decades for allowing access to the vast volumes of information, the access to such information was often burdensome and time consuming.

The popularity of the internet, and the access thereto in recent years, has enjoyed a great deal of success, due primarily to the ease of access and the ability to provide new and updated information and data on a daily or hourly basis. Moreover, with the abundance of home and office computers, and with the proliferation of internet service providers, access to all kinds of information can be readily had by a person at either the office or home using a computer, and at the convenience of the subscriber. A subscriber connected to the internet via a telephone line modem and service provider can browse through the various internet data bases, generally at only the cost of a connection to the internet service provider. With regard to internet subscribers, an internet connection is generally accomplished by the modem dialing a local number. The telephone operating companies thus do not obtain revenue therefrom, as such calls are often not of the toll or long distance type. The revenue obtained by the telephone operating companies for internet connections is generally only for leased lines from the internet service provider to the internet connection point. Despite that the local telephone operating companies have had to accommodate the additional load imposed on them for providing telephone connection services, very little, if any, additional revenue has been gained.

The internet architecture includes a government-installed network, termed the “backbone”, to which many governmental and educational institutions are directly connected. Accordingly, a vast amount of data and information is easily distributed throughout government and educational institutions by large mainframe computer data bases, without involving private or public telephone companies. In order for individuals and businesses other than those with internet mainframe computers to be connected to the backbone, many service providers, i.e., web sites, have become available for connecting subscribers to the internet. The web sites themselves also employ additional data bases which are accessible by any person wishing to access the internet. Generally, subscribers establish internet connections by dialing via analog modems to a modem “pool” that is served by a computer of the internet service provider. The web site computer then provides a connection appearance to the internet via a high speed leased line ultimately to the internet backbone. Each subscriber has a unique IP address, and each service provider has a unique address, such as mainhost.Cyberspace.net. In like manner, the address of the service provider is generally known as a domain name server. Similarly, each web site has a unique address, such as http://WWW.UH.edu. As noted above, while the local telephone operating companies do not obtain additional revenues from the subscribers during the connection to the internet, certain revenues are obtained for the high speed leased lines.

With the widespread use of the internet by many individuals using analog modems, substantial traffic burdens have been placed on the public telephone network, in that the local telephone operating company provides a switched network connection for each subscriber to reach the service provider. While such internet connections at the local central office do not involve any technical problems, such connections do indeed reduce the capability of the telephone companies to handle the routine telephone set traffic, especially during peak demand periods. It is well known that the traffic needs of telephone switching equipment are based on the statistical average of routine telephone calls. In practice, an average telephone-to-telephone call lasts approximately 100 seconds. Thus, based on the plain old telephone service (POTS), even at peak demand periods when the switching network may be operating at full capacity, a user does not need to wait for a very long period of time in order to complete a connection through the network to a destination, whether it be local or long distance. However, the telephone network connection provided for an internet subscriber lasts significantly longer than the nominal 100 seconds, and may remain for hours.

A central office connection provided by a local telephone company that is dedicated to a single subscriber for many hours thereby disrupts the statistical traffic demands that are normal for routine telephone calls. While the telephone operating companies can overcome this problem by expanding the central office switching equipment to accommodate more subscriber connections, such solution involves extremely costly equipment, space and time to install new switching equipment.

The information provided to internet subscribers often involves video data in the nature of graphics. In order to recreate pictures or graphical data on a CRT via a standard 28.8 K analog modem, a substantial amount of time is incurred in waiting for the transfer of large amounts of video data, as well as the display of the same on the CRT. This waiting period is due primarily to the bandwidth bottle-neck of the modems. While ISDN data links are available, and operate between 56 and 128 kilobits per second, the use thereof does not significantly overcome the waiting problem.

The bandwidth problem can be overcome by the use of optical fibers that are higher speed and more environmentally durable than the traditional twisted copper pairs. However, the installation of fiber optic transmission facilities is costly, and thus acceptance thereof has been generally limited to high traffic situations. There is, however, a continued growth of the use of fiber optic telecommunications into residential neighborhoods. An emerging technology in this area is called “fiber to the curb.” RELTEC Corporation of Bedford, Tex. is a leader in providing this new technology. Even with fiber optic capability extended to residential homes, apartments and businesses, the primary usage thereof is yet for routine telephone calls and computer modem traffic. As such, the fiber optic systems represents excess capabilities that are not used to the fullest extent.

It would be highly advantageous to utilize the high speed optical medium for computer network capabilities, especially in view that many residential homes and/or offices are equipped with computers and modems for accessing the internet as well as a host of other services. The networking of computers is a well-established function that allows a number of computers to communicate with each other according to a predefined protocol. One of the most popular network protocols is the Ethernet protocol, or otherwise known as the IEEE 802.3 standard. While this local area network protocol functions ideally in a local area, it is not easily expanded geographically without the use of expensive “network” bridges. The area limitations of the Ethernet protocol is based primarily on the “round trip timing” of signals carried on the network. This period of time is directly related to the physical length of the network medium and the time delay of electrical signals carried by the medium. According to the Ethernet standards, in order to minimize signal attenuation, each source or destination computer must be no further from the network than about 328 feet. The Ethernet protocol includes an algorithm to detect when two computers attempt to transmit data packets on the network at the same time and avoid the corresponding “collision” of signals. To date, there has been no acceptable solution for extending the geographical area of an Ethernet network without utilizing expensive bridges. While the use of bridges is widely known, such solution involves the receipt of the data packets, decoding the various fields and otherwise processing of the data fields themselves, and the attendant slowing down the transport speed of the overall data transmission.

From the foregoing, it can be seen that a need exists for a technique to provide users with connections to the internet, without tying up local central office switching equipment for long periods of time. A further need exists for the use of conventional equipment and software to provide such connections to internet services, without the need for new or expensive computer equipment or software protocols. Another need exists for a better utilization of fiber optic and other high speed data transmission facilities that are available to residential users. A significant need exists for extending data networks without the use of bridges and similar equipment while yet maintaining conformance to the appropriate protocol. Another need exists for providing an improved utilization of high speed data lines in extended data networks, and providing residential and other users further incentives to use high speed data services.

SUMMARY OF THE INVENTION

In accordance with the principles and concepts of the invention, disclosed is a technique for overcoming or substantially reducing the problems attendant with the traditional connections provided to the internet, via the local telephone operating companies.

In accordance with an important aspect of the invention, rather than employing modem data coupled through the switching fabric of a central office, the subscriber's personal computer employs a conventional network card to generate data packets according to a standard local area network protocol, such as Ethernet. The data packets are thereafter multiplexed with other data packets and converted to corresponding optical signals for transfer via an optical fiber medium to an Ethernet switch or other similar equipment, such as a LAN adapter located in the central office. The central office allows the internet connection request to be switched and/or transferred external to the switching fabric via high speed lines for subsequent connection to the internet backbone. With this arrangement, unlike the traditional modem data, the data packets communicated between the internet and the subscriber personal computer are not carried or switched through the switching fabric of the central office. Thus, lengthy internet connection periods do not adversely affect the voice traffic carrying capability of the central office switching system. Also, by reason of the central office capability of processing internet access requests, the central office can itself function as a service provider, i.e., as a domain name server.

In the preferred embodiments employing the invention, a household or office personal computer is connected to a standard twisted pair having a 10 MHz bandwidth for carrying Ethernet data packets or frames. The data packets are transmitted on the twisted pair at a 10 MHz rate by a 10-Base-T transmission method. Within no more than about 500 feet of home or office personal computers, there is located an optical network unit for converting the digital signals of the Ethernet frames to corresponding optical signals that are carried on a fiber optic line. The optical network unit provides a carrier sense multiple access with collision detection (CSMA/CD) functions with respect to the computer connected to the 10-Base-T input ports thereof. In addition, the optical network unit can include additional ports to convert analog voice signals from telephone sets to PCM signals which are multiplexed with the computer digital data. Other digital carrier capabilities, such as DS1, can also be multiplexed onto the optical medium by the optical network unit. With regard to the data frames transmitted to the optical network unit by the computer, if no collision of signals is detected, then the data packets are stored in a buffer memory and retransmitted back to the other computers locally connected to the 10-Base-T ports of the optical network unit. Moreover, if no collision is detected, the data frame is transmitted as optical signals toward a central office via a host digital terminal. Importantly, a host digital terminal can be located several miles or more from an optical network unit, and can receive optical inputs from a number of such units.

The host digital terminal may typically be located remotely with respect to the central office and coupled thereto by yet other optical fiber or electrical data transmission lines. Much like the optical network units, the host digital terminal includes plural optical interface units that receive the network data frames and provide a collision avoidance function. As such, the network connection is extended from the residences beyond the traditional geographical limits, to the host digital terminal.

Each optical interface unit of the host digital terminal is interconnected by a common high speed electrical bus to provide networking of data frames therebetween so that such frames can be transmitted back to all of the other computers connected in a wide area network. In addition to the echoing of the data frames to the sources, and if no collision is detected, the data frame is read from a buffer memory and transmitted to a standard Ethernet switch where such data is transferred on a high speed line toward the internet backbone. The host digital terminal also transfers the multiplexed optical signals of PCM and DS1 data by way of fiber optic cables or electrical lines to the central office where the signals are reconverted to bipolar signals. The PCM data is switched by the switching fabric of the central office to a destination in a conventional manner.

In various other alternatives in the practice of the invention, there may be intermediate conversions and reconversions of optical signals to 10-Base-T signals before arriving at the central office. In addition, various multiplexing and de-multiplexing of the optical signals can be carried out to increase the efficiency and throughput of the system.

In accordance with another feature of the invention, the host digital terminal is adapted for separating digitized PCM voice signals originating from the subscriber's telephone sets, from the data packets generated by the subscriber's personal computer, whereby the digitized voice signals are routed to the central office for switching via the switch fabric, and the data packets bypass the switching fabric and are routed to the internet bridge.

In accordance with yet another feature of the invention, the data packets generated by the subscriber's computer are preferably those that comply with the Ethernet protocol. In this manner, standard commercial personal computer software and hardware can be utilized to transmit and receive the Ethernet data packets at a 10 MHz rate, without employing any new personal computer software or hardware. By carrying out the internet bidirectional communications via Ethernet data packets, the response time to the subscriber in receiving large masses of internet information, such as multimedia information, is substantially facilitated, as compared to the traditional 28.8 K data rate of a personal computer modem.

DETAILED DESCRIPTION OF THE INVENTION

Conventional Internet Connection

The various aspects of the invention are best understood by comparison with the current technique for connecting a subscriber to the internet network, as shown inFIG. 1. Although many different variations of the network connection exist in actual practice,FIG. 1is illustrative of the manner in which a user having a personal computer10, or the like, is connected via different telecommunications systems and computers to the internet backbone, designated as reference numeral12. Typically, the user's computer10is coupled by way of a modem14to a conventional 24-26 gauge twisted pair telephone line16, as is the subscriber's telephone set18. Either the user or the user's personal computer10is dynamically assigned a unique IP address when the subscriber is registered or otherwise authorized to access the internet12. The modems14in widespread use are generally capable of transferring data at a baud rate of about 28.8 K bits per second. Accordingly, even though the subscriber line16is capable of transmitting data at a rate of 10 MHz, such data rate cannot be realized because it is limited to the lower baud rate of the analog modem14and intervening channel card CODEC circuits and corresponding filters. The computer modem14converts a serial digital data stream generated by the computer10into corresponding QAM analog signals transferred over the telephone line16to a local central office20. The standard telephone line16has tip and ring conductors that are twisted together. It is a common practice in the installation of telecommunication services to a household or business to install at least two or more twisted pairs, even if only a single pair is to be utilized. As can be appreciated, a telephone line16can only be utilized at one time by either the computer10or the telephone set18.

The central office20is a switching system operated by a local telephone company for serving numerous residential and business customers with telephone and other telecommunication services. Indeed, and while not shown, the central office20is connected to other central offices by trunks, as well as to other toll switching systems for carrying toll-type telephone traffic. The various and sundry other communication services and equipment is denoted inFIG. 1as the public switched network22.

With regard to the local central office20, whether the communication traffic is transported by way of telephone sets18or computers10, such traffic is switched through the switching fabric24and therefrom to either a local or remote destination. The switching fabric24can constitute a wide variety of apparatus adapted for providing an electrical connection between the subscriber and the destination for as long as the subscriber is off-hook and using the telephone line16. The connection afforded by the switching fabric24can be maintained for as few as several seconds for short voice communications using the telephone set18, or many hours, which is typical of subscribers using personal computers10to access the internet12. The actual connection in the switching fabric24can be either by way of relays or other similar switches, as is common in step-by-step, panel and cross-bar type of central offices, or can be electronically switched such as in the time division multiplexed switching fabrics of electronic switching systems. Irrespective of the utilization of either space or time-switching fabrics24employed by the specific type of central office20, the switching connection is dedicated to the user, and only to that user, for so long as the subscriber is communicating with the destination.

The traffic load of a central office switching system20is dependant upon the number of subscribers and a host of other parameters that are statistically considered to entitle the various users the fulfillment of communication needs without having to wait before being allocated usage thereof. The telephone traffic patterns have in the past anticipated that the majority of calls would be those initiated by telephone sets18, and which last statistically on an average of about 100 seconds. However, with the widespread use of modems14and computers10in both the residential and business environments, the time that each subscriber utilizes the services of the switching system20, and thus the switching fabric24, has increased substantially, thereby placing severe burdens on the traffic capacity of the central offices20. As noted above, one way to resolve this burden is to expand the capacity of the switching fabric24of the central office, or add additional central office switching equipment, both options of which are extremely expensive. As set forth more fully below, the present invention not only provides user connections to the internet without burdening the switching fabric24, but the information transferred between the user and the internet is at a much higher speed and therefore the response time as seen by the subscriber is much faster.

With reference again to the establishing of a connection to the internet backbone12, shown inFIG. 1, the public switched network22provides a connection to the specific service provider26-28, depending upon which provider the subscriber has paid for such services. Each service provider has a domain name which, when input into the computer10by the subscriber, uniquely identifies the particular service provider through which access to the internet12can be obtained. The domain name may be in the nature of “mainhost.abcde.net”, which allows the public switched network to route the subscriber to the particular service provider. The service provider26-28will verify that the subscriber is authorized to access the internet, by verifying the user name, password and MAC layer address of the computer10, as imbedded in the Ethernet LAN card.

After confirming that the subscriber is authorized to access the internet12, the particular service provider26accesses a web site32by way of a dedicated leased communication line30and the internet backbone12. The web site32can be a government office, a university, a business, etc. that has a direct connection to the internet backbone12. In the event the web site32is a university, the address thereof may be in the nature of “http://www.efg.edu.” The foregoing is an example of the equipment and systems employed in completing a bidirectional communication channel between the computer10of the subscriber and the internet12.

Generally, access requests dispatched from the computer10are short commands, whereas the information transferred from the internet12to the computer10can be substantial volumes of data, which may include video, text, etc. In order to transfer large volumes of data and to reproduce the same on the monitor or CRT of the computer10, certain time delays are involved. The time delays are primarily a result of the speed of the modem14, which by today's is a 28.8 K baud rate. It is not uncommon for time periods of 10-30 seconds to elapse between the request of information from the internet12, and the corresponding display thereof to the subscriber.

As can be appreciated, there currently exists no type of arrangement where computer equipment can be networked together, except with the traditional LAN protocols. As noted above, such protocols generally impose an area limitation on the network connections to preserve the collision avoidance algorithms. Moreover, to extend high speed data lines, like fiber to the curb, such service would not be highly cost effective, as the telephone line and modem equipment do not presently warrant such a high speed and expensive connections. The utilization of the present invention provides the incentive to provide fiber to the curb telecommunication services.

Switching Fabric Bypass of Internet Connections

With reference toFIG. 2, there is depicted in generalized block diagram form a technique for connecting a computer10to the internet12without involving the switching fabric24of the central office20. A digital interface system40is preferably located within about 500 feet (as per the Bellcore TR-909 standard) from the residence or office housing the computer10and telephone set18so as to be connected by standard twisted pair telephone conductors that can accommodate 10-Base-T transmission. The telephone set18is connected by one standard telephone pair16, while the computer10is connected to the digital interface40by differential transmit and receive pairs17and19. The digital interface40serves to provide conversion of analog signals to corresponding digital signals, on-hook, off-hook and other signaling, alarm and maintenance, and digital communications of voice-signals with the central office20by way of a digital carrier42, such as the standard T1 or other carrier system. In addition, the digital interface40provides a connection between the personal computer10and the internet12by way of an Ethernet switch or router44and other standard high speed digital lines46. While not shown, the digital line46will be interconnected by way of one or more leased lines dedicated to the service provider solely for internet use. Such lines46are standard equipment presently used for connecting subscribers to the internet backbone12. The digital information transferred between the interface40and the internet router44on path45can be by way of electrical or optical signals. Moreover, the signals carried on path45can be packets of data, such as generated according to the Ethernet protocol, or other hybrid technologies such as HDSL or ADSL to provide LAN connection to and from the subscriber. Importantly, other digital equipment, such as other computers can be networked together using the digital interface40. Indeed, by employing the techniques described in detail below, the Ethernet protocol can yet be employed, as well as all the standard Ethernet equipment, but the geographical area of LAN connections can be greatly expanded.

In brief operation, the digital interface40couples all communications received by the telephone set18on the subscriber line16and directed to the central office20, in the standard manner for switching via the fabric24to a destination. On the other hand, the digital interface40receives access commands on the twisted pair transmit line17connected to the computer10, and transmits data packets to the computer10on the twisted pair receive line19. When the digital interface40receives the access command, such request is initially transferred via the digital line45to the central office20, to a domain name server, which determines whether the computer10is authorized for access to the internet services12. If so, the central office signals the digital interface40by way of the digital lines45, whereupon the interface40provides a connection between the computer10and the internet leased line46. In this manner, the computer10is connected to the internet services12without hampering or otherwise impeding the usage of the switching fabric24of the central office20for voice and other standard communications.

In accordance with an important feature of the invention, the digital interface40preferably comprises a host digital terminal (HDT) coupled to an optical network unit (ONU) by way of an optical fiber to provide a large bandwidth usable by numerous subscribers serviced by the digital interface40. In view that the standard telephone conductor pairs17and19are capable of carrying 10 MHz digital signals, the optical fiber circuits do not present a bottleneck for such signals, even when plural users connected to the digital interface40are accessing the internet services12at the same time. More preferably, two twisted pairs17and19are employed to provide high speed differential transmit and differential receive Ethernet LAN capabilities to the subscriber computer10. The usage of an additional transmission pair does not normally involve an impediment, as more than one twisted pair are generally installed at the residence or business office.

In accordance with another important feature of the present invention, a modem14is not required in the practice of the present invention. Rather, and to be described in more detail below, Ethernet transmission control protocol (TCP/IP) packets or internet protocol exchange (IPX) packets of data are employed in transmitting requests, instructions, commands, data, etc. between the subscriber computer10and the internet12. Both the host digital terminal and the optical network unit can be spaced apart a distance far greater than the 328 feet spacing previously limited by signal attenuation concerns. In addition, both the HDT and the ONU employ collision avoidance algorithm, as well as data packet buffer memories to provide networking of the data packets between all the plural ONU's, without using the conventional Ethernet bridges.

As an alternative to the utilization of fiber optic circuits, and as noted above, specialized hybrid transport technologies, such as HDSL or ADSL can be employed. Set forth below is another embodiment of the invention in which the local area network is extended several hundred miles between two network extenders using a DS1 line. Indeed, the primary transport of universal data according to the invention is by way of standard Ethernet packets generated and received directly by the subscriber computer10. By employing the Ethernet TCP/IP or IPX packet transport protocol, or other types of well-known data packet transmission protocols, the cost to the subscriber is minimal, as such technology is already well developed and commercially available. As will be set forth more fully below, the digital interface40functions to extend transmission of the LAN packet data without utilizing an expensive Ethernet or other type of bridge.

In order to accommodate the advantages of the invention, an Ethernet LAN interface card, or other LAN protocol cards that are readily available on the market, are simply installed in the subscriber computer10. The required software or “protocol stack” and network service/client functions are already integrated into popular personal computer operating systems, such as the Windows and Macintosh operating systems. Accordingly, the subscriber need only purchase a low cost LAN interface card, and in most likelihood, no special or proprietary software is required as many subscriber computers10already employ operating systems that support the Ethernet LAN packet transport protocol.

FIG. 3illustrates in more detail the various features of the digital interface40, which comprises a host digital terminal50connected to the central office router44by way of the digital line45. In the preferred embodiment of the invention, the host digital terminal50can comprise a DISC*S host digital terminal, obtainable from RELTEC Corporation, Bedford, Tex. Such equipment is conventionally available for providing the transport of PCM voice signals to the central office20via a digital line42. The DISC*S FITL (fiber in the loop) equipment configured with a DISC*S ONU provides fiber to the curb capabilities. When modified to provide distributed hub capabilities, as described below, a highly versatile system is achieved. The host digital terminal50can be connected via the router44to the domain name server52which may be also located within the central office20. The internet router44can be coupled to other central offices, such as noted inFIG. 3, by dedicated T1 or higher speed inter-office links. The internet router44is connected by a high speed connection, via a dedicated data link46, to provide a connection appearance to the internet via high speed leased lines. While not shown, the connection appearance to the internet12is by way of other high speed leased lines which ultimately connect to the internet “backbone.”

Each host digital terminal50includes digital carrier equipment for transporting digitized PCM voice signals and Ethernet data packets to the switching system20via the respective digital carrier lines42and45. Those skilled in the art may find that both the PCM, DS1 and PC data packets can be efficiently multiplexed together and transported on a single line to the central office20, where such signals are then separated from each other. The host digital terminal50can serve one or more optical interface units54to provide an optical-electrical and electrical-optical interface between the host digital terminal50and the digital transmission lines42and45. The host digital terminal50is also connected to one or more optical network units56by a respective optical fiber58. Based on the statistical usage data or the traffic expected with respect to each optical network unit56, each such unit is contemplated to provide service to at least four computers10. In addition, it is contemplated that each optical network unit56can provide service to about twelve telephone sets. When utilized for residential connections, the optical network unit56is located within about five hundred feet of the respective residences in accordance with the Bellcore TR-909 standard so that two twisted pair cables can be connected to each computer10. In like manner, each telephone set is connected to the optical network unit56by a single standard telephone twisted pair. The length of the optical fiber58is expected to be no longer than about 12,000 feet, without repeaters. Thus, the radius of networked connections with respect to each host digital terminal50is about 12,000 feet, as compared to the Ethernet standard of 328 feet.

The other central offices60and62can be similarly connected to respective host digital terminals and optical network units to thereby provide communication services to numerous other residences or businesses. Each central office is connected by a dedicated DS1 (1.544 MHz) or higher speed inter-office link64to the router44of the central office20having situated therein the domain name server52. Hence, in a connection of any computer10to any of the central offices20,60and62, the LAN packet information can be transferred to and from the internet12without involving the switching fabric of any of the central offices. In this manner, subscribers can fully utilize the information dispersal of the internet, without tying up or otherwise increasing the load on the central office switching systems. Equally important, each computer101-104is connected together with the Ethernet protocol by the optical network unit561, as well as to the computers (not shown) associated with the other optical network units562-564. As will be explained below, the host digital terminal50provides an additional level of networking between each of the optical network units561-564so that all computers are networked together and collision avoidance protection is provided. This arrangement thereby provides a distributed hub function to geographically extend the Ethernet network without the use of bridges.

FIG. 4is a more detailed diagram showing the central office20, the host digital terminal50and the optical network units56ofFIG. 3. Each host digital terminal50can support a group70of optical network units56. In the preferred embodiment of the invention, and due particularly to the hardware architecture design, the host digital terminal50is equipped to support eight optical network units56, each of which can, in turn, support twelve telephone sets18and four personal computers10. In this configuration, a single host digital terminal50can provide telephone service to ninety-six telephone sets and can provide Ethernet hub connections between thirty-two computers. Again, the number of telephone sets and personal computers supported by a single optical network unit56is solely dependent upon the equipment and the nature of the subscribers, the expected peak usage and other parameters. While telephone sets and computers are disclosed as the typical equipment connected to the optical network units56, the invention can provide the full advantages thereof when utilized with other devices or equipment. Although each telephone set18and each personal computer10can be connected to the optical network unit56by standard twisted pairs, such conductors are dedicated on the respective I/O ports of the optical network unit56to either telephone sets or to computers10. In other words, the twelve (or twenty-four) twisted pairs coupled to a first type of optical network unit port can serve only telephone sets18, and an additional eight twisted pairs connected to an Ethernet I/O port can only support differential transmit and receive data packets of four personal computers. In this manner, based on which twisted pair is active (i.e., off-hook), the optical network unit56can readily identify whether the electrical signals coupled thereon are from a personal computer10or from a telephone set18. Indeed, subscribers and other users can nonetheless utilize a standard modem connected to the subscriber telephone line16and transmit and/or receive modulated QAM signals via the optical network unit56and to the central office20for switching through the fabric24in a conventional manner. In this event, the optical network unit56treats the computer FSK signals in the same manner as that from any telephone set18. As will be described in more detail below, each optical network unit56employs integrated circuits for switching or otherwise transferring data packets according to the Ethernet protocol.

In the preferred embodiment, the optical network units provide fiber optic transmission capability in accordance with the Bellcore TR-909 standard. Preferably, each pedestal optical network unit services customers, whether residential, apartment, business, etc, when within about 500 feet thereof. Standard 22 gauge twisted pair conductors suitable for carrying 10 Mb/s data can provide pots and digital service to each subscriber in the locale of the optical network unit.

Each optical network unit56further includes conventional digital channel units having CODECs for converting analog voice signals to corresponding digital signals, and vice versa, for allowing voice communications between the telephone sets18and a dialed destination. While not shown inFIG. 1, optical and electrical circuits also constitute a part of each optical network unit56to convert PCM voice data originating as analog signals from the telephone sets18, and digital packet data from the computers10into corresponding optical signals, and vice versa. The optical signals are carried on a fiber58to an optical channel shelf54located in the host digital terminal50. Although the optical fiber58is capable of carrying high bandwidth signals, it is contemplated that in the embodiment ofFIG. 4, a 12 megabit per second optical data rate is sufficient to accommodate the traffic expected by twelve to twenty-four telephone sets and four personal computers. As will be described more fully below, each optical network unit56is equipped with circuits for transporting transmit/receive data packets of the Ethernet protocol, between any of the computers associated with the unit and to the host digital. The host digital terminal50provides LAN network capabilities between each of the optical network units. moreover, each optical network unit and the host digital terminal are provided with collision detection capabilities to coordinate the transmit/receive data packets according to the Ethernet protocol. This networking of the computer10is carried out efficiently and reliably despite that the 10-Base-T lines may be up to 500 feet long and the fiber optic line58may extend up to above 12,000 feet without the use of optical repeaters.

The optical channel shelf54in the host digital terminal50includes eight substantially identical channels, each optical channel associated with a corresponding optical network unit56. The optical signals of each channel are converted to corresponding electrical signals. The optical channel shelf separates the PCM and any DS1 signals from the PC data packets, and passes the PCM and DS1 signals to the central office20. The PC data packets are temporarily stored in a respective buffer memory. Each channel unit includes a circuit that provides collision avoidance of the data packets transmitted to or received by such channel unit. If a high speed bidirectional data bus60is idle, then one channel unit will place a data packet thereon for receipt by each of the other seven channel units. In this manner, each of the other seven channel units can temporarily store the received data packet and retransmit it back to the respective optical network unit, where it will then be transmitted and echoed to each of the four computers10. Once the data packet is placed on the high speed bus60, the optical maintenance unit62temporarily stores the data packet and checks for potential collision avoidance with a 10-Base-T bus64connected to one of twenty-four ports of a Fast Ethernet switch or other similar Ethernet switching equipment. The Fast Ethernet switch66is conventionally available for combining plural 10-Base-T inputs and for coupling a pair of 100-Base-T lines68to the local central office20. As noted above, the optical channel shelf functions to separate the PCM voice signals from the computer data packets. The data packet information is routed to the central office and is separately switched or otherwise routed so as to avoid being coupled to the switching fabric, identified as the “local switch” inFIG. 4.

As noted above, Ethernet LAN cards are conventionally available for many type of computers, as is the protocol stack that merges the Ethernet protocol with the TCP/IP or IPX packets for accessing the internet. Accordingly, the Ethernet TCP/IP or IPX data packets are generated at the personal computers10and carried either as optical or electrical signals to the central office20. It is important to note that in accordance with an important feature of the invention, the optical network units70and the optical channel units54only transport the transmit/receive data packets, but do not decode the various fields and carry out processing thereof, as do conventional Ethernet bridges. As such, the switching and transport speed of the data packets through the circuits of the invention are significantly enhanced.

With reference again to the Ethernet switch66, the multiplex data packets are transferred on the 100 Mbit/s line68to the central office, and then to other cross-connect or interface equipment72. From the cross-connect interface72, the signals are transferred to an internet router74, and therefrom to the internet by a downstream high speed line46. As can be appreciated, not only are the data packets networked between the various computers by the distributed hub, but such data also bypasses the switching fabric of the central office20. While not shown, the central office may also be equipped with one or more domain name servers so that the central office can function as an internet service provider.

With reference back to the host digital terminal50, it is noted that the PCM voice data is separated from the data packets by circuits in the optical channel unit54. In view that each telephone set18and each computer10has a dedicated input/output port on the optical network unit56, such information is readily identified as to source, and thus can be multiplexed into specified time slots of a transmission frame. The specific time slot and framing format utilized is not a part of the present invention, as many different framing formats and protocols can be employed by those skilled in the art. In any event, based on the PCM voice signals and any DS1 data received by the optical channel unit54from the respective optical network units56, such data is separated and coupled on a PCM bus to PCM channel equipment78, or other PCM equipment adapted for transmitting such type of data. In the preferred embodiment of the invention, the PCM channel equipment may include DISC*S HDT equipment obtainable from RELTEC Corporation, Bedford, Tex. In any event, the PCM data is coupled from the host digital terminal50to the central office20by way of a DS1, optical or other type of transmission line42. The PCM voice data is processed by the central office20by way of a multiplexer or other type of interface82and coupled to the public switched network22by way of the local switch fabric24.

Optical Interface Units—Distributed Hub

In order to better understand the structure and operation of the distributed hub according to the invention, reference is made toFIG. 5. Shown is the distributed hub architecture constructed according to the preferred embodiment of the invention. There are shown eight optical network units56, each equipped with optical interface circuits90providing four ports for personal computer (PC) data packets and one port for a DS1 digital line. The optical interface circuits90are connected to respective PCM channel units92for converting analog signals received on the subscriber telephone line16to corresponding PCM digital signals. The PCM channel unit92can typically accommodate 12 to 24 voice grade telephone lines. The optical interface unit90receives the PC data packets from the four computer lines, the digital signals from the DS1 line and the PCM signals from the telephone lines and multiplexes the same according to a predefined scheme as optical signals on the twelve Mbit/s optical fiber line58. As noted above, based on the particular port in which the analog or digital signals are coupled to the optical network unit56, such signals are identified thereby and multiplexed in prescribed time slots, as optical signals on the fiber line58. While not shown, the optical interface circuits90include a standard Ethernet hub repeater circuit with four ports for networking the PC data packets between the four computers connected thereto. Other circuits in the optical interface circuit90are programmed to provide collision detection and avoidance between data packets received on the optical fiber58and PC data packets received from the hub repeater circuit. With this arrangement, each computer connected to a particular optical network unit56is networked together, and in addition PC data packets can be transmitted and received from the optical channel shelf54to the particular optical network unit56. It can be appreciated that the circuits in the optical network unit56effectively extend the hub function to the optical channel shelf. Each of the eight optical network units operate in an identical manner for networking the PC data packets to the computers connected thereto, as well as extending the data packets to a respective circuit in the optical channel shelf54. The data rate on any one of the differential transmit or receive computer lines can be transported at a 10 Mbit/s rate. However, the transmit and receive data rate on the optical fiber58is 12.352 Mbit/s. While only a single optical fiber58is shown, those skilled in the art may readily utilize one fiber for transmit functions and another fiber for receive functions.

An additional layer or level of networking of the PC data packets is provided in the optical channel shelf54. Here, eight substantially identical optical interface units94have at least one optical port for transporting transmit/receive optical data from the associated optical network unit56. In addition, each optical interface circuit94is coupled together by a wired-OR 10 Mbit/s data bus60. In practice, the data bus60comprises a 4-bit transmit bus and a 4-bit receive bus, where eight bits of transmit data can be transported in a single clock cycle, and eight bits of receive data can be transferred in a single cycle. A PCM data bus76is also connected to each of the optical interface circuits94for coupling the PCM voice data separated by each circuit from the data packets. The PCM bus76also carries the DS1 signals that are separated from the computer data packets by the optical interface circuits94. Accordingly, the optical channel shelf54functions to separate the computer PC data packets from the other digital signals that are coupled to the local central office or other type of telecommunication switching system for further transfer and switching according to conventional techniques.

Each optical interface circuit94of the channel shelf54includes a buffer memory and collision detection/avoidance circuits that function to prevent the simultaneous use of the respective buses. In operation, each optical interface circuit94checks the idle status of both the data bus60as well as the electrical digital signals converted from optical signals from the optical line58to determine whether the respective bus is busy so that a data packet received on one bus can be transmitted to the other bus. It is significant to note that any one of the eight optical interface circuits94can only transmit on the data bus60at the same instance, and only when such bus is not also being used for transmission of data packets by the optical maintenance unit62. It is also important to understand that when any one of the optical interface circuits94, or the optical maintenance units62, transmits a PC data packet on the data bus60, such data packet is received by the other seven optical interface circuits94, converted to corresponding optical signals and transmitted on the respective fiber to the associated optical network unit56. Each optical interface circuit90of the respective optical network unit56receives the data packet, verifies the idle nature of the line, and then retransmits the data packet to the various computer connected thereto. As can be appreciated, any data packet transmitted by any one computer is received by all the other computers by way of the distributed hub shown inFIG. 5.

With regard to any data packet placed on the data bus60by any one of the optical interface circuits94, the optical maintenance unit62also temporarily stores such data packet, checks for the idle nature of the 10-Base-T line64, and if idle retransmits the data packet on such line to the Ethernet switch66. Again, it can be seen that the optical maintenance unit62provides yet another layer or level of collision detection/avoidance for the transport of the data packets between the optical channel shelf54and the Ethernet switch66. Accordingly, in addition to the networking of the data packets between each of the computers, any data packet transmitted by any of the computers is received by the Ethernet switch and transferred on the 100 Mbit/s line45. In the preferred embodiment of the invention, the line45is extended to a central office for subsequent routing to the internet. However, the data packets can be processed or otherwise routed to other destinations in any manner desired by those skilled in the art.

While the distributed hub shown inFIG. 5includes circuits for integrating PCM voice data and DS1 signals with computer data packets, such integration is not a necessity. Those skilled in the art may find that the distributed hub can be employed solely for carrying Ethernet data packets in a network fashion over a geographical area significantly larger than anticipated by the IEEE 802.3 standard. In practice, it has been found that when the invention is employed as shown for accessing the internet, a 1 Mbyte file can be downloaded from the internet in about one second, as compared to five to fifteen minutes when using a 28.8 Kb/s modem. Moreover, and as noted above, while higher speed lines and data modems can be employed, the access speed can be improved, but networking capabilities are not readily achievable or available. It should also be noted that while the preferred embodiment provides a distributed networking capability using the Ethernet protocol, the principles and concepts of the invention can be employed with equal effectiveness with other types of network protocols.

FIG. 6illustrates in block diagram form the major functional circuits of the optical interface circuit90that is part of the optical network unit56of ofFIG. 5. The optical interface circuit90includes a field programmable gate array chip100having three general I/O digital ports. The digital signals carried by each of the three electrical digital ports are multiplexed together according to a predefined framing format, and converted to corresponding optical signals for transport on the optical fiber line58. The first digital port102transports DS1 digital signals processed by a line interface unit104. The line interface unit104transmits and receives digital signals from DS1 lines106and processes the asynchronous signals to identify the various frames of data, to stuff bits into various time slots based on the number of digital zeroes encountered, and carries out other routine functions that are well known by those skilled in the art. Secondly, the gate array chip100includes PCM buses108for transmitting and receiving serial PCM bits from the PCM channel unit92ofFIG. 5. Lastly, the gate array chip100includes a third digital port110coupled to the serial I/O data port of a conventional hub repeater chip112. The hub repeater chip is a standard 20 MHz device having at least four differential I/O ports for connection by 10-Base-T lines to respective personal computers. Hub repeater chips of such type LXT914 (Level One, Inc.), are conventionally available. Importantly, the hub repeater chip112provides Ethernet hub functions according to the standard IEEE 802.3 protocol. In other words, the hub repeater chip112determines the idle status of the I/O line110and the four differential inputs to determine if a data transmission can take place and thus to provide collision detection/avoidance functions. As is common with such type of chip, the data transmitted by a computer on any one of the four differential inputs is echoed to the other three differential inputs to thereby network the data packets. In addition, the data packets (or frames) are transported to the gate array chip100on the serial line110.

As will be described in more detail below, the gate array chip100includes a static RAM114for temporarily storing all the PC digital packet data that is either transmitted by or received from the serial port110of the chip. As noted above, data packets, PCM data and DS1 data found to be transferrable by the gate array chip100toward the optical fiber58are multiplexed in a predefined format and transmitted as electrical signals to a laser driver116and converted to optical signals. The optical signals corresponding to the data are transferred to an optical duplexer118and driven as light signals on the optical fiber58. Optical signals received by the duplexer118from the fiber58are transferred to an optical receiver120, converted to corresponding electrical signals, and then coupled to the gate array chip100.

The laser driver116, the optical duplexer118and the optical receiver120are not part of the invention, and can be implemented with a host of different optical/electrical apparatus. Indeed, instead of using a single optical fiber58, one fiber can be used for transmission, another fiber for receiving signals, and the duplexer can thus be eliminated by coupling the two optical lines directly to the respective laser driver116and optical receiver120.

Based on the electrical signals input into the gate array chip100from the optical receiver120on an Rdata line, a voltage controlled crystal oscillator122is provided to recover clock pulses from the received NRZ signals. It is noted that while a field programmable gate array100is well adapted for the development of prototypes and the like, it is contemplated that a masked semiconductor device is ideally suited in terms of cost and speed considerations. Indeed, those skilled in the art may find that a high speed digital signal processor may function with equal effectiveness, but at a higher cost due to both device cost and software development.

FIG. 7illustrates in block diagram form the optical interface circuit94that is repeated as eight identical circuits in the optical channel shelf54ofFIG. 5. In the preferred form of the invention, the circuit ofFIG. 7is connected by the optical fiber line58to the circuit ofFIG. 6. The optical interface unit94ofFIG. 7includes an optical duplexer124for coupling transmit/receive optical signals to the optical fiber58. In addition, a laser driver126and an optical receiver128are coupled to the optical duplexer124as well as to a field programmable gate array chip130. The optical circuits124,126and128perform functions substantially identical to those described above in connection with the circuit ofFIG. 6. The gate array chip130includes memory control circuits for reading and writing a static random access memory132. Digital data of any type input to the gate array chip130is initially stored in the memory132and transmitted thereafter, if the bus or line on which the data is to be delivered is not then busy. To that end, the gate array chip130is programmed to provide collision detection/avoidance functions. DS1 data communicated between DS1 lines134and the gate array chip130is processed in a conventional manner by a line interface unit136. A data packet bus60provides a transmit/receive bus with regard to the gate array chip130. In practice, the data packet bus60includes a 4-bit transmit bus and a 4-bit receive bus that are connected to the other seven optical interface units94of the optical channel shelf54. Lastly, an 8-bit PCM bus76is connected in common to the other similar buses of the optical channel shelf circuits. The PCM bus76carries the PCM voice signals from the various subscribers associated with the optical network units56, to the digital terminal for further transmission and processing by the central office.

Each gate array chip130of the optical channel shelf54is provided with clock signals from the common equipment shelf, or other circuits of the digital terminal. The digital terminal includes common digital carrier equipment for transmitting and receiving digitized voice signals according to conventional telecommunications protocols, such as the T1 carrier format. The system clock is input to each gate array chip130by way of a phase locked loop circuit138that multiplies the clock rate by a factor of eight. The frequency typically input from the phase lock loop138to the gate array chip130is 12.352 MHz.

In the following detailed description of the optical interface circuits90(FIG. 6) and 94(FIG. 7), it is important to understand the functions provided, rather than the actual hardware or circuitry that provides such functions. As such, those skilled in the art may find that in other situations the functions can be more efficiently carried out or better adapted by using digital processors and/or other software techniques.

Data Packet Transporting Circuits

With reference now toFIG. 8, there is illustrated in detailed block diagram form the functional circuits of the gate array chip100of the optical interface unit90. In the preferred form of the invention, the gate array chip100is fabricated of CMOS circuits in a silicon semiconductor die. This is primarily the case because of the high speed and low cost considerations of such type of circuit construction.

The gate array chip100shown inFIG. 8includes the circuits for carrying out the distributed hub function for the optical interface circuit90of the optical network unit56shown inFIG. 5. In accordance with an important feature of the gate array chip100, the data packets input thereto by way of the 10-Base-T PC data bus110or the Rdata bus is temporarily stored in the static random access memory114. Thereafter, when the selected bus on which such data is to be transmitted is found to be idle, the data packet or frame is read from the memory114and transmitted accordingly. The memory114is sectioned so as to store data packets received from the PC data bus110(as received from the subscriber's computers) in one section of the memory114, and to store frames of Rdata as received from the fiber optic line58in another section of the memory114. The memory114is a device that preferably has an access speed of 25 nanoseconds and a total storage capability of 32 K by 8 bits. The address, read and write control of the memory114is controlled by a RAM interface circuit150and a RAM access state machine152. The RAM interface150includes register circuits for generating addresses as specified by the state machine152, and includes bidirectional data latches for providing an input and output path of data to the memory114. The RAM interface is coupled by a 14-bit address line154and an 8-bit data line156to the memory114. The RAM interface150includes other counters, registers and standard memory control circuits well known to those skilled in the art.

The RAM interface circuit150is controlled by the RAM access state machine152by a number of control lines extended therebetween. The RAM access state machine152includes an output enable line158and a write enable line160for controlling the reading and writing of the memory114. As will be described more thoroughly below, the RAM access state machine152includes signal and handshake lines extended to other circuits of the gate array chip100for coordinating the transmission and receipt of PC data packets and other PCM and DS1 data between the numerous IO ports thereof. In addition, the RAM access state machine152includes a receive frame counter and a transmit frame counter for maintaining an account of the respective frames of PC data stored in the memory114. In other words, when a PC data frame is received from the PC data I/O port110, such counter is incremented accordingly. On the other hand, when such frame of data is read from the memory and transmitted to the transmit framer circuit, the respective counter is decremented.

On the other hand, when PC packet data is received from the receive framer circuit and stored in the memory, a transmit frame counter is incremented. When such data is read from the memory and transported to the PC data I/O port110, the transmit frame counter is decremented. It can be seen that the receive frame counter is associated with one section of the memory, and the transmit frame counter is associated with the other section of the memory. In this manner, whenever the counters are greater than unity, received data from one of the input ports has been temporarily stored in the gate array chip100and is required to be transmitted as quickly as possible thereafter to the appropriate output port. In order to maximize the throughput efficiency of the chip, the SRAM114is a high speed memory that can be written and read at a high speed rate. As will be described below, the RAM access state machine determines whether a frame of PC data is bona fide, and otherwise controls the destination of the PC data packets with respect to the various ports of the gate array chip100.

A receive framer170and a transmit framer178are instrumental in coupling receive data and transmit data with respect to the fiber optic line58. Further, the transmit framer178receives 8 bits of parallel data on bus204from a backplane interface184. The data coupled on this bus is PCM voice and other digital data, signals and alarms according to the conventional T1 type of channel equipment. The transmit framer178also receives 8-bits of DS1 data on bus202. A DS1 interface188couples 8-bits of DS1 data on bus202to the transmit framer178. Lastly, the transmit framer178receives 8-bits of parallel data on bus200from the RAM interface150. The data coupled to the transmit framer178on bus200is the PC data packets received via the 10-Base-T interface162and temporarily stored in the memory114. In addition, the transmit framer178is coupled by a number of control and signal lines199to a transmit state machine198. The transmit framer178also includes an alarm input port (not shown) for coupling and multiplexing alarm signals onto the Tdata line. The transmit framer178includes a four-port multiplexer for multiplexing the data placed on the buses200,202,204and the alarm bus (not shown) to a single 8-bit multiplexer output. Then, the eight parallel bits are coupled to a parallel-to-serial converter for converting the eight parallel bits to eight serial bits. Moreover, the transmit framer178includes a scrambler circuit for scrambling the bits according to a fifteenth order polynomial algorithm. This is a standard scrambling technique well known by those skilled in the art.

The transmit state machine198controls the transmit framer178as to which input port to be multiplexed to the output, in accordance with a predefined framing format. To that end, the transmit state machine198is designed to multiplex the PCM data from the backplane interface184, the DS1 data from the DS1 interface188and the PC data packets received indirectly from the 10-Base-T interface162, as well as the alarms, onto a serial Tdata line. The particular multiplexing format employed is not a part of the current invention, as many different data stream formats can be employed. It is noted that a primary function between the transmit framer178and the transmit state machine198is the signaling to the RAM access state machine152the time periods in which data stored in the memory114must be read and provided to the transmit framer178on bus200to fill the predefined time slots.

The receiver framer170operates in conjunction with a receive state machine180for coordinating the receipt of serial data on the incoming Rdata bus. As noted above, the Rdata bus includes multiplexed PC data packets, PCM data, DS1 and perhaps other signaling and control information data multiplexed thereon. The receive framer170includes serial-to-parallel converters, demultiplexers and descramblers for converting the serial data to parallel 8-bit bytes and for distributing such data on the respective 8-bit buses182,186and190. The receive state machine180is coupled to the receive framer170by a number of control and signal lines181for controlling the demultiplexer and other circuits in the receive framer170for distributing data to the various parallel buses182,186and190. The receive state machine180is provided with circuits to recognize the framing intervals of the Rdata frames and to decode the various time slots and the data therein for distribution to the respective parallel buses. As can be appreciated, the same data framing format is employed on the Tdata bus as is employed on the Rdata bus, although this is not a necessary requirement for the operation of the invention.

A clock recovery circuit172receives signals from a voltage controlled crystal oscillator122on input174, and receives the serial Rdata on another input thereof. The clock recovery circuit172includes conventional clock circuits for recovering the clock from the bit rate of the data bits on the Rdata line. The recovered clock signal is coupled to the receive framer170on line176.

The receive state machine180is coupled to the backplane state machine212by one or more signal control lines192. When the receive framer170has received PCM data in the appropriate time slots, the receive state machine180signals to the backplane state machine212on line192of such condition, so that the backplane state machine212can prepare the backplane interface184for receipt of the PCM data byte on bus182. The receive state machine180also communicates with the DS1 interface188on control line196to provide a similar function, namely, for signaling the DS1 interface188that a byte of DS1 data is going to be transferred by the receive framer170on bus186. Lastly, the receive state machine180communicates with the RAM access state machine152on control lines194for signaling the latter that a byte of packet data will be transferred thereto on the 8-bit bus190. As noted above, the RAM access state machine152controls the RAM interface150so that when the byte of PC packet data is transferred on bus190, the data byte is temporarily stored in the interface150and associated with a 14-bit address for writing in the memory114. The receive state machine180also includes circuits for detecting a loss of framing on the Rdata line so that the various circuits of the gate array chip100can be reset and a new framing interval initiated. Recovery signals can be transmitted between the various circuits of the chip100to reset or recover from loss of framing or other failures in the receipt or transmission of data.

The gate array chip100is provided with a backplane interface184for receiving PCM data from the receive framer170on bus182, and for transferring data to the transmit framer178on bus204. The backplane interface184is associated with the backplane state machine212and controlled thereby by control signals on lines218. The backplane interface184includes voice and control signal circuitry as well as parallel-serial converters and serial-parallel converters and other circuits for providing synchronization and clock signals, as is standard in the industry. A pair of serial PCM data buses108are coupled to respective input ports of the backplane interface184. One input port includes a serial transmit port and another port is a serial receive port for communicating PCM data. The backplane interface184provides channel unit synchronization signals216for synchronizing conventional T1 or other type of channels for transmit and receive functions. A clock signal214is also provided to the channel units, as is common in the industry.

The DS1 interface188includes standard DS1 interface circuitry for converting incoming serial DS1 data to parallel data for output on bus202. In like manner, parallel data transmitted to the DS1 interface188on bus186is converted to serial form and output on the serial output line102. The DS1 transmission protocol framing and synchronization is well known to those skilled in the art. While not shown, the series transmit and receive lines102are coupled to a standard DS1 line interface circuit which provides the framing synchronization and formatting operations typical of DS1 transmission protocols.

The 10-Base-T interface102, as noted above, is coupled to a serial bidirectional line110and a parallel 8-bit bidirectional bus166. Associated with the 10-Base-T interface162is a corresponding state machine164for controlling the operation of the interface162, as well as signaling the RAM access state machine152on signal and control lines168. The 10-Base-T interface162includes serial-to-parallel converters, and parallel-to-serial converters, bidirectional multiplexers and control signal circuits. While not shown, the 10-Base-T interface162includes a number of bidirectional control lines extended to the Ethernet hub chip112(FIG. 6). The 10-Base-T state machine164includes Ethernet collision/avoidance circuits that operate in conjunction with the Ethernet hub chip to prevent the simultaneous transmission of data on the same bus110. The 10-Base-T state machine164controls the associated interface162so as to configure it for the reception of data from either the Ethernet hub chip112or from the RAM interface150. Moreover, the 10-Base-T interface162can be controlled to transmit on the serial bus110, or to transmit PC packet data on the parallel bus166. In contrast to the transmit framer178and the receive framer170, the 10-Base-T interface162can be configured to either be a transmitter or a receiver of PC data packets.

As can be appreciated from the foregoing, the 10-Base-T interface162, the RAM interface150, the transmit framer178and the receive framer170function in a coordinated manner to carry PC data packets in one direction, and in the opposite direction, and at the same time avoid collisions therebetween in an overall manner similar to the Ethernet protocol. To that end, the gate array chip100functions to extend and otherwise distribute the Ethernet data packets and thereby function as a distributed Ethernet hub.

The RAM access state machine152operates cyclicly in four distinct time periods, each of which is about 80 nanoseconds, for a total of 320 nanoseconds. During one period of time, the RAM access state machine is responsive to the receive framer170for determining whether a byte of PC data is to be transferred on bus190to the RAM interface150. In the second time period, the RAM access state machine152is responsive to the transmit framer178so that a byte of PC packet data can be transferred from the memory114, via the RAM interface150, to the transmit framer178on bus200. In a third time period, the RAM access state machine152is responsive to the transmission of data from the 10-Base-T interface on bus166to the RAM interface150. In the last time period, the RAM access state machine152is responsive to the reception of data from the memory114via the RAM interface150for transport to the 10-Base-T interface162via the bus166. Insofar as the PCM data or the DS1 data is not stored in the memory114, the RAM access state machine152is not involved in the transport of such data.

An example of the distributed hub and data transporting capability of the gate array chip100, the following is assumed. In transmitting a PC data packet, a frame of data is transported from the computer10to the hub repeater chip112(FIG. 6). The hub repeater chip112conducts its standard collision detection/avoidance routine to determine whether the serial bus110is idle for subsequent transmission of the PC data packet thereon. In addition, the data packet transmitted by one PC is echoed by the hub repeater chip112to the other three PCs connected to such chip.

The hub repeater chip112signals the 10-Base-T interface162on lines not shown, that data is available. In like manner, such signals are transferred from the 10-Base-T interface162to the 10-Base-T state machine164of the presence of a data packet. The 10-Base-T state machine164also receives the preamble of the data packet. The preamble of the Ethernet data packet typically includes the destination and source address as well as which bytes of the frame constitute data. On the initial receipt of the Ethernet data packet, the 10-Base-T state machine164signals the RAM access state machine152on line168of the incoming data packet. When converting the serial input data to parallel bytes, the 10-Base-T state machine162has sufficient time to signal the RAM access state machine152. Indeed, when the first byte of actual data has been converted to parallel form by the 10-Base-T interface162, the state machine164signals the RAM access state machine152that a byte of data is available. The byte of data is transferred as a eight parallel bits on bus166to the RAM interface150, where it is temporarily stored in a data register. Substantially simultaneously, the RAM access state machine152reads an address counter and transfers such address to the RAM interface150to be associated with the byte of data. In addition, the RAM access state machine152increments the address counter in preparation of storing the next byte of data received from the 10-Base-T interface162. With the appropriate 14-bit address on the memory address bus154and the data byte on the data bus156, the RAM access state machine152controls the write enable line160to write the byte of data in the memory114at the address presented thereto. Each successive byte of the Ethernet data packet received by the 10-Base-T interface162is similarly communicated on bus166to the RAM interface150and stored at the next address in the memory114.

The 10-Base-T state machine164includes circuits for counting the incoming bytes of data. If an insufficient number of bytes of data are received to constitute a bona fide Ethernet frame, the 10-Base-T state machine164will signal the RAM access state machine152of the same, whereupon the runt data packet is aborted. In this event, the RAM access state machine152will reload the address register with the prior address that was available before the runt data packet was received. With this arrangement, the runt data packet stored in the memory114will be overwritten with the subsequently received data packet. The RAM access state machine152will also reinitialize the various registers and counters so as to reestablish the states of the circuits as they existed before the runt data packet was received.

The 10-Base-T state machine164also includes circuits for counting and detecting data bytes of an Ethernet packet that exceed 1508 bytes. It is noted that the maximum number of Ethernet data bytes may only be 1508 bytes. Hence, in receiving a frame that has more than this number of bytes, it is known that the data packet is invalid. Again, the 10-Base-T state machine164will signal the RAM access state machine152of the excess number of bytes, whereupon the RAM access state machine152will again reset the address counters and other circuits to the states as they existed before the receipt of the invalid data frame.

In monitoring the receipt of the Ethernet data packet, the 10-Base-T state machine164will detect an end-of-frame (EOF) field. The EOF field is typically a string of digital ones that does not include an escape flag. In detecting an EOF field, the 10-Base-T state machine164signals the RAM access state machine152on line168that the end of the Ethernet frame has been received. When the last byte of data and the end of frame field have been written by the RAM access state machine152, via the RAM interface150into the memory114, the RAM access state machine152increments a receive frame counter. The receive frame counter signifies the temporary storage of a data packet in the memory114. As can be appreciated, the RAM access state machine152includes a 16 K counter corresponding to the 16 K×8 storage capability of bytes received via the 10-Base-T interface162. Should a data frame be received whose number of bytes exceeds the last usable memory location, the RAM access state machine152detects an overflow condition, and aborts the storage of such frame.

As noted above, the RAM access state machine152cyclically determines if there is a request by the transmit state machine198to receive a data byte and transmit the same by way of the transmit framer178. In the example, when the RAM access state machine152determines that there is a data request on line206from the transmit state machine198, it is noted that the receive frame counter is greater than zero. In this event, the RAM access state machine152to signals to the RAM interface150to drive the address bus154with the address of the oldest data byte. The output enable line158and the write enable line160are driven such that the oldest byte stored in the memory114is read and presented on the data bus156. Also, the RAM access state machine152signals the transmit state machine198of the availability of a data byte, whereupon the RAM interface150is controlled to drive the transmit framer data bus200with such byte of data. The transmit state machine198controls the transmit framer178by way of signal and control lines199to receive the data byte from bus200, convert the parallel data to serial data, scramble the data and drive the serial data in the appropriate time slots on the Tdata bus. Periodically, when the PC data time slots are about to exist, the transmit state machine198will signal the RAM access state machine152of the need for another byte of data for transmission on the Tdata line time slots. The RAM access state machine152will continue controlling the RAM interface150to read data bytes and provide the same on bus200to the transmit framer178. When the RAM access state machine152detects an end of frame flag, constituting a number of binary ones, the receive frame counter will be decremented. In the event that the receive frame counter is at a zero count, and the transmit state machine198signals the need for PC data, the RAM access state machine152will control the RAM interface150to produce a byte of all digital ones, indicating an idle condition or flag. The transmission of the idle state by the transmit framer178facilitates the recovery of a clock signal by the optical interface unit94in the optical channel shelf54.

It should be also noted that the transmit state machine198controls the input ports of the transmit framer178so as to receive bytes of data on the respective buses200,202and204, to serialize and scramble such data and present the serial data bits in the appropriate time slots on the Tdata bus. In controlling the transmit framer178, and as noted above, the transmit state machine198signals the backplane state machine212on line210, and signals the DS1 interface188on line208for coupling respective data bytes to the transmit framer178.

Data transported from the Rdata input at the left side ofFIG. 8to the right side thereof is carried out according to the following. PCM data, DS1 data and PC data packets multiplexed on the fiber optic line58are converted to electrical signals and coupled to the Rdata bus. The receive framer170and the clock recovery circuit172receive the data signals. As noted above, a clock signal is recovered from the data string and provides a time base to the receive framer170. The receive state machine180controls the receive framer170by signal and control lines181to appropriately descramble the serial data, convert the same to parallel form and multiplex the PCM data to output bus182, the DS1 data to output bus186and the PC data packets to output bus190. On the receipt of the respective types of data, the receive state machine180signals the other state machines of the same so that data can be transported thereto. With regard to the PC data packets, the RAM access state machine152is signaled on line194by the receive state machine180, whereupon the preamble of the Ethernet data packet is coupled to the RAM interface150on bus190.

All of the PC data packets received from the receive framer170are stored in a different 16 K section of the memory114, as compared to the data packets received by the 10-Base-T interface162. As such, the RAM access state machine152configures addresses registers in the RAM interface150for coordinating the sequential storage of bytes of data received via bus190in the second memory section. It should be understood that the RAM access state machine150allocates one-fourth of its cycle to the receive framer170for receiving PC data packets therefrom. Much like the 10-Base-T state machine164, the receive state machine180also includes circuits for detecting a runt data packet or a data packet that includes too many bytes of data as determined by the Ethernet protocol. When either abnormality occurs, the receive state machine180signals the RAM access state machine152for the resetting of address registers and other counter circuits. In any event, as the bytes of data of an Ethernet frame are transferred to the RAM interface150from the receive framer170, such bytes are sequentially stored at sequential address locations in the second portion of the memory.

When the RAM access state machine152detects an end of frame flag, e.g., an idle flag of all digital ones, a transmit frame counter is incremented. This means that an entire frame of an Ethernet data packet has been stored in the memory114and is ready for transfer to the 10-Base-T interface162. The RAM access state machine signals the 10-Base-T state machine164via control line168that a frame of data is ready for transmission. When the 10-Base-T state machine164signals the RAM access state machine152that it is ready to begin receiving the Ethernet data packet, the RAM access state machine152causes the first byte of the frame to be read from the memory114and transferred to the 10-Base-T interface162as parallel bits on bus166. It should be noted that prior to the signaling by the 10-Base-T state machine164that it is ready to receive the Ethernet data packet, it carries out a collision detection/avoidance routine for determining if the serial bus110is presently being used by the hub repeater chip112. This collision detection/avoidance protocol is substantially the same as that used by the Ethernet protocol. Once the 10-Base-T state machine164causes the corresponding interface162to commence transmission of the Ethernet data packet on the serial line110, the RAM access state machine152continues to read the bytes of the data packet from the memory114and pass the same via the RAM interface150to the 10-Base-T interface162. The 10-Base-T interface162carries out the reverse operation, in that it converts the parallel bits to serial and transmits the same to the hub repeater chip112on the 10-Base-T data line110. When the RAM access state machine152detects the end of the Ethernet data packet, the frame transmit counter will be decremented. Also, the 10-Base-T interface162detects the end of the Ethernet data packet and reinitializes the circuits thereof to transport another data packet on bus166or on serial bus110.

From the foregoing, it is noted that the Rdata and Tdata serial buses are clocked at a 12.352 MHz rate, whereas the 10-Base-T serial data bus110is clocked at a 10 MHz rate. The clock rate of the receive framer170and transmit framer178are primarily a function of the optical transmitting apparatus, whereas the data rate on the serial 10-Base-T interface data bus110is a function of the Ethernet transmission rate. In order to provide a buffering of the transmit and receive PC data packets by the gate array chip100, the temporary storage of the same in the memory114is important.

With reference again toFIG. 5, different types of data are multiplexed by the optical network unit56and carried by the optical line58to the optical channel shelf54. Indeed, each optical interface unit94situated at an optical channel shelf54receives data packets from plural computers, as well as PCM data from plural telephone sets, and data bytes from a DS1 line. Each of the eight optical interface units94of a single optical channel shelf54functions to separate the PC data packets from the PCM data and DS1 data. The latter types of data are transferred on bus76to a digital terminal, as noted inFIG. 5. In contrast, the communication of all PC data packets, whether being transmitted or received by the optical channel shelf54, are coupled via the wired-OR data bus60which, in practice, includes separate 4-bit buses, one for transmit nibbles and one for receive nibbles. Importantly, the Ethernet hub is extended to the optical channel shelf54, in that each optical interface unit94as well as an optical maintenance unit62have circuits for detecting and avoiding collisions based on the attempted simultaneous use of the nibble buses60. In like manner, the optical maintenance unit62and the fast Ethernet switch66are programmed with similar collision detection/avoidance algorithms that are common to the Ethernet protocol. Moreover, when one optical interface unit94transmits an Ethernet data packet on the wired-OR bus60, the other seven units94receive such data packets and retransmit the same to the respective optical network units56. Each optical network unit56then retransmits the data to each associated computer, thereby providing an extended networking of the data packets between all of the computers. It can be seen that the geographical area in which the data packets are networked is substantially larger than that available using either Ethernet equipment, and without using the expensive Ethernet bridges. The radius of the distributed hub according to the invention is the length of the optical line58, plus the length of the 10-Base-T lines17and19. As will be described below, the optical line58of the preferred embodiment can be replaced with a DS1 or other electrical transmission line. The transporting of data information by the optical interface unit94of the optical channel shelf54is described below.

InFIG. 9, there is shown a detailed block diagram of an optical interface unit94that is situated in each optical channel shelf54. As described above in connection withFIG. 7, the serial optical data received on the fiber optic line58is coupled to the optical receiver28and converted to serial, electrical data on the Rdata bus. In like manner, multiplexed serial data is coupled from the gate array chip130on the Tdata line, converted to corresponding optical signals by the laser driver126and then coupled to the optical duplexer124for transmission on the optical fiber line58. The Rdata and Tdata buses carrying serial, multiplexed data are shown inFIG. 9.

Much like the gate array chip100described above in connection withFIG. 8, the gate array chip94ofFIG. 9includes a receive framer220and a clock recovery circuit222that receive the serial data from the Rdata bus. The clock recovery circuit222provides clock signals to the receive framer220to synchronize the incoming serial Rdata. The receive framer220includes serial-to-parallel converters and parallel-to-serial converters as well as a descrambler circuit and bus multiplexers, all controlled by a receive state machine224by way of signal and control lines226. The receive state machine224is also coupled to the RAM access state machine250by signal and control lines254. The receive state machine224includes circuits responsive to the various time slots of the Rdata bus for demultiplexing the data bytes. The DS1 data is demultiplexed and placed on the 8-bit bus228and coupled to a DS1 interface circuit230. PCM and PC data packets are demultiplexed and placed on the 8-bit bus232and coupled to a RAM interface234. In the gate array chip94of the optical channel shelf54, both PCM and PC data packets are stored in a static random access memory (SRAM)236. The DS1 interface230includes a parallel-to-serial converter and other circuits for directly coupling the DS1 data from the parallel bus228to a corresponding serial transmitting bus238. The serial DS1 data on bus238can be further transmitted to the central office20by conventional digital carrier lines, or the like, not shown. The converse conversion of serial DS1 data on a receive line238to parallel data coupled on bus242also takes place.

The gate array chip94includes a transmit framer240that receives data on a parallel 8-bit bus242from the DS1 interface230. In like manner, the transmit framer240receives data on an 8-bit bus244from the RAM interface234. A transmit state machine246controls the transmit framer240on control and signal lines248. The transmit framer240includes two 8-bit multiplexers and a parallel-serial converter, as well as a data scrambler circuit. The transmit state machine246is responsive to the appearance of various time slots of the Tdata bus for placing the DS1 data from bus244thereon, or the PCM and PC data packets on bus244in the appropriate time slots. The transmit state machine246is coupled to a RAM access state machine250by signal and control lines252. In like manner, the RAM access state machine250is coupled to a backplane state machine256by signal and control lines258. The RAM access state machine250includes a number of signal and control lines260for controlling the RAM interface234.

The buffer memory236is a 32 K×8 memory that is sectioned into two 16 K portions. One 16 K×8 portion stores receive PCM data and PC data packet and the other 16 K×8 portion stores transmit PCM and PC packet data. The memory236can be a static random access type having an access time of 25 nanoseconds, or faster. The RAM access state machine250controls the memory236by an output enable line262and a write enable line264. Data is coupled between the memory236and the RAM interface234by an 8-bit data bus266. A 14-bit addresses bus268provides addresses from the RAM interface234to the memory236. The RAM interface234includes circuits that carry out functions substantially identical to the corresponding circuit150of the gate array chip100ofFIG. 8.

Unlike the RAM access state machine152ofFIG. 8, the RAM access state machine250ofFIG. 9provides an arbitration between the multiple accesses to the memory236from the various state machines, based on a priority. The RAM access state machine250includes circuits for providing the highest priority to the transmit state machine246when access is requested of the memory236. The receive state machine224has the next highest priority, and then the backplane state machine256. The RAM access state machine250includes a transmit frame counter and a receive frame counter for maintaining an account of the amount of data temporarily stored in the respective sections of the memory236for transmission by the transmit framer240or a data bus interface270.

The data bus interface270is coupled by an 8-bit bus272to the RAM interface234. The data bus interface270includes a receive circuit coupled to a 4-bit receive bus274for sequentially receiving a first data nibble and a second data nibble and for combining the two nibbles into a byte of data. In like manner, the data bus interface270includes circuits for converting a byte of data from the bus272to two serial data nibbles for sequential transmission on the 4-bit transmit bus276. The buses274and276are each wired-OR type of buses, connected in common to the other similar gate array chips94of the optical channel shelf54. The 8-bit data bus interface270is controlled by a data bus state machine280which, in turn, communicates with the RAM access state machine250by way of signal and control lines282. The data bus state machine280includes circuits for preventing collisions on the transmit bus276with attempted simultaneous transmissions thereon by the other optical interface units94of the optical channel shelf54. The data bus state machine280controls the data bus interface270for the transporting of data in accordance with the state diagram ofFIG. 10.

The backplane state machine256includes circuits for controlling a backplane interface284by way of signal and control lines286. The backplane interface284includes a bidirectional 8-bit bus288coupled to the RAM interface234for transporting PCM data therebetween. The backplane interface284includes a receive serial PCM line290and a serial PCM transmit line292, and includes circuits for converting parallel data from the bus288to serial data for transmission on the line292. The interface284also includes serial-to-parallel converters for converting the serial data received on bus290, to corresponding parallel data for transport on bus288. The backplane interface284also includes the standard circuits for detecting framing of the signals. Connected to the backplane interface284is also a CUDL bus294a data link and alarm bus296and a system clock line298. These buses and lines connected to the backplane interface284are coupled to conventional common equipment for transmitting the PCM and other data to the central office20. In like manner, the DS1 interface230is also coupled to the common equipment for transport of the DS1 data to the central office20.

It should be noted from the foregoing that the gate array chip94operates in a synchronous manner, in that the input and output data rates are substantially the same, e.g., operating at 12.353 MHz. To that end, a common clock signal synchronizes all of the state machines for synchronous operation.

FIG. 10illustrates the 4-bit bus interconnections between each of the eight optical interface units94and the optical maintenance unit62. With regard to the 4-bit bus274, eight bits can be transferred from the optical maintenance unit62to each optical interface unit94. Four bits are first transferred in a 320 nanosecond logical high portion of the cycle, and the remaining four bits of a byte are transferred in the 320 nanosecond low going portion of the bus cycle. The most significant bits of the byte are transferred on the logic high portion and the least significant bits are transmitted on the logical low portion of the cycle. Thus, in one bus cycle of 640 nanoseconds in length, a total of eight bits are transferred from the optical maintenance unit62to each of the eight optical interface units94.

The 4-bit bus274operates in an identical bus cycle to transmit eight bits to the optical maintenance unit62, with a most significant nibble transferred during one bus cycle, and the least significant nibble transferred in the remaining half of the bus cycle. While the 4-bit bus configuration is not by way of necessity, those skilled in the art may prefer to transmit eight bits, or one byte on a corresponding 8-bit bus.

Each optical interface unit94includes circuits for detecting and avoiding collisions due to the simultaneous attempt to use the 4-bit bus274. The optical maintenance unit62includes the same type of collision avoidance/detection circuits, as it shares the same bus274. Each data bus interface270(FIG. 9) not only includes a 4-bit driver for transmitting a nibble on the transmit bus274, but also includes in parallel therewith a 4-bit receiver so that it can sense the same bits that it transmits on the bus274. Moreover, a pair of 4-bit comparators are provided in each optical interface unit94to compare the transmitted data on bus274with the data received by the same chip on such bus. In this manner, each optical interface unit94can ascertain that the bits it transmitted on the bus are maintained at the respective logic high and logic low levels, and are not otherwise corrupted by the attempted use of the bus274by another optical interface unit or the optical maintenance unit62.

In the event that two optical interface units941and948(FIG. 10) attempt to simultaneously transmit data bits on the bus274, a collision will eventually occur in which one unit will attempt to drive one bit line of the 4-bit bus274low and the other unit will attempt to drive the same bit line of the bus274high. Due to the open collector and wired-OR nature of the bus274, the logic low will dominate and prevail over the logic high signal. The unit attempting to drive the bit line of the bus274high will sense that the line was actually driven low, whereupon the comparison between what the unit transmitted on the bus274will not match with what such unit sensed on the bus274. In this event, the unit will register an error. When an optical interface unit94registers an error due to a difference between what it transmitted and what it sensed, it will halt transmission for a random period of time before reattempting a subsequent transmission of the nibble.

The optical interface unit94that attempted to drive the line of the bus274with a logic low signal will not detect an error as it did indeed drive such line low and it sensed the logic low signal on the line of the bus274. Thus, only one optical unit may eventually prevail, and all other optical interface units94in contention for the bus274at the same time will detect an error and halt transmission thereof. It can be appreciated that in certain instances the various bits of nibbles transmitted by multiple units may coincide for a while, but eventually the bits will differ. This is because the MAC address of each Ethernet user is different, and the transmitted Ethernet data packet includes the user's MAC address. As noted above, all optical interface units941through948as well as the optical maintenance unit62, have such collision detection/avoidance circuits to provide a coordinated use of the bus274. The operation of the optical maintenance unit62in transmitting data on the 10-Base-T transmit line300and receiving data on the 10-Base-T receive line302will be described in more detail in connection with the function of such unit.

FIG. 11is a diagram of the operations of the data bus state machine280in communicating data between the bidirectional 8-bit bus272and the wired-OR 4-bit bus274. It should be noted that the data bus interface270includes a counter that counts the number of bytes received on the 4-bit data bus274. Other digital circuits responsive to start, escape and idle flags on the 4-bit bus274are also integrated into the data bus interface270. Moreover the various counters and detectors of the data bus interface270signal the data bus state machine280of the same. It is noted that an Ethernet start flag comprises a specified number and arrangement of bits according to the Ethernet protocol. An escape flag is also a specified length and arrangement of digital signals. Lastly, an idle flag is a series of all logic ones.

The diagram ofFIG. 11illustrates a number of states in which the data bus state machine280undergoes, depending upon the various bus flags detected. In state310, the data bus state machine280sets idle waiting for an idle flag. If an unescaped idle flag is detected on the 4-bit bus274by the data bus state machine280, it proceeds to the idle state312. From the idle state312, the data bus state machine280can proceed either to state314to receive the first 64 bytes of data on bus274, or to state316where, if the transmit frame counter is greater than unity, data is transmitted on bus274and such data is received on bus274. As noted above, because of the wired-OR nature of the 4-bit bus274, the data bus interface270can transmit a nibble on the bus274and at the same time sense the data on the bus274to determine if the data has been corrupted by the simultaneous use of another circuit sharing the bus274. With regard to state314, the data bus state machine280has detected a start flag signifying the start of an Ethernet frame of data. The state machine280receives the first 64 bytes of data and determines if an unescaped idle flag has been detected therein. If so, the state machine280proceeds from state314back to the wait state310. If, on the other hand, no unescaped idle flag has been detected in the first 64 bytes of data, it can be considered that the frame is not a runt frame, whereupon the state machine280proceeds to state318. When it is determined that the Ethernet frame is not a runt frame, a transmit frame counter is incremented to thereby indicate that the memory236has stored an Ethernet frame of data as received from the bus274, and such frame should be transported to the transmit framer240. In state318, the data bytes are passed from the data bus interface270, via the 8-bit bus272to the RAM interface234for storage in the memory236. Again, the storage of data bytes is under control of the RAM access state machine250. As soon as data bytes from a received frame are sequentially stored in the memory236, the RAM access state machine250also begins to read the memory236and transfer the bytes in a FIFO manner to the transmit framer240on bus244. As noted above, the RAM access state machine250polls the transmit state machine246periodically to ascertain whether to transmit data bytes to the transmit framer240. With this arrangement, the memory236does not store an entire frame of Ethernet data before commencement of the transporting thereof to the transmit framer240. Rather, the memory236functions as a first-in, first-out memory so that the transport of data can be commenced before the end of received frame has been detected. The data bus state machine280continues to receive data bytes of the Ethernet frame until an unescaped idle flag is detected. When an unescaped idle flag is detected, the data bus state machine280returns from state318to state312to detect a start flag of a subsequent frame.

Returning now to the send and receive state316, the data bus state machine280controls the data bus interface270to transmit bytes and receive bytes at the same time. If, during the attempted transmission of a data nibble on bus274, a collision of data occurs, processing proceeds from state316to state314where transmission is interrupted and the data bus interface270continues to receive nibbles on the bus274. The collision of simultaneous data transmissions on bus274is detected in the manner described above in connection withFIG. 10. To reiterate, if two or more optical interface units94attempt to simultaneously transmit on the 4-bit bus274, each unit will sense and compare what it actually transmitted on the bus versus the logic states that were carried by the bus to determine if a match therebetween exists. In view that a logic low dominates over a logic high on the wired-OR bus274, only one optical interface unit94will eventually prevail, it being the one that drove the bus with a logic low when the contending unit attempted to drive the bus with a logic high. The optical interface unit94that dominated the bus274continues to transmit thereon, and the other contending units halt transmission for a random period of time before re-attempting to transmit a nibble on the bus274.

In the event no collision is detected while the data bus state machine280is in state316, and if 64 bytes have been received on the receive nibble bus274, processing proceeds to state320where the data bus state machine280continues sending data on nibble bus274and continues receiving on nibble bus274. In state320, the data bus state machine280controls the data bus interface270to continue a transmitting nibbles on the bus274until an end of frame has been detected. When an end of frame has been detected, the data bus state machine280returns to state312. It is also noted that when the receive framer220receives PCM and PC data bytes, the same is transferred and temporarily stored via the RAM interface234in the memory236. However, in order to reduce time delays in the optical interface unit94, retransmission of the received bytes that are stored in the memory236can commence via the data bus interface270before the entire frame has been stored in the memory236.

In the preferred embodiment of the optical interface unit94, data packets received by the receive framer220are temporarily stored and retransmitted on the nibble bus274via the data bus interface270. However, the RAM access state machine250could be configured or designed to provide a retransmission of the data packets back over the fiber optical line58via the transmit framer240. With this configuration, the data transmission route undergoes a U-turn, to be redirected toward the origin. The U-turn of data may facilitate testing or other functions. In addition, the RAM access state machine250could be configured to retransmit data to both the data bus interface270and the transmit framer240to provide a parallel branching of the same data.

It can be seen from the foregoing that neither gate array chip100or94decodes the Ethernet frames to process the various fields thereof or to change the data in the fields, as does an Ethernet bridge. Rather, the Ethernet data frames are merely temporarily stored and transported to a destination. It is also noted that neither gate array chip94or100requires any minimum round trip timing or maximum bus length, as does the Ethernet equipment. Rather, the collision detection/avoidance technique of the invention merely buffers the data until a retransmission thereof is possible. Also, while two levels of optical interface units90and94are provided in the preferred embodiment, fewer or more levels can be utilized with the attendant advantages.

FIG. 12illustrates a detail block diagram of the optical maintenance unit62. As noted inFIG. 5, the optical maintenance unit62is coupled to each of the eight optical interface units94by way of the 4-bit bus274. The function of the optical maintenance unit62is to provide a coordinated transfer of PC data packets between each of the eight optical interface units94and the fast Ethernet switch66.

The optical maintenance unit62includes a data bus interface310for providing an interface to the 4-bit nibble bus274. To that end, the data bus interface310includes circuits very similar to that of the data bus interface270shown inFIG. 9. The function of the data bus interface310is to provide collision detection/avoidance with regard to the nibble bus274, and to combine two data nibbles from the nibble bus274and provide a full byte of data on the bidirectional data bus312. Also, the data bus interface310includes circuits for converting a byte of data received from the bus312to a most significant nibble and a least significant nibble for transport on the nibble bus274. Like many of the other interfaces in the optical interface unit94, the data bus interface310includes circuits for detecting idle, escape and start flags to signal to a data bus state machine314where it is in the processing of a Ethernet data packet. The interface310has a counter that counts the number of bytes either transmitted or received to provide detection for runt frames and frames having a number of bytes that exceed the Ethernet protocol. The signaling between the data bus interface310and the data bus state machine314is carried out on lines connected therebetween. The data bus state machine314provides the same type of collision detection/avoidance function on the nibble bus274, as described above in connection with the optical interface units94ofFIG. 10. The data bus state machine314includes control circuits that are responsive to the start flags, end of frame flags, escape flags and idle flags, and signals the RAM access state machine316of the same on signal and control lines318. The RAM access state machine316operates in conjunction with a RAM interface320and an SRAM322for providing the temporary storage of transmit data in one 32 K×8 memory section and receive data in another 32 K×8 memory section.

A 10-Base-T interface324provides an interface to 10-Base-T transmit and receive lines64. Associated with the 10-Base-T interface324is a 10-Base-T state machine326. The 10-Base-T interface324is coupled to the RAM interface320by a bidirectional 8-bit bus328. The 10-Base-T state machine326also communicates with the RAM access state machine316by signal and control lines330. It should be noted that the RAM access state machine316, the RAM interface320, the memory322, the 10-Base-T interface324and the 10-Base-T state machine326operate in a manner identical to the corresponding circuits of the gate array chip100shown inFIG. 8. Stated another way, the transfer of data between 10-Base-T transmit and receive lines102with respect to the optical network unit receive framer170and transmit framer178(FIG. 8), is carried out in a manner similar to the operation of the circuit ofFIG. 12which communicates PC packet data between the 10-Base-T lines64and the data bus interface310. Insofar as the circuits for interfacing with the 10-Base-T lines64and the storage of data in the memory322are similar to those noted above in connection withFIG. 8, the description hereof need not be encumbered with repetitive discussions.

With reference again toFIGS. 5 and 12, it is noted that the optical maintenance unit62is coupled by the transmit and receive 10-Base-T lines64to the fast Ethernet switch66. The Ethernet switch66is of conventional design and readily available for combining a number of lines64together for multiplexing and transmission thereof on a 100-Base-FX high speed line45. The PC data packets carried back and forth on the high speed line45are transported to the internet backbone either directly, or indirectly through a central office. In accordance with an important feature of the invention, the PC data packets are not switched via the central office switching fabric and thus do not compete with subscriber telephone conversations for switching fabric connections.

As noted above, it is not necessary that the distributed hub feature of the invention utilize a fiber optic line58to extend the operation of an Ethernet hub.FIG. 13illustrates the distributed hub feature of the invention employing a master circuit350and a slave circuit352connected by a DS1 digital carrier line354. It is significant to note that the DS1 line354may extend for hundreds of miles by way of central offices to thereby network data packets between the master circuit350and the slave circuit352. In practice, the DS1 line354comprises a transmit DS1 line and a receive DS1 line for providing bidirectional networking of data packets between the master350and the slave352. With this arrangement, the distributed hub function can be utilized to carry Ethernet or other types of data packets over distances well beyond that which can be accommodated by a traditional Ethernet LAN.

When in a transmitting mode, the master350or the slave352can receive plural 10-Base-T inputs, multiplex the data packets on the DS1 line354, and transport the same to the destination. At the destination, the data packets are demultiplexed and distributed to the appropriate output. As can be appreciated, the DS1 line354would typically pass through one or more central offices or other types of switching systems. The master350and the slave352would each include programmable logic arrays or gate arrays similar to that described above. In a typical data pack transmission, from the master350to the slave352, the slave352receives the data packet as if the data packed were transmitted in the immediate vicinity of the slave computer. In like manner, when the slave352transmits a data packet to the master computer350, the packet is received by the master350as if the MAC address of the slave were located in the vicinity of the master350. The area of coverage is thus significantly extended to many hundreds of miles.

While the present invention has been described above in connection with the various embodiments, it is understood that the present disclosure has been made by way of example, as any changes in detail or structure may be made to the invention without departing from the spirit and scope of the invention as defined by the appended claims.