Memory package including a memory chip and a memory controller

A memory package includes a package substrate including power wiring and ground wiring. The memory package also includes a memory controller disposed over an upper surface of the package substrate and electrically connected to the power wiring and the ground wiring. The memory package further includes a memory chip disposed over the memory controller and electrically connected to the power wiring and the ground wiring. The memory package additionally includes a band pass filter disposed at one side of the memory controller over the upper surface of the package substrate and including an inductor and a capacitor which are connected in series. The inductor and the capacitor connected in series are electrically connected between the power wiring and the ground wiring.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0050620 filed on Apr. 27, 2020, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

This patent document relates to a memory package, and more particularly, to a memory package including a memory chip and a memory controller.

2. Related Art

Electromagnetic interference refers to a phenomenon in which a high-frequency noise generated from an electronic circuit or system affects adjacent circuits, systems, or a human body. One method of blocking or attenuating the electromagnetic interference phenomenon is blocking or attenuating power noise.

SUMMARY

In an embodiment, a memory package may include: a package substrate including power wiring and ground wiring; a memory controller disposed over an upper surface of the package substrate and electrically connected to the power wiring and the ground wiring; a memory chip disposed over the memory controller and electrically connected to the power wiring and the ground wiring; and a band pass filter disposed at one side of the memory controller over the upper surface of the package substrate and including an inductor and a capacitor which are connected in series, wherein one of one electrode of the inductor and one electrode of the capacitor is electrically connected to the power wiring, and an other of the one electrode of the inductor and the one electrode of the capacitor is electrically connected to the ground wiring.

In another embodiment, a memory package may include: a package substrate including power wiring and ground wiring; a memory controller disposed over an upper surface of the package substrate and electrically connected to the power wiring and the ground wiring; a memory chip disposed over the memory controller and electrically connected to the power wiring and the ground wiring; and a band pass filter disposed at one side of the memory controller over the upper surface of the package substrate and including an inductor and a capacitor which are connected in series. The inductor and the capacitor connected in series are electrically connected between the power wiring and the ground wiring.

DETAILED DESCRIPTION

Hereinafter, various embodiments of the disclosure are described in detail with reference to the accompanying drawings.

The drawings might not be necessarily to scale, and in some instances, proportions of at least some structures appearing in the drawings may have been exaggerated in order to clearly illustrate certain features of the described embodiments or implementations. In presenting a specific embodiments in a drawing or description having two or more layers in a multi-layer structure, the relative positioning relationship of such layers or the sequence of arranging the layers as shown reflects a particular implementation for the described or illustrated embodiment and a different relative positioning relationship or sequence of arranging the layers may be possible. In addition, a described or illustrated embodiment of a multi-layer structure might not reflect all layers present in that particular multilayer structure (e.g., one or more additional layers may be present between two illustrated layers). As a specific example, when a first layer in a described or illustrated multi-layer structure is referred to as being “on” or “over” a second layer or “on” or “over” a substrate, the first layer may be directly formed on the second layer or the substrate but may also represent a structure where one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

FIG. 1is a circuit diagram illustrating a circuit corresponding to a memory package according to an embodiment of the present disclosure.

Referring toFIG. 1, the memory package may include a memory chip120, a memory controller110electrically connected to the memory chip120and controlling the memory chip120, and a band pass filter130connected to an electrical connection path between the memory chip120and the memory controller110.

The memory chip120may include a memory cell array122and a signal input/output circuit124. The memory cell array122may store data. The signal input/output circuit124may transmit signals, such as data, between the memory controller110and the memory cell array122.

The memory cell array122may function to store data corresponding to a data signal transmitted from the signal input/output circuit124. The memory cell array122may include non-volatile memory. For example, the memory cell array122may include NAND memory. However, the present disclosure is not limited thereto. The memory cell array122may include non-volatile memory, such as phase-change random-access memory (PRAM), magneto-resistive random-access memory (MRAM), and the like. The memory cell array122may include volatile memory, such as dynamic random-access memory (DRAM), static random-access memory (SRAM), and the like. The memory cell array122may also include a combination of volatile and non-volatile memory.

The signal input/output circuit124may be connected to a signal path142that electrically connects the memory controller110and the signal input/output circuit124. The signal input/output circuit124may receive a signal from the memory controller110or output a signal to the memory controller110. Also, the signal input/output circuit124may be connected between a power path144and a ground path146to receive a power voltage such as VCCQ and a ground voltage such as VSSM. The signal input/output circuit124may operate using these voltages.

The memory controller110and the memory chip120may TO share the power voltage and ground voltage. For this reason, the memory controller110may be also connected between the power path144and the ground path146, and receive a power voltage and a ground voltage, which are equal to the power voltage and the ground voltage supplied to the memory chip120, respectively, from an outside. The memory controller110may operate using these voltages.

The power supplied during the operation of the memory controller110and the signal input/output circuit124may be preferably in a static state. However, in actual operations, power noise may be generated, and such noise may generate a high impedance in an operating frequency band and a harmonic frequency band of the memory controller110and/or the signal input/output circuit124. This impedance may induce charges to accumulate in conducting wires, and thus electromagnetic waves are emitted. This may cause problems such as electromagnetic interference. Therefore, the impedance may be lowered by blocking the power noise in a specific frequency band. In this embodiment, to satisfy this requirement, the band pass filter130may be additionally connected between the power path144and the ground path146.

The band pass filter130may mean a filter that selectively passes only a frequency of a specific band and blocks/attenuates the rest. The band pass filter130may include an inductor132and a capacitor134connected in series. In other words, the band pass filter130may be an LC filter. The inductor132may have a characteristic of suppressing a high frequency, and the capacitor134may have a characteristic of passing the high frequency. Accordingly, when the inductor132and the capacitor134are connected in series, a frequency can be selectively passed or blocked. As a result, it may be possible to block/attenuate the power noise in a specific frequency band, thereby shielding EMI. In the present disclosure, one end of the inductor132is connected to the power path144and one end of the capacitor134is connected to the ground path146. However, the positions of the inductor132and the capacitor134may be reversed.

Meanwhile, in the band pass filter130of the present embodiment, the capacitor134may also function as a decoupling capacitor for preventing insufficient power supply generated during the operation of the memory controller110. For this reason, the capacitor134and the band pass filter130including the same may be placed adjacent to the memory controller110. For example, the capacitor134and the band pass filter130including the same may be disposed closer to the memory controller110than the memory chip120in each of the power path144and the ground path146.

According to the above-described circuit, the band pass filter130may have an effect of shielding EMI by blocking/attenuating the noise of the power supplied during the operation of the memory chip120and the memory controller110.

In addition, the capacitor134included in the band pass filter130may be used to prevent a power shortage generated during the operation of the memory controller110.

Further, the power noise may adversely affect the signal transmission between the memory chip120and the memory controller110. When the power noise is blocked/attenuated as described above, the integrity of the signals transmitted between the memory chip120and the memory controller110may be secured.

Hereinafter, a memory package in which the circuit ofFIG. 1is implemented will be described with reference toFIGS. 2 to 5.

FIG. 2is a plan view illustrating a memory package according to an embodiment of the present disclosure,FIG. 3is a cross-sectional view taken along a line A1-A1′ ofFIG. 2,FIG. 4is a cross-sectional view taken along a line A2-A2′ ofFIG. 2, andFIG. 5is a cross-sectional view taken along a line A3-A3′ ofFIG. 2.

Referring toFIGS. 2 to 5, the memory package may include a package substrate100, a memory controller110and a band pass filter130formed over an upper surface of the package substrate100, a memory chip120formed over the memory controller110, and an external connection terminal150formed over a lower surface of the package substrate100.

The package substrate100may have a multilayer wiring structure for transmitting electrical signals. As an example, the package substrate100may be a printed circuit board (PCB). The multilayer wiring structure of the package substrate100will be described in detail after the memory controller110, the memory chip120, and the band pass filter130are first described.

The memory controller110may be disposed over the upper surface of the package substrate100. The memory controller110may include a plurality of connection terminals112,114, and116for connecting to the package substrate100and receiving power or signals from the package substrate100. Among the plurality of connection terminals112,114, and116, a terminal to which a signal is applied will be referred to as a signal terminal112, a terminal to which a power voltage is applied will be referred to as a power terminal114, and a terminal to which a ground voltage is applied will be referred to as a ground terminal116. In this embodiment, the connection terminals112,114, and116may be conductive bumps formed over a lower surface of the memory controller110, which faces the package substrate100. In addition, in this embodiment, the signal terminal112, the ground terminal116, and the power terminal114may be arranged at each of both side edges of the memory controller110in a first direction, while being arranged in a line along a second direction. However, the present disclosure is not limited thereto, and the shape, number, and arrangement of the connection terminals112,114, and116may be variously modified.

The memory chip120may be disposed over the memory controller110. The memory chip120may be directly attached to an upper surface of the memory controller110. Alternatively, the memory chip120may be attached to the upper surface of the memory controller110using an adhesive material (not shown). In this embodiment, the memory chip120may have a larger planar area than the memory controller110. Also, the memory chip120may be disposed such that a center of the memory chip120overlaps the memory controller110. However, the present disclosure is not limited thereto, and the planar area of the memory chip120or the overlapping portion with the memory controller110may be variously modified as long as the memory chip120is disposed over and overlaps the memory controller110.

A plurality of chip pads122,124, and126may be disposed over an upper surface of the memory chip120. The chip pads122,124, and126may be electrically connected to the package substrate100and receive power or a signal from the package substrate100. Among the plurality of chip pads122,124, and126, a chip pad to which a signal is applied will be referred to as a signal chip pad122, a chip pad to which a power voltage is applied will be referred to as a power chip pad124, and a chip pad to which a ground voltage is applied will be referred to as a ground chip pad126. In this embodiment, the chip pads122,124, and126may be arranged in a line at one edge of the memory chip120in the first direction. As an example, two signal chip pads122, one ground chip pad126, and one power chip pad124are shown. However, the present disclosure is not limited thereto, and the number, arrangement, and the like of the chip pads122,124, and126may be variously modified.

The chip pads122,124, and126may be electrically connected to a portion of the package substrate100, for example, a plurality of bonding pads102,104, and106disposed over the upper surface of the package substrate100, through bonding wires128. Among the plurality of bonding pads102,104, and106, a bonding pad to which a signal is applied will be referred to as a signal bonding pad102, a bonding pad to which a power voltage is applied will be referred to as a power bonding pad104, and a bonding pad to which a ground voltage is applied will be referred to as a ground bonding pad106. In this embodiment, the bonding pads102,104, and106may correspond to the chip pads122,124, and126, respectively. The bonding pads102,104, and106may be arranged in a line at one edge of the package substrate100in the first direction. As an example, two signal bonding pads102, one ground bonding pad106, and one power bonding pad104are shown. However, the present disclosure is not limited thereto, and the number, arrangement, and the like of the bonding pads102,104, and106may be variously modified.

The bonding wire128may have both ends connected to the signal chip pad122and the signal bonding pad102corresponding thereto, respectively, and electrically connect them. In addition, the bonding wire128may have both ends connected to the power chip pad124and the power bonding pad104corresponding thereto, respectively, and electrically connect them. In addition, the bonding wire128may have both ends connected to the ground chip pad126and the ground bonding pad106corresponding thereto, respectively, and electrically connect them.

Meanwhile, in order to easily connect the chip pads122,124, and126and the bonding pads102,104, and106using the bonding wire128, the memory chip120may be preferably disposed to expose the bonding pads102,104, and106disposed at the one edge of the package substrate100in the first direction. As an example, the memory chip120may have a smaller planar area than the package substrate100and be disposed to overlap a center of the package substrate100.

The band pass filter130may include an inductor132and a capacitor134. The inductor132and the capacitor134may be disposed over the upper surface of the package substrate100. One of both electrodes of the inductor132and one of both electrodes of the capacitor134may be connected to the package substrate100, and receive power from the package substrate100. In this embodiment, a power voltage is applied to one electrode of the inductor132and a ground voltage is applied to one electrode of the capacitor134. However, vice versa may be possible. The other of the both electrodes of the inductor132and the other of the both electrodes of the capacitor134may be connected to the package substrate100, and electrically connected to each other through the package substrate100.

In this embodiment, the inductor132and the capacitor134may be disposed at the other side of the memory controller110in the first direction. The inductor132and the capacitor134may be spaced apart from the memory controller by a distance. In this case, the power connection terminal114and the ground connection terminal116disposed at the other edge of the memory controller110in the first direction may be connected to the inductor132and the capacitor134, respectively, and thus, a distance between the power connection terminal114and the inductor132and/or between the ground connection terminal116and the capacitor134may be reduced as much as possible. As described above, when the electrical connection path between the capacitor134and the memory controller110decreases, a shortage of power generated during the operation of the memory controller110may be more readily solved by the capacitor134. However, the present disclosure is not limited thereto, and the arrangement and positions of the inductor132and the capacitor134may be variously modified.

In addition, in this embodiment, the inductor132and the capacitor134may be disposed at the other edge of the package substrate100in the first direction, so as not to overlap the memory chip120. However, the present disclosure is not limited thereto, and at least a portion of the inductor132and/or at least a portion of the capacitor134may overlap the memory chip120. That is, at least a portion of the inductor132and/or at least a portion of the capacitor134may be disposed in a space between the memory chip120and the package substrate100.

The package substrate100may have a multilayer wiring structure. In this embodiment, the package substrate100may include four layers L1, L2, L3, and L4at which horizontal wirings are formed. For convenience of description, the four layers L1, L2, L3, and L4will be referred to as a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4, respectively, according to a distance from the upper surface of the package substrate100. In addition, the horizontal wirings formed at the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4, respectively, will be referred to as a first horizontal wiring W1, a second horizontal wiring W2, a third horizontal wiring W3, and a fourth horizontal wiring W4. The upper or lower surface of the package substrate100and the horizontal wirings W1, W2, W3, and W4may be connected to each other through vertical wirings. Hereinafter, a vertical wiring connecting the upper surface of the package substrate100and the first horizontal wiring W1will be referred to as a first vertical wiring V1, a vertical wiring connecting the upper surface of the package substrate100and the second horizontal wiring W2will be referred to as a second vertical wiring V2, a vertical wiring connecting the upper surface of the package substrate100and the third horizontal wiring W3will be referred to as a third vertical wiring V3, and a vertical TO wiring connecting the upper surface of the package substrate100and the fourth horizontal wiring W4will be referred to as a fourth vertical wiring V4. In this embodiment, the third horizontal wiring W3and the fourth horizontal wiring W4may be used as power wiring that receives power from the outside. For this reason, a fifth vertical wiring V5may be formed to connect the third horizontal wiring W3and the lower surface of the package substrate100on which the external connection terminal150is disposed. In addition, a sixth vertical wiring V6may be formed to connect the fourth horizontal wiring W4and the lower surface of the package substrate100on which the external connection terminal150is disposed. The rest of the package substrate100, except for the horizontal wirings W1, W2, W3, and W4, and the vertical wirings V1, V2, V3, V4, V5, and V6, may include an insulating material.

Hereinafter, referring toFIGS. 2 and 3, a ground voltage transmission path in the package substrate100will be described. In this embodiment, the wirings used for transmitting the ground voltage may be the fourth horizontal wiring W4, and the fourth and sixth vertical wirings V4and V6connected thereto. However, the present disclosure is not limited thereto, and any one of the first to third horizontal wiring W1, W2, and W3, and the vertical wirings connected thereto may be used to transmit the ground voltage.

The fourth horizontal wiring W4may be electrically connected to the ground connection terminal116of the memory controller110, TO the ground bonding pad106over the upper surface of the package substrate100, and the one electrode of the inductor132. As an example, the ground connection terminal116may be electrically connected to the fourth horizontal wiring W4through the fourth vertical wiring V4that overlaps and directly connects to the ground connection terminal116. The ground bonding pad106may also be electrically connected to the fourth horizontal wiring W4through the fourth vertical wiring V4that overlaps and directly connects to the ground bonding pad106. On the other hand, the one electrode of the inductor132may be electrically connected to the fourth horizontal wiring W4through the first vertical wiring V1that overlaps and directly connects to the one electrode of the inductor132, the first horizontal wiring W1that connects to the first vertical wiring V1and extends to the fourth vertical wiring V4, and the fourth vertical wiring V4. However, the present disclosure is not limited thereto, the ground connection terminal116, the ground bonding pad106, and the one electrode of the inductor132may be electrically connected to the fourth vertical wiring V4, by an appropriate combination of the first to third vertical wirings V1, V2, and V3and the first to third horizontal wirings W1, W2, and W3.

Meanwhile, in this cross-sectional view, the external connection terminal150should not be visible, but for convenience of description, a ground external connection terminal156to which the ground voltage is applied, among the external connection terminals150, is illustrated together. The fourth horizontal wiring W4may be electrically connected to the ground external connection terminal156through the sixth vertical wiring V6.

Accordingly, a ground voltage supply path that transmits the ground voltage to the ground connection terminal116and the ground bonding pad106through the ground external connection terminal156, the sixth vertical wiring V6, the fourth horizontal wiring W4, and the fourth vertical wiring V4, may be formed. In addition, a ground voltage supply path that transmits the ground voltage to the one electrode of the inductor132through the ground external connection terminal156, the sixth vertical wiring V6, the fourth horizontal wiring W4, the fourth vertical wiring V4, the first horizontal wiring W1, and the first vertical wiring V1, may be formed.

In a plan view, the above ground voltage supply path may have a line shape that is bent in various directions to interconnect the ground bonding pad106, the ground connection terminal116, the ground external connection terminal156, and the one electrode of the inductor132.

Next, referring toFIGS. 2 and 4, a power voltage transmission path in the package substrate100will be described. In this embodiment, the wirings used for transmitting the power voltage may be the third horizontal wiring W3, and the third and fifth vertical wirings V3and V5connected thereto. However, the present disclosure is not limited thereto, and any one of the first, second, and fourth horizontal wirings W1, W2, and W4, and vertical wirings connected thereto may be used to transmit the power voltage.

The third horizontal wiring W3may be electrically connected to the power connection terminal114of the memory controller110, the power bonding pad104over the upper surface of the package substrate100, and the one electrode of the capacitor134. As an example, the power connection terminal114may be electrically connected to the third horizontal wiring W3through the third vertical wiring V3that overlaps and directly connects to the power connection terminal114. The power bonding pad104may also be electrically connected to the third horizontal wiring W3through the third vertical wiring V3that overlaps and directly connects to the power bonding pad104. On the other hand, the one electrode of the capacitor134may be electrically connected to the third horizontal wiring W3through the first vertical wiring V1that overlaps and directly connects to the one electrode of the capacitor134, the first horizontal wiring W1that is connected to the first vertical wiring V1and extends to the third vertical wiring V3, and the third vertical wiring V3. However, the present disclosure is not limited thereto, and the power connection terminal114, the power bonding pad104, and the one electrode of the capacitor134may be electrically connected to the third vertical wiring V3by an appropriate combination of the first and second vertical wirings V1and V2, and the first and second horizontal wirings W1and W2.

Meanwhile, in this cross-sectional view, the external connection terminal150should not be seen, but for convenience of description, a power external connection terminal154to which the power voltage is applied, among the external connection terminals150, is illustrated together. The third horizontal wiring W3may be electrically connected to the power external connection terminal154through the fifth vertical wiring V5.

Accordingly, a power voltage supply path for transmitting the power voltage to the power connection terminal114and the power bonding pad104through the power external connection terminal154, the fifth vertical wiring V5, the third horizontal wiring W3, and the third vertical wiring V3, may be formed. In addition, a power voltage supply path for transmitting the power voltage to the one electrode of the capacitor134through the power external connection terminal154, the fifth vertical wiring V5, the third horizontal wiring W3, the third vertical wiring V3, the first horizontal wiring W1, and the first vertical wiring V1, may be formed.

In a plan view, the above power voltage supply path may have a line shape that is bent in various directions to interconnect the power bonding pad104, the power connection terminal114, the power external connection terminal154, and the one electrode of the capacitor134. In addition, the power voltage supply path may be spaced apart and separated from the ground voltage supply path described above.

Next, referring toFIGS. 2, 3, and 4, a connection path between the inductor132and the capacitor134in the package substrate100will be described. In this embodiment, the wirings used to connect the inductor132and the capacitor134may be the first horizontal wiring W1and the first vertical wiring V1connected thereto. However, the present disclosure is not limited thereto, and any one of the second to fourth horizontal wirings W2, W3, and W4, and vertical wirings connected thereto may be used to connect the inductor132and the capacitor134.

The first horizontal wiring W1may be electrically connected to the other electrode of the inductor132and the other electrode of the capacitor134through the first vertical wiring V1that overlaps and directly connects to each of the other electrode of the inductor132and the other electrode of the capacitor134. Because the first vertical wiring V1and the first horizontal wiring W1only serve to connect the inductor132and the capacitor134, there is no need to connect to the external connection terminal150, or the like.

Next, referring toFIGS. 2 and 5, a signal transmission path in the package substrate100will be described. In this embodiment, the wirings used to transmit signals between the memory controller110and the memory chip120may be the second horizontal wiring W2and the second vertical wiring V2connected thereto. However, the present disclosure is not limited thereto, and any one of the first, third, and fourth horizontal wirings W1, W3, and W4, and vertical wirings connected thereto may be used to transmit the signals.

The second horizontal wiring W2may be electrically connected to the signal connection terminal112of the memory controller110and the signal bonding pad102over the upper surface of the package substrate100. As an example, the signal connection terminal112may be electrically connected to the second horizontal wiring W2through the second vertical wiring V2that overlaps and directly connects to the signal connection terminal112. The signal bonding pad102may also be electrically connected to the second horizontal wiring W2through the second vertical wiring V2that overlaps and directly connects to the signal bonding pad102. However, the present disclosure is not limited thereto, and the signal connection terminal112and the signal bonding pad102may be electrically connected to the second vertical wiring V2by an appropriate combination of the first vertical wiring V1and the first horizontal wiring W1. Because the second vertical wiring V2and the second horizontal wiring W2only serve to connect the memory chip120and the memory controller110, there is no need to connect to the external connection terminal150, or the like.

According to the memory package described above, because the circuit ofFIG. 1is implemented, all effects obtained by the circuit ofFIG. 1can be obtained.

In addition, because the path connecting the inductor132and the capacitor134in the package substrate100is shortest by using the first horizontal wiring W1and the first vertical wiring V1, an electrical connection thereof may be implemented smoothly.

In addition, because the path connecting the memory chip120and the memory controller110in the package substrate100is next shortest by using the second horizontal wiring W2and the second vertical wiring V2, it may be possible to smoothly exchange signals between them.

Further, instead of directly connecting the one electrode of the inductor132and the one electrode of the capacitor134with the third and fourth vertical wirings V3and V4, the one electrode of the inductor132and the one electrode of the capacitor134may be connected to the third and fourth vertical wirings V3and V4via the first vertical wiring V1and the first horizontal wiring W1. The first horizontal wiring W1connected to the one electrode of the inductor132may extend to the fourth vertical wiring V4that is connected to the ground connection terminal116of the memory controller110, The first horizontal wiring W1connected to the one electrode of the capacitor134may extend to the third vertical wiring V3that is connected to the power connection terminal114of the memory controller110. In this case, the distance between the memory controller110and the inductor132and the electrical connection path between the memory controller110and the capacitor134may be reduced. As a result, the decoupling capacitor function of the capacitor134can be improved.

FIG. 6is a diagram illustrating an effect of the memory package according to the present embodiment. InFIG. 6, a first case (case1) represents a case in which only a capacitor is formed between the memory controller110and the memory chip120, and a second case (case2) represents a case in which the band pass filter130including the inductor132and the capacitor134which are connected in series is formed between the memory controller110and the memory chip120.

Referring toFIG. 6, it can be seen that the impedance of the second case is reduced by reducing power noise in a specific frequency band, for example, a Wi-Fi band, compared to the first case.

FIG. 7Ais a diagram illustrating another effect of the memory package of the present embodiment, andFIG. 7Bis a diagram for comparison withFIG. 7A.FIG. 7Ashows a field strength indicating the degree of electromagnetic wave generation when the band pass filter130including the inductor132and the capacitor134which are connected in series is formed between the memory controller110and the memory chip120.FIG. 7Bis shows a field strength when only a capacitor is formed between the memory controller110and the memory chip120.

Referring toFIG. 7A, it can be seen that the field strength is significantly reduced, compared toFIG. 7B. As a result, it can be seen that the degree of electromagnetic wave generation is reduced according to the memory package of this embodiment.

According to the embodiments of the disclosure, a memory package is provided which can shield the electromagnetic interference and ensure signal integrity by blocking/attenuating the power noise.

FIG. 8shows a block diagram illustrating an electronic system including a memory card7800employing at least one of the semiconductor packages according to the embodiments. The memory card7800includes a memory7810, such as a nonvolatile memory device, and a memory controller7820. The memory7810and the memory controller7820may store data or read out the stored data. At least one of the memory7810and the memory controller7820may include at least one of the semiconductor packages according to described embodiments.

The memory7810may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller7820may control the memory7810such that stored data is read out or data is stored in response to a read/write request from a host7830.

FIG. 9shows a block diagram illustrating an electronic system8710including at least one of the semiconductor packages according to described embodiments. The electronic system8710may include a controller8711, an input/output device8712, and a memory8713. The controller8711, the input/output device8712, and the memory8713may be coupled with one another through a bus8715providing a path through which data move.

In an embodiment, the controller8711may include one or more microprocessor, digital signal processor, microcontroller, and/or logic device capable of performing the same functions as these components. The controller8711or the memory8713may include one or more of the semiconductor packages according to the embodiments of the present disclosure. The input/output device8712may include at least one selected among a keypad, a keyboard, a display device, a touchscreen and so forth. The memory8713is a device for storing data. The memory8713may store data and/or commands to be executed by the controller8711, and the like.

The memory8713may include a volatile memory device such as a DRAM and/or a nonvolatile memory device such as a flash memory. For example, a flash memory may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system8710may stably store a large amount of data in a flash memory system.

The electronic system8710may further include an interface8714configured to transmit and receive data to and from a communication network. The interface8714may be a wired or wireless type. For example, the interface8714may include an antenna or a wired or wireless transceiver.

The electronic system8710may be realized as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.

If the electronic system8710represents equipment capable of performing wireless communication, the electronic system8710may be used in a communication system using a technique of CDMA (code division multiple access), GSM (global system for mobile communications), NADC (north American digital cellular), E-TDMA (enhanced-time division multiple access), WCDMA (wideband code division multiple access), CDMA2000, LTE (long term evolution), or Wibro (wireless broadband Internet).

Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure as defined in the following claims.