Semiconductor device with integrated resistive element and method of making

A resistive device (44) and a transistor (42) are formed. Each uses a portion of a metal layer (18) that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer (34) overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.

BACKGROUND

This disclosure relates generally to semiconductor devices, and more specifically, to semiconductor devices with integrated resistive elements and methods of making the same.

2. Related Art

As device dimensions shrink, high dielectric constant (high-k or hi-k) materials are being considered for use as the gate dielectric for devices operating at the lowest voltages in a corresponding integrated circuit, henceforth referred to as core devices. However, problems exist if a high-k material, such as HfO2(hafnium oxide), is used for high voltage devices, such as an intermediate thickness gate oxide devices (henceforth known as TGO devices), a thicker gate oxide devices (henceforth known as DGO devices), or capacitors on the integrated circuit. For example, if HfO2is formed over SiO2(silicon dioxide), the Hf (hafnium) and Hf-induced defects may diffuse into the SiO2during manufacturing. The diffusion will cause poor reliability, especially in high voltage applications. In addition, using a high-k material changes the work function of the device. When the work function changes, the technology associated with the device must be typically altered, which consumes time and resources by having to develop new technology. Furthermore, it is unknown if any effects due to interaction between the high-k material and other materials at the edge of a patterned gate are created when using HfO2in a high voltage device.

Integrated circuit passive devices traditionally include polysilicon resistors. One example of forming a polysilicon resistor includes doping polysilicon to control its resistance. As indicated herein above, as integrated circuit device dimensions shrink, transistor devices are migrating to high-K dielectrics and metal gate transistors. However, added complexities and increased manufacturing costs are incurred with respect to the formation of polysilicon passive devices with the high-K dielectric and metal gate transistor devices. In other words, the traditional approaches in the formation of polysilicon passive devices are no longer suitable for use with high-K dielectric and metal gate transistor technology.

Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.

DETAILED DESCRIPTION

As mentioned herein above, with the advancement of technology towards smaller and smaller devices, metal gate and high-k transistors are replacing poly-Si and silicon oxy-nitride transistors. The use of metal gate electrodes is incompatible with the traditional method of forming polysilicon resistors. In conventional polysilicon technology, a 1000 Angstrom P-Poly has a resistivity on the order of 540 ohm/sq. With metal gate/high-k technologies a metal layer is typically underneath the polysilicon and above the high-k gate dielectric. It has been found that the low resistivity metal of a metal gate layer is dominant in determining a resistance of the passive device, when the passive device has been formed with polysilicon overlying the low resistivity metal. Since metal used within a metal gate stack of a transistor has low resistivity, the same metal cannot be used for a passive device with high resistance in a circuit application on the same integrated circuit, absent the embodiments of the present disclosure. For example, in metal gate technology, a 200 Angstrom TaC metal gate metal has a resistivity on the order of 70 ohm/sq. A passive element comprising a 1000 Angstrom P-Poly (540 ohm/sq) formed overlying a 100 Angstrom TaC (140 ohm/sq) provides a cumulative resistivity on the order of 111 ohm/sq.

The embodiments of the present disclosure advantageously overcome such a limitation by providing a passive device with high resistance, as discussed further herein. The embodiments include selectively treating a portion of a metal gate metal to obtain a high resistance material, wherein the high resistance material is used for forming the passive resistive element with desired high resistivity. In one embodiment, by selectively increasing a percentage of oxygen in the metal gate metal, the resistivity of the metal can be increased by an amount on the order of five to ten times (5-10×). For example, an untreated 100 Angstrom TaC having a resistivity of 140 ohm/sq can be treated, as discussed herein, to produce an increased oxygen concentration in the metal layer, and thereby resulting in a change in resistivity to a value on the order of approximately 700 to 1400 ohm/sq.

A semiconductor substrate as described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.

FIG. 1is a cross-sectional view of a portion of a substrate in the process of making a semiconductor device10with an integrated resistive element according to one embodiment of the present disclosure. The making of semiconductor device10begins with the providing of a substrate12, the forming of shallow trench isolation (STI) region14, and the formation of an active area well region16, using any suitable well known techniques. In the illustration, substrate12includes a P-type substrate, shallow trench isolation region14includes a field oxide, and active area well region16includes an N-type well region. A high-K dielectric layer18is formed overlying the shallow trench isolation region14and the active area well region16, using any suitable well known techniques. The characteristics of the substrate12, isolation region14, active area well region16, and high-K dielectric layer18are selected according to the requirements of the particular semiconductor device and integrated circuit application.

FIG. 2is a cross-sectional view of a portion of the substrate ofFIG. 1during a further stage in the process of making a semiconductor device10with an integrated resistive element according to one embodiment of the present disclosure. A gate metal layer20, having a given resistivity of x ohm-cm, is formed overlying the high-K dielectric layer18. The gate metal layer20is formed to include desired characteristics (i.e., composition, thickness, etc.) that are selected according to the requirements of the particular semiconductor device application. In one embodiment, gate metal layer20comprises PVD TaC. Subsequent to the formation of gate metal layer20, a patterned photoresist22is formed. The patterned photoresist22overlies a region of the substrate that includes the active area well region16, as well as, a portion of the STI region14. In particular, a lateral edge24of the patterned photoresist22extends over a portion of the STI region14by a desired amount of overlap, for example, as indicated by reference numeral26inFIG. 2. The amount of overlap is at least an amount sufficient, such that during a subsequent increased resistivity processing of the metal layer20, the active area well region16is protected from such processing.

Subsequent to the formation of patterned photoresist22, the substrate is further processed with an ion implantation of an implant species28that modifies the resistivity of the metal layer20in the region not protected by the patterned photoresist22. In other words, a first portion of the metal layer is selectively treated by implanting the first portion of the metal layer with an implant species that amorphizes the first portion of the metal layer. The implant species are selected from at least one of oxygen, xenon, fluorine, nitrogen, carbon, silicon, phosphorus, sulfur, chlorine, argon or krypton. In one example, the ion implant can include an atomized or ionized oxygen implant of sufficient implantation characteristics to obtain a desired increase in resistivity of the treated portion of the metal layer. Modification of the resistivity of the metal layer20includes increasing the resistivity from a first resistivity of x ohm-cm to a second resistivity of y ohm-cm, as designated by reference numeral32inFIG. 3. In addition, the ion implantation of the implant species28may also modify the high-K dielectric layer18in a region thereof not protected by the patterned photoresist22; however, such a modification to the high-K dielectric layer does not adversely affect the resistivity of the implanted portion32of the metal layer. The patterned photoresist22is then removed using suitable processing. In another embodiment, the method comprises selectively treating the first portion of the metal layer by implanting the first portion of the metal layer with an implant species that produces at least one of a changed phase or a secondary phase in the first portion of the metal layer. In a further embodiment, the method comprises selectively treating the first portion of the metal layer by adding an impurity element to the first portion of the metal layer, wherein the impurity element can include at least one of oxygen, xenon, fluorine, nitrogen, carbon, silicon, phosphorus, sulfur, chlorine, argon or krypton.

FIG. 3is a cross-sectional view of a portion of the substrate ofFIG. 2during a further stage in the process of making a semiconductor device with an integrated resistive element according to one embodiment of the present disclosure. The portion of metal layer20having a resistivity of x ohm-cm is separated from the post-processed portion32of the metal layer by an interface or boundary30. Subsequent to modifying the resistivity of the metal layer, a polycrystalline semiconductor material34is formed overlying the metal layer20and the post-processed portion32of the metal layer. The polycrystalline semiconductor material34is formed to include desired characteristics (i.e., composition, thickness, etc.) that are selected according to the requirements of the particular semiconductor device application. In one embodiment, the polycrystalline semiconductor material34includes polycrystalline silicon.

FIG. 4is a cross-sectional view of a portion of the substrate ofFIG. 3during a further stage in the process of making a semiconductor device with an integrated resistive element according to one embodiment of the present disclosure. A patterned photoresist36is formed overlying the polycrystalline semiconductor material34, wherein a portion38of the patterned photoresist36defines a gate dimension of a transistor device yet to be formed. In addition, a portion40of the patterned photoresist36defines one dimension of a passive element yet to be formed.

FIG. 5is a cross-sectional view of a portion of the substrate ofFIG. 4during a further stage in the process of making a semiconductor device with an integrated resistive element according to one embodiment of the present disclosure. In particular, the substrate ofFIG. 4with the patterned photoresist36is etched using a suitable etch process, such as, a plasma or other dry etch, followed by subsequent removal of the patterned photoresist36. As a result, gate stack42and resistive element stack44are formed.

FIG. 6is a cross-sectional view of a semiconductor device with an integrated resistive element formed by the process of making the same according to one embodiment of the present disclosure. Beginning with the portion of the substrate as shown inFIG. 5, processing continues with forming source and drain extension regions46and48within the active area well region16, and forming sidewall spacers which include sidewall spacers50on sidewalls of gate stack42and sidewall spacers52on sidewalls of the resistive element stack44. Subsequent to formation of the sidewall spacers, source and drain implant regions56and58are formed within the active area well region16using suitable S/D implants and anneals, according to the particular requirements of a given semiconductor device application.

In the illustration ofFIG. 6, the resistive element stack44includes a width dimension that extends from the left-hand side sidewall spacer52to the right-hand side sidewall spacer52. Resistive element stack44further includes a length dimension that extends into and out-of the page of the drawing, wherein the specific dimensions are selected according to the requirements of a given resistive element stack implementation. Subsequent to the formation of the source and drain regions, further processing includes forming silicided contact regions on both the gate stack42and on desired locations of the resistive element stack44. Locations of the silicided contact regions on the resistive element stack44are determined according to the needs of a given resistive element stack implementation.

FIG. 7is a cross-sectional view of a portion of the substrate ofFIG. 1during a further stage in the process of making a semiconductor device100with an integrated resistive element according to another embodiment of the present disclosure. Gate metal layer20, having a given resistivity of x ohm-cm, is formed overlying the high-K dielectric layer18. The gate metal layer20is formed to include desired characteristics (i.e., composition, thickness, etc.) that are selected according to the requirements of the particular semiconductor device application. In one embodiment, gate metal layer20comprises TaC. Subsequent to the formation of gate metal layer20, a patterned hardmask60is formed. The patterned hardmask60can include an oxide or nitride. Patterned hardmask60overlies a region of the substrate that includes the active area well region16, as well as, a portion of the STI region14. In particular, a lateral edge62of the patterned hardmask60extends over a portion of the STI region14by a desired amount of overlap, for example, as indicated by reference numeral64inFIG. 7. The amount of overlap is at least an amount sufficient, such that during a subsequent increased resistivity processing of the metal layer20, the active area well region16is protected from such processing.

Subsequent to the formation of patterned hardmask60, in one embodiment, the substrate is further processed with a resistivity modification treatment102that modifies the resistivity of the metal layer20in the region not protected by the patterned hardmask60. In one embodiment, the resistivity modification treatment102includes treating the corresponding portion of the metal layer by performing an anneal in a gaseous ambient that increases the resistivity of that portion of the metal layer. Modification of the resistivity of the metal layer20includes increasing the resistivity from a first resistivity of x ohm-cm to a second resistivity of y ohm-cm, as designated by reference numeral32inFIG. 3. In addition, the resistivity modification treatment102may also modify the high-K dielectric layer18in a region thereof not protected by the patterned hardmask60; however, such a modification to the high-K dielectric layer does not adversely affect the resistivity of the implanted portion32of the metal layer. Subsequent to the resistivity modification treatment, the patterned hardmask60is removed using suitable processing. The portion of the substrate illustrated inFIG. 7is then processed in a manner similar to that as discussed herein with reference toFIGS. 3-6.

FIG. 8is a cross-sectional view of a portion of the substrate ofFIG. 1during a further stage in the process of making a semiconductor device with an integrated resistive element according to yet another embodiment of the present disclosure. Gate metal layer20, having a given resistivity of x ohm-cm, is formed overlying the high-K dielectric layer18. The gate metal layer20is formed to include desired characteristics (i.e., composition, thickness, etc.) that are selected according to the requirements of the particular semiconductor device and integrated circuit application. In one embodiment, gate metal layer20comprises TaC. Subsequent to the formation of gate metal layer20, a polycrystalline semiconductor material112is formed overlying the metal layer20. The polycrystalline semiconductor material112is formed to include desired characteristics (i.e., composition, thickness, etc.) that are selected according to the requirements of the particular semiconductor device application. In one embodiment, the polycrystalline semiconductor material112includes polycrystalline silicon.

Subsequent to formation of polycrystalline semiconductor material112, a patterned photoresist114is formed. The patterned photoresist114overlies a region of the substrate that includes the active area well region16, as well as, a portion of the STI region14. In particular, a lateral edge116of the patterned photoresist114extends over a portion of the STI region14by a desired amount of overlap, for example, as indicated by reference numeral118inFIG. 2. The amount of overlap is at least an amount sufficient, such that during a subsequent increased resistivity processing of the metal layer20, the active area well region16is protected from such processing.

Subsequent to the formation of patterned photoresist114, in one embodiment, the substrate is further processed with an ion implantation of an implant species120that modifies the resistivity of the metal layer20in the region not protected by the patterned photoresist114. In one embodiment, the ion implant includes an oxygen implant of sufficient implantation characteristics to obtain a desired increase in resistivity of the treated portion of the metal layer. Modification of the resistivity of the metal layer20includes increasing the resistivity from a first resistivity of x ohm-cm to a second resistivity of z ohm-cm, as designated by reference numeral122inFIG. 9. In addition, the ion implantation of the implant species120may also modify the high-K dielectric layer18in a region thereof not protected by the patterned photoresist114; however, such a modification to the high-K dielectric layer does not adversely affect the resistivity of the implanted portion122of the metal layer. The patterned photoresist114is then removed using suitable processing.

FIG. 9is a cross-sectional view of a portion of the substrate ofFIG. 8during a further stage in the process of making a semiconductor device with an integrated resistive element according to the yet another embodiment of the present disclosure. As a result of the resistivity treatment discussed with respect toFIG. 8, the portion of metal layer20having a resistivity of x ohm-cm is separated from the post-processed portion122of the metal layer by an interface or boundary126. The portion of the substrate illustrated inFIG. 9is then processed in a manner similar to that as discussed herein with reference toFIGS. 4-6.

FIG. 10is a three-dimensional plan view of a portion of an integrated resistive element125according to one embodiment of the present disclosure, wherein the resistive element comprises a resistor. The resistive element125is formed with use of the passive device stack44ofFIG. 6and further includes first and second spaced apart silicide regions126and128, respectively. The passive device stack44ofFIG. 6is representative of a cross-section of element125, wherein one of the silicide regions is in front of the plane of the drawing and the other is behind the plane of the drawing. Referring back toFIG. 10, the effective resistance of the resistive element125is proportional to the composition of the passive device stack44and the spacing between the first silicide region126and the second silicide region128. The spacing between the first silicide region126and the second silicide region128is thus selected according to the make-up of the passive device stack44and the requirements of a particular integrated resistive element application. Subsequent to formation of the first and second silicide regions, terminals130and132are formed for providing electrical contact to the corresponding silicide regions. Terminals130and132comprise any suitable conductive material, wherein the conductive material is compatible for the given process flow used in the manufacture of the passive device stack and corresponding resistive element.

FIG. 11is a three-dimensional plan view of a portion of an integrated resistive element134according to another embodiment of the present disclosure, wherein the resistive element comprises a fuse. The resistive element134is formed with use of the passive device stack44ofFIG. 6and further includes first and second spaced apart silicide regions126and128, respectively. The passive device stack44ofFIG. 6is representative of a cross-section of element134, wherein one of the silicide regions is in front of the plane of the drawing and the other is behind the plane of the drawing. Referring back toFIG. 11, the fuse characteristics of the resistive element134are proportional to the composition of the passive device stack44and the spacing between the first silicide region126and the second silicide region128, in addition to a height and width dimensions of the polysilicon34of the passive device stack. The spacing between the first silicide region126and the second silicide region128, as well as height and width dimensions, are thus selected according to the make-up of the passive device stack44and the requirements of a particular integrated resistive element fuse application. Subsequent to formation of the first and second silicide regions, terminals130and132are formed for providing electrical contact to the corresponding silicide regions. Terminals130and132comprise any suitable conductive material, wherein the conductive material is compatible for the given process flow used in the manufacture of the passive device stack and for the resistive fuse element. In operation, responsive to a flow of current of a sufficient magnitude passing through the resistive fuse element, a portion of the passive device stack melts and creates a void. In other words, the current needs to be sufficient to create a void (i.e., create an open circuit between the first and second electrical terminals) and thus render the resistive fuse element non-conductive. The characteristics of the resistive fuse element are chosen according to the fuse requirements of the integrated circuit application for which the resistive fuse element is to be used.

By now it should be appreciated that there has been provided a number of implementations herein. According to one embodiment, the method comprises providing a semiconductor substrate and forming a metal layer overlying both a first portion of the semiconductor substrate and a second portion of the semiconductor substrate. The metal layer comprises a layer having a predetermined resistance. A first portion of the metal layer overlying the first portion of the semiconductor substrate is selectively treated to increase the predetermined resistance of the metal layer of the first portion while not increasing the resistance of a second portion of the metal layer different from the first portion. A polycrystalline semiconductor material layer is then formed overlying and in physical contact with the first portion of the metal layer. A passive resistive device is formed from the first portion of the metal layer and the polycrystalline semiconductor material layer overlying the first portion of the semiconductor substrate. In addition, a transistor is formed overlying the second portion of the semiconductor layer, wherein the second portion of the metal layer is used as a control electrode of the transistor. In one embodiment, the polycrystalline semiconductor material layer comprises a polysilicon layer.

In another embodiment, selectively treating the first portion of the metal layer is carried out by implanting the first portion of the metal layer with an implant species that amorphize the first portion of the metal layer. In a further embodiment, the method further comprises selectively treating the first portion of the metal layer by implanting the first portion of the metal layer with an implant species that produces at least one of a changed phase or a secondary phase in the first portion of the metal layer. In yet another embodiment, the method can comprise selectively treating the first portion of the metal layer by adding an impurity element to the first portion of the metal layer. In addition, the method further includes selecting at least one of oxygen, xenon, fluorine, nitrogen, carbon, silicon, phosphorus, sulfur, chlorine, argon or krypton as the impurity element or implant species.

In yet another embodiment, the method further comprises coupling first and second electrical terminals to the passive resistive device for receiving a fuse voltage for creating an open circuit between the first and second electrical terminals, the passive resistive device thereby functioning as a fuse.

In another embodiment, the method includes treating the first portion of the metal layer after forming the polycrystalline semiconductor material layer overlying the first portion of the metal layer. In a further embodiment, the method includes treating the first portion of the metal layer by performing an anneal in a gaseous ambient that increases the resistivity of the first portion of the metal layer.

In another embodiment, a method comprises providing a semiconductor substrate and forming a metal layer overlying both a first portion of the semiconductor substrate and a second portion of the semiconductor substrate, wherein the metal layer has a predetermined resistance. A first portion of the metal layer overlying the first portion of the semiconductor substrate is selectively treated to increase the predetermined resistance of the metal layer of the first portion while not increasing the resistance of a second portion of the metal layer different from the first portion. A resistive capping layer is formed overlying and in physical contact with the first portion of the metal layer, the resistive capping layer having a greater resistance than the first portion of the metal layer prior to treating the first portion of the metal layer. A passive resistive device is formed from the first portion of the metal layer and the capping layer overlying the first portion of the semiconductor substrate. In addition, a transistor is formed overlying the second portion of the semiconductor layer wherein the second portion of the metal layer is used as a control electrode of the transistor.

The method can further comprise selectively treating the first portion of the metal layer by implanting oxygen into the first portion of the metal layer. Still further, the method can also comprise providing electrical connections to the passive resistive device and coupling a programming voltage to the passive resistive device to form a void in the metal layer and capping layer that creates an open circuit between the electrical connections of the passive resistive device, the passive resistive device functioning as a fuse.

The method can still further comprise selectively treating the first portion of the metal layer by implanting the first portion of the metal layer with an implant species that amorphize the first portion of the metal layer. In another embodiment, selectively treating the first portion of the metal layer can comprise implanting the first portion of the metal layer with an implant species that produces at least one of a changed phase or a secondary phase in the first portion of the metal layer. In a further embodiment, selectively treating the first portion of the metal layer can comprise adding an impurity element to the first portion of the metal layer. Still further, treating the first portion of the metal layer can include performing a plasma anneal to increase the resistivity of the first portion of the metal layer.

In another embodiment of the present disclosure, a semiconductor device comprises a metal layer having an increased sheet resistivity by being treated with an implant species; and a polysilicon layer adjacent to and in contact with the metal layer, the polysilicon layer having a sheet resistivity that is less than the increased sheet resistivity of the metal layer, the metal layer and polysilicon layer forming a resistive device having first and second terminals. The semiconductor device further comprises a transistor lateral to the resistive device, the transistor having a gate that uses a different portion of metal from the metal layer, the different portion of the metal having a lower sheet resistivity than the increased sheet resistivity.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims. The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.