Method and apparatus for maintaining data integrity using a system management processor

The disclosed embodiments relate generally to providing increased data integrity in computer systems and, more particularly, to using a system management processor to maintain the integrity of stored information. A system management processor detects an attempt to reboot the computer system and holds the system processor or processors in a reset state. While the system processor or processors are held in the reset state, the system management processor checks data such as the system BIOS to identify corruption. If the data checked by the system management processor is not corrupted, the system processor or processors are removed from the reset state and allowed to continue normal operation. If the data checked by the system management processor is corrupted, the system management processor repairs the corrupted data before removing the system processor or processors from the reset state.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The disclosed embodiments relate generally to providing increased data integrity in computer systems and, more particularly, to using a system management processor to maintain the integrity of stored information.

2. Background of the Related Art

Since the introduction of the first personal computer (“PC”) over 20 years ago, technological advances to make PCs more useful have continued at an amazing rate. Microprocessors that control PCs have become faster and faster, with operational speeds eclipsing the gigahertz (one billion operations per second) and continuing well beyond.

Productivity has also increased tremendously because of the explosion in development of software applications. In the early days of the PC, people who could write their own programs were practically the only ones who could make productive use of their computers. Today, there are thousands and thousands of software applications ranging from games to word processors and from voice recognition to web browsers.

a. The Evolution of Networked Computing and System Management Tools

In addition to improvements in PC hardware and software generally, the technology for making computers more useful by allowing users to connect PCs together and share resources between them has also seen rapid growth in recent years. This technology is generally referred to as “networking.” In a networked computing environment, PCs belonging to many users are connected together so that they may communicate with each other. In this way, users can share access to each other's files and other resources, such as printers. Networked computing also allows users to share internet connections, resulting in significant cost savings. Networked computing has revolutionized the way in which business is conducted across the world.

Not surprisingly, the evolution of networked computing has presented technologists with some challenging obstacles along the way. One obstacle is connecting computers that use different operating systems (“OSes”) and making them communicate efficiently with each other. Each different OS (or even variations of the same OS from the same company) has its own idiosyncrasies of operation and configuration. The interconnection of computers running different OSes presents significant ongoing issues that make day-to-day management of a computer network challenging.

Another significant challenge presented by the evolution of computer networking is the sheer scope of modern computer networks. At one end of the spectrum, a small business or home network may include a few client computers connected to a common server, which may provide a shared printer and/or a shared internet connection. On the other end of the spectrum, a global company's network environment may require interconnection of hundreds or even thousands of computers across large buildings, a campus environment, or even between groups of computers in different cities and countries. Such a configuration would typically include a large number of servers, each connected to numerous client computers.

Further, the arrangements of servers and clients in a larger network environment could be connected in any of a large number of topologies that may include local area networks (“LANs”), wide area networks (“WANs”) and municipal area networks (“MANs”). In these larger networks, a problem with any one server computer (for example, a failed hard drive, corrupted system software, failed network interface card or OS lock-up to name just a few) has the potential to interrupt the work of a large number of workers who depend on network resources to get their jobs done efficiently. Needless to say, companies devote a lot of time and effort to keeping their networks operating trouble-free to maximize productivity.

An important aspect of efficiently managing a large computer network is to maximize the amount of analysis and repair that can be performed remotely (for example, from a centralized administration site). Tools that facilitate remotely analyzing and servicing server problems help to control network management costs by reducing the number of network management personnel required to maintain a network in good working order. System management also makes network management more efficient by reducing the delay and expense of analyzing and repairing network problems. Using remote management tools, a member of the network management team may identify problems and, in some cases, solve those problems without the delay and expense that accompanies an on-site service call to a distant location.

In one system management strategy, a system management processor, which is completely separate from the system microprocessor(s), operates independently to provide system management functionality and remote communication capability. These system management processors have the capability of monitoring and controlling a wide range of system information. Some system management processors may be powered up even when the main computer system that they support is not powered up.

b. The Need for Robustness When System Data Becomes Corrupted

Modern users of computer systems typically expect very high levels of availability from their systems. To satisfy this desire, manufacturers of computer systems strive to make systems as robust as possible. One source of potential system problems is corruption of data stored in non-volatile random access memory (NVRAM) or electrically erasable and programmable read only memory (EEPROM). The corruption of data can occur for any number of reasons, such as system power failure during operation of the computer system or the like.

The system BIOS of most computer systems is typically stored in EEPROM memory. If the system BIOS becomes corrupt, the computer system will probably not be able to boot or otherwise operate correctly. When a system is down because of BIOS corruption, users are not able to access system resources, making it more difficult for them to perform their assigned tasks. Repair of systems with corrupted BIOS can be costly and time consuming. A method and apparatus that reduces undesirable system downtime because of corruption of data stored in memory, including the system BIOS, is desirable.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Referring now toFIG. 1, a schematic block diagram of a computer system utilizing the present invention is illustrated. A computer system is generally indicated by the numeral100and comprises a processor (or processor complex comprising multiple central processing units)102. Also included in the computer system100are core logic chipset104(or north bridge), system random access memory (“RAM”)106, a video graphics controller(s)110, a video display(s)112, a PCI/SCSI bus adapter114, a PCI/EISA/LPC bridge116, and a PCI/ATA controller118. A hard drive128and CD ROM drive134may be connected to the PCI/ATA controller118.

Single or multilevel cache memory (not illustrated) may also be included in the computer system100according to the current art of microprocessor computer systems. If the computer system100includes multiple processors, they may be arranged in a symmetric or asymmetric multi-processor configuration.

The processor102is connected to the core logic104through a host bus103. The system RAM106is connected to the core logic104through a memory bus105. The configuration registers of the computer system may be incorporated into the processor or in the system RAM106(or some combination of the two). The configuration registers may be designed to control the operation of many of the system components shown in FIG.1.

The video graphics controller(s)110is connected to the core logic104through an AGP bus107(or other bus for transporting video data). The PCI/SCSI bus adapter114, PCI/EISA/LPC bridge116, and PCI/ATA controller118are connected to the core logic104through a primary PCI bus109. Those of ordinary skill in the art will appreciate that a PCI-X bus or Infiniband bus may be substituted for the primary PCI bus109. The specific protocol of the bus109is not a crucial aspect of the present invention.

Also connected to the PCI bus109are a network interface card (“NIC”)122and a PCI/PCI bridge124. Some of the PCI devices such as the NIC122and PCI/PCI bridge124may plug into PCI connectors on the computer system100motherboard (not illustrated). The PCI/PCI bridge124provides an additional PCI bus117.

Hard disk130and tape drive132are connected to the PCI/SCSI bus adapter114through a SCSI bus111. The NIC122is connected to a local area network119. The PCI/EISA/LPC bridge116connects over a low pin count (LPC) bus113to a Electrically Erasable Random Access Memory (“EEPROM”)140, a non-volatile random access memory (NVRAM)142, a modem120, and an input-output controller126. The EEPROM140may store the system BIOS and may include flash memory. The NVRAM142may store system configuration settings and the like. The NVRAM142may include a programmable logic array (“PAL”) or any other type of programmable non-volatile storage. The modem120connects to a telephone line121. The input-output controller126interfaces with a keyboard146, CD-ROM drive144, mouse148, floppy disk drive (“FDD”)150, serial/parallel ports152and a real time clock (“RTC”)154. The LPC bus113is a slower information bus than the PCI bus109, but it costs less to interface with the LPC bus113.

FIG. 2shows a functional block diagram of one exemplary embodiment of the disposition of a system management processor in the context of the present invention. A system management processor200is connected so that it may exchange information over the PCI bus109.

Many modern computer systems employ a messaging protocol known as the Advanced Programmable Interrupt Controller protocol, which is sometimes referred to by the acronym APIC. Computer systems based on IA-32 processors manufactured by Intel Corporation of Santa Clara, Calif. are examples of computer systems that may employ the APIC protocol. Intel also produces IA-64 processors that employ a similar protocol known as System Advanced Programmable Interrupt Controller protocol or SAPIC. The APIC and SAPIC protocols provide the system microprocessor(s)102with the ability to send and receive software interrupts. The system management processor200may be adapted to send and receive messages using the APIC or SAPIC protocols via the PCI bus109or any other communication interface.

The system management processor200may be disposed on an add-in card or it may be embedded on the motherboard or other circuit board of the computer system100. The exact configuration and location of the system management processor200is not a crucial aspect of the present invention. Additionally, the system management processor200may have access to independent communications interfaces to facilitate transmitting information to users or members of a network management team. Examples of such interfaces include a Universal Serial Bus (USB) interface, an LCD interface, a floppy drive interface and/or a CD ROM interface. These interfaces may be independent of similar interfaces that are used by the computer system100.

As set forth above, the system management processor200may be adapted to monitor a wide variety of activities and functions of the system processor or processors102or other components of the computer system100. The system management processor200may be connected so that it is powered up and functional even though the computer system100is powered down and not operating. Moreover, the system management processor200operates independently of the system processor or processors102. This independent operation makes the system management processor200ideally suited to perform monitoring and remote management tasks. The independent nature of the system management processor200makes the computer system100more robust because it allows a user to obtain information about system problems and service many problems remotely without requiring on-site user intervention.

The system management processor200is connected so that it may monitor the status of a system power switch202. The system power switch202provides main power to the computer system100. As previously set forth, the system power switch202does not control the application of power to the system management processor200, which is powered up continuously in the illustrated embodiment. Additionally, the system management processor200is connected so that it may control a reset line204of the system processor (or processors)102. The system management processor200may be adapted to intercept a signal to reboot the computer system100and to hold the system processor (or processors)102in a reset state while the system management processor performs monitoring operations.

The system management processor200may be adapted to determine when the computer system100is being booted in a variety of ways. In the illustrated embodiment, the system management processor200knows that the system is being booted when it detects that the system is being powered up by the system power switch202. The system management processor may also be adapted to detect when a request to boot interrupt (INT 19) is asserted, for example, using either the APIC or SAPIC protocols. The exact method by which the system management processor determines that the computer system100is being booted is not a crucial aspect of the present invention.

While the system management processor200is holding the system processor (or processors)102in a reset state, the system management processor200may perform a variety of tasks to verify data integrity. For example, the system management processor200may be adapted to check the integrity of a set of target data, such as programming stored in the system NVRAM140and/or the system EEPROM142. One method of determining the integrity of the set of target data may be to compute a checksum for the relevant data and compare the computed value to a previously-stored value. If the computed value does not match the previously-stored “known good” value, the data may be assumed to be corrupted. The system management processor200may be adapted to employ any method to determine the validity of the data that it is assessing. The specific means of determining whether the data is corrupted is not a crucial aspect of the present invention. If the system management controller determines that the data that it is verifying is valid (i.e. not corrupted) the system management processor200may allow the normal boot process to continue by deasserting the reset line204to allow the system processor (or processors)102to continue normal operation.

If the system management processor200determines that the set of target data (the system BIOS, for example) is corrupt, the system management processor200may notify a user of the computer system100with an error message. The system management processor200may additionally inform the user (either local or remote) to load an uncorrupted image from a media such as a floppy disk or CD ROM disk. If the computer system100is connected to a network, such as via a network interface card (NIC)122, the system management processor may request an uncorrupted image from a network location.

Upon obtaining an uncorrupted image of the programming that the system management processor200determined to be defective, the system management processor200may reprogram the corrupted portion of memory. After the corrupted memory has been successfully reprogrammed, the system management processor200removes the system processor (or processors) from the reset state by deasserting the reset line204. The system processor (or processors)102then continue normal operation.

The system management processor200may be adapted to communicate information back and forth with the OS of the computer system100. For example, the system management processor200may be adapted to communicate using the microcontroller descriptor set forth in the Advanced Configuration and Power Interface standard.

FIG. 3is a process flow diagram illustrating the operation of an embodiment of the present invention. The process is generally referred to by the reference numeral300. At302, the process is initiated by the powering on of the computer system100(FIG.1). At304, the system management processor200(FIG. 2) detects an attempt to boot the computer system100. In response, the system management processor200holds the system processor(s)102in a reset state, as depicted at306.

While the system processor(s)102are held in the reset state, the system management processor200checks to determine if selected data has become corrupted. By way of example, the system management processor200may check the system BIOS, which may be stored in EEPROM142(FIG.2), to determine if it has become corrupted. If the data is not corrupted, the system management processor200releases the system processor(s)102from the reset state, as shown at314. If the target data checked by the system management processor200is corrupted, repair of the corrupted target data is attempted as described above with reference to FIG.2. Upon such repair, the system processor(s)102are released from the reset state at314. At316, the process ends.