Source driver and method for restraining noise thereof

The present invention discloses a source driver and a method for restraining noise output by a source driver during power on/off of a power supply. The source driver includes a data bus, a plurality of channels, a multiplexer and a plurality of output pads. The channels are connected to the output pads via the multiplexer. Each channel has a latch unit. Data is transmitted on the data bus and stored in the latch units. The source driver is powered by a first supply voltage from the power supply. The method comprises determining whether the first supply voltage is insufficient, and if yes, performing the following steps. First, set the data transmitted on the data bus to be a predetermined value. Then, keep the latch units turned on, thereby the data is sent out from the latch units. Then, keep the multiplexer turned on for outputting a driving voltage based on the data via the output pads.

FIELD OF THE INVENTION

This invention relates to a display, and more particularly, to a source driver of a display and a method thereof.

BACKGROUND OF THE INVENTION

Recently, liquid crystal displays (LCD) have been widely applied in electrical products due to the rapid progress of optical technology and semiconductor technology. Moreover, with advantages of high image quality, compact size, light weight, low driving voltage and low power consumption, LCDs have been introduced into portable computers, personal digital assistants and color televisions, and have become the mainstream display apparatus.

FIG. 1shows a diagram of a conventional source driver100of the LCD. The source driver100includes channels (108,110), a multiplexer112, output pads (114,116), a databus118and a charge sharing switch120. The channels108and110are connected to the output pads114and116, respectively, via the multiplexer112. The charge sharing switch120is electrically connected between the output pads114and116to share the voltages on the outputs if needed. Each channel has a shift register (122or132), a latch unit (123or133), a level shifter (128or138) and a digital-to-analog converter (DAC) (130or140). Each latch unit comprises a first latch (124or134) and a second latch (126or136) connected in series. The data is transmitted on the data bus118and stored in the latch units, and moreover, the data is stored first in the first latch and then stored in the second latch. The data is further sent to a display (not shown) via the output pads114and116to show corresponding images on the display.

However, when the power supply powering the source driver is being turned off, the power supplying to the source driver decreases and the channels may malfunction owing to the power insufficient, which results in abnormal images, such as line defects or band mura, shown on the display.

SUMMARY OF THE INVENTION

Therefore, an aspect of the present invention is to provide a source driver and a method for restraining noise thereof in which abnormal images shown on the display during power on/off of a power supply can be restrained.

Another objective of the present invention is to provide a source driver with a power down detector for detecting whether the power supply is turning on/off and if yes, asserting a reset signal.

In order to achieve the aforementioned aspects, the present invention provides a method for restraining noise output by a source driver during power on/off of a power supply. The source driver includes a data bus, a plurality of channels, a multiplexer and a plurality of output pads. The channels are connected to the output pads via the multiplexer. Each channel has a latch unit. Data is transmitted on the data bus and stored in the latch units. The source driver is powered by a first supply voltage from the power supply. The method comprises the following steps. First, determine whether the first supply voltage is insufficient, and if yes, perform the following steps. Set the data transmitted on the data bus to be a predetermined value. Then, keep the latch units turned on, thereby the data is sent out from the latch units. Then, keep the multiplexer turned on for outputting a driving voltage based on the data via the output pads.

To achieve the aforementioned aspects, the present invention provides a source driver powered by a power supply. The source driver comprises a data bus, at least two channels, a multiplexer, at least two output pads and a power down detector. Each channel has a latch unit. Data is transmitted on the data bus and stored in the latch units. The output pads are coupled to the channels via the multiplexer. The power down detector is used for detecting whether a first supply voltage from the power supply is insufficient and if yes, asserting a reset signal. If the reset signal is asserted, the data transmitted on the data bus is set to be a predetermined value, the latch units are turned on, thereby the data is sent out from the latch units, and the multiplexer is turned on for outputting a driving voltage via the output pads based on the data.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In order to make the illustration of the present invention more explicit and complete, the following description is stated with reference toFIGS. 2 through 4.

FIG. 2shows a diagram of a source driver according to a preferred embodiment of the present invention. The source driver200inFIG. 2is powered by a power supply202, and the source driver200comprises channels (channel208, channel210. . . ), at least one multiplexer (MUX)212, output pads (output pad214, output pad216. . . ) coupled to the channels via the multiplexer212, a charge sharing switch220electrically connected between the output pads214and216to share the voltages on the outputs if needed, a power down detector204connected to the power supply202, and a controller206connected to the power down detector204. The power supply202may provide a first supply voltage which is at high level and a second supply voltage which is at low level.

The power down detector204determines whether power is turning on or off and generates a reset signal RS if yes. The determination of power on/off is made by detecting whether any one of the first supply voltage and the second supply voltage from the power supply202is in sufficient, that is, below certain thresholds.

The reset signal RS is sent to the controller206. The controller206then generates a control signal CN in accordance with the reset signal RS and sends the control signal CN to the charge sharing switch220to turn off the charge sharing switch220. The control signal CN is further sent to the multiplexer to disconnect the channels with the output pads so that the possibly abnormal data would not be transmitted to the output pads when the power supply202powering the source driver is being turned on/off. Thus, the display keeps showing the original image during power on/off of the power supply.

FIG. 3shows a diagram of another source driver according to the preferred embodiment of the present invention. The source driver300inFIG. 3is powered by a power supply302, and the source driver300comprises channels308and310, a multiplexer (MUX)312, output pads314and316, a data bus318, a charge sharing switch320, a power down detector304connected to the power supply302, and a controller306connected to the power down detector304. The output pads314and316are coupled to the channels308and310via the multiplexer312. The charge sharing switch320is electrically connected between the output pads314and316of the source driver300to share the voltages on the outputs if needed.

Each channel has a shift register (322or332), a latch unit (323or333), a level shifter (328or338) and a digital-to-analog converter (DAC) (330or340). Each latch unit comprises a first latch (324or334) and a second latch (326or336) connected in series. The data is transmitted on the data bus318and stored in the latch units, and moreover, the data is stored first in the first latch and then stored in the second latch.

When the power supply302supplies power to the source driver300normally, the data in the channels is inputted to the multiplexer312and further sent to a display (not shown in the drawing) via the output pads314and316to show corresponding images on the display. However, when the power supply302is being turned on or off, the power sent to the source driver300becomes insufficient. The power down detector304generates a reset signal RS if the voltage sent from the power supply302is insufficient and sends the reset signal RS to the controller306to generate a control signal CN based on the reset signal RS. The control signal CN is sent to the charge sharing switch320to turn it off. Then, the control signal CN is also sent to the data bus318to set the data transmitted on the data bus318to be a predetermined value. Moreover, the control signal CN is also sent to the latch units323and333to keep the latch units323and333turned on, thereby the data is sent out from the latch units323and333. The control signal CN is further sent to the multiplexer312to keep the multiplexers312turned on for outputting a driving voltage based on the data via the output pads. Thus, the output pads314and316output the predetermined voltage to a display (not shown in the drawing). Therefore, the display shows a corresponding black image or a white image during power on/off of the power supply.

It is noted that the charge sharing switch is optional in other embodiments of the present invention. Thus, the step of turning off the charge sharing switch if the power supply302is being turned on or off, i.e. the first supply voltage is insufficient, is also optional in other embodiments of the present invention. Furthermore, the step of keeping the latch unit on is to keep the second latch on in the preferred embodiment of the present invention.

The following describes in detail the structure of the power down detector and the generation of the reset signal RS.

FIG. 4shows a diagram of the power down detector according to the preferred embodiment of the present invention. The power down detector304inFIG. 4comprises a first voltage divider402, a second voltage divider404, a first comparator406, a second comparator408, a first inverter410, a second inverter412, a third inverter414, a fourth inverter416, a level shifter418, a fifth inverter420and an OR gate426. The OR gate426comprises a NOR gate422and a sixth inverter424connected in series. The first voltage divider402includes series-connected resistors R1-R7, and the second voltage divider404includes series-connected resistors R11-R16.

The first voltage divider402generates a first divided voltage VA1based on the first supply voltage VDDA from the power supply, and the second voltage divider404generates a second divided voltage VD1based on the second supply voltage VDDD from the power supply. The first comparator406compares the first divided voltage VA1with the threshold voltage VTHand generates a first comparison signal RSA. The first comparison signal RSA is logic high if the first divided voltage VA1is smaller than the threshold voltage VTH, inferring that the power supply is insufficient due to being turned on/off. The first comparison signal RSA is logic low if the first divided voltage VA1is greater than the threshold voltage VTH, inferring that the power supply supplies power to the source driver normally.

Similarly, the second comparator408compares the second divided voltage VD1with the threshold voltage VTHand generates a second comparison signal RSD. The second comparison signal RSD is logic high if the second divided voltage VD1is smaller than the threshold voltage VTH, inferring that the power supply is being turned on/off. The second comparison signal RSD is logic low if the second divided voltage VD1is greater than the threshold voltage VTH, inferring that the power supply supplies power to the source driver normally. The first supply voltage VDDA is a high voltage compared to the second supply voltage VDDD, and the first comparator is a high-voltage element and the second comparator is a low-voltage element. The setting of the first divided voltage VA1, the second divided voltage VD1and the threshold voltage VTHcan be determined and changed by users.

The threshold voltage VTHis generated by a circuit that is not easily affected by the decreasing output of the power supply, such as a band-gap voltage generator.

The first comparison signal RSA is sent through the first inverter410and the second inverter412and to one input node of the OR gate426. The second comparison signal RSD is sent through the third inverter414and the fourth inverter416and then to the level shifter418to shift the level of the second comparison signal RSD. The level-shifted second comparison signal RSD is further sent through the fifth inverter420and to the other input node of the OR gate426. If the first comparison signal RSA and the second comparison signal RSD are both logic low, the OR gate426outputs a logic low signal inferring that the power supply supplies power to the source driver normally so that no reset signal is generated. Contrarily, if the first comparison signal RSA and/or the second comparison signal RSD are/is logic high, the OR gate426outputs a logic high signal inferring that the power supply is being turned on/off and the reset signal RS is generated.

According to the aforementioned description, one advantage of the embodiment is that abnormal images shown on the display during power off of a power supply can be restrained.

According to the aforementioned description, yet another advantage of the embodiment is that a power down detector is used in the present invention to detect whether the power supply is being turned on/off and generates a reset signal if yes.