Memory stripe coding management

A method includes writing, to a first sub-set of memory blocks of a first plane associated with a memory device, first data corresponding to recovery of an uncorrectable error and writing, to a first sub-set of memory blocks of a second memory plane associated with the memory device, second data corresponding to recovery of the uncorrectable error. A relative physical location of the first sub-set of memory blocks of the first memory plane and a relative physical location of the first sub-set of memory blocks of the second memory plane are a same relative physical location with respect to the first memory plane and the second memory plane.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to memory stripe coding management for a memory sub-system.

BACKGROUND

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to memory stripe coding management, in particular to memory sub-systems that include a memory stripe coding management component. A memory sub-system can be a storage system, storage device, a memory module, or a combination of such. An example of a memory sub-system is a storage system such as a solid-state drive (SSD). Examples of storage devices and memory modules are described below in conjunction withFIG.1, et alibi. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A memory device can be a non-volatile memory device. One example of non-volatile memory devices is a negative-and (NAND) memory device (also known as flash technology). Other examples of non-volatile memory devices are described below in conjunction withFIG.1. A non-volatile memory device is a package of one or more dice. Each die can consist of one or more planes. Planes can be groups into logic units (LUN). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. For some memory devices, blocks (also hereinafter referred to as “memory blocks”) are the smallest area than can be erased. Pages cannot be erased individually, and only whole blocks can be erased.

Each of the memory devices can include one or more arrays of memory cells. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values. There are various types of cells, such as single level cells (SLCs), multi-level cells (MLCs), triple level cells (TLCs), and quad-level cells (QLCs). For example, a SLC can store one bit of information and has two logic states.

Some NAND memory devices employ a floating-gate architecture in which memory accesses are controlled based on a relative voltage change between the bit line and the word lines. Other examples of NAND memory devices can employ a replacement-gate architecture that can include the use of word line layouts that can allow for charges corresponding to data values to be trapped within memory cells based on properties of the materials used to construct the word lines.

A memory sub-system can employ techniques to perform data recovery in the event of a memory defect associated with the programming of user data (e.g., data written by a host system) to a memory device of the memory sub-system. Conventionally, memory defects can be managed by a controller of the memory sub-system by generating parity data (e.g., exclusive-or (XOR) parity data) based on the written host data. The generated parity data (e.g., the XOR parity data) can be written by a controller to a cache memory (e.g., a volatile memory device such as a random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM)) of the controller.

In many electronic devices (e.g., mobile devices) including electronic devices having an array of memory cells storing multiple bits per cell (e.g., quad-level cells (QLCs)), both multiple page (e.g., multi-page) parity protection and multiple plane (e.g., multi-plane) parity protection (e.g., protection for a failure of a memory device) is employed. In such systems, a large amount of cache memory storage space is required in order to store both multi-page parity data and multi-plane parity data. For example, for multi-page parity protection, 16 KB of parity data can be generated for each page line of the memory sub-system. In addition, a memory sub-system can have a multi-plane memory die (e.g., N planes) including multiple blocks of memory cells arranged in multiple planes (e.g., a multi-plane memory device) for which multi-plane parity protection can be employed. Each block can be divided into multiple sub-blocks that can each include multiple pages per block.

In general, major failures in a memory sub-system can invoke multiple word lines of the memory device and/or multiple planes of the memory device. Memory sub-systems having multiple planes (e.g., N planes per memory die) can require generation and storage of multi-plane parity data to enable protection against a multi-plane failure (e.g., a failure of some or all planes of the memory device). Similarly, memory sub-systems having multiple pages can require generation and storage of multi-page parity data to enable protection against a failure invoking multiple word lines of the memory device (e.g., a failure of some or all word lines of the memory device). However, protecting against both multi-word line failures and multi-plane failures can be difficult both in terms of an amount of memory space required to protect against both types of failures and in performance limitations associated with a memory sub-system.

In some approaches, for a multi-plane arrangement (e.g., a memory die having N planes), memory sub-systems can generate multi-plane parity data by executing an exclusive-or (XOR) operation based on the data written by the host system (also referred to as a resource value (R)) to multiple logical units (e.g., logical unit1to logical unit Y) of the memory sub-system. It is noted that each logical unit can include multiple planes (e.g., Plane 0, Plane 1, . . . , Plane N-1). The multi-plane parity data for each plane can be stored in cache memory of the controller. In some approaches, the controller executes an additional XOR operation on the data associated with all of the planes to generate multi-page parity data for each page (e.g., sub-block) or page line (e.g., word line). This multi-page parity can also be stored in cache memory of the controller.

For example, for a multi-plane memory die having N planes having two memory block sub-sets, 16 KB of parity data can be generated and stored for each plane. If each memory block sub-set includes3pages, then 48 KB of parity data can be generated and stored for each memory block sub-set across N planes. Furthermore, an additional sub-block of cache memory can be required for each memory block sub-set of the multi-plane memory in order to generate multi-plane parity data. For example, in a memory sub-system managing parity data for a multi-plane memory having 4 planes (e.g., N=4), a total controller cache memory requirement for one memory block sub-set of a multi-plane parity protection can be 96 KB per plane resulting in a cache memory requirement of 384 KB (e.g., 96 KB×4 planes). This represents a significant controller cache expenditure associated with some approaches to management of multi-page and multi-plane parity protection. Accordingly, there is a need to reduce expenditure of controller cache memory in connection with the storage of multi-page and/or multi-plane parity data used of the execution of a data recovery operation in the event of a loss of host written data.

In addition, given the storage limitations of some memory sub-systems, the parity data can, as memory resources become tied up, be written more frequently. This can lead to a write performance penalty being incurred by the memory sub-system in which more writes (and hence, more program-erase cycles) are incurred in order to protect the host written data. Accordingly, there is a need to reduce the quantity of program-erase cycles invoked in connection with the storage of multi-page and/or multi-plane parity data used of the execution of a data recovery operation in the event of a loss of host written data.

Aspects of the present disclosure address the above and other deficiencies by managing memory stripe coding such that multi-page and multi-plane parity protection can be provided within a shared stripe of parity data. As described in more detail, herein, the shared parity stripe can include redundant array of independent NAND (RAIN) recovery data. In some embodiments, the shared parity stripe can be coded such that, in contrast to approaches in which the same sub-blocks or pages are placed in different planes within a same RAIN stripe, different sub-blocks or pages are placed in different planes within a same RAIN stripe.

As described below, this can reduce the amount of memory resources required in some approaches to protect against failures that can lead to a loss of host written data. Further, such coding schemes can enable customizable parity data management based on failure schemes associated with a memory sub-system. In addition, embodiments described herein can be realized in the absence of firmware (or changes to firmware) to invoke different data recovery steps for different types of memory sub-system failures (e.g., multi-word line failures vs. multi-plane failures).

The term “RAIN,” as used herein, is an umbrella term for computer information (e.g., data) storage schemes that divide and/or replicate (e.g., mirror) information among multiple pages of a memory sub-system, for instance, in order to help protect the data stored in the memory sub-system. A RAIN array may appear to a user and the operating system of a computing device as a single memory device (e.g., disk). RAIN can include striping (e.g., splitting) information so that different portions of the information are stored on different pages of the memory sub-system. The portions of the memory sub-system that store the split data can be collectively referred to as a stripe. As used herein, RAIN can also include mirroring, which can include storing duplicate copies of data on more than one page of more than one memory sub-system.

A RAIN stripe can include (e.g., be a combination of) user data and parity data. The parity data of the RAIN stripe, which can be referred to herein as the parity portion of the RAIN stripe, can include error protection data that can be used to protect user data stored in the memory sub-system against defects and/or errors that may occur during operation of the memory sub-system. For example, the RAIN stripe can protect user data stored in memory sub-system against defects and/or errors that may occur during operation of the memory sub-system, and can therefore provide protection against a failure of the memory sub-system.

The memory devices130,140can include any combination of the different types of non-volatile memory devices and/or volatile memory devices. The volatile memory devices (e.g., memory device140) can be, but are not limited to, random access memory (RAM), such as dynamic random-access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

The memory sub-system110can include a memory stripe coding management component113. Although not shown inFIG.1so as to not obfuscate the drawings, the memory stripe coding management component113can include various circuitry to facilitate organization and selective writing of data (e.g., parity data) to particular pages of memory of a memory device130,140. For example, the memory stripe coding management component113can cause similar parity data (e.g., the data338-1to338-7described in connection withFIG.3, herein) to be written to pages (e.g., the pages238-1to238-M illustrated inFIG.2, herein) that are located in physically different locations within planes (e.g., the planes234-1to234-P illustrated inFIG.2, herein) of a memory device130,140. In some embodiments, the memory stripe coding management component113can include special purpose circuitry in the form of an ASIC, FPGA, state machine, and/or other logic circuitry that can allow the memory stripe coding management component113to orchestrate and/or perform operations to perform memory stripe coding management operations for the memory device130and/or the memory device140as described herein.

In some embodiments, the memory sub-system controller115includes at least a portion of the memory stripe coding management component113. For example, the memory sub-system controller115can include a processor117(processing device) configured to execute instructions stored in local memory119for performing the operations described herein. In some embodiments, the memory stripe coding management component113is part of the host system110, an application, or an operating system.

In some embodiments, an apparatus (e.g., the computing system100) can include a memory stripe coding management component113. The memory stripe coding management component113can be resident on the memory sub-system110. As used herein, the term “resident on” refers to something that is physically located on a particular component. For example, the memory stripe coding management component113being “resident on” the memory sub-system110refers to a condition in which the hardware circuitry that comprises the memory stripe coding management component113is physically located on the memory sub-system110. The term “resident on” may be used interchangeably with other terms such as “deployed on” or “located on,” herein.

FIG.2illustrates an example memory device230in accordance with some embodiments of the present disclosure. The memory device230can be analogous to the memory device130illustrated inFIG.1, herein. Although not shown so as not obfuscate the drawings, the memory device230can be a non-volatile memory device230that includes an array of non-volatile memory cells. In some embodiments, the memory device230can be a NAND flash memory device (e.g., a 3-D NAND flash memory device) and/or can be deployed in a mobile computing device such as a mobile phone, laptop, IoT device, or the like.

As shown inFIG.2, the memory device230can include multiple memory dice232-1to232-N (e.g., the MEMORY DIE_0 to the MEMORY DIE N), which can each include multiple planes234-1to234-P (e.g., the PLANE 0 to the PLANE P). A number of blocks (or sub-blocks), which can be referred to as pages238-1to238-M (e.g., the PAGE_0 to the PAGE_M), can be included in each of the planes234-1to234-P. That is, as shown inFIG.2, a number of physical blocks (or sub-blocks) or pages238-1to238-P can be included in a plane234-1to234-P, and a number of planes234-1to234-P can be included on a memory die232-1to232-N.

As shown inFIG.2, the pages238-1to238-M can be included in one or more physical rows236-1to236-R. The rows236-1to236-R can be coupled to word lines (e.g., access lines) and can, as is appropriate given the context, be referred to as word lines236-1to236-R, herein. Further, although not shown inFIG.2, the memory cells can be coupled to sense lines (e.g., data lines and/or digit lines). As one of ordinary skill in the art will appreciate, each row236-1to236-R can include a number of pages of memory cells (e.g., physical pages). A physical page refers to a unit of programming and/or sensing (e.g., a number of memory cells that are programmed and/or sensed together as a functional group). In some embodiments, each row236-1to236-R comprises one physical page of memory cells. However, embodiments of the present disclosure are not so limited. For instance, in some embodiments, each row236-1to236-R can include multiple physical pages238-1to238-M of memory cells (e.g., one or more even pages of memory cells coupled to even-numbered word lines and/or bit lines, and one or more odd pages of memory cells coupled to odd numbered word lines and/or bit lines). Additionally, for embodiments including multilevel cells, a physical page238-1to238-M of memory cells can store multiple logical pages of data (e.g., an upper page of data and a lower page of data, with each cell in a physical page storing one or more bits towards an upper page of data and one or more bits towards a lower page of data).

Although not explicitly shown inFIG.2, a row236-1to236-R of memory cells can comprise a number of physical sectors (e.g., subsets of memory cells). Each physical sector of cells can store a number of logical sectors of data. Additionally, each logical sector of data can correspond to a portion of a particular page of data. As an example, one logical sector of data stored in a particular physical sector can correspond to a logical sector corresponding to one page (e.g., the page238-1) of data, and the other logical sector of data stored in the particular physical sector can correspond to the other page (e.g., the page238-M) of data. Each physical sector can store system data, user data, and/or overhead data, such as error correction code (ECC) data, LBA data, and/or metadata.

FIG.3illustrates an example memory device330and memory stripe coding management component313in accordance with some embodiments of the present disclosure. The memory stripe coding management component313can be analogous to the memory stripe coding management component113illustrated inFIG.1and the memory device330can be analogous to the memory device130illustrated inFIG.1and/or the memory device230illustrated inFIG.2. In some embodiments, the memory device330and/or the memory stripe coding management component313can be deployed in a mobile computing device, such as a smartphone, laptop computer, IoT device, or the like.

As shown inFIG.3, the memory device330includes a memory die332, which can be analogous to one of the memory dice232-1to232-N illustrated inFIG.2. The memory die332can include multiple memory planes (PLANE_0334-1, PLANE_1334-2, PLANE_3334-3, PLANE_4334-4, etc.), which can be analogous to the memory planes234-1to234-N illustrated inFIG.2. Each of the planes334-1to334-4can include one or more memory pages (e.g., the pages238-1to238-M illustrated inFIG.2, herein) that can include a page of data (P_0338-1, P_1338-2, P_2338-3, P_3338-4, P_4338-5, P_5338-6, P_6338-7, P_7338-8, etc.). The pages of data338-1to338-8can include parity data (e.g., RAIN parity data) that can be used in a data recovery operation such as a RAIN recovery operation.

Pages of the memory device (e.g., the pages238-1to238-M illustrated inFIG.2, herein) can include data and be referred to as pages of data338-1to338-8. The pages of data338-1to338-8can be included in one or more physical rows336-1to336-R, which can be analogous to the physical rows236-1to236-R illustrated inFIG.2, herein. As described above, the rows336-1to336-R can be coupled to word lines (e.g., access lines) and can, as is appropriate given the context, be referred to as word lines336-1to336-R, herein.

In a non-limiting example, the memory stripe coding management component313can cause a first page of data (e.g., the page of data P_0338-1) corresponding to a data recovery operation to be written to a plane334-1of a memory device330. The memory stripe coding management component313can cause a second page of data (e.g., the page of data P_1338-2) corresponding to a data recovery operation to be written to a different plane334-2of the memory device330. In some embodiments, a relative physical location of the first page of data P_0338-1with respect to the plane334-1and a relative physical location of the second page of data P_1338-2with respect to the plane334-2are a same relative physical location with respect to a memory die332on which the plane334-1and the second334-2are located. Similarly, a relative physical location of the page of data P_4338-5with respect to the plane334-1and a relative physical location of the second page of data P_5338-6with respect to the plane334-2are a same relative physical location with respect to a memory die332on which the plane334-1and the second334-2are located, and so forth.

For example, in contrast to approaches in which each page of data is written to a same relative physical location with respect to the planes334-1,334-2,334-3, and334-4, the first page of data P_0338-1is located in a first position of a word line336-1with respect to the plane334-1and the second page of data P_1338-2is located in a first position of the word line336-1with respect to the plane334-1. By writing the pages of data338-1to338-8in the manner illustrated inFIG.3, both multi-page and multi-plane failures can be recovered without utilizing additional cache (e.g., SRAM) resources than are generally used to protect merely against multi-page failures or merely against multi-plane failures.

In some embodiments, the first page of data P_0338-1and the second page of data P_1338-2can be collocated on a single memory stripe (e.g., the word line336-1) that invokes at least one memory die332of the memory device330. Continuing with the above example, the first page of data P_0338-1and the second page of data P_1338-2can be part of a redundant array of independent NAND (RAIN) stripe written to the memory device330. Accordingly, the first page of data P_0338-1and the second page of data P_1338-2can contain data corresponding to a parity portion of RAIN stripe written to the memory device330.

The memory stripe coding management component313can cause a third page of data (e.g., the page of data P_7338-8) corresponding to the data recovery operation to be written to a different plane (e.g., the plane334-3) of the memory device330and cause a fourth page of data (e.g., the page of data P_4338-5) corresponding to the data recovery operation to be written to yet another plane (e.g., the plane334-4) of the memory device330. A relative physical location of the page of data P_7338-8with respect to the plane334-3and a relative physical location of the page of data P_4338-5with respect to the plane334-4can be a same relative physical location with respect to the memory die332on which the plane334-3and the plane334-4are located. In some embodiments, the page of data P_7338-8and the page of data338-5are written to a redundant array of independent NAND (RAIN) stripe (e.g., the word line336-2that is different than a RAIN stripe (e.g., the word line or row336-1) to which the first page (e.g., the page of data338-1) and the second page (e.g., the page of data338-2) are written.

In some embodiments, the memory stripe coding management component313can cause performance of the data recovery operation using the first page of data (e.g., the page of data P_0338-1) or the second page of data (e.g., the page of data P_1338-2), or both. The memory stripe coding management component313can cause performance of the data recovery operation responsive to a determination that that a failure involving host data written to the memory device330has occurred. The data recovery operation can be, for example, a RAIN recovery operation to recover host data having uncorrectable errors associated therewith.

In another non-limiting example, a memory sub-system (e.g., the memory sub-system110illustrated inFIG.1, herein) can include a plurality of memory planes334-1,334-2,334-3,334-4, etc. Each of the memory planes can include one or more sub-sets of memory blocks (e.g., the pages238-1to238-M illustrated inFIG.2, herein) that are physically arranged such that a first sub-set of memory blocks within a first memory plane is located in a same physical position within the first memory plane as a first sub-set of memory blocks with a second memory plane. A processing device (e.g., the memory stripe coding management component313) can perform operations that include writing first data (e.g., a page of data such as the pages of data338-1to338-8) comprising a first portion of a redundant array of independent NAND (RAIN) stripe to the first sub-set of memory blocks and writing second data (e.g., a page of data such as the pages of data338-1to338-8) comprising a second portion of the RAIN stripe to the second sub-set of memory blocks.

In some embodiments, the memory sub-system further includes a third sub-set of memory blocks within the first memory plane and a fourth sub-set of memory blocks within the second memory plane. The processing device can further perform operations including writing third data comprising a first portion of a different RAIN stripe to the third sub-set of memory blocks and/or writing fourth data comprising a second portion of the different RAIN stripe to the fourth sub-set of memory blocks. As shown inFIG.3, the third sub-set of memory blocks can be located in a same physical position within the first memory plane as the fourth sub-set of memory blocks is located within the second memory plane.

Continuing with this example, in some embodiments, the processing device further perform operations including causing performance of a data recovery operation using the first data or the second data, or both. For example, the processing device can further perform operations including causing performance of a data recovery operation responsive to a determination that that a failure involving host data written to the plurality of sub-sets of memory blocks has occurred.

FIG.4is a flow diagram corresponding to a method for memory stripe coding management in accordance with some embodiments of the present disclosure. The method440can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method440is performed by the memory stripe coding management component113ofFIG.1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation442, data (e.g., a page of data338-1to338-8illustrated inFIG.3, herein) corresponding to recovery of an uncorrectable error can be written to a sub-set of memory blocks (e.g., the block238-1to238-M illustrated inFIG.2, herein) of a memory plane (e.g., the panes334-1to334-4illustrated inFIG.3, herein) associated with a memory device (e.g., the memory device330illustrated inFIG.3, herein).

At operation446, different data corresponding to recovery of the uncorrectable error can be written to a sub-set of memory blocks of a different memory plane associated with the memory device. In some embodiments, a relative physical location of the sub-set of memory blocks of the first memory plane and a relative physical location of the sub-set of memory blocks of the second memory plane are a same relative physical location with respect to the first memory plane and the second memory plane.

At operation448, redundant array of independent NAND (RAIN) data can be written as part of writing the data corresponding to recovery of the uncorrectable error. In some embodiments, a first portion of redundant array of independent NAND (RAIN) parity data or a second portion of RAIN parity data, or both can be written as part of writing the data corresponding to recovery of the uncorrectable error.

In some embodiments, the first memory plane and the second memory plane are configured to store a portion of a first redundant array of independent NAND (RAIN) stripe and an operation to write third data corresponding to recovery of a different uncorrectable error to a first sub-set of memory blocks of a third plane associated with a memory device and/or an operation to write second data corresponding to recovery of the different uncorrectable error to a first sub-set of memory blocks of a fourth memory plane associated with the memory device can be performed. As described above, a relative physical location of the first sub-set of memory blocks of the third memory plane and a relative physical location of the first sub-set of memory blocks of the fourth memory plane are a same relative physical location with respect to the third memory plane and the fourth memory plane. In some embodiments, the third memory plane and the fourth memory plane are configured to store a portion of a second RAIN stripe.

As described above, a further operation to perform a data recovery operation using the first data or the second data, or both can be performed by, for example, a processing device, such as the memory stripe coding management component113illustrated inFIG.1, herein. In some embodiments, the data recovery operation can be performed in response to a determination that a failure involving host data written to the memory device has occurred.