Antifuse structures, antifuse array structures, methods of manufacturing the same

Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.

PRIORITY STATEMENT

This non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-0104060, filed on Oct. 16, 2007, in the Korean Intellectual Property Office, the entire contents of which is incorporated herein by reference.

BACKGROUND

Description of the Related Art

Conventional semiconductor devices, for example, a conventional semiconductor memory device, may include a relatively large number of cells. If even one of the cells is defective, the semiconductor memory device may not function properly. If the semiconductor memory device does not function properly, it may need to be discarded. This may reduce (e.g., severely reduce) product yield.

To assist in improving product yield, conventional semiconductor memory devices may include a plurality of redundancy cells (e.g., pre-formed redundancy cells) for replacing defective cells. The plurality of redundancy cells may comprise a plurality of spare rows and a plurality of spare columns, each of which may be formed at an interval of a few (e.g., 1, 2, 3, . . . ) cell arrays apart. A repairing operation using the redundancy cells may be performed by replacing a defective row and/or column with a spare row and/or column of the redundancy memory cells.

FIG. 1is a diagram of a conventional antifuse. Referring toFIG. 1, a conventional antifuse may include an n-type well region110formed on or within a p-type semiconductor substrate112. An n-type source diffusing region114and a n-type drain diffusing region116may be formed within the n-type well region110. The n-type source diffusing region114and the n-type drain diffusing region116may form ohmic contacts with the n-type well region110.

A gate dielectric layer122and a gate electrode120may be formed sequentially on the n-type well region110. A spacer123may be formed at each end of the gate dielectric layer122and the gate electrode120. The gate electrode120may be connected to a first terminal124of the antifuse100. The source diffusing region114and the drain diffusing region116may be connected to a second terminal126of the antifuse100. A p-type diffusing region130may also be formed within the semiconductor substrate112. The p-type diffusing region130may provide ohmic contact coupling between the semiconductor substrate112and a voltage Vbb.

InFIG. 1, the conventional antifuse100may have a common transistor structure, in which a source and a drain may be connected to each other using an n-type well structure. However, if the structure shown inFIG. 1is arranged in an array, the array structure may require a relatively large area or region and/or require a relatively high driving voltage. Accordingly, increasing integration of a semiconductor device may be relatively difficult.

SUMMARY

Example embodiments relate to antifuse structures and antifuse arrays, for example, antifuses in which all or substantially all antifuse cells connected to a bitline via a single contact may be connected to each other so that all or substantially all antifuse cells connected to the bitline may be selected via a wordline perpendicular to the bitline. Example embodiments also relate to methods of fabricating and operating antifuses and antifuse arrays.

At least one example embodiment provides a simpler antifuse structure in which all or substantially all antifuse cells may be connected by a bitline and a wordline such that all or substantially all cells may be selected for writing/reading data simultaneously or concurrently.

According to at least one example embodiment, an antifuse structure may include a bitline formed as a first diffusing region within a semiconductor substrate, an insulation layer formed on the bitline, and a wordline formed on the insulation layer.

According to at least some example embodiments, the antifuse structure may further include a second diffusing region formed in a region surrounding the bitline. The bitline may be a region doped with a first dopant, and the second diffusing region may be a region doped with a second dopant. The antifuse structure may further include shallow trench isolations formed at both ends of the bitline. The bitline may be a region doped with a first dopant, and the second diffusing region may be a region doped with a second dopant.

At least one other example embodiment provides an antifuse array. According to at least this example embodiment, the antifuse array may include a plurality of bitlines formed as a first diffusing region in a first direction within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer in a direction crossing the bitlines.

At least one other example embodiment provides a method of manufacturing an antifuse structure. According to at least this example embodiment, a diffusing region may be formed within a semiconductor substrate. The diffusing region may include a bitline. An insulation layer may be formed on the bitline, and a wordline may be formed on the insulation layer.

At least one other example embodiment provides a method of manufacturing an antifuse array structure. According to at least this example embodiment, a plurality of antifuse structures may be formed in an array structure. For example, a plurality of diffusing regions may be formed within a semiconductor substrate. Each of the plurality of diffusing regions may include a bitline. A plurality of insulation layers may be formed on the bitlines, and a plurality of wordlines may be formed on the insulation layers.

At least one other example embodiment provides an antifuse structure. The antifuse structure may include at least one bitline formed within a semiconductor substrate. The bitline may be a portion of the semiconductor substrate doped with a first dopant. At least one insulation layer may be formed on the bitline, and at least one wordline may be formed on the at least one insulation layer. The at least one wordline may be doped with a second dopant. The second dopant may be different from the first dopant.

At least one other example embodiment provides an antifuse array structure. The antifuse array structure may include a plurality of bitlines formed within a semiconductor substrate. The plurality of bitlines may be formed in separate portions of the semiconductor substrate by doping each region with a first dopant. A plurality of insulation layers may be formed on the bitlines, and a plurality of wordlines may be formed on the insulation layers. The wordlines may be doped with a second dopant. The second dopant may be different from the first dopant.

According to at least some example embodiments, an upper surface of at least one bitline may be planar with an upper surface of the semiconductor substrate. At least one bitline may have a semi-circular shape.

According to at least some example embodiments, at least one of the plurality of second diffusing regions and the plurality of bitlines may have has a semi-circular shape. An upper surface of each of the plurality of bitlines may be planar with an upper surface of the semiconductor substrate. Each of the bitlines may have a first length and a first width, wherein the first length is greater than the first width. The plurality of bitlines may be spaced apart from one another by a first distance in the first direction. The first distance may be greater than a width of each of the plurality of bitlines.

According to at least some example embodiments, the diffusing region may be formed by doping a portion of the semiconductor substrate with a first dopant to form the diffusing region, and doping a portion of the diffusing region with a second dopant to form the bitline. The second dopant may be different from the first dopant. The insulation layer may include at least a first portion and a second portion. The first portion may be thicker than the second portion. The forming of the insulation layer may include forming the first portion of the insulation layer on an upper surface the second diffusing region, and forming the second portion of the insulation layer on an upper surface of the bitline.

According to at least some example embodiments, the bitline may compose the entire diffusing region. In at least this example embodiment, forming of the bitline may include doping a portion of the semiconductor substrate with a first dopant to form the bitline.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are shown. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

It will be understood that when an element or layer is referred to as being “formed on,” another element or layer, it can be directly or indirectly formed on the other element or layer. That is, for example, intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly formed on,” to another element, there are no intervening elements or layers present. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between,” versus “directly between,” “adjacent,” versus “directly adjacent,” etc.).

FIG. 2Ais a diagram of an antifuse structure according to an example embodiment. Referring toFIG. 2A, an antifuse structure20may include a semiconductor substrate21having a bitline23formed at least partially within the substrate21. The bitline23may be formed as a first diffusing region. The bitline23may be formed within (e.g., entirely within) the substrate21, such that an upper surface of the bitline23is planar or substantially planar with the upper surface of the substrate21. The antifuse structure20may further include an insulation layer24and a wordline25formed (e.g., sequentially formed) on the semiconductor substrate21. If the bitline23is a region formed of a first type of dopant, the wordline25may be a region formed of a second type of dopant. The first and second types of dopant may be different.

For example, if the bitline23is formed of an n-type dopant, the wordline25may be formed of a poly-silicon doped with a p-type dopant. In this example, the semiconductor substrate21may be a p-type semiconductor substrate. The antifuse structure20may further include a shallow trench isolation region22formed at each end of the bitline23. The shallow trench isolation regions22may be formed to a depth greater than the depth at which the bitline23is formed in the substrate21. As shown inFIG. 2A, the bitline23may be formed to have a semi-circular or substantially semi-circular shape. However, the bitline23may have any suitable shape.

Still referring toFIG. 2A, the bitline23may be formed in a first portion of the semiconductor substrate21, and the shallow trench isolation regions22may be formed in second and third portions of the substrate21. Each of the shallow trench isolation regions22may border the bitline23. Upper surfaces of the bitline23and the shallow trench isolation regions22may comprise the upper surface (e.g., entire upper surface) of the substrate21.

FIG. 2Bis a perspective view of an antifuse array structure according to an example embodiment. The antifuse array structure ofFIG. 2Bmay include a plurality of antifuse structures in accordance with the example embodiment shown inFIG. 2A.

As shown inFIG. 2B, the antifuse array structure may include a plurality of bitlines23and a plurality of wordlines25formed perpendicular or substantially perpendicular to the plurality of bitlines23. For example, the plurality of bitlines23and the plurality of wordlines25may be formed to cross one another. An insulation layer24may be formed between each wordline25and the plurality of bitlines23. According to at least one example embodiment, each insulation layer24may be formed to have the same or substantially the same shape as a corresponding wordline25.

Still referring toFIG. 2B, each bitline23may have a first length and a first width, wherein the first length may be greater than the first width. The first width may extend in a first direction D1, and the first length may extend in a second direction D2. The plurality of bitlines23may be spaced apart from one another in the first direction D1. The bitlines23may be spaced apart from one another by a first distance. The first distance may be greater than the width of a bitline23.

Each wordline25may have a first length and a first width, wherein the first length may be greater than the first width. The first length may extend in the first direction D1, and the first width may extend in the second direction D2. The plurality of wordlines25may be spaced apart from one another in the second direction D2.

FIG. 3Ais a diagram of an antifuse structure according to another example embodiment. Referring toFIG. 3A, an antifuse structure30may include a bitline34formed as a first diffusing region within a semiconductor substrate31, and a second diffusing region33also formed within the semiconductor substrate31. The second diffusing region33may surround the bitline34within the semiconductor substrate31. The bitline34and the second diffusing region33may be formed within (e.g., entirely within) the substrate31, such that an upper surface of the bitline34is planar or substantially planar with the upper surface of the substrate31. Upper surfaces of the second diffusing region33may also be planar or substantially planar with the upper surface of the substrate31.

The bitline34may be doped with a first type of dopant and the second diffusing region33may be doped with a second type of dopant. The first type of dopant and the second type of dopant may be different. For example, if the bitline34is a region doped with a p-type dopant, the second diffusing region33may be doped with an n-type dopant. In this example, the second diffusing region33and the bitline34may form a p-n diode structure. The antifuse structure30may further include an insulation layer35and a wordline36formed (e.g., sequentially formed) on the semiconductor substrate31. A shallow trench isolation32may be formed at each end of the second diffusing region33.

Still referring toFIG. 3A, the bitline34may be formed in a first portion of the semiconductor substrate31, the second diffusing region33may be formed in a second portion of the substrate31, and the shallow trench isolation regions32may be formed in third and fourth portions of the substrate31. Each of the shallow trench isolation regions32may border the second diffusing region33, which may surround the bitline34within the semiconductor substrate31. Upper surfaces of the bitline34, the second diffusing region33, and the shallow trench isolation regions22may comprise the upper surface (e.g., entire upper surface) of the substrate31.

FIG. 3Bis a perspective view of an antifuse array structure according to another example embodiment. The antifuse array structure ofFIG. 3Bmay include a plurality of antifuses30ofFIG. 3A. As shown inFIG. 3B, bitlines34and wordlines36may be formed perpendicular or substantially perpendicular to one another. For example, the bitlines34and the wordlines36may be formed to cross each other perpendicularly or substantially perpendicularly.

The antifuse array structure shown inFIG. 3Bmay be similar or substantially similar to the antifuse array structure shown inFIG. 2B, except that the antifuse array structure shown inFIG. 3Bmay include antifuse structures such as those shown inFIG. 3A.

Referring toFIGS. 2A and 3A, the antifuse structures may differ in that the antifuse30ofFIG. 3Amay include a second diffusing region33surrounding the bitline34within the semiconductor structure31, and the bitline34in the antifuse structure30inFIG. 3Amay be smaller than the bitline23of the antifuse structure20inFIG. 2A. The size and/or shape of the bitline34and second diffusing region33may be similar or substantially similar to the size and/or shape of the bitline23inFIG. 2A.

FIGS. 4A through 4Care diagrams illustrating a method of manufacturing an antifuse structure according to an example embodiment. The example method shown inFIGS. 4A through 4Cmay be used to manufacture or fabricate the antifuse structure20shown inFIG. 2A.

Referring toFIGS. 4A and 4B, a plurality of (e.g., two or more) shallow trench isolations or isolation regions22may be formed to a first depth in the semiconductor substrate21. A mask26may be formed on the shallow trench isolation regions22, and the bitline23may be formed by doping a region of the semiconductor substrate21between the shallow trench isolations22(hereinafter the first diffusing region) to a second depth with a first type of dopant. The second depth may be less than the first depth. In forming the bitline23, the semiconductor substrate21may be doped such that the first diffusing region or bitline23has a semi-circular, substantially semi-circular, or similar shape. However, the bitline23may have any suitable shape. The first type of dopant may be an n-type dopant or a p-type dopant.

Referring toFIG. 4C, the mask26may be removed, and the insulation layer24and the wordline25may be formed (e.g., sequentially formed) on the semiconductor substrate21. The insulation layer24may be formed of a semiconductor insulating material such as SiO2, Si3N4, or the like. The wordline25may be formed of a material doped with a second type of dopant. The second type of dopant may be different from the first type of dopant. For example, if the bitline23is formed by doping the first diffusing region with an n-type dopant, the wordline25may be formed of, for example, poly-silicon doped with a p-type dopant.

FIGS. 5A through 5Fare diagrams illustrating a method of manufacturing an antifuse according to another example embodiment.

Referring toFIG. 5A, a plurality of (e.g., two or more) shallow trench isolations or isolation regions532may be formed to a first depth in the semiconductor substrate531. InFIG. 5B, a mask538may be formed on each of the shallow trench isolations532, and a second diffusing region533may be formed by doping a region of the semiconductor substrate531between the shallow trench isolations532to a second depth with a first type of dopant. The second depth may be less than the first depth. In forming the second diffusing region533, the semiconductor substrate531may be doped such that the second diffusing region533has a semi-circular or similar shape. However, the second diffusing region533may have any suitable shape. In one example, the first type of dopant may be an n-type dopant.

A mask or masks536may be formed on a surface of the second diffusing region533, such that a portion of the second diffusing region533remains exposed. For example, a mask536may be formed at outer portions (e.g., each end) of the second diffusing region533such that the center portion of the second diffusing region533remains exposed. The exposed portion of the semiconductor substrate531may be doped to a third depth with a second type of dopant to form the bitline534. The third depth may be less than the first and second depths. The bitline534may be doped such that the bitline534has a semi-circular or similar shape. However, the bitline534may have any suitable shape.

The portion of the second diffusing region533doped with the second type of dopant may be referred to as the first diffusing region. The second type of dopant may be different from the first type of dopant. In one example, the second type of dopant may be a p-type dopant. However, if the first type of dopant is a p-type dopant, the second type of dopant may be an n-type dopant.

Referring toFIGS. 5C through 5E, a first insulation layer541may be formed on the semiconductor substrate531by applying an oxide material on a top surface of the semiconductor substrate531, using a thermal oxidization process or the like. The first insulation layer541may be composed of, for example, a semiconductor insulating material such as SiO2, Si3N4, or the like.

As shown inFIG. 5D, at least a portion of the first insulation layer541on a top surface of the bitline534may be removed to expose the top surface of the bitline534. According to at least this example embodiment, a first portion541A and a second portion541B of the first insulation layer541may remain. A second insulation layer542may be formed on the exposed top surface of the bitline534. The second insulation layer542may be thinner than the first insulation layer541. Alternatively, the portion of the first insulation layer541on the top surface of the bitline534may be only partially removed so that the portion of the first insulation layer541on the top surface of the bitline534has a thickness less than remaining portions541A and541B of the first insulation layer541. As a result, the insulation layer535may be formed on the semiconductor substrate531.

As shown inFIG. 5E, the resultant insulation layer535may include first and second portions541A,541B and a third portion542. The first and second portions541A,541B may cover an upper surface of the second diffusing region533. The portion542may cover the upper surface of the bitline534. The height or thickness of the second portion542may be less then the height or thickness of the portions541A,541B.

As shown inFIG. 5F, a wordline536may be formed by applying a conductive material on the insulation layer535. The insulation layer portions541A,541B, and542may be oxide layers formed using a thermal oxidization (or similar) process on the top surface of the semiconductor substrate531. Alternatively, the insulation layer portions541A,541B, and542may be formed by applying SiO2, Si3N4, or the like, on the top surface of the semiconductor substrate531.

In one example, the wordline536may be formed of a material doped with a first type of dopant. For example, if the bitline534is doped with a p-type dopant, the wordline36may be formed using a material doped with an n-type dopant. Because the second insulation layer542on the top surface of the bitline534is thinner than the first insulation layer portions541A,541B, voltages applied through the wordline536and the bitline534may be more concentrated to the second insulation layer542.

A method of driving or operating antifuse cells according to example embodiments will now be described in more detail below.

FIGS. 6A and 6Bare diagrams illustrating methods of operating antifuse structures according to example embodiments. The methods shown inFIGS. 6A and 6Bmay be implemented in conjunction with the antifuse structures and/or antifuse array structures shown inFIGS. 2A,2B,3A, and/or3B.

As shown inFIGS. 6A and 6B, a plurality of bitlines be through b6and a plurality of wordlines w1through w6may be formed to cross each other. Antifuse cells may be formed at intersecting regions (intersections) of the bitlines b1through b6and the wordlines w1through w6.

Referring toFIGS. 2A and 6A, for example, the bitline23, the insulation layer24and the wordline25may be formed sequentially in a cell region A. A method of writing data to an antifuse at the cell region A, according to an example embodiment, will be described in more detail below with regard toFIG. 6A. In at least this example embodiment, the bitlines b2through b6may be in a floating state, whereas the bitline b1may be grounded.

The wordlines w2through w6may be in a floating state, and a writing (or programming) voltage Vp may be applied to the wordline w1to write data to the antifuse cell at cell region A. After the data writing operation, each of the cells may function as a diode.

According to at least this example embodiment, each of the cells on the bitline b1may be selected and programmed simultaneously or concurrently.

A method of reading data written to an antifuse cell at the cell region A, according to an example embodiment, will be described in more detail below with reference toFIG. 6B.

Referring toFIG. 6B, in this example, the bitlines b2through b6may be in a floating state, and the bitline b1may be grounded. The wordlines w2through w6may be in a floating state, and a reading voltage Vs may be applied to the wordline w1to read data written to the antifuse in cell region A.

According to at least this example embodiment, each of the cells on the bitline b1may be selected and read simultaneously or concurrently.

According to at least some example embodiments, all or substantially all antifuse cells may be connected to each other using a single contact connected to either the bitlines b2through b6or the wordlines w2through w6, and thus, data may be written/read to/from all or substantially all antifuse cells simultaneously or concurrently.

FIGS. 7A and 7Bare diagrams for explaining methods of driving or operating antifuse structures according to other example embodiments. The methods shown inFIGS. 7A and 7Bmay be implemented in conjunction with the antifuse structures and/or antifuse array structures shown inFIGS. 2A,2B,3A, and/or3B.

Referring toFIGS. 7A and 7B, a plurality of bitlines b1through b6and a plurality of wordlines w1through w6may be formed to cross each other. Antifuse cells may be formed at the intersecting regions (intersections) of the bitlines b1through b6and the wordlines w1through w6. For example, the antifuse cell30shown inFIG. 3Amay be formed at a cell region B, and thus, a diode and a capacitor may be formed in series.

An example embodiment of a method for writing data to (programming) an antifuse cell at cell region B is described below with regard toFIG. 7A.

Referring toFIG. 7A, the bitlines b2through b6may be in a floating state, and the bitline b1may be grounded. The wordlines w2through w6may be in a floating state, and a writing voltage Vp may be applied to the wordline w1to write data to the antifuse cell.

According to at least this example embodiment, each of the cells on the bitline b1may be selected and programmed simultaneously or concurrently.

An example embodiment of a method of reading data written to the antifuse cell at the cell region B is described below with reference toFIG. 7B.

Referring toFIG. 7B, the bitlines b2through b6may be in a floating state, and the bitline b1may be grounded. The wordlines w2through w6may be in a floating state, and a reading voltage Vs may be applied to the wordline we to read data written in the antifuse cell at cell region B.

According to at least this example embodiment, each of the cells on the bitline b1may be selected and read simultaneously or concurrently.

According to example embodiments, all or substantially all antifuse cells may be connected by bitlines and wordlines, and thus, data may be written/read to/from all or substantially all antifuse cells simultaneously or concurrently because all or substantially all cells may be selected simultaneously or concurrently. Example embodiments may also provide a simpler antifuse structure.