An apparatus and associated method for writing data to a non-volatile memory cell, such as a resistive random access memory (RRAM) cell. In some embodiments, a control circuitry is configured to write a logic state to a resistive sense element while simultaneously verifying the logic state of the resistive sense element.

BACKGROUND

Data storage devices generally operate to store and retrieve data in a fast and efficient manner. Some storage devices utilize a semiconductor array of solid-state memory cells to store individual bits of data. Such memory cells can be volatile (e.g., DRAM, SRAM) or non-volatile (RRAM, STRAM, flash, etc.).

As will be appreciated, volatile memory cells generally retain data stored in memory only so long as operational power continues to be supplied to the device, while non-volatile memory cells generally retain data storage in memory even in the absence of the application of operational power.

In these and other types of data storage devices, it is often desirable to increase efficiency and accuracy during operation, particularly with regard to the reliability of writing data to a memory cell.

SUMMARY

Various embodiments of the present invention are generally directed to an apparatus and associated method for writing data to a non-volatile memory cell, such as a resistive random access memory (RRAM) cell.

In accordance with various embodiments, the apparatus generally comprises a control circuit configured to write a logic state to a resistive sense element while simultaneously verifying the logic state of the resistive sense element.

In other embodiments, the method generally comprises writing a logical state to a resistive sense element (RSE), and simultaneously verifying the written logical state of the RSE during the writing step.

These and various other features and advantages which characterize the various embodiments of the present invention can be understood in view of the following detailed discussion and the accompanying drawings.

DETAILED DESCRIPTION

FIG. 1provides a functional block representation of a data storage device100constructed and operated in accordance with various embodiments of the present invention. The device100includes a top level controller (CPU)102, an interface (I/F) circuit104and a non-volatile (NV) data storage array106. The I/F circuit104operates under the direction of the controller102to transfer data between the array106and a host device.

The data storage array106is formed from an array of non-volatile memory cells which store data in relation to programmable resistance states of the cells. Data are written to the cells as generally set forth inFIG. 2.

During a data write operation upon a selected memory cell110, a write power source112applies the necessary input such as in the form of a selected write current or voltage to configure the cell110to the desired state. In some embodiments, each cell stores a single logical bit value of 0 or 1. A relatively low programmed resistance, such as RL, can be used to denote a logical 0, and a relatively high programmed resistance, such as RH, can be used to denote a logical 1. In other embodiments, multiple resistance levels are provided which enables individual cells to store multiple bits. For example, four resistance levels (R1<R2<R3<R4) can be used to store two bits (e.g., a resistance of R1=00; R2=01; R3=10 and R4=11). More generally, the use of 2Nselectively programmable states can be used to store N bits of data.

A data read operation can be carried out as generally set forth byFIG. 3to read a previously written state of the cell110. A read power source114supplies an appropriate read bias current IRwhich is applied to the memory cell110. A voltage drop across the memory cell, VMC, will have a magnitude in relation to the programmed state of the cell. For example, using the single bit write operation illustrated inFIG. 2, VMCwill be generally proportional to IRRLwhen the cell110is programmed to the low resistance RL, and VMCwill be generally proportional to IRRHwhen the cell110is programmed to the high resistance RH.

The voltage VMCis sensed by a sense amplifier116, which compares the voltage VMCto a suitable reference voltage VREFfrom a reference voltage source118. If the reference voltage VREFhas a magnitude that falls between the respective high and low VMClevels, the sense amplifier will be able to reliably output a logic bit (0 or 1) that corresponds to the programmed state of the cell110.

A write-read-verify operation can be carried out when data are written to the cells110of the array106to ensure that the contents of the array accurately match the input data supplied thereto. A write-read-verify operation can be carried out by first writing the desired state to the cell110as shown inFIG. 2, and then following this with a read operation upon the cell110as shown inFIG. 3. If the input data are not correctly retained by the cell, the cell can be identified as having a defect and can be deallocated from the array. This helps to ensure data integrity.

While operable, a disadvantage of this approach is the penalty paid in the time required to carry out each data write operation, since the write operation cannot be declared completed until the data have been successfully read back. Those skilled in the art will appreciate that various factors, such as parasitic capacitances, can increase the time required to both write the data state to the cell, and to subsequently read the written state from the cell. This reduces the ability of the device100inFIG. 1to quickly transfer data from the host to the array106.

It will further be appreciated that devices such as100inFIG. 1can utilize a hierarchy of data caches and buffers between the host and the storage array (main memory)106. For example, local L1, L2 and L3 caches may be incorporated into the controller102to store data and instructions in fast accessible memory. One or more data buffers may be incorporated into the I/F circuitry104to store data pending transfer to or from the array106. The use of write-read-verify operations upon these caches and buffers can further help to ensure data integrity, but at the potential cost of additional reductions in overall data transfer rates.

Accordingly, as explained below various embodiments of the present invention operate to simultaneously read a memory cell during the writing of the data to the cell. This is generally carried out by sensing the transition in resistance of the cell from the write current as the desired state is written. This eliminates the need to follow up with a subsequent application of a read bias current to read the cell. Different reference voltages and/or different sense amplifiers may be switched in depending on which state is being written to the cell. In some embodiments, one or more of the sense amplifiers used during the simultaneous read operation can subsequently be used during normal read operations.

The simultaneous read operations presented herein can be applied to any number of different types of memory cells. Two exemplary cell constructions are set forth byFIGS. 4A and 4B.

FIG. 4Ashows the memory cell110configured as a spin-torque transfer random access memory (STRAM) cell. The memory cell110, also referred to herein as a unit cell, generally comprises a resistive sense element (RSE)120and a switching device122. In some embodiments, the RSE is characterized as a magnetic tunneling junction (MTJ), and the switching device is characterized as a metal oxide semiconductor field effect transistor (MOSFET).

The RSE120includes a fixed magnetic reference layer124and a free magnetic layer126separated by an intervening antiferromagnetic layer128. In some embodiments, the reference layer124comprises spin polarizing material that orients the spin of current passing through the MTJ in a predetermined direction. The magnetization direction of the reference layer124may be pinned to a separate layer (not shown) that maintains the reference layer in a specified magnetic orientation. In other embodiments, additional layers (not shown) can provide spin polarizing characteristics capable of injecting spin torque-transfer switching in the MTJ.

The free layer126is also formed of a suitable magnetic material, and is arranged so as to have selectively different magnetization directions which are established responsive to the application of suitable write currents. The intervening layer128can take any number of suitable constructions, such as Magnesium Oxide (MgO). While the respective magnetization directions are shown to be substantially perpendicular to the direction of write current, those skilled in the art will appreciate that other magnetic orientations, including parallel orientations, can be utilized as desired. Those skilled in the art will appreciate that additional layers, including seed layers, shield layers, and additional free and/or reference layers can be incorporated into the RSE120as desired, but such have been omitted for clarity.

A low resistance state for the RSE120inFIG. 4Acan be achieved when the magnetization of the free layer126is oriented to be substantially in the same direction (parallel) as the magnetization of the reference layer124. To orient the RSE120to a parallel (P) resistance state, a write current passes downwardly through the MTJ from a bit line (BL) to a source line (SL) so that the magnetization direction of the reference layer124sets the magnetic orientation of the free layer126.

A high resistance state for the RSE124is characterized as an anti-parallel orientation in which the magnetization direction of the free layer126is substantially opposite that of the reference layer124. To orient the RSE120in the anti-parallel (AP) resistance state, a write current passes upwardly through the MJT120from the SL to the BL. This write current sets the direction of magnetization of the free layer126so as to be opposite that of the reference layer124.

FIG. 4Bshows the memory cell110ofFIGS. 2 and 3with a resistive random access memory (RRAM) construction. As before, the cell110inFIG. 4Bincludes a resistive sense element (RSE)130in series with a switching device (MOSFET)132.

The RSE130inFIG. 4Bis formed from opposing electrode layers134,136which are separated by an intervening oxide layer138. Changes in RSE resistance are obtained by extending one or more electrically conductive metallization filaments (not shown) through the oxide layer from one electrode to the other electrode. The presence of the filaments lowers the overall characteristic resistance of the cell110.

The filaments are formed through the application of an appropriate voltage potential and/or current in the appropriate direction to promote metallization. Such filaments are subsequently retracted through the application of an appropriate write voltage potential and/or current in a different direction through the RSE.

It is contemplated that applying a suitable voltage across the RRAM cell110inFIG. 4Bfrom BL to SL will promote the formation of one or more filaments that extend from the top electrode layer134to the bottom electrode layer136. This will provide the RSE130with a low resistance RL. Applying a suitable voltage across the cell in the opposite direction from SL to BL will result in retraction of the filament(s), returning the RSE130to a high resistance RH.

The write current magnitude required to program a given RSE to a given programmed resistance state is generally inversely proportional to the write current pulse width. For example, the current magnitude to program the STRAM cell110inFIG. 4Acan be generally modeled by the following theoretical equation:
IC=ICO{1−((kT)/E)ln(τ/τ0)}  (1)
where ICis the critical switching current, which is the minimal current required for RSE resistance switching; ICOis the critical switching current at 0K; E is the magnetization stability energy barrier; τ is pulse duration time; and τ0is the inverse of the attempt frequency. From equation (1) it can be seen that for a smaller magnitude of applied switching current, generally a longer writing pulse will be required, and vice versa. It has been found that below around 10 ns, short time magnetization dynamics can dominate and the critical switching current can increase rapidly.

It has been found that the required write current magnitude for RSE switching ICcan vary from cell to cell and even from cycle to cycle. These cell-to-cell and cycle-to-cycle variations of IC(and/or the required write pulse width τ) may result in an unsuccessful write to the memory cell from time to time, leading to an associated reduction in performance for a data storage device.

Accordingly,FIG. 5provides a schematic representation of a control circuit140constructed and operated in accordance with various embodiments of the present invention. It is contemplated that the control circuit140represents at least portions of the array106ofFIG. 1, and utilizes a number of STRAM memory cells as set forth byFIG. 4A. Such is merely illustrative, however, and is not limiting.

The memory cells are individually denoted as110A,110B and110C, and are selectively accessed via a common bit line (BL)142, a common source line (SL)144, and respective word lines (WL0-2)146. The word lines WL0-2facilitate access to the individual memory cells through the application of a suitable voltage thereto, which serve to place the MOSFETs122into a drain-source conductive state. The orthogonal arrangements of the BL, SL and WLs inFIG. 5can be readily modified, including the use of a source plane for enhanced data density.

First and second current drivers are respectively denoted at148and150, with the first current driver selectively coupleable to the BL142and the second current driver selectively coupleable to the SL144. A sense amplifier152is used for read sensing during normal read operations, and a sense amplifier154is used for read sensing during write operations. A number of multiplexors (MUXs) are used to selectively connect the sense amplifiers152,154during these respective operations, as will now be explained.

A normal read operation is carried out upon a selected memory cell inFIG. 5, in this case cell110A, in accordance with the timing diagram ofFIG. 6. During the normal write operation, a write enable (WE) signal is held low, as shown at160inFIG. 6. The WE signal is applied to a mux162inFIG. 5, which connects the BL142to the normal read (NR) sense amplifier158.

A read enable (RE) signal is next asserted, as shown at164inFIG. 6, which directs a suitable read current from the driver148through the selected cell110A. Although not shown in the timing diagrams, it will be appreciated that this read operation includes assertion of the WL0146to place the MOSFET122into a drain-source conductive state.

A sense amplifier enable signal SANRis next asserted, as shown at166inFIG. 6, which enables the sense amplifier152to carry out a comparison of the voltage drop across the cell110A with a suitable reference voltage VREFfrom source168(FIG. 5). The sense amplifier152accordingly outputs a “normal read sense” logic state indicative of the programmed state of the cell110A; the output will be a logical 0 if the cell110A is programmed low, and the output will be a logical 1 if the cell110A is programmed high.

A write with read sense operation will next be described in accordance with the timing diagram ofFIG. 7. The diagram ofFIG. 7is divided into two portions. The first, left-most portion is generally indicative of various signals during the writing of a logical 1 (“write data1”) to the memory cell110A inFIG. 5. The second, right-most portion ofFIG. 7is generally indicative of various signals during the writing of a logical 0 (“write data0”) to the memory cell110A. Each of these different write operations will be discussed in turn.

In the configuration ofFIG. 5, it is contemplated that the writing of a logical 1 to the cell110A involves the application of a suitable write current upwardly through the cell from the driver150, so that the write current passes from the SL144to the BL142. To this end, the aforementioned write enable (WE) signal160inFIG. 6is initially asserted high. This disconnects the mux162inFIG. 5, taking the normal read sense amplifier152out of the circuit. It will be noted that the read enable (RE) signal164ofFIG. 6remains low throughoutFIG. 7.

The high WE signal160asserts a mux170inFIG. 5which is coupled to the BL142as shown. A current pulse, referred to herein as a write/read or WR pulse, is generally represented at172inFIG. 7, and corresponds to the application of the write current from the driver150. The actual duration and shape of the write current pulse can vary depending on the requirements of a given application, so the WR pulse172generally serves to indicate the application of such current during some or all of the assertion of the WE signal160.

FIG. 7further shows a WRITE1signal174, which is asserted high when the data to be written is a logical 1. The WRITE1signal174remains low when the data to be written is a logical 0. Upstream circuitry (not separately shown inFIG. 5) can be used to detect the written state and assert the WRITE1signal accordingly.

The WRITE1signal, and its complement, are respectively supplied to muxs176,178inFIG. 5. These muxs respectively connect the appropriate control path (BL or SL) to the sense amplifier154. In some embodiments, the sense amplifier154can be configured to detect an actual transition in programmed resistance as it occurs, or can be switched in to detect the transition immediately after it occurs. In either case, the sensing occurs simultaneously with the write since the voltage drop sensed by the sense amplifier154is generated by the write current used to set the programmed state of the cell, rather than by a subsequently applied read current. It is contemplated that in many cases, the simultaneous read sensing of the written state can occur within a single clock cycle of the write circuit.

As noted above, it is contemplated that different reference voltages may be required to sense a transition from 0 to 1 as compared to a transition from 1 to 0. To this end,FIG. 5additionally provides muxs180and182, which are responsive to the WRITE1signal174(and its complement) to respectively connect first and second reference voltages VREF0and VREF1from sources184and186. During the writing of a logical 1, the mux182is asserted so that the VREF1voltage is supplied to the sense amplifier154. A write/read sense enable signal (SAWR)188inFIG. 7is asserted to enable the sense amplifier154to carry out this comparison. If the writing operation is successful, the resulting output of the sense amplifier154will match the written state, that is, a logical 1. The sense amplifier154is thus used to verify the write operation.

The writing of a logical 0 to the cell110A is carried out in similar fashion. It is contemplated in the circuit140ofFIG. 5that a write current to write a logical 0 will pass from the current driver148and downwardly through the cell110A from the BL142to the SL144. The various signals ofFIG. 7will be asserted as described above, resulting in the voltage drop across the cell from the write current being sensed by the sense amplifier154and compared to the reference voltage VREF0. As before, the writing operation is verified as successful if the output of the sense amplifier154is a logical 0.

FIG. 8displays a flow diagram of a WRITE OPERATION WITH SIMULTANEOUS READ routine200to summarize the foregoing discussion.

A write operation is carried out at step202that involves writing a selected logic state to the RSE of a selected non-volatile memory cell, such as the RSE120of cell110A inFIG. 5. When writing the selected logical state, the bit line voltage or the source line voltage will change when the state of the RSE switches. In step204, a sense amplifier verifies the correct logic state was written to the RSE during the writing operation by comparing the post-write bit line and/or source line voltage with a suitable reference voltage. A skilled artisan can appreciate that the reference voltage could be different between writing a logic state “0” and “1”. Thus, one or more muxs may be needed to select the corresponding reference voltage. A verification step is indicated by decision step206. Upon verification of the logic state in step204, the routine either moves on to the next write operation, as indicated by decision step208, or ends at step210.

In the event that the correct logic state was not written to the RSE, as shown by decision step212the circuit can make a determination whether to attempt a rewrite of the logic state, step214, or to mark the cell as defective, step216. In certain applications, a defective mark at step216can result in a new set of cells being allocated for the writing of the input data, and subsequent analysis of the marked cell can be carried out to determine whether the marked cell should be permanently deallocated from use.

As can be appreciated by one skilled in the art, the various embodiments illustrated herein provide advantages over the prior art. The simultaneous verification of written data during the write operation can enhance data throughput rates and reduce power consumption because separate read currents are not required to carry out read verify operations. It will be appreciated that the various embodiments discussed herein have numerous potential applications and are not limited to a certain field of electronic media or type of data storage devices.

For purposes of the appended claims, the term “simultaneous” and the like will be construed consistent with the foregoing discussion to describe a read sense verification that occurs during or immediately following a write state transition and uses a voltage drop generated by the write current used to induce such transition without the need to apply a separate read current to subsequently verify the written state.