Solar cells having hybrid architectures including differentiated P-type and N-type regions

A solar cell, and methods of fabricating said solar cell, are disclosed. The solar cell can include a substrate having a light-receiving surface and a back surface. The solar cell can include a first semiconductor region of a first conductivity type disposed on a first dielectric layer, wherein the first dielectric layer is disposed on the substrate. The solar cell can also include a second semiconductor region of a second, different, conductivity type disposed on a second dielectric layer, where a portion of the second thin dielectric layer is disposed between the first and second semiconductor regions. The solar cell can include a third dielectric layer disposed on the second semiconductor region. The solar cell can include a first conductive contact disposed over the first semiconductor region but not the third dielectric layer. The solar cell can include a second conductive contact disposed over the second semiconductor region, where the second conductive contact is disposed over the third dielectric layer and second semiconductor region. In an embodiment, the third dielectric layer can be a dopant layer.

BACKGROUND

Photovoltaic (PV) cells, commonly known as solar cells, are devices for conversion of solar radiation into electrical energy. Generally, solar radiation impinging on the surface of, and entering into, the substrate of a solar cell creates electron and hole pairs in the bulk of the substrate. The electron and hole pairs migrate to p-doped and n-doped regions in the substrate, thereby creating a voltage differential between the doped regions. The doped regions are connected to the conductive regions on the solar cell to direct an electrical current from the cell to an external circuit. When PV cells are combined in an array such as a PV module, the electrical energy collected from all of the PV cells can be combined in series and parallel arrangements to provide power with a certain voltage and current.

DETAILED DESCRIPTION

Efficiency is an important characteristic of a solar cell as it is directly related to the capability of the solar cell to generate power. Likewise, efficiency in producing solar cells is directly related to the cost effectiveness of such solar cells. Accordingly, techniques for increasing the efficiency of solar cells, or techniques for increasing the efficiency in the manufacture of solar cells, are generally desirable. Some embodiments of the present disclosure allow for increased solar cell manufacture efficiency by providing novel processes for fabricating solar cell structures. Some embodiments of the present disclosure allow for increased solar cell efficiency by providing novel solar cell structures.

“Comprising.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or steps.

“Configured To.” Various units or components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the units/components include structure that performs those task or tasks during operation. As such, the unit/component can be said to be configured to perform the task even when the specified unit/component is not currently operational (e.g., is not on/active). Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, sixth paragraph, for that unit/component.

“First,” “Second,” etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, reference to a “first” semiconductor region does not necessarily imply that this semiconductor region is the first semiconductor region in a sequence; instead the term “first” is used to differentiate this semiconductor region from another semiconductor region (e.g., a “second” semiconductor region). As used herein, a semiconductor region can be a polycrystalline silicon emitter region, e.g., a polycrystalline silicon doped with a P-type or an N-type type dopant. In one example, a first semiconductor region can be a first polycrystalline silicon emitter region, where multiple polycrystalline emitter regions can be formed (e.g., a second polycrystalline silicon emitter region).

“Coupled”—The following description refers to elements or nodes or features being “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element/node/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically.

Methods of fabricating solar cell semiconductor regions and the resulting solar cells, are described herein. In the following description, numerous specific details are set forth, such as specific process flow operations, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known fabrication techniques, such as lithography and patterning techniques, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

FIG.1illustrates a cross-sectional view of a portion of a solar cell100, according to some embodiments. In an embodiment, the solar cell100can include a substrate106having a front side102and a back side104, the front side102opposite the back side104. In some embodiments, the front side102can be referred to as a front surface and the back side104can be referred to as a back surface. In an embodiment, the front side can have a texturized surface. A texturized surface130may be one which has a regular or an irregular shaped surface for scattering incoming light, decreasing the amount of light reflected off the light-receiving and/or exposed surfaces of the solar cell100.

Referring again toFIG.1, in one embodiment, the solar cell100can include a first dielectric layer114disposed on the back side104of the substrate106. In some embodiments, the first dielectric layer114can be referred to as a first thin dielectric layer. In an example, the first dielectric layer114can be a thin oxide layer such as a tunnel dielectric layer (e.g., tunnel oxide, silicon oxynitride, silicon oxide). In an embodiment, the first dielectric layer114can have a thickness of approximately 2 nanometers or less.

Referring again toFIG.1, in an embodiment, the solar cell100can include a first semiconductor region108disposed on the first dielectric layer114. In one embodiment, the first semiconductor region108can be a first polycrystalline silicon emitter region. In an embodiment, the first semiconductor region can include a first conductivity type. In an example, first semiconductor region108can be a first polycrystalline silicon emitter region of a first conductivity type. In a specific embodiment, the first conductivity type is N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In some embodiments, the first conductivity type can be P-type (e.g., formed using boron).

Referring again toFIG.1, in an embodiment, the solar cell100can include a second dielectric layer120disposed on the back side104of the substrate106. In an embodiment, the second dielectric layer120can be partially disposed116,118on portions117,115of the first semiconductor region108. In some embodiments, the second dielectric layer120can be referred to as a second thin dielectric layer. In an example, the second dielectric layer120can be a thin oxide layer such as a tunnel dielectric layer (e.g., tunnel oxide, silicon oxynitride, silicon oxide). In an embodiment, the second dielectric layer120can have a thickness of approximately 2 nanometers or less.

Referring again toFIG.1, in an embodiment, the portions116,118can instead be referred to as another dielectric layer (e.g., a third, fourth or fifth dielectric layer, etc.). In one embodiment, the portions116,118can be portions of the second dielectric layer120. In an embodiment, the portions116,118can instead be a separate and distinct layer different from the second dielectric layer120. In an embodiment, the portions116,118can instead be portions of the first dielectric layer114. In an example, the portions116,118can be the same or a different, distinct layer, from the first dielectric layer114and/or the second dielectric layer120. In some embodiments, the first dielectric layer114and the second dielectric layer120can be different and distinct layers. In an embodiment, the first dielectric layer114and the second dielectric layer120can be the same dielectric layer. In an example, the first dielectric layer114and the second dielectric layer120can be a single continuous dielectric layer. In one example, the first dielectric layer114, the second dielectric layer120, and layers116,118can be a single continuous dielectric layer.

Referring still again toFIG.1, in an embodiment, the solar cell100can include a second semiconductor region112disposed over the back side of the solar cell100. In an embodiment, the second semiconductor region112can be disposed on the second dielectric layer120. In an embodiment, the second semiconductor region112can be a second polycrystalline silicon emitter region. In an embodiment, the second semiconductor region112can include a second conductivity type. In an example, second semiconductor region112can be a second polycrystalline silicon emitter region of a second conductivity type. In a specific embodiment, the second conductivity type is P-type (e.g., formed using boron impurity atoms). In an embodiment, the second conductivity type can be N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In one embodiment, the second dielectric layer120can include a portion which is disposed over118an outer portion117of the first semiconductor region108. In an embodiment, the second dielectric layer120can include a portion disposed laterally116over a lateral portion115of the first semiconductor region108. In one embodiment, portions118,116of the second dielectric layer120can be between the first semiconductor region108and second semiconductor region112. In an example, the dielectric layers116,118can be a boundary for the metallurgical junction between first semiconductor region108from second semiconductor region112. In one example, the dielectric layer116can be a boundary for the metallurgical junction between the first semiconductor region108from second semiconductor region112(e.g., without dielectric layer118). In some embodiments, the second semiconductor region is a pre-doped polycrystalline silicon emitter region. In one such embodiment, the second semiconductor region is formed having a specific conductivity type (e.g., p-type or n-type).

Referring again toFIG.1, in an embodiment, a third dielectric layer125can be disposed on the second semiconductor region112. In an embodiment, the third dielectric layer can be a dopant layer. In one embodiment, the dopant layer can have a second conductivity type. In an embodiment, the dopant layer is of the same conductivity type as the second semiconductor region112. In an example, the dopant layer is N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In an embodiment, the dopant layer can be P-type (e.g., formed using boron impurity atoms). In an embodiment, a portion of the second semiconductor region112and the dopant layer125can be disposed between the first and second conductive contacts128,129. In some embodiments, the second semiconductor region112and the dopant layer125can be aligned with an edge of the insulating layer110. In an embodiment, the third dielectric layer125can be a non-continuous layer (e.g., as shown inFIG.1). In an example, the third dielectric layer125can be broken into discreet portions and can still be referred to as a single dielectric layer or dopant layer. In some embodiments, the third dielectric layer need not be formed (e.g., where the second semiconductor region includes a pre-doped polycrystalline emitter region). In one embodiment, the third dielectric layer125can include silicon oxide, silicon oxynitride and silicon nitride. In an embodiment, the third dielectric layer125can include an insulator and/or an insulating material.

Referring again toFIG.1, in an embodiment, the solar cell100can further include an insulating region110disposed on the first semiconductor region108. In one example, the insulating region110can be a silicon dioxide.

Referring again toFIG.1, in an embodiment, the solar cell100can include a first conductive contact128disposed over the first semiconductor region108. In an embodiment, the first conductive contact128can be disposed through the insulating region110, as is depicted inFIG.1. In one embodiment, the first conductive contact128is disposed through a contact hole121in the insulating region110.

In an embodiment, a second conductive contact129can be disposed over the second semiconductor region112. In one embodiment, the second conductive contact129is disposed through the third dielectric layer125. In an embodiment, the second conductive contact129is disposed through a contact hole123in the third dielectric layer125.

In one embodiment, the first and second conductive contacts128,129can include a plated metal. In an example, the first and second conductive contacts128,129can include copper, tin, titanium, tungsten, and/or nickel, among other metals. In some embodiments, the first and second conductive contacts128,129can include a deposited metal or a metal foil. In an example, the first and second conductive contacts128,129can include aluminum or aluminum foil. In an embodiment, the first and second conductive contacts128,129can include a wire, a thermally compressed wire and/or an aluminum wire.

In one embodiment, a portion124of the second semiconductor region112and/or third dielectric layer125can be disposed between the first conductive contact128and second conductive contact129. In some embodiments, the second semiconductor region112and third dielectric layer125can instead be laterally aligned to the second conductive contact129, e.g., not extending from the second conductive contact129in contrast to that shown inFIG.1. In one embodiment, the second semiconductor region112and third dielectric layer125may not be aligned. In an example, at the portion124, the second semiconductor region112can extend further from the second conductive contact129than third dielectric layer125. In an embodiment, as shown at124, the second conductive contact129can be formed over the first semiconductor region108and the second semiconductor region112. In contrast, in some embodiments, the second conductive contact129can be formed over the second semiconductor region112only. In an embodiment, the second conductive contact139can be formed over the third dielectric layer125and the second semiconductor region112.

Referring once again toFIG.1, in an embodiment, the solar cell100further can include a fourth dielectric layer132disposed on the front side102. In an embodiment the fourth dielectric layer132can be an anti-reflective coating (ARC) layer. In an example, the layer132can include silicon nitride. In an embodiment, the fourth dielectric layer132can include silicon oxide. In an example, an oxide layer (e.g., a tunnel oxide) can be formed on the front side102. In an embodiment, a silicon layer can be disposed over the fourth dielectric layer132(e.g., over the oxide layer). In an example, the silicon layer can include amorphous silicon and/or polycrystalline silicon. In an embodiment, an antireflective layer can be disposed over the silicon layer (e.g., silicon nitride).

Referring again toFIG.1, in some embodiments, the first semiconductor region108can be a N-type polycrystalline silicon emitter region. In one embodiment, the second semiconductor region112can be a P-type polycrystalline silicon emitter region. In an embodiment, the substrate106can be a N-type monocrystalline silicon substrate. In some embodiments, the second semiconductor region112can be a P-type polycrystalline silicon emitter region. In an embodiment, the substrate106can be a P-type monocrystalline silicon substrate. In an embodiment, the first dielectric layer114, the second dielectric layer120and the third dielectric layer125can include silicon oxide. In an embodiment, insulating region110includes silicon dioxide. In an embodiment where the third dielectric layer125can include a dopant layer, the dopant layer125can include phosphorus or boron.

Referring again toFIG.1, in an embodiment, the first conductive contact and/or second conductive contact128,129can include a deposited metal. In an embodiment, the deposited metal can be an aluminum-based. In one such embodiment, the aluminum-based deposited metal can have a thickness approximately in the range of 0.3 to 20 microns and include aluminum in an amount greater than approximately 97% and silicon in an amount approximately in the range of 0-2%. In an example, the aluminum-based deposited metal can include copper, titanium, titanium tungsten, nickel, and/or aluminum, among other metals. In an embodiment, the aluminum-based deposited metal is formed from a blanket deposition process. In an embodiment, the aluminum-based deposited metal can be a metal seed layer. In some examples, the deposited metal can be a deposited aluminum. In one embodiment, each of the first conductive contact128and the second conductive contact129can include copper, tin, nickel, and/or aluminum, among other metals.

Referring once again toFIG.1, in some embodiments, the first and/or second conductive contacts128,129each include a metal foil. In an embodiment, the metal foil is an aluminum (Al) foil having a thickness approximately in the range of 5-100 microns. In one embodiment, the Al foil is an aluminum alloy foil including aluminum and second element such as, but not limited to, copper, manganese, silicon, magnesium, zinc, tin, lithium, or combinations thereof. In one embodiment, the Al foil is a temper grade foil such as, but not limited to, F-grade (as fabricated), O-grade (full soft), H-grade (strain hardened) or T-grade (heat treated). In one embodiment, the aluminum foil is an anodized aluminum foil. In another embodiment, the aluminum foil is not anodized.

Referring still again toFIG.1, in an embodiment, first and/or second conductive contacts128,129each include a conductive wire. In an embodiment, the conductive wire can include an electrically conducting material (e.g., a metal such as aluminum, copper or another suitable conductive material, with or without a coating such as tin, silver, nickel or an organic solderability protectant). In an example, the conductive wires can be bonded to the first and second semiconductor regions by a thermocompression bonding, ultrasonic bonding, or thermosonic bonding process. In an example, the conductive wires can include aluminum wires.

Turning toFIG.2, a flowchart200illustrating a method for fabricating a solar cell is shown, according to some embodiments. In various embodiments, the method described inFIG.2can include additional (or fewer) blocks than illustrated.

Referring to operation202of flowchart200, a method of fabricating a solar cell can include performing a texturization process on the front side of the substrate. In an example, a hydroxide-based wet etchant can be used to form a texturized surface on the front side of the substrate. It is to be appreciated, however, that the texturizing of the front side may be omitted from the process flow. In an embodiment, prior to or within the same or a single process step of the texturization process, the substrate can be cleaned, polished, planarized and/or thinned. In an example, a wet chemical clean process can be performed prior and/or subsequent to the texturization process. Although, as shown, the texturization process can be performed at the start of the fabrication process, in another embodiment, the texturization process can be performed at another step in the fabrication process. In an example, the texturization process can instead be performed subsequent to a patterning process. In one example, the texturization process can be performed prior to a thermal process. In one such example, the texturization process can be performed subsequent to a patterning (e.g., patterning of polycrystalline silicon regions) and prior to a thermal process.

In an embodiment, although operation202is shown to be performed prior to operation204, operation202can also be performed in the middle or at the end of the method described herein. For example, operation202can be performed subsequent to operation208. In one example, operation202can be performed after operation210and prior to operation212. In an embodiment, operation202can be performed at the beginning, middle, end or at any other time in the process described in flow chart202.

Referring to operation204of flowchart200, a method of fabricating a solar cell can include forming a first dielectric layer on the back side of the substrate. In an embodiment, the first dielectric layer can be formed in an oxidation process and is a thin oxide layer such as a tunnel dielectric layer (e.g., silicon oxide). In one embodiment, the first dielectric layer can be formed in a deposition process. In an embodiment, the first dielectric layer is a thin oxide layer (e.g., silicon oxide) or silicon oxynitride layer. In an embodiment, forming the first dielectric layer can include forming the first dielectric layer at a thickness of approximately 2 nanometers or less. In an example, a thermal process or oven can be used to grow the first dielectric layer. As used herein, the first dielectric layer can also be referred to as a first thin dielectric layer.

Referring to operation206of flowchart200, a method of fabricating a solar cell can include forming a first semiconductor region on the first dielectric layer. In an embodiment, forming a first semiconductor region can include forming a first polycrystalline silicon emitter region. In an embodiment, forming a first semiconductor region can include forming a first silicon layer on the first dielectric layer, forming an insulator layer over the first silicon layer and, subsequently, patterning the first silicon layer, insulator layer and first dielectric layer to form an insulating region and the first semiconductor region (e.g., a first polycrystalline silicon emitter region having an insulating region thereon). Further detail in operations for forming a first semiconductor region are shown in the flowchart300ofFIG.3below. In an embodiment, the operation204and206can be performed in the same process step or at different, e.g., separate, process steps.

Referring to operation208of flowchart200, a method of fabricating a solar cell can include forming a second dielectric layer on portions of the first semiconductor region and on portions of the substrate. In an embodiment, the second dielectric layer can be formed in an oxidation process and is a thin oxide layer such as a tunnel dielectric layer (e.g., silicon oxide). In one embodiment, the second dielectric layer can be formed in a deposition process. In an embodiment, the second dielectric layer is a thin oxide layer (e.g., silicon oxide) or silicon oxynitride layer. In an embodiment, the second dielectric layer can have a thickness of approximately 2 nanometers or less. In an example, forming the second dielectric layer on portions of the first semiconductor region and portions of the substrate can include forming the second dielectric layer on exposed portions of the first semiconductor region and on exposed portions of the substrate. In one example, the exposed regions of the first semiconductor region and the substrate can be formed after a patterning process performed at the operation of206. As used herein, the second dielectric layer can also be referred to as a second thin dielectric layer.

Referring again to operation208of flowchart200, in an embodiment, forming the second dielectric layer on portions of the first semiconductor region can instead include forming a separate, different and/or distinct dielectric layer on portions of the first semiconductor region. In an example, forming the second dielectric layer on portions of the first semiconductor region can include forming another dielectric layer on portions of the first semiconductor region. In an embodiment, this dielectric layer can be referred to as a fourth or a fifth dielectric layer.

Referring to operation210of flowchart200, a method of fabricating a solar cell can include forming a second semiconductor region over a back side of a substrate. In an embodiment, forming second semiconductor region over a back side of a substrate includes forming the second semiconductor region on or over the second dielectric layer. Forming the second semiconductor region can include forming a second silicon layer on or over the second dielectric layer, forming a third dielectric layer over the second silicon layer, patterning the second silicon layer, third dielectric layer and second dielectric layer and, subsequently performing a thermal process to drive dopants from the dopant layer to the second silicon layer to form the second semiconductor region. In an embodiment, as described herein, the third dielectric layer can include a dopant layer, where patterning the second silicon layer, third dielectric layer and second dielectric layer can include patterning the second silicon layer, dopant layer and second dielectric layer. Further detail in operations for forming a second semiconductor region are shown in the flowchart400ofFIG.4below.

Referring to operation212of flowchart200, a method of fabricating a solar cell can include forming conductive contact structures over the first semiconductor region and the second semiconductor region. In an embodiment, forming the conductive contact structures can include performing a sputtering process, locally depositing a metal, a blanket deposition process, a plating process, bonding a metal foil and/or bonding wires to first and the second semiconductor regions. In an example, the conductive contact structures can include a locally deposited aluminum, aluminum foil and/or an aluminum wire. In an embodiment, the conductive contact structures can include one or more metals and/or metal alloys. In an example, the conductive contact structures can include aluminum, titanium tungsten and/or copper, among other metals. In an embodiment, the conductive contact structures can include one, two or more layers of metal. In an example, the conductive contact structures can include a metal seed layer. In an embodiment, the metal seed layer can include a first layer including copper, a second layer including tungsten and a third layer including aluminum.

Referring again to operation212of flowchart200, a method of fabricating a solar cell can include patterning an insulating region and a third dielectric layer (e.g., a dopant layer) to expose portions of the first and second semiconductor emitter regions, where a first conductive contact and second conductive contact can be electrically connected to the exposed portions to first semiconductor region and second semiconductor region, respectively. Further detail in operations for forming conductive contact structures over the first and second semiconductor regions are shown in the flowchart500ofFIG.5.

Referring toFIG.3, a flowchart300illustrating operations in forming a first semiconductor region is shown, according to some embodiments. In various embodiments, the method described inFIG.3can include additional (or fewer) blocks than illustrated. Although one embodiment for forming a first semiconductor region (e.g., first polycrystalline emitter region) is shown below, other operations can be used. In an example, in contrast to the operations of flowchart300, a screen printing, inkjet printing or any other process for directly depositing a patterned silicon can used to form the first semiconductor region.

Referring to operation302of flowchart300, forming a first semiconductor region can include forming a first silicon layer on a first dielectric layer. In an embodiment, the first dielectric layer is formed over a back side of a substrate (e.g., a silicon substrate). In one embodiment the first dielectric layer is a thin oxide layer. In an embodiment, the first silicon layer can be deposited over the first dielectric layer. In one example, a low pressure chemical vapor deposition process can be used to deposit the first silicon layer over the first dielectric layer. In an embodiment, the first silicon layer is grown on the first dielectric layer in a thermal process and/or an oven. In one embodiment, the first dielectric layer and the first silicon layer can be formed (e.g., grown) in the same or in a single oven and/or in the same or single process step. In some embodiments, the first dielectric layer and the first silicon layer can be formed on the back side, the front side and/or side edges of the substrate, where, in a subsequent patterning (e.g., operation306) or cleaning process can be performed to remove the first dielectric layer and the first semiconductor layer from the front side and/or side edges of the substrate.

Referring again to operation302of flowchart300, forming a first semiconductor region can include, in an embodiment, forming a first silicon layer having a first conductivity type. In an example, forming the first silicon layer can include growing an N-type silicon layer over the first dielectric layer (e.g., a thin oxide layer). In other embodiments, the first silicon layer can be a P-type silicon layer. In an embodiment, the first silicon layer is an amorphous silicon layer. In one such embodiment, the amorphous silicon layer is formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). In an embodiment, the first silicon layer can be an amorphous silicon and/or polycrystalline silicon. In an embodiment, the first silicon layer is grown on the first dielectric layer in a thermal process and/or an oven. In one embodiment, the first dielectric layer and the first silicon layer can be grown in the same or single oven and/or in the same or single process step.

Referring once again to operation302of flowchart300, in another embodiment, the first silicon layer can be formed undoped. In one such embodiment, a dopant layer can be formed on the first silicon layer and a thermal process can be performed to drive dopants from the dopant layer into the first silicon layer resulting in a first silicon layer having a first conductivity type (e.g., n-type or p-type).

Referring to operation304of flowchart300, forming a first semiconductor region can include forming an insulator layer on the first silicon layer. In an embodiment the insulator layer can include silicon dioxide. In an example, a blanket deposition process can be performed to form the insulator layer. In an embodiment, the insulator layer can be formed to a thickness less than or equal to approximately 1000 Angstroms.

Referring to operation306of flowchart300, the insulator layer, first silicon layer and first dielectric layer can be patterned to form a first semiconductor region. In an embodiment, the first semiconductor region can have an insulating region formed over the first semiconductor region. In an embodiment, the insulating region can be formed from the patterning the insulator layer of operation304. In an embodiment, a lithographic or screen print masking and subsequent etch process can be used to pattern the insulator layer and the first silicon layer. In another embodiment, a laser ablation process (e.g., direct write) can be used to pattern the insulator layer, the first silicon layer and/or the first dielectric layer.

Referring toFIG.4, a flowchart400illustrating operations in forming a second semiconductor region is shown, according to some embodiments. In various embodiments, the method described inFIG.4can include additional (or fewer) blocks than illustrated. Although one embodiment for forming a second semiconductor region (e.g., second polycrystalline emitter region) is shown below, other operations can be used. In an example, in contrast to the operations of flowchart400, a screen printing, inkjet printing or any other process for directly depositing a patterned silicon can used to form the second semiconductor region.

Referring to operation402of flowchart400, forming a second semiconductor region can include forming a second silicon layer over a back side of the substrate. In an embodiment, forming the second silicon layer over the back side of the substrate can include forming the second silicon layer on a second dielectric layer and an insulating region disposed on the back side of the substrate. In an embodiment, the second dielectric layer is formed from the operations as described above in flowchart200and300. In one embodiment the second dielectric layer is a thin oxide layer. In one embodiment, the second silicon layer can be deposited over the second dielectric layer. In one example, a low pressure chemical vapor deposition process (LPCVD) or a plasma enhanced chemical vapor deposition (PECVD) can be used to deposit the second silicon layer over the second dielectric layer. In an embodiment, the second silicon layer can be a polycrystalline silicon. In an embodiment, the second silicon layer is grown on the second dielectric layer in a thermal process and/or an oven. In one embodiment, the second dielectric layer and the second silicon layer can be grown in the same or single oven and/or in the same or single process step. In an embodiment, the second silicon layer can be formed undoped. In an embodiment, the second silicon layer is an amorphous silicon layer. In one such embodiment, the amorphous silicon layer is formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

Referring again to operation402of flowchart400, in another embodiment, forming a second semiconductor region can include forming a second silicon layer having a second, different, conductivity type from the first semiconductor region. In one such example, forming the second silicon layer can include forming a pre-doped silicon layer. In one example, forming the second silicon layer can include growing a p-type silicon layer over the second dielectric layer (e.g., a thin oxide layer).

Referring again to operation402of flowchart400, the second dielectric layer and the second silicon layer can be formed on the back side, the front side and/or side edges of the substrate, where, in a subsequent patterning or cleaning process (e.g., operation406) can be performed to remove the second dielectric layer and the second semiconductor layer from the front side and/or side edges of the substrate.

Referring to operation404of flowchart400, forming a second semiconductor region can include forming a third dielectric layer on the second silicon layer. In an embodiment, the third dielectric layer can include a dopant layer. In one such embodiment, the dopant layer can have a second conductivity type. In one embodiment, the second conductivity type can be P-type. In one example, the dopant layer can be a layer of boron. In some embodiments, the second conductivity type can be N-type (e.g., a layer of phosphorus). In an embodiment, a deposition process can be performed to form the third dielectric layer (e.g., dopant layer). In one example, a low pressure chemical vapor deposition process can be used to deposit the third dielectric layer over the second silicon layer. In one embodiment, the third dielectric layer can include silicon oxide or silicon oxynitride. In an embodiment, the third dielectric layer can include an insulator and/or an insulating material.

Referring to operation406of flowchart400, forming a second semiconductor region can include patterning the dopant layer and second silicon layer to form a second semiconductor region. In an embodiment, a lithographic or masking (e.g., screen printing, inkjet printing) and, subsequent to masking, an etch process can be used to pattern the dopant layer, second silicon layer and second thin dielectric layer. In another embodiment, a laser process (e.g., laser ablation, direct write, etc.) can be used in the patterning. In one embodiment, the patterning can also include etching process (e.g., wet chemical etching). In some embodiments, the patterning can also include a subsequent cleaning process. In an embodiment, the patterning can form a second semiconductor region of a second conductivity type (e.g., P-type). In some embodiments, the patterning or operation406need not be performed.

Referring to operation408of flowchart400, where the third dielectric layer can include a dopant layer, forming a second semiconductor region can include performing a thermal process to drive dopants from the dopant layer to the second silicon layer. In an embodiment, the second conductivity type can be P-type. In one example, the dopant layer can be a layer of boron. In an example, the thermal process can include heating to a temperature approximately greater than or equal to 900 degrees-C to drive dopants from dopant layer to the second silicon layer. In some embodiments, the patterning or operation406can be performed subsequent to the thermal process or operation408. In some embodiments, e.g., where the silicon layer is pre-doped or formed including a n-type or p-type conductivity type, the thermal process need not be performed.

Referring toFIG.5, a flowchart500illustrating operations in forming conductive contact structures over a first and second semiconductor regions are shown, according to some embodiments. In various embodiments, the method described inFIG.5can include additional (or fewer) blocks than illustrated.

Referring to operations502of flowchart500, forming a conductive contact structures over the first and second semiconductor regions can include patterning an insulating region and a third dielectric layer formed over the first and second semiconductor regions, respectively (e.g., as shown in flowcharts200,300and400above). In an embodiment, patterning the insulating region and a third dielectric layer forms contact holes through the insulating region and the third dielectric layer. In an embodiment, the contact holes can be formed using a mask and etching process. In an example, a mask can be formed and a subsequent wet chemical etching process can be performed to form the contact holes. In some embodiments, a wet chemical cleaning processes can be performed to remove the mask. In one embodiment, the patterning can include performing a laser patterning process (e.g., laser ablation) to form contact holes in the insulating region and the third dielectric layer. In one embodiment the patterning process for forming contact holes in the insulating region and third dielectric layer can be performed in the same or single step (e.g., using a laser in a same or a single laser processing chamber) or, alternatively, can be performed separately (e.g., separate laser patterning processes can be used to form contact holes in the insulating region and third dielectric layer). In an embodiment, where the third dielectric layer can include a dopant layer, the patterning can include patterning the insulating region and the dopant layer to form contact holes through the insulating region and dopant layer in a single step or performed separately.

Referring to operations504of flowchart500, forming a conductive contact over a first semiconductor regions can include forming a first conductive contact over a first semiconductor region. In an example, forming the forming a first conductive contact over a first semiconductor region can include forming a first conductive contact on a first polycrystalline silicon emitter region. In an embodiment, the first semiconductor region (e.g., first polycrystalline silicon emitter region) can have a first conductivity type (e.g., N-type). In an embodiment, the first conductive contact can be formed by one or more metallization processes. In an embodiment, the first conductive contact can have the same conductivity type as the first semiconductor region. In an example, the first conductive contact can be a N-type metal contact and the conductivity type of the first semiconductor region can be N-type. In another example, the first conductive contact can be a P-type metal contact and the conductivity type of the first semiconductor region can be P-type.

Referring to operations506of flowchart500, forming a conductive contact over a second semiconductor regions can include forming a second conductive contact over a second semiconductor. In an example, forming the forming a second conductive contact over a second semiconductor region can include forming a second conductive contact on a second polycrystalline silicon emitter region. In an embodiment, the second semiconductor region (e.g., second polycrystalline silicon emitter region) can have a second conductivity type (e.g., P-type). In an embodiment, the second conductive contact can be formed by one or more metallization processes. In an embodiment, the second conductive contact can have the same conductivity type as the second semiconductor region. In an example, the second conductive contact can be a P-type metal contact and the conductivity type of the second semiconductor region can also be P-type. In another example, the second conductive contact can be a N-type metal contact and the conductivity type of the second semiconductor region can be N-type.

Referring again to operations504,506of flowchart500, forming the first and second conductive contacts can include performing a sputtering process, locally depositing a metal, a blanket deposition process, a plating process, bonding a metal foil and/or bonding wires to form a first and the second semiconductor regions (e.g., as described above). In an example, the first and second conductive contacts can include a locally deposited aluminum, aluminum foil and/or an aluminum wire. In one embodiment, a thermal compression process can be used to electrically connect the first and second conductive contacts to the first and second semiconductor regions (e.g., (e.g., first and second polycrystalline silicon emitter region). In an example, a thermal compression process can be used to adhere a wire or a plurality of wires to the first and second semiconductor regions. In one embodiment, a metal foil can be bonded (e.g., welded) to the first and semiconductor regions. In an embodiment, forming the first and second conductive contacts can include performing a blanket deposition process. In an example, forming the first and second conductive contacts can include performing an electroplating process. In some examples, forming the first and second conductive contacts can include performing a blanket deposition process to form a metal seed layer. In the same example, a plating process can be subsequently performed to plate metals to the metal seed layer. In the same example, a patterning process can be performed after forming the metal seed layer and performing the plating process to form the first and second conductive contacts.

Referring again to operations504,506of flowchart500, the methods described above can be used in the operations of504and506separately or in a same or single process step. In an example, forming the first and second conductive contacts using a plating process can include placing the substrate in a bath to plate metal to the substrate and form the first and second conductive contacts. In another embodiment, a local metal deposition process can be used to form the first and second conductive contacts in one process step. In one embodiment, wires can be placed and thermally bonded to the first conductive contact and to the second conductive contact. In an embodiment, wires can be placed and thermally bonded to the first and second conductive contacts in a same or a single process step.

Disclosed herein are methods of fabricating solar cells. In an exemplary process flow,FIGS.6-16illustrate cross-sectional views of various stages in the fabrication of a solar cell, according to some embodiments. In various embodiments, the methods ofFIGS.6-16can include additional (or fewer) blocks than illustrated. For example, in some embodiments, the patterning processes ofFIGS.14and15may instead be combined into a single patterning process or performed in a same or single processing step.

Referring toFIG.6, a method of fabricating a solar cell600can include performing a texturization process to form a textured surface630on a front side602of substrate606. In an embodiment, the substrate606is a silicon substrate. In an example, the substrate606can be a monocrystalline silicon substrate, such as a bulk single crystalline N-type doped silicon substrate. In another example, the substrate606can be as a bulk single crystalline P-type doped silicon substrate. It is to be understood, however, that substrate606may be a layer, such as a multi-crystalline silicon layer, disposed on a global solar cell substrate. In an embodiment, the substrate606can have a front side602and a back side604, where the front side602is opposite the back side604. In one embodiment, the front side602can be referred to as a light receiving surface602and the back side can be referred to as a back surface604. In an embodiment, the substrate606can also have side edges641, e.g., edges of a wafer or the substrate, as shown.

Referring again toFIG.6, in an embodiment, performing a texturization process can include using a hydroxide-based wet etchant to form a texturized surface630on the front side602of the substrate606. A texturized surface630may be one which has a regular or an irregular shaped surface for scattering incoming light, decreasing the amount of light reflected off the light-receiving and/or exposed surfaces of the solar cell600. In an embodiment, as shown inFIG.6, a singled sided texturization process can be performed to form a texturized surface630on the front side602of the substrate606. In an embodiment, the texturization process may be performed on the front side602and the back side604of substrate600. In one such embodiment, prior to or within the same or single process step of the texturization process, the substrate can be cleaned, polished, planarized and/or thinned. In some embodiments, the texturization process need not be performed.

Referring again toFIG.6, in an embodiment, although the texturization process is shown to be performed at the start of the process flow, the texturization process can also be performed in the middle, or at the end of the method described herein. For example, texturization process can be performed subsequent to the processes described inFIG.15.

Referring toFIG.6, in an embodiment, a method of fabricating a solar cell600can include forming a first dielectric layer614on the back side604of the substrate606. In an embodiment, the first dielectric layer614can be formed in an oxidation process. In one embodiment, the first dielectric layer614can be formed in a deposition process. In an embodiment, the first dielectric layer614is a thin oxide layer, a silicon oxide layer or silicon oxynitride layer. In an embodiment, the first dielectric layer614can have a thickness of approximately 2 nanometers or less. In an embodiment, the first dielectric layer614is a tunnel oxide layer.

Referring again toFIG.7, in an embodiment, a method of fabricating a solar cell600can include forming a first silicon layer609on the first dielectric layer614. In an embodiment, the first silicon layer605can be a polycrystalline silicon layer. In an embodiment, the first silicon layer605can be doped to have a first conductivity type either through in situ doping, post a low pressure chemical deposition process, deposition implanting, or a combination thereof. In a specific embodiment, the first conductivity type is N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In another embodiment, the first silicon layer609can be formed undoped. In one such embodiment, a dopant layer can be formed on the first silicon layer609and a thermal process can be performed to drive dopants from the dopant layer into the first silicon layer609resulting in a first silicon layer having a first conductivity type (e.g., n-type or p-type).

Referring once again toFIG.7, in an embodiment, the first silicon layer605can be an amorphous silicon layer such as a hydrogenated silicon layer represented by a-Si:H which is implanted with dopants of the first conductivity type subsequent to deposition of the amorphous silicon layer. In one such embodiment, the first silicon layer605can be subsequently annealed (at least at some subsequent stage of the process flow) to ultimately form a polycrystalline silicon layer. In an embodiment, for either a polycrystalline silicon layer or an amorphous silicon layer, if post deposition implantation can be performed, the implanting is performed by using ion beam implantation or plasma immersion implantation. In one such embodiment, a shadow mask can be used for the implanting. In an embodiment, the first silicon layer605can have a thickness greater than or equal to approximately 300 Angstroms.

Referring again toFIG.7, an insulator layer609can be formed on the first silicon layer605. In an embodiment the insulator layer609can include silicon dioxide. In an example, a deposition process can be performed to form the insulator layer609. In an example, a blanket deposition process can be performed to form the insulator layer609.

Referring toFIG.8, a method of fabricating a solar cell600can include patterning the insulator layer609, first silicon layer605and first dielectric layer614. In an embodiment, the patterning can include forming a mask611over the insulator layer609, first silicon layer605and first thin dielectric layer614. In an example, the mask611can be formed using a screen printing, inkjet printing and/or any applicable masking process. In an embodiment, the mask611can be patterned to protect portions and expose other portions603of the insulator layer609, first silicon layer605and first dielectric layer614during an etching process. After etching, the mask611can be subsequently removed. For example, a lithographic or screen print masking and subsequent wet chemical etch process can be used to pattern the insulator layer609, first silicon layer605and first dielectric layer614and subsequently remove the mask611(e.g., in a cleaning step). In another embodiment, a laser process (e.g., laser ablation, direct write) can be used to pattern the insulator layer609, first silicon layer605and first thin dielectric layer614.FIG.9shows a first semiconductor region608, insulating region610and first dielectric layer614following the patterning processes described inFIG.8above.

Referring again toFIG.8, in one embodiment, the first dielectric layer614and the first silicon layer605can be formed on the back side604, the front side602and/or side edges641of the substrate, where, a subsequent patterning or cleaning process can be performed to remove the first dielectric layer614and the first silicon layer605from the front side602and/or side edges641of the substrate606.

Referring toFIG.9, an insulating region610, a first semiconductor region608and first dielectric layer614is shown subsequent to the patterning process ofFIG.8, according to some embodiments. In an embodiment, as described above, the first semiconductor region can be a first polycrystalline silicon emitter region. In a specific embodiment, the first semiconductor region608can have a first conductivity type which is N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In some embodiments, the first semiconductor region608can have a first conductivity type which is P-type. In an embodiment, the insulating region610can be include silicon dioxide. In some embodiments, the insulating region610can include other insulating materials e.g., a polyimide. As shown inFIG.9, portions615,617of the first semiconductor region608can be exposed subsequent to the patterning process (e.g., masking and etching, laser patterning, etc.) described inFIG.9. Similarly, also shown, portions619of the substrate606can also be exposed subsequent to the patterning.

In contrast to the processes shown inFIG.8andFIG.9, other patterning process can be used. For example, the mask611fromFIG.8need not be formed. In one example, a laser patterning process (e.g., without a mask611) can be used to pattern the insulator layer609, first silicon layer605and first thin dielectric layer614.

Referring toFIG.10, a method of fabricating a solar cell600can include forming a second dielectric layer620on portions of the first semiconductor region608and on portions of the substrate606. In an embodiment, the second dielectric layer620can be formed in an oxidation process and is a thin oxide layer such as a tunnel dielectric layer (e.g., silicon oxide). In one embodiment, the second dielectric layer620can be formed in a deposition process. In an embodiment, the second dielectric layer620is a thin oxide layer or silicon oxynitride layer. In an embodiment, the second dielectric layer620can have a thickness of approximately 2 nanometers or less. Referring toFIGS.9and10, in an embodiment, the second dielectric layer620can be formed616,618over exposed portions615,617of the first semiconductor region608. Similarly, the second dielectric layer620can be formed over exposed portions619of the substrate606. As used herein, the second dielectric layer620can also be referred to as a second thin dielectric layer.

Referring again to operation208of flowchart200, in an embodiment, forming the second dielectric layer on portions of the first semiconductor region608can instead include forming a separate, different and/or distinct dielectric layer616,618on portions of the first semiconductor region608. In an example, forming the second dielectric layer on portions of the first semiconductor region can instead include forming another dielectric layer616,618on portions of the first semiconductor region608. In an embodiment, this dielectric layer616,618can be referred to as a fourth or a fifth dielectric layer which is separate and different from the second dielectric layer620.

Referring once again toFIG.11, a method of fabricating a solar cell600can include forming a second silicon layer607over the back side604of the substrate606. In an embodiment, forming the second silicon layer607over the back side604of the substrate606can include forming the second silicon layer607on or over the second dielectric layer620and on the insulating region610. In one embodiment, the second silicon layer607can be deposited over the second dielectric layer620. In one example, a low pressure chemical vapor deposition (LPCVD) process or a plasma enhanced chemical vapor deposition (PECVD) process can be used to deposit the silicon layer607. In an embodiment, the second silicon layer607can be a polycrystalline silicon. In one embodiment, processes ifFIGS.10and12can be performed in a single chamber and/or manufacturing step. In an example, a second dielectric layer620can be grown and, subsequently, the second silicon layer607can be deposited over the second dielectric layer620in the same or single process chamber and/or manufacturing process. In an embodiment, the second silicon layer607can be formed undoped. In an embodiment, the second silicon layer607can be an amorphous silicon layer. In one such embodiment, the amorphous silicon layer is formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). In an embodiment, the second silicon layer607can have a thickness greater than or equal to approximately 300 Angstroms.

Referring again toFIG.11, in an embodiment, a method of fabricating a solar cell600can include forming a second silicon layer607having a second, different, conductivity type from the first semiconductor region608. In one such example, forming the second silicon layer607can include forming a pre-doped silicon layer. In one example, forming the second silicon layer607can include growing a p-type silicon layer over the second dielectric layer (e.g., a thin oxide layer).

Referring toFIG.12, a method of fabricating a solar cell600can include forming a third dielectric layer625over the back side of the substrate. In an embodiment, forming the third dielectric layer can include forming the third dielectric layer on the second silicon layer607and the insulating region610. In one embodiment, the third dielectric layer625can include silicon oxide, silicon oxynitride and silicon nitride. In an embodiment, the third dielectric layer625can be a dopant layer. In one such embodiment, the dopant layer625can have a second conductivity type. In an embodiment, the second conductivity type can be P-type. In one example, the dopant layer625can include boron. In an embodiment, a deposition process can be performed to form the dopant layer625. In an example, a chemical vapor deposition process can be used to from the dopant layer625. In one embodiment, the dopant layer can have a thickness in the range of approximately 100-2000 Angstroms. In an embodiment, the dopant layer625has a conductivity type which is opposite to the conductivity type of the the first semiconductor region608.

Referring toFIG.13, a method of fabricating a solar cell600can include patterning a third dielectric layer and a second silicon layer to form a second semiconductor region. As described herein, in an embodiment, patterning the third dielectric layer can include patterning a dopant layer (e.g., where the third dielectric layer includes a dopant or a dopant layer). In an embodiment, the patterning can include forming a mask613over the dopant layer625. In an embodiment, the mask613can be patterned to protect portions of the dopant layer625, second silicon layer607and second thin dielectric layer620during an etching process. After etching, the mask613can be subsequently removed. For example, a lithographic or screen print masking and subsequent wet chemical etch process can be used to pattern the dopant layer625and second silicon layer607. In another embodiment, a laser patterning process (e.g., laser ablation, direct write) can be used to pattern the dopant layer625, second silicon layer607and second thin dielectric layer620. The structure shown inFIG.14shows a second semiconductor region612formed following the patterning processes described inFIG.13above.

Referring again toFIG.13, in one embodiment, the second dielectric layer620and the second silicon layer607can be formed on the back side604, the front side602and/or side edges641of the substrate606, where, a subsequent patterning or cleaning process can be performed to remove the second dielectric layer620and the second silicon layer607from the front side602and/or side edges641of the substrate606.

In contrast to the processes shown inFIG.13andFIG.14, other patterning process can be used. For example, the mask613fromFIGS.13and14need not be formed. In one example, a laser patterning process (e.g., without a mask613) can be used to pattern the dopant layer625and second silicon layer607ofFIG.13.

Referring toFIG.14, a portion of the insulating region610fromFIG.13can be exposed, e.g., between the mask portion613, subsequent to the patterning process described inFIG.13. Also, although not shown, the mask613can be removed. In an example, subsequent to a patterning ofFIGS.13and14, the mask613can removed by a cleaning process. In an example, a wet chemical clean or ink strip process can be used to remove the mask613.

Referring still again toFIG.13andFIG.14, where the third dielectric layer can include a dopant layer, a method of fabricating a solar cell600can include performing a thermal process to drive dopants from dopant layer625. In the same embodiment, the mask portion613fromFIG.13andFIG.14can be removed prior to performing the thermal process. In an embodiment, subsequent to the thermal process, the second silicon layer612can have the same conductivity type as the dopant layer625. In one such embodiment, the second conductivity type can be P-type. In an example, the thermal process can include heating to a temperature greater than or equal to approximately 900 degrees-C. In an embodiment, the heating temperature can be approximately within the range of 900-1100 degrees-C. In another embodiment, a laser doping process can be used to drive dopants from dopant layer625to the second silicon layer607. In an embodiment, the thermal process can be performed subsequent to the patterning and/or cleaning processes described above.

Referring again toFIG.13andFIG.14, a method of fabricating a solar cell600can include forming a second semiconductor region612subsequent to the thermal process described above, according to some embodiments. In an embodiment, the second semiconductor region612can be a second polycrystalline silicon emitter region. In one embodiment, the second semiconductor region612can have a second conductivity type. In an embodiment, the second semiconductor region612can have the same conductivity type as the third dielectric layer625, e.g., where the third dielectric layer includes dopant (e.g., a dopant layer). In one embodiment, the second conductivity type is P-type. In an embodiment, the second conductivity type can be N-type. In one embodiment, second semiconductor region can be a pre-doped polycrystalline silicon emitter regions. In one such example, the second semiconductor region can be formed including an n-type or p-type conductivity directly, where the third dielectric layer does not include a dopant layer or the third dielectric layer is not formed altogether.

Referring toFIG.15, a method of fabricating a solar cell600can include patterning the insulating region610and a third dielectric layer (e.g., in some embodiments a dopant layer)625to form contact holes621,623through the insulating region610and a dopant layer625. In an embodiment, the patterning can form a contact hole621over the first semiconductor region608. In an embodiment, the patterning can form a contact hole623over the second semiconductor emitter region612. In an embodiment, the contact holes can be formed using a mask and etching process, laser process, or any other applicable patterning process.

Referring toFIG.16, a method of fabricating a solar cell600can include forming a first conductive contact638over the first semiconductor region608. In an embodiment, the first conductive contact638can be formed by one or more metallization processes. In an example, the first conductive contact638can be formed by performing a sputtering process, locally depositing a metal, a blanket deposition process, a plating process, bonding a metal foil and/or performing a wire bonding process. In an embodiment, the first conductive contact638can have the same conductivity type as the first semiconductor region608(e.g., first polycrystalline silicon emitter region). In an example, the first conductive contact638can be a N-type metal contact and the conductivity type of the first semiconductor region608can also be N-type.

Referring again toFIG.16, a method of fabricating a solar cell600can include forming a second conductive contact639over a second semiconductor region. In an embodiment, the second conductive contact639can be formed by one or more metallization processes. In an example, the second conductive contact639can be formed by performing a sputtering process, locally depositing a metal, a blanket deposition process, a plating process, bonding a metal foil and/or performing a wire bonding process. In an embodiment, the second conductive contact639can have the same conductivity type as the second semiconductor region612(e.g., second polycrystalline silicon emitter region). In an example, the second conductive contact can be a P-type metal contact and the conductivity type of the second semiconductor region can also be P-type. In an embodiment, as shown at624, the second conductive contact can be formed over the first semiconductor region and the second semiconductor region. In contrast, in some embodiments, the second conductive contact can be formed over the second semiconductor region only. In an embodiment, the second conductive contact639can be formed over the third dielectric layer625and the second semiconductor region612. In one example, the second conductive contact639can be formed over a dopant layer and the second semiconductor region612(e.g., the dopant layer disposed on the second semiconductor region612).

Referring again toFIG.16, in an embodiment, the first and second conductive contacts638,639can include one or more metals and/or metal alloys. In an example, the first and second conductive contacts638,639can include aluminum, titanium tungsten, nickel and/or copper, among other metals. In an embodiment, the first and second conductive contacts638,639can include one, two or more layers of metal. In an example, the metal seed layer can include a first layer including copper, a second layer including tungsten and a third layer including aluminum. In an example, the first and second conductive contacts638,639can include a locally deposited aluminum, aluminum foil, an aluminum wire, a blanket deposited metal (e.g., metal seed layer) and/or a plated metal.

Referring once more toFIG.16, a fourth dielectric layer632can be formed on the front side602of the solar cell600. In an embodiment the fourth dielectric layer632can be an anti-reflective layer (ARC). In one example, the fourth dielectric layer632can include silicon nitride. In some embodiments, other layers can be formed over the front side602. In an example, an amorphous silicon layer or another polysilicon layer can be formed over the front side602.

Referring once again toFIG.16, a solar cell600is shown fabricated using the methods corresponding to the flowcharts200,300,400and500ofFIGS.2,3,4and5and the methods ofFIGS.6-16. As shown, the solar cell ofFigures600ofFIG.16has similar reference numbers to elements of the solar cell100ofFIG.1, where like reference numbers refer to similar elements throughout the figures. In an embodiment, the structure of the solar cell600ofFIG.16is substantially similar to the structure of the solar cell100ofFIG.1, except as described above. Therefore, the description of corresponding portions ofFIG.1applies equally to the description ofFIG.16. In an example, the first semiconductor region608ofFIG.16can correspond to the first semiconductor region108ofFIG.1. In one example, the third dielectric layer625ofFIG.16can correspond to the third dielectric layer125ofFIG.1. As disclosed above, the third dielectric layer625can include a dopant layer. In some embodiments, the third dielectric layer625can include silicon oxide or silicon oxynitride. In one embodiment, the third dielectric layer625can include an insulator layer or an insulating material. In one embodiment, a portion at624of the second semiconductor region612can be disposed between the first conductive contact628and second conductive contact629. In an embodiment, a portion at624of the third dielectric layer625can be also disposed between the first conductive contact628and second conductive contact629.