Printed circuit board, method of fabricating printed circuit board, and semiconductor device

A printed circuit board has capacitors, a grounding wiring pattern having a bonding surface on which a semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to first electrodes of the capacitors, and a power supply wiring pattern having a bonding surface on which the semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to second electrodes of the capacitors. The grounding and power supply wiring patterns are alternately arranged in a predetermined direction, and the capacitors are coupled in parallel with respect to the grounding and power supply wiring patterns.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to printed circuit boards, methods of fabricating the printed circuit boards, and semiconductor devices, and more particularly to a printed circuit board having a capacitor that is electrically coupled to a semiconductor chip, a method of fabricating such a printed circuit board, and a semiconductor device having such a printed circuit board.

2. Description of the Related Art

FIG. 1is a cross sectional view showing an example of a conventional semiconductor device which reduces an inductance between a semiconductor chip and an internal capacitor of a printed circuit board, by electrically connecting the semiconductor chip and the capacitor by a minimum distance.

A semiconductor device200shown inFIG. 1includes a printed circuit board201, a semiconductor chip202, and external connection terminals203. The printed circuit board201has insulator layers211and225, pads212, a capacitor213having a pair of electrodes, vias218,219,226and227, wirings222and223, connection pads231and232for external connection, and a solder resist layer234.

The capacitor213is embedded in the insulator layer211. Each pad212has a bonding surface212A for flip-chip bonding of the semiconductor chip202which will be described later. The pads212are embedded in the insulator layer211so that the bonding surfaces212A approximately match a surface211A of the insulator layer211.

The capacitor213is disposed immediately under the pads212. One of the pair of electrodes of the capacitor213is electrically connected to the pads212at portions located on an opposite end from the bonding surfaces212a, via (that is, by way of) internal connection terminals215. The capacitor213functions as a decoupling capacitor for reducing power supply noise caused by changes in current consumption of the semiconductor chip202. Pads216which electrically connect to the other of the pair of electrodes of the capacitor213are provided on the surface of the capacitor213located on an opposite end from the surface provided with the internal connection terminals215.

The vias218are embedded in the insulator layer211, and electrically connect the pads212to the wirings222. The vias219are embedded in the insulator layer211, and electrically connect the pads216to the wirings223.

The wirings222are provided on a surface211B of the insulator layer211, located on an opposite end from the surface211A of the insulator layer211. The wirings222are formed integrally with the vias218. The wirings222are electrically connected to the pads212via the vias218.

The wirings223are provided on the surface211B of the insulator layer211. The wirings223are formed integrally with the vias219. The wirings223are electrically connected to the pads216via the vias219.

The insulator layer225is provided on the surface211B of the insulator layer211so as to expose portions of the wirings222and223. The vias226are embedded in the insulator layer225, and the vias226are electrically connected to the wirings222. The vias227are embedded in the insulator layer225, and the vias227are electrically connected to the wirings223.

The connection pads231are provided on a surface225A of the insulator layer255, located on an opposite end of a surface of the insulator layer225making contact with the insulator layer211. The connection pads231are formed integrally with the vias226. The pads231are electrically connected to the wirings222via the vias226.

The connection pads232are provided on the surface225A of the insulator layer225. The connection pads232are formed integrally with the vias227. The connection pads232are electrically connected to the wirings223via the vias227.

The solder resist layer234is provided on the surface225A of the insulator layer225. The solder resist layer234includes openings234A that expose the connection pads231, and openings234B that expose the connection pads232.

The semiconductor chip202is flip-chip bonded on the bonding surfaces212A of the pads212. Hence, terminals of the semiconductor chip202are electrically connected to the capacitor213via the pads212and the internal connection terminals215. For example, a semiconductor chip which operates at high frequencies may be used for the semiconductor chip202.

The external connection terminals203are provided on portions of the connection pads231that are exposed via the openings234A, and on portions of the connection pads232that are exposed via the openings234B. For example, a Japanese Laid-Open Patent Publication No. 2003-197809 proposes a structure having exposed connection terminals.

However, the operating frequency of the semiconductor chip202has increased in recent years, and an inductance component generated from the capacitor213introduces undesirable effects on the semiconductor chip202, such as an erroneous operation of the semiconductor chip202.

On the other hand, if the semiconductor chip202has various frequency characteristics, the single capacitor213within the printed circuit board201cannot cope with the various frequency characteristics of the semiconductor chip202.

SUMMARY OF THE INVENTION

Accordingly, it is a general object of one aspect of the present invention to provide a novel and useful printed circuit board, method of fabricating the printed circuit board, and semiconductor device, in which the problems described above are suppressed.

Another and more specific object of one aspect of the present invention is to provide a printed circuit board, a method of producing the printed circuit board, and a semiconductor device, which can reduce an inductance component generated from a capacitor, and make the capacitor cope with a semiconductor chip having various frequency characteristics, in order to reduce power supply noise caused by a change in a current consumption of the semiconductor chip.

According to one aspect of the present invention, there is provided a printed circuit board comprising a plurality of capacitors each having a first electrode and a second electrode; a grounding wiring pattern having a first chip bonding surface on which a semiconductor device is to be flip-chip bonded, and a first contact surface that is located on an opposite end from the first chip bonding surface and is coupled to first electrode of the capacitors; and a power supply wiring pattern having a second chip bonding surface on which the semiconductor device is to be flip-chip bonded, and a second contact surface that is located on an opposite end from the second chip bonding surface and is coupled to the second electrode of the capacitors, wherein the grounding wiring pattern and the power supply wiring pattern are alternately arranged in a predetermined direction, and the plurality of capacitors are coupled in parallel with respect to the grounding wiring pattern and the power supply wiring pattern.

According to one aspect of the present invention, there is provided a semiconductor device comprising a semiconductor chip; and a printed circuit board, the printed circuit board comprising a plurality of capacitors each having a first electrode and a second electrode; a grounding wiring pattern having a first chip bonding surface on which a semiconductor device is to be flip-chip bonded, and a first contact surface that is located on an opposite end from the first chip bonding surface and is coupled to first electrode of the capacitors; and a power supply wiring pattern having a second chip bonding surface on which the semiconductor device is to be flip-chip bonded, and a second contact surface that is located on an opposite end from the second chip bonding surface and is coupled to the second electrode of the capacitors, wherein the grounding wiring pattern and the power supply wiring pattern are alternately arranged in a predetermined direction, and the plurality of capacitors are coupled in parallel with respect to the grounding wiring pattern and the power supply wiring pattern.

According to one aspect of the present invention, there is provided a method of fabricating a printed circuit board according to one aspect of the present invention described above, comprising forming, on a support body, a resin layer having openings exposing the first chip bonding surface and openings exposing the second chip bonding surface; forming the ground wiring pattern and the power supply wiring pattern on the resin layer, so that the ground wiring pattern and the power supply wiring pattern are alternately arranged in the predetermined direction; coupling the plurality of capacitors to the grounding wiring pattern and the power supply wiring pattern; after coupling the plurality of capacitors, forming, on the resin layer, a reinforcing member made of an insulator and having a penetration part configured to accommodate the plurality of capacitors; and removing the support body.

According to one aspect of the present invention, it is possible to reduce an inductance component generated from the capacitor, and make the capacitor cope with the semiconductor chip having various frequency characteristics, in order to reduce power supply noise caused by a change in a current consumption of the semiconductor chip.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2is a cross sectional view showing a semiconductor device in an embodiment of the present invention. InFIG. 2, “A” indicates a predetermined direction in which grounding wiring patterns25and power supply wiring patterns26are alternately arranged. The printed circuit board11shown inFIG. 2corresponds to a cross section of a structure shown inFIG. 3, cut along a line B-B, which will be described later.

In this embodiment, a semiconductor device10includes a printed circuit board11, a semiconductor chip12, external connection terminals13-1for signals, external connection terminals13-2for grounding, and external connection terminals13-3for power supply.

The printed circuit board11has a reinforcing member21, an insulating member22, signal pads24, m+1 grounding wiring patterns25, m power supply wiring patterns26, a plurality of capacitors28and29, vias31,32and33, a solder resist layer36, and a multi-layer wiring structure (or multi-level interconnection structure)38, m is a natural number greater than or equal to one. In this embodiment, m=1, and thus, two grounding wiring patterns25are provided, and one power supply wiring pattern26is provided.

The reinforcing member21is made of an insulator, and is provided between the solder resist layer36and the multi-layer wiring structure38. A first planar surface21A of the reinforcing member21makes contact with the solder resist layer36. A second planar surface21B of the reinforcing member21makes contact with the multi-layer wiring structure38. The reinforcing member21includes penetration parts41and penetration holes42. The penetration part41is formed at a central portion of the reinforcing member21. The penetration part41functions as an accommodating part for accommodating the plurality of capacitors28and29. The penetration hole42is formed at a portion of the reinforcing member21located on the outer side of a region in which the penetration part41is formed. The penetration hole42exposes a portion of a contact surface24B of the signal pad24, located on an opposite end from a chip bonding surface24A of the signal pad24on which the semiconductor chip12is bonded. For example, the reinforcing member21may be formed by a glass epoxy substrate that is made up of a glass fiber covered by a resin.

By providing the reinforcing member21, which is formed by the glass epoxy substrate that is made up of a glass fiber covered by a resin, for example, between the solder resist layer36and the multi-layer wiring structure38, the reinforcing member21functions as a support member for supporting the multi-layer wiring structure38, and it is possible to reduce warping of the multi-layer wiring structure38.

For example, if the height of the plurality of capacitors28and29is 50 μm, the thickness of the reinforcing member21may be 150 μm.

The insulating member22is provided in the penetration parts41so as to encapsulate the plurality of capacitors28and29which are connected to the m+1 grounding wiring patterns25and the m power supply wiring patterns26. The insulating member22has penetration holes44and45. The penetration hole44penetrates a portion of the insulating member22opposing a contact surface (or first contact surface)25B of the grounding wiring pattern25. The penetration hole44exposes a portion of the contact surface25B. The penetration hole45penetrates a portion of the insulating member22opposing a contact surface (or second contact surface)26B of the power supply wiring pattern26. The penetration hole45exposes a portion of the contact surface26B. A first planar surface22A of the insulating member22, located on an opposite end from the end provided with the semiconductor chip12by the flip-chip bonding, approximately matches the planar surface21A of the reinforcing member21. A second planar surface22B of the insulator member22, located on an opposite end from the first planar surface22A of the insulator member22, approximately matches the planar surface21B of the reinforcing member21. For example, the insulating member22may be made of a material selected from materials such as epoxy resins and polyimide resins.

By providing the insulating member22which encapsulates the plurality of capacitors28and29, and making the planar surface22A of the insulating member22approximately match the planar surface21A of the reinforcing member21, it becomes possible to form the multi-layer wiring structure38on the surface22A of the insulating member22and the surface21A of the reinforcing member21.

The signal pads24have the chip bonding surface24A on which the semiconductor chip12is flip-chip bonded, and the contact surface24B located on the opposite end from the chip bonding surface24A. The signal pads24are embedded in the reinforcing member21, so that a chip bonding surface24A of each signal pad24approximately matches the surface21A of the reinforcing member21. The signal pads24are arranged on the outer side of a region in which the grounding wiring patterns25and the power supply wiring patterns26are formed. The semiconductor chip12is flip-chip bonded on the signal pads24, and the contact surfaces24B the signal pads24are connected to the vias31. In addition, the signal pads24are electrically connected to the external connection terminals13-1for signals, via the multi-layer wiring structure38. For example, the signal pads24may be made of Cu.

The grounding wiring patterns25have chip bonding surfaces (or first chip bonding surfaces)25A, and contact surfaces25B. The grounding wiring patterns25are embedded in the insulating member22, so that the chip bonding surfaces25A approximately match the surface22A of the insulating member22. The grounding wiring patterns25are disposed so that the grounding wiring pattern25and the power supply wiring pattern26are alternately arranged in the direction A. The semiconductor chip12is flip-chip bonded on the chip bonding surfaces25A, and the contact surfaces are25B are connected to first electrodes28A and29A of the capacitors28and29and the vias32. In addition, the grounding wiring patterns25are electrically connected to the external connection terminals13-2for grounding, via the multi-layer wiring structure38. For example, the grounding wiring patterns25may be made of Cu.

The power supply wiring patterns26have chip bonding surfaces (or second chip bonding surfaces)26A, and contact surfaces26B. The power supply wiring patterns26are embedded in the insulating member22, so that the chip bonding surfaces26A approximately match the surface22A of the insulating member22. The power supply wiring patterns26are disposed so that the grounding wiring pattern25and the power supply wiring pattern26are alternately arranged in the direction A. The semiconductor chip12is flip-chip bonded on the chip bonding surfaces26A, and the contact surfaces26B are connected to second electrodes28B and29B of the capacitors28and29. In addition, the power supply wiring patterns26are electrically connected to the external connection terminals13-3for power supply, via the multi-layer wiring structure38. For example, the power supply wiring patterns26may be made of Cu.

FIG. 3is a plan view showing the grounding wiring patterns and the power supply wiring patterns connected to the plurality of capacitors. For the sake of convenience,FIG. 3only shows the signal pads24, the grounding wiring patterns25, the power supply wiring patterns26, the solder resist layer36, and the plurality of capacitors28and29. InFIG. 3, those parts that are the same as those corresponding parts shown inFIG. 2are designated by the same reference numerals, and a description thereof will be omitted.

A description will now be given of the plurality of capacitors28and29, by referring toFIGS. 2 and 3. The plurality of capacitors28(two in this embodiment) are each formed by a two-terminal capacitor having the pair of electrodes28A and28B. The electrode28A connects to the contact surface25B of one of the two grounding wiring patterns25that is not connected to the capacitor29. The electrode28B connects to the contact surface26B of the power supply wiring pattern26.

The plurality of capacitors29(two in this embodiment) are each formed by a two-terminal capacitor having the pair of electrodes29A and29B. The electrode29A connects to the contact surface25B of the grounding wiring pattern25that is not connected to the capacitor28. The electrode29B connects to the contact surface26B of the power supply wiring pattern26. In other words, the plurality of capacitors28and29are arranged in parallel with respect to the m+1 grounding wiring patterns25and the m power supply wiring patterns26. The plurality of capacitors28and29are disposed under the semiconductor chip12, and are electrically connected to the semiconductor chip12via the grounding wiring patterns25and the power supply wiring patterns26. The plurality of capacitors28and29function as decoupling capacitors for reducing power supply noise caused by changes in current consumption of the semiconductor chip12.

Accordingly, the m+1 grounding wiring patterns25and the m power supply wiring patterns26are disposed so that the grounding wiring pattern25and the power supply wiring pattern26are alternately arranged in the direction A. Further, the plurality of capacitors28and29are connected in parallel with respect to the m+1 grounding wiring patterns25and the power supply wiring patterns26. For this reason, it is possible to reduce the inductance components of the plurality of capacitors28and29, when compared to the inductance component of the single capacitor213provided in the printed circuit board201of the conventional semiconductor device200shown inFIG. 1.

The capacitances of the plurality of capacitors28and29may be set to mutually different values in a case where the semiconductor chip12has various high-frequency characteristics. By setting the capacitances of the plurality of capacitors28and29to mutually different values in order to cope with the semiconductor chip12having various high-frequency characteristics, it becomes possible to reduce the power supply noise caused by the changes in the current consumption of the semiconductor chip12by the plurality of capacitors28and29.

As shown inFIG. 2, the vias31are provided in the penetration holes42, and connect to the contact surfaces24B of the signal pads24. Hence, the vias31are electrically connected to the semiconductor chip12via the signal pads24. In addition, the vias31are electrically connected to the external connection terminals13-1for signals, via the multi-layer wiring structure38.

The vias32are provided in the penetration holes44, and connect to the contact surfaces25B of the grounding wiring patterns25. Thus, the vias32are electrically connected to the semiconductor chip12via the grounding wiring patterns25. Further, the vias32are electrically connected to the external connection terminals13-2for grounding, via the multi-layer wiring structure38.

The vias33are provided in the penetration holes45, and connect to the contact surfaces26B of the power supply wiring patterns26. Hence, the vias33are electrically connected to the semiconductor chip12via the power supply wiring patterns26. Moreover, the vias33are electrically connected to the external connection terminals13-1for power supply, via the multi-layer wiring structure38. For example, the vias31,32and33may be made of Cu.

The solder resist layer36is provided on the surface21A of the reinforcing member21and the surface22A of the insulating member22. The solder resist layer36includes openings47,48and49. The opening47exposes the chip bonding surface24A of the signal pad24. The opening48exposes the chip bonding surface25A of the grounding wiring pattern25. The opening49exposes the chip bonding surface26A of the power supply wiring pattern26.

The multi-layer wiring structure38is provided on a surface21B of the reinforcing member21and the surface22B of the insulating member22. The multi-layer wiring structure38includes wirings51,52and53, insulator layers55and62, wiring patterns57,58and59, vias64,65and66, connection pads68,69and71for external connection, and a solder resist layer72.

The wiring51is provided on the surface21B of the reinforcing member21, and is formed integrally to the via31. The wiring51is electrically connected to the signal pad24via the via31.

The wiring52is provided on the surface22B of the insulating member22, and is formed integrally to the via32. The wiring52is electrically connected to the grounding wiring pattern25via the via32.

The wiring53is provided on the surface22B of the insulating member22, and is formed integrally to the via33. The wiring53is electrically connected to the power supply wiring pattern26via the via33. For example, the wirings51,52and53may be made of Cu.

The insulator layer55is provided on the surface21B of the reinforcing member21and on the surface22B of the insulating member22, so as to cover portions of the wirings51,52and53. The insulator layer55includes openings75,76and77. The opening75exposes a portion of the wiring51. The opening76exposes a portion of the wiring52. The opening77exposes a portion of the wiring53. For example, the insulator layer55may be formed by a resin layer. When the insulator layer55is formed by the resin layer, this resin layer may be made of a material such as epoxy resins and polyimide resins.

The wiring pattern57is provided in the opening75and on a surface55A of the insulator layer55that is located on the end where the insulator layer62is provided. The wiring pattern57is connected to the wiring51. The wiring pattern58is provided in the opening76and on the surface55A of the insulator layer55. The wiring pattern58is connected to the wiring52. The wiring pattern59is provided in the opening77and on the surface55A of the insulator layer55. The wiring pattern59is connected to the wiring53. For example, the wiring patterns57,58and59may be made of Cu.

The insulator layer62is provided on the surface55A of the insulator layer55, so as to cover portions of the wiring patterns57,58and59. The insulator layer62includes openings81,82and83. The opening81exposes a portion of the wiring pattern57. The opening82exposes a portion of the wiring pattern58. The opening83exposes a portion of the wiring pattern59. For example, the insulator layer59may be formed by a resin layer. When the insulator layer59is formed by the resin layer, this resin layer may be made of a material such as epoxy resins and polyimide resins.

The via64is provided in the opening81. The via64is connected to the wiring pattern57. The via65is provided in the opening82. The via65is connected to the wiring pattern58. The via66is provided in the opening83. The via66is connected to the wiring pattern59. For example, the vias64,65and66may be made of Cu.

The connection pad68is provided on a surface62A of the insulator layer62, and is formed integrally to the via64. The connection terminal68is electrically connected to the wiring pattern57via the via64. The connection pad69is provided on the surface62A of the insulator layer62, and is formed integrally to the via65. The connection pad69is electrically connected to the wiring pattern58via the via65. The connection pad71is provided on the surface62A of the insulator layer62, and is formed integrally to the via66. The connection pad71is electrically connected to the wiring pattern59via the via66. For example, the connection pads68,69and71may be formed by a stacked structure which is formed on the surface62A of the insulator layer62by successively stacking a Cu layer, a Ni layer and a Au layer.

The solder resist layer72is provided on the surface62A of the insulator layer62. The solder resist layer72includes openings72A,72B and72C. The opening72A exposes a portion of the connection pad68. The opening72B exposes a portion of the connection pad69. The opening72C exposes a portion of the connection pad71.

According to the printed circuit board11of this embodiment, the m+1 grounding wiring patterns25and the m power supply wiring patterns26are disposed so that the grounding wiring pattern25and the power supply wiring pattern26are alternately arranged in the direction A. In addition, the plurality of capacitors28and29are connected in parallel with respect to the mil grounding wiring patterns25and the power supply wiring patterns26. For this reason, it is possible to reduce the inductance components of the plurality of capacitors28and29, when compared to the inductance component of the single capacitor213provided in the printed circuit board201of the conventional semiconductor device200shown inFIG. 1.

In addition, the capacitances of the plurality of capacitors28and29may be set to mutually different values in a case where the semiconductor chip12has various high-frequency characteristics. By setting the capacitances of the plurality of capacitors28and29to mutually different values in order to cope with the semiconductor chip12having various high-frequency characteristics, it becomes possible to reduce the power supply noise caused by the changes in the current consumption of the semiconductor chip12by the plurality of capacitors28and29.

As shown inFIG. 2, the semiconductor chip12includes an electrode pad85for signal, an electrode pad86for grounding, and an electrode pad87for power supply. A bump89is provided on each of the electrode pads85,86and87. The bump89provided on the electrode pad85is fixed to the chip bonding surface24A of the signal pad24by solder91. Hence, the electrode pad85is electrically connected to signal pad24.

The bump89provided on the electrode pad86is fixed to the chip bonding surface25A of the grounding wiring pattern25by solder91. Hence, the electrode pad86is electrically connected to the grounding wiring pattern25.

The bump89provided on the electrode pad87is fixed to the chip bonding surface26A of the power supply wiring pattern26. Hence, the electrode pad87is electrically connected to the power supply wiring pattern26.

In other words, the semiconductor chip12is flip-chip bonded with respect to the chip bonding surfaces24A of the signal pads24, the chip bonding surfaces25A of the m+1 grounding wiring patterns25, and the chip bonding surfaces26A of the m power supply wiring patterns26. Thus, the semiconductor chip12is electrically connected to the printed circuit board11. For example, a semiconductor chip having a CPU, a semiconductor chip for high-frequency operation, and the like may be used for the semiconductor chip12.

The connection terminal13-1is provided on a portion of the connection pad68exposed in the opening72A. For example, the connection terminal13-1may be formed by a solder ball. The connection terminal13-2is provided on a portion of the connection pad69exposed in the opening72B. For example, the connection terminal13-2may be formed by a solder ball. The connection terminal13-3is provided on a portion of the connection pad71exposed in the opening72C. For example, the connection terminal13-3may be formed by a solder ball. The connection terminals13-1,13-2and13-3form external connection terminals that are used for mounting the semiconductor device10on a mounting substrate or board (not shown), such as a mother board.

According to the semiconductor device10of this embodiment, it is possible to obtain effects similar to those obtainable by the printed circuit board11described above, because the semiconductor10has the printed circuit board11described above.

In the semiconductor device10of this embodiment, the m+1 grounding wiring patterns25and the m power supply wiring patterns26are disposed so that the grounding wiring pattern25and the power supply wiring pattern26are alternately arranged in the direction A. In addition, the plurality of capacitors28and29are connected in parallel with respect to the m+1 grounding wiring patterns25and the power supply wiring patterns26. For this reason, it is possible to reduce the inductance components of the plurality of capacitors28and29, when compared to the inductance component of the single capacitor213provided in the printed circuit board201of the conventional semiconductor device200shown inFIG. 1.

In addition, the capacitances of the plurality of capacitors28and29may be set to mutually different values in a case where the semiconductor chip12has various high-frequency characteristics. By setting the capacitances of the plurality of capacitors28and29to mutually different values in order to cope with the semiconductor chip12having various high-frequency characteristics, it becomes possible to reduce the power supply noise caused by the changes in the current consumption of the semiconductor chip12by the plurality of capacitors28and29.

In the embodiment described above, m+1 grounding wiring patterns25and m power supply wiring patterns26are provided. However, it is of course possible provide m grounding wiring patterns25and m+1 power supply wiring patterns26instead. In this latter case, it is possible to obtain the same effects as those obtainable by the printed circuit board11and the semiconductor device10described above.

Furthermore, the number of each of the capacitors28and29provided with respect to the m+1 grounding wiring patterns25and the m power supply wiring patterns26is not limited to that of the embodiment described above.

FIGS. 4 through 20are diagrams showing fabricating processes of the semiconductor device in this embodiment of the present invention. The cross sections shown inFIGS. 4 through 20correspond to the cross section of the structure shown inFIG. 3, cut along the line B-B. Although the electrode28B of the capacitor28and the electrode29B of the capacitor29will contact each other in the cross section when the structure shown inFIG. 3is cut along the line B-B, the electrodes28B and29B are actually separated from each other as may be seen fromFIG. 3. For this reason,FIGS. 8 through 20show the structure in a state where the electrode28B of the capacitor28and the electrode29B of the capacitor29are separated from each other.

InFIGS. 4 through 20, those parts that are the same as those corresponding parts inFIGS. 2 and 3are designated by the same reference numerals, and a description thereof will be omitted. InFIG. 16, “C” denotes a cutting position where a main support body103and two metal films105are cut.

A description will be given of the method of fabricating the semiconductor device10of this embodiment, by referring toFIG. 4.

First, in the preparation process shown inFIG. 4, a support body101for use in fabricating the printed circuit board11is prepared. The support body101includes a plate-shaped main support body103, metal films105provided on both surfaces103A and103B of the main support body103, and a bonding agent106which bonds an outer peripheral part of the metal film105to the main support body103.

For example, the main support body103may be made of a metal plate or a resin substrate that is provided with a metal film. The metal plate forming the main support body103may be made of a metal such as CU, Ni and Al, glass epoxy, and the like. In this case, the main support body103may have a thickness of 0.8 mm, for example.

For example, the metal film105may be made of Cu. A Cu film forming the metal film105may have a thickness of 12 μm, for example.

In the resin layer forming process shown inFIG. 5, the solder resist layer36made of a resin and having the openings47,48and49is formed on a surface105A of the metal film105which is provided on the surfaces103A and103B of the main support body103. More particularly, the solder resist layer36is formed by adhering a dry film resist on the surface105A of the metal film105, and thereafter exposing and developing the dry film resist at portions corresponding to the regions where the openings47,48and49are formed.

The opening47exposes the portion of the signal pad24on which the semiconductor chip12is flip-chip bonded. Hence, the opening47is formed so as to expose a portion of the surface105A of the metal film105corresponding to the region where the signal pad24is formed. The opening48exposes the portion of the grounding wiring pattern25on which the semiconductor chip12is flip-chip bonded. Hence, the opening48is formed so as to expose a portion of the surface105A of the metal film105corresponding to the region where the grounding wiring pattern25is formed. The opening49exposes the portion of the power supply wiring pattern36on which the semiconductor chip12is flip-chip bonded. Hence, the opening49is formed so as to expose a portion of the surface105A of the metal film105corresponding to the region where the power supply wiring pattern26is formed.

Next, in the process shown inFIG. 6, the solder91is formed so as to fill the openings47,48and49provided in the structure shown inFIG. 5. More particularly, the solder91is formed in the openings47,48and49by electroplating using the metal films105as power feed layers.

In the wiring pattern forming process shown inFIG. 7, the signal pads24covering a surface91A of the solder91filling the opening47, the m+1 grounding wiring patterns25covering the surface91A of the solder91filling the openings48, and the m power supply wiring patterns26covering the surface91A of the solder91filling the openings49, are simultaneously formed on a surface36A of the solder resist layer36which is provided in the structure shown inFIG. 6. More particularly, the signal pads24, the m+1 grounding wiring patterns25and the m power supply wiring patterns26are formed using the semi-additive technique, for example.

In this state, the m+1 grounding wiring patterns25and the m power supply wiring patterns26are formed so that the grounding wiring pattern25and the power supply wiring pattern26are alternately arranged in the direction A. For example, the signal pads24, the m+1 grounding wiring patterns25and the m power supply wiring patterns26may be made of Cu.

Next, in the capacitor connecting process shown inFIG. 8, the plurality of capacitors28and29are connected in parallel with respect to the m+1 grounding wiring patterns25and the power supply wiring patterns26that are provided on the top and bottom surfaces of the structure shown inFIG. 7. The plurality of capacitors28are each formed by a two-terminal capacitor having the pair of electrodes28A and28B. The electrode28A connects to the contact surface25B of one of the two grounding wiring patterns25that is not connected to the capacitor29, and the electrode28B connects to the contact surface26B of the power supply wiring pattern26.

The plurality of capacitors29are each formed by a two-terminal capacitor having the pair of electrodes29A and29B. The electrode29A connects to the contact surface26B of the grounding wiring pattern25that is not connected to the capacitor28. The electrode29B connects to the contact surface26B of the power supply wiring pattern26.

Accordingly, by forming the solder resist layer36including the openings47,48and49on the support body101, then filling the openings47,48and49by the solder91, then forming the m+1 grounding wiring patterns25and the m power supply wiring patterns26on the surface36A of the solder resist layer36and the surface91A of the solder91so that the grounding wiring pattern25and the power supply wiring pattern26are alternately arranged in the direction A, and then connecting the plurality of capacitors28and29in parallel with respect to the m+1 grounding wiring patterns25and the power supply wiring patterns26, it becomes possible to reduce the inductance components of the plurality of capacitors28and29, when compared to the inductance component of the single capacitor213provided in the printed circuit board201of the conventional semiconductor device200shown inFIG. 1.

In addition, by setting the capacitances of the plurality of capacitors28and29to mutually different values in order to cope with the semiconductor chip12having various high-frequency characteristics when connecting the plurality of capacitors28and29in parallel with respect to the m+1 grounding wiring patterns25and the power supply wiring patterns26in the capacitor connecting process, it becomes possible to reduce the power supply noise caused by the changes in the current consumption of the semiconductor chip12by the plurality of capacitors28and29.

Next, in the reinforcing member forming process shown inFIG. 9, the reinforcing member21, which is an insulator and has the penetration part41for accommodating the plurality of capacitors28and29, is formed on the surface36A of the solder resist layer36that is provided on the structure shown inFIG. 8. For example, the reinforcing member21may be formed by a glass epoxy substrate that is made up of a glass fiber covered by a resin. If the height of the plurality of capacitors28and29is 50 μm, the thickness of the reinforcing member21may be 150 μm.

By providing the reinforcing member21, which is formed by the glass epoxy substrate that is made up of a glass fiber covered by a resin, for example, it is possible to reduce warping of the multi-layer wiring structure38.

Next, in the insulating member forming process shown inFIG. 10, the plurality of capacitors28and29accommodated within the penetration part41are encapsulated by the insulating member22. In this state, the insulating member22is formed so that the surface22B of the insulating member22and the surface21B of the reinforcing member21approximately match. For example, the insulating member22may be made of epoxy resins and polyimide resins.

By forming the insulating member22to encapsulate the plurality of capacitors28and29accommodated within the penetration part41, and making the surface22B of the insulating member22approximately match the surface21B of the reinforcing member21, it becomes possible to form the multi-layer wiring structure38on the surface21B of the reinforcing member21and the surface22B of the insulating member22.

Next, in the process shown inFIG. 11, the penetration hole42is formed in the reinforcing member21that is provided on the structure shown inFIG. 10in order to expose the contact surface24B. In addition, the penetration holes44and45are formed in the insulating member22that is provided on the structure shown inFIG. 10in order to expose the contact surface25B and the contact surface26B, respectively. For example, the penetration holes42,44and45may be formed by laser processing.

InFIG. 11, the penetration holes44and45are illustrated as if the penetration holes44and34are formed along the line B-B inFIG. 3, but this illustration is made in order to facilitate the understanding of the positional relationship between the grounding wiring pattern25and the penetration hole44and the positional relationship between the power supply wiring pattern26and the penetration hole45, in the cross section. In the plan view ofFIG. 3, the penetration holes44and45would not be formed at least on the capacitors28and29themselves. Rather, the penetration hole44in the plan view would be formed on the contact surface25B at a portion where the capacitors28and29are not formed. Similarly, the penetration hole45in the plan view would be formed on the contact surface26B at a portion where the capacitors28and29are not formed. The above similarly applies to each ofFIG. 2andFIGS. 11 through 20.

Next, in the process shown inFIG. 12, the via31which fills the penetration hole42, the wiring51that is formed integrally with the via31, the via32which fills the penetration hole44, the wiring52that is formed integrally with the via32, the via33which fills the penetration hole45, and the wiring53that is formed integrally with the via33are formed simultaneously. More particularly, the vias31,32and33and the wirings51,52and53are formed using the semi-additive technique, for example. For example, the vias31,32and33and the wirings51,52and53may be made of Cu.

Next, in the process shown inFIG. 13, the insulator layer55, including the openings75,76and77, is formed on the surface21B of the reinforcing member21and the surface22B of the insulating member22that are provided on the structure shown inFIG. 12. For example, the insulator layer55may be made of a resin. When forming the insulator layer55by a resin layer, this resin layer may be made of epoxy resins, polyimide resins and the like. For example, the openings75,76and77may be formed in the insulator layer55by laser processing. The opening75is formed so as to expose a portion of the wiring51, and the opening76is formed so as to expose a portion of the wiring52. The opening77is formed so as to expose a portion of the wiring53.

Next, in the process shown inFIG. 14, the wiring pattern57is formed in (to fill) the opening75and on the surface55A of the insulator layer55, the wiring pattern58is formed in (to fill) the opening76and on the surface55A of the insulator layer55, and the wiring pattern59is formed in (to fill) the opening77and on the surface55A of the insulator layer55, simultaneously. More particularly, the wiring patterns57,58and59may be formed using the semi-additive technique, for example. For example, the wiring patterns57,58and59may be made of Cu.

Next, in the process shown inFIG. 15, a process similar to that shown inFIG. 13is performed. In other words, the insulator layer62, including the openings81,82and83, is formed on the surface55A of the insulator layer55that is provided on the structure shown inFIG. 14, and thereafter, a process similar to that shown inFIG. 14is performed in order to form the vias64,65and66and the connection pads68,69and71on the insulator layer62.

For example, the insulator layer62is made of a resin. When a resin layer is used for the insulator layer62, this resin layer may be made of epoxy resins, polyimide resins and the like. For example, the vias64,65and66may be made of Cu. For example, the connection pads68,69and71may be formed by a stacked structure which is formed on the surface62A of the insulator layer62by successively stacking a Cu layer, a Ni layer and a Au layer.

Next, in the process shown inFIG. 16, the solder resist layer72, including the openings72A,72B and72C, is formed on the surface62of the insulator layer62that is provided on the structure shown inFIG. 15. In this state, the opening72A is formed to expose a portion of the connection pad68, and the opening72B is formed to expose a portion of the connection pad69. In addition, the opening72C is formed to expose a portion of the connection pad71. Hence, a structure110having the metal film105and the printed circuit board11, successively formed on each of the surfaces103A and103B of the main support body103, is formed. The printed circuit board11includes the multi-layer wiring structure38that is provided on the metal film105. The processes shown inFIGS. 12 through 16form to a multi-layer wiring structure forming process.

Next, in the process shown inFIG. 17, the main support body103and the two metal films105are cut along the cutting position B shown inFIG. 16, in order to form two separate structures110.

Next, in the process shown inFIG. 18, the structure110shown in the upper half ofFIG. 17is turned upside-down, so that the capacitor28of this structure110is arranged on the right side of the capacitor29, and the metal film105is thereafter removed from the structure110in this upside-down orientation. For example, the metal film105may be removed from the structure110by a wet etching. As a result, the printed circuit board11is fabricated. The processes shown inFIGS. 17 and 18form a support body removing process.

Next, in the process shown inFIG. 19, the semiconductor chip12having the bumps89formed on the electrode pads85,86and87is prepared, and the bumps89are pressed against the solder91. In addition, the solder91is melted, in order to perform flip-chip bonding of the semiconductor chip12on the signal pads24, the ground wiring patterns25and the power supply wiring patterns26.

Next, in the process shown inFIG. 20, the external connection terminals13-1are formed on the connection pads68, the external connection terminals13-2are formed on the connection pads69, and the external connection terminals13-3are formed on the connection pads71. As a result, the semiconductor device10of this embodiment is fabricated. For example, solder balls may be used for the external connection terminals13-1,13-2and13-3.

According to the method of fabricating the printed circuit board11in this embodiment, by forming the solder resist layer36including the openings47,48and49on the support body101, then filling the openings47,48and49by the solder91, then forming the m+1 grounding wiring patterns25and the m power supply wiring patterns26on the surface36A of the solder resist layer36and the surface91A of the solder91so that the grounding wiring pattern25and the power supply wiring pattern26are alternately arranged in the direction A, and then connecting the plurality of capacitors28and29in parallel with respect to the m+1 grounding wiring patterns25and the power supply wiring patterns26, it becomes possible to reduce the inductance components of the plurality of capacitors28and29, when compared to the inductance component of the single capacitor213provided in the printed circuit board201of the conventional semiconductor device200shown inFIG. 1.

In addition, by setting the capacitances of the plurality of capacitors28and29to mutually different values in order to cope with the semiconductor chip12having various high-frequency characteristics when connecting the plurality of capacitors28and29in parallel with respect to the m+1 grounding wiring patterns25and the power supply wiring patterns26in the capacitor connecting process, it becomes possible to reduce the power supply noise caused by the changes in the current consumption of the semiconductor chip12by the plurality of capacitors28and29.

Furthermore, by providing the reinforcing member21, which is formed by the glass epoxy substrate that is made up of a glass fiber covered by a resin, for example, it is possible to reduce warping of the multi-layer wiring structure38.

In the embodiment described above, the external connection terminals13-1,13-2and13-3are formed after bonding the semiconductor chip12on the printed circuit board11by flip-chip bonding. However, it is of course possible to provide a process of forming the external connection terminals13-1,13-2and13-3between the process of forming the solder resist layer72and the process of cutting the main support body103and the two metal films105.

Moreover, in the embodiment described above, the solder resist layer36having the openings47,48and49is formed on the Cu film, then the pads and the wiring patterns are formed, and thereafter the insulator (resin) layer is stacked. However, it is of course possible instead to form a resist on the Cu film, then, form the openings corresponding to the openings47,48and49in the resist, then form the vias and/or the wirings, and thereafter form the solder resist layer on the insulator (resin) layer so as to expose a portion of the pad or wiring pattern.

Therefore, the present invention is applicable to various printed circuit boards having capacitors to be electrically connected to a semiconductor chip, methods of fabricating such printed circuit boards, and semiconductor devices having such printed circuit boards.

This application claims the benefit of Japanese Patent Applications No. 2008-135610 filed on May 23, 2008 and No. 2009-121425 filed on May 19, 2009, in the Japanese Patent Office, the disclosures of which are hereby incorporated by reference.