Semiconductor device, manufacturing method thereof, and display apparatus

Provided is a semiconductor device including a buffer layer that is on a substrate and includes an inclined surface; a crystalline silicon layer that is on the buffer layer; a gate electrode that is on the crystalline silicon layer while being insulated from the crystalline silicon layer; and a source electrode and a drain electrode that are each electrically connected to the crystalline silicon layer, the angle between the substrate and the inclined surface being in a range of about 17.5 degrees to less than about 70 degrees.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2014-0099976, filed on Aug. 4, 2014, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device, Manufacturing Method Thereof, and Display Apparatus,” is incorporated by reference herein in its entirety.

BACKGROUND

One or more embodiments relate to a semiconductor device, a manufacturing method thereof, and a display apparatus.

2. Description of the Related Art

A display apparatus such as an organic light-emitting display apparatus and a liquid crystal display apparatus may include a thin film transistor (TFT) that may be used for a pixel switch or a driving circuit. Laser annealing using a laser beam may be performed as a part of a method of manufacturing the TFT at a low temperature processor.

SUMMARY

Embodiments may be realized by providing a semiconductor device, including a buffer layer that is on a substrate and includes an inclined surface; a crystalline silicon layer on the buffer layer; a gate electrode that is on the crystalline silicon layer and insulated from the crystalline silicon layer; and a source electrode and a drain electrode that are each electrically connected to the crystalline silicon layer, an angle between the substrate and the inclined surface being in a range of about 17.5 degrees to less than about 70 degrees.

A slope of an upper surface of the crystalline silicon layer that overlaps with the inclined surface in a plan view may be smaller than a slope of the inclined surface.

The upper surface of the crystalline silicon may be substantially planar.

The buffer layer may include a first buffer layer on the substrate, and a second buffer layer on the first buffer layer. An upper surface of the first buffer layer may be planar and an upper surface of the second buffer layer may have the inclined surface.

The first buffer layer may include silicon nitride (SiNx) and the second buffer layer may include silicon oxide (SiOx).

The buffer layer may include a planar portion, and the inclined surface may include a first inclined surface and a second inclined surface that each extend outward from the planar portion.

Embodiments may be realized by providing a method of manufacturing a semiconductor, the method including forming a buffer layer on a substrate; forming an inclined surface by etching the buffer layer; forming an amorphous silicon layer on the buffer layer; and forming a crystalline silicon layer by crystallizing the amorphous silicon layer using a laser beam, at least some of the laser beam being irradiated from a laser source, completely reflected by the inclined surface, and then absorbed by the amorphous silicon layer.

An angle θ between the substrate and the inclined surface may be in a range of sin−1(n2/n1) to about 70 degrees where n1is a refractive index of the amorphous silicon layer, and n2is a refractive index of the buffer layer.

A slope of an upper surface of the amorphous silicon layer that overlaps with the inclined surface in a plan view may be smaller than a slope of the inclined surface.

The buffer layer may include a planar portion, and the inclined surface may include a first inclined surface and a second inclined surface that each extend outward from the planar portion.

The buffer layer may include a first buffer layer on the substrate, and a second buffer layer on the first buffer layer. An upper surface of the first buffer layer may be planar and an upper surface of the second buffer layer may include the inclined surface.

The laser source may be an excimer laser or a frequency doubled Q-switched Nd:YAG laser.

The method may further include, after forming the crystalline silicon layer, forming a gate electrode insulated from the crystalline silicon layer, and forming a source electrode and a drain electrode that are each electrically connected to the crystalline silicon layer.

Embodiments may be realized by providing a display apparatus, including a buffer layer that is on a substrate and includes an inclined surface in an upper surface thereof; a crystalline silicon layer on the buffer layer; a gate electrode on the crystalline silicon layer and insulated from the crystalline silicon layer; a source electrode and a drain electrode that are each electrically connected to the crystalline silicon layer; a pixel electrode that is electrically connected to one of the source electrode and the drain electrode; an intermediate layer that is on the pixel electrode and includes an organic light-emitting layer; and an opposite electrode on the intermediate layer, an angle θ between the substrate and the inclined surface being in a range of about 17.5 degrees to less than about 70 degrees.

A slope of the upper surface of the crystalline silicon layer that overlaps with the inclined surface in a plan view may besmaller than a slope of the inclined surface.

The upper surface of the crystalline silicon layer may be substantially planar.

The buffer layer may include a first buffer layer on the substrate, and a second buffer layer on the first buffer layer. An upper surface of the first buffer layer may be planar and an upper surface of the second buffer layer may include the inclined surface.

The first buffer layer may include silicon nitride (SiNx), and the second buffer layer may include silicon oxide (SiOx).

The buffer layer may include a planar portion, and the inclined surface may include a first inclined surface and a second inclined surface that each extend outward from the planar portion.

The inclined surface may only be in an area corresponding to the crystalline silicon layer.

DETAILED DESCRIPTION

FIG. 1illustrates a schematic cross-sectional view of a semiconductor device according to an embodiment. Referring toFIG. 1, according to an embodiment, a semiconductor device100may include a buffer layer20that is disposed on a substrate10and has inclined surfaces20band20cat the upper surface thereof; a crystalline silicon layer30that is disposed on the buffer layer20; a gate electrode50that is disposed on the crystalline silicon layer30and insulated from the crystalline silicon layer30; and a source electrode70S and a drain electrode70D that are each electrically connected to the crystalline silicon layer30.

The substrate10may be a transparent glass substrate or a plastic substrate. The buffer layer20may be disposed on the substrate10, and according to an embodiment, the buffer layer20may include a first buffer layer21disposed on the substrate10, and a second buffer layer22disposed on the first buffer layer21.

The first buffer layer21and the second buffer layer22may be, for example, silicon nitride (SiNx) and silicon oxide (SiOx), respectively. The buffer layer20may be formed as a single layer, or as three or more layers. The first buffer layer21and the second buffer layer22may be formed not only of silicon nitride and silicon oxide, but of other inorganic materials or organic materials, and the second buffer layer22may include, for example, a material with a low refractive index.

The upper surface of the first buffer layer21may be planar, and the upper surface of the second buffer layer22may include a planar portion20aand inclined surfaces20band20c. The inclined surfaces20band20cmay include a first inclined surface20band a second inclined surface20cthat each extend outward from the planar portion20a.

The inclined surfaces20band20care inclined at a predetermined angle θ to the substrate10, and each angle θ between the substrate10and the inclined surfaces20band20cmay be in a range of about 17.5 to less than about 70 degrees.

Each angle θ between the substrate10and the inclined surfaces20band20cin the buffer layer20may be greater than a critical angle, which is an angle required for complete, e.g., total, reflection, i.e., an incident laser beam is completely, e.g., totally, reflected, and crystallization efficiency may be increased in a crystallizing process that crystallizes an amorphous silicon layer30′ (seeFIG. 2c) to form crystalline silicon. The critical angle is determined by a refractive index of the amorphous silicon layer30′ (seeFIG. 2c) and the buffer layer20, and will be described later in detail.

The crystalline silicon layer30is disposed on the buffer layer20. The crystalline silicon layer30may be formed by the crystallization and patterning of the amorphous silicon layer30′ (seeFIG. 2c), and the slope of the upper surface of the crystalline silicon layer30, which overlaps with the inclined surfaces20band20cin the buffer layer20in a plan view, is smaller than that of the inclined surfaces20band20c. By forming this structure, the amount of the laser beam reflected on the upper surface of the amorphous silicon layer30′ (seeFIG. 2c) may be reduced, and the amount of the laser beam lost to the outside may be reduced.

The upper surface of the crystalline silicon layer30according to an embodiment may be, for example, planar. In an embodiment, the crystalline silicon layer30may not be planar.

The gate electrode50, the source electrode70S, and the drain electrode70D may be disposed on the crystalline silicon layer30; a gate insulating layer40may be interposed between the crystalline silicon layer30and the gate electrode50; and an interlayer insulating layer60may be interposed between the gate electrode50and the source electrode70S and between the gate electrode50and the drain electrode70D.

The gate electrode50may include one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) and may be formed, for example, as a three-layer structure of Ti/Al/Ti or Mo/Al/Mo.

The source electrode70S and the drain electrode70D each may be electrically connected to a source area and a drain area in the crystalline silicon layer30via a contact hole formed in the interlayer insulating layer60and the gate insulating layer40. The source electrode70S and the drain electrode70D may include one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) in the same manner as the gate electrode50, and be formed as a three-layer structure of Ti/Al/Ti or Mo/Al/Mo.

FIGS. 2A to 2Fillustrate sequential views of the manufacturing process of the semiconductor device ofFIG. 1. Referring toFIG. 2A, the first buffer layer21is formed on the substrate10, and a second unpatterned buffer layer22′ is formed on the first buffer layer21. For example, the substrate10may be formed of transparent glass or plastic; the first buffer layer21may be formed of silicon nitride (SiNx); and the second unpatterned buffer layer22′ may be formed of silicon oxide (SiOx).

The first buffer layer21and the second unpatterned buffer layer22′ may be deposited by various deposition methods such as a plasma enhanced chemical vapor deposition (PECVD) method, an atmospheric pressure CVD (APCVD) method, and a low pressure CVD (LPCVD) method.

Referring toFIG. 2B, the second buffer layer22including the inclined surfaces20band20cmay be formed by etching the second unpatterned buffer layer22′. The second buffer layer22may include the planar portion20a, and the first inclined surface20band the second inclined surface20c, which each extend outward from the planar portion20a.

The inclined surfaces20band20care formed to extend outward at a predetermined angle from the substrate10, and the angle θ between the substrate10and each of the inclined surfaces20band20cmay be in a range of about 17.5 degrees and less than about 70 degrees.

Referring toFIGS. 2C and 2D, after the amorphous silicon layer30′ is formed on the buffer layer20, the amorphous silicon layer30′ may be crystallized by irradiating the same with a laser beam. A laser source used herein may be an excimer laser having a wavelength of about 308 nm or a frequency doubled Q-switched Nd:YAG laser having a wavelength of about 532 nm.

The temperature of the amorphous silicon layer30′ may be elevated by absorbing the laser beam irradiated from the laser source, and as the temperature drops, the crystallization of the amorphous silicon layer30′ begins. However, the amorphous silicon layer30′ may only absorb less than 50% of incident laser beam, and the absorptance rate of the laser beam may further decrease during crystallizing the amorphous silicon layer30′ using a Nd:YAG laser.

The buffer layer20in the semiconductor device100according to an embodiment may include the inclined surfaces20band20cat the upper surface thereof, the laser beam transmitted through the amorphous silicon layer30′ may be totally reflected by the inclined surfaces20band20c, the amorphous silicon layer30′ may be irradiated again, and the absorptance rate of the laser beam may be increased.

For the laser beam to be totally reflected by the inclined surfaces20band20c, each angle θ between the substrate10and the inclined surfaces20band20cmay be greater than a critical angle ic. A refractive index of the amorphous silicon layer30′ is n1, a refractive index of the second buffer layer22, which is a part of buffer layer20and contacts with the amorphous silicon layer30′, is n2, and the angle θ may be larger than the critical angle ic, i.e., sin−1(n2/n1), for total reflection. A refractive index n1of the amorphous silicon layer30′, a refractive index n2of the second buffer layer22, and the critical angle iccalculated therefrom when using the laser beams of 308 nm and 532 nm are shown in Table 1 below.

Referring to Table 1, each angle θ between the substrate10and the inclined surfaces20band20cis, for example, 17.5 degrees or more.

Each angle θ between the substrate10and the inclined surfaces20band20cmay be less than 70 degrees. If the angle θ is greater than 70 degrees, the laser beam may not reach to the boundary between the planar portion20aand the inclined surfaces20band20c, and the crystallization may not occur. By forming the inclined surfaces20band20cto extend outward from the substrate10at the angle θ of less than 70 degrees, the crystallization may evenly occur over the whole area of the amorphous silicon layer30′.

The slope of the upper surface of the crystalline silicon layer30, which overlaps with the inclined surfaces20band20cin the buffer layer20in a plan view, may be smaller than that of the inclined surfaces20band20c, and by forming this structure, the amount of the laser beam reflected on the upper surface of the amorphous silicon layer30′ may be reduced, and the amount of the laser beam lost to the outside may be reduced.

According to an embodiment, the upper surface of the amorphous silicon layer30′ may be, for example, substantially planar.

Referring toFIG. 2D, the amount of laser beam absorbed by the amorphous silicon layer30′ may vary depending on the total reflection at the inclined surfaces20band20c. In other words, the amount of laser beam absorbed by the area of the amorphous silicon layer30′ corresponding to the inclined surfaces20band20cmay be greater than the amount of laser beam absorbed by the area of the amorphous silicon layer30′ corresponding to the planar portion20a, and the amorphous silicon layer30′ may have an area having a relatively low temperature and an area having a relatively high temperature according to the arrangement of the planar portion20aand the inclined surfaces20band20cof the second buffer layer22.

After irradiating the amorphous silicon layer30′ with the laser beam to melt the amorphous silicon layer30′, the crystallization occurs as the amorphous silicon layer30′ cools. The crystallization may begin in the area of the amorphous silicon layer30′ corresponding to the planar portion20ahaving a relatively low temperature, and proceed in a horizontal direction and along the inclined surfaces20band20c, which is a lateral growth.

Due to the lateral growth, crystalline silicon having a homogeneous crystal structure may be formed, and a semiconductor device with high performance may be formed.

Referring toFIGS. 2E and 2F, after the crystallization and patterning of the amorphous silicon layer30′ (seeFIG. 2c) to form the crystalline silicon layer30, the gate insulating layer40that covers the crystalline silicon layer30is formed and then the gate electrode50is formed on the gate insulating layer40.

At least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) may be provided on the gate insulating layer40, and then the gate electrode50may be formed by forming a pattern thereon.

After forming the gate electrode50, the interlayer insulating layer60is formed to cover the gate electrode50. The gate insulating layer40and the interlayer insulating layer60may have a single layer or multi-layer structure formed of an inorganic material such as SiOx, SiNx, SiON, Al2O3, TiO2, Ta2O5, HfO2, ZrO2, BST, and PZT.

After forming the interlayer insulating layer60, the contact hole may be formed in the interlayer insulating layer60and the gate insulating layer40. At least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) are provided on the interlayer insulating layer60, and pattern is provided thereon to form the source electrode70S and the drain electrode70D ofFIG. 1.

Although not illustrated in drawings, the manufacturing method of the semiconductor device100according to an embodiment may further include the forming of the source area and the drain area, wherein after forming the gate electrode50, doping is performed at the both sides of the crystalline silicon layer30using the gate electrode50as a mask to form the source area and the drain area.

FIG. 3illustrates a schematic cross-sectional view of a display apparatus according to an embodiment. A display apparatus1is disposed on the substrate10, and may include the buffer layer20that includes the inclined surfaces20band20cat the upper surface thereof; the crystalline silicon layer30disposed on the buffer layer20; the gate electrode50disposed on but insulated from the crystalline silicon layer30; the source electrode70S and the drain electrode70D that are each electrically connected to the crystalline silicon layer30; a pixel electrode110electrically connected to one of the source electrode70S and the drain electrode70D; an intermediate layer120that is disposed on the pixel electrode110and includes an organic light-emitting layer; and an opposite electrode130disposed on the intermediate layer120.

The substrate10may be a transparent glass substrate or a plastic substrate. The buffer layer20may be disposed on the substrate10, and the buffer layer20according to an embodiment may include the first buffer layer21disposed on the substrate10, and the second buffer layer22disposed on the first buffer layer21.

The first buffer layer21and the second buffer layer22may be, for example, silicon nitride (SiNx) and silicon oxide (SiOx), respectively. The buffer layer20may be formed as a single layer, or as three or more layers. The first buffer layer21and the second buffer layer22may be formed not only of silicon nitride and silicon oxide, but of other inorganic materials or organic materials, and the second buffer layer22may include, for example, a material with a low refractive index.

The upper surface of the first buffer layer21may be planar, and the upper surface of the second buffer layer22may include the planar portion20aand the inclined surfaces20band20c. The inclined surfaces20band20cmay include the first inclined surface20band the second inclined surface20cthat each extend outward from the planar portion20a.

The inclined surfaces20band20care inclined at a predetermined angle θ to the substrate10, and each angle θ between the substrate10and the inclined surfaces20band20cmay be in a range of about 17.5 to less than about 70 degrees.

The inclined surfaces20band20cin the buffer layer20are formed to totally reflect the incident laser beam, which may help increase the crystallization efficiency when crystallizing the amorphous silicon layer30′ (seeFIG. 2c) into crystalline silicon. Each angle θ between the substrate10and the inclined surfaces20band20cmay be larger than the critical angle for the total reflection, i.e., 17.5 degrees, while each angle θ between the substrate10and the inclined surfaces20band20cmay be less than 70 degrees, and the amorphous silicon layer30′ may be crystallized evenly including the boundary area between the planar portion20aand the inclined surfaces20band20c.

The crystalline silicon layer30is disposed on the buffer layer20. The crystalline silicon layer30may be formed by the crystallization and patterning of the amorphous silicon layer30′ (seeFIG. 2c), and the slope of the upper surface of the crystalline silicon layer30, which overlaps with the inclined surfaces20band20cin the buffer layer20in a plan view, is smaller than that of the inclined surfaces20band20c. By forming this structure, the amount of laser beam reflected on the upper surface of the amorphous silicon layer30′ (seeFIG. 2c) may be reduced.

The upper surface of the crystalline silicon layer30according to an embodiment may be, for example, planar. In an embodiment, the upper surface of the crystalline silicon layer30may not be planar.

The inclined surfaces20band20cmay be only formed in the area of the buffer layer20corresponding to the crystalline silicon layer30, and another area of the display apparatus1may not have inclined surfaces, e.g., any inclined surfaces. The inclined surfaces20band20care formed to facilitate the crystallizing of the amorphous silicon layer30′ (seeFIG. 2c) in an effective manner, and may be only formed in the area of the buffer layer20corresponding to the crystalline silicon layer30by etching and no pattern may be formed in the other area of the buffer layer20.

The gate electrode50, the source electrode70S and the drain electrode70D may be disposed on the crystalline silicon layer30; the gate insulating layer40may be interposed between the crystalline silicon layer30and the gate electrode50; and the interlayer insulating layer60may be interposed between the gate electrode50, and the source electrode70S and between the gate electrode50and the drain electrode70D.

The source electrode70S and the drain electrode70D each may be electrically connected to the source area and the drain area in the crystalline silicon layer30via the contact hole formed in the interlayer insulating layer60and the gate insulating layer40.

A planarization layer80that covers the source electrode70S and the drain electrode70D may be disposed on the interlayer insulating layer60, and an organic light-emitting device (OLED) including the pixel electrode110, the intermediate layer120including the organic light-emitting layer, and the opposite electrode130may disposed on the planarization layer80.

A pixel defining layer90that defines a pixel area may disposed at the both sides of the pixel electrode110. The planarization layer80may include a via hole, and through the via hole, the pixel electrode110may be electrically connected to one of the source electrode70S and the drain electrode70D.

The pixel electrode110may be a reflective electrode including a reflective layer. For example, the reflective layer may include at least one selected from silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir) and chromium (Cr), and on the reflective layer, a transparent or semitransparent electrode layer formed of at least one selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO) may be further disposed

For example, the pixel electrode110may be formed as a three-layer structure of ITO/Ag/ITO.

The intermediate layer120may include, for example, at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL) and an electron injection layer (EIL) as well as an organic light-emitting layer. The intermediate layer120may further include various function layers.

The opposite electrode130may be a transparent or semitransparent electrode formed as a thin film having a thickness of a few to dozens of nm, and at least one material selected from silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), calcium (Ca), copper (Cu), LiF/Ca, LiF/Al, MgAg and CaAg.

According to an embodiment illustrated inFIG. 3, the display apparatus1is, for example, a top-emitting type OLED having the pixel electrode110as the reflective electrode, and the opposite electrode130as the transparent or semitransparent electrode. In other words, a display apparatus according to another embodiment of may be a bottom-emitting type OLED having a pixel electrode as a transparent or semi-transparent electrode, and an opposite electrode as a reflective electrode.

FIG. 4illustrates a schematic cross-sectional view of a display apparatus according to another embodiment. A display apparatus2illustrated inFIG. 4has the same structure as the display apparatus1of an embodiment illustrated inFIG. 3except for a buffer layer220and a crystalline silicon layer230.

The buffer layer220included in the display apparatus2ofFIG. 4may be formed as a single layer. The upper surface of the buffer layer220may include a planar portion220a, and the inclined surfaces220band220c. The first inclined surface220band second inclined surface220cincluded in the upper surface of the buffer layer220may each extend outward from the planar portion220a. Each angle between the substrate10and the inclined surfaces220band220cin the buffer layer220may be in a range of about 17.5 degrees to 70 degrees.

The inclined surfaces220band220cin the buffer layer220may be formed on the whole surface of the display apparatus2. A crystalline silicon layer230may be formed by the process of the crystallization and patterning of the amorphous silicon layer, wherein in the process, the inclined surfaces220band220cof the buffer layer20that are formed on the whole surface of the display apparatus2may facilitate the crystallizing of the amorphous silicon layer in an effective manner.

The crystalline silicon layer30may be formed on the buffer layer220, and the slope of the upper surface of the crystalline silicon layer30, which overlaps with the inclined surfaces220band220cin the buffer layer220in a plan view, may be smaller than that of the inclined surfaces.

FIG. 5illustrates a schematic cross-sectional view of a display apparatus according to another embodiment. A liquid crystal layer320may be disposed between the substrate10and an upper substrate370. The liquid crystal layer320may be disposed between a first pixel electrode310and the second pixel electrode330, and may block or transmit light emitted from a back light (not shown) by adjusting an orientation of the liquid crystal depending on the voltage applied to the first pixel electrode310an the second pixel electrode330.

The first pixel electrode310may be disposed on the planarization layer80. The first pixel electrode310may be electrically connected to the drain electrode70D through the via hole of the planarization layer80, and may include a transparent conductive material.

The upper substrate370may be, for example, a transparent glass substrate or a plastic substrate, similar to the substrate10. The upper substrate370may have a color filter350, a black matrix360, an overcoat layer340and the second pixel electrode330.

The color filter350may be formed of, for example, a photo-organic material, and may impart a color to the light that is emitted from the back light and passes through the liquid crystal layer320. The black matrix360may prevent the light that passes through the color filter350from being mixed and interrupted.

The overcoat layer340may be disposed on the color filter350and the black matrix360, and may protect the color filter350. The overcoat layer340may include material such as acrylic-based epoxy.

The second pixel electrode330may be disposed on the overcoat layer340and include a transparent conductive material. The second pixel electrode330may directly apply a voltage to the liquid crystal layer320along with the first pixel electrode310.

By way of summation and review, in laser annealing using a laser beam, the laser beam may be emitted onto an amorphous semiconductor layer, which may be formed as a film on a substrate, to locally heat the semiconductor layer, and then the semiconductor layer may be crystallized as the semiconductor layer cools. The mobility of a carrier may be increased in the crystallized semiconductor layer, and the thin film transistor may show high performance.

As described above, according to the one or more of the above embodiments, the semiconductor device, the manufacturing method thereof and the display apparatus may increase a crystallization efficiency of a laser beam during a laser annealing, and may induce a lateral growth of a grain.