Recording element substrate and recording head including recording element substrate

A recording element substrate includes a recording element array including a plurality of recording elements, a drive circuit configured to drive the recording elements, and a heater located to surround the recording element array as viewed in a direction perpendicular to a surface of the recording element substrate and located above or below a capacitive element or a resistive element included in the drive circuit as viewed on a cross section of the recording element substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a recording element substrate and a recording head including the recording element substrate.

2. Description of the Related Art

FIG. 8is a diagram illustrating the structure of a recording element substrate discussed in Japanese Patent Application Laid-Open No. 2002-79671. A substrate300includes a heater and a drive circuit that are integrally formed by a semiconductor process. A heater array302A including a plurality of heaters is arranged along an ink supply port301. A sub-heater3011heats the substrate300and a temperature detection unit304detects the temperature of the substrate300. Power or signals are input from the outside of the substrate300to terminals305. A drive circuit303drives the heaters.

As described above, the drive circuit303includes a metal-oxide semiconductor (MOS) transistor whose operation characteristics are changed by heat. Therefore, when the sub-heater3011is arranged close to the MOS transistor, the operation of the MOS transistor is likely to be affected by heat generated from the sub-heater3011.FIG. 12is a graph illustrating the relationship between a variation in voltage (horizontal axis) between the gate and the source of the MOS transistor and a variation in drain current (vertical axis). When the temperature is changed, voltage-current characteristics are changed.

The operation of a logic circuit is also affected by the temperature. For example, a variation in the speed of a circuit was simulated. As a result of the simulation, one period was about 65 ns (nanosecond) at a temperature of 25° C. and one period was about 90 ns at a temperature of 100° C. The period at a temperature of 100° C. was 1.5 times longer than that at a temperature of 25° C. Thus, when the response speed of a logic circuit is decreased by heat, an error is likely to occur in the operation of the logic circuit.

SUMMARY OF THE INVENTION

The present invention is directed to a recording element substrate including a heater capable of preventing the influence of heat generated from a sub-heater on a circuit of the recording element substrate and controlling the temperature of the recording element substrate.

According to an aspect of the present invention, a recording element substrate includes a recording element array including a plurality of recording elements, a drive circuit configured to drive the recording elements, and a heater located to surround the recording element array as viewed in a direction perpendicular to a surface of the recording element substrate and located above or below a capacitive element or a resistive element included in the drive circuit as viewed on a cross section of the recording element substrate.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a layout diagram illustrating the surface of a recording element substrate100according to a first exemplary embodiment of the invention as viewed from the vertical direction (upper or lower side). Heaters102constitute a heater array102A arranged as illustrated inFIG. 1. A drive circuit103includes a transistor or a logic circuit that drives the heaters102. The logic circuit includes, for example, a shift register and a decoder. A wiring area104includes a power line for supplying power and a signal line for supplying a control signal. An external signal or power is input through terminals105. The wiring area104includes a signal line for supplying the signal from the terminal105to the drive circuit103. A capacitive element109is connected to, for example, the signal line or the power line that connects the terminal105and the drive circuit103to prevent the influence of noise on the signal.FIG. 13is a diagram illustrating a portion of a recording head according to the first exemplary embodiment. Ink is supplied from an ink supply port101and is then discharged from a nozzle1201by heat generated by the heater102.

A heater (sub-heater)106is a heating unit that heats the substrate100to control the temperature of the substrate100. The heater (sub-heater)106is arranged to surround the ink supply port101on the surface of the substrate in a plan view ofFIG. 1. In addition, the heater106is provided above the capacitive element109. This is because the capacitive element (capacitor)109is less affected by heat than a MOS transistor.

FIG. 2is an enlarged view illustrating a portion of the drive circuit103illustrated inFIG. 1. A description of reference numerals101to107which have been described with reference toFIG. 1will not be repeated. For simplicity of description, a description of other signal lines will not be given. The drive circuit103illustrated inFIG. 1includes logic circuits, such as a decoder108, a driving voltage generation circuit110, a data output circuit111, a latch circuit112, and a shift register113. The data output circuit111checks data signals input from the outside to the shift register113. A logic voltage VDD is input to the terminal105and is then supplied to the decoder108through a power line114. The capacitive element109is connected to the power line114. The power line114for supplying the logic voltage VDD is connected to logic circuits, such as the latch circuit112and the shift register113.

FIG. 6Ais a cross-sectional view illustrating the recording element substrate100. The capacitive element109is arranged below the heater (sub-heater)106. The recording element substrate100includes a silicon substrate201, an oxide film202, a polysilicon film203, a boron-doped phospho-silicate glass (BPSG) (an insulating film)204, an insulating film205, and an aluminum wiring line207. Since the MOS transistor118is located away from the sub-heater106, the influence of heat generated from the heater (sub-heater)106on the MOS transistor can be reduced.

FIG. 10is a functional block diagram illustrating the recording element substrate100. For simplicity of illustration, some signal lines or some circuit blocks are not illustrated. The recording element substrate100includes the terminals105, and a voltage VH (24 V), a voltage VHT (24 V), a voltage VDD (5 V), a signal DATA, a signal CLK, a signal LT, and a signal HE are input to the terminals105. The above-mentioned logic circuit includes the decoder108, the latch circuit112, the shift register113, a level converter (LVC)121, and AND circuits122A and123A.

For example, the heater array102A, which includes128heaters102, performs a time-division driving operation in which 16 heaters are driven at the same time, and 128 heaters are driven for 8 driving timings. Therefore, the shift register113stores 16-bit data. The latch circuit112latches the data output from the shift register113.

The driving voltage generation circuit110receives the voltage VHT (24 V), generates a voltage VHTM (14 V), and outputs the generated voltage VHTM. The AND circuit122A is provided to correspond to the heater102.

FIG. 11is a diagram illustrating a portion of the drive circuit103. For simplicity of description,FIG. 11is an equivalent circuit diagram illustrating a circuit for driving one heater. The MOS transistor (MOSFET)120is controlled to drive the heater102. The AND circuit122performs an AND operation on the signal input from the decoder108and the signal input from the logic circuit123A and outputs the operation result to the level converter121. The level converter (LVC)121receives the voltage VHTM and converts the output voltage from the AND circuit122into a driving voltage for the transistor120. The heater102is supplied with the voltage VH. The AND circuit122is supplied with the voltage VDD. The MOS transistor120is connected to the ground (GND).

Next, a case in which the first exemplary embodiment (FIGS. 1 and 2) is not implemented will be described with reference toFIG. 9. The drive circuit includes a recording element drive circuit407, a data output circuit411, a capacitive element (capacitor)409, a driving voltage generation circuit410, a decoder408, a latch circuit412, and a shift register413. In the structure illustrated inFIG. 9, a description of the same components as those illustrated inFIG. 1orFIG. 2will not be repeated. In the structure illustrated inFIG. 9, the data output circuit411is arranged such that the heater (sub-heater)406overlaps with the data output circuit411without considering the influence of heat generated from the heater (sub-heater)406. Therefore, the operation of the data output circuit411is affected by heat generated from the heater406.

On the other hand, as in the first exemplary embodiment (FIGS. 1 and 2), the capacitive element109is arranged such that the heater106overlaps the capacitive element109. This is because the capacitive element (capacitor)109is less affected by heat than the MOS transistor, as described above. A resistive element109A may be provided instead of the capacitive element109. Therefore, as illustrated inFIG. 6B, the resistive element109A may be arranged to overlap the heater106. For example, a POL resistor provided on a polysilicon layer is used as the resistive element109A.

FIG. 3is a block diagram illustrating the circuit layout of a recording element substrate100according to a second exemplary embodiment of the invention. A description of the same components as those illustrated inFIG. 1will not be repeated, and only components different from those illustrated inFIG. 1will be described.

The capacitive element109is provided between the heater array102A and the terminal105. The heater (sub-heater)106is provided between the heater array102A and the drive circuit103. Similar to the first exemplary embodiment, in the second exemplary embodiment, the heater106(sub-heater) is provided above the capacitive element109.

FIG. 4is an enlarged view illustrating a portion of the drive circuit103illustrated inFIG. 3. A description of the same components as those in the first exemplary embodiment will not be repeated. For simplicity of description, other signal lines are not illustrated. A voltage VHT is input to the terminal105and is then supplied to the recording element drive circuit107through a power line115. The capacitive element109is connected to the power line115.

FIG. 5is a diagram illustrating the recording element drive circuit107illustrated inFIG. 4. The recording element drive circuit107includes, for example, a shift register/latch506, a decoder505, a shift register/latch508, a transistor120, and logic elements503and504. For simplicity of description, the driving voltage generation circuit110is not illustrated.

A recording head divides a plurality of heaters into a plurality of (M) groups and time-divisionally drives the groups of heaters. Each group includes N heaters102. One heater selected from each group is driven at one driving timing. Then, the heaters to be driven are switched at each driving timing.

The shift register506stores data (DATAB) for selecting the heaters in each group. The decoder505decodes the data stored in the shift register506and outputs the decoded signal to a signal line507. The shift register508stores 1-bit data allocated to each of the groups (G1, G2, . . . , GM). The shift register/latch508is arranged in the direction in which the heaters102are arranged. The decoder505outputs a signal for selecting one of N heaters. The decoder505selects the heater102to be driven and the transistor120is driven according to the value of the data stored in the shift register/latch508.

Similar to the first exemplary embodiment, as an element that is relatively less affected by heat, instead of the capacitive element109, the resistive element109A may be provided below the heater106.

FIG. 7is a block diagram illustrating the circuit layout of a recording element substrate100according to a third exemplary embodiment of the invention. Components denoted by reference numerals100to109are similar to those illustrated inFIG. 1orFIG. 3. The capacitive element109maybe arranged in the direction in which the heaters102are arranged.

The heater (sub-heater)106is provided to surround the ink supply port101on the surface of the substrate in a plan view ofFIGS. 1 and 3. An endless heater106may be used or a portion of the heater106may be cut.

The circuit element that is arranged to overlap the heater106is not limited to the capacitive element109or the resistive element109A as long as it is relatively less affected by heat.

This application claims priority from Japanese Patent Application No. 2008-296697 filed Nov. 20, 2008, which is hereby incorporated by reference herein in its entirety.