Method and/or apparatus for stabilizing the frequency of digitally synthesized waveforms

An apparatus comprising a first circuit, a second circuit, a third circuit and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to (i) a modulated signal and (ii) a seed value. The second circuit may be configured to generate a first control signal in response to the demodulated signal. The third circuit may be configured to generate a second control signal in response to (i) the first control signal and (ii) a compensation signal. The fourth circuit may be configured to generate the seed value in response to the second control signal.

FIELD OF THE INVENTION

The present invention relates to frequency synthesis generally and, more particularly, to a method and/or apparatus for stabilizing the frequency of digitally synthesized waveforms.

BACKGROUND OF THE INVENTION

In a conventional Direct Digital Synthesis (DDS) approaches, a digital waveform is synthesized by accumulating a value equal to a fraction of pi every clock cycle. The value is stored in an accumulator. An output of the accumulator is translated into a digital waveform through a fixed or programmable look up table that contains the desired waveform for all values of pi. With such a conventional architecture, the frequency of a synthesized waveform depends on a programmed value equal to the desired radian change per clock cycle (i.e., DDS seed) and the clock frequency used to accumulate the DDS seed values. With conventional approaches, if either the DDS seed or the clock frequency changes, the frequency of the synthesized waveform of the output also changes. Therefore, if a system clock is phase locked to an external reference source, the stability of the DDS waveform frequency is directly proportional to the stability of the system clock.

It would be desirable to have a system to synthesize a digital waveform to maintain a constant output frequency independently of variations in the system clock frequency.

SUMMARY OF THE INVENTION

The present invention concerns an apparatus comprising a first circuit, a second circuit, a third circuit and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to (i) a modulated signal and (ii) a seed value. The second circuit may be configured to generate a first control signal in response to the demodulated signal. The third circuit may be configured to generate a second control signal in response to (i) the first control signal and (ii) a compensation signal. The fourth circuit may be configured to generate the seed value in response to the second control signal.

The objects, features and advantages of the present invention include providing a method and/or apparatus for stabilizing the frequency of digitally synthesized waveforms that may (i) allow phase lock loop clocks to produce stable carrier signals for applications such as radio frequency (RF) modulators, (ii) compensate for variations in the synthesized waveform, (iii) differentiate between frequency deviations in the quantized signal and deviations in the quantization period, (iv) compensate for the synthesized waveform in amplitude demodulation in video decoders, (v) compensate for the synthesized waveform in coherent spectral translation of intermediate frequencies (IF) down to baseband frequencies and/or (vi) generate a fixed frequency, such as a frequency modulated (FM) or amplitude modulated (AM) carrier.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIG. 1, a diagram of a circuit100illustrating a direct digital synthesis (DDS) technique is shown. The circuit100generally comprises a block (or circuit)102and a block (or circuit)104. The circuit102may present a signal (e.g., A) to the circuit104. The signal A may be generated in response to an input signal (e.g., DDS_SEED) and a clock signal (e.g., CLK). The signal CLK may be a system clock signal oscillating at a predetermined frequency. The circuit104may generate a signal (e.g., OUT) in response to the signal A.

The circuit102generally comprises a numerically controlled oscillator (NCO). The circuit104generally comprises a sine table. The signal OUT may be a synthesized signal having a target frequency. The frequency of the signal OUT may depend on (i) the magnitude of the signal DDS_SEED (e.g., expressed in radians change per clock period) and (ii) the frequency of the clock signal CLK. The signal DDS_SEED may be calculated using the following formula: DDS_SEED=(desired frequency of synthesized signal/DDS clock frequency)*2^N where N is an integer equal to the number of bits used in the NCO102.

Referring toFIG. 2, a diagram of a circuit150illustrating a modulation of baseband signals using a DDS technique is shown. The circuit150generates an output signal (e.g., OUT_MOD) in response to an input signal (e.g., IN_BASE). The signal OUT_MOD may be a modulated signal. The signal IN_BASE may be a baseband signal. The circuit150generally comprises a circuit102′, the sine table104, a block (or circuit)106and a block (or circuit)108. The circuit150generates the signal OUT_MOD in response to the signal IN_BASE, a clock signal (e.g., CLK) and a signal (e.g., CARRIER_SEED). The circuit106may be implemented as a low pass filter (LPF) The circuit108may be implemented as a multiplier circuit. The circuit108generates the signal OUT_MOD in response to a signal MOD from the sine table104and the output of the circuit106. The circuit150may be used to digitally modulate the signal IN_BASE received by the low pass filter106. In one example, the low pass filter106changes the signal BASEBAND to a desired signal bandwidth before being modulated by the circuit108.

Referring toFIG. 3, a diagram of a circuit200is shown illustrating the demodulation of modulated signals using a DDS technique. The circuit200may generate an output signal (e.g., OUT_DEMOD) in response to an input signal (e.g., IN_MOD). The signal OUT_DEMOD may be a demodulated signal. The signal IN_MOD may be a modulated signal. The circuit200generally comprises a circuit102″, a sine table104′, a circuit110and a circuit112. The circuit110may be implemented as a phase detector circuit. The circuit112may be implemented as a loop filter circuit. The demodulated signal OUT_DEMOD may be steered by the loop filter112. In one example, the frequency of the DDS waveform (the signal OUT_DEMOD) may be dependent on the sum of the initial signal (e.g., DDS_SEED)+/−an error signal generated by the loop filter112. When used to generate a fixed frequency, such as a frequency modulated (FM) or amplitude modulated (AM) carrier, the circuit200needs the period of the signal CLK to remain stable to avoid varying the output frequency in response to variations in the frequency of input clock signal CLK.

In one example, a 10 MHz carrier (e.g., DEMOD) may be generated with the NCO102′ clocked at 100 MHz (e.g., by the clock signal CLK) using a 32-bit register phase accumulator signal (e.g., PHASE) presented to the sine table104. One or more bits of the register may be used. The signal DDS_SEED may be: seed—10=(106/1006)*2^32 or transposing, desired frequency =(seed—10 /2^32)*1006. If the frequency of the clock signal CLK changes by +1% to 101 MHz, the value of the desired frequency of the signal DEMOD may also change by 1% to 10.1 MHz. Hence, it may be difficult to modulate or demodulate a signal at a fixed carrier frequency with any sort of fidelity using a time varying clock.

Referring toFIG. 4, a diagram is shown illustrating the effect on signal modulation using a DDS design. The frequency of the signal DEMOD for the modulated signal may vary depending upon the clock frequency. For applications such as digital video encoders, the variation in the frequency of the carrier may cause the color subcarrier frequency to go outside the pull-in range of the PLL within the television set. If the subcarrier frequency is outside the pull-in range, the displayed signal may be displayed in monochrome.

Referring toFIG. 5, a diagram is shown illustrating demodulation using a DDS design. The modulated signal OUT_DEMOD may be at a fixed carrier frequency. In one example, the frequency of the demodulation signal generated by the DDS may vary due to changes in the DDS clock frequency. This may cause asymmetric sidebands in the demodulated baseband signal.

Referring toFIG. 6, a circuit300illustrating demodulation using a clock compensated DDS technique is shown. The circuit300may generate an output signal (e.g., OUT_DEMOD) in response to an input signal (e.g., IN_MOD). The signal OUT_DEMOD may be a demodulated signal. The signal IN_MOD may be a modulated signal. The circuit300generally comprises a circuit302, a circuit304, a circuit306and a circuit308. The circuit302may be implemented as a phase detector. The circuit304may be implemented as a loop filter. The circuit306may be implemented as a numerically controlled oscillator (NCO) or a digitally controlled oscillator. The circuit308may be implemented as a sine table. To overcome the challenges presented by time varying clocks, the change in the frequency of the clock signal CLK may be used to directly scale the input to the NCO306. The NCO306may then be used by the sine table308to maintain a stable frequency of the signal OUT_DEMOD.

The phase detector302generally comprises a circuit310and a circuit312. The circuit310may be implemented as a multiplier circuit. The circuit312may be implemented as a low pass filter circuit. The loop filter304may be implemented as a multiplier circuit320, a multiplier circuit322and an adder circuit324. The NCO306may be implemented as a register circuit330, an adder circuit332, an adder circuit334and an adder circuit336. However, the various components used to implement the phase detector302, the loop filter304and the NCO306may be varied to meet the design criteria of a particular implementation. The adder circuit336may generate a signal (e.g., A′) in response to the signal A and a compensation signal (e.g., SEED_COMPENSATION). The adder circuit334may generate a signal (e.g., A″) in response to the signal A′ and the signal DDS_SEED. The adder circuit332may generate a signal (e.g., NCO_PHASE) in response to the signal A″ and the signal A′″. The register circuit330generally generates the signal A′″ in response to the signal CLK and the signal NCO_PHASE. The sine table308may generate a signal (e.g., DEMOD) in response to the signal NCO_PHASE. The signal DEMOD may be a seed value used by the phase detector302.

The adder circuit336may correct the magnitude of the programmed signal DDS_SEED to compensate for changes in the frequency of the signal CLK. While a demodulator circuit has been described, a modulator circuit may be implemented in a similar manner to produce a stable carrier frequency in the presence of an unstable clock. In one example, the desired frequency may be given by: desired frequency=((seed—10* (100/101))/2^32)*106=106.

The frequency of a Direct Digital Synthesis (DDS) waveform may be directly proportional to the rate of change of a radian value into a lookup table308. The frequency may be a fixed sub-multiple of the system clock signal CLK. To maintain a constant DDS output frequency when the frequency of the system clock CLK is locked to an external reference, a deviation of the clock signal CLK may be calculated and the magnitude of the signal DDS_SEED may be modified accordingly. The circuit300may use a Phase Lock Loop (PLL) error term to generate the signal SEED_COMPENSATION. The PLL error term may be directly proportional to the change in frequency of the signal CLK to scale the nominal value of the signal DDS_SEED. The scaled signal DDS_SEED may then be added to the original DDS seed (e.g., the signal A) so that the sum of the two seed values maintains the desired ratio of the frequency of the signal OUT_DEMOD to nominal clock frequency of the signal IN_MOD.

Referring toFIG. 7, a diagram illustrating a circuit400illustrating a modulation of a baseband signal using a clock compensated DSS technique is shown. The circuit400generally comprises a circuit402, a circuit404, a circuit406, and a circuit408. The circuit408may be similar to the circuit306ofFIG. 2. The signal NCO_PHASE may be used by the sine table406to generate the signal MOD. The circuit404may generate the signal OUT_MOD in response to the signal MOD and the output of the circuit402.

In an alternate approach, for DDS applications using a fixed crystal reference, the number of cycles generated by the circuit300over a period of time may be measured against a system reference. The difference between the desired number of cycles and the actual number generated may be used to scale the original value DDS_SEED to compensate for errors in the external crystal frequency. If an output of an MPEG is connected to a digital composite video encoder (DENC), the clock variation due to Program Clock Recovery (PCR) may generate a chrominance subcarrier which deviates more than +/−100 Hz away from nominal. Such a deviation may cause some picture monitors to lose color lock. The degree of clock variation may be calculated directly from the PCR recovery logic, and in a similar way to a PLL, could be used to directly scale the chrominance subcarrier SEED programmed into a DENC.