NOR flash memory device and method for fabricating the same

Embodiments of a NOR flash memory and method for fabricating the same are provided. Bit lines can be formed as self-aligned source and drain regions between adjacent first polysilicon patterns. Contacts for the source and drain regions can be provided according to bit line instead of per cell. Word lines can be formed as second polysilicon patterns, which are used as control gates, and are provided perpendicular to the longitudinal axis of the bit lines. During formation of the second polysilicon patterns, a dielectric film and exposed regions of the first polysilicon patterns can be etched to form floating gates below the second polysilicon patterns.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims the benefit under 35 U.S.C. §119 of Korean Patent Application No. 10-2007-0081597, filed Aug. 14, 2007, which is hereby incorporated by reference in its entirety.

BACKGROUND

Non-volatile memory has the advantage that stored data is not lost even when a power supply is interrupted. As a result, it is often used for storing data in systems, such as a personal computer (PC) basic input/output system (BIOS), a set top box, a printer, and a network server. Recently, non-volatile memory is being used in digital cameras and cellular phones.

One common non-volatile memory is an electrically erasable programmable read-only memory (EEPROM) type flash memory device capable of electrically erasing data in a memory cell in a lump manner or according to sector unit. During a programming operation for such a flash memory device, channel hot electrons from in a drain region to accumulate the electrons in a floating gate, thereby increasing the threshold voltage of a cell transistor.

During an erase operation, the flash memory device generates a high voltage between a source, substrate, and the floating gate to discharge electrons accumulated in the floating gate, thereby lowering the threshold voltage of the cell transistor.

With the rapid progress of high integration, the reduction of the cell size is needed. However, since it is difficult to secure a margin in a process, a further reduction is difficult to accomplish.

BRIEF SUMMARY

Embodiments of the present invention provide a NOR flash memory device and method for fabricating the same.

A NOR flash memory device according to an embodiment can include a gate formed on a semiconductor substrate, the gate configured having first polysilicon patterns aligned in a row, a dielectric film on the first polysilicon patterns, and a second polysilicon pattern on the dielectric film and aligned over the first polysilicon patterns. A plurality of electrodes can be provided in the semiconductor substrate in a column form between adjacent first polysilicon patterns. Each electrode column can be provided with contacts at an end portion.

A method for fabricating a NOR flash memory device according to an embodiment can comprise: forming a tunnel oxide film on a semiconductor substrate; forming first polysilicon patterns on the tunnel oxide film; forming electrode lines on the semiconductor substrate between adjacent first polysilicon patterns by performing an ion implantation process on the semiconductor substrate using the first polysilicon patterns as a mask; forming a dielectric film and second polysilicon patterns on the semiconductor substrate on which the tunnel oxide film and the first polysilicon pattern are formed; and forming contacts at an end of each electrode line.

DETAILED DESCRIPTION

Hereinafter, embodiments of a NOR flash memory device and a method for fabricating the same will be described with reference to the accompanying drawings.

When the terms “on” or “over” are used herein, when referring to layers, regions, patterns, or structures, it is understood that the layer, region, pattern or structure can be directly on another layer or structure, or intervening layers, regions, patterns, or structures may also be present. When the terms “under” or “below” are used herein, when referring to layers, regions, patterns, or structures, it is understood that the layer, region, pattern or structure can be directly under the other layer or structure, or intervening layers, regions, patterns, or structures may also be present.

In the drawings, the thickness and size of each layer may be exaggerated or schematically shown or omitted for convenience and clarity for explanation. Also, the size of each component is not necessarily to scale.

A NOR flash memory device can provide an external address bus for read operations, allowing random-access capabilities. In addition, cells are connected in parallel to the bit lines, which allows cells to be read and programmed individually. Erasing and writing operations of a NOR flash memory device proceeds on a sector-by-sector basis.

FIG. 6is a cross-sectional view of a NOR flash memory device according to an embodiment andFIG. 7is a perspective view of a NOR flash memory device according to an embodiment.

Referring toFIGS. 6 and 7, a NOR flash memory device according to an embodiment includes a gate80formed on a semiconductor substrate10and configured of first polysilicon patterns32, a dielectric film40, and a second polysilicon pattern60; a plurality of electrodes18in a line form in the semiconductor substrate10between adjacent first polysilicon patterns32; and contacts (see reference70ofFIG. 8) formed on each electrode18line.

As shown inFIG. 5b, the dielectric film40can be formed of an oxide-nitride-oxide (ONO) film configured of a stack of a first oxide film42, a nitride film44, and a second oxide film46. The first oxide film42can be provided such that a region of the first oxide film42contacting the electrodes18of the semiconductor substrate10is thicker than a region of the first oxide film42contacting the first polysilicon patterns32.

According to embodiments, the electrodes18can be provided in an intersecting pattern with the second polysilicon pattern60. For example, the second polysilicon patterns60can be formed perpendicular to the longitudinal axis of the electrode lines18.

A method of fabricating a NOR flash memory device will be described with reference toFIGS. 1-7.

First, referring toFIG. 1, an N-well12and a P-well14can be formed in a semiconductor substrate10. Although not shown, the semiconductor substrate10may include epitaxial layers.

The N-well can be formed by implanting ions, such as arsenic (As) or phosphorous (P), at high concentration into the substrate10, and the P-well can be formed by implanting ions, such as boron (B), at low concentration into the substrate10.

Referring toFIG. 2, a tunnel oxide film20and a first polysilicon film30can be formed on the semiconductor substrate10.

The tunnel oxide film20is utilized when programming (hot carrier injection) and erasing (Fouler Nordheim tunneling (FN tunneling)). Therefore, in certain embodiments, a high quality oxide film can be formed by a wet oxidation process.

Referring toFIG. 3, the first polysilicon film30can be patterned to form lines of first polysilicon patterns32separated from each other by a predetermined interval.

The first polysilicon pattern32can be used as a floating gate.

At this time, a coupling ratio can be increased by minimizing the interval between the first polysilicon patterns32.

In the conventional flash memory device contacts are formed between floating gates so that a design margin is needed for forming the contact between the floating gates.

However, according to embodiments of the present invention, since the electrodes for source/drain regions are formed in the semiconductor substrate, it is possible to reduce the conventional contact margin.

Therefore, a high integration of the flash memory device can be realized by minimizing the interval between the first polysilicon patterns32.

As shown inFIG. 4, an ion implantation process can be performed over the semiconductor substrate10on which the first polysilicon pattern32is formed to form ion implantation layer patterns16.

In one embodiment, the ion implantation process can be performed by implanting arsenic (As) ions at a dose of 1×1015˜5×1015atoms/cm2and an energy of about 20˜40 KeV using the first polysilicon patterns32as the mask.

Since the ion implantation ion is performed using the lines of the first polysilicon patterns32as the mask, the ion implantation patterns16are formed by a self-align method without requiring a further mask.

The ion implantation layer patterns16are activated by a heat treatment process so that they can be used as the electrodes (see reference18ofFIG. 5a).

Referring toFIGS. 5aand5b, a dielectric film40can be formed on the semiconductor substrate10including the first polysilicon patterns32.

The dielectric film40can be formed of an oxide-nitride-oxide (ONO) where the first oxide film42, the nitride film44, and the second oxide film46are sequentially formed.

The dielectric film40performs a role of isolating the upper and lower polysilicon patterns.

The first oxide film42can be formed, for example, by a thermal oxidation process. The nitride film44can be formed, for example, by a low pressure chemical vapor deposition (LP-CVD) process. The second oxide film42can be formed, for example, by a high temperature oxide (HTO) through a chemical vapor deposition (CVD) process.

In the thermal oxidation process for forming the first oxide film42, a diffusion phenomenon of the ion implantation patterns16can be activated to from the electrodes18.

Accordingly, the electrodes18can be formed by a self-align method using the first polysilicon patterns32. Therefore, conformance of an overlay with the first polysilicon pattern32being the floating gate is not required.

Furthermore, after forming the ion implantation layer patterns16, the ion implantation layer16can be activated by the thermal oxidation process for forming the first oxide film42without requiring a separate thermal process for activation.

Also, referring toFIG. 5b, when performing the thermal oxidation process for forming the first oxide film42, the speed of the thermal oxidation occurs faster at the region where the ion implantation layer patterns16are formed so that the region42acontacting the electrodes18of the semiconductor substrate10is formed to be thicker than the region42bcontacting the first polysilicon patterns32.

Because the region42acontacting the electrodes18of the semiconductor substrate10is formed to be thicker than the region42bcontacting the first polysilicon patterns32, damage to the substrate where the electrodes18are formed can be inhibited during the etching process for forming the control gate (described later). Therefore, it is possible to inhibit an increase of resistance in the electrodes18caused by etching damage.

In a specific embodiment, the first oxide film42of the region42bcontacting the first polysilicon pattern32can be formed to a thickness of about 100 Å and the first oxide film42of the region contacting the electrode18of the semiconductor substrate10can be formed to a thickness of about 250˜300 Å.

Referring toFIG. 6, the second polysilicon pattern60can be formed on the semiconductor substrate10on which the first polysilicon pattern32and the dielectric40are formed. The first polysilicon pattern32, the dielectric film40, and the second polysilicon pattern60provide a gate80.

According to an embodiment, a second polysilicon film can be formed on the substrate10. Then, a pattern mask for forming the second polysilicon patterns60can be provided through, for example, a photolithography process. The second polysilicon film can be etched to form the second polysilicon patterns60. In further embodiments, the exposed dielectric40and the exposed regions of the first polysilicon patterns32can be removed.

In the etching process, because the first oxide film42of the region42acontacting the electrode18of the semiconductor substrate10is thickly formed, damage to the electrodes18can be inhibited.

The second polysilicon pattern60can be used as a control gate to excite charges in the first polysilicon patterns32formed below so that the second polysilicon pattern60performs a role of applying bias voltage for charging and discharging.

Referring toFIG. 7, the control gate (the second polysilicon pattern60) can be used as a word line (WL) and the electrode18can be used as a bit line (BL).

In a further embodiment, a spacer (not shown) can be formed on a side wall of the gate80and an interlayer isolating film (not shown) can be formed on the semiconductor substrate10on which the gate80and the spacer are formed. A contact (see reference70ofFIG. 8) connected to each electrode18can be formed through the interlayer isolating film.

At this time, one contact can be formed for each electrode18used as the bit lines.

FIGS. 8 to 11are views for explaining the operation of the NOR flash memory device according to an embodiment.

FIG. 8is a schematic plan view of the NOR flash memory device arranged according to an embodiment andFIG. 9is a view for explaining a programming operation.

As shown inFIG. 8, the NOR flash memory device is formed so that the electrode18and the second polysilicon pattern60used as the control gate are aligned in intersecting lines.

A contact70can be formed on each electrode18at an end region of an electrode line18on an outer side of the second polysilicon pattern lines60.

The control gate (second polysilicon pattern60) can be used as the word line (WL) and the electrode18can be used as the bit line (BL).

In the NOR flash memory device according to an embodiment, to program the C region, the BL0and BL3electrodes are floated, the BL1electrode is grounded, and the BL2electrode is applied with 5V.

The WL0, WL2, and WL3electrodes of the control gates (second polysilicon patterns60) are grounded, the WL1electrode is applied with 9V, and the P-well region14of the semiconductor substrate10is grounded.

As shown inFIG. 9, which shows a cross-section including the C region, the ground and 5V is applied to the channel of the C region (using BL1and BL2) to generate the hot carriers and at the same time 9V is applied to the WL1electrode, so that the hot carriers from the channel of the C region are injected to the floating gate (first polysilicon pattern32) for programming.

At this time, no programming occurs in the A region even with the voltage of 9V applied to the WL1electrode and the ground applied to the channel of the A region from BL1because BL0is floating.

In addition, no programming occurs in the B region even with the voltage of 5V applied to the channel of the B region and the 9V applied to the WL1electrode because BL3is floating.

The ground and the 5V is applied to the channel of the D region and the E region, generating the hot carriers, but the WL0and the WL2electrodes are grounded so that the program operation is not performed for those regions.

FIG. 10is a schematic plan view of the NOR flash memory device arranged according to an embodiment andFIG. 11is a view for explaining an erase operation.

In the NOR flash memory device according to an embodiment, in order to erase the programmed C region, the BL0and BL3electrodes are floated, the BL1electrode is grounded, and the BL2electrode is applied with 9V.

The WL0, WL2, and WL3electrodes of the control gates are grounded, the WL1electrode is applied with −9V, and the P-well region14of the semiconductor substrate10is applied with 9V.

As shown inFIG. 11, the ground and 9V are applied to the channel of the C channel and at the same time −9V is applied to the WL1electrode and 9V is applied to the P-well region14of the semiconductor substrate10to discharge electrons that were injected to the floating gate during the programming operation. The discharging occurs through F-N tunneling.

Table 1 shows applied voltage for operations of the NOR flash memory device according to a specific embodiment.

The electrode18can be a source or a drain according to the operating cell. Therefore, the source and drain distinctions provided in the table represents the particular bit line being the electrode18for a cell.

As described above, because the electrode being the bit line is self-aligned using the floating gate, the alignment of the floating gate and the active area should conform.

Also, since the electrodes are formed by implanting ions using the floating gate as the mask, a separate mask is not needed. In addition, by forming an initial oxide film for an ONO film using a thermal oxidation process, a separate heat treatment process after the ion implantation is also not required.

Further, by providing contacts according to bit lines instead of per cell, the process margin can be increased and the integration of the cell is increased, making it possible to implement compactness of the memory device.

By utilizing the NOR type structure, high speed operation can be implemented, and by provided the reduced number of contacts as with a NAND type flash memory, it is possible to have advantage of both the NOR type and the NAND type flash memories.

According to embodiments, the oxide film of the ONO film contacting the electrode regions is formed thicker than the portions of the oxide film contacting the other regions so that the electrode is protected when performing a subsequent etching process during forming the control gates. Therefore, it is possible to inhibit the increase in the resistance of the bit line due to etching damage.

According to an embodiment, each cell is separated by the electrodes without requiring the forming of shallow trench isolation between cells, making it possible to reduce the size of the cell and increase the integration of the memory device.