Low-dropout (LDO) regulator with a feedback circuit

A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

BACKGROUND

Reference voltage generators, such as low-dropout (LDO) regulators, often are used in semiconductor devices. For instance, an LDO regulator is typically used to provide a well-specified and stable direct-current (DC) voltage. Generally, a LDO regulator is characterized by its low dropout voltage, which refers to a small difference between respective input voltage and output voltage. A typical application for an LDO regulator is a memory device, such as a resistive random access memory (RRAM).

In order to save area, a shared and centralized LDO is commonly adopted for multiple memory macros. However, wire resistance of a connector increases with an increase in the number of connected macros, and voltage drop becomes worse with such an increased number of macros. Such voltage drop due to wire resistance across different macros may cause near-far effect and voltage drop, resulting in reduced write performance.

DETAILED DESCRIPTION

A low-dropout (LDO) voltage regulator provides a specified and stable direct-current (DC) output voltage (e.g., a regulated output voltage) based on an input voltage (e.g., an unregulated input voltage) with a low dropout voltage. The “dropout voltage” used herein refers to a minimum voltage across the (LDO) voltage regulator to maintain the output voltage being regulated. Even though the input voltage, provided by a power source, falls to a level very near that of the output voltage and is unregulated, the LDO voltage regulator can still produce the output voltage that is regulated and stable. Such a stable characteristic enables the LDO voltage regulator to be used in a variety of integrated circuit (IC) applications, for example, a memory device, a power IC device, etc. To save area of the IC circuits, a shared and centralized LDO is typically utilized for multiple macros of the IC circuit. However, using one centralized LDO causes different voltage levels for the different macros because of a voltage drop across a connector.

The disclosure provides a LDO voltage regulator circuit with a location-aware feedback loop to supply a stable output voltage to multiple macros while addressing voltage drop and near-far effect due to wire resistance across different macros. The LDO voltage regulator circuit described herein includes a LDO voltage regulator and a feedback circuit which dynamically monitors an instantaneous voltage level at each macro connection node and provides the instantaneous voltage to the LDO voltage regulator as a feedback response so as to avoid the above-mentioned issues while simultaneously maintaining the LDO voltage regulator's stable output voltage. In some embodiments, the feedback circuit includes a feedback path from each macro connection nodes to a comparator of the LDO voltage regulator. The comparator of the LDO voltage regulator compares the instantaneous voltage level of the each micro connection nodes to a reference voltage level, and adjusts an output voltage of the LDO voltage regulator in real time. The LDO voltage regulator circuit will now be described in greater detail in the following sections of the disclosure.

FIG. 1is a diagram of a low-dropout (LDO) voltage regulator circuit100, in accordance with various embodiments. As shown inFIG. 1, LDO voltage regulator circuit100includes a LDO voltage regulator102, a load104, and a feedback circuit112. Load104is connectable to LDO voltage regulator102at a connection node110via a load switch SW_PU. Connection node110is located on a connector114. That is, the load switch SW_PU is switched-on to connect load104to a connection node110of LDO voltage regulator102. Moreover, the load switch SW_PU is switched-off to disconnect load104from connection node110of LDO voltage regulator102. Feedback circuit112is connectable to connection node110of LDO voltage regulator102.

LDO voltage regulator102includes a first input terminal106and an output terminal108. Connector114is connected to output terminal108. In some embodiments, LDO voltage regulator102is configured to receive an input voltage VCH_REF (also referred to as Vin) at first input terminal106and provide a stable output voltage VCH (also referred to as Vout) at output terminal108. The input voltage VCH_REF may be provided by a power source (e.g., a battery (not shown)) that may be unregulated. The voltage level of the output voltage VCH may be lower than the voltage level of the input voltage VCH_REF by a small amount (e.g., from about 100 mV to about 1 V), which is generally referred to as LDO voltage regulator's102dropout voltage. As the name “low-dropout” implies, such a dropout voltage is typically selected to be substantially small.

In example embodiments, feedback circuit112is configured to assist in maintaining of the output voltage VCH of LDO voltage regulator102at a substantially stable value while various levels of load104are coupled to connection node110. For example, feedback circuit112is configured to provide an instantaneous voltage level at connection node110as a feedback to LDO voltage regulator102. LDO voltage regulator102, based on the received instantaneous voltage level, can adjust the output voltage VCH to maintain a predetermined voltage level at connection node110. Details of the LDO voltage regulator102and feedback circuit112are discussed in further detail below.

FIG. 2illustrates an exemplary circuit diagram of the LDO voltage regulator102, in accordance with various embodiments. It is noted that the illustrated embodiment ofFIG. 2is merely a simplified circuit diagram provided for explanation. That is, LDO voltage regulator102can be implemented as any of a variety of circuit diagrams of an LDO voltage regulator to include other circuit elements and/or circuits, for example, a voltage divider, a Miller compensation circuit, one or more switches, etc.

As shown inFIG. 2, LDO voltage regulator102includes an amplifier202and a current source212. Amplifier202includes a first input terminal204and a second input terminal206. First input terminal204and second input terminal206are also referred to as a non-inverting input terminal and an inverting input terminal respectively. Amplifier202further includes an amplifier output terminal208. Amplifier output terminal208is connected to a first internal node210of LDO voltage regulator102. In example embodiments, amplifier202is an operational amplifier (also referred to as an op-amp or opamp). In some examples, amplifier202is also referred to as an error amplifier.

Current source212is connected in series with amplifier202. For example, amplifier output terminal208is connected to current source212via first internal node210. In example embodiments, current source212is formed by a transistor214. In some embodiments, current source212is implemented as a p-type metal-oxide-semiconductor (PMOS) transistor214. However, it is understood that current source212may be implemented as any of a variety of transistors and/or circuits. Further to the embodiment where current source212is implemented as PMOS transistor214, a gate of transistor214is coupled amplifier output terminal208via first internal node210. A source of transistor214is coupled to a transistor supply voltage (for example, Vdd), and a drain of transistor214is coupled to a second internal node216of LDO voltage regulator102. Second internal node216is connected to output terminal108of LDO voltage regulator circuit100. In example embodiment, transistor214is symmetric. That is, the source of transistor214can be coupled to second internal node216and the drain of transistor208can be coupled to the supply voltage.

As discussed above, since the illustrated embodiment of LDO voltage regulator102inFIG. 2is merely a simplified example, operation of LDO voltage regulator102is briefly described as follows. To operate LDO voltage regulator102, in some embodiments, a source current Is (also referred to a standby current Is) is generated by current source212and sinked at second internal node216. The source current Is establishes the output voltage VCH at second internal node216. The output voltage VCH is controlled by the input voltage VCH_REF at the non-inverting input terminal of amplifier202. More specifically, when the voltage level of VCH is relatively high, an error voltage (i.e., the output of amplifier202) received by the gate of transistor214proportionally increases. The increase in the error voltage reduces source-gate voltage (Vsg) of transistor214(that is, current source212), which causes a decrease in the source current Is. As a result, the voltage level of the output voltage VCH decreases. Through an opposite mechanism, a relatively low output voltage level pulls down the error voltage, then increases the source current Is, and in turn increases the voltage level of the output voltage VCH. In other words, LDO voltage regulator102is configured to control the voltage level of the output voltage VCH to be at a substantially stable value, and such a stable value is controlled to be close to the voltage level of the input voltage VCH_REF.

FIG. 3is a diagram generally illustrating another example LDO voltage regulator circuit100which includes a plurality of macros at a plurality of connection nodes in accordance with some embodiments. As shown inFIG. 3, LDO voltage regulator circuit100includes LDO voltage regulator102operative to provide a stable supply voltage to load104.

Load104may include a plurality of macros. For example, load104includes a first Macro[0], a second Macro[1], continuing to a (n−1)thMacro[N−1], and a nthMacro[N]. Each of the plurality of macros is connectable to one of a plurality of connection nodes of LDO voltage regulator circuit100. LDO voltage regulator102is configured to provide a stable supply voltage to each of the plurality of macros. For example, load104includes a memory device, and LDO voltage regulator102is configured to provide the supply voltage when the memory device is accessed, e.g., read or written to, by a user. When the memory device (i.e., load104) is accessed, LDO voltage regulator102may generate a voltage for a word line of the memory device to read out a data bit from memory cells of the memory device. Further, according to some embodiments, LDO voltage regulator circuit100is also activated to provide the source current Is.

For example, and as shown inFIG. 3, LDO voltage regulator circuit100includes a plurality of connection nodes, that is, a first connection node110[0], a second connection node110[1], continuing to a (n−1)thconnection node110[N−1], and a nthconnection node110[N]. The plurality of connection nodes are located on connector114associated with output terminal108of LDO voltage regulator102. In some examples, the plurality of connection nodes may be equally spaced on the connector. Although, the plurality of connection nodes are shown to be located on one connector114which is connected to output terminal108of LDO voltage regulator102, it will be apparent to a person with ordinary skill in the art after reading this disclosure that the plurality of connection nodes may be located on more than one connectors connected to output terminal108of LDO voltage regulator102.

A length of connector114between consecutive connection nodes is represented by a resistor. For example, a length of connector114between first connection node110[0] and second connection node110[1] is represented by first resistor R[0] continuing to a length of connector114between (n−2)thconnection node (not shown) and (n−1)thconnection node110[N−1] being represented by (n−1)thresistor R[N−1]. Finally, a length of connector114between (n−1)thconnection node110(N−1) and nthconnection node110[N] is represented by nthresistor R[N].

In example embodiments, the plurality of macros are connectable to a corresponding connection node of the plurality of connection nodes of LDO voltage regulator circuit100through a corresponding load switch. For example, as shown inFIG. 3, LDO voltage regulator circuit100includes a plurality of load switches SW_PUs, for example, a first load switch SU_PU[0], a second load switch SW_PU[1], continuing to a (n−1)thload switch SW_PU [N−1], and a nthload switch SW_PU [N]. First Macro[0] is connectable to first connection node110[0] though first load switch SW_PU[0]. Similarly, second Macro[1] is connectable to second connection node110[1] through second load switch SW_PU[1], continuing to (n−1)thMacro[N−1] which is connectable to (n−1)thconnection node through (n−1)thload switch SW_PU[N−1]. Finally, nthMacro[N] is connectable to nthconnection node110[N] through nthload switch SW_PU[N]. In example embodiments, the plurality of load switches SW_PUs can be transistors, for example, a PMOS transistor, an NMOS transistor, etc. However, other types of switches are within scope of the disclosure.

In examples, a load switch SW_PU is switched-on to connect a corresponding macro to a corresponding connection node and is switched-off to disconnect the corresponding macro from the corresponding connection node. For example, first load switch SW_PU[0] is switched-on to connect first Macro[0] to first connection node110[0]. Moreover, first load switch SW_PU[0] is switched-off to dis-connect first Macro[0] from first connection node110[0]. Similarly, second load switch SW_PU[1] is switched-on to connect second Macro[1] to second connection node110[1] and is switched-off to dis-connect second Macro[1] from second connection node110[1]. Continuing to, (n−1)thload switch SW_PU[N−1] which is switched-on to connect (n−1)thMacro[N−1] to (n−1)thconnection node110[N−1] and is switched-off to dis-connect (n−1)thMacro[N−1] from (n−1)thconnection node110[N−1]. Finally, nthload switch SW_PU[N] which is switched-on to connect nthMacro[N] to nthconnection node110[N] and is switched-off to dis-connect nthMacro[N] from nthconnection node110[N].

In example embodiments, each of the plurality connection nodes of LDO voltage regulator circuit100are connectable to a feedback node218via a plurality of feedback loops and a plurality of feedback switches of feedback circuit112. For example, feedback circuit112includes a first feedback loop FL[0], a second feedback loop FL[1], continuing to a (n−1)thfeedback loop FL[N−1], and a nthfeedback loop FL[N]. In addition, feedback circuit112includes a first feedback switch SW[0], a second feedback switch SW[1], continuing to a (n−1)thfeedback switch SW[N−1], and a nthfeedback switch SW[N]. In example embodiments, the plurality of feedback switches can be transistors, for example, a PMOS transistor, an NMOS transistor, etc. However, other types of switches are within scope of the disclosure.

First connection node110[0] is connectable to feedback node218though first feedback loop FL[0] and first feedback switch SW[0]. Similarly, second connection node110[1] is connectable to feedback node218through first feedback loop FL[1] and second feedback switch SW_PU[1], continuing to (n−1)thconnection node110[N−1] which is connectable to feedback node218through (n−1)thfeedback loop FL[N−1] and (n−1)thfeedback switch SW[N−1], and nthconnection node110[N] being connectable to feedback node218via nthfeedback loop FL[N] and nthfeedback switch SW[N].

In examples, one of the plurality of feedback switches SWs is switched-on to connect a corresponding connection node to feedback node218through a corresponding feedback loop and is switched-off to disconnect a connection node from feedback node218. For example, first feedback switch SW[0] is switched-on to connect first connection node110[0] to feedback node218and is switched-off to disconnect first connection node110[0] from feedback node218through first feedback loop FL[0]. Similarly, second feedback switch SW[1] is switched-on to connect second connection node110[1] to feedback node218and is switched-off to disconnect second connection node110[1] from feedback node218through second feedback loop FL[1]. Continuing to, (n−1)thfeedback switch SW[N−1] which is switched-on to connect (n−1)thconnection node110[N−1] to feedback node218and is switched-off to dis-connect (n−1)thconnection node110[N−1] from feedback node218through (n−1)thfeedback loop FL[N−1]. Finally, nthfeedback switch SW[N] which is switched-on to connect nthconnection node110[N] to feedback node218and is switched-off to dis-connect nthconnection node110[N] from feedback node218through nthfeedback loop FL[N].

When connected, each of the plurality of feedback loops is configured to provide an instantaneous voltage of a corresponding connection node to second input terminal206of amplifier202. For example, feedback node218is connected to second input terminal206of amplifier202. So, when connected to first connection node110[0], a first feedback loop FL[0] is configured to provide first instantaneous voltage VCH[0] of first connection node110[0] to second terminal206of amplifier202. Similarly, when connected to second connection node110[1], second feedback loop FL[1] is configured to provide a second instantaneous voltage VCH[0] of second connection node110[1] to second terminal206of amplifier202. This continues to (n−1)thfeedback loop FL[N−1] which when connected to (n−1)thconnection node110[N−1] provides a (n−1)thinstantaneous voltage VCH[N−1] of (n−1)thconnection node110[N−1] to second terminal206of amplifier202. Finally, nthfeedback loop FL[N] when connected to nthconnection node110[N] provides a nthinstantaneous voltage VCH[N] of nthconnection node110[N] to second terminal206of amplifier202.

In example embodiments, LDO voltage regulator102is operative to provide a predetermined supply voltage to each of the plurality of macros. For example, LDO voltage regulator102is operative to provide a first write voltage WR[0] to first Macro[0], a second write voltage WR[1] to second Macro[1], continuing to (n−1)thvoltage WR[N−1] to (n−1)thMacro[N−1], and nthwrite voltage WR[N] to nthMacro[N]. In example embodiments, each of the plurality of write voltages is substantially same or approximately equal to one another. That is, first write voltage WR[0] is substantially same as (or approximately equal to) second write voltage WR[1] which in turn is approximately equal to (n−1)thwrite voltage WR[N−1], which is approximately equal to nthwrite voltage WR[N].

In example embodiments, LDO voltage regulator102is configured to adjust the instantaneous voltage of the plurality of connection nodes based on the received feedback to maintain a voltage level at each of the plurality of connection nodes substantially or approximately equal to a corresponding write voltage level. For example, LDO voltage regulator102is operative to maintain a voltage level of first connection node110[0] approximately equal to first write voltage WR[0]. Similarly, LDO voltage regulator102is operative to maintain a voltage level of second connection node110[1] approximately equal to second write voltage WR[1], continuing to (n−1)thconnection node110[N−1] which is to be maintained at (n−1)thwrite voltage WR[N−1], and nthconnection node110[N] which is to be maintained at nthwrite voltage WR[N].

For example, amplifier202is operative to compare the instantaneous voltage with the input voltage VCH_REF, and current source212is operative to provide a predetermined source current Is to regulate the voltage level at the plurality of connection nodes. That is, amplifier202, based on a difference between the instantaneous voltage and the input voltage VCH_REF, is operative to increase or decrease the source current Is to increase or decrease the instantaneous voltage at one or more of the plurality of connection nodes.

In example embodiments, although the plurality of feedback loops are shown to be connected between the plurality of connection nodes and the plurality of load switches, it will be apparent to a person with ordinary skill in the art after reading this disclosure that the plurality of feedback loops can also be connected between the plurality of load switches and the plurality of macros instead of being connected between the plurality of connection nodes and the plurality of load switches. Moreover, although the plurality of feedback loops are shown to be connectable to the plurality of connection nodes through a plurality of feedback switches, it will be apparent to a person with ordinary skill in the art after reading this disclosure that the plurality of feedback loops can be connectable to the plurality of connection nodes via the plurality of load switches thereby obviating the need for the plurality of feedback switches.

For example,FIG. 4illustrates an example LDO voltage regulator circuit100minus feedback switches in accordance with some embodiments. As shownFIG. 4, the plurality of loops are connectable to the plurality of connection nodes through the plurality of load switches SW_PUs. For example, first feedback loop FL[0] is connectable to first connection node110[0] through first load switch SW_PU[0]. Similarly, second feedback loop FL[1] is connectable to second connection node SW_PU[1] through second load switch SW_PU[1], continuing to (n−1)thfeedback loop FL[N−1] which is connectable to (n−1)th connection node110[n−1] through (n−1)thload switch SW_PU[N−1], and nthfeedback loop FL[N] being connectable to nthconnection node110[N] through nthload switch SW_PU[N].

In examples, a load switch SW_PU is switched-on to connect both a corresponding macro and a corresponding feedback loop to a corresponding connection node and is switched-off to disconnect both the corresponding macro and the corresponding feedback loop from the corresponding connection node. For example, first load switch SW_PU[0] is switched-on to connect first Macro[0] and first feedback loop FL[0] to first connection node110[0]. Moreover, first load switch SW_PU[0] is switched-off to dis-connect first Macro[0] and first feedback loop FL[0] from first connection node110[0]. Similarly, second load switch SW_PU[1] is switched-on to connect second Macro[1] and second feedback loop FL[1] to second connection node110[1] and is switched-off to dis-connect second Macro[1] and second feedback loop FL[1] from second connection node110[1], and so forth.

In examples, multiple macros can be connected to each of the plurality of connection nodes of LDO voltage regulator circuit100. For example, a predetermined number of macros can be connected to each of the plurality of connection nodes.FIG. 5is a diagram generally illustrating an example LDO voltage regulator circuit100with multiple macros connected at each of the plurality of connection nodes in accordance with some embodiments. For example, and shown inFIG. 5, Macros[0:M] are connected to each of first connection node110[0], second connection node110[1], continuing to (n−1)thconnection node110[N−1], and nthconnection node110[N]. Although each of the plurality of connection nodes of LDO voltage regulator circuit100ofFIG. 5is shown to include a same number of macros (that is, M macros), it will be apparent to person with ordinary skill in the art after reading this disclosure that a different number of macros can be connected to one or more of the plurality of connection nodes.

In some examples, an alternative current (AC) compensation circuit can be provided in LDO voltage regulator circuit100.FIG. 6illustrates an example LDO voltage regulator circuit100with an AC compensation circuit602(also referred to as a frequency compensation circuit602). In example embodiments, AC compensation circuit602is connected in series with LDO voltage regulator102. For example, and as shown inFIG. 6, AC compensation circuit602is connected between first internal node210and second internal node216. AC compensation circuit602is configured to avoid an unintentional creation of positive feedback which may cause amplifier202of LDO voltage regulator102to oscillate. In addition, AC compensation circuit602is configured to control an overshoot and ringing in amplifier's202response. An example AC compensation circuit602is discussed in greater detail with reference toFIG. 7.

FIG. 7illustrates an example AC compensation circuit602in accordance with some embodiments of the disclosure. As shown inFIG. 7, AC compensation circuit602comprises a RC circuit having a trimmable register bank and a trimmable capacitor bank. For example, and as shown inFIG. 7, AC compensation circuit602includes a register bank702and a capacitor bank704. Register bank702is connected in series with capacitor bank704.

Register bank702includes a plurality of connectable resistors and a plurality of switches to connect or disconnect one or more of the plurality of connectable registers. For example, register bank702comprises a first connectable resistor Rc[0] and a first switch SW_R[0] to connect and disconnect first connectable resistor Rc[0] from the RC circuit, a second connectable resistor Rc[1] and a second switch SW_R[1] to connect and disconnect second connectable resistor Rc[1] from the RC circuit, continuing to a nthconnectable resistor Rc[N] and a nthswitch SW_R[N] to connect and disconnect nthconnectable resistor Rc[N] from the RC circuit. In addition, register bank702includes a bypass switch Rpass to bypass register bank702. For example, when switched-on, the bypass switch Rpass provides a direct path thereby bypassing the plurality of resistors of register bank702.

In example embodiments, register bank702is trimmable and a desired resistance value for register bank702is selected by connecting or disconnecting one or more of the plurality of connectable registers of register bank702. For example, first switch SW_R[0] is switched-on to connect first connectable resistor Rc[0] to the RC circuit and is switched-off to disconnect first connectable resistor Rc[0] from the RC circuit. In example embodiments, a number of connectable resistors connected to the RC circuit is dependent on load104of LDO voltage regulator circuit100. For example, the number of connectable resistors connected to the RC circuit is dependent on a number of macros in load104of LDO voltage regulator circuit100. In example embodiments, the plurality of switches of resistor bank702can be transistors, for example, a PMOS transistor, an NMOS transistor, etc. However, other types of switches are within scope of the disclosure.

Capacitor bank704comprises a plurality of connectable capacitors and a plurality of switches to connect or disconnect one or more of the plurality of connectable capacitors. For example, capacitor bank704comprises a first connectable capacitor Cc[0] and a first switch SW_C[0] to connect and disconnect the first connectable capacitor Cc[0] from the RC circuit, a second connectable capacitor Cc[1] and a second switch SW_C[1] to connect and disconnect the second connectable capacitor Cc[1] from the RC circuit, continuing to a nthconnectable capacitor Cc[N] and a nthswitch SW_C[N] to connect and disconnect the nthconnectable capacitor Cc[N] from the RC circuit. In addition, capacitor bank704includes a bypass switch Cpass to bypass capacitor bank704. For example, when switched-on, the bypass switch Cpass provides a direct path thereby bypassing the plurality of capacitors of capacitor bank702.

In example embodiments, capacitor bank704is trimmable and a desired capacitance value for capacitor bank704is selected by connecting or disconnecting one or more of the plurality of connectable capacitors of capacitor bank704. For example, first switch SW_C[0] is switched-on to connect first connectable capacitor Cc[0] to the RC circuit and is switched-off to disconnect first connectable capacitor Cc[0] from the RC circuit. In example embodiments, a number of connectable capacitors connected to the RC circuit is dependent on load104of LDO voltage regulator circuit100. For example, the number of connectable capacitors connected to the RC circuit is dependent on a number of macros in load104of LDO voltage regulator circuit100. In example embodiments, the plurality of switches of capacitor bank704can be transistors, for example, a PMOS transistor, an NMOS transistor, etc. However, other types of switches are within scope of the disclosure.

FIG. 8is a diagram800generally illustrating example voltages at connection nodes along a connector of LDO voltage regulator circuit100in accordance with some embodiments. First plot802ofFIG. 8illustrates a plot of voltages at the plurality of connection nodes along a connector of LDO voltage regulator circuit100and second plot804ofFIG. 8illustrates a plot of voltages at the plurality of connection nodes along a connector of a conventional regulator circuit. As shown by first plot802, the voltage at the plurality of connection nodes of LDO voltage regulator circuit100remains constant while with a number of connection nodes. However, and as shown by second plot804, the voltage at the connection nodes of a conventional regulator circuit drops with an increasing connection nodes.

FIG. 9is a flow diagram illustrating a method900for providing a supply voltage in accordance with some embodiments. Method900may be implemented in LDO voltage regulator circuit100or a chip comprising LDO voltage regulator circuit100. In addition, steps of method900may be stored as instructions which may be executed by a processor to implement method900.

At block910of method900, a supply voltage to a plurality of macros is provided by a low-dropout voltage regulator, for example, LDO voltage regulator102. The plurality of macros are connectable at a plurality of connection nodes on a connector connected to an output terminal of the low-dropout voltage regulator. For example, a plurality of macros (that is, first Macro[0], . . . , nthMacro[N]) are connectable to a plurality of connection nodes (that is, first connection node110[0], . . . , nthconnection node [N]). LDO voltage regulator102is operative to provide a supply voltage to the plurality of macros.

At block920of method900, an instantaneous voltage of a connection node of the plurality of connection is received through a feedback loop of a plurality of feedback loops. The plurality of feedback loops are connectable to the plurality of connection nodes. The instantaneous voltage is received at an amplifier of the low-dropout voltage regulator. For example, a plurality of feedback loops (that is, first feedback loop FL[0], . . . , nthfeedback loop FL[N]) are connectable to the plurality of connection nodes (that is, first connection node110[0], . . . , nthconnection node [N]). The instantaneous voltage is received at amplifier202of LDO voltage regulator102.

At block930of method900, a difference between the received instantaneous voltage and a reference voltage is determined. In example embodiments, the difference between the received instantaneous voltage and a reference voltage is determined by amplifier202. The received instantaneous voltage is provided at second input terminal206and the reference voltage is provided at first input terminal204of amplifier202which is operative to compare inputs and determine a difference between the inputs.

At block940of method900, an amount of a source current being sinked by a current source at the output terminal of the low-dropout voltage regulator is adjusted based on the determined difference. For example, an amount of the source current being sinked by current source212at output terminal108of LDO voltage regulator102is adjusted based on the difference between the received instantaneous voltage of a connection node and the reference voltage. Current source212is connected in series with amplifier202. Adjusting the amount of the source current being sinked by current source212includes adjusting the amount of the source current being sinked by current source212to maintain the supply voltage approximately equal to the reference voltage.

In accordance with some embodiments, a voltage regulator circuit comprises: a voltage regulator configured to provide an output voltage at an output terminal; a plurality of macros connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator; and a feedback circuit comprising a plurality of feedback loops connectable to the plurality of connection nodes, wherein a feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator, and wherein the voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

In some example embodiments, a voltage regulator circuit comprises: a voltage regulator configured to provide an output voltage at an output terminal; a connector connected to the output terminal, the connector comprising a plurality of connection nodes spaced along a length of the connector; a plurality of macros connectable at the plurality of connection nodes of the connector; and a plurality of feedback loops connectable at the plurality of connection nodes, wherein each of the plurality of feedback loops, when connected to a corresponding connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the corresponding connection node as a feedback to the voltage regulator, and wherein the voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the corresponding connection node approximately equal to a reference voltage.

In accordance with example embodiments, a method of providing a supply voltage comprises: providing, by a low-dropout voltage regulator, a supply voltage to a plurality of macros connectable at a plurality of connection nodes on a connector connected to an output terminal of the low-dropout voltage regulator; receiving an instantaneous voltage of a connection node of the plurality of connection nodes through a feedback loop of a plurality of feedback loops connectable to the plurality of connection nodes at an amplifier of the low-dropout voltage regulator; determining, by the amplifier, a difference between the received instantaneous voltage and a reference voltage; and adjusting, based on the determined difference, an amount of a source current being sinked by a current source at the output terminal of the low-dropout voltage regulator, wherein the current source is connected in series with the amplifier, and wherein adjusting the amount of the source current being sinked by the current source comprises adjusting the amount of the source current being sinked by the current source to maintain the supply voltage approximately equal to the reference voltage.