Video codec and method thereof

A video codec method is provided, for processing video data processed by a Discrete Cosine Transformation (DCT) operation, comprising: (a) if a transformation matrix having a plurality of coefficients comprises at least one non-integer coefficient among the coefficients, multiplying the transformation matrix by a multiplication factor α to make all coefficients of the transformation matrix integers, (b) estimating a compensation set, (c) performing a Column in Row out IDCT two-dimensional operation on the video data according to the transformation matrix and the compensation set, to obtain a compensated two-dimension operation result, (d) selectively dividing the compensated two-dimension operation result by α2 to obtain an IDCT operation result.

CROSS REFERENCE TO RELATED PATENT APPLICATION

This patent application is based on Taiwan, R.O.C. patent application No. 099123693 filed on Jul. 19, 2010.

FIELD OF THE INVENTION

The present invention relates to a video codec and method thereof.

BACKGROUND OF THE INVENTION

A conventional structure of a multimedia application, such as a video codec complying with H.264 specification, as shown inFIG. 1, includes a Discrete Cosine Transformation (DCT) operation circuit110, a Quantization (Q) unit120, an Inverse Quantization (IQ) unit130, and an Inverse DCT (IDCT) operation circuit140. The DCT operation circuit110acts in a Row in Column out (R→C) mode, and the IDCT operation circuit140also acts in a Row in Column out mode, and receives the output of the IQ unit130.

In practice, the DCT operation circuit110and the IDCT operation circuit140must operate complying with a specification, otherwise mismatch between an encoding path and a decoding path will occur, resulting in a “drifting” effect during video playback. However, in some cases, the R→C operation of the IDCT operation circuit140is not straightforward in data flow, and a transposition is needed, accordingly. In addition, the prior art needs an extra buffer135to store data temporarily, for transforming Column data outputted from the DCT operation circuit110into Row data to be inputted to the IDCT operation circuit140, thereby leading to both increases in processing time and cost of the video codec.

Therefore, an IDCT scheme for processing in a Column in Row out (C→R) mode, capable of real-time compensation, and requiring no extra buffer for temporarily storing data, so as to reduce processing time and cost in a video codec, is needed.

SUMMARY OF THE INVENTION

The present invention is aimed to provide a video codec and method thereof, capable of performing an IDCT in a Column in Row out (C→R) mode as well as real-time compensation.

According to one embodiment, a video codec method is provided, for processing video data processed by a Discrete Cosine Transformation (DCT) operation, including: (a) if a transformation matrix having a plurality of coefficients comprises at least one non-integer coefficient among the coefficients, multiplying the transformation matrix by a multiplication α to make all coefficients of the transformation matrix integers, (b) estimating a compensation set, (c) performing a Column in Row out IDCT two-dimensional operation on the video data according to the transformation matrix and the compensation set, to obtain a compensated two-dimension operation result, (d) selectively dividing the compensated two-dimension operation result by α2to obtain an IDCT operation result.

According to another embodiment of the present invention, a video codec is provided, for processing video data processed by a Discrete Cosine Transformation (DCT) operation, including: a DCT operation circuit, for performing a Row in Column out IDCT operation on the video data, to obtain a DCT operation result, a quantization circuit and an inverse quantization circuit, coupled to the DCT operation circuit, for performing a quantization operation and an inverse quantization operation on the DCT operation result, an IDCT operation circuit, coupled to the inverse quantization circuit, for performing a Column in Row out IDCT operation on the output of the inverse quantization circuit to generate an IDCT operation result; and a compensation circuit, coupled to the IDCT operation circuit, for providing a compensation set to the IDCT operation circuit to compensate the IDCT operation result.

Following description and figures are disclosed to gain a better understanding of the advantages of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In an embodiment of the present invention, column data outputted from a DCT operation circuit is inputted to a Column in Row out IDCT operation circuit (i.e., an IDCT operation circuit acting in a Column in Row out mode); as a result, no additional buffer memory ahead of the IDCT operation circuit is needed. However, due to limitations of the number of bits, an operation result of the Column in Row out IDCT operation circuit may have some errors in response to an order inversion and round-off/carry-in operations. Thus, in the embodiment of the present invention, the errors are calculated in advance and corrected.

In mathematics theory (where the number of bits is unlimited), either the IDCT operation circuit acts in the Row in Column out mode or in the Column in Row out mode, the operation result should be identical. However, in practice, because the number of bits of the video codec is limited, if a fractional rounding operation is performed, the operation result of the Column in Row out IDCT operation circuit may be different from that of the Row in Column out IDCT operation circuit.

FIG. 2is a function block diagram of a video codec according to an embodiment of the present invention. As shown inFIG. 2, the video codec comprises: a DCT operation circuit210, a quantization unit220, an inverse quantization unit230, an IDCT operation circuit240, and a compensation unit250. The compensation unit250inducts a compensation set Δ to an output of the IDCT operation circuit240, for obtaining a required correct result. Rounding mismatches resulted from an order inversion can be real-time corrected by utilizing the compensation unit250, and circuit area of the compensation unit250is much less than that of theFIG. 1required buffer135.

In the H.264 specification, the two-dimensional (2D) IDCT transformation is defined as Y=T●X●Tt.

FIG. 3AandFIG. 3Brespectively illustrate the Row in Column out (R→C) IDCT operation and the Column in Row out (C→R) IDCT operation. Yt=(T●X●Tt)t=T●Xt●Tt=Y′. In a floating-point operation in which the number of bits is unlimited, Y′ is equal to the transposition result of Y. However, in a design in which the number of bits is limited, if a transformation matrix T has at least a non-integer coefficient (such as ½), fraction rounding effects resulted from the order inversion must be considered. A situation that the transformation matrix T has non-integer coefficients is shown as follows:

In this situation, Y′ is not equal to the transposition result of Y (i.e., (Y′!=Yt)). That is to say, the transposition result of Y shown inFIG. 3Ais not equal to Y′ shown inFIG. 3B.

Therefore, in the embodiment, when the matrix input order is inverted from X to Xt, the following steps must be performed to correct the errors.

(1) Firstly, changing the non-integer coefficients of the transformation matrix into integer coefficients is performed. For example, in the above example, multiplying the transformation matrix T by 2, so that the coefficients (elements) of the obtained transformation matrix (2T) are all integers. Since the transformation matrix (2T) does not include any non-integer coefficients, no error occurs even when fraction rounding operations are performed. In regard toFIG. 3AandFIG. 3B,
Z=(2T)●X●(2T)t;
Z′=(2T)●Xt●(2T)t;
andZ=(Z′)t.

(2) Since the number of bits is limited, in the embodiment, the compensation set Δ is calculated in advance, according to transpose symmetry and a rule of the rounding operation. Therefore, a compensated result is determined as Y″=(Z′+Δ)/4.

(3) The compensated result Y″ may be regarded as the transposition result of the matrix Y, as if it is the two-dimensional (2D) transformation result of the matrix X (that is, as if it is the result obtained by the Row in Column out IDCT). Therefore, the relationship between the matrix Y″ and the matrix Y may be expressed as Y=(Y″)t.

Calculation of the compensation set Δ is depicted as follows.

In a fixed-point design, the result of right shifting the number X by one bit (that is, dividing the number X by 2 if the number X is expressed in binary) is equal to the result of subtracting the Least Significant Bit (LSB) thereof from the number X and then dividing it by 2. It can be expressed as following equation (a):
X>>1=½X=½(X−X[0])  (a)

Wherein, “X>>1” represents right shifting X by one bit, and X[0] represents the LSB of the number X.

In H.264 specification, the two-dimensional transformation of the Row in Column out IDCT is defined as Y=T●X●Tt.

Likewise, the two-dimensional transformation of the Column in Row out IDCT is defined as Y′=T●Xt●Tt.

Using the coefficient Y01of the above matrix Y as an example, as shown inFIG. 6.

As inFIG. 6, a one-dimensional (1D) compensation set and a two-dimensional (2D) compensation set are denoted respectively. The 1D compensation set and the 2D compensation set respectively include a set of coefficients of the matrix Y. The coefficient Y01can be expressed as:

Wherein, italic items belong to the 1D compensation set and boldface items belong to the 2D compensation set. After substituting the equation (a) into the 1D compensation set of the Y01(i.e. ½X30, ½X31, ½X32, ½X33), the Y01may be expressed as a combination of equations (b)˜(e):

When substituting equation (a) into equation (c) again, and simplifying the LSB of the 2D compensation set (X01+X11+X21+(½) X31) in equation (c) as X01[0] ^X11[0]^X21[0]^X31[1], Y01may be expressed as follows:

As Z is defined as Z=(2 T)●X●(2T)t, Z has no rounding effects, because the transformation matrix (2T) has no non-integer coefficients.

As shown inFIG. 7, the coefficient Z01of the matrix Z may be expressed as:

As Z′ is defined as Z′=(2T)●Xt●(2T)t, Z′ also has no rounding effects, because the transformation matrix (2T) has no non-integer coefficients, either.

As shown inFIG. 8, by comparison, it can be determined that Z′10is equal to Z01(i.e. Z′=Zt).

After scaling up the matrix Y by 4 times, the relationship between Y10and Z′10may be expressed as:

In the above expression, (−2X30[0]−X31[0]+2X32[0]+2X33[0]) represents the 1D compensation set, and (−2X01[0]^X11[0]^X21[0]^X31[0]) represents the 2D compensation set.

As described above, the following steps, concluded from the above, are utilized for compensation of mismatch resulted from the order inversion (i.e. changing the IDCT from the Row in Column out mode to the Column in Row out mode).

(1) Changing non-integer coefficients of the transformation matrix into integer coefficients is performed. For example, in the above example, multiplying the transformation matrix by 2, such that the coefficients of the obtained transformation matrix are all integers. Therefore, no errors occur even when fractional rounding operations are performed.
Z=(2T)●X●(2T)t;
Z′=(2T)●Xt●(2T)t;
andZ=(Z′)t.

(2) Since the number of bits is limited, calculating the compensation set Δ in advance (according to transpose symmetry and the rule of the rounding operation) is performed. Then, the compensated result is determined to be Y″=(Z′+Δ)/4.

(3) The compensated result Y″ may be regarded as the transposition result of the matrix Y, as if it is the two-dimensional (2D) transformation result of the matrix X (that is, as if it is the result obtained by the Row in Column out IDCT). Therefore, the relationship between the matrix Y″ and the matrix Y may be expressed as Y=(Y″)t. That is, Y=(Z′+Δ—1D+Δ—2D)t/4=(Z′+Δ)t/4, wherein, Δ—1D represents the one-dimensional compensation set, and Δ—2D represents the two-dimensional compensation set.

Referring toFIG. 4, taking the matrix Xtas an input matrix, the IDCT operation circuit performs the operation of Z′=(2T)●Xt●(2T)t, for obtaining Z′. Subsequently, after performing the compensation (adding Δ and being divided by 4) and the transposition, the matrix Y can be obtained. That is to say, Y=((Z′+Δ)/4)t. This operation is performed by the compensation unit.

With the above deducing process, it can be concluded that the one-dimensional compensation set (may be named as Δ—1D or 1D-term) and the two-dimensional compensation set (may be named as Δ—2D or 2D-term) are respectively expressed as follows:

FIG. 5AandFIG. 5Brespectively illustrate two possible implementations of the IDCT operation circuit240according to embodiments of the present invention. InFIG. 5A, the compensation unit242performs a one-dimensional compensation set compensation operation on the output of the column IDCT operation circuit241, and the compensation unit246performs a two-dimensional compensation set compensation operation on the output of the row IDCT operation circuit245. A transposition memory243is disposed between the column IDCT operation circuit241and the row IDCT operation circuit245. From the above descriptions, the detail operations of the column IDCT operation circuit241and the row IDCT operation circuit245are familiar to those skilled in the art, and are omitted herein.

As shown inFIG. 5B, the compensation unit250performs the one-dimensional compensation set compensation operation and the two-dimensional compensation set compensation operation on the output of the Row IDCT operation circuit245directly. The 1D-term and 2D-term listed in the above equations may respectively represent the one-dimensional compensation set and the two-dimensional compensation set inFIG. 5B. The one-dimensional compensation set Δ—1D and the two-dimensional compensation set Δ—2D inFIG. 5Acan be deduced from the above descriptions by those skilled in the art, and the detailed descriptions are omitted herein.

Although the compensation set is calculated by the above expressions, in other specifications, different transformation matrixes may be adopted. According to the above descriptions of the present invention, as to different specifications and different transformation matrixes, the present invention is also applicable. That is, changing all of the non-integer coefficients of the transformation matrix into integer coefficients (such as scaling up) for avoiding the mismatch resulted from a fixed-point calculation. Then, substituting compensation sets into the matrix according to the rounding operating principle and the transposing principle. Afterwards, transposing the matrix obtained by scaling down an operation result of the above steps, so as to acquire a required correct result.

In addition, although the above embodiment takes multiplying the transformation matrix by 2 as an example, the present invention is not limited to this. In other possible embodiments of the present invention, it can multiply all of the coefficients of the transformation matrix by α, such that all coefficients are integers, and divide the operation result by α2.