Uniform passivation method for conductive features

The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, and more particularly to methods of passivating metallization structures.

BACKGROUND

As technology has progressed, the demand for smaller semiconductor devices with improved performance has increased. A move is being made away from the traditional materials used in the past in semiconductor device designs, to meet these demands. For example, in the past, aluminum and aluminum alloys were most often used as a conductive material for conductive lines and vias in metallization structures, and silicon dioxide was used as an insulator between conductive lines and vias. However, as semiconductor devices have been scaled down in size, conductive features made from these materials have exhibited an increase in propagation delay.

For example, as minimum feature size decreases, RC time delay begins to limit the propagation delay of integrated circuits. RC time delay refers to the product of the metal resistance (R) and the dielectric capacitance (C). To reduce the RC time delay, low dielectric constant materials are being used as insulating materials, and there is a switch being made to the use of copper for interconnect materials, rather than aluminum.

One advantage of switching from aluminum to copper for semiconductor device interconnects is increased speed. Because the use of copper decreases the RC time delay due to the decreased resistivity of copper, devices can operate faster. There are also other advantages of switching to copper interconnects. For example, copper has a lower resistivity and increased electromigration resistance compared to aluminum. The reduced resistivity of copper results in the ability to manufacture thinner conductive lines, reducing the sidewall capacitance of the conductive lines. Also, because copper has improved electromigration resistance, higher current densities may be used.

RC time delays for interconnects can severely limit microprocessor clock speed. This limitation can be overcome by switching from aluminum to copper, and can be further improved by the use of copper in conjunction with low-k dielectric materials. Combining copper interconnects with low-k dielectric materials increases interconnect speed by reducing the RC time delay, for example.

However, there are some challenges in using copper for an interconnect material. For example, copper oxidizes at a relatively low temperature compared to aluminum, and the oxide formed on copper is not a high quality oxide, as is aluminum oxide. Copper does not form a self-passivating oxide on its surface, as aluminum does. Rather, portions of the copper interconnect remain exposed and are thus more susceptible to corrosion. It is difficult to directly etch copper, e.g., in a subtractive etch process, and thus, copper interconnects are often formed using damascene processes rather than by direct etching. A damascene process is one in which a dielectric material is deposited on a wafer, and then the dielectric material is patterned with the conductive line pattern. The conductive line pattern typically comprises a plurality of trenches, for example. The trenches are then filled in with conductive material, and a chemical-mechanical polish (CMP) process is used to remove the excess conductive material from the top surface of the dielectric material. The conductive material remaining within the dielectric material comprises the conductive lines.

Damascene processes are typically either single or dual damascene. In a single damascene process, one metal layer is formed at a time. For example, the insulating layer is patterned and then filled with metal, and a CMP process is used to form a single metal layer. In a dual damascene process, two adjacent horizontal insulating layers are patterned, e.g., using two lithography patterns in the two insulating layers or a single insulating layer that are filled with metal, and a CMP process is used to remove excess conductive material and form patterned conductive material in the insulating layers. For example, the patterns may comprise conductive lines in one insulating layer portion, and vias in the underlying insulating layer portion. The vias may connect the conductive lines to devices or interconnect layers that reside in the underlying insulating layer. Thus, in a dual damascene process, conductor and via trenches are filled in one fill step.

Because copper oxidizes easily, it may be desirable to treat the top surface of copper conductive lines, e.g., with a passivation layer. However, it can be challenging to form a passivation layer that is uniform over the entire surface of a semiconductor workpiece.

Thus, what are needed in the art are improved methods of forming passivation layers over conductive features of semiconductor devices.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention, which provide novel methods of passivating conductive features of semiconductor devices. Conductive features are treated with a novel treatment solution to improve the adhesive properties of the top surface of the conductive features, and improve selectivity of the passivation layer formation. The passivation layer formed is uniform, even, and completely covers the conductive features over the entire surface of a workpiece or individual die, for example.

In accordance with a preferred embodiment of the present invention, a method of treating a semiconductor device having at least one conductive feature formed thereon, before forming a passivation layer over the at least one conductive feature, includes treating a top surface of the at least one conductive feature with a treatment solution. The treatment solution comprises a cleaning solution and a chemical grafting precursor.

In accordance with another preferred embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a workpiece, forming at least one conductive feature over the workpiece, and treating at least a top surface of the at least one conductive feature with a treatment solution, the treatment solution comprising a cleaning solution and a chemical grafting precursor. A passivation layer is formed over the at least one conductive feature.

Advantages of preferred embodiments of the present invention include providing novel methods of forming passivation layers that are formed evenly and uniformly over conductive features across a surface of a semiconductor workpiece. The passivation layers may be formed before or after a CMP process, on conductive features formed by a damascene process or a subtractive etch process. A novel treatment solution is used to treat at least the top surface of the conductive features. The treatment solution improves the adhesive properties of the conductive features, provides improved selectivity between the conductive features and the insulating layer, and causes the formation of a uniform passivation layer across the surface of a semiconductor workpiece.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to preferred embodiments in a specific context, namely a semiconductor device having conductive features such as conductive lines and/or vias comprised of copper and/or copper alloys. The invention may also be applied, however, to semiconductor devices having conductive features comprised of other conductive materials, such as aluminum, aluminum alloys, tungsten, tungsten alloys, or other materials, as examples.

A less preferred embodiment of the present invention will first be described, with reference toFIGS. 1 and 2. A semiconductor device100that has been treated with a passivation layer108comprising a passivating material such as CoWP is shown in a cross-sectional view inFIG. 1, and in a top view inFIG. 2.

A problem with the passivation layer108shown is that the CoWP does not cover every conductive feature106evenly, as intended. For example, inFIG. 1, some conductive features106are covered with the passivation layer108, e.g., in region110, but other conductive features106are not covered with the passivation layer108, as shown in region112. Conductive features106at the edges of a die may not be covered with the passivation layer108, for example, because of uneven coverage or de-wetting of the passivation layer108material. FIG.2shows a top view of a semiconductor wafer or workpiece102. Entire or partial individual die in region114, e.g., at the edges and/or corners of the wafer102, may not be coated with the passivation layer108, as in other regions116of the wafer102, for example.

In the semiconductor device100shown inFIGS. 1 and 2, the passivation layer108is formed by forming a layer of CoWP after a CMP process to form the conductive lines106in a damascene method. The workpiece102may be pre-cleaned prior to forming the passivation layer108, using a low acid solution, such as a solution of a low concentration of H2SO4or citric acid, as examples. After the CMP process, if the conductive lines106are exposed to air, a thin layer of oxide may form over the conductive lines106, which may prevent the passivation layer108from forming on the conductive lines106. The pre-cleaning step removes the copper oxide that may have formed on the top surface of the conductive lines106during or after the CMP process, for example.

The passivation layer108is typically formed by dipping the dry wafer or workpiece102into a bath or by a chemical spray, as examples. However, the top surface of the conductive features106may not have good adhesive properties, resulting in non-uniformity of the passivation layer108formed across the top surface of the workpiece102. The conductive lines of die at the edges or corners of a workpiece may have more of the insulating layer104exposed, for example, preventing conductive lines106in those regions114from wetting with the passivation layer108material, as shown in a top view inFIG. 2. Thus, the passivation layer108is not uniform and may be thicker in some regions and thinner in other regions, and there may be no passivation layer108formed at all in some regions114of the workpiece102, as shown inFIG. 2.

Increasing the thickness of the passivation layer108in order to attempt to improve the coverage is undesirable, because the effective conductive line thickness is increased, which can increase the resistance. Changing the chemistry of the passivation layer108deposition process is also undesirable, because process changes would be introduced that could change the material of the passivation layer108, for example. For example, the passivation layer108may be formed by a selective deposition process, e.g., by selectively forming the passivation layer108on the conductive lines106but not on the insulating layer104. Changing the chemistry of the passivation layer108deposition process may result in the loss of the selectivity in the deposition process, for example.

Thus, what are needed are methods of forming passivation layers over conductive features of semiconductor devices that provide even, uniform coverage on conductive features across the entire surface of a workpiece.

Embodiments of the present invention achieve technical advantages by providing a method of forming a passivation layer that evenly coats conductive features of a workpiece and exhibits a reduced amount of de-wetting, or exhibits no de-wetting problems. Either before or after a CMP process, the top surface of a workpiece (e.g., having exposed conductive features) is cleaned with a novel treatment solution before the passivation layer is formed. The treatment solution prepares the top surface of the conductive features, improving the adhesive properties and making the passivation layer form more uniformly over the conductive features. The resulting uniform passivation layer protects the conductive lines from oxidation. The treatment solution prepares the top surface of the conductive lines and improves the uniformity in coverage of the passivation layer.

FIGS. 3 through 7show cross-sectional views of a preferred embodiment of the present invention at various stages of manufacturing. With reference now toFIG. 3, there is shown a semiconductor device200in a cross-sectional view including a workpiece202. The workpiece202may include a semiconductor substrate comprising silicon or other semiconductor materials covered by an insulating layer, for example. The workpiece202may also include other active components or circuits, not shown. The workpiece202may comprise silicon oxide over single-crystal silicon, for example. The workpiece202may include other conductive layers or other semiconductor elements, e.g., transistors, diodes, etc. Compound semiconductors, GaAs, InP, Si/Ge, or SiC, as examples, may be used in place of silicon. The workpiece202may also comprise a silicon-on-insulator (SOI) substrate.

An insulating layer204is formed over the workpiece. The insulating layer204may comprise a low dielectric constant (k) material, having a dielectric constant of about 3.5 or lower, in one embodiment. Alternatively, the insulating layer204may comprise a dielectric constant of about 3.5 or greater, in another embodiment, for example. The insulating layer204may comprise SiO2, SiON, or fluorinated silicon glass (FSG), as examples, although the insulating layer204may alternatively comprise other materials. The insulating layer204may comprise a thickness of about 5000 Angstroms or less, and in one embodiment, preferably comprises a thickness of about 2000 to about 4000 Angstroms, for example, although the insulating layer204may alternatively comprise other thicknesses. The insulating layer204may be deposited by chemical vapor deposition (CVD) or by a spin-on process, as examples, although alternatively, the insulating layer204may be formed using other methods.

The insulating layer204may then be patterned as shown inFIG. 4, e.g., by depositing a photoresist (not shown in the figures), patterning the photoresist, and using the photoresist as a mask while exposed portions of the insulating layer204are etched away. The photoresist is then removed. Alternatively, the insulating layer204may be directly etched, using ion beam lithography (IBL) or other direct etching technique, for example. The insulating layer204may be patterned using a single damascene process, as shown, or alternatively, the insulating layer204may be patterned using a dual damascene process, not shown. The trenches218formed in the insulating layer204may extend partially (as shown) or fully through the insulating layer204(not shown inFIG. 4; see conductive features206′ formed in insulating layer204′ inFIG. 9), for example.

A conductive material220is formed over the insulating layer204, as shown inFIG. 5. The conductive material220preferably comprises copper in one embodiment. For example, the conductive material220may comprise pure copper or a copper alloy. The conductive material220may also comprise other conductive materials, such as aluminum, aluminum alloys, tungsten, tungsten alloys, or other conductive materials, as examples. The conductive material220may be formed using electroplating, electro-less deposition, physical vapor deposition (PVD), or CVD, as examples, although alternatively, other deposition methods may be used to form the conductive material220. The conductive material220may include a liner formed over the patterned insulating layer204, not shown.

In this embodiment, the workpiece202is exposed to a CMP process to remove the excess conductive material220from over top surface of the insulating layer204and to form conductive features206formed in the insulating layer204, as shown inFIG. 6. For example, the workpiece202may be polished using a polishing pad with a slurry or using a dry process. The conductive features206may comprise conductive lines or conductive vias, as examples.

Next, the top surfaces of the conductive features206and the insulating layer204are treated with a treatment solution222in accordance with an embodiment of the present invention, as shown inFIG. 6. The treatment solution222preferably comprises a chemical that improves the adhesiveness of the top surface224of the conductive features206, yet does not damage or deleteriously affect the top surface of the insulating layer204, for example. The treatment solution222preferably comprises a cleaning solution combined with a chemical grafting precursor, and an optional leveling and wetting agent.

The cleaning solution of the treatment solution222preferably comprises a pre-rinse chemical comprising a low acid solution or a low concentration of acid. For example, the cleaning solution may comprise about 0.01 to 0.1% in weight of H2SO4. The cleaning solution of the treatment solution222may also comprise other acids, such as citric acid in a low concentration, e.g., about 0.01 to 0.1% in weight of citric acid. The remainder of the cleaning solution preferably comprises H2O or other solvents, such as ethanol or acetone, as examples, although alternatively, the remainder of the cleaning solution may comprise other chemicals.

The chemical grafting precursor of the treatment solution222preferably comprises vinyl pyridine, and alternatively may comprise phenyldiazonium salts, aryl bromides, or alkylenes, as examples, although other grafting precursors may also be used. The chemical grafting precursor of the treatment solution222is preferably adapted to recondition the top surfaces of224of the conductive features206and the top surface of the insulating layer204, resulting in improved passivation layer226(seeFIG. 7) formation selectivity on the conductive features206, but not the insulating layer204. The chemical grafting precursor of the treatment solution222is also preferably adapted to improve the coverage uniformity, e.g., providing a uniform passivation layer226across the workpiece202.

The optional leveling and wetting agent of the treatment solution222preferably comprises polyethylene glycol, and may alternatively comprise other chemicals, such as polypropylene glycol, or a block copolymer of propylene oxide and ethylene oxide, as examples, although other chemicals may also be used. The leveling and wetting agent of the treatment solution222preferably comprises a molecular weight ranging from about 400 to 20,000, for example, although alternatively, the molecular weight may comprise other values. For example, the leveling and wetting agent of the treatment solution222preferably comprises polyethylene glycol with molecular weight of about 1,000 to about 3,000, with a concentration of about 100 to about 300 parts per million (p.p.m.), in one embodiment. The leveling and wetting agent is preferably adapted to improve the coverage uniformity of the chemical grafting precursor of the treatment solution222, for example.

The top surfaces224of the conductive features206and the top surfaces of the insulating layer204are preferably rinsed with the treatment solution222for about 30 seconds to 1.5 minutes at room temperature, although alternatively, other times and temperatures may also be used. A pre-cleaning step is not required in this embodiment of the invention, as described with reference to the less preferred embodiment shown inFIGS. 1 and 2. Rather, the treatment solution222replaces the pre-cleaning step described in the embodiment shown inFIGS. 1 and 2. The novel treatment solution222is also adapted to remove residue left remaining on the top surfaces of the conductive features206and the insulating layer204, as well as any oxide that has formed on the top surface of the conductive features206.

Next, a passivation layer226is formed over the treated conductive features206. The passivation layer226preferably comprises a cobalt (Co) alloy in one embodiment. The passivation layer226may alternatively comprise other materials, such as a nickel (Ni) alloy. The passivation layer226preferably comprises Co or Ni combined with other materials, such as tungsten W, phosphorous (P), boron (B), or combinations thereof, in one embodiment. The passivation layer226preferably comprises Co, CoWP, CoP, CoWB, CoMoP, CoMoB, Ni, NiWP, NiP, NiB, NiMoP, or NiMoB, as examples, although the passivation layer226may alternatively comprise other materials. The passivation layer226preferably comprises about 90% or greater of Co or Ni, in one embodiment. The passivation layer226comprises a thickness of about 200 Angstroms or less, and preferably comprises a thickness of about 100 Angstroms, in one embodiment. The passivation layer226preferably comprises a conductive material.

The passivation layer226is preferably selectively formed on the conductive features206, e.g., by electro-less deposition. The passivation layer226may be formed by introducing aqueous Co, Ni, or alloy solutions thereof into a chamber with the workpiece202at a temperature of about 65 to 98 degree C., at a pressure of about 1 atmosphere, in a gas environment of N2, for about 2 to 10 minutes, as an example, although alternatively, the passivation layer226may be formed using other chemistries, temperatures, atmospheric pressures, gas environments, and other time periods.

If the conductive features206comprise copper, the passivation layer226preferably comprises Co or Ni because of the lower resistance and barrier properties of Co and Ni for copper diffusion. Furthermore, Co and Ni may be selectively formed over the conductive features206, e.g., the passivation layer226preferably is formed over the conductive features206and not over the insulating layer204. In addition, Co and Ni are advantageous materials to use for the passivation layer226because they may be electrolessly deposited. Co and Ni also provide oxidation resistance for copper, and have good adhesion to copper, for example. The passivation layer226may also comprise other materials exhibiting these properties, for example. The passivation layer226forms an alloy cap layer over the top surface of the conductive features206, which features206have been treated with the novel treatment solution222in accordance with an embodiment of the present invention.

The passivation layer226thickness is substantially uniform across the entire surface of the workpiece202in accordance with preferred embodiments of the present invention. Preferably, all of the conductive features206of the workpiece202are coated with substantially the same thickness of the passivation layer226. If a plurality of die is formed on the workpiece202, preferably all of the conductive features206of each die are covered with substantially the same thickness of passivation layer226, in accordance with an embodiment of the invention.

After the formation of the uniform passivation layer226, an optional etch stop layer228may be formed over the passivation layer226and exposed portions of the insulating layer204, as shown inFIG. 8. An etch stop layer228may be used if a subsequently deposited insulating layer204′ comprises a low k material, to provide an etch stop during the etch process of the insulating layer204′, for example. The etch stop layer228may comprise a material different than the insulating layer materials204and/or204′, for example. The etch stop layer228may comprise a material having a different etching rate than the insulating layer materials204and204′, for example. The etch stop layer228may comprise a thickness of about 800 Angstroms or less, e.g., and may comprise about 300 to about 600 Angstroms, of SiN, as examples, although alternatively, the etch stop layer228may comprise other materials and thicknesses.

A passivation layer226′ may be selectively formed on conductive features206′ in subsequently formed metallization layers, as shown inFIG. 9, after treating the top surface of the conductive features206′ and the insulating layer204′ with the treatment solution222, as described herein with reference toFIG. 6. A passivation layer226and226′ may be formed on one or more metallization layers of the semiconductor device200, or on all of the metallization layers that include the conductive features206and206′ of a semiconductor device200, for example.

The novel treatment solution222may be used before forming passivation layers of damascene structures, as shown with reference toFIGS. 3 through 9, using single or dual damascene processes. Alternatively, the treatment solution222may also be used for semiconductor devices300having conductive features306formed in a subtractive etch process, as shown in a cross-sectional view inFIGS. 10 and 11. In this embodiment, like numerals are used for the various elements that were described inFIGS. 3 through 9, and to avoid repetition, each reference number shown inFIGS. 10 and 11is not described again in detail herein. Rather, similar materials x02, x04, x06, etc. are preferably used for the various material layers shown as were described forFIGS. 3 through 9, where x=2 inFIGS. 3 through 9, and x=3 inFIGS. 10 and 11.

In this embodiment, a workpiece302is provided, and a layer of conductive material320is formed or deposited over the workpiece302. The layer of conductive material320may optionally be treated with the treatment solution322at this point of the manufacturing process, and a passivation layer326, shown in phantom, may be formed over the layer of conductive material320. The layer of conductive material320and the passivation layer326are then patterned, e.g., using lithography techniques, to form a plurality of conductive features306capped with a passivation layer326, as shown inFIG. 11. An insulating layer304is formed over the patterned conductive features306and passivation layer326, and the insulating layer304is exposed to a CMP process to remove excess insulating layer304from over the top surface of the passivation layer326. Note that in this embodiment, the insulating layer304is not treated with the treatment solution322.

In another embodiment, the layer of conductive material320is not treated immediately with the treatment solution322after depositing the layer of conductive material320. Rather, in this embodiment, the layer of conductive material320is patterned into the desired shape of the conductive lines306using a subtractive etch process. The insulating layer304is formed over the patterned conductive lines306, and if an excess amount of the insulating layer304resides over the top surface of the conductive lines306, a CMP process is used to remove the excess insulating layer304from over the top surface of the conductive lines306. The top surface of the conductive lines306and the top surface of the insulating layer304are then treated with the novel treatment solution322, and then a passivation layer326is selectively formed over the top surface of the treated conductive lines306, as shown inFIG. 11. Note that in this embodiment, the passivation layer326may extend above the top surface of the insulating layer304, rather than residing below the top surface of the insulating layer304, as shown inFIG. 11.

Embodiments of the invention have useful application in any type of semiconductor device, including memory and logic devices, as examples. Embodiments of the invention are useful in semiconductor devices having a single metallization layer, or in semiconductor devices having two or more metallization layers, as examples.

Advantages of embodiments of the invention include forming uniform passivation layers226,226′, and326over conductive features206,206′, and306of a workpiece202and302. The passivation layers226,226′, and326have substantially the same thickness over and across the entire surface of the workpiece202and302. The passivation layers226,226′ and326have improved wetting and improved deposition uniformity. The uniform passivation layers226,226′, and326may be formed before or after a CMP process, on conductive features206,206′, or306formed by a damascene process (conductive features206or206′) or a subtractive etch process (conductive features306). A novel treatment solution222and322is used to treat the top surface of the conductive features206,206′, and306and may be used to treat the insulating layers204,204′, and304surrounding the conductive features206,206′, and306. The treatment solution222and322improves the adhesive properties of the conductive features206,206′, and306and provides improved selectivity between the conductive features206,206′, and306and the insulating layers204,204′, and304during the formation of the passivation layers226,226′, and326. Embodiments of the invention are readily implementable into existing manufacturing process flows, for example.