SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device includes a memory core including a memory cell array, and a peripheral circuit configured to transfer data input to a pad unit to the memory core, and transfer data transferred from the memory core to the pad unit. The peripheral circuit includes a first region including a first data bus having a first wiring resistance, and a second region including a second data bus having a second wiring resistance lower than the first wiring resistance. The first region transfers data parallel at a first operating speed, and the second region serially transfers data at a second operating speed higher than the first operating speed.

DETAILED DESCRIPTION

In general, according to one embodiment, there is provided a semiconductor memory device comprising:

a memory core including a memory cell array; and

a peripheral circuit configured to transfer data input to a pad unit to the memory core, and transfer data transferred from the memory core to the pad unit,

wherein the peripheral circuit includes a first region including a first data bus having a first wiring resistance, and a second region including a second data bus having a second wiring resistance lower than the first wiring resistance,

the first region transfers data parallel at a first operating speed, and

the second region serially transfers data at a second operating speed higher than the first operating speed.

Embodiments will be explained below with reference to the accompanying drawings. Note that these drawings are exemplary or conceptual, so the dimensions and ratios of each drawing are not necessarily the same as real dimensions and ratios. Several embodiments to be described below represent examples of apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is not specified by the shapes, structures, and layouts of the constituent parts. Note that in the following explanation, the same reference numerals denote elements having the same functions and arrangements, and a repetitive explanation will be made only when necessary.

First Embodiment

A semiconductor memory device will be explained below by taking a three-dimensional stacked type NAND flash memory in which a plurality of memory cells are stacked on a substrate as an example.

[1] Arrangement of Semiconductor Memory Device

First, the arrangement of the semiconductor memory device (NAND flash memory) according to this embodiment will be explained.

FIG. 1is a block diagram of the NAND flash memory according to the first embodiment. This NAND flash memory includes a core (memory core)11as a data storage unit, and a peripheral circuit12for controlling the core11.

The core11includes a plurality of planes13.

This embodiment will be explained by taking four planes13-0to13-3as an example, but the number of planes13can be freely set. The plane13-0includes a memory cell array20-0, sense amplifiers (S/As)21A-0and21B-0, and a row decoder22-0. The planes13-1to13-3each have the same arrangement as that of the plane13-0. Note that in the following explanation, the planes13-0to13-3will simply be referred to as planes13if it is not particularly necessary to distinguish between them, and the same shall apply to the internal circuits of the planes.

The memory cell array20includes, for example, four units UT0to UT3. Each unit UT includes a plurality of blocks BLK. Each block BLK includes a plurality of nonvolatile memory cells, and data in the same block BLK are erased at once.

The row decoder22performs selection in the row direction of the memory cell array20. Also, when writing, reading, and erasing data, the row decoder22applies various voltages to word lines, select gate lines, and backgate lines formed in the memory cell array20.

Sense amplifier21A is formed to correspond to units UT0and UT1. Sense amplifier21A controls the voltages of bit lines formed in units UT0and UT1. When reading data, sense amplifier21A senses and amplifies the data read from a memory cell. When writing data, sense amplifier21A transfers write data to a memory cell. Sense amplifier21B is formed to correspond to units UT2and UT3. The operation of sense amplifier21B is the same as that of sense amplifier21A.

Next, the arrangement of the peripheral circuit12will be explained. The peripheral circuit12includes plane drivers23-0to23-3, a voltage generator24, a controller25, a selector26, and a pad unit27.

The plane drivers23-0to23-3are formed to respectively correspond to the planes13-0to13-3. The plane driver23controls the plane13when writing, reading, and erasing data. The voltage generator24generates various voltages necessary for operations (write, read, and erase operations) of the NAND flash memory, and applies the various voltages to the plane drivers23-0to23-3.

The pad unit27includes a plurality of pads. The pad unit27exchanges (receives and transmits) data with an external circuit (for example, a host apparatus), and receives power from the external circuit. When data is input from the external circuit to the pad unit27, the selector26supplies the input data to a data bus for a selected plane. Also, when data is output from a selected plane, the selector26supplies the output data to the pad unit27.

The controller25controls the operation of the whole NAND flash memory. To perform this control, the controller25supplies various control signals to the individual circuits of the NAND flash memory.

[1-1] Arrangement of Memory Cell Array20

The arrangement of the memory cell array20will be explained below. As described above, the memory cell array20(more specifically, each unit UT) includes the plurality of blocks BLK.FIG. 2is a circuit diagram of one block BLK.

The block BLK includes a plurality of memory groups GP. This embodiment will be explained by taking an arrangement in which one block BLK includes four memory groups GP0to GP3as an example, but the number of memory groups GP can be freely set. Each memory group GP includes n (n is a natural number) NAND strings NS.

Each NAND string NS includes, for example, eight memory cell transistors MT (MT0to MT7), two select transistors ST1and ST2, and a backgate transistor BT. Each memory cell transistor MT includes a multilayered gate including a control gate and charge storage layer, and nonvolatilly stores data. Note that the number of memory cell transistors MT is not limited to 8, and can also be, for example, 16, 32, 64, or 128, i.e., the number can be freely set. Similar to the memory cell transistor MT, the backgate transistor BT includes a multilayered gate including a control gate and charge storage layer. The backgate transistor BT does not store data, and is turned on when writing, reading, and erasing data.

The memory cell transistors MT and backgate transistor BT are arranged between the select transistors ST1and ST2, so as to connect their current paths in series. The backgate transistor BT is formed between the memory cell transistors MT3and MT4. The current path of the memory cell transistor MT7at one end of this series connection is connected to one end of the current path of the select transistor ST1. The current path of the memory cell transistor MT0at the other end of the series connection is connected to one end of the current path of the select transistor ST2.

The gates of the select transistors ST1of each of the memory groups GP0to GP3are connected together to a corresponding one of select gate lines SGDO to SGD3. The gates of the select transistors ST2of each of the memory groups GP0to GP3are connected together to a corresponding one of select gate lines SGS0to SGS3. The control gates of the memory cell transistors MT0to MT7in the same block BLK are respectively connected together to word lines WL0to WL7. The control gates of the backgate transistors BT in the same block BLK are connected together to a backgate line BG.

That is, the plurality of memory groups GP in the same block BLK share the word lines WL0to WL7and backgate line BG, but the select gate lines SGD and SGS are formed for each memory group GP even in the same block BLK.

Of the NAND strings NS arranged in a matrix in the memory cell array20, the other-end sides of the current paths of the select transistors ST1of the NAND strings NS in the same row are connected together to one of n (n is a natural number) bit lines BL (BLO to BLn). That is, the bit lines BL connect the NAND strings NS together between the plurality of blocks BLK. Also, the other-end sides of the current paths of the select transistors ST2are connected together to a source line SL. The source line SL connects the NAND strings NS together between, for example, the plurality of blocks BLK.

As described previously, data in the memory cell transistors MT in the same block BLK are erased at once. By contrast, data read or write is performed at once to a plurality of memory cell transistors MT connected together to a given word line WL in a given memory cell group GP. This unit will be called a page.

FIG. 3is a sectional view of the memory cell array20.FIG. 3shows a section taken along the column direction of the memory cell array20.

The memory cell array20is formed on an insulating layer31on a semiconductor substrate30. Each block BLK included in the memory cell array20includes a plurality of NAND strings NS.

The NAND string NS includes a U-shaped semiconductor layer33. That is, the semiconductor layer33includes a pair of columnar portions extending perpendicularly to the surface of the semiconductor substrate30, and a connecting portion for connecting the lower ends of the pair of columnar portions. The semiconductor layer33has one end connected to the bit line BL, and the other end connected to the source line SL. The semiconductor layer33functions as the body (channel formation portion) of the NAND string NS.

An insulating layer34is formed to surround the semiconductor layer33. The insulating layer34is obtained by stacking a tunnel insulating film, charge storage layer, and block insulating film in this order from the semiconductor layer33. The tunnel insulating film and block insulating film are made of, for example, silicon oxide (SiO2). The charge storage layer is made of, for example, silicon nitride (SiN).

A conductive layer32functioning as the control gate (backgate line BG) of the backgate transistor BT is formed on the insulating layer31. Four conductive layers are formed on an insulating layer on the conductive layer32, and function as the control gate (word line WL) of the memory cell transistor MT. A conductive layer is formed on an insulating layer on the uppermost word line, and functions as the gates (select gate lines SGD and SGS) of the select transistors ST1and ST2. The U-shaped semiconductor layer33and the insulating layer34surrounding the semiconductor layer33are formed to extend through the backgate line, word lines WL, and select gate lines.

The line width and sectional area of the bit line BL decrease as the micropatterning of the memory cell array20advances. For example, the line width of the bit line BL is a minimum feature size F. An interconnect layer on the same level as that of the bit line BL will be represented by D1hereinafter. An interconnect (D1interconnect) included in interconnect layer D1has almost the same sectional area as that of the bit line BL, and hence is a high-resistance interconnect.

Power lines PL, feed through lines FTL, and the like are formed above the bit line BL. An interconnect layer on the same level as that of the power line PL will be represented by D2hereinafter. An interconnect (D2interconnect) included in interconnect layer D2has a line width and sectional area much larger than those of a D1interconnect. Accordingly, a D2interconnect is a low-resistance interconnect. That is, the wiring resistance of a D2interconnect is much lower than that of a D1interconnect.

[1-2] Arrangement of Data Buses

The arrangement of data buses of the NAND flash memory will now be explained.FIG. 4is a view for explaining the arrangement of the data buses of the NAND flash memory.FIG. 4specifically shows data buses for the planes13-1and13-2. Also, inFIG. 4, thin lines indicate interconnects formed by interconnect layer D1(i.e., high-resistance interconnects), and thick lines indicate interconnects formed by interconnect layer D2(i.e., low-resistance interconnects). Although circuits of the plane13-2will be explained below as an example, the same shall apply to other planes13. In this embodiment, the explanation will be made by assuming that data transfer is performed for every eight bits. However, the bit width can be freely set. In the entire embodiment, a connection of a data bus and a circuit includes manners in which (a) the data bus and the circuit are electrically connected, (b) the data bus and the circuit are physically connected, and (c) the data bus and the circuit are connected through an electric element (for example, a transistor).

The core11includes four flip-flops (FFs)40-0to40-3for holding data of the plane13-2. Flip-flops40-0to40-3are respectively formed to correspond to units UT0to UT3. Flip-flop40-0performs data transfer with unit UT0in a memory cell array20-2via a sense amplifier21A-2. Flip-flop40-1performs data transfer with unit UT1via sense amplifier21A-2. Flip-flop40-2performs data transfer with unit UT2via a sense amplifier21B-2. Flip-flop40-3performs data transfer with unit UT3via sense amplifier21B-2. Each of flip-flops40-0to40-3can hold eight bits at one time.

A shift register SR_PB2<7:0> includes flip-flops41-0to41-3, and flip-flops42-0to42-3. Each of flip-flops41-0to41-3can hold eight bits at one time. Likewise, each of flip-flops42-0to42-3can hold eight bits at one time.

Flip-flop40-0in the core11is connected to flip-flop41-0in shift register SR_PB2<7:0> via an 8-bit data bus IOBUS0_PB2<7:0>. Flip-flop40-1is connected to flip-flop41-1via a data bus IOBUS1_PB2<7:0>. Flip-flop40-2is connected to flip-flop41-2via a data bus IOBUS2_PB2<7:0>. Flip-flop40-3is connected to flip-flop41-3via a data bus IOBUS3_PB2<7:0>.

Flip-flops41-0to41-3are respectively connected to flip-flops42-0to42-3via 8-bit data buses. Flip-flops42-0to42-3are connected in series via 8-bit data buses, and configured to shift data. More specifically, flip-flops42-0and42-1are connected by a data bus YBUS1_PB2<7:0>. Flip-flops42-1and42-2are connected by a data bus YBUS2_PB2<7:0>. Flip-flops42-2and42-3are connected by a data bus YBUS3_PB2<7:0>. Flip-flop42-0is connected to the selector26via an 8-bit data bus YIO_PB2<7:0>.

Referring toFIG. 4, a low-operating-speed region of the peripheral circuit12shown inFIG. 1will be represented by a peripheral circuit12-1, and a high-operating-speed region of the peripheral circuit12will be represented by a peripheral circuit12-2. The operating speed of peripheral circuit12-1is, for example, 50 MHz, and that of peripheral circuit12-2is, for example, 200 MHz. The operating speed of the core11is 50 MHz, i.e., the same as that of peripheral circuit12-1.

Flip-flops40-0to40-3in the core11are formed near the boundary to peripheral circuit12-1, and exchange data with peripheral circuit12-1. Flip-flops41-0to41-3in peripheral circuit12-1are formed near the boundary to peripheral circuit12-2, and exchange data with peripheral circuit12-2. Flip-flops42-0to42-3in peripheral circuit12-2are formed near the boundary to peripheral circuit12-1, and exchange data with peripheral circuit12-1. The flip-flops are thus arranged near the boundaries of the areas.

Flip-flop40-0holds data of data bus IOBUS0_PB2<7:0> when inputting the data, and holds data read from unit UT0when outputting the data. Flip-flops40-1to40-3are the same as flip-flop40-0.

Flip-flop41-0holds data from flip-flop42-0when inputting the data, and holds data of data bus IOBUS0_PB2<7:0> when outputting the data. Flip-flops41-1to41-3are the same as flip-flop41-0.

Flip-flop42-0holds data of data bus YIOPB2<7:0> when inputting the data, and holds data from flip-flop41-0when outputting the data. Flip-flops42-1to42-3are the same as flip-flop42-0.

Flip-flops40-0to40-3and flip-flops41-0to41-3operate by a clock CLK1having a frequency of 50 MHz. Flip-flops42-0to42-3operate by a clock CLK2having a frequency of 200 MHz. An interconnect43for supplying clock CLK1to flip-flops40-0to40-3, an interconnect44for supplying clock CLK1to flip-flops41-0to41-3, and an interconnect46for supplying clock CLK2to flip-flops42-0to42-3are formed by interconnect layer D2. Also, interconnects43and44are connected by an interconnect45formed adjacent to the power line PL. Like the power line PL, interconnect45is formed by interconnect layer D2. Note that those portions of interconnects43and44that intersect the power line PL are formed by interconnect layer D1so as to be away from the power line PL.

Data buses IOBUS in peripheral circuit12-1are formed by interconnect layer D1. On the other hand, the data buses in the core11and peripheral circuit12-2are formed by interconnect layer D2. In other words, in the peripheral circuit12shown inFIG. 4, data buses running in the vertical direction ofFIG. 4are formed by interconnect layer D1, and data buses running in the horizontal direction ofFIG. 4are formed by interconnect layer D2.

[1-3] Arrangement of Shift Register SR

FIG. 5is a circuit diagram showing an example of one shift register SR.

A data bus IOBUS0<7:0> is connected to a latch circuit (LAT)50-0, the first input of a multiplexer (MUX)51-0, and the output of a three-state buffer (TBUF)52-0. The output of multiplexer51-0is connected to the input of the D flip-flop (DFF)42-0. The output of flip-flop42-0is connected to a data bus YBUS0<7:0>. Flip-flop42-0holds an output from multiplexer51-0on the rising edge of clock CLK2.

Data bus YBUS0<7:0> is connected to the input of a three-state buffer53, and the input of three-state buffer52-0. The output of three-state buffer53is connected to a data bus YIO<7:0>. A signal DOUTP is input to the gate of three-state buffer53. When signal DOUTP is high, three-state buffer53outputs data of data bus YBUS0<7:0>.

A circuit including latch circuit50-0, multiplexer51-0, and three-state buffer52-0corresponds to flip-flop41-0shown inFIG. 4. Circuit configurations concerning data buses IOBUS1to IOBUS3are the same as the above-described circuit configuration pertaining to data bus IOBUS0.

The output of flip-flop42-1is connected to the second input of multiplexer51-0via a data bus YBUS1<7:0>. The output of flip-flop42-2is connected to the second input of a multiplexer51-1via a data bus YBUS2<7:0>. The output of flip-flop42-3is connected to the second input of a multiplexer51-2via a data bus YBUS3<7:0>.

Data bus YIO<7:0> is connected to the first input of a multiplexer54. The second input of multiplexer54is grounded (GND). A signal DINP is input to the gate of multiplexer54. When signal DINP is high, multiplexer54outputs data of data bus YIO<7:0>.

An AND gate55has a first input to which clock CLK1is input, and a second input to which signal DINP is input. The output of AND gate55is connected to the gates of three-state buffers52-0to52-3.

An AND gate56has a first input to which clock CLK1is input, and a second input (inverted input) to which signal DINP is input. The output of AND gate56is connected to the gates of multiplexers51-0to51-3.

FIG. 6is a circuit diagram showing an example of three-state buffer TBUF. A gate terminal G is connected to the input of an inverter57A. The output of the inverter57A is connected to the input of an inverter57B.

An input terminal IN is connected to the first input of a NAND gate57D, and the first input of a NOR gate57E. The output of the inverter57B is connected to the input of an inverter57C, and the second input of the NAND gate57D. The output of the inverter57C is connected to the second input of the NOR gate57E.

The output of the NAND gate57D is connected to the gate of a P-channel MOSFET57F. The output of the NOR gate57E is connected to the gate of an N-channel MOSFET57G. The source of the P-channel MOSFET57F is connected to a power terminal Vdd. The drain of the P-channel MOSFET57F is connected to an output terminal OUT, and the drain of the N-channel MOSFET57G. The source of the N-channel MOSFET57G is grounded.

FIG. 7is a circuit diagram showing an example of latch circuit LAT. An input/output terminal10is connected to the input of an inverter58A, and the output of an inverter58B. The output of the inverter58A is connected to the input of the inverter58B.

[2] Operation of NAND Flash Memory

Next, the operation of the NAND flash memory configured as described above will be explained.

The NAND flash memory of this embodiment is a three-dimensional stacked type memory, and the memory cell array20can be micropatterned. Accordingly, the capacitance of the bit line BL must be reduced in order to prevent the decrease in operating speed of the memory cell array20. Therefore, the line width and sectional area of the bit line BL are decreased. In addition, the three-dimensional stacked type NAND flash memory requires a region for extracting a plurality of multilayered word lines WL and the like. This increases the size of the peripheral circuit12, particularly, the length of the peripheral circuit12in the vertical direction ofFIG. 4. For example, the length of the peripheral circuit12(peripheral circuits12-1and12-2inFIG. 4) is about 2,000 μm in the vertical direction.

As shown inFIG. 4, data buses IOBUS running in the vertical direction are formed by the same interconnect layer (high-resistance interconnect) D1as that of the bit line BL, and hence cause a large wiring delay undesirable for the data buses. In this embodiment, therefore, the data buses of the peripheral circuit12are divided into a D1interconnect region (peripheral circuit12-1) and a D2interconnect region (peripheral circuit12-2). Since the long D1interconnects are used in peripheral circuit12-1close to the core11, the lengths of the data buses are increased, and the flip-flops are arranged near the circuit boundary, thereby operating the data buses parallel at 50 MHz, i.e., the same low speed as that of the core11. On the other hand, in peripheral circuit12-2on the side of the pad unit27, the D2interconnects are used in most of the region, so the data buses are serially operated at a high speed of 200 MHz.

[2-1] Data Input Operation

FIG. 8is a view for explaining data flows in the shift register SR when inputting data. Arrows inFIG. 8indicate the data flows.FIG. 9is a timing chart showing the data input operation of the NAND flash memory. As described earlier, the frequency of clock CLK1is, for example, 50 MHz, and that of clock CLK2is, for example, 200 MHz.

First, data is serially input every eight bits from an external circuit to the pad unit27. The selector26sequentially supplies the input data to data bus YIO<7:0> corresponding to a plane (called a selected plane) as a data input target.

When inputting data, signal DINP goes high. Flip-flop42-3holds input data D00input via multiplexers54and51-3on the rising edge of clock CLK2. On the next rising edge of clock CLK2, flip-flop42-2holds input data D00input via data bus YBUS3<7:0> and multiplexer51-2, and flip-flop42-3holds input data D10following input data D00. By repeating this operation, input data D00to D30are shifted in flip-flops42-3to42-0, and flip-flops42-0to42-3respectively hold input data D00to D30.

Subsequently, flip-flops41-0to41-3respectively hold input data D00to D30on the falling edge of clock CLK1. Input data D00to D30held in flip-flops41-0to41-3are respectively transferred to flip-flops40-0to40-3in the core11via data buses IOBUS0<7:0> to IOBUS3<7:0>. At this point of time, the operation of transferring input data D00to D30in the peripheral circuit12is completed.

After that, sense amplifiers21A and21B write input data D00to D30to the memory cell array20in the selected plane13. The same operation as that described above is repetitively performed on input data D01to D31following input data D00to D30.

By this data input operation, the data transfer rate can be converted from 200 to 50 MHz in the boundary between peripheral circuits12-1and12-2. Also, in peripheral circuit12-1using the long D1interconnects as the data buses, the data buses can be operated parallel at a low speed of 50 MHz, so data transfer can accurately be performed even when a wiring delay increases.

[2-2] Data Output Operation

FIG. 10is a view for explaining data flows in the shift register SR when outputting data. Arrows inFIG. 10indicate the data flows.FIG. 11is a timing chart showing the data output operation of the NAND flash memory.

First, a read operation is executed in a plane (called a selected plane) as a data output target, and output data read from the selected plane13is held in flip-flops40-0to40-3in the core11. When outputting data, signal DOUTP goes high.

Then, output data D00to D30respectively held in flip-flops40-0to40-3are transferred to data buses IOBUS0<7:0> to IOBUS3<7:0>. Flip-flops41-0to41-3respectively hold output data D00to D30on the falling edge of clock CLK1.

Subsequently, flip-flops42-0to42-3respectively hold output data D00to D30input via multiplexers51-0to51-3on the rising edge of clock CLK2. At this time, output data D00held in flip-flop42-0is output to data bus YIO<7:0> via data bus YBUS0<7:0> and three-state buffer53.

On the next rising edge of clock CLK2, flip-flop42-0holds output data D10input via data bus YBUS1<7:0> and multiplexer51-0, and flip-flop42-1holds output data D20following output data D10. By repeating this operation, output data D00to D30are shifted in flip-flops42-0to42-3. Consequently, flip-flop42-0serially transfers output data D00to D30to data bus YIO<7:0>.

The selector26selects the output data transferred to YIO<7:0>. The selector26outputs the data to an external circuit via the pad unit27. The same operation is repetitively performed on output data D01to D31following output data D00to D30.

By this data output operation, the data transfer rate can be converted from 50 to 200 MHz in the boundary between peripheral circuits12-1and12-2. Also, in peripheral circuit12-1using the long D1interconnects as the data buses, the data buses can be operated parallel at a low speed of 50 MHz, so data transfer can accurately be performed even when a wiring delay increases.

In the first embodiment as has been explained in detail above, the peripheral circuit12for transferring data between the core (memory core)11and pad unit27is divided into the first region (peripheral circuit12-1) in which data buses formed by the D1interconnects (high-resistance interconnects) are formed, and the second region (peripheral circuit12-2) in which data buses formed by the D2interconnects (low-resistance interconnects) are formed. The data buses in peripheral circuit12-1transfer data at a first operating speed (for example, 50 MHz), whereas the data buses in peripheral circuit12-2transfer data at a second operating speed (for example, 200 MHz) higher than the first operating speed.

Accordingly, the first embodiment can easily and more accurately increase the speed of the data buses as a whole in the peripheral circuit12. It is also possible to implement first-in first-out (FIFO) data transfer at high speed.

Furthermore, in peripheral circuit12-1using the high-resistance interconnects, data transfer is performed parallel at 50 MHz, i.e., the same operating speed as that of the core11, so the data transfer operation can accurately and reliably performed. In peripheral circuit12-2, a high-speed operation can be performed because data transfer is serially performed at an operating speed of 200 MHz. In addition, the arrangement of the first embodiment is flexibly changeable by the floor plan of the peripheral circuit12or the interconnect manufacturing process.

Also, the shift register SR is formed in the boundary between peripheral circuits12-1and12-2, and the operating speed is converted by using the flip-flops included in the shift register SR. This makes it possible to accurately convert the operating speed in the boundary between peripheral circuits12-1and12-2.

Moreover, the arrangement of this embodiment does not require many drivers in order to ensure a high-speed operation. Therefore, it is possible to assure an accurate high-speed operation while reducing the cost without complicating the circuit configuration.

Second Embodiment

In the second embodiment, data buses are divided into a low-speed region and high-speed region as in the first embodiment, but a tree structure is used as the data buses in order to eliminate data transfer variations between planes.FIG. 12is a view for explaining the arrangement of the data buses of a NAND flash memory according to the second embodiment.

The following explanation will be made by taking the arrangement of a shift register SR for a plane13-2as an example, but the same explanation applies to other planes13. In this embodiment, data transfer is performed for, for example, every eight bits.

A shift register SR_PB2A<7:0> includes flip-flops41-0and41-1and flip-flops42-0and42-1. Each of flip-flops41-0and41-1and flip-flops42-0and42-1can hold eight bits at one time.

Flip-flop41-0is connected to a data bus IOBUS0_PB2<7:0>. Flip-flop41-1is connected to a data bus IOBUS1_PB2<7:0>. Flip-flops41-0and41-1are respectively connected to flip-flops42-0and42-1via 8-bit data buses. Flip-flops42-0and42-1are connected in series. Flip-flops42-0and42-1are configured to shift data.

A shift register SR_PB2B<7:0> includes flip-flops41-2and41-3and flip-flops42-2and42-3. Each of flip-flops41-2and41-3and flip-flops42-2and42-3can hold eight bits at one time.

Flip-flop41-2is connected to a data bus IOBUS2_PB2<7:0>. Flip-flop41-3is connected to a data bus IOBUS3_PB2<7:0>. Flip-flops41-2and41-3are respectively connected to flip-flops42-2and42-3via 8-bit data buses. Flip-flops42-2and42-3are connected in series. Flip-flops42-2and42-3are configured to shift data.

Shift registers SR_PB2A<7:0> and SR_PB2B<7:0> can have the same arrangement as that of the shift register explained with reference toFIG. 5in the first embodiment.

Flip-flops42-1and42-2are connected to a flip-flop60-2. Flip-flop60-2for the plane13-2is connected to a flip-flop61-1via a data bus YIO_PB2<7:0>. A flip-flop60-3for a plane13-3is connected to flip-flop61-1via a data bus YIO_PB3<7:0>. A flip-flop60-0for a plane13-0is connected to a flip-flop61-0via a data bus YIO_PB0<7:0>. A flip-flop60-1for a plane13-1is connected to flip-flop61-0via a data bus YIO_PB1<7:0>.

Flip-flops61-0and61-1are connected to a flip-flop62via data buses. Flip-flop62is connected to a pad unit27via flip-flops63and64.

Data buses IOBUS in a peripheral circuit12-1are formed by an interconnect layer D1(i.e., high-resistance interconnects). On the other hand, data buses in a core11and peripheral circuit12-2are formed by an interconnect layer D2(i.e., low-resistance interconnects). In other words, in a peripheral circuit12shown inFIG. 12, data buses running in the vertical direction ofFIG. 12are formed by interconnect layer D1, and data buses running in the horizontal direction ofFIG. 12are formed by interconnect layer D2. Referring toFIG. 12, thin lines indicate the interconnects formed by interconnect layer D1, and thick lines indicate the interconnects formed by interconnect layer D2.

The frequency of a clock CLK1is, for example, 50 MHz, and that of a clock CLK2is, for example, 100 MHz. Note that clock CLK2is supplied to all flip-flops in peripheral circuit12-2, but interconnects for clock CLK2are omitted fromFIG. 12in order to avoid the complexity of the drawing.

Next, the operation of the NAND flash memory configured as described above will be explained. In a data input operation, the pad unit27performs a DDR (Double Data Rate) operation, thereby converting the data transfer rate from 200 to 100 MHz. Also, the data transfer rate is converted from 100 to 50 MHz in the boundary between peripheral circuits12-2and12-1. In peripheral circuit12-1using the long D1interconnects as the data buses, an operation can be performed at a low speed of 50 MHz, so accurate data transfer can be performed even when a wiring delay increases.

In a data output operation, the data transfer rate is converted from 50 to 100 MHz in the boundary between peripheral circuits12-1and12-2. In addition, the data transfer rate is converted from 100 to 200 MHz by performing the DDR operation in the pad unit27. In peripheral circuit12-1using the long D1interconnects as the data buses, an operation can be performed at a low speed of 50 MHz, so accurate data transfer can be performed even when a wiring delay increases.

In the second embodiment as has been explained in detail above, as shown inFIG. 12, the data buses extending from the pad unit27toward peripheral circuit12-1sequentially branch in peripheral circuit12-2. That is, the data buses of peripheral circuit12-2have a tree structure. Accordingly, the interconnect lengths between the planes13can be made almost the same for the data buses in the peripheral circuit12. This makes it possible to reduce variations in transfer rate between the planes13. The rest of the effects are the same as those of the first embodiment.

Third Embodiment

In the third embodiment, some data buses are arranged below a memory cell array. In addition, the data buses below the memory cell array are operated at low speed, and data buses near a pad unit are operated at high speed, thereby increasing the speed of the data buses as a whole.

[1] Arrangement of Data Buses

FIG. 13is a view for explaining the arrangement of data buses of a NAND flash memory according to the third embodiment.FIG. 13specifically shows data buses corresponding to one plane13. The arrangement of data buses for other planes is the same as that shown inFIG. 13. This embodiment will be explained by assuming that data transfer is performed for, for example, every eight bits, but the bit width can be freely set.

FIG. 13specifically shows data latches XDL as circuits included in a core11. The plane13includes the data latches XDL that temporarily hold data read from a memory cell array20, and temporarily hold data to be written to the memory cell array20. The data latches XDL are included in a sense amplifier21. One data latch XDL shown inFIG. 13can hold eight bits at one time.

A first data latch XDL connected to a unit UT0is connected to a flip-flop41-0N in a shift register SR<7:0> via an 8-bit data bus IOBUS0_N<7:0>. A second data latch XDL connected to unit UT0is connected to a flip-flop41-0F in the shift register SR<7:0> via an 8-bit data bus IOBUS0_F<7:0>. Although operations concerning the two data buses (IOBUS0_N<7:0> and IOBUS0_F<7:0>) connected to unit UT0will be explained below, more data buses are actually connected to unit UT0. The same shall apply to other units.

A first data latch XDL connected to a unit UT1is connected to a flip-flop41-1N in the shift register SR<7:0> via an 8-bit data bus IOBUS1_N<7:0>. A second data latch XDL connected to unit UT1is connected to a flip-flop41-1F in the shift register SR<7:0> via an 8-bit data bus IOBUS1_F<7:0>. Likewise, flip-flops41-2N and41-2F are respectively connected to a unit UT2via data buses IOBUS2_N<7:0> and IOBUS2_F<7:0>. Also, flip-flops41-3N and41-3F are respectively connected to a unit UT3via data buses IOBUS3_N<7:0> and IOBUS3_F<7:0>.

Flip-flops41-0N and41-0F are connected to a flip-flop42-0via 8-bit data buses. Flip-flops41-1N and41-1F are connected to a flip-flop42-1via 8-bit data buses. Flip-flops41-2N and41-2F are connected to a flip-flop42-2via 8-bit data buses. Flip-flops41-3N and41-3F are connected to a flip-flop42-3via 8-bit data buses.

Flip-flops42-0to42-3are connected in series via 8-bit data buses, and thus configured to shift data. More specifically, flip-flops42-0and42-1are connected by a data bus YBUS1<7:0>. Flip-flops42-1and42-2are connected by a data bus YBUS2<7:0>. Flip-flops42-2and42-3are connected by a data bus YBUS3<7:0>. Flip-flop42-0is connected to a pad unit27via an 8-bit data bus YIO<7:0>.

Flip-flops41-0N to41-3N operate with a clock CLK1. Flip-flops41-0F to41-3F operate with a clock CLK2. Flip-flops42-0to42-3operate with a clock CLK0. The frequency of clock CLK0is, for example, 200 MHz. The frequencies of clocks CLK1and CLK2are, for example, 25 MHz, and have different phases. That is, the operating speed of a peripheral circuit12-1(including data buses IOBUS0to IOBUS3, and some data buses and some flip-flop included in the shift register SR) is, for example, 25 MHz, and that of a peripheral circuit12-2(including some data buses and some flip-flop included in the shift register SR) is, for example, 200 MHz. The operating speed of the core11is 25 MHz, i.e., the same as that of peripheral circuit12-1.

In this embodiment, peripheral circuit12-1is embedded below the memory cell array as shown inFIG. 14, and operated parallel at low speed (25 MHz). On the other hand, peripheral circuit12-2is positioned near the pad unit27outside the memory cell array, and serially operated at high speed (200 MHz). This makes it possible to increase the speed of the data buses as a whole, reduce the power consumption of the data buses, and reduce the circuit area of the NAND flash memory.

[2] Arrangement of Shift Register SR

FIG. 15is a circuit diagram showing an example of the shift register SR.

Data bus IOBUS0_N<7:0> is connected to a latch circuit (LAT)50-0N, the second input of a multiplexer (MUX)51-0, and the output of a three-state buffer (TBUF)52-0N. The first input of multiplexer51-0is grounded. Data bus IOBUS0_F<7:0> is connected to a latch circuit50-0F, the third input of multiplexer51-0, and the output of a three-state buffer52-0F. The output of multiplexer51-0is connected to the input of the D flip-flop (DFF)42-0. The output of flip-flop42-0is connected to a data bus YBUS0<7:0>. Flip-flop42-0holds an output from multiplexer51-0on the rising edge of clock CLK0. Data bus YBUS0<7:0> is connected to the inputs of three-state buffers53,52-0N, and52-0F.

A circuit including latch circuit50-0N, multiplexer51-0, and three-state buffer52-0N corresponds to flip-flop41-0N shown inFIG. 13. A circuit including latch circuit50-0F, multiplexer51-0, and three-state buffer52-0F corresponds to flip-flop41-0F shown inFIG. 13. Circuit configurations concerning data buses IOBUS1to IOBUS3are the same as the above-described circuit configuration pertaining to data bus IOBUS0.

The output of flip-flop42-1is connected to the fourth input of multiplexer51-0via data bus YBUS1<7:0>. The output of flip-flop42-2is connected to the fourth input of multiplexer51-1via data bus YBUS2<7:0>. The output of flip-flop42-3is connected to the fourth input of multiplexer51-2via data bus YBUS3<7:0>.

An AND gate55-1has a first input to which clock CLK1is input, and a second input to which a signal DINP is input. The output of AND gate55-1is connected to the gates of three-state buffers52-0N to52-3N. An AND gate55-2has a first input to which clock CLK2is input, and a second input to which signal DINP is input. The output of AND gate55-2is connected to the gates of three-state buffers52-0F to52-3F.

An AND gate56-1has a first input to which clock CLK1is input, and a second input (inverted input) to which signal DINP is input. The output of AND gate56-1is connected to the first gates of multiplexers51-0to51-3. An AND gate56-2has a first input to which clock CLK2is input, and a second input (inverted input) to which signal DINP is input. The output of AND gate56-2is connected to the second gates of multiplexers51-0to51-3.

[3] Operation of NAND Flash Memory

The operation of the NAND flash memory configured as described above will be explained below.

[3-1] Data Input Operation

FIG. 16is a view for explaining data flows in the shift register SR when inputting data. Arrows inFIG. 16indicate the data flows.FIG. 17is a timing chart showing the data input operation of the NAND flash memory. As described earlier, the frequency of clock CLK0is, for example, 200 MHz, and the frequencies of clocks CLK1and CLK2are, for example, 25 MHz and have different phases.

First, data is serially input every eight bits from an external circuit to the pad unit27. When inputting data, signal DINP goes high. Flip-flop42-3holds input data D00input via multiplexers54and51-3on the rising edge of clock CLK0. On the next rising edge of clock CLK0, flip-flop42-2holds input data D00input via data bus YBUS3<7:0> and multiplexer51-2, and flip-flop42-3holds input data D10following input data D00. By repeating this operation, input data D00to D30are shifted in flip-flops42-3to42-0, and flip-flops42-0to42-3respectively hold input data D00to D30.

Subsequently, flip-flops41-0N to41-3N respectively hold input data D00to D30on the falling edge of clock CLK1. Input data D00to D30held in flip-flops41-0N to41-3N are respectively transferred to the plane13via data buses IOBUS0_N<7:0> to IOBUS3_N<7:0>.

Similarly, after input data D01to D31are respectively held in flip-flops42-0to42-3, flip-flops41-0F to41-3F respectively hold input data D01to D31on the falling edge of clock CLK2. Input data D01to D31held in flip-flops41-0F to41-3F are respectively transferred to the plane13via data buses IOBUS0_F<7:0> to IOBUS3_F<7:0>.

By this data input operation, the data transfer rate can be converted from 200 to 25 MHz in the boundary between peripheral circuits12-1and12-2. Also, in peripheral circuit12-1, the data buses can be operated parallel at a low speed of 25 MHz, so data transfer can accurately be performed even when a wiring delay increases.

[3-2] Data Output Operation

FIG. 18is a view for explaining data flows in the shift register SR when outputting data. Arrows inFIG. 18indicate the data flows.FIG. 19is a timing chart showing the data output operation of the NAND flash memory.

First, a read operation is executed in the plane13, and output data D00to D30read from the plane13are respectively transferred to data buses IOBUS0_N<7:0> to IOBUS3_N<7:0>. When outputting data, signal DOUTP goes high. Then, flip-flops41-0N to41-3N respectively hold output data D00to D30on the falling edge of clock CLK1.

Subsequently, flip-flops42-0to42-3respectively hold output data D00to D30input via multiplexers51-0to51-3on the rising edge of clock CLK0. At this time, output data D00held in flip-flop42-0is output to data bus YIO<7:0> via data bus YBUS0<7:0> and three-state buffer53.

On the next rising edge of clock CLK0, flip-flop42-0holds output data D10input via data bus YBUS1<7:0> and multiplexer51-0, and flip-flop42-1holds output data D20following output data D10. By repeating this operation, output data D00to D30are shifted in flip-flops42-0to42-3. Consequently, flip-flop42-0serially transfers output data D00to D30to data bus YIO<7:0>.

Analogously, after output data D01to D31are transferred to data buses IOBUS0_F<7:0> to IOBUS3_F<7:0>, flip-flops41-0F to41-3F respectively hold output data D01to D31on the falling edge of clock CLK2. Flip-flops42-0to42-3respectively hold output data D01to D31input via multiplexers51-0to51-3on the rising edge of clock CLK0. After that, flip-flops42-0to42-3shift output data D01to D31, and flip-flop42-0serially transfers output data D01to D31to data bus YIO<7:0>.

By this data output operation, the data transfer rate can be converted from 25 to 200 MHz in the boundary between peripheral circuits12-1and12-2. Also, in peripheral circuit12-1, the data buses can be operated parallel at a low speed of 25 MHz, so data transfer can accurately be performed even when a wiring delay increases.

As has been explained in detail above, the third embodiment can easily and more accurately increase the speed of the data buses as a whole in the peripheral circuit12. It is also possible to implement first-in first-out (FIFO) data transfer at high speed. Furthermore, in peripheral circuit12-1, data transfer is performed parallel at an operating speed of 25 MHz, so the data transfer operation can accurately and reliably performed. In peripheral circuit12-2, a high-speed operation can be performed because data transfer is serially performed at an operating speed of 200 MHz.

In addition, peripheral circuit12-1is embedded below the memory cell array. Even when the data buses of this embodiment are implemented, therefore, the circuit area of the NAND flash memory can be reduced. Also, the power consumption of data transfer can further be reduced by further decreasing the data bus operating speed in peripheral circuit12-1from 50 to 25 MHz.

Comparative Example

FIG. 20is a view for explaining the arrangement of data buses of a NAND flash memory according to a comparative example. In a peripheral circuit12shown inFIG. 20, data buses running in the longitudinal direction are formed by an interconnect layer D1(i.e., high-resistance interconnects), and data buses running in the lateral direction are formed by an interconnect layer D2(i.e., low-resistance interconnects). Referring toFIG. 20, thin lines indicate interconnects (D1interconnects) formed by interconnect layer D1, and thick lines indicate interconnects (D2interconnects) formed by interconnect layer D2.

In this comparative example, the D1interconnects are used as global interconnects in the longitudinal direction in the peripheral circuit12, and cause a large wiring delay undesirable for the data buses. Especially when the size of the peripheral circuit12in the longitudinal direction is large, the lengths of the high-resistance D1interconnects increase, and this is very disadvantageous to increase the speed of the data buses.

The data buses of the peripheral circuit12operate at a uniform speed of 100 MHz. Since, however, the very long D1interconnects are used between flip-flops (FFs), a very large wiring delay (RC delay) occurs, and the possibility that no high-speed operation can be performed is very high. In this case, many drivers must be used in order to ensure a high-speed operation.

On the other hand, in this embodiment, the high-resistance D1interconnects are collectively arranged in peripheral circuit12-1, and peripheral circuit12-1is operated at a low speed of 50 MHz. Accordingly, accurate data transfer can be performed even when a wiring delay increases in peripheral circuit12-1. In addition, peripheral circuit12-2is operated at high speed by using the low-resistance D2interconnects. Consequently, it is possible to perform an accurate data transfer operation and increase the operating speed at the same time.

Note that the semiconductor memory device is explained by taking the three-dimensional multilayered NAND flash memory as an example in each embodiment described above, but each embodiment is not limited to this. That is, each embodiment is applicable to a planar NAND flash memory, and various semiconductor memory devices other than the NAND flash memory.

Each embodiment is not limited to the NAND flash memory which comprises U-shaped NAND strings described above. That is, each embodiment is applicable to a three-dimensional multilayered NAND flash memory comprises I-shaped type NAND strings in each of which the semiconductor layer extends directly in a perpendicular direction. Furthermore, a structure of the memory cell array is not limited as above description. A memory cell array formation may be disclosed in U.S. patent application Ser. No. 12/532,030. U.S. patent application Ser. No. 12/532,030, the entire contents of which are incorporated by reference herein.