Oscillation circuit

An oscillation circuit has a first inverter connected to an external piezoelectric resonator, a first feedback resistor disposed between input/output terminals of the first inverter, first/second variable capacitive elements connected to input/output of the first inverter, a charging circuit supplying input/output terminal with a reference current to charge the capacitive element, a comparator comparing a charging voltage of input/output with a reference voltage, and a control circuit that, in a calibration operation, at a first time, causes the charging circuit to start supply the reference current to the input terminal or the output terminal, and, at a second time after the first time, generates the control signal for setting a capacitance value of the first or second variable capacitive element so that the charging voltage becomes close to the reference voltage according to a comparison result of the comparator.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2010-261418, filed on Nov. 24, 2010, the entire contents of which are incorporated herein by reference.

FIELD

The present invention relates to an oscillation circuit.

BACKGROUND

An oscillation circuit (a crystal oscillator) using a piezoelectric resonator such as a crystal resonator obtain an oscillation frequency with a relatively high degree of accuracy and so has been widely used. For example, in a radio communication system, a phase locked loop (PLL) that generates a local oscillation signal necessary for modulating a received signal and demodulating a transmission signal is mounted inside an integrated circuit (IC). The PLL circuit includes a voltage controlled oscillator (VCO). The PLL circuit generates an appropriate local oscillation signal by changing a control voltage or a phase so that an output frequency multiplied by a reference clock is obtained. However, since an IC has a manufacture variation, in each sample, the reference clock and the output frequencies of the PLL circuit slightly different from each other.

Such a variation is adjusted in a digital baseband unit through an auto frequency control (AFC) circuit that matches a frequency of a reference clock of a terminal with a frequency of a reference signal from a base station during communication. The AFC circuit has a controllable range, and an allowable frequency variation of the reference clock is limited to the controllable range. Thus, the reference clock generally requires a high degree of accuracy of the order of tens of parts per million (ppm) with respect to the voltage, the temperature, and a manufacture variation. For this reason, there has been used a voltage controlled temperature compensated crystal oscillator (VCTCXO), which is an oscillator having a small frequency variation, an expensive external component.

In recent years, in a radio communication system, the miniaturization, lightening, and cost reduction has been strongly demanded. Particularly, since the demand for cost reduction is high, an oscillation circuit employing a piezoelectric resonator (a crystal resonator) such as a quartz crystal is attracting attention as an inexpensive oscillation circuit that substitutes for the VCTCXO.

The oscillation circuit has a simple configuration in which an inexpensive piezoelectric element such as a quartz crystal, an IC internal oscillator such as a complementary metal oxide semiconductor (CMOS) inverter, and variable IC internal load capacitors connected to an input and an output of the CMOS inverter are mounted. However, a variation of the piezoelectric resonator such as a quartz crystal is large, and a degree of frequency accuracy is not as high as the VCTCXO. The frequency of the oscillation circuit is decided depending on the piezoelectric resonator such as a quartz crystal and a load capacitance value inside the IC. Thus, the frequency variation is reduced by minutely adjusting the variable capacitance value inside the IC.

An oscillation circuit is disclosed in, for example, Japanese Patent Application Laid-Open Nos. 7-131247, 11-330856, and 2006-157767.

However, the crystal oscillation circuit has a problem in that since there are not only a variation of the piezoelectric resonator such as a quartz crystal influenced by the temperature, but also an internal load capacitance variation in the IC, the frequency of the reference clock that is not adjusted yet is greatly different from a desired value and deviates from the controllable range of AFC control inside the communication system. The load capacitance variation is reduced by mounting a high-accuracy IC external component. However, in this case, the number of components increases, and miniaturization and cost reduction are difficult to achieve. Further, in order to directly detect that an oscillation frequency has been deviated, a high-accuracy frequency detector of the order of ppm is necessary. However, this technique is not suitable for miniaturization and cost reduction.

As described above, the oscillation circuit employing the piezoelectric resonator such as a quartz crystal is required to simply reduce the oscillation frequency variation at a low cost.

SUMMARY

An one aspect of the embodiments is an oscillation circuit, connected to an external piezoelectric resonator, including: a first inverter circuit that includes an input terminal and an output terminal which are connected to both terminals of the piezoelectric resonator, respectively; a first feedback resistor that is disposed between the input terminal and the output terminal of the first inverter circuit; first and second variable capacitive elements that are connected to the input terminal and the output terminal of the first inverter circuit, respectively, and have capacitance values that are variably settable by a control signal; a charging circuit that supplies the input terminal or the output terminal with a certain reference current in order to charge the first or second variable capacitive element; a comparator that compares a charging voltage of the input terminal or the output terminal with a reference voltage; and a control circuit that, in a calibration operation, at a first time, causes the charging circuit to start supply the reference current to the input terminal or the output terminal, and, at a second time after the first time, generates the control signal for setting a capacitance value of the first or second variable capacitive element so that the charging voltage becomes close to the reference voltage according to a comparison result of the comparator.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a diagram illustrating a communication device having an oscillation circuit according to the present embodiment. Particularly,FIG. 1illustrates a configuration of a transmission unit of the communication device. Meanwhile, the oscillation circuit according to the present embodiment may be used for generating a reference clock of a reception unit as well.

The transmission unit includes a low pass filter LPF that receives an analog input IN, a variable gain amplifier VGA that amplifies an output of the filter, a mixer MIX that performs up-conversion by multiplying an output of the amplifier VGA by a local clock LCK generated by a synthesizer60, and a high frequency circuit RF that outputs a high frequency output RFOUT based on an output signal of the mixer MIX.

The transmission unit further includes a digitally controlled crystal oscillator (DCXO) as an oscillation circuit that supplies the synthesizer60with a reference clock SCK. As illustrated inFIG. 1, a typical Pierce-type DCXO includes a piezoelectric resonator4(which will be hereinafter described through a crystal resonator that is an example of the piezoelectric resonator) such as a quartz crystal, which is externally connected to input and output terminals of a CMOS inverter1disposed in a radio frequency RF chip100, capacitive elements2aand2bwhich are respectively connected to the input and output terminals of the CMOS inverter1and have a variable/controllable capacitance, and a resistive element3that makes the input terminal of the CMOS inverter1have the same DC potential as the output terminal of the CMOS inverter1.

The input and output terminals of the CMOS inverter1are set to a threshold voltage by the feedback resistor3. If electric potential of the input terminal changes due to a certain noise, the oscillation circuit DCXO starts an oscillation by an operation of the CMOS inverter1of inverting the input and the output. As will be described later, an oscillation frequency is decided depending on an inductance and a capacitance value of the crystal resonator4and capacitance values of the input and output terminals of the inverter1.

Thus, by controlling the capacitive elements2aand2bby a digital signal, it is possible to change the oscillation frequency of the oscillation circuit DCXO. This is the reason why it is called the digitally controlled crystal oscillator DCXO.

Based on the reference clock SCK generated by the oscillation circuit DCXO, the PLL synthesizer60generates the local clock LCK multiplied by the reference clock SCK. The mixer MIX generates a high frequency transmission signal by multiplying a transmission signal by the local clock LCK. For this reason, the reference clock SCK requires a high degree of frequency accuracy. In the present embodiment, the capacitance values of the variable capacitive elements2aand2bare capable of being minutely adjusted by the digital control signal, so that the reference clock SCK is generated with a high degree of accuracy even if there is a variation in the crystal resonator4. Further, input and output parasitic capacitances of the inverter1, parasitic capacitances of pads of terminals61and62, a parasitic capacitance of up to a substrate board on which the crystal resonator4is arranged, and the like are applied to nodes connected to the variable capacitive elements2aand2b. When total capacitance values of the nodes including these parasitic capacitances are measured by a calibration circuit with a high degree of accuracy, then a capacitance value is set appropriately.

First Embodiment

FIG. 2is a circuit diagram of an oscillation circuit according to the present first embodiment. InFIG. 2, illustrated are a crystal resonator4that configures the oscillation circuit DCXO, and a circuit5which is connected to the external crystal resonator4and formed inside an IC chip. An equivalent circuit of the crystal resonator4includes a series circuit which is configured with an inductor L1, a capacitor C1, and a resistor R1and a capacitor C0connected in parallel to the serial circuit. The circuit5inside the chip includes terminals61and62connected to the crystal resonator4, an inverter circuit1having an input terminal connected to the terminal61and an output terminal connected to the terminal62, a feedback resistor3disposed between the input terminal and the output terminal of the inverter circuit1, load capacitors2aand2bwhich are respectively connected between the input terminal and the output terminal of the inverter circuit1and the ground, respectively, and a control circuit12that sets control signals (control codes) DA and DB for controlling capacitance values of the variable capacitive elements2aand2b.

I/O circuits for preventing electrostatic discharge (ESD) damage are disposed near the terminals61and62of the chip. Further, between the external crystal resonator4and the IC5, a line pattern for connecting the crystal resonator4with the IC5is formed on a circuit board. For this reason, a total capacitance viewed at the terminals61and62includes parasitic capacitances of pads of the terminals61and62, parasitic capacitances of the I/O circuits, a parasitic capacitance of the circuit board, an input parasitic capacitance of the inverter1, and capacitances of the variable capacitive elements2aand2b. The composite capacitance is added to the capacitor C0of the crystal resonator4, so that an oscillation frequency is determined accordingly.

The circuit5inside the chip includes a switch6that connects an oscillation loop of the oscillation circuit and turns electrical power on, switches7aand7bthat supply the input terminal and the output terminal of the CMOS inverter1with a reference current, respectively, switches8aand8bthat fix the input terminal and the output terminal of the CMOS inverter1to a ground GND potential, respectively, a reference current generation circuit10that includes a current source I0and P-type transistors P1, P2, and P3and generates a reference current I, an external resistive element9that generates a reference potential VR, and a comparator11that compares the reference potential VRwith the potential of the input terminal or the output terminal of the CMOS inverter1.

The control circuit12generates the control signals DA and DB for setting the values of the load capacitors2aand2baccording to the comparison result of the comparator11. A clock CLK, an enable signal EN, and a reset signal XRST are supplied to the control circuit12. The control circuit12resets a circuit state in response to the reset signal XRST, starts a calibration operation in response to the enable signal EN, and performs the calibration operation in synchronization with timing of the clock CLK. In a normal state, the control circuit12keeps the control signals DA and DB adjusted by the calibration operation.

FIG. 2illustrates normal operation states of the switches6,7a,7b,8a, and8b. That is, the switch6is in an electrical conduction state, and the remaining switches are in an electrical non-conduction state. Since the switch6is in the electrical conduction state, the oscillation loop of the oscillation circuit including the inverter circuit1and the crystal resonator4is formed.

In this state, a short circuit is formed between the input and the output of the inverter1by the feedback resistor3, and DC potentials of the input and the output of the inverter1are fixed to approximately a threshold voltage of the inverter1. When a negative resistance decided by a parameter such as a transconductance gm of the inverter1is sufficiently larger than a resonant resistance component of the crystal resonator4, the oscillation circuit DCXO is triggered by the occurrence of a noise and resonates like a waveform illustrated inFIG. 2. If L1is defined as a series inductance of the crystal resonator4, C1as a series capacitance, C0as a parallel capacitance, and 2×CLas capacitances of load capacitors2aand2b, the frequency is as follows:
Crystal resonator series resonant frequency:Fs=1/(2π√L1·C1))  Equation 1, and
DCXO resonant frequency with load:FL=Fs·(1+(C1/(2·(C0+CL))))  Equation 2.

Since it is regarded that the load capacitors2aand2bare serially connected to both terminals of the crystal resonator4, the series capacitance thereof becomes CL. A composite capacitance including the parallel capacitance C0inside the crystal resonator4and the load capacitors2aand2bbecomes (C0+CL).

As described above, the output clock SCK of the oscillation circuit DCXO oscillates at the frequency illustrated in Equation 2, and a value of the frequency is decided depending on the parameters L1, C1, and C0of the crystal resonator4and the load capacitance CL. Since the parameters of the crystal resonator4are fixed values specific to components, the frequency of the output clock SCK is variably adjusted by adjusting the capacitance value of the load capacitor CLof the IC internal circuit5. That is, an oscillation circuit that variably controls the frequency is implemented by disposing a mechanism for variably setting the load capacitor CLthat is a variable capacitive element.

However, when a manufacturing variation of the load capacitors2aand2bintegrated inside the IC occurs or when the capacitance values of the load capacitors2aand2bvary by the power voltage or the temperature, the resonant frequency FLgreatly deviates from a design value. Further, as described above, the load capacitance CLis a value including the parasitic capacitance by the I/O circuits inside the IC, a line pattern of an external printed circuit board connected with the terminals61and62, or the like. For this reason, the load capacitance easily varies according to a used I/O circuit, the line length of a printed circuit board, and a material used for it, and this is a cause of the frequency variation.

The circuit5, which configures the oscillation circuit according to the present embodiment, includes a circuit that measures the capacitances of the load capacitors2aand2band of the parasitic capacitors connected to the load capacitors2aand2bin a DC manner. The circuit includes the reference current generating circuit10, the comparator11, a group of switches6,7a,7b,8a, and8b, the external resistor9. Through this circuit having this configuration, the load capacitors2aand2band the parasitic capacitors thereof are calibrated to have capacitance values suitable for generating an ideal frequency.

FIG. 3is a diagram illustrating a calibration operation state of the oscillation circuit illustrated inFIG. 2.FIG. 4is a diagram illustrating a configuration of a capacitor at the input terminal side of the inverter1illustrated inFIG. 3. In the calibration operation, the capacitance value of the capacitor2aat the input terminal side of the inverter1and the capacitance value of the load capacitor2bat the output terminal side thereof are measured, respectively. The calibration operation is performed as follows during an operation preparation time such as when electrical power is turned on.

First, the switch6that connects the oscillation loop of the DCXO5and makes power enable is turned off, and the switch8bfor fixing the output terminal of the CMOS inverter1to the GND potential is turned on. The switch8aat the input terminal side is turned on to discharge electric charges of the load capacitor2aand then immediately turned off. In this state, the input potential and the output potential of the CMOS inverter1are connected to the ground GND potential together. Further, as illustrated inFIG. 4, the load capacitor2a, the parallel capacitor C0of the crystal resonator4, the input parasitic capacitor of the CMOS inverter1, and the parasitic capacitor CPcaused by an I/O cell of the terminal61and a line pattern of an external printed circuit board are present between the input terminal of the CMOS inverter1and the ground GND. Here, let us define CIN(=C2a+C0+CP) as a total capacitance of the input terminal of the CMOS inverter1.

Next, the switch7afor supplying the reference current I generated by the reference current generating circuit10to the input terminal side of the CMOS inverter1is turned on. In this case, an input voltage VCof the CMOS inverter1increases by a gradient I/CINto a time t as represented by:
VC=I·t/CIN
Thus, after one cycle of the clock CLK of the frequency FCthat becomes a certain reference, that is, after a time t=1/FCelapses, the potential VCof the input terminal becomes
VC=I/(FC·CIN)  Equation 3

Meanwhile, by allowing the same reference current I to flow to the external resistive component9from the reference current generating circuit10ofFIG. 3, the following reference voltage VRis obtained:
VR=I·RextEquation 4.
Rext is the external component whose resistance value does not depend on the manufacturing variation, the temperature, or the voltage of the IC. A reference voltage generating circuit configured with the transistor P2for supplying the reference current I and the external resistive component9generates the reference voltage VR.

The resistance value of the external resistive component9, is selected to a value which causes VCto be equal to VRat timing when one cycle of the clock CLK (the frequency FC) elapses after the switch7ais turned on, when the total capacitance CINof the input terminal of the inverter1is an ideal value CIDL(CIN=CIDL). That is, in terms of Equations 3 and 4, a value that satisfies Rext=1/(FC·CIDL) is selected.

For example, when the parallel capacitance C0of the crystal resonator that is already known is 1 pF, FCis set to 10 MHz, and the capacitance CINof the input terminal is desired to be set to the ideal capacitance CIDL=10 pF, 10 kΩ is selected as Rext.

The external resistor Rext is selected as described above, and the switch7ais turned on, so that, in accordance with the reference current I, the input terminal of the inverter1starts to be charged. Then, after one cycle (1/Fc) of the clock CLK elapses, the potential of VCis compared with the potential of VR. In this way, a deviation of an actually manufactured load capacitor from the ideal design value CIDLis detected in a DC manner.

That is, when the reference current I is removed from Equations 3 and 4 and the ideal capacitance expected as the ideal design value is set to CIDL, if Rext=1/(Fc·CIDL) is considered, following Equation 5 is obtained:
VC/VR=1/(Fc·CIN)·Rext=(Fc·CIDL)/(Fc·CIN)=CIDL/CINEquation 5

Equation 5 means that VC>VRwhen CIN<CIDLand VC<VRwhen CIN>CIDL. That is, it means that it is judged whether or not the actually manufactured capacitance CINis larger than the ideal capacitance CIDLthrough the magnitude relationship of Vc and VR.

FIG. 5is a timing diagram of a calibration operation. The switch7ais turned on at a time T0, the comparator11outputs a comparison result between the potential (the charging voltage) Vc of the input terminal of the inverter1and the reference voltage VRat timing T1when one cycle=1/Fc of the clock CLK elapses. It is seen fromFIG. 5that the comparison result is Vc>VRwhen CIN<CIDL, the comparison result is Vc<VRwhen CIN>CIDL, and the comparison result is Vc=VRwhen CIN=CIDL.

The capacitance value of the load capacitor2aofFIG. 4changes by digitally controlling the number of turned-on switches. The control circuit12performs control for increasing or decreasing the number of turned-on switches by the control code DA so that the input voltage Vc of the inverter1become close to the reference voltage VRbased on the judgment of the comparator11. The switch control may be performed such that the number of turned-on switches is controlled through binary search by a multi-bit control signal and a decoder.

Comparison timing by the comparator11need not be necessarily timing when one cycle of the clock CLK elapses after charging starts, and timing when N cycles (N is an integer larger than 2) elapse may be selected.

The control circuit12obtains the optimum number of turned-on switches such that the potential of the input voltage Vc of the inverter1becomes as close to the reference voltage VRas possible, by repeating the comparison operation and the switch control operation multiple times.

After the number of turned-on switches of the variable capacitive element2ais obtained, setting information (the control code DA) of turned-on switches is saved in a register inside the control circuit12, and then a similar calibration operation is performed even on the output side of the CMOS inverter1. That is, by replacing the switch7awith the switch7b, the switch8awith the switch8b, and the load capacitor2awith the load capacitor2b, a similar comparison operation and a similar switch control operation are performed. When detection at the output side is finished, setting information (the control code DB) is similarly saved in the register inside the control circuit12, and transition to the normal operation illustrated inFIG. 2is performed by turning the switch6on and turning switches7a,7b,8a, and8boff.

As understood from Equation 5, since the same reference current I is used for generation of the voltages Vc and VR, the comparison result between the voltages Vc and VRis measured with a high degree of accuracy without depending on the magnitude or variation of the reference current I of the reference current generating circuit10. Further, since the capacitance values CINof the input terminal and the output terminal of the CMOS inverter1are independently detected/adjusted, for example, even though the parasitic capacitance of the external printed circuit board or the parasitic capacitance between a gate and a source of the CMOS inverter at the input side is different from that at the output side, the capacitance at the input side and the capacitance at the output side is set to be close to the ideal design capacitance values, respectively.

Second Embodiment

FIGS. 6A and 6Bare circuit diagrams of an oscillator according to a second embodiment. Similarly toFIGS. 2 and 3,FIGS. 6A and 6Billustrate a crystal resonator4and a circuit5connected to the external crystal resonator4and disposed inside an IC chip that configures the oscillation circuit DCXO. The same circuit components as inFIGS. 2 and 3are denoted by the same reference numerals.

A configuration ofFIGS. 6A and 6Bis different from the configuration ofFIGS. 2 and 3in that an external component resistor3is disposed instead of the internal feedback resistor3that has been interposed between the input and the output of the CMOS inverter1, and as an IC internal resistor9is disposed instead of the external resistor component9for generating the reference voltage VR. Further, disposed are switches7aand7bfor supplying the input and the output of the CMOS inverter1with a bias potential (a first potential) V1, a resistor13for generating the bias potential V1, and switches7cand7dthat connect the input and the output of the CMOS inverter1with the comparator11, respectively.

In addition, a first voltage generating circuit that generates the first voltage (the bias potential) V1is configured with a transistor P3of the reference current generating circuit10and the internal resistor13. Further, a second voltage generating circuit that generates the reference voltage VRis configured with a transistor P2and the internal resistor9.

In the second embodiment, similarly to the first embodiment, the input potential of the CMOS inverter1is defined as VC, and a description will be made in connection with a calibration operation for detecting/adjusting the capacitance value of the load capacitor2aat the input side of the CMOS inverter1. The calibration operation is performed during an operation preparation time such as when electrical power is turned on.

FIG. 7is a timing diagram of a calibration operation according to the second embodiment.

First, at a time T0ofFIG. 7, as illustrated inFIG. 6A, the switch6that connects the oscillation loop of the oscillator and makes electrical power enable is turned off, and the switch7afor applying the bias potential V1to the input terminal of the CMOS inverter1and the switch7cfor supplying the input of the comparator11with the input terminal voltage VCof the inverter1are turned on. In this state, the switches8aand8bfor fixing the input and the output of the CMOS inverter1to the GND potential are in an OFF state. Thus, there is no path through which electric charges from the input and output terminals of the CMOS inverter1are discharged, and the potential VCof the input terminal of the CMOS inverter1is raised to the bias potential V1decided by the reference current I of the reference current generating circuit10and the IC internal resistor13. That is, the load capacitor2aof the input terminal of the inverter1and the parasitic capacitor thereof are charged to the bias potential V1, so that VCbecomes equal to V1.

Next, at a time T1ofFIG. 7, as illustrated inFIG. 6B, the switch7ais turned off, and the switch8bfor fixing the output terminal of the CMOS inverter1to the GND potential is turned on. Thus, formed is a path through which electric charges are discharged from the input terminal of the CMOS inverter1to the GND potential via the external resistor3and the switch8b. As a result, the voltage VCof the input terminal of the inverter1is lowered by discharging.

If Rfis defined as a resistance value of the external resistor3and CIN(=C2a+C0+CP) as a total capacitance viewed at the input terminal of the CMOS inverter1, the potential VCof the input terminal decreases from the bias potential (the first voltage) V1according to a time constant of RfCINas a time goes by when the switch8bis turned on. The potential VCof the input terminal decreases as VC=V1(exp(−t/RfCIN)).

Thus, when one cycle of the clock CLK (the frequency FC) that becomes a reference elapses, that is, at a time T2after t=1/FC, the potential VCof the input terminal becomes V1=exp(−1/(FC·Rf·CIN)).

If CIDLis an ideal capacitance expected as the design value, when CIN<CIDL, the potential VCis lower than when CIN=CIDL, and when CIN>CIDL, the potential VCis higher than when CIN=CIDL. That is, when CIN<CIDL, since the charge quantity by the bias voltage V1is small, the potential drop of the potential VCafter one cycle of the clock CLK is large, whereas when CIN>CIDL, since the charge quantity is large, the potential drop of the potential VCis small. Thus, by monitoring the potential at a time T2after discharging starts, a relative magnitude of the IC internal capacitance CINto the ideal capacitance CIDLwill be measured.

The comparator11compares the potential (the discharging voltage) VCof the input terminal with the previously set reference potential VRat certain timing. In order to make the potential VCobtained after one cycle t(=1/Fc) of the clock CLK equal to the reference potential VRwhen the total capacitance CINof the input terminal is equal to the ideal capacitance CIDL, the resistance value Rfof the feedback resistor3is preferably set as follows. In order to satisfy VR=VC=V1(exp(−1/(Fc·Rf·CIN))), the resistance value Rfof the feedback resistor is preferably set as in Equation 6:
Rf=1/(FC·CIN·In(V1/VR))  Equation 6

The parameters FC, V1, VR, and Rfare decided according to the ideal value CIDLof the capacitance CINof the input terminal that is desired to set or an operation condition (the speed or a dynamic range) of the comparator so that Equation 6 will be true. For example, when the capacitance CINof the input terminal is set to 11 pF, if FCis 2 MHz, V1is 1.0 V, and VRis 0.4 V, Rf≈50 kΩ is preferable in terms of Equation 6. The resistance value Rfof the external resistor3will be set with a high degree of accuracy.

In the calibration operation, as illustrated inFIG. 7, the comparator11compares with the potential VCwith the reference voltage VRat timing when the clock CLK rises to a high level, and the control circuit12controls the control code DA based on the comparison result. That is, similarly to the first embodiment, the control circuit12performs control so that the capacitance value of the load capacitor2ais equal to the ideal value by changing the control code DA for increasing or decreasing the number of turned-on switches of the load capacitor2aso that the comparison result becomes close to VC=VR.

Timing by the comparator11need not necessarily be timing when one cycle of the clock CLK elapses after charging starts, and timing may be selected so that Equation 6 will be true.

After the number of turned-on switches is obtained, setting information such as the control code DA is saved in the register inside the control circuit. Then, a similar calibration operation is performed even on the load capacitor2bat the output side of the CMOS inverter1. That is, by replacing the switch7awith the switch7b, the switch7cwith the switch7d, the switch8awith the switch8b, and the load capacitor2awith the load capacitor2b, a similar comparison process and similar control of the control code DB are performed. When the control code DB of the load capacitor2bat the output terminal is decided, setting information thereof is saved in the register inside the control circuit. Then, transition to the normal operation is performed by turning the switch6on and turning switches7ato7d,8a, and8boff.

In the first embodiment, the potential VCis measured during the charging operation of the load capacitors2aand2b, whereas in the second embodiment, the potential VCis measured during the discharging operation of the load capacitors2aand2b. In the second embodiment, as seen from the Equation 6, when the resistance value Rfof the external feedback resistor3has a high degree of accuracy, it is detected with a high degree of accuracy whether or not the capacitances CINof the input and output terminals of the inverter1are equal to the ideal capacitance CIDL. Further, even in the second embodiment, since the bias potential (the first voltage) V1and the reference potential VRwhich are set in advance are generated based on the reference current value I of the reference current generating circuit10and the IC internal resistors13and9, respectively, the comparator11performs a comparison operation with a high degree of accuracy regardless of a variation in the reference current value I.

Third Embodiment

FIGS. 8 and 9are circuit diagrams of an oscillation circuit according to a third embodiment. Similarly toFIGS. 6A and 6B,FIGS. 8 and 9illustrate a crystal resonator4that configures the oscillation circuit DCXO and a circuit5which is connected to the external crystal resonator4and disposed inside an IC chip. The same circuit components as inFIGS. 6A and 6Bare denoted by the same reference numerals.

A configuration ofFIGS. 8 and 9is different from the configuration ofFIGS. 6A and 6Bin that an IC internal resistor3is disposed instead of the external resistive element3interposed between the input and the output of the CMOS inverter1, a switch14athat causes a short circuit between the terminals of the load capacitor2aand a switch14bthat causes a short circuit between the terminals of the load capacitor2bare added. Further, the switches7cand7dthat connect the input and output terminals of the CMOS inverter1with the input of the comparator11, respectively, are removed.

In addition, a first voltage generating circuit that generates the first voltage (the bias potential) V1is configured with the transistor P3of the reference current generating circuit10and the internal resistor13. Further, a second voltage generating circuit that generates the reference voltage VRis configured with the transistor P2and the internal resistor9.

A description will be made below in connection with a calibration operation of detecting and adjusting the capacitance value of the load capacitor2aat the input terminal side of the CMOS inverter1.

As illustrated inFIG. 8, the switch6that connects the oscillator loop and makes electrical power enable is turned off, and the switches7aand7bfor applying the bias potential (the first voltage) V1to the input and output terminals of the CMOS inverter1and the switches14aand14bfor causing short circuits between the terminals of the load capacitors2aand2b, respectively, are turned on. In this state, a portion between both terminals of the parallel capacitor C0of the crystal resonator and a portion between terminals of the load capacitor2aand the parasitic capacitor CPare fixed to the bias potential V1.

FIGS. 10A and 10Bare equivalent circuit diagrams in a calibration operation ofFIGS. 8 and 9, respectively.FIG. 11is a timing diagram of a calibration operation. As shown inFIG. 10A, the charge quantity of the capacitors around C0, CPand C2aare zero in theFIG. 8connection.

Next, at a time T1ofFIG. 11, as illustrated inFIGS. 9 and 10B, the switches7aand14aare turned off, and the switch8ais turned on. As a result, the parallel capacitor C0of the crystal resonator, the load capacitor2a, and the parasitic capacitor CPare serially connected between the bias potential V1and the ground GND. Since charge injection from the outside or discharging to the outside is not performed when a state ofFIG. 10Achanges to a state ofFIG. 10B, the charge quantity (=0) ofFIG. 10Ais equal to the charge quantity ofFIG. 10Bdue to the principle of charge conservation, and thus the following equation is true:
0=VC·(C2a+CP)+(VC−V1)·C0
If this equation is solved, the potential VCof the CMOS inverter1that is a serially connected intermediate node is as follows:
VC=V1·C0/(C2a+C0+CP)=V1·C0/CINEquation 7

This means that the potential VCchanges from the bias potential (the first voltage) V1to V1·C0/CINwhen the switches are switched from a state ofFIG. 10A(FIG. 8) to a state ofFIG. 10B(FIG. 9) and means that the total capacitance CINof the input terminal relative to the ideal capacitance value CIDLwill be detected when the equivalent parallel capacitance value C0of the crystal resonator that is an external component is fixed. If CIDLis the ideal capacitance expected as the design value, the potential VCof the input terminal after switching of the switches is higher than when CIN=CIDLif CIN<CIDLand is lower than when CIN=CIDLif CIN>CIDL.

The comparator11compares the potential VCwith the previously set reference potential VR. For example, in the case of desiring to set CINto 11 pF using the crystal resonator in which C0is 1 pF, the reference voltage VRis set so that VR=V1·C0/CIN=V1/11 is true. That is, when an operation is performed at the potential V1of 1.1 V, the resistance values of the IC internal resistors13and19and the current value of the current source circuit10are decided so that VRwill be 0.1 V.

The comparator11compares the potential VCwith the potential VRat arbitrary timing after switching of the switches at the time T1. Similarly to the first and second embodiments, based on the comparison result of the comparator11, the control circuit12performs control so that the total capacitance CINof the input terminal of the inverter will be close to the ideal capacitance CIDLby increasing or decreasing the number of turned-on switches of the load capacitor2athat is a variable capacitive element and so changing the value of the load capacitor2a. That is, the control circuit12sets the control code DA so that the potential VCwill be almost equal to the potential VR.

After the number of turned-on switches is obtained, setting information such as the control code DA is saved in the register inside the control circuit12. Then, a similar calibration operation is performed even on the output side of the CMOS inverter1. That is, by replacing the switch7awith the switch7b, the switch8awith the switch8b, the switch14awith the switch14b, and the load capacitor2awith the load capacitor2b, a similar comparison and similar setting of the control code are performed. When the control code detection operation at the output terminal side is finished, similarly, setting information thereof is saved in the register inside the control circuit. Then, transition to the normal operation is performed by turning the switch6on and turning switches7a,7b,8a,8b,14a, and14boff.

In the third embodiment, since the capacitance value is relatively detected according to a potential change by movement of electric charges, when the parallel capacitance value C0of the external crystal resonator does not greatly vary, the capacitance value CINwill be adjusted with a high degree of accuracy. Further, in the present embodiment, the case of using the operation clock CLK has been described, but since the potential VCis maintained at a certain potential after switching of the switches as illustrated inFIG. 11, comparison timing of the comparator may be arbitrary timing after switching of the switches. Thus, the calibration operation may be performed using a combination logic circuit without using a high-accuracy clock CLK.

FIG. 12is a diagram illustrating a modified circuit of the first and second embodiments. In the first embodiment, the comparison operation is performed at timing when one cycle or N cycles of the clock CLK elapse after charging starts, whereas in the second embodiment, the comparison operation is performed at timing when one cycle or N cycles of the clock CLK elapse after discharging starts. For this reason, the clock CLK needs to be supplied from any place.

In the modified circuit ofFIG. 12, a circuit25that includes a second inverter21, a second feedback resistor23, and load capacitors22aand22bthat configures the oscillation circuit together with the crystal resonator4is further disposed inside the IC. As switches13disposed on the terminals61and62, one at the circuit25side is turned on and one at the circuit5side off, the crystal oscillator is configured with the crystal resonator4and the circuit25, and the clock CLK generated by the crystal oscillator is supplied as a reference clock of the control circuit12inside the circuit5. Also, the clock CLK is supplied to the comparator11.

The circuit5ofFIG. 12is the same as the circuit5according to the first embodiment but may be the same as that according to the second embodiment. In this case, the clock CLK in the second embodiment is used as the reference clock of the calibration operation.

The circuit25includes the CMOS inverter21, the internal capacitors22aand22bthat are connected to the input and the output of the CMOS inverter21, respectively, a resistive element23that is interposed between the input and the output of the CMOS inverter21and serves to make the DC potentials of the input be equal to the DC potential of the output, and a switch26that connects the oscillation loop of the oscillation circuit with the resonator4and makes electrical power enable.

In this modified circuit, the clock CLK in the first or second embodiment is generated by the oscillation circuit including the circuit25inside the IC and the crystal resonator4. That is, when the calibration operation is performed during the operation preparation time such as when electrical power is turned on, the oscillation circuit configured with the crystal resonator4and the circuit25by a connection illustrated inFIG. 12oscillates. That is, the switch6is turned off, the switch26is turned on, and the switches13are controlled to connect the crystal resonator4with the circuit25. The oscillation circuit configured with the crystal resonator4and the circuit25starts to oscillate, and the clock CLK output from the oscillation circuit is input to the comparator11and the control circuit12. Thus, the calibration operation is performed by the circuit inside the IC without being supplied with the clock from the outside.

The load capacitors22aand22binside the circuit25are preferably fixed capacitors for oscillation, and the capacitance value thereof does not require a degree of absolute accuracy. This is because even if the load capacitors22aand22bhave been manufactured to have values greatly deviated from design values and the clock CLK has been deviated from the ideal frequency by 100 ppm, an error of the potential VCof Equation 3 is mere 0.01% on the ideal clock frequency, and thus it is sufficient as a degree of accuracy of the clock used at the time of capacitance correction.

After calibration of the load capacitance according to the first or second embodiment using the clock CLK is performed, transition to the normal operation is performed by turning the switch6on, turning the switch26off, and controlling the switch13so that the crystal resonator4is connected with the circuit5.

FIGS. 13A and 13Bare diagrams illustrating a modified circuit of the first to third embodiments.FIG. 14is a timing diagram of the circuit illustrated inFIG. 13A.

In the second modification, as illustrated inFIG. 13A, in addition to the circuit5of the oscillation circuit other than the crystal resonator, a starter circuit30is disposed inside the IC chip. The clock CLK and a power voltage VDDX are supplied to the circuit5from a power regulator (not illustrated), whereas the clock CLK and two power voltages VDD and VDDX are supplied to the starter circuit30from the power regulator. The power regulator first starts a first power voltage VDD at the time of power activation and then starts a second power voltage VDDX. Using a sequence of two power voltages VDD and VDDX, the starter circuit30generates the reset signal XRST before the calibration operation starts and the enable signal EN for controlling the calibration start and supplies the circuit5with these signals.

Further, the starter circuit30illustrated inFIG. 13Bis a shift register including flip flop circuits70to73. The first power voltage VDD is input to a data terminal D of the flip flop circuit70, the second power voltage VDDX is input to reset terminals RB of the flip flop circuit70to73, and the clock CLK is supplied to clock terminals. Further, outputs Q2and Q3of the second and third flip flop circuits are input to an NAND gate74.

As illustrated in an operation diagram ofFIG. 14, before power is activated, the reset signal XRST and the enable signal EN have the low level. If the first power voltage VDD transitions to the high level at the same time when system power is activated and then the second power voltage VDDX transitions to a high level (at a time t2), the flip flop circuits are once reset, the output Q2and Q3have the low level, and the reset signal XRST of the high level is output from the AND gate74. Then, at a time t3of the clock CLK, the output Q1transitions to the high level, and at a time t4, the output Q2transitions to the high level, and the output Q3has the low level. Thus, at the time t4, the NAND gate outputs the reset signal XRST of the low level. The reset signal XRST of the low level resets the inside of the circuit5.

In addition, at a time t5, the output Q3transitions to the high level, and the NAND gate outputs the reset signal XRST of the high level, so that the reset is released. Finally, at a time t6, the output Q of the flip flop73transitions to the high level, and so the enable signal EN transitions to the high level. In response to this, the circuit5starts the calibration operation. In the calibration operation, as described above, control of a group of switches according to each of the first to third embodiments starts.

According to this modified circuit, by disposing the starter circuit30inside the IC, a self calibration operation is performed without complicated control from the outside.

FIGS. 15A and 15Bare diagrams illustrating another modified circuit of the first to third embodiments.

In this modified circuit, as illustrated inFIG. 15A, the IC chip includes the circuit5of the oscillation circuit DCXO other than the crystal resonator4and the starter circuit30. In addition, a terminal62for receiving a clock of a second oscillation circuit element40such as VCTCXO is disposed inside the IC chip. Inside the IC chip, disposed is a clock detector circuit50that detects whether or not a clock VCK has been supplied to the terminal62. Further, an OR gate81outputs either the clock VCK from the oscillation circuit element40or the clock from the oscillation circuit DCXO configured with the crystal resonator4and the circuit5as a generation clock SCK. The clock SCK is used as the reference clock of the PLL synthesizer inside the RF circuit.

Further, the enable signal EN of the starter circuit30is gated by an AND gate80according to a logic level of a detection signal PD of the clock detector circuit50and supplied to the circuit5as an enable signal ENXO for the oscillation circuit DCXO. The starter circuit30is the same as in the second modified circuit illustrated inFIGS. 13A,13B, and14.

In this modification, any one of two oscillation circuits, that is, any one of the oscillation circuit DCXO (the crystal resonator4and the circuit5) and the oscillation circuit element40such as the oscillation circuit VCTCXO may be arbitrarily selected. Further, switching is performed depending on whether the crystal resonator4or the oscillation circuit element40is connected as an external component to the IC chip, without using electrical control from the outside.

For example, when it is desired to manufacture a portable terminal of a low cost even though an initial variation of the clock SCK is large and a degree of accuracy is low, the clock of the oscillation circuit DCXO is used by connecting the crystal resonator4. Further, when it is desired to manufacture a portable terminal in which an initial variation of the clock SCK is small and a degree of accuracy is high, an expensive oscillation circuit element40such as VCTCXO is connected and used. Through the configuration capable of selecting the external component of the oscillator and connecting it with the IC chip, an oscillation circuit according to a customer's specification is configured by the same circuit, the same chip configuration, the same system, and the same software. By providing general versatility as described above, the cost will be reduced.

The external oscillator40outputs the clock VCK when the power voltage VDDV is supplied from a power management module. The clock detector circuit50includes a diode D1, a capacitor C10, resistors RA and RB, and a comparator51as illustrated inFIG. 15B. The clock detector circuit50outputs the detection signal PD of a high level when the clock VCK is input from the oscillator40but outputs that of a low level when the clock VCK is not input from the oscillator40.

The potential of a node VP inside the clock detector circuit50is raised by an electric current from the diode D1when the clock VCK is input, but is not raised when the clock VCK is not input because the diode D1does not allow an electric current to flow. The comparator51is a circuit that outputs the detection signal PD of a high level when the potential of the internal node VP is higher than the potential of the bias voltage VR (for example, VR=VDD/2). Thus, the comparator51outputs the signal of the high level at a point in time when the potential of the node VP exceeds the internal bias voltage VR if the clock VCK is input, but outputs the signal of the low level when the clock VCK is not input.

The enable signal ENXO input to the circuit5of the oscillation circuit DCXO is generated by NAND gate that inputs an inversion of a logic level of the detection signal PD of the clock detector circuit50and the enable signal EN generated by the starter circuit30through the AND gate80. That is, when the oscillator40is connected, since the detection signal PD becomes a high level by the clock VCK generated by the oscillator40, even if the enable signal EN from the starter circuit30has a high level, the enable signal ENXO becomes a low level, so that the circuit5of the oscillation circuit DCXO does not operate. Further, when the crystal resonator4is connected, the clock VCK is not input, and the detection signal PD remains a low level. For this reason, the enable signal EN from the starter circuit30becomes the enable signal ENXO “as is”, and the calibration operation of the circuit5starts by the enable signal ENXO. The output clock SCK is obtained by OR gate that inputs the clock VCK from the oscillator (for example, VCTCXO)40and the clock from the circuit5that configures the oscillation circuit DCXO.

FIG. 16is a timing diagram illustrating an operation when the oscillator (for example, VCTCXO)40is connected as the external component. The oscillator40outputs the clock VCK when the power voltage VDDV is input. The clock detector circuit50operates at the rising edge of the power voltage VDD of the system, and the detection output PD transitions to a high level when the voltage VP is higher than the reference voltage VR. Meanwhile, the starter circuit30generates the reset signal XRST and the enable signal EN of the circuit5of the oscillation circuit DCXO. Since the enable signal EN has the high level but an inversion of the detection output PD of the clock detector circuit50transitions to the low level, the enable signal ENXO of the low level is output from the AND gate80, and the circuit5becomes a power-down state. In this case, the clock output from the circuit5is fixed to the low level, and the clock VCK of the VCTCXO40is output from the OR gate81as the output clock SCK.

Further, when the crystal resonator4is externally connected, since the detection output PD of the clock detector circuit50has the low level, the enable signal ENXO of the high level is output from the AND gate80, and so the oscillator DCXO configured with the crystal resonator4and the circuit5performs an oscillation operation. In this case, since the oscillator40is not connected, the clock VCK has the low level, and the clock from the circuit5that configures the oscillation circuit DCXO is output as the output clock SCK through the OR gate81.

According to the first, second and third embodiments, there are the following advantages.

(1) The frequency deviation of the oscillator is not detected by directly measuring an oscillation frequency in an AC manner by an external measuring device or the like, but is detected by measuring a variation in capacitance value deciding an oscillation frequency in a DC manner by a circuit inside an IC. Thus, an extensive measuring environment is not necessary, and the cost is reduced.

(2) Since a variation in capacitance value is measured and detected in a DC manner by a circuit inside an IC, capacitance correction for reducing the variation is performed by self-completion within its own circuit using the comparator, the switch, or the control circuit.

(3) The capacitance is corrected by the calibration operation during the operation preparation time such as when electrical power is turned on, and the result is saved in the register and reflected at the time of the normal operation. Thus, an initial variation of the oscillator is reduced.

(4) Since the external component of the oscillator may be arbitrarily selected and connected, different uses may be made according to a customer's specification by the same circuit, the same chip configuration, the same system, and the same software, and the cost is reduced.