LOW POWER AND AREA OPTIMIZED TM4 AND TM5 COMPLIANT COMBINATION TMIO TRANSMITTER ARCHITECTURE

The application discloses a system for altering an input/output (I/O) data signal of a NAND programming operation. The system includes a skew-gen circuit comprising: a delay block coupled to an input of a two input logic OR gate, and a MUX logic gate coupled to an output of the logic OR gate. The skew-gen circuit is configured to: alter the pulse width of a input data signal by increasing the width of the data high signal and decreasing the width of the data low signal; and output the altered data signal to the MUX, the MUX configured to select either the altered data signal or the input data signal depending on the mode.

BACKGROUND

Semiconductor memory is widely used in various electronic devices, such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile and non-mobile computing devices, vehicles, and so forth. Semiconductor memory may comprise non-volatile memory and/or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory) and Electrically Erasable Programmable Read-Only Memory (EEPROM).

NAND-type flash memories typically have multiple memory dies or chips controlled by a controller. Each die contains a memory array and peripheral circuits. At any one time, each die may be involved in various memory operations including input/output (I/O) operations with the memory controller. I/O operations are demanding on peripheral circuits. For example, in enterprise SSD (Solid-State Disk) and Client SSD the input/output (“I/O”), there may be 8 to 16 dies stacked on same I/O channel or interface and they may operate at 200 MHz (Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM)) speed with reduced power.

DETAILED DESCRIPTION

NAND memory includes various input (I/O) interface standards for transmission signaling. For example, NAND memory interfaces can include fourth generation standards (Open NAND Flash Interface (ONFI) 4.0) and fifth generation standards (ONFI 5.0). The fourth generation standard introduces the Non-volatile DDR3 (NV-DDR3) data interface. Operation of the NV-DDR3 interface (e.g., NV-DDR3 operation) allows the I/O power (VCCQ) requirement to reach down to 1.2V to support a lower voltage for signaling in a 1.2V controller. The release of ONFI 5.0 specifications added an additional NV-LPDDR4 data interface. Operation of the NV-LPDDR4 interface (e.g., NV-LPDDR4 operation) emphasizes lowering overall power consumption while upscaling the transfer rate of each interface. For example, the ONFI 5.0 standard upscales the transfer rate of the NV-DDR3 and NV-LPDDR4 interfaces to 2400MT/s.

The NV-DDR3 interface uses center tapped terminated (CTT) signaling. To properly conduct CTT signaling, the NV-DDR3 data interface requires a PMOS based pull-up driver. In contrast, NV-LPDDR4 interface I/Os uses low voltage swing terminated logic (LVSTL) signaling for high-speed signaling. NV-LPDDR4 data interfaces can use NMOS pull-up drivers. NV-DDR3 and NV-LPDDR4 data interfaces can use combination PMOS/NMOS pull-up drivers.

Although conventional PMOS based pull-up drivers can be used in NV-Low-Power DDR4 (NV-LPDDR4) operation, they suffer from a variety of deficiencies. For example, during NV-LPDDR4 operation, the PMOS based pull-up driver performance degrades due to an imbalance in output rise and fall in slew-rates since pull-up impedance doubles when compared to ODT impedance. This failure is amplified, and thus especially significant, when a higher load is applied.

The conventional design of a combination PMOS and NMOS pull-up driver used in NV-LPDDR4 operation addresses the deficiencies of the PMOS based pull-up driver during LPDDR4 operation. However, the combination PMOS and NMOS pull-up driver results in an increase in circuit area an increase in capacitance at the I/O pad and an increase in power (e.g., static power and dynamic power). For example, because the combination PMOS and NMOS pull-up driver includes a plurality of NMOS pull-up drivers, the footprint of the circuit is increased. The additional circuit footprint results in decreased circuit performance.

The skew-gen circuit proposed herein allows for a PMOS based-pull up driver to be used in NV-LPDDR4 operation without the need for a plurality of NMOS pull-up drivers. Thus, the skew-gen circuit allows for area and power savings by removing the need to combine PMOS and NMOS pull-up drivers. The skew-gen circuit proposed herein also continues to meet the performance and output requirements of the ONFI specification.

The skew-gen circuit is configured to alter the pulse-width of the input signal and pass skewed signal to sub-sequent blocks (e.g., remaining datapath, pre-driver and driver). The pulse-width of the skewed the signal is altered such that pulse-width of data high signal increases and pulse-width of data low signal reduces for LVSTL signaling. Altering the pulse width of the data high signal alters the ON time of the pull-up driver and pull-down driver during NV-LPDDR4 operation. Thus the increased width of the pulse increases the ON time of the pull-up driver and reduces ON time the pull-down driver for LVSTL signaling.

In one embodiment, the skew-gen circuit includes a plurality of skew-gen circuit components. The plurality of skew-gen circuit components includes a delay block. The input signal is coupled to a first input of the OR/AND gate. The delay block is communicatively coupled to a second input of the two input logic OR/AND gate. The logic OR/AND gate includes an output communicatively coupled to an input of a MUX. The MUX includes a mode input configured to inactivate the skew-gen circuit during NV-DDR3 operation and activate the skew-gen circuit during NV-LPDDR4 operation.

The plurality of skew-gen circuit components are configured to increase the pulse width of the I/O data high signal. Each individual component of the plurality of skew-gen circuit components is configured to alter the pulse width of the data signal (both high and low). For example, the delay block coupled to the second input of the OR gate is configured to skew the data high signal by increasing the pulse duration, which increases the pulse width. The skewed signal is passed to the pull-up and pull-down driver through their respective pre-drivers. The increased pulse width increases the ON time for the pull-up driver and reduces the ON time for pull-down driver.

FIG.1is a block diagram of an example non-volatile memory system100. In one embodiment, the non-volatile memory system100is a card-based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, memory system100is part of an embedded memory system. For example, the flash memory may be embedded within the host. In other examples, memory system100can be a solid state drive (SSD). The non-volatile memory system100includes one or more non-volatile memory dies108, and a controller122. The memory die108can be a complete memory die or a partial memory die. As seen here, the memory die108includes a memory structure126, control circuitry110, and read/write/erase circuits128. The memory structure126is addressable by wordlines via a row decoder124and by bitlines via a column decoder132. The read/write/erase circuits128include multiple sense blocks150including SB1, SB2, . . . , SBp (hereinafter referred to as sensing circuitry). The read/write/erase circuits128and sensing circuitry allow a page of memory cells to be read, programmed, or erased in parallel.

In one embodiment, memory structure126comprises a three-dimensional (3D) memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material. In another embodiment, memory structure126comprises a two-dimensional (2D) memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates.

The exact type of memory array architecture or memory cell included in memory structure126is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure126. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure126include 2D arrays, 3D arrays, and other memory structures that may have a string configuration. Although current iterations of other memory structure (e.g., MRAM, PCM, and Spin RAM) are configured without a string, memories of these cells can be configured into a topology that has a string, and thus could be utilized in a format that would allow them to be erased in a block format and programmed in chunks. Thus, in this potential configuration, embodiments of the disclosure could be foreseeably applied.

The control circuitry110cooperates with the read/write/erase circuits128to perform memory operations (e.g., write, read, erase) on memory structure126, and includes state machine112, an on-chip address decoder114, and a power control circuit116. In one embodiment, control circuitry110includes buffers such as registers, read-only memory (ROM) fuses and other storage devices for storing default values such as base voltages and other parameters. The on-chip address decoder114provides an address interface between addresses used by host140or controller122and the hardware address used by the decoders124and132. Power control circuit116controls the power and voltages supplied to the wordlines, bitlines, and select lines during memory operations. The power control circuit116includes voltage circuitry, in one embodiment. Power control circuit116may include charge pumps for creating voltages. The sense blocks150include bitline drivers. The power control circuit116executes under control of the state machine112, in one embodiment.

State machine112and/or controller122(or equivalently functioned circuits), in combination with all or a subset of the other circuits depicted inFIG.1, can be considered a control circuit that performs the functions described herein. Such a control circuit can include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuit. A control circuit can include a processor, a PGA (Programmable Gate Array), an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or another type of integrated circuit or circuit more generally.

The controller122interfaces with the one or more memory dies108. In one embodiment, controller122and multiple memory dies (together comprising non-volatile storage system100) implement an SSD, which can emulate, replace, or be used in place of a hard disk drive inside a host, as a network access storage (NAS) device, in a laptop, in a tablet, in a server, etc. Additionally, the SSD need not be made to work as a hard drive.

Some embodiments of the non-volatile storage system100may include one memory die108connected to one controller122. Other embodiments may include multiple memory dies108in communication with one or more controllers122. In one example, the multiple memory dies108can be grouped into a set of memory packages. Each memory package may include one or more memory dies108in communication with controller122. In one embodiment, a memory package includes a printed circuit board (or similar structure) with one or more memory dies108mounted thereon. In some embodiments, a memory package can include molding material to encase the memory dies108of the memory package. In some embodiments, controller122is physically separate from any of the memory packages.

In one embodiment, a controller122is included in the same package (e.g., a removable storage card) as the memory die108. In other embodiments, the controller is separated from the memory die108. In some embodiments the controller is on a different die than the memory die108. In some embodiments, one controller122communicates with multiple memory dies108. In other embodiments, each memory die108has its own controller. Commands and data are transferred between a host140and controller122via a data bus120, and between controller122and the memory die108via bus lines118. In one embodiment, memory die108includes a set of input and/or output (I/O) pins that connect to bus lines118.

The controller122includes one or more processors122c, ROM122a, random access memory (RAM)122b, a memory interface (MI)122d, and a host interface (HI)122e, all of which may be interconnected. The storage devices (ROM122a, RAM122b) store code (software) such as a set of instructions (including firmware), and one or more of the processors122care operable to execute the set of instructions to provide functionality described herein (e.g., non-transitory computer readable storage medium). Alternatively or additionally, one or more processors122ccan access code from a storage device in the memory structure, such as a reserved area of memory cells connected to one or more wordlines. RAM122bcan be used to store data for controller122, including caching program data (discussed below). MI122d—in communication with ROM122a, RAM122b, and processor(s)122c—may be an electrical circuit that provides an electrical interface between controller122and memory die108. For example, MI122dcan change the format or timing of signals, provide a buffer, isolate from surges, latch I/O, etc. One or more processors122ccan issue commands to control circuitry110(or another component of memory die108) via MI122d. Host interface122eprovides an electrical interface with host140via data bus120in order to receive commands, addresses and/or data from host140to provide data and/or status to host140.

FIG.2is a block diagram of example memory system100that depicts more details of one embodiment of controller122. While the controller122in the embodiment ofFIG.2is a flash memory controller, it should be appreciated that the one or more non-volatile memory dies108are not limited to flash memory. Thus, the controller122is not limited to the particular example of a flash memory controller. As used herein, a flash memory controller is a device that manages data stored on flash memory and communicates with a host, such as a computer or electronic device. A flash memory controller can have various functionality in addition to the specific functionality described herein. For example, the flash memory controller can format the flash memory to ensure the memory is operating properly, map out bad flash memory cells, and allocate spare memory cells to be substituted for future failed cells. Some part of the spare cells can be used to hold firmware to operate the flash memory controller and implement other features. In an example operation, when a host needs to read data from or write data to the flash memory, it will communicate with the flash memory controller. If the host provides a logical address to which data is to be read/written, the flash memory controller can convert the logical address received from the host to a physical address in the flash memory. Alternatively, the host itself can provide the physical address. The flash memory controller can also perform various memory management functions including, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid pages of data to a new block, so that the block can be erased and reused).

In some embodiments, non-volatile memory system100includes a single channel between controller122and non-volatile memory die108. However, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, 2, 4, 8 or more channels may exist between the controller and the memory die, depending on controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the controller and the memory die, even if only a single channel is shown in the drawings.

As depicted inFIG.2, controller122includes a front-end module208that interfaces with a host, a back-end module210that interfaces with the memory die108, and various other modules that perform functions which will now be described in detail. The components of controller122depicted inFIG.2may take various forms including, without limitation, a packaged functional hardware unit (e.g., an electrical circuit) designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro) processor or processing circuitry that usually performs a particular function of related functions, a self-contained hardware or software component that interfaces with a larger system, or the like. For example, each module may include an ASIC, an FPGA, a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof. Alternatively or additionally, each module may include software stored in a processor readable device (e.g., memory) to program a processor to enable controller122to perform the functions described herein. The architecture depicted inFIG.2is one example implementation that may (or may not) use the components of controller122depicted inFIG.1(e.g., RAM, ROM, processor, interface).

Referring again to modules of the controller122, a buffer manager/bus control214manages buffers in RAM216and controls the internal bus arbitration of controller122. ROM218stores system boot code. Although illustrated inFIG.2as located separately from the controller122, in other embodiments, one or both of RAM216and ROM218may be located within the controller. In yet other embodiments, portions of RAM216and ROM218may be located within the controller122, while other portions may be located outside the controller. Further, in some implementations, the controller122, RAM216, and ROM218may be located on separate semiconductor dies.

Front-end module208includes a host interface220and a physical layer interface (PHY)222that provide the electrical interface with the host or next level storage controller. The choice of the type of host interface220can depend on the type of memory being used. Examples of host interfaces220include, but are not limited to, SATA, SATA Express, SAS, Fiber Channel, USB, PCIe, and NVMe. The host interface220typically facilitates transfer for data, control signals, and timing signals.

Back-end module210includes an error correction code (ECC) engine224that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the non-volatile memory108. A command sequencer226generates command sequences, such as program and erase command sequences, to be transmitted to non-volatile memory108. A RAID (Redundant Array of Independent Dies) module228manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the non-volatile memory system100. In some cases, the RAID module228may be a part of the ECC engine224. Note that the RAID parity may be added as one or more extra dies, or may be added within the existing die, e.g., as an extra plane, an extra block, or extra WLs within a block. A memory interface230provides the command sequences to non-volatile memory die108and receives status information from non-volatile memory die108. In one embodiment, memory interface230may be a double data rate (DDR) interface, such as a Toggle Mode200,400, or greater interface. A flash control layer232controls the overall operation of back-end module210.

Additional components of system100illustrated inFIG.2include media management layer (MML)238, which performs wear leveling of memory cells of non-volatile memory die108, as well as, other discrete components240, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with controller122. In alternative embodiments, one or more of the physical layer interface222, RAID module228, MML238, or buffer management/bus controller214are optional components.

MML238(e.g., Flash Translation Layer (FTL)) may be integrated as part of the flash management for handling flash errors and interfacing with the host. In particular, MML238may be a module in flash management and may be responsible for the internals of NAND management. In particular, MML238may include an algorithm in the memory device firmware which translates writes from the host into writes to the memory126of die108. MML238may be needed because: 1) the memory126may have limited endurance; 2) the memory126may only be written in multiples of pages; and/or 3) the memory126may not be written unless it is erased as a block (or a tier within a block in some embodiments). MML238understands these potential limitations of the memory126which may not be visible to the host. Accordingly, MML238attempts to translate the writes from host into writes into the memory126.

FIG.3is a perspective view of a portion of a monolithic 3D memory array that includes a plurality of non-volatile memory cells, and that can comprise memory structure126in one embodiment.FIG.3illustrates, for example, a portion of one block of memory. The structure depicted includes a set of bitlines (BLs) positioned above a stack of alternating dielectric layers and conductive layers. For example purposes, one of the dielectric layers is marked as D and one of the conductive layers (i.e., wordline layers) is marked as WL. The number of alternating dielectric and conductive layers can vary based on specific implementation requirements. In some embodiments, the 3D memory array includes between 108-300 alternating dielectric and conductive layers. One example embodiment includes 96 data wordline layers, 8 select layers, 6 dummy wordline layers, and110dielectric layers. More or less than 108-300 layers can also be used. Data wordline layers include data memory cells. Dummy wordline layers include dummy memory cells. As will be explained below, the alternating dielectric and conductive layers are divided into four “fingers” by local interconnects LI.FIG.3shows two fingers and two local interconnects LI. Below the alternating D layers and WL layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that inFIG.3, the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. More details of the three dimensional monolithic memory array that comprises memory structure126is provided below with respect toFIG.4A-4G.

One of the local interconnects LI separates the block into two horizontal sub-blocks HSB0, HSB1. The block comprises multiple vertical sub-blocks VSB0, VSB1, VSB2. The vertical sub-blocks VSB0, VSB1, VSB2can also be referred to as “tiers.” Each vertical sub-block extends across the block, in one embodiment. Each horizontal sub-block HSB0, HSB1in the block is a part of vertical sub-block VSB0. Likewise, each horizontal sub-block HSB0, HSB1in the block is a part of vertical sub-block VSB1. Likewise, each horizontal sub-block HSB0, HSB1in the block is a part of vertical sub-block VSB2. For purpose of discussion, vertical sub-block VSB0will be referred to as a lower vertical sub-block, vertical sub-block VSB1will be referred to as a middle vertical sub-block, and VSB2will be referred to as an upper vertical sub-block. In one embodiment, there are two vertical sub-blocks in a block. There could be four or more vertical sub-blocks in a block.

A memory operation for a vertical sub-block may be performed on memory cells in one or more horizontal sub-blocks. For example, a programming operation of memory cells in vertical sub-block VSB0may include: programming memory cells in horizontal sub-block HSB0but not horizontal sub-block HSB1; programming memory cells in horizontal sub-block HSB1but not horizontal sub-block HSB0; or programming memory cells in both horizontal sub-block HSB0and horizontal sub-block HSB1.

The different vertical sub-blocks VSB0, VSB1, VSB2are treated as separate units for erase/program purposes, in one embodiment. For example, the memory cells in one vertical sub-block can be erased while leaving valid data in the other vertical sub-blocks. Then, memory cells in the erased vertical sub-block can be programmed while valid data remains in the other vertical sub-blocks. In some cases, memory cells in the middle vertical sub-block VSB1are programmed while there is valid data in the lower vertical sub-block VSB0and/or the upper vertical sub-block VSB2. Programming the memory cells in middle vertical sub-block VSB1presents challenges due to the valid data in the other vertical sub-blocks VSB0, VSB2.

FIG.4Ais a block diagram explaining one example organization of memory structure126, which is divided into two planes302and304. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes can also be used. In on embodiment, a block of memory cells is a unit of erase. That is, all memory cells of a block are erased together. In other embodiments, memory cells can be grouped into blocks for other reasons, such as to organize the memory structure126to enable the signaling and selection circuits. In some embodiments, a block represents a groups of connected memory cells as the memory cells of a block share a common set of wordlines.

FIGS.4B-4Fdepict an example three dimensional (“3D”) NAND structure that corresponds to the structure ofFIG.3and can be used to implement memory structure126ofFIG.2.FIG.4Bis a block diagram depicting a top view of a portion of one block from memory structure126. The portion of the block depicted inFIG.4Bcorresponds to portion306in block2ofFIG.4A. As can be seen fromFIG.4B, the block depicted inFIG.4Bextends in the direction of332. In one embodiment, the memory array has many layers; however,FIG.4Bonly shows the top layer.

FIG.4Bdepicts a plurality of circles that represent the vertical columns. Each of the vertical columns include multiple select transistors (also referred to as a select gate or selection gate) and multiple memory cells. In one embodiment, each vertical column implements a NAND string. For example,FIG.4Bdepicts vertical columns422,432,442and452. Vertical column422implements NAND string482. Vertical column432implements NAND string484. Vertical column442implements NAND string486. Vertical column452implements NAND string488. More details of the vertical columns are provided below. Since the block depicted inFIG.4Bextends in the direction of arrow332, the block includes more vertical columns than depicted inFIG.4B.

FIG.4Balso depicts a set of bitlines415, including bitlines411,412,413,414, . . .419.FIG.4Bshows twenty-four bitlines because only a portion of the block is depicted. It is contemplated that more than twenty-four bitlines connected to vertical columns of the block. Each of the circles representing vertical columns has an “x” to indicate its connection to one bitline. For example, bitline414is connected to vertical columns422,432,442and452.

The block depicted inFIG.4Bincludes a set of local interconnects402,404,406,408and410that connect the various layers to a source line below the vertical columns. Local interconnects402,404,406,408and410also serve to divide each layer of the block into four regions; for example, the top layer depicted inFIG.4Bis divided into regions420,430,440and450, which are referred to as fingers. In the layers of the block that implement memory cells, the four regions are referred to as wordline fingers that are separated by the local interconnects. In one embodiment, the wordline fingers on a common level of a block connect together to form a single wordline. In another embodiment, the wordline fingers on the same level are not connected together. In one example implementation, a bitline only connects to one vertical column in each of regions420,430,440and450. In that implementation, each block has sixteen rows of active columns and each bitline connects to four rows in each block. In one embodiment, all of four rows connected to a common bitline are connected to the same wordline (via different wordline fingers on the same level that are connected together); therefore, the system uses the source side selection lines and the drain side selection lines to choose one (or another subset) of the four to be subjected to a memory operation (program, verify, read, and/or erase).

AlthoughFIG.4Bshows each region having four rows of vertical columns, four regions and sixteen rows of vertical columns in a block, those exact numbers are an example implementation. Other embodiments may include more or less regions per block, more or less rows of vertical columns per region and more or less rows of vertical columns per block.FIG.4Balso shows the vertical columns being staggered. In other embodiments, different patterns of staggering can be used. In some embodiments, the vertical columns are not staggered.

FIG.4Cdepicts an embodiment of a stack435showing a cross-sectional view along line AA ofFIG.4B. Two SGD layers (SGD0, SDG1), two SGS layers (SGS0, SGS1) and six dummy wordline layers DWLD0, DWLD1, DWLM1, DWLM0, DWLS0and DWLS1are provided, in addition to the data wordline layers WLL0-WLL95. Each NAND string has a drain side select transistor at the SGD0layer and a drain side select transistor at the SGD1layer. In operation, the same voltage may be applied to each layer (SGD0, SGD1), such that the control terminal of each transistor receives the same voltage. Each NAND string has a source side select transistor at the SGS0layer and a drain side select transistor at the SGS1layer. In operation, the same voltage may be applied to each layer (SGS0, SGS1), such that the control terminal of each transistor receives the same voltage. Also depicted are dielectric layers DL0-DL106.

Columns432,434of memory cells are depicted in the multi-layer stack. The stack includes a substrate301, an insulating film250on the substrate, and a portion of a source line SL. A portion of the bitline414is also depicted. Note that NAND string484is connected to the bitline414. NAND string484has a source-end439at a bottom of the stack and a drain-end438at a top of the stack. The source-end439is connected to the source line SL. A conductive via441connects the drain-end438of NAND string484to the bitline414. The metal-filled slits404and406fromFIG.4Bare also depicted.

The stack435is divided into three vertical sub-blocks (VSB0, VSB1, VSB2). Vertical sub-block VSB0includes WLL0-WLL31. The following layers could also be considered to be a part of vertical sub-block VSB0(SGS0, SGS1, DWLS0, DWLS1). Vertical sub-block VSB1includes WLL32-WLL63. Vertical sub-block VSB2includes WLL64-WLL95. The following layers could also be considered to be a part of vertical sub-block VSB2(SGD0, SGD1, DWLD0, DWLD1). Each NAND string has a set of data memory cells in each of the vertical sub-blocks. Dummy wordline layer DMLM0is between vertical sub-block VSB0and vertical sub-block VSB1. Dummy wordline layer DMLM1is between vertical sub-block VSB1and vertical sub-block VSB2. The dummy wordline layers have dummy memory cell transistors that may be used to electrically isolate a first set of memory cell transistors within the memory string (e.g., corresponding with vertical sub-block VSB0wordlines WLL0-WLL31) from a second set of memory cell transistors within the memory string (e.g., corresponding with the vertical sub-block VSB1wordlines WLL32-WLL63) during a memory operation (e.g., an erase operation or a programming operation).

In another embodiment, one or more middle junction transistor layers are used to divide the stack435into vertical sub-blocks. A middle junction transistor layer contains junction transistors, which do not necessarily contain a charge storage region. Hence, a junction transistor is typically not considered to be a dummy memory cell. Both a junction transistor and a dummy memory cell may be referred to herein as a “non-data transistor.” A non-data transistor, as the term is used herein, is a transistor on a NAND string, wherein the transistor is either configured to not store user or system data or operated in such a way that the transistor is not used to store user data or system data. A wordline that is connected to non-data transistors is referred to herein as a non-data wordline. Examples of non-data wordlines include, but are not limited to, dummy wordlines, and a select line in a middle junction transistor layer.

The stack435may have more than three vertical sub-blocks. For example, the stack435may be divided into four, five or more vertical sub-blocks. Each of the vertical sub-block contains at least one data memory cell. There may additional layers similar to the middle dummy wordline layers DWLM in order to divide the stack435into the additional vertical sub-blocks. In one embodiment, the stack has two vertical sub-blocks.

FIG.4Ddepicts an alternative view of the SG layers and wordline layers of the stack435ofFIG.4C. The SGD layers SGD0and SGD0(the drain-side SG layers) each includes parallel rows of SG lines associated with the drain-side of a set of NAND strings. For example, SGD0includes drain-side SG regions420,430,440and450, consistent withFIG.4B.

Below the SGD layers are the drain-side dummy wordline layers. Each dummy wordline layer represents a wordline, in one approach, and is connected to a set of dummy memory cells at a given height in the stack. For example, DWLD0comprises wordline layer regions451,453,455and457. A dummy memory cell, also referred to as a non-data memory cell, does not store data and is ineligible to store data, while a data memory cell is eligible to store data. Moreover, the Vth of a dummy memory cell is generally fixed at the time of manufacturer or may be periodically adjusted, while the Vth of the data memory cells changes more frequently, e.g., during erase and programming operations of the data memory cells.

Below the dummy wordline layers are the data wordline layers. For example, WLL95comprises wordline layer regions471,472,473and474. Below the data wordline layers are the source-side dummy wordline layers. Below the source-side dummy wordline layers are the SGS layers. The SGS layers SGS0and SGS1(the source-side SG layers) each includes parallel rows of SG lines associated with the source-side of a set of NAND strings. For example, SGS0includes source-side SG lines475,476,477and478. Each SG line can be independently controlled, in one approach. Or, the SG lines can be connected and commonly controlled.

FIG.4Edepicts a view of the region445ofFIG.4C. Data memory cell transistors520and521are above dummy memory cell transistor522. Below dummy memory cell transistor522are data memory cell transistors523and524. A number of layers can be deposited along the sidewall (SW) of the memory hole444and/or within each wordline layer, e.g., using atomic layer deposition. For example, each column (e.g., the pillar which is formed by the materials within a memory hole) can include a blocking oxide/block high-k material470, charge-trapping layer or film463such as SiN or other nitride, a tunneling layer464, a polysilicon body or channel465, and a dielectric core466. A wordline layer can include a conductive metal462such as Tungsten as a control gate. For example, control gates490,491,492,493and494are provided. In this example, all of the layers except the metal are provided in the memory hole. In other approaches, some of the layers can be in the control gate layer. Additional pillars are similarly formed in the different memory holes. A pillar can form a columnar active area (AA) of a NAND string.

When a data memory cell transistor is programmed, electrons are stored in a portion of the charge-trapping layer which is associated with the data memory cell transistor. These electrons are drawn into the charge-trapping layer from the channel, and through the tunneling layer. The Vth of a data memory cell transistor is increased in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel. For example, in one embodiment, the erase operation includes removing electrons from the floating gate in order to change the state of the cell to 1. During the erase operation, a large negative voltage is required to repel electrons from the floating gate. This can be accomplished by grounding the control gate and applying a high voltage (e.g., about 18V or more) to the substate. As a result, electrons are removed from the floating gate due to the FN tunneling effect.

Non-data transistors (e.g., select transistors, dummy memory cell transistors) may also include the charge trapping layer463. InFIG.4E, dummy memory cell transistor522includes the charge trapping layer463. Thus, the threshold voltage of at least some non-data transistors may also be adjusted by storing or removing electrons from the charge trapping layer463. It is not required that all non-data transistors have an adjustable Vth. For example, the charge trapping layer463is not required to be present in every select transistor.

Each of the memory holes can be filled with a plurality of annular layers comprising a blocking oxide layer, a charge trapping layer, a tunneling layer and a channel layer. A core region of each of the memory holes is filled with a body material, and the plurality of annular layers are between the core region and the WLLs in each of the memory holes. In some cases, the tunneling layer464can comprise multiple layers such as in an oxide-nitride-oxide configuration.

FIG.4Fis a schematic diagram of a portion of the memory depicted inFIGS.3-4E.FIG.4Fshows physical wordlines WLL0-WLL95running across the entire block. The structure ofFIG.4Fcorresponds to portion306in Block2ofFIGS.4A-E, including bitlines411,412,413,414, . . .419. Within the block, each bitline is connected to four NAND strings. Drain side selection lines SGD0, SGD1, SGD2and SGD3are used to determine which of the four NAND strings connect to the associated bitline(s). Source side selection lines SGS0, SGS1, SGS2and SGS3are used to determine which of the four NAND strings connect to the common source line. The block can also be thought of as divided into four horizontal sub-blocks HSB0, HSB1, HSB2and HSB3. Horizontal sub-block HSB0corresponds to those vertical NAND strings controlled by SGD0and SGS0, Horizontal sub-block HSB1corresponds to those vertical NAND strings controlled by SGD1and SGS1, Horizontal sub-block HSB2corresponds to those vertical NAND strings controlled by SGD2and SGS2, and Horizontal sub-block HSB3corresponds to those vertical NAND strings controlled by SGD3and SGS3.

FIG.4Gis being used to explain the concept of a selected memory cell. A memory operation is an operation designed to use the memory for its purpose and includes one or more of reading data, writing/programming data, erasing memory cells, refreshing data in memory cells, and the like. During any given memory operation, a subset of the memory cells will be identified to be subjected to one or more parts of the memory operation. These memory cells identified to be subjected to the memory operation are referred to as selected memory cells. Memory cells that have not been identified to be subjected to the memory operation are referred to as unselected memory cells. Depending on the memory architecture, the memory type, and the memory operation, unselected memory cells may be actively or passively excluded from being subjected to the memory operation.

As an example of selected memory cells and unselected memory cells, during a programming process, the set of memory cells intended to take on a new electrical characteristic (or other characteristic) to reflect a changed programming state are referred to as the selected memory cells while the memory cells that are not intended to take on a new electrical characteristic (or other characteristic) to reflect a changed programming state are referred to as the unselected memory cells. In certain situations, unselected memory cells may be connected to the same wordline as selected memory cells. Unselected memory cells may also be connected to different wordlines than selected memory cells. Similarly, during a reading process, the set of memory cells to be read are referred to as the selected memory cells while the memory cells that are not intended to be read are referred to as the unselected memory cells.

To better understand the concept of selected memory cells and unselected memory cells, assume a programming operation is to be performed and, for example purposes only, that wordline WL94and horizontal sub-block HS0are selected for programming (seeFIG.4G). That means that all of the memory cells connected to WL94that are in horizontal sub-blocks HSB1, HSB2and HSB3(the other horizontal sub-blocks) are unselected memory cells. Some of the memory cells connected to WL94in horizontal sub-block HS0are selected memory cells and some of the memory cells connected to WL94in horizontal sub-block HS0are unselected memory cells depending on how the programming operation is performed and the data pattern being programmed. For example, those memory cells that are to remain in the erased state S0will be unselected memory cells, because their programming state will not change in order to store the desired data pattern, while those memory cells that are intended to take on a new electrical characteristic (or other characteristic) to reflect a changed programming state (e.g., programmed to states S1-S7) are selected memory cells. Looking atFIG.4G, assume for example purposes, that memory cells511and514(which are connected to wordline WL94) are to remain in the erased state; therefore, memory cells511and514are unselected memory cells (labeled unsel inFIG.4G). Additionally, assume for example purposes that memory cells510,512,513and515(which are connected to wordline WL94) are to be programmed to any of the data states S1-S7; therefore, memory cells510,512,513and515are selected memory cells (labeled sel inFIG.4G).

Although the example memory system ofFIGS.3-4Gis a three dimensional memory structure that includes vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures can also be used with the technology described herein.

FIG.5is a block diagram of example memory system500that depicts more details of the example non-volatile memory system100and memory die108. The memory die108may be connected to the storage controller122via the memory interface524and operates based on commands from the storage controller122. For example, the memory die108transmits and receives, for example, one or more data signals (DQ signals) to and from the storage controller122via data bus118of the memory interface524. The one or more DQ signals may be an n-bit wide signal, where each data signal is a 1-bit wide signal. For example, n may be 7, thus the DQ signal may be an 8-bit wide signal. The DQ signals may be encoded with input/output (I/O) data, for example, data in (DIN)/data out (DOUT) for data operations (e.g., read operations, write operations, etc.), address data (e.g., address codes) for address sequencing for the data operations, and/or command data (e.g., command codes) for command sequencing for the data operations.

Data sent over the DQ signals is latched with respect to a rising edge or a falling edge of a clock (CLK) signal. The CLK signal, in various examples, can include a pair of complementary CLK signals, such as a DQS (e.g., data strobe signal) and DQSB (e.g., inverse data strobe signal). The DQSB CLK signal is the logical inverse of the DQS CLK signal. The DQSB CLK signal is added for redundancy since rising and falling edges of one signal may be distorted during transmission. DQ data can be latched on either or both of the rising and falling edges of the CLK signal to achieve a double data rate.

The memory die108also receives control (CO) signals, such as, but not limited to, chip enable (CEn) signal, command latch enable (CLE) signal, address latch enable (ALE) signal, write enable (WEn) signal, and read enable (REn) signal from the storage controller122via bus lines DQ, CO, CLK, R/Bn of the memory interface524. The memory die108also transmits control signals, for example but not limited to, a ready/busy signal (R/Bn) to the storage controller102. In some embodiments, each of CO signals may be a one-bit wide signal. In other embodiments, the control signals CO signals may have other bit-widths as desired.

The storage controller122issues a command code to perform a read operation, a command code to perform a write operation, or the like to the memory die108in response to a command from a host device. The storage controller122manages the memory space of the memory die108. As part of the read or write operation, the storage controller122issues various commands to perform for a respective operation and the memory die108and/or storage controller122transmit DIN/DOUT to complete the respective operation.

Storage controller122comprises I/O circuit534electrically connected to the I/O circuit522of the memory die108via a plurality of electrical contacts or terminals. The electrical contacts may comprise pads, pins, etc. for electrically connecting the memory die108to the storage controller122via a respective bus of the memory interface524. For example, the storage controller122includes a plurality of contacts502a-nelectrically connected to a plurality of contacts504a-nof the memory die108. The I/O circuit534transmits the CO signals and CLK signal to the memory die108over the various buses of the memory interface524via respective pins and transmits DQ signals (e.g., DIN data signals) over the data bus DQ of the memory interface524via respective pins. The I/O circuit522can transmit the R/Bn signal to the storage controller122over the DQ bus and the DQ signals (e.g., DOUT data signals) over the DQ bus via respective pins.

As illustrated inFIG.5, the memory die108includes I/O circuit522, a logic control circuit506, a status register508, an address register510, a command register512, a sequencer514, a ready/busy circuit516, a voltage generation circuit518, a data register520, CLK input circuit522, row decoder510, a sense blocks532, and column decoder512. The various components506-520may be included as part of the die controller, for example, as part of the control circuit506.

The I/O circuit522controls input and output of the DQ signals to and from the storage controller122. For example, the I/O circuit522comprises a transmitter (Tx) and/or receiver (Rx) circuit530configured to exchange DQ signals with a transmitter (Tx) and/or receiver (Rx) circuit530on the I/O circuit534of storage controller122. In the case of a write operation, Tx/Rx circuit530receives command codes and DIN from Tx/Rx circuit532. Tx/Rx circuit530also DIN to data register520, address codes to the address register510, and command codes to the command register512. DIN, command codes, and address codes are transmitted to the memory die104aas DQ signals encoded with a bit pattern for the DIN, command, or address. The Tx/Rx circuit530also can transmits status information STS received from the status register508, DOUT received from the data register520to be transmitted to the storage controller122. STS and DOUT are transmitted as DQ signals encoded with a bit pattern for the STS or DOUT. The I/O circuit522and the data register520are connected via an internal data bus528. For example, the internal data bus528includes a plurality internal I/O data lines (e.g.,100to107corresponding to 8-bit DQ signals such as DQ[0:7]). The number of internal I/O data lines is not limited to eight, but may be set to 16, 32, or any number of data lines.

The logic control circuit506receives, for example, the CO signals from the storage controller122via CO bus. Then, logic control circuit506controls the I/O circuit522and the sequencer514in accordance with a received signal. The status register508temporarily stores status information STS, for example, in a write operation, a read operation, and an erasing operation for data and notifies the storage controller122whether the operation normally ends.

The address register510temporarily stores the address code received from the storage controller122via the I/O circuit522. For example, the I/O circuit522may detect DQ signals and sample the DQ signals according to the CLK signal to obtain a bit pattern encoded thereon. The I/O circuit522may then decode the bit pattern to obtain the data, which in this example may be an address code. The address code is then temporarily stored in the address register510. Then, the address register510transmits a row address (row addr) to the row decoder510and transmits a column address (col addr) to the column decoder512.

The command register512temporarily stores the command code received from the storage controller122via the I/O circuit522and transmits the command code to the sequencer514. For example, the I/O circuit522may detect DQ signals and sample the DQ signals according to the CLK signal to obtain a bit pattern encoded thereon. The I/O circuit522may then decode the bit pattern to obtain the data, which in this example may be a command code. The command code is then temporarily stored in the command register512.

The sequencer514controls operation of the memory die108. For example, the sequencer514controls the status register508, the ready/busy circuit516, the voltage generation circuit518, the row decoder510, the sense blocks532, the data register520, the column decoder512, and the like according to a command code stored in the command register512to execute the write operation, the read operation, and the erasing operation according to the code.

The ready/busy circuit516transmits the R/Bn signal to the storage controller102according to an operation state of the sequencer514. For example, the R/Bn signal is transmitted to the storage controller122via the control bus526of the memory interface524.

The voltage generation circuit518receives a high supply voltage VDDQ and low supply voltage VSSQ (which may be ground or zero in some embodiments) and generates voltages necessary for a desired operation (e.g., a write operation, a read operation, or an erasing operation) according to control of the sequencer514. For example, voltage generation circuit518may generate a reference voltage Vref for distinguishing between logic states of a read or write operation. The voltage generation circuit518supplies the generated voltage, for example, to the memory structure506, the row decoder510, and the sense blocks532. The row decoder510and the sense blocks532apply a voltage supplied from the voltage generation circuit518to memory cells in the memory structure506.

The data register520includes a plurality of latch circuits. The latch circuits store the write data (WD) and the read data (RD). For example, in a write operation, the data register520temporarily stores the write data received from the I/O circuit522and transmits the write data to the sense blocks232. For example, in a read operation, the data register520temporarily stores the read data received from the sense blocks232and transmits the read data to the I/O circuit222.

The clock input circuit582receives the clock signal CLK via pin504c. The CLK signal may be two complementary clock signals (e.g., DQS and DQSB). The clock input circuit582receive a clock enable signal CKE from the logic control circuit506and provides a phase controlled internal clock signal LCLK. The phase controlled internal clock signal LCLK is supplied to the I/O circuit222and is used as a timing signal for sampling DIN/DOUT on the data bus as well as performing other functions of the memory die104a.

The I/O circuit522is supplied with high supply voltage VDDQ and low supply voltage VSSQ via respective pins. The supply voltages VDDQ and VSSQ may be used for the I/O circuit522so that power supply noise generated by the I/O circuit522does not propagate to the other circuit blocks of device memory die108.

FIG.6Ais an example illustration of a center tapped termination (CTT) logic circuit.FIG.6Bis an example I/O signal waveform650transmitted from the transmitting device to the a receiving device via the CTT logic circuit.

Referring toFIG.6A, the circuit600comprises a transmission driver610on a transmitting device602connected to a termination circuit620on a receiving device604. The transmission driver610in the transmitting device602drives an I/O pad612based on a transmission signal (ST) from an internal signal of the transmitter device602. The I/O pad612of the transmission driver610is connected to I/O pad622of receiving device604through a bus line630. A termination circuit620of the CTT logic is connected to the I/O pad622of the receiving device604for impedance matching so to reduce signal reflection. An input receiver (IREC)640(also referred to as a reception buffer) is provided in the receiving device604configured to compare the input signal SI received through the I/O pad622with a reference voltage Vref to provide a buffer signal BF to an internal circuit of the receiving device604.

In an example implementation, the transmitting device602may be the storage controller102with I/O circuit234comprising transmission driver610as an example Tx/Rx circuit532and the receiving device604may be the memory die104awith I/O circuit222comprising termination circuit620and input receiver640as an example Tx/Rx circuit530, for example, in a case of a write operation in which storage controller102is transmitting DIN data to memory die104a. Further, bus line630, I/O pad612, and I/O pad622may be implemented as a data bus line of data bus228, one of contacts502a, and one of contacts504a. That is, in a case of an 8-bit wide data bus228, there may be eight contacts502aand eight contacts504a. Each respective contact502ais connected to a respective contact504avia a data bus line of data bus228.FIG.6Adepicts one such configuration, where bus line630is an example of a single line of the data bus228, and I/O pads612and622are single electrical contact or pads.

In another example, the transmitting device602may be the memory die104awith I/O circuit222comprising transmission driver610as an example Tx/Rx circuit530and the receiving device604may be the storage controller102with I/O circuit234comprising transmission driver620and input receiver640as an example Tx/Rx circuit532, in a case of a read operation in which memory die104ais transmitting DOUT data to storage controller102. In this scenario, bus line630, I/O pad612, and I/O pad622may be implemented as a data bus line of data bus228, one of contacts504a, and one of contacts502a.

The transmission driver610may include a pull-up driver RPUconnected between a first power supply voltage VCCQ and the I/O pad612and a pull-down driver RPDconnected between the I/O pad612and a second power supply voltage VSSQ lower than the first power supply voltage VCCQ. The pull-up driver RPUmay include a p-channel metal oxide semiconductor (PMOS) transistor that is switched in response to the transmission signal ST. The pull-down driver Rpdmay include a n-channel metal oxide semiconductor (NMOS) transistor that is switched in response to the transmission signal ST. Each of pull-up driver RPUand pull-up driver RPUmay have a resistance Ronbetween the VCCQ and VSSQ, respectively, and the I/O pad612when each of the pull-up driver RPUand pull-up driver RPUis turned on based on the transmission signal ST.

The termination circuit620may include a first sub termination circuit connected between the first power supply voltage VCCQ and the I/O pad622and a second sub termination circuit connected between the I/O pad622and the second power supply voltage VSSQ. The first sub termination circuit may include a first termination resistor RTTand the second sub termination circuit may include a second termination resistor RTT.

In case of the termination circuit620, a high voltage level VOH and a low voltage level VOL of the input signal SI may be represented as waveform650shown inFIG.6B. The second power supply voltage VSSQ may be assumed to be a ground voltage (e.g., VSSQ=0) and the voltage drop along the transmission line630may be neglected. Thus, reference voltage Vref for the CTT scheme may be calculated as follows:

Thus, Vref is a fixed value at half of VCCQ, because the high voltage level VOH is fixed based on VCCQ applied to the first sub termination circuit.

The receiving device can distinguish between a logic high level and a logic low level of an encoding in the transmission signal ST by leveraging the comparison of the input signal SI with the reference voltage Vref at IREC640. For example, as shown inFIG.6B, a logic low level may be detected when the voltage level of the input signal SI is below the reference voltage Vref (e.g., at low voltage level VOL), while a logic high level may be detected when the voltage level on the input signal SI is above the reference voltage Vref (e.g., at high voltage level VOH). Due to the high voltage level VOH being fixed and the reference voltage Vref being fixed at half VCCQ, as described above, the receiving device604can distinguish between the logic high level and logic low level to accurately detect data on the bus line630.

The circuit700comprises a transmission driver710on a transmitting device702connected to a termination circuit720on a receiving device704. The transmission driver710in the transmitting device704drives an I/O pad712based on a transmission signal ST from an internal signal of the transmitter device702. The I/O pad712of the transmission driver710is connected to I/O pad722of receiving device704through a bus line730. A termination circuit720is connected to the I/O pad722of the receiving device704for impedance matching so to reduce signal reflection. A IREC740(also referred to as reception buffer740) is provided in the receiving device704configured to compare the input signal SI received through the I/O pad722with a reference voltage Vref to provide a buffer signal BF to an internal circuit of the receiving device704.

In an example implementation, the transmitting device702may be the storage controller102with I/O circuit234comprising transmission driver710as an example Tx/Rx circuit532and the receiving device702may be the memory die104awith I/O circuit222comprising termination circuit720and input receiver740as an example Tx/Rx circuit530, for example, in a case of a write operation in which storage controller102is transmitting DIN data to memory die104a. Further, bus line730, I/O pad712, and I/O pad722may be implemented as a data bus line of data bus228, one of contacts502a, and one of contacts504a.

In another example, the transmitting device702may be the memory die104awith I/O circuit222comprising transmission driver710as an example Tx/Rx circuit530and the receiving device704may be the storage controller102with I/O circuit234comprising termination circuit720and input receiver740as an example Tx/Rx circuit532, in a case of a read operation in which memory die104ais transmitting DOUT data to storage controller102. In this scenario, bus line730, I/O pad712, and I/O pad722may be implemented as a data bus line of data bus228, one of contacts504a, and one of contacts502a.

The transmission driver710may include a pull-up driver RPUconnected between a first power supply voltage VCCQ and the I/O pad712and a pull-down driver RPDconnected between the I/O pad712and a second power supply voltage VSSQ lower than the first power supply voltage VCCQ. The pull-up driver RPUmay include a NMOS transistor that is switched in response to the transmission signal ST. The pull-down driver RPDmay include a NMOS transistor that is switched in response to the transmission signal ST. Each of pull-up driver RPUand pull-up driver RPUmay have a resistance Ronbetween the VCCQ and VSSQ, respectively, and the I/O pad712when each of the pull-up driver RPUand pull-up driver RPUis turned on based on the transmission signal ST. The termination circuit720may include a termination resistor RTTconnected between the I/O pad722and the low power supply voltage VSSQ.

In case of the termination circuit720, the high voltage level VOH and the low voltage level VOL of the input signal SI may be represented as waveform750shown inFIG.7B. The low power supply voltage VSSQ may be assumed to be a ground voltage (e.g., VSSQ=0) and the voltage drop along the transmission line730may be neglected. Thus, the low voltage level VOL is equal to VSSQ and because the high voltage level VOH is not fixed, the reference voltage Vref is unknown. However, the LVST logic provides for low power consumption in the termination circuit720since the high voltage level VOH is not fixed to the high voltage level VCCQ. Thus, lower voltage levels may be utilized as the high voltage level (e.g., lower than VDDQ), which results in lower voltage swings and reduced power consumption along the bus line730and receiving device704. For example, the power consumption on bus line730can be reduced up to approximately 50% as compared to power consumption on bus line bus line630of the CTT logic. Yet to implement the circuit implementation700, the IREC740needs to be fed a reference voltage Vref that can be used to distinguish between different logic levels in the voltage swings. Accordingly, training receiving device704is needed to so that receiving device704can locate a reference voltage Vref that can be used by the IREC740in distinguishing between different logic levels on the input signal SI to decode a data pattern and latch incoming data correctly.

FIGS.8and9are schematic illustrations of conventional designs for PMOS and a combination PMOS and NMOS pull-up drivers. The conventional PMOS based pull-up driver is typically used for NV-DDR3 operation. The conventional PMOS based pull-up driver can also be used in NV-LPDDR4 operation. However, the conventional PMOS based pull-up driver suffers from a variety of fatal flaws when used in NV-LPDDR4 operation. For example, during operation in NV-LPDDR4, the PMOS based pull-up driver performance degrades due to an imbalance in output rise and fall in slew-rates as pull-up impedance is doubled compared to ODT impedance. This failure is amplified, and thus especially significant, when a higher load is applied. The conventional design of a combination PMOS and NMOS pull-up driver addresses the deficiencies of the PMOS based pull-up driver during NV-LPDDR4. However, the combination PMOS and NMOS pull-up driver results in an increase in area (e.g., footprint of the circuit), an increase in capacitance at the I/O pad612and an increase in power (both static power and dynamic power). The proposed driver allows the PMOS based-pull up driver to be used in NV-LPDDR4 without the need for the plurality of NMOS pull-up drivers. Thus, the proposed driver results in area savings and power savings while meeting the performance and output requirements of the ONFI specification.

Referring now toFIG.8, the PMOS based pull-up driver includes a plurality of PMOS transistors. The plurality of PMOS transistors includes a “N+2” number of PMOS transistors. For example, MPbase PMOS transistor, an MP0PMOS transistor, an MP1PMOS transistor and so on up to MP_N PMOS transistor. Each PMOS transistor includes a gate, source and drain. The source of each PMOS transistor is communicatively coupled the VCCQ. For example, the source of the MPbase PMOS transistor is communicatively coupled to the VCCQ bus. For example, the source of the MP0PMOS transistor is communicatively coupled to the VCCQ bus. For example, the source of the MP1 PMOS transistor is communicatively coupled to the VCCQ bus. For example, the source of the MP_N PMOS transistor is communicatively coupled to the VCCQ bus. In one embodiment, the drain of each PMOS transistor is communicatively coupled to resistor820. The resistor820is communicatively coupled to the I/O pad612. For example, the drain of MPbase PMOS transistor is communicatively coupled to resistor820. The drain of MP0PMOS transistor is communicatively coupled to resistor820. The drain of MP1 PMOS transistor is communicatively coupled to resistor820. The drain of MP_N PMOS transistor is communicatively coupled to resistor820.

When the conventional PMOS based pull-up driver of NV-DDR3 is used in NV-LPDDR4 mode, the performance degrades due to an imbalance in output rise and fall slew-rates as pull-up impedance is double compared to on-die termination (ODT) and pull-down impedance. Due to the imbalance in output rise and fall in slew-rates the output common mode falls significantly violating ONFI NAND requirements. For example, when the conventional PMOS based pull-up driver is used in NV-LPDDR4, the PMOS based pull-up driver will be having low current driving capability. For NV-LPDDR4 protocol, ZQ calibration is done at VOH level (e.g. VCCQ/3, VCCQ/2.5) and signal would transition from VOL (=0) to VOH for low to high transition and VOH to VOL(=0) for high to low transition. Pull-up would be used for low to high transition. For PMOS based Pull-up driver, due to nonlinearity, pull-impedance would be higher when it starts charging output from 0(VOL) and it gradually decreases to calibrated value when output signal reaches to VOH. Due to this and as pull-up impedance is double than ODT and pull-down impedance at VOH (calibration voltage) level, signal rising slew-rate is much lesser compared to signal fall slew-rate and imbalance in output rise and fall slew-rate increases as output load increases. Here, the I/O pad612may not reach the required VOH voltage levels at high speed. To boost slew rate if the pre-driver is strengthened and power is increased, even then if it reaches the required VOH voltage level, because of the imbalance in slew-rates output common mode falls and VREFQ will not be within specification.

FIG.9is a schematic illustration of a conventional combination PMOS/NMOS pull-up driver, according to one embodiment. The combination PMOS/NMOS pull-up driver (hereafter referred to as a combination pull-up driver) includes a plurality of PMOS transistors and NMOS transistors communicatively coupled to the I/O pad612. The plurality of PMOS transistors includes a (N+2) number of PMOS transistors. For example, MPbase PMOS transistor, MP0PMOS transistor, MP1 PMOS transistor, and MP_N PMOS transistor, etc. The plurality of NMOS transistors include a (N+2) number of NMOS transistors. For example, MPbase PMOS transistor, MN1PMOS transistor, MN2PMOS transistor and MP_N transistor, etc.

Each PMOS and NMOS transistor includes a gate, source and drain. The source of each PMOS transistor is communicatively coupled to the VCCQ. For example, the source of the MPbase PMOS transistor is communicatively coupled to the VCCQ bus. For example, the source of the MP0PMOS transistor is communicatively coupled to the VCCQ bus. For example, the source of the MP1PMOS transistor is communicatively coupled to the VCCQ bus. For example, the source of the MP_N PMOS transistor is communicatively coupled to the VCCQ bus. In one embodiment, the drain of each PMOS transistor is communicatively coupled to resistor820. The resistor820is communicatively coupled to the I/O pad612. For example, the drain of MPbase PMOS transistor is communicatively coupled to resistor820. The drain of MP0PMOS transistor is communicatively coupled to resistor820. The drain of MP1 PMOS transistor is communicatively coupled to resistor820. The drain of MP_N PMOS transistor is communicatively coupled to resistor820.

The drain of each NMOS transistor is communicatively coupled to the VCCQ. For example, the drain of MNbase NMOS transistor is communicatively coupled to the VCCQ bus. For example, the drain of the MN1NMOS transistor is communicatively coupled to the VCCQ bus. For example, the drain of the MN2NMOS transistor is communicatively coupled to the VCCQ bus. For example, the drain of the MN_N NMOS transistor is communicatively coupled to the VCCQ bus. The source of each NMOS transistor is communicatively coupled to the I/O pad612. For example, the source of the MNbase NMOS transistor is communicatively coupled to the I/O pad612. The source of the MN1NMOS transistor is communicatively coupled to the I/O pad612. The source of the MN2NMOS transistor is communicatively coupled to the I/O pad612. The source of the MN_N NMOS transistor is communicatively coupled to the I/O pad612.

To get back performance, the NMOS based pull-up driver is used in NV-LPDDR4 mode. Contrary to PMOS based pull-up, pull-up impedance would be much lower at VOL (=0) compared to calibrated pull-up impedance for NMOS based pull-up as VGS of NMOS is much higher when signal is low compared to VGS at calibration voltage (e.g. VCCQ/3, VCCQ/2.5). e.g., for VOH=VCCQ/3, NMOS based pull-up would be calibrated at VCCQ/3 and at that voltage, VGS of NMOS would be “VCCQ*2/3” but when signal is low, VGS of NMOS would be “VCCQ” which is ˜33% higher compared to calibrated impedance which results in much lower pull-up impedance when output signal start rising thus output signal rise slew-rate increases significantly. Accordingly, I/O pad612will reach the required VOH level without violating the VREFQ specification requirements. However, the VGS of the NMOS at the calibration point will be ⅔ of the VCCQ, thus requiring a greater number of NMOS transistors and subsequent data-path. The additional NMOS transistors significantly increase area and power.

FIG.10Aillustrates a signal path to the PAD, according to one embodiment. At node B, the input signal is delayed by a second amount Td. The delay Td alters the pulse width of the input voltage signal to have an increased pulse width. The increased pulse width of the voltage signal can be observed at node C. For example, delay block1092applies to a delay Td to the input signal.

In TM5 mode, the skew gen block increases the pulse width of the input voltage signal and transmits voltage signal with increased pulse width to the pull-up driver1098and pull-down driver1099via connections1008and1009. This increased pulse width at the driver allows the pull-up driver to be on for higher duration, thus allowing the PAD612to reach the required VOH level.

The signal path includes an OR logic gate1093, a delay block1092, a MUX1070, a pull-up predriver1098and a pull-down predriver1099. The amount of delay created by the delay block1092affects the width of the pulse (e.g., the duration of the pulse).

In a configuration, the pulse width can be determined/altered using the following equations:

Td represents the amount of delay of the delay block1092. TPH refers to the pulse high pulse width of the input data signal, and TPL refers to the pulse low pulse width of the input data signal. TPHskew refers to the increased pulse width of the pulse high input data signal. TPLskew refers to the decreased pulse width of the pulse low input data signal. Equation 1 can be used to determine the pulse width. Using this equation, the pulse duration (e.g., the width of the pulse) can be determined based on the delay of the delay block1092. In addition, in POD signaling, TPHskew refers to the decreased pulse width of the pulse high input data signal and TPLskew refers to the increased pulse width of the pulse low input data signal.

FIG.10Bis an example illustration of a skew gen circuit1001, according to one embodiment. The skew gen circuit1001alters the pulse width of the data high signal. In one embodiment, a first data high signal having a first pulse duration is applied as an input to the skew gen circuit1001. The skew gen circuit1001outputs the first data high signal as a “skewed” out data high signal having an increased pulse duration. The increased pulse duration can be observed as an increased pulse width. For purposes of the disclosure herein “skewed” refers to an altered pulse width of a data high signal. The altered data high signal is any input signal that undergoes an observable change to its waveform to generate an output waveform that includes different waveform features than the input signal. In one embodiment, the different waveform features include amplitude, duration (e.g., width) and phase of the waveform. For example, the pulse width of the input data high signal is less than the pulse width of the output data high signal coming from the skew-gen circuit1001. Altering the voltage waveform generates additional time for the driver output signals to reach rail to rail.

The plurality of skew-gen circuit components are configured to increase the pulse width of the I/O data high signal. Each individual component of the plurality of skew-gen circuit components is configured to alter the data high signal. For example, the plurality of inverters comprising three inverters coupled in series and the inverter coupled to the second input of the AND gate are configured to skew the data high signal by increasing the pulse width. The skewed data high signal is transmitted to the pull up predriver and the pull down predriver to perform I/O functions.

The skew gen circuit1001, in one implementation, may include a plurality of inverters1010A-D,1050, an AND gate and a MUX1070. The plurality of inverters1010A-D are coupled to a two input AND gate1030. In one implementation, the plurality of inverters1010include a first inverter1010A, a second inverter1010B, third inverter1010C and a fourth inverter1010D. In one implementation, the first inverter1010A is coupled to a first input of the AND gate1030and the second inverter1010B, third inverter1010C and fourth inverter1010D are coupled to the second input of the AND gate1030. In one embodiment, the second inverter1010B, third inverter1010C and fourth inverter1010D are coupled in series. For example, as seen inFIG.10, the output of the second inverter1010B is coupled to the input of the third inverter1010C. The output of the third inverter1010C is coupled to the input of the fourth inverter1010D. The output of the fourth inverter1010D is coupled to the second input of the AND gate1030.

Inverter1050is communicatively coupled to both the AND gate1030and the MUX1070. The output of the AND gate1030is communicatively coupled to an input of inverter1050. The output the inverter1050is communicatively coupled to the first input of the MUX1070. The MUX1070includes the first input, a second input, a mode input, and an output. In one configuration, the two-input AND logic gate1030and inverter1050are replaced with a two-input NAND logic gate1031. The output of the two-input NAND logic gate1031is coupled to the input of MUX1070.

During NV-DDR3 operation, the skew gen block will not disturb the voltage wave except imparting a slight delay to the data high signal transmitted to the I/O PAD612. NV-DDR3 operation does not require the skew gen circuit1000, thus using the mode input, the skew gen circuit1000can be selectively used depending on whether the I/O is in NV-DDR3 operation or NV-LPDDR4 operation. For example, during NV-DDR3 operation (e.g., “TM4 mode”), the skew gen circuit1000is inoperable. During NV-LPDDR4 (e.g., “TM5 mode”), the skew gen circuit1000is used to skew the pulse width of the data high signal.

Inverter1010A and inverter1010B both have the same input. The plurality of inverters1010B,1010C and1010D each alter the data high signal to increase the pulse width. As the data high signal is passed through each inverter of the plurality of inverters, the pulse width of the data high signal is increased. Thus, the amount of inverters can be increased or decreased to adjust the delay.

The input data signal is transmitted along path1006A to inverter1010A and along path1007A to inverter1010B. The input data signal is inverted at inverter1010A and inverter1010B. The inverted data signal generated by inverter1010B is further passed through inverters1010C and1010D where it is inverted two more times. Although three inverters1010B,1010C and1010D are shown, any number of inverters can be used. The amount of inverters coupled in series increases the pulse width of the data high signal. Each data signal generated by paths1006and1007is applied as a respective input to the two input AND gate1030. For example, the data signal generated by path1006is applied as a first input to the AND gate1030and the data signal generated by path1007is applied as a second input to the AND gate1030. The data signal is delayed by path1006and by path1007. The data signal is transmitted to the NAND logic gate1031so that the data signal is skewed so that the data high signal pulse width is increased and data low signal pulse width is reduced. The skewed data signal is applied as an input to MUX1070.

FIG.10Cis a timing diagram of an input data signal applied to the skew-gen circuit, according to one embodiment. The timing diagram includes a plurality of example data high signals. Each data high signal corresponds to a data high signal observed at a node of the plurality of nodes of the skew-gen circuit1000. At node IN, an input data high signal is applied to the skew-gen circuit1000. The input data high signal includes a duty cycle having a first pulse width. For example, the data high signal includes a pulse duration of about 50% of the duty cycle (e.g., the data high signal includes a pulse width of about 50% of the duty cycle).

The data signal observed at nodesN2andN1, includes an altered pulse width compared to the input data high pulse width IN. As seen by the data signals observed at nodes N1, N2andN2, each inversion of the voltage waveform slightly alters the data high pulse. For example, the data signal observed at nodeN1includes a first altered data signal, and the data signal observed at nodeN2includes a second altered data signal. The data signals observed at nodesN1andN2are applied to the NAND gate1031as inputs. The NAND gate1031returns the data\signal observed at nodeN3. The data signal observed at nodeN3includes a data high pulse width that is greater than the data high pulse width of the input data signal. The altered pulse duration of the data signal inFIG.10Bis not limited to a drastic change in pulse duration (e.g., an input data signal having a pulse duration of 50% percent and an altered data signal having a pulse duration of 80%), and can be an altered pulse duration of more or less than a percent. For example, the input data high signal IN includes a pulse duration that is 48% of the duty cycle, and the data high signal observed atN3includes a pulse duration that is 49% percent of the duty cycle.

FIG.10Dis an example illustration of an alternative skew-gen circuit1004, according to one embodiment. The alternative skew gen circuit1000can be used to alter the data signal transmitted to pseudo open drain (POD) drivers. POD drivers have a strong pull-up strength and a weaker pull-down strength. To generate the strong pull-down strength, the POD drivers require a longer ON time for pull-down device(s). Thus, POD drivers require a duty cycle with a larger duration (e.g., width) of data low signal and a shorter duration of data high signal. By inverting the data signal observed at nodeN3ofFIGS.10A and10B, the alternative skew-gen circuit1004can generate a data signal with a longer data low duration and shorter data high duration (e.g., a narrow data high pulse).

In one configuration, the alternative skew-gen circuit1004includes a two input AND logic gate1030instead of the two input NAND logic gate1031. The output of either the two input AND logic gate1030or two input NAND logic gate1031is coupled to the input of MUX1070.

FIG.11is an example of a block diagram1100of a first conventional data path, according to one embodiment. The block diagram1100includes a first conventional datapath1133, a second conventional datapath1150and a skew-gen datapath1170. Each datapath1133,1150,1170includes a plurality of circuit elements. For example, the first conventional data path1133includes a PU predriver1135, a PD predriver1136, a PMOS PU800and a NMOS PD1138. The second conventional datapath1150includes a PU predriver1135, a PMOS PU800, a LVSTL PU predriver1155, a NMOS PU950, a PD predriver1156and a NMOS PD1138. The skew-gen datapath1170includes the skew-gen circuit1000, the PU predriver1135, the PMOS PU800, the PD Predriver1136and the NMOS PD1138. Each circuit element in the plurality of circuit elements includes a respective input and output configured to receive and send data along a bus. Predriver1135, predriver1136and LVSTL PU predriver1155can be configured to provide the necessary integrated charge pump, gate drive and protection capabilities to drive field effect transistor (FET) switches. The PMOS PU driver800and NMOS PU driver950are configured to alter the signal to logic level high. The NMOS PD driver1138is configured to alter the signal to logic level low.

The first conventional datapath1133includes a pull-up (PU) Predriver1135, the PMOS based PU driver800, a pull-down (PD) Predriver1136and a NMOS PD circuit1138. An I/O bus118is coupled to an input of the PU predriver1135and an input of the PD predriver1136. The output of the PU predriver1135is coupled to the input of the PMOS based PU driver800. The output of the PD predriver1136is coupled to the input of the NMOS based PD driver1138.

The second conventional datapath1150includes the PU Predriver1135, the PMOS based PU driver800, a LVSTL PU Predriver1155, the NMOS PU driver950, the PD Predriver1156and the NMOS PD driver1138. The data I/O datapath118is coupled to the input of the PU predriver1135, the input of the LVSTL PU predriver1155and the input of the PD predriver1156. The output of the PU predriver1135is coupled to the input of the PMOS PU driver800. The output of the LVSTL PU predriver1155is coupled to the input of the NMOS PU driver950. The output of the PD predriver1156is coupled to the input of the NMOS PD driver1138. The PU predriver is communicatively coupled to the PMOS based PU driver800.

The proposed datapath1170includes a skew gen circuit1000, a PU Predriver1135, a PD Predriver1136a PMOS PU800and a NMOS PD1138. The PU predriver is communicatively coupled to the PMOS based PU driver800. The PD predriver is communicatively coupled to the NMOS PD1138.

FIGS.12A-12Cillustrate eye diagrams at I/O pat612for the PMOS based pull-up driver800, the combination pull-up driver900and the proposed driver with skew gen circuit1000.FIG.12Aillustrates an eye diagram1210at I/O pad612for the PMOS based pull-up driver800.FIG.12Billustrates an eye diagram1230at I/O pad612for the combination pull-up driver900.FIG.12Cillustrates an eye diagram1250at I/O pad612for the proposed driver with a skew gen circuit1000.

Each eye diagram1210,1230and1250is bounded by a vertical and horizontal axis. The vertical axis includes the v(pad). The horizontal axis includes a UI(unit interval). All of the measurements (jitter, slew rate, etc.,) are measured with respect to the VREFQ level. In one embodiment, measurements are conducted at a minimum VREFQ value of 160 mV to meet ONFI specifications. Measurements of voltage levels other than VREFQ have resulted in performance degradation.

As seen inFIG.12Afor the conventional PMOS based pull-up driver800, the reference voltage (VREF) is between about 50 mV and 100 mV. As seen inFIG.12Bfor the conventional combination PMOS/NMOS pull-up driver900, the VREFQ is between about 150 mV and 200 mV. As seen inFIG.12Cfor the proposed driver with skew gen circuit1000, the VREFQ is between about 150 mV and 200 mV. ONFI specifications require about 160 mV VREFQ values for normal NAND operation. As seen inFIG.12A, for the PMOS pull-up-driver800, a VREFQ between 50 mV and 100 mV is insufficient to meet the ONFI specification requirements. As seen inFIG.12Bfor the conventional combination PMOS/NMOS pull-up driver900, the VREFQ signal of about 170 mV is within ONFI specification requirements, however, the area of the combination PMOS/NMOS pull-up driver900circuit is very large as it requires a large amount of hardware which requires a large amount of power and padcap. The conventional combination PMOS/NMOS pull-up driver900circuit requires about 32 percent more area compared to the conventional PMOS based pull-up driver800circuit. The proposed driver with skew-gen circuit1000occupies only about 3 percent more area than the conventional PMOS based pull-up driver800circuit.

The proposed driver with skew-gen circuit1000incorporates the smaller footprint of the conventional PMOS based pull-up driver800with the VREFQ values of the conventional combination PMOS/NMOS pull-up driver900. Thus, the proposed driver with skew-gen circuit1000generates the VREFQ required to meet ONFI specifications while minimizing the footprint.

Table 1 illustrates the minimum and maximum VREFQ level, jitter, duty-cycle distortion (DCD), padcap, supply leakage and pad-leakage with drive strength of about 75Ω pull-up, about 37.5Ω pull-down, about 37.5Ω on-die termination (ODT) and about 8 pf load at schematic level for SMIC40 technology among each data path. As seen in table 1, in the conventional PMOS based pull-up driver900, the minimum VREFQ ONFI specification requirements are violated. Moreover, the ABS jitter is very high (e.g., about 325 ps at 160 mV).

The proposed driver with skew-gen circuit1000further offers static and dynamic power reduction in both read operations and write operation. The decreased footprint of the proposed driver with skew-gen circuit1000includes a circuit footprint that is smaller than the combination PMOS/NMOS pull-up driver900, since the proposed driver does not require the NMOS leg of the PMOS/NMOS pull-up driver900.

FIG.13is an illustration of an example data high signal at the I/O pad produced by a conventional PMOS based pull-up driver, and the proposed driver with skew-gen circuit900. with and without the skew-gen circuit for a PMOS based pull-up driver, according to one embodiment. The first data high signal1330is generated by the proposed driver with skew-gen circuit900. The second data high signal1350is generated by the pull-up based PMOS driver800.

The first data high signal1330includes a first pulse generated over a first duration (e.g., charging time1365). The first waveform1330includes a first pulse width1365. The second voltage waveform1350includes a second pulse generated over a second duration (e.g., charging time1367). The second voltage waveform1350includes a second pulse width1367. The first data high signal1330is observed at the I/O pad612with the skew-gen circuit1000applied to the first conventional datapath1130(e.g., the skew-gen datapath1170). The second data high signal1350is observed at the I/O pad612without the skew-gen circuit1000(e.g., the first conventional datapath1130). The skew-gen circuit1000is able to “skew” the data high signal to increase the pulse width of the input data high signal. For the purposes of the disclosure herein, the waveform is “skewed” to increase the pulse width.

As seen inFIG.13, the first data high signal and second data high signal include fast rise times (e.g., a rise time of less than about 5 ns) and fast fall times (a fall time of less than about 5 ns). The first data high signal includes a pulse width of about 49.9% of the duty cycle. The second data high signal includes pulse width of about 48.1% of the duty cycle.

Increasing the pulse duration (e.g., increasing the pulse width) increases the ON time of pull-up devices and decreases the ON time of pull-down devices. In one embodiment, increasing the pulse duration increases the ON time of pull-up predriver1135and decreases the ON time of pull-down predriver1136. By increasing the pulse duration, the skew-gen circuit1000can alter/adjust the amount of time that pull-up device and pull-down devices are ON.

I/O operations in NV-LPDDR4 operating mode require an unterminated mode for command and address operations. If the skew-gen circuit1001is used in unterminated mode the duty cycle degrades. To avoid degrading the duty cycle, the skew-gen circuit1001is bypassed. If the I/O operation is configured to operate in high-speed data transfer without termination and run the I/O operation at low-speed, then there is an observable duty cycle difference in the voltage waveform. For example, in one embodiment, if the I/O operation is run at a low-speed, a duty cycle difference of almost 1.8% (180pat 100 MHZ) can be observed.

FIG.14is an illustration of a first graph and second graph comparing duty cycle distortion (dcd) under load with and without a skew-gen circuit1000for PMOS based pull-up drivers in terminated case at high speed. The illustration includes a first graph1404charting dcd under load with a skew-gen circuit1000and a second graph1406charting dcd under load without a skew-gen circuit1000.

As the load is increased from 0p to 20p, the duty cycle of the waveform generated by the PMOS based pull-up driver800differs (e.g., is distorted) from the duty cycle of the waveform generated by the proposed driver with skew-gen circuit1000. For example, in one embodiment, the duty cycle of the waveform generated by the PMOS based pull-up driver800differs by about 8% from the duty cycle of the proposed driver with skew-gen circuit1000. As seen inFIG.14, the duty cycle of PMOS based pull-up driver800measured at VCCQ/6 has a minimum value of 33.8 at 20p and a maximum value of 41.4 at 20p. In comparison, the duty cycle of the proposed driver with skew-gen circuit1000measured at VCCQ/6 has a minimum value of 47.2 at 20p and a maximum value of 50.1 at 20p.

The processes and algorithms may be implemented partially or wholly in application-specific circuitry. The various features and processes described above may be used independently of one another, or may be combined in various ways. Different combinations and sub-combinations are intended to fall within the scope of this disclosure, and certain method or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate, or may be performed in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed example embodiments.

As used herein, a circuit might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAS, PALs, CPLDs, FPGAs, logical components, software routines or other mechanisms might be implemented to make up a circuit. In implementation, the various circuits described herein might be implemented as discrete circuits or the functions and features described can be shared in part or in total among one or more circuits. Even though various features or elements of functionality may be individually described or claimed as separate circuits, these features and functionality can be shared among one or more common circuits, and such description shall not require or imply that separate circuits are required to implement such features or functionality.

It is intended that the foregoing be understood as an illustration of selected forms that the invention can take and not as a definition of the invention. Finally, it should be noted that any aspect of any of the preferred embodiments described herein can be used alone or in combination with one another.