Deinterleaver for a communication device

A deinterleaver for a wireless communication device is provided that is simple and inexpensive to implement. In particular, a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme is provided, the deinterleaver comprising preprocessing means for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator for the at least one memory, the generator being adapted to determine the addresses in the at least one memory that pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.

TECHNICAL FIELD OF THE INVENTION

The invention relates to a communication device, and in particular relates to a deinterleaver for a communication device.

BACKGROUND OF THE INVENTION

Interleaving techniques are commonly used in communication systems to protect transmissions against burst errors. Burst errors result in a number of consecutive bits being received erroneously, with the rest of the transmission being received successfully.

Data correction bits are derived for the data prior to transmission, which are used by the receiver to detect whether the data has been received successfully, and whether erroneously received bits can be corrected. Only a certain number of erroneous bits can be corrected in each symbol to be transmitted. Therefore, interleaving is used to spread the bits for each symbol across the transmission. Thus, if a burst error occurs, only a small number of bits from each symbol are affected, so the receiver will be able to correct the received symbols using the data correction bits.

In many established standards, for example wireless communication standards, block interleaving is used, as it is easy and straightforward to implement. However, as data rates and distances between nodes increase, nested or concatenated interleaving schemes are becoming more important. The direct mapping of deinterleavers for such advanced interleaving schemes to hardware is usually suboptimal, so different optimization techniques can be used to save silicon area and reduce power consumption.

The “MultiBand OFDM Physical Layer Specification” Release 1.0 from the MultiBand OFDM Alliance proposes a three-stage interleaving scheme. In the first stage, symbol interleaving is used which permutes the bits across a number of consecutive OFDM symbols (usually six) to exploit frequency diversity within a band group. In the second stage, intra-tone interleaving is used which permutes the bits across the data sub-carriers (tones) within an OFDM symbol to exploit frequency diversity across sub-carriers. In the third stage, intra-symbol cyclic shifts are used which cyclically shift the bits in successive OFDM symbols by deterministic amounts.

FIG. 1shows a block diagram of an interleaver in accordance with the above scheme. The interleaver2comprises a symbol interleaving unit4, a tone interleaving unit6and a cyclic shift unit8connected in series. The symbol interleaving unit4receives input bits denoted {U(i)}, operates on the bits and outputs bits denoted {S(i)}. The tone interleaving unit6receives the bits denoted {S(i)}, operates on the bits and outputs bits denoted {V(i)}. The cyclic shift unit8receives the bits denoted {V(i)}, operates on the bits and outputs bits denoted {B(i)}.

The symbol interleaving operation performed by symbol interleaving unit4comprises dividing the coded bits into blocks of 6NCBPScoded bits, where NCBPSis the number of coded bits per symbol, and therefore 6NCBPScorresponds to six OFDM symbols. Each group of coded bits is then permuted using a block interleaver of size 6NCBPSby 6/NTDS, where NTDSis the time spreading factor. The sequences {U(i)} and {S(i)}, where i=0, . . . , NCBP6S−1 and NCBP6Sis the number of coded bits in six symbols, represent the input and output bits of the symbol interleaving unit4respectively. The input-output relationship of this unit is given by the equation

S⁡(i)=U⁢{Floor⁡(iNCBPS)+6NTDS⁢Mod⁡(i,NCBPS)},(1)
where Floor(x) is a function which returns the largest integer value less than or equal to its argument value, and Mod(x,y) is the modulus operator which returns the non-negative integer remainder when x is divided by y.

The output bits of the symbol interleaving unit4, which are grouped together into blocks of NCBP6Sbits, are permuted together using a regular block interleaver of size NTint×10, where NTint=NCBPS/10. The sequences {S(i)} and {V(i)}, where i=0, . . . , NCBP6S−1, represent the input and output bits of the tone block interleaver unit6respectively. The input-output relationship of this unit is given by the equation

The output of the tone interleaving unit6is passed through intra-symbol cyclic shift unit8. The sequences {V(i)} and {B(i)}, where i=0, . . . , NCBP6S−1, represent the input and output bits of the cyclic shift unit8respectively. The output of the cyclic shift unit8is given by the following equation
B(i)=V[m(i)×NCBPS+mod(i+m(i)×Ncyc,NCBPS)]  (3)
where m(i)=Floor (i/NCBPS) and i=0, . . . , NCBP6S−1.

US 2005/0152327 discloses an interleaver for a multiband OFDM transceiver of an ultra wideband personal access network in accordance with the above three-stage interleaving scheme. This document also describes a deinterleaver which is a concatenation of three blocks, a cyclic de-shift unit, a tone-deinterleaving unit and a symbol deinterleaving unit, which is costly in terms of silicon area and is not scalable.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a deinterleaver for a wireless communication device that is simple and inexpensive to implement.

In accordance with a first aspect of the invention, there is provided a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme, the deinterleaver comprising preprocessing means for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator for the at least one memory, the generator being adapted to determine the addresses in the at least one memory that pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.

In accordance with a second aspect of the invention, there is provided a device for use in an ultra-wideband system comprising a deinterleaver as described above.

In accordance with a third aspect of the invention, there is provided a communication device for use in receiving a stream of data bits representing a plurality of symbols, the device comprising a deinterleaver as described above.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although the invention will be described with reference to an ultra-wideband network in accordance with the “MultiBand OFDM Physical Layer Specification” Release 1.0 from the MultiBand OFDM Alliance mentioned above, it will be appreciated that the invention is applicable to other communication networks in which multi-level interleaving is used.

In the following description of the invention, it is assumed that data to be transmitted has been interleaved using the three-stage interleaving scheme described above with reference toFIG. 1and Equations (1), (2) and (3), with the data being interleaved over six symbols, or three symbols (with the above equations being modified accordingly).

In the exemplary network, there are nine possible data rates that can be used: 39.4 Mb/s, 53.3 Mb/s, 80 Mb/s, 106.7 Mb/s, 160 Mb/s, 200 Mb/s, 320 Mb/s, 400 Mb/s and 480 Mb/s. The data rate 39.4 Mb/s is just used for the header. The parameters NTDS, NTint, Ncycand NCBPSused in the interleaving scheme described above all depend on the data rate being used at that time.FIG. 2is a table showing exemplary values for the parameters.

It has been recognized that the order in which symbol data bits are output from an interleaver can be classified into three main types based on the data rate and other parameters used by the interleaver to interleave the data stream. Thus, in accordance with the invention, a new parameter deintv_type is defined, and its value is based on the data rate used to transmit the data stream. The parameter deintv_type has a value of 1 when the data rate is 39.4 Mb/s, 53.3 Mb/s and 80 Mb/s, a value of 2 when the data rate is 106.7 Mb/s, 160 Mb/s and 200 Mb/s, and a value of 3 when the data rate is 320 Mb/s, 400 Mb/s and 480 Mb/s. The values of deintv_type are shown inFIG. 2.

The number of symbols used in the interleaving at the transmitter is denoted M and has the value M=0, . . . , 2 for data rates less than 320 Mb/s and M=0, . . . , 5 for data rates greater than 200 Mb/s (the range of values for M are also shown in the table ofFIG. 2). Assuming that the input data to the deinterleaver architecture is written in a continuous way, the soft bits from the Mthsymbol will be written into addresses N*M to N*(M+1)−1, where N=NCBPS.

FIGS. 3(a),3(b),3(c),4(a),4(b) and4(c) show the natural order in which interleaved symbol bits are received at a deinterleaver for different values of deintv_type. Specifically,FIGS. 3(a),3(b) and3(c) show the ordering of data bits and how they are virtually stored in memory at the deinterleaver for deintv_type=1, 2 and 3 respectively. The mthbit of the Mthsymbol is denoted symM,m.FIGS. 4(a),4(b) and4(c) show the ordering of data bits in the virtual memory addresses.

In a preferred embodiment, two data bits can be stored in a single physical memory location, with the virtual address being mapped to a physical address by dividing by

It can be seen fromFIGS. 3(a),3(b) and3(c) that there are three patterns in the output addresses.

(i) The first pattern is that the data from each symbol is output in a round robin way. For example, the output will be sym0,m, sym1,m, sym2,m, sym0,m+1, sym1,m+1, sym2,m+1, etc. This is due to the symbol-interleaving unit4in the transmitter.

(ii) If two consecutive output addresses from the same symbol are grouped together starting from the first output address, it can be seen that for most of the groups, the address gap is 10 for data rates of 39.4 Mb/s, 53.3 Mb/s and 80 Mb/s and 20 for data rates greater than 80 Mb/s. For example, the address gap between sym0,0and sym0,1inFIG. 3(a) is 10. This is due to the intra-symbol tone-interleaving block6in the transmitter.

(iii) The pattern described in (ii) may occasionally be broken, but, in these cases, another pattern is available. Here, two consecutive samples have index of m, (m+gap)−M*N. This is shown inFIG. 3(b) where the addresses of two consecutive data bits are 588 (sym2,6) and 408 (sym2,7). This is due to the cyclic shift unit8in the transmitter.

As a result of the above observations, a deinterleaver10is presented inFIG. 5. The deinterleaver10comprises an intra-symbol preprocessing unit12, which preprocesses the incoming interleaved data stream by reordering the data stream to the pattern in paragraph (ii). The intra-symbol preprocessing unit12has an output to a demultiplexer14, which selectively outputs the preprocessed data stream to a first memory16or a second memory18. In a preferred embodiment, the first and second memories16,18may be dual port random access memories. A read/write address generator20determines the locations in the first and second memories16,18to which data is to be written to or read from. A multiplexer22is connected to the output of the first and second memories16,18and selectively passes the output of one of the memories16,18to an inter-symbol post-processing unit24. The inter-symbol post-processing unit24reorders the data received from the respective memory16or18selected by the multiplexer22to the pattern inFIG. 3(a) orFIG. 3(c). This architecture allows symbol and bit deinterleaving to be carried out at the same time.

The deinterleaver10preferably comprises control means that determines the value of deintv_type for the incoming transmission from the indication of the data rate in the header of the packet. In some embodiments, this header is a PLCP header.

At any time, one of the memories16or18is responsible for writing soft bits received in the incoming data stream, and the other is responsible for reading out soft bits stored therein. The memories16,18switch responsibilities after 6 OFDM symbol periods. In a preferred embodiment where each memory location stores two data bits, the memories16,18each have 3*NCBPSmemory locations, one location for each pair of bits in six symbols.

FIG. 6shows a block diagram of an intra-symbol preprocessing unit12in accordance with the invention. The unit12comprises three register arrays, a first main register array26, a second main register array28and a special register array30. The first and second main register arrays26,28have twenty register locations, labeled R0to R19. The special register array30has ten register locations, labeled R0to R9. The preprocessing unit12further comprises a demultiplexer32for receiving the data stream at the input of the unit12and selectively outputting the data stream to one of the register arrays26,28or30. The unit12also comprises a multiplexer34for outputting data from a selected register array26,28and30.

The intra-symbol preprocessing unit12has three different operating modes, one for each of the possible values for deintv_type. Due to frequency domain de-spreading, two soft data bits will be input to the preprocessing unit12each clock cycle when deintv_type=1. As the deinterleaver is a parallel design, four soft bits will be input to the preprocessing unit12each clock cycle when deintv_type=2 or 3.

FIGS. 7(a) to7(g) illustrate the operation of the preprocessing unit12when deintv_type=1. When deintv_type=1, only the first main register array26is used to process the incoming data stream. Thus the demultiplexer32is controlled to direct the incoming data stream to the first main register array26, and the multiplexer34is controlled to select the first main register array26for the output of the preprocessing unit12. The second main register array28and the special register array30are not used when deintv_type=1.

As mentioned above, the intra-symbol preprocessing unit12processes the incoming data stream and outputs the data bits in accordance with the pattern described in paragraph (ii) above. That is, the unit12groups the data stream into pairs of bits whose indices are 10 apart.

Each ofFIGS. 7(a)-(g) show the state of the register26at the end of a single clock cycle. Illustrated above the register26are a pair of data bits dxdx+1which will be received in the next clock cycle. The pair of data bits dydy+10illustrated below the register26are the data bits output from the register26during the clock cycle represented by that Fig.

FIG. 7(a) shows that the first ten data bits, denoted d0to d9, have been stored in locations R0to R9respectively in the register26. In the next clock cycle, data bits d10and d11will be received. It will be noted that register locations R10to R19are not used when deintv_type=1.

The operation of the register26follows a set pattern, with the pattern repeating every twenty data bits received, or, in other words, every ten clock cycles.

In each of the first five clock cycles of the pattern, when a new pair of data bits are received at the register26, a first one of the pair of data bits is read straight out of the register along with a data bit previously stored in the register26. This data bit will have an index that is ten less than the first data bit in the incoming pair. The other data bit in the pair is read into a vacant register location in the register26.

So, as shown inFIG. 7(b), the incoming data bit d10is read straight out of the register26with data bit d0, which was stored in register location R0. Data bit d1in register location R1is moved to register location R0, and incoming data bit d11is stored in register location R1. Alternatively (but not illustrated), data bit d1may remain in register location R1, and incoming data bit d11can be stored in register location R0. In either case, a pair of data bits whose indices are 10 apart are output from the register26to one of the first or second memories16,18, via the multiplexer34and demultiplexer14. In the register26, data bits d1and d11are now stored in adjacent register locations.

InFIG. 7(c), the data bits d12d13are received at the register26. Data bit d12is read straight out of the register26with data bit d2, which was stored in register location R2. Data bit d3moves to register location R2, and the incoming data bit d13is stored in the adjacent register location R3.

As shown inFIG. 7(d), after the first five cycles of the pattern, each consecutive pair of register locations has a respective pair of data bits stored therein, with the data bits having indices that are 10 apart. Thus, register locations R6and R7have data bits d7and d17stored therein, and so on.

In the last five clock cycles of the pattern, pairs of data bits stored in consecutive register locations are read out of the register26, and both of the incoming data bits are stored in the vacated register locations.

Thus, inFIG. 7(e), the data bits d1and d11in consecutive register locations R0and R1respectively are read out of the register26to one of the first or second RAMs16,18, and the incoming pair of data bits d20and d21are stored in the now-vacant register locations R0and R1. This process continues as shown inFIG. 7(f).

After the tenth clock cycle of the pattern, the state of the register26will be as shown inFIG. 7(g). Thus, consecutive data bits d20to d29have been stored in respective register locations R0to R9, and each of data bits d0to d9have been read out of the register26with a corresponding data bit that has an index that is 10 higher. It can be seen that the state of the register26inFIG. 7(g) corresponds to the state of the register26inFIG. 7(a). Thus, the pattern of ten clock cycles repeats for the remainder of the incoming data stream.

FIGS. 8(a) to8(f) illustrate the operation of the preprocessing unit12when deintv_type=2. As when deintv_type=1, only the first main register array26is used to process the incoming data stream. The second main register array28and the special register array30are not used when deintv_type=2.

As mentioned above, the intra-symbol preprocessing unit12processes the incoming data stream and outputs the data bits in accordance with the pattern described in paragraph (ii) above. Thus, the unit12groups the data stream into pairs of bits whose indices are 20 apart.

In order to reduce the number of figures required to illustrate the operation of the preprocessing unit12when deintv_type=2, each ofFIGS. 8(a)-(f) show the state of the register26at the end of a clock cycle. As the deinterleaver10is a parallel design (which allows the clock speed to be decreased, for example from 528 MHz to 264 MHz), four soft data bits will be input to the preprocessing unit12each clock cycle, and illustrated above the register26are two pairs of data bits dxdx+1dx+2dx+3which will be received during the next clock cycle. The two pairs of data bits dydy+20dy+2dy+22illustrated below the register26are the data bits output from the register26during the clock cycle represented by that Fig.

FIG. 8(a) shows that the first twenty data bits, denoted d0to d19, have been stored in locations R0to R19respectively in the register26. In the next clock cycle, data bits d20, d21, d22and d23will be received.

As when deintv_type=1, the operation of the register26follows a set pattern, with the pattern repeating every forty data bits received, or, in other words, every ten clock cycles.

In each of the first five clock cycles of the pattern, when a new quartet of data bits are received at the register26, the first and third ones of the quartet of data bits are read straight out of the register along with two data bits previously stored in the register26. These data bits will have an index that is twenty less than the first and third data bits in the incoming quartet respectively. The other data bits in the quartet are read into vacant register locations in the register26.

As shown inFIG. 8(b), the incoming data bits d20and d22are read straight out of the register26with respective data bits d0and d2, which were stored in respective register locations R0and R2. Data bits d1and d3in respective register locations R1and R3are moved to register locations R0and R2, and incoming data bits d21and d23are stored in register locations R1and R3respectively. Alternatively (but not illustrated), data bits d1and d3may remain in respective register locations R1and R3, and incoming data bits d21and d23can be stored in respective register locations R0and R2. In either case, two pairs of data bits whose indices are 20 apart are output from the register26each clock cycle to one of the first or second memories16,18, via the multiplexer34and demultiplexer14. In the register26, data bits d1and d21and d3and d23are now stored in adjacent register locations.

This process continues as shown inFIG. 8(c).FIG. 8(d) shows the state of the register26after five clock cycles. Each consecutive pair of register locations has a respective pair of data bits stored therein, with the data bits having indices that are 20 apart. Thus, register locations R6and R7have data bits d7and d27stored therein, and so on.

In the last five clock cycles of the pattern, two pairs of data bits stored in consecutive register locations are read out of the register26, and all four of the incoming data bits are stored in the vacated register locations.

Thus, inFIG. 8(e), the data bits d1and d21in consecutive register locations R0and R1respectively are read out of the register26to one of the first or second RAMs16,18, and the incoming pair of data bits d40and d41are stored in the now-vacant register locations R0and R1. This process continues, until the tenth clock cycle in the pattern, when the state of the register26is as shown inFIG. 8(f).

After the tenth clock cycle of the pattern, consecutive data bits d40to d59have been stored in respective register locations R0to R19, and each of data bits d0to d19have been read out of the register26with a corresponding data bit that has an index that is 20 higher. It can be seen that the state of the register26inFIG. 8(f) corresponds to the state of the register26inFIG. 7(a). Thus, the pattern of ten clock cycles repeats for the remainder of the incoming data stream.

FIGS. 9(a) to9(g) illustrate the operation of the preprocessing unit12when deintv_type=3.

According to the Wimedia PHY specification, when the data rate is higher than 200 Mb/s, i.e. when deintv_type=3, dual carrier modulation is used. In a dual carrier modulator, two hundred incoming bits are grouped into fifty groups of four bits, which are modulated on two sub-carriers. At the dual carrier demodulator (which is not shown inFIG. 5), the output bits are also in groups. Based on a data stream comprising bits d0, d1, d2, . . . , the data stream is output from the dual carrier demodulator in the order d0, d1, d50, d51, d2, d3, . . . .

As when deintv_type=1 or 2, the intra-symbol preprocessing unit12processes the incoming data stream and outputs the data bits in accordance with the pattern described in paragraph (ii) above. Thus, the unit12groups the data stream into pairs of bits whose indices are 20 apart.

However, as a result of the operation of the dual carrier demodulator when deintv_type=3, the processing required to group the data bits is more complicated than when deintv_type=1 or 2. Thus, the intra-symbol preprocessing unit12uses all three of the first main register array26, the second main register array28and the special register array30to process the incoming data stream.

In order to reduce the number of figures required to illustrate the operation of the preprocessing unit12when deintv_type=3, each ofFIGS. 9(a)-(g) show the state of the registers26,28and30at the end of every ten clock cycles. As four soft data bits will be input to the preprocessing unit12each clock cycle, illustrated above the registers26,28and30are twenty pairs of data bits dxdx+1. Due to the nature of the output of the dual carrier demodulator mentioned above, the forty data bits will not be consecutively numbered (i.e. they will not be in the order dx. . . dx+40). The twenty pairs of data bits dydy+20illustrated below the registers26,28and30are the data bits output from those registers during the ten clock cycles represented by that Fig.

FIG. 9(a) shows that the first forty data bits, denoted d0to d19and d50to d69have been received at the preprocessing unit12and have been directed by the demultiplexer32to appropriate locations in the first main register array26, second main register array28and special register array30. Data bits d0to d19have been stored in locations R0to R19respectively in the first main register array26, data bits d50to d59have been stored in locations R0to R9respectively in the second main register array28, and data bits d60to d69have been stored in locations R0to R9respectively in the special register array30. In the next ten clock cycles, data bits d20. . . d39and d70. . . d89will be received.

As shown inFIG. 9(b), the incoming data bits with even indices d20, d22, . . . , d38are read straight out of the register26with respective data bits with even indices d0, d2, . . . , d18which were stored in respective even-numbered register locations R0, R2, . . . , R18. Data bits with odd indices d1, d3, . . . , d19in respective odd-numbered register locations R1, R3, . . . , R19are moved to newly vacated even-numbered register locations R0, R2, . . . , R18, and incoming data bits with odd indices d21, d23, . . . , d39are stored in respective locations R1, R3, . . . , R19in the first main register array26. Alternatively (but not illustrated), the data bits with odd indices in the first main register array26may remain in their respective register locations, and the incoming data bits with odd indices d21, d23, . . . , d39can be stored in respective even-numbered register locations R0, R2, . . . , R18. In either case, two pairs of data bits whose indices are 20 apart are output from the register26each clock cycle to one of the first or second memories16,18, via the multiplexer34and demultiplexer14. In the register26, each data bit is stored adjacent to a data bit whose index differs from that first data bit by 20.

The process continues as shown inFIGS. 9(c)-(g) with two pairs of consecutive data bits being written into one of the registers26,28or30each clock cycle, and two pairs of data bits whose indices differ by 20 being read out of one of the registers26,28or30, until all of the incoming data stream has been processed. It should be noted that as there is a gap between symbols at the input of the deinterleaver, the indicated register locations inFIGS. 9(f) and (g) are kept empty until all two hundred bits of the current symbol are processed.

In an alternative embodiment, if there is a reordering block after or in the dual carrier demodulator, the data stream can be provided to the deinterleaver in a natural order, i.e. d0, d1, d2, d3, d4, . . . . Therefore, it is not necessary for the intra-symbol preprocessing unit12to use the second main register array28or the special register array30. Instead, the operation of the preprocessing unit12will be as shown inFIGS. 8(a)-(f) for deintv_type=2.

As described above, the output from the intra-symbol preprocessing unit12each clock cycle is a pair of data bits, whose indices differ by 10 when deintv_type=1, or by 20 when deintv_type=2 or 3. Due to the high throughput requirement of the deinterleaver10, and the limited access speed of current memories (particularly CMOS memories), each pair of soft bits output by the preprocessing unit12are stored at a single memory address in one of the first or second memories16,18.

Also as described above, at any one time, one of the memories16,18will be receiving and storing pairs of data bits from the preprocessing unit12for a current set of six symbols, while the other memory16,18will be outputting pairs of data bits for a set of six symbols that have been previously stored in the memory16,18.

The read/write address generator20determines the locations in the first and second memories16,18to which data is to be written to or read from. As described, the read/write generator controls the memory16,18that are receiving pairs of data bits from the intra-symbol preprocessing unit12so that the bits for each OFDM symbol are stored at appropriate addresses in the memory16,18.

When deintv_type=1, the write address for the data bits dxdx+10in the Mthsymbol in the first or second memory16,18is determined from the following equation:

2⁢⁢Mod⁡(x,20)+20⁢⁢Floor⁡(x20)+100⁢⁢M(4)
where Mod(x,y) is the modulus operator which returns the non-negative integer remainder when x is divided by y, and Floor(z) is the floor function which returns the largest integer value less than or equal to its argument value.

When deintv_type=2 or 3, the write address for the data bits dxdx+20in the Mthsymbol in the first or second memory16,18is determined from the following equation:

However, the read address generator that generates the addresses that data is to be read from is more complicated.

Essentially, the address generator20uses a pre-fetching mechanism to deal with the cyclic shift in the third stage of the interleaver. When pre-fetching is enabled for the current OFDM symbol, the corresponding memory location is first pre-fetched and it is combined with the following data in a normal way before being passed to the inter-symbol processing unit24.

At the same time, different address counters (addr0, addr1, addr2, addr3, addr4, addr5) are used to facilitate the generation of the read addresses. Basically, each address counter is responsible for one OFDM symbol, which is located in one continuous section in the respective memory16,18, and each address counter is incremented by a certain value each clock cycle during normal operation. Once the address counter reaches the boundary value of that memory section (i.e. the section of the memory16,18in which that OFDM symbol is stored), the address value will be wrapped around within the memory section. The read address generation is preferably controlled by a dual loop counter, which uses an inner loop and an outer loop. When the inner loop count, inner_cnt, reaches a certain threshold, it is reset to zero and the outer loop count, outer_cnt, is incremented by 1.

The operation of the address generator20will now be described in detail with reference toFIG. 10. In step101, an initialization is performed. Parameters inner_cnt and outer_cnt are set to zero. The six address counters, addr0, addr1, addr2, addr3, addr4, addr5, are initialized to zero. Initial address values init_addr0, init_addr1, init_addr2, init_addr3, init_addr4and init_addr5which represent the first address in the continuous section of the memory16,18in which the data bits for the respective OFDM symbol are stored are determined. A parameter, pref_en, is set for each OFDM symbol, which indicates whether pre-fetching is enabled for that symbol. The parameter, pref_en, is initially set to disabled.

In step103, the first three of the address counters, addr0, addr1and addr2, are set to the initial address values init_addr0, init_addr1and init_addr2respectively. If deintv_type=3, then the fourth, fifth and sixth address counters, addr3, addr4, addr5, are set to the initial address values init_addr3, init_addr4and init_addr5respectively.

In step105, a pair of data bits in one memory location are pre-fetched for each OFDM symbol whose pref_en is high. These data bits are obtained from the address indicated by the appropriate init_addr.

In step107, one memory location for symbols0and1are read in accordance with the values of addr0and addr1respectively.

In step109, the value of addr0is incremented by 20, and the value of addr1is incremented by 20 if the current value of addr1is less than 180. Otherwise, the value of addr1is decremented by 80.

In step111, it is determined whether deintv_type=3. If deintv_type=1 or 2, then the process moves to step113in which a memory location for symbol2is read in accordance with the value of addr2. In step115, which follows step113, the value of addr2is incremented by 20 if the current value of addr2is less than 280, otherwise, the value of addr2is decremented by 80. The process then moves to step117.

If, in step111, it is determined that deintv_type=3, then the process moves to step119in which one memory location for symbols2,3,4and5are read in accordance with the values of addr2, addr3, addr4and addr5respectively. In step121, which follows step119, the value of addr2is incremented by 20 if the current value of addr2is less than 280, otherwise, the value of addr2is decremented by 80. The value of addr3is incremented by 20 if the current value of addr3is less than 380, otherwise, the value of addr3is decremented by 80. The value of addr4is incremented by 20 if the current value of addr4is less than 480, otherwise, the value of addr4is decremented by 80. The value of addr5is incremented by 20 if the current value of addr5is less than 580, otherwise, the value of addr5is decremented by 80. The process then moves to step117.

In step117, it is determined whether the value of inner_cnt is 4. If the value of inner_cnt is not 4, the process moves to step123in which the inner_cnt is incremented. After the inner_cnt is incremented, the process returns to step107and a memory location is read for symbols0and1in accordance with the current values for addr0and addr1.

If the value of inner_cnt is not 4, the process moves to step125in which it is determined whether the outer_cnt is 19. If the value of the outer_cnt is 19, the process is complete for those six OFDM symbols, and the process returns to the initialization step101, where to process repeats for subsequent symbols. If the value of the outer_cnt is not 19, the process moves to step127.

In step127, if deintv_type=1, the value of the outer_cnt is incremented by 1, and the values of init_addr0, init_addr1and init_addr2are incremented by 1.

If deintv_type=3, then the value of the outer_cnt is incremented by 1, and the values of init_addr0, init_addr1, init_addr2, init_addr3, init_addr4and init_addr5are incremented by 1.

In all three situations, the inner_cnt is set to zero.

The process then passes to step129in which the value of pref_en is updated based on the current value of the outer_cnt for each OFDM symbol. The table inFIG. 11illustrates the values of pref_en for the various possible combinations of deintv_type, outer_cnt and the index of the current symbol.

After the pref_en value has been updated, the process returns to step103, where the address counters are set to the value of the respective init_addr.

As mentioned above, the data bits output from the selected memory16,18via the multiplexer22, pass into an inter-symbol post-processing unit24.FIG. 12is a block diagram of the post-processing unit24in accordance with the invention. The inter-symbol post-processing unit24performs symbol deinterleaving to reverse the operation of the symbol interleaving unit4shown inFIG. 1. The post-processing unit24comprises a register array36having twelve locations, respectively numbered R0, R1, . . . , R11, and a controller38for controlling the operation of the register array36.

As mentioned, two data bits are stored at each memory address in the memories16,18, so two data bits are output from one of the memories16,18to the post processing unit24each clock cycle. Due to the operation of the preprocessing unit12, these data bits are consecutive data bits from the same symbol. However, only one soft data bit is stored in each register location of register array36.

The post-processing unit24reorders these pairs of data bits so that the output of the post-processing block matches the expected deinterleaved pattern (i.e. 6/TSF symbols output their deinterleaved bits in a round robin way), which will be the pattern of data bits that were provided to the interleaver2in the transmitter.

FIGS. 13(a)-(d) illustrate the operation of the post-processing unit24in accordance with the invention. The shaded register locations indicate that valid data is stored there. The un-shaded register locations are available for receiving data. As shown inFIG. 13(a), data bits are written to register locations R0, R1, R2and R3.

Then, as shown inFIG. 13(b), the data bits in register locations R0and R2are read out, along with any data bits stored in register locations R4and R6. New data bits are written to register locations R4, R5, R6and R7. It will be appreciated that the operation to read the bits stored in register locations R4and R6occurs before the operation to write new bits to those locations. In practice, these operations will occur during the same processor clock cycle.

Then, as shown inFIG. 13(c), the data bits in register locations R1and R3are read out of the register, along with any data bits stored in register locations R8and R10. New data bits are written to register locations R8, R9, R10and R11.

Then, as shown inFIG. 13(d), the data bits in register locations R5, R7, R9and R11are read out of the register. These register locations are accessed in numerical order, i.e. R5, R7, R9and then R11. New data bits are written to register locations R0, R1, R2and R3. The process then repeats fromFIG. 13(b) onwards.

Thus, as can be seen from the operation of the post-processing unit24described above, the pairs of consecutive data bits from the same symbol are separated for output from the deinterleaver10.

Thus, as the deinterleaver structure according to the invention uses a combination of registers and memories, the deinterleaver is simple and inexpensive to design and implement. If the scheme used to interleave the data stream is modified in any way, or if an alternative interleaving scheme is used, it is easy to adapt the deinterleaver by changing the operation of the address generation part of the register arrays. Changes in the size of symbols can also be easily adapted to by modifying the size of the memories16,18used in the deinterleaver10.

As mentioned above, although the invention has been described with reference to an ultra-wideband network in accordance with the “MultiBand OFDM Physical Layer Specification” Release 1.0 from the MultiBand OFDM Alliance, the invention is applicable to any other system which uses multi-level interleaving to protect data communications between two devices. For example, the invention is also applicable to wireless, mobile and satellite communication systems, optical and magneto-optical storage systems and hard disk and digital tape storage systems.