Semiconductor Fin FET device with epitaxial source/drain

In a method of fabricating a Fin FET, first and second fin structures are formed. The first and second fin structures protrude from an isolation insulating layer. A gate structure is formed over the first and second fin structures, each of which has source/drain regions, having a first width, outside of the gate structure. Portions of sidewalls of the source/drain regions are removed to form trimmed source/drain regions, each of which has a second width smaller than the first width. A strain material is formed over the trimmed source/drain regions such that the strain material formed on the first fin structure is separated from that on the second fin structure. An interlayer dielectric layer is formed over the gate structure and the source/drain regions with the strain material. A contact layer is formed on the strain material such that the contact layer wraps around the strain material.

TECHNICAL FIELD

The disclosure relates to a semiconductor integrated circuit, more particularly to a semiconductor device having conformal epitaxial source/drain regions and wrap-around contacts and its manufacturing process.

BACKGROUND

As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (Fin FET). Fin FET devices are a type of multi-gate structure that typically include semiconductor fins with high aspect ratios and in which channel and source/drain regions of semiconductor transistor devices are formed. A gate is formed over and along the sides of the fin structure (e.g., wrapping) utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. Formation of contact areas in the source/drain regions are increasingly limited by the increasing device densities of the Fin FET devices.

DETAILED DESCRIPTION

FIG. 1Ais an exemplary perspective view of a Fin FET device100having a fin structure, andFIG. 1Bis an exemplary perspective view of a Fin FET device101in accordance with one embodiment of the present disclosure. In these figures, some layers/features are omitted for simplification. The present disclosure includes examples relating to Fin FET devices for purposes of explaining features of the provided subject matter but the present disclosure may relate to other multi-gate structures depending on implementation.

The Fin FET device100and Fin FET device101respectively depicted inFIGS. 1A and 1Binclude, among other features, a substrate110, a fin structure120, a gate dielectric layer132and a gate electrode layer134. The substrate110may be a silicon substrate.

InFIGS. 1A and 1B, the fin structure120is disposed over the substrate110. The fin structure120may be made of the same material as the substrate110and may continuously extend from the substrate110. In this embodiment, the fin structure is made of silicon (Si). The silicon layer of the fin structure120may be intrinsic, or appropriately doped with an n-type impurity or a p-type impurity.

Three fin structures120are disposed over the substrate110inFIGS. 1A and 1B. However, the number of the fin structures is not limited to three. The numbers may be one, two or four or more. In addition, one or more dummy fin structures may be disposed adjacent to both sides of the fin structures120to improve pattern fidelity in patterning operations. The width of the fin structure120is in a range of about 5 nm to about 40 nm in some embodiments, and may be in a range of about 7 nm to about 12 nm in certain embodiments. The height of the fin structure120is in a range of about 100 nm to about 300 nm in some embodiments, and may be in a range of about 50 nm to 100 nm in other embodiments.

Spaces between the fin structures120and/or a space between one fin structure and another element formed over the substrate110are filled by an isolation insulating layer150(or so-called a “shallow-trench-isolation (STI)” layer) including an insulating material. The insulating material for the isolation insulating layer150may include one or more layers of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material.

The lower part of the fin structure120under the gate electrode layer134is referred to as a well region120A, and the upper part of the fin structure120is referred to as a channel region120B. Under the gate electrode layer134, the well region120A is embedded in the isolation insulating layer150, and the channel region120B protrudes from the isolation insulating layer150. A lower part of the channel region120B may also be embedded in the isolation insulating layer150to a depth of about 1 nm to about 5 nm.

The channel region120B protruding from the isolation insulating layer150is covered by a gate dielectric layer132, and the gate dielectric layer132is further covered by a gate electrode layer134. Part of the channel region120B not covered by the gate electrode layer134functions as a source and/or drain of the Fin FET device100.

Source and drain regions125are also formed in the upper part of the fin structure120not covered by the gate electrode layer134, by appropriately doping impurities in the source and drain regions125. An alloy of Si or Ge and a metal such as Co, Ni, W, Ti or Ta or any other suitable material may be formed on the source and drain regions125.

Formation of the source/drain regions125are based on existing fabrication operations which include a deep source/drain recess operation, a selective epitaxial growth operation and a top-contact formation operation. The contact area depends on the surface area of the epitaxial source/drain region (e.g., the source/drain regions125). The different growth rates of the different crystal orientations may result in a faceted or diamond-shaped source/drain structure.

InFIG. 1A, the source/drain regions125from adjacent fins are typically merged. As device densities increase, the fin pitch shrinkage causes a decrease in space between adjacent fins thereby increasing the likelihood of the source/drain regions125merging. Although the three source/drains (for three fin FETs) are designed to have the same electrical potential, in such a structure, a contact plug to the source/drain regions125from above may touch only the upper portions of the source/drain regions125, and may not touch the side surface (in particular, bottom of the side surfaces) of the source/drain regions125. This limits the formation of a “wrap-around” contact to the source/drain regions, and decreases the amount of contact area available, thereby increasing the parasitic resistance in the Fin FET device100.

In contrast to the Fin FET device100shown inFIG. 1A, inFIG. 1B, the adjacent source/drain regions125are not merged with each other. Accordingly, the contact plug to the source/drain regions125from above can touch both the upper portions of the source/drain regions125and substantially the entire side walls of the source/drain regions125, forming a “wrap-around” contact. In the structure ofFIG. 1B, a greater contact area can be obtained, which can reduce parasitic capacitance.

The present disclosure provides for the formation of non-faceted fin-shaped, high aspect ratio (e.g., tall and thin) epitaxial source/drain regions that do not merge with that of an adjacent fin device (e.g.,FIG. 1B). In this regard, wrap-around contact plugs may be formed for fins with an aggressively scaled fin pitch and a high aspect ratio. The combination of the wrap-around contact plug and the conformal epitaxial source/drain on fin-shaped source/drain can increase the amount of contact area and reduce the parasitic resistance in the Fin FET device. In addition, source/drain defects such as a void may be prevented due to the absence of merged source/drain regions. The advantageous features of the present disclosure include compatibility with existing FinFET-based CMOS device fabrication process flows with low additional cost compared with the original fabrication flow.

FIGS. 2-19illustrate examples of cross sectional perspective views of intermediate stages in the sequential fabrication process of a Fin FET device200in accordance with some embodiments of the present disclosure. Not all of the depicted components may be required, however, and one or more implementations may include additional components not shown in the figure. Variations in the arrangement and type of the components may be made without departing from the scope of the claims as set forth herein. Additional components, different components, or fewer components may be provided. Further, the order of the operations may be changed.

FIG. 2is a perspective view of the Fin FET device200at an early stage of various stages of a first sequential fabrication process according to one embodiment of the present disclosure. In this embodiment, the substrate110includes a crystalline silicon substrate (e.g., wafer). A p-type substrate or n-type substrate may be used and the substrate110may include various doped regions, depending on design requirements. In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for an n-type Fin FET, or alternatively configured for a p-type Fin FET.

Alternatively, the substrate110may comprise another elementary semiconductor, such as germanium; a compound semiconductor including IV-IV compound semiconductors such as SiC and SiGe, III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlinAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In one embodiment, the substrate110is a silicon layer of an SOI (silicon-on insulator) substrate. When an SOI substrate is used, the fin structure120may protrude from the silicon layer of the SOI substrate or may protrude from the insulator layer of the SOI substrate. In the latter case, the silicon layer of the SOI substrate is used to form the fin structure120. Amorphous substrates, such as amorphous Si or amorphous SiC, or insulating material, such as silicon oxide may also be used as the substrate110.

Also alternatively, the substrate may include an epitaxial layer. For example, the substrate may have an epitaxial layer overlying a bulk semiconductor. Further, the substrate may be strained for performance enhancement. For example, the epitaxial layer may include a semiconductor material different from that of the bulk semiconductor, such as a layer of silicon germanium overlying bulk silicon or a layer of silicon overlying bulk silicon germanium. Such strained substrates may be formed by selective epitaxial growth (SEG). Also alternatively, the substrate may include a buried dielectric layer, such as a buried oxide (BOX) layer, such as that formed by separation by implantation of oxygen (SIMOX) technology, wafer bonding, SEG, or other appropriate operation.

As shown inFIG. 2, a pad layer204aand a mask layer204bare formed on the semiconductor substrate110. The pad layer204amay be a thin film having silicon oxide formed, for example, using a thermal oxidation operation. The pad layer204amay act as an adhesion layer between the semiconductor substrate110and the mask layer204b. In at least one embodiment, the mask layer204bis formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer204bis used as a hard mask during subsequent patterning operations. A photoresist layer206is formed over the mask layer204band is then patterned by a lithography patterning operation, thereby forming openings in the photoresist layer206. The photoresist layer may be removed after patterning of the mask layer204band pad layer204aand before the trench etching.

FIG. 3is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. The mask layer204band pad layer204aare etched to expose underlying semiconductor substrate110. The exposed semiconductor substrate110is then trench-etched to form trenches210by using the patterned mask layer204band pad layer204aas a mask.

In the trench etching operation, the substrate110may be etched by various methods, including a dry etch, a wet etch, or a combination of dry etch and wet etch. The dry etching operation may implement fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C4F8), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), bromine-containing gas (e.g., HBr and/or CHBr3), oxygen-containing gas, iodine-containing gas, other suitable gases and/or plasmas, or combinations thereof. In some embodiments, a wet cleaning operation may be performed to remove a native oxide of the semiconductor substrate110after the trench etching. The cleaning may be performed using dilute hydrofluoric (DHF) acid.

Portions of the semiconductor substrate110between trenches210form semiconductor fins120. The fins120may be arranged in strips (viewed from the top of the Fin FET device200) parallel to each other, and closely spaced with respect to each other. Each of the fins120has a width W and a depth D, and are spaced apart from an adjacent fin by a width S of the trench210. For example, the width W of the semiconductor fin120may be in a range of about 2 nm to about 20 nm in some embodiments.

FIG. 4is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. After trenches210and fins120are formed, trenches210are filled with one or more layers of dielectric material214. The dielectric material214may include silicon oxide. In one or more implementations, the dielectric material214is made of, for example, silicon dioxide formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. In the flowable CVD, flowable dielectric materials instead of silicon oxide are deposited. Flowable dielectric materials, as their name suggests, can “flow” during deposition to fill gaps or spaces with a high aspect ratio. Usually, various chemistries are added to silicon-containing precursors to allow the deposited film to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include a silicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS), a perhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silyl-amine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multiple-operation process. After the flowable film is deposited, it is cured and then annealed to remove un-desired element(s) to form silicon oxide. When the un-desired element(s) is removed, the flowable film densifies and shrinks. In some embodiments, multiple anneal processes are conducted, and the flowable film is cured and annealed more than once.

In some embodiments, one or more layers of other dielectric materials, such as silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or a low-K dielectric material, may also be used to form the dielectric material214. In an embodiment, the dielectric material214is formed using a high-density-plasma (HDP) CVD operation, using silane (SiH4) and oxygen (O2) as reacting precursors. In other embodiments, the dielectric material214may be formed using a sub-atmospheric CVD (SACVD) operation or high aspect-ratio process (HARP), in which process gases may include tetraethylorthosilicate (TEOS) and/or ozone (O3). In yet other embodiments, the dielectric material214may be formed using a spin-on-dielectric (SOD) operation, such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). In some embodiments, the filled recess region (or the trenches210) may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

After the deposition of the dielectric material214, a planarization operation such as a chemical mechanical polish (CMP) and an etch-back operation is then performed. In some embodiments, an annealing operation may be performed after the trenches210are filled with the dielectric material214. The annealing operation includes rapid thermal annealing (RTA), laser annealing operations, or other suitable annealing operations.

During the planarization operation, the mask layer204band pad layer204amay be removed. Alternatively, in at least one embodiment, if the mask layer204bis formed of silicon nitride, the mask layer204bmay be removed using a wet operation using H3PO4. The pad layer204amay be removed using dilute HF acid if the pad layer204ais formed of silicon oxide. The remaining portions of the dielectric material214in the trenches210are hereinafter referred to as isolation regions150.

FIG. 5is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. The top portion of each of the semiconductor fin120is recessed to form a recessed portion226of the semiconductor fin120having a top surface219below the top surfaces217of the first and second isolation regions150a,150b. In one embodiment, a biased etching operation is performed to recess top surface219of the semiconductor fin120to form the recessed portion226of the semiconductor fin120. In an embodiment, the etching operation may be performed using HBr and/or Cl2as etch gases.

FIG. 6is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. As shown inFIG. 6, in the recessed portion226, a semiconductor material for the channel region120B (including the source and drain regions125) and a hard mask layer602are formed in this order. The hard mask layer602is disposed on the channel region120B. The hard mask layer602is used as a hard mask for patterning the semiconductor fins120in the source/drain region during subsequent etching operations. The hard mask layer602has a substantially slower etch rate compared to the channel region120B. In some embodiments, the channel region120B, such as silicon carbon (SiC) and/or silicon phosphide (SiP), is epitaxially grown by a LPCVD process over the recessed semiconductor fins120. In at least another embodiment, the channel region120B, such as silicon germanium (SiGe) or germanium tin (GeSn), may be epitaxially grown by the LPCVD process over the recessed semiconductor fins120. The hard mask layer602, such as Si, may be epitaxially grown by the LPCVD process. In some embodiments, the channel region120B is made of Si and the hard mask layer602is made of SiC.

FIG. 7is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. An etching operation is performed to etch part of isolation regions150to expose the channel region120B of the semiconductor fins120from the isolation regions150. In this embodiment, the hard mask layer602remains on the channel region120B. The etching operation may include a dry etching operation, wet etching operation, or combination dry and wet etching operations to remove portions of the isolation regions150. It is understood that the etching operation may be performed as one etching operation or multiple etching operations.

The remaining isolation regions150include top surfaces217. Further, the channel regions120B of the semiconductor fins120protruding over the top surfaces217of the remaining isolation regions150thus are used to form an active area of the Fin FET device200. The channel region120B of the semiconductor fins120may include top surfaces223and sidewalls224. Height H of the channel region120B of the semiconductor fins120from the top surface217of the isolation regions150may be in a range of about 6 nm to about 200 nm. In some embodiments, the height H is greater than 200 nm or smaller than 6 nm.

FIG. 8is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure.

After the channel region120B is exposed from isolation regions150, a gate stack130is formed over the exposed channel region120B, so as to extend along the top surfaces217of the first isolation region150aand the second isolation region150b. In this embodiment, a section of the hard mask layer602is interposed between the semiconductor fin120(the exposed channel region120B) and the gate stack130. The gate stack130includes a gate dielectric layer132and a gate electrode layer134disposed on the gate dielectric layer132.

The gate dielectric layer132is formed to cover the top surface223and sidewalls224of at least a portion of the channel region120B of the semiconductor fins120. In some embodiments, the gate dielectric layer132includes one or more layers of silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectrics. High-k dielectrics may include metal oxides. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/or mixtures thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HMO, HfSiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. The gate dielectric layer132may be formed using a suitable operation such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. The gate dielectric layer132may further include an interfacial layer (not shown) to reduce damage between the gate dielectric layer132and the semiconductor fin120. The interfacial layer may include silicon oxide.

The gate electrode layer134is then formed on the gate dielectric layer132. In at least one embodiment, the gate electrode layer134covers the channel region120B of more than one semiconductor fin120. In some alternative embodiments, each of the channel regions120B of the semiconductor fins120may be used to form a separate Fin FET device200. The gate electrode layer134may include a single layer or a multilayer structure. The gate electrode layer134may include poly-silicon. Further, the gate electrode layer134may be doped poly-silicon with the uniform or non-uniform doping. In some alternative embodiments, the gate electrode layer134may include a metal such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, other conductive materials with a work function compatible with the substrate material, or combinations thereof. The gate electrode layer134may be formed using a suitable operation such as ALD, CVD, PVD, plating, or combinations thereof. In some embodiments, a hard mask layer, which has been used to pattern a poly silicon layer, is formed on the gate stack130.

In some embodiments, one or more work function adjustment layers (not shown) may be interposed between the gate dielectric layer132and the gate electrode layer134. The work function adjustment layer may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), liner layer, wetting layer, adhesion layer, metal alloy or metal silicide. The work function adjustment layers are made of a conductive material such as a single layer of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or a multilayer of two or more of these materials. In some embodiments, the work function adjustment layer may include a first metal material for the n-channel Fin FET and a second metal material for the p-channel Fin FET. For example, the first metal material for the n-channel Fin FET may include metals having a work function substantially aligned with a work function of the substrate conduction band, or at least substantially aligned with a work function of the conduction band of the channel region120B. Similarly, for example, the second metal material for the p-channel Fin FET may include metals having a work function substantially aligned with a work function of the substrate valence band, or at least substantially aligned with a work function of the valence band of the channel region120B. For the n-channel Fin FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer, and for the p-channel Fin FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer. In some embodiments, the work function adjustment layer may alternatively include a polysilicon layer. The work function adjustment layer may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable operation. Further, the work function adjustment layer may be formed separately for the n-channel Fin FET and the p-channel Fin FET, which may use different metal layers.

FIG. 9is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. Following the formation of the gate stack130, a lightly-doped-drain (LDD) implantation902is performed on the source/drain regions125of the semiconductor fins120not covered by the gate stack130. The LDD implantation902may be performed with a tilt angle relative to vertical axis904. In one or more implementations, the LDD implantation902may not be performed if the hard mask layer602is removed from the top surface223of the semiconductor fins120immediately after the patterning of the gate stack130. The LDD implantation902may utilize p-type dopants (e.g., B or In) for PMOS devices and n-type dopants (P or As) for NMOS devices.

In some aspects, the LDD implantation902implants the dopant species using implant energy in a range of about 0.1 KeV to about 500 KeV. In some embodiments, the implant dosage may be in a range of about 1×1012atoms/cm2to about 1×1015atoms/cm2. In other embodiments, the acceleration voltage is in a range of about 10 KeV to about 100 KeV. In one or more implementations, ions are also implanted into the sidewalls224of the exposed semiconductor fins120. The tilt angle may vary in a range of about 0 degrees to about 45 degrees relative to the vertical axis904. In addition, the ions can be implanted from two directions (e.g., 0 degrees and 180 degrees by rotating the wafer) or four directions.

Following the LDD implantation902, a dielectric layer may be disposed along the side of the gate stack130to form sidewall spacers (not shown). In some embodiments, the dielectric layer includes one or more layers of silicon oxide, silicon nitride, silicon oxy-nitride, or other suitable material. The dielectric layer may include a single layer or multilayer structure. A blanket layer of the dielectric layer may be formed by CVD, PVD, ALD, or other suitable technique. Then, an anisotropic etching and/or etch-back operation is performed on the dielectric layer to form a pair of sidewall spacers on two sides of the gate stack130. During the formation of the gate stack130, various cleaning/etching operations, which etch the STI regions150aand150b, are performed. After the formation of the sidewall spacers, additional ion implantation operation may be performed to introduce impurities in the source and drain regions125.

FIG. 10is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. Following the LDD implantation902, a lateral trimming of the sidewalls224of the semiconductor fins120by an etch operation1002is performed. The hard mask layer602serves to protect the top surface223of the semiconductor fins120by retaining the integrity of the sidewalls224. In this regard, the hard mask layer602can reduce the etching rate at the top surface223thereby reducing the amount of etching at the top surface223for the same duration of etching on the remainder of the channel region120B.

The portions of the sidewalls224located beneath the hard mask layer602can be removed (or etched) to reduce the size (width) of the source/drain region125(e.g., along the <110> axis) and thereby reduce the likelihood of the source/drain region125merging when a strain material is formed (e.g., adjacent strain materials becoming connected). In this embodiment, the etch operation1002is applied without a bias voltage (e.g., 0 V bias) but the bias voltage may vary for other implementations. The total amount of etching for the lateral trimming may be about 40% to about 60% of the original width of the channel region120B. In other embodiments, the total amount of etching for the lateral trimming may be up to about 45% to about 50% of the original width of the channel region120B. In this example, the minimum width of the source/drain regions125may be about 2.0 nm after the lateral trimming operation is performed. The etching rate and/or the duration of the etch operation1002may vary to yield the desired post-trimming width of the source/drain regions125. In one or more implementations, the etching rates of the different crystal orientations (e.g., <100>, <110>, <101>) may vary relative to the respective epitaxy rates. In some embodiments, the etch operation1002is applied recursively in a closed loop until the desired post-trimming width is reached. For example, a number of iterations for removing material from the sidewalls224are performed to yield the desired width of the source/drain regions125.

The etch operation may include a dry etching operation, wet etching operation, or combination dry and wet etching operations. It is understood that the etching operation may be performed as one etching operation or multiple etching operations. The etch operation also may include an anisotropic etching and/or etch-back operation performed on the sidewalls224to reduce the width of the source/drain regions125.

In one or more implementations, a surface plasma treatment may be applied on the sidewalls224to increase the etching rate at the surface of the sidewalls224. In other implementations, an atomic layer etch operation is applied to shape the sidewalls224to the desired width for subsequent source/drain epitaxial operations.

FIG. 11is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. Following the trimming operation1002, the hard mask layer602is removed from the top surface223of the semiconductor fins120. The hard mask layer602may be removed using suitable etching and/or cleaning operations. In some embodiments, remnants of the hard mask layer602may be interposed between the gate dielectric layer132and the channel region120B under the gate stack130.

FIG. 12is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. The structures depicted inFIG. 12are produced by selectively growing a strained material160over the trimmed semiconductor fin120and extending over the top surfaces217of the first and second isolation regions150a,150b. Since the lattice constant of the strained material160is different from the channel region120B, the channel region120B is strained or stressed to increase carrier mobility and enhance the device performance. In this embodiment, the strained material160is formed separately (i.e., without merging) with respect to each semiconductor fin120. The trimmed portions of the semiconductor fin120allow for an increase in the spaces between adjacent fin structures and reduce the likelihood of the strain material160of merging (e.g., adjacent strain material becoming merged).

In at least one embodiment, the strained material160, such as silicon carbide (SiC) and/or silicon phosphide (SiP), is epitaxially grown by a LPCVD operation to form the source and drain regions125for an n-type Fin FET device. In at least another embodiment, the strained material160, such as silicon germanium (SiGe), is epitaxially grown by a LPCVD operation to form the source and drain regions125for a p-type Fin FET device. In this example, the n-type Fin FET may be covered by, for example, a silicon nitride (SiN) layer such that the n-type Fin FET is protected during the recess and source/drain formation in the p-type Fin FET. After the strained material160is formed for the p-type Fin FET, the p-type Fin FET is covered by the SiN layer, and then similar operations including recess formation and strain material formation are performed on the n-type Fin FET.

FIG. 13is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. After forming the strain material160, an operation of depositing an interlayer dielectric (ILD) layer1302is performed. The ILD layer1302is deposited by a suitable technique, such as CVD. In this example, the ILD layer1302may be applied as a layer uniformly over the source/drain regions125. The ILD layer1302includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, a low-k dielectric material or a combination thereof. The ILD layer1302may be subsequently planarized by a CMP operation.

FIG. 14is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. After CMP of the ILD layer1302, an operation of removing the dummy gate (e.g., the gate stack130) and an operation of removing the dummy gate dielectric (e.g., the gate dielectric layer132) are performed, hence leaving an open area1402. The dummy gate and dummy gate dielectric are removed using suitable etching operations. In this embodiment, the hard mask layer602interposed between the gate stack130and the semiconductor fins120remains on the top surface223of the channel region120B.

FIG. 15is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. Following the removal of the gate stack130, the hard mask layer602that remained on the top surface223of the channel region120B is removed. The hard mask layer602can be removed by suitable etching operations. In this regard, the removal of the hard mask layer602provides for an increase in the gate control thereby yielding an increase in performance of the operational current. If the hard mask layer602remains on the channel region120B, the gate control would be adversely affected thereby inducing operational current degradation by about 6-10%. In some aspects, the induced operational current degradation worsens as the thickness of the hard mask layer602increases. By removing the hard mask layer602, such problems can be eliminated.

FIG. 16is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. Subsequently, a metal gate1602and a high-k gate dielectric (not shown) are formed over the channel region120B. According to embodiments of the disclosure, the high-k gate dielectric may include one or more layers of HfO2, HfSiO, HfSiON, HMO, HfSiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof. The metal gate1602material may include one or more layers of Ti, TiN, titanium-aluminum alloy, Al, AlN, Ta, TaN, TaC, TaCN, TaSi, and the like.

FIG. 17is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. After formation of the metal gate electrode structure, the source/drain regions125are exposed by etching part of the ILD layer1302. In some embodiments, openings over the source/drain regions125may be formed by patterning the ILD layer1302, such as a lithographic process together with an etch operation to form the openings exposing the source/drain regions with strain material160.

FIG. 18is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. After exposing the source/drain regions125from the ILD layer1302, an operation of depositing a conductive material to form a wrap-around contact layer1802(or an interlayer contact layer) on the surface of the strained material160is performed. The wrap-around contact layer1802may represent an interconnection to/from the source/drain regions125.

The wrap-around contact layer1802is deposited by a suitable technique, such as sputtering, plating or CVD. In one embodiment, the wrap-around contact layer1802may be applied as a uniform layer over the source/drain regions125. Examples of the conductive material include one or more layer of metal such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, other conductive materials.

FIG. 19is a perspective view of the Fin FET device200at one of various stages of a first sequential fabrication process according to an embodiment of the present disclosure. After forming the wrap-around contact layer1802, an operation of depositing an interconnect layer1902may be performed. In some aspects, the interconnect layer1902serves as a contact plug to interconnect the wrap-around contact layer1802to upper wiring layers (not shown) of the Fin FET device200.

In this example, the interconnect layer1902may be applied to fill in the opening/space over wrap-around contact layer1802formed over the source/drain regions125. A suitable conductive material, such as copper, tungsten, nickel, titanium, or the like, is deposited on the wrap-around contact layer1802. For example, tungsten may be used to form tungsten plugs in the opening over the source/drain regions125. The interconnect layer1902may be formed by CVD, PVD, plating, etc. A damascene technology may be utilized to form the interconnect layer1902.

In contrast to the Fin FET device100(FIG. 1A), the combination of a trimmed source/drain regions and conformal epitaxial strained material growth on the source/drain regions125of the Fin FET device200(FIG. 19) increases the contact area and reduces the parasitic capacitance present in the Fin FET device200. For example, in merged diamond-shaped source/drain regions125(FIG. 1A), a contact plug may contact only the upper surface of the merged source/drain regions125. In contrast, inFIG. 19, the contact plug (e.g., the interconnect layer1902) can contact the side surfaces of the source/drain regions125, and therefore greater contact area can be obtained, which reduces parasitic capacitance.

FIGS. 20-31illustrate examples of perspective views of intermediate stages of a second sequential fabrication process of a Fin FET structure in accordance with some embodiments of the present disclosure. Because many of the operations and features in this embodiment are the same or similar to the operations with respect toFIGS. 2-19, some of the detailed discussion may be omitted for simplification.

FIG. 20is a perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 8, gate stack130is formed over the substrate110over the top surface223and sidewalls224of the semiconductor fin120, and extending to the top surfaces217of the first isolation region150aand the second isolation region150b. A section of the hard mask layer602is interposed between the semiconductor fin120and the gate stack130. The gate stack130includes a gate dielectric layer132and a gate electrode layer134disposed on the gate dielectric layer132.

FIG. 21is a perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 9, following the formation of the gate stack130, a LDD implantation2102is performed on the source/drain regions125of the semiconductor fins120. The LDD implantation2102may be performed with a tilt angle relative to the vertical axis904. In one or more implementations, the LDD implantation2102may not be performed if the hard mask layer602is removed from the top surface223of the semiconductor fins120immediately after the patterning of the gate stack130.

FIG. 22is a cross-sectional perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 13but unlikeFIGS. 10-12, an operation of depositing an interlayer dielectric (ILD) layer2202is performed. The ILD layer2202is deposited by a suitable technique, such as CVD. In this example, the ILD layer2202may be applied as a layer uniformly over the source/drain regions125. The ILD layer2202may be subsequently planarized by a CMP operation.

FIG. 23is a perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 14, after CMP of the ILD layer2202, an operation of removing the gate stack130and an operation of removing the gate dielectric layer132are performed, hence leaving an open area2302. The gate stack130and the gate dielectric layer132are removed using suitable etching operations.

FIG. 24is a perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 15, following the removal of the gate stack130, the hard mask layer602that remained on the top surface223of the channel region120B is removed, resulting etched area2402. The hard mask layer602can be removed by suitable etching operations.

FIG. 25is a perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 16, after the hard mask layer602is removed, an operation of depositing a metal gate structure including a metal gate2502and a high-k gate dielectric layer (not shown) within the open area2302(see,FIG. 23) is performed.

FIG. 26is a perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 17, by using an etching operation such as dry etching and/or wet etching on the ILD layer2202, the source/drain regions125of the semiconductor fins120are exposed as shown inFIG. 26. The etching operation may be performed as one etching operation or multiple etching operations. In this embodiment, the hard mask layer602remains on the top surface223of the exposed semiconductor fins120.

FIG. 27is a perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 10, after the source/drain regions125are exposed from the ILD layer2202, a lateral trimming of the sidewalls224of the source/drain regions125of the semiconductor fins120by an etch operation2702is performed. In some embodiments, the etch operation2702is applied recursively in a closed loop until the desired post-trimming width is reached. For example, a number of iterations for removing material from the sidewalls224are performed until the width of the source/drain regions125becomes about 40% to about 60% of the original width of the channel region120B. The hard mask layer602protects the top surface223of the source/drain regions125of the semiconductor fins120.

FIG. 28is a perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 11, after the trimming operation, the hard mask layer602is removed from the top surface223of the semiconductor fins120. The hard mask layer602may be removed using suitable etching and/or cleaning operations.

FIG. 29is a perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 12, a strained material160is selectively grown over the source/drain region125of the semiconductor fin120to cover the surface of the sidewalls224and top surface223of the source/drain regions125along the different crystal orientations (e.g., <100>, <110>, <101>). In this embodiment, the strained material160is formed spatially separated (without merging) with respect to each semiconductor fin120. Like inFIG. 11, the trimmed portions of the source/drain regions125allow for the size of the source and drain regions125to be reduced along the <110> axis, thereby reducing the likelihood of the strain material160of merging.

FIG. 30is a perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 18, after forming the strain material160, an operation of depositing a conductive material to form a wrap-around contact layer3002(or an interlayer contact layer) on the surface of the strained material160is performed. The wrap-around contact layer1802is deposited by a suitable technique such as CVD or ALD.

FIG. 31is a perspective view of the Fin FET device200at one of various stages of a second sequential fabrication process according to an embodiment of the present disclosure. Similar toFIG. 19, after forming the wrap-around contact layer3002, an operation of depositing an interconnect layer3102is performed. In some aspects, the interconnect layer3102serves as a contact plug to interconnect the wrap-around contact layer3002to other interconnect layers (not shown) of the Fin FET device200.

Subsequent processing according to embodiments of the present disclosure may also form various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the semiconductor substrate110, configured to connect the various features or structures of the Fin FET device200. For example, a multilayer interconnection includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines.

The Fin FET device200serves only as one example. The Fin FET device200may be used in various applications such as digital circuit, imaging sensor devices, a hetero-semiconductor device, dynamic random access memory (DRAM) cell, a single electron transistor (SET), and/or other microelectronic devices (collectively referred to herein as microelectronic devices). Of course, aspects of the present disclosure are also applicable and/or readily adaptable to other type of transistor, including single-gate transistors, double-gate transistors, and other multiple-gate transistors, and may be employed in many different applications, including sensor cells, memory cells, logic cells, and others.

The present disclosure provides for the formation of non-faceted fin-shaped, high aspect ratio (e.g., tall and thin) epitaxial source/drain regions that do not merge with that of an adjacent fin device. The combination of the wrap-around contact and the conformal epitaxial source/drain on fin-shaped source/drain can increase the amount of contact area and reduce the parasitic resistance in the Fin FET device. In addition, source/drain defects may be avoided due to the absence of merged source/drain regions. The advantageous features of the present disclosure include compatibility with existing FinFET-based CMOS device fabrication process flows with low additional cost compared with the original fabrication flow.

According to one embodiment of the present disclosure, in a method of fabricating a fin field-effect transistor (Fin FET) device, a first fin structure and a second fin structure are provided over a substrate. The first and second fin structures protrude from an isolation insulating layer disposed over the substrate. A gate structure is formed over the first fin structure and the second fin structure. Each of the first fin structure and the second fin structure has a channel region beneath the gate structure and source/drain regions outside of the gate structure. The source/drain regions have a first width. Portions of sidewalls of the source/drain regions in the first fin structure and the second fin structure are removed to form trimmed source/drain regions. Each of the trimmed source/drain regions has a second width smaller than the first width. A strain material is formed over the trimmed source/drain regions of the first fin structure and the second fin structure. The strain material is formed such that the strain material formed on the first fin structure is separated from the strain material formed on the second fin structure. An interlayer dielectric layer is formed over the gate structure and the source/drain regions with the strain material. A contact layer is formed on the strain material formed on the source/drain regions of the first fin structure and the second fin structure such that the contact layer wraps around the strain material on the source/drain regions.

In another embodiment, in a method of fabricating a Fin FET device, a first fin structure and a second fin structure are provided over a substrate. The first and second fin structures protrude from an isolation insulating layer disposed over the substrate. A gate structure is formed over the first fin structure and the second fin structure. Each of the first fin structure and the second fin structure has a channel region beneath the gate structure and source/drain regions outside of the gate structure. The source/drain regions have a first width. An interlayer dielectric layer is formed over the gate structure and the source/drain regions having the first width. Parts of the interlayer dielectric layer are removed to expose the source/drain regions having the first width. Portions of sidewalls of the exposed source/drain regions of the first fin structure and the second fin structure are removed to form trimmed source/drain regions. Each of the trimmed source/drain regions has a second width smaller than the first width. A strain material is formed over the trimmed source/drain regions of the first fin structure and the second fin structure. The strain material is formed such that the strain material formed on the first fin structure is separated from the strain material formed on the second fin structure. A contact layer is formed on the strain material formed on the first fin structure and the second fin structure such that the contact layer wraps around the strain material of the source/drain regions.

In still another embodiment, a semiconductor device comprises a substrate, first and second fin structure, a gate structure, first and second strain material layer and a contact layer. The first fin structure is disposed over the substrate and includes a first channel region and a first source/drain region. The second fin structure is disposed over the substrate and includes a second channel region and a second source/drain region. The gate structure is disposed over at least a portion of the first fin structure and the second fin structure. The first and second channel regions are beneath the gate structure and the first and second source/drain regions are outside of the gate structure. The first strained material layer is disposed over the first source/drain region and the second strain material layer is disposed over the second source/drain region. The first and second strain material layers provide stress to the first and second channel regions, respectively. The contact layer wraps around the first and second strain material layers. The first strain material layer is separated from the second strain material layer.