Automated generation of surface-mount package design

A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.

BACKGROUND

The present invention relates to surface-mount packaging, and more specifically, to automated generation of surface-mount package design.

A surface-mount package acts as an interface between an integrated circuit (i.e., chip) and the printed circuit board (PCB) on which the chip is placed. Thus, the surface-mount package is sometimes referred to as a chip interface or chip carrier. An example of a surface-mount package is a flip chip plastic ball grid array (FCPBGA). A surface-mount package can be a single-chip or multi-chip interface. The top pins of the surface-mount package interface with one or more integrated circuits, and the bottom pins of the surface-mount package interface with the PCB.

SUMMARY

Embodiments of the present invention are directed to systems and methods to perform automated surface-mount package design. A method includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. Analysis and processing of the physical inputs and the electrical inputs are automatically performed, and a design file is automatically generated for manufacture of the surface-mount package. The design file specifies a number and material of layers of the surface-mount package.

DETAILED DESCRIPTION

As previously noted, a surface-mount package acts as an interface between one or more integrated circuits or chips and the board below (e.g., PCB) that provides mechanical and electrical support. A design file specifies the parameters, connections, and constraints used to manufacture the surface-mount package. While the design file is not new, it is typically generated manually and can take a day or more to generate. Embodiments of the systems and methods detailed herein relate to automated generation of surface-mount package design. The design is then fabricated into the surface-mount package. Physical inputs and electrical inputs are provided for automated inclusion in the design file. In addition, electrical checks are performed without operator intervention prior to providing the design file.

FIG. 1is a block diagram of a system100to perform automated generation of surface-mount package design according to one or more embodiments of the invention. The system100includes processing circuitry110and memory115that is used to generate the design file that is ultimately fabricated into the surface-mount package120. A side view of an exemplary surface-mount package120and a board125(e.g., PCB) on which the surface-mount package120can be placed are shown. A top view of an integrated circuit105that can be placed on the surface-mount package120is also shown. As previously noted, the surface-mount package120acts as an interface between the board125and the integrated circuit105, with bottom pins122of the surface-mount package120connecting to the board125and top pins121of the surface-mount package120connecting to the integrated circuit105. While only peripheral pins (121,122) are visible inFIG. 1, each layer typically includes a full array of pins (121,122). An exemplary surface-mount package120can have pins (121,122) on the order of 20,000 or more. Fabrication of an exemplary surface-mount package120is further discussed with reference toFIG. 6.

FIG. 2is a general process flow of an automated process for generating a surface-mount package design according to one or more embodiments of the invention. Physical inputs210and electrical inputs220are provided. At block230, processes detailed with reference toFIG. 3are implemented to perform automated surface-mount package design. Performing the automated surface-mount package design, at block230, results in a design file240. The design file240is in a specific format that facilitates manufacture of the surface-mount package120. An exemplary format for the design file240is the Cadence design format (i.e., Design Exchange Format).

The physical inputs210can be provided as a file (e.g., spreadsheet). The physical inputs210provided for automated surface-mount package design, at block230, are not different than the physical inputs210provided for manual generation of the design file240. Some of the inputs include the name and location (e.g., x and y) of the top pins121and bottom pins122, network connections, network parameter names, differential pair identification, bus or group membership information, packaging material (e.g., organic, ceramic), chip technology, package size, diced chip size, core information for pertinent nets (i.e., interconnect specifications) to facilitate subsequent automatic addition of wiring and vias, and decapsulation information (e.g., name, type, location (e.g., x, y)). The electrical inputs220, like the physical inputs210, are the same inputs that can be provided for manual package design.

The electrical inputs220can include network parameter characteristics (e.g., impedance, maximum delay, frequency, maximum resistance, coupled noise tolerance, reference-above and -below nets, risetime), differential pair parameter characteristics (e.g., bottom-pin-adjacency/neighbor allowance information, coupled noise tolerance, pair impedance, pair impedance tolerance, skew, whether swappable or not), and group parameter characteristics (e.g., level, skew, leading skew, trailing skew, reference net, reference pair). The resulting design file240includes information about the pins (121,122), constraints (e.g., physical constraints), and layers (e.g., number of layers, thicknesses, naming convention of layers, material) so that the surface-mount package120can be fabricated.

FIG. 3is an exemplary process flow of a method of performing automated surface-mount package design, at block230, according to one or more embodiments of the invention. At block310, cross referencing inputs by parameter name refers to extracting physical and electrical input information from the files of physical inputs210and electrical inputs220and identifying parameters that are referenced in both the physical inputs210and electrical inputs220based on their names. At block320, the processes include creating and placing top and bottom symbols for the surface-mount package120, decoupling capacitors, and bottom pins122. Reading the network connection list, from the physical inputs210, facilitates assigning nets to all the pins (121,122) at block330.

At block340, the processes include converting electrical parameters from the file of electrical inputs220to physical sizes, spacings, and lengths. Performing additional electrical checks, at block350, is further detailed with reference toFIGS. 4 and 5. At block360, reading in the core library wiring and via information is optional. This process refers to populating internal wires and relies on the core specification being provided. Performing physical parameter checks, at block370, prevents, for example, two pins (121,122) from having the same name.

The electrical checks, at block350, refer to four types of checks and can generate four output files for review. While an ordering (e.g., first check, second check) of the checks is referenced for explanatory purposes, the electrical checks can be performed in any order according to alternate embodiments. The first check ensures that all pins are within a requisite distance to the nearest ground pin420(FIG. 4). This check is further discussed with reference toFIG. 4. The second electrical check, at block350, examines the noise associated with pairs of pins510(FIG. 5) and is further discussed with reference toFIG. 5. The third electrical check, at block350, is essentially a sanity check on the electrical inputs220. The parameters (e.g., resistance) in the electrical inputs220are compared to existing standards, which can be derived based on experience and industry knowledge. The output provided based on this check can be a file that lists parameters that are outside their respective standard values. For example, a target resistance for a particular net may be specified as 2.0 while the standard maximum resistance is 1.8. To perform this check, the processing circuitry110can compare electrical inputs220with a table of standard values according to parameter names, for example. The fourth electrical check, at block350, pertains to noise sensitivity of nets. Specifically, the check is whether a specified maximum number of adjacent pins that have a given noise requirement is exceeded. An output file can be generated to indicate pins that violate the guidelines associated with low cumulative noise tolerance nets and pairs.

FIG. 4illustrates an exemplary electrical check performed (at block350) as part of the process flow of automatically generating the design file240according to one or more embodiments of the invention.FIG. 4shows an exemplary bottom layer410with bottom pins122specified as ground pins420and signal pins430. An electrical check is performed, at block350, regarding the round-trip time between each signal pin430and the respective nearest ground pin420. Specifically, that round-trip time must not be less than a specified percentage of the rise time of the signal associated with the signal pin430. A file may be output, based on the electrical check, of signal pins430that violate the check.

For example, the distance d from a signal pin430xto the nearest ground pin420gis 3.16 millimeters (mm). Thus, the round-trip distance is double the distance d or 6.32 mm. The time-of-flight of signals is specified as, for example, 6.17 picoseconds (ps)/mm. Thus, the round-trip time between the signal pin430xand the ground pin420gis 6.17 ps/mm*6.32 mm (38.9944 ps). The specified percentage of the rise time is, for example, 30 percent, and the rise time for the signal at the signal pin430xis, for example, 130 ps. Thus, the electrical check would be whether the round-trip time (38.9944 ps) is less than 30 percent of the rise time (39 ps). Because 38.9944, the round-trip time, is less than 39, the specified percentage of the rise time, the signal pin430xcan be indicated in the output file as passing the check.

FIG. 5illustrates information used for a pin pattern placement check as one of the electrical checks, at block350, according to one or more embodiments. This check pertains to the relative arrangement of pairs of pins (121,122). An exemplary weighting factor used with each type of pin pair510is indicated. For example, the weighting factor associated with a diagonal pin pair510ais 1.2, the weighting factor associated with a side-by-side or box pin pair510bis 4.5, the weighting factor associated with a staggered pin pair510cis 1, and the weighting factor associated with an in-line pin pair510dis 2.8. The weighting factors shown inFIG. 5are exemplary values. Generally, weighting factors associated with each type of pin pair510are specified a priori based on experience and expertise.

An example that uses the exemplary weighting factors is illustrated below the exemplary types of pin pairs510. A set of pin pairs510is shown along with the weighting factor associated with each pin pair510based on its type. Lower weighting factor values indicate less noise coupling from aggressors (shown with the diagonal pattern) to victims (shown with the dotted pattern). The weighting factors are summed. In the example shown inFIG. 5, the sum of the weighting factors is 14. This sum is compared with a predefined threshold value, and an error is issued if the sum exceeds the threshold value.

FIG. 6is a process flow of fabricating a surface-mount package120that is designed according to one or more embodiments of the invention. At block610, forming a core includes forming one or more core layers. Forming dielectric layers, at block620, includes forming a first dielectric layer on either side of (e.g., above and below) the core, and forming a metal plane (MP) dielectric layer on each of the first dielectric layers. Forming a MP, at block630, is on the MP dielectric layer on either side of the core. At block640, forming additional dielectric layers is also on both sides of the core. The process at block650, of forming wire features, is part of each of the processes at blocks610through640. That is, one or more core layers, the dielectric layers, and the MP can all be formed with wire features in or on the layers. A wire feature is an electrically conductive structure (e.g., copper) and can include a via that interconnects two layers as well as a wire coplanar with the layer. Wire features on the top and bottom surfaces of the structure that is fabricated according to the processes shown inFIG. 6are the pins121,122. A power or ground plane, which is an electrically conductive structure that provides electric potential or ground to circuits within or attached to the surface-mount package120, can additionally be formed within one or more of the dielectric layers.