FUSE ELEMENT FOR PROCESS-INDUCED DAMAGE PROTECTION STRUCTURE

An integrated circuit (IC) structure includes a transistor in a device layer over a substrate, the transistor including a gate; and a plurality of interconnect layers over the device layer, the plurality of interconnect layers including a last metal layer. A process-induced damage (PID) protection structure includes a conductor coupling the gate to a well in the substrate but includes an open fuse element therein. A first metal interconnect extends from a first terminal of the open fuse element to a first pad in the last metal layer, and a second metal interconnect extending from a second terminal of the open fuse element to a second pad in the last metal layer. The fuse element is closed during fabrication, and the metal interconnects allow opening of the fuse element to deactivate the PID protection structure after fabrication.

BACKGROUND

The present disclosure relates to integrated circuits (ICs), and more particularly, to an IC structure including a fuse element for selectively disconnecting a process-induced damage protection structure.

In integrated circuit fabrication, process induced damage (PID) can occur during manufacture of certain structures, such as back-end-of-line (BEOL) interconnect layers above a first metal layer, and may reduce yield. PID can take the form of, for example, electrostatic charge that damages sensitive structures within the IC structure. Current approaches to protect against PID include adding protection structures, such as forming reverse bias diode or similar structure with a conductor coupling the transistor gate to the local substrate to direct any electrostatic charge to ground. The presence of the reverse bias diode in the final IC product presents other challenges such as increased parasitic harmonics based on its non-linear operation and an inability to use the transistor in a reverse mode, e.g., for an n-type field effect transistor (nFET), where pulling the gate negative will forward bias the diode. Where a reverse bias diode is not possible, design rule restrictions create limited viable options relative to changing other structure. For example, one approach attempts to adjust total metal area versus oxide area (i.e., metal via, line and/or gate area versus oxide area) to protect against PID. The changing of structures within an IC structure disadvantageously adds restrictions to the design and performance of the final product. Other approaches attempt to control fabrication tools to reduce PID with limited efficacy.

SUMMARY

All aspects, examples and features mentioned below can be combined in any technically possible way.

An aspect of the disclosure provides an integrated circuit (IC) structure, comprising: a transistor in a device layer over a substrate, the transistor including a gate; a plurality of interconnect layers over the device layer, the plurality of interconnect layers including a last metal layer; the gate coupled by a conductor to a well in the substrate but including an open fuse element therein; a first metal interconnect extending from a first terminal of the open fuse element to a first pad in the last metal layer; and a second metal interconnect extending from a second terminal of the open fuse element to a second pad in the last metal layer.

Another aspect of the disclosure includes any of the preceding aspects, and the first terminal, the second terminal and a portion of the conductor are in a first metal layer of the plurality of interconnect layers.

Another aspect of the disclosure includes any of the preceding aspects, and the first metal interconnect and the first terminal are on a first side of the open fuse element closest to the gate, and the second metal interconnect and the second terminal are on a second side of the open fuse element farther from the gate than the first metal interconnect and the first terminal, wherein a voltage applied to the second pad created the open fuse element.

Another aspect of the disclosure includes any of the preceding aspects, and the voltage applied to the second pad is a positive voltage.

Another aspect of the disclosure includes any of the preceding aspects, and the well includes an n-well in the substrate.

Another aspect of the disclosure includes any of the preceding aspects, and the conductor includes a metal wire in a first metal layer of the plurality of interconnect layers, and a conductive via coupling the metal wire to the substrate.

Another aspect of the disclosure relates to a process-induced damage (PID) protection structure for an integrated circuit (IC) structure, the PID protection structure comprising: a transistor in a device layer over a substrate, the transistor including a gate; the gate coupled by a conductor to a well in the substrate and including a fuse element therein a first metal interconnect extending from a first terminal of the fuse element through a plurality of interconnect layers over the device layer to a first pad in a last metal layer; and a second metal interconnect extending from a second terminal of the fuse element through the plurality of interconnect layers over the device layer to a second pad in the last metal layer, wherein the fuse element is in an open state.

Another aspect of the disclosure includes any of the preceding aspects, and the first terminal, the second terminal and a portion of the conductor are in a first metal layer of the plurality of interconnect layers.

Another aspect of the disclosure includes any of the preceding aspects, and the first metal interconnect and the first terminal are on a first side of the open fuse element closest to the gate, and the second metal interconnect and the second terminal are on a second side of the open fuse element farther from the gate than the first metal interconnect and the first terminal.

Another aspect of the disclosure includes any of the preceding aspects, and the voltage applied to the second pad is a positive voltage.

Another aspect of the disclosure includes any of the preceding aspects, and the well includes an n-well in the substrate.

Another aspect of the disclosure includes any of the preceding aspects, and the conductor includes a metal wire in a first metal layer of the plurality of interconnect layers, and a conductive via coupling the metal wire to the well in the substrate.

Another aspect of the disclosure includes any of the preceding aspects, and the PID protection structure is a reverse bias diode.

Another aspect includes a method, comprising: forming a process-induced damage (PID) protection structure including a transistor including a gate in a device layer over a substrate, and a conductor connecting the gate to a well in the substrate, the conductor including a fuse element therein; forming a plurality of interconnect layers over the device layer, the plurality of interconnect layers including a last metal layer, wherein forming the plurality of interconnect layers includes forming: a first metal interconnect extending from a first terminal of the fuse element to a first pad in the last metal layer, and a second metal interconnect extending from a second terminal of the fuse element to a second pad in the last metal layer; and after forming the last metal layer, applying a voltage to the second pad to disconnect the fuse element, creating an open fuse element.

Another aspect of the disclosure includes any of the preceding aspects, and the first terminal, the second terminal and a portion of the conductor are in a first metal layer of the plurality of interconnect layers.

Another aspect of the disclosure includes any of the preceding aspects, and the first metal interconnect and the first terminal are on a first side of the open fuse element closest to the gate, and the second metal interconnect and the second terminal are on a second side of the open fuse element farther from the gate than the first metal interconnect and the first terminal, wherein the voltage is not applied to the gate.

Another aspect of the disclosure includes any of the preceding aspects, and the fuse element is placed in the open state by applying a positive voltage to the second pad.

Another aspect of the disclosure includes any of the preceding aspects, and the well includes an n-well in the substrate.

Another aspect of the disclosure includes any of the preceding aspects, and the conductor includes a metal wire in a first metal layer of the plurality of interconnect layers, and a conductive via coupling the metal wire to the substrate.

Another aspect of the disclosure includes any of the preceding aspects and creating the open fuse element deactivates the PID protection structure.

Two or more aspects described in this disclosure, including those described in this summary section, may be combined to form implementations not specifically described herein.

DETAILED DESCRIPTION

Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.

Embodiments of the disclosure includes an integrated circuit (IC) structure including a transistor in a device layer over a substrate, the transistor including a gate. A plurality of interconnect layers, e.g., middle-of-line (MOL) and/or back-end-of-line (BEOL) layers, are over the device layer and include a last metal layer. A deactivated process-induced damage (PID) protection structure includes a conductor coupling the gate to a well in the substrate but includes an open fuse element therein, i.e., a fuse element in an open state. A first metal interconnect extends from a first terminal of the open fuse element to a first pad in the last metal layer, and a second metal interconnect extending from a second terminal of the open fuse element to a second pad in the last metal layer. The fuse element is closed during fabrication allowing the PID protection structure to operate as intended. After fabrication, the metal interconnects allow opening of the fuse element to deactivate the PID protection structure. The teachings of the disclosure allow use of a PID protection structure(s) while eliminating the non-ideal consequences, such as parasitic impedance, capacitance, inability to operate devices in accumulation (reverse bias mode), when the PID protection structure(s) remain in the final product.

FIG.1shows a cross-sectional view of an intermediate IC structure100including a PID protection structure102, after fabrication, andFIG.2shows a schematic view of PID protection structure102, according to embodiments of the disclosure. Intermediate IC structure100and PID protection structure102may include a transistor110in a device layer112over a substrate114. Transistor110may include any now known or later developed metal-oxide semiconductor field effect transistor (MOSFET). Transistor110includes a gate116. Gate116may take any polyconductor form, e.g., metal gate or polysilicon. Transistor110may also include source/drain regions118formed within a well120in substrate. Well120can take either polarity, i.e., n-type or p-type, but will be referenced as n-type for purposes of description. Transistor110may be isolated from other devices by trench isolations122.

Intermediate IC structure100includes a plurality of interconnect layers130over device layer112. Plurality of interconnect layers130may include any number of MOL and/or BEOL layers and includes a last metal layer LM. Each layer130includes a dielectric material, e.g., oxide, having interconnects such as metal wires, e.g., copper, aluminum, etc., running laterally therethrough or metal contacts, e.g., tungsten, running vertically therethrough. Appropriate refractory metal liner(s) (not shown) such as tantalum, titanium nitride, etc., may line the metal wires and contacts to prevent electromigration. Only some of layers130are shown as indicated by the vertical dashed lines. Intermediate IC structure100, as shown inFIG.1, can be formed using any now known or later developed semiconductor fabrication techniques.

Intermediate IC structure100and PID protection structure102thereof may also include a conductor140coupling gate116to well120in substrate114. As shown inFIG.2, conductor140from gate116to well120, e.g., n-well, of substrate114creates a reverse bias diode148. That is, PID protection structure102is a reverse bias diode148. Diode148protects transistor110from process induced damage during fabrication, such as electrostatic discharge or related damage.FIG.1shows intermediate IC structure100after fabrication. Conductor140can include any number of metal wires in first metal layer M1of plurality of interconnect layers130, and/or contacts necessary to couple gate116to well120. More specifically, conductor140includes a metal wire142in a first metal layer M1, and one or more conductive via(s)144coupling metal wire142to substrate114, e.g., well120. Conductor140may also include one or more conductive via(s)146for coupling metal wire142to gate116. Conductive via(s)144,146may be in a local interconnect layer VO. Metal wire142and conductive via(s)144,146may include any of the afore-described materials for layers130.

In accordance with embodiments of the disclosure, conductor140of PID protection structure102also includes a fuse element150therein. Fuse element150can include any now known or later developed fusing structure, such as but not limited to a thinner portion within metal wire142capable of disconnection upon application of a threshold voltage. While shown as a vertically narrowed structure, fuse element150can be alternatively, or in addition thereto, narrowed in a lateral direction (into and out of page). First terminal162, second terminal172of fuse element150and a portion of conductor140, e.g., metal wire142, are in first metal layer M1.

Intermediate IC structure100and PID protection structure102also include a first metal interconnect160extending from a first terminal162of fuse element150to a first pad164in last metal layer LM, and a second metal interconnect170extending from a second terminal172of fuse element150to a second pad174in last metal layer LM. First metal interconnect160and first terminal162are on a first side of fuse element150closest to gate116, and second metal interconnect170and second terminal172are on a second side of fuse element150farther from gate116than first metal interconnect160and first terminal162. Each metal interconnect160,170may include any number of metal wires and contacts arranged in any manner extending through interconnect layers130. In certain embodiments, contacts of metal interconnects160,170include a minimal area contact to minimize metal area versus oxide area to protect against PID. Each pad164,174is accessible in last metal layer LM for application of a voltage thereto from any now known or later developed voltage source180.

A method according to embodiments of the disclosure may include forming intermediate IC structure100and PID protection structure102. As described, PID protection structure102may include transistor110including gate116in device layer112over substrate114, and conductor140connecting gate116to well120in substrate114. Conductor140includes fuse element150therein. As understood, intermediate IC structure100may include a large and wide variety of other integrated circuit elements (not shown) such as but not limited to other transistors, capacitors, and resistors, that collectively form an integrated circuit.

A method may also include forming a plurality of interconnect layers130over device layer112. Layers130include last metal layer LM. Forming layers130also include forming first metal interconnect160extending from first terminal162of fuse element150to first pad164in last metal layer LM, and second metal interconnect170extending from second terminal172of fuse element150to second pad174in last metal layer LM. Any number of layers130may be formed. Intermediate IC structure100and PID protection structure102may be formed using any now known or later developed semiconductor fabrication techniques. During the fabrication process, PID protection structure102protects transistor110and other structure from process induced damage such as but not limited to electrostatic discharge and related. PID protection structure102protects transistor110by grounding gate116thereof to substrate114, e.g., n-well120, directing any damaging electric current into substrate during fabrication.

After forming last metal layer LM, a voltage is applied, i.e., by voltage source180, to second pad174to disconnect fuse element150, creating an open fuse element190. That is, fuse element190is in an open, non-conducting state.FIG.3shows a cross-sectional view of IC structure200including deactivated PID protection structure202, andFIG.4shows a schematic view of deactivated PID protection structure202, after disconnecting fuse element150(FIGS.1-2), according to embodiments of the disclosure. Fuse element150(FIGS.1-2) may be disconnected (e.g., blown) by applying a positive voltage to second metal interconnect170, second terminal172of fuse element150and to well120via second pad174. Similarly, a negative voltage is consequently applied to first metal interconnect160, first terminal162of fuse element150and to gate116via first pad164. Hence, gate116and transistor110are at negative/ground voltage protecting them from damage during deactivation of PID protection structure102(FIGS.1-2). Voltage source180is used to apply the voltages to first and second pads164,174. Creating open fuse element190disconnects gate116from well120and creates IC structure200with deactivated PID protection structure202(FIGS.3-4).

With reference toFIGS.3and4, IC structure100including deactivated PID protection structure202are shown in the way they exist in a final product, according to embodiments of the disclosure. IC structure200and deactivated PID protection structure202may include transistor110in device layer112over substrate114. As noted, transistor110may include any now known or later developed metal-oxide semiconductor field effect transistor (MOSFET). Transistor110also includes gate116. As noted, gate116may take any polyconductor form, e.g., metal gate or polysilicon. Transistor110may also include source/drain regions118formed within well120in substrate. Well120can take either polarity, i.e., n-type or p-type, but has been referenced herein as n-type. IC structure200includes a plurality of interconnect layers130over device layer112, as described herein. As noted, plurality of interconnect layers130may include any number of MOL and/or BEOL layers and includes last metal layer LM.

IC structure200and deactivated PID protection structure202may include conductor140coupling gate116to well120in substrate114, i.e., but for open fuse element190. Conductor140can include any number of metal wires in first metal layer M1, and/or contacts necessary to couple gate116to well120. More specifically, conductor140includes metal wire142in first metal layer M1, and conductive via(s)144,146coupling metal wire142to substrate114, e.g., well120. Conductive via(s)144,146may be in local interconnect layer VO. In accordance with embodiments of the disclosure, conductor140also includes open fuse element190therein. In this manner, PID protection structure102(FIGS.1-2) is no longer active. First terminal162, second terminal172of fuse element190and a portion of conductor140, e.g., metal wire142, are in first metal layer M1.

IC structure200and deactivated PID protection structure202also include first metal interconnect160extending from first terminal162of open fuse element190to first pad164in last metal layer LM, and second metal interconnect170extending from second terminal172of open fuse element190to second pad174in last metal layer LM. First metal interconnect160and first terminal162are on a first side of open fuse element190closest to gate116, and second metal interconnect170and second terminal172are on a second side of open fuse element190farther from gate116than first metal interconnect160and first terminal162. As noted, each metal interconnect160,170may include any number of metal wires and contacts arranged in any manner extending through interconnect layers130.

Embodiments of the disclosure provide various technical and commercial advantages, examples of which are discussed herein. For example, embodiments of the disclosure use a PID protection structure102during fabrication, but only provides the deactivated PID protection structure in the final product. Hence, a quality PID protection structure can be used during fabrication, while also eliminating the non-ideal consequences such as parasitic impedance, capacitance, inability to operate devices in accumulation (reverse bias mode), where the PID protection structure remains in the final product. The teachings of the disclosure also provide a simple and low-cost solution that does not require additional considerations relative to design rules and performance of the final product.