Method of and apparatus for reducing current of semiconductor memory device

A clock generator circuit of a dynamic random access memory (RAM) comprises a power-on reset circuit and an NOR gate conneced to a row address strobe (RAS) terminal and the reset circuit. In operation, the power-on reset circuit generates a one-shot pulse immediately after the power supply is turned on. During a period of a pulse width of the one-shot pulse, this clock generator circuit operates as if it receives a high-level row address strobe (RAS) signal and, as a result, it is possible to reduce an excessive current flowing into the dynamic random access memory (RAM) at the time of turning on the power supply.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates generally to semiconductor memory devices, 
and more particularly, a method of and an apparatus for reducing current 
flow from a power supply into a memory device immediately after the power 
supply is turned on. 
2. Description of the Prior Art 
FIG. 1 is a block diagram showing a memory board generally employed in 
apparatuses utilizing computers. Referring to FIG. 1, the memory board 40 
comprises a number of memory chips 1 for storing data signals and a 
control circuit 41 for controlling the memory chip 1. The memory chip 1 is 
connected to receive voltage from an external power supply Vcc.sub.1 
through a terminal 42 and the control circuit 41 is connected to receive a 
voltage from another external power supply Vcc.sub.2 through a terminal 
43. The control circuit 41 generates a RAS (Row Address Strobe) signal, a 
CAS (Column Address Strobe) signal and address signals, and controls 
reading/writing of the memory chip 1 based on instructions from a CPU 
(Central Processing Unit). 
In order to supply power to the memory chip 1 and the control circuit 41, 
different power supplies Vcc.sub.1 and Vcc.sub.2 such as shown in FIG. 1 
are utilized, or a common power supply is utilized. For example, if a 
backup power supply for a memory chip 1 is used, two different supply 
voltages are applied. In either case, the level (high or low) of the RAS 
signal applied to the memory chip 1 depend on the system when the power is 
turned on. 
FIG. 2 is a block diagram showing a conventional 1 M-bit dynamic RAM 
(Random Access Memory Device). The dynamic RAM such as shown in FIG. 1 is 
disclosed in "A reliable 1-M bit DRAM with a multi-bit-test mode" by M. 
Kumanoya et al., 1985 (IEEE Journal Solid-State Circuits, vol. SC-20, pp. 
909-913) and also in "A Fast 256K.times.4 CMOS DRAM with a Distributed 
Sense and Unique Restore Circuits" by H. Miyamoto et al., 1987 (IEEE 
Journal Solid-State Circuits, vol. SC-22, pp. 861-867). 
Referring to FIG. 2, the dynamic RAM comprises a clock generator circuit 10 
for outputting clock signals .phi..sub.1 and .phi..sub.2 which control 
this dynamic RAM in response to a CAS signal and a RAS signal. The CAS 
signal and the RAS signal are externally applied through a CAS terminal 8 
and a RAS terminal 4, respectively. A power supply Vcc (5 V) and the 
ground Vss (0 V) are externally applied through a power supply terminal 2 
and a ground terminal 3, respectively. 
FIG. 3 is a timing chart showing the change of the current to be consumed 
in the dynamic RAM. Referring to FIG. 3, the dynamic RAM has two states of 
operation, that is, standby state and active state. The dynamic RAM is 
brought to the standby state when a high level RAS signal is applied, 
while it is brought to the active state when a low level RAS signal is 
applied. As is apparent from the figure, the current Icc to be consumed 
flowing from the power supply (Vcc shown in FIG. 2) changes dependent on 
the state of operation of the dynamic RAM. 
In the standby state, an approximately constant current I.sub.2 of about 
1.about.3 mA flows from the power supply Vcc to the dynamic RAM. (The 
reason for this will be described later.) 
Immediately after the change of the RAS signal from high level to low 
level, the dynamic RAM is brought to the active state and a transient 
current I.sub.a flows. The current I.sub.a mainly comprises a charging 
current for activating the clock generator circuit 10 and an operating 
current for operating the row address buffer 21 and the row decoder 22 in 
FIG. 2. After 30.about.50 n sec from the change of the RAS signal to the 
low level, a transient current I.sub.b flows. The current I.sub.b is 
consumed by the sense amplifier 24 to charge bit lines in the memory array 
25. The bit line charging operation by the sense amplifier 24 in the 
active state will be described in detail later. 
When the current I.sub.b is decreased, a constant current I.sub.4 flows to 
activate the data output buffer 27. The current I.sub.4 is less than 10 mA 
in a normal state. 
Thereafter, immediately after the change of the RAS signal from the low 
level to the high level, the dynamic RAM returns to the standby state and 
a transient current I.sub.c flows. The current I.sub.c mainly comprises a 
current for bringing the clock generator circuit 10 to the standby state 
and a current for bringing the row address buffer 21 and the row decoder 
22 to the standby state. 
FIG. 4 is a schematic diagram showing the clock generator circuit of the 
dynamic RAM in FIG. 2. Referring to FIG. 4, the clock generator circuit 10 
comprises a buffer circuit connected to a RAS terminal 4 and a inner 
circuit 11 connected between a power supply Vcc and the ground Vss for 
outputting clock signals .phi..sub.1 and .phi..sub.2 in response to a 
signal from the buffer circuit. The buffer circuit comprises two inverters 
5a and 5b connected in series. A reference character Icc represents 
consumed current flowing from the power supply Vcc to a dynamic RAM 1. 
In general, for a circuit receiving an input signal from the outside, a 
buffer circuit connected to an input terminal comprises inverters. For 
example, a buffer circuit employing inverters is described by Neil H. E. 
Weste et al. in "PRINCIPLES OF CMOS VLSI DESIGN", pp. 227-229, published 
by ADDISON-WESLEY PUBLISHING COMPANY in 1985. 
A description is made of operation which occurs when the supply voltage Vcc 
is externally applied to the dynamic RAM in FIG. 4. 
FIGS. 5 and 6 are timing charts showing a change of signals for explaining 
the operation of the dynamic RAM in FIG. 4. Referring to FIGS. 5 and 6, 
the supply voltage Vcc starts to be applied to the terminal 2 from a time 
t.sub.1 and the applied voltage rises up to a predetermined voltage level. 
When the applied voltage reaches the predetermined voltage level, it will 
not change thereafter. 
FIG. 5 shows the case in which a high-level RAS signal is applied to the 
RAS terminal 4 before the time t.sub.1. The dynamic RAM is in the standby 
state when the RAS signal is at high level and it is in the active state 
when the RAS signal is at low level. Power consumption is small when the 
dynamic RAM is in the standby state and it is large when the dynamic RAM 
is in the active state. Therefore, the supply voltage Vcc (for example 5 
V) is applied to the dynamic RAM while the dynamic RAM is in the standby 
state in FIG. 5. As a result, after the current Icc flowing into the 
dynamic RAM reaches its small peak value of I.sub.1 (several mA) at a time 
t.sub.2, the value is reduced to I.sub.2 which is smaller than I.sub.1, 
and then stabilized. The value of I.sub.2 is a current value necessary for 
operation in the standby state. The reason why these different values flow 
will be described in the following. 
FIG. 7 is a schematic diagram showing a buffer circuit in the clock 
generator circuit 10 shown in FIG. 4. Referring to FIG. 7, the buffer 
circuit comprises two inverters 5a and 6a. The inverter 5a comprises a 
series connection of a P channel MOS transistor Q1 and an N channel MOS 
transistor Q2 connected between the power supply Vcc and the ground Vss. 
The gates of the transistors Q1 and Q2 are connected together and the RAS 
signal is applied thereto. The inverter 5b also comprises a P channel MOS 
transistor Q3 and an N channel MOS transistor Q4 connected in a similar 
manner as the inverter 5a. The gates of the transistors Q3 and Q4 are 
connected together to the output of the inverter 5a. A stray capacitance 
C10 exists between the output node N10 of the inverter 5a and the ground 
Vss, and a stray capacitance C11 exists between the output node N11 of the 
inverter 5b and the ground Vss. 
FIG. 8 is a timing chart showing the change of the voltage at output nodes 
of two inverters shown in FIG. 7 when the power supply Vcc rises. 
Referring to FIGS. 7 and 8, the nodes N10 and N11 are at 0 V before the 
voltage of the power supply Vcc rises. When the power supply Vcc rises 
after a high level RAS signal is applied, the output node N10 of the 
inverter 5a remains at 0 V. Meanwhile, the output node N11 of the inverter 
5b is brought to a high level voltage, so that the stray capacitance C11 
existing between the node N11 and the ground Vss is charged. Therefore, a 
charging current flows from the power supply Vcc. 
Various peripheral circuits are provided in the dynamic RAM as shown in 
FIG. 2, each of which comprising, in most cases, circuits such as shown in 
FIG. 7. As described above, immediately after the power supply Vcc is 
turned on, charging currents for charging stray capacitances in these 
circuits flow in, causing a peak current I.sub.1 at the time t.sub.2 shown 
in FIG. 5. 
Referring again to FIG. 7, the current I.sub.2 of a constant value consumed 
after the time t.sub.2 will be described. The current I.sub.2 corresponds 
to the current I.sub.2 from the power supply Vcc which is shown in FIG. 3. 
Generally, the RAS signal has a voltage level called TTL (Transistor 
Transistor Logic) level. More specifically, the high level of the RAS 
signal is about 2.4 V when the power supply Vcc is 5 V. The transistor Q2 
turns on in response to a high level RAS signal applied between the gate 
and the source thereof. Meanwhile, the transistor Q1 receives 
approximately -2.6[=-(Vcc-2.4)]V between the gate and the source thereof, 
and turns on. Therefore, both transistors Q1 and Q2 turn on and a current 
flows from the power supply Vcc to the ground Vss. This current is 
included in the current I.sub.2 shown in FIG. 5, which flows constantly. 
In addition, a current which will be described in the following is also 
included in the current I.sub.2. 
FIG. 9 is a schematic diagram showing a ring oscillator provided for 
generating negative voltage in the dynamic RAM. Referring to FIG. 9, the 
ring oscillator comprises an odd-number of inverters 29 which is connected 
in series to form a ring. A pulsating current which fluctuates in several 
mega-hertz frequency flows into the ring oscillator from the power supply 
Vcc. Since this current is of high frequency, it seems as a direct current 
and is included in the current I.sub.2 shown in FIG. 5. 
On the other hand, the timing chart of the FIG. 6 shows the case in which 
the supply voltage Vcc starts to be applied to the dynamic RAM from the 
time t.sub.1, while the RAS signal is low level. Since the supply voltage 
Vcc is applied to the RAM chip while the RAM chip is in the active state, 
the current Icc after the time t.sub.1 is increased. At this time, since 
each node of circuits in the dynamic RAM has not been necessarily brought 
to a predetermined high or low level, excessive current Icc flows therein. 
As a result, after the current Icc reaches its big peak value of I.sub.3 
(several tens of mA) which is bigger than the value of I.sub.1 at the time 
t.sub.3, it is reduced to the value of I.sub.4 (below 10 mA) which is 
considerably smaller than the value of I.sub.3, and then stabilized. The 
value of I.sub.4 is a current value necessary for operation in the active 
state, which is the same as that shown in FIG. 3. 
A description is made of the reason for the inflow of the excessive current 
hereinafter. 
FIG. 10 is a schematic diagram showing an example of portions of the sense 
amplifier 24 and the memory array 25 of the dynamic RAM shown in FIG. 2. 
Referring to FIG. 10, the sense amplifier 24 comprises two latch circuits 
connected between a bit line 241 and a bit line 242. One latch circuit is 
constituted by N channel MOS transistors Q10 and Q11 and is connected to 
the ground Vss through an N channel MOS transistor Q12. The other circuit 
is constituted by P channel MOS transistors Q13 and Q14 and is connected 
to the power supply Vcc through a P channel MOS transistor Q15. The gates 
of the transistors Q12 and Q15 are connected such that they receive sense 
signals .phi..sub.s and .phi..sub.s respectively, which signals are 
inverted from each other. 
The memory array 25 is connected to the sense amplifier 24 through the bit 
lines 241 and 242. Memory cells MC each consisted of one N channel MOS 
transistor and a capacitor are connected between the bit line 241 or 242 
and the word line 243. There are stray capacitances C.sub.B1 and C.sub.B2 
between respective bit lines 241 and 242 and the ground Vss. 
FIG. 11 is a timing chart showing the operation of a circuit shown in FIG. 
10 when the power supply Vcc rises after a high level RAS signal is 
applied (in this case, it corresponds to the case shown in FIG. 5). 
Referring to FIGS. 10 and 11, the bit lines 241 and 242 are at 0 V before 
the power supply Vcc rises. When a high level RAS signal is applied and 
the power supply Vcc rises, a sense signal .phi..sub.s of 0 V is applied 
to the gate of the transistor Q12. Therefore, the transistor Q12 remains 
off. Meanwhile, a sense signal .phi..sub.s which goes to a high level from 
0 V simultaneously with the rise of the power supply Vcc is applied to the 
gate of the transistor Q15. Therefore, the transistor Q15 also remains 
off. Since both transistors Q12 and Q15 are off, the stray capacitances 
C.sub.B1 and C.sub.B2 are not charged. That is, the bit lines 241 and 242 
are not charged by the power supply Vcc, and no current flows in from the 
power supply Vcc. 
FIG. 12 shows a timing chart in which the power supply Vcc rises while the 
RAS signal remains at low level (corresponding to the case shown in FIG. 
6). Referring to FIGS. 10 and 12, the bit lines 241 and 242 are at 0 V 
before the rise of the power supply Vcc. A sense signal .phi..sub.s which 
has risen to a high level from 0 V simultaneously with the rise of the 
power supply Vcc is applied to the gate of the transistor Q12. Therefore, 
the transistor Q12 turns on. Meanwhile, a sense signal .phi..sub.s of 0 V 
is applied to the transistor Q15, and the transistor Q15 also turns on. 
Since both transistors Q12 and Q15 are turned on, current flows into the 
bit lines 241 and 242 from the power supply Vcc through the transistor Q15 
and to the ground Vss through the transistor Q12. The voltages at the bit 
lines 241 and 242 are slightly increased from 0 V due to this current. On 
this occasion, a through current flows from the power supply Vcc to the 
ground Vss through the transistor Q15, Q13 or Q14, Q10 or Q11, and Q12. 
Thereafter, since the sense amplifier 24 comprises two latch circuits as 
described above, the bit line 241, for example, is brought to a high level 
and the bit line 242 is brought to a low level. Which of the two bit lines 
241 and 242 is brought to the high level is determined by a slight 
imbalance between the stray capacitances C.sub.B1 and C.sub.B2 having 
approximately the same capacitance value. Since one of the two bit lines 
241 and 242 is charged by the power supply Vcc, a charging current flows 
into the dynamic RAM from the power supply Vcc. Generally, one stray 
capacitance C.sub.B1 or C.sub.B2 has a value less than 0.4 pF. Therefore, 
in a case of 1 mega-bit dynamic RAM, for example, 2048 stray capacitances 
are charged, with the total capacitance value being 819 pF (=0.4 
pF.times.2048). A current for charging the total capacitance is included 
in the current I.sub.3 shown in FIG. 6. 
The current I.sub.3 shown in FIG. 6 comprises the following current besides 
the above described through current and the charging current from the 
power supply Vcc. Referring again to FIG. 7, when the power supply Vcc 
rises with the RAS signal being low level, the output node N10 of the 
inverter 5a is brought to a high level voltage from 0 V. Therefore, the 
stray capacitance C10 existing between the node N10 and the ground Vss is 
charged by the power supply Vcc and a charging current flows in from the 
power supply Vcc. As described above, the dynamic RAM comprises a number 
of circuits such as shown in FIG. 7 and such charging currents are 
included in the current I.sub.3 shown in FIG. 6. 
Meanwhile, the constant current I.sub.4 which flows after the time t.sub.3 
corresponds to the current I.sub.4 of the timing chart shown in FIG. 3. 
As described above, in the conventional dynamic RAM, the excessive current 
I.sub.3 (for example 50 mA) from the power supply Vcc flows in when the 
power supply Vcc is turned on. Because of this excessive current I.sub.3, 
power supply capacity could be insufficient, so that other circuits could 
not operate correctly or the line fuse could be blown. In addition, the 
heat produced by this excessive current could cause a malfunction of the 
dynamic RAM. 
SUMMARY OF THE INVENTION 
One object of the invention is to reduce excessive current flowing in a 
semiconductor memory device, when power is first turned on. 
Another object is to reduce excessive current in a dynamic RAM, when power 
is first turned on. 
Another object is to reduce excessive current in a dynamic RAM having first 
and second operating states, when power is fist turned on. 
Yet another object is to reduce excessive current in a dynamic RAM having 
active and standby operating states, when power is first turned on. 
Still another object is to reduce excessive current in a dynamic RAM having 
active and standby operating states, wherein the DRAM has a tendency to be 
in the active state, when power is first applied. 
Another object of the invention is to improve the reliability of 
semiconductor memory devices. 
Still another object is to reduce power supply requirements in a 
semiconductor memory device system. 
Yet another object is to prevent damage to semiconductor memory devices as 
a result of excessive current flow therethrough when power is first 
applied. 
Briefly stated, the present invention comprises a first control circuit 
responsive to an external control signal for controlling a semiconductor 
memory device to operate selectively in a first operating state and a 
second operating state which state consumes less current; a detector 
circuit for detecting an application of power to the memory device; a 
generating circuit responsive to the detector circuit for generating a 
pseudo-state signal defining the second operating state of the memory 
device; and a second control circuit responsive to the external control 
signal or said pseudo-state signal for operating the memory device in the 
second operating state. 
In operation, a pseudo-state signal is generated immediately after the 
application of power. The memory device operates in the second operating 
state responsive to the pseudo-state signal, thereby reducing current 
consumption. 
In a preferred embodiment, the present invention is applied to a dynamic 
random access memory (RAM). Therefore, the current consumed by the dynamic 
RAM after the application of power can be reduced. 
In another preferred embodiment, a power on reset pulse generating circuit 
is applied as a circuit for generating the pseudo-state signal. Therefore, 
a pseudo-state signal generating circuit can be readily obtained. 
In another aspect, the present invention is a method for operating a 
semiconductor memory device comprising a first control circuit responsive 
to an external control signal for operating the memory device selectively 
in a first operating state and a second operating state which state 
consumes less current, comprising the steps of: detecting application of 
power to the memory device; generating a pseudo-state signal responsive to 
the application of power to the memory device, which signal defining the 
second operating state; and operating the memory device in the second 
operating state responsive to the external control signal or to the 
pseudo-state signal. 
In operation, the pseudo-state signal is generated immediately after the 
application of power. The memory device operates in the second operating 
state in response to the pseudo-state signal, thereby reducing current 
consumption. 
In accordance with a preferred embodiment in this suspect, the method is 
applied to a dynamic RAM. Therefore, the current consumed by the DRAM 
after the application of power can be reduced. 
These objects and other objects, features, aspects and advantages of the 
present invention will become more apparent from the following detailed 
description of the present invention when taken in conjunction with the 
accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 13 is a schematic diagram showing one embodiment of a clock generator 
circuit of a dynamic RAM in accordance with the present invention. 
Referring to FIG. 13, the clock generator circuit 10 comprises a buffer 
circuit connected to a RAS terminal 4 and an inner circuit 11 for 
outputting clock signals .phi..sub.1 and .phi..sub.2 in response to an 
output signal from the buffer circuit. The buffer circuit comprises an NOR 
gate 7 and an inverter 5b connected in series, and a power-on reset 
circuit 6. One input of the NOR gate 7 is connected to the RAS terminal 4 
and the other input is connected to receive an output signal POR of the 
power-on reset circuit 6. The output of the NOR gate 7 is connected to the 
input of the inverter 5b. The output of the inverter 5b is connected to 
the inner circuit 11. Since the other circuits except for the buffer 
circuit are the same as the conventional circuit shown in FIG. 4, a 
description thereof is omitted. 
Next, a description is made of operation of the circuit. 
FIGS. 14 and 15 are timing charts showing a change of signals for 
explaining operation of the dynamic RAM of FIG. 13. Referring to FIGS. 14 
and 15, a supply voltage Vcc starts to be applied to the terminal 2 from a 
time t.sub.1 and the applied voltage rises to a predetermined voltage 
level. When the applied voltage reaches the predetermined voltage, the 
voltage will not change thereafter. After the supply voltage Vcc is 
applied, a one-shot pulse signal POR having a predetermined pulse width is 
outputted from the power-on reset circuit 6. 
FIG. 14 shows the case in which a high-level RAS signal is applied to the 
terminal 4 before the time t.sub.1. The RAS signal is applied to the inner 
circuit 11 through the NOR gate 7. The RAS signal and the one-shot pulse 
POR are applied to the NOR gate 7, but in this case, the output signal of 
the NOR gate 7 is not affected by this pulse POR. Therefore, like in the 
case of FIG. 5, the supply voltage Vcc is applied while the RAM chip 1 is 
in the standby state. As a result, the current Icc flowing from the power 
supply Vcc to the dynamic RAM reaches its small peak value of I.sub.1 
(several mA) at the t.sub.2, the value is reduced to I.sub.2 which is 
smaller than I.sub.1, and then stabilized. The value of I.sub.2 is the 
current value necessary for operation in the standby state. 
On the other hand, the timing chart of FIG. 15 shows the case in which a 
supply voltage Vcc starts to be applied to the dynamic RAM from the time 
t.sub.1, while the RAS signal is low level. When the dynamic RAM is in the 
active state, the supply voltage Vcc starts to be applied from the time 
t.sub.1. A one-shot pulse POR is generated immediately after the supply 
voltage Vcc is applied and it is applied to the other input of NOR gate 7. 
The dynamic RAM is brought to the standby state during a period of time of 
a pulse width (until a time t.sub.4) for a short time by this pulse POR. 
Therefore, during this short standby period, after the current Icc flowing 
into the dynamic RAM reaches its small peak value of I.sub.1 (several mA) 
at the time t.sub.2, it is reduced to the value of I.sub.2 which is 
smaller than I.sub.1, and then stabilized. Next, since the pulse POR 
changes to low level at the time t.sub.4, the dynamic RAM is brought to 
the active state. When the dynamic RAM becomes the active state, the 
current Icc of a peak values of I.sub.a and I.sub.b which are considerably 
smaller than the current value of I.sub.3 in FIG. 6 flows in and the 
current Icc is reduced to the value of I.sub.4 which is smaller than 
I.sub.a and I.sub.b, and then stabilized. The value of I.sub.4 is a 
current value necessary for operation in the active state. 
As described above, since the dynamic RAM is brought to the active state 
after it is brought to the standby state for a short time by the one-shot 
pulse POR, the inflow of the excessive current I.sub.3 shown in FIG. 6 can 
be prevented. 
FIG. 16 is a schematic diagram showing another embodiment of the clock 
generator circuit of a dynamic RAM in accordance with the present 
invention. 
Referring to FIG. 16, as compared with the circuit diagram of FIG. 13, the 
clock generator circuit in FIG. 16 further comprises an NOR gate 9 having 
its one input connected to a CAS terminal 8 and an inverter 5c connected 
in series. The other input of the NOR gate 9 is connected to a power-on 
reset circuit 6. The output of the NOR gate 9 is connected to an inner 
circuit 11 through the inverter 5c. Since the other circuit portions are 
the same as those of the clock generator circuit of FIG. 13, a description 
thereof is omitted. 
In operation, like the circuit controlled by the above described RAS 
signal, the circuit controlled by the CAS signal has a decrease in the 
inflow of an excessive current for a moment immediately after the supply 
voltage Vcc is applied. 
FIG. 17 is a schematic diagram showing one example of a power-on reset 
circuit employed in the clock generator circuit in accordance with the 
present invention shown in FIGS. 13 and 16. 
Referring to FIG. 17, the power-on reset circuit comprises a resistor R and 
a capacitor C connected in series between a power supply Vcc and the 
ground Vss and three inverters 31, 32 and 33 connected in series to an 
intersecting point of the resistor R and the capacitor C. A one-shot pulse 
POR is outputted from the inverter 33 of the last stage. A resistor value 
"R" of the resistor R and a capacitance value "C" of the capacitor C are 
selected so that the product of both values (that is time constant "RC") 
may be bigger than a rise time of power supply Vcc. Nodes N1, N2 and N3 
represent input points of the inverter 31, 32 and 33, respectively. A node 
N4 represents an output point of the inverter 33. 
FIG. 18 is a timing chart for explaining operation of the power-on reset 
circuit of FIG. 17. Referring to FIG. 18, a description is made of 
operation of the power-on reset circuit of FIG. 17. 
At the time s1, a voltage of the power supply Vcc starts to increase from 0 
V to a voltage value of Vcc. A voltage of the node N1 also starts to 
increase in accordance with the time constant "RC". The time constant "RC" 
is bigger than a rise time of the power supply Vcc, the node N1 is not 
immediately charged and its voltage is at low level during a short period 
from the time s1 to s2. A voltage of the node N2 starts to increase from 
the time s2 and it is brought to a high-level constant voltage. A voltage 
of the node N3 is at low level during this period. A voltage of the node 
N4 starts to increase from the time s2 and it is brought to a high-level 
constant voltage. A voltage of the node N1 continuing to increase exceeds 
a threshold voltage of the inverter 31 (approximately 1/2 Vcc) at the time 
s3. Since the inverter 31 receives a high-level input voltage after the 
time s3, a voltage of the node N2 starts to decrease. A voltage of the 
node N3 starts to increase. As a result, a voltage of the node N4 starts 
to decrease from the time s4. The one-shot pulse POR can be obtained as 
described above from the node N4 after the power supply Vcc is turned on. 
FIGS. 19A to 19D are schematic diagrams showing other preferred examples of 
the power on reset circuit applied to the clock generator circuit shown in 
FIG. 13 or 16. 
Although the embodiment of the present invention employing the clock 
generator circuit of a dynamic RAM as one example was described in the 
foregoing, the present invention is applicable to a static RAM and the 
same effect can be brought about. In the case in which the present 
invention is applied to the static RAM, the power-on reset circuit 6 and 
the NOR gate 7 are provided in a circuit connected to a CS (Chip Select) 
terminal instead of the RAS terminal 4. 
As described above, the semiconductor memory device to which the present 
invention is applied comprises a circuit for detecting an application of 
power to the memory device and a circuit for generating a pseudo-state 
signal in response to the detector circuit, whereby the device is 
temporarily brought to the standby state when the power supply is turned 
on for a first time. Therefore, the excessive current which flows when the 
power is turned on can be reduced. In addition, the dynamic RAM to which 
the present invention is applied comprises a circuit for detecting an 
application of power to the memory device, and a circuit for generating a 
pseudo-state signal in response to the detector circuit, whereby the 
device is temporarily brought to the standby state when the power supply 
is turned on for the first time. Therefore, the excessive current which 
flows when the power is turned on can be reduced. Meanwhile, since the 
shortage of the supply capacity due to the excessive current can be 
prevented, the semiconductor memory device operates normally, thereby 
improving reliability. In addition, the damages of the semiconductor 
memory device due to the excessive current can be prevented. The power 
supply requirement of the semiconductor memory device can be reduced. 
Although the present invention has been described and illustrated in 
detail, it is clearly understood that the same is by way of illustration 
and example only and is not to be taken by way of limitation, the spirit 
and scope of the present invention being limited only by the terms of the 
appended claims.