Amplifier circuit

An amplifier circuit is disclosed comprising: an input terminal configured to receive a radio frequency input signal; an output terminal configured to provide a radio frequency output signal; a first transistor having a first collector, a first emitter, and a first base; a second transistor having a second collector, a second emitter, and a second base; a bypass switch; and a controller. The first base is connected to the input terminal and the second emitter. The first collector is connected to a circuit voltage supply and the output terminal. The first emitter is connected to ground and to the second base. The second collector is connected to a collector voltage supply. The bypass switch is connected between the first base and the output terminal. The controller is configured to operate the amplifier circuit in a normal mode of operation or a bypass mode of operation in accordance with an amplitude level of the radio frequency input signal, wherein the controller is configured to open the bypass switch in the normal mode of operation and close the bypass switch in the bypass mode of operation to selectively bypass the first transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority under 35 U.S.C. §119 of European patent application no. 13193163.6, filed on Nov. 15, 2014, the contents of which are incorporated by reference herein.

This disclosure relates to amplifiers, and particularly, although not exclusively, to low noise amplifiers (LNAs) that may be configured for use with radio frequency (RF) signals, for example in wireless local area network (WLAN) applications.

Microwave and millimeter wave frequency amplifiers and LNAs are been increasingly realized in silicon bipolar and metal-oxide FET technologies with transit frequency, ft>100 GHz.

According to a first aspect of the invention there is provided an amplifier circuit comprising: an input terminal configured to receive a radio frequency input signal; an output terminal configured to provide a radio frequency output signal; a first transistor having a first collector, a first emitter, and a first base; a second transistor having a second collector, a second emitter, and a second base; a bypass switch; and a controller. The first base is connected to the input terminal and the second emitter; the first collector is connected to a circuit voltage supply and the output terminal; the first emitter is connected to ground and to the second base; the second collector is connected to a collector voltage source; and the bypass switch is connected between the first base and the output terminal. The controller is configured to operate the amplifier circuit in a normal mode of operation or a bypass mode of operation in accordance with an amplitude level of the radio frequency input signal, wherein the controller is configured to open the bypass switch in the normal mode of operation and close the bypass switch in the bypass mode of operation to selectively bypass the first transistor.

If the controller closes the bypass switch to bypass the first transistor, then in the absence of the second transistor, a device such as a series isolation switch would be required to prevent harmonic signal generation. Such a switch can be very difficult and expensive to implement for operation of the amplifier circuit at high frequencies using a standard silicon NMOS device, at least in part due to excessive losses. Advantageously, the second transistor in the amplifier circuit acts to cancel second harmonic distortions in the amplifier circuit. The first transistor may be considered a primary amplification device and the second transistor may be considered a harmonic cancelling device.

The controller may be configured to compare the amplitude level of the radio frequency input signal with a predetermined amplitude threshold to determine whether to operate in the normal mode of operation or in the bypass mode of operation. There may be a plurality of predetermined threshold levels to account for hysteresis and the controller may be configured to compare the amplitude level of the radio frequency input signal to a selected predetermined amplitude threshold.

The controller may be configured to operate in the bypass mode of operation when the amplitude level of the radio frequency input signal is above the predetermined amplitude threshold. The controller may be configured to operate in the normal mode of operation when the amplitude level of the radio frequency input signal is below the predetermined amplitude threshold.

The first transistor and second transistor may be matched. That is, the first and second transistors may be considered to be equivalent, or identical transistors, each connected in the amplifier circuit as described above. The first transistor and second transistor may each have one or more of: the same area; the same form factor; the same shape; and the same orientation.

By matching the first and second transistors, the amplifier circuit advantageously acts to cancel second harmonic distortions independently of any process variations. This is because the circuit in respect of the first and second transistor is symmetrical due to the transistors being matched/equivalent.

The amplifier circuit may comprise a bias circuit. The controller may be configured to control the bias circuit such that it provides a bias voltage to the first base of the first transistor in the normal mode of operation. The controller may be configured to control the bias circuit such that the bias voltage is disconnected from the first base of the first transistor in the bypass mode of operation.

The amplifier circuit may comprise a first emitter bias voltage source selectively connectable to the first emitter via a first emitter bias switch. The amplifier circuit may comprise a second emitter bias voltage source selectively connectable to the second emitter via a second emitter bias switch. The controller may be configured to operate the first emitter bias switch and the second emitter bias switch in the bypass mode of operation such that bias voltages are applied to the first emitter and the second emitter. The controller may be configured to operate the first emitter bias switch and the second emitter bias switch in the normal mode of operation such that bias voltages are disconnected from the first emitter and the second emitter.

By including first and second voltage sources, advantageously, the first and second transistors may be biased, which provides enhanced removal of signal distortion in the amplifier circuit and increases the linearity of the amplifier circuit.

The amplifier circuit may comprise a first capacitor. The first capacitor may be connected between a junction between the input terminal and the bypass switch, and the first base. The amplifier circuit may comprise a second capacitor. The second capacitor may be connected between a junction between the input terminal and the bypass switch, and the second emitter.

Advantageously, connecting first and second capacitors in this way desirably maintains the symmetry of the circuit in respect of the first and second transistors, and further, these capacitors act to prevent biases provided by the first and second voltage sources from interfering with each other by acting as DC blocks.

The first emitter bias voltage source may be configured to supply a voltage which is substantially half the voltage which the second emitter bias voltage source is configured to supply. This advantageously arises due to the symmetry of the circuit and provides for easier and more predictable amplifier circuit operation.

The amplifier circuit may comprise an input capacitor between the input terminal and a junction between the first base, the second emitter and the bypass switch. The amplifier circuit may comprise an output capacitor between the output terminal and a junction between the bypass switch, the first collector and a voltage source.

The amplifier circuit may comprise a pull-up inductor connected between ground and a junction between the bypass switch, the output terminal and the first collector. The amplifier circuit may comprise an input inductor connected between the input terminal and a junction between the first base, the second emitter and the bypass switch. The amplifier circuit may comprise a degeneration inductor connected between ground and a junction between the first emitter and the second base.

According to a further aspect of the invention, there is provided an electronic device comprising the amplifier circuit as described above.

According to a further aspect of the invention, there is provided an integrated circuit comprising the amplifier circuit as described above.

One or more embodiments disclosed herein relate to an amplifier circuit configured to amplify a received radio frequency input signal when operating in a normal/high gain mode, and allow the signal to pass through the circuit without significant amplification when operating in a bypass mode. The amplifier circuit may include a pair of matched back-to-back transistors such that one of the transistors performs the amplification in the normal mode, yet the pair of transistors together may advantageously reduce or minimise even-numbered (as opposed to odd-numbered) harmonic interference in the output signal in the bypass mode. Matched transistors may each have the same form factor, shape, and/or orientation in the circuit. Orienting the transistors (of the same size/area) in a similar way side by side in the circuit acts to match them and can aid in process parameter tracking.

Throughout the following description, the amplifier circuit may be described as operating in a normal mode of operation or a bypass mode of operation. The normal mode may also be considered an active mode, a high gain mode, or an amplifier mode. The bypass mode may be considered a non-amplification mode, or a passive mode.

Low noise amplifiers (LNAs) may be implemented in bipolar processes for WLAN applications at 2.4 GHz and 5.8 GHz frequencies. Co-location of different frequency transceivers can require the receiver LNA to handle larger signals because the signal source may be positioned close to the amplifier. In other situations the signal source may be relatively far from the amplifier leading to small/weak received signals. When the LNA receives large input signals, an amplifier bias may be turned off and the amplifier device may then be bypassed using a switch. This is described below with reference toFIG. 1a.The signal levels in the bypass mode can generate harmonics even though the amplifier device is in an off state. The power level of harmonics returning to the antenna are required to be below −45 dBm in some applications.

Amplifier circuits described herein comprise at least one transistor. The transistors that are illustrated are bipolar junction transistors (BJTs) with terminals labelled as the base, collector, and emitter. In examples having two matching transistors as inFIGS. 2a-2cand 3a-3c, the paired transistors may have a common emitter/source, or be in a cascade or back-to-back configuration.

FIG. 1aillustrates an amplifier circuit which can operate in both a normal mode and a bypass mode. The normal mode of such an amplifier circuit may be used to amplify a weak received signal; that is, one with a low power level. It is important that as little noise as possible is added to the signal when it is being amplified, as the added noise will be amplified by the amplifier circuit along with the input signal, which is why LNAs can be used.

The amplifier circuit comprises an input terminal RFin102configured to receive a radio frequency input signal, and an output terminal RFout104configured to provide a radio frequency output signal. The amplifier circuit100also comprises a transistor Q1106having a collector108, an emitter110, and a base112, a connection switch S2114and a bypass switch S3116.

A bias circuit150is connected to a bias voltage node132. The bias voltage node132is located between the input terminal RFin102and a first terminal of the connection switch S2114. The second terminal of the connection switch S2114is connected to the base112of the transistor106. The bias circuit150is configured to provide a bias voltage to the base112of the transistor Q1106when the circuit is operating in the normal mode. The bias circuit150comprises a bias switch S1152configured to close when the circuit100is operating in the normal mode to allow a bias voltage to be provided, and configured to open when the circuit100is operating in the bypass mode so that a bias current is not provided to the base112from the bias circuit150.

The input terminal RFin102is connectable to the base112via the connection switch S2114. The input terminal RFin102is connectable to the output terminal RFout104via the bypass switch S3116. The collector108is connected to a circuit voltage supply Vcc120and the output terminal RFout104. The emitter110is connected to ground118.

A large input signal provided at the input terminal RFin102may be very close in frequency to the output signal expected at the output terminal RFout104. Thus it may be difficult to filter out interference caused by the input signal on the output signal when the transistor Q1106is used amplify large signals. It can therefore be undesirable to have a large input signal provided to the base112of the transistor Q1106as this can cause harmonic interference in the output signals. Therefore the transistor Q1106can be bypassed using the bypass switch S3116for large input signals, allowing the amplifier circuit100to operate in a bypass mode.

In the normal mode, the bias switch S1152and the connection switch S2114are closed, and the bypass switch S3116is open. Losses from the amplifier circuit100associated with the switch S2114may add to the noise figure of the amplifier circuit100. Such additional losses may particularly cause concern when using an NMOS field effect transistor at higher RF and microwave frequencies. The noise levels in the output signal may be acceptably low if a smaller input signal is used. The connection switch S2114should have as low a loss as possible to reduce the noise in the amplifier circuit100. Such a very low loss switch may require sophisticated technology. It can be very difficult, if not impossible, to have a connection switch S2114which achieves low enough losses for an acceptable amplifier to be provided.

Achieving an acceptable connection switch S2114can become more challenging as performance requirements increase. Switches typically do not have 0Ω resistance and they have a parasitic capacitance. A connection switch S2114can be made as large as possible to reduce losses, but it will still have an associated parasitic capacitance at high signal frequencies. The parasitic capacitance can be nonlinear, and may have an undesirable effect on the substrate of an integrated circuit on which the amplifier circuit is provided, which therefore also has an undesirable effect on the performance of the amplifier circuit.

InFIG. 1a, the amplifier circuit100can operate in a bypass mode when the bypass switch S3116is closed and the bias switch S1and the connection switch S2are open. The bypass mode can be used when a large input signal is received. The input signal may thus be routed directly from the input terminal RFin102to the output terminal RFout104in the bypass mode. This provides isolation of the base112of the transistor Q1106from the input signal under large input signal conditions.

By way of example, a small input signal may be considered a signal which is approximately 10-15 dB lower than the compression point of the amplifier. For example, for an input compression of 0 dB, a small signal may be considered to be a signal lower than −10 dBm. A large signal may be considered to be a signal which is closer to the compression point of the amplifier.

FIG. 1billustrates another amplifier circuit160which can operate in both a normal mode and a bypass mode. The amplifier circuit160comprises an input terminal RFin162, an output terminal RFout164, a transistor Q1166, a bias circuit194connected to a bias voltage node192located between the input terminal RFin162and the base172of the transistor Q1166, and a bypass switch S3176, as inFIG. 1a. An emitter bias voltage source VE186is connectable to the emitter166via an emitter bias switch S4188. The connection switch S2184inFIG. 1bis in a different location to that ofFIG. 1a, such that it need not necessarily be an extremely low loss switch as is required for the connection switch S2in the amplifier circuit ofFIG. 1a. The connection switch S2ofFIG. 1bis not directly in the series path between the input terminal RFinand the base172of the transistor Q1, but it is instead connected between the emitter170and ground178. In this example, an inductor Le190is connected in series between the connection switch S2184and ground178.

Closing the connection switch S2184connects the emitter170to ground178via the inductor Le190, allowing current to flow through the transistor Q1and therefore enabling the transistor Q1to be used as an amplifier. When the connection switch S2184is open, the emitter170is not connected to ground178and the transistor Q1cannot conduct and therefore cannot amplify.

The circuit can be operated in the normal mode by closing the bias switch S1196, closing the connection switch S2184, opening the emitter bias switch S4188and opening the bypass switch S3176.

The circuit160can operate in the bypass mode by opening the bias switch S1196, opening the connection switch S2184, closing the emitter bias switch S4188and closing the bypass switch S3176. The transistor Q1166may be considered to be turned off in the bypass mode. The transistor Q1166does not amplify the received signal in the bypass mode because the signal bypasses the transistor Q1166and passes from the input terminal RFin162through the closed bypass switch S3176to the output terminal RFout164. The emitter bias switch S4188is closed in the bypass mode to reverse bias the transistor (acting as a diode) and enhance the linear performance when the circuit operates passively.

The nonlinear base-emitter junction of the transistor Q1166causes the transistor Q1166to behave similarly to a zero-biased diode, which is a distorting device and is therefore undesirable in the circuit. To reduce the likelihood of harmonics (such as second harmonics) creating signal distortions at the output terminal RFout164and also at the input terminal RFin162, in this example the emitter bias voltage source VE186is connected to the emitter170by closing the emitter bias switch S4188in the bypass mode of operation. This acts to apply a reverse bias to the base-emitter junction of the transistor166. Connecting a positive voltage VE186to the base-emitter junction causes it to be back-biased/reverse biased, which may reduce distortion in the amplifier circuit160. This back-bias acts to linearise the transistor Q1166when the amplifier circuit160is operating in the bypass mode and therefore improve performance.

The back-bias applied from VE186can be, however, limited due to the small breakdown voltage of narrow and high speed SiGe base-emitter junctions of modern transistors. Further, the connection switch S2184should still be as large as possible (for example, a 2 mm switch) to be a low-loss device, and this can require a high on-chip area, which is not always desirable.

Therefore, when the amplifier circuit160ofFIG. 1bis operating in the bypass mode, it is still possible to have unacceptably high levels of second harmonics at both the output terminal RFout164and the input terminal RFin162. Such problems may be addressed by an amplifier circuit as described below in relation toFIGS. 2a-2candFIGS. 3a-3c.

FIG. 2ashows an amplifier circuit200comprising two back-to-back transistors206,214. The amplifier circuit200can operate in normal and bypass modes without requiring a reverse bias to be applied.FIG. 2billustrates how the circuit ofFIG. 2aoperates in the normal mode.FIG. 2cillustrates how the circuit ofFIG. 2aoperates in the bypass mode.

The amplifier circuit shown inFIGS. 2a-2ccomprises an amplifier device (such as a transistor) in conjunction with a matched device such that even-numbered harmonics, especially the second harmonics, are reduced, minimized or cancelled when the amplifier circuit operates in the bypass mode, whilst circuit performance in the normal mode is not significantly affected. The matched device may be considered to provide a second harmonic reduction/minimising function, and may in some examples allow the amplifier circuit to yield 50 dBc second harmonic rejection performance tracking over process and temperature variation at around 5 dBm blocker levels.

The amplifier circuit200ofFIG. 2acomprises an input terminal RFin202configured to receive a radio frequency input signal and an output terminal RFout204configured to provide a radio frequency output signal. It also comprises a first transistor Q1206having a first collector208, a first emitter210, and a first base212, as well as a second transistor Q2214having a second collector216, a second emitter218, and a second base220. In this example the first transistor Q1206is the amplifier device and the second transistor Q2is the matched device referred to above. The amplifier circuit200also comprises a bypass switch S3222and a controller201. It will be appreciated that the controller201can operate all of the switches shown inFIG. 2a, although it is also illustrated as controlling the bypass switch S3222so as not to overcomplicate the drawing.

The first base212is connected to the input terminal RFin202and the second emitter218. The input terminal RFin202is also connectable to the output terminal RFout204via the bypass switch S3222. The first collector208is connected to a circuit voltage supply Vcc224, and to the output terminal RFout204. The first emitter210is connected to ground226and to the second base220. The second collector216is connected to a collector voltage supply228, so that the second collector216mimics the first collector208of the first transistor Q1206. The collector voltage supply228acts as a ground when AC signals are used in the amplifier circuit200because the circuit voltage supply Vcc224is bypassed to AC ground in this case. The second emitter218is connected to the input terminal RFin202and the first base212. The bypass switch S3222is connected between the input terminal RFin202and the output terminal RFout204. In this example a bias circuit250is connected between the input terminal RFin202and a junction between the first base212, second emitter218, and bypass switch S3222.

In this example, the second transistor Q2214and the first transistor Q1206are matched (they are the same type of transistor with the same characteristics such as area, form factor, shape and orientation). The primary active device for amplification is the first transistor Q1206. The second transistor Q2214is added in the amplifier circuit200across the first transistor Q1206to cancel distortion created by the first transistor Q1206. The emitter of the second transistor Q2214is connected to the base212of the active transistor Q1206; and the base220of the second transistor Q2214is connected to the emitter210of the first transistor Q1206. This advantageously provides a symmetrical circuit which acts to reduce/minimise second harmonics in the circuit200.

The controller201is configured to either open or close the bypass switch S3222in accordance with an amplitude level of the radio frequency input signal received at the input terminal RFin202. In this way the first transistor Q1206can be selectively bypassed. The controller201may be configured to compare the amplitude level of the radio frequency input signal with a predetermined amplitude threshold level to determine whether to open or close the bypass switch S3222. There may be two predetermined threshold levels to provide for hysteresis in the circuit. If the amplitude level of the radio frequency input signal provided to the input terminal RFin202is above the predetermined amplitude threshold level then the bypass switch S3222is closed so that amplification is not provided. If the amplitude level of the radio frequency input signal provided to the input terminal RFin202is below the predetermined amplitude threshold then the bypass switch S3222is opened so as to connect the first transistor Q1206in the circuit200and amplify the signal.

In this example, the amplifier circuit200also comprises a first capacitor230in series between the input terminal RFin202and a junction between the first base212, the second emitter218and the bypass switch S3222. The amplifier circuit200also comprises a second capacitor232in series between the output terminal RFout204and a junction between the bypass switch S3222, the first collector208and the circuit voltage supply224. The first capacitor230acts as a DC blocking capacitor that prevents the DC current that is provided by the bias circuit250from reaching an antenna that is connected to the input terminal RFin202. The second capacitor232acts as a DC blocking capacitor that prevents the DC current that is provided by the bias circuit250from reaching a stage that is connected to the output terminal RFout204of the amplifier circuit200.

In this example, the amplifier circuit200also comprises three inductors: a pull-up inductor Lc234connected between the circuit voltage supply224and a junction between the bypass switch S3222, the output terminal RFout204and the first collector208; an input inductor Ls236connected between the input terminal RF202and a junction between the first base212, the second emitter218and the bypass switch S3222; and a degeneration inductor Le238connected between ground226and a junction between the first emitter210and the second base220. The inductors Lc234, Ls236and Le238are configured to, in combination with the transistor's parasitic capacitance values, match the amplifier circuit200impedance to that of the source impedance.

The first transistor Q1206may be impedance matched with the degeneration inductor/bond-wire Le238and an input/input package bondwire Ls236to a 50Ω source.

The size/area of the first transistor Q1206may be optimized to yield an acceptable noise performance (that is, an acceptable low level of noise in the output signal) by optimizing the level of base resistance. This also brings the “noise match” closer to 50Ω. In an ideal circuit the degeneration inductor/bond-wire Le238would work with the capacitance of the amplifier circuit to generate an input impedance equal to the 50Ω source. In such a case the amplifier may be considered to be impedance matched to the source.

The bias circuit250includes a reference transistor Q0, reference current source I0and beta-helper transistor Qbthat can together provide bias a current level that is independent of supply and process variation. The reference transistor Q0and the beta-helper transistor Qbare provided as part of a current mirror circuit.

The bias circuit250can be turned off if the first transistor Q1206is bypassed. Current may be prevented from passing through the transistor Q1206by closing the switch S4254, closing the switch S5258and opening switch S1in the bias circuit250.

First transistor Q1206and second transistor Q2214are equal (identical) and are connected opposite to each other, so they together provide an “odd” transfer function when the circuit is in the bypass mode, as described with reference equations 1 and 2 below. In this way, they provide a second harmonic “canceller”. The resulting “odd” function cancels nonlinear distortions and so a very low second harmonic distortion can be achieved. This approach can be at least as effective as using a very large connection switch S2in the circuit ofFIG. 1b.

For the amplifier circuit as described in relation toFIGS. 2a-2c, there may be no need to apply a reverse bias as shown in the amplifier circuit ofFIG. 1b. Using the amplifier circuit200ofFIG. 2a, it is possible to achieve 55 dB distortion, which is an acceptably low level in some applications.

InFIG. 2bthe amplifier circuit200is shown operating in the normal mode. The bias switch S1256is closed. Bias switches S4254and S5258as well as bypass switch S3222, are open. The open bypass switch S3222behaves as a parasitic capacitor Cs2off262, as shown inFIG. 2b. The second transistor Q2214is reverse biased (that is, it is off), and the base-emitter junction is depleted. The emitter218of the second transistor Q2214is connected to the input terminal RFin202. The second collector216of the second transistor Q2214is connected to the collector voltage supply228. Thus the collector-emitter junction of the second transistor Q2214is reverse-biased and acts as a small capacitive sink Cq2260which only minimally affects the circuit operation. This is because it has a small capacitance compared with the capacitance Cπ1across the base-emitter junction of the first transistor Q1206, which is in parallel with the capacitive sink Cq2. The capacitance Cq2reduces further as the charges become more separated in a reverse-biased junction.

InFIG. 2cthe amplifier circuit200is shown operating in the bypass mode. The bias switch S1256is open, and bias switches S4254and S5258, as well as bypass switch S3222are closed. When a large signal is input to the input terminal RFin202it is desirable to turn off the bias (that is, disconnect the bias circuit250) because it is not required at the first base212of the first transistor Q1206. In this way, energy is not wasted. The transistor Q1206then operates as a (inverted) zero bias diode (shown with reference264inFIG. 2c), matched with the second transistor Q2214which also operates as a diode (shown with reference266inFIG. 2c).

In certain examples, the second harmonic minimizing effect may be further linearized by applying appropriate bias voltages to the emitters of the first transitor and the second transistor, for example as inFIGS. 3a-3c, to achieve >65 dBc second harmonic rejection performance tracking over process and temperature variation when the blocker levels are around 11 dBm.

FIG. 3ashows an amplifier circuit300comprising two back-to-back transistors which may each have a voltage bias applied for improved circuit linearity.FIG. 3billustrates how the circuit ofFIG. 3aoperates in the normal mode.FIG. 3cillustrates how the circuit ofFIG. 3aoperates in the bypass mode.

The amplifier circuit300ofFIG. 3aincludes components that are shown inFIG. 2a. Similar elements betweenFIGS. 2a-2cand 3a-3chave been provided with similar reference numerals, and common elements discussed in relation toFIGS. 2a-2cwill not necessarily be discussed again in detail with respect toFIGS. 3a-3c.

The amplifier circuit300can act more linearly when the first transistor Q1306and the second transistor Q2314are reverse biased. This can act to cancel distortion in the amplifier circuit300.

The amplifier circuit300inFIG. 3acomprises a first emitter bias voltage source VE1382connected to the first emitter310via a first emitter bias switch S7384, and a second emitter bias voltage source VE2386connected to the second emitter318via a second emitter bias switch S6388. The emitter bias voltage sources VE1382and VE2386may be switched in by the emitter bias switches S7384and S6388respectively to reverse bias the second harmonic canceling connection of the Q1/Q2transistor pair306,314. This amplifier circuit300can provide greater than 65 dBc second harmonic rejection at input levels of 11 dBm.

The amplifier circuit300comprises a first capacitor C13002and a second capacitor C23004. The first capacitor C13002is connected between a junction between the input terminal RFin302and the bypass switch S3322, and the first base312. The second capacitor C23004is connected between a junction between the input terminal RFin302and the bypass switch S3322, and the second emitter318. In this example, the first capacitor C13002and the second capacitor C23004are identical. They serve as DC blocks to prevent biases from the first emitter bias voltage source VE1382and the second emitter bias voltage source VE2386from interfering with each other. Overall the amplifier circuit300advantageously maintains symmetry.

The first emitter bias voltage source VE1382and second emitter bias voltage source VE2386may each be connected to a common voltage supply, and a voltage divider may be used to achieve the bias levels required. In some examples, the first emitter bias voltage source VE1382may be configured to supply a voltage that is substantially half the voltage which the second emitter bias voltage source VE2386is configured to supply. For example, if 0.8 V is connected to the first emitter310in reverse bias, the second transistor Q2314may be reverse biased by the same amount when connecting1.6V from the second voltage source VE2386. That is, double the voltage may be applied from the second emitter bias voltage source VE2386as from the first emitter bias voltage source VE1382to balance the circuit.

FIGS. 3band 3cshow the amplifier circuit300operating in the normal mode and the bypass mode respectively. The reverse bias applied to the first transistor Q1306by the first emitter bias voltage source VE1in the bypass mode is shown inFIG. 3cas a voltage source364. The reverse bias applied to the second transistor Q2314by the second emitter bias voltage source VE2in the bypass mode is shown inFIG. 3cas a voltage source366. The first and second transistors Q1306and Q2314behave as reverse biased diodes364,366when the amplifier circuit300operates in a bypass mode.

The amplifier circuit300comprises a bias circuit350that can provide a bias voltage to the first base312of the first transistor Q1.

The amplifier circuit300ofFIG. 3amay allow for further removal of second harmonic distortions when compared with the circuit ofFIG. 2a. Both first and second transistors Q1306and Q2314may be reverse biased by the first emitter bias voltage source VE1382and the second emitter bias voltage source VE2386to achieve an even lower distortion. For example, a 10 dBm input signal may be received at the input terminal RFin302to meet specification standards. A 65 dB distortion reduction of the second harmonics can be achieved, which is very good. Otherwise such levels may not be achievable, or may only be achieved using, for example, a large expensive switch for the bypass switch S2as inFIG. 1a.

Amplifier circuits as disclosed herein may be constructed using commercial bipolar and BiCMOS technologies.

In the amplifier circuits200,300ofFIGS. 2a-2cand 3a-3c, the “odd” transfer function provided by the matched first and second transistors Q1206,306and Q2214,314in the bypass mode arises as described below.

In the bypass mode, when the bias is turned off, the transistors Q1206,306and Q2214,314act as two passive diodes264,364;266,366connected back to back as shown inFIGS. 2cand 3c. The second transistor Q2214,314is in an off state when the first transistor Q1206,306is on during the normal mode, and thus the second transistor Q2214,314does not significantly affect the performance of the amplifier circuit200,300when operating in the normal mode.

The current through the first transistor Q1, i1is defined as:

i1=is⁢ⅇ(qVbenKT),
where isis the saturation current, q is charge, Vbeis the base emitter voltage, n is an ideality factor (close to 1), K is Boltzmann's constant, and T is temperature.

In the bypass mode, a transfer characteristic

i2=-is⁢ⅇ(-qVbenKT)
is introduced, where i2is the current through the second transistor Q2214,314.

The net i-v characteristics of the amplifier circuit may be expressed as:

α=qnKT,
t is time and and Inis a modified Bessel function of order n.

This function has an “odd” symmetry due to the sinh function of equation 1, which is represented by the (2k+1) multiplier in equation 2. In this way, the “even-numbered” harmonics, including the second harmonic, under periodic sinusoidal excitations are cancelled out.

Thus, it will be appreciated that the addition of the second transistor Q2214,314creates a nonlinear transfer function that cancels the even harmonics, which may otherwise be generated by the transistor Q1206,306when the amplifier circuit200,300operates in the bypass mode.

Any components that are described herein as being “coupled” or “connected” could be directly or indirectly coupled or connected. That is, one or more components could be located between two components that are said to be coupled or connected whilst still enabling the required functionality to be achieved.