Semiconductor device and manufacturing method therefor

The semiconductor device according to an aspect of the invention includes: an internal circuit area having an internal circuit; an I/O circuit area positioned outside the internal circuit area; and an electrode pad placed across an outer edge of the I/O circuit area. In the electrode pad, an area outside the outer edge of the I/O circuit area is a bonding area, and an area inside the outer edge is a probe area.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a manufacturing method therefor. In particular, the invention relates to a semiconductor device including an electrode pad and a manufacturing method therefor.

2. Description of Related Art

A semiconductor device generally includes an internal circuit and an I/O circuit where an input/output buffer circuit is built. An electrode pad for connecting an external electrode is formed on the I/O circuit. Further, a test probe as an electrical characteristic tester is brought into contact with the electrode pad formed on the I/O circuit to pass a current through the semiconductor device through the test probe for electrical characteristic testing, which is the so-called probing. That is, there are two applications of the electrode pad; the two applications are for wire bonding and for contact with the test probe. If the same electrode pad is subjected to bonding and probe testing, there is a fear that bonding strength is lowered upon the wire bonding owing to a physical damage on the electrode pad due to the test.

Japanese Unexamined Patent Application Publication No. 2002-329742 discloses a semiconductor device that is devised for overcoming this drawback. In the semiconductor device, a testing pad that contacts a test probe and a bonding pad for wire bonding are formed on the electrode pad.

However, in the semiconductor device, an inner portion of a chip may be physically damaged upon the wire bonding of the electrode pad on the chip. In other words, a circuit under the electrode pad may be physically damaged at the time of wire bonding. To that end, a wire bonding apparatus needs to execute bonding under such conditions that the chip inner portion is not physically damaged due to a load of the wire bonding. Thus, the wire bonding apparatus and its use conditions etc. should be carefully examined in consideration of the sectional structure in the chip. That is, since a load applied to the chip varies depending on a chip's sectional shape or the like, the use conditions of the bonding apparatus need to be separately set for chips of different structures. In addition, in the case of using different bonding apparatuses, the conditions have to be set for each apparatus. Especially in the case of shipping products in a chip (pellet) form without bonding, a purchaser (user) uses a desired bonding apparatus. Thus, it is necessary to carefully and individually set the optimal conditions for various bonding apparatuses.

As described above, the conventional semiconductor device has a possibility that an inner circuit of a chip is damaged depending on wire bonding conditions, so the bonding apparatus and its use conditions should be carefully examined.

SUMMARY OF THE INVENTION

A semiconductor device according to an aspect of the invention includes: an internal circuit area having an internal circuit; an I/O circuit area positioned outside the internal circuit area; and an electrode pad placed across an outer edge of the I/O circuit area. Thus, the pad can be bonded in a position outside the I/O circuit area, so the semiconductor device can be prevented from being damaged. Hence, yield can be improved and productivity can be improved as well.

According to another aspect of the invention, a manufacturing method for a semiconductor device including an internal circuit area having an internal circuit, and an I/O circuit area positioned outside the internal circuit area, includes: placing an electrode pad across an outer edge of the I/O circuit area; bringing a probe into contact with the electrode pad inside the outer edge of the I/O circuit area to execute testing; and wire-bonding the electrode pad outside the outer edge of the I/O circuit area. Thus, the pad can be bonded in a position outside the I/O circuit area, so the semiconductor device can be prevented from being damaged. Hence, yield can be improved and productivity can be improved as well.

According to the present invention, it is possible to provide a semiconductor device and a manufacturing method therefor, which can suppress a damage resulting from bonding in a simple manner.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present invention is described. The following description is given for demonstrating the embodiment of the invention, so the present invention is not construed as being limited to the following embodiment. For precise explanation, the following description is partially omitted and simplified as appropriate. In addition, those skilled in the art would readily make change, addition, and replacement of components of the following embodiment within the scope of the invention. Incidentally, the same components are denoted by identical reference numerals throughout the accompanying drawings, and description thereof is omitted if not necessary.

Referring toFIGS. 1 and 2, a semiconductor device according to the present invention is described.FIG. 1is a top view schematically showing the structure of a semiconductor wafer including a semiconductor device of the present invention.FIG. 2is a top view schematically showing the structure of a semiconductor chip mounted on the semiconductor wafer ofFIG. 1.

As shown inFIG. 1, a plurality of rectangular semiconductor chips1is formed on a semiconductor wafer100. Then, scribe lines11extend between the semiconductor chips1for separating the semiconductor chips1from one another. The scribe lines11are arranged in the X or Y direction. Assuming that the semiconductor wafer100is cut along the scribe lines11, the wafer is divided into the semiconductor chips1. The semiconductor chip1is structured as shown inFIG. 2.FIG. 2is a top view showing the structure of the semiconductor chip1.

As shown inFIG. 2, an internal circuit area2having an internal circuit including a memory circuit or a logic circuit is positioned at the center of the semiconductor chip1. Plural I/O circuit areas3are formed to surround the internal circuit area2like a frame. The plural I/O circuit areas3are arranged along the outer edge of the semiconductor chip1. That is, the I/O circuit areas3are arranged along the four sides of the rectangular semiconductor chip1. In the I/O circuit areas3outside the internal circuit area2, an I/O circuit such as an input buffer circuit or an output buffer circuit is formed. Electrode pads4are put on the respective I/O circuit areas3. The electrode pad4partially protrudes from the I/O circuit area3. Each electrode pad4and the I/O circuit in the I/O circuit area3are electrically connected together. The electrode pad4on the I/O circuit area3is connected with an external electrode by means of wire bonding. An input signal from the external electrode is input to the internal circuit through the I/O circuit in the I/O circuit area3. Furthermore, an output signal from the internal circuit is output to the external electrode through the I/O circuit in the I/O circuit area3.

Referring toFIGS. 3 and 4, the structure of the electrode pad4on the I/O circuit area3is described.FIG. 3is an enlarged top view of the structure of a peripheral portion of the electrode pad4.FIG. 3illustrates the electrode pad4in the I/O circuit area3on the lower side of the semiconductor chip1ofFIG. 2.FIG. 4is an enlarged side sectional view of the structure of the peripheral portion of the electrode pad.

As shown inFIG. 3, the electrode pad4is placed on the I/O circuit area3. As shown inFIG. 4, in the I/O circuit area3, a transistor structural part13of the I/O circuit is formed. In the transistor structural part13, a transistor serving as an I/O circuit and its electrodes are formed. Furthermore, a line structural part15is formed on the transistor structural part13through an interlayer insulating film14. In the line structural part15, a line extending up to the transistor structural part13is formed, for example. In addition, the line of the line structural part15is connected with the electrode pad4. The interlayer insulating film14is sandwiched between the transistor structural part13and the line structural part15. The line of the line structural part15is connected with the transistor of the transistor structural part13or the like through a via-hole formed in the interlayer insulating film14. Moreover, an uppermost insulating film7is formed on the line structural part15. On a substrate12as a wafer, an area including the transistor structural part13and the line structural part15corresponds to the I/O circuit area3. Meanwhile, the interlayer insulating film14is formed outside the I/O circuit area3. That is, neither electrode nor line is formed below the electrode pad4outside the I/O circuit area3. In this area, only the insulating film is formed. Incidentally, the uppermost insulating film7is partially removed to expose the electrode pad4. That is, the uppermost insulating film7is patterned to expose a conductive portion of the electrode pad4. Further, the uppermost insulating film7overlaps end portions of the electrode pad4. Accordingly, only the end portions of the electrode pad4are covered with the uppermost insulating film7. Thus, a central portion of the electrode pad4is exposed. Here,FIG. 4schematically shows the structure of the peripheral portion of the electrode pad of the semiconductor device of this embodiment, but the present invention is not limited to this structure.

The electrode pad4partially protrudes from the I/O circuit area3. That is, only an inner portion of the electrode pad4is formed on the I/O circuit area3, and the outer portion thereof projects from the I/O circuit area3. In other words, the electrode pad4is placed across an outer edge9of the I/O circuit area3. Here, an area on the I/O circuit area3and an area outside the I/O circuit area3out of the exposed portion of the electrode pad4are a probe area5and a bonding area6, respectively. The exposed portion of the electrode pad4extends over the I/O circuit area3. The electrode pad4is constituted of the probe area5positioned inside the outer edge9and the bonding area6positioned outside the outer edge9. That is, the electrode pad4is divided into the bonding area6and the probe area5across the outer edge9of the I/O circuit area3.

As shown inFIG. 4, the test probe21contacts the probe area5for probe testing. Further, a bonding wire22is connected with the bonding area6for bonding. As shown inFIG. 3, the uppermost insulating film7is formed around the electrode pad4. The exposed portion of the electrode pad4is subjected to probing and bonding.

The electrode pad4ofFIG. 3has a rectangular shape with the width of 75 μm in the X direction and the length of 156 μm in the Y direction. The exposed portion of the electrode pad4has the width of 67 μm in the X direction and the length of 148 μm in the Y direction. That is, the outer peripheral portion of the electrode pad4is covered with the uppermost insulating film7with the width of 4 μm. Thus, the exposed portion of the electrode pad4takes a rectangular shape that measures 67 μm×148 μm. The uppermost insulating film7partially covers the electrode pad4like a frame. A pitch between the adjacent electrode pads4in the X direction is 80 μm.

Here, the length of the bonding area6in the X direction is preferably set equal to the width of the exposed portion of the electrode pad4in the Y direction. That is, in the above example, the width of the bonding area6is preferably 67 μm. In this case, the surface area of the bonding area6is 67 μm×67 μm, and the surface area of the probe area5is 67 μm×81 μm. Thus, the bonding area6has substantially square shape. A 60 μm-diameter circular portion of the square bonding area6is connected with the bonding wire22. That is, the bonding wire22contacts the bonding area in the 60 μm-diameter circular portion. Hence, in the bonding area6, an area other than the contact portion with the bonding wire22can be reduced. That is, even if the bonding area6is small, the bonding wire22can be reliably bonded within the bonding area6. Incidentally, the aforementioned size of the electrode pad4is just a typical value, and the present invention is not limited to this value. The sizes of the bonding area6and the probe area5may be determined in accordance with accuracy of the bonding apparatus and the probe testing apparatus.

The scribe line11extends along the X direction, outside the I/O circuit area3. The scribe line11is formed along the outer edge9of the I/O circuit area3. The plural electrode pads4are arranged along the scribe line11. Then, the semiconductor wafer100is cut along the scribe line. The semiconductor wafer100is scribed into the plural semiconductor chips1. To scribe the wafer on the scribe line11, the electrode pad4is placed inside the scribe line11. That is, the bonding area6of the electrode pad4is defined between the scribe line11and the I/O circuit area3. The width of the scribe line11at the scribe center and edge portions is, for example, 50 μm. A distance from the scribe edge of the scribe line11to the electrode pad4is, for example, 25.65 μm.

As described above, an area inside the outer edge9of the I/O circuit area3and an area outside the outer edge9of the I/O circuit area3of the electrode pad4are set to the probe area5and the bonding area6, respectively. Furthermore, the probe area5and the bonding area6are different areas. Then, in a step of inspecting the semiconductor chip1, a test probe21comes into contact with the probe area5of the electrode pad4for probe testing. As shown inFIG. 3, in the inspecting step, the test probe forms a probe mark23in the probe area5of the electrode pad4.

The bonding wire22for establishing connection with the external electrode is connected with the bonding area6of the electrode pad4. The semiconductor chip1obtained by scribing the wafer along the scribe line11is wire-bonded in a wire-bonding step. The bonding area6is positioned outside the I/O circuit area3. Thus, only the uppermost insulating film7, the interlayer insulating film14, or other such insulating film is formed below the bonding area6, and lines, electrodes, or transistors of the I/O circuit are not formed. Accordingly, it is possible to prevent the circuit from being damaged due to a load of the wire bonding. Thus, wire-bonding can be executed without individually setting the optimum use conditions for different bonding apparatuses. Thus, even if a product is shipped in a chip form, it is unnecessary to set the optimal conditions for each bonding apparatus, and any desired bonding apparatus can be used. Thus, even in the case of shipping the product in a chip form, the wire-bonding can be easily and simply performed.

Further, according to the present invention, the probe area5and the bonding area6are different areas. Therefore, it is possible to prevent the formation of the probe mark in the bonding area6and to reliably execute bonding. That is, the test probe21comes into contact with the probe area5different from the bonding area6. Hence, no probe mark remains in the bonding area6, and the surface is kept flat. Accordingly, the bonding wire is not connected with the probe mark. Hence, the wire-bonding can be reliably executed.

The above semiconductor chip manufacturing process is described. First, patterns are formed on the semiconductor wafer100, the I/O circuit is implemented in the I/O circuit area3, and the internal circuit is implemented in the internal circuit area2using a general film formation or lithographic process. In this case, the electrode pad4is formed on the I/O circuit area3. Further, the electrode pad4partially protrudes from the outer edge of the I/O circuit area3. The electrode pad4is generally formed using a metal conductive film such as an aluminum film.

After the formation of the electrode pad4together with the internal circuit and the I/O circuit, electrical inspection is carried out. First, the test probe for inspection is moved to the probe area5of the electrode pad4, and the tip end of the test probe is brought into contact with the electrode pad4. Then, an inspection signal is input from the test probe for inspection through the electrode pad4, and the output signal is monitored. As a result, the quality of a semiconductor chip on the semiconductor wafer is checked. More specifically, the tip end of the test probe21is put into contact with the electrode pad4of the semiconductor chip1, and an electrical signal is output from a tester (not shown). An output signal from the semiconductor chip based on the electrical signal is detected to measure and test electrical characteristics of the semiconductor chip1. The quality of the semiconductor chip is checked based on the result of probe testing. This inspection is executed for all semiconductor chips to inspect in the wafer.

As a result of the quality check, passed semiconductor chips and rejected ones are given different marks and screened out. Then, the semiconductor wafer100is cut along the scribe line, after which the rejected semiconductor chips are discarded. The passed semiconductor chips1are passed to an assembling step and subjected to die-bonding or wire-bonding. At this time, the wire is bonded to the bonding area6of the electrode pad4through the wire bonding. The bonding area6is separate from the probe area5, so the bonding can be reliably carried out. That is, since no probe mark remains in the bonding area6upon the probe testing, the wire can be bonded to a flat portion in the electrode pad4. As a result, a bonding reliability can be improved.

At this time, the outer edge9of the I/O circuit area3can be used as a mark for defining the probe area5or the bonding area. That is, bonding or probing is executed while the electrode pad4is optically observed. Lines or electrodes are formed inside the outer edge9of the I/O circuit area3, and only an insulating film is formed outside the outer edge. Accordingly, the bonding area6of the electrode pad is positioned outside the outer edge of the metal film. Hence, it is possible to easily determine whether a target area is positioned outside or inside the outer edge9of the I/O circuit area3, and to easily distinguish between the probe area5and the bonding area6. Thus, it is possible to readily distinguish whether the bonding wire or the tip end of the test probe contacts the probe area5or the bonding area6. Accordingly, the probing and the bonding can be accurately executed.

Owing to the above structure, the wire can be bonded outside the I/O circuit area3, so it is possible to suppress a physical damage due to the bonding. Furthermore, a part of the electrode pad4is placed in a spare space between the outer edge9of the I/O circuit area3and the scribe line11. As a result, enlargement of a chip can be prevented. Further, even if bonding is executed using different bonding apparatuses, it is unnecessary to individually set the conditions for each bonding apparatus. Therefore, various bonding apparatuses can be used for bonding in a simple manner. Hence, the semiconductor device of the present invention is suitable for shipment in the chip form. Further, in the case of evaluating a chip after the bonding, bonding wire for evaluation can be connected to the probe area5. Consequently, the chip can be mounted to an evaluating package and evaluated readily and simply.