Wafer level integrated interconnect decal and manufacturing method thereof

A wafer level integrated interconnect decal manufacturing method and wafer level integrated interconnect decal arrangement. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

FIELD OF THE INVENTION

The present invention relates to a wafer level integrated interconnect decal manufacturing method. In accordance with the current state of the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, there are employed underfills which comprise liquid encapsulates and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

Concerning the foregoing, in accordance with a conventional method, a liquefied underfill is ordinarily dispensed into and is adapted to fill a gap which is present between the semiconductor chip and the substrate through the intermediary of capillary force, subsequent to implementing the assembly of the chip to the substrate. In that connection, the capillary action is normally slow in nature in filling the interspace that is present between the semiconductor chip and the substrate, and thereafter the curing of the liquid underfill requires a lengthy time in a high-temperature or oven-like environment. Consequently, the currently employed types of underfill processes represent a bottleneck in the expenditure of manufacturing time. Moreover, due to the developing miniaturization aspects of the various electronic devices in the technology and industry, which renders the gap which is present between the semiconductor chip and substrate to become evermore narrow, the underfill method causes the entraining of voids in the electronic packages intermediate the semiconductor chips and the substrates, potentially adversely effecting the reliability thereof.

THE PRIOR ART

Heretofore, as set forth in the disclosure of Pennisi, et al., U.S. Pat. No. 5,128,746, there has been utilized a no-flow underfill which is intended to avoid the limitation encountered in the capillary flow of underfill, and which combines the aspects of solder joint reflow and underfill into a single process step. The no-flow segment in the filling process is concerned with dispensing the underfill material on the substrates prior to the placement of a single chip.

Pursuant to Shi, et al., U.S. Pat. No. 6,746,896 B1, there is disclosed a wafer level underfill method which is also intended to avoid the capillary flow of underfill, and which combines the solder joints reflow and underfill curing processes into a single step. However, the wafer level underfill is applied on a bumped wafer and the wafer is then diced into single chips, and thereafter each semiconductor chip with the underfill present thereon is aligned with and positioned on a substrate. In both of the foregoing instances of respectively the no-flow underfill and wafer level underfill processes there is, however, necessitated a separate solder bumping step on the semiconductor chip prior to the application of the underfill, and a thermal compression force is required in order to exclude the presence of any underfill material from the solder joints.

Pursuant to a further aspect which is described in Gruber, U.S. Pat. No. 5,673,846, the latter of which is commonly assigned to the Assignee of the present application, there is provided a unique and novel solder decal which is rendered possible through the application of an injection molding solder (IMS) process. In that instance, a decal is primarily employed as a mold and which is fixed in forming solder bumps on a wafer or on substrates. However, pursuant to the present invention, the decal can also be employed as the actual underfill material, wherein in one form, three superimposed layers of decals can produce solder features which are on both sides of one decal, i.e. a center decal, subsequent to peeling off the two other layers.

SUMMARY OF THE INVENTION

Accordingly, in order to improve upon the foregoing methods, an object of the present invention resides in simplifying the conventional steps of solder bumping on wafer and underfill processes and the further art relating to the solder anchoring decal and method of manufacture as described in U.S. Pat. No. 5,673,846 whereby, instead of effectuating underfill dispensing after solder bumping on the wafer according to a conventional process, pursuant to the present invention the solder bumping and underfill process method can be implemented independently of the wafer process, while avoiding the trapping of voids. Thus, while wafers are processed through Under Bump Metallurgy (UBM) deposition, and patterning processes implemented to facilitate wetting of solder, in a film-type underfill, which film in decal form has through-holes, the latter are filled with solder. Subsequent to the inspection of the underfill with the solder, it is attached to a wafer whereby this manner of processing reduces total cycle time and enables each process flow step to be optimized independently, thereby further reducing the overall or total time of the bumping process. Thereafter, the wafer is diced into single chips, and individual chips are placed on the substrates. This method is also applicable to a three dimensional stacking of wafers or individual dies.

DETAILED DESCRIPTION

Referring in particular to the drawings, applicants note thatFIGS. 1A-Cpertain to various prior art methods of utilizing underfill materials between semiconductor chips and substrates.

Thus,FIG. 1Adiscloses in sequence steps of a capillary underfill method whereby solder bumps10are attached to a semiconductor chip12, then the latter is positioned on a substrate14so as to cause outer located bumps10to form a gap16between the semiconductor chip12and the substrate14. Thereafter underfill material18in liquid form is filled into the gap16between the semiconductor chip and the substrate adapted to encompass the solder bumps. However, this method may lead to the entrapment of voids20between the bumps10, in view of the ever decreasing size of the gaps16due to the miniaturization of the electronic packages and various components in the current technology.

As indicated inFIG. 1Bof the drawings, in an exploded view there is illustrated a no-flow underfill method pursuant to the prior art wherein a semiconductor chip12having solder bumps10attached thereto is placed in spaced relationship with a substrate14, the surface of which is covered with a no-flow underfill material22. Thereafter the chip12with the solder bumps10are pressed into the no-flow underfill material. This, however, provides for the possibility that the underfill material22may coat the surface of at least some of the solder bumps to, resultingly preventing electrical contact with the substrate, and thereby adversely affecting the reliability of any electronic package formed by this process.

Furthermore, with regard toFIG. 1Cof the drawings, which also illustrates in a exploded manner, a prior art wafer level underfill method, in that instance, the semiconductor chip12with the solder bumps10attached thereto, leave the latter already encased in a wafer level underfill material24which with the chip and bumps is then pressed down onto the substrate14, and which may also, similar to the no-flow underfill, raise the possibility that the solder bumps10may be surface covered prematurely with underfill material24, which may inhibit any proper or reliable electrical contact with operative components on the substrate14.

Reverting to the invention inFIG. 2Aof the drawings, there are indicated three decal layers30,32,34which may be in the form of film webs, and wherein the upper layer30includes tapered or conical feature holes36, the center layer32also includes through holes38which are adapted to the aligned with the feature holes36and which layer32contains vacuum holes40around the periphery thereof, and further the third layer34also has tapered through holes42including vacuum holes44which are adapted to the aligned with those in the center layer32.

In essence, as shown inFIG. 2Bof the drawings, in both plan/view wherein the essentially circular wafer structure50comprises a pattern in a wafer size array for the different holes36,38,42which are aligned with respect to the superimposed upper, lower and center films, and wherein vacuum holes52arranged spaced about the rim54of a carrier56positioned beneath the lower film34are aligned with the vacuum holes44,40extending through the lower film34, and center film32contacting the facing surface58of the upper film30so as to clamp together all three film layers in an aligned position.

The carrier56may be constituted from material of a similar CTE (Coefficient of Thermal Expansion) and size as the wafer50, with the exception that it includes an outer attachment edge or rim portion. Hereby, all of the decals30,32,34may be constituted typically from a polyimide, such as Kapton, Upilex, Ultem (registered trademarks) which are able to withstand a subsequent IMS (Inspection Molding Solder) process which is conducted at the solder melting temperature. In particular, the center decal layer32which is utilized as the final underfill material may be made from a filler-containing polymer which will improve the required properties of CTE, modulus, etc.

Moreover, the collective through holes found in each of the upper, center and lower decals30,32,34can be produced either etched by photolithographical processes, laser drilling, or the like.

In particular, it is an important aspect to note that the upper and lower decals30,34which are on both sides of, respectively, the center decal32have the tapered holes36,42which enlarge in size towards the surfaces facing the through holes38which are aligned therewith in the center decal32. Thus, upon filling these aligned feature holes with solder60, as shown inFIG. 2C, it is then possible to remove in sequence, as inFIG. 2Dthe top decal or film layer30by peeling the latter away from the center decal32constituting the underfill material, and upon release of the vacuum from the aligned vacuum holes; thereafter as shown inFIG. 2E, a suitable adhesive62is dispensed onto the upper surface of the center decal32encompassing the projecting solder portion64which remains in place subsequent to the removal of the top layer film or decal30.

Alternatively, an adhesive may also be applied between the lower decal34and a carrier, which can be made from materials easily adhered to each other and separated by means of heat.

As illustrated inFIG. 2F, a wafer50having pads68which include Under Bump Materials (UBM)70is positioned onto the adhesive62and solder portions64, and engaged with the adhesive on the upper surface of the exposed surface of the center decal32.

Thereafter, as shown inFIG. 2Gof the drawings, the carrier56is removed from the lower surface of the lower or bottom decal34, thereby enabling the lower decal or bottom layer to be pulled away from the surface of the center decal32with which it is in contact, as shown inFIG. 2Hof the drawings, thereby exposing the opposite end portion72of the solder60projecting from the center decal32, the latter of which constitutes the underfill material.

As shown inFIG. 2I, after dicing the wafer (not shown), an adhesive74is then applied to the bottom surface of the center decal32, encompassing the projecting solder material72; and a substrate76is applied to the bottom surface of the decal32, as shown inFIG. 2J, contacting and compressing the adhesive74about the solder material portion72.

As shown in the alternative embodiment of FIG.2I(I-1), the wafer50is diced to form the chip80and the adhesive on the substrate assembly is dispersed, whereby the substrate76is then applied onto the adhesive74encompassing the lower surface of the center decal32.

In order to implement three dimensional 3D stacking, as shown inFIG. 2Kby wafer to wafer bonding, or alternatively die to die bonding, after dicing of the wafer this step may be implemented for subsequent three-dimensional (3D) stacking.

As shown inFIG. 3A, illustrated a silicon chip80with thick UBMs82and passivation layer96projecting therefrom, the underfill material comprising the essentially center decal84will be covered with a thin adhesive86,88on both sides thereof subsequent to implementing an IMS process, as previously described, and thereafter is effected a removal of the upper and lower decals.

Hereby, the lower surface of the underfill material providing decal84may be contacted by a substrate90having thick electrical pads92positioned thereon, and the entire assembly pressed together whereby the silicon chip80with the UBMs82thereon engages into the upper end of the solder material94with the adhesive86,88compressed therebetween, whereas at the lower surface, the substrate90with thick pads92is pressed into the lower end portions of the solder94and into contact with the lower surface of the underfill material84.

As shown inFIG. 3B, with the thick UBMs102and a thick pad104and with a single layer of film106, a silicon chip108having a thin adhesive layer110applied about the thick UBMs102facing towards the underfill material decal106, the latter of which is filled with solder112derived from the IMS process, a lower substrate114is positioned at the opposite side of the underfill material decal106, including the thick pad104, whereby the entire assembly is then pressed together, similar to the process as inFIG. 3A.

As shown inFIG. 4Athere is provided a wafer-to-wafer bonding structure120with thick UBMs122and a single layer of film124whereby a wafer126(rather than a silicon chip) is provided with thick UBMs122facing towards the single layer underfill material decal124having through openings128filled with solder130in an IMS process, and thin layers of adhesive132applied to both surfaces thereof subsequent to the IMS process having been implemented.

At the opposite side or lower side of the underfill material layer124, there is provided a similar wafer126with thick UBMs122facing towards the holes128filled with solder130facing at the bottom of the underfill material decal, and the components are then pressed together, whereby the upper wafer126presses into the solder130at the upper end with adhesive132interposed therebetween, and the lower wafer126presses into the lower end with the UBM's122in contact with the solder material130and also with an adhesive material layer132pressed therebetween.

As shown inFIG. 4B, there is provided a wafer to wafer bonding structure with thick UBMs122and decal of a single layer of film124, wherein the upper wafer with thick UBMs has a thin adhesive layer132applied thereabout, and a thin adhesive layer132is also applied to encompass the thick UBMs122projecting towards the underfill material decal124in a lower wafer at the opposite side of the underfill material whereby these are then compressed together such that the adhesive material is interposed between both wafers and the opposite surfaces of the underfill material decal and the UBMs of both the upper wafer and lower wafer contact into the solder130in each of the respective through holes128in the underfill material decal124.

In the modification as shown inFIG. 5Aof the drawings, there is provided a silicon chip140containing thick UBMs142facing towards the upper surface of a decal144and having solder filled holes146in the resultant underfill material. Adhesives148,150are applied to both sides onto the surfaces of the underfill material144, the upper adhesive layer148being somewhat thinner than the lower adhesive layer150, and which are both applied subsequent to the IMS process. Thereafter, a substrate154having a thick pads156, and silicon chip140are pressed together towards, respectively, the lower and upper surfaces of the underfill material decal144, with the adhesive layers being interposed therebetween, and the UBMs142entering into contact with the, respective, upper ends of solder160in the holes146, and the substrate pads156being in contact with the lower ends of the solder160projecting from the holes in the underfill material decal144.

Similarly, inFIG. 5Bof the drawings, showing thick UBMs142and a layer of film material144, a thin adhesive layer170encompasses the thick UBMs142depending from a silicon chip140, facing the solder filled holes146in the underfill material forming the decal144. A further thin adhesive layer172projecting from thick conductive pads174on a substrate176on the opposite of the decal144, enables these components then to be compressed, such that the UBMs142enter into the solder160at the upper end of the holes in the underfill material decal144whereas the projecting lower ends of the solder160come into contact with the pads174on the substrate176.

InFIG. 6A, similar toFIG. 4A, employing similar reference numerals for similar components, there is illustrated a wafer-to-wafer bonding structure120with thick UBMs180on an upper wafer126underfill decal of a single film layer182, with a thin adhesive184being applied to opposite surfaces thereof subsequent to an IMS process.

Furthermore, a lower wafer126having upwardly extending UBMs122is adapted to contact the universal holes192in the decal182, which are filled with the solder160during the IMS process, in order to produce interconnects between a chip and a substrate (not shown). These universal holes in the decal182forming the underfill material enable an electron flow in a direction which is not perpendicular but along the longitudinal direction of the structure, and enables the method to be applied to ultra-fine pitch products, saving process time since there is no requirement for any alignment to be present among the semiconductor chip, decal layer and the substrate components.

Finally, similar toFIG. 6A, as illustrated inFIG. 6Bof the drawing wafer-to-wafer bonding with thick UBM and one layer film is also applicable herein, wherein the upper and lower structural components are essentially identical in opposite directions and contain thick UBMs and adhesive material, a thin layer thereof encompassing the UBMs facing towards the underfill material decal containing the universal holes which are filled with the solder by the IMS process. As the wafers are pressed towards the opposing surfaces of the underfill material decal, the adhesive layers are contacting therebetween, and the UBMs on both sides contact the ends of each of the solder materials contained in the various universal holes formed in the underfill material decal.