Duty cycle corrector and converter for differential clock signals

Various techniques are provided to correct the duty cycles and convert differential clock signals in synchronized systems. In one example, a method includes receiving an input differential clock signal having a distorted duty cycle. The method also includes adjusting the input differential clock signal to provide an output differential clock signal with a corrected duty cycle. The adjusting is performed in response to signals provided by a differential amplifier and a common mode amplifier of an analog feedback circuit receiving the output differential clock signal. Additional methods and systems are also provided.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and the benefit of India Provisional Patent Application No. 202041050960 filed Nov. 23, 2020 and entitled “DUTY CYCLE CORRECTOR AND CONVERTER FOR DIFFERENTIAL CLOCK SIGNALS”, which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present invention relates generally to clock signals and, more particularly, to maintaining clock signal duty cycles in high speed circuits.

BACKGROUND

High speed electronic circuits frequently rely on corresponding high speed clock signals to maintain synchronization and facilitate accurate data transfers. However, increased clock speeds can increase the possibility of clock signal errors.

For example, clock signals used for serializing and deserializing data typically rely on strict 50 percent duty cycles to provide appropriate setup and hold time margins for high speed applications that utilize both positive and negative edge transitions of the clock signals. Such applications include, for example, double-data-rate (DDR) synchronous dynamic random access memory (SDRAM), double sampling analog-to-digital converters (ADCs), and half rate clock and data recovery.

However, clock signals often pass from a clock generator through long routings (e.g., circuit traces and/or clock trees) before ultimately being received by a destination circuit to be synchronized. Such configurations can make the clock signals susceptible to duty cycle distortions caused by variations in process, voltage and temperature (PVT). As a result, distorted clock signals that deviate from the original 50 percent duty cycle may be received by the destination circuit. As clock speeds increase, these unintended changes in duty cycle can adversely affect the setup and hold times that may be required to synchronize the destination circuit.

SUMMARY

In accordance with embodiments set forth herein, various techniques are provided to correct the duty cycles and convert differential clock signals in synchronized systems.

In one embodiment, a method includes receiving an input differential clock signal having a distorted duty cycle; adjusting the input differential clock signal to provide an output differential clock signal with a corrected duty cycle; and wherein the adjusting is performed in response to signals provided by a differential amplifier and a common mode amplifier of an analog feedback circuit receiving the output differential clock signal.

In another embodiment, a system includes a converter circuit configured to adjust an input differential clock signal having a distorted duty cycle to provide an output differential clock signal with a corrected duty cycle; an analog feedback circuit configured to receive the output differential clock signal, the feedback circuit comprising a differential amplifier and a common mode amplifier; and wherein the converter circuit is configured to adjust the input differential clock signal in response to signals provided by the differential amplifier and the common mode amplifier.

DETAILED DESCRIPTION

In accordance with various embodiments, systems and methods are provided to adjust (e.g., correct) differential clock signals used to synchronize high speed circuits (e.g., greater than 10 gigabits per second (Gbps) in some embodiments). In some embodiments, a clock correction circuit may be provided that adjusts the duty cycle of a differential clock signal. In some embodiments, the clock correction circuit may further convert a CML clock signal to an CMOS clock signal to facilitate interfacing synchronized high speed circuits with upstream circuit paths (e.g., circuit traces and/or clock trees).

In some embodiments, various advantages may be provided over conventional clock circuit implementations. For example, in some embodiments, the clock correction circuit may be implemented as a fully differential circuit with high accuracy that reduces jitter in the clock path due to a high power supply rejection ratio (PSRR) and a high common mode rejection ratio (CMRR). In some embodiments, the clock correction circuit may further convert a CML clock signal to a CMOS clock signal without degrading power supply rejection (PSR), in contrast with conventional circuits that are generally limited to CML output clock signals.

In some embodiments, alternating current (AC) coupling capacitors are provided upstream of a feedback circuit of the clock correction circuit (e.g., which helps optimize gain of CML input buffers for high speed designs), in contrast with conventional circuits that typically provide a feedback path directly from input buffers. In some embodiments, power savings may be achieved by not requiring extra current for duty cycle correction in a CML buffer stage of the clock correction circuit.

Turning now to the drawings,FIG. 1illustrates a clock correction circuit100in accordance with an embodiment of the disclosure. Clock correction circuit100receives an input differential clock signal at nodes102A-B (e.g., also referred to as input ports and labeled clkp and clkn respectively) and provides an output differential clock signal passed by output ports190A and190B (labeled outp and outn respectively).

In some embodiments, the input differential clock signal may be a differential CML clock signal having a duty cycle that varies from a preferred 50 percent duty cycle. As discussed, such variance may occur as a result of PVT effects on the input clock signal as it is passed from a clock generator through various circuit paths before being received by clock correction circuit100. In some embodiments, clock correction circuit100processes the differential CML clock signal to provide the output clock signal as a CMOS clock signal having a corrected duty cycle of 50 percent or approximately 50 percent.

As shown, clock correction circuit100includes a gain stage circuit110, a CML to CMOS converter circuit120, and an analog feedback circuit130. As also shown, feedback circuit130includes low pass filter circuits140A-B and a duty cycle adjustment circuit150. As further shown, duty cycle adjustment circuit150provides two feedback return paths, namely, a differential feedback return path including a differential amplifier circuit154and a common mode feedback return path including a common mode amplifier circuit158.

FIG. 2illustrates further details of gain stage circuit110in accordance with an embodiment of the disclosure. Gain stage circuit110operates to amplify the differential CML clock signal received at nodes102A-B to provide sufficient voltage swing to convert the differential CML clock signal to a CMOS clock signal. In particular, gain stage circuit110includes a buffer circuit210, a first active inductor stage circuit240, and a second active inductor stage circuit270.

Buffer circuit210is a resistor load differential buffer that receives the differential CML clock signal at nodes102A-B and provides a buffered differential CML clock signal having an appropriate common mode voltage at nodes212A-B (labeled outp1 and outn1).

First active inductor stage circuit240receives the buffered differential CML clock signal and amplifies it to provide a first amplified differential CML clock signal at nodes242A-B (labeled outp2 and outn2). As shown, first active inductor stage circuit240further includes transistors244A-B (e.g., labeled M10 and M9 operating in the deep-triode region) through which nodes242A-B are coupled to the gates of PMOS transistors246A-B (labeled M6 and M5) via source follower transistors248A-B (labeled M8 and M7), respectively. By adjusting the gate voltages of transistors244A-B (e.g., through appropriate control signals provided by control circuit830ofFIG. 8), they operate as variable resistors. As a result, the inductance exhibited by first active inductor stage circuit240will be correspondingly adjusted to affect the gain (e.g., amplification) of first active inductor stage circuit240exhibited at different frequencies.

For example,FIG. 6illustrates plots610A-F of the gain applied by first active inductor stage circuit240ofFIG. 2Bover a range of frequencies as different voltages are applied to transistors244A-B in accordance with an embodiment of the disclosure. The amplification exhibited by plots610A-F at different frequencies can be adjusted (e.g., tuned) in response to associated voltages applied to the control gates of transistors244A-B to provide desired amplification for different clock frequencies as appropriate. InFIG. 6, plots610A-F are associated with gate voltages of 0.5 volts, 0.4 volts, 0.3 volts, 0.2 volts, 0.1 volts, and 0.0 volts, respectively. As shown, such a configuration permits amplification across a range of high frequencies (e.g., from less than 10{circumflex over ( )}9 Hz to greater than 10{circumflex over ( )}10 Hz).

First and second active inductor stage circuits240and270may be implemented in a cascaded configuration as shown inFIG. 2. Second active inductor stage circuit270receives the first amplified differential CML clock signal and further amplifies it to provide a second amplified differential CML clock signal at nodes272A-B (labeled outp3 and outn3). As shown, second active inductor stage circuit240further includes transistors274A-B (labeled M18 and M17),276A-B (labeled M14 and M13), and278A-B (labeled M16 and M15) operating in a similar manner as discussed with regard to corresponding features of first active inductor stage circuit240.

FIG. 3illustrates further details of CML to CMOS converter circuit120in accordance with an embodiment of the disclosure. As shown, converter circuit120includes coupling capacitors310A and310B, an adjustment stage320, and an inverter stage380. As also shown, converter circuit120provides a fully differential circuit path comprising circuit path302A (e.g., also referred to as a PMOS circuit path) and circuit path302B (e.g., also referred to as an NMOS circuit path) to carry the complementary signals of a differential clock signal.

Capacitors310A-B receive the second amplified differential CML clock signal from nodes272A-B of second active inductor stage circuit240. Capacitors310A-B operate to filter out common mode voltage in the second amplified differential CML clock signal upstream of return paths of feedback circuit130to provide a filtered CML clock signal.

Adjustment stage320receives and adjusts the filtered clock signal to provide a corrected CMOS clock signal to nodes360A-B having an adjusted common mode voltage and a corrected duty cycle. In this regard, the common mode voltage and duty cycle of circuit path302A is set by a resistor322A, a current source324A, a transistor330(e.g., in response to a signal provided to node332from differential amplifier circuit154), and a transistor334(e.g., in response to a signal provided to node338(e.g., connected to shared gates of transistors334and336) by common mode amplifier circuit158. The common mode voltage and duty cycle of circuit path302B is set by a resistor322B, a current source324B, a transistor340(e.g., in response to a signal provided to node342from differential amplifier circuit154), and a transistor336(e.g., in response to the signal provided to node338by common mode amplifier circuit158).

Adjustment stage320adjusts the duty cycle of the differential clock signal in response to signals provided by a common mode loop and a differential loop of feedback circuit130. In this regard, the common mode loop including common mode amplifier circuit158provides a common mode feedback signal to node338feeding the gates of transistors334and336. The differential loop including differential mode amplifier circuit154provides differential feedback signals to nodes332and342feeding the gates of transistors330and340. Transistors330and334adjust the current flowing through resistor322A to provide the correct bias voltage to node360A, while transistors336and340adjust the current flowing through resistor322B to provide the correct bias voltage to node360B such that duty cycle at output nodes190A and190B is 50 percent. Current sources324A and324B provide duty cycle correction in both directions.

Inverter stage380receives the corrected differential CMOS clock signal and passes it through a plurality of inverters382disposed in circuit paths302A-B between nodes360A-B and output nodes190A-B to provide a buffer between adjustment stage320and output nodes190A-B. Inverter stage380further includes cross-coupled inverters384A-B that operate to reduce skew in the corrected CMOS clock signal.

Referring again toFIG. 1, as discussed, clock correction circuit100includes a feedback circuit130that includes low pass filter circuits140A-B and duty cycle adjustment circuit150. As shown inFIG. 1, the corrected differential CMOS clock signal provided to output nodes190A-B is passed back through feedback circuit130to facilitate duty cycle adjustment. In particular, the corrected differential CMOS clock signal is initially passed to low pass filter circuits140A-B for feedback circuit130.

FIG. 4illustrates low pass filter circuits140A and140B in accordance with an embodiment of the disclosure. Low pass filter circuit140A includes a resistor410A and a capacitor414A which operate as an RC circuit to perform low pass filtering on the PMOS circuit path complement of the corrected differential CMOS clock signal to provide an average voltage (e.g., as a result of the transient response time of the RC circuit determined by the values of resistor410A and capacitor414A) of the PMOS complement at node420A (labeled vfiltp).

Similarly, low pass filter circuit140B includes a resistor410B and a capacitor414B which operate as an RC circuit to perform low pass filtering on the NMOS circuit path complement of the corrected differential CMOS clock signal to provide an average voltage (e.g., as a result of the transient response time of the RC circuit determined by the values of resistor410B and capacitor414B) of the NMOS complement at node420B (labeled vfiltn).

In some embodiments, a difference in the average voltages at nodes420A-B may indicate a duty cycle error between the two clock complements that differs from a desired 50 percent duty cycle. The voltages of nodes420A-B are provided to differential amplifier circuit154to correct the duty cycle as further discussed herein.

As further shown inFIGS. 1 and 4, low pass filter circuits140A-B are connected to resistors412A-B to provide an average of the voltages of nodes420A-B at a node430(labeled Vfilt_cm). In this regard, a voltage at node430that differs from an expected 50 percent average (e.g., different from 50 percent of a supply voltage), may indicate a differential duty cycle error between the complementary signals of the differential clock signal. Accordingly, the voltage of node430may be provided to common mode amplifier circuit158to correct differential duty cycle error as further discussed herein.

FIG. 5Aillustrates differential amplifier circuit154in accordance with an embodiment of the disclosure. As shown, the average voltages of nodes420A and420B are provided to the gates of transistors510A and510B. It will be appreciated that differences in the voltages at nodes of nodes420A and420B will cause the voltages of nodes332(dcp) and342(dcn) to be pulled up or down inversely (e.g., adjusted in opposite amounts). For example, if node420A exhibits a higher voltage than node420B (e.g., associated with the PMOS circuit path clock signal complement exhibiting a longer duty cycle than the NMOS circuit path clock signal complement), then node332(dcp) will be pulled to a lower voltage than node342(dcn). As a result, when the voltages of nodes332and342are applied to the gates of transistors330and340of converter circuit120, transistor340will pass more current from resistor322B than transistor330passes from resistor322A to adjust the duty cycle. It will be appreciated that these operations can be reversed if node420A exhibits a lower voltage than node420B.

By continuously adjusting the voltages provided to nodes332and342, the complementary signals of the differential clock signal at nodes360A-B can be adjusted to maintain duty cycles equal to each other such that the duty cycle error difference between output nodes190-A is equal to or approaches zero.

FIG. 5Billustrates common mode amplifier circuit158in accordance with an embodiment of the disclosure. As shown, the voltage of node430(e.g., corresponding to an average of the voltages of nodes420A and420B) is provided to the gate of a transistor530while a fixed voltage (e.g., half a supply voltage labeled Vdd/2) is provided to node542corresponding to the gate of transistor540.

As discussed, a voltage at node430that differs from an expected 50 percent average may indicate a differential duty cycle error between the complementary signals of the differential clock signal. Accordingly, if the voltage of node430varies from the fixed voltage of node542, this will result in changes in the voltage of node338provided to transistors334and336of converter circuit120. In this regard, as the voltage at node338changes, transistors334and336will pass currents equally from resistors322A and322B to adjust the duty cycle.

By continuously adjusting the voltage provided to node430, the duty cycles of the complementary signals of the differential clock signal can be adjusted to exhibit an average duty cycle equal to or approaching 50 percent such that the differential clock signal exhibits a duty cycle equal to or approximately 50 percent.

FIG. 7illustrates plots710and720of distorted and corrected clock signals in accordance with an embodiment of the disclosure. Plot710illustrates the complements of the differential CML clock signal received at nodes102A and102B. As shown, the complements in plot710exhibit substantial distortion (e.g., deviation from a desired 50 percent duty cycle) with a duty cycle of approximately 35 percent.

Plot720illustrates the complements of the corrected differential CMOS clock signal provided at output nodes190A-B. As shown, the complements in plot720have been corrected with output nodes190A-B each exhibiting a duty cycle of approximately 50 percent.

Clock correction circuit100may be implemented in various host systems as appropriate, such as logic devices, consumer electronics devices, and/or other systems. For example,FIG. 8illustrates a host system800comprising clock correction circuit100ofFIG. 1and additional components in accordance with an embodiment of the disclosure.

A clock generator810(e.g., a phase lock loop (PLL) or other appropriate circuit) provides a CML differential clock signal to be used for synchronizing a destination circuit840(e.g., a synchronized circuit such as a serializer/deserializer (SerDes) circuit and/or other types of circuits as appropriate). When initially provided to nodes812A-B, the CML differential clock signal may exhibit a duty cycle of 50 percent as shown inFIG. 8. However, as the CML differential clock signal is distributed through various circuit paths820(e.g., circuit traces, clock trees, and/or other circuits providing clock distribution circuit paths) on its way to destination circuit840, it may exhibit changes in its duty cycle caused by PVT variations introduced as the CML differential clock signal passes through circuit paths820. As a result, when the CML differential clock signal is ultimately received at nodes102A-B of clock correction circuit100, it may exhibit duty cycle distortion as shown inFIG. 8and also similarly discussed with regard to plot710ofFIG. 7.

Clock correction circuit100may operate to convert the CML differential clock signal to a CMOS clock signal and also adjust its duty cycle as discussed. As also shown, one or more control circuits830(e.g., implemented by associated logic circuits, microcontrollers, processors, and/or other circuitry) may be used to provide control signals to clock correction circuit100to facilitate such operation as appropriate. As a result, clock correction circuit100provides a corrected CMOS differential clock signal to output nodes190A-B for use by destination circuit840.

FIG. 9illustrates a process performed by clock correction circuit100ofFIG. 1and host system800ofFIG. 8in accordance with an embodiment of the disclosure. It will be appreciated that the process ofFIG. 9may be performed in accordance with the various principles discussed herein with regard toFIGS. 1 to 8.

In block910, clock generator810generates a differential CML clock signal that is provided to nodes812A and812B. In block912, the differential CML clock signal passes through one or more circuit paths820to nodes102A and102B of clock correction circuit100.

In block914, the differential CML clock signal is buffered by buffer circuit210. In block916, the buffered differential CML clock signal is amplified by first and second active inductor stage circuits240and270. In some embodiments, the amplification may be adjusted to operate over a desired frequency range (e.g., as discussed with regard toFIG. 6) to accommodate high speed clock signals.

In block918, the amplified differential CML clock signal is filtered by coupling capacitors310A-B. In block920, adjustment stage320operates to convert the amplified differential CML clock signal to a differential CMOS clock signal. Also in block920, adjustment stage operates to adjust the duty cycle of the differential CMOS clock signal as discussed. In block922, the differential CMOS clock signal is passed through inverter stage380.

In block924, the differential CMOS clock signal is provided to destination circuit840at output nodes190A-B (e.g., a corrected differential clock signal). Accordingly, it will be appreciated that block924may also include synchronizing destination circuit840using the differential CMOS clock signal such that destination circuit840is effectively synchronized with the original CML clock signal provided by clock generator810.

In blocks926to932, the differential CMOS clock signal is processed by feedback circuit130to provide appropriate adjustment signals (e.g., voltages) to perform the duty cycle adjustment of block920. Accordingly, in block926, the differential CMOS clock signal is passed to feedback circuit130.

In block928, the differential CMOS clock signal is filtered by low pass filter circuits140A-B. In block930, differential amplifier circuit154operates to adjust the duty cycle of the differential CMOS clock signal as discussed. In block932, common mode amplifier circuit158operates to adjust the duty cycle of the differential CMOS clock signal as discussed.

Following block932, the process returns to block920where the duty cycle of the differential CMOS clock signal continues to be corrected in realtime through successive iterations of blocks920to932.

In view of the present disclosure, it will be appreciated that clock correction circuit100may be used to adjust the duty cycle of differential clock signals in high speed systems with clock speeds in excess of 10 GHz. For example, by feeding back the corrected differential CMOS clock signal after gain stage circuit110, buffer circuit210may be implemented to operate on high speed differential CML clock signals. In addition, by implementing clock correction circuit100with a fully differential circuit path, jitter associated with power supply can be reduced. Moreover, as discussed, clock correction circuit100permits differential CML clock signals to be converted to CMOS clock signals at high speeds.

In addition, by implementing feedback path130as analog circuit, the duty cycle adjustment signals provided to nodes332,338, and342may be continuously adjusted with high precision to perform common mode and differential duty cycle adjustments to the complementary signals of the differential clock signal to provide a desired 50 percent duty cycle for the differential clock signal. This provides improved precision and accuracy in adjusting and maintaining the duty cycle in contrast to conventional digital systems that rely on the sizing of inverters and related capacitive loading to maintain duty cycles.

Where applicable, various embodiments provided by the present disclosure can be implemented using hardware, software, or combinations of hardware and software. Also where applicable, the various hardware components and/or software components set forth herein can be combined into composite components comprising software, hardware, and/or both without departing from the spirit of the present disclosure. Where applicable, the various hardware components and/or software components set forth herein can be separated into sub-components comprising software, hardware, or both without departing from the spirit of the present disclosure. In addition, where applicable, it is contemplated that software components can be implemented as hardware components, and vice-versa. Embodiments described above illustrate but do not limit the invention. It should also be understood that numerous modifications and variations are possible in accordance with the principles of the present invention. Accordingly, the scope of the invention is defined only by the following claims.