Pin-assignment method for integrated circuit packages to increase the electro-static discharge protective capability

A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus of the IC chip. This allows for an increased ESD protective capability for the no-connect pins. Moreover, the pin-assignment method can simplify the wiring complexity of the IC package.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates in general to a pin-assignment method for integrated circuit (IC) packages, which can allow an increase in the electro-static discharge (ESD) protective capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power line, whereby the IC chip can be increased in its ESD protective capability and simplified in its wiring complexity.

2. Description of Related Art

Electrostatic discharge (ESD) is a movement of static electricity from a nonconductive surface, which usually causes damage to the semiconductors and various other circuit components in IC chips. A person walking on a carpet, for instance, can carry an amount of electrostatic charge up to several thousands of volts under high relative humidity (RH) conditions and over 10,000 volts under low relative humidity conditions. If such a person touches an IC chip by hand, the electrostaticity on his/her body would instantaneously be discharged to the IC chip, thus causing damage to the IC chip. The ESD damage is particularly common and severe on CMOS (complementary metal-oxide semiconductor) IC devices.

To protect IC chips against ESD damage, various solutions have been proposed. One solution suggests the provision of an ESD protective circuit between the internal circuit of the IC chip and each of the bonding pads.FIG. 1shows a conventional pin-assignment method used on an IC package. As shown, the IC package includes an IC chip on which an internal circuit20and a plurality of bonding pads11,13,15are formed. Further, the IC package includes a plurality of pins10,12,14,16,17,18,19on the periphery thereof, of which the pin10is a power pin (i.e., VDDor VSSpin) which is internally connected via a bonding wire100to the bonding pad11; the pin12is an I/O pin which is internally connected via a bonding wire120to the bonding pad13; the pin14is an input pin which is internally connected via a bonding wire140to the bonding pad15; and the other pins16,17,18,19are not in use (not wired) and thus are referred to as “no-connect pins”. To prevent ESD current from flowing via the bonding pads11,13,15into the internal circuit, each of the bonding pads11,13,15is connected to a ESD protective circuit (not shown).

A trend in IC packaging is to provide a larger number of pins on a single package so as to achieve the purpose of a high packing density of pins on the IC package. Since the IC package is very small in size, the increased number of pins will cause the gap (i.e., the pitch) between two adjacent pins, as indicated by the reference numeral G inFIG. 1between the pins14and19, to be further reduced. The reduction of the pin gap, however, causes a new problem in ESD protection for the IC package. This problem is described in a paper entitled “New Failure Mechanism due to No-Connect Pin ESD Stressing” which is authored by Matsumoto et al. and published in 1994 EOS/ESD Symposium, pp. 90-95. This paper reveals the fact that, when a human body model (HBM) ESD pulse is repeatedly applied to a certain no-connect pin on the IC package, any of its two neighboring pins, if wired to the internal circuit, would become particularly vulnerable to ESD damage. This is because that the electrostatic charge will accumulate in the resin around the no-connect pin, thus resulting in a large potential difference between the no-connect pin and its neighboring pins, thus significantly reducing the ESD resistant capability of the neighboring pins.

Taking the IC package ofFIG. 1as an example, assume that the input pin14is able to withstand a maximum of ESD stress of 3 kV (kilovolt), then when an ESD stress of 1.5 kV is applied to the no-connect pin19, the electrostatic charge therefrom will accumulate in the resin around the no-connect pin19, eventually resulting in a large potential difference between the no-connect pin19and its neighboring pins (i.e.,14,18). When this potential reaches a large enough level, it would cause a sudden ESD current to flow through the gap G to the neighboring pin14. Said ESD current will then flow from the pin14via the bonding wire140and the bonding pad15to the internal circuit, whereby an ESD damage could occur. In short, when an ESD stress of 3 kV is being applied to the pin14, the internal circuit of the IC chip wired to the pin14would not be damaged thereby; however, the application of an ESD stress of 1.5 kV to the no-connect pin19would cause ESD damage to the internal circuit wired to the neighboring pin14.

Early types of IC packages have only a small number of pins thereon, so the above-mentioned proximity problem that would cause ESD damage is unobvious. However, newer types of IC packages, such as QFP (quad flat packages), MQFP, TQFP, etc., usually come with more than one hundred pins that are packed in plastic or resin compounds. With such a large number of pins on a small-size IC package, the above-mentioned proximity problem becomes a serious consideration. One conventional solution to this problem is to increase the ESD protective capability of the input and I/O pins of the IC package to a higher level, for example from 2 kV to 4-5 kV. This scheme can protect the input and I/O pins of the IC package against ESD damage when any of its neighboring no-connect pins is subjected to an ESD stress of 2 kV. One drawback to this solution, however, is that the ESD protective circuitry needed to provide such an ESD protective capability will take up more area on the IC chip, thus increasing the chip size.

On an IC package, those pins that are electrically and functionally engaged, such as input pins, output pins, I/O pins, and power pins, are referred to as active pins. Each active pin is electrically wired to a bonding pad and an ESD protective circuit. Typically, the circuit connected to the power buses on the IC chip has the highest ESD protective capability since the power pins are connected to the power bus VDDor VSS. In addition to its high ESD capacity, each power bus has a capacitance of from 1 nF (nanofarad) to 10 nF formed between the N-well and P-well, or between the N-well and the substrate of the IC chip, which can absorb a great amount of charges from ESD. The input pins, I/O pins and output pins are inferior to the power pins in ESD protective capability.

FIGS. 2A and 2Bare schematic diagrams used to depict two conventional pin-assignment methods used for pin assignment on IC packages.

Referring toFIG. 2A, the IC package shown here includes an IC chip58having a plurality of bonding pads42,44,46,48formed thereon. Further, the IC-package includes a plurality of pins30,32,34,36,38,40, which are respectively assigned as a VSSpower pin, an input pin, a first no-connect pin, a VDDpower pin, a second no-connect pin, and an I/O pin. The VSSpower pin30, the input pin32, the VDDpower pin36, and the I/O pin40are wired respectively via a plurality of bonding wires50,52,54,56to the bonding pads42,44,46,48; while the first and second no-connect pins34,38are unwired. Via the bonding pads42,44,46,48, these active pins (i.e.,30,32,36,40) are functionally connected to the internal circuit of the IC chip58.

Referring toFIG. 2B, the IC package shown here includes an IC chip88having a plurality of bonding pads72,74,76,78formed thereon. Further, the IC package includes a plurality of pins60,62,64,66,68,70, which are respectively assigned as a VSSpower pin, an input pin, a first no-connect pin, a second no-connect pin, an I/O pin, and a VDDpower pin. The VSSpower pin60, the input pin62, the I/O pin68, and the VDDpower pin70are wired respectively via a plurality of bonding wires80,82,84,86to the bonding pads72,74,76,78; while the first and second no-connect pins64,66are unwired. Via the bonding pads72,74,76,78, these active pins (i.e.,60,62,68,70) are functionally connected to the internal circuit of the IC chip88.

It can be seen fromFIGS. 2A and 2Bthat, by the conventional pin-assignment methods, the no-connect pins are arranged arbitrarily; in the case ofFIG. 2A, for example, the no-connect pins are arranged next to the input pin, the VDDpower pin, and the I/O pin; while in the case ofFIG. 2B, the no-connect pins are arranged next to the input pin and the I/O pin. These pin-assignment methods take no consideration of ESD protections. Therefore, when these pin-assignment methods are utilized on IC packages with a high density of pins, the arrangement of the no-connect pins next to ESD-sensitive pins could cause the problem of ESD damage.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide a pin-assignment method for an IC package, which can increase the ESD protective capability for the IC chip encased in the IC package and also simplify the complexity of the ESD protective circuitry needed to provide the ESD protective capability.

In accordance with the foregoing and other objectives of the present invention, a pin-assignment method capable of increasing the ESD protective capability of an IC chip is provided. The pin-assignment method organize said no-connect pins into at least one group including either one no-connect pin or a number of consecutive no-connect pins, and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus. Fundamentally, the pins of an IC package are organized in such a manner that the no-connect pins are set apart into a plurality of groups, each group containing one no-connect pin or a number of consecutive no-connect pins, and each of the two pins that bound each no-connect pin group is assigned to a power line. This allows for an increased ESD protective capability for the no-connect pins.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In accordance with the invention, the pins of an IC package are organized in such a manner that the no-connect pins are set apart into a plurality of groups or at least one group, with each group containing one single no-connect pin or a number of consecutive no-connect pins, and then each of the two pins that bound both sides of each no-connect pin group is assigned to be a power pin, such as a power pin VDD, a power pin VSS, or a ground pin GND, for electrically connect to a power bus VDD, a power bus VSS, or a ground bus GND of the IC chip. This arrangement is based on the fact that the pins that are connected to a power bus can better withstand the condition of its neighboring no-connect pin being subjected to an ESD-stress of 5 kV. Therefore, in this case, the ESD protective circuitry for the power pins needs not be expanded while nonetheless retaining good ESD protective capability.

FIG. 3is a schematic diagram depicting the pin-assignment method according to the invention for pin assignment on an IC package. The IC package includes an IC chip134having a plurality of bonding pads116,118,122,124formed thereon. Further, the IC package includes a plurality of pins102,104,106,108,112,114which are assigned respectively as an input pin, a VSSpower pin, a first no-connect pin, a second no-connect pin, a VDDpower pin, and an I/O pin. The input pin102is internally wired via a bonding wire126to the bonding pad116; the VSSpower pin104is internally wired via a bonding wire128to the bonding pad118; the VDDpower pin112is internally wired via a bonding wire130to the bonding pad122; the I/O pin114is internally wired via a bonding wire132to the bonding pad124; and the no-connect pins106,108are unwired. The two no-connect pins106,108are consecutive in order on the IC package and therefore are considered as one group. In accordance with the invention, the two pins that bound both sides of this no-connect pin group, i.e., the pin104and the pin112, are each assigned as a power line; for example, in the case ofFIG. 3, the pin104is assigned as a VSSpower pin, while the pin112is assigned as a VDDpower pin. With this arrangement, the ESD stress applied to the two no-connect pins106,108would substantially cause no ESD damage to other pins. The no-connect pins106,108therefore need not be connected to additional ESD protective circuits.

FIG. 4is a schematic top view of an IC package used to depict the definition of “no-connect pin group” in accordance with the pin-assignment method of the invention. The IC package200here is a quad flat package having four sides and four corners. A no-connect pin group is defined as a single no-connect pin or a number of consecutive no-connect pins. If two no-connect pins are arranged on the same corner but on different sides, for example the pin216and the pin218, on the angle214, the pin224and the pin226on the angle222, and the pin230and the pin236on the corner228, they are still considered as consecutive and thus belong to the same group.

In the case ofFIG. 4, for example, assume the following no-connect pin groups are arranged: the pins216,218,220; the pin202; the pins224,226; the pins204,206,208; and the pins234,236,230,232. In accordance with the invention, each no-connect pin group should be bounded by two power pins. Therefore, the two pins238,240which bound the consecutive group of no-connect pins216,218,220are each assigned as a power pin; the two pins242,244which bound the single no-connect pin202are each assigned as a power pin; the two pins246,248which bound the consecutive group of no-connect pins224,226are each assigned as a power pin; the two pins250,252which bound the consecutive group of no-connect pins204,206,208are each assigned as a power pin; and the two pins254,256which bound the consecutive group of no-connect pins234,236,230,232are each assigned as a power pin. The power pins can be electrically connected to the power bus VDD, the power bus VSS, or the ground bus GND of the IC chip.

Further to the benefit of an increased ESD protective capability, the pin-assignment method of the invention can allow for easy bonding of wires onto those bonding pads that are connected to power pins. This benefit is described in the following with reference to FIG.5.

Referring toFIG. 5, the IC package shown here includes an IC chip334having a plurality of bonding pads316,318,324formed thereon. Further, the IC package includes a plurality of pins302,304,306,308,312,314which are respectively assigned as an input pin, a first power pin, a first no-connect pin, a second no-connect pin, a second power pin, and an I/O pin. The input pin102is internally connected via a bonding wire326to the bonding pad316; and the I/O pin314is internally connected via a bonding wire332to the bonding pad324. The pin-assignment method here differs from that shown inFIG. 3only in that the two power pins (i.e.,304,312) that bound the consecutive group of no-connect pins306,308is wired to a common bonding pad (i.e., respectively via the bonding wire328and the bonding wire330to the same bonding pad318. This arrangement also can prevent the ESD stress applied to the two no-connect pins306,308from causing ESD damage to other pins. Therefore, the bonding pads on the IC chip can be arranged in such a manner that at least one bonding pad used for power connection is disposed near each no-connect pin group. This allows the same bonding pad to be wired to the two power pins that bound the no-connect pin group, thus saving the number of bonding wires that can reduce the manufacturing cost.

The invention is characterized in that the pins of an IC package are organized in such a manner that the no-connect pins are set apart into a plurality of groups or at least one group, with each group containing one single no-connect pin or a number of consecutive no-connect pins, and then each of the two pins that bound both sides of each no-connect pin group is assigned as a power pin. The invention not only can provide an increased ESD protective capability, but also allow for a reduced wiring complexity and thus the manufacturing cost. The pin-assignment method of the invention is useful on IC packages with plastics or resin compounds, such as QFP, MQFP, and TQFP. Besides, the pin-assignment method of the invention is particularly useful to provide an increased ESD protective capability when used on IC packages having more than 100 pins, of which at least five are no-connect pins, such as 100-pin, 128-pin, and 160-pin IC packages having at least five no-connect pins, or on IC packages with more than 200 pins, of which at least 10 are no-connect pins, such as 208-pin IC packages having at least 10 no-connect pins.