Method for self-aligned punchthrough implant using an etch-back gate

A self-aligned MOSFET incorporating a punchthrough implant, and the method for forming such a transistor. A dielectric layer is used as a hard mask over a semiconductor substrate. A portion of the dielectric layer is removed to expose a region of the semiconductor substrate. A punchthrough implant is made with the remaining portion of the dielectric layer acting as a mask layer such that the doping concentration is raised by the punchthrough implant only in the exposed region of the semiconductor substrate. A doped layer of polysilicon is formed over the region into which the implant was made to provide a self-aligned gate over the highly doped region. A source and drain are formed on opposite sides of the doped region. A protective layer is formed over the device and metallized contacts are formed to the source, drain, and gate.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to the field of fabrication of semiconductor 
transistors. Specifically, the present invention relates to the formation 
of MOS devices. 
2. Prior Art 
Metal-Oxide-Silicon, MOS, transistors such as Field Effect Transistors, 
MOSFETs, are well known in the art. Such devices are typically formed 
having a source region and a drain region, of similar conductivity type, 
separated by a channel region, of a differing conductivity type, capped 
with a conductive gate. The gate to source voltage controls the passage of 
current through the channel between the source and the drain regions. In 
typical n-channel operation, a positive voltage is applied between the 
drain and the source with the source grounded to a reference potential. 
Due to the differing conductivity type of the channel separating the 
source and the drain, usually no current flows between the source and 
drain. However, if a sufficiently large voltage is applied between the 
gate and source, the conductivity in the channel region will increase, 
thereby allowing current to flow between the source and the drain. The 
gate voltage required to induce the flow of current between the drain and 
the source is referred to as the threshold voltage. 
Under certain circumstances, however, unwanted current flow may occur 
between the source and the drain even when no voltage is applied to the 
gate. Such a condition may be due to avalanche breakdown or punchthrough. 
Punchthrough occurs when the MOS transistor is biased in an off state with 
the gate and the source both at approximately zero volts with respect to 
ground, but with the drain at a voltage as high as 5 volts. Even though no 
flow of current is desired, drain current may still occur regardless of 
the zero gate voltage. This is due to the fact that under such conditions, 
the normal doping concentration of the channel region is not sufficient to 
prevent current flow between the source and drain regions. 
In order to eliminate punchthrough currents, the doping concentration in 
the substrate of the MOS device is raised. A high energy or so-called 
"punchthrough" implant is used to locally raise the doping concentration 
of the MOS device substrate. Typically, the "punchthrough" implant is made 
as a blanket implant over the active region of the MOS device. 
Unfortunately, the punchthrough implant also raises the doping 
concentration of the substrate in the source and drain region. As a 
consequence of the increased doping concentration, the source-drain 
junction capacitance is also increased. 
Furthermore, MOS semiconductor transistors, such as MOSFETs, often 
experience current leakage and other problems due to short channel 
lengths. The short channel, which occurs as a consequence of difficult to 
control manufacturing processes, results in closely spaced source and 
drain regions. Due to the close proximity of the source to the drain, 
current leakage or other "short channel" effects may hamper the 
performance of the semiconductor device. 
Consequently, a need exists to prevent punchthrough effects in 
semiconductor devices such as MOSFETs using a high energy or punchthrough 
implant without substantially increasing source-drain junction 
capacitance, and which minimizes short channels effects. 
SUMMARY OF THE INVENTION 
One embodiment of the present invention provides a self-aligned 
semiconductor MOS transistor which minimizes punchthrough currents and 
short channel effects without increasing source-drain junction 
capacitance, and the method for forming such a transistor. This is 
accomplished by performing a punchthrough implant while using a dielectric 
layer as a hard mask to confine the region of the implant to only the 
channel region of the semiconductor device. In so doing, the doping 
concentration is increased by the punchthrough implant in the channel 
region without causing unwanted punchthrough implant overlap of the source 
or drain regions of the device. Furthermore, by increasing the doping 
concentration in the channel region, current leakage and other problems 
associated with short channel lengths are minimized. 
Additionally, the present invention also provides a self-aligned gate 
formed over the doped channel region which allows the source and drain to 
be properly spaced so as to minimize short channel effects. The dielectric 
layer used to confine the punchthrough implant to the channel region of 
the device also allows the dimensions of the gate to be more precisely and 
easily controlled than was possible using standard gate formation 
processes. 
In another embodiment of the present invention, a large tilt angle 
implanted drain, "LATID", technology is used to form the source region and 
drain regions of the MOSFET of the present invention. In such an 
embodiment, the source and drain regions are formed into the semiconductor 
substrate before the gate of the MOSFET is formed. By forming the source 
and drain regions with a LATID implant, the gate region can be formed 
fully overlapping a portion of both the source and drain region, thereby 
improving hot carrier reliability.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Reference will now be made in detail to the preferred embodiments of the 
invention, examples of which are illustrated in the accompanying drawings. 
While the invention will be described in conjunction with the preferred 
embodiments, it will be understood that they are not intended to limit the 
invention to these embodiments. On the contrary, the invention is intended 
to cover alternatives, modifications and equivalents, which may be 
included within the spirit and scope of the invention as defined by the 
appended claims. 
With reference to FIG. 1A, a cross-sectional view of the MOS device of the 
present invention is shown illustrating the starting step used in the 
fabrication of such a device. A p-doped silicon substrate 20, having a 
first sacrificial gate oxide layer 22 and field oxide layers 24 formed 
thereon, is shown. Although the p-doped silicon semiconductor substrate 20 
is formed of silicon in the preferred embodiment, any other suitable 
semiconductor material may be used. Additionally, the substrate 20 may 
also have a different conductivity type if desired or may have been 
subsequently doped as in any standard CMOS type process. Although a MOSFET 
is formed in the present embodiment, the methods of the present invention 
are also well suited to other MOS devices. The first sacrificial gate 
oxide layer 22 is then removed from the semiconductor substrate 20. The 
first sacrificial gate oxide layer 22 may be etched from the substrate 20 
using a plasma etch or any of the numerous etching techniques well known 
in the art. Furthermore, in the present preferred embodiment of the 
present invention, an n-MOS transistor is formed. However, the following 
description would also apply to the formation of a p-MOS type transistor 
by reversing the conductivity types of the dopants. 
As shown in FIG. 1B, a second sacrificial gate oxide layer 26 is then grown 
over the semiconductor substrate 20. Note that by forming and removing the 
first sacrificial oxide layer as shown 22 in FIG. 1A, the semiconductor 
substrate 20 is better prepared for subsequent wafer fabrication 
processes. The sacrificial oxide is SiO.sub.2 and is thermally grown. 
Next, a shielding layer 28 of dielectric material is deposited over the 
semiconductor substrate 20 such that second sacrificial gate oxide layer 
26 is disposed between the semiconductor substrate 20 and the dielectric 
shielding layer 28. The dielectric shielding layer 28 is formed of silicon 
nitride in the present embodiment, however, any other dielectric shielding 
layer would also be suitable. Additionally, in this preferred embodiment 
of the present invention, the dielectric shielding layer 28 is deposited 
to a thickness of approximately 2000 to 5000 angstroms. Although the 
above-stated thickness is used in the preferred embodiment of the present 
invention, variations in the thickness of the dielectric shielding layer 
28 may be made based on the needed gate length and/or shielding 
requirements. 
Referring now to FIG. 1C, a photoresist layer 30 of photoresist material is 
deposited over the dielectric shielding layer 28 such that the dielectric 
shielding layer 28 is disposed between the photoresist layer 30 and the 
second sacrificial gate oxide layer 26. Photoresist layer 30 is formed of 
a suitable photosensitive material and processed using standard 
techniques. 
With reference now to FIG. 1D, a photomasking operation is used to 
selectively remove a portion of the photoresist layer 30 and the 
dielectric shielding layer 28 such that an area 32 of the semiconductor 
substrate 20 is covered only by the second sacrificial gate oxide layer 
26. The area 32 extends lengthwise for a distance L across the 
semiconductor substrate 20. 
Referring now to FIG. 1E, a "punchthrough" implant and threshold voltage 
adjust implant are made with the remaining portion of the dielectric 
shielding layer 28 acting as a hard mask layer, and the photoresist layer 
30 adding additional protection for the remaining covered portions of the 
substrate 20. In so doing, the doping concentration is raised by the 
punchthrough implant only in a localized region 34 of the semiconductor 
substrate 20. A dopant having the same conductivity type as the 
semiconductor substrate 20, which is p-type in one preferred embodiment of 
the present invention, is used for both the threshold voltage adjust and 
the punchthrough implant. Generally, the punchthrough implant will be of 
the same conductivity type as the substrate. The threshold voltage implant 
may have a differing conductivity type depending upon the need. For a 
typical CMOS process, however, the threshold voltage implant will be 
p-type for both n-channel and p-channel transistors. The punchthrough 
implant is made at high energy. In this preferred embodiment of the 
present invention, the punchthrough implant is made at an energy of at 
least 100 KeV, and preferably in the range of 100-150 KeV. Furthermore, 
although the voltage threshold adjust implant is made before the 
punchthrough implant, in a preferred embodiment of the present invention, 
the present invention is equally well suited to having the voltage 
threshold adjust implant made after the punchthrough implant. 
With reference still to FIG. 1E, the doped region 34 functions as the 
channel of the MOS device of the present invention. Thus, the doping 
concentration of the substrate 20 is only increased in the channel region 
34 of the device and not in the source and drain regions as found in prior 
semiconductor devices. Therefore, the present invention is able to 
minimize punchthrough and short channel effects by doping only the channel 
region 34 without substantially increasing the source-drain junction 
capacitance. This is in contrast to the prior art which uses a blanket 
punchthrough implant. 
Referring next to FIG. 1F, the remaining portions of the photoresist layer 
30 of FIG. 1E are removed, and the portion of the second sacrificial gate 
oxide layer 26 of FIG. 1E, which resides in the area above the channel 
region 34 of substrate 20, is removed. In a preferred embodiment of the 
present invention, the photoresist layer is not removed until after the 
punchthrough and voltage threshold adjust implant have been made so that 
the photoresist layer may provide additional protection for the substrate 
20. However, the methods of the present invention are equally well suited 
to having the photoresist layer removed before the punchthrough and 
voltage threshold adjust implants are made. 
With reference now to FIG. 1G, a new portion 36 of a gate oxide layer is 
formed over the channel region 34, as illustrated. 
As shown in FIG. 1H, a layer of polysilicon 38 is formed over the channel 
region 34 and the dielectric layer 28. The polysilicon layer 38 is doped 
with a dopant having a conductivity which can be different from the 
conductivity of the substrate 20 and the channel region 34. In order to 
insure that polysilicon layer 38 fills in the volume above the channel 
region 34, the polysilicon layer 38 is formed having a depth which is, for 
example, at least half as great as the dimension L of the volume from 
which the dielectric layer has been etched. 
Referring now to FIG. 1I, the doped layer of polysilicon is selectively 
removed such that only that portion 40 of the polysilicon layer 38, 
residing in the area above channel region 34, is left. The portion 40 of 
polysilicon which remains after the removal process comprises the gate of 
the MOS device of the present invention. The polysilicon layer 38 is 
removed using an isotropic polysilicon etch process. A photomasking 
operation is used to define the polysilicon contact regions as well as 
other regions where polysilicon will remain. Therefore, the present 
invention provides a gate 40 which is self-aligned over the channel region 
34 of substrate 20 wherein the punchthrough implant was made. 
Additionally, the size and shape of the gate 40 is defined by etching of 
the dielectric hard mask layer 28 and not by the more difficult to control 
methods of the prior art such as etching of polysilicon alone. Thus, the 
present invention provide a self-aligned gate 40. The present invention 
allows for easier fabrication of the gate. Additionally, the present 
invention provides for improved control of the dimensions of the gate. 
Referring next to FIG. 1J, the remaining portion of the dielectric 
shielding layer 28 of FIG. 1I is removed. Next, a source region 42 and a 
drain region 44 are formed on opposite sides of the channel region 34. 
Both the source and drain region have an n conductivity type. The source 
and drain regions may be formed using any of the numerous dopant 
implantation techniques well known in the art. A protective layer 46 of 
material such as, for example, silicate glass is then formed over the 
device and metallized contacts 48 and 50, are formed to the source 42, and 
to the drain 44, respectively. A metallized contact, not shown, is also 
formed to gate 40. 
An alternative embodiment of the present invention is shown in FIGS. 2A-B. 
In this embodiment, the present invention is used in conjunction with 
large tilt angle implanted drain, LATID, technology. In such an 
embodiment, the source region 42 is formed as shown in FIG. 2A using an 
implant made at an angle .alpha., and drain region 44 is made from the 
opposite side again at an angle .alpha. as shown in FIG. 2B. In such an 
embodiment, the processing steps are the same as in the embodiment of 
FIGS. 1A-1J, with the exception that the source region 42 and the drain 
region 44 are formed after the punchthrough and threshold voltage adjust 
implant have been made, and the photoresist layer of FIGS. 1C-E has been 
removed, but before the gate of the MOS device is formed. By forming the 
source and drain regions as shown in FIGS. 2A-B, the gate region is formed 
fully overlapping a portion of both the source and drain region, thereby 
improving hot carrier reliability. 
The present invention as described above has several advantages over the 
prior art. By using the dielectric shielding layer 28 of FIG. 1B as a hard 
mask, the punchthrough implant can be localized to the channel region. As 
a result, punchthrough current and short channel effects are minimized 
without adversely increasing the source-drain junction capacitance as 
found in the prior art. Additionally, the present invention allows the 
dielectric mask layer 28 of FIG. 1B to be used to define the size and 
shape of MOS device gate, rather than having to control the size and shape 
using only the more difficult to control polysilicon layer 30 of FIG. 1C. 
Thus, fabrication of the gate structure is simplified while simultaneously 
providing for improved control over the dimensions of the gate. 
The foregoing descriptions of specific embodiments of the present invention 
have been presented for the purposes of illustration and description. They 
are not intended to be exhaustive or to limit the invention to the precise 
forms disclosed, and obviously many modifications and variations are 
possible in light of the above teaching. The embodiments were chosen and 
described in order to best explain the principles of the invention and its 
practical application, to thereby enable others skilled in the art to best 
utilize the invention and various embodiments with various modifications 
as are suited to the particular use contemplated. It is intended that the 
scope of the invention be defined by the claims appended hereto and their 
equivalents.