Image sensors and image processing systems using multilevel signaling techniques

An image sensor includes a pixel array configured to generate a plurality of pixel signals, an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals, a plurality of memories, respective ones of which are configured to store respective bits of the digital codes, a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits, each of the analog signals corresponding to multiple ones of the stored bits, and a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits. Related image processing systems and methods are also described.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119(a) from Korean Patent Application No. 10-2014-0070657 filed on Jun. 11, 2014, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Embodiments of the inventive concept relate to semiconductor devices and, more particularly, to image sensors, image processing systems and methods of operating the same.

Image sensors are devices that convert an optical image into an electrical signal. Image sensors include charge coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors.

A CMOS image sensor (or a CMOS image sensor chip) may be described as an active pixel sensor manufactured using CMOS semiconductor processes. A typical CMOS image sensor includes a pixel array including a plurality of pixels. Each of the pixels includes a photoelectric conversion element that converts an optical signal into an analog electrical signal and an additional circuit that converts the analog electrical signal into a digital signal.

A typical CMOS image sensor may include, for example, analog to digital converter (ADC) circuitry configured to convert pixel signals into multi-bit digital codes, which may be stored in memory. The store digital codes may be transferred from the memory to a data bus in a bit by bit manner. For example, in response to a first address, a first bit of a first digital code corresponding to a first pixel may be transferred to the data bus, in response to a second address, a first bit of a second digital code corresponding to a second pixel may be transferred to the data bus, in response to a third address, a first bit of a third digital code may be transferred to the data bus, and so on.

The number of pixels, the resolution of an analog-to-digital converter, and a high frame rate are important factors that determine the quality of images processed by the CMOS image sensor. These factors may correlate with the data transfer efficiency of the data bus.

Data bus frequency may be increased in order to increase the data transfer efficiency of the data bus. However, when the data bus frequency increases, there may be a problem in restoring data in a receiver due to interference during data transmission. In addition, when the resolution of the analog-to-digital converter circuitry is increased and a multi-channel data bus is used, more silicon area may be required to form the analog-to-digital converter and the multi-channel data bus. As a result, the die size of the CMOS image sensor chip may increase. Therefore, the die size may need to be reduced by decreasing the silicon area in order to increase gross die or net die. Here, gross die or net die may be defined as the number of semiconductor chips that can be formed in a single wafer.

SUMMARY

Some embodiments of the inventive concept can provide an image sensor having increased efficiency for transfer of data over a data bus, which can reduce silicon area needed to form the data bus and thus reduce die size. Further embodiments provide image processing systems including such sensors and related methods of operating image sensors.

Some embodiments of the inventive concept provide methods of operating an image sensor. The methods include storing a plurality of 1-bit signals in respective ones of a plurality of 1-bit storage devices, generating weighted sum signals having at least three different levels using the 1-bit signals stored in the 1-bit storage devices, and comparing respective ones of a plurality of reference signals with the weighted sum signals to generate a plurality of digital signals. The methods may further include generating the 1-bit signals responsive to a pixel signals output from a plurality of pixels.

In some embodiments, the methods may include converting pixel signals output from the plurality of pixels into digital codes, wherein each of the 1-bit signals are from the same positions in the digital codes. In some embodiments, the 1-bit signals may be generated based on pixel signals output from pixels and the 1-bit signals are included in respective digital codes corresponding to respective ones of the pixel signals and are adjacent to each other in the digital codes.

According to some embodiments, generating the weighted sum signal may include adjusting a plurality of weighted sum coefficients and generating the weighted sum signals using a result of the adjustment and the 1-bit signals.

In some embodiments, generating the weighted sum signals may include decoding a column address and activating a column selection signal and generating a weighted sum signal using the column selection signal and the 1-bit signals. In some embodiments, generating the weighted sum signals may include decoding a single column address and simultaneously activating a plurality of column selection signals and generating a weighted sum signal using the column selection signals and a set of the 1-bit signals, wherein the number of the 1-bit signals in the set is the same as the number of the activated column selection signals.

According to some embodiments, the number of the 1-bit signals in the set maybe T, the number of the reference signals may be 2T−1, wherein T is a natural number greater than or equal to 2. According to some embodiments, the number of the 1-bit signals in the set may be T, the number of the levels may be 2T, wherein T is a natural number greater than or equal to 2. In some embodiments, the number of the levels maybe greater than the number of the reference signals.

Further embodiments of the inventive concept provide an image sensor including a plurality of 1-bit storage devices, respective ones of which are configured to store respective ones of a plurality of 1-bit signals, a signal generator configured to generate weighted sum signals having at least three different levels using the 1-bit signals stored in the 1-bit storage devices, and a comparator array configured to compare each of a plurality of reference signals with the weighted sum signals and to responsively generate a plurality of digital signals.

The image sensor may further include a plurality of pixels configured to generate respective pixel signals and a plurality of analog-to-digital converters configured to convert respective ones of the pixel signals into respective digital codes, wherein respective ones of the 1-bit signals are included in respective ones of the digital codes and the 1-bit signals are at the same bit positions in the digital codes. The image sensor may also include a column address decoder configured to decode a single column address and to simultaneously activate a plurality of column selection signals, wherein the signal generator generates the weighted sum signals using the column selection signals and the 1-bit signals.

In some embodiments, the image sensor may include a pixel configured to output a pixel signal and an analog-to-digital converter configured to convert the pixel signal into a digital code, wherein the 1-bit signals are included in the digital code and adjacent to each other in the digital code.

In further embodiments, the comparator array may include a plurality of comparators, respective ones of which are configured compare respective ones of the reference signals with the weighted sum signal and a decoder configured to decode comparison signals output from the comparators to generate the digital signals.

In still further embodiments, an image processing system includes an image sensor including a plurality of 1-bit storage devices configured to store respective ones of a plurality of 1-bit signals, a signal generator configured to generate weighted sum signals having at least 3 different levels using the 1-bit signals stored in the 1-bit storage devices, and a comparator array configured to compare respective ones of a plurality of reference signals with the weighted sum signals and to responsively generate a plurality of digital signals. The system further includes a processor configured to control the image sensor. The image sensor and the processor may be configured to communicate via a camera serial interface (CSI).

Additional embodiments of the inventive concept provide an image sensor including a pixel array configured to generate a plurality of pixel signals, an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals, a plurality of memories, respective ones of which are configured to store respective bits of the digital codes, a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits, each of the analog signals corresponding to multiple ones of the stored bits, and a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits. In some embodiments, each of the analog signals may correspond to multiple bits from two or more of the digital codes. In further embodiments, each of the analog signals may correspond to multiple bits from one of the digital codes.

According to some embodiments, the image sensor may further include an address decoder configured to select at least two of the memories responsive to a given address to provide multiple bits to the signal processing circuit, wherein the signal processing circuit is configured to generate one of the analog signals responsive to the provided multiple bits. In some embodiments, the address decoder may be configured to simultaneously select memories corresponding to at least two of the digital codes responsive to a given address to provide the multiple bits to the signal processing circuit from multiple ones of the digital codes. In further embodiments, the address decoder may be configured to simultaneously select memories corresponding to one of the digital codes responsive to a given address to provide the multiple bits to the signal processing circuit from the one of the digital codes.

Still further embodiments provide methods including storing respective digital codes corresponding respective ones of a plurality of pixel signals, generating analog signals responsive to bits at the store digital codes, each of the analog signals corresponding to multiple ones of the bits, and comparing the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the bits.

DETAILED DESCRIPTION

FIG. 1is a block diagram of an image sensor100A according to some embodiments of the inventive concept. Referring toFIG. 1, the image sensor (or image sensor chip)100A includes a pixel array110, an analog-to-digital converter (ADC) block130, a memory block150, a signal processing block170A, a comparator array block190A, and a column address decoder195A.

The pixel array110includes a plurality of pixels111. Each of the pixels111includes a photoelectric conversion element and a pixel signal processing circuit that processes an output signal of the photoelectric conversion element. The photoelectric conversion element may be implemented as a photodiode, a phototransistor, a pinned photodiode, or a photogate. The photodiode may be implemented as an organic photodiode. The pixels111may output analog pixel signals P1through Pm (where “m” is a natural number) to the ADC block130through respective column lines.

The ADC block130may perform analog-to-digital conversion on the analog pixel signals P1through Pm. The ADC block130includes a plurality of ADCs ADC_1through ADC_m which may respectively convert the analog pixel signals P1through Pm into n-bit signals D[n:1]. Here, “n” is 2 or a natural number greater than 2. In other words, each of the ADCs ADC_1through ADC_m may convert corresponding one of the analog pixel signals P1through Pm into an n-bit digital code D[n:1].

The memory block150includes a plurality of memories151_1through151_m. Each of the memories151_1through151_mhas a structure capable of storing the n-bit signal D[n:1] output from corresponding one of the ADCs ADC_1through ADC_m. For example, each of the memories151_1through151_mmay include “n” 1-bit storage devices. A 1-bit storage device may be implemented, for example, as a static random access memory (SRAM), a latch, or a flip-flop.

The signal processing block170A includes a plurality of signal generators171_1through171_k,172_1through172_k, . . . , and173_1through173_kand a plurality of data buses175_1A,175_2A,176_1A,176_2A, . . . ,177_1A, and177_2A. The signal generator171_1may generate weighted sum signals WS1iand WS1ibhaving one of at least three levels using a first bit signal D1_1in the n-bit signal D[n:1] output from the first memory151_1, a first bit signal D1_2in the n-bit signal D[n:1] output from the second memory151_2, and column selection signals CSL1and CSL2; and may transmit the weighted sum signals WS1iand WS1ibto a comparator array191_1through a pair of the data buses175_1A and175_2A, respectively.

In other words, the signal generator171_1may generate the weighted sum signals WS1iand WS1ibusing bit signals at the same positions (e.g., the first bit positions) in the n-bit signals D[n:1] respectively output from the memories151_1and151_2.

The signal generator172_1may generate weighted sum signals WS2iand WS2ibhaving one of the at least three levels using a second bit signal D2_1in the n-bit signal D[n:1] output from the first memory151_1, a second bit signal D2_2in the n-bit signal D[n:1] output from the second memory151_2, and the column selection signals CSL1and CSL2; and may transmit the weighted sum signals WS2iand WS2ibto a comparator array191_2through a pair of the data buses176_1A and176_2A, respectively.

In other words, the signal generator172_1may generate the weighted sum signals WS2iand WS2ibusing bit signals at the same positions (e.g., the second bit positions) in the n-bit signals D[n:1] respectively output from the memories151_1and151_2.

The signal generator173_1may generate weighted sum signals WSni and WSnib having one of the at least three levels using an nthbit signal Dn_1in the n-bit signal D[n:1] output from the first memory151_1, an nthbit signal Dn_2in the n-bit signal D[n:1] output from the second memory151_2, and the column selection signals CSL1and CSL2; and may transmit the weighted sum signals WSni and WSnib to a comparator array191_3through a pair of the data buses177_1A and177_2A, respectively.

In other words, the signal generator173_1may generate the weighted sum signals WSni and WSnib using bit signals at the same positions (e.g., the nthbit positions) in the n-bit signals D[n:1] respectively output from the memories151_1and151_2.

The weighted sum signals WS1iand WS1ib, WS2iand WS2ib, WSni and WSnib may be generated in parallel or simultaneously. The weighted sum signals WS1ithrough WSnib may be voltage or current.

The signal generator171_kmay generate weighted sum signals WS1iand WS1ibhaving one of the at least three levels using a first bit signal D1_(m−1) in the n-bit signal D[n:1] output from the (m−1)thmemory151_(m−1), a first bit signal D1_min the n-bit signal D[n:1]_output from the mthmemory151_m, and column selection signals CSLm−1 and CSLm; and may transmit the weighted sum signals WS1iand WS1ibto the comparator array191_1through the data buses175_1A and175_2A, respectively.

The signal generator172_kmay generate weighted sum signals WS2iand WS2ibhaving one of the at least three levels using a second bit signal D2_(m−1) in the n-bit signal D[n:1] output from the (m−1)thmemory151_(m−1), a second bit signal D2_min the n-bit signal D[n:1] output from the mthmemory151_m, and the column selection signals CSLm−1 and CSLm; and may transmit the weighted sum signals WS2iand WS2ibto the comparator array191_2through the data buses176_1A and176_2A, respectively.

The signal generator173_kmay generate the weighted sum signals WSni and WSnib having one of the at least three levels using an nthbit signal Dn_(m−1) in the n-bit signal D[n:1] output from the (m−1)thmemory151_(m−1), an nthbit signal Dn_m in the n-bit signal D[n:1] output from the mthmemory151_m, and the column selection signals CSLm−1 and CSLm; and may transmit the weighted sum signals WSni and WSnib to the comparator array191_3through the data buses177_1A and177_2A, respectively.

For clarity of the description,FIG. 1shows the embodiments in which weighted sum signals are generated using bit signals output from two respective memories and two column selection signals. However, an image sensor may have a structure in which weighted sum signals are generated using bit signals output from three memories and three column selection signals in other embodiments of the inventive concept.

The comparator array block190A may compare a plurality of reference signals with weighted sum signals and generate a plurality of digital signals. The comparator array block190A includes a plurality of the comparator arrays191_1through191_3.

The comparator array191_1may generate two digital signals DS1_1and DS1_2corresponding to the two bit signals D1_1and D1_2, D1_3and D1_4, . . . , or D1_(m−1) and D1_musing a plurality of reference signals and the weighted sum signals WS1iand WS1ib.

The comparator array191_2may generate two digital signals DS2_1and DS2_2corresponding to the two bit signals D2_1and D2_2, D2_3and D2_4, . . . , or D2_(m−1) and D2_musing the reference signals and the weighted sum signals WS2iand WS2ib.

The comparator array191_3may generate two digital signals DSn_1and DSn_2corresponding to the two bit signals Dn_1and Dn_2, Dn_3and Dn_4, . . . , or Dn_(m−1) and Dn_m using the reference signals and the weighted sum signals WSni and WSnib.

The column address decoder195A may activate two column selection signals at a time in response to a given column address CADD input.

FIG. 2is a circuit diagram of the signal generator171_1illustrated inFIG. 1.FIG. 3is a diagram of the output waveforms of the column address decoder195A illustrated inFIG. 1according to some embodiments of the inventive concept.FIG. 4is a conceptual diagram of the operation of the signal generator171_1illustrated inFIG. 2. The structure and the operations are substantially the same among the signal generators171_1through171_k,172_1through172_k, . . . , and173_1through173_k. Thus, for clarity of the description, the structure and the operations of the signal generator171_1are representatively described.

The signal generator171_1includes two differential amplifiers DA1and DA2. The differential amplifiers DA1and DA2include control circuits CS1and CS2, respectively, which control a swing level in response to control signals CTRL1and CTRL2, respectively. For example, the control signals CTRL1and CTRL2may be generated from a timing generator (not shown) that controls the operations of the image sensor100A. For example, the control circuits CS1and CS2may control bias current of the differential amplifiers DA1and DA2, respectively.

As shown inFIG. 3, a pair of the column selection signals CSL1and CSL2, CSL3and CSL4, . . . , or CSLm−1 and CSLm is simultaneously activated in response to a column address CADD1input at a first point T1, a column address CADD2input at a second point T2, or a column address CADDs input at an sthpoint Ts. Here, “s” is a natural number. For clarity of the description, it is assumed that a current of 1.5 Io is supplied to the data buses175_1A and175_2A at each of points T1through Ts.

As shown inFIG. 4, when the first bit signal D1_1in the n-bit signal D[n:1] output from the first memory151_1is low or logic “0” and the first bit signal D1_2in the n-bit signal D[n:1] output from the second memory151_2is low, a signal D1b_1is high or logic “1” and a signal D1b_2is high. NMOS transistors N2, N3, N5, and N6are turned on in response to the signals D1b_1, CSL1, D1b_2, and CSL2, respectively, and NMOS transistors N1and N4are turned off in response to the signals D1_1and D1_2, respectively. As a result, the weighted sum current WS1iflowing in the data bus175_1A becomes 0 and the weighted sum current WS1ibflowing in the data bus175_2A remains at 1.5 Io.

When the first bit signal D1_1in the n-bit signal D[n:1] output from the first memory151_1is low and the first bit signal D1_2in the n-bit signal D[n:1] output from the second memory151_2is high, the signal D1b_1is high and the signal D1b_2is low. The NMOS transistors N2, N3, N4, and N6are turned on in response to the signals D1b_1, CSL1, D1_2, and CSL2, respectively, and the NMOS transistors N1and N5are turned off in response to the signals D1_1and D1b_2, respectively. As a result, the weighted sum current WS1iflowing in the data bus175_1A becomes 0.5 Io and the weighted sum current WS1ibflowing in the data bus175_2A becomes 1.0 Io.

When the first bit signal D1_1in the n-bit signal D[n:1] output from the first memory151_1is high and the first bit signal D1_2in the n-bit signal D[n:1] output from the second memory151_2is low, the signal D1b_1is low and the signal D1b_2is high. The NMOS transistors N1, N3, N5, and N6are turned on in response to the signals D1_1, CSL1, D1b_2, and CSL2, respectively, and the NMOS transistors N2and N4are turned off in response to the signals D1b_1and D1_2, respectively. As a result, the weighted sum current WS1iflowing in the data bus175_1A becomes 1.0 Io and the weighted sum current WS1ibflowing in the data bus175_2A becomes 0.5 Io.

When the first bit signal D1_1in the n-bit signal D[n:1] output from the first memory151_1is high and the first bit signal D1_2in the n-bit signal D[n:1] output from the second memory151_2is high, the signal D1b_1is low and the signal D1b_2is low. The NMOS transistors N1, N3, N4, and N6are turned on in response to the signals D1_1, CSL1, D1_2, and CSL2, respectively, and the NMOS transistors N2and N5are turned off in response to the signals D1b_1and D1b_2, respectively. As a result, the weighted sum current WS1iflowing in the data bus175_1A becomes 1.5 Io and the weighted sum current WS1ibflowing in the data bus175_2A becomes 0.

In the embodiments illustrated inFIG. 4, the weighted sum currents WS1iand WS1ibmay be set to one of four levels according to the level of the first bit signal D1_1output from the first memory151_1and the level of the first bit signal D1_2output from the second memory151_2.

FIG. 5is a block diagram of an example of the comparator array191-1illustrated inFIG. 1.FIG. 6is a diagram of signal waveforms for explaining the operation of the comparator array191_1A illustrated inFIG. 5. The comparator arrays191_1through191_3substantially have the same structure and substantially perform the same operations. Thus, the structure and the operations of the comparator array191-1will be representatively described. The example of the comparator array191-1, i.e. a comparator array191_1A includes a plurality of comparators201,203, and205and a decoder207. Each of the comparators201,203, and205may be implemented as a voltage comparator or a current comparator.

The comparator201compares the weighted sum signal WS1iwith a first reference signal Iref1and outputs a first comparison signal CS1. The comparator203compares the weighted sum signal WS1iwith a second reference signal Iref2and outputs a second comparison signal CS2. The comparator205compares the weighted sum signal WS1iwith a third reference signal Iref3and outputs a third comparison signal CS3.

Referring toFIG. 6, when the weighted sum signal WS1iis at a first level SL1(=1.5 Io), the comparison signals CS1, CS2, and CS3are at a high level.

When the weighted sum signal WS1iis at a second level SL2(=1.0 Io), the first comparison signal CS1is at a low level and the other comparison signals CS2and CS3are at the high level.

When the weighted sum signal WS1iis at a third level SL3(=0.5 Io), the first and second comparison signals CS1and CS2are at the low level and the third comparison signal CS is at the high level.

When the weighted sum signal WS1iis at a fourth level SL4(=0), the comparison signals CS1, CS2, and CS3are at the low level.

The decoder207may decode the level of each of the comparison signals CS1, CS2, and CS3and output the digital signals DS1_1and DS1_2respectively corresponding to two bit signals D1_1and D1_2according to the decoding result.

For example, when the comparison signals CS2and CS3are at the high level, the decoder207may generate two bit signals D1_1and D1_2at a high level. When the comparison signals CS2and CS3are at the low level, the decoder207may generate two bit signals D1_1and D1_2at a low level.

FIG. 7is a block diagram of another example of the comparator array191_1illustrated inFIG. 1. The comparator arrays191_1through191_3substantially have the same structure and substantially perform the same operations. Thus, the structure and the operations of the comparator array191-1will be representatively described. The example of the comparator array191-1, i.e. a comparator array191_1B includes a plurality of comparators202,204, and206and the decoder207. Each of the comparators202,204, and206may be implemented as a voltage comparator or a current comparator.

The comparator202may compare a difference (e.g., WS1i-WS1ib) between the weighted sum signals WS1iand WS1ibwith a difference between first reference signals Iref1and Iref1band output a first comparison signal CS1. The first reference signals Iref1and Iref1bmay be differential signals.

The comparator204may compare the difference between the weighted sum signals WS1iand WS1ibwith a difference between second reference signals Iref2and Iref2band output a second comparison signal CS2. The second reference signals Iref2and Iref2bmay be differential signals.

The comparator206may compare the difference between the weighted sum signals WS1iand WS1ibwith a difference between third reference signals Iref3and Iref3band output a third comparison signal CS3. The third reference signals Iref3and Iref3bmay be differential signals.

When the difference (e.g., WS1i-WS1ib) between the weighted sum signals WS1iand WS1ibis at the first level SL1(=+1.5 Io) as shown inFIG. 6, the comparison signals CS1, CS2, and CS3are at the high level.

When the difference (e.g., WS1i-WS1ib) between the weighted sum signals WS1iand WS1ibis at the second level SL2(=+0.5 Io), the first comparison signal CS1is at the low level and the other comparison signals CS2and CS3are at the high level.

When the difference (e.g., WS1i-WS1ib) between the weighted sum signals WS1iand WS1ibis at the third level SL3(=−0.5 Io), the comparison signals CS1and CS2are at the low level and the third comparison signal CS3is at the high level.

When the difference (e.g., WS1i-WS1ib) between the weighted sum signals WS1iand WS1ibis at the fourth level SL4(=−1.5 Io), the comparison signals CS1, CS2, and CS3are at the low level.

The decoder207may decode the level of each of the comparison signals CS1, CS2, and CS3and output the digital signals DS1_1and DS1_2respectively corresponding to two bit signals D1_1and D1_2according to the decoding result.

For example, when the comparison signals CS2and CS3are at the high level, the decoder207may generate two bit signals D1_1and D1_2at the high level. When the comparison signals CS2and CS3are at the low level, the decoder207may generate two bit signals D1_1and D1_2at the low level.

As has been described with reference toFIGS. 1 through 7, when at least one weighted sum signal is generated using a 1-bit signal output from each of T memories (where T is 2 or a natural number greater than 2) among the memories151_1through151_m, the weighted sum signal may be set to one of 2Tlevels and each comparator array may include (2T−1) comparators.

FIG. 8is a block diagram of an image sensor100B according to further embodiments of the inventive concept. Referring toFIG. 8, the image sensor100B includes a pixel array110, an ADC block130, a memory block150, a signal processing block170B, a comparator array block190B, and a column address decoder195B.

The signal generator271_1may generate weighted sum signals WS1iand WS1ibhaving one of at least three levels using the first and second bit signals D1_1and D2_1output from the first memory151_1and the column selection signals CSL1and CSL2and may transmit the weighted sum signals WS1iand WS1ibto a comparator array291_1through a pair of the data buses275_1and275_2, respectively.

The signal generator272_1may generate weighted sum signals WS0iand WS0ibhaving one of the at least three levels using (n−1)thand nthbit signals D(n−1)_1 and Dn_1output from the first memory151_1and the column selection signals CSL1and CSL2and may transmit the weighted sum signals WS0iand WS0ibto a comparator array292_1through a pair of the data buses276_1and276_2, respectively.

The signal generator271_mmay generate the weighted sum signals WS1iand WS1ibhaving one of the at least three levels using the first and second bit signals D1_mand D2_moutput from the mthmemory151_mand the column selection signals CSLm−1 and CSLm and may transmit the weighted sum signals WS1iand WS1ibto the comparator array291_1through the data buses275_1and275_2, respectively.

The signal generator272_mmay generate the weighted sum signals WS0iand WS0ibhaving one of the at least three levels using (n−1)thand nthbit signals D(n−1)_mand Dn_m output from the mthmemory151_mand the column selection signals CSLm−1 and CSLm and may transmit the weighted sum signals WS0iand WS0ibto the comparator array292_1through the data buses276_1and276_2, respectively.

The structure and the operations of the comparator arrays291_1through292_1are substantially the same as those of the comparator array191_1A illustrated inFIG. 5or the comparator array191_1B illustrated inFIG. 7.

As described above, each of the signal generators271_1through271_m, . . . , or272_1through272_mmay generate weighted sum signals having one of 2Tlevels (where T is 2 or a natural number greater than 2) using T 1-bit signals output from corresponding one of the memories251_1through251_m.

The comparator array block190B may compare a plurality of reference signals with weighted sum signals and generate a plurality of digital signals. The comparator array block190B includes a plurality of the comparator arrays291_1through292_1.

The comparator array291_1may generate two digital signals DS1and DS2corresponding to the two bit signals D1_1and D2_1, D1_2and D2_2, . . . , or D1_mand D2_moutput from corresponding one of the memories251_1through251_musing a plurality of reference signals and the weighted sum signals WS1iand WS1ib.

The comparator array292_1may generate two digital signals DS(n−1) and DSn corresponding to the two bit signals D(n−1)_1 and Dn_1, D(n−1)_2 and Dn_2, . . . , or D(n−1)_mand Dn_m output from corresponding one of the memories251_1through251_musing a plurality of reference signals and the weighted sum signals WS0iand WS0ib.

The column address decoder195B may activate two column selection signals at a time in response to a given column address CADD input.

FIG. 9is a circuit diagram of the signal generator271_1illustrated inFIG. 8. The structure and the operations are substantially the same among the signal generators271_1through271_m, . . . , and272_1through272_m. Thus, the structure and the operations of the signal generator271_1will be representatively described for clarity of the description.

The signal generator271_1includes two differential amplifiers DA1and DA2. Except for some input signals D2_1and D2b_1, the structure and the operations of the signal generator271_1illustrated inFIG. 9are substantially the same as those of the signal generator171_1illustrated inFIG. 2.

FIG. 10is a block diagram of an image sensor100C according to additional embodiments of the inventive concept.FIG. 12is a diagram of the output waveforms of a column address decoder195C illustrated inFIG. 11according to some embodiments of the inventive concept. Except for the column address decoder195C, the structure and the operations of the image sensor100C illustrated inFIG. 10are substantially the same as those of the image sensor100A illustrated inFIG. 1.

In detail, the column address decoder195C sequentially activate the odd-numbered column selection signals CSL1, CSL3, . . . , CSLm−1 in response to the column addresses CADD1through CADDs, respectively, input at the respective points T1through Ts, as shown inFIG. 12.

FIG. 11is a circuit diagram of the signal generator171_1illustrated inFIG. 10. The structure and the operations of the signal generator171_1illustrated inFIG. 11are substantially the same as those of the signal generator171_1illustrated inFIG. 2with the exception that both of the transistors N3and N6operate in response to a single column selection signal CSL1.

FIG. 13is a block diagram of an image sensor100D according to yet further embodiments of the inventive concept. Except for a column address decoder195D, the structure and the operations of the image sensor100D illustrated inFIG. 13are substantially the same as those of the image sensor100B illustrated inFIG. 8.

FIG. 14is a circuit diagram of the signal generator271_1illustrated inFIG. 13. The structure and the operations of the signal generator271_1illustrated inFIG. 14are substantially the same as those of the signal generator271_1illustrated inFIG. 9with the exception that both of the transistors N3and N6operate in response to a single column selection signal CSL1.

FIG. 15is a block diagram of an image processing system300according to some embodiments of the inventive concept. Referring toFIGS. 1 through 15, the image processing system300includes the image sensor100A,100B,100C, or100D (collectively denoted by100), a processor310, a display400, and storage500.

The image processing system300may be implemented as a portable electronic device or mobile computing device. The portable electronic device may be a laptop computer, a cellular phone, a smartphone, a tablet personal computer (PC), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or portable navigation device (PND), a handheld game console, a mobile internet device (MID), a wearable computer, an internet of things (IoT) device, an internet of everything (IoE) device, or an e-book.

The image sensor100may be implemented as a CMOS image sensor chip. The processor310may control the operations of the elements100,400, and500. The processor310may be implemented as an integrated circuit (IC), a system on chip (SoC), an application processor (AP), or a mobile AP.

The image sensor100may transmit image data to the processor310through serial interface, e.g., mobile industry processor interface (MIPI®) camera serial interface (CSI). A CSI host313included in the processor310may perform serial communication with a CSI device101included in the image sensor100using the CSI.

The processor310may transmit image data to the display400using MIPI® display serial interface (DSI). A DSI host311included in the processor310may perform serial communication with a DSI device101included in the display400using the DSI. The processor310may store image data in the storage500and may read image data from the storage500.

FIG. 16is a flowchart of a method of operating an image sensor according to some embodiments of the inventive concept. Referring toFIGS. 1 through 16, an n-bit digital code output from each of the ADCs ADC_1through ADC_m may be stored in one of the memories151_1through151_m. For example, 1-bit signals in the n-bit digital code may be stored in respective 1-bit storage devices in each of the memories151_1through151_min operation S110.

A signal generator may generate a weighted sum signal(s) having one of at least three levels using 1-bit signals stored in respective 1-bit storage devices in operation S120. The signal generator may transmit the weighted sum signal(s) to a data bus in operation S130. A comparator block may compare each of a plurality of reference signals with the weighted sum signal and generate a plurality of digital signals in operation S140.

As described above with reference toFIGS. 1 and 10, each of the 1-bit signals may be generated based on pixel signals respectively output from different pixels. Each of the ADCs ADC_1through ADC_m may convert one of the pixel signals P1through Pm output by columns of the pixels111into the digital code D[n:1]. The 1-bit signals are bit signals at the same positions in digital codes respectively corresponding to different pixels.

In some embodiments, as described above with reference toFIGS. 8 and 13, the 1-bit signals may be generated based on a pixel signal output from one pixel. The 1-bit signals may be included in a digital code corresponding to the pixel signal and may be adjacent to each other in the digital code.

The image sensor100may adjust a plurality of weighted sum coefficients for each of the control circuits CS1and CS2included in the signal generator171_1or271_1according to the control of the processor310. The weighted sum coefficients for each of the control circuits CS1and CS2may be adjusted or determined based on the control signal CTRL1or CTRL2. The signal generator171_1or271_1may generate a weighted sum signal using the adjustment result and the 1-bit signals.

FIG. 17is a block diagram of an image processing system900according to further embodiments of the inventive concept. Referring toFIGS. 1 through 17, the image processing system900may be implemented as a portable electronic device which can use or support MIPI. The image processing system900includes an AP910, the CMOS image sensor100, and the display400.

A CSI host913in the AP910may perform serial communication with the CSI device101in the CMOS image sensor100through CSI. A deserializer DES and a serializer SER may be implemented in the CSI host913and the CSI device101, respectively. The CMOS image sensor100may be one of the CMOS image sensors100A through100D described with reference toFIGS. 1 through 14.

A DSI host911in the AP910may perform serial communication with the DSI device510in the display400through DSI. A serializer SER and a deserializer DES may be implemented in the DSI host911and the DSI device510, respectively. The serializers SER and the deserializers DES may process electrical signals or optical signals.

The image processing system900may also include a radio frequency (RF) chip940communicating with the AP910. A physical layer (PHY)915of the AP910and a PHY941of the RF chip940may communicate data with each other according to MIPI DigRF.

A central processing unit (CPU)917included in the AP910may control the operations of the CMOS image sensor100and the display400. The CPU917may also control the operations of the DSI host911, the CSI host913, and the PHY915.

The image processing system900may further include a global positioning system (GPS) receiver950, a memory951such as dynamic random access memory (DRAM), a data storage953implemented as a non-volatile memory such as NAND flash memory, a microphone (MIC)955, and/or a speaker957. The image processing system900may communicate with external devices using at least one communication protocol or standard, e.g., worldwide interoperability for microwave access (Wimax)959, wireless local area network (WLAN)961, ultra-wideband (UWB)963, or long term evolution (LTETM)965. The image processing system900may communicate with external devices using Bluetooth, near field communication (NFC), or WiFi.

As described above, according to some embodiments of the inventive concept, an image sensor may increase transfer efficiency of data transmitted through a data bus and decrease a silicon area necessary to form the data bus. As a result, the entire die size for the image sensor may be decreased. Instead of transmitting each of sequential bits through a data bus, the image sensor may transmit a single weighted sum signal corresponding to at least two bits through a data bus, thereby increasing data transfer efficiency of the data bus.