A conventional D-type flip-flop transfers the data input D to a first output Q and a second output Q', where the second output Q' is the complement of the first output Q, on the transitions of a clock signal CK. This involves the transfer of data from a master latch and a series-connected slave latch which are loaded on alternating phases of the clock signal CK. The present invention provides for asynchronous loading of replacement data into the flip-flop by using a tri-stable buffer in both the master and slave latches. In response to a load signal LD, replacement data is injected into the master and slave latches overriding the current value stored at the Q and Q' outputs. This occurs because the load signal disables the normally active buffers while activating the loading buffers causing the normally active data path to go the tri-state condition. The state of the clock signal CK is of no importance to the outcome of the asynchronous load operation since both the master and the slave latch are overwritten during the load phase.

BACKGROUND OF THE INVENTION 
1.Field of the Invention 
The present invention relates to a CMOS D-type flip-flop that can be loaded 
asynchronously to a clock input. 
2. Discussion of the Prior Art 
A flip-flop is a logic circuit that includes feedback so that its output 
state is a function not only of the input, but also of the previous 
history of the input. Thus, a flip-flop may be used as a memory element. 
For example, a flip-flop has two outputs, usually called Q and Q' to 
indicate that if the Q output is a 1, then the Q' output must be a 0. A 
momentary input signal will cause the outputs to "flip" so that the Q 
output becomes a 0 and the Q' output becomes a 1. The two output signals 
will remain in these states even though the input signal is removed. 
An edge-triggered D-type flip-flop transfers a data input D to the Q and Q' 
outputs on the transitions of a clock CK. However, there are circumstances 
in which it is necessary to load data into the flip-flop at times other 
than at the clock transitions, i.e. asynchronously to the clock. For 
example, if the flip-flop is to be used as a timer or a counter, then an 
initial value must be loaded to begin the timing or the count. Also, 
asynchronous events may occur that require that the data value currently 
stored in the flip-flop be overridden. 
An asynchronously loadable D-type flip-flop can be obtained by utilizing a 
conventional D flip-flop with asynchronous clear and preset, such as a 
generic HC74 device, and providing external logic to clear or preset when 
loading a 0 or 1, respectively. A conventional flip-flop of this type is 
illustrated in FIG. 1. While this approach works well, additional logic is 
required to steer the preset and clear lines to perform the load function. 
SUMMARY OF THE INVENTION 
A conventional D-type flip-flop transfers the data input D to a first 
output Q and a second output Q', where the second output Q' is the 
complement of the first output Q, on the transitions of a clock signal CK. 
This involves the transfer of data from a master latch and a 
series-connected slave latch which are loaded on alternating phases of the 
clock signal CK. The present invention provides for asynchronous loading 
of replacement data into the flip-flop by using a tri-stable buffer in 
both the master and slave latches. In response to a load signal, 
replacement data is injected into the master and slave latches, overriding 
the current value stored at the Q and Q' outputs. This occurs because the 
load signal disables the normally active buffers while activating the 
loading buffers, causing the normally active data path to go into the 
tri-state condition. The state of the clock signal CK is of no importance 
to the outcome of the asynchronous load operation since both the master 
and the slave latch are overwritten during the load phase. 
The asynchronously loadable flip-flop of the present invention uses less 
active devices than the conventional approach. Also, the flip-flop cell is 
smaller than the conventional design when implemented as an integrated 
circuit since it uses series P-channel and N-channel devices in its master 
and slave portions which can share source/drain regions and, thus, utilize 
less die area. Another benefit is that the propagation delay between the 
loading of data into the flip-flop to its becoming valid on the outputs is 
faster than the conventional technique since fewer delay paths are in the 
load path. 
A better understanding of the features and advantages of the present 
invention will be obtained by reference to the following detailed 
description of the invention and accompanying drawings which set forth an 
illustrative embodiment in which the principles of the invention are 
utilized.

DETAILED DESCRIPTION OF THE INVENTION 
FIG. 2 shows an asynchronously loadable D-type flip-flop in accordance with 
the present invention wherein the loading function is accomplished in the 
flip-flop itself, eliminating the need for additional external logic. 
Referring to FIG. 2, in the normal operation of the conventional D-type 
flip-flop, input data D is clocked into the normal storage buffer of the 
master latch via node Al during a first phase of clock cycle CK which 
enables transmission gate 10. At the same time, the value stored in the 
normal storage buffer of the slave latch is fed back to node B1 via 
inverter 18 and enabled transmission gate 20. During the second phase of 
the clock cycle CK, the value loaded in the storage buffer of the master 
latch is clocked into the storage buffer of the slave latch via node B1 
and enabled transmission gate 16 and fed back to node A1 via inverter 12 
and enabled transmission gate 14. 
In accordance with the present invention, the asynchronous loading of the 
flip-flop is performed by using a tri-stable loading buffer in both the 
master latch and the slave latch of the D-type flip-flop. 
The tri-stable loading buffer in the master latch consists of P-channel 
devices P1 and P2 and N-channel devices N1 and N2 which are connected in 
series between a positive power supply and ground. A similar 
series-connected transistor combination consisting of P-channel devices P3 
and P4 and N-channel devices N3 and N4 is cross-coupled at the 
source/drain connections of devices P2, N1 and P4, N3, respectively. The 
load data signal DI is provided to the gates of devices P4 and N3. Devices 
P2 and N1 are controlled by the data input D via transmission gate 10, 
which is enabled by the clock signal CK and its complement CK'. 
A similar tri-state loading buffer is provided in the slave latch and 
consists of series connected P-channel devices P5 and P6 and N-channel 
devices N5 and N6 which are cross-coupled to series connected P-channel 
devices P7 and P8 and N-channel devices N7 and N8. 
As shown in FIG. 2, when the load signal LD is high, data is injected into 
the flip-flop, overriding the current value stored at the Q and Q' 
outputs. That is, when the load signal LD is high, the loading paths are 
activated since devices N4, P3, N8 and P7 all turn on. The loading buffer 
is activated, that is devices P1, N2, P5 and N6 turn off, causing the 
normally active path to assume the high impedance or tri-state. The value 
of load data DI is loaded into the master latch making INT.dbd.DI'. 
Likewise, DI' is loaded into the slave latch causing Q.dbd.DI, since there 
is an inversion inherent in the tri-state loading structure. 
The state of the clock input CK is of no importance to the outcome of the 
load operation (asynchronous load) since both the master and slave latches 
are overwritten during the load phase. 
In the non-loading operation, i.e., when the load signal LD is low, the 
flip-flop works as a regular rising edge triggered D flip-flop since the 
loading buffers are disabled. That is, devices P3, N4, P7 and N8 are off 
causing the load injection buffers to be in a high impedance state. 
Obviously, devices P1, N2, P5 and N6 are active in the non-loading state, 
yielding a simple inversion from nodes A1 to INT and B1 to Q, which is how 
a conventional D-type flip-flop is implemented. 
It should be understood that the invention is not intended to be limited by 
the specifics of the above-described embodiment, but rather defined by the 
accompanying claims.