Manufacturing method of thin film transistor and thin film transistor, and display

A manufacturing method of a thin film transistor made of a stack of an organic semiconductor layer, a gate insulating film and a gate electrode in this order on a substrate, which includes the steps of pattern coating a gate electrode material on the gate insulating film by printing; and carrying out a heat treatment to form the gate electrode resulting from drying for solidification of the pattern coated gate electrode material.

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention contains subjects related to Japanese Patent Application JP 2006-135995 filed in the Japan Patent Office on May 16, 2006, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a manufacturing method of a thin film transistor and to a thin film transistor and also to a display. In more detail, the invention relates to a manufacturing method of a thin film transistor of a top gate type using an organic semiconductor layer as a channel layer and to a thin film transistor and also to a display using the same.

2. Description of the Related Art

A thin film transistor (TFT) is widely used as a pixel transistor in electronic circuits, in particular flat panel displays of an active matrix type.

At present, the majority of thin film transistors is an Si based inorganic semiconductor transistor using amorphous silicon or polycrystalline silicon as a semiconductor layer. Since the manufacture of the same employs fabrication requiring a vacuum treatment chamber such as chemical vapor deposition (CVD) for the formation of a semiconductor layer, the process costs are high. Also, since a heat treatment at high temperatures is necessary, a substrate is required to have heat resistance.

On the other hand, in a thin film transistor utilizing an organic semiconductor, it is possible to coat and fabricate an organic semiconductor layer which becomes a channel layer at low temperatures. For that reason, not only such is advantageous for realizing low costs, but also it is possible to achieve the formation on a flexibly substrate with low heat resistance such as plastics.

Of the foregoing thin film transistors, in particular, a thin film transistor of a top gate type is studied as a drive device of an active matrix type in display devices such as electronic paper. In the case of the top gate structure, a channel layer is disposed in a side of a back side substrate with respect to a gate electrode as compared with the case of a bottom gate structure, and therefore, there is brought an advantage that influences of a potential of a pixel electrode against the channel layer can be made small. In the former case, as a forming method of the gate electrode, there is often employed an example in which a metal such as gold is subjected to pattern formation via a shadow mask by, for example, vapor deposition (see, for example,Advanced Function Materials, (United States) 2003, Vol. 13, p. 199; andApplied Physics Letters, (United States) 2002, Vol. 81, p. 1735 (Non-Patent Documents 1 and 2)).

SUMMARY OF THE INVENTION

However, in the vapor deposition via a shadow mask, it is difficult to form a fine pattern of not more than 100 μm in a large area, and there are involved problems that not only throughput of mass production becomes worse, but also the costs become high easily.

In view of the foregoing problems of the related art, it is desirable to provide a manufacturing method of a thin film transistor which is suitable for mass production and is able to be manufactured at low costs and a thin film transistor and also a display using the same.

According to an embodiment of the invention, there is provided a manufacturing method of a thin film transistor made of a stack of an organic semiconductor layer, a gate insulating film and a gate electrode in this order on a substrate, wherein the following steps are carried out successively. First of all, a step of pattern coating a gate electrode material on the gate insulating film by printing is carried out. Next, a heat treatment is carried out to form the gate electrode resulting from drying for solidification of the pattern coated gate electrode material.

Also, according to an embodiment of the invention, there is provided a thin film transistor made of a stack of an organic semiconductor layer, a gate insulating film and a gate electrode in this order on a substrate, wherein the gate electrode is formed by heat treating a gate electrode material having been pattern coated by printing.

According to the manufacturing method of a thin film transistor and the thin film transistor ad described above, since the gate electrode material is pattern coated by printing, the costs are low as compared with the case of pattern forming a gate electrode by employing a usual lithography technology, and they are suitable for mass production. Furthermore, as described later in detail in the section of “Detailed Description of the Preferred Embodiments”, it has been confirmed that the thin film transistor having a gate electrode resulting from drying for solidification of the pattern coated gate electrode material is not only improved in a subthreshold characteristic but also increased in an on/off ratio as compared with a thin film transistor having a gate electrode formed by vapor deposition using a shadow mask,

Also, according to an embodiment of the invention, there is provided a display including a thin film transistor made of a stack of an organic semiconductor layer, a gate insulating film and a gate electrode in this order on a substrate; and a display device connected to this thin film transistor disposed and formed on a substrate, wherein the gate electrode is formed by heat treating a gate electrode material having been pattern coated by printing.

According to such a display, by providing the foregoing thin film transistor, not only a subthreshold characteristic of the thin film transistor is improved, but also an on/off ratio is increased.

As described previously, since the manufacturing method of a thin film transistor and the thin film transistor according to embodiments of the invention are not only low in costs but also suitable for mass production, they are able to improve the productivity. Also, since not only a subthreshold characteristic of the thin film transistor is improved, but also an on/off ratio is increased, it is possible to obtain a thin film transistor having excellent electric characteristics.

Also, since the display according to an embodiment according to the invention is not only improved in a subthreshold characteristic but also increased in an on/off ratio, it is possible to design to realize low electricity consumption.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments according to the invention are hereunder explained in detail with reference to the accompanying drawings.

<Manufacturing Method of Thin Film Transistor and Thin Film Transistor>

One example of a manufacturing method of a thin film transistor according to an embodiment of the invention is explained with reference to a sectional view of manufacturing step as illustrated in each ofFIGS. 1A to 1D. The thin film transistor according to an embodiment of the invention is a thin film transistor of a top gate type (stagger type). In the present embodiment, a configuration of a thin film transistor of a top gate/bottom contact type is explained in order of manufacturing steps.

First of all, as illustrated inFIG. 1A, a source electrode12and a drain electrode13are pattern formed on a substrate11. In that case, a silver ink is coated on the plastic-made substrate11made of polyethersulfone (PES) by, for example, spin coating and heat treated at 150° C., thereby fabricating a conductive film (not illustrated) made of silver in a thickness of 30 nm. Next, a resist pattern in which patterns of the source electrode12and the drain electrode13are provided by photolithography is formed on the conductive film. Subsequently, the source electrode12and the drain electrode13are pattern formed by wet etching using a silver etching solution.

Though PES is used herein as the substrate11, glass and plastics with high heat resistance such as polyethylene naphthalate (PEN), polyimide (PI), polycarbonate (PC), and polyacrylate (PAR) can also be used as the substrate11.

Also, in addition to silver, metals having good ohmic contact with a p-type semiconductor (for example, gold, platinum, and palladium) and conductive organic materials made of poly(3,4-ethylenedioxythiophene)/poly(4-styrenesulfonate) [PEDOT/PSS] and polyaniline (PANI) can also be used as the source electrode12and the drain electrode13.

Also, in the forming step of the source electrode12and the drain electrode13, ink jetting, screen printing and laser plotting may be employed as a forming method of a resist pattern which is used for a mask of etching. Furthermore, direct patterning by ink jetting, screen printing or microcontact printing can also be employed. However, in a later step, an organic semiconductor layer is formed on the substrate11in a state that it covers the source electrode12and the drain electrode13, and a gate insulating film is formed on the organic semiconductor layer. Accordingly, for the purpose of forming a good interface between the organic semiconductor layer and the gate insulating film, it is preferable that each of the source electrode12and the drain electrode13has a flat surface and has a thickness as not more than 100 nm as thin as possible. In order to form each of the flattened source electrode12and drain electrode13having a thickness of not more than 100 nm, it is preferred to employ the foregoing spin coating. Besides, gravure coating, roll coating, kiss coating, knife coating, die coating, slit coating, and blade coating can also be employed.

Next, as illustrated inFIG. 1B, an organic semiconductor layer14is formed on the substrate11in a state that it covers the source electrode12and the drain electrode13. Here, a 1% by weight toluene solution of a pentacene derivative is coated by, for example, spin coating, and the solvent is then vaporized at 100° C., thereby forming the organic semiconductor layer14of 50 nm.

Here, in addition to the foregoing pentacene derivatives, high molecular weight materials (for example, polythiophene, fluorene-thiophene copolymers, and polyallylamine) and low molecular weight materials (for example, rubrene, thiophene oligomers, and naphthacene derivatives) may be used as the organic semiconductor14.

Also, in addition to the foregoing spin coating, the organic semiconductor14may also be formed by printing such as ink jetting, dispenser method, flexography, gravure printing, and offset printing. Incidentally, though an example of forming the organic semiconductor layer14is formed in a solid film state is explained herein, the organic semiconductor layer14may be subjected to patterning for every device by various printing methods, or the organic semiconductor layer14may be subjected to pattern formation by vacuum deposition using a shadow mask.

Next, as illustrated inFIG. 1C, a gate insulating film15is formed on the organic semiconductor layer14. Here, it is preferable that a surface of the gate insulating film15coming into contact with the organic semiconductor layer14is constituted of a water-repellent material. Thus, when a gate electrode material is pattern coated on the gate insulating film15by printing and heat treated in a later step, the gate electrode material is dried for solidification, whereby an interfacial characteristic between the organic semiconductor layer14and the gate insulating film15is improved during the formation of a gate electrode. As the water-repellent material, fluorocarbon resins and resins containing a water-repellent surface treating agent containing a perfluoroalkyl group, an alkysilyl group or the like can be used. Here, an amorphous perfluorocarbon resin which is a fluorocarbon resin (for example, CYTOP 809M, manufactured by Asahi Glass Co., Ltd.) is coated on the organic semiconductor layer14by, for example, spin coating, and the solvent is vaporized at 100° C., thereby forming the gate insulating film15in a thickness of 4 μm. Thereafter, by subjecting a surface of the gate insulating film15made of a water-repellent material to oxygen ashing to modify the surface state, its adhesion to a gate electrode to be formed in an upper layer is improved.

Incidentally, though an example of configuring the gate insulating film15by a single-layer film made of a water-repellent material is explained herein, a stack film of two or more kinds of insulating films may be configured. For example, it is more preferable that a second insulating layer made of a crosslinking high molecular weight material such as polyvinylphenol (PVP) is stacked on a first insulating layer made of the foregoing water-repellent material to form the gate insulating film15. In that case, a surface of the first insulating layer is subjected to oxygen ashing to form the second insulating layer. Thus, since the gate insulating film15becomes in a state that its gate electrode side as described later is covered by the crosslinking high molecular weight material, it is possible to prevent surely the leakage of a current. Examples of the foregoing crosslinking high molecular weight material which can be used include, in addition to the foregoing PVP, polymethyl methacrylate (PMMA), polyimide, polyvinyl alcohol (PVA), polyvinylidene fluoride (PVDF), polyisobutylene (PIB), polystyrene (PS), polyvinyl chloride (PVC), polyethylene terephthalate (PET), polycarbonate (PC), and benzocyclobutene (BCB).

Next, as illustrated inFIG. 1D, a gate electrode16is formed on the gate insulating film15. In that case, a gate electrode material made of a silver paste is pattern coated on the gate insulating film15by, for example, screen printing. Next, by performing a heat treatment, the foregoing silver paste is dried for solidification, thereby forming the gate electrode16made of silver. Here, it is preferable that the foregoing heat treatment is carried out at a temperature in the range of higher than a temperature at which a metal oxide contained in the gate electrode material is reduced and metallized and a temperature at which the foregoing organic semiconductor layer14is not deteriorated, for example, in a temperature range of 100° C. or higher and lower than 150° C. Here, the heat treatment is carried out at 120° C. Thus, not only the metal oxide contained in the silver paste is reduced and metallized, whereby the gate electrode16having a low resistivity value can be formed, but also the deterioration of the organic semiconductor layer14is prevented. Also, as described previously, after pattern coating the gate electrode material by printing, the heat treatment is carried out to form the gate electrode16, whereby an interfacial characteristic between the organic semiconductor layer14and the gate insulating film15is improved.

Incidentally, though the gate electrode16is constituted of silver herein, in addition to silver, metals (for example, gold, platinum, and palladium) and conductive organic materials made of poly(3,4-ethylenedioxythiophene)/poly(4-styrenesulfonate) [PEDOT/PSS] and polyaniline (PANI) can also be used.

Also, though an example of pattern coating the gate electrode material by employing screen printing is explained herein, any printing method is employable in an embodiment according to the invention. For example, ink jetting, flexography, offset printing, and pad printing may be employed. However, the formation of a gate electrode by screen printing is preferable because even when the substrate has a large area, the gate electrode material can be pattern coated with good reproducibility.

A thin film transistor10of a top gate type is thus accomplished on the substrate11.

Here,FIG. 2shows results obtained by measuring gate voltage (Vg)−drain current (Id) with respect to the thin film transistor10of the foregoing embodiment.

Here, a graph (1) shows results obtained by measuring the thin film transistor10in which the gate electrode16made of silver is formed on the gate insulating film15made of an amorphous perfluorocarbon resin by screen printing and heat treatment in the same manner as in the foregoing embodiment explained while referring toFIGS. 1A to 1D. Also, a graph (2) shows results obtained by measuring a thin film transistor in which the gate electrode16made of silver is formed on a gate insulating film in which a first insulating film made of an amorphous perfluorocarbon resin and a second insulating film made of PVP are stacked in this order by screen printing and heat treatment. Furthermore, a graph (3) shows results obtained by measuring a thin film transistor in which a gate electrode made of gold is formed on a gate insulating film made of an amorphous perfluorocarbon resin via a shadow mask by vapor deposition.

Incidentally, each of the thin film transistors is set up such that when a minus gate voltage (approximately −40 V) is applied, it becomes in an “ON” state. In measuring a drain current value, monitoring was carried out while continuously shifting the gate voltage in a minus direction and a plus direction.

As a result, it was confirmed that in the thin film transistor shown in the graph (3) to which an embodiment according to the invention is not applied, a turn-on voltage is 37 V, whereas in the thin film transistors shown in the graphs (1) and (2) to which an embodiment according to the invention is applied, a turn-on voltage is respectively 16 V and 6 V and shifted in a low voltage side, whereby a subthreshold characteristic is improved. Also, in the thin film transistors shown in the graphs (1) and (2), it was confirmed that an OFF-state current decreases and that an on/off ratio increases. In particular, in the case where the thin film transistor has a gate insulating film in which a first insulating film made of an amorphous perfluorocarbon resin and a second insulating film made of PVP are stacked as shown in the graph (2), it was confirmed that not only the subthreshold characteristic is markedly improved, but also the on/off ratio increases even in comparison with the results of the thin film transistor as shown in the graph (1).

Incidentally, while illustration is omitted herein, with respect to a thin film transistor of a bottom gate type in which a gate electrode is formed by screen printing and heat treatment, since irregularities are formed in a surface side of the gate electrode and irregularities are also formed on an interface between a gate insulating film and an organic semiconductor layer to be formed successively in an upper layer of the gate electrode, it was confirmed that a sufficient performance to such an extent that it is useful as a thin film transistor is not obtained.

Next, a display to which the foregoing thin film transistor of the present embodiment is applied is explained while referring to a liquid crystal display of an active matrix type in which the foregoing thin film transistor is disposed and formed on a back side substrate as an example. Incidentally, in explaining the configuration of a display, configuring elements of the thin film transistor are given the same symbols as inFIGS. 1A to 1Dand explained.

Here, a circuit diagram of an active matrix type provided on a back side substrate101in a display is illustrated inFIG. 3. As illustrated in this drawing, plural signal lines102and scanning lines103are disposed in a matrix state in a display region101A positioned in a central part of the back side substrate101made of a plastic-made substrate. In each intersect between the scanning line103and the signal line102, a thin film transistor10of a top gate type is provided as a pixel transistor. An auxiliary capacity device S and a display device D are connected to this thin film transistor10, and an auxiliary capacity line104is disposed in parallel to the foregoing scanning line103.

Also, a signal electrode drive circuit105to which the respective signal lines102are connected and a scanning electrode drive circuit106to which the respective scanning lines103are connected are disposed in a peripheral region of the display region101A in the back side substrate101. Also, the respective auxiliary capacity lines104are connected to a common electrode202disposed in a display side substrate as described later.

Next, a more detail configuration of the display region101A in the first substrate101is explained on the basis of a plan view ofFIG. 4Aand a sectional view ofFIG. 4B. Here,FIG. 4Ais an outline plan view in which a pixel region101B surrounded by the signal line102and the scanning line103in the display region101A (seeFIG. 3) is enlarged; andFIG. 4Bis an A-A′ line sectional view inFIG. 4A.

The signal line102made of silver and the drain electrode13are pattern formed on the back side substrate101illustrated only inFIG. 4B. The signal102is disposed in a state that it is provided extending in one direction, and the source electrode12is configured of a part of the signal line102. Also, the drain electrode13is disposed in a state that it covers the whole of the pixel region101B within a range not coming into contact with the signal line102. Incidentally, while an example in which the drain electrode13is disposed in a state that it covers the whole of the pixel region101B has been explained herein, it is enough that the drain electrode13is provided in a state that it overlaps a via and an auxiliary capacity electrode as described later at minimum.

The organic semiconductor layer14made of, for example, a pentacene derivative, which becomes a channel layer is pattern formed on the back side substrate101between the source electrode12and the drain electrode13. Also, the gate insulating film15made of an amorphous perfluorocarbon resin is provided on the back side substrate101including a top of the source electrode12and a top of the drain electrode13in a state that it covers this organic semiconductor layer14.

The scanning line103made of silver is disposed on the foregoing gate insulating film15in a state that it is provided extending in a direction orthogonal to the foregoing signal line102, and the auxiliary capacity line104made of silver is disposed in parallel to the foregoing scanning line103. The gate electrode16configured of a part of the foregoing scanning line103is disposed in a state that it covers a top of the organic semiconductor layer14; and an auxiliary capacity electrode17configured of a part of the auxiliary capacity line104is disposed in a state that it covers a part of a top of the foregoing drain electrode13. By interposing the gate insulating film15between the drain electrode13and the auxiliary capacity electrode17, the auxiliary capacity device S (see the foregoingFIG. 3) is configured. That is, the gate insulating film15also works as an auxiliary capacity insulating film.

Furthermore, an interlayer insulating film107is disposed on the gate insulating film15in a state that it covers the scanning line103and the auxiliary capacity line104. Also, a via hole107areaching the foregoing drain electrode13is provided in the foregoing gate insulating film15and the foregoing interlayer insulating film107. A pixel electrode109connected to the drain electrode13via a via108provided within the via hole107ais disposed in a matrix state on the interlayer insulating film107in a state that it covers the whole of the pixel region101B.

On the other hand, a display side substrate201which is disposed in a state that it is opposed to the foregoing back side substrate101is configured of a plastic-made substrate made of, for example, light transmissive PES. A common electrode202is disposed on a surface of the display side substrate201faced at a liquid crystal layer, and the auxiliary capacity line104disposed on the gate insulating film15is connected to this common electrode202.

A liquid crystal layer301is interposed between the foregoing back side substrate101and the foregoing display side substrate201in a state that the pixel electrode109and the common electrode202are opposed to each other. For this liquid crystal layer301, for example, a polymer dispersed liquid crystal (PDLC) is used.

Such a display is manufactured in the following manner. First of all, a conductive film made of silver is formed on the back side substrate101by, for example, spin coating, and the signal line102including the source electrode12and the drain electrode13are pattern formed by employing a usual lithography technology. Next, the organic semiconductor layer14made of a pentacene derivative is pattern formed by, for example, ink jetting. Next, the gate insulating film15made of an amorphous perfluorocarbon resin is formed on the back side substrate101including the top of the signal line102and the top of the drain electrode13by, for example, spin coating in a state that it covers the foregoing organic semiconductor layer14.

Next, a gate electrode material made of a silver paste is pattern coated on the gate insulating film15by screen printing and heat treated at 120° C., thereby forming the scanning line103(gate electrode16) made of silver and the auxiliary capacity line104(auxiliary capacity electrode17). Subsequently, the interlayer insulating film107made of polyimide is formed on the gate insulating film15by, for example, die coating in a state that it covers the scanning line103. Thereafter, the via hole107ain a state that it reaches the drain electrode13is formed in a region between the gate electrode16and the auxiliary capacity electrode17in the interlayer insulating film107and the gate insulating film15by a usual lithography technology.

Next, a silver paste is screen printed in a state that it embeds this via hole107aand dried for solidification, thereby not only forming the via108connected to the drain electrode13within the via hole107abut also disposing the pixel electrode109connected to this via108on the interlayer insulating film107in a matrix state.

On the other hand, the common electrode202made of ITO (indium tin oxide) is formed on the display side substrate201by, for example, sputtering.

Next, the back side substrate101and the display side substrate201are disposed opposite to each other in a state that the foregoing pixel electrode109and the foregoing common electrode202are opposed to each other, thereby bonding the both with a sealing material (not illustrated) provided in the surroundings of the back side substrate101and the display side substrate201. Subsequently, a liquid crystal material is filled between the back side substrate101and the display side substrate201, thereby forming the liquid crystal layer301. The liquid crystal display1thus accomplished is configured such that the display device D (see the foregoingFIG. 3) in which the liquid crystal layer301is interposed between the pixel electrode109and the common electrode202is disposed and formed in the thin film transistor10of a top gate type.

In the light of the above, according to the manufacturing method of a thin film transistor and the thin film transistor of the present embodiment, since the gate electrode material is pattern coated by printing, this case is low in costs and suitable for mass production as compared with the case of pattern forming the gate electrode16by employing a usual lithography technology. Accordingly, it is possible to improve the productivity. Furthermore, in the case of the thin film transistor10having the gate electrode16resulting from drying for solidification of the pattern coated gate electrode material, as explained previously while referring toFIG. 2, not only a subthreshold characteristic is improved, but also an on/off ratio increases as compared with the case of a thin film transistor having a gate electrode formed by vapor deposition using a shadow mask. Thus, it is possible to obtain a thin film transistor having excellent electric characteristics.

Also, since the display according to the present embodiment is not only improved in a subthreshold characteristic of the thin film transistor10but also increased in an on/off ratio, it is possible to design to realize low electricity consumption. Furthermore, according to the display of the present embodiment, when the pixel electrode109in a state that it is connected to the drain electrode13is formed on the interlayer insulating film107in a state that it covers the pixel region101B, an aperture can be taken widely so that it is possible to improve a luminance.

Modification Example 1

Incidentally, in the foregoing embodiment, though an example of forming the scanning line103and the auxiliary capacity line104in the same layer has been explained, the scanning line103and the auxiliary capacity line104may be formed in a different layer from each other. In that case, an outline configuration of the drive circuit to be provided in the back side substrate101is the same as that explained while referring toFIG. 3in the embodiment. In the present Modification Example, the same configurations as those in the foregoing embodiment are given the same symbols and explained.

Here,FIG. 5Ais an outline plan view in which a pixel region101B surrounded by a signal line102and a scanning line103in the display region101A (seeFIG. 3) is enlarged; andFIG. 5Bis a B-B′ line sectional view inFIG. 5A.

Here, an auxiliary capacity line104made of, for example, silver, apart of which becomes an auxiliary capacity electrode17, is pattern formed on a back side substrate101illustrated only inFIG. 5Bin a state that it is provided extending in one direction. This auxiliary capacity line104is disposed in parallel to a scanning line as described later. Incidentally, though an example in which the auxiliary capacity line104is disposed in parallel to the scanning line is explained herein, the disposal shape of the auxiliary capacity line104is not particularly limited and, for example, the auxiliary capacity line104may be disposed in parallel to a signal line as described later.

Incidentally, though the auxiliary capacity line104is constituted of silver herein, metals (for example, gold, platinum, and palladium) and conductive organic materials made of poly(3,4-ethylenedioxythiophene)/poly(4-styrenesulfonate) [PEDOT/PSS] and polyaniline (PANI) can also be used.

Also, an auxiliary capacity insulating film110is disposed on the back side substrate101in a state that it covers the foregoing auxiliary capacity line104. Here, it is preferable that this auxiliary capacity insulating film110is made of a material having a relatively large dielectric constant as from approximately 4 to 20 and formed in a thickness thinner than that of a gate insulating film as described later. For example, PVP can be used as this auxiliary capacity insulating film110. Thus, as described in detail later, it is possible to design an auxiliary capacity (Cs) large against a gate electrode-to-source electrode capacity (Cgs).

Also, the signal line102a part of which becomes a source electrode12and a drain electrode13are pattern formed on the auxiliary capacity insulating film110. This signal line102is provided extending in an orthogonal state to the foregoing auxiliary capacity line104, and the drain electrode13is disposed in a state that it covers the entire region of the pixel region101B within a range of not coming into contact with the signal line102. Here, a pixel electrode of a display device is configured in a state that it is connected to this drain electrode13in the same layer. For that reason, in the display of the present embodiment, a via for the extraction from the drain electrode13into the pixel electrode may not be formed, thereby omitting the formation step of a via. Such is preferable because not only a complicated lithography step for forming a via hole may not be carried out, but also a via hole may not be formed in a gate insulating film or an interlayer insulating film formed by coating in which an etching selection ratio to a resist material is hardly taken. By interposing the auxiliary capacity insulating film110between the drain electrode13and the auxiliary capacity electrode17, an auxiliary capacity device S (see the foregoingFIG. 3) is configured.

Also, an organic semiconductor layer14made of, for example, a pentacene derivative, which becomes a channel layer is pattern formed on the auxiliary capacity insulating film110between the source electrode12and the drain electrode13. Also, a gate insulating film15is provided on the auxiliary capacity insulating film110including a top of the source electrode12and a top of the drain electrode13in a state that it covers this organic semiconductor layer14.

The scanning line103is disposed on the foregoing gate insulating film15in a state that it is provided extending in a direction orthogonal to the foregoing signal line102and in parallel to the foregoing auxiliary capacity line104. Also, a gate electrode16configured of a part of the foregoing scanning line103is disposed in a state that it covers a top of the organic semiconductor layer14. Furthermore, an interlayer insulating film107is disposed on the gate insulating film15in a state that it covers this scanning line103.

On the other hand, likewise the embodiment, in the display side substrate201to be disposed in a state that it is opposed to the foregoing back side substrate101, a common electrode202is fabricated, and a liquid crystal layer301is interposed between the back side substrate101and a display side substrate201in a state that their electrode forming surface sides are opposed to each other.

Such a display is manufactured in the following manner. First of all, a silver ink is coated on the back side substrate101by, for example, spin coating and heat treated at 150° C., thereby fabricating a conductive film (not illustrated) made of silver in a thickness of 30 nm. Next, the auxiliary capacity line104made of silver is pattern formed by employing a usual lithography technology.

Here, in the forming step of the foregoing auxiliary capacity line104, ink jetting, screen printing and laser plotting may be employed as a forming method of a resist pattern used for a mask of etching. Furthermore, direct patterning by ink jetting, screen printing or microcontact printing can also be employed. However, in a later step, since an auxiliary capacity insulating film and a drain electrode (pixel electrode) are stacked successively on the back side substrate101in a state that it covers the auxiliary capacity line104, for the purpose of realizing good maintenance of a charge with less leakage of a current in an auxiliary capacity part, it is preferable that the surface of the auxiliary capacity line104has a flat surface and has a thickness as not more than 100 nm as thin as possible. In order to form the auxiliary capacity line104having a flattened surface and having a thickness of not more than 100 nm, it is preferred to employ the foregoing spin coating because the reproducibility is high. Besides, gravure coating, roll coating, kiss coating, knife coating, die coating, slit coating, and blade coating can also be employed.

Next, the auxiliary capacity insulating film110made of PVP is formed on the back side substrate101by, for example, die coating in a state that it covers the auxiliary capacity line104. Next, a conductive film made of silver is formed on the auxiliary capacity insulating film110by, for example, spin coating, and the signal line102including the source electrode12and the drain electrode13are pattern formed by employing a usual lithography technology.

Next, the organic semiconductor layer14made of a pentacene derivative is pattern formed on the auxiliary capacity insulating film110between the source electrode12and the drain electrode13by, for example, ink jetting. Next, the gate insulating film15is formed on the auxiliary capacity insulating film110including a top of the signal line102and a top of the drain electrode13by, for example, spin coating in a state that it covers the foregoing organic semiconductor layer14.

Next, a gate electrode material made of a silver paste is pattern coated on the gate insulating film15by screen printing and heat treated at 120° C., thereby forming the scanning line103(gate electrode16) made of silver. Subsequently, the interlayer insulating film107made of polyimide is formed on the gate insulating film15by, for example, die coating in a state that it covers the scanning line103.

The subsequent steps are carried out in the same manner as in the embodiment. That is, the common electrode202is formed on the display side substrate201; and the back side substrate101and the display side substrate201are disposed opposite to each other in a state that their electrode forming surfaces are opposed to each other, thereby bonding the both with a sealing material (not illustrated) provided in the surroundings of the back side substrate101and the display side substrate201. Subsequently, a liquid crystal material is filled between the back side substrate101and the display side substrate201, thereby forming the liquid crystal layer301.

The liquid crystal display2thus accomplished is configured such that a display device D (see the foregoingFIG. 3) in which the liquid crystal layer301is interposed between the pixel electrode made of the drain electrode13and the common electrode202is disposed and formed in the thin film transistor10of a top gate type.

Here, a pixel equivalent circuit diagram of the foregoing display device D is illustrated inFIG. 6. As illustrated in this drawing, the display device D and the auxiliary capacity device S are connected to the thin film transistor10in which the source electrode12, the drain electrode13, the organic semiconductor layer14and the gate electrode16are stacked in this order.

In this equivalent circuit diagram, when the pixel electrode charged at the time when the thin film transistor10is in an ON-state [(gate voltage Vg)=VHIGH] becomes in an OFF-state [(gate voltage Vg)=VLOW], it is influenced by the transition of the gate voltage, whereby the potential is lowered. The lowering of this voltage is called a field through voltage (ΔV) and expressed by the following expression (1).

Cdisplay: capacity of display partCs: auxiliary capacity

Though a shift of this field through voltage (ΔV) can be corrected by adjusting a Vcomvoltage of the common electrode202, it is desirable that it is designed to be as small as possible. Namely, in order to make ΔV small, the design must be made such that the gate electrode-to-source electrode capacity (Cgs) is small, whereas the auxiliary capacity (Cs) is large. The capacity C is regulated by dielectric constant and thickness of the insulating film as expressed by the following expression (2).

C=ɛ0⁢ɛrt(2)ε0: dielectric constant in vacuoεr: dielectric constant of insulating filmt: thickness of insulating film

In the embodiment, as explained previously while referring toFIGS. 4A and 4B, in the case where the scanning line103and the auxiliary capacity line104are formed in the same layer, since the gate insulating film15also works as an auxiliary capacity insulating film, a ratio of the gate electrode-to-source electrode capacity (Cgs) and the auxiliary capacity (Cs) is regulated by an area ratio of the gate electrode16and the auxiliary capacity electrode17.

However, as in the present Modification Example, in the case where the scanning line103and the auxiliary capacity line104are formed in a different layer from each other, since a ratio of the auxiliary capacity (Cs) to the gate electrode-to-source electrode capacity (Cgs) can be made large by not only using a material having a high dielectric constant for the auxiliary capacity insulating film110but also forming the auxiliary capacity insulating film110in a thickness thinner than that of the gate insulating film15, the field through voltage (ΔV) is reduced.

As explained previously, according to the liquid crystal display2of the present Modification Example, since the scanning line103is formed by heat treating the gate electrode material having been pattern formed by printing, the same effects as in the foregoing embodiment can be brought.

Furthermore, according to the display of the present Modification Example, since the auxiliary capacity line104and the scanning line103are formed in a different layer from each other, the field through voltage (ΔV) can be made small as described previously. Also, according to the foregoing display, since the drain electrode13also works as a pixel electrode, the forming step of a via can be omitted, and therefore, the manufacturing steps are simplified.

Incidentally, though in the foregoing embodiment and Modification Example 1, an example of a thin film transistor of a top gate/bottom contact type has been explained, an embodiment according to the invention is also applicable to a thin film transistor of a top gate/top contact type. Also, though in the foregoing embodiment and Modification Example 1, an example of a display provided with a liquid crystal display device as the display device D has been explained, it should not be construed that an embodiment according to the invention is limited thereto, but other display devices, for example, an organic electroluminescent device (organic EL device) and an electrophoresis type display device (E-ink) may be provided.