WLED driver and drive control method

A WLED driver and a drive control method. The WLED driver includes 2N2 switches, and each CS module includes 2N switches, where one end of each of N switches in the 2N switches is connected to an output end of an error amplifier, another end of each of the N switches is connected to a gate of each of N NMOS transistors, one end of each of remaining N switches is connected to a negative input end of the error amplifier, and another end of each of the remaining N switches is connected to a positive input end of each of N feedback resistors. After a control circuit generates a clock control signal group Φgroup. the control circuit controls switching actions of the 2N2 switches on a time-division basis according to the clock control signal group Φgroup.

TECHNICAL FIELD

The present invention relates to the field of technologies for controlling a current mismatch between channels in a white light emitting diode (WLED) driver, and in particular, to a WLED driver and a drive control method.

BACKGROUND

A WLED (White Light Emitting Diode, white light emitting diode) has advantages of a small size, pure light color, high light emitting efficiency, long service life, and the like, and is extensively applied in technical fields of display screen backlight, lighting, and the like, and in particular, is applied in mobile devices such as a smartphone and a tablet computer. Compared with other backlight technologies, it may significantly reduce a volume and weight of a device, and prolong a discharge time of a battery.

When working, the WLED requires a WLED driver and an input power source, where the WLED driver is integrated with a chip, and connected externally to a few peripheral components. In an actual application, to ensure consistency of luminance of multiple WLEDs while taking simplification of a WLED driver circuit and reduction of power consumption into account, generally, the multiple WLEDs are made into a WLED string or array. In terms of process and circuit feasibility, generally, a quantity of WLEDs that can be connected in series in one WLED string or array is approximately 11. For a device having a screen size of 4 to 6 inches, one WLED string including 11 WLEDs can meet an application requirement of the device. However, for a device having a screen size of more than 6 inches, such as a large-screen smartphone, a tablet computer, or a notebook computer, one WLED string cannot meet an application requirement of the device. Based on this, the prior art further proposes a WLED driver integrating multiple WLED string channels, where each channel corresponds to one WLED string. Therefore, when there are more channels, more WLED strings can be driven simultaneously.

As shown inFIG. 1, which shows a schematic structural diagram of a WLED driver in the prior art, the WLED driver includes a DC-DC CONVERTER (boost converter), a control circuit, and two precise programmable-controlled CSs (Current Sink, current sink1, where the DC-DC CONVERTER is configured to regulate an output voltage VOUTto an appropriate value according to a quantity of WLEDs mounted on any channel, the first current sink CS1is connected to the first channel IFB1, the second current sink CS2is connected to the second channel IFB2, and each CS is configured to determine a current intensity of a WLED string corresponding to a channel to which the CS is connected. In an ideal case, the current determined by the CS and a reference voltage VREFare in a preset proportional relationship.

CS precision of each channel is a key to ensuring consistency of luminance of WLED strings between channels. Generally, a CS implementation manner is to connect a high-gain operational amplifier and a power stage to form a unit negative feedback loop. However, in an actual application process, a mismatch between an input offset voltage of the operational amplifier and a feedback resistance of the power stage may cause a current difference between different channels in the WLED driver. For a present integrated circuit manufacturing process, it is easier to implement a good match of feedback resistances, but the input offset voltage of the operational amplifier has relatively great impact on a current mismatch between channels in the WLED driver. Therefore, in the prior art, to achieve consistency of luminance of WLED strings between multiple channels, a key lies in elimination of the channel current mismatch caused by the input offset voltage of the operational amplifier.

Still usingFIG. 1as an example, in the prior art, to reduce the current mismatch between the two channels IFB1and IFB2, it is necessary to introduce an error amplifier (EA, error amplifier) with a low input offset voltage. For a CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) process, the input offset voltage of the error amplifier is approximately several millivolts to tens of millivolts. A method for reducing the input offset voltage of the error amplifier is to make sizes of components in the error amplifier greater. However, this causes a die size of a chip to increase, which is disadvantageous for cost control, and cannot completely eliminate the current mismatch between channels. In addition, a trimming circuit may be added to an error amplifier circuit in the prior art to reduce the input offset voltage of the error amplifier. However, this method requires that trimming should be performed on each error amplifier separately, which increases the circuit complexity and cost.

Therefore, the prior art urgently requires a method for implementing an exact current match between multiple channels integrated in a WLED driver under a prerequisite that the input offset voltage of the error amplifier is not eliminated, to ensure consistency of luminance of WLEDs between multiple channels.

SUMMARY

In view of this, the present invention provides a WLED driver and a drive control method to provide a method for implementing an exact current match between multiple channels integrated in the WLED driver under a prerequisite that an input offset voltage of an error amplifier is not eliminated, to ensure consistency of luminance of WLEDs between multiple channels. Technical solutions are as follows:

According to a first aspect, the present invention provides a WLED driver, including a boost converter, a controller, and N channels, where N is a positive integer that is greater than 1, and each channel includes a current sink CS module, where the CS module is configured to drive a WLED string, and the CS module includes an error amplifier EA, an n-type metal-oxide-semiconductor NMOS transistor, and a feedback resistor, where: the WLED driver includes a total of 2N2switches, and each CS module includes 2N switches, where the 2N2switches constitute a switch matrix SG=Sg(i, j) and a switch matrix SFB=Sfb(i, j), where Sg(i, j) is a switch between an output end of an error amplifier in an ithCS module and a gate of an NMOS transistor in a jthCS module, Sfb(i, j) is a switch between a negative input end of the error amplifier in the ithCS module and a positive input end of a feedback resistor in the jthCS module, and both i and j are positive integers that are less than or equal to N;

the boost converter is configured to regulate an output voltage of the WLED driver according to a maximum quantity of WLEDs in a WLED string corresponding to any channel;

one end of each of N switches in the 2N switches included in the CS module is connected to an output end of the error amplifier, another end of each of the N switches is connected to a gate of each of N NMOS transistors, one end of each of remaining N switches is connected to a negative input end of the error amplifier, another end of each of the remaining N switches is connected to a positive input end of each of N feedback resistors, and the CS module is configured to determine a value of a current flowing through the WLED string on the channel; and

the control circuit is configured to generate a clock control signal group Φgroup, and control switching actions of the 2N2switches on a time-division basis according to the clock control signal group Φgroup, so that in a clock period T, an input offset voltage of the error amplifier is evenly applied on each channel in sequence on a time-division basis; where

the clock control signal group Φgroup=(Φ1, Φ2, . . . , ΦN), the clock control signal group Φgroupincludes N clock signals Φ, the N clock signals Φ are non-overlapping N-phase clock signals Φ of a same source, a clock signal Φi+jhas a delay of j×T/N in comparison with Φi, and T is a clock period of each phase clock.

In a first possible implementation manner of the first aspect,

the control circuit is specifically configured to control, According to the clock signal Φi, turn-on of switches in [Sg1i, Sg2(i+1), Sg(n−i+1)n, Sg(n−i+2)1, . . . , Sgn(i−1)] in the switch matrix SG, and turn-off of other switches in the switch matrix SG in the switch matrix SG; and control turn-on of switches [Sfb1i, Sfb2(i+1), . . . , Sfb(n−i+1)n, Sfb(n−i+2)1, . . . , Sfbn(i−1)] in the switch matrix SFB, and turn-off of other switches in the switch matrix SG in the switch matrix SFB.

With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner, the N is 2, 3, or 4.

According to a second aspect, the present invention provides a drive control method for a WLED driver, applied to a WLED driver, where the WLED driver includes N channels, where N is a positive integer that is greater than 1, and each channel includes a current sink CS module, where the CS module is configured to drive a WLED string, and the CS module includes an error amplifier EA, a metal-oxide-semiconductor NMOS transistor, and a feedback resistor, where: each CS module includes 2N switches, and the WLED driver includes a total of 2N2switches, where one end of each of N switches in the 2N switches included in the CS module is connected to an output end of the error amplifier, another end of each of the N switches is connected to a gate of each of N NMOS transistors, one end of each of remaining N switches is connected to a negative input end of the error amplifier, another end of each of the remaining N switches is connected to a positive input end of each of N feedback resistors, and the 2N2switches constitute a switch matrix SG=Sg(i, j) and a switch matrix SFB=Sfb(i, j), where Sg(i, j) is a switch between an output end of an error amplifier in an ithCS module and a gate of an NMOS transistor in a jthCS module, Sfb(i, j) is a switch between a negative input end of the error amplifier in the ithCS module and a positive input end of a feedback resistor in the jthCS module, and both i and j are positive integers that are less than or equal to N; and

the method includes:

generating a clock control signal group Φgroup, where the clock control signal group Φgroup=(Φ1, Φ2, . . . , ΦN), the clock control signal group Φgroupincludes N clock signals Φ, the N clock signals Φ are non-overlapping N-phase clock signals Φ of a same source, a clock signal Φi+jhas a delay of j×T/N in comparison with Φi, and T is a clock period of each phase clock; and

controlling switching actions of the 2N2switches on a time-division basis according to the clock control signal group Φgroup, so that in a clock period T, an input offset voltage of the error amplifier is evenly applied on each channel in sequence on a time-division basis.

In a first possible implementation manner of the second aspect, the controlling switching actions of the 2N2switches on a time-division basis according to the clock control signal group Φgroupspecifically includes:

controlling, according to the clock signal Φi, turn-on of switches in [Sg1i, Sg2(i+1), . . . , Sg(n−i+1)n, Sg(n−i+2)1, . . . , Sgn(i−1)] in the switch matrix SG, and turn-off of other switches in the switch matrix SG in the switch matrix SG; and controlling turn-on of switches [Sfb1i, Sfb2(i+1), . . . , Sfb(n−i+1)n, Sfb(n−i+2)1, . . . , Sfbn(i−1)] in the switch matrix SFB, and turn-off of other switches in the switch matrix SG in the switch matrix SFB.

With reference to the first possible implementation manner of the second aspect, in a second possible implementation manner, the N is 2, 3, or 4.

According to the foregoing technical solutions of the present invention, a WLED driver includes 2N2switches, and each CS module includes 2N switches. Specifically, one end of each of N switches in the 2N switches included in the CS module is connected to an output end of an error amplifier, another end of each of the N switches is connected to a gate of each of N NMOS transistors, one end of each of remaining N switches is connected to a negative input end of the error amplifier, and another end of each of the remaining N switches is connected to a positive input end of each of N feedback resistors. After a control circuit generates a clock control signal group Φgroup, the control circuit controls switching actions of the 2N2switches on a time-division basis according to the clock control signal group Φgroup, so that in a clock period T, an input offset voltage of the error amplifier is evenly applied on each channel in sequence on a time-division basis. Therefore, a problem of a current mismatch between channels that is caused by the input offset voltage of the error amplifier is eliminated, and thereby consistency of luminance of WLEDs between multiple channels is ensured.

DETAILED DESCRIPTION

Referring toFIG. 2, which shows a schematic structural diagram of a WLED driver according to the present invention, the WLED driver includes a boost converter100, a control circuit200, and N channels300, where each channel300includes a CS (current sink) module400, the CS module400is configured to drive a WLED string500, and N is a positive integer that is greater than 1.

The CS module400includes an EA (error amplifier, error amplifier)401, an n-type Metal-Oxide-Semiconductor (NMOS) transistor402, and a feedback resistor RFB403. In the present invention, each CS module400further includes 2N switches, where one end of each of N switches is connected to an output end of the EA401, another end of each of the N switches is connected to a gate of each of N NMOS transistors402, one end of each of remaining N switches is connected to a negative input end of the EA401, and another end of each of the remaining N switches is connected to a positive input end of each of N feedback resistors RFB403.

For ease of clear description, in the present invention, the N CS modules400are defined as a CS1module400, a CS2module400, a CS3module400, . . . , a CSn module400. Correspondingly, an NMOS transistor402located in the CS1module400is defined as Ms1, a feedback resistor RFB403located in the CS1module400is defined as RFB1, an NMOS transistor402located in the CS2module400is defined as Ms2, a feedback resistor RFB403located in the CS2module400is defined as RFB2, . . . , an NMOS transistor402located in the CSn module400is defined as Msn, and a feedback resistor RFB403located in the CSn module400is defined as RFBn. In addition, a channel including the CS1module400is defined as IFB1, a channel including the CS2module400is defined as IFB2, and a channel including the CSn module400is defined as IFBn.

Further, in the present invention, the CS1module400is used as an example to describe in detail a specific manner of setting switches in each CS module400, as shown inFIG. 3.

As seen from the figure, N switches exist between an output end of an EA1and the Ms1. Actually, one end of a switch VG1is connected to the output end of the EA1, while another end of the switch VG1is connected to a gate of the Ms1; one end of a switch VG2is connected to the output end of the EA1, while another end of the switch VG2is connected to a gate of the Ms2; and likewise, one end of a switch VGNis connected to the output end of the EA1, while another end of the switch VGNis connected to a gate of the Msn. Therefore, by controlling turn-on and turn-off of the N switches existing between the output end of the EA1and the Ms1in the figure, connections between the EA1and gates of NMOS transistors402in different CS modules400may be implemented.

In addition, as seen from the figure, N switches exist between a negative input end of the EA1and positive input ends of N feedback resistors. Actually, one end of a switch VFB1is connected to the negative input end of the EA1, while another end of the switch VG1is connected to a positive input end of the RFB1; one end of a switch VFB2is connected to the negative input end of the EA1, while another end of the switch VFB2is connected to a positive input end of the RFB2; likewise, one end of a switch VFBNis connected to the negative input end of the EA1, while another end of the switch VFBNis connected to a positive input end of the RFBN. Therefore, by controlling turn-on and turn-off of the N switches existing between the negative input end of the EA1and the N feedback resistors in the figure, connections between the EA1and positive input ends of the feedback resistors RFB403in different CS modules400may be implemented.

Because the WLED driver in the present invention includes a total of N CS modules400, and each CS module400includes 2N switches, the WLED driver in the present invention includes a total of 2N2switches. For ease of controlling switching of the 2N2switches, in the present invention, the 2N2switches are represented by two N×N switch matrices SGand SFB, where switch matrix SG=Sg(i, j) , and switch matrix SFB=Sfb(i, j) . Specifically, Sg(i, j) is a switch between an output end VOiof an error amplifier401in an ithCS module 400 and a gate of an NMOS transistor402in a jthCS module400, Sfb(i, j) is a switch between a negative input end of the error amplifier401in the ithCS module400and a positive input end of a feedback resistor403in the jthCS module400, and both i and j are positive integers that are less than or equal to N.

Specifically, in the present invention, an input voltage VINof the WLED driver generally does not meet a requirement for driving a WLED string. Therefore, a boost convert100is included in the WLED driver, and configured to regulate an output voltage VOUTof the WLED driver according to a maximum quantity of WLEDs in a WLED string corresponding to any channel300.

The CS module400is specifically configured to determine a value of a current flowing through the WLED string corresponding to the channel300. In an actual application process, the CS module400is generally a precise programmable-controlled CS module.

The control circuit200is configured to generate a clock control signal Φgroup, and control switching actions of the 2N2switches on a time-division basis according to the clock control signal group Φgroup, so that in a clock period T, an input offset voltage of the error amplifier is evenly applied on each channel in sequence on a time-division basis.

The clock control signal group Φgroup=(Φ1, Φ2, . . . , ΦN), the clock control signal group Φgroupincludes N clock signals Φ, the N clock signals Φ are non-overlapping N-phase clock signals Φ of a same source, a clock signal Φi+jhas a delay of j×T/N in comparison with Φi, and T is a clock period of each phase clock.

FIG. 4shows a schematic waveform diagram of a clock control signal group Φgroupaccording to the present invention. A clock period of each phase clock signal Φ is T, a duty cycle is 1/N, and there is a delay of T/N between adjacent clock signals Φ. Herein it should be noted that a clock period T of a clock signal Φ may be set freely, so long as blinking of WLEDs cannot be perceived by human eyes in principle.

Further, the control circuit200in the present invention is specifically configured to control, according to the clock signal Φi, turn-on of switches in [Sg1i, Sg2(i+1), . . . , Sg(n−i+1)n, Sg(n−i+2)1, . . . , Sgn(i=1)] in the switch matrix SG, and turn-off of other switches in the switch matrix SG in the switch matrix SG; and control turn-on of switches [Sfb1i, Sfb2(i+1), . . . , Sfb(n−i+1)n, Sfb(n−i+2)1, . . . , Sfbn(i−1)] in the switch matrix SFB, and turn-off of other switches in the switch matrix SG in the switch matrix SFB. Specifically, when the clock signal Φiis at a high level, the control circuit is configured to controls turn-on or turn-off of related switches in the switch matrices SGand SFB.

Specifically, in the present invention,

when a clock signal Φ1is received, and the Φ1is at a high level:

control turn-on of switches [Sg11, Sg22, . . . , Sgnn] in the switch matrix SG, and turn-off of other switches in the switch matrix SG; and

control turn-on of switches [Sfb11, Sfb22, . . . , Sfbnn] in the switch matrix SFB, and turn-off of other switches in the switch matrix SG;

when a clock signal Φ2is received, and the Φ2is at a high level:

control turn-on of switches [Sg12, Sg23, . . . , Sg(n−1)n, Sgn1] in the switch matrix SG, and turn-off of other switches in the switch matrix SG; and

control turn-on of switches [Sfb12, Sfb23, . . . , Sfb(n−1)n, Sfbn1] in the switch matrix SFB, and turn-off of other switches in the switch matrix SG;

when a clock signal Φiis received, and the Φiis at a high level:

when a clock signal ΦNis received, and the ΦNis at a high level:

control turn-on of switches [Sg1n, Sg21, . . . , Sg(n−1)(n−2), Sgn(n−1)] in the switch matrix SG, and turn-off of other switches in the switch matrix SG; and

control turn-on of switches [Sfb1n, Sfb21, . . . , Sfb(n−1)(n−2), Sfbn(n−1)] in the switch matrix SFB, and turn-off of other switches in the switch matrix SG.

Assuming that a loop gain of each CS module400in the present invention is high enough, and that input offset voltages of an EA1, an EA2, . . . , EAN are VOS1, VOS2, . . . , VOSNrespectively, then in a clock period T, an average current flowing through each CS module400is:

Apparently, the input offset voltage of each EA401has same impact on the average current of each CS module400in the present invention. To eliminate a problem of a current mismatch between multiple channels300in the WLED driver and achieve consistency of luminance of WLEDs between the multiple channels300, it is only necessary to ensure a good match of feedback resistors RFB403in the CS modules400.

Therefore, according to the foregoing technical solution of the present invention, a WLED driver includes 2N2switches, and each CS module400includes 2N switches. Specifically, one end of each of N switches in the 2N switches included in the CS module400is connected to an output end of an error amplifier401, another end of each of the N switches is connected to a gate of each of N NMOS transistors402, one end of each of remaining N switches is connected to a negative input end of the error amplifier401, and another end of each of the remaining N switches is connected to a positive input end of each of N feedback resistors403. After a control circuit200generates a clock control signal group Φgroup, the control circuit200controls switching actions of the 2N2switches on a time-division basis according to the clock control signal group Φgroup, so that in a clock period T, an input offset voltage of the error amplifier401is evenly applied on each channel300in sequence on a time-division basis. Therefore, a problem of a current mismatch between channels300that is caused by the input offset voltage of the error amplifier401is eliminated, and thereby consistency of luminance of WLEDs between multiple channels is ensured.

Preferably, in the present invention, N is equal to 2, 3, or 4. The present invention is hereinafter described in detail by using N=2 as an example.

Referring toFIG. 5, which shows another schematic structural diagram of a WLED driver according to the present invention, the WLED driver includes only a first channel IFB1and a second channel IFB2, where the first channel IFB1includes a first CS module410(hereinafter the CS1module for short), and the second channel IFB2includes a second CS module420(hereinafter the CS2module for short).

In this embodiment, the WLED driver includes a total of eight switches, where the CS1module includes four switches, and the CS2module includes four switches. Herein, in the present invention, a switch between an output end of an EA1in the CS1module and a gate of an NMOS transistor in the CS2module is defined as S1, a switch between the output end of the EA1in the CSi module and a gate of an NMOS transistor in the CS1module is defined as S2, a switch between a negative input end of the EA1in the CS1module and a positive input end of a feedback resistor RFB1in the CS1module is defined as S3, and a switch between the negative input end of the EA1in the CS1module and a positive input end of a feedback resistor RFB2in the CS2module is defined as S4.

Likewise, a switch between an output end of an EA2in the CS2module and the gate of the NMOS transistor in the CS1module is defined as S5, a switch between the output end of the EA2in the CS2module and the gate of the NMOS transistor in the CS2module is defined as S6, a switch between a negative input end of the EA2in the CS2module and the positive input end of the feedback resistor RFB2in the CS2module is defined as S7, and a switch between the negative input end of the EA2in the CS2module and the positive input end of the feedback resistor RFB1in the CS1module is defined as S8.

In this embodiment, a clock control signal group Φgroup=(Φ1, Φ2), that is, the eight switches in this embodiment are controlled by a clock signal Φ1and a clock signal Φ2. Specifically, the clock signal Φ1and the clock signal Φ2are non-overlapping two-phase clock signals of a same source, as shown inFIG. 6. When the clock signal Φ1is at a high level, the S2, S3, S6, and S7are turned on, and S1, S4, S5, and S8are turned off. When the clock signal Φ2is at a high level, S2, S3, S6, and S7are turned off, and S1, S4, S5, and S8are turned on.

In this embodiment, assuming that resistances of the feedback resistor RFB1and the feedback resistor RFB2are equal, and that loop gains of the CS1module and the CS2module are high enough, and that input offset voltages of the EA1and the EA2are VOS1and VOS2respectively, then in a clock period T, average currents flowing through the CS1module and the CS2module are respectively as follows:

Apparently, for the channels IFB1and IFB2, average currents of the channels are irrelevant to the input offset voltage of the EA. So long as a good match of the feedback resistor RFB1and the feedback resistor RFB2is ensured, a problem of an average current mismatch between the channels IFB1and IFB2in the WLED driver may be eliminated.

Based on a WLED driver provided by the present invention above, the present invention further provides a drive control method for a WLED driver, applied to a WLED driver. The WLED driver includes N channels, where N is a positive integer that is greater than 1, and each channel includes a CS module, where the CS module is configured to drive a WLED string.

The CS module includes an error amplifier EA, an NMOS transistor, and a feedback resistor. Each CS module includes 2N switches, and the WLED driver includes a total of 2N2switches. Specifically, one end of each of N switches in the 2N switches included in the CS module is connected to an output end of the error amplifier, another end of each of the N switches is connected to a gate of each of N NMOS transistors, one end of each of remaining N switches is connected to a negative input end of the error amplifier, and another end of each of the remaining N switches is connected to a positive input end of each of N feedback resistors. The 2N2switches constitute a switch matrix SG=Sg(i, j) and a switch matrix SFB=Sfb(i, j), where Sg(i, j) is a switch between an output end of an error amplifier in an ithCS module and a gate of an NMOS transistor in a jthCS module, Sfb(i, j) is a switch between a negative input end of the error amplifier in the ithCS module and a positive input end of a feedback resistor in the jthCS module, and both i and j are positive integers that are less than or equal to N.

Specifically, as shown inFIG. 7, the drive control method for a WLED driver includes:

Step101: Generate a clock control signal group Φgroup.

The clock control signal group Φgroup=(Φ1, Φ2, . . . , ΦN), the clock control signal group Φgroupincludes N clock signals Φ, the N clock signals Φ are non-overlapping N-phase clock signals Φ of a same source, a clock signal Φi+jhas a delay of j×T/N in comparison with Φi, and T is a clock period of each phase clock.

Step102: Control switching actions of 2N2switches on a time-division basis according to the clock control signal group Φgroup, so that in a clock period T, an input offset voltage of an error amplifier is evenly applied on each channel in sequence on a time-division basis.

In the present invention, when the WLED driver is working, the switching actions of the 2N2switches are controlled on a time-division basis according to the clock control signal group Φgroup.

when a clock signal Φ1is received, and the Φ1is at a high level, control turn-on of switches [Sg11, Sg22, . . . , Sgnn] in the switch matrix SG, and turn-off of other switches in the switch matrix SG; and control turn-on of switches [Sfb11, Sfb22, . . . , Sfbnn] in the switch matrix SFB, and turn-off of other switches in the switch matrix SG;

when a clock signal Φ2is received, and the Φ2is at a high level, control turn-on of switches [Sg12, Sg23, . . . , Sg(n−1)n, Sgn1] in the switch matrix SG, and turn-off of other switches in the switch matrix SG; and control turn-on of switches [Sfb12, Sfb23, . . . , Sfb(n−1)n, Sfbn1] in the switch matrix SFB, and turn-off of other switches in the switch matrix SG;

when a clock signal Φ1is received, and the Φiis at a high level, control turn-on of switches [Sg1i, Sg2(i+1), . . . , Sg(n−i+1)n, Sg(n−i+2)1, . . . , Sgn(i−1)] in the switch matrix SG, and turn-off of other switches in the switch matrix SG; and control turn-on of switches [Sfb1i, Sfb2(i+1), . . . , Sfb(n−i+1)n, Sfb(n−i+2)1, . . . , Sfbn(i−1)] in the switch matrix SFB, and turn-off of other switches in the switch matrix SG; and

when a clock signal ΦNis received, and the ΦNis at a high level, control turn-on of switches [Sg1n, Sg21, . . . , Sg(n−1) (n−2), Sgn(n−1)] in the switch matrix SG, and turn-off of other switches in the switch matrix SG; and control turn-on of switches [Sfb1n, Sfb21, . . . , Sfb(n−1) (n−2), Sfbn(n−1)] in the switch matrix SFB, and turn-off of other switches in the switch matrix SG.

Preferably, in the present invention, N is equal to 2, 3, or 4.

It should be noted that the embodiments in this specification are all described in a progressive manner, and that each embodiment focuses on a difference from other embodiments. For same or similar parts in the embodiments, reference may be made to these embodiments. The embodiment of the drive control method for a WLED driver is basically similar to the embodiment of a WLED driver, and therefore is described briefly. For related parts, reference may be made to partial descriptions in the embodiment of a WLED driver.

In the end, it should be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another, and do not necessarily require or imply that any actual relationship or sequence exists between these entities or operations. Moreover, the terms “include”, “include”, or their any other variant is intended to cover a non-exclusive inclusion, so that a process, a method, an article, or an apparatus that includes a list of elements not only includes those elements but also includes other elements which are not expressly listed, or further includes elements inherent to such process, method, article, or apparatus. An element preceded by “includes a . . . ” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

The WLED driver and drive control method provided in the embodiments of the present invention are described in detail above. The principle and implementation of the present invention are described herein through specific examples. The description about the embodiments of the present invention is merely provided to help understand the method and core ideas of the present invention. In addition, persons of ordinary skill in the art can make variations and modifications to the present invention in terms of the specific implementations and application scopes according to the ideas of the present invention. Therefore, the content of specification shall not be construed as a limit to the present invention.