Dual encapsulation integration scheme for fabricating integrated circuits with magnetic random access memory structures

Integrated circuits with magnetic random access memory (MRAM) and dual encapsulation for double magnesium oxide tunnel barrier structures and methods for fabricating the same are disclosed herein. As an illustration, an integrated circuit includes a magnetic random access memory structure that includes a bottom electrode that has a bottom electrode width and has bottom electrode sidewalls and a fixed layer overlying the bottom electrode that has a fixed layer width that is substantially equal to the bottom electrode width and has fixed layer sidewalls. The MRAM structure of the integrated circuit further includes a free layer overlying a central area of the fixed layer. Still further, the MRAM structure of the integrated circuit includes a first encapsulation layer disposed along the free layer sidewalls and a second encapsulation layer disposed along the bottom electrode sidewalls and the fixed layer sidewalls.

TECHNICAL FIELD

The present disclosure generally relates to integrated circuits and methods for fabricating integrated circuits. More particularly, the present disclosure relates to dual encapsulation integration scheme for fabricating integrated circuits with magnetic random access memory structures.

BACKGROUND

The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through an underlying channel between the source and drain regions.

Magnetic random access memory (MRAM) is a non-volatile computer memory technology based on magnetoresistance. MRAM differs from volatile random access memory (RAM) in several respects. Because MRAM is non-volatile, MRAM can maintain memory content when the memory device is not powered. Though non-volatile RAM is typically slower than volatile RAM, MRAM has read and write response times that are comparable to that of volatile RAM. Unlike typical RAM technologies that store data as electric charge, MRAM data is stored by magnetoresistive elements. Generally, the magnetoresistive elements are made from two magnetic layers, each of which holds a magnetization. The two magnetic layers are separated from one another by a barrier layer. Together, the two magnetic layers and the barrier layer are referred to as a “magnetic tunnel junction stack” (“MTJ stack”). The magnetization of one of the magnetic layers (the “pinned layer” or “fixed layer”) is fixed in its magnetic orientation, and the magnetization of the other layer (the “free layer”) can be changed by an external magnetic field generated by a programming current. Thus, the magnetic field of the programming current can cause the magnetic orientations of the two magnetic layers to be either parallel, giving a lower electrical resistance across the layers (“0” state), or antiparallel, giving a higher electrical resistance across the layers (“1” state). The switching of the magnetic orientation of the free layer and the resulting high or low resistance states across the magnetic layers provide for the write and read operations of the typical MRAM cell.

Presently-known MRAM structures and methods for fabricating such structures all suffer from several drawbacks. For example, the prior art has experienced difficulties in embedding an MRAM structure into sub-100 nanometer (nm) complementary MOS (CMOS) logic devices with common back-end-of-line (BEOL) interconnects, such as contacts, insulators, metal levels, bonding sites for chip-to-package connections, etc., without substantially impacting yield and reliability. That is, subsequent to performing an etching process used to form the two magnetic layers and the barrier layer, sidewalls of the MTJ stack are exposed. The MTJ stack, having exposed sidewalls, may be damaged during BEOL processing. Furthermore, mobile ions and other contaminants related to the MTJ stack etching process may degrade BEOL inter-level dielectrics (ILDs). Integration is particularly challenging when the MTJ stack is disposed with fine-pitch interconnects (e.g., to achieve smaller memory cells) in conjunction with the ILDs common to sub-100 nm CMOS devices.

Accordingly, it would be desirable to provide integrated circuits and methods for fabricating integrated circuits with MRAM structures that are not susceptible (or are less susceptible) to damage during common BEOL processes. Additionally, it would be desirable to provide integrated circuits and methods for fabricating integrated circuits with MRAM structures that are able to be integrated with fine-pitch (e.g., sub-100 nm) CMOS devices. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

BRIEF SUMMARY

Integrated circuits with magnetic random access memory structures and methods for fabricating integrated circuits with magnetic random access memory structures are disclosed herein. In one exemplary embodiment, an integrated circuit includes a magnetic random access memory (MRAM) structure that includes a bottom electrode that has a bottom electrode width in a width direction and comprises bottom electrode sidewalls that extend in a sidewall direction that is perpendicular to the width direction, a fixed layer overlying the bottom electrode that has a fixed layer width in the width direction that is substantially equal to the bottom electrode width in the width direction and comprises fixed layer sidewalls that extend in the sidewall direction, and a free layer overlying a central area of the fixed layer that has a free layer width in the width direction that is narrower than the bottom electrode width in the width direction and comprises free layer sidewalls that extend in the sidewall direction. The MRAM structure of the integrated circuit further includes a top electrode overlying the free layer that has a top electrode width in the width direction that is substantially equal to the free layer width in the width direction and comprises top electrode sidewalls that extend in the sidewall direction a first encapsulation layer disposed along the free layer sidewalls and the top electrode sidewalls and a second encapsulation layer disposed along the bottom electrode sidewalls and the fixed layer sidewalls.

In another exemplary embodiment, method for fabricating a magnetic random access memory structure of an integrated circuit includes forming a bottom electrode material layer, forming a fixed layer material layer and a first tunnel barrier layer material layer (e.g., of magnesium oxide) over the bottom electrode material layer, forming a free layer material layer over the fixed layer material layer and a second tunnel barrier layer material layer (e.g., of magnesium oxide), and forming a top electrode material layer over the fixed layer material layer. The method further includes removing the free layer material layer and the top electrode material layer from first lateral areas to form a free layer that has a free layer width in a width direction and that comprises free layer sidewalls that extend in a sidewall direction that is perpendicular to the width direction and a top electrode that has a top electrode width in the width direction that is substantially equal to the free layer width in the width direction and that comprises top electrode sidewalls that extend in the sidewall direction. The method further includes forming a first encapsulation layer along the free layer sidewalls and the top electrode sidewalls and over the top electrode and the first tunnel barrier layer material layer, subsequent to forming the first encapsulation layer, removing the bottom electrode material layer and the fixed layer material layer from second lateral areas to form a bottom electrode that has a bottom electrode width in the width direction that is wider than the free layer width in the width direction and that comprises bottom electrode sidewalls that extend in the sidewall direction and a fixed layer that has a fixed layer width in the width direction that is substantially equal to the bottom electrode width in the width direction and that comprises fixed layer sidewalls that extend in the sidewall direction Still further, the method includes forming a second encapsulation layer along the bottom electrode sidewalls and the second tunnel barrier layer material layer and the fixed layer sidewalls.

In yet another exemplary embodiment, an integrated circuit includes a magnetic random access memory structure that includes a bottom electrode that has a bottom electrode width in a width direction and has bottom electrode sidewalls that extend in a sidewall direction that is perpendicular to the width direction and a fixed layer overlying the bottom electrode that has a fixed layer width in the width direction that is substantially equal to the bottom electrode width in the width direction and has fixed layer sidewalls that extend in the sidewall direction. The bottom electrode includes a first conductive material and the fixed layer includes an anti-ferromagnetic material. The MRAM structure of the integrated circuit further includes a free layer overlying a central area of the fixed layer that has a free layer width in the width direction that is narrower than the bottom electrode width in the width direction and has free layer sidewalls that extend in the sidewall direction and a top electrode overlying the free layer that has a top electrode width in the width direction that is substantially equal to the free layer width in the width direction and has top electrode sidewalls that extend in the sidewall direction. The free layer includes a ferromagnetic material and the top electrode includes a second conductive material. Still further, the MRAM structure of the integrated circuit includes a first encapsulation layer disposed along the free layer sidewalls and the top electrode sidewalls and a second encapsulation layer disposed along the bottom electrode sidewalls and the fixed layer sidewalls. The first and second encapsulation layers include a silicon nitride material, and this is dual encapsulation for a double barrier layer magnetic tunnel junction scheme.

DETAILED DESCRIPTION

The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.

Embodiments of the present disclosure are generally directed to integrated circuits with magnetic random access memory structures and methods for fabricating integrated circuits with magnetic random access memory structures. For the sake of brevity, conventional techniques related to integrated circuit device fabrication may not be described in detail herein. Moreover, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor-based memory structures are well-known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

As used herein, it will be understood that when an element or layer, such as an MRAM element or layer, is referred to as being “on,” “overlying,” “connected to” or “coupled to” another element or layer, it may be directly on, overlying, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. Further, spatially relative terms, such as “beneath,” “below,” “over,” “under,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the MRAM structure in the figures is turned over, elements described as being “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substantially” refers to the complete, or nearly complete, extent or degree of an action, characteristic, property, state, structure, item, or result. As an arbitrary example, an object that is “substantially” enclosed would mean that the object is either completely enclosed or nearly completely enclosed. The exact allowable degree of deviation from absolute completeness may in some cases depend on the specific context. However, generally speaking the nearness of completion will be so as to have the same overall result as if absolute and total completion were obtained.

FIGS. 1-13illustrate, in cross section, integrated circuits with MRAM structures and methods for fabricating integrated circuits with MRAM structures in accordance with exemplary embodiments of the present disclosure. With attention toFIG. 1, the cross-sectional view illustrates a first interlayer dielectric layer (ILD layer)101with a first metallization layer102disposed within the first ILD layer101. In one embodiment, the first ILD layer101is formed of one or more low-k dielectric materials, un-doped silicate glass (USG), silicon nitride, silicon oxynitride, or other commonly used materials. The dielectric constants (k value) of the low-k dielectric materials may be less than about 3.9, for example, less than about 2.8. The first ILD layer101is formed using conventional deposition techniques, which depend on the particular material employed. In an exemplary embodiment, the first ILD layer101includes a silicon oxide material and is formed by means of a chemical vapor deposition (CVD) process or a plasma-enhanced CVD process in which tetraethyl orthosilicate (TEOS) is used as a reactant.

Though not illustrated for simplicity in the Figures, the first ILD layer101may be formed over an active region of a semiconductor substrate forming part of the integrated circuit. In this regard, the semiconductor substrate may include a plurality of isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. The isolation features may define and isolate the various microelectronic elements (not shown). Examples of the various microelectronic elements that may be formed in the substrate include transistors (e.g., MOSFETs and/or bipolar junction transistors (BJT)), and/or other suitable elements. These microelectronic elements may be used as selector devices for the disclosed MRAM structures, as is known in the art.

The first metallization layer102includes a conductive material compatible with the particular BEOL processes employed. For example, in one embodiment, the first metallization layer102includes a copper material. In this embodiment, the first metallization layer102is formed using conventional damascene processes. That is, trenches or cavities for the first metallization layer102are formed in the first ILD layer101. The copper material is then be deposited over the first ILD layer101to overfill the trenches or cavities, and the excess copper material is removed by polishing (such as chemical mechanical polishing), such that an upper surface of the first metallization layer102and an upper surface of the first ILD layer101are substantially co-planar, as illustrated. In another embodiment, the first metallization layer102includes a conductive material that does not require damascene processes, such as aluminum. In this embodiment, a layer of an aluminum material may be formed over the first ILD layer101and then etched into the desired shape of the first metallization layer102. Additional ILD material is then deposited alongside the first metallization layer102resulting in the structure as shown inFIG. 1. Regardless of the material employed, the first metallization layer102may be deposited using conventional deposition techniques, such as physical vapor deposition (PVD).

With reference now toFIG. 2, a passivation layer103is formed over the upper surfaces of the first metallization layer102and the first ILD layer101. In one embodiment, the passivation layer103is formed of a non-organic material selected from un-doped silicate glass (USG), silicon nitride, silicon oxynitride, silicon oxide, or combinations thereof. In an alternative embodiment, the passivation layer103is formed of a polymer layer, such as an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like, although other organic dielectric materials may also be used. In a particular embodiment, the passivation layer103is formed of a silicon carbide-based passivation material layer including nitrogen. For example, silicon carbide with nitrogen deposited using CVD from a trimethylsilane source, which is commercially available from Applied Materials (Santa Clara, Calif., USA) under the trade name of BLOK®, is used as the passivation layer103.

FIG. 3illustrates the formation of a second ILD layer106over the passivation layer103and the formation of a conductive via structure105through both the passivation layer103and the second ILD layer106. The second ILD layer106, as with first ILD layer101, is formed of one or more low-k dielectric materials, USG, silicon nitride, silicon oxynitride, or other commonly used materials. The second ILD layer106is formed using conventional deposition techniques, which depend on the particular material employed.

The conductive via structure105is formed by etching a trench through the passivation layer103and the second ILD layer106to expose a portion of the upper surface of the first metallization layer102and filling the trench with a conductive material. In this regard, known photolithographic patterning and etching procedures are used to form the trench through the passivation layer103and the second ILD layer106. That is, a photoresist layer (not separately illustrated) is deposited over the second ILD layer106and then is exposed to an image pattern and treated with a developing solution to form a pattern opening within the photoresist layer. With the photoresist layer thus patterned, the second ILD layer106and the passivation layer103are etched to form the trench, which is then filled with the conductive material to form the conductive via structure105. In one embodiment, the conductive material may be the same material used in to form the first metallization layer102, such as the copper material or the aluminum material. In other embodiments, the conductive material may be different. Chemical mechanical polishing may be used to remove excess conductive material, such that an upper surface of the conductive via structure105and an upper surface of the second ILD layer106are substantially co-planar, as illustrated.

With reference now toFIG. 4, in an exemplary embodiment, a series of material layers107,108,109,110,111, and185are formed overlying one another. As illustrated, a bottom electrode material layer107is formed overlying the upper surfaces of the conductive via structure105and the second ILD layer106, a fixed layer material layer108is formed overlying the bottom electrode material layer107, a first tunnel barrier layer material layer109is formed overlying the fixed layer material layer108, a free layer material layer110is formed overlying the first barrier layer material layer109, a second tunnel barrier layer material layer111is formed overlying the free layer material layer110, and a top electrode material layer185is formed overlying the second barrier layer material layer111. As previously noted, as used herein, the term “overlying” may refer to a direct and abutting overlay, or there may be other layers disposed in between that stated overlying layers. As such, and by way of example, while the top electrode material layer185is illustrated in as directly and abuttingly overlying the second barrier layer material layer111, it will be understood that the top electrode material layer185may be considered as overlying any of the material layers107through110as well. Material layers108,109,110, and111form the basis of the MTJ stack of the MRAM structure to be formed. By means of the conductive via structure105, the bottom electrode material layer107is electrically connected to the first metallization layer102, and thus to the MTJ stack of the MRAM to be formed. The thicknesses of each such layer107,108,109,110,111, and185will depend on the overall dimensions of the MRAM structure to be formed, as well as the operational parameters of the MRAM structure to be formed, as is known in the art. The processes used for forming such layers are conventional with respect to the particular material selected.

In one embodiment, the bottom electrode material layer107includes a conductive material. For example, the bottom electrode material layer107may include a conductive metal, such as tantalum, tantalum nitride, or titanium, or a combination of one or more thereof. The fixed layer material layer108includes an anti-ferromagnetic material. For example, the fixed layer material layer108may include a metal alloy such as platinum manganese (PtMn), iridium manganese (IrMn), nickel manganese (NiMn), or iron manganese (FeMn), or a combination of one or more thereof. It will be appreciated that the fixed layer material layer108could include multiple layers such as a synthetic anti-ferromagnetic (SAF) layer to ensure that the fixed layer magnetism is fixed. Other fine-tuning layer(s) to improve coupling could also be added, in an embodiment. The first barrier layer material layer109includes an insulating tunnel barrier material, such as magnesium oxide, amorphous aluminum oxide, or silicon dioxide, or a combination of one or more thereof. The free layer material layer110includes a ferromagnetic material. For example, the free layer material layer110may include a metal alloy such as cobalt iron boron (CoFeB). The second barrier layer material layer111, as with the first barrier layer material layer109, includes an insulating tunnel barrier material, such as magnesium oxide, amorphous aluminum oxide, or silicon dioxide, or a combination of one or more thereof. Further, the top electrode material layer185, independently from the bottom electrode material layer107, may include a conductive metal, such as tantalum, tantalum nitride, or titanium, or a combination of one or more thereof.

FIG. 5further depicts the structure that results after the removal of a portion of the free layer material layer110, a portion of the second barrier layer material layer111, and a portion of the top electrode material layer185illustrated inFIG. 4. That is, as shown inFIG. 5, the remaining portion of each of material layers110,111, and185form a free layer112, a second barrier layer113, and a top electrode114. The removed portions of material layers110,111, and185fromFIG. 4are removed from first lateral areas190aand190b, as shown inFIG. 5. After such removal, the remaining portion of each of material layers110,111, and185are in first central area191, which is positioned between first lateral areas190aand190b, as illustrated. As such, the layers112,113, and114are all overlying the first central area191of the material layers107,108, and109. Additionally, an upper surface of the first barrier layer material layer109is exposed in areas first lateral190aand190b. The removal of the portions of material layers110,111, and185may be accomplished using any conventional patterning and etching process. For example, a photoresist layer (not separately illustrated) is deposited over the top electrode material layer185and then is exposed to an image pattern and treated with a developing solution to form a pattern opening within the photoresist layer. With the photoresist layer thus patterned, the material layers110,111, and185are etched away in first lateral areas190aand190b, leaving the material layers110,111, and185remaining in first central area191to form the layers112,113, and114. The free layer112, the second barrier layer113, and the top electrode114each have a width186in a width direction (the term “width direction” is used herein with respect to a direction that is substantially parallel to an upper surface of the semiconductor substrate of the integrated circuit) that is substantially the same with respect to each such layer112,113, and114. That is, a free layer width, a second barrier layer width, and a top electrode width in the width direction are all substantially equal with respect to one another. Additionally, the free layer112has free layer sidewalls145at lateral ends thereof, the second barrier layer113has second barrier layer sidewalls146at lateral ends thereof, and the top electrode114has top electrode sidewalls147at lateral ends thereof. The sidewalls145,146, and147each extend in a direction188that is generally perpendicular to the above-described width direction, that is, in a direction perpendicular to the upper surface of the semiconductor substrate of the integrated circuit, which is hereinafter referred to as a “sidewall direction.” With the widths of the layers112,113, and114being substantially the same as described above, the sidewalls145,146, and147are substantially co-planar with one another, as illustrated.FIG. 5also shows that a first encapsulation layer115is formed in-situ with regard to the etch process, for example by conventional conformal deposition processes, over the exposed upper surface of the first barrier layer material layer109in first lateral areas190aand190b, along the sidewalls145,146, and147, and over the top electrode114in first central area191. The first encapsulation layer115includes a dielectric material, such as a silicon nitride material. The first encapsulation layer115serves to protect the free layer112, the second barrier layer113, and the top electrode114, in particular the sidewalls145,146, and147thereof, from subsequent BEOL processes that could damage such layers (or sidewalls), as described above.

As shown inFIG. 6, a hardmask layer material layer176is formed over the first encapsulation layer115. The hardmask layer material layer176is formed of a dielectric material, such as a silicon oxide material, using conventional blanket deposition processes. In this regard, the first encapsulation layer overlies first lateral areas190aand190bof the material layers107,108, and109, wherein, as noted above the lateral areas190a,190bof these material layers are adjacent to the central area191of these material layers. Moreover, the hardmask material layer176overlies the first encapsulation layer115and the lateral areas190a,190bof the material layers107,108, and109.

FIGS. 7 and 8depict the removal of a portion of the bottom electrode material layer107, a portion of the fixed layer material layer108, a portion of the first barrier layer material layer109, a portion of the first encapsulation layer115, and a portion of the hardmask layer material layer176. The removal of the portions of material layers107,108,109,115, and176may be accomplished using any conventional patterning and etching process. That is, as shown inFIG. 7, a photoresist layer177is deposited over the hardmask layer material layer176and then is exposed to an image pattern and treated with a developing solution to form a pattern opening within the photoresist layer177. With the photoresist layer177thus patterned, the material layers107,108,109,115, and176are etched away in second lateral areas192aand192bas shown inFIG. 8, leaving the material layers107,108,109,115, and176remaining in second central area193. The etching thus forms a bottom electrode118, a fixed layer119, a first barrier layer120, and a hardmask layer121. Additionally, the upper surface of the second ILD layer106is exposed in second lateral areas192aand192b. The bottom electrode118, the fixed layer119, the first barrier layer120, and the hardmask layer121each have a width187in the above-described width direction that is substantially the same with respect to each such layer118,119,120, and121. That is, a bottom electrode width, a fixed layer width, a first barrier layer width, and a hardmask layer width are all substantially equal with respect to one another. As width187is wider than width186(and conversely, width186is narrower than width187) each of the bottom electrode width, the free layer width, the first barrier layer width, and the hardmask layer width is wider than each of the free layer width, the second barrier layer width, and the top electrode width. The difference in widths186and187, in an embodiment, may be at least about 20%, such as at least about 50%. Additionally, the bottom electrode118has bottom electrode sidewalls122at lateral ends thereof, the fixed layer119has fixed layer sidewalls123at lateral ends thereof, the first barrier layer120has first barrier layer sidewalls124at lateral ends thereof, and the hardmask layer121has hardmask layer sidewalls125at lateral ends thereof. The sidewalls122,123,124, and125each extend in a direction that is generally perpendicular to the above-described width direction, i.e., in the sidewall direction. With the widths of the layers118,119,120, and121being substantially the same as described above, the sidewalls122,123,124, and125are substantially co-planar with one another, as illustrated.FIG. 8also shows that a second encapsulation layer126is formed, for example by conventional conformal deposition processes, over the exposed upper surface of the second ILD layer106in second lateral areas192aand192b, along the sidewalls122,123,124, and125, and over the hardmask layer121in second central area193. The second encapsulation layer126includes a dielectric material, such as a silicon nitride material. The second encapsulation layer126serves to protect the bottom electrode118, the fixed layer119, and the first barrier layer120, in particular the sidewalls122,123, and124thereof, from subsequent BEOL processes that could damage such layers (or sidewalls), as described above.

With reference now toFIG. 9, a third ILD layer127is formed over the second encapsulation layer126. The third ILD layer127, as with first ILD layer101and second ILD layer106, is formed of one or more low-k dielectric materials, USG, silicon nitride, silicon oxynitride, or other commonly used materials. The third ILD layer127is formed using conventional deposition techniques, which depend on the particular material employed.

FIG. 10illustrates the removal of a portion of the second encapsulation layer126overlying the hardmask layer121, a portion of the hardmask layer121, and a portion of the first encapsulation layer115overlying the top electrode114. This removal may be accomplished using a suitable polishing or planarization technique, such as chemical mechanical polishing. The removal of portions of each of the layers126,121, and115occurs above an upper surface of the top electrode114and within second central area193. As a result of this polishing or planarization, first encapsulation layer115is separated into first encapsulation layer portions115aand115b, with portion115abeing disposed over the first barrier layer120in first lateral area190aand along sidewalls145,146, and147adjacent thereto, and with portion115bbeing disposed over the first barrier layer120in first lateral area190band along sidewalls145,146, and147adjacent thereto. The second encapsulation layer126is separated into second encapsulation layer portions126aand126b, with portion126abeing disposed over the second ILD layer106in second lateral area192aand along sidewalls122,123,124, and125adjacent thereto, and with portion126bbeing disposed over the second ILD layer106in second lateral area192band along sidewalls122,123,124, and125adjacent thereto. The hardmask layer121is separated into hardmask layer portions121aand121b, with portion121abeing disposed between the first and second encapsulation layer portions115a,126a, and with portion121bbeing disposed between the first and second encapsulation layer portions115b,126b, as illustrated. Furthermore, as a result of this polishing or planarization, upper surfaces of the third ILD layer127, the hardmask layer portions121a,121b, and the top electrode114are substantially co-planar with respect to one another. Upper ends of the first encapsulation layer portions115a,115band upper ends of the second encapsulation layer portions126a,126bare also co-planar with respect thereto.

With reference now toFIG. 11, a third encapsulation layer128is formed, for example by conventional conformal deposition processes, over the upper surfaces of the third ILD layer127, the hardmask layer portions121a,121b, and the top electrode114. The third encapsulation layer also connects with the upper ends of the first encapsulation layer portions115a,115band with the upper ends of the second encapsulation layer portions126a,126b. The third encapsulation layer128includes a dielectric material, such as a silicon nitride material. As further shown inFIG. 9, a fourth ILD layer129is formed over the third encapsulation layer128. The fourth ILD layer129, as with first ILD layer101, second ILD layer106, and the third ILD layer127is formed of one or more low-k dielectric materials, USG, silicon nitride, silicon oxynitride, or other commonly used materials. The fourth ILD layer129is formed using conventional deposition techniques, which depend on the particular material employed.

FIG. 12illustrates the formation of a second metallization layer130within the fourth ILD layer129and the third encapsulation layer128. The second metallization layer130includes a conductive material compatible with the particular BEOL processes employed. For example, in one embodiment, the second metallization layer130includes a copper material. In this embodiment, the second metallization layer130is formed using conventional damascene processes. That is, trenches or cavities for the for the second metallization layer130are formed in the fourth ILD layer129and the third encapsulation layer128to expose at least a portion of the top electrode114. The copper material is then be deposited over the fourth ILD layer129to overfill the trenches or cavities, and the excess copper material is removed by polishing (such as chemical mechanical polishing), such that an upper surface of the second metallization layer130and an upper surface of the fourth ILD layer129are substantially co-planar, as illustrated. In this manner, the second metallization layer130becomes electrically connected with the top electrode114. In another embodiment, the second metallization layer130includes a conductive material that does not require damascene processes, such as aluminum. In this embodiment, a layer of an aluminum material may be formed over the fourth ILD layer129and then etched into the desired shape of the second metallization layer130. Additional ILD material is then deposited alongside the second metallization layer130resulting in the structure as shown inFIG. 12. Regardless of the material employed, the second metallization layer130may be deposited using conventional deposition techniques, such as PVD.

Thereafter, the MRAM structure may be completed by forming conventional interconnect structures and chip-to-chip connection structures. By way of non-limiting illustration,FIG. 13illustrates interconnection structure135electrically connected to the second metallization layer130in area137. Additionally, interconnection structure135may include a bonding site136for chip-to-chip connection structures (not separately illustrated herein). Interconnection structure135may include any suitable conductive material, such as aluminum. Interconnection structure135may be otherwise isolated from the second metallization layer130of the MRAM structure by one or more diffusion barrier layers131, one or more passivation layers132,134, and one or more dielectric insulation layers133, each of which may be formed using conventional materials as are known in the art and using conventional processes as are known in the art. The completion of an integrated circuit including the above-described MRAM structures may be accomplished using conventional BEOL processes, and in particular BEOL processes that are suitable for the formation of CMOS logic devices in sub-100 nm design architectures.

Accordingly, disclosed herein are integrated circuits with magnetic random access memory structures and methods for fabricating integrated circuits with magnetic random access memory structures. As described above, the first encapsulation layer115serves to protect the free layer112, the second barrier layer113, and the top electrode114, in particular the sidewalls145,146, and147thereof, from BEOL processes that could damage such layers/sidewalls. Further, the second encapsulation layer126serves to protect the bottom electrode118, the fixed layer119, and the first barrier layer120, in particular the sidewalls122,123, and124thereof, from these BEOL processes. In this manner, the described embodiments provide integrated circuits and methods for fabricating integrated circuits with MRAM structures that are not susceptible (or are less susceptible) to damage during common BEOL processes. In particular, the described integrated circuits and methods for fabricating integrated circuits with MRAM structures are able to be integrated with sub-100 nm CMOS devices.