System and method of controlling power consumption

A system and method of controlling power consumption are provided. The example method may be directed to controlling power consumption in a system including first and second interface blocks, and may include transitioning a first interface block to a power saving mode in response to a status of a first transmission channel, the first transmission channel configured to forward information from the first interface block to a second interface block and transitioning a second interface block to the power saving mode in response to a status of a second transmission channel, the second transmission channel configured to forward information from the second interface block to the first interface block. The example system may include a first interface block transitioning to a power saving mode in response to a status of a first transmission channel and a second interface block transitioning to the power saving mode in response to a status of a second transmission channel, the first transmission channel configured to forward information from the first interface block to the second interface block and the second transmission channel configured to forward information from the second interface block to the first interface block.

PRIORITY STATEMENT

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application 2005-113651 filed on Nov. 25, 2005, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Example embodiments of the present invention are related generally to a system and method thereof, and more particularly to a system and method of controlling power consumption.

2. Description of the Related Art

Low-voltage differential signaling (LVDS) may be employed in various fields of commercial applications. LVDS may refer to a type of interface standard for higher-speed data transmissions. For example, the ANSI/TIA/EIA-644-1995 standard may be an example LVDS standard which may define specifications for physical layers as electronic interface solutions. LVDS techniques including lower-voltage signals may increase bit rates, lower power consumption, and/or reduce noise in, for example, mobile communication stations, asynchronous transfer mode (ATM) switch applications, higher-resolution display devices, printers, digital copying machines, etc.

Internet applications may increasingly require higher amounts of data bandwidth. Furthermore, data streaming operations may be performed with higher bandwidth for digital video processing, higher-definition televisions and/or color graphic treatments. Conventionally, higher bandwidth data transmission systems may employ LVDS, which may allow higher data bandwidth (e.g., multi-gigabit data transmission) through copper-based interconnection via a higher-frequency analog circuit technology. Different versions of LVDS may include ground-referenced LVDS (GRLVDS) and bus LVDS (BLVDS), which may be deployed in bilateral and/or multi-drop schemes. GRLVDS may provide higher-frequency data communication with lower voltages by making differential and common mode signals swing near to a ground voltage level. Generally, LVDS, BLVDS and GRLVDS may represent examples of serial interfaces.

SUMMARY OF THE INVENTION

An example embodiment of the present invention is directed to a method of controlling power consumption in a system including first and second interface blocks, including transitioning a first interface block to a power saving mode in response to a status of a first transmission channel, the first transmission channel configured to forward information from the first interface block to a second interface block and transitioning a second interface block to the power saving mode in response to a status of a second transmission channel, the second transmission channel configured to forward information from the second interface block to the first interface block.

Another example embodiment of the present invention is directed to a system, including a first interface block transitioning to a power saving mode in response to a status of a first transmission channel and a second interface block transitioning to the power saving mode in response to a status of a second transmission channel, the first transmission channel configured to forward information from the first interface block to the second interface block and the second transmission channel configured to forward information from the second interface block to the first interface block.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS OF THE PRESENT INVENTION

Detailed illustrative example embodiments of the present invention are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present invention. Example embodiments of the present invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.

Accordingly, while example embodiments of the invention are susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments of the invention to the particular forms disclosed, but conversely, example embodiments of the invention are to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like numbers may refer to like elements throughout the description of the figures.

FIG. 1is a block diagram illustrating a first sub-system1000and a second sub-system2000according to an example embodiment of the present invention. In the example embodiment ofFIG. 1, first and second sub-systems1000and2000may communicate via a serial interface. In an example, the serial interface may conform with lower-voltage differential signaling (LVDS) standards for interfacing with higher-frequency data transmission. However, it will be appreciated by one of ordinary skill in the art that other well-known serial interfaces may also be used (e.g., bus LVDS (BLVDS), ground referenced LVDS (GRLVDS), etc.)

In the example embodiment ofFIG. 1, the first sub-system1000may include an application processor (AP)1200and a first serial interface block1400. The second sub-system2000may include a second serial interface block2200and a user interface block2400. In the first sub-system1000, the first serial interface block1400may transform parallel data, provided from the AP1200, into serial data, and may output the serial data to the second sub-system2000in accordance with a given serial interface protocol (e.g., LVDS). The first serial interface block1400may also transform serial data, provided from the second sub-system2000, into parallel data, and may output the parallel data to the AP1200. In the second sub-system2000, the second serial interface block2200may transform serial data, transferred from the first sub-system1000, into parallel data, and may output the parallel data to the user interface block2400. The user interface block2400may process the data output from the second serial interface block2200(e.g., for output to a user). In an example, the user interface block240may include a display such a liquid crystal display (LCD) unit, a speaker for outputting audio signals, etc.

While not shown inFIG. 1, if the system ofFIG. 1is embodied as a portable device, such as a mobile phone or a notebook computer, the first sub-system1000may be supplied with power via a power supply unit (e.g., a battery) (not shown). The second sub-system2000may likewise be supplied with power from the power supply unit of the first sub-system1000. Generally, if batteries are used, it may be desirable to reduce standby power so as to increase an operating time of portable devices between charges. In order to reduce standby power, the system ofFIG. 1may be configured to selectively engage a power saving mode (e.g., in a standby or inactive mode), as will now be described in greater detail with respect to example embodiments of the present invention.

FIG. 2is a block diagram illustrating the first and second serial interface blocks1400and2200of the first and second sub-systems1000and2000, respectively, ofFIG. 1according to another example embodiment of the present invention.

In the example embodiment ofFIG. 2, the serial interface block1400of the first sub-system1000may include a system controller1410, a host controller1420, a client controller1430, an interface unit1440, and a LVDS input/output (I/O) unit1450. In an example, the system controller1410, the host controller1420, the client controller1430, and the interface unit1440may be configured so as to communicate with each other via bus1401. While not illustrated in the example embodiment ofFIG. 2, the system controller1410, the host controller1420, and the client controller1430may each include one or more registers for storing information.

In the example embodiment ofFIG. 2, the system controller1410may be configured to supply a system clock signal SCLK to components of the serial interface block1400in response to a clock signal CLK provided from a clock generator1460. The clock generator1460may be regulated by the system controller1410in operation, and may supply the clock signal CLK to the system controller1410in response to an oscillation signal OSC provided from an external device (e.g., a crystal oscillator. Methods of outputting the clock signal CLK, at the clock generator1460, with a given duty ratio from the oscillation signal OSC will be easily understood by one of ordinary skill in the art, and will not be described further for the sake of brevity.

In the example embodiment ofFIG. 2, the host controller1420may include a link layer module for processing signals to be transferred through the LVDS I/O unit1450. The host controller1420may convert data (e.g., scheduled to be transferred through the LVDS I/O unit1450) into packet data. The client controller1430may also include a link layer module for processing signals to be transferred through the LVDS I/O unit1450. The client controller1430may restore the packet data transferred through the LVDS I/O unit1450. The interface unit1440may provide an interface operation with the AP1200. In addition, the interface unit1440, although not shown in the example embodiment ofFIG. 2, may interface with a central processing unit (CPU), may perform an RGB mode, and/or may interface with a camera system. The LVDS I/O1450may include a physical layer module which may transform serial packet data (e.g., “parallel” data) of the host controller1420into serial packet data (e.g., “serial” data) and may transform serial packet data of the second sub-system2000into parallel packet data.

In the example embodiment ofFIG. 2, the serial interface block2200of the second sub-system2000may include a system controller2210, a host controller2220, a client controller2230, an interface unit2240, and a LVDS I/O unit2250. In an example, the system controller2210, the host controller2220, the client controller2230, and the interface unit2240may be configured so as to communicate with each other via bus2201. While not shown in the example embodiment ofFIG. 2, the system controller1410, the host controller1420, and the client controller1430may each include one or more registers for storing information.

In the example embodiment ofFIG. 2, the system controller2210may be configured to supply a system clock signal SCLK to components of the serial interface block2200in response to a clock signal CLK provided from a clock generator2260. The clock generator2260may be regulated by the system controller2210and may supply the clock signal CLK to the system controller2210in response to an oscillation signal OSC provided from an external device (e.g., the crystal oscillator supplying the oscillation signal to the first serial interface block1400). The host controller2220may include a link layer module for processing signals scheduled to be transferred through the LVDS I/O unit2250. The host controller2220may convert data, scheduled to be transferred through the LVDS I/O unit2250, into packet data. The client controller2230may also include a link layer module for processing signals scheduled to be transferred through the LVDS I/O unit2250. The client controller2230may restore the packet data transferred through the LVDS I/O unit2250. The interface unit2240may interface with the user interface block2400. In addition, the interface unit2240, although not shown in the example embodiment ofFIG. 2, may interface with a central processing unit (CPU), may perform an RGB mode, and/or may interface with a camera system. The LVDS I/O2250may include a physical layer module which may transform serial packet data (e.g., “parallel” data) of the host controller2220into serial packet data (e.g., “serial” data) and may transform serial packet data of the second sub-system1000into parallel packet data.

FIG. 3is a flow chart illustrating a process of establishing a power saving mode according to another example embodiment of the present invention.FIGS. 4A and 4Bare block diagrams illustrating flows of control operations between serial interface blocks1400and2200during the process ofFIG. 3according to other example embodiments of the present invention.

In the example embodiment ofFIG. 3, the AP1200of the first sub-system1000may determine whether to initiate a power saving mode (at S100). For example, the power saving mode may be triggered by an idle state (e.g., a given period where no user inputs have been received or no data is scheduled for processing). If the first sub-system1000does not determine to initiate the power saving mode, the process ofFIG. 3may not trigger the power saving mode.

In the example embodiment ofFIGS. 3 and 4A, if the first sub-system1000determines to initiate the power saving mode, the AP1200may store triggering information in the registers1411and2211of the system controllers1410and2210to trigger the power saving mode, respectively, via signal paths {circle around (1)} and {circle around (2)} shown in the example embodiment ofFIG. 4A(at S110). Here, the triggering information for the power saving mode may include information related to whether to enable or disable the clock generators1410and2210, as well as information related to whether to enable or disable detecting functions of the LVDS I/O units1450and2250.

In the example embodiment ofFIG. 2, the AP1200may disable external interface functions of the first and second serial interface blocks1400and2200(at S120). For example, the AP1200may disable functions for interfacing with external units, among the interface functions provided by the interface unit1440of the first serial interface block1400(e.g., an RGB interface, a camera interface, etc.). Also, the AP1200may disable functions for interfacing with external units, among the interface functions provided by the interface unit2240of the second serial interface block2200(e.g., an RGB interface, a camera interface, etc.). Further, an interface with the AP1200provided by the first serial interface block1400and a General Purpose Input/Output (GPIO) interface function provided by the second serial interface block2400may not be disabled.

In the example embodiment ofFIG. 2, a transmission channel from the second sub-system2000toward the first sub-system1000(hereinafter, referred to as ‘downlink channel’) may transition into a suspension state (at S130). For example, the AP1200may set a register2221(e.g., in the host controller2220of the second sub-system2000) to the suspension state via a signal path {circle around (3)} illustrated in the example embodiment ofFIG. 4A. As used herein, a suspension state may refer to a condition where a driver output may be set to a higher impedance (Hi-Z) by interrupting a driver function in a component thereof. Thus, in an example, an output of the host controller2220of the second serial interface block2200may be set to the higher impedance state. Thereafter, the client controller1430of the first serial interface block1400may detect whether the host controller2220of the second serial interface unit2200is set to the suspension state. The transition to the suspension state may be detected by checking whether, through input/output blocks, an output of the host controller2220is set to the higher impedance.

In the example embodiment ofFIG. 2, if the higher impedance at the host controller2220is detected, the client controller1430may establish a suspension state bit in the register1431to indicate that the downlink channel (e.g., the transmission channel from the second sub-system2000to the first sub-system1000) may be in the suspension state. The AP1200may evaluate the suspension state bit from the register1431of the client controller1430via a signal path {circle around (4)} as shown in the example embodiment ofFIG. 4A. If the suspension state bit indicates that the downlink channel is in the suspension state, the serial interface block2200of the second sub-system2000may be set into the power saving mode by control of the AP1200. Accordingly, the register2211of the system controller2210may be set into the power saving mode via a signal path {circle around (5)}, as shown in the example embodiment ofFIG. 5. If the register2211of the system controller2210transitions into the power saving mode, the system clock signal SCLK, which may be supplied to components of the serial interface block2200, may be interrupted or disabled in accordance with the power saving mode information stored in the register2211(at S140).

In another example embodiment of the present invention, referring toFIG. 2, a current condition of the downlink channel, whether or not the suspension state is set, may be sensed in a number of ways. For example, if the register2221of the host controller2220includes bit information indicating the suspension state, the host controller2210may provide the AP1200, through the interface unit2240(e.g., a GPIO interface function of the interface unit2240) with a flag signal that indicates that the downlink channel in the suspension state. Here, the AP1200may set the serial interface block2200of the second sub-system2000into the power saving mode in a manner similar as that described above.

In the example embodiment ofFIG. 2, the register2211may store information for disabling the clock generator2260, and the system controller2210may stop, or pause, generating the clock signal CLK in the power saving mode. Thus, there may be no generation of the system clock signal SCLK during the power saving mode. In contrast, if the register2211stores information for enabling the clock generator2260, the system controller2210may stop generating the system clock signal SCLK while the clock generator2260may still be active.

In the example embodiment ofFIG. 2, after the second serial interface block2200transitions to the power saving mode, a transmission channel from the first sub-system1000to the second sub-system2000(hereinafter, referred to as ‘uplink channel’) may transition into a suspension state by control of the AP1200(at S150). For example, the AP1200may set a register1421, which is included in the host controller1420of the second sub-system1000, into the suspension state via a signal path {circle around (6)} shown inFIG. 4B. As discussed above, the suspension state may refer to a condition where a driver output may transition to a higher impedance (Hi-Z) by interruption of a driver function in the component thereof. Thus, an output of the host controller1420of the second serial interface block1400may transition to the higher impedance state.

In the example embodiment ofFIG. 2, the host controller1420may set a suspension state bit in the register1421to indicate that the uplink channel (e.g., the transmission channel from the first sub-system1000to the second sub-system2000) may be in the suspension state. The AP1200may detect the suspension state bit from the register1421of the host controller1420via a signal path {circle around (7)} as shown in the example embodiment ofFIG. 4B. If the suspension state bit indicates that the uplink channel is in the suspension state, the first serial interface block1440may be transitioned into the power saving mode by control of the AP1200(at S160). Thus, the register1411of the system controller1410may transition into the power saving mode via a signal path {circle around (8)}. If the register1411of the system controller1410is transitioned into the power saving mode, the system clock signal SCLK, which may be supplied to components of the serial interface block1400, may be interrupted or paused, in compliance with the power saving mode information stored in the register1411. The interruption of the system clock signal SCLK may be performed in the same manner as discussed above, and as such will not be further described for the sake of brevity.

In the example embodiment ofFIG. 2, the serial interface blocks1400and2200may transition into the power saving mode so as to reduce standby power consumption of the sub-systems1000and2000, which may communicate with each other over a serial interface. However, under certain triggering conditions, the serial interface blocks1400and2200may have to be “released” from the power saving mode (e.g., to re-enter an “active” mode again). For example, it may be permissible to release the power saving mode of the serial interface blocks1400and2200through the first sub-system1000(e.g., in response to a triggering condition detected thereof). In another example, it may also be permissible to release the power saving mode of the serial interface blocks1400and2200through the second sub-system2000(e.g., in response to a triggering condition detected thereof). Below, example embodiments are directed generally to where the triggering condition is detected at the second sub-system2000. However, it will be appreciated that such a description is for example purposes only, and other example embodiments may trigger a release from the standby or power saving mode upon a triggering condition detected at the first sub-system1000.

FIG. 5is a flow chart illustrating a process of releasing the power saving mode according to another example embodiment of the present invention.

FIG. 6is a timing diagram illustrating signal state transitions for signals within the first and second serial interface blocks1400and2200during the process ofFIG. 5according to another example embodiment of the present invention.

FIG. 7is a block diagram illustrating signal flows within the first and second serial interface blocks1400and2200for the signals ofFIG. 6according to another example embodiment of the present invention.

The example process ofFIG. 5will now be described with reference toFIGS. 6 and 7.

In the example embodiment ofFIG. 5, if there is an “interrupt” (e.g., a condition for triggering a release from the power saving mode or standby mode) (at S200), the power saving mode of the first serial interface block1400may be released by enabling the system clock signal SCLK (at S210). Then, the uplink channel may be activated so as to output packet data via the activated uplink channel (at S220). If the packet data is transferred to the second serial interface block2200through the uplink channel, the power saving mode of the second serial interface block2200may be released by enabling the system clock signal SCLK (at S230). Then, the downlink channel may be activated and flag packet data may be output via the activated downlink channel (at S240). The AP1200may then be informed that the first and second serial interface blocks1400and2200have been released from the power saving mode (at S250) (e.g., via an evaluation of the suspension bits of the registered stored therein).

A more detailed description of the example process ofFIG. 5will now be given with respect toFIGS. 6 and 7.

In the example embodiment ofFIG. 5with reference toFIGS. 6 and 7, the interface unit1440of the first serial interface block1400may generate a control signal WAKEUP_BY_CPU in response to an interrupt information signal WAKEUP provided from the AP1200. The system controller1410may be released from the power saving mode if there is an input of the control signal WAKEUP_BY_CPU. Concurrently, the system controller1410may internally generate a clock enable signal CLK_EN to activate the system clock signal SCLK. The activation of the system clock signal SCLK may be performed in any of numerous ways. For example, if the clock generator1460becomes inactive in the power saving mode, the system controller1410may first inactivate the clock generator1460. The clock generator1460may output the clock signal CLK in response to an oscillation signal OSC provided from an external device and the system controller1410may generate the system clock signal SCLK in response to the clock signal CLK. Alternatively, if the clock generator1460is active in the power saving mode, the system controller1410may generate the system clock signal SCLK, based on the clock signal CLK provided from the clock generator1460, in response to an input of the control signal WAKEUP_BY_CPU.

In the example embodiment ofFIG. 5with reference toFIGS. 6 and 7, the system controller1410may generate a control signal LINK_WAKEUP. The suspension state of the host controller1420may be released by an activation of the control signal LINK_WAKEUP. For example, the host controller1420may activate the uplink channel in response to the activation of the control signal LINK_WAKEUP. The host controller1420may output a wakeup packet WAKEUP_PACKET through the activated uplink channel. The wakeup packet WAKEUP_PACKET may be serialized via the LVDS I/O unit1450.

In the example embodiment ofFIG. 5with reference toFIGS. 6 and 7, the LVDS I/O unit2250of the second serial interface block2200may generate a control signal WAKEUP_BY_LINK in response to the wakeup packet WAKEUP_PACKET transferred through the uplink channel. The system controller2210may be released from the power saving mode if there is an input of the control signal WAKEUP_BY_LINK. Concurrently, the system controller2210may internally generate a clock enable signal CLK_EN to activate the system clock signal SCLK. The activation of the system clock signal SCLK may be performed in any of numerous ways. For example, if the clock generator2260is inactive in the power saving mode, the system controller2210may first inactivate the clock generator2260. Thereby, the clock generator2260may output the clock signal CLK in response to the oscillation signal OSC provided from an external device and the system controller2210may generate the system clock signal SCLK in response to the clock signal CLK. Alternatively, if the clock generator2260is active in the power saving mode, the system controller2210may generate the system clock signal SCLK, based on the clock signal CLK provided from the clock generator2260, in response to an input of the control signal WAKEUP_BY_LINK.

In the example embodiment ofFIG. 5with reference toFIGS. 6 and 7, after enabling the system clock signal SCLK, the system controller2210may output a control signal LINK_WAKEUP to the host controller2220. The suspension state of the host controller2220may be released by the control signal LINK_WAKEUP, which may thereby activate the downlink channel. The host controller2220may output flag packet FLAG_PACKET through the activated downlink channel. The flag packet FLAG_PACKET may be serialized via the LVDS I/O unit2250. The flag packet FLAG_PACKET may be transferred to the interface unit1440via the LVDS I/O unit1450and the client controller1430of the first serial interface block1400. The interface unit1440may cause an “interrupt” in response to the flag packet FLAG_PACKET. The interface unit1440may indicate or inform, to the AP1200, that the first and second serial interface blocks1400and2200have each been released from the power saving mode. Then, the AP1200may enable the interface functions of the first and second serial interface blocks1400/2200which were previously disabled in the power saving mode.

FIG. 8is a flow chart illustrating another process of releasing the power saving mode according to another example embodiment of the present invention.

FIG. 9is a timing diagram illustrating signal state transitions for signals within the first and second serial interface blocks1400and2200during the process ofFIG. 8according to another example embodiment of the present invention.

FIG. 10is a block diagram illustrating signal flows within the first and second serial interface blocks1400and2200for the signals ofFIG. 9according to another example embodiment of the present invention.

The example process ofFIG. 8will now be described with reference toFIGS. 6 and 7.

In the example embodiment ofFIG. 10, if there is an “interrupt from an external interrupt source (at S300), the power saving mode of the second serial interface block2200may be released so as to enable the system clock signal SCLK (at S310). A downlink channel may then be activated so as to output packet data via the activated downlink channel (at S320). If the packet data is transferred to the first serial interface block1400through the downlink channel, the power saving mode of the first serial interface block1400may be released so as to enable the system clock signal SCLK (at S330). Then, an uplink channel may be activated (at S340) and the AP1200may be informed that the first and second serial interface blocks1400and2200have been released from the power saving mode (at S350) (e.g., based on the suspension state bit).

A more detailed description of the example process ofFIG. 8will now be given with respect toFIGS. 9 and 10.

In the example embodiment ofFIG. 8, with reference toFIGS. 9 and 10, the interface unit2240(e.g., a GPIO interface) of the second serial interface block2200may generate a control signal WAKEUP_BY_GPIO in response to an interrupt information signal provided from an external interrupt source. The system controller2210may be released from the power saving mode if there is an input of the control signal WAKEUP_BY_GPIO. Concurrently, the system controller2210may internally generate a clock enable signal CLK_EN to activate the system clock signal SCLK. The activation of the system clock signal SCLK may be performed in any of numerous ways. For example, if the clock generator1460is inactive in the power saving mode, the system controller2210may first inactivate the clock generator2260. Thereby, the clock generator2260may output the clock signal CLK in response to the oscillation signal OSC provided from an external device and the system controller2210may generate the system clock signal SCLK in response to the clock signal CLK. Alternatively, if the clock generator2260is active in the power saving mode, the system controller2210may generate the system clock signal SCLK, based on the clock signal CLK provided from the clock generator2260, in response to an input of the control signal WAKEUP_BY_GPIO.

In the example embodiment ofFIG. 8, with reference toFIGS. 9 and 10, the system controller2210may generate a control signal LINK_WAKEUP. The suspension state of the host controller2220may be released in accordance with the control signal LINK_WAKEUP. The host controller2220may activate the downlink channel in response to the activation of the control signal LINK_WAKEUP. The host controller2220may output a wakeup packet WAKEUP_PACKET through the activated downlink channel. The wakeup packet WAKEUP_PACKET may be serialized via the LVDS I/O unit2250.

In the example embodiment ofFIG. 8, with reference toFIGS. 9 and 10, the LVDS I/O unit1450of the first serial interface block1400may generate a control signal WAKEUP_BY_LINK in response to the wakeup packet WAKEUP_PACKET transferred through the downlink channel. The system controller1410may be released from the power saving mode if there is an input of the control signal WAKEUP_BY_LINK. Concurrently, the system controller1410may internally generate a clock enable signal CLK_EN to activate the system clock signal SCLK. The activation of the system clock signal SCLK may be performed in any of numerous ways. For example, if the clock generator1460is inactive in the power saving mode, the system controller1410may first inactivate the clock generator1460. The clock generator1460may output the clock signal CLK in response to the oscillation signal OSC provided from an external device and the system controller1410may generate the system clock signal SCLK in response to the clock signal CLK. Alternatively, if the clock generator1460is active in the power saving mode, the system controller1410may generate the system clock signal SCLK, based on the clock signal CLK provided from the clock generator1460, in response to an input of the control signal WAKEUP_BY_LINK.

In the example embodiment ofFIG. 8, with reference toFIGS. 9 and 10, after enabling the system clock signal SCLK, the system controller1410may output a control signal LINK_WAKEUP to the host controller1420. The suspension state of the host controller1420may be released by the control signal LINK_WAKEUP, thereby activating the uplink channel. Concurrently, the host controller1420may generate a control signal SYSTEM_WAKEUP, and the interface unit1440may interrupt (e.g., reactivate) in response to the control signal SYSTEM_WAKEUP. The interface unit1440may indicate, to the AP1200, that the first and second serial interface blocks1400and2200have each been released from the power saving mode.

In another example embodiment of the present invention, the components of each of the first and second sub-systems1000/2000may be formed in independent chips, respectively, or may alternatively be integrated within a single chip. If a device including the first and second sub-systems1000/2000is a mobile communication device, the device may include a divided structure with top and bottom parts (e.g., the first and second sub-systems, respectively), and as such may be embodied as a folder-type mobile phone or a slide-type mobile phone.

Example embodiments of the present invention being thus described, it will be obvious that the same may be varied in many ways. For example, while above described example embodiments are directed generally to a system employing LVDS protocols, it will be readily appreciated that the above described example embodiments of the present invention may be easily adapted for use in systems employing other signaling protocols.

Such variations are not to be regarded as a departure from the spirit and scope of example embodiments of the present invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.