Semiconductor package, method of evaluating same, and method of manufacturing same

A semiconductor package includes a wiring board, a semiconductor device mounted on the wiring board, an electrically-conductive thermal interface material provided on the semiconductor device, a test electrode in contact with a first surface of the thermal interface material to be electrically connected to the thermal interface material, and an electrically-conductive heat spreader in contact with a second surface of the thermal interface material opposite to its first surface.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2009-252170, filed on Nov. 2, 2009, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a semiconductor package having a thermal interface material (TIM), a method of evaluating the semiconductor package, and a method of manufacturing the semiconductor package.

BACKGROUND

A semiconductor device used as a central processing unit (CPU) or the like is electrically connected to and fixed on a board in a semiconductor package. The temperature of the semiconductor device becomes high at the time of its operation. Therefore, the semiconductor device may be damaged unless its temperature is forcibly reduced. Accordingly, a heat spreader or a radiator fin (or a heat pipe) is attached on the semiconductor device to ensure a path for effectively radiating heat generated by the semiconductor device to its outside. Attempts have been made at smooth heat conduction by interposing a thermal interface material (TIM) between the semiconductor device and the heat spreader or the like so that the thermal interface material follows their respective uneven surfaces to reduce thermal contact resistance.

FIG. 1is a cross-sectional view of a conventional semiconductor package including a thermal interface material. In the semiconductor package, heat generated by a semiconductor device200mounted on a board100is transferred to a heat spreader400via a thermal interface material300aprovided on the semiconductor device200. Further, the heat transferred to the heat spreader400is transferred to a radiator fin500via a thermal interface material300bprovided on the heat spreader400.

Thus, the thermal interface materials300aand300bare used as means for thermally connecting the semiconductor device200and the heat spreader400and thermally connecting the heat spreader400and the radiator fin500.

Reference may be made to Japanese Laid-Open Patent Application No. 57-039364 for related art.

SUMMARY

According to an aspect of the invention, a semiconductor package includes a wiring board; a semiconductor device mounted on the wiring board; an electrically-conductive thermal interface material provided on the semiconductor device; a test electrode in contact with a first surface of the thermal interface material to be electrically connected to the thermal interface material; and an electrically-conductive heat spreader in contact with a second surface of the thermal interface material opposite to the first surface thereof.

According to an aspect of the invention, a method of evaluating a semiconductor package includes measuring an electrical resistance of a part of the semiconductor package from a heat spreader through a test electrode via a thermal interface material provided on the semiconductor device, the test electrode being in contact with a first surface of the thermal interface material to be electrically connected to the thermal interface material, the heat spreader being in contact with a second surface of the thermal interface material opposite to the first surface thereof; and evaluating a magnitude of a thermal contact resistance between the thermal interface material and each of the heat spreader and the semiconductor device based on a measurement of the electrical resistance.

According to an aspect of the invention, a method of manufacturing a semiconductor package includes mounting a semiconductor device on a wiring board; providing an electrically-conductive thermal interface material on the semiconductor device; providing a test electrode in contact with a first surface of the thermal interface material so that the test electrode is electrically connected to the thermal interface material; providing an electrically-conductive heat spreader in contact with a second surface of the thermal interface material opposite to the first surface thereof; and evaluating a magnitude of a thermal contact resistance between the thermal interface material and each of the heat spreader and the semiconductor device by the method of evaluating a semiconductor package as set forth above.

DESCRIPTION OF EMBODIMENTS

The thermal contact resistance between a thermal interface material and a semiconductor device or a heat spreader is a factor that determines the performance of the thermal interface material, and it is preferable that the contact thermal resistance be as low as possible. Conventionally, in evaluating the performance of the thermal interface material, thermal resistance is measured that includes the thermal interface material as well as the semiconductor device and the heat spreader, one on each side of the thermal interface material. For example, the semiconductor device is electrically loaded to generate heat, and the internal temperature of the semiconductor device and the surface temperature of the heat spreader are measured. Then, thermal resistance is calculated from a difference between the measured internal temperature of the semiconductor device and the measured surface temperature of the heat spreader.

However, there is a problem in that measurement of thermal contact resistance requires a complicated evaluation system and takes a lot of evaluation time.

According to one aspect of the present invention, a semiconductor package is provided that allows the performance of its thermal interface material to be evaluated in a simple manner, and a method of evaluating the semiconductor package and a method of manufacturing the semiconductor package are provided.

A description is given, with reference to the accompanying drawings, of embodiments of the present invention.

[a] First Embodiment

A description is given of a semiconductor package structure according to a first embodiment.

FIG. 2is a cross-sectional view of a semiconductor package according to the first embodiment. Referring toFIG. 2, a semiconductor package10according to the first embodiment includes a semiconductor device20, a multilayer wiring (interconnection) board30, multiple solder bumps40, underfill resin50, a thermal interface material (TIM)60, and a heat spreader70.

The semiconductor device20is substantially centered on the multilayer wiring board30via the bumps40, and is sealed with the underfill resin50. Further, the semiconductor device20is connected to the heat spreader70via the thermal interface material60.

A description is given below of the semiconductor device20, the multilayer wiring board30, the solder bumps40, the underfill resin50, the thermal interface material60, and the heat spreader70.

The semiconductor device20includes a semiconductor substrate21, multiple electrode pads22, and a through electrode23. The semiconductor substrate21is, for example, a silicon (Si) or germanium (Ge) substrate, in which a semiconductor integrated circuit (not graphically illustrated) is formed. The electrode pads22are formed on one side of the semiconductor substrate21to be electrically connected to the semiconductor integrated circuit. Examples of the material of the electrode pads22include aluminum (Al); copper (Cu) and aluminum stacked in layers in this order; and copper, aluminum, and silicon stacked in layers in this order.

Hereinafter, in the semiconductor device20, a surface on the side on which the electrode pads22are formed may be referred to as a “principal surface,” a surface on the side opposite to the principal surface and substantially parallel to the principal surface may be referred to as a “bottom surface,” and a surface substantially perpendicular to the principal surface and the bottom surface may be referred to as a “side surface.”

The through electrode23is formed through the semiconductor substrate21from the principal surface side to the bottom surface side. A first end of the through electrode23is electrically connected to a corresponding one of the electrode pads22. A second end of the through electrode23is exposed at the bottom surface of the semiconductor substrate21(a bottom surface20aof the semiconductor device20) to be in contact with a first surface60aof the thermal interface material60on the semiconductor device20side. For example, the through electrode23is circular in a plan view (taken from the principal surface side or the bottom surface side of the semiconductor substrate21), and may be, for example, 100 μm in diameter. Examples of the material of the through electrode23include copper.

The multilayer wiring board30includes a first interconnection layer31, a first insulating layer32, a second interconnection layer33, a second insulating layer34, and a third interconnection layer35, which are successively stacked. The multilayer wiring board30further includes solder resist layers36so formed as to cover the first interconnection layer31and the third interconnection layer35.

The solder resist layers36are formed on the first insulating layer32and the second insulating layer34so as to cover the first interconnection layer31and the third interconnection layer35. The solder resist layers36have openings36xso that the first interconnection layer31and the third interconnection layer35are partly exposed in the openings36xof the solder resist layers36. Examples of the material of the solder resist layers36include photosensitive resin compositions containing epoxy resin, imide resin, etc. The solder resist layers36may each be, for example, approximately 30 μm in thickness.

A metal layer or the like may be formed on the first interconnection layer31and the third interconnection layer35in the openings36x, where the first interconnection layer31and the third interconnection layer35are exposed, as required.

Examples of the metal layer include an Au layer, a Ni/Au layer (a metal layer formed of a Ni layer and a Au layer stacked in this order), a Ni/Pd/Au layer (a metal layer of a Ni layer, a Pd layer, and a Au layer stacked in this order).

Examples of the material of the first interconnection layer31include copper. The first interconnection layer31may be, for example, approximately 10 μm in thickness. A left end portion of the first interconnection layer31inFIG. 2is referred to as a “test pad39” for convenience of description. Portions of the first interconnection layer31which are not covered with the first insulating layer32and exposed serve as electrode pads to be connected to a motherboard or the like.

In the semiconductor package10, the part of the through electrode23through the test pad39via the corresponding electrode pad22, the corresponding solder bump40, the third interconnection layer35, and the second interconnection layer33is a typical example of the test electrode according to this embodiment. Hereinafter, the above-described part of the through electrode23through the test pad39may be referred to as “test electrode.”

The first insulating layer32is so formed as to cover the first interconnection layer31. Examples of the material of the first insulating layer32include epoxy resin and polyimide resin. The first insulating layer32may be, for example, approximately 30 μm in thickness.

The second interconnection layer33is formed on the first insulating layer32. The second interconnection layer33includes via-filling portions filling in first via holes32xpenetrating through the first insulating layer32to expose the upper surface of the first interconnection layer31, and an interconnection pattern formed on the first insulating layer32. The second interconnection layer33is electrically connected to the first interconnection layer31at the first via holes32x, where the first interconnection layer31is exposed. Examples of the material of the second interconnection layer33include copper. The interconnection pattern forming the second interconnection layer33may be, for example, approximately 10 μm in thickness.

The second insulating layer34is so formed on the first insulating layer32as to cover the second interconnection layer33. Examples of the material of the second insulating layer34include epoxy resin and polyimide resin. The second insulating layer34may be, for example, approximately 30 μm in thickness.

The third interconnection layer35is formed on the second insulating layer34. The third interconnection layer35includes via-filling portions filling in second via holes34xpenetrating through the second insulating layer34to expose the upper surface of the second interconnection layer33, and an interconnection pattern formed on the second insulating layer34. The third interconnection layer35is electrically connected to the second interconnection layer33at the second via holes34x, where the second interconnection layer33is exposed. Examples of the material of the third interconnection layer35include copper. The interconnection pattern forming the third interconnection layer35may be, for example, approximately 10 μm in thickness.

In the multilayer wiring board30, the test pad39is electrically connected to the through electrode23via the second interconnection layer33, the third interconnection layer35, the corresponding solder bump40, and the corresponding electrode pad22. This structure may be a feature according to the semiconductor package10of this embodiment. A function of this structure is described in detail below in “Method of Evaluating Performance of Thermal Interface Material in Semiconductor Package according to First Embodiment.”

The solder bumps40electrically connect the third interconnection layer35(or the metal layer if the metal layer is formed on the third interconnection layer35), exposed in the openings36xof the (upper) solder resist layer36of the multilayer wiring board30, to the electrode pads22of the semiconductor device20. Examples of the material of the solder bumps40include alloys including lead (Pb), alloys of tin (Sn) and Cu, alloys of Sn and silver (Ag), and alloys of Sn, Ag, and Cu.

The underfill resin50fills in the space between the opposed surfaces of the semiconductor device20and the multilayer wiring board30. Examples of the material of the underfill resin50include epoxy resin and polyimide resin.

The thermal interface material60is provided on the bottom surface20aof the semiconductor device20. The thermal interface material60serves to thermally connect the semiconductor device20and the heat spreader70. Examples of the material of the thermal interface material60include indium (In), which is a highly electrically conductive material having good thermal conductivity, silicone grease containing a highly electrically conductive material, and an organic resin binder containing metal filler or graphite. Further, the thermal interface material60may also be sheet-shaped molded resin containing carbon nanotubes, which are a highly electrically conductive material, arranged in a heat conduction direction. Since the thermal interface material60forms part of a path through which electric current flows as described below, the material of the thermal interface material60includes a highly electrically conductive material and serves as a conductor. The thermal interface material60may be, for example, approximately 10 μm to approximately 200 μm in thickness.

The heat spreader70is provided on the thermal interface material60(in contact with a second surface60bof the thermal interface material60). The heat spreader70may be, for example, a radiator plate. A material having high thermal conductivity, such as nickel-plated oxygen-free copper or aluminum, may be used for the heat spreader70. Since the heat spreader70forms part of a path through which electric current flows as described below, the material of the heat spreader70serves as a conductor. The heat spreader70serves to disperse the density of the heat generated by the semiconductor device20. Further, since the heat spreader70is provided over the semiconductor device20, the heat spreader70serves to mechanically protect the semiconductor device20. The heat spreader70may be approximately 10 mm square to approximately 40 mm square in size in a plan view. The heat spreader70may be, for example, approximately 1 mm to approximately 3 mm in thickness.

The semiconductor package10according to the first embodiment has a structure as described above. In the semiconductor package10, however, a radiator fin may be further provided over the heat spreader70with a thermal interface material interposed between the heat spreader70and the radiator fin. Further, a resin layer may be provided between the peripheral portion of the heat spreader70and the multilayer wiring board30.

[Method of Evaluating Performance of Thermal Interface Material in Semiconductor Package according to First Embodiment]

Next, a description is given of a method of evaluating the performance of a thermal interface material in a semiconductor package according to the first embodiment.

FIG. 3is a diagram for illustrating a method of evaluating the performance of a thermal interface material in a semiconductor package according to the first embodiment. InFIG. 3, the same elements as those ofFIG. 2are referred to by the same reference numerals, and a description thereof may be omitted.

As illustrated inFIG. 3, a lead91is connected to the plus side of a direct-current (DC) power supply90and the heat spreader70, and a lead92is connected to the minus side of the DC power supply90and the test pad39. The plus side of the DC power supply90and the heat spreader70may be connected using a pin or by soldering, for example. The minus side of the DC power supply90and the test pad39may be connected using a pin or by soldering, for example. It may be arbitrarily determined which of the plus side and the minus side of the DC power supply90is connected to the test pad39or the heat spreader70.

FIG. 4is another diagram for illustrating the method of evaluating the performance of a thermal interface material in a semiconductor package according to the first embodiment. InFIG. 4, the same elements as those ofFIG. 2are referred to by the same reference numerals, and a description thereof may be omitted.

InFIG. 4, an arrow93indicates a path in which electric current flows. As described above, since the heat spreader70is a conductor, electric current flows through the heat spreader70. Further, since the thermal interface material60is made of indium or contains a highly electrically conductive material such as metal filler, graphite, or carbon nanotubes, the thermal interface material60serves as a conductor to allow electric current to flow through the thermal interface material60.

That is, inFIG. 4, electric current flows through the path indicated by the arrow93(the plus side of the DC power supply90to the lead91to the heat spreader70to the thermal interface material60to the through electrode23to the corresponding electrode pad22to the corresponding solder bump40to the third interconnection layer35to the second interconnection layer33to the test pad39to the lead92to the minus side of the DC power supply90). The path indicated by the arrow93is electrically isolated from the semiconductor integrated circuit (not graphically illustrated) of the semiconductor device20.

By providing an ammeter (not graphically illustrated) for monitoring electric current flowing through the path indicated by the arrow93and a voltmeter (not graphically illustrated) for monitoring the voltage applied across (the part of) the heat spreader70through the test pad39in the path indicated by the arrow93, it is possible to measure the electrical resistance of (the part of) the heat spreader70through the test pad39in the path indicated by the arrow93.

In the path indicated by the arrow93, the electrical resistance is substantially constant through the part of the through electrode23, the corresponding electrode pad22, the corresponding solder bump40, the third interconnection layer35, the second interconnection layer33, and the test pad39. However, the electrical resistance of the part of the thermal interface material60(where the thermal interface material60is in contact with the heat spreader70and the semiconductor device20) varies greatly depending on the state of contact of the highly electrically conductive material contained in the thermal interface material60and the heat spreader70and the state of contact of the highly electrically conductive material contained in the thermal interface material60and the through electrode23. A description is given of this with reference toFIGS. 5A and 5BandFIGS. 6A and 6B.

FIGS. 5A and 5Bare enlarged views of a circled portion A inFIG. 3, illustrating states of the circled portion A in the case where the thermal interface material60is silicone grease containing metal filler or the like as a highly electrically conductive material61or the thermal interface material60is organic resin containing metal filler or graphite as the highly electrically conductive material61. InFIGS. 5A and 5B, the same elements as those ofFIG. 3are referred to by the same reference numerals, and a description thereof may be omitted.

FIG. 5Aillustrates a case where the highly electrically conductive material61is not in sufficient contact with the surface of the through electrode23or the surface of the heat spreader70. In this case, the electrical resistance of the part of the thermal interface material60is high. On the other hand,FIG. 5Billustrates a case where the highly electrically conductive material61is in sufficient contact with the surface of the through electrode23and the surface of the heat spreader70. In this case, the electrical resistance of the part of the thermal interface material60is low.

FIGS. 6A and 6Bare enlarged views of the circled portion A inFIG. 3, illustrating states of the circled portion A in the case where the thermal interface material60is organic resin containing carbon nanotubes62as a highly electrically conductive material. InFIGS. 6A and 6B, the same elements as those ofFIG. 3are referred to by the same reference numerals, and a description thereof may be omitted.

FIG. 6Aillustrates a case where the carbon nanotubes are not in sufficient contact with the surface of the through electrode23or the surface of the heat spreader70. In this case, the electrical resistance of the part of the thermal interface material60is high. On the other hand,FIG. 6Billustrates a case where the carbon nanotubes62are in sufficient contact with the surface of the through electrode23and the surface of the heat spreader70. In this case, the electrical resistance of the part of the thermal interface material60is low.

Thus, the electrical resistance of the part of the thermal interface material60differs greatly depending on the state of contact of the highly electrically conductive material contained in the thermal interface material60and the heat spreader70and the state of contact of the highly electrically conductive material contained in the thermal interface material60and the through electrode23. Further, if the highly electrically conductive material is not in sufficient contact with the surface of the through electrode23or the surface of the heat spreader70as illustrated inFIG. 5AorFIG. 6A, heat is less likely to be transferred from the semiconductor device20to the heat spreader70via the thermal interface material60, so that the thermal contact resistance increases. On the other hand, if the highly electrically conductive material is in sufficient contact with the surface of the through electrode23and the surface of the heat spreader70as illustrated inFIG. 5BorFIG. 6B, heat is likely to be transferred from the semiconductor device20to the heat spreader70via the thermal interface material60, so that the thermal contact resistance decreases.

That is, there is a correspondence between the electrical resistance of the part of the thermal interface material60and the thermal contact resistance of the part of the thermal interface material60. Accordingly, if the correspondence between the electrical resistance of the part of the thermal interface material60and the thermal contact resistance of the part of the thermal interface material60is predetermined or found in advance, it is possible to determine the thermal contact resistance of the part of the thermal interface material60by measuring the electrical resistance of the part of the thermal interface material60in the individually manufactured semiconductor package10.

In practice, the thermal contact resistance of the part of the thermal interface material60is easily determined by predetermining the correspondence between the electrical resistance of the heat spreader70through the test pad39in the path indicated by the arrow93inFIG. 4and the thermal contact resistance of the part of the thermal interface material60and measuring the electrical resistance of the heat spreader70through the test pad39in the path indicated by the arrow93in the individually manufactured semiconductor package10.

If it is preknown that the highly electrically conductive material is in sufficient contact with the surface of the through electrode23and the surface of the heat spreader70as inFIG. 5BorFIG. 6B, it is possible to determine the presence or absence of the delamination of the thermal interface material60from the semiconductor device20and/or the heat spreader70by the method of evaluating the performance of the thermal interface material60in the semiconductor package10according to the first embodiment.

[Method of Manufacturing Semiconductor Package according to First Embodiment]

Next, a description is given of a method of manufacturing a semiconductor package according to the first embodiment.

FIGS. 7A through 7Eare diagrams illustrating processes for manufacturing a semiconductor package according to the first embodiment. InFIGS. 7A through 7E, the same elements as those ofFIG. 2are referred to by the same reference numerals, and a description thereof may be omitted.

First, in the process illustrated inFIG. 7A, the multilayer wiring board30manufactured by a known build-up process is prepared. The details of the multilayer wiring board30are as described above. Pre-solder41is formed on the third interconnection layer35(on a metal layer if the metal layer is formed on the third interconnection layer35) in the openings36x, where the third interconnection layer35is exposed, of the (upper) solder resist layer36of the multilayer wiring board30. Examples of the material of the pre-solder41include alloys containing Pb, alloys of Sn and Cu, alloys of Sn and Ag, and alloys of Sn, Ag, and Cu. The pre-solder41may be formed by being provided on the third interconnection layer35(on a metal layer if the metal layer is formed on the third interconnection layer35) on which flux has been applied as a surface treatment agent and then subjected to reflowing at temperatures of approximately 240° C. to approximately 260° C.; and thereafter having its surface washed to have the flux removed.

Next, in the process illustrated inFIG. 7B, a semiconductor device20A having a semiconductor integrated circuit (not graphically illustrated) and the electrode pads22formed on the semiconductor substrate21is prepared by a known method. Then, a through hole29is formed in the semiconductor substrate21of the semiconductor device20A so as to expose a surface of a corresponding one of the electrode pads22on one side. The through hole29may be circular in a plan view (taken from the principal surface side or the bottom surface side of the semiconductor substrate21), and may be, for example, 100 μm in diameter. The through hole29may be formed by an anisotropic etching process such as deep reactive ion etching (DRIE). With the formation of the below-described through electrode23, the semiconductor device20A ultimately becomes the semiconductor device20.

Next, in the process illustrated inFIG. 7C, the through electrode23is formed. For example, first, an insulating film (not graphically illustrated) is formed to cover the inner wall surface of the through hole29. For example, if the semiconductor substrate21is silicon, the insulating film may be formed by subjecting the semiconductor substrate21to thermal oxidation. The insulating film may be, for example, approximately 0.5 μm to approximately 1.0 μm in thickness. Next, the through electrode23is formed by filling the through hole29covered with the insulating film with metal. The filling with the metal may be performed by, for example, electroless plating or electroplating. Examples of the material of the filling metal include copper. By this process, the through electrode23is formed in the semiconductor device20A, so that the semiconductor device20is completed.

Next, in the process illustrated inFIG. 7D, pre-solder42is formed on the electrode pads22. Then, the third interconnection layer35side of the multilayer wiring board30and the electrode pads22side of the semiconductor device20are opposed to each other so that the pre-solder41and the pre-solder42are placed at respective positions corresponding to each other. Examples of the material of the pre-solder42include alloys containing Pb, alloys of Sn and Cu, alloys of Sn and Ag, and alloys of Sn, Ag, and Cu. The pre-solder42may be formed by being provided on the electrode pads22on which flux has been applied as a surface treatment agent and then subjected to reflowing at temperatures of approximately 240° C. to approximately 260° C.; and thereafter having its surface washed to have the flux removed.

Next, in the process illustrated inFIG. 7E, the pre-solder41and the pre-solder42are heated to, for example, 230° C. to melt solder, thereby forming the solder bumps40. Then, the space between the opposed surfaces of the semiconductor device20and the multilayer wiring board30is filled with the underfill resin50. Examples of the material of the underfill resin50include epoxy resin and polyimide resin.

Next, the thermal interface material60is provided on the bottom surface20aof the semiconductor device20, and the heat spreader70is provided on the thermal interface material60. Then, the heat spreader70is pressed toward the semiconductor device20, so that the semiconductor package10illustrated inFIG. 2is completed. Examples of the material of the thermal interface material60include indium, which has good thermal conductivity, silicone grease containing metal filler or the like, and an organic resin binder containing metal filler, graphite, etc. Further, the thermal interface material60may also be sheet-shaped molded resin containing carbon nanotubes arranged in a heat conduction direction. The thermal interface material60may be, for example, approximately 10 μm to approximately 200 μm in thickness. An electrically conductive material having high thermal conductivity, such as nickel-plated oxygen-free copper or aluminum, may be used for the heat spreader70.

Then, the performance of the thermal interface material60in the semiconductor package10is evaluated. The method of evaluating performance is as described above. The performance evaluation may be performed as one of the processes of a performance test for semiconductor packages such as an open/short test that is normally performed. The performance evaluation may also be performed as an independent process. This makes it possible to ship the individual semiconductor package10after checking the performance of the thermal interface material60, so that it is possible to improve the quality of the semiconductor package10at the time of shipment. If it is preknown that the highly electrically conductive material is in sufficient contact with the surface of the through electrode23and the surface of the heat spreader70as inFIG. 53orFIG. 6B, it is possible to determine whether there is delamination of the thermal interface material60from the semiconductor device20and/or the heat spreader70by this process.

Thus, in a semiconductor package according to the first embodiment, a test electrode is provided that includes a through electrode penetrating through a semiconductor device and having a first end in contact with a first surface of a thermal interface material on the semiconductor device side; and an interconnection layer of a wiring board, the interconnection layer being electrically connected to the through electrode. This makes it possible to measure the electrical resistance of the part of a heat spreader through the test electrode via the thermal interface material and to evaluate (determine) the magnitude of the thermal contact resistance between the thermal interface material and each of the heat spreader and the semiconductor device based on the measurement of the electrical resistance.

That is, in evaluating the performance of the thermal interface material, there is no need to measure the internal temperature of the semiconductor device and the surface temperature of the heat spreader by causing the semiconductor device to be electrically loaded and generate heat, and to calculate thermal resistance from a difference between the measured internal temperature of the semiconductor device and the measured surface temperature of the heat spreader, as is conventionally performed. As a result, it is possible to avoid a conventional problem in that measurement of thermal resistance requires a complicated evaluation system and takes a lot of evaluation time, so that it is possible to evaluate the performance of the thermal interface material (the thermal contact resistance of the part of the thermal interface material) in a simple manner, and to reduce evaluation time.

Further, by introducing the method of evaluating the performance of a thermal interface material in a semiconductor package according to the first embodiment into a semiconductor package manufacturing process, it is possible to ship semiconductor packages after checking the performance of thermal interface materials in the individual semiconductor packages, so that it is possible to improve the quality of the semiconductor packages at the time of their shipment.

Next, a description is given of a variation according to the first embodiment.

In the variation of the first embodiment, a case is illustrated where a thermal interface material is divided into multiple regions, and the respective regions are provided with corresponding test electrodes.

FIG. 8is a plan view of a semiconductor package according to the variation of the first embodiment.FIG. 9is a cross-sectional view of the semiconductor package according to the variation of the first embodiment. InFIG. 8, the graphical representation of the heat spreader7illustrated inFIG. 9is omitted.

Referring toFIG. 8andFIG. 9, a semiconductor package11according to the variation of the first embodiment is different from the semiconductor package10according to this embodiment in that the thermal interface material60is divided into 16 regions60cas indicated by broken lines and that the 16 divided regions60care provided with corresponding test electrodes (the through electrodes23and the corresponding test pads39), respectively, but otherwise has the same configuration as the semiconductor package10. Of the semiconductor package11, the same elements as those of the semiconductor package10are referred to by the same reference numerals, and a description thereof is omitted.

The method of manufacturing the semiconductor package11is the same as the method of manufacturing the semiconductor package10, and accordingly, a description thereof is omitted.

The method of evaluating the performance of a thermal interface material in the semiconductor package11is substantially the same as that in the semiconductor package10. The difference lies in that the performance of the thermal interface material is evaluated on a region-by-region basis by connecting the leads91and92to the heat spreader70and the test pad39(connected to the through electrode23connected to the thermal interface material60), respectively, in each of the regions60csubjected to the evaluation one after another.

Thus, according to the variation of the first embodiment, the same effects as in the first embodiment are produced. Further, according to the variation of the first embodiment, the following effects are additionally produced. That is, by dividing a thermal interface material into multiple regions and providing test electrodes corresponding to the respective regions, it is possible to measure the electrical resistances of multiple paths corresponding to the multiple regions. As a result, it is possible to determine the thermal contact resistance of the part of the thermal interface material region by region. That is, it is possible to understand the state of the thermal contact of the thermal interface material and each of the semiconductor device and the heat spreader on a region-by-region basis.

In the variation of the first embodiment, the thermal interface material60is divided into the 16 regions60c, and the 16 regions60care provided with corresponding test electrodes, respectively. Alternatively, it is also possible to divide the thermal interface material60into more than or less than 16 regions and provide the regions with respective test electrodes.

[b] Second Embodiment

A description is given of a second embodiment.

In the second embodiment, a case is illustrated where the through electrode23of the first embodiment is replaced with external electrodes80.FIG. 10is a plan view of a semiconductor package according to the second embodiment.FIG. 11is a cross-sectional view of the semiconductor package according to the second embodiment. InFIG. 10, the graphical representation of the heat spreader70illustrated inFIG. 11is omitted.

Referring toFIG. 10andFIG. 11, in a semiconductor package12according to the second embodiment, the semiconductor device20of the first embodiment is replaced with a semiconductor device20A. That is, the semiconductor package12does not include the through electrode23.

Further, according to the semiconductor package12, the thermal interface material60is divided into four regions60das indicated by broken lines inFIG. 10, and the external electrodes80are provided on a bottom surface20Aa of the semiconductor device20A so as to correspond to the four divided regions60d. Each of the external electrodes80is a metal layer that extends from the bottom surface20Aa of the semiconductor device20A over a side surface of the semiconductor device20A, the underfill resin50, and the solder resist layer36. Each of the external electrodes80has an end portion80aelectrically connected to the third interconnection layer35(or a metal layer if the metal layer is formed on the third interconnection layer35) in a corresponding one of the openings36x, where the third interconnection layer35is exposed, of the (upper) solder resist layer36of the multilayer wiring board30. Examples of the material of the external electrodes80include copper. The external electrodes80may be formed by, for example, electroless plating, electroplating, or vapor deposition. In the semiconductor package12, the part of each external electrode23through the corresponding test pad39via the third interconnection layer35and the second interconnection layer33is a typical example of the test electrode according to this embodiment. Hereinafter, the above-described part of the external electrode80through the corresponding test pad39may be referred to as “test electrode.”

The thermal interface material60is provided on the external electrodes80. In the semiconductor package12, the same elements as those of the semiconductor package10of the first embodiment are referred to by the same reference numerals, and a description thereof is omitted.

The method of manufacturing the semiconductor package12is substantially the same as the method of manufacturing the semiconductor package10, but additionally includes the process of forming the external electrodes80on the bottom surface20Aa of the semiconductor device20A by, for example, electroless plating, electroplating, or vapor deposition.

The method of evaluating the performance of a thermal interface material in the semiconductor package12is substantially the same as that in the semiconductor package10. The difference lies in that the performance of the thermal interface material is evaluated on a region-by-region basis by connecting the leads91and92to the heat spreader70and the test pad39(connected to the external electrode80), respectively, as illustrated inFIG. 12in each of the regions60dsubjected to the evaluation one after another.

Thus, according to the second embodiment, the same effects as in the first embodiment are produced. Further, according to the second embodiment, the following effects are additionally produced. That is, an external electrode is provided in a semiconductor package in place of a through electrode. This makes it possible to evaluate the performance of a thermal interface material (the thermal contact resistance of the part of the thermal interface material) in the semiconductor package without executing the process of providing the through electrode in a semiconductor device.

Further, the thermal interface material is divided into multiple regions, and the multiple regions are provided with corresponding test electrodes. This makes it possible to measure the electrical resistances of multiple paths corresponding to the multiple regions. As a result, it is possible to evaluate the magnitude of the thermal contact resistance between the thermal interface material and each of the heat spreader and the semiconductor device on a region-by-region basis. That is, it is possible to understand the state of the thermal contact of the thermal interface material and each of the semiconductor device and the heat spreader on a region-by-region basis.

In the second embodiment, the thermal interface material60is divided into the four regions60d, and the four regions60dare provided with as many corresponding test electrodes. Alternatively, the thermal interface material60may not be divided into four regions, and a single test electrode may be provided. Further, it is also possible to divide the thermal interface material60into more than or less than four regions and provide the regions with respective test electrodes.

A description is given of a third embodiment. In the third embodiment, a case is illustrated where the through electrode23of the first embodiment is replaced with external electrodes81.FIG. 13is a plan view of a semiconductor package according to the third embodiment.FIG. 14is a cross-sectional view of the semiconductor package according to the third embodiment. InFIG. 13, the graphical representation of the heat spreader70illustrated inFIG. 14is omitted.

Referring toFIG. 13andFIG. 14, in a semiconductor package13according to the third embodiment, the semiconductor device20of the first embodiment is replaced with the semiconductor device20A. That is, the semiconductor package13does not include the through electrode23.

Further, according to the semiconductor package13, the thermal interface material60is divided into the four regions60das indicated by broken lines inFIG. 13, and the external electrodes81are provided on the bottom surface20Aa of the semiconductor device20A so as to correspond to the four divided regions60d. Each of the external electrodes81is a metal layer that extends from the bottom surface20Aa of the semiconductor device20A over a side surface of the semiconductor device20A, the underfill resin50, and the solder resist layer36, so as to have an end portion81aelectrically connected to the third interconnection layer35(or a metal layer if the metal layer is formed on the third interconnection layer35) in a corresponding one of the openings36x, where the third interconnection layer35is exposed, of the (upper) solder resist layer36of the multilayer wiring board30. The external electrodes81have their respective end portions81apositioned on the outer side compared with the heat spreader70.

The end portions81aof the external electrodes81do not necessarily have to be electrically connected to the third interconnection layer35(or a metal layer if the metal layer is formed on the third interconnection layer35) in the corresponding openings36x, where the third interconnection layer35is exposed, of the (upper) solder resist layer36of the multilayer wiring board30, and may be fixed to the multilayer wiring board30.

Portions of the third interconnection layer35to which the external electrodes81are connected are not electrically connected to the first interconnection layer31of the multilayer wiring board30, so that the external electrodes81are not electrically connected to the first interconnection layer31of the multilayer wiring board30via the third interconnection layer35. That is, the semiconductor package13does not have the test pad39. The lead92is connected directly to each of the external electrodes81. Examples of the material of the external electrodes81include copper. The external electrodes81may be formed by, for example, electroless plating, electroplating, or vapor deposition. In the semiconductor package13, the external electrodes81are typical examples of the test electrode according to this embodiment. Hereinafter, the external electrodes81may be referred to as “test electrodes.”

The thermal interface material60is provided on the external electrodes81. In the semiconductor package13, the same elements as those of the semiconductor package10of the first embodiment are referred to by the same reference numerals, and a description thereof is omitted.

The method of manufacturing the semiconductor package13is substantially the same as the method of manufacturing the semiconductor package10, but additionally includes the process of forming the external electrodes81on the bottom surface20Aa of the semiconductor device20A by, for example, electroless plating, electroplating, or vapor deposition.

The method of evaluating the performance of a thermal interface material in the semiconductor package13is substantially the same as that in the semiconductor package10. The difference lies in that the performance of the thermal interface material is evaluated on a region-by-region basis by connecting the leads91and92to the heat spreader70and the external electrode81, respectively, as illustrated inFIG. 15in each of the regions60dsubjected to the evaluation one after another.

Thus, according to the third embodiment, the same effects as in the first embodiment are produced. Further, according to the second embodiment, the following effects are additionally produced. That is, an external electrode is provided in a semiconductor package in place of a through electrode. This makes it possible to evaluate the performance of a thermal interface material (the thermal contact resistance of the part of the thermal interface material) in the semiconductor package without executing the process of providing the through electrode in a semiconductor device.

Further, the thermal interface material is divided into multiple regions, and the multiple regions are provided with corresponding test electrodes. This makes it possible to measure the electrical resistances of multiple paths corresponding to the multiple regions. As a result, it is possible to evaluate the magnitude of the thermal contact resistance between the thermal interface material and each of the heat spreader and the semiconductor device on a region-by-region basis. That is, it is possible to understand the state of the thermal contact of the thermal interface material and each of the semiconductor device and the heat spreader on a region-by-region basis.

Further, the external electrode has an end portion positioned on the outer side than the heat spreader. This makes it possible to measure the electrical resistance of a predetermined path without providing a test pad corresponding to the external electrode.

In the third embodiment, the thermal interface material60is divided into the four regions60d, and the four regions60dare provided with as many corresponding test electrodes. Alternatively, the thermal interface material60may not be divided into four regions, and a single test electrode may be provided. Further, it is also possible to divide the thermal interface material60into more than or less than four regions and provide the regions with respective test electrodes.

A description is given of a fourth embodiment.

In the fourth embodiment, a case is illustrated where the through electrode23of the first embodiment is replaced with external electrodes82.FIG. 16is a plan view of a semiconductor package according to the fourth embodiment.FIG. 17is a cross-sectional view of the semiconductor package according to the fourth embodiment. InFIG. 16, the graphical representation of the heat spreader70illustrated inFIG. 17is omitted.

Referring toFIG. 16andFIG. 17, in a semiconductor package14according to the fourth embodiment, the semiconductor device20of the first embodiment is replaced with the semiconductor device20A. That is, the semiconductor package14does not include the through electrode23.

Further, according to the semiconductor package14, the thermal interface material60is divided into the four regions60das indicated by broken lines inFIG. 16, and the external electrodes82are provided on the bottom surface20Aa of the semiconductor device20A so as to correspond to the four divided regions60d. The external electrodes82are adhered and fixed to the bottom surface20Aa of the semiconductor device20A with an electrically conductive adhesive agent (not graphically illustrated) such as silver paste. The external electrodes82have respective end portions82aadhered and fixed, with solder83, onto the third interconnection layer35(or a metal layer if the metal layer is formed on the third interconnection layer35) in the corresponding openings36x, where the third interconnection layer35is exposed, of the (upper) solder resist layer36of the multilayer wiring board30.

The end portions82aof the external electrodes82do not necessarily have to be adhered and fixed, with solder83, onto the third interconnection layer35(or a metal layer if the metal layer is formed on the third interconnection layer35) in the corresponding openings36x, where the third interconnection layer35is exposed, of the (upper) solder resist layer36of the multilayer wiring board30, and may be fixed to the multilayer wiring board30.

Portions of the third interconnection layer35to which the external electrodes82are connected are not electrically connected to the first interconnection layer31of the multilayer wiring board30, so that the external electrodes82are not electrically connected to the first interconnection layer31of the multilayer wiring board30via the third interconnection layer35. That is, the semiconductor package14does not have the test pad39. The lead92is connected directly to each of the external electrodes82.

The external electrodes82may be, for example, pressed metal plates formed of a material having good thermal and electrical conductivities, such as copper. Examples of the material of the solder83include alloys containing Pb, alloys of Sn and Cu, alloys of Sn and Ag, and alloys of Sn, Ag, and Cu. The external electrodes82are typical examples of the test electrode according to this embodiment. Hereinafter, the external electrodes82may be referred to as “test electrodes.”

The thermal interface material60is provided on the external electrodes82. In the semiconductor package14, the same elements as those of the semiconductor package10of the first embodiment are referred to by the same reference numerals, and a description thereof is omitted.

The method of manufacturing the semiconductor package14is substantially the same as the method of manufacturing the semiconductor package10, but additionally includes the process of adhering and fixing the external electrodes82onto the bottom surface20Aa of the semiconductor device20A with an electrically conductive adhesive agent such as silver paste and the process of adhering and fixing the end portions82aof the external electrodes82, with the solder83, onto the third interconnection layer35(or a metal layer if the metal layer is formed on the third interconnection layer35) in the corresponding openings36x, where the third interconnection layer35is exposed, of the (upper) solder resist layer36of the multilayer wiring board30.

The method of evaluating the performance of a thermal interface material in the semiconductor package14is substantially the same as that in the semiconductor package10. The difference lies in that the performance of the thermal interface material is evaluated on a region-by-region basis by connecting the leads91and92to the heat spreader70and the external electrode82, respectively, as illustrated inFIG. 18in each of the regions60dsubjected to the evaluation one after another.

Thus, according to the fourth embodiment, the same effects as in the first embodiment are produced. Further, according to the second embodiment, the following effects are additionally produced. That is, an external electrode formed of a metal plate or the like is provided in a semiconductor package in place of a through electrode. This makes it possible to evaluate the performance of a thermal interface material (the thermal contact resistance of the part of the thermal interface material) in the semiconductor package without executing the process of providing the through electrode in a semiconductor device or performing electroless plating on the semiconductor device.

Further, the thermal interface material is divided into multiple regions, and the multiple regions are provided with corresponding test electrodes. This makes it possible to measure the electrical resistances of multiple paths corresponding to the multiple regions. As a result, it is possible to evaluate the magnitude of the thermal contact resistance between the thermal interface material and each of the heat spreader and the semiconductor device on a region-by-region basis. That is, it is possible to understand the state of the thermal contact of the thermal interface material and each of the semiconductor device and the heat spreader on a region-by-region basis.

In the fourth embodiment, the thermal interface material60is divided into the four regions60d, and the four regions60dare provided with as many corresponding test electrodes. Alternatively, the thermal interface material60may not be divided into four regions, and a single test electrode may be provided. Further, it is also possible to divide the thermal interface material60into more than or less than four regions and provide the regions with respective test electrodes.

For example, in each of the first through fourth embodiments, a semiconductor package is illustrated that has a semiconductor device and a multilayer wiring board connected via solder bumps. However, the present invention may also be applied to semiconductor packages where a semiconductor device and a multilayer wiring board are connected by other methods such as gold bumps, and to semiconductor packages where a semiconductor device and a multilayer wiring board are directly connected.

Further, the present invention may also be applied to semiconductor packages other than those having a coreless multilayer wiring board manufactured by a build-up process. For example, the present invention may be applied to semiconductor packages having various types of wiring boards such as a multilayer wiring board having a core part manufactured by a build-up process, a single-sided (single-layer) wiring board having an interconnection layer formed on only one side of the board, a double-sided (two-layer) wiring board having an interconnection layer formed on each side of the board, a multilayer wiring board having interconnection layers connected with through vias, and an interstitial via hole (IVH) multilayer wiring board having particular interconnection layers connected with an IVH.