Vertical elevated pore phase change memory

A vertical elevated pore structure for a phase change memory may include a pore with a lower electrode beneath the pore contacting the phase change material in the pore. The lower electrode may be made up of a higher resistivity lower electrode and a lower resistivity lower electrode underneath the higher resistivity lower electrode. As a result, more uniform heating of the phase change material may be achieved in some embodiments and better contact may be made in some cases.

BACKGROUND

This invention relates generally to electronic memories and particularly to electronic memories that use phase change material.

Phase change materials may exhibit at least two different states. The states may be called the amorphous and crystalline states. Transitions between these states may be selectively initiated. The states may be distinguished because the amorphous state generally exhibits higher resistivity than the crystalline state. The amorphous state involves a more disordered atomic structure. Generally any phase change material may be utilized. In some embodiments, however, thin-film chalcogenide alloy materials may be particularly suitable.

The phase change may be induced reversibly. Therefore, the memory may change from the amorphous to the crystalline state and may revert back to the amorphous state thereafter, or vice versa, in response to temperature changes. In effect, each memory cell may be thought of as a programmable resistor, which reversibly changes between higher and lower resistance states. The phase change may be induced by resistive heating.

Existing phase change memories may experience inefficient heating of the phase change material. Thus, there is a need for better ways to heat phase change material.

DETAILED DESCRIPTION

Referring toFIG. 1, a phase change memory10may include a plurality of phase change memory cells including the adjacent cells12aand12bon adjacent bitlines14. Each bitline14is positioned over a barrier material16. The barrier material16may extend into a pore46on top of the phase change material18which may be a chalcogenide material in one embodiment of the present invention.

Examples of phase change memory material include, but are not limited to, chalcogenide element(s) compositions of the class of tellerium-germanium-antimony (TexGeySbz) material or GeSbTe alloys, although the scope of the present invention is not limited to just these. Alternatively, another phase change material may be used whose electrical properties (e.g. resistance, capacitance, etc.) may be changed through the application of energy such as, for example, light, heat, or electrical current.

The pore46may be defined by a sidewall spacer22in one embodiment. The pore46and sidewall spacer22may be defined by an opening formed in a dielectric or insulating material20. The material20may be an oxide, nitride, or any other insulating material.

Below the pore46is a pair of lower electrodes including a relatively higher resistivity lower electrode24and a relatively lower resistivity lower electrode26. The higher resistivity electrode24maybe responsible for heating the adjacent portion of the phase change material18and, thus, may have a greater vertical extent. The lower resistivity electrode material26functions to distribute electrical current efficiently across the entire width of the higher resistivity electrode material24.

Electrical current is received from the lower resistivity electrode material26and passes through the pedestal liner conductor30in one embodiment. The conductor30may be cup-shaped in one embodiment of the present invention and may be filled with an insulator28which also surrounds the pedestal liner conductor30.

A nitride layer32may be penetrated by the pedestal liner conductor30. The nitride layer32may be positioned over an isolating layer35formed on a semiconductor substrate including a p+ region38.

The p+ region38may be adjacent a silicide contact region34. Below the p+ region38is an n-type silicon layer40. An n+ region36may be positioned between adjacent bitlines14. Underneath the n-type silicon layer40is a p-type epitaxial (EPI) silicon layer42and a P++ type silicon substrate44in one embodiment of the present invention.

The resistivity of the relatively higher resistivity lower electrode24may be in the 1–500 mohm-cm, preferably 30–100 mohm-cm range. The lower resistivity lower electrode26may have a resistivity in the 0.01–1.0 mohm-cm, preferably 0.05–0.15 mohm-cm range in one embodiment of the present invention. Examples of resistive materials that may be used as the electrodes24and26include silicon nitride and tantalum nitride.

A processor-based system, shown inFIG. 2, may include a processor50such as a general purpose or digital signal processor as two examples. The processor50may be coupled to the memory10, for example, by a bus52. In some embodiments, a wireless interface54may be provided. The wireless interface54may include a transceiver or an antenna, to give two examples.