Semiconductor package including a backside redistribution layer

A semiconductor package includes a frame having a cavity and having a wiring structure connecting first and second surfaces opposing each other; a connection structure disposed on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a semiconductor chip disposed in the cavity and having a connection pad connected to the first redistribution layer; an encapsulant encapsulating the semiconductor chip; and a second redistribution layer having a redistribution pattern and a connection via connecting the wiring structure and the redistribution pattern. The connection via includes a first via connected to the wiring structure and a second via disposed on the first via and connected to the redistribution pattern, a lower surface of the second via has an area larger than an area of an upper surface of the first via.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims benefit of priority to Korean Patent Application No. 10-2018-0132775 filed on Nov. 1, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a semiconductor package.

BACKGROUND

One of the major trends in the development of technology related to semiconductor chips in recent years is to reduce the size of components, and in the field of packages as well, compact semiconductor chips with multiple pins to ensure a compact size are required to be realized as demand therefor has increased.

In order to meet the demand, a fan-out semiconductor package has been proposed. In the fan-out semiconductor package, connection terminals may be redistributed even in a region outside a region overlapping a semiconductor chip, thus realizing multiple pins, while having a compact size. Some semiconductor packages may require a backside redistribution layer (RDL). However, such a backside RDL requires additional lithography as a separate line process.

SUMMARY

An aspect of the present disclosure may provide a semiconductor package having a redistributed layer which may be realized through a simplified process.

According to an aspect of the present disclosure, a semiconductor package may include: a frame having a cavity and having a wiring structure connecting first and second surfaces configured to oppose each other; a connection structure disposed on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a semiconductor chip disposed on the connection structure in the cavity and having a connection pad connected to the first redistribution layer; an encapsulant encapsulating the semiconductor chip located in the cavity and covering the second surface of the frame; and a second redistribution layer having a redistribution pattern embedded in the encapsulant and exposed in one surface thereof and a connection via connecting the wiring structure and the redistribution pattern through the encapsulant. The connection via may include a first via connected to the wiring structure and a second via disposed on the first via and connected to the redistribution pattern, a lower surface of the second via may have an area larger than an area of an upper surface of the first via, and the first and second vias may have an integrated structure.

According to another aspect of the present disclosure, a semiconductor package may include: a frame having a cavity and having a wiring structure connecting first and second surfaces configured to oppose each other; a connection structure disposed on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a semiconductor chip disposed on the connection structure in the cavity and having a connection pad connected to the first redistribution layer; an encapsulant encapsulating the semiconductor chip located in the cavity and covering the second surface of the frame; and a second redistribution layer having a redistribution pattern embedded in the encapsulant and exposed in one surface thereof and a connection via connecting the wiring structure and the redistribution pattern through the encapsulant. The connection via may include a first via connected to the wiring structure and a second via disposed on the first via, having the center offset from the center of the first via, and connected to the redistribution pattern.

DETAILED DESCRIPTION

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.

Electronic Device

Hereinafter, exemplary embodiments in the present disclosure will be described in detail with reference to the accompanying drawings.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.

Referring toFIG. 1, an electronic device1000may accommodate a mainboard1010therein. The mainboard1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to other components, to be described below, to form various signal lines1090.

FIG. 2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG. 2, a semiconductor package may be used for various purposes in the various electronic devices1000as described above. For example, a motherboard1110may be accommodated in a body1101of a smartphone1100, and various electronic components1120may be physically or electrically connected to the motherboard1110. In addition, other components that may or may not be physically or electrically connected to the mainboard1010, such as a camera module1130, may be accommodated in the body1101. Some of the electronic components1120may be the chip related components, and the semiconductor package100may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone1100, but may be other electronic devices as described above.

Semiconductor Package

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a semiconductor finished product in itself, and may be damaged due to external physical or chemical impact. Therefore, the semiconductor chip may not be used by itself, but is instead packaged and used in an electronic device or the like in a package state.

The reason why semiconductor packaging is commonly used is that there is generally a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connection. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and use of packaging technology for buffering a difference in a circuit width between the semiconductor and the mainboard is thus advantageous.

A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the drawings.

Fan-In Semiconductor Package

FIGS. 3A and 3Bare schematic cross-sectional views illustrating a fan-in semiconductor package before and after being packaged, andFIG. 4shows a series of schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, a semiconductor chip2220may be, for example, an integrated circuit (IC) in a bare state, including a body2221including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads2222formed on one surface of the body2221and including a conductive material such as aluminum (Al), or the like, and a passivation layer2223such as an oxide film, a nitride film, or the like, formed on one surface of the body2221and covering at least portions of the connection pads2222. In this case, since the connection pads2222are significantly small, it may be difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the mainboard of the electronic device, or the like.

Therefore, depending on a size of the semiconductor chip2220, a connection structure2240may be formed on the semiconductor chip2220in order to redistribute the connection pads2222. The connection structure2240may be formed by forming an insulating layer2241on the semiconductor chip2220using an insulating material such as a photo imageable dielectric (PID) resin, forming via holes2243opening on to the connection pads2222, and then forming wiring patterns2242and vias2243. Then, a passivation layer2250protecting the connection structure2240may be formed, and an opening2251may be formed to have an underbump metal layer2260, or the like, extending therethrough. That is, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the connection structure2240, the passivation layer2250, and the underbump metal layer2260may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip, are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size.

However, since all I/O terminals generally need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has a large spatial limitation. Therefore, it may be difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a small size. In addition, due to the disadvantages described above, the fan-in semiconductor package may not be directly mounted and used on the mainboard of the electronic device. The reason is that even in the case that a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the mainboard of the electronic device.

FIG. 5is a schematic cross-sectional view illustrating a fan-in semiconductor package mounted on an interposer substrate that is ultimately mounted on a mainboard of an electronic device, andFIG. 6is a schematic cross-sectional view illustrating a fan-in semiconductor package embedded in an interposer substrate that is ultimately mounted on a mainboard of an electronic device.

Referring to the drawings, in a fan-in semiconductor package2200, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more through an interposer substrate2301, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device in a state in which it is mounted on the interposer substrate2301. In this case, solder balls2270, and the like, may be fixed by an underfill resin2280, or the like, and an external surface of the semiconductor chip2220may be covered with an encapsulant2290, or the like. Alternatively, a fan-in semiconductor package2200may be embedded in a separate interposer substrate2302, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed once more by the interposer substrate2302in a state in which the fan-in semiconductor package2200is embedded in the interposer substrate2302, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device.

As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the mainboard (e.g.,2500) of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate (e.g.,2301or2302) and be then mounted on the mainboard of the electronic device through a packaging process or may be mounted and used on the mainboard of the electronic device in a state in which it is embedded in the interposer substrate.

Fan-Out Semiconductor Package

Referring toFIG. 7, in a fan-out semiconductor package2100, for example, an external surface of a semiconductor chip2120may be protected by an encapsulant2130, and connection pads2122of the semiconductor chip2120may be redistributed outwardly of the semiconductor chip2120by a connection structure2140. In this case, a passivation layer2202may be further formed on the connection structure2140, and an underbump metal layer2160may be further formed in openings of the passivation layer2202. Solder balls2170may be further formed on the underbump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, the connection pads2122, a passivation layer (not illustrated), and the like. The connection structure2140may include an insulating layer2141, redistribution layers2142formed on the insulating layer2141, and vias2143electrically connecting the connection pads2122and the redistribution layers2142to each other.

In the present manufacturing process, the connection structure2140may be formed after the encapsulant2130is formed outside the semiconductor chip2120. In this case, a process for forming the connection structure2140is performed from the via(s) connected to the connection pads2122of the semiconductor chip2120and the redistribution layer, and thus, the vias2143may have a width reduced toward the semiconductor chip2120(see an enlarged region).

As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip2120through the connection structure2140formed on the semiconductor chip2120. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip generally need to be disposed inside the semiconductor chip (e.g., within the footprint of the semiconductor chip on the package). Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls generally need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. Meanwhile, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip2120are redistributed and disposed outwardly of the semiconductor chip2120(e.g., outwardly from the footprint of the semiconductor chip) through the connection structure2140formed on the semiconductor chip as described above. Therefore, even in the case that a size of the semiconductor chip2120is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using a separate interposer substrate, as described below.

FIG. 8is a schematic cross-sectional view illustrating a fan-out semiconductor package mounted on a mainboard of an electronic device.

Referring toFIG. 8, a fan-out semiconductor package2100may be mounted on a mainboard2500of an electronic device through solder balls2170, or the like. That is, as described above, the fan-out semiconductor package2100includes the connection structure2140formed on the semiconductor chip2120and capable of redistributing the connection pads2122to a fan-out region that is outside of an area/footprint of the semiconductor chip2120, such that the standardized ball layout may be used in the fan-out semiconductor package2100as it is. As a result, the fan-out semiconductor package2100may be mounted on the mainboard2500of the electronic device without using a separate interposer substrate, or the like.

As described above, since the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem caused by the occurrence of a warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to a packaging technology for mounting the semiconductor chip on the mainboard of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts. The fan-out semiconductor package is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

FIG. 9is a side cross-sectional view illustrating a semiconductor package according to an exemplary embodiment in the present disclosure, andFIGS. 10A and 10Bare a top view (“T” directional view) and a bottom view (“B” directional view) illustrating the semiconductor package illustrated inFIG. 9.

Referring toFIG. 9, a semiconductor package100according to the present exemplary embodiment includes a frame110having a cavity110X and a first surface110A and a second surface110B opposing each other, a semiconductor chip120disposed in the cavity110X, a connection structure140disposed below the first surface110A of the frame110and the semiconductor chip120, and an encapsulant130encapsulating the semiconductor chip120located in the cavity110X and covering the second surface110B of the frame110.

The frame110includes an insulating member111and a wiring structure connecting the first surface110A and the second surface110B. In this embodiment, the wiring structure may include a first wiring pattern112aand a second wiring pattern112brespectively disposed on the first surface110A and the second surface110B of the frame110, and a through via113connecting the first and second wiring patterns112aand112b.

The connection structure140includes an insulating layer141and a first redistribution layer145formed on the insulating layer141. The first redistribution layer145includes a first redistribution pattern142disposed on the insulating layer and a via143connected to the first redistribution pattern142through the insulating layer141. The first redistribution layer145may be connected to a wiring structure (in particular, the first wiring pattern112a) of the frame110, and a connection pad120P of the semiconductor chip120by a via143. The first redistribution layer145employed in the present exemplary embodiment is illustrated as having a two-level structure disposed on each of two insulating layers141but is not limited thereto and may have a one-level structure or three or more level structure.

The semiconductor package100according to the present exemplary embodiment includes a second redistribution layer165having a second redistribution pattern162(hereinafter, referred to as a “redistribution pattern”) and a connection via163, as a backside redistribution layer. The second redistribution pattern162is embedded in the encapsulant130such that one surface of the second redistribution pattern162is exposed from an upper surface of the encapsulant130. The connection via163may penetrate through the encapsulant130to connect the second redistribution pattern162to the wiring structure of the frame110(in particular, the second wiring pattern112b). The second redistribution pattern162may be connected to the second wiring pattern112bthrough the connection via163and may be connected to the first redistribution layer145and the semiconductor chip120through the wiring structure of the frame110.

Referring toFIGS. 11A and 11B, the structure of the second redistribution layer165employed in this exemplary embodiment will be described in more detail.FIGS. 11A and 11Bare an enlarged cross-sectional view and an enlarged partial plan view, respectively, illustrating a region indicated by “A” in the semiconductor package illustrated inFIG. 9.FIG. 11Ais a side cross-sectional view taken along line II-II′ inFIG. 11B, illustrating a cross section connecting the contacts of a land L and the second redistribution layer162connected to the connection via163.

Referring toFIGS. 11A and 11B, the second redistribution pattern162is embedded in the encapsulant130such that one surface thereof is exposed, and the exposed surface of the second redistribution pattern162may be substantially coplanar with the surface of the encapsulant130, but is not limited thereof. For example, the exposed surface of the second redistribution layer162may be located slightly higher or slightly lower than the surface of the encapsulant130.

The connection via163includes a first via163aconnected to the second wiring pattern112bof the wiring structure and a second via163bdisposed on the first via163aand extending in a horizontal direction so as to be connected to the second redistribution layer162. Since the second via163bextends to be connected to the second redistribution layer162, the second via163has a lower surface having an area (or width) greater than that of an upper surface of the first via163a. Referring toFIG. 11A, the first and second vias163aand163bhave a discontinuous side profile and the second via163bmay be expressed as having a width D2(or diameter) greater than a width D1(or diameter) of the first via163a.

Also, the first and second vias163aand163bemployed in this exemplary embodiment have a discontinuous side profile but have an integrated structure.

In this disclosure, the term “integrated structure” does not mean that two elements are simply in contact with each other but refers to a structure formed integrally using the same metal through the same process. For example, when the first via163aand the second via163bare formed together through the same plating process, the first and second vias163aand163bmay be integrated.

As illustrated inFIGS. 11A and 11B, the connection via163includes a seed layer163S located at an interface with the encapsulant130and a plating layer163P formed on the seed layer163S. In this case, since the first and second vias163aand163bare integrally formed, they may be formed by one seed layer163S. The seed layer163S is formed to extend from a bottom surface and a side surface of the first via163ato a side surface of the second via163b. Further, the seed layer163S may also be located at an interface between the second via163band the second redistribution pattern162.

The second redistribution pattern162may be connected to a region of an outer periphery of the second via163b. Since the connection via163employed in this exemplary embodiment is formed by a process different from the second redistribution pattern162, an interface such as a grain boundary may be observed between the second via163band the second redistribution pattern162.

The second via163bhas a relatively large area and serves as a land of the second redistribution pattern162for connection with the second wiring pattern112b. Since the existing second redistribution pattern has a ring-shaped land, a narrow inlet of the ring is blocked before a hole is fully filled during plating for hole filling to generate a seam void in a connection via. In contrast, in this exemplary embodiment, a relatively extended inlet for filling is provided as with the second via163b, and thus, occurrence of a seam void may be prevented (seeFIGS. 15B and 15C).

The second via163bmay have a height h2different from a thickness t0of the second redistribution pattern162. In this exemplary embodiment, it is illustrated that the height h2of the second via163bis slightly larger than the thickness t0of the second redistribution pattern162. However, since the second redistribution pattern162is formed through a process different from that of the second via163b, the height h2of the second via163bmay be slightly smaller than the thickness t0of the second redistribution pattern162or may be substantially equal depending on each process. The height h2of the second via163bmay be smaller than a height h1of the first via163a, but is not limited thereto.

As illustrated inFIG. 11B, the second via163bmay be provided as a land of the second redistribution pattern162, and the first via163amay be connected to the second via163band provided as a connection part with the land L of the second wiring pattern112b. A center C2of the second via163bmay be offset from a center C1of the first via163a. The center C2of the second via163bmay be closer to a connected portion of the second redistribution pattern162than the center C1of the first via163a.

A matching error may occur in a lamination process of embedding the second redistribution pattern162in the encapsulant130. Considering such an error, the land L of the second wiring pattern112b, which is a connection target, needs to be formed to have a size (e.g., a diameter of 200 μm or greater) significantly larger than a size (diameter of 150 μm or smaller) of a general land, and in this case, design freedom of the second wiring pattern112bmay be significantly restricted. The present exemplary embodiment provides a method for solving the problem of matching error by providing a connection via163having a multi-stage structure instead of extending the land L of the second wiring pattern112b. Specifically, the first via163amay be used to be precisely connected to the land L of the second wiring pattern112b, and the second via163bhaving an expanded area may be used to be connected to the second redistribution pattern162.

In this manner, the connection via employed in this exemplary embodiment suppresses occurrence of a seam void and eliminates the necessity of expanding the land of the wiring pattern in consideration of a matching error, advantageously allowing a circuit pattern located at the land level to be formed with high density.

As illustrated inFIG. 10A, the second redistribution layer165may provide an array of a plurality of first and second pads P1and P2corresponding to an arrangement of connection terminals of another semiconductor chip/package to be disposed on the semiconductor package100. Specifically, a first passivation layer171is formed on a surface of the encapsulant130on which the second redistribution layer165is formed. The first passivation layer171has a first opening O1exposing a portion of the second redistribution pattern162and defining a region of the plurality of first and second pads P1and P2, and the first opening O1is formed to correspond to an arrangement of connection terminals of another semiconductor chip/package to be disposed on the semiconductor package100. The plurality of first and second pads P1and P2are arranged as illustrated inFIG. 10Aand may be divided into the first pad of a fan-out region and the second pad of a fan-in region.

Although the second redistribution layer165employed in this exemplary embodiment is illustrated as having a single layer structure, it may also be realized as having a multilayer structure including two or more layers using an insulating resin layer. In this exemplary embodiment, the second redistribution pattern is illustrated to be directly embedded in the encapsulant. However, in some exemplary embodiments, before the lamination process, an insulating resin layer such as ABF for embedding the second redistribution pattern may be formed in advance and the insulating resin layer and the encapsulant may be bonded.

Hereinafter, each component included in the semiconductor package100according to the present exemplary embodiment will be described in more detail.

The frame110may maintain rigidity of the semiconductor package100. The semiconductor chip120may be disposed in the cavity110X of the frame110and the semiconductor chip120may be fixed by the encapsulant130. The frame110provides an extended routing region in the semiconductor package100and may improve design freedom of the semiconductor package100. The wiring structure of the frame110employed in this exemplary embodiment is merely an example and may be modified to be realized in various forms. For example, the wiring structure may further include one or more patterns located at an intermediate level of the frame110. For example, such a pattern may include a ground (GND) pattern, a power (PWR) pattern, and a signal pattern in addition to a pattern for redistribution. The wiring structure may be formed before the semiconductor chip120is disposed, thereby alleviating a problem of yield reduction due to the semiconductor chip120.

The insulating member111of the frame110may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with a reinforcing agent such as glass fiber and/or an inorganic filler. For example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT) resin, and the like, may be used. Alternatively, a photosensitive insulating material such as a photo imageable dielectric (PID) resin may be used. In another example, a metal having excellent rigidity and thermal conductivity may be used, and here, an Fe—Ni-based alloy may be used as the metal. Here, Cu plating may be formed on a surface of the Fe—Ni-based alloy in order to ensure adhesion with the encapsulant130and any other interlayer insulating materials, and the like. The insulating member111may be formed of glass, ceramics, plastic, or the like, but is not limited thereto. Meanwhile, the wiring structure may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or alloys thereof, but is not limited thereto.

The connection structure140is basically a component for redistributing connection pads120P of the semiconductor chip120. Tens to hundreds of connection pads120P having various functions may be redistributed through the connection structure140and may be physically and/or electrically connected to an external device through an electrical connection metal190. The connection structure140is connected to the connection pad120P of the semiconductor chip120and may support the semiconductor chip120. The connection structure140may be directly electrically connected to the semiconductor chip120and the wiring structure of the frame110and the second redistribution layer165may be electrically connected to the semiconductor chip120by bypassing the first redistribution layer145of the connection structure140.

As described above, the connection structure140includes the insulating layer141and a first redistribution layer145formed on the insulating layer141. Similarly to other insulators described above, the insulating layer141may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin having a reinforcing material such as an inorganic filler impregnated with the thermosetting resin and the thermoplastic resin, or a photosensitive insulating material such as a PID resin may be used.

The first and second redistribution layers145and165may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or alloys thereof. A surface treatment layer may further be formed on exposed pad P1and P2regions of the second redistribution pattern162as necessary.

The encapsulant130is a component for protecting the semiconductor chip120. In this exemplary embodiment, the encapsulant130encapsulates the second surface110B of the frame110together with the semiconductor chip120. An encapsulating form is not limited and may be any form that surrounds the semiconductor chip120. For example, the encapsulant130may cover the semiconductor chip120and fill the other remaining space in the cavity110X of the frame110. Since the encapsulant130fills the cavity110X, the encapsulant130may serve as an adhesive and serve to reduce buckling of the semiconductor chip120. The encapsulant130may cover all surfaces excluding a lower surface of the semiconductor chip120. Only a portion of the lower surface of the semiconductor chip120may be covered depending on a position and shape of the connection pad120P of the semiconductor chip120. In some exemplary embodiments, the encapsulant130may include a plurality of layers formed of a plurality of materials. For example, the space in the cavity110X may be filled with a first encapsulant, and the first surface110A of the frame110and the semiconductor chip120may be covered with a second encapsulant different from the first encapsulant.

The material of the encapsulant130is not limited. For example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, and a resin having a reinforcing material such as glass fiber and/or inorganic filler, for example, prepreg, ABF, or the like, impregnated with the thermosetting resin and the thermoplastic resin may be used. In addition, a known molding material such as EMC may be used. In some exemplary embodiments, a material including glass fiber and/or an inorganic filler and an insulating resin may be used to effectively improve warpage.

In some exemplary embodiments, the encapsulant130may include conductive particles for electromagnetic shielding. For example, the conductive particles may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and/or solder, but are not limited thereto.

The semiconductor package100according to the present exemplary embodiment may further include a second passivation layer172disposed under the connection structure140, similarly to the first passivation layer171disposed on the encapsulant130on which the second redistribution layer165is formed.

The first and second passivation layers171and172are configured to protect the second redistribution layer165and the connection structure140from external physical or chemical damage. The second passivation layer172has a second opening O2that exposes at least a portion of the first redistribution pattern142of the connection structure140, similarly to the first passivation layer171described above.

A material of the first and second passivation layers171and172is not particularly limited, and for example, a solder resist may be used. In some exemplary embodiments, a material which is the same or similar to the insulating material used for the frame110and/or the connection structure140(e.g., PID resin, ABF, etc.) may be used.

The semiconductor package100according to the present exemplary embodiment may further include the electrical connection metal190disposed at the second opening O2of the second passivation layer172and exposed to the outside. The electrical connection metal190is configured to physically and/or electrically connect the semiconductor package100to the outside. For example, the semiconductor package100may be mounted on a motherboard of an electronic device through the electrical connection metal190. The electrical connection metal190is connected to the first redistribution pattern142exposed by the second opening O2. In some exemplary embodiments, additional under bump metallurgy (UBM) layer180may be formed on first redistribution pattern142to form the electrical connection metal190.

For example, the electrical connection metal190may be formed of a low melting point metal, e.g., tin (Sn) or an alloy including tin (Sn). The electrical connection metal190may have various structures such as a land, a ball, a pin, and the like, but is not limited thereto.

As illustrated inFIG. 10B, a portion of the electrical connection metal190may be disposed at the fan-out region. The fan-out package is superior in reliability to a fan-in package, has a plurality of I/O terminals, and facilitates 3D interconnection. The arrangement (number, spacing, etc.) of the connection terminals is not limited and may be variously modified depending on conditions of an external device on which the semiconductor package100is to be mounted. In this exemplary embodiment, the electrical connection metal190is illustrated to be provided only on a lower surface of the connection structure140, but in some exemplary embodiment, an external connection terminal similar to the electrical connection metal190may also be provided on the second redistribution layer165, i.e., on the first and second pads P1and P2.

The connection via employed in this exemplary embodiment is illustrated as including the second via extending in the horizontal direction, relative to the first via, and connected to the redistribution pattern, but the present disclosure is not limited thereto. For example, without forming the second via to extend to have an area larger than that of the first via, the second via may be connected to the redistribution pattern, by offsetting the center of the second via from the center of the first via.

In a specific example, as illustrated inFIGS. 12A and 12B, the second via163bmay be realized as a plurality of vias Va, Vb, and Vc arranged such that the centers Ca, Cb, and Cc thereof are offset from each other. The enlarged view illustrated inFIGS. 12A and 12Bmay be understood as a portion corresponding to the portion A inFIG. 9.

Although the plurality of vias Va, Vb, and Vc constituting the second vias are not formed to have a larger area than the first vias163a, the plurality of vias Va, Vb, and Vc may be connected to the second redistribution pattern162by forming the plurality of vias Va, Vb, and Vc to partially overlap each other and offsetting the centers Ca, Cb, and Cc little by little toward the second redistribution pattern162. Since one via Va among the plurality of vias Va, Vb, and Vc is connected to the land L of the second wiring pattern112b, the second wiring pattern112band the second redistribution pattern162spaced apart from each other may be stably connected.

In some exemplary embodiments, the plurality of vias Va, Vb, Vc are formed using the same laser beam and therefore may have approximately the same size, and similarly, they may have the substantially same size as the first vias163a.

FIGS. 13A and 13Bare an enlarged side cross-sectional view and an enlarged plan view, respectively, illustrating a partial region of the semiconductor package according to an exemplary embodiment in the present disclosure.

Referring toFIGS. 13A and 13B, a portion of the redistribution pattern162has a repair portion162R filled with the same metal as the connection via163. Regarding the repair portion162R, as a short-circuited portion of the redistribution pattern162, after the redistribution pattern162is laminated to be embedded in the encapsulant130, a region of the encapsulant130corresponding to a short-circuited portion is removed during a hole forming process (seeFIG. 15B) for the second via163band may be repaired during a plating process (seeFIG. 15C) for the connection via163, and the redistribution pattern may be normally connected by the plated-filled repair portion162R through a planarization process (seeFIG. 15D). Accordingly, a thickness t of the repair portion162R may be substantially equal to the height h2of the second via163b.

Meanwhile, as illustrated inFIG. 13A, although the connection via163is planarized after being filled, an upper surface RC in which a portion adjacent to the center C1of the first via163awhich is relatively deep is recessed may remain.

FIGS. 14A through 14Fare cross-sectional views illustrating major processes of a method of manufacturing the semiconductor package illustrated inFIG. 9. In the following description of the method of manufacturing the semiconductor package100, redundant descriptions which are the same as the above descriptions may be omitted or simplified.

Referring toFIG. 14A, the wiring structure is formed on the insulating member111to prepare the frame110. The insulating member111may be a copper clad laminate (CCL) having a thin metal layer, e.g., a copper foil (not shown) formed on upper and lower surfaces thereof. The copper foil may be used as a seed layer for pattern formation. The first and second wiring patterns112aand112band the through vias113connecting the first and second wiring patterns112aand112bare formed on the insulating member111. A hole for the through vias113may be formed using mechanical drilling and/or laser drilling (e.g., CO2laser or YAG laser). A resin smear in the hole (not shown) may be removed by performing desmearing. The through vias113and the first and second wiring patterns112aand112bmay be formed by electrolytic copper plating or electroless copper plating using a dry film pattern. More specifically, the through vias113and the first and second wiring patterns112aand112bmay be formed using a method such as subtractive, additive, semi-additive process (SAP), modified semi-additive process (MSAP), or the like, but is not limited thereto, and may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or sputtering, if necessary.

Referring toFIG. 14B, a cavity110X penetrating through the first and second surfaces110A and110B of the frame110is formed.

A method of forming the cavity110X is also not limited and the cavity110X may be formed by, for example, mechanical drilling and/or laser drilling, a sand blast method using abrasive particles, a dry etching method using plasma, or the like. In case where the cavity110X is formed using mechanical drilling and/or laser drilling, the resin smear in the cavity110X may be removed by performing desmearing. A size and shape of the cavity110X may be designed according to a size, a shape and the number of the semiconductor chips120(FIG. 14C) to be mounted.

Next, referring toFIG. 14C, after an adhesive support210is adhered to the second surface110B of the frame110, the semiconductor chip120is placed in the cavity110X, an encapsulant130for encapsulating the semiconductor chip120is formed.

The adhesive support210may be various supporting parts having an adhesive surface capable of fixing the frame110. For example, various types of adhesive tapes such as a heat-curable adhesive tape whose adhesion is weakened by a heat treatment, an ultraviolet-curable adhesive tape whose adhesion is weakened by ultraviolet irradiation, or the like, may be used as the adhesive support210.

The semiconductor chip120may be adhered to the adhesive support210in the cavity110X. The connection pad120P of the semiconductor chip120may be adhered to the adhesive support210(face-down). When the connection pad120P of the semiconductor chip120is embedded, the first surface110A of the frame110and a lower surface of the semiconductor chip120may be substantially coplanar. Alternatively, if the connection pad120P of the semiconductor chip120protrudes, the second surface110B of the frame110and a lower surface of the connection pad120P may be substantially coplanar.

In this exemplary embodiment, in a state in which a material for forming the encapsulant130is applied, before the material is completely cured (i.e., a semi-cured state), the second redistribution pattern162prepared on a temporary support220may be transferred to be embedded to the surface of the encapsulant130(seeFIGS. 14D and 14E).

Specifically, referring toFIG. 14D, the second redistribution pattern162prepared on the temporary support220may be laminated to a surface of the uncured or semi-cured encapsulant130.

The temporary support220may be, but is not limited to, a copper clad laminate including a thin metal layer, e.g., a copper foil (not shown), formed on upper and lower surfaces thereof. A release layer may be formed on the copper foil or a surface treatment may be applied so that the second redistribution pattern162may be easily separated in a follow-up process. The second redistribution pattern162may be formed through plating using the copper foil as a seed layer.

This process may be performed using a rivet pin matching method, without a separate matching facility. That is, by fixing the temporary support220, together with the adhesive support210or a support part thereof, by a rivet pin, a position of the second redistribution pattern162to be laminated in each package unit may precisely aligned. Here, although the second redistribution pattern162is aligned using the rivet pin, an unavoidable matching error may occur.

Next, referring toFIG. 14E, the second redistribution pattern162may be embedded in the surface of the encapsulant130.

Since the encapsulant130is in the uncured state, for example, in the semi-cured state, the encapsulant130may allow the second redistribution pattern162, which is formed to be convex with respect to the surface of the temporary support220, to be embedded therein through the lamination process. In the case of using the lamination process, the lamination process may be carried out by hot pressing to press for a predetermined period of time at a high temperature and decompress and cool to room temperature, and subsequently cold pressing to cool additionally.

As illustrated inFIGS. 16A and 16B, the embedded second redistribution pattern162does not overlap the land L of the second wiring pattern112band may be spaced apart therefrom by a predetermined distance d in a horizontal direction. Such a distance d may increase due to the matching error mentioned above. In a state in which the second redistribution pattern162is embedded, a complete curing process may be performed. Even after the second redistribution pattern162is embedded, the temporary support220may be retained to be used as a support in the process of forming the first redistribution layer (or connection structure).

Referring toFIG. 14F, after the adhesive support210is removed from the frame110and the semiconductor chip120, the connection structure140may be formed.

The removal process is not limited and may be carried out in various ways. For example, when a heat-curable adhesive tape whose adhesion is weakened by a heat treatment, an ultraviolet-curable adhesive tape whose adhesion is weakened by ultraviolet irradiation, or the like, is used as the adhesive support210, the removal process may be performed after the adhesive support210is heat-treated to be weakened in adhesion or after ultraviolet rays are irradiated to the adhesive support210to weaken adhesion thereof. As described above, the temporary support220is used as a support in the process of forming the first redistribution layer.

The connection structure140having the first redistribution layer145is formed on lower surfaces of the frame110and the semiconductor chip120, and the second passivation layer172may be formed below the connection structure140.

After performing the above-described processes, a process of forming the second redistribution layer165positioned on the second surface110B of the frame110may be performed. Specifically, a process of forming a connection via for connecting the embedded second redistribution pattern to the wiring structure (in particular, the second wiring pattern112b) is performed.FIGS. 15A to 15Dare cross-sectional views of major processes illustrating a process (connection via formation process) of connecting the second redistribution layer in the manufacturing method of the semiconductor package illustrated inFIG. 9.

Referring toFIG. 15A, after the temporary support220is removed from the surface of the encapsulant130, a first hole H1, which is connected to the land L of the second wiring pattern112b, may be formed.

The temporary support220may be removed so that the embedded second redistribution pattern162remains on the surface of the encapsulant130. The temporary support220may be easily removed using a separation part such as the release layer described above. This removal process may be easily performed after adhesion is weakened by a heat treatment, ultraviolet rays, or the like, depending on the characteristics of the temporary support or the release layer.

The first hole H1for opening the land L of the second wiring pattern112bis formed in the encapsulant. The process of forming the first hole H1may be performed using mechanical drilling and/or laser drilling. As illustrated inFIGS. 17A and 17B, the first hole H1may be connected to the land L of the second redistribution pattern112bbut may not be connected to the second redistribution pattern162.

Thereafter, referring toFIG. 15B, a second hole H2connecting the first hole H1and the second redistribution pattern162may be formed.

The second hole H2may extend an upper region of the first hole H1. For example, in the case of using a laser drilling process, the second hole H2may be formed by expanding a laser beam size using an optical system, or the like, and adjusting the output or an irradiation time so as to have a size larger than the first hole H1and have a depth lower than the first hole H1. After the drilling process, desmearing may be performed using a permanganate method, or the like, to remove a resin smear.

Specifically, as illustrated inFIGS. 18A and 18B, an upper region of the first hole H1may be extended by the second hole H2so as to be connected to the second redistribution pattern162. In this manner, the via hole H including the first and second holes H1and H2may be formed to be connected from the land L to the second redistribution pattern162. Since the center C2of the second hole H2is located closer to the connecting portion of the second redistribution pattern162than the center C1of the first hole H1, a cross-section of the hole H1for a connection via may have a bilateral asymmetric structure when viewed from a side cross-section (seeFIG. 18B) connecting the two centers C1and C2.

In another exemplary embodiment, the second hole H2may be formed as a plurality of holes corresponding to the plurality of vias Va, Vb, and Vc, as illustrated inFIGS. 12A and 12B. The plurality of holes may partially overlap each other and may be arranged toward the connection portion of the second redistribution pattern162. Such a plurality of holes may be formed by repeatedly irradiating a laser beam with the same size.

As described above with reference toFIGS. 13A and 13B, the encapsulant130region located in the short-circuited portion of the second redistribution pattern162may be removed together in this process and may be repaired during plating (seeFIG. 15C) for the connection via163in a follow-up process. Thus, a thickness of the encapsulant130region removed for the repair may be substantially equal to the depth of the second hole H2.

Thereafter, referring toFIG. 15C, a plating layer163′ may be formed on the encapsulant130so that the inside of the via hole H is filled.

In this process, the seed layer163S is formed on the surface of the encapsulant130including the inner surface of the via hole H (seeFIG. 19), and then the plating layer163′ is formed through plating using the seed layer. The plating layer163′ may fill the internal space of the via hole H.

Specifically, as illustrated inFIG. 19, the plating layer163′ may fill the internal space of the via hole H, and here, a region corresponding to the via hole H is slightly recessed. Also, the second redistribution pattern162does not have a ring-shaped land, and since the inlet of the via hole H1has a large size due to the extended second hole H2, the internal space of the hole H may be substantially completely filled during plating. That is, since the relatively large inlet is not blocked during the filling process, the via hole H may be filled without a seam void.

Next, referring toFIG. 15D, a portion of the plating layer located on the encapsulant130is removed so that the connection via163is formed.

Such a removal process may be performed as a planarization process such as etch-back or grinding. The plating layer portion remaining in the via hole H may be provided as the connection via163. The connection via163may connect the second wiring pattern112bof the wiring structure and the second redistribution pattern162. Specifically, as illustrated inFIG. 20, the connection via163may include the first via163aconnected to the wiring structure and the second via163bdisposed on the first via163aand extending in the horizontal direction so as to be connected to the second redistribution pattern162. The first and second vias163aand163bmay be integrated. The connection via163may provide a desired second redistribution layer165together with the second redistribution pattern162.

The connection via163includes the seed layer163S located at an interface with the encapsulant130and the plating layer163P formed on the seed layer163S. The seed layer163S is formed to extend from the bottom surface and the side surface of the first via163ato the side surface of the second via163b. In particular, the seed layer163S may be located at the interface between the second via163band the second redistribution pattern162and also between the interface between the second via163band the encapsulant130, and actually, the interface between the second via163band the second redistribution pattern162may be observed.

By this process, the exposed surface of the second redistribution pattern162may be substantially coplanar with the surface of the encapsulant130. In this exemplary embodiment, the upper surface of the connection via163may have a planarized upper surface, but if the recessed portion illustrated inFIG. 19is formed to be deep, the upper surface of the connection via163may have a recessed portion RC adjacent to a central axis of the first via163aas illustrated inFIG. 13Aeven after the planarization process.

The connection via163employed in the present exemplary embodiment provides a scheme of stably connecting the land located below and the redistribution pattern located above although mismatching occurs during the lamination process. Therefore, it is not necessary to expand the area of the land located below in consideration of mismatching (i.e., matching error), and thus, a circuit pattern located at the land level may be formed with high density. Further, since a ring-shaped structure is not required to be employed in the redistribution pattern connected to the land, occurrence of a seam void in the connection via connecting the land and the redistribution pattern may be suppressed.

In the follow-up processes, after the first passivation layer171is formed in a similar manner to the second passivation layer172, the plurality of first and second openings O1and O2are formed in the first and second passivation layers171and172, respectively, the electrical connection metal190is formed in the UBM layer180located in the second opening O2, thus manufacturing the semiconductor package100illustrated inFIG. 9. If necessary, an electrical connection metal may be additionally formed in the second opening O2.

As set forth above, according to some exemplary embodiments of the present disclosure, the scheme of stably connecting the land located below and the redistribution pattern located above although mismatching occurs during the lamination process may be provided. Therefore, it is not necessary to expand the area of the land located below in consideration of mismatching, and thus, a circuit pattern located at the land level may be formed with high density.

Further, according to some exemplary embodiments, a ring-shaped structure is not required to be employed in the redistribution pattern connected to the land, and thus, occurrence of a seam void in the connection via connecting the land and the redistribution pattern may be suppressed.