Chaotic oscillator-based random number generation

Chaotic oscillator-based random number generation is described. In an example, a circuit includes a negative differential resistance (NDR) device to receive an alternating current (AC) bias. The circuit further includes a capacitance in parallel with the NDR device, the capacitance having a value such that, in response to a direct current (DC) bias applied to the NDR device and the capacitance, a voltage across the capacitance oscillates with a chaotic period. The circuit further includes a random number generator to generate random numbers using samples of the voltage across the capacitance.

BACKGROUND

Random number generators are useful for a large number of applications, such as in computing systems. Some random number generators are software-based. Software-based random number generators depend on the randomness of user input, such as keyboard strokes and mouse movement, to generate random numbers. However, this so-called “user entropy” can sometimes be unavailable for seeding random numbers in some applications, such as with virtual machines running on a computer system. As such, the randomness of the numbers generated by a software-based solution can be insufficient for various applications. Some random number generators are hardware-based, and can generate “pseudo-random” numbers. A hardware-based generator can generate a sequence of numbers that approximate the properties of random numbers. The sequence is not truly random, as it is completely determined by a small set of initial values or “seed values.” In some applications, truly random numbers are preferred to pseudorandom numbers.

DETAILED DESCRIPTION

FIG. 1is a schematic diagram showing a chaotic oscillator circuit100according to an example implementation. The chaotic oscillator circuit100can include a bias voltage supply102, a resistance104, a negative differential resistance (NDR) device106, a bias voltage supply108, and a capacitance110. Element112identifies electrical ground or other common potential. The NDR device106is in series with the bias voltage supply108. The NDR device106and the bias voltage supply108are in parallel with the capacitance110. The NDR device106and the capacitance110are in series with the resistance104. In an example, the bias voltage supply102supplies a direct current (DC) bias voltage, and the bias voltage supply108supplies an alternating current (AC) bias voltage. In an example, the magnitude of the AC bias voltage is less than the DC bias voltage. The frequency of the AC bias voltage can be selected based on the values of the properties of the resistance104, capacitance110, and NDR device106, The resistance104can be provided by any type of resistive component, such as a resistor or other type of semiconductor formation resulting in resistance. The capacitance110can be provided by any type of capacitive component, such as a capacitor or other type of semiconductor formation resulting in capacitance.

In an example, the NDR device106is a current-controlled NDR device. For example, the NDR device106can be a metal-oxide-metal device that functions as a threshold switch. In another example, the NDR device106can be an amorphous silicon device. The following describes the manner in which an oscillating signal is produced with a chaotic oscillation period.

When a DC bias voltage is applied by the bias voltage supply102, the DC bias voltage will be divided between the resistance104and the NDR device106. The same voltage applied across the NDR device106will be coupled across the capacitance110. The voltage across the capacitance110will begin increasing. The capacitance110will charge according to a time constant defined by the capacitance110and the resistance104. After the capacitance110charges to a particular voltage level, the current flowing through the NDR device106will cause the voltage across the NDR device106to fall within an “NDR region” (described below with respect toFIG. 2), which essentially causes the NDR device106to provide a negative resistance. A device that exhibits a “negative resistance” will experience a decrease in voltage with a rise in current at certain current levels. This is opposed to standard electric devices that always experience an increase in voltage with an increase in current. Due to the negative resistance, the NDR device106will experience a decrease in voltage with the rising current. This will cause the capacitance110to begin to discharge.

FIG. 2shows a graph200relating current through the NDR device106to voltage across the NDR device106according to an example implementation. The graph200includes an axis202representing current, and an axis204representing voltage. A curve208represents the voltage-current relationship for the NDR device106. As voltage across the NDR device106increases, current begins to flow through the NDR device106. When the current reaches a certain value, the voltage across the NDR device106begins decreasing. There exists a region206(NDR region) where the voltage decreases with increasing current. As the current is still further increased, the voltage will again begin to increase, eventually outside of the region206.

Returning toFIG. 1, the voltage across the NDR device106oscillates according to the AC bias voltage of the source108, but generally increases as the capacitance110is charged by the DC bias of the source102. Once current through the NDR device106triggers negative resistance, the voltage across the NDR device106generally decreases. After the capacitance110has discharged below a certain level, the current flowing through the NDR device106will fall outside of the NDR region. Thus, the voltage across the NDR device106will once again increase with increasing current. This will cause the capacitance110to begin charging again. The continual charging and discharging of the capacitance110causes an oscillating voltage signal across the capacitance110(“oscillating output voltage”).

The value of the capacitance110controls the period of the oscillating output voltage.FIG. 3Ashows a graph300of oscillating period versus capacitance according to an example implementation. The graph300includes an axis302representing the period of oscillation, and an axis304representing capacitance. The period of oscillation increases in a step-pattern as the capacitance increases. In an example, the period doubles after each step. That is, the period is constant and stable for a certain range of capacitance, and then increases (e.g., doubles) and remains constant and stable for another range of capacitance. For example, a stable oscillating period308exists for a certain range of capacitance, followed by an increased stable oscillating period310for another range of capacitance. A region306(“transition region”) of capacitance between the ranges marks a transition between stable period308and stable period310. The period becomes unstable at a certain range of capacitance in the transition region306.

Notably,FIG. 3Bshows a graph301of oscillating period versus capacitance in the transition region306according to an example implementation. Initially, the capacitance results in the stable period308. As the capacitance increases, the period begins increasing (e.g., doubling). The increasing periods, however, exist for narrower and narrower ranges of capacitance. Eventually the capacitance is increased to a point resulting in the stable period310. Thus, a region312of capacitance exists where the period increases rapidly between two stable periods. The behavior of the period in the capacitance region312is unstable and chaotic in the presence of noise. Within the capacitance region312, there is a period multiplication route to chaos. By “chaos”, it is meant that the period is highly sensitive to slight changes in conditions such that small alterations in the conditions (e.g., noise) can give rise to large changes in the period.

Returning toFIG. 1, the capacitance110can be a component, such as a capacitor, designed to have a specific capacitance (“target capacitance”) such that the period of the oscillating output voltage is unstable and chaotic in the presence of noise in the circuit100, as shown inFIG. 3B. Thus, the circuit100can be designed to provide an oscillating output voltage having an unstable and chaotic period of oscillation. Such an oscillating output voltage with chaotic period can be used for random number generation, as discussed below.

The circuit100generally provides a relaxation oscillator that is driven by an NDR device having an AC bias. The capacitance in the relaxation oscillator is tuned to an edge of stability such that the oscillation period of the output voltage experiences a multiplication route to chaos. Thus, the output voltage will oscillate with an unstable and chaotic period in the presence of noise.

FIG. 4a schematic diagram showing another chaotic oscillator circuit400according to an example implementation. Elements ofFIG. 4that are the same or similar toFIG. 1are designated with identical reference numerals and described in detail above. In the present example, the capacitance110can be replaced with an adjustable capacitance402. In an example, the adjustable capacitance402can be a voltage-controlled capacitance, such as a varactor or the like. Thus, the adjustable capacitance402can be tuned dynamically during operation to an edge of stability such that the oscillation period of the output voltage experiences a multiplication route to chaos.

FIG. 5is a block diagram showing a circuit500to generate random numbers according to an example implementation. The circuit500includes a chaotic oscillator502, voltage sources503, and a random number generator504. The chaotic oscillator502receives bias voltage from the voltage source503, and produces an oscillating output voltage with chaotic oscillation period. The random number generator504samples the oscillating output voltage to generate voltage samples, and uses the voltage samples as seed values to generate random numbers. The chaotic oscillator502includes a relaxation oscillator506having a DC bias input508, an AC bias input510, a resistance512, an NDR device514, and a capacitance516. In an example, the relaxation oscillator506can be arranged as shown by the circuit100ofFIG. 1or the circuit400ofFIG. 4. The capacitance516can be tuned to result in an unstable and chaotic oscillation period, as described above. The random number generator504can include various analog and digital circuits to sample the oscillating output voltage and digital representations of random numbers based on initial “seed values.”

The circuit500provides a hardware-based random number generator that can be used to generate random numbers for various applications, such as for use in computing devices and systems by various software applications, operating systems, hardware peripherals, and the like. The input entropy (e.g., seed values) is chaotic resulting in true random numbers, in contrast to pseudo-random numbers generated by other types of circuits, such as shift-register based circuits.

FIG. 6illustrates a semiconductor device600according to an example implementation. The semiconductor device600includes bias circuits602, conductive interconnect604, and chaotic oscillator circuits606. The chaotic oscillator circuits606can include an NDR device608and a capacitance610. The chaotic oscillator circuits606can receive bias voltages from the bias circuits602through the conductive interconnect604. The capacitance610can be formed on the semiconductor device600using any of various capacitive formations, capacitors, or adjustable capacitances. The NDR device608can include a metal-oxide-metal device.

FIG. 7shows a cross-section of the NDR device608according to an example implementation. The NDR device608includes an electrode702, an electrode706, and an oxide704between the electrodes702and706. The oxide704can be made from various materials, including vanadium oxide materials, iron oxide materials, niobium oxide materials, titanium oxide materials, manganese oxide materials, and the like. The electrodes702and706can be mode from various conductive materials, such as copper, gold, aluminum, and the like. The metal-oxide-metal structure of the NDR device608can exhibit negative resistance with the application of a current to the metal-oxide-metal device. Negative resistance occurs when electric current is injected between the electrodes702and706, which locally heats the oxide704above a transition temperature. The transition temperature is the temperature at which a solid material changes from one crystal state to another. This rise above the transition temperature causes current filamentation to occur. Current filamentation is an inhomogeneity in the current density distribution orthogonal to the direction of current flow. This current filamentation is what causes the negative resistance at certain current levels.

Returning toFIG. 6, the bias circuits602, the conductive interconnect604, and the chaotic oscillator circuits606can be connected and formed on the semiconductor device600to operate according to the circuit100shown inFIG. 1. The semiconductor device600can also include logic608forming a random number generator circuit. The bias circuits602, the conductive interconnect604, the chaotic oscillator circuits606, and the logic608can be connected and formed on the semiconductor device600to operate according to the circuit500shown inFIG. 5.

The chaotic oscillator606can be fabricated using a complementary metal oxide semiconductor (CMOS) compatible process. Accordingly, the chaotic oscillator can be used to seed a random number generate at a microprocessor level (e.g., the chaotic oscillator can be formed on an integrated circuit along with the random number generator). The chaotic oscillator606can be relatively small in size compared to other types of hardware-based solutions and requires less power. In an example, the chaotic oscillator606includes conductive interconnect, a metal-oxide-metal device, and a capacitor. Classical CMOS circuits for producing random numbers can be large and require a substantial amount of feedback, which limits the speed and increases power consumption. Classical optical and quantum based circuits are incompatible with standard CMOS processes, and require their own separate packages and overhead.