Switching converter with power level selection

A converter and a method of operating a switching converter in a low power mode are presented. The invention relates to a III/V semiconductor switching converter. A switching converter contains a first power switch coupled to a second power switch via a switching node. There is an inductor coupled to the switching node, and a clamp circuit containing a third power switch is coupled in parallel to the first power switch. The switching converter is adapted to turn the first power switch off and to enable control of the third power switch upon identifying that the switching converter provides a low level of power.

TECHNICAL FIELD

The present disclosure relates to a low power switching converter and a method of operating a switching converter in a low power mode. In particular, the present disclosure relates to a III/V semiconductor switching converter.

BACKGROUND

Transistors based on III/V semiconductors such as Gallium Nitride, GaN, display a relatively low on-resistance and can achieve higher switching speed compared to their silicon-based counterpart. As such, GaN transistors are well suited for the design of fast power switching converters. However, current GaN-based switching converters are not suitable for low-power applications.

It is an object of the disclosure to address one or more of the above-mentioned limitations.

SUMMARY

According to a first aspect of the disclosure, there is provided a switching converter comprising: a first power switch coupled to a second power switch via a switching node; an inductor coupled to the switching node; and a clamp circuit comprising a third power switch coupled in parallel to the first power switch; the switching converter being adapted to turn the first power switch off and to enable control of the third power switch upon identifying that the switching converter provides a low level of power.

For example, the first power switch may be a high-side power switch and the second power switch may be a low-side power switch. A low level of power may be a level of power that is less than a reference power value. The reference power value may be set as minimum power value which may be a percentage of a normal power of the switching converter. Alternatively, the minimum value may be defined by a minimum amount of power required to operate a driver operating the first power switch.

Optionally, the switching converter may comprise a controller coupled to the clamp circuit, the controller being adapted to sense an electrical parameter of the switching converter; and to compare the electrical parameter with a threshold value to identify the level of power of the switching converter.

For example, the electrical parameter may be a parameter associated with a level power provided by the converter. Such a parameter may include one or more of the output power, the output voltage, the load current and the duty cycle of the switching converter.

Optionally, the third power switch may be coupled to a capacitor, the clamp circuit being adapted to turn off the third power switch when the second power switch is turned on, to charge the inductor; and to turn on the third power switch when the second power switch is turned off, to charge the capacitor.

Optionally, the third power switch comprises a power transistor having a first terminal coupled to a ground via a ground isolation switch, a second terminal coupled to the switching node; and a third terminal coupled to the capacitor.

Optionally, the clamp circuit comprises a control switch coupled in parallel between the first and the second terminal of the third power switch.

Optionally, the clamp circuit comprises a Zener diode coupled in parallel with the control switch. The Zener diode may be a III/V semiconductor based Zener diode. For instance, the Zener diode may be implemented by three GaN diodes coupled in series.

Optionally, the clamp circuit comprises a resistor coupled in parallel between the first terminal and the third terminal of the third power switch. The resistor may be a III/V semiconductor based resistor such as a GaN resistor.

Optionally, the third power switch may be an enhancement mode power switch.

Optionally, the clamp circuit comprises a filter coupled in parallel to the control switch.

Optionally, at least one of the first power switch, the second power switch and the third power switch is a III/V semiconductor based transistor. For example, the III/V semiconductor may be a GaN semiconductor.

According to a second aspect of the disclosure, there is provided a method of operating a switching converter comprising a first power switch coupled to a second power switch via a switching node, an inductor coupled to the switching node and a capacitor; the method comprising providing a third power switch coupled in parallel to the first power switch; and upon identifying that the switching converter provides a low level of power, turning the first power switch off, and enabling control of the third power switch.

Optionally, the method comprises sensing an electrical parameter of the switching converter; and comparing the electrical parameter with a threshold value.

Optionally, the method comprises turning off the third power switch when the second power switch is turned on to charge the inductor; and turning on the third power switch when the second power switch is turned off to charge the capacitor.

Optionally, turning off the third switch comprises lowering a gate voltage of the third switch.

According to a third aspect of the disclosure, there is provided a clamp circuit for use with a half bridge, the clamp circuit comprising a power switch having a first terminal for coupling to a ground, a second terminal for coupling to a switching node; and a third terminal for coupling to a capacitor.

Optionally, the clamp circuit comprises a control switch coupled in parallel between the first and the second terminal of the power switch.

Optionally, the clamp circuit comprises a Zener diode coupled in parallel with the control switch.

Optionally, the clamp circuit comprises a resistor coupled in parallel between the first terminal and the third terminal of the power switch.

Optionally, the power switch may be an enhancement mode power switch.

Optionally, the clamp circuit comprises a filter coupled in parallel to the control switch.

Optionally, at least one of the power switch, the resistor and the Zener diode is a III/V semiconductor based component. For example, the III/V semiconductor may be a GaN semiconductor.

DESCRIPTION

FIG. 1illustrates a conventional fly-back power converter100for providing an output voltage to a load140. The circuit100includes a so-called half-bridge formed by a high side power switch105coupled to a low side power switch110via a switching node LX. The high side power switch105has a first terminal coupled to an input voltage Vbus via a capacitor Csnub115, a second terminal coupled to the switching node, and a third terminal coupled to a high side driver120. The high-side driver120includes a boot capacitor Cboot122for powering the high-side driver. The boot capacitor122is coupled at one end to a voltage Vdd via a diode, and at another end to a ground via the low side power switch110. Control circuitry is provided to control the gate voltage of the high side switch105.

The low side power switch110has a first terminal coupled to the switching node LX, a second terminal coupled to the ground and a third terminal coupled to a low side driver, not shown, for operating the low side power switch. A transformer has a primary winding132coupled to a secondary winding134. The primary winding132is coupled at one end to the switching node LX and at another end to the capacitor Csnub115. The secondary winding134is coupled in parallel to an output capacitor136. A diode138is provided between the secondary winding134and the output capacitor138.

In operation, the low side switch110also referred to as main switch is turned on and off alternatively. When the low side power switch110is closed, the primary winding is connected to the input voltage Vbus. The current in the primary winding132increases and a voltage induced in the secondary winding134is negative. As a result, the diode138is reverse-biased and energy is provided to the load140by the output capacitor136. When the low side power switch110is open, the primary winding132is disconnect from the ground and cannot charge. The current in the primary winding132decreases and a voltage induced in the secondary winding134is positive. The diode138is forward-biased, allowing the transformer to provide energy to both the load140and to the output capacitor136, hence recharging it.

The capacitor Csnub115in parallel with the primary winding132, provides a circuit also referred to as passive snubber circuit for suppressing voltage overshoots. These overshoots can be caused by the leakage inductance of the transformer when the high side and low side power switches are operated. Such a passive snubber circuit however dissipates energy and therefore decreases the efficiency of the converter. To reduce power losses in the snubber circuit, the high side power switch105is used as an active clamp. The high-side driver120is powered by the boot capacitor Cboot122. The boot capacitor122can only charge up when the low-side power switch110is turned on (closed). However, in a low-power mode, the on-time of the low-side power switch110only last for a relatively short time. As a result, the boot capacitor122cannot charge sufficiently to provides enough power to operate the high-side driver120reliably.

If the switching converter100were to be designed using GaN technology, it would require even more energy. Since GaN technology does not provide p-channel devices, such as p-channel transistors, the power converter would need to be designed using n-channel devices. Such n-channel transistors operate in enhancement mode HEMT and therefore require a significant amount of power.

FIG. 2is a flow chart of a method of operating a switching converter comprising a first power switch coupled to a second power switch via a switching node; an inductor coupled to the switching node, and a capacitor.

At step210, a third power switch, also referred to as clamp switch, is provided. The third power switch is coupled in parallel to the first power switch.

At step220, the first power switch is turned off, and control of the third power switch is enabled upon identifying that the switching converter provides a low level of power. Identifying that the switching converter is operating in a low power mode may be achieved by sensing an electrical parameter of the switching converter. For example, the electrical parameter may be a parameter associated with a level power provided by the converter. Such a parameter may include one or more of the output power, the output voltage, the load current and the duty cycle of the switching converter. The electrical parameter may then be compared with a threshold value. For example, the threshold value may correspond to a minimum amount of power provided by the switching regulator. Such a minimum amount of power may be defined by a percentage, for instance less than 1% or less than 5%, of the power provided by the switching regulator in a normal mode of operation. For example, if the switching converter provides about 100 Watts in a normal mode then a low power mode may be identified when the switching regulator provides less than 5 Watts. Such a threshold value may depend on the type of converter being used and on the application. The threshold value may also correspond to a minimum load current or a maximum output voltage of the switching converter. For example, a low power mode of operation may be identified when the output voltage increases beyond the maximum output voltage value.

Alternatively, the threshold value may be defined by the minimum amount of power required to operate the high-side driver reliably. As explained above, this depends on the on-time of the low-side power switch.

At step230, the third power switch is turned off when the second power switch is turned on, to charge the inductor.

At step240, the third power switch is turned on, when the second power switch is turned off, to charge the capacitor.

FIG. 3is a diagram of a power converter300for use in a low power mode. In this example, the power converter300is a fly-back converter provided with an active-clamp circuit350, also referred to as low-power active-clamp circuit, which can be used when there is very little or no load applied to the switching converter.

The circuit300includes a high side power switch305coupled to a low side power switch310via a switching node LX. The high side power switch305has a first terminal coupled to an input voltage Vbus via a capacitor C1315, a second terminal coupled to the switching node, and a third terminal coupled to a high side driver320. In this example, the high-side driver320is identical to the high-side driver described with respect toFIG. 1. The high-side driver320includes a boot capacitor Cboot322for powering the high-side driver. The low side power switch310has a first terminal coupled to the switching node LX, a second terminal coupled to the ground and a third terminal coupled to a low side driver, for operating the low side power switch.

A transformer has a primary winding332coupled to a secondary winding334. The primary winding332is coupled at one end to the switching node LX and at another end to the capacitor C1315. A discrete leakage inductor is shown to represent the energy leakage of the primary coil332, which as part of any real transformer experiences coupling losses. The secondary winding334is coupled in parallel to an output capacitor336. A diode338is provided between the secondary winding334and the output capacitor336.

The clamp circuit350comprises a power switch352, also referred to as low-power switch LPSW, coupled in parallel to the high-side power switch305. For example, the low-power switch352may be an enhancement mode transistor such as a GaN transistor. The low-power switch352has a first terminal, for example a drain terminal coupled to the capacitor C1, a second terminal, for example a source terminal coupled to the switching node LX, and a third terminal, for example a gate terminal coupled to a ground via another switch, referred to as isolation switch360, for controlling isolation of the low-power switch gate from the ground. An optional current sink362may be provided between the isolation switch360and the ground. The current sink362may be used to limit the current and therefore avoid overstressing the clamp circuit350.

A resistance R1354is provided in parallel between the first terminal and the third terminal of the low-power switch352. The resistor R1354may be implemented in GaN technology. In this case the resistance may display two-dimensional electron gas (2DEG) properties.

A Zener diode D1,356, is provided in parallel between the second terminal and the third terminal of the low-power switch352, hence clamping the gate voltage of the LPSW. For example, the Zener diode356can be implemented in GaN technology by three GaN diodes in series.

An additional switch, also referred to as disconnection switch Q1358is provided in parallel between the second terminal and the third terminal of the low-power switch. The disconnection switch358is provided to prevent self-activation of the low power switch352in a so-called normal operation mode.

Optionally, a filter, also referred to as gate protection filter359, may be provided in parallel with the Zener diode. For example, the filter may be an RC filter. In this example, the filter359is provided by a capacitor C2provided in parallel with the Zener diode356and a resistor R2having a first terminal coupled to D1356and a second terminal coupled to C2.

A controller370is provided for generating a set of logic signals for driving the high side power switch305, the low side power switch310, the disconnection switch358and the isolation switch360. The controller has multiple inputs for receiving a plurality of sensing signals. For instance, the controller can have a first input for receiving a current sensing signal of the current through the primary inductor, a second input for receiving a signal at the switching node such as a voltage at LX, and a third input for receiving an output signal such as the output voltage Vout of converter. The current through the primary winding332may be sensed via the low side switch310. Optionally, the controller370may also receive a sensing signal of the input voltage Vbus. The controller370may be a CMOS controller allowing to control the low-side power switch310without significant power losses during standby.

The switching converter300may use GaN based devices, such as GaN diodes, GaN resistances and GaN transistors. The switching converter300may also be implemented using both Si and GaN technologies. This may be achieved using different chips for GaN and Si components, and then combining these chips within a package, also referred to as system in package or SIP.

FIG. 4is a timing diagram showing the state, open or closed, of the different switches used in the power converter ofFIG. 3. The time diagram includes the states labelled410,420,430,440and450of the low-side power switch, the high-side power switch, the disconnection switch, the isolation switch, and the low-power switch respectively.

At time t0the switching converter operates in a so called normal mode. Such a mode of operation may be identified by the controller370based on a plurality of sensing values. The disconnection switch358is on (closed)430, hence disconnecting the low-power switch352, which remains off (open)450. When, the low-side power switch310is on, the high-side power switch is off. The high side power switch switches on a short time after the low side power switch is turned off. This short delay is referred to as dead time.

At time t1, the switching converter starts operating in a so called low-power mode. The low power level of the switching converter may be identified by the controller370. The high-side switch305is turned off420. The disconnection switch Q1turns off (Vgs=0)430, therefore enabling the gate control of the low-power switch352.

At time t2, the isolation switch360turns on440. Since the Zener diode D1356is forward biased, a current flows from LX to the ground via the isolation switch, hence disabling the low-power switch352. This avoids turning on the LPSW via the resistance R1during the on-time of the low-side power switch310.

Shortly after, at time t3, the low-side power switch310turns on410and the primary winding332charges. The on-time of the low-side power switch310defines the amount of energy stored in the primary winding332.FIG. 3shows a primary inductor current I1flowing through inductor332.

At time t4, both the low-side power switch310and the isolation switch360turn off. The primary inductor current I1is interrupted, the primary inductor332stops charging, and the voltage at node LX increases. An inductor current I2starts from the inductor332towards the capacitor C1in reverse conduction mode, hence charging the capacitor C1. This increases the drain voltage as well as the gate voltage of the LPSW352.

At time t5, the gate to source voltage Vgs of the low-power switch352is sufficient (Vgs>Vth) to turns the low power switch on450. When LPSW352is turned on, the energy stored in C1causes a current I2to flow from C1via the LPSW (forward mode) to charge the primary inductor LP. The LPSW352will remain switched on, as long as there is enough energy in the capacitor C1to maintain Vgs>Vth. Depending on the value of R1, the gate voltage of LPSW352will discharge via the low resistive drain-source path of the LPSW352until LPSW turns off. By choosing a resistance R1, that is relatively large it is possible to reach the desired gate voltage of the LPSW352quickly. For example, R1may have a value ranging from about 100KΩ to several MΩ. In addition, this allows to reduce power dissipation in R1. If R1is implemented in GaN technology, then R1will have high-ohmic values for high substrate voltages, due to the 2DEG properties of GaN resistors. The resistor R1will therefore have high-ohmic values when the voltage at the LX node is high.

The proposed active clamp circuit therefore provides a simple bidirectional and controllable path for the leakage energy present in the inductor of the switching converter. The leakage energy can be recycled and improve the efficiency of the switching converter. The low-power clamp circuit350does not depend on the high side driver320. The low power switch352is not charged by the boot capacitor322but by the capacitor C1315. As a result, the low-power clamp circuit352can operate even when the low-power switch on-time is very short. As a result, the switching converter can operate reliably even when the load is relatively low. The power consumption of the clamp circuit350depends mainly on the on-time of the isolation switch360. Since in a low-power mode the duty cycle is low, the power losses in the clamp circuit can be considered negligible.

FIG. 5shows a diagram of another power converter500. In this example, the power converter500is a boost converter provided with an active clamp circuit. The circuit ofFIG. 5shares common features with the circuit ofFIG. 3above, with like elements being indicated by like reference numbers. In particular, the power converter500includes a clamp circuit identical to the clamp circuit350described above.

The boost converter500includes an inductor532and an output capacitor Cout536. The inductor532has a first terminal coupled to an input voltage Vbus and another terminal coupled to the switching node LX. The low-power switch352of the clamp circuit350has a first terminal, for example a drain terminal coupled to the output capacitor Cout536, a second terminal, for example a source terminal coupled to the switching node LX, and a third terminal, for example a gate terminal coupled to a ground via another switch, referred to as isolation switch360, for controlling isolation of the low-power switch gate from the ground.

In operation, when the controller370identifies a low power, the high-side switch305is turned off. The disconnection switch Q1turns off, therefore enabling the gate control of the low-power switch352.

A short time before the low side switch310turns on, the isolation switch360turns on and disables the low-power switch352. When the low-side power switch310turns on the inductor532starts charging. The on-time of the low-side power switch310defines the amount of energy stored in the inductor532.FIG. 5shows an inductor current I1′ flowing through inductor532.

When both the low-side power switch310and the isolation switch360turn off, the inductor532stops charging, and the voltage at node LX increases. When the gate to source voltage Vgs of the low-power switch352is sufficient (Vgs>Vth) the low power switch352turns on. An inductor current I2′ starts flowing from the inductor532towards the capacitor Cout536in reverse conduction mode, hence charging the capacitor Cout. As the inductor discharges into the capacitor Cout, the voltage at node LX starts decreasing, and eventually the LPSW352turns off.

A skilled person will appreciate that variations of the disclosed arrangements are possible without departing from the disclosure. The active-clamp circuit described above is not limited to fly-back or boost topology and could be applied to any other type of switching converter using a half-bridge configuration. For example, the active-clamp circuit could be used with a buck converter, or a buck-boost converter. Accordingly, the above description of the specific embodiment is made by way of example only and not for the purposes of limitation. It will be clear to the skilled person that minor modifications may be made without significant changes to the operation described.