Packaged leadless semiconductor device

A packaged leadless semiconductor device (20) includes a heat sink flange (24) to which semiconductor dies (26) are coupled using a high temperature die attach process. The semiconductor device (20) further includes a frame structure (28) pre-formed with bent terminal pads (44). The frame structure (28) is combined with the flange (24) so that a lower surface (36) of the flange (24) and a lower section (54) of each terminal pad (44) are in coplanar alignment, and so that an upper section (52) of each terminal pad (44) overlies the flange (24). Interconnects (30) interconnect the die (26) with the upper section (52) of the terminal pad (44). An encapsulant (32) encases the frame structure (28), flange (24), die (26), and interconnects (30) with the lower section (54) of each terminal pad (44) and the lower surface (36) of the flange (24) remaining exposed from the encapsulant (32).

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to semiconductor devices. More specifically, the present invention relates to leadless semiconductor devices.

BACKGROUND OF THE INVENTION

Semiconductor chips or dies (also typically referred to in plural as dice or die) are typically encapsulated in a semiconductor package for protection from damage by external stresses and to provide a system for carrying electrical signals to and from the chips. Many different types of semiconductor packages exist including dual-in-line packages, pin grid array packages, tape-automated bonding (TAB) packages, multi-chip modules (MCMs), and power packages. One type of power package is used for a high power semiconductor device that is capable of dissipating, for example, greater than thirty watts of power. Such a power package may be utilized in, for example, a radiofrequency application.

DETAILED DESCRIPTION

There is an increasing trend to surface mount high power, e.g., greater than thirty watt, radiofrequency semiconductor devices directly onto circuit boards with embedded copper for grounding and thermal mounting. Such a surface mount technique may help to lower costs through standardized surface mount manufacturing processes. Presently, the leads of such surface mount packages are formed in a gull wing configuration that extend from the exterior sidewalls of the packaged semiconductor device and are bent in order to make contact with an underlying printed circuit board when surface mounted. Unfortunately, for high frequency applications, e.g., greater than three hundred megahertz (MHz), inductance in the gull wing leads lowers the system performance. Moreover, for high power applications, power distribution on the semiconductor device typically calls for a grid of power and ground lines to run across the device. This grid of power and ground lines further increases the line inductance causing unacceptable noise and further lowering system performance.

Leadless surface mount techniques are evolving to circumvent the problems associated with high inductance of the gull wing leads. In a leadless semiconductor device, a leadframe typically includes a die flange or paddle and terminal pads surrounding the die flange. One or more semiconductor dies are attached using, for example, epoxy or high temperature solder to the die flange, and the terminal pads are electrically interconnected with the semiconductor die or dies using a wire bonding process. These terminal pads are formed coplanar with the device backside in order to make contact with an underlying printed circuit board when surface mounted.

For high power applications, it is desirable to surface mount the one or more semiconductor dies of a semiconductor device using a robust, highly reliable die attach process, for example, a high temperature metallurgical bonding process such as gold-silicon bonding, gold-tin bonding, silver bonding, and so forth. Unfortunately, a high temperature bonding process is not a suitable for typical leadless surface mount packages containing multiple dies because the high temperature can cause warping of or otherwise damage the leadframe.

Embodiments described herein entail a leadless semiconductor device for high power applications and an assembly process for packaging the leadless semiconductor device. The semiconductor device includes a relatively thick heat sink flange and a separate frame structure. The frame structure is pre-formed with bent terminal pads. The semiconductor dies can be attached to the heat sink flange using a high temperature die attach process. The frame structure can subsequently be combined with the heat sink flange so that the lower surface of the heat sink flange and a portion of the terminal pads are in coplanar alignment. The structure can then be encapsulated in an encapsulant (such as a plastic material) so that the lower surface of the heat sink flange and the terminal pads remain exposed from the encapsulant.

Such a technique facilitates packaging flexibility and achieves improvements in wire bond quality. Furthermore, flatness of the packaged semiconductor device and coplanarity of the elements is maintained due to the relatively thick heat sink flange. Accordingly, a lower package with enhanced performance and improved reliability can be achieved for high power radiofrequency applications.

Referring toFIGS. 1-3,FIG. 1shows a top perspective view of a semiconductor device20in accordance with an embodiment.FIG. 2shows a bottom perspective view of semiconductor device20, andFIG. 3shows a cross-sectional view of semiconductor device20. In general, semiconductor device20includes a heat sink flange24, one or more semiconductor dies26, a frame structure28, and bond wires30. Semiconductor device20is a leadless surface mount package in which the components of semiconductor device20are substantially encased in an encapsulant32, such as a molding compound encapsulant.

For clarity of illustration, different shading and/or hatching is utilized in the following illustrations to distinguish the different elements of semiconductor device20. In addition, a term “horizontal” may be used herein to define a plane parallel to the plane or surface of the semiconductor device20, regardless of its orientation. Thus, a term “vertical” refers to a direction perpendicular to the horizontal as defined. Terms, such as “above,” “below,” “top,” “bottom,” “side” (as in “sidewall”), “upper,” “lower,” and so forth are defined with respect to the horizontal plane.

Heat sink flange24has an upper surface34and a lower surface36spaced apart from upper surface34by a flange thickness38. Heat sink flange24may be thermally and electrically conductive copper or a copper laminate material. One or more semiconductor dies26are coupled to upper surface34of heat sink flange24. In an embodiment, semiconductor dies26may be high power, e.g., greater than thirty watt, radiofrequency semiconductor dies that are attached to upper surface34of heat sink flange24using a high temperature bonding process, such as a gold-silicon eutectic bonding die attach process. In such an embodiment, flange thickness38of heat sink flange24may be of suitable thickness, for example, at least thirty mils, in order to withstand the high temperatures (e.g., greater than four hundred degree Celsius) needed for gold-silicon eutectic bonding without damage.

Frame structure28has a perimeter40(best seen inFIG. 7) defining a cavity42in which heat sink flange24resides. Frame structure28further includes terminal pads44surrounding at least a portion of cavity42. In an embodiment, each of terminal pads44is a folded arrangement having a first section46, a second section48, and a connector section50interconnecting first and second sections46and48, respectively. As shown, second section48is arranged approximately parallel to first section46, and is outwardly laterally displaced away from heat sink flange24relative to first section46.

A top side of first section46includes a surface, referred to herein as an upper surface52, and an underside of second section48includes another surface, referred to herein as a lower surface54. Upper and lower surfaces52and54are spaced apart by a distance56that is greater than flange thickness38of heat sink flange24. Thus, heat sink flange24is positioned in cavity42such that lower surface36of heat sink flange24and lower surface54of each of terminal pads44are in coplanar alignment on an underside58of semiconductor device20. Additionally, lower surface36of heat sink flange24and lower surface54of each of terminal pads44remain exposed from molding compound32.

At least a portion of upper surface52of each of terminal pads44overlies upper surface34of heat sink flange24. Additionally, first section46is spaced apart from upper surface34of heat sink flange24by a gap60. Connector section50is oriented approximately perpendicular to first and second sections46and48, respectively, and is spaced apart from lateral sidewalls62of heat sink flange24by another gap64. The shape of terminal pads44and location of at least a portion of upper surface52of first section46overlying upper surface34of heat sink flange24enables bond wires30to be formed that are shorter than in prior art devices. Accordingly, lead inductance is lowered relative to prior art devices, thereby increasing system performance.

For simplicity of illustration, semiconductor device20is presented inFIG. 3and some ensuing illustrations with bond wires30that appear sharply bent or kinked. Those skilled in the art will readily recognize that in practice bond wires30are not typically sharply bent, but are, instead, more likely to be curved or rounded. In addition, semiconductor device20is illustrated with two terminal pads44positioned on opposing sides of cavity42. In alternative embodiments, frame structure28may include multiple terminal pads44at the two opposing sides of cavity42and/or multiple terminal pads44at one side of cavity42or any of multiple sides of cavity42.

In an embodiment, gaps60and64may be filled with an electrically insulating dielectric material66such as, for example, a plastic material, glass, porcelain, and the like. Dielectric material66may be bonded between heat sink flange24and frame structure28prior to wire bonding. Dielectric material66is an electrical insulator that can be polarized by an applied electric field. Polarization of dielectric material66by the applied electric field can increase the capacitance between heat sink flange24and frame structure28to further enhance system performance.

Semiconductor dies26include die bond pads68. Die bond pads68are electrically interconnected with upper surface52of terminal pads44in accordance with a particular design configuration by bond wires30using, for example, a wire bonding process. Such bond wires30and wire bonding processes are known by those skilled in the art. In an embodiment two mil gold wires may be utilized, and in another embodiment, ten mil aluminum wires may be used. However, various known wires of varying materials and diameters may be utilized in accordance with particular design requirements.

As mentioned briefly above, semiconductor device20includes molding compound encapsulant30that substantially encases the entirety of frame structure28, heat sink flange24, semiconductor dies26, and bond wires30. However, lower surface36of heat sink flange24and lower surface54of each of terminal pads44remain exposed. The exposed lower surface36and lower surfaces54are used to connect semiconductor device20to other devices, such as a printed circuit board (not shown). Accordingly, in addition to terminal pads44, the exposed lower surface36may be a source terminal, e.g., ground, for semiconductor dies26in some embodiments. In addition, or alternatively, the exposed lower surface36allows heat to dissipate from heat sink flange24, and hence semiconductor dies26.

Molding compound encapsulant32may comprise a plastic material or other molding materials as is commonly used in packaged electronic devices and is formed over frame structure28, heat sink flange24, semiconductor dies26, and bond wires30during a conventional overmolding process.

Portions of frame structure28such as connector section50and first section46may include notches70. In this embodiment, notches70extend only partially through the material thickness of frame structure28. However, in alternative embodiments, notches70may extend through an entirety of the material thickness of frame structure28. When semiconductor device20is overmolded, encapsulant30fills notches70to secure molding compound encapsulant30to frame structure28so that semiconductor device20is less likely to delaminate, or separate. In addition, or alternatively, heat sink flange24may include lock features72, such as notches, grooves, extended regions, and so forth. Encapsulant30fills or otherwise bonds with these lock features72to secure molding compound encapsulant30to frame structure28so that semiconductor device20is less likely to delaminate.

Now referring toFIG. 4,FIG. 4shows a flowchart of a semiconductor device assembly process74in accordance with another embodiment. In general, process74includes operations for assembling semiconductor device20.

Semiconductor device assembly process74begins with a task76. At task76, heat sink flange24is provided. Referring toFIG. 5in connection with task76,FIG. 5shows a perspective view of heat sink flange24of semiconductor device20provided at an initial stage of assembly in accordance with task76of assembly process74. It should be recalled that in an embodiment, flange thickness38of heat sink flange24is at least thirty mils (762 microns). Heat sink flange24may include one or more lock features72extending inwardly from lateral sidewalls62. Lock features72may additionally be formed in upper surface34or additionally or alternatively in lower surface36of heat sink flange24as shown inFIG. 3.

Heat sink flange24may be formed from copper or a copper laminate material for effective heat dissipation. Only one heat sink flange24is shown for simplicity of illustration. In some embodiments, heat sink flange24may be a single flange, or die paddle, in an array of interconnected heat sink flanges24(not shown), as known to those skilled in the art. Heat sink flange24is sized to accommodate one or more semiconductor dies (FIG. 3) in accordance with the particular design of semiconductor device20(FIG. 3). In this illustration, locations78on upper surface34of heat sink flange24at which semiconductor dies26are to be attached are demarcated by dashed lines. Locations78may be selectively plated to provide a portion of upper surface34of heat sink flange24suitable for a subsequent die attach operation.

Referring back toFIG. 4, following task76, assembly process74continues with a task80. At task80, semiconductor dies26are coupled to heat sink flange24. Referring toFIG. 6in connection with task80,FIG. 6shows a perspective view of heat sink flange24at a subsequent stage of assembly process74. As shown, a number of semiconductor dies26are coupled to upper surface34of heat sink flange24. In an embodiment, semiconductor dies26are coupled to heat sink flange24using a high temperature die attach process, such as gold-silicon eutectic bonding. Such a high temperature (e.g., greater than four hundred degrees Celsius) may effectively be accomplished due to flange thickness38of heat sink flange24in excess of thirty mils.

Referring back toFIG. 4, following task80, assembly process74continues with a task82. At task82, frame structure28is provided. Referring toFIG. 7in connection with task84,FIG. 7shows a perspective view of a frame structure panel84for frame structure28of semiconductor device20(FIG. 3) provided at a subsequent stage of assembly in accordance with assembly process74.

In the illustrative embodiment, frame structure panel84is an array of frame structures28. In this example, frame structure panel84is a 3×1 array of frame structures28. However, in practice, the arrays will generally be larger. Moreover, the array need not have a single row, or the same number of rows as columns.

Each of frame structures28within frame structure panel84includes perimeter40defining cavity42. As previously mentioned, each cavity42is sized and shaped to receive heat sink flange24(FIG. 3). In the embodiment shown, perimeter40of each frame structure28is defined, or circumscribed by tie bars86from which terminal pads44extend. Frame structure panel86has a predefined thickness that is less than flange thickness38(FIG. 1), for example, approximately eight mils. However, frame structure panel84is preformed such that each of terminal pads44is in the folded arrangement of first section46, second section48, and connector section50interconnecting first and second sections46and48, respectively.

Returning toFIG. 4, following task82, assembly process74continues with a task88. At task88, frame structure28is coupled with heat sink flange24such that flange24is positioned in cavity42of frame structure28. Referring toFIG. 8in connection with task88,FIG. 8shows a perspective view of frame structure panel84coupled with a number of heat sink flanges24at a subsequent stage of assembly in accordance with assembly process74. Individual heat sink flanges24may be positioned in cavities42of frame structures28. Heat sink flanges24can then be staked to, adhered to, or otherwise coupled to frame structures28. As an example, staking may be accomplished using a high precision mechanical staking process, laser joining process, or spot welding process. In an embodiment, a suitable coupling process is implemented to ensure that the frame structure panel84remains or is kept electrically insulated from heat sink flanges24.

It should be recalled that semiconductor dies26were previously bonded to heat sink flanges24. Thus, semiconductor dies26are resident on heat sink flanges24when flanges24are coupled to frame structures28. Although heat sink flanges24are illustrated as being individual elements, heat sink flanges24may be provided as a corresponding array of flanges24that mates with frame structure panel84.

With reference back toFIG. 4, assembly process74continues with a task90following task88. At task90, additional measures may be taken to ensure that frame structure28is electrically isolated from heat sink flange24. By way of example, dielectric material66(FIG. 3) may be bonded in gaps60and64(FIG. 3) between frame structure28and heat sink flange24. In an alternative embodiment, an insulator frame suitable for inclusion with a cap may be formed to ensure electrical isolation. The insulator frame and cap configuration will be discussed below in connection withFIGS. 11 and 12.

Following task90, a task92is performed. At task92, semiconductor dies26coupled to heat sink flange28are electrically interconnected with terminal pads44using bond wires30. Referring toFIG. 9in connection with task92,FIG. 9shows an enlarged perspective view of heat sink flange24and frame structure28at a subsequent stage of assembly in accordance with the assembly process74.FIG. 9depicts only one heat sink flange24and frame structure28for simplicity of illustration. It should be understood, however, that bond wires30may be formed in a batch mode assembly processes while frame structure28is interconnected with other frame structure28of frame structure panel84(FIG. 7). Since upper surface52of terminal pads44within frame structure28overlie at least a portion of heat sink flange24, bond wires30between semiconductor dies26and terminal pads44are shorter than in prior art configurations thereby decreasing system inductance and enhancing system performance.

In this example, the electrical interconnections, e.g., bond wires30, are formed utilizing a wire bonding process. The electrical interconnections are formed between various semiconductor dies26coupled to heat sink flange24and/or between semiconductor dies26and terminal pads44in accordance with a particular semiconductor device design. Although wire bonding is mentioned herein, electrical interconnections may be formed in alternative embodiments using, for example, tape automated bonding (TAB), ribbon bonding, or any other suitable existing or developing technique for forming the electrical interconnections.

Referring back toFIG. 4, following task92, semiconductor device assembly process74continues with a task94. At task94, the assembly that includes heat sink flange24, frame structure28, semiconductor dies26, and bond wires30is encased in an encapsulant. In this embodiment, the assembly is overmolded using molding compound encapsulant32. Referring toFIG. 10in connection with task94,FIG. 10shows a perspective view of semiconductor devices20at a subsequent stage of assembly in accordance with the assembly process74.

Molding compound encapsulant32may be a glass-filled epoxy-based plastic that is overmolded over substantially an entirety of heat sink flange24, frame structure28, semiconductor dies26, and bond wires30. Notches70(FIG. 3) and/or lock features72(FIG. 3) can serve as mold locks to improve the adhesion of molding compound encapsulant32to frame structure28(FIG. 3) and heat sink flange24(FIG. 3). However, lower surface36(FIG. 3) and lower surface54(FIG. 3) of each of terminal pads44remain exposed from molding compound encapsulant32to form the leadless interconnects for semiconductor device20. Molding compound encapsulant32provides protection from environmental conditions for the components of device20. Additionally, molding compound encapsulant32reinforces or improves the strength and durability of semiconductor device20.

Following task94, assembly process74continues with a task96. At task96, terminal pads44(FIG. 3) of frame structure28are singulated. More particularly, tie bars86(FIG. 10) are cut or otherwise removed, so that terminal pads44are isolated from one another. Following task96, multiple leadless surface mount semiconductor devices20are produced. Ellipses following task96represent subsequent operations that may be performed on semiconductor devices20, such as inspection, testing, cleaning, and so forth.

Referring now toFIGS. 11 and 12,FIG. 11shows a perspective view of heat sink flange24and frame structure28in accordance with an alternative embodiment, andFIG. 12shows a perspective view of a cap98utilized in accordance with the alternative embodiment. Semiconductor device20(FIG. 1) and semiconductor device assembly process74(FIG. 4) are described in connection with an overmolded configuration. In some situations, it may be preferential to provide an air cavity in which semiconductor dies26reside. Thus, assembly process74is readily adapted to provide a capped semiconductor device structure.

In particular, at task90(FIG. 4) of assembly process74(FIG. 4), frame structure28is electrically isolated from heat sink flange24. In an embodiment, an insulator frame100may be formed surrounding frame structure28and heat sink flange prior to wire bonding. Insulator frame100may be formed from, for example, a molding compound102that is allowed to encapsulate a portion of each of heat sink flange24and frame structure28. However, upper surface34of heat sink flange24and semiconductor dies26remain exposed from molding compound102. Additionally, upper surface52of each of terminal pads44remain exposed from molding compound102. Like semiconductor device20, lower surface36(FIG. 3) of heat sink flange24and lower surface54of each of terminal pads44also remain exposed from molding compound102.

Following electrically interconnecting terminal pads44with semiconductor dies26, as discussed above, cap98is coupled to insulator frame100using adhesive, laser bonding, or any other suitable technique such that semiconductor dies26, bond wires30(FIG. 3), and terminal pads44reside in an interior volume104of cap98.

FIG. 13shows a cross-sectional view of a semiconductor device106in accordance with another alternative embodiment. Like semiconductor device20, semiconductor device106includes frame structure28and one or more semiconductor dies26suitably interconnected by bond wires30. Frame structure28includes terminal pads44arranged in the folded arrangement with first section46, second section48, and connector section50interconnecting first and second sections46and48, respectively. Semiconductor device106may be assembled in accordance with semiconductor device assembly process74(FIG. 4) as discussed in detail above.

In accordance with this alternative embodiment, semiconductor device106includes a heat sink flange108having a peripheral portion110and a central portion112at least partially surrounded by peripheral portion110. Each of portions110and112includes an upper surface114and a lower surface116. Upper surface114of peripheral portion110is spaced apart from lower surface116by a flange thickness118. Likewise, upper surface114of central portion112is spaced apart from lower surface116by a flange thickness120that is greater than flange thickness118. Lower surface116of central portion112is coplanar with lower surface116of peripheral portion110. Thus, heat sink flange108represents a dual thickness heat sink flange configuration.

Semiconductor dies26may be coupled to upper surface114of the relatively thicker central portion112of heat sink flange108, and first surface52of each of terminal pads44may overlie the relatively thinner peripheral portion110of heat sink flange108. Flange thickness120of central portion112of heat sink flange108may be sufficiently thick (e.g., at least thirty mil) to effectively serve as a heat sink for semiconductor dies26. In addition, implementation of the relatively thinner peripheral portion110can result in decreased length of bond wires30and/or shorter overall length of connector section50of terminal pads44interconnecting first and second sections46and48. Accordingly, the dual thickness configuration of heat sink flange108enables the implementation of electrically conductive signal paths that may be made even shorter so as to further lower inductance, and thereby further increase system performance.

In summary, embodiments set forth herein entail a packaged leadless surface mount semiconductor device that may be used for high power applications and an assembly process for such a packaged device. The packaged semiconductor device includes a relatively thick heat sink flange and a separate frame structure. The frame structure is pre-formed with bent terminal pads. The semiconductor dies can be attached to the heat sink flange using a high temperature die attach process. The frame structure can subsequently be combined with the heat sink flange so that the lower surface of the heat sink flange and a lower surface of the terminal pads are in coplanar alignment, and so that an upper surface of the terminal pads overlies the heat sink flange. Electrical interconnects between the semiconductor dies and the upper section of the terminal pads are formed after the high temperature die attach process. The electrical interconnects are short due to the overlying configuration of the terminal pads so as to lower inductance, and thereby increase system performance. The structure can then be entirely encapsulated so that the lower surface of the heat sink flange and the lower surface of the terminal pads remain exposed from the encapsulant.

Although the preferred embodiments of the invention have been illustrated and described in detail, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims. That is, it should be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention.