Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

BACKGROUND

In a semiconductor device, current flows through a channel region between a source region and a drain region upon application of a sufficient voltage or bias to a gate of the device. When current flows through the channel region, the device is generally regarded as being in an ‘on’ state, and when current is not flowing through the channel region, the device is generally regarded as being in an ‘off’ state.

DETAILED DESCRIPTION

According to some embodiments, a semiconductor arrangement comprise a first active region, a second active region and a shallow trench isolation (STI) region, the STI region between the first active region and the second active region. According to some embodiments, a first metal connect is over the first active region and connected to the first active region. According to some embodiments, a second metal connect is over a second active region and connected to the second active region. In some embodiments, a third metal connect is over the first metal connect, the STI region and the second metal connect, and connected to the first metal connect and the second metal connect such that the third metal connect connects the first metal connect to the second metal connect. In some embodiments, the first active region is one of a source or a drain. In some embodiments, the second active region is one of a source or a drain. In some embodiments, the third metal connect connects at least one of a source of the first active region to a source of the second active region, a drain of the first active region to a drain of the second active region, or a source of the first active region to a drain of the second active region. In some embodiments, the third metal connect mitigates resistance-capacitance (RC) coupling because a distance between the third metal connect and a gate associated with the semiconductor arrangement is greater than a distance between the gate and a different metal connect that would otherwise be used to connect the first active region to the second active region, such as a different metal connect that is not over the first metal connect, the STI region and the second metal connect. In some embodiments, a reduced or minimized RC coupling between the gate and a metal connect, such as the third metal connect, that connects the first active region to the second active region results in at least one of reduced resistance-capacitance (RC) delay or better performance, wherein better performance comprises at least one of improved speed or operative predictability.

According to some embodiments, forming a semiconductor arrangement comprises forming a first opening over a first active region, a shallow trench isolation (STI) region and a second active region, such that the first opening is over a first metal connect in the first active region and is over a second metal connect in the second active region. According to some embodiments, a third metal connect is formed in the first opening such that the third metal connect connects the first metal connect to the second metal connect. In some embodiments, as second opening is formed over a gate in the STI region. In some embodiments, a metal contact is formed in the second opening. In some embodiments, the first opening and the second opening are formed concurrently. In some embodiments, the first metal connect has a third height and the second metal connect has a fourth height, the third height substantially equal to the fourth height. In some embodiments, the gate has fifth height, the fifth height substantially equal to the third height. In some embodiments, the third metal connect, which is over the first metal connect and the second metal connect, has a first height.

A method100of forming a semiconductor arrangement200according to some embodiments is illustrated inFIG. 1and one or more structures formed thereby at various stages of fabrication are illustrated inFIGS. 2-17. According to some embodiments, such as illustrated inFIG. 16, the semiconductor arrangement200comprises a first active region205, a second active region207and a shallow trench isolation (STI) region209, the STI region209between the first active region205and the second active region207. According to some embodiments, a first metal connect215is over the first active region205and connected to the first active region205. According to some embodiments, a second metal connect216is over the second active region207and connected to the second active region207. In some embodiments, a third metal connect218is over the first metal connect215, the STI region209and the second metal connect216, and connected to the first metal connect215and the second metal connect216, such that the third metal connect218connects the first metal connect215to the second metal connect216thereby connecting the first active region205to the second active region207.

Turning toFIG. 2an overview or top down view of the semiconductor arrangement200is illustrated according to some embodiments, where a second dielectric layer224illustrated inFIGS. 3-15is not shown inFIG. 2so that features underlying the second dielectric layer224are visible inFIG. 2. InFIG. 2four lines240,242,244and246are drawn to illustrate cross-sections that are depicted in other FIGS. A first line240cuts through the second active region207, multiple gates208, the second metal connect216and the third metal connect218, where the second active region207is a region where as at least one of a source or a drain are formed, according to some embodiments.FIG. 15is a cross sectional view of the semiconductor arrangement200taken along the first line240at a latter stage of fabrication. A second line242cuts through the STI region209, the multiple gates208, multiple metal contacts214and the third metal connect218, where the STI region209comprises STI220.FIGS. 3, 5, 7, 9, 11 and 13are cross sectional views of the semiconductor arrangement200taken along the second line242at various stages of fabrication. A third line244cuts through the first active region205, the multiple gates208, the first metal connect215and the third metal connect218, where the first active region205is a region where as at least one of a source or a drain are formed, according to some embodiments.FIGS. 4, 6, 8, 10, 12 and 14are cross sectional views of the semiconductor arrangement200taken along the third line244at various stages of fabrication. A fourth line246, cuts through the first metal connect215, the third metal connect218and the second metal connect216, according to some embodiments, where the third metal connect218is formed to connect the first active region205to the second active region207.FIG. 16is a cross sectional view of the semiconductor arrangement200taken along the fourth line246at a latter stage of fabrication.

At102, a second opening226is formed over a gate208in the STI region209, as illustrated inFIG. 5. Turning toFIG. 3, which illustrates a cross-section of the second line242ofFIG. 2, where the second line242cuts through the STI region209. The semiconductor arrangement200comprises a substrate202. In some embodiments, the substrate202comprises at least one of silicon oxide or silicon nitride. According to some embodiments, the substrate202comprises at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, an STI220is formed over the substrate202in the STI region209. In some embodiments, the STI220comprises a dielectric material, such as silicon oxide (SiO2). In some embodiments, the STI220formation comprises deposition of the dielectric material. In some embodiments, the STI region209comprises the STI220. In some embodiments, the STI220has a thickness between about 20 nm to about 70 nm. Turning toFIG. 4, which illustrates a cross-section of the third line244ofFIG. 2, where the third line244cuts through the first active region205. In some embodiments, one or more fins204are formed in the substrate202of the first active region205. In some embodiments, the one or more fins204comprise the same material as the substrate202. In some embodiments, the one or more fins204have a height between 5 nm to about 45 nm. In some embodiments, an epitaxial (Epi) cap206is formed over the one or more fins204. In some embodiments, the Epi cap206is grown. In some embodiments, the Epi cap206comprises at least one of silicon, nitride, or oxide. In some embodiments, the second active region207is formed substantially the same way as the first active region205. In some embodiments, a first dielectric layer212is formed, such as by deposition, over the STI220and the Epi cap206, as illustrated inFIGS. 3, 4 and 17. In some embodiments, the Epi cap206acomprises at least one of a source or a drain. In some embodiments, the Epi cap206bcomprises a source if the Epi cap206acomprises a drain, and the Epi cap206bcomprises a drain if the Epi cap206acomprises a source. In some embodiments, the first dielectric layer212comprises a standard dielectric material with a medium or low dielectric constant, such as SiO2. In some embodiments, the first dielectric layer212has thickness between about 20 nm to about 150 nm. In some embodiments, the gate208, or a plurality of gates208, as illustrated inFIGS. 3 and 4, are formed in the first dielectric layer212, such that the gate208is in contact with the Epi cap206of the first active region205and the Epi cap206of the second active region207and over the STI region209. In some embodiments, the gate208comprises a layer of high dielectric constant material in contact with the Epi cap206of the first active region205and the second active region207, as illustrated inFIGS. 4 and 17. In some embodiments, the high dielectric constant material comprises at least one of nitride or oxide. In some embodiments, the gate208comprises a conductive material, such as metal, formed, such as by deposition, over the high dielectric constant material. In some embodiments, a hard mask210is formed, such as by deposition, over the gate208. In some embodiments, the gate208has a fifth height225between about 20 nm to about 130 nm. In some embodiments, the hard mask210comprises oxide or nitride. In some embodiments, the first metal connect215is in contact with the Epi cap206bin the first active region205. In some embodiments, the Epi cap206ais in contact with the first metal connect215(not shown). In some embodiments, the first metal connect215comprises a conductive material such as at least one of metal or polysilicon. In some embodiments, the first metal connect215formation comprises deposition. In some embodiments, the first metal connect215has a third height221between about 30 nm to about 130 nm, as illustrated inFIG. 4. In some embodiments, the second metal connect216has a fourth height223, as illustrated inFIG. 15, substantially equal to the third height221. In some embodiments, the fifth height225of the gate208is substantially equal to the third height221. In some embodiments, an etch stop layer222is formed over the hard mask210, the first dielectric layer212and the first metal connect215, such as by deposition. In some embodiments, the etch stop layer222comprises at least one of silicon, nitride or oxide. In some embodiments, the second metal connect216is in contact with the Epi cap206bin the second active region207. In some embodiments, the second metal connect216is formed in substantially the same manner as the first metal connect215. In some embodiments, a second dielectric layer224is formed over the etch stop layer222. In some embodiments, the second dielectric layer224comprises a standard dielectric material with a medium or low dielectric constant, such as SiO2. In some embodiments, the second dielectric layer224has thickness between about 20 nm to about 150 nm. Turning toFIG. 5, the second opening226is formed, such as by etching, in the second dielectric layer224, the etch stop layer222, and the hard mask210, such that the second opening226exposes at least part of the gate208.

At104, a first opening228is formed over the first active region205, the STI region209and the second active region207, such that the first opening228is over the first metal connect215and the second metal connect216, as illustrated inFIGS. 7 and 8. In some embodiments, the first opening228is formed, such as by etching, through the second dielectric layer224and the etch stop layer222. In some embodiments, the first opening228is formed, such that in the first active region205and the second active region207the first opening228exposes at least a portion of the first metal connect215and at least a portion of the second metal connect216. In some embodiments, the first opening228is formed such that in the STI region209, the first opening228exposes at least part of the first dielectric layer212.

At106, the third metal connect218is formed in the first opening228and the metal contact214is formed into the second opening226, as illustrated inFIGS. 13-15. Turning toFIG. 9, a first metal layer230is formed in the first opening228and the second opening226. In some embodiments, the first metal layer230is formed by deposition. In some embodiments, the first metal layer230comprises titanium. In some embodiments, the first metal layer230has a thickness of 1 nm to about 10 nm. In some embodiments, the first metal layer230in the second opening226is in contact with the gate208, as illustrated inFIG. 9. In some embodiments, the first metal layer230in the first opening228is in contact with the first metal connect215in the first active region205, as illustrated inFIG. 10, and the second metal connect216in the second active region206, as illustrated inFIG. 15. Turning toFIGS. 11-12, which illustrates a second metal layer232formed over the first metal layer230in the first opening228and over the first metal layer230in the second opening226. In some embodiments, the second metal layer232is formed by deposition. In some embodiments, the second metal layer232comprises titanium nitride. In some embodiments, the second metal layer232has a thickness of 1 nm to about 10 nm. Turning toFIGS. 13-15, which illustrates the formation of a metal fill234in the first opening228to form the third metal connect218and the formation of the metal fill234in the second opening226over the second metal layer232to form the metal contact214. In some embodiments, the metal fill234is formed by deposition. In some embodiments, the metal fill234comprises tungsten. In some embodiments, excess first metal layer230, second metal layer232and metal fill234are removed, such as by chemical mechanical planarization (CMP). Turning toFIG. 16, which illustrates a cross-section of the fourth line246ofFIG. 2, where the fourth line246cuts through the first metal connect215, the second metal connect216and the third metal connect218. In some embodiments, the third metal connect218has a third metal length227, the third metal length227substantially equal to a semiconductor arrangement length229. In some embodiments, the semiconductor arrangement length229is measured from a first distal sidewall231bof the first metal connect215to a second distal sidewall231aof the second metal connect216.

Turning toFIG. 17, a 3D cross-sectional view of the semiconductor arrangement is illustrated as viewed from a perspective indicated by arrows on line17-17inFIG. 2, where the second dielectric layer224is removed. According to some embodiments, the one or more fins204with Epi caps206pass through the gate208, such that on a first side256of the gate208, the Epi caps206bcomprises one of a source or a drain and on a second side258of the gate208, the Epi caps206acomprises a source if the Epi caps206bcomprise a drain or a drain if the Epi caps206bcomprises a source. In some embodiments, the first metal connect215is formed around the one or more fins204with Epi caps206bin the first active region205. In some embodiments, the second metal connect216is formed around the one or fins204with Epi caps206bin the second active region207. In some embodiments, the STI region209comprises the STI220, where the STI220is situated such that the STI220separates the one or more fins204with Epi caps206in the first active region205from the one or more fins204with Epi caps206in the second active region207. In some embodiments, the third metal connect218connects the first metal connect215to the second metal connect216, such that the one or more fins204with Epi caps206bin the first active region205are connected to the one or more fins204with Epi caps206bin the second active region207. In some embodiments, the Epi caps206bin the first active region205and the Epi caps206bin the second active region20comprise drains, and thus the third metal connect218connects a first drain to a second drain. In some embodiments, the Epi caps206bin the first active region205and the Epi caps206bin the second active region207comprise sources, and thus the third metal connect218connects a first source to a second source.

According to some embodiments, a semiconductor arrangement comprises a first active region, a second active region, and a shallow trench isolation (STI) region between the first active region and the second active region. In some embodiments, a first metal connect is over the first active region and connected to the first active region, a second metal connect is over the second active region and connected to the second active region, and a third metal connect is over the first metal connect, the STI region and the second metal connect. In some embodiments, the third metal connect is connected to the first metal connect and to the second metal connect, such that the third metal connect connects the first metal connect to the second metal connect.

According to some embodiments, a method of forming a semiconductor arrangement comprises forming a first opening over a first active region, a shallow trench isolation (STI) region and a second active region, such that the first opening is over a first metal connect in the first active region, and is over a second metal connect in the second active region. In some embodiments, forming a semiconductor arrangement comprises forming a third metal connect in the first opening such that the third metal connect connects the first metal connect to the second metal connect.

According to some embodiments, a semiconductor arrangement comprises a first active region, a second active region, and a shallow trench isolation (STI) region between the first active region and the second active region. In some embodiments, a gate is over the first active region, the second active region and the STI region. In some embodiments, a first metal connect adjacent the gate is over the first active region and connected to the first active region, a second metal connect adjacent the gate is over the second active region and connected to the second active region, and a third metal connect is over the first metal connect, the STI region and the second metal connect. In some embodiments, the third metal connect is connected to the first metal connect and to the second metal connect such that the third metal connect connects the first metal connect to the second metal connect.

It will be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers features, elements, etc. mentioned herein, such as etching techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques such as magnetron or ion beam sputtering, growth techniques, such as thermal growth or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), for example.