Array of vertical bipolar junction transistors, in particular selectors in a phase change memory device

A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.

BACKGROUND

1. Technical Field

The present invention relates to an array of vertical bipolar junction transistors. In particular, the invention may be advantageously used to form an array of selectors in a phase change memory device, without however being limited thereto.

2. Description of the Related Art

As is known, phase change memories are formed by memory cells connected at the intersections of bitlines and wordlines and comprising each a memory element and a selection element. A memory element comprises a phase change region made of a phase change material, i.e., a material that may be electrically switched between a generally amorphous and a generally crystalline state across the entire spectrum between completely amorphous and completely crystalline states.

Typical materials suitable for the phase change region of the memory elements include various chalcogenide elements. The state of the phase change materials is non-volatile, absent application of excess temperatures, such as those in excess of 150° C., for extended times. When the memory is set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reprogrammed, even if power is removed.

Selection elements may be formed according to different technologies, for example they can be implemented by diodes, by MOS transistors or bipolar transistors.

U.S. Pat. No. 7,227,171 discloses a method for manufacturing bipolar type selection transistors in a phase change memory device. Although the process described therein is satisfactory, it is susceptible of improvement, in particular as regards the emitter formation. Furthermore, this known process does not provide for salicided junctions of the selection transistors, but only of the circuitry transistors.

To improve the above process, the inventors have devised a process including defining, in a semiconductor body, a plurality of active areas delimited by field insulation regions; forming a plurality of base regions in the active areas; forming a plurality of silicide protection strips extending transversely to the field insulation regions above the semiconductor body; forming a plurality of emitter regions in each active area on a first side of the silicide protection strips; forming base contact regions in each active areas on a second side of the silicide protection strips; and forming silicide regions on the emitter and base contact regions. Thus, in each active area, the silicide protection strips separate the emitter regions from the base contact regions.

However, with the continuous miniaturization of the circuits, there is the risk the lateral diffusion of the implants during the activation causes the emitter regions and the base contact regions to be very close or even short-circuited, thus causing unwanted leakages in the selection transistors.

This problem is clarified with reference toFIGS. 1-3, showing a portion of a memory device accommodating selection transistors. In these figures, a substrate1comprises a subcollector region2a first conductivity type (e.g., P+), a collector region3of the first conductivity type (here, P type) and a base region4, overlying the collector region3and of a second conductivity type (here, N type). The subcollector region2and the collector region3extend at least in part below the field oxide regions6and are common to and shared by the entire memory device. The base regions4have a strip-like form and extend each in an own active area5of the matrix. The active areas5, as visible from the top view ofFIG. 1, have also a strip-like shape and are insulated from each other by field oxide regions6obtained by STI (Shallow Trench Insulation).

Above the surface of the substrate1, silicide protection regions10, e.g., of silicon nitride, extend perpendicularly to the field oxide regions6; in each active area5, base contact regions11, of N+ type, extend within the base region4on one side of each silicide protection region10and emitter regions12, of P type, extend within the base region4on the other side of each silicide protection region10, so that each base contact region11is separated by the neighboring emitter regions12by a silicide protection region10.

The base contact regions11and the emitter regions12are covered by silicide regions15and the surface of the substrate1is covered by a dielectric layer16. Base plugs17and emitter plugs18extend through the dielectric layer16for electrically connecting the base contact regions11and the emitter regions12, respectively.

In the described structure, the silicide protection regions10may have a width of 100 nm; the plugs17and18may have a width of 80 nm, the distance between adjacent silicide protection regions10may be 120 nm. With the indicated dimensions, considering the lateral diffusion of the doping agents and possible mask misalignments (FIG. 1also shows the emitter implant mask19), there is the risk that the base contact regions11and the emitter regions12come into contact and behave like Zener diodes, giving rise to current leakages, which is undesired.

US 2002/0081807 discloses a phase-change memory device having a dual trench isolation, wherein each selection element (a diode) is isolated from the adjacent ones in both directions by shallow trench regions. The upper region of the selection element is silicided. US 2002/0079483 and US 2002/0079524 disclose other phase-change memory devices having a dual trench isolation. These processes are particularly burdensome and cannot be used to manufacture transistors having at least two terminals connected to upper metal layers.

BRIEF SUMMARY

One embodiment is a process for manufacturing bipolar junction transistors overcoming the shortcomings of the prior art.

According to one embodiment, there is provided a method for manufacturing an array of bipolar junction transistors, as well as an array of bipolar junction transistors, as defined in claims1and9, respectively.

DETAILED DESCRIPTION

Thereafter,FIGS. 5 and 6, a thin oxide layer27and a nitride layer28are deposited. Then,FIG. 7, the nitride layer28is patterned, using a resist mask not shown, to form a hard mask28′. In particular, the nitride layer28may be dry etched using a process that is selective toward silicon, followed by stripping. The hard mask28′ includes a plurality of strips, extending transversely, e.g., perpendicularly, to the deep field oxide regions26.

Using the hard mask28′, the wafer is subject to a thermal oxidation (LOCOS), thereby causing surface field oxide regions29to grow in the active areas22, partly within the substrate20, where the surface is not covered by the hard mask28′,FIG. 8. The surface field oxide regions29are thus strip-shaped and shallower than the deep field oxide regions26and extend through only a surface portion of each base region25. For example, the surface field oxide regions29may have a depth of 80 nm.

Using a wet process and phosphoric agent,FIG. 9, the hard mask28′ of nitride is removed, and then the oxide layer27is removed as well. Thereby, also the protruding part of the field oxide regions29is at least partially removed, thus substantially planarizing the surface.

Then,FIG. 10, a P-implant protection mask30, of resist, is formed on the surface of the substrate21, by spinning, exposing and developing a photoresist layer. The P-implant protection mask30comprises a plurality of strips extending parallel to the surface field oxide regions29but offset thereto so as to cover the surface of the substrate21between pairs of surface field oxide regions29, as well as part of the latter. Then, an emitter implant with boron is performed, thereby forming emitter regions31. The emitter regions31may have a depth of 20 nm, thus are shallower or at least not deeper than the surface field oxide regions29.

Subsequently,FIG. 11, after removing the P-implant protection mask30, an N-implant protection mask35is formed, which covers the emitter regions31(in practice, the implant protection mask35is a negative of the P-implant protection mask30). Then, an N+-implant with arsenic is carried out, thereby forming base contact regions36. Accordingly, the base contact regions36are arranged alternately to the emitter regions31on two opposed sides of each surface field oxide regions29in each active area. The base contact regions36may have a depth of 40 nm, thus are shallower or at least not deeper than the surface field oxide regions29. Thereby, the surface field oxide regions29separate the emitter regions31from the base contact regions36.

After removing the N-implant protection mask35and performing an implant activation/diffusion step in RTP (Rapid Temperature Process) at a temperature comprised between 900 and 1100° C., salicide regions37are formed, in a per se known manner, over the emitter regions31and the base contact regions36,FIG. 12.

Then,FIG. 13, a nitride layer38(preferably, with a thickness of 20 nm) and a first dielectric layer39(preferably, USG—Undoped Silicate Glass—with a thickness of 700 nm) are deposited and planarized down to about 600 nm. Using a resist mask not shown, the dielectric layer40and the nitride layer38are etched where contacts are to be formed so as to form openings40that reach the silicide regions37. The apertures40are filled by a contact material to form plugs or contacts41aand41b; e.g., filling may envisage depositing a barrier layer, e.g., a multiple Ti/TiN layer, and a tungsten layer, and then planarizing the deposited layers.

Finally, back end steps or the steps to form the memory elements are carried out. In the latter case, for example, the process described in U.S. Patent Application Publication No. 2007/051936 may be used, to obtain the final structure ofFIGS. 14 and 15, taken respectively in the direction of the wordlines and in the direction of the bit-lines.

In detail, a second dielectric layer76is deposited; openings are formed in the second dielectric layer76above the emitter regions31; a spacer layer75of silicon nitride is formed on the walls of the openings; a heater layer77and a sheath layer74are subsequently deposited to cover the walls and the bottom of the openings; a third dielectric layer67is deposited to fill the openings; and the wafer is planarized. Accordingly, the heaters77are generally cup-shaped. InFIG. 14, the heaters77extend on first-level plugs41bwhich are in electrical contact with the emitter regions31. Next, a chalcogenic layer78of GST (Ge2Sb2Te5), and a metal layer79are deposited and defined to form resistive bit lines, which run perpendicularly to the plane ofFIG. 14. Metal lines79thus create a first metal level.

Then, a sealing layer80and a fourth dielectric layer81are deposited; holes are opened, coated with a barrier layer and filled by a metal layer83or84, of Cu.

Thus, the cross-section ofFIG. 14shows second-level, base plugs83which extend through the layers76,80and81to contact the first-level plugs41aand, thus, the base contact regions36;FIG. 15show second-level, intermediate plugs84extending through the layers80and81to contact the first metal layer79.

Then, wordlines WL, from a second metal layer, are formed on the fourth dielectric layer81in electrical contact with the second-level, base plugs83and thus the base region25, through the first-level plugs41aand the base contact regions36; conductive regions85are formed from the same second metal layer as the wordline WL, as visible fromFIG. 15, and are in electrical contact with the second-level, intermediate plugs84to allow electrical connections between the latter and bit-lines BL.

The wordlines WL and the conductive regions85are insulated from each other by a second nitride layer86and a fifth dielectric layer87(FIG. 15).

A third nitride layer88and a sixth dielectric layer89are formed on the fifth dielectric layer87, the wordlines WL and the conductive regions85; bit lines BL of conductive material are formed in the sixth dielectric layer89from a third metal layer; vias90connect the bitlines BL to the conductive regions85.

FIGS. 16 and 17show an embodiment wherein the surface field oxide regions29are grown in recesses of the substrate20(recessed LOCOS technique). In detail, after forming the hard mask28′ (FIG. 7), the thin oxide layer27and a surface portion of the substrate21are etched, thereby forming recesses50having a depth of 30 nm,FIG. 16. Then, thermal growth of oxide follows, forming the surface field oxide regions29that fill the recesses50and are approximately planar with the surface of the substrate21. Then, the steps discussed with reference toFIGS. 9-15are performed. The resulting structure has a better planarity than that obtainable with the embodiment ofFIGS. 7-8.

FIG. 18shows an embodiment wherein each base contact region36is formed every two emitter regions31, so that couples of adjacent emitter regions31are spaced only by a surface field oxide region29. Thus, each base contact region36forms two bipolar transistors with the adjacent emitter regions31. In addition, analogously to the solution ofFIGS. 2 and 3and to the embodiments ofFIGS. 4-17, each base region25has a strip-like form and extends in an own active area22(FIG. 6) of the array. Thus, in the direction of the worldlines WL, the base region25is shared by all the adjacent selection transistors and are insulated from each other by the deep field oxide regions26.

Turning toFIG. 19, a portion of a system500in accordance with an embodiment of the present invention is described. System500may be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly. System500may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, a cellular network, although the scope of the present invention is not limited in this respect.

System500includes a controller510, an input/output (I/O) device520(e.g., a keypad, display), static random access memory (SRAM)560, a memory530, and a wireless interface540coupled to each other via a bus550. A battery580is used in some embodiments. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components.

Controller510comprises, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. Memory530may be used to store messages transmitted to or by system500. Memory530may also optionally be used to store instructions that are executed by controller510during the operation of system500, and may be used to store user data. Memory530may be provided by one or more different types of memory. For example, memory530may comprise any type of random access memory, a volatile memory, a non-volatile memory such as a flash memory and/or a memory such as memory discussed herein.

I/O device520may be used by a user to generate a message. System500uses wireless interface540to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of wireless interface540may include an antenna or a wireless transceiver, although the scope of the present invention is not limited in this respect.

The advantages of the described embodiments are clear from the above description. In particular, it is pointed out that the transistor array has a good separation between the base contact regions36and the emitter regions31, since they are isolated in both directions, either by the deep field oxide regions26or the surface field oxide regions29(inside each active area22).

The process is simple, can be performed using standard manufacturing machinery and is well controllable, by virtue of the implants being self-aligned. In particular, the surface field oxide regions29ensure a confinement of the base contact and emitter implants, whose lateral diffusion during activation is limited; furthermore, the same surface field oxide regions29ensure a confinement of silicide regions37.

The formation of the surface field oxide regions29through the LOCOS technique has the advantage of avoiding possible shorts typical of dual trench isolation, because pure LOCOS does not require a silicon etch and, in the case of recessed LOCOS, the oxidation removes possible residuals of silicon along the surface isolation trench.

The formation of the salicide regions37after growing the surface field oxide regions29and forming the base contact regions32and the emitter regions31has the advantage of helping the dielectric etch landing on the emitter and base contact without damaging them. Moreover the salicide guarantees a low contact resistance.

Finally, it is clear that numerous variations and modifications may be made to the process described and illustrated herein, all falling within the scope of the invention. In particular, the invention, although described with reference to the manufacture of a phase change memory device, may be used to any application wherein an array of bipolar junction transistor is used and a confinement of the conducting regions is sought.

Furthermore, the surface field oxide regions29may be grown before forming the deep field oxide regions26, thus exchanging the order of forming the field oxide regions26,29.