Voltage comparison circuit, and semiconductor integrated circuit and electronic device having the same

A disclosed voltage comparison circuit for detecting a voltage difference of two input signals includes one or more differential amplifier circuits, each of which has a differential pair of first and second input transistors each having an electrode to which a corresponding one of the input signals is input, a constant current circuit configured to generate constant current according to a control signal and supply the constant current to the first and second input transistors, and a first resistor connected between the constant current circuit and the first input transistor; and a current control circuit configured to control a value of the first constant current. The current control circuit controls the value so that a voltage difference between both ends of the first resistor becomes equal to a predetermined value.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed to a voltage comparison circuit capable of detecting that two different signals reach a certain offset level and used for suppressing noise in a differential serial signal and detecting connection to transmission lines used for transmitting a differential serial signal. The present invention, in particular, relates to a voltage comparison circuit having an offset, applicable to a squelch circuit and a disconnection detection circuit, for example, used in USB 2.0, and also applicable for Hall signal detection by a hysteresis comparator used in a motor driver.

2. Description of the Related Art

A conventional voltage comparison circuit having an offset uses a method of setting the value of the offset voltage by connecting load resistors to the source terminals of transistors forming a differential pair, as shown inFIG. 11(for example, see Patent Document 1). In addition, as a means to vary the offset voltage value, MOS switches for changing the resistance value are used or laser trimming is performed, to improve the accuracy of the setting of the offset voltage value. Another conventional method sets the offset voltage value by controlling the current value of one terminal of a constant current source load (e.g. see Patent Document 2).[Patent Document 1] Japanese Laid-open Patent Application Publication No. 2004-194124[Patent Document 2] Japanese Patent Publication No. 3926645

However, in the case illustrated inFIG. 11, it is necessary to use a resistor large enough to be able to ignore the on-resistance of the MOS switches or the trimming bit resistor of the laser trimming, and therefore, the amount of current allowed to flow through the differential pair is limited. Accordingly, the conventional technology is unsuitable for high-speed response detection capable of detecting the level difference of two signals in compliance with high-speed serial transmission, for example, USB 2.0 serial data link. Also, resistors and MOS switches relatively large in size are required, leading to an increase in the circuit size. Furthermore, in the case of setting the offset voltage by switching the MOS switches or by laser trimming, the setting needs to be made in a post-manufacturing process, which leads to an increase in cost. The case of setting the offset voltage by controlling the current value of one terminal of a constant current source load is suitable for high-speed serial transmission since it allows high-speed response; however, if matching of respective transistors is not ideal, the accuracy of the setting of the offset voltage value varies to an extent, thereby making it difficult to control the current value. Furthermore, if the detection offset level of a differential signal is large, the current ratio between the transistors of the differential pair becomes extremely large, making it difficult to control the variation.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems, the present invention aims at providing a voltage comparison circuit for detecting a voltage difference of two input signals. The voltage comparison circuit includes one or more differential amplifier circuit units, each of which has a differential pair of a first input transistor and a second input transistor each having a control electrode to which a corresponding one of the input signals is input, a constant current circuit unit configured to generate a first constant current in accordance with an input control signal and supply the first constant current to the first input transistor and the second input transistor, and a first resistor connected between the constant current circuit unit and the first input transistor; and a current control circuit unit configured to perform operational control on the constant current circuit unit to control a current value of the first constant current. The current control circuit unit controls the current value of the first constant current so that a voltage difference between both ends of the first resistor becomes equal to a predetermined value.

DETAILED DESCRIPTION OF THE PREFERED EMBODIMENTS

Next is described the present invention in detail based on an embodiment illustrated in the drawings.

First Embodiment

FIG. 1illustrates a structural example of a voltage comparison circuit according to the first embodiment of the present invention.

The voltage comparison circuit1ofFIG. 1, having an offset, generates an output signal Sout which indicates whether a voltage difference between input signals D+ and D−, each of which is input to a corresponding input terminal, is equal to or greater than a predetermined value Va and outputs the output signal Sout from an output terminal OUT.

The voltage comparison circuit1includes a differential amplifier circuit2having input terminals to which the input signal D+ and the input signal D− are respectively input; an amplifier circuit3for amplifying a signal output from the differential amplifier circuit2and outputting the amplified signal; and a current control circuit4for controlling bias currents, which flow through the differential amplifier circuit2and the amplifier circuit3, respectively.

The differential amplifier circuit2includes a differential input circuit11having input transistors M1and M2, which are a differential pair of PMOS transistors; a constant current circuit12for generating a constant current in accordance with a control signal input from the current control circuit4and inputting the generated constant current into the differential input circuit11as a bias current; load circuits13and14, which function as load elements of the differential input circuit11; and a resistor R1having a resistance value R, connected between the input transistor M1and the constant current circuit12and configured to provide an offset voltage.

The resistor R1is connected between the current output terminal of the constant current circuit12and the source terminal of the input transistor M1, and the load circuit13is connected between the drain terminal of the input transistor M1and ground potential GND. The input signal D+ is input to the gate terminal of the input transistor M1.

Furthermore, the source terminal of the input transistor M2is connected to the current output terminal of the constant current circuit12, and the load circuit14is connected between the drain terminal of the input transistor M2and ground GND. The input signal D− is input to the gate terminal of the input transistor M2. The connection between the input transistor M2and the load circuit14forms an output terminal of the differential amplifier circuit2, and is connected to the input terminal of the amplifier circuit3. The output terminal of the amplifier circuit3is connected to the output terminal OUT, from which the output signal Sout is output.

The current control circuit4performs control such that the signal level of the output signal Sout is inverted when a voltage difference between the input signals D+ and D− exceeds the predetermined value Va. Specifically, the current control circuit4performs control on the constant current circuit12in terms of the current value of an output current (2×i) in such a manner that a voltage drop (i×R) becomes equal to the predetermined value Va. The voltage drop (i×R) is induced when a current i, which is ½ the current (2×i) supplied from the constant current circuit12, flows through the resistor R1.

FIG. 2illustrates a circuit example of the voltage comparison circuit1ofFIG. 1.

InFIG. 2, the current control circuit4includes PMOS transistors M4and M5, an NMOS transistor M6, a resistor R2having the resistance value R, a subtraction circuit15, an operational amplifier circuit16, and a reference voltage source17for generating and outputting a reference voltage Vref having the predetermined value Va. InFIG. 2, a PMOS transistor M3functions as the constant current circuit12, an NMOS transistor M7functions as the load circuit13, and an NMOS transistor M8functions as the load circuit14. The NMOS transistors M7and M8form a current mirror circuit. The amplifier circuit3includes a PMOS transistor M11, an NMOS transistor M12and an inverter21.

Note that the input transistor M1corresponds to the “first input transistor” as defined in the appended claims. Similarly, the input transistor M2corresponds to the “second input transistor”; the PMOS transistor M3, the “constant current circuit” and “first transistor”; the resistor R1, the “first resistor”; the differential amplifier circuit2, the “differential amplifier circuit unit”; the current control circuit4, the “current control circuit unit”; the PMOS transistor M4, the “proportional current generation circuit unit” and “second transistor”; the resistor R2, the “second resistor”; the operational amplifier circuit16, the “control circuit”; the load circuit13, the “first load circuit”; the load circuit14, the “second load circuit”; the PMOS transistor M5, the “third transistor”; and the NMOS transistor M6, the “third load circuit”.

As for the PMOS transistor M3, the source terminal is connected to a power supply voltage VDD, the drain terminal is connected to the connection between the resistor R1and the source terminal of the input transistor M2, and the gate terminal is connected to the output terminal of the operational amplifier circuit16. As for the PMOS transistor M4, the source terminal is connected to the power supply voltage VDD, and the gate terminal is connected to the output terminal of the operational amplifier circuit16. The resistor R2is connected between the drain terminal of the PMOS transistor M4and the source terminal of the PMOS transistor M5, and an NMOS transistor M6is connected between the drain terminal of the PMOS transistor M5and ground GND. The gate terminal of the PMOS transistor M5is connected to ground GND. The gate terminal of the NMOS transistor M6is connected to its drain terminal, thus forming a diode. Each end of the resistor R2is connected to the subtraction circuit15. The output terminal of the subtraction circuit15is connected to the non-inverting input terminal of the operational amplifier circuit16. The reference voltage Vref is input to the inverting input terminal of the operational amplifier circuit16.

As for the NMOS transistors M7and M8, their source terminals are connected to the ground voltages GND. Their gate terminals are connected to each other, and the connection is connected to the drain terminal of the NMOS transistor M7. The drain terminal of the NMOS transistor M7is connected the drain terminal of the input transistor M1, and the drain terminal of the NMOS transistor M8is connected to the drain terminal of the input transistor M2.

In the amplifier circuit3, the PMOS transistor M11and the NMOS transistor M12are connected in series between the power supply voltage VDD and ground GND. The gate terminal of the PMOS transistor M11is connected to the output terminal of the operational amplifier circuit16, and the gate terminal of the NMOS transistor M12is connected to the connection between the drain terminal of the input transistor M2and the drain terminal of the NMOS transistor M8. The connection between the PMOS transistor M11and the NMOS transistor M12is connected to the input terminal of the inverter21. The output terminal of the inverter21is connected to the output terminal OUT.

In the above-described structure, the size of the PMOS transistor M4is ½ that of the PMOS transistor M3, and the resistance value of the resistor R2is the same as that of the resistor R1. The input transistors M1and M2and the PMOS transistor M5have the same transistor size, and the NMOS transistors M6through M8have the same transistor size. The subtraction circuit15calculates a voltage difference between the ends of the resistor R2, and outputs the calculated difference to the non-inverting input terminal of the operational amplifier circuit16. Then, the operational amplifier circuit16performs operational control on the PMOS transistors M3, M4and M11in such a manner that the output voltage of the subtraction circuit15becomes equal to the reference voltage Vref.

Accordingly, the current i output from the PMOS transistor M4becomes equal to Va/R, and the current output from the PMOS transistor M3becomes equal to 2×i=2×Va/R. That is, when the signal level of the output signal Sout is inverted, the current i flows through each of the input transistors M1and M2. Since the input transistors M1and M2have the same gate-source voltages Vgs, the signal level of the output signal Sout is inverted when the voltage difference between the input signal D+ input to the gate terminal of the input transistor M1and the input signal D− input to the gate terminal of the input transistor M2becomes equal to the voltage value Va.

When the signal level of the output signal Sout is inverted, the current values of the currents flowing through the input transistors M1and M2are substantially the same, and even if the voltage value Va is high, the ratio of these currents remains constant. Therefore, if the input transistors M1and M2are formed with high accuracy so that the transistor size ratio between the input transistors M1and M2becomes constant, it is possible to very simply achieve the voltage comparison circuit1capable of accurately setting the offset value.

In addition, in order to set the offset value of the voltage comparison circuit1accurately to the voltage value Va, it is necessary to set the ratio of the resistance values of the resistors R1and R2with high accuracy. The ratio of the resistance values can be relatively easily set with high accuracy by forming the resistors R1and R2on a single silicon substrate. It is, therefore, possible to simply achieve the voltage comparison circuit1capable of accurately setting the offset value.

In the case where the resistors R1and R2are manufactured in a single integrated circuit (IC), the ratio of their resistance values can be maintained with high accuracy; however, variation in the absolute values of the resistors R1and R2occurs due to process fluctuation and temperature fluctuation. According to the structure of the voltage comparison circuit1of the first embodiment, however, even if variation in the absolute values of the resistors R1and R2occurs due to process fluctuation and temperature fluctuation, the current of the constant current source changes in accordance with the variation. For example, if the finished resistors R1and R2have a resistance value 30% less than a desired resistance value, the current value of the constant current i contrarily becomes 30% larger than originally expected. Accordingly, the offset amount is corrected so that the offset voltage is maintained at the voltage value Va, and the voltage comparison circuit1is able to always detect whether the voltage difference between the input signals D+ and D− exceeds the voltage value Va. Herewith, the voltage comparison circuit1is preferably produced in a single IC.

FIG. 2illustrates an example in which PMOS transistors are used for the input transistors M1and M2; however, NMOS transistors may be used instead. In this case, the circuit structure ofFIG. 2is changed to that ofFIG. 3.

For the sake of simple explanation, inFIG. 2, the influence of the channel length modulation effect λ of the input transistors M1and M2is ignored; however, the source-drain current ids of a MOS transistor is expressed by the following equation (1).
ids=β/2×W/L×(Vgs−Vth)2×(1+λ×Vds)  (1)

If the voltage difference between the drain-source voltages Vds of the input transistors M1and M2, i.e. the voltage value Va, is small, the influence of the channel length modulation effect λ is almost negligible; however, if the voltage value Va is large, a large error occurs. In this case, such an error can be substantially eliminated by inserting a resistor R3having the same resistance value R as those of the resistors R1and R2between the input transistor M2and the NMOS transistor M8, as shown inFIG. 4. Note that the resistor R3corresponds to the “fourth resistor” as defined in the appended claims.

However, in this case, since the response speed of the voltage comparison circuit1slightly decreases, it is necessary to set the resistance value R as small as possible while setting the current value of the current i as large as possible, thereby setting the detection speed of the voltage comparison circuit1to a desired speed.

InFIG. 2, the transistor size of the PMOS transistor M4may be 1/(2×α) the transistor size of the PMOS transistor M3; the transistor size of the PMOS transistor M5, 1/α the transistor size of the input transistors M1and M2; the transistor size of the NMOS transistor M6, 1/α the transistor size of the NMOS transistors M7and M8; the resistance value of the resistor R1, γ×R; and the resistance value of the resistor R2, α×R. In this case, the voltage difference detected by the voltage comparison circuit1is determined to be a product of the ratio of the reference voltage Vref to the resistance value of the resistor R1and the ratio of the reference voltage Vref to the resistance value of the resistor R2. Herewith, it is possible to allow the constant current circuit12, which does not need to have an operating speed as high as that of the differential input circuit11, to have low power consumption.

The circuit structure ofFIG. 2is able to detect only (D+voltage)−(D−voltage)>Va. Given this factor, another differential amplifier circuit2and amplifier circuit3may be added to the circuit ofFIG. 2, as shown inFIG. 5(the transistor sizes and the resistance value are the same as those ofFIG. 2). In the added differential amplifier circuit2, the input signals D− and D+ are input to the gate terminals of the input transistors M2and M1, respectively. An OR circuit22performs the logical OR operation on output signals of the two amplifier circuits3to detect whether |(D+voltage)−(D−voltage)|>Va. In addition, if the resistance value of each resistor R1ofFIG. 5is set to α×R, it is possible to detect whether |(D+voltage)−(D−voltage)|>α×Va.

Hence, to detect whether |(D+voltage)−(D−voltage)|>Va as well as whether |(D+voltage)−(D−voltage)|>α×Va, it only takes two voltage comparison circuits1ofFIG. 5, i.e. the voltage comparison circuit1having the resistor R1whose resistance value is R and the voltage comparison circuit1having the resistor R1whose resistance value is α×R. In this case, the single current control circuit4can be shared by the two voltage comparison circuits1, thereby reducing the cost of production.

For example, the circuit for detecting whether |(D+voltage)−(D−voltage)|>Va may be used as a squelch detection circuit for detecting that a serial data signal is equal to or lower than the squelch level; and the circuit for detecting whether |(D+voltage)−(D−voltage)|>α×Va may be used as a disconnection detection circuit for detecting disconnection of a serial data transmission line. Although such a squelch detection circuit and a disconnection detection circuit used in USB 2.0 Host/Function are required to ensure high detection accuracy and high-speed response, these detection circuits can be readily provided by using the voltage comparison circuits1shown inFIG. 5. Furthermore, in the case of using both the squelch detection circuit and the disconnection detection circuit, only one current control circuit4is necessary, thereby reducing the cost of production.

FIG. 6is another circuit example of the current control circuit4. InFIG. 6, the same reference numerals are given to the components which are common to those ofFIG. 2.

InFIG. 6, the current control circuit4includes PMOS transistors M4, M5and M15, NMOS transistors M6and M16, the resistor R2having the resistance value R, the subtraction circuit15, the operational amplifier circuit16and the reference voltage source17.

The PMOS transistors M4and M15form a current mirror circuit. As for the PMOS transistors M4and M15, each source terminal is connected to the power supply voltage VDD, and their gate terminals are connected to each other. The connection of the gate terminals is connected to the drain terminal of the PMOS transistor M15and also connected to the gate terminals of the PMOS transistors M3and M11.

The resistor R2is connected between the drain terminal of the PMOS transistor M4and the source terminal of the PMOS transistor M5, and the NMOS transistor M6is connected between the drain terminal of the PMOS transistor M5and ground GND. The gate terminal of the PMOS transistor M5is connected to ground GND. The gate terminal of the NMOS transistor M6is connected to its drain terminal, thus forming a diode. Each end of the resistor R2is connected to the subtraction circuit15. The output terminal of the subtraction circuit15is connected to the inverting input terminal of the operational amplifier circuit16. The reference voltage Vref is input to the non-inverting input terminal of the operational amplifier circuit16.

The NMOS transistor M16is connected between the drain terminal of the PMOS transistor M15and ground GND. The gate terminal of the NMOS transistor M16is connected to the output terminal of the operational amplifier circuit16. The PMOS transistors M15, M4, M3and M11form a current mirror circuit. The operational amplifier circuit16controls the currents output from the PMOS transistor M4, M3and M11by performing operational control on the PMOS transistor M16in such a manner that the output voltage of the subtraction circuit15becomes equal to the reference voltage Vref.

FIG. 7illustrates a circuit example of the subtraction circuit15.

InFIG. 7, the subtraction circuit15is designed to generate a voltage (V1−V2) obtained by subtracting an input voltage V2from an input voltage V1and output the generated voltage, and includes a PMOS transistor M21, an operational amplifier circuit31, and resistors R21and R22.

The input voltage V1is input to the inverting input terminal of the operational amplifier circuit31via the resistor R22, and the input voltage V2is input to the non-inverting input terminal of the operational amplifier circuit31. Between the inverting input terminal of the operational amplifier circuit31and ground GND, the PMOS transistor M21and the resistor R21are connected in series, and the gate terminal of the PMOS transistor M21is connected to the output terminal of the operational amplifier circuit31. The output voltage (V1−V2) is output from the connection of the PMOS transistor M21and the resistor R21.

FIG. 8illustrates another circuit example of the subtraction circuit15. InFIG. 8, the same reference numerals are given to the components which are common to those ofFIG. 7.

InFIG. 8, the subtraction circuit15is designed to generate the voltage (V1−V2) obtained by subtracting the input voltage V2from the input voltage V1and output the generated voltage, and includes the operational amplifier circuit31and resistors R25through R28.

The input voltage V1is input to the inverting input terminal of the operational amplifier circuit31via the resistor R26, and the resistors R27and R28are connected in series between the input voltage V2and ground GND. The connection between the resistors R27and R28is connected to the non-inverting input terminal of the operational amplifier circuit31, and the resistor R25is connected between the inverting input terminal and output terminal of the operational amplifier circuit31. The output voltage (V1−V2) is output from the output terminal of the operational amplifier circuit31.

Next,FIG. 9illustrates another circuit example of the current control circuit4. InFIG. 9, the same reference numerals are given to the components which are common to those ofFIG. 2, and their descriptions are omitted while only a difference fromFIG. 2is explained.

The difference ofFIG. 9fromFIG. 2is the circuit structure of the current control circuit4.

In the current control circuit4ofFIG. 9, the PMOS transistor M4forms a current mirror circuit together with the PMOS transistors M3and M11. The source terminal of the PMOS transistor M4is connected to the power supply voltage VDD, and the gate terminal of the PMOS transistor M4is connected to its drain and also connected to the gate terminals of the PMOS transistors M3and M11.

The drain terminal of the PMOS transistor M4is connected to the drain terminal of the NMOS transistor M6, and the resistor R2is connected between the source terminal of the NMOS transistor M6and ground GND. In the operational amplifier circuit16, the inverting input terminal is connected to the connection between the NMOS transistor M6and the resistor R2, the reference voltage Vref is input to the non-inverting input terminal, and the output terminal is connected to the gate terminal of the NMOS transistor M6. Note that, inFIG. 9, the NMOS transistor M6and the operational amplifier circuit16form a control circuit.

The operational amplifier circuit16performs operational control on the NMOS transistor M6in such a manner that the voltage at the connection between the NMOS transistor M6and the resistor R2becomes equal to the reference voltage Vref. The same current flowing through the NMOS transistor M6also flows through the PMOS transistor M4, and currents proportional to the current flowing through the PMOS transistor M4respectively flow through the PMOS transistors M3and M11. When the resistance value of the resistor R1is R, the resistance value of the resistor R2is (α×R)/γ and the voltage value of the reference voltage Vref is Va. Accordingly, a constant current (Va×γ)/(α×R) flows through the PMOS transistor M4. The transistor size of the PMOS transistor M3is 2×α times that of the PMOS transistor M4, and when the current value of the current flowing through the resistor R1is Va×γ/R, i.e. a voltage between both ends of the resistor R1is γ×Va, the signal level of the output signal Sout is inverted. It should be noted that the current control circuit ofFIG. 9may be used as the current control circuit4ofFIGS. 3 through 5.

In the case where hysteresis is provided in the voltage comparison circuit1ofFIG. 9, the circuit structure ofFIG. 9is changed to that ofFIG. 10.FIG. 10differs fromFIG. 9in that a resistor R11and switches SW1and SW2are added to the differential amplifier circuit2ofFIG. 9and an inverter23is added to the amplifier circuit3ofFIG. 9. Note that the resistor R11corresponds to the “third resistor” as defined in the appended claims. Similarly, the switches SW1and SW2correspond to the “first switch unit” and “second switch unit”, respectively.

The resistor R11is connected between the drain terminal of the PMOS transistor M3and the source terminal of the PMOS transistor M2, and the switches SW1and SW2are connected parallel to the resistors R1and R11, respectively.

The output terminal of the inverter21is connected to the input terminal of the inverter23, and the output terminal of the inverter23is connected to the output terminal OUT. The switch SW1performs a switching operation in accordance with the signal level of the output signal Sout, and the switch SW2performs a switching operation in accordance with the signal level of the output signal of the inverter21. Herewith, hysteresis can be provided in the voltage comparison circuit1. Note thatFIG. 10is based on the case ofFIG. 9; however, hysteresis can be provided in the cases ofFIGS. 2 through 5. Since the application of the hysteresis to the cases ofFIGS. 2 through 5is the same as shown inFIG. 10, the explanation is omitted.

As has been described above, the voltage comparison circuit of the first embodiment includes the resistor R1connected in series between the constant current circuit12and one (M1) of the two input transistors of the differential input circuit11, and is designed so that the current control circuit4controls the current output from the PMOS transistor M3, which functions as the constant current circuit12for supplying the bias currents to the input transistors M1and M2, in such a manner that the voltage difference between both ends of the resistor R1becomes constant at the predetermined value Va. Herewith, the variation in the threshold voltage can be reduced, and it is possible to detect the occurrence of a predetermined offset voltage between the two input signals at high speed and with high accuracy.

Note that the voltage comparison circuit of the first embodiment may be incorporated into a semiconductor integrated circuit, and such a semiconductor integrated circuit may be used in various electronic devices having predetermined functions.

This application is based on Japanese Patent Application No. 2008-032706 filed on Feb. 14, 2008, the contents of which are hereby incorporated herein by reference.