CONDUCTIVE PILLAR BUMP AND MANUFACTURING METHOD THEREFORE

A conductive pillar bump includes a first conductive portion and a second conductive portion. The second conductive portion is located on the first conductive portion. A sidewall of the second conductive portion has at least one trench. The trench extends from a top portion of the second conductive portion to a bottom portion of the second conductive portion. The trench exposes a portion of a top surface of the first conductive portion.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a semiconductor device and a manufacturing method thereof, and particularly relates to a conductive pillar bump and a manufacturing method thereof.

Description of Related Art

Currently, there are several die attach methods for flip chip bonding technology. Among them, controlling the bonding state of bump in the flip chip bonding process is the key to controlling the yield. For example, in the flip chip bonding process, the solder will be squeezed by the bump (such as the copper pillar bump). When the amount of solder (such as tin) is large, the solder will be squeezed out too much, thus causing the problem of bridging of adjacent solders. In addition, when the amount of solder is too small, it is easy to cause empty welding, or bump cracks occur in the subsequent reliability experiment due to the lack of solder as a buffer.

SUMMARY OF THE INVENTION

The invention provides a conductive pillar bump and a manufacturing method thereof, which can better control the bonding of the bump to improve the yield.

The invention provides a conductive pillar bump, which includes a first conductive portion and a second conductive portion. The second conductive portion is located on the first conductive portion. A sidewall of the second conductive portion has at least one trench. The trench extends from a top portion of the second conductive portion to a bottom portion of the second conductive portion. The trench exposes a portion of a top surface of the first conductive portion.

The invention provides a method of manufacturing a conductive pillar bump, which includes the following steps. A substrate structure is provided. A first patterned photoresist layer is formed on the substrate structure. The first patterned photoresist layer has a first opening exposing the substrate structure. A first conductive portion is formed on the substrate structure exposed by the first opening. The first patterned photoresist layer is removed. A second patterned photoresist layer is formed on the substrate structure. The second patterned photoresist layer has a second opening exposing the first conductive portion. The second patterned photoresist layer includes at least one protrusion. The protrusion covers a portion of a top surface of the first conductive portion. A second conductive portion is formed on the first conductive portion exposed by the second opening. A sidewall of the second conductive portion has at least one trench. The trench extends from a top portion of the second conductive portion to a bottom portion of the second conductive portion. The second patterned photoresist layer is removed so that the trench exposes the portion of the top surface of the first conductive portion.

The invention provides another method of manufacturing a conductive pillar bump, which include the following steps. A substrate structure is provided. A conductive pillar bump is formed on the substrate structure by a three-dimensional (3D) printing method. The conductive pillar bump includes a first conductive portion and a second conductive portion. The second conductive portion is located on the first conductive portion. A sidewall of the second conductive portion has at least one trench. The trench extends from a top portion of the second conductive portion to a bottom portion of the second conductive portion. The trench exposes a portion of a top surface of the first conductive portion.

Based on the above description, in the conductive pillar bump and its manufacturing method according to the invention, the sidewall of the second conductive portion has at least one trench, and the trench exposes a portion of the top surface of the first conductive portion. Therefore, in the flip chip bonding process, the trench on the second conductive portion can provide more area for solder to attach, thereby reducing the amount of solder squeezed out. In addition, the portion of the top surface of the first conductive portion exposed by the trench can be used as a blocking portion for blocking the solder. Therefore, the portion of the top surface of the first conductive portion exposed by the trench can be used to determine the attachment height of the solder, so that the amount of solder squeezed out can be further controlled. In this way, the bump bonding process can be better controlled to improve the yield.

In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, several exemplary embodiments accompanied with figures are described in detail below.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1AtoFIG. 1Fare cross-sectional views illustrating a manufacturing process of a conductive pillar bump according to an embodiment of the invention.FIG. 2AtoFIG. 2Fare top views of a patterned photoresist layer and/or a conductive portion inFIG. 1AtoFIG. 1F, respectively.FIG. 1AtoFIG. 1Fare cross-sectional views taken along a section line I-I′ inFIGS. 2A to 2F.FIG. 3is a top view of a conductive pillar bump according to another embodiment of the invention.FIG. 4is a perspective view of the conductive pillar bump inFIG. 1F.

Referring toFIG. 1AandFIG. 2A, a substrate structure100is provided. For example, the substrate structure100may be a die. The substrate structure100may include a substrate102, and may further include at least one of a pad104, a passivation layer106, and an under bump metallization (UBM) layer108, but the invention is not limited thereto. The substrate102may be a semiconductor substrate such as a silicon substrate. In addition, a required semiconductor device (e.g., an active device or a passive device) (not shown) and a required interconnect structure (not shown) electrically connected to the semiconductor device may be formed on the substrate102according to requirements. The pad104may be located on the substrate102and may be electrically connected to the semiconductor device by the interconnect structure. The material of the pad104may include aluminum. The passivation layer106may be located on the substrate102. The material of the passivation layer106may include polyimide (PI) or polybenzoxazole (PBO). Furthermore, the passivation layer106may cover a portion of the pad104. That is, the passivation layer106may expose a portion of the pad104. The UBM layer108may be located on the pad104and the passivation layer106. The material of the UBM layer108may include aluminum, titanium, copper, nickel, tungsten, chromium, gold, tungsten titanium, tin-lead, nickel-vanadium, and/or an alloy thereof.

A patterned photoresist layer110is formed on the substrate structure100. The patterned photoresist layer110has an opening OP1exposing the substrate structure100. In the present embodiment, the opening OP1may expose the UBM layer108of the substrate structure100, but the invention is not limited thereto. The patterned photoresist layer110may be formed by a lithography process.

Referring toFIG. 1BandFIG. 2B, a conductive portion P1is formed on the substrate structure100exposed by the opening OP1. In the present embodiment, the conductive portion P1is, for example, formed on the UBM layer108of the substrate structure100, but the invention is not limited thereto. The conductive portion P1has the maximum diameter D1(FIG. 2B). The material of the conductive portion P1may include copper, silver, gold, or an alloy thereof. The method of forming the conductive portion P1is, for example, an electrochemical plating (ECP) method, an evaporation method, an electroplating method, or a printing method.

Referring toFIG. 1CandFIG. 2C, the patterned photoresist layer110is removed. The method of removing the patterned photoresist layer110is, for example, a dry stripping method or a wet stripping method.

Referring toFIG. 1DandFIG. 2D, a patterned photoresist layer112is formed on the substrate structure100. The patterned photoresist layer112has an opening OP2exposing the conductive portion P1. The patterned photoresist layer112includes at least one protrusion112a. The protrusion112acovers a portion of the top surface TS of the conductive portion P1. In the present embodiment, the number of the protrusions112ais, for example, plural, but as long as the number of the protrusions112ais at least one, it falls within the scope of the invention. The patterned photoresist layer112may be formed by a lithography process.

Referring toFIG. 1EandFIG. 2E, a conductive portion P2is formed on the conductive portion P1exposed by the opening OP2. For example, the bottom portion BP of the conductive portion P2may be located on the top surface TS of the conductive portion P1. The sidewall of the conductive portion P2has at least one trench T. The trench T extends from the top portion TP of the conductive portion P2to the bottom portion BP of the conductive portion P2. In the present embodiment, the number of the trenches T is, for example, plural, but as long as the number of the trenches T is at least one, it falls within the scope of the invention. The trenches T may be arranged symmetrically or asymmetrically.

In the present embodiment, the conductive portion P1and the conductive portion P2may be independent components. That is, the conductive portion P1and the conductive portion P2are formed by different processes rather than being formed continuously, but the invention is not limited thereto. The conductive portion P1and the conductive portion P2may be the same material or different materials. The material of the conductive portion P2may include copper, silver, gold, or an alloy thereof. The method of forming the conductive portion P2is, for example, an electrochemical plating method, an evaporation method, an electroplating method, or a printing method.

In addition, the conductive portion P2has the maximum diameter D2(FIG. 2E). The maximum diameter D2of the conductive portion P2may be less than or equal to the maximum diameter D1of the conductive portion P1(FIG. 2B). In the present embodiment, the maximum diameter D2of the conductive portion P2is, for example, equal to the maximum diameter D1of the conductive portion P1, but the invention is not limited thereto. In other embodiments, as shown inFIG. 3, the maximum diameter D2of the conductive portion P2may be less than the maximum diameter D1of the conductive portion P1. Furthermore, the shapes and the sizes of the conductive portion P1and the conductive portion P2may be adjusted by the opening OP1of the patterned photoresist layer110and the opening OP2of the patterned photoresist layer112according to the product requirements, and are not limited to what is shown in the drawings.

Referring toFIG. 1FandFIG. 2F, the patterned photoresist layer112is removed so that the trench T exposes the portion of the top surface TS of the conductive portion P1. The method of removing the patterned photoresist layer112is, for example, a dry stripping method or a wet stripping method.

A portion of the UBM layer108not covered by the conductive portion P1may be removed by using the conductive portion P1as the mask layer. That is, only the UBM layer108under the conductive portion P1is left. A portion of the UBM layer108may be removed by an etching process such as wet etching. In the present embodiment, the UBM layer108covers a portion of the top surface of the passivation layer106, but the invention is not limited thereto. In other embodiments, the UBM layer108may not cover the top surface of the passivation layer106. The shape and the size of the UBM layer108may be determined by the shape and the size of the conductive portion P1as the mask layer. In another embodiment, a portion of the UBM layer108not covered by the conductive portion P1may be removed by using an additionally formed mask layer as a mask. In this case, the shape and the size of the UBM layer108may be determined by the shape and the size of the additionally formed mask layer.

Hereinafter, the conductive pillar bump CP of the present embodiment is described with reference toFIG. 1F,FIG. 2F, andFIG. 4. In addition, although the method of forming the conductive pillar bump CP is described by taking the above method as an example, the invention is not limited thereto. In other embodiments, the conductive pillar bump CP may be formed on the substrate structure100by using the 3D printing method. In the case where the conductive pillar bump CP is formed by the 3D printing method, the conductive portion P1and the conductive portion P2may be integrally formed. That is, the conductive portion P1and the conductive portion P2may be continuously formed by the same 3D printing process.

Referring toFIG. 1F,FIG. 2F, andFIG. 4, the conductive pillar bump CP includes a conductive portion P1and a conductive portion P2. The conductive portion P2is located on the conductive portion P1. The sidewall of the conductive portion P2has at least one trench T. The trench T extends from the top portion TP of the conductive portion P2to the bottom portion BP of the conductive portion P2. The trench T exposes the top surface TS of the conductive portion P1. In the present embodiment, the bottom surface BS of the conductive portion P1is, for example, a convex surface (FIG. 1F), but the invention is not limited thereto. In other embodiments, the bottom surface BS of the conductive portion P1may be a flat surface. Moreover, the material, the arrangement, and the forming method of each component of the conductive pillar bump CP have been described in detail in the aforementioned embodiments, and the description thereof are not repeated here.

FIG. 5is a schematic view of a flip chip bonding process according to an embodiment of the invention.

Hereinafter, an embodiment of the flip chip bonding process using the conductive pillar bump CP is described with reference toFIG. 5. Referring toFIG. 5, during the flip chip bonding process, the substrate structure100(die) is first aligned with the die200. In addition, the conductive pillar bump CP is disposed on the substrate structure100, and a solder202is disposed on the die200. Then, the conductive pillar bump CP and solder202are bonded.

Based on the above embodiments, in the conductive pillar bump CP, the sidewall of the conductive portion P2has at least one trench T, and the trench T exposes a portion of the top surface TS of the conductive portion P1. Therefore, in the flip chip bonding process, the trench T on the conductive portion P2can provide more area for the solder202to attach, thereby reducing the amount of the solder202squeezed out. In addition, the portion of the top surface TS of the conductive portion P1exposed by the trench T can be used as a blocking portion for blocking the solder202. Therefore, the portion of the top surface TS of the conductive portion P1exposed by the trench T can be used to determine the attachment height of the solder202, so that the amount of the solder202squeezed out can be further controlled. In this way, the bump bonding process can be better controlled to improve the yield.

In summary, in the conductive pillar bump and its manufacturing method of the aforementioned embodiments, since the conductive pillar bump has a trench and a blocking portion, the amount of solder squeezed out can be reduced by the trench, and the amount of solder squeezed out can be further controlled by the blocking portion, so that the bump bonding process can be better controlled to improve the yield.