Semiconductor memory device

A semiconductor memory device includes a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit line connected to each of the sub arrays; and a write/read circuit arranged to correspond to each of the sub arrays, writing data to the sub array, and reading data from the sub array, wherein a pair of the sub array and the write/read circuit is repeatedly arranged along the paired bit lines, allowing the data to be transferred via the write/read circuit and the paired bit lines.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2007-340103, filed on Dec. 28, 2007, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a static random access memory (SRAM) and particularly relates to a configuration of a write/read circuit and a structure of a bit line to which write/read data is transferred.

2. Description of the Related Art

An SRAM is a kind of a writable/readable memory (RAM) by random access and employs a flip-flop circuit or the like as a storage element. In recent years, it has been increasingly difficult to develop stably operating SRAMs following downsizing of integrated circuits.

If a magnitude of wirings (a design rule) forming the SRAM is made small, an irregularity in threshold voltage becomes conspicuous among transistors constituting the flip-flop circuit. This results in operation failures such as deterioration in stability of various operations performed by the SRAM and deterioration in writing characteristic. Particularly for the SRAM, improvement in stability and improvement in writing characteristic are in a tradeoff relationship. For this reason, it is disadvantageously quite difficult to improve both the stability and the writing characteristic.

To solve the problem, there is known a method of dividing a bit line used to write or read data to or from a storage element into a plurality of bit lines and further providing a dedicated bit line for data transfer, as disclosed in Japanese Patent Application Laid-Open No. 59-165292. The method disclosed in the Japanese Patent Application Laid-Open No. 59-165292 has the following problems. An area of peripherals of memory cells disadvantageously increases, thus deteriorating area efficiency of the entire SRAM.

For these reasons, it is disadvantageously difficult to downsize the SRAM so as to improve operation stability and writing characteristic according to the conventional technique.

SUMMARY OF THE INVENTION

A semiconductor memory device according to the present invention includes: a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit line connected to each of the sub arrays; and a write/read circuit arranged to correspond to each of the sub arrays, writing data to the sub array, and reading data from the sub array, wherein a pair of the sub array and the write/read circuit is repeatedly arranged along the paired bit lines, allowing the data to be transferred via the write/read circuit and the paired bit lines.

DETAILED DESCRIPTION OF THE EMBODIMENTS

A semiconductor memory device according to embodiments of the present invention will be described hereinafter with reference to the accompanying drawings.

First Embodiment

FIG. 1is a partial configuration diagram of a memory cell array10and a dummy circuit70constituting a semiconductor memory device (hereinafter, “SRAM”) according to a first embodiment of the present invention. As shown inFIG. 1, the memory cell array10includes a plurality of sub arrays SAs in each of which a plurality of memory cells MCs are arranged.

FIG. 2is a partial configuration diagram of each memory cell MC. The memory cell MC includes two current paths103arranged bilaterally symmetrically to each other and each formed by connecting a pMOS transistor101and an nMOS transistor102in series. The left current path103will be referred to as “current path103L” and the right current path103will be referred to as “current path103R” hereinafter. If the both current paths103are generically referred to, they will be denoted by103without giving symbol L or R. The same is true of the other constituent elements (101,102, and104).

A second main electrode of a selection transistor104is connected to a node N10to which first main electrodes of the pMOS transistor101and the nMOS transistor102are connected in each current path103. Further, gate electrodes of the pMOS transistor101R and the nMOS transistor102R forming the right current path103R are connected to the node N10L of the left current path103L. Likewise, gate electrodes of the pMOS transistor101L and the nMOS transistor102L forming the left current path103L are connected to the node N10R of the right current path103R.

A first main electrode of the selection transistor104connected to each current path103is connected to one of paired bit lines BLs and a gate electrode thereof is connected to a word line WL in common. It is assumed, for example, that the first main electrode is a drain electrode and the second main electrode is a source electrode. While the 6-Tr SRAM is employed in the first embodiment, a 4-Tr 2-R SRAM or an SRAM of the other type may be employed.

Referring back toFIG. 1, the semiconductor memory device according to the first embodiment will be continuously described.

A plurality of memory cells MCs is connected to paired bit lines BLs and constitute one sub array SA. A write/read circuit50is arranged to correspond to each of a plurality of sub arrays SAs. The sub arrays SAs and corresponding write/read circuits50are repeatedly formed along a direction of bit lines BLs (“first direction”). Data can be thereby transferred between the paired bit lines BLs divided in each of a plurality of sub arrays SAs.

In this way, the memory cell array10is formed such that the write/read circuits50couple a plurality of sub arrays SAs to be repeatedly formed. As shown inFIG. 1, the sub arrays SAs arranged in the same first direction are coupled by the write/read circuits50and a plurality of groups of the coupled sub arrays SAs are arranged along a direction of word lines WLs (“second direction”). For convenience of description, the groups of sub arrays SAs will be referred to as one to n columns, respectively. An input buffer, not shown, is connected to an uppermost stage of each column and an output buffer, not shown, is connected to a lowermost stage thereof.

Therefore, in the first embodiment, the divided paired bit lines BLs are also used to transfer data to the output buffer, not shown. It is to be noted that a plurality of paired bit lines BLs are all formed on the same wiring layer.

A conventional SRAM employs a dedicated bit line formed on another wiring layer so as to transfer data held in each memory cell MC to an output buffer. In the first embodiment, in contrast, fewer wiring layers than those of the conventional SRAM can be formed because of use of the divided paired bit lines BLs for data transfer.

An internal configuration of the memory cell array10constituting the SRAM according to the first embodiment will be described next with reference toFIGS. 3A to 3D.FIG. 3Ais a partial plan view of the memory cell array10andFIGS. 3B to 3Dare plan views showing wiring layers of the memory cell array10shown inFIG. 3A, respectively. InFIGS. 3B to 3D, an upper wiring layer relative to that shown inFIG. 3Dis shown inFIG. 3Cand an upper wiring layer relative to that shown inFIG. 3Cis shown inFIG. 3B.FIG. 3Ashows portions in which the write/read circuits50couple the memory cells MCs arranged along the first direction. Accordingly, inFIG. 3A, regions89in which the memory cells MCs are formed and a region90in which the write/read circuits50are formed are present.

The memory cell array10includes an N-type diffusion layer80and a P-type diffusion layer81formed in a well91of a silicon substrate (hereinafter, simply “substrate”). Furthermore, gate lines82are formed to cross the diffusion layers80and81.FIG. 3Dshows the diffusion layers80and81, the gate lines82, and contact plugs CPs coupling the diffusion layers81and81and the gate lines82to a first wiring layer83shown inFIG. 3C, which are formed on a surface layer of the substrate.

FIG. 3Cshows the first wiring layer83and contact plugs CP2coupling the first wiring layer83to second wiring layers84to88shown inFIG. 34. Furthermore, positions of the contact plugs CPs coupling the surface layer of the substrate shown inFIG. 3Dto the first wiring layer83are indicated by dotted line identical in shape to the contact plugs CPs shown inFIG. 3D, respectively. For example, a contact plug CP[0] shown inFIG. 3Dis connected to a position of a contact plug CP[0] indicated by a dotted line inFIG. 3C, and a contact plug CP[1] shown inFIG. 3Dis connected to a position of a contact plug CP[1] indicated by a dotted line inFIG. 3C. The same is true of contact plugs CP[2] to CP[4]. The other contact plugs CPs are connected to dotted lines indicated at positions corresponding to the contact plugs CPs shown inFIG. 3D, respectively.

FIG. 3Bshows bit lines84, VDD lines85, VSS lines86, word lines87, and signal lines Pre88formed on the second wiring layer. Similarly toFIG. 3C, positions of the contact plugs CP2coupling the first wiring layer83to the second wiring layers84to88are indicated by dotted lines identical in shape to the contact plugs CP2shown inFIG. 3C, respectively.

A configuration of each of the write/read circuits50will be described next.FIG. 4is a configuration diagram of the write/read circuit50. The write/read circuit50formed between sub arrays SA[i] and SA[i+1] will be described by way of example.

The sub array SA[i] is connected to bit lines BL[2i−1] and BL[2i] and the sub array SA[i+1] is connected to bit lines BL[2i+1] and BL[2i+2].

The write/read circuit50is configured to include a first current path50A and a second current path50B. The first current path50A is formed by connecting a pMOS transistor101, a first nMOS transistor102, and a second nMOS transistor103in series in this order. The bit line BL[2i−1] is connected to a gate electrode of the first nMOS transistor102. The bit line BL[2i+1] is connected to first main electrodes of the pMOS transistor101and the first nMOS transistor102. A signal line Pre[i] is connected to gate electrodes of the pMOS transistor101and the second nMOS transistor102. A first voltage is applied to the signal line Pre[i] if data is to be transferred to the bit line BL[2i+1] and a second voltage is applied thereto if the bit line BL[2i+1] is to be precharged. For example, the first voltage is 3 volts (V) and the second voltage is 0 V. The first voltage may be higher than 3 V and the second voltage may be lower than 0 V. For example, the first main electrode is a drain electrode and the second main electrode is a source electrode.

As shown inFIG. 4, the second current path50B is formed bilaterally symmetrical to the first current path50A about the signal line Pre[i]. The bit line BL[2i] is connected to a position symmetrical to that of the bit line BL[2i−1] and the bit line BL[2i+2] is connected to a position symmetrical to that of the bit line BL[2i+1].

The signal line Pre[i] is connected to the dummy circuit70. The relationship between the dummy circuit70and the memory cell array10will now be described with reference toFIGS. 1 and 4.

Similar to the memory cell array10, the dummy circuit70is formed by connecting a plurality of sub arrays SAs each formed by connecting a plurality of memory cells MCDs to a pair of bit lines BLD[i−1] and BLD[i] along the first direction. Although it is preferable that the number of memory cells MCDs forming each sub array SA of the dummy circuit70is equal to that of memory cells MCs forming each sub array SA of the memory cell array10, the former number may be smaller than the latter number.

A configuration of the dummy circuit70differs from that of the memory cell array10in that not the write/read circuits50but inverters71couple a plurality of sub arrays SAs. As shown inFIG. 1, in the dummy circuit70, a plurality of sub arrays SAs are coupled to one another by two inverters71connected in series. It is to be noted that the inverters71coupling the sub arrays SA are arranged on one of the paired bit lines BLDs constituting the sub arrays SAs.

As shown inFIG. 1, the signal line Pre[i] is connected in common to the gate electrodes of the MOS transistors in each of the write/read circuits50arranged along the second direction in the memory cell array10. It is necessary to supply data inverted from data stored in each of the memory cells MCs of the dummy circuit70to the gate electrodes of the MOS transistors in each write/read circuit50. Due to this, one inverter71is connected in series to the signal line Pre[i]. Although the number of inverters71connected in series to the signal line Pre[i] is one in the first embodiment, the number of inverters71may be an odd number other than one.

Write/read operations performed by the SRAM according to the first embodiment will be described next with reference toFIGS. 1,5A,5B, and6.FIG. 5Ais a timing chart of the read operation andFIG. 5Bis a truth table related to the read operation. The read operation will first be described while referring to an instance of reading data from a memory cell MC[0] in the sub array SA[i] shown inFIG. 1by way of example.

As shown inFIG. 5A, before timing t0, that is, on standby, all bit lines BLs are in a precharge state (“1” state”). At the timing t0, a read voltage RV is applied to a word line WL[0] connected to the memory cell MC[0]. Accordingly, at timing t1, data read from the memory cell MC[0] is output to the bit lines BL[2i−1] and BL[2i]. For example, “1” is output to the bit line BL[2i−1] and “0” is output to the bit line BL[2i].

Next, the read data is transferred to the output buffer, not shown, connected to the lowermost stage of the column. Accordingly, the read data is transferred to the bit lines BL[2i+1] and BL[2i+2] connected to the sub array SA[i+1] that is the next stage to the sub array SA[i]. To transfer data on the bit lines BL[2i−1] and BL[2i] to the bit lines BL[2i+1] and BL[2i+2], it is necessary to set the signal line Pre[i] to “1”. Accordingly, it is necessary to set the bit line BLD[i] in the dummy circuit70to “0”. It is to be noted that the paired bit lines BLDs forming the dummy circuit70are similarly in the precharge state (“1” state) on standby.

Fixed data for always setting the bit line BLD[i] to “0” is held in all the memory cells MCDs in the dummy circuit70. The data held in the memory cells MCDs may be read to set the bit line BLD[i] to “0”.

As can be understood, if data is to be transferred from the bit lines BL[2i−1] and BL[2i] to the bit lines BL[2i+1] and BL[2i+2], the data held in the memory cells MCDs connected to the bit lines BLD[i] in the dummy circuit70is read. By doing so, the signal line Pre[i] turns into “1” at timing t2, and the data inverted from the data output to the bit lines BL[2i−1] and BL[2i] is transferred to the bit lines BL[2i+1] and BL[2i+2]. The operation is repeatedly performed and the data is eventually transferred to the output buffer, not shown, connected to the lowermost stage of the column.

As shown inFIG. 5A, it is necessary to control the dummy circuit70so as to set the signal line Pre[i] to “1” after the data read from the memory cell MC[0] is completely reflected on the bit lines BL[2i−1] and BL[2i]. The reason is as follows. If the signal line Pre[i] is set to “1” before the data read from the memory cell MC[0] is completely reflected on the bit lines BL[2i−1] and BL[2i], data inverted from the precharged data (“1” and “1”) is transferred to the bit lines BL[2i+1] and BL[2i+2]. To prevent this, it is necessary to control the dummy circuit70so as to set the signal line Pre[i] to “1” after the data “1” and “0” to be transferred is completely reflected on the bit lines BL[2i−1] and BL[2i].

Furthermore, it is necessary to set an output from the write/read circuit50, which is arranged on an upper stage relative to the memory cell MC[0] from which data is to be read, to a high impedance. The reason is as follows. If the output from the write/read circuit50arranged on the upper stage relative to the memory cell MC[0] is set to a certain voltage, data may possibly be erroneously written to the memory cell MC[0] by the certain voltage.

FIG. 6is a timing chart of the write operation. The write operation will be described with reference to an instance of writing data to the memory cell MC[0] in the sub array SA[i+1] shown inFIG. 1by way of example.FIG. 6shows a state in which write data is transferred to the bit lines BL[2i−1] and BL[2i] and a state after the transfer state.

At timing t0, the write data is transferred to the bit lines BL[2i−1] and BL[2i]. After the data is completely transferred, the signal line Pre[i] is set to “1” and the data is transferred to the bit lines BL[2i+1] and BL[2i+2] at timing t1. Further, a write voltage WV is applied to the word line WL[0] to which the memory cell MC[0] is connected, thereby writing the data to the memory cell MC[0]. It is to be noted that the write/read circuit50does not perform transfer operation and the data is not transferred after the data is written to the memory cell MC[0].

Second Embodiment

FIG. 7is a partial configuration diagram of a memory cell array130constituting an SRAM according to a second embodiment of the present invention. As shown inFIG. 7, the memory cell array130includes a plurality of sub arrays SAs in each of which a plurality of memory cells MCs are arranged. In this respect, the second embodiment is similar to the first embodiment.

FIG. 8is a configuration diagram of each write/read circuit150. The write/read circuit150formed between sub arrays SA[n] and SA[n+1] will be described by way of example. The sub array SA[n] is connected to bit lines BL[2n−1] and BL[2n] and the sub array SA[n+1] is connected to bit lines BL[2n+1] and BL[2n+2]. As shown inFIG. 8, the write/read circuit150according to the second embodiment is configured to include a first current path150A and a second current path150B formed to be bilaterally symmetrical to the first current path150A.

The first current path150A is formed by connecting a first pMOS transistor101A, a second pMOS transistor101B, a third pMOS transistor101C, a first nMOS transistor102A, and a second nMOS transistor102B in series in this order. A main electrode of the third pMOS transistor101C is connected to a node N30to which the second pMOS transistor101B and the first nMOS transistor102A are connected. The bit line BL[2n−1] is connected to gate electrodes of the second pMOS transistor101B and the first nMOS transistor102A. The bit line BL[2n+1] is connected to the node N30. A signal line Pre[n] is connected to a gate electrode of the third pMOS transistor101C. A first voltage is applied to the signal line Pre[n] if data is to be transferred from the bit line BL[2n−1] to the bit line BL[2n+1]. A second voltage is applied to the signal line Pre[n] if the bit line BL[2n+1] is to be precharged. A signal line Transb[n] to which a third voltage is applied if data is to be transferred to the bit line BL[2n+1] is connected to a gate electrode of the first pMOS transistor101A. A signal line Trans[n] to which a fourth voltage is applied if data is to be transferred to the bit line BL[2n+1] is connected to a gate electrode of the second nMOS transistor102B. The first or fourth voltage is, for example, 3 V and the second or third voltages is, for example, 0 V. The first or fourth voltage may be a voltage higher than 3 V and the second or third voltage may be lower than 0 V.

As shown inFIG. 8, the second current path150B is formed to be bilaterally symmetrical to the first current path150A about the signal line Pre[n]. The bit line BL[2n] is connected to a position symmetrical to that of the bit line BL[2n−1] and the bit line BL[2n+2] is connected to a position symmetrical to that of the bit line BL[2n+1].

Write/read operations performed by the SRAM according to the second embodiment will be described next with reference toFIGS. 7,8, and9.FIG. 9is a truth table related to the read operation. The read operation will first be described, referring to an instance of reading data from a memory cell MC[0] in the sub array SA[n] shown inFIG. 7by way of example.

On standby, all bit lines BLs are in a precharge state (“1” state”). A read voltage RV is applied to a word line WL[0] (not shown) connected to the memory cell MC[0] from which data is to be read. Accordingly, data read from the memory cell MC[0] is output to the bit lines BL[2n−1] and BL[2n]. For example, “1” is output to the bit line BL[2n−1] and “0” is output to the bit line BL[2n]. The read operation according to the second embodiment is similar to that according to the first embodiment in these respects.

Next, the read data is transferred to an output buffer, not shown, connected to a lowermost stage of a column to which the sub array SA[n] belongs. Accordingly, the read data is transferred first to the bit lines BL[2n+1] and BL[2n+2]. To transfer data on the bit lines BL[2n−1] and BL[2n] to the bit lines BL[2n+1] and BL[2n+2], it is necessary to set the signal line Pre[n] to “1”, to set the signal line Transb[n] to “0”, and to set the signal line Trans[n] to “1”, as shown inFIG. 9. A controller, not shown, controls these settings.

Furthermore, it is necessary to set an output from the write/read circuit150arranged on an upper stage relative to the memory cell MC[0] from which data is to be read to a high impedance if the data is to be read from the memory cell MC[0]. Therefore, as shown inFIG. 9, if the output from the write/read circuit150is set to the high impedance, then the signal line Pre[n] is controlled to be set to “1”, the signal line Transb[n] is controlled to be set to “1”, and the signal line Trans[n] is controlled to be set to “0”.

Similar to the first embodiment, during the write operation, data is continuously transferred from an input buffer, not shown, connected to an uppermost stage of the column to the memory cell MC[0] to which write data is to be written. The transfer operation performed by the write/read circuit150during the write operation is similar to that during the read operation.

The embodiments of the present invention have been described so far. However, the present invention is not limited to the embodiments but various changes, modifications, replacements, additions, deletions and the like can be made of the present invention within the scope of the spirit of the present invention.