Semiconductor device and semiconductor device manufacturing method

A semiconductor device according to the present invention includes a semiconductor substrate, and an interlayer dielectric film, formed on the semiconductor substrate, having a multilayer structure of a compressive stress film and a tensile stress film.

TECHNICAL FIELD

The present invention relates to a semiconductor device, particularly a power semiconductor device and a method of manufacturing the same.

BACKGROUND ART

In recent years, a power semiconductor device (hereinafter referred to as a “transformer device”) including a transformer has been developed in the field of power electronics.

FIG. 5is a schematic sectional view of a transformer device.

A transformer device101includes a first wiring layer102made of SiO2(silicon oxide) on an unshown semiconductor substrate.

A first wiring trench103is formed in the first wiring layer102. A first wire105made of a metallic material (hereinafter referred to as a “Cu wire material”) mainly composed of Cu (copper) is embedded in the first wiring trench103through a barrier metal104. A coil groove106, spiral in plan view, having the same depth as the first wiring trench103is formed in the first wiring layer102at an interval from the first wiring trench103. A first coil108is embedded in the coil grove106through a barrier metal107.

A diffusion preventing/etching stopper film109made of SiN and an interlayer dielectric film110made of SiO2are stacked on the first wiring layer102. Further, an etching stopper film111made of SiN and a second wiring layer112made of SiO2are stacked on the interlayer dielectric film110.

A second wiring trench113is formed in the second wiring layer112. The second wiring trench113is dug down from the upper surface of the second wiring layer112to the upper surface of the interlayer dielectric film110. A second wire115made of a Cu wire material is embedded in the second wiring trench113through a barrier metal114. A coil groove116, spiral in plan view, having the same depth as the second wiring trench.113is formed in the second wiring layer112at an interval from the second wiring trench113. A second coil118constituting a transformer along with the first coil108is embedded in the coil groove116through a barrier metal117.

The second wiring trench113is formed in a pattern having a portion intersecting with the first wire105in plan view. In the portion where the first wire105and the second wiring trench113(the second wire115) intersect with each other in plan view, a via hole119passing through the diffusion preventing/etching stopper film109and the interlayer dielectric film110is formed between the first wire105and the second wiring trench113. A via121is embedded in the via hole119through a barrier metal120. Thus, the first wire105and the second wire115are electrically connected with each other through the via121.

A diffusion preventing/etching stopper film122and an interlayer dielectric film123are stacked on the second wiring layer112.

PRIOR ART DOCUMENT

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

An extremely large potential difference is caused between the first coil108and the second coil118constituting the transformer. Therefore, the interlayer dielectric film110interposed between the first coil108and the second coil118must have a large thickness capable of exhibiting a withstand voltage (3500 V, for example) not causing dielectric breakdown resulting from the potential difference. In order to ensure dielectric strength of 3500 V for the interlayer dielectric film110, for example, the thickness of the interlayer dielectric film110must be about 5 μm, since the dielectric strength of SiO2is about 6 to 7 MV/cm.

However, the interlayer dielectric film110made of SiO2has compressive stress. If the interlayer dielectric film110has a large thickness, therefore, the semiconductor substrate causes remarkable warping deformation convexed on the side of the interlayer dielectric film110. If a matrix for the semiconductor substrate is a semiconductor wafer having a diameter of 300 mm, particularly remarkable warping deformation may be caused, and the semiconductor wafer may be impossible to handle.

An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, each capable of inhibiting a semiconductor substrate from causing warping deformation in such a structure that an interlayer dielectric film having a relatively large thickness is formed on the semiconductor substrate (a semiconductor wafer).

Means for Solving the Problems

A semiconductor device according to an aspect of the present invention includes a semiconductor substrate, and an interlayer dielectric film, formed on the semiconductor substrate, having a multilayer structure of a compressive stress film and a tensile stress film.

According to the structure, the interlayer dielectric film formed on the semiconductor substrate has the multilayer structure of the compressive stress film and the tensile stress film. Therefore, compressive stress of the compressive stress film and tensile stress of the tensile stress film cancel each other on the semiconductor substrate. Even if the interlayer dielectric film is formed in a relatively large thickness, therefore, the semiconductor substrate can be inhibited from causing warping deformation.

The interlayer dielectric film may have a multilayer structure of not less than three layers alternately repetitively formed by the compressive stress film and the tensile stress film. The compressive stress film and the tensile stress film are alternately stacked, so that the thickness of the interlayer dielectric film can be increased while inhibiting the semiconductor substrate from causing warping deformation.

The interlayer dielectric film may include a plurality of the compressive stress films. The semiconductor device may further include a first wire provided on a side of the interlayer dielectric film closer to the semiconductor substrate, a second wire opposed to the first wire through the interlayer dielectric film, and a plurality of vias, provided in via holes passing through the respective compressive stress films respectively, for electrically connecting the first wire and the second wire with each other.

In order to form the via holes in the compressive stress films, selective etching of the compressive stress films is performed. In order to embed the vias in the via holes, further, planarization (planarization by CMP (Chemical Mechanical Polishing), for example) of a material for the vias formed on the compressive stress films and the surfaces of the compressive stress films is performed. These treatments (steps) reduce the compressive stress of the compressive stress films. Therefore, the semiconductor substrate can be inhibited from causing warping deformation also by providing the vias on the compressive stress films.

In the case where the via holes are formed in the respective compressive stress films, the tensile stress film is preferably made of a material having etching selectivity with respect to the material for the compressive stress films. Thus, the tensile stress film can be utilized as an etching stopper in the etching for forming the via holes in the compressive stress films.

The vias may be made of a metallic material containing Cu, and in this case, the tensile stress film is preferably made of a material having a barrier property against Cu. Cu contained in the vias can be prevented from diffusing into the compressive stress films formed on the vias, due to the tensile stress film.

Further, the first wire may be made of a metallic material containing Cu, and in this case, the semiconductor device preferably further includes a barrier film, interposed between the interlayer dielectric film and the first wire, made of a material having a barrier property against Cu. Cu contained in the first wire can be prevented from diffusing into the interlayer dielectric film, due to the barrier film.

The barrier film preferably has tensile stress. The compressive stress of the compressive stress films of the interlayer dielectric film can be canceled, due to the tensile stress of the barrier film. Consequently, the semiconductor substrate can be more effectively inhibited from causing warping deformation.

A semiconductor device according to another aspect of the present invention includes a semiconductor substrate, an interlayer dielectric film, formed on the semiconductor substrate, having a multilayer structure of a plurality of first dielectric films, a first coil provided on a side of the interlayer dielectric film closer to the semiconductor substrate, a second coil, opposed to the first coil through the interlayer dielectric film, for constituting a transformer along with the first coil, and a plurality of vias provided in via holes passing through the respective first dielectric films respectively.

According to the structure, the interlayer dielectric film formed on the semiconductor substrate has the multilayer structure of the plurality of first dielectric films. The first coil and the second coil constituting the transformer are provided on the semiconductor substrate, and oppose to each other through the interlayer dielectric film. The via holes passing through the first dielectric films are formed in the respective first dielectric films, and the vias are embedded in the respective via holes.

In order to form the via holes in the first dielectric films, selective etching of the first dielectric films is performed. In order to embed the vias in the via holes, further, planarization (planarization by CMP, for example) of a material for the vias formed on the first dielectric films and the surfaces of the first dielectric films is performed. Even if the first dielectric films are compressive stress films having compressive stress, these treatments (steps) reduce the compressive stress of the first dielectric films. Even if the interlayer dielectric film is formed in a relatively large thickness, therefore, the semiconductor substrate can be inhibited from causing warping deformation.

The semiconductor device according to the other aspect can be manufactured by a manufacturing method including the following steps I to III:

I. a step of forming a first coil on a semiconductor substrate,

II. a step of forming an interlayer dielectric film having a multilayer structure of a plurality of first dielectric films on the first coil by repeating the steps of forming a first dielectric film, forming a via hole in the first dielectric film by etching, and embedding a via in the via hole in this order, and

III. a step of forming a second coil for constituting a transformer along with the first coil on a position opposed to the first coil through the interlayer dielectric film.

The interlayer dielectric film may include a second dielectric film, made of a material different from the material for the first dielectric films, between the first dielectric films. Preferably in this case, the first dielectric films are compressive stress films, and the second dielectric film is a tensile stress film. In other words, the interlayer dielectric film preferably has a multilayer structure of a plurality of compressive stress films and a tensile stress film. According to the structure, compressive stress of the compressive stress films and tensile stress of the tensile stress film cancel each other on the semiconductor substrate. Even if the interlayer dielectric film is formed in a relatively large thickness, therefore, the semiconductor substrate can be more inhibited from causing warping deformation.

The semiconductor device according to the other aspect may further include a first wire provided on the side of the interlayer dielectric film closer to the semiconductor substrate and a second wire opposed to the first wire through the interlayer dielectric film. In this case, the vias may electrically connect the first wire and the second wire with each other.

Alternatively, the vias may be dummy vias not contributing to the electrical connection between the first wire and the second wire.

The second dielectric film is preferably made of a material having etching selectivity with respect to the material for the first dielectric films. Thus, the tensile stress film can be utilized as an etching stopper in the etching for forming the via holes in the compressive stress films.

The vias may be made of a metallic material containing Cu, and in this case, the second dielectric film is preferably made of a material having a barrier property against Cu. Cu contained in the vias can be prevented from diffusing into the first dielectric films formed on the vias, due to the second dielectric film.

The first wire may be made of a metallic material containing Cu, and in this case, the semiconductor device preferably further includes a barrier film, interposed between the interlayer dielectric film and the first wire, made of a material having a barrier property against Cu. Cu contained in the first wire can be prevented from diffusing into the interlayer dielectric film, due to the barrier film.

The barrier film preferably has tensile stress. Compressive stress of the compressive stress films of the interlayer dielectric film can be canceled, due to the tensile stress of the barrier film. Consequently, the semiconductor substrate can be more effectively inhibited from causing warping deformation.

The vias are preferably formed by a single damascene process. In the single damascene process, a step of forming a via in a first dielectric film is separately carried out every first dielectric film, and selective etching and planarization of the first dielectric film are performed in each step. Therefore, the compressive stress of each first dielectric film can be reduced. Consequently, the semiconductor substrate can be effectively inhibited from causing warping deformation.

The foregoing and, other objects, features and effects of the present invention will become more apparent from the following detailed description of the embodiments with reference to the attached drawings.

MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention are now described in detail with reference to the attached drawings.

FIG. 1is a schematic sectional view of a semiconductor device according to an embodiment of the present invention.

A semiconductor device1is a transformer device, and includes a semiconductor substrate2. As the semiconductor substrate2, an Si (silicon) substrate, an SiC (silicon carbide) substrate or the like can be illustrated.

An etching stopper film3is stacked on the semiconductor substrate2. The etching stopper film3is made of SiN, and has tensile stress. The thickness of the etching stopper film3is 0.3 μm (=300 nm), for example.

A first wiring layer4is stacked on the etching stopper film3. The first wiring layer4is made of SiO2, and has compressive stress. The thickness of the first wiring layer4is 2.1 μm, for example.

A first wiring trench5is formed in the first wiring layer4. The first wiring trench5is in the form of a recess dug down from the upper surface of the first wiring layer4, and passes through the first wiring layer4and the etching stopper film3under the first wiring layer4.

A barrier metal6is formed on the inner surfaces (the side surfaces and the bottom surface) of the first wiring trench5. The barrier metal6has a structure obtained by stacking a Ta (tantalum) film, a TaN (tantalum nitride) film and a Ta film in this order from the side of the semiconductor substrate2. A first wire7made of a Cu wire material (a metallic material mainly composed of Cu) is embedded in the first wiring trench5through the barrier metal6. The surface of the first wire7is flush with the surface of the first wiring layer4. Cu contained in the first wire7is prevented from diffusing into the first wiring layer4, due to the barrier metal6.

In the first wiring layer4, a first coil groove8spiral in plan view is formed at an interval from the first wiring trench5. The first coil groove8has the same depth as the first wiring trench5, and passes through the first wiring layer4and the etching stopper film3under the first wiring film4.

A barrier metal9is formed on the inner surfaces (the side surfaces and the bottom surface) of the first coil groove8. The barrier metal9has the same multilayer structure as the barrier metal6formed on the inner side surfaces of the first wiring trench5. In other words, the barrier metal9has a structure obtained by stacking a Ta film, a TaN film and a Ta film in this order from the side of the semiconductor substrate. A first coil10made of a Cu wire material identical to the material for the first wire7is embedded in the first coil groove8through the barrier metal9. The surface of the first coil10is flush with the surface of the first wiring layer4. Cu contained in the first coil10is prevented from diffusing into the first wiring layer4, due to the barrier metal6.

A diffusion preventing/etching stopper film11is stacked on the first wiring layer4. The diffusion preventing/etching stopper film11is made of SiN, and has tensile stress. The thickness of the diffusion preventing/etching stopper film11is 0.3 μm, for example. Cu contained in the first wire7and the first coil10is prevented from diffusing into first dielectric films13described below, due to the diffusion preventing/etching stopper film11.

An interlayer dielectric film12is stacked on the diffusion preventing/etching stopper film11. The interlayer dielectric film12has such a multilayer structure that the first dielectric films13and a second dielectric film14are alternately stacked from the side of the semiconductor substrate2. More specifically, the interlayer dielectric film12has such a three-layer structure that the second dielectric film14is interposed between two first dielectric films13. That is, the interlayer dielectric film12does not include the etching stopper film3, an etching stopper film15(described later), a second wiring layer16(described later) and the first wiring layer4. The interlayer dielectric film12has a relatively large thickness, e.g., a thickness of 4.5 μm.

The first dielectric films13are made of SiO2, and have compressive stress. The thickness of each first dielectric film13is 2.1 μm, for example.

The second dielectric film14is made of SiN, and has tensile stress. The thickness of the second dielectric film14is 0.3 μm, for example.

An etching stopper film15is stacked on the interlayer dielectric film12. The etching stopper film15is made of SiN, and has tensile stress. The thickness of the etching stopper film15is 0.3 μm (=300 nm), for example.

A second wiring layer16is stacked on the etching stopper film15. The second wiring layer16is made of SiO2, and has compressive stress. The thickness of the second wiring layer16is 2.1 μm, for example.

A second wiring trench17is formed in the second wiring layer16. The second wiring trench17is in the form of a recess dug down from the upper surface of the second wiring layer16, and passes through the second wiring layer16and the etching stopper film15under the second wiring layer16.

A barrier metal18is formed on the inner surfaces (the side surfaces and the bottom surface) of the second wiring trench17. The barrier metal18has a structure obtained by stacking a Ta film, a TaN film and a Ta film in this order from the side of the semiconductor substrate2. A second wire19made of a Cu wire material (a metallic material mainly composed of Cu) is embedded in the second wiring trench17through the barrier metal18. The surface of the second wire19is flush with the surface of the second wiring layer17. Cu contained in the second wire19is prevented from diffusing into the first dielectric films13(the interlayer dielectric film12) and the second wiring layer16, due to the barrier metal18.

In the second wiring layer16, a second coil groove20spiral in plan view is formed at an interval from the second wiring trench17. The second coil groove20has the same depth as the second wiring trench17, and passes through the second wiring layer16and the etching stopper film15under the second wiring layer16.

A barrier metal21is formed on the inner surfaces (the side surfaces and the bottom surface) of the second coil groove20. The barrier metal21has the same multilayer structure as the barrier metal18formed on the inner surfaces of the second wiring trench17. In other words, the barrier metal21has a structure obtained by stacking a Ta film, a TaN film and a Ta film in this order from the side of the semiconductor substrate2. A second coil22made of a Cu wire material identical to the material for the second wire19is embedded in the second coil groove20through the barrier metal21. The surface of the second coil22is flush with the surface of the second wiring layer16. Cu contained in the second coil22is prevented from diffusing into the second wiring layer16, due to the barrier metal21.

The second wiring trench17is formed in a pattern having a portion intersecting with the first wire7in plan view. In the portion where the first wire7and the second wiring trench17intersect with each other in plan view, a plurality of vias23are provided in series therebetween.

More specifically, a via hole24is formed in each first dielectric film13of the interlayer dielectric film12. The via hole24formed in the first dielectric film13on the upper-layer side passes through the first dielectric film13, and further passes through the second dielectric film14under the first dielectric film13. The via hole24formed in the first dielectric film13on the lower-layer side passes through the first dielectric film13, and further passes through the diffusion preventing/etching stopper film11under the first dielectric film13. A barrier metal25is formed on the inner surface of each via hole24. The barrier metal25has a structure obtained by stacking a Ta film, a TaN film and a Ta film in this order from the side of the semiconductor substrate2. The via23made of a Cu wire material is embedded in each via hole24through the barrier metal25. Cu contained in the via23is prevented from diffusing into the first dielectric film13, due to the barrier metal25. The first wire7and the second wire19are electrically connected with each other through the vias23and the barrier metals25.

A diffusion preventing/etching stopper film26and an interlayer dielectric film27etc. are stacked on the second wiring layer16. The diffusion preventing/etching stopper film26is made of SiN, and has tensile stress. The thickness of the diffusion preventing/etching stopper film26is 0.3 μm, for example. Cu contained in the second wire19and the second coil22is prevented from diffusing into the interlayer dielectric film27, due to the diffusion preventing/etching stopper film metal26. The interlayer dielectric film27may have a multilayer structure similar to that of the interlayer dielectric film12, or may have a single-layer structure of SiO2.

One or a plurality of interlayer dielectric films may be interposed between the semiconductor substrate2and the etching stopper film3. In this case, each interlayer dielectric film may have a multilayer structure similar to that of the interlayer dielectric film12, or may have a single-layer structure of SiO2. Further, another wire may be formed under the first wire7. In this case, the first wire7is electrically connected with the wire under the first wire7through a via28, as shown inFIG. 1. Needless to say, the first wiring layer4may be formed in contact with the semiconductor substrate2, and the first wire7may be the lowermost wire.

FIGS. 2A to 2Nare schematic sectional views for illustrating a method of manufacturing the semiconductor device shown inFIG. 1.

As shown inFIG. 2A, the etching stopper film3and the first wiring layer4are stacked on the semiconductor substrate2by CVD (Chemical Vapor Deposition).

Then, the first wiring trench5and the first coil groove8are formed by photolithography and etching, as shown inFIG. 2B. At this time, the etching stopper film3is utilized as an etching stopper against etching of the first wiring layer4.

Thereafter a multilayer film (a Ta film, a TaN film and a Ta film)31made of the material for the barrier metals6and9is formed on the upper surface of the first wiring layer4and the inner surfaces of the first wiring trench5and the first coil groove8by sputtering, as shown inFIG. 2C. Then, a plating layer32made of a Cu wire material is formed on the multilayer film31by plating. The first wiring trench5and the first coil groove8are filled up with the plating layer32.

Then, the plating layer32and the multilayer film31are continuously polished by CMP, as shown inFIG. 2D. The polishing is continued until unnecessary portions of the plating layer32and the multilayer film31formed outside the first wiring trench5and the first coil groove8are entirely removed and the surface of the plating layer32buried in the first wiring trench5and the first coil groove8is flush with the surface (the upper surface) of the first wiring layer4. Thus, the first wire7embedded in the first wiring trench5through the barrier metal6and the first coil10embedded in the first coil groove8through the barrier metal9are obtained. At this time, the surface of the first wiring layer4is also slightly polished.

Thereafter the diffusion preventing/etching stopper film11and the first dielectric film13are successively stacked by CVD, as shown inFIG. 2E.

Then, the via23is formed by a single damascene process. More specifically, the via hole24is formed by photolithography and etching, as shown inFIG. 2F. At this time, the diffusion preventing/etching stopper film11is utilized as an etching stopper against etching of the first dielectric film13.

Thereafter a multilayer film (a Ta film, a TaN film and a Ta film)33made of the material for the barrier metal25is formed on the upper surface of the first dielectric film13and the inner surface of the via hole24by sputtering, as shown inFIG. 2G. Then, a plating layer34made of a Cu wire material is formed on the multilayer film33by plating. The via hole24is filled up with the plating layer34.

Then, the plating layer34and the multilayer film33are continuously polished by CMP, as shown inFIG. 2H. The polishing is continued until unnecessary portions of the plating layer34and the multilayer film33formed outside the via hole24are entirely removed and the surface of the plating layer34buried in the via hole24is flush with the surface (the upper surface) of the first dielectric film13. Thus, the via23embedded in the via hole24through the barrier metal25is obtained. At this time, the surface of the first dielectric film13is also slightly polished.

After the formation of the via23, the second dielectric film14and the first dielectric film13are successively stacked by CVD, as shown inFIG. 2I.

Then, through steps similar to the steps shown inFIGS. 2F to 2H, the via hole24is formed in the first dielectric film13on the upper-layer side and the via23is embedded in the via hole24through the barrier metal25, as shown inFIG. 2J. At this time, the second dielectric film14is utilized as an etching stopper against etching of the first dielectric film13.

After the formation of the via23, the etching stopper film15and the second wiring layer16are stacked on the first dielectric films13(the interlayer dielectric film12) by CVD, as shown inFIG. 2K.

Then, the second wiring layer17and the second coil groove20are formed by photolithography and etching, as shown inFIG. 2L. The etching stopper film15is utilized as an etching stopper against etching of the second wiring layer16.

Thereafter a multilayer film (a Ta film, a TaN film and a Ta film)35made of the material for the barrier metals18and21is formed on the upper surface of the second wiring layer16and the inner surfaces of the second wiring trench17and the second coil groove20by sputtering, as shown inFIG. 2M. Then, a plating layer36made of a Cu wire material is formed on the multilayer film35by plating. The second wiring trench17and the second coil groove20are filled up with the plating layer36.

Then, the plating layer36and the multilayer film35are continuously polished by CMP, as shown inFIG. 2N. The polishing is continued until unnecessary portions of the plating layer36and the multilayer film35formed outside the second wiring trench17and the second coil groove20are entirely removed and the surface of the plating layer36buried in the second wiring trench17and the second coil groove20is flush with the surface (the upper surface) of the second wiring layer16. Thus, the second wire19embedded in the second wiring trench17through the barrier metal18and the second coil22embedded in the second coil groove20through the barrier metal21are obtained. At this time, the surface of the second wiring layer16is also slightly polished.

Thereafter the diffusion preventing/etching stopper film26and the interlayer dielectric film27etc. are stacked on the second wiring layer16by CVD, and the semiconductor device1shown inFIG. 1is obtained.

As hereinabove described, the interlayer dielectric film12formed on the semiconductor substrate2has the three-layer structure in which the second dielectric film14is interposed between the two first dielectric films13. The first dielectric films13made of SiO2are compressive stress films. On the other hand, the second dielectric film14made of SiN is a tensile stress film. In other words, the interlayer dielectric film12has the multilayer structure of the compressive stress films and the tensile stress film. Therefore, compressive stress of the compressive stress films and tensile stress of the tensile stress film cancel each other on the semiconductor substrate2. Even if the interlayer dielectric film12is formed in a relatively large thickness, therefore, the semiconductor substrate2can be inhibited from causing warping deformation.

The interlayer dielectric film12may alternatively have a two-layer structure formed by the first dielectric film13and the second dielectric film14. In this case, the second dielectric film14can be substituted for the etching stopper film15, and hence the etching stopper film15may be omitted.

Each first dielectric film13is provided with the via hole24passing through the first dielectric film13, and the via23is embedded in each via hole24through the barrier metal25. In order to form the via23, selective etching of the first dielectric film13is performed (seeFIG. 2F). In order to embed the via23in the via hole24, further, polishing (planarization) of the plating layer34, made of the material for the via, formed on the first dielectric film13is performed, and the first dielectric film13is also slightly polished (planarized) at this time. These treatments (steps) reduce the compressive stress of the first dielectric film13. Therefore, the semiconductor substrate2can be inhibited from causing warping deformation also by embedding the via23in the first dielectric film13.

The second dielectric film14is made of SiN, and has etching selectivity with respect to SiO2, which is the material for the first dielectric film13. Therefore, the second dielectric film14can be utilized as an etching stopper in the etching for forming the via hole24in the first dielectric film13on the upper-layer side. Consequently, the via hole24can be accurately formed without causing a so-called overetching.

SiN has a barrier property against Cu, and hence Cu contained in the via23can be prevented from diffusing into the first dielectric film13on the via23, due to the second dielectric film14.

Further, the diffusion preventing/etching stopper film11interposed between the first wire7and the interlayer dielectric film12is made of SiN, and has a barrier property against Cu. Therefore, Cu contained in the first wire7can be prevented from diffusing into the interlayer dielectric film12(the first dielectric films13), due to the diffusion preventing/etching stopper film11.

In addition, the diffusion preventing/etching stopper film11has tensile stress. Therefore, the compressive stress of the first dielectric films13can be canceled also by the tensile stress of the diffusion preventing/etching stopper film11. Consequently, the semiconductor substrate2can be more effectively inhibited from causing warping deformation.

The interlayer dielectric film12formed on the semiconductor substrate2has the multilayer structure of the plurality of first dielectric films13. On the semiconductor substrate2, the first coil10and the second coil22constituting the transformer are provided to oppose to each other through the interlayer dielectric film12. Each first dielectric film13is provided with the via hole24passing through the first dielectric film13, and the via23is embedded in each via hole24.

In order to form the via23, the selective etching of the first dielectric film13is performed (seeFIG. 2F). In order to embed the via23in the via hole24, further, the polishing (planarization) of the plating layer34, made of the material for the via, formed on the first dielectric film13is performed, and the first dielectric film13is also slightly polished (planarized) at this time. These treatments (steps) reduce the compressive stress of the first dielectric film13. Even if the interlayer dielectric film12is formed in a relatively large thickness, therefore, the semiconductor substrate2can be inhibited from causing warping deformation by embedding the via23in the first dielectric film13.

The interlayer dielectric film12includes the second dielectric film14made of SiN between the first dielectric films13made of SiO2. The first dielectric films13made of SiO2are compressive stress films. On the other hand, the second dielectric film14made of SiN is a tensile stress film. In other words, the interlayer dielectric film12has the multilayer structure of the compressive stress films and the tensile stress film. Therefore, the compressive stress of the compressive stress films and the tensile stress of the tensile stress film cancel each other on the semiconductor substrate2. Thus, the semiconductor substrate2can be more inhibited from causing warping deformation.

Each via23is formed by the single damascene process. In the single damascene process, the step of forming the via23in the first dielectric film13is separately carried out every first dielectric film13, and the selective etching and the planarization of the first dielectric film13are carried out in each step. Therefore, the compressive stress of each first dielectric film13can be reduced. Consequently, the semiconductor substrate2can be effectively inhibited from causing warping deformation.

FIG. 3is a graph showing changes in the quantities of warping of semiconductor wafers before and after steps of etching compressive stress films.

Three semiconductor wafers (bare silicon wafers) having diameters of 300 mm which were matrices for the semiconductor substrates2were prepared, compressive stress films made of SiO2having thicknesses of about 8 μm, about 11 μm and about 13 μm respectively were formed on the surfaces of the three semiconductor wafers, and the quantity of warping (the height with respect to a plane) of each semiconductor wafer was measured before and after an etching step for forming a through-hole in each compressive stress film.FIG. 3shows the quantities of warping before the etching step with black circles, and shows the quantities of warping after the etching step with white circles.

It is understood from the results shown inFIG. 3that the quantity of warping of the semiconductor wafer after the etching step is smaller than the quantity of warping of the semiconductor wafer before the etching step, in whichever thickness the compressive stress film is formed.

After the etching step on the compressive stress film of about 13 μm, a tensile stress film made of SiN of 0.3 μm was formed on the compressive stress film, and the quantity of warping of the semiconductor wafer was measured. The quantity of warping at this time was about 300 μm on a side where the surface of the semiconductor wafer was convexed, and it is understood that the same was by far smaller than about 460 μm which was the quantity of warping before the formation of the tensile stress film.

FIG. 4is a graph showing the relation between the thicknesses of compressive stress films and the quantities of warping of semiconductor wafers.

A semiconductor wafer (a bare silicon wafer) having a diameter of 300 mm which was a matrix for the semiconductor substrate2was prepared, and in the process of forming a compressive stress film made of SiO2on the surface of the semiconductor wafer, the quantity of warping (the height with respect to a plane) of the semiconductor wafer was measured every time the thickness of the compressive stress film increased by 1.2 μm.FIG. 4shows the results of the measurement with white circles.

On the other hand, a tensile stress film made of SiN having a thickness of 0.3 μm was formed on the surface of another semiconductor wafer provided with a natural oxide film of 0.3 μm, and the quantity of warping of the semiconductor wafer after the formation of the tensile stress film was measured. The quantity of warping at this time was about 150 μm on a side where the surface of the semiconductor wafer was concaved. In the process of thereafter forming a compressive stress film made of SiO2on the tensile stress film, the quantity of warping of the semiconductor wafer was measured every time the thickness of the compressive stress film increased by 1.2 μm.FIG. 4shows the results of the measurement with black circles.

In a case where only a compressive stress film is formed on the surface of a semiconductor wafer, for example, warping deformation of not less than 200 μm is caused on the semiconductor wafer at a moment when the compressive stress film is formed up to a thickness of 2.4 μm. In a case where a tensile stress film is formed on the surface of a semiconductor wafer, on the other hand, warping deformation is hardly caused on the semiconductor wafer at a moment when a compressive stress film is formed up to a thickness of 2.4 μm. It is understood from the results that the semiconductor substrate2can be inhibited from causing warping deformation, due to the multilayer structure of the compressive stress films and the tensile stress film.

While the present invention has been described in detail by way of the embodiments thereof, it should be understood that these embodiments are merely illustrative of the technical principles of the present invention but not limitative of the invention. The spirit and scope of the present invention are to be limited only by the appended claims.

This application corresponds to Japanese Patent Application No. 2008-248903 and Japanese Patent Application No. 2008-248904 filed with the Japan Patent Office on Sep. 26, 2008, the entire disclosures of which are incorporated herein by reference.

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