Test system and methodology to improve stacked NAND gate based critical path performance and reliability

A test system and methodology to improve the performance and reliability of critical paths including stacked NAND gates with sub-minimum channel transistors employs one or more inverter based ring oscillators to generate reliability data. The reliability data is used to calibrate an aged transistor model, which describes the hot carrier reliability of sub-minimum channel length transistors. A computer simulation uses the calibrated, aged transistor model to simulate the critical path circuitry including the stacked NAND gates.

TECHNICAL FIELD
 The invention relates to testing integrated circuits and more particularly
 to evaluating performance and hot carrier reliability of critical path
 circuitry including transistors of different, very deep sub-micron channel
 lengths.
 BACKGROUND ART
 Due to hot carrier effects, which are pronounced in sub-micron geometries,
 there is a tradeoff between performance and reliability when selecting an
 appropriate channel length for field-effect transistors, such as MOSFETs
 or IGFETs. A shorter channel length creates a correspondingly greater
 electric field between the source and the drain of the transistor, which
 increases drive current (I.sub.D) On one hand, an increased drive current
 due to a shorter channel length is able to more rapidly charge or
 discharge the load capacitance of the transistor. Consequently, a circuit
 including the transistor can run at higher frequencies. On the other hand,
 an increased electric field, particularly near the drain region, causes an
 increase in "hot carrier" effects, in which accelerated electrons ionize
 the silicon lattice, generating pairs of electrons and holes. Over time,
 these hot carriers break bonds and become trapped, changing electrical
 properties of the transistor. In NMOS transistors, electron mobility is
 degraded, causing a reduction in the drive current and hence performance
 of the transistor.
 By industry convention, the lifetime of a transistor is the stress time
 that elapses until there is a 10% reduction in the drive current due to
 hot carrier effects. Compensating for the reduction in drive current by
 increasing the source-to-drain potential difference (V.sub.DS), however,
 increases local electric fields and rate of hot carrier degradation.
 In order to enhance microprocessor speed, we have been investigating the
 use of sub-minimum (i.e., very deep sub-micron, around 0.25 micron)
 channel length transistors in stacked NAND gate circuits, commonly part of
 a microprocessor's critical path. A critical path of a microprocessor is a
 series of interconnected gates, registers, and other elements through
 which a propagation delay is determinative of the processing speed of the
 microprocessor. Therefore, reducing the propagation delay of any element,
 for example, a NAND gate, in the critical path enables the microprocessor
 to execute at higher speeds.
 Referring to FIG. 1, depicted is a three-input stacked NAND gate 100
 implemented in CMOS technology, comprising three PMOS transistors 102,
 104, and 106 coupled in parallel and three NMOS transistors 112, 114, and
 116 coupled in series. The three-input stacked NAND gate 100 is merely
 illustrative, because stack NAND gates in a critical path of a
 microprocessor may comprise up to at least sixteen inputs. In a stacked
 NAND circuit, the V.sub.DS for each NMOS transistor is typically much less
 than the supply voltage, especially for the second and third transistors
 114 and 116. Since the associated hot carrier effects are smaller due to a
 smaller electric field, the performance of NMOS transistors 112, 114, and
 116 can be improved by reducing their channel lengths as much as possible
 while maintaining respective device lifetimes within acceptable norms,
 commonly specified at five or ten years. Since the V.sub.DS for each NMOS
 transistor 112, 114, and 116 is different from the others, performance and
 reliability can be improved by using different channel lengths for the
 transistors. For example, NMOS transistors 112, 114, and 116 may have
 channel lengths of 0.25 micron, 0.225 micron, and 0.2 micron,
 respectively. NMOS transistor 112 has the greatest potential difference,
 V.sub.DS, across it and hence the longest channel length.
 In microprocessor design, it is desirable to accurately predict the
 performance and reliability of the sub-minimum channel transistors in the
 stacked NAND gates in the critical path of the microprocessor. However,
 stacked NAND gates and other critical path circuitry are not easily found
 or readily available as test structures for evaluating hot carrier
 effects.
 SUMMARY OF THE INVENTION
 There exists a need for accurately predicting the performance and hot
 carrier reliability of circuitry including stacked NAND gates with
 sub-minimum channel length transistors. There is also a need for a testing
 methodology that can use readily available test structures.
 These and other needs are met by the present invention, which evaluates a
 circuit by simulation, using a transistor model calibrated by empirical
 data from a ring oscillator experiment. Ring oscillators are readily
 available test structures, and calibrating a transistor model in a hot
 carrier reliability simulation of an integrated circuit enables more
 accurate prediction of the performance and reliability of the circuit.
 Accordingly, one aspect of the invention is a method of analyzing an
 integrated circuit, such as a critical path for a microprocessor that
 includes a stack NAND gate having two or more NMOS transistors coupled in
 series, each with a channel length less than 0.5 micron, preferably less
 than 0.25 micron. The method comprises the step of fabricating one or more
 ring oscillators according to the fabrication technology of the integrated
 circuit. The method further comprises measuring reliability data, e.g.
 frequency degradation over time, from operating the one or more ring
 oscillators, calibrating a transistor model based on the reliability data,
 and simulating the integrated circuit according to the calibrated
 transistor model. Preferably, the reliability data is measured for a
 plurality of different stress voltages and channel lengths.
 According to another aspect of the invention, a test system for analyzing
 an integrated circuit to be fabricated according to a given fabrication
 technology comprises a circuit simulator, such as a computer programmed
 with simulation software, for simulating the integrated circuit according
 to an aged transistor model. The system includes one or more ring
 oscillators fabricated on a wafer, preferably with the integrated circuit,
 according to the given technology. A measurement system can be coupled to
 one of the ring oscillators for measuring reliability data, such as
 frequency degradation over time, from operating the ring oscillator for a
 prescribed period of time. A calibration system is configured to calibrate
 the aged transistor model based on the reliability data.
 Additional objects, advantages, and novel features of the present invention
 will be set forth in part in the description which follows, and in part,
 will become apparent to those skilled in the art upon examination or may
 be learned by practice of the invention. The objects and advantages of the
 invention may be realized and obtained by means of the instrumentalities
 and combinations particularly pointed out in the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
 A method and system for analyzing the performance and hot carrier
 reliability of an integrated circuit are described. In the following
 description, for purposes of explanation, numerous specific details are
 set forth in order to provide a thorough understanding of the present
 invention. It will be apparent, however to one skilled in the art that the
 present invention may be practiced without these specific details. In
 other instances, well-known structures and devices are shown in block
 diagram form in order to avoid unnecessarily obscuring the present
 invention.
 Hot Carrier Reliability Computer Simulation
 With reference to FIG. 6, an embodiment of the present invention employs a
 hot carrier reliability computer simulation, implemented on a programmed
 design simulating computer 600. Computer simulation is advantageous in the
 design and manufacture of integrated circuits, because design parameters
 620, e.g., gate widths and channel lengths of transistors, from an initial
 design 622, can be adjusted relatively inexpensively (as modified
 parameters 624) within an simulation environment until desired results are
 obtained within that environment. The resulting design 604 is then
 physically fabricated in an integrated chip or other physical
 implementation 630. Examples of software simulation packages include
 HSpice.TM. from Meta-Software, Inc. of Calif., or other "Spice"-type
 circuit simulators that are common in the industry and the BeRT.TM.
 reliability tool package from Berkeley Technology Associates of Calif.
 According to the invention, an integrated circuit is analyzed using a
 circuit simulator that employs an aged transistor model 602 for analyzing
 hot carrier reliability over time. An aged transistor model describes the
 behavior of a transistor over stress time, thus allowing for hot carrier
 degradation effects to be taken into account. In one embodiment, an aged
 transistor model contains stress time-dependent transistor parameters
 derived from repeatedly applying a BSIM (Berkeley Short-Channel IGFET
 Model) method once to fresh and stressed transistor devices.
 Alternatively, other appropriate methods for modeling a transistor may be
 used.
 An aged transistor model is produced according to one of these methods by
 measuring the I-V characteristics of a fresh transistor device, e.g.
 substrate current (I.sub.SUB), drive current (I.sub.D), gate voltage
 (V.sub.G), and source-to-drain voltage (V.sub.DS). The fresh transistor
 device is then aged by repeatedly applying a DC stress voltage for a
 plurality of time periods, after each of which the I-V characteristics of
 the device are measured again. This process is repeated for other stress
 voltages, which are typically greater than the normal operating voltage of
 the device in order to obtain a degradation detectable within a reasonable
 period of time, e.g. within 500-1000 hours. These sets of I-V curves are
 applied to a computer simulation model for ascertaining the transistor
 model parameters.
 The lifetime .tau. of a device is defined to be the time at which the
 percent degradation of the drive current due to hot carrier effects
 attains 10%. According to a well-known substrate current model, the
 lifetime .tau. of an NMOS transistor of a given channel length is also
 expressed by the following formula:
 ##EQU1##
 where W represents the width of the gate, H represents an empirical
 coefficient related to the manufacturing condition of the device, and m
 represents an empirical index correlated to impact ionization and
 generation of interface energy levels. Therefore, it is possible to
 estimate the lifetime of each NMOS device in an integrated circuit within
 a simulation environment by using equation (1) with H and m appropriately
 calibrated based on experimental results.
 If H and m are calibrated based on results of the DC stress test, the
 results of equation (1) may not match the actual degradation of an NMOS
 transistor in a stacked NAND gate, because the quasi-static approach of
 the DC stress test may not be valid under AC conditions. The DC stress
 model, furthermore, ignores additional factors, such as the contribution
 of PMOS transistors in the NAND gate. Therefore, it is desirable to
 calibrate these parameters according to AC stress conditions, preferably
 with readily available test structures.
 Using a Ring Oscillator Experiment to Calibrate a Hot Carrier Reliability
 Simulation
 A method of analyzing a circuit 604 including stacked NAND gate 606 uses a
 computer simulation calibrated by empirical data derived from an AC stress
 experiment on a ring oscillator 610 in accord with the invention. More
 specifically, the ring oscillator experiment provides data for more
 accurately calibrating computer simulation parameters, such as H and m.
 Referring to flowchart 200 of FIG. 2, one or more ring oscillators are
 fabricated in step 202 as test structures according to the same
 fabrication technology as implemented for the integrated circuit, e.g. a
 microprocessor, including a stacked NAND gate. These experimental ring
 oscillators may be manufactured on a portion of the same wafer of the
 integrated circuit under analysis so that processing variations similarly
 affect both the text structure and the batch. Preferably, a plurality of
 ring oscillators is fabricated so that a plurality of AC stress
 experiments can be performed with different combinations of stress
 voltages and channel length geometries.
 Referring to FIG. 3, depicted are portions of a 91-stage simple inverter
 based ring oscillator 300 according to one embodiment of the present
 invention. Persons of skill in the art will appreciate that implementation
 of the present invention is not limited to ninety-one (91) stages but may
 include any number of stages preferably odd, such as seventy-one (71), and
 one hundred one (101). Moreover, those skilled in the art will recognize
 that the number of output stages 320-1 to 320-3 can vary, for example,
 one, two, three, or more.
 Each stage of the ring oscillator preferably comprises a simple inverter.
 For example, stage 310-1 comprises a CMOS inverter including a PMOS
 transistor 312-1 and an NMOS transistor 314-1. Likewise, the other ring
 oscillator stages, 310-2 to 310-91, comprise CMOS inverters including PMOS
 transistors 312-2 to 312-91 and NMOS transistors 314-2 to 312-91,
 respectively. The channel lengths of the NMOS transistors 314-1 to 314-91
 of ring oscillator 300 are the same, preferably the same length as channel
 lengths of an NMOS transistor of a stacked NAND gate under analysis.
 However, other ring oscillators in the batch may employ NMOS transistor
 having a different, common channel length.
 Each inverter of the ring oscillator stages 310-1 to 310-91 receives a
 common supply voltage V.sub.ccI. The common supply voltage is generally
 greater than the normal operating voltage of the integrated circuit and
 remains constant throughout an AC stress experiment. Other AC stress
 experiments, however, on other ring oscillators will employ a different
 common supply voltage, as described in more detail hereinafter. The common
 supply voltage (V.sub.ccO) for output stages 320-1 to 320-3, preferably
 CMOS inverters with non-sub-minimum channel lengths, is lower to reduce
 the hot carrier effects on the output stage.
 After the ring oscillators are fabricated, an AC stress experiment is
 performed on a ring oscillator. Preferably, a plurality of AC stress
 experiments can be performed with different combinations of stress
 voltages, e.g 3.3V and 5.5V, and channel length geometries. e.g. 0.25
 micron, 0.225 micron, and 0.2 micron. When each AC stress experiment on a
 ring oscillator is performed, the ring oscillator is set running at a
 given stress voltage, V.sub.ccI. When the ring oscillator is running, the
 frequency is continually measured, for example, by a frequency measurement
 system or other test structure 612 coupled to an output of the final
 output stage 320-3. Over time, the frequency will slow down due to hot
 carrier effects, and the elapsed time, i.e. the lifetime .tau., when
 frequency degradation reaches 10% is recorded. FIG. 4 depicts a log-log
 graph showing a relationship between the frequency degradation on the
 y-axis and the elapsed time on the x-axis for a plurality of stress
 voltages V1 to V3. For example, a plot of the frequency degradation versus
 elapsed time for stress voltage V1 crosses the 10% degradation line when
 the elapsed time is t1. Accordingly, t1 is recorded as the lifetime
 .tau..sub.1 for the stress voltage V1.
 In step 206, the transistor model is calibrated based on the recorded
 reliability data. Specifically, the measured lifetimes from AC stress
 experiments on ring oscillators employing the same channel length are
 compared against corresponding substrate currents, derived from respective
 stress voltages based on I-V curves measured during the DC stress tests.
 FIG. 5 depicts a log-log graph showing a relationship between measured
 lifetimes .tau..sub.i and substrate currents I.sub.SUB. From this graph,
 the constants H and m of the computer simulation can be fine-tuned. With
 some algebraic manipulation to equation (1), the lifetime .tau. is related
 to the substrate current as follows:
 ##EQU2##
 Taking the logarithm of each side yields:
 ##EQU3##
 Therefore, plotting lifetime versus substrate current (suitably multiplied
 by constant factors such as the drive current at a given stress voltage
 and time and gate width) on a log-log graph yields a line having a slope
 of -m and a y-intercept of log H. Therefore, the values of m and H can be
 calibrated for a computer simulation according the measured reliability
 data from an AC stress test. Suitable values for m and H may be obtained,
 for example, from the experimental data by a calibration system such as a
 computer programmed for curve fitting operations 614 to find a linear fit,
 for example a least-square linear fit in a known manner. The computer
 programmed for curve fitting 614 may be the same computer as the design
 simulating computer 600 or may be a different computer. The reliability
 data from AC stress experiments on ring oscillators employing other
 channel lengths is also used to calibrate the parameters, i.e., channel
 length, of transistors with that geometry.
 After the computer model has been calibrated by the procedure described
 hereinabove, the integrated circuit 604 including stacked NAND gates 606,
 for example a critical path of a microprocessor, is simulated using the
 computer model. During, or after the simulation, an integrated circuit
 designer is able to determine the reliability, i.e. hot carrier lifetime,
 and performance of the integrated circuit. Specifically, the designer is
 able to easily modify design parameters 624, especially the channel
 lengths of the stacked NMOS transistors, to ascertain whether the
 modification improves the reliability, or performance of the integrated
 circuit.
 While this invention has been described in connection with what is
 presently considered to be the most practical and preferred embodiment, it
 is to be understood that the invention is not limited to the disclosed
 embodiment, but on the contrary, is intended to cover various
 modifications and equivalent arrangements included within the spirit and
 scope of the appended claims.