Method and apparatus for using a previous column pointer to read entries in an array of a processor

A method and apparatus are described for using a previous column pointer to read a subset of entries of an array in a processor. The array may have a plurality of rows and columns of entries, and each entry in the subset may reside on a different row of the array. A previous column pointer may be generated for each of the rows of the array based on a plurality of bits indicating the number of valid entries in the subset to be read, the previous column pointer indicating whether each entry is in a current column or a previous column. The entries in the subset may be read and re-ordered, and invalid entries in the subset may be replaced with nulls. The valid entries and nulls may then be outputted.

FIELD OF INVENTION

This application is related to the design of a processor.

BACKGROUND

Dedicated pipeline queues have been used in multi-pipeline execution units of processors in order to achieve faster processing speeds. In particular, dedicated queues have been used for execution (EX) units having multiple EX pipelines that are configured to execute different subsets of a set of supported micro-instructions. Dedicated queuing has generated various bottlenecking problems and problems for the scheduling of microinstructions that required both numeric manipulation and retrieval/storage of data.

Processors are conventionally designed to process operations (Ops) that are typically identified by operation codes (OpCodes), (i.e., instruction codes). In the design of new processors, it is important to be able to process all of a standard set of Ops so that existing computer programs based on the standardized codes will operate without the need for translating Ops into an entirely new code base. Processor designs may further incorporate the ability to process new Ops, but backwards compatibility to older instruction sets is often desirable.

Execution of micro-instructions/Ops is typically performed in an execution unit of a processor. To increase speed, multi-core processors have been developed. Furthermore, to facilitate faster execution throughput, “pipeline” execution of Ops within an execution unit of a processor core is used. Cores having multiple execution units for multi-thread processing are also being developed. However, there is a continuing demand for faster throughput for processors.

One type of standardized set of Ops is the instruction set compatible with “x86” chips, (e.g., 8086, 286, 386, and the like), that have enjoyed widespread use in many personal computers. The micro-instruction sets, such as the “x86” instruction set, include Ops requiring numeric manipulation, Ops requiring retrieval and/or storage of data, and Ops that require both numeric manipulation and retrieval/storage of data. To execute such Ops, execution units within processors have included two types of pipelines: arithmetic logic pipelines (“EX pipelines”) to execute numeric manipulations, and address generation (AG) pipelines (“AG pipelines”) to facilitate load and store Ops.

In order to quickly and efficiently process Ops as required by a particular computer program, the program commands are decoded into Ops within the supported set of microinstructions and dispatched to the execution unit for processing. Conventionally, an OpCode is dispatched that specifies the Op/micro-instruction to be performed along with associated information that may include items such as an address of data to be used for the Op and operand designations.

Dispatched instructions/Ops are conventionally queued for a multi-pipeline scheduler queue of an execution unit. Queuing is conventionally performed with some type of decoding of a micro-instruction's OpCode in order for the scheduler queue to appropriately direct the instructions for execution by the pipelines with which it is associated within the execution unit.

The processing speed of the execution unit may be affected by the operation of any of its components. For example, any delay in scheduling of the instructions may adversely affect the overall speed of the execution unit.

SUMMARY OF EMBODIMENTS

A method and apparatus are described for using a previous column pointer to read a subset of entries of an array in a processor. The array may have a plurality of rows and columns of entries, and each entry in the subset may reside on a different row of the array. A previous column pointer may be generated for each of the rows of the array based on a plurality of bits indicating the number of valid entries in the subset to be read, the previous column pointer indicating whether each entry is in a current column or a previous column.

Each of the entries may include a physical register number (PRN). A row pointer may be used to indicate a first entry of the subset on a specific row of the array. The bits having a select logic value may be shifted together, and then the shifted bits may be rotated based on the row pointer. A new row pointer may be generated based on the rotated bits. The entries in the subset may be read and re-ordered, and invalid entries in the subset may be replaced with nulls. The valid entries and nulls may then be outputted.

A processor may include a decode unit configured to generate a plurality of bits, and an array having a plurality of rows and columns of entries, each entry in the subset residing on a different row of the array. A previous column pointer may be generated for each of the rows of the array based on the bits to indicate whether each entry is in a current column or a previous column.

A computer-readable storage medium may be configured to store a set of instructions used for manufacturing a semiconductor device. The semiconductor device may comprise the decode unit and the array described above. The instructions may be Verilog data instructions or hardware description language (HDL) instructions.

A computer-readable storage medium may be configured to store data for using a previous column pointer to read a subset of entries of an array having a plurality of rows and columns of entries where each entry in the subset resides on a different row of the array, by generating a previous column pointer for each of the rows of the array based on a plurality of bits indicating the number of valid entries in the subset to be read, and the previous column pointer indicating whether each entry is in a current column or a previous column.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1shows an example block diagram of a processor100, (e.g., a central processing unit (CPU)), including an execution (EX) unit105and a decode unit110. The EX unit105may include an arithmetic logic unit (ALU)115and a scheduler120. The ALU115may include a physical register file (PRF)125. The scheduler120may include a mapper130having a physical register number (PRN) array135, (otherwise known as a freelist macro).

The EX unit105is responsible for all integer execution, (including AG), as well as coordination of all instruction retirement and exception handling. The EX unit105may be configured to translate all architectural source registers to their current physical registers, and to assign new physical registers to architectural destination registers through a rename and mapping process, using the mapper130and the PRN array135. Physical tags, (i.e., indexes into the PRF125), may be produced that are used for all subsequent dependency tracking. The PRF entries may be allocated and deallocated out-of-order. Therefore, the free entries need to be tracked in the PRN array135(i.e., a freelist structure). The PRN array135may store free PRF entries and provide free PRNs to rename destination registers. The PRN array135may be a first-in first-out (FIFO) queue that is read in-order with a read pointer. Up to eight (8) PRNs may be read out each cycle of the processor100. There is a write pointer at the other end of the queue where newly freed PRNs are written. Up to eight (8) newly freed PRNs may be written each cycle.

Eight (8) PRNs may be read every cycle of the processor100, but they all may not come from the same column. The PRN array135, (i.e., a freelist macro), may be an array which stores 8 (rows)×10 (columns)=80 free PRNs. Each PRN may include 8 bits.

The EX unit105may receive a destination valid signal140(8 bits) from the decode unit110, in a pipe stage, which indicates the number of destinations that were valid in four (4) dispatch packets (2 bits each). A dispatch valid signal (not shown) may be received one cycle later in a mapping pipe stage which indicates whether 1, 2, 3 or 4 dispatch packets were valid. Both these valid signals may be used to determine where (which row) to start reading the PRNs in the cycle. Thus, instead of just using row and column pointers, an additional pointer is needed, (i.e., a previous column pointer), which determines whether it is necessary to read from a current column or a previous column for a particular row.

The scheduler queue120determines the order that operations (Ops)/instructions are executed by the EX unit105. The mapper130maps architectural registers, (designated by architectural register numbers (ARNs), to physical registers, (designated by PRNs). The PRN array135is used to determine which of the PRNs in the PRF125are “free”, (i.e., valid and available for use). At the beginning of each cycle of the processor100, the decode unit115sends a destination valid signal140to the ALU115and the scheduler120that indicates which of a subset of the PRNs stored in entries of the PRF125are valid and invalid. As an example, the destination valid signal140may have 8 bits, whereby each bit having a logic 1 value indicates a valid PRN, and each bit having a logic 0 value indicates an invalid PRN. The number of valid PRNs indicated by each destination valid signal140is provided to the PRN array135in the mapper130to determine the number of entries in the subset that are valid to be used.

As an example shown inFIG. 2, the PRN array135may include 80 entries2050,2051,2052,2053, . . . ,20577,20578and20579, each including a respective eight (8)-bit PRN P0, P1, P2, P3, . . . , P77, P78and P79, which may be considered for reading at a rate of eight (8) entries per cycle of the processor100.

FIG. 3shows an example of reading the PRN array135in the processor100ofFIG. 1based on the destination valid signal140received for each cycle of the processor100. As shown inFIG. 3, in cycle N of the processor100, the PRNs P0-P7in the PRN135are considered for reading. However, in this example, the destination valid signal140having a value “10001011” indicates that only four (4) PRNs are valid to be used, and thus only PRNs P0-P3are used in cycle N, and PRNs P4-P7were not used because they were considered to be invalid. In cycle N+1 of the processor100, the PRNs P4-P11in the PRN array135are considered for reading. However, in this example, the destination valid signal140having a value “10111011” indicates that six (6) PRNs are valid to be used, and thus PRNs P4-P9are used in cycle N+1, and PRNs P10and P11were not used because they were considered to be invalid. In cycle N+2 of the processor100, the PRNs P11-P17in the PRN array135are considered for reading. However, in this example, the destination valid signal140having a value “10000000” indicates that only one (1) PRN is valid to be used, and thus PRN P10is used in cycle N+2, and PRNs P11-P17were not used because they were considered to be invalid. This process of reading PRNs may continue until all of the PRNs have been read.

One relatively simple way to implement this process would be to use a PRN array with eight (8) read ports and 80 entries. However, this may require a relatively large silicon area on the chip of the processor100. Furthermore, undesired timing issues and a reduction in the speed of the processor100may result.

FIG. 4shows an example of the configuration of a PRN array135having 80 entries, with 8 rows and 10 columns. Each entry stores a PRN (P0-P7).

FIG. 5shows an example of reading eight (8) PRNs at a time. Assuming that, previously, an attempt was made to read PRNs P10-P17, but only two PRNs were determined to be valid (e.g., the destination valid signal was “10010000”), only P10and P11would be read in the current cycle. Since P10is the first PRN to be read and it resides on the third row of the PRN array135, a row pointer is set to row3using a one-hot 8-bit indicator “00100000”. In the next cycle, an attempt to read PRNs P12-P19is made, whereby four (4) of the PRNs are in a previous column505of the PRN135and the other four (4) PRNs are in a current column510of the PRN array135. A current column pointer (CCP) is set to column3, (e.g., using a one-hot 10-bit indicator “0010000000”), a previous column pointer (PCP) is set to 0 for rows1-4because the PRNs P16-P19are in the current column510, the PCP is set to a logic 1 for rows5-8because the PRNs P12-P15are in the previous column505, and the row pointer is set to row5, (e.g., using a one-hot 8-bit indicator “00001000”).

FIG. 6shows an example circuit600for reading a first PRN (P16) from a first row of the PRN array135ofFIG. 5in the current (third) column510. The circuit600may include a plurality of multiplexers (MUXes)60511-60510, each being controlled by the PCP. Since the first PRN (P16) is in the current column510, the PCP is set to a logic 0 and the CCP is set to column3, the first PRN (P16) is read via the logic 0 input of MUX6053and a wordline (WL)610.

FIG. 7shows an example circuit700for reading a second PRN (P17) from a second row of the PRN array135ofFIG. 5in the current (third) column510. The circuit700may include a plurality of MUXes7051-70510, each being controlled by the PCP. Since the second PRN (P17) is in the current column510, the PCP is set to a logic 0 and the CCP is set to column3, the second PRN (P17) is read via the logic 0 input of MUX7053and a WL710.

FIG. 8shows an example circuit800for reading a third PRN (P18) from a third row of the PRN array135ofFIG. 5in the current (third) column510. The circuit800may include a plurality of MUXes8051-80510, each being controlled by the PCP. Since the second PRN (P18) is in the current column510, the PCP is set to a logic 0 and the CCP is set to column3, the third PRN (P18) is read via the logic 0 input of MUX8053and a WL810.

FIG. 9shows an example circuit900for reading a fourth PRN (P19) from a fourth row of the PRN array135ofFIG. 5in the current (third) column510. The circuit900may include a plurality of MUXes9051-90510, each being controlled by the PCP. Since the fourth PRN (P19) is in the current column510, the PCP is set to a logic 0 and the CCP is set to column3, the fourth PRN (P19) is read via the logic 0 input of MUX9053and a WL910.

FIG. 10shows an example circuit1000for reading a fifth PRN (P12) from a fifth row of the PRN array135ofFIG. 5in the previous (second) column505. The circuit1000may include a plurality of MUXes10051-100510, each being controlled by the PCP. Since the fifth PRN (P12) is in the previous column505, the PCP is set to a logic 1 and the CCP remains set to column3, the fifth PRN (P12) is read via the logic 1 input of MUX10052and a WL1010.

FIG. 11shows an example circuit1100for reading a sixth PRN (P13) from a sixth row of the PRN array135ofFIG. 5in the previous (second) column505. The circuit1100may include a plurality of MUXes11051-110510, each being controlled by the PCP. Since the sixth PRN (P13) is in the previous column505, the PCP is set to a logic 1 and the CCP remains set to column3, the sixth PRN (P13) is read via the logic 1 input of MUX11052and a WL1110.

FIG. 12shows an example circuit1200for reading a seventh PRN (P14) from a seventh row of the PRN array135ofFIG. 5in the previous (second) column505. The circuit1200may include a plurality of MUXes12051-120510, each being controlled by the PCP. Since the seventh PRN (P14) is in the previous column505, the PCP is set to a logic 1 and the CCP remains set to column3, the seventh PRN (P14) is read via the logic 1 input of MUX12052and a WL1210.

FIG. 13shows an example circuit1300for reading an eighth PRN (P15) from an eighth row of the PRN array135ofFIG. 5in the previous (second) column505. The circuit1300may include a plurality of MUXes13051-130510, each being controlled by the PCP. Since the eighth PRN (P15) is in the previous column505, the PCP is set to a logic 1 and the CCP remains set to column3, the eight PRN (P15) is read via the logic 1 input of MUX13052and a WL1210.

FIG. 14is a block diagram of an optional PRN array processing circuit1400for generating an output of the PRN array135. The PRN array processing circuit1400may include a sorting logic unit1405and a validation logic unit1410used to generate a PRN array output1415. The sorting logic unit1405receives the PRNs as they are read by the circuits600-1300ofFIGS. 6-13and re-orders the entries in the subset of PRNs such that they are in sequential order. The validation logic unit receives a destination valid signal and generates a PRN array output1415including valid PRNs and nulls.

FIG. 15is a flow diagram of a procedure1500for using a previous column pointer to read a subset of PRNs from an array. A plurality of bits are received indicating how many entries in a subset of entries to be read from a PRN array are valid, starting with a first entry on a specific row of the PRN array indicated by a row pointer, the PRN array having a plurality of rows and columns, each entry in the subset residing on a different row of the PRN array (1505). The bits having a logic 1 value are shifted together (1510), and then the bits are rotated based on the row pointer (1515). A previous column pointer is generated for each of the rows of the PRN array based on the rotated bits to indicate whether each entry is in a current column or a previous column (1520). A determination is made, based on the rotated bits, whether a current column pointer needs to be moved such that it points to the current column (1525). A new row pointer is generated based on the rotated bits (1530). The steps1520,1525and1530may be performed concurrently. The entries in the subset are then read (1535). Optionally, the entries in the subset may be re-ordered, and the invalid entries in the subset may be replaced with nulls (1540). The valid entries (and nulls) are then output from the PRN array (1545). The procedure1500may be continuously repeated starting with step1505.

FIG. 16is a block diagram of an example device1600in which one or more disclosed embodiments may be implemented. The device1600may include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. The device1600includes a processor1602, a memory1604, a storage1606, one or more input devices1608, and one or more output devices1610. The device1600may also optionally include an input driver1612and an output driver1614. It is understood that the device1600may include additional components not shown inFIG. 16. The processor1602may be configured in a similar fashion to the processor100shown inFIG. 1.

The processor1602may include a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, wherein each processor core may be a CPU or a GPU. The memory1604may be located on the same die as the processor1602, or may be located separately from the processor1602. The memory1604may include a volatile or non-volatile memory, for example, random access memory (RAM), dynamic RAM, or a cache.

The input driver1612communicates with the processor1602and the input devices1608, and permits the processor1602to receive input from the input devices1608. The output driver1614communicates with the processor1602and the output devices1610, and permits the processor1602to send output to the output devices1610. It is noted that the input driver1612and the output driver1614are optional components, and that the device1600will operate in the same manner is the input driver1612and the output driver1614are not present.

Embodiments of the present invention may be represented as instructions and data stored in a computer-readable storage medium. For example, aspects of the present invention may be implemented using Verilog, which is a hardware description language (HDL). When processed, Verilog data instructions may generate other intermediary data, (e.g., netlists, GDS data, or the like), that may be used to perform a manufacturing process implemented in a semiconductor fabrication facility. The manufacturing process may be adapted to manufacture semiconductor devices (e.g., processors) that embody various aspects of the present invention.

Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, a graphics processing unit (GPU), an accelerated processing unit (APU), a DSP core, a controller, a microcontroller, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), any other type of integrated circuit (IC), and/or a state machine, or combinations thereof.