Approaches for folding multiply-and-accumulate (MAC) logic in a circuit design involve a design tool recognizing a first instance of the MAC logic and a second instance of the MAC logic. The design tool replaces the first instance of the MAC logic and the second instance of the MAC logic with one instance of pipelined MAC logic. The design tool configures the pipelined MAC logic to input data signals of the first instance of the MAC logic and the second instance of the MAC logic to the pipelined MAC logic at a first clock rate, and switch between selection of the data signals of the first instance of the MAC logic and the second instance of the MAC logic at a second clock rate that is double the first clock rate. The design tool further configures the pipelined MAC logic to pipeline input data signals at the second clock rate, and to capture intermediate results at the second clock rate. The design tool further configures a register to capture output of the pipelined MAC logic at the first clock rate.

TECHNICAL FIELD

The disclosure generally relates to folding multiply-and-accumulate logic of a circuit design.

BACKGROUND

Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.

Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.

Recognizing that there is a finite number of DSPs available on an FPGA, experienced designers may choose to fold logic implemented on two DSPs into one time-multiplexed DSP. A circuit designer can specify the controls and circuit structures for time-multiplexing a DSP in a circuit design. However, specifying register transfer language (RTL) for time-multiplexing a DSP requires considerable effort of the designer and can be prone to error.

SUMMARY

A disclosed method includes recognizing by a design tool executing on a computer processor, a first instance and a second instance of multiply-and-accumulate (MAC) logic in a circuit design, the first instance inputting first data signals and the second instance inputting second data signals. The method has the design tool replacing the first instance and the second instance of the MAC logic in the circuit design with one instance of pipelined MAC logic. In performing the method, the design tool configures the one instance of pipelined MAC logic by the design tool to input the first data signals and the second data signals to the one instance of pipelined MAC logic at a first clock rate, and switch between selection of the first data signals and the second data signals at a second clock rate that is double the first clock rate. The design tool further configures the one instance of pipelined MAC logic to pipeline at the second clock rate, select data signals of the first data signals and the second data signals, and capture intermediate results generated by the one instance of pipelined MAC logic at the second clock rate. The design tool further configures a register to capture output of the pipelined MAC logic at the first clock rate.

A disclosed system includes a processor and a memory arrangement coupled to the processor. The memory arrangement is configured with instructions and in response to execution of the instructions, the processor performs operations of recognizing a first instance and a second instance of multiply-and-accumulate (MAC) logic in a circuit design. The first instance inputs first data signals and the second instance inputs second data signals. Execution of the instructions further cause the processor to replace the first instance and the second instance of the MAC logic in the circuit design with one instance of pipelined MAC logic. The processor in response to executing the instructions further configures features of the one instance of pipelined MAC logic. The features include input of the first data signals and the second data signals to the one instance of pipelined MAC logic at a first clock rate, switching between selection of the first data signals and the second data signals at a second clock rate that is double the first clock rate, pipelining at the second clock rate, selected data signals of the first data signals and the second data signals, and capturing intermediate results generated by the one instance of pipelined MAC logic at the second clock rate. The processor further configures, in executing the instructions, a register to capture output of the pipelined MAC logic at the first clock rate.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to describe specific examples presented herein. It should be apparent, however, to one skilled in the art, that one or more other examples and/or variations of these examples may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same reference numerals may be used in different diagrams to refer to the same elements or additional instances of the same element.

The disclosed approaches relate to a design tool recognizing opportunities to time-multiplex DSPs and automatically folding multiply-and-accumulate logic specified on a pair of DSP circuits into a single time-multiplexed DSP circuit. The design tool automatically generates a faster clock signal for the time-multiplexed DSP circuit and schedules input of the control and data signals.

DSP circuits are configurable to implement multiply-and-accumulate functions, and the disclosed approaches improve circuit designs by reducing the number of DSP circuits required and reducing the time required to design a circuit through the automated identification of multiply-and-accumulate logic that can be folded into time-multiplexed DSP logic. The circuit design tool recognizes first and second instances of multiply-and-accumulate (MAC) logic that are eligible for folding in a circuit design. The design tool replaces the first and second instances of the MAC logic in the circuit design with one instance of pipelined MAC logic. The pipelined MAC logic is configured to operate in a time-multiplexed manner and replace the computations of the first and second instances of the MAC logic. The design tool configures the pipelined MAC logic to input data signals of the first instance of MAC logic and input data signals of the second instance of MAC logic at a first clock rate. The design tool further configures the pipelined MAC logic to switch between selection of the first data signals and the second data signals at a second clock rate that is double the rate of the first clock rate. The selected data signals are pipelined at the second clock rate, and the pipelined MAC logic captures intermediate results at the second clock rate. The design tool configures a capture register to capture the output of the pipelined MAC logic at the first clock rate.

The disclosed processes can improve the way a computer system operates in processing circuit designs. By folding instances of MAC logic into a single time-multiplexed DSP circuit, fewer memory resources are used by the design tool in representing the circuit design for synthesis, mapping, place-and-route, optimization, and simulation processes. In addition, processing cycles of the computer system hosting design tools are reduced as a result of having to process fewer DSP circuits in the design flow. Performing two MACs in one DSP instance allows twice the number of MAC operations to be performed on the same programmable IC, which can improve the throughput of applications previously limited by MAC resources.

FIG. 1shows an exemplary digital signal processing (DSP) circuit100that is configurable to time-multiplex DSP functions. The exemplary DSP is configurable to perform multiply-and-accumulate, multiply-and-subtract, and multiply-and-AND functions. Input data values A, B, C, and D are stored in registers102,104,106, and108. The value of B stored in register102and the value of A stored in register104are input to multiplexer110. The control signal to the multiplexer can be provided by the signal from a configuration memory cell (not shown).

Circuit112is configurable to add or subtract the value output by multiplexer110and the input value D from register106. The output of circuit112is stored in register114. Multiplexer116selects one of the values from registers102and114, and the selection can be controlled by the state of a configuration memory cell (not shown). Multiplier circuit118multiplies the output signal of multiplexer116with the value output by register114, the result of which is stored in register120.

Also shown inFIG. 1is multiplexer124, having as inputs the value of C stored in register108and a value fed back from output signal P. To generate output signal P, accumulator122receives as inputs the value stored in register120and the value output by multiplexer124. The accumulator circuit122is configurable to perform one of an addition function, a subtraction function, or an AND function. The accumulator circuit122can be configured by way of one or more configuration memory cells associated with the DSP circuit100. Register132stores the value output by accumulator122and generates output signal P, which in turn is fed back to multiplexer124.

Also in accordance withFIG. 1, the value output by accumulator122may undergo an XOR126operation before being stored in register130and used to generate output signal XOR. Multiplexer128can operate as a pattern detector, selecting either the value output by accumulator122or the input data value of C from register108. The output of multiplexer128is stored in register134, which provides the output signal “pattern detect.”

FIG. 2shows the DSP circuit100ofFIG. 1configured to operate as a multiply-and-accumulate circuit in which the accumulate function is addition. Registers102and104store input values B and A respectively. The value of B stored in register102is input to multiplexer116, and the value of A stored in register104is input to multiplexer110. Multiplier circuit118multiplies the values output by multiplexers110and116, and the result is stored in register120. Multiplexer124is configured to select the value fed back from output signal P; the selection can be controlled by the state of a configuration memory cell (not shown). Accumulator122is configured to perform an addition function and adds the value stored in register120to the feedback value selected by multiplexer124. The value resulting from the addition is stored in register132, and the value from register132is used to generate output signal P.

FIG. 3shows exemplary multiply-and-accumulate logic that qualifies to be folded into a single DSP circuit. DSP circuit301receives as inputs data values A and B from registers303and305. The values of A and B as stored in registers303and305are input to multiplier307, and the product is stored in register309. Accumulator313performs an accumulation function on the value stored in register309and the value selected by multiplexer311. The result of the accumulation function is stored in register315. The accumulation function can be one of addition or a logic AND of the two inputs. In general, in order to qualify for folding the accumulation function can be any function that is commutative and associative. The value output by register315is accumulated with the output of DSP circuit302by configurable accumulator318and the result is stored in register320.

DSP circuit302receives as inputs data values C and D from registers304and306. The values of C and D are input to multiplier308, and the product is stored in register310. Accumulator314performs an accumulation function on the value stored in register310and the value selected my multiplexer312. The result of the accumulation function is stored in register316. The accumulation function of accumulator314is the same as the accumulation function of accumulator313. The value output by register316from DSP circuit302is accumulated with the output of DSP circuit301by configurable accumulator318, and the accumulation function of accumulator318is the same as the accumulation functions of accumulators313and314.

In order to qualify for logic folding, DSP circuits301and302are configured as identical DSP circuits operating on different input data values. Data values A and B are the inputs of DSP circuit301, and data values C and D are input into DSP circuit302. To qualify for logic folding, the accumulation function of accumulators313and314are the same. The outputs of DSPs301and302are combined by accumulator318, which is configured to perform the same accumulation function as accumulators313and314of in the DSP circuits. For example, if accumulators313and314are configured to perform addition, the resulting values are summed by accumulator318.

The values of an enable signal and reset signals are stored in registers322,324A, and324B, respectively. The reset and enable signals together implement a control path and are shared between DSPs301and302at intermediate registers309,310,315, and316. The shared control path is one of the features required for DSP logic to qualify for logic folding. That is, the enable signal from register322is provided to both registers309and310, as well as to registers315and316; resetM signal from register324A is provided to both registers309and310; and resetP signal from register324B is provided to both register315and register316.

Also depicted inFIG. 3is a clear signal, the value of which is stored in register326. The clear signal is routed to multiplexers311and312. In response to deassertion of the clear signal, the multiplexers select a fixed 0 value instead of the feedback values from registers315and316.

FIG. 4shows a DSP circuit401configured to time-multiplex two multiply-and-accumulate (MAC) functions. The DSP circuit401operates at twice the clock rate (a frequency of 2×) of the DSP circuits301and302inFIG. 3and alternates between performing a MAC function on the input data values A and B and a MAC function on the input data values C and D. Input data values A, B, C, and D are stored in registers402,403,404, and405, respectively. The value of A stored in register402along with the value of C stored in register404provide the inputs to multiplexer406, and the value of B stored in register403and the value of D stored in register405provide the inputs to multiplexer407. The control signal to multiplexers406and407is provided by register424, which is clocked at twice the clock speed at which the registers402,403,404, and405are clocked. On one cycle of the 2× clock signal, multiplexers406and407select the input value A from register402along with input value B stored in register403. In the next successive cycle of the 2× clock signal, multiplexers406and407select input value C from register404and input value D from register405.

DSP circuit401has registers408,409,410, and411that are configured to pipeline input data values. The registers408,409,410, and411are clocked at twice the rate at which the registers402,403,404, and405are clocked. In one cycle of the 2× clock signal, the input data values selected by the multiplexers406and407are stored in registers408and409. In the next cycle of the 2× clock signal, the data values in registers408to409are shifted into registers410and411so that the other pair of input data values selected by the multiplexers406and407can be stored in the registers408and409.

The data values from registers410and411are input to multiplier circuit412, and the output of the multiplier circuit is stored in register414, which is clocked at twice the rate of the registers402,403,404, and405. The value output by register414is input to the accumulator418. The accumulator418performs an accumulation function on the value from the register414and the value selected by multiplexer416, which is one of a feedback value from register420or a constant value 0. The accumulation function may be one of addition or a logic AND. The result of the accumulation function is stored in register420, which is clocked at twice the rate at which registers402,403,404, and405are clocked. The output of register420is captured in register422, which is operated at a clock signal frequency of 1×.

The value of the enable signal is stored in register426, which is clocked at the 1× clock speed, and the output of register426is provided as the enable input to flip-flops408,409,410, and411. The value of the enable signal output by register426is also stored in register432, which is clocked by the clock signal having the frequency of 2×, and the output of register432is provided as the enable signal for controlling register420.

The value of the signal resetM is stored in register428-A, which is clocked at the frequency of 1×. The output of register428-A is buffered in register430, which is clocked at the frequency of 1×. The buffered resetM signal from register430is provided as the reset signal to register414. The value of the signal resetP is stored in register428-B, which is clocked at the frequency of 1×. The output of register428-B is buffered in register434, which is clocked at the frequency of 2×. The buffered resetP signal from register434is provided as the reset signal to register420. Resets of registers408,409,410, and411are unused after folding.

The value of the clear signal is stored in register436, which is operated at the clock frequency of 1×. The output of register436is input as the set signal to register438, which is operated at the clock frequency of 2× and whose value toggles at the clock frequency of 2× in response to deassertion of the set signal. When the set signal is asserted the value will remain static to 1. The output signal from register438is provided as the control signal to multiplexer416, which selects the constant value 0 or the feedback signal from register420in response to the state of the control signal.

FIG. 5shows logic that provides clock signals having frequencies of 1× and 2× to a time-multiplexed DSP circuit401. In an exemplary application, a multi-mode clock manager (MMCM)502can be used to generate the clock signals for time-multiplexing a DSP circuit. For example, in FPGAs from XILINX, Inc., the MMCM is a primitive design object that is configurable to generate multiple clock signals having defined phase and frequency relationships to a given input clock signal.

The circuit design tool can determine whether or not an MMCM is present in the circuit design. If an MMCM is present in the circuit design, the design tool can specify configuration of the MMCM502to generate and output a dock signal having a frequency of 2×. The design tool configures the MMCM to drive one clock buffer with clock dividing factor set to 2(BUFCGE_DIV:2)504to output a clock signal having the frequency of 1× and another dock buffer with clock dividing factor set to 1 (BUFGE_DIV:1)506to output a clock signal having a frequency of 2×. If no MMCM is present in the circuit design, the circuit design tool instantiates and configures an MMCM to take 1× frequency clock as input and generate2xfrequency clock as described above.

FIG. 6is a flowchart of an exemplary process for automatically folding multiply-and-accumulate logic specified in a circuit design600into a single time-multiplexed DSP circuit. A design tool inputs the circuit design600at block602. According to one feature, an attribute can be associated with the circuit design to turn on and turn off automatic folding. The attribute can be embedded in the circuit design600or specified as a command parameter, for example.

If the folding attribute is set, decision block604directs the design tool to block606, at which the design tool searches for multiply-and-accumulate logic that can be folded into a single DSP circuit. For two instances of multiply-and-accumulate logic to quality for folding, the instances must share enable, reset, and clear signals as described above. In addition, the output values of the instances must be combined with an accumulate function that matches the accumulate functions of the two instances.

In response to finding two instances of multiply-and-accumulate logic that qualify for folding, at block608the design tool folds the instances into a single instance of time-multiplexed multiply-and-accumulate logic. The one instance of time-multiplexed multiply-and-accumulate logic can be as shown by the circuitry ofFIG. 4.

At block610, the design tool specifies logic that generates one clock signal having a frequency of 1×, and another clock signal having a frequency of 2×. The design tool connects the 1× and2xclock signals to the registers of the DSP circuitry as shown inFIG. 4.

The design tool at block612generates circuit implementation data. The tool can perform synthesis of a hardware description language (HDL) specification of the circuit design, technology mapping, place-and-route, optimization processes, and simulations. The circuit implementation data can be a configuration bitstream for programmable logic or data that specifies fabrication details for an ASIC, for example. At block614, a circuit can be implemented and made by way of configuring a programmable IC with a configuration bitstream, or fabricating, making, or producing an ASIC from the implementation data, thereby creating a circuit that operates according to the resulting circuit design.

FIG. 7is a block diagram illustrating an exemplary data processing system (system)700. System700is an example of an EDA system. As pictured, system700includes at least one processor circuit (or “processor”), e.g., a central processing unit (CPU)705coupled to memory and storage arrangement720through a system bus715or other suitable circuitry. System700stores program code and circuit design600within memory and storage arrangement720. Processor705executes the program code accessed from the memory and storage arrangement720via system bus715. In one aspect, system700is implemented as a computer or other data processing system that is suitable for storing and/or executing program code. It should be appreciated, however, that system700can be implemented in the form of any system including a processor and memory that is capable of performing the functions described within this disclosure.

Memory and storage arrangement720includes one or more physical memory devices such as, for example, a local memory (not shown) and a persistent storage device (not shown). Local memory refers to random access memory or other non-persistent memory device(s) generally used during actual execution of the program code. Persistent storage can be implemented as a hard disk drive (HDD), a solid state drive (SSD), or other persistent data storage device. System700may also include one or more cache memories (not shown) that provide temporary storage of at least some program code and data in order to reduce the number of times program code and data must be retrieved from local memory and persistent storage during execution.

Input/output (I/O) devices such as user input device(s)730and a display device735may be optionally coupled to system700. The I/O devices may be coupled to system700either directly or through intervening I/O controllers. A network adapter745also can be coupled to system700in order to couple system700to other systems, computer systems, remote printers, and/or remote storage devices through intervening private or public networks. Modems, cable modems, Ethernet cards, and wireless transceivers are examples of different types of network adapter745that can be used with system700.

Memory and storage arrangement720can store an EDA application750. EDA application750, being implemented in the form of executable program code, includes one or more design tools that are is executed by processor(s)705. As such, EDA application750is considered part of system700. System700, while executing EDA application750, receives and operates on circuit design600. In one aspect, system700performs a design flow on circuit design600, and the design flow can include the automated folding of multiply-and-accumulation logic, synthesis, mapping, placement, routing, optimization, simulation, and generation of implementation data. System700generates a modified version of circuit design600and generates implementation data, which are shown as circuit design and implementation data760.

EDA application750, circuit design600, circuit design760, and any data items used, generated, and/or operated upon by EDA application750are functional data structures that impart functionality when employed as part of system700or when such elements, including derivations and/or modifications thereof, are loaded into an IC such as a programmable IC causing implementation and/or configuration of a circuit design within the programmable IC.

Though aspects and features may in some cases be described in individual figures, it will be appreciated that features from one figure can be combined with features of another figure even though the combination is not explicitly shown or explicitly described as a combination.

The methods and system are thought to be applicable to a variety of systems for folding multiply-and-accumulate logic. Other aspects and features will be apparent to those skilled in the art from consideration of the specification. It is intended that the specification and drawings be considered as examples only, with a true scope of the invention being indicated by the following claims.