Duty cycle measurement circuit for measuring and maintaining balanced clock duty cycle

A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to integrated circuit (IC) clock systems and more particularly to maintaining duty cycle timing balance in ICs.

2. Background Description

Large high performance very large scale integration (VLSI) chips like microprocessors are synchronized to an internal clock. A typical internal clock is distributed throughout the chip, triggering chip registers to synchronously capture incoming data at the register latches and launch data from register latches. Ideally, each clock edge arrives simultaneously at each register every cycle and data arrives at the register latches sufficiently in advance of the respective clock edge, that all registers latch the correct data and simultaneously. Unfortunately, various chip differences can cause timing uncertainty, i.e., a variation in edge arrival to different registers.

Such timing uncertainties can arise from data propagation variations and/or from clock arrival variations. Data propagation variations, for example, may result in a capturing latch that randomly enters metastability or latches invalid data because the data may or may not arrive at its input with sufficient set up time. Clock edge arrival variations include, for example, clock frequency fluctuations (jitter) and/or register to register clock edge arrival variations (skew). Both data path and clock edge arrival variations can arise from a number of sources including, for example, ambient chip conditions (e.g., local temperature induced circuit variations or circuit heat sensitivities), power supply noise and chip process variations. In particular, power supply noise can cause clock propagation delay variations through clock distribution buffers. Such clock propagation delay variations can cause skew variations from clock edge arrival time uncertainty at the registers. Typically, chip process variations include device length variations with different device lengths at different points on the same chip. So, a buffer at one end of a chip may be faster than another identical (by design) buffer at the opposite end of the same chip. Especially for clock distribution buffers, these process variations are another source of timing uncertainty.

Furthermore, as technology features continue to shrink, power bus or Vddnoise is becoming the dominant contributor to total timing uncertainty. High speed circuit switching may cause large, narrow current spikes with very rapid rise and fall times, i.e., large dI/dt. In particular, each of those current spikes cause substantial voltage spikes in the on-chip supply voltage, even with supply line inductance (L) minimum. Because V=LdI/dt, these supply line spikes also are referred to as L di/dt noise. Since current switching can vary from cycle to cycle, the resulting noise varies from cycle to cycle. When the Vddnoise drops the on-chip supply voltage in response to a large switching event, can slow the entire chip including both the clock path (clock buffers, local clock blocks, clock gating logic and etc.) as well as the data path logic (combinational logic gates, inverters and etc.). Vddnoise can also be very localized in its impact, depending on many factors such as the robustness of the power distribution grid. When the noise dissipates and the on-chip supply later recovers, or even overshoots as the supply current falls; then, the circuits (buffers, gates and etc.) in these same paths speed up, returning to their nominal performance (with the normal stage delay) or even faster. The number of stages that can complete changes as the data path slows down or speeds up relative to the clock path. Currently, in particular, such switching noise is the dominant component of total timing uncertainty, more even than skew or jitter (which are themselves affected by switching noise) or chip process variations. Thus, it would be useful to be able to determine switching noise and how it affects circuit performance

Clock skew and jitter, power supply noise and chip ambient and process variations may be considered the primary sources of timing uncertainty. In particular, the overall or total timing uncertainty is a complex combination of both clock and data path uncertainty that reduces the number of combinational logic stages (typically called the fan out of 4 (FO4) number) that can be certifiably completed in any clock cycle and so, reduces chip performance. The FO4 number is the number of fan-out of four inverter delays that can fit in one cycle. This design parameter serves to determine chip pipeline depth, e.g., in a microprocessor. By design, register latch boundaries are determined by the maximum number of logic stages (FO4) that may be guaranteed to be completed in every clock cycle. Typically, designers apply some guard band number to the FO4 number (i.e., reduce the FO4 number by some delta) to account for timing uncertainties. Previously, this delta was a guess of how the number of combinational logic stages that can be completed had changed from cycle to cycle. If the guess was too high, chip problems would result. If not, there was no way to determine if that guess was too low and by how much.

Furthermore, state of the art microprocessors, for example, use what is known as clock doubling for additional performance improvement. Typical clock doubling triggers circuits off each clock transition with the on-chip clock period being the time between such transitions. Clock duty cycle is the percentage of the clock cycle that the clock signal is high. A duty cycle that is 50% is balanced with the time between transitions being equal. Consequently, these state of the art microprocessors, especially, require a well-controlled, balanced duty cycle. Unfortunately, while typical state of the art phase locked loop (PLL) circuits rely on analog duty cycle monitoring/correction of the clock signal output, these typical PLLs do not correct duty cycle distortion that the clock distribution tree/buffers introduce, which requires designers to account for expected duty cycle imbalance, e.g., by “guardbanding” or foreshortening the logic paths to accommodate for expected half cycle foreshortening. So, while the clock frequency may have doubled, performance is lost frequently by guardbanding for an unbalanced duty cycle.

Thus, there is a need for a way to measure clock duty cycle and adjust on-chip clocks to maintain a balanced duty cycle.

SUMMARY OF THE INVENTION

It is a purpose of the invention to improve integrated circuit (IC) chip design;

It is another purpose of the invention to facilitate determination of timing path variations;

It is yet another purpose of the invention to reliably measure on chip duty cycle uncertainty;

It is yet another purpose of the invention to accurately determine the number of completed logic stages on a half cycle-by-half cycle basis, monitor and compensate duty cycle timing variations.

It is yet another purpose of this invention to accurately identify duty cycle imbalances and recover duty cycle timing variations for maintaining a balanced duty cycle.

The present invention relates to a circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.

DESCRIPTION OF PREFERRED EMBODIMENTS

Turning now to the drawings and, more particularly,FIG. 1shows a block diagram of an example of a logic stage counter100according to a preferred embodiment of the present invention. A local clock block (LCB) or clock buffer102receives and re-drives a global chip clock104into 2 complementary local clocks106,108. One clock, a launch clock106, is provided to a delay line110and launches the timing edge in the delay. The LCB102and delay line110mimic data propagation delay through an actual data path, e.g., in a microprocessor. Both clocks106,108clock an N bit register112. Delay line taps114are stage inputs to N bit register112. For example, N=129 may be a convenient length for holding 3 cycles worth of edges. The second clock, a capture clock108, captures the forward position of the timing edges in the N bit register112. Although in this example, the launch clock106drives the delay line110, either clock, the launch or the capture clock can drive the delay line110. In this example, the rising edge of launch clock106and the falling edge of the capture clock108(which latches the data) are coincident and are derived from the same global clock104edge. This rising edge is the principal edge of interest and marks the end/start of the cycle boundary. It should be noted that the present invention is described herein with the registers (e.g.,112) being clocked by complementary clocks106,108. This is for example only and not intended as a limitation and the registers/latches may be pulsed latches or any suitable equivalent register/latch such as are well known in the art.

The launch clock106drives the delay line110and, preferably, the delay difference between each pair of taps114is equivalent to one logic block delay. Typically, the total timing uncertainty metric is the number of combinational logic stages that complete in a cycle, sometimes referred to as the fan-out of 4 (FO4) inverter count or FO4 number. Delay line110may include any suitable inverting and/or non-inverting logic gates such as AND/NAND gates, OR/NOR gates, XOR/XNOR gates. However, for the best time resolution the preferred delay between delay line taps114is the minimum delay for the particular technology, e.g., the delay for a single fan-out inverter (FO1 inverter). Preferably, the delay line110is at least three clock periods long, i.e., long enough that the start of one clock cycle, the leading clock edge, has not propagated through the delay line110before the start of second following cycle enters the delay line110. Therefore, preferably, the delay line110normally has 3 edges passing through it. The N bit register112is clocked by both the launch clock106and the capture clock108. Essentially, at the start of a global clock period, the launch clock106passes a previously loaded N bits out of the register112as the leading edge begins traversing the delay line110. At the end of each global clock period, the capture clock108latches the state of the delay line taps114in the capture register112, capturing the progress of the launch clock106edges through the delay line110. In the absence of jitter or other sources of timing uncertainty, the location of the edges (tap number) does not change from cycle to cycle.

So, for example, the delay line110may be a series of suitably loaded inverters with delay line taps114being the inverter outputs. As a result, the taps114alternate ones and zeros and the clock edges are located by a matched pair (either 2 zeros in a row, or 2 ones in a row) of adjacent delay line taps114. The space between matching tap pairs, e.g., 60 inverter stages between leading/rising clock edges, is a measure of logic propagation during a complete clock cycle. Thus, the same local clock block102both launches and captures the timing edges and, because the local clock itself is the launched data, the clock takes a snapshot of itself in the capturing latches. The captured edges are evenly spaced in the absence of timing uncertainty either in the clock path or data path. However, timing uncertainty and in particular, jitter, e.g., from local or chip noise, is exhibited in a variation in the tap number where the edges get captured.

In particular, the present invention may be used to identify a poor clock source, e.g., a phase locked loop (PLL) with significant jitter may be identified as a source of timing uncertainty. It may be useful to understand if the PLL has an occasional short cycle or, worse, 2 or more short cycles in a row, the occurrence of which may be found from 3 cycles worth of edges stored in the capture register. So, for example, the first edge (e.g., a leading or rising edge) is always captured in bit position0(register latch0) and in the absence of jitter, the second (leading) edge is in bit60and the third in bit position120. Without jitter the edges always fall in the same bit positions. However, with an occasional short cycle the second edge (for the shorter cycle) shifts by one to bit59; the third edge is captured in bit119. With 2 consecutive short cycles, however, the second edge still shifts to bit59, but the third edge shifts to bit118. For multi-cycle paths such as in a microprocessor, this underscores the advantage of capturing several cycles in the latched-tapped delay chain—so that relationships between consecutive cycles can be identified and monitored.

Additionally, as can be seen from the supply noise characterization plot ofFIG. 2A, the present invention facilitates determining and relating supply line (Vddswitching current) noise to performance degradation and, in particular, to the FO4 number reduction.FIG. 2Bshows an example of a flow diagram200of steps in determining for a particular technology the relationship between switching current noise and FO4 number according to a preferred embodiment of the present invention, with reference to the circuit example100ofFIG. 1. Alternately, other preferred embodiments such asFIG. 3Acan also be used for Vdd waveform recovery. All of the steps inFIG. 2Bare done under quiet chip conditions, i.e., where chip switching activity is kept to a minimum. First, in step202a run is done at nominal Vdd, and the tap positions are noted. Then, in step204, the supply voltage is lowered by some delta, e.g., 25 millivolts (25 mV). In step206, edge capture tap positions are noted. In step208, a check is made to determine if a lower accepted supply voltage limit, e.g., 250 mV below specified nominal and, if not, returning to step204the supply is dropped and tap positions are noted in step206. Once the lower limit is reached in step208, in step210the supply voltage is raised by some delta, which may be the same as that used in ramping the supply voltage down, i.e., 25 mV. Then, in step212the captured edge tap positions are noted. In step214, the supply voltage is checked to determine if an upper limit (nominal in this example) is reached and, if not, returning to step210, the supply voltage is raised another delta and tap positions are noted in step212. The calibration runs are completed in step214when the upper limit is reached and, the results may be tabulated with the resulting table indicating the on-chip FO4 number relationship to supply switching noise. Thus, for the particular technology of the example ofFIG. 2A, each 25 mV drop in Vdd, whether from switching noise or arising from other sources, reduces the FO4 number by 1.

As is also apparent from the supply noise characterization plot example ofFIG. 2A, typical noise events are relatively long, lasting several cycles and even many cycles. Once the relationship between the FO4 number reduction and supply line drop is determined, e.g., as described for the flow chart ofFIG. 2B, the present invention (e.g.,) can be used to accurately characterize supply noise, generating a plot similar to that ofFIG. 2A, e.g., using the logic stage counter100ofFIG. 1.FIG. 2Cshows an example of a flow chart220for generating a characterization plot by iteratively logging edges during such an event. In step222a logger count is initialized to point to the beginning or just before the beginning of the particular event. Then, in step224both the cycle counter and the chip are initialized to an initial state and started. Essentially, supply noise is characterized by repeatedly scanning through the particular event and logging tap contents at successive cycles during the scan. So in step226in the first pass, the contents of the capture register are collected after N cycles, near in time to the beginning of the particular on-chip switching noise event and, in step226the tap locations are logged. In step228the current logger count is checked to determine if the count is at or after the end of the event. Next, since the count is not at the end of the event, in step130, the logger count is incremented and, returning to step224, the chip is restarted from the same initial state and run for N+1 cycles, and in step226the tap locations of the captured edges are logged. This is repeated for N+2 cycles, N+3 cycles, and etc., until in step228, it is determined that the event has passed. The collected tap locations are converted to mV and the on-chip VDD level may be plotted against time (cycle number) to recover the waveform as in the example ofFIG. 2A. Further, once the relationship between supply noise and FO4 number reduction is ascertained, such noise can be mitigated as described in U.S. application Ser. No. 10/712,926 entitled “Clock Gated Power Supply Noise Compensation” to Phillip J. Restle, assigned to the assignee of the present invention, now issued as U.S. Pat. No. 6,933,754 B2, and incorporated herein by reference.

FIG. 3Ashows a block diagram of another example of a logic timing uncertainty quantifier120with cross coupled clocks to measure clock skew according to a preferred embodiment of the present invention. This example includes 2 paths122,124, similar to the single path100ofFIG. 1and, as in normal logic (e.g., microprocessor) paths, different local clock blocks can drive the launching and receiving registers. In this example, however, both launch clocks106A,106B are passed to select logic, e.g., a mutiplexor (mux)126,128in each path122,124. Each mux126,128selectively passes either its own local launch clock106A,106B, respectively, or the remote launch clock106B,106A to the local delay line110A,110B. For example, each path, e.g.,122, can select providing its own launch clock106A to its delay110A or, select the launch clock106B from remote path124.

In addition to locating jitter as described for the example ofFIG. 1, this cross coupled embodiment better separates and quantizes chip wide timing uncertainty, accounting for global clock skew, as well as path delay variations. With a cross-coupled embodiment, in the absence of skew (or at least less than the granularity of one inverter stage delay) between the two global clock connections, clock edges launched from either clock106A,106B travel the same tap number in each of the two receiving delay lines110B,110A and, the clock edges are captured by the local capture clocks108B,108A at the same point in the registers112B,112A. Propagation is asymmetric when global clock skew exists between the two global clock inputs104A,104B. The asymmetry occurs because one of the global clocks104A,104B arrives at the particular LCB102A,102B before the other and so one of the launch clocks, has a head start over the other. So, because of that head start, one edge propagates farther along its respective delay line compared to the other, before being captured. Also, the capture clock of the “late” LCB will occur later compared to the “early” LCB, which gives the launch edge with the head start even more time to travel through inverters before it is captured, compared to the other.

Thus, by locating the edges in the delay lines110A,110B, first with passing the local launch clock106A,106B through the respective mux126,128, and then, switching the muxes126,128to pass the remote launch clocks, e.g.,106B,106A, respectively, global clock skew can also be quantified. By utilizing the muxes126,128to select the remote launch clock, total timing uncertainty can be measured more completely.

FIG. 3Bshows a gate level diagram of the example ofFIG. 3B, with like features labeled identically. In this example, each delay line110A,110B is N series connected inverters130which drive the delay tap outputs114. Each N bit register112A,112B includes N master-slave type flip flops or latches132. After setting each of muxes126,128to select an input, the measurement begins when the local LCB102A,102B drives the corresponding selected launch clock106A,106B to enable the latches132in the corresponding registers112A,112B. Coincidentally, the selected clock passes through the muxes126,128and begins propagating through the selected delay path122,124, i.e., the respective series connected inverters130. When the local capture clock108A,108B arrives, the state of the inverters130is captured in the respective registers110A,110B.

Thus, in the above examples, the raw data that is captured in the capture latches (e.g.,132of registers112A,112B) as a pattern of alternating 0's and 1's from the inverters130in the corresponding delay chains110A,110B. As noted above, edges may be identified by a switch in the pattern, e.g., from 1's and 0's to 0's and 1's and back. So, the exception in the alternating pattern locates where an edge has been captured and is an identical pair of consecutive 0's or consecutive 1's. These locations can be identified by exclusive ORing (XOR) or NORing (XNOR) the contents of adjacent latches132, which results in a 0 (or 1) in the clock edge locations and 0s (or 1s) in all remaining locations. Further, the clock edge locations can be more precisely located by including one or more variable delay stages in delay lines110A,110B or for LCBs102A,104A to slew the clock edges within a delay stage, such that the edges move to the next or the previous stage.

FIG. 4shows an example of a selectable delay inverter140for sliding the timing edges to more precisely locate the timing edges within the delay110. Essentially, in this example, selectable delay inverter140includes a single inverter142with three parallel selectable inverters144,146,148. Inverter142includes a single p-type field effect transistor (PFET)142P and a single n-type field effect transistor (NFET)142N connected at the drains at output1400and in series between a supply (Vdd) and ground. Each selectable inverter144,146,148includes a select PFET144SP,146SP,148SP between the supply and an inverter PFET144P,146P,148P and a select NFET144SN,146SN,148SN connected between a inverter NFET144N,146N,148N and ground. The drain of each inverter PFET144P,146P,148P is connected to a corresponding inverter NFET144N,146N,148N at output1400, which is the common connection to the drains of all inverter PFETs142P,144P,146P,148P and NFETs142N,144N,146N,148N. The input1401of selectable delay inverter140is the common gate connection to the gates of all inverter PFETs142P,144P,146P,148P and NFETs142N,144N,146N,148N. Each of the parallel selectable inverters144,146,148are selected/deselected by a corresponding pair of complementary select signals, collectively, S1, S2, S3.

Maximum selectable delay inverter140delay is realized with all of the parallel selectable inverters144,146,148deselected and only inverter142driving output1400. Selectable delay inverter140delay is reduced by selecting one or more of parallel selectable inverters144,146,148, effectively increasing the output1400drive. Correspondingly, selectable delay inverter140delay is increased from minimum (with all three selectable inverters144,146,148enabled) by deselecting one or more of parallel selectable inverters144,146,148, effectively decreasing the output1400drive. Although each of the parallel selectable inverters144,146,148may be tailored to provide different delay reductions, preferably, each provides an identical delay difference, e.g., 3 picosecond (3 ps) delay increase/reduction for a normal delay line inverter delay of 20 ps. Thus, for example, the selectable delay inverter140may be set for minimum delay with all of the parallel selectable inverters144,146,148selected. Once the edges are located, e.g., deselecting all 3 parallel selectable inverters144,146,148, in subsequent passes to scan the edges past the delay path inverter/capture latch boundaries by sequentially selecting additional parallel selectable inverters144,146,148.

FIG. 5shows a cross sectional example of an application of preferred embodiment logic timing uncertainty quantifier150, e.g.,122ofFIG. 3A, selectively timed with a selectable delay inverter e.g.,140ofFIG. 4, that is capable of holding and passing captured edges on for subsequent analysis. Shift logic152selectively passes the contents of capture register112A to a sticky register154, e.g., an N−1 bit register. A counter156counts for a selected period and at the end of the period the output (a sticky_mode line)158of the counter156initiates sticky mode in shift logic152, accumulating capture edge locations. The sticky register154contents are provided to error-detect logic160, which identifies shifting timing edges for example, and provides an error indication162upon detection of an error.

So, when the counter156receives a request for sticky mode, the counter156delays until a selected count completes, e.g., counting down to delay data logging until after certain start-up transients have subsided. Optionally, a binary delay cycle number may be scanned into the counter156with the counter156counting down to zero from that number. Once the count down is complete, the counter output158is asserted to initiate sticky mode and data logging begins. Additionally in this example, selectable delay inverter140provides a fine delay adjust in the delay line path for better than single inverter time resolution, e.g., 3 ps increments, to more precisely locate where in the captured bucket (register latch location) the captured edges fall. For example, if the inverter delay is 20 ps, captured edges may be located anywhere within that 20 ps interval. Adding fine delay in 3 ps increments, e.g., by deselecting parallel inverters (144,146,148inFIG. 4) until an edge moves to the next bucket (i.e., is captured in the next capture latch), accurately locates the edge within the 20 ps window. With each measurement, error detect logic160compares the edge bit locations in the sticky-register with a programmable (trigger_mask) mask, i.e., a bit set that pre-defines valid edge locations or valid edge ranges. An edge falling outside of this valid bit range or zone is an error. Upon occurrence of an error, the error output signal162is initiated and provided, for example, to a service processor to log the event and other selected system state information.

FIG. 6shows a cross sectional example of data logging logic152with reference to the example ofFIG. 5. In this example, one or more of the capture registers (e.g.,12A with representative latches130i,130i+1) selectively provide data to the sticky register154, which preferably is a parallel in/serial out shift register. A single sticky register latch154L is shown in this cross section. The data logging logic152includes an XNOR1522performing a bitwise compare at each neighboring pair of capture latches132i,132i+1with a match indicating the forward edge of the clock. When an edge is captured, the compare results in a single 1 at an XNOR1522at the captured edge from the 2 consecutive 1's or 0's and zeros elsewhere. The XNOR1522output is an input to an AND gate1524and hold select not (hold_mode_n) is a second input. The output of AND gate1524is an input to OR gate1526. A second AND gate1528combines the hold/sticky select signal (hold_mode or sticky_mode) with a corresponding sticky register bit (sticky_reg_q(i)) and its output is a second input to OR gate1526. Optionally, each of1524,1526and1528may be a NAND gate, which is logically equivalent to the illustrative AND-OR combination. The output of OR gate1526is an input to sticky shift MUX1530and an adjacent sticky register bit (sticky_reg_q(i+1)) is a second input. The output of sticky shift MUX1530is an input to the sticky register154.

In hold mode, the capture latch data, i.e., from one capture register112N, is written into and frozen in a separate register, i.e., the sticky register154. Similarly, in sticky mode the capture latch edges can accumulate over a number of cycles in the sticky register154. So, if timing uncertainty causes a previously captured edge to move to another capture latch, then the sticky register154location of the originally captured edge keeps the 1 state. However, the capture latch also captures the bit location corresponding to the new position. In this way, the extremes of the movement (total timing uncertainty) of the captured edges are detected and stored in the sticky register154. Also, the sticky register contents can be read out on the fly using a functional shift, i.e., without using scan-path latches and without stopping the clocks. Then, a service processor (not shown) can perform data logging on the output and analyze the edge detection events stored in the sticky register.

Furthermore, the preferred logic stage counter may be adapted for providing for highly accurate digital duty cycle monitoring and correction. Clock duty cycle is the percentage of the clock cycle that the clock signal is high. Many circuits require a duty cycle that is as close to 50% as possible. Microprocessors especially require a well-controlled duty cycle for equally distributed timing, e.g. for clock doubling performance improvement techniques. Dynamic circuits and arrays, for example, can use (i.e., trigger on) mid-cycle edges. Thus, for these types of clock doubled circuits, duty cycle is a critical design parameter; and an especially important parameter is the timing relationship of the mid-cycle edge with respect to the full-cycle edge. Previously, PLLs relied on analog duty cycle monitoring/correction of the clock signal output. However, these prior PLLs did not correct duty cycle distortion that the clock distribution tree/buffers introduced, which reduced the half cycle (i.e., clock doubled) logic path because of necessary guardbanding.

However,FIG. 7shows an example of application of a preferred timing edge uncertainty/distortion measurement circuit170(a variation on the logic timing uncertainty quantifier150ofFIGS. 5 and 6with like elements labelled identically) for highly accurate digital duty cycle monitoring and correction according to a preferred embodiment of the present invention. In this embodiment the select logic126′ (e.g., a 4:1 mux) receives the global clock104being provided to the LCB102. Also, tap inverters172are available to tune the delay line110(again at least 3 clock cycles long, e.g., 128+ inverters) and invert the tap outputs (i.e., outputs of inverters130-0,130-1,130-2,130-3, . . . ,130-(N−1)) to provide inputs to N bit capture register112, at each of register latches132-0,132-1,132-2, . . . ,132-(N−1). The capture register112has outputs174-0,174-1,174-2, . . . ,174-(N−1) that are inputs to shift logic152′, which is substantially simpler for duty cycle measurement. Essentially, the shift logic152′ includes N XNORs176-0,176-1,176-2, . . . ,176-(N−1), each providing an input to 2 input AND gates178-1,178-2, . . . ,178-(N−1), which in turn each provide an input to a corresponding latch154-0,154-1,154-2, . . . ,154-(N−1) in the sticky register154. An inverter180-1,180-2, . . . ,180-(N−2) at the output of each XNOR176-0,176-1,176-2, . . . ,176-(N−2) provides a second input to a corresponding one of the AND gates178-1,178-2, . . . ,178-(N−1).

The global clock102simultaneously enters both the LCB104and the mux126′ and begins traversing the delay line110. Alternating ones and zeroes latch in each of the register latches132-0,132-1,132-2, . . . ,132-(N−1), except at an edge. Again at each timing edge, latch contents match in at least two adjacent register latches132-0,132-1,132-2, . . . ,132-(N−1). So, a logic one will be present only at an edge in the outputs of each of the XNORs176-0,176-1,176-2, . . . ,176-(N−2), at the edge, i.e., at matching adjacent register latches132-0,132-1,132-2, . . . ,132-(N−1). Occasionally, contents in several consecutive register latches132-0,132-1,132-2, . . . ,132-(N−1) may match, e.g., due to latch metastability from late/early edge arrival. If this occurs, multiple adjacent ones are present in the outputs of each of the XNORs176-0,176-1,176-2, . . . ,176-(N−2). However, since inverters180-1,180-2, . . . ,180-(N−2) preceding an edge provide ones, while inverters180-1,180-2, . . . ,180-(N−2) at the edge (i.e., receiving a one from an XNOR output) provide zeros; only the first encountered AND gate178-1,178-2, . . . ,178-(N−1) receives both ones and a one only passes through the first AND gate178-1,178-2, . . . ,178-(N−1). Thus, the shift logic152′, essentially filters the capture register112results such that a single one is latched at each edge in a corresponding location in the sticky register154. The space between ones in capture register112is a measure of each “half” cycle and, therefore equal spacing indicates a balanced 50% duty cycle. Any difference is a measurement of timing uncertainty/distortion and may be quantified and provided as PLL correction signals for adjusting the global clock102to provide highly accurate timing and duty cycle.

It should be noted that the mux126′ in this embodiment selects from the global clock104,2remote clocks (e.g., as shown in the cross-coupled example ofFIG. 3A) and, optionally, from the LCB102clock output. The selected clock passes from the mux126′ down the delay line110. In particular, the mux126′ is tuned to minimize the global clock input104delay attributable to the mux126′, such that the clock edge is captured in the first capture register latch132-0, i.e., locating to in the first capture register latch132-0. This tuning, which is a benefit for testing because it locates the to edge with certainty, is affected by intentionally introducing a race condition. The race condition allows the global clock104to traverse the mux126′ and through the first inverter130-0in time to be captured in the first capture register latch132-0, as it is clocked by the local clock from the LCB102. Thus, the race condition guarantees that the cycle-starting edge of the global clock, the falling edge in this duty cycle example, is captured in the first latch132-0, which provides a “t0” reference mark in the capture register in each captured set of clock periods and most efficiently uses the delay line. So every cycle, the capture register112′ latches the raw data in the delay line110to take a snapshot of the state of the clocks traversing the delay line110, i.e., at the outputs of inverters130-0,130-1,130-2,130-3, . . . ,130-(N−1).

As with the example ofFIG. 3A, the global clocks may be sent from two preferred timing edge uncertainty/distortion measurement circuits170, located some distance away from each other, for cross-coupled measurements. By cross-coupling, any skew between the global clocks104A and104B causes a difference in delay line taps that may be determined by comparing the contents of the two capture registers112, the result of which provides global clock skew data.

Optionally in this embodiment, the delay line110is insensitive to supply voltage variations, e.g., tap inverters130-0,130-1,130-2,130-3, . . . ,130-(N−1) and the capture register112are Vddinsensitive or supplied from a stable, relatively noise free supply connection, e.g., a separate Vddand ground (GND). Thus in this optional embodiment, more duty cycle measurement accuracy may be realized, free from supply originated variations, by separating theses circuits112,130from the on-chip power supply and connecting to a dedicated Vddand GND.

FIGS. 8A-Bshow an example of preferred compare logic160′ for generating edge correction signals based on timing edge uncertainty/distortion measurements for digital duty cycle correction and a timing diagram representing the relationship of edge measurements according to a preferred embodiment of the present invention. The compare logic160′ includes a pair of m bit edge detect muxes182L and182H, where m is large enough to detect a high to low transition and a low to high transition, respectively. So, for a 128 bit sticky register154m is 8, for indicating 0-127. The output of edge detect mux182L passes to a first input of a subtractor188. The output of the other edge detect mux182H passes directly to the other input of the subtractor188. The output of edge detect mux182L passes to comparators190U and190D, which compare the results of the subtractor188with the value at the output of edge detect mux182L. Duty cycle error extraction circuits192U,192D (e.g., twos complement adders/subtractors) also receive the output of edge detect mux182L and the subtractor188results and determine the magnitude of any difference between the two, i.e., a duty cycle error signal. The comparators190U,190D determine whether that difference is passed as an up signal (UP) or a down signal (DOWN) from AND gates194U,194D in this example. If the duty cycle is balanced, both the UP and DOWN are zero.

So, for example, edge detect muxes182L and182H may be gated by expected edge locations, e.g., for a 30/30 tap delay duty cycle at sticky register154outputs sticky_reg-q(29), sticky_reg-q(30), sticky_reg-q(31) and sticky_reg-q(32), and at sticky_reg-q(58), sticky_reg-q(59), sticky_reg-q(60) and sticky_reg-q(61), respectively. With reference toFIG. 8B, an eight bit value corresponding to each expected edge location may be input to the respective edge detect muxes182L and182H with the actual edge location selecting the corresponding value, b and a, respectively. The difference (B) in the two values from the subtractor188indicates the duration of one of the two phases, and the value a is the duration of the other phase. Duty cycle error extraction circuits192U,192D provide the magnitude of duty cycle error for each corresponding phase, which is further characterized by the comparators190U,190D. In this example, the up/down signals, UP/DOWN from AND gates194U,194D, may be four bits wide.

FIG. 9, which shows an example of application of the timing edge uncertainty/distortion measurement circuit170ofFIG. 7and the compare logic160′ ofFIG. 8, substantially similar to the example ofFIG. 5with like elements labelled identically. In this example, the up/down signals194U,194D are then returned to a digital duty cycle correction circuit196in the PLL198, which adjusts the duty cycle of global clock104until both correction signals194U,194D are 0.

Alternately, instead of generating UP/DOWN correction signals in hardware194U,194D, the corrections may be determined in software, e.g., running on a service processor. In this alternate embodiment, the sticky register contents are serially scanned out to determine the edge locations, i.e., by identifying scan string location. The processor then calculates correction signals based on edge locations and passes those calculated correction signals back to the PLL.

Advantageously, the present invention facilitates the determination of duty cycle timing uncertainty in synchronous very large scale integration (VLSI) chips such as microprocessors and the like. By the first edge (t0) is located in the first capture register latch benefits testing because it locates the t0edge in the chain with certainty. Further, by detecting clock edge locations and calculating the distance (which corresponds to time) between falling-rising and rising-falling edges from these detected locations, these calculated distances are translated to a pair of digital correction signals. The magnitude of the digital correction signals indicates the difference between the two distances and are passed to the PLL for duty cycle correction. So, designers can compensate more accurately for clock duty cycle variation rather than budgeting a portion of the useful cycle as dead time to compensate for estimated such variations. By contrast, the present invention facilitates measuring this total duty cycle uncertainty and, further, precisely locating upper and lower bounds under real chip workloads. Thus, the present invention allows designers to determine the number of combinational logic stages that can be completed in a cycle, factoring in all sources of timing uncertainty, including duty cycle uncertainty, on a cycle-by-cycle basis.

While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. It is intended that all such variations and modifications fall within the scope of the appended claims. Examples and drawings are, accordingly, to be regarded as illustrative rather than restrictive.