Device and method for digitizing pet radiation events

A device and method used in the high resolution Positron Emission Tomography (PET) systems for digitizing radiation events for a scintillation camera and a data acquisition system. The device comprises a scintillation digitizer, including a plurality of comparators and amplifiers, two ADCs, and an analyzer for resolving the digital values of radiation events. The method comprises comparing a plurality of analog electric pulses generated upon radiation event detections with a reference voltage corresponding to an energy level of interest, amplifying all of the signals with two groups of coefficients, summing the two groups of amplified signals, digitizing the summed signals, and analyzing the digitized sums to determine digital values corresponding to a plurality of the radiation events.

TECHNICAL FIELD

This invention relates to the field of positron emission tomography (PET). More particularly, the present invention relates to signal processing devices and methods used in PET front-end electronics.

BACKGROUND

Positron emission tomography (PET) is a technique used in clinical medicine and biomedical research to create images that show anatomical structures as well as how certain tissues are performing their physiological functions. Radioactive nuclei are introduced into the body as labels on tracer molecules. These nuclei emit positrons which collide with electrons in the tissue. Each collision constitutes an annihilation event that may result in two gamma photons. By detecting the gamma photons and processing the result with image processing tools, an image of the activity in the tissue can be produced to display the physiological functions.

In positron emission tomography (PET) systems, a scintillation light pulse generated upon the interaction of a photon from the annihilation event with a scintillator is collected by photomultiplier tubes (PMT), or avalanche photodiodes (APD), and converted into a charge pulse. Hamamatsu Photonics K.K. Electron Tube Center,Fundamental and Applications of Photomultiplier Tube, JP:Hamamatsu Photonics K.K, 1995, the contents of which are hereby incorporated by reference, provides further details on the PMT. The charge pulse is often amplified and filtered to form a new voltage pulse that has a peak amplitude proportional to the area under the original scintillation light pulse, and hence proportional to the amount of photon energy that is deposited in the scintillator during the interaction. The peak amplitude is then sampled and converted into digital data by use of analog-to-digital converters (ADCs) for subsequent processing. An event time is typically obtained by using constant fraction discriminators (CFDs). Depth of Interaction Detector Block for High Resolution Positron Emission Tomography (U.S. Pat. No. 6,288,399 to Andreaco et al.), provides further details on implementation of PET detectors.

Efforts to achieve higher spatial resolution and a larger imaging volume have led to use of more and more small scintillators in PET design. Since every scintillator output needs to be separately processed, the number of ADC channels in a modern PET system is rapidly increasing. In addition, as faster scintillators and a 3D imaging mode are more widely used, high-speed ADCs are often desirable. However, a PET system that employs a large number of high-speed ADCs not only consumes a large amount of power, but also is often too expensive for many applications.

SUMMARY

Consistent with embodiments of the present invention, methods and devices may be provided for digitizing Gamma ray energy and characterizing peak time and decay time constant with a minimum number of ADCs.

Consistent with the present invention, a method is performed by a PET system for digitizing radiation events. The method includes combining a group of analog voltage pulses generated by PET detectors to create fewer analog signals than the number of analog voltage pulses in the group, digitizing the created analog signals, and analyzing the digitized signals to obtain a digitized voltage value of each individual analog voltage pulse in the group.

Also consistent with the invention, a device may provide electronic means to carry out the method of digitizing PET radiation events by using minimum number of ADCs. The device may include plural sets of amplifiers, each set of amplifiers coupled to receive a same group of analog voltage pulses generated by PET detectors; a plurality of adders, each coupled to receive outputs from one set of amplifiers of the plural sets of amplifiers and to sum the outputs into one signal; a plurality of ADCs, each ADC coupled to receive an output of one of the adders to convert the output into digital form; and an analyzer coupled to receive outputs of the plurality of ADCs to determine digital voltage value of each individual voltage pulse in the group of analog voltage pulses.

DETAILED DESCRIPTION

FIG. 1illustrates an exemplary PET system100consistent with the present invention. PET system100includes a PMT detector102to detect light pulses from a scintillator (not shown) and convert the detection result into a charge pulse. Detector102includes circuitry for amplifying and filtering the charge pulse to provide a voltage pulse. An analog subsection104of PET system100receives and processes the voltage pulse. Analog subsection104includes a digitizer106to digitize the voltage pulse and to provide, in digital form to a digital subsection108, parameters of the voltage pulse that are relevant to PET event detection. Digital subsection108performs all of the digital signal processing procedures needed by a PET system, and the results of the digital processing by digital subsection108can be further transmitted to other systems by a communication subsection110, or displayed on a console and image reconstruction subsection112.

Communication subsection110may be any appropriate type of communication system or device used to transmit the results of the digital processing. Console and image reconstruction subsection112may include any appropriate type of console device or computer system used to display the results of the digital processing from Digital subsection108.

FIG. 2shows an exemplary voltage pulse generated by a PET detector102, in particular, a lutetium oxyorthosilicate crystal coupled PMT (LSO/PMT) detector, upon interaction of a gamma ray photon with the LSO. The pulse is measured across a resistor that is directly connected to the LSO/PMT detector. The illustrated exemplary voltage pulse was sampled by using a digital oscilloscope at a 5 GHz sampling rate. The peak time and decay constant observed from numerous such pulses are about 10 ns and 40-45 ns, respectively.

FIG. 3illustrates a block diagram of a digitizer200corresponding to digitizer106inFIG. 1. Digitizer200may be based on any appropriate type of mechanisms, such as application specific integrated circuit (ASIC), field programmable gate array (FPGA), and/or a combination of software programs and a microprocessor. As shown inFIG. 3, digitizer200comprises a plurality of inputs202-1to202-n; a plurality of comparators204-1to204-n; a plurality of gates206-1to206-n; two sets of amplifiers, the first set including a plurality of amplifiers208-11to208-1nand the second set including a plurality of amplifiers208-21to208-2n; two adders210-1and210-2; two analog-to-digital converters (ADCs)212-1and212-2; a non-zero selector214; an analyzer216; a reference voltage input218; and an output220. It should be understood that the number of components, the reference voltage levels, and steps for performing the invention are exemplary and not intended to be limiting. The number of components or devices may be changed, the order of the components may be changed, the functionalities of components may be combined into different components without departing from the principle and scope of the present invention.

During operations of digitizer200, inputs202-1to202-nreceive a plurality of analog voltage pulses Vi(t) generated by PET detectors that need to be processed. The total number n of analog voltage pulses is determined based on the actual algorithms used, which will be explained in detail in the descriptions corresponding toFIGS. 4 and 5. The received analog voltage pulses may or may not be pre-amplified. First inputs of comparators204-1to204-nare coupled to receive the plurality of analog voltage pulses from the inputs202-1to202-n, respectively. Second inputs of comparators204-1to204-nare coupled to receive a reference voltage Vreffrom input218. The reference voltage Vrefis a pre-determined voltage level of interest such that any input voltage pulse Vi(t) lower than Vrefis considered to have a zero magnitude and only an input voltage pulse Vi(t) higher than or equal to Vrefis considered as a valid detected event.

Inputs of gates206-1to206-nare coupled to inputs202-1to202-n, respectively, to receive the analog voltage pulses Vi(t). Outputs of gates206-1to206-nare coupled both to inputs of the first set of amplifiers208-11to208-1n, respectively, and to inputs of the second set of amplifiers208-21to208-2n, respectively. Gates206-1to206-nare also coupled to be controlled by outputs of comparators204-1to204-n, respectively. Each of comparators204-1to204-nis configured to provided an output equal to the reference voltage Vrefif the corresponding analog voltage pulse on the first input of the comparator is less than or equal to the reference voltage Vref. If an output of a comparator equals the reference voltage Vref, the gate corresponding to the comparator will be turned off under the control of the output of the comparator. Otherwise, the gate will be turned on to permit an analog voltage pulse on the input of the gate to reach two corresponding amplifiers. If the analog voltage pulse is greater than the reference voltage Vref, then the output of the comparator is substantially equal to the analog voltage pulse, which is higher than the reference voltage Vref.

Two sets of amplifiers208-11to208-1nand208-21to208-2namplify the same plurality of analog voltage pulses separately according to different algorithms. Operations of the amplifiers208-11to208-1nand208-21to208-2nwill be explained in detail below with reference toFIGS. 4 and 5. Adder210-1is coupled to receive all outputs of amplifiers208-11to208-1n. Adder210-1sums all received outputs into one output signal. Similarly, adder210-2is coupled to receive all outputs of amplifiers208-21to208-2n, and adder210-2sums all received outputs into one output signal. ADCs212-1and212-2are coupled to convert output signals from adders210-1and210-2, respectively, into digital form. ADCs212-1and212-2are high-speed, high-precision analog-to-digital converters (ADCs). The precision of ADCs212-1and212-2is preferably higher than what is needed for converting any individual analog input voltage within the plurality of analog voltage pulses.

Non-zero selector214is coupled to receive outputs from comparators204-1to204-nto determine whether a particular output is zero, which means whether an output is equal to the reference voltage Vref. Non-zero selector214outputs the determined result in a suitable format, including but not limiting to a bit-mask representation. Analyzer216is coupled to receive digital outputs from ADCs212-1and212-2and non-zero selector214. Using the digital outputs from ADCs212-1and212-2, and the output from non-zero selector214, analyzer216performs various arithmetic operations according to different algorithms that may be used to practice the present invention, details of which are explained in the descriptions corresponding toFIGS. 4 and 5. As a result of the arithmetic operations, analyzer216determines a digital value for each individual analog voltage pulse of the plurality of analog voltage pulses. Analyzer216then outputs the digital values corresponding to the individual analog voltage pulses on output220. Output220provides digital signals to other digital signal processing units (not shown) for further PET signal processing. It is understood that all the components shown inFIG. 3may be implemented individually or may be implemented on a single VLSI device such as ASIC, FPGA or FPAA. Computer software may also be used to achieve the same result when appropriately implemented.

FIG. 4is a diagram of logic300representing a non-limiting example of the operation of digitizer106in a manner consistent with the present invention.FIG. 4shows receipt of analog voltage pulses V0, V1, . . . , Vn-1at inputs202-1to202-n, respectively. The logical operations performed by comparators204-2and gates206-2are represented by logic blocks. For example, the test of whether an analog voltage pulse is greater than Vrefis represented by logic such as logic block302-1. More specifically, as previously explained, any voltage pulse Vi(t) lower than Vrefis considered to have a zero magnitude. Thus, each such voltage pulse having a magnitude lower than Vrefis assigned a magnitude of zero resulting in the “N” (no) response when the assigned magnitude is tested as to whether it is greater than zero. Alternatively, if the magnitude of the voltage pulse is greater than or equal to Vref, its actual value is compared to zero, and the result of the test is “Y” (yes).

In the case the test result is “N,” the value V=0 (block304-1a) is assigned to a computational term Vs0(block306-1). If the test result is “Y,” the value V is determined as the actual value V of the voltage pulse amplified, e.g., by amplifier208-11, to provide an amplified value of V=V+0×2r(block304-1b). This amplified value is assigned to the computational term Vs0. Further details regarding the magnitude of amplification are provided below.

InFIG. 4, the computational terms Vs0+ . . . +Vs, n-1are applied to functional blocks308-1and308-2. Functional block308-1represents amplifiers208-11to208-1nand adder210-1, and functional block308-2represents amplifiers208-21to208-2nand adder210-2. Since, in general, the digital conversion performed by an ADC is done via quantization, an output value of an ADC does not correspond to a unique input value, but to a small range of input values. The resolution or precision of an ADC is thus the number of unique output values representing the analog input signal, and is generally represented by the number of bits. For an ADC with an s-bit precision, the ADC can have 2s−1 unique output values. The higher the precision of an ADC, the more unique output values it can have. InFIG. 4, m-bit precision ADCs are used in the illustrated embodiment. Among m bits, only r bits are required to convert any input analog voltage, where m is greater than r.

An integer k is defined such that k<m−r. A total number of n analog voltage pulses V0, V1, . . . , Vn-1may then be combined together as a group, where n=1, 2, 4, . . . , 2k. Accordingly, n inputs202-1to202-n; n comparators204-1to204-n; n gates206-1to206-n; two sets of amplifiers, the first set including n amplifiers208-11to208-1nand the second set including n amplifiers208-21to208-2n; two adders210-1and210-2; two analog-to-digital converters (ADCs)212-1and212-2; a non-zero selector214; an analyzer216; a reference voltage input218; and an output220are implemented to perform the logical operations represented inFIG. 4. If any input analog voltage pulse Viis lower than the reference voltage Vref, the input analog voltage pulse Viis considered as a zero voltage, and is not involved in further processing. If any input analog voltage pulse Viis considered as a non-zero voltage, then a voltage of i×2ris added to the pulse Viby the corresponding amplifier208-1i. This results in an amplified analog voltage pulse:
Vs,i=Vi+i×2r,
where i=0, 1, . . . , n−1. The amplified voltage pulse is then applied to adder210-1. The resulting summed signal from adder210-1is in the form:
Vd1=Vs0+Vs1+ . . . +Vs, n-1,  (1)
where Vs0is either V0=0 or V0+0×2r, Vs1is either V1=0 or V1+1×2r, . . . , and Vs,n-1is either Vn-1=0 or Vn-1+(n−1)×2r, according to the logic described above.

The same input analog voltage pulse Viis, at the same time, processed by a second set amplifier208-2n, but in a reversed sequence. Instead of adding a voltage of i×2r, a voltage of (n−1−i)×2ris added by a corresponding amplifier208-2n. In the case that the analog voltage pulse is greater than Vref, this results in an amplified analog voltage pulse of:
Vs,i=Vi+(n−1−i)×2r,
where i=0, 1, . . . , n−1. The amplified voltage pulse is then applied to adder210-2. The resulting summed signal from adder210-2is in the form of:
Vd2=Vs0+Vs1+ . . . +Vs, n-1(2)
where Vs0is either V0=0 or V0+(n−1)×2r, Vs1is either V1=0 or V1+(n−1)×2r, . . . , and Vs,n-1is either Vn-1=0 or Vn-1+0×2r.

The summed signals from adders210-1and210-2, within functional blocks308-1and308-2, respectively, are digitized by ADCs212-1and212-2, respectively. The digitized results representing equations (1) and (2) are provided to analyzer216corresponding to logic block310.

Analyzer216solves equations (1) and (2) to obtain digital values of individual analog pulses V0, V1, . . . , Vn-1. It should be understood that equations (1) and (2) may be solved individually, or solved in combination. In a timing window, there may be only two variables are not less than Vref. If there are more than two variables larger than Vref, although less likely, all events in the timing window may be discarded. Further, equations (1) and (2) may be simplified by identifying the zero voltage pulse using non-zero selector214.

FIG. 5is a diagram of logic400representing another non-limiting example of the operation of digitizer106in a manner consistent with the present invention. InFIG. 5, functional block402-1represents amplifiers208-11to208-1nand adder210-1, and functional block402-2represents amplifiers208-21to208-2nand adder210-2. InFIG. 5, m-bit precision ADCs are also used. A total number of m analog voltage pulses Vd=[V0, V1, . . . , Vm-1] may be received for processing, that is, n is equal to m. Accordingly, n number of inputs202-1to202-n; n comparators204-1to204-n; n gates206-1to206-n; two sets of amplifiers, the first set including n amplifiers208-11to208-1nand the second set including n amplifiers208-21to208-2n; two adders210-1and210-2; two analog-to-digital converters (ADCs)212-1and212-2; a non-zero selector214; an analyzer216; a reference voltage input218; and an output220are provided. The first set of amplifiers208-11to208-1napply a set of coefficients αi=[α0,i, α1,i, . . . , αm-1,i]Tto the input analog voltage pulses. As a result, outputs from ADC212-1can then be represented as:
Vd·αi,

Similarly, the second set of amplifiers208-21to208-2napply a different set of coefficients βi=[β0,i+β1,i+ . . . +βm-1,i]Tto the input analog voltage pulses. As a result, outputs from ADC212-2can be represented as:
Vd·βi.
Coefficient sets αiand βimay be determined according to the structure of digitizer200or to the geometry of PET system100. For example, αimay be chosen as αi=I+1; and βimay be chosen as βi=m−i. Therefore, analyzer216may determine a digital value of each individual analog voltage pulse by solving the following equations (3) and (4):
α0V0+α1V1+ . . . +αm-1Vm-1=Vd1,  (3)
β0V0+β1V1+ . . . +βm-1Vm-1=Vd2,  (4)
Any zero input analog voltage pulse may be omitted from equations (3) and (4) with the information provided by non-zero selector214, to simplify the computation. As explained above, in a timing window, there may be only two variables are not less than Vref. If there are more than two variables larger than Vref, although less likely, all events in the timing window may be discarded. Equations (3) and (4) may be solved similarly as to equations (1) and (2).