Method for manufacturing silicon carbide semiconductor device

A method for manufacturing a silicon carbide semiconductor device includes steps below. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface having a maximal diameter greater than 100 mm, is prepared. An impurity region is formed on a side of the first main surface of the silicon carbide substrate. In a plan view, a cover member is arranged on the side of the first main surface so as to cover at least the entire impurity region. The silicon carbide substrate is annealed at a temperature lower than a melting point of the cover member while the cover member is arranged on the side of the first main surface of the silicon carbide substrate.

TECHNICAL FIELD

This invention relates to a method for manufacturing a silicon carbide semiconductor device and particularly to a method for manufacturing a silicon carbide semiconductor device in which warpage can be lessened and adhesion of an impurity can be suppressed.

BACKGROUND ART

In order to allow a semiconductor device such as a metal oxide semiconductor field effect transistor (MOSFET) to be high in breakdown voltage and low in loss and to be used in a high-temperature environment, silicon carbide has recently increasingly been adopted as a material forming a semiconductor device. Silicon carbide is a wide band gap semiconductor greater in band gap than silicon which has conventionally widely been used as a material forming a semiconductor device. Therefore, by adopting silicon carbide as a material forming a semiconductor device, a higher breakdown voltage and a lower on-resistance of a semiconductor device can be achieved. A semiconductor device in which silicon carbide has been adopted as a material is also advantageous in that lowering in characteristics during use in a high-temperature environment is less than in a semiconductor device in which silicon has been adopted as a material.

For example, Japanese Utility Model Laying-Open No. 4-34732 (PTD 1) describes an apparatus for annealing a wafer. With the apparatus for manufacturing by annealing of a wafer, a GaAs wafer is annealed, with a ring-shaped cover over the GaAs wafer being provided to cover only an outer circumferential portion of the GaAs wafer having a diameter of 76 mm.

S. J. Pearton and R. Caruso, “Rapid thermal annealing of GaAs in a graphite susceptor-comparison with proximity annealing,” J. Appl. Phys. 66 (2), 15 Jul. 1989, page 663-665 (NPD 1) describes a method of rapid thermal annealing, with a GaAs substrate being arranged in a susceptor made of graphite. According to the rapid thermal annealing method, a GaAs substrate is annealed, with a graphite cap being arranged above the GaAs substrate having a diameter of 2 inches (approximately 50 mm).

CITATION LIST

Patent Document

Non Patent Document

SUMMARY OF INVENTION

Technical Problem

When warpage of a silicon carbide substrate is great, in arranging the silicon carbide substrate, for example, on a surface of a substrate holding portion, a region where the silicon carbide substrate is in contact with the surface of the substrate holding portion and a region where the silicon carbide substrate is not in contact with the surface of the substrate holding portion are created. Therefore, for example, in a step of activation annealing for activating an impurity or in a step of annealing a silicon carbide substrate such as alloying annealing in which an electrode is alloyed, a region of the silicon carbide substrate in contact with the substrate holding portion is more likely to be heated by heat conduction from the substrate holding portion than a region not in contact with the substrate holding portion, which results in failure in uniform heating of the silicon carbide substrate. This will be a cause for non-uniformity of electrical characteristics of a silicon carbide semiconductor device including the silicon carbide substrate. As described in the document, when a diameter is not greater than approximately 76 mm, warpage of a silicon carbide semiconductor substrate is not so great. When a diameter is greater than 100 mm, however, warpage of a silicon carbide semiconductor substrate is noticeably great.

Furthermore, adhesion of an impurity such as sodium or iron to a surface of a silicon carbide semiconductor substrate may cause degradation in characteristics such as lowering in threshold voltage or lowering in breakdown voltage of a silicon carbide semiconductor device.

The present invention was made to solve the problem as above, and an object thereof is to provide a method for manufacturing a silicon carbide semiconductor device in which warpage can be lessened and adhesion of an impurity can be suppressed.

Solution to Problem

A method for manufacturing a silicon carbide semiconductor device according to the present invention includes the steps below. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface having a maximal diameter greater than 100 mm, is prepared. An impurity region is formed on a side of the first main surface of the silicon carbide substrate. In a plan view, a cover member is arranged on the side of the first main surface so as to cover at least the entire impurity region. The silicon carbide substrate is annealed at a temperature lower than a melting point of the cover member while the cover member is arranged on the side of the first main surface of the silicon carbide substrate.

Advantageous Effects of Invention

According to the present invention, a method for manufacturing a silicon carbide semiconductor device in which warpage can be lessened and adhesion of an impurity can be suppressed can be provided.

DESCRIPTION OF EMBODIMENTS

Description of Embodiment of Invention of Present Application

An embodiment of the present invention will be described hereinafter with reference to the drawings. In the drawings below, the same or corresponding elements have the same reference characters allotted and description thereof will not be repeated. In addition, regarding crystallographic denotation herein, an individual orientation, a group orientation, an individual plane, and a group plane are shown in [ ], < >, ( ), and { }, respectively. Moreover, a crystallographically negative index is expressed by a number with a bar “-” thereabove, however, a negative sign herein precedes a number. In expressing an angle, a system in which a total azimuth angle is defined as 360 degrees is employed.

(1) A method for manufacturing a silicon carbide semiconductor device1according to the embodiment includes steps below. A silicon carbide substrate10having a first main surface10aand a second main surface10bopposite to first main surface10a, first main surface10ahaving a maximal diameter greater than 100 mm, is prepared. An impurity region4is formed on a side of first main surface10aof silicon carbide substrate10. A cover member2is arranged on the side of first main surface10aso as to cover at least the entire impurity region4in a plan view. Silicon carbide substrate10is annealed at a temperature lower than a melting point of cover member2while cover member2is arranged on the side of first main surface10aof silicon carbide substrate10.

According to the method for manufacturing silicon carbide semiconductor device1according to the above, cover member2is arranged on the side of first main surface10aof silicon carbide substrate10so as to cover at least the entire impurity region4in a plan view, and silicon carbide substrate10is annealed at a temperature lower than a melting point of cover member2while cover member2is arranged on the side of first main surface10aof silicon carbide substrate10. Since cover member2is arranged on the side of first main surface10aof silicon carbide substrate10, warpage of silicon carbide substrate10can be lessened by a weight of cover member2. Since silicon carbide substrate10is annealed while cover member2is arranged on the side of first main surface10aof silicon carbide substrate10so as to cover the entire impurity region4, adhesion of such a metal impurity as sodium in the vicinity of impurity region4can be suppressed.

(2) In the method for manufacturing silicon carbide semiconductor device1according to (1), preferably, in the step of arranging cover member2, cover member2satisfying a condition that an absolute value of a difference between a first amount of warpage and a second amount of warpage is not greater than 100 μm is arranged, with an amount of warpage of silicon carbide substrate10at a room temperature being defined as the first amount of warpage and an amount of warpage of cover member2at a room temperature being defined as the second amount of warpage. Thus, a gap between first main surface10aof silicon carbide substrate10and cover member2can effectively be made smaller. Consequently, adhesion of such a metal impurity as sodium in the vicinity of impurity region4can be suppressed.

(3) In the method for manufacturing silicon carbide semiconductor device1according to (1) or (2), preferably, the first main surface has a maximal diameter not smaller than 150 mm. Thus, warpage of silicon carbide substrate10can effectively be lessened even in such a situation that a diameter of silicon carbide substrate10is greater and silicon carbide substrate10tends to warp.

(4) In the method for manufacturing silicon carbide semiconductor device1according to any of (1) to (3), preferably, silicon carbide substrate10has a thickness not greater than 700 μm. Thus, warpage of silicon carbide substrate10can effectively be lessened even in such a situation that a thickness of silicon carbide substrate10is smaller and silicon carbide substrate10tends to warp.

(5) In the method for manufacturing silicon carbide semiconductor device1according to any of (1) to (4), preferably, a width of cover member2along first main surface10aof silicon carbide substrate10is greater than a width of first main surface10a. Thus, warpage of silicon carbide substrate10can effectively be lessened and adhesion of a metal impurity to first main surface10aof silicon carbide substrate10can effectively be suppressed.

(6) In the method for manufacturing silicon carbide semiconductor device1according to any of (1) to (5), preferably, the step of arranging cover member2includes the step of arranging cover member2as being in contact with first main surface10aof silicon carbide substrate10. The step of annealing silicon carbide substrate10includes the step of activating an impurity in impurity region4. Since cover member2is thus arranged as being in contact with first main surface10aof silicon carbide substrate10, adhesion of such a metal impurity as sodium to first main surface10aof silicon carbide substrate10can be suppressed.

(7) In the method for manufacturing silicon carbide semiconductor device1according to (6), preferably, cover member2is made of a material containing at least any of carbon and silicon carbide. Thus, adhesion of such a metal impurity as sodium to first main surface10aof silicon carbide substrate10can effectively be suppressed also in a temperature range of annealing for activating an impurity in impurity region4.

(8) In the method for manufacturing silicon carbide semiconductor device1according to any of (1) to (5), preferably, a gate electrode27provided to face impurity region4of silicon carbide substrate10is formed after impurity region4is formed. An interlayer insulating film21covering gate electrode27is formed. A source electrode16in contact with first main surface10aof silicon carbide substrate10is formed. The step of arranging cover member2includes the step of arranging cover member2so as to be in contact with interlayer insulating film21and distant from source electrode16. Since cover member2is thus distant from source electrode16, reaction between cover member2and source electrode16resulting in variation in contact resistance between source electrode16and silicon carbide substrate10can be suppressed.

(9) In the method for manufacturing silicon carbide semiconductor device1according to (8), preferably, the cover member is made of a material containing at least any of carbon, silicon, quartz, and silicon carbide. Thus, adhesion of such a metal impurity as sodium to first main surface10aof silicon carbide substrate10can effectively be suppressed also in a temperature range of alloying source electrode16.

(10) The method for manufacturing silicon carbide semiconductor device1according to any of (1) to (9) preferably further includes the step of pressing cover member2against silicon carbide substrate10after the step of arranging cover member2. Thus, since a gap between cover member2and silicon carbide substrate10is made smaller, adhesion of such a metal impurity as sodium to first main surface10aof silicon carbide substrate10can effectively be suppressed. In addition, since silicon carbide substrate10is heated by heat conduction through a mechanism pressing cover member2against silicon carbide substrate10, a temperature in silicon carbide substrate10is made uniform. Consequently, warpage of silicon carbide substrate10can effectively be lessened.

(11) The method for manufacturing silicon carbide semiconductor device1according to (10) preferably further includes the step of holding silicon carbide substrate10on a substrate holding portion3such that second main surface10bof silicon carbide substrate10faces a surface3aof substrate holding portion3after the step of forming impurity region4. In the step of pressing cover member2against silicon carbide substrate10, cover member2is pressed against silicon carbide substrate10such that a gap between an outer circumferential portion10cof second main surface10bof silicon carbide substrate10and surface3aof substrate holding portion3is made smaller. Since a gap between outer circumferential portion10cof second main surface10bof silicon carbide substrate10and surface3aof substrate holding portion3is thus made smaller, heat from substrate holding portion3can effectively conduct to silicon carbide substrate10. Consequently, a temperature in silicon carbide substrate10is made uniform and warpage of silicon carbide substrate10can effectively be lessened.

Details of Embodiment of Invention of Present Application

A construction of a MOSFET1representing a silicon carbide semiconductor device according to one embodiment of the present invention will initially be described. Referring toFIG. 1, MOSFET1according to the present embodiment mainly has silicon carbide substrate10, gate electrode27, a gate insulating film15, interlayer insulating film21, source electrode16, a surface protecting electrode19, a drain electrode20, and a backside protecting electrode23. Silicon carbide substrate10has first main surface10aand second main surface10bopposite to first main surface10aand mainly includes a silicon carbide single-crystal substrate11and a silicon carbide epitaxial layer5provided on silicon carbide single-crystal substrate11.

Silicon carbide single-crystal substrate11is composed of single crystals of hexagonal silicon carbide having, for example, a polytype of 4H. First main surface10aof silicon carbide substrate10has a maximal diameter greater than 100 mm, preferably not smaller than 150 mm, and more preferably not smaller than 200 mm. First main surface10aof silicon carbide substrate10is, for example, a {0001} plane or a surface angled off by not greater than 8° from the {0001} plane. Specifically, first main surface10ais, for example, a (0001) plane or a surface angled off by approximately not greater than 8° from the (0001) plane, and second main surface10bis a (000-1) plane or a surface angled off by approximately not greater than 8° from the (000-1) plane. Silicon carbide substrate10has a thickness, for example, not greater than 700 μm and preferably not greater than 600 μm. Silicon carbide substrate10has a thickness preferably not smaller than 250 μm and smaller than 600 μm, more preferably not smaller than 300 μm and smaller than 600 μm, further preferably not smaller than 250 μm and not greater than 500 μm, and further preferably not smaller than 350 μm and not greater than 500 μm.

Silicon carbide epitaxial layer5has a drift region12, a body region13, a source region14, and a contact region18. Drift region12is an n-type (a first conductivity type) region containing such an impurity as nitrogen. An impurity concentration in drift region12is, for example, around 5.0×1015cm−3. Body region13is a region having a p-type (a second conductivity type). An impurity contained in body region13is, for example, aluminum (Al) or boron (B). A concentration of an impurity contained in body region13is, for example, around 1×1017cm−3.

Source region14is an n-type region containing such an impurity as phosphorus. Source region14is formed in body region13as being surrounded by body region13. Source region14is higher in impurity concentration than drift region12. An impurity concentration in source region14is, for example, 1×1020cm−3. Source region14is spaced apart from drift region12by body region13.

Contact region18is a p-type region. Contact region18is provided as being surrounded by source region14and formed as being in contact with body region13. Contact region18contains such an impurity as Al or B at a concentration higher than a concentration of an impurity contained in body region13. A concentration of an impurity such as Al or B in contact region18is, for example, 1×1020cm−3.

Gate insulating film15is formed as being in contact with first main surface10aof silicon carbide substrate10so as to extend from an upper surface of one source region14to an upper surface of the other source region14. Gate insulating film15is in contact with source region14, body region13, and drift region12at first main surface10aof silicon carbide substrate10. Gate insulating film15is composed, for example, of silicon dioxide.

Gate electrode27is arranged as being in contact with gate insulating film15so as to extend from above one source region14to above the other source region14. Gate electrode27is formed on source region14, body region13, and drift region12, with gate insulating film15being interposed. Gate electrode27is formed of a conductor such as polysilicon doped with an impurity or Al.

Source electrode16extends from above each of a pair of source regions14to above contact region18in a direction away from gate insulating film15and is arranged as being in contact with first main surface10aof silicon carbide substrate10. Source electrode16is in contact with source region14and contact region18at first main surface10aof silicon carbide substrate10. Source electrode16contains, for example, TiAlSi and is in ohmic contact with source region14and contact region18in silicon carbide substrate10.

Interlayer insulating film21is provided to cover gate electrode27and to be in contact with gate electrode27and gate insulating film15. Interlayer insulating film21electrically isolates gate electrode27and source electrode16from each other. Surface protecting electrode19is formed as being in contact with source electrode16and contains a conductor such as Al. Surface protecting electrode19is electrically connected to source region14through source electrode16.

Drain electrode20is provided on second main surface10bof silicon carbide substrate10as being in contact therewith. Drain electrode20may be composed of another material such as nickel silicide (NiSi) which can establish ohmic contact with silicon carbide single-crystal substrate11. Drain electrode20is thus electrically connected to silicon carbide single-crystal substrate11. Backside protecting electrode23is formed as being in contact with a main surface of drain electrode20opposite to silicon carbide single-crystal substrate11. Backside protecting electrode23has a stack structure constituted, for example, of a Ti layer, a Pt layer, and an Au layer.

A method for manufacturing MOSFET1representing the silicon carbide semiconductor device according to the present embodiment will now be described.

Initially, a silicon carbide substrate preparing step (S10:FIG. 2) is performed. For example, silicon carbide single-crystal substrate11is prepared by slicing an ingot composed of single crystals of hexagonal silicon carbide formed with a sublimation method and having polytype 4H. Then, silicon carbide epitaxial layer5is formed on silicon carbide single-crystal substrate11, for example, with chemical vapor deposition (CVD). Specifically, a carrier gas containing hydrogen (H2) and a source gas containing monosilane (SiH4), propane (C3H8), and nitrogen (N2) are supplied over silicon carbide single-crystal substrate11, and silicon carbide single-crystal substrate11is heated to a temperature, for example, approximately not lower than 1500° C. and not higher than 1700° C. Thus, as shown inFIG. 3, silicon carbide epitaxial layer5is formed on silicon carbide single-crystal substrate11. As above, silicon carbide substrate10having first main surface10aand second main surface10bopposite to first main surface10ais prepared. Silicon carbide substrate10includes silicon carbide single-crystal substrate11forming second main surface10band silicon carbide epitaxial layer5provided on silicon carbide single-crystal substrate11and forming first main surface10a.

Referring toFIG. 4, first main surface10aof silicon carbide substrate10has a substantially annular shape, and first main surface10ahas a maximal diameter D1greater than 100 mm, preferably not smaller than 150 mm, and more preferably not smaller than 200 mm. Silicon carbide substrate10has a thickness T (seeFIG. 5), for example, not greater than 700 μm and preferably not greater than 600 μm. Silicon carbide substrate10has a thickness preferably not smaller than 250 μm and smaller than 600 μm, more preferably not smaller than 300 μm and smaller than 600 μm, further preferably not smaller than 250 μm and not greater than 500 μm, and further preferably not smaller than 350 μm and not greater than 500 μm.

An amount of warpage of silicon carbide substrate10and an amount of warpage of cover member2will be described with reference toFIGS. 5 and 6.

Referring toFIG. 5, when silicon carbide substrate10is arranged, for example, on flat surface3aof substrate holding portion3, due to warpage of silicon carbide substrate10, a central portion of second main surface10bof silicon carbide substrate10is in contact with surface3aof substrate holding portion3, whereas an outer circumferential portion of second main surface10bof silicon carbide substrate10is distant from surface3aof substrate holding portion3. An amount of warpage h of silicon carbide substrate10represents a distance from a position max in second main surface10bwhere second main surface10bof silicon carbide substrate10is most distant from surface3aof substrate holding portion3to surface3aof substrate holding portion3(in other words, a position min where second main surface10bof silicon carbide substrate10is closest to surface3aof substrate holding portion3) in a cross-sectional view (a field of view in a direction in parallel to surface3aof substrate holding portion3). As shown inFIG. 5, a case that silicon carbide substrate10warps as protruding toward surface3aof substrate holding portion3is herein defined as negative warpage.

Referring toFIG. 6, a case that silicon carbide substrate10warps as protruding in a direction opposite to surface3aof substrate holding portion3is defined as positive warpage. In this case, when silicon carbide substrate10is arranged, for example, on flat surface3aof substrate holding portion3, due to warpage of silicon carbide substrate10, the outer circumferential portion of second main surface10bof silicon carbide substrate10is in contact with surface3aof substrate holding portion3, whereas the central portion of second main surface10bof silicon carbide substrate10is distant from surface3aof substrate holding portion3. A first amount of warpage h of silicon carbide substrate10represents a distance from position max in first main surface10awhere first main surface10aof silicon carbide substrate10is most distant from surface3aof substrate holding portion3to position min in first main surface10awhere first main surface10aof silicon carbide substrate10is closest to surface3aof substrate holding portion3in a cross-sectional view. Definition of an amount of warpage of cover member2which will be described later is the same as the definition of the amount of warpage of silicon carbide substrate10. The amount of warpage of each of cover member2and silicon carbide substrate10is measured while silicon carbide substrate10or cover member2is arranged on flat surface3aat a room temperature (27° C.) and cover member2and silicon carbide substrate10are not clamped, for example, by an electrostatic chuck.

Then, an impurity region forming step (S20:FIG. 2) is performed. Specifically, referring toFIG. 7, ions are implanted into first main surface10aof silicon carbide substrate10. For example, aluminum (Al) ions are implanted into first main surface10aof silicon carbide substrate10, so that body region13having the p conductivity type is formed in silicon carbide epitaxial layer5. Then, for example, ions of phosphorus (P) are implanted into body region13to a depth smaller than an implantation depth of Al ions, so that source region14having the n conductivity type is formed. For example, Al ions are further implanted into source region14, so that contact region18surrounded by source region14, having a depth as large as source region14, and having the p conductivity type is formed. A region in silicon carbide epitaxial layer5where none of body region13, source region14, and contact region18is formed is defined as drift region12. As above, impurity region4formed through ion implantation, which includes body region13, source region14, and contact region18, is formed on a side of first main surface10aof silicon carbide substrate10. First main surface10aof silicon carbide substrate10may include impurity region4and outer circumferential portion10cwhere impurity region is not formed.

Then, a first cover member arranging step (S30:FIG. 2) is performed. Specifically, referring toFIGS. 8 and 9, in a plan view (a field of view along a direction of normal to first main surface10a), first cover member2is arranged on the side of first main surface10aof silicon carbide substrate10so as to cover at least the entire impurity region4including body region13, source region14, and contact region18. Preferably, as shown inFIG. 8, first cover member2is arranged as being in contact with first main surface10aof silicon carbide substrate10. First cover member2should only be in contact with at least a part of first main surface10aof silicon carbide substrate10and does not have to be in contact with the entire first main surface10a. For example, first cover member2may be provided as being in contact with impurity region4exposed at first main surface10aand as being distant from an outer circumferential portion10dof first main surface10a.

As shown inFIG. 14, in a cross-sectional view, a width W2of first cover member2along first main surface10aof silicon carbide substrate10may be greater than a width W1of first main surface10ain the direction along first main surface10a. Preferably, first cover member2is made of a material containing at least any of carbon and silicon carbide. In other words, first cover member2may be a carbon layer or a silicon carbide layer, a member obtained by coating a surface of a silicon carbide layer with a carbon layer, or a member obtained by coating a surface of a carbon layer with a carbon layer denser than the former carbon layer. First cover member2may be arranged such that a coated layer faces first main surface10aof silicon carbide substrate10. Preferably, first cover member2is composed of polycrystalline silicon carbide. Polycrystalline silicon carbide is smaller in amount of warpage and lower in cost than single-crystal silicon carbide.

In the first cover member arranging step (S30:FIG. 2), first cover member2satisfying a condition that an absolute value of a difference between a first amount of warpage and a second amount of warpage is not greater than 100 μm is arranged as being in contact with first main surface10aof silicon carbide substrate10, with an amount of warpage of silicon carbide substrate10at a room temperature being defined as the first amount of warpage and an amount of warpage of first cover member2at a room temperature being defined as the second amount of warpage. First amount of warpage h of silicon carbide substrate10is, for example, 50 μm when first main surface10ais a silicon face, and it is, for example, −50 μm when first main surface10ais a carbon face. When first main surface10ais the silicon face, silicon carbide substrate10warps as first main surface10aprotrudes as shown inFIG. 6. An amount of warpage of first cover member2is, for example, approximately not smaller than −50 μm and not greater than 50 μm.

Referring toFIG. 9, as first cover member2is arranged on first main surface10aof silicon carbide substrate10, an amount of warpage of silicon carbide substrate10is reduced by the weight of first cover member2. Namely, an amount of warpage g of silicon carbide substrate10after first cover member2is arranged is smaller than first amount of warpage h of silicon carbide substrate10before first cover member2is arranged. When an absolute value of a difference between the first amount of warpage of silicon carbide substrate10and the second amount of warpage of first cover member2is small, an area of contact between first main surface10aof silicon carbide substrate10and first cover member2increases. Namely, since a gap between first main surface10aof silicon carbide substrate10and first cover member2is smaller, for example, adhesion of such an impurity as sodium onto first main surface10aof silicon carbide substrate10can effectively be suppressed. Preferably, first cover member2is arranged on the side of first main surface10aof silicon carbide substrate10such that a direction of warpage of first cover member2(positive and negative of warpage) is the same as a direction of warpage of silicon carbide substrate10(positive and negative of warpage). First cover member2is preferably greater in thickness than silicon carbide substrate10. First cover member2has a thickness, for example, approximately not smaller than 300 μm and not greater than 1 mm. First cover member2is merely arranged on first main surface10aof silicon carbide substrate10and not fixed to silicon carbide substrate10.

Then, an activation annealing step (S40:FIG. 2) is performed. Specifically, silicon carbide substrate10is annealed at a temperature lower than a melting point of cover member2while cover member2is arranged on the side of first main surface10aof silicon carbide substrate10. More specifically, second main surface10bof silicon carbide substrate10is arranged on surface3aof substrate holding portion3and held on substrate holding portion3while impurity region4is in contact with first cover member2at first main surface10aof silicon carbide substrate10. Silicon carbide substrate10and first cover member2are heated to a temperature, for example, not lower than 1600° C. and not higher than 2000° C. for approximately 30 minutes. Thus, impurities in impurity region4formed in the ion implantation step are activated and desired carriers are thus generated.

With arrangement of cover member2on the side of first main surface10aof silicon carbide substrate10in the activation annealing step (S40:FIG. 2), adhesion of such a metal impurity as sodium (Na) and iron (Fe) present in an annealing furnace to first main surface10aof silicon carbide substrate10can be suppressed. A metal impurity may be chromium (Cr), copper (Cu), zinc (Zn), calcium (Ca), potassium (K), manganese (Mn), magnesium (Mg), cobalt (Co), nickel (Ni), and aluminum (Al). A density of each of the metal impurities on first main surface10aof silicon carbide substrate10after the activation annealing step (S40:FIG. 2) is desirably less than 1×1012atoms/cm2. A density of a metal impurity can be measured with inductively coupled plasma mass spectrometry (ICP-MS) or fluorescent X-rays.

Referring toFIG. 10, after first cover member2is arranged, first cover member2may be pressed against silicon carbide substrate10. Specifically, for example, a pressing portion6made of carbon is arranged on a surface of first cover member2opposite to the surface in contact with silicon carbide substrate10and pressing portion6is moved downward from above inFIG. 10(in other words, in a direction from first main surface10ato second main surface10bof silicon carbide substrate10) to press first cover member2against silicon carbide substrate10. As shown inFIG. 10, pressing portion6may be arranged on a center side of first cover member2in a cross-sectional view. Alternatively, as shown inFIG. 15, pressing portion6may be arranged on an outer circumferential side of first cover member2in a cross-sectional view.

When pressing portion6is arranged on the center side of first cover member2in a cross-sectional view, the center side of first cover member2is pressed against a center side of first main surface10aof silicon carbide substrate10, so that an amount of warpage of silicon carbide substrate10is reduced. When pressing portion6is arranged on the outer circumferential side of first cover member2, the outer circumferential side of first cover member2is pressed against an outer circumferential side of first main surface10aof silicon carbide substrate10so that an amount of warpage of silicon carbide substrate10is reduced.

After the impurity region forming step (S20:FIG. 2), silicon carbide substrate10may be held on substrate holding portion3such that second main surface10bof silicon carbide substrate10faces surface3aof substrate holding portion3. Preferably, when first cover member2is pressed against silicon carbide substrate10, first cover member2is pressed against silicon carbide substrate10such that gap g between outer circumferential portion10cof second main surface10bof silicon carbide substrate10and surface3aof substrate holding portion3is made smaller (seeFIGS. 9 and 15). Preferably, first cover member2is pressed against silicon carbide substrate10such that outer circumferential portion10cof second main surface10bof silicon carbide substrate10is in contact with surface3aof substrate holding portion3.

The step of pressing first cover member2against silicon carbide substrate10may be performed during or before the activation annealing step (S40:FIG. 2). In other words, first cover member2and silicon carbide substrate10may be heated after first cover member2is pressed against silicon carbide substrate10, or first cover member2may be pressed against silicon carbide substrate10after silicon carbide substrate10is heated and an amount of warpage of silicon carbide substrate10increases, so that an amount of warpage of silicon carbide substrate10may be reduced. After the activation annealing step ends, first cover member2is removed from first main surface10aof silicon carbide substrate10.

Then, a gate insulating film forming step (S50:FIG. 2) is performed. Referring toFIG. 11, for example, gate insulating film15composed of silicon dioxide is formed to cover first main surface10aof silicon carbide substrate10, by heating silicon carbide substrate10for approximately 1 hour in an atmosphere containing, for example, oxygen, for example, at 1350° C. Specifically, gate insulating film15is formed as being in contact with drift region12, body region13, source region14, and contact region18at first main surface10a, so as to extend from one contact region18to the other contact region18.

Then, a gate electrode forming step (S60:FIG. 2) is performed. Gate electrode27being in contact with gate insulating film15and composed of polysilicon containing an impurity is formed, for example, with low pressure chemical vapor deposition (LPCVD). Gate electrode27is formed to face source region14and body region13representing impurity region4, with gate insulating film15being interposed.

Then, an interlayer insulating film forming step (S70:FIG. 2) is performed. Interlayer insulating film21composed of silicon dioxide is formed to cover gate electrode27and to be in contact with gate insulating film15and gate electrode27, for example, with plasma (P)-CVD. In other words, interlayer insulating film21is formed such that gate electrode27is surrounded by gate insulating film15and interlayer insulating film21.

Then, a source electrode forming step (S80:FIG. 2) is performed. Referring toFIG. 12, interlayer insulating film21and gate insulating film15are removed in a region where source electrode16is to be formed, and a region where source region14and contact region18are exposed through interlayer insulating film21and gate insulating film15is formed. Then, source electrode16containing, for example, NiSi or TiAlSi (titanium aluminum silicon) is formed in that region, for example, through sputtering. Source electrode16is formed as being in contact with source region14and contact region18at first main surface10aof silicon carbide substrate10.

Then, a second cover member arranging step (S90:FIG. 2) is performed. Specifically, second cover member2is arranged on the side of first main surface10aof silicon carbide substrate10so as to cover at least the entire impurity region4including body region13, source region14, and contact region18in a plan view. Preferably, as shown inFIG. 13, second cover member2is arranged on the side of first main surface10aof silicon carbide substrate10so as to be in contact with interlayer insulating film21and distant from source electrode16.

As shown inFIG. 14, in a cross-sectional view, width W2of second cover member2along first main surface10aof silicon carbide substrate10may be greater than width W1of first main surface10ain the direction along first main surface10a. Preferably, second cover member2is made of a material containing at least any of carbon, silicon, quartz, and silicon carbide. In other words, second cover member2may be a carbon layer or a silicon carbide layer, a member obtained by coating a surface of a silicon carbide layer with a carbon layer, or a member obtained by coating a surface of a carbon layer with a carbon layer denser than the former carbon layer. First cover member2may be arranged such that a coated layer faces first main surface10aof silicon carbide substrate10. Preferably, first cover member2is composed of polycrystalline silicon carbide. Polycrystalline silicon carbide is smaller in amount of warpage and lower in cost than single-crystal silicon carbide.

In the second cover member arranging step (S90:FIG. 2), second cover member2satisfying a condition that an absolute value of a difference between a first amount of warpage and a second amount of warpage is not greater than 100 μm is arranged on the side of first main surface10aof silicon carbide substrate10, with an amount of warpage of silicon carbide substrate10at a room temperature being defined as the first amount of warpage and an amount of warpage of second cover member2at a room temperature being defined as the second amount of warpage. An amount of warpage of second cover member2is, for example, approximately not smaller than −50 μm and not greater than 50 μm.

Referring toFIG. 9, as second cover member2is arranged on the side of first main surface10aof silicon carbide substrate10, an amount of warpage of silicon carbide substrate10is reduced by the weight of second cover member2. When an absolute value of a difference between the first amount of warpage of silicon carbide substrate10and the second amount of warpage of second cover member2is small, an area of contact between interlayer insulating film21provided on the side of first main surface10aof silicon carbide substrate10and second cover member2increases. Namely, since a gap between interlayer insulating film21provided on the side of first main surface10aof silicon carbide substrate10and second cover member2is made smaller, for example, diffusion of such an impurity as sodium into an interface between first main surface10aof silicon carbide substrate10and gate insulating film15can effectively be suppressed. Preferably, second cover member2is arranged on the side of first main surface10aof silicon carbide substrate10such that a direction of warpage of second cover member2(positive and negative of warpage) is the same as a direction of warpage of silicon carbide substrate10(positive and negative of warpage). Second cover member2is preferably greater in thickness than silicon carbide substrate10. Second cover member2has a thickness, for example, approximately not smaller than 300 μm and not greater than 1 mm. Second cover member2is merely arranged on interlayer insulating film21provided on the side of first main surface10aof silicon carbide substrate10and not fixed to interlayer insulating film21.

Then, a source electrode annealing step (S100:FIG. 2) is performed. Specifically, second main surface10bof silicon carbide substrate10is arranged as being in contact with surface3aof substrate holding portion3such as a tray and held on substrate holding portion3while second cover member2is arranged on the side of first main surface10aof silicon carbide substrate10so as to be in contact with interlayer insulating film21and distant from source electrode16. Silicon carbide substrate10provided with source electrode16and second cover member2are preferably annealed for approximately 5 minutes at a temperature not lower than 900° C. and not higher than 1300° C. Thus, at least a part of source electrode16is silicided and source electrode16in ohmic contact with source region14and contact region18is formed.

When cover member2is arranged on the side of first main surface10aof silicon carbide substrate10in the source electrode annealing step (S100:FIG. 2), adhesion of a metal impurity such as sodium (Na) and iron (Fe) present in an annealing furnace to first main surface10aof silicon carbide substrate10can be suppressed. A metal impurity may be chromium (Cr), copper (Cu), zinc (Zn), calcium (Ca), potassium (K), manganese (Mn), magnesium (Mg), cobalt (Co), nickel (Ni), and aluminum (Al). A density of each of the metal impurities at the interface between first main surface10aof silicon carbide substrate10and gate insulating film15after the source electrode annealing step (S100:FIG. 2) is desirably less than 1×1012atoms/cm2. A density of a metal impurity can be measured with ICP-MS or fluorescent X-rays.

Second cover member2may be pressed against interlayer insulating film21provided on the side of first main surface10aof silicon carbide substrate10. Specifically, for example, pressing portion6made of carbon is arranged on a surface of second cover member2opposite to the surface in contact with interlayer insulating film21of silicon carbide substrate10and pressing portion6is moved in a direction from first main surface10ato second main surface10bof silicon carbide substrate10to press second cover member2against interlayer insulating film21provided on silicon carbide substrate10. Pressing portion6may be arranged on a center side of second cover member2in a cross-sectional view, or pressing portion6may be arranged on an outer circumferential side of second cover member2in a cross-sectional view.

Silicon carbide substrate10may be held on substrate holding portion3such that second main surface10bof silicon carbide substrate10faces surface3aof substrate holding portion3. Preferably, when second cover member2is pressed against interlayer insulating film21provided on the side of first main surface10aof silicon carbide substrate10, second cover member2is pressed against silicon carbide substrate10such that gap g between outer circumferential portion10cof second main surface10bof silicon carbide substrate10and surface3aof substrate holding portion3is made smaller (seeFIGS. 9 and 15). Preferably, second cover member2is pressed against silicon carbide substrate10such that outer circumferential portion10cof second main surface10bof silicon carbide substrate10is in contact with surface3aof substrate holding portion3.

The step of pressing second cover member2against silicon carbide substrate10may be performed during or before the source electrode annealing step (S100:FIG. 2). In other words, second cover member2and silicon carbide substrate10may be heated after second cover member2is pressed against interlayer insulating film21provided on silicon carbide substrate10, or second cover member2may be pressed against interlayer insulating film21provided on silicon carbide substrate10after silicon carbide substrate10is heated and an amount of warpage of silicon carbide substrate10increases, so that an amount of warpage of silicon carbide substrate10may be reduced. After the source electrode annealing step ends, second cover member2is removed from the side of first main surface10aof silicon carbide substrate10.

Then, surface protecting electrode19is formed to be in contact with source electrode16and to cover interlayer insulating film21. Source electrode16is composed of a material containing, for example, aluminum. Then, drain electrode20composed, for example, of NiSi is formed as being in contact with second main surface10bof silicon carbide substrate10. Drain electrode20may be composed, for example, of TiAlSi. Though drain electrode20is preferably formed through sputtering, it may be formed through vapor deposition. After drain electrode20is formed, drain electrode20is heated, for example, through laser annealing. At least a part of drain electrode20is thus silicided and drain electrode20in ohmic contact with silicon carbide single-crystal substrate11is formed. Backside protecting electrode23is formed as being in contact with drain electrode20.

Though a method for manufacturing a MOSFET including both of the first cover member and the second cover member has been described in the embodiment above, a MOSFET may be manufactured with only any one of the first cover member and the second cover member being used. In the embodiment above, a MOSFET in which the n-type and the p-type are interchanged may be employed. Though a planar MOSFET has been described in the embodiment by way of example of the silicon carbide semiconductor device according to the present invention, the silicon carbide semiconductor device may be, for example, a trench MOSFET, an insulated gate bipolar transistor (IGBT), or a Schottky barrier diode.

A function and effect of the method for manufacturing a MOSFET representing the silicon carbide semiconductor device according to the present embodiment will now be described.

According to the method for manufacturing MOSFET1according to the present embodiment, cover member2is arranged on the side of first main surface10aof silicon carbide substrate10so as to cover at least the entire impurity region4in a plan view, and silicon carbide substrate10is annealed at a temperature lower than a melting point of cover member2while cover member2is arranged on the side of first main surface10aof silicon carbide substrate10. Since cover member2is arranged on the side of first main surface10aof silicon carbide substrate10, warpage of silicon carbide substrate10can be lessened by a weight of cover member2. Since silicon carbide substrate10is annealed while cover member2is arranged on the side of first main surface10aof silicon carbide substrate10so as to cover the entire impurity region4, adhesion of such a metal impurity as sodium in the vicinity of impurity region4can be suppressed.

According to the method for manufacturing MOSFET1according to the present embodiment, in the step of arranging cover member2, cover member2satisfying a condition that an absolute value of a difference between a first amount of warpage and a second amount of warpage is not greater than 100 μm is arranged, with an amount of warpage of silicon carbide substrate10at a room temperature being defined as the first amount of warpage and an amount of warpage of cover member2at a room temperature being defined as the second amount of warpage. Thus, a gap between first main surface10aof silicon carbide substrate10and cover member2can effectively be made smaller. Consequently, adhesion of such a metal impurity as sodium in the vicinity of impurity region4can effectively be suppressed.

According to the method for manufacturing MOSFET1according to the present embodiment, in the step of arranging cover member2, the first main surface has a maximal diameter not smaller than 150 mm. Thus, warpage of silicon carbide substrate10can effectively be lessened even in such a situation that a diameter of silicon carbide substrate10is greater and silicon carbide substrate10tends to warp.

According to the method for manufacturing MOSFET1according to the present embodiment, silicon carbide substrate10has a thickness not greater than 700 μm. Thus, warpage of silicon carbide substrate10can effectively be lessened even in such a situation that a thickness of silicon carbide substrate10is smaller and silicon carbide substrate10tends to warp.

According to the method for manufacturing MOSFET1according to the present embodiment, a width of cover member2along first main surface10aof silicon carbide substrate10is greater than a width of first main surface10a. Thus, warpage of silicon carbide substrate10can effectively be lessened and adhesion of a metal impurity to first main surface10aof silicon carbide substrate10can effectively be suppressed.

According to the method for manufacturing MOSFET1according to the present embodiment, the step of arranging cover member2includes the step of arranging cover member2as being in contact with first main surface10aof silicon carbide substrate10. The step of annealing silicon carbide substrate10includes the step of activating an impurity in impurity region4. Since cover member2is thus arranged as being in contact with first main surface10aof silicon carbide substrate10, adhesion of such a metal impurity as sodium to first main surface10aof silicon carbide substrate10can be suppressed.

According to the method for manufacturing MOSFET1according to the present embodiment, made of a material containing at least any of carbon and silicon carbide. Thus, adhesion of such a metal impurity as sodium to first main surface10aof silicon carbide substrate10can effectively be suppressed also in a temperature range of annealing for activating an impurity in impurity region4.

According to the method for manufacturing MOSFET1according to the present embodiment, gate electrode27provided to face impurity region4in silicon carbide substrate10is formed after impurity region4is formed. Interlayer insulating film21covering gate electrode27is formed. Source electrode16in contact with first main surface10aof silicon carbide substrate10is formed. The step of arranging cover member2includes the step of arranging cover member2so as to be in contact with interlayer insulating film21and distant from source electrode16. Since cover member2is thus distant from source electrode16, reaction between cover member2and source electrode16resulting in variation in contact resistance between source electrode16and silicon carbide substrate10can be suppressed.

According to the method for manufacturing MOSFET1according to the present embodiment, the cover member is made of a material containing at least any of carbon, silicon, quartz, and silicon carbide. Thus, adhesion of such a metal impurity as sodium to first main surface10aof silicon carbide substrate10can effectively be suppressed also in a temperature range of annealing for alloying source electrode16.

The method for manufacturing MOSFET1according to the present embodiment further includes the step of pressing cover member2against silicon carbide substrate10after the step of arranging cover member2. Thus, since a gap between cover member2and silicon carbide substrate10is made smaller, adhesion of such a metal impurity as sodium to first main surface10aof silicon carbide substrate10can effectively be suppressed. In addition, since silicon carbide substrate10is heated by heat conduction through a mechanism pressing cover member2against silicon carbide substrate10, a temperature in silicon carbide substrate10is made uniform. Consequently, warpage of silicon carbide substrate10can effectively be lessened.

The method for manufacturing MOSFET1according to the present embodiment further includes the step of holding silicon carbide substrate10on substrate holding portion3such that second main surface10bof silicon carbide substrate10faces surface3aof substrate holding portion3after the step of forming impurity region4. In the step of pressing cover member2against silicon carbide substrate10, cover member2is pressed against silicon carbide substrate10such that a gap between the outer circumferential portion of second main surface10bof silicon carbide substrate10and surface3aof substrate holding portion3is made smaller. Since a gap between the outer circumferential portion of second main surface10bof silicon carbide substrate10and surface3aof substrate holding portion3is thus made smaller, heat from substrate holding portion3can effectively conduct to silicon carbide substrate10. Consequently, a temperature in silicon carbide substrate10is made uniform and warpage of silicon carbide substrate10can effectively be lessened.

REFERENCE SIGNS LIST