Combined command and response on-chip data interface for a computer system chipset

An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention generally relates to on-chip data interfaces and in particular to integrated circuit chips having circuit units that may interchange requests and responses.

2. Description of the Related Art

Integrated circuit chips are often used for data processing and are known to comprise a number of different circuit units. Generally, each circuit unit is for performing a specific function, and of course there may be different circuit units provided on one chip for performing the same function or performing different functions. The circuit units may operate sequentially or simultaneously and they may function independently from each other or dependent on the operation of other circuit units.

In the latter case, the circuit units are usually interconnected via an interface to allow the circuit units to interchange data needed for making the operation of one circuit unit dependent on the operation of the other circuit unit. The data exchange is often done by sending transactions from one circuit unit to the other circuit unit. A transaction is a sequence of packets that are exchanged between the circuit units and that result in a transfer of information. The circuit unit initiating a transaction is called the source, and the circuit unit that ultimately services the transaction on behalf of the source is called the target. It is to be noted that there may also be intermediary units between the source and the target.

Transactions may be used to place a request or to respond to a received request. Taking the requests, posted requests may be distinguished from non-posted requests dependent on whether the request requires a response. Specifically, a non-posted request is a request that requires a response while a posted request does not require a response.

When focusing on the functions which are performed by the interconnected circuit units, the circuit units can often be divided into hosts and devices. The term host then means a circuit unit that provides services to the dependent device. A transaction from the host to the device is said to be downstream while a transaction in the other direction is said to be upstream. In bidirectional configurations, both the host and the device may send and receive requests and responses so that a device may be a source as well as a target, and the host may also function as a source as well as target.

A field where such integrated circuit chips are widely used are personal computers. Referring toFIG. 1, the hardware components of a common motherboard layout are depicted. It is to be noted that this figure shows only one example of a motherboard layout, and other configurations exist as well. The basic elements found on the motherboard ofFIG. 1include the CPU (Central Processing Unit)100, a northbridge105, a southbridge110, and system memory115. The northbridge105is usually a single chip in a core logic chip set that connects the processor100to the system memory115and, e.g., to the AGP (Accelerated Graphic Port) bus. Often a proprietary (or public) interface is provided between the processor100and northbridge105like, e.g. Athlon's proprietary FSB (Front Side Bus) EV6, the proprietary FSB (hublink) of Pentium 4, or Opteron's Hypertransport.

The southbridge110is usually the chip in a system core logic chip set that controls the IDE (Integrated Drive Electronics) or EIDE (Enhanced IDE) bus. The USB (Universal Serial Bus) that provides plug-n-play support manages the keyboard/mouse controller, provides power management features, and controls other peripherals. Common peripheral interfaces are, e.g. USB 2.0, EIDE, and SATA (Serial Advanced Technology Attachment).

FIG. 2shows the components of a typical prior art southbridge. Of course, only a design example is illustrated inFIG. 2, and other arrangements exist as well. The device comprises a host circuit210and a device circuit230. The host circuit210is connected by a chip-to-chip interface200to a northbridge or to another integrated circuit chip such as a memory controller or processor. On the other side, the southbridge includes a chip-to-peripheral interface240to connect the device circuit230to the peripherals. Further, there is an on-chip interface220provided between the host circuit210and the device circuit230. This on-chip interface is usually a split transaction interface. Split transaction interfaces are interfaces where requests and responses are transferred on the bus as completely decoupled and independent transactions.

An example of a split transaction interface is shown inFIG. 3. Usually, a split transaction interface has two components: a target interface and a source interface. The target interface is the interface where requests (also denoted as “commands”) are sent downstream, i.e. from the host300to the device345, and responses are sent upstream. On the other hand, the source interface is the interface where requests are sent upstream and responses downstream. For reasons of clarity, only the downstream parts of the interface are shown inFIG. 3.

In addition to the partitioning into the target and source interfaces, a split transaction interface is usually further split up into command interface units305,335and response interface units310,340. While the command interface unit305of the host300is connected to the command interface unit335of the device345by multiple command signal lines315,320, the response interface unit310of the host300is connected to the response interface unit340of the device345by a number of response signal lines325,330. In particular, the command signal lines include a command transfer request signal line315over which the host300provides the device345with a command transfer request signal indicating that the host300is sending a command, and one or more command data signal lines320over which the data forming the command are sent. Accordingly, the response signal lines include a response transfer request signal line325and one or more response data signal lines330.

While such a split transaction interface provides high speed data transport, this design suffers from the need for a large number of wires to implement the separated command interface units305,335and response interface units310,340. Therefore, usual split transaction interfaces have the disadvantage of low design density and efficiency and thus increased manufacturing costs.

SUMMARY OF THE INVENTION

An improved on-chip interface is therefore provided that may allow for increasing the overall architecture density and the efficiency and that may reduce the product costs.

In one embodiment, an integrated circuit chip is provided that comprises a first and a second circuit unit. Each of the first and second circuit units are capable of sending requests to the other one of the first and second circuit units. Further, each of the first and second circuit units are capable of sending back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.

In another embodiment, there may be provided a southbridge device that comprises an integrated circuit chip having a first and a second circuit unit. Each of the first and second circuit units are capable of sending requests to the other one of the first and second circuit units. Further, each of the first and second circuit units are capable of sending back a response when receiving a request that requires a response. The first circuit unit is connected to the second circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.

In a further embodiment, a method of operating an integrated circuit chip that comprises a first and a second circuit unit is provided. The method comprises sending requests from one of the first and second circuit units to the other one of the first and second circuit units and sending back a response from the other one of the first and second circuit units to the one of the first and second circuit units if the request requires a response. The method further comprises operating the first circuit unit to send to the second circuit unit request data relating to a request to be sent by the first circuit unit and response data relating to a response to be sent by the first circuit unit over a shared signal line.

DETAILED DESCRIPTION OF THE INVENTION

The illustrative embodiments of the present invention will be described with reference to the figure drawings wherein like elements and structures are indicated by like reference numbers.

Referring now to the drawings, and particularly toFIG. 4which illustrates an on-chip interface according to an embodiment, the device comprises a host circuit300and a device circuit345which are connected to each other over a number of signal lines315,325,410. In comparison toFIG. 3which shows an on-chip interface according to prior art, the downstream command and response interface units have been merged to build the host channel400,420. In the host channel400,420there may be provided a shared command/response data signal line410over which both command data forming a host command, i.e. a command to be sent downstream from the host300to the device345, and response data forming a host response, i.e. a response to be sent downstream, may be sent from the host300to the device345.

According to the present embodiment, the host300buffers host commands before decoding and forwarding them to the respective host channel400,420. Also device responses, i.e. responses to host commands, may be buffered by the host300. Therefore, the device345may be allowed to delay or pause the transmission of host requests and may further be allowed to split up the transmission of a device response. Further, the host300may be allowed to pause the transmission of host commands and device responses.

On the other hand, the device345may buffer device commands and host responses, i.e. responses to device commands. In particular, the host300may forward all incoming host responses to the device345, and it may be to the responsibility of the device345to provide sufficient buffer space for the host responses. Therefore, the device345may not be allowed to pause the transmission of device commands or to delay or pause the transmission of host responses, while the host300may be allowed to pause the transmission of device commands and host responses. Moreover, the host300may be allowed to pause the transmission of a host command in order to transmit a host response. Host responses may return out of order. It may be to the responsibility of the device345to reorder the host responses if necessary.

It is to be noted that inFIG. 4, only downstream interfaces and data lines are shown for reasons of clarity. In addition to the depicted host channel400,420, a device channel may also be provided for managing device requests and device responses sent upstream from the device345to the host300to which the presented techniques may similarly apply. For simplifying the discussion, host requests (commands) and host responses will be denoted in the following as “requests” (“commands”) and “responses”, respectively.

In the present embodiment, there may be two types of commands: read commands and write commands. For both types of commands, a command transmission may consist of an ordered sequence of phases: while for a read command, an address phase may be followed by one byte enable phase, for a write command, an address phase followed by one or multiple data phases may be transmitted. A response transmission may consist of one or multiple data phases.

According to the embodiment, the commands and responses have individual transaction enable signals, i.e. a command transfer request signal and a response transfer request signal, that may be sent from the host300to the device345over the command transfer request signal line315and the response transfer request signal line325, respectively. The assertion of those enable signals may determine the type of the current transactions, i.e. whether the host300is sending a command or a response.

The device345may comprise a command FSM (Finite State Machine) unit and a response FSM unit for processing commands and responses, respectively. The command transfer request signal line315may be connected to the command FSM unit and the response transfer request signal line325may be linked to the response FSM unit, while the shared command/response data signal line410may be coupled to both the command FSM unit and the response FSM unit.

Turning now toFIG. 5, a more detailed view of the on-chip interface according to the present embodiment is provided. As already indicated with respect toFIG. 4, the host channel400,420may transfer commands and responses from the host300to the device345. According to the present embodiment, both transactions are multiplexed on the same data bus comprising a shared command/response data signal line510, a shared command/response type signal line520, and a shared command/response tag signal line530.

During the address phase of a command, the data bus may hold the following information: a request address on the command/response data signal line510, a request type on the command/response type signal line520, and a request tag on the command/response tag signal line530in case of a non-posted request. For a posted request, the command/response tag signal may stay unchanged.

During the byte enable phase of a read command, the command/response data signal line510may hold byte enables for the first dword and/or byte enables for the last dword in case of a burst. Further, during the byte enable phase, the command/response type signal line520may hold host request information bits and the command/response tag signal line530may hold the number of dwords to read minus one.

While a data phase of a write command is transmitted, the data bus may hold a dword of write data on the command/response data signal line510, byte enables for the current write data on the command/response type signal line520, and numbers of dwords still to write in subsequent data phases on the command/response tag signal line530. The value on the command/response tag signal line530may reach zero with the last data phase of the write command.

In addition to the shared signal lines510,520,530, the host300may further be connected to the device345over a command transfer request signal line315and a response transfer request signal line325which have already been introduced when discussingFIG. 4. While the command transfer request signal being asserted may indicate that the data bus holds command data, the response transfer request signal being asserted may indicate that the bus holds response data.

According to the present embodiment, the transmission of commands and responses can be interleaved, i.e. the command transfer request signal and the response transfer request signal can be asserted alternately. The command transfer request signal and the response transfer request signal may not be set at the same time. When both the command transfer request signal and the response transfer request signal are de-asserted, the host channel400,420may be idle. When the host channel400,420enters or is in the idle state, the data bus signals may not change.

There may be a clock signal externally provided to the host300and the device345over the clock signal line500. When the host channel400,420is in the idle state, this clock signal might be gated.

A ready signal line550may allow the device345to communicate to the host300that it is ready for receiving command data: according to the present embodiment, the device345must set the ready signal on the ready signal line550when it is able to accept the next command phase. Once the ready signal is asserted, it must not de-assert it before the device345samples the command transfer request signal asserted. Further, the device345must not make the state of the ready signal dependent on the state of the command transfer request signal.

Thus, the device345may be allowed to pause or delay the transmission of a command by unsetting the ready signal. On the other hand, according to the present embodiment, the device345cannot pause the transmission of a response.

Command data may be transferred and the transmission of command data may proceed to the next phase at a rising clock edge when both the command transfer request signal and the ready signal are asserted. On the other hand, response data may be transferred and the transmission of response data may proceed to the next phase at a rising clock edge when the response transfer request signal is asserted, independently of the state of the ready signal.

The device345may have the possibility to flush outstanding data phases by setting a flush request signal on the flush request signal line560instead of the ready signal. When both the command transfer request signal and the flush request signal are asserted, no command data may be transferred and the command data transmission may complete at a rising clock edge. According to the present embodiment, the device345must only set the flush request signal during a data phase of a write command. The flush request signal and the ready signal must not be asserted at the same time. Once the flush request signal is asserted, it must stay asserted until the device345samples the command transfer request signal asserted. In order to quickly terminate a command data transmission, the host300may set the command transfer request signal immediately after sampling the flush request signal asserted without placing valid data onto the data bus.

Once the host300has asserted the command transfer request signal, it may not de-assert it until it samples the ready signal asserted and proceeds to the next command phase or it sets the response transfer request signal to transmit an interleaved response. In the present embodiment, the host300must reassert the command transfer request signal in the same clock cycle with the de-assertion of the response transfer request signal.

The transmission of a command may be paused after each transmitted phase by the host300by unsetting the command transfer request signal or by the device345by unsetting the ready signal. After the last data phase of a command transmission, the host300may be allowed to start a new transmission in the next clock cycle by keeping the command transfer request signal asserted to start another command back-to-back or by de-asserting the command transfer request signal and asserting the response transfer request signal to start a response. According to the embodiment, the host300must not transmit other commands before the transmission of a current command is completed.

During a data phase of a response, the data bus may hold a dword of response data on the command/response data signal line510in case of a response with data, i.e. a successful read response. In all other cases, i.e. non-successful or write responses, the command/response data signal may stay unchanged. Further, the bus may hold during the response data phase a response status indicating whether the data phase is the last data phase of the current response on the command/response type signal line520and a response tag on the command/response tag signal line530. The command/response tag signal may stay unchanged in all data phases of the response transmission.

According to the present embodiment, once the host300has asserted the response transfer request signal, it must not de-assert it until it has completed the transmission of the response, or it asserts the command transfer request signal to transmit an interleaved command, or it wants to pause the transmission of a response. After the last data phase of a response transmission, the host300may be allowed to start a new transmission in the next clock cycle by keeping the response transfer request signal set to start a response back-to-back, or by de-asserting the response transfer request signal and asserting the command transfer request signal to start a command. The host300may not be allowed to transmit other responses before the transmission of the current response is completed.

A response may be considered to be valid when a regarding response validation signal is set on the response validation signal line540. If the device345is required to obey the ordering rules, it may not use the response until it is valid. The device345may not make the acceptance of any posted or non-posted command contingent upon the prior reception of any response.

The host300may be allowed to set the response validation signal independently of the state of the response transfer request signal. For example, the host300may assert the response validation signal at the start of a response transmission or later. The host300may assert multiple response validation signals at the same time. Once asserted, the host300may keep the response validation signal asserted until the transmission of another response with the same tag starts.

According to the present embodiment, there may be split responses being responses with data which do not contain all the data requested from the host300. Split responses which belong to the same device request may bear the same tag, i.e. the tag of the device request. In this embodiment, split responses pertaining to the same device request must be transferred in order.

The host300may be allowed to transmit other commands or responses between split responses belonging to the same device request.

The device345may be allowed to use split responses before receiving all data requested from the host300. According to the embodiment, a successful split response transfers a response status indicating whether it completes the data requested from the host300on the command/response type signal line520. After a split response with a response status other than the status indicating that it does not complete the data requested from the host300, no more split responses which belong to the same device request follow. When the device345receives a split response with a response status other than the one indicating whether it completes the data requested from the host300, it may treat the whole response as a non-successful response with the same response status code. It is to be noted that data of previous split responses which belong to the same device request and were transferred with a response status indicating that they do not complete the data requested from the host300may be used by the device345.

Turning now toFIG. 6, a flow chart of a host channel transmission is depicted. In step600, it may be determined whether there are command data to be transmitted. If this is not the case, it may be determined in step610whether there are response data to be transmitted. If not, the processing scheme may return to step600. If there are response data to be transmitted, a corresponding response transmission may be performed in step640. This will be explained in more detail with respect toFIG. 8.

If step600yields that there are command data to be transmitted, it may be determined in step620whether there are response data to be transmitted which are preferred in view of the command data to be transmitted. If this is the case, the preferred response data may be transmitted in step640. If not, the command data may be transmitted in step630.

FIG. 7shows a flow diagram illustrating the command transmission step630ofFIG. 6. In step700, the command transfer request signal may be set on the command transfer request signal line315. In step710, it may be determined whether on the ready signal line550there is a ready signal set. If this is the case, one phase of command data may be transferred in step750. Subsequently it may be determined in step760whether there are command data left that are to be transmitted. If not, the command transfer request signal may be unset in step770and the command transmission may be complete at this point.

If step710yields that the ready signal is not set, it may be determined in step720whether the flush request signal is asserted on the flush request signal line560. If so, the command transmission scheme may proceed to step770. If the flush request signal is not set, it may be determined in step730whether there are response data to be transmitted that are preferred in view of the command data to be transmitted. If there are preferred response data to be transmitted, the command transfer request signal may be unset in step780, and instead of the command data, the preferred response data may be transmitted in step790. This may be performed according to the response transmission scheme explained below with respect toFIG. 8.

If it is determined in step730that there are no preferred response data to be transmitted, it may be queried in step740whether the transmission is to be paused. If so, the command transmission scheme may proceed to step770for unsetting the command transfer request signal, otherwise the scheme may return to step710. If step760yields that there are command data left that are to be transmitted, the command transmission scheme may proceed to step730for determining whether there are preferred response data to be transmitted.

A response transmission scheme according to an embodiment is shown in the flow diagram ofFIG. 8. The response transfer request signal may be set on the response transfer request signal line325in step800. Then, in step810, a response data phase may be transferred. In step820, it may be determined whether there are response data left that are to be transferred. If not, the response transfer request signal may be de-asserted in step850and the response transmission may be complete at this point.

If step820yields that there are response data left, it may be determined in step830whether there are command data to be transmitted which are preferred in view of the response data to be transmitted. If so, the response transfer request signal may be unset in step860and the scheme may proceed with transmitting the preferred command data in step870. This may be accomplished according to the above-described command transmission process ofFIG. 7.

If it is determined in step830that there are no preferred command data to be transmitted, it may be detected in step840whether the response transmission is to be paused. If so, the response transmission scheme may proceed to step840for unsetting the response transfer request signal. Otherwise, the scheme may return to step810for transferring another response data phase.

It is noted that the sequence of steps shown inFIGS. 6,7and8has been chosen for illustration purposes only and is not to be understood as limiting the invention. For example, the queries710to740inFIG. 7may be performed in a different order as well as the queries820to840inFIG. 8. Moreover, the role of command data and response data could be interchanged inFIG. 6.

Turning now toFIGS. 9 to 17, wave forms will be discussed in more detail that may occur when performing the process of host channel transmission. InFIG. 9, there are two read commands transmitted in cycles900and905, respectively. In each cycle, address data910,920, command type data930,940, and command tag data950,960followed by byte enables915,925, command information bits935,945, and the number of dwords to be read minus one955,965, respectively, are transmitted. As can be seen fromFIG. 9, at the time the second cycle905starts, the ready signal is still down. In the example ofFIG. 9, the device345sets the ready signal one clock later so that the device345delays the execution of the second cycle905by one clock period.

In the example ofFIG. 10, there is shown a single posted write cycle1000where following an address phase1005,1025, a first data phase1010,1030,1045, a second data phase1015,1035,1050, and a third data phase1020,1040,1055are transferred. After the host300has sent the first data phase1010,1030,1045, the device345unsets the ready signal so that the second data phase1015,1035,1050is delayed by two clock cycles.

The example ofFIG. 11shows one single posted write cycle where the host300and the device345delay the second data phase for two clocks. Once the address phase1110,1130and the first data phase1115,1135,1150have been transmitted, the host300unsets the command transfer request signal1100and the device345also de-asserts the ready signal. The ready signal is re-asserted one clock cycle later, however the second data phase1120,1140,1155and a subsequent third data phase1125,1145,1160are only transmitted when the host300also resets the command transfer request signal1105.

FIG. 12depicts a single posted write cycle where the device345flushes subsequent data phases after the second one. While the command transfer request signal1200is set, the address phase1215,1235, a first data phase1220,1240,1255, and a second data phase1225,1245,1260are transferred. Although the host300re-asserts the command transfer request signal1205, a third data phase1230,1250,1265is flushed by the device345setting the flush request signal1210.

FIG. 13depicts a read response which is stalled by two clock cycles. While the host300asserts the response transfer request signal1300, three subsequent data phases are transmitted. While the command/response data signal line holds one of the first data items1310, the second data item1315, and the third data item1320in each of the three data phases respectively, the command/response type signal line continuously holds a response status1330indicating that the current data phase is not the last data phase, and the command/response tag signal line continuously holds the response tag1340of the currently transmitted response. After a stall of two clock cycles, the response transfer request signal1305is re-asserted and, in a fourth data phase, a fourth data item1325is transmitted, the response status1335indicates that the fourth data phase is the last data phase, and the command/response tag signal line still holds the response tag1340. During the stall, the response gets validated.

FIG. 14shows the case of back-to-back read and write responses where the first response gets validated later. While the response transfer request signal1400is set, three data phases1405,1410,1415,1420,1425,1435of a read response are transmitted. Thereby, the response status1425indicates that the third data phase is the last data phase of the read response. In the next clock cycle in which the response transfer request signal1400is still asserted, a write response1430,1440is transmitted.

In the example ofFIG. 15, two responses are transmitted which get validated at the same time. While the host300asserts the response transfer request signal1505, three data phases of a first response1510,1515,1520,1530,1535,1550as well as one data phase of a second response1540,1555are transmitted. When the host300de-asserts the response transfer request signal1505and asserts the command transfer request signal1500, the transmission of an address phase1525,1545,1555of a command is started.

FIG. 16shows the wave forms of a read response and an interleaved posted write command according to an embodiment. The command transfer request signal1600,1602,1604and the response transfer request signal1606,1608,1610are alternately asserted. While the response transfer request signal1606is asserted, a first data phase1612,1624,1636of the read response is transmitted. Then, during assertion of the command transfer request signal1600, an address phase1614,1626,1636of the write command is sent, and during subsequent assertion of the response transfer request signal1608, a second data phase1616,1628,1638of the read response is transferred. When the host300asserts the command transfer request signal1602the next time, it intends to transmit a data phase1618,1630,1638of the write command. However, at this time the ready signal is not set. Therefore, the information intended to be transmitted can only be sent the next time both the command transfer request signal1604and the ready signal are asserted, i.e. in the data phase1622,1634,1642. In the meantime, a third data phase1620,1632,1640of the read response has been transmitted while the response transfer request signal1610was asserted.

InFIG. 17, an example of a split read response and an interleaved non-posted read command is illustrated. While the host300asserts the response transfer request signal1705, the first and second data phases1715,1720,1745,1750,1775of the read response are transferred. Thereby, the response status items1745and1750indicate that the response is not complete and that the response is a split response, respectively. During the time the response transfer request signal is de-asserted and the command transfer request signal1700is asserted, the data phase1725,1755,1780and the byte enable phase1730,1760,1785of the read command are transmitted. Then, by de-asserting the command transfer request signal1700and re-asserting the response transfer request signal1710, the host300resumes the transmission of the split read response, i.e. transmits a third and a fourth data phase1735,1740,1765,1770,1790.

As apparent from the above description of embodiments, a method to prevent double buffering by unhindered delivery of responses through interleaving has been presented. For efficient use of buffers, a requester of read data is to buffer the read responses. Many conventional implementations provide separate response and command interfaces to that requester so that the delivery of responses cannot be blocked, e.g., by write commands to that device. In order to save interface pins, the response and command interfaces have been merged according to the described embodiments.

Both responses and commands may have individual transaction enable signals, the described command transfer request and response transfer request signals, the assertion of which may determine the type of the current transactions. If a response is to be delivered, the command transfer request signal may be de-asserted at any stage of the transaction and the response transfer request signal may be asserted. Thus, unhindered delivery of responses may be guaranteed on a shared data bus.

The discussed embodiments may provide a response and command interleaving for, e.g., a low pin count packet-based internal bus. The described on-chip interface may be an internal high-speed interface express. Further, the presented techniques may be used in combination with AMD's 5537 chip set.

While reducing the internal interface width, the above embodiments may allow for maintaining optimized, i.e. minimal, buffer sizes. Therefore, the embodiments may improve both component density and efficiency and thus reduce manufacturing costs. While the invention has been described with respect to the physical embodiments constructed in accordance therewith, it will be apparent to those skilled in the art that various modifications, variations and improvements of the present invention may be made in light of the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention. In addition, those areas in which it is believed that those of ordinary skill in the art are familiar, have not been described herein in order to not unnecessarily obscure the invention described herein. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrative embodiments, but only by the scope of the appended claims.