Semiconductor manufacturing apparatus and method of operating the same

In one embodiment, a semiconductor manufacturing apparatus includes an electrostatic chuck that includes a base and a first electrode provided on the base and is configured to electrostatically adsorb a wafer on the first electrode. The apparatus further includes a measurement module configured to measure potential of the wafer. The apparatus further includes a controller configured to adjust potential of the base based on the potential of the wafer and to adjust potential of the first electrode based on the potential of the wafer or the base, when the potential of the wafer measured by the measurement module changes.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2015-169673, filed on Aug. 28, 2015, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor manufacturing apparatus and a method of operating the same.

BACKGROUND

For example, when a process target layer on a wafer is to be processed, the wafer is mounted on an electrostatic chuck (ESC) base through a high voltage (HV) electrode. In some cases, the process target layer, a first hard mask layer, a second hard mask layer and a resist layer are formed on the wafer, an opening that penetrates through the resist layer, the second hard mask layer and the first hard mask layer is formed by dry etching, and a portion of the process target layer within the opening is processed by dry etching.

In these cases, when the second hard mask layer is removed during the processing of the process target layer within the opening, the state of the wafer varies and the potential of the wafer is changed. Therefore, when the potential of the wafer is changed, a dry etching apparatus changes the potential of the ESC base to adjust the potential of the ESC base to be equal to the potential of the wafer. As a result, the potential difference between the wafer or ESC base and the HV electrode is changed, and a current flowing through the HV electrode increases. The increase of this current may adversely affect the dry etching.

DETAILED DESCRIPTION

In one embodiment, a semiconductor manufacturing apparatus includes an electrostatic chuck that includes a base and a first electrode provided on the base and is configured to electrostatically adsorb a wafer on the first electrode. The apparatus further includes a measurement module configured to measure potential of the wafer. The apparatus further includes a controller configured to adjust potential of the base based on the potential of the wafer and to adjust potential of the first electrode based on the potential of the wafer or the base, when the potential of the wafer measured by the measurement module changes.

First Embodiment

FIG. 1is a cross-sectional view schematically illustrating a structure of a semiconductor manufacturing apparatus of a first embodiment. The semiconductor manufacturing apparatus ofFIG. 1is a dry etching apparatus.

The semiconductor manufacturing apparatus ofFIG. 1includes a chamber11, an ESC12, an upper electrode13, an AC power supply14, a coolant feeder15, a measurement module16and a controller17. The ESC12further includes an HV electrode (lower electrode)21, an insulator22, an ESC base23, an HV power supply24and an ESC power supply25. The HV electrode21is an example of a first electrode, and the upper electrode13is an example of a second electrode.

The chamber11houses a wafer1to be processed by dry etching. An example of the wafer1is a semiconductor substrate such as a silicon substrate.FIG. 1shows an X direction and a Y direction that are parallel to a surface of the wafer1and perpendicular to each other, and a Z direction that is perpendicular to the surface of the wafer1. In this specification, a +Z direction is treated as an upward direction and a −Z direction is treated as a downward direction. The −Z direction in the present embodiment may or may not correspond to the direction of gravitational force.

FIGS. 2A and 2Bare cross-sectional views for describing operation of the semiconductor manufacturing apparatus of the first embodiment.

In the present embodiment, a process target layer2, a first hard mask layer3a, a second hard mask layer3band a resist layer4are formed on the wafer1(FIG. 2A), and the wafer1is then carried into the chamber11, for example. The process target layer2may be directly formed on the wafer1or may be formed above the wafer1through another layer. An example of the process target layer2is a tetraethyl orthosilicate (TEOS) film. An example of the first hard mask layer3ais a carbon film. An example of the second hard mask layer3bis a spin on glass (SOG) film.

Next, an opening5that penetrates through the resist layer4, the second hard mask layer3band the first hard mask layer3ais formed by dry etching in the chamber11(FIG. 2B). An example of the dry etching is reactive ion etching (RIE). The resist layer4may be intentionally removed after the etching of the second hard mask layer3b, or may be non-intentionally removed during the etching of the first hard mask layer3a.

Next, a portion of the process target layer2within the opening5is processed by dry etching in the chamber11, and the wafer1is then carried out of the chamber11. When the portion of the process target layer2within the opening5is processed by the dry etching, the second hard mask layer3bis also processed by this dry etching. Therefore, the second hard mask layer3bis removed during the processing of the process target layer2within the opening5, so that the state of the wafer varies.

Next, the description of the semiconductor manufacturing apparatus will be continued by referring again toFIG. 1.

The ESC12is used to support the wafer1in the chamber11. The HV electrode21is covered with the insulator22and provided on the ESC base23. The wafer1is mounted on the HV electrode21through the insulator22. The ESC12electrostatically adsorbs the wafer1with the HV electrode21. The wafer1can be moved up and down using a plurality of pins provided on the upper surface of the ESC12.

Reference character V1denotes the potential of the wafer1. Reference character V2denotes the potential of the HV electrode21. Reference character V3denotes the potential of the ESC base23. The HV power supply24is a variable voltage source used to adjust the potential V2of the HV electrode21. The ESC power supply25is a variable voltage source used to adjust the potential V3of the ESC base23.

The upper electrode13is located above the HV electrode21. The semiconductor manufacturing apparatus of the present embodiment generates plasma between the HV electrode21and the upper electrode13to treat the wafer1with plasma. Specifically, the resist layer4, the second hard mask layer3b, the first hard mask layer3aand the process target layer2are processed by dry etching using the plasma.

The AC power supply14supplies an AC current to the upper electrode13. Consequently, the plasma is generated between the HV electrode21and the upper electrode13.

The coolant feeder15feeds a coolant into holes H created in the HV electrode21, the insulator22and the ESC base23. Consequently, the wafer1is cooled with the coolant. An example of the coolant is a helium (He) gas. AlthoughFIG. 1shows only two holes H, the ESC12preferably includes three or more holes H.

The measurement module16measures the potential V1of the wafer1while the wafer1is treated with plasma. In other words, the potential V1of the wafer1is measured during dry etching. The potential V1of the wafer1measured by the measurement module16is output to the controller17.

The controller17controls operation of the semiconductor manufacturing apparatus of the present embodiment. The controller17controls, for example, the operation of the chamber11, the operation of the ESC12, the on/off-state and the current of the AC power supply14, the on/off-state and the feeding amount of the coolant of the coolant feeder15, the voltage of the HV power supply24, and the voltage of the ESC power supply25.

In addition, the controller17adjusts the potential V3of the ESC base23based on the potential V1of the wafer1and adjusts the potential V2of the HV electrode21based on the potential V1of the wafer1or the potential V3of the ESC base23, when the potential V1of the wafer1measured by the measurement module16changes. The potential V2of the HV electrode21can be adjusted by controlling the voltage of the HV power supply24. The potential V3of the ESC electrode23can be adjusted by controlling the voltage of the ESC power supply25. Details on such potential adjustments will be described later by referring toFIGS. 3 and 4.

FIG. 3is a graph for describing the operation of the semiconductor manufacturing apparatus of the first embodiment.

FIG. 3shows the potential V1of the wafer1and a current I2flowing through the HV electrode21. The axis of ordinates ofFIG. 3represents a voltage (V) and a current (A). The axis of abscissas ofFIG. 3represents time (second). Although the potential V1of the wafer1in the present embodiment is negative,FIG. 3shows the absolute value of the potential V1of the wafer1.

Reference character R represents a timing at which the second hard mask layer3bis removed during the processing of the process target layer2within the opening5. At this time, the state of the wafer1varies from a state where the second hard mask layer3bexists to a state where the second hard mask layer3bdoes not exist. As a result, the potential V1of the wafer1changes as shown by an arrow A1. The reason for this is that the impedance of layers on the wafer1changes when the second hard mask layer3bis removed.

Therefore, the controller17changes the potential V3of the ESC base23when the potential V1of the wafer1varies. Therefore, the controller17adjusts the potential V3of the ESC base23to be equal to the potential V1of the wafer1. The reason for this is that abnormal electrical discharge may occur between the wafer1and the ESC base23if the difference between the potential V1and the potential V3is large. When the potential V3of the ESC base23is adjusted, a potential difference V2−V1between the HV electrode21and the wafer1or a potential difference V2−V3between the HV electrode21and the ESC base23varies. Accordingly, the current I2flowing through the HV electrode21increases as shown by an arrow A2. In other words, a spike current I2is generated in the HV electrode21.

An increase in the current I2may adversely affect dry etching. The controller17therefore retains the threshold of the current I2in a storage module. An example of the threshold is 75 μA. If the current I2exceeds the threshold, the controller17outputs an error signal and forcibly stops dry etching inside the chamber11. It is preferable, however, to avoid such forced stop as much as possible.

Therefore, the controller17adjusts the potential V3of the ESC base23to be equal to the potential V1of the wafer1, when the potential V1of the wafer1varies. In addition, the controller17adjusts the potential V2of the HV electrode21so that the potential difference V2−V1between the wafer1and the HV electrode21becomes constant. For example, if the potential V1of the wafer1decreases by 1000 V, the controller17decreases the potential V3of the ESC base23by 1000 V and the potential V2of the HV electrode21by 1000 V as well. Consequently, it is possible to prevent an increase in the current I2, thereby preventing the current I2from exceeding the threshold.

As described above, when the potential V1of the wafer1measured by the measurement module16changes, the controller17adjusts the potential V3of the ESC base23to a same value as the potential V1, and adjusts the potential V2of the HV electrode21so that the potential difference V2−V1becomes constant. The controller17can therefore control the current I2flowing through the HV electrode21so as not to exceed the threshold.

Furthermore, when the potential V1of the wafer1is changed, the controller17adjusts the potential V2of the HV electrode21so that the adsorption of the wafer1by the ESC12is maintained. The ESC12of the present embodiment can adsorb the wafer1by setting the potential difference V2−V1between the wafer1and the HV electrode21to 1000 V or larger. Accordingly, the controller17adjusts the potential V2of the HV electrode21so that the potential difference V2−V1is 1000 V or larger.

For example, before the potential V1of the wafer1changes, the potential V1of the wafer1is set to −2500 V, the potential V2of the HV electrode21is set to +2500 V, and the potential V3of the ESC base23is set to −2500 V. In this case, if the potential V1of the wafer1changes from −2500 V to −3500 V, the potential V2of the HV electrode21is adjusted from +2500 V to −2500 V or higher. Since the potential V2of the HV electrode21in the present embodiment is adjusted so that the potential difference V2−V1becomes constant, the potential V2is adjusted from +2500 V to +1500 V. As a result, the potential difference V2−V1is maintained at 5000 V.

FIG. 4is a flowchart illustrating a method of operating the semiconductor manufacturing apparatus of the first embodiment.

First, the resist layer4, the second hard mask layer3band the first hard mask layer3aare processed by dry etching in the chamber11(step S1). At this time, the potential V1of the wafer1is set to −2500 V, the potential V2of the HV electrode21is set to +2500 V, and the potential V3of the ESC base23is set to −2500 V.

Next, the potential V1of the wafer1is changed when the second hard mask layer3bis removed during the processing of the process target layer2within the opening5(step S2). The measurement module16of the present embodiment measures the potential V1of the wafer1and outputs the result of measurement of the potential V1to the controller17. Consequently, the controller17detects that the potential V1of the wafer1has changed from −2500 V to −3500 V. The value “−2500 V” of the potential V1is an example of a first value. The value “−3500 V” of the potential V1is an example of a second value.

Next, the controller17adjusts the potential V3of the ESC base23to the same value as the potential V1(step S3). As a result, the potential V3of the ESC base23is changed from −2500 V to −3500 V. Consequently, the potentials of the wafer1and the ESC base23can be equalized once again.

Next, the controller17adjusts the potential V2of the HV electrode21so that the potential difference V2−V1becomes constant (step S4). As a result, the potential V2of the HV electrode21is changed from +2500 V to +1500 V. The value “+2500 V” of the potential V2is an example of a third value. The value “+1500 V” of the potential V2is an example of a fourth value. Consequently, it is possible to prevent an increase in the current I2flowing through the HV electrode21.

Thereafter, the potential V1of the wafer1changes from −3500 V back to −2500 V. The controller17also changes the potential V3of the ESC base23from −3500 V back to −2500 V when a certain period of time elapses from when the potential V1has changed back to −2500 V. On the other hand, the controller17maintains the potential V2of the HV electrode21at the adjusted value “+1500 V” even if a certain period of time elapses from when the potential V1has changed back to −2500 V (step S5). The reason for this is that any large spike current I2is less likely to arise in the HV electrode21and the adsorption of the wafer1can be maintained, even if the potential V2is not changed back to the unadjusted value. A modified example of step S5will be described in a second embodiment.

As described above, the controller17of the present embodiment adjusts the potential V3of the ESC base23based on the potential V1of the wafer1and adjusts the potential V2of the HV electrode21based on the potential V1of the wafer1or the potential V3of the ESC base23, when the potential V1of the wafer1measured by the measurement module16changes. Specifically, the controller17of the present embodiment adjusts the potential V3of the ESC base23to the same value as the potential V1, and adjusts the potential V2of the HV electrode21so that the potential difference V2−V1(=V2−V3) becomes constant. Consequently, according to the present embodiment, it is possible to suppress the current I2flowing through the HV electrode21.

Potential adjustments in the present embodiment can also be applied to wafers other than the wafer1in which the process target layer2, the first hard mask layer3a, the second hard mask layer3band the resist layer4are arranged. For example, the potential adjustments in the present embodiment can be applied to various cases where a spike current may arise due to a change in the impedance of layers on a wafer.

Although the potential difference V2−V1between the wafer1and the HV electrode21is set to 1000 V or larger in the present embodiment, the lower limit 1000 V may be replaced with other values. For example, the lower limit of the potential difference V2−V1may be set to a value dependent on the pressure of a coolant supplied from the coolant feeder15, since the potential difference V2−V1necessary to adsorb the wafer1may change depending on the pressure of the coolant.

In addition, the potential V3of the ESC base23may be adjusted to a value different from the potential V1, instead of being adjusted to the same value as the potential V1. For example, adjusting the potential V3to a value close to the potential V1makes it possible to obtain the same effect as in the case of adjusting the potential V3to the same value as the potential V1.

Additionally, the potential V2of the HV electrode21may be adjusted so that the potential difference V2−V1does not become constant, as long as the current I2of the HV electrode21can be controlled to less than the threshold. The potential V2may be adjusted so that the current I2does not change or changes to a value less than the threshold.

Second Embodiment

FIG. 5is a flowchart illustrating a method of operating a semiconductor manufacturing apparatus of a second embodiment.

The structure of the semiconductor manufacturing apparatus of the present embodiment is the same as that of the semiconductor manufacturing apparatus of the first embodiment illustrated inFIG. 1. In addition, steps S1to S4shown inFIG. 5are executed in the same way as steps S1to S4shown inFIG. 4.

In step S5shown inFIG. 4, the controller17changes the potential V3of the ESC base23from −3500 V back to −2500 V when a certain period of time elapses from when the potential V1has changed back to −2500 V. However, the controller17maintains the potential V2of the HV electrode21at the adjusted value (i.e., value after adjustment) “+1500 V”.

On the other hand, in step S5shown inFIG. 5, the controller17changes the potential V3of the ESC base23from −3500 V back to −2500 V when a certain period of time elapses from when the potential V1has changed back to −2500 V, and changes the potential V2of the HV electrode21back to the unadjusted value (i.e., value before adjustment) “+2500 V”. When the potential V2of the HV electrode21is to be changed back, the controller17preferably slowly changes back the potential V2so that the current I2of the HV electrode21does not exceed the threshold.

The ESC12of the present embodiment can adsorb the wafer1by setting the potential difference V2−V1between the wafer1and the HV electrode21to 1000 V or larger. If the potential difference V2−V1is too small, the ESC12fails to adsorb the wafer12. On the other hand, too large a potential difference V2−V1causes the problem of electrical discharge taking place in the wafer1. Accordingly, the potential difference V2−V1is preferably maintained at an appropriate setpoint. An example of such a setpoint is 5000 V.

According to step S5in the present embodiment, the potential difference V2−V1can be maintained at 5000 V by changing the potential V2of the HV electrode21back to +2500 V. On the other hand, according to step S5in the first embodiment, the step of changing the potential V2of the HV electrode21back to +2500 V can be omitted to simplify step S5.