Mesa type semiconductor device and manufacturing method thereof

Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N− type semiconductor layer and the thermal oxide film. With the structure described above, an influence of the positive electric charges in the thermal oxide film is weakened and an extension of a depletion layer into the N− type semiconductor layer at the interface with the thermal oxide film is secured.

CROSS-REFERENCE OF THE INVENTION

This application claims priority from Japanese Patent Application No. 2008-153850, the content of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor device having a mesa groove and its manufacturing method. In this application, the semiconductor device having a mesa groove is named as a mesa type semiconductor device.

2. Description of the Related Art

A mesa type power diode has been known as one of the mesa type semiconductor devices. A mesa type diode according to a prior art is described referring toFIGS. 8 and 9.FIG. 8is an outline plan view showing a semiconductor wafer in which a plurality of the mesa type diodes according to the prior art is arrayed in a matrix form.FIG. 9is a cross-sectional view of a section X-X inFIG. 8, showing the wafer after being diced along scribe lines DL.

An N−type semiconductor layer102is formed on a surface of an N+type semiconductor substrate101. A first insulation film105is formed on a P type semiconductor layer103that is formed on a surface of the N−type semiconductor layer102. There is formed an anode electrode106that is electrically connected with the P type semiconductor layer103.

Also, there is formed a mesa groove108that extends from a surface of the P type semiconductor layer103to the N+type semiconductor substrate101. The mesa groove108penetrates through the N−type semiconductor layer102, and its bottom is located inside the N+type semiconductor substrate101. Sidewalls of the mesa groove108are tapered down from the surface of the P type semiconductor layer103to the bottom of the mesa groove108to have a normal tapered shape. The mesa type diode is surrounded by the mesa groove108to have a mesa type structure.

A second insulation film130made of a polyimide film is formed to cover the sidewalls of the mesa groove108, and a cathode electrode107is formed on a back surface of the N+type semiconductor substrate101.

The mesa type semiconductor device is described in Japanese Patent Application Publication No. 2003-347306, for example.

The second insulation film130in the conventional mesa type diode is shown inFIG. 9to cover inner walls of the mesa groove108with a uniform thickness. In reality, however, the second insulation film130is thinner at upper portions of the inner walls of the mesa groove108and accumulates thicker at the bottom of the mesa groove108, as shown inFIG. 11. The shape as described above is formed in following process steps. When the second insulation film130is provided into the mesa groove108by dispensing or the like, the mesa groove108is filled with the second insulation film130, as shown inFIG. 10. Imidization reaction takes place during subsequent thermal treatment, and because of increased fluidity of the second insulation film130, the second insulation film130as a whole flows toward the bottom of the mesa groove108to reduce the thickness of the second insulation film130at the upper portions of the inner walls of the mesa groove108, as shown inFIG. 11.

As a result, the thickness of the second insulation film130is reduced at a mesa groove-side sidewall110corresponding to a PN junction PNJC where an electric field is most intense, causing serious problems to be solved such as deterioration in a withstand voltage of the PN junction and increase in a leakage current to reduce yield and reliability. As a method to solve the problems, it is conceivable that the second insulation film is formed repeatedly. However, this method increases a cost of the semiconductor device because a material of the second insulation film is expensive.

SUMMARY OF THE INVENTION

The invention provides a method of manufacturing a mesa type semiconductor device. The method includes providing a semiconductor substrate of a first general conductivity type, and forming a first semiconductor layer of the first general conductivity type on the semiconductor substrate. The impurity concentration of the first semiconductor layer is lower than the impurity concentration of the semiconductor substrate. The method further includes forming a second semiconductor layer of a second general conductivity type on the first semiconductor layer, forming a mask on the second semiconductor layer, etching the second semiconductor layer, the first semiconductor layer and the semiconductor substrate using the mask so as to form a groove so that the semiconductor substrate is exposed at a bottom of the groove, forming an oxide film in the groove and on a top surface of the second semiconductor layer, and forming an organic insulation film in the groove so as to cover the oxide film. When the width of the groove is small, the formation of the organic insulation film may be omitted.

The invention also provides a mesa type semiconductor device that includes a semiconductor substrate of a first general conductivity type and a first semiconductor layer of the first general conductivity type disposed on the semiconductor substrate. The impurity concentration of the first semiconductor layer is lower than the impurity concentration of the semiconductor substrate. The device further includes a second semiconductor layer of a second general conductivity type disposed on the first semiconductor layer so as to form a PN junction between the first and second semiconductor layers, a mesa groove penetrating into the semiconductor substrate through the first and second semiconductor layers, an oxide film disposed on the second semiconductor layer and in the mesa groove, and an organic insulation film disposed in the mesa groove so as to cover the oxide film at the PN junction. When the width of the mesa groove is small, the organic insulation film may be omitted.

DETAILED DESCRIPTION OF THE INVENTION

A mesa type semiconductor device and its manufacturing method according to an embodiment of this invention are described taking an example in which the mesa type semiconductor device is represented as a mesa type diode.FIGS. 1 through 5are cross-sectional views showing the mesa type diode and its manufacturing method according to the embodiment. It is noted that drawings used in the following explanation on the manufacturing method of the mesa type diode show only one mesa type diode out of a plurality of mesa type diodes for the sake of simplicity, although the manufacturing method is applied to a semiconductor substrate in a wafer form in which the plurality of mesa type diodes is arrayed in a matrix form.

There is provided an N+type semiconductor substrate1(a single crystalline silicon substrate, for example) that is doped with high concentration N type impurities such as phosphorus, as shown inFIG. 1. An N−type semiconductor layer2, that is an N type semiconductor layer with a low impurity concentration, is formed on a surface of the N+type semiconductor substrate1by epitaxial growth. A double layer structure made of the N+type semiconductor substrate1and the N−type semiconductor layer2may be formed by thermally diffusing impurities such as phosphorus to form N+type semiconductor layers in surfaces on both sides of an N−type semiconductor substrate and by subsequent chemical etching or mechanical polishing to remove one of the N+type semiconductor layers. Particularly in manufacturing an ultra high withstand voltage product which requires the N−type semiconductor layer2being thick, there are cases where the diffusion method is preferable to the epitaxial method.

After that, a P type semiconductor layer3is formed in a surface of the N−type semiconductor layer2by diffusing P type impurities such as boron. As a result, a PN junction PNJC is formed at an interface between the N−type semiconductor layer2and the P type semiconductor layer3. In the structure described above, a thickness of stacked layers of the N+type semiconductor substrate1, the N−type semiconductor layer2and the P type semiconductor layer3is approximately 200 μm, for example. It is noted that conductivity types such as N+, N and N−belong in one general conductivity type and conductivity types such as P+, P and P−belong in another general conductivity type.

Next, a photoresist layer4having openings4A in regions where mesa grooves5are to be formed is formed on the P type semiconductor layer3, as shown inFIG. 2. The mesa grooves5are formed by dry-etching all the way through the P type semiconductor layer3and the N−type semiconductor layer2and partway through a thickness of the N+type semiconductor substrate1using the photoresist layer4as a mask. After that, a damage layer caused by the dry-etching on a sidewall of the mesa groove5is removed using an etching solution including hydrofluoric acid or nitric acid. After the etching, the photoresist layer4used as the mask is removed by an ashing method or with a resist removing solution.

Next, a thermal oxide film6of a thickness of several micrometers or less is formed on the sidewall of the mesa groove5, on the P type semiconductor layer3and on the N+type semiconductor substrate1in an atmosphere of dry O2or wet O2in a high-temperature furnace, as shown inFIG. 3. The problem that the withstand voltage would not be secured due to a reduced thickness of a film covering a sidewall11of the mesa groove5, which corresponds to the PN junction PNJC, when the mesa groove5would be filled with polyimide or the like is easily solved, since the sidewall11of the mesa groove5is covered and protected by the thermal oxide film6that is thick enough to secure the withstand voltage. However, the mesa groove5is not completely filled with the thermal oxide film6and a ditch surrounded by the thermal oxide film6is formed in the mesa groove5, since a width of the mesa groove5in this embodiment is larger than 10 μm.

With some of the mesa type diodes having the mesa groove5covered with the thermal oxide film6, there is found a problem as with a planar type high voltage NPN transistor that a dielectric breakdown is caused at a surface so that the withstand voltage does not reach a withstand voltage determined by a bulk resistivity, because an electron accumulation layer is formed in the N−type semiconductor layer2, which makes a collector layer, at an interface with the oxide film and a depletion layer does not extend sufficiently. In the case of the planar type transistor, this problem is solved by forming several P+guard rings diffused from the surface of the collector. Providing the mesa type diode with the P+guard rings in the mesa groove5deprives the mesa type diode of the advantage of a reduced manufacturing cost compared with the planar type device.

Thus, an insulation film7is formed in the ditch surrounded by the thermal oxide film6in the mesa groove5and on the thermal oxide film6above the P type semiconductor layer3excluding a region where an anode electrode8is to be formed, as shown inFIG. 4. When the insulation film7is made of an epoxy resin, for example, the epoxy resin gets into the ditch surrounded by the thermal oxide film6, that is of hydrophilic, more easily than into the mesa groove5in which a silicon surface, that is of hydrophobic, is directly exposed. In the case where the semiconductor is silicon, positive ions due to excess silicon are caused in the thermal oxide film6at the interface with the N−type semiconductor layer2during the thermal oxidation, while interface states due to dangling bonds existing at the interface between silicon and the oxide film are caused as well. As a result, the thermal oxide film6as a whole is charged with positive electric charges to some extent. If nothing is done, electrons are accumulated in the N−type semiconductor layer2at the interface with the thermal oxide film6to cause reduction in the withstand voltage.

In order to cancel out the positive electric charges, the epoxy resin or the like, that has negative electric charges and is of low-cost, can be selected as the material to form the insulation film7on the thermal oxide film6. Since the insulation film7is formed over the N−type semiconductor layer2and others through the thermal oxide film6, the negative electric charges in the insulation film7serve to weaken the effect of the positive electric charges in the thermal oxide film6on the N−type semiconductor layer2, rather than directly affecting the N−type semiconductor layer2and the others. Even if an amount of the negative electric charges in the insulation film7increases to cancel out all the positive electric charges in the thermal oxide film6and further to leave net negative electric charges over the N−type semiconductor layer2, there is no problem unless the N−type semiconductor layer2in the mesa groove5at the interface with the thermal oxide film6is inverted to a P type.

As a result, the dielectric breakdown at the sidewall11of the mesa groove5occurs less likely so that the withstand voltage becomes closer to the value determined by the bulk resistivity, since the accumulation of electrons in the N−type semiconductor layer2due to the positive electric charges in the thermal oxide film6at the interface between the N−type semiconductor layer2and the thermal oxide film6is reduced and the depletion layer extends more easily. Also, there can be avoided the problems of the leakage current and the like that would be caused by a P type inversion layer at an interface between the N−type semiconductor layer2and the insulation film7if the insulation film7made of epoxy resin having the negative electric charges would be formed immediately upon the sidewall of the mesa groove5.

Although the insulation film7is formed not only in the mesa groove5but also in other locations in the mesa type semiconductor device according to the embodiment, the effects described above can be obtained as long as the sidewall11of the mesa groove5corresponding to the PN junction PNJC and below are covered with the insulation film7. In the case where the mesa groove5is not completely filled with the insulation film7, however, chemical solution used in forming the anode electrode8might be left in the mesa groove5to cause a reliability problem, or unevenness15might be caused in a photoresist layer14on a semiconductor wafer16as shown inFIG. 7to reduce the yield. Therefore, it is preferable that the mesa groove5is completely filled with the insulation film7.

A so-called permanent resist such as an organic resist film, a polyimide film, an inorganic or organic SOG (Spin On Glass) film, a silicon nitride film or the like may be used as the insulation film7.

Finally, an opening6A for a connection between the P type semiconductor layer3and the anode electrode8, that is to be described, is formed in the thermal oxide film6through a predetermined photolithography process, as shown inFIG. 5. The thermal oxide film6formed on the N+type semiconductor substrate1is also removed in the process. After that, a conductive material such as aluminum is formed on the P type semiconductor layer3by a sputtering method or by a vapor deposition method and the anode electrode8is formed through a predetermined process, while a cathode electrode9is formed on the N+type semiconductor substrate1similarly. Forming the electrodes as described above completes the mesa type diode having the mesa groove5filled with the thermal oxide film6that is simple and stable and the insulation film7that is made of inexpensive epoxy resin or the like.

When necessary, a passivation film10made of a silicon nitride film and having an opening8A above the anode electrode8is formed by plasma CVD as shown inFIG. 6to improve the reliability. In the case where the objective is realized by filling only the mesa groove5with the insulation film7as described above, forming a width of the passivation film10slightly larger than the width of the mesa groove5prevents the negative electric charges in the insulation film7from varying so that the mesa type diode of high reliability is realized.

Mesa type diodes according to other embodiments of this invention are hereafter described referring toFIGS. 12A and 12B. A feature of the mesa type diodes according to the other embodiments is that the mesa groove5is filled with an oxide film or oxide films only.

A structure shown inFIG. 12Ais different from the structure shown inFIG. 6in that the mesa groove5is completely filled with the thermal oxide film6and an oxide film12A formed by CVD and the insulation film7is formed on them. Other features are the same as the structure shown inFIG. 6.

A structure shown inFIG. 12Bdiffers from the structure shown inFIG. 6in that the mesa groove5is completely filled only with an oxide film12B formed by CVD and the insulation film7is formed on it. Other features are the same as the structure shown inFIG. 6.

Although the mesa groove5in the semiconductor device according to the embodiment is described to be about 100 μm deep and about 10 μm wide, for example, the depth and the width of the mesa groove5may be varied variously, and a structure of the oxide film formed in the mesa groove5may be varied depending on the various depth and width. When the oxide film is formed in a mesa groove of a width smaller than the width described in the embodiment, it becomes possible that the mesa groove5is completely filled only with the thermal oxide film instead of the oxide film12B shown inFIG. 12Bto further simplify the manufacturing process. For example, the mesa groove5can be filled only with the thermal oxide film when the width is 5 μm or less. In this case, a growth rate of the thermal oxide film6may be reduced to reduce the positive electric charges due to the excess silicon in the oxide film and hydrogen annealing or the like is adopted when necessary to reduce the dangling bonds caused at the interface between the N−type semiconductor layer2and the thermal oxide film6to reduce the positive electric charges in the thermal oxide film6so that the mesa type diode is securely provided with the feature of the low leakage current and the ultra high withstand voltage.

This invention may be applied not only to the mesa type diode which is described above, but also to other mesa type semiconductor devices such as a mesa type transistor.

With the mesa type semiconductor device and its manufacturing method according to the embodiment of this invention, the withstand voltage of the PN junction can be improved while the leakage current is reduced with the inexpensive material.