SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric fin disposed between the first and second semiconductor fins, wherein the dielectric fin also extends along the first direction. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction, the gate structure comprising a first portion and a second portion. A top surface of the dielectric fin is vertically above respective top surfaces of the first and second semiconductor fins. The first portion and the second portion are electrically isolated by the dielectric fin. The first portion of the gate structure overlays an edge portion of the first semiconductor fin, and the second portion of the gate structure overlays a non-edge portion of the second semiconductor fin.

BACKGROUND

The present disclosure generally relates to semiconductor devices, and particularly to methods of making a non-planar transistor device.

DETAILED DESCRIPTION

An integrated circuit typically includes a large number of devices (e.g., transistors). To fabricate these devices, a number of (e.g., planar and/or non-planar) active regions and a number of gate structures that intersect the active regions can be formed on a substrate or wafer to define such devices. To further configure those device to operate as certain circuits, some of the devices can be operatively connected to or disconnected from each other. For example, a gate structure can be cut or otherwise disconnected following the formation of a corresponding dummy gate structure or following the formation of the gate structure. Given the large number of transistors formed on the substrate, the number of gate structures to be cut may increase accordingly, which sometimes causes issues. For example, when the number of to-be-cut gate structures increases above a threshold (e.g., 4 gate structures), a discrepancy of profiles and dimensions among those gate structures can occur, which can cause one or more of the gate structures to be undesirably connected to a source/drain region or a corresponding contact.

Embodiments of the present disclosure are discussed in the context of forming non-planar devices (e.g., FinFET devices), and in particular, in the context of forming one or more isolation structures (e.g., dummy fin structures) between some of the devices. Different from the existing technologies, the dummy fin structures may each be formed between adjacent active regions (sometimes referred to as active fin structures, or active channels), prior to the formation of (e.g., either dummy or active) gate structures. Further, the dummy fin structures may be formed higher than the active fin structures. In some embodiments, the dummy fin structures may have a top surface coplanar with a top surface of the later formed gate structures. As such, some of the gate structures can be “spontaneously” cut or disconnected into different portions, upon being formed. By using the method, as disclosed herein, even though the number of gate structures to be cut is large, the above-identified discrepancy issues, which typically results from different etching conditions (e.g., different etching rates), can be avantageously avoided.

Further, in advanced technology nodes, some of the active fin structures may be cut or otherwise disconnected for facilitating the overall design of an integrated circuit. As such, a portion of some of the gate structures, in addition to overlaying a top surface of the cut active fin structure, may extend along an edge of the cut active fin structure. Such a portion of the gate structure that extends along the edge of a cut active fin structure may sometimes be referred to as a poly-oxide diffusion-edge (PODE), and the portion of the gate structure that does not extend along the edge of a cut active fin structure may sometimes be referred to as a non-poly-oxide diffusion-edge (non-PODE). In the existing technologies, it is typically selected not to cut such PODE and non-PODE, as the above-identified gate-contact short issue may occur. This can disadvantageously constrain flexibility of the overall design. Using the disclosed method to spontaneously cut the PODE and non-PODE, however, can avoid the issue.

FIG.1Aillustrates a top view of an example semiconductor device100that includes the disclosed dummy fin structure separating a PODE and a non-PODE, in accordance with various embodiments. As shown, the semiconductor device100includes: active regions102and104that extend along a first lateral direction (e.g., the X direction); dummy regions112,114, and116that also extend along the X direction; and a gate structure120that extends along a second lateral direction (e.g., the Y direction).

The active regions102-104and gate structures120can define one or more planar or non-planar transistors. For example, the semiconductor device100can include a number of FinFETs. It should be understood that the semiconductor device can include any of various other transistors (e.g., gate-all-around (GAA) transistors, nanosheet transistors, nanowire transistors, etc.), while remaining within the scope of the present disclosure.

When the transistors are implemented as FinFETs, each of the active regions102-104is formed as a three-dimensional fin structure protruding from a substrate. Accordingly, the active regions102-104may sometimes be referred to as active fin structures102-104, respectively. Similarly, each of the dummy regions112-116is formed as a three-dimensional fin structure protruding from a substrate. Accordingly, the dummy regions112-116may sometimes be referred to as dummy fin structures112-116, respectively. In some embodiments, the dummy fin structures112-116are each formed to upwardly extend higher than the active fin structures102-104. Further, adjacent active fin structures102-104are separated by one of the dummy fin structures112-116.

The gate structure120, which may be a metal gate structure (sometimes referred to as an active gate structure), is formed to straddle the active fin structures102-104. Further, the gate structure120can either straddle or be cut by the dummy fin structures. For example, the gate structure120straddles the active fin structures102-104and the dummy fin structure112, and is cut by the dummy fin structures114and116. As shown inFIG.1A, the gate structure120is cut (by the dummy fin structures114and116, respectively) into three separate portions,120-1,120-2, and120-3. In some embodiments, one or more of the active fin structures can be cut or disconnected. For example, the active fin structure104may be cut around the gate structure120. Accordingly, in addition to straddling the active fin structure104(like other portions of the gate structure120), the portion120-2can further extend along an edge of such a cut active fin structure104. Based on the above definition, the portions120-1,120-2, and120-3may sometimes be referred to as non-PODE120-1, PODE120-2, and non-PODE120-3, respectively.

Each of the active regions102-104can be configured to form one or more channels and one or more source/drain structures. For example, a channel132, straddled by the non-PODE120-1, can be formed in the active fin structure102; and source/drain structures134and136, not straddled by any gate structure or gate structure portion, can be formed in the active fin structure102on opposite sides of the channel132. In another example, even though an edge portion of the active fin structure104is straddled by the portion120-2, which is a PODE, this edge portion may not function as a channel. However, a source/drain structure138, not straddled by any gate structure or gate structure portion, can be formed in the active fin structure104on a side of the PODE120-2.

For purposes of clarification,FIG.1Billustrates a perspective view of a portion (e.g.,101) of the example semiconductor device100shown inFIG.1A, in accordance with various embodiments. As shown, the dummy fin structure114that separates the non-PODE120-1and PODE120-2is formed on a shallow trench isolation (STI) structure150. To separate the non-PODE120-1and PODE120-2, the dummy fin structure114, upon being formed, may be formed to have a same or similar height as (e.g., dummy) gate structure portions that are replaced with respective portions of the active gate structure120, in some embodiments. Further, the semiconductor device100includes an interlayer dielectric (ILD)152formed on sides of the dummy fin structure114where no active gate structure is formed, which will be discussed in further detail below.

FIG.1A(andFIG.1B) are provided as a reference to illustrate a number of cross-sections in subsequent figures. For example, cross-section B-B extends along a longitudinal axis of the gate structure120; cross-section A-A extends in parallel with cross-section B-B and crosses the source/drain structure136; and cross-section C-C is perpendicular to cross-section A-A/B-B and is along a longitudinal axis of the active fin structure104. Subsequent figures refer to these reference cross-sections for clarity.

FIG.2illustrates a flowchart of a method200to form a non-planar transistor device, according to one or more embodiments of the present disclosure. For example, at least some of the operations (or steps) of the method200can be used to form a FinFET device (e.g., semiconductor device100). However, it should be understood that the method200can be used to form a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, a gate-all-around (GAA) transistor device, or the like, while remaining within the scope of the present disclosure. It is noted that the method200is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method200ofFIG.2, and that some other operations may only be briefly described herein. In some embodiments, operations of the method200may be associated with cross-sectional views of an example FinFET device at various fabrication stages as shown inFIGS.3,4,5,6,7,8A,8B,9A,9B,9C,10,11,12,13,14,15A, and15B, respectively, which will be discussed in further detail below.

In brief overview, the method200starts with operation202of providing a substrate. The method200continues to operation204of forming a number of active fins. The method200continues to operation206of cutting one or more of the active fins. The method200continues to operation208of forming an isolation structure. The method200continues to operation210of forming a number of dummy fins. The method200continues to operation212of forming a dummy gate structure over the active fins. The method200continues to operation214of forming a gate spacer. The method200continues to operation216of growing source/drain structures. The method200continues to operation218of forming an interlayer dielectric (ILD). The method200continues to operation220of recessing one or more of the dummy fins. The method200continues to operation222of forming an active gate structure.

Corresponding to operation202ofFIG.2,FIG.3is a cross-sectional view of the FinFET device300including a semiconductor substrate302at one of the various stages of fabrication. The cross-sectional view ofFIG.3is cut along the lengthwise direction of an active/dummy gate structure of the FinFET device300(e.g., cross-section B-B indicated inFIGS.1A-B).

Corresponding to operation204ofFIG.2,FIG.4is a cross-sectional view of the FinFET device300including semiconductor fins402and404at one of the various stages of fabrication. The cross-sectional view ofFIG.4is cut along the lengthwise direction of an active/dummy gate structure of the FinFET device300(e.g., cross-section B-B indicated inFIGS.1A-B). In some embodiments, the semiconductor fins402and404may correspond to the active regions102and104shown inFIG.1A, respectively.

The semiconductor fins402-404may be each configured as an active fin (structure), which will be adopted as an active (e.g., electrically functional) fin or channel in a respective completed FinFET. Hereinafter, the semiconductor fins402and404may sometimes be referred to as “active fins402and404,” respectively. Although two semiconductor fins are shown in the illustrated example, it should be appreciated that the FinFET device300can include any number of semiconductor fins while remaining within the scope of the present disclosure.

The semiconductor fins402-404are formed by patterning the substrate302using, for example, photolithography and etching techniques. For example, a mask layer, such as a pad oxide layer406and an overlying pad nitride layer408, is formed over the substrate302. The pad oxide layer406may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer406may act as an adhesion layer between the substrate302and the overlying pad nitride layer408. In some embodiments, the pad nitride layer408is formed of silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. Although only one pad nitride layer408is illustrated, a multilayer structure (e.g., a layer of silicon oxide on a layer of silicon nitride) may be formed as the pad nitride layer408. The pad nitride layer408may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), for example.

The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. For example, the photoresist material is used to pattern the pad oxide layer406and pad nitride layer408to form a patterned mask410, as illustrated inFIG.4.

The patterned mask410is subsequently used to pattern exposed portions of the substrate302to form trenches (or openings)411, thereby defining the active fins402-404between adjacent trenches411as illustrated inFIG.4. When multiple fins are formed, such a trench may be disposed between any adjacent ones of the fins. In some embodiments, the active fins402-404are formed by etching trenches in the substrate302using, for example, reactive ion etch (RIE), neutral beam etch (NBE), the like, or combinations thereof. The etch may be anisotropic. In some embodiments, the trenches411may be strips (viewed from the top) parallel to each other, and closely spaced with respect to each other. In some embodiments, the trenches411may be continuous and surround the active fins402-404.

FIGS.3and4illustrate an embodiment of forming the active fins402-404, but a fin may be formed in various different processes. For example, a top portion of the substrate302may be replaced by a suitable material, such as an epitaxial material suitable for an intended type (e.g., N-type or P-type) of semiconductor devices to be formed. Thereafter, the substrate302, with epitaxial material on top, is patterned to form the active fins402-404that include the epitaxial material.

As another example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form one or more fins.

In yet another example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the substrate; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form one or more fins.

In embodiments where epitaxial material(s) or epitaxial structures (e.g., the heteroepitaxial structures or the homoepitaxial structures) are grown, the grown material(s) or structures may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material in an NMOS region different from the material in a PMOS region. In various embodiments, the active fins402-404may include silicon germanium (SixGe1-x, where x can be between 0 and 1), silicon carbide, pure silicon, pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Corresponding to operation206ofFIG.2,FIG.5is a cross-sectional views of the FinFET device300in which one of the active fins404is cut or otherwise discontinued at one of the various stages of fabrication. The cross-sectional view ofFIG.5is cut along a direction in parallel with the lengthwise direction of an active/dummy gate structure of the FinFET device300(e.g., cross-section A-A indicated inFIGS.1A-B).

An etching process501may be performed to remove a portion of the active fin404, which is enclosed by a dotted line inFIG.5. Such a removed portion of the active fin404can be referenced to the top view ofFIG.1A, e.g., the portion of the active region104on the right-hand side of the gate structure120. This cut active fin404(i.e., with one or more of its portions removed) can be better appreciated in the following figures that are cut along cross-section C-C. In accordance with various embodiments, the etching process501can remove the portion of the active fin404, while covering the active fin402. Thus, the active fin402may remain substantially intact, e.g., continuously extending from one point to the other point on the substrate302. By contrast, the active fin404, which may continuously extend between the same points as the active fin402(upon being formed in operation204), may be cut into a number of discontinuous portions, one of which is shown inFIG.1A.

For example, the etching process501can include a plasma etching process. In such a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes), gas sources such as chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen (H2), nitrogen trifluoride (NF3), and other suitable gas sources and combinations thereof can be used with passivation gases such as nitrogen (N2), oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as argon (Ar), helium (He), neon (Ne), and other suitable dilutive gases and combinations thereof.

Corresponding to operation208ofFIG.2,FIG.6is a cross-sectional view of the FinFET device300including an isolation region/structure600at one of the various stages of fabrication. The cross-sectional view ofFIG.6is cut along the lengthwise direction of an active/dummy gate structure of the FinFET device300(e.g., cross-section B-B indicated inFIGS.1A-B). It is noted thatFIG.6(and the following cross-sectional views) is not cut along cross-section A-A, so that the cut active fin404(i.e., the remaining portions of the active fin404) is still visible.

The isolation structure600, which is formed of an insulation material, can electrically isolate neighboring fins from each other. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or combinations thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or combinations thereof. Other insulation materials and/or other formation processes may be used. In an example, the insulation material is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. A planarization process, such as a chemical mechanical polish (CMP), may remove any excess insulation material and form top surfaces of the isolation structure600and a top surface of the fins402-404that are coplanar (not shown). The patterned mask410(FIG.4) may also be removed by the planarization process.

In some embodiments, the isolation structure600includes a liner, e.g., a liner oxide (not shown), at the interface between the isolation structure600and the substrate302(active fins402-404). In some embodiments, the liner oxide is formed to reduce crystalline defects at the interface between the substrate302and the isolation structure600. Similarly, the liner oxide may also be used to reduce crystalline defects at the interface between the active fins402-404and the isolation structure600. The liner oxide (e.g., silicon oxide) may be a thermal oxide formed through a thermal oxidation of a surface layer of the substrate302, although other suitable method may also be used to form the liner oxide.

Next, the isolation structure600is recessed to form shallow trench isolations (STIs)600, as shown inFIG.6. The isolation structure600is recessed such that the upper portions of the active fins402-404protrude from between neighboring STIs600. Respective top surfaces of the STIs600may have a flat surface (as illustrated), a convex surface, a concave surface (such as dishing), or combinations thereof. The top surfaces of the STIs600may be formed flat, convex, and/or concave by an appropriate etch. The isolation structure600may be recessed using an acceptable etching process, such as one that is selective to the material of the isolation structure600. For example, a dry etch or a wet etch using dilute hydrofluoric (DHF) acid may be performed to recess the isolation structure600.

Corresponding to operation210ofFIG.2,FIG.7is a cross-sectional views of the FinFET device300including dummy fins (structures)712,714, and716at one of the various stages of fabrication. The cross-sectional view ofFIG.7is cut along the lengthwise direction of an active/dummy gate structure of the FinFET device300(e.g., cross-section B-B indicated inFIG.1). In some embodiments, the dummy fins712,714, and716may correspond to the dummy fins112,114, and116shown inFIG.1A, respectively.

In advanced processing nodes, such a dummy fin can be disposed next to one or more active fins (e.g., between two adjacent active fins) to improve the overall design and fabrication of a semiconductor device. For example, dummy fins can be used for optical proximity correction (OPC) to enhance a pattern density and pattern uniformity in the stage of designing the semiconductor device. In another example, adding dummy fins adjacent to active fins can improve chemical-mechanical polishing (CMP) performance when fabricating the semiconductor device. The dummy fin is designed to stay inactive or electrically non-functional, when the semiconductor device is appropriately configured and powered.

The dummy fins712-716may be formed concurrently with or subsequently to the formation of the isolation structure600. As an example, after cutting the active fin404(FIG.5), the insulation material of the isolation structure600may be deposited over the active fins402-404in a controlled deposition rate, thereby causing cavities to be spontaneously formed in the trenches411. The cavities are then filled with a dielectric material of the dummy fin712-716(using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), for example), followed by a CMP process to form the dummy fins712-716. The dielectric material, for example, may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, or combinations thereof. In another example, the dielectric material may include group IV-based oxide or group IV-based nitride, e.g., tantalum nitride, tantalum oxide, hafnium oxide, or combinations thereof. The insulation material (of the isolation structure600) is then recessed to form the STIs600. Using such a method to form the dummy fins712-716, the dummy fins712-716are formed over the isolation structure600, as shown inFIG.7.

As another example, after depositing the insulation material of the isolation structure600over the active fins402-404, a patterned mask may be formed over the isolation structure600to expose portions of the isolation structure600to form the dummy fins712-716(e.g., in the trenches411). Subsequently, the exposed portions of the isolation structure600may be etched using, for example, reactive ion etch (ME), neutral beam etch (NBE), the like, or combinations thereof, thereby defining cavities. The cavities are then filled with the dielectric material of the dummy fins (as described above), followed by a CMP process to form the dummy fins712-716. The insulation material (of the isolation structure600) is then recessed to form the STIs600. As such, the dummy fins712-716are formed over the isolation structure600, as shown inFIG.7.

In accordance with various embodiments, the dummy fins712-716is formed to have a height, H1, greater than a height of the active fins402-404, H2, both of which are measured from the top surface of the STIs600, as shown inFIG.7. Alternatively stated, the dummy fins712-716may outwardly extend from the substrate302farther than the active fins402-404. As a non-limiting example, H1may range between about 10 nm and about 200 nm, and H2may range between about 5 nm and about 150 nm. Further, the dummy fins712-716may each have a width, W, which can range between about 2 nm and 500 nm, for example. In some embodiments, the height (H1) of the dummy fins712-716may be similar as the height of a dummy gate structure, which will be discussed below. Forming such a higher dummy fins, the dummy gate structure can be spontaneously divided or otherwise separated into a number of different portions. The higher dummy fins712-716can be formed by performing a selective etching process on the active fins402-404. For example, following the CMP process (to form the dummy fins712-716), an etching process selective to remove the active fins more than the dummy fins (using etchants such as, for example, Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, NF3) is performed.

By forming the dummy fins using the above-described method(s), the dummy fins712-716may each contain a continuously formed one-piece structure. For example, each of the dummy fins712-716is formed as a one-piece structure protruding from the substrate302or STI600. In some other embodiments, the dummy fins712-716may be formed concurrently with or subsequently to the formation of a dummy gate structure, which will be discussed as follows. When forming the dummy fins712-716in this way, each of the dummy fins712-716can include a number of dielectric structures relatively arranged to each other. These dummy fins that include a number of pieces of dielectric structures will be discussed in further detail below.

Corresponding to operation212ofFIG.2,FIG.8Ais a cross-sectional view of the FinFET device300including a dummy gate structure800at one of the various stages of fabrication. The cross-sectional view ofFIG.8Ais cut along the lengthwise direction of the dummy gate structure800(e.g., cross-section B-B indicated inFIGS.1A-B). Corresponding to the same operation,FIG.8Billustrates another cross-sectional view of the FinFET device300cut along a lengthwise direction of the cut active fin404(e.g., cross-section C-C indicated inFIG.1A). In some embodiments, the dummy gate structure800may correspond to a footprint where the gate structure120(as shown inFIGS.1A-B) is formed.

In various embodiments, the dummy gate structure800may be formed with a similar height as the dummy fins712-716. Consequently, the dummy gate structure800is cut into a number of different portions (along its lengthwise direction). These different portions may be respectively separated by the dummy fin structures712-716. For example inFIG.8A, the dummy gate structure800is cut into (dummy gate) portions800-1,800-2,800-3, and800-4. The portions800-1and800-2are separated by the dummy fin structure712; the portions800-2and800-3are separated by the dummy fin structure714; and the portions800-3and800-4are separated by the dummy fin structure716. As the dummy fin structures are formed with the same height as the dummy gate structure800, the dummy gate structure800is spontaneously cut into a number of portions by the dummy fin structures. Accordingly, an active gate structure that replaces the dummy gate structure may be cut into a number of separated (active gate) portions. However, in certain cases where some of the separated (active gate) portions are designed to be coupled to each other, the dummy fin structure(s) separating those portions may be recessed to allow those portions to electrically couple to each other, which will be discussed in further detail below.

The dummy gate structure800includes a dummy gate dielectric802and a dummy gate804, in some embodiments. A mask (not shown) may be formed over the dummy gate structure800. To form the dummy gate structure800, a dielectric layer is formed to overlay the active fins402-404and extend along sidewalls of the dummy fins712-716. The dielectric layer may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, or the like, and may be deposited or thermally grown.

A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, such as by a CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed of, for example, polysilicon, although other materials may also be used. The mask layer may be formed of, for example, silicon nitride or the like.

After the layers (e.g., the dielectric layer, the gate layer, and the mask layer) are formed, the mask layer may be patterned using suitable lithography and etching techniques to form the mask. The pattern of the mask then may be transferred to the gate layer and the dielectric layer by a suitable etching technique to form the dummy gate804and the underlying dummy gate dielectric802. The dummy gate804and the dummy gate dielectric802can straddle or otherwise cover a respective portion (e.g., a channel region) of each of the active fins402-404. For example, when one dummy gate structure is formed, a dummy gate and dummy gate dielectric of the dummy gate structure may straddle respective central portions of the active fins. The dummy gate804may also have a lengthwise direction perpendicular to the lengthwise direction of the fins, including the active fins and dummy fins.

The dummy gate dielectric802is shown to be formed over the active fins402-404(e.g., over the respective top surfaces and the sidewalls of the active fins) and over the STIs600in the example ofFIG.8A. In some embodiments, the dummy gate dielectric802may be formed by, e.g., thermal oxidization of a material of the fins. As such, the dummy gate dielectric802may be formed over the active fins but not over the STIs600. It should be appreciated that these and other variations are still included within the scope of the present disclosure.

Referring now to the cross-sectional view ofFIG.8B(cut along the lengthwise direction of the active fin404), the cut active fin404is overlaid by the portion800-3. Specifically, in addition to overlaying a portion of a top surface404T of the active fin404, the portion800-3can extend along one of the sidewalls (or edge) of the active fin404and be in contact with the top surface of a portion of the STI600. Such a portion of the STI600may be formed over a portion of the substrate302that is exposed when cutting the active fin404. As shown in the illustrated example ofFIG.8B, the portion800-3may present a reverse L-shape on this cross-section.

In some other embodiments, the dummy fins712-716may be formed, following the formation of the dummy gate structure800. For example, after forming the dummy gate structure800that overlays the active fins402-404and be in contact with the top surface of the STI600, portions of the dummy gate structure800, which respectively define footprints of the to-be formed dummy fins, can be removed (e.g., etched). As such, a number of cavities extending through the dummy gate structure800are formed, thereby exposing portions of the top surface of the STI600. Next, the cavities can be filled with one or more layers, each of which includes the above-described dielectric material of the dummy fins, to form the dummy fins712-716. When multiple layers are formed, each of the dummy fins712-716can include one or more layers lining itself. For example inFIG.9A, the dummy fins712-716are lined by the layers712′,714′ and716′, respectively.

Further, after filling the cavities with the one or more dielectric layers (to form the dummy fins712-716), respective upper portions of the dummy fins712-716may be removed and then replaced with one or more other dielectric layers. For example inFIG.9B, when removing the upper portions via an anisotropic etching process, the exposed top surfaces of the dummy fins712-716may have a flat surface. The one or more dielectric layers912/912′,914/914′, and916/916′ can thus follow such a flat profile. For example inFIG.9C, when removing the upper portions via an isotropic etching process, the exposed top surfaces of the dummy fins712-716may have a valley-based surface. The one or more dielectric layers922/922′,924/924′, and926/926′ can thus follow such a valley-based profile.

Corresponding to operation214ofFIG.2,FIG.10is a cross-sectional view of the FinFET device300including a gate spacer1000at one of the various stages of fabrication. The cross-sectional view ofFIG.10is cut along a lengthwise direction of the cut active fin404(e.g., cross-section C-C indicated inFIG.1A).

The gate spacer1000is formed around the dummy gate structure800. For example, the gate spacer1000may be formed on opposing sidewalls of each portion of the dummy gate structure800(inFIG.9, e.g., the gate spacer1000extending along opposite sidewalls of the dummy gate portion800-3). Although the gate spacer1000is shown as a single layer in the example ofFIG.9(and the following figures), it should be understood that the gate spacer can be formed to have any number of layers while remaining within the scope of the present disclosure. The gate spacer1000may be a low-k spacer and may be formed of a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, or the like. Any suitable deposition method, such as thermal oxidation, chemical vapor deposition (CVD), or the like, may be used to form the gate spacer1000. The shapes and formation methods of the gate spacer1000as illustrated inFIG.10are merely non-limiting examples, and other shapes and formation methods are possible. These and other variations are fully intended to be included within the scope of the present disclosure.

Corresponding to operation216ofFIG.2,FIG.11is a cross-sectional view of the FinFET device300including a number of source/drain structures1100at one of the various stages of fabrication. The cross-sectional view ofFIG.12is cut along a lengthwise direction of the cut active fin404(e.g., cross-section C-C indicated inFIG.1A). In some embodiments, the source/drain structure1100may correspond to the source/drain structure138shown inFIG.1A.

The source/drain structure(s) are generally formed in recesses of each of the active fin adjacent to a dummy gate structure, e.g., between adjacent dummy gate structures and/or next to a dummy gate structure. The recesses are formed by, e.g., an anisotropic etching process using the dummy gate structure(s) with the corresponding gate spacer(s) as an etching mask, in some embodiments, although any other suitable etching process may also be used. As shown inFIG.11, one source/drain structure1100is formed in a recess of the cut active fin404. Specifically, the source/drain structure1100is formed on a side opposite to the edge of the active fin404that is exposed after being cut (see, e.g.,FIG.5). Although not shown, it should be understood that during this fabrication stage, the FinFET device300can include a number of pairs of source/drain structures formed in one or more other non-cut active fins (e.g.,402) on opposite sides of the dummy gate structure800. For example, on the opposite sides of the dummy gate portion800-2(FIG.8A), a pair of source/drain structures can be formed, which may correspond to the source/drain structures134and136shown inFIG.1A, respectively.

The source/drain structures (e.g.,1100ofFIG.11) are formed by epitaxially growing a semiconductor material in the recess, using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof.

As illustrated inFIG.11, the epitaxial source/drain structure1100may have a surface raised from the top surface of the active fin404(e.g. raised above the non-recessed portions of the active fin404). Further, the source/drain structure1100may have facets. In some embodiments, when the resulting FinFET device is an n-type FinFET, the source/drain structure1100can include silicon carbide (SiC), silicon phosphorous (SiP), phosphorous-doped silicon carbon (SiCP), or the like. In some embodiments, when the resulting FinFET device is a p-type FinFET, the source/drain structure1100can include SiGe, and a p-type impurity such as boron or indium.

The epitaxial source/drain structure1100may be implanted with dopants, followed by an annealing process. The implanting process may include forming and patterning masks such as a photoresist to cover the regions of the FinFET device300that are to be protected from the implanting process. The source/drain structure1100may have an impurity (e.g., dopant) concentration in a range from about 1×1019cm−3to about 1×1021cm−3. P-type impurities, such as boron or indium, may be implanted in the source/drain structure1100of a P-type transistor. N-type impurities, such as phosphorous or arsenide, may be implanted in the source/drain structure1100of an N-type transistor. In some embodiments, the epitaxial source/drain structure1100may be in situ doped during their growth.

Corresponding to operation216ofFIG.2,FIG.12is a cross-sectional view of the FinFET device300including an interlayer dielectric (ILD)1200at one of the various stages of fabrication. The cross-sectional view ofFIG.12is cut along a lengthwise direction of the cut active fin404(e.g., cross-section C-C indicated inFIG.1A). In some embodiments, the ILD1200may correspond to the ILD152shown inFIG.1B.

In some embodiments, prior to forming the ILD1200, a contact etch stop layer (CESL)1202is formed over the structure, as illustrated inFIG.12. The CESL1202can function as an etch stop layer in a subsequent etching process, and may comprise a suitable material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like, and may be formed by a suitable formation method such as CVD, PVD, combinations thereof, or the like.

Next, the ILD1200is formed over the CESL1202and over the dummy gate structure800. In some embodiments, the ILD1200is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. After the ILD1200is formed, an optional dielectric layer (not shown) is formed over the ILD1200. The dielectric layer can function as a protection layer to prevent or reduce the loss of the ILD1200in subsequent etching processes. The dielectric layer may be formed of a suitable material, such as silicon nitride, silicon carbonitride, or the like, using a suitable method such as CVD, PECVD, or FCVD. After the dielectric layer is formed, a planarization process, such as a CMP process, may be performed to achieve a level upper surface for the dielectric layer. The CMP may also remove the mask (used to define the dummy gate structure800) and portions of the CESL1202disposed over the dummy gate structure. After the planarization process, the upper surface of the ILD1200or the dielectric layer (if formed) is level with the upper surface of the dummy gate, in some embodiments.

An example gate-last process (sometimes referred to as replacement gate process) can then performed to replace the dummy gate structure800with an active gate structure (which may also be referred to as a replacement gate structure or a metal gate structure). Prior to forming the active gate structure, one or more of the dummy fins may be recessed so as to allow some portions of the active gate structure to electrically couple to each other.FIGS.13-15Billustrate the cross-sectional views of further processing (or making) of the FinFET device300, which will be discussed in more detail as follows.

Corresponding to operation218ofFIG.2,FIG.13is a cross-sectional view of the FinFET device300in which the dummy fin712is recessed at one of the various stages of fabrication. The cross-sectional view ofFIG.13is cut along the lengthwise direction of the dummy gate structure800(e.g., cross-section B-B indicated inFIGS.1A-B).

The dummy fin712may be selected to be recessed as the respective portions of an active gate structure that will later replace the dummy gate portions800-1and800-2are designed to be electrically coupled to each other. By recessing the dummy fin712, a cavity may be formed between the portions800-1and800-2, which can be filled with a metal gate. Thus, the active gate portions that replace the dummy gate portions800-1and800-2can be electrically coupled to each other by the metal-filled cavity. To recess the dummy fin712, a mask (not shown) may be formed over the workpiece to expose a portion of the dummy fin712, followed by an etching processes to remove an upper portion of the dummy fin712, as illustrated inFIG.13.

The etching process may be configured to have at least some anisotropic etching characteristic to limit the undesired lateral etch. For example, the etching process can include a plasma etching process, which can have a certain amount of anisotropic characteristic. In such a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes), gas sources such as chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen (H2), nitrogen trifluoride (NF3), and other suitable gas sources and combinations thereof can be used with passivation gases such as nitrogen (N2), oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as argon (Ar), helium (He), neon (Ne), and other suitable dilutive gases and combinations thereof to control the above-described etching rates. As a non-limiting example, a source power of 10 watts to 3000 watts, a bias power of 0 watts to 3000 watts, a pressure of 1 millitorr to 5 torr, and an etch gas flow of 0 standard cubic centimeters per minute to 5000 standard cubic centimeters per minute may be used in the etching process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges are also contemplated.

In another example, the etching process can include a wet etching process, which can have a certain amount of isotropic characteristic, in combination with the plasma etching process. In such a wet etching process, a main etch chemical such as hydrofluoric acid (HF), fluorine (F2), and other suitable main etch chemicals and combinations thereof can be used with assistive etch chemicals such as sulfuric acid (H2SO4), hydrogen chloride (HCl), hydrogen bromide (HBr), ammonia (NH3), phosphoric acid (H3PO4), and other suitable assistive etch chemicals and combinations thereof as well as solvents such as deionized water, alcohol, acetone, and other suitable solvents and combinations thereof to control the above-described etching rates.

In some embodiments, the dummy fin712may be recessed, while leaving the neighboring dummy gate portions800-1and800-2substantially intact. As such, the cavity may have a similar width as the dummy fin712. However, it should be understood that portions of the dummy gate portions800-1and800-2can also be etched during recessing the dummy fin712, while remaining within the scope of the present disclosure. As such, the cavity may be formed with a wider width than the dummy fin712. Further, although the recessed top surface of the dummy fin712is shown as having a flat surface inFIG.13, it should be understood that the recessed top surface of the dummy fin712can be convex, concave, or otherwise curvature-based.

In some other embodiments, the dummy fin712may be recessed after the dummy gate structure800is removed.FIG.14illustrates a cross-sectional view of the FinFET device300at one of various fabrication stages in such embodiments. The cross-sectional view ofFIG.14is cut along the same direction asFIG.13. As shown inFIG.14, after removing the dummy gate structure800, a gate trench1400can be formed. The gate trench1400may also have a number of portions,1400-1,1400-2,1400-3, and1400-4, separated by the dummy fins712-716. Upon forming the gate trench, the dummy fin712may be recessed through the similar processes as discussed above. Once the upper portion of the dummy fin712is removed, the separated (gate trench) portions1400-1and1400-2may become connected to each other, as shown inFIG.14.

Corresponding to operation220ofFIG.2,FIG.15Ais a cross-sectional view of the FinFET device300including an active gate structure1500at one of the various stages of fabrication. The cross-sectional view ofFIG.15Ais cut along a lengthwise direction of the active gate structure1400(e.g., cross-section B-B indicated inFIG.1). Corresponding to the same operation,FIG.15Billustrates another cross-sectional view of the FinFET device300cut along a lengthwise direction of the cut active fin404(e.g., cross-section C-C indicated in FIG.1A). In some embodiments, the active gate structure1500may correspond to the gate structure120(as shown inFIGS.1A-B).

The active gate structure1500may be formed by replacing the dummy gate structure800. Specifically, the active gate structure1500can be formed by filling a gate trench (formed by removing the dummy gate structure800) with at least a gate dielectric layer and a metal gate layer. As illustrated, the active gate structure1500may include (active gate) portions,1500-1,1500-2, and1500-3, that are separated by the dummy fins714and716. The portion1500-1can overlay the active fin402, and the portion1500-2can overlay the cut active fin404. After the active gate structure1500is formed, the FinFET device300can include a number of transistors. For example, an active transistor, adopting the portion1500-1as its active gate structure and a portion of the active fin402(overlaid by the portion1500-1) as its channel, may be formed. However, it should be appreciated that the portion1200-2and the cut active fin404B (that is overlaid by the portion1500-2) may not form an active transistor. As defined above, the active gate portions1500-1and1500-2are sometimes referred to as non-PODE and PODE, respectively.

The active gate structure1500can include a gate dielectric layer1502, a metal gate layer1504, and one or more other layers that are not shown for clarity. For example, the active gate structure1500may further include a capping layer and a glue layer. The capping layer can protect the underlying work function layer from being oxidized. In some embodiments, the capping layer may be a silicon-containing layer, such as a layer of silicon, a layer of silicon oxide, or a layer of silicon nitride. The glue layer can function as an adhesion layer between the underlying layer and a subsequently formed gate electrode material (e.g., tungsten) over the glue layer. The glue layer may be formed of a suitable material, such as titanium nitride.

The gate dielectric layer1502is formed in a corresponding gate trench to surround (e.g., straddle) one or more fins. In an embodiment, the gate dielectric layer1502can be a remaining portion of the dummy gate dielectric802. In another embodiment, the gate dielectric layer1502can be formed by removing the dummy gate dielectric802, followed by conformal deposition or thermal reaction. In yet another embodiment, the gate dielectric layer1502can be formed by removing the dummy gate dielectric802, followed by no further processing step (i.e., the gate dielectric layer1502may be a native oxide over the active fins402-404).

The gate dielectric layer1502includes silicon oxide, silicon nitride, or multilayers thereof. In example embodiments, the gate dielectric layer1502includes a high-k dielectric material, and in these embodiments, the gate dielectric layer1502may have a k value greater than about 7.0, and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. The formation methods of gate dielectric layer1502may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. A thickness of the gate dielectric layer1502may be between about 8 Å and about 20 Å, as an example.

The metal gate layer1504is formed over the gate dielectric layer1502. The metal gate layer1504may be a P-type work function layer, an N-type work function layer, multi-layers thereof, or combinations thereof, in some embodiments. Accordingly, the metal gate layer1504is sometimes referred to as a work function layer. For example, the metal gate layer1504may be an N-type work function layer. In the discussion herein, a work function layer may also be referred to as a work function metal. Example P-type work function metals that may be included in the gate structures for P-type devices include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. Example N-type work function metals that may be included in the gate structures for N-type devices include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof.

A work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage Vtis achieved in the device that is to be formed. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process. The thickness of a P-type work function layer may be between about 8 Å and about 15 Å, and the thickness of an N-type work function layer may be between about 15 AÅ and about 30 Å, as an example.

Referring now to the cross-sectional view ofFIG.15B(cut along the lengthwise direction of the active fin404), the cut active fin404is overlaid by the (active gate) portion1500-2, which replaces the (dummy gate) portion800-3(FIG.8B). Thus, the active gate portion1500-2can inherit the profiles and dimensions of the dummy gate portion800-3. For example, in addition to overlaying a portion of a top surface404T of the active fin404, the portion1500-2can extend along one of the sidewalls (or edge) of the active fin404and be in contact with the top surface of a portion of the STI600. As shown in the illustrated example ofFIG.15B, the portion1500-2may present a reverse L-shape on this cross-section.

FIG.16illustrates a circuit diagram of an example circuit1600that can be formed by the disclosed methods, andFIG.17illustrates a top view of a portion of an integrated circuit1700including a number of the example circuits1600that are formed in accordance with the disclosed methods. As shown inFIG.16, the circuit1600includes a six-transistor (6T) Static Random Access Memory (SRAM) cell. However, it should be understood that any of various other circuits can also be formed by the disclosed methods such as, for example, an eight-transistor (8T) SRAM cell, a ten-transistor (10T) SRAM cell, a dual port SRAM cell, etc., while remaining within the scope of the present disclosure.

Referring first toFIG.16, the circuit1600includes six transistors:1602,1604,1606,1608,1610, and1612. The transistors1602-1604are each implemented as a p-type transistor, and the transistors1606-1612are each implemented as an n-type transistor. The transistors1602-1608are coupled between a first power supply, VCC (e.g., 0.75V), and a second power supply, VSS (e.g., ground). Further, the pair of transistors1602and1606and the pair of transistors1604and1608function as a first invertor and a second invertor, respectively. These two inverters are cross-coupled to each other, with a first internal node “X” coupled to a bit line (BL)1623through the transistor1610and a second internal node “Y” coupled to a bit line bar (BLB)1625through the transistor1612. The transistors1610and1612are gated by a word line (WL)1621. In general, the transistors1602-1604are referred to as pull-up (PU) transistors; the transistors1606-1608are referred to as pull-down (PD) transistors; and transistors1610-1612are referred to as pass-gate (PG) transistors.

Referring then toFIG.17, upon being at least partially formed, the integrated circuit1700includes active regions1702,1704,1706, and1708, each of which may be formed as a fin structure extending along a first lateral direction, as discussed above. Hereinafter, the active regions1702-1708are referred to as active fins1702-1708, respectively. In some embodiments, the active fins1702and1708are formed in a first conduction type (e.g., n-type), and the active fins1704and1706are formed in a second conduction type (e.g., p-type). The integrated circuit1700includes dummy regions1710,1712,1714,1716, and1718, each of which may also be formed as a fin structure extending along the same first lateral direction, as discussed above. Hereinafter, the dummy regions1710-1718are referred to as active fins1710-1718, respectively. The integrated circuit1700includes active gate structures1720,1722,1724, and1726, each of which may extend along a second lateral direction, as discussed above.

Each active fin is straddled (or otherwise overlaid) by the active gate structures1720-1726to define the respective channels of a number of transistors, and on the opposite sides of each active gate structure in the active fin, a number of source/drain structures can be formed. For example, source/drain structures1702-1and1702-2are formed on opposite sides of the active gate structure1722in the active fin1702; source/drain structures1702-2and1702-3are formed on opposite sides of the active gate structure1724in the active fin1702; source/drain structures1704-1and1704-2are formed on opposite sides of the active gate structure1724in the active fin1704; source/drain structures1706-1and1706-2are formed on opposite sides of the active gate structure1722in the active fin1706; source/drain structures1708-1and1708-2are formed on opposite sides of the active gate structure1722in the active fin1708; and source/drain structures1708-2and1708-3are formed on opposite sides of the active gate structure1724in the active fin1708.

By using the disclosed methods to form the integrated circuit1700, the active gate structures can each be cut into a number of portions by the dummy fins, upon those dummy fins being formed. For example, the active gate structure1720is cut into (active gate) portions1720-1,1720-2, and1720-3by the dummy fins1714and1712, respectively; the active gate structure1722is cut into (active gate) portions1722-1,1722-2, and1722-3by the dummy fins1714and1712, respectively; the active gate structure1724is cut into (active gate) portions1724-1,1724-2, and1724-3by the dummy fins1716and1714, respectively; and the active gate structure1726is cut into (active gate) portions1726-1,1726-2, and1726-3by the dummy fins1716and1714, respectively.

As such, those six transistors of a 6T-SRAM cell (e.g.,1600) can be realized. For example, the PG transistor1610can be defined by the active gate portion1722-3and the source/drain structures1702-1and1702-2; the PD transistor1606can be defined by the active gate portion1724-3and the source/drain structures1702-2and1702-3; the PU transistor1602can be defined by the active gate portion1724-3and the source/drain structures1704-1and1704-2; the PU transistor1604can be defined by the active gate portion1722-1and the source/drain structures1706-1and1706-2; the PD transistor1608can be defined by the active gate portion1722-1and the source/drain structures1708-1and1708-2; and the PG transistor1612can be defined by the active gate portion1724-1and the source/drain structures1708-2and1708-3. It should be understood that the integrated circuit1700can include any number of 6T-SRAM cells, while remaining within the scope of the present disclosure. Such 6T-SRAM cells may abut to each other, and thus, share some of the structures. The active fins1702-1708may each laterally extend further, which may be overlaid by a number of active gate structures to form neighboring cells. For example, the active gate structure1720, with the source/drain structure1702-1and a source/drain structure formed opposite the portion1720-3from the source/drain structure1702-1(not shown), can form one of the PG transistors of a neighboring (e.g., abutted to the left) cell.

Further, the integrated circuit1700includes a number of contacts1751,1752,1753,1754,1755,1756,1757, and1758. Each of the source/drain structures can be electrically coupled to a corresponding one of the contacts, causing the six transistors to collectively function as an SRAM cell. For example, the contact1751electrically connects the source/drain structure1702-1to a BL (e.g.,1623); the contact1752electrically connects the source/drain structures1702-2and1704-1together (thereby forming the internal node X); the contact1753electrically connects the source/drain structure1702-3to VSS; the contact1754electrically connects the source/drain structure1706-1to VCC; the contact1755electrically connects the source/drain structures1706-2and1708-2together (thereby forming the internal node Y); the contact1756electrically connects the source/drain structure1704-2to VCC; the contact1757electrically connects the source/drain structure1708-1to VSS; and the contact1758electrically connects the source/drain structure1708-3to a BLB (e.g.,1625).

In the existing technologies, the gate structures between neighboring PU transistors of a 6T SRAM cell are continuous (i.e., not being cut). This is because cutting these gate structures typically requires cutting a large number of other gate structures between the PU transistors of neighboring SRAM cells. Using the existing technologies to cut such a large number of gate structures commonly results in a discrepancy of cut profiles, which can disadvantageously induce a short between a contact and an active gate structure (e.g., between the contact1756and the active gate structure1726, between the contact1754and the active gate structure1720). However, using the disclosed methods to make the integrated circuit1700, the active gate structures1720-1726can each be spontaneously cut between the PU transistors (e.g.,1602and1604) by the dummy fin1714(upon the dummy fin1714being formed). Alternatively stated, the disclosed methods does not require an additional step to cut gate structures. In this way, the contact-gate short issues can be avoided.

In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric fin disposed between the first and second semiconductor fins, wherein the dielectric fin also extends along the first direction. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction, the gate structure comprising a first portion and a second portion. A top surface of the dielectric fin is vertically above respective top surfaces of the first and second semiconductor fins. The first portion and the second portion are electrically isolated by the dielectric fin. The first portion of the gate structure overlays an edge portion of the first semiconductor fin, and the second portion of the gate structure overlays a non-edge portion of the second semiconductor fin.

In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a memory cell. The memory cell includes a first active region, a second active region, a third active region, and a four active region, wherein the first through four active regions each extend along a first direction. The memory cell includes a first dielectric fin, a second dielectric fin, and a third dielectric fin, wherein the first through third dielectric fins each extend along the first direction, and wherein the first dielectric fin is disposed between the first and second active regions, the second dielectric fin is disposed between the second and third active regions, and the third dielectric fin is disposed between the third and fourth active regions. The memory cell includes a first gate structure and a second gate structure, wherein the first and second gate structures both extend along a second direction perpendicular to the first direction, and wherein the first gate structure comprises a first portion, a second portion, and a third portion, and the second gate structure comprises a first portion, a second portion, and a third portion. The first and second portions of the first gate structure are separated by the first dielectric fin, and the second and third portions of the first gate structure are separated by the second dielectric fin. The first and second portions of the second gate structure are separated by the second dielectric fin, and the second and third portions of the second gate structure are separated by the third dielectric fin.

In yet another aspect of the present disclosure, a method for fabricating a semiconductor device is disclosed. The method includes forming a first semiconductor fin and a second semiconductor fin, wherein the first and second semiconductor fins both extend along a first direction. The method includes forming a dielectric fin disposed between the first and second semiconductor fins, wherein the dielectric fin also extends along the first direction and is taller than the first and second semiconductor fins. The method includes forming a gate structure extending along a second direction perpendicular to the first direction, wherein the gate structure comprises a first portion and a second portion. The first portion and the second portion are separated by the dielectric fin. The first portion of the gate structure overlays an edge portion of the first semiconductor fin, and the second portion of the gate structure overlays a non-edge portion of the second semiconductor fin.