Sense amplifier and semiconductor device for securing operation margin of sense amplifier

A sense amplifier includes an equalization unit configured to precharge a pair of bit lines to a level of a bit line precharge voltage in response to a bit line equalizing signal; and an amplification unit configured to sense and amplify voltages of the pair of bit lines, supply, during an active operation, a ground voltage to a pull-down node of a latch section, and supply, when a precharge signal is enabled, a first voltage lower than the ground voltage to the pull-down node of the latch section for a predetermined time.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2015-0055447 filed on Apr. 20, 2015, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a sense amplifier and a semiconductor device including the same, and more particularly to a technology for securing the operation margin of a sense amplifier.

2. Related Art

Recent developments in electronic systems are leading to advances in highly integrated high-speed semiconductor memory devices. In order to increase the operating speeds of the semiconductor memory devices, a synchronous memory device has been developed. This synchronous memory device is a device that has an interface being synchronized with a system clock.

A single data rate (hereinafter, referred to as “SDR”) synchronous memory device usually refers to a synchronous memory device in which only one word of data is transmitted per clock cycle. In the SDR synchronous memory device, for example, the input and output of the data is in synchronization with the rising edge of a clock signal.

The next generation of synchronous memory device is double data rate (hereinafter, referred to as “DDR”) synchronous memory device. A DDR synchronous memory device usually refers to a synchronous memory device that reads or writes two words of data per clock cycle. The interface technology of the DDR synchronous memory device may be accomplished by reading and writing data on both the rising and falling edges of the clock signal.

This allows a doubling of bandwidth without having to change the frequency of the clock signal.

Among various semiconductor memory devices, a dynamic random access memory (hereinafter, referred to as “DRAM”) is a representative volatile memory. The memory cell of the DRAM may include a cell transistor and a cell capacitor.

The cell transistor allows a memory controller to control an access to the cell capacitor, which stores charges corresponding to data. That is to say, according to the amount of the charges stored in the cell capacitor, a sense amplifier may sense the amount of the charges to determine what the charges stored in the cell capacitor represent between a logic-high level and a logic-low level. If a word line is enabled in a semiconductor memory device, charge sharing occurs between a bit line and a bit line bar, and then the sense amplifier operates.

FIG. 1illustrates that a logic-low data stored in a cell is driven by a pull-down control signal after a charge-sharing operation started. A sense amplifier senses the logic-low data of the cell through a pair of bit lines BL and BLB when a word line WL is enabled.FIG. 2illustrates that a logic-high data stored in the cell is driven by a pull-up control signal after a charge-sharing operation started. The sense amplifier senses the logic-high data of the cell through the pair of bit lines BL and BLB when the word line WL is enabled.

However, continued advances in highly integrated DRAM are leading to a reduction in cell area, which may cause a decrease in capacitance of cell capacitors. As a consequence, a sensing margin Delta V may decrease as shown inFIGS. 1 and 2.

SUMMARY

Various embodiments are directed to controlling the driving voltage of a sense amplifier and securing an operation margin.

In an embodiment, a sense amplifier may include: an equalization unit configured to precharge a pair of bit lines to a level of a bit line precharge voltage in correspondence to a bit line equalizing signal; and an amplification unit configured to sense and amplify voltages of the pair of bit lines, supply a ground voltage to a pull-down node in an active operation, and supply a first voltage lower than the ground voltage to the pull-down node for a predetermined time when a precharge signal is enabled.

In an embodiment, a semiconductor device may include: a sense amplifier configured to precharge a pair of bit lines to a level of a bit line precharge voltage in correspondence to a bit line equalizing signal, and sense and amplify data of the pair of bit lines in correspondence to driving voltages applied to a pull-up power line and a pull-down power line; and a sense amplifier control circuit configured to supply a core voltage to the pull-up power line in correspondence to a pull-up driving signal, and supply a minus voltage lower than a ground voltage to the pull-down power line for a predetermined time in correspondence to a pull-down driving signal when a precharge signal is enabled.

According to the embodiments, since it is possible to secure the operation margin of a sense amplifier, the manufacturing yield of a semiconductor device may be increased and a chip size may be decreased.

DETAILED DESCRIPTION

Hereinafter, a sense amplifier and a semiconductor device including the same will be described below with reference to the accompanying drawings through various examples of embodiments.

The data stored in a semiconductor device in accordance with an embodiment is identified as a high level (H) or a low level (L) in correspondence to a voltage level, and is expressed as ‘1’ or ‘0’. A data value is differently identified according to a voltage level and a current magnitude. In the case of binary data, a high level is defined as a high voltage, and a low level is defined as a low voltage lower than the high level.

FIG. 3is a configuration diagram illustrating an example of a memory cell100and a sense amplifier200in accordance with an embodiment.

The memory cell100may store charges therein and, if the memory cell100is storing charges, provide the charges to a bit line BL coupled to the memory cell100. The memory cell100, which include an NMOS transistor N1and a capacitor C1, may be coupled to a word line WL through which the memory cell100may be selected. The NMOS transistor N1is coupled between the bit line BL and the capacitor C1, and has a gate terminal which is coupled to the word line WL. The capacitor C1, which is coupled between the NMOS transistor N1and a terminal to which a cell plate voltage VCP applies, may store data.

When the word line WL is enabled, the memory cell100stores the data applied from a pair of bit lines BL and BLB or outputs stored data to the sense amplifier200through the pair of bit lines BL and BLB.

A unit cell (e.g., the memory cell100) includes a switching element (e.g., N1) and a capacitor (e.g., C1). The switching element, which is coupled between the bit line BL and the capacitor, may be turned-on in response to a signal (e.g., a logic-high signal) applied to the word line WL. The capacitor, which is coupled between a terminal of a cell plate voltage and the switching element, may store data.

The sense amplifier200may include an equalization unit210, an amplification unit220, and a column selection unit230.

The equalization unit210precharges the pair of bit lines BL and BLB to the level of a bit line precharge voltage VBLP in response to a bit line equalizing signal BLEQ. The bit line precharge voltage VBLP may be a voltage corresponding to (VCORE/2)−Vminus. That is to say, the bit line precharge voltage VBLP may be a voltage lower by a minus voltage Vminus than one half of a core voltage VCORE.

The equalization unit210may include a plurality of NMOS transistors N2to N4. The gate terminals of the plurality of NMOS transistors N2to N4are coupled in common to a terminal to which the bit line equalizing signal BLEQ is applied. The NMOS transistors N2and N3are coupled between a terminal to which the bit line precharge voltage VBLP is applied and the pair of bit lines BL and BLB, respectively. The source/drain terminals of the NMOS transistor N4are coupled to the pair of bit lines BL and BLB, respectively.

The amplification unit220may include a pull-up section221, a latch section222and pull-down sections223and224, and may amplify voltage signals transmitted through the pair of bit lines BL and BLB.

The pull-up section221may supply the core voltage VCORE to the latch section222in response to a driving signal SWB. The pull-up section221may include a PMOS transistor P1. The PMOS transistor P1may be coupled between the latch section222and a terminal through which the core voltage VCORE is transmitted, and may be applied with the driving signal SWB through the gate terminal thereof.

The latch section222amplifies the data transmitted through the pair of bit lines BL and BLB. The latch section222may include PMOS transistors P2and P3and NMOS transistors N5and N6forming a latch structure. The gate terminals of the PMOS transistor P2and the NMOS transistor N5are coupled to the bit line bar BLB in common. The gate terminals of the PMOS transistor P3and the NMOS transistor N6are coupled to the bit line BL in common.

The pull-down section223is controlled by a driving signal SW1, and pulls the voltage level of the latch section222down to the level of a ground voltage VSS. The pull-down section223may include an NMOS transistor N7which is coupled between a pull-down node of the latch section222and a terminal through which the ground voltage VSS is applied, and may be applied with the driving signal SW1through the gate terminal thereof. The pull-down section223is turned on if the driving signal SW1is enabled at a time when the amplification unit220operates, and supplies the ground voltage VSS to the latch section222.

The pull-down section224is controlled by a driving signal SW2, and pulls the voltage level of the latch section222down to the level of the minus voltage Vminus. In an embodiment, the minus voltage Vminus has a negative voltage level lower than the ground voltage VSS. The pull-down section224may include an NMOS transistor N8which is coupled between the latch section222and a terminal through which the minus voltage Vminus is applied, and may be applied with the driving signal SW2through the gate terminal thereof.

The pull-down section224is turned on and supplies the minus voltage Vminus to the latch section222when the driving signal SW1is disabled and the pull-down section223is turned off. In other words, in order to additionally secure an operation voltage of the bit line sense amplifier200, the minus voltage Vminus is supplied to the latch section222.

In the case where the minus voltage Vminus is supplied as the driving voltage of the sense amplifier200, an abrupt current loss may be induced. Thus, the ground voltage VSS is supplied during active, write and read operation periods, and the minus voltage Vminus is supplied by a precharge command before the pair of bit lines BL and BLB are equalized. After a signal being outputted from the memory cell100is amplified and stored in the latch section222, an equalization operation for the pair of bit lines BL and BLB is performed.

The pull-down section224is turned off if the driving signal SW2is disabled at a time when the amplification unit220is disabled.

The column selection unit230selectively controls electrically coupling of the pair of bit lines BL and BLB and a pair of input/output lines IO and IOB in response to a column select signal YI. The column selection unit230may include NMOS transistors N9and N10which are coupled between the pair of bit lines BL and BLB and the pair of input/output lines IO and IOB, and may be applied with the column select signal YI through the common gate terminal thereof.

FIG. 4is a detailed configuration diagram illustrating an example of a driving signal control circuit for driving the sense amplifier200shown inFIG. 3.

The driving signal control circuit may include a word line driving block300, a sense amplifier driving block400, and a bank control block500. The sense amplifier driving block400may be formed in a repeater region. The bank control block500may include a command control unit510, delay units520and530, a driving signal generation unit540, a pull-up control unit550, and pull-down control units560and570.

The word line driving block300may include an inverter IV1, which drives a signal transmitted through a main word line MWL, and output a resultant signal to the word line WL. While the embodiment illustrates only one inverter IV1which operates as a driving block, it is to be noted that the word line driving block300may include a plurality of inverters.

The sense amplifier driving block400may include a plurality of inverters IV2to IV5. The inverter IV2drives a bit line equalizing signal BLEQB, and outputs a bit line equalizing signal BLEQ to the equalization unit210. The inverter IV3drives a pull-up driving signal SAP, and outputs a driving signal SWB to the pull-up section221. The inverter IV4drives a pull-down driving signal SANB1, and outputs a driving signal SW1to the pull-down section223. The inverter IV5drives a pull-down driving signal SANB2, and outputs the driving signal SW2to the pull-down section224.

While the embodiment illustrates only one of each of the inverters IV2to IV5which operate as a driving block, it is to be noted that the sense amplifier driving block400may be realized by a plurality of inverter chains.

The command control unit510generates an active signal ACT and a precharge signal PCG in response to a bank control signal BKACC. The bank control signal BKACC is a bank access signal which is enabled by an external active command and is disabled by an external precharge command.

The delay unit520delays the active signal ACT by a predetermined time, and outputs an active delay signal ACTD1to the pull-up control unit550and the pull-down control unit560. The delay unit530delays the precharge signal PCG by a predetermined time, and outputs a precharge delay signal PCGD2to the driving signal generation unit540, the pull-up control unit550and the pull-down control unit570.

The driving signal generation unit540generates a signal to transmit it though the main word line MWL and the bit line equalizing signal BLEQB in response to the active signal ACT and the precharge delay signal PCGD2. The pull-up control unit550outputs the pull-up driving signal SAP in response to the active delay signal ACTD1and the precharge delay signal PCGD2.

The pull-down control unit560outputs a signal for controlling a pull-down operation, to the pull-down control unit570, in response to the active delay signal ACTD1and the precharge signal PCG. The pull-down control unit570generates the pull-down driving signals SANB1and SANB2for controlling pull-down operations in response to the precharge delay signal PCGD2and the output signal of the pull-down control unit560.

In an embodiment, the pull-down control unit560first controls the driving signals SW1and SW2by being inputted with the precharge signal PCG not having passed through delay means. Further, after the precharge signal PCG is enabled and is delayed by a delay time of the delay unit530, the driving signal generation unit540and the pull-up control unit550control the signal of the word line WL, the bit line equalizing signal BLEQ and the driving signal SWB.

FIG. 5is a timing diagram to explain the operation process of the sense amplifier200shown inFIG. 3.

In the case where the active signal ACT is enabled to a high level, the driving signal generation unit540outputs the bit line equalizing signal BLEQB having a high level and outputs a signal having a low level to the main word line MWL.

Then, the signal of the word line WL which is outputted from the word line driving block300transitions to a high level, and the bit line equalizing signal BLEQ becomes a low level. The charges stored in the cell100are transferred to the bit line BL, and the equalization unit210becomes a turned-off state.

After the delay time of the delay unit520, the driving signal SWB is disabled and the driving signal SW1is enabled. The delay unit520has the delay time until a sensing margin voltage Delta V of the sense amplifier200is secured.

That is to say, in the case where the driving signal SWB is a high level and the driving signals SW1and SW2are low levels, the sense amplifier200does not operate. In the case where the sense amplifier200is in a precharge state, the sense amplifier200precharges bit lines with the bit line precharge voltage VBLP. If the word line WL is enabled, the pair of bit lines BL and BLB start to develop due to the difference between the voltages applied to the pair of bit lines BL and BLB.

The delay unit520delays the active signal ACT, and enables the active delay signal ACTD1after the delay time. The pull-up control unit550enables the pull-up driving signal SAP in response to the active delay signal ACTD1. If the driving signal SWB becomes a low level, the pull-up section221is turned on, and the amplification unit220operates. If the pull-up section221is turned on, the core voltage VCORE is supplied to the latch section222.

If the active delay signal ACTD1is enabled, the pull-down driving signal SANB1is first enabled to a low level by the operations of the pull-down control units560and570. Also, the driving signal SW1transitions to a high level by the sense amplifier driving block400.

In the case where the driving signal SW1is the high level, the pull-down section223is turned on, and the ground voltage VSS is supplied to the latch section222. In other words, the ground voltage VSS is supplied as a pull-down voltage to the latch section222during a period in which the driving signal SW1is the high level.

The pull-down control unit570enables the pull-down driving signal SANB2to a low level after a predetermined delay time has passed from when the pull-down driving signal SANB1is enabled to the low level. The driving signal SW2retains the low level during a period in which the driving signal SW1is the high level.

Thereafter, if the bank control signal BKACC is disabled and the precharge signal PCG is enabled, the pull-down control units560and570disable the pull-down driving signal SANB1to a high level. Then, the driving signal SW1is disabled to the low level by the sense amplifier driving block400. When the pull-down section223is turned off, the ground voltage VSS is not supplied any more to the latch section222.

If the precharge signal PCG is enabled to a high level, the pull-down control units560and570make the pull-down driving signal SANB2transition to the low level. Then, the driving signal SW2transitions to a high level by the sense amplifier driving block400.

When the pull-down section224is turned on during a period in which the driving signal SW2is the high level, the minus voltage Vminus is supplied to the latch section222. In an embodiment, during a specified period (e.g., a period T1) from the enable time of the precharge signal PCG, a sensing margin Delta V of the sense amplifier200may be increased, whereby it is possible to secure the sensing margin Delta V of the sense amplifier200.

The pull-down section224supplies the minus voltage Vminus to the latch section222during the period (e.g., the period T1) from when the precharge signal PCG is enabled to the high level to before the bit line equalizing signal BLEQ is enabled to a high level. A time during which the driving signal SW2is enabled and the pull-down section224supplies the minus voltage Vminus may be set as the delay time of the delay unit530.

If the active signal ACT transitions to a low level, the driving signal generation unit540outputs a signal having a high level to the main word line MWL. Then, the word line driving block300makes a signal being outputted from the word line WL transition to a low level. When the NMOS transistor N1of the cell100is turned off, the charges of the cell100are not transferred any more to the bit line BL.

After the precharge signal PCG is enabled to the high level, if the delay time of the delay unit530has passed, the precharge delay signal PCGD2is enabled. Then, the driving signal generation unit540makes the bit line equalizing signal BLEQB transition to a low level.

The bit line equalizing signal BLEQ transitions to the high level by the sense amplifier driving block400. When the equalization unit210is turned on, the pair of bit lines BL and BLB are equalized to the level of the bit line precharge voltage VBLP.

If the precharge delay signal PCGD2is enabled, the pull-up control unit550transitions the pull-up driving signal SAP to a low level. The sense amplifier driving block400transitions and outputs the driving signal SWB to the high level. Then, the pull-up section221is turned off, and the sense amplifier200does not operate.

If the precharge delay signal PCGD2is enabled, the pull-down control unit570transitions the pull-down driving signal SANB2to the high level. The sense amplifier driving block400transitions the driving signal SW2to the low level. Then, as the pull-down section224is turned off, the minus voltage Vminus is not supplied any more to the latch section222.

In an embodiment, the minus voltage Vminus is supplied to the sense amplifier200during an enable period (e.g., the period T1) of the driving signal SW2, and thus an amplified voltage signal may be stored in a memory cell. As a consequence, a sensing margin for the next active operation may increase as compared to known sense amplifiers not using negative voltages.

FIG. 6is a configuration diagram illustrating an example of a sense amplifier600and a sense amplifier control circuit in accordance with an embodiment. The sense amplifier control circuit may include a sense amplifier driving block700and a driving signal generation unit800.

The sense amplifier600according to an embodiment may include an equalization unit610, an amplification unit620, a pull-down unit630, and a column selection unit640.

The equalization unit610precharges a pair of bit lines BL and BLB to the level of a bit line precharge voltage VBLP in response to a bit line equalizing signal BLEQ.

The equalization unit610may include a plurality of NMOS transistors N11to N13. The gate terminals of the plurality of NMOS transistors N11to N13are coupled in common to a terminal to which the bit line equalizing signal BLEQ is applied. The NMOS transistors N11and N12are coupled between a terminal to which the bit line precharge voltage VBLP is applied and the pair of bit lines BL and BLB, respectively. The source/drain terminals of the NMOS transistor N13are coupled to the pair of bit lines BL and BLB, respectively.

The amplification unit620amplifies the data transmitted through the pair of bit lines BL and BLB in response to the voltages applied from a pull-up power line RTO and a pull-down power line SB. The amplification unit620may include PMOS transistors P4and P5and NMOS transistors N14and N15forming a latch structure. The gate terminals of the PMOS transistor P4and the NMOS transistor N14are coupled to the bit line bar BLB in common. The gate terminals of the PMOS transistor P5and the NMOS transistor N15are coupled to the bit line BL in common.

The pull-down unit630is controlled by a driving signal SAN1, and pulls the voltage level of the amplification unit620down to the level of a ground voltage VSS. The pull-down unit630may include an NMOS transistor N16which is coupled between the amplification unit620and the application terminal of the ground voltage VSS, and may be applied with the driving signal SAN1through the gate terminal thereof. The pull-down unit630is turned on if the driving signal SAN1is enabled at a time when the amplification unit620operates, and supplies the ground voltage VSS to the amplification unit620.

The column selection unit640selectively controls electrically coupling of the pair of bit lines BL and BLB and a pair of input/output lines IO and IOB in response to a column select signal YI. The column selection unit640may include NMOS transistors N17and N18which are coupled between the pair of bit lines BL and BLB and the pair of input/output lines IO and JOB, and may be applied with the column select signal YI through the common gate terminal thereof.

The sense amplifier driving block700may include a pull-up driving unit710, a precharge unit720, and a pull-down driving unit730.

The pull-up driving unit710supplies a core voltage VCORE to the pull-up power line RTO in response to a pull-up driving signal SAP. The pull-up driving unit710may include a PMOS transistor P6which is coupled between the pull-up power line RTO and a terminal to which the core voltage VCORE is applied, and may be applied with the pull-up driving signal SAP through the gate terminal thereof.

The precharge unit720precharges the pull-up power line RTO and the pull-down power line SB to the level of the bit line precharge voltage VBLP in response to the bit line equalizing signal BLEQ.

The precharge unit720may include a plurality of NMOS transistors N19to N21. The gate terminals of the plurality of NMOS transistors N19to N21are coupled in common to a terminal to which the bit line equalizing signal BLEQ is applied. The NMOS transistors N19and N20are coupled between a terminal to which the bit line precharge voltage VBLP is applied and the pull-up power line RTO and the pull-down power line SB, respectively. The source/drain terminals of the NMOS transistor N21are coupled to the pull-up power line RTO and the pull-down power line SB, respectively.

The pull-down driving unit730is controlled by a driving signal SAN2and supplies a minus voltage Vminus to the pull-down power line SB. The pull-down driving unit730may include an NMOS transistor N22which is coupled between the precharge unit720and a terminal to which the minus voltage Vminus is applied, and may be applied with the pull-down driving signal SAN2through the gate terminal thereof.

The pull-down driving unit730is turned on at a time when the pull-down driving signal SAN2is enabled, and supplies the minus voltage Vminus to the pull-down power line SB. The pull-down driving unit730is turned off at a time when the pull-down driving signal SAN2is disabled.

In an embodiment, a layout for the pull-down unit630and pull-down driving unit730may be designed such that a direct current path is not formed between them. For example, the pull-down unit630, which supplies the ground voltage VSS to the pull-down power line SB by the driving signal SAN1, is disposed in the region of the bit line sense amplifier600, whereas the pull-down driving unit730, which supplies the minus voltage Vminus to the pull-down power line SB, is positioned in the region of the sense amplifier driving block700. Since a direct current path is not formed between the pull-down unit630and the sense amplifier driving block700, a sense amplifier in accordance with an embodiment of the present invention may reduce noise.

The driving signal generation unit800generates the pull-up driving signal SAP and the pull-down driving signal SAN2in response to an active signal ACT and a precharge signal PCG, and outputs the pull-up driving signal SAP and the pull-down driving signal SAN2to the sense amplifier driving block700.

FIG. 7is a timing diagram to explain the operation process of the sense amplifier600and the sense amplifier driving block700shown inFIG. 6.

In the case where the active signal ACT is enabled to a high level, the signal of a word line WL transitions to a high level, and the bit line equalizing signal BLEQ becomes a low level. As a result, charge-sharing between the cell100and the bit line BL occurs, and the equalization unit610becomes a turned-off state.

In the case where the driving signal SAN1is a low level, the sense amplifier600does not operate. In the case where the sense amplifier600is in a precharge state, the sense amplifier600precharges bit lines with the bit line precharge voltage VBLP. If the word line WL is enabled, the pair of bit lines BL and BLB start to develop due to the difference between the voltages applied to the pair of bit lines BL and BLB.

After a predetermined time is delayed from when the active signal ACT is enabled, the driving signal generation unit800enables the pull-up driving signal SAP to a low level and enables the driving signal SAN1to a high level.

If the pull-up driving signal SAP is enabled to the low level, the pull-up driving unit710is turned on, and the core voltage VCORE is supplied to the pull-up power line RTO. If the driving signal SAN1is enabled to the high level, the pull-down unit630is turned on, and the ground voltage VSS is supplied to the pull-down power line SB and the amplification unit620operates. In other words, the ground voltage VSS is supplied as a pull-down voltage to the amplification unit620during a period in which the driving signal SAN1is the high level.

Thereafter, if the precharge signal PCG is enabled to a high level, the driving signal generation unit800disables the driving signal SAN1to the low level and enables the pull-down driving signal SAN2to a high level.

When the pull-down unit630is turned off, the ground voltage VSS is not supplied any more to the pull-down power line SB. The pull-down driving unit730is turned on, and the minus voltage Vminus is supplied to the pull-down power line SB during a period (e.g., a period T2) in which the pull-down driving signal SAN2has the high level.

In an embodiment, during a specified period (e.g., the period T2) from the enable time of the precharge signal PCG, the sensing margin Delta V of the sense amplifier600may increase.

The pull-down driving unit730supplies the minus voltage Vminus to the pull-down power line SB during the specified period (e.g., the period T2) from when the precharge signal PCG is enabled to the high level to before the bit line equalizing signal BLEQ is enabled to a high level. A time during which the pull-down driving signal SAN2is enabled and the pull-down driving unit730supplies the minus voltage Vminus may be set as a delay time in the driving signal generation unit800.

If the active signal ACT transitions to a low level, the signal of the word line WL transitions to a low level. When the NMOS transistor N1of the cell100is turned off, the charges of the cell100are not transferred any more to the bit line BL.

If a predetermined delay time (e.g., the period T2) has passed after the precharge signal PCG is enabled to the high level, the bit line equalizing signal BLEQ transitions to the high level. When the equalization unit610is turned on, the pair of bit lines BL and BLB are equalized to the level of the bit line precharge voltage VBLP.

In the case where the bit line equalizing signal BLEQ is the high level, the precharge unit720is turned on, and the pull-up power line RTO and the pull-down power line SB are precharged to the level of the bit line precharge voltage VBLP.

If the pull-up driving signal SAP transitions to a high level, the pull-up driving unit710is turned off, and the amplification unit620does not operate. If the pull-down driving signal SAN2transitions to a low level, the pull-down driving unit730is turned off, and the minus voltage Vminus is not supplied any more to the pull-down power line SB.

In an active operation mode, the core voltage VCORE is supplied to the pull-up power line RTO and the ground voltage VSS is supplied to the pull-down power line SB. In a precharge operation mode, the core voltage VCORE is supplied to the pull-up power line RTO and the minus voltage Vminus lower than the ground voltage VSS is supplied to the pull-down power line SB during the predetermined period (e.g., the period T2).

So far, various embodiments have been described in detail. For reference, embodiments including additional component elements, which are not directly associated with the technical spirit of the present invention, may be exemplified in order to describe the present inventive concept in further detail. Moreover, an active high configuration or an active low configuration for indicating the activated states of signals and circuits may vary depending upon an embodiment.

Furthermore, the configurations of transistors may be changed as the occasion demands in order to realize the same function. That is to say, the configurations of a PMOS transistor and an NMOS transistor may be replaced with each other, and as the occasion demands, various transistors may be employed. Since these circuit changes have a large number of cases and can be easily inferred by those skilled in the art, the enumeration thereof will be omitted herein.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the sense amplifier and the semiconductor device including the same described herein should not be limited based on the described embodiments.