Low resistance vertical channel 3D memory

A memory device, which can be configured as a 3D NAND flash memory, includes a stack of conductive strips and an opening through the stack exposing sidewalls of conductive strips on first and second sides of the opening. Some of the conductive strips in the stack are configured as word lines. Data storage structures are disposed on the sidewalls of the stack. A vertical channel film is disposed vertically in contact with the data storage structures. The vertical channel film is connected at a proximal end to an upper channel pad over the stack, and at a distal end to a lower channel pad disposed in a lower level of the opening. The upper and lower channel pads may comprise an epitaxial semiconductor and be thicker than the vertical channel film disposed on the sidewalls of the stack.

BACKGROUND

Field of the Invention

The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.

Description of Related Art

As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin-film transistor techniques are applied to charge trapping memory technologies in Lai et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.

Another structure that provides vertical NAND cells in a charge trapping memory technology is described in Katsumata, et al., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009. The structure described in Katsumata et al. includes a vertical NAND gate, using silicon-oxide-nitride-oxide-silicon SONOS charge trapping technology to create a storage site at each gate/vertical channel interface. The memory structure is based on a column of semiconductor material arranged as the vertical channel for the NAND gate, with a lower select gate adjacent the substrate, and an upper select gate on top. A plurality of horizontal word lines is formed using planar word line layers that intersect with the columns, forming a so-called gate-all-around the cell at each layer.

In another 3D NAND flash memory technology with a vertical thin-channel memory, vertical thin-channel cells in the memory can be arranged along vertical active pillars which support cells on opposing sides of one pillar, and in some configurations comprise U-shaped semiconductor thin-film structure in which a NAND string extends down one side and up the other side of a single pillar. The active pillars are disposed between stacks of conductive strips operable as word lines with memory elements in between as described in U.S. Pat. No. 9,524,980, issued 20 Dec. 2016, which is incorporated by reference as if fully set forth herein. As a result of these structures, two memory cells are formed per frustum of the active pillar, where each memory cell at the frustum includes a channel in the U-shaped semiconductor thin-film structure on one side of the active pillar. In alternative approaches, vertical channel structures can support even and odd NAND strings on opposing sides of each vertical channel structure.

In general, vertical channel structures can suffer from high resistance, specifically in the lower region of the structure. Furthermore, it can be difficult to have a good electrical connection between the bit lines in the 3D NAND flash memory and thin films in the upper regions of the vertical channel structures.

It is desirable to provide a structure for three-dimensional integrated circuit memory with vertical channel structures having with lower resistance and higher reliability in the lower regions and having better and more reliable connection to bit lines or other conductors in the upper regions.

SUMMARY

A memory is described, which can be configured as a 3D NAND flash memory. The memory comprises a stack of conductive strips. An opening, such as a trench or a hole, through the stack exposes sidewalls of conductive strips on first and second sides of the opening. Data storage structures are disposed on the sidewalls of one or both sides of the opening and are adjacent to the conductive strips in the stack. A vertical channel structure comprising one or more vertical channel films is disposed vertically in contact with the data storage structures on one or both sides of the opening. The vertical channel structure has a proximal end at the top or upper levels of the stack and a distal end in the lower levels of the stack. In some embodiments of the vertical channel structure, the vertical channel film is connected at the proximal end to an upper channel pad disposed on top of the stack. The upper channel pad can be formed by selective epitaxy, forming a self-aligned pad of epitaxial silicon or other material, having a thickness greater than the thickness of the vertical channel film in the vertical channel structure.

In some embodiments of the vertical channel structure, the vertical channel film is connected at the distal end to a lower channel pad. The lower channel pad can be formed by selective epitaxy, forming a self-aligned pad of epitaxial silicon or other material, having a thickness greater than the thickness of the vertical channel film in the vertical channel structure. Also, the lower channel pad and the upper channel pad can be formed in the same selective epitaxy growth process, whereby self-aligned pads are formed on both the proximal and distal ends of the vertical channel structure.

In some embodiments of the vertical channel structure, the vertical channel film is connected at the proximal end to a second upper channel pad disposed on top of the stack. The second upper channel pad can be formed by selective epitaxy, forming a self-aligned pad of epitaxial silicon or other material, having a thickness greater than the thickness of the vertical channel film in the vertical channel structure. Also, the second upper channel pad, and one or both of the first mentioned upper channel pad and the lower channel pad can be formed in the same selective epitaxial growth process, whereby two self-aligned pads are formed on the proximal end of the vertical channel structure and one is formed on the distal end of the vertical channel structure.

As used herein, a “connection” or “connected” between the vertical channel films in a vertical channel structure and the pads refers to an electrical connection as by physical contact so that current suitable for operation of the memory passes from the vertical channel films through the pads.

In some embodiments, the upper and lower channel pads are conductively doped, including N+ doping (or P+) having a greater concentration of doping than the vertical channel film, which can be doped for operation as channels for the memory cells in the NAND strings.

In some embodiments, the memory may include one or more patterned conductor layers over the stack, including a source line, and an interlayer connector connecting the source line to the upper channel pad over the stack. In some embodiments, the memory may include one or more patterned conductor layers over the stack, including a bit line, and an interlayer connector connecting the bit line to the upper channel pad over the stack.

Methods for manufacturing memory devices with one or more vertical channel and one or more channel pads as described herein are also provided. In one embodiment, a method for manufacturing includes forming vertical channel films disposed on the sidewalls of the openings in the stack. The method for manufacturing further includes forming upper channel pads at the tops of stacks of conductive strips and lower channel pads in a lower level of the opening.

In an example described herein, a 3D memory device comprises a stack of conductive strips with an opening. A vertical channel structure is arranged in the opening, the vertical channel structure in contact with the data storage structure on the sidewalls of the openings. The vertical channel structure includes a first vertical channel film and a second channel film. Both the first and second channel films have proximal ends and distal ends. The first channel film is electrically connected at the proximal end to a first upper channel pad at the top of the stack, and the second channel film is electrically connected at the proximal end to a second upper channel pad at the top of the stack. The first and second vertical channel films are connected at the distal ends to a lower channel pad located in the lower region of the opening. The upper and lower channel pads comprise epitaxially grown semiconductor structures with thicknesses greater than that of the vertical channel films. The conductive strips in intermediate levels in the stack can be configured as word lines. The conductive strips in a lower level in the stack can be configured as inversion assist gate lines. The lower channel pad increases the conductivity of the vertical channel structure near the lower region. Furthermore, the lower channel pad enables the inversion assist gate lines to better control the conductivity near the bottom of the vertical channel structure.

In an example described herein, the memory device comprises an array or a string of NAND memory cells at cross-points between the vertical channel structure and conductive strips in intermediate levels in the stack configured as word lines. A top frustum of the memory device includes a first switch on the first side of the opening controlled by a signal on a top conductive strip in the stack, and a second switch on the second side of the opening controlled by a signal on a top conductive strip in the stack. The first switch (e.g., GSL) can be used to connect the NAND string to a common source line, or another reference line, and the second switch (e.g., SSL) can be used to connect the NAND string to a bit line, or other line coupled to sensing circuitry. The first upper channel pad over the stack provides a better connection for the vertical channel structure and the common source line or another reference line. The second upper channel pad over the stack provides a better connection for the vertical channel structure and the bit source line or other line coupled to sensing circuitry.

DETAILED DESCRIPTION

A detailed description of embodiments of the present invention is provided with reference to theFIGS. 1-18.

FIG. 1is a schematic diagram of a three-dimensional 3D memory device100having a U-shaped thin-film structure according to a 3D vertical channel technology as described in U.S. Pat. No. 9,524,980, showing connection techniques applied to thin-channel films in vertical channel structures of the prior art.

The memory device100includes an insulating substrate101. A plurality of conductive layers on the insulating substrate101includes openings that form a plurality of stacks of conductive strips, including at least a top plane of conductive strips (ground select lines or GSLs, and string select lines or SSLs), a plurality of intermediate planes of conductive strips (world lines or WLs), and a bottom plane of conductive strips (assisted gate or AG). In the example shown inFIG. 1, a first stack102includes a bottom plane of conductive strips (AG), a plurality of intermediate planes of conductive strips (WLs), and a top plane of conductive strips (GSL). A second stack104includes a bottom plane of conductive strips (AG), a plurality of intermediate planes of conductive strips (WLs), and a top plane of conductive strips (SSL). Adjacent word lines in the first stack102and the second stack104are connected to separate bias circuits (not shown) so that two charge storage sites at the frustum of each vertical channel structure between the adjacent word lines can be separately accessed and used for data storage.

A u-shaped thin-film structure170is disposed between the first stack102and the second stack104, and can comprise semiconductor materials adapted to act as channels for the memory cells. In the illustrated example, a plurality of patterned conductor layers, such as the bit line160and the common source line140, are arranged orthogonally over the first and second stacks, and are connected to the plurality of first and second stacks, including the upper regions of the u-shaped thin-film structure170through interlayer connectors161. The interlayer connectors161in this example comprise a semiconductor, such as polysilicon, formed by deposition in vias over the thin-film semiconductor used in formation of the vertical channel films. Thus, precise alignment of the vias used to form the connectors161is needed. Also an etch process to form the vias must avoid damage to the thin film on top of the stacks. Other difficulties can arise in establishing quality contacts.

The memory device includes data storage structures in interface regions at cross-points180between sidewalls of the first and second conductive strips in the plurality of intermediate planes (WLs) in the stacks and the u-shaped thin-film structure170. The memory layer can include a multilayer data storage structure, known from flash memory technologies, including for example flash memory technologies known as ONO (oxide-nitride-oxide), ONONO (oxide-nitride-oxide-nitride-oxide), SONOS (silicon-oxide-nitride-oxide-silicon), BE-SONOS (bandgap engineered silicon-oxide-nitride-oxide-silicon), TANOS (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon), and MA BE-SONOS (metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon).

A NAND string comprises the memory cells on opposing sides of the first and second stacks of conductive strips. The channel in the memory cells of the u-shaped thin-film structure170is comprised of respective thin films172,173of semiconductor material separated by a gap174which acts as an insulating structure, or as part of an insulating structure between the thin films. The gap may enclose gas175, such as gas from the atmosphere, in the chamber during formation. Thin films172,173are connected at the bottom of the active pillar, and the circuit path177illustrates the current flow for a u-shaped NAND string between the common source line140and the bit line160. The thin film at the bottom of the trench-shaped holes can have relatively high resistance, and otherwise suffer from reliability problems because of difficulty in maintaining uniformity at depth in the opening.

FIG. 2is a heuristic cross-section of a u-shaped thin-film structure250in the 3D memory device100inFIG. 1. The u-shaped thin-film structure250includes a vertical semiconductor body, including first and second vertical thin-channel films251aand251balong the length of the pillar, and is electrically connected at the bottom of the pillar. The thickness of the u-shaped thin-film structure250may be less than 20 nanometers and less than 10 nanometers for beneficial effects of thin-channel bodies in the memory cells along the entire length of the structure. A charge storage element269is disposed on each side of the pillar. The first thin-channel film251aprovides a channel body for a string select line transistor on one side and the second thin-channel film251bprovides a channel body for a ground select line transistor on the other side. The thin-channel films251a,251bare connected at the bottom of the u-shaped thin-film structure250.FIG. 2illustrates conductive strips254and255configured as a string select line and a ground select line, respectively, both in the upper level of the stacks of conductive strips. The select line conductive strips254and255can include a more highly conductive film256,257on the outside surfaces, such as a film of a metal silicide.FIG. 2also illustrates assist gate lines260and261which can be implemented as conductive strips in the stacks. The assist gate lines260,261can include more highly conductive films262on the outside surfaces, such as a film of metal silicide. Conductive strips are disposed as first and second word lines on opposing sides of the U-shaped thin-film structure250. Thus, a first word line259is disposed opposite a second word line258in the structure. Eight word line layers are illustrated in this example. The structure illustrated inFIG. 2provides memory cells270,271, having independent charge storage sites on the first and second sides of the u-shaped thin-film structure250. Also, the structure supports operating a single u-shaped NAND string extending along the opposing sides of the u-shaped thin-film structure250.

In the illustration ofFIG. 2, the thickness in the vertical dimension of the word lines, the string select lines, and the ground select lines determines the channel lengths of the string select transistor, the memory cells, and the ground select transistors. The string and ground select line conductive strips254,255in the structure ofFIG. 3have substantially greater thickness than the word line conductive strips. This greater channel length facilitates operating the string select transistor using a bias voltage on one side of the vertical channel structure which is sufficient to turn off the transistor, even when the bias voltage on the opposite side might otherwise be sufficient to turn it on.

The assist gate lines260,261in the structure illustrated inFIG. 2also have substantially greater thickness than the word lines. The region of the u-turn280in the u-shaped thin-film structure250is below the assist gate lines260,261.

A common source line structure, such as a line in a patterned metal layer, can be arranged orthogonally over the first and second stacks of conductive strips and connected to the u-shaped thin-film structure250at the landing282. A bit line structure, such as a line in a patterned metal layer, can be arranged orthogonally over the first and second stacks of conductive strips and connected to the u-shaped thin-film structure250at the landing281. Common source line landing282and bit line landing281can be formed by the thin film deposition process used to make the channel films in the u-shaped thin-film structure250, which can be less than 20 nanometers. Such thin landing pads present manufacturing problems, and can result in a poor electrical connection to the overlying patterned conductors, including the common source line or the bit line.

FIG. 3is a cross-section of a vertical channel structure550including two vertical channel films, two upper channel pads formed by selective epitaxy and a lower channel pad by selective epitaxy in a 3D memory device, according to one embodiment. The vertical channel structure550can include a first vertical channel film551band a second vertical channel film551a. The first vertical channel film551bis connected at the proximal end to a first upper channel pad582. The second vertical channel film551ais connected at the proximal end to a second upper channel pad581. The first vertical channel film551band the second vertical channel film551aare connected at the distal end to a lower channel pad580. The first upper channel pad582, the second upper channel pad581and the lower channel pad580may comprise self-aligned, epitaxially grown semiconductor structures with thicknesses greater than that of the vertical channel films. Using the self-aligned process to increase the thickness of the landing areas for the upper pads and to improve the connection structure in the lower levels of the vertical channel structure can improve the reliability and performance of the NAND strings.

A charge storage element569is disposed on each side of the pillar. The first vertical channel film551bprovides a channel body for a string select line transistor on one side and the second vertical channel film551aprovides a channel body for a ground select line transistor on the other side.

FIG. 3illustrates conductive strips554and555configured as a string select line and a ground select line, respectively, both in the upper level of the stacks of conductive strips. The select line conductive strips554and555can include a more highly conductive film556,557on the outside surfaces, such as a film of a metal silicide.FIG. 3also illustrates assist gate lines560and561which can be implemented as conductive strips in the stacks. The assist gate lines560,561can include more highly conductive films562on the outside surfaces, such as a film of metal silicide. Conductive strips are disposed as first and second word lines on opposing sides of the vertical channel structure550. Thus, a first word line559is disposed opposite a second word line558in the structure. Eight word line layers are illustrated in this example. The structure illustrated inFIG. 3provides memory cells570,571having independent charge storage sites on the first and second sides of the vertical channel structure550. Also, the structure supports operating a single u-shaped NAND string extending along the opposing sides of the vertical channel structure550.

In the illustration ofFIG. 3, the thickness in the vertical dimension of the word lines, the string select lines, and the ground select lines determines the channel lengths of the string select transistor, the memory cells, and the ground select transistors. The string and ground select line conductive strips554,555in the structure ofFIG. 3have substantially greater thickness than the word line conductive strips. The resulting greater channel length facilitates operating the string select transistor using a bias voltage on one side of the vertical channel structure which is sufficient to turn off the transistor, even when the bias voltage on the opposite side might otherwise be sufficient to turn it on. The assist gate lines560,561in the structure illustrated inFIG. 3also have substantially greater thickness than the word lines.

The first upper channel pad582over the first stack provides a better connection for the vertical channel structure550and the common source line. The second upper channel pad581over the second stack provides a better connection for the vertical channel structure550and the bit source line. The lower channel pad580at the bottom of the vertical channel structure can overlap with the assist gate lines, thereby in combination with the assist gate lines to improve the conductivity near the lower regions of the vertical channel structures.

The first vertical channel film551band the second vertical channel film551acan comprise semiconductor materials adapted to act as channels for the memory cells, such materials as Si, Ge, SiGe, GaAs, SiC, and graphene. The first upper channel pad582, the second upper channel pad581and the lower channel pad580can comprise semiconductor materials, such as Si, polysilicon, Ge, SiGe, GaAs, and SiC, that can be epitaxially grown. The first upper channel pad582, the second upper channel pad581and the lower channel pad580may further comprise a semiconductor, such as polysilicon, having a relatively high doping concentration so that they have higher conductivity than the first vertical channel film551band the second vertical channel film551a.

Therefore, 3D memory devices with vertical channel structures are disclosed, the vertical channel structures including one or more vertical channel films and at least one or more channel pads. The channel pads in the vertical channel structure may be upper channel pads or lower channel pads. The upper channel pads are connected to the vertical channel films at the proximal ends. The lower channel pads are connected to the vertical channel films at the distal ends. In some embodiments, the upper and lower channels pads may have higher doping concentrations than the vertical channel films, thereby enabling the channel pads to have a lower resistance than the vertical channel films. The upper channel pads may act as thicker, low-resistance landing pads for any patterned conductor layers over the 3D memory device. The lower channel pads located near the lower regions of the vertical channel structures may enable the assist gate lines to have better modulation of the conductivity of the lower regions. The lower channel pads may also reduce the resistance of the lower regions of the vertical channel structures due to greater doping and a more reliable formation processes.

The technology can be utilized in other vertical channel structures as well.FIG. 4is a heuristic cross-section of a vertical channel structure for a vertical NAND string including two vertical channel films, an upper channel pad and a lower channel pad in a 3D memory device, according to an alternative gate-all-around NAND string configuration. The 3D memory inFIG. 3includes a plurality of lower select lines as described herein. The vertical channel structure310is disposed in an opening that penetrates a plurality of levels, where each level includes a corresponding conductive strip (340,341,342,343,344,345,346) including strips configured as select lines (345,346) or word lines (340,341,342,343,344) separated from other conductive strips by insulating material. The conductive strips can comprise polysilicon, tungsten, or other conductive semiconductor or metal or metal alloy, a metal compound, or combinations of conductive materials, as suits a particular embodiment. The insulating material is not represented to avoid crowding in the figure. The depth of the opening in which the vertical channel structure310is implemented can be significant, such that there may be 16, 32, 64 or more levels in a given implementation.

The vertical channel structure310as illustrated in cross-section includes a first vertical channel film324on one side of the hole-shaped opening and a second vertical channel film325on the other side of the hole-shaped opening. The films324and325can comprise a single cylindrical film. Also the films324and325are connected at the top and bottom. The first vertical channel film324and the second vertical channel film325merge and overlie the stack in region348A, and act as a seed for epitaxial growth on the proximal end of upper channel pad348B. The upper channel pad348B is electrically connected to a bit line (not shown). The first vertical channel film324and the second vertical channel film325are also connected to epitaxially grown, lower channel pad349. The lower channel pad349is electrically connected to a reference line, such as a common source line (not shown).

The vertical channel films in this example comprise semiconductor materials adapted to act as channels for the memory cells, such materials as Si, Ge, SiGe, GaAs, SiC, and graphene. The upper and lower channel pad inFIG. 3can comprise semiconductor materials, such as Si, polysilicon, Ge, SiGe, GaAs, and SiC, that can be epitaxially grown. The upper and lower channel pads may further comprise a doped semiconductor, such as epitaxial silicon, having a relatively high doping concentration so that they have higher conductivity than the vertical channel films.

The 3D memory comprises a data storage layer which lines the sidewalls of the conductive strips within the opening, forming memory cells at cross-points of conductive strips used as word lines with the vertical channel structure310. The data storage layer in this example comprises a blocking dielectric layer321, a dielectric charge trapping layer322, and a tunneling dielectric layer323. Other types of data storage layers can be utilized as well.

In this embodiment, the conductive strip340in an upper level (the uppermost level in this example) is configured to be part of an upper select line, referred for the purposes of this example as a string select line SSL, for the vertical channel structure, whereby an upper select gate transistor is formed at the frustum in the cross-point of the conductive strip340and the vertical channel structure310. The conductive strip is configured to be part of a string select line by connection to electrical routing to a decoded driver circuit for controlling operation of the upper select gate. The gate dielectric for the upper select gate transistor in this example is formed by the data storage layer (321,322,323). During manufacturing or configuration of the NAND string, the data storage layer for the upper select gate transistor may be set to a low threshold state so that it acts as a switch for connecting the NAND string to the corresponding bit line. In alternative embodiments, the gate dielectric can be implemented using a single layer of oxide for example or other gate dielectric material that does not tend to store charge.

Conductive strips (341,342,343,344,345) in the intermediate levels are configured to be part of word lines. These conductive strips are configured to be part of word lines by connection to electrical routing to word line drivers. Memory cells are disposed by the structure at the frustums of the vertical channel structure310at cross-points with the conductive strips (341-344) configured to be part of word lines.

A conductive strip346in a lower level is configured to be part of a lower select line, referred to for the purposes of this example as a ground select line GSL, for the vertical channel structure, whereby a lower select gate transistor is formed at the frustum in the cross-point of the conductive strip346and the vertical channel structure310. The gate dielectric for the lower select gate transistor in this example is formed by an insulator, as illustrated, between the lower channel pad349at the bottom of the vertical channel structure and the conductive strip346. The lower select gate transistor acts as a switch for connecting the NAND string to the corresponding reference line.

FIG. 5is a cross-section of an alternative vertical channel structure450supporting even and odd NAND strings. The vertical channel structure450has memory cells on two sides, and conductive strips configured as even and odd string select lines SSLe, SSLo, even and odd ground select lines GSLe, GSLo, even word lines and odd word lines.

The vertical channel structure450inFIG. 5includes a vertical polysilicon semiconductor body including an even vertical channel film470and an odd vertical channel film469separated by a seam453. The even vertical channel film470and the odd vertical channel film469are connected at the distal end to a reference line conductor452A. Also, a lower channel pad452B comprising an epitaxial semiconductor, such as epitaxial silicon grown by self-aligned selective epitaxy as discussed above, is disposed between the even vertical channel film470and the odd vertical channel film469in the lower levels of the opening. The 3D memory device includes charge storage elements on each side of the semiconductor body, which can be continuous on the sidewalls of the stacks as shown, or separated into separate elements on the sidewalls of the conductive layers in the stacks which act as word lines.

The vertical channel structure450includes a portion providing a vertical channel body for string select line transistors adjacent the SSLe and SSLo conductive strips, and a portion which incorporates the reference conductor through the lower channel pad452B. Between the portions of the vertical channel structure which contact or incorporate the lower channel pad452B, the seam453is disposed within the vertical channel structure450between the even and odd word lines. The seam453separates the even vertical channel film470and the odd vertical channel film469bodies at the frustum of the column (e.g., at the level of even word line458and odd word line459) at which the word lines cross, in the regions of the conductive strips configured as word lines, providing thin-channel films for the memory cells.

FIG. 5illustrates conductive strips454and455configured as string select lines. The string select line conductive strips454and455can include a more highly conductive film on the outside surfaces, such as a film of a metal silicide. The channel films469and470in the vertical channel structure in this example overlie the top of the structure, forming a basis for epitaxial growth of first and second upper channel pads479and480. The first and second upper channel pads479and480can comprise epitaxial semiconductor, such as epitaxial silicon grown by self-aligned selective epitaxy as discussed above.

FIG. 5also illustrates conductive strips462,463in a lower level configured as even and odd ground select lines GSLe, GSLo. The ground select lines462,463can include more highly conductive films on the outside surfaces, such as a film of metal silicide. Likewise, conductive strips in intermediate levels are disposed as even and odd word lines on opposing sides of the vertical channel structure450. Thus, an even word line458is disposed opposite an odd word line459in the structure. A smaller or larger number of word line layers, such as 4, 16, 32, or more can be utilized. Also, in some embodiments, dummy word lines may be included, in addition to those used for actual data storage. In other embodiments, all or some of the string select lines, word lines and ground select lines are implemented using metal, or other conductive material, rather than polysilicon.

The structure illustrated inFIG. 5comprises first and second NAND strings on opposing sides of the vertical channel structure450. Using the structure ofFIG. 5, a memory device is provided, comprising a plurality of stacks of conductive strips, the plurality of stacks including even stacks and odd stacks; a plurality of vertical channel structures arranged between corresponding even and odd stacks of conductive strips in the plurality of stacks with even and odd upper channel pads, vertical channel structures in the plurality comprising even and odd vertical thin-channel films, and lower channel pads.

The even and odd vertical channel films inFIG. 5can comprise semiconductor materials adapted to act as channels for the memory cells, such materials as Si, Ge, SiGe, GaAs, SiC, and graphene.

FIGS. 6 through 14illustrate an example process flow for a 3D memory device with vertical channel films and channel pads for a structure like that ofFIG. 3.

FIG. 6illustrates a stage of the process flow after forming a plurality of conductive layers on top of an insulating layer605which can comprise silicon oxide or another dielectric on a semiconductor substrate. To form the structure shown inFIG. 6, a plurality of layers610,620,630,640,650of a first conductive material, such as doped polysilicon, or other material suitable for use as word lines, separated by layers615,625,635,645,655of insulating material, are disposed over the insulating layer605. A top layer665of silicon nitride is disposed on the plurality of conductive and insulating layers. In embodiments described herein, the conductive material can be a heavily p-type doped polysilicon (P+ polysilicon) or other material selected for compatibility with the data storage structures. The layer of silicon nitride can be used to provide tensile stress. The silicon nitride layer can improve the uniformity of the stacks and reduce bending during high aspect ratio etching. The layers of insulating material can comprise silicon dioxide deposited in a variety of ways as known in the art. Also, the layers of insulating material can comprise other insulating materials, and combinations of insulating materials. In this example, all of the insulating layers, with the exception of the top layer665, consist of the same material. In other examples, different materials can be used in different layers as suits a particular design goal. After the plurality of layers is formed, a patterned etch is applied to form a plurality of stacks of conductive strips and openings.

FIG. 7illustrates a stage of the process after etching the plurality of layers, and stopping below the top surface of the insulating layer605to define a plurality of stacks of conductive strips, including stacks702,704and706. The stacks702,704and706include at least a lower (e.g. bottom) level (AG) of conductive strips610, a plurality of intermediate levels (WLs)620,630,640of conductive strips, and an upper (e.g. top) level650of conductive strips (SSL/GLS) as labeled in stack706. A top layer660of silicon nitride strips is disposed on each stack. The stacks702,704and706include layers615,625,635,645,655of insulating material separating the conductive strips from one another.

The etching process further defines openings710and720. The opening may be a trench or a hole. For the purpose of this application, a process flow is shown where the etching process defines one or more trenches. However, the technology disclosed herein can also be formed in a hole opening. In the example illustrated inFIG. 7, the opening may be for example 70 to 120 nm wide.

FIG. 8illustrates a stage of the process flow after forming a memory layer812over and on sides of conductive strips in the plurality of stacks. The memory layer contacts side surfaces of the plurality of conductive strips. The memory layer can comprise a multilayer data storage structure including a tunneling layer, a charge storage layer, and a blocking layer, examples of which are discussed above.

FIG. 9illustrates a stage of the process flow after forming a first semiconductor layer912over and having a surface conformal with the memory layer on the plurality of stacks. In the dielectric charge storage embodiment, the first semiconductor layer912contacts the memory layer812at least in the regions in which memory cells are being formed. The semiconductor material in the first semiconductor layer912comprises a semiconductor adapted by choice of material, e.g., silicon, and doping concentrations (e.g., undoped or lightly doped) to act as channel regions for vertical strings of memory cells, at least in the regions between the stacks so as to form channel films on the sidewalls of the opening. The first semiconductor layer912can have a thickness of about 10 nanometers or less. As illustrated inFIG. 9, in the regions between the stacks, the first semiconductor layer912extends to the bottom of the openings between the stacks, and overlies the memory layer812.

FIG. 10illustrates a stage in the process flow after performing a step to form masks1012on the sidewalls of the stacks next to the first semiconductor layer912. The masks1012may comprise an oxide, e.g., silicon oxide, or a semiconductor, e.g., silicon nitride suitable to act as a mask during epitaxial growth. The masks1012may be formed by depositing a layer of silicon oxide or silicon nitride over and having a surface conformal with the first semiconductor layer on the plurality of stacks, followed by a spacer etch (anisotropic etch) to form a spacer structure on the sidewall. The spacer structures form the masks1012, exposing areas1002,1004,1006,1008,1010to expose seed layer for self-aligned epitaxial growth to form semiconductor pads.

FIG. 11illustrates a stage in the process after growing semiconductor pads on the areas1002,1004,1006,1008and1010exposed by the masks1012. The semiconductor pads1102,1104,1106,1108and1110are grown through a self-aligned, selective epitaxy of silicon seeded by the semiconductor layer912in the exposed areas1002,1004,1006,1008and1010. Selective epitaxial growth is a technique for epitaxially growing a semiconductor material on a semiconductor substrate in a desired, seeded area. The desired, seeded areas are generally exposed by dielectric masks. Semiconductor growth conditions are selected to ensure epitaxial growth on the exposed areas, but not on the dielectric masks. Epitaxial growth is initiated selectively in the seed windows on the exposed areas. The growth is referred to as Selective Epitaxial Growth (SEG).

In one embodiment, the semiconductor pads may have thicknesses greater than 20 nanometers and can be for example between 20 and 150 nanometers, and preferably 40 to 70 nanometers after SEG. The thicknesses of the upper pads can be different than the thickness of the lower pads due to the dynamics of SEG on the upper surface as compared to deep in the opening. In one embodiment, the semiconductor pads may comprise semiconductor materials, such as Si, polysilicon, Ge, SiGe, GaAs, and SiC, that can be epitaxially grown. In one embodiment, the semiconductor pads may comprise a semiconductor, such as polysilicon, having a relatively high doping concentration so that they have higher conductivity than the first semiconductor layer912.

FIG. 12illustrates a stage in the process flow after the masks1012are removed, resulting in gaps1202between the semiconductor pads1108,1110and the first semiconductor layer912. In one embodiment, the masks1012may be removed by wet etching with hydrofluoric acid or phosphoric acid.

FIG. 13illustrates a stage in the process flow after a second semiconductor layer1302is deposited over and having a surface conformal with semiconductor pads1102,1104,1106,1108,1110and the first semiconductor layer912. Depositing the second semiconductor layer1302fills the gaps1202created after the masks are removed. The second semiconductor layer1302can have a thickness of about 10 nanometers or less. The semiconductor material in the second semiconductor layer1302comprises a semiconductor adapted by choice of material, e.g., silicon, and doping concentrations (e.g., undoped or lightly doped) to act as channel regions for vertical strings of memory cells.

The structure inFIG. 13may be further annealed to connect and improve the electrical conductance between the semiconductor pads1102,1104,1106,1108,1110, the first semiconductor layer912and the second semiconductor layer1302, and form a vertical channel structure.

FIG. 14illustrates a stage in the process flow after annealing. The structure comprises a vertical channel structure including vertical channel films1402and1404disposed on the sidewalls of the stacks. The vertical channel film1402is connected at the proximal end to a first upper channel pad1406. The vertical channel film1404is connected at the proximal end to a second upper channel pad1408. The vertical channel films1402and1404are connected at the distal ends to a lower channel pad1410.

The structure inFIG. 14may be further processed to form 3D memory devices as illustrated by FIGS. 11-18 in U.S. Pat. No. 9,524,980, which is incorporated by reference as if fully set forth herein. The openings between stacks are filled on the inside surfaces of the channel structure with an insulating material such as silicon dioxide. In one embodiment, an air gap may be left at least in regions adjacent the intermediate layers of conductive strips. After the filling step, pillars may be etched between the stacks to form a plurality of vertical channel structures in a honeycomb arrangement, so that each row of vertical channel structures is offset in the row direction from adjacent rows. This honeycomb arrangement facilitates the formation of overlying bit lines with a tighter pitch. The structure is then etched to form arrays of first stacks and second stacks, connected by vertical channel structures. The upper channel pads of the vertical channel structures provide thicker landing areas for interlayer connectors for connection to a common source line and the bit line. An array of contact plugs, which can be metal contact plugs, including tungsten plugs, are then formed along with a first patterned conductor layer including conductor lines connected to the GSL sides of the NAND strings (operated as common source lines) and a second patterned conductor layer including bit lines connected to the SSL sides of the NAND strings (operated as bit lines).

FIG. 15is a simplified perspective diagram of a 3D memory device1500including vertical channel structures as described herein. The memory device1500includes an array of NAND strings of memory cells. The memory device1500includes an integrated circuit substrate1501, and a plurality of stacks of conductive strips separated by insulating material, including at least a top level of conductive strips (ground select lines or GSLs, and string select lines or SSLs), a plurality of intermediate levels of conductive strips (world lines or WLs), and a bottom level of conductive strips (assisted gate or AG). In the example shown inFIG. 15, a first stack1502includes a bottom level of conductive strips (AG), a plurality of intermediate levels of conductive strips (WLs), and a top level of conductive strips (GSL). A second stack1504includes a bottom level of conductive strips (AG), a plurality of intermediate levels of conductive strips (WLs), and a top level of conductive strips (SSL). Adjacent word lines in the first stack1502and the second stack1504are connected to separate bias circuits (not shown), so that two charge storage sites at the frustum of each vertical channel structure between the adjacent word lines can be separately accessed and used for data storage. This arrangement of independent word lines can be implemented for example by connecting first stack word lines to a first bias structure, and second stack of word lines to a separate bias structure, examples of which are described below.

The conductive strips acting as word lines, string select lines, ground select lines and an assisted gate can comprise a variety of materials including doped semiconductors, metals, and conductive compounds, including materials comprising Si, Ge, SiGe, SiC, TiN, TaN, W, and Pt.

A vertical channel structure1570is disposed between the first stack1502and the second stack1504. The vertical channel structure1570comprises vertical channel films1572and1573disposed on the sidewalls of the first stack1502and the second stack1504, respectively. The vertical channel films1572and1573are connected to a first upper channel pad1591at the top of the first stack1502and to a second upper channel pad1592at the top of the second stack1504. Both the vertical channel films1572and1573are connected at the distal ends to a lower channel pad1593.

In the illustrated example, a plurality of bit line structures1560and a plurality of common source line structures1540are arranged orthogonally over the first and second stacks, and are connected to the plurality of first and second stacks through the first upper channel pad1591and the second upper channel pad1592of the vertical channel structure1570and interlayer connectors1561.

The memory device includes memory layers, such as data storage structures, in interface regions at cross-points1580between side surfaces of the first and second conductive strips in the plurality of intermediate planes (WLs) in the stacks and the vertical channel structure1570. The memory layer can include a multilayer data storage structure, known from flash memory technologies, including for example flash memory technologies known as ONO (oxide-nitride-oxide), ONONO (oxide-nitride-oxide-nitride-oxide), SONOS (silicon-oxide-nitride-oxide-silicon), BE-SONOS (bandgap engineered silicon-oxide-nitride-oxide-silicon), TANOS (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon), and MA BE-SONOS (metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon).

In a representative device, the dielectric layer of memory material can include a bandgap engineered composite tunneling dielectric layer comprising a layer of silicon dioxide1530less than 2 nm thick, a layer of silicon nitride1531less than 3 nm thick, and a layer of silicon dioxide1532less than 4 nm thick. In one embodiment, the composite tunneling dielectric layer consists of an ultrathin silicon oxide layer O1(e.g., <=15 Å), an ultrathin silicon nitride layer N1(e.g. <=30 Å) and an ultrathin silicon oxide layer O2(e.g. <=35 Å), which results in an increase in the valence band energy level of about 2.6 eV at an offset 15 Å or less from the interface with the semiconductor body. The O2layer separates the N1layer from the charge trapping layer, at a second offset (e.g., about 30 Å to 45 Å from the interface), by a region of lower valence band energy level (higher hole tunneling barrier) and higher conduction band energy level. The electric field sufficient to induce hole tunneling raises the valence band energy level after the second location to a level that effectively eliminates the hole tunneling barrier because the second location is at a greater distance from the interface. Therefore, the O2layer does not significantly interfere with the electric field assisted hole tunneling, while improving the ability of the engineered tunneling dielectric to block leakage during low fields. These layers can be conformally deposited using for example LPCVD. A charge trapping layer in the layer of memory material in one embodiment comprises silicon nitride having a thickness greater than 50 Å, including for example about 70 Å. Other charge trapping materials and structures may be employed, including for example silicon oxynitride (SixOyNz), silicon-rich nitride, silicon-rich oxide, trapping layers including embedded nano-particles and so on. The blocking dielectric layer of memory material in one embodiment comprises a layer of silicon dioxide having a thickness greater than 50 Å, including for example about 90 Å, and can be formed by LPCVD or another wet conversion from the nitride by a wet furnace oxidation process. Other blocking dielectrics can include high-κ materials like aluminum oxide.

In the illustrated example, the memory cells in the cross-points1580on the opposing sides of the first and second stacks of conductive strips are configured in a NAND string. The NAND string can be operated for read, erase and program operations. A circuit path1577illustrates the current flow for the NAND string which is connected to the common source line structures1540and the bit line structures1560, through the first upper channel pad1591, the vertical channel film1572, the lower channel pad1593, the vertical channel film1573, and the second upper channel pad1592. The first upper channel pad1591over the first stack provides a better connection for the vertical channel structure1570and the common source line structure1540. The second upper channel pad1592over the second stack provides a better connection for the vertical channel structure1570and the bit line structures1560. The lower channel pad1593in the lower region of the vertical channel structure1570overlaps with the assist gate lines, thereby enabling the assist gate lines to have increased control of the conductivity near the lower regions of the vertical channel structures.

FIG. 16is a perspective view of a lower region of the channel structure1570in the 3D memory device1500as described herein. The embodiment illustrated inFIG. 16includes the vertical channel film1572and the vertical channel film1573. The vertical channel films are preferably thin-films, having thicknesses of 20 nm or less. The vertical channel films are connected to a lower channel pad1593with an upper surface1616and a lower surface1618. A first side stack of semiconductor strips includes strip1631which can be configured as an assist gate line. The first assist gate line1631has an upper surface1631aand a lower surface1631b. A second side stack of semiconductor strips includes strip1611which can also be configured as an assist gate line. The second assist gate line1611has an upper surface1611aand a lower surface1611b. The upper surface1616of the lower channel pad1593is above the lower surface1631bof the first assist gate line1631and the lower surface1611bof the second assist gate line1611. The lower surface1618of the lower channel pad1593is below the lower surface1631bof the first assist gate line1631and the lower surface1611bof the second assist gate line1611. Therefore, the resistance of the lower region of the channel structure1570can be controlled by the first assist line1631and the second assist line16111during the read operation of the memory cells due to their overlap with the lower channel pad1593. Switching the assist lines1631and1611will enable the lower region of the channel structure1570to have a low resistance during the read operation. In some embodiments, the lower channel pad1593may comprise a semiconductor material with higher doping than that found in the vertical channel films1572and1573. Therefore, the lower channel pad1593may have a higher conductivity when compared to the conductivities of the vertical channel films1572,1573.

FIG. 17is a flowchart illustrating a method for manufacturing a 3D memory with vertical channel films and channel pads as described herein. The method includes identifying areas on a substrate for formation of a vertical channel structure having a structure like that ofFIG. 14. For each area, the method includes forming an insulating layer on the substrate by, for example, depositing a layer of silicon dioxide, or other dielectric material or combination of materials on the substrate (step1701). Over the insulating layer (e.g.,605inFIG. 6), the process includes forming a plurality of layers of a first conductive material, suitable to act as word lines, separated by insulating material (step1702), and etching the plurality of layers to define a plurality of stacks (e.g.,702,704,706inFIG. 7) of conductive strips and a plurality of openings (e.g.,710,720inFIG. 7) (step1703). The stacks can include at least a bottom plane (assist gates) of conductive strips, a plurality of intermediate planes (WLs) of conductive strips, and a top plane of conductive strips (SSLs and GSLs).

The method includes forming a memory layer (e.g.,812inFIG. 8) on side surfaces of conductive strips in the plurality of stacks to provide data storage structures (step1703). The memory layer can comprise a dielectric charge trapping layer and are in contact with the side surfaces of the plurality of conductive strips.

The method includes forming a first semiconductor layer (e.g.,912inFIG. 9) over and having a surface conformal with the memory layer on the plurality of stacks (step1704). The first semiconductor layer extends down the sidewalls of the trenches between the stacks, and over the bottom of the openings.

A thin layer of silicon oxide or silicon nitride is deposited and then etched to form masks (e.g.,1012inFIG. 10) on the first semiconductor layer on the sidewalls of adjacent stacks (step1705). The masks expose areas for the growth of semiconductor pads.

Then, the semiconductor pads are grown by SEG in the areas exposed by the masks as discussed with reference toFIG. 11(step1706). The semiconductor pads may have a higher N+ doping than the first semiconductor layer. The mask is then removed (step1707) and a second semiconductor layer (1302inFIG. 13) is deposited (step1708) as discussed above with reference toFIG. 12andFIG. 13. The first semiconductor layer, the second semiconductor pads, and the second semiconductor are then annealed (step1709) to form a vertical channel structure. The vertical channel structure comprises vertical channel films (e.g.,1402and1404inFIG. 14) disposed on the sidewalls of the first and second stacks. The vertical channel films are connected at the proximal end to a first upper channel pad (e.g.,1406inFIG. 14) and a second upper channel pad (e.g.,1408inFIG. 14), and at the distal end to a lower channel pad (e.g.,1410inFIG. 14).

FIG. 18is a simplified chip block diagram of an integrated circuit1801including a 3D NAND array with vertical channel films and channel pads. The integrated circuit1801includes a memory array1860including one or more memory blocks as described herein with vertical channel structures comprising vertical channel films and channel pads on an integrated circuit substrate.

An SSL/GSL decoder1840is coupled to a plurality of SSL/GSL lines1845, arranged in the memory array1860. A first/second level decoder1850is coupled to a plurality of first/second word lines1855. A global bit line column decoder1870is coupled to a plurality of global bit lines1865arranged along columns in the memory array1860for reading data from and writing data to the memory array1860. Addresses are supplied on bus1830from control logic1810to decoder1870, decoder1840and decoder1850. Sense amplifier and program buffer circuits1880are coupled to the column decoder1870, in this example via first data lines1875. The program buffer in circuits1880can store program data to indicate program or inhibit states for selected bit lines. The column decoder1870can include circuits for selectively applying program and inhibit voltages to bit lines in the memory in response to the data values in the program buffer.

Sensed data from the sense amplifier/program buffer circuits are supplied via second data lines1885to multi-level data buffer1890, which is in turn coupled to input/output circuits1891via a data path1893. Also, input data is applied in this example to the multi-level data buffer1890for use in support of multiple-level program operations for each of the independent sides of the independent double gate cells in the array.

Input/output circuits1891drive the data to destinations external to the integrated circuit1801. Input/output data and control signals are moved via data bus1805between the input/output circuits1891, the control logic1810and input/output ports on the integrated circuit1801or other data sources internal or external to the integrated circuit1801, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the memory array1860.

In the example shown inFIG. 18, control logic1810, using a bias arrangement state machine, controls the application of supply voltages generated or provided through the voltage supply or supplies in block1820, such as read, erase, verify and program bias voltages. The control logic1810is coupled to the multi-level data buffer1890and the memory array1860. The control logic1810includes logic to control multiple-level program operations. In embodiments supporting the vertical NAND structures described herein, the logic is configured to perform the method of: (i) selecting a layer of memory cells in the array, such as using a word line layer decoder; (ii) selecting a side of the vertical channel structures in the selected layer such as by selecting a second or first side word line structure; (iii) selecting vertical channel structures in a selected row in the array such as by using SSL switches and GSL switches on the rows of vertical channel structures; and (iv) storing charge in charge trapping sites in the selected layer on the selected side of vertical channel structures in one or more selected columns in the array, to represent data using bit line circuitry like page buffers on global bit lines coupled to the selected row of vertical channel structures.

In some embodiments, the logic is configured to select a layer and select a side by selecting one of second and first interdigitated word line structures in the selected layer of the array, such as by controlling the second and first word line layer decoders.

In some embodiments, the logic is configured to store multiple levels of charge to represent more than one bit of data in the charge trapping sites in the selected layer on the selected side. In this manner, a selected cell in a selected frustum of a vertical channel structure in the array stores more than two bits, including more than one bit on each side of the cell. Also, single-bit-per-cell embodiments can include the structures described herein.

The control logic1810can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the control logic comprises a general-purpose processor, which can be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor can be utilized for implementation of the control logic.