SEMICONDUCTOR DIE PACKAGE AND METHODS OF FORMATION

A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.

BACKGROUND

Various semiconductor device packing techniques may be used to incorporate one or more semiconductor dies into a semiconductor device package. In some cases, semiconductor dies may be stacked in a semiconductor device package to achieve a smaller horizontal or lateral footprint of the semiconductor device package and/or to increase the density of the semiconductor device package. Semiconductor device packing techniques that may be performed to integrate a plurality of semiconductor dies in a semiconductor device package may include integrated fanout (InFO), package on package (PoP), chip on wafer (CoW), wafer on wafer (WoW), and/or chip on wafer on substrate (CoWoS), among other examples.

DETAILED DESCRIPTION

In a wafer on wafer (WoW) semiconductor die package, semiconductor dies are directly bonded such that the semiconductor dies are vertically arranged in the WoW semiconductor die package. The use of direct bonding and vertical stacking of dies may reduce interconnect lengths between the semiconductor dies (which reduces power loss and signal propagation times) and may enable increased density of semiconductor die packages in a semiconductor device package that includes the WoW semiconductor die package.

Through silicon via (TSV) structures may be included in a WoW semiconductor die package. A TSV structure is an elongated conductive structure that extends through a silicon substrate (e.g., a device region) of one or more of the semiconductor dies of the WoW semiconductor die package. A TSV structure may enable a back end of line (BEOL) region of one or more of the semiconductor dies to be electrically connected to a redistribution structure (and to external electrically connectors) of the WoW semiconductor die package.

In some cases, a TSV structure may be located near a semiconductor device (e.g., a transistor or another type of semiconductor device) included in a silicon substrate of a semiconductor die of a WoW semiconductor die package. In particular, the TSV structure may extend through one or more types of doped wells (e.g., a p-doped well, an n-doped well) included in the silicon substrate in which the semiconductor device is included.

Forming the TSV structure through a doped well may include etching the silicon substrate to form a recess through the doped well, and depositing one or more conductive materials in the recess to form the TSV structure. In some cases, the etch operation to form the recess may result in the formation of dangling bonds in the surface of the silicon substrate in the doped well. These dangling bonds may act as charge trapping states, which may cause a trap-assist tunnel (TAT) to form in the silicon substrate. In particular, if the doped well is located adjacent to another doped well of opposite dopant type, the formation of trap-assist tunnels may result in current leakage between the doped well and the adjacent doped well. The current leakage may result in current leakage in a semiconductor device that is formed in the doped well and the adjacent doped well, which may lead to reduced performance for the semiconductor device and/or failure of the semiconductor device. Current leakage may become an increasing occurrence as the pitch or distance between semiconductor devices and TSV structures in WoW semiconductor die packages is decreased so that increased semiconductor device density in the WoW semiconductor die packages can be achieved.

In some implementations described herein, a semiconductor die package (e.g., a WoW semiconductor die package) includes a high dielectric constant (high-k) dielectric layer over a device region (e.g., a silicon substrate) of a first semiconductor die that is bonded with a second semiconductor die in a WoW configuration. A TSV structure (e.g., a backside TSV (BTSV) structure) may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the negative charges (e.g., electron carriers) in the high-k dielectric layer attracts hole charge carriers in the device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Therefore, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die. This may increase the performance of the semiconductor devices and/or may enable the semiconductor devices to be placed closer together and closer to the TSV structure, which enables reduced semiconductor device pitch and increased semiconductor device density in the first semiconductor die, among other examples.

FIG.1is a diagram of an example environment100in which systems and/or methods described herein may be implemented. As shown inFIG.1, the example environment100may include a plurality of semiconductor processing tools102-114and a wafer/die transport tool116. The plurality of semiconductor processing tools102-112may include a deposition tool102, an exposure tool104, a developer tool106, an etch tool108, a planarization tool110, a plating tool112, a bonding tool114, and/or another type of semiconductor processing tool. The tools included in example environment100may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and/or manufacturing facility, among other examples.

The deposition tool102is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some implementations, the deposition tool102includes a spin coating tool that is capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, the deposition tool102includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some implementations, the deposition tool102includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the deposition tool102includes an epitaxial tool that is configured to form layers and/or regions of a device by epitaxial growth. In some implementations, the example environment100includes a plurality of types of deposition tools102.

The developer tool106is a semiconductor processing tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool104. In some implementations, the developer tool106develops a pattern by removing unexposed portions of a photoresist layer. In some implementations, the developer tool106develops a pattern by removing exposed portions of a photoresist layer. In some implementations, the developer tool106develops a pattern by dissolving exposed or unexposed portions of a photoresist layer through the use of a chemical developer.

The etch tool108is a semiconductor processing tool that is capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etch tool108may include a wet etch tool, a dry etch tool, and/or the like. In some implementations, the etch tool108includes a chamber that is filled with an etchant, and the substrate is placed in the chamber for a particular time period to remove particular amounts of one or more portions of the substrate. In some implementations, the etch tool108may etch one or more portions of the substrate using a plasma etch or a plasma-assisted etch, which may involve using an ionized gas to isotropically or directionally etch the one or more portions.

The planarization tool110is a semiconductor processing tool that is capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, a planarization tool110may include a chemical mechanical planarization (CMP) tool and/or another type of planarization tool that polishes or planarizes a layer or surface of deposited or plated material. The planarization tool110may polish or planarize a surface of a semiconductor device with a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). The planarization tool110may utilize an abrasive and corrosive chemical slurry in conjunction with a polishing pad and retaining ring (e.g., typically of a greater diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head may rotate with different axes of rotation to remove material and even out any irregular topography of the semiconductor device, making the semiconductor device flat or planar.

The plating tool112is a semiconductor processing tool that is capable of plating a substrate (e.g., a wafer, a semiconductor device, and/or the like) or a portion thereof with one or more metals. For example, the plating tool112may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and/or the like) electroplating device, and/or an electroplating device for one or more other types of conductive materials, metals, and/or similar types of materials.

The bonding tool114is a semiconductor processing tool that is capable of bonding two or more work pieces (e.g., two or more semiconductor substrates, two or more semiconductor devices, two or more semiconductor dies) together. For example, the bonding tool114may include a hybrid bonding tool. A hybrid bonding tool is a type of bonding tool that is configured to bond semiconductor dies together directly through copper-to-copper (or other direct metal) connections. As another example, the bonding tool114may include a eutectic bonding tool that is capable of forming a eutectic bond between two or more wafers together. In these examples, the bonding tool114may heat the two or more wafers to form a eutectic system between the materials of the two or more wafers.

Wafer/die transport tool116includes a mobile robot, a robot arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated materially handling system (AMHS), and/or another type of device that is configured to transport substrates and/or semiconductor devices between semiconductor processing tools102-114, that is configured to transport substrates and/or semiconductor devices between processing chambers of the same semiconductor processing tool, and/or that is configured to transport substrates and/or semiconductor devices to and from other locations such as a wafer rack, a storage room, and/or the like. In some implementations, wafer/die transport tool116may be a programmed device that is configured to travel a particular path and/or may operate semi-autonomously or autonomously. In some implementations, the example environment100includes a plurality of wafer/die transport tools116.

For example, the wafer/die transport tool116may be included in a cluster tool or another type of tool that includes a plurality of processing chambers, and may be configured to transport substrates and/or semiconductor devices between the plurality of processing chambers, to transport substrates and/or semiconductor devices between a processing chamber and a buffer area, to transport substrates and/or semiconductor devices between a processing chamber and an interface tool such as an equipment front end module (EFEM), and/or to transport substrates and/or semiconductor devices between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some implementations, a wafer/die transport tool116may be included in a multi-chamber (or cluster) deposition tool102, which may include a pre-clean processing chamber (e.g., for cleaning or removing oxides, oxidation, and/or other types of contamination or byproducts from a substrate and/or semiconductor device) and a plurality of types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations). In these implementations, the wafer/die transport tool116is configured to transport substrates and/or semiconductor devices between the processing chambers of the deposition tool102without breaking or removing a vacuum (or an at least partial vacuum) between the processing chambers and/or between processing operations in the deposition tool102.

In some implementations, one or more of the semiconductor processing tools102-116and/or the wafer/die transport tool116may perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools102-114and/or the wafer/die transport tool116may bond a first semiconductor die and a second semiconductor die at a bonding interface, where the bonding interface is located on a first side of the second semiconductor die; may form a high-k dielectric layer over a second side of the second semiconductor die opposing the first side, where the high-k dielectric layer has a negative charge polarity; may form, from the second side of the second semiconductor die, a recess through the high-k dielectric layer, through a device region of the second semiconductor die, and into a portion of an interconnection region of the second semiconductor die to expose a portion of a metallization layer in the interconnection region; and/or may form a BTSV structure in the recess.

The number and arrangement of devices shown inFIG.1are provided as one or more examples. In practice, there may be additional devices, fewer devices, different devices, or differently arranged devices than those shown inFIG.1. Furthermore, two or more devices shown inFIG.1may be implemented within a single device, or a single device shown inFIG.1may be implemented as multiple, distributed devices. Additionally, or alternatively, a set of devices (e.g., one or more devices) of the example environment100may perform one or more functions described as being performed by another set of devices of the example environment100.

FIG.2is a diagram of an example semiconductor die package200described herein. The semiconductor die package200includes an example of a wafer on wafer (WoW) semiconductor die package or another type of semiconductor die package in which semiconductor dies are directly bonded and vertically arranged or stacked.

As shown inFIG.2, the semiconductor die package200includes a first semiconductor die202and a second semiconductor die204. In some implementations, the semiconductor die package200includes additional semiconductor dies. The first semiconductor die202may include an SoC die, such as a logic die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a digital signal processing (DSP) die, an application specific integrated circuit (ASIC) die, and/or another type of SoC die. Additionally and/or alternatively, the first semiconductor die202may include a memory die, an input/output (I/O) die, a pixel sensor die, and/or another type of semiconductor die. A memory die may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, a NAND die, a high bandwidth memory (HBM) die, and/or another type of memory die. The second semiconductor204may include the same type of semiconductor die as the first semiconductor die202, or may include a different type of semiconductor die.

The first semiconductor die202and the second semiconductor die204may be bonded together (e.g., directly bonded) at a bonding interface206. In some implementations, one or more layers may be included between the first semiconductor die202and the second semiconductor die204at the bonding interface206, such as one or more passivation layers, one or more bonding films, and/or one or more layers of another type. In some implementations, a thickness of the second semiconductor die204is included in a range of approximately 0.5 microns to approximately 5 microns. However, other values for the range are within the scope of the present disclosure.

The first semiconductor die202may include a device region208and an interconnect region210adjacent to and/or above the device region208. In some implementations, the first semiconductor die202may include additional regions. Similarly, the second semiconductor die204may include a device region212and an interconnect region214adjacent to and/or below the device region212. In some implementations, the second semiconductor die204may include additional regions. The first semiconductor die202and the second semiconductor die204may be bonded at the interconnect region210and the interconnect region214. The bonding interface206may be located at a first side of the interconnect region214facing the interconnect region210and corresponding to a first side of the second semiconductor die204.

The device regions208and212may each include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon on insulator (all) substrate, a germanium substrate (Ge), a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate. The device region212may include one or more semiconductor devices216included in the silicon substrate of the device region212. The device region208may include one or more semiconductor devices218included in the silicon substrate of the device region208. The semiconductor devices216and218may each include one or more transistors (e.g., planar transistors, fin field effect transistors (FinFETs), nanosheet transistors (e.g., gate all around (GAA) transistors), memory cells, capacitors, inductors, resistors, pixel sensors, and/or another type of semiconductor devices.

The interconnect regions210and214may be referred to as BEOL regions. The interconnect region210may include one or more dielectric layers220, which may include a silicon nitride (SiNx), an oxide (e.g., a silicon oxide (SiOx) and/or another oxide material), a low dielectric constant (low-k) dielectric material, and/or another type of dielectric material. In some implementations, one or more etch stop layers (ESLs) may be included in between layers of the one or more dielectric layers220. The one or more ESLs may include aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (SiN), silicon oxynitride (SiOxNy), aluminum oxynitride (AlON), and/or a silicon oxide (SiOx), among other examples.

The interconnect region210may further include metallization layers222in the one or more dielectric layers220. The semiconductor devices218in the device region208may be electrically connected and/or physically connected with one or more of the metallization layers222. The metallization layers222may include conductive lines, trenches, vias, pillars, interconnects, and/or another type of metallization layers. Contacts224may be included in the one or more dielectric layers220of the interconnect region210. The contacts224may be electrically connected and/or physically connected with one or more of the metallization layers222. The contacts224may include conductive terminals, conductive pads, conductive pillars, and/or another type of contacts. The metallization layers222and the contacts224may each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and/or another type of conductive materials.

The interconnect region214may include one or more dielectric layers226, which may include a silicon nitride (SiNx), an oxide (e.g., a silicon oxide (SiOx) and/or another oxide material), a low dielectric constant (low-k) dielectric material, and/or another type of dielectric material. In some implementations, one or more etch stop layers (ESLs) may be included in between layers of the one or more dielectric layers226. The one or more ESLs may include aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (SiN), silicon oxynitride (SiOxNy), aluminum oxynitride (AlON), and/or a silicon oxide (SiOx), among other examples.

The interconnect region214may further include metallization layers228in the one or more dielectric layers226. The semiconductor devices216in the device region212may be electrically connected and/or physically connected with one or more of the metallization layers228. The metallization layers228may include conductive lines, trenches, vias, pillars, interconnects, and/or another type of metallization layers. Contacts230may be included in the one or more dielectric layers226of the interconnect region214. The contacts230may be electrically connected and/or physically connected with one or more of the metallization layers228. Moreover, the contacts230may be electrically and/or physically connected with the contacts224of the first semiconductor die202. The contacts230may include conductive terminals, conductive pads, conductive pillars, UBM structures, and/or another type of contacts. The metallization layers228and the contacts230may each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and/or another type of conductive materials.

As further shown inFIG.2, the semiconductor die package200may include a redistribution structure232. The redistribution structure232may include a redistribution layer (RDL) structure and/or another type of redistribution structure. The redistribution structure232may be configured to fan out and/or route signals and I/O of the semiconductor dies202and204.

The redistribution structure232may include one or more dielectric layers234and a plurality of metallization layers236disposed in the one or more dielectric layers234. The dielectric layer(s)234may include a silicon nitride (SiNx), an oxide (e.g., a silicon oxide (SiOx) and/or another oxide material), a low dielectric constant (low-k) dielectric material, and/or another suitable dielectric material.

The metallization layers236of the redistribution structure232may include one or more materials such as a gold (Au) material, a copper (Cu) material, a silver (Ag) material, a nickel (Ni) material, a tin (Sn) material, and/or a palladium (Pd) material, among other examples. The metallization layers236of the redistribution structure232may include metal lines, vias, interconnects, and/or another type of metallization layers.

As further shown inFIG.2, the semiconductor die package200may include one or more BTSV structures238through the device region212, and into a portion of the interconnect region214. The one or more BTSV structures238may include vertically elongated conductive structures (e.g., conductive pillars, conductive vias) that electrically connect one or more of the metallization layers228in the interconnect region214of the second semiconductor die204to one or more metallization layers236in the redistribution structure232. The BTSV structures238may be referred to as through silicon via (TSV) structures in that the BTSV structures238extend fully through a silicon substrate (e.g., the silicon substrate of the device region212) as opposed to extending fully through a dielectric layer or an insulator layer. The one or more BTSV structures238may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and/or another type of conductive materials.

A buffer oxide layer240may be included between the second semiconductor die204and the redistribution structure232. In particular, the buffer oxide layer240may be included over and/or on the second side of the second semiconductor die204. The one or more BTSV structures238may extend through the buffer oxide layer240. The buffer oxide layer240may include one or more oxide layers that function as a buffer between the device region212of the second semiconductor die204and the redistribution structure232. The buffer oxide layer240may include one or more oxide materials, such as a silicon oxide (SiOx), a silicon oxycarbide (SiOC), a silicon oxynitride (SiON), and/or another type of oxide material.

A high-k dielectric layer242may be included between the second semiconductor die204and the redistribution structure232. In particular, the high-k dielectric layer242may be included over the second side of the second semiconductor die204and on the buffer oxide layer240. The one or more BTSV structures238may extend through the high-k dielectric layer242.

The high-k dielectric layer242is a layer having a negative charge polarity. In other words, the high-k dielectric layer242includes one or more materials having an excess of electron charge carriers. The high-k dielectric layer242may have an intrinsic negative charge polarity in that material(s) may be selected for the high-k dielectric layer242that have an excess of electron charge carriers. The negative charge polarity of the high-k dielectric layer242facilitates attraction of hole charge carriers in the silicon substrate of the device region212toward the electron charge carriers in the high-k dielectric layer242.

As indicated above, dangling bonds that are formed during etching of a recess in which a BTSV structure238is formed may act as charge trapping states, which may cause trap-assist tunnels to form in the silicon substrate of the device region212. The trap-assist tunnels may result in electron current leakage from the p-well302to the n-well304via the BTSV structure238. The current leakage may occur through adjacent doped wells associated with the semiconductor device216. The negative charge polarity of the high-k dielectric layer242provides a coupling voltage to modify the electric potential in the silicon substrate of the device region212. In particular, the electron charge carriers in high-k dielectric layer242attracts hole charge carriers in the silicon substrate of the device region212, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the BTSV structure238. Therefore, the high-k dielectric layer242may reduce the likelihood of (and/or the magnitude of) current leakage in the semiconductor device216.

In some implementations, a thickness of the high-k dielectric layer242is included in a range of approximately 20 angstroms to approximately 500 angstroms to provide a sufficient amount of electron charge carriers in order to attract hold charge carriers in the silicon substrate of the device region212and to suppress the trap-assist tunnels. However, other values for the range are within the scope of the present disclosure.

The high-k dielectric layer242may include one or more high-k dielectric materials such as a hafnium oxide (HfOx), an aluminum oxide (ALxOy), a tantalum oxide (TaxOy), a gallium oxide (GaxOy), a titanium oxide (TiOx), a niobium oxide (NbxOy), and/or another suitable high-k dielectric material, among other examples. Additionally and/or alternatively, one or more low-k dielectric materials may be included in the high-k dielectric layer242. Materials may be selected for the high-k dielectric layer242and/or a thickness of the high-k dielectric layer242such that a sufficient amount of electron charge carriers is included in the high-k dielectric layer242.

In some implementations, an equivalent surface charge density of electron charge carriers in the high-k dielectric layer is included in a range of approximately −8×10−9coulombs per square centimeter (C/cm2) to approximately −1.6×10−7C/cm2to provide to provide a sufficient amount of electron charge carriers in order to attract hold charge carriers in the silicon substrate of the device region212and to suppress the trap-assist tunnels. However, other values for the range are within the scope of the present disclosure.

UBM layers244may be included on a top surface of the one or more dielectric layers234. The UBM layers244may be electrically connected and/or physically connected with one or more metallization layers236in the redistribution structure232. The UBM layers244may be included in recesses in the top surface of the one or more dielectric layers234. The UBM layers244may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and/or another type of conductive materials.

As further shown inFIG.2, the semiconductor die package200may include conductive terminals246. The conductive terminals246may be electrically connected and/or physically connected with the UBM layers244. The UBM layers244may be included to facilitate adhesion to the one or more metallization layers236in the redistribution structure232, and/or to provide increased structural rigidity for the conductive terminals246(e.g., by increasing the surface area to which the conductive terminals246are connected). The conductive terminals246may include ball grid array (BGA) balls, land grid array (LGA) pads, pin grid array (PGA) pins, and/or another type of conductive terminals. The conductive terminals246may enable the semiconductor die package200to be mounted to a circuit board, a socket (e.g., an LGA socket), an interposer or redistribution structure of a semiconductor device package (e.g., a chip on wafer on substrate CoWoS package, an integrated fanout (InFO) package), and/or another type of mounting structure.

As further shown inFIG.2, the semiconductor die package200may include one or more regions248in which a BTSV structure238is located near (e.g., adjacent to, next to, and/or through) a semiconductor device216in the device region212of the second semiconductor die204. Subsequent figures, such asFIGS.3A and3B, may refer to a region248in the semiconductor die package200.

FIGS.3A and3Bare diagrams of an example implementation of a region248of the semiconductor die package200described herein. The region248may include a BTSV structure238that extends adjacent to one or more semiconductor devices216in the silicon substrate of the device region212, and through the buffer oxide layer240and the high-k dielectric layer242.

As shown inFIGS.3A, a plurality of doped regions may be included in the silicon substrate of the device region212. For example, a p-well302may be included in the silicon substrate of the device region212. The p-well302may include a portion of the silicon substrate that is doped with one or more p-type dopants such as boron (B) or germanium (Ge), among other examples. As another example, an n-well304may be in the silicon substrate of the device region212. The n-well304may be included next to (e.g., adjacent to or side-by-side with) the p-well302such that edges of the p-well302and n-well304are interfaced. The n-well304may include one or more n-type materials such as phosphorous (P) or arsenic (As), among other examples. In some implementations, additional doped regions are included, such as a deep n-well306under the n-well304.

As further shown inFIG.3A, the one or more semiconductor devices216may include a source/drain region308and a source/drain region310. In some implementations, the source/drain region308and the source/drain region310are included on opposing sides of the BTSV structure238. A source/drain region refers to a source region, a drain region, or a combination of a source region and a drain region, depending on the context. The source/drain regions308and310may be source/drain regions of one or more transistors of the one or more semiconductor devices216.

The source/drain regions308and310include silicon (Si) with one or more dopants, such as a p-type material (e.g., boron (B) or germanium (Ge), among other examples), an n-type material (e.g., phosphorous (P) or arsenic (As), among other examples), and/or another type of dopant. For example, the source/drain region308may be included in an n-well304and may be referred to as an n-type source/drain region in that the source/drain region308is doped with one or more n-type dopants. As another example, the source/drain region310may be included in a p-well302and may be referred to as a p-type source/drain region in that the source/drain region310is doped with one or more p-type dopants.

A shallow trench isolation (STI) region312may be included between the source/drain regions308and310to provide electrical isolation between the source/drain regions308and310. The STI region312may include a dielectric material such as a silicon oxide (SiOx), a silicon nitride (SixNy), a silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or another suitable insulating material. The STI region312may include a multi-layer structure, for example, having one or more liner layers.

As further shown inFIG.3A, a sidewall spacer314may be included around the BTSV structure238between the BTSV structure238and the p-well302. Moreover, the sidewall spacer314may be included between the BTSV structure238and the silicon substrate of the device region212. Moreover, the sidewall spacer314may be included between the BTSV structure238and the buffer oxide layer240. Moreover, the sidewall spacer314may be included between the BTSV structure238and the high-k dielectric layer242. The sidewall spacer314may include one or more dielectric materials such as silicon oxide (SiOx, such as SiO2), silicon nitride (SixNy), and/or silicon oxynitride (SiON), among other examples.

The BTSV structure238may extend through the p-well302and not through the n-well304. Moreover, the BTSV structure238does not extend through any other n-wells, which would otherwise result in direct current leakage between the BTSV structure238and the other n-wells. A distance (D1) between the sidewall of the BTSV structure238and the edge of the edge of the p-well302next to the n-well304may be referred to as a keep-out zone (KOZ). The KOZ may be a design rule that prohibits the placement of the BTSV structure238closer to the edge of the p-well302next to the n-well304. As indicated above, dangling bonds that are formed during etching of a recess in which as BTSV structure238is formed may act as charge trapping states, which may cause trap-assist tunnels to form in the silicon substrate of the device region212. The trap-assist tunnels may result in electron current leakage from the p-well302to the n-well304via the BTSV structure238. Accordingly, the distance (D1) may be selected to reduce the likelihood of and/or prevent current leakage from the BTSV structure238.

The negative charge polarity of the high-k dielectric layer242provides a coupling voltage to modify the electric potential in the silicon substrate of the device region212. In particular, the electron charge carriers in high-k dielectric layer242attracts hole charge carriers in the silicon substrate of the device region212, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the BTSV structure238. This enables the distance (D1) to be reduced, and enables the BTSV structure238to be placed closer to the edge of the p-well302(e.g., the edge of the p-well302that is interfaced with and/or next to the edge of the n-well304) without increasing the likelihood of and/or magnitude of current leakage in the one or more semiconductor devices. In some implementations, the distance (D1) is included in a range of approximately 0.2 microns to approximately 2 microns as a result of the inclusion of the negative charge polarity of the high-k dielectric layer242, whereas the distance (D1) might otherwise be included in a range of approximately 0.5 microns to approximately 50 microns. However, other values for these ranges are within the scope of the present disclosure.

FIG.3Billustrates a cross-section view along line A-A inFIG.3A(e.g., looking downward from a top view along the cross-section. As shown inFIG.3B, the sidewall spacer314may surround BTSV structure238such that the BTSV structure238is not in direct contact with the p-well302(and thus, the silicon substrate of the device region212). The BTSV structure238being in direct contact with the p-well302might otherwise cause current leakage and/or copper migration into the silicon substrate, and/or delamination of the BTSV structure238from the silicon substrate, among other examples.

As indicated above,FIGS.3A and3Bare provided as an example. Other examples may differ from what is described with regard toFIGS.3A and3B.

FIG.4is a diagram of an example implementation400of charge polarities of various high-k dielectric materials described herein. One or more of the high-k dielectric materials may be included in the high-k dielectric layer242described herein.

The charge polarities are illustrated in the example implementation400as a function of interface state density (Dit)402in electron volts per square centimeter (eV−1/cm2) and fixed charge density (Qƒ/q)404in cm2. As shown inFIG.4, high-k dielectric materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), aluminum nitride (AiN), and gallium oxide (Ga2O3) have a negative fixed charge density404(or a primarily negative fixed charge density404in the case of hafnium oxide) across the spectrum of interface state densities for these high-k dielectric materials. Other high-k dielectric materials such as titanium oxide (TiO2) and niobium oxide (Nb2O5) also have a negative fixed charge density404across the spectrum of interface state densities for these high-k dielectric materials.

FIG.5is a diagram of an example implementation500of a depletion edge502described herein. The depletion edge502may occur in the p-well302in the silicon substrate in the device region212of the second semiconductor die204described herein.

The depletion edge502represents the boundary of a depletion region in the p-well302. Inside the depletion region (e.g., the area in the p-well302between the edge of the n-well304and the depletion edge502), a built-in electric field results in the majority of carriers to be depleted. If the depletion edge touches the BTSV structure238, the built-in electric field may easily result in the creation of a current leakage path through the dangling bonds at the sidewalls of the BTSV structure238.

Since the high-k dielectric layer242has an intrinsic negative charge polarity, the negative/electron charge carriers in the high-k dielectric layer242is able to attract hole charge carriers in the p-well302, which suppresses the depletion region and reduces a depletion width (D2) of the depletion region. This causes the depletion edge502to curl away from the BTSV structure238, as opposed to the depletion edge502progressing toward the BTSV structure238(which would otherwise result in current leakage). In some implementations, the intrinsic negative charge polarity of the high-k dielectric layer242results in the depletion width (D2) of the depletion region being less than or approximately equal to 1.22 microns. However, other values for the depletion width (D2) are within the scope of the present disclosure.

FIGS.6A-6Eare diagrams of an example implementation600of forming a semiconductor die described herein. In some implementations, the example implementation600includes an example process (or a portion thereof) for forming the second semiconductor die204. While the operations described in connection withFIGS.6A-6Eare described in connection with the second semiconductor die204, similar operations may be performed to form the first semiconductor die202.

In some implementations, one or more operations described in connection withFIGS.6A-6Emay be performed by one or more of the semiconductor processing tools102-114and/or the wafer/die transport tool116. In some implementations, one or more operations described in connection withFIGS.6A-6Emay be performed by another semiconductor processing tool. Turning toFIG.6A, one or more of the operations in the example implementation600may be performed in connection with the silicon substrate of the device region212of the second semiconductor die204.

As shown inFIG.6B, one or more semiconductor devices216may be formed in the device region212. For example, one or more of the semiconductor processing tools102-114may perform photolithography patterning operations, etching operations, deposition operations, CMP operations, and/or another type of operations to form one or more transistors, one or more capacitors, one or more memory cells, and/or one or more semiconductor devices of another type. In some implementations, one or more regions of the silicon substrate of the device region212may be doped in an ion implantation operation to form one or more p-wells302, one or more n-wells304, and/or one or more deep n-wells306. In some implementations, the deposition tool102may deposit one or more source/drain regions308, one or more source/drain regions310, and/or one or more STI regions312, among other examples.

As shown inFIGS.6C-6E, the interconnect region214of the second semiconductor die204may be formed over and/or on the silicon substrate of the device region212. One or more of the semiconductor processing tools102-114may form the interconnect region214by forming one or more dielectric layers226and forming a plurality of metallization layers228in the plurality of dielectric layers226. For example, the deposition tool102may deposit a first layer of the one or more dielectric layers226(e.g., using a CVD technique, an ALD technique, a PVD technique, and/or another type of deposition technique), the etch tool108may remove portions of the first layer to form recesses in the first layer, and the deposition tool102and/or the plating tool112may form a first metallization layer of the plurality of metallization layers228in the recesses (e.g., using a CVD technique, an ALD technique, a PVD technique, an electroplating technique, and/or another type of deposition technique). At least a portion of the first metallization layer may be electrically connected and/or physically connected with the semiconductor device(s)216. The deposition tool102, the etch tool108, the plating tool112, and/or another semiconductor processing tool may continue to perform similar processing operations to forming the interconnect region214until a sufficient or desired arrangement of metallization layers228is achieved.

As shown inFIG.6E, one or more of the semiconductor processing tools102-114may form another layer of the one or more dielectric layers226, and may form a plurality of contacts230in the layer such that the contacts230are electrically connected and/or physically connected with one or more of the metallization layers228. For example, the deposition tool102may deposit the layer of the one or more dielectric layers226(e.g., using a CVD technique, an ALD technique, a PVD technique, and/or another type of deposition technique), the etch tool108may remove portions of the layer to form recesses in the layer, and the deposition tool102and/or the plating tool112may form the contacts230in the recesses (e.g., using a CVD technique, an ALD technique, a PVD technique, an electroplating technique, and/or another type of deposition technique).

As indicated above,FIGS.6A-6Eare provided as an example. Other examples may differ from what is described with regard toFIGS.6A-6E.

FIGS.7A-7Dare diagrams of an example implementation700of forming a portion of a semiconductor die package200described herein. In some implementations, one or more operations described in connection withFIGS.7A-7Dmay be performed by one or more of the semiconductor processing tools102-114and/or the wafer/die transport tool116. In some implementations, one or more operations described in connection withFIGS.7A-7Dmay be performed by another semiconductor processing tool.

As shown inFIG.7A, the first semiconductor die202and the second semiconductor die204may be bonded at the bonding interface206such that the first semiconductor die202and the second semiconductor die204are vertically arranged or stacked in a WoW configuration. The bonding tool114may perform a bonding operation to bond the first semiconductor die202and the second semiconductor die204at the bonding interface206. The bonding operation may include a direct bonding operation (or hybrid bonding operation) in which bonding of first semiconductor die202and the second semiconductor die204is achieved through the physical connection of the contacts224with the contacts230.

As shown inFIG.7B, the buffer oxide layer240may be formed on the second semiconductor die204. The second semiconductor die204may be bonded with the first semiconductor die202at a first side of the second semiconductor die204, which may correspond to a first side of the interconnect region214. The buffer oxide layer240may be formed on a second side of the second semiconductor die204opposing the first side, which may correspond to a first side of the device region212of the second semiconductor die204. The deposition tool102may deposit the buffer oxide layer240using an epitaxy technique, a CVD technique, a PVD technique, an ALD technique, another deposition technique described above in connection withFIG.1, and/or a deposition technique other than as described above in connection withFIG.1.

As further shown inFIG.7B, the high-k dielectric layer242may be formed over the second semiconductor die204. The high-k dielectric layer242may be formed over the second side of the second semiconductor die204opposing the first side, which may correspond to the first side of the device region212of the second semiconductor die204. The high-k dielectric layer242may be formed on the buffer oxide layer240. The deposition tool102may deposit the buffer oxide layer240using an epitaxy technique, a CVD technique, a PVD technique, an ALD technique, another deposition technique described above in connection withFIG.1, and/or a deposition technique other than as described above in connection withFIG.1. The high-k dielectric layer242may be deposited at a temperature that is included in a range of approximately 150 degrees Celsius to approximately 300 degrees Celsius. However, other values for the range are within the scope of the present disclosure.

As described above the high-k dielectric layer242may have an intrinsic negative polarity. Accordingly, forming the high-k dielectric layer242may include depositing one or more materials having an intrinsic negative charge polarity to form the high-k dielectric layer242. The intrinsic negative charge polarity results from lattice defects, in the one or more materials, that form during deposition of the one or more materials.

As shown inFIG.7C, one or more recesses702may be formed through the high-k dielectric layer242, through the buffer oxide layer240, through the silicon substrate of the device region212, and into a portion of the dielectric layer226of the interconnect region214. The one or more recesses702may be formed to expose one or more portions of a metallization layer228in the interconnection region214. Thus, the one or more recesses702may be formed over the one or more portions of a metallization layer228.

In some implementations, a pattern in a photoresist layer is used to form the one or more recesses702. In these implementations, the deposition tool102forms the photoresist layer on the high-k dielectric layer242. The exposure tool104exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool106develops and removes portions of the photoresist layer to expose the pattern. The etch tool108etches through the high-k dielectric layer242, through the buffer oxide layer240, through the device region212, and into the interconnect region214to form the one or more recesses702. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the one or more recesses702based on a pattern.

As shown inFIG.7D, one or more BTSV structures238may be formed in the one or more recesses702. In this way, the one or more BTSV structures238extend through the high-k dielectric layer242, through the buffer oxide layer240, through the device region212, and into the interconnect region214. Moreover, one or more BTSV structures238may be formed adjacent to one or more semiconductor devices216in the device region212, and may be formed through one or more p-wells302(e.g., p-wells302that are associated with one or more semiconductor devices216) in the silicon substrate of the device region212. The one or more BTSV structures238may be electrically connected and/or physically connected with the one or more portions of the metallization layer228that were exposed through the one or more recesses702.

The deposition tool102and/or the plating tool112may deposit the one or more BTSV structures238using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection withFIG.1, and/or a deposition technique other than as described above in connection withFIG.1. In some implementations, the planarization tool110may perform a CMP operation to planarize the one or more BTSV structures238after the one or more BTSV structures238are deposited.

As indicated above,FIGS.7A-7Dare provided as an example. Other examples may differ from what is described with regard toFIGS.7A-7D.

FIGS.8A-8Dare diagrams of an example implementation800of forming a portion of a semiconductor die package200described herein. In some implementations, one or more operations described in connection withFIGS.8A-8Dmay be performed after one or more operations described in connection withFIGS.7A-7D. In some implementations, one or more operations described in connection withFIGS.8A-8Dmay be performed by one or more of the semiconductor processing tools102-114and/or the wafer/die transport tool116. In some implementations, one or more operations described in connection withFIGS.8A-8Dmay be performed by another semiconductor processing tool.

As shown inFIG.8A, the redistribution structure232of the semiconductor die package200may be formed over the second semiconductor die204. One or more of the semiconductor processing tools102-114may form the redistribution structure232by forming one or more dielectric layers234and forming a plurality of metallization layers236in the plurality of dielectric layers234. For example, the deposition tool102may deposit a first layer of the one or more dielectric layers234(e.g., using a CVD technique, an ALD technique, a PVD technique, and/or another type of deposition technique), the etch tool108may remove portions of the first layer to form recesses in the first layer, and the deposition tool102and/or the plating tool112may form a first metallization layer of the plurality of metallization layers236in the recesses (e.g., using a CVD technique, an ALD technique, a PVD technique, an electroplating technique, and/or another type of deposition technique). At least a portion of the first metallization layer may be electrically connected and/or physically connected with the one or more BTSV structures238. The deposition tool102, the etch tool108, the plating tool112, and/or another semiconductor processing tool may continue to perform similar processing operations to forming the redistribution structure232until a sufficient or desired arrangement of metallization layers236is achieved.

As shown inFIG.8B, recesses802may be formed in the one or more dielectric layers234. The recesses802may be formed to expose portions of a metallization layer236in the redistribution structure232. Thus, the recesses802may be formed over the one or more portions of a metallization layer236.

In some implementations, a pattern in a photoresist layer is used to form the recesses802. In these implementations, the deposition tool102forms the photoresist layer on the one or more dielectric layers234. The exposure tool104exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool106develops and removes portions of the photoresist layer to expose the pattern. The etch tool108etches into the one or more dielectric layers234to form the recesses802. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the recesses802based on a pattern.

As shown inFIG.8C, UBM layers244may be formed in the recesses802. The deposition tool102and/or the plating tool112may deposit the UBM layers244using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection withFIG.1, and/or a deposition technique other than as described above in connection withFIG.1. In some implementations, a continuous layer of conductive material is deposited on the top surface of the redistribution structure232, including in the recess802. The continuous layer of conductive material is then patterned (e.g., by the deposition tool102, the exposure tool104, and the developer tool106) to form a pattern on the continuous layer of the conductive material, and the etch tool108removes portions of the continuous layer of the conductive material based on the pattern. Remaining portions of the continuous layer of the conductive material may correspond to the UBM layers244.

As shown inFIG.8D, conductive terminals246may be formed in the recesses802over the UBM layers244. In some implementations, the plating tool112forms the conductive terminals246using an electroplating technique. In some implementations, solder is dispensed in the recesses802to form the conductive terminals246.

As indicated above,FIGS.8A-8Dare provided as an example. Other examples may differ from what is described with regard toFIGS.8A-8D.

FIG.9is a diagram of example components of a device900described herein. In some implementations, one or more of the semiconductor processing tools102-114and/or the wafer/die transport tool116may include one or more devices900and/or one or more components of device900. As shown inFIG.9, device900may include a bus910, a processor920, a memory930, an input component940, an output component950, and a communication component960.

Bus910may include one or more components that enable wired and/or wireless communication among the components of device900. Bus910may couple together two or more components ofFIG.9, such as via operative coupling, communicative coupling, electronic coupling, and/or electric coupling. Processor920may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. Processor920is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor920may include one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

Memory930may include volatile and/or nonvolatile memory. For example, memory930may include random access memory (RAM), read only memory (ROM), a hard disk drive, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory). Memory930may include internal memory (e.g., RAM, ROM, or a hard disk drive) and/or removable memory (e.g., removable via a universal serial bus connection). Memory930may be a non-transitory computer-readable medium. Memory930stores information, instructions, and/or software (e.g., one or more software applications) related to the operation of device900. In some implementations, memory930may include one or more memories that are coupled to one or more processors (e.g., processor920), such as via bus910.

Input component940enables device900to receive input, such as user input and/or sensed input. For example, input component940may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an accelerometer, a gyroscope, and/or an actuator. Output component950enables device900to provide output, such as via a display, a speaker, and/or a light-emitting diode. Communication component960enables device900to communicate with other devices via a wired connection and/or a wireless connection. For example, communication component960may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.

Device900may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory930) may store a set of instructions (e.g., one or more instructions or code) for execution by processor920. Processor920may execute the set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions, by one or more processors920, causes the one or more processors920and/or the device900to perform one or more operations or processes described herein. In some implementations, hardwired circuitry is used instead of or in combination with the instructions to perform one or more operations or processes described herein. Additionally, or alternatively, processor920may be configured to perform one or more operations or processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

The number and arrangement of components shown inFIG.9are provided as an example. Device900may include additional components, fewer components, different components, or differently arranged components than those shown inFIG.9. Additionally, or alternatively, a set of components (e.g., one or more components) of device900may perform one or more functions described as being performed by another set of components of device900.

FIG.10is a flowchart of an example process1000associated with forming a semiconductor die package. In some implementations, one or more process blocks ofFIG.10are performed by one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools102-114). Additionally, or alternatively, one or more process blocks ofFIG.10may be performed by one or more components of device900, such as processor920, memory930, input component940, output component950, and/or communication component960.

As further shown inFIG.10, process1000may include forming a high-k dielectric layer over a semiconductor die (block1010). For example, one or more of the semiconductor processing tools102-114may form a high-k dielectric layer242over the second semiconductor die204, as described herein. In some implementations, the high-k dielectric layer242has a negative charge polarity. In some implementations the second semiconductor die204is bonded with the first semiconductor die202at a bonding interface206.

As further shown inFIG.10, process1000may include forming a recess through the high-k dielectric layer, through a device region of the semiconductor die, and into a portion of an interconnection region of the semiconductor die to expose a portion of a metallization layer in the interconnection region (block1020). For example, one or more of the semiconductor processing tools102-114may form a recess702through the high-k dielectric layer242, through a device region212of the second semiconductor die204, and into a portion of an interconnection region214of the second semiconductor die204to expose a portion of a metallization layer228in the interconnection region214, as described herein.

As further shown inFIG.10, process1000may include forming a conductive via structure in the recess (block1030). For example, one or more of the semiconductor processing tools102-114may form a BTSV structure238in the recess702, as described herein.

In a first implementation, forming the BTSV structure238includes forming the BTSV structure238adjacent to one or more semiconductor devices216in the device region212of the second semiconductor die204.

In a second implementation, alone or in combination with the first implementation, forming the BTSV structure238includes forming the BTSV structure238through a p-well302associated with the one or more semiconductor devices216, where the p-well302is adjacent to an n-well304associated with the one or more semiconductor devices216.

In a third implementation, alone or in combination with one or more of the first and second implementations, forming the high-k dielectric layer242includes forming the high-k dielectric layer242to a thickness that is in a range of approximately 20 angstroms to approximately 500 angstroms.

In a fourth implementation, alone or in combination with one or more of the first through third implementations, forming the high-k dielectric layer242includes depositing one or more materials having an intrinsic negative charge polarity to form the high-k dielectric layer242.

In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, the one or more materials includes at least one of a hafnium oxide (HfOx), an aluminum oxide (ALxOy), a tantalum oxide (TaxOy), a gallium oxide (GaxOy), a titanium oxide (TiOx), or a niobium oxide (NbxOy).

In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, the intrinsic negative charge polarity results from lattice defects, in the one or more materials, that form during deposition of the one or more materials.

In a seventh implementation, alone or in combination with one or more of the first through sixth implementations, process1000includes forming a buffer oxide layer240on the device region212, where forming the high-k dielectric layer242includes forming the high-k dielectric layer242on the buffer oxide layer240.

In an eighth implementation, alone or in combination with one or more of the first through seventh implementations, the process1000includes bonding the first semiconductor die202and the second semiconductor die204by performing a hybrid bonding operation to bond the first semiconductor die202and the second semiconductor die204in a WoW configuration.

AlthoughFIG.10shows example blocks of process1000, in some implementations, process1000includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted inFIG.10. Additionally, or alternatively, two or more of the blocks of process1000may be performed in parallel.

In this way, a semiconductor die package (e.g., a WoW semiconductor die package) includes a high-k dielectric layer over a device region (e.g., a silicon substrate) of a first semiconductor die that is bonded with a second semiconductor die in a WoW configuration. A TSV structure (e.g., a BTSV structure) may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the negative charges (e.g., electron carriers) in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Therefore, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die. This may increase the performance of the semiconductor devices and/or may enable the semiconductor devices to be placed closer together and closer to the TSV structure, which enables reduced semiconductor device pitch and increased semiconductor device density in the first semiconductor die, among other examples.

As described in greater detail above, some implementations described herein provide a semiconductor die package. The semiconductor die package includes a first semiconductor die. The semiconductor die package includes a second semiconductor die, bonded with the first semiconductor die at a first side of the second semiconductor die, comprising, a device region including one or more semiconductor devices an interconnect region between the device region and the first semiconductor die. The semiconductor die package includes a dielectric layer over a second side of the second semiconductor die opposing the first side, where the dielectric layer has an intrinsic negative charge polarity. The semiconductor die package includes a conductive via structure that extends through the dielectric layer, through the device region, and into a portion of the interconnect region.

As described in greater detail above, some implementations described herein provide a method. The method includes forming a high-k dielectric layer over a semiconductor die, where the high-k dielectric layer has a negative charge polarity. The method includes forming a recess through the high-k dielectric layer, through a device region of the semiconductor die, and into a portion of an interconnection region of the semiconductor die to expose a portion of a metallization layer in the interconnection region. The method includes forming a conductive via structure in the recess.

As described in greater detail above, some implementations described herein provide a semiconductor die package. The semiconductor die package includes a first semiconductor die. The semiconductor die package includes a second semiconductor die, bonded with the first semiconductor die at a first side of the second semiconductor die, comprising, a device region including one or more semiconductor devices an interconnect region between the device region and the first semiconductor die. The semiconductor die package includes a high-k dielectric layer over a second side of the second semiconductor die opposing the first side, where the high-k dielectric layer has an intrinsic negative charge polarity. The semiconductor die package includes a TSV structure that extends through the high-k dielectric layer, through the device region, and into a portion of the interconnect region, where the TSV structure extends through a p-well that is next to an n-well in the device region. The intrinsic negative charge polarity of the high-k dielectric layer is configured to resist current leakage from the p-well to the n-well.