Memory with level shifting word line driver and method thereof

A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to memories and more particularly to powering memories.

BACKGROUND

Memories typically are implemented as bit cell arrays accessed via word line drivers, where the word line drivers are activated based on the decoding of row addresses associated with memory accesses. For data reliability and performance reasons, it often is advantageous to operate the bit cell array and the word line drivers at a higher voltage than the peripheral circuitry of the memory. This dual-voltage domain technique also is advantageous in that the peripheral circuitry of the memory can be placed in a low-power mode to reduce leakage current without disturbing the voltage supply to the bit cell array, thereby allowing the bit cell array to retain stored data.

The use of dual voltage domains typically requires the use of voltage level shifters between the peripheral circuitry and the word line drivers and bit cell array. Conventional level shifting implementations typically require a relatively large substrate area, thereby inhibiting their use in a memory topology having a relatively small memory cell pitch, particularly in memory cell topologies utilizing hierarchical word line decoding. These conventional level shifting implementations also typically implement relatively slow circuitry, which, being in the critical path between the peripheral circuitry and the word lines, impedes the performance of memory accesses. Accordingly, an improved technique for voltage level shifting in a multiple-voltage-domain memory would be advantageous.

DETAILED DESCRIPTION

In accordance with one aspect of the present disclosure, a word line driver has a first input to receive a first predecode value, a second input to receive a second predecode value, and an output coupled to a word line of a memory. The word line driver includes a first transistor having a gate electrode coupled to the first input, a first current electrode coupled to the second input, and a second current electrode coupled to a first node, and a second transistor having a gate electrode coupled to a first voltage reference, a first current electrode coupled to a second voltage reference, and a second current electrode coupled to the first node. The word line driver further includes a third transistor having a gate electrode coupled to the first node, a first current electrode coupled to a third voltage reference, and a second current electrode coupled to a second node. The second node is coupled to a word line of a memory. The word line driver also includes a fourth transistor having a gate electrode coupled to the first node, a first current electrode coupled to the second node, and a second current electrode coupled to the first voltage reference.

In accordance with another aspect of the present disclosure, a memory includes a plurality of global word lines and global word line driver circuitry having a plurality of outputs. Each output is coupled to a corresponding global word line of the plurality of global word lines. The memory further includes address decode circuitry having an output to provide a predecode value and a local bit cell array including a plurality of local word lines. The memory additionally includes local word line driver circuitry having an input coupled to the output of the address decode circuitry, an input coupled to corresponding global word line of the plurality of global word lines, and a plurality of outputs. Each output is coupled to a corresponding local word line of the plurality of local word lines. The local word line driver circuitry includes a plurality of voltage level shifters, each voltage level shifter associated with a corresponding local word line of the local bit cell array. The global word line driver circuitry and address decode circuitry are operable in a first voltage domain and the local bit cell array and local word line driver circuitry are operable in a second voltage domain different than the first voltage domain.

In accordance with another aspect of the present disclosure, a method is provided for a memory including address decode circuitry operable at a first voltage and including word line driver circuitry and a bit cell array operable at a second voltage. The memory includes providing the first voltage to the address decode circuitry and providing the second voltage to the word line driver circuitry and the bit cell array in an active mode. The method also includes providing a third voltage to the address decode circuitry, wherein the address decode circuitry is substantially inoperable at the third voltage and providing a fourth voltage to bit cell array in a low power mode. The bit cell array is operable to retain stored data at the fourth voltage.

FIGS. 1-5illustrate exemplary techniques for utilizing voltage level shifting (hereinafter, “level shifting”) in a memory device having multiple voltage levels. In accordance with at least one embodiment, the memory includes peripheral circuitry, such as address decode circuitry, operated in a first voltage domain and a bit cell array and word line drivers operated in a second voltage domain, where the peripheral circuitry can be shut-down or placed in a low-power state by reducing or shutting off the voltage to the first voltage domain while maintaining a voltage at the second voltage domain for data retention purposes. As the second voltage domain can be operated at a voltage greater than the voltage supplied to the first voltage domain, the word line drivers can implement voltage level shifters (hereinafter, “level shifters”) to facilitate interfacing between the first voltage domain and the second voltage domain. In one embodiment, the transistors of the peripheral circuitry are implemented using a first gate oxide thickness and the transistors of the word line drivers (including the level shifters) and the transistors of the bit cell array are implemented using a second gate oxide thickness that is greater than the first gate oxide thickness. Thus, the transistors of the peripheral circuitry can operate faster and at a lower voltage than the transistors of the word line drivers and the bit cell arrays. The use of a thicker gate oxide for transistors of the bit cell array also reduces leakage current in these transistors at the higher voltage supplied to the second voltage domain.

Referring toFIG. 1, an exemplary processing system100is illustrated in accordance with at least one embodiment of the present disclosure. The processing system100can include, for example, a microprocessor or microcontroller, and may be implemented as a single integrated circuit device, such as, for example, a system-on-a-chip (SOC) or an application-specific integrated circuit (ASIC). Alternately, the processing system100can be implemented as a plurality of separate integrated circuit devices.

In the depicted example, the processing system100includes a memory102(e.g., a random access memory (RAM)) having two voltage domains, a central processing unit (CPU)104and one or more peripheral components (e.g., peripheral components106and108) connected via one or more busses110. The processing system100further includes a power supply112to provide a voltage VDD1(e.g., approximately 0.9 volts) for a first voltage domain of the processing system100and a power supply114to provide a voltage VDD2(e.g., approximately 1.2 volts) for a second voltage domain of the processing system100when the processing system100is in an active mode. In one embodiment, the power supply112and the power supply114are a single power supply.

The memory102includes peripheral circuitry, such as address decode circuitry116, operated in the first voltage domain. The memory102also includes word line driver circuitry118and a bit cell array120operated in the second voltage domain. As described in greater detail herein, the operational voltages of the first voltage domain and the second voltage domain differ (e.g., the operational voltage of the second voltage domain is higher than the operational voltage of the first voltage domain). Accordingly, the word line driver circuitry118implements level shifting circuitry to facilitate interfacing between the two different voltages of the first and second voltage domains.

To enable the memory102to operate over two or more voltage domains, the transistors implemented in the components of the first voltage domain, such as the transistors of the address decode circuitry116, utilize a first gate oxide thickness and the transistors implemented in the components of the second voltage domain, such as the transistors of the word line driver circuitry118and the bit cell array120, utilize a second gate oxide thickness. In at least one embodiment, the second gate oxide thickness is greater than the first gate oxide thickness. For example, the first gate oxide thickness can be less than 14 angstroms and the second gate oxide thickness can be less than 19 angstroms. Example gate oxide materials can include silicon dioxide, silicon nitride, and the like.

It will be appreciated that transistors having a thicker gate oxide typically have a greater minimum operational voltage than transistors having a thinner gate oxide. Conversely, transistors having a thicker gate oxide typically experience less leakage current than transistors having a thinner gate oxide. Accordingly, in one embodiment, the second voltage domain is supplied with a higher operational voltage than the first voltage domain (i.e., VDD2>VDD1) while the memory102is in an active mode so that the transistors of the peripheral circuitry, the word line driver circuitry118and the bit cell array120all are operational. In a low-voltage mode (e.g., a sleep mode), the second voltage domain is supplied with a voltage sufficient for data retention purposes at the bit cell array120and the transistors of the peripheral circuitry (e.g., the address decode circuitry116) are placed in an inoperative state by supplying a voltage to the first voltage domain that is less than the threshold voltage of the transistors of the peripheral components (e.g., by supplying zero volts). As a result, power can be conserved by effectively shutting down the peripheral circuitry of the memory102during inactive periods while maintaining the data in the bit cell array120. In an alternate embodiment, the second voltage domain is supplied with a lower operational voltage than the first voltage domain (i.e., VDD2<VDD1).

In order to implement the different modes of operation, the processing system100includes a mode controller122to control the power supplies112and114in response to a mode select signal124provided by the CPU104, where the mode select signal124can be used to indicate whether the memory102is to enter the active mode or the low-voltage mode. In response to the mode select signal124indicating the active mode, the mode controller122directs power supply112to provide the VDD1voltage and the power supply114to provide the VDD2voltage, thereby maintaining the peripheral circuitry of the first voltage domain and the word line driver circuitry118and the bit cell array120of the second voltage domain in operative states. In response to the mode select signal124indicating the low voltage mode, the mode controller122directs the power supply112to provide a voltage lower than VDD1and lower than the threshold voltage of the transistors of the peripheral circuitry (e.g., provide zero volts) and directs the power supply114to continue to provide the VDD2voltage. As a result, the periphery circuitry of the memory102is effectively disabled while the bit cell array120continues to retain the stored data.

Referring toFIG. 2, an exemplary implementation of the memory102ofFIG. 1is illustrated in accordance with at least one embodiment of the present disclosure. The memory102includes the address decode circuitry116operated in the voltage domain202(receiving voltage VDD1during an active mode). The memory102further includes the word line driver circuitry118(including level shifting circuitry) and the bit cell array120operated in the voltage domain204(receiving voltage VDD2during an active mode).

In the depicted implementation, the address decode circuitry116includes a latch206having a first input to receive a row address value208, a second input to receive a clock signal210, and a plurality of outputs, each output providing a latched representation of a corresponding bit value of the row address value208responsive to the clock signal210. For purposes of illustration, it is assumed that the row address value208is a six bit value (bits RA[0]-RA[5]) and the latch206therefore provides latched output bits RA[0]-RA[5].

The address decode circuitry116further includes a decoder212and a decoder214, where the decoder212has inputs to receive a first subset of the bit values of the latched row address value208and the decoder214has input to receive a second subset of the bit values of the latched row address value208. The first and second subsets can be mutually exclusive or may overlap. The decoder212has a plurality of outputs, each output providing a corresponding bit of a first predecode value (PredA) determined by the decoder212based on the first subset of bit values. The decoder214has a plurality of outputs, each output providing a corresponding bit of a second predecode value (PredB) determined by the decoder214based on the second subset of bit values. In the illustrated example, the decoder212includes a 4-to-16 decoder having four inputs to receive bits RA[0]-RA[3] of the latched row address value208and sixteen outputs to provide sixteen bits for PredA (i.e., PredA[0]-PredA[15]). Further, in this example the decoder214includes a 2-to-4 decoder having two inputs to receive bits RA[4] and RA[5] and four outputs to provide four bits for PredB (i.e., PredB[0]-PredB[3]).

In the depicted example, the word line driver circuitry118includes a first set of inputs connected to the outputs of the decoder212to receive the corresponding bit values for PredA[0]-PredA[15] and a second set of inputs connected to the decoder214to receive the corresponding bit values for PredB[0]-PredB[3]. The word line driver circuitry118further includes a plurality of outputs that are connected to the word lines of the bit cell array120, where the particular word line is asserted by the word line driver circuitry118during any given access cycle is determined based on a final decode of the bits PredA[0]-PredA[15] and PredB[0]-PredB[3] received at the word line driver circuitry118. In the illustrated example, the word line driver circuitry118is connected to sixty-four word lines (WL0-WL63) of the bit cell array120.

As noted above, the transistors of the address decode circuitry116are implemented using a thinner gate oxide so that the address decode circuitry116can be operable at a lower voltage for VDD1and the transistors of the word line driver circuitry118and the bit cell array120are implemented using a thicker gate oxide so that the word line driver circuitry118and the bit cell array120are operable at a higher voltage (as well as being less susceptible to leakage current). However, as the voltage VDD2provided to the word line driver circuitry118and the bit cell array120can be higher than the voltage VDD1provided to the address decode circuitry116to take advantage of the benefits of the different transistor voltage and leakage characteristics, a voltage difference is present between the outputs of the decoders212and214and the voltages at which the word lines WL0-WL63 are operated. Accordingly, the word line driver circuitry118implements level shifters for each of the word lines WL0-WL63. Exemplary implementations of a word line driver of the word line driver circuitry118for a corresponding word line are illustrated in greater detail with reference toFIGS. 3 and 4.

Referring toFIG. 3, an exemplary implementation of a word line driver300utilized to drive a corresponding word line (e.g., WL0) of the bit cell array120(FIG. 2) is illustrated in accordance with at least one embodiment of the present disclosure. In the depicted example, the word line driver300includes transistors302,304,306, and308, where the transistors302and308are n-channel transistors (e.g., n-channel field effect transistors or NFETs) and the transistors304and306are p-channel transistors (e.g., p-channel field effect transistors or PFETs). As noted above, the transistors302,304,306and308are implemented using a gate oxide thickness that greater than the gate oxide thickness of the transistors of the periphery circuitry (e.g., the address decode circuitry116) of the memory102(FIG. 2), thereby requiring the transistors302,304,306and308to have a higher operational voltage but resulting in less leakage current.

The transistor302includes a gate electrode to receive a corresponding bit value of PredA (e.g., PredA[0]), a first current electrode to receive a corresponding bit value of PredB (e.g., PredB[0]), and a second current electrode connected to a node310. The transistor304includes a gate electrode connected to the voltage reference VSS(or ground), a first current electrode connected to the node310, and a second current electrode connected to a node312, where the node312is connected to receive voltage from the second voltage domain204(e.g., voltage VDD2in an active mode). The transistor306includes a gate electrode connected to the node310, a first current electrode connected to the node312, and a second current electrode connected to a node314, where the node314is connected to the corresponding word line (e.g., WL0) of the bit cell array120(FIG. 2). The transistor308includes a gate electrode connected to the node310, a first current electrode connected to the node314, and a second current electrode connected to the voltage reference VSS(e.g., ground).

In operation, the output voltage of the node314, and thus the word line WL0, is dependent on the PredA[0] and PredB[0] bit values. The transistor302acts as a final decode of PredA and PredB in that when the corresponding bit of each of PredA and PredB assigned to the word line driver300are asserted (PredA[0] and PredB[0] in the illustrated example), the node310is pulled to a lower voltage potential and node314is pulled to substantially the same voltage potential as node312, thereby resulting in the assertion of the word line WL0. Otherwise, if either of the corresponding bits are unasserted, the node310is pulled to a voltage potential substantially equal to the voltage VDD2, thereby causing the node314to be pulled to a voltage potential substantially equal to the voltage VSS, which results in the word line WL0 being unasserted.

As illustrated, the word line driver300implements level shifting in that the input signals (e.g., PredA[0] and PredB[0]) are based on the lower voltage VDD1of the voltage domain202(FIG. 2), whereas the output of the word line driver300drives the corresponding word line based on the higher voltage VDD2of the voltage domain204(FIG. 2). Due to the relatively low number of transistors used to implement both the final decoding of the PredA and PredB value and to drive the corresponding word line, the word line driver300can be utilized in memories having relatively small pitches.

Referring toFIG. 4, an alternate implementation of a word line driver400is illustrated in accordance with at least one embodiment of the present disclosure. The word line driver400includes the transistors302,304,306and308connected as described above with respect to the word line300ofFIG. 3, except that the second current electrode of the transistor304is connected to a third voltage domain having voltage VDD3, such that the word line driver400can shift between the more than two voltage domains, thereby allowing voltage VDD2to be reduced to a voltage potential substantially equivalent to the voltage VSSduring a low-power mode, which reduces current leakage in the word line driver400while in the low-power mode.

Referring toFIG. 5, another exemplary implementation of the memory102ofFIG. 1is illustrated in accordance with at least one embodiment of the present disclosure. In the depicted example, the memory102includes a latch502, global predecode circuitry504, a global word line driver circuitry506, local predecode circuitry508, a plurality of local word line driver circuitries (including level shifting circuitry), such as local word line drivers510,512, and514, and a plurality of local bit cell arrays, such as local bit cell arrays520,522, and524. The latch502, the global predecode circuitry504, the global write line driver506and the local predecode circuitry508are operated in a voltage domain530(operating voltage VDD1). The local word line drivers510,512, and514and the local bit cell arrays520,522and524are operated in a voltage domain532(operating voltage VDD2).

In the depicted implementation, the latch502includes a first input to receive the row address value208, a second input to receive the clock signal210, and a plurality of outputs, each output providing a latched representation of a corresponding bit value of the row address value208responsive to the clock signal210. For purposes of illustration, it is assumed that the row address value208is a six bit value and the latch502therefore provides six latched output bits.

The global predecode circuitry504includes an input to receive the latched row address bits and an output to provide a first set of predecode bit values (e.g., PredA) based on the latched row address bits. Likewise, the local predecode circuitry508includes an input to receive the latched row address bits and an output to provide a second set of predecode bit values (e.g., PredB) based on the latched row address bits.

The global word line driver circuitry506includes an input connected to the output of the global predecode circuitry504to receive the first set of predecode bit values. The global word line driver circuitry506further includes a plurality of outputs, each output connected to a corresponding global word line (e.g., global word lines540,542, and544), where a particular global word line is asserted by the global word line driver circuitry506during any given access cycle based on the values of the first set of predecode bits received at the global word line driver circuitry506. In the illustrated example, the global word line driver circuitry506is connected to N global word lines (GWL[0]-GWL[N−1]).

Each of the local word line driver circuitries includes a first input connected to a corresponding global word line and a second input connected to the local predecode circuitry508to receive the second set of predecode bits. Each of the local word line driver circuitries further includes a plurality of outputs, each output connected to a corresponding local word line of the corresponding local bit cell array, where the particular local word line is asserted by a local word line driver circuitry during any given access cycle is based on the values of the second set of predecode bits and further based on which of the global word lines is asserted by the global word line driver circuitry506. To illustrate, the local word line driver circuitry510includes an input connected to GWL[0] and a plurality of outputs connected to the N local word lines (LWL[0]-LWL[N−1]) of the local bit cell array520, the local word line driver circuitry512includes an input connected to GWL[1] and a plurality of outputs connected to the N local word lines (LWL[0]-LWL[N−1]) of the local bit cell array522, and the local word line driver circuitry514includes an input connected to GWL[N−1] and a plurality of outputs connected to the N local word lines (LWL[0]-LWL[N−1]) of the local bit cell array524.

As noted above, the latch502, the global predecode circuitry505, the global write line driver circuitry506and the local predecode circuitry508are operated in a different voltage domain than the local word line driver circuitries and the local bit cell arrays. Accordingly, the transistors of the circuitry operated in the voltage domain530are implemented using a thinner gate oxide so the circuitry of the voltage domain530can be operated at a lower voltage for VDD1, whereas the transistors of the circuitry operated in the voltage domain532are implemented using a thicker gate oxide so that the circuitry of the voltage domain532can be operable at a higher voltage (as well as being less susceptible to leakage current). However, as the voltage VDD2provided to the local word line driver circuitries and the local bit cell arrays is greater than the voltage VDD1supplied to the peripheral circuitry to take advantage of the benefits of the different transistor voltage and leakage characteristics, a voltage difference is present between the voltage level of the output of the local predecode508and the global word lines and the voltage level that the local word line driver circuitries drive onto a local word line. Accordingly, the local word line driver circuitries implement level shifters for each of the local word lines LWL[0]-LWL[N—1]. Exemplary implementations of a word line driver of the word line driver circuitries for a corresponding word line were illustrated in greater detail with reference toFIGS. 3 and 4. In these implementations, the input value from the corresponding global word line can serve as the input to either the gate electrode or the first current electrode of the transistor302(FIGS. 3 and 4), while the corresponding predecode bit value from the local predecode circuitry508serves as the input to the other of the gate electrode or the first current electrode of the transistor302.

It will be appreciated that the use of local word line drivers partitions an array of bit cells into blocks and allows only a fraction of the cells along the global word line to be selected. By enabling the selection of fewer cells, less power is consumed by the memory. Further, the global word line driver can be implemented in the domain of VDD1using transistors having a thinner gate oxide thickness, which increases the speed of the transistors and permits a lower operational voltage, thereby improving the speed and power consumption of the memory.

Other embodiments, uses, and advantages of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. To illustrate, although exemplary voltages and gate oxide thicknesses have been described herein, these values are exemplary only and alternate embodiments may have any number of voltage domains, any number of different voltage levels, and any number of different gate thicknesses. The specification and drawings should be considered exemplary only, and the scope of the disclosure is accordingly intended to be limited only by the following claims and equivalents thereof.