Methods of modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device

Methods for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device, and methods for fabricating an integrated circuit, are provided. In an embodiment, a method includes providing a circuit design layout that has a plurality of element patterns. A first library of problematic sections is provided. An initial circuit section and an additional circuit section within the circuit design layout are determined to match problematic sections in the first library, and the initial and additional circuit sections have overlapping peripheral boundaries. A second library of replacement sections is provided. The replacement sections correspond to the problematic sections. The circuit sections that match the problematic sections are replaced with a replacement section that corresponds to the respective problematic sections to form the final circuit layout. Boundary characteristics of the replacement sections are substantially the same as the circuit sections replaced thereby.

TECHNICAL FIELD

The technical field generally relates to methods for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device, and more particularly relates to methods that include identifying and replacing problematic element patterns in a circuit design layout to form a final circuit layout that is used to generate a mask employed to form the semiconductor device.

BACKGROUND

Modern integrated circuits (ICs), can include millions of transistors fabricated in and on a semiconductor substrate. In making a mask to fabricate such a complex device, a circuit design layout will pass through a variety of filters, checks, and modifications before being taped out to a mask. Ideally, the process results in a mask that is used to lithographically fabricate a final circuit design layout on a semiconductor substrate without printing defects and without defects in the fabricated final circuit layout.

The circuit design layout may contain standard cells and standard device designs as well as new cell and device designs, and generally complies with rigid design rules that include minimum feature size, minimum spacing between device elements, and the like. To improve functional and yield characteristics of the circuit design layout, the circuit design layout generally passes through multiple simulations, many of which are time consuming. Short cuts are available to reduce simulation time, and hence cost, without sacrificing accuracy of the final circuit layout. One method for providing approximate but fast evaluation of sensitivity of the circuit design layout to lithographic effects that can affect variability and yield is pattern matching. Pattern matching is particularly known for use to determine lithographic or printability problems. Printability problems are problems in which a circuit design layout on a mask, for example a particular array of lines and spaces, cannot be accurately reproduced in or on a semiconductor substrate by etching through the circuit design layout on the mask. In conventional pattern matching techniques, element patterns in the circuit design layout that are known to cause printability problems are first identified by comparing element patterns in the circuit design layout at sensitive locations to a library of problematic element patterns. The library of problematic element patterns is generally developed in collaboration between a design house and their foundry partner and is further recorded to enable the problematic element patterns to be avoided in implementing future designs or design revisions. In practice, an evolving layout pattern can be subjected to pattern matching software to identify patterns in the layout design that are similar to the library patterns.

Upon identifying element patterns in the circuit design layout that are similar to problematic element patterns in the library, existing techniques involve changing the problematic element patterns through a global rule change that is applied based upon the identified defect in the problematic element pattern. In particular, the global rule change involves modifying a particular design parameter that is responsible for the problems associated with particular problematic element features, with the modification applied across the entire circuit design layout. However, the global approach to modifying the entire circuit design layout may result in modifications to the circuit design layout that may be unnecessary or that may cause unintended problems at various locations within the circuit design layout.

Accordingly, it is desirable to provide methods for modifying the physical design of an electrical circuit used in the manufacture of a semiconductor device that enables a local approach to alleviating problematic element patterns and that avoids unintended modifications to the circuit design layout that may be unnecessary or that may cause unintended problems after modification of the problematic element patterns. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

BRIEF SUMMARY

Methods for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device, and methods for fabricating an integrated circuit, are provided. In an embodiment, a method for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device includes providing a circuit design layout that has a plurality of element patterns. A first library is provided that includes problematic sections that include a problematic element pattern. The first library is stored in a storage medium. An initial circuit section that includes an element pattern within the circuit design layout, and that includes a peripheral boundary, is determined to match a problematic section in the first library using a computer processor that is in communication with the storage medium. Another circuit section that includes another element pattern within the circuit design layout is determined to match another problematic section in the first library using the computer processor that is in communication with the storage medium. The other circuit section includes a peripheral boundary that overlaps the peripheral boundary of the initial circuit section. A second library of replacement sections is provided and stored in the storage medium. The replacement sections include a replacement element pattern and correspond to the problematic sections. Only the circuit sections that match the problematic sections are replaced with a replacement section that corresponds to the respective problematic sections using the computer processor to form a final circuit layout including the replacement sections and original sections of the circuit design layout.

In another embodiment, a method for fabricating an integrated circuit includes providing a circuit design layout for a mask. The circuit design layout has a plurality of element patterns. A first library is provided that includes problematic sections that include a problematic element pattern. The first library is stored in a storage medium. An initial circuit section that includes an element pattern within the circuit design layout, and that includes a peripheral boundary, is determined to match a problematic section in the first library using a computer processor that is in communication with the storage medium. Another circuit section that includes another element pattern within the circuit design layout is determined to match another problematic section in the first library using the computer processor that is in communication with the storage medium. The other circuit section includes a peripheral boundary that overlaps the peripheral boundary of the initial circuit section. A second library of replacement sections is provided and stored in the storage medium. The replacement sections include a replacement element pattern and correspond to the problematic sections. The circuit sections that match the problematic sections are replaced with a replacement section that correspond to the respective problematic sections using the computer processor. Boundary characteristics of the replacement sections are substantially the same as the circuit sections replaced by the replacement sections. The mask including the replacement sections and original sections of the circuit design layout is generated to transfer a final circuit layout to the mask. The mask is employed to implement the final circuit layout in or on a semiconductor substrate of the integrated circuit.

In another embodiment, a method for fabricating an integrated circuit includes providing a circuit design layout for a mask. The circuit design layout has a plurality of element patterns. A first library is provided that includes problematic sections that include a problematic element pattern having a known printing or electrical problem associated with the problematic element pattern. The first library is stored in a storage medium. A determination is sequentially made whether circuit sections that include element patterns within the circuit design layout match aproblematic section in the first library using a computer processor in communication with the storage medium. An initial circuit section matches a problematic section in the first library and another circuit section that includes another element pattern within the circuit design layout matches another problematic section in the first library. The other circuit section includes a peripheral boundary that overlaps the peripheral boundary of the initial circuit section. At least one of the initial replacement section or the other replacement section contains at least one new vertex that is confined within a peripheral boundary thereof. The at least one new vertex is also within a peripheral boundary of the overlapping circuit section. A second library of replacement sections is provided and stored in the storage medium. The replacement sections include a replacement element pattern and correspond to the problematic sections. Circuit sections that have fewer new vertices within the peripheral boundary of the overlapping circuit section and that match a problematic section are replaced with replacement sections that correspond to the problematic sections using the computer processor before replacing circuit sections that have more new vertices within the peripheral boundary of the overlapping circuit section. Boundary characteristics of the replacement sections are substantially the same as the circuit sections that are replaced by the replacement sections. The mask including the replacement sections and original sections of the circuit design layout is generated to transfer a final circuit layout to the mask. The mask is employed to implement the final circuit layout in or on a semiconductor substrate of the integrated circuit.

DETAILED DESCRIPTION

Methods for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device, such as an integrated circuit, are provided herein. The methods provided herein enable identification and alleviation of problematic element patterns within a circuit design layout, i.e., a new or candidate circuit pattern that is proposed for implementing into a semiconductor device, using a pattern-based approach. Problematic element patterns may include element patterns that present printing difficulties and/or an electrical problem when the element pattern is transferred in or on a semiconductor substrate of the semiconductor device. To alleviate the problematic element patterns within the circuit design layout, the methods provided herein enable replacement of the problematic elements patterns with a replacement pattern, which is implemented locally for each identified problematic element pattern. In this regard, replacement of the problematic element patterns is conducted through a pattern-based approach that is independently conducted for each instance of different problematic element patterns in the circuit design layout, as opposed to alleviating the problematic element patterns with a rules-based approach that modifies similar element patterns globally across the circuit design layout. Further, the methods described herein enable overlapping problematic sections that are identified in the circuit design layout to be replaced while minimizing potential defects that could result from replacement of the overlapping problematic sections. The pattern-based approach avoids unintended modifications to the circuit design layout that may be unnecessary or that may cause unintended problems at various locations after modification of the problematic element patterns.

An embodiment of a method for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device will now be described with reference toFIG. 1. The method for modifying the physical design of the electric circuit is conducted before the tape-out of a mask or masks for purposes of transferring the physical design into an underlying substrate. A “mask” as referred to herein is a medium that transfers its image (patterns on the mask) on a photoresist coating over a semiconductor substrate. Semiconductor devices for which the mask can be used include any such devices where pattern etch through a mask is employed, such as for purposes of forming vias and trenches that are later filled to form an electrical circuit in the semiconductor devices.

Referring toFIG. 1, the method begins by providing a circuit design layout in block100. The circuit design layout210, as referred to herein and momentarily referring toFIG. 2, is a candidate or preliminary pattern that is proposed for implementing into the semiconductor device, such as an integrated circuit, and that is represented in a two-dimensional plane212in the form of lines214that form element patterns. In an embodiment, the circuit design layout is generated using a computer program that is executed by a computer processor, and the circuit design layout may be stored within a storage medium that is in electrical communication with the computer processor.

In an embodiment and as shown at block104inFIG. 1, a first library of problematic sections that include a problematic element pattern is provided. Problematic element patterns, as referred to herein, refer to element patterns that have a known problem associated therewith. Problems that are associated with the problematic element patterns are not particularly limited and can be any problem that would make identification of and replacement of the problematic element patterns desirable. Examples of problems that may make replacement of the problematic element patterns desirable include, but are not limited to, printing problems or electrical problems in an electrical circuit that are formed in the shape of the element patterns. The first library of problematic sections that include a problematic element pattern can be stored in the storage medium that is in electrical communication with the computer processor, thereby enabling the computer processor to access the first library. In accordance with the methods described herein, the first library can be built or can be obtained from an outside service provider, and the problematic sections in the first library can be created using simulation results or using results from actual implementation of element patterns where problems are experienced, such as by fabricating physical test structures.

Referring to block106inFIG. 1, the method further includes determining if a circuit section or circuit sections match a problematic section in the first library using the computer processor that is in communication with the storage medium. As alluded to above and with reference toFIG. 2, the circuit design layout210has a plurality of element patterns220that, together, form the circuit design layout210. In an embodiment, the circuit section216includes an element pattern220within the circuit design layout210. In other embodiments and although not shown, the circuit section may include the entire circuit design layout210. As referred to herein, determining if the circuit section matches a problematic section includes comparing problematic sections from the first library to various element patterns across the circuit design layout210, and identifying a circuit section216based on a confirmed match. Referring again toFIG. 2, the circuit section216includes a peripheral boundary218in the two-dimensional plane212, with the element pattern220contained within the peripheral boundary218. In particular, the circuit section216includes the element pattern220that represents a sufficiently small portion of the overall circuit design layout210that can be analyzed to determine if any of the features in the element pattern220are problematic. It is to be appreciated that the peripheral boundary218can have any shape, including a polygonal shape or a circular shape, and that the shape of the peripheral boundary18will generally correspond to a shape of the problematic section from the first library. Referring toFIG. 2, although the peripheral boundary218of the circuit section216is shown in a polygonal shape, it is to be appreciated that similar or different shapes may be employed for different circuit sections across the circuit design layout210. Although the circuit section216as referred to herein is not limited, the method described herein is most useful when the element pattern220that is included in the circuit section216includes at least one confined vertex222within the circuit section216. As referred to herein, a “confined vertex” refers to a corner or intersection of elements of the element pattern220that is wholly contained within the peripheral boundary218of the circuit section216, i.e., the confined vertex222does not lie on the peripheral boundary218. The methods described herein are particularly useful when the element pattern220within the circuit section216includes at least two different elements therein, e.g., two different lines214that do not contact each other, which enables interrelationships between the elements in the element pattern220to be analyzed for problems. In an embodiment and referring toFIG. 2, the peripheral boundary218of the circuit section216intersects at least one element of the circuit design layout210, thereby creating a new vertex224between the peripheral boundary218and the element of the circuit design layout210at each instance where the peripheral boundary218intersects elements of the circuit design layout210, with the new vertices224lying on the peripheral boundary218.

As referred to herein, a match between a circuit section and a problematic section is confirmed when elements in the element pattern that is contained in the circuit section are identical to or fall within a pre-set deviation range from a particular problematic section. Physical pattern matching may be employed to determine if a circuit section or circuit sections match a problematic section in the first library, as described above. For example, in an embodiment, problematic sections are compared to circuit sections that have the same confined vertex or vertices as the problematic sections as one measure that is employed to determine if a match or mis-match exists. In a further embodiment, when the problematic sections include at least two different elements, the problematic sections are compared to circuit sections that have the same number of elements to determine if a match exists using the computer processor. In yet a further embodiment, when the peripheral boundary of the problematic element patterns intersect at least one element of a circuit design layout, the problematic element patterns are compared to circuit sections that have a peripheral boundary that intersects the at least one element of the circuit design layout in the same manner as the problematic element patterns. Various measurements of distances between the peripheral boundary of the circuit section and element pattern contained therein may be employed to determine whether a match to a problematic section exists, and various measurements of distances between elements in the circuit section can also be employed for purposes of determining whether a match to a problematic section exists. It is to be appreciated that a range of the various distance measurements may be established whereby a value within the range represents a sufficient match between circuit sections and problematic element sections, thereby creating a buffer that enables identification of a match for circuit sections and problematic element sections without requiring an identical physical match.

In an embodiment and as shown inFIG. 1, a determination is made if a circuit section matches a problematic section in the first library in block106, followed by sequentially determining if other circuit sections match problematic sections in the first library. The method provided herein generally involves determining if a plurality of circuit sections matches problematic sections in the first library to enable blanket coverage of the circuit design layout. In this manner, a determination can be made of whether circuit sections match problematic sections across the circuit design layout to effectively break up the circuit design layout into smaller units that can be more readily analyzed. Furthermore, determinations are made on whether overlapping circuit sections match problematic sections, which enables more complete testing of the element patterns across the entire circuit design layout. For example, in an embodiment and as shown inFIG. 2, an initial circuit section216including an element pattern within the circuit design layout210is determined to match a problematic section, and another circuit section217that includes another element pattern within the circuit design layout210is determined to match another problematic section in the first library, with the other circuit section217including a peripheral boundary219that overlaps the peripheral boundary218of the initial circuit section216. As referred to herein, the terms “initial” and “another” that are used when referring to the circuit sections216,217merely serve to distinguish an earlier circuit section that is determined to match a problematic section from a later circuit section that is determined to match a problematic section, and it is to be appreciated that further circuit sections may be determined to match problematic sections from the first library either before or after the “initial” circuit section is determined to match a problematic section. While at least some of the circuit sections overlap, it is to be appreciated that some of the circuit sections can be completely independent of other circuit sections. As described in further detail below, conflict resolution techniques are provided in accordance with the methods described herein that enable complications from circuit section overlap to be avoided.

Referring to block108inFIG. 1, a second library of replacement sections is provided, with the replacement sections including replacement element patterns. The replacement sections correspond to the problematic sections in the first library and enable one or more problems that are associated with the problematic sections to be alleviated. As referred to herein, the replacement sections correspond to the problematic sections by providing the same functionality as the problematic sections but also incorporate a design change in the element pattern that alleviates one or more problems that are associated with the corresponding problematic sections. By providing the replacement sections in the second library that correspond to the problematic sections, the method described herein provides a pattern-based approach to replacement of the problematic sections in the circuit design layout. In an embodiment, the replacement patterns in the replacement sections correspond to the problematic sections in that at least boundary characteristics of the replacement section are substantially the same as the problematic section, and by extension the circuit section that is replaced by the replacement section, so that the same elements that intersect the peripheral boundary of the circuit section also intersect the peripheral boundary of the replacement section in substantially the same location, thereby minimizing stitching complications that could otherwise result from replacement of the circuit section. In an embodiment, the second library is stored in the storage medium and is accessible by the computer processor so that, upon determination that a circuit section matches a problematic section in the first library, the second library is available to enable replacement of the circuit section with the appropriate replacement section.

In accordance with the methods described herein, the second library of replacement sections may be provided by building the second library of replacement sections based upon identified solutions for the problematic sections. Alternatively, the second library of replacement sections can be obtained from an outside service provider. The replacement sections in the second library can be created by determining fixes to individual problematic element patterns, and implementing the fixes into the problematic sections to generate replacement sections. The replacement sections may be created by using simulation results or by using results from actual implementation of modifications to problematic element patterns, such as by fabricating physical test structures. For example, the second library can be built by creating variants of the element pattern in the corresponding problematic sections and performing printability simulations, with suitable replacement sections identified for problematic sections based upon the results of the printability simulations.

After determining that one or more circuit sections match problematic sections from the first library, and as shown in block110inFIG. 1, the exemplary method proceeds with replacing circuit sections that match problematic sections with a replacement section that corresponds to the respective problematic sections using the computer processor. Replacement of the one or more circuit sections is conducted through a local approach, where only the particular circuit section that is determined to match the problematic section is replaced with a particular replacement pattern. In the local approach, any circuit sections that are to be replaced are individually determined to match a problematic section, and there is no global rule implementation across the circuit design layout for purposes of modifying element patterns within the circuit design layout. In an embodiment, circuit sections that match problematic sections are replaced with replacement sections that correspond to the problematic sections after determining whether the circuit sections match problematic sections. In this manner, conflicts in pattern replacement that may arise due to circuit section overlap can be addressed together based upon which circuit sections require replacement. Further details regarding resolution of conflicts due to overlap of circuit sections that require replacement are described in further detail below. In other embodiments and although not shown, it is to be appreciated that replacement of circuit sections that match problematic sections from the first library may be conducted after a determination is made of whether each circuit section matches a problematic section, i.e., replacement of one circuit section with a replacement section can be conducted before determining whether other circuit sections match problematic sections in the first library in a looped approach to pattern replacement. The looped approach to pattern replacement may be appropriate if no circuit section overlap exists across the circuit design layout.

In an embodiment and referring momentarily toFIG. 4, the replacement section226that corresponds to the problematic section, and by extension the circuit section that is determined to match a particular problematic section, has substantially the same boundary characteristics as the circuit section that is replaced by the replacement section226, with the peripheral boundary228of the replacement section226and the peripheral boundary218of the circuit section shown inFIG. 3. “Boundary characteristics” as referred to herein, refer to layout of element features that cross the peripheral boundaries and affect the geometries thereof. Peripheral boundaries between the circuit section and the replacement section need not be identical to have substantially the same boundary characteristics. As alluded to above, matching of the boundary characteristics between the circuit section and the replacement section ensures that the same elements that cross the peripheral boundary of the circuit section also cross the peripheral boundary of the replacement section in the same location, thereby avoiding stitching complications that could otherwise result from replacement of the circuit section. In an embodiment and as shown inFIGS. 3 and 4, the replacement section (as shown inFIG. 4) has the same number of vertices on the peripheral boundary of the replacement section as the number of vertices on the peripheral boundary of the corresponding problematic section (as shown inFIG. 3). In a further embodiment, the location of the vertices on the peripheral boundary of the replacement section is also the same as the location of vertices on the peripheral boundary of the corresponding problematic section. In yet further embodiments, although not shown in the Figures, the element pattern in a particular circuit section may include an electrical interconnect that is provided to establish electrical connection between overlying elements and underlying elements relative to the circuit design layout, i.e., the electrical interconnect provides an electrical connection between the overlying element and the underlying element relative to the circuit design layout. In this embodiment, the replacement section also includes the electrical interconnect in the same location as the circuit section that is replaced thereby to maintain the connectivity provided by the position of the electrical interconnect within the circuit section that is replaced by the replacement section.

In an embodiment and as shown inFIGS. 3 and 4, at least one of the replacement sections226is smaller than the circuit section216that is replaced by the replacement section226. For example, the replacement section226may be reduced in dimension relative to the circuit section216on sides of the replacement section226where the peripheral boundary228of the replacement section226intersects at least one element of the circuit design layout210. By providing the replacement section226that is smaller than the circuit section216, and particularly with the replacement section226reduced in dimension relative to the circuit section216on sides where the peripheral boundary228of the replacement section226intersects at least one element of the circuit design layout, the circuit section216can be replaced with the replacement section226without impacting other elements of the circuit design layout that are adjacent to the circuit section216that is replaced while still effectively alleviating problems that are associated with the problematic element pattern220to be replaced.

While the replacement sections that correspond to the problematic sections have substantially the same boundary characteristics, the replacement section generally has a different internal element pattern from the problematic section, and by extension the circuit section that is replaced by the replacement section, which alleviates one or more of the problems associated with the problematic element pattern in the problematic section. In an embodiment and referring momentarily toFIG. 4, at least one of the replacement sections226that replace the circuit sections includes a replacement pattern232that has a new vertex230in the replacement pattern232, and the replacement pattern232may include a plurality of new vertices230. The new vertices230are confined within the peripheral boundary228of the replacement section226, which avoids boundary complications that may otherwise result if any of the new vertices230were to be located on the peripheral boundary228. In an embodiment, the replacement sections226that replace the circuit sections do not modify the electrical connectivity within the circuit sections, meaning that electrical connectivity both within the circuit design layout remains the same between the replacement section and the circuit section replaced thereby, and also that electrical connectivity to overlying elements and the underlying elements relative to the circuit design layout also remain the same between the replacement section and the circuit section replaced thereby.

Optionally, after replacement of any circuit sections that match problematic sections and as shown inFIG. 1, further determinations of whether the circuit sections match problematic sections can again be conducted to verify that the replacement sections do not give rise to other problems. Once it is determined that no further circuit sections match problematic sections, a final circuit layout is generated that includes any replacement sections along with original circuit sections from the circuit design layout. In an embodiment, a mask may then be generated for the final circuit layout as shown in block112inFIG. 1, with the final circuit layout transferred to the mask. Techniques for generating a mask from a circuit design layout are known in the art and can be conducted using the computer processor in conjunction with patterning tools. In an embodiment, the mask is generated by transferring the circuit design layout into a first mask layer, such as through a lithography technique. Suitable lithography techniques include photolithography, embossing, nanoimprinting, and the like. In an embodiment, the replacement sections are transferred into the first mask layer concurrent with transferring the circuit design layout into the first mask layer, with the replacement sections supplanting problematic elements of the circuit design layout in the first mask layer. In another embodiment, the replacement sections are transferred separate from the circuit design layout. For example, the replacement sections may be transferred into a second mask layer that overlies the first mask layer, with the second mask layer including the element patterns of the replacement sections as modifications to the circuit design layout in the first mask layer. In all embodiments, the mask includes the final circuit layout therein.

As indicated in block114, the method further includes employing the mask generated in block112to transfer a final circuit layout to the mask. The mask is employed to fabricate the semiconductor device by implementing the final circuit layout in or on a semiconductor substrate. The semiconductor substrate may be included, for example, in an integrated circuit. An exemplary manner in which the mask may be employed to implement the final circuit layout in or on the semiconductor substrate includes transferring the final circuit layout through the mask to a photoresist layer over the semiconductor substrate, followed by etching the semiconductor substrate or a layer that overlies the semiconductor substrate through the final circuit layout in the photoresist layer to form an etched pattern in or on the semiconductor substrate. The etched pattern may then be filled to form an electrical circuit in or on the semiconductor substrate, consistent with known integrated circuit fabrication techniques.

An exemplary embodiment of a method for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device will now be described with reference toFIGS. 2-4. As shown inFIG. 2and as alluded to above, a circuit design layout210is provided with a plurality of element patterns that are formed by lines214. A circuit section216that is determined to match a problematic section in the first library includes an element pattern220without a peripheral boundary218of the circuit section216extending longitudinally within elements in the element pattern220, i.e., the shape of the circuit section216that matches a problematic section has the peripheral boundary218that intersects elements in the element pattern220but is largely located within pattern-free portions. While the circuit section216that matches a problematic section has a polygonal shape in the embodiment shown inFIG. 2, it is to be appreciated that the shape is arbitrary, based upon particular problematic patterns in the first library to which the circuit sections are determined to match, and is not limited to the configuration shown. Referring toFIG. 3, in this example, the decision is made that replacement of the circuit section216that matches a problematic section is required. The hatched line inFIG. 3represents a shortened peripheral boundary228of the replacement section226, as represented inFIG. 4, with the replacement section226reduced in dimension relative to the circuit section216on sides of the replacement section226where the peripheral boundary228of the replacement section226intersects elements of the circuit design layout. The replacement section226includes ten new vertices230that are confined within the peripheral boundary228of the replacement section226. The mask is then generated with the replacement section226, and with original sections of the circuit design layout that are not replaced, in the manner described above.

Another exemplary embodiment of a method for modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device will now be described with reference toFIGS. 5-7. In this embodiment, the method is identical to the method described above in the context ofFIG. 1but provides for additional conflict resolution functionality in the event of circuit section overlap. As shown inFIG. 6, a circuit design layout510is provided with a plurality of element patterns that are formed by lines514. However, in this embodiment, an initial circuit section516and another circuit section517within the circuit design layout510are determined to match a problematic section in the first library, with the decision made that replacement of the initial circuit section516and the other circuit section517is required. For purposes of the instant application and referring toFIGS. 6 and 7, a conflict is determined to exist when the other circuit section517overlaps the initial circuit section516, the initial replacement section526or an other replacement section527contains a new vertex that is confined within a peripheral boundary thereof, and when the new vertex is also within a peripheral boundary of the overlapping circuit section216,217. For example and as shown inFIG. 6, the other circuit section517overlaps the initial circuit section516to illustrate conflict resolution techniques that may be employed in accordance with the method shown inFIG. 5, which enables complications from circuit section overlap to be avoided. Referring toFIG. 5, after determining that a circuit section matches a problematic section, a determination is made if a conflict exists between matched circuit sections, as shown in block107. For example, as shown inFIG. 7, the initial replacement section526is determined to be in conflict with the other replacement section527because a replacement element pattern532in the initial replacement section526includes new vertices530that also lie within the other replacement section527. However, the other replacement section527is not in conflict with the initial replacement section526because no new vertices531of the other replacement section527lie within the initial replacement section526.

As shown inFIG. 5at block109, conflicts are resolved prior to replacing the matched circuit sections that are determined to match a problematic section. To determine order of replacement under circumstances where there is a conflict, one of the circuit sections that has the least number of new vertices within the peripheral boundary of the overlapping circuit section are replaced before replacing circuit sections that have more new vertices within the peripheral boundary of the overlapping circuit section. In the embodiment shown inFIGS. 6 and 7, the other replacement section527has no new vertices within the peripheral boundary of the initial circuit section516, whereas the initial replacement section526has new vertices within the peripheral boundary of the other circuit section517. As such, the other circuit section517is replaced prior to replacing the initial circuit section516because the other replacement section527will not impact the initial replacement section526. Such an approach may enable simple, automated conflict resolution; however, it is to be appreciated that other conflict resolution techniques may be employed to ensure that conflicts do not give rise to further problems upon replacement of conflicting circuit sections with replacement sections. Although not shown, it is to be appreciated that in other embodiments, one or more of the circuit sections may overlap multiple other circuit sections, with the circuit sections containing new vertices confined within a peripheral boundary thereof that are also within a peripheral boundary of multiple other overlapping circuit sections. In these embodiments, one of the circuit sections having no new vertices within the peripheral boundary of the overlapping circuit sections are replaced before replacing circuit sections that have the new vertices within the peripheral boundary of the overlapping circuit sections, with circuit sections having the least number of new vertices that are also within a peripheral boundary of other overlapping circuit sections replaced before circuit sections that have greater numbers of new vertices that are also within a peripheral boundary of other overlapping circuit sections.