Optoelectronic device comprising an active photonic interposer to which a microelectronic chip and an electro-optical conversion chip are connected

The invention relates to an optoelectronic device comprising a photonic interposer comprising: a photonic circuit containing at least one active optical component, an upper interconnect layer comprising at least one upper control portion, a lower interconnect layer comprising at least one lower control portion and lower intermediate portions, at least one TSV directly connecting the upper control portion to the lower control portion, conductive vias connecting the lower intermediate portions to the active optical component; at least one first microelectronic chip joined to the upper face of the photonic interposer; a second microelectronic chip joined to the lower face of the photonic interposer, and connected to the lower control portion and to the lower intermediate portions.

TECHNICAL FIELD

The field of the invention is that of optoelectronic devices comprising an active photonic interposer, that is to say an interposer comprising a photonic circuit with active optical components, and to which microelectronic chips are mechanically joined and electrically connected. The invention is applicable in particular in the field of high-performance computing.

PRIOR ART

Interposers are one-piece devices to which microelectronic chips are mechanically joined and electrically connected. Such chips may be CMOS integrated circuits, and may comprise electronic components such as transistors, resistors, capacitors, etc. They may be computing chips, memory chips, electro-optical conversion chips or the like. Such interposers may be produced based on silicon.

These interposers may be said to be photonic when they comprise a photonic circuit formed of passive optical components (waveguides, multiplexers, etc.) and possibly active optical components (modulators, diodes, etc.). It is known that an optical component is said to be active when it comprises at least one electrical terminal. When an active photonic interposer is involved, at least one electro-optical conversion microelectronic chip provides the electronic interface between another microelectronic chip and the active optical components.

The article by Thonnart et al. entitledPOPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based3D Integrated Systemsdescribes one example of an optoelectronic device comprising a silicon-based active photonic interposer, through which there extends a photonic circuit comprising active optical components (modulators, filters or photodiodes). Computing chips and electro-optical conversion chips are joined and connected to the photonic interposer on the upper face thereof. However, there is a need to improve the performance of such an optoelectronic device.

DISCLOSURE OF THE INVENTION

One aim of the invention is to at least partially rectify the drawbacks of the prior art, and more particularly to propose an optoelectronic device, with an active photonic interposer, exhibiting improved performance.

To this end, one subject of the invention is an optoelectronic device comprising:a photonic interposer, having an upper face and an opposite, lower face, produced based on silicon, and comprising: a photonic circuit containing at least one active optical component, and an upper interconnect layer, defining the upper face, and comprising at least one first upper conductive control portion;at least one first microelectronic chip, joined to the upper face and connected to the first upper conductive control portion, intended to transmit or receive an electrical signal to or from a second microelectronic chip;the second microelectronic chip, called electro-optical conversion chip, joined and connected to the photonic interposer, which provides the electrical connection of the second microelectronic chip to the active optical component, on the one hand, and to the first microelectronic chip, on the other hand.

According to the invention, the photonic interposer comprises: a lower interconnect layer, defining the lower face, comprising at least one first lower conductive control portion, and first lower conductive intermediate portions; at least one through-silicon via directly connecting the first upper conductive control portion to the first lower conductive control portion; conductive vias connecting the first lower conductive intermediate portions to the active optical component. In addition, the second microelectronic chip is joined to the lower face, and is connected to the first lower conductive control portion, on the one hand, and to the first lower conductive intermediate portions, on the other hand.

Some preferred but non-limiting aspects of this optoelectronic device are as follows.

The photonic interposer may comprise a stack of layers, including a thick silicon layer and an optical layer in which the photonic circuit is formed, the thick silicon layer being situated towards the upper face and the optical layer being situated towards the lower face.

The photonic interposer may comprise a dielectric layer made of a silicon oxide, and situated between and in contact with the thick layer and the optical layer.

The photonic interposer may comprise first lower conductive power supply portions situated at the lower face and connected to an electric power source of the first microelectronic chip, and upper conductive power supply portions situated at the upper face and connected to the first lower conductive power supply portions by through-silicon vias. And the first microelectronic chip may comprise conductive power supply portions connected to the upper conductive power supply portions.

The photonic interposer may comprise second lower conductive power supply portions situated at the lower face and connected to an electric power source of the second microelectronic chip, and second conductive intermediate power supply portions situated at the lower face and connected to the second lower conductive power supply portions. And the second microelectronic chip may comprise conductive power supply portions connected to the second conductive intermediate power supply portions.

The photonic interposer may comprise one or more redistribution layers, comprising conductive lines and conductive vias, situated between and in contact with a lower dielectric layer and the lower interconnect layer, the redistribution layer providing the electrical connection between the second conductive intermediate power supply portions and the second lower conductive power supply portions.

The active optical component of the photonic circuit may be chosen from an optical modulator, an optical filter and a photodiode.

The optoelectronic device may comprise external waveguides optically coupled to the photonic circuit of the photonic interposer.

The optoelectronic device may comprise an encapsulating layer extending over the upper face of the photonic interposer and coming into contact with the first microelectronic chip.

The photonic interposer may have a thickness, between its lower and upper faces, of less than or equal to 200 μm.

The optoelectronic device may comprise a plurality of through-silicon vias directly connecting the first upper conductive control portion to the first lower conductive control portion, the first upper conductive control portions being connected to the first microelectronic chip by upper interconnect pads and the first lower conductive control portions being connected to the second microelectronic chip by lower interconnect pads, the upper interconnect pads and the lower interconnect pads being arranged with a pitch less than or equal to 40 μm.

The second microelectronic chip may be joined to the photonic interposer by way of lower interconnect pads, the latter being in contact with the second microelectronic chip and the photonic interposer.

The photonic interposer may rest on a power supply support by way of power supply pads whose thickness is greater than that of the second microelectronic chip.

The invention also relates to a method for manufacturing an optoelectronic device according to any one of the above features, comprising the following steps:providing an SOI substrate, comprising a thick silicon layer, a dielectric layer made of a silicon oxide, and a thin silicon layer;producing an optical layer from the thin silicon layer;producing through-silicon vias, in blind openings extending through the optical layer, the dielectric layer, and through part of the thick silicon layer;producing a lower dielectric layer extending over and in contact with the optical layer;producing the lower interconnect layer on a lower dielectric layer;joining a first handle substrate through direct bonding to the lower interconnect layer;thinning the thick silicon layer, so as to open out the through-silicon vias;producing the upper interconnect layer, in conductive portions in contact with the through-silicon vias;removing the first handle substrate.

The manufacturing method may comprise the following steps:before removing the first handle substrate, joining the first microelectronic chip to the upper interconnect layer, and depositing an encapsulating layer that covers the upper face;joining a second handle substrate to a free planar face formed by the first microelectronic chip and the encapsulating layer, and removing the first handle substrate;removing the second handle substrate;joining the second microelectronic chip.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

In the figures and in the remainder of the description, the same references have been used to designate identical or similar elements. In addition, the various elements are not shown to scale so as to improve the clarity of the figures. Moreover, the various embodiments and variants are not mutually exclusive and may be combined with one another. Unless otherwise indicated, the terms “substantially”, “around” and “of” the order of mean to within 10%, and preferably to within 5%. Moreover, the terms “between . . . and . . . ” and equivalents mean that the bounds are included, unless indicated otherwise.

FIG.1is a schematic and partial cross-sectional view of an optoelectronic device1according to one embodiment.FIG.2is a detailed view of the optoelectronic device1illustrated inFIG.1(in which only one microelectronic chip20is illustrated), andFIGS.3A and3Bare plan views of various parts of the optoelectronic device1illustrated inFIG.2.

In general, the optoelectronic device1comprises microelectronic chips20,30that are joined and connected to one another by way of a photonic interposer10, and in this case at least one first microelectronic chip20connected to at least one second microelectronic chip, called electro-optical conversion chip30. The optoelectronic device1may be intended for high-performance computing, or even be used in the field of Ethernet switches for datacom transmission applications between devices using optical fibers.

A direct orthogonal three-dimensional coordinate system XYZ is defined here and for the remainder of the description, in which the X- and Y-axes form a plane parallel to the main plane of the photonic interposer10, and in which the +Z direction is oriented from the conversion chip30to the microelectronic chip20. In the remainder of the description, the terms “lower” and “upper” are understood to relate to positions of increasing distance from the conversion chip30in the +Z direction.

The photonic interposer10is a one-piece device to which multiple microelectronic chips20,30are mechanically joined, and which provides the electrical connection between the microelectronic chips20,30. It is said to be photonic and active since it comprises a photonic circuit14.1containing at least one optical component, such as an optical modulator (for example based on a Mach-Zehnder interferometer or a resonant ring), a tunable optical filter or a photodiode. Finally, it is a silicon interposer since it is produced based on silicon. In other words, it is made mostly of silicon or of a material containing silicon. (e.g. SOI)

Among the microelectronic chips, the optoelectronic device1comprises at least a first microelectronic chip20intended to transmit or receive an electrical signal to or from the second electro-optical conversion microelectronic chip30. This microelectronic chip20is called host chip, and may be a microprocessor, a high bandwidth memory (HBM), a programmable logic circuit (FPGA), an ASIC application-specific circuit or the like. The microelectronic chip30is electrically connected to the active optical component14.2, and therefore also to the first microelectronic chip20. In this example, the photonic interposer10in this case comprises a photonic circuit14.1containing an optical modulator14.2and a photodiode14.3, these two optical components in this case being connected to the same conversion chip30.

The photonic interposer10is therefore a one-piece device having a first face, called upper face10a, and a second, opposing face, called lower face10b. The upper face10aand lower face10beach have a planar surface allowing the mechanical joining of the microelectronic chips20,30.

It is formed of a stack of layers made mostly of silicon or of a material containing silicon. In this example, it is in particular produced from an SOI (silicon on insulator) substrate. It thus comprises, from top to bottom:an upper interconnect layer11, which defines the upper face10aand by way of which the microelectronic chip20is joined and connected to the photonic interposer10;a dielectric layer13.1, preferably produced based on an oxide, nitride or silicon oxynitride;a thick silicon layer12,a dielectric layer13.2, in this case made of a silicon oxide (BOX, for buried oxide),an optical layer14containing the photonic circuit14.1formed of at least one integrated waveguide, and comprising at least one active optical component (in this case an optical modulator14.2and a photodiode14.3);a lower dielectric layer15, preferably produced based on an oxide, nitride or silicon oxynitride;an electrical redistribution layer16, containing conductive vias and conductive lines;a lower interconnect layer17, formed of metal pads, which defines the lower face10band by way of which the conversion chip30is joined and connected to the photonic interposer10.

In this example, the photonic interposer10comprises the redistribution layer16situated close to the lower face10b. It may also comprise a redistribution layer situated close to the upper face10a, between the upper interconnect layer11and the thick layer12, or even integrated into the upper interconnect layer11. As another variant, it might not comprise any redistribution layer, in particular when the microelectronic chips20,30are not supplied with electric power by way of the photonic interposer10, but by way of a wired connection (wire bonding).

The upper interconnect layer11in this case extends over the dielectric layer13.1, which is itself in contact with the thick silicon layer12, and defines the upper face10a. It is formed in this case of distinct conductive portions, made of at least one electrically conductive material, for example gold, titanium, copper, etc., separated from one another in the XY plane by a dielectric material, for example an oxide, nitride or silicon oxynitride. Other dielectric materials may be used, such as a hafnium oxide or aluminum oxide, or even an aluminum nitride, inter alia. The upper face10ais in this case formed by the conductive portions and by the dielectric material.

The conductive portions are in this case conductive power supply portions11.1intended to provide the supply of electric power to the microelectronic chip20situated on the upper face10a, and at least one conductive control portion11.2,11.3intended to provide the electrical connection between the microelectronic chip20and the conversion chip30. In this example, purely by way of illustration, the upper interconnect layer11comprises:first conductive power supply portions11.1for supplying power to the microelectronic chip20,first upper conductive control portions11.2, connected to the conversion chip30in this case by a through-silicon via18.1and by the portions17.2and32, andsecond upper conductive control portions11.3, connected to the conversion chip30in this case by a through-silicon via18.2and by the portions11.3and34.

The photonic interposer10comprises a lower interconnect layer17, which extends in this case in contact with the electrical redistribution layer16, and defines the lower face10b. It is formed in this case of distinct conductive portions, made of at least one electrically conductive material, for example gold, titanium, copper, etc., separated from one another by a dielectric material, for example an oxide, nitride or silicon oxynitride or the like. The lower face10bis therefore formed by the conductive portions and by the dielectric material.

The conductive portions are in this case conductive power supply portions intended to provide the supply of electric power to the microelectronic chip20situated on the upper face10a, conductive power supply portions intended to provide the supply of electric power to the conversion chip30situated on the lower face10b, at least one conductive control portion and conductive intermediate portions intended to provide the electrical connection between the microelectronic chip20and the optical component via the conversion chip30. In this example, purely by way of illustration, the lower interconnect layer17comprises:first lower conductive power supply portions17.1for supplying power to the microelectronic chip20,second lower conductive power supply portions17.6and second lower conductive intermediate portions17.7for supplying electric power to the conversion chip30,first lower conductive control portions17.2and first lower conductive intermediate portions17.3for the connection between the microelectronic chip20and the optical modulator14.2, via the conversion chip30;second lower conductive control portions17.4and second lower conductive intermediate portions17.5for the connection between the microelectronic chip20and the photodiode14.3, via the conversion chip30.

The photonic interposer10comprises the thick silicon layer12, which in this case extends underneath and in contact with the upper interconnect layer11. This layer originates from an SOI substrate. It contributes to providing the mechanical strength of the optoelectronic device1, in this case with the microelectronic chip20and the encapsulating layer5, as described below. It may have a thickness of preferably less than 200 μm, for example of the order of around one hundred microns, for example equal to around 100 μm. A dielectric layer13.1, made for example of a silicon oxide, provides the electrical insulation between the upper interconnect layer11and the thick silicon layer12.

The photonic interposer10comprises the dielectric layer13.2, which in this case extends underneath and in contact with the thick silicon layer12. It is made in this case of a silicon oxide, and corresponds to the buried oxide layer (BOX) of the SOI substrate. It contributes to forming the sleeve with a low refractive index that surrounds the photonic circuit14.1.

The photonic interposer10comprises the optical layer14, which in this case extends underneath and in contact with the dielectric layer13.2. It is said to be optical in the sense that it comprises the photonic circuit14.1, which is formed by one or more waveguides. The waveguides are in this case made of silicon, from the thin silicon layer of the SOI substrate. As a variant, they may be made of a material with a high refractive index and that is transparent to the wavelength of the optical signal intended to flow in the photonic circuit14.1, such as for example a silicon nitride or the like. The optical layer14is formed by the waveguides, which may have a constant thickness, and for example a dielectric material with a low refractive index, for example a silicon oxide. Moreover, the photonic circuit14.1comprises at least one active optical component such as an optical modulator, an optical filter, or a photodiode. In this example, it comprises an optical modulator14.2and a photodiode14.3.

The photonic interposer10then comprises the lower dielectric layer15, which in this case extends underneath and in contact with the optical layer14. It is made in this case of a dielectric material, for example of a silicon oxide or the like. It contributes to forming the sleeve with a low refractive index that surrounds the photonic circuit14.1.

The photonic interposer10then comprises one or more redistribution layers16(i.e. BEOL routing layers), which in this case extend underneath and in contact with the lower dielectric layer15. It comprises conductive vias and conductive lines in order to at least provide electrical redistribution between power supply portions17.1,17.6,17.7and through-silicon vias19(TSV) in order in this case to provide the supply of electric power (or even also the transmission of electric data) to the microelectronic chip20and the conversion chip30. It should be noted that the interposer may also comprise an upper redistribution layer situated between the interconnect layer11and the dielectric layer13.1. Moreover, such a redistribution layer16may be absent when the photonic interposer10does not contribute to supplying electric power to the microelectronic chips20,30.

In addition, the photonic interposer10comprises at least one TSV called control TSV18, and in this case at least two control TSVs, one 18.1 of which provides the electrical connection between the first upper conductive control portion11.2(intended to be connected to the microelectronic chip20) and the first lower conductive control portion17.2(intended to be connected to the conversion chip30), and the other 18.2 of which provides the electrical connection between the second upper conductive control portion11.3(intended to be connected to the microelectronic chip20) and the second lower conductive control portion17.4(intended to be connected to the conversion chip30). These control TSVs18extend vertically, along the Z-axis, over substantially the entire thickness of the photonic interposer10, and therefore pass through at least the dielectric layer13.1, the thick silicon layer12, the dielectric layer13.2, the optical layer14and the lower dielectric layer15. They may have a height of the order of around 100 μm and a diameter of around 10 μm.

It is apparent from this that the control TSVs18provide a vertical and direct electrical connection between two microelectronic chips20,30situated facing one another on either side of the photonic interposer10, in this case between the microelectronic chip20and the conversion chip30, without involving an intermediate conductive line situated for example in a redistribution layer16. As a result, the first upper and lower control portions11.2and17.2, respectively, are situated perpendicular to one another, just as is the case here for the second upper and lower control portions11.3and17.4, respectively. Therefore, the microelectronic chip20and conversion chip30are at least partially situated vertical (plumb) to one another. This thus reduces the distance between these microelectronic chips20,30, which may be of the order of around one hundred microns, and no longer of the order of several hundred microns or of a millimeter as in the example from the prior art when the microelectronic chips are arranged next to one another in the XY plane.

The photonic interposer10may comprise TSVs called power supply TSVs19, which contribute to providing the electrical connection between the first upper and lower power supply portions11.1and17.1, respectively, for supplying electric power to the microelectronic chip20. These TSVs19extend vertically, along the Z-axis, over at least part of the thickness of the photonic interposer10, and therefore in this case pass through the thick silicon layer12, the dielectric layer13.2, the optical layer14and the lower dielectric layer15. Conductive vias and conductive lines of the redistribution layer16provide the electrical connection of the power supply TSVs19to the lower power supply portions11.1.

Moreover, the photonic interposer10rests on a power supply support2by way of power supply pads6, for example in this case conductive balls made of a ductile material, such as for example tin-based alloys such as SnAg. The first lower power supply portions17.1are in contact with first conductive balls6(for supplying electric power to the microelectronic chip20), and the second lower power supply portions17.6are in contact with second conductive balls6(for supplying electric power to the conversion chip30). The conductive balls6may have a diameter greater than the thickness of the one or more chips30, for example of the order of 300 μm, thus allowing the optoelectronic device1to be transferred onto the power supply support2. The power supply support2may be a printed circuit board PCB. It may also transmit electric data to the chips20and30.

The optoelectronic device1in this case comprises at least one microelectronic chip20, mechanically joined and electrically connected to the photonic interposer10by the upper face10athereof. The microelectronic chip20may in this case be intended to communicate with the optical modulator14.2and the photodiode14.3by way of the conversion chip30. It sends and receives information to and from the conversion chip30; for example, it may send a control signal intended for the optical modulator14.2, and receive a measurement signal coming from the photodiode14.3. The microelectronic chip20in this case comprises a CMOS electronic integrated circuit EIC, and comprises active electronic components such as diodes, transistors, capacitors, resistors, etc. In this case, it comprises an interconnect layer, comprising conductive portions, including conductive power supply portions21, at least one first conductive control portion22(for communicating with the optical modulator14.2) and at least one second conductive control portion23(for communicating with the photodiode14.3).

The one or more first microelectronic chips20may comprise a thermal cooling device4, formed in this case by fins made of a thermally conductive material, which extend from the upper face of the microelectronic chips20. This device makes it possible to effectively cool the microelectronic chips20. It should be noted in this case that the active optical components14.2,14.3are situated close to the lower face10bof the photonic interposer10, and are therefore at a distance from the microelectronic chips20. They are therefore not or only slightly impacted by the heating of the microelectronic chips20, thereby making it possible to maintain their performance.

Moreover, the microelectronic chips20may be kept joined to the photonic interposer10by an encapsulating layer5, for example made of silicone or epoxy resin, which covers the upper face10aof the photonic interposer10, extends between the interconnect pads24, and extends in contact with the microelectronic chips20in the XY plane. The interconnect pads24, like the interconnect pads36, may be arranged periodically with a pitch less than or equal to around 40 μm.

The optoelectronic device1in this case comprises at least one electro-optical conversion chip30, mechanically joined and electrically connected to the photonic interposer10by the lower face10bthereof. The conversion chip30in this case provides the electrical or electronic interface between the microelectronic chip20, on the one hand, and the optical modulator14.2and the photodiode14.3, on the other hand. It exchanges data (electrical signals) with the chip20(for example it processes the information received from the chip20in order to store it temporarily, orient it, reformat it and then transmit it to the optical modulator14.2and/or the photodiode14.3. The same applies for the information received from the optical modulator14.2and/or from the photodiode14.3to be transmitted to the chip20). The conversion chip30in this case comprises a (for example CMOS) electronic integrated circuit, and comprises active electronic components such as diodes, transistors, capacitors, resistors, etc. More specifically, it comprises a CMOS transmitter for driving the optical modulator14.2at a rate of several tens of Gb/s, for example 20 to 50 Gb/s, or even more. It also comprises a CMOS receiver (for example a transimpedance amplifier TIA) for adapting the electrical signal received from the photodiode14.3and transmitting it to the microelectronic chip20. In this case, it comprises an interconnect layer, comprising conductive portions, including conductive power supply portions31, first conductive control and intermediate portions32and33, respectively, for communicating with the microelectronic chip20and the optical modulator14.2, and second conductive control and intermediate portions34and35, respectively, for communicating with the microelectronic chip20and the photodiode14.3.

The photonic circuit14.1comprises an optical input14.1eand an optical output14.1sdesigned to receive and to transmit the optical signal to external waveguides, for example optical fibers3. These may be arranged so as to transmit the optical signal through the slice of the photonic interposer10, or be arranged vertically or inclined with respect to the XY plane. The photonic interposer10may comprise notches for positioning and aligning the optical fibers with respect to the optical input and output, as described in particular in document FR3075991A1.

By way of example, the microelectronic chips20may have a thickness of the order of 100 μm, and the interconnect pads24between the photonic interposer10and the microelectronic chips20may have a thickness of the order of 30 μm. The photonic interposer10may have a thickness of the order of 100 μm between its upper face10aand lower face10b, and the power supply balls6may have a thickness of the order of 250 μm.

During operation, the microelectronic chip20is supplied with electric power by way of the photonic interposer10. The electric supply current flows through the power supply balls6, the lower conductive power supply portions17.1, the conductive lines of the redistribution layer16, the power supply TSVs19, the upper conductive power supply portions11.1, and the conductive power supply portions21for supplying power to the microelectronic chip20.

The conversion chip30is supplied with electric power by way of the photonic interposer10. The electric supply current flows through the power supply balls6, the second lower conductive power supply portions17.6, the conductive lines of the redistribution layer16, the second lower conductive intermediate portions17.7, and the conductive power supply portions31for supplying power to the conversion chip30.

An optical signal is transmitted in the photonic circuit14.1by an external optical fiber, and flows between the input14.1eand the output14.1s. It is modulated by the optical modulator14.2, which is controlled by the microelectronic chip20. For this purpose, the microelectronic chip20emits an electrical signal in the direction of the conversion chip30, which is transmitted by its first conductive control portion22, the first upper conductive control portion11.2, the control TSV18.1, the first lower conductive control portion17.2, and then by the first conductive control portion32of the conversion chip30. The electrical signal is adapted by the microelectronic chip20, and is then transmitted to the optical modulator14.2by the conductive intermediate portions33, the lower conductive intermediate portions17.3, and the conductive vias15.1. The optical signal is then consequently modulated.

In addition, the microelectronic chip20receives an electrical signal representative of the signal detected by the photodiode14.3. For this purpose, the photodiode14.3emits an electrical signal in the direction of the conversion chip30, which flows through the conductive vias15.2, the second lower conductive intermediate portions17.5, and through the conductive intermediate portions35of the conversion chip30. The latter adapts the electrical signal, and then transmits it to the microelectronic chip20, which then flows through the second conductive control portion34, the second lower conductive control portion17.4, the control TSV18.2, the second upper conductive control portion11.3, and through the second conductive control portion23of the microelectronic chip20.

Therefore, due to the fact that the microelectronic chip20and conversion chip30are situated on either side of the photonic interposer10and are connected directly to one another by at least one control TSV18, the distance between these two microelectronic chips20,30is reduced and may be of the order of around one hundred microns. This then makes it possible to reduce communication latency between the microelectronic chips, and to reduce electricity consumption and the thermal budget. In addition, this gives a space saving on the upper face10aof the photonic interposer10, which may be harnessed to connect more microelectronic chips20, such as computing chips and memory chips. Moreover, the bandwidth between the microelectronic chips20,30may be increased due to a reduction in parasitic effects linked to the propagation of high-frequency signals over longer distances. Finally, situating the active optical components close to the lower face10bmakes it possible to limit the negative impact on the performance thereof that may be brought about by the heating of the first microelectronic chips20. In addition, the proximity between the optical components and the chip30is retained in the same way as in conventional architectures. The photonic interposer10may form an ONoC (optical network on chip) network on chip. Multiple photonic interposers may be connected to one another by way of fibers or optical guides.

FIGS.4A to4Lare schematic and partial views illustrating various steps of a method for manufacturing an optoelectronic device1similar to the one illustrated inFIG.2. The photonic interposer10is produced from an SOI substrate, and the optical layer14with the photonic circuit14.1is situated between the thick silicon layer12and the lower face10b.

With reference toFIG.4A, an SOI substrate41is provided. It is formed of a thick silicon layer12, of a dielectric layer13.2(BOX) made of a silicon oxide intended to form the upper dielectric layer, and of a thin silicon layer41.1. The thick silicon layer12may have a thickness of several hundred microns, for example of 725 μm.

With reference toFIG.4B, the optical layer14is then produced, in this case from the thin silicon layer41.1, which contains the photonic circuit14.1. The waveguides are made of silicon, and the active optical components are produced, for example in this case an optical modulator14.2(for example a ring resonator) and a photodiode14.3. A dielectric material with a low refractive index, for example a silicon oxide, surrounds the photonic circuit14.1in the XY plane.

With reference toFIG.4C, a dielectric layer with a low refractive index is produced through deposition on the optical layer14. This dielectric layer forms the lower dielectric layer15. Next, openings43that open out onto the active optical components are also produced, these openings43being intended for the subsequent production of the conductive vias. Blind openings42that are intended to subsequently form the TSVs are also produced through dry etching. These openings42extend through the dielectric layer15, the optical layer14(into the dielectric material), into the dielectric layer13.2, and extend over part of the thickness of the thick layer12. They have a diameter of the order of 10 μm and a height of the order of 100 μm.

With reference toFIG.4D, the control TSVs18and the power supply TSVs19, along with the conductive vias15.1,15.2, are produced by depositing at least one metal material in the various openings. The one or more metal materials may be for example tungsten, copper, aluminum or the like. In practice, the openings43are produced, and then the conductive vias15.1and15.2are produced. Next, the openings42are produced, and then the TSVs18and19are produced.

With reference toFIG.4E, the redistribution layer16is produced, which comprises conductive vias and conductive lines extending into a dielectric material such as a silicon oxide. This is a BEOL (back end of line) layer. The power supply TSVs19are flush with the redistribution layer16without passing through it, while the control TSVs18and the conductive vias of the active optical components pass through it.

The lower interconnect layer17is then produced. This comprises conductive portions that are surrounded in the XY plane by a dielectric material such as a silicon oxide. The conductive portions are in this case the first lower power supply portions17.1(connected to the power supply TSVs19by the conductive lines of the redistribution layer16), the first conductive control portions17.2,17.4(in contact with the control TSVs18), first conductive intermediate portions17.3,17.5(in contact with the conductive vias), and second conductive power supply portions17.6,17.7(connected to one another by the conductive lines of the redistribution layer16).

With reference toFIG.4F, a handle substrate44is joined to the interconnect layer17, in this case through direct bonding, and the structure that is obtained is flipped. The thickness of the thick layer12is then reduced through mechanical abrasion and selective plasma etching, so as to open up the TSVs18,19. The thick layer12may then have a thickness of the order of around one hundred microns.

With reference toFIG.4G, the interconnect layer11is produced, which comprises conductive portions in contact with the TSVs18,19that are insulated from the thick layer12by a dielectric layer13.1, and surrounded in the XY plane by a dielectric material. The conductive portions are in this case conductive power supply portions11.1(in contact with the power supply TSVs19) and conductive control portions11.2,11.3(in contact with the control TSVs18).

With reference toFIG.4H, interconnect pads24, also called copper pillars, are produced (physical vapor deposition (PVD) of a sublayer of Ti/Cu, lithography to define the size of the pads (diameter of the order of 10 to 500 μm and with a minimum pitch between the pads of 20 μm), electrolysis of Cu/Ni/SnAg and removal of the resin (stripping), etching of the Ti/Cu sublayer around the pads, and then thermal annealing) or UBM (for under bumping metallization) formed of a Cu/Ni/Au stack, in contact with the conductive portions of the interconnect layer11. The microelectronic chip20is then placed on and joined to the interposer10through collective soldering. It will be noted that joining the handle substrate44through direct bonding makes it possible to withstand a soldering joining temperature between the microelectronic chip20and the interconnect pads24that may be of the order of 260° C.

An encapsulating layer5(or molding) is then deposited, such that it extends over the upper face10aand surrounds the microelectronic chip20and the interconnect pads24in the XY plane, thus bolstering the mechanical strength of the microelectronic chip20on the photonic interposer10. The encapsulating layer5may be made of an epoxy resin or the like.

With reference toFIG.4I, another handle substrate45is joined to the free planar face formed by the microelectronic chip20and the encapsulating layer5, in this case by way of a polymer adhesive46. The structure thus obtained is flipped, and the handle substrate44is removed through abrasion. The face of the interconnect layer17is freed up, and the interconnect pads36are produced in contact with the various conductive portions called UBM and formed of the Cu/Ni/Au stack.

With reference toFIG.4J, the handle substrate45and the adhesive layer46are removed. The structure thus obtained may be manipulated despite the reduced thickness of the photonic interposer10, in this case by virtue of the thickness and the mechanical strength of the stack formed of the photonic interposer10, the microelectronic chip20and the encapsulating layer5.

With reference toFIG.4K, the conversion chip30and the power supply balls6are joined to the various interconnect pads through ball placement or screen printing.

With reference toFIG.4L, the structure thus obtained is flipped, and is then joined to a power supply support2by way of the power supply balls6. A cooling device may be fastened to the microelectronic chip20.

This thus gives an optoelectronic device1formed of an active photonic interposer10to which at least one microelectronic chip20and at least one conversion chip30are joined and connected. The microelectronic chip20and the conversion chip30are directly connected to one another by control TSVs, thus reducing the distance between them, thereby improving the performance of the optoelectronic device1(reduced latency time, reduced electricity consumption, increased bandwidth, etc.). In addition, the microelectronic chip20is situated on the upper face10aof the photonic interposer10, and the photonic circuit14.1is situated close to the lower face10b. This thus limits the drop in performance of the active optical components that may be brought about by the heating of the microelectronic chip20. Moreover, the number of microelectronic chips (computing, memory, etc.) situated on the upper face10amay be increased.

Particular embodiments have just been described. Various modifications and variants will be obvious to anyone skilled in the art. As indicated above, the photonic interposer10may comprise one or more redistribution layers16between the upper interconnect layer11and the thick silicon layer12. It might also not comprise any redistribution layers if the chips are supplied with power through a wired connection (wire bonding).