Device and method for computing a channel estimate

An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

The present disclosure is generally related to electronic devices and techniques for operating electronic devices.

II. DESCRIPTION OF RELATED ART

Advances in technology have resulted in smaller and more powerful electronic devices. For example, there currently exist a variety of mobile devices, such as wireless telephones, personal digital assistants (PDAs), and paging devices. The mobile devices may be small, lightweight, and easily carried by users. Wireless telephones, such as cellular telephones and Internet Protocol (IP) telephones, can communicate voice and data packets over wireless networks. Further, many wireless telephones include other types of devices that are incorporated therein. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, wireless telephones can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, wireless telephones and other mobile devices can include significant computing capabilities.

Increasingly, users expect mobile devices to provide high (e.g. “fast”) performance while also consuming low power (e.g., having long battery life). However, to enable such processing capabilities, the mobile devices may store and process a large number of instructions, which consumes power. Battery life may be conserved by reducing the number of the instructions or reducing the speed at which the instructions are processed. However, conserving battery life in this manner may slow performance of the mobile devices, frustrating users. Some mobile devices use scalar hardware to perform certain operations. Scalar hardware may not feature sufficient performance for some applications (e.g., to rapidly estimate a channel impulse response to recover a transmitted signal by a mobile device within a communication system). Vector hardware may be computationally robust, but may be complex to implement.

Communication systems may use a code division multiple access (CDMA) technique to enable a network device to communicate with multiple mobile devices over a wireless channel. For example, a receiver in a CDMA communication system may correlate a data sequence of a received signal to a CDMA code (e.g., a CDMA “chip” sequence) to estimate a channel impulse response (e.g., to compute a channel estimate) associated with a wireless channel. The channel estimate may be used to recover data transmitted by a mobile device over the wireless channel, such as by using the channel estimate to compensate for effects (e.g., fading) of the wireless channel on the received signal.

Correlating the data sequence with respect to a code sequence (e.g., the CDMA “chip” sequence) to determine the channel estimate may be computationally intensive and may occur often, thus consuming processing resources of devices of a CDMA communication system. For example, a device may calculate a channel estimate h(n) according to the following equations:

In the foregoing equations, r indicates a data sample vector, c indicates a code sequence vector, c* indicates a complex conjugate of the code sequence vector, [r].[c] indicates a dot product between r and c, and n indicates a time lag, as described further below.

A device in accordance with the present disclosure “splices” data samples of a data sequence and “shifts” (e.g., rotates) code samples of a code sequence instead of shifting the data samples. Shifting the code samples instead of the data samples may avoid certain complex computations and may enable channel estimation using simplified vector hardware. For example, shifting the code samples may be simpler than shifting the data samples when each data sample includes a sixteen-bit vector and each code sample includes a two-bit vector, as explained further below.

In a particular embodiment, an apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

In another particular embodiment, a method of computing a channel estimate includes storing a first set of samples in a first set of registers and storing a second set of samples in a second set of registers. The method further includes selecting a first subset of the first set of samples. The first subset is selected according to an offset value and includes a first sample of the first set of samples and a second sample of the first set of samples. The first sample is stored at a first register of the first set of registers and the second sample is stored at a second register of the first set of registers. The method further includes correlating the first subset of the first set of samples with the second set of samples to generate a first value associated with the channel estimate. In response to generating the first value, the second set of samples is shifted according to a step value to generate a shifted second set of samples.

In another particular embodiment, an apparatus includes means for selecting a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes means for shifting a second set of samples stored at a second set of registers to generate a shifted second set of samples. The apparatus further includes means for generating a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

In another particular embodiment, a computer-readable storage medium stores instructions that are executable by a processor to cause a radio frequency (RF) interface to perform operations that include storing a first set of samples in a first set of registers and storing a second set of samples in a second set of registers. The operations further include selecting a first subset of the first set of samples. The first subset is selected according to an offset value and includes a first sample of the first set of samples and a second sample of the first set of samples. The first sample is stored at a first register of the first set of registers and the second sample is stored at a second register of the first set of registers. The operations further include correlating the first subset of the first set of samples with the second set of samples to generate a first value associated with the channel estimate. The operations further include, in response to generating the first value, shifting the second set of samples according to a step value to generate a shifted second set of samples.

One particular advantage provided by at least one of the disclosed embodiments is computation of a channel estimate by shifting code samples (e.g., instead of shifting data samples). Shifting the code samples instead of the data samples may avoid certain complex computations and may enable channel estimation using simplified vector hardware. Because each data sample may include a sixteen-bit vector and each code sample may include a two-bit vector, shifting the code samples instead of shifting the data samples may enable simplified hardware design and lower power consumption as compared to devices that shift data samples. Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.

V. DETAILED DESCRIPTION

Referring toFIG. 1, a particular illustrative embodiment of a device at a first particular time of operation is depicted and generally designated100. In a particular embodiment, the device100corresponds to a portion of a radio frequency (RF) interface, such as a modem. The device100may correspond to a vector machine that performs operations on vectors to determine channel estimates used to receive signals transmitted over a channel, as described further below.

The device100includes a first set of registers to store a first set of samples (e.g., data registers104to store a set of data samples) and a second set of registers to store a second set of samples (e.g., code registers108to store a set of code samples, such as a CDMA code sequence). The device100further includes selection logic112, a channel estimator116, and shift logic124. The selection logic112is responsive to the data registers104and to the code registers108. The channel estimator116is responsive to the selection logic112. The code registers108may be responsive to the shift logic124to shift (e.g., shift horizontally, or “rotate”) the set of code samples stored at the code registers108, as described further below.

In the particular example ofFIG. 1, the set of data samples stored in the data registers104includes data samples r0, r1, . . . r191. The set of code samples stored in the code registers108includes code samples c0, c1, . . . c63, as illustrated inFIG. 1. The example ofFIG. 1further depicts that the data registers104include a first data register128, a second data register132, and a third data register136. The data registers104further include destination registers138, which may store results of computations performed by the channel estimator116, such as partial correlations, as described further below.

In operation, the channel estimator116may generate a channel estimate based on data samples and code samples selected by the selection logic112. The channel estimate may correspond to h(n) described above. The channel estimate may include partial channel estimates, such as h(0), h(1), . . . h(31), which may each correspond to the channel estimate at a respective time. For example, h(0) may correspond to the channel estimate at a first time (i.e., n=0), h(1) may correspond to the channel estimate at a second time (i.e., n=1), and h(31) may correspond to the channel estimate at a thirty-second time (i.e., n=31).

In a particular embodiment, the channel estimate at each time is determined as a combination (e.g., a sum) of partial correlations between subsets of the set of data samples at the data registers104and the set of code samples at the code registers108. A particular illustration is provided below in which a channel estimate h(0) is determined as a combination of values, such as partial correlations h0(0) and h1(0) (also referred to herein as partial products and partial channel estimates).

To determine h0(0), the selection logic112may select a first subset of the data samples and the code samples (or a second subset of the code samples). The selection logic112may provide the code samples and the first subset of the data samples to the channel estimator116. The channel estimator116may generate a first value120(e.g., h0(0)) based on the code samples and the first subset (e.g., by computing a dot product between the code samples and the first subset). For example, the channel estimator116may perform a partial correlation based on the code samples and the first subset to calculate:
h0(0)=r0*c0+r1*c1+r2*c2+r3*c3+r64*c64+r65*c65+r66*c66+r67*c67.

The first value120may be stored at the destination registers138. Further, a second value, such as a second partial correlation h1(0), may be determined according to:
h1(0)=r64*c63+r1*c0+r2*c1+r3*c2+r128*c127+r65*c64+r66*c65+r67*c66.

To determine h1(0), some devices may shift each of the data samples. For example, a device may shift each of the data samples left one position (i.e., so that the leftmost data sample in the first data register128is r1 instead of r0, and so on) and then read out the data samples beginning at the first shifted data sample (i.e., beginning at r1). However, such devices may require complex hardware to shift each of the data samples, which can be particularly difficult to implement when each of the data samples includes a large vector. In a particular embodiment, the device100shifts the code samples stored at the code registers108rather than shifting the data samples stored at the data registers104.

For example,FIG. 2depicts the device100ofFIG. 1at a second particular time of operation. In the example ofFIG. 2, the code samples of the code registers108are shifted instead of the data samples. Thus,FIG. 2depicts that the shift logic124has left-shifted the set of code samples according to a step value148. InFIG. 2, the step value148is equal to one. Thus, each of the set of code samples is right-shifted one position, so that the leftmost sample is c63 and the rightmost sample is c62. Accordingly, the channel estimator116may determine h1(0) based in part on the shifted set of code samples (e.g., c63, c0, c1, . . . c62). Further, inFIG. 2, the selection logic112selects a second subset of the set of the data values (e.g., a predetermined number of consecutive samples) based on an offset value140. In the example ofFIG. 2, the offset value140is equal to one (i.e., one data sample, r0, has been “skipped” to select the second subset). Depending on the particular application, the offset value140may be a different value.

Continuing with the above example, the channel estimator116may compute a second value (e.g., h1(0)) based on the shifted code samples (or a subset of the shifted code samples) and further based on the second subset such that:
h1(0)=r64*c63+r1*c0+r2*c1+r3*c2+r128*c127+r65*c64+r66*c65+r67*c66.

The second value may be stored at the destination registers138. By shifting code samples of the code registers108instead of data samples of the data registers104, large shifting operations of the data samples may be avoided. For example, when each of the data samples includes a sixteen-bit data vector and each of the code samples includes a two-bit code vector, shifting the code samples may avoid large shifting operations associated with shifting the large data samples. In a particular embodiment, the code registers108store a CDMA “chip sequence” of two-bit vectors, where each of the two-bit vectors indicates a respective value of 1, −1, sqrt(−1), or −sqrt(−1). Alternatively, each of the two-bit vectors may respectively indicate 1+sqrt(−1), 1−sqrt(−1), −1+sqrt(−1), or −1−sqrt(−1), or another combination of values.

Further, because the selection logic112can select data samples in multiple consecutive registers, data samples may be selected without shifting or moving the data samples (e.g., into a single register), thus simplifying operation. For example, non-contiguous data samples may be selected (e.g., R1 and R64) without moving the data samples (e.g., without adding R64 to the contents of the first data register128and then selecting the entire contents of the first data register128). By selecting non-contiguous data samples, certain conventional circuitry, such as a “tapped delay line,” may be avoided (e.g., a large circuit to shift or overwrite data values at the data registers104may be avoided).

Additional partial correlations (e.g., h2(0), h3(0), . . . h15(0)) may be generated in a similar fashion. The channel estimator116may combine the partial correlations (e.g., h0(0), h1(0)) . . . h15(0)) to determine a channel estimate220at a first time (e.g., to determine h(0), as described above). Similarly, the channel estimator116may combine additional partial channel estimates (e.g., h0(1), h1(1), . . . h5(1)) to determine the channel estimate220at a second time (i.e., h(1)). The channel estimate220at the first time may indicate a first response of a channel at the first time, and the channel estimate220at the second time may indicate a second response of the channel at the second time (e.g., a time “lag” from the first time to the second time).

The offset value140and the step value148are used by the selection logic112to select contents of particular registers of the data registers104. The offset value140and the step value148may indicate register locations corresponding to the particular time for which the channel estimate220is to be estimated. For example, at the time n=0, the offset value140and the step value148may each have a value of zero indicating a 0thregister location the data registers104and the code registers108, respectively. At the time n=1, the offset value140and the step value148may each have a value of one indicating a 1stregister location the data registers104and the code registers108, respectively. Further, the offset value140and the step value148may correspond to a number of bits of the data samples and a number of bits of the code samples. In the particular example ofFIG. 2, the time lag is equal to one (i.e., from the first time to the second time), the offset value140is equal to sixteen bits (i.e., r0 to r1 spans sixteen bits), and the step value148is equal to two bits (i.e., from c63 to c0 spans two bits).

In connection withFIG. 2, the second subset includes data samples beginning at a register corresponding to the offset value140in the first data register128(i.e., at r1) and “wrapping around” through the offset value140minus one in the third data register136(i.e., to r128). Thus, the second subset is selected by choosing data samples beginning at the offset value140(e.g., an nthcolumn or “lane”) through the end sample of the first data register128(e.g., the “maximum” of the register, which corresponds to r63 inFIG. 2) and “wrapping around” from the beginning sample of the third data register136(i.e., r128) to the offset value140minus one (i.e., an n−1 column or “lane,” which corresponds to one minus one, or zero, in the particular example ofFIG. 2). Thus, a predetermined number of consecutive data samples are read from the data registers104beginning at the offset value140in one of the data registers (i.e., the first data register128) and ending at the offset value140minus one in another of the data registers104(i.e., the third data register136). Thus, the selection logic112may select the second subset by “splicing” data samples from multiple consecutive registers of the data registers104based on the offset value140.

In a particular illustrative embodiment, the channel estimator116includes a processor configured to determine the channel estimate220for different time lags in parallel. For example, the channel estimate220at the first time (i.e., h(0)) (or a portion thereof) may be determined in parallel with the channel estimate220at the second time (i.e., h(1)) (or a portion thereof) by executing a single instruction at the processor. To further illustrate, the processor may execute the single instruction to determine partial correlations in parallel (e.g., to determine h0(1) in parallel with h1(1)).

In at least one alternative embodiment, the second set of samples may include a second set of data samples instead of code samples. For example, the second set of data samples may be used in applications where the channel estimator116performs covariance calculations (e.g., instead of correlation calculations) to generate the channel estimate220. Accordingly, the destination registers138may be configured to temporarily store partial correlations (e.g., h0(0), h1(0), . . . h15(0)), results of covariance calculations, or a combination thereof. In a particular embodiment, each column (e.g., “lane”) of the first set of registers has a corresponding destination register to store a partial correlation. Continuing with the example ofFIG. 2, a first destination register may correspond to the first lane of the first set of registers (i.e., the lane storing r0, r64, and r128) and may store the first partial correlation h0(0). As another example, a second destination register may correspond to the second lane of the first set of registers (i.e., the lane storing r1, r65, and r129) and may store the second partial correlation h1(0). The destination registers may temporarily store the partial correlations h0(0), h1(0), . . . h15(0) until the partial correlations h0(0), h1(0), . . . h15(0) are combined to generate h(0), at which time partial correlations corresponding to h(1) are written to the destination registers (i.e., h0(1), h1(1), . . . h15(1)).

The data registers104and the code registers108may be of appropriate sizes for a particular application. For example, the registers104,108may be configured to store 128 samples. In a particular embodiment, the code registers108include two registers each configured to store 64 samples (e.g., a fourth register configured to store c0 . . . c63, as shown inFIGS. 1 and 2, and a fifth register (not shown) that is configured to store c64 . . . c127). The shift logic124may be further configured to shift the code samples by shifting samples of both the fourth register and the fifth register (e.g., to left-shift c63 relative to c0, as depicted inFIGS. 1 and 2, and further to left-shift c127 relative to c64). Alternatively, the registers104,108may be configured to store 256 samples, or another number of samples. If the registers104,108store 256 samples, operations can be “broken” up into two sets of 128 operations.

Referring toFIG. 3A, a particular illustrative embodiment of a method performed by the device100is depicted and generally designated300. Operations of the method300may be performed by the channel estimator116.

The method300includes storing a first set of samples (e.g., data samples associated with a received signal) in a first set of registers, at304. The first set of samples may correspond to the data samples described with reference toFIGS. 1 and 2(i.e., r0, r1, . . . r191). The first set of registers may correspond to the data registers104described with reference toFIGS. 1 and 2.

At308, the method300further includes storing a second set of samples (e.g., code samples associated with a code sequence, such as a CDMA “chip” sequence that includes unity values, such as 1 and −1 or sqrt(−1) and −sqrt(−1)) in a second set of registers. The second set of samples may correspond to the code samples described with reference toFIGS. 1 and 2(i.e., c0, c1, . . . c63). The second set of registers may correspond to the code registers108described with reference toFIGS. 1 and 2.

At312, the method300further includes selecting a first subset of the first set of samples. The first subset may correspond to r0, r1, r2, r3, r64, r65, r66, r67, as described with reference toFIG. 1. The first subset may be selected by the selection logic112without shifting the first set of samples. The first subset is selected according to an offset value and includes a first sample of the first set of samples and a second sample of the first set of samples. The first sample is stored at a first register of the first set of registers, and the second sample stored at a second register of the first set of registers. For example, the first sample may be stored at one of the data registers128,132,136and the second sample may be stored at another of the data registers128,132,136. The offset value may correspond to the offset value140ofFIG. 2.

At316, the method300further includes correlating (e.g., using a dot product operation) the first subset of the first set of samples with the second set of samples (or a second subset of the second set of samples) to generate a first value associated with a channel estimate. Correlating the first subset with the second set of samples may be performed by the channel estimator116. The first value may correspond to the first value120(e.g., h0(0)) described with reference toFIG. 1. The channel estimate may correspond to the channel estimate220ofFIG. 2. The first value may be stored at the destination registers138.

At320, in response to generating the first value, the method300further includes shifting the second set of samples according to a step value to generate a shifted second set of samples. The step value may correspond to the step value148ofFIG. 2. The second set of samples may be shifted by the shift logic124ofFIGS. 1 and 2.

At324, a second value is generated based on a second subset of the first set of samples and further based on the shifted second set of samples. For example, the second value may correspond to h1(0) and may be generated as described with reference toFIG. 2.

Referring toFIG. 3B, a particular illustrative embodiment of another method performed by the device100is depicted and generally designated350. Operations of the method350may be performed by the channel estimator116and may be performed in response to performing the method300ofFIG. 3A.

The method350includes selecting a second subset of the first set of samples, at328. The second subset may correspond to r1, r2, r3, r64, r65, r66, r67, r128, as described with reference toFIG. 2. The second subset may be selected by the selection logic112without shifting the first set of samples.

At332, the second subset is correlated (e.g., using a dot product operation) with the shifted second set of samples (or a second subset of the shifted second set of samples) to generate a second value associated with the channel estimate. The second value may correspond to h1(0), as described above, and may be stored at the destination registers138. The first value and the second value may correspond to partial correlations associated with the channel estimate for a first time n=0.

At336, in response to generating the second value, the shifted second set of samples is re-shifted according to the step value. For example, the shifted second set of samples may be re-shifted to generate a sequence c62, c63, c0, c1, c2, . . . c61 at the code registers108. The method350may include generating additional partial channel estimates for the first time n=0, such as h2(0), h3(0), . . . h15(0) (not shown inFIG. 3B).

At340, the method350further includes combining at least the first partial correlation and the second partial correlation to generate the channel estimate at the first time. For example, h0(0), h1(0), . . . h15(0) may be combined (e.g., added) to generate the channel estimate at the first time n=0 (i.e., to generate h(0)).

At344, a third partial correlation and a fourth partial correlation are generated. The third partial correlation and the fourth partial correlation may correspond to h0(1) and h1(1), respectively, which may correspond to a second time n=1. Additional partial correlations may be generated for the second time n=1, such as h2(1), h3(1), . . . h15(1). The method350further includes combining at least the third partial correlation and the fourth partial correlation (e.g., by adding h0(1), h1(1), h2(1), . . . h15(1)) to generate the channel estimate at the second time n=1 (i.e., to generate h(1)), at348. The second time n=1 is a “time lag” after the first time n=0 and the offset value and the step value are based on the time lag (i.e., the offset value and the step value are selected based on the time lag).

Computation of channel estimates using the methods300,350ofFIGS. 3A and 3Bmay reduce complexity of computations and may enable simplified vector hardware. For example, shifting code samples instead of shifting data samples may avoid certain complex computations when each data sample includes a sixteen-bit vector and each code sample includes a two-bit vector. Thus, shifting code samples instead of shifting data samples may enable simplified hardware design and lower power consumption as compared to devices that shift data samples.

Referring toFIG. 4, a block diagram of a particular illustrative embodiment of a communication device is depicted and generally designated400. The communication device400may include a processor410, such as a digital signal processor (DSP). The processor410may be coupled to a computer-readable storage medium, such as a memory432(e.g., a non-transitory computer-readable medium). The memory432may store instructions454executable by the processor410, data456accessible to the processor410, or a combination thereof.

FIG. 4also shows a display controller426that is coupled to the processor410and to a display428. A coder/decoder (CODEC)434can also be coupled to the processor410. A speaker436and a microphone438can be coupled to the CODEC434. A camera446may be coupled to a camera controller490. The camera controller490may be coupled to the processor410.

FIG. 4also indicates that a wireless controller440can be coupled to the processor410. The wireless controller may be further coupled to an antenna442via a radio frequency (RF) interface450. The RF interface450may include the device100ofFIGS. 1 and 2. In a particular embodiment, the device100corresponds to a modem (or a portion of a modem) included in the RF interface450. The wireless controller440, the RF interface450, and the antenna442may be used to receive signals, such as signals transmitted via a CDMA network. In a particular embodiment, the data registers104store data samples associated with the received signals and the code registers108store a code sequence associated with the CDMA network (e.g., a CDMA “chip” sequence).

In a particular embodiment, the processor410, the memory432, the display controller426, the camera controller490, the CODEC434, the wireless controller440, and the RF interface450are included in the system-in-package or system-on-chip device422. An input device430and a power supply444may be coupled to the system-on-chip device422.

Moreover, in a particular embodiment, and as illustrated inFIG. 4, the display428, the input device430, the camera446, the speaker436, the microphone438, the antenna442, and the power supply444are external to the system-on-chip device422. However, each of the display428, the input device430, the camera446, the speaker436, the microphone438, the antenna442, and the power supply444can be coupled to a component of the system-on-chip device, such as to an interface or to a controller.

In connection with the described embodiments, a computer-readable storage medium (e.g., the memory432) stores instructions (e.g., the instructions454) that are executable by a processor (e.g., the processor410) to cause a radio frequency (RF) interface (e.g., the RF interface450) to perform operations, such as one or more operations corresponding to the methods300,350ofFIGS. 3A and 3B. In a particular embodiment, the operations include storing a first set of samples (e.g., r0, r1, . . . r191, which may correspond to a signal received via the antenna442and the RF interface450) in a first set of registers (e.g., the data registers104). The operations further include storing a second set of samples (e.g., c0, c1, . . . c63, which may correspond to a code sequence, such as a CDMA code sequence) in a second set of registers (e.g., the code registers108). The operations further include selecting a first subset (e.g., the first subset described with reference toFIG. 2) of the first set of samples. The first subset is selected according to an offset value (e.g., the offset value140) and includes a first sample of the first set of samples and a second sample of the first set of samples. The first sample is stored at a first register of the first set of registers (e.g., one of the data registers128,132,136), and the second sample is stored at a second register of the first set of registers (e.g., another of the data registers128,132,136). The operations further include correlating the first subset of the first set of samples with the second set of samples to generate a first value (e.g., a partial correlation, such as h0(0)) associated with the channel estimate. The operations further include, in response to generating the first value, shifting the second set of samples according to a step value to generate a shifted second set of samples (e.g., to generate c63, c0, . . . c62 as depicted inFIG. 2).

In connection with the described embodiments, an apparatus (e.g., the system-on-chip device422) includes means for selecting (e.g., the selection logic112) a first subset of a first set of samples (e.g., r0, r1, . . . r191) stored at a first set of registers (e.g., the data registers104). The first subset includes a first sample stored at a first register (e.g., one of the data registers128,132,136) of the first set of registers and further includes a second sample stored at a second register (e.g., another of the data registers128,132,136) of the first set of registers. The apparatus further includes means for shifting (e.g., the shift logic124) a second set of samples (e.g., c0, c1, . . . c63) stored at a second set of registers (e.g., the code registers108) to generate a shifted second set of samples (e.g., c63, c0, c1 . . . c62). The apparatus further includes means for generating a first value (e.g., a partial correlation, such as h0(0)) associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.

Those of skill in the art will appreciate that the foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g. RTL, GDSII, GERBER, etc.) stored on computer-readable media. Some or all such files may be provided to fabrication handlers who fabricate devices based on such files. Resulting products include semiconductor wafers that are separated into semiconductor dies and packaged into semiconductor chips. The semiconductor chips are then employed in devices, such as the device100, the communication device400, or a combination thereof.