IMAGE SENSOR FOR REDUCING NOISE

An image sensor includes a pixel array connected to a plurality of column lines, a first ramp signal generator generating a first ramp signal, a second ramp signal generator generating a second ramp signal, and an analog-to-digital conversion (ADC) circuit operating in a first mode. The ADC circuit includes a first comparator group comparing the first ramp signal with a first pixel signal received from a first column line group, among the plurality of column lines, and a second comparator group comparing the second ramp signal with a second pixel signal received from a second column line group, among the plurality of column lines. The comparing of the first ramp signal occurs at a comparison time point different from a comparison time point during which the comparing of the second ramp signal occurs.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. patent application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0143955, filed on Nov. 1, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.

1. TECHNICAL FIELD

The inventive concept relates to an image sensor, and more particularly, to an image sensor for reducing noise.

2. DISCUSSION OF RELATED ART

Image sensors are capable of capturing a two-dimensional (2D) or a three-dimensional (3D) image of an object. The image sensors may generate an image of the object using a photoelectric transformation element that reacts according to an intensity of light reflected from the object. With the recent development of complementary metal-oxide semiconductor (CMOS) technology, CMOS image sensors using CMOS have been widely used.

Each of the image sensors may include a pixel array having a plurality of pixels, where each of the pixels includes the photoelectric transformation element. However, noise may be introduced when the image sensors read one row line of the pixel array at the same time to cause performance and image performance to deteriorate. Thus, there is a need for an image sensor capable of operating with reduced noise.

SUMMARY

At least one embodiment of the inventive concept provides an image sensor capable of reducing noise by varying time points at which pixel signals are compared for the same row line using a plurality of ramp signal generators.

According to an aspect of the inventive concept, there is provided an image sensor including a pixel array, a first ramp signal generator, a second ramp signal generator, and an analog-to-digital conversion (ADC) circuit. The pixel array is connected to a plurality of column lines. The first ramp signal generator is for generating a first ramp signal. The second ramp signal generator is for generating a second ramp signal. The analog-to-digital conversion (ADC) circuit operates in a first mode. The ADC circuit includes a first comparator group and a second comparator group. The first comparator group is for comparing the first ramp signal with a first pixel signal received from a first column line group, among the plurality of column lines. The second comparator group is for comparing the second ramp signal with a second pixel signal received from a second column line group, among the plurality of column lines. The comparing of the first ramp signal occurs at a comparison time point different from a comparison time point during which the comparing of the second ramp signal occurs.

According to another aspect of the inventive concept, there is provided an image sensor including a pixel array, a first ramp signal generator, a second ramp signal generator, an analog-to-digital conversion (ADC) circuit, and a timing controller. The pixel array includes a plurality of pixels. The pixel array is connected to a plurality of column lines outputting a plurality of pixel signals generated by the plurality of pixels. The first ramp signal generator is for generating a first ramp signal. The second ramp signal generator is for generating a second ramp signal. The analog-to-digital conversion (ADC) circuit analog-to-digital is for converting the plurality of pixel signals and operates in a first mode. The timing controller controls timings of the first ramp signal generator and the second ramp signal generator. The ADC circuit includes a first correlated double sampling (CDS) circuit and a second CDS circuit. The first CDS circuit is for reading the plurality of pixel signals based on the first ramp signal. The second CDS circuit is for reading the plurality of pixel signals based on the second ramp signal in the first mode. The plurality of pixel signals include a plurality of first pixel signals and a plurality of second pixel signals. The plurality of column lines include a plurality of first column lines and a plurality of second column lines. The first CDS circuit reads the plurality of pixel signals at a timing different from a timing at which the second CDS circuit reads the plurality of pixel signals.

According to another aspect of the inventive concept, there is provided an image sensor including a first ramp signal generator, a second ramp signal generator, a pixel array, and an analog-to-digital conversion (ADC) circuit. The first ramp signal generator is for generating a first ramp signal. The second ramp signal generator is for generating a second ramp signal. The pixel array includes first color pixels connected to a first column line and a second column line and second color pixels connected to a third column line and a fourth column line. The ADC circuit includes a first comparator and a second comparator. The first comparator is for comparing a first pixel signal received from the first column line and the third column line with the first ramp signal. The second comparator is for comparing a second pixel signal received from the second column line and the fourth column line with the second ramp signal. The comparing of the first pixel signal occurs at a comparison time point different from a comparison time point during which the comparing of the second pixel signal occurs.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1is a block diagram illustrating a configuration of an image sensor100according to an embodiment.

The image sensor100may be mounted in an electronic device having an image or light sensing function. For example, the image sensor100may be mounted in electronic devices, such as cameras, smartphones, wearable devices, the Internet of things (IoT), tablet personal computers (PCs), personal digital assistants (PDAs), portable multimedia players (PMPs), and navigation devices. In addition, the image sensor100may be mounted on electronic devices provided as parts, such as vehicles, furniture, manufacturing facilities, doors, and various measurement devices.

The image sensor100may include a pixel array110, a row driver120(e.g., a driver circuit), a ramp signal generator (or a ramp generator)130, an analog-to-digital conversion (ADC) circuit140(e.g., an analog-to-digital converter), a data output circuit150, and a timing controller160(e.g., a control circuit). The image sensor100may further include a signal processor170.

The pixel array110includes a plurality of pixels PX connected to a plurality of row lines RL and a plurality of column lines CL and arranged in rows and columns.

Each of the pixels PX may include at least one photoelectric transformation element, and the pixel PX may sense light using the photoelectric transformation element and output an image signal that is an electrical signal according to the detected light. For example, the photoelectric transformation element may include a photodiode, a phototransistor, a photogate, or a pinned photodiode. For example, the sensed light may be received from an object or reflected from the object.

Each of the pixels PX may sense light in a certain spectral range. For example, the pixels PX may include a red pixel converting light in a red spectral range into an electrical signal, a green pixel converting light in a green spectral range into an electrical signal, and a blue pixel converting light in a blue spectral range into an electrical signal. However, the inventive concept is not limited thereto. For example, the pixels PX may further include white pixels. As another example, the pixels PX may include pixels combined in different color configurations, for example, yellow pixels, cyan pixels, and green pixels.

A color filter array allowing light in a certain spectral range to be transmitted therethrough may be disposed above the pixels PX, and colors that the corresponding pixels may detect may be determined according to the color filters disposed above the pixels, respectively. However, the inventive concept is not limited thereto. In an embodiment, a certain photoelectric transformation element may transform light of a certain wavelength band to an electrical signal according to a level of an electric signal applied thereto.

The row driver120drives the pixel array110in units of rows. The row driver120may decode a row control signal (e.g., an address signal) received from the timing controller160and select at least one of the row lines constituting the pixel array110in response to the decoded row control signal. For example, the row driver120may generate a selection signal for selecting one of the row lines that corresponds to the address signal. Also, the pixel array110outputs a pixel signal, for example, a pixel voltage, from the row line selected by the selection signal provided from the row driver120. The pixel signal may include a reset signal and an image signal.

The row driver120may transmit control signals for outputting pixel signals to the pixel array110, and the pixels PX may operate in response to the control signals to output pixel signals.

In an embodiment, the ramp signal generator130generates a ramp signal RAMP having a level rising or falling with a certain slope under the control of the timing controller160. The ramp signal generator130may include a first ramp signal generator130athat generates a first ramp signal (e.g., RAMP1inFIG.2) and a second ramp signal generator130bthat generates a second ramp signal (e.g., RAMP2inFIG.2). The first ramp signal RAMP1and the second ramp signal RAMP2may be respectively provided to a plurality of comparators141(e.g., comparator circuits) provided in the ADC circuit140. In an embodiment, a slope of the first ramp signal RAMP1is the same as a slope of the second ramp signal RAMP2. Hereinafter, description is given mainly with reference to the fact that the slope of the first ramp signal RAMP1is the same as the slope of the second ramp signal RAMP2, but embodiments are not limited thereto. For example, when the image sensor100operates in a certain mode, the ramp signal generator130may generate the first ramp signal RAMP1and the second ramp signal RAMP2such that the slopes of the first ramp signal RAMP1and the second ramp signal RAMP2are different from each other.

The ADC circuit140may include a plurality of comparators141and a plurality of counter (CNTR) circuits142. The ADC circuit140may convert a pixel signal (e.g., a pixel voltage) input from the pixel array110into a pixel value that is a digital signal. The pixel signals respectively received through the column lines CL are converted into pixel values that are digital signals by the comparators141and the counter circuits142.

The comparators141may compare the pixel signals received through the column lines CL, for example, pixel voltages, with the first ramp signal RAMP1or the second ramp signal RAMP2to generate a comparison result as a comparison result signal for output. In an embodiment, when the level of the first ramp signal RAMP1or the second ramp signal RAMP2is equal to the level of the pixel signal, the comparators141output a comparison signal transitioning from a first level (e.g., logic high) to a second level (e.g., logic low) different from the first level. A time point at which the level of the comparison signal transitions may be determined according to the level of the pixel signal. In an embodiment, a time point at which the level of the comparison signal transitions when comparing the pixel voltage with the first ramp signal RAMP1may be different from a time point at which the level of the comparison signal transitions when comparing the pixel voltage with the second ramp signal RAMP2. Some embodiments are described below with reference toFIGS.5to7.

The comparators141may be a plurality of correlated double sampling (CDS) circuits. A CDS circuit may sample a pixel signal provided from the pixel PX according to a CDS method. The CDS circuit may sample a reset signal received as a pixel signal and compare the reset signal with the first ramp signal RAMP1or the second ramp signal RAMP2to generate a comparison signal in accordance with the reset signal. The CDS circuit may store the reset signal. Thereafter, the CDS circuit may sample an image signal correlated with the reset signal and compare the image signal with the first ramp signal RAMP1or the second ramp signal RAMP2to generate a comparison signal in accordance with the image signal. In an embodiment, the CDS circuit includes two comparators. For example, the two comparators may be implemented by an operational transconductance amplifier (OTA) (or a differential amplifier). Some embodiments are described below with reference toFIG.10.

The counter circuit142may count a level transition time point of a comparison result signal output from the comparators141to generate a count value and output the count value. In an embodiment, the counter circuit142includes a latch circuit and an arithmetic circuit.

The data output circuit150may temporarily store the pixel value output from the ADC circuit140and then output the pixel value. The data output circuit150may include a plurality of column memories (BF)151and a column decoder152(e.g., a decoder circuit). The column memory151stores the pixel value received from the counter circuit142. In an embodiment, each of the column memories151may be provided in the counter circuit142. The pixel values respectively stored in the column memories151may be output as image data IDTA under control by the column decoder152.

The timing controller160may output a control signal to each of the row driver120, the ramp signal generator130, the ADC circuit140, and the data output circuit150to control an operation or timing of the row driver120, the ramp signal generator130, the ADC circuit140, and the data output circuit150. In an embodiment, a control signal transmitted from the timing controller160to the first ramp signal generator130ais different from a control signal transmitted from the timing controller160to the second ramp signal generator130b, so that the operation or timing of the first ramp signal generator130ais different from that of the second ramp signal generator130b.

The signal processor170may perform noise reduction processing, gain adjustment, waveform shaping processing, interpolation processing, white balance processing, gamma processing, edge enhancement processing, and binning on the image data IDTA. In an embodiment, the signal processor170may also be located in an external processor of the image sensor100. In an embodiment, the signal processor170generates a final digital signal based on a plurality of digital signals. As an example, the signal processor170may perform an average operation on binary values of the digital signals to calculate an average value of the digital signals as a final digital signal.

FIG.2is a block diagram illustrating an implementation of an image sensor200according to an embodiment. In some embodiments, the image sensor200ofFIG.2may be an example of the image sensor100ofFIG.1. Referring toFIG.2, the image sensor200may include a pixel array110a, a first ramp signal generator130a, a second ramp signal generator130b, and an ADC circuit140a.

The pixel array110amay include a plurality of pixels PX and may be connected to a plurality of column lines CL outputting a plurality of pixel signals generated by the pixels PX. In some embodiments, a pixel group of the same color may be divided into two pixel groups PX1or PX2and may be connected to two column line groups CL1or CL2. For example, the pixels PX may include first color pixels and second color pixels. The first pixel group PX1may include some of the first color pixels and some of the second color pixels, and the second pixel group PX2may include the other first color pixels and the other second color pixels. The column lines may include a first column line group CL1and a second column line group CL2, and the first column line group CL1may output a first pixel signal from the first pixel group PX1and the second column line group CL2may output a second pixel signal from the second pixel group PX2.

The first ramp signal generator130amay include a first current source Tramp1and first variable resistor Rramp1. The second ramp signal generator130bmay include a second current source Iramp2and a second variable resistor Rramp2. The variable resistor Rramp1and Rramp2may be implemented by a potentiometer as an example. The first ramp signal generator130amay generate a ramp voltage (e.g., a first ramp voltage Vramp1inFIG.6) having a level that rises or falls with a certain slope. The second ramp signal generator130bmay generate a ramp voltage (e.g., a second ramp voltage Vramp2inFIG.6) having a level that rises or falls with a certain slope. The first ramp voltage Vramp1may be provided as the first ramp signal RAMP1to the first comparator group141a, and the second ramp voltage Vramp2may be provided as the second ramp signal RAMP2to the second comparator group141b. In an embodiment, the slope of the first ramp voltage Vramp1generated by the first ramp signal generator130ais the same as the slope of the second ramp voltage Vramp2generated by the second ramp signal generator130b.

The ADC circuit140amay include the first comparator group141a, the second comparator group141b, and a counter circuit142a. In an embodiment, the first comparator group141areceives the first ramp voltage Vramp1generated by the first ramp signal generator130aand the first pixel signal output by the first column line group CL1, and compares the first ramp voltage Vramp1with the first pixel signal to generate a comparison signal. The second comparator group141bmay receive the second ramp voltage Vramp2generated by the second ramp signal generator130band the second pixel signal output from the second column line group CL2, and compare the second ramp voltage Vramp2with the second pixel signal to generate a comparison signal.

Referring further toFIGS.1and2, a control signal transmitted from the timing controller160to the first ramp signal generator130amay be different from a control signal transmitted from the timing controller160to the second ramp signal generator130b, and a time point at which the level of the first ramp voltage Vramp1changes may be different from a time point at which the level of the second ramp voltage Vramp2changes, so that a comparison time point of the first comparator group141amay be different from a comparison time point of the second comparator group141b. When the comparison time point of the first comparator group141ais different from the comparison time point of the second comparator group141b, introduction of the same noise may be prevented and noise may be canceled with each other, thereby reducing noise of the image sensor100. Examples of the time point at which the level of the first ramp voltage Vramp1changes and the time point at which the level of the second ramp voltage Vramp2changes is described below with reference toFIGS.5to7.

The counter circuit142amay be the same as the counter circuit142ofFIG.1described above. In an embodiment, a level transition time point of the comparison result signal output from the first comparator group141aor the second comparator group141bis counted to generate a count value and the count value may be output.

FIG.3is a view illustrating arrangement of pixels of an image sensor according to an embodiment and shows a Bayer pattern. In some embodiments, a pixel group PGa ofFIG.3may be an example of the pixels PX ofFIG.2. The pixel group PGa may be repeatedly disposed in the pixel array110aofFIG.2. The Bayer pattern may refer to a pattern in which green that is 50% and red and blue that are each 25% are alternately disposed according to human visual characteristics. For example, 25% of the Bayer pattern may correspond to red pixel(s), 25% of the Bayer pattern may correspond to blue pixel(s), and 50% of the Bayer pattern may correspond to green pixel(s).

The pixel group PGa may be configured in a 2×2 Bayer pattern. For example, the pixel group PGa may include a first green pixel Gr, a red pixel R, a second green pixel Gb, and a blue pixel B, wherein the first green pixel Gr and the second green pixel Gb may be located in a diagonal direction, and the red pixel R and the blue pixel B may be located in a diagonal direction. In some embodiments, the pixel group PGa may be configured in a 4×4 Bayer pattern. For example, the pixel group PGa may include four first green pixels Gr, four red pixels R, four second green pixels Gb, and four blue pixels B. In addition to this, the pixel groups may be configured in Bayer patterns of various sizes.

Referring further toFIGS.2and3, in some embodiments, pixels of the same color may be divided into two groups to transfer a pixel signal to the first comparator group141aor the second comparator group141b. For example, the first green pixels Gr and the red pixels R may be arranged on the same row line, and some of the first green pixels Gr and some of the red pixels R may be included in the first pixel group PX1, and the other pixels among the first green pixels Gr and the other pixels among the red pixels R may be included in the second pixel group PX2. The second green pixels Gb and the blue pixels B may be arranged on the same row line some of the second green pixels Gb and some of the blue pixels B may be included in the first pixel group PX1, the other pixels among the second green pixels Gb and the other pixels among the blue pixels B may be included in the second pixel group PX2. The first column line group CL1may output first pixel signals from the first pixel group PX1, and the second column line group CL2may output second pixel signals from the second pixel group PX2.

FIGS.4A and4Bare diagrams illustrating arrangements of pixels of an image sensor according to an embodiment, and show a tetra pattern. In some embodiments, a pixel group PGc1ofFIG.4Aor a pixel group PGc2ofFIG.4Bmay be an example of the pixels PX ofFIG.2. The pixel group PGc1or PGc2may be repeatedly arranged in the pixel array110aofFIG.2.

The pixel group PGc1or PGc2may include red pixels R arranged in a 2×2 matrix, blue pixels B arranged in a 2×2 matrix, and green pixels G arranged in a 2×2 matrix, and the arrangement of these pixels may be referred to as a tetra pattern. However, the inventive concept is not limited thereto, and the pixel group PGc1or PGc2may include red pixels R arranged in an n×n matrix (n is an integer greater than or equal to 3), blue pixels B arranged in an n×n matrix, and green pixels G arranged in an n×n matrix.

Referring further toFIGS.2,4A, and4B, in some embodiments, pixels of the same color may be divided into two groups, and each of the two groups may transfer pixel signals to a corresponding comparator group, among the first comparator group141aand the second comparator group141b. For example, the green pixels G and red pixels R may be arranged on the same row line, and some (e.g., G1) of the green pixels and some (e.g., R1) of the red pixels R may be included in the first pixel group PX1, and the other pixels (e.g., G2) among the green pixels G and the other pixels (e.g., R2) among the red pixels R may be included in the second pixel group PX2. The green pixels G and the blue pixels B may be arranged on the same row line, some (e.g., G1) of the green pixels G and some (e.g., B1) of the blue pixels may be included in the first pixel group PX1, and the other pixels (e.g., G2) among the green pixels G and the other pixels (e.g., B2) among the blue pixels B may be included in the second pixel group PX2, the first column line group CL1may output first pixel signals from the first pixel group PX1, and the second column line group CL2may output second pixel signals from the second pixel group PX2.

FIG.5is a graph illustrating a time point at which a comparator according to a comparative example of the inventive concept compares a ramp signal with a pixel signal. Referring further toFIG.2, a case in which the ramp voltage Vramp1generated by the first ramp signal generator130ais equal to the ramp voltage Vramp2generated by the second ramp signal generator130bis illustrated. Graph300amay show that the first comparator group141acompares the first pixel signal with the ramp voltage Vramp1, and graph300bshows that the second comparator group141bcompares the second pixel signal with the ramp voltage Vramp2.

The first comparator group141amay sample a first reset signal received as a first pixel signal from the first pixel group PX1through the first column line group CL1, and compare the first reset signal with the ramp voltage Vramp1at time point T1to generate a comparison signal according to the first reset signal. The second comparator group141bmay sample a second reset signal received as a second pixel signal from the second pixel group through the second column line group CL2, and compare the second reset signal with the ramp voltage Vramp2at time point T1to generate a comparison signal according to the second reset signal. The first comparator group141amay store the first reset signal. The second comparator group141bmay store the second reset signal. The first comparator group141amay sample a first image signal correlated with the first reset signal, and compare the first image signal with the ramp voltage Vramp1at time point T2to generate a comparison signal in accordance with the first image signal. The second comparator group141bmay sample a second image signal correlated with the second reset signal, and compare the second image signal with the ramp voltage Vramp2at time point T2to generate a comparison signal in accordance with the second image signal.

When the ramp voltage Vramp1generated by the first ramp signal generator130ais equal to the ramp voltage Vramp2generated by the second ramp signal generator130b, the first comparator group141aand the second comparator group141bmay generate the comparison signal at the same time point (T1or T2), and the same noise may be introduced and reinforce each other, so the noise may be amplified and performance of the image sensor may be degraded due to the amplified noise.

FIGS.6and7are graphs illustrating a time point at which a comparator according to an embodiment compares a ramp signal with a pixel signal. Referring further toFIG.2, a case in which a time point at which the level of the ramp voltage Vramp1generated by the first ramp signal generator130achanges is different from a time point at which the level of the ramp voltage Vramp2generated by the second ramp signal generator130bchanges is illustrated. A graph400aor500amay show that the first comparator group141acompares the first pixel signal with the ramp voltage Vramp1, and a graph400bor500bmay show that the second comparator group141bcompares the second pixel signal with the ramp voltage Vramp1.

In an embodiment, the first comparator group141aand the second comparator group141bmay be CDS circuits. The CDS circuit may sample a pixel signal provided from the pixel group PX1or PX2according to a CDS method.

Referring toFIGS.1,2, and6, in an embodiment, a control signal transmitted from the timing controller160to the first ramp signal generator130ais different from a control signal transmitted from the timing controller160to the second ramp signal generator130b, the ramp voltage Vramp1generated by the first ramp signal generator130ahas the same slope as that of the ramp voltage Vramp2generated by the second ramp signal generator130b, and a time point at which the level of the ramp voltage Vramp1transitions is different from a time point at which the level of the ramp voltage Vramp2transitions by T5. The first comparator group141amay sample the first reset signal received as the first pixel signal from the first pixel group PX1through the first column line group CL1and compare the first reset signal with the ramp voltage Vramp1at the time point T1to generate a comparison signal in accordance with the first reset signal, and the second comparator group141bmay sample the second reset signal received as the second pixel signal from the second pixel group PX2through the second column line group CL2and compare the second reset signal with the ramp voltage Vramp2at time point T3later by T5than time point T1. The first comparator group141amay store a first reset signal. The second comparator group141bmay store a second reset signal. Thereafter, the first comparator group141amay sample the first image signal correlated with the first reset signal and compare the first image signal with the ramp voltage Vramp1at time point T2to generate a comparison signal in accordance with the first image signal, and the second comparator group141bmay sample the second image signal correlated with the second reset signal and compare the second image signal with the ramp voltage Vramp2at time point T4later by T5than time point T1to generate a comparison signal in accordance with the second image signal.

Referring toFIGS.1,2, and7, a control signal transmitted from the timing controller160to the first ramp signal generator130ais different from a control signal transmitted from the timing controller160to the second ramp signal generator130b, the slope at which the level of the ramp voltage Vramp1generated by the first ramp signal generator130afalls is the same as the slope at which the level of the ramp voltage Vramp2generated by the second ramp signal generator130bfalls, and time points at which the levels fall are different from each other. The first comparator group141amay sample the first reset signal received as the first pixel signal from the first pixel group PX1through the first column line group CL1and compare the first reset signal with the ramp voltage Vramp1at the time point T1to generate a comparison signal in accordance with the first reset signal. The second comparator group141bmay sample the second reset signal received as the second pixel signal from the second pixel group PX2through the second column line group CL2and compare the second reset signal with the ramp voltage Vramp2at time point T3′ later than time point T1. The first comparator group141aor the second comparator group141bmay store a first reset signal or a second reset signal. Thereafter, the first comparator group141amay sample the first image signal correlated with the first reset signal and compare the first image signal with the ramp voltage Vramp1at time point T2to generate a comparison signal in accordance with the first image signal. The second comparator group141bmay sample the second image signal correlated with the second reset signal and compare the second image signal with the ramp voltage Vramp2at time point T4′ earlier than time point T2to generate a comparison signal in accordance with the second image signal. However, the embodiments are not limited thereto, and time point T1may be different from time point T3′, and time point T2may be different from time point T4′. For example, time point T3′ may occur earlier than time point T1, and time point T2may occur earlier than time point T4′.

Referring toFIGS.6and7, when a time point at which the level of the ramp voltage Vramp1generated by the first ramp signal generator130achanges is different from a time point at which the level of the ramp voltage Vramp2generated by the second ramp signal generator130bchanges, a time point at which the first comparator group141agenerates the comparison signal in accordance with the pixel signal may be different from a time point at which the second comparator group141bgenerates the comparison signal in accordance with the pixel signal. That is, because time point T1may be different from time point T3(or time point T3′) and time point T2may be different from time point T4(or time point T4′), the same noise may be prevented from being introduced and noise may be canceled out with each other, thereby improving the performance of the image sensor.

FIG.8is a block diagram illustrating an implementation example of an image sensor200aaccording to an embodiment. In some embodiments, the image sensor200aofFIG.8may be an example of the image sensor200ofFIG.2. Referring toFIG.8, the image sensor200amay include a pixel array110a′, a first ramp signal generator130a′, a second ramp signal generator130b′, an ADC circuit140a′, and a multiplexer600.

The pixel array110a′ may be an example of the pixel array110aofFIG.2described above. For example, the first pixel group PX1may include pixels arranged in a (4n+1)-th (n is an integer greater than or equal to 0) column and a (4n+2)-th column, and the second pixel group PX2may include pixels arranged in a (4n+3)-th column and a (4n+4)-th column. The pixels of the first pixel group PX1may be connected to a (4n+1)-th (n is an integer greater than or equal to 0) column line and a (4n+2)-th column line, and the second pixel group PX2may be connected to a (4n+3)-th column line and a (4n+4)-th column line.

The first ramp signal generator130a′ may be the same as the first ramp signal generator130aofFIG.2described above, the second ramp signal generator130b′ may be the same as the second ramp signal generator130bofFIG.2described above, and the ADC circuit140a′ may be the same as the ADC circuit140aofFIG.2described above. Descriptions that are previously given are omitted.

The multiplexer600may connect column line groups connected to the pixel array110a′ to comparator groups, and may change a connection relationship between the column line groups and the comparator groups according to a mode change signal. In an embodiment, in a first mode, the multiplexer600receives a first mode signal MS1, connects the first column line group CL1connected to the first pixel group PX1of the pixel array110a′ to the first comparator group141a′ receiving the ramp voltage Vramp1generated by the first ramp signal generator130a′, and may connect the second column line group CL2connected to the second pixel group PX2of the pixel array110a′ to a second comparator group141b′ receiving the ramp voltage Vramp2generated by the second ramp signal generator130b′. For example, the first comparator group141a′ may be connected to the (4n+1)-th column line and the (4n+2)-th column line, and the second comparator group141b′ may be connected to the (4n+3)-th column line and the (4n+4)-th column line. At this time, the ramp voltage Vramp1generated by the first ramp signal generator130a′ may have the same slope as that of the ramp voltage Vramp2generated by the second ramp signal generator130b′ and time points thereof at which levels thereof change to have a slope may be different from each other. Accordingly, a time point at which the first comparator group141a′ compares the first pixel signal received from the first column line group CL1with the ramp voltage Vramp1may be different from a time point at which the second comparator group141b′ compares the second pixel signal received from the second column line group141b′ with the ramp voltage Vramp2. An operation in the first mode is described below with reference toFIGS.9A and9B.

In an embodiment, the multiplexer600receives a second mode signal MS2in the second mode, and the image sensor200areads one row line of the pixel array110a′ during a first period and a second period. For example, during the first period, the multiplexer600may connect some of the column lines of the first column line group CL1to the first comparator group141a′ and the second comparator group141b′ and may connect some of the column lines of the second column line group CL2to the first comparator group141a′ and the second comparator group141b′. For example, some of the column lines of the first column line group CL1may be the (4n+1)-th column line, and some of the column lines of the second column line group CL2may be the (4n+3)-th column line.

After the first period, the multiplexer600may connect the other column lines of the first column line group CL1to the first comparator group141a′ and the second comparator group141b′ and connect the other column lines of the second column line group CL2to the first comparator group141a′ and the second comparator group141b′. For example, the other column lines of the first column line group CL1may be the (4n+2)-th column line, and the other column lines of the second column line group CL2may be the (4n+4)-th column line. The ramp voltage Vramp1generated by the first ramp signal generator130a′ may have a slope different from that of the ramp voltage Vramp2generated by the second ramp signal generator130b′. An operation in the second mode is described below with reference toFIGS.9A and9C.

FIG.9Ais a block diagram illustrating an implementation example of a pixel array110baccording to an embodiment, andFIGS.9B and9Care tables illustrating operations according to modes of an image sensor according to an embodiment. In some embodiments, the pixel array110bofFIG.9Amay be an example of the pixel array110a′ ofFIG.8,FIG.9Bshows an example illustrating a first mode operation of the image sensor200aofFIG.8according to the first mode signal MS1, andFIG.9Cmay be an example illustrating a second mode operation of the image sensor200aofFIG.8according to the second mode signal MS2.

In some embodiments, referring toFIGS.3and9A, the pixel array110bmay include the pixel group PGa ofFIG.3, and the pixel group of the same color may be divided into two groups. For example, the first green pixels Gr may be divided into Gr1 pixels and Gr2 pixels, red pixels R may be divided into R1 pixels and R2 pixels, blue pixels B may be divided into B1 pixels and B2 pixels, and the second green pixels Gb may be divided into Gb1 pixels and Gb2 pixels. The Gr1, R1, Gr2, and R2 pixels may be sequentially arranged on one row line, and B1, Gb1, B2, and Gb2 pixels may be sequentially arranged on another row line.

In some embodiments, referring toFIGS.8,9A, and9B, when the multiplexer600receives the first mode signal MS1, the multiplexer600may connect the column line CL connected to the Gr1 pixel, the R1 pixel, the B1 pixel, and the Gb1 pixel to the first comparator group141a′ receiving the ramp voltage Vramp1generated by the first ramp signal generator130a′ and may connect the column line CL connected to the Gr2 pixel, the R2 pixel, the B2 pixel, and the Gb2 pixel to the second comparator group141b′ receiving the ramp voltage Vramp2generated by the second ramp signal generator130b′. The ramp voltage Vramp1generated by the first ramp signal generator130a′ and the ramp voltage Vramp2generated by the second ramp signal generator130b′ may have the same slope, and time points at which the levels change to have the slope may be different. Therefore, a time point at which the first comparator group141a′ compares a pixel signal of the Gr1 pixel with the ramp voltage Vramp1may be different from a time point at which the second comparator group141b′ compares a pixel signal of the Gr2 pixel with the ramp voltage Vramp2, a time point at which the first comparator group141a′ compares a pixel signal of the R1 pixel with the ramp voltage Vramp1may be different from a time point at which the second comparator group141b′ compares a pixel signal of the R2 pixel with the ramp voltage Vramp2, a time point at which the first comparator group141a′ compares a pixel signal of the B1 pixel with the ramp voltage Vramp1may be different from a time point at which the second comparator group141b′ compares a pixel signal of the pixel B2 with the ramp voltage Vramp2, and a time point at which the first comparator group141a′ compares a pixel signal of the Gb1 pixel with the ramp voltage Vramp1may be different from a time point at which the second comparator group141b′ compares a pixel signal of the Gb2 pixel with the ramp voltage Vramp2, so that introduction of the same noise may be prevented and pieces of noise may be canceled out with each other, thereby reducing noise to increase the performance of the image sensor.

In some embodiments, referring toFIGS.8,9A, and9C, when the multiplexer600receives the second mode signal MS2, the multiplexer600may connect the column line CL connected to the Gr1 pixel to the first comparator group141a′ and the second comparator group141b′ and may connect the column line CL connected to the Gr2 pixel to the first comparator group141a′ and the second comparator group141b′ during a first period 1 h-time. During a second period 2 h-time, the multiplexer600may connect the column line CL connected to the R1 pixel to the first comparator group141a′ and the second comparator group141b′ and may connect the column line CL connected to the R2 pixel to the first comparator group141a′ and the second comparator group141b′. During a third period 3 h-time, the multiplexer600may connect the column line CL connected to the B1 pixel to the first comparator group141a′ and the second comparator group141b′ and may connect the column line CL connected to the B2 pixel to the first comparator group141a′ and the second comparator group141b′. During a fourth period 4 h-time, the multiplexer600may connect the column line CL connected to the Gb1 pixel to the first comparator group141a′ and the second comparator group141b′ and may connect the column line CL connected to the Gb2 pixel to the first comparator group141a′ and the second comparator group141b′. The first ramp voltage Vramp1generated by the first ramp signal generator130a′ may have a slope different from that of the second ramp voltage Vramp2generated by the second ramp signal generator130b′. Therefore, for a pixel signal of one of the Gr1 pixels, Gr2 pixels, R1 pixels, R2 pixels, B1 pixels, B2 pixels, Gb1 pixels, and Gb2 pixels, two comparison signal values (a comparison signal value compared with the first ramp voltage Vramp1and a comparison signal value compared with the second ramp voltage Vramp2) may be generated, and one of the two comparison signal values may be used in a dark screen and the other signal value among the two comparison signal values may be used in a bright screen, and thus, a dynamic range (DR) may increase. For example, the slope of the first ramp voltage Vramp1may be smaller than the slope of the second ramp voltage Vramp2, in a dark screen, the comparison signal value compared with the first ramp voltage Vramp1may be used, and in a bright screen, a comparison signal value compared with the second ramp voltage Vramp2may be used.

FIG.10is a block diagram illustrating a portion of an image sensor800according to an embodiment. In some embodiments, the image sensor800ofFIG.10may be an example of the image sensor200ofFIG.2. The image sensor800may include a pixel111and an ADC circuit140a′.

The pixel111may be one of the pixels PX included in the pixel array110aofFIG.2, and may include a photodiode PD and a plurality of transistors, e.g., a transfer transistor TX, a reset transistor RX, a driving transistor DX, and a selection transistor SX. The photodiode PD may convert light incident from the outside into an electrical signal. The photodiode PD generates a charge according to light intensity. The reset transistor RX may be turned on in response to a reset control signal RS applied to a gate terminal thereof to reset a floating diffusion node FD based on a pixel power voltage VDD. The transfer transistor TX may be turned on in response to a transfer control signal TG applied to the gate terminal thereof to transmit a charge generated by the photodiode PD to the floating diffusion node FD. Charges may be accumulated in the floating diffusion node FD. Charges accumulated in the floating diffusion node FD may generate a voltage. The driving transistor DX may operate as a source follower based on a bias current Ib generated by a current source CS connected to the column line CL, and output a voltage corresponding to a voltage of the floating diffusion node FD, as a pixel voltage PXS through the selection transistor SX. The selection transistor SX may select the pixel PX. The selection transistor SX may be turned on in response to a selection signal SEL applied to the gate terminal and output the pixel voltage PXS (or current) output from the driving transistor DX to a column line COL. The pixel voltage PXS may be provided to the ADC circuit140a′ through the column line COL.

The ADC circuit140a′ may include a comparator141a′ and a counter circuit142a′. The comparator141a′ may be one of the first comparator group141aand the second comparator group141bofFIG.2, and is described below as the first comparator group141a, but embodiments are not limited thereto. The comparator141a′ may include a first amplifier141_1COMP1and a second amplifier141_2COMP2. The comparator141a′ may be initialized in response to an auto-zero signal in an auto-zero period before performing a comparison operation, and may control a bias current or voltage in response to switch control signals while performing a comparison operation.

The first amplifier141_1COMP1may be implemented to compare a pixel voltage PXS output through the column line COL received through an input capacitor C1to a ramp signal Ramp Gen1generated by the first ramp signal generator130areceived through an input capacitor C2and output a comparison result. The first amplifier141_1COMP1may further include switches, and may remove an offset of the first amplifier141_1COMP1in response to a switch control signal.

The second amplifier141_2COMP2may be implemented to amplify an output OUT1of the first amplifier141_1COMP1. For example, the second amplifier141_2COMP2may include a differential amplifier, and an output OUT2of the second amplifier141_2COMP2may be provided to the counter circuit142a′ as a comparison result signal. The second amplifier141_2COMP2may further include switches, and may remove an offset of the second amplifier141_2COMP2in response to a switch control signal.

The counter circuit142a′ may be the same as the counter circuit142aofFIG.2and may be implemented to count the comparison result signal OUT2based on a counting clock signal CNT_CLK and an inverted signal CONV to generate and output a counted digital signal DS. The digital signal DS may have an image component from which a reset component is removed from the pixel voltage PXS, that is, a digital value corresponding to the image signal.

FIGS.11A and11Bare block diagrams of an electronic device1000including a multi-camera module.FIG.12is a detailed block diagram of a camera module1100bofFIGS.11A and11B.

Referring toFIG.11A, the electronic device1000may include a camera module group1100, an application processor (AP)1200, a power management integrated circuit (PMIC)1300, and an external memory1400.

The camera module group1100may include a plurality of camera modules1100a,1100b, and1100c. Although an embodiment in which three camera modules1100a,1100b, and1100care arranged is illustrated, embodiments are not limited thereto. In some embodiments, the camera module group1100may include only two camera modules or may be modified to include n (n is a natural number of 4 or greater) camera modules.

Hereinafter, a detailed configuration of the camera module1100bis described in detail with reference toFIG.12, but the following description may be equally applied to the other camera modules1100aand1100caccording to embodiments.

Referring toFIG.12, the camera module1100bmay include a prism1105, an optical path folding element (OPFE)1110, an actuator1130, an image sensing device1140, and storage1150.

The prism1105may include a reflective surface1107of a light reflective material to change a path of light L incident from the outside.

In some embodiments, the prism1105may change the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. In addition, the prism1105may rotate the reflective surface1107of the light reflective material in an A direction based on a central axis1106or rotate the central axis1106in a B direction to change the path of light L incident in the first direction X to the second direction Y perpendicular thereto. Here, the OPFE1110may also move in a third direction Z perpendicular to the first direction X and the second direction Y.

In some embodiments, as shown, a maximum angle of rotation of the prism1105in the A direction may be less than 15 degrees in a plus (+) A direction and greater than 15 degrees in a minus A direction, but the embodiments are not limited thereto.

In some embodiments, the prism1105may move the reflective surface1107of the light reflective material in a third direction (e.g., a Z direction) parallel to an extension direction of the central axis1106.

In some embodiments, the camera module1100bmay include two or more prisms, through which the path of the light L incident in the first direction X may change to the second direction perpendicular to the first direction X, to the first direction X or the third direction Z again, and to the second direction Y again.

The OPFE1110may include, for example, optical lenses including m (here, m is a natural number) groups. The m lenses may move in the second direction Y to change an optical zoom ratio of the camera module1100b. For example, when a basic optical zoom ratio of the camera module1100bis Z and m optical lenses included in the OPFE1110are moved, the optical zoom ratio of the camera module1100bmay change to an optical zoom ratio of 3Z or 5Z or to an optical zoom ratio of 5Z or higher.

The actuator1130may move the OPFE1110or an optical lens (hereinafter referred to as an optical lens) to a certain position. For example, the actuator1130may adjust a position of the optical lens so that an image sensor (or a sensor)1142is located at a focal length of the optical lens for accurate sensing.

The image sensing device1140may include the image sensor1142, a control logic (or a logic)1144, and a memory1146. The image sensor1142may sense an image of a sensing target using light L provided through the optical lens. In some embodiments, the image sensor1142may include two ramp signal generators (e.g., the first ramp signal generator130aand the second ramp signal generator130binFIG.2), two comparator groups (e.g., the first comparator group141aand the second comparator group141binFIG.2), and a pixel array including a pixel group in which pixel groups of the same color are divided into two groups (e.g., the pixel array110ainFIG.2). Each of the ramp signals generated by the two ramp signal generators may have the same slope, and time points at which the levels change to have the slopes may be different from each other. Accordingly, the two comparator groups compare the pixel signals of the pixel groups divided into two groups at different time points to prevent the same noise from being introduced and to cancel out pieces of noise with each other to reduce noise.

The control logic1144may control the overall operation of the camera module1100band process a sensed image. For example, the control logic1144may control the operation of the camera module1100baccording to a control signal provided through the control signal line CSLb, and extract image data corresponding to a certain image (e.g., a person's face, arms, legs, etc.) from the sensed image.

In some embodiments, the control logic1144may perform image processing, such as encoding and noise reduction of the sensed image. As an embodiment, the control logic1144may receive compressed configuration data through the control signal line CSLb and decompress the received compressed configuration data.

The memory1146may store information required for operation of the camera module1100b, such as configuration data or calibration data1147. The memory1146may store the compressed configuration data and decompressed configuration data. The configuration data may include sensor calibration information including crosstalk (XTK) and lens shading correction (LSC), FW TnP, sensor exposure time, gain, and the like. The calibration data1147is information used to calibrate the camera module1100bto generate image data using the light L provided from the outside. The calibration data1147may include, for example, information on the degree of rotation, information on a focal length, information on an optical axis, and the like. When the camera module1100bis implemented in the form of a multi-state camera in which the focal length changes according to the position of the optical lens, the calibration data1147may include a focal length value for each position (or state) of the optical lens and information related to auto-focusing.

The storage1150may store image data sensed through the image sensor1142. The storage1150may be located outside the image sensing device1140and may be implemented in a stacked form with a sensor chip constituting the image sensing device1140. In some embodiments, the image sensor1142may be configured as a first chip, and the control logic1144, the storage1150, and the memory1146may be configured as a second chip, so that the two chips may be implemented in a stacked form.

In some embodiments, the storage1150may be implemented as electrically erasable programmable read-only memory (EEPROM), but embodiments are not limited thereto. In some embodiments, the image sensor1142includes a pixel array, and the control logic1144may include an ADC and an image signal processor processing the sensed image.

Referring toFIGS.11A and12together, in some embodiments, each of the camera modules1100a,1100b, and1100cmay include an actuator1130. Accordingly, each of the camera modules1100a,1100b, and1100cmay include the same or different calibration data1147according to the operation of the actuator1130included therein.

In some embodiments, one camera module (e.g.,1100b), among the camera modules1100a,1100b, and1100c, is a folded lens-type camera module including the prism1105and the OPFE1110described above. camera module, and the other camera modules (e.g.,1100aand1100c) may be vertical camera modules that do not include the prism1105and the OPFE1110, but are not limited thereto.

In some embodiments, one camera module (e.g.,1100c), among the camera modules1100a,1100b, and1100c, may be a vertical-type depth camera extracting depth information using infrared rays (IR), for example. In this case, the AP1200may generate a 3D depth image by merging image data provided from the depth camera and image data provided from another camera module (e.g.,1100aor1100b).

In some embodiments, each of the camera modules1100a,1100b, and1100cmay be located to be physically separated from another. That is, the camera modules1100a,1100b, and1100cmay not use a divided portion of a sensing region of the single image sensor1142, but the independent image sensor1142may be located in each of the camera modules1100a,1100b, and1100c.

Referring back toFIG.11A, the AP1200may include an image processing device1210, a memory controller1220, and an internal memory1230. The AP1200may be implemented as a semiconductor chip separately from the camera modules1100a,1100b, and1100c, for example.

The image processing device1210may include a plurality of sub-image processors (or sub-processors)1212a,1212b, and1212c, an image generator1214, and a camera module controller1216.

The image processing device1210may include a plurality of sub-image processors1212a,1212b, and1212ccorresponding to the number of camera modules1100a,1100b, and1100c.

Image data generated by the camera module1100amay be provided to the sub-image processor1212athrough an image signal line ISLa, image data generated by the camera module1100bmay be provided to the sub-image processor1212bthrough an image signal line ISLb, and image data generated by the camera module1100cmay be provided to the sub-image processor1212cthrough an image signal line ISLc. Such image data transmission may be performed using, for example, a camera serial interface (CSI) based on mobile industry processor interface (MIPI), but is not limited thereto.

Meanwhile, in some embodiments, one sub-image processor may be arranged to correspond to a plurality of camera modules. For example, the sub-image processor1212aand the sub-image processor1212cmay not be separately implemented as shown, but may be integrated into one sub-image processor, and image data provided from the camera module1100aand the camera module1100cmay be selected through a selection element (e.g., a multiplexer) and the like, and then provided to the integrated sub-image processor. In this case, the sub-image processor1212bmay not be integrated and may receive image data from the camera module1100b.

Also, in some embodiments, image data generated by the camera module1100amay be provided to the sub-image processor1212athrough the image signal line ISLa, image data generated by the camera module1100bmay be provided to the sub-image processor1212bthrough the image signal line ISLb, and image data generated by the camera module1100cmay be provided to the sub-image processor1212cthrough the image signal line ISLc. Also, the image data processed by the sub-image processor1212bmay be directly provided to the image generator1214, while one of the image data processed by the sub-image processor1212aand the image data processed by the sub-image processor1212cmay be selected by a selection element (e.g., a multiplexer) and then provided to the image generator1214.

The image data processed by each of the sub-image processors1212a,1212b, and1212cmay be provided to the image generator1214. The image generator1214may generate an output image using image data provided from each of the sub-image processors1212a,1212b, and1212caccording to image generating information or a mode signal.

Referring toFIG.11B, in some embodiments, the image processing device1210may further include a selection unit (or a Mux)1213selecting outputs from the sub-image processors1212a,1212b, and1212cand transferring the selected output to the image generator1214.

In this case, the selection unit1213may perform different operations according to a zoom signal or zoom factor. For example, when the zoom signal is a fourth signal (e.g., a zoom magnification is a first magnification), the selection unit1213may select one of the outputs from the sub-image processors1212a,1212b, and1212cand transfer the selected output to the image generator1214.

Also, when the zoom signal is a fifth signal (e.g., the zoom factor is a second factor) different from the fourth signal, the selection unit1213may sequentially transfer p outputs, among the outputs from the sub-image processors1212a,1212b, and1212c, to the image generator1214. For example, the selection unit1213may sequentially transfer the outputs from the sub-image processor1212band the sub-image processor1212cto the image generator1214. Also, the selection unit1213may sequentially transfer the outputs from the sub-image processor1212aand the sub-image processor1212bto the image generator1214. The image generator1214may generate an output image by merging the p outputs that are sequentially provided.

Here, image processing, such as demosaic, down scaling to a video/preview resolution size, gamma correction, and high dynamic range (HDR) processing, may be performed in advance by the sub-image processors1212a,1212b, and1212c, and resultant image data may be transferred to the image generator1214. Therefore, even if the resultant image data is provided to the image generator1214to one signal line through the selection unit1213, the image merging operation of the image generator1214may be performed at a high speed.

In some embodiments, the image generator1214may receive a plurality of pieces of image data having different exposure times from at least one of the sub-image processors1212a,1212b, and1212c, and perform an HDR operation on the image data, thereby generating merged image data with increased dynamic range.

The camera module controller1216may provide control signals respectively to the camera modules1100a,1100b, and1100c. The control signals generated by the camera module controller1216may be provided to corresponding camera modules1100a,1100b, and1100cthrough separate control signal lines CSLa, CSLb, and CSLc, respectively.

The AP1200may store the received image signal, that is, an encoded image signal, in the internal memory1230or the external memory1400of the AP1200, and thereafter, the AP1200may read the encoded image signal from the internal memory1230or the external memory1400, decode the read image signal, and display image data generated based on the decoded image signal. For example, a corresponding sub-image processor, among the sub-image processors1212a,1212b, and1212c, of the image processing device1210may perform decoding and may also perform image processing on the decoded image signal.

The PMIC1300may supply power, for example, a power supply voltage, to each of the camera modules1100a,1100b, and1100c. For example, the PMIC1300may supply first power to the camera module1100athrough a power signal line PSLa, supply second power to the camera module1100bthrough a power signal line PSLb, and supply third power to the camera module1100cthrough a power signal line PSLc.