Address translation for scalable linked devices

Systems, methods, and devices can include a processing engine implemented at least partially in hardware, the processing engine to process memory transactions; a memory element to index physical address and virtual address translations; and a memory controller logic implemented at least partially in hardware, the memory controller logic to receive an index from the processing engine, the index corresponding to a physical address and a virtual address; identify a physical address based on the received index; and provide the physical address to the processing engine. The processing engine can use the physical address for memory transactions in response to a streaming workload job request.

BACKGROUND

Accelerators are a type of connected device or endpoint that can offload general purpose processing and execute certain workloads more efficiently in terms of performance and power. Address virtualization capabilities allow for scalable, robust use of accelerators, address virtualization capabilities. An operating system can manage virtual address spaces and the assignment of real memory to virtual memory. Address translation hardware in the central processing unit, often referred to as a memory management unit or MMU, can translate virtual addresses to physical addresses, and vice versa.

DETAILED DESCRIPTION

Although the following embodiments may be described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™. And may be also used in other devices, such as handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatus', methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As will become readily apparent in the description below, the embodiments of methods, apparatus', and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) are vital to a ‘green technology’ future balanced with performance considerations.

As computing systems are advancing, the components therein are becoming more complex. As a result, the interconnect architecture to couple and communicate between the components is also increasing in complexity to ensure bandwidth requirements are met for optimal component operation. Furthermore, different market segments demand different aspects of interconnect architectures to suit the market's needs. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings. Yet, it is a singular purpose of most fabrics to provide highest possible performance with maximum power saving. Below, a number of interconnects are discussed, which would potentially benefit from aspects of the disclosure described herein.

Referring toFIG. 1, an embodiment of a block diagram for a computing system including a multicore processor is depicted. Processor100includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SOC), or other device to execute code. Processor100, in one embodiment, includes at least two cores—core101and102, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor100may include any number of processing elements that may be symmetric or asymmetric.

Physical processor100, as illustrated inFIG. 1, includes two cores—core101and102. Here, core101and102are considered symmetric cores, i.e. cores with the same configurations, functional units, and/or logic. In another embodiment, core101includes an out-of-order processor core, while core102includes an in-order processor core. However, cores101and102may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a translated Instruction Set Architecture (ISA), a co-designed core, or other known core. In a heterogeneous core environment (i.e. asymmetric cores), some form of translation, such a binary translation, may be utilized to schedule or execute code on one or both cores. Yet to further the discussion, the functional units illustrated in core101are described in further detail below, as the units in core102operate in a similar manner in the depicted embodiment.

As depicted, core101includes two hardware threads101aand101b, which may also be referred to as hardware thread slots101aand101b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor100as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers101a, a second thread is associated with architecture state registers101b, a third thread may be associated with architecture state registers102a, and a fourth thread may be associated with architecture state registers102b. Here, each of the architecture state registers (101a,101b,102a, and102b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers101aare replicated in architecture state registers101b, so individual architecture states/contexts are capable of being stored for logical processor101aand logical processor101b. In core101, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block130may also be replicated for threads101aand101b. Some resources, such as re-order buffers in reorder/retirement unit135, ILTB120, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB115, execution unit(s)140, and portions of out-of-order unit135are potentially fully shared.

Processor100often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. InFIG. 1, an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core101includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer120to predict branches to be executed/taken and an instruction-translation buffer (I-TLB)120to store address translation entries for instructions.

Core101further includes decode module125coupled to fetch unit120to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots101a,101b, respectively. Usually core101is associated with a first ISA, which defines/specifies instructions executable on processor100. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic125includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below decoders125, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders125, the architecture or core101takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note decoders126, in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders126recognize a second ISA (either a subset of the first ISA or a distinct ISA).

In one example, allocator and renamer block130includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads101aand101bare potentially capable of out-of-order execution, where allocator and renamer block130also reserves other resources, such as reorder buffers to track instruction results. Unit130may also include a register renamer to rename program/instruction reference registers to other registers internal to processor100. Reorder/retirement unit135includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

Here, cores101and102share access to higher-level or further-out cache, such as a second level cache associated with on-chip interface110. Note that higher-level or further-out refers to cache levels increasing or getting further way from the execution unit(s). In one embodiment, higher-level cache is a last-level data cache—last cache in the memory hierarchy on processor100—such as a second or third level data cache. However, higher level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder125to store recently decoded traces. Here, an instruction potentially refers to a macro-instruction (i.e. a general instruction recognized by the decoders), which may decode into a number of micro-instructions (micro-operations).

In the depicted configuration, processor100also includes on-chip interface module110. Historically, a memory controller, which is described in more detail below, has been included in a computing system external to processor100. In this scenario, on-chip interface11is to communicate with devices external to processor100, such as system memory175, a chipset (often including a memory controller hub to connect to memory175and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus105may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

Memory175may be dedicated to processor100or shared with other devices in a system. Common examples of types of memory175include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device180may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.

Recently however, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor100. For example in one embodiment, a memory controller hub is on the same package and/or die with processor100. Here, a portion of the core (an on-core portion)110includes one or more controller(s) for interfacing with other devices such as memory175or a graphics device180. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, on-chip interface110includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link105for off-chip communication. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory175, graphics processor180, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.

In one embodiment, processor100is capable of executing a compiler, optimization, and/or translator code177to compile, translate, and/or optimize application code176to support the apparatus and methods described herein or to interface therewith. A compiler often includes a program or set of programs to translate source text/code into target text/code. Usually, compilation of program/application code with a compiler is done in multiple phases and passes to transform hi-level programming language code into low-level machine or assembly language code. Yet, single pass compilers may still be utilized for simple compilation. A compiler may utilize any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

Larger compilers often include multiple phases, but most often these phases are included within two general phases: (1) a front-end, i.e. generally where syntactic processing, semantic processing, and some transformation/optimization may take place, and (2) a back-end, i.e. generally where analysis, transformations, optimizations, and code generation takes place. Some compilers refer to a middle, which illustrates the blurring of delineation between a front-end and back end of a compiler. As a result, reference to insertion, association, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes, as well as any other known phases or passes of a compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, etc. in one or more phases of compilation, such as insertion of calls/operations in a front-end phase of compilation and then transformation of the calls/operations into lower-level code during a transformation phase. Note that during dynamic compilation, compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution during runtime. As a specific illustrative example, binary code (already compiled code) may be dynamically optimized during runtime. Here, the program code may include the dynamic optimization code, the binary code, or a combination thereof.

Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and/or translate code. Therefore, reference to execution of code, application code, program code, or other software environment may refer to: (1) execution of a compiler program(s), optimization code optimizer, or translator either dynamically or statically, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (2) execution of main program code including operations/calls, such as application code that has been optimized/compiled; (3) execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software related operations, or to optimize code; or (4) a combination thereof.

Process Address Space ID (PASID) allows multiple software processes to operate within their own unique address space without unwanted accesses by other processes. To achieve this, platform infrastructure manages translating Virtual Addresses (VAs) from various address spaces to system memory Physical Addresses (PAs). Address Translation Services (ATS) can optimize the management of translations. A device can store translations (PAs) in an Address Translation Cache (ATC), and then issue translated addresses rather than untranslated addresses to access the rest of the system.

While there are significant benefits to having devices support ATS, implementing an ATC can be costly in terms of complexity and real estate. This disclosure describes how accelerators can implement an ATC using a hybrid prefetching algorithm and use a prefetch buffer for storing VA and PAs mapped to an index.

Streaming workloads for connected devices, such as accelerators, have high throughput and low long term locality, which makes caching less effective than prefetching. The prefetching approach requests each address translation shortly before the translation is needed, and then explicitly discards the translation after it has been used. In conjunction with prefetching, single-entry caches can be used to reduce redundant translations of large pages.

This disclosure describes an implementation of Address Translation Services (ATS) and Translation Prefetch Buffer (TPB) (or prefetch ATC) optimized for streaming workload devices that have high throughput and low long term address locality.FIG. 2is a schematic diagram of an example computer system200that includes an Address Translation Service and Translation Prefetch Buffer in accordance with embodiments of the present disclosure. The system200includes a root complex (RC)202(e.g., PCIe RC) or other type of device hosting system (e.g., PCI bridge). The RC202connects a processor and memory subsystem (e.g., memory204) to one or more devices, such as device216coupled to the RC202by a root port (RP)214and a multi-lane link. The RC202can include a root complex integrated endpoint (RCiEP)210. In some embodiments, a switch fabric222can be coupled to the RC202via an RP220across a multi-lane link. The switch fabric222can be coupled to one or more devices (224,228) across a multi-lane link to connect the devices224and228to the RC202.

The RC202is coupled to a memory subsystem204. Memory subsystem204can be system memory for a host system, shared memory, other accessible memory. The memory subsystem204can be used by the one or more devices for memory transactions, such as reads and writes, to execute jobs tasked by the host system. The system200also includes an address translation agent206coupled to an address translation and protection table (ATPT)208. The address translation agent206can include hardware circuitry, software, or a combination of hardware and software. The address translation agent206and the ATPT208can be used to provide address translation services (ATS) for address spaces in the memory subsystem204to allow one or more of the devices to perform memory transactions to satisfy job requests issued by the host system. InFIG. 2, RCiEP210is illustrated to be performing address translation services with the translation agent206.

The RCiEP210and devices216,224, and228can be devices that are compliant with an interconnect protocol, such as PCIe. Examples of devices include accelerators, disk controller, network controller, graphics controller, or other type of device that is involved in streaming workloads. Each of RCiEP210and devices216,224, and228can include a translation prefetch buffer212,218,226, and230, respectively. The translation prefetch buffers (TPBs) can include an indexed random access memory for storing a mapping between virtual addresses and physical addresses, and can index the mapping. Other types of memory can be used for the TPB. The TPB can be considered a memory element that has one or more memory element locations or entries, and each memory element location can be indexed. An index value can point to a memory element location that is allocated for or contains a VA and PA translation.

In some embodiments, the TPB can include a single-entry cache, as described below. The TPB can be used in addition to or in the alternative to an address translation cache. In embodiments, the address translation cache can be augmented or enhanced with memory elements to allow for index-based retrieval of virtual address translations.

The root complex202, root ports214and220, switch fabric222, and the links can be compliant with the PCIe protocol. Other interconnect protocols are also within the scope of the disclosure.

Accelerator device workloads may be generalized as involving reading data from memory, processing that data, and then writing the processed data back to memory. With the addition of ATS, the device manages the translation of provided Virtual Addresses (VAs) to Physical Addresses (PAs). To read from memory, the device first translates (or requests translation of) the provided VA to a PA and then uses that translated PA to perform a memory read. Similarly, in order to write to memory the device must also first translate the provided VA to a PA and then use that translated PA to write to memory.

VA can include any untranslated address including Virtual Address, Guest Physical Address, Input Output Virtual Address, etc. PASID should be understood to potentially be a part of the VA when the term VA is used in this document. PA translation can include a PA translation of a requested VA, but can also include permissions (fulfilled by ATPT208). Stored in the TPB (and when used, (single-entry) cache) are not only the VA and PA, but also the permissions that were returned along with the PA. Similarly, the TPB receives permissions along with the PA translation.

FIG. 3is a schematic diagram300of a device302that includes a translation prefetch buffer304in accordance with embodiments of the present disclosure. Within the device302, the reading, processing, and writing of data can be performed by a processing engine306and the management of translations as being done by the translation prefetch buffer (TPB)304. Processing engine306can include hardware and/or software elements to allow the device302to perform jobs on behalf of the host system, such as streaming workloads that use memory transactions using the TPB304. The processing engine306can be logic circuitry within a device that works on a job request and coordinates sending translation requests, data read requests, data write requests, and any other work associated with a job request.

In a streaming workload, job requests contain the Virtual Addresses. Upon receiving a job request the device can determine or otherwise identify the addresses that need to be translated. With streaming workloads, the sequence of virtual addresses identified in the job request is typically sequential and can be extrapolated deterministically. Streaming workloads typically have large amounts of sequential data that are moved and the data streaming workloads read or write does not typically rely on branching or looping. Even with branching or looping, processing engines can still use the TPB to reuse the same translation explicitly multiple times simply by not explicitly evicting a translation until all deterministic uses of that translation have finished. The TPB on its own gives up opportunistic address-based reuse. However, this is mitigated for streaming workloads by the addition of a Single Entry Cache particularly when using large pages.

Determining VAs in advance (allowing deeper pipelining or prefetching) and assuming that PAs will typically not be reused or are sequential (allowing explicit eviction policy) allows for the prefetching of PAs from a set of VAs. The TPB304can store and provide a mapping of PAs and VAs with an index in the TPB304.

The processing engine306can send VA(s) to the TPB304early on in a previous pipelined translation stage312. The TPB304sends an ATS translation request that includes the VA(s) to an address translation agent (such as address translation agent206shown inFIG. 2). Translation agent206can be logic circuitry and/or software to perform address translations. After some amount of latency, the TPB304receives an ATS translation response that includes PA(s), which the TPB304stores internally (e.g., using an indexed random access memory305). The TPB304provides an index (Idx) to the processing engine306that is a direct pointer to the translated PA that the processing engine306is interested in using. When the processing engine306wants to do a memory read314, the processing engine306can use the supplied Idx to receive a PA from the TPB304that the processing engine306can then use to perform a memory read. Similarly for a write stage316, with an Idx, the processing engine306can receive a PA from the TPB304and use the PA to perform a memory write.

A memory controller320implemented in hardware, software, or a combination of hardware and software, can perform various tasks, such as populating the memory element305with translations of virtual addresses to physical addresses, parsing the memory element305for indexed translations of virtual addresses to physical addresses, returning indexes to the processing engine306, and requesting address translations from connected address translation services logic, such as translation agents.

FIG. 4Ais a schematic diagram of an example indexed random access memory400for translation prefetching in accordance with embodiments of the present disclosure. The indexed random access memory400can include entries for an index that directly points to a VA entry404and a PA entry406(e.g., a VA-PA mapping). The indexed random access memory400implementation uses a random access memory structure, employing an index to retrieve a PA. This allows the TPB to reduce complexity. The TPB implementation is able to use an efficient register file or SRAM for storage. This allows the TPB to have reduced area costs per entry.

The index-based implementation employed by the TPB does not require VA comparators and can reliably and immediately retrieve the translation at the requested index.

With the TPB's index-based approach, processing engines only need to store the index returned by the TPB in the initial translation stage. This index is smaller (approximately 8 bits depending on size of TPB) than a full VA (PASID+address) and reduces the area cost for engines.

The TPB does explicit eviction management. When an index is returned to the translation stage, the index will be available for use later by the read or write stages. Once the translation has been used for its one-time purpose, the entry is explicitly evicted, clearing that RAM slot for reuse by a new translation. This means that there is no unpredictability in terms of whether a translation will be evicted right before it is about to be used, and this means more reliable device performance.

FIG. 4Bis a schematic diagram of an example translation prefetch buffer (TPB)450that includes a single-entry cache452illustrating a cache hit in accordance with embodiments of the present disclosure. If a particular processing engine is doing a long sequential stream of e.g., 4 KB VA reads and the latest translation was e.g., a 2 MB PA, then that latest 2 MB PA translation can get stored in the single filter entry associated with that engine's data reads and will intercept and mask all future matching 4 KB VAs that the processing engine uses to perform memory transactions. Matching 4 KB VAs will hit the cache and will not generate new ATS requests (shown inFIG. 4B), while non-matching 4 KB VAs will miss the cache and will generate new ATS requests (shown inFIG. 4C). Both hit and miss translation requests will update the VA stored in the cache, but the cached PA is valid if the latest ATS response matches the latest cached VA after applying bit masking according to the translation's page size (e.g., 20 bits for 2 MB). This is likely to occur when sequential accesses are made within a large page.

The processing engine can make a translation request by providing a VA to the TPB450. The TPB450can first check the single-entry cache452to determine if the VA-PA translation is already in the single-entry cache452. If there is a cache hit, the TPB450can populate the indexed random access memory400with the VA-PA translation, and can provide a corresponding index to the processing engine for later use.

Although illustrated as a single-entry cache inFIGS. 4A-B, the cache used can be any type of a cache memory or fast memory element.

FIG. 4Cis a schematic diagram of an example translation prefetch buffer450that includes a single-entry cache illustrating a cache miss in accordance with embodiments of the present disclosure. For a cache miss, the VA is indexed into the TPB and an index associated with the VA is provided to the processing engine. The TPB450can perform an ATS request for translating the received VA into PA. The TPB450can then receive the translations from the ATS to populate the indexed random access memory400. Upon receiving an index from the processing engine, the TPB450can provide the corresponding PA.

FIG. 5Ais a swim lane diagram500for performing a translation prefetch using a translation prefetch buffer in accordance with embodiments of the present disclosure. During a translation stage, the processing engine of a device can initiate translation services to populate a TPB indexed random access memory. The processing engine can receive a job request (502). The processing engine can send VA(s) to a memory controller fthe TPB (504). The TPB can allocate a memory element location in RAM for the VA, and can identify an index for the memory element location (506). The TPB can send the index to the processing engine (508).

The TPB can transmit the VA(s) to the translation agent for PA translations (510). The translation agent can perform the translation(s) and provide the PA translation to the TPB (512). The TPB can store the PA translation in the memory element location allocated for the corresponding VA in an indexed random access memory (514). The PA translation is stored in the memory element location entry previously allocated for that translation request. That previously allocated entry's location is the index that was sent to the processing engine.

To execute a memory transaction, the processing engine can send the indexes for memory transactions associated with the streaming workload transactions to the TPB for address translation (516). The TPB can return the corresponding PAs to the processing engine (518). The device can then perform the memory transactions to satisfy the job request using the PAs received from the TPB (520). Memory transactions can include reads or writes to system memory, device memory, shared memory, external memory, network memory, hard drive, etc.

FIG. 5Bis a process flow diagram550for performing a translation prefetch using a translation prefetch buffer that includes cache (such as a single-entry cache) in accordance with embodiments of the present disclosure. At some point during a job request execution, the memory controller can have populated the (single-entry) cache with a virtual memory address and a physical memory address translation. The translation prefetch buffer (TPB) can receive a translation request that includes an indication of one or more VAs (552). The TPB can first check the (single-entry) cache for a corresponding PA using the VA received (554). If the VA an PA are present in the (single-entry) cache, the TPB can use the cache entry to populate the indexed random access memory (556). The TPB can then provide the corresponding index to the processing engine (558).

If the VA received is not present in the single-entry cache (cache miss), then the TPB can allocate a memory element location in the TPB for the VA and for a corresponding PA translation (564). The TPB can send an index corresponding to the memory element location to the processing engine (566). The TPB send the VA to a translation agent and receive a corresponding PA translation from the translation agent (568). The TPB can use the received PA from the translation agent to populate the memory element location (570), the memory element location corresponding to the VA and the index.

The TPB can receive an index from the processing engine in response to a need by the processing engine for memory transactions (560). The TPB can send the processing engine a PA corresponding to the index (562).

Invalidation flows are described by the PCIe ATS specification as a mechanism for the system to clear specific sets of translations from device ATCs. A typical use for an invalidation flow would be to make sure that any translations associated with a particular PASID have been cleared from the system and the PASID can be utilized for a newly spawned process. When an invalidation request is sent to a device, it must clear its ATC of all translations that match the provided PASID and address range. Before returning the invalidation completion upstream, the device must also make sure that all previous usages of the invalidated translations are ordered ahead of the invalidation completion so that the system can rely on not seeing any usage of stale invalidated translations.

In a standard caching ATC implementation, there is no way to know if there are any memory access transactions that are in flight that are using an address in the ATC that must be invalidated. Thus, the device must take a conservative approach and wait for all in-flight execution that may be using a translation to drain. This includes waiting for all pending reads to finish and all pending writes to flush regardless of whether they were using the translations being invalidated. In the translation prefetch buffer (TPB) implementation described herein, there is explicit eviction of translations as soon as they are done being used so the device is less likely to get translations matching requesting invalidations in the first place. Even when translations do match an invalidation request, the device will evict that translation as soon as any usage of that translation is finished as part of its normal operation, thus allowing the invalidation to finish. In this case, the invalidation does not have to wait for unaffected execution, reads, or writes to finish.

One interconnect fabric architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices. PCI Express is a high performance, general purpose I/O interconnect defined for a wide variety of future computing and communication platforms. Some PCI attributes, such as its usage model, load-store architecture, and software interfaces, have been maintained through its revisions, whereas previous parallel bus implementations have been replaced by a highly scalable, fully serial interface. The more recent versions of PCI Express take advantage of advances in point-to-point interconnects, Switch-based technology, and packetized protocol to deliver new levels of performance and features. Power Management, Quality Of Service (QoS), Hot-Plug/Hot-Swap support, Data Integrity, and Error Handling are among some of the advanced features supported by PCI Express.

Referring toFIG. 6, an embodiment of a fabric composed of point-to-point Links that interconnect a set of components is illustrated. System600includes processor605and system memory610coupled to controller hub615. Processor605includes any processing element, such as a microprocessor, a host processor, an embedded processor, a co-processor, or other processor. Processor605is coupled to controller hub615through front-side bus (FSB)606. In one embodiment, FSB606is a serial point-to-point interconnect as described below. In another embodiment, link606includes a serial, differential interconnect architecture that is compliant with different interconnect standard.

System memory610includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system600. System memory610is coupled to controller hub615through memory interface616. Examples of a memory interface include a double-data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

In one embodiment, controller hub615is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnection hierarchy. Examples of controller hub615include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH) a southbridge, and a root port controller/hub. Often the term chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include the MCH integrated with processor605, while controller615is to communicate with I/O devices, in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported through root complex615.

Here, controller hub615is coupled to switch/bridge620through serial link619. Input/output modules617and621, which may also be referred to as interfaces/ports617and621, include/implement a layered protocol stack to provide communication between controller hub615and switch620. In one embodiment, multiple devices are capable of being coupled to switch620.

Switch/bridge620routes packets/messages from device625upstream, i.e. up a hierarchy towards a root complex, to controller hub615and downstream, i.e. down a hierarchy away from a root port controller, from processor605or system memory610to device625. Switch620, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Device625includes any internal or external device or component to be coupled to an electronic system, such as an I/O device, a Network Interface Controller (NIC), an add-in card, an audio processor, a network processor, a hard-drive, a storage device, a CD/DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, and other input/output devices. Often in the PCIe vernacular, such as device, is referred to as an endpoint. Although not specifically shown, device625may include a PCIe to PCI/PCI-X bridge to support legacy or other version PCI devices. Endpoint devices in PCIe are often classified as legacy, PCIe, or root complex integrated endpoints.

Graphics accelerator630is also coupled to controller hub615through serial link632. In one embodiment, graphics accelerator630is coupled to an MCH, which is coupled to an ICH. Switch620, and accordingly I/O device625, is then coupled to the ICH. I/O modules631and618are also to implement a layered protocol stack to communicate between graphics accelerator630and controller hub615. Similar to the MCH discussion above, a graphics controller or the graphics accelerator630itself may be integrated in processor605.

Turning toFIG. 7an embodiment of a layered protocol stack is illustrated. Layered protocol stack700includes any form of a layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or other layered stack. Although the discussion immediately below in reference toFIGS. 6-9are in relation to a PCIe stack, the same concepts may be applied to other interconnect stacks. In one embodiment, protocol stack700is a PCIe protocol stack including transaction layer705, link layer710, and physical layer720. An interface, such as interfaces617,618,621,622,626, and631inFIG. 1, may be represented as communication protocol stack700. Representation as a communication protocol stack may also be referred to as a module or interface implementing/including a protocol stack.

PCI Express uses packets to communicate information between components. Packets are formed in the Transaction Layer705and Data Link Layer710to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side the reverse process occurs and packets get transformed from their Physical Layer720representation to the Data Link Layer710representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer705of the receiving device.

Transaction Layer

In one embodiment, transaction layer705is to provide an interface between a device's processing core and the interconnect architecture, such as data link layer710and physical layer720. In this regard, a primary responsibility of the transaction layer705is the assembly and disassembly of packets (i.e., transaction layer packets, or TLPs). The translation layer705typically manages credit-base flow control for TLPs. PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response.

In addition PCIe utilizes credit-based flow control. In this scheme, a device advertises an initial amount of credit for each of the receive buffers in Transaction Layer705. An external device at the opposite end of the link, such as controller hub115inFIG. 1, counts the number of credits consumed by each TLP. A transaction may be transmitted if the transaction does not exceed a credit limit. Upon receiving a response an amount of credit is restored. An advantage of a credit scheme is that the latency of credit return does not affect performance, provided that the credit limit is not encountered.

In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as 64-bit address. Configuration space transactions are used to access configuration space of the PCIe devices. Transactions to the configuration space include read requests and write requests. Message space transactions (or, simply messages) are defined to support in-band communication between PCIe agents.

Therefore, in one embodiment, transaction layer705assembles packet header/payload706. Format for current packet headers/payloads may be found in the PCIe specification at the PCIe specification website.

Quickly referring toFIG. 8, an embodiment of a PCIe transaction descriptor is illustrated. In one embodiment, transaction descriptor800is a mechanism for carrying transaction information. In this regard, transaction descriptor800supports identification of transactions in a system. Other potential uses include tracking modifications of default transaction ordering and association of transaction with channels.

Transaction descriptor800includes global identifier field802, attributes field804, and channel identifier field806. In the illustrated example, global identifier field802is depicted comprising local transaction identifier field808and source identifier field810. In one embodiment, global transaction identifier802is unique for all outstanding requests.

According to one implementation, local transaction identifier field808is a field generated by a requesting agent, and it is unique for all outstanding requests that require a completion for that requesting agent. Furthermore, in this example, source identifier810uniquely identifies the requestor agent within a PCIe hierarchy. Accordingly, together with source ID810, local transaction identifier808field provides global identification of a transaction within a hierarchy domain.

Attributes field804specifies characteristics and relationships of the transaction. In this regard, attributes field804is potentially used to provide additional information that allows modification of the default handling of transactions. In one embodiment, attributes field804includes priority field812, reserved field814, ordering field816, and no-snoop field818. Here, priority sub-field812may be modified by an initiator to assign a priority to the transaction. Reserved attribute field814is left reserved for future, or vendor-defined usage. Possible usage models using priority or security attributes may be implemented using the reserved attribute field.

In this example, ordering attribute field816is used to supply optional information conveying the type of ordering that may modify default ordering rules. According to one example implementation, an ordering attribute of “0” denotes default ordering rules are to apply, wherein an ordering attribute of “1” denotes relaxed ordering, wherein writes can pass writes in the same direction, and read completions can pass writes in the same direction. Snoop attribute field818is utilized to determine if transactions are snooped. As shown, channel ID Field806identifies a channel that a transaction is associated with.

Link Layer

Link layer710, also referred to as data link layer710, acts as an intermediate stage between transaction layer705and the physical layer720. In one embodiment, a responsibility of the data link layer710is providing a reliable mechanism for exchanging Transaction Layer Packets (TLPs) between two components a link. One side of the Data Link Layer710accepts TLPs assembled by the Transaction Layer705, applies packet sequence identifier711, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 712, and submits the modified TLPs to the Physical Layer720for transmission across a physical to an external device.

Physical Layer

In one embodiment, physical layer720includes logical sub block721and electrical sub-block722to physically transmit a packet to an external device. Here, logical sub-block721is responsible for the “digital” functions of Physical Layer721. In this regard, the logical sub-block includes a transmit section to prepare outgoing information for transmission by physical sub-block722, and a receiver section to identify and prepare received information before passing it to the Link Layer710.

Physical block722includes a transmitter and a receiver. The transmitter is supplied by logical sub-block721with symbols, which the transmitter serializes and transmits onto to an external device. The receiver is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is de-serialized and supplied to logical sub-block721. In one embodiment, an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received. Here, special symbols are used to frame a packet with frames723. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

As stated above, although transaction layer705, link layer710, and physical layer720are discussed in reference to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not so limited. In fact, any layered protocol may be included/implemented. As an example, an port/interface that is represented as a layered protocol includes: (1) a first layer to assemble packets, i.e. a transaction layer; a second layer to sequence packets, i.e. a link layer; and a third layer to transmit the packets, i.e. a physical layer. As a specific example, a common standard interface (CSI) layered protocol is utilized.

Referring next toFIG. 9, an embodiment of a PCIe serial point to point fabric is illustrated. Although an embodiment of a PCIe serial point-to-point link is illustrated, a serial point-to-point link is not so limited, as it includes any transmission path for transmitting serial data. In the embodiment shown, a basic PCIe link includes two, low-voltage, differentially driven signal pairs: a transmit pair906/911and a receive pair912/907. Accordingly, device905includes transmission logic906to transmit data to device910and receiving logic907to receive data from device910. In other words, two transmitting paths, i.e. paths916and917, and two receiving paths, i.e. paths918and919, are included in a PCIe link.

A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or other communication path. A connection between two devices, such as device905and device910, is referred to as a link, such as link415. A link may support one lane—each lane representing a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

A differential pair refers to two transmission paths, such as lines416and417, to transmit differential signals. As an example, when line416toggles from a low voltage level to a high voltage level, i.e. a rising edge, line417drives from a high logic level to a low logic level, i.e. a falling edge. Differential signals potentially demonstrate better electrical characteristics, such as better signal integrity, i.e. cross-coupling, voltage overshoot/undershoot, ringing, etc. This allows for better timing window, which enables faster transmission frequencies.

Note that the apparatus, methods, and systems described above may be implemented in any electronic device or system as aforementioned. As specific illustrations, the figures below provide exemplary systems for utilizing the disclosure as described herein. As the systems below are described in more detail, a number of different interconnects are disclosed, described, and revisited from the discussion above. And as is readily apparent, the advances described above may be applied to any of those interconnects, fabrics, or architectures.

Turning toFIG. 10, a block diagram of an exemplary computer system formed with a processor that includes execution units to execute an instruction, where one or more of the interconnects implement one or more features in accordance with one embodiment of the present disclosure is illustrated. System1000includes a component, such as a processor1002to employ execution units including logic to perform algorithms for process data, in accordance with the present disclosure, such as in the embodiment described herein. System1000is representative of processing systems based on the PENTIUM III™, PENTIUM 4™, Xeon™, Itanium, XScale™ and/or StrongARM™ microprocessors available from Intel Corporation of Santa Clara, Calif., although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and the like) may also be used. In one embodiment, sample system1000executes a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used. Thus, embodiments of the present disclosure are not limited to any specific combination of hardware circuitry and software.

Embodiments are not limited to computer systems. Alternative embodiments of the present disclosure can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications can include a micro controller, a digital signal processor (DSP), system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform one or more instructions in accordance with at least one embodiment.

In this illustrated embodiment, processor1002includes one or more execution units1008to implement an algorithm that is to perform at least one instruction. One embodiment may be described in the context of a single processor desktop or server system, but alternative embodiments may be included in a multiprocessor system. System1000is an example of a ‘hub’ system architecture. The computer system1000includes a processor1002to process data signals. The processor1002, as one illustrative example, includes a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. The processor1002is coupled to a processor bus1010that transmits data signals between the processor1002and other components in the system1000. The elements of system1000(e.g. graphics accelerator1012, memory controller hub1016, memory1020, I/O controller hub1024, wireless transceiver1026, Flash BIOS1028, Network controller1034, Audio controller1036, Serial expansion port1038, I/O controller1040, etc.) perform their conventional functions that are well known to those familiar with the art.

In one embodiment, the processor1002includes a Level 1 (L1) internal cache memory1004. Depending on the architecture, the processor1002may have a single internal cache or multiple levels of internal caches. Other embodiments include a combination of both internal and external caches depending on the particular implementation and needs. Register file1006is to store different types of data in various registers including integer registers, floating point registers, vector registers, banked registers, shadow registers, checkpoint registers, status registers, and instruction pointer register.

Execution unit1008, including logic to perform integer and floating point operations, also resides in the processor1002. The processor1002, in one embodiment, includes a microcode (ucode) ROM to store microcode, which when executed, is to perform algorithms for certain macroinstructions or handle complex scenarios. Here, microcode is potentially updateable to handle logic bugs/fixes for processor1002. For one embodiment, execution unit1008includes logic to handle a packed instruction set1009. By including the packed instruction set1009in the instruction set of a general-purpose processor1002, along with associated circuitry to execute the instructions, the operations used by many multimedia applications may be performed using packed data in a general-purpose processor1002. Thus, many multimedia applications are accelerated and executed more efficiently by using the full width of a processor's data bus for performing operations on packed data. This potentially eliminates the need to transfer smaller units of data across the processor's data bus to perform one or more operations, one data element at a time.

Alternate embodiments of an execution unit1008may also be used in micro controllers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System1000includes a memory1020. Memory1020includes a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, or other memory device. Memory1020stores instructions and/or data represented by data signals that are to be executed by the processor1002.

Note that any of the aforementioned features or aspects of the disclosure may be utilized on one or more interconnect illustrated inFIG. 10. For example, an on-die interconnect (ODI), which is not shown, for coupling internal units of processor1002implements one or more aspects of the disclosure described above. Or the disclosure is associated with a processor bus1010(e.g. Intel Quick Path Interconnect (QPI) or other known high performance computing interconnect), a high bandwidth memory path1018to memory1020, a point-to-point link to graphics accelerator1012(e.g. a Peripheral Component Interconnect express (PCIe) compliant fabric), a controller hub interconnect1022, an I/O or other interconnect (e.g. USB, PCI, PCIe) for coupling the other illustrated components. Some examples of such components include the audio controller1036, firmware hub (flash BIOS)1028, wireless transceiver1026, data storage1024, legacy I/O controller1010containing user input and keyboard interfaces1042, a serial expansion port1038such as Universal Serial Bus (USB), and a network controller1034. The data storage device1024can comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

Referring now toFIG. 11, shown is a block diagram of a second system1100in accordance with an embodiment of the present disclosure. As shown inFIG. 11, multiprocessor system1100is a point-to-point interconnect system, and includes a first processor1170and a second processor1180coupled via a point-to-point interconnect1150. Each of processors1170and1180may be some version of a processor. In one embodiment,1152and1154are part of a serial, point-to-point coherent interconnect fabric, such as Intel's Quick Path Interconnect (QPI) architecture. As a result, the disclosure may be implemented within the QPI architecture.

While shown with only two processors1170,1180, it is to be understood that the scope of the present disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

Processors1170and1180are shown including integrated memory controller units1172and1182, respectively. Processor1170also includes as part of its bus controller units point-to-point (P-P) interfaces1176and1178; similarly, second processor1180includes P-P interfaces1186and1188. Processors1170,1180may exchange information via a point-to-point (P-P) interface1150using P-P interface circuits1178,1188. As shown inFIG. 11, IMCs1172and1182couple the processors to respective memories, namely a memory1132and a memory1134, which may be portions of main memory locally attached to the respective processors.

Processors1170,1180each exchange information with a chipset1190via individual P-P interfaces1152,1154using point to point interface circuits1176,1194,1186,1198. Chipset1190also exchanges information with a high-performance graphics circuit1138via an interface circuit1192along a high-performance graphics interconnect1139.

Chipset1190may be coupled to a first bus1116via an interface1196. In one embodiment, first bus1116may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

As shown inFIG. 11, various I/O devices1114are coupled to first bus1116, along with a bus bridge1118which couples first bus1116to a second bus1120. In one embodiment, second bus1120includes a low pin count (LPC) bus. Various devices are coupled to second bus1120including, for example, a keyboard and/or mouse1122, communication devices1127and a storage unit1128such as a disk drive or other mass storage device which often includes instructions/code and data1130, in one embodiment. Further, an audio I/O1124is shown coupled to second bus1120. Note that other architectures are possible, where the included components and interconnect architectures vary. For example, instead of the point-to-point architecture ofFIG. 11, a system may implement a multi-drop bus or other such architecture.

Using the various inertial and environmental sensors present in a platform, many different use cases may be realized. These use cases enable advanced computing operations including perceptual computing and also allow for enhancements with regard to power management/battery life, security, and system responsiveness.

For example with regard to power management/battery life issues, based at least on part on information from an ambient light sensor, the ambient light conditions in a location of the platform are determined and intensity of the display controlled accordingly. Thus, power consumed in operating the display is reduced in certain light conditions.

As to security operations, based on context information obtained from the sensors such as location information, it may be determined whether a user is allowed to access certain secure documents. For example, a user may be permitted to access such documents at a work place or a home location. However, the user is prevented from accessing such documents when the platform is present at a public location. This determination, in one embodiment, is based on location information, e.g., determined via a GPS sensor or camera recognition of landmarks. Other security operations may include providing for pairing of devices within a close range of each other, e.g., a portable platform as described herein and a user's desktop computer, mobile telephone or so forth. Certain sharing, in some implementations, are realized via near field communication when these devices are so paired. However, when the devices exceed a certain range, such sharing may be disabled. Furthermore, when pairing a platform as described herein and a smartphone, an alarm may be configured to be triggered when the devices move more than a predetermined distance from each other, when in a public location. In contrast, when these paired devices are in a safe location, e.g., a work place or home location, the devices may exceed this predetermined limit without triggering such alarm.

Responsiveness may also be enhanced using the sensor information. For example, even when a platform is in a low power state, the sensors may still be enabled to run at a relatively low frequency. Accordingly, any changes in a location of the platform, e.g., as determined by inertial sensors, GPS sensor, or so forth is determined. If no such changes have been registered, a faster connection to a previous wireless hub such as a Wi-Fi™ access point or similar wireless enabler occurs, as there is no need to scan for available wireless network resources in this case. Thus, a greater level of responsiveness when waking from a low power state is achieved.

It is to be understood that many other use cases may be enabled using sensor information obtained via the integrated sensors within a platform as described herein, and the above examples are only for purposes of illustration. Using a system as described herein, a perceptual computing system may allow for the addition of alternative input modalities, including gesture recognition, and enable the system to sense user operations and intent.

In some embodiments one or more infrared or other heat sensing elements, or any other element for sensing the presence or movement of a user may be present. Such sensing elements may include multiple different elements working together, working in sequence, or both. For example, sensing elements include elements that provide initial sensing, such as light or sound projection, followed by sensing for gesture detection by, for example, an ultrasonic time of flight camera or a patterned light camera.

Also in some embodiments, the system includes a light generator to produce an illuminated line. In some embodiments, this line provides a visual cue regarding a virtual boundary, namely an imaginary or virtual location in space, where action of the user to pass or break through the virtual boundary or plane is interpreted as an intent to engage with the computing system. In some embodiments, the illuminated line may change colors as the computing system transitions into different states with regard to the user. The illuminated line may be used to provide a visual cue for the user of a virtual boundary in space, and may be used by the system to determine transitions in state of the computer with regard to the user, including determining when the user wishes to engage with the computer.

In some embodiments, the computer senses user position and operates to interpret the movement of a hand of the user through the virtual boundary as a gesture indicating an intention of the user to engage with the computer. In some embodiments, upon the user passing through the virtual line or plane the light generated by the light generator may change, thereby providing visual feedback to the user that the user has entered an area for providing gestures to provide input to the computer.

Display screens may provide visual indications of transitions of state of the computing system with regard to a user. In some embodiments, a first screen is provided in a first state in which the presence of a user is sensed by the system, such as through use of one or more of the sensing elements.

In some implementations, the system acts to sense user identity, such as by facial recognition. Here, transition to a second screen may be provided in a second state, in which the computing system has recognized the user identity, where this second the screen provides visual feedback to the user that the user has transitioned into a new state. Transition to a third screen may occur in a third state in which the user has confirmed recognition of the user.

In some embodiments, the computing system may use a transition mechanism to determine a location of a virtual boundary for a user, where the location of the virtual boundary may vary with user and context. The computing system may generate a light, such as an illuminated line, to indicate the virtual boundary for engaging with the system. In some embodiments, the computing system may be in a waiting state, and the light may be produced in a first color. The computing system may detect whether the user has reached past the virtual boundary, such as by sensing the presence and movement of the user using sensing elements.

In some embodiments, if the user has been detected as having crossed the virtual boundary (such as the hands of the user being closer to the computing system than the virtual boundary line), the computing system may transition to a state for receiving gesture inputs from the user, where a mechanism to indicate the transition may include the light indicating the virtual boundary changing to a second color.

In some embodiments, the computing system may then determine whether gesture movement is detected. If gesture movement is detected, the computing system may proceed with a gesture recognition process, which may include the use of data from a gesture data library, which may reside in memory in the computing device or may be otherwise accessed by the computing device.

If a gesture of the user is recognized, the computing system may perform a function in response to the input, and return to receive additional gestures if the user is within the virtual boundary. In some embodiments, if the gesture is not recognized, the computing system may transition into an error state, where a mechanism to indicate the error state may include the light indicating the virtual boundary changing to a third color, with the system returning to receive additional gestures if the user is within the virtual boundary for engaging with the computing system.

As mentioned above, in other embodiments the system can be configured as a convertible tablet system that can be used in at least two different modes, a tablet mode and a notebook mode. The convertible system may have two panels, namely a display panel and a base panel such that in the tablet mode the two panels are disposed in a stack on top of one another. In the tablet mode, the display panel faces outwardly and may provide touch screen functionality as found in conventional tablets. In the notebook mode, the two panels may be arranged in an open clamshell configuration.

In various embodiments, the accelerometer may be a 3-axis accelerometer having data rates of at least 50 Hz. A gyroscope may also be included, which can be a 3-axis gyroscope. In addition, an e-compass/magnetometer may be present. Also, one or more proximity sensors may be provided (e.g., for lid open to sense when a person is in proximity (or not) to the system and adjust power/performance to extend battery life). For some OS's Sensor Fusion capability including the accelerometer, gyroscope, and compass may provide enhanced features. In addition, via a sensor hub having a real-time clock (RTC), a wake from sensors mechanism may be realized to receive sensor input when a remainder of the system is in a low power state.

In some embodiments, an internal lid/display open switch or sensor to indicate when the lid is closed/open, and can be used to place the system into Connected Standby or automatically wake from Connected Standby state. Other system sensors can include ACPI sensors for internal processor, memory, and skin temperature monitoring to enable changes to processor and system operating states based on sensed parameters.

In an embodiment, the OS may be a Microsoft® Windows® 8 OS that implements Connected Standby (also referred to herein as Win8 CS). Windows 8 Connected Standby or another OS having a similar state can provide, via a platform as described herein, very low ultra idle power to enable applications to remain connected, e.g., to a cloud-based location, at very low power consumption. The platform can supports 3 power states, namely screen on (normal); Connected Standby (as a default “off” state); and shutdown (zero watts of power consumption). Thus in the Connected Standby state, the platform is logically on (at minimal power levels) even though the screen is off. In such a platform, power management can be made to be transparent to applications and maintain constant connectivity, in part due to offload technology to enable the lowest powered component to perform an operation.

Referring now toFIG. 12, a block diagram of components present in a computer system in accordance with an embodiment of the present disclosure is illustrated. As shown inFIG. 12, system1200includes any combination of components. These components may be implemented as ICs, portions thereof, discrete electronic devices, or other modules, logic, hardware, software, firmware, or a combination thereof adapted in a computer system, or as components otherwise incorporated within a chassis of the computer system. Note also that the block diagram ofFIG. 12is intended to show a high level view of many components of the computer system. However, it is to be understood that some of the components shown may be omitted, additional components may be present, and different arrangement of the components shown may occur in other implementations. As a result, the disclosure described above may be implemented in any portion of one or more of the interconnects illustrated or described below.

As seen inFIG. 12, a processor1210, in one embodiment, includes a microprocessor, multi-core processor, multithreaded processor, an ultra low voltage processor, an embedded processor, or other known processing element. In the illustrated implementation, processor1210acts as a main processing unit and central hub for communication with many of the various components of the system1200. As one example, processor1200is implemented as a system on a chip (SoC). As a specific illustrative example, processor1210includes an Intel® Architecture Core™-based processor such as an i3, i5, i7 or another such processor available from Intel Corporation, Santa Clara, Calif. However, understand that other low power processors such as available from Advanced Micro Devices, Inc. (AMD) of Sunnyvale, Calif., a MIPS-based design from MIPS Technologies, Inc. of Sunnyvale, Calif., an ARM-based design licensed from ARM Holdings, Ltd. or customer thereof, or their licensees or adopters may instead be present in other embodiments such as an Apple A5/A6 processor, a Qualcomm Snapdragon processor, or TI OMAP processor. Note that many of the customer versions of such processors are modified and varied; however, they may support or recognize a specific instructions set that performs defined algorithms as set forth by the processor licensor. Here, the microarchitectural implementation may vary, but the architectural function of the processor is usually consistent. Certain details regarding the architecture and operation of processor1210in one implementation will be discussed further below to provide an illustrative example.

Processor1210, in one embodiment, communicates with a system memory1215. As an illustrative example, which in an embodiment can be implemented via multiple memory devices to provide for a given amount of system memory. As examples, the memory can be in accordance with a Joint Electron Devices Engineering Council (JEDEC) low power double data rate (LPDDR)-based design such as the current LPDDR2 standard according to JEDEC JESD 209-2E (published April 2009), or a next generation LPDDR standard to be referred to as LPDDR3 or LPDDR4 that will offer extensions to LPDDR2 to increase bandwidth. In various implementations the individual memory devices may be of different package types such as single die package (SDP), dual die package (DDP) or quad die package (67P). These devices, in some embodiments, are directly soldered onto a motherboard to provide a lower profile solution, while in other embodiments the devices are configured as one or more memory modules that in turn couple to the motherboard by a given connector. And of course, other memory implementations are possible such as other types of memory modules, e.g., dual inline memory modules (DIMMs) of different varieties including but not limited to microDIMMs, MiniDIMMs. In a particular illustrative embodiment, memory is sized between 2 GB and 16 GB, and may be configured as a DDR3LM package or an LPDDR2 or LPDDR3 memory that is soldered onto a motherboard via a ball grid array (BGA).

To provide for persistent storage of information such as data, applications, one or more operating systems and so forth, a mass storage1220may also couple to processor1210. In various embodiments, to enable a thinner and lighter system design as well as to improve system responsiveness, this mass storage may be implemented via a SSD. However in other embodiments, the mass storage may primarily be implemented using a hard disk drive (HDD) with a smaller amount of SSD storage to act as a SSD cache to enable non-volatile storage of context state and other such information during power down events so that a fast power up can occur on re-initiation of system activities. Also shown inFIG. 12, a flash device1222may be coupled to processor1210, e.g., via a serial peripheral interface (SPI). This flash device may provide for non-volatile storage of system software, including a basic input/output software (BIOS) as well as other firmware of the system.

In various embodiments, mass storage of the system is implemented by a SSD alone or as a disk, optical or other drive with an SSD cache. In some embodiments, the mass storage is implemented as a SSD or as a HDD along with a restore (RST) cache module. In various implementations, the HDD provides for storage of between 320 GB-4 terabytes (TB) and upward while the RST cache is implemented with a SSD having a capacity of 24 GB-256 GB. Note that such SSD cache may be configured as a single level cache (SLC) or multi-level cache (MLC) option to provide an appropriate level of responsiveness. In a SSD-only option, the module may be accommodated in various locations such as in a mSATA or NGFF slot. As an example, an SSD has a capacity ranging from 120 GB-1 TB.

Various input/output (IO) devices may be present within system1200. Specifically shown in the embodiment ofFIG. 12is a display1224which may be a high definition LCD or LED panel configured within a lid portion of the chassis. This display panel may also provide for a touch screen1225, e.g., adapted externally over the display panel such that via a user's interaction with this touch screen, user inputs can be provided to the system to enable desired operations, e.g., with regard to the display of information, accessing of information and so forth. In one embodiment, display1224may be coupled to processor1210via a display interconnect that can be implemented as a high performance graphics interconnect. Touch screen1225may be coupled to processor1210via another interconnect, which in an embodiment can be an I2C interconnect. As further shown inFIG. 12, in addition to touch screen1225, user input by way of touch can also occur via a touch pad1230which may be configured within the chassis and may also be coupled to the same I2C interconnect as touch screen1225.

The display panel may operate in multiple modes. In a first mode, the display panel can be arranged in a transparent state in which the display panel is transparent to visible light. In various embodiments, the majority of the display panel may be a display except for a bezel around the periphery. When the system is operated in a notebook mode and the display panel is operated in a transparent state, a user may view information that is presented on the display panel while also being able to view objects behind the display. In addition, information displayed on the display panel may be viewed by a user positioned behind the display. Or the operating state of the display panel can be an opaque state in which visible light does not transmit through the display panel.

In a tablet mode the system is folded shut such that the back display surface of the display panel comes to rest in a position such that it faces outwardly towards a user, when the bottom surface of the base panel is rested on a surface or held by the user. In the tablet mode of operation, the back display surface performs the role of a display and user interface, as this surface may have touch screen functionality and may perform other known functions of a conventional touch screen device, such as a tablet device. To this end, the display panel may include a transparency-adjusting layer that is disposed between a touch screen layer and a front display surface. In some embodiments the transparency-adjusting layer may be an electrochromic layer (EC), a LCD layer, or a combination of EC and LCD layers.

In various embodiments, the display can be of different sizes, e.g., an 11.6″ or a 13.3″ screen, and may have a 16:9 aspect ratio, and at least 300 nits brightness. Also the display may be of full high definition (HD) resolution (at least 1920×1080p), be compatible with an embedded display port (eDP), and be a low power panel with panel self refresh.

As to touch screen capabilities, the system may provide for a display multi-touch panel that is multi-touch capacitive and being at least 5 finger capable. And in some embodiments, the display may be 10 finger capable. In one embodiment, the touch screen is accommodated within a damage and scratch-resistant glass and coating (e.g., Gorilla Glass™ or Gorilla Glass 2™) for low friction to reduce “finger burn” and avoid “finger skipping”. To provide for an enhanced touch experience and responsiveness, the touch panel, in some implementations, has multi-touch functionality, such as less than 2 frames (30 Hz) per static view during pinch zoom, and single-touch functionality of less than 1 cm per frame (30 Hz) with 200 ms (lag on finger to pointer). The display, in some implementations, supports edge-to-edge glass with a minimal screen bezel that is also flush with the panel surface, and limited IO interference when using multi-touch.

For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to processor1210in different manners. Certain inertial and environmental sensors may couple to processor1210through a sensor hub1240, e.g., via an I2C interconnect. In the embodiment shown inFIG. 12, these sensors may include an accelerometer1241, an ambient light sensor (ALS)1242, a compass1243and a gyroscope1244. Other environmental sensors may include one or more thermal sensors1246which in some embodiments couple to processor1210via a system management bus (SMBus) bus.

Using the various inertial and environmental sensors present in a platform, many different use cases may be realized. These use cases enable advanced computing operations including perceptual computing and also allow for enhancements with regard to power management/battery life, security, and system responsiveness.

For example with regard to power management/battery life issues, based at least on part on information from an ambient light sensor, the ambient light conditions in a location of the platform are determined and intensity of the display controlled accordingly. Thus, power consumed in operating the display is reduced in certain light conditions.

As to security operations, based on context information obtained from the sensors such as location information, it may be determined whether a user is allowed to access certain secure documents. For example, a user may be permitted to access such documents at a work place or a home location. However, the user is prevented from accessing such documents when the platform is present at a public location. This determination, in one embodiment, is based on location information, e.g., determined via a GPS sensor or camera recognition of landmarks. Other security operations may include providing for pairing of devices within a close range of each other, e.g., a portable platform as described herein and a user's desktop computer, mobile telephone or so forth. Certain sharing, in some implementations, are realized via near field communication when these devices are so paired. However, when the devices exceed a certain range, such sharing may be disabled. Furthermore, when pairing a platform as described herein and a smartphone, an alarm may be configured to be triggered when the devices move more than a predetermined distance from each other, when in a public location. In contrast, when these paired devices are in a safe location, e.g., a work place or home location, the devices may exceed this predetermined limit without triggering such alarm.

Responsiveness may also be enhanced using the sensor information. For example, even when a platform is in a low power state, the sensors may still be enabled to run at a relatively low frequency. Accordingly, any changes in a location of the platform, e.g., as determined by inertial sensors, GPS sensor, or so forth is determined. If no such changes have been registered, a faster connection to a previous wireless hub such as a Wi-Fi™ access point or similar wireless enabler occurs, as there is no need to scan for available wireless network resources in this case. Thus, a greater level of responsiveness when waking from a low power state is achieved.

It is to be understood that many other use cases may be enabled using sensor information obtained via the integrated sensors within a platform as described herein, and the above examples are only for purposes of illustration. Using a system as described herein, a perceptual computing system may allow for the addition of alternative input modalities, including gesture recognition, and enable the system to sense user operations and intent.

In some embodiments one or more infrared or other heat sensing elements, or any other element for sensing the presence or movement of a user may be present. Such sensing elements may include multiple different elements working together, working in sequence, or both. For example, sensing elements include elements that provide initial sensing, such as light or sound projection, followed by sensing for gesture detection by, for example, an ultrasonic time of flight camera or a patterned light camera.

Also in some embodiments, the system includes a light generator to produce an illuminated line. In some embodiments, this line provides a visual cue regarding a virtual boundary, namely an imaginary or virtual location in space, where action of the user to pass or break through the virtual boundary or plane is interpreted as an intent to engage with the computing system. In some embodiments, the illuminated line may change colors as the computing system transitions into different states with regard to the user. The illuminated line may be used to provide a visual cue for the user of a virtual boundary in space, and may be used by the system to determine transitions in state of the computer with regard to the user, including determining when the user wishes to engage with the computer.

In some embodiments, the computer senses user position and operates to interpret the movement of a hand of the user through the virtual boundary as a gesture indicating an intention of the user to engage with the computer. In some embodiments, upon the user passing through the virtual line or plane the light generated by the light generator may change, thereby providing visual feedback to the user that the user has entered an area for providing gestures to provide input to the computer.

Display screens may provide visual indications of transitions of state of the computing system with regard to a user. In some embodiments, a first screen is provided in a first state in which the presence of a user is sensed by the system, such as through use of one or more of the sensing elements.

In some implementations, the system acts to sense user identity, such as by facial recognition. Here, transition to a second screen may be provided in a second state, in which the computing system has recognized the user identity, where this second the screen provides visual feedback to the user that the user has transitioned into a new state. Transition to a third screen may occur in a third state in which the user has confirmed recognition of the user.

In some embodiments, the computing system may use a transition mechanism to determine a location of a virtual boundary for a user, where the location of the virtual boundary may vary with user and context. The computing system may generate a light, such as an illuminated line, to indicate the virtual boundary for engaging with the system. In some embodiments, the computing system may be in a waiting state, and the light may be produced in a first color. The computing system may detect whether the user has reached past the virtual boundary, such as by sensing the presence and movement of the user using sensing elements.

In some embodiments, if the user has been detected as having crossed the virtual boundary (such as the hands of the user being closer to the computing system than the virtual boundary line), the computing system may transition to a state for receiving gesture inputs from the user, where a mechanism to indicate the transition may include the light indicating the virtual boundary changing to a second color.

In some embodiments, the computing system may then determine whether gesture movement is detected. If gesture movement is detected, the computing system may proceed with a gesture recognition process, which may include the use of data from a gesture data library, which may reside in memory in the computing device or may be otherwise accessed by the computing device.

If a gesture of the user is recognized, the computing system may perform a function in response to the input, and return to receive additional gestures if the user is within the virtual boundary. In some embodiments, if the gesture is not recognized, the computing system may transition into an error state, where a mechanism to indicate the error state may include the light indicating the virtual boundary changing to a third color, with the system returning to receive additional gestures if the user is within the virtual boundary for engaging with the computing system.

As mentioned above, in other embodiments the system can be configured as a convertible tablet system that can be used in at least two different modes, a tablet mode and a notebook mode. The convertible system may have two panels, namely a display panel and a base panel such that in the tablet mode the two panels are disposed in a stack on top of one another. In the tablet mode, the display panel faces outwardly and may provide touch screen functionality as found in conventional tablets. In the notebook mode, the two panels may be arranged in an open clamshell configuration.

In various embodiments, the accelerometer may be a 3-axis accelerometer having data rates of at least 50 Hz. A gyroscope may also be included, which can be a 3-axis gyroscope. In addition, an e-compass/magnetometer may be present. Also, one or more proximity sensors may be provided (e.g., for lid open to sense when a person is in proximity (or not) to the system and adjust power/performance to extend battery life). For some OS's Sensor Fusion capability including the accelerometer, gyroscope, and compass may provide enhanced features. In addition, via a sensor hub having a real-time clock (RTC), a wake from sensors mechanism may be realized to receive sensor input when a remainder of the system is in a low power state.

In some embodiments, an internal lid/display open switch or sensor to indicate when the lid is closed/open, and can be used to place the system into Connected Standby or automatically wake from Connected Standby state. Other system sensors can include ACPI sensors for internal processor, memory, and skin temperature monitoring to enable changes to processor and system operating states based on sensed parameters.

In an embodiment, the OS may be a Microsoft® Windows® 8 OS that implements Connected Standby (also referred to herein as Win8 CS). Windows 8 Connected Standby or another OS having a similar state can provide, via a platform as described herein, very low ultra idle power to enable applications to remain connected, e.g., to a cloud-based location, at very low power consumption. The platform can supports 3 power states, namely screen on (normal); Connected Standby (as a default “off” state); and shutdown (zero watts of power consumption). Thus in the Connected Standby state, the platform is logically on (at minimal power levels) even though the screen is off. In such a platform, power management can be made to be transparent to applications and maintain constant connectivity, in part due to offload technology to enable the lowest powered component to perform an operation.

Also seen inFIG. 12, various peripheral devices may couple to processor1210via a low pin count (LPC) interconnect. In the embodiment shown, various components can be coupled through an embedded controller1235. Such components can include a keyboard1236(e.g., coupled via a PS2 interface), a fan1237, and a thermal sensor1239. In some embodiments, touch pad1230may also couple to EC1235via a PS2 interface. In addition, a security processor such as a trusted platform module (TPM)1238in accordance with the Trusted Computing Group (TCG) TPM Specification Version 1.2, dated Oct. 2, 2003, may also couple to processor1210via this LPC interconnect. However, understand the scope of the present disclosure is not limited in this regard and secure processing and storage of secure information may be in another protected location such as a static random access memory (SRAM) in a security coprocessor, or as encrypted data blobs that are only decrypted when protected by a secure enclave (SE) processor mode.

In a particular implementation, peripheral ports may include a high definition media interface (HDMI) connector (which can be of different form factors such as full size, mini or micro); one or more USB ports, such as full-size external ports in accordance with the Universal Serial Bus Revision 3.0 Specification (November 2008), with at least one powered for charging of USB devices (such as smartphones) when the system is in Connected Standby state and is plugged into AC wall power. In addition, one or more Thunderbolt™ ports can be provided. Other ports may include an externally accessible card reader such as a full size SD-XC card reader and/or a SIM card reader for WWAN (e.g., an 8 pin card reader). For audio, a 3.5 mm jack with stereo sound and microphone capability (e.g., combination functionality) can be present, with support for jack detection (e.g., headphone only support using microphone in the lid or headphone with microphone in cable). In some embodiments, this jack can be re-taskable between stereo headphone and stereo microphone input. Also, a power jack can be provided for coupling to an AC brick.

System1200can communicate with external devices in a variety of manners, including wirelessly. In the embodiment shown inFIG. 12, various wireless modules, each of which can correspond to a radio configured for a particular wireless communication protocol, are present. One manner for wireless communication in a short range such as a near field may be via a near field communication (NFC) unit1245which may communicate, in one embodiment with processor1210via an SMBus. Note that via this NFC unit1245, devices in close proximity to each other can communicate. For example, a user can enable system1200to communicate with another (e.g.,) portable device such as a smartphone of the user via adapting the two devices together in close relation and enabling transfer of information such as identification information payment information, data such as image data or so forth. Wireless power transfer may also be performed using a NFC system.

Using the NFC unit described herein, users can bump devices side-to-side and place devices side-by-side for near field coupling functions (such as near field communication and wireless power transfer (WPT)) by leveraging the coupling between coils of one or more of such devices. More specifically, embodiments provide devices with strategically shaped, and placed, ferrite materials, to provide for better coupling of the coils. Each coil has an inductance associated with it, which can be chosen in conjunction with the resistive, capacitive, and other features of the system to enable a common resonant frequency for the system.

As further seen inFIG. 12, additional wireless units can include other short range wireless engines including a WLAN unit1250and a Bluetooth unit1252. Using WLAN unit1250, Wi-Fi™ communications in accordance with a given Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard can be realized, while via Bluetooth unit1252, short range communications via a Bluetooth protocol can occur. These units may communicate with processor1210via, e.g., a USB link or a universal asynchronous receiver transmitter (UART) link. Or these units may couple to processor1210via an interconnect according to a Peripheral Component Interconnect Express™ (PCIe™) protocol, e.g., in accordance with the PCI Express™ Specification Base Specification version 3.0 (published Jan. 17, 2007), or another such protocol such as a serial data input/output (SDIO) standard. Of course, the actual physical connection between these peripheral devices, which may be configured on one or more add-in cards, can be by way of the NGFF connectors adapted to a motherboard.

In addition, wireless wide area communications, e.g., according to a cellular or other wireless wide area protocol, can occur via a WWAN unit1256which in turn may couple to a subscriber identity module (SIM)1257. In addition, to enable receipt and use of location information, a GPS module1255may also be present. Note that in the embodiment shown inFIG. 12, WWAN unit1256and an integrated capture device such as a camera module1254may communicate via a given USB protocol such as a USB 2.0 or 3.0 link, or a UART or I2C protocol. Again the actual physical connection of these units can be via adaptation of a NGFF add-in card to an NGFF connector configured on the motherboard.

In a particular embodiment, wireless functionality can be provided modularly, e.g., with a WiFi™ 802.11ac solution (e.g., add-in card that is backward compatible with IEEE 802.11abgn) with support for Windows 8 CS. This card can be configured in an internal slot (e.g., via an NGFF adapter). An additional module may provide for Bluetooth capability (e.g., Bluetooth 4.0 with backwards compatibility) as well as Intel® Wireless Display functionality. In addition NFC support may be provided via a separate device or multi-function device, and can be positioned as an example, in a front right portion of the chassis for easy access. A still additional module may be a WWAN device that can provide support for 3G/4G/LTE and GPS. This module can be implemented in an internal (e.g., NGFF) slot. Integrated antenna support can be provided for WiFi™, Bluetooth, WWAN, NFC and GPS, enabling seamless transition from WiFi™ to WWAN radios, wireless gigabit (WiGig) in accordance with the Wireless Gigabit Specification (July 2010), and vice versa.

As described above, an integrated camera can be incorporated in the lid. As one example, this camera can be a high resolution camera, e.g., having a resolution of at least 2.0 megapixels (MP) and extending to 6.0 MP and beyond.

To provide for audio inputs and outputs, an audio processor can be implemented via a digital signal processor (DSP)1260, which may couple to processor1210via a high definition audio (HDA) link. Similarly, DSP1260may communicate with an integrated coder/decoder (CODEC) and amplifier1262that in turn may couple to output speakers1263which may be implemented within the chassis. Similarly, amplifier and CODEC1262can be coupled to receive audio inputs from a microphone1265which in an embodiment can be implemented via dual array microphones (such as a digital microphone array) to provide for high quality audio inputs to enable voice-activated control of various operations within the system. Note also that audio outputs can be provided from amplifier/CODEC1262to a headphone jack1264. Although shown with these particular components in the embodiment ofFIG. 12, understand the scope of the present disclosure is not limited in this regard.

In a particular embodiment, the digital audio codec and amplifier are capable of driving the stereo headphone jack, stereo microphone jack, an internal microphone array and stereo speakers. In different implementations, the codec can be integrated into an audio DSP or coupled via an HD audio path to a peripheral controller hub (PCH). In some implementations, in addition to integrated stereo speakers, one or more bass speakers can be provided, and the speaker solution can support DTS audio.

In some embodiments, processor1210may be powered by an external voltage regulator (VR) and multiple internal voltage regulators that are integrated inside the processor die, referred to as fully integrated voltage regulators (FIVRs). The use of multiple FIVRs in the processor enables the grouping of components into separate power planes, such that power is regulated and supplied by the FIVR to only those components in the group. During power management, a given power plane of one FIVR may be powered down or off when the processor is placed into a certain low power state, while another power plane of another FIVR remains active, or fully powered.

In one embodiment, a sustain power plane can be used during some deep sleep states to power on the I/O pins for several I/O signals, such as the interface between the processor and a PCH, the interface with the external VR and the interface with EC1235. This sustain power plane also powers an on-die voltage regulator that supports the on-board SRAM or other cache memory in which the processor context is stored during the sleep state. The sustain power plane is also used to power on the processor's wakeup logic that monitors and processes the various wakeup source signals.

During power management, while other power planes are powered down or off when the processor enters certain deep sleep states, the sustain power plane remains powered on to support the above-referenced components. However, this can lead to unnecessary power consumption or dissipation when those components are not needed. To this end, embodiments may provide a connected standby sleep state to maintain processor context using a dedicated power plane. In one embodiment, the connected standby sleep state facilitates processor wakeup using resources of a PCH which itself may be present in a package with the processor. In one embodiment, the connected standby sleep state facilitates sustaining processor architectural functions in the PCH until processor wakeup, this enabling turning off all of the unnecessary processor components that were previously left powered on during deep sleep states, including turning off all of the clocks. In one embodiment, the PCH contains a time stamp counter (TSC) and connected standby logic for controlling the system during the connected standby state. The integrated voltage regulator for the sustain power plane may reside on the PCH as well.

In an embodiment, during the connected standby state, an integrated voltage regulator may function as a dedicated power plane that remains powered on to support the dedicated cache memory in which the processor context is stored such as critical state variables when the processor enters the deep sleep states and connected standby state. This critical state may include state variables associated with the architectural, micro-architectural, debug state, and/or similar state variables associated with the processor.

The wakeup source signals from EC1235may be sent to the PCH instead of the processor during the connected standby state so that the PCH can manage the wakeup processing instead of the processor. In addition, the TSC is maintained in the PCH to facilitate sustaining processor architectural functions. Although shown with these particular components in the embodiment ofFIG. 12, understand the scope of the present disclosure is not limited in this regard.

Power control in the processor can lead to enhanced power savings. For example, power can be dynamically allocate between cores, individual cores can change frequency/voltage, and multiple deep low power states can be provided to enable very low power consumption. In addition, dynamic control of the cores or independent core portions can provide for reduced power consumption by powering off components when they are not being used.

Some implementations may provide a specific power management IC (PMIC) to control platform power. Using this solution, a system may see very low (e.g., less than 5%) battery degradation over an extended duration (e.g., 16 hours) when in a given standby state, such as when in a Win8 Connected Standby state. In a Win8 idle state a battery life exceeding, e.g., 9 hours may be realized (e.g., at 150 nits). As to video playback, a long battery life can be realized, e.g., full HD video playback can occur for a minimum of 6 hours. A platform in one implementation may have an energy capacity of, e.g., 35 watt hours (Whr) for a Win8 CS using an SSD and (e.g.,) 40-44 Whr for Win8 CS using an HDD with a RST cache configuration.

A particular implementation may provide support for 15 W nominal CPU thermal design power (TDP), with a configurable CPU TDP of up to approximately 25 W TDP design point. The platform may include minimal vents owing to the thermal features described above. In addition, the platform is pillow-friendly (in that no hot air is blowing at the user). Different maximum temperature points can be realized depending on the chassis material. In one implementation of a plastic chassis (at least having to lid or base portion of plastic), the maximum operating temperature can be 52 degrees Celsius (C). And for an implementation of a metal chassis, the maximum operating temperature can be 46° C.

In different implementations, a security module such as a TPM can be integrated into a processor or can be a discrete device such as a TPM 2.0 device. With an integrated security module, also referred to as Platform Trust Technology (PTT), BIOS/firmware can be enabled to expose certain hardware features for certain security features, including secure instructions, secure boot, Intel® Anti-Theft Technology, Intel® Identity Protection Technology, Intel® Trusted Execution Technology (TXT), and Intel® Manageability Engine Technology along with secure user interfaces such as a secure keyboard and display.

In the claims, and elsewhere in this document, an order of operations is not implied. The systems, methods, and apparatuses can include one or a combination of the following examples:

Example 1 is an apparatus comprising a processing engine implemented at least partially in hardware, the processing engine to process memory transactions; a memory element to index virtual address and physical address translations; and a memory controller logic implemented at least partially in hardware. The memory controller logic is to receive an index from the processing engine, the index corresponding to a physical address and a virtual address; identify a physical address based on the received index; and provide the physical address to the processing engine.

Example 2 may include the subject matter of example 1, wherein the memory element comprises one of a translation prefetch buffer or a prefetching address translation cache.

Example 3 may include the subject matter of any of examples 1-2, wherein the memory element comprises an indexed random access memory.

Example 4 may include the subject matter of any of examples 1-3, wherein the apparatus comprises one of an accelerator, disk controller, network controller, or graphics controller.

Example 5 may include the subject matter of any of examples 1-4, the memory controller logic to receive a virtual address from the processing engine; send an index to the processing engine, the index corresponding to a memory element location allocated for the virtual address and physical address translation; request translation of the virtual address from an address translation service; receive a physical address corresponding to the virtual address; and populate the memory element location with the physical address translation.

Example 6 may include the subject matter of any of examples 1-5, further comprising a cache, the memory controller logic to populate a cache with a virtual address and physical address translation; receive a virtual address from the processing engine; determine that the virtual address is present in the cache with a corresponding physical address; populate the memory element with the virtual address and the physical address into the memory element; and provide an index to the processing engine corresponding to the virtual address and the physical address.

Example 7 may include the subject matter of any of examples 1-5, further comprising a cache, the memory controller logic to receive a virtual address from the processing engine; determine that the virtual address is not present in the cache; populate a memory element with the virtual address; send an index corresponding to the memory element to the processing engine; transmit the virtual address to an address translation service; receive a physical address from the address translation service corresponding to the virtual address; and populate the memory element with the physical address translation.

Example 8 may include the subject matter of any of examples 1-7, the memory controller logic to evict the virtual address and physical address corresponding to the index sent from the processing engine

Example 9 may include the subject matter of any of examples 1-8, the processing engine provide a set of virtual addresses to the memory controller logic based on receiving a job request, the job request comprising a workload that relies on deterministic memory address location accesses.

Example 10 may include the subject matter of any of examples 1-9, the processing engine to use the physical address for memory transactions.

Example 11 is a computer implemented method comprising receiving, from a processing engine, a pointer value identifying a memory element location containing a mapping of a virtual memory address to a physical memory address; identifying a physical memory address based on the pointer value; and providing the processing engine the physical memory address.

Example 12 may include the subject matter of example 11, further comprising receiving a virtual memory address from the processing engine; sending a pointer value to the processing engine, the pointer value corresponding to a memory element allocated for the virtual memory address and physical memory address translation; requesting translation of the virtual memory address from an address translation service; receiving a physical memory address corresponding to the virtual memory address; and populating the memory element with the physical memory address.

Example 13 may include the subject matter of any of examples 11-12, further comprising populating a cache with a virtual address and physical address translation; receiving a virtual memory address from the processing engine; determining that the virtual memory address is present in a cache with a corresponding physical memory address; populating a memory element with the virtual memory address and the physical memory address into the memory element; and providing a pointer value to the processing engine corresponding to the virtual memory address and the physical memory address.

Example 14 may include the subject matter of any of examples 11-12, further comprising receiving a virtual memory address from the processing engine; determining that the virtual memory address is not present in a cache; sending a pointer value to the processing engine, the pointer value corresponding to a memory element allocated for the virtual memory address and physical memory address translation; transmitting the virtual memory address to an address translation service; receiving a physical memory address from the address translation service corresponding to the virtual memory address; and populating the memory element with the physical memory address.

Example 15 may include the subject matter of any of examples 11-14, further comprising performing memory transactions using the physical memory address.

Example 16 is a non-transitory computer-readable medium having program instructions stored therein, wherein the program instructions are executable by a computer system to perform operations comprising receiving, from a processing engine, a pointer value identifying a memory element location containing a mapping of a virtual memory address to a physical memory address; identifying a physical memory address based on the pointer value; and providing the processing engine the physical memory address.

Example 17 may include the subject matter of example 16, the operations further comprising receiving a virtual memory address from the processing engine; sending a pointer value to the processing engine corresponding to a memory element allocated for the virtual memory address and physical memory address translation; requesting translation of the virtual memory address from an address translation service; receiving a physical memory address corresponding to the virtual memory address; and populating the memory element with the physical memory address.

Example 18 may include the subject matter of any of examples 16-17, the operations further comprising populating a cache with a virtual address and physical address translation; receiving a virtual memory address from the processing engine; determining that the virtual memory address is present in a cache with a corresponding physical memory address; populating a memory element with the virtual memory address and the physical memory address into the memory element; and providing a pointer value to the processing engine corresponding to the virtual memory address and the physical memory address.

Example 19 may include the subject matter of any of examples 16-17, the operations further comprising receiving a virtual memory address from the processing engine; determining that the virtual memory address is not present in a cache; sending a pointer value index corresponding to a memory element allocated for the virtual memory address and physical memory address translation to the processing engine; transmitting the virtual memory address to an address translation service; receiving a physical memory address from the address translation service corresponding to the virtual memory address; and populating the memory element with the physical memory address.

Example 20 may include the subject matter of any of examples 16-19, the operations further comprising performing memory transactions using the physical memory address.

Example 21 is a system comprising a host processor comprising one or more core processing units; a system memory; a device in communication with the host processor and the system memory, the device comprising a processing engine implemented at least partially in hardware, the processing engine to process memory transactions; a memory element to index physical address and virtual address translations; and a memory controller logic implemented at least partially in hardware, the memory controller logic to receive an index from the processing engine, the index corresponding to a physical address and a virtual address; identify a physical address based on the received index; and provide the physical address to the processing engine.

Example 22 may include the subject matter of example 21, further comprising a translation engine implemented at least partially in hardware; and a memory address translation table; the translation engine to receive a virtual address from the device; identify a physical address from the virtual address; and provide the physical address to the device.

Example 23 may include the subject matter of example 21, the memory controller logic to receive a virtual address from the processing engine; send an index corresponding to the virtual address and physical address to the processing engine; request translation of the virtual address from the translation engine; receive a physical from the translation engine corresponding to the virtual address; and populate the memory element with the virtual address and the physical address.

Example 24 may include the subject matter of any of examples 21-23, wherein the device comprises a cache, the memory controller logic to populate the memory element with a physical address corresponding to the virtual address from the cache.

Example 25 may include the subject matter of any of examples 21-24, wherein the device is one of a root complex integrated endpoint or a device connected to the host processor across a multi-lane link based on the Peripheral Component Interconnect Express protocol.

Example 26 may include the subject matter of any of examples 21-25, wherein the device comprises one of an accelerator, disk controller, network controller, or graphics controller.

Example 27 is a device comprising means for receiving, from a processing engine, a pointer value identifying a memory element location containing a mapping of a virtual memory address to a physical memory address; means for identifying a physical memory address based on the pointer value; and means for providing the processing engine the physical memory address.

Example 28 may include the subject matter of example 27, further comprising means for receiving a virtual memory address from the processing engine; means for sending a pointer value corresponding to the virtual memory address and physical memory address to the processing engine; means for requesting translation of the virtual memory address from an address translation service; means for receiving a physical memory address corresponding to the virtual memory address; and means for populating a memory element with the virtual memory address and the physical memory address.

Example 29 may include the subject matter of any of examples 27-28, further comprising means for receiving a virtual memory address from the processing engine; means for determining that the virtual memory address is present in a cache with a corresponding physical memory address; means for populating a memory element with the virtual memory address and the physical memory address into the memory element; and means for providing a pointer value to the processing engine corresponding to the virtual memory address and the physical memory address.

Example 30 may include the subject matter of any of examples 27-28, further comprising means for receiving a virtual memory address from the processing engine; means for determining that the virtual memory address is not present in a cache; means for transmitting the virtual memory address to an address translation service; receiving a physical memory address from the address translation service corresponding to the virtual memory address; means for populating a memory element with the virtual memory address and the physical memory address; and means for sending an index corresponding to the virtual memory address and physical memory address to the processing engine.

Example 31 may include the subject matter of any of examples 27-30, further comprising means for performing memory transactions using the physical memory address.