DEVICE AND METHOD FOR BULK INDUCED PRE-EMPHASIS TECHNIQUE IN CURRENT MODE TRANSMITTER FOR HIGH SPEED LINKS

An integrated circuit includes a current mode transmitter having a first driver and a second driver. The first driver receives a single bit data stream. The second driver receives a delayed data stream corresponding to the single bit data stream delayed by a clock cycle. The current mode transmitter has a transition detector that generates a bulk modulation signal having a first value when the single bit data stream is the same as the delayed data stream and having a second value when the single bit data stream is different from the delayed data stream. The transition detector supplies the bulk modulation signal to the bulk terminals of driver switches of the first and second drivers.

BACKGROUND

Technical Field

The present disclosure is related to integrated circuits, and more particularly, to integrated circuits that include current mode transmitters.

Description of the Related Art

Integrated circuits are utilized for a large variety of applications. In many applications, it is desirable to transmit data from one device to another. Integrated circuits can be utilized in various ways to transmit and receive data. Integrated circuits may transmit data to other integrated circuits on a same printed circuit board or in other configurations or systems.

One method of data transmission is current mode transmission. In current mode transmission, data is transmitted by modulating the current flowing in a transmission medium. This can be a highly effective way to transmit signals. However, one drawback to current mode transmission schemes is that it can be difficult to maintain low power consumption while ensuring high readability of signals.

All of the subject matter discussed in the Background section is not necessarily prior art and should not be assumed to be prior art merely as a result of its discussion in the Background section. Along these lines, any recognition of problems in the prior art discussed in the Background section or associated with such subject matter should not be treated as prior art unless expressly stated to be prior art. Instead, the discussion of any subject matter in the Background section should be treated as part of the inventor's approach to the particular problem, which, in and of itself, may also be inventive.

BRIEF SUMMARY

Embodiments of the present disclosure provide an integrated circuit that includes a current mode transmitter that is able to transmit data effectively and efficiently. The current mode transmitter includes a bulk modulation circuit that generates a bulk modulation signal for selectively biasing a bulk terminal of a driver switch. The value of the bulk modulation signal depends on whether or not a current data value is different from a most recent previous data value. By selectively biasing the bulk terminal of the driver switch in this manner, the current mode transmitter is able to efficiently and effectively transmit data.

In one embodiment, the current mode transmitter transmits data values by modulating transmission currents on two transmission lines. More particularly, data values are indicated by the voltage difference between the two data lines. An increase in the voltage difference amplitude indicates that the current data value is different from the previous data value. If the voltage difference decreases or stays the same, then the current data value is the same as the previous data value.

In one embodiment, the bulk modulation circuit generates the bulk modulation signal with a high value (e.g. VDD) when the current data value is different than the previous data value. Applying the high value of the bulk modulation signal to the bulk terminal of the driver switch reduces the threshold voltage of the driver switch, thereby enabling a higher current amplitude (and greater voltage difference) than if the threshold voltage was higher. The bulk modulation circuit generates the bulk modulation signal with a low value (e.g. ground) when the current data value is the same as the most recent value. Thus, when the voltage difference is to increase, the bulk terminal of the driver switch receives a high voltage. When the voltage difference is to decrease or stay the same, the bulk terminal of the driver switch receives a low voltage. This results in improved efficiency in current mode data transmission.

In one embodiment, the driver switch includes a plurality of transistors coupled in parallel. The driver switch may receive the bulk modulation signal on the bulk terminals of each of the plurality of transistors. In one embodiment, the driver switch receives the bulk modulation signal on the bulk terminals of only some of the transistors, while the other transistors always received ground under bulk terminals.

In one embodiment, an integrated circuit includes an input data source and a current mode transmitter coupled to the input data source. The current mode transmitter includes a primary driver including a first driver switch, a secondary driver including a second driver switch, a delay circuit coupled between the input data source and the secondary driver, and a transition detector. The transition detector includes a first input coupled to the input of the primary driver and the secondary driver, a second input coupled to the input of the secondary driver, and an output coupled to a bulk terminal of the first driver switch and to a bulk terminal of the second driver switch.

In one embodiment, an integrated circuit includes a first driver of a current mode transmitter. The first driver includes an input and a first driver switch having a bulk terminal. The integrated circuit includes a transition detector having an input coupled to an input of the first driver circuit and an output coupled to the bulk terminal of the first driver switch.

In one embodiment, a method includes receiving a first stream of data values at a first driver of a current mode transmitter and receiving the first stream of data values at a transition detector. The method includes generating, with the transition detector, a bulk modulation voltage based on the first stream of data values and supplying the bulk modulation voltage to a bulk terminal of a first driver switch of the first driver.

In one embodiment, a method includes receiving a first stream of data values at a first driver of a current mode transmitter, generating a second stream of data values by delaying the first stream of data values by one or more cycles of a clock signal, receiving the second stream of data values at a second driver of the current mode transmitter, and receiving the first and second streams of data values at a transition detector. The method includes generating, with the transition detector, a bulk modulation voltage having an amplitude based on the first and second data streams, supplying the bulk modulation voltage to a bulk terminal of a first driver switch of the first driver, supplying the bulk modulation voltage to a bulk terminal of a second driver switch of the second driver, and generating a current mode data stream based on outputs of the first and second drivers.

DETAILED DESCRIPTION

FIG.1Ais a schematic diagram of a system100, according to one embodiment. The system100includes a first integrated circuit102and a second integrated circuit103. The first and second integrated circuits102and103are coupled together in a current mode transmission scheme. As will be set forth in more detail below, the components of the integrated circuit102cooperate to provide a bulk modulation signal that increases the efficiency and readability of the current mode transmitter104.

The integrated circuits102and103are coupled together by a transmission medium105. The transmission medium105can include structures, circuits, or components that enable the transmission of current mode data signals between the integrated circuit102and the integrated circuit103.

In one embodiment, the system100is implemented on a printed circuit board. In this case, the integrated circuits102and103are coupled to the printed circuit board. The transmission medium105can include conductive signal traces that communicatively couple the first integrated circuit102to the second integrated circuit103. The signal traces can include metal lines or other conductive structures. The transmission medium105can include other types of signal propagation structures without departing from the scope of the present disclosure.

The integrated circuit102includes a current mode transmitter104. The current mode transmitter104includes a first driver106and a second driver108. The first driver106may be termed a primary driver or a main driver. The second driver108may be termed a secondary driver or a delay driver.

The driver106includes a first output terminal coupled to a transmission line TXP. The driver106includes a second output terminal coupled to a second transmission line TXN. The driver108includes a first output terminal coupled to the transmission line TXP. The driver108includes a second output terminal coupled to the transmission line TXN. The transmission lines TXP and TXN are each coupled to a respective terminal110of the integrated circuit102. As will be set forth in more detail below, the drivers106and108drive currents through the transmission lines TXP and TXN. The data values may be read by the integrated circuit103as voltage differences between TXP and TXN based on the drive currents.

The integrated circuit102includes a data generator112. The data generator112generates a stream of data values. In particular, the data generator112generates a single bit stream of data values. The data generator112outputs the single bit stream of data values in accordance with a clock signal CLK. In one embodiment, the data generator112outputs a single-bit data value on each cycle of the clock signal CLK. The data generator112can represent any circuit, or combination of circuits within the integrated circuit102that may generate data values for current mode data transmission.

In one embodiment, the data generator112is a parallel in serial out (PISO) circuit. In this case, the data generator112may receive a plurality of data values in parallel in accordance with a second clock signal having a frequency lower than the first clock signal. The PISO serializes the plurality of data values into a single bit serial data stream. Because the first clock cycle CLK that controls the PISO has a frequency that is much faster than the frequency of the second clock signal, the PISO112is able to serialize the parallel data values into a single bit serial data stream. Other types of data generators112can be utilized without departing from the scope of the present disclosure.

The data generator112includes two data outputs. In practice, the two data outputs collectively provide the single bit data stream. The first data output of the data generator112may output the single bit data stream, while the second data output may output the logical complement of the single bit data stream. Accordingly, if the first data output has a logical high value, then the second data output has a logical low value. If the first data output has a logical low value, then the second data output has a logical high value.

In one embodiment, the data generator112outputs the single bit data stream in a voltage modulation scheme. In a voltage modulation scheme, a high voltage may represent a logical 1 while a low voltage may represent a logical 0, or vice versa. Other transmission schemes can be utilized for the data generator112without departing from the scope of the present disclosure.

In one embodiment, the clock signal CLK is a high-speed clock signal. The clock signal CLK may have a frequency between 100 MHz and 20 GHz. Other frequencies can be utilized for the clock signal CLK without departing from the scope of the present disclosure.

The current mode transmitter104includes a first predriver circuit114. The first predriver circuit receives the first and second data outputs from the data source112. In other words, the first predriver circuit114receives the single bit data stream from the data source112. It is possible that the data source112may output the serial data signal with a nonstandard voltage modulation. For example, the amplitude differences between high and low values in the data stream may be lower or higher than desired. The predriver circuit114may perform the function of receiving the data stream from the data source112in nonstandard amplitudes and outputting the data stream with desired amplitudes. For example, the predriver circuit114may ensure that logical high values of the data stream have an amplitude of VDD, while logical low values of the data stream have an amplitude of ground or 0 V.

The first predriver circuit114has a first output terminal that provides data values D+. The first predriver circuit114is a second output terminal that provides data values D−. In practice, D−may simply be the logical complement of D+. As described previously the data source112provides the first and second data output, with the second output being the logical complement of the first output. Similarly, the first predriver circuit114applies first and second data outputs, with D−being the logical complement of D+.

In one embodiment, the predriver circuit114includes a first plurality of buffer circuits coupled in series. The first plurality of buffer circuits receives the first output of the data source112and outputs the serial data stream D+. The predriver circuit114also includes a second plurality of buffer circuits coupled in series. The second plurality of buffer circuits receives the second output of the data source112and outputs the serial data stream D−. The first and second plurality of buffer circuits have the same number of buffer circuits. The predriver circuit114can have other components and configurations of components without departing from the scope of the present disclosure.

The first driver circuit106has a first input terminal that receives the data values D+from the predriver circuit114. The first driver circuit106has a second input terminal that receives the data values D−from the predriver circuit114. The first driver circuit106contributes data transmission currents onto the transmission lines TXP and TXN based on D+and D−. Further details regarding the function of the first driver106will be provided below.

The current mode transmitter104includes a first flip-flop118and a second flip-flop120. The first and second flip-flops118and120receive the clock signal CLK on the respective clock input terminals. The data terminal of the first flip-flop118is coupled to the first output of the data source112. The data terminal of the second flip-flop120is coupled to the second output of the data source112. The data output terminal of the first flip-flop118is coupled to a first input of the second predriver116. The data output terminal of the second flip-flop120is coupled to a second input of the second predriver116.

When the data source112outputs a new data value in accordance with a current cycle of the clock signal CLK, the data value is received substantially immediately by the first predriver114. However, the second predriver116does not receive the new data value substantially immediately. Instead, the second predriver116receives the data value with a delay relative to the first predriver circuit116. The delay of the second predriver116relative to the first predriver114is the period of a single cycle of the clock signal CLK. This is because when the flip-flops118and120receive the new data value (the new data value and the logical compliment, respectively) the flip-flops118and120do not output the new data value until the next rising edge (or falling edge, according to the configurations of the flip-flops118and120) of the clock signal CLK. The result is that the second predriver116is always one clock signal behind the first predriver114.

As an example, if the data source112outputs a series of N data values on N consecutive cycles of the clock signal CLK, the then the first predriver circuit114receives the first data value on the first clock cycle. The predriver circuit116does not receive a data value on the first clock cycle. The predriver circuit114receives the second data value on the second clock cycle. The predriver circuit116receives the first data value on the second clock cycle. The first predriver circuit114receives the third data value on the third clock cycle. The second predriver circuit116receives the second data value on the third clock cycle. This continues until the first predriver114receives the Nth data value on the Nth clock cycle and the second predriver114receives the Nth data value on clock cycle N+1. Accordingly, the inputs of the second predriver circuit116are delayed by a single clock cycle relative to the first predriver circuit114.

The second predriver circuit116can perform substantially the same function as the first predriver circuit114. In particular, the second predriver circuit116receives delay data values with possibly nonstandard amplitudes and outputs delayed data values D+dand D−d. The delayed data value D+dcorresponds to D+, but delayed by a single clock cycle. The delayed data value D−dcorresponds to D−, but delayed by a single clock cycle. The second predriver circuit116can have substantially the same structures or components as the first predriver circuit114. For example, the second pre-are circuit116can include first and second groups of serially coupled buffers, having the same numbers of buffers as the first and second groups of serially coupled buffers in the first predriver circuit114.

The second driver circuit108has a first input terminal that receives the delayed data values D+dfrom the predriver circuit116. The second driver circuit108has a second input terminal that receives the data values D−dfrom the predriver circuit116. The second driver circuit108contributes data transmission currents onto the transmission lines TXP and TXN based on D+dand D−d.

The first output of the second driver108is coupled to the transmission lines TXP. The second output of the second driver108is coupled to the transmission line TXN. Accordingly, the first output of the second driver108contributes current to the transmission line TXP. The second output of the second driver108contributes current to the transmission line TXN. Accordingly, the total current flowing in the transmission lines is based on the current supplied by both the first driver106and the second driver108.

The current mode transmitter104also includes resistors R1and R2. The resistor R1is coupled between TXP and VDD. The resistor R2is coupled between TXN and the VDD. The resistors R1and R2have a same value. In one embodiment, the resistors R1and R2each have a value of 50 ohms. The resistors R1and R2can have other values without departing from the scope of the present disclosure.

The second integrated circuit103includes resistors R3and R4. The resistor R3is coupled between VDD and TXP. The resistor R4is coupled between VDD and TXN. In one embodiment, the resistors R3and R4have the same values as resistors R1and R2. Accordingly, the resistors R1and R2and R3and R4are utilized for impedance matching between the integrated circuits102and103.

Prior to describing further details regarding the components of the current mode transmitter104, it is beneficial to describe current mode transmission signals in reference toFIG.1B.FIG.1Bis a graph150illustrating voltages on the transmission lines TXP and TXN. The voltage Vp is the voltage on the transmission line TXP. The voltage Vn is the voltage on the transmission line VXN. The voltages are based on how the drivers106and108drive currents through the resistors R1-R4. Accordingly, Vp can be given by the following relationship:

where Ixp is the sum of the currents flowing through R1and R3into the drivers106and108, and Rp is the parallel resistance of R1and R3(or the parallel resistance between R2and R4). Ixp can have values of I1, I2, I1+I2, or 0, where I1is the current driven by the driver106and I2is the current driven by the driver108. Vn can be given by the following relationship:

where Ixn is the sum of the currents flowing through R2and R4into the drivers106and108. In can have values of I1, I2, I1+I2, or 0.

FIG.1Billustrates a differential voltage VD corresponding to the amplitude of the voltage difference between TXP and TXN. Accordingly, VD is the amplitude of Vp-Vn. VD can have a low value of VD=Rp*(I1−I2). VD can have a high value of Rp*(I1+I2). As set forth in more detail below, both I1and I2have higher values in the high amplitude mode than in the low amplitude mode.

FIG.1Billustrates a plurality of unit intervals UI. Each unit interval (UI) corresponds to the period of one cycle of the clock CLK. A data value of either 0 or 1 is assigned to each UI. The data value assigned to the UI corresponds to the data value of the single bit serial data stream for that UI.

The data values are encoded as changes in the amplitude of VD, or as changes in the amplitude of the currents flowing in the transmission line. VD can have one of two values: a high value and a low value. If VD has a high value during a UI, then the data value during that UI is different from the data value during the preceding UI. If VD has the low value during a UI, then the data value during that UI is the same as during the previous UI.

With reference toFIG.1B, during the first UI, the single bit data stream has a data value of 0 and VD has a low value. During the second UI, the single bit data stream has a data value 1. This represents a change from the data value of the first UI. Accordingly, the amplitude of VD increases to the high value during the second UI. During the third UI, the data value of the single bit data stream is 1. Accordingly, the amplitude of VD decreases from the high value to the low value in the third UI, indicating that the data value in the third UI is the same as the data value in the second UI. The data value for the fourth UI is 0. This represents a change from the data value of the third UI. Accordingly, the amplitude of VD increases to the high value during the fourth UI. Accordingly, data is encoded in TXP and TXN based on whether or not the amplitude changes.

With reference again toFIG.1A, as described previously the first and second drivers106and108each have a respective driver switch. Each driver switch has a bulk terminal. This is shown in greater detail in relation toFIG.2. The threshold voltage of the driver switches is based, in part, on the voltage of the bulk terminals. For N type driver switches, a higher voltage on the bulk terminal results in a lower threshold voltage. A lower threshold voltage in turn results in higher currents for a given gate to source voltage. When it is desired to have a high value VD, it is beneficial to drive a higher current through the driver switches. Accordingly, the current mode transmitter103modulates the voltage of the bulk terminals of the driver switches of the drivers106and108. The modulation includes applying a high voltage, such as VDD, to the bulk terminals of the driver switches when a high value of VD is desired. The modulation includes applying a low voltage, such as ground, to the bulk terminals of the driver switches when a low value of VD is desired. This can result in greater differences in VD between high and low amplitudes, resulting in more reliable reading of data at the integrated circuit103.

The current mode transmitter104includes a transition detector122. The transition detector122generates a modulation voltage BM. The modulation voltage BM is supplied to the bulk terminals of the driver switches of the drivers106and108. The modulation voltage BM has a high value when D+and D+dhave different values. Because D+dis delayed from D+by a single clock cycle, or UI, different values of D+and D+dindicates changes in the value of the data stream between a most recent UI and the current UI. The transition detector may also be termed a bulk voltage modulation generator.

The transition detector122includes a first input coupled to the first output of the predriver114and the first input of the driver106. The transition detector122includes a second input coupled to the first output of the predriver116and the first input of the driver108. The transition detector122includes an output coupled to bulk terminals of the driver switches of the drivers106and108.

In one embodiment, the transition detector122detects transitions in the data values from one UI to the next, or from one clock cycle to the next. If there is a transition, i.e. if a current UI is different from the data value of the previous UI, then BM goes high. If the data value of the current UI is the same as the data value of the previous UI, then BM is low.

In one embodiment, the transition detector122is an XOR gate. The XOR gate has a first input coupled to the first output of the predriver114. The XOR gate has a second input coupled to the first output of the predriver116. The XOR gate has an output coupled to the bulk terminals of the driver switches of the driver circuits106and108. Other types of detection logic circuits or logic gates can be utilized for the transition detector122without departing from the scope of the present disclosure.

FIG.2is a schematic diagram of portions of the integrated circuit102, according to one embodiment.FIG.2illustrates the first driver106and the second driver108of the current mode transmitter104, as well as the transition detector122, ofFIG.1, according to one embodiment.

The driver106includes a driver switch T1, an NMOS transistor T3, and an NMOS transistor T4. The NMOS driver switch T1is an NMOS transistor. The source terminals of the transistors T3and T4are coupled to the driver switch of the transistor T1. The gate terminal of the transistor T3receives the data value D+. The gate terminal of the transistor P4receives the data value D−. The drain terminal of the transistor T3is coupled to the transmission line TXP. The drain terminal of the transistor T4is coupled to the transmission line TXN. The source terminal of the driver switch T1is coupled to ground. The gate terminal of the driver switch T1is coupled to the gate terminal of a current mirror transistor T7, as will be described in more detail below. The bulk terminal of the driver switch T1is coupled to the output of the transition detector122and receives the bulk modulation voltage BM.

The driver108includes a driver switch T2, an NMOS transistor T5, and an NMOS transistor T6. The NMOS driver switch T2is an NMOS transistor. The source terminals of the transistors T5and T6are coupled to the drain terminal of the driver switch T2. The gate terminal of the transistor T5receives the data value D−d. The gate terminal of the transistor T6receives the data value D+d. The drain terminal of the transistor T5is coupled to the transmission line TXP. The drain terminal of the transistor T6is coupled to the transmission line TXN. The source terminal of the driver switch T2is coupled to ground. The gate terminal of the driver switch T2is coupled to the gate terminal of a current mirror transistor T7, as will be described in more detail below. The bulk terminal of the driver switch T2is coupled to the output of the transition detector122and receives the bulk modulation voltage BM.

The NMOS transistor T7is coupled to the gate terminals of the drive switches T1and T2in a current mirror configuration. The drain terminal of the transistor T7is coupled to the output of a current source that provides a reference current Iref. The drain terminal of the transistor T7is coupled to the gate terminal of the transistor T7. The bulk terminal of the transistor T7is coupled to ground. The source terminal of the transistor T7is coupled to ground.

The current mirror configuration of the transistor T7causes the driver switch T1to drive a current I1. The current I1may be different from the current Iref based on the relative sizes of T1and T7. If T1is larger, i.e., has a higher effective width to length ratio than T7, then I1will be larger than Iref. Furthermore, as described previously, I1has a variable value based on the value of the bulk modulation signal BM. I1is higher when BM is high than when BM is low. Accordingly, I1has a high value when BM is high. I1has a low value when BM is low.

The current mirror configuration of the transistor T7causes the driver switch T2to drive a current I2. The current I2may be different from the current Iref based on the relative sizes of T2and T7. If T2is larger, i.e., has a higher effective width to length ratio than T7, then I2will be larger than Iref. Furthermore, as described previously, I2has a variable value based on the value of the bulk modulation signal BM. I2is higher when BM is high than when BM is low. Accordingly, I2has a high value when BM is high. I2has a low value when BM is low.

The driver switches T1and T2may be designed so that I1has a higher magnitude than I2. Alternatively, the driver switches T1and T2may be designed so that I2has a higher magnitude than I1.

The operation of the driver circuits106and108the can be understood in relation toFIGS.2and1B. The current I1will either flow through T3or T4into T1, depending on the values of D+and D−. If I1flows through T3, then I1flows from R1and R3through TXP into the driver106. If I1flows through T4, then I1flows from R2and R4through TXN into the driver106. The current I2will either flow through T5or T6into T2, depending on the values of D+dand D−d. If I2flows through T5, then I2flows from R1and R3through TXP into the driver108. If I2flows through T6, then I2flows from R2and R4through TXN into the driver108.

With reference to bothFIGS.2and1B, during the first UI the data value is 0. Though not shown, the data value during the UI before the first UI shown inFIG.1Bwas also 0. Thus, during the first UI, D+and D+dare both 0, while D−and D−dare both 1. The result is that I1flows through the resistors R2and R4(not shown) into the transmission line TXN, through the transistor T4and through the driver switch T1. This results in a voltage on TXN of Vn=VDD−Rp*I1. The current I2flows through the resistors R1and R3(not shown), through the transistor T5and through the driver switch T2. This result is a voltage on TXP of Vp=VDD−Rp*I2. The result is that VD=Rp*(I1−I2), where I1and I2have their low values due to the low value of BM.

During the second UI, the data value is 1. The data value during the first U1was 0. Thus, during the second UI, D+and D−dare both 1, while D−and D+dare both 0. The result is that I1and I2both flow through the resistors R1and R3, while no current flows through R2and R4. This results in Vp=VDD−Rp*(I1+I2), Vn=VDD, and VD=Rp*(I1+I2), where I1and I2have their higher values due to the high value of BM.

During the third UI, the data value is 1. The data value during the second U1was 1. Thus, during the third UI, D+and D+dare both 1, while D−and D−dare both 0. The result is that I1flows through the resistors R1and R3, while 12 flows through the resistors R2and R4. This results in Vp=VDD−Rp*I1, Vn=VDD−Rp*I2, and VD=Rp*(I1−I2), where I1and I2have their lower values due to the low value of BM.

During the fourth UI, the data value is 0. The data value during the third U1was 1. Thus, during the fourth UI, D+and D−dare both 0, while D−and D+dare both 1. The result is that I1and I2flow through the resistors R2and R4, while no current flows through the resistors R1and R3. This results in Vp=VDD), Vn=VDD−Rp*(I1+R2), and VD=Rp*(I1+I2), where I1and I2have their higher values due to the high value of BM.

FIG.3is a schematic diagram of a driver switch T1, in accordance with some embodiments. The driver switch T1includes a plurality of transistors TS1-TS5coupled together in parallel. The drain terminals of the transistors TS1-TS5are all coupled together. The source terminals of the transistors TS1-TS5are all coupled together. The gate terminals of the transistors TS1-TS5all receive the mirror voltage VM. The bulk terminals of the transistors TS1-TS5all receive the bulk modulation signal BM. The current I1is the sum of the currents flowing through all of the transistors TS1-TS5. WhileFIG.3illustrates a driver switch T1including five transistors, the driver switch T1can have other numbers of transistors coupled in parallel without departing from the scope of the present disclosure. The driver switch T2can be substantially identical to the driver switch T1. In some embodiments, the driver switch T2has a smaller number of parallel-coupled transistors than does the driver switch T1.

FIG.4is a schematic diagram of a driver switch T1, in accordance with some embodiments. The driver switch T1ofFIG.4is substantially identical to the driver switch T1ofFIG.3, except that only a subset of the transistors receives the bulk modulation voltage, while the other transistors of the bulk terminal coupled to ground. In particular, the bulk terminals of TS1and TS2are coupled to ground, while the bulk terminals of the transistors TS3-TS5receive the bulk modulation signal BM. The driver switch T2can be substantially identical to the driver switch T1. In some embodiments, the driver switch T2has a smaller number of parallel-coupled transistors than does the driver switch T1. The driver switch T2may have a same number of transistors that receive the bulk modulation signal BM as the driver switch T1. Alternatively, the driver switch T2may have a different number of transistors that receive the bulk modulation signal BM.

FIG.5is a graph500including a plurality of signals related to current mode transmission, according to one embodiment.FIG.5illustrates the clock signal CLK and times t0-t15. UI1corresponds to the first clock cycle having a period between times t0and t1. UI2corresponds to the second clock cycle having a period between times t1and t2. This pattern continues until UI15corresponding to the 15thclock cycle between t14and t15. The graph500illustrates the single bit data stream D. The single bit data stream has a data value of either binary 0 or binary 1 for each UI, or for each clock cycle. The graph500illustrates the delayed single bit data stream DD, delayed from the single bit data stream D by a single clock cycle or by a single UI.

The graph500also illustrates the bulk modulation voltage VBM. The bulk modulation voltage of VBM has a value that is high when D and DDhave different values. VBM has a low value when D and DDhave the same value. For example, at UI1, D and DDare both 0, so VBM is low. At UI2, D is 1 and DD is 0, so VBM is high. At UI3, D is 0, DDis 1, and VBM is 1. At UI4, D and DDare both 0, so VBM is low. This pattern is evident through the remainder of the UIs or clock cycles.

FIG.6is a flow diagram of a method600, according to one embodiment. The method600can utilize systems, components, and processes described in relation toFIGS.1A-5. At602, the method600includes receiving a first stream of data values at a first driver of a current mode transmitter. At604, the method600includes receiving the first stream of data values at a transition detector. At606, the method600includes generating, with the transition detector, a bulk modulation voltage based on the first stream of data values. At608, the method600includes supplying the bulk modulation voltage to a bulk terminal of a first driver switch of the first driver.

FIG.7is a flow diagram of a method700, according to one embodiment. The method700can utilize systems, components, and processes described in relation toFIGS.1A-6. At702, the method700includes receiving a first stream of data values at a first driver of a current mode transmitter. At704, the method700includes generating a second stream of data values by delaying the first stream of data values by one or more cycles of a clock signal. At706, the method700includes receiving the second stream of data values at a second driver of the current mode transmitter. At708, the method700includes receiving the first and second streams of data values at a transition detector. At710, the method700includes generating, with the transition detector, a bulk modulation voltage having an amplitude based on the first and second data streams. At712, the method700includes supplying the bulk modulation voltage to a bulk terminal of a first driver switch of the first driver. At714, the method700includes supplying the bulk modulation voltage to a bulk terminal of a second driver switch of the second driver. At716, the method700includes generating a current mode data stream based on outputs of the first and second drivers.

In one embodiment, an integrated circuit includes an input data source and a current mode transmitter coupled to the input data source. The current mode transmitter includes a primary driver including a first driver switch, a secondary driver including a second driver switch, a delay circuit coupled between the input data source and the secondary driver, and a transition detector. The transition detector includes a first input coupled to the input of the primary driver and the secondary driver, a second input coupled to the input of the secondary driver, and an output coupled to a bulk terminal of the first driver switch and to a bulk terminal of the second driver switch.

In one embodiment, an integrated circuit includes a first driver of a current mode transmitter. The first driver includes an input and a first driver switch having a bulk terminal. The integrated circuit includes a transition detector having an input coupled to an input of the first driver circuit and an output coupled to the bulk terminal of the first driver switch.

In one embodiment, a method includes receiving a first stream of data values at a first driver of a current mode transmitter and receiving the first stream of data values at a transition detector. The method includes generating, with the transition detector, a bulk modulation voltage based on the first stream of data values and supplying the bulk modulation voltage to a bulk terminal of a first driver switch of the first driver.

In one embodiment, a method includes receiving a first stream of data values at a first driver of a current mode transmitter, generating a second stream of data values by delaying the first stream of data values by one or more cycles of a clock signal, receiving the second stream of data values at a second driver of the current mode transmitter, and receiving the first and second streams of data values at a transition detector. The method includes generating, with the transition detector, a bulk modulation voltage having an amplitude based on the first and second data streams, supplying the bulk modulation voltage to a bulk terminal of a first driver switch of the first driver, supplying the bulk modulation voltage to a bulk terminal of a second driver switch of the second driver, and generating a current mode data stream based on outputs of the first and second drivers.