Semiconductor substrate, semiconductor package, and method for forming the same

The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.

BACKGROUND

Electronic packages, such as electronic control modules, generally contain fabricated electrical circuitry including electronic components such as transistors and resistors. The circuitry conducts electrical current which, in turn, generates thermal energy (heat) within the electronic package. Excessive heat build-up within certain electronic packages and other components within a module may lead to adverse effects including electrical circuit failure. Thus, it is desirable to dissipate heat away from the electronic package.

Many electronic packages employ semiconductor devices in the form of a flip chip. Some comparative techniques for dissipating thermal energy from the electronic package employ a thermally conductive heat sink supported in contact with the package via clamps, or directly mounted onto a printed circuit board.

While comparative approaches generally suffice to dissipate some of the thermal energy (heat) away from the semiconductor device, many approaches do not offer optimal heat dissipation. For example, many approaches achieve a substantial amount of heat dissipation in one general direction, primarily by placing a heat sink in thermal contact with one surface of the semiconductor device. While some additional heat dissipation may be achieved in other directions through air or some other medium exhibiting poor thermal conductivity, such heat dissipation is generally inadequate. The resultant heat dissipation realized in many comparative semiconductor packages results in size and power limitations.

Accordingly, it is therefore desirable to provide a semiconductor device and heat sink package and method of dissipating thermal energy (heat) away from the semiconductor device in an optimal manner.

SUMMARY

Some embodiments of the present disclosure provide a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure has a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface.

Some embodiments of the present disclosure provide a semiconductor package, including a dielectric structure having a bottom surface configured to be proximal to a solder bump and a side surface connecting to the bottom surface, a first patterned conductive layer proximal to a top surface of the dielectric structure, the top surface being opposite to the bottom surface, a second patterned conductive layer extending on the side surface, a third patterned conductive layer closer to the bottom surface than the first patterned conductive layer and extending on the side surface; and a semiconductor die over the top surface.

Some embodiments of the present disclosure provide a method for manufacturing a semiconductor package, including providing a carrier, forming a first patterned conductive layer on the carrier, defining a scribe line region in the dielectric structure by forming an opening in the dielectric structure, and concurrently forming a second patterned conductive layer on the dielectric structure and extending into the opening.

DETAILED DESCRIPTION

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

The numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, and the numerical values set forth in the specific examples may be reported as precisely as possible. Some numerical values, however, may contain certain errors resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of a given value or range. Alternatively, the term “about” means within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along a same plane, such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of lying along the same plane. When referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values.

Some packages possess greater requirements of heat dissipation. In some embodiments, attaching an extra heat sink over molding compound, removing a portion of the molding compound in order to expose the chip being packaged, or adopting new molding compound materials having better heat conductance have been utilized to meet the demand from a packaging level. Nevertheless, the aforesaid measures increase the cost to overall package production.

On the other hand, increasing copper density, for example, thickening copper lines or plating extra copper in the substrate, may also meet the demand from a substrate level. However, thickness of the substrate, and hence thickness of the entire package, may be increased as a result.

The present disclosure further provides substrate units surrounded by scribe lines. By plating copper into trenches positioned on the scribe lines concurrently with plating copper to form conductive wirings in the substrate, copper density in substrate can be effectively increased. Such operation enhances heat dissipation through greater copper density without additional manufacturing operations. Due to the fact that the width of the scribe line trench is greater than the width of the conductive wiring trench, it is anticipated that the conductive wiring trench is filled before the scribe line trench. Such unfilled scribe line trench may further alleviate substrate warpage.

Referring toFIG. 1AandFIG. 1B,FIG. 1AandFIG. 1Bare perspective views of a portion of a semiconductor substrate, according to some embodiments of the present disclosure. The semiconductor substrate is composed of a plurality of units101defined by corresponding scribe line regions111. As shown inFIG. 1A, each of the units101is surrounded at four sides by the scribe line regions111, thus defining a tetragonal shape unit101. In some embodiments, the scribe line regions111are in a form of filled or partially-filled continuous trenches. Alternatively, the scribe line regions111can be formed of filled or partially-filled vias, such as those shown inFIG. 1B.

In reference toFIG. 1C,FIG. 1Cis a cross-sectional view dissected from line AA inFIG. 1AandFIG. 1B. Line AA dissects one unit on the substrate from its left boundary to its right boundary. Starting from the left boundary and traversing to the right, scribe line regions111are first seen on the left, followed by a plurality of conductive layers112within the unit, and finally the other scribe line regions111are seen at the right boundary. In some embodiments, the conductive layers112may function as power lines and re-distribution lines (RDL). The plurality of conductive layers112are formed in a layer-based dielectric structure, that is, each conductive layer is formed in a corresponding dielectric layer, and manufacturing traces such as a seed layer disposed prior to conductive layer plating can be identified under a microscope with or without slight etching. Similarly, such manufacturing traces can also be found in the scribe line regions111. Details of such manufacturing traces are described inFIG. 3AandFIG. 3Bof the present disclosure.

Referring toFIG. 2A,FIG. 2B, andFIG. 2C,FIG. 2A,FIG. 2B, andFIG. 2Care cross-sectional views illustrating three different semiconductor packages, according to some embodiments of the present disclosure. InFIG. 2A, a semiconductor substrate shown inFIG. 1Cis integrated with solder bumps201at a bump side201′ and a semiconductor die202at a die side202′ to form a semiconductor package20A. In some embodiments, the die202is joined with the substrate through conductive bumps and thermal interface materials (TIM)204. Alternatively, the TIM204can be applied in proximity to the die side202′ of the substrate over the scribe line regions111, and a heat sink203is joined with the substrate via the TIM204over the scribe line regions111. The semiconductor package20A provides better heat dissipation than comparative semiconductor packages because at least the scribe line regions111possess higher density conductive materials, such as copper, so that the heat generated at the die202can be effectively dissipated through a more effective heat-conducting channel from the heat sink203to the conductive materials at the scribe line regions111.

InFIG. 2B, a semiconductor substrate shown inFIG. 1Cis integrated with solder bumps201at a bump side201′ and a semiconductor die202at a die side202′ to form a semiconductor package20B. In some embodiments, the die202is joined with the substrate through conductive bumps and underfill materials. Alternatively, a molding compound205with suitable heat conductance covers the die202and concurrently contacts the conductive materials at the scribe line regions111. The semiconductor package20B provides better heat dissipation than comparative semiconductor packages because at least the scribe line regions111possess higher density conductive materials, such as copper, so that the heat generated at the die202can be effectively dissipated through a more effective heat-conducting channel from the molding compound205to the conductive materials at the scribe line regions111.

InFIG. 2C, a semiconductor substrate shown inFIG. 1Cis integrated with solder bumps201at a bump side201′ and a semiconductor die202at a die side202′ to form a semiconductor package20B. In some embodiments, the die202is joined with the substrate through conductive bumps and/or underfill materials. Alternatively, a molding compound205with suitable heat conductance covers the die202and concurrently contacts the conductive materials at the scribe line regions111. Furthermore, a copper wire206further connects a conductive surface204, for example, at a back side of the die202, to the conductive materials at the scribe line regions111. The semiconductor package20C provides better heat dissipation than comparative semiconductor packages because at least the scribe line regions111possess higher density conductive materials, such as copper, so that the heat generated at the die202can be effectively dissipated through a more effective heat-conducting channel from the molding compound205and the copper wire206to the conductive materials at the scribe line regions111.

Referring toFIG. 3A,FIG. 3Ais a cross-sectional view illustrating a semiconductor substrate10, according to some embodiments of the present disclosure. The semiconductor substrate10includes a first patterned conductive layer L1and a first dielectric structure D1on the first patterned conductive layer L1. In some embodiments, the first patterned conductive layer L1extends over a within unit region112′ and the first patterned conductive layer L1′ extends over a scribe line region111. The within unit region112′ is referred to herein as a conductive pattern region. Referring back toFIG. 1C, the first dielectric structure D1possesses a side surface S1over the scribe line region111, rather than over the within unit region112′, of the substrate10. The first dielectric structure D1includes a plurality of via trenches L21in the within unit region112′, wherein the plurality of via trenches L21are filled with conductive materials and connect to a portion of the first patterned conductive layer L1. The first dielectric structure D1includes at least a scribe line trench M11, in the scribe line region111, wherein the scribe line trench M11is filled or partially filled with conductive materials and connects to the first patterned conductive layer L1′ of the scribe line region111. The scribe line trench M11is about 3 to 6 times wider than the via trench L21. In some embodiments, a width W2of a via trench L21is from about 50 to 70 μm, and a width W1of a scribe line trench M11is from about 250 to 300 μm. A scribe line SC inFIG. 3Aillustrates a cutting edge of the substrate10after the die mount, molding encapsulation, and soldering are conducted and a semiconductor package is completed. After each unit is separated along the scribe line SC to form individual packages, the side surface S1of the first dielectric structure D1is a slanted surface at the edge of the individual package.

As shown inFIG. 3A, the conductive materials filled in the via trenches L21and the scribe line trench M11include a second patterned conductive layer SE1, a third patterned conductive layer L2, and a metal structure M1. In some other embodiments where several metal structures are presented, the metal structure M1can be a first metal structure. In some embodiments, the third patterned conductive layer L2and the metal structure M1are formed in a single deposition operation. The third patterned conductive layer L2and the metal structure M1penetrate the first dielectric structure D1and contact the first patterned conductive layer L1and first patterned conductive layer L1′, respectively. In some embodiments, the first patterned conductive layer L1′ is electrically coupled with the first patterned conductive layer L1. In some embodiments, the first patterned conductive layer L1′ is electrically coupled with the third patterned conductive layer L2through the metal structure M1. In some embodiments, the conductive layer and the metal structure at the scribe line region111may or may not electrically connect to the conductive layer at the within unit region112′.

The second patterned conductive layer SE1may be a copper seed layer. The copper seed layer may be formed of copper or of one of copper alloys that include silver, chromium, nickel, tin, gold, and combinations thereof. The thickness of the copper seed layer is in a range between about 2000 and about 8000 Angstrom. The third patterned conductive layer L2and the metal structure M1can be composed of the same materials as the first patterned conductive layer L1. Since the scribe line trench M11is wider than the via trench L21, the conductive materials may completely fill the via trench L21but partially fill the scribe line trench M11. The extent of how much the scribe line trench M11is filled can be determined by the relative widths of the via trench L21and the scribe line trench M11. As previously discussed inFIG. 1AandFIG. 1B, the scribe line region111may include filled or partially-filled continuous trenches or filled or partially-filled vias; therefore, the scribe line trench M11in other embodiments represents a scribe line via.

Referring toFIG. 3B,FIG. 3Bis a cross-sectional view illustrating a semiconductor package10′, according to some embodiments of the present disclosure. The semiconductor package10′ includes a first dielectric structure D1having a top surface T proximal to a semiconductor die202and a bottom surface B proximal to a solder bump201. The package10′ includes a first patterned conductive layer L1close to the top surface T. In some embodiments, the first patterned conductive layer L1extends over a within unit region112′ and the first patterned conductive layer L1′ extends over a scribe line region111. Referring back toFIG. 1C, the first dielectric structure D1possesses a side surface S1′ over the scribe line region111, rather than over the within unit region112′, of the package10′. The first dielectric structure D1includes a plurality of via trenches L21, in the within unit region112′, filled with conductive materials and connecting to a portion of the first patterned conductive layer L1. The first dielectric structure D1includes at least a scribe line trench M11′, in the scribe line region111, filled or partially filled with conductive materials, connecting to the first patterned conductive layer L1′ of the scribe line region111. The scribe line trench M11is about 3 to 6 times wider than the via trench L21. In some embodiments, a width W2of a via trench L21is from about 50 to 70 μm, and a width W1of a scribe line trench M11′ is from about 250 to 300 μm. A scribe line SC inFIG. 3Billustrates a cutting edge of the package10′. After each unit is separated along the scribe line SC to form individual packages, the side surface S1of the first dielectric structure D1is a slanted surface at the edge of the individual package.

As shown inFIG. 3B, the conductive materials filled in the via trenches L21and the scribe line trench M11′ include a second patterned conductive layer SE1′, a third patterned conductive layer L2, and a metal structure M1′. In some embodiments, the third patterned conductive layer L2and the metal structure M1′ are formed in a single deposition operation. The third patterned conductive layer L2and the metal structure M1′ penetrate the first dielectric structure D1and contact the first patterned conductive layer L1and first patterned conductive layer L1′, respectively. In some embodiments, the first patterned conductive layer L1′ is electrically coupled with the first patterned conductive layer L1. In some embodiments, the first patterned conductive layer L1′ is electrically coupled with the third patterned conductive layer L2through the metal structure M1′. In some embodiments, the conductive layer and the metal structure at the scribe line region111may or may not electrically connect to the conductive layer at the within unit region112′.

The second patterned conductive layer SE1′ may be a copper seed layer. The copper seed layer may be formed of copper or of one of copper alloys that include silver, chromium, nickel, tin, gold, and combinations thereof. The thickness of the copper seed layer is in a range between about 2000 and about 8000 Angstrom. The third patterned conductive layer L2and the metal structure M1′ can be composed of the same materials as the first patterned conductive layer L1. Since the scribe line trench M11′ is wider than the via trench L21, the conductive materials may completely fill the via trench L21but partially fill the scribe line trench M11′. The extent to which the scribe line trench M11′ is filled can be determined by the relative widths of the via trench L21and the scribe line trench M11′. As previously discussed in descriptions ofFIG. 1AandFIG. 1B, the scribe line region111may include filled or partially-filled continuous trenches or filled or partially-filled vias; therefore, the scribe line trench M11in other embodiments represents a scribe line via.

InFIG. 3B, the semiconductor die202is disposed over the top surface T of the first dielectric structure D1, joining with a bump over the top surface T of the first dielectric structure D1. The semiconductor die202is further encapsulated by a molding compound205disposed on the top surface T.

FIG. 4toFIG. 8are cross-sectional views illustrating various semiconductor substrates, according to some embodiments of the present disclosure.FIG. 4illustrates a semiconductor substrate40based on the semiconductor structure10ofFIG. 3A. Identical numeric labels inFIG. 4can be interpreted as substantially identical elements or equivalents of those inFIG. 3A, and descriptions thereof are omitted for brevity. In addition to the first patterned conductive layer L1, L1′, the second patterned conductive layer SE1, the first dielectric layer D1, the first metal structure M1, and the third patterned conductive layer L2, the semiconductor substrate40further includes a second dielectric layer D2covering a portion of the first metal structure M1and the third patterned conductive layer L2, a fourth patterned conductive layer SE2extending on the side surface of the first and second dielectric layer D1, D2, a fifth patterned conductive layer L3, and a second metal structure M2extending on the side surface of the first and second dielectric layers D1and D2. In some embodiments, the second metal structure M2may be composed of the same material as that comprising the first metal structure M1. In some embodiments, the fourth patterned conductive layer SE2may be composed of the same material as that comprising the second patterned conductive layer SE1. In some embodiments, the fifth patterned conductive layer L3may be composed of the same material as that comprising the third patterned conductive layer L2.

Similar to the connection between the first metal structure M1and the third patterned conductive layer L2, the second metal structure M2at the scribe line region111may or may not electrically connect to the conductive layers at the within unit region112′.

In the semiconductor structure40, the second metal structure M2extends from a top surface T2of the second dielectric layer D2toward the side surface of the second dielectric layer D2, and overlaps with the portion of the first metal structure M1extending over the side surface of the first dielectric layer D1down to the bottom of the scribe line trench M11. Alternatively stated, the second metal structure M2extends toward a level lower than the top surface T1of the first dielectric layer D1. After suitable fine polishing and micro-etching, the fourth patterned conductive layer SE2can be easily observed to be positioned between the first metal structure M1and the second metal structure M2, as well as between the second metal structure M2and the second dielectric layer D2.

Referring toFIG. 5,FIG. 5illustrates a semiconductor substrate50similar to that of the semiconductor substrate40, except for the portion of the first metal structure M1and the second metal structure M2. InFIG. 5, the first metal structure M1possesses a top surface T1′ level with the top surface of the third patterned conductive layer L2. Similarly, the second metal structure M2possesses a top surface T2′ level with the top surface of the fifth patterned conductive layer L3. Note the first metal structure M1and the second metal structure M2fill the scribe line region111to an extent that a vertical sidewall V can be observed after die separation. A portion of the vertical sidewall V is a cutting edge of the second metal structure M2, and a portion of the vertical sidewall V is a cutting edge of the first metal structure M1. The fourth patterned conductive layer SE2is positioned on the top surface T1′, the side surface and the top surface of the second dielectric layer D2, separating the second metal structure M2from the first metal structure M1and the second dielectric layer D2.

Referring toFIG. 6,FIG. 6illustrates a semiconductor substrate60similar to that of the semiconductor substrate40, except for the portion of the first metal structure M1and the second metal structure M2. InFIG. 6, the second metal structure M2possesses a top surface T2′ level with the top surface of the fifth patterned conductive layer L3. Note the second metal structure M2fills the scribe line region111to an extent that a vertical sidewall V can be observed after die separation. The vertical sidewall V is a cutting edge of the second metal structure M2. The first metal structure M1delineates the side surface of the first dielectric layer D1and is positioned on the first patterned conductive layer L1′. The fourth patterned conductive layer SE2is positioned on a side surface and the top surface of the second dielectric layer D2, separating the second metal structure M2from the first metal structure M1and the second dielectric layer D2. The second metal structure M2also extends below the top surface T1of the first dielectric layer D1.

Referring toFIG. 7,FIG. 7illustrates a semiconductor substrate70similar to that of the semiconductor substrate40, except for the portion of the first metal structure M1and the second metal structure M2. InFIG. 7, the first metal structure M1possesses a top surface T1′ level with the top surface of the third patterned conductive layer L2. Note the first metal structure M1fills the scribe line region111to an extent that a vertical sidewall V can be observed after die separation. The vertical sidewall V is a cutting edge of the first metal structure M1. The second metal structure M2delineates the side surface of the second dielectric layer D2and is positioned on the top surface T1′ of the first metal structure M1.

Referring toFIG. 8,FIG. 8illustrates a semiconductor substrate80similar to that of the semiconductor substrate40, except for the portion of the first metal structure M1and the second metal structure M2. InFIG. 8, no first metal structure M1is presented at the level of the first dielectric layer D1and the third patterned conductive layer L2. The second metal structure M2delineates the side surface of the first dielectric layer D1and the second dielectric layer D2down to the level of the first patterned conductive layer L1′. In an alternative embodiment not shown inFIG. 8, the second metal structure M2fills the scribe line region111to an extent that a vertical sidewall V can be observed after die separation. The vertical sidewall V is a cutting edge of the second metal structure M2in such alternative embodiment.

FIG. 9toFIG. 13are cross-sectional views illustrating various semiconductor packages, according to some embodiments of the present disclosure.FIG. 9toFIG. 13show semiconductor packages90,100,110,120and130fabricated on respective semiconductor substrates40,50,60,70and80, as described inFIG. 4toFIG. 8. Details of the respective semiconductor substrates40,50,60,70and80are provided inFIG. 4toFIG. 8of the present disclosure and are therefore omitted herein for brevity. In addition to the semiconductor substrates40,50,60,70and80, each of the semiconductor packages90,100,110,120and130includes a top surface T and a bottom surface B of the dielectric structure D. The bottom surface B is proximal to a solder bump901, and the top surface T is opposite to the bottom surface B and closer to the semiconductor die202than the bottom surface B. The semiconductor die202is joined with the respective semiconductor substrates40,50,60,70and80through a solder bump902and a bond pad903on the semiconductor die202. A molding compound205encapsulates at least the semiconductor die202and the bond pad903, and the molding compound205is positioned on the top surface T of the dielectric structure D and is in contact with the first patterned conductive layer L1.

FIG. 9toFIG. 13provide one example of the various semiconductor packages including respective semiconductor substrates40,50,60,70and80. Other package structures, such as those described with respect toFIG. 2A,FIG. 2B, andFIG. 2Ccan also include respective semiconductor substrates40,50,60,70and80and are within the contemplated scope of the present disclosure.

FIG. 14AtoFIG. 14Fare cross-sectional views illustrating the semiconductor substrate10in various manufacturing stages, according to some embodiments of the present disclosure. InFIG. 14A, a carrier1401is provided with a first patterned conductive layer L1. The first patterned conductive layer L1can be formed by additive manufacturing or subtractive manufacturing. In additive manufacturing, a photoresist (PR) layer is formed prior to electroplating of the conductive materials. The conductive pattern is formed after the removal of the PR. On the other hand, the subtractive manufacturing performs a blanket electroplating of the conductive materials prior to PR formation. Portions of the conductive materials not covered by the PR will then be removed.

InFIG. 14B, a dielectric layer D1is laminated over the first patterned conductive layer L1. InFIG. 14C, several openings O1and O2are formed in the dielectric layer D1by laser grooving, and the openings O1and O2taper from the top toward the bottom of the dielectric layer D1, exposing a top surface of the first patterned conductive layer L1. In some embodiments, at least one opening O1is formed in the scribe line region111and one opening O2is formed in the conductive pattern region112′. The opening O1at the scribe line region111can be a localized via or a cross section of a saw street extending between a plurality of units101. A width W2of the opening O2in the conductive pattern region112′ is from about 50 to 70 μm, and a width W1of the opening O1in the scribe line region111is from about 250 to 300 μm.

InFIG. 14D, a second patterned conductive layer SE1, such as a seed layer, is formed by an electroless plating operation to cover the top surface of the dielectric layer D1, the side walls of the openings O1and O2, and a portion of the first patterned conductive layer L1, L1′, unselectively. A third patterned conductive layer L2is formed over the second patterned conductive layer SE1by an additive manufacturing operation, both in the scribe line region111and in the conductive pattern region112′. After removing the PR in the additive manufacturing operation, a desired pattern is obtained in the third patterned conductive layer L2. The portion of the conductive layer residing in the scribe line region111is a metal structure M1, and the portion residing in the conductive pattern region112′ is referred to herein as the third patterned conductive layer L2. Due to the fact that the width W1is greater than the width W2, when conducted under one electroplating operation with identical electroplating conditions, the opening O2is completely filled while the opening O1is partially filled. In some embodiments, the electroplating operation conducted inFIG. 14Dis a pattern plating operation, which is configured to form finer conductive lines delineating a contour of the opening O1in the scribe line region111, in contrast to a panel plating operation, which will be described in relation toFIG. 16Dof the present disclosure.

A flash etching is conducted to further remove the remaining second patterned conductive layer SE1, which was originally under PR coverage, thereby exposing a portion of the top surface of the dielectric layer D1through the second patterned conductive layer SE1and the third patterned conductive layer L2. InFIG. 14E, a solder resist SR is formed over the third patterned conductive layer L2, but the solder resist SR is free from covering the scribe line region111. After die bonding and molding operations (not shown), individual units are separated at the scribe line region111. A semiconductor substrate10having a unique metal structure M1at the scribe line region111after separation is illustrated inFIG. 14F. The metal structure M1in the semiconductor substrate10enhances heat dissipation through extra copper density without additional manufacturing operations, while, at the same time, the unfilled scribe line trench may further alleviate substrate warpage problems.

FIG. 15AtoFIG. 15Jare cross-sectional views illustrating the semiconductor substrate40in various manufacturing stages, according to some embodiments of the present disclosure. Descriptions ofFIG. 15AtoFIG. 15Dcan be found by referring to those provided forFIG. 14AtoFIG. 14Dand are not repeated here for brevity. InFIG. 15E, a second dielectric layer D2is laminated over the third patterned conductive layer L2and fills the partially filled scribe line trench delineated with the first metal structure M1. InFIG. 15F, several openings O3and O4are formed in the dielectric layer D2by laser grooving, and the openings O3and O4taper from the top toward the bottom of the dielectric layer D2, exposing a top surface of the second patterned conductive layer L2. In some embodiments, at least one opening O3is formed in the scribe line region111and one opening O2is formed in the conductive pattern region112′. In some embodiments, the opening O3aligns with the first opening O1. The opening O1at the scribe line region111can be a localized via or a cross section of a saw street extending between plurality of units101. A width W3of the opening O3in the conductive pattern region112′ is between about 50 and 70 μm, and a width W4of the opening O4in the scribe line region111is between about 250 and 300 μm.

InFIG. 15G, a fourth patterned conductive layer SE2, such as a seed layer, is formed by an electroless plating operation to cover the top surface of the dielectric layer D2, the side walls of the openings O3and O4, and a portion of the first metal structure M1, unselectively. A fifth patterned conductive layer L3is formed over the fourth patterned conductive layer SE2by an additive manufacturing operation, both in the scribe line region111and in the conductive pattern region112′. After removing the PR in the additive manufacturing operation, a desired pattern is obtained in the fifth patterned conductive layer L2. The portion of the conductive layer residing in the scribe line region111is a metal structure M2, and the portion residing in the conductive pattern region112′ is referred to herein as the fifth patterned conductive layer L3. Due to the fact that the width W3is greater than the width W4, when conducted under one electroplating operation with identical electroplating conditions, the opening O4is completely filled while the opening O3is partially filled. In some embodiments, the electroplating operation conducted inFIG. 15Gis a pattern plating operation. A flash etching is conducted to further remove the remaining fourth patterned conductive layer SE2, which was originally under PR coverage, thereby exposing a portion of the top surface of the dielectric layer D2through the fourth patterned conductive layer SE2and the fifth patterned conductive layer L3.

InFIG. 15HtoFIG. 15I, the carrier1401is removed from a second side S2of the dielectric layers D1and D2. Solder resist SR is subsequently formed on the first side S1and the second side S2of the dielectric layers D1and D2, but the solder resist SR is free from covering the scribe line region111. After die bonding and molding operations (not shown), individual units are separated at the scribe line region111. A semiconductor substrate40having unique metal structures M1and M2at the scribe line region111after separation is illustrated inFIG. 15J. The metal structures M1and M2in the semiconductor substrate40enhance heat dissipation through extra copper density without additional manufacturing operations, while, at the same time, the unfilled scribe line trench may further alleviate substrate warpage problems.

FIG. 16AtoFIG. 16Lare cross-sectional views illustrating the semiconductor substrate50in various manufacturing stages, according to some embodiments of the present disclosure. Description ofFIG. 16AtoFIG. 16Ccan be found by referring to those provided forFIG. 14AtoFIG. 14Cand are not repeated here for brevity. InFIG. 16D, a second patterned conductive layer SE1, such as a seed layer, is formed by an electroless plating operation to cover the top surface of the dielectric layer D1, the side walls of the openings O1and O2, and a portion of the first patterned conductive layers L1and L1′, unselectively. A third patterned conductive layer L2′ is panel plated over the second patterned conductive layer SE1, both in the scribe line region111and in the conductive pattern region112′. In contrast to the pattern plating operation, the panel plating operation conducted inFIG. 16Dforms coarser conductive lines, completely filling the opening O1in the scribe line region111and the opening O2in the conductive pattern region112′. In some embodiments, the electroplating operation ofFIG. 16Dcan be conducted by a pattern plating followed by a panel plating.

Comparing the pattern plating inFIG. 14Dto the panel plating inFIG. 16D, panel plating allows the semiconductor substrate to possess a greater volume of conductive material, for example, greater volume of copper, thereby enhancing mechanical strength or rigidity of the semiconductor substrate. By adopting both panel plating and pattern plating in a suitable fashion, one can control the conductive material volume in the opening O1, thereby achieving desirable mechanical strength or rigidity of the semiconductor substrate in order to protect against foreseeable warpage problems.

InFIG. 16E, a reduction operation is conducted to remove excess conductive material from above the top surface of the dielectric layer D1. InFIG. 16F, the third patterned conductive layer L2is completed by, for example, a subtractive manufacturing process. FollowingFIG. 16E, a conductive layer is plated over the top surface of the dielectric layer D1, followed by a patterned PR formation. As shown inFIG. 16F, the portion of the conductive layer exposed through the patterned PR is removed, rendering the third patterned conductive layer L2in the conductive pattern region112′ and the first metal structure M1in the scribe line region111. InFIG. 16G, a second dielectric layer D2is laminated over the third patterned conductive layer L2and covers the first metal structure M1. InFIG. 16H, several openings O3and O4are formed in the dielectric layer D2by laser grooving, and the openings O3and O4taper from the top toward the bottom of the dielectric layer D2, exposing a top surface of the second patterned conductive layer L2and the first metal structure M1. In some embodiments, at least one opening O3is formed in the scribe line region111and one opening O4is formed in the conductive pattern region112′. In some embodiments, the opening O3aligns with the first opening O1. The opening O1at the scribe line region111can be a localized via or a cross section of a saw street extending between a plurality of units101. A width W4of the opening O4in the conductive pattern region112′ is between about 50 and 70 μm, and a width W3of the opening O3in the scribe line region111is between about 250 and 300 μm.

InFIG. 16I, a fourth patterned conductive layer SE2, such as a seed layer, is formed by an electroless plating operation to cover the top surface of the dielectric layer D2, the side walls of the openings O3and O4, and a portion of the first metal structure M1, unselectively. A fifth patterned conductive layer L3and the second metal structure M2are formed over the fourth patterned conductive layer SE2, in the conductive pattern region112′ and in the scribe line region111, respectively. In some embodiments, formation of the fifth patterned conductive layer L3and the second metal structure M2may follow the description of the formation of the third patterned conductive layer L2and the first metal structure M1in the current embodiment, and the description thereof is not repeated here for brevity.

InFIG. 16JtoFIG. 16K, the carrier1401is removed from a second side S2of the dielectric layers D1and D2. A solder resist SR is subsequently formed on the first side S1and the second side S2of the dielectric layers D1and D2, but the solder resist SR is free from covering the scribe line region111. After die bonding and molding operations (not shown), individual units are separated at the scribe line region111. A semiconductor substrate50having unique metal structures M1and M2at the scribe line region111after separation is illustrated inFIG. 16L. The metal structures M1and M2in the semiconductor substrate50enhance heat dissipation through extra copper density without additional manufacturing operations. Although the scribe line trench is filled with conductive materials, substrate warpage problems can be better alleviated compared to the configuration where just the dielectric layers D1and D2reside in the scribe line region111.

FIG. 17AtoFIG. 17Lare cross-sectional views illustrating the semiconductor substrate60in various manufacturing stages, according to some embodiments of the present disclosure. Descriptions ofFIG. 17AtoFIG. 17Fcan be found by referring to descriptions ofFIG. 15AtoFIG. 15Fand are not repeated here for brevity. InFIG. 17G, a fourth patterned conductive layer SE2, such as a seed layer, is formed by an electroless plating operation to cover the top surface of the dielectric layer D2, the side walls of the openings O3and O4, and portions of the third patterned conductive layer L2and the first metal structure M1, unselectively. A fifth patterned conductive layer L3′ is panel plated over the fourth patterned conductive layer SE2, both in the scribe line region111and in the conductive pattern region112′. In contrast to the pattern plating operation, the panel plating operation conducted inFIG. 17Gforms coarser conductive lines, completely filling the opening O3in the scribe line region111and the opening O4in the conductive pattern region112′. In some embodiments, the electroplating operation ofFIG. 17Gcan be conducted by a pattern plating followed by a panel plating.

InFIG. 17H, a reduction operation is conducted to remove excess conductive material from above the top surface of the dielectric layer D2. InFIG. 17I, the fifth patterned conductive layer L3is completed by, for example, a subtractive manufacturing process. FollowingFIG. 17H, a conductive layer is plated over the top surface of the dielectric layer D2, followed by a patterned PR formation. As shown inFIG. 17I, the portion of the conductive layer exposed through the patterned PR is removed, rendering the fifth patterned conductive layer L3in the conductive pattern region112′ and the second metal structure M2in the scribe line region111. Due to the panel plating conducted inFIG. 17G, the third opening is completely filled with conductive materials, such as copper. As previously discussed, the mechanical strength or rigidity of the semiconductor substrate can thus be further enhanced to protect against the warpage effect.

InFIG. 17JtoFIG. 17K, the carrier1401is removed from a second side S2of the dielectric layers D1and D2. A solder resist SR is subsequently formed on the first side S1and the second side S2of the dielectric layers D1and D2, but the solder resist SR is free from covering the scribe line region111. After die bonding and molding operations (not shown), individual units are separated at the scribe line region111. A semiconductor substrate60having unique metal structures M1and M2at the scribe line region111after separation is illustrated inFIG. 17L. The metal structures M1and M2in the semiconductor substrate60enhance heat dissipation through extra copper density without additional manufacturing operations. Although the scribe line trench is filled with conductive materials, the substrate warpage problem can be better alleviated compared to the configuration where just the dielectric layers D1and D2reside in the scribe line region111.

FIG. 18AtoFIG. 18Lare cross-sectional views illustrating the semiconductor substrate70in various manufacturing stages, according to some embodiments of the present disclosure. Descriptions ofFIG. 18AtoFIG. 18Hcan be found by referring to descriptions addressingFIG. 16AtoFIG. 16Hand are not repeated here for brevity. InFIG. 18I, a fourth patterned conductive layer SE2, such as a seed layer, is formed by an electroless plating operation to cover the top surface of the dielectric layer D2, the side walls of the openings O3and O4, a portion of the second patterned conductive layer L2, and the first metal structure M1, unselectively. A fifth patterned conductive layer L3is formed over the fourth patterned conductive layer SE2by an additive manufacturing operation, both in the scribe line region111and in the conductive pattern region112′. After removing the PR in the additive manufacturing operation, a desired pattern is obtained in the fifth patterned conductive layer L3. The portion of the conductive layer residing in the scribe line region111is a metal structure M2, and the portion residing in the conductive pattern region112′ is referred to herein as the fifth patterned conductive layer L3. Due to the fact that the width W3is greater than the width W4, when conducted under one electroplating operation with identical electroplating conditions, the opening O4is completely filled while the opening O3is partially filled. In some embodiments, the electroplating operation conducted inFIG. 18Iis a pattern plating operation.

InFIG. 18JtoFIG. 18K, the carrier1401is removed from a second side S2of the dielectric layers D1and D2. A solder resist SR is subsequently formed on the first side S1and the second side S2of the dielectric layers D1and D2, but the solder resist is free from covering the scribe line region111. After die bonding and molding operations (not shown), individual units are separated at the scribe line region111. A semiconductor substrate70having unique metal structures M1and M2at the scribe line region111after separation is illustrated inFIG. 18L. The metal structures M1and M2in the semiconductor substrate70enhance heat dissipation through extra copper density without additional manufacturing operations, while, at the same time, the unfilled scribe line trench may further alleviate substrate warpage problems.

FIG. 19AtoFIG. 19Lare cross-sectional views illustrating the semiconductor substrate80in various manufacturing stages, according to some embodiments of the present disclosure. Descriptions ofFIG. 19AtoFIG. 19Bcan be found by referring to descriptions addressingFIG. 14AtoFIG. 14B, and are not repeated herein for brevity. InFIG. 19C, several openings O2are formed in the dielectric layer D1by laser grooving, and the openings O2taper from the top toward the bottom of the dielectric layer D1, exposing a top surface of the first patterned conductive layer L1. In some embodiments, openings O2are selectively formed in the conductive pattern region112′ with a width W2of from about 50 to 70 μm. Descriptions ofFIG. 19DtoFIG. 19Gcan be found by referring to descriptions addressingFIG. 18DtoFIG. 18Gand are not repeated herein for brevity. InFIG. 19H, several openings O3′ and O4are formed in the dielectric layer D2by laser grooving, and the openings O3′ and O4taper from the top toward the bottom of the dielectric layer D2, exposing a top surface of the first patterned conductive layer L1′ and a top surface of the second patterned conductive layer L2, respectively. In some embodiments, at least one opening O3′ is formed in the scribe line region111. In some embodiments, the opening O3′ aligns with the first patterned conductive layer L1′. The opening O3′ at the scribe line region111can be a localized via or a cross section of a saw street extending between a plurality of units101. A width W3of the opening O3′ in the conductive pattern region112′ is between about 250 and 300 μm, and a width W4of the opening O4in the scribe line region111is between about 50 and 70 μm.

InFIG. 19I, a fourth patterned conductive layer SE2, such as a seed layer, is formed by an electroless plating operation to cover the top surface of the dielectric layer D2, the side walls of the openings O3′ and O4, a portion of the second patterned conductive layer L2, and the first patterned conductive layer L1′, unselectively. A fifth patterned conductive layer L3is formed over the fourth patterned conductive layer SE2by an additive manufacturing operation, both in the scribe line region111and in the conductive pattern region112′. After removing the PR in the additive manufacturing operation, a desired pattern is obtained in the fifth patterned conductive layer L3. The portion of the conductive layer residing in the scribe line region111is a metal structure M2, and the portion residing in the conductive pattern region112′ is referred to herein as the fifth patterned conductive layer L3. Due to the fact that the width W3is greater than the width W4, when conducted under one electroplating operation with identical electroplating conditions, the opening O4is completely filled while the opening O3is partially filled. In some embodiments, the electroplating operation conducted inFIG. 19Iis a pattern plating operation.

Alternatively, inFIG. 19I, a fifth patterned conductive layer L3can be formed over the fourth patterned conductive layer SE2by a subtractive manufacturing operation, such as those described inFIG. 17GtoFIG. 17I, wherein the opening O3′ is completely filled with conductive material, enhancing the rigidity of the semiconductor substrate80. It should be noted that, inFIG. 19I, the second metal structure M2is in direct contact with the first patterned conductive layer L1′ in the scribe lien region111without the presence of the first metal structure M1.

InFIG. 19JtoFIG. 19K, the carrier1401is removed from a second side S2of the dielectric layers D1and D2. A solder resist SR is subsequently formed on the first side S1and the second side S2of the dielectric layers D1and D2, but free from covering the scribe line region111. After die bonding and molding operations (not shown), individual units are separated at the scribe line region111. A semiconductor substrate80having unique metal structures M1and M2at the scribe line region111after separation is illustrated inFIG. 19L. The metal structures M1and M2in the semiconductor substrate80enhance heat dissipation through extra copper density without additional manufacturing operations, while, at the same time, the unfilled scribe line trench may further alleviate substrate warpage problems.

The foregoing outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure.