Schottky diode

An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.

BACKGROUND

Integrated circuit (IC) technologies are constantly being improved. Such improvements frequently involve scaling down device geometries to achieve lower fabrication costs, higher device integration density, higher speeds, and better performance. Along with the advantages from reducing geometry size, improvements are being made directly to the IC devices. One such IC device is a Schottky barrier diode, which exhibits low forward voltage drop, switching speeds that approach zero time, and particular usefulness in radio-frequency applications. The Schottky barrier diode includes a metal in contact with a semiconductor material surface. For example, a Schottky device includes a metal silicide layer in contact with a well region, such as an n-well region, of a silicon substrate to form the Schottky contact region. As the doping concentration of the n-well region increases, the doping at the junction of the metal silicide layer/n-well region increases, thus leading to lower breakdown voltages and higher leakage currents than desired. Accordingly, although existing Schottky devices and methods of fabricating Schottky devices have been generally adequate for their intended purposes, as device scaling down continues, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

FIG. 1is a diagrammatic top view of an embodiment of an integrated circuit device100according to various aspects of the present disclosure, andFIG. 2is a diagrammatic sectional side view of the integrated circuit device100taken along line2-2inFIG. 1. In the depicted embodiment, the integrated circuit device100is a Schottky diode. The integrated circuit device100may be an integrated circuit (IC) chip, system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, metal-oxide semiconductor field effect transistors (MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, high voltage transistors, high frequency transistors, oter suitable components, or combinations thereof.FIGS. 1 and 2will be discussed concurrently and have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in the integrated circuit device100, and some of the features described below can be replaced or eliminated for other embodiments of the integrated circuit device100.

The integrated circuit device100includes a substrate110. In the depicted embodiment, the substrate110is a semiconductor substrate including silicon. Alternatively or additionally, the substrate110comprises another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. The substrate110may be a semiconductor on insulator (SOI). The semiconductor substrate110may include a doped epi layer, a gradient semiconductor layer, and/or a semiconductor layer overlying another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer. In the depicted embodiment, the substrate110is a p-doped silicon substrate. P-type dopants that the substrate110are doped with include boron, gallium, indium, other suitable p-type dopants, or combinations thereof. Because the depicted integrated circuit device100includes a p-doped substrate, doping configurations described below should be read consistent with a p-doped substrate. The integrated circuit device100may alternatively include an n-doped substrate, in which case, the doping configurations described below should be read consistent with an n-doped substrate (for example, read with doping configurations having an opposite conductivity). N-type dopants that the substrate110can be doped with include phosphorus, arsenic, other suitable n-type dopants, or combinations thereof.

Isolation features112are formed in the substrate110to isolate various active (OD) regions of the substrate110. The isolation features112may also isolate the integrated circuit device100from other devices (not shown). In the depicted embodiment, the isolation features112utilize shallow trench isolation (STI) technology to form STI features that define and electrically isolate the various regions. Alternatively, the isolation features112utilize another isolation technology, such as local oxidation of silicon (LOCOS). The isolation features112comprise silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. The isolation features112are formed by a suitable process. As one example, forming a STI includes a photolithography process, etching a trench in the substrate (for example, by using a dry etching and/or wet etching), and filling the trench (for example, by using a chemical vapor deposition process) with one or more dielectric materials. For example, the filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide. In another example, the STI structure may be created using a processing sequence such as: growing a pad oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning an STI opening using photoresist and masking, etching a trench in the substrate, optionally growing a thermal oxide trench liner to improve the trench interface, filling the trench with oxide, using chemical mechanical polishing (CMP) processing to etch back and planarize, and using a nitride stripping process to remove the silicon nitride.

The substrate110includes various doped regions. For example, in the depicted embodiment, the substrate110includes an n-type buried layer, i.e., a deep n-well (DNW) region114. The DNW region114is implanted deeply within the substrate110. For example, the DNW region114is implanted in the substrate110at a depth (d) from a top surface of the substrate110. In the depicted embodiment, the DNW region114is at a depth of about 4 μm to about 6 μm. A thickness (t) of the DNW region114is about 0.5 μm to about 4 μm, and a doping concentration of the DNW region114is about 1×1015atoms/cm3to about 1×1017atoms/cm3. The DNW region114is formed by implanting the substrate110with an n-type dopant, such as phosphorous or arsenic, and subjecting the DNW region114to an annealing process, such as a rapid thermal anneal or laser anneal. Alternatively, the DNW region114is formed by another suitable process, such as a diffusion process

The substrate110also includes p-well (PW) regions116. The PW regions116extend from the top surface of the substrate110a distance (D1) into the substrate110. In the depicted embodiment, the PW regions116extend a distance into the substrate110that is about equal to the depth of the DNW region114, for example, about 4 μm to about 6 μm. The PW regions116are adjacent to the DNW region114, and portions of the PW regions116abut the DNW region114. The PW regions116are formed by implanting the substrate110with a p-type dopant, such as boron, and subjecting the PW regions116to an annealing process, such as a rapid thermal anneal or laser anneal. Alternatively, the PW regions116are formed by another suitable process, such as a diffusion process.

The substrate110includes a native (NTN) region. The native region is a region without p-well or n-well implants, and thus, is free of n-wells or p-wells. The native region is disposed above the DNW region114and between the PW regions116, such that the DNW region114and PW regions116define a boundary of the native region. In the depicted embodiment, the native region includes a diffused region118. The DNW region114defines a bottom of the diffused region118, and the PW regions116define sidewalls of the diffused region118. Put another way, the PW regions116define a perimeter of the diffused region118. In the depicted embodiment, the diffused region118is lightly doped with an n-type dopant, forming lightly doped N— diffusion region118. In the depicted embodiment, the lightly doped N— diffusion region has a doping concentration less than the DNW region114. For example, the lightly doped N— diffusion region118means having a doping concentration of about 1×1015atoms/cm3to about 1×1016atoms/cm3. One skilled in the art will recognize that the terms lightly doped and heavily doped are terms of art that describe a doping concentration of the region depending on the specific device type, technology generation, minimum feature size, and/or other factors. Accordingly, lightly doped and heavily doped should be interpreted in light of the technology being evaluated and not limited to the described embodiments herein. In the depicted embodiment, the lightly doped N— diffusion region118is formed when the DNW region114is subjected to the annealing process. For example, when the DNW region114is subjected to the annealing process, n-type dopants diffuse into the native region, thereby forming the lightly doped N— diffusion region118. The DNW region114can thus alternatively be referred to as a diffusion source. Annealing processes performed on other doped regions and other features of the integrated circuit device100may also cause dopants from the DNW region114to diffuse into the native region, contributing to the forming of the lightly doped N-diffusion region.

Doped regions120,122, and124are also formed in the substrate110. Doped regions120and124are heavily doped with a p-type dopant, such as boron, and doped regions122are heavily doped with an n-type dopant, such as phosphorus or arsenic. Accordingly, the doped regions120and124are referred to as P+ regions120and124, and the doped regions122are referred to as N+ regions. The P+ regions120and124may have a same or different dopant type, doping concentration, and/or doping profile. Each of the doped regions120,122, and124is formed between isolation features112, such that each of the doped regions120,122, and124is isolated from another doped region120,122, or124by the isolation features112. P+ regions120are formed between isolation features112and in the PW regions116, extending from the top surface of the substrate110into the PW regions116. The P+ regions120surround the N+ regions122and P+ regions124. The P+ regions120may be referred to as a P+ guard ring. N+ regions122are formed between isolation regions112and in the N— diffusion region118, extending from the top surface of the substrate110into the N— diffusion region118. P+ regions124are formed in the N-diffusion region118between a metal layer130and isolation feature112, extending from the top surface of the substrate110into the N-diffusion region118. The P+ regions124surround the metal layer130, and may also be referred to as a guard ring.

The metal layer130is disposed over the substrate110between P+ regions124, and is electrically coupled to the lightly doped N— diffusion region118. A Schottky barrier forms at a junction132of the metal layer130and lightly doped N— diffusion region118. In the depicted embodiment, the metal layer130is a metal silicide layer comprising, for example, titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), platinum silicide (PtSi), tantalum silicide (TaSi), other suitable metal silicide materials, or combinations thereof. The metal silicide layer may be formed by a salicide (self-aligned silicidation) process, which includes forming a metal layer (not shown) over the substrate, specifically over the lightly doped N— diffusion region118of the substrate110and performing an annealing process to cause a reaction between the metal layer and the underlying silicon. The annealing process utilizes an elevated temperature that is selected based on the composition of the metal layer. The unreacted metal layer is removed thereafter. Additional thermal processes may be implemented to reduce the resistance of the metal silicide. Alternatively, the metal layer130comprises other metal materials suitable for forming a Schottky barrier, such as tungsten, titanium, chromium, silver, palladium, other suitable metal materials, or combinations thereof.

The integrated circuit device100includes a contact structure that includes contacts140,142,144, and146. The contacts140,142,144, and146include a conductive material, such as titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), copper (Cu), other conductive material, or combinations thereof. In the depicted embodiment, the contacts140,142,144, and146comprise a same size, shape, and material, but alternatively, the contacts140,142,144, and146may differ in size, shape, and/or material depending on design requirements of the integrated circuit device100. The contacts140are electrically coupled with the P+ regions120, the contacts142are electrically coupled with the N+ regions142, the contacts144are electrically coupled with the P+ regions132and metal layer130, and the contact146is electrically coupled with the metal layer130. The contacts140,142,144, and146may be coupled with the various regions via silicide features, such as a metal silicide.

The contacts140,142,144, and146are formed by a suitable process. For example, the contacts140,142, and146may be formed in a not-illustrated interlayer (or inter-level) dielectric (ILD) layer formed over the substrate110. Forming the contacts140,142,144, and146may include patterning and etching the ILD layer to form trenches, partially filling the trenches with a metal barrier layer, such as TiN, and then depositing a contact plug layer, such as W, on the metal barrier layer to fill the trenches. The ILD layer comprises a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS formed oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low-k dielectric materials include fluorinated silica glass (FSG), carbon doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, Calif.), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB (bis-benzocyclobutenes), SiLK® (Dow Chemical, Midland, Mich.), polyimide, or combinations thereof. The ILD layer may alternatively have a multilayer structure having multiple dielectric materials.

The integrated circuit device100may include additional features. For example, various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) may be formed over the substrate110, configured to connect the various features or structures of the integrated circuit device100. The additional features may provide electrical interconnection to the device100. For example, the contacts140,142,144, and146may be coupled with the multiplayer interconnect features. In an example, a multilayer interconnection includes vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may implement various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure.

FIG. 3is a diagrammatic top view of an integrated circuit device200that is an alternative embodiment of the integrated circuit device100ofFIGS. 1 and 2.FIG. 4is a diagrammatic sectional side view of the integrated circuit device200taken along line4-4inFIG. 3. The embodiment ofFIGS. 3 and 4is similar in many respects to the embodiment ofFIGS. 1 and 2. Accordingly, similar features inFIGS. 1-2and3-4are identified by the same reference numerals for clarity and simplicity.FIGS. 3 and 4will be discussed concurrently and have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Accordingly, additional features can be added in the integrated circuit device200, and some of the features described below can be replaced or eliminated for other embodiments of the integrated circuit device200.

The integrated circuit device200is a Schottky diode. The integrated circuit device200does not include the DNW region114as a diffusion source for the native region. Instead, the integrated circuit device200includes n-well (NW) regions250as a diffusion source. The NW regions250extend from the top surface of the substrate110a distance (D2) into the substrate110. In the depicted embodiment, the NW regions250extend from doped regions122. The NW regions250extend a distance into the substrate110that is about the distance the PW regions116extend into the substrate110, for example, about 4 μm to about 6 μm. The NW regions250are laterally spaced a distance, s, from the PW regions116. In the depicted embodiment, a width (w) of the NW regions250is about 0.5 μm to about 3 μm, and a doping concentration of the NW regions250is about 1×1016atoms/cm3to about 1×1018atoms/cm3. The NW regions250are formed by implanting the substrate110with an n-type dopant, such as phosphorous or arsenic. In the depicted embodiment, the NW regions250are subjected to an annealing process, such as a rapid thermal anneal or laser anneal. Alternatively, the NW regions250are formed by another suitable process, such as a diffusion process.

Similar to the integrated circuit device100inFIGS. 1 and 2, the native (NTN) region is disposed between the PW regions116, which define the boundary of the native region. In the depicted embodiment, a diffused region218is disposed in the native region between the NW regions250. The NW regions250are adjacent to the diffused region218. In the depicted embodiment, the diffused region218is lightly doped with an n-type dopant, forming lightly doped N— diffusion region218. The lightly doped N— diffusion region has a doping concentration less than the NW regions250. For example, the lightly doped N— diffusion region218means having a doping concentration of about 1×1015atoms/cm3to about 1×1016atoms/cm3. One skilled in the art will recognize that the terms lightly doped and heavily doped are terms of art that describe a doping concentration of the region depending on the specific device type, technology generation, minimum feature size, and/or other factors. Accordingly, lightly doped and heavily doped should be interpreted in light of the technology being evaluated and not limited to the described embodiments herein. In the depicted embodiment, the lightly doped N— diffusion region218is formed when the NW regions250are subjected to the annealing process. For example, when the NW regions250are subjected to the annealing process, n-type dopants diffuse into the native region, specifically between the NW regions250, thereby forming the lightly doped N— diffusion region218. Annealing processes performed on other doped regions and other features of the integrated circuit device200may also cause dopants from the NW regions250to diffuse into the native region, contributing to the forming of the lightly doped N— diffusion region.

FIG. 5is a diagrammatic top view of an integrated circuit device300that is another alternative embodiment of the integrated circuit device100ofFIGS. 1 and 2.FIG. 6is a diagrammatic sectional side view of the integrated circuit device300taken along line6-6inFIG. 5. The embodiment ofFIGS. 5 and 6is similar in many respects to the embodiments ofFIGS. 1-4. Accordingly, similar features inFIGS. 1-4and5-6are identified by the same reference numerals for clarity and simplicity.FIGS. 5 and 6will be discussed concurrently and have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Accordingly, additional features can be added in the integrated circuit device300, and some of the features described below can be replaced or eliminated for other embodiments of the integrated circuit device300.

The integrated circuit device300is a Schottky diode. The integrated circuit device300includes both the DNW region114and the NW regions250, which both provide a diffusion source for the native region. In the depicted embodiment, the NW regions250extend a distance into the substrate110that is about the depth (d) of the DNW region114, for example, about 4 μm to about 6 μm. The NW regions250are laterally spaced a distance, s, from the PW regions116. Further, in the depicted embodiment, the doping concentration of the NW regions250is about an order higher than the DNW region114. For example, a doping concentration of the DNW region114is about 1×1015atoms/cm3to about 1×1017atoms/cm3, and a doping concentration of the NW regions250is about 1×1016atoms/cm3to about 1×1018atoms/cm3. As noted above, the DNW region114and NW regions250are formed by implanting the substrate110with an n-type dopant, such as phosphorous or arsenic. In the depicted embodiment, the DNW region114and NW regions250are subjected to an annealing process, such as a rapid thermal anneal or laser anneal. Alternatively, the DNW region114and NW regions250are formed by another suitable process, such as a diffusion process.

Similar to the integrated circuit device100inFIGS. 1-2and the integrated circuit device200inFIGS. 3-4, the native (NTN) region is disposed above the DNW region114and between the PW regions116, such that the DNW region114and PW regions116define a boundary of the native region. In the depicted embodiment, the native region includes a diffused region318. The DNW region114defines a bottom of the diffused region318, and the NW regions250define sidewalls of the diffused region318. In the depicted embodiment, the diffused region318is lightly doped with an n-type dopant, forming lightly doped N— diffusion region318. Further, in the depicted embodiment, and the lightly doped N— diffusion region318has a doping concentration less than the NW regions250and DNW region114. For example, the lightly doped N— diffusion region318means having a doping concentration of about 1×1015atoms/cm3to about 1×1016atoms/cm3. One skilled in the art will recognize that the terms lightly doped and heavily doped are terms of art that describe a doping concentration of the region depending on the specific device type, technology generation, minimum feature size, and/or other factors. Accordingly, lightly doped and heavily doped should be interpreted in light of the technology being evaluated and not limited to the described embodiments herein. In the depicted embodiment, the lightly doped N— diffusion region318is formed when the DNW region114and NW regions250are subjected to the annealing processes. For example, when the DNW region114and NW regions250are subjected to the annealing processes, n-type dopants diffuse into the native region, specifically between the NW regions250, thereby forming the lightly doped N— diffusion region318. Annealing processes performed on other doped regions and other features of the integrated circuit device300may also cause dopants from the DNW region214and NW regions250to diffuse into the native region, contributing to the forming of the lightly doped N-diffusion region.

FIG. 7is a flow chart of a method400for fabricating an integrated circuit device according to various aspects of the present disclosure. The method400begins at block402where a semiconductor substrate is provided. At block404, various doped regions are formed in the semiconductor substrate. At block406, an annealing process is performed on the various doped regions, thereby forming a lightly doped diffusion region in the semiconductor substrate. At block408, a conductive layer is formed that contacts the lightly doped diffusion region. A junction of the conductive layer and the lightly doped diffusion region forms a Schottky region. At block410, fabrication of the integrated circuit device is completed. Additional steps can be provided before, during, and after the method400, and some of the steps described can be replaced or eliminated for other embodiments of the method.

The method400can be implemented to fabricate the integrated circuit device100described above. For example, referring toFIGS. 1 and 2, at block402, the substrate110is provided. At block404, the DNW region114is formed by implanting n-dopants, such as phosphorous or arsenic, at the depth (d) in the substrate110. After forming the DNW region114, the PW regions116are formed by implanting the substrate110with p-type dopants, such as boron. In the depicted embodiment, the doped regions120,122, and124are formed by a diffusion process. The isolation features112may be formed at any time to isolate the various features of the integrated circuit device100. For example, the isolation features112are formed after the DNW region114and PW regions116, but before the doped regions120,122, and124. At block406, an annealing process is performed and n-type dopants from the DNW region114diffuse into a native region of the substrate110to form the lightly doped N— diffused region118. In the depicted embodiment, the annealing process is a thermal annealing process at a temperature of about 850° C. to about 1,100° C. for a time of about 30 minutes to about an hour. Other temperatures and times may be used to achieve particular characteristics of the lightly doped N— diffusion region118. As noted above, annealing processes performed on the other doped regions, such as the PW regions116and doped regions120,122, and124, may also cause dopants from the DNW region114to diffuse into the native region, contributing to forming the lightly doped N— diffused region118. Accordingly, the annealing processes to form the integrated circuit device100are tuned (for example, temperature and time of each of the annealing processes) to ensure that the lightly doped N— diffused region118in the completed integrated circuit device100exhibits the desired doping concentration, doping profile, and/or electrical characteristics. At block408, the metal layer130is formed, providing a Schottky barrier at junction132of the metal layer130and lightly doped N— diffusion region118. At block410, fabrication of the integrated circuit device100is completed. For example, an interconnection structure including various metal and dielectric layer may be formed over the substrate110. For example, in the depicted embodiment, the various contacts140,142,144, and146are formed in a dielectric layer (not illustrated) over the substrate110, and coupled with various features of the integrated circuit device100.

The method400can also be implemented to fabricate the integrated circuit device200described above. For example, referring toFIGS. 3 and 4, at block402, the substrate110is provided. At block404, the PW regions116are formed by implanting the substrate110with p-type dopants, such as boron. The NW regions250are formed by implanting the substrate110with n-type dopants. In the depicted embodiment, the doped regions120,122, and124are formed by a diffusion process. The isolation features112may be formed at any time to isolate the various features of the integrated circuit device200. For example, the isolation features112are formed after the PW regions116and NW regions250, but before the doped regions120,122, and124. At block406, an annealing process is performed, and n-type dopants from the NW regions250diffuse into a native region of the substrate110to form the lightly doped N— diffused region218. In the depicted embodiment, the annealing process is a thermal annealing process at a temperature of about 850° C. to about 1,100° C. for a time of about 30 minutes to about an hour. Other temperatures and times may be used to achieve particular characteristics of the lightly doped N— diffusion region218. It should be noted that annealing processes performed on the other doped regions, such as the PW regions116and doped regions120,122, and124, may also cause dopants from the NW regions250to diffuse into the native region to form the lightly doped N— diffused region218. Accordingly, the annealing processes to form the integrated circuit device200are tuned (for example, temperature and time of each of the annealing processes) to ensure that the lightly doped N— diffused region218in the completed integrated circuit device200exhibits the desired doping concentration, doping profile, and/or electrical characteristics. At block408, the metal layer130is formed, providing a Schottky barrier at junction132of the metal layer130and lightly doped N— diffusion region218. At block410, fabrication of the integrated circuit device200is completed. For example, an interconnection structure including various metal and dielectric layer may be formed over the substrate110. For example, in the depicted embodiment, the various contacts140,142,144, and146are formed in a dielectric layer (not illustrated) over the substrate110, and coupled with various features of the integrated circuit device200.

The method400can also be implemented to fabricate the integrated circuit device300described above. For example, referring toFIGS. 5 and 6, at block402, the substrate110is provided. At block404, the DNW region114is formed by implanting n-dopants, such as phosphorous or arsenic, at the depth (d) in the substrate110. After forming the DNW region114, the PW regions116are formed by implanting the substrate110with p-type dopants, such as boron, and the NW regions250are formed by implanting the substrate110with n-type dopants. In the depicted embodiment, the doped regions120,122, and124are formed by a diffusion process. The isolation features112may be formed at any time to isolate the various features of the integrated circuit device200. For example, the isolation features112are formed after the DNW region114, PW regions116, and NW regions250, but before the doped regions120,122, and124. At block406, an annealing process is performed, and n-type dopants from the DNW region114and NW regions250diffuse into a native region of the substrate110to form the lightly doped N— diffused region318. In the depicted embodiment, the annealing process is a thermal annealing process at a temperature of about 850° C. to about 1,100° C. for a time of about 30 minutes to about an hour. Other temperatures and times may be used to achieve particular characteristics of the lightly doped N— diffusion region318. It should be noted that annealing processes performed on the other doped regions, such as the PW regions116and doped regions120,122, and124, may also cause dopants from the DNW region214and NW regions250to diffuse into the native region to form the lightly doped N— diffused region318. Accordingly, the annealing processes to form the integrated circuit device300are tuned (for example, temperature and time of each of the annealing processes) to ensure that the lightly doped N— diffused region318in the completed integrated circuit device300exhibits the desired doping concentration, doping profile, and/or electrical characteristics. At block408, the metal layer130is formed, providing a Schottky barrier at junction132of the metal layer130and lightly doped N— diffusion region218. At block410, fabrication of the integrated circuit device300is completed. For example, an interconnection structure including various metal and dielectric layer may be formed over the substrate110. For example, in the depicted embodiment, the various contacts140,142,144, and146are formed in a dielectric layer (not illustrated) over the substrate110, and coupled with various features of the integrated circuit device300.

The foregoing description discloses Schottky devices that exhibit improved performance by implementing a conductive layer in contact with a lightly doped diffusion region (such as the lightly doped N— diffusion regions118,218, and/or318described above) to form a Schottky barrier. The lightly doped diffusion region reduces a doping concentration at a junction of the conductive layer/lightly doped diffusion region, leading to increased breakdown voltages (VBD) and decreased leakage current of the disclosed Schottky devices. The wells of the same conductivity type adjacent to the lightly doped diffusion regions (for example, NW regions250) can reduce parasitic resistance exhibited by the Schottky devices. Further, the Schottky devices disclosed above (integrated circuit device100,200, and/or300) are easily formed on a same wafer using standard CMOS processes without implementing extra processing (such as extra masking steps) and/or costs. This allows Schottky devices having varying breakdown voltages and turn on voltages to be easily manufactured on a single integrated circuit device. Different embodiments may have different advantages, and no particular advantage is necessarily required of any one embodiment.

The present disclosure provides for many different embodiments. In an example, an integrated circuit device includes a semiconductor substrate having a top surface and a bottom surface; a lightly doped diffusion region disposed in the semiconductor substrate; a first well extending from the top surface into the semiconductor substrate, the first well surrounding the lightly doped diffusion region; a second well disposed in the semiconductor substrate, the second well disposed below the lightly doped diffusion region and partially abutting a bottom portion of the first well; and a conductive layer disposed adjacent to the lightly doped diffusion region, wherein a Schottky region is formed at a junction of the conductive layer and the lightly doped diffusion region. The semiconductor substrate and the first well are a first conductivity type. The lightly doped diffusion region and second well are a second conductivity type. A doping concentration of the lightly doped diffusion region may be less than a doping concentration of the second well. The integrated circuit device can further include a third well of the second conductivity type extending from the top surface into the semiconductor substrate to the second well, wherein the third well defines sidewalls of the lightly doped diffusion region. In an example, the lightly doped diffusion region is a lightly doped N— region, the first well is a deep n-well (DNW), and the second well is a p-well (PW).

The integrated circuit device can further include a first doped region of the first conductivity type disposed in the lightly doped diffusion region and adjacent to the top surface of the substrate, the first doped region surrounding the conductive layer. An isolation feature may be disposed in the substrate between the first doped region and a second doped region of the second conductivity type, the second doped region being disposed in the lightly doped diffusion region and adjacent to the top surface of the substrate. The integrated circuit device may further include a third doped region of the first conductivity type disposed in the first well and adjacent to the top surface of the substrate. Another isolation feature may be disposed in the substrate between the second and third doped regions. In an example, the first, second, and third doped regions are heavily doped diffusion regions. A contact structure may be coupled with the conductive layer, first doped region, second doped region, and third doped region.

In another example, an integrated circuit device includes a semiconductor substrate having a top surface and a bottom surface; a lightly doped diffusion region disposed in the substrate; a first well and a second well extending from the top surface into the semiconductor substrate, the lightly doped diffusion region being disposed between the first and second wells; a third well extending from the top surface into the semiconductor substrate, the third well surrounding the first and second wells; and a conductive layer disposed adjacent to the lightly doped diffusion region, wherein a Schottky region is formed at a junction of the conductive layer and the lightly doped diffusion region. The semiconductor substrate and the third well are a first conductivity type. The lightly doped diffusion region, first well, and second well are a second conductivity type. The integrated circuit device can further include a fourth well of the second conductivity type disposed in the semiconductor substrate below the lightly doped diffusion region and partially abutting a bottom portion of the third well. The first and second wells may extend from the top surface of the semiconductor substrate to the fourth well. The integrated third well may be laterally spaced a distance from the first and second wells.

The first and second wells may have a doping concentration of at least an order higher than the fourth well. For example, the first and second wells may have a doping concentration of about 1×1016atoms/cm3to about 1×1018atoms/cm3, the fourth well has a doping concentration of about 1×1015atoms/cm3to about 1×1017atoms/cm3, and the lightly doped diffusion region has a doping concentration of about 1×1015atoms/cm3to about 1×1016atoms/cm3. In an example, the lightly doped diffusion region is a lightly doped N— region, the first and second wells are n-wells (NW), the third well is a p-well (PW), and the fourth well is a deep n-well (DNW).

The integrated circuit device may further include a first doped region disposed in the lightly doped diffusion region and adjacent to the top surface of the substrate, the first doped region surrounding the conductive layer; a second doped disposed in the first and second wells and adjacent to the top surface of the substrate, the second doped region having a first portion surrounded by the first well and a second portion surrounded by the second well; and a third doped region disposed in the third well and adjacent to the top surface of the substrate. The first and third doped regions may be the first conductivity type, and the second doped region may be the second conductivity type. An isolation feature may be disposed between the first and second doped regions, and an isolation feature disposed between the second and third doped regions.

In yet another example, a method includes providing a semiconductor substrate having a top surface and a bottom surface, the semiconductor substrate being a first conductivity type; forming a first well and a second well of a second conductivity type extending from the top surface into the semiconductor substrate; forming a third well of the first conductivity type extending from the top surface into the semiconductor substrate, the third well surrounding the first and second wells; performing an annealing process to form a lightly doped diffusion region disposed in the semiconductor substrate between the first and second wells, the lightly doped diffusion region being doped with the second conductivity type; and forming a conductive layer adjacent to the lightly doped diffusion region, wherein a junction of the conductive layer and the lightly doped diffusion region forms a Schottky region. The annealing process may be tuned so that dopants diffuse from the first and second wells to form the lightly doped diffusion region. In an example, the method may further include forming a fourth well of the second conductivity type disposed in the semiconductor substrate and partially abutting a bottom portion of the third well, wherein the first and second wells extend from the top surface of the semiconductor substrate to the fourth well, and wherein the lightly doped diffusion region is disposed above the fourth well. In this example, the annealing process may be tuned so that dopants diffuse from the first, second, and fourth wells to form the lightly doped diffusion region.