SEMICONDUCTOR INTEGRATED CIRCUIT AND RECEIVER DEVICE

A semiconductor integrated circuit includes a first input terminal inputting a first signal, a second input terminal supplied to a first voltage, an output terminal outputting a second signal. The circuit includes: a first transistor having first, second, control terminals respectively connected to a first node, the output terminal and first input terminals; a second transistor having first, second, control terminals respectively connected to the first and second nodes, the output terminal; a third transistor having a first terminal supplied to a second voltage, second and control terminals respectively connected to the first node and the second input terminal; a fourth transistor having first and control terminals respectively connected to the output terminal and the second node, a second terminal supplied to a third voltage; and a fifth transistor having first and control terminals connected to the second node, and a second terminal supplied to the third voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-041277, filed Mar. 15, 2023, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor integrated circuit and a receiver device.

BACKGROUND

A transmitter device and a receiver device are connected via a transmission path. The transmitter device superimposes data on an analog signal and outputs the analog signal. The receiver device receives the analog signal that has passed through the transmission path. The receiver device includes a semiconductor integrated circuit that processes the analog signal. The receiver device generates a digital signal based on the analog signal. The receiver device recovers the data based on the generated digital signal.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor integrated circuit includes a first buffer having a first input terminal to which a first signal is input, a second input terminal to which a first voltage is supplied, and a first output terminal from which a second signal is output. The first buffer includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor has a first terminal connected to a first node, a second terminal connected to the first output terminal, and a control terminal connected to the first input terminal. The second transistor has a first terminal connected to the first node, a second terminal connected to a second node, and a control terminal connected to the first output terminal. The third transistor has a first terminal to which a second voltage is supplied, a second terminal connected to the first node, and a control terminal connected to the second input terminal. The fourth transistor has a first terminal connected to the first output terminal, a second terminal to which a third voltage is supplied, and a control terminal connected to the second node. The fifth transistor has a first terminal and a control terminal each connected to the second node, and a second terminal to which the third voltage is supplied.

Note that, in the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. In a case where elements having similar configurations are particularly distinguished from each other, letters or numbers different from each other may be added to the ends of the same reference numerals.

An embodiment will be described.

1.1 Communication System

A configuration of a communication system including a receiver device according to the embodiment will first be described.FIG.1is a block diagram illustrating an example of a configuration of the communication system including the receiver device according to the embodiment.

A communication system1is configured to transmit data from one device or circuit to another device or circuit by high-speed serial communication. Specifically, for example, the communication system1achieves a communication speed of 128 Gbps. The communication system1includes a transmitter device2, a transmission path3, and a receiver device4. The communication system1may be constituted by a plurality of devices or circuits provided on the same printed circuit board, or may be constituted by a plurality of devices or circuits provided on different printed circuit board.

The transmitter device2is configured to transmit signals TR and /TR to the receiver device4via the transmission path3. The signals TR and /TR are differential signals. The signals TR and /TR are, for example, signals including a plurality of pulse signals. Data is superimposed on each pulse signal of the signals TR and /TR. The voltage level of each pulse signal of the signals TR and /TR corresponds to data of one or more bits. The data superimposed on the pulse signal is transmitted from the transmitter device2to the receiver device4via the transmission path3.

The transmission path3is a physical or spatial transmission medium for transmitting the signals TR and /TR to the receiver device4. The transmission path3is, for example, wiring that connects the transmitter device2and the receiver device4. The transmission path3may have various transmission characteristics depending on the structure and material of the transmission medium. The transmission characteristics of the transmission path3have, for example, a frequency characteristic with a loss of gain in a specific frequency band.

The signals TR and /TR transmitted by the transmitter device2pass through the transmission path3, thereby suffering a loss corresponding to the transmission characteristics of the transmission path3. Thus, inter-symbol interference (ISI) occurs in the signals TR and /TR that have passed through the transmission path3. Therefore, the signals TR and /TR that have passed through the transmission path3are processed as analog signals in an initial stage circuit of the receiver device4. In the following, the signals TR and /TR that have passed through the transmission path3and have suffered loss are referred to as signals RV and /RV.

The receiver device4is configured to receive the signals RV and /RV from the transmitter device2via the transmission path3. The receiver device4decodes the data superimposed on the signals TR and /TR by the transmitter device2based on the signals RV and /RV. The receiver device4has a receiver circuit for correctly decoding data superimposed on the signals TR and /TR. The receiver circuit may be referred to as a semiconductor integrated circuit.

1.2 Receiver Circuit

FIG.2is a block diagram illustrating an example of a configuration of a receiver circuit of the receiver device according to the embodiment.

The receiver device4includes, for example, pads P1and P2, a AFE10, a TI-ADC20, a VREFGEN30, a DSP40, and a CDR50as a receiver circuit.

Each of the pads P1and P2is a terminal connected to the transmission path3. The example ofFIG.2illustrates a case where the pads P1and P2receive the signals RV and /RV, respectively, from the transmitter device2via the transmission path3.

The AFE10is an analog front end. The AFE10includes, for example, a continuous time linear equalizer (CTLE) and a variable gain amplifier (VGA). The CTLE is an amplifier circuit having a frequency characteristic that compensates for the frequency characteristic of the transmission path3. The VGA is an amplifier circuit capable of changing a gain. The signals RV and /RV are input to the AFE10from the pads P1and P2, respectively. The AFE10performs analog processing on the signals RV and /RV using the CTLE and the VGA. The AFE10generates signals Sin and /Sin based on the signals RV and /RV. In other words, the signals Sin and /Sin are analog signals, as are the signals RV and /RV. The AFE10outputs the signals Sin and /Sin to the TI-ADC20.

The TI-ADC20is a time-interleaved AD converter. In the communication system1that achieves 128 Gbps, in a case where the bit depth is 2 bits, the TI-ADC20achieves, for example, a sampling rate of 64 GS/s. In this case, the Nyquist frequency of the TI-ADC20is 32 GHz. The TI-ADC20performs a process of converting an analog signal to a digital signal. The signals Sin and /Sin are input to the TI-ADC20from the AFE10. A bias voltage VB and reference voltages VRp and VRn (VRp/n) are input to the TI-ADC20from the VREFGEN30. Signals CK1and CK2are input to the TI-ADC20from the CDR50. The TI-ADC20converts the signals Sin and /Sin to a signal X0based on the reference voltages VRp and VRn, and the signals CK1and CK2. The TI-ADC20outputs the signal X0to the DSP40. The configuration of the TI-ADC20will be described later.

The bias voltage VB is a voltage used in a process of buffering an analog signal in the TI-ADC20.

The reference voltages VRp and VRn are voltages used in the process of converting the analog signal to the digital signal in the TI-ADC20. The TI-ADC20generates the signal X0based on the magnitude relation between the potential difference between the signals Sin and /Sin and the potential difference (VRp−VRn) between the reference voltages VRp and VRn.

The signal CK1includes nr1clock signals. nr1is an integer greater than or equal to 1 (e.g., 8). The nr1clock signals of the signal CK1differ in phase by at least 360°/nr1, for example. In the following, the nr1clock signals in the signal CK1may be indicated by being distinguished as in signals CK1_0, . . . , and CK1_nr1−1). The frequency of the signal CK1is equal to or lower than the frequency of clock signal embedded in the signals TR and /TR by the transmitter device2.

The signal CK2includes nr2clock signals. nr2is an integer greater than nr1(e.g.,32). The nr2clock signals of the signal CK2differ in phase by at least 360°/nr2, for example. In the following, the nr2clock signals in the signal CK2may be indicated by being distinguished as in signals CK2_0, . . . , and CK2_(nr2−1). The frequency of the signal CK2is lower than the clock signal embedded in the signals TR and /TR by the transmitter device2.

The signal X0output by the TI-ADC20is a digital signal. The signal X0includes a plurality of consecutive digital values. One digital value included in the signal X0is sampled from one symbol of the signals Sin and /Sin based on one clock signal (specifically, an edge of the clock signal) of the signal CK2. One digital value is, for example, 8-bit data. The value of each bit of the nr2consecutive digital values included in the signal XC is sampled from the nr2consecutive symbols of the signals Sin and /Sin based on the nr2clock signals of the signal CK2. In the following, the generation period of the nr2consecutive digital values included in the signal X0by the TI-ADC20is also simply referred to as a “period”. The nr2consecutive digital values included in the signal X0are also referred to as a “signal X0for one period”.

In addition, the nr2consecutive digital values included in the signal X0may be indicated by being distinguished as in digital values X0_0, . . . , and X0_(nr2−1). The 8-bit data string included in the digital value X0_jmay be indicated as in a bit string X0_j<7:0> (0≤j≤nr2−1). Note that the bit string X0_j<7:0> means a data string in which eight bits from the most significant bit (MSB)X0_j<7> to the least significant bit (LSB)X0_j<0> are arranged in order.

The VREFGEN30is a voltage generator. The VREFGEN30is configured to generate a bias voltage VB and reference voltages VRp and VRn.

The DSP40is a digital signal processor. The DSP40includes, for example, a feed forward equalizer (FFE), a decision feedback equalizer (DFE), and a data determination circuit. The signal XC is input to the DSP40. The DSP40performs digital processing on the signal XC using, for example, the FFE, DFE, and data determination circuit. Specifically, the DSP40generates a signal X and data A based on the signal XC. The DSP40outputs the signal X and the data A to the CDR50. The DSP40outputs the signal X and data A to a subsequent processing circuit (not illustrated). In the subsequent processing circuit, the signal X and the data A are processed. The signal X and the data A output to the CDR50and the signal X and the data A output to the subsequent processing circuit (not illustrated) may be the same signals or different signals, respectively.

The signal X is a digital signal, as is the signal X0. The signal X for one period is a set of nr2digital values. The data A is data decoded based on the signal X.

The CDR50is a clock data recovery circuit. The signal X and the data A are input to the CDR50in each period. For example, a reference clock signal CKREF is input to the CDR50from the transmitter device2. The reference clock signal CKREF may be generated in the CDR50or in the receiver device4independently of the transmitter device2. The CDR50calculates phase correction amount of the signals CK1and CK2based on the reference clock signal CKREF and the signal X and the data A. The CDR50recovers the signals CK1and CK2based on the calculated phase correction amount. The CDR50outputs the recovered signals CK1and CK2to the TI-ADC20in each period. As described above, the CDR50recovers the signals CK1and CK2serving as the reference of the sampling timing of the subsequent signal X0for one period, based on the signal X and data A which are generated from the signal X0for one period. Such cyclical processing for each period by the TI-ADC20, the DSP40, and the CDR50is also referred to as a “CDR loop”.

In the following, a case where (8,32) is applied as a specific combination of (nr1, nr2) will be described.

1.3 AD Converter

The internal configuration of the AD converter (TI-ADC) included in the receiver circuit according to the embodiment will now be described.FIG.3is a block diagram illustrating an example of the configuration of the AD converter included in the receiver circuit according to the embodiment.

The TI-ADC20includes an SFE21and a plurality of SAR-ADCs22. The plurality of SAR-ADCs22includes 32 SAR-ADCs22_0, . . . , and22_31. In the example ofFIG.3, the four SAR-ADCs22_0,22_8,22_16, and22_24are indicated as “SAR-ADC22_0+8k” (0≤k≤3). Similarly, the four SAR-ADCs22_1,22_9,22_17, and22_25are indicated as “SAR-ADC22_1+8k”. The four SAR-ADCs22_2,22_10,22_18, and22_26are indicated as “SAR-ADC22_2+8k”. The four SAR-ADCs22_3,22_11,22_19, and22_27are indicated as “SAR-ADC22_3+8k”. The four SAR-ADCs22_4,22_12,22_20, and22_28are indicated as “SAR-ADC22_4+8k”. The four SAR-ADCs22_5,22_13,22_21, and22_29are indicated as “SAR-ADC22_5+8k”. The four SAR-ADCs22_6,22_14,22_22, and22_30are indicated as “SAR-ADC22_6+8k”. The four SAR-ADCs22_7,22_15,22_23, and22_31are indicated as “SAR-ADC22_7+8k”.

The SFE21is a sampling front end. The bias voltage VB is supplied to the SFE21. The SFE21includes a plurality of buffers BF, a plurality of switching elements SW, and a plurality of capacitors CP. The plurality of buffers BF includes four first-stage buffers BF_a, BF_b, BF_c, and BF_d, and eight second-stage buffers BF_0, BF_1, BF_2, BF_3, BF_4, BF_5, BF_6, and BF_7. Each of the four first-stage buffers BF_a to BF_d and each of the eight second-stage buffers BF_0to BF_7has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The plurality of switching elements SW includes eight switching element groups SW_0, SW_1, SW_2, SW_3, SW_4, SW_5, SW_6, and SW_7. Each of the eight switching element groups SW_0to SW_7includes two switching elements. The plurality of capacitors CP includes eight capacitor groups CP_0, CP_1, CP_2, CP_3, CP_4, CP_5, CP_6, and CP_7. Each of the eight capacitor groups CP_0to CP_7includes two capacitors. The four first-stage buffers BF_a to BF_d and the eight second-stage buffers BF_0to BF_7may each have an equivalent configuration. In the following, in a case where each of the four first-stage buffers BF_a to BF_d and each of the eight second-stage buffers BF_0to BF_7are not distinguished from each other, these buffers are simply referred to as “buffers BF”.

A signal Sin is input to the first input terminal of each of the first-stage buffers BF_a to BF_d. A signal /Sin is input to the second input terminal of each of the first-stage buffers BF_a to BF_d.

A voltage VOP_a is output from the first output terminal of the first-stage buffer BF_a. The first output terminal of the first-stage buffer BF_a is connected to respective first terminals of one of the switching elements in the switching element group SW_0and one of the switching elements in the switching element group SW_4. A voltage VON_a is output from the second output terminal of the first-stage buffer BF_a. The second output terminal of the first-stage buffer BF_a is connected to respective first terminals of the other of the switching elements in the switching element group SW_0and the other of the switching elements in the switching element group SW_4.

A voltage VOP_b is output from the first output terminal of the first-stage buffer BF_b. The first output terminal of the first-stage buffer BF_b is connected to respective first terminals of one of the switching elements in the switching element group SW_2and one of the switching elements in the switching element group SW_6. A voltage VON_b is output from the second output terminal of the first-stage buffer BF_b. The second output terminal of the first-stage buffer BF_b is connected to respective first terminals of the other of the switching elements in the switching element group SW_2and the other of the switching elements in the switching element group SW_6.

A voltage VOP_c is output from the first output terminal of the first-stage buffer BF_c. The first output terminal of the first-stage buffer BF_c is connected to respective first terminals of one of the switching elements in the switching element group SW_1and one of the switching elements in the switching element group SW_5. A voltage VON_c is output from the second output terminal of the first-stage buffer BF_c. The second output terminal of the first-stage buffer BF_c is connected to respective first terminals of the other of the switching elements in the switching element group SW_1and the other of the switching elements in the switching element group SW_5.

A voltage VOP_d is output from the first output terminal of the first-stage buffer BF_d. The first output terminal of the first-stage buffer BF_d is connected to respective first terminals of one of the switching elements in the switching element group SW_3and one of the switching elements in the switching element group SW_7. A voltage VON_d is output from the second output terminal of the first-stage buffer BF_d. The second output terminal of the first-stage buffer BF_d is connected to respective first terminals of the other of the switching elements in the switching element group SW_3and the other of the switching elements in the switching element group SW_7.

A second terminal of one of the switching elements in the switching element group SW_0is connected to a first terminal of one of the capacitors in the capacitor group CP_0and the first input terminal of the second-stage buffer BF_0. A second terminal of the other of the switching elements in the switching element group SW_0is connected to a first terminal of the other of the capacitors in the capacitor group CP_0and the second input terminal of the second-stage buffer BF_0. A second terminal of each of the two capacitors in the capacitor group CP_0is grounded. Being grounded means being connected to wiring to which a reference potential (e.g., a voltage AVSS=0 V) is applied when the SFE21operates. In a case where the signal CK1_0is at the “H” level, the switching element group SW_0is turned on. In a case where the signal CK1_0is at the “L” level, the switching element group SW_0is turned off.

A second terminal of one of the switching elements in the switching element group SW_1is connected to a first terminal of one of the capacitors in the capacitor group CP_1and the first input terminal of the second-stage buffer BF_1. A second terminal of the other of the switching elements in the switching element group SW_1is connected to a first terminal of the other of the capacitors in the capacitor group CP_1and the second input terminal of the second-stage buffer BF_1. A second terminal of each of the two capacitors in the capacitor group CP_1is grounded. In a case where the signal CK1_1is at the “H” level, the switching element group SW_1is turned on. In a case where the signal CK1_1is at the “L” level, the switching element group SW_1is turned off.

A second terminal of one of the switching elements in the switching element group SW_2is connected to a first terminal of one of the capacitors in the capacitor group CP_2and the first input terminal of the second-stage buffer BF_2. A second terminal of the other of the switching elements in the switching element group SW_2is connected to a first terminal of the other of the capacitors in the capacitor group CP_2and the second input terminal of the second-stage buffer BF_2. A second terminal of each of the two capacitors in the capacitor group CP_2is grounded. In a case where the signal CK1_2is at the “H” level, the switching element group SW_2is turned on. In a case where the signal CK1_2is at the “L” level, the switching element group SW_2is turned off.

A second terminal of one of the switching elements in the switching element group SW_3is connected to a first terminal of one of the capacitors in the capacitor group CP_3and the first input terminal of the second-stage buffer BF_3. A second terminal of the other of the switching elements in the switching element group SW_3is connected to a first terminal of the other of the capacitors in the capacitor group CP_3and the second input terminal of the second-stage buffer BF_3. A second terminal of each of the two capacitors in the capacitor group CP_3is grounded. In a case where the signal CK1_3is at the “H” level, the switching element group SW_3is turned on. In a case where the signal CK1_3is at the “L” level, the switching element group SW_3is turned off.

A second terminal of one of the switching elements in the switching element group SW_4is connected to a first terminal of one of the capacitors in the capacitor group CP_4and the first input terminal of the second-stage buffer BF_4. A second terminal of the other of the switching elements in the switching element group SW_4is connected to a first terminal of the other of the capacitors in the capacitor group CP_4and the second input terminal of the second-stage buffer BF_4. A second terminal of each of the two capacitors in the capacitor group CP_4is grounded. In a case where the signal CK1_4is at the “H” level, the switching element group SW_4is turned on. In a case where the signal CK1_4is at the “L” level, the switching element group SW_4is turned off.

A second terminal of one of the switching elements in the switching element group SW_5is connected to a first terminal of one of the capacitors in the capacitor group CP_5and the first input terminal of the second-stage buffer BF_5. A second terminal of the other of the switching elements in the switching element group SW_5is connected to a first terminal of the other of the capacitors in the capacitor group CP_5and the second input terminal of the second-stage buffer BF_5. A second terminal of each of the two capacitors in the capacitor group CP_5is grounded. In a case where the signal CK1_5is at the “H” level, the switching element group SW_5is turned on. In a case where the signal CK1_5is at the “L” level, the switching element group SW_5is turned off.

A second terminal of one of the switching elements in the switching element group SW_6is connected to a first terminal of one of the capacitors in the capacitor group CP_6and the first input terminal of the second-stage buffer BF_6. A second terminal of the other of the switching elements in the switching element group SW_6is connected to a first terminal of the other of the capacitors in the capacitor group CP_6and the second input terminal of the second-stage buffer BF_6. A second terminal of each of the two capacitors in the capacitor group CP_6is grounded. In a case where the signal CK1_6is at the “H” level, the switching element group SW_6is turned on. In a case where the signal CK1_6is at the “L” level, the switching element group SW_6is turned off.

A second terminal of one of the switching elements in the switching element group SW_7is connected to a first terminal of one of the capacitors in the capacitor group CP_7and the first input terminal of the second-stage buffer BF_7. A second terminal of the other of the switching elements in the switching element group SW_7is connected to a first terminal of the other of the capacitors in the capacitor group CP_7and the second input terminal of the second-stage buffer BF_7. A second terminal of each of the two capacitors in the capacitor group CP_7is grounded. In a case where the signal CK1_7is at the “H” level, the switching element group SW_7is turned on. In a case where the signal CK1_7is at the “L” level, the switching element group SW_7is turned off.

The voltages VOP_0and VON_0are output from the first output terminal and the second output terminal of the second-stage buffer BF_0, respectively. Each of the first output terminal and the second output terminal of the second-stage buffer BF_0is connected to the SAR-ADCs22_0,22_8,22_16, and22_24.

The voltages VOP_1and VON_1are output from the first output terminal and the second output terminal of the second-stage buffer BF_1, respectively. Each of the first output terminal and the second output terminal of the second-stage buffer BF_1is connected to the SAR-ADCs22_1,22_9,22_17, and22_25.

The voltages VOP_2and VON_2are output from the first output terminal and the second output terminal of the second-stage buffer BF_2, respectively. Each of the first output terminal and the second output terminal of the second-stage buffer BF_2is connected to the SAR-ADCs22_2,22_10,22_18, and22_26.

The voltages VOP_3and VON_3are output from the first output terminal and the second output terminal of the second-stage buffer BF_3, respectively. Each of the first output terminal and the second output terminal of the second-stage buffer BF_3is connected to the SAR-ADCs22_3,22_11,22_19, and22_27.

The voltages VOP_4and VON_4are output from the first output terminal and the second output terminal of the second-stage buffer BF_4, respectively. Each of the first output terminal and the second output terminal of the second-stage buffer BF_4is connected to the SAR-ADCs22_4,22_12,22_20, and22_28.

The voltages VOP_5and VON_5are output from the first output terminal and the second output terminal of the second-stage buffer BF_5, respectively. Each of the first output terminal and the second output terminal of the second-stage buffer BF_5is connected to the SAR-ADCs22_5,22_13,22_21, and22_29.

The voltages VOP_6and VON_6are output from the first output terminal and the second output terminal of the second-stage buffer BF_6, respectively. Each of the first output terminal and the second output terminal of the second-stage buffer BF_6is connected to the SAR-ADCs22_6,22_14,22_22, and22_30.

The voltages VOP_7and VON_7are output from the first output terminal and the second output terminal of the second-stage buffer BF_7, respectively. Each of the first output terminal and the second output terminal of the second-stage buffer BF_7is connected to the SAR-ADCs22_7,22_15,22_23, and22_31.

With the above-described configuration, the second-stage buffer BF_0receives the voltages VOP_a and VON_a and outputs the voltages VOP_0and VON_0, at the timing when the signal CK1_0has an “H” level. The second-stage buffer BF_1receives the voltages VOP_c and VON_c and outputs the voltages VOP_1and VON_1, at the timing when the signal CK1_1has an “H” level. The second-stage buffer BF_2receives the voltages VOP_b and VON_b and outputs the voltages VOP_2and VON_2, at the timing when the signal CK1_2has an “H” level. The second-stage buffer BF_3receives the voltages VOP_d and VON_d and outputs the voltages VOP_3and VON_3, at the timing when the signal CK1_3has an “H” level. The second-stage buffer BF_4receives the voltages VOP_a and VON_a and outputs the voltages VOP_4and VON_4, at the timing when the signal CK1_4has an “H” level. The second-stage buffer BF_5receives the voltages VOP_c and VON_c and outputs the voltages VOP_5and VON_5, at the timing when the signal CK1_5has an “H” level. The second-stage buffer BF_6receives the voltages VOP_b and VON_b and outputs the voltages VOP_6and VON_6, at the timing when the signal CK1_6has an “H” level. The second-stage buffer BF_7receives the voltages VOP_d and VON_d and outputs the voltages VOP_7and VON_7, at the timing when the signal CK1_7has an “H” level.

Each of the SAR-ADC22_0to the SAR-ADC22_31is a successive approximation register AD converter. The signals CK2_0to CK2_31are input to the SAR-ADC22_0to the SAR-ADC22_31, respectively. The reference voltages VRp and VRn are supplied to each of the SAR-ADC22_0to the SAR-ADC22_31via different wiring, respectively. The SAR-ADC22_0to the SAR-ADC22_31output the signals X0_0to X0_31, respectively, based on the signals CK2_0to CK2_31, and the reference voltages VRp and VRn, which are respectively correspondingly input. The SAR-ADC22_0to SAR-ADC22_31each have an equivalent configuration.

FIG.4is a block diagram illustrating an example of the configuration of the buffer included in the AD converter according to the embodiment.FIG.4illustrates, as an example, a configuration of one buffer BF among the first-stage buffers BF_a to BF_d and the second-stage buffers BF_0to BF_7, which have equivalent configurations.

The buffer BF functions as a differential input buffer. Specifically, the buffer BF includes two buffer units BFP and BFN. The buffer unit BFP has five input terminals NIP, NIXP, NBP, NCP, and NCXP, and one output terminal NOP. The buffer unit BFN has five input terminals NIN, NIXN, NBN, NCN, and NCXN, and one output terminal NON. The buffer units BFP and BFN have equivalent configurations.

A voltage VIP is supplied to the input terminal NIP of the buffer unit BFP and the input terminal NIXN of the buffer unit BFN. In a case where the buffer BF is any one of the first-stage buffers BF_a to BF_d, the voltage VIP is the voltage of the signal Sin. In a case where the buffer BF is the second-stage buffer BF_0or BF_4, the voltage VIP is the voltage VOP_a. In a case where the buffer BF is the second-stage buffer BF_2or BF_6, the voltage VIP is the voltage VOP_b. In a case where the buffer BF is the second-stage buffer BF_1or BF_5, the voltage VIP is the voltage VOP_c. In a case where the buffer BF is the second-stage buffer BF_3or BF_7, the voltage VIP is the voltage VOP_d.

A voltage VIN is supplied to the input terminal NIXP of the buffer unit BFP and the input terminal NIN of the buffer unit BFN. In the case where the buffer BF is any one of the first-stage buffers BF_a to BF_d, the voltage VIN is the voltage of the signal/Sin. In the case where the buffer BF is the second-stage buffer BF_0or BF_4, the voltage VIN is the voltage VON_a. In the case where the buffer BF is the second-stage buffer BF_2or BF_6, the voltage VIN is the voltage VON_b. In the case where the buffer BF is the second-stage buffer BF_1or BF_5, the voltage VIN is the voltage VON_c. In the case where the buffer BF is the second-stage buffer BF_3or BF_7, the voltage VIN is the voltage VON_d.

A bias voltage VB is supplied to the input terminal NBP of the buffer unit BFP and the input terminal NBN of the buffer unit BFN. The input terminal NCP of the buffer unit BFP is connected to the input terminal NCXN of the buffer unit BFN. The input terminal NCXP of the buffer unit BFP is connected to the input terminal NCN of the buffer unit BFN.

A voltage VOP is output from the output terminal NOP of the buffer unit BFP. In the case where the buffers BF are the first-stage buffers BF_a to BF_d, the voltages VOP are the voltages VOP_a to VOP_d, respectively. In a case where the buffers BF are the second-stage buffers BF_0to BF_7, the voltages VOP are the voltages VOP_0to VOP_7, respectively.

A voltage VON is output from the output terminal NON of the buffer unit BFN. In the case where the buffers BF are the first-stage buffers BF_a to BF_d, the voltages VON are the voltages VON_a to VON_d, respectively. In the case where the buffers BF are the second-stage buffers BF_0to BF_7, the voltages VON are the voltages VON_0to VON_7, respectively.

FIG.5is a circuit diagram illustrating an example of the configuration of the buffer included in the AD converter according to the embodiment.FIG.5illustrates details of the circuit configuration of the buffer units BFP and BFN illustrated inFIG.4.

The buffer units BFP and BFN are buffers to which differential signals are input. Each of the buffer units BFP and BFN is a source follower. Specifically, the buffer unit BFP includes transistors M1, M2, M3, M4, M5, M6, and M7, capacitors C1and C2, a resistor R1, a current source I1, a load Z1, and nodes N1and N2. The buffer unit BFN includes transistors M8, M9, M10, M11, M12, M13, and M14, capacitors C3and C4, a resistor R2, a current source I2, a load Z2, and nodes N3and N4. The transistors M1, M4, M5, M8, M11, and M12are N-conductivity type MOSFETs. The transistors M2, M3, M6, M7, M9, M10, M13, and M14are P-conductivity type MOSFETs. The transistors M1to M7have characteristics equivalent to those of the transistors M8to M14, respectively. The capacitors C1and C3have equivalent characteristics. The capacitors C2and C4have equivalent characteristics. The resistors R1and R2have equivalent characteristics. The current sources I1and I2have equivalent characteristics. The loads Z1and Z2have equivalent characteristics.

The circuit configuration of the buffer unit BFP will first be described.

The transistor M1is a main source follower in the buffer unit BFP. The transistor M1has a first terminal connected to the input terminal NCP, a second terminal connected to the output terminal NOP, and a control terminal connected to the input terminal NIP.

The transistor M2has a first terminal connected to the input terminal NCP, a second terminal connected to the node N1, and a control terminal connected to the output terminal NOP.

The transistor M3has a first terminal to which a voltage AVDD is supplied, a second terminal connected to the input terminal NCP, and a control terminal connected to the node N2. The voltage AVDD is a power supply voltage that drives the buffer BF.

The transistors M4and M5constitute a current mirror. The transistor M4has a first terminal connected to the output terminal NOP, a second terminal grounded, and a control terminal connected to the node N1. The transistor M5has a first terminal and a control terminal each connected to the node N1, and a second terminal grounded.

The transistor M6has a first terminal to which the voltage AVDD is supplied, a second terminal connected to the output terminal NOP, and a control terminal connected to the input terminal NCP.

The transistor M7has a first terminal to which the voltage AVDD is supplied, a second terminal connected to the output terminal NOP, and a control terminal connected to the input terminal NIXP.

The resistor R1is a wiring resistor. The resistor R1has a first terminal connected to the node N2and a second terminal connected to the input terminal NBP.

The capacitor C1has a first terminal connected to the node N2and a second terminal connected to the input terminal NCXP.

The capacitor C2has a first terminal connected to the input terminal NCP and a second terminal connected to the output terminal NOP.

The current source I1has an input terminal connected to the output terminal NOP and an output terminal grounded.

The load Z1has a first terminal connected to the output terminal NOP and a second terminal grounded.

A circuit configuration of the buffer unit BFN will now be described.

The transistor M8is a main source follower in the buffer unit BFN. The transistor M8has a first terminal connected to the input terminal NCN, a second terminal connected to the output terminal NON, and a control terminal connected to the input terminal NIN.

The transistor M9has a first terminal connected to the input terminal NCN, a second terminal connected to the node N3, and a control terminal connected to the output terminal NON.

The transistor M10has a first terminal to which a voltage AVDD is supplied, a second terminal connected to the input terminal NCN, and a control terminal connected to the node N4.

The transistors M11and M12constitute a current mirror. The transistor M11has a first terminal connected to the output terminal NON, a second terminal grounded, and a control terminal connected to the node N3. The transistor M12has a first terminal and a control terminal each connected to the node N3, and a second terminal grounded.

The transistor M13has a first terminal to which the voltage AVDD is supplied, a second terminal connected to the output terminal NON, and a control terminal connected to the input terminal NCN.

The transistor M14has a first terminal to which the voltage AVDD is supplied, a second terminal connected to the output terminal NON, and a control terminal connected to the input terminal NIXN.

The resistor R2is a wiring resistor. The resistor R2has a first terminal connected to the node N4and a second terminal connected to the input terminal NBN.

The capacitor C3has a first terminal connected to the node N4and a second terminal connected to the input terminal NCXN.

The capacitor C4has a first terminal connected to the input terminal NCN and a second terminal connected to the output terminal NON.

The current source I2has an input terminal connected to the output terminal NON and an output terminal grounded.

The load Z2has a first terminal connected to the output terminal NON and a second terminal grounded.

1.5 Effect According to Embodiment

In order to realize the TI-ADC20which operates at a high speed, the buffer BF which can secure a wide bandwidth (hereinafter simply referred to as a “bandwidth”) in which a gain of the voltage VOP with respect to the voltage VIP (hereinafter simply referred to as a “gain”) is greater than or equal to 0 dB is required. Specifically, in a TI-ADC20where a sampling rate of 64 GS/s is required, it is desirable that the bandwidth of the first-stage buffers BF_a to BF_d is, for example, greater than or equal to 32 GHz.

According to the embodiment, the transistor M1functions as the main source follower in the buffer unit BFP. The transistor M3functions as an element that determines the magnitude of the direct current flowing through the buffer unit BFP. The transistor M4functions as an element that determines the magnitude of the direct current flowing through the transistor M1. The transistor M5constitutes a current mirror with the transistor M4, thereby functioning as an element that determines the magnitude of the direct current flowing through the transistor M2. Thus, the transistors M2and M5can function as elements that improve the gain and linearity while keeping the voltage between the drain and source of the transistor M1constant. Accordingly, it is possible to reduce the load of the compensation function in the CTLE and the VGA in the AFE10.

Similarly, the transistor M8functions as the main source follower in the buffer unit BFN. The transistor M10functions as an element that determines the magnitude of the direct current flowing through the buffer unit BFN. The transistor M11functions as an element that determines the magnitude of the direct current flowing through the transistor M8. The transistor M12constitutes a current mirror with the transistor M11, thereby functioning as an element that determines the magnitude of the direct current flowing through the transistor M9. Thus, the transistors M9and M12can function as elements that improve the gain and linearity of the voltage VON with respect to the voltage VIN while keeping the voltage between the drain and source of the transistor M8constant. Therefore, it is possible to reduce the load of the compensation function in the CTLE and the VGA in the AFE10.

Note that, in a high frequency band, a pole may be formed by coupling of the resistors R1and R2, which are wiring resistors, with the capacitance of the transistor M3and the capacitance of the transistor M10, respectively. If the pole is formed, a gain characteristic in the high frequency band is deteriorated, which is not preferable. According to the embodiment, the capacitor C1has the first terminal connected to the node N2and the second terminal connected to the input terminal NCN via the input terminal NCXP. The capacitor C3has the first terminal connected to the node N4and the second terminal connected to the input terminal NCP via the input terminal NCXN. Thus, it is possible to suppress the deterioration of the gain characteristic in the high frequency band due to the resistor R1and capacitance of the transistor M3, and the deterioration of the gain characteristic in the high frequency band due to the resistor R2and the capacitance of the transistor M10. Accordingly, it is possible to extend the bandwidth of the buffer BF.

In addition, the transistor M7has the first terminal to which the voltage AVDD is supplied, the second terminal connected to the output terminal NOP, and the control terminal to which the voltage VIN is supplied. The current source I1has the input terminal connected to the output terminal NOP and the output terminal grounded. The transistor M14has the first terminal to which the voltage AVDD is supplied, the second terminal connected to the output terminal NON, and the control terminal to which the voltage VIP is supplied. The current source I2has the input terminal connected to the output terminal NON and the output terminal grounded. Thus, a pair of the transistor M7and the current source I1and a pair of the transistor M14and the current source I2can function as differential amplifiers. Therefore, it is possible to improve the gain characteristic over the entire frequency band. Accordingly, it is possible to reduce the load of the compensation function in the CTLE and VGA in the AFE10, and to extend the bandwidth of the buffer BF.

In addition, the transistor M6has the first terminal to which the voltage AVDD is supplied, the second terminal connected to the output terminal NOP, and the control terminal connected to the input terminal NCP. The transistor M13has the first terminal to which the voltage AVDD is supplied, the second terminal connected to the output terminal NON, and the control terminal connected to the input terminal NCN. Thus, the transistors M6and M13can function as inverting amplifiers. Therefore, it is possible to reduce the output resistance of the voltages VOP and VON, and to improve the gain characteristic particularly in the high frequency band. Accordingly, it is possible to extend the bandwidth of the buffer BF.

In addition, the capacitor C2has the first terminal connected to the input terminal NCP and the second terminal connected to the output terminal NOP. The capacitor C4has the first terminal connected to the input terminal NCN and the second terminal connected to the output terminal NON. Thus, it is possible to improve the gain characteristic particularly in the high frequency band. Accordingly, it is possible to extend the bandwidth of the buffer BF.

Note that the embodiment is not limited to the examples described above, and various modifications may be applied.

In the above-described embodiment, a case where the N-conductivity type MOSFET is applied to the main source follower in the buffer BF has been described, but the embodiment is not limited thereto. For example, a P-conductivity type MOSFET may be applied to the main source follower in the buffer BF.FIG.6is a circuit diagram illustrating an example of a configuration of a buffer included in an AD converter according to a modification.FIG.6corresponds toFIG.5in the embodiment.FIG.6illustrates buffer units BFP′ and BFN′.

The buffer unit BFP′ includes transistors M1′, M2′, M3′, M4′, M5′, M6′, and M7′, a resistor R1′, capacitors C1′ and C2′, a current source I1′, and a load Z1′. The buffer unit BFN′ includes transistors M8′, M9′, M10′, M11′, M12′, M13′, and M14′, a resistor R2′, capacitors C3′ and C4′, a current source I2′, and a load Z2′. The transistors M1′ to M14′, the resistors R1′ and R2′, the capacitors C1′ to C4′, the current sources I1′ and I2′, and the loads Z1′ and Z2′ in the buffer units BFP′ and BFN′ correspond to the transistors M1to M14, the resistors R1and R2, the capacitors C1to C4, the current sources I1and I2, and the loads Z1and Z2in the buffer units BFP and BFN illustrated inFIG.5, respectively. The configurations of the buffer units BFP′ and BFN′ are equivalent to the configurations of the buffer units BFP and BFN, except that the conductivity types of the internal transistors M1′ to M14′ and the relationship between the supplied voltages AVDD and AVSS are inverted from those of the buffer units BFP and BFN. Even if such buffer units BFP′ and BFN′ are used, it is possible to obtain the effects equivalent to those of the buffer units BFP and BFN.

In addition, in a case where the buffer BF has a two-stage configuration having the first-stage buffers BF_a to BF_d and the second-stage buffers BF_0to BF_7, the buffers BF of the same conductivity type may be applied for each stage, or the buffers BF of different conductivity types may be applied for each stage. Specifically, for example, an N-conductivity type MOSFET may be applied to the main source follower in the first-stage buffers BF_a to BF_d, and a P-conductivity type MOSFET may be applied to the main source follower in the second-stage buffers BF_0to BF_7. Which conductivity type of buffer BF is applied to which stage can be determined according to the magnitude of the direct current components of the voltages VIP and VIN, and the voltage AVDD to be input to the buffer BF.

In addition, in the above-described embodiment, a case where the buffer unit BFP includes the transistors M1to M7, the resistor R1, the capacitors C1and C2, the current source I1, and the load Z1, and the buffer unit BFN includes the transistors M8to M14, the resistor R2, the capacitors C3and C4, the current source I2, and the load Z2has been described, but the embodiment is not limited thereto. For example, the buffer units BFP and BFN may be configured not to include the capacitors C1and C3, respectively. In the case of a configuration not including the capacitors C1and C3, the input terminal NCP and the input terminal NCXN are not connected to each other, and the input terminal NCXP and the input terminal NCN are not connected to each other. For example, the buffer units BFP and BFN may also be configured not to include the transistor M7and the current source I1, and the transistor M14and the current source I2, respectively. In the case of the configuration not including the transistor M7and the current source I1, and the transistor M14and the current source I2, the input terminal NIP and the input terminal NIXN are not connected to each other, and the input terminal NIXP and the input terminal NIN are not connected to each other. For example, the buffer units BFP and BFN may also be configured not to include the transistors M6and M13, respectively. For example, the buffer units BFP and BFN may also be configured not to include the capacitors C2and C4, respectively.

In addition, in the above-described embodiment, a case where the signal to be input to the TI-ADC20is generated by using the buffer having a two-stage configuration has been described, but the embodiment is not limited thereto. The signal to be input to the TI-ADC20may be generated by a buffer having a one-stage configuration or may be generated by a buffer having a configuration of three or more stages.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. Indeed, the embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The embodiments and modifications are included in the scope and spirit of the invention and are included in the scope of the claimed inventions and their equivalents.