Sharing compiler optimizations in a multi-node system

Embodiments of the invention enable application programs running across multiple compute nodes of a highly-parallel system to compile source code into native instructions, and subsequently share the optimizations used to compile the source code with other nodes. For example, determining what optimizations to use may consume significant processing power and memory on a node. In cases where multiple nodes exhibit similar characteristics, it is possible that these nodes may use the same set of optimizations when compiling similar pieces of code. Therefore, when one node compiles source code into native instructions, it may share the optimizations used with other similar nodes, thereby removing the burden for the other nodes to figure out which optimizations to use. Thus, while one node may suffer a performance hit for determining the necessary optimizations, other nodes may be saved from this burden by simply using the optimizations provided to them.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to improving the efficiency of multi-node computing systems. More specifically, embodiments of the invention may be configured to improve performance on a multi-node computing system by selectively compiling source code to native instructions among compute nodes of such a system.

2. Description of the Related Art

Powerful computers may be designed as highly parallel systems where the processing activity of thousands of processors (CPUs) is coordinated to perform computing tasks. These systems are highly useful for a broad variety of applications, including financial modeling, hydrodynamics, quantum chemistry, astronomy, weather modeling and prediction, geological modeling, prime number factoring, and image processing (e.g., CGI animations and rendering), to name but a few examples.

For example, one family of parallel computing systems has been (and continues to be) developed by International Business Machines (IBM) under the name Blue Gene®. The Blue Gene/L architecture provides a scalable, parallel computer that may be configured with a maximum of 65,536 (216) compute nodes. Each compute node includes a single application specific integrated circuit (ASIC) with 2 CPU's and memory. The Blue Gene/L architecture has been successful and on Oct. 27, 2005, IBM announced that a Blue Gene/L system had reached an operational speed of 280.6 teraflops (280.6 trillion floating-point operations per second), making it the fastest computer in the world at that time. Further, as of June 2005, Blue Gene/L installations at various sites world-wide were among five out of the ten top most powerful computers in the world.

The compute nodes in a parallel system typically communicate with one another over multiple communication networks. For example, the compute nodes of a Blue Gene/L system are interconnected using five specialized networks. The primary communication strategy for the Blue Gene/L system is message passing over a torus network (i.e., a set of point-to-point links between pairs of nodes). The torus network allows application programs developed for parallel processing systems to use high level interfaces such as Message Passing Interface (MPI) and Aggregate Remote Memory Copy Interface (ARMCI) to perform computing tasks and distribute data among a set of compute nodes. Of course, other message passing interfaces have been (and are being) developed. Additionally, the Blue Gene/L includes both a collective network and a global interrupt network. Further, certain nodes are also connected to a gigabit Ethernet. These nodes are typically used to perform I/O operations between the Blue Gene core and an external entity such as a file server. Other massively parallel architectures also use multiple, independent networks to connect compute nodes to one another.

Massively parallel systems such as the Blue Gene architecture were originally designed to support a SIMD (Single Instruction Multiple Data) programming paradigm. This typically involves running one large scale tightly coupled MPI-based application across all of the compute nodes in a partition. In comparison to other available packaging strategies, the Blue Gene packaging produces many teraflops per rack, has a large memory footprint, and low power consumption. This also makes the Blue Gene architecture attractive for a High Throughput Computing (HTC) model. HTC provides a computing model that allows for independent work units on each node. A launcher program resides on each compute node of a massively parallel system. The launcher program listens for work-requests from a scheduler, performs the request, and restarts. In such a case, each node in the system executes the same program, but may execute different portions of the program, depending on the actual work request taken up by a node. The scheduler is generally an external program transferring work requests to the launcher collective.

SUMMARY OF THE INVENTION

One embodiment of the invention provides a computer-implemented method for optimizing a program executing on plurality of compute nodes of a massively parallel computing system. This method may generally include identifying a plurality of blocks of code included in the program and selecting, for at least a first block of code, a plurality of sets of optimization parameters to use in compiling the first block of code into a set of native instructions. The method may further include transmitting one of the sets of optimization parameters to each of the plurality of compute nodes, compiling, by each of the plurality of compute nodes, the first block of code using the set of optimization parameters received by a respective compute node, and monitoring at least a performance characteristic of the program when the set of native instructions generated by compiling the block of code according to the set of optimization parameters are executed by one of the compute nodes.

Another embodiment of the invention includes a computer-readable storage medium containing a program which, when executed by a processor, performs an operation for optimizing an application program executing on plurality of compute nodes of a massively parallel computing system. The operation may generally include identifying a plurality of blocks of code included in the program and selecting, for at least a first block of code, a plurality of sets of optimization parameters to use in compiling the first block of code into a set of native instructions. The method may further include transmitting one of the sets of optimization parameters to each of the plurality of compute nodes, compiling, by each of the plurality of compute nodes, the first block of code using the set of optimization parameters received by a respective compute node, and monitoring at least a performance characteristic of the program when the set of native instructions generated by compiling the block of code according to the set of optimization parameters are executed by one of the compute nodes.

Still another embodiment of the invention includes a system having a plurality of compute nodes, each having a processor and a memory, and each executing an application program. The system may further include a service node having a processor and a memory, and executing program, which when executed on the service node performs an operation for optimizing the application program executing on the plurality of compute nodes. The operation may generally include identifying a plurality of blocks of code included in the program, and selecting, for at least a first block of code, a plurality of sets of optimization parameters to use in compiling the first block of code into a set of native instructions. The operation may further include transmitting one of the sets of optimization parameters to each of the plurality of compute nodes, compiling, by each of the plurality of compute nodes, the first block of code using the set of optimization parameters received by a respective compute node, and monitoring at least a performance characteristic of the program when the set of native instructions generated by compiling the block of code according to the set of optimization parameters are executed by one of the compute nodes.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the invention enable application programs running across multiple compute nodes of a highly-parallel system to selectively compile source code (or bytecode) into native instructions as well as to share optimizations used to compile the source code with other nodes. Sharing optimization hints may reduce each node's burden in determining the best native instructions to create for a given block of code (e.g., a method, object, class or package, etc.) on a given node. Determining what optimizations to use frequently consumes significant processing power and memory on a node. However, when multiple compute nodes exhibit similar characteristics, and run the same underlying applications, it is possible that these nodes may use the same set of optimizations when compiling similar (or the same) pieces of code. For example, when one node selects to compile a block of source code (or bytecode), it may share what optimizations were used with other similar nodes, thereby removing the burden to determine which optimizations to use for a given block of code. Thus, while one node may suffer a performance hit when determining the necessary optimizations, other nodes may avoid this burden by simply using the optimizations determined to be effective for the given bock of source code. In one embodiment, a central node may be used to track what optimizations were applied to what portions of compiled code and evaluate the effectiveness of different optimization parameters.

Further, in addition to sharing optimization hints to reduce each node's burden in determining the best native instructions to create for a given method on a given node, the process may be divided across nodes. This may be accomplished by segregating packages, classes, and/or methods such that some nodes determine the proper native code for certain blocks of the code. That is, the optimization problem may be parallelized by selecting different nodes to evaluate different portions of source code.

In one embodiment, when a given block of code is selected to be compiled, the compute node may request that another node actually perform the compilation. For example, if a node determines that compiling the block of code locally requires a significant amount of local resources, it may in some cases off-load the task to a remote node. Once the remote node compiles the source code to native instructions, it may subsequently transmit the native instructions back to the local node.

Further, nodes may also cooperatively try out different combinations of optimizations, and share the results with other nodes (or with a centralized manager). In this way, as nodes determine more and more effective optimizations, this information may be shared with other nodes allowing them to recompile their code using the more effective optimizations.

FIG. 1is a block diagram illustrating components of a massively parallel computer system100, according to one embodiment of the present invention. Illustratively, computer system100shows the high-level architecture of an IBM Blue Gene® computer system, it being understood that other parallel computer systems could be used, and the description of a preferred embodiment herein is not intended to limit the present invention.

As shown, computer system100includes a compute core101having a plurality of compute nodes112arranged in a regular array or matrix. Compute nodes112perform the useful work performed by system100. The operation of computer system100, including compute core101, may be controlled by service node102. Various additional processors in front-end nodes103may perform auxiliary data processing functions, and file servers104provide an interface to data storage devices such as disk based storage109A,109B or other I/O operations. Functional network105provides the primary data communication path among compute core101and other system components. For example, data stored in storage devices attached to file servers104is loaded and stored to other system components through functional network105.

Also as shown, compute core101includes I/O nodes111A-C and compute nodes112A-I. Compute nodes112provide the processing capacity of parallel system100, and are configured to execute applications written for parallel processing. I/O nodes111handle I/O operations on behalf of compute nodes112. For example, the I/O node111may retrieve data from file servers104requested by one of compute nodes112. Each I/O node111may include a processor and interface hardware that handles I/O operations for a set of N compute nodes112, the I/O node and its respective set of N compute nodes are referred to as a Pset. Compute core101contains M Psets115A-C, each including a single I/O node111and N compute nodes112, for a total of M×N compute nodes112. The product M×N can be very large. For example, in one implementation M=1024 (1K) and N=64, for a total of 64K compute nodes.

In general, application programming code and other data input required by compute core101to execute user applications, as well as data output produced by the compute core101, is communicated over functional network105. The compute nodes within a Pset115communicate with the corresponding I/O node over a corresponding local I/O collective network113A-C. The I/O nodes, in turn, are connected to functional network105, over which they communicate with I/O devices attached to file servers104, or with other system components. Thus, the local I/O collective networks113may be viewed logically as extensions of functional network105, and like functional network105, are used for data I/O, although they are physically separated from functional network105.

Service node102may be configured to direct the operation of the compute nodes112in compute core101. In one embodiment, service node102is a computer system that includes a processor (or processors)121, internal memory120, and local storage125. The service node102may also include profile126, a profile analyzer127, and a scheduler128. An attached console107(i.e., a keyboard, mouse, and display) may be used by a system administrator or similar person to initialize computing jobs on compute core101. Service node102may also include an internal database which maintains state information for the compute nodes in core101, and an application which may be configured to, among other things, control the allocation of hardware in compute core101, direct the loading of data on compute nodes111, migrate processes running on one of compute nodes112to another one of compute nodes112, and perform diagnostic and maintenance functions.

The profile126may maintain a profile for various blocks of source code (e.g. methods, classes, and packages, and the like) of an application running on the compute nodes112. Accordingly, while only one profile126is shown, the service node102may include a plurality of profiles126. The profile126may include information indicating the overhead (i.e. CPU/memory usage) incurred by running the source code on a particular compute node112. The profile may also include information indicating the optimizations used to compile the source code into native instructions, along with the overhead incurred performing the compile.

The profile126may be analyzed by the profile analyzer127. The profile analyzer127may determine any performance gains achieved by compiling the source code to native instructions. For example, the profile analyzer127may determine that the execution time of the native instructions is faster than the execution time of the source code.

Furthermore, the profile analyzer127may also determine whether execution performance of an application running on other compute nodes112may benefit from compiling a given blocks of source code. By evaluating the profiles of methods, classes, packages, etc., running on different compute nodes112, the profile analyzer127may determine that a plurality of compute nodes112exhibit similar behavior. Therefore, the performance gains achieved by compiling source code to native instructions on a first compute node112, is likely to result in similar performance gains on a second compute node112having similar characteristics. Therefore, the service node102may schedule a compilation to the other similar compute nodes. Furthermore, the service node102may also share the optimizations used to compile the source code on the first compute node to the second node, thereby removing the burden on the second mode to determine which optimizations to use.

In one embodiment, the profile126, the profile analyzer127and the scheduler127may reside on one (or more) of the compute nodes112of the compute core101. In this case, the compute node may act as a central node configured to build and evaluate profiles and share the compiler optimizations used by one compute node112with other compute nodes112of the compute core101. In another embodiment, the profile126, the profile analyzer127and the scheduler127may reside on any of the front-end nodes103.

Illustratively, memory120also includes a control system122. In embodiments of the invention, Control system122may be a software application configured to control the allocation of compute nodes112in compute core101, direct the loading of application and data on compute nodes111, and perform diagnostic and maintenance functions, among other things.

In one embodiment, service node102communicates control and state information with the nodes of compute core101over control system network106. Network106is coupled to a set of hardware controllers108A-C. Each hardware controller communicates with the nodes of a respective Pset115over a corresponding local hardware control network114A-C. The hardware controllers108and local hardware control networks114are logically an extension of control system network106, although physically separate. In one embodiment, control system network106may include a JTAG (Joint Test Action Group) network, configured to provide a hardware monitoring facility. As is known, JTAG is a standard for providing external test access to integrated circuits serially, via a four- or five-pin external interface. The JTAG standard has been adopted as an IEEE standard. Within a Blue Gene system, the JTAG network may be used to send performance counter data to service node102in real-time. That is, while an application is running on compute core101, network performance and/or network state data may be gathered and transmitted to service node102without affecting the performance of that application. In one embodiment, the profile analyzer127may access information about the performance of an application, and the result of different compilation optimizations, by querying individual compute nodes112over control network106. Of course, other massively parallel architectures may similarly provide this (or other mechanisms) for monitoring and querying application state on a collection of compute nodes.

In addition to service node102, front-end nodes103provide computer systems used to perform auxiliary functions which, for efficiency or otherwise, are best performed outside compute core101. Functions which involve substantial I/O operations are generally performed in the front-end nodes103. For example, interactive data input, application code editing, or other user interface functions are generally handled by front-end nodes103, as is application code compilation. Front-end nodes103are also connected to functional network105and may communicate with file servers104.

The scheduler128may be configured to provide an application program configured to respond to work requests made by an application executing on one of the compute nodes112. In one embodiment, the same application executes on each of a group of compute nodes112(commonly referred to as a partition) and each node submits work requests to the scheduler128. Further, as a given compute node in the group completes executing an assignment received from the scheduler128, results may be returned to a central node (or group of nodes), to the scheduler, or to another application tasked with receiving and processing results. At the same time, each compute node112may select to compile blocks of code included in the application, or different optimizations to use when compiling a given block of code.

As stated, in a massively parallel computer system100, compute nodes112may be logically arranged in a three-dimensional torus, where each compute node112may be identified using an x, y and z coordinate.FIG. 2is a conceptual illustration of a three-dimensional torus network of system100, according to one embodiment of the invention. More specifically,FIG. 2illustrates a 4×4×4 torus201of compute nodes, in which the interior nodes are omitted for clarity. AlthoughFIG. 2shows a 4×4×4 torus having 64 nodes, it will be understood that the actual number of compute nodes in a parallel computing system is typically much larger. For example, a Blue Gene/L system may be configured with 65,536 compute nodes112along with and an additional 1024 I/O nodes111. Illustratively, each compute node112in torus201includes a set of six node-to-node communication links202A-F which allows each compute nodes in torus201to communicate with its six immediate neighbors, two nodes in each of the x, y and z coordinate dimensions.

As used herein, the term “torus” includes any regular pattern of nodes and inter-nodal data communications paths in more than one dimension, such that each node has a defined set of neighbors, and for any given node, it is possible to determine the set of neighbors of that node. A “neighbor” of a given node is any node which is linked to the given node by a direct inter-nodal data communications path. That is, a path which does not have to traverse another node. The compute nodes may be linked in a three-dimensional torus201, as shown inFIG. 2, but may also be configured to have more or fewer dimensions. Also, it is not necessarily the case that a given node's neighbors are the physically closest nodes to the given node, although it is generally desirable to arrange the nodes in such a manner, insofar as possible.

In one embodiment, the compute nodes in any one of the x, y, or z dimensions form a torus in that dimension because the point-to-point communication links logically wrap around. For example, this is represented inFIG. 2by links202D,202E, and202F which wrap around from compute node203to other end of compute core201in each of the x, y and z dimensions. Thus, although node203appears to be at a “corner” of the torus, node-to-node links202A-F link node203to nodes204,205, and206, in the x, y, and Z dimensions of torus201.

FIG. 3illustrates components of a compute node112of the system100ofFIG. 1, according to one embodiment of the invention. As shown, compute node112includes processor cores301A and301B, each having an instruction address register306A and306B. Compute node112also includes memory302used by both processor cores301; an external control interface303which is coupled to local hardware control network114(e.g., control system network106); an external data communications interface304which is coupled to the corresponding local I/O collective network113and the corresponding six node-to-node links202of the torus network201; and includes monitoring and control logic305which receives and responds to control commands received through external control interface303. Monitoring and control logic305may access processor cores301and locations in memory302on behalf of service node102to read (or in some cases alter) the operational state of node112. In one embodiment, each compute node112may be physically implemented as a single integrated circuit.

As described, functional network105may service many I/O nodes113, and each I/O node113is shared by a group of compute nodes112(i.e., a Pset). Thus, it is apparent that the I/O resources of parallel system100are relatively sparse when compared to computing resources. Although it is a general purpose computing machine, parallel system100is designed for maximum efficiency in applications which are computationally intense.

As shown inFIG. 3, memory302stores an operating system image311. Operating system image311provides a copy of a simplified-function operating system running on compute node112, referred to as a compute node kernel. The compute node kernel provides a minimal set of functions required to support operation of the compute node112. In one embodiment, a virtual machine312may also reside within memory302. The virtual machine312running on compute node112may be configured to execute applications created for the virtual machine312. For example, the virtual machine312may be an implementation of a Java® virtual machine and operating environment available from Sun Microsystems, Inc.

Furthermore, a copy of the virtual machine312may be present and executing on thousands of compute nodes112, where, in one embodiment, each compute node executes the same application but maintains application data local to a given compute node112. For example, as described above each compute node112may be configured to request work from a scheduler128and process tasks received from the scheduler128to, collectively, perform a computing task. In another embodiment, some compute nodes may execute a different application, or simply remain idle. Further, applications running on the compute nodes112may be configured to share and transfer application data using well known message passing techniques (e.g., MPI or ARMCI).

Illustratively, virtual machine312is shown executing application314. In the case of a Java® based virtual machine, application314may be written using a programming language and compiler configured to generate bytecode (from source code, i.e. classes, methods, packages, etc.) for the particular virtual machine312. In turn, the virtual machine312may execute application314by interpreting the compiled bytecode into instructions understandable by processor cores301A and301B.

While executing, the application314may instantiate objects3161,3162,316nby dynamically allocating memory. For example, the Java® programming language provides the “new” operator used to create an object and allocate memory at runtime for that object. Other programming languages provide similar constructs. Each object3161,3162,316nmay be defined by a class (or the bytecode of the given class), and therefore, each object3161,3162,316nmay be an instance of the class. Furthermore, each object may have an associated method, which may provide a mechanism for manipulating and accessing (i.e reading and writing) data stored in an object or a class. Accordingly, objects3161,3162,316nmay also be representative of a class or a method for the objects3161,3162,316nor simply the bytecode for the given method or class.

As illustrated, virtual machine312may also include a just-in-time compiler318. In one embodiment, the just-in-time compiler318may compile the bytecode of a given method class or package to native instructions, i.e., to a set of instructions that may be executed on CPU301A and CPU301B directly, without the need to be interpreted by the virtual machine302. Once compiled, calls to the method or class may be handled by the native instructions instead of the virtual machine's312interpretation of the code.

In one embodiment, the just-in-time compiler318may compile the bytecode associated with a given block of code once it has been accessed and interpreted a certain number of times. This is also known as Mixed Mode Interpretation (MMI) to those skilled in the art. With MMI, a count may be kept of the number of times each application's method or class is executed. Bytecode corresponding to the method may be interpreted until that count reaches a predetermined threshold value. In this way, for methods used only a small number of times, the overhead incurred to perform a just-in-time compilation may be avoided. For methods that are frequently reused when the threshold count is reached, just-in-time compilation may be performed, and method execution time may be optimized.

As further shown inFIG. 3, the virtual machine312may also include a history320. The history320may store information regarding the execution times of methods before and after compilation. The history may also include the compiler optimizations used to compile the methods. Additionally, the history may also include the compute resources (i.e. memory and CPU usage) used to compile the method, and the resources used to execute a method (pre and post-compilation). Thus, over time, the history320may provide a profile of a method's behavior (and effectiveness) on a given node.

When performing a just-in-time compilation, the just-in-time compiler318may use a variety of different compiler optimizations (i.e. aggressive method inlining, dataflow-based optimizations, loop optimizations, etc.). The optimizations used may be dependent on the characteristics of the compute node112on which the application314is running. For example, the compilation may be optimized to a targeted CPU's instruction set and operating system model where the application314runs. Furthermore, the just-in-time compiler318may also make optimizations using the profile126generated for methods of an object invoked by the application314.

In one embodiment, the virtual machine312and just-in-time compiler318may evaluate history320to determine locally what optimizations to make when compiling a given block of code. Furthermore, each compute node112may share the optimizations used with other nodes in the system101. For example, in one embodiment, a compute node112may communicate a set of optimizations, along with the other information stored in its history320, to the service node102. In turn, the service node102may store this information along with a profile126for each method invoked by an application running on the compute nodes112. In another embodiment, the service node102may periodically poll the compute nodes and gather information stored in the history320of each of the compute nodes112.

FIGS. 4-6illustrate an example of operations for compiling source code (or bytecode). Specifically,FIG. 4illustrates a method400for compiling source code (i.e. a method, classes, and/or packages associated with an application program), according to one embodiment of the invention. As shown, the method400begins at step402, where an application314is executed on a compute node112. At step404, a method of the application314is accessed. That is, the application312may invoke the execution of a block of instructions associated with the application402, e.g., a sequence of bytecode representing an object method. At step406, the virtual machine312may determine whether the block of instructions has been compiled to native instructions. If so, the virtual machine may access the native instructions (step416) and subsequently execute the native instructions (step418).

However, in the case where the block of code has not been compiled to native instructions, at step408, the virtual machine may interpret the bytecode into instructions understandable by the CPU(s)301A,301B of the compute node112. Once interpreted, then at step410, the virtual machine312may execute the interpreted code. At step412, the virtual machine312may determine if the number of times the block of code has been interpreted has reached a specified threshold. In this case, the virtual machine312may track the number of times that a given method has been accessed and interpreted. If the number of times exceeds the threshold, the virtual machine may subsequently compile the method into native instructions using the just-in-time compiler318(step414). However, if the number of times does not exceed the threshold, the method400returns to step402, where the application312continues to execute.

FIG. 5illustrates a method500for compiling a block of code (e.g., bytecode) to native instructions, according to one embodiment of the invention. Specifically, method500illustrates a technique to distribute the compilation of a method from a first compute node112to a second compute node112. As shown, method500begins at step502, where it is determined whether the amount of computing resources (e.g., memory, processor cycles) required to compile the block of code exceeds a predetermined threshold. If not, at step514, the block of code may be compiled locally using the just-in-time compiler318. Further, in one embodiment, the just-in-time compiler may select a set of optimizations to apply to the block of code during the compilation process and share what optimizations were selected with the profile analyzer128. At step512, the virtual machine312may execute the native instructions.

However, at step502, the virtual machine312may determine that the compiling the block of code would exceed the capacity of available computing resources on node112. In such a case, at step504, the virtual machine312may determine if another compute node112can handle the compile. Accordingly, in one embodiment, the virtual machine312running on the first compute node112may be configured to communicate with a second compute node112to determine whether the second compute node has computing resources available to perform the compilation. If so, then at step506, the bytecode may be transmitted to the second compute node112. If not, then at step516, the block of code may be interpreted by the virtual machine running on the first compute node, skipping compilation altogether.

Once the block of code is transmitted to the second compute node112, at step508, the second compute node may compile the block of code to native instructions. After compilation, at step510, the second compute node112may transmit the native instructions back to the original node. Subsequently, at step512, once the native instructions are returned, the first node may execute the native instructions locally. Further, in one embodiment, the just-in-time compiler318may select a set of optimizations to apply to the block of code during the compilation process and share what optimizations were selected with the profile analyzer128. At step516, the virtual machine312may execute the native instructions.

FIG. 6illustrates a method600for distributing blocks of source code for compilation by a plurality of compute nodes, according to one embodiment of the invention. As discussed above, a compute node112may share the optimizations used to compile a given block of code (e.g., bytecode representing a given method, object, class or package). In doing so, other nodes may reduce the burden of determining an optimal sequence of native instructions to create for a given block of code. As shown, method600begins at step602, where a block of code is compiled to native instructions. At step604, once a block of code has been compiled to native instructions, the compute node112may notify the service node102of the compile and the set of optimizations used to compile the block of code.

In one embodiment, the compute nodes112and the service node102may be configured to share data using well known message passing techniques (e.g., MPI or ARMCI). In another embodiment, the service node102may use the JTAG network to gather data. For example, the JTAG network may be used to periodically poll the compute nodes112to collect information from the history320of a compute node112. The information collected may include which blocks of code present on a respective compute node112have been compiled to native machine instructions. Other information collected may include, e.g., execution times for a method (before and after the method has been compiled), the optimizations used to compile the method(s), and the compute resources required to compile the method(s).

At step606, the information is returned to the service node102, where at step606, it is used to build a profile126for the block of code. The profile126may be analyzed by the profile analyzer127to determine performance gains achieved as a result of compiling the block of code to native instructions. For example, in one embodiment, the profile analyzer127may compare execution times for a method before and after being compiled to native instructions to determine which version of the code performs faster, uses less memory, or how the native performance affect application performance suing another measured performance characteristic.

Additionally, the profile analyzer127may also perform a comparative analysis between profiles126of a given block of code executing on different compute nodes112. For example, the profile analyzer127may compare different profiles126and determine that two or more compute nodes exhibit similar characteristics. For example, the two or more compute nodes may execute the same blocks of code (i.e. methods, classes, etc.). Thus, if it is determined that compiling a block of code to native instructions on a first compute node results in a performance gain, then compiling the same block of code on a similar compute node may result in a similar performance gain.

Accordingly, at step608, the profile analyzer127may determine that another compute node may benefit (i.e. achieve a performance gain) from compiling a block of code to native instructions. In response, at step610, the scheduler128of the service node102may send a command (i.e. via an MPI message) to other nodes to compile the block of code using the same optimizations used to compile that block of code on the first node. That is, in one embodiment, the scheduler128may simply pass the optimizations used in the first node to the other nodes having similar characteristics. The other nodes may store the optimizations locally, and access them when compiling a given block of code.

In another embodiment, the scheduler128may also expedite the compilation on the other node(s). For example, the command to compile the method may also be configured to lower the threshold for the number of times a method needs to be interpreted before being compiled. In another embodiment, the scheduler may set the threshold to zero, thereby effectively bypassing the threshold altogether. In this case, the block of code may be compiled the next time it is accessed. In the case where the profile analyzer127determines that other compute nodes may not achieve a performance gain (or possibly experience a performance loss), at step612, then the block of code is not compiled.

In one embodiment, the profile analyzer127may also be configured to perform a comparative analysis to determine an optimal set of optimization parameters to compile a particular block of code. For example, different compute nodes112may compile an object method using different optimizations parameters. Therefore, in one embodiment, the profile analyzer127may evaluate the optimizations performed of the same block of code, compiled using different optimization parameters, to identify which optimizations result in the greatest performance gain. In one embodiment, the profile analyzer127may compare the post-compilation execution times of similar methods and determine which optimization techniques resulted in the fastest execution times (or lowest memory usage, or “best” result for another performance metric). Once determined, the scheduler127may send a message to compute nodes executing the same application to compile the given block of code method using the identified optimizations.

In another embodiment, the profile analyzer127may determine that the optimizations resulting in the fastest execution time also require extensive compute power and/or memory. In such a case, the profile analyzer127may first evaluate whether a given compute node112has adequate resources to support running the native code using these optimizations. Consider an example where a first compute node and second compute node both execute the same method. However, suppose that the first compute node performs far less operations than the second compute node. If the first compute node compiles the method using optimizations that result in a fast execution time, and also require an extensive amount of compute resources, the first compute node may not be affected, since the first compute node does not perform many operations to begin with. Therefore, the first compute node can afford to execute the method compiled with these optimizations. However, if the second compute node compiles its method with the same optimizations, it may suffer from a performance hit. That is, while the one method may execute quickly, the other operations performed by the second node may perform slowly due to the resource consumption by the compiled method. Therefore, in one embodiment, the profile analyzer127may determine a different set of optimizations for a compute node to use for compiling the method.

In another embodiment, the compute nodes112may cooperatively test out different setting for optimization parameters for the same block of code. For example, the scheduler127may send a different set of optimization parameters to different compute nodes112executing the same block of code. After the compute nodes112are done compiling the methods, the service node102may gather information from the history320of each of the compute nodes112, and store this information in a profile126associated with the block of code. Thereafter, the profile analyzer127may perform a comparative analysis for the different optimizations and determine which optimization was the most effective (e.g., in terms of execution time, resource consumption, or other performance metrics). Once the most effective optimization is identified, the service node102may send a message to the nodes to recompile this block of code using the most effective optimization parameters.

FIG. 7illustrates an example of a plurality of compute nodes700performing the compilation method ofFIG. 5. As shown, the plurality of compute nodes700includes a local node A702and first remote node B704, a second remote node C706and an Nth remote node N708. Also shown is the local node A′710, which illustrates local node A702after the compilation method is complete.

The local node A702is shown executing a plurality of methods or classes7501-750nfor an application. In one embodiment, for example in a Java® environment, the methods or classes may be compiled bytecode. As stated earlier, bytecode may be interpreted into instructions understandable by a processor by a virtual machine. After the number of times a given block of code has been interpreted reaches a threshold, the local node may invoke a just-in-time compiler318to compile the block of code to native instructions. Furthermore, as discussed in reference toFIG. 5, the local node A702may decide that compiling the block of code may consume an excessive amount of compute resources. As a result, the local node A702may transmit the block of code (e.g., the particular sequence of bytecode) to a remote node for compilation.

Accordingly, local node A702is shown transmitting a plurality of object methods to different remote nodes. For example, object methods7501-7502may be transmitted to remote node B704(see arrow7121), object methods7503-7504may be transmitted to remote node C (see arrow7122), and object method750nmay be transmitted to remote node C (see arrow712n). Accordingly, remote nodes B, C, and N, are shown with object methods7501-7502,7503-7504, and750n, respectively.

Once the object methods are received, the remote nodes B, C, N may compile the object methods to native instructions using a just-in-time compiler. Accordingly, remote node B is shown compiling object methods7501-7502to native instructions750′1-750′2(see arrow7141), remote node C is shown compiling object methods7503-7504to native instructions750′3-750′4(see arrow7142), and remote node N is shown compiling object method750nto native instructions750′n(see arrow714n).

After compilation is complete, remote nodes B, C, N may subsequently transmit the native instructions generated by the compilation process to the local node (illustrated as local node A′710. Accordingly, native instructions750′1-750′2may be migrated from remote node B704to local node A′710(see arrow7161), native instructions750′3-750′4may be migrated from remote node C to local node A′710(see arrow7162), and native instructions750′nmay be migrated from remote node C to local node A′710(see arrow716n). Additionally, local node A′710is shown with native instructions750′1-750′n. Thus, the local node may then execute the native instructions locally.