FIELD EFFECT TRANSISTOR WITH P-FET TYPE BEHAVIOUR

A field effect transistor includes a substrate; an electron channel layer disposed on the substrate; a barrier layer disposed on the electron channel layer; a hole channel layer disposed on the barrier layer; a p-type doped semiconductor material layer disposed on the hole channel layer; a source electrode including a first portion in ohmic contact with the electron channel layer and a second portion in ohmic contact with the p-type doped semiconductor material layer; a drain electrode in ohmic contact with the electron channel layer; and a gate electrode disposed facing the p-type doped semiconductor material layer, between the source and drain electrodes.

TECHNICAL FIELD OF THE INVENTION

The technical field of the invention is that of power electronics. The present invention relates to a field effect transistor (or FET) based on III-N semiconductor materials such as gallium nitride (GaN).

TECHNOLOGICAL BACKGROUND OF THE INVENTION

The high electron mobility transistor (HEMT) is a field effect transistor that benefits from the conduction properties of a 2-Dimensional Electron Gas (2DEG). It comprises a vertical stack of III-N semiconductor layers on a substrate, typically made of silicon, silicon carbide or sapphire. The 2-dimensional electron gas is formed by a heterojunction between a channel layer, typically gallium nitride (GaN), and a barrier layer, typically aluminium gallium nitride (AlGaN).

The HEMT transistor holds high current densities in the on state, due to the high density of charge carriers and the high mobility of these carriers in the 2-dimensional electron gas. It can also have a high switching speed.

The HEMT transistor is an N-channel field effect transistor, commonly called an n-FET, that is, a transistor whose conduction is provided by electrons. To make logic circuits compatible with power applications, typically an inverter, this n-FET is associated with a P-channel field effect transistor, or p-FET, in other words a transistor whose conduction is provided by holes. The p-FET has to have similar performance to that of the n-FET, especially in terms of current, voltage withstand and switching speed.

FIG.1schematically represents a GaN inverter described in the document [“Gallium nitride-based complementary logic integrated circuits”, Z. Zheng et al, Nature Electronics, Vol. 4, pp. 595-603, 2021]. This GaN inverter comprises an n-FET transistor1aconnected in series with a p-FET transistor1b.

The n-FET transistor1ais a conventional HEMT transistor especially comprising a silicon substrate11, a GaN channel layer12disposed on the substrate11, an AlGaN barrier layer13disposed on the channel layer12and a gate structure. The gate structure comprises a p-doped GaN layer14(p-GaN) and a gate electrode15ain contact with the p-GaN layer14(so-called p-GaN gate). The n-FET transistor1afurthermore comprises a drain electrode16aand a source electrode17ain ohmic contact with the 2-dimensional electron gas located in the immediate vicinity of the interface between the channel layer12and the barrier layer13.

The p-FET transistor1bcomprises the same stack of semiconducting layers11to14, a gate electrode15b, a drain electrode16band a source electrode17b. The p-GaN layer14forms a hole conduction layer which extends continuously between the drain electrode16band the source electrode17b. The portion of the p-GaN layer14located under the gate15bforms the channel region and is thinned so that it can be effectively (and electro-statically) controlled by the gate15b. This portion is subjected to an oxygen plasma treatment to depopulate the channel region of holes (at thermal equilibrium) and impart a normally-off behaviour to the p-FET transistor.

Because of the low mobility of the holes in the p-GaN 14 layer (compared with that of the electrons in the 2DEG), the current density of the p-FET transistor1bis about 100 times lower than that of the n-FET transistor1a. To be able to hold the same current, the p-FET transistor1btherefore has to have an active surface area around 100 times greater than that of the n-FET transistor1a, which increases the cost of the inverter.

SUMMARY OF THE INVENTION

There is therefore a need to provide a field effect transistor having the behaviour of a p-FET transistor and a high current density, typically of the same order of magnitude as that of an n-FET transistor formed from the same semiconductor materials.

According to a first aspect of the invention, this need tends to be satisfied by providing a field effect transistor comprising:a substrate;an electron channel layer disposed on the substrate;a barrier layer disposed on the electron channel layer;a hole channel layer disposed on the barrier layer;a p-type doped semiconductor material layer disposed on the hole channel layer;a source electrode comprising a first portion in ohmic contact with the electron channel layer and a second portion in ohmic contact with the p-type doped semiconductor material layer;a drain electrode in ohmic contact with the electron channel layer;a gate electrode disposed facing the p-type doped semiconductor material layer, between the source and drain electrodes.

The ohmic contact between the second portion of the source electrode and the p-type doped semiconductor material layer allows free holes to be injected into the hole channel layer when a negative voltage is applied between the gate electrode and the source electrode. These holes attract free electrons to the interface between the electron channel layer and the barrier layer, thus forming a conduction channel between the source electrode and the drain electrode. The field effect transistor then behaves as a p-FET transistor even though its conduction is provided by electrons.

In a first embodiment of the transistor, the p-type doped semiconductor material layer extends continuously from the source electrode to the drain electrode and the drain electrode is in Schottky contact with the p-type doped semiconductor material layer.

In a second embodiment, the p-type doped semiconductor material layer extends discontinuously from the source electrode to the drain electrode and the drain electrode is in ohmic contact with the p-type doped semiconductor material layer.

In addition to the characteristics just discussed in the preceding paragraphs, the transistor according to the first aspect of the invention may have one or more complementary characteristics from among the following, considered individually or according to any technically possible combination:the hole channel layer is made of an unintentionally doped semiconductor material;the electron channel layer and the hole channel layer are formed of a same material, for example unintentionally doped gallium nitride;the p-type doped semiconductor material layer is a p-type doped gallium nitride layer;the electron channel layer is comprised of unintentionally doped gallium nitride and the barrier layer is comprised of doped aluminium gallium nitride, preferably unintentionally doped aluminium gallium nitride;the gate electrode is separated from the p-type doped semiconductor material layer by a dielectric layer;the p-type doped semiconductor material layer has a concentration of doping impurities of between 1·1017cm−3and 1·1018cm−3;the barrier layer is comprised of aluminium gallium nitride and has an aluminium content of between 15% and 25%; andthe barrier layer is comprised of aluminium gallium nitride and has a thickness of between 2 nm and 10 nm.

A second aspect of the invention relates to an integrated circuit comprising:a substrate;an electron channel layer disposed on the substrate;a barrier layer disposed on the electron channel layer;a hole channel layer disposed on the barrier layer;a p-type doped semiconductor material layer disposed on the hole channel layer;a first source electrode comprising a first portion in ohmic contact with the electron channel layer and a second portion in ohmic contact with the p-type doped semiconductor material layer;a first drain electrode in ohmic contact with the electron channel layer;a first gate electrode disposed facing the p-type doped semiconductor material layer, between the source and drain electrodes;a second source electrode in ohmic contact with the electron channel layer;a second drain electrode in ohmic contact with the electron channel layer; anda gate structure disposed between the second source and drain electrodes;
the first source, drain and gate electrodes belonging to a field effect transistor according to the first aspect of the invention and the second source electrode, the second drain electrode and the gate structure belonging to a high electron mobility transistor.

The first drain electrode may be electrically connected to the second drain electrode so as to be subjected to the same electrical potential.

In a preferred embodiment, the gate structure of the high electron mobility transistor comprises a portion of the p-type doped semiconductor material layer and a second gate electrode disposed facing said portion.

For the sake of clarity, identical or similar elements are marked by identical reference signs throughout the figures.

DETAILED DESCRIPTION

FIG.2is a schematic cross-sectional view of a field effect transistor2according to a first embodiment. The field effect transistor2is an electronic component formed from III-N semiconductor materials. It has advantageous applications in power electronics.

The transistor2is similar to a p-FET (type) transistor in that it has a negative threshold voltage VTand a negative drain-source current IDS. However, unlike the p-FET transistor of prior art (whose conduction in the on state is provided by holes), the current of the transistor2(in the on state) is due to the transport of electrons. Transistor2is therefore an electron current transistor having a p-FET type behaviour (more simply, it will be referred to as an electron current p-FET transistor). Connected to one or more n-FET transistors, it can form logic gates, for example an inverter.

With reference toFIG.2, the transistor2comprises a substrate21and a vertical stack of semiconducting layers on the substrate21. This stack comprises at least:an electron channel layer22disposed on the substrate21;a barrier layer23disposed on the electron channel layer22;a hole channel layer24disposed on the barrier layer23; anda p-type doped semiconductor material layer25disposed on the hole channel layer24and hereinafter called the p-doped layer.

The substrate21is for example of silicon (Si), silicon carbide (SiC), gallium nitride (GaN) or sapphire (Al2O3). The electron channel layer22, the barrier layer23, the hole channel layer24and the p-doped layer25are semiconducting layers of III-V semiconductor material, preferably based on gallium nitride (GaN) (in other words GaN or a GaN alloy such as AlGaN, InGaN . . . ).

The electron channel layer22is the layer in which the conduction channel of the transistor2is formed. It is comprised of a first III-N semiconductor material. The barrier layer23is comprised of a second III-N semiconductor material having a bandgap greater than that of the first III-N semiconductor material (electron channel layer22), in order to create a potential barrier.

The discontinuity of the conduction band at the interface between the electron channel layer22and the barrier layer23forms, under certain bias conditions, a potential well in which the electrons are confined, thus creating a 2-dimensional electron gas (2DEG).

Thus, the transistor2comprises a first heterostructure comprising the electron channel layer22and the barrier layer23. The first heterostructure is for example of the GaN/AlGaN type. The electron channel layer22is then comprised of gallium nitride, preferably unintentionally doped gallium nitride (UID GaN), while the barrier layer23is comprised of aluminium gallium nitride, preferably unintentionally doped aluminium gallium nitride (UID AlGaN). A semiconductor material is considered unintentionally doped when its concentrations of donor type and acceptor type dopants are less than 1016cm−3(NA<1016cm−3and ND<1016cm−3). Preferably, the electron channel layer22has a thickness of between 20 nm and 500 nm, while the barrier layer23has a thickness of between 2 nm and 30 nm. The thickness of a layer is measured in a direction perpendicular to the substrate21.

The first heterostructure may also comprise an intermediate layer (not illustrated in the figure), disposed between the electron channel layer22and the barrier layer23, to increase the density and mobility of electrons in the 2-dimensional electron gas. Such an intermediate layer, also called a spacer layer, is typically extremely thin (thickness less than or equal to 1 nm) and can be comprised of aluminium nitride (AlN), this material being particularly adapted to the interface between an electron channel layer22of GaN and a barrier layer23of AlGaN.

The hole channel layer24is comprised of a third III-N semiconductor material having a bandgap smaller than that of the second III-N semiconductor material (barrier layer23). The third III-N semiconductor material (hole channel layer24) is preferably unintentionally doped. It is advantageously identical to the first III-N semiconductor material (electron channel layer22), for example unintentionally doped GaN. Preferably, the hole channel layer24has a thickness of between 5 nm and 300 nm.

Thus, the transistor2comprises a second heterostructure comprising the barrier layer23and the hole channel layer24. The second heterostructure is juxtaposed to the first heterostructure (also referred to as a double heterostructure, here GaN/AlGaN/GaN).

The p-doped layer25is preferably comprised of a fourth p-doped III-N semiconductor material. The p-doped layer25is for example a p-doped GaN (or p-GaN) layer. It has a concentration of p-type doping impurities which is advantageously between 1·1016cm−3and 5·1018cm−3. The thickness of the p-doped layer25can be between 5 nm and 40 nm. The doping impurities in the p-doped layer25are for example magnesium ions. The hole channel layer24and the p-doped layer25are preferably placed side by side, that is, disposed in direct contact.

The p-doped layer25is distinct from the hole channel layer24in that it has a doping different from the hole channel layer24(p-doping versus unintentionally doped).

Still with reference toFIG.2, the transistor2advantageously comprises a semi-insulating buffer layer26disposed between the substrate21and the electron channel layer22. This buffer layer26limits the lateral and vertical leakage currents in the transistor2and improves its (lateral) voltage withstand in the off state. The buffer layer26preferably comprises a III-N semiconductor material, such as GaN or AlGaN. This semiconductor material may be doped with impurities, such as carbon atoms. The buffer layer26can especially be formed by a single GaN:C layer or by a GaN:C/AlxGa1-xN bilayer, with x between about 4% and 8%. The thickness of the buffer layer26is for example between 1 μm and 15 μm.

In addition to the stack of semiconducting layers, the transistor2comprises a source electrode27, a drain electrode28and a gate electrode29. It may also comprise a dielectric layer30which covers the stack of semiconducting layers, and more particularly the p-doped layer25, between the source electrode27and the drain electrode28.

The source electrode27comprises a first portion27ain ohmic contact with the electron channel layer22and a second portion27bin ohmic contact with the p-doped layer25. The first and second portions27a-27bof the source electrode27are arranged so as to be subjected to the same electrical potential. They are preferably placed side by side (in other words in direct contact).

The first portion27amay extend vertically (that is, perpendicularly to the substrate21) to the electron channel layer22, as represented inFIG.2, to the interior of the barrier layer23or to the upper face of the barrier layer23. It is comprised of a metal material or several stacked metal materials. The first portion27aof the source electrode27is comprised, for example, of a two-layer stack comprising an aluminium layer disposed on a titanium layer (the titanium being in contact with the electron channel layer22or the barrier layer23, depending on the depth of the ohmic contact).

The second portion27bof the source electrode27may also be comprised of a metal material or of several stacked metal materials. These materials are advantageously different from those of the first portion27a. The second portion27bis for example comprised of a nickel/gold type two-layer stack (the nickel being in contact with the p-doped layer25) annealed for example under N2:O2at 560° C. for 40 minutes. Alternatively, the second portion27bmay be formed of a two-layer stack comprising a metal layer, for example magnesium, disposed on a heavily p-doped III-N semiconductor material layer (p++; concentration between 1018cm−3and 1020cm−3) in order to form a low resistive (ohmic) contact with the p-doped layer25.

The drain electrode28is in ohmic contact with the electron channel layer22. Advantageously, it is formed of the same metal material or the same stack of metal materials as the first portion27aof the source electrode27.

The gate electrode29is disposed facing the p-doped layer25between the source electrode27and the drain electrode28. It is preferably separated from the p-doped layer25by the dielectric layer30, as represented byFIG.2. Alternatively, the gate electrode29may be in Schottky contact with the p-doped layer25. The gate electrode29may be comprised of a metal material or of several stacked metal materials. It is for example formed of titanium nitride (TiN).

The dielectric layer30acts as a passivation layer by neutralising defects on the surface of p-doped layer25. It may be comprised of a single electrically insulating material, for example silicon dioxide (SiO2), silicon nitride (Si3N4), aluminium nitride (AlN) or alumina (Al2O3). Alternatively, the passivation layer may include a plurality of stacked sublayers formed of different insulating materials, typically alternating oxide (for example SiO2) and nitride (for example SiN) sublayers.

The operation of the transistor2will now be described in relation toFIGS.3and4. The electrical potentials of the source electrode27, the drain electrode28and the gate electrode29are denoted as VS, VDand VGrespectively.

When the gate-source voltage VGSis zero, for example when VG=VS=0 V (seeFIG.3), the p-doped layer25depletes the 2-dimensional electron gas located in the electron channel layer22in the immediate vicinity of the interface between the electron channel layer22and the barrier layer23(as in a p-GaN gate HEMT transistor). No (electron) current flows from the drain electrode28to the source electrode27when a negative drain-source voltage VDS(for example VD=−3 V) is applied. The transistor2is in the off state.

On the other hand, when a highly negative gate-source voltage VGSis applied, for example by choosing VG=−5 V and VS=0 V (seeFIG.4), free holes are injected into the hole channel layer24by the source electrode27through the p-doped layer25, by means of the ohmic contact between the second portion27bof the source electrode27and the p-doped layer25. These holes are distributed in the hole channel layer24from the source electrode27to the drain electrode28, due to the electric field generated by the negative drain-source voltage VDS(for example VD=−3 V). By electrostatic effect, they attract free electrons to the interface between the electron channel layer22and the barrier layer23, thus reconstituting a conduction channel40which electrically connects the source electrode27and the drain electrode28. In FIG.4, the conduction channel40is symbolised by dashed lines in the electron channel layer22along the interface between the electron channel layer22and the barrier layer23. An electron current flows in this channel40(from the drain electrode28to the source electrode27) under the effect of the electric field generated by the negative drain-source voltage VDS. The transistor2is in the on state.

The transistor2thus behaves as a normally-off type (no current under a zero gate voltage VGS) p-FET transistor (negative threshold voltage VTand negative current IDSunder a negative drain-source voltage VDS).

Unlike the 2-dimensional electron gas formed by heterojunction between the electron channel layer22and the barrier layer23(in the absence of the p-doped layer25), the conduction channel40does not have a uniform electron concentration. This is due to a non-uniform distribution of holes in the hole channel layer24and of the electric field as a result of the bias of the gate29.

The mobility of the electrons in the conduction channel40is nevertheless much greater than the mobility of the holes in a p-GaN channel layer. The transistor2therefore has a much higher current density than the p-FET transistor of prior art. The on state current density of the transistor2is of the same order of magnitude as that of a high electron mobility transistor (HEMT), since conduction in these two types of transistor is based on the same type of charge carriers.

FIGS.5to9represent different current-voltage characteristics of an example transistor according toFIG.2, obtained by means of TCAD electrical simulations. In this example, the transistor2comprises a 3 μm-thick GaN UID electron channel layer22, an AlGaN UID barrier layer23, a 10 nm-thick GaN UID hole channel layer24and a 5 nm-thick p-GaN p-doped layer25. The concentration of doping impurities (magnesium ions) in the p-doped layer25is equal to 3.1017cm−3, except in the simulation inFIG.5where this parameter varies. The aluminium content in the AlGaN barrier layer23is equal to 20%, except in the simulation inFIG.6where this parameter varies. The thickness of the AlGaN barrier layer23is equal to 5 nm, except in the simulation ofFIG.7where this parameter varies.

FIG.5represents (in logarithmic scale) the absolute value of the drain-source current IDS(denoted as |IDS|) as a function of the gate-source voltage VGS, for several values of the concentration of doping impurities (magnesium ions) in the p-doped layer25. This figure shows that the doping level of the p-doped layer25influences the off state current (the leakage current). The higher the concentration of doping impurities, the lower the off state current. This is due to greater depletion of the 2-dimensional electron gas. On the other hand, the doping level does not influence the on state current, because the free holes injected into the hole channel layer24do not come from the p-doped layer25. A concentration of doping impurities of between 1·1017cm−3and 1·1018cm−3is a good compromise between leakage current and threshold voltage.

It may also be noted that, in this example, the threshold voltage VTof the transistor is about −2 V and that the on state current density is in the order of 0.1 A/mm.

FIG.6represents the drain-source current |IDS| (still in logarithmic scale) as a function of the gate-source voltage VGS, for several values of the aluminium content in the AlGaN barrier layer23. This figure shows that the on state current of the transistor increases with the aluminium content in the barrier layer23. Indeed, the higher the aluminium content, the higher the level of positive bias in the barrier layer23at the interface with the electron channel layer22, and therefore the more electrons the conduction channel40contains. The leakage current also increases, as the 2-dimensional electron gas is less depleted in the off state. An aluminium content of between 15% and 25% is a good compromise between on state current and off state current.

FIG.7represents the drain-source current |IDS| (still in logarithmic scale) as a function of the gate-source voltage VGS, for several values of thickness of the AlGaN barrier layer23(denoted as tAlGaN). This figure shows that the on state current and off state current of the transistor increase with the thickness of the barrier layer23, as it induces a variation in its electric field linked to the bias charges. A thickness of between 2 nm and 10 nm is a good compromise between on state current and off state current.

FIG.8represents the drain-source current IDS(in linear scale) as a function of the drain-source voltage VDS, for several values of the gate-source voltage VGS. This figure shows a threshold effect in the increase of the drain-source current |IDS| (IDSin absolute value) when the drain-source voltage |VDS| increases. This threshold effect is characteristic of the Schottky diode formed by the second portion27bof the source electrode27, the p-doped layer25and the drain electrode28.

In other words, a threshold value of drain-source voltage |VDS| has to be exceeded in order to be able to inject holes into the hole channel layer24and create (by electrostatic effect) the conduction channel40.

FIG.8also shows that this threshold value of drain-source voltage |VDS| decreases when the gate-source voltage |VGS| increases, down to about |VGS|=3 V (VGS=−3 V).

FIG.9represents the drain-source current |IDS| (still in logarithmic scale) as a function of the gate-source voltage VGS, for several values of the position DG of the gate electrode29. The position DG of the gate electrode29is the distance separating the centre of the gate electrode29from the centre of the layers23to25(seeFIG.2). The position DG of the gate modifies the distribution of the electric field in the structure and influences the threshold voltage VTas well as the off state current. A position DG of between 0.4 μm and 0.8 μm is a good compromise between off state current and threshold voltage.

In the first embodiment illustrated byFIG.2, the p-doped layer25extends continuously from the source electrode27to the drain electrode28. The 2-dimensional electron gas is then completely depleted, which minimises the leakage current of the transistor2in the off state. The drain electrode28is in Schottky contact with the p-doped layer25, in order to avoid a hole current in the p-doped layer25.

FIG.10represents a second embodiment of the electron current p-FET transistor2. This second embodiment differs from the first embodiment (FIG.2) in that the p-doped layer25extends discontinuously from the source electrode27to the drain electrode28. More particularly, the p-doped layer25comprises several disjoint portions, a first portion25alocated facing, or in other words in vertical alignment with, the gate electrode29, a second portion25blocated in ohmic contact with the second portion27bof the source electrode27and a third portion25cin ohmic contact with the drain electrode28.

The ohmic contacts (between the source electrode27and the p-doped layer25, on the one hand, and between the drain electrode28and the p-doped layer25, on the other hand) make it possible to generate, in the on state, a hole current in the hole channel layer24, which is added to the electron current in the conduction channel40. The transistor2according to this second embodiment therefore benefits from a slightly higher current density than the transistor2according to the first embodiment (the hole current is much lower than the electron current, because of the lower mobility of the holes).

The drain electrode28can thus include, like the source electrode27, a first portion28ain ohmic contact with the electron channel layer22and a second portion28bin ohmic contact with the p-doped layer25. The first portion27aof the source electron27and the first portion28aof the drain electron28are preferably formed of the same metal material or materials. The second portion27bof the source electron27and the second portion28bof the drain electron28are preferably formed of the same material or materials (metal and/or heavily doped III-V semiconductor).

An example method for manufacturing the electron current p-FET transistor2will now be described in relation toFIGS.11A-11E. These figures schematically represent steps S1to S5for manufacturing the transistor2ofFIG.2.

Step S1illustrated byFIG.11Acomprises forming the stack of semiconducting layers on the substrate21. The stack is preferably formed from the substrate21by successively epitaxially growing the buffer layer26(if required), the electron channel layer22, the barrier layer23, the hole channel layer24and the p-doped layer25.

Step S1may furthermore comprise depositing the dielectric layer30, or passivation layer, onto the p-doped layer25. The passivation layer30preferably covers the entire upper face of the p-doped layer25. Depositing the passivation layer30and growing the semiconducting layers are preferably operations performed in the same equipment.

Step S2inFIG.11Bconsists in etching a portion of the passivation layer30so as to be able to access the p-doped layer25and subsequently form the second portion27bof the source electrode27. In other words, a portion of the p-doped layer25is uncovered. This first etching step S2, called the step of opening the ohmic contact on the p-doped layer25, is selective with respect to the p-doped layer25.

Step S3inFIG.11Cconsists in forming the second portion27bof the source electrode27, in ohmic contact with the p-doped layer25. As a reminder, the second portion27bmay comprise a so-called contact layer of a heavily p-doped (p++) III-N semiconductor material or a metal material layer, in direct contact with the p-doped layer25.

In a first embodiment of this step S3, forming the second portion27bcomprises depositing a first metal layer onto the uncovered portion of the p-doped layer25and onto the passivation layer30, and then etching the portion of the first metal layer disposed on the passivation layer30. The first metal layer may comprise several stacked sub-layers formed of different metal materials (for example Ni/Au).

In a second embodiment, forming the second portion27bcomprises (epitaxially) growing a p++-doped contact layer only on the uncovered portion of the p-doped layer25(the passivation layer30preventing growth otherwise).

In an alternative embodiment of the manufacturing method, (epitaxially) growing the p++-doped contact layer is performed in step S1of forming the stack of semiconducting layers, after growing the p-doped layer25and before depositing the passivation layer30. The p++-doped contact layer then completely covers the p-doped layer25. It is then etched to delimit the second portion27bof the source electrode27. And then, the passivation layer30is formed on the p-doped layer25where the p++-doped contact layer has been etched.

With reference toFIG.11D, the manufacturing method then comprises a step S4during which two cavities50intended to make the drain and source electrodes are etched into the stack of layers. This step S4is called the step of opening the source and drain contacts. Etching may extend to the upper face of the barrier layer23(therefore through the passivation layer30or the p++-doped contact layer, the p-doped layer25and the hole channel layer24), to the interior of the barrier layer23(the barrier layer23is furthermore etched over part of its thickness) or, as represented byFIG.11D, to the interior of the electron channel layer22(the barrier layer23is etched over its entire thickness and the electron channel layer22is etched over part of its thickness).

Finally, step S5inFIG.11Econsists in forming the first portion27aof the source electrode27and the drain electrode28in the cavities50, as well as the gate electrode29on the passivation layer30, facing the p-doped layer25. The first portion27aof the source electrode27is formed so as to be in contact with the second portion27b.

Advantageously, the first portion27aof the source electrode27and the drain electrode28are formed simultaneously, by depositing and etching a second metal layer. Like the first metal layer, the second metal layer may comprise several stacked sub-layers formed of different metal materials. The second metal layer is preferably deposited onto the entire surface of the substrate (“full plate deposition”), in other words at the bottom and against the side walls of the cavities50, onto the second portion27bof the source electrode27and onto the passivation layer30. And then, the portion of the second metal layer disposed on the passivation layer30is etched (selectively with respect to the passivation layer30).

The gate electrode29may also be formed by depositing and etching a third metal layer (said third metal layer may comprise several sub-layers), before or after the first portion27aof the source electrode27and the drain electrode28.

To manufacture the transistor2ofFIG.10, the step S1of forming the stack may furthermore comprise an operation of etching the p-doped layer25, selectively with respect to the hole channel layer24. This etching operation is preferably performed before the operation of depositing the passivation layer30, such that the latter also covers the uncovered part of the hole channel layer24. Because of this selective etching step, the transistor2ofFIG.10is more difficult to make than the transistor2ofFIG.2.

The structure of the electron current p-FET transistor2is remarkable in that it is very close to that of a conventionally designed HEMT transistor, and more particularly a p-GaN gate HEMT transistor. It therefore becomes easy to integrate an electron current p-FET transistor2and a HEMT type n-FET transistor on a same substrate.

FIG.12represents a preferred embodiment of an integrated circuit100comprising an electron current p-FET transistor2and a HEMT transistor3.

This integrated circuit100comprises the substrate21and the stack of semiconducting layers previously described in relation toFIG.2. A first part of the stack is dedicated to the formation of the electron current p-FET transistor2and a second part of the stack is dedicated to the formation of the HEMT transistor3. An electrical insulation trench110electrically insulates the part of the stack dedicated to the electron current p-FET transistor2and that dedicated to the HEMT transistor3. The electrical insulation trench110extends at least through the p-doped layer25, the hole channel layer24, the barrier layer23and part of the electron channel layer22(so as to electrically insulate the conduction channel40of the p-FET transistor2and the 2DEG of the HEMT transistor3).

In addition to the second part of the stack, the HEMT transistor3comprises:a source electrode31in ohmic contact with the electron channel layer22;a drain electrode32in ohmic contact with the electron channel layer22; anda gate structure33disposed between the source and drain electrodes31-32.

The drain electrode28of the p-FET transistor2can be electrically connected to the drain electrode32of the HEMT transistor3so as to be subjected to the same electrical potential. The two transistors are then connected in series, forming the base of an inverter.

In this preferred embodiment, the gate structure33of the HEMT transistor3comprises a portion331of the p-doped layer25, for example of p-GaN, and a gate electrode332disposed facing said portion331. Thus, the gate structure33is a p-GaN type gate structure.

The portion331of the p-doped layer25is separated from the source electrode31and the drain electrode32of the HEMT transistor3by a portion of the passivation layer30. The gate electrode332can be separated from the portion331of the p-doped layer25by the passivation layer30, as illustrated byFIG.12, or on the contrary be placed side by side with said portion331.

In an alternative embodiment of the integrated circuit100illustrated byFIG.13, the HEMT transistor3comprises an MOS type gate structure33, that is, a gate structure33comprising a gate dielectric layer333(for example formed of the same dielectric material as the passivation layer30) and a gate electrode334(typically of metal). The gate electrode334is separated from the electron channel layer22and the barrier layer23by the gate dielectric layer333. The gate structure33is called buried, because in this alternative embodiment it extends through the barrier layer23to the electron channel layer22(to “cut” the 2DEG in two). The p-doped layer25and at least part of the hole channel layer24have advantageously been removed in the second part of the stack dedicated to the HEMT transistor3. The electron current p-FET transistor2is identical to that represented byFIGS.2and12.

Naturally, all these embodiments of the integrated circuit100are compatible with the electron current p-FET transistor2illustrated inFIG.10. The operation of selectively etching the p-doped layer25is then advantageously performed for both transistors simultaneously.