Semiconductor device comprising an isolation trench including semiconductor islands

The present invention provides semiconductor devices and methods for fabricating the same, in which superior dielectric termination of drift regions is accomplished by a plurality of intersecting trenches with intermediate semiconductor islands. Thus, a deep trench arrangement can be achieved without being restricted by the overall width of the isolation structure.

FIELD OF THE INVENTION

The present invention generally relates to the field of high voltage semiconductor devices, and more specifically to isolation structures capable of electrically isolating (blocking) high voltage devices, such as lateral high voltage devices in thick-film SOI power integrated circuit technologies.

High voltage (HV) semiconductor devices such as diodes, transistors and IGBTs insulated gate bipolar transistors), usually include more or less heavily doped semiconductor areas so as to define a pn junction. In HV applications, which are to understood as applications requiring the handling von approximately 60 V and higher, such as 100V and more, for instance up to several hundred Volts, usually contain a dedicated pn junction, which depletes in the off-state and supports the off-state voltage, i.e., the depleted region electrically isolates the p-doped region and the n-doped region from each other. This part is called “drift region”, “lowly-doped region” or “voltage supporting region”. To those skilled in the art, the engineering of this drift region is well-established.

The high voltage device is embedded in a semiconductor substrate or material, which is normally held at a low voltage. For this reason high voltage semiconductor devices also contain isolation regions, which electrically isolate the device from the surrounding substrate. These isolation regions ensure that the high voltage is contained within the high voltage device and that the high voltage does not negatively impact the surrounding devices and the package.

Electrical isolation is achieved either by reverse-biased pn-junctions or by dielectric materials. Junction isolation utilizes similar lowly-doped regions as the drift region of the HV device. In order to be effective these isolation areas must have a higher voltage carrying capability than the interior device. In this way the voltage rating is given by the interior device only. For high voltages beyond about 100V large radii of curvature are required at respective “corners” of the interface between the interior device and the isolation region so as to minimize 2-dimensional (2D) and 3D effects of the electric field distribution which will otherwise limit the voltage carrying capability of the junction isolation area. Such curved sections with increased radii of curvature surrounding the HV device therefore increase the area requirement in the substrate for the HV device.

For lateral high voltage devices such as LDMOS, LIGBT, the lowly-doped drift region not only needs to be isolated from the surrounding substrate. The drift region also needs to be terminated in such a way that the carefully engineered field or potential distribution is not altered, since only this case the full voltage rating of the HV device can be realized. In junction isolation this requirement is achieved by rounded and oval portions commonly referred to as racetrack design. A disadvantage of these racetrack portions is that the required large inner radii increase the size of the core device. In particular, the pitch of lateral HV devices becomes larger than predicted from 2D considerations. Hence, great efforts are being made to improve this fundamental design requirement of junction isolation.

Another technique to isolate the device and terminate the drift region is dielectric isolation. Here, the task of isolation and drift region termination is fundamentally simpler. Vertical isolation is realized by using SOI (Silicon on Insulator) material, which contains a BOX (Buried Oxide) layer between the active top layer and the handle wafer substrate. Lateral isolation is achieved by forming oxide filled trenches or field oxide reaching all the way down to the BOX.

An efficient electric insulation can be achieved with relatively small geometries, due to the high electric field strength of common dielectric materials, such as silicon dioxide, silicon nitride and the like. Also, large radii of curvature are not strictly required as only the electric field strength needs to be considered, while 2D and 3D effects according to semiconductor device physics may be neglected due to the dielectric nature of the isolating material. Thus the area consumption of dielectric isolation and termination is small, when compared to junction isolation.

In thin-film SOI, with a thickness of the top silicon layer on the order of 1 μm or less, shallow trench isolation (STI) or local oxidation of silicon (LOCOS) is used to form the lateral isolation and termination. This form of isolation has practically no limitation on the width of the isolation structure, as shown inFIG. 1andFIG. 2.

FIG. 1schematically illustrates a cross-sectional view of a semiconductor device1that comprises a substrate4, for instance a handle wafer, a buried oxide layer3and a silicon layer2formed on the buried oxide layer3. Furthermore, a trench5is formed in the silicon layer2and extends to the buried oxide layer3. Hence, the depth5dof the trench5substantially corresponds to the thickness of the silicon layer2, when a pronounced etching into the buried oxide layer3has been avoided during the preceding patterning process for forming the trench5. As discussed above, the trench5has also a width5wthat is appropriate for providing the desired insulating effect after being filled with a dielectric material, such as silicon dioxide. As discussed above, for a thin-film SOI architecture the width5wof the trench5is typically significantly greater than the depth5dthereof. The trench5can be fabricated on the basis of well-established manufacturing techniques including lithography and etch techniques for etching material of the silicon layer2selectively to an etch mask and the buried oxide layer3.

FIG. 2schematically illustrates the device1at a further advanced manufacturing phase, in which the trench5is filled with a dielectric material6, such as silicon dioxide. The deposition of the material6is accomplished by CVD (chemical vapour deposition), and the like using well-known deposition recipes. As illustrated, the material6can be deposited with a thickness6dthat is greater than the depth5dof the trench5, due to the moderately low depth5dof the thin-film SOI configuration, thereby enabling a complete and reliable filling of the trench5, since the filling process, at least in the centre of the trench5, advances from bottom to top, while the growth of the material6from the sidewalls is less pronounced due to the small aspect ratio defined by the depth5dto the width5w.

Thus, by using the shallow but wide trench5filled with the material6as an isolation structure, lateral HV devices can efficiently be isolated from the surrounding material of the layer2and therefore can be readily implemented into a thin-film SOI technology.

On the other hand, when using deep trenches for isolation, the width of such trenches is limited to a few microns. This situation is due to the fact that filling the trenches with dielectric layers is realized by depositing such layers on the trench sidewalls, as will be explained with reference toFIGS. 3 and 4.

FIG. 3schematically illustrates a cross-section view of the semiconductor device1according to a thick-film SOI architecture. As illustrated, the device1comprises the trench5as a deep trench due to an increased thickness of the silicon layer2, which may range from several μm to several tens of μm. In the example shown, the width5wis substantially smaller than the depth5dof the trench5inFIG. 3in order to enable a reliable filling of the trench5with a practicable thickness of a dielectric material.

FIG. 4schematically illustrates the device1according to the thick-film SOI architecture, wherein the trench5is filled with the dielectric material6, which has now a thickness6dthat is at most half the width5d. Hence, during the deposition process for forming the material6the trench5is filled from the sidewalls, thereby allowing a complete filling with the thickness6dof the material6being less than the depth5dof the trench5. In this case, however, the width5wis restricted to moderately small values.

As explained above with reference toFIG. 1andFIG. 2, very wide trenches would require very thick dielectric films to fill relatively deep trenches, but this is expensive and to leads to difficulties during standard CMOS manufacturing due to stress that may be created in the dielectric material during the deposition thereof. Hence, it is very difficult to fill wide and deep trenches, unless creating a severe topography.

FIG. 5schematically illustrates the device5when the trench5represents a deep and moderately wide trench. When “filling” the trench5with the dielectric material6having a thickness6dthat is similar to the thickness6dofFIG. 4, a hole of gap6aremains after planarization and such surfaces are very difficult to be manufactured in a standard planar semiconductor process. Thus, the width5wof the deep trench5is limited to twice the dielectric layer thickness6dat best. Again, this property of DTI (deep trench isolation) is a fundamental contrast to STI (shallow trench isolation), which fill from the bottom and thus have no width constriction, as is explained above with reference toFIG. 1andFIG. 2.

For a purely electric HV isolation, this width limitation of a deep trench is not an issue. For example, a one micron wide oxide-filled trench can isolate several 100's of volts.

However, when using an isolation trench for the lateral termination of depleted drift regions the limited width of the trench degrades the achievable breakdown voltage. The semiconductor area outside the HV device acts as a field plate and changes the potential distribution in the drift region, as will be described with reference toFIGS. 6 to 9.

FIG. 6schematically illustrates a top view of a conventional device1, which comprises a HV element in the form of a PIN (p-doped, intrinsic, n-doped) diode7, which is laterally isolated by the isolation structure5having wide width. Moreover, as previously discussed, the diode7is vertically isolated by a buried oxide layer (not shown). The diode7represents a HV device, i.e., a device that may be operated with voltages of 100 V and higher. The diode7comprises a p-doped region7aand an n-doped region7ceach having a dopant concentration as required for obtaining the desired diode functional behaviour. Moreover, a drift region7bis laterally positioned between the regions7a,7c. As discussed above, the drift region7ctypically has a lower dopant concentration compared to the regions7aand7cso as to allow a depleted area to form upon applying a reverse bias voltage. The depletion zone in the drift region7bthus provides for the desired electric field strength or dielectric strength in the reverse bias mode.

FIG. 7schematically illustrates the device1, when the diode7is operated in a reverse bias mode, wherein uniformly spaced potential lines8(lines of constant electric potential) allow the highest breakdown voltage V1, which is physically possible in this arrangement. That is, the isolation structure5is provided with a sufficiently great width so as to not affect the distribution of the potential lines8.

FIG. 8depicts the device1when comprising the isolation structure5based on a reduced width5w, i.e., the isolation structure5represents a narrow trench isolation that separates the device7from the surrounding semiconductor layer2, which may be provided in the form of p-doped material. The doping of layer2is of less importance.

FIG. 9shows the device1in the reverse bias mode, wherein the potential lines8crowd around the region7c, which may be at a high yet reduce positive voltage compared to the arrangement ofFIG. 7. This field crowding in the vicinity of the region7cthus leads to a substantially smaller breakdown voltage V2due to the increased distance of potential lines8in the drift region7bin this configuration compared to the substantially non-influenced configuration described with reference toFIG. 7.

FIG. 10schematically illustrates the device1, wherein the trench isolation structure5has an increased width at least an area adjacent to the drift region7b. In order to significantly reduce the influence of the isolation structure5on the finally obtained dielectric strength of the drift region7bin the reverse bias mode, the width5wis selected to be at least in the range or order of the drift region width7w. In this case the potential lines are uniform in reverse bias mode and the electric field is uniform and hence, the breakdown voltage is as high as V1inFIG. 7.

FIG. 11illustrates the device1in the above described arrangement. That is, the potential lines8may have a substantially equal spacing within the drift region7band the adjacent portion of the trench isolation structure5having the width5w, thereby providing for the desired high dielectric strength of the drift region7b.

In thick SOI technologies, however, it is very difficult to terminate the drift region7bdielectrically using deep trenches, as is shown inFIG. 11, because they can not be filled with a dielectric material without creating undesired topography or causing significant stress, as previously discussed. Hence, junction isolation is commonly used to terminate the drift region in thick-film SOI technologies and therefore, the same area penalty applies as in HV bulk technologies. Additionally, the DTI of reduced width is then used to isolate the internally junction-terminated HV device dielectrically to the substrate.

SUMMARY OF THE INVENTION

It is therefore an object of the claimed invention to provide semiconductor devices having an efficient isolation structure while avoiding one or more of the problems identified above.

Generally, the present invention provides a semiconductor device and a method of fabricating the same, wherein a dielectric termination of a semiconductor region used for accommodating a specified reverse voltage is accomplished by providing deposition conditions that are compatible with CMOS manufacturing techniques while at the same time providing an effective total width of the isolation structure that corresponds to a wide trench isolation configuration. The effective desired wide isolation width is obtained by selecting a width as required for obtaining a desired distribution of the potential lines, wherein additionally isolated semiconductor regions are maintained within the isolation structure in order to provide a geometry during the deposition of the insulating material that allows a reliable filling of the trenches with a layer thickness of the insulating material that is less than the trench depth. Hence, during the deposition of the insulating material the device geometry is similar to the situation encountered during the filling of deep narrow trenches, while on the other hand, the remaining semiconductor portions or islands do not significantly influence the overall distribution of the electric field within the isolation structure, thereby achieving the desired “wide trench” behaviour adjacent to the semiconductor region accommodating the specified reverse voltage.

It should be appreciated that a semiconductor region that is provided with an appropriate dopant concentration and size so as to provide a desired electric field strength or dielectric strength when operated in a depleted mode will also be referred to as a drift region.

According to one aspect the object is solved by a semiconductor device that comprises a first semiconductor region formed above a substrate, wherein the first semiconductor region comprising a drift region. A second semiconductor region is formed above the substrate and laterally encloses at least a portion of the first semiconductor region. The semiconductor device further comprises an isolation structure positioned laterally between at least the drift region and the second semiconductor region, wherein the isolation structure comprises a first plurality of isolation trenches filled with an insulating material and extending along a first lateral direction and being spaced apart by portions of semiconductor material having a first width along the first lateral direction. The isolation structure further comprises a second plurality of isolation trenches filled with the insulating material and extending along a second lateral direction and being spaced to apart by the portions of semiconductor material having a second width along the second lateral direction, wherein the first and second plurality of isolation trenches form a plurality of intersection areas.

Hence, the isolation structure of the semiconductor device comprises semiconductor portions embedded in the insulating material, thereby providing for an enhanced topography of the isolation structure irrespective of the lateral size and the depth thereof. Additionally, the semiconductor portions do not adversely affect the field distribution in the isolation structure and thus in the adjacent drift region.

In a further embodiment each of the first and second portions of semiconductor material is electrically insulated from the drift region so that insulating material is positioned next to and adjacent to the drift region.

In a further embodiment, for each isolation trench of the first and second pluralities of isolation trenches a depth thereof is greater than a width. Therefore, an isolation regime is established in which each of the individual isolation trenches represents a “deep trench” configuration, which may be advantageously used in applications requiring a moderately large extension of the semiconductor circuit elements along a depth direction, as is, for instance, the case in thick-film SOI architectures.

In one embodiment the depth is 1 μm or more, while in other embodiments the depth is 5 μm or more, thereby providing increased design flexibility with respect to dielectric strength and drive current capability of the circuit elements.

In a further embodiment the semiconductor circuit element further comprises a p-doped region and an n-doped region that are laterally separated by the drift region. Hence, any circuit elements may be formed that require a specified electric field strength of the drift region when inversely biased, wherein the electric field strength can be adjusted in a space-efficient manner within a wide range. The field strength is considered a synonym for dielectric strength.

In one illustrative embodiment the drift region has a first lateral dimension oriented along a current flow direction between the p-doped region and the n-doped region, wherein the isolation structure has a width along a lateral direction perpendicular to the current flow direction and wherein the width is at least 0.5, preferably about 0.8 to 1.2 times the first lateral dimension. Consequently, the isolation structure may dielectrically terminate the drift region such that the distance between equidistant potential lines in to the drift region and isolation structure is comparable, thereby suppressing or at least reducing any undue modification of the dielectric strength of the drift region.

In further embodiments the semiconductor circuit element is one of a diode structure, a field effect transistor a bipolar transistor and an insulated gate bipolar transistor. Thus, the power circuit elements for many applications may be provided by using the enhanced isolation structure.

In a further preferred embodiment the portions of semiconductor material form a regular array. Hence, the distribution of the potential lines may appropriately be adjusted by selecting the size and configuration of the array, which is to be understood as a two-dimensional array that comprises individual and separated array elements along two linearly independent lateral directions. For example, if the semiconductor portions, i.e., the array elements are electrically floating, a substantially non-disturbed field distribution may be obtained by selecting the size and position of the semiconductor portions in an appropriate manner within the regular array while also not exceeding a specified “maximum” distance between adjacent two of the array elements in order to provide the superior deposition geometry during the deposition of the insulating material into the array of semiconductor portions. Some or all of the array elements may be connected to one or more specific reference potentials, thereby allowing a specific patterning of the field distribution in the isolation structure based on the configuration of the array.

In a further embodiment the first and second widths of the portions of semiconductor material are formed on the basis of the same design width. That is, the first and second widths are equal to each other except for process induced variations. For example, the portions of semiconductor material are provided in the form of square-like “islands” within the insulating material of the isolation structure.

In one preferred embodiment the semiconductor device further comprises a buried insulating layer formed below the first and second semiconductor regions to define an SOI configuration. Hence, sophisticated SOI devices including HV devices, such as thick-film SOI architectures, having a thickness of the first and second semiconductor regions of 1 μm or more, and thin-film SOI architectures, having a thickness of the first and second semiconductor regions of less than 1 μm, may efficiently be realized with increased design flexibility and reduced area penalty compared to conventional techniques as described above.

In another embodiment the first and second pluralities of isolation trenches extend to the buried insulating layer. In this manner, the intermediate portions of semiconductor material are electrically isolated from each other, so that the field distribution remains substantially non-affected by the portions of semiconductor material.

The trenches may terminate in semiconductor material, for instance above a buried insulating layer or in the substrate material of a bulk configuration.

According to another aspect of the present invention the object is solved by a method of forming a semiconductor device. The method comprises a step of forming a plurality of intersecting trenches in a semiconductor layer adjacent to a drift region of a semiconductor circuit element. Additionally, the plurality of intersecting trenches is filled with a dielectric material to form an isolation structure laterally separating the drift region from semiconductor material.

Due to the plurality of intersecting trenches intermediate semiconductor material is preserved during the patterning of the trenches so that enhanced conditions during the filling in of dielectric material are achieved.

In a further embodiment the plurality of intersecting trenches is formed so as to extend to a buried insulating layer located below said semiconductor layer.

In another embodiment the plurality of intersecting trenches is formed so as to form electrically isolated portions of the semiconductor layer, each of which is electrically isolated from the drift region.

In one illustrative embodiment the method further comprises: forming the drift region so as to provide a depletion zone for accommodating a reverse bias voltage of 100 V or higher. Hence, HV voltage circuit elements, such as diodes, transistors, IGBTs, and the like may be fabricated by using the inventive concept.

Preferably, forming the isolation structure comprises: selecting a target lateral dimension of the isolation structure along a direction perpendicular to a current flow direction in the drift region, wherein the target lateral direction corresponds to a length of a depletion zone forming along the current flow direction when applying a rated reverse bias voltage.

In this way, the effective size of the isolation structure may efficiently adapted to the drift length provided by the drift region when operated in the reverse bias mode.

In a further embodiment the plurality of intersecting trenches comprises first trenches that are oriented perpendicular to second trenches, thereby providing for an efficient overall layout of the isolation structure.

In a further embodiment a spacing between adjacent two of the first plurality of isolation trenches is selected to be equal to a spacing between adjacent two of the second plurality of isolation trenches, thereby obtaining a regular array of intermediate portions of semiconductor material.

In one embodiment the step of filling the plurality of intersecting isolation trenches comprises: depositing a dielectric material with a layer thickness that is less than a depth of each of the plurality of intersecting isolation trenches. Thus, a “deep trench” arrangement is obtained for each of the intersecting isolation trenches, while at the same time a desired effective large width of the isolation structure as a whole is achieved.

The present invention thus allows the dielectric side termination of the drift region of high voltage devices with deep trench isolation (DTI). The advantage is a reduced area requirement for HV devices in thick-film SOI technologies, comparable to that of thin-film SOI technologies. Other advantages are simple design and flexibility with regard to voltage rating of the devices.

DETAILED DESCRIPTION OF EMBODIMENTS

With reference toFIGS. 12 to 16further embodiments of the present invention will now be described, wherein also reference is made toFIGS. 1 to 11, if required. It should be appreciated that throughout the figures similar or like features are denoted by the same reference numerals, irrespective of whether theses features correspond to conventional semiconductor devices or to semiconductor devices according to the present invention. Moreover, any positional statements in the description or the claims are to be understood as ‘relative’ position information based on an appropriate reference, such as the substrate surface of the carrier material of the semiconductor device. Hence, a lateral direction is to be considered as a direction parallel to the reference plane, while a depth direction or a vertical direction is a direction that is perpendicular to the lateral directions.

FIG. 12illustrates a top view of a semiconductor device1comprising a first semiconductor region2ain and above which is formed a semiconductor circuit element7, such as a diode, a field effect transistor, an IGBT, and the like. In the embodiment shown the circuit element represents a diode that is designed for HV applications, i.e., for voltages of approximately 100 V and higher. The circuit element7comprises a drift region7b, which connects, along a current flow direction indicated as L, at one end to a p-doped region7aand at the other end to an n-doped region7c. As previously discussed with reference toFIGS. 1 to 11, the drift region7bis appropriately configured with respect to dopant profile and size so as to provide a desired high electric field strength (or: dielectric strength) when operated in the reverse bias mode. Furthermore, the device1comprises a second semiconductor region2b, which is laterally isolated from the first semiconductor region2aand thus from the circuit element7by an isolation structure5. The isolation structure5connects to the drift region7band has an effective width5walong a lateral direction W that is perpendicular to the direction L. The width5wis selected such that a desired field distribution is achieved that may be compatible with the “dielectric requirements” (HV-requirements) of the drift region7b, as is also discussed above. In the embodiment shown the width5wis selected so as to be comparable to a “length”7lof the drift region, thereby insuring a reduced modification of the field distribution in the drift region7bin the reverse bias mode. For example, the width5wis selected to be about 0.5, or preferably 0.8 to 1.2 times the length7b. The width5wmay be selected, however, in any other manner as demanded by the design to requirements, wherein advantageously the width5wand a depth of the isolation structure may be selected independently from each other without causing an undue topography. For this purpose, the isolation structure5comprises a plurality of at least laterally isolated portions or islands2cof semiconductor material, which can be considered as a spacing between a plurality of intersecting isolation trenches5a,5b. is For example, the trenches5arepresent a plurality of trenches extending along the lateral direction W, while the trenches5bextend along the direction L and intersect the trenches5aat respective intersect areas5c. Thus, the width of the individual trenches5a,5bmay be selected so as to comply with the gap fill capabilities of a deposition process used to fill the isolation structure5with a dielectric material6, such as silicon dioxide, silicon nitride, and the like. Moreover, a first trench5fof the trenches5bis positioned immediately adjacent to the drift region7b, thereby avoiding a direct contact of any of the islands2cwith the drift region7b. In the embodiment shown, the trenches5a,5band thus the portions or islands2cdefine a regular array, which may thus efficiently be used for adjusting the field distribution in the isolation structure5in a precise and predictable manner. Furthermore, in the embodiment ofFIG. 12, the portions2chave substantially the same width along the lateral directions L, W, that is, a width21may be equal to a width21, except for any process related variations.

FIG. 13schematically illustrates a section along the line XIII ofFIG. 12. As illustrated, the device1comprises a substrate4and a buried insulating layer3, such as an oxide layer, on which are formed the portions2cand the dielectric material6. In the manufacturing stage shown, the material of the layer6may still be formed so as to extend above the portions2c, wherein any excess material can be removed in a later stage, for instance, by CMP (chemical mechanical polishing), etching, and the like. Moreover, a depth5dof the isolation structure5, i.e., a depth of trenches5a, is, in this embodiment, greater than a width5lof the trenches and also greater than the width2lof the portions2c. Hence, in this case for each of the individual trenches5aa “deep trench” configuration can be established without creating a pronounced surface topography, for instance due to any holes or gaps, as is previously discussed with reference toFIG. 5.

FIG. 14schematically illustrates a section along the line XIV ofFIG. 12. As illustrated, the trenches5bhave a width5uand the depth5d, wherein the width5uand also the width2wof the portions2care less than the depth5d, thereby also providing for a “deep trench” configuration for the trenches5b. Moreover, the first trench5fprovides for the lateral isolation of the portions2cfrom the drift region7b, as also previously explained. It should be appreciated that the lateral dimensions5u,5lmay be different, if considered appropriate for the overall field distribution in the isolation structure5.

The semiconductor device1may be fabricated on the basis of well-established process techniques, such as CMOS manufacturing strategies. That is, prior to or after defining an active area for the circuit element7, an etch process may be performed on the basis of an etch mask that is formed by using a lithography mask including a pattern which corresponds to the desired configuration of the trenches5a,5b. Thus, the lithography process creates an etch mask that defines the width5u,5lof the trenches as well as the number thereof, so that the total width5wof the isolation structure is obtained. Furthermore, the overall lateral shape of the isolation structure5is defined so as to correspond to the desired lateral size of the circuit element7and of the second semiconductor region2b. For example, the portion of the isolation structure5having the width5wmay not necessarily extend along the entire length of the circuit element7along the direction L, but only the first trench5fmay be the non-critical region7a, or at least a significant portion thereof.

After etching the trenches5a,5binto the semiconductor material2down to a specified depth, for instance down to the buried insulating layer3, when an SOI configuration is considered, thereby forming the first and second semiconductor regions2a,2b, the trenches5a,5bare filled with the insulating material6. During the deposition process the portions2cprovide for a device geometry that results in a fill behaviour as is previously described with reference toFIG. 4. Consequently, deposition techniques, such as CVD, may be applied that are compatible with the entire manufacturing flow, since any undue topography that would unduly affect the further processing is avoided while also the required thickness of the material6is moderately small, as discussed with reference toFIG. 4. Thereafter excess material may be removed and the further processing may be continued by forming the circuit element7, for instance by incorporating the dopant species for the regions7aand7c, or forming gate electrode structures for field effect transistors and IGBTs, and the like.

FIG. 15schematically illustrates a cross-sectional view of the device1according to an embodiment, in which a bulk configuration is used in combination with the isolation structure5. As illustrated, the substrate4represents a semiconductor material, such as silicon, and the portions2care formed in the substrate4so as to extend to a desired depth. In this case at least some of the portions2cmay electrically be connected via the substrate4, while in other embodiments a vertical isolation may be achieved by providing an “isolation” layer4athat is in contact with the portions2c. For example, the isolation layer4arepresents a doped material layer of the substrate4so as to obtain a junction isolation between the remaining substrate4and the portions2c. In other to embodiments the layer4amay isolate some of the portions2cwhile other portions2care in contact with the substrate4, thereby enabling enhanced flexibility of adjusting the overall field distribution within the isolation structure5and thus within the drift region7b.

FIG. 16schematically illustrates the device ofFIG. 12, when operated in the reverse bias mode. In the reverse bias mode a positive voltage V1is applied to the region7c, while the region7aand the second semiconductor region2bare held at 0 V. Since the width5wis appropriately adapted to the length7lof the drift region7bthe potential lines8may substantially not be distorted at the sides of the drift region7bthat is terminated by the isolation structure5. The deep trenches5a,5bare arranged in a matrix, such that the small semiconductor islands2cremain as, thereby effectively forming a wide dielectric region compatible with DTI process technology, i.e. the trenches5a,5bare completely filled with the dielectric film6. On the other hand this matrix of deep trenches5a,5bbehaves electrically like a single wide trench. The semiconductor islands2cdo substantially not disturb the potential distribution because, in this embodiment, they are electrically floating. In this case, the potential distribution in the drift region7bis uniform and the reverse bias reaches the breakdown voltage V1of an ideal HV diode.

Hence, a scalable and simplified HV termination for drift regions is obtained. This provides real area savings compared to conventional strategies. Furthermore, the present invention is applicable to any SOI technique and also to bulk architectures.