Manufacturing method of semiconductor device

A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.

BACKGROUND

Technical Field

The disclosure relates to a manufacturing method of an integrated circuit, and particularly relates to a manufacturing method of a semiconductor device.

Description of Related Art

According to the increase of the demand for high-performance circuits, semiconductor-on-insulator (SOI) technology has attracted much attention because the traditional bulk metal-oxide-semiconductor field-effect transistor (MOSFET) structure cannot overcome issues, such as short-channel effects, parasitic capacitance, and current leakage.

In the SOI technology, an insulating layer (e.g., a buried oxide (BOX) layer) is formed between a MOSFET device and a bulk substrate. Therefore, the MOSFET device has a smaller parasitic capacitance and thus exhibits more desirable speed properties in circuit operations. With the advantages of the SOI technology, it is expected that the SOI MOSFET device will become the mainstream device structure. Recently, the SOI technology are appealing for high frequency applications, such as radio frequency (RF) communication circuits. However, there are still some challenges to overcome.

SUMMARY

Accordingly, the present disclosure provides a manufacturing method of a semiconductor device to reduce stresses of interconnection structures and achieve the desired electrical characteristics thereof. Moreover, the performance of the device structure and the performance of second harmonic distortion are improved simultaneously.

A manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.

According to some embodiments of the disclosure, the first temperature is higher than the second temperature.

According to some embodiments of the disclosure, the first temperature is between 350° C. and 450° C.

According to some embodiments of the disclosure, the second temperature is between 150° C. and 250° C.

According to some embodiments of the disclosure, the gas mixture includes 10% to 20% of hydrogen.

According to some embodiments of the disclosure, the gas mixture further includes nitrogen, helium, neon, argon, or a combination thereof.

According to some embodiments of the disclosure, the first annealing process is performed between 30 minutes and 2 hours.

According to some embodiments of the disclosure, the second annealing process is performed between 30 minutes and 2 hours.

According to some embodiments of the disclosure, a material of the first interconnection structure includes Al, Al alloy, Cu, Cu alloy, or a combination thereof.

According to some embodiments of the disclosure, a material of the second interconnection structure includes Al, Al alloy, Cu, Cu alloy, or a combination thereof.

According to some embodiments of the disclosure, the first interconnection structure includes a plurality of dielectric layers and a plurality of circuit structures.

According to some embodiments of the disclosure, the second interconnection structure includes a plurality of dielectric layers and a plurality of circuit structures.

According to some embodiments of the disclosure, the second interconnection structure is electrically connected to the device structure and the first interconnection structure.

According to some embodiments of the disclosure, the manufacturing method further includes bonding the substrate with a wafer via the front side of the substrate after performing the first annealing process and before performing the second annealing process.

According to some embodiments of the disclosure, the wafer includes a trap rich layer.

Based on the above, in the present disclosure, after the device structure and the interconnection structure are formed on the front side of the substrate, the first annealing process is performed in the atmosphere of pure hydrogen at a higher temperature. Thus, the performance of the device structure is improved. Also, the stresses of the interconnection structure on the front side of the substrate can be reduced, and the desired electrical characteristics of the interconnection structure can also be achieved. Then, after the interconnection structure is formed on the back side of the substrate, the second annealing process can be performed in the atmosphere of gas mixture including hydrogen at a lower temperature. Similarly, the stresses of the interconnection structure on the back side of the substrate can be reduced, and the desired electrical characteristics of the interconnection structure can also be achieved. Furthermore, if the substrate with the device structure and the interconnection structure on the front side is bonded with the trap rich layer (TRL) wafer after performing the first annealing process, only the second annealing process with a lower temperature is performed to the TRL wafer. Thereby, the performance of the second harmonic distortion is improved. As a result, the performance of the device structure and the second harmonic distortion can be improved simultaneously.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a flow chart illustrating a manufacturing method of a semiconductor device according to some embodiments of the disclosure.FIG. 2AtoFIG. 2Fare cross-sectional views illustrating a manufacturing method of a semiconductor device according to some embodiments of the disclosure. In the present embodiment, the semiconductor device may be a semiconductor device manufactured according to a radio frequency (RF) SOI technique, but the invention is not limited thereto.

Referring toFIG. 1,FIG. 2A, andFIG. 2B, a manufacturing method of a semiconductor device of the present embodiment includes the following steps. A step S10is performed, such that a substrate100having a device structure200and a first interconnection structure120on a front side is provided.

Referring toFIG. 2A, the substrate100has the front side and a back side opposite to each other. In some embodiments, the substrate100may be a semiconductor substrate, for example. The semiconductor substrate may be a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI) substrate, for example. The doped silicon substrate may be P-type doped, N-type doped, or a combination thereof. In the exemplary embodiment, the substrate100is, for example, the SOI substrate including a bulk silicon layer100a, an insulating layer100b, and a thin silicon layer100c, but the invention is not limited thereto. Specifically, the insulating layer100bis disposed between the bulk silicon layer100aand the thin silicon layer100c. The thin silicon layer100cis closer to the front side of the substrate100, and the bulk silicon layer100ais closer to the back side of the substrate100, for example. In some embodiments, a material of the insulating layer100bincludes an oxide, such as a silicon oxide layer. For instance, the insulating layer100bmay be a buried oxide (BOX) layer disposed on the bulk silicon layer100a, but the invention is not limited thereto.

In some embodiments, a plurality of isolation structures106are formed on the front side of the substrate100to define an active region102for the device structure200. In other words, the isolation structures106are formed in the thin silicon layer100cto define an active region102for the device structure200. In the exemplary embodiment, only one active region102is shown inFIG. 2A, but the invention is not limited thereto. In some embodiments, the isolation structures106may be shallow trench isolation (STI) structures, for example. A material of the isolation structure106includes an insulating material. The insulating material may be silicon oxide, silicon nitride, or a combination thereof, for example.

In the exemplary embodiment, the device structure200is a transistor, for example, but the invention is not limited thereto. Specifically, the device structure200includes a doped regions204and206, a gate structure202, and spacers208. The device structure200is disposed on the active region102. The gate structure202includes a gate dielectric layer202aand a gate202b. The gate dielectric layer202ais disposed between the gate202band the active region102, so as to electrically isolate the gate202bfrom the active region102. In some embodiments, a material of the gate dielectric layer202aincludes silicon oxide, for example. A method of forming the gate dielectric layer202aincludes thermal oxidation or chemical vapor deposition (CVD), for example. A material of the gate202bincludes polycrystalline silicon, for example. A method of forming the gate202bincludes CVD, for example. The spacers208are disposed on two sides of the gate structure202on the active region102. A method of forming the spacers208is familiar to people skilled in the art and shall not be detailed here. The doped regions204and206are respectively disposed in the active region102on two sides of the gate structure202. A method of forming the doped regions204and206includes, for example, performing ion implantation by using the gate structure202and the spacers208as a mask to implant a dopant into the active region102. In some embodiments, the doped region204may be a source, and the doped region206may be a drain. However, the invention is not limited thereto. In other embodiments, the doped region204may be a drain, and the doped region206may be a source. In some embodiments, the doped regions204and206are of the same conductivity type. For example, the doped regions204and206may be of N-type conductivity, so that the device structure200is an N-type transistor. Conversely, the doped regions204and206may be of P-type conductivity, so that the device structure200is a P-type transistor. In an alternative embodiment, the device structure200includes a radio frequency (RF) transistor, but the invention is not limited thereto.

Referring toFIG. 2B, a protective layer104is conformally formed on the substrate100. Specifically, the protective layer104conformally covers the device structure200and top surfaces of the isolation structures106. In some embodiments, a material of the protective layer104includes a nitride, such as silicon nitride, silicon oxynitride, or a combination thereof. A method of forming the protective layer104includes CVD or atomic layer deposition (ALD), for example.

After that, a plurality of contacts are formed on the protective layer104. In detail, an interlayer dielectric layer110is formed on the protective layer104first. In some embodiments, a material of the interlayer dielectric layer110includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. A method of forming the interlayer dielectric layer110includes CVD, for example. Next, a plurality of openings (not shown) are formed in the interlayer dielectric layer110and the protective layer114. In some embodiments, a method of forming the openings includes an etching process, such as a dry etching process. The dry etching process is a reactive ion etching (RIE) process, for example. Then, a conductor material (not shown) is filled in the openings and covers the interlayer dielectric layer110. Thereafter, a planarization process is performed to remove the conductor material on the interlayer dielectric layer110. In some embodiment, the planarization process is, for example, a chemical-mechanical polishing (CMP) method or an etch-back process. In some embodiment, the conductor material includes a metal material, such as tungsten (W), aluminum (Al), copper (Cu), or a combination thereof. Thus, the contacts112,114,116, and118are formed. Specifically, the contacts112and116are electrically connected to the doped regions206and204respectively. The contact114is electrically connected to the gate structure202. The contact118is disposed in the interlayer dielectric layer110, the protective layer104, the isolation structure106, and the insulating layer100bbeside the device structure200. However, the invention is not limited thereto.

Then, the first interconnection structure120is formed on the interlayer dielectric layer110. Specifically, the first interconnection structure120includes a plurality of dielectric layers126and a plurality of circuit structures124. The circuit structures124are disposed in the dielectric layer126to be electrically connected to the contacts112,114,116, and118respectively. Furthermore, a plurality of vias122are formed to provide interconnection between the circuit structures124in different metal layers. In the exemplary embodiment, two metal layers are shown inFIG. 2B. In detail, four circuit structures124are depicted in a first metal layer, and two circuit structures124are depicted in a second metal layer, but the invention is not limited thereto. In addition, although only two metal layers are depicted herein, this is merely illustrative and it should be understood that the number of the metal layers may be less or more according to the demands. In some embodiments, a material of the dielectric layer126includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The dielectric layer126may be one layer or more, for example. In some embodiments, a material of the circuit structure124and the via122includes a metal material, such as Al, Al alloy, Cu, Cu alloy, or a combination thereof. A method of forming the circuit structure124and the via122includes damascene, or dual damascene, for example.

Referring toFIG. 1andFIG. 2C, a step S12is performed, such that a first annealing process A1is performed in an atmosphere of pure hydrogen at a first temperature. In some embodiments, the first temperature is between 350° C. and 450° C. In other embodiments, the first temperature is between 380° C. and 420° C. In some embodiments, the first annealing process A1is performed between 30 minutes and 2 hours. However, the invention is not limited thereto.

It should be noted that, the dangling bonds existing in the device structure200are neutralized by attaching hydrogen atoms at this step. Therefore, the performance of the device structure200is improved. In addition, since the first annealing process A1is performed in the atmosphere of pure hydrogen at a high temperature, the dangling bonds in the device structure200are efficiently reduced. Furthermore, since the performance of the device structure is improved at this step, a second annealing process A2(described in detail later) can be performed at a lower temperature. On the other hand, after performing the first annealing process Al, internal and/or external stresses of the metallization structure (e.g., the first interconnection structure120) can be reduced, and the desired electrical characteristics, such as electromigration, can also be achieved.

Referring toFIG. 2D, the substrate100having the device structure200and the first interconnection structure120on the front side is bonded with a wafer130via the front side of the substrate100. In the exemplary embodiment, the wafer130may be a trap rich layer (TRL) wafer. In other words, the wafer130includes a TRL, for example, and the TRL may be a bonding interface between the first interconnection structure120and the wafer130. Specifically, the bonding interface is an amorphous layer requiring more dangling bonds to trap RF signal noise. However, the invention is not limited thereto.

In some embodiments, before the substrate100having the device structure200and the first interconnection structure120on the front side is bonded with the wafer130, a bonding layer128is formed on the first interconnection structure120. The bonding layer128may be a combination of one or more insulating layers and passivation layers to isolate and protect the first interconnection structure120and the device structure200. In addition, the bonding layer128is used to bond the first interconnection structure120and the wafer130. In some embodiments, a method of forming the bonding layer128includes CVD or thermal oxidation, for example. However, the invention is not limited thereto.

Referring toFIG. 1andFIG. 2E, a step S14is performed, such that a second interconnection structure140is formed on the back side of the substrate100. In detail, after the substrate100having the device structure200and the first interconnection structure120on the front side is bonded with the wafer130, the wafer130is attached to a carrier (not shown), and the structure ofFIG. 2Dis turned upside down. Then, a wet etching process is performed to thin or remove the substrate100. In the exemplary embodiment, the substrate100is partially removed. Specifically, the bulk silicon layer100ais removed as shown inFIG. 2E, but the invention is not limited thereto. Thereafter, the second interconnection structure140is formed on the insulating layer100b. Specifically, the second interconnection structure140includes a plurality of dielectric layers146and a plurality of circuit structures144. In the exemplary embodiment, the circuit structures144are disposed in the dielectric layer146. As shown inFIG. 2E, the circuit structures144may be electrically connected to the first interconnection structure120via the contacts118, and the circuit structures144may be electrically connected to the device structure200, but the invention is not limited thereto. Furthermore, a plurality of vias142are formed to provide interconnection between the circuit structures144in different metal layers. In the exemplary embodiment, two metal layers are shown inFIG. 2E. In detail, two circuit structures144are depicted in a first metal layer, and one circuit structure144is depicted in a second metal layer, but the invention is not limited thereto. In addition, although only two metal layers are depicted herein, this is merely illustrative and it should be understood that the number of the metal layers may be less or more according to the demands. In some embodiments, a material of the dielectric layer146includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The dielectric layer146may be one layer or more, for example. In some embodiments, a material of the circuit structure144and the via142includes a metal material, such as Al, Al alloy, Cu, Cu alloy, or a combination thereof. A method of forming the circuit structure144and the via142includes damascene, or dual damascene, for example.

In other embodiments, an inductor structure (not shown) may be formed on the back side of the substrate100according to the demands. For instance, the inductor structure may be electrically connected to integrated circuits on the front side of the substrate100through the substrate100. In some embodiments, a passivation layer (not shown) may be formed on the second interconnection structure140. However, the invention is not limited thereto.

Referring toFIG. 1andFIG. 2F, a step S16is performed, such that a second annealing process A2is performed in an atmosphere of gas mixture including hydrogen at a second temperature. In some embodiments, the second temperature is between 150° C. and 250° C. In other embodiments, the second temperature is between 180° C. and 220° C. Specifically, the first temperature is higher than the second temperature. In some embodiments, the gas mixture includes 10% to 20% of hydrogen, for example. In some embodiments, the gas mixture further includes nitrogen, helium, neon, argon, or a combination thereof, for example. In the exemplary embodiment, the gas mixture includes hydrogen and nitrogen, but the invention is not limited thereto. In some embodiments, the second annealing process A2is performed between 30 minutes and 2 hours. In other embodiments, the second annealing process A2is performed for approximately 30 minutes, for example. However, the invention is not limited thereto.

It should be noted that, in the traditional annealing process, the wafer is annealed at a temperature of about 400° C. in the atmosphere of gas containing hydrogen to repair the damage caused by various process steps, such as a plasma etching process or ion implantation. Since hydrogen gas molecules are able to diffuse throughout the circuit structures of the semiconductor device to react with the dangling bonds due to their small size, the dangling bonds existing in the device structure are reduced. Thus, the performance of the device structure is improved. However, the performance of second harmonic distortion is degraded in a such high temperature condition. Accordingly, in the embodiment of the disclosure, after the device structure is formed on the front side of the substrate, the first annealing process is performed in the atmosphere of pure hydrogen at a high temperature. The performance of the device structure is improved at this step. Then, the substrate with the device structure and the interconnection structure is bonded with another wafer, such as a TRL wafer. Thereafter, another interconnection structure is formed on the back side of the substrate. Subsequently, the second annealing process can be performed in the atmosphere of gas mixture including hydrogen at a lower temperature, instead of original high temperature. Therefore, the dangling bonds can be kept in this lower temperature condition, thereby improving the performance of the second harmonic distortion. On the other hand, after the second annealing process A2, internal and/or external stresses of the metallization structure (e.g., the second interconnection structure140) can be reduced, and the desired electrical characteristics can also be achieved.

FIG. 3is a graph illustrating normalized intermodulation distortion (IMD) power when the second annealing process is performed at different temperatures.

Referring toFIG. 3, when the second annealing process A2is performed below 250° C., the normalized intermodulation distortion (IMD) power of the second harmonic distortion is lower than approximately −85 dBm. Particularly, when the second annealing process A2is performed at 200° C., the IMD power of the second harmonic distortion is approximately −87 dBm which meets a spec requirement. In other words, the second annealing process A2is performed at a lower temperature, so that the number of the traps is not decreased. Thus, the performance of the second harmonic distortion is improved. Moreover, since the first annealing process A1is performed in an atmosphere of pure hydrogen at a higher temperature, the device performance is also improved.

In view of above, in the present disclosure, after the device structure and the interconnection structure are formed on the front side of the substrate, the first annealing process is performed in the atmosphere of pure hydrogen at a higher temperature. Thus, the performance of the device structure is improved. Also, the stresses of the interconnection structure on the front side of the substrate can be reduced, and the desired electrical characteristics of the interconnection structure can also be achieved. Then, after the interconnection structure is formed on the back side of the substrate, the second annealing process can be performed in the atmosphere of gas mixture including hydrogen at a lower temperature. Similarly, the stresses of the interconnection structure on the back side of the substrate can be reduced, and the desired electrical characteristics of the interconnection structure can also be achieved. Furthermore, if the substrate with the device structure and the interconnection structure on the front side is bonded with the TRL wafer after performing the first annealing process, only the second annealing process with a lower temperature is performed to the TRL wafer. Thereby, the performance of the second harmonic distortion is improved. As a result, the performance of the device structure and the second harmonic distortion can be improved simultaneously.