Image sensor

An image sensor includes different first and second focus pixels in a substrate; a first adjacent pixel in the substrate and adjacent to the first focus pixel in a positive first direction, a pixel being absent between the first focus pixel and the first adjacent pixel; a first micro-lens covering the first adjacent pixel; a second adjacent pixel in the substrate and adjacent to the second focus pixel in a positive first direction, a pixel being absent between the second focus pixel and the second adjacent pixel; and a second micro-lens covering the second adjacent pixel, and an area of the first micro-lens being different from an area of the second micro-lens.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No. 10-2021-0051004 filed on Apr. 20, 2021 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. § 119, the contents of which in its entirety are herein incorporated by reference.

BACKGROUND

Some example embodiments relate to image sensors.

Image sensors refer to a device that captures a two-dimensional or three-dimensional image of an object. The image sensor generates an image of the object using a photoelectric conversion element that responds to an intensity of light reflected from the object. With recent development of CMOS (complementary metal-oxide semiconductor) technology, a CMOS based image sensor using the CMOS has been widely used.

SUMMARY

Some example embodiments provide image sensors in which sizes and/or areas of micro-lenses respectively covering adjacent pixels respectively adjacent to focus pixels may be different from each other, thereby compensating for a difference between an intensity of a pixel signal output from the adjacent pixel and an intensity of a pixel signal output from a normal pixel.

According to some example embodiments of inventive concepts, an image sensor includes different first and second focus pixels in a substrate; a first adjacent pixel in the substrate and adjacent to the first focus pixel in a positive first direction, a pixel being absent between the first focus pixel and the first adjacent pixel; a first micro-lens covering the first adjacent pixel; a second adjacent pixel in the substrate and adjacent to the second focus pixel in a positive first direction, a pixel being absent between the second focus pixel and the second adjacent pixel; and a second micro-lens covering the second adjacent pixel, and an area of the first micro-lens is different from an area of the second micro-lens.

According to some example embodiments of inventive concepts, an image sensor includes a substrate including a first surface on which light is incident, and a second surface opposite the first surface; a first focus pixel and a first adjacent pixel in the substrate, wherein the first focus pixel and the first adjacent pixel are separated from each other via a pixel separation pattern, and are sequentially arranged in a positive first direction and are adjacent to each other, a pixel being absent between the first focus pixel and the first adjacent pixel; a second focus pixel and a second adjacent pixel in the substrate, wherein the second focus pixel and the second adjacent pixel are separated from each other via the pixel separation pattern, and are sequentially arranged in the positive first direction and are adjacent to each other, a pixel being absent between the second focus pixel and the second adjacent pixel; a first micro-lens on the first surface of the substrate, and covering the first adjacent pixel; a second micro-lens on the first surface of the substrate, and covering the second adjacent pixel; a third micro-lens on the first surface of the substrate, and covering the first focus pixel; and a fourth micro-lens on the first surface of the substrate, and covering the second focus pixel, a minimum spacing between the first micro-lens and the third micro-lens in the first direction is different from a minimum spacing between the second micro-lens and the fourth micro-lens in the first direction.

According to some example embodiments of inventive concepts, an image sensor includes different first to third focus pixels in a substrate; a first adjacent pixel in the substrate and adjacent to the first focus pixel in a positive first direction, a pixel being absent between the first focus pixel and the first adjacent pixel; a second adjacent pixel in the substrate and adjacent to the second focus pixel in the positive first direction, a pixel being absent between the second focus pixel and the second adjacent pixel; a third adjacent pixel in the substrate and adjacent to the third focus pixel in the positive first direction, a pixel being absent between the third focus pixel and the third adjacent pixel; a normal pixel in the substrate and not adjacent to the first focus pixel, the second focus pixel, and the third focus pixel; a first micro-lens covering the first adjacent pixel; a second micro-lens covering the second adjacent pixel; a third micro-lens covering the third adjacent pixel; and a fourth micro-lens covering the normal pixel, an area of the first micro-lens being different from each of an area of the second micro-lens, an area of the third micro-lens, and an area of the fourth micro-lens.

DETAILED DESCRIPTIONS

FIG.1is a block diagram for illustration of an image sensing device according to some example embodiments.

Referring toFIG.1, an image sensing device1according to some example embodiments may include an image sensor10and an image signal processor20.

The image sensor10may sense an image of a sensing target using light to generate an image signal IS. In some example embodiments, the generated image signal IS may be, for example, a digital signal. However, some example embodiments according to the technical idea of the present disclosure is not limited thereto.

The image signal IS may be provided to the image signal processor20in which the signal may be processed. The image signal processor20may receive the image signal IS output from the buffer17of the image sensor10and process the received image signal IS so as to be easily displayed on a display.

In some example embodiments, the image signal processor20may perform digital binning on the image signal IS output from the image sensor10. In this connection, the image signal IS output from the image sensor10may be a raw image signal from an active pixel sensor array (APS)15which may not be subjected to analog binning or may be an image signal on which the analog binning has already been performed.

In some example embodiments, the image sensor10and the image signal processor20may be separated from each other as shown. For example, the image sensor10may be mounted on a first chip, and the image signal processor20may be mounted on a second chip while the image sensor10and the image signal processor20may communicate with each other over a predefined (e.g., desired or selected) interface. However, example embodiments are not limited thereto. The image sensor10and the image signal processor20may be embodied as one package, for example, an MCP (multi-chip package).

The image sensor10may include the active pixel sensor array15, a control register block11, a timing generator12, a row driver14, a readout circuit16, a ramp signal generator13, and a buffer17.

The control register block11may control all of operations of the image sensor10. In particular, the control register block11may transmit an operation signal directly to the timing generator12, the ramp signal generator13, and the buffer17.

The timing generator12may generate a signal acting as a reference for an operation timing of each of various components of the image sensor10. The operation timing reference signal generated by the timing generator12may be transmitted to the ramp signal generator13, the row driver14, the readout circuit16, and the like.

The ramp signal generator13may generate and transmit a ramp signal used in the readout circuit16. For example, the readout circuit16may include a correlated double sampler (CDS), a comparator, etc. The ramp signal generator13may generate and transmit the ramp signal used in the correlated double sampler, the comparator, and the like.

The row driver14may selectively activate a row of the active pixel sensor array15.

The active pixel sensor array15may sense an external image. The active pixel sensor array15may include a plurality of pixels.

The readout circuit16may sample a pixel signal provided from the active pixel sensor array15, and compare the sampled pixel signal with the ramp signal, and then convert an analog image signal (data) into a digital image signal (data) based on the comparison result.

The buffer17may include, for example, a latch. The buffer17may temporarily store therein the image signal IS to be provided to an external component, and may transmit the image signal IS to an external memory or an external device.

FIG.2is a block diagram to illustrate an image sensor according to some example embodiments.

Referring toFIG.2, the image sensor10of the present implementation may include a stack of a first chip30and a second chip40. The second chip40may be stacked, for example, on the first chip30in a third direction DR3.

The first chip30may include a sensor array area SAR, a connection area CR, and a pad area PR.

The sensor array area SAR may include an area corresponding to the active pixel sensor array15ofFIG.1. For example, a plurality of pixels arranged two-dimensionally (e.g., in a matrix form) may be disposed in the sensor array area SAR. The sensor array area SAR may include a light-receiving area APS and a light-blocking area OB. Active pixels that receive light and generate an active signal may be arranged in the light-receiving area APS. In the light-blocking area OB, optical black pixels that block light and generate an optical black signal may be arranged. The light-blocking area OB may be formed, for example, along a periphery of the light-receiving area APS. However, this is only exemplary.

In some example embodiments, a photoelectric conversion layer may not be formed in a portion of the light-blocking area OB. Further, in some example embodiments, dummy pixels may be formed in a portion of the light-receiving area APS adjacent to the light-blocking area OB.

The connection area CR may be formed around the sensor array area SAR. The connection area CR may be formed on one side of the sensor array area SAR. However, this is only exemplary. Lines may be formed in the connection area CR, and may be configured to transmit and receive an electrical signal of the sensor array area SAR.

The pad area PR may be formed around the sensor array area SAR. The pad area PR may be formed adjacent to an edge of the image sensor according to some example embodiments. However, this is only exemplary. The pad area PR may be connected to an external device and the like, and may be configured to transmit/receive an electrical signal between the image sensor according to some example embodiments and the external device.

Although the connection area CR is shown to be interposed between the sensor array area SAR and the pad area PR, this is only exemplary. In some example embodiments, the arrangement of the sensor array area SAR, the connection area CR, and the pad area PR may vary according to need or desire.

The second chip40may be disposed below the first chip30, and may include a logic circuit area LC. The second chip40may be electrically connected to the first chip30. The logic circuit area LC of the second chip18may be electrically connected to the sensor array area SAR via, for example, the pad area CR of the first chip30.

The logic circuit area LC may include a plurality of elements for driving the sensor array area SAR. The logic circuit area LC may include, for example, the control register block11, the timing generator12, the ramp signal generator13, the row driver14, and the readout circuit16ofFIG.1.

FIG.3is a schematic layout diagram to illustrate a light-receiving area of an image sensor according to some example embodiments.

Referring toFIG.3, a plurality of focus pixels FP1and FP2, a plurality of adjacent pixels AP1to AP10, and a plurality of normal pixels NP may be disposed in the light-receiving area APS of the image sensor according to some example embodiments. The plurality of focus pixels FP1and FP2, the plurality of adjacent pixels AP1to AP10, and the plurality of normal pixels NP may be arranged in a two-dimensional manner, for example, in a matrix form, and in a plane including a first direction DR1and a second direction DR2. The active pixel sensor array15inFIG.1may include an area corresponding to the light-receiving area APS.

The focus pixels FP1and FP2may be arranged in the first direction DR1and/or the second direction DR2and in the light-receiving area APS. The second direction DR2may intersect the first direction DR1.

In the image sensor according to some example embodiments, the focus pixels FP1and FP2may include, for example, a first focus pixel FP1and a second focus pixel FP2adjacent to each other. That is, the focus pixels FP1and FP2may occupy an area corresponding to twice of an area of one normal pixel and/or one adjacent pixel. However, the present disclosure is not limited thereto. The focus pixel may include at least two focus pixels.

No pixel may be disposed between the first focus pixel FP1and the second focus pixel FP2. For example, the first focus pixel FP1and the second focus pixel FP2may be adjacent to each other in the first direction DR1, while no pixel may be disposed between the first focus pixel FP1and the second focus pixel FP2. In a following description, when two components are “adjacent” to each other, this may mean that no component is disposed between the two components. In still another example, unlike shown in the figure, the first focus pixel FP1and the second focus pixel FP2may be adjacent to each other in the second direction DR2, while no pixel may be disposed between the first focus pixel FP1and the second focus pixel FP2. As such, it will be understood that orientations may change while retaining the spatial relationship between pixels, for example, the first focus pixel FP1and the second focus pixel FP2.

Each of the focus pixels FP1and FP2may perform an auto focus function (AF). Each of the focus pixels FP1and FP2may perform the auto focus function using phase detection AF (PDAF).

The adjacent pixels AP1to AP10may be arranged around the focus pixels FP1and FP2. The adjacent pixels AP1to AP10may be disposed adjacent to the focus pixels FP1and FP2, such that no pixel may be disposed between the adjacent pixels AP1to AP10and the focus pixels FP1and FP2. For example, a first adjacent pixel AP1, the first focus pixel FP1, the second focus pixel FP2, and a second adjacent pixel AP2may be sequentially arranged in the first direction DR1, while no pixel may be disposed therebetween. That is, the first adjacent pixel AP1may be adjacent to the first focus pixel FP1in a negative first direction DR1, while the second adjacent pixel AP2may be adjacent to the second focus pixel FP2in a positive first direction DR1. A third adjacent pixel AP3, the first focus pixel FP1and a fourth adjacent pixel AP4may be arranged sequentially in the second direction DR2such that no pixel may be disposed therebetween. A fifth adjacent pixel APS, the second focus pixel FP2, and a sixth adjacent pixel AP6may be arranged sequentially in the second direction DR2such that no pixel may be disposed therebetween. That is, the third adjacent pixel AP3and the first focus pixel FP1and may be arranged in a positive second direction DR2. The fifth adjacent pixel AP5and the second focus pixel FP2may be arranged in a positive second direction DR2. The fourth adjacent pixel AP4and the first focus pixel FP1may be arranged in a negative second direction DR2. The sixth adjacent pixel AP6and the second focus pixel FP2may be arranged in a negative second direction DR2. In this connection, a positive direction means a direction according to an arrow shown in the drawing, while a negative direction means an opposite direction to the positive direction. A seventh adjacent pixel AP7may be adjacent to the first focus pixel FP1in a negative fifth fourth direction DR4. An eighth adjacent pixel AP8may be adjacent to the first focus pixel FP1in a positive fifth direction DR5. A ninth adjacent pixel AP9may be adjacent to the second focus pixel FP2in a negative fifth direction DR5. A tenth adjacent pixel AP10may be adjacent to the second focus pixel FP2in a positive fourth direction DR4. No pixel may not be disposed between the seventh adjacent pixel AP7and the first focus pixel FP1, between the eighth adjacent pixel AP8and the first focus pixel FP1, between the ninth adjacent pixel AP9and the second focus pixel FP2, and between the tenth adjacent pixel AP10and the second focus pixel FP2. The positive fourth direction DR4may be a diagonal direction between the positive first direction DR1and the positive second direction DR2. The positive fifth direction DR5may be a diagonal direction between the negative first direction DR1and the positive second direction DR2.

The normal pixel NP may be disposed adjacent to the adjacent pixels AP1to AP10. The normal pixel NP may mean pixels other than the adjacent pixels AP1to AP10and the focus pixels FP1and FP2.

FIG.4is a diagram to illustrate a pixel signal of the light-receiving area ofFIG.3.

Referring toFIG.3andFIG.4, each of first to tenth contours C1to C10represents an intensity of a pixel signal output from each of the first to tenth adjacent pixels AP1to AP10based on a position of each of the first to tenth adjacent pixels AP1to AP10in the light-receiving area APS, relative to an intensity of a pixel signal output from the normal pixel NP. As the contour becomes a darker gray color, (e.g., closer to black) this indicates that the intensity of the pixel signal is greater than the intensity of the pixel signal output from the normal pixel NP (e.g., in adjacent pixels AP1, AP2, and AP5). As the contour becomes a lighter gray color (e.g., closer to white), this indicates that the intensity of the pixel signal is the same as the intensity of the pixel signal output from the normal pixel NP. As the contour becomes a gray color, this indicates that the intensity of the pixel signal is lower than the intensity of the pixel signal output from the normal pixel NP (e.g., in adjacent pixels AP3, AP4, AP6, and AP10compared to the darker gray).

Each of the plurality of focus pixels FP1and FP2, the plurality of adjacent pixels AP1to AP10, and the plurality of normal pixels NP may detect light incident from an outside using a photoelectric conversion layer112to be described later to generate photo-charges, and may convert the photo-charges into a voltage or current signal and output the voltage or current signal as the pixel signal.

One micro-lens may be disposed on the focus pixels FP1and FP2to simultaneously cover the focus pixels FP1and FP2. Each micro-lens covering each of the adjacent pixels AP1to AP10and the normal pixel NP may be disposed on each of the adjacent pixels AP1to AP10and the normal pixel NP. A shape and/or a size of the micro-lens covering the focus pixels FP1and FP2may be different from a shape and/or a size of each micro-lens covering each of the adjacent pixels AP1to AP10and/or the normal pixel NP. Accordingly, the pixel signal output from each of the adjacent pixels AP1to AP10adjacent to the focus pixels FP1and FP2may be different from the pixel signal output from the normal pixel NP as each of the first to tenth contour C1to C10may be so. Thus, an image may be deteriorated due to a difference between the intensity of the pixel signal output from each of the adjacent pixels AP1to AP10adjacent to the focus pixels FP1and FP2and the intensity of the pixel signal output from the normal pixel NP.

For example, a first contour C1represents the intensity of the pixel signal of the first adjacent pixel AP1adjacent to the first focus pixel FP1in the negative first direction DR1, based on a position in the light-receiving area APS. Referring to the first contour C1, as a position is farther away from a center of the light-receiving area APS in the negative first direction DR1, the intensity of the pixel signal output from the first adjacent pixel AP1is greater than the intensity of the pixel signal output from the normal pixel NP. As a position is farther away from the center of the light-receiving area APS in the positive first direction DR1, the intensity of the pixel signal output from the first adjacent pixel AP1is lower than the intensity of the pixel signal output from the normal pixel NP. In some example embodiments, a sixth contour C6represents the intensity of the pixel signal of the sixth adjacent pixel AP6adjacent to the second focus pixel FP2in the positive second direction DR2, based on a position in the light-receiving area APS. Referring to the sixth contour C6, the intensity of the pixel signal output from the sixth adjacent pixel AP6is lower than the intensity of the pixel signal output from the normal pixel NP as the position is farther away from the center of the light-receiving area APS in the positive first direction DR1. The intensity of the pixel signal output from the sixth adjacent pixel AP6is lower than the intensity of the pixel signal output from the normal pixel NP as the position is farther away from the center of the light-receiving area APS in the positive second direction DR2.

Therefore, in the image sensor according to some example embodiments, the size and/or area of the micro-lens covering each of the adjacent pixels AP1to AP10may be adjusted to compensate for the difference between the intensity of the pixel signal output from each of the adjacent pixel AP1to AP10and an intensity of the pixel signal output from the normal pixel NP. Hereinafter, this will be described in detail with reference toFIG.5,FIG.6,FIG.7AtoFIG.7eandFIG.8AtoFIG.8D.

FIG.5is an enlarged view of the first contour C1ofFIG.4, andFIG.6is an enlarged view of the second contour C2ofFIG.4.FIG.7AtoFIG.7Dare schematic layout diagrams to illustrate a R1 area to a R4 area ofFIG.5andFIG.6, respectively.FIG.7Eis a schematic layout diagram to illustrate a R5 area ofFIG.3.FIG.8Ais a cross-sectional view taken along a line A-A′ of the R1 area.FIG.8Bis a cross-sectional view taken along a line B-B′ of the R2 area.FIG.8Cis a cross-sectional view taken along a line C-C′ of the R3 area.FIG.8Dis a cross-sectional view taken along a line D-D′ of the R3 area.FIG.8Eis a cross-sectional view taken along a line E-E′ of the R4 area.

Referring toFIG.5,FIG.6,FIG.7AtoFIG.7DandFIG.8AtoFIG.8E, the R1 area may include a first-first focus pixel FP11, a first-second focus pixel FP12, first-first to first-tenth adjacent pixels AP11to AP110(as in AP11, AP12, AP13, AP14, AP15, AP16, AP17, AP18, AP19, and AP110) adjacent to the first-first focus pixel FP11and the first-second focus pixel FP12, and the normal pixel NP. No pixel may be disposed between the first-first focus pixel FP11and the first-second focus pixel FP12and the first-first to first-tenth adjacent pixels AP11to AP110. The R2 area may include a second-first focus pixel FP21, a second-second focus pixel FP22, second-first to second-tenth adjacent pixels AP21to AP210(as in AP21, AP22, AP23, AP24, AP25, AP26, AP27, AP28, AP29, and AP210) adjacent to the second-first focus pixel FP21and the second-second focus pixel FP22, and the normal pixel NP. No pixel may be disposed between the second-first focus pixel FP21and the second-second focus pixel FP22and the second-first to second-tenth adjacent pixels AP21to AP210. The R3 area may include a third-first focus pixel FP31, a third-second focus pixel FP32, third-first to third-tenth adjacent pixels AP31to AP310(as in AP31, AP32, AP33, AP34, AP35, AP36, AP37, AP38, AP39, and AP310) adjacent to the third-first focus pixel FP31and the third-second focus pixel FP32, and the normal pixel NP. No pixel may be disposed between the third-first focus pixel FP31, and the third-second focus pixel FP32and the third-first to third-tenth adjacent pixels AP31to AP310. The R4 area may include a fourth-first focus pixel FP41, a fourth-second focus pixel FP42, fourth-first to fourth-tenth adjacent pixels AP41to AP410(as in AP41, AP42, AP43, AP44, AP45, AP46, AP47, AP48, AP49, and AP410) adjacent to the fourth-first focus pixel FP41and the fourth-second focus pixel FP42, and the normal pixel NP. No pixel may be disposed between the fourth-first focus pixel FP41and the fourth-second focus pixel FP42and the fourth-first to fourth-tenth adjacent pixels AP41to AP410.

The image sensor according to some example embodiments includes a first substrate110, the photoelectric conversion layer112, a pixel separation pattern120, a first electronic element TR1, a first line structure IS1, a surface insulating film140, a color filter layer170, a grid pattern150, a planarization film180, and an micro-lens array ML11to ML110, ML21to ML210, ML31to ML310, ML41to ML410, M7, and M8.

The first substrate110may be a semiconductor substrate. For example, the first substrate110may be made of bulk silicon or (SOI) silicon-on-insulator. The first substrate110may be a silicon substrate. Alternatively, the first substrate110may be made of a material such as silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide and/or gallium antimonide. Alternatively, the first substrate110may include a base substrate and an epitaxial layer formed on the base substrate.

The first substrate110may include a first surface110aand a second surface110bopposite to each other. In example embodiments as described below, the first surface110amay be referred to as a back side of the first substrate110, while the second surface110bmay be referred to as a front side of the first substrate110. In some example embodiments, the first surface110aof the first substrate110may act as a light-receiving surface on which the light is incident. That is, the image sensor according to some example embodiments may be embodied as a back side irradiated (BSI) image sensor.

The photoelectric conversion layer112may be formed in the first substrate110. A plurality of photoelectric conversion layers112may be arranged to respectively correspond to the plurality of focus pixels FP1and FP2, the plurality of adjacent pixels AP1to AP10, and the plurality of normal pixels NP. For example, the photoelectric conversion layers112may be arranged two-dimensionally, for example, in matrix form, and in a plane including the first direction DR1and the second direction DR2and may be respectively disposed in the plurality of focus pixels FP1and FP2, the plurality of adjacent pixels AP1to AP10, and the plurality of normal pixels NP. The photoelectric conversion layer112may generate charges in proportion to an amount of light incident from the outside.

The photoelectric conversion layer112may be formed by doping impurities into the first substrate110. For example, the photoelectric conversion layer112may be formed via ion implantation of n-type impurities into a p-type first substrate110. In some example embodiments, the photoelectric conversion layer112may have a potential slope in a vertical direction (DR3) normal to a surface of the first substrate110, for example, the first surface110aor the second surface110b. For example, a concentration of the impurities in the photoelectric conversion layer112may decrease as the layer extends from the second surface110btoward the first surface110a.

The photoelectric conversion layer112may include at least one of, for example, a photo diode, a photo transistor, a photo gate, a pinned photo diode, an organic photo diode, a quantum dot, and combinations thereof. However, the present disclosure is not limited thereto.

The pixel separation pattern120may be formed in the first substrate110. The pixel separation pattern120may define the plurality of focus pixels FP11, FP12, FP21, FP22, FP31, FP32, FP41, and FP42, the plurality of adjacent pixels AP11to AP110, AP21to AP210, AP31to AP310, and AP41to AP410, and the plurality of normal pixels NP in the first substrate110. For example, the pixel separation pattern120may be formed in a grid form in a plan view and may surround each of the focus pixels FP11, FP12, FP21, FP22, FP31, FP32, FP41, and FP42, the adjacent pixels AP11to AP110, AP21to AP210, AP31to AP310, and AP41to AP410, and the normal pixels NP which may be arranged in a matrix form.

In some example embodiments, the pixel separation pattern120may extend through the first substrate110. For example, the pixel separation pattern120may extend continuously from the second surface110bof the first substrate110to the first surface110aof the first substrate110.

In some example embodiments, a width of the pixel separation pattern120may decrease as the pattern extends away from the second surface110bof the first substrate110. In this connection, the width means a width in a direction parallel to the surface of the first substrate110, for example, the first surface110aor the second surface110b. This may be due to characteristics of an etching process for forming the pixel separation pattern120. For example, a process of etching the first substrate110to form the pixel separation pattern120may be performed on the second surface110bof the first substrate110.

In some example embodiments, the pixel separation pattern120may include a conductive filling pattern122and an insulating spacer film124. For example, in the first substrate110, a separation trench defining the plurality of focus pixels FP1and FP2, the plurality of adjacent pixels AP1to AP10, and the plurality of normal pixels NP may be formed. The insulating spacer film124may extend along a side surface of the separation trench. The conductive filling pattern122may be formed on the insulating spacer film124to fill a remaining area of the separation trench. The insulating spacer film124may electrically insulate the conductive filling pattern122from the first substrate110.

The conductive filling pattern122may include, for example, polysilicon (poly Si). However, the present disclosure is not limited thereto. In some example embodiments, a ground voltage or a negative voltage may be applied to the conductive filling pattern122. In this case, ESD (electrostatic discharge) bruise defect of the image sensor may be effectively prevented, or the occurrence of may be reduced. In this connection, the ESD bruise defect refers to a phenomenon in which charges resulting from ESD are accumulated on the first substrate110, thereby generating stains such as bruises on a resulting image.

The insulating spacer film124may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. However, the present disclosure is not limited thereto. In some example embodiments, the insulating spacer film124may include a low refractive index material having a lower refractive index than that of the first substrate110. In this case, the insulating spacer film124may improve light condensing efficiency by refracting or reflecting the light incident obliquely to the photoelectric conversion layer112, thereby improving the quality of the image sensor. Further, the insulating spacer film124may prevent or reduce photo-charges generated in a specific pixel due to the incident light from moving to an adjacent pixel via random drift.

The first electronic element TR1may be formed on the second surface110bof the first substrate110. The first electronic element TR1may include various transistors for processing an electrical signal generated from the pixels. For example, the first electronic element TR1may include transistors such as a transmission transistor, a reset transistor, a source follower transistor, or a selection transistor.

In some example embodiments, the first electronic element TR1may include a vertical transmission transistor (TG). For example, a portion of the first electronic element TR1including the aforementioned vertical transmission transistor (TG) may extend into the first substrate110. The vertical transmission transistor TG may reduce an area of a pixel, thereby enabling high integration of the image sensor.

The first line structure IS1may be formed on the second surface110bof the first substrate110. The first line structure IS1may include one or a plurality of lines. For example, the first line structure IS1may include a first inter-line insulating film130, and a plurality of first lines132in the first inter-line insulating film130. The number of layers of lines constituting the first line structure IS1shown in the drawings and the arrangement thereof are only exemplary. The technical spirit of the present disclosure is not limited thereto.

In some example embodiments, the first line132may be electrically connected to the pixels. For example, the first line132may be connected to the first electronic element TR1.

The surface insulating film140may be formed on the first surface110aof the first substrate110. The surface insulating film140may extend along the first surface110aof the first substrate110. The surface insulating film140may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, and combinations thereof. However, the present disclosure is not limited thereto.

In some example embodiments, the surface insulating film140may be composed of a multi-film. For example, the surface insulating film140may include an aluminum oxide film, a hafnium oxide film, a silicon oxide film, a silicon nitride film, and a hafnium oxide film that are sequentially stacked on the first surface110aof the first substrate110.

In some example embodiments, the surface insulating film140may function as a reflective anti-reflective film to prevent or reduce reflection of light incident on the first substrate110. Accordingly, a light reception ability of the photoelectric conversion layer112may be improved. Further, the surface insulating film140may function as a planarization film, such that the color filter layer170and the micro-lens array ML11to ML110, ML21to ML210, ML31to ML310, ML41to ML410, M7, and M8which will be described later may be formed to have a uniform vertical dimension.

The color filter layer170may be formed on the first surface110aof the first substrate110. For example, the color filter layer170may be formed on the surface insulating film140. A plurality of color filter layers170may be arranged in a respectively corresponding manner to the focus pixels FP11, FP12, FP21, FP22, FP31, FP32, FP41, and FP42, the adjacent pixels AP11to AP110, AP21to AP210, AP31to AP310, and AP41to AP410, and the normal pixels NP. For example, the color filter layers170may be arranged in a plane including the first direction DR1and the second direction DR2and may be arranged two-dimensionally, for example, in a matrix form. Each of the color filter layers170may be disposed in each of the focus pixels FP11, FP12, FP21, FP22, FP31, FP32, FP41and FP42, the adjacent pixels AP11to AP110, AP21to AP210, AP31to AP310, and AP41to AP410, and the normal pixels NP.

The color filter layer170may have various colors. For example, the color filter layer170may include a red color filter, a green color filter, and/or a blue color filter. However, this is only exemplary. The color filter layer170may include a yellow filter, a magenta filter, and/or a cyan filter. The color filter layer170may further include a white filter.

The grid pattern150may be formed on the second surface110bof the first substrate110. For example, the grid pattern150may be formed on the surface insulating film140. The grid pattern150may be interposed between the color filter layers170. For example, the grid pattern150may be formed in a grid form in a plan view to surround each of the color filter layers170arranged in a matrix form. In some example embodiments, the grid pattern150may be disposed to overlap the pixel separation pattern120in the third direction DR3. However, the grid pattern150may not be disposed between the first-first focus pixel FP11and the first-second focus pixel FP12, between the second-first focus pixel FP21and the second-second focus pixel FP22, between the third-first focus pixel FP31and the third-second focus pixel FP32, and between the fourth-first focus pixel FP41and the fourth-second focus pixel FP42.

In some example embodiments, the grid pattern150may include a first material pattern152and a second material pattern154. The first material pattern152and the second material pattern154may be sequentially stacked on the surface insulating film140. The first material pattern152and the second material pattern154may include different materials. In some example embodiments, the first material pattern152may be a metal pattern, while the second material pattern154may be an oxide pattern. In some example embodiments, the first material pattern152may be a first metal pattern while the second material pattern154may be a second metal pattern different from the first metal pattern.

The metal pattern may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof. However, the present disclosure is not limited thereto. In some example embodiments, the first material pattern152including the metal pattern prevents or reduces charges generated from the ESD from accumulating on the surface of the first substrate110, for example, the first surface110a, thereby effectively preventing, or may reduce the occurrence of the ESD bruise.

The oxide pattern may include, for example, at least one of metal oxides such as titanium oxide, tantalum oxide, tungsten oxide, aluminum oxide, copper oxide, silicon oxide, and combinations thereof. However, the present disclosure is not limited thereto. In some example embodiments, the second material pattern154may include a low refractive index material that has a lower refractive index than that of silicon (Si). In this case, the second material pattern154may improve the light condensing efficiency by refracting or reflecting the light incident obliquely to the photoelectric conversion layer112, thereby improving the quality of the image sensor.

In some example embodiments, a first protective film160may be further formed on the surface insulating film140and the grid pattern150. The first protective film160may conformally extend along a profile of a top surface of the surface insulating film140, a side surface of the grid pattern150, and a top surface of the grid pattern150. The first protective film160may be interposed between the surface insulating film140and the color filter layer170and between the grid pattern150and the color filter layer170.

The first protective film160may prevent or reduce damage to the surface insulating film140and the grid pattern150. The first protective film160may include, for example, aluminum oxide. However, the present disclosure is not limited thereto.

The planarization film180may be formed on the color filter layer170. The planarization film180may cover the color filter layer170. The planarization film180may include insulating material. For example, the planarization film180may include silicon oxide. However, the present disclosure is not limited thereto.

Each of first-first to first-tenth micro-lenses ML11to ML110may cover each of the first-first to first-tenth adjacent pixels AP11to AP110. Each of second-first to second-tenth micro-lenses ML21to ML210may cover each of the second-first to second-tenth adjacent pixels AP21to AP210. Each of third-first to third-tenth micro-lenses ML31to ML310may cover each of the third-first to third-tenth adjacent pixels AP31to AP310. Each of fourth-first to fourth-tenth micro-lenses ML41to ML410may cover each of the fourth-first to fourth-tenth adjacent pixels AP41to AP410. A seventh micro-lens ML7may cover the first-first and first-second focus pixels FP11and FP12, the second-first and second-second focus pixels FP21and FP22, the third-first and third-second focus pixels FP31and FP32, and the fourth-first and fourth-second focus pixels FP41and FP42. The eighth micro-lens ML8may cover the normal pixel NP.

Each of the first-first adjacent pixel AP11, the second-first adjacent pixel AP21, the third-first adjacent pixel AP31and the fourth-first adjacent pixel AP41may be adjacent to each of the first-first focus pixel FP11, the second-first focus pixel FP21, the third-first focus pixel FP31and the fourth-first focus pixel FP41in a negative first direction DR1.

Referring toFIG.5andFIG.7AtoFIG.7D, the intensity of the pixel signal output from the first-first adjacent pixel AP11in the R1 area is greater than the intensity of the pixel signal output from the normal pixel NP in the R1 area. The intensity of the pixel signal output from the second-first adjacent pixel AP21in the R2 area is greater than the intensity of the pixel signal output from the normal pixel NP in the R2 area, but is lower than the intensity of the pixel signal output from the first-first adjacent pixel AP11. The intensity of the pixel signal output from the third-first adjacent pixel AP31in the R3 area is the same or substantially the same as the intensity of the pixel signal output from the normal pixel NP in the R3 area. The intensity of the pixel signal output from the fourth-first adjacent pixel AP41in the R4 area is lower than the intensity of the pixel signal output from the normal pixel NP in the R4 area. That is, the intensity of the pixel signal output from the first-first adjacent pixel AP11is greater than the intensity of the pixel signal output from the second-first adjacent pixel AP21. The intensity of the pixel signal output from the second-first adjacent pixel AP21is greater than the intensity of the pixel signal output from the third-first adjacent pixel AP31. The intensity of the pixel signal output from the third-first adjacent pixel AP31is greater than the intensity of the pixel signal output from the fourth-first adjacent pixel AP41.

Accordingly, an area S11of the first-first micro-lens ML11, an area S21of the second-first micro-lens ML21, an area S31of the third-first micro-lens ML31, and an area S41of the fourth-first micro-lens ML41may be different from each other. Each of the area S11of the first-first micro-lens ML11and the area S21of the second-first micro-lens ML21may be smaller than an area S8of an eighth micro-lens ML8. The area S11of the first-first micro-lens ML11may be smaller than the area S21of the second-first micro-lens ML21. The area S31of the third-first micro-lens ML31may be the same or substantially the same as the area S8of the eighth micro-lens ML8. In this connection, “same” means not only exactly the same, but also includes a slight difference that may occur due to a margin on a process. The area S41of the fourth-first micro-lens ML41may be larger than the area S8of the eighth micro-lens ML8. Accordingly, the intensity of the pixel signal output from each of the first-first adjacent pixel AP11and the second-first adjacent pixel AP21may be reduced, while the intensity of the pixel signal output from the fourth-first adjacent pixel AP41may be increased, thereby compensating for a difference between the intensity of the pixel signal output from each of the first-first adjacent pixel AP11, the second-first adjacent pixel AP21, and the fourth-first adjacent pixel AP41and the intensity of the pixel signal output from the normal pixel NP.

Further, each of the first-second adjacent pixel AP12, the second-second adjacent pixel AP22, the third-second adjacent pixel AP32and fourth-second adjacent pixel AP42may be adjacent to each of the first-second focus pixel FP12, the second-second focus pixel FP22, the third-second focus pixel FP32and the fourth-second focus pixel FP42in a positive first direction DR1.

Referring toFIG.6andFIG.7AtoFIG.7E, the intensity of the pixel signal output from the first-second adjacent pixel AP12in the R1 area is lower than the intensity of the pixel signal output from the normal pixel NP. The intensity of the pixel signal output from the second-second adjacent pixel AP22in the R2 area is lower than the intensity of the pixel signal output from the normal pixel NP, but is greater than the intensity of the pixel signal output from the first-second adjacent pixel AP12. The intensity of the pixel signal output from the third-second adjacent pixel AP32in the R3 area is the same or substantially the same as the intensity of the pixel signal output from the normal pixel NP. The intensity of the pixel signal output from the fourth-second adjacent pixel AP42in the R4 area is greater than the intensity of the pixel signal output from the normal pixel NP.

Therefore, each of an area S12of the first-second micro-lens ML12and an area S22of the second-second micro-lens ML22may be larger than the area S8of the eighth micro-lens ML8. The area S12of the first-second micro-lens ML12may be larger than the area S21of the second-second micro-lens ML22. An area S32of the third-second micro-lens ML32may be the same or substantially the same as the area S8of the eighth micro-lens ML8. An area S42of the fourth-second micro-lens ML42may be smaller than the area S8of the eighth micro-lens ML8. Accordingly, the intensity of the pixel signal output from the first-second adjacent pixel AP12and the second-second adjacent pixel AP22may be increased, while the intensity of the pixel signal output from the fourth-second adjacent pixel AP42may be reduced, thereby compensating for a difference between the intensity of the pixel signal output from each of the first-second adjacent pixel AP12, the second-second adjacent pixel AP22, and the fourth-second adjacent pixel AP42and the intensity of the pixel signal output from the normal pixel NP.

Similarly, referring to the third contour C3inFIG.4, for example, an area S13of the first-third micro-lens ML13may be larger than an area S23of the second-third micro-lens ML23. The area S23of the second-third micro-lens ML23may be larger than an area S33of the third-third micro-lens ML33. The area S33of the third-third micro-lens ML33may be larger than an area S43of the fourth-third micro-lens ML43. Referring to the fourth contour C4ofFIG.4, for example, an area S14of the first-4 micro-lens ML14may be larger than an area S24of the second-fourth micro-lens ML24. The area S24of the second-fourth micro-lens ML24may be larger than an area S34of the third-fourth micro-lens ML34. The area S34of the third-fourth micro-lens ML34may be larger than an area S44of the fourth-fourth micro-lens ML44. Referring to the fifth contour C5ofFIG.4, for example, an area S15of the first-fifth micro-lens ML15may be smaller than an area S25of the second-fifth micro-lens ML25. The area S25of the second-fifth micro-lens ML25may be smaller than an area S35of the third-fifth micro-lens ML35. The area S35of the third-fifth micro-lens ML35may be smaller than an area S45of the fourth-fifth micro-lens ML45. Referring to the sixth contour C6ofFIG.4, for example, an area S16of the first-sixth micro-lens ML16may be smaller than an area S26of the second-sixth micro-lens ML26. The area S26of the second-sixth micro-lens ML26may be smaller than an area S36of the third-sixth micro-lens ML36. The area S36of the third-sixth micro-lens ML36may be smaller than an area S46of the fourth-sixth micro-lens ML46. An area S17of the first-seventh micro-lens ML17, an area S27of the second-seventh micro-lens ML27, an area S37of the third-seventh micro-lens ML37, and an area S47of the fourth-seventh micro-lens ML7may be determined with reference to the seventh contour C7as shown inFIG.4. An area S18of the first-eighth micro-lens ML18, an area S28of the second-eighth micro-lens ML28, an area S38of the third-eighth micro-lens ML38, and an area S48of the fourth-eighth micro-lens ML8may be determined with reference to eighth contour C8as shown inFIG.4. An area S19of the first-ninth micro-lens ML19, an area S29of the second-ninth micro-lens ML29, an area S39of the third-ninth micro-lens ML39, and an area S49of the fourth-ninth micro-lens ML9may be determined with reference to the ninth contour C9as shown inFIG.4. An area S110of the first-tenth micro-lens ML110, an area S210of the second-tenth micro-lens ML210, an area S310of the third-tenth micro-lens ML310, and an area S410of the fourth-tenth micro-lens ML10may be determined with reference to tenth contour C10as shown inFIG.4.

Referring toFIG.7AtoFIG.7D, in some example embodiments, an area of each of the first-first to first-tenth micro-lenses ML11to ML110, the second-first to second-tenth micro-lenses ML21to ML210, the third-first to third-tenth micro-lenses ML31to ML310, and the fourth-first to fourth-tenth micro-lenses ML41to ML410may vary based on a width thereof in a direction in which each lens is adjacent to the seventh micro-lens ML7. For example, each of a maximum width W11of the first-first micro-lens ML11and a maximum width W21of the second-first micro-lens ML21in the first direction DR1may be smaller than a maximum width of the eighth micro-lens ML8in the first direction DR1. Each of a maximum width W21of the first-first micro-lens ML11and a maximum width W22of the second-first micro-lens ML21in the second direction DR2may be equal or substantially equal to a maximum width of the eighth micro-lens ML8in the second direction DR2. The maximum width W11of the first-first micro-lens ML11may be smaller than the maximum width W21of the second-first micro-lens ML21.

In some example embodiments, an area of each of the first-first to first-tenth micro-lenses ML11to ML110, the second-first to second-tenth micro-lenses ML21to ML210, the third-first to third-tenth micro-lenses ML31to ML310, and the fourth-first to fourth-tenth micro-lenses ML41to ML410may vary based on a minimum spacing between each micro-lens and the seventh micro-lens ML7in a direction in which each micro-lens is adjacent to the seventh micro-lens ML7, or a maximum spacing between each micro-lens and the seventh micro-lens ML7in the third direction DR3in which each micro-lens overlaps the seventh micro-lens ML7. The micro-lens may overlap when an outer bound of the shape of the micro-lens which contacts, or would contact, the planarization film180intersects another outer bound of a micro-lens.

A minimum spacing D1between the first-first micro-lens ML11and the seventh micro-lens ML7in the first direction DR1and in the R1 area may be greater than a minimum spacing D2between the second-first micro-lens ML21and the seventh micro-lens ML7in the first direction DR1and in the R2 area. In still another example, in the R4 area, the fourth-second micro-lens ML42may be spaced apart from the seventh micro-lens ML7by a minimum spacing D3in the first direction DR1. That is, the first-first micro-lens ML11and the seventh micro-lens ML7in the R1 area may not contact each other. The second-first micro-lens ML21and the seventh micro-lens ML7in the R2 area may not contact each other. The fourth-second micro-lens ML42and the seventh micro-lens ML7in the R4 area may not contact each other.

In this connection, the maximum width W11of the first-first adjacent pixel AP11in the first direction DR1may refer to a spacing between a first start point thereof and a first end point adjacent to the first-first focus pixel FP11. A maximum width of the normal pixel NP adjacent to the first-first adjacent pixel AP11in the first direction DR1may refer to a spacing between a second start point and a second end point. The second start point may be disposed on a first extension line L1extending from the first start point in the second direction DR2. The second end point may not be disposed on a second extension line L2extending from the first end point in the second direction DR2, but may be positionally-biased in a positive first direction DR1relative to the second extension line L2.

Thus, for example, a top surface of the planarization film180between the first-first micro-lens ML11and the seventh micro-lens ML7in the R1 area, between the second-first micro-lens ML21and the seventh micro-lens ML7in the R2 area, and between the fourth-second micro-lens ML42and the seventh micro-lens ML7in the R4 area may be exposed and may be in contact with the second protective film185. Further, the seventh micro-lens ML7and the first-second micro-lens ML12in the R1 area may overlap each other in the third direction DR3. The seventh micro-lens ML7and the second-second micro-lens ML22in the R2 area may overlap each other in the third direction DR. The fourth-first micro-lens ML41and the seventh micro-lens ML7in the R4 area may overlap each other in the third direction DR3. Accordingly, each of a point where the seventh micro-lens ML7and the first-second micro-lens ML12in the R1 area come in contact each other, a point where the seventh micro-lens ML7and the second-second micro-lens ML22in the R2 area come into contact with each other, and a point where the fourth-first micro-lens ML41and the seventh micro-lens ML7in the R4 area come into contact with each other may be disposed above a top surface of the planarization film180.

FIGS.9and10are schematic layout diagrams of the R1 area inFIGS.5and6. For convenience of description, differences from the previous description will be mainly described below.

Referring toFIG.9, in the image sensor according to some example embodiments, an area of each of the first-first to first-tenth micro-lenses ML11to ML110may vary based on a width thereof in a direction intersecting a direction in which each micro-lens is adjacent to the seventh micro-lens ML7. For example, a maximum width W11′ of the first-first micro-lens ML11in the first direction DR1may be equal or substantially equal to a maximum width of the eighth micro-lens ML8in the first direction DR1. A maximum width W21′ of the first-first micro-lens ML11in the second direction DR2may be smaller than a maximum width of the eighth micro-lens ML8in the second direction DR2. Further, the first-second micro-lens ML12may overlap, in the third direction DR3, the eighth micro-lens ML8covering each of the normal pixels NP adjacent to the first-second micro-lens ML12in the second direction DR2.

Referring toFIG.10, in the image sensor according to some example embodiments, an area of each of the first-first to first-tenth micro-lenses ML11to ML110may vary based on a maximum width thereof in the first direction DR1and/or the second direction DR2. Further, an outermost point of the first-first micro-lens ML11in a negative first direction DR1may be deviated in a positive first direction DR1from an outermost point in the negative first direction DR1of the normal pixel NP adjacent to the first-first micro-lens ML11in the second direction DR2. However, the present disclosure is not limited thereto. An area of each of the first-first to first-tenth micro-lenses ML11to ML110, the second-first to second-tenth micro-lenses ML21to ML210, the third-first to third-tenth micro-lenses ML31to ML310and the fourth-first to fourth-tenth micro-lenses ML41to ML410may vary in various manners.

FIG.11is a cross-sectional view taken along a line A-A′ of the R1 area ofFIG.5andFIG.6. For convenience of description, differences from the previous description will be mainly described below.

Referring toFIG.11, in the image sensor according to some example embodiments, a top surface of the planarization film180between the first-first micro-lens ML11and the seventh micro-lens ML7may be recessed180C into the planarization film180.

FIG.12is a diagram to illustrate a first pixel group ofFIG.3.FIG.13is a diagram to illustrate a second pixel group ofFIG.3.FIG.14is a diagram to illustrate a third pixel group ofFIG.3.

Referring toFIG.3andFIG.12, the pixels of the first pixel group PG1may be arranged in a bayer pattern form. The group may include a pixel in which a blue color filter B is disposed, a pixel in which a green color filter G is disposed, and a pixel in which a red color filter R is disposed. The pixels having the green color filters G respectively may be arranged in a diagonal direction, that is, in the fourth direction DR4, rather than in the first direction DR1and the second direction DR2.

Referring toFIG.3andFIG.13, the pixels of the second pixel group PG2may be arranged in a tetra pattern form. For example, pixels having blue color filters B respectively may be arranged in a 2×2 form. Pixels having green color filters G respectively may be arranged in a 2×2 form. Pixels having red color filters R respectively may be arranged in a 2×2 form. The tetra pattern may be similar to the bayer pattern, with each group of color filters being in a 2×2 form.

Referring toFIG.3andFIG.14, the pixels of the third pixel group PG3may be arranged in a nona pattern form. For example, pixels having blue color filters B respectively may be arranged in a 3×3 form. Pixels having green color filters G respectively may be arranged in a 3×3 form. Pixels having red color filters R respectively may be arranged in a 3×3 form. The nona pattern may be similar to the bayer pattern, with each group of color filters being in a 3×3 form.

In this connection, each pixel may be one of the plurality of focus pixels FP1and FP2, the plurality of adjacent pixels AP1to AP10, and the plurality of normal pixels NP as described above. The color filter may be the color filter170ofFIG.8AtoFIG.8Eas described above. Further, the present disclosure is not limited thereto. The pixels may be arranged in a hexadeca pattern form in which pixels having blue color filters B respectively may be arranged in a 4×4 form, pixels having green color filters G respectively may be arranged in a 4×4 form, and pixels having red color filters R respectively may be arranged in a 4×4 form.

FIG.15is a diagram to illustrate the pixel signal of the light-receiving area ofFIG.3. For convenience of description, differences from the previous description will be mainly described below.

Referring toFIG.3andFIG.15, in the image sensor according to some example embodiments, an area of the micro-lens covering each of the first to tenth adjacent pixels AP1to AP10may vary based on each of the first to tenth contours C1to C10. For example, the intensity of the pixel signal output from the fifth adjacent pixel AP5increases as a position is father away from the center of the light-receiving area APS in the positive second direction DR2, that is, decreases as a position is closer to the center of the light-receiving area APS in the negative second direction DR2. Thus, an area of the micro-lens covering the fifth adjacent pixel AP5disposed at the highest level in the positive second direction DR2in the light-receiving area APS may be smaller than an area of the micro-lens covering the fifth adjacent pixel AP5disposed at the lowest level in the negative second direction DR2in the light-receiving area APS.

FIG.16is a block diagram to illustrate an image sensor according to some example embodiments. For convenience of description, differences from the description usingFIG.2will be mainly described below.

Referring toFIG.16, an image sensor10′ may further include a memory chip50. The memory chip50, the second or lower chip40, and the first or upper chip30may be stacked sequentially in the third direction DR3. The memory chip50may include a memory device. For example, the memory chip50may include a volatile memory device such as DRAM or SRAM. The memory chip50may receive a signal from the upper chip30and the lower chip40and process the signal using the memory device.

FIG.17is a schematic cross-sectional view for illustration of an image sensor according to some example embodiments. For the convenience of description, differences from the previous description will be mainly described below.

Referring toFIG.17, an image sensor according to some example embodiments may include a sensor array area SAR, a connection area CR, and a pad area PR. The sensor array area SAR, the connection area CR, and the pad area PR may be embodied as the sensor array area SAR, the connection area CR, and the pad area PR ofFIG.2andFIG.16, respectively. InFIG.17, the cross-sectional view ofFIG.8Ais shown as a cross-sectional view of the sensor array area SAR by way of example.

In some example embodiments, a first line structure IS1may include a first line132in the sensor array area SAR and a second line134in the connection area CR. The first line132may be electrically connected to pixels of the sensor array area SAR. For example, the first line132may be connected to the first electronic element TR1. At least a portion of the second line134may be electrically connected to at least a portion of the first line132. For example, at least a portion of the second line134may extend from the sensor array area SAR. Accordingly, the second line134may be electrically connected to pixels of the sensor array area SAR.

In some example embodiments, a second protective film185may be further formed on the micro-lenses ML11, ML7, and ML12. The second protective film185may extend along a surface of the micro-lens array ML11, ML7, and ML12. The second protective film185may extend along a top surface of a planarization film170between the first-first micro-lens ML11and the seventh micro-lens ML7. In some example embodiments, the second protective film185may be disposed on the micro-lens array ML11to ML110, ML21to ML210, ML31to ML310, ML41to ML410, M7, and M8as previously described.

The second protective film185may include an inorganic oxide. For example, the second protective film185may include at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof. However, the present disclosure is not limited thereto. In some example embodiments, the second protective film185may include a low-temperature oxide (LTO).

The second protective film185may protect the micro-lens array ML11, ML7, and ML12from the outside. For example, the second protective film185including an inorganic oxide may cover and protect the micro-lens array ML11, ML7, and ML12including an organic material such as a light-transmissive resin. Further, the second protective film185may improve the quality of the image sensor by improving the light condensing efficiency of each of the micro-lenses ML11, ML7, and ML12. For example, the second protective film185may fill spaces between the micro-lenses ML11, ML7, and ML12to reduce reflection, refraction, and scattering of incident light reaching the spaces between the micro-lenses ML11, ML7, and ML12.

The image sensor according to some example embodiments may further include a second substrate210, a second line structure IS2, a first connection structure350, a second connection structure450, a third connection structure550, an element separation pattern115, a light-blocking filter270C, and a third protective film380.

The second substrate210may be made of bulk silicon or SOI (silicon-on-insulator). The second substrate210may be a silicon substrate. Alternatively, the second substrate210may be made of a material such as silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. Alternatively, the second substrate210may include a base substrate and an epitaxial layer formed on the base substrate.

The second substrate210may include a third surface210aand a fourth surface210bopposite to each other. In some example embodiments, the third surface210aof the second substrate210may face toward the second surface110bof the first substrate110.

In some example embodiments, a second electronic element TR2may be formed on the third surface210aof the second substrate210. The second electronic element TR2may be electrically connected to the sensor array area SAR to transmit/receive an electrical signal to and from each pixel of the sensor array area SAR. For example, the second electronic element TR2may include electronic elements constituting the control register block11, the timing generator12, the ramp signal generator13, the row driver14, the readout circuit16ofFIG.1, and the like.

The second line structure IS2may be formed on the third surface210aof the second substrate210. The second line structure IS2may be attached to the first line structure IS1. For example, as shown inFIG.15, a top surface of the second line structure IS2may be attached to a bottom surface of the first line structure IS1.

The second line structure IS2may include one or a plurality of lines. For example, the second line structure IS2may include a second inter-line insulating film230, and a plurality of lines232,234, and236in the second inter-line insulating film230. InFIG.15, the number of layers of the lines constituting the second line structure IS2and the arrangement thereof are only exemplary. Thus, the present disclosure is not limited thereto.

At least some of the lines232,234, and236of the second line structure IS2may be connected to the second electronic element TR2. In some example embodiments, the second line structure IS2may include a third line232in the sensor array area SAR, a fourth line234in the connection area CR, and a fifth line236in the pad area PR. In some example embodiments, the fourth line234may be an uppermost line among the plurality of lines in the connection area CR. The fifth line236may be an uppermost line among the plurality of lines in the pad area PR.

The first connection structure350may be formed in the light-blocking area OB. The first connection structure350may be formed on the surface insulating film140and in the light-blocking area OB. In some example embodiments, the first connection structure350may contact the pixel separation pattern120. For example, a first trench355texposing the pixel separation pattern120may be formed in the first substrate110and the surface insulating film140and in the light-blocking area OB. The first connection structure350may be formed in the first trench355tso as to contact a portion of the pixel separation pattern120in the light-blocking area OB. In some example embodiments, the first connection structure350may extend along a profile of a side surface and a bottom surface of the first trench355t.

In some example embodiments, the first connection structure350may be electrically connected to the conductive filling pattern122to apply a ground voltage or a negative voltage to the conductive filling pattern122. Accordingly, charges resulting from the ESD may be discharged to the first connection structure350via the conductive filling pattern122. Thus, the ESD bruise defects may be effectively prevented, or the occurrence of may be reduced.

The second connection structure450may be formed in the connection area CR. The second connection structure450may be formed on the surface insulating film140and in the connection area CR. The second connection structure450may electrically connect the first substrate110and the second substrate210to each other. For example, a second trench455texposing the second line134and the fourth line234may be formed in the first substrate110, the first line structure IS1, and the second line structure IS2and in the connection area CR. The second connection structure450may be formed in the second trench455tto connect the second line134and the fourth line234to each other. In some example embodiments, the second connection structure450may extend along a profile of a side surface and a bottom surface of the second trench455t.

The third connection structure550may be formed in the pad area PR. The third connection structure550may be formed on the surface insulating film140and in the pad area PR. The third connection structure550may be electrically connected to the second substrate210and an external device.

For example, a third trench550texposing the fifth line236may be formed in the first substrate110, the first line structure IS1, and the second line structure IS2and in the pad area PR. The third connection structure550may be formed in the third trench550tand contact the fifth line236. Further, in a portion of the first substrate110in the pad area PR, a fourth trench555tmay be formed. The third connection structure550may be formed in the fourth trench555tso as to be exposed. In some example embodiments, the third connection structure550may extend along a profile of a side surface and a bottom surface of each of the third trench550tand the fourth trench555t.

Each of the first connection structure350, the second connection structure450and the third connection structure550may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), and combinations thereof. However, the present disclosure is not limited thereto. In some example embodiments, the first connection structure350, the second connection structure450, and the third connection structure550may be formed at the same level or substantially the same level. In this specification, “being formed at substantially the same level” means being formed using the same manufacturing process.

In some example embodiments, a first pad355filling the first trench355tmay be formed on the first connection structure350. In some example embodiments, on the third connection structure550, a second pad555filling the fourth trench555tmay be formed. Each of the first pad355and the second pad555may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof. However, the present disclosure is not limited thereto. In some example embodiments, the first pad355and the second pad555may be formed at the same level or substantially the same level.

In some example embodiments, a first filling insulating film460filling the second trench455tmay be formed on the second connection structure450. In some example embodiments, a second filling insulating film560filling the third trench550tmay be formed on the third connection structure550. Each of the first filling insulating film460and the second filling insulating film560may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof. However, the present disclosure is not limited thereto. In some example embodiments, the first filling insulating film460and the second filling insulating film560may be formed at the same level or substantially the same level.

In some example embodiments, the first protective film160may cover the first connection structure350, the first pad355, the second connection structure450, and the third connection structure550. For example, the first protective film160may conformally extend along a profile of each of the first connection structure350, the first pad355, the second connection structure450, and the third connection structure550. In some example embodiments, the first protective film160may expose the second pad555.

The element separation pattern115may be formed in the first substrate110. For example, an element separation trench115tmay be formed in the first substrate110. The element separation pattern115may be formed in the element separation trench115t. In some example embodiments, the element separation pattern115may extend from the first surface110aof the first substrate110. In some example embodiments, the element separation pattern115may be spaced apart from the second surface110bof the first substrate110.

FIG.18is a schematic cross-sectional view to illustrate an image sensor according to some example embodiments. For convenience of description, differences from the description usingFIG.17will be mainly described below.

Referring toFIG.18, in the image sensor according to some example embodiments, a width of the pixel separation pattern120may increase as the pattern extends away from the second surface110bof the first substrate110. This may be due to the characteristics of the etching process for forming the pixel separation pattern120. For example, a process of etching the first substrate110to form the pixel separation pattern120may be performed on the first surface110aof the first substrate110.

In some example embodiments, the pixel separation pattern120may not completely extend through the first substrate110. For example, the pixel separation pattern120may extend from the first surface110aof the first substrate110but not to the second surface110bof the first substrate210. That is, the lowermost surface of the pixel separation pattern120may be disposed in the first substrate110.

FIG.19is a block diagram of an electronic device including a multi-camera module.FIG.20is a detailed block diagram of a camera module ofFIG.19.

Referring toFIG.19, an electronic device1000may include a camera module group1100, an application processor1200, a PMIC1300and an external memory1400.

The camera module group1100may include a plurality of camera modules1100a,1100b, and1100c. Although the drawing shows some example embodiments in which the three camera modules1100a,1100b, and1100care arranged, example embodiments of the present disclosure is not limited thereto. In some example embodiments, the camera module group1100may be modified to include only two camera modules. Further, in some example embodiments, the camera module group1100may be modified to include n camera modules (n being a natural number equal to or greater than 4).

Hereinafter, with reference toFIG.20, a detailed configuration of the camera module1100bwill be described more specifically. A following description may be equally applied to other camera modules1100aand1100cdepending on some example embodiments.

Referring toFIG.20, the camera module1100bmay include a prism1105, an optical path folding element (hereinafter, “OPFE”)1110, an actuator1130, an image sensing device1140, and a storage1150.

The prism1105may include a reflective surface1107made of a light reflective material, and thus may change a path of light L incident from the outside.

In some example embodiments, the prism1105may change the path of light L incident in the first direction X into the second direction Y perpendicular to the first direction X. Further, the prism1105may rotate the reflective surface1107made of the light reflective material around a center axis1106in an A direction or may rotate the center axis1106in a B direction so that the path of the light L incident in the first direction X may be changed to the second direction Y perpendicular thereto. In this connection, the OPFE1110may move in a third direction Z perpendicular to a plane including the first direction X and the second direction Y.

In some example embodiments, as shown, a maximum rotation angle in the A direction of the prism1105may be smaller than or equal to about or exactly 15 degrees in a plus (+) A direction, and may be greater than about or exactly 15 degrees in a minus (−) A direction. However, example embodiments of the present disclosure is not limited thereto.

In some example embodiments, the prism1105may move by a range about or exactly 20 degrees, or between about or exactly 10 and about or exactly 20 degrees, or between about or exactly 15 and about or exactly 20 degrees in the plus (+) or minus (−) B direction. In this connection, the prism1105may move by the same angle in the plus (+) and minus (−) B directions. Alternatively, angles by which the prism1105may move in the plus (+) and minus (−) B directions, respectively may have a difference of about or exactly 1 degree therebetween.

In some example embodiments, the prism1105may move the reflective surface1106made of the light reflective material in the third direction, for example, the Z direction parallel to an extension direction of the center axis1106.

The OPFE1110may include a group of m optical lens (m being a natural number). The group of m optical lenses may move in the second direction Y to change an optical zoom ratio of the camera module1100b. For example, a basic optical zoom ratio of the camera module1100bmay be Z. When the m optical lenses included in the OPFE1110move, the optical zoom ratio of the camera module1100bmay be changed to an optical zoom ratio equal to or higher than 3Z or 5Z.

The actuator1130may move the OPFE1110or the optical lens to a specific position. For example, the actuator1130may adjust a position of the optical lens so that the image sensor1142is located at a focal length of the optical lens for accurate sensing.

The image sensing device1140may include an image sensor1142, a control logic1144and a memory1146. The image sensor1142may sense an image of a sensing target using the light L provided through the optical lens. The control logic1144may control all of operations of the camera module1100b. For example, the control logic1144may control an operation of the camera module1100bbased on a control signal provided through a control signal line CSLb.

The memory1146may store therein information necessary (or beneficial or useful) for the operation of the camera module1100b, such as calibration data1147. The calibration data1147may include information required when the camera module1100bgenerates image data using the light L provided from the outside. The calibration data1147may include, for example, information about a degree of rotation, information about a focal length, information about an optical axis, and the like, as described above. When the camera module1100bis implemented in a multi-state camera form in which the focal length varies based on a position of the optical lens, the calibration data1147may include a focal length value based on each position (or each state) of the optical lens, and information related to auto focusing.

The storage1150may store therein image data sensed via the image sensor1142. The storage1150may be disposed outside the image sensing device1140, and may be implemented to be stacked on a sensor chip constituting the image sensing device1140. In some example embodiments, the storage1150may be embodied as an EEPROM (Electrically Erasable Programmable Read-Only Memory). However, example embodiments of the present disclosure is not limited thereto.

Referring toFIG.19andFIG.20together, in some example embodiments, each of the plurality of camera modules1100a,1100b, and1100cmay include each actuator1130. Accordingly, each of the plurality of camera modules1100a,1100b, and1100cmay include the same or different calibration data1147based on an operation of the actuator1130included therein.

In some example embodiments, one camera module (e.g.,1100b) among the plurality of camera modules1100a,1100b, and1100cmay be a camera module in a folded lens form including the prism1105and the OPFE1110as described above, while each of the remaining camera modules (e.g.,1100aand1100c) may be a vertical type camera module that does not include the prism1105and the OPFE1110. However, example embodiments are not limited thereto.

In some example embodiments, one camera module (e.g.,1100c) among the plurality of camera modules1100a,1100b, and1100c, may be a depth camera of a vertical form that extracts depth information, for example, using IR (Infrared Ray). In this case, the application processor1200may merge image data provided from the depth camera and image data provided from another camera module (e.g.,1100aor1100b) to generate a three-dimensional depth image (3D depth image).

In some example embodiments, at least two (e.g.,1100aand1100b) of the plurality of camera modules1100a,1100b, and1100cmay have different FOVs (Field of Views). In this case, for example, at least two of the plurality of camera modules1100a,1100b, and1100c, for example, optical lenses of at least two (e.g.,1100aand1100b) of the plurality of camera modules1100a,1100b, and1100cmay be different from each other. However, the present disclosure is not limited thereto.

Further, in some example embodiments, FOVs of the plurality of camera modules1100a,1100b, and1100cmay be different from each other. In this case, the optical lenses respectively included in the plurality of camera modules1100a,1100b, and1100cmay also be different from each other. However, the present disclosure is not limited thereto.

In some example embodiments, the plurality of camera modules1100a,1100b, and1100cmay be physically separated from each other. That is, instead of a scheme in which a sensing area of one image sensor1142are divided into a plurality of sub-areas which correspond to the plurality of camera modules1100a,1100b, and1100c, a scheme in which an individual image sensor1142may be disposed in each of the plurality of camera modules1100a,1100b, and1100cmay be employed.

Referring back toFIG.19, the application processor1200may include an image processing device1210, a memory controller1220, and an internal memory1230. The application processor1200may be implemented to be separated from the plurality of camera modules1100a,1100b, and1100c. For example, the application processor1200and the plurality of camera modules1100a,1100b, and1100cmay be implemented as separate semiconductor chips separated from each other.

The image processing device1210may include a plurality of auxiliary image processors1212a,1212b, and1212c, an image generator1214and a camera module controller1216.

The number of the auxiliary image processors1212a,1212b, and1212cmay correspond to the number of camera modules1100a,1100b, and1100c.

Image data generated from each of the camera modules1100a,1100b, and1100cmay be provided to each of the auxiliary image processors1212a,1212b, and1212cvia each of image signal lines ISLa, ISLb, and ISLc separated from each other. For example, the image data generated from the camera module1100amay be transmitted to the auxiliary image processor1212avia the image signal line ISLa. The image data generated from the camera module1100bmay be transmitted to the auxiliary image processor1212bvia the image signal line ISLb. The image data generated from the camera module1100cmay be transmitted to the auxiliary image processor1212cvia the image signal line ISLc. The image data transmission may be performed, for example, using a camera serial interface (CSI) based on a MIPI (Mobile Industry Processor Interface). However, example embodiments of the present disclosure are not limited thereto.

In some example embodiments, one auxiliary image processor may correspond to a plurality of camera modules. For example, the auxiliary image processor1212aand the auxiliary image processor1212cmay not be implemented separately from each other as shown, but may be integrated into one auxiliary image processor. The image data provided from the camera module1100aand the camera module1100cmay be selected via a selection element, for example, a multiplexer, and then may be provided to the integrated auxiliary image processor.

The image data provided to each of the auxiliary image processors1212a,1212b, and1212cmay be provided to the image generator1214. The image generator1214may generate an output image using the image data provided from each of the auxiliary image processors1212a,1212b, and1212cand based on image generation information or a mode signal.

Specifically, the image generator1214may merge at least a portion of the image data generated from the camera modules1100a,1100b, and1100chaving different FOVs, and based on the image generation information or the mode signal, and thus may generate the output image as the merging result. Further, the image generator1214may select one of the image data generated from the camera modules1100a,1100b, and1100chaving different FOVs, and based on the image generation information or the mode signal and thus may generate the output image as the selected data.

In some example embodiments, the image generation information may include a zoom signal or a zoom factor. Further, in some example embodiments, the mode signal may be, for example, a signal based on a mode selected by a user.

When the image generation information is the zoom signal or the zoom factor, and the camera modules1100a,1100b, and1100chave different FOVs, the image generator1214may perform different operations based on types of the zoom signal. For example, when the zoom signal is a first signal, the image generator may merge the image data output from the camera module1100aand the image data output from the camera module1100cwith each other, and generate the output image using the merged image data, and the image data output from the camera module1100bnot used in the merging operation. When the zoom signal is a second signal different from the first signal, the image generator1214may not perform such an image data merging operation, but may select one of the image data output from the camera modules1100a,1100b, and1100cand may generate the selected data as the output image. However, example embodiments are not limited thereto and schemes for processing the image data may be modified as needed or desired.

In some example embodiments, the image generator1214may receive a plurality of image data having different exposure times from at least one of the plurality of auxiliary image processors1212a,1212b, and1212c, and may perform HDR (high dynamic range) processing on the received plurality of image data, thereby generating merged image data having an increased dynamic range.

The camera module controller1216may provide a control signal to each of the camera modules1100a,1100b, and1100c. The control signal generated from the camera module controller1216may be provided to a corresponding one of the camera modules1100a,1100b, and1100cvia a corresponding one of the control signal lines CSLa, CSLb, and CSLc separated from each other.

One of the plurality of camera modules1100a,1100b, and1100cmay be designated as a master camera (e.g.,1100b) based on the image generation information including the zoom signal or the mode signal, while each of the remaining camera modules (e.g.,1100aand1100c) may be designated as a slave camera. This designation information may be included in the control signal and may be provided to a corresponding one of the camera modules1100a,1100b, and1100cvia a corresponding one of the control signal lines CSLa, CSLb, and CSLc separated from each other.

The camera module acting as the master or slave camera may vary based on the zoom factor or an operation mode signal. For example, when the FOV of the camera module1100ais larger than that of the camera module1100b, and the zoom factor indicates a low zoom ratio, the camera module1100bmay act as a master camera, while the camera module1100amay act as a slave camera. Conversely, when the zoom factor indicates a high zoom ratio, the camera module1100amay act as a master camera, while the camera module1100bmay act as a slave camera.

In some example embodiments, the control signal from the camera module controller1216provided to each of the camera modules1100a,1100b, and1100cmay include a sync enable signal. For example, when the camera module1100bis the master camera, and each of the camera modules1100aand1100cis the slave camera, the camera module controller1216may transmit the sync enable signal to the camera module1100b. Upon receiving such a sync enable signal, the camera module1100bmay generate a sync signal based on the provided sync enable signal, and may provide the generated sync signal to the camera modules1100aand1100cvia a sync signal line SSL. The camera module1100band the camera modules1100aand1100cmay transmit the image data to the application processor1200while the camera module1100band the camera modules1100aand1100care synchronized with each other using the sync signal.

In some example embodiments, the control signal from the camera module controller1216provided to each of the plurality of camera modules1100a,1100b, and1100cmay include mode information according to the mode signal. Based on this mode information, the plurality of camera modules1100a,1100b, and1100cmay operate in a first operation mode or a second operation mode in relation to a sensing speed.

In the first operation mode, the plurality of camera modules1100a,1100b, and1100cmay generate an image signal at a first speed (for example, may generate an image signal at a first frame rate), may encode the image signal at a second speed higher than the first speed (for example, encode the image signal at a second frame rate higher than the first frame rate) and may transmit the encoded image signal to the application processor1200. In this connection, the second speed may be lower than or equal to 30 times of the first speed.

The application processor1200may store the received image signal, that is, the encoded image signal, in the memory1230provided therein, or a storage1400external to the application processor1200, and then, read and decode the encoded image signal from the memory1230or the storage1400, and then, display image data generated based on the decoded image signal. For example, a corresponding auxiliary processor among the plurality of auxiliary processors1212a,1212b, and1212cof the image processing device1210may perform the decoding, and may perform the image processing on the decoded image signal.

In the second operation mode, the plurality of camera modules1100a,1100b, and1100cmay generate an image signal at a third speed lower than the first speed (for example, generate an image signal at a third frame rate lower than the first frame rate), and then transmit the image signal to the application processor1200. The image signal provided to the application processor1200may be an unencoded signal. The application processor1200may perform image processing on the received image signal or may store the image signal in the memory1230or the storage1400.

The PMIC1300may supply power, for example, a power supply voltage to each of the plurality of camera modules1100a,1100b, and1100c. For example, the PMIC1300may supply first power to the camera module1100athrough a first power signal line PSLa, supply second power to the camera module1100bthrough a second power signal line PSLb, and supply third power to the camera module1100cthrough a third power signal line PSLc, under control of the application processor1200.

The PMIC1300may generate power corresponding to each of the plurality of camera modules1100a,1100b, and1100cand adjust a power level, in response to a power control signal PCON from the application processor1200. The power control signal PCON may include an operation mode-based power adjustment signal for the plurality of camera modules1100a,1100b, and1100c. For example, the operation mode may include a low power mode and a low power mode. In this connection, the power control signal PCON may include information about a camera module operating in the low power mode and a set power level. Levels of powers provided to the plurality of camera modules1100a,1100b, and1100cmay be the same as or different from each other. Further, the level of the power may vary dynamically.

The image signal processor20(or other circuitry, for example, the timing generator12, control register block11, RAMP signal generator13, row driver14, readout circuit16, buffer17, electronic device1000, application processor1200, image generator1214, camera module controller1216, memory controller1220, PMIC1300, camera1100a(1100b,1100c, etc.), or other circuitry discussed herein) may include hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.

Although the example embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these example embodiments. The present disclosure may be implemented in various modified manners within the scope not departing from the technical idea of the present disclosure. Accordingly, the embodiments disclosed in the present disclosure are not intended to limit the technical idea of the present disclosure, but to describe the present disclosure. the scope of the technical idea of the present disclosure is not limited by the embodiments. Therefore, it should be understood that the embodiments as described above are illustrative and non-limiting in all respects. The scope of protection of the present disclosure should be interpreted by the claims, and all technical ideas within the scope of the present disclosure should be interpreted as being included in the scope of the present disclosure.