Metal-oxide-metal capacitor with improved alignment and reduced capacitance variance

A capacitor has reduced misalignment in the interconnect layers and lower capacitance variance. The capacitor includes a first endcap having a first section and a second section orthogonal to the first section. The capacitor includes a first set of conductive fingers orthogonally coupled to the first section. The capacitor includes a third set of conductive fingers orthogonally coupled to the second section of the endcap and a second endcap parallel to the first section of the endcap. The capacitor includes a second set of conductive fingers orthogonally coupled to a second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. The capacitor includes a third endcap parallel to the second section of the first endcap and a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.

BACKGROUND

Field

Aspects of the present disclosure relate to semiconductor devices and, more particularly, to a metal-oxide-metal (MOM) capacitor with robust alignment and reduced capacitance variance.

Background

Mobile radio frequency (RF) chips (e.g., mobile RF transceivers) have migrated to a deep sub-micron process node due to cost and power consumption considerations. Designing mobile RF transceivers is further complicated by added circuit functions for supporting communication enhancements, such as carrier aggregation. Further design challenges for mobile RF transceivers include using passive devices, which directly affect analog/RF performance considerations, including mismatch, noise, and other performance considerations.

Passive devices may involve high performance capacitor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors. These integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors, metal-insulator-metal (MIM) capacitors, poly-to-poly capacitors, metal-oxide-metal (MOM) capacitors, and other like capacitor structures. MOM capacitors are also known as vertical parallel plate (VPP) capacitors, natural vertical capacitors (NVCAP), lateral flux capacitors, comb capacitors, as well as interdigitated finger capacitors. MOM capacitors exhibit beneficial characteristics including high capacitance density, low parasitic capacitance, superior RF characteristics, and good matching characteristics without additional masks or process steps relative to other capacitor structures.

MOM capacitors are one of the most widely used capacitors due to their beneficial characteristics. MOM capacitor structures realize capacitance by using the fringing capacitance produced by sets of interdigitated fingers. For example, MOM capacitors harness lateral capacitive coupling between plates formed by metallization layers and wiring traces.

The MOM capacitors, however, may be subject to misalignment in each interconnect layer during a fabrication process, such as double patterning lithography and may also be subject to capacitance variance.

SUMMARY

A capacitor may include a first endcap having a first section and a second section that is orthogonal to the first section. The capacitor also includes a first set of conductive fingers orthogonally coupled to the first section of the first endcap. The capacitor also includes a third set of conductive fingers orthogonally coupled to the second section of the first endcap. The capacitor further includes a second endcap parallel to the first section of the first endcap. The capacitor further includes a second set of conductive fingers orthogonally coupled to the second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. Furthermore, the capacitor includes a third endcap parallel to the second section of the first endcap and a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.

A method of making a capacitor may include fabricating, with a first mask, a first endcap having a first section and a second section that is orthogonal to the first section. The method may also include fabricating, with the first mask, a first set of conductive fingers orthogonally coupled to the first section of the first endcap. The method further includes fabricating, with the first mask, a third set of conductive fingers orthogonally coupled to the second section of the first endcap. The method also includes fabricating, with a second mask, a second endcap parallel to the first section of the first endcap. The method further includes fabricating, with the second mask, a second set of conductive fingers orthogonally coupled to the second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. The method further includes fabricating, with the second mask, a third endcap parallel to the second section of the first endcap. Furthermore, the method includes fabricating, with the second mask, a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.

A capacitor may include a first endcap having a first section and a second section that is orthogonal to the first section. The capacitor also includes a first set of conductive fingers orthogonally coupled to the first section of the first endcap. The capacitor also includes a third set of conductive fingers orthogonally coupled to the second section of the first endcap. The capacitor further includes first means for receiving/transmitting charge to/from the capacitor parallel to the first section of the first endcap. The capacitor further includes a second set of conductive fingers orthogonally coupled to the first charge receiving/transmitting means and interdigitated with the first set of conductive fingers at a first interconnect layer. Furthermore, the capacitor includes second means for receiving/transmitting charge to/from the capacitor parallel to the second section of the first endcap and a fourth set of conductive fingers orthogonally coupled to the second charge receiving/transmitting means and interdigitated with the third set of conductive fingers at the first interconnect layer.

DETAILED DESCRIPTION

As described herein, the use of the term “and/or” is intended to represent an “inclusive OR”, and the use of the term “or” is intended to represent an “exclusive OR”. As described herein, the term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As described herein, the term “coupled” used throughout this description means “connected, whether directly or indirectly through intervening connections (e.g., a switch), electrical, mechanical, or otherwise,” and is not necessarily limited to physical connections. Additionally, the connections can be such that the objects are permanently connected or releasably connected. The connections can be through switches. As described herein, the term “proximate” used throughout this description means “adjacent, very near, next to, or close to.” As described herein, the term “on” used throughout this description means “directly on” in some configurations, and “indirectly on” in other configurations.

Passive devices in mobile RF transceivers may include high performance capacitor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors. These integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors, metal-insulator-metal (MIM) capacitors, poly-to-poly capacitors, metal-oxide-metal (MOM) capacitors, and other like capacitor structures. Capacitors are generally passive elements used in integrated circuits for storing an electrical charge. For example, parallel plate capacitors are often made using plates or structures that are conductive with an insulating material between the plates. The amount of storage, or capacitance, for a given capacitor is contingent upon the materials used to make the plates and the insulator, the area of the plates, and the spacing between the plates. The insulating material is often a dielectric material.

These parallel plate capacitors, however, often take up a large area on a semiconductor chip because many designs place the capacitor over the substrate of the chip. Unfortunately, this approach reduces the available area for active devices. Another approach is to create a vertical structure, which may be known as a vertical parallel plate (VPP) capacitor. VPP capacitor structures may be created through stacking of the interconnect layers on a chip.

VPP capacitors structures, however, have lower capacitive storage, or lower density, in that these structures do not store much electrical charge. In particular, the interconnect and via layer interconnect traces used to fabricate VPP capacitors may be very small in size. The spacing between the interconnects and via layer conductive traces in VPP structures is limited by design rules, which often results in a large area for achieving certain desired capacitance for such structures. Although described as “vertical,” these structures can be in any direction that is substantially perpendicular to the surface of the substrate, or at other angles that are not substantially parallel to the substrate.

A MOM capacitor as well as a MOS capacitor are examples of VPP capacitors. MOM capacitors are one of the most widely used capacitors due to their beneficial characteristics. In particular, MOM capacitors are used for providing high quality capacitors in semiconductor processes without incurring the cost of an extra processing step relative to other capacitor structures. MOM capacitor structures realize capacitance by using the fringing capacitance produced by sets of interdigitated fingers. For example, MOM capacitors harness lateral capacitive coupling between plates formed by metallization layers and wiring traces.

MOM capacitors may be subject to misalignment in the interconnect layer during a fabrication process such as double patterning lithography and may also be subject to capacitance variance. Thus, it is desirable to have a MOM capacitor that matches simulation models as closely as possible for circuit design. However, capacitance variance between fabrication and simulation cannot be avoided due to the double patterning process in advanced processes (14 nanometer (nm) and below). The misalignment in the interconnect layer randomly happens in horizontal and vertical directions, which makes the capacitance variation unpredictable.

Various aspects of the present disclosure provide a MOM capacitor with reduced misalignment in the interconnect layer and reduced capacitance variance. For example, the proposed MOM capacitor decreases the capacitance variance by half relative to a conventional implementation when a same probability of occurrence of the capacitance variance exists. The aspects of the present disclosure are characterized by much smaller probability relative to the conventional implementation for a same amount of variance.

The process flow for fabrication of the capacitor may include front-end-of-line (FEOL) processes, middle-of-line (MOL) processes, and back-end-of-line (BEOL) processes. As described, the back-end-of-line interconnect layers may refer to the conductive interconnect layers (e.g., a first interconnect layer (M1) or metal one M1, metal two (M2), metal three (M3), metal four (M4), etc.) for electrically coupling to front-end-of-line active devices of an integrated circuit. The various back-end-of-line interconnect layers are formed at corresponding back-end-of-line interconnect levels, in which lower back-end-of-line interconnect levels use thinner metal layers relative to upper back-end-of-line interconnect levels. The back-end-of-line interconnect layers may electrically couple to middle-of-line interconnect layers, for example, connecting the M1 layer to an oxide diffusion (OD) layer of an integrated circuit. The middle-of-line interconnect layer may include a zero interconnect layer (M0) for connecting the M1 layer to an active device layer of an integrated circuit. A back-end-of-line first via (V2) may connect the M2 layer to the M3 layer or others of the back-end-of-line interconnect layers. It will be understood that the term “layer” includes film and is not to be construed as indicating a vertical or horizontal thickness unless otherwise stated. As described, the term “substrate” may refer to a substrate of a diced wafer or may refer to a substrate of a wafer that is not diced. Similarly, the terms “chip” and “die” may be used interchangeably.

According to aspects of the present disclosure, a capacitor (e.g., a metal-oxide-metal (MOM) capacitor) is formed with reduced misalignment in the interconnect layer and reduced capacitance variance. In some aspects, an integrated circuit may include the MOM capacitor in at least one back-end-of-line (BEOL) interconnect level. The MOM capacitor may have a first endcap (or manifold) having a first section and a second section that is orthogonal to the first section. A first set of conductive fingers is orthogonally coupled to the first section of the first endcap. A third set of conductive fingers is orthogonally coupled to the second section of the first endcap. A second endcap is parallel to the first section of the first endcap. A second set of conductive fingers is orthogonally coupled to the second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. A third endcap is parallel to the second section of the first endcap. A fourth set of conductive fingers is orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.

In one aspect of the disclosure, a capacitance of the second set of conductive fingers interdigitated with the first set of conductive fingers is the same as a capacitance of the fourth set of conductive fingers interdigitated with the third set of conductive fingers. The endcaps may extend through multiple interconnect layers. The capacitor may further include a fifth set of conductive fingers orthogonally coupled to the first section of the first endcap at the second interconnect layer. A sixth set of conductive fingers is orthogonally coupled to the second section of the first endcap at the second interconnect layer. A seventh set of conductive fingers is orthogonally coupled to the second endcap at the second interconnect layer and interdigitated with the fifth set of conductive fingers at the second interconnect layer. An eighth set of conductive fingers is orthogonally coupled to the third endcap and interdigitated with the sixth set of conductive fingers at the second interconnect layer. In one aspect of the disclosure, the first set of conductive fingers and the fifth set of conductive fingers are aligned (e.g., geometrically). In other aspects of the present disclosure, the first set of conductive fingers and the fifth set of conductive fingers are staggered or not geometrically aligned.

FIG. 1is a schematic diagram of a radio frequency (RF) front end (RFFE) module100employing passive devices including a capacitor116(e.g., a metal-oxide-metal capacitor) with reduced misalignment and reduced capacitance variance. The RF front end module100includes power amplifiers102, duplexer/filters104, and a radio frequency (RF) switch module106. The power amplifiers102amplify signal(s) to a certain power level for transmission. The duplexer/filters104filter the input/output signals according to a variety of different parameters, including frequency, insertion loss, rejection, or other like parameters. In addition, the RF switch module106may select certain portions of the input signals to pass on to the rest of the RF front end module100.

The radio frequency (RF) front end module100also includes tuner circuitry112(e.g., first tuner circuitry112A and second tuner circuitry112B), the diplexer200, a capacitor116, an inductor118, a ground terminal115, and an antenna114. The tuner circuitry112(e.g., the first tuner circuitry112A and the second tuner circuitry112B) includes components such as a tuner, a portable data entry terminal (PDET), and a house keeping analog to digital converter (HKADC). The tuner circuitry112may perform impedance tuning (e.g., a voltage standing wave ratio (VSWR) optimization) for the antenna114. The RF front end module100also includes a passive combiner108coupled to a wireless transceiver (WTR)120. The passive combiner108combines the detected power from the first tuner circuitry112A and the second tuner circuitry112B. The wireless transceiver120processes the information from the passive combiner108and provides this information to a modem130(e.g., a mobile station modem (MSM)). The modem130provides a digital signal to an application processor (AP)140.

As shown inFIG. 1, the diplexer200is between the tuner component of the tuner circuitry112and the capacitor116, the inductor118, and the antenna114. The diplexer200may be placed between the antenna114and the tuner circuitry112to provide high system performance from the RF front end module100to a chipset including the wireless transceiver120, the modem130, and the application processor140. The diplexer200also performs frequency domain multiplexing on both high band frequencies and low band frequencies. After the diplexer200performs its frequency multiplexing functions on the input signals, the output of the diplexer200is fed to an optional LC (inductor/capacitor) network including the capacitor116and the inductor118. The LC network may provide extra impedance matching components for the antenna114, when desired. Then, a signal with the particular frequency is transmitted or received by the antenna114. Although a single capacitor and inductor are shown, multiple components are contemplated.

FIG. 2is a schematic diagram of a wireless local area network (WLAN) (e.g., WiFi) module170including a first diplexer200-1and an RF front end (RFFE) module150including a second diplexer200-2for a chipset160, including a capacitor with reduced misalignment and reduced capacitance variance. The WiFi module170includes the first diplexer200-1communicably coupling an antenna192to a wireless local area network module (e.g., WLAN module172). The RF front end module150includes the second diplexer200-2communicably coupling an antenna194to the wireless transceiver (WTR)120through a duplexer180. The wireless transceiver120and the WLAN module172of the WiFi module170are coupled to a modem (MSM, e.g., baseband modem)130that is powered by a power supply152through a power management integrated circuit (PMIC)156. The chipset160includes capacitors162and164, as well as an inductor(s)166to provide signal integrity.

The PMIC156, the modem130, the wireless transceiver120, and the WLAN module172each include capacitors (e.g.,158,132,122, and174) and operate according to a clock154. In addition, the inductor166couples the modem130to the PMIC156. The geometry and arrangement of the various capacitors and inductor in the chipset160may consume substantial chip area. The design of the chipset160likely includes integrating MOM/MIM/MOS capacitors with inductors and/or transformers. Unfortunately, integrating MOM/MIM/MOS capacitors with inductors and/or transformers may degrade performance of the inductors and/or transformers. Consequently, conventional arrangements for implementing multi-turn inductors continue to consume unused area in RF integrated circuit (RFIC) analog devices.

Capacitors are widely used in analog integrated circuits.FIG. 3is a block diagram illustrating a cross-section of an analog integrated circuit (IC) device300including an interconnect stack310. The interconnect stack310of the IC device300includes multiple conductive interconnect layers (M1, . . . , M9, M10) on a semiconductor substrate (e.g., a diced silicon wafer)302. The semiconductor substrate302support a metal-oxide-metal (MOM) capacitor330and/or a metal-oxide-semiconductor (MOS). In this example, the MOM capacitor330is formed in the M3 and M4 interconnect layers, below the M5 and M6 interconnect layers. The MOM capacitor330is formed from lateral conductive fingers of different polarities using the conductive interconnect layers (M3 and M4) of the interconnect stack310. A dielectric (not shown) is provided between the conductive fingers.

In this example, the MOM capacitor330is formed within the lower conductive interconnect layers (e.g., M1-M4) of the interconnect stack310. The lower conductive interconnect layers of the interconnect stack310have smaller interconnect widths and spaces. For example, the dimensions of the conductive interconnect layers M3 and M4 are half the size of the dimensions of the conductive interconnect layers M5 and M6. Likewise, the dimensions of the conductive interconnect layers M1 and M2 are half the size of the dimensions of the conductive interconnect layers M3 and M4. The small interconnect widths and spaces of the lower conductive interconnect layers enable the formation of MOM capacitors with increased capacitance density. As shown inFIG. 3, the MOM capacitor330makes use of a lateral (intra layer) capacitive coupling340between fingers (e.g.,350,370) formed by standard metallization of the conductive interconnects (e.g., wiring lines and vias).

FIGS. 4A-4Cillustrate top views of metal-oxide-metal (MOM) capacitor structures400(including a MOM capacitor structure400A, a MOM capacitor structure400B, and a MOM capacitor structure400C) subject to misalignment in the interconnect layers during fabrication. Each of the MOM capacitor structures400A-400C ofFIGS. 4A-4Cmay be fabricated in one or more BEOL interconnect levels (e.g., M1-M4).

Referring toFIG. 4A, a top view of the MOM capacitor structure400A includes a first capacitor routing terminal (e.g., endcap or manifold)430and a second endcap440. The first endcap430is parallel to the second endcap440. The first endcap430is of a first polarity (e.g., positive) while the second endcap440is of a second polarity (e.g., negative). A first set of parallel conductive capacitor routing traces (e.g., conductive fingers) of the MOM capacitor structure400A include a first conductive finger432, a second conductive finger434, and a third conductive finger436.

Each of the first conductive finger432, the second conductive finger434, and the third conductive finger436is orthogonally coupled to the first endcap430. Each of the first conductive finger432, the second conductive finger434, and the third conductive finger436is of the first polarity.

A second set of parallel conductive fingers of the MOM capacitor structure400A include a fourth conductive finger442, a fifth conductive finger444, and a sixth conductive finger446. Each of the fourth conductive finger442, the fifth conductive finger444, and the sixth conductive finger446is orthogonally coupled to the second endcap440. Each of the fourth conductive finger442, the fifth conductive finger444, and the sixth conductive finger446is of the second polarity.

The first set of parallel conductive fingers are interdigitated with the second set of parallel conductive fingers at a first interconnect layer to form an array of capacitors420(including a first capacitor420a, a second capacitor420b, a third capacitor420c, a fourth capacitor420d, and a fifth capacitor420e) between the conductive fingers of the first polarity and the conductive fingers of the second polarity. For example, the second capacitor420bof the array of capacitors420is formed between the second conductive finger434, which is a conductive finger of the first polarity and the sixth conductive finger446, which is a conductive finger of the second polarity. The third capacitor420cof the array of capacitors420is formed between the second conductive finger434and the fifth conductive finger444.

The first endcap430is parallel to the second endcap440such that a first gap separates the first set of parallel conductive fingers from the second endcap440and a second gap separates the second set of parallel conductive fingers from the first endcap430. A desirable capacitor structure may be achieved when the distance of the first gap is the same as the second gap in order to achieve a symmetrical structure. For example, a desirable capacitor structure may be achieved when a distance d between the third conductive finger436and the second endcap440is equal to a distance d between the sixth conductive finger446and the first endcap430. When the distance d is not equal during fabrication, the MOM capacitor structure400A is considered misaligned or staggered.

The first set of parallel conductive fingers are interdigitated with the second set of parallel conductive fingers at a first interconnect layer such that a third gap separates each of the first set of parallel conductive fingers from a one or more adjacent second set of parallel conductive fingers. A desirable capacitor structure may be achieved when the distance of the third gap separating the first set of parallel conductive fingers from one or more adjacent second set of parallel conductive fingers is the same. For example, a desirable capacitor structure may be achieved when a distance S (e.g., 50 nanometers (nm)) between the second conductive finger434and each of the fifth conductive finger444and the sixth conductive finger446is the same. When the distance S is not equal during fabrication, the MOM capacitor structure400A is considered misaligned or staggered.

Referring toFIG. 4B, a top view of the MOM capacitor structure400B illustrates misalignment (e.g., horizontal misalignment) in the interconnect layer and corresponding increased capacitor variance due to the misalignment in the interconnect layer during a fabrication process. For illustrative purposes, some of the labelling and numbering of the devices and features ofFIG. 4Bare similar to those ofFIG. 4A.

During a fabrication process, such as a double patterning process, the MOM capacitor structure400B may experience misalignment in the interconnect layer. For example, the process may include fabrication of two sets of parallel conductive fingers by two lithography masks. The misalignment in the interconnect layer may be random and may be a combination of horizontal and vertical misalignments in the interconnect layer. For example, an undesirable capacitor structure may result when a distance S1 (e.g., 60 nm) between the second conductive finger434and the sixth conductive finger446is different from a distance S2 (e.g., 40 nm) between the second conductive finger434and the fifth conductive finger444. This follows because the change in the distance between the plates of the capacitor varies a capacitance c of the MOM capacitor structure400B by delta c (Δc). This misalignment in the interconnect layer is deemed horizontal misalignment.

Referring toFIG. 4C, a top view of the metal-oxide-metal (MOM) capacitor structure400C illustrates misalignment (e.g., vertical misalignment) in the interconnect layer. For illustrative purposes, some of the labelling and numbering of the devices and features ofFIG. 4Care similar to those ofFIG. 4AandFIG. 4B. During a fabrication process, such as a double patterning process, the MOM capacitor structure400C may experience vertical shift that may not result in a variance in the capacitance. The lack of variance in the capacitance follows because the vertical shift causes a distance dl between the third conductive finger436and the second endcap440to be equal to a distance dl between the sixth conductive finger446and the first endcap430. The variation between dl and d is much smaller than the finger length. Therefore, capacitance variation due to vertical misalignment can be ignored. Thus, the capacitance c of the MOM capacitor structure400C is maintained.

Although the terms “vertical” and “horizontal” are used to illustrate the misalignment in the interconnect layer, the misalignment may be represented in other orientations depending on an orientation of the MOM capacitor structure or the orientation of an electronic device or system in which the MOM capacitor structure is implemented.

FIGS. 5A-5Cillustrate top views of metal-oxide-metal (MOM) capacitor structures500(including MOM capacitor structure500A, MOM capacitor structure500B, and MOM capacitor structure500C) with reduced misalignment in the interconnect layer and reduced capacitance variance, according to aspects of the present disclosure. For illustrative purposes, some of the labelling and numbering of the devices and features ofFIGS. 5A-5Care similar to those ofFIGS. 4A-4C.FIGS. 5A-5Care directed to MOM capacitor structures with smaller capacitance variance (relative to those ofFIGS. 4A-4C). The capacitor structures are robust to misalignment during the double patterning process.

Referring toFIG. 5A, the top view of the MOM capacitor structure500A is illustrated. The MOM capacitor structure500A includes a first endcap having a first section530and a second section550that is orthogonally coupled to the first section530. The MOM capacitor structure500A further includes a first set of parallel conductive fingers that include a first conductive finger532, a second conductive finger534, and a third conductive finger536. The first set of parallel conductive fingers is orthogonally coupled to the first section530of the first endcap. For example, the first conductive finger532, the second conductive finger534, and the third conductive finger536are orthogonally coupled to a first surface503of the first section530of the first endcap. The first surface503of the first section530is opposite a second surface505that is a free surface.

The MOM capacitor structure500A further includes a third set of parallel conductive fingers that include a seventh conductive finger552, an eighth conductive finger554, and a ninth conductive finger556. The third set of parallel conductive fingers is orthogonally coupled to the second section550of the first endcap. For example, the seventh conductive finger552, the eighth conductive finger554, and the ninth conductive finger556are orthogonally coupled to a first surface511of the second section550of the first endcap. The first surface511of the second section550is opposite a second surface513that is a free surface. The first section530and the second section550of the first endcap are of the first polarity (e.g., positive).

The MOM capacitor structure500A further includes the second endcap440and a third endcap560. The second set of parallel conductive fingers includes the fourth conductive finger442, the fifth conductive finger444, and the sixth conductive finger446. The second set of parallel conductive fingers is orthogonally coupled to the second endcap440. For example, the fourth conductive finger442, the fifth conductive finger444, and the sixth conductive finger446are orthogonally coupled to a first surface507of the second endcap440. The first surface507of the second endcap440is opposite a second surface509, which is a free surface. The first set of parallel conductive fingers and the second set of parallel conductive fingers are fabricated in a region that is partially surrounded by the first section530of the first endcap, the second section550of the first endcap, and the second endcap440.

A fourth set of parallel conductive fingers includes a tenth conductive finger562, an eleventh conductive finger564, and a twelfth conductive finger566. The fourth set of parallel conductive fingers are orthogonally coupled to the third endcap560. For example, the tenth conductive finger562, the eleventh conductive finger564, and the twelfth conductive finger566are orthogonally coupled to a first surface515of the third endcap560. The first surface515of the third endcap560is opposite a second surface517, which is a free surface.

The first section530of the first endcap is parallel to the second endcap440. Accordingly, the first set of parallel conductive fingers and the second set of parallel conductive fingers are between the first section530of the first endcap and the second endcap440. The second section550of the first endcap is parallel to the third endcap560. Accordingly, the third set of parallel conductive fingers and the fourth set of parallel conductive fingers are between the second section550of the first endcap and the third endcap560.

The first set of parallel conductive fingers are interdigitated with the second set of parallel conductive fingers at a first interconnect layer. The third set of parallel conductive fingers are interdigitated with the fourth set of parallel conductive fingers. The first set of parallel conductive fingers and the third set of parallel conductive fingers are of the first polarity (e.g., positive). The second set of parallel conductive fingers and the fourth set of parallel conductive fingers are of the second polarity (e.g., negative).

In one aspect of the disclosure, a capacitance of the first set of parallel conductive fingers interdigitated with the second set of parallel conductive fingers is the same as a capacitance of the third set of parallel conductive fingers interdigitated with the fourth set of parallel conductive fingers.

The aspects of the present disclosure reduce the capacitance variance by as much as fifty percent (50%) relative to conventional implementations under similar conditions (e.g., under a same probability of variance). For a same amount of variance, the probability that the small amount of variance occurs is much smaller for the improved capacitor relative to the conventional implementations. The MOM capacitor structure can be fabricated with zero additional cost (e.g., for masking) relative to the conventional implementation.

FIGS. 5B and 5Cillustrate that the aspects of the present disclosure reduce the capacitance variance by as much as fifty percent (50%) relative to conventional implementations under similar conditions (e.g., under a same probability of variance), whether the misalignment in the interconnect layer is horizontal or vertical. For illustrative purposes, some of the labelling and numbering of the devices and features ofFIG. 5BandFIG. 5Care similar to those ofFIG. 5A.

Referring toFIG. 5B, a top view of the MOM capacitor structure500B is illustrated.FIG. 5Bis directed to a first type of misalignment in a first direction (e.g., horizontal misalignment). The MOM capacitor structure500B includes a first capacitor portion525and a second capacitor portion535that have a combination of parallel conductive fingers in a first direction (e.g., vertical direction) and a second direction (e.g., horizontal direction). In some aspects of the present disclosure, a capacitance of the first capacitor portion525is equal to a capacitance of the second capacitor portion535. For example, the first conductive finger532, the second conductive finger534, the third conductive finger536, the fourth conductive finger442, the fifth conductive finger444, and the sixth conductive finger446are in the vertical direction. The seventh conductive finger552, the eighth conductive finger554, the ninth conductive finger556, the tenth conductive finger562, the eleventh conductive finger564, and the twelfth conductive finger566are in the horizontal direction.

A misalignment in the horizontal direction during fabrication processing (e.g., the horizontal misalignment) may only affect the first capacitor portion525. For example, the horizontal misalignment occurs when a distance51(e.g., 60 nm) between the second conductive finger534and the sixth conductive finger446is different from a distance S2 (e.g., 40 nm) between the second conductive finger534and the fifth conductive finger444. This follows because the horizontal misalignment between the plates of the MOM capacitor structure500B varies the capacitance of the MOM capacitor structure500B.

The capacitance variance resulting from the horizontal misalignment is only fifty percent of a capacitance variance of a conventional implementation because it may only affect the first capacitor portion525and not the second capacitor portion535. For example, for a specified capacitance c, if the change in capacitance is delta c (Δc) for a conventional implementation, the variance of the conventional implementation is Δc/c. Thus, the variance for the aspects of the present disclosure is half (0.5 Δc/c) the variance of the conventional implementation.

Referring toFIG. 5C, a top view of the MOM capacitor structure500C is illustrated. For illustrative purposes, some of the labelling and numbering of the devices and features ofFIG. 5Care similar to those ofFIG. 5AandFIG. 5B.FIG. 5Cis directed to a second type of misalignment in a second direction (e.g., vertical misalignment).

A misalignment in the vertical direction (e.g., the vertical misalignment) may only affect the second capacitor portion535. For example, the vertical misalignment occurs when a distance S1 (e.g., 60 nm) between the twelfth conductive finger566and the eighth conductive finger554is different from a distance S2 (e.g., 40 nm) between the twelfth conductive finger566and the ninth conductive finger556. This follows because the vertical misalignment between the plates of the MOM capacitor structure500C varies the capacitance of the MOM capacitor structure500C.

The capacitance variance resulting from the vertical misalignment is only fifty percent of a capacitance variance of a conventional implementation because it may only affect the second capacitor portion535and not the first capacitor portion525. For example, for a specified capacitance c, if the change in capacitance is delta c (Δc) for a conventional implementation, the variance of the conventional implementation is Δc/c. Thus, the variance for the new capacitor structure is half (0.5 Δc/c) the variance of the conventional implementation.

For example, consider that a probability of a maximal misalignment in an x-direction (e.g., horizontal misalignment) is P1 (e.g., 10%) and a probability of maximal misalignment in a y-direction is P2, which is also equal to P1. The two occurrences are independent of each other. As noted, the probability for misalignment in the x-direction yields a variance, for the new capacitor structure, of half (0.5 Δc/c) the variance of the conventional implementation. Thus, the capacitance variance decreases by 50% for a same probability. However, for misalignment in both the x and the y directions where the variance is Δc/c, the probability is given by the product of the two probabilities (e.g., P1*P1), which is equal to 1%. This probability of 1% is much smaller than a probability of 11% for conventional MOM capacitors. Thus, for a same amount of variance, the new capacitor structure has a smaller probability for misalignment in both the x and the y directions.

FIG. 6AandFIG. 6Brespectively illustrate top views of first and second conductive interconnect layers of metal-oxide-metal (MOM) capacitor structures with reduced misalignment in each of the first and second conductive interconnect layers and reduced capacitance variance, according to aspects of the present disclosure.

Referring toFIG. 6A, a top view of a MOM capacitor structure600A in a first conductive interconnect layer (Mx) is illustrated. The MOM capacitor structure600A is the same as the MOM capacitor structure500A.

Referring toFIG. 6B, a top view of a MOM capacitor structure600B in a second conductive interconnect layer (Mx−1) is illustrated. For example, the MOM capacitor structure600B includes a first endcap having a first section630and a second section650that is orthogonally coupled to the first section630. The first endcap of the MOM capacitor structure600B and the first endcap of the MOM capacitor structure600A may form a single endcap. In some aspects, the first endcap of the MOM capacitor structure600B may be coupled to the first endcap of the MOM capacitor structure600A by a via. In this aspect, the first endcap of the MOM capacitor structure600B is aligned with the first endcap of the MOM capacitor structure600A.

The MOM capacitor structure600B further includes a first set of parallel conductive fingers, which includes a first conductive finger632, a second conductive finger634, and a third conductive finger636. The first set of parallel conductive fingers of the MOM capacitor structure600B is orthogonally coupled to the first section630of the first endcap of the MOM capacitor structure600B.

The MOM capacitor structure600B further includes a third set of parallel conductive fingers, which includes a seventh conductive finger652, an eighth conductive finger654, and a ninth conductive finger656. The third set of parallel conductive fingers of the MOM capacitor structure600B is orthogonally coupled to the second section650of the first endcap. The first section630and the second section650of the first endcap of the MOM capacitor structure600B are of the first polarity (e.g., positive).

The MOM capacitor structure600B further includes a second endcap640and a third endcap660. The second set of parallel conductive fingers of the MOM capacitor structure600B includes a fourth conductive finger642, a fifth conductive finger644, and a sixth conductive finger646. The second set of parallel conductive fingers of the MOM capacitor structure600B is orthogonally coupled to the second endcap640. A fourth set of parallel conductive fingers of the MOM capacitor structure600B includes a tenth conductive finger662, an eleventh conductive finger664, and a twelfth conductive finger666. The fourth set of parallel conductive fingers of the MOM capacitor structure600B is orthogonally coupled to the third endcap660.

The first section630of the first endcap of the MOM capacitor structure600B is parallel to the second endcap640of the MOM capacitor structure600B. Accordingly, the first set of parallel conductive fingers of the MOM capacitor structure600B and the second set of parallel conductive fingers of the MOM capacitor structure600B are between the first section630of the first endcap and the second endcap640of the MOM capacitor structure600B. The second section650of the first endcap of the MOM capacitor structure600B is parallel to the third endcap660of the MOM capacitor structure600B. Accordingly, the third set of parallel conductive fingers of the MOM capacitor structure600B and the fourth set of parallel conductive fingers of the MOM capacitor structure600B are between the second section650of the first endcap and the third endcap660.

The first set of parallel conductive fingers of the MOM capacitor structure600B is interdigitated with the second set of parallel conductive fingers of the MOM capacitor structure600B at the second conductive interconnect layer Mx−1. The third set of parallel conductive fingers of the MOM capacitor structure600B is interdigitated with the fourth set of parallel conductive fingers of the MOM capacitor structure600B. The first set of parallel conductive fingers and the third set of parallel conductive fingers of the MOM capacitor structure600B are of the first polarity (e.g., positive). The second set of parallel conductive fingers and the fourth set of parallel conductive fingers of the MOM capacitor structure600B are of the second polarity (e.g., negative).

In one aspect of the disclosure, an overall capacitance of the first set of parallel conductive fingers interdigitated with the second set of parallel conductive fingers of the MOM capacitor structure600B is the same as an overall capacitance of the third set of parallel conductive fingers interdigitated with the fourth set of parallel conductive fingers of the MOM capacitor structure600B.

The conductive fingers of the first polarity of the MOM capacitor structure600B have an inter-layer alignment relationship with respect to the conductive fingers of the first polarity of the MOM capacitor structure600A. Similarly, the conductive fingers of the second polarity of the MOM capacitor structure600B have an inter-layer alignment relationship with respect to the conductive fingers of the second polarity of the MOM capacitor structure600A. Moreover, endcaps of the first polarity and the endcaps of the second polarity of the of the MOM capacitor structure600B, respectively, have an inter-layer alignment relationship with respect to the endcaps of the first polarity and the endcaps of the second polarity of the MOM capacitor structure600A. Thus, an inter-layer alignment exists between the conductive fingers of the first polarity of the first conductive interconnect layer Mx and the conductive fingers of the first polarity of the second conductive interconnect layer Mx−1. Similarly, an inter-layer alignment exists between the conductive fingers of the second polarity of the first conductive interconnect layer Mx and the conductive fingers of the second polarity of the second conductive interconnect layer Mx−1.

For example, the first endcap of the MOM capacitor structure600B in the second conductive interconnect layer Mx−1 has an inter-layer alignment relationship with respect to the first endcap of the MOM capacitor structure600A in the first conductive interconnect layer Mx. The first conductive finger532, the second conductive finger534, and the third conductive finger536of the MOM capacitor structure600A, respectively, have an inter-layer alignment relationship with respect to the first conductive finger632, the second conductive finger634, and the third conductive finger636of the MOM capacitor structure600B.

The fourth conductive finger442, the fifth conductive finger444, and the sixth conductive finger446of the MOM capacitor structure600A, respectively, have an inter-layer alignment relationship with respect to the fourth conductive finger642, the fifth conductive finger644, and the sixth conductive finger646of the MOM capacitor structure600B. The seventh conductive finger552, the eighth conductive finger554, and the ninth conductive finger556of the MOM capacitor structure600A, respectively, have an inter-layer alignment relationship with respect to the seventh conductive finger652, the eighth conductive finger654, and the ninth conductive finger656of the MOM capacitor structure600B. The tenth conductive finger562, the eleventh conductive finger564, and the twelfth conductive finger566of the MOM capacitor structure600A, respectively, have an inter-layer alignment relationship with respect to the tenth conductive finger662, the eleventh conductive finger664, and the twelfth conductive finger666of the MOM capacitor structure600B.

FIG. 6Cillustrates a cross-section600C of a portion of the multiple conductive interconnect layers of metal-oxide-metal (MOM) capacitor structures with reduced misalignment in one or more of the interconnect layers, according to aspects of the present disclosure. For illustrative purposes, some of the labelling and numbering of the devices and features ofFIG. 6Care similar to those ofFIGS. 6A and 6B.

For example,FIG. 6Cillustrates an inter-layer alignment configuration between the MOM capacitor structure600A in the first conductive interconnect layer Mx, the MOM capacitor structure600B in the second conductive interconnect layer Mx−1 and a subsequent MOM capacitor structure in a subsequent conductive interconnect layer (e.g., third conductive interconnect layer Mx−2). The cross-section600C corresponds to a cross-section along a first cross-sectional line670. The cross-section600C illustrates portions of the conductive interconnect layers (e.g., the first conductive interconnect layer Mx, the second conductive interconnect layer Mx−1, and a third conductive interconnect layer Mx−2).

The first conductive interconnect layer Mx of the cross-section600C includes conductive fingers of the first polarity (e.g., the seventh conductive finger552and the eighth conductive finger554of the MOM capacitor structure600A). The first conductive interconnect layer Mx of the cross-section600C also includes conductive fingers of the second polarity (e.g., the tenth conductive finger562and the eleventh conductive finger564of the MOM capacitor structure600A).

Similarly, the second conductive interconnect layer Mx−1 of the cross-section600C includes conductive fingers of the first polarity (e.g., the seventh conductive finger652and the eighth conductive finger654of the MOM capacitor structure600B). The second conductive interconnect layer Mx−1 of the cross-section600C also includes conductive fingers of the second polarity (e.g., the tenth conductive finger662and the eleventh conductive finger664of the MOM capacitor structure600B).

The third conductive interconnect layer Mx−2 of the cross-section600C includes conductive fingers of the first polarity (e.g., a seventh conductive finger672and an eighth conductive finger674of a subsequent MOM capacitor structure (not shown in top view)). The third conductive interconnect layer Mx−2 of the cross-section600C also includes conductive fingers of the second polarity (e.g., a tenth conductive finger682and an eleventh conductive finger684of the subsequent MOM capacitor structure (not shown in top view)).

In this aspect, the conductive fingers of the first polarity of the first conductive interconnect layer Mx, the second conductive interconnect layer Mx−1, and the third conductive interconnect layer Mx−2 have an inter-layer alignment relationship with respect to each other. For example, the seventh conductive finger552of the MOM capacitor structure600A, overlaps (e.g., is directly over) the seventh conductive finger652of the MOM capacitor structure600B, which overlaps (e.g., is directly over) the seventh conductive finger672of the MOM capacitor structure in the next layer (not shown in top view). Similarly, the tenth conductive finger562of the MOM capacitor structure600A overlaps the tenth conductive finger662of the MOM capacitor structure600B, which overlaps the tenth conductive finger682of the MOM capacitor structure in the next layer (not shown in top view).

FIG. 6DandFIG. 6Erespectively illustrate top views of first and second conductive interconnect layers of metal-oxide-metal (MOM) capacitor structures with reduced misalignment in each of the first and second conductive interconnect layers, according to aspects of the present disclosure.

Referring toFIG. 6D, a top view of a MOM capacitor structure600D in a first conductive interconnect layer (Mx) is illustrated. The MOM capacitor structure600D is the same as the MOM capacitor structure600A.

Referring toFIG. 6E, a top view of a MOM capacitor structure600E in a second conductive interconnect layer (Mx−1) is illustrated. The MOM capacitor structure600E is similar to the MOM capacitor structure600B. However, the tenth conductive finger662, the eleventh conductive finger664, and the twelfth conductive finger666of the MOM capacitor structure600E are staggered/offset relative to those of the MOM capacitor structure600D in order to cause interlayer misalignment between the MOM capacitor structure600D and the MOM capacitor structure600E.

For example, the conductive fingers of the first polarity that are orthogonally coupled to the second section550of the first endcap of the MOM capacitor structure600D have an inter-layer misalignment relationship with respect to the conductive fingers of the first polarity orthogonally coupled to the second section650of the first endcap of the MOM capacitor structure600E. This inter-layer misalignment relationship is illustrated inFIG. 6F.

FIG. 6Fillustrates a cross-section600F of a portion of the multiple conductive interconnect layers of metal-oxide-metal (MOM) capacitor structures with reduced misalignment in one or more of the interconnect layers, according to aspects of the present disclosure. For illustrative purposes, some of the labelling and numbering of the devices and features ofFIG. 6Fare similar to those ofFIGS. 6A, 6B and 6C.

FIG. 6Fillustrates an inter-layer misalignment configuration between the MOM capacitor structure600D in the first conductive interconnect layer Mx, the MOM capacitor structure600E in the second conductive interconnect layer Mx−1 and MOM capacitor structure in a subsequent conductive interconnect layer (e.g., a third conductive interconnect layer Mx−2) not shown in top view. The cross-section600F corresponds to a cross-section along a second cross-sectional line680. The cross-section600F illustrates portions of the conductive interconnect layers (e.g., the first conductive interconnect layer Mx, the second conductive interconnect layer Mx−1, and the third conductive interconnect layer Mx−2).

The first conductive interconnect layer Mx of the cross-section600F includes conductive fingers of the first polarity (e.g., the seventh conductive finger552and the eighth conductive finger554of the MOM capacitor structure600D). The first conductive interconnect layer Mx of the cross-section600F also includes conductive fingers of the second polarity (e.g., the tenth conductive finger562and the eleventh conductive finger564of the MOM capacitor structure600D).

Similarly, the second conductive interconnect layer Mx−1 of the cross-section600F includes conductive fingers of the first polarity (e.g., the seventh conductive finger652and the eighth conductive finger654of the MOM capacitor structure600E). The second conductive interconnect layer Mx−1 of the cross-section600F also includes conductive fingers of the second polarity (e.g., the tenth conductive finger662and the eleventh conductive finger664of the MOM capacitor structure600E).

The third conductive interconnect layer Mx−2 of the cross-section600F includes conductive fingers of the first polarity (e.g., the seventh conductive finger672and the eighth conductive finger674of the MOM capacitor structure of a next layer (not shown in top view)). The third conductive interconnect layer Mx−2 of the cross-section600F also includes conductive fingers of the second polarity (e.g., the tenth conductive finger682and the eleventh conductive finger684of the MOM capacitor structure of the next layer (not shown in top view)).

In this aspect, the conductive fingers of the first polarity of the first conductive interconnect layer Mx, the second conductive interconnect layer Mx−1, and the third conductive interconnect layer Mx−2 have an inter-layer misalignment relationship with respect to each other. For example, the seventh conductive finger552of the MOM capacitor structure600D, overlaps (e.g., is directly over) the tenth conductive finger662of the MOM capacitor structure600E, which overlaps (e.g., is directly over) the seventh conductive finger672of the subsequent layer (not shown in top view). Similarly, the tenth conductive finger562of the MOM capacitor structure600D overlaps the seventh conductive finger652of the MOM capacitor structure600E, which overlaps the tenth conductive finger682of the subsequent layer (not shown in top view). Thus, in this aspect, the conductive fingers of the first polarity are alternately aligned with the conductive fingers of the second polarity.

FIG. 7illustrates a top view of a metal-oxide-metal (MOM) capacitor structure700with reduced misalignment, according to additional aspects of the present disclosure. For illustrative purposes, some of the labelling and numbering of the devices and features ofFIG. 7are similar to those ofFIGS. 5A-5CandFIGS. 6A-6F. However, instead of the second surface505of the first section530of the first endcap being a free surface, as inFIG. 5A(for example), a fifth set of (e.g., positive) conductive fingers are orthogonally coupled to the second surface505of the first section530. For example, each of the fifth set of conductive fingers (e.g., a thirteenth conductive finger742, a fourteenth conductive finger744, and a fifteenth conductive finger746) is orthogonally coupled to the second surface505of the first section530of the MOM capacitor structure700.

The MOM capacitor structure700includes a fourth endcap having a first section730and a second section750that is orthogonally coupled to the first section730. The MOM capacitor structure700further includes a sixth set of parallel conductive fingers (e.g., of the second polarity), which include a sixteenth conductive finger732, a seventeenth conductive finger734, and an eighteenth conductive finger736. The sixth set of parallel conductive fingers is orthogonally coupled to the first section730of the fourth endcap. For example, the sixteenth conductive finger732, the seventeenth conductive finger734, and the eighteenth conductive finger736are orthogonally coupled to a first surface703of the first section730of the fourth endcap. The first surface703of the first section730is opposite a second surface705, which is a free surface.

The MOM capacitor structure700further includes a seventh set of parallel conductive fingers, which include a nineteenth conductive finger752, a twentieth conductive finger754, and a twenty-first conductive finger756. The seventh set of parallel conductive fingers is orthogonally coupled to the second section750of the fourth endcap. For example, the nineteenth conductive finger752, the twentieth conductive finger754, and the twenty-first conductive finger756are orthogonally coupled to a first surface711of the second section750of the fourth endcap. The first surface711of the second section750is opposite a second surface713, which is a free surface. The first section730and the second section750of the fourth endcap are of the second polarity.

The MOM capacitor structure700further includes a fifth endcap760. An eighth set of parallel conductive fingers include a twenty-second conductive finger762, a twenty-third conductive finger764, and a twenty-fourth conductive finger766. The eighth set of parallel conductive fingers is orthogonally coupled to the fifth endcap760. For example, the twenty-second conductive finger762, the twenty-third conductive finger764, and the twenty-fourth conductive finger766are orthogonally coupled to a first surface715of the fifth endcap760. The first surface715of the fifth endcap760is opposite a second surface717, which is a free surface.

The first section730of the fourth endcap is parallel to the first section530of the first endcap. The second section750of the fourth endcap is parallel to the fifth endcap760.

FIG. 8is a process flow diagram illustrating a method800for fabricating a metal-oxide-metal (MOM) capacitor with reduced misalignment and reduced capacitance variance, according to aspects of the present disclosure. In block802, a first endcap having a first section and a second section that is orthogonal to the first section is fabricated with a first mask. In block804, a first set of conductive fingers orthogonally coupled to the first section of the first endcap is fabricated with the first mask. In block806, a third set of conductive fingers orthogonally coupled to the second section of the first endcap is fabricated with the first mask. In block808, a second endcap parallel to the first section of the first endcap is fabricated with a second mask.

In block810, a second set of conductive fingers orthogonally coupled to the second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer is fabricated with the second mask. In block812, a third endcap parallel to the second section of the first endcap is fabricated with the second mask. In block814, a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer is fabricated with the second mask.

According to a further aspect of the present disclosure, a capacitor includes first means for receiving/transmitting charge to/from the capacitor and second means for receiving/transmitting charge to/from the capacitor. In one configuration, the first charge receiving/transmitting means may be the second endcap440, as shown inFIGS. 4, 6A, 6D and 7. In one configuration, the second charge receiving/transmitting means may be the third endcap560, as shown inFIGS. 6A, 6D and 7. In another aspect, the aforementioned means may be any structure or any material configured to perform the functions recited by the aforementioned means.

FIG. 9is a block diagram showing an exemplary wireless communication system900in which an aspect of the present disclosure may be advantageously employed. For purposes of illustration,FIG. 9shows three remote units920,930, and950and two base stations940. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units920,930, and950include IC devices925A,925C, and925B that include the disclosed capacitor. It will be recognized that other devices may also include the disclosed capacitor, such as the base stations, switching devices, and network equipment.FIG. 9shows forward link signals980from the base station940to the remote units920,930, and950and reverse link signals990from the remote units920,930, and950to base stations940.

InFIG. 9, remote unit920is shown as a mobile telephone, remote unit930is shown as a portable computer, and remote unit950is shown as a fixed location remote unit in a wireless local loop system. For example, the remote units may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit, such as a personal data assistant, a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit, such as a meter reading equipment, or other device that stores or retrieves data or computer instructions, or combinations thereof. AlthoughFIG. 9illustrates remote units, according to the aspects of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Aspects of the present disclosure may be suitably employed in many devices, which include the disclosed capacitor.

FIG. 10is a block diagram illustrating a design workstation used for circuit, layout, and logic design of a semiconductor component, such as the capacitors disclosed above. A design workstation1000includes a hard disk1001containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation1000also includes a display1002to facilitate design of a circuit1010or an RF component1012such as a capacitor. A storage medium1004is provided for tangibly storing the design of the circuit1010or the RF component1012(e.g., the capacitor). The design of the circuit1010or the RF component1012may be stored on the storage medium1004in a file format such as GDSII or GERBER. The storage medium1004may be a CD-ROM, DVD, hard disk, flash memory, or other appropriate device. Furthermore, the design workstation1000includes a drive apparatus1003for accepting input from or writing output to the storage medium1004.

Data recorded on the storage medium1004may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium1004facilitates the design of the circuit1010or the RF component1012by decreasing the number of processes for designing semiconductor wafers.

The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

The previous description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.