LDMOS device with short channel and associated fabrication method

A method of fabricating an LDMOS device includes: forming a gate of the LDMOS device on a semiconductor substrate; performing tilt body implantation by implanting dopants of a first conductivity type in the semiconductor substrate using a mask, wherein the tilt body implantation is implanted at an angle from a vertical direction; performing zero tilt body implantation by implanting dopants of the first conductivity type using the same mask, wherein the zero tilt body implantation is implanted with zero tilt from the vertical direction, and wherein the tilt body implantation and the zero tilt body implantation are configured to form a body region of the LDMOS device; and forming a source region and a drain contact region of the LDMOS device, wherein the source region and the drain contact region are of a second conductivity type.

TECHNICAL FIELD

The present invention generally relates to semiconductor device, more particularly and not exclusively relates to LDMOS device and associated fabrication method.

BACKGROUND

Lateral Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOS) devices are widely used for high breakdown voltage and good thermal performance when compared to other types of transistor devices. An LDMOS device comprises a drain11, a source12, a gate13and a body14as shown inFIG. 1. When turned “ON”, a voltage is applied on the gate13, a channel region15below the gate13converts from p-type into n-type, and a current path forms between the drain11and the source12.

High breakdown voltage and low on-resistance are two important parameters desired by an LDMOS device. In order to have a lower on-resistance and smaller cell pitch, short channel is preferred. However, in prior art short channel approaches, short channel may lead to lower punch-through breakdown voltage which is one critical parameter for an LDMOS device.

In order to achieve higher punch-through breakdown voltage, one solution is to have a shallower source junction. But this might cause leakage if silicide formation in the later process consumes too much source region. Another solution is to rely on the body formation of the normal lateral Double Diffused MOSFET (DDMOS). But this requires high thermal budget which would affect the other junction profiles. For example, in Bipolar-CMOS-DMOS (BCD) semiconductor process, the high thermal budget in forming the body region of a conventional DDMOS device would affect the CMOS devices and bipolar transistors. It would also require a large cell pitch.

Accordingly, an LDMOS device is required to address some or all of the above deficiencies.

SUMMARY

In one embodiment, a method of fabricating an LDMOS device comprises: forming a gate of the LDMOS device on a semiconductor substrate; performing tilt body implantation by implanting dopants of a first conductivity type in the semiconductor substrate using a mask, wherein the tilt body implantation is implanted at an angle from a vertical direction; performing zero tilt body implantation by implanting dopants of the first conductivity type using the same mask, wherein the zero tilt body implantation is implanted with zero tilt from the vertical direction, and wherein the tilt body implantation and the zero tilt body implantation are configured to form a body region of the LDMOS device; and forming a source region and a drain contact region of the LDMOS device, wherein the source region and the drain contact region are of a second conductivity type.

In another embodiment, a method of fabricating an LDMOS device comprises: forming a gate of the LDMOS device on a semiconductor substrate; implanting dopants of a first conductivity type into a body region of the LDMOS device vertically; performing a rapid thermal annealing process and forming a short channel of the LDMOS device; and forming a source region and a drain contact region of the LDMOS device, wherein the source region and the drain contact region are of a second conductivity type.

In yet another embodiment, an LDMOS device comprises: a gate; a drain region of a first conductivity type; a body region of a second conductivity type different from the first conductivity type; and a source region of the first conductivity type and formed in the body region; wherein the drain region is at one side of the gate and the source region is at the other side of the gate, and wherein the peak concentration of the second conductivity type is beneath the source region.

DETAILED DESCRIPTION

LDMOS devices according to some embodiments of the present invention are formed adopting zero-tilt body implantation and without conventional high-thermal-budget lateral body diffusion. Accordingly these LDMOS devices have short channel or small cell pitch, and also have relatively high punch-through voltage.

FIG. 2illustrates a sectional view of an LDMOS device200according to an embodiment of the present invention. LDMOS device200comprises an N-type drain region21, an N-type source region22, a gate region23, and a P-type body region24. In detail, the gate23comprises a dielectric layer231, an electrical conducting layer232formed on the dielectric layer231, and a gate seal oxide233formed on the electrical conducting layer232and on the side surface of the gate23. The P-type body region24is adjacent to the drain region21. The LDMOS device200further comprises a P+ body contact region241contacting the body region24. The drain region21comprises a lowly doped N− drift region211and a highly doped N+ drain contact region212. The highly doped N+ source region22is formed in the body region24. In the sectional view as shown inFIG. 2, the drain region21is at one side of the gate region23while the source region22is at the other side of the gate region23.

Continuing withFIG. 2, the body region24is at least partly formed by zero tilt implantation and is formed without conventional lateral diffusion which has high thermal budget. Accordingly, unlike the conventional lateral diffusion which has the peak concentration of P-type substances at the surface201of the semiconductor substrate required for lateral diffusion, the peak concentration of P-type substances of the body region according to the embodiment of the present invention is at the region beneath the N+ source region22.

FIG. 3illustrates a diagram of several doping concentration curves A1, A2and A3along a line AB traversing the source region22and body region24in vertical direction with reference toFIG. 2, according to an embodiment of the present invention. The curve A1in bold represents the doping concentration of P-type substances along line AB according to an embodiment of the present invention which adopts a zero tilt body implantation and without conventional lateral body diffusion. The curve A2in dotted line represents the doping concentration of P-type substances in the body region24along line AB, according to a conventional lateral diffused body region. And the curve A3in thin line represents the doping concentration of N-type substances of the N+ source region22along line AB. It can be seen that in the conventional lateral diffused P-type body approach with reference to curve A2, the peak concentration of P-type substances is at point A, which is at the surface201of the semiconductor substrate. Whereas according to the embodiment of the present invention, when formed with zero tilt body implantation and without conventional lateral body diffusion, the peak concentration is at point C which is below the N+ source region22, with reference to curve A1. This peak concentration distribution according to the embodiment of the present invention has advantages of lower body resistance to make LDMOS device robustness stronger without causing low punch-through breakdown voltage.

FIG. 4illustrates a method400of fabricating an LDMOS device according to an embodiment of the present invention. The method400comprises at a first step401forming a gate of the LDMOS device on a semiconductor substrate. In one embodiment, forming the gate comprises forming a dielectric layer on the semiconductor substrate and then forming an electrical conducting layer on the dielectric layer. The method400further comprises in a second step402performing tilt body implantation by implanting P-type dopants into a body region of the LDMOS device in the semiconductor substrate with shallow depth and tilt angle using a mask. This tilt body implantation aims to form a channel region of the LDMOS device and to increase the punch-through voltage of the LDMOS device. After the tilt body implantation, the method400further comprises in step403performing zero tilt body implantation by implanting P-type dopants into the same body region with a deeper junction using the same mask. And the zero tilt body implantation is performed with a zero tilt. The zero tilt body implantation in step403has a depth deeper than the tilt body implantation taken out in step402and is partly overlapped with the tilt body implantation region. The zero tilt body implantation adds on a deeper junction to improve Safe Operating Area (SOA) of the LDMOS device. In the meantime, the zero tilt body implantation shares a same mask with the tilt body implantation and is cost effective. The tilt body implantation and the zero tilt body implantation are configured to form a body region of the LDMOS device. A more detailed process flow embodiment will be described with reference toFIGS. 5A-5I.

FIGS. 5A-5Iillustrate a process flow of fabricating an LDMOS device according to an embodiment of the present invention.

InFIG. 5A, a semiconductor substrate51is provided. The semiconductor substrate51comprises an original substrate511, an N-type Buried Layer (NBL)512and an epitaxial layer513. The original substrate511may be N type, P type or intrinsic semiconductor material. The NBL512may be replaced with other structures. The epitaxial layer513may be N type, P type or intrinsic semiconductor material and has a top surface52. The semiconductor substrate51may have other circuit(s)/device(s)/system(s) integrated in it. In some embodiments, the semiconductor substrate may have other configuration or without some of the above regions.

InFIG. 5B, N-type dopants are implanted into the semiconductor substrate51from the top surface52to form an N-type well53. The N-type well53is lightly doped and has a lower doping concentration than that in a source region or a drain contact region of the LDMOS device. In the shown embodiment, the doping depth is controlled that the N-type well53contacts with the NBL512.

InFIG. 5C, a gate region24is formed on the surface52. Forming the gate23comprises forming a dielectric layer541on the surface52of the semiconductor substrate51, and then forming an electrical conducting layer542on the dielectric layer541. In one embodiment, the dielectric layer541comprises silicon dioxide (SiO2), and the conducting layer542comprises polycrystalline silicon. In one embodiment, after forming the silicon dioxide layer and polycrystalline silicon layer, forming the gate23may further comprise patterning the gate by etching via a mask.

InFIG. 5D, gate seal oxide55is formed at the sidewall551and top surface552of the gate23. However, in another embodiment, the gate seal oxide may be not necessary or replaced by other structures.

InFIG. 5E, a mask560is adopted and P-type dopants are implanted into an opening of the mask560from a first direction at an angle θ from the vertical direction C to form a part of the body region. A direction may contain information in a three dimensional coordinates. With this tilt body implantation, P-type dopants are implanted under the gate23to form the channel at one side.

InFIG. 5F, the direction of tilt body implantation is adjusted, and P-type dopants are implanted in the same opening of the mask560from a second direction at the angle θ from the vertical direction C, to form the channel of the LDMOS device at another side.

In one embodiment, tilt body implantation may be further performed from a third direction and from a fourth direction both at the angle θ from the vertical direction C. In one embodiment, the first direction, the second direction, the third direction and the fourth direction each is separated form the next direction by 90 degrees rotated from the vertical axis C. Or in other words, when the first direction, the second direction, the third direction and the fourth direction each has a projected direction angle in a horizontal plane with a first projected direction angle, a second projected direction angle, a third projected direction angle and a fourth projected direction angle respectively, the first projected direction angle, the second projected direction angle, the third projected direction angle and the fourth projected direction angle in the horizontal plane each is separated from the next by 90 degrees, wherein the horizontal plane is a plane perpendicular to the vertical axis C. Accordingly, the LDMOS transistors can be oriented in any of the four directions.

InFIG. 5G, zero tilt body implantation is performed and P-type dopants are implanted vertically with zero tilt from the vertical direction into the same opening of the mask560. The zero tilt body implantation has a deeper junction than the tilt body implantation. And the body region is formed by the combination of the tilt body implantation and the zero tilt body implantation. Since no lateral body diffusion is required, the doping concentration of the P-type dopants may be controlled beneath the source region of the LDMOS device.

InFIG. 5H, N-type dopants are implanted with high doping concentration to form the N+ source region22at one side of the gate23and the N+ drain contact region212at the other side of the gate23.

And inFIG. 5I, P type substances of high doping concentration are implanted in the body region24between the source regions22to form a P+ body contact region56. In one embodiment, P+ body contact region56is shorted to the N+ source region22by forming an electrical conducting layer on them.

Some other prior art steps such as forming contacts, interconnection, and packaging, are not shown for ease of illustration. However, embodiments with these prior art steps are also within the spirit and scope of the invention as defined by the appended claims.

FIG. 6illustrates a method600of fabricating an LDMOS device according to another embodiment of the present invention. The method600comprises at a first step601forming a gate of the LDMOS device on a semiconductor substrate. In one embodiment, forming the gate comprises forming a dielectric layer on the semiconductor substrate and then forming an electrical conducting layer on the dielectric layer. The method600further comprises in a second step602implanting P-type dopants into a body region of the semiconductor substrate vertically with zero tilt. In step603, a Rapid Thermal Annealing (RTA) process is performed. The RTA process aims to form lightly doped drain (LDD) region(s) or lightly doped source region(s) as well as to form the short channel region of the LDMOS device. The RTA process has lower thermal budget than the conventional annealing process for forming the laterally diffused body region, and thus has less affect to other junctions and also is suitable for forming a short channel of an LDMOS device. And in step604, source region and drain contact region are formed. A more detailed process flow embodiment will be described with reference toFIGS. 7A-7I.

FIGS. 7A-7Iillustrate a process flow of fabricating an LDMOS device according to an embodiment of the present invention.

The processes inFIGS. 7A-7Dare similar to those inFIGS. 5A-5D. For ease of illustration, the description toFIGS. 7A-7Dwill not be described in detail and may refer to the descriptions with reference toFIGS. 5A-5D.

InFIG. 7E, a mask750is adopted and P-type dopants are implanted into an opening of the mask750with zero tilt angle from the vertical direction to form a body region of the LDMOS device. In the shown embodiment, the P-type region75is implanted self-aligned to the gate region23. It would be apparent to persons of ordinary skill in the art that the final shape of the body region of a LDMOS device will be affected and adjusted by the later processes which affect the junction depth of different regions.

InFIG. 7F, an LDD region76is formed by implanting lightly doped N-type substances. And in another embodiment, a P-type LDD region may be formed by implanting P-type lightly doped substances. In the shown embodiment, an N-type LDD region76is formed in the P-type body region75with a shallower junction than that of the body region75. The N-type LDD region76may be formed substantially self-aligned to the gate region23and sharing the same mask750with the body region75and accordingly no additional mask is required. In another embodiment, a LDD region is formed in other area(s) of the semiconductor substrate. However, in yet another embodiment, an LDD region may be not required.

And then inFIG. 7G, RTA process is taken out to activate the implanted N-type LDD region76. In the meantime, the P-type body region75diffuses laterally under the gate23to form a short channel77. The P-type dopants of boron is more diffusive than the N-type dopants of phosphorus, thus when the phosphorus atoms are implanted with the same mask for implanting the boron atoms of the body region, after RTA process, the boron diffuses farther than the phosphorus to form the short channel77.

InFIG. 7H, N-type dopants with high doping concentration are implanted to form the N+ source region78and the N+ drain contact region212.

And inFIG. 7I, P-type dopants with high doping concentration are implanted between the source regions78and contacting the body region75to form the P+ body contact region79. In one embodiment, the P+ body contact region79is electrically shorted to the N+ source region78by forming an electrical conducting layer on them.

The process flow steps as illustrated above are not meant to confine the processing sequences, and the processing sequences may differ from those referred in the appended drawings.

It should be known that the conductivity type for each region may be in an alternating type, for example, the N type regions may be replaced with P type regions while the P type regions are replaced with N type regions. In one embodiment as claimed in the appended claims, the first conductivity type may be N type and the second conductivity type is P type. And in another embodiment, the first conductivity type is P type and the second conductivity type is N type.

The N type substance can be selected from one of the following: nitrogen, phosphorus, arsenic, antimony, bismuth and the combination thereof. And the P type substance can be selected from one of the following: boron, aluminum, gallium, indium, thallium and the combination thereof.