SYSTEM ON CHIP

A system on chip is provided. The system on chip includes a bus including a data channel through which data is transmitted in at least one direction and a master interface configured to receive first data from the data channel, perform a bit operation on the first data and on second data input before input of the first data, determine an encoding operation for the first data based on a result of the bit operation, perform the encoding operation on the first data, to obtain encoded data, and provide the encoded data and a transformation signal indicating the encoding operation to the data channel.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0112251, filed in the Korean Intellectual Property Office on Aug. 25, 2023, the entire contents of which are incorporated herein by reference.

BACKGROUND

A system on chip (SoC) is a form of functional block with various existing functions, for example, intellectual property (IP) blocks, intensively implemented on one chip thanks to the development of semiconductor process technology. As electronic devices are becoming lighter, simpler, and more functional, research on enhancing SoC integration and operational speed is also in progress. As SoC integration and operation speed increase, power consumption is an area of ongoing development. When power consumption is high, a temperature of the chip increases, which may lead to not only inoperability but also damage to a package, and thus the importance of low-power design in integrated SoCs is increasing. As one of the low-power design methods in SoC, clock gating technology is applied to a bus interface. By applying the clock gating, power consumption may be improved by reducing operations of devices within the bus interface.

SUMMARY

The present disclosure relates to systems on chips. In general, in some aspects, the present disclosure embodies a system on chip that improves the efficiency of clock gating by reflecting the data pattern characteristics before and after data is processed.

In general, in some other aspects, the present disclosure embodies a system on chip that improves the power consumption efficiency of all flip-flops in a data channel.

In general, in some aspects, the present disclosure relates to a system on chip that includes: a bus including a data channel through which data is transmitted in at least one direction and a master interface configured to receive first data from the data channel, perform a bit operation on the first data and on second data input before input of the first data, determine an encoding operation for the first data based on a result of the bit operation, perform the encoding operation on the first data, to obtain encoded data, and provide the encoded data and a transformation signal indicating the encoding operation to the data channel may be provided.

Some aspects of this disclosure describe system on chip that includes: a bus including a data channel through which data is transmitted in at least one direction and a slave interface configured to receive, from the data channel, encoded data and a transformation signal indicating an encoding operation performed to obtain the encoded data, and performs a maintenance operation, an invert operation, or a circular shift operation on the encoded data based on at least a part of the encoded data and based on the transformation signal may be provided.

Some aspects of this disclosure describe a system on chip that includes: a master interface configured to perform a bit operation on first data and second data input before input of the first data, perform an encoding operation on the first data based on a result of the bit operation, to obtain encoded data, and output the encoded data and a transformation signal indicating the encoding operation, a bus including a data flipflop configured to latch the encoded data based on a clock signal, a clock gating circuit configured to clock-gate the clock signal, and a data channel configured to transmit the encoded data in at least one direction through the data flipflop and a slave interface configured to receive the encoded data and the transformation signal from the bus, and performs a decoding operation on the encoded data based on at least a part of the encoded data and based on the transformation signal may be provided.

DETAILED DESCRIPTION

Hereinafter, with reference to accompanying drawings, various examples of the present disclosure will be described in detail and thus a person of an ordinary skill can easily practice them in the technical field to which the present disclosure belongs. The present disclosure may be implemented in many different forms and is not limited to the examples described herein.

In order to clearly describe the disclosure with reference to the drawings, parts not related to the description are omitted, and similar reference numerals are designated to similar parts throughout the specification.

In addition, the size and thickness of each component shown in the drawing are arbitrarily represented for the convenience of description, and thus the present disclosure is not necessarily limited to the drawings. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. In addition, in the drawing, for convenience of description, the thickness of some layers and regions are exaggerated.

FIG.1is a block diagram that illustrates a configuration of a system on chip (SoC) according to some implementations.

Referring toFIG.1, an SoC1ais an electronic system integrated into a single chip and may perform various functions by encompassing a plurality of functional blocks with various functions.

The SoC1amay include a processor10P, a memory10Mem, a plurality of IP devices10ato10c(sometimes referred to as IP blocks), and a bus BUS.

The processor10P may include at least one of a microprocessor, a digital signal processor, and logic elements that perform functions similar to functions performed by the microprocessor and the digital signal processor.

The memory10Mem may be a storage device that stores data and/or instructions, and/or the like. Although not clearly shown, the memory10Mem is an operating memory for the operation of the processor10P and may include high-speed DRAM and/or SRAM, and/or the like depending on the implementation.

The plurality of IP devices10ato10cmay be circuit blocks performing specific functions in the SoC1a. In some implementations, the plurality of IP devices10ato10cmay include a special function register. The processor10P may process data using the special function register.

The processor10P, the memory10Mem, and the plurality of IP devices10ato10cmay be connected to each other through the bus BUS. In some implementations, the bus BUS may be an advanced microcontroller bus architecture (AMBA), and the AMBA may be a standard bus specification for connection and management of the plurality of IP devices10ato10cin SoC1a. In some implementations, the bus BUS may be a one-chip communication bus for the design of an embedded microprocessor.

As bus types for the AMBA, an advanced high-performance bus (AHB), an advanced peripheral bus (APB), and an advanced extensible interface (AXI) can be used. Among these, the AXI is an interface protocol between IP devices and may provide multiple outstanding address functions, multiple outstanding transaction functions, and data interleaving functions.

Here, the multiple outstanding address function is a function that allows utilization of empty transmission time occurring between addresses by transmitting the address for each data only once through the address line while simultaneously transmitting each data and transmitting when information is provided through the address line and data line of the bus. In particular, it may be used when providing data in burst mode. In addition, the multiple outstanding transaction function is an in-parallel transaction processing function that makes it possible to transmit a plurality of transactions to a slave device. Accordingly, one of the plurality of transactions can be selected and processed preferentially by the slave device, and read and write operations can be simultaneously executed through the AXI.

The data interleaving function is a function that allows data to be mixed at a slave level when multiple master devices transmit data to one slave. Accordingly, bandwidth use becomes more efficient and latency can be reduced.

FIG.2is provided for description of the bus and the interface of the SoC according to some implementations.

Each of the master device10mand slave device10smay be one of the processor10P, the memory10Mem, and the plurality of IP devices10ato10cin the SoC1aofFIG.1. The master device10mis a device that plays a leading role in using the bus BUS, and the master device10mmay use the bus BUS. In some implementations, the master device10mmay be the processor10P ofFIG.1, but implementations are not limited thereto, and a other devices within the SoC1aofFIG.1may be transferred to/assigned as the master device10mand use the bus BUS.

The slave device10smay play an opposite role to the master device10mand may perform functions in response to a control signal Ctrl led by the master device10m. Accordingly, the slave device10sdetermines whether the master device10mtransmits the control signal Ctrl with respect to the corresponding slave device10sthrough an address ADDR, and may need to be prepared to take an action in response.

The master device10mand the slave device10smay be connected with the bus BUS through interfaces MI and SI. The master device10mmay include a master interface MI and the slave device10smay include a slave interface SI. In cases in which the slave device10soperates as a master, the slave interface SI may become the master interface MI. That is, the master device may change into a slave device, and the slave device may change into a master device depending on an operating situation.

The master device10maccording to some implementations may provide write data WD, a transformation signal Ts, and an address ADDR/control signal Ctrl to the slave device10sthrough the bus BUS, and the slave device10smay provide a write response WR to the master device10m. Although it is not illustrated, the slave device10smay provide read data to the master device10m.

The master interface MI according to some implementations may include a data encoding circuit110, and the slave interface SI according to some implementations may include a data decoding circuit120.

The data encoding circuit110according to some implementations may perform an encoding operation on data before providing data from the master device10mto the bus BUS. The data encoding circuit110may provide encoded data in the form of write data WD to a write data channel CW of the bus BUS. A detailed description of the data encoding circuit110will be provided later with reference toFIG.4andFIG.6.

The data decoding circuit120may perform decoding operation with respect to the write data WD received from the write data channel CW. The data decoding circuit120will be described in detail later with reference toFIG.5andFIG.7. The data encoding circuit110and the data decoding circuit120may be configured as a data pattern optimizer DPO.

In addition, as shown inFIG.2, the transformation signal Ts may be provided to the data decoding circuit120through the write data channel CW, but implementations are not limited thereto; in some implementations, the transformation signal Ts may be transmitted through other additional channels of the bus BUS besides the write data channel CW.

Although it is not illustrated, the master interface MI and the slave interface SI may include an arbiter, a decoder, and/or the like. Through the arbiter, the master device10mand the slave device10smay request the right to use the bus BUS. Through the decoder, the master device10mmay activate the slave device10s, which is a target of the address ADDR.

FIG.3is provided for description of the data channel according to some implementations.

Referring toFIG.2andFIG.3, the write data channel CW may include a plurality of data flipflops FF00to FFTx and a plurality of data clock gating circuits CG00to CGTx arranged in parallel. In some implementations, the plurality of data flipflops FF00to FFTx may be arranged in (x+2) rows and (x+1) columns, and the plurality of data clock gating circuits CG00to CGTx may also be arranged in (x+2) rows and (x+1) columns. The write data channel CW is a data path between the master device10mand the slave device10s, and the SoC1aofFIG.1may perform a buffering operation or register slice operation through arrangement of the plurality of data flipflops FF00to FFTx in the write data channel CW.

An (n_0)th encoded data Dn[0] output from the data encoding circuit110may be provided to the data decoding circuit120as a 0th output encoded data Do[0] through data flipflops FF00to FF0xof the 0-th row. An (n_m)th encoded data Dn[m] output from the data encoding circuit110may be provided to the data decoding circuit120as m-th output encoded data Do[m] through data flipflops FFm0 to FF0mxof an m-th row. The provision operation for the (n_0)th encoded data Dn[0] and the (n_m)th encoded data Dn[m] may also be applied to the remaining n-th encoded data Dn[0:m].

Likewise, an n-th transformation signal Tsn output from the data encoding circuit110may be provided to the data decoding circuit120as an output transformation signal Tso through data flipflops FFT0-FFTx of an (m+2)th row.

In addition, the plurality of data flipflops FF00to FFTx may perform a latch on an n-th encoded data Dn[0:m] and an n-th transformation signal Tsn based on the clock signal clk. Through repeated latch operations, the n-th encoded data Dn[0:m] may be provided to the data decoding circuit120as an output encoded data Do[0:m].

The plurality of data clock gating circuits CG00to CGTx are provided with data of an input stage and data of an output stage to each corresponding data flipflop FF00to FFTx, and perform a clock gating operation on the clock signal clk input to the plurality of data flipflops FF00to FFTx.

As an example, a 0_0-th data clock gating circuit CG00may include a clock gating AND operator CG_A and a clock gating XOR operator CG_X.

The clock gating XOR operator CG_X may provide an XOR operation result value to the clock gating AND operator CG_A based on data of an input terminal and latch data of the 0_0th data flipflop FF00. The clock gating AND operator CG_A gates the XOR bit operation result value and the clock signal clk by performing an AND operation and may provide input as a clock of the data flipflops FF00to FFTx.

A 0_0th data clock gating circuit CG00compares (n_0)th encoded data Dn[0] and (n−1_0)th encoded data Dn−1[0], and performs clock gating with respect to the clock signal Clk input to the 0_0th data flipflop FF00.

The description of the 0_0th data clock gating circuit CG00and the 0_0th data flipflop FF00may also be applied to the remaining plurality of clock gating circuits CG00to CGTx and the plurality of data flipflops FF00to FFTx.

FIG.4is a block diagram of the data encoding circuit according to some implementations.

Referring toFIG.2andFIG.4, the data encoding circuit110may include a plurality of encoding flipflops111, a plurality of encoding clock gating circuits112, a first bit operator113, a second bit operator114, a first adder115, a second adder116, a first comparator117, a second comparator118, an encoding control unit119, a mask unit110MU, and a data transformation logic110DT.

The data encoding circuit110may encode an (n+1)th data DP (n+1) [0:m] input through the master interface MI (refer toFIG.2) to an (n+1) encoded data Dn+1[0:m] by performing an encoding operation, and may provide the (n+1) encoded data Dn+1[0:m] and an (n+1)th transformation signal Ts (n+1) to the write data channel CW.

The plurality of encoding flipflops111may latch an n-th encoded data Dn[0:m] and an n-th transformation signal Tsn input before the input of the n-th data DPn 1[0:m].

The plurality of encoding clock gating circuits112may perform the clock gating operation with respect to the clock of the plurality of encoding flipflops111based on the n-th encoded data Dn[0:m] and the n-th transformation signal Tsn latched to the output terminal of the plurality of encoding flipflops111and the (n+1)th encoded data D(n+1) [0:m]) and the (n+1)th transformation signal Ts(n+1) input to the input terminal of plurality of encoding flipflops111. The descriptions of the plurality of encoding clock gating circuit112and the plurality of encoding flipflops111may be as provided for the 0_0th data clock gating circuit CG00and the 0_0th data flipflop FF00ofFIG.3.

The first bit operator113may perform a bit operation for the (n+1)th data DPn+1[0:m] and the n-th encoded data Dn[0:m] latched to the plurality of encoding flipflop111, and may provide a result of the bit operation to the first adder115. In some implementations, the bit operation of the first bit operator113may be an XOR operation, but the implementations are not limited to that bit operation example. When the bit operation of the first bit operator113is an XOR operation and a bit value of each digit of the result value of first bit operator113is 1, it means that a bit value corresponding to a position in the (n+1)th data DPn+1[0:m] and a bit value corresponding to a position in the n-th encoded data Dn[0:m] are different from each other.

For example, when an XOR bit operation is formed on random data “1001(2)” and “1101(2)”, a result of the bit operation may be “0100(2)”. Since a most significant bit (MSB) value of the “1001(2)” and an MSB value of the “1101(2)” are equal to each other, an MSB value of the result value “0100(2)” is 0. Since an MSB-1 bit value of “1001(2)” and an MSB-1 bit value of “1101(2)” are different from each other, an MSB-1 value of the result value “0100(2)” is 1.

The second bit operator114may perform a bit operation on (n+1)th shift data SDPn+1[0:m] obtained by performing a circular shift operation on the (n+1)th data DPn+1[0:m] and the n-th encoded data Dn[0:m], and the result value of the bit operation may be provided to the second adder116. In some implementations, the circular shift operation may be performed in the right direction by 1-bit units, but the shift direction and shift bit unit are not limited thereto.

In some implementations, the bit operation of the second bit operator114may be an XNOR operation, but the bit operation is not limited thereto. When the bit operation of the second bit operator114is the XNOR operation and a bit value of each digit of the result value of the second bit operator114is 1, it means that a bit value of a corresponding digit in the (n+1)th shift data SDPn+1[0:m] and a bit value of a corresponding digit in the n-th encoded data Dn[0:m] equal to each other.

The first adder115may generate a first sum value A by bit counting the result value of the first bit operator113, and provide the first sum value A to the first comparator117and the second comparator118.

The second adder116may generate a second sum value B by bit counting the result value of the second bit operator114and provide the second sum value B to the second comparator118.

The first comparator117may output an (n+1)th invert signal SIn+1 and provide the (n+1)th invert signal SIn+1 to the mask unit110MU and the encoding control unit119based on the first sum value A and the number of bits m+1 of the (n+1)th data DPn+1[0:m]. For example, the first comparator117may perform a comparison operation based on the m+1 value and the size of the first sum value A, and output the (n+1)th invert signal SIn+1 according to the comparison result.

Through the comparison operation of the first comparator117, the data encoding circuit110may predict a clock gating efficiency of the (n+1)th encoded signal Dn+1[0:m] converted by performing an invert operation on the (n+1)th data DPn+1[0:m].

The second comparator118may output a (n+1)th shift signal SSn+1 and provide the same to the mask unit110MU and the encoding control unit119based on the first sum value A, the second sum value B, and the nit number m+1 of the (n+1)th data DPn+1[0:m]. For example, the second comparator118may perform a comparison operation based on the size of m+1 value, the first sum value A, and the second sum value B, and output the (n+1)th shift signal SSn+1 according to the comparison result.

Through the comparison operation of the second comparator118, the data encoding circuit110in some implementations may predict a clock gating efficiency of an (n+1)th encoding signal Dn+1[0:m] converted by performing a circular shift operation on the (n+1)th data DPn+1[0:m].

The encoding control unit119may receive at least a part of the (n+1)th data DPn+1[0:m], the (n+1)th invert signal SIn+1, and the (n+1)th shift signal SSn+1, and may provide an invert enable signal IEn and a shift enable signal SEn to the mask unit110MU.

The encoding control unit119may include a burst counter119B and a pattern selector119PS.

The burst counter119B checks whether a data input/output mode of the master interface MI is a burst mode, and if it is the burst mode, the burst counter119B may provide the invert enable signal IEn and the shift enable signal SEn of a turn-on level to the mask unit110MU.

For example, when the burst counter119B is in the burst mode in which data output of the (n+1)th data DPn+1[0:m] and n-th encoding signal Dn[0:m] is performed continuously with one request, the invert enable signal IEn and the shift enable signal SEn can be set to turn-on level.

On the other hand, burst counter119B may turn off the invert enable signal IEn and the shift enable signal SEn when the data output of (n+1)th data DPn+1[0:m] and n-th encoding signal Dn[0:m] are performed by different requests.

The pattern selector119PS may receive at least a part of the (n+1)th data DPn+1[0:m], the (n+1)th invert signal SIn+1, and the (n+1)th shift signal SSn+1, and may determine an encoding operation to be performed on the (n+1)th data DPn+1[0:m]. Depending on the determination, the pattern selector119PS may turn on/off the invert enable signal IEn and/or shift enable signal SEn.

The conditions for the determination of the pattern selector119PS may vary depending on the implementation. The pattern selector119PS will be described in detail, together with a pattern selector129PS ofFIG.5, later with reference toFIG.9toFIG.12.

In addition to the (n+1)th data DPn+1[0:m], the (n+1)th invert signal SIn+1, and the (n+1)th shift signal SSn+1, the pattern selector119PS may receive separate control signals such as a special function register (SFR) signal and a signal output from the master device10m. The pattern selector119PS may turn on/off an invert enable signal IEn and/or shift enable signal SEn at once by the separate control signal.

The pattern selector119PS in some implementations may turn on/off the invert enable signal IEn and/or shift enable signal SEn according to an operation mode of the master device10m. As an example, the pattern selector119PS may collectively turn on/off the invert enable signal IEn and/or shift enable signal SEn depending on the operation mode of the master device10m.

Information on the operation mode of the master device10mmay be transmitted to the pattern selector129PS ofFIG.5. The information on the operation mode may be transmitted in the form of a separate flag bit or a partial pattern of the (n+1)th encoded data Dn+1[0:m] to the pattern selector129PS ofFIG.5.

The mask unit110MU may receive the (n+1)th invert signal SIn+1, the (n+1)th shift signal SSn+1, the invert enable signal IEn, and the shift enable signal SEn, and may activate the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 based on the invert enable signal IEn and the shift enable signal SEn. The mask unit110MU may output an (n+1)th transformation signal Tsn+1 based on the activated (n+1)th invert signal SIn+1 and (n+1)th shift signal SSn+1. In some implementations, the output (n+1)th transformation signal Tsn+1 may be 1 bit. Since the number of bits allocated to the transformation signal Ts (refer toFIG.1) may be 1, a bandwidth output together in parallel with the (n+1)th data DPn+1[0:m] of the present disclosure can be reduced.

The mask unit110MU may provide the activated (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 in the form of selection signals to a data transformation logic110DT. In addition, the mask unit110MU may provide the (n+1)th transformation signal Tsn+1 output based on the (n+1)th invert signal SIn+1, the (n+1)th shift signal SSn+1, the invert enable signal IEn, and the shift enable signal SEn to the plurality of encoding flipflops111.

The data transformation logic110DT may perform a transformation operation on the (n+1)th data DPn+1[0:m] based on the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1. The transformation operation may include performing one of a maintenance operation, an invert operation, or a circular shift operation on the (n+1)th data DPn+1[0:m]. The transformation operation performed on the (n+1)th data DPn+1[0:m] may be determined based on the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1.

The data transformation logic110DT may provide the (n+1)th data DPn+1[0:m] to input terminals of the plurality of encoding flipflops111before the transformation operation.

FIG.5is a block diagram of the data decoding circuit according to some implementations.

Referring toFIG.5together withFIG.2, the data decoding circuit120may include a plurality of decoding flipflops121, a plurality of decoding clock gating circuits122, a decoding control unit129, and the data transformation logic120DT.

The data decoding circuit120may decode output decoded data Do[0:m] input through the slave interface SI (refer toFIG.2) to decoded data DDo[0:m] by performing a decoding operation.

The plurality of decoding flipflops121may receive preceding decoded data DDo−1[0:m] as input before inputting the decoded data DDo[0:m]. The plurality of decoding flipflops121may receive and latch the preceding decoded data DDo−1[0:m].

The plurality of decoding clock gating circuits122may perform a clock gating operation on the plurality of decoding flipflops121based on the preceding decoded data DDo−1[0:m] latched to output terminals of the plurality of decoding flipflops121and the decoded data DDo[0:m] input to the input terminals of the plurality of decoding flipflops121. Description of the plurality of decoding clock gating circuits122and the plurality of decoding flipflops121may be as provided for the 0_0th data clock gating circuit CG00and the 0_0th data flipflop FF00ofFIG.3.

The decoding control unit129may receive at least a part of the output encoded data Do[0:m] and the output transformation signal Tso, and output the output invert signal SIo and the output shift signal SSo and provide them to the data transformation unit120DT.

The decoding control unit129may include a pattern selector129PS. The pattern selector129PS may receive at least a part of the output encoded data Do[0:m] and the output transformation signal Tso, and may determine a decoding operation to be performed on the output encoded data Do[0:m]. According to the determination, the pattern selector129PS may output the output invert signal SIo and the output shift signal SSo.

The conditions for the determination of the pattern selector129PS may vary depending on the implementation. A detailed description of the pattern selector129PS is provided in reference to the pattern selector119PS ofFIG.4, together with reference toFIG.9toFIG.12.

The pattern selector129PS may receive information on the operation mode of the master device10mthrough at least a part of the output encoded data Do[0:m] and a separate flag bit. In some implementations, the pattern selector129PS may receive information on the operation mode of the master device10mthrough at least a part of the output encoded data Do[0:m].

The data transformation logic120DT may perform a transformation operation for the output encoded data Do[0:m] based on the output invert signal SIo and the output shift signal SSo. The transformation operation may include performing any one of a maintenance operation, an invert operation, or a circular shift operation on the output encoded data Do[0:m]. The transformation operation performed on the output encoded data Do[0:m] can be determined based on the output invert signal SIo and the output shift signal SSo.

FIG.6is a circuit diagram provided for description of a data encoding circuit according to some implementations.

A data encoding circuit110aofFIG.6may be in a form implemented according to the example of the data encoding circuit110ofFIG.4. Referring toFIG.4andFIG.6, data encoding circuit110amay include a plurality of encoding flipflops111, a plurality of encoding clock gating circuits112, a first bit operator113, a second bit operator114a, a first adder115, a second adder116, a first comparator117, a second comparator118, an encoding control unit119, a mask unit110MU, and a data transformation logic110DTa.

The plurality of encoding flipflops111may include 0th to m-th encoding flipflops111_0to111_mand a transformation flipflop111_T. Each of the 0th to m-th encoding flipflops111_0to111_mmay respectively receive a bit of an (n+1)th data DPn+1[0:m] or a bit of an (n+1)th encoded data Dn+1[0:m] output through the data transformation logic110DTa.

For example, the 0th encoding flipflop111_0may receive an (n+1_0)th data DPn+1[0] before performing a transformation operation for the (n+1)th data DPn+1[0:m], and may receive an (n+1_0)th encoded data Dn+1[0] after performing the transformation operation for the (n+1_0)th encoded data Dn+1[0].

The transformation flipflop111_T may receive an (n+1)th transformation signal Tsn+1 output from the mask unit110MU.

The plurality of encoding clock gating circuits112may include 0th to m-th encoding clock gating AND operators112_0to112_mand a transformation clock gating AND operator112_T. A detailed description of the plurality of encoding clock gating circuits112is provided along with a description of the first bit operator113.

The first bit operator113may include 0-th to m-th XOR operators113X_0to113X_m and a transformation XOR operator113_. The 0-th to m-th XOR operators113X_0to113X_m and the transformation XOR operator113_T may perform an XOR bit operation for the n-th encoded data Dn[0:m] latched to output terminals of the 0th to m-th encoding flipflops111_0to111_mand the transformation flipflop111_T, and an n-th transformation signal Tsn and the n-th encoded data Dn[0:m] and an (n+1)th transformation signal Tsn+1 input to input terminals of the 0-th to m-th encoding flipflops111_0to111_m.

The 0-th to m-th XOR operators113X_0to113X_m may provide an XOR result value XORout[0:m], which is a result of the XOR bit operation, to the first adder115and the 0-th to m-th encoding clock gating AND operators112_0to112_m. The transformation XOR operator113_T may provide an operation result to the transformation clock gating AND operator112_T.

For example, the 0th XOR operator113X_0performs an XOR operation for the (n_0)th encoded data Dn[0] latched to an output terminal of the 0th encoding flipflop111_0and the (n+1_0)th data DPn+1[0] input to an input terminal of the 0-th encoding flipflop111_0, outputs an 0th XOR result value XORout[0], and provides the 0-th XOR result value XORout[0] to the first adder115and a 0th encoding clock gating AND operator112_0.

The XOR result value XORout[0:m] of the 0th to m-th XOR operators113X_0to113X_m may be transmitted to the first adder115through 0th to m-th invert loop prevention buffers ILB_0to ILB_m. When an enable signal EN is input to the 0th to m-th invert loop prevention buffers ILB_0to ILB_m, the XOR result value XORout[0:m] may be input to the first adder115. Through the 0th to m-th invert loop prevention buffers ILB_0to ILB_m, the data encoding circuit110amay prevent an (n+1)th invert signal SIn+1 and an (n+1)th shift signal SSn+1 output by the XOR result value XORout[0:m] from being feedback due to the XOR result value XORout[0:m].

Each of the 0-th to m-th encoding clock gating AND operators112_0to112_mand the transformation clock gating AND operator112_T may operate as one clock gating circuit with 0th to m-th XOR operators113X_0to113X_m of the first bit operator113and the transformation XOR operator113_T. Descriptions of the 0th to m-th encoding clock gating AND operators112_0to112_m, the transformation clock gating AND operator112_T, the 0-th to m-th XOR operators113X_0to113X_m, and the transformation XOR operator113_T may be as provided for the 0_0th data clock gating circuit CG00ofFIG.3.

For example, a 0th to m-th XOR operator113X_0may output a 0-th XOR result value XORout[0] by receiving the (n+1_0)th data DPn+1[0], which is input data of the 0-th encoding flipflop111_0and the (n+0)th encoded data Dn[0], and may provide the 0-th XOR result value XORout[0] to the 0-th encoding clock gating AND operator112_0. The 0-th encoding clock gating AND operator112_0may perform a clock gating operation for a clock of the 0th encoding flipflop111_0based on a clock signal clk and the 0-th XOR result value XORout[0].

The second bit operator114amay include 0th to m-th XNOR operators114XN_0to114XN_m. The 0th to m-th XNOR operators114XN_0to114XN_m may perform an XNOR bit operation for the n-th encoded data Dn[0:m] latched to an output terminal of the 0th to m-th encoding flipflops111_0to111_mand data circularly shifted by 1-bit units in the right direction with respect to the (n+1)th data DPn+1[0:m].

The 0-th to m-th XNOR operators114XN_0to114XN_m may provide the XNOR result value XNORout[0:m], which is a result of the XNOR bit operation, to the second adder116.

For example, the 0th XNOR operator114XN_0performs an XNOR operation for (n_0)th encoded data Dn[0] latched to an output terminal of the 0th encoding flipflop111_0and an n+1_1 data DPn+1[1] input to an input terminal of the first encoding flipflop111_1, outputs a 0th XNOR result value XNORout[0], and provides the 0th XNOR result value XNORout[0] to the second adder116. In addition, the m-th XNOR operator114XN_m may perform an XNOR operation for an (n_m)th encoded data Dn[m] latched to an output terminal of an m-th encoding flipflop111_mand an (n+1_0)th data DPn+1[0] input to an input terminal of the 0th encoding flipflop111_0, and may output and provide an m-th XNOR result value XNORout[m] to the second adder116.

The XNOR result values XNORout[0:m] of the 0th to m-th XNOR operators114XN_0to114XN_m may be transmitted to the second adder116through 0th to m-th shift loop prevention buffers SLB_0to SLB_m. When an enable signal EN is input to the 0th to m-th shift loop prevention buffers SLB_0to SLB_m, the XNOR result value XNORout[0:m] may be input to the second adder116. The data encoding circuit110amay prevent the (n+1)th shift signal SSn+1 output by the XNOR result value XNORout[0:m] from being fed back to the XNOR result value XNORout[0:m] through the 0th to m-th shift loop prevention buffers SLB_0to SLB_m.

The first adder115may bit count the XOR result value XORout[0:m], generate a first sum value A, and provide the first sum value A to the first comparator117and the second comparator118.

The second adder116may bit count the XNOR result value XNORout[0:m], generate a second sum value B, and provide the second sum value B to the second comparator118.

In some implementations, the first comparator117may output the (n+1)th invert signal SIn+1 based on whether Equation 1 below is satisfied, but operations of the first comparator117are not limited thereto. The output (n+1)th invert signal Sin+1 may be provided to the mask unit110MU and the encoding control unit119.

In Equation 1, A denotes the first sum value A and M denotes the number of bits of the first data DPn+1[0:m]). Here, M may be m+1. Through the comparison operation of the first comparator117, the data encoding circuit110in some implementations performs an invert operation on the (n+1)th data DPn+1[0:m] to predict a clock gating efficiency of the converted (n+1)th encoding signal Dn+1[0:m].

In some implementations, the second comparator118may output the (n+1)th shift signal SSn+1 based on whether Equation 2 below is satisfied, but operations of the second operator118are not limited thereto. The output (n+1)th shift signal SSn+1 may be provided to the mask unit110MU and the encoding control unit119.

In Equation 2, A denotes the first sum value A, B denotes the second sum value B, and M is the number of bits of the first data DPn+1[0:m]. Here, M may be m+1. The second comparator118calculates based on the first sum value A, the second sum value B, and the number of bits m+1 of (n+1)th data DPn+1[0:m] to thereby predict the clock gating efficiency of the (n+1)th encoding signal Dn+1[0:m] transformed by performing a circular shifting operation on the (n+1)th data DPn+1[0:m].

In some implementations, the encoding control unit119may receive the (n+1_0)th to (n+1_2)th data DPn+1[0:2]), the (n+1)th invert signal SIn+1, and the (n+1)th shift signal SSn+1, and may output and provide an invert enable signal IEn and a shift enable signal SEn to the mask unit110MU.

The encoding control unit119may include a burst counter119B and a pattern selector119PS.

The burst counter119B checks whether a data input/output mode of the master interface MI is a burst mode, and if it is a burst mode, sets the invert enable signal IEn and the shift enable signal SEn to a turn-on level and provides the enable signal IEn and the shift enable signal SEn in the turn-on level to the mask unit110MU. When an output of the (n+1)th data DPn+1[0:m] and an data output of the n-th encoding signal Dn[0:m] are performed by different requests, the burst counter119B may set the invert enable signal IEn and the shift enable signal SEn to a turn-off level.

In some implementations, the pattern selector119PS receives (n+1_0)th to (n+1_2)th data DPn+1[0:2], the (n+1)th invert signal SIn+1, and the (n+1)th shift signal SSn+1, and may determine an encoding operation to be performed on the (n+1)th data DPn+1[0:m]. According to the determination, the pattern selector119PS may set the invert enable signal IEn and/or shift enable signal SEn to an enable/turn-off level.

For example, the pattern selector119PS may perform an OR operation for the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1, and may output the invert enable signal IEn and/or shift enable signal SEn according to a pattern of the (n+1_0)th to (n+1_2)th data DPn+1[0:2].

For example, when a value of the OR operation for the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 is “1” and the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are different from each other, the pattern selector119PS may set the invert enable signal IEn to a turn-off level and the shift enable signal SEn to a turn-on level. When the OR operation value for the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 is “1” and the (n+1_0)th data DPn+1[0], the (n+1_1)th data DPn+1[1], and the (n+1_2)th data DPn+1[2] are all the same, the pattern selector119PS may set the invert enable signal IEn to a turn-on level and the shift enable signal SEn to a turn-off level. When the OR operation value for the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 is “1” and the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are the same and only the (n+1_0)th data DPn+1[0] is different, the pattern selector119PS may set both the invert enable signal IEn and the shift enable signal SEn to a turn-off level.

This pattern of the (n+1)th data DPn+1[0:m] and outputs of the invert enable signal IEn and the shift enable signal SEn according to the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 are described as an example, and the scope of implementations according to the present disclosure is not limited to that pattern.

The pattern selector119PS is described in additional detail with reference toFIG.9toFIG.12and with reference to the pattern selector129PS ofFIG.7.

The pattern selector119PS shown inFIG.6receives the (n+1_0)th to (n+1_2)th data DPn+1[0:2]) among the (n+1)th data DPn+1[0:m] and outputs the invert enable signal IEn and/or shift enable signal SEn based on the received data. However, the input data to the pattern selector119PS from among the (n+1)th data DPn+1[0:m] is not limited to this example.

In some implementations, the mask unit110MU may include first and second invert AND operators Ian_1and Ian_2, first and second shift AND operators San_1and San_2, and a transformation OR operator TsOR.

The first invert AND operator Ian_1and the second invert AND operator Ian_2may receive the invert enable signal IEn and the (n+1)th invert signal SIn+1. The first invert AND operator Ian_1may provide an AND operation result of the invert enable signal IEn and the (n+1)th invert signal SIn+1 to a data transformation unit110DTa. The second invert AND operator Ian_2may provide an AND operation result of the invert enable signal IEn and the (n+1)th invert signal SIn+1 to a transformation OR operator TsOR. The first invert AND operator Ian_1may determine activation of the (n+1)th invert signal SIn+1 through an AND operation with the invert enable signal IEn. The first invert AND operator Ian_1may output the activated (n+1)th invert signal SIn+1.

The first and second shift AND operators San_1and San_2may receive the shift enable signal SEn and the (n+1)th shift signal SSn+1. The first shift AND operator San_1may provide an AND operation result of the shift enable signal SEn and the (n+1)th shift signal SSn+1 to the data transformation unit110DTa. The second shift AND operator San_2may provide an AND operation result of the shift enable signal SEn and the (n+1)th shift signal SSn+1 to the transformation OR operator TsOR. The first shift AND operator San_1may determine activation of the (n+1)th shift signal SSn+1 through an AND operation with the shift enable signal SEn. The first shift AND operator San_1may output the activated (n+1)th shift signal SSn+1.

The transformation OR operator TsOR may output an (n+1)th transformation signal Tsn+1 based on an operation result of the second invert AND operator Ian_2and the second shift AND operator San_2. The transformation OR operator TsOR may output the (n+1)th transformation signal Tsn+1 that considers activation of the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 based on an operation result of the second invert AND operator Ian_2and an operation result of the second shift AND operator San_2.

The output (n+1)th transformation signal Tsn+1 may be 1 bit. Since the number of bits allocated to the transformation signal Ts (refer toFIG.1) can be 1, a bandwidth output in parallel with the (n+1)th data DPn+1[0:m] of the present disclosure can be reduced.

In addition, the (n+1)th transformation signal Tsn+1 is a signal output from the OR operation of the activated (n+1)th invert signal SIn+1 and the activated (n+1)th shift signal SSn+1, and when one of the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 is activated, the (n+1)th transformation signal Tsn+1 may be activated. For example, when a value of one of the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 is “1”, a value of the (n+1)th transformation signal Tsn+1 may be “1”.

However, when both the (n+1)th invert signal Sin+1 and the (n+1)th shift signal SSn+1 are deactivated, the (n+1)th transformation signal Tsn+1 may be deactivated. For example, when values of the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 are “0”, the value of the (n+1)th transformation signal Tsn+1 may be “O”.

The data transformation unit110DTa may perform an encoding operation of any one of a maintenance operation, an invert operation, or a circular shift operation for the (n+1)th data DPn+1[0:m] based on the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1.

In some implementations, the data transformation unit110DTa may include 0-th to m-th transformation XOR operators TX_1to TX_m and 0-th to m-th transformation MUXs TM_0to TM_m. Each of the 0-th to m-th transformation XOR operators TX_1to TX_m may receive the (n+1)th data DPn+1[0:m] and (n+1)th invert signal SIn+1 and perform an XOR bit operation.

For example, the 0-th transformation XOR operator TX_0may receive the (n+1_0)th data DPn+1[0] and the (n+1)th invert signal SIn+1. When the received (n+1)th invert signal SIn+1 is “0”, the 0-th transformation XOR operator TX_0may output the (n+1_0)th data DPn+1[0] as it is, and when the received (n+1)th invert signal SIn+1 is “1”, the 0-th transformation XOR operator TX_0may invert and output the (n+1_0)th data DPn+1[0]. In some implementations, the value of the (n+1)th transformation signal Tsn+1 may be “1”.

Each of the 0th to m-th transformation MUXs TM_0to TM_m may receive a result value of each of the 0th to m-th transformation XOR operators TX_1to TX_m and each data circularly shifted in 1-bit units in the right direction with respect to the (n+1)th data DPn+1[0:m], and may receive the (n+1)th shift signal SSn+1 as a selection signal. Each of the 0th to m-th transformation MUXs TM_0to TM_m may output any one of the result value of each of the 0th to m-th transformation XOR operators TX_1to TX_m and the circularly shifted data based on the (n+1)th shift signal SSn+1.

For example, the 0th MUX TM_0may receive a result value of the 0th transformation XOR operator TX_0and the (n+1_1)th data DPn+1[1], and may receive the (n+1)th shift signal SSn+1 as a selection signal. When the received (n+1)th shift signal SSn+1 is “0”, the 0th transformation MUX TM_0outputs a result value of the 0th transformation XOR operator TX_0and provides the output result value to the 0th encoding flipflop111_0. When the received (n+1)th shift signal SSn+1 is “1”, the 0th transformation MUX TM_0may output the (n+1_1)th data DPn+1[1] and provide the output data to the 0th encoding flipflop111_0.

In addition, the m-th transformation MUX TM_m may receive a result value of the mth transformation XOR operator TX_m and the (n+1_0)th data DPn+1[0], and may receive the (n+1)th shift signal SSn+1 as a selection signal. When the (n+1)th shift signal SSn+1 is “0”, the m-th transformation MUX TM_m may output a result value of the m-th transformation XOR operator TX_m and provide the output result value to the m-th encoding flipflop111_m. When the (n+1)th shift signal SSn+1 is “1”, the 0th transformation MUX TM_m may output the (n+1_0)th data DPn+1[0] and provide the output data to the m-th encoding flipflop111_m.

The data transformation unit110DTa outputs the (n+1)th encoded data Dn+1[0:m] on which any one of a maintenance operation, an invert operation, or a circular shift operation for the (n+1)th data DPn+1[0:m] based on the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1, and provides the output encoded data to the plurality of encoding flipflops111.

Accordingly, the (n+1)th transformation signal Tsn+1 output based on the activated (n+1)th invert signal SIn+1 and (n+1)th shift signal SSn+1 may include encoding operation information with respect to the (n+1)th data DPn+1[0:m].

In addition, the data transformation unit110DTa may control the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 before performing the encoding operation, and provides (n+1)th data DPn+1[0:m] to an input terminal of each of the 0th to m-th encoding flipflops111_0to111_m. Before the encoding operation of the data transformation unit110DTa, first bit operator113may output the XOR result value XORout[0:m] based on the provided (n+1)th data DPn+1[0:m]. the (n+1)th transformation signal Tsn+1 may indicate whether any one of an invert operation, or a circular shift operation for the (n+1)th data DPn+1[0:m] is performed.

FIG.7is a circuit diagram provided for description of a data decoding circuit according to some implementations.

A data decoding circuit120aofFIG.7is an example of the data decoding circuit120ofFIG.5. Referring toFIG.5andFIG.7, the data decoding circuit120amay include a plurality of decoding flipflops121, a plurality of decoding clock gating circuits122, a decoding control unit129, and a data transformation logic120DTa.

The plurality of decoding flipflops121may include 0th to m-th decoding flipflops121_0to121_m. Each of the 0th to m-th decoding flipflops121_0to121_mmay receive a bit of decoded data DDo[0:m] output through the data transformation logic120DTa through an input terminal, and may latch preceding decoded data DDo−1[0:m] to an output terminal. For example, the 0th decoding flipflops121_0may receive 0th decoded data DDo[0] through an input terminal and latch 0th preceding decoded data DDo−1[0] to an output terminal.

The plurality of decoding clock gating circuits122may include 0th to m-th decoding clock gating AND operators122A_0to122A_m and 0th to m-th decoding clock gating XOR operators122X_0to122X_m.

The 0th to m-th decoding clock gating XOR operators122X_0to122X_m may provide XOR operation result value to the 0th to m-th decoding clock gating AND operators122A_0to122A_m based on data at the input terminals of the 0th to m-th decoding flipflops121_0to121_mand latch data at the output terminals of the 0th to m-th decoding flipflops121_0to121_m. The 0th to m-th decoding clock gating AND operators122A_0to122A_m may gate the XOR operation result value and a clock signal clk by performing an AND operation and input as a clock of the 0th to m-th decoding flipflops121_0to121_m.

For example, the 0th decoding clock gating XOR operator122X_0may provide an XOR operation result value to the 0th decoding gating AND operator122A_0based on the 0th decoded data DDo[0] and the 0th preceding decoded data DDo−1[0] latched to the 0th decoding flipflops121_0. The 0th decoding gating AND operator122A_0may gate the XOR operation result value and the clock signal clk by performing an AND operation, and provide input as a clock of the 0th decoding flipflops121_0.

The plurality of decoding clock gating circuits122compare each decoded data DDo[0:m] and the preceding decoded data DDo−1[0:m] latched to the 0th to m-th decoding flipflops121_0to121_m, and may perform clock gating with respect to the clock signal clk input to the 0th to m-th decoding flipflops121_0to121_m.

The decoding control unit129may receive the 0th and first output encoded data Do[0:1], which are adjacent bits among the output encoded data Do[0:m] and an output transformation signal Tso, and may output an output invert signal SIo and an output shift signal SSo based on the 0th and first output encoded data Do[0:1] and the output transformation signal Tso and provide the output invert signal SIo and the output shift signal SSo to the data transformation unit120DTa.

The decoding control unit129may include a pattern selector129PS. The pattern selector129PS may determine a decoding operation to be performed on the output encoded data Do[0:m] based on the 0th and first output encoded data Do[0:1] and the output transformation signal Tso. According to the determination, the pattern selector129PS may turn on/off the output invert signal SIo and/or the output shift signal SSo.

For example, when a value of the output transformation signal Tso is “0”, the pattern selector129PS turns off both the output invert signal SIo and the output shift signal SSo such that that the operation for the output encoded data Do[0:m] may be determined as a maintenance operation. When a value of the output transformation signal Tso is “1” and the 0th and first output encoded data Do[0:1] are different from each other, the pattern selector129PS turns off the output invert signal SIo and turns on the output shift signal SSo such that the decoding operation for the output encoded data Do[0:m] can be determined as a shift operation. When a value of the output transformation signal Tso is “1” and the 0th and first output encoded data Do[0:1] are equal to each other, the pattern selector129PS turns on the output invert signal SIo and turns off the output shift signal SSo such that the decoding operation for the output encoded data Do[0:m] may be determined as an invert operation.

The operation of the pattern selector129PS is described in detail with reference toFIG.9toFIG.12and in reference to the pattern selector119PS ofFIG.6.

The pattern selector129PS may receive the 0th and first output encoded data Do[0:1] among the output encoded data Do[0:m] and output the output invert signal Slo and the output shift signal SSo based on the 0th and first output encoded data Do[0:1]. In some implementations, the data input from among the output encoded data Do[0:m] is not limited to Do[0:1] but can be other data from among the output encoded data Do[0:m].

The data transformation unit120DTa may perform an encoding operation among any one of a maintenance operation, an invert operation, or a circular shift operation for the output encoded data Do[0:m] based on the output invert signal SIo and the output shift signal SSo.

In some implementations, the data transformation unit120DTa may include 0th and m-th decoding XOR operators DX_0to DX_m and 0th and m-th decoding MUXs DM_0to DM_m. Each of the 0th and m-th decoding XOR operators DX_0to DX_m may receive the output encoded data Do[0:m] and the output invert signal SIo, and perform an XOR bit operation.

For example, the 0th decoding XOR operator DX_0may receive 0th output encoded data Do[0] and the output invert signal SIo. When the output invert signal SIo is “0”, the 0th decoding XOR operator DX_0outputs the 0th output encoded data Do[0] as it is, and when the output invert signal SIo is “1”, the 0th decoding XOR operator DX_0may invert and output the 0th output encoded data Do[0].

Each of the 0th and m-th decoding MUXs DM_0to DM_m may receive a result value of each of the 0th to m-th decoding XOR operators DX_0to DX_m and data circularly shifted to 1 bit unit in the left direction with respect to the output encoded data Do[0:m], and may receive the output shift signal SSo as a selection signal. Each of the 0th and m-th decoding MUXs DM_0to DM_m may output any one of the result value of the 0th and m-th decoding XOR operators DX_0to DX_m and the circularly shifted data based on the output shift signal SSo.

For example, the 0th decoding MUX DM_0may receive a result value of the 0th decoding XOR operator DX_0and the m-th output encoded data Do[m], and receive the output shift signal SSo as a selection signal. When the output shift signal SSo is “0”, the 0th decoding MUX DM_0may output a result value of the 0th decoding XOR operator DX_0and provide to the 0th decoding flipflops121_0. When the output shift signal SSo is “1”, the 0th decoding MUX DM_0may output the m-th output encoded data Do[m] and provide to the 0th decoding flipflops121_0.

In addition, the first decoding MUX DM_1may receive a result value of the first decoding XOR operator DX_m and the 0th output encoded data Do[0], and receive the output shift signal SSo as a selection signal. When the output shift signal SSo is “0”, the first decoding MUX DM_1outputs a result value of the first decoding XOR operator DX_m and provide to the first decoding flipflops121_1. When the output shift signal SSo is “1”, the first decoding MUX DM_1outputs the 0th output encoded data Do[0] and provide to the first decoding flipflops121_1.

The data transformation unit120DTa may output decoded data Do[0:m] on which any one of the maintenance operation, the invert operation, or the circular shift operation with respect to the output encoded data Do[0:m] has been performed, and provide the output decoded data Do[0:m] to the plurality of decoding flipflops121based on the output invert signal SIo and the output shift signal SSo

FIG.8is provided for description of an example of an encoding operation of the data encoding circuit according to some implementations.FIG.8shows an example of an operation of the data encoding circuit110aofFIG.6when the invert enable signal IEn and the shift enable signal SEn are set to the turn-on level and the (n+1)th data DPn 1[0:7], where m is 7, is input three times in succession,

Referring toFIG.6andFIG.8, the data encoding circuit110amay receive “11101011 2” as an (n+1)th data DPn+1[0:7] for a first clock cycle clockcycle1, “11101010 2” for a second clock cycle clockcycle2, and “00001110 2” for a third clock cycle clockcycle3.

Since the n-th encoded data Dn[0:7] is not latched in the first clock cycle clockcycle1, the first bit operator113and the second bit operator114amay not normally output an XOR result value XORout[0:7] and an XNOR result value XNORout[0:7]. Thus, “11101011 2” input to an input terminal of the plurality of encoding flipflops111before the transformation operation of the data transformation logic110DTa may be latched to an output terminal of the plurality of encoding flipflops111based on the clock signal clk.

“11101011 2” may be latched as the n-th encoded data Dn[0:7] to the output terminal of the plurality of encoding flipflops111in the second clock cycle clockcycle2, and “00001110 2” may be input as the (n+1)th data DPn+1[0:7] to the input terminal of the plurality of encoding flipflops111. The XOR result value XORout[0:7] may be “11100101 2” and the XNOR result value XNORout[0:7] may be “00010011 2”. Accordingly, the first sum value A may be 5 and the second sum value B may be 3.

Thus, the first comparator117may output by setting the (n+1)th invert signal Sin+1 to the turn-on level, and the second comparator118may output by setting the (n+1)th shift signal SSn+1 the turn-off level. The mask unit110MU may output by setting the (n+1)th transformation signal Tsn+1 to the turn-on level, assuming that the invert enable signal IEn and shift enable signal SEn are set to the turn-on level.

The data transformation logic110DTa may perform an invert operation for the “00001110(2)” in the second clock cycle clockcycle2 and may output “11110001(2)” as the (n+1)th encoded data Dn+1[0:7]. The data transformation logic110DTa may provide “1110001(2)” to the input terminal of the plurality of encoding flipflops111. “11110001(2)” input to the input terminal of plurality of encoding flipflops111may be latched to the output terminal of plurality of encoding flipflops111based on the clock signal clk.

“11110001(2)” may be latched as the n-th encoded data Dn[0:7] to the output terminal of the plurality of encoding flipflops111in the third clock cycle clockcycle3, and “11101010(2)” may be input as the (n+1)th data DPn+1[0:7] to the input terminal of the plurality of encoding flipflops111. The XOR result value XORout[0:7] may be “00011011(2)” and the XNOR result value XNORout[0:7] may be “01111011(2)”. Accordingly, the first sum value A may be 4 and the second sum value B may be 6.

Thus, the first comparator117may turn off the (n+1)th invert signal SIn+1 and output, and the second comparator118may turn on the (n+1)th shift signal SSn+1 and output. The mask unit110MU may output by setting the (n+1)th transformation signal Tsn+1 to the turn-on level, assuming that the invert enable signal IEn and the shift enable signal SEn are set to the turn-on level.

In the third clock cycle clockcycle3, the data transformation logic110DTa may perform a circular shift operation of 1 bit units in the right direction with respect to “11101010(2)”, and may output “01110101(2)” as the (n+1)th encoded data Dn+1[0:7]. The data transformation logic110DTa may provide “01110101(2)” to the input terminal of the plurality of encoding flipflops111. “01110101(2)” input to the input terminal of the plurality of encoding flipflops111may be latched to the output terminal of the plurality of encoding flipflops111based on the clock signal clk.

The data encoding circuit110amay receive the (n+1)th data DPn+1[0:7] in the order of “11101011(2)”, “00001110(2)”, and “11101010(2)” in the first to third clock cycles clockcycle1 to clockcycle3. The data encoding circuit110amay output the (n+1)th data DPn+1[0:7] in the order of “11101011(2)”, “11110001(2)”, and “01110101(2)” and may output the (n+1)th transformation signal Tsn+1 in the order of “0(2)”, “1(2)”, and “1(2)” in the first to third clock cycles clockcycle1 to clockcycle3.

FIG.9toFIG.10are provided for description of an example of the encoding operation of the data encoding circuit.FIG.9toFIG.10are provided for description of the operation of the data encoding circuit110aofFIG.6when the (n+1)th data DPn+1[0:7], where m is 7, is input four times in succession.

Referring toFIG.6,FIG.9, andFIG.10, the data encoding circuit110amay receive “01000001(2)” as the (n+1)th data DPn+1[0:7] in the first clock cycle clockcycle1, “10100010(2)” in the second clock cycle clockcycle2, “11101111(2)” in the third clock cycle clockcycle3, and “10100001(2)” in the fourth clock cycle clockcycle4.

In addition, as described with reference toFIG.6, the pattern selector119PS performs an OR operation for the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1, and may output the invert enable signal IEn and/or shift enable signal SEn according to patterns of (n+1_0)th to (n+1_2)th data DPn+1[0:2].

In some implementations, when a value of the OR operation for the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 is “1” and the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are different from each other, the pattern selector119PS may turn off the invert enable signal IEn and set the shift enable signal SEn on the turn-on level. When a value of the OR operation for the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 is “1” and the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are the same, the pattern selector119PS may set the invert enable signal IEn on the turn-on level and turn off the shift enable signal SEn. When a value of the OR operation for the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 is “1” and the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[2] are the same and only the (n+1_0)th data DPn+1[0] is different, the pattern selector119PS may turn off both the invert enable signal IEn and the shift enable signal SEn.

Since the n-th encoded data Dn[0:7] is not latched in the first clock cycle clockcycle1, the first bit operator113and the second bit operator114amay not normally output the XOR result value XORout[0:7] and the XNOR result value XNORout[0:7]. Thus, before the transformation operation of the data transformation logic110DTa, “01000001(2)” input to the input terminal of the plurality of encoding flipflops111may be latched to the output terminal of the plurality of encoding flipflops111based on the clock signal clk. Since the invert operation and the circular shift operation are not performed in the data transformation logic110DTa, the mask unit110MU may turn off (e.g., set to a turn-off level) and output the (n+1)th transformation signal Tsn+1.

“01000001(2)” may be latched as the n-th encoded data Dn[0:7] to the output terminal of the plurality of encoding flipflops111in the second clock cycle clockcycle2, and “10100010(2)” may be latched as the n-th encoded data Dn[0:7] to the input terminal of the plurality of encoding flipflops111. The XOR result value XORout[0:7] may be “11100011(2)” and the XNOR result value XNORout[0:7] may be “11101111(2)”. Accordingly, the first sum value A may be 5 and the second sum value B may be 7.

Thus, the first comparator117may set the (n+1)th invert signal SIn+1 to the turn-on level and output, and the second comparator118may set the (n+1)th shift signal SSn+1 to the turn-on level and output. Since the OR operation result value of the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 is “1”, a value of an (n+1_1)th data DPn+1[1] is “1”, and a value of an (n+1_2)th data DPn+1[1] is “0”, that is they are different from each other, the pattern selector119PS may turn off the invert enable signal IEn and may set the shift enable signal Sen to the turn-on level. The mask unit110MU may set the (n+1)th transformation signal Tsn+1 to the turn-on level and output.

In the second clock cycle clockcycle2, the data transformation logic110DTa receives an activated (n+1)th shift signal SSn+1, and may output “01010001(2)” by circularly shifting “10100010(2)” in 1 bit units in the right direction. The data transformation logic110DTa may provide “01010001(2)” to the input terminal of the plurality of encoding flipflops111. “01010001(2)” input to the input terminal of the plurality of encoding flipflops111may be latched to the output terminal of the plurality of encoding flipflops111based on the clock signal clk.

In the third clock cycle clockcycle3, “01010001(2)” may be latched as the n-th encoded data Dn[0:7] to the output terminal of the plurality of encoding flipflops111, and “11101111(2)” as the (n+1)th encoded data Dn+1[0:7] to the input terminal of the plurality of encoding flipflops111. The XOR result value XORout[0:7] may be “10111110(2)” and the XNOR result value XNORout[0:7] may be “01011001(2)”. Accordingly, the first sum value A may be 6 and the second sum value B may be 4.

Thus, the first comparator117may set the (n+1)th invert signal SIn+1 to the turn-on level and output, and the second comparator118may set the (n+1)th shift signal SSn+1 to the turn-on level and output. Since the OR operation result value of the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 is “1” and the values of the (n+1_0)th data DPn+1[0], the (n+1_1)th data DPn+1[1], and the (n+1_2)th data DPn+1[1] are equally “1”, the pattern selector119PS may set the invert enable signal IEn to the turn-on level and turn off the shift enable signal SEn. The mask unit110MU may set the (n+1)th transformation signal Tsn+1 to the turn-on level and output.

In the third clock cycle clockcycle3, the data transformation logic110DTa receives an activated (n+1)th invert signal SIn+1, and invert “11101111(2)” to “00010000(2)” and output. The data transformation logic110DTa may provide “00010000(2)” to the input terminal of the plurality of encoding flipflops111. “00010000(2)” input to the input terminal of the plurality of encoding flipflops111may be latched to the output terminal of the plurality of encoding flipflops111based on the clock signal clk.

In the fourth clock cycle clockcycle4, “00010000(2)” may be latched as the n-th encoded data Dn[0:7] to the output terminal of the plurality of encoding flipflops111, and “10100001(2)” may be latched as the (n+1)th data DPn+1[0:7] to the input terminal of the plurality of encoding flipflops111. The XOR result value XORout[0:7] may be “10110001(2)” and the XNOR result value XNORout[0:7] may be “00111111(2)”. Accordingly, the first sum value A may be 4 and the second sum value B may be 6.

Thus, the first comparator117may turn off the (n+1)th invert signal SIn+1 and output, and the second comparator118may set the (n+1)th shift signal SSn+1 to the turn-on level and output. Since the OR operation result value of the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 is “1” and the values of the (n+1_1)th data DPn+1[1] and the (n+1_2)th data DPn+1[1] are equally “0” and the value of the (n+1_0)th data DPn+1[0] is “1”, the value of the (n+1_1)th data DPn+1[1] is different. Thus, the pattern selector119PS may turn off both the invert enable signal IEn and the shift enable signal SEn. The mask unit110MU may turn off the (n+1)th transformation signal Tsn+1 and output.

In the fourth clock cycle clockcycle4, the data transformation logic110DTa receive the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1, which are all deactivated, and may maintain “10100001(2)” as it is and output. The data transformation logic110DTa may provide “10100001(2)” to the input terminal of the plurality of encoding flipflops111. “10100001(2)” input to the input terminal of the plurality of encoding flipflop111may be latched to the output terminal of the plurality of encoding flipflops111based on the clock signal clk.

InFIG.9andFIG.10, the data encoding circuit110amay receive the (n+1)th data DPn+1[0:7] in the order of “01000001(2)”, “10100010(2)”, “11101111(2)”, and “10100001(2)” in the first to fourth clock cycles clockcycle1 to clockcycle4. The data encoding circuit110amay output the (n+1)th data DPn+1[0:7] in the order of “01000001(2)”, “01010001(2)”, “00010000(2)”, and “10100001(2)” in the first to fourth clock cycles clockcycle1 to clockcycle4. The data encoding circuit110amay output the (n+1)th transformation signal Tsn+1 in the order of “0(2)”, “1(2)”, “1(2)”, and “0(2)”.

FIG.11toFIG.12are provided for description of an example of the decoding operation of the data decoding circuit.FIG.11toFIG.12illustrate an operation of the data decoding circuit120aofFIG.7when the output encoded data Do[0:7], where m is 7, and the output transformation signal Tso are input continuously four times.

Referring toFIG.7,FIG.11, andFIG.12, the data decoding circuit120amay receive “01000001(2)” and the output encoded data Do[0:7] in a first clock cycle clockcycle1′, “01010001(2)” in a second clock cycle clockcycle2′, “00010000(2)” in a third clock cycle clockcycle3′, and “10100001(2)” in a fourth clock cycle clockcycle4′. The data decoding circuit120amay receive “0(2)” as the output transformation signal Tso in the first clock cycle clockcycle1′, “1(2)” in the second clock cycle clockcycle2, “1(2)” in the third clock cycle clockcycle3′, and “0(2)” in the fourth clock cycle clockcycle4′. The output encoded data Do[0:7] and the output transformation signal Tso received in the first to fourth clock cycles clockcycle1′ to clockcycle4′ may match an (n+1)th encoded data Dn+1[0:7] and an (n+1)th transformation signal Tsn+1 output from the data encoding circuit110ain the first to fourth clock cycles clockcycle1 to clockcycle4 ofFIG.9andFIG.10.

In addition, as described with reference toFIG.7, the pattern selector129PS in some implementations may turn off both the output invert signal SIo and the output shift signal SSo to determine the decoding operation for the output encoded data Do[0:m] as a maintenance operation when the value of the output transformation signal Tso is “0”. When the value of the output transformation signal Tso is “1”, which corresponds to the turn-on level, and the 0th and first output encoded data Do[0:1] are different from each other, the pattern selector129PS turns off the output invert signal SIo and sets the output shift signal SSo to the turn-on level, thereby determining the decoding operation for the output encoded data Do[0:m] as a shift operation. When the value of the output transformation signal Tso is “1” and the 0th and first output encoded data Do[0:1] are equal to each other, the pattern selector129PS sets the output invert signal SIo to the turn-on level to turn off the output shift signal SSo, thereby determining the decoding operation for the output encoded data Do[0:m] as an invert operation. However, the determination operation of the pattern selector129PS is an example, and implementations of the pattern selector129PS having other operations are within the scope of this disclosure.

In the first clock cycle clockcycle1′, the output transformation signal Tso received by the decoding control unit129is “0(2)”, and therefore the pattern selector129PS may turn off both the output invert signal SIo and the output shift signal SSo and output. The data transformation logic120DTa may receive the output invert signal SIo and the output shift signal SSo, which are all turned off.

The data transformation logic120DTa maintains “01000001(2)” as it is as the output encoded data Do[0:7] based on the turned-off output invert signal SIo and the turned-off output shift signal SSo, and output “01000001(2)” and provide it to the input terminal of the plurality of decoding flipflops121. “01000001(2)” input to the input terminal of the plurality of decoding flipflops121may be latched to the output terminal of the plurality of decoding flipflops121based on the clock signal clk.

In the second clock cycle clockcycle2′, “01000001(2)” is latched as preceding decoded data DDo−1[0:7] to the output terminal of the plurality of decoding flipflops121, and “01010001(2)” may be received as the output encoded data Do[0:7]. The output transformation signal Tso received by the decoding control unit129is “1(2)”, the value of the 0th output encoded data Do[0] is “1”, and the value of the first output encoded data Do[1] are “0”, which are different, the pattern selector129PS turns off the output invert signal SIo and sets the output shift signal SSo to the turn-on level and outputs.

The data transformation logic120DTa performs a circular shift operation in 1-bit units in the left direction for “01010001(2)” to output “10100010(2)” based on the output shift signal SSo, and outputs “10100010(2)” at the input terminal of plurality of decoding flipflops121. “10100010(2)” input to the input terminal of the plurality of decoding flipflops121may be latched to the output terminal of the plurality of decoding flipflops121based on the clock signal clk.

In the third clock cycle clockcycle3′, “10100010(2)” is latched as preceding decoded data DDo−1[0:7] to the output terminal of the plurality of decoding flipflops121, and the data decoding circuit120may receive “00010000(2)” as the output encoded data Do[0:7]. The output transformation signal Tso received at the decoding control unit129is “1(2)”, the value of the 0th output encoded data Do[0] is “1”, and the value of the first output encoded data Do[1] is “0”, and thus the 0th output encoded data Do[0] and the output encoded data Do[1] have the same value. The pattern selector129PS may set the output invert signal SIo to the turn-on level and turn off the output shift signal SSo and output.

The data transformation logic120DTa performs an invert operation for “00010000(2)”, which is the output encoded data Do[1] based on the output invert signal Slo, and thus outputs “11101111(2)” as the decoded data DDo[0:7] and provides it to the input terminal of the plurality of decoding flipflops121. “11101111(2)” input to the input terminal of the plurality of decoding flipflops121may be latched to the output terminal of the plurality of decoding flipflops121based on the clock signal clk.

In the fourth clock cycle clockcycle4′, the output transformation signal Tso received at the decoding control unit129is “0(2)”, and thus the pattern selector129PS may turn off both the output invert signal SIo and the output shift signal SSo and output. The data transformation logic120DTa may receive the output invert signal SIo and the output shift signal SSo that are both turned off.

The data transformation logic120DTa may maintain “10100001(2)” as it is as the output encoded data Do[0:7] based on the turned-off output invert signal SIo and the turned-off output shift signal SSo and output “10100001(2)” as the decoded data Do[0:7]. The data transformation logic120DTa may provide the decoded data Do[0:7] to the input terminal of the plurality of decoding flipflops121. “10100001(2)” input to the input terminal of the plurality of decoding flipflops121may be latched to the output terminal of the plurality of decoding flipflops121based on the clock signal clk.

Referring toFIG.6,FIG.8, andFIG.9together, in the first to fourth clock cycles clockcycle1′ to clockcycle4′, the decoded data DDo[0:7] output by the data transformation logic120DTa is output in the order of “01000001(2)”, “10100010(2)”, “11101111(2)”, and “10100001(2)”, and the output order of the decoded data DDo[0:7] is equal to the input order of the (n+1)th data DPn+1[0:7] ofFIG.8andFIG.9.

In the first clock cycle clockcycle1 ofFIG.9, “01000001(2)” output by performing the maintenance operation in the data transformation logic110DTa may be decoded by performing a maintenance operation by the data transformation logic120DTa in the first clock cycle clockcycle1′ inFIG.11.

“01010001(2)”, which is circularly shifted to the right direction by 1 bit unit and output by the data transformation logic110DTa in the second clock cycle clockcycle2 ofFIG.9may be circularly shifted to the left direction by 1 bit unit and decoded by the data transformation logic120DTa in the second clock cycle clockcycle2′ ofFIG.11. However, the shift direction of the circular shift operation performed in the data transformation logic110DTa and the shift direction of the circular shift operation performed in the data transformation logic120DTa are different from each other.

“00010000(2)” inverted and output by the data transformation logic110DTa in the third clock cycle clockcycle3 ofFIG.10may be inverted and decoded by the data transformation logic120DTa in the third clock cycle clockcycle3′ ofFIG.12.

“10100001(2)” output by performing a maintenance operation by the data transformation logic110DTa in the fourth clock cycle clockcycle4 ofFIG.10may be decoded by the maintenance operation performed by the data transformation logic120DTa in the fourth clock cycle clockcycle4′ ofFIG.12.

The reliability of the encoding/decoding operations of the data encoding circuit110and the data decoding circuit120can be increased by setting the determination operation of the pattern selector119PS of the data encoding circuit110and the pattern selector129PS of the data decoding circuit120.

Referring toFIG.9toFIG.12, the clock gating operation in the plurality of encoding clock gating circuits112for the (n+1)th encoded data Dn+1[0:m] in the first to fourth clock cycles clockcycle1 to clockcycle4 is performed 16 times, and the clock gating operation of the plurality of decoding clock gating circuits122for the decoded data DDo[0:m] in the first to fourth clock cycles clockcycle1′ to clockcycle4′ is performed 11 times.

The data encoding circuit110may reduce the number of data toggles in the sequential circuit by performing an encoding operation on data, and particularly the number of the clock gating is increased by increasing the clock gating operation efficiency for continuously input/output data, thereby improving power consumption to pass data.

The data encoding circuit110can improve the operation efficiency of all gate clock circuits CG00to CGTx (refer toFIG.3) disposed in the data channel CW (refer toFIG.3) by efficiently encoding the data pattern in data clock gating operation.

FIG.13is provided for description of the data encoding circuit according to some implementations.FIG.13is provided for description of a part of a data encoding circuit110b. For convenience in description, the data encoding circuit110bwill be described with reference toFIG.13through comparison with the data encoding circuit110aofFIG.6. In particular, a data transformation unit110DTb, which is different from the data transformation unit110DTa ofFIG.6, and a second bit operator114b, which is different from the second bit operator114aofFIG.6, will be mainly described.

Each of the 0th to m-th transformation MUXs TM′_0to TM′_m may receive a result value of each of the 0-th to m-th transformation XOR operators TX_1to TX_m and data circularly shifted by 2 bit units in the right direction with respect to the (n+1)th data DPn+1[0:m], and may receive the (n+1)th shift signal SSn+1 as a selection signal. Each of the 0th to m-th transformation MUXs TM′_0to TM′_m may output any one of the result values of the 0-th to m-th transformation XOR operators TX_1to TX_m and the circularly shifted data based on the (n+1)th shift signal SSn+1.

For example, the 0th transformation MUX TM′_0may receive a result value of the 0th transformation XOR operator TX_0and the (n+1_2)th data DPn+1[2], and may receive the (n+1)th shift signal SSn+1 as a selection signal. When the received (n+1)th shift signal SSn+1 is “0”, the 0th transformation MUX TM′_0outputs the result value of the 0th transformation XOR operator TX_0and provides to the 0th encoding flipflop111_0. When the received (n+1)th shift signal SSn+1 is “1”, the 0th transformation MUX TM′_0may output the (n+1_2)th data DPn+1[2] and provide to the 0th encoding flipflop111_0.

In addition, the m-th transformation MUX TM′_m may receive a result value of the m-th transformation XOR operator TX_m and the (n+1_1)th data DPn+1[1], and receive the (n+1)th shift signal SSn+1 as a selection signal. When the (n+1)th shift signal SSn+1 is “0”, the m-th transformation MUX TM′_m may output a result value of the m-th transformation XOR operator TX_m and provide to the m-th encoding flipflop111_m. When the (n+1)th shift signal SSn+1 is “1”, the 0-th transformation MUX TM′_m may output the (n+1_1)th data DPn+1[1] and provide to the m-th encoding flipflop111_m.

The data transformation unit110DTb may output the (n+1)th encoded data Dn+1[0:m] on which any one of the maintenance operation, the invert operation, or the circular shift operation is performed with respect to the (n+1)th data DPn+1[0:m] based on the (n+1)th invert signal SIn+1 and the (n+1)th shift signal SSn+1 and provide to the plurality of encoding flipflops111. In particular, the circular shift operation of the data transformation unit110DTb may be shifted to by a 2-bit unit.

The second bit operator114bmay include 0th to m-th XNOR operators114XN′_0to114XN′_m. The 0th to m-th XNOR operators114XN′_0to114XN′_m may perform an XNOR bit operation on the n-th encoded data Dn[0:m] latched to the output terminal of the 0th to m-th encoding flipflops111_0to111_mand data circularly shifted by the 2-bit unit in the right direction with respect to the (n+1)th data DPn+1[0:m].

For example, the 0th XNOR operator114XN′_0may perform an XNOR operation for the (n_0)th encoded data Dn[0] latched to the 0th encoding flipflop111_0and the (n+1_1)th data DPn+1[1] input to the input terminal of the first encoding flipflop111_1, and output and provide an 0th XNOR result value XNORout[0] to the second adder116. In addition, the m-th XNOR operator114XN′_m may perform an XNOR operation with respect to an (n_m)th encoded data Dn[m] latched to the output terminal of the m-th encoding flipflop111_mand an (n+1_1)th data DPn+1[1] input to the input terminal of the first encoding flipflop111_1, and output and provide an m-th XNOR result value XNORout[m] to the second adder116.

The XNOR result values XNORout[0:m] of the 0th to m-th XNOR operators114XN′_0to114XN′_m may be transmitted to the second adder116through the 0-th to m-th shift loop prevention buffers SLB_0to SLB_m. When the enable signal EN is input to the 0-th to m-th shift loop prevention buffers SLB_0to SLB_m, the XNOR result value XNORout[0:m] may be input to the second adder116.

FIG.14is provided for description of the data decoding circuit according to some implementations.FIG.14is provided for description of a data decoding circuit120b. For convenience in description, the data decoding circuit120bofFIG.14will be described through comparison with the data decoding circuit120aofFIG.7. In particular, a data transformation unit120DTb, which is different from the data transformation unit120DTa ofFIG.7, will be mainly described.

Referring toFIG.7andFIG.14, in some implementations, the data transformation unit120DTb may include 0th and m-th decoding XOR operators DX_0to DX_m and 0th to m-th decoding MUXs DM′_0to DM′_m.

Each of the 0th to m-th decoding MUXs DM′_0to DM′_m may receive a result value of each of the 0th to m-th decoding XOR operators DX_0to DX_m and data circularly shifted by a 2-bit unit in the left direction for the output encoded data Do[0:m], and may receive the output shift signal SSo as a selection signal (some SSo connections are omitted fromFIG.14for clarity). Each of the 0th to m-th decoding MUXs DM′_0to DM′_m may output any one of a result value of each of the 0th and m-th decoding XOR operators DX_0to DX_m and the circularly shifted data based on the output shift signal SSo.

For example, the 0th decoding MUX DM′_0may receive a result value of the 0th decoding XOR operator DX_0and the m-th output encoded data Do[m−1], and may receive the output shift signal SSo as a selection signal. When the output shift signal SSo is “0”, the 0th decoding MUX DM′_0may output a result value of the 0th decoding XOR operator DX_0and provide to the 0th decoding flipflops121_0. When the output shift signal SSo is “1”, the 0th decoding MUX DM′_0may output the m-th output encoded data Do[m-1] and provide to the 0th decoding flipflops121_0.

In addition, the first decoding MUX DM′_1may receive a result of the first decoding XOR operator DX_m and the 0th output encoded data Do[m], and may receive the output shift signal SSo as a selection signal. When the output shift signal SSo is “0”, the first decoding MUX DM′_1may output the result value of the first decoding XOR operator DX_m and provide to the first decoding flipflops121_1. When the output shift signal SSo is “1”, the first decoding MUX DM′_1may output the 0th output encoded data Do[m] and provide to the first decoding flipflops121_1.

FIG.15is provided for description of the data encoding circuit according to some implementations.FIG.15is provided for description of a data transformation unit110DTc of a data encoding circuit110c. For convenience in description, the data transformation unit110DTc ofFIG.15will be described through comparison with the data transformation unit110DTa ofFIG.6.

The data transformation unit110DTc may include 0th to m-th transformation MUXs TM″_0to TM″_m.

Each of the 0th to m-th transformation MUXs TM″_0to TM″_m may receive bits of each of (n+1)th data DPn+1[0:m], bits of each of (n+1)th invert data DIn+1[0:m] with respect to the (n+1_0)th data DPn+1[0], and bits circularly shifted in 1-bit units in the right direction for each of the (n+1)th data DPn+1[0:m], and may receive the (n+1)th shift signal SSn+1 and the (n+1)th invert signal SIn+1 as selection signals. Each of the 0th to m-th transformation MUXs TM″_0to TM″_m may output any one of the (n+1)th data DPn+1[0:m], the (n+1)th invert data DIn+1[0:m], or the circularly shifted data based on a combination of the (n+1)th shift signal SSn+1 and the (n+1)th invert signal SIn+1.

For example, the 0th transformation MUX TM″_0may receive the (n+1_0)th data DPn+1[0], the (n+1)th invert data DIn+1[0], and the (n+1_1)th data DPn+1[1], and may receive the (n+1)th shift signal SSn+1 and the (n+1)th invert signal SIn+1 as selection signals. Through the combination of the (n+1)th shift signal SSn+1 and the (n+1)th invert signal SIn+1, the 0th transformation MUX TM″_0may output any one of the (n+1_0)th data DPn+1[0], the (n+1)th invert data DIn+1[0], and the (n+1_1)th data DPn+1[1] as the (n+1_0)th encoded data Dn+1[0].

Some examples have been described in detail above, but the scope of the present disclosure is not limited thereto, and numerous variations and improvements made by a person of an ordinary skill in the art using the concepts of the present disclosure may also fall within the scope of the present disclosure.