Method for producing a moisture sensor at the wafer level and moisture sensor

In accordance with an embodiment, a method for producing a moisture sensor includes providing a substrate arrangement, applying a sensor structure, applying a first cover layer on the sensor structure, locally removing the planar cover layer arrangement to expose portions of an insulation layer, applying a third cover layer on the exposed portions of the insulation layer, exposing the planar cover layer arrangement covering the sensor structure, and applying a moisture-absorbing layer element on the planar cover layer arrangement covering the sensor structure to obtain the moisture sensor.

This application claims the benefit of German Patent Application No. 102018220169.2, filed on Nov. 23, 2018 which application is hereby incorporated herein by reference.

TECHNICAL FIELD

Exemplary embodiments relate to a method for producing a moisture sensor at the wafer level and to a corresponding moisture sensor for measuring the moisture in the ambient atmosphere.

BACKGROUND

The recording of environmental and/or ambient parameters in the ambient atmosphere is gaining ever greater importance in the implementation of corresponding sensors inside mobile devices, but also for use in home automation, such as for example smart homes, and for example also in the automobile sector. With the more comprehensive use of sensors, however, there is in particular also a need to be able to produce corresponding sensors as straightforwardly and therefore economically as possible, although the resulting reliability and accuracy of the sensors are nevertheless to be maintained.

In the monitoring of relative humidity in the environment of the sensor, or of the device in which the sensor is installed, the combination of sensor structure and application specific integrated circuits (ASICs) is often problematic in terms of an economical production process flow. This is relevant particularly for electronic consumer devices, since in this case sensors that are as economical as possible to produce, such as for example sensors for measuring relative humidity, are intended to be used.

SUMMARY

A method100,100′ for producing a moisture sensor300at the wafer level comprises the following steps: providing105a substrate arrangement200, which comprises a semiconductor substrate202, for example with components204arranged thereon, and having a metallization layer stack206arranged on the semiconductor substrate202, the metallization layer stack206comprising a multiplicity of metallization structures210,210-1embedded in an insulation material208, an insulation layer212being arranged on the metallization layer stack206; applying no a sensor structure214having a multiplicity of conductive sensor structure elements214-1,214-2on the insulation layer212of the metallization layer stack206; applying115a first cover layer216on the sensor structure214and uncovered sections of the insulation layer212, the first cover layer216covering the conductive sensor structure214, and a section, covering the conductive sensor structure214, of the first cover layer216being configured in a planar fashion in order to form a planar cover layer arrangement220; locally removing125the planar cover layer arrangement220, the sensor structure214remaining covered with the planar cover layer arrangement220; applying130a third cover layer222on the exposed insulation layer212and the planar cover layer stack220covering the sensor structure214; exposing135the planar cover layer stack220covering the sensor structure214; and applying145a moisture-absorbing layer element232on the planar cover layer stack220covering the sensor structure in order to obtain the moisture sensor300.

According to one exemplary embodiment, the method100furthermore comprises the following step: applying120a second cover layer218on the planar first cover layer216, in order to obtain the planar cover layer arrangement220as a planar cover layer stack220having the first and second cover layers216,218on the sensor structure214.

According to one exemplary embodiment, the method100furthermore comprises the following step: planarizing the first cover layer, in order to form in a planar fashion at least the section216-1, covering the sensor structure214, of the first cover layer216.

According to one exemplary embodiment, the method100′ furthermore comprises the following step: arranging a sacrificial layer structure217between the neighboring sensor structure elements214-1,214-2of the sensor structure214after the application of the first cover layer216, in order to obtain a cavity region234between the neighboring sensor structure elements214-1,214-2of the sensor structure214.

According to one exemplary embodiment, the method100,100′ furthermore comprises the following step: applying140a passivation layer arrangement, on the planar cover layer arrangement covering the sensor structure214, the step135of exposing the planar cover layer arrangement covering the sensor layer structure214being carried out through the passivation layer arrangement and the third cover layer222.

According to one exemplary embodiment, during the application110of the sensor structure214having a multiplicity of conductive sensor structure elements214-1,214-2, a reference electrode structure215having a multiplicity of conductive reference structure elements215-1,215-2is furthermore applied on the insulation layer212.

According to one exemplary embodiment, the reference electrode structure215is embedded in the third cover layer after the application of the third cover layer.

According to one exemplary embodiment, the reference electrode structure215is formed as a metallization structure embedded in the metallization layer stack.

According to one exemplary embodiment, the metallization layer stack206comprises next to the sensor structure214a metallization structure210-1, which is configured as a shielding element for the sensor structure214in order to reduce a parasitic capacitance.

According to one exemplary embodiment, the method100furthermore comprises the following step after the application of the third cover layer222: applying further insulation layer structures, metallization layer structures and/or component structures on one another or on the third cover layer222.

According to one exemplary embodiment, during the step of applying further insulation structures, metallization layer structures and/or component structures, a rewiring layer, an insulation layer, an uppermost metallization layer and/or a passivation layer arrangement are applied and structured in such a way that the planar cover layer arrangement220covering the sensor structure214is exposed.

According to one exemplary embodiment, the moisture-absorbing layer element232comprises a polymer material.

According to one exemplary embodiment, the sensor structure elements214-1,214-2of the sensor structure214comprise copper or aluminum with a thickness of ≤500 nm or about 200 nm and a lateral spacing of about 100 nm.

According to one exemplary embodiment, the sensor structure elements214-1,214-2are arranged in an interdigital arrangement with respect to one another.

According to one exemplary embodiment, the components204arranged on the semiconductor substrate202are formed during an FEOL treatment process of the semiconductor substrate202.

According to one exemplary embodiment, the FEOL components comprise components based on CMOS technology.

According to one exemplary embodiment, the metallization layer stack206is formed during a BEOL treatment process of the substrate arrangement200.

According to one exemplary embodiment, the metallization layer stack206comprises a multiplicity of conductive track structures210in different planes M #. in the insulation material208.

A moisture sensor300,300′ comprises a substrate arrangement200, which comprises a semiconductor substrate202with components204arranged thereon, and a metallization layer stack206arranged on the semiconductor substrate202, the metallization layer stack206comprising a multiplicity of metallization structures embedded in an insulation material208, an insulation layer212being arranged on the metallization layer stack206of the substrate arrangement200; a sensor structure214having a multiplicity of conductive sensor structure elements214-1,214-2on the insulation layer212of the metallization layer stack206, a planar cover layer arrangement220being arranged on the sensor structure214; and a moisture-absorbing layer element232on the planar cover layer arrangement220covering the sensor structure214.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Before exemplary embodiments of the present concept are explained in more detail below with the aid of the drawings, it is pointed out that elements, objects, functional units and/or method steps which are identical, functionally equivalent or have the same effect in the various figures are provided with the same references, so that the description of these elements, objects, functional units and/or method steps presented in different exemplary embodiments is mutually interchangeable and/or may be applied to one another.

Various embodiments are directed an effective production of moisture sensors. Various embodiment moisture sensors can be integrated in a straightforward manner into existing semiconductor wafer treatment processes with which reliably and accurately operating humidity sensors can be obtained.

A basic sequence or flow diagram of a method100for producing a moisture sensor300at the wafer level according to one exemplary embodiment will now be described below with reference toFIG. 1.

First, a substrate arrangement200is now provided inFIG. 1in the production method100at step105. The substrate arrangement200comprises a semiconductor substrate202having for example components204arranged thereon, such as for example active or passive semiconductor components, and furthermore a metallization layer stack206arranged on the semiconductor substrate202. The metallization layer stack206comprises for example a multiplicity of metallization structures210embedded in an insulation material208, an insulation layer212, for example of a dielectric material, being arranged, for example as the uppermost layer, on the metallization layer stack206.

The semiconductor substrate202may for example be a semiconductor wafer processed in an FEOL process (FEOL=front end of line), such as for example a silicon wafer having an integrated circuit arrangement or ASIC (ASIC=application specific integrated circuit), or in general having CMOS components, on which the metallization layer stack or wiring layer stack206is applied in a BEOL process (BEOL=back end of line). The metallization or wiring layer stack206is, for example, provided in order to provide wiring planes for the FEOL components204, i.e. to provide predetermined connections between FEOL components and/or connections to pad contacts on the upper side of the metallization layer stack206.

The metallization structures210embedded in the insulation material208comprise for example a metal or metal alloy material, such as for example copper, aluminum, etc. The insulation layer212comprises for example a dielectric material, such as for example silicon nitride SiN. InFIG. 1, the embedded metallization structures210are denoted for example by M4as the fourth and uppermost metal level of the metallization layer stack206.

In step110, a conductive sensor structure214having a multiplicity of sensor structure elements214-1,214-2is now applied on the insulation layer212of the metallization layer stack206. The sensor structure elements214-1,214-2may be arranged in a so-called interdigital arrangement with respect to one another, which may for example be read out capacitively. The sensor structure elements214-1,214-2of the conductive sensor structure214comprise for example a metal or a metal alloy, such as for example copper, aluminum, etc. The sensor structure elements214-1,214-2have, for example, a thickness of ≤500 nm or about 200 nm. For example, the sensor structure elements214-1,214-2may have a thickness d214(vertically with respect to a plane of the main surface region of the insulation layer212) in a range of from 100 nm to 500 nm, from 150 nm to 250 nm, or of about 200 nm. Furthermore, the sensor structure elements214-1,214-2may be laterally separated with a spacing a214of about 50 nm to 150 nm or of about 100 nm (with respect to the plane of the main surface region212-A of the insulation layer212).

As is furthermore represented by way of example in step110, in the metallization layer stack206there may be arranged next to (=below inFIG. 1) the conductive sensor structure214in the insulation material208, opposite to the sensor structure214, an optional metallization layer structure210-1, which may be configured as a shielding element for the sensor structure214in order to reduce a parasitic capacitance CPAR.

The conductive sensor structure214may for example comprise a metal, such as for example aluminum, or a metal alloy, aluminum for example also being used as the material for a redistribution layer and/or as the material for contact pads (=pad material) for current CMOS technologies.

In step115, a first cover layer (=passivation layer)216is now applied onto the sensor structure214and the uncovered regions of the insulation layer212of the metallization layer stack206. The first cover layer216in this case covers the sensor structure214, a section216-1, covering the sensor structure214, of the first cover layer216being configured in planar or (as far as possible) topology-free fashion.

To configure at least the section216-1, covering the sensor structure214, of the first cover layer216in a planar fashion, the first cover layer216is planarized, in which case a corresponding planarization process may be carried out by means of a CMP process (CMP=chemical-mechanical polishing).

In semiconductor production processes, chemical-mechanical polishing, or chemical-mechanical planarization, refers to a polishing method in wafer treatment in order to erode thin layers uniformly, i.e. to obtain a maximally planar or topology-free surface thereof.

The first cover layer216is applied, for example as silicon dioxide material (SiO2) or as silicon nitride material (Si3N4), onto the conductive sensor structure214and further uncovered regions of the insulation layer212on the substrate arrangement200, and subsequently planarized, for example by means of a CMP process or another planarization process, in order to obtain a maximally planar or topology-free surface region216-1of the first cover layer216. The final thickness d216(after the planarization process) of the first cover layer216is greater, for example by a factor of from 1.5 to 2.5, than the thickness d214of the electrically conductive sensor structure elements (detection electrodes)214-1,214-2of the electrically conductive sensor structure214.

In an optional step120, a second cover layer218may now be applied on the planar or planarized first cover layer216in order to obtain a planar cover layer stack or a planar layer arrangement220on the conductive sensor structure214and further, or the remaining, regions of the insulation layer212.

As the following comments will also show, the optionally applied second cover layer218may be effective as a thin etch stop layer during one of the subsequent process steps. The second cover layer218comprises for example a dielectric material, such as for example silicon nitride (Si3N4).

Since the second cover layer218is only applied optionally on the planar or planarized first cover layer216, for example if this is advantageous or necessary in terms of process technology, according to one exemplary embodiment the planar cover layer arrangement220may comprise the planar or planarized first cover layer216and, according to a further exemplary embodiment, it may comprise the planar or planarized first cover layer216and the second cover layer218applied thereon as a planar cover layer stack (220).

In step125, the planar cover layer arrangement220having the first and optionally the second cover layer216,218is locally removed, the conductive sensor structure214remaining covered with the planar cover layer arrangement220. The planar cover layer arrangement220has a width a220(parallel to the plane of the main surface region212-A of the first insulation layer212) which is, for example, greater than the width a214of the electrically conductive sensor structure214. The planar cover layer stack220is therefore configured in order to cover the sensor structures as well. For the signal generation, the stray capacitance of the electrodes is used by this special construction. The latter changes as a function of the moisture.

In step130, a third cover layer (=further passivation layer)222is applied onto the uncovered or exposed sections or surface regions of the insulation layer112, and furthermore onto the planar cover layer arrangement220having the electrically conductive sensor structure214embedded therein. The third cover layer222may for example comprise a dielectric material, such as for example a silicon dioxide material SiO2having a thickness in a range of from 500 nm to 1500 nm, or of about 1000 nm.

In step135, the planar cover layer arrangement220covering the sensor structure214is now exposed through the third cover layer (=further passivation layer)222, in which case, for example, the optional layer218of the layer arrangement220may be configured as an etch stop layer for the exposure step135, carried out by means of an etching process, of the planar cover layer stack220covering the sensor structure214.

According to further optional exemplary embodiments, further insulation structures, metallization layer structures and/or component structures may be arranged on one another, or on the fourth cover layer, after the step130of applying the third cover layer222. Thus, for example, in the optional step of applying further insulation layer structures, metallization layer structures and/or component structures on the third cover layer222, a redistribution layer, one or more further insulation layers, an uppermost metallization layer and/or at least one passivation layer may be applied and (subsequently, for example in step135) structured in such a way that the planar cover layer arrangement220covering the sensor structure is uncovered. The optional further insulation structures, metallization layer structures and/or component structures are thus applied and structured in such a way that they are removed at the location of the moisture sensor300, i.e. above the cover layer arrangement220, and expose to the environment the planar cover layer arrangement220covering the conductive sensor structure214.

In a step145, a moisture-absorbing layer element232is applied on the planar cover layer arrangement220covering the conductive sensor structure, in order to obtain the moisture sensor300.

According to one exemplary embodiment of the present concept100for producing the moisture sensor300at the wafer level, the moisture-absorbing material232is applied after the concluding treatment of the substrate arrangement200. The moisture-absorbing layer structure232may for example comprise a moisture-absorbing material, such as for example a material based on a polymer, such as for example photoimide, SU-8, silicone etc., this list of materials being intended to be regarded only as exemplary and not as exhaustive.

The moisture-absorbing material232may optionally be structured and removed outside the desired moisture sensor element300.

For the moisture detection, for example, the change in the capacitance of the sensor electrodes214-1,214-2caused by the applied stray electric field as a function of the moisture content inside the moisture-absorbing material232is used.

A basic sequence diagram of a method or a process100′ for producing a moisture sensor300′ at the wafer level according to a further exemplary embodiment will now be described below on the basis ofFIG. 2.

The following comments refer essentially to the method steps differing fromFIG. 1, the other comments in relation to the method100ofFIG. 1being similarly applicable to the method100′ ofFIG. 2.

As is represented in step105of the method100′, the substrate arrangement200is again provided. The substrate arrangement200again comprises a semiconductor substrate202having for example components204arranged thereon, such as for example active or passive semiconductor components, and furthermore a metallization layer stack206arranged on the semiconductor substrate202. The metallization layer stack206comprises for example a multiplicity of metallization structures210embedded in an insulation material208, an insulation layer212, for example of a dielectric material, being arranged, for example as the uppermost layer, on the metallization layer stack206.

In step no, a conductive sensor structure214having a multiplicity of sensor structure elements214-1,214-2is applied on the insulation layer212of the metallization layer stack206. Furthermore, in step no (before the step of applying the first cover layer216on the conductive sensor structure214), a sacrificial layer or a sacrificial layer structure217is arranged between neighboring sensor structure elements214-1,214-2of the conductive sensor structure214. The arranging of the sacrificial layer structure217between neighboring sensor structure elements214-1,214-2may, for example, be carried out according to two different process options.

According to a first optional process option, the conductive sensor structure214having the multiplicity of sensor structure elements214-1,214-2may initially be applied on the insulation layer212, whereupon the sacrificial layer structure217is arranged between the neighboring sensor structure elements214-1,214-2, to this end the sacrificial layer217being for example applied onto the desired regions and, for example, a polishing process, for example a CMP process, subsequently being carried out in order to configure the sacrificial layer structure217flush with the height d214of the conductive sensor structure214.

According to a second optional process optional, the sacrificial layer217may initially be applied and structured, whereupon the conductive sensor structure214having the multiplicity of sensor structure elements214-1,214-2is arranged adjacent to the sacrificial layer structure217, so that the sacrificial layer structure217is arranged between the neighboring sensor structure elements214-1,214-2of the conductive sensor structure214. Subsequently, a planarization or polishing step, for example a CMP method, may in turn be carried out in order to obtain a flush configuration of the sacrificial layer structure217and of the conductive sensor structure214having the thickness d214.

According to the exemplary embodiment represented inFIG. 2of the method100′ for producing the moisture sensor300, the conductive sensor structure214therefore comprises the sacrificial layer structure217arranged between the multiplicity of sensor structure elements214-1,214-2.

In step115, the first cover layer (=passivation layer)216is again arranged on the conductive sensor structure214having the sacrificial layer structure217arranged there and on the insulation layer212of the metallization layer stack206, the first cover layer or passivation layer216covering the conductive sensor structure214, and the section216-1, covering the sensor structure214, of the first cover layer being configured in a planar fashion. Now, in step120, the second cover layer (=etch stop layer)218is in turn applied onto the planar first cover layer216in order to obtain the cover layer arrangement220on the sensor structure214, the section220-1, covering the sensor structure214, of the cover layer arrangement220again being configured in a planar fashion. This is achieved since the sacrificial layer structure217arranged between neighboring sensor structure elements214-1,214-2forms a flush, or planar, surface with the conductive sensor structure214.

According to one exemplary embodiment, the cover layer arrangement220may comprise next to the planar section220-1of the cover layer arrangement220on the sensor structure214a step or a transition, which is based on the step existing between the insulation layer112and the conductive sensor structure114applied thereon with the sacrificial layer217arranged therebetween.

In step125, the first and second cover layers216,218are in turn locally removed, the sensor structure214having the planar section220-1of the cover layer arrangement220remaining covered.

In step127, the sacrificial layer structure217is now at least partially or even fully removed between the neighboring sensor structure elements214-1,214-2of the sensor structure214, in order to obtain cavities or free spaces234between the neighboring sensor structure elements214-1,214-2of the conductive sensor structure214.

The further method steps130,135,140(optional) and145ofFIG. 1may be carried out likewise after step127ofFIG. 2.

Further exemplary embodiments of the method100,100′ for producing a moisture sensor300at the wafer level will now be discussed below.

Furthermore, further optional method or process steps of the method100,100′ or optional supplements to the method steps of the method100,100′ are represented by way of example inFIGS. 1 and 2.

Thus, in the production method100,100′, in step110of applying the conductive sensor structure214having the multiplicity of sensor structure elements214-1,214-2on the insulation layer212, an optional reference electrode structure215having a multiplicity of reference electrode elements215-1,215-2may furthermore be applied on the insulation layer212. According to one exemplary embodiment, the reference electrode structure215is embedded in the third cover layer222during the application of the third cover layer222(and remains embedded therein).

According to one exemplary embodiment of the method100,100′, both the conductive sensor structure214, which is sensitive to a moisture change, and the reference electrode structure215, which is insensitive to a moisture change because of being accommodated in the “thick” third cover layer222, may thus be produced inside the same production process module, for example after the standard CMOS metallization process and before the pad fabrication module. According to one exemplary embodiment, the reference electrodes215-1,215-2of the reference electrode structure215are therefore covered by, or embedded in, the third cover layer222, which is for example configured as a thick passivation layer comprising a silicon dioxide material having a thickness of about 1000 nm, in order to prevent or suppress moisture sensitivity of the reference electrode structure215. The third cover layer222may be configured as a cover layer arrangement or passivation layer arrangement, for example having a multiplicity of different insulation layers, such as for example a silicon dioxide layer SiO2and a silicon nitride layer Si3N4(for example as a stack), or a single passivation or cover layer222or also from a single passivation layer comprising a silicon dioxide material SiO2or a silicon nitride material Si3N4, in which case, for example, a final cover layer or a concluding cover layer stack may furthermore also be provided on the third cover layer222.

According to one exemplary embodiment, the two electrode structures, i.e. the measuring electrode structure214and the reference electrode structure215, may therefore also be produced at different successive times and/or during different process steps in the overall process flow.

The optional reference electrode structure215is shown by way of example inFIGS. 1 and 2.

According to a further exemplary embodiment, as an alternative or in addition to the reference electrode structure215, a reference electrode structure210may also be configured as a metallization structure210embedded in the metallization layer stack206. As is represented by way of example inFIGS. 1 and 2of the method100,100′, the optional reference electrode structure210may, for example, be formed in the uppermost metallization plane M4(=metallization plane4) of the metallization layer stack206and, for example, comprise copper, aluminum, etc. or another metal, or another metal alloy, as the conductive material.

According to one exemplary embodiment, the metallization layer stack206may furthermore comprise, adjacent to the conductive sensor structure, for example in the metallization plane M4, an optional metallization layer structure210-1which is configured as an electrostatic shielding element for the sensor structure214in order to reduce the parasitic capacitance CPAR of the sensor structure214.

Further optional exemplary method steps of the method100,100′, which may be equally applied both to the production method100represented inFIG. 1and to the production method100′ represented inFIG. 2, will now be presented below with the aid ofFIG. 3.

According to one exemplary embodiment, after the step130of applying the third cover layer222, further insulation layer structures, metallization layer structures and/or component structures may furthermore be applied in a structured fashion on one another or on the fourth cover layer222.

As is now represented inFIG. 3in step137, optional metallization regions224made of a metal or a metal alloy, such as for example aluminum, may for example be applied. These additional metallization structures224may, for example, have a thickness in a range of from 1000 nm to 1500 nm and, for instance, of 1200 nm.

In step “140”, an upper passivation layer arrangement230may furthermore now be applied onto the further insulation structures, metallization structures and/or component structures applied in step137, such as for example the optional metallization structures224, onto the uncovered main surface region of the substrate arrangement200, i.e. onto the uncovered process surface of the substrate arrangement200, the passivation layer arrangement230covering the applied further insulation layer structures, metallization structures and/or component structures on the third cover layer222as well as the uncovered sections or surface regions of the third cover layer222. The upper passivation layer arrangement230may for example comprise a first passivation layer236, such as for example a silicon dioxide material SiO2with a thickness of between 300 and 600 nm, and of about 450 nm, and a second passivation layer238arranged thereover, such as for example comprising a silicon nitride material Si3N4, with a thickness of between 300 and 500 nm, and of about 400 nm.

In step135, the planar cover layer arrangement220covering the sensor structure214is now exposed, in which case the optional layer218of the layer stack220may be configured for example as an etch stop layer for the exposing step135, carried out by means of an etching process, of the planar cover layer stack220covering the sensor structure214.

In a step143, a further passivation layer242, which comprises for example a silicon nitride material Si3N4with a thickness of between 30 and 100 nm, and of about 50 nm, may now optionally be applied onto the remaining process surface of the substrate arrangement200. The optional further passivation layer242may, for example, be arranged also on the planar cover layer arrangement220covering the conductive sensor structure214.

In step145, a moisture-absorbing layer element232is applied on the planar cover layer arrangement220covering the conductive sensor structure and on the optional further passivation layer242, in order to obtain the moisture sensor300,300′.

According to one exemplary embodiment, the components204, for example CMOS components, arranged on the semiconductor substrate may be formed during an FEOL treatment process of the semiconductor substrate202. The FEOL components204can comprise active and/or passive components based on CMOS technology.

According to one exemplary embodiment, the metallization layer stack206may be formed during a BEOL treatment process of the substrate arrangement200. According to one exemplary embodiment, the metallization layer stack206comprises a multiplicity of conductive track structures210,210a,210betc. in different planes in the insulation material208.

A moisture sensor300,300′ according to one exemplary embodiment will now be described below with the aid ofFIGS. 4aand 4bin a basic, or schematic, cross-sectional representation.

As is represented by way of example inFIGS. 4aand 4b, the moisture sensor300,300′ comprises a substrate arrangement200, which comprises a semiconductor substrate202with components204arranged thereon, and a metallization layer stack206arranged on the semiconductor substrate202, the metallization layer stack206comprising a multiplicity of metallization structures embedded in an insulation material208, and an insulation layer212being arranged on the metallization layer stack206of the substrate arrangement200.

The moisture sensor300,300′ furthermore comprises a sensor structure214having a multiplicity of conductive sensor structure elements214-1,214-2on the insulation layer212of the metallization layer stack206, a planar cover layer arrangement220being arranged on the sensor structure214, and furthermore a moisture-absorbing layer element232on the planar cover layer stack220covering the sensor structure214. The planar cover layer arrangement220furthermore comprises a second cover layer216or, as a layer stack, a second and third cover layer216,218on the sensor structure214.

According to one exemplary embodiment, the planar cover layer arrangement220comprises the first cover layer216, which covers the conductive sensor structure214, a section, covering the conductive sensor structure214, of the first cover layer216being configured in a planar fashion in order to form the planar cover layer arrangement220.

According to a further exemplary embodiment, the planar cover layer arrangement220comprises a second and third cover layer216,218on the sensor structure214, in order to obtain the planar cover layer arrangement220as a planar cover layer stack220having the first and second cover layers216,218on the sensor structure214, a material of the first cover layer being arranged in an intermediate region between the neighboring conductive sensor structure elements214-1,214-2of the sensor structure, or the intermediate space between neighboring conductive sensor structure elements214-1,214-2of the sensor structure214being left free as a cavity region.

As is represented by way of example inFIG. 4a, the moisture sensor300comprises the material of the first cover layer216in an intermediate region between the neighboring conductive sensor structure elements214-1,214-2of the sensor structure214.

As is represented by way of example inFIG. 4b, the moisture sensor300′ comprises the intermediate region is left free is as a cavity region234between the neighboring conductive sensor structure elements214-1,214-2of the sensor structure214.

According to one exemplary embodiment, the moisture sensor300,300′ furthermore comprises a passivation layer arrangement on the planar cover layer arrangement220covering the layer structure.

According to one exemplary embodiment, the moisture sensor300,300′ furthermore comprises a third cover layer222on uncovered regions of the insulation layer212and of the planar cover layer arrangement220of the sensor structure214.

According to one exemplary embodiment, the moisture sensor300,300′ comprises a reference electrode structure215having a multiplicity of reference structure elements215-1,215-2on the insulation layer212.

According to one exemplary embodiment, the reference electrode structure is embedded in the third cover layer. According to one exemplary embodiment, the reference electrode structure is configured as a metallization structure embedded in the metallization layer stack206.

According to one exemplary embodiment, the metallization layer stack206comprises next to the sensor structure214a metallization structure210-1, which is configured as a shielding element for the sensor structure214in order to reduce a parasitic capacitance.

The sensor region of the moisture sensor300′ will now be described below with the aid ofFIG. 5in the form of a schematic cross-sectional view with a basic representation of the resulting components of the acting electric field.

As is represented inFIG. 5, the conductive sensor structure214comprises the multiplicity of sensor structure elements214-1,214-2on the first cover layer212of the metallization layer stack206, a planar cover layer arrangement220being arranged on the conductive sensor structure214. Furthermore, the moisture-absorbing layer element232is arranged on the planar cover layer arrangement220covering the conductive sensor structure. As is furthermore represented by way of example inFIG. 5, the intermediate regions between the sensor structure elements214-1,214-2are configured as cavities234, the metallization structure210-1effective as a shielding element furthermore being arranged next to the conductive sensor structure214in the metallization layer stack206.

During operation of the moisture sensor300′, a potential difference with a voltage of +V relative to 0 volts is for example now applied between the sensor structure elements214-1,214-2of the conductive sensor structure240. The resulting electric field, or stray field, respectively propagates perpendicularly out from the first sensor structure element214-1and perpendicularly back into the second sensor structure element214-2and with a field line density corresponding to the potential difference between the two sensor structure elements214-1,214-2.

The component of the overall field which passes through the moisture-absorbing layer element232is referred to as the stray field. In other words, the overall capacitance CGESof the sensor structure214is given by the sum of the stray capacitance CSTRAYand the parasitic capacitance CPAR.

The electric field lines passing through the moisture-absorbing layer element232now contribute to the stray capacitance CSTRAYand therefore to the measurement signal. The change in the overall capacitance ΔCGis now a function of the relative humidity, or the change in the relative humidity, which has been absorbed in the moisture-absorbing layer element232. The signal-to-noise ratio (SNR) of the moisture sensor300,300′ is now proportional to the ratio between the change in the overall capacitance ΔCGto the overall capacitance CG.

The signal-to-noise ratio is therefore all the greater, the smaller the parasitic capacitance CPARcan be kept. The parasitic capacitance may, for example, be reduced by producing the cavities234with a material, such as for example air, having a relatively low relative dielectric constant εr, the relative dielectric constant of air being about 1 (εr≈1).

Furthermore, the metallization structure210-1may contribute to further reducing the parasitic capacitance CPAR since the electric field lines emerging from the sensor structure element214-1in the direction of the metallization structures210-1are short-circuited inside the metallization structure210-1on the way to the second sensor structure element214-2, i.e. they cover only a small fraction of the path inside the insulation layer212, and can therefore be reduced further, i.e. compared with a case in which the conductive layer structure210-1is not formed.

Aspects of the present methods100,100′ for producing a moisture sensor300,300′ at the wafer level will be further discussed below.

According to a first aspect of the present method for producing a moisture sensor at the wafer level, an e.g. one-layer planar passivation layer (=first cover layer) is formed above the sensor structure, formed for example as an interdigital structure or capacitive measurement structure, of the moisture sensor. The e.g. one-layer planar passivation layer (first cover layer) is relatively simple to produce in the process sequence and may be integrated very well into previous process sequences. The moisture-absorbing layer of the moisture sensor may be applied extremely simply onto the extremely planar passivation layer above the sensor structure elements or interdigital structure (and a second cover layer arranged thereon, which is provided for example as an etch stop layer during the production method), since there is no topology or surface unevenness.

According to a second aspect of the present method for producing a moisture sensor at the wafer level, an (at least) two-layer passivation layer arrangement is arranged on or above the sensor structure configured as an interdigital structure, one of the passivation layers being configured as a sacrificial layer in order to obtain a hollow space, or a cavity, between opposite sensor structure elements, for example between opposite finger elements of the interdigital structure, after at least local removal of the sacrificial layer. The moisture-absorbing layer of the moisture sensor may be applied extremely simply onto the extremely planar passivation layer arrangement above the sensor structure elements or interdigital structure (and a second cover layer arranged thereon, which is provided for example as an etch stop layer during the production method), since there is no or only a small topology or surface unevenness.

In the hollow space (or the hollow spaces or cavities), a relative dielectric constant εr≈1 of air may then be assumed. The “ineffective” component of the electric field may therefore be minimized, the ineffective component of the electric field, or of the electric field lines, being regarded as the component which does not pass through the moisture-absorbing layer.

By the provision of hollow spaces, or cavities, according to the second aspect between neighboring sensor structure elements in the passivation layer arrangement covering the measurement structure, the measurement results of the sensor structure may be improved further since the ineffective component of the electric field, or of the electric field lines, which does not pass through the moisture-absorbing material, can be minimized. Since a relative dielectric constant εrof about 1 can be assumed in the hollow spaces, the parasitic capacitance of the measurement capacitance can be kept relatively low and the signal-to-noise ratio (SNR) in the output signal of the sensor structure can therefore be increased significantly compared with conventional approaches.

The sacrificial material used may, besides very many different suitable sacrificial materials, comprise for example carbon, which may be ashed with oxygen. In the second aspect of the production method, the upper side of the hollow space may have an offset Δx with respect to the surface of the electrode structures, so that for example a residual topology remains on the upper passivation layer, onto which the moisture-absorbing material is then applied.

Both aspects of the present method for producing a moisture sensor at the wafer level may be introduced very simply into existing CMOS process sequences, the sensor structure elements, arranged for example as an interdigital structure, with the one-layer or two-layer passivation layer arrangement arranged thereon, which is configured in a relatively planar fashion above the interdigital structure, being produced. This passivation layer arrangement is then structured, at least the sections of the passivation layer arrangement which cover the sensor structure elements being preserved. This structured passivation layer arrangement is then preserved (“interim parked”) during the further process steps for the moisture sensor, or further circuit elements on the BEOL stack, i.e. the substrate arrangement, with the CMOS circuit arrangement until the planar passivation layer arrangement (and the second cover layer arranged thereon, which is provided for example as an etch stop layer during the production method, and which with the planar passivation layer arrangement forms the planar cover layer arrangement, or the planar cover layer stack) is exposed again on the interdigital structure and then the measurement layer, i.e. the moisture-absorbing layer element, is applied in order finally to form the moisture sensor.

Both aspects of the present method for producing a moisture sensor at the wafer level are surface-neutral, since the moisture sensor may for example be arranged above regions with CMOS logic in the semiconductor substrate which are present anyway.

Furthermore, a reference capacitance or reference electrode structure may be provided in order to be able to compensate effectively for possible perturbing cross-influences in the case of interconnection of the measurement capacitance with the reference capacitance to form a Wheatstone bridge.

The production of the sensor structure is thus, for example, carried out in such a way that the moisture-sensitive electrodes and the moisture-insensitive reference electrodes are produced inside the same process module, after the standard CMOS metallization process step and before carrying out the pad fabrication module.

According to exemplary embodiments of the present method for producing a moisture sensor at the wafer level, the sensor structure elements may be integrated monolithically with the application-specific integrated circuit arrangement (ASIC) on the same semiconductor substrate. Furthermore, the sensor structure elements of the moisture sensor and the ASIC may be produced within a commonly employed process sequence, or process flow. In this case, the sensor structure elements may be embedded inside a dielectric material (the passivation layer arrangement and the second cover layer, i.e. the cover layer stack, optionally arranged thereon). The dielectric material of the passivation layer is for example planarized, for example by means of a CMP process (CMP=chemical-mechanical polishing), which exposes a flat surface region of the passivation layer without relevant topology. The moisture-sensitive material is then applied on the upper side of the planar cover layer arrangement covering the sensor structure, or the cover layer stack (=passivation layer and the second cover layer arranged thereon).

Furthermore, according to the present method, reference electrode structures without moisture sensitivity may be produced simultaneously in a parallel fashion in order to produce the measurement sensor structure elements, for example in order to form a capacitive bridge circuit (Wheatstone bridge) with the capacitive measurement and reference electrode structures.

According to exemplary embodiments, both components of the signal generation, i.e. the moisture sensor300,300′, and of the signal processing for processing the sensor signals, for example in the form of the FEOL components204, are available on the same chip. Furthermore, the moisture sensor300,300′ may be integrated economically into existing sensor systems or sensor solutions, in order for example to form multi-sensor systems. In particular, an integrated production process or production sequence may be carried out for the moisture sensor with the associated CMOS-ASIC, in which case production processes may be used together. Furthermore, a thin planarized cover layer or passivation layer or layer structure on the sensor electrodes (sensor structure elements) permits a high signal yield and therefore accuracy of the moisture sensor300. Furthermore, the moisture sensor300at the wafer level may be arranged on the metallization layer stack206above active circuit regions of the FEOL components204, so that available chip surface may be used. In this case, the term “sensor-over-active” sensor arrangement is used.

According to one exemplary embodiment, a method100,100′ for producing a moisture sensor300,300′ at the wafer level comprises the following steps: providing105a substrate arrangement200, which comprises a semiconductor substrate202and a metallization layer stack206arranged on the semiconductor substrate202, the metallization layer stack206comprising a multiplicity of metallization structures210,210-1embedded in an insulation material208, an insulation layer212being arranged on the metallization layer stack206, applying no a sensor structure214having a multiplicity of conductive sensor structure elements214-1,214-2on the insulation layer212of the metallization layer stack206, applying115a first cover layer216on the sensor structure214and uncovered sections of the insulation layer212, the first cover layer216covering the conductive sensor structure214, and a section, covering the conductive sensor structure214, of the first cover layer216being configured in a planar fashion in order to form a planar cover layer arrangement220, locally removing125the planar cover layer arrangement220, the sensor structure214remaining covered with the planar cover layer arrangement220, applying130a third cover layer222on the exposed insulation layer212and the planar cover layer stack220covering the sensor structure214, exposing135the planar cover layer arrangement220covering the sensor structure214, and applying145a moisture-absorbing layer element232on the planar cover layer arrangement220covering the sensor structure, in order to obtain the moisture sensor300.

According to a further exemplary embodiment, the method100furthermore comprises the following step: applying120a second cover layer218on the planar first cover layer216, in order to obtain the planar cover layer arrangement220as a planar cover layer stack220having the first and second cover layers216,218on the sensor structure214.

According to a further exemplary embodiment, the method100furthermore comprises the following step: planarizing the first cover layer, in order to form at least the section216-1, covering the sensor structure214, of the first cover layer216in a planar fashion.

According to a further exemplary embodiment, the method100′ furthermore comprises the following step: arranging a sacrificial layer structure217between the neighboring sensor structure elements214-1,214-2of the sensor structure214after the application of the first cover layer216, in order to obtain a cavity region234between the neighboring sensor structure elements214-1,214-2of the sensor structure214.

According to a further exemplary embodiment, the method100,100′ furthermore comprises the following step: applying140a passivation layer arrangement onto the planar cover layer arrangement220covering the sensor structure214, the step135of exposing the planar cover layer arrangement220covering the sensor layer structure214being carried out through the passivation layer arrangement and the third cover layer222.

According to a further exemplary embodiment, during the application110of the sensor structure214having a multiplicity of conductive sensor structure elements214-1,214-2, a reference electrode structure215having a multiplicity of conductive reference structure elements215-1,215-2is furthermore applied on the insulation layer212.

According to a further exemplary embodiment, the reference electrode structure215is embedded in the third cover layer after the application of the third cover layer.

According to a further exemplary embodiment, the reference electrode structure215is formed as a metallization structure embedded in the metallization layer stack.

According to a further exemplary embodiment, the metallization layer stack206comprises next to the sensor structure214a metallization structure210-1, which is configured as a shielding element for the sensor structure214in order to reduce a parasitic capacitance.

According to a further exemplary embodiment, the method100,100′ furthermore comprises the following step after the application of the third cover layer222: applying further insulation layer structures, metallization layer structures and/or component structures on one another or on the third cover layer222.

According to a further exemplary embodiment, during the step of applying further insulation structures, metallization layer structures and/or component structures, a rewiring layer, an insulation layer, an uppermost metallization layer and/or a passivation layer arrangement are applied and structured in such a way that the planar cover layer arrangement220covering the sensor structure214is exposed.

According to a further exemplary embodiment, the moisture-absorbing layer element232comprises a polymer material.

According to a further exemplary embodiment, the sensor structure elements214-1,214-2of the sensor structure214comprise copper or aluminum with a thickness of 500 nm or about 200 nm and a lateral spacing of about 100 nm.

According to a further exemplary embodiment, the sensor structure elements214-1,214-2are arranged in an interdigital arrangement with respect to one another.

According to a further exemplary embodiment, the components204arranged on the semiconductor substrate202are formed during an FEOL treatment process of the semiconductor substrate202.

According to a further exemplary embodiment, the FEOL components comprise components based on CMOS technology.

According to a further exemplary embodiment, the metallization layer stack206is formed during a BEOL treatment process of the substrate arrangement200.

According to a further exemplary embodiment, the metallization layer stack206comprises a multiplicity of conductive track structures210in different planes M#. in the insulation material208.

According to a further exemplary embodiment, a moisture sensor300comprises the following features: a substrate arrangement200, which comprises a semiconductor substrate202having components204arranged thereon and a metallization layer stack206arranged on the semiconductor substrate202, the metallization layer stack206comprising a multiplicity of metallization structures embedded in an insulation material208, an insulation layer212being arranged on the metallization layer stack206of the substrate arrangement200, a sensor structure214having a multiplicity of conductive sensor structure elements214-1,214-2on the insulation layer212of the metallization layer stack206, a planar cover layer arrangement220being arranged on the sensor structure214, and a moisture-absorbing layer element232on the planar cover layer stack220covering the sensor structure214.

According to a further exemplary embodiment, the planar cover layer arrangement220comprises a first cover layer216, which covers the conductive sensor structure214, and a section, covering the conductive sensor structure214, of the first cover layer216is configured in a planar fashion in order to form the planar cover layer arrangement220.

According to a further exemplary embodiment, the planar cover layer arrangement220furthermore comprises a second and a third cover layer216,218on the sensor structure214, in order to obtain the planar cover layer arrangement220as a planar cover layer stack220having the first and second cover layers216,218on the sensor structure214, a material of the first cover layer being arranged in an intermediate region between the neighboring conductive sensor structure elements214-1,214-2of the sensor structure, or the intermediate space between neighboring conductive sensor structure elements214-1,214-2of the sensor structure214being left free as a cavity region.

According to a further exemplary embodiment, a passivation layer arrangement is furthermore arranged on the planar cover layer arrangement220covering the layer structure.

According to a further exemplary embodiment, a third cover layer222is furthermore arranged on uncovered regions of the insulation layer212and of the planar cover layer arrangement220of the sensor structure214.

According to a further exemplary embodiment, the moisture sensor300furthermore comprises the following feature: a reference electrode structure215having a multiplicity of reference structure elements215-1,215-2on the insulation layer212.

According to a further exemplary embodiment, the reference electrode structure is embedded in the third cover layer.

According to a further exemplary embodiment, the reference electrode structure is formed as a metallization structure embedded in the metallization layer stack206.

According to a further exemplary embodiment, the metallization layer stack206comprises next to the sensor structure214a metallization structure210-1, which is configured as a shielding element for the sensor structure214in order to reduce a parasitic capacitance.

Although some aspects of the present disclosure have been described as features in connection with a device, it is clear that such a description may likewise be regarded as a description of corresponding method features. Although some aspects have been described as features in connection with a method, it is clear that such a description may also be regarded as a description of corresponding features of a device, or of the functionality of a device.

In the detailed description above, various features have sometimes been grouped together in examples in order to rationalize the disclosure. This type of disclosure should not be interpreted as meaning that the claimed examples comprise more features than are explicitly specified in each claim. Rather, as the following claims reflect, the subject-matter may reside in fewer than all the features of an individual disclosed example. Consequently, the following claims are hereby included in the detailed description, wherein each claim may stand as an individual separate example. While each claim may stand as an individual separate example, it should be noted that, although dependent claims in the claims refer back to a specific combination with one or more other claims, other examples also comprise a combination of dependent claims with the subject-matter of any other dependent claim or a combination of any feature with other dependent or independent claims. Such combinations are to be included unless it is mentioned that a specific combination is not intended. It is furthermore intended that a combination of features of one claim with any other independent claim is also included, even if this claim is not directly dependent on the independent claim.

Although specific exemplary embodiments have been presented and described herein, it will be clear to a person skilled in the art that many alternative and/or equivalent implementations may be substituted for the exemplary embodiments specifically shown and presented there, without departing from the subject-matter of the present application. This application text is intended to cover all adaptations and variations of the specific exemplary embodiments described and discussed herein. The present application subject-matter is therefore limited only by the wording of the claims and the equivalent embodiments thereof.