Voltage regulator

A voltage regulator is capable of continuously and smoothly preventing an inrush current independently of a startup characteristic of a reference voltage circuit. The voltage regulator is provided with an inrush current protection circuit composed of a constant-current circuit, a first transistor having the source thereof connected to the constant-current circuit and the gate thereof controlled by an output voltage detection circuit, a capacitor connected between the first transistor and the gate of an output transistor, a second transistor having the gate thereof connected to the drain of the first transistor and the source thereof connected to a power supply terminal, and a third transistor, which is connected between the second transistor and the output transistor and the gate of which is controlled by the output voltage detection circuit.

RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2011-075590 filed on Mar. 30, 2011, the entire content of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a voltage regulator provided with an inrush current protection circuit and more particularly to an inrush current protection circuit that controls an inrush current by restricting a fluctuation at the gate of an output driver so as to restrain an inrush current into an output capacitor occurring at a startup.

2. Description of the Related Art

A conventional inrush current protection circuit will be described.FIG. 3is a circuit diagram of a conventional constant-voltage circuit. The constant-voltage circuit is composed of a constant-voltage source401and a soft start circuit, which is an inrush current protection circuit. The soft start circuit has a comparator404, a delay circuit412, a constant-current source407, a capacitor408, a resistor403, and switches402,410and411.

The contact point of the constant-current source407and the capacitor408is connected to an output terminal101of the constant-voltage circuit. The output terminal101is connected to a non-inverting input terminal of the comparator404, and an output terminal of the constant-voltage source401is connected to an inverting input terminal of the comparator404through the intermediary of an offset voltage405. An output terminal of the comparator404is connected to the switch402, the constant-current source407, and the delay circuit412. An output terminal of the delay circuit412is connected to the switch411.

The capacitor408is charged by receiving constant current Ic from the constant-current source407. The comparator404compares the voltage obtained by subtracting the predetermined offset voltage405from an output voltage of the constant-voltage source401and the voltage at the contact point of the constant-current source407and the capacitor408, and issues an output voltage based on the result of the comparison. The output voltage of the comparator404controls the switch402, the constant-current source407, and the switch411through the delay circuit412. When the switch402is turned on, the capacitor408is charged by the constant-voltage source401through the resistor403on the basis of an RC time constant. After predetermined time elapses since a output voltage is received from the comparator404, the delay circuit412turns the switch411on. When the switch411is turned on, the output voltage of the constant-voltage source401is directly output to the output terminal101.

The operation of the conventional constant-voltage circuit will now be described. In the state wherein the switch410is on, the constant-voltage circuit is not in operation and the output voltage at the output terminal101is 0 volt. When the switch410is turned off, the constant-voltage circuit is actuated. The constant-current source407supplies the constant current Ic to start charging the capacitor408with the constant current. At this time, the output voltage at the output terminal101linearly rises according to the constant current Ic and the capacitance of the capacitor408. If the voltage charged in the capacitor408exceeds the voltage, which is obtained by subtracting the offset voltage405from the voltage of the constant-voltage source401, then an output signal of the comparator404is inverted. This causes the switch402to turn on and the constant-current source407to stop and the delay circuit412to be actuated. When the constant-current source407stops its operation, the capacitor408is charged with the output voltage of the constant-voltage source401through the resistor403.

The moment the switch411turns on after the elapse of the predetermined time since the delay circuit412was actuated, the output voltage of the constant-voltage source401immediately reaches the output voltage at the output terminal101. As described above, the output voltage at the output terminal101of the constant-voltage circuit gradually increases, thus allowing the output terminal101of the constant-voltage circuit to be protected from an inrush current (refer to, for example, FIG. 2 in patent document 1).

However, the conventional art has been posing a problem in that changing from a soft start phase over to a constant-voltage output phase by a switch inconveniently causes discontinuity in a linearly increasing output voltage. There has been another problem in that the need for a comparator and a delay circuit inevitably results in a larger circuit scale.

SUMMARY OF THE INVENTION

The present invention has been made with a view toward the problems described above, and it is an object of the invention to provide a voltage regulator with an inrush current protection circuit which has a small circuit scale and which is capable of achieving a continuous and smooth rise of an output voltage.

A voltage regulator provided with an inrush current protection circuit in accordance with the present invention includes: a reference voltage circuit which outputs a reference voltage; an output transistor; a first differential amplifier circuit which amplifies and outputs the difference between the reference voltage and a divided voltage obtained by dividing a voltage output from the output transistor and controls a gate of the output transistor; an inrush current protection circuit which controls a gate voltage of the output transistor to prevent an inrush current; and an output voltage detection circuit which controls the inrush current protection circuit, wherein the inrush current protection circuit includes: a constant-current circuit having one end thereof connected to a power supply terminal; a first transistor having a source thereof connected to the other end of the constant-current circuit and a gate thereof controlled by the output voltage detection circuit; a capacitor having one end thereof connected to a drain of the first transistor and the other end thereof connected to the gate of the output transistor; a second transistor having a gate thereof connected to the source of the first transistor and a source thereof connected to a power supply terminal; and a third transistor having a drain thereof connected to the gate of the output transistor, a source thereof connected to a drain of the second transistor and a gate thereof controlled by the output voltage detection circuit.

The voltage regulator provided with the inrush current protection circuit in accordance with the present invention does not use any switches, thus making it possible to continuously restrain an inrush current. In addition, the voltage regulator does not involve self-consumption current, so that a reduced circuit scale can be achieved.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIG. 1is a circuit diagram of a voltage regulator according to a first embodiment. The voltage regulator according to the first embodiment is constituted of a reference voltage circuit101, a differential amplifier circuit102, a PMOS transistor104, resistors105and106, an inrush current protection circuit103, an output voltage detection circuit110, a power supply terminal150, a ground terminal100, and an output terminal180. The inrush current protection circuit103is constituted of an input terminal210, an output terminal211, PMOS transistors203,204and205, a constant-current circuit202, and a capacitor206.

The inverting input terminal of the differential amplifier circuit102is connected to the reference voltage circuit101, while the non-inverting input terminal thereof is connected to the connection point of the resistors105and106, and the output terminal thereof is connected to the gate of the PMOS transistor104and an output terminal211of the inrush current protection circuit103. The other end of the reference voltage circuit101is connected to a ground terminal100. The source of the PMOS transistor104is connected to the power supply terminal150and the drain thereof is connected to the output terminal180and the other end of the resistor105. The other end of the resistor106is connected to the ground terminal100. The gate of the PMOS transistor204is connected to an input terminal210of the inrush current protection circuit103and the gate of the PMOS transistor205, the source thereof is connected to the constant-current circuit202and the gate of the PMOS transistor203, and the drain thereof is connected to the capacitor206. The other end of the constant-current circuit202is connected to the power supply terminal150. The source of the PMOS transistor205is connected to the drain of the PMOS transistor203, and the drain thereof is connected to the other end of the capacitor206and the output terminal211of the inrush current protection circuit103. The source of the PMOS transistor203is connected to the power supply terminal150. The input terminal210is connected to the output voltage detection circuit110.

The operation of the voltage regulator according to the present embodiment will now be described.

The resistors105and106divide an output voltage Vout, which is the voltage of the output terminal180, and output a divided voltage Vfb. The differential amplifier circuit102compares an output voltage Vref of the reference voltage circuit101with the divided voltage Vfb to control the gate voltage of the PMOS transistor104such that the output voltage Vout remains constant. If the output voltage Vout is higher than a desired value, then the divided voltage Vfb will be higher than the reference voltage Vref and the output signal of the differential amplifier circuit102(the gate voltage of the PMOS transistor104) will become high. Further, the PMOS transistor104turns off, causing the output voltage Vout to be lower. Thus, the output voltage Vout is controlled to remain at a constant level. If the output voltage Vout is lower than the desired value, then a reverse operation from the above is performed to increase the output voltage Vout. In this manner, the output voltage Vout is controlled to remain at the constant level.

The operation at the startup of the supply voltage of the voltage regulator according to the present embodiment will now be described.

When the differential amplifier circuit102detects that the output voltage Vout is low, it controls the gate voltage such that the PMOS transistor104turns on. The output voltage detection circuit110outputs a Lo signal to the terminal210of the inrush current protection circuit103. In the inrush current protection circuit103, the PMOS transistors204and205turn on. When the PMOS transistor204turns on, the gate voltage of the PMOS transistor203becomes low, causing the PMOS transistor203to turn on. The PMOS transistor203and the PMOS transistor205turn on, so that the gate voltage is controlled such that the PMOS transistor104turns off. The currents from the PMOS transistor203and the PMOS transistor205are designed to be smaller than the current from a transistor in an output stage of the differential amplifier circuit102. Hence, the PMOS transistor203and the PMOS transistor205function to prevent the differential amplifier circuit102from excessively turning the PMOS transistor104on. Thus, the inrush current protection circuit103restrains the inrush current of the output terminal180.

When the supply voltage is started to increase, the amount of a transient fluctuation at the gate of the PMOS transistor104changes according to a stabilizing capacitance or load current condition. Hence, as the amount of the fluctuation increases, the amount of fluctuation in the gate voltage of the PMOS transistor203with respect to the supply voltage increases and the operation for returning the gate voltage of the PMOS transistor104to the supply voltage is enhanced accordingly. Inversely, as the amount of the fluctuation decreases, the amount of fluctuation in the gate voltage of the PMOS transistor203with respect to the supply voltage decreases and the operation on the gate of the PMOS transistor104is hardly carried out. Thus, a prompt startup can be achieved by restraining the inrush current to a minimum according to a stabilizing capacitance or a load current.

After the rise of the output voltage, a Hi signal is output from the output voltage detection circuit110, causing the voltage at the input terminal210to become high. This turns the PMOS transistors204and205off, stopping the operation of the inrush current protection circuit103. Thus, malfunctions can be prevented in a normal operation, permitting reduced power consumption.

As described above, the voltage regulator according to the first embodiment is capable of preventing an inrush current at the time of turning the power on and achieving a prompt startup.

Second Embodiment

FIG. 2is a circuit diagram of a voltage regulator according to a second embodiment. This voltage regulator differs from the one illustrated inFIG. 1in that the constant-current circuit202has been replaced by a resistor301. The configuration also enables the voltage regulator to be operated in the same manner as the voltage regulator according to the first embodiment.