Microsystem device and methods for fabricating the same

A microsystem includes a base layer formed from an electrical insulating material. The base layer has an inner surface defining a cavity and an external surface opposed to the inner surface, and in direct communication with an environment. A cap layer and a microelectromechanical (MEMS) device layer are formed from electrical insulating material or an other electrical insulating material. The cap has an inner surface defining a cavity, and an external surface opposed to the inner surface, and in direct communication with the environment. A MEMS device on/in the MEMS device layer is disposed between the base and the cap. Respective adjacent portions of the base, the cap and the device substrate are bonded to define an enclosed space. The enclosed space at least partially includes the base cavity or the cap cavity. At least a portion of a MEMS device on the device layer is in the enclosed space.

BACKGROUND

MEMS timing and inertial measurement units (TIMUs) are devices used to measure inertial effects and time with a wide range of applications. For example, TIMUs may be used in determining speed, acceleration, and direction, thereby having applications in navigation. MEMS TIMUs can perform the functions of angular rate sensors (gyroscopes), accelerometers, and mechanical oscillators for timers and filters. While discrete sensor and timing units have been successful, integration of several such devices in a single integrated MEMS structure has been met with drawbacks.

For example, silicon structures for timing and inertial measurement devices, including micromachined resonant accelerometers, gyroscopes, capacitive accelerometers and micromechanical resonators for timing units have been tried and tested. In some cases, the conductive properties of silicon have required application scientists to take additional steps to insulate conductors disposed on a silicon substrate.

Some of the drawbacks encountered in previous attempts at integrating a TIMU in a single MEMS structure have been: large size, coupling between devices and the conflicting process and package requirements for accelerometers, gyroscopes, and timing units. System integration is a particular challenge, including the incorporation of temperature control, vibration/shock isolation and sensor fusion.

DETAILED DESCRIPTION

The present disclosure relates generally to micro-electro-mechanical systems (MEMS).

FIG. 1is a cross sectional view of an example of a microsystem10as disclosed herein. A MEMS device layer40is shown disposed between a package base layer20and a cap layer30. The package base layer20is formed from a first substrate of an electrical insulating material.

In examples of the present disclosure, the electrical insulating material may include fused silica, fused quartz, glass, ceramic, zero expansion glass-ceramic, ultra low expansion (ULE®) glass, Zerodur®, Pyrex®, Borofloat®, Clearceram®, mica, alumina, sapphire, or quartz. Fused silica is a type of glass that is mainly silica in a non-crystalline form. An example of fused silica is Corning 7980 0F UV grade commercially available from Valley Design Corporation, Santa Cruz, Calif. Fused silica wafers are commercially available in many diameters and thicknesses. For example, a Valley Design Corporation part number FS-105 is 200 mm in diameter×0.5 mm thick, and part number FS-148 is 100 mm in diameter×2.3 mm thick. Fused silica may be micromachined using a variety of dry and wet etching techniques, or fused silica may be molded into a particular shape.

Still referring toFIG. 1, the package base layer20has a base inner surface26defining a base cavity28. A base external surface27is opposed to the base inner surface26and in direct communication with an environment18. A cap layer30is formed from a second substrate of the electrical insulating material or another electrical insulating material. The cap layer30has a cap inner surface36defining a cap cavity38. A cap external surface37is opposed to the cap inner surface36, and is in direct communication with the environment18.

The MEMS device layer40is disposed between the package base layer20and the cap layer30. The MEMS device layer40is formed from a device layer substrate. The MEMS device layer substrate may be a substrate of the electrical insulating material from which the package base layer20or the cap layer30is formed or a substrate of another electrical insulating material. It is to be understood that any number and combination of electrical insulating materials may be used to form electrical insulating materials. In a non-limiting example, the package base layer may be a first electrical insulating material, the MEMS device layer substrate may be a second electrical insulating material, and the cap may be formed from a third electrical insulating material. In another example, the package base layer substrate and the cap layer may be formed from the first electrical insulating material, and the MEMS layer substrate may be formed from a second electrical insulating material. Selection from first, second, third, etc. electrical insulating material for each substrate may be independent.

In examples of the present disclosure, the microsystem10may include more than one MEMS device layer40. In an example, a MEMS device layer40may include or be formed from a substrate of an electrical insulating material, and another MEMS device layer40′ (seeFIG. 4) may include or be formed from a substrate chosen from, e.g., silicon, silicon-on-insulator, silicon dioxide, germanium, silicon carbide, silicon carbon, graphite, graphene, gallium arsenide, gallium nitride, gallium phosphide, indium phosphide, zinc oxide, zinc sulfide, zinc selenide, lead zirconium titanate, cadmium selenide, cadmium telluride, cadmium mercury telluride, lithium niobate, lithium tantalite, yttrium aluminum garnet (YAG), magnesium oxide, magnesium fluoride, lithium fluoride, barium fluoride, barium titanate, strontium titanate, metals, or combinations thereof. In such an example, the other MEMS device layer40′ is not necessarily (but may be) formed on/from an insulating substrate. It is to be understood that combinations as used herein may include any combination in or on the MEMS layer including alloys of metals, mixtures of materials, layers of materials, and dispersions of materials.

In examples of the present disclosure, at least a portion of the MEMS device layer may be unsupported by the MEMS device layer substrate. A portion of the substrate may be removed during fabrication, thereby leaving the unsupported portion of the MEMS device layer. Furthermore, the MEMS device43may be formed in the device layer substrate of the MEMS device layer40by micromachining.

In the example of the present disclosure depicted inFIG. 1, respective adjacent portions of the package base layer20, the cap layer30and the MEMS device layer40are bonded to define an enclosed space58between the package base layer20and the cap layer30. The enclosed space58at least partially includes the base cavity28or the cap cavity38. In examples of the present disclosure, the respective adjacent portions of the package base layer20, the cap layer30, and the MEMS device layer40may be respective adjacent edges of the package base layer20, the cap layer30, and the MEMS device layer40. At least an operative portion of the MEMS device43is disposed in the enclosed space58. As used herein, an enclosed space means a volume that is substantially surrounded by a barrier. In some examples, the enclosed space58may be a sealed space58′ that has substantially no flow of material in or out of the sealed space58′. In other examples, fluid communication may be possible between the enclosed space58and the ambient space external to the enclosed space58. For example, an atmospheric pressure sensor (not shown) may be disposed inside the enclosed space58. In the example, a port (not shown) may be disposed in the MEMS device layer40, the package base layer20and/or the cap layer30to allow the atmospheric air to be in fluid communication with the pressure sensor.

In the example depicted inFIG. 1, a low thermal coefficient of expansion (TCE) glass frit50is used to bond the package base layer20, the cap layer30and the MEMS device layer40. It is to be understood that other bonding techniques are disclosed herein. For example, solders (i.e., eutectic solders) and other conductors may be used as bonding materials.

In examples of the present disclosure, the MEMS device43is chosen from sensors, actuators, mechanical isolators, thermal isolators, shock absorbers, and combinations thereof. It is to be understood that there may be one or more than one MEMS device43in a single MEMS device layer40.

A feedthrough via51may be formed in respective adjacent portions of the package base layer20, cap layer30, and the MEMS device layer40. For example, the vias may be disposed in respective adjacent edges34,34′, and34″ of the cap layer30, the MEMS device layer substrate40, and the package base layer20respectively. An electrically conductive feedthrough52may be disposed in the via51to allow electrical communication through the electrical insulating material with the MEMS device43in the sealed space58′. In examples of the disclosed microsystem10having feedthroughs52passing through an electrical insulator material, the feedthroughs52are naturally isolated from one another. Connections to the feedthroughs52are made using conductors62deposited on the package base layer20, cap layer30, and/or the MEMS device layer40and brought out to the edge34,34′34″ where they are connected to the feedthroughs52. A conductor62or operative material may be deposited on the package base layer20, the cap layer30, and/or the MEMS device layer substrate to functionalize the MEMS devices43for sensors, actuators, and/or other operative portions of the microsystem10. An operative material may be deposited on at least a portion of the base inner surface26, the cap inner surface36, or combinations thereof to form an electrode, a getter60, a shock stop61, or to operatively perform as a portion of a sensor, actuator, and/or other operative portion of the microsystem10. It is to be understood that a getter60may maintain a vacuum in an evacuated sealed space58′ by chemically reacting with or adsorbing gas molecules.

FIG. 1depicts an integrated sensor41formed, for example, by micromachining the MEMS device layer substrate. The integrated sensor41may include, for example, a drive42, a mass44, and a transducer46. An operative material48may be deposited on portions of the MEMS device layer substrate to form device elements including electrodes, capacitors, resistors, inductors and connector traces. In the example depicted inFIG. 1, atomic layer deposition (ALD) may be used to deposit tungsten as indicated on the surfaces at reference numeral48. A 3-axis vibration/thermal isolation platform56having a vertical spring54(e.g. formed from poly-silicon) is depicted. It is to be understood that in this cross-sectional view, thin support whiskers attaching various components are not shown by drawing convention. However, it is to be further understood that some examples of the disclosed microsystem10may include a mass44that is held in place by electric or magnetic fields without a mechanical connection to adjacent parts.

FIGS. 2 and 3depict examples of the disclosed microsystem in which a single MEMS device layer40may support either one MEMS device43, or a plurality of MEMS devices43chosen from sensors, actuators, mechanical isolators and thermal isolators and shock absorbers.

Referring toFIG. 4, examples of the microsystem10disclosed herein may include two MEMS device layers40,40′. As depicted inFIG. 4, at least a portion of one of the two MEMS device layers40may be mechanically connected to at least a portion of the other of the two device layers40′. The mechanical connection may be made by bonding the portions (e.g., using a glass frit50or other bonding material including solder or other metals), or by creating a mechanical linkage using gears, levers, latches, interlocks, springs, electrostatic fields, magnetic fields or friction surfaces (not shown). In other examples, at least a portion of one of the two MEMS device layers40may be mechanically isolated from at least a portion of the other of the two MEMS device layers40′.

FIG. 5depicts an example of the present disclosure having two MEMS device layers40,40′ formed from one material (e.g., fused silica) and third MEMS device layer40″ formed from another material (e.g., quartz). InFIG. 6, the two MEMS device layers40,40′ formed from the one material (depicted at reference numeral73) are depicted bonded together (i.e. with glass frit50) and the third MEMS device layer (depicted at reference numeral72) is mechanically isolated from the two MEMS device layers73. The package base layer20and the cap layer30depicted inFIG. 5are formed from the same electrical insulating material from which the two MEMS device layers40,40′ are formed (e.g., fused silica), although it is to be understood that the layers20,30,40,40′,40″ may instead each be formed from independently selected different electrical insulating materials.

FIG. 6depicts an example of the disclosed microsystem10in which the cap external surface37and the base external surface27may be used to form different sensors and actuators. In other words, the package base layer20and the cap layer30may function as elements of a sensor or actuator in addition to forming a package and enclosing the microsystem10. InFIG. 6, an external mass78is attached to the cap layer30, and if the cap layer30is thin enough, the external mass78together with the thin cap layer30and the MEMS device layers40,40′,40″ may form accelerometers, pressure sensors, or force sensors. For example, a conductive surface80deposited on the MEMS device layer40as shown may cooperate with electrode61to form a capacitor. Deflection of the base inner surface26from vibration of the external mass78may be correlated to a change in capacitance of the capacitor. As such, an example of an accelerometer has been demonstrated. In a variation of this example, a conductive material may be deposited on at least a portion of the base inner surface26(as depicted in61), the cap inner surface36, (as depicted in62), the MEMS device layers40′,40″, or combinations thereof to form an inductive element or capacitive plate to electromagnetically communicate with an electromagnetic element (not shown) within or external to the microsystem10without direct connection with the electromagnetic element.

FIG. 7depicts an example in which an active device84is attached to the MEMS device layer40. In the example, the active device84, which may be a different technology or material from the MEMS device layer substrate, is flip chip bonded/attached to the MEMS device layer40. In the example, the MEMS device layer40provides an isolation platform for thermal, mechanical, and shock isolation for the flip-chip bonded device. The active device84may be monolithically integrated with the MEMS devices layer. For example, diodes and transistors may be co-fabricated during the MEMS device fabrication. In some cases, the active device84may not require fabrication from the same material that was used to form the MEMS device layer40. For example, a silicon active device may be flip-chip bonded to a MEMS device layer40made from a fused silica substrate. Active device84may similarly be bonded/attached to the package base layer20, a partition layer (seeFIG. 9), the cap layer30, a MEMS device layer40or combinations thereof. It is to be understood that a plurality of active devices84may be included in the microsystem10using hybrid or monolithic integration.

FIG. 8depicts an example of a microsystem10having integrated devices on the MEMS device layer substrate using a variety of micromachining technologies, including surface micromachining. In an example in which the MEMS device layer substrate is fused silica, many of the same semiconductor fabrication technologies used for silicon devices may be applied. In the example depicted inFIG. 8, a surface micromachined Si device88is disposed on an isolation platform56formed from the MEMS device layer substrate. The isolation platform56may be a thermal and/or mechanical isolation platform.

FIG. 9depicts an example of microsystem10having a partition layer70. The partition layer70is formed from a third substrate of the electrical insulating material. The partition layer70is similar to a combined cap layer30and package base layer20. The partition layer70has a first surface76defining a first cavity74and a second surface77opposite the first surface76defining a second cavity75wherein the partition layer70divides the sealed space58′ into at least two hydraulically separated sealed spaces64,64′. The at least two hydraulically separated sealed spaces64,64′ may present particular environments to the MEMS devices43. For example, one sealed space64may be filled with a particular fluid at a particular pressure, and the other sealed space64′ may be substantially evacuated.

FIG. 10depicts an example that combines the examples depicted inFIGS. 2-9. A complete microsystem10′ is fabricated, for example, using fused silica layers (wafers) that are bonded together. The microsystem10′ provides an enclosed space58for the MEMS devices43inside. In examples of the disclosed microsystem, the enclosed space58may contain vacuum, air, other gasses or other materials. As depicted inFIG. 10, there may be several MEMS device layers40between the package base layer20and the cap layer30. In the example, a first sensor (for sensing in a vertical direction using the orientation shown on the page) is depicted at12. A second sensor13senses in a lateral direction orthogonal to first sensor12. A third sensor14senses in a lateral direction orthogonal to both sensor12and sensor13. At16, an Nth sensor is depicted to show that any number of MEMS device layers40may be included in the microsystem10′. Adjacent to the Nth sensor16is an N−1 sensor15. In the example depicted inFIG. 10, all of the MEMS device layers40are made out of fused silica or a combination of fused silica and other materials.

Sensors, actuators, resonators, and various other mechanical structures may be formed from fused silica, or from layers that are deposited on top of fused silica wafers. Other materials, such as semiconductors, metals and insulators may be deposited on the fused silica wafers to form the MEMS devices43or to form feedthroughs52. Electrical, optical, and fluidic interconnections can be made between cap layer30, MEMS device layers40, and package base layer20using appropriate feedthroughs52. Electrical feedthroughs52are formed using conductors that pass through either all of the MEMS device layers40, or through only some of the MEMS device layers40, and/or through the cap layer30, and/or through the base layer20to transfer signals to the outside world or to interconnect MEMS devices43formed on the different MEMS device layers40. In addition, the MEMS device layers40may include conductors62which pass through the MEMS device layer to connect the top of the layer to the bottom of the layer, to interconnect devices on the same MEMS device layer40.

FIG. 10shows how conductors62may be interconnected in the three dimensional (3-D) microsystem10′. Glass frit50may be used to bond and electrically insulate layers and portions of layers. ALD tungsten48may be deposited on the layers as electrodes and conductors. For example, the feedthrough with reference numeral22may be electrode #1in the example shown connected as a common bias. Feedthrough23may be connected to electrode X from the first sensor12and electrode Y from the Nth sensor16. Feedthrough24may be connected to electrode A from the first sensor12. Feedthrough25may be connected to electrode K from the second sensor13and electrode B from the Nth sensor16.

The microsystem10disclosed herein may include optically transparent or translucent substrates (e.g., fused silica, glass, and quartz). The MEMS devices43or the active devices84(see, e.g.,FIG. 7) may communicate optically through the package base layer20, the cap layer30, the partition layer70(see, e.g.,FIG. 9) or at least one of the MEMS device layers40. For example, optical signals encoded with accelerometer output data may be transmitted by a light emitting diode (not shown) through the layers of the microsystem10. It is to be understood that laser trimming may be accomplished through the optically transparent or translucent substrates (see discussion ofFIG. 31below). For example, resistors (not shown) on the MEMS device layer40may be calibrated by laser trimming using a laser source outside of the microsystem10even after the microsystem10has been sealed.

Where optical communication is used in examples of the microsystem10disclosed herein, some or all feedthroughs52may be omitted. As such, the package base layer20, the cap layer30, the partition layer70and the at least one MEMS device layer40may be electrically isolated from each other. For example, electrical feedthroughs may be omitted in examples having optical communication. Optical feedthroughs (e.g., light pipes (not shown)) may be used to direct optical signals to and from the MEMS devices43.

A non-limiting example of a method for forming a microsystem according to the present disclosure is depicted inFIGS. 11A through 11Rtogether. As shown inFIG. 11A, a fused-silica layer73(e.g., 100 μm thick) is fusion bonded on opposed sides to two silicon wafers71,71′ (e.g., each wafer 100 μm thick, the Si wafers to be used as masking layers). The front-side silicon71is through-etched using silicon deep reactive-ion etching (DRIE), and subsequently, the fused-silica wafer73is through-etched using the Si mask71(FIG. 11B). It is to be understood that portions of the assembly at this stage are being prepared for usage as a vibration isolator17, a resonator19, a planar resonant accelerometer21, and a Z-axis resonant accelerometer29in the microsystem. Similarly, the backside silicon71′ is through-etched using silicon DRIE and subsequently the fused-silica wafer73is etched from the backside to locally thin isolator springs to form a flexible vibration isolation platform (FIG. 11C, note a thinned-down isolation beam at31) or to make beams of different thicknesses to form a z-axis resonant accelerometer29or other device structure106. The silicon masks71,71′ are dissolved using, e.g., tetramethyl ammonium hydroxide (TMAH) wet etching. The fused silica layer73may then be annealed at a temperature ranging from about 1200° C. to about 1400° C. to reduce DRIE sidewall scalloping (FIG. 11D). The surface roughness of the DRIE patterns may be a major energy loss contributor, and may be minimized by using the process described above.

In the step depicted inFIG. 11E, low pressure chemical vapor deposition (LPCVD) is used to deposit a first high-Phosphorus doped polysilicon layer (first-poly)32to form a TCF-compensating layer for the integrated resonators and also to reduce the gap for capacitive sensors. The first-poly layer is either in-situ P-doped or doped separately to increase conductivity (ρ˜10−3Ω-cm). The polysilicon layer32is selectively patterned using XeF2through a spray-coated photoresist mask (FIG. 11F). It is to be understood that forms of the word “pattern” used herein may include the concept of depositing and then patterning or patterning through the deposition process. The wafer is thermally oxidized to form a shallow oxide layer33around the polysilicon layer32, which forms the gap between the resonator19and the electrode (second poly45, discussed further below) (FIG. 11G). The thickness of the oxide layer33is thin so as to not consume the entire polysilicon layer32. The thermal oxide layer33will be used as a sacrificial layer for the resonator19. The oxide layer grown on comb-drive electrodes is etched away. To etch a shallow recess for the polysilicon trench refilling (for a vertical accelerometer), another pair of single-crystal silicon wafers35,35′ is fusion bonded to each of the opposed sides. The single crystal silicon wafers35,35′ are patterned, for example, using a two-step process (FIG. 11H). The fused silica is etched through in the regions where silicon has been etched through39(FIG. 11I). In the step depicted inFIG. 11J, the etch mask is removed using wet etchant.

In the step depicted in11K, a second high-Phosphorus doped polysilicon layer (2ndpoly)45is deposited using LPCVD and selectively patterned using XeF2.FIG. 11Kalso includes representation of three subcomponents of the fused silica layer: the unreleased resonator47, comb drive electrode49, and polysilicon filled bridge53. The planar resonant accelerometer21is depicted inFIG. 11K. The 2ndpoly45is a thick layer that closes the gap between the oxide layers and serves as the resonator drive and sensor electrodes. The 2ndpoly45is also selectively patterned using XeF2, except the regions for the bridge53, gyro and resonator electrodes (FIG. 11L). This layer will serve as an electrode layer for the resonator. Either single or differential mode vertical accelerometers may be made. The fused silica between the polysilicon bridges53is removed as indicated by the voids shown at55. The vertical resonant accelerometer is complete as indicated by the section shown at29′ (FIG. 11M). A thin layer of metal59, e.g., tungsten (W), is deposited selectively on the top of the gyroscopes and accelerometers using atomic layer deposition (ALD) with a shadow mask57on capacitive readout electrodes (this may also be accomplished using lithography) (FIG. 11N). If used, the shadow mask57is firmly attached to the fused silica layer to prevent unwanted deposition. If lithography is used, the tungsten layer is lithographically patterned using a spray coated photoresist mask (not shown). Other layers of metals59′ serving as a temperature sensor, a heater, and electrical leads from the vertical feedthrough52to the tungsten layer, are deposited (e.g., via sputter or evaporative deposition) using a similar shadow masking deposition technique (FIG. 11O). This completes the fabrication of the gyro and accelerometers.

In the step shown inFIG. 11P, a conformal layer of Parylene-Al-Parylene65is deposited to serve as an HF mask. The mask is open at the resonator gap. The resonator is released using HF as shown by the void indicated at63. The HF mask is dry and wet etched, and the wafer is annealed again (e.g., at about 1000° C.) to remove moisture, organics, and ionic material trapped on the surface (FIG. 11Q). Then the silica wafer is aligned with a separately processed layer, and bonded using low-temperature (e.g., low thermal coefficient of expansion (TCE)) glass frit50. Electrical connections, as indicated by continuous feedthroughs52, between layers are formed using conformal deposition (e.g., sputtering) or solder paste (FIG. 11R).

The process described corresponding toFIGS. 11A-11Rabove is a suitable fabrication process. It is to be understood that other fabrication processes are within the purview of the present disclosure. It is further to be understood that various techniques (such as deposition techniques) within the process described above may also be substituted with other suitable techniques.

The MEMS device43may be a gyroscope. The main error sources of bias stability related to the mechanical structure are: scale factor change due to Q; frequency and temperature fluctuation; and sensitivity to vibration. Temperature is the main factor in variation of Q. Frequency change is dependent on both temperature and acceleration. Vibration sensitivity depends on the mode shape and the vibration isolating stage. In the disclosed architecture, the gyroscopes are integrated on a vibration and temperature isolating stage. As shown inFIG. 12, tuning-fork (TF) gyroscopes may be used in examples of the present disclosure. Driving and sensing modes of planar tuning fork gyroscope are shown at reference numerals66and67, respectively. Driving and sensing modes of a yaw tuning fork gyroscope are shown at reference numerals66′ and68, respectively. The TF architecture has advantages of simplicity, large effective mass, and large driving amplitude. However, in examples of the present disclosure, a ring gyroscope may be substituted for the TF gyroscope. As shown in Table 1 below, the disclosed gyroscopes have a mass of less than 600 μg, a simulated Q of greater than 1 million dominated by thermoelastic damping (TED), and an operating frequency of about 15 kHz. The operating frequency may be adjusted to reduce cross coupling between the sensors. The disclosed gyroscope may be configured to have mode separation between the parasitic modes and the drive or sensor greater than about 10%. Calculated performance with Finite Element Model (FEM) simulated Q factors is shown in Table 1. The overall Q of the tuning fork gyroscopes are substantially dominated by surface loss when the DRIE roughness is from about 10 nm to about 15 nm. If sidewall roughness is reduced to less than about 1.0 nm by annealing, other factors such as anchor loss or TED will dominate. To achieve the disclosed bias stability, temperature stability on the order of milli-degree is required. Such temperature control may be achieved using the methods disclosed herein. An open-loop mode may be used to produce a gyroscope with relatively higher sensitivity. A force-feedback mode may provide larger bandwidth.

The MEMS device43may include an accelerometer that includes resonant devices in the place of the standard capacitive configurations. High-Q fused silica may allow relative performance improvements over a standard capacitive configuration. Isolation platforms as disclosed herein may reduce environmental sensitivity that has typically impacted resonant sensors. A double-ended tuning fork (DETF) resonant accelerometer for in-plane signals, and a vertically-hinged resonant accelerometer for out-of-plane signals are disclosed herein. (SeeFIGS. 13A and 13B.) It is to be understood that in examples of the present disclosure, a clamp-clamp beam resonant accelerometer, a vertically-hinged resonant accelerometer, or an electrostatic non-resonant accelerometer may be substituted for the DETF accelerometer. InFIG. 13A, a double-ended tuning fork is depicted at reference numeral69. A force amplification lever is shown at reference numeral79. A support beam is shown at reference numeral81. InFIG. 13B, polysilicon hinges are depicted at reference numeral82, and a polysilicon torsional resonator is shown at reference numeral83. The accelerometers disclosed herein have relatively flexible vibrating tines85. The disclosed microfabrication process allows deposition of high-aspect ratio polysilicon which allows the relatively flexible vibrating tines85. The calculated performance specifications shown in Table 2 are based on flexible polysilicon tines85and hinges82.

The MEMS device43may include thermal-and-vibration-isolating platforms integrated with each of the sensors disclosed herein. (SeeFIGS. 14A and 14B.) InFIGS. 14A and 14B, an isolated mass86is shown loosely supported by long spring members87,87′. Isolating the sensors will reduce an acoustic cross-coupling effect, and allow individual tuning of a resonant frequency for each isolating platform. Further, isolating platforms will improve thermal impedance due to reduction of lead lines. The disclosed architecture achieves improvement in both mechanical and thermal aspects. From FEM simulation, lateral and rotational cutoff frequencies may be selected. As shown in Table 3, the selected lateral and rotational cutoff frequencies may range from about 2 kHz to about 10 kHz for a beam height of 100 μm. With a thinner beam height, the cutoff frequency may be further reduced.

Sense mode frequency shift of a lateral gyroscope due to electrical softening may be reduced by further improvements to the structure of the stage and the gyro-controlling architecture. A preliminary configuration for an example of a resonator achieves a cutoff frequency from about 1 kHz to about 3 kHz along a lateral translational mode. (The example of the resonator is sensitive in the lateral direction.) With the disclosed architecture, a thermal resistivity due to conduction of 105K/W may be achieved.

For shock protection, soft-material coatings (i.e. evaporated gold) may be disposed on all available MEMS device43surfaces as well as the cap inner surface36, the base inner surface26, the partition first surface76and the partition second surface77(seeFIGS. 1, 6 and 9).

FIG. 15depicts an example of an overall MEMS device43placement for an active area. In the example, the bottom MEMS device layer97includes three-axis gyroscopes98,99,100, and the top MEMS device layer92includes three-axis resonant accelerometers89,90,91and a clock resonator19. An x-axis accelerometer89, a y-axis accelerometer90, and a z-axis accelerometer91are show in the same (top) layer as resonator19. In the example depicted inFIG. 15, the top MEMS device layer92has a length93of about 8.3 mm (millimeters) and a width94of about 3.3 mm. Spacing96between the accelerometers89,90, and91is about 100 micrometers. The bottom device layer97includes an x-axis gyroscope with a platform98, a y-axis gyroscope with a platform99, and a z-axis gyroscope with a platform100. As depicted, the example has suspension beams with 100 μm width formed between every sensor and about the perimeter of the MEMS device layer for placing: 1) electrical leads, 2) nonlinear-beam/soft-coating shock stops along the lateral regions, 3) sensing electrode for the z-axis resonant accelerometer, and 4) a damper for acoustic energy isolation between sensors. Vertical feedthrough holes95are about 400 μm×400 μm. Both the cap layer30, the package base layer20will include shock protection/radiation shields (not shown) and bottom electrodes (not shown) for lateral tuning-fork gyros.

FIG. 16is a semi-schematic perspective diagram depicting and example of isolating stages101in a microsystem10″ according to the present disclosure. Three fused silica layers11are stacked to form the microsystem10″. A bonding seal ring150is shown at the perimeter. Vertical feedthroughs are shown at144.

FIG. 17is a semi-schematic perspective diagram depicting an example of MEMS devices43integrated with the isolating stages ofFIG. 16in a microsystem10″ according to the present disclosure.FIG. 17depicts 7 MEMS devices43integrated with 3 isolating stages101. In the example depicted inFIG. 17, the MEMS devices43include three gyroscopes98,99,100, three accelerometers89,90, and91, and a resonator19.

FIG. 18is a semi-schematic side cross-sectional view depicting an example of a TIMU according to the present disclosure. Materials in the example are depicted with different crosshatch patterns. The crosshatch pattern shown at102depicts fused silica;103depicts Poly-Si;104depicts metal for thermal compression bonding; and105depicts metal for electrodes and interconnects. It is to be understood that the mapping of crosshatch patterns to materials fromFIG. 18is not necessarily applicable to any other figures in this disclosure unless specifically stated herein. Isolation legs146support the tuning fork gyro148. Vertical feedthroughs144allow connection to the MEMS device layer40through the cap layer30. Bonding seal rings150are shown between the cap layer30and the MEMS device layer40and between the MEMS device layer40and the packaging base layer20.

FIG. 19is a semi-schematic top cross-sectional view depicting an example of the TIMU ofFIG. 18according to the present disclosure. The x-axis gyroscope98and the x-axis accelerometer89are shown on a common isolating stage101. The y-axis gyroscope99and the y-axis accelerometer90and the resonator19are also shown on the common isolating stage101adjacent to the isolating stage101associated with the x-axis. On the right side inFIG. 19, the z-axis gyroscope100and the z-axis accelerometer91are shown on a common isolating stage101. A bonding seal ring150is shown at the edge of the device layer. An approximate length93of the TIMU shown is about 7.3 mm, and an approximate width94is about 4.36 mm. The thickness (not shown) of the TIMU inFIG. 19is about 0.3 mm. Therefore, the volume of the TIMU shown inFIG. 19is about 9.55 mm^3 (cubic millimeters).

FIG. 20is a semi-schematic top cross-sectional view depicting a scaled example of a portion of the TIMU ofFIG. 19according to the present disclosure. The dimension depicted at94corresponds to the width94depicted inFIG. 19. The dimension shown at reference numeral108associated with isolating legs146is about 100 micrometers. The gyroscope98,99,100dimensions are depicted at reference numerals107and109are respectively about 2.0 mm and about 2.0 mm. Dimensions for other portions of the example of a TIMU may be approximated by their relative size inFIG. 20.

FIGS. 21A-21Ncollectively depict a semi-schematic side cross-sectional view depicting examples of steps in a process according to the present disclosure. It is to be understood that this process is suitable for devices with in-plane vibration modes only. A tuning fork gyro is given as an example in the process described below.

With particular reference toFIG. 21A, step1of the process is represented, which includes a pattern masking layer110and DRIE of a first fused silica wafer112. In examples, the pattern masking layer110may be nickel, Si, or poly-Si. In this example, a Si wafer114is non-permanent bonded to the first fused silica wafer112, but other bonding types may be used.FIG. 21Brepresents step2, which includes depositing poly-Si116to fill and narrow trenches in the fused silica layer112and dope the poly-Si. An example of filling a trench and narrowing a trench is indicated by reference numerals118and120, respectively.FIG. 21Crepresents step3, which includes timed etching of the poly-Si followed by chemical mechanical planarization (CMP) if desired (i.e., the CMP portion is optional). Reference numeral122indicates a portion of the material having been removed, depicting an exposed surface of the fused silica layer112. Step4is represented inFIG. 21Dand includes using a shadow mask to remove poly-Si from particular selected, which may depend upon a design application or an intended usage of the device. The selected regions are indicated by reference numeral124, depicting other exposed surfaces of the fused silica layer112. Step5is represented inFIG. 21Eand includes depositing a first metal layer126using a shadow mask to form electrodes and interconnects. In step6, as represented inFIG. 21F, the process includes depositing and patterning a second metal layer128for bonding and contacts.

Continuing in the process ofFIGS. 21A-21N, step7includes patterning a second fused silica wafer130in a manner similar to that discussed above (FIG. 21G). Step8includes bonding the first and second fused silica wafers (112and130, respectively) using, e.g., thermal compression bonding (FIG. 21H). Step9includes removal of the bottom Si wafer (FIG. 21I). It is to be understood that fused silica wafer112is the device layer in this example process. As shown in21I, the elements of the device layer112remain bonded after Si wafer removal. Reference numeral132indicates an exposed surface of fused silica wafer112where there is no longer a Si wafer. Step10includes depositing and patterning another metal layer134at portions of the back side of the device layer112for bonding (FIG. 21J). Step11includes patterning a third fused silica wafer136(FIG. 21K). As related to21L, step12includes bonding the third fused silica wafer136to the structure of step10. Step13includes removal of the top Si wafer (indicated by reference numeral138, which identifies a newly exposed surface) and patterning a metal layer140to form the contact pads (FIG. 21M). Step14relates toFIG. 21Nand includes removal of the bottom Si wafer (indicated by reference numeral142, which identifies another newly exposed surface). As shown in21N, with the conclusion of step14, a vertical feed-through is formed (e.g., at144), an isolation stage is developed (including isolation legs146), a tuning fork gyroscope is formed (indicated generally at148) within the isolation legs146, and a bonding ring150is included.

FIG. 22depicts a cutaway perspective view of an example of a TIMU according to the present disclosure. MEMS devices43are depicted on isolating stages in a microsystem10′″.FIG. 22depicts 7 MEMS devices43integrated with 3 isolating stages101. In the example depicted inFIG. 22, the MEMS devices43include three gyroscopes98,99,100, three accelerometers89,90, and91, and a resonator19. As illustrated by comparingFIG. 22andFIG. 17, a variety of arrangements of the MEMS devices43is disclosed herein.

FIGS. 23A-23Gare representative of a process flow for devices with an out-of-plane vibration mode. It is to be understood that devices with these requirements may need about three extra masks. The steps described here will be carried out after steps1-9discussed above (i.e., after21I). Therefore these steps will be referred to as step9.1,9.2, etc. Step9.1represented byFIG. 23Aincludes patterning metal156on the back side of the device layer112including one portion of the metal156serving as an electrode158. Note that the patterning does not reach the region of the proof mass and supporting beams. Step9.2includes preparing a fused silica wafer160with patterns as indicated byFIG. 23B. Also note the portion of the fused silica wafer160serving as an electrode161. Step9.3includes bonding as shown inFIG. 23C, bringing together fused silica wafer112with fused silica wafer160. Step9.4includes thinning the bottom fused silica wafer160to result in thinned fused silica wafer160′ as shown inFIG. 23D. Step9.5includes patterning the bottom fused silica wafer as shown inFIG. 23E, exposing portions of fused silica wafer160′ as indicated at reference numeral162. It is to be understood that step9.5may be accomplished prior to step9.4.

Moving forward in this example process, step10corresponds to the previously discussed step10. CompareFIG. 23FtoFIG. 21J. Step10includes depositing and patterning another metal layer134at the backside of the device layer for bonding and contacts. Steps11-14correspond to that discussed above, including the results as shown inFIG. 23G, adding another fused silica layer162. Note that the cavity and thickness of the fused silica wafer162is slightly exaggerated as compared to the previous structure. A device with an out-of-plane vibration mode is represented at reference numeral164.

FIGS. 24A-24Eare semi-schematic side cross-sectional views depicting examples of steps in a process for fabricating a MEMS clock device. It is to be understood that this process may require about 13 masks. In Step11as indicated inFIG. 24A, the process includes a pattern masking layer166and DRIE of a fused silica wafer168. Step12is represented inFIG. 24Bincluding depositing and patterning doped poly-Si, SiN and SAC ox. It is to be understood that this depositing and patterning is to fill a via, creating embedded protective SIN and SAC ox, and is also to narrow a gap in the fused silica wafer168. The poly-Si is indicated by reference numeral174. Note the filled via at170and the narrowed gap at172. Step13(FIG. 24C) includes patterning the Poly-Si174to create a poly plate176for process and to create solder bond protective walls178. Step14(FIG. 24D) includes patterning a heater/temperature sensor115, and solder180on the backside as indicated inFIG. 24D. Note the solder at180. Step15is represented inFIG. 24Eand includes application of the resonator process182and includes patterning solder184on top. Also included is the removal of the refilled poly on the support/VIS beam. It is to be understood that at the conclusion of step15, the MEMS device clock (DEV1) is ready for bonding.

FIGS. 25A-25Eare semi-schematic side cross-sectional views depicting examples of steps in a process for fabricating a MEMS gyroscope/accelerometer device according to the present disclosure. It is to be understood that this process may require about 8 masks. Step21, as indicated inFIG. 25A, includes a pattern masking layer186and DRIE of a fused silica wafer188. Step22is represented inFIG. 25Band includes depositing doped poly-Si194to fill a via (the filled via indicated by reference numeral190) and to create narrowed gaps in the fused silica wafer (the narrowed gaps indicated by reference numeral192). Step23(FIG. 25C) includes patterning Poly194to create solder bond protective walls indicated by reference numeral196inFIG. 25C. Step24(FIG. 25D) includes patterning a heater, temperature sensor, and solder on the backside. Note the solder at198. Step25is represented inFIG. 25Eand includes application of the resonator process200and patterning of solder202on top along with removal of refilled poly on the support/VIS beam. It is to be understood that at the conclusion of step25, the gyroscope/accelerometer (DEV2) is ready for bonding.

FIGS. 26A-26Eare semi-schematic side cross-sectional views depicting examples of steps in a process for fabricating cap layers according to the present disclosure. Steps31-33will discuss fabrication of a Cap3, and Steps41-42will discuss fabrication of a Cap4. Step31, as indicated inFIG. 26A, includes a pattern masking layer204and DRIE of a fused silica wafer206. Step32is represented inFIG. 26Band includes depositing doped poly-Si210to fill a via (the filled via indicated by reference numeral208). Step33is represented inFIG. 26Cand includes patterning poly210to create solder bond protective walls212. Step33also includes patterning solder214, etching a recess (edge of recess indicated by reference numeral216), and depositing a getter218. At this point, Cap3is ready for bonding. Now referring toFIG. 26D, Step41includes depositing and patterning poly-Si on a fused silica wafer219for solder bond protective walls220. Step42, represented inFIG. 26E, includes patterning solder222, etching a recess (edge of recess indicated by reference numeral224) and depositing a getter226. At this point, Cap4is ready for bonding.

FIG. 27is a semi-schematic side cross-sectional view depicting an example of feedthroughs (indicated at reference numeral144) in a microsystem according to the present disclosure. Materials in the example are depicted with different crosshatch patterns. The crosshatch pattern shown at102depicts fused silica;103depicts Poly-Si,104depicts metal for thermal compression bonding; and105depicts metal for electrodes and interconnects. It is to be understood that the mapping of crosshatch patterns to materials fromFIG. 27is not necessarily applicable to any other figures in this disclosure unless specifically stated herein. The microsystem shown includes fused silica layers206,168,188, and219. The microsystem ofFIG. 27includes devices as indicated at reference numeral163. The devices163may include a clock, accelerometer and gyroscope. In this example, vertical feedthroughs144run from top cap206to bottom cap219allowing connection to the device layers168,188. Shown also are legs of an isolating stage146and a bonding seal ring150.

FIG. 28is a semi-schematic top view depicting an example of a TIMU with vias according to the present disclosure. An x-axis gyroscope98and an x-axis accelerometer89are shown on a common isolating stage101. The y-axis gyroscope99and the y-axis accelerometer90are shown on the common isolating stage101adjacent to the isolating stage101associated with the x-axis. A bonding seal ring150is shown at the edge of the device layer. Surrounding the bonding seal ring150is a saw street111to allow space for dicing. A poly-Si filled via170is depicted with solder stops.

InFIG. 28, a poly-Si filled via170is shown having solder bond protective walls178on opposite sides of each filled via170. Support beam81is shown with conductors62disposed as linear traces on the support beam81. Conductors62are also shown as traces leading to the poly-Si filled vias170along the top edge as shown in the enlarged portion ofFIG. 28.

FIG. 29is a semi-schematic cutaway perspective view depicting an example of a TIMU according to the present disclosure. An edge has been cut away vertically to reveal surface117. Poly-Si filled vias170are depicted connecting the MEMS device layers40to external conductor pads152on the cap layer30.

FIG. 30is a semi-schematic perspective view depicting a portion of conductive elements in an example of a TIMU according to the present disclosure. Solder reflow protective bonds178are shown on opposite sides of each filled poly-Si filled via170.

FIG. 31is a semi-schematic side cross-sectional view depicting an example of laser trimming in a process for fabricating a microsystem according to the present disclosure. In this example, a top glass cap230is shown adjacent to a first device layer232. A second device layer234is adjacent to the first device layer232, distal to the top glass layer230. A bottom glass cap236is adjacent to the second device layer236, distal to the first device layer232. A light beam238, e.g., a laser light beam, is shown laser trimming a device in the first device layer232through the top glass cap230. Similarly, a light beam240is shown laser trimming a device in the second device layer234through the bottom glass cap236. It is to be understood that the caps230,236are optically transmissive for the light wavelength of the light beam238,240.

FIGS. 32A-32Gare semi-schematic side cross-sectional views depicting examples of steps in a process for fabricating a microsystem according to the present disclosure. With reference toFIG. 32A, the process includes establishing a first fused silica substrate250. The first fused silica substrate250may be about 200 micrometers thick. The first fused silica substrate may have recesses etched in one or both of its surfaces, i.e. it may not be planar (not shown). The process further includes patterning a thin metal252to dispose a first electrode and conductor on the fused silica substrate250. The process still further includes patterning a thick metal254to dispose a first thermal compression bonding layer on the thin metal252. With reference toFIG. 32B, the process includes establishing a second fused silica substrate256. The second fused silica substrate may be about 500 micrometers thick. The process further includes bonding the first fused silica substrate250to the second fused silica substrate256. It is to be understood that the first thermal compression bonding layer and a mounting layer are between the first fused silica substrate250and the second fused silica substrate256as represented by reference numeral258. The first fused silica substrate250may be ground to about 50 micrometers thick.

With reference toFIG. 32C, the process includes applying deep reactive-ion etching (DRIE) to pattern the first fused silica substrate and form an undercut119in the mounting layer258. As represented byFIG. 32D, the process further includes patterning sputtered metal260to dispose a second electrode and conductor on the first fused silica substrate250and on a portion of the mounting layer258. The process still further includes depositing a second thick metal262on the second electrode and conductor to dispose a second thermal compression bonding layer.

In one example according to this process indicated byFIG. 32E, the process further includes releasing a microelectromechanical system (MEMS) device layer264from the mounting layer258, cleaning the MEMS device layer264using solvent, and baking the MEMS device layer to evaporate solvent from the MEMS device layer264. In another example according to this process indicated byFIG. 32F, the process further includes dicing a plurality of MEMS devices on the second fused silica substrate256to separate the plurality of MEMS devices. It is to be understood that the dicing process (not shown) may include separating a plurality of devices from the second fused silica substrate into individual MEMS devices.

With reference toFIG. 32G, the process further includes establishing a bottom cap266, stacking a MEMS device layer264on the bottom cap266, stacking a top cap268on the MEMS device layer264, and applying pressure and heat to create a thermal compression bond between the bottom cap266, the MEMS device layer264; and the top cap268. As shown, example microsystems may include multiple device layers for various purposes, indicated generically by reference numeral40. Further, in this example, a getter270is included in the cap layer268.

It is to be understood use of the words “a” and “an” and other singular referents may include plural as well, both in the specification and claims, unless the context clearly indicates otherwise.

It is to be understood that the ranges provided herein include the stated range and any value or sub-range within the stated range. For example, a range from about 1 kHz to about 3 kHz should be interpreted to include not only the explicitly recited limits of about 1 kHz to about 3 kHz, but also to include individual values, such as 1500 Hz, 2000 Hz, 2500 Hz, etc., and sub-ranges, such as from about 1000 Hz to about 2100 Hz, from about 1800 Hz to about 1950 Hz, etc. Furthermore, when “about” is utilized to describe a value, this is meant to encompass minor variations (up to +/−10%) from the stated value.

It is to be understood that the terms “connect/connected/connection” and/or the like are broadly defined herein to encompass a variety of divergent connected arrangements and assembly techniques. These arrangements and techniques include, but are not limited to (1) the direct communication between one component and another component with no intervening components therebetween; and (2) the communication of one component and another component with one or more components therebetween, provided that the one component being “connected to” the other component is somehow in operative communication with the other component (notwithstanding the presence of one or more additional components therebetween).

While several examples have been described in detail, it will be apparent to those skilled in the art that the disclosed examples may be modified. Therefore, the foregoing description is to be considered non-limiting.