Feedback-controlled biased inverting limiter for RFI suppression

A method and apparatus is provided for reducing interference in a communication system. A feedback-controlled biased inverting limiter is used to reduce interference power by trapping the interfering signal, while passing the wanted signal through to the output. The amplitude trap triples the frequency of a signal component of a particular amplitude, thus shifting it out of the communication band and into the stopband of the receiver or transponder filter. The feedback-controlled biased inverting limiter uses a hard limiter, window comparator, feedback loop, and an exclusive NOR gate to trap the interfering signal, while allowing the wanted signal to pass through to a receiver.

FIELD

The present disclosure relates generally to communication systems, and more specifically, to techniques for reducing interference in communication systems.

BACKGROUND

In various types of communication systems, electromagnetic interference may cause problems with the operation of the communication system. Generally, electromagnetic interference is a disturbance that can affect the operation of a circuit due to electromagnetic induction or electromagnetic radiation emitted from an external source. In a communication system, electromagnetic interference may cause the degradation or loss of data. Exemplary sources of electromagnetic interference include other electronic devices, undesired wireless signals, radio jamming signals, as well as natural phenomenon.

One example of a radio-frequency interference (RFI) suppression technique is described in U.S. Pat. No. 5,742,900 (Arnstein, et al.), which is incorporated by reference herein. In this example, a biased inverting limiter is used to reduce interference. This example requires two signal paths; one path to estimate the amplitude envelope of the interference signal, and a second path to process with the nonlinear biased inverting limiter acting as the “amplitude trap”. A carefully calibrated bulk delay line and compensating linear amplifier are required in the second, nonlinear processing path to match the group delay of the control path.

The requirement of a delay element in the nonlinear RF signal path is problematic for implementation, as is the linear booster amplifier to compensate for the attenuation inherent in practical delay elements. In an interference environment, linear amplifiers early in the receiver signal chain are already vulnerable to saturation or undesirable nonlinear effects.

SUMMARY

An apparatus is provided for reducing interference in an input signal, the input signal having a wanted signal and a larger interference signal, the circuit including a hard limiter circuit coupled to the input signal for detecting the polarity of the input signal, a window comparator circuit coupled to the input signal for detecting when the absolute value of the amplitude of the input signal exceeds a threshold value, and generating a pulse-width modulated rectangular wave output signal, a feedback circuit coupled to an output of the window comparator for generating a control signal that controls the duty cycle of the pulse-width modulated rectangular wave output signal, and a logic circuit having a first input coupled to the hard limiter circuit, a second input coupled to the window comparator circuit, and an output, wherein an output signal of the logic circuit includes the wanted signal at a first frequency and the interference signal at a second, higher frequency.

Another embodiment provides a method of reducing interference in an input signal having a wanted signal and an interference signal, the method including detecting the polarity of the interference signal, detecting when the absolute value of the amplitude of the interference signal exceeds a threshold value to generate a pulse-width modulated rectangular wave signal having a frequency higher than the interference signal, using the detected polarity and the generated pulse-width modulated rectangular wave signal to generate an output signal containing the wanted signal at first frequency and the interference signal at a second, higher frequency, and filtering out the second frequency to create a filtered output signal.

Another embodiment provides an RFI suppression system including a hard limiter circuit coupled to an RF input signal, a window comparator circuit coupled to the RF input signal, a feedback circuit coupled to the output of the window comparator for controlling the duty cycle of the output of the window comparator, and a logic circuit having inputs coupled to outputs of the hard limiter and window comparator circuits and having an output coupled to a radio receiver.

Other features and advantages of the present disclosure will be apparent from the accompanying drawings and from the detailed description that follows below.

DETAILED DESCRIPTION

In general, the present disclosure describes a circuit and method for reducing interference in a communication system, such as a wireless communication system. As is described in detail below, a biased inverting limiter RFI suppression system is used which reduces manufacturing and maintenance costs through simplification and self-adaptation of the control path. In one example, an RFI suppression system uses a feedback control path within a biased inverting limiter to achieve various advantages. In one example, an RFI suppression system is used that does not require a separate signal path to derive the biased inverting limiter control parameter, or a delay element and linear booster amplifier in the signal path of the biased inverting limiter. In another example, an RFI suppression system is used that reduces the sensitivity of a biased inverting limiter to implementation variations, environmental factors such as temperature, or effects on the implementation due to aging.

While the system and methods described below may be applied to any desired system that would benefit from interference reduction, the system and methods will be described in the exemplary context of wireless communication systems. For example, the techniques disclosed may be used with wireless communication systems that operate in a high noise environment due to other wireless communication systems, jamming signals, spurious emissions from other electronic equipment, etc.

Generally, a feedback-controlled biased inverting limiter is used to reduce interference power by trapping an interfering signal, while passing a wanted signal through to a receiver. In one example, the amplitude trap increases the frequency of a signal component of a particular amplitude (in one example, tripling the frequency), thus shifting it out of the communication band and into the stopband of the receiver or transponder filter. In one example, the feedback-controlled biased inverting limiter uses a hard limiter, window comparator, and an exclusive NOR gate to trap the interfering signal, while allowing the wanted signal to pass through to the receiver.

FIG. 1is a block diagram of an example of an RFI suppression system used with a radio receiver.FIG. 1shows a wireless communication system10. A feedback-controlled biased inverting limiter12(described in detail below) is coupled between an antenna14and a radio16. The radio16includes a low noise amplifier (LNA)18and a tuner and demodulator20. For clarity, other conventional components of the radio receiver16are not shown, as one skilled in the art would understand. Similarly,FIG. 1also does not show a transmit path. The feedback-controlled biased inverting limiter12suppresses RFI interference, improving the performance of the radio receiver16. The communication system10also includes an optional bypass loop, including one or more RF switch(es) S1, which can be activated to bypass the feedback-controlled biased inverting limiter12, if desired. In one example, the switch S1is activated via a control line21by the limiter12, or other controller. For example, if the feedback-controlled biased inverting limiter12is being used to suppress RFI from a jamming signal, it may be desirable to bypass the feedback-controlled biased inverting limiter12at times when the controller determines that a jamming signal is not present. Of course, other ways of bypassing or disabling the feedback-controlled biased inverting limiter12are also possible.

FIG. 2is a block diagram of an example of an RFI suppression system that is integrated into a radio receiver.FIG. 2shows a wireless communication system22. In this example, a feedback-controlled biased inverting limiter (described in detail below) is integrated with an LNA, as shown in block24. The feedback-controlled biased inverting limiter/LNA24is coupled between an antenna26and a tuner and demodulator28. Like before, for clarity, other conventional components of the radio receiver (and transmitter) are not shown, as one skilled in the art would understand. As before, the feedback-controlled biased inverting limiter suppresses RFI interference, improving the performance of the radio receiver. The communication system22may also includes a bypass loop similar to that shown inFIG. 1, which can be activated to bypass the feedback-controlled biased inverting limiter, if desired.

FIGS. 3A and 3Bare block diagrams of examples of the feedback-controlled biased inverting limiter shown inFIGS. 1 and 2.FIGS. 3A and 3Beach show a feedback-controlled biased inverting limiter30having an input32and an output34. In the exemplary implementation shown inFIG. 1, the input32would be coupled to the antenna, and the output34to the radio receiver.

In these examples, the biased inverting limiter30includes an exclusive-NOR gate (XNOR)34having two inputs coupled to two comparator circuit elements operating on the RF input signal (at input32). The RF input signal includes the desired signal, plus interference. A first input of the XNOR34is coupled to the output of a hard limiter36. The hard limiter36is a comparator circuit that uses zero for its reference, thus indicating when the input signal has either a positive or negative polarity. The output of the hard limiter36is a digital signal that will be high (VOH) when the input signal is greater than zero, and low (VOL) when the input signal is less than zero.

A second input of the XNOR34is coupled to the output of a window comparator38. The window comparator38is a comparator circuit that is a compound comparator in an arrangement known in the art as a window comparator, interval test, or limit comparator. One having ordinary skill in the art may implement this function in a number of ways. In one example, the input voltage is compared with two thresholds, in this example, the thresholds (Vt′, −Vt) are additive inverses of each other. Therefore, the output of the window comparator38indicates when the absolute value of the input voltage is greater than the threshold (control) input (Vt).FIGS. 3A and 3Balso show a loop filter40, a summing element42, and a bandpass filter44(discussed below).

In the example ofFIG. 3A, a duty cycle discriminator41is coupled between the output of the window comparator38and the summing element42. The duty cycle discriminator41is a circuit that provides an output that is a monotonically increasing function of the duty cycle of the input. In one example, the duty cycle discriminator outputs a DC value that is proportional to the duty cycle of its input. The summing element42subtracts the desired duty cycle input (in this example, ⅓) from the output of the duty cycle discriminator41. As is described in more detail below, the loop filter40uses the output of the summing element42to generate the appropriate control signal Vt.FIG. 3Bis an example of one implementation of the circuit shown inFIG. 3A(described below).

FIG. 4is a timing diagram showing a typical response to a sinusoidal input signal by the window comparator, hard limiter, and XNOR gate. As shown inFIG. 4, a sinusoidal input signal50having a frequency fois present at the input of the window comparator and hard limiter (input32inFIG. 3B). Whenever the amplitude of the input signal50reaches +/−Vt, the output (signal52) of the window comparator is high. The output is low at other times.

The window comparator38can be visualized as converting an input signal of amplitude A at some center frequency fo, to a pulse-width modulated rectangular wave of frequency 2fo. The pulse width, or duty cycle, of the rectangular wave output is dependent upon A and Vt, and the interaction of other signals and noise in the frequency band. If the input signal is comprised of multiple signals, the fundamental frequency of the window comparator output is twice that of the dominant (largest amplitude) input component.

The output signals of the comparators36and38are digital, or logic output signals having two states, represented by a high voltage (VOH) and a low voltage (VOL). The outputs of the hard limiter36and the window comparator38are combined via the XNOR34to produce the desired biased inverting limiter function. Comparators can also be implemented with current outputs rather than voltages: ordinary skill is all that is required to design the system for the appropriate circuit element choices.

As shown inFIG. 4, the output of the hard limiter (signal54) is high when the input signal50is greater than zero, and is low when the input signal50is less than zero.FIG. 4also shows the output of the XNOR34(signal56). The output of the XNOR34will be high whenever its two inputs (signals52and54) are either both high, or both low. A transfer function can also help to illustrate the relationship between the input signal50and the output signal56.FIG. 5is an input to output transfer function illustrating the relationship between the output signal56and the input signal50. As shown inFIG. 5(as well as inFIG. 4), the output signal56is either high or low, depending on the voltage of the input signal50.

In this example, the XNOR output signal56is a rectangular wave having a frequency of 3fo, and a duty cycle dependent on the amplitude A of the input signal and the value of threshold voltage Vt′. In the example shown inFIG. 4, the control voltage Vtis at an optimal value for suppression of the sinusoidal input signal, that is, the duty cycle of the output of the XNOR is approximately 50%, with a pulse width approximately ⅙ the period T of the input signal.

Note that the window comparator38produces an output (signal52inFIG. 4) with spectral components at baseband (low frequencies including DC), and at even multiples of the input frequency. In particular, the DC value of the output signal varies from VOHto VOLas Vtis varied from 0 to A, the peak amplitude of the input sinusoid, and remains at VOLfor Vtgreater than A. The relationship follows an arc sine function (equation (1) below), and is represented in the diagram ofFIG. 6, which plots the DC component of the window comparator output as a function of the ratio of threshold control voltage to input signal peak amplitude.

Referring toFIGS. 3 and 4, in one example, the technique described above uses the baseband component of the window comparator output52as the error term for a feedback control path. As shown inFIG. 3B, the feedback control path comprises the loop filter40and the summing element42. The desired DC value (described below) for optimum RFI suppression is subtracted from the error signal (the output of the window comparator38) by the summing element42. The resultant difference is then used as an input to the loop filter40to generate the control voltage Vt, which is used by the window comparator38, as illustrated inFIG. 4. The DC level of the window comparator output has a monotonically non-positive slope as a function of Vt, thereby ensuring negative feedback stability for positive loop gain.

Conventional control system design techniques can be employed to design the loop filter40to meet desired performance goals, such as response time, steady-state error, settling time, percent overshoot, frequency response, etc. The loop filter40may be implemented with passive devices, active devices, digital or analog circuitry, as desired.

In one example, the loop filter40is implemented with 1) a low-pass filter to isolate the baseband component of the window comparator output, and 2) an ideal integrator to ensure zero DC steady-state error. Furthermore, the control DC value for optimum RFI suppression is selected to cause the window comparator output due to the interfering signal to be asserted for one third (⅓) of the time (i.e. a duty cycle of ⅓). In other words, Vtis set to cause the output of the window comparator38to have a pulse width equal to ⅙ of the period of input signal50, like that shown inFIG. 4. This goal is met when the control DC level is equal to:

VOH+2⁢VOL3,(2)
which is shown inFIG. 3Bas an input to the summing element42(to be subtracted from the output of the window comparator38).

Referring again toFIG. 6, this optimal operating point is illustrated by the intersection of the curve and the value of equation (2). The control signal DC level is derived from VOHand VOLfor the logic circuits involved. For example, if the output voltages of the window comparator are +3.0 V when the absolute value of the input is greater than the threshold Vt, and 0 V otherwise, then the DC control value for optimum RFI suppression is 1.0 V (using equation (2) above).

An examination of the timing diagram ofFIG. 4illustrates how the biased inverting limiter reduces RFI. A periodic input signal with fundamental frequency fo(signal50), produces a square wave output (i.e. rectangular wave with 50% duty cycle) with fundamental frequency 3fo(signal56). The proper duty cycle required to sustain this condition is maintained by the feedback control loop. Bandpass variations of frequency and phase of the signal have no effect on the duty cycle of the signal, and therefore do not diminish the effectiveness of the RFI suppression.

The presence of additional signals at the input of the biased inverting limiter is manifested as variations in the amplitude and phase of the input signal50, which produce variations in the duty cycle and phase of the output rectangular wave (signal56). These variations pass through the radio receiver's bandpass filter44as the desired signal. They also produce non-DC baseband components in the window comparator38output which may be exploited as wanted in the loop filter40.

FIGS. 7-9are exemplary representations of frequency spectra of the feedback-controlled biased inverting limiter described above.FIG. 7shows an exemplary spectrum of the input of the feedback-controlled biased inverting limiter.FIG. 7shows phase-modulated interference spectrum60and a desired signal spectrum62near frequency fo. Without the RFI suppression techniques described above, the interference may make it difficult or impossible to use the desired signal62.FIG. 8shows the frequency spectrum at the output of the window comparator38, which includes a DC component64and interference66at frequency 2fo.FIG. 9shows the frequency spectrum at the output of the XNOR gate34. As shown, the interference68is centered at 3fo, where it will not cause any problems, since it will not pass through the bandpass filter of the receiver. The desired signal70is still at fo, along with residual intermodulation interference72. The residual interference72near fomay not cause any problems, but may be filtered out, if desired.

Thus, the feedback-controlled biased inverting limiter performs RFI mitigation without 1) an envelope detector, 2) a parallel signal path for estimating envelope, or 3) delays and gains associated with an estimation signal path, as are taught in some prior art solutions.

In some examples, the control loop filter40may also incorporate nonlinear behavior, such as a control algorithm to autonomously determine if RFI suppression is needed. This may be as simple as another comparator circuit element observing the Vtoutput of the loop filter40presented to the window comparator38. In this example, the output of the comparator circuit operates an RF switch (for example, switch S1inFIG. 1) to select an alternate low-noise amplifier (LNA) path, or the RFI suppression path. More complicated algorithms may be implemented in analog circuits, a digital computer or logic, if desired.

In some examples, the hard limiter and XNOR circuits can behave as an LNA for small signal input. In this example, the controller does not permit Vtto go below a certain value, corresponding to an input RF level in which interference power is not harmful. Because the Vtthreshold is high enough never to activate the window comparator, the composite input signal is simply amplified by the linear characteristic of the limiter and XNOR circuits.

The circuit described above also allows for self-calibration. To self-calibrate, a test signal can be injected at the biased inverting limiter input32, while the output is monitored by a computer or signal processing circuit. The computer or signal processing circuit can then adjust the control voltage Vtto cause the test signal to be completely eliminated from the output. This adjustment may be desirable due to age-related drifting of electronic component parameters, or even to permit the use of lower-cost components or methods in the construction of the circuit.

The biased inverting limiter RFI suppression system described above provides numerous benefits. For example, in contrast to some prior art solutions, the need for a separate RFI estimation signal path is obviated. Similarly, the need for a lossy bulk delay element and associated linear gain function are likewise obviated. Manufacturing and age-related variations of circuit elements can be compensated by the feedback loop for more stable performance for the life of the equipment. Well-understood and practiced techniques can be employed in the design of the loop filter in order to achieve desired system behavior goals. Manufacturing and maintenance costs are likewise reduced due to simplification and elimination of delicate elements such as the bulk delay and additional signal analysis path.

As mentioned above, the techniques described may be used with wireless communication systems to deal with RFI due to other wireless communication systems, jamming signals, spurious emissions from other electronic equipment, etc. The biased inverting limiter RFI suppression system described above also enables a related application, a dual-use spectrum system. In such a system, two or more communication systems can simultaneously share a common frequency spectrum.FIG. 10is a block diagram of an exemplary dual-use spectrum system. In this example, two communication systems operate over the same (or close) frequency spectrum.FIG. 10shows a first transmitter70(“transmitter A”) and a second transmitter72(“transmitter B”).FIG. 10also shows corresponding receivers74and76. While both transmitters70and72operate over the same frequency range, transmitter70transmits at a higher power than transmitter72. Using the techniques described above, each receiver74and76is able to suppress the unwanted signal, and receive and process the wanted signal.

The receiver74, which desires to receive the higher power signal A from transmitter70, can suppress the lower power signal B from the transmitter72using a hard limiter, similar to a conventional FM receiver. The receiver76, which desires to receive the lower power signal B from transmitter72, can suppress higher power signal A from the transmitter70using the feedback-controlled biased inverting limiter described above with respect toFIGS. 1-3. From the perspective of receiver76, signal A from transmitter70is interference. As described above, the feedback-controlled biased inverting limiter is able to suppress the stronger signal A from the transmitter70, while allowing the receiver76to receive and process the desired signal B from transmitter72. In another example, large and small signals can be combined prior to transmission, analogous to conventional multi-signal transponders, and received separately, as described above.