Vertical metal insulator metal capacitor

A semiconductor device and a method are disclosed herein. The semiconductor device includes a device die, a molding layer surrounding the device die, a plurality of first vertical conductive structures formed within the molding layer, and a plurality of second vertical conductive structures formed within the molding layer. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and an insulating structure is formed between the first vertical conductive structures and the second vertical conductive structures.

BACKGROUND

Capacitors are widely used in integrated circuits. The capacitance of a capacitor is proportional to the capacitor area and the dielectric constant (k) of the insulation layer, and is inversely proportional to the thickness of the insulation layer. Therefore, to increase the capacitance, it is preferable to increase the area and k value and to reduce the thickness of the insulation layer.

A problem associated with the increased area is that a greater chip area is required. Conventional metal-insulator-metal (MIM) capacitors in integrated circuits have various horizontal comb structures. The horizontal structure capacitance correlates with inter-metal layer thickness. However, the thickness of an inter-metal layer is very difficult to control. This results in high variation of MIM capacitance in production for a target value. Accordingly, new methods and structures are desired for MIM capacitors.

DETAILED DESCRIPTION

In this document, the term “coupled” may also be termed as “electrically coupled”, and the term “connected” may be termed as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

FIG. 1is a schematic diagram illustrating a semiconductor structure100including a vertical capacitor in accordance to some embodiments of the present disclosure.

As illustratively shown inFIG. 1, the semiconductor structure100includes electrodes120and140. The electrode120includes a conductive plane122and vertical conductive structures124. The electrode140includes a conductive plane142and vertical conductive structures144. The vertical conductive structures124and the vertical conductive structures144are interlaced with each other, and a dielectric material160is filled between the electrode120and the electrode140.

The conductive plane122and the conductive plane142include conductive material, including, for example, copper, silver, gold, and the like. In some embodiments, the conductive plane122and the conductive plane142include other suitable conductive material other than metal.

Reference is made toFIG. 2.FIG. 2is a schematic diagram illustrating an integrated Fan-Out (InFO) package200including the semiconductor structure100as illustrated inFIG. 1in accordance with some embodiments of the present disclosure. With respect to the embodiments ofFIG. 1, like elements inFIG. 2are designated with the same reference numbers for ease of understanding.

For illustration, the package200includes a polymer base layer203, an InFO backside redistribution layer (RDL)204, a seed layer205, a conductive material206, conductive through molding via (TMV)207, a device die208, a molding layer209, a conductive layer210, polymer layers211,213, and215, redistribution layers (RDLs)212and214, Under Bump Metallurgies (UBMs)216, and an external connectors217.

As illustratively shown inFIG. 2, in some embodiments, the semiconductor structure100shown inFIG. 1is formed in the integrated Fan-Out (InFO) package200. Since the semiconductor structure100is fabricated simultaneously with other features of the package200, the manufacturing cost is relatively low.

For illustration, the semiconductor structure100includes vertical conductive structures124formed within the molding layer209and electrically coupled to the conductive plane122, and vertical conductive structures144formed within the molding layer209and electrically coupled to the conductive plane142. The conductive plane142is disposed over the molding layer209. The vertical conductive structures124and144are formed by the conductive material206overlying the seed layer205, which is filled within the through molding vias (TMVs) extending through the molding compound (MC). The conductive plane122is formed within the InFO backside RDL204. The conductive plane142is formed within the RDL212, and the device die208and the conductive plane142are electrically coupled via the RDL214.

In some embodiments, the vertical conductive structures124and the vertical conductive structures144have a square shape, a rectangular shape, a circular shape, an oval shape, any other suitable shape in a cross section, or any combinations thereof. The vertical conductive structures124are distributed uniformly on the conductive plane122, and the vertical conductive structures144are distributed uniformly under the conductive plane142. In some embodiments, the vertical conductive structures124are distributed in a square grid pattern on the conductive plane122, and the vertical conductive structures144are distributed in a square grid pattern under the conductive plane142.

In some embodiments, the molding compound MC is applied in the molding layer209to surround the device die208, the vertical conductive structures124and the vertical conductive structures144on the polymer base layer203. Alternatively stated, in some embodiments, the molding compound MC in the integrated Fan-Out (InFO) package200is filled between the vertical conductive structures124and the vertical conductive structures144as the dielectric material160shown inFIG. 1. In some embodiments, the molding compound MC includes high-k polymer or silica.

In some embodiments, the polymer layer211overlies the molding layer209. The RDL212overlies the polymer layer211. The polymer layer213overlies the RDL212. The RDL214overlies the polymer layer213. The polymer layer215overlies the RDL214. The Under Bump Metallurgies (UBMs)216are formed over the RDL214. The external connectors217are disposed on the UBMs216and configured to be the input/output (I/O) pads, including, for example, solder balls, to electrically connect to the device die208through the RDL214. In some embodiments, the external connectors217are ball grid array (BGA) balls, controlled collapse chip connector (C4) bumps, or the like. In some embodiments, the connectors217are used to electrically connect package200to other package components including, for example, another device die, interposers, package substrates, printed circuit boards, a mother board, or the like.

FIG. 3is a flowchart illustrating a method300of forming the Integrated Fan-Out (InFO) package200as illustrated inFIG. 2, in accordance with some embodiments of the present disclosure. For better understanding of the present disclosure, the method300is discussed in relation to the semiconductor structure100shown inFIGS. 1-2, but is not limited thereto.

For illustration, the manufacturing process of the Integrated Fan-Out (InFO) package200illustrated inFIG. 2is described by the method300together withFIGS. 4-19.FIGS. 4-19are cross sectional views of the Integrated Fan-Out (InFO) package200at different stages of the manufacturing process, in accordance with some embodiments of the present disclosure. After the different stages inFIGS. 4-19, the package200has the cross sectional view inFIG. 2. AlthoughFIGS. 4-19are described together with the method300, it will be appreciated that the structures disclosed inFIGS. 4-19are not limited to the method300. Like elements inFIGS. 4-19are designated with the same reference numbers for ease of understanding.

With reference to the method300inFIG. 3, in operation S310, the carrier201, the adhesive layer202, and the polymer base layer203are provided, as illustrated inFIG. 4.

In some embodiments, the carrier201includes glass, ceramic, or other suitable material to provide structural support during the formation of various features in device package. In some embodiments, the adhesive layer202, including, for example, a glue layer, a light-to-heat conversion (LTHC) coating, an ultraviolet (UV) film or the like, is disposed over the carrier201. The polymer base layer203is coated on the carrier201via the adhesive layer202. In some embodiments, the carrier201and the adhesive layer202are removed from the InFO package after the packaging process. In some embodiments, the polymer base layer203is formed of PolyBenzOxazole (PBO), Ajinomoto Buildup Film (ABF), polyimide, BenzoCycloButene (BCB), Solder Resist (SR) film, Die-Attach Film (DAF), or the like, but the present disclosure is not limited thereto.

With reference to the method300inFIG. 3, in operation S320, subsequently, the InFO backside redistribution layer (RDL)204is formed, as illustrated inFIG. 5. In some embodiments, the backside RDL204includes conductive features, including, for example, conductive lines and/or vias, formed in one or more polymer layers. In some embodiments, the polymer layers are formed of any suitable material, including PI, PBO, BCB, epoxy, silicone, acrylates, nano-filled pheno resin, siloxane, a fluorinated polymer, polynorbornene, or the like, using any suitable method, including, for example, a spin-on coating technique, sputtering, and the like.

In some embodiments, the conductive features are formed in polymer layers. The formation of such conductive features includes patterning polymer layers, for example, using a combination of photolithography and etching processes, and forming the conductive features in the patterned polymer layers, for example, depositing a seed layer (i.e., TiCu) and then plating a conductive metal layer (i.e., Cu) and using a mask layer to define the shape of the conductive features. For illustration, some conductive features are designed to form the conductive plane122of the semiconductor structure100, and some other conductive features are designed to form functional circuits and input/output features for subsequently attached dies.

Next, in operation S330, a patterned photoresist601is formed over the InFO backside RDL204and the carrier201, as illustrated inFIG. 6. In some embodiments, for example, photoresist601is deposited as a blanket layer over the backside RDL204. Next, portions of photoresist601are exposed using a photo mask (not shown). Exposed or unexposed portions of photoresist601are then removed depending on whether a negative or positive resist is used. The resulting patterned photoresist601includes openings602disposed at peripheral areas of the carrier201. In some embodiments, the openings602further expose conductive features in the backside RDL204.

Next, in operation S340, the seed layer205is deposited overlying the patterned photoresist601, as illustrated inFIG. 7.

Next, in operation S350, the openings602are filled with the conductive material206including, for example, copper, titanium, nickel, tantalum, palladium, silver or gold and the like to form conductive vias, as illustrated inFIG. 8. In some embodiments, the openings602are plated with the conductive material206during a plating process, including, for example, electro-chemically plating, electroless plating, or the like. In some embodiments, the conductive material206overfills the openings602, and a chemical mechanical polishing (CMP) process is performed to remove excess portions of the conductive material206over the photoresist601, as illustrated inFIG. 9.

Next, in operation S360, the photoresist601is removed, as illustrated inFIG. 10. In some embodiments, a wet strip process is used to remove the photoresist601. In some embodiments, the wet strip solution contains Dimethyl sulfoxide (DMSO) and Tetramethyl ammonium hydroxide (TMAH) to remove the photoresist material.

Thus, the vertical conductive structures124, and the vertical conductive structures144are formed over the InFO backside RDL204and the polymer base layer203respectively. For illustration, in some embodiments, the conductive through molding vias207are formed over the backside RDL204. In some embodiments, the conductive through molding vias207have a square shape, a rectangular shape, a circular shape, an oval shape, any other suitable shape in a cross section, or any combinations thereof. Alternatively, in some embodiments, the conductive through molding vias207are replaced with conductive studs or conductive wires, including, for example, copper, titanium, nickel, tantalum, palladium, silver or gold wire. In some embodiments, the conductive through molding vias207are spaced apart from each other and from the vertical conductive structures124and the vertical conductive structures144by the openings1001. For illustration, at least one opening1001between the conductive through molding vias207and the semiconductor structure100is large enough to dispose one or more semiconductor dies therein.

Next, in operation S370, one or more device dies208are mounted and attached to the package200, as illustrated inFIG. 11. For illustration, the device package200includes the carrier201, and the backside RDL204having conductive features as shown. In some embodiments, other interconnect structures including, for example, the conductive through molding vias207electrically coupled to the conductive features in the backside RDL204is also included. In some embodiments, an adhesive layer is used to affix the device die208to the backside RDL204.

Next, in operation S380, the molding compound MC is formed within the molding layer209in the package200after the device die208is mounted to the backside RDL204in the opening1001, as illustrated inFIG. 12. The molding compound MC is dispensed to fill gaps between the device die208and the conductive through molding vias207, and gaps between the vertical conductive structures124and the vertical conductive structures144. In some embodiments, the molding compound MC is filled in the gaps between the vertical conductive structures124and the vertical conductive structures144to form an insulating structure.

In some embodiments, the molding compound MC includes material with relatively high dielectric constant, including, for example, high-K polymer or silica. In some embodiments, compressive molding, transfer molding, and liquid encapsulent molding are suitable methods for forming molding compound MC, but the present disclosure is not limited thereto. For example, molding compound MC is dispensed in liquid form. Subsequently, a curing process is performed to solidify molding compound MC. In some embodiments, the filling of molding compound MC overflows the conductive through molding vias207, the device die208, and the vertical conductive structures124and144, so that the molding compound MC covers top surfaces of the device die208and conductive through molding vias207.

Next, in operation S390, a grinding process is performed. Next, in operation S399, a chemical mechanical polishing (CMP) process is performed. In operation S390and S399, excess portions of the molding compound MC are removed, and the molding compound MC is ground back to reduce its overall thickness and thus expose the conductive through molding vias207and the vertical conductive structures124and144, as illustrated inFIG. 13.

Because the resulting structure includes conductive through molding vias207that extend through molding compound MC, the conductive through molding vias207and the vertical conductive structures124and144are also referred to as through molding vias (TMVs), through inter vias (TIVs), and the like. For illustration, the conductive through molding vias207provide electrical connections to the backside RDL204in the package200. In some embodiments, the thinning process used to expose the conductive through molding vias207is further used to expose conductive pillar2081of the device die208.

Next, in operation S400, the conductive layer210is formed overlying the molding layer and the molding compound MC, as illustrated inFIG. 14. For example, in some embodiments the conductive material forming the conductive layer210includes copper, silver, gold, or the like.

Next, in operation S410, a patterned photoresist1501is formed over the conductive layer210, as illustrated inFIG. 15. Portions of photoresist1501are exposed using a photo mask (not shown). Exposed or unexposed portions of photoresist1501are then removed depending on whether a negative or positive resist is used. Portions of photoresist1501are removed to form openings exposed at the area of the conductive layer210overlying the vertical conductive structures124, and the resulting patterned photoresist1501disposed at the area of the conductive layer210overlying the vertical conductive structures144.

Next, in operation S420, an etching process is performed to remove the exposed portions of the conductive layer210, as illustrated inFIG. 16. In some embodiments, the etching process includes a plasma etching, but the present disclosure is not limited thereto.

Next, in operation S430, photoresist1501is removed, as illustrated inFIG. 16. In some embodiments, a plasma ashing or wet strip process is used to remove photoresist1501. In some embodiments, the plasma ashing process is followed by a wet dip in a sulfuric acid (H2SO4) solution to clean package200and remove remaining photoresist material.

Thus, the conductive plane142is formed within the conductive layer210and electrically coupled to the vertical conductive structures144. When the operation S430is completed, the semiconductor structure100including the electrode120and the electrode140is formed in the package200. As illustratively shown inFIG. 16, the electrode120includes the conductive plane122and the vertical conductive structures124, and the electrode140includes the conductive plane142and the vertical conductive structures144. The vertical conductive structures124and the vertical conductive structures144are interlaced with each other, and the molding compound MC is filled, as the dielectric material160, between the electrode120and the electrode140.

Next, in operation S440, the patterned polymer layer211having openings is formed overlying the molding compound MC and the conductive layer210, as illustrated inFIG. 17. In some embodiments, the polymer layer211includes PI, PBO, BCB, epoxy, silicone, acrylates, nano-filled pheno resin, siloxane, a fluorinated polymer, polynorbornene, or the like. In some embodiments, the polymer layer211is selectively exposed to a plasma etchant, including, for example, CF4, CHF3, C4F8, HF, etc., configured to etch the polymer layer211to form the openings.

In some embodiments, the openings are filled with a conductive material. For illustration, a seed layer (not shown) is formed in the openings and the conductive material is plated in the openings using, for example, an electrochemical plating process, electroless plating process, or the like. The resulting via holes in the polymer layer211are electrically coupled to the conductive pillar2081, the conductive layer210, or the conductive through molding vias207, as illustratively shown.

In some embodiments, one or more additional polymer layers having conductive features are formed over the polymer layer211. In operation S450, the RDL212having conductive features is formed, as illustrated inFIG. 17. As illustratively shown, in some embodiments, the conductive features are electrically coupled to the conductive layer210through the via holes in the polymer layer211.

Next, in operation S460, the patterned polymer layer213having openings is formed overlying the patterned polymer layer211and the RDL212, as illustrated inFIG. 18. In some embodiments, the polymer layer213includes PI, PBO, BCB, epoxy, silicone, acrylates, nano-filled pheno resin, siloxane, a fluorinated polymer, polynorbornene, or the like. In some embodiments, the polymer layer213is selectively exposed to a plasma etchant, including, for example, CF4, CHF3, C4F8, HF, etc., configured to etch the polymer layer213to form the openings.

Next, in operation S470, the RDL214having at least one conductive feature is formed, as illustrated inFIG. 18. As illustratively shown, in some embodiments, the conductive features are electrically coupled to the conductive features in the RDL212through the via holes in the polymer layer213. The conductive feature is electrically coupled to the device die208through the conductive vias and the conductive pillar2081, and electrically coupled to the electrode140through the conductive vias and the conductive layer210. In some embodiments, the RDLs212and214are substantially similar to the backside RDL204both in composition and formation process, and thus detailed description is omitted for brevity. In some embodiments, the patterned polymer layer215is formed overlying the patterned polymer layer213and the RDL214, as illustrated inFIG. 18.

Next, in operation S480, external connectors217, which are configured to be the input/output (I/O) pads, including, for example, solder balls on Under Bump Metallurgies (UBMs)216are then formed to electrically connect to the device die208through the RDL214, as illustrated inFIG. 19. In some embodiments, the connectors217are ball grid array (BGA) balls, controlled collapse chip connector (C4) bumps, and the like disposed upon UBMs216, which are formed over the RDL214. In some embodiments, the connectors217are used to electrically connect the InFO package200to other package components including, for example, another device die, interposers, package substrates, printed circuit boards, a mother board, and the like.

Next, the carrier201and adhesive layer202are removed from the InFO package. The resulting structure is shown inFIG. 2. In some embodiments, the polymer base layer203is also removed from the InFO package. In some alternative embodiments, the polymer base layer203is not removed, and is left in the resulting package as a bottom protective layer.

The above illustrations include exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure.

Reference is made toFIG. 20.FIG. 20is a schematic diagram illustrating another integrated Fan-Out (InFO) package200including the semiconductor structure100inFIG. 1in accordance with some other embodiments of the present disclosure. With respect to the embodiments ofFIG. 2, like elements inFIG. 20are designated with the same reference numbers for ease of understanding.

Compared with the embodiments shown inFIG. 2, in the embodiments illustratively shown inFIG. 20, the dielectric material160and the molding compound MC are different materials. The dielectric material160is filled between the vertical conductive structures124and the vertical conductive structures144in the semiconductor structure100to form an insulating structure. For example, in some embodiments, the dielectric constant (or permittivity) value of the dielectric material160is greater than that of the molding compound MC. In some embodiments, the molding compound MC is applied in the molding layer outside the semiconductor structure100to surround the device die208, and the molding compound MC has a low-k value, e.g., less than about 3.9, and even less than about 2.5 in other embodiments. In some embodiments, the molding compound MC includes any suitable material including, for example, an epoxy resin, a molding underfill, or the like.

FIG. 21is a flowchart illustrating a method2100of forming the Integrated Fan-Out (InFO) package200as illustrated inFIG. 20, in accordance with some embodiments of the present disclosure. For better understanding of the present disclosure, the method2100is discussed in relation to the semiconductor structure100shown inFIG. 1andFIG. 20, but is not limited thereto.

For illustration, the manufacturing process of the Integrated Fan-Out (InFO) package200illustrated inFIG. 20is described by the method2100withFIGS. 22-26FIGS. 22-26are cross sectional views of the Integrated Fan-Out (InFO) package200at different stages of the manufacturing process, in accordance with some embodiments of the present disclosure. After the different stages inFIGS. 4-19andFIGS. 22-26, the package200has the cross sectional view inFIG. 20. AlthoughFIGS. 22-26are described together with the method2100, it will be appreciated that the structures disclosed inFIGS. 22-26are not limited to the method2100. With respect to the embodiments ofFIGS. 4-19, Like elements inFIGS. 22-26are designated with the same reference numbers for ease of understanding.

Compared to the method300illustrated in theFIG. 3, in the method2100illustrated inFIG. 21, the molding compound MC includes material with relatively low dielectric constant, including, for example, an epoxy resin, a molding underfill, or the like.

After the grinding process in operation S390is performed, as illustrated inFIG. 22, operation S391is performed. In operation S391, a patterned photoresist2201is formed over the molding compound MC, as illustrated inFIG. 22. Portions of photoresist2201are exposed using a photo mask (not shown). Exposed or unexposed portions of photoresist2201are then removed depending on whether a negative or positive resist is used. Portions of photoresist2201are removed to form openings exposed at the area of the molding compound MC between the vertical conductive structures124and the vertical conductive structures144, and the resulting patterned photoresist2201disposed at the area of the molding compound MC surrounding the device die208.

Next, in operation S393, an etching process is performed to remove the exposed portions of the molding compound MC between the vertical conductive structures124and the vertical conductive structures144, as illustrated inFIG. 23. In some embodiments, a wet etching using HF and AMAR (Cu+NH3compound) is applied. In some other embodiments, a wet etching using HF and LDPP, which contains TMAH, is applied.

Next, in operation S395, the photoresist2201is removed, as illustrated inFIG. 24. In some embodiments, a wet strip process is used to remove the photoresist2201. In some embodiments, during the wet strip process, Dimethylsufoxide (DMSO) and Tetramethyl ammonium hydroxide (TMAH) are used to remove the photoresist material. For example, the photoresist2201is removed using Dimethylsufoxide (DMSO) to dissolve photoresist2201and make photoresist2201swollen, and Tetramethyl ammonium hydroxide (TMAH) is used to cut the polymer cross-linkage.

Next, in operation S397, the dielectric material160is formed between the vertical conductive structures124and the vertical conductive structures144and overlying the molding layer209, as illustrated inFIG. 25. In some embodiments, the dielectric constant of the dielectric material160is higher than which of the molding compound MC.

Next, the chemical mechanical polishing (CMP) process in operation S399is performed to remove excess portions of the dielectric material160and to expose out conductive features such as conductive material206, conductive vias207, and the conductive pillar2081, as illustrated inFIG. 26. Thus, the dielectric material160different from the molding compound MC is filled between the vertical conductive structures124and the vertical conductive structures144.

In some embodiments, the method2100includes operations S310-S390performed before operation S391, and operations S400-S480performed after operation S399. Operations S310-S390and S400-S480in the method2100are similar to of which in the method300, and are fully described in the aforementioned paragraphs andFIGS. 4-19. Thus, detailed description is omitted for brevity.

The above illustrations include exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure.

Reference is made toFIG. 27.FIG. 27is a schematic diagram illustrating another Integrated Fan-Out (InFO) package200including the semiconductor structure100inFIG. 1in accordance with various embodiments of the present disclosure. With respect to the embodiments ofFIG. 2, like elements inFIG. 27are designated with the same reference numbers for ease of understanding.

Compared with the embodiments shown inFIG. 2, in the embodiments illustratively shown inFIG. 27, the device die208includes two conductive pillars2081and2082, and the conductive through molding via207is arranged at another side of the device die208. For illustration, in some embodiments, the conductive through molding via207is electrically coupled to the external connector217a, through the RDLs212and214, to connect to the ground, and electrically coupled to the vertical conductive structures124via the backside redistribution layer204. Thus, the bottom electrode of the MIM structure is coupled to the ground. The conductive pillar2081is electrically coupled through RDLs212and214into the positive voltage side of the Finger MIM. In addition, the vertical conductive structures144are electrically coupled to each other via the RDL212. Thus, the upper electrode of the MIM structure is coupled to the device die208via the RDL214and the conductive pillar2081. The conductive pillar2082is electrically coupled to the external connector217b, through the RDLs212and214, to receive the input signal for the device die208via the external connector217b. Similar to the embodiment shown inFIG. 2, the high-k molding compound MC is filled in the molding layer209and filled between the vertical conductive structures124and the vertical conductive structures144in the semiconductor structure100to form a finger-typed MIM capacitor structure for suppressing the signal noise sent from the die208through conductive pillar2081and RDLs214,212and210. In some embodiments, the vertical conductive structures124and144have a square shape, a rectangular shape, any other suitable shape in a cross section, or any combinations thereof.

The manufacturing process of the Integrated Fan-Out (InFO) package200illustrated inFIG. 27is similar to the manufacturing process of the Integrated Fan-Out (InFO) package200illustrated inFIG. 2, which is fully described in the above paragraphs and thus is omitted for the sake of the brevity.

Reference is made toFIG. 28.FIG. 28is a schematic diagram illustrating another Integrated Fan-Out (InFO) package200including the semiconductor structure100inFIG. 1in accordance with alternative embodiments of the present disclosure. With respect to the embodiments ofFIG. 20, like elements inFIG. 28are designated with the same reference numbers for ease of understanding.

Compared with the embodiments shown inFIG. 27, in the embodiments illustratively shown inFIG. 28, the dielectric material160and the molding compound MC are different materials. The dielectric material160is filled between the vertical conductive structures124and the vertical conductive structures144in the semiconductor structure100to form an insulating structure. For example, in some embodiments, the dielectric constant (or permittivity) value of the dielectric material160is greater than that of the molding compound MC. In some embodiments, the molding compound MC is applied in the molding layer outside the semiconductor structure100to surround the device die208, and the molding compound MC has a low-k value, e.g., less than about 3.9, and even less than about 2.5 in other embodiments. In some embodiments, the molding compound MC includes any suitable material including, for example, an epoxy resin, a molding underfill, or the like. Similarly, the manufacturing process of the Integrated Fan-Out (InFO) package200illustrated inFIG. 28is similar to the manufacturing process of the Integrated Fan-Out (InFO) package200illustrated inFIG. 20, which is fully described in the above paragraphs and thus is omitted for the sake of the brevity.

In some embodiments, a semiconductor device is disclosed that the semiconductor device includes a device die, a molding layer surrounding the device die, a plurality of first vertical conductive structures formed within the molding layer, and a plurality of second vertical conductive structures formed within the molding layer. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and an insulating structure is formed between the first vertical conductive structures and the second vertical conductive structures.

Also disclosed is a method that includes forming a first conductive plane on a substrate; forming a plurality of first vertical conductive structures on the first conductive plane and electrically coupled to the first conductive plane; forming a plurality of second vertical conductive structures on the substrate, in which the first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and an insulating structure is formed between the first vertical conductive structures and the second vertical conductive structures; attaching a device die on the substrate; applying a molding compound in a molding layer overlying the substrate to surround the device die; and forming a second conductive plane on the molding layer, in which the second conductive plane is electrically coupled to the second vertical conductive structures.

Also disclosed is a method that includes forming a capacitor structure on a substrate, in which the capacitor structure includes a plurality of first vertical conductive structures, a plurality of second vertical conductive structures and an insulating structure between the first vertical conductive structures and the second vertical conductive structures; attaching a device die on the substrate; and applying a molding compound in a molding layer overlying the substrate to surround the device die and the capacitor structure.