Wafer-level chip-scale package with redistribution layer

A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further includes a passivation layer formed over the semiconductor structure and the first bonding pad, exposing portions of the first bonding pad. The WLCSP further includes a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further includes a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further includes an under-bump-metallurgy (UBM) layer formed over the planarization layer and a conductive bump formed over the UBM layer.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to integrated circuits (ICs), and in particular to a wafer-level chip scale package (WLCSP) with a redistribution layer and a method of manufacturing the same.

Description of the Related Art

The desire to make electronic products small, lightweight, and high-performing has developed into a desire to make electronic parts small, lightweight, and high-performing. This desire has caused developments to proceed in various packaging technologies, along with developments in the technologies related to designing and manufacturing semiconductors. Representative examples of packaging technologies include the ball grid array (BGA), the flip-chip, and the chip scale package (CSP) based on area array and surface-mount packaging.

Among the above, the CSP is a packaging technology that enables a small package to be the same size as the real chip to be developed. In particular, in a Wafer-level chip scale package (WLCSP), the packaging is performed in a wafer level so that the packaging costs per chip can be remarkably reduced. Typically, the WLCSP includes a redistribution layer (RDL) wiring traces, an under bump metallurgy (UBM) layer forming a bump, and a passivation layer protecting a circuit.

BRIEF SUMMARY OF THE INVENTION

An exemplary Wafer-level chip scale package (WLCSP) comprises a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further comprises a passivation layer formed over the semiconductor structure and the first bonding pad, wherein the passivation layer exposes a plurality of portions of the first bonding pad. The WLCSP further comprises a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further comprises a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further comprises an under-bump-metallurgy (UBM) layer formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. The WLCSP further comprises a conductive bump formed over the UBM layer.

An exemplary method for forming a Wafer-level chip scale package (WLCSP) comprises providing a semiconductor structure having a first bonding pad formed over the semiconductor structure and forming a passivation layer over the semiconductor structure and the first bonding pad, wherein the passivation layer exposes a plurality of portions of the first bonding pad. The method further comprises forming a conductive redistribution layer over the passivation layer and the portions of the first bonding pad exposed by the passivation layer, and forming a planarization layer over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The method further comprises forming an under-bump-metallurgy (UBM) layer over the portion of the portion of the conductive redistribution layer exposed by the planarization layer, and forming a conductive bump formed over the UBM layer.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a schematic cross section showing a Wafer-level chip scale package (WLCSP) according to an embodiment of the present disclosure.

As shown inFIG. 1, the WLCSP comprises a semiconductor structure100, a bonding pad102, a passivation layer104, a first planarization layer106, a second planarization layer112, a conductive redistribution layer110, an under-bump-metallurgy (UBM) layer116, and a conductive bump118.

Herein, the semiconductor structure100is illustrated as a structure having a flat top surface for the purpose of simplifying the figure. It should be noted that the semiconductor structure100can be a wafer-level semiconductor substrate having a plurality of semiconductor devices and interconnect structures (both not shown) formed thereon. The semiconductor devices formed over the semiconductor structure100can be, for example, active devices such as transistors or diodes and/or passive devices such as capacitors, resistors and conductors. The interconnect structures in the semiconductor structure100may comprise a multi-layer metallization structure isolated and supported by a plurality of interlayer dielectric layers. In this embodiment, only a portion of the semiconductor structure100is illustrated as the WLCSP.

Referring toFIG. 1, the bonding pad102is formed over a portion of the semiconductor structure100and may be electrically connected with one of the interconnect structure (not shown) of a circuit formed in the semiconductor structure100. The passivation layer104and the first planarization layer106are sequentially formed over the semiconductor structure100, and the passivation layer104and the first planarization layer106partially respectively cover portions of the bonding pad102. An opening108is formed in the first planarization layer106to expose a portion of the bonding pad102, and the conductive redistribution layer110is conformably formed over portions of the first planarization layer106and in the opening to cover the portion of the bonding pad102exposed by the opening108. The second planarization layer112is formed over the first planarization layer106and the conductive redistribution layer110, and an opening116is formed in the second planarization layer112to expose a portion of the conductive redistribution layer110. The UBM layer116is formed over a portion of the second planarization layer112and the portion of the conductive redistribution layer110exposed by the second planarization layer112, and the conductive bump118is formed over the UBM layer116.

In this embodiment, the bonding pad102may comprise conductive materials such as aluminum, and the passivation layer104may comprise dielectric materials such as silicon oxide, silicon nitride, or combination thereof. The first planarization layer106and the second planarization layer108may comprise dielectric materials such as silicon nitride, silicon oxide, or polymer. In one embodiment, the polymer suitable for the first planarization layer106and the second planarization layer108can be, for example, polyimide, polybenzoxazole, or benzocyclobutene. The conductive redistribution layer110may comprise conductive materials such as copper, nickel, or aluminum. The UBM layer116may comprise conductive materials such as metals or metal alloys such as Ni layers, Ag layers, Al layers, Cu layers or alloys thereof, or materials of doped polysilicon, monocrystalline silicon or conductive glasses. Additionally, refractory metal materials such as titanium, molybdenum, chromium or titanium tungsten layers can be used to individually form the UBM layers or be combined with other metal layers. Typically, the first passivation layer106is provided with a thickness C of about 51 μm to about 7.5 μm a step-height of the first planarization layer over the bonding pad102is too large, such that opening108formed in the first planarization layer106is a single opening of a greater dimension of, for example, about 22 μm to about 30 μm. Therefore, the conductive redistribution layer110is conformably formed over portions of the first planarization layer106and the portion of the bonding pad102exposed by the opening108and has a step portion A of a step-like configuration near the opening108and a flat portion B of a flat configuration extending from the opening114and over the first planarization layer106. In addition, the opening114formed in the second planarization layer112exposes a portion of the planar portion B of the conductive redistribution layer110, such that the UBM layer116can be conformably disposed over portions of the second planarization layer112and the planar portion B of the conductive redistribution layer110exposed by the opening114.

In the WLCSP shown inFIG. 1, since the first planarization layer106is provided, and it has a thickness C of about 5 μm to about 7.5 μm, the step-height of the first planarization layer106near the opening108is too large to make the opening108smaller. Thus, the portion of the conductive redistribution layer110near the opening108is formed with a step-like configuration, and the UBM layer116and the solder bump118formed over the UBM layer only can be formed over the planar portion B of the conductive redistribution layer110extending from the opening108and over the first passivation layer106. Therefore, the footprint of the WLCSP shown inFIG. 1is quite large, which is undesirable because of the trend towards further reduction in the size of the integrated circuits in the WLCSP.

Therefore,FIGS. 2-8are schematic cross sections showing a method for forming a Wafer-level chip scale package (WLCSP) having a structure with a reduced size, according to another embodiment of the present disclosure.

Referring toFIG. 2, a semiconductor structure200having a bonding pad202formed over a portion of the semiconductor structure200is provided. Next, a passivation layer204is conformably formed over the semiconductor structure200and the first bonding pad204by, for example, a chemical vapor deposition (CVD) process (not shown). Since the passivation layer204is conformably formed over the semiconductor structure200and the first bonding pad202, the passivation layer204has a non-flat top surface over the semiconductor structure200. In one embodiment, the portion of the passivation layer204formed over the semiconductor structure200has a thickness T of about 1 μm to about 6 μm.

In one embodiment, the semiconductor structure200is the same as the semiconductor structure100shown inFIG. 1, and the passivation layer204and the bonding pad202are respectively the same as those used for forming the passivation layer104and the bonding pad102shown inFIG. 1.

Referring toFIG. 3, a planarization process206is performed to level a top surface of the passivation layer204and reduce the thickness of the passivation layer204, thereby leaving a passivation layer204ahaving a flat top surface over both the semiconductor structure200and the bonding pad202. At this time, the passivation layer204ahas a reduced thickness T′ of about 1 μm to about 6 μm above the semiconductor structure200. The planarization process206can be a chemical mechanical polishing (CMP) process, for example, or an etching back process.

Referring toFIG. 4, a patterning process208is next performed on the passivation layer204ashown inFIG. 3to form a plurality of openings210only in portions of the passivation layer204aover the bonding pad202. Therefore, a plurality of portions of the bonding pad202is exposed by the openings210. Each of the openings210has a dimension W, for example a width, of about 2 μm or above, and the openings210may have a circular, stripe-like, or polygonal shape from a top view (not shown). In one embodiment, the patterning process208may comprise photolithography and etching steps (not shown) with suitable patterned masks (not shown) used as an etching mask.

Referring toFIG. 5, a patterned conductive redistribution layer212is next formed over portions of the passivation layer204aover the bonding pad202. As shown inFIG. 5, the patterned conductive redistribution layer212comprises a plurality of first portions212afilling the openings210formed in the passivation layer204a, and a second portion212bformed above the flat top surface of the passivation layer204aand the openings210. Therefore, the patterned conductive redistribution layer212is also provided with a substantially flat top surface, as shown inFIG. 5. The patterned conductive redistribution layer212can be formed by first forming a conductive redistribution layer212over the passivation layer204aand in the openings210, and then the conductive redistribution layer212is patterned by a patterning process (not shown) comprising photolithography and etching steps (not shown) incorporating suitable patterned masks (not shown) as an etching mask. Conductive materials for forming the patterned conductive redistribution layer212can be the same as those of the conductive redistribution layer110shown inFIG. 1, with a thickness of about 4 μm to about 9 μm above the passivation layer204a.

Referring toFIG. 6, a planarization layer214is formed over the top surface of the structure shown inFIG. 5, and an opening216is then formed in a portion of the planarization layer214to expose a portion of the patterned conductive redistribution layer212. The planarization layer214can be formed by a chemical vapor deposition (CVD) or spin coating process, for example, and may be patterned by a patterning process (not shown) comprising photolithography and etching steps (not shown) incorporating suitable patterned masks (not shown) as an etching mask. Materials for forming the planarization layer214can be the same as those of the first planarization layer112shown inFIG. 1, and the planarization layer214may have a thickness of about 7.5 μm to about 10 μm which is greater than the thickness of the patterned conductive redistribution layer212.

Referring toFIG. 7, an under-bump-metallurgy (UBM) layer218is next formed over the portion of the patterned conductive redistribution layer212exposed by the opening216and portions of the planarization layer214adjacent to the opening216. The UBM layer218can be formed by forming a layer of conductive material over the structure shown inFIG. 6by, for example, a chemical vapor deposition (CVD) or electrical plating process, and is then patterned by a patterning process (not shown) comprising photolithography and etching steps (not shown) incorporating suitable patterned masks (not shown) as an etching mask. Materials for forming the UBM layer218can be the same as that of the UBM layer116shown inFIG. 1, and the UBM layer218may have a thickness of about 4 μm to about 9 μm.

Referring toFIG. 8, a conductive bump220is next formed over the UBM layer218by conventional solder bump formation processes. Since the patterned conductive redistribution layer212is now provided with a substantially flat top surface rather than a step-like configuration, the UBM layer218and the conductive bump220can be sequentially and firmly formed over the patterned conductive redistribution layer212. In addition, since the patterned conductive redistribution layer212is formed directly over the bonding pad202, the conductive bump220and the UBM layer218are also formed directly over the bond pad202, so that a bonding structure for the WLCSP with a reduced size can be obtained.

In addition, since there is only one planarization layer214utilized in the WLCSP shown inFIG. 8, the WLCSP inFIG. 8can be fabricated more easily than the WLCSP shown inFIG. 1, which utilizes two planarization layers.

In addition to the exemplary embodiment shown inFIG. 8,FIG. 9is a schematic cross section showing another exemplary Wafer-level chip scale package (WLCSP) of the present disclosure. At this time, the WLCSP shown inFIG. 9is modified from the WLCSP shown inFIG. 8, and similar components inFIG. 9are represented with the same reference numbers shown inFIG. 8, and only differences between the WLCSPs shown inFIGS. 8-9are discussed as below.

Referring toFIG. 9, the second portion212bof the patterned conductive redistribution layer212having a flat top surface is not only formed over the bonding pad202as shown inFIG. 8, but it further extends over a portion of the passivation layer204anot covering the bonding pad202to thereby provide a line-routing function, so that the UBM layer218and the conductive bump220can thus be formed over a portion of the second portion212bof the patterned conductive redistribution layer212at a place that is not covering the bonding pad202. Similarly, since there is only one planarization layer214utilized in the WLCSP shown inFIG. 9, the WLCSP inFIG. 9can also be fabricated more easily than the WLCSP shown inFIG. 1, which utilizes two planarization layers.

In addition to the exemplary embodiment shown inFIG. 9,FIG. 10is a schematic cross section showing another exemplary Wafer-level chip scale package (WLCSP) of the present disclosure. At this time, the WLCSP shown inFIG. 10is modified from the WLCSP shown inFIG. 9, and similar components shown inFIG. 10are represented with the same reference numbers, and only differences between the WLCSPs shown inFIGS. 9-10are discussed as below.

Referring toFIG. 10, the semiconductor structure200is now provided with two isolated bonding pads202formed thereover, and configurations of the passivation layer204aand the openings210formed in the passivation layer204aare the same at a place over each of the bonding pads202. In this embodiment, the patterned conductive redistribution layer212has a first portion212aformed in the openings210which are formed over each of the passivation layers204aover the bonding pads202and a second portion212bover the leveled passivation layer204abetween the bonding pads202. The UBM layer218and the conductive bump220are formed over a portion of the second portion212bof the conductive redistribution layer212over one of the bonding pads202.

Similarly, the patterned conductive redistribution layer212is now provided with a substantially flat top surface, so the UBM layer218and the conductive bump220can thus be formed firmly over the patterned conductive redistribution layer212. In addition, since the patterned conductive redistribution layer212is formed directly over the bonding pad202, the conductive bump220and the UBM layer218are also formed directly over one of the bond pads202, so that a bonding structure for the WLCSP with a reduced size can be obtained.

Moreover, since there is only one planarization layer214utilized in the WLCSP shown inFIG. 10, the WLCSP inFIG. 9can be fabricated more easily than the WLCSP shown inFIG. 1, which utilizes two planarization layers.