Copy protection for analog video signals from computing devices

A copy protection method and apparatus is provided to inhibit unauthorized viewing or copying of a video signal. A varying set of additional or invalid video pulses are generated onto a typical video signal. A pulse sequence identifier identifies the location of the invalid or additional pulses and is likewise generated onto the video signal prior to the occurrence of the identified pulses. The combined signal is received at an authorized display which then decodes or filters the additional or invalid portion of the video signal from the original signal according to a decode protocol stored in local memory. A resultant video output signal is guaranteed from only the original signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

Not applicable.

STATEMENTS REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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REFERENCE TO A MICROFICHE APPENDIX

Not applicable.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to copy-protected video playback systems and more particularly to protection against unauthorized copying of video signals from computing devices.

2. Description of the Related Art

The Digital Video Disk (DVD) format gives consumers the ability to view exceptional quality video. In many instances, DVD players have replaced VHS players for home movie viewing. In addition, the DVD player functionality is now a feature of many of the personal computers (PCs) that are sold on the consumer market. This is a valuable feature that allows consumers to watch DVD movies on the PC.

Concurrently, video converters have also become available to allow consumers to use the standard TV as a monitor for PC. A combination of the PC DVD player along with video converter allows consumers to play video games and watch DVD movies using a large screen display. However, the DVD format also allows individuals to make near commercial-quality VHS recordings from any unprotected DVD program. The consumer is able to connect the output signal of the converter to the input of a VCR where the DVD signal may be recorded. Since the movie is stored digitally on a DVD disk, a high quality copy can be made of the movie.

As DVDs increase in resolution, movie studios have become increasingly concerned about consumers' ability to make high quality copy of movies. If widespread copying of DVD movies resulted, movie studios would be forced to stop releasing movies on DVD or delay the release of quality movies on DVD.

A number of techniques have been developed to address DVD copy protection. A watermarking process has been contemplated which permanently marks each digital video frame with background noise. Watermark signatures can be recognized by video playback and recording equipment to prevent copying. However placing a watermark signature directly on the video frame presents obvious video quality clarity issues. In addition, a watermarking process contemplates new players or other equipment to support watermarking. These issues, along with the difficult task of obtaining a common compatible standard agreeable among the principal commercial entities, pose significant hurdles to a watermarking solution.

Other non-destructive solutions, from the video signal standpoint, have been proposed. Digital Copy Protection Systems (DCPS) have been developed whereby the DVD player and a digital TV or a digital VCR exchange keys and identification certificates to establish secure channels. In addition, Content Scrambling Systems (CSS) have been proposed as a form of data encryption to discourage reading media files directly from the desk. Here again, encryption keys are exchanged so the video is decrypted before being displayed by the display device. Like the proposed watermarking solution, both of these other proposals require significant additional hardware (and cost) for movie copy protection. In addition, the CSS proposal contemplates a preliminary licensing requirement before any hardware may be implemented.

One approach to copy protection of video signals by Macrovision Corporation of Cupertino, Calif. involves inserting pseudo-synchronization pulses during the vertical blanking interval of video signals and varying the output levels. This confuses the fast phase locked loops (PLLs) and auto-gain controls (AGCs) used on recording devices but does not significantly affect the slower PLLs and AGCs used on televisions.

BRIEF SUMMARY OF THE INVENTION

In a video system, processing of video signals is provided by a copy protection system to inhibit unauthorized viewing and copying of the video signal, such as from the PC DVD player. During a vertical blanking interval (VBI) portion of the video signal, a number of additional horizontal synchronization (H-sync) pulses are generated onto the video signal by a video graphics adapter (VGA). The resultant video signal comprises a set of original H-sync pulses that are output normally from the VGA and the additional H-sync pulses generated by the copy protection system's encoder. The encoder also generates an H-sync pulse identifier onto the video signal after the first H-sync pulse occurrence. The copy protection system's decoder uses a decoding table, provided in a memory of a decoder, and the H-sync pulse identifier to determine which of the following H-sync pulses are valid and which ones are added. Only the valid pulses are used to generate sync pulses for the display monitor.

Increased security is provided as the sequence of valid pulses is constantly changing through generation of successive sequences of additional synchronization pulses different from the preceding sequences. For each successive sequence of additional synchronization pulses, an associated sync pulse identifier is generated. The decoding table includes all of the potential synchronization pulse identifiers along with a matched identifier location to inform the decoder where to look for the next successive synchronization pulse identifier. After a specified number of identifiers have been generated, the process is reset and repeated.

Flexibility is provided through polling of both the encoder (the video source) and the decoder (receiving or display device) to determine if they are authorized devices. If the decoder is not an authorized device the encoder will not output the protected video signal. The copy protection system is enabled only if the video material indicates it should be protected, using existing techniques (such as CGMS).

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

The illustrative system described in this patent application provides a technique for protecting video signals against unauthorized copying. For purposes of explanation, specific embodiments are set forth to provide a thorough understanding of the illustrative system. However, it will be understood by one skilled in the art, from reading the disclosure, that the technique may be practiced without these details. Further, although the embodiments are described in terms of a DVD player, it should be understood that this embodiment is illustrative and is not meant in any way to limit the practice of the disclosed system to DVD systems. Also, the use of the term monitor and player to illustrate how the system works is not intended to infer that the illustrative system requires a specific type of display device or video signal generator. Rather, any of a variety of display devices or video signal sources may be employed in practicing the technique described herein. Moreover, well-known elements, devices, process steps, and the like are not set forth in detail in order to avoid obscuring the disclosed system.

As used herein, the term “video signal” includes both RGB and synchronization signals unless otherwise noted. Further, reference to “synchronization signals” refers to both horizontal synchronization (H-sync) and vertical synchronization (V-sync) signals unless otherwise noted. Additionally, reference to RGB signals refers to video signals typically used for red, green, and blue, but should be understood to mean equivalent signals in alternate color spaces.

Furthermore, the description of the various RGB signals and synchronization signals is not intended to imply that separate wiring connections are required for each signal. All of the RGB and synchronization signals may be transmitted across a signal cable typically known as a “composite video” cable or across component video cables, such as S-video or separate R, G, B, H-sync, and V-sync cables, as desired.

Turning toFIG. 1, shown is an exemplary video viewing system100employing a copy protection system according to an embodiment of the present invention. A computer system102or other computing device provides as its output video content for which certain anti-copy protection is desired. For example, a DVD drive (not shown) embedded into the computer system102provides a video signal output that may be copy protected according to an embodiment of the disclosed subject matter. If the computer system102did not have the copy protection system and displayed a DVD movie, the output of the computer system102could be copied by the VCR108, resulting in a high-quality copy.FIG. 1depicts a computer system102with the copy protection system and a display device112with the copy protection system. In this case, the VCR108will be unable to record the DVD movie when the copy protection system is engaged. Of course, it should be noted that the video output is not limited to a signal originated from a DVD drive, but instead can be generated through any number of video sources, such as subscription service of a video download from the Internet or a video transmission satellite, such as a high definition satellite.

The computer system102outputs a video signal representing an image being rendered on the computer system102to a graphics controller104, typically associated with a video graphics card in the computer system102. A VGA to video encoder106may be provided to convert the signal for use with a videotape recorder108or a display device. According to one embodiment of the disclosed subject matter, before the video signal is output from the computer system102to either the display device112or the videotape recorder108, a number of additional signals are incorporated into the horizontal sync signals. Thus, the video signal output from the computer system102across communication lines to the display device112or108includes both an original set of horizontal sync pulses which represents a correct image to be displayed along with a set of additional or invalid sync pulses which, without the present decoding technique, prevents a display from recognizing the signal. This results in a display output that is not recognizable and thus not valuable for copying.

An embodiment of the disclosed subject matter also preferably includes a decoder device110, either internal or external to the display device112. The decoder device110is programmed to recognize the anti-copying protocol and to decode the original H-sync signals from the combination signal, which includes both the original H-sync pulses along with the added or invalid H-sync pulses. The decoder device110then essentially filters out the additional or invalid H-sync pulses and outputs only the original H-sync pulses, thus, providing the original video signal only, without the additional H-sync pulses, to the display112.

Referring now toFIG. 2, a simplified block diagram of a typical computer system200is shown including a video card250. A central processing unit202is coupled to a host bus210. The central processing unit202may be a single microprocessor, such as Intel Corporation's PENTIUM4® or Advanced Micro Devices, Inc.'s ATHLON™ or a more complete computer system including multiple microprocessors, a cache controller, external co-processors, and other components, coupled to one another or to the host bus210. The host bus210functions to interface the CPU202to the rest of the computer system200. The host bus210typically is located on a motherboard but may be configured as any of another of other sub-systems as well known in the art.

Also coupled to the host bus210is a cache204. The cache204may be a write-through, a write-back, or multiple cache systems for storing commonly used or recently used data values. The cache generally consists of a high-speed static RAM structure, addressable within the memory space of the CPU's address lines.

A main memory206, typically comprising a dynamic RAM, is coupled to the memory controller bridge226. The main memory206provides relatively high-speed data storage for instructions and data needed for the processor202to perform its functions. Also included in many computer systems is a dedicated ROM236, providing system BIOS and other firmware sets of instructions to the processor202, on initial boot up and also thereafter.

Also coupled to the memory controller bridge226is an I/O controller hub224. The I/O controller hub224typically has a disk controller with a number of IDE ports to couple external devices. The disk controller in the I/O controller hub224provides a connection to a CD-ROM drive212, a DVD drive218, and a hard disk drive214. The CD-ROM drive212and the DVD drive218provide optical storage and data retrieval capabilities, and the hard drive214provides magnetic storage device capabilities to the computer system200. An AC-97 CODEC258and speakers260can also be connected to the I/O controller224.

Also coupled to the I/O controller hub224is a PCI bus222. The disk controller in the I/O controller hub224can be a separate device on the PCI bus222. The PCI bus222is coupled to a plurality of additional devices, including a network interface controller252, an audio device or audio card254, and in some embodiments an additional PCI bridge (not shown). The audio card254generally is coupled to audio speakers256or some other audio output device to provide an audio output.

The AGP extension bus220, coupled to the memory controller bridge226, provides an extension for additional peripheral components, typically video related. The AGP extension bus220is coupled to an additional device, such as the video card250. The video card250typically includes a graphics controller208and a video encoder/decoder (CODEC)228. The video card250is coupled to a monitor240via one or more coaxial cables or other computer connectors. Alternatively, the graphics controller208and the video card250can be coupled to the PCI bus222.

The graphics controller208is electronic circuitry that takes data that represents a computed image and converts it to a varying electrical signal that drives an external display device so as to produce a visible representation of the image. A video processor is a set of electronic circuitry which takes data which represents a moving picture (e.g., a movie) and modifies it in some way (e.g., increases the saturation) to generate a resultant data which is typically sent to the graphics controller208for display.

In a PC, the graphics controller208will typically contain video processing circuitry which is used to change the color space of the input image, scale it, and de-interlace it so it is in a format which the graphics controller208can use for display. For example, MPEG uses a YCrCbcolorspace but all VGAs have ADCs that use the RGB colorspace so the video processing circuitry executes a matrix transformation to convert between the two colorspaces.

An extension bus230is coupled to the I/O controller hub224, providing an extension for additional peripheral components. A super input/output controller232, coupled to the extension bus230, typically provides a connection between the extension bus230, a mouse device234, a parallel port262, serial ports264, and a keyboard device248. Although these devices are shown coupled through the super input/output controller232to the extension bus230, it should be noted that other configurations are possible; for example, the mouse device234and the keyboard248may instead be coupled to an infrared device for communicating directly to a remote controller interface (not shown) via wireless technology. Additionally, the super input/output controller232provides a connection to a floppy disk drive216, which provides additional magnetic storage device capabilities for the computer system200.

The computer system200may be of any number of different configurations and components. It will be recognized that additional devices may be coupled via various connects to the various buses. The flexibility of computer system200is not restricted to particular example shown inFIG. 2. Instead, a wide variety of systems could be used instead of the disclosed computer system200without departing from the spirit of the invention.

According to an embodiment of the disclosed subject matter, copy protection is implemented by reading video data from DVD218after a certain internal authentication and encryption is performed. The encrypted video stream is then communicated to the CPU202, where decryption is performed. CPU software decodes and generates the digital video and audio, which is then communicated across the AGP bus220, to the video card250. The audio is sent across the PCI bus222to the audio card254. The video then is output from the video card250where a monitor240receives the signal through a VGA connector on the back of the video card250. The monitor240may be any display device, such as the display device112ofFIG. 1.

FIG. 3depicts an embodiment of the copy protection system. In this case, copy protection data is transmitted on a green signal310between two H-sync pulses332and334on the horizontal sync line330and the vertical blanking interval occurs when a vertical synchronization signal320is high. The actual encoding of the data and the polarity of the signals can vary. According to one embodiment, a preamble340is provided to allow a receiver to synchronize to a clock signal embedded within a data350resulting in copy protected transmission of eight bits of data. Other protocols and word lengths can be utilized without departing from the disclosed subject matter. Further, other RGB signal lines and timing outside the vertical blanking intervals can be utilized for transmission of the copy protection signals without departing from the disclosed subject matter.

Turning now toFIG. 4, shown is the relationship between the H-sync (410) and V-sync (420) video signals. Specifically, H-sync pulses402and404may be either original H-sync pulses and output from the DVD player or may be additional or invalid H-sync pulses added to the video signal during processing by the video card250. Also shown is an exemplary pulse sequence identifier406which provides information to the decoder on the receiving end, such as decoder device110, regarding the location of invalid H-sync pulses along with the location of the next pulse sequence identifier (seeFIG. 5). According to one embodiment, the pulse sequence identifiers406are placed on the H-sync signal410during the V-sync blanking interval408. However, with only minor modifications, the pulse sequence identifiers406may be placed at any point within the H-sync signal410. Thus, during the vertical-blanking interval408, when the V-sync signal420is active, the pulse sync identifier406is modulated onto the H-sync line410between H-sync pulses402and404, for example. This pulse sync identifier406then is read by the receiving authorized display device112to determine which H-sync pulse signals are valid signals and which H-sync pulse signals are invalid and should be ignored. According to an alternative embodiment, with only minor modifications, the copy protection signals may be placed on the V-sync signal420.

Referring now toFIG. 5, shown is an exemplary lookup table500according to an embodiment of the disclosed subject matter. With reference toFIG. 4, the receiving display device112expects to receive the pulse sequence identifier406after the first H-sync pulse402, during the vertical-blanking interval408. The pulse sequence identifier406that is modulated onto the H-sync signal410has a value in this example of 10101010b (where the trailing “b” indicates the value is a binary value). The display112then uses the lookup table500as part of the decoder device110to determine the next sequence of valid H-sync pulses and the location of the next valid pulse sequence identifier406. According to the lookup table500, the pulse sequence identifier value406provides the information in code column520given in entry2. The horizontal sync sequence530of entry2informs the decoder device110that beginning with the next H-sync pulse sequence, the first three H-sync pulses are valid, the next two H-sync are to be ignored, the next four H-sync pulses are valid and the final three H-sync pulses are to be ignored. This means that the first three H-sync pulses that the decoder device110receives are valid and should in fact be used or passed to the display device. The next two H-sync pulses are invalid and should be discarded or filtered from the display device112. The next four H-sync pulses are valid and should be used, then the next three H-sync pulses are invalid and should be filtered. The addition of the invalid pulses will prevent a receiver device without the copy protection system from locking onto the horizontal synchronization signal thus resulting in a blank display.

The fourth column540in the table500provides the display112with information of the location of the next valid pulse sequence identifier. Thus, for entry2, the next valid pulse sequence identifier will be received in the 32ndblanking line on the next frame. The decoder device110is then able to ignore all pulse sequence identifiers occurring between this received pulse sequence identifier and the identifier at the 32ndblanking line on the next frame. This feature makes it difficult to determine which pulse sequence identifier is actually controlling the decoder device110. Until this valid decoding pulse sequence identifier is received, the H-sync sequence is repeated to determine the valid sync pulses. After a specified number of valid pulse sequence identifiers406are received, the process is reset and begins anew. This reset feature allows, among others, for quick recovery if the decoding circuit110in the display device112loses its synchronization. It should be noted the next valid pulse sequence identifier406can be generated randomly or according to a finite set of location identifiers or other methods without departing from the disclosed subject matter. Further, the codes in columns520and their interpretation in columns530and540are exemplary and illustrative only, and other codes520and interpretations530and540can be used.

Turning now toFIG. 6, shown is a simplified timing diagram illustrating the relationship between original sync pulses and additional or invalid sync pulses. Specifically, the top vertical sync (612) and horizontal sync (614) signal group610represents the output from the graphic controller104ofFIG. 1. This group of signals represents the original unprotected signal output. The bottom horizontal sync signal620includes the original horizontal sync pulses616of the top horizontal sync signal614in combination with the additional or invalid sync pulses622which comprise the encoded output. As can be seen, the additional sync pulses622are added in a random or non-repeating pattern according to the lookup table500ofFIG. 5, for example. A previous pulse sync406identifier then will have informed the receiving decoding device110as to which of the horizontal sync pulses of the encoded output are valid and which should be filtered as invalid pulses.

Turning now toFIG. 7, shown are flow diagram for the encoding (702) and decoding (720) processes. Referring back toFIG. 1, the encoding process702occurs at a DVD or other video signal generation side of the viewing system100, such as at the computer system102and the graphics controller104. The decoder decoding process720, on the other hand, occurs at the display device112and at the decoder device110. Beginning with the video signal generation side, a video signal is encoded according to the encoding process702. Beginning at step704, the encoding process is initiated once the video signal has been determined to be a copy protected video signal. In other words, for video signals that do not require any copy protection, the encoding process, including adding additional H-sync pulses and pulse sequence identifiers, is bypassed, allowing the video signal to be transmitted in its original form at step712. If the video signal is indicated as a video signal to be copy protected, the process continues at step706where invalid H-sync pulses622are added to the set of original H-sync pulses616as shown inFIG. 6. In step708, according to one embodiment, the system detects whether the outgoing signal is within a vertical blanking interval. If so, at step710the pulse sequence identifier406is added to the video signal shown inFIG. 7as a green signal310ofFIG. 3. If not, the now combined set of original H-sync pulses616and invalid H-sync pulses622are directly transmitted as the outgoing video signal to the display device at712. According to one embodiment, the pulse sequence identifiers406are added to the green video signal (not shown inFIG. 6) only during a vertical-blanking interval. It should be understood that with minor modifications to the disclosed embodiment, such a restriction is not required and pulse sequence identifiers406may be incorporated into the outgoing video signal at any point in time.

On the decoding side, the decoding process720begins at step722where the decoder device110detects whether the video signal is copy protected. If not, the video signal is immediately passed to the display device112where it is displayed. In that instance, no invalid H-sync pulses622have been added, thus, there is no need to perform any filtering function. If the video signal is in fact copy protected, control proceeds to step724where the decoder device110recognizes invalid H-sync pulses622from original H-sync pulses616based on a prior received pulse sequence identifier406. At step724, the decoder device filters out all invalid H-sync pulses622from the original H-sync pulses616. The original H-sync pulses616are then passed to the display device112, which then displays the image represented by the video signal as intended. At step726, if within a vertical blanking interval, the decoder device receives the next pulse sequence identifier406at step728. This next pulse sequence identifier406represents the next sequence of valid and invalid H-sync pulses616and622and, in addition, the location of the next valid pulse sequence identifier406. This information is used to decode the next set of H-sync pulses. If not within a vertical blanking interval at step726, the decoding device110does not attempt to detect such a pulse sequence identifier406, but instead, directly transmits the decoded video signal or filtered video signal to the video display device112. The video display device112may then display the video signal at step730. Additional steps such a validation and authentication of the source and receiver devices can be added within the spirit of this invention.

Although shown inFIG. 7as the green video signal, the video signal encoded or decoded by encoding steps702or decoding steps720can be any video signal. One skilled in the art will recognize that the flowcharts ofFIG. 7are exemplary and illustrative only and other techniques or steps and other ordering of steps could be used. Additionally, the illustrated steps can be implemented in multiple ways, including software, firmware, or hardware.

Turning now toFIG. 8, shown are schematic representations of logic associated with the encoding process and decoding process. At the video signal generation side, the encoder is represented by encoder logic802. The encoder logic802illustrates an exemplary embodiment for combining the encoded control logic output containing the additional or invalid H-sync signals622onto the original H-sync signal814, corresponding to the signal614ofFIG. 6, containing the original set of H-sync pulses616. The Encode input810indicates whether the copy protection system should be engaged. The Hsync and Vsync signals814and812are the unencoded synchronization signals from the VGA's CRT controller250ofFIG. 2. The clock804is a free running oscillator. The state machine806generates both the additional horizontal synchronization pulses622to be inserted into the horizontal synchronization signal814and the control word (the pulse sequence identifier406) to be inserted into the green signal816. Output818of the state machine806is ORed by OR gate808with the original horizontal synchronization signal814to generate the encoded horizontal synchronization signal815(corresponding to signal620ofFIG. 6). XOR gates can be inserted onto the various synchronization pulse inputs and outputs to control polarity. The other output819of the state machine806is wire-ORed (i.e., the output is physically connected) to the green output816to generate the encoded green output817. This works because the green output816will be low during the vertical-blanking interval. A simple variation would be to switch the green output816between the VGA's green output819and the output of the state machine806. The output level of the green signal817could then be increased when the pulse sequence identifier406is sent. This would potentially damage receivers that do not support the copy protection system that attempted to connect to the copy protected output. In one embodiment, the encoder802can be integrated into the VGA.

The decoding process is represented by decoder logic820. According to one embodiment, decoding of the encoded H-sync signal815encoded by encoder802is performed by control logic826, receiving input pulse sequence identifier information from the data821of the green signal output817as well as the V-sync signal812to determine when a vertical blanking interval occurs. The XOR gate822is used to invert the vertical synchronization pulse producing the Vgate signal840in the case where the vertical synchronization is active low instead of high. The receiving device can determine the polarity of the V-sync synchronization signal812using standard techniques known to those skilled in the art. The comparator824is used to convert the incoming analog signal on the green line817to a digital signal by comparing it to a specific voltage reference834. The output of the comparator824, data signal838, is gated by the AND gate828with the Vgate signal840so the PLL832clock input836is only active when a pulse sequence identifier is being received. This allows the PLL832to recover the clock in the control word so the data signal838can be decoded. The clock836, the data838, and the V-sync synchronization pulses on the Vgate signal840are used to drive the state machine826that controls the gating of the horizontal synchronization pulses on encoded H-sync signal815. The encoded horizontal synchronization is gated by the AND gate830in conjunction with the output of the state machine826so the original horizontal synchronization signal814is reconstructed. An additional XOR gate could be included to allow the output polarity of the horizontal synchronization signal814to be inverted. In one embodiment, the decoder820is integrated into logic within the receiving device112. One skilled in the art will recognize that the logic elements shown inFIG. 8are exemplary and illustrative only, and other logic elements and other connections or arrangements of logic elements can be used.

Thus, according the disclosed subject matter, a video signal copy protection apparatus and protocol is provided. The protocol is flexible to provide copy protection for any number of video signal sources including DVD, protected satellite transmissions and other subscription type video services. A computer system or device is provided with encoding functions to add video protection signals onto an original video output. Specifically, a number of additional horizontal synchronization pulses, indistinguishable from original horizontal synchronization pulses, are added onto the horizontal synchronization signal. Without decoding, inclusion of these additional H-sync pulses prevent a display device or a video tape recorder from receiving or generating a coherent video image from the modified video signal. The computer system or computer device also modulates onto a portion of the outgoing video signal an identifier code for use in the decoding process.

A decoder device is provided to receive the modified H-sync signal, including the original H-sync pulses along with the added H-sync pulses and the rest of the video signal including the identifier code. The decoder device decodes the H-sync signal according to the identifier code, which identifies the original H-sync pulses from the additional H-sync pulses. A lookup table is provided at the decoder device to allow for a number of constantly changing mapping schemes represented by an equal number of different identifier codes. The decoder device then filters the added or invalid H-sync pulses from the video signal and passes the filtered signal to the display device. Enhanced copy protection is provided as the sequence of added H-sync pulses is constantly changing, this function is supported by the simplicity of the lookup table and the fact that attached with every sequence of added H-sync pulses is also included a next pulse sequence identifier and the location of the next pulse sequence identifier.

Additional copy protection is provided by encoding a number of invalid H-sync pulse identifiers along with the valid H-sync pulse identifiers. Specifically, H-sync pulse identifiers are encoded onto the video signal at varied locations in the video signal. Only the sequence identifier that is received at the expected identifier location at the decoder device is actually used to perform the decoding functions. Thus, a multi-level copy protection system is provided with only minor modifications to a computer system along with a receiving or authorized display device.

The foregoing disclosure and description of the various embodiments are illustrative and explanatory thereof, and various changes in the video source video player, the display device, the computing device, the description of the video signal, the graphics controller and other circuitry, the organization of the components, and the order and timing of steps taken, as well as in the details of the illustrated system may be made without departing from the spirit of the invention.