Method of manufacturing wiring board

A method of manufacturing a wiring board including an insulating layer where a semiconductor chip is embedded includes: forming, on a supporting board, the insulating layer where the semiconductor chip is embedded and a wiring connected to the semiconductor chip; removing the supporting board by etching; and simultaneously forming first and second reinforcing layers so as to sandwich the insulating layer after removing the supporting board.

This application claims foreign priority based on Japanese Patent application No. 2005-246438, filed Aug. 26, 2005, the content of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing a wiring board, and in particular to a wiring board in which a semiconductor chip is incorporated.

2. Description of the Related Art

Nowadays, the performance of electronic apparatuses that use semiconductor devices such as semiconductor chips are being advanced, and as a result, there are demands for mounting semiconductor chips on a board at a higher density, and miniaturizing and downsizing the board to which the semiconductor chips are mounted.

Thus, there have been proposed substrates in which semiconductor chips are built, so-called chip built-in wiring boards (for example, refer to JP-A-2004-327624) and various structures designed to build a semiconductor chip in a substrate. Such a chip built-in wiring board has wiring connected to a semiconductor chip and includes a connecting section formed thereon to connect the wiring board to another device, a mother board, etc.

A possible warpage of a wiring board has presented a problem in a case where a chip built-in wiring board with a thinner design and higher packing density is to be provided. To cope with such a warpage, a structure is required where a board such as a core board having a predetermined thickness is laminated on a layer where a semiconductor chip is embedded for effective suppression of warpage. In such a laminated structure, it is difficult to achieve a thinner design and higher density of a wiring board.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above circumstances, and provides a method of manufacturing an innovative and useful wiring board that solves the above problems.

An object of an embodiment of the invention is to achieve a thinner chip-built-in wiring board as well as to suppress warpage of the wiring board.

In some implementations of the invention, a method manufacturing a wiring board comprising:

forming, on a supporting board, an insulating layer in which a semiconductor chip is embedded and a wiring being connected to the semiconductor chip;

removing the supporting board; and

forming a first reinforcing layer and a second reinforcing layer simultaneously so as to sandwich the insulating layer after removing the supporting board.

According to the method of the invention, the supporting board is removed after the insulating layer where a semiconductor chip is embedded and the wiring connected to the semiconductor chip are formed, and the first and second reinforcing layers are simultaneously formed so as to sandwich the insulating layer and the like where the supporting board is absent. In general, a reinforcing layer shows large shrinkage on curing. However, since the first and second reinforcing layers are simultaneously formed so as to sandwich the insulating layer, the shrinkage on curing is uniformly applied from above and below the insulating layer, thus preventing an occurrence of warpage.

In the method of manufacturing a wiring board, the reinforcing layer is made of a prepreg material.

According to the method of the invention, a prepreg material is used as a reinforcing layer. This makes it easy to form the reinforcing layer as well as enhance the rigidity of the reinforcing layer.

The method of manufacturing a wiring board comprising:

forming a stop layer on the supporting board before the insulating layer and the wiring are formed on the supporting board,

wherein the removal of the supporting board is stopped by the stop layer.

According to the method of the invention, removal of a supporting board is stopped by the stop layer thus preventing removal of the supporting board from having an effect on the layers that are inside of the stop layer. Control of removal processing in removing the supporting board is made easy, and thus the manufacture of a wiring board is simplified.

The method of manufacturing a wiring board comprising:

forming a first solder resist layer and a second solder resist layer simultaneously after forming the first reinforcing layer and the second reinforcing layer, the first solder resist layer being laminated on the first reinforcing layer, and the second solder resist layer being laminated on the second reinforcing layer,

wherein an opening is formed at a wiring position in each of the first solder resist layer and the second solder resist layer.

The method of manufacturing a wiring board comprising:

performing surface treatment simultaneously on a first wiring and a second wiring that are exposed from the opening formed in the first solder resist layer and the second solder resist layer respectively, after the first solder resist layer and the second solder resist layer are formed.

According to the method of the invention, it is possible to simultaneously form layers that are formed on and under the insulating layer, thus the manufacturing process is facilitated and time required for manufacture is reduced.

According to the method of the invention, it is possible to provide a thinner chip-built-in wiring board that suppress a warpage in the wiring board.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred embodiment of the invention will be described referring to drawings.

FIG. 1is a schematic cross-sectional view of a wiring board100manufactured by a method of manufacturing a wiring board as an embodiment of the invention. For the purpose of explanation, the structure of the wiring board100will be described before describing the method of manufacturing the wiring board100.

As shown inFIG. 1, the wiring board100manufactured in this embodiment has an insulating layer106including a so-called buildup resin material such as epoxy where a semiconductor chip110is embedded. First and second reinforcing layers103,114are formed with respect to the insulating layer106.

The reinforcing layers103,114are arranged so as to sandwich the insulating layer106from top and bottom as shown in the figure. The reinforcing layers103,114are formed using a material having a high rigidity such as a prepreg material. The insulating layer106is formed of a buildup resin material that is flexible as mentioned earlier. By providing reinforcing layers103,114to sandwich the insulating layer106, the insulating layer106is reinforced by the reinforcing layers103,114.

The semiconductor chip110is connected to a wiring section (described later) and is connected to an electrode102formed in an opening in a solder resist119or an electrode118formed in an opening in a solder resist117via the wiring section. The electrode102or118is used for connection to a mother board, another device, or a connecting device, for example.

On the electrode pad (no shown) of the semiconductor chip110is formed a stud bump111composed of for example Au. The stud bump111is connected to a wiring section108embedded in the insulating layer106via a solder-connecting section109, for example. Under the semiconductor chip110is formed an underfill layer110A from the viewpoint of protecting the stub bump111and suppressing generating of a stress.

The wiring board100has wiring sections105,113,116as well as the wiring section108. The wiring sections105,108,113,116are formed of for example, Cu.

The wiring section105includes a via plug105aand pattern wiring105b. The via plug105ais formed at the opening formed in the reinforcing layer103. On the reinforcing layer103is formed pattern wiring105bconnected to the via plug105a.

The wiring section108is formed in the insulating layer106. The wiring section108is formed above the wiring section105as shown in the figure. The wiring section108includes a via plug108aformed on the pattern wiring105band a pattern wiring108bconnected to the via plug108a. To the pattern wiring108bis connected a semiconductor chip110via the solder-connecting section109and the stud bump111as described earlier.

The wiring section113is formed in the insulating layer106. The wiring section113is formed above the wiring section108as shown in the figure. The wiring section113is electrically connected to the wiring section108. The wiring section113includes a via plug113aformed on the pattern wiring108band a pattern wiring113bconnected to the via plug113a.

The wiring section116is formed above the wiring section113as shown in the figure. The wiring section116is electrically connected to the wiring section113. The wiring section116includes a via plug116aformed on the pattern wiring113band a pattern wiring116bconnected to the via plug116a. The via plug116ais formed at the opening formed in the reinforcing layer114. The pattern wiring116bis formed above the reinforcing layer114.

At the opening in solder resist119positioned below the insulating layer106is formed an electrode102connected to the via plug105a. At the opening of the solder resist117positioned above the insulating layer106is formed an electrode118connected to the pattern wiring116b. Thus, the wiring board100may provide electric connection to the semiconductor chip110via the electrodes102,118on top and bottom.

The solder resist layers119,117are formed so as to cover the reinforcing layers103and114. In each solder resist layer119,117is formed an opening for forming the electrode102,118. A solder ball120is formed as required on the electrode102. The solder ball120may be formed on the electrode118.

The wiring board100thus structured has the insulating layer106where the semiconductor chip110and the wiring sections105,108,113,116are embedded, the insulating layer106sandwiched by a pair of reinforcing layers103,114. Thus, even when the insulating layer106is made of a flexible resin material, the insulating layer106is reinforced from both sides by the reinforcing layers103,114with high rigidity, which reduces a warpage in the wiring board100and provides the wiring board100with high flatness and that can cope with a finely arranged wiring.

For example, the reinforcing layers103,114are preferably formed using a prepreg material. The prepreg material may be used as a material of a core board used to form a multi-layer wiring board (buildup board).

For example, the prepreg material has a structure where glass fibers are impregnated with an epoxy resin and has a higher post-heat-curing rigidity than a general buildup resin material. For example, the elastic modulus (Young's modulus) of a buildup resin material is about 5 GPa to 8 GPa while the elastic modulus of a prepreg material is 20 GPa or above, which shows the high rigidity of the latter that reduces a warpage in a wiring board.

A material used for the reinforcing layers103,114is not limited to a prepreg material but may be a mold resin with high rigidity. A material used for the reinforcing layers103,114may be a metallic material although a structure to insulate the wiring section from the reinforcing layer is preferably added in case a conductive material such as a metal is used. The wiring board100according to this embodiment may be formed based on a buildup method that allows a thin design of the wiring board100.

Next, the method of manufacturing the wiring board will be described step by step referring toFIGS. 2 to 21.

In the process shown inFIG. 2, a supporting board101of 200 micrometers thick, formed of a conducting material such as Cu is provided. A stop layer121is formed on the supporting board101by the electroplating method. The stop layer121is a nickel film 2 to 3 micrometers thick and is formed on the top surface of the supporting board101by using the supporting board101as an electrode by the electroplating method.

On that occasion, for the electroplating, the supporting board101works as an energizing path. The supporting board101is preferably a conductive material, or more preferably, a low-resistance material such as Cu.

In the process shown inFIG. 3, pattern wiring105bis formed on the supporting board101where a stop layer121is formed. To be more precise, the pattern wiring105bforms a resist pattern (not shown) by way of photolithography. The resist pattern is used as a mask to deposit Cu by electroplating, and the resist pattern is removed to form the pattern wiring105b.

Next, in the process shown inFIG. 4, the insulating layer106is formed on the supporting board101so as to cover the pattern wiring105b. The insulating layer106is made of a buildup material such as a thermosetting epoxy resin. In the insulating layer106formed on the supporting board101is formed a via hole106A with laser beams so as to expose part of the pattern wiring105b.

Next, in the process shown inFIG. 5, desmear process is performed on the surface of the insulating layer106as required, and the residue in the via hole is removed and surface treatment made. A seed layer107of Cu is formed on the surface of the insulating layer106and the exposed pattern wiring105bby electroless plating.

Next, in the process shown inFIG. 6, the photolithography method is used to form a resist pattern (not shown). Next, the resist pattern is used as a mask to apply electroplating with Cu to form a via plug108ain the via hole106A as well as form a pattern wiring108bintegrally connected to the via plug108aon the insulating layer106. The via plug108aand the pattern wiring108bconstitute a wiring section108. When the wiring section108is formed, the resist pattern is stripped and an excessive seed layer107exposed is removed by etching.

Next, in the process shown inFIG. 7, an insulating layer106ais formed on the insulating layer106so as to cover the wiring section108. The insulating layer106ais a buildup material made of for example a thermosetting epoxy resin, the same material as that of the insulating layer106. Thus, the insulating layer106aand the insulating layer106are substantially integral. In the process shown inFIG. 7and afterwards, the insulating layer106is assumed to include the insulating layer106a.

Next, in the process shown inFIG. 8, an opening106B is formed in the insulating layer106by using the laser beam machining method so as to expose part of the wiring section108(via plug108a). Next, the desmear process is applied to the insulating layer106as required to remove residue in the opening and perform surface treatment. After that, as shown inFIG. 9, the electroplating method is used to form a solder-connecting section109at the opening106B.

Next, in the process shown inFIG. 10, a process to mount a semiconductor chip110on the insulating layer106is executed. The semiconductor chip110has a stud bump111of Au formed thereon in advance. On the semiconductor chip110, the stud bump111and the solder-connecting section109are positioned to correspond to each other and are flip-chip connected onto the wiring section108(pattern wiring108b). On that occasion, an underfill layer110A is formed between the semiconductor chip110and the insulating layer106.

Next, in the process shown inFIG. 11, the insulating layer106bis formed on the insulating layer106so as to cover the semiconductor chip110. The insulating layer106bis a buildup material such as a thermosetting epoxy resin. The insulating layer106band the insulating layer106are substantially integral. In the process shown inFIG. 11and afterwards, the insulating layer106is assumed to include the insulating layer106b.

Next, in the process shown inFIG. 12, a via hole106C is formed in the insulating layer106. The via hole106C is formed so as to expose the pattern wiring108bfor example by using the laser beam machining method. Next, the desmear process is applied on the surface of the insulating layer106as required, thus removing residue in the via hole and performing surface treatment.

Next, on the surface of the insulating layer106and on the surface of the pattern wiring108bis formed a seed layer112made of Cu by the electroless plating method. The seed layer112is electrically connected to a supporting board101made of Cu via the wiring section108, pattern wiring105b, and a stop layer121made of Ni.

Next, in the process shown inFIG. 13, the photolithography method is used to form a resist pattern (not shown). Next, the resist pattern is used as a mask to apply electroplating with Cu to form a via plug113ain the via hole106C as well as form a pattern wiring113bconnected to the via plug113aon the insulating layer106. The via plug113aand the pattern wiring113bconstitute a wiring section113. When the wiring section113is formed, the resist pattern is stripped and an excessive seed layer exposed is removed by etching.

Next, in the process shown inFIG. 14, an insulating layer (buildup layer)106cmade of for example a thermosetting epoxy resin is formed on the insulating layer106so as to cover the wiring section108. The insulating layer106cand the insulating layer106are substantially integral. In the process shown inFIG. 14and afterwards, the insulating layer106is assumed to include the insulating layer106c.

In each of the foregoing processes, a process is made to laminate the insulating layer106, pattern wiring105b, and wiring sections108,113on the supporting board101. On that occasion, the insulating layer106is made of a resin material with a small elastic modulus and with a dense filler packed therein, which is unlikely to generate a warpage in the layer. Thus, No problematic warpage will take place in the processes show inFIGS. 2 to 14.

Next, in the process shown inFIG. 15, the supporting board101is removed by etching. The etching liquid used should dissolve the supporting board101(Cu) but not Ni of the stop layer121. This causes the stop layer121to stop removal of the supporting board101, thereby preventing the etching liquid from having an effect on the layers inside the stop layer121, that is, the insulating layer106, the pattern wiring105b, and the wiring sections108,113. Management of removal processing in removing the supporting board101is made easy thus simplifying the manufacture of the wiring board100. When removal of the supporting board101is complete, the stop layer121is removed with an etching liquid that dissolves Ni but does not resolve Cu.

The supporting board101is removed, which means that no members support the insulating layer106. When the supporting board101is removed, the insulating layer106is about 200 to 300 micrometers thick assuring a rigidity to withstand handling. The absence of the supporting board101does not become an obstacle to processes shown inFIG. 16and after that are described later.

Next, in the process shown inFIG. 16, a reinforcing layer103is formed under the insulating layer106and a reinforcing layer114is formed at the same time on the insulating layer106. The insulating layer106is sandwiched by the reinforcing layers103and114.

Here, the reinforcing layers103and114are formed simultaneously. This means that curing of the reinforcing layers103and114are performed simultaneously so that shrinkage of the reinforcing layers103and114on curing is uniformly applied from above and below the insulting layer106, etc., thus preventing a possible warpage of the wiring board. Also, by performing the curing simultaneously, a heat history of the reinforcing layer103and a heat history of the reinforcing layer114can be identical.

In this case, the reinforcing layers103and114are pressed and attached temporarily to the insulating layer106, and then the curing is performed. The reinforcing layers103and114may be attached to the insulating layer106separately, or simultaneously.

The reinforcing layers103,114are formed for example by laminating a prepreg material under heat and pressure. The prepreg material has a structure where glass fibers are impregnated with an epoxy resin as mentioned earlier and has a higher post-heat-curing rigidity than a general buildup resin material. For example, the elastic modulus (Young's modulus) of a buildup resin material is about 5 GPa to 8 GPa while the elastic modulus of a prepreg material is 20 GPa or above, which shows the high rigidity of the latter that reduces a warpage in a wiring board.

Next, in the process shown inFIG. 17, a via hole103A is formed in the reinforcing layer103by using laser beams so as to expose pattern wiring105b. Then, via holes114A are formed in the reinforcing layer114and an insulating layer106by using laser beams so as to expose a wiring section113(pattern wiring113b). The via holes103A and114A are simultaneously formed.

Next, in the process shown inFIG. 18, the desmear process is applied as required to the bottom surface of the reinforcing layer103and the top surface of the reinforcing layer114in order to remove residue in the via hole and surface treatment. Then, seed layers104,115of Cu are respectively formed on the bottom surface of the reinforcing layer103and the top surface of the reinforcing layer114(including part of the insulating layer106exposed from the via hole114A) by the electroless plating method. The seed layers104,115are simultaneously formed.

Next, in the process shown inFIG. 19, the photolithography method is used to form a resist pattern (not shown) in the seed layer104and the seed layer115. Next, the resist pattern is used as a mask to apply electroplating with Cu to form a via plug105aon the reinforcing layer103so as to provide connection to the pattern wiring105b. The via plug105aand the pattern wiring105bconstitute a wiring section105.

At the same time, the resist pattern is used as a mask to form a via plug116aby electroplating with Cu so as to provide connection to the pattern wiring113bexposed from the via hole114A formed in the reinforcing layer114. On the reinforcing layer114is formed pattern wiring116bto provide connection to the via plug116a. The via plug116aand the pattern wiring116bconstitute a wiring section116.

After the wiring sections105,116are formed, the resist pattern is stripped and the excessive seed layers104,115exposed are removed by etching.

Next, in the process shown inFIG. 20, a solder resist119is formed to cover the reinforcing layer103and an opening119A is formed at a predetermined position where the wiring section105(via plug105a) of the solder resist119is exposed. A solder resist117is formed so as to cover the reinforcing layer114. An opening117A is formed at a predetermined position where the wiring section116(pattern wiring116b) of the solder resist117is exposed. The solder resist117including the opening117A and the solder resist119including the opening119A are simultaneously formed.

Next, in the process shown inFIG. 21, an electrode118including for example an Au layer118aand an Ni layer118bis formed on the wiring section116(pattern wiring116b) exposed from the opening117A. An electrode102including for example an Au layer102aand an Ni layer102bis formed on the wiring section105(via plug105a) exposed from the opening119A (surface treatment). The electrode102and the electrode118are simultaneously formed.

After that, a solder ball120is formed on the electrode102to form the wiring board100shown inFIG. 1.

The above manufacturing method is a buildup method that uses a coreless structure (structure without a supporting board). This approach provides a thin, compact and lightweight design of a wiring board. Use of the reinforcing layers103,114reduces a warpage in the wiring board. This makes it possible to form a thin wiring board that includes a superfine wiring section.

In this embodiment, the insulating layer106where the semiconductor chip110is embedded and wiring sections105,108,113are formed, and then the supporting board101is removed. The reinforcing layers103and114are simultaneously formed to sandwich the insulating layer106to which the supporting board101is not attached. In general, each of the reinforcing layers103,114show a large shrinkage on curing. The reinforcing layers103,114are simultaneously formed so as to sandwich the insulating layer106, the wiring section116, etc. Thus, the shrinkage on curing is uniformly applied from above and below the insulating layer106, the wiring section116, etc., thus preventing a possible warpage.

According to this embodiment, in the processes that follows removal of the supporting board110, to be more specific, in the processes shown inFIGS. 15 to 21, processing on the top surface of the insulating layer106and processing on the bottom surface shown in the figure take place simultaneously. In this way, after the supporting board101is removed, layers are simultaneously formed on and under the insulating layer106thus facilitating the manufacturing process and reducing time required for manufacturing.

While the invention has been described referring to preferable embodiments, the invention is not limited to these specific embodiments but variations and change may be made to the invention without departing from the claims.