Self-aligned contact formation for semiconductor devices

In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.

FIELD OF THE INVENTION 
The present invention relates generally to contact formation on an 
integrated circuit, and more specifically to forming contacts on an 
integrated circuit to enhance fabrication yield. 
BACKGROUND OF THE INVENTION 
Integrated circuits, such as dynamic random access memories (DRAMs), are 
fabricated with devices that have microscopic features that can only be 
manufactured with processing steps that require careful alignment of 
equipment used to build the devices. The manufacturing costs of integrated 
circuits are expensive because (1) the processing steps must be 
accomplished with costly and sophisticated equipment, and experienced 
operators, and (2) such steps are not always successful. For example, if 
the processing equipment, such as a mask, is inadvertently misaligned, 
then the DRAM may be fabricated incorrectly and fail. As a result, 
processing yields decrease and production costs increase. Therefore, to 
reduce manufacturing costs, a DRAM fabrication process that has enhanced 
process tolerances is desirable. Such a process would permit successful 
fabrication of DRAMs, despite minor misalignments. 
U.S. Pat. No. 5,439,846 to Nguyen et al. (hereinafter the Nguyen Patent), 
which is herein incorporated by reference, discloses a method of 
fabricating transistor contacts in DRAMs. The Nguyen Patent teaches 
consecutively forming silicon nitride, tungsten silicide, polysilicon, 
gate oxide and a field oxide on a silicon substrate to partially construct 
a transistor. Subsequently, a nitride etch is performed. Thus, a portion 
of the silicon nitride, defined by a masking process, is removed to expose 
the tungsten silicide. As a result, a contact can be later deposited on 
and connected to the exposed gate contact opening of the transistor. 
Next, the Nguyen Patent teaches performing a gate etch to define gate 
stacks. Thus, portions of silicon nitride, tungsten silicide, polysilicon 
and gate oxide are removed from the substrate. However, if the nitride and 
gate etches are misaligned, for example due to mask misalignment, then 
field oxide may be inadvertently removed, or a sliver of silicon nitride 
may be formed on the gate contact. If field oxide is inadvertently 
removed, then the contact could short the gate stack to the silicon 
substrate. Hence, the transistor gate and active regions may be coupled, 
disabling the transistor. Alternatively, if the silicon nitride sliver is 
formed, then it may be more difficult to successfully complete 
subsequently performed processing steps used to form the contact on the 
gate contact opening. Therefore, it is desirable to fabricate DRAMs with a 
process that is more tolerant of misalignments between the nitride and 
gate etches. 
Additionally, the topography of the DRAM is no longer flat after the 
nitride etch has been performed with the method of the Nguyen Patent. As a 
result, the lithography step used to define the gate stacks with the 
process of the Nguyen Patent must be performed with equipment having a 
relatively large field of depth, which may be more costly. Therefore, 
there is a need for a DRAM process that is tolerant of misalignments, and 
does not require lithography equipment with a relatively large field of 
depth. 
SUMMARY OF THE INVENTION 
In accordance with the present invention, there is provided a method for 
fabricating a contact on an integrated circuit, such as a DRAM. The method 
includes the following steps. A gate stack is formed on the integrated 
circuit. Spacers are formed on sidewalls of the gate stack. An insulating 
film is formed on the integrated circuit. The insulating film is 
planarized. Finally, a gate contact opening is formed through the 
planarized insulating film. 
In one embodiment, the gate contact opening is formed by removing the 
insulator, spacer and insulating film by etching. In this embodiment, the 
insulator, spacer and insulating film are etched at substantially similar 
rates. As a result, the integrated circuit is tolerant of mask 
misalignments, and is not susceptible to over-etched field oxide or 
silicon nitride slivers. 
In another embodiment, the planarizing step is performed with chemical 
mechanical planarization to form a substantially flat topography on the 
surface of the integrated circuit. Thus, the present invention does not 
require lithography equipment with a relatively large field of depth. 
In yet a third embodiment, the method may comprise additional steps, 
including forming additional dielectric on the integrated circuit. Then, 
gate and bitline contact openings are formed through the additional 
dielectric. Finally, gate and bitline contacts are formed in 
self-alignment to the gate stacks. This embodiment may be implemented by 
forming the gate and bitline contact openings with an etch that removes 
the additional dielectric, but does not substantially remove the spacer. 
As a result, the bitline contact is not inadvertently connected to a gate 
stack that functions as a wordline. This connection might disable the 
integrated circuit. 
Because it is more tolerant of misalignment, the present invention enhances 
the yield of current DRAM designs. Also, the present invention permits 
higher device density in future DRAM designs. Further features and 
advantages of the present invention, as well as the structure and 
operation of various embodiments of the present invention, are described 
in detail below with reference to the accompanying drawings.

DETAILED DESCRIPTION OF THE EMBODIMENT 
In the following detailed description of the preferred embodiments, 
reference is made to the accompanying drawings which form a part hereof, 
and in which is shown by way of illustration specific preferred 
embodiments in which the invention may be practiced. These embodiments are 
described in sufficient detail to enable those skilled in the art to 
practice the invention, and it is to be understood that other embodiments 
may be utilized and that logical, mechanical and electrical changes may be 
made without departing from the spirit and scope of the present invention. 
The following detailed description is, therefore, not to be taken in a 
limiting sense, and the scope of the present invention is defined only by 
the appended claims. 
The present invention is directed toward facilitating a method for 
fabricating an integrated circuit, such as a DRAM. In the subsequently 
described embodiment, the present invention will be shown to form a DRAM. 
The initial formation of the DRAM 150 is shown in FIG. 1. The DRAM is 
subsequently manufactured in accordance with the process steps in FIG. 2. 
The DRAM 150 is first fabricated by forming n and p wells in a base layer 
103 (step 252), such as a silicon. Subsequently active and field 
dielectric 102 areas are formed (step 254). Then gate dielectric 104 is 
formed on the base layer 103 (step 256). The gate dielectric 104 may be 
oxide or oxynitride. The oxide may be grown or deposited by conventional 
techniques. The field dielectric 102 may be an oxide, such as 
conventionally used field oxide. 
Next, a conductor 107 is formed on the DRAM 150 (step 258). The conductor 
107 may comprise one or more conductive layers, such as polysilicon 106 
and tungsten silicide 108. The polysilicon 106 may be deposited and then 
doped, or deposited doped insitu. The tungsten silicide 108 may be formed 
by deposition or sputtering. Specific methods of forming the polysilicon 
106 and tungsten silicide 108 are know to persons skilled in the art. 
Next, an insulator 110 is deposited on the conductor 107 (step 260). The 
insulator 110 may be a nitride, an oxide or a combination thereof. In the 
exemplary embodiment, the insulator 110 is silicon nitride. 
Subsequently, gate stacks are formed by patterning and removing material 
from the DRAM 150 (step 262), as shown in FIG. 3. The gate stacks may be 
wordlines 310 and gates 312. Removal is performed with a gate etch. 
Methods of patterning and removal to form gate stacks are known to persons 
skilled in the art. 
Next, the active areas are doped by a conventional implant, otherwise known 
as a lightly doped drain (LDD) implant (step 264). During the LDD implant 
(step 264), n- and p-type dopants are implanted in self-alignment to the 
gate stacks into uncovered active regions of the corresponding n and p 
wells of the DRAM 150. 
After the LDD implant (step 264), a spacer 402 is formed on the sides of 
the wordlines 210 and gates 212 (step 266), as shown in FIG. 4. The spacer 
402 can be comprised of one or more spacer insulators 411, 412. The spacer 
insulators 411, 412 may be oxides, nitrides or a combination thereof. For 
example, the spacer 402 may be comprised of a first spacer insulator 411 
that is an oxide grown on the sidewalls of the conductor. Subsequently, 
the second spacer insulator 412, an oxide or nitride, is formed on first 
spacer insulator 411, the insulator 110, the field oxide 104, and the base 
layer 103. Alternatively, only the second spacer insulator 412 may be 
formed on the DRAM 150. In this case, the second spacer insulator 412 may 
be a nitride film that is deposited and then etched back. 
Subsequently, an insulating film 520 is formed on the DRAM 150 (step 268), 
as shown in FIG. 5. The insulating film may be formed by depositing 
tetraethyloxysilicate (TEOS) 522 and borophosphosilicate glass (BPSG) 524 
in succession on the DRAM 150. The TEOS 522 is undoped. The BPSG 524 is 
doped. The TEOS 522 and BPSG 524 have respective thicknesses of between 
100 angstroms and 500 angstroms, and 1000 angstroms and 3000 angstroms. 
Deposition of the insulating film 520 is performed in a manner known to 
persons skilled in the art. 
Next, the BPSG 524 is planarized (step 270) to about the height of the gate 
stacks with chemical mechanical planarization (CMP). Because BPSG 524 can 
be easily planarized and CMP is selective to nitride, a substantially flat 
topology is readily formed on the DRAM 150 surface. Conventionally, the 
TEOS 522 and BPSG 544 are used to form capacitors in the DRAM 150. 
However, the present invention also utilizes the insulating film 520 to 
provide the flat topology on the DRAM 150. The flat topology permits 
patterning the gate contact opening with lithography equipment having a 
reduced field of depth. 
After planarization (step 270), a gate contact opening 602 is formed by 
patterning and removing some insulating film 520, insulator 110, and 
spacer 402 (step 272), as shown in FIG. 6. The gate contact opening 602 
exposes the conductor 107. The patterning of the gate contact opening 602 
is defined with a mask. The removal is performed with a nitride etch, such 
as a dry etch, that removes the insulating film 520, insulator 110, and 
spacer 402 at about the same rate. 
If the position of the nitride etch is misaligned from the position of the 
gate etch in a direction away from the wordlines 210, additional 
insulating film 520 and some spacer 402 may also be removed. However, 
remaining insulating film 520 and the spacer 402 are sufficiently thick to 
prevent any field dielectric 102 from being removed. As a result, no 
undesirable short between the gate stack and the base layer 103 will 
occur. Thus, contact formation will not result in disabled transistors, 
and integrated circuit yield will increase. However, if the position of 
the nitride etch is misaligned from the position of the gate etch in a 
direction towards the wordlines 210, slivers of insulator 110 will not be 
formed because the insulator 110 is surrounded by the spacer 402 and 
insulating films. Thus, the completion of subsequent processing steps used 
to form the contact in the gate contact opening 602 will not be made more 
difficult. 
Subsequently, additional dielectric 760, is formed (step 274), by 
deposition for example, to create a capacitor container and an insulator 
between the contacts 750, 752 as shown in FIG. 7. Then, the gate contact 
opening 602, again, and a bitline contact opening are defined, or formed, 
by patterning and removing some additional dielectric 760 (step 276). The 
patterning is accomplished with another mask. To make this process step 
tolerant of mask misalignments, the removal is performed with an etch that 
will remove the additional dielectric 760, but substantially no spacer 
402. Thus, for example, an etch that is selective to nitride can be used 
to remove additional dielectric 760 which is not nitride, but no spacer 
402 which is nitride. As a result, bitline and gate contacts 750, 752 can 
be formed (step 278) in self-alignment to the bitline and gate contact 
openings. The bitline and gate contacts 750, 752 can be formed by 
conventional metallization techniques.