Test apparatus

A test apparatus including a first buffer section and a second buffer section that each buffers fail data and address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using an RMW process; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section.

BACKGROUND

1. Technical Field

The present invention relates to a test apparatus.

2. Related Art

A memory test apparatus includes a fail analysis memory section having therein an address fail memory (AFM) with the same address space as a memory under test. The memory test apparatus compares data read from the memory under test to an expected value, and writes fail data to the corresponding address of the AFM when the comparison result is a mismatch. The memory test apparatus performs a fail repair analysis for the memory under test, based on the fail data in the AFM.

The memory test apparatus performs the comparison between the data read from the memory under test and the expected value in units of cells (bits). In contrast, the AFM data is written and read in word units of 16 bits or 32 bits, for example.

Furthermore, there are cases in which the memory test apparatus tests the same cell a plurality of times. In this case, the memory test apparatus writes data indicating a fail to the AFM when this cell is judged to be defective. Even if this cell is judged to be non-defective in later testing, the memory test apparatus does not write data to the AFM indicating that the cell is non-defective, and therefore the information indicating that the cell is defective remains in the AFM.

The memory test apparatus writes fail data for a given cell (bit) at a given address of the memory under test to a bit corresponding to a corresponding address of the AFM, using a read-modify-write process. In this way, the memory test apparatus writes data in bit units to an AFM in which data is read and written word units. Therefore, once a fail judgment is recorded for a given bit, even if the memory test apparatus later judges that the corresponding cell is not defective during later testing, the memory test apparatus still stores a defective judgment for this bit.

However, the operation of writing data to a memory using a read-modify-write process requires an extremely long time. Therefore, when testing the memory under test at high speed, the writing of the fail data to the AFM is too slow.

To solve this problem, a memory test apparatus is known that includes a fail analysis memory section in which a plurality of AFMs are arranged in parallel corresponding to a single memory under test. This memory test apparatus sequentially selects one of the AFMs at a time in an interleaved manner and writes the fail data to the selected one AFM. This memory test apparatus can increase the speed at which the fail data is written from the perspective of the fail analysis memory section. Therefore, this memory test apparatus can prevent the writing of the fail data to the AFMs from being too slow.

However, with this memory test apparatus, a large number of AFMs must be mounted. Accordingly, with this memory test apparatus, the apparatus is large and the cost is high.

SUMMARY

To solve the above problems, according to a first aspect related to the innovations herein, provided is a test apparatus that tests a memory under test, comprising a testing section that outputs fail data indicating that a cell of the memory under test is defective and address data indicating an address of the cell; a first buffer section that buffers the fail data and the address data; a second buffer section that buffers the fail data and the address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using a read-modify-write process; a switching section that switches whether the fail data and address data output from the testing section or the fail data and address data buffered in the second buffer section are supplied to the first buffer section; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1shows a configuration of a test apparatus10according to an embodiment of the present invention, along with a memory under test200. The test apparatus10of the present invention detects defective cells by testing the memory under test200. Furthermore, the test apparatus10performs a repair analysis for making the memory under test200an acceptable article, by electrically replacing address lines including defective cells with spare lines.

The test apparatus10includes a testing section20and a fail analysis memory section22. The testing section20tests the memory under test200and outputs fail data indicating that a cell of the memory under test200is defective and address data indicating the address of the cell.

The testing section20includes a timing generator12, a pattern generator14, a waveform shaper16, and a logical comparator18. The timing generator12generates a reference clock and supplies the reference clock to the pattern generator14. The pattern generator14generates address data, a data signal, and a control signal to be supplied to the memory under test200, based on the reference clock, and supplies the address data, data signal, and control signal to the waveform shaper16. Furthermore, the pattern generator14generates expected value data that is compared to the output data of the memory under test200, and supplies the expected value data to the logical comparator18.

The waveform shaper16forms an application signal based on the address data, the data signal, and the control signal, and supplies the application signal to the memory under test200. The logical comparator18compares the expected value data to the output data output by the memory under test200, for each cell (bit) of the memory under test200. The logical comparator18outputs fail data when the output data does not match the expected value data. In the present embodiment, the fail data has a value of 1 when the output data does not match the expected value data, i.e. when there is a fail, and a value of 0 when the output data does match the expected value data, i.e. when there is a pass.

The fail analysis memory section22receives the address data and the fail data output from the testing section20. The fail analysis memory section22stores the fail data at an address corresponding to the address of the defective cell of the memory under test200. In this way, after testing of the memory under test200is completed, the fail analysis memory section22can store information indicating whether each cell of the memory under test200is a defective cell or an acceptable cell.

FIG. 2shows a configuration of the fail analysis memory section22according to the present embodiment. The fail analysis memory section22includes a fail formatter32, an address formatter34, a first buffer section40, an address fail memory section42, a second buffer section46, a switching section48, and a control section50.

The fail formatter32receives, in address units of the memory under test200, the fail data output from the logical comparator18of the testing section20. The fail formatter32converts the fail data in address units of the memory under test200into a bit format corresponding to words, which may be 16 bits or 32 bits, for example, of the address fail memory section42.

The fail formatter32supplies the second buffer section46and the first buffer section40with the fail data in word units that has the converted format. In the present embodiment, data that includes a value of 1, which is the value representing a fail, for at least one bit in the data output from the fail formatter32is referred to as fail data.

The fail formatter32supplies the control section50with a FLEX signal, in addition to outputting the fail data. In the present embodiment, the fail formatter32outputs the FLEX signal with a value of 1 in a case where not all of the bits in the output data have a value of 0, i.e. when the output data is fail data, and outputs the FLEX signal with a value of 0 when data differing from the above data is output.

The address formatter34receives the address data output from the pattern generator14of the testing section20. The address formatter34converts the received address data into a data format indicating an address of the address fail memory section42. The address formatter34supplies the first buffer section40and the second buffer section46with the format-converted address data, in association with the fail data output from the address formatter34.

The first buffer section40receives either a set of fail data and address data output from the testing section20(the fail data and the address data output from the fail formatter32and the address formatter34in the present embodiment) or a set of the fail data and address data buffered in the second buffer section46. The first buffer section40buffers the received fail data and address data. The first buffer section40may be a FIFO (First In First Out) memory, for example.

The testing section20can change the period of the test cycle during testing. Furthermore, if the address fail memory section42downstream from the first buffer section40uses a clock-synchronized memory such as an SDRAM (Synchronous Dynamic Random Access Memory), the address fail memory section42must operate with a constant period. Therefore, since the period of the test cycle generated by the testing section20is not the same as the operating period of the address fail memory section42, the inclusion of the first buffer section40enables the difference between the period of the test cycle and the period of the operation clock of the address fail memory section42to be absorbed.

The address fail memory section42includes an internal memory60having an address space corresponding to the memory under test200. The internal memory60may be an SDRAM-type random access memory, such as a DDR (Double-Data-Rate)2 SDRAM or a DDR3 SDRAM.

The address fail memory section42receives the fail data buffered in the first buffer section40, and writes this fail data to the internal memory60. In this case, the address fail memory section42writes the received fail data to an address indicated by the address data corresponding to the fail data in the internal memory60.

Furthermore, in this case, the address fail memory section42writes the received fail data to an address of the address data received by the internal memory60using a read-modify-write process. Specifically, the address fail memory section42reads one or more words of previously written data from the corresponding address of the internal memory60, calculates the logical sum of each bit of the fail data and corresponding bits of the read data, and writes the one or more words of data resulting from the logical sum calculation back to the corresponding address of the internal memory60.

Prior to testing, the internal memory60is initialized to have a value of 0 for every piece of stored data. Accordingly, when testing is completed for all of the addresses of the memory under test200and writing of all fail data and address data buffered in the second buffer section46to the internal memory60is completed, the internal memory60can store data indicating which cells at which addresses of the memory under test200are defective.

The second buffer section46receives the fail data and address data output by the testing section20(the fail data and address data output by the fail formatter32and the address formatter34in the present embodiment). The second buffer section46buffers the received fail data and address data. The fail data and address data buffered by the second buffer section46are transmitted to the first buffer section40under the control of the control section50.

The second buffer section46includes an upstream memory section62and a downstream memory section64. If the downstream memory section64uses a clock-synchronized memory such as an SDRAM therein, the upstream memory section62may be a FIFO memory that buffers the fail data and address data output from the testing section20. As a result, the upstream memory section62can absorb the difference between the period of the test cycle and the period of the operation clock of the downstream memory section64.

The downstream memory section64includes an intra-buffer memory66, which is a random access memory. The intra-buffer memory66may be an SDRAM-type random access memory such as a DDR2 SDRAM or a DDR3 SDRAM.

The downstream memory section64sequentially inputs the buffered fail data and the address data into the upstream memory section62, and writes this information to the intra-buffer memory66using a burst write process. In other words, the downstream memory section64sequentially inputs the buffered fail data and the address data into the upstream memory section62and writes this information to the intra-buffer memory66without using the read-modify-write process.

The downstream memory section64does not write the data to the intra-buffer memory66using a read-modify-write process, and therefore the data can be written to the intra-buffer memory66in a shorter time than needed to write the data to the internal memory60in the address fail memory section42. The fail data and address data written to the intra-buffer memory66are supplied to the first buffer section40via the switching section48, under the control of the control section50.

Under the control of the control section50, the switching section48switches between supplying the first buffer section40with the fail data and address data output by the testing section20, i.e. the fail data and address data output by the fail formatter32and the address formatter34, and supplying the first buffer section40with the fail data and address data buffered in the second buffer section46. The switching section48may be a multiplexer, for example.

The control section50controls operation of the first buffer section40, the address fail memory section42, the second buffer section46, and the switching section48.

More specifically, the control section50supplies the first buffer section40with a first write command (FAWT) and a first write address (FAWA). Upon receiving the first write command (FAWT) from the control section50, the first buffer section40stores the fail data and address data received via the switching section48at the address indicated by the first write address (FAWA).

The control section50supplies the first buffer section40with a first read command (FARD) and a first read address (FARA). Upon receiving the first read command (FARD) from the control section50, the first buffer section40outputs the fail data and address data stored at the first read address (FARA). In this case, the address fail memory section42acquires the fail data and address data output from the first buffer section40and writes the acquired fail data to the address in the internal memory60indicated by the acquired address data, using a read-modify-write process.

As an example, the control section50may calculate the amount of effective fail data, which is the fail data and address data that is buffered by the first buffer section40but has yet to be written to the address fail memory section42, by subtracting the value of the first read address (FARA) from the value of the first write address (FAWA). Furthermore, the control section50calculates the remaining capacity of the first buffer section40by subtracting the amount of effective fail data buffered by the first buffer section40from the total capacity of the first buffer section40.

The control section50supplies the upstream memory section62of the second buffer section46with a second write command (FSWT) and a second write address (FSWA). Upon receiving the second write command (FSWT) from the control section50, the upstream memory section62of the second buffer section46stores the received fail data and address data at the address indicated by the second write address (FSWA).

The control section50supplies the upstream memory section62of the second buffer section46with a second read command (FSRD) and a second read address (FSRA). Upon receiving the second read command (FSRD) from the control section50, the upstream memory section62of the second buffer section46outputs the fail data and address data stored at the second read address (FSRA). When outputting the fail data and address data from the second buffer section46, in order to perform the burst write process in the downstream memory section64, the control section50causes a designated number of pieces of fail data and address data to be output in series.

The control section50supplies the downstream memory section64of the second buffer section46with a third write command (SDWT) and address (SDAD) or a third read command (SDRD) and address (SDAD). In response to receiving the third write command (SDWT) and the address (SDAD) from the control section50, the downstream memory section64writes the designated number of pieces of fail data and address data sequentially output in series by the upstream memory section62to a designated range from the address of the intra-buffer memory66indicated by the address (SDAD), using a burst write process.

In response to receiving the third read command (SDRD) and the address (SDAD) from the control section50, the downstream memory section64reads the fail data and address data in a designated range from the address of the intra-buffer memory66indicated by the address (SDAD), using a burst read process, and outputs the read data in synchronization with the operation clock of the testing section20. The fail data and address data output from the downstream memory section64are supplied to the first buffer section40via the switching section48.

As an example, the control section50may generate the address to be supplied to the downstream memory section64when writing data to the intra-buffer memory66using an internal write address counter. As another example, the control section50may generate the address to be supplied to the downstream memory section64when reading data from the intra-buffer memory66using an internal read address counter.

The control section50switches between outputting the read address counter value and outputting the write address counter value as the address (SDAD), according to the content of the command supplied to the downstream memory section64. The control section50manages the region to be written to or read from in the intra-buffer memory66, based on the read address counter value and the write address counter value.

The control section50also manages the unused region of the downstream memory section64. When the downstream memory section64of the second buffer section46overflows, the control section50sets an overflow flag in an internal register. After testing is finished, the computer controlling the test apparatus10, for example, can know whether an overflow occurred by reading the value in this register.

The control section50supplies a switch command (DSEL) to the switching section48. When the switch command (DSEL) supplied from the control section50has a value of 0, for example, the switching section48supplies the first buffer section40with the fail data and address data output from the testing section20, which is the fail data and address data from the fail formatter32and the address formatter34in the present embodiment. When the switch command (DSEL) supplied from the control section50has a value of 1, for example, the switching section48supplies the first buffer section40with the fail data and address data output from the internal memory60of the second buffer section46.

The control section50sets the fail analysis memory section22to be in one of a first state, a second state, and a third state. The control section50then switches the transmission path of the fail data and address data according to the set state.

FIG. 3shows the flow of data in the first state of the fail analysis memory section22according to the present embodiment. In the first state, the control section50sets the switch command (DSEL) to have a value of 0. As a result, the switching section48can supply the first buffer section40with the fail data and address data output from the testing section20, i.e. the fail data and address data output from the fail formatter32and the address formatter34.

In the first state, each time a FLEX signal is supplied from the fail formatter32, the control section50supplies the first buffer section40with a first write address (FAWA) and a first write command (FAWT). The control section50increments the first write address (FAWA) by 1 after data is written to the first buffer section40. As a result, in the first state, the first buffer section40can sequentially store the pieces of fail data and address data output sequentially from the testing section20, while incrementing the address by 1 for each piece of data. In this way, while in the first state, the fail analysis memory section22can supply the first buffer section40with the fail data and the address data output from the testing section20.

Furthermore, in the first state, on a condition that fail data and address data not yet sent to the address fail memory section42is stored in the first buffer section40, the control section50supplies the first buffer section40with a first read address (FARA) and a first read command (FARD) each time the address fail memory section42is capable of writing. After the address fail memory section42receives data from the first buffer section40, the control section50increments the first read address (FARA) by 1. As a result, the first buffer section40can sequentially output the stored fail data and address data while incrementing the address by 1 for each piece of data.

In response to fail data and address data being output from the first buffer section40, the address fail memory section42acquires the output fail data and address data. The address fail memory section42writes the acquired fail data to the address in the internal memory60indicated by the acquired address data, using a read-modify-write process. In this way, in the first state, the fail analysis memory section22can output the fail data and address data form the first buffer section40and store the fail data in the address fail memory section42.

FIG. 4shows the flow of data in the second state of the fail analysis memory section22according to the present embodiment. In the second state, each time a FLEX signal is supplied from the fail formatter32, the control section50supplies the upstream memory section62of the second buffer section46with a second write address (FSWA) and a second write command (FSWT). After data is written to the upstream memory section62, the control section50increments the second write address (FSWA) by 1. As a result, in the second state, the upstream memory section62of the second buffer section46can sequentially store the fail data and address data output sequentially from the testing section20, while incrementing the address by 1 for each piece of data.

In the second state, the control section50supplies the upstream memory section62of the second buffer section46with a second read address (FSRA) and a second read command (FSRD) each time the downstream memory section64is capable of writing. When a second read address (FSRA) and a second read command (FSRD) are supplied, the upstream memory section62outputs the fail data and address data stored at the second read address (FSRA). The control section50then increments the second read address (FSRA) by 1. In this way, the upstream memory section62of the second buffer section46can sequentially output the stored fail data and address data in series, while incrementing the address by 1 for each piece of data.

Furthermore, in the second state, on a condition that the amount of fail data and address data stored in the upstream memory section62of the second buffer section46is greater than or equal to a predetermined amount, the control section50supplies the downstream memory section64with a third write command (SDWT) indicating a burst write process and an address (SDAD) indicating a start address for the burst write process. Upon receiving the third write command (SDWT) and the address (SDAD), the downstream memory section64sequentially writes fail data and address data output from the upstream memory section62of the second buffer section46over the data in a designated range from the start address in the intra-buffer memory66indicated by the address (SDAD). In this way, the downstream memory section64can write the fail data and address data buffered in the upstream memory section62to the intra-buffer memory66using a burst write process.

In this way, in the second state, the fail analysis memory section22can write the fail data and address data output from the testing section20to the second buffer section46.

Furthermore, in the second state, the control section50supplies the first buffer section40with a first read address (FARA) and a first read command (FARD), in the same manner as in the first state. The address fail memory section42also performs processing in the same manner as in the first state. Therefore, in the second state, the fail analysis memory section22can output the fail data and address data from the first buffer section40and can store the fail data in the address fail memory section42.

FIG. 5shows the flow of data in the third state of the fail analysis memory section22according to the present embodiment. In the third state, the control section50sets the switch command (DSEL) to have a value of 1. As a result, the switching section48can supply the first buffer section40with the fail data and address data output from the downstream memory section64of the second buffer section46.

In the third state, on a condition that the amount of fail data and address data stored in the downstream memory section64of the second buffer section46is greater than or equal to a predetermined amount, the control section50supplies the downstream memory section64with a third read command (SDRD) indicating a burst read process and an address (SDAD) indicating a start address for the burst write process. Upon receiving the third read command (SDRD) and the address (SDAD), the downstream memory section64sequentially reads the fail data and address data in series in a designated range from the start address in the intra-buffer memory66indicated by the address (SDAD). In this way, the downstream memory section64can read the fail data and address data stored in the intra-buffer memory66using a burst read process.

In the third state, the control section50supplies the first buffer section40with a first write address (FAWA) and a first write command (FAWT) each time the fail data and address data for one address is output from the downstream memory section64. The control section50increments the first write address (FAWA) after data is written to the first buffer section40. In this way, in the third state, the first buffer section40can sequentially store the fail data and address data output sequentially and in series from the downstream memory section64, while incrementing the address by one for each piece of data, using a burst read process.

In the third state, each time a FLEX signal is supplied from the fail formatter32, the control section50supplies the upstream memory section62of the second buffer section46with a second write address (FSWA) and a second write command (FSWT). After data is written to the upstream memory section62, the control section50increments the second write address (FSWA) by 1. As a result, in the third state, the upstream memory section62of the second buffer section46can sequentially store the fail data and address data output sequentially from the testing section20, while incrementing the address by 1 for each piece of data.

In this way, in the third state, the fail analysis memory section22can supply the first buffer section40with the fail data and address data buffered in the second buffer section46and can also write the fail data and address data output from the testing section20to the second buffer section46.

Furthermore, in the third state, the control section50supplies the first buffer section40with a first read address (FARA) and a first read command (FARD), in the same manner as in the first state. The address fail memory section42also performs processing in the same manner as in the first state. Therefore, in the third state, the fail analysis memory section22can output the fail data and address data from the first buffer section40and can store the fail data in the address fail memory section42.

Furthermore, in the third state, the control section50continuously outputs data from the upstream memory section62and continuously writes data using a burst write process performed by the downstream memory section64, in the same manner as in the second state. Before the testing is finished, the control section50gives more priority to executing the process of transmitting data from the upstream memory section62to the downstream memory section64than to executing the process for transmitting the data from the downstream memory section64to the first buffer section40. As a result, the control section50can prevent the upstream memory section62from overflowing.

After testing is completed, the control section50gives more priority to executing the process of transmitting data from the downstream memory section64to the first buffer section40than to executing the process for transmitting the data from the upstream memory section62to the downstream memory section64. As a result, the control section50can decrease the time needed to write all of the pieces of fail data to the address fail memory section42.

FIG. 6shows transition conditions for the state of the fail analysis memory section22according to the present embodiment. Before testing is begun, the control section50clears the address fail memory section42by writing a value of 0 for every address. Furthermore, before testing is begun, the control section50sets the first write address (FAWA), the first read address (FARA), the second write address (FSWA), and the second read address (FSRA) to an initial value, e.g. a value of 0.

Next, when the testing section20begins testing, the control section50transitions the fail analysis memory section22to the first state (S10). Specifically, when the testing begins, the control section50supplies the first buffer section40with the fail data and address data output from the testing section20. As a result, the control section50can buffer the fail data and address data output from the testing section20in the first buffer section40.

In the first state, if the writing rate at which the address fail memory section42writes the fail data is lower than the data rate of the fail data and address data output from the testing section20, the unused capacity of the first buffer section40gradually decreases. Accordingly, if this state continues, the first buffer section40will overflow.

Therefore, during the state in which the control section50causes the fail data and address data output from the testing section20to be written to the first buffer section40, i.e. during the first state, when the unused capacity of the first buffer section40becomes less than or equal to a predetermined first threshold value (A1), the control section50transitions the fail analysis memory section22to the second state (S11). In other words, in the first state, when the unused capacity of the first buffer section40becomes less than or equal to a predetermined first threshold value (A1), the control section50causes the fail data and address data output from the testing section20to be written to the second buffer section46instead of to the first buffer section40.

At the same time, the control section50stops the writing of the fail data and address data output from the testing section20to the first buffer section40. Accordingly, the fail analysis memory section22can prevent overflow of the first buffer section40by transitioning from the first state to the second state.

In the present embodiment, the second buffer section46includes the upstream memory section62and the downstream memory section64. The fail data and address data output from the testing section20is first buffered in the upstream memory section62, and then transmitted to the intra-buffer memory66in the downstream memory section64. The downstream memory section64writes the data buffered in the upstream memory section62to the intra-buffer memory66using a burst write process, and does not use a read-modify-write process. Accordingly, the process of writing the data buffered in the upstream memory section62to the downstream memory section64is performed faster than the process for writing the data buffered in the first buffer section40to the address fail memory section42.

The second buffer section46is designed and controlled to prevent overflow of the intra-buffer memory66in the downstream memory section64and the upstream memory section62. The upstream memory section62is a FIFO memory, in the same manner as the first buffer section40, and therefore prevents overflow by reading the fail data and address data with a speed greater than the speed at which the fail data and address data is written, which is at most the period of the test cycle, and performing the burst write process to the intra-buffer memory66as described above. Furthermore, the intra-buffer memory66can decrease the chances of an overflow by using a high capacity memory such as an SDRAM. Furthermore, if the third state can be transitioned to during testing, the control section50can transmit the fail data and address data from the intra-buffer memory66to the first buffer section40. In this case, the control section50can write the resulting new fail data and address data to the intra-buffer memory66, and can therefore decrease the chances of the intra-buffer memory66overflowing.

Next, in a state where the fail data and address data is written from the testing section20to the second buffer section46, i.e. the second state, when the unused capacity of the first buffer section40becomes greater than a second threshold value (A2) that is greater than or equal to the first threshold value (A1), the control section50transitions the fail analysis memory section22to the first state (S12). In other words, in the second state, when the remaining capacity of the first buffer section40becomes greater than the second threshold value (A2), the control section50causes the fail data and address data output from the testing section20to be written to the first buffer section40instead of to the second buffer section46.

In this way, the control section50can return to a state in which the fail data and address data from the testing section20are buffered in the first buffer section40. After testing is completed, if effective fail data that has not yet been written to the address fail memory section42remains in the intra-buffer memory66of the second buffer section46, it is necessary to transition to the third state to transmit this fail data to the first buffer section40and write this fail data in the address fail memory section42. Therefore, when there is a large amount of unused capacity in the first buffer section40, the control section50can decrease the number of pieces of effective fail data in the second buffer section46after testing by transitioning from the second state to the first state and writing the fail data to the first buffer section40.

Next, in the first state, when the data rate of the fail data and address data output from the testing section20is less than the rate at which the fail data is written in the address fail memory section42, the amount of remaining effective fail data stored in the first buffer section40gradually decreases. Accordingly, when this state continues, the effective fail data is removed from the first buffer section40, and the writing of the fail data to the address fail memory section42stops. However, when there is effective fail data in the intra-buffer memory66before all of the effective fail data is removed from the first buffer section40, before transitioning to the third state and stopping, the effective fail data can be written to the address fail memory section42without stopping by reading the effective fail data from the intra-buffer memory66and writing this fail data to the first buffer section40.

Therefore, the control section50transitions the fail analysis memory section22from the state in which the fail data and address data output from the testing section20are written to the first buffer section40, i.e. the first state, to the third state (S13). The conditions for transitioning from the first state to the third state are that, while in the first state, the intra-buffer memory66contains effective fail data and the amount of effective fail data in the first buffer section40is less than a preset third threshold value (B1). When the third state is transitioned to, the control section50supplies the first buffer section40with the effective fail data buffered in the second buffer section46and writes the fail data and address data output from the testing section20to the second buffer section46.

As a result, the control section50can cause the effective fail data that has yet to be written to the address fail memory section42from the second buffer section46to be output and buffered in the first buffer section40. Accordingly, as a result of transitioning from the first state to the third state, the fail analysis memory section22stops the writing of fail data to the address fail memory section42, and can therefore avoid the increased time needed to finish the writing of fail data to the address fail memory section42.

The control section50transitions the fail analysis memory section22from a state in which the fail data and address data buffered in the second buffer section46are supplied to the first buffer section40, i.e. the third state, to a the first state (S14). The conditions for transitioning from the third state to the first state is that, while in the third state, there is no effective fail data in the intra-buffer memory66or that the amount of effective fail data in the first buffer section40is greater than a preset fourth threshold value (B2), which is greater than the third threshold value (B1). When the first state is transitioned to, the control section50stops the supply of the effective fail data buffered in the second buffer section46to the first buffer section40, and writes the fail data and address data output from the testing section20to the first buffer section40.

In this way, the control section50can return to a state in which the fail data and address data output from the testing section20are buffered in the first buffer section40, and can decrease the amount of fail data and address data buffered in the second buffer section46. Therefore, the control section50can shorten the process of transmitting the effective fail data in the second buffer section46to the first buffer section40after testing is finished.

After testing is finished and the output of fail data and address data from the testing section20is finished, if effective fail data remains in the second buffer section46, the control section50transitions the fail analysis memory section22to the third state. In this way, the control section50can supply the first buffer section40with the effective fail data buffered in the second buffer section46after testing.

In the manner described above, after testing is finished, the fail analysis memory section22can transmit all of the effective fail data buffered in the second buffer section46to the first buffer section40. As a result, the fail analysis memory section22can store all of the fail data output from the testing section20in the address fail memory section42.

In the manner described above, with the test apparatus10of the present embodiment, even when testing the memory under test200at high speed, the fail data can be written to the address fail memory section42as long as an overflow does not occur due to insufficient capacity in the intra-buffer memory66. With the test apparatus10, speed can be increased without providing a plurality of address fail memory sections42and performing an interleaved operation, and therefore the fail analysis memory section22can be made smaller and less expensive.

FIG. 7shows a configuration of the second buffer section46according to a first modification of the present embodiment. The second buffer section46shown inFIG. 7is a modification of the second buffer section46described in reference toFIGS. 1 to 6, and therefore components having the same function and configuration are given the same reference numerals and the following description includes only differing points.

The second buffer section46of the present modification includes the upstream memory section62, a compressing section72, the downstream memory section64, and an expanding section74. The compressing section72compresses the data (fail data and address data) to be written to the downstream memory section64, using a preset compression algorithm.

For example, the compressing section72may be provided between the upstream memory section62and the downstream memory section64to compress the data output from the upstream memory section62. Instead, the compressing section72may be provided upstream from the upstream memory section62to compress the data to be input to the upstream memory section62.

The expanding section74expands the data read from the downstream memory section64using an expansion algorithm corresponding to the compression algorithm. In this way, the second buffer section46of the present modification can increase the amount of data (fail data and address data) that can be stored in the downstream memory section64. Furthermore, increasing the amount of data that can be stored in the downstream memory section64also increases the amount of fail data written by the burst write operation per unit time.

FIG. 8shows a configuration of the fail analysis memory section22according to a second modification of the present embodiment. The fail analysis memory section22according to the present modification shown inFIG. 8adopts substantially the same function and configuration as the fail analysis memory section22described in relation toFIGS. 1 to 7, and therefore components of this fail analysis memory section22that have the same function and configuration as components of the fail analysis memory section22of the present embodiment are given the same reference numerals and the following description includes only differing points.

The fail analysis memory section22of the present modification includes a fail formatter32, an address formatter34, a plurality of processing blocks80, and a block selecting section82.

The fail formatter32supplies fail data with a converted format to each of the processing blocks80. The address formatter34supplies address data with a converted format to each of the processing blocks80. The address formatter34also outputs addresses for selecting among the plurality of processing blocks80. The block selecting section82decodes the address selected by the address formatter34to select one block among the plurality of processing blocks80to which fail data is to be written.

The processing blocks80correspond respectively to partial regions obtained by dividing the address space of the memory under test200. For example, if the address space of the memory under test200is divided in half, the fail analysis memory section22includes two processing blocks80. When the address space of the memory under test200is divided in to N regions, where N is an integer greater than or equal to 2, the fail analysis memory section22includes N processing blocks80-1to80-N.

The processing blocks80may each correspond to values of a predetermined number of bits (e.g. 1 bit, 2 bits, etc.) from the least significant bit in each address of the memory under test200. For example, the processing blocks80may each correspond to the value of the least significant bit of each address of the memory under test200(in other words, each processing block80may correspond to even-numbered addresses or odd-numbered addresses). In this case, N=2, and therefore the fail analysis memory section22includes two processing blocks80. Furthermore, when the processing blocks80each correspond to the value of two bits from the least significant bit of each address, N=4, and therefore the fail analysis memory section22includes four processing blocks80.

Each time fail data is output from the testing section20, e.g. each time a FLEX signal is output from the fail formatter32, the block selecting section82decodes the processing block selection address output from the address formatter34when the fail data is output from the testing section20, and selects the processing block80for which the fail data write process is to be performed. In this way, the block selecting section82can select one processing block80, from among the plurality of processing blocks80, corresponding to the partial region that includes the cell that is indicated to be defective by the fail data output from the testing section20.

Each processing block80includes a first buffer section40, an address fail memory section42, a second buffer section46, a switching section48, and a control section50. The internal memory60in the address fail memory section42of each processing block80includes an address space corresponding to the partial region corresponding to the processing block80.

Each processing block80receives the fail data and address data output from the testing section20, in response to the processing block80being selected. More specifically, the control section50of each processing block80causes the fail data and address data output from the fail formatter32and the address formatter34to be buffered in the first buffer section40or the second buffer section46, in response to the processing block80being selected.

Each processing block80performs the same process as the fail analysis memory section22described inFIGS. 1 to 7, for the received fail data and address data. As a result, each processing block80can store data indicating whether each cell at each address in the corresponding partial region of the memory under test200is defective.

The fail analysis memory section22according to the present modification selects one processing block80among the plurality of processing blocks80and stores fail data in the address fail memory section42of the one selected processing block80. Accordingly, when the testing section20outputs data (fail data and address data) at high speed, the fail analysis memory section22of the present modification can decrease the average rate of the data input to each processing block80. Furthermore, with the fail analysis memory section22of the present modification, the address fail memory section42in each processing block80can perform the data writing process in parallel. Therefore, the fail analysis memory section22of the present modification can increase the rate of acquiring data directly with the first buffer section40without passing through the second buffer section46, and can therefore lower the chances of the intra-buffer memory66overflowing.

Furthermore, in a conventional test apparatus that includes an interleaving fail analysis memory section, the fail data sequentially output from the logical comparator is divided according to time, and is therefore scattered and stored among a plurality of AFMs. Accordingly, with such a test apparatus, each AFM must have a capacity equivalent to that of the memory under test. In other words, when the test apparatus includes N AFMs that perform interleaved operation, memory with a capacity N times that of the memory under test must be provided.

In contrast, with the fail analysis memory section22of the present modification, although there is a chance that an overflow could occur depending on the capacity of the intra-buffer memories66in the processing blocks80, the occurrence of an overflow would indicate that the memory under test has a large number of defective cells and would still be a defective article even if a repair analysis were performed, and therefore this overflow is not actually a problem. Furthermore, with the fail analysis memory section22of the present modification, each processing block80is configured to decrease the chances of an overflow therein, and address fail memory sections42can be provided with capacities corresponding to the partial regions of the memory under test200. In other words, the total capacity of the internal memories60in the address fail memory sections42of the processing blocks80is the same as the capacity of the memory under test200. Accordingly, the fail analysis memory section22of the present modification can use a lower total memory capacity for the address fail memory and therefore achieve a lower cost, compared to a conventional test apparatus that includes a fail analysis memory section using an interleaving operation.

Yet further, with the fail analysis memory section22of the present modification, each address fail memory section42writes the fail data in parallel using a read-modify-write process. Accordingly, the fail analysis memory section22of the present modification can increase the amount of fail data writing to the address fail memory sections42that can be completed during testing of the memory under test200. Therefore, the fail analysis memory section22of the present modification can decrease the amount of data remaining in the second buffer sections46when testing by the testing section20is finished, thereby decreasing the time needed to finish writing of the fail data after testing is completed.