Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2011-195018, filed Sep. 7, 2011, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

A NAND flash memory in which memory cells are three-dimensionally arranged is known.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor memory device includes: a memory cells; a selection transistor; a memory string; a block; a word line; a select gate line; a bit line; and a transfer circuit. The memory cells are stacked on a semiconductor substrate, and include a charge accumulation layer and control gate. In the memory string, the current paths of the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. The word line is coupled to the control gate of the memory cell. The select gate line is coupled to the gate of the selection transistor. The bit line is coupled to one of the memory cells via the current path of the selection transistor. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block.

First Embodiment

A semiconductor memory device according to the first embodiment will be explained below. This semiconductor memory device will be explained by taking, as an example, a three-dimensionally stacked NAND flash memory in which memory cells are stacked above a semiconductor substrate.

1. Arrangement of Semiconductor Memory Device

First, the arrangement of the semiconductor memory device according to this embodiment will be explained.

1.1 Overall Arrangement of Semiconductor Memory Device

FIG. 1is a block diagram of the semiconductor memory device according to this embodiment. As shown inFIG. 1, a NAND flash memory1includes a memory cell array10, row decoders11(11-0to11-3), a driver circuit12, a sense amplifier13, a voltage generator14, and a control circuit15.

The memory cell array10includes a plurality of (in this embodiment, four) blocks BLK (BLK0to BLK3) each of which is a set of nonvolatile memory cells. Data in the same block BLK is erased at once. Each block BLK includes a plurality of (in this embodiment, four) memory groups GP (GP0to GP3) each of which is a set of NAND strings16in which memory cells are connected in series. The number of blocks in the memory cell array10and the number of memory groups in the block BLK are, of course, arbitrary numbers.

The row decoders11-0,11-1,11-2, and11-3respectively associated with the blocks BLK0, BLK1, BLK2, and BLK3, and each select the row direction of an associated block BLK.

The driver circuit12applies voltages necessary for data write, read, and erase to the row decoders11. The row decoders11apply these voltages to memory cells.

In data read, the sense amplifier senses and amplifies data read out from a memory cell. In data write, the sense amplifier transfers write data to a memory cell.

The voltage generator14generates the voltages necessary for data write, read, and erase, and applies these voltages to the driver circuit12.

The control circuit15controls the operation of the whole NAND flash memory.

Details of the arrangement of the memory cell array10will be explained below.FIG. 2is a circuit diagram of the block BLK0. The blocks BLK1to BLK3also have the same arrangement.

As shown inFIG. 2, the block BLK0includes the four memory groups GP. Each memory group GP includes n (n is a natural number) NAND strings16.

Each NAND string16includes, e.g., eight memory cell transistors MT (MT0to MT7), selection transistors ST1and ST2, and a backgate transistor BT. The memory cell transistor MT includes a stacked gate including a control gate and charge accumulation layer, and holds data in a nonvolatile manner. Note that the number of memory cell transistors MT is not limited to eight and may also be, e.g., 16, 32, 64, or 128, i.e., the number is not limited. Similarly to the memory cell transistor MT, the backgate transistor BT includes a stacked gate including a control gate and charge accumulation layer. However, the backgate transistor BT does not hold data, and functions as a mere current path in data write and erase. The memory cell transistors MT and backgate transistor BT are arranged between the selection transistors ST1and ST2such that their current paths are connected in series. Note that the backgate transistor BT is formed between the memory cell transistors MT3and MT4. The current path of the memory cell transistor MT7at one end of this series connection is connected to one end of the current path of the selection transistor ST1. The current path of the memory cell transistor MT0at the other end of the series connection is connected to one end of the current path of the selection transistor ST2.

The gates of the selection transistors ST1of each of the memory groups GP0to GP3are connected together to an associated one of select gate lines SGD0to SGD3, and the gates of the selection transistors ST2of each of the memory groups GP0to GP3are connected together to an associated one of select gate lines SGS0to SGS3. On the other hand, the control gates of the memory cell transistors MT0to MT7in the same block BLK0are connected together to word lines WL0to WL7, respectively, and the control gates of the backgate transistors BT are connected together to a backgate line BG (BG0to BG3in the blocks BLK0to BLK3, respectively).

That is, the word lines WL0to WL7and backgate lines BG are connected together across the plurality of memory groups GP0to GP3in the same block BLK0, but the select gate lines SGD and SGS are independent for each of the memory groups GP0to GP3even in the same block BLK0.

Also, among the NAND strings16arranged in a matrix in the memory cell array10, the other-ends of the current paths of the selection transistors ST1of the NAND strings16in the same row are connected together to one of bit lines BL (BL0to BLn, n is a natural number). That is, the bit line BL connects the NAND strings16together across the plurality of blocks BLK. Furthermore, the other-ends of the current paths of the selection transistors ST2are connected together to a source line SL. The source line SL connects the NAND strings16together across, e.g., a plurality of blocks.

As described previously, data of the memory cell transistors MT in the same block BLK is erased at once. On the other hand, data read and write are performed for a plurality of memory cell transistors MT connected together to a given word line WL in a given memory group GP of a given block BLK. This unit is called a “page”.

Next, the three-dimensionally stacked structure of the memory cell array10will be explained below with reference toFIGS. 3 and 4.FIGS. 3 and 4are a perspective view and sectional view, respectively, of the memory cell array10.

As shown inFIGS. 3 and 4, the memory cell array10is formed above a semiconductor substrate20. The memory cell array10includes a backgate transistor layer L1, memory cell transistor layer L2, selection transistor layer L3, and interconnection layer L4sequentially formed above the semiconductor substrate20.

The backgate transistor layer L1functions as the backgate transistors BT. The memory cell transistor layer L2functions as the memory cell transistors MT0to MT7(NAND strings16). The selection transistor layer L3functions as the selection transistors ST1and ST2. The interconnection layer L4functions as the source line SL and bit lines BL.

The backgate transistor layer L1includes a backgate conductive layer21. The backgate conductive layer21is formed to two-dimensionally extend in the row and column directions parallel to the semiconductor substrate20. The backgate conductive layer21is separated for each block BLK. The backgate conductive layer21is made of, e.g., polysilicon. The backgate conductive layer21functions as the backgate lines BG.

As shown inFIG. 4, the backgate conductive layer21has a backgate hole22. The backgate hole22is made to scoop out the backgate conductive layer21. The backgate hole22is made into an almost rectangular shape having a longitudinal direction in the column direction when viewed from the upper surface.

The memory cell transistor layer L2is formed on the backgate conductive layer L1. The memory cell transistor layer L2includes word line conductive layers23ato23d. The word line conductive layers23ato23dare stacked with interlayer dielectric layers (not shown) being sandwiched between them. The word line conductive layers23ato23dare formed into strips extending in the row direction at a predetermined pitch in the column direction. The word line conductive layers23ato23dare made of, e.g., polysilicon. The word line conductive layer23afunctions as the control gates (word lines WL3and WL4) of the memory cell transistors MT3and MT4, the word line conductive layer23bfunctions as the control gates (word lines WL2and WL5) of the memory cell transistors MT2and MT5, the word line conductive layer23cfunctions as the control gates (word lines WL1and WL6) of the memory cell transistors MT1and MT6, and the word line conductive layer23dfunctions as the control gates (word lines WL0and WL7) of the memory cell transistors MT0and MT7.

As shown inFIG. 4, the memory cell transistor layer L2has memory holes24. The memory holes24are made to extend through the word line conductive layers23ato23d. The memory holes24are made to align with the end portion of the backgate hole22in the column direction.

As shown inFIG. 4, the backgate transistor layer L1and memory cell transistor layer L2further include a block insulating layer25a, charge accumulation layer25b, tunnel insulating layer25c, and semiconductor layer26. The semiconductor layer26functions as the body (the back gate of each transistor) of the NAND string16.

As shown inFIG. 4, the block insulating layer25ais formed with a predetermined thickness on sidewalls facing the backgate hole22and memory holes24. The charge accumulation layer25bis formed with a predetermined thickness on the side surfaces of the block insulating layer25a. The tunnel insulating layer25cis formed with a predetermined thickness on the side surfaces of the charge accumulation layer25b. The semiconductor layer26is formed in contact with the side surfaces of the tunnel insulating layer25c. The semiconductor layer26is formed to fill the backgate hole22and memory holes24.

The semiconductor layer26is formed into a U-shape when viewed in the row direction. That is, the semiconductor layer26includes a pair of pillar portions26aextending in a direction perpendicular to the surface of the semiconductor substrate20, and a connecting portion26bconnecting the lower ends of the pair of pillar portions26a.

The block insulating layer25aand tunnel insulating layer25care made of, e.g., silicon oxide (SiO2). The charge accumulation layer25bis made of, e.g., silicon nitride (SiN). The semiconductor layer26is made of polysilicon. The block insulating layer25a, charge accumulation layer25b, tunnel insulating layer25c, and semiconductor layer26form MONOS transistors that function as the memory cell transistors MT.

In the arrangement of the backgate transistor layer L1, the tunnel insulating layer25cis formed to surround the connecting portions26b. The backgate conductive layer21is formed to surround the connecting portions26b.

Also, in the arrangement of the memory cell transistor layer L2, the tunnel insulating layer25cis formed to surround the pillar portions26a. The charge accumulation layer25bis formed to surround the tunnel insulating layer25c. The block insulating layer25ais formed to surround the charge accumulation layer25b. The word line conductive layers23ato23dare formed to surround the block insulating layers25ato25cand pillar portions26a.

As shown inFIGS. 3 and 4, the selection transistor layer L3includes conductive layers27aand27b. The conductive layers27aand27bare formed into strips extending in the row direction so as to have a predetermined pitch in the column direction. A pair of conductive layers27aand a pair of conductive layers27bare alternately arranged in the column direction. The conductive layer27ais formed in an upper layer of one pillar portion26a, and the conductive layer27bis formed in an upper layer of the other pillar portion26a.

The conductive layers27aand27bare made of polysilicon. The conductive layer27afunctions as the gate (select gate line SGS) of the selection transistor ST2. The conductive layer27bfunctions as the gate (select gate line SGD) of the selection transistor ST1.

As shown inFIG. 4, the selection transistor layer L3has holes28aand28b. The holes28aand28brespectively extend through the conductive layers27aand27b. Also, the holes28aand28balign with the memory holes24.

As shown inFIG. 4, the selection transistor layer L3includes gate insulating layers29aand29b, and semiconductor layers30aand30b. The gate insulating layers29aand29bare respectively formed on sidewalls facing the holes28aand28b. The semiconductor layers30aand30bare formed into pillars extending in the direction perpendicular to the surface of the semiconductor substrate20, so as to come in contact with the gate insulating layers29aand29b, respectively.

In the arrangement of the selection transistor layer L3, the gate insulating layer29ais formed to surround the pillar semiconductor layer30a. The conductive layer27ais formed to surround the gate insulating layer29aand semiconductor layer30a. The gate insulating layer29bis formed to surround the pillar semiconductor layer30b. The conductive layer27bis formed to surround the gate insulating layer29band semiconductor layer30b.

As shown inFIGS. 3 and 4, the interconnection layer L4is formed on the selection transistor layer L3. The interconnection layer L4includes a source line layer31, plug layer32, and bit line layer33. The source line layer31is formed into a plate extending in the row direction. The source line layer31is formed in contact with the upper surfaces of the pair of semiconductor layers27aadjacent to each other in the column direction. The plug layer32is formed in contact with the upper surface of the semiconductor layer27b, so as to extend in the direction perpendicular to the surface of the semiconductor substrate20. The bit line layer33is formed into strips extending in the column direction at a predetermined pitch in the row direction. The bit line layer33is formed in contact with the upper surface of the plug layer32. The source line layer31, plug layer32, and bit line layer33are made of a metal such as tungsten (W). The source line layer31functions as the source line SL explained with reference toFIGS. 1 and 2, and the bit line layer33functions as the bit lines BL.

FIG. 5shows an equivalent circuit of the NAND string16shown inFIGS. 3 and 4. As shown inFIG. 5, the NAND string16includes the selection transistors ST1and ST2, memory cell transistors MT0to MT7, and backgate transistor BT. As described above, the memory cell transistors MT are connected in series between the selection transistors ST1and ST2. The backgate transistor BT is connected in series between the memory cell transistors MT3and MT4. In data write and read, the backgate transistor BT is kept ON.

The control gates of the memory cell transistors MT are connected to the word lines WL, and the control gate of the backgate transistor BT is connected to the backgate line BG. A set of the plurality of NAND strings16arranged along the row direction inFIG. 3is equivalent to the memory group GP explained with reference toFIG. 2.

The arrangement of the row decoders11will be explained below. The row decoders11-0to11-3are respectively associated with the blocks BLK0to BLK3, in order to select or unselect the blocks BLK0to BLK3.FIG. 6shows the arrangement of the row decoder11-0and driver circuit12. Note that the row decoders11-1to11-3also have the same arrangement as that of the row decoder11-0.

As shown inFIG. 6, the row decoder11includes a block decoder40, and high-withstand-voltage, n-channel enhancement type (E type: the threshold value is positive) MOS transistors50to54(50-0to50-7,51-0to51-3,52-0to52-3,53-0to53-3, and54-0to54-3) and55. All the transistors50to54are high-breakdown-voltage transistors, and equal in channel region impurity concentration and threshold voltage.

As shown inFIG. 6, the block decoder40includes an AND gate41, a low-withstand-voltage, n-channel depletion type MOS transistor42, high-withstand-voltage, n-channel depletion type (D type: the threshold voltage is negative) MOS transistors43and44, a high-breakdown-voltage, p-channel E type MOS transistor45, and a level shifter46.

The AND gate41performs an AND operation the bits of an externally supplied block address BA. If the block address BA indicates the block BLK0associated with the row decoder11-0, the AND gate41outputs “H” level.

The level shifter46shifts the level of the output from the AND gate41, and outputs the level-shifted signal. The level shifter46outputs, as a signal RDECADn, a signal obtained by inverting the output from the AND gate41and shifting the level of the inverted output. Also, the level shifter46supplies, to the transistor42, a signal obtained by shifting the level of the output from the AND gate41without inverting the output. That is, the level shifter46includes low-withstand-voltage, n-channel E type MOS transistors46aand46b, low-withstand-voltage, p-channel E type MOS transistors46cand46d, and an inverter46e.

The inverter46einverts the output from the AND gate41. The transistor46chas a gate connected to the output node of the AND gate41, and a source and back gate to which a power supply voltage Vdd is applied. The transistor46dhas a gate connected to the output node of the inverter46e, and a source and back gate to which the power supply voltage Vdd is applied. The transistor46ahas a drain connected to the drain of the transistor46c, a source and back gate to which a negative voltage VBB is applied, and a gate connected to the drain of the transistor46d. The transistor46bhas a drain connected to the drain of the transistor46d, a source and back gate to which the negative voltage VBB is applied, and a gate connected to the drain of the transistor46c. The potential of the drains of the transistors46aand46cand the gate of the transistor46bis the signal RDECADn.

The transistor42has a current path having one end connected to the drains of the transistors46dand46band the gate of the transistor46a, and has a gate to which a signal BSTON is supplied. The transistor43has a current path having one end connected to the other end of the current path of the transistor42, and the other end connected to a signal line TG, and has a gate to which the signal BSTON is supplied. The signal BSTON is a signal to be asserted (to “H” level) when receiving address information of the block decoder40, and supplied by, e.g., the control circuit15.

The transistor45has a current path having one end connected to the signal line TG, and the other end connected to the back gate, and has a gate to which the signal RDECADn is supplied. The transistor44has a current path having one end to which a voltage VRDEC is supplied, and the other end connected to the other end of the current path of the transistor45, and has a gate connected to the signal line TG.

In data write, read, and erase, if the block address BA matches the block BLK0, the transistors44and45are turned on to apply the voltage VRDEC (in this embodiment, “H” level) to the signal line TG. If the block address BA does not match the block BLK0, the MOS transistors44and45are turned off, and the signal line TG is set at, e.g., 0 V (“L” level).

The transistors50will be explained below. The transistors50transfer voltages to the word lines WL of a selected block BLK. Each of the transistors50-0to50-7has a current path having one end connected to an associated one of the word lines WL0to WL7of the block BLK0, and the other end connected to an associated one of signal lines CG0to CG7, and has a gate connected to the signal line TG.

Accordingly, in the row decoder11-0associated with the selected block BLK0, for example, the transistors50-0to50-7are turned on to connect the word lines WL0to WL7to the signal lines CG0to CG7. On the other hand, in the row decoders11-1to11-3associated with the unselected blocks BLK1to BLK3, the transistors50-0to50-7are turned off to disconnect the word lines WL0to WL7from the signal lines CG0to CG7.

The transistors51and52will be explained below. The transistors51and52transfer voltages to the select gate lines SGD. Each of the transistors51-0to51-3has a current path having one end connected to an associated one of the select gate lines SGD0to SGD3of the block BLK0, and the other end connected to an associated one of signal lines SGDD0to SGDD3, and has a gate connected to the signal line TG, and a back gate to which the negative voltage VBB is applied. Each of the transistors52-0to52-3has a current path having one end connected to an associated one of the select gate lines SGD0to SGD3of the block BLK0, and the other end connected to a node SGD_COM, and has a gate to which the signal RDECADn is supplied. The node SGD_COM is at a voltage that turns off the selection transistor ST1, e.g., at 0 V.

Accordingly, in the row decoder11-0associated with the selected block BLK0, for example, the transistors51-0to51-3are turned on, and the transistors52-0to52-3are turned off. Therefore, the select gate lines SGD0to SGD3of the selected block BLK0are connected to the signal lines SGDD0to SGDD3.

On the other hand, in the row decoders11-1to11-3associated with the unselected blocks BLK1to BLK3, the transistors51-0to51-3are turned off, and the transistors52-0to52-3are turned on. Therefore, the select gate lines SGD0to SGD3of the unselected blocks BLK1to BLK3are connected to the node SGD_COM.

The transistors53and54transfer voltages to the select gate lines SGS. The connection and operation are equivalent to those of the transistors51and52with the select gate lines SGD replaces by the select gate lines SGS.

That is, in the row decoder11-0associated with the selected block BLK0, the transistors53-0to53-3are turned on, and the transistors54-0to54-3are turned off. On the other hand, in the row decoders11-1to11-3associated with the unselected blocks BLK1to BLK3, the transistors53-0to53-3are turned off, and the transistors54-0to54-3are turned on.

The transistor55will be explained below. The transistor55transfers voltages to the backgate line BG. The transistor55has a current path having one end connected to the backgate line BG0of the block BLK0, and the other end connected to a signal line BGD, and has a gate connected to the signal line TG.

Accordingly, the transistor55is turned on in the row decoder11-0associated with the selected block BLK0, and turned off in the row decoders11-1to11-3associated with the unselected blocks BLK1to BLK3.

1.3.6 Well Isolation of Row Decoder11

FIG. 7is a sectional view of a partial region of the row decoder11. As shown inFIG. 7, the transistors42,43,46a,46b, and51to54having the back gates to which the negative voltage VBB is applied are formed on p-well regions36. Each p-well region36is formed in the surface of an n-well region35formed in the surface of the semiconductor substrate20. Thus, the transistors42,43,46a,46b, and51to54are electrically isolated from the transistors having the back gates to which a voltage of 0 V or more is applied.

Note that inFIG. 7, the pair of the transistors42and43, the pair of the transistors46aand46b, the pair of the transistors51and52, and the pair of the transistors53and54are formed on different well regions36. However, the four well regions36(and four well regions35) may also be collected into a single region.

Note also that inFIG. 7, the transistor50is formed on the semiconductor substrate20. The transistor50may thus be formed on the semiconductor substrate20because the transistor50does not transfer any negative voltage, but the transistor50may also be formed on the well region36.

The arrangement of the driver circuit12will now be explained. The driver circuit12transfers voltages necessary for data write, read, and erase to the signal lines CG0to CG7, SGDD0to SGDD3, SGSD0to SGSD3, and BGD.

As shown inFIG. 6, the driver circuit12includes CG drivers60(60-0to60-7), SGD drivers61(61-0to61-3), SGS drivers62(62-0to62-3), a BG driver64, and a voltage driver63.

First, the voltage driver63will be explained. The voltage driver63generates voltages to be used by the block decoder40and CG drivers60.

FIG. 8is a circuit diagram of the voltage driver63. As shown inFIG. 7, the voltage driver63includes first, second, and third drivers70,71, and72for generating voltages VBST, VRDEC, and VCGSEL, respectively.

The first driver70includes high-withstand-voltage, n-channel MOS transistors73and74, and local pump circuits L/P1and L/P2.

The current path of the transistor73has one end to which a voltage VPGMH is applied in programming, and which is connected to the local pump circuit L/P1. The voltage VPGMH is applied by the voltage generator14, and higher than a voltage VPGM. VPGM is a high voltage to be applied to a selected word line in programming. Also, the local pump circuit L/P1applies a voltage to the gate of the transistor73in programming.

The current path of the transistor74has one end to which a voltage VREADH is applied in data read, and which is connected to the local pump circuit L/P2. The voltage VREADH is applied by the voltage generator14, and higher than a voltage VREAD. VREAD is a voltage that is applied to an unselected word line in data read, and turns on the memory cell transistor MT regardless of held data. Also, the local pump circuit L/P2applies a voltage to the gate of the transistor74in data read. The other-ends of the current paths of the transistors73and74are connected together, and the voltage of this connection node is output as the voltage VBST.

In the first decoder70in the above-mentioned arrangement, the transistor73is turned on to output voltage VBST=VPGMH in programming. In data read, the transistor74is turned on to output voltage VBST=VREADH.

The second driver71will be explained below. The second driver71includes high-withstand-voltage, n-channel MOS transistors75and76, and local pump circuits L/P3and L/P4.

The current path of the transistor75has one end to which the voltage VPGMH is applied in programming, and which is connected to the local pump circuit L/P3. The local pump circuit L/P3applies a voltage to the gate of the transistor75in programming.

The current path of the transistor76has one end to which the voltage VREADH is applied in data read, and which is connected to the local pump circuit L/P4. The local pump circuit L/P4applies a voltage to the gate of the transistor76in data read. The other-ends of the current paths of the transistors75and76are connected together, and the voltage of this connection node is output as the voltage VRDEC.

In the second decoder71in the aforementioned arrangement, the transistor75is turned on to output voltage VRDEC=VPGMH in programming. In data read, the transistor76is turned on to output voltage VRDEC=VREADH.

The third driver72will be explained below. The third driver72includes high-withstand-voltage, re-channel MOS transistors77to80, a high-withstand-voltage, n-channel depletion type MOS transistor81, a resistance element82, local pump circuits L/P5and L/P6, and level shifters L/S1and L/S2.

The voltage VPGM is applied to one end of the current path of the transistor77, and this end is connected to the local pump circuit L/P5. The local pump circuit L/P5applies a voltage to the gate of the transistor77.

The current path of the transistor81has one end connected to the other end of the current path of the transistor77, and the other end connected to one end of the current path of the transistor78. An output from the level shifter L/S1is applied to the gates of the transistors78and81. In programming, the level shifter L/S1receives the voltage VBST from the first driver70, shifts the level of the voltage VBST, and outputs the level-shifted voltage.

The transistor79has a current path having one end to which a voltage VPASS is applied, and which is connected to the local pump circuit L/P6, and has a gate to which an output from the local pump circuit L/P6is applied. The voltage VPASS is a voltage that is applied to an unselected word line of an unselected block in programming, and turns on the memory cell transistor MT regardless of held data.

The transistor80has a current path having one end to which a voltage VCGR is applied, and has a gate to which an output from the level shifter L/S2is applied. In data read, the level shifter L/S2receives the voltage VREADH from the voltage generator14, shifts the level of the voltage VREADH, and outputs the level-shifted voltage.

The resistance element82has one terminal connected to one end of the current path of the transistor77, and the other terminal connected to the other end of the current path of the transistor77.

The other-ends of the current paths of the transistors78to80are connected together. This connection node is the output node of the third driver72, and outputs the voltage VCGSEL.

Note that a charge pump circuit in the voltage generator14generates the voltages VPGMH, VREADH, VPASS, and VCGR described above and a voltage VPASSA to be described later. Note also that the voltages VPGM and VREAD are generated by, e.g., stepping down the voltages VPGMH and VREADH.FIG. 9shows an arrangement example for generating the voltages VPGMH and VPGM in the voltage generator14.

As shown inFIG. 9, the voltage generator14includes a charge pump circuit90, limiter circuit91, and high-withstand-voltage, n-channel MOS transistor92. The charge pump circuit90generates the voltage VPGMH, and outputs the voltage VPGMH to a node N1. The transistor92is diode-connected between the node N1and a node N2. The transistor92has the same size and same threshold voltage as those of the transistor50.

The potential of the node N2is output as VPGM. Accordingly, VPGMH=VPGM+Vth where Vth is the threshold voltage of the transistor92. The limiter circuit91monitors the voltage VPGM, and controls the charge pump circuit90to give VPGM a desired value. This similarly applies to VREADH and VREAD.

The CG drivers60will be explained below. The CG drivers60-0to60-7each transfer necessary voltages to an associated one of the signal lines CG0to CG7(word lines WL0to WL7).FIG. 10is a circuit diagram of the CG driver60-0. The CG drivers60-1to60-7also have the same arrangement.

The transistor100has a current path having one end to which the voltage VCGSEL is applied, and the other end connected to an associated signal line CG (CGi in a CG driver60-iwhere i is one of 0 to 7), and has a gate to which an output from the level shifter L/S3is applied. In programming or data read, the level shifter L/S3receives the voltage VBST from the voltage driver63, shifts the level of the voltage VBST, and outputs the level-shifted voltage. The transistor101has a current path having one end to which the voltage VPASS is applied and which is connected to the local pump circuit L/P6, and the other end connected to the associated signal line CG, and has a gate to which an output from the local pump circuit L/P6is applied. The transistor103has a current path having one end to which the voltage VREAD is applied and which is connected to the local pump circuit L/P8, and the other end connected to the associated signal line CG, and has a gate to which an output from the local pump L/P8is applied. The transistor104has a current path having one end to which a voltage VISO is applied, and the other end connected to the associated signal line CG, and has a gate to which an output from the level shifter L/S4is applied. In programming, the level shifter L/S4receives the voltage VREADH, shifts the level of the voltage VREADH, and outputs the level-shifted voltage. The voltage VISO is a voltage for turning off the memory cell transistor MT regardless of held data.

In the CG driver60associated with a selected word line WL in the aforementioned arrangement, the control circuit15or the like turns on the transistor100in programming, thereby transferring the voltage VPGM (VCGSEL=VPGM) to the associated signal line CG in programming. In data read, the transistor100is turned on to transfer the voltage VCGR (VCGSEL=VCGRV) to the associated signal line CG. These voltages are transferred to the selected word line WL via the current path of the transistor50in the row decoder11.

In the CG driver60associated with an unselected word line, the control circuit15or the like turns on the transistor100and/or101or the transistor104in programming. The CG driver60in which the transistor100and/or101is turned on transfers the voltage VPASS to the associated signal line CG. The CG driver60in which the transistor104is turned on transfers the voltage VISO to the associated signal line CG. In data read, the transistor103is turned to transfer the voltage VREAD to the associated signal line CG. These voltages are transferred to the unselected word line WL via the current path of the transistor50in the row decoder11.

Note that the blocks BLK may also share CG0to CG7. That is, the four word lines WL0belonging to the four blocks BLK0to BLK3may also be driven by the same CG driver60-0via the transistors50-0of the associated row decoders11-0to11-3. This similarly applies to the signal lines CG1to CG7.

The SGD drivers61will be explained below. The SGD drivers61-0to61-3transfer necessary voltages to the signal lines SGDD0to SGDD3(select gate lines SGD0to SGD3).FIG. 11is a circuit diagram of the SGD driver61-0. The SGD drivers61-1to61-3also have the same arrangement.

As shown inFIG. 11, the SGD driver61includes high-withstand-voltage, n-channel E-type MOS transistors110and111, and a level shifter L/S5. The transistor110has a current path having one end to which a voltage VSGD is applied, and the other end connected to an associated signal line SGDD (SGDDj in an SGD driver61-jwhere j is one of 0 to 3), and has a gate to which an output from the level shifter L/S5is applied. In programming or data read, the level shifter L/S5receives the voltage VREADH, shifts the level of the voltage VREADH, and outputs the level-shifted voltage. The transistor111has a source to which the negative voltage VBB is applied, a drain connected to the associated signal line SGDD, and a gate to which a signal USEL1is supplied. The control circuit15sets the signal USEL1at “L” level (e.g., VBB) when the SGD driver61is associated with a NAND string including a selected cell in data write and read, and at “H” level in other SGD drivers61.

When performing data read and write in the above-described arrangement, in the SGD driver61associated with the select gate line SGD connected to the NAND string16including a selected word line, the transistor110is turned on, and the transistor111is turned off. Accordingly, the voltage VSGD is transferred to the associated signal line SGDD. The voltage VSGD is a voltage for turning on the selection transistor ST1in data read (in data write, this voltage turns on the transistor in accordance with write data). In other SGD drivers61, the transistors111are turned on, and the transistors110are turned off, thereby transferring the negative voltage VBB to the signal lines SGDD.

The transistor111transfers a negative voltage. Like the transistors51to54and the like explained with reference toFIG. 7, therefore, the transistor111is formed on the p-well region36electrically isolated from the semiconductor substrate20. Note that the transistor110may be formed on either the semiconductor substrate20or well region36.

The SGS drivers62will be explained below. The SGS drivers62-0to62-3transfer necessary voltages to the signal lines SGSD0to SGSD3(select gate lines SGS0to SGS3).FIG. 12is a circuit diagram of the SGS driver62-0. The SGS drivers62-1to62-3also have the same arrangement.

As shown inFIG. 12, the SGS driver62includes high-withstand-voltage, n-channel MOS transistors120and121, and a level shifter L/S6. The transistor120has a current path having one end to which the voltage VSGS is applied, and the other end connected to an associated signal line SGSD (SGSDk in an SGS driver62-kwhere k is one of 0 to 3), and has a gate to which an output from the level shifter L/S6is applied. In data read, the level shifter L/S6receives the voltage VREADH, shifts the level of the voltage VREADH, and outputs the level-shifted voltage. The transistor121has a source to which the negative voltage VBB is applied, a drain connected to the associated signal line SGSD, and a gate to which a signal USEL2is supplied. In data write, the control circuit15or the like sets the signal USEL2at “H” level in all the SGS drivers62. In data read, the signal USEL2is set at “L” level (e.g., VBB) when the SGD driver61is associated with a NAND string including a selected cell, and “H” level in other SGD drivers61.

When performing data read in the above-described arrangement, in the SGS driver62associated with the select gate line SGS connected to the NAND string16including a selected word line, the transistor120is turned on, and the transistor121is turned off, thereby transferring a voltage VSGS to the associated signal line SGSD. The voltage VSGS is a voltage for turning on the selection transistor ST2. In other SGS drivers62, the transistors121are turned on, and the transistors120are turned off, thereby transferring the negative voltage VBB to the signal lines SGSD.

In data write, the transistors120are turned off and the transistors121are turned on in all the SGS drivers62, thereby transferring the negative voltage VBB to the signal lines SGSD.

The transistor121transfers a negative voltage. Like the transistor111, therefore, the transistor121is formed on the p-well region36. Note that the transistor120may be formed on either the semiconductor substrate20or well region36.

The BG driver64will now be explained. The BG driver64is equivalent to, e.g., an arrangement obtained by omitting the VCGSEL transfer path from the CG driver60explained with reference toFIG. 10. That is, in data write, the transistor101or103transfers VPASS or VISO to the backgate line BG. In data read, the transistor103transfers VREAD to the backgate line BG.

2. Operation of Semiconductor Memory Device1

The operation of the NAND flash memory having the above arrangement will now be explained.

2.1 Write Operation

First, the write operation will be explained below with reference toFIGS. 13 and 14.FIG. 13is a timing chart showing the potentials of the interconnections in the write operation.FIG. 14is a circuit diagram of the memory cell array10and row decoders11in programming (an operation of trapping electric charge in the charge accumulation layer). As an example,FIG. 14shows a state in which the block BLK0is selected, and the memory cell transistor MT5in the memory group GP0in the selected block BLK0is selected. Note thatFIG. 14shows only the memory groups GP0and GP1of the block BLK0for convenience, but the memory groups GP2and GP3are the same as GP1.

As shown inFIG. 13, the sense amplifier13first transfers write data to each bit line BL. Data “L” (e.g., VSS=0 V) is applied to the bit line BL in order to raise the threshold value by injecting electric charge in the charge accumulation layer, and data “H” (e.g., 2.5 V) is applied in other cases. Also, a source line driver (not shown) applies, e.g., 2.5 V to the source line SL.

In the row decoder11, the block decoder40decodes the block address BA to set TG=“H” level in a selected block, and the transistors50,51, and53of the row decoder11are turned on. That is, as shown inFIG. 14, in the row decoder11-0associated with the selected block BLK0, the transistors50,51, and53are turned on, and the transistors52and54are turned off. In the row decoders11-1to11-3associated with the unselected blocks BLK1to BLK3, TG=“L” level (e.g., VBB) is set, the transistors50,51, and53are turned off, and the transistors52and54are turned on.

In the unselected blocks BLK1to BLK3, therefore, the transistors52and54transfer the negative voltage VBB to the select gate lines SGD and SGS, thereby cutting off both the selection transistors ST1and ST2.

On the other hand, in the selected block BLK0, the voltage VSGD (e.g., 4 V) is transferred to the select gate line SGD0associated with the memory group GP0including a selected page, and the transistors111and121transfer the negative voltage VBB to the select gate lines SGD1to SGD3and SGS1to SGS3associated with the memory groups GP1to GP3. Accordingly, the selection transistor ST1is turned on and the selection transistor ST2is turned off in the memory group GP0, and both the selection transistors ST1and ST2are turned off in the memory groups GP1to GP3.

After that, the control circuit15or the like decreases the voltage VSGD from 4 V to about 2.5 V. This voltage turns on the selection transistor ST1when data “L” is transferred to the bit line BL, and cuts off the transistor when data “H” is transferred.

Then, the control circuit15or the like activates the CG driver60to transfer a voltage to each signal line CG. That is, VPGM is transferred to the CG driver60associated with a selected word line, and VPASS (or VISO) is transferred to the CG driver60associated with an unselected word line. Referring toFIG. 14, the voltage VPGM is transferred to the signal line CG5, and the voltage VPASS is transferred to the signal lines CG0to CG4, CG6, and CG7(VISO may also be transferred to a given CG line). Since the transistors50are ON in the selected block BLK0, these voltages are transferred to the word lines WL0to WL7. On the other hand, the transistors50are OFF in the unselected blocks BLK1to BLK3, so none of these voltages are transferred to the word lines WL. That is, the word lines WL0to WL7in the unselected blocks BLK1to BLK3are electrically floated.

2.2 Read Operation

Next, the read operation will be explained with reference toFIG. 15.FIG. 15is a timing chart showing the potentials of the interconnections in the read operation.

As shown inFIG. 15, the CG driver60first generates the voltages VCGRV and VREAD. In a selected block, therefore, the voltages VCGRV and VREAD are transferred to the word lines WL. In an unselected block, the word lines WL are electrically floated.

Then, voltages are transferred to the select gate lines SGD and SGS. In a selected memory group of the selected block BLK, the transistors110and120transfer the voltages VSGD and VSGS (e.g., 4 V) to the select gate lines SGD and SGS. This turns on the selection transistors ST1and ST2. In an unselected memory group of the selected block BLK, the transistors111and121transfer the voltage VBB to the select gate lines SGD and SGS. This turns off the selection transistors ST1and ST2. Furthermore, in an unselected block BLK, the transistors52and54transfer the voltage VBB to the select gate lines SGD and SGS. This turns off the selection transistors ST1and ST2.

Also, the source line SL is set at VSS, and VBL (0.5 V), for example, is applied to the bit lines BL.

3. Effects of this Embodiment

The arrangement according to this embodiment can improve the operational reliability of a NAND flash memory. This effect will be explained below.

For a NAND string in which no data is to be written (no electric charge is to be injected) in a NAND flash memory, the channel potential is raised by coupling with a word line by cutting off the selection transistor ST1. This technique is known as the self-boost technique.

In the three-dimensionally stacked NAND flash memory (this embodiment) shown inFIGS. 3,4, and5, the threshold value of the select gates at the two ends of the NAND string16is difficult to control from the viewpoint of fabrication. This is so because the channel portions of the selection transistors ST1and ST2are made of intrinsic polysilicon. Therefore, the threshold value of the selection transistors ST1and ST2may be a negative value in some cases.

As a consequence, even when the ground potential VSS is supplied to unselected select gate lines SGD and SGS of a selected block or to the select gate lines SGD and SGS of an unselected block in, e.g., data write, it is sometimes impossible to cut off the selection transistors ST1and ST2and sufficiently raise the channel potential, so the data may be written in an unselected cell.

In this embodiment, however, the negative voltage can be applied to unselected select gate lines SGD and SGS of a selected block (and to the select gate lines SGD and SGS of an unselected block).

Also, the transistors (transistors51to54,111, and121) for transferring the negative voltage are formed in the triple well (seeFIG. 7), and the negative voltage is applied to this well (back gate). This makes it possible to transfer the negative voltage. Furthermore, in order to turn on the transistors51to54,111, and121, the transistors42,43,46a, and46bfor driving the gates of these transistors are also formed in the triple well, and the negative voltage is applied to the well.

Accordingly, even when the threshold value of the selection transistors ST1and ST2to be cut off is a negative value, it is possible to prevent the selection transistors ST1and ST2from being turned on, and improve the operation reliability.

Also, in the three-dimensionally stacked NAND flash memory, very many interconnections (word lines and select gate lines) are extracted to a narrow pitch of one NAND string. This extremely increases the area of the row decoders in order to independently control these interconnections for each NAND string (i.e., each memory group).

In this embodiment, therefore, a plurality of NAND strings (memory groups) share the word lines WL (seeFIG. 2). As described earlier, the unit of this sharing is a block. The selectivity of each NAND string in a block is secured by independently controlling the select gate lines SGD and SGS for each NAND string. This makes it possible to decrease the size of the row decoders11.

Second Embodiment

A semiconductor memory device according to the second embodiment will be explained below. In this embodiment, the channel compositions of the transistors50and51are made different in the above-mentioned first embodiment. Only the differences from the first embodiment will be explained below.

1. Arrangement of Row Decoder11

FIG. 16is a circuit diagram of a row decoder11according to this embodiment. As shown inFIG. 16, the row decoder11according to this embodiment has an arrangement in which the impurity concentration (and/or the impurity type) in the channel regions of transistors50and55is made different from that of transistors51and53, and intrinsic type (I-type) transistors having a threshold voltage of almost 0 V are used as the transistors50and55, inFIG. 6explained in the first embodiment.

Also, a transistor92of a voltage generator14explained inFIG. 9is also the same I-type as the transistors50and55, and they have the same threshold voltage.

2. Effects of this Embodiment

In the arrangement according to this embodiment, the transistor50for transferring a voltage to a word line WL is a high-withstand-voltage, I-type MOS transistor. Even in this case, the transistor50can be cut off by applying a negative voltage VBB to a signal line TG.

In this arrangement, the potential of the signal line TG can be decreased because the threshold value of the transistor50is smaller than that of the first embodiment. The potential of the signal line TG in a selected block is VRDEC, and this value is VPGMH (=VPGM+Vth) in data write as explained in the first embodiment. VPGMH is the highest voltage in a NAND flash memory1. In this respect, this embodiment can decrease the value of VPGMH by decreasing the value of Vth. Consequently, it is possible to reduce the load of a charge pump circuit90for generating VPGMH, and reduce the current consumption of the NAND flash memory1.

Especially in a three-dimensionally stacked NAND flash memory, the threshold voltage of a memory cell in an erased state sometimes has a positive value. That is, electric charge is trapped in a charge accumulation layer even in the erased state. In this case, the threshold voltages of memory cells in a written state also shift to high voltages as a whole. Accordingly, the power consumption of this NAND flash memory is higher than that of a memory in which the threshold value of a memory cell in the erased state is negative. From the viewpoint of the ability to reduce power consumption, therefore, this embodiment is desirably applied to a NAND flash memory like this.

As described above, the semiconductor memory device1according to this embodiment includes the memory cell (MT inFIG. 2), selection transistor (ST1inFIG. 2), memory string (NAND string16inFIG. 2), block (BLK inFIG. 1), word line (WL inFIG. 2), select gate line (SGD inFIG. 2), bit line (BL inFIG. 2), and transfer circuit (row decoder11inFIG. 14). The memory cell (MT inFIG. 2) is stacked above a semiconductor substrate, and includes a charge accumulation layer and control gate. In the memory string (NAND string16inFIG. 2), the current paths of the memory cells and the selection transistor are connected in series. The block (BLK inFIG. 1) includes a plurality of memory strings. The word line (WL inFIG. 2) is coupled to the control gate. The select gate line (SGD inFIG. 2) is coupled to a gate of the selection transistor. The bit line (BL inFIG. 2) is coupled to one of the memory cells through the current path of the selection transistor. In data write and read, the transfer circuit (row decoder11inFIG. 14) transfers a positive voltage (VSGD inFIG. 14) to a select gate line (SGD0inFIG. 14) associated with a selected memory string in a selected block (BLK0inFIG. 14), and a negative voltage (VBB inFIG. 14) to a select gate line (SGD1inFIG. 14) associated with an unselected memory string in the selected block (BLK0inFIG. 14), and to a select gate line (SGD inFIG. 14) associated with a memory string in an unselected block (BLK1-3inFIG. 14).

As described above, since the row decoder (transfer circuit)11for applying a negative potential to the select gate line is used, the selection transistor in an unselected NAND string16of a selected block can be cut off even when the transistor has a negative threshold value. This can be achieved by forming the driving transistors51to54of the select gate lines in the triple wells, and changing the well potential to a negative potential during programming or read. In programming or read, normal read or write can be performed by setting the select gate lines of unselected strings of an unselected block and selected block at a negative potential, and connecting the select gate line of a selected string of the selected block to another node (the driver circuit12).

Note that the embodiments are not limited to the forms explained above, and various modifications can be made. For example, the transistor50explained with reference toFIG. 16may also be a depletion type (D-type) MOS transistor having a negative threshold value. By using an I-type or D-type transistor, the transistor50can be turned off, even when its threshold value becomes 0 V or less, by appropriately setting the potential of the signal line TG.

The memory cell array shown inFIG. 2may also have an arrangement as shown inFIG. 17.FIG. 17is a circuit diagram of the block BLK0, and the blocks BLK1to BLK3can have the same arrangement. As shown inFIG. 17, the word lines WL0to WL3, backgate line BG, even-numbered select gate lines SGD0and SGD2, and odd-numbered select gate lines SGS1and SGS3are extracted to one side of the memory cell array10. On the other hand, the word lines WL4to WL7, even-numbered select gate lines SGS0and SGS2, and odd-numbered select gate lines SGD1and SGD3are extracted to the other side of the memory cell array10, which is opposite to the above-mentioned one side. An arrangement like this is also possible.

In this arrangement, it is possible to divide the row decoder11into two row decoders, and arrange them such that they oppose each other with the memory cell array10being sandwiched between them. In this arrangement, one row decoder can select the select gate lines SGD0, SGD2, SGS1, and SGS3, word lines WL0to WL3, and backgate line BG, and the other row decoder can select the select gate lines SGS0, SGS2, SGD1, and SGD3, and word lines WL4to WL7. This arrangement can reduce the complexity of interconnections such as the select gate lines and word lines in the region (including the row decoder11) between the driver circuit12and memory cell array10.

Moreover, in each of the above embodiments, the semiconductor memory device is explained by taking a three-dimensionally stacked NAND flash memory as an example. However, the three-dimensionally stacked NAND flash memory is not limited to the arrangement shown inFIGS. 3,4, and5. For example, the semiconductor layer26need not have a U-shape, and can also be a single pillar. In this arrangement, the transistor BT is unnecessary. Also, the embodiments are applicable not only to the three-dimensionally stacked memory, but also to, e.g., a conventional NAND flash memory in which memory cells are two-dimensionally arranged in the plane of a semiconductor substrate. Furthermore, each embodiment is explained by taking the operation in which data is erased for each block BLK as an example, but the present embodiments are not limited to this. As an example, data may also be erased for a plurality of NAND strings16.

Further, the timing of applying VBB to the unselected select gate lines is not limited to the case shown inFIG. 13andFIG. 15, and can be modified. For example, when the semiconductor memory device is powered-on, the voltage generator14may start and continue a generating VBB. In this case, VBB may be constantly applied to the unselected select gate lines. As a result, inFIG. 13andFIG. 15, resetting the potential of the unselected select gate lines to VSS at the start and the end of the operations is not necessary for every operation.