Signal generation apparatus for frequency conversion in communication system

A signal generation apparatus includes a signal generation portion and a phase compensator. The phase compensator generates a phase error control signal that maintains a phase difference between the in-phase and quadrature-phase signals generated by the signal generation portion. The phase compensator includes an offset compensator and a delay compensator. The offset compensator is set to compensate for an offset voltage through the phase compensator. The delay compensator is set to compensate for a difference of delays through paths for the in-phase and quadrature-phase signals within the phase compensator.

BACKGROUND OF THE INVENTION

This application claims priority under 35 USC §119 to Korean Patent Application No. 2007-29324 filed on Mar. 26, 2007 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

1. Field of the Invention

The present invention relates generally to communication systems, and more particularly, to a signal generation apparatus for generating in-phase and quadrature (I/Q) signals with compensation of offset voltage and phase delay in a phase compensator.

2. Background of the Invention

In general, a zero-IF structure and an image rejection structure in a receiver or transmitter of a communication system typically uses an in-phase signal (hereinafter, referred to as an “I signal”) and a quadrature-phase signal (hereinafter, referred to as a “Q signal”) that are desired to have a phase difference of about 90°.FIG. 1shows a block diagram of a frequency converting apparatus10which may be used in a receiver or transmitter according to the prior art. Referring toFIG. 1, the frequency converting apparatus10includes a signal generation circuit12, a first mixer18, and a second mixer20.

The signal generation circuit12generates the I signals Ip and In as differential signals and generates the Q signals Qp and Qn as differential signals. The signal generation circuit12includes a voltage control oscillator (VCO)14and an I/Q signal generator16. The voltage control oscillator14generates differential oscillating signals In+and In−. The I/Q signal generator16generates the differential I signals Ip and In and the differential Q signals Qp and Qn from the differential oscillating signals In+and In−. The pair of signals Ip and Qp are desired to have a phase difference of 90°, and the pair of signals In and Qn are desired to have a phase difference of 90°.

The first mixer18mixes a wireless (i.e., radio frequency) input signal RFIN and at least one of the I signals Ip and In to generate an in-phase intermediate frequency signal IIF. The second mixer20mixes the wireless input signal RFIN and at least one of the Q signals Qp and Qn to generate a quadrature-phase intermediate frequency signal IQF. When the phase difference between the signals Ip and the Qp or the signals In and the Qn is not accurately maintained at 90°, an image rejection characteristic of each of the first and second mixers18and20may disadvantageously be deteriorated.

A plurality of phase compensators (not shown inFIG. 1) compensate for a phase difference between the In and Qn signals to be maintained at 90°. However, the phase difference between the Ip and Qp signals may not be accurately maintained at 90° because of an offset voltage and a phase delay in the phase compensator. For example, the phase delay may be due to differences through multiple transfer paths within the phase compensator.

In addition, the Ip and Qp signals or the In and Qn signals may not have an accurate phase difference of 90° from variable parameters such as the manufacturing process, a supply voltage, and temperature. Thus, a signal-to-noise ratio (SNR) is deteriorated, and consequently a receiving sensitivity of a receiver or a transmitting sensitivity of a transmitter in a communication system is deteriorated.

SUMMARY OF THE INVENTION

Accordingly, a phase compensator of a signal generation apparatus is calibrated for compensating for the offset voltage and the phase delay in the phase compensator.

A signal generation apparatus according to an aspect of the present invention includes a signal generation portion and a phase compensator. The signal generation portion generates in-phase and quadrature-phase signals. The phase compensator generates a phase error control signal that maintains a phase difference between the in-phase and quadrature-phase signals. The phase compensator includes an offset compensator and a delay compensator. The offset compensator is set to compensate for an offset voltage through the phase compensator. The delay compensator is set to compensate for a difference of delays through paths for the in-phase and quadrature-phase signals within the phase compensator.

In another embodiment of the present invention, the phase compensator includes first and second delay units, a switch portion, and a main controller. The first delay unit provides a first delay to the in-phase signal, and the second delay unit provides a second delay to the quadrature-phase signal. The main controller controls the switch portion to selectively couple or uncouple each of the in-phase and quadrature-phase signals to the first and second delay units depending on each of a plurality of modes of operation of the signal generation apparatus.

In an example embodiment of the present invention, the modes of operation include calibration of the delay compensator, calibration of the offset compensator, and normal operation of the phase compensator. In that case, the phase compensator further includes first, second, and third registers. The first register stores an offset control code determined during the calibration of the offset compensator, and the offset control code is used to compensate for the offset voltage through the phase compensator.

The second register stores a phase delay control code determined during the calibration of the delay compensator, and the phase delay control code is used to compensate for the difference of the delays through the paths for the in-phase and quadrature-phase signals within the phase compensator. The third register stores a phase error control code determined during normal operation of the phase compensator, and the phase error control code is used to maintain the phase difference between the in-phase and quadrature-phase signals.

In a further embodiment of the present invention, the delay compensator includes the first and second delay units, and the signal generation apparatus further includes a code controller that sets the phase delay control code for determining at least one of the first and second delays for minimizing the difference of the delays through the paths for the in-phase and quadrature-phase signals within the phase compensator.

In another embodiment of the present invention, the signal generation apparatus further includes a switch portion, a mixer, a low-pass filter, a differentiator, and a comparator. The switch portion selectively couples a same one of the in-phase and quadrature-phase signals through the first and second delay units during calibration of the delay compensator. The mixer mixes outputs from the first and second delay units to generate a mixed signal. The low-pass filter filters the mixed signal to generate a filtered signal. The differentiator differentiates the filtered signal to generate a differentiated signal. The comparator compares the differentiated signal to a desired delay level. The code controller adjusts the phase delay control code for determining at least one of the first and second delays until the differentiated signal is at the desired delay level.

In that case in an example embodiment of the present invention, the first and second delay units, the code controller, the switch portion, the mixer, the low-pass filter, the differentiator, and the comparator are disposed within the phase compensator.

In another embodiment of present invention, the offset compensator includes the first and second delay units and an offset compensation unit that adjusts a combination of signals from the first and second delay units according to the offset control code that is set to minimize an effect of the offset voltage through the first and second signal paths. In addition, such an offset compensator further includes a switch portion, a mixer, a low-pass filter, a comparator, and a code controller.

The switch portion uncouples the in-phase and quadrature-phase signals from the first and second delay units during calibration of the offset compensator. The mixer mixes outputs from the first and second delay units to generate a mixed signal. The offset compensation unit adjusts the mixed signal according to the offset control code to generate an offset compensated signal. The low-pass filter filters the offset compensated signal to generate a filtered signal. The comparator compares the filtered signal to a desired offset level. The code controller adjusts the offset control code until the filtered signal is at the desired offset level. In that case, the first and second delay units, the offset compensation unit, the switch portion, the mixer, the low-pass filter, the comparator, and the code controller are disposed within the phase compensator.

The signal generation apparatus according to another embodiment of the present invention includes the first and second delay units with the first and second delays set for minimizing the difference of the delay between the in-phase and quadrature-phase signals through the phase compensator. In that case, the signal generation apparatus also includes a switch portion, a mixer, an offset compensation unit, a low-pass filter, a comparator, and a code controller.

In that case, the switch portion couples the in-phase signal to the first delay unit and couples the quadrature-phase signal to the second delay unit for normal operation of the phase compensator. The mixer mixes outputs from the first and second delay units to generate a mixed signal. The offset compensation unit adjusts the mixed signal to generate an offset compensated signal for minimizing an effect of the offset voltage through the first and second delay units. The low-pass filter filters the offset compensated signal to generate a filtered signal. The comparator compares the filtered signal to a desired phase difference level. The code controller adjusts the phase error control signal for adjusting the phase difference between the in-phase and quadrature-phase signals until the filtered signal is at the desired phase difference level. In this case, the first and second delay units, the switch portion, the mixer, the offset compensation unit, the low-pass filter, the comparator, and the code controller are disposed within the phase compensator.

The signal generation apparatus according to another embodiment of the present invention includes an oscillator for generating an oscillating signal and includes a signal generation portion. The signal generation portion uses the oscillating signal to generate the in-phase and quadrature-phase signals having the phase difference according to the phase error control signal.

In this manner, the offset voltage and the phase delay through the paths for the in-phase and quadrature-phase signals within the phase compensator are compensated. With such correction for the offset voltage and the phase delay in the phase compensator, the in-phase and quadrature-phase signals are maintained to have a phase difference of 90°. The present invention may be used to particular advantage when the in-phase and quadrature-phase signals are used for frequency conversion of a radio frequency input signal in a communication system.

The figures referred to herein are drawn for clarity of illustration and are not necessarily drawn to scale. Elements having the same reference number inFIGS. 1,2,3,4,5,6,7,8,9,10, and11refer to elements having similar structure and/or function.

DETAILED DESCRIPTION OF THE INVENTION

The above drawings for illustrating preferred embodiments of the present invention are referred to in order to gain a sufficient understanding of the present invention, the merits thereof, and the objectives accomplished by the implementation of the present invention. Hereinafter, the present invention is described in detail by explaining preferred embodiments of the invention with reference to the attached drawings.

FIG. 2is a block diagram of a frequency converting apparatus100according to an embodiment of the present invention. The frequency converting apparatus100may be used in a receiver or a transmitter of a communication system for example.FIG. 3is a block diagram of a phase compensator140ofFIG. 2according to an embodiment of the present invention.

Referring toFIGS. 2 and 3, the frequency converting apparatus100includes a signal generation apparatus110, a buffer portion150, a first mixer155, and a second mixer157. A receiver including the frequency converting apparatus100would include an antenna (not shown) that receives a radio frequency input signal RFIN.

The signal generation apparatus110generates at least one in-phase signal Ip and/or In and at least one quadrature-phase signal Qp and/or Qn. The in-phase signals Ip and In are differential signals with respect to each-other, and the quadrature-phase signals Qp and Qn are differential signals with respect to each-other.

The pair of in-phase and quadrature-phase signals Ip and Qp are desired to have a phase difference of 90°. The pair of in-phase and quadrature-phase signals In and Qn are desired to have a phase difference of 90°. The phases of the in-phase and quadrature-phase signals are set according to a phase error control code C-code for compensation of any phase error between at least one of the pair of in-phase and quadrature-phase signals Ip and Qp and the pair of in-phase and quadrature-phase signals In and Qn.

The signal generation apparatus110includes a signal generation portion120, an oscillator130, and a phase compensator140. The signal generation portion120generates the differential in-phase signals Ip and In and the differential quadrature-phase signals Qp and Qn from differential oscillating signals Din+ and Din− generated by the oscillator130. The present invention may also be practiced with a single ended in-phase signal I and a single ended quadrature-phase signal Q.

The buffer portion150includes a first buffer151and a second buffer153. The first buffer151buffers the in-phase signal Ip and/or In from the signal generation portion120, and the second buffer153buffers the quadrature-phase signal Qp and/or Qn from the signal generation portion120. The first mixer155mixes the radio frequency input signal RFIN and at least one of the output signals of the first buffer151to generate an in-phase intermediate frequency signal IF. The second mixer157mixes the radio frequency input signal RFIN and at least one of the output signals of the second buffer153to generate a quadrature-phase intermediate frequency signal QF.

The oscillator130is a voltage controlled oscillator (VCO) according to an embodiment of the present invention, but the present invention is not limited thereto. The phase compensator140receives the in-phase signals Ip and In and the quadrature-phase signals Qp and Qn, detects a phase error between the in-phase and quadrature-phase signals to generate the C-code. Thus, the phase compensator140maintains the phase difference between the pair of in-phase and quadrature-phase signals In and Qn at about 90° and maintains the phase difference between the pair of in-phase and quadrature-phase signals Ip and Qp at about 90°.

The phase compensator140includes components that compensate for a DC offset voltage within the phase compensator140and a phase delay θdtof signal paths for the in-phase and quadrature-phase signals within the phase compensator140. The phase compensator140includes a phase error detection portion142, a code control portion144, and a main controller146.

The phase error detection portion142includes a switch portion142-1, a delay portion comprised of a first delay unit142-3and a second delay unit142-5, a mixer142-7, an offset compensation portion142-9, and a low pass filter142-11. The code control portion144includes a differentiator144-1, a comparator144-3, a code controller144-5, a first register144-7, a second register144-9, and a third register144-11.

Referring toFIG. 10, the main controller146includes a main data processor146-1and a main memory device146-2having sequences of instructions (i.e., software) stored therein. Execution of such sequences of instructions by the main data processor146-1causes the main data processor146-1to perform steps S51, S53, and S55in the flow-chart ofFIG. 11.

In such steps, the main controller146generates a first control signal C1for controlling a configuration of the switch portion142-1. The main controller146also generates a second control signal C2for controlling a first by-pass switch142-9A coupled to the offset compensation portion142-9. The main controller146also generates a third control signal C3for controlling a second by-pass switch144-1A coupled to the differentiator144-1.

Further referring toFIG. 10, the code controller144-5includes a code data processor144-5A and a code memory device144-5B having sequences of instructions (i.e., software) stored therein. Execution of such sequences of instructions by the code data processor144-5A causes the code data processor144-5A to perform steps S52, S54, and S56in the flow-chart ofFIG. 11and steps S10, S20, S31, S33, S35, S41, S43, and S45ofFIG. 7.

Operation of the phase compensator140in the frequency converting apparatus100is now described. Referring toFIGS. 3,4,10, and11, the main controller146configures the phase compensator140as illustrated inFIG. 4for calibration of an offset compensator comprised of the offset compensation portion142-9(step S51inFIG. 11). In that case, the main controller146generates the first control signal C1for controlling the switch portion142-1to uncouple the in-phase signal Ip and/or In and the quadrature-phase signal Qp and/or Qn from the first and second delay units142-3and142-5.

In addition, the main controller146generates the second control signal C2for controlling the first bypass switch142-9A to be open. Furthermore, the main controller146generates the third control signal C3for controlling the second bypass switch144-1A to be closed for bypassing the differentiator144-1.

With such configuration ofFIG. 4, the code controller144-5determines the offset control code O-code that compensates for the DC offset voltage in the phase compensator140. With the in-phase signal Ip and/or In and the quadrature-phase signal Qp and/or Qn cut off by the switch portion142-1, only the DC offset voltage of the phase compensator140are generated at the outputs of the first and second delay units142-3and142-5.

The mixer142-7mixes outputs from the first and second delay units142-3and142-5to generate a mixed signal. The offset compensation portion142-9adjusts the mixed signal from the mixer142-7according to the offset control code O-code as stored in the first register144-7by the code controller to generate an offset compensated output. The low pass filter142-11performs low-pass filtering on the offset compensated output to generate a filtered signal that may be differential signals or complementary signals.

The comparator144-3compares the filtered signal to a desired offset level. The code controller144-5adjusts the offset control code O-code until the filtered signal is substantially at the desired offset level (step S52ofFIG. 11). When the filtered signal is substantially at the desired offset level, the DC offset voltage within the phase compensator140is satisfactorily compensated. The offset control code O-code, of N bits with N being a natural number, resulting in the filtered signal being substantially at the desired offset level is stored into the first register144-7.

After calibration of the offset compensator142-9, the main controller146configures the phase compensator140as illustrated inFIG. 5for calibration of a delay compensator comprised of the first and second delay units142-3and142-5(step S53inFIG. 11). In that case, the main controller146generates the first control signal C1for controlling the switch portion142-1to couple just the selected in-phase signal Ip and/or In to both of the first and second delay units142-3and142-5. During the calibration of the delay compensator, a selected one of the in-phase signal or the quadrature-phase signal is coupled to the first and second delay units142-3and142-5.

In addition, the main controller146generates the second control signal C2for controlling the first bypass switch142-9A to be closed for bypassing the offset compensation portion142-9. Furthermore, the main controller146generates the third control signal C3for controlling the second bypass switch144-1A to be open such that the differentiator144-1is used.

With such configuration ofFIG. 5, the code controller144-5determines the phase delay control code D-code that compensates for a phase delay between the signal paths for the in-phase and quadrature phase signals (step S54ofFIG. 11). The first delay unit142-3is a first signal path that transmits the in-phase signal Ip and/or In, and the second delay unit142-5is a second signal path that transmits the quadrature-phase signal Qp and/or Qn.

Further referring toFIG. 5, the first delay unit142-3transmits the in-phase signal Ip and/or In with a first phase delay θd1. The second delay unit142-5transmits the same in-phase signal Ip and/or In with a second phase delay θd2. The mixer142-7mixes such outputs from the first and second delay units142-3and142-5to generate the mixed signal. The low pass filter142-11performs low-pass filtering on the mixed signal to generate a filtered signal.

The differentiator144-1differentiates the filtered signal to generate a differentiated signal. The comparator144-3compares the differentiated signal to a desired delay level. The code controller144-5adjusts the phase delay control code D-code until the differentiated signal is substantially at the desired delay level (step S54ofFIG. 11). In one embodiment of the present invention, the second delay unit142-5adjusts the second delay θd2according to the phase delay control code D-code.

When the differentiated signal is substantially at the desired delay level, the phase delay between the signals output from the first and second delay units142-3and142-7is minimized to a desired level. The phase delay control code D-code resulting in the differential signal being substantially at the desired delay level is stored into the second register144-9.

The present invention may be practiced with at least one of the first and second phase delays θd1and θd2being adjusted according to the phase delay control code D-code. For example, at least one of the first and second phase delays θd1and θd2is a digitally controlled delay.

During calibration of the delay compensator, assume that the in-phase signal Ip and/or In transmitted to the first and second delay units142-3and142-5is expressed as cos(w·t). In addition, assume that the output of the first delay unit142-3is cos(w·t). In that case, the output of the second delay unit142-5is expressed as cos(w·t+θdt), with θdt=θd2−θd1.

Such outputs cos(w·t) and cos(w·t+θdt) of the first and second delay units142-3and142-5are mixed by the mixer142-7. The output of the mixer142-7is filtered by the low pass filter142-11to remove a high harmonic component such that the output of the low pass filter142-11is cos(θdt) as illustrated inFIG. 6.

The differentiator144-1differentiates the signal from the low pass filter142-11to generate the differentiated signal. The comparator144-3and the code controller144-5operate according to the flow-chart ofFIG. 7to determine the phase delay control code D-code. Referring toFIGS. 5,6, and7, the code controller144-5first increases the D-code from an initial value (step S10ofFIG. 7).

Then, the code controller144-5determines whether the output of the comparator144-3is at a first logic state (i.e., a high state) or at a second logic state (i.e., a low state) (step S20ofFIG. 7). Referring toFIG. 6, note that the output of the comparator144-3is at the first logic state if cos(θdt) is increasing and is at the second logic state if cos(θdt) is decreasing. The phase delay control code D-code is adjusted such that the phase difference θdtis changed by a step RS.

If the output of the comparator144-3is at the first logic state at step S20, the phase delay control code D-code is increased (step S31ofFIG. 7) such that the phase difference θdtis increased by a step RS. Thereafter, the code controller144-5determines whether the output of the comparator144-3is at the first logic state or the second logic state (step S33ofFIG. 7). If the output of the comparator144-3is at the first logic state at step S33, the phase delay control code D-code is further increased with a return to step S31.

Steps S33and S31are repeated until the output of the comparator144-3is at the second logic state when the phase delay control code D-code is decreased (step S35) such that the phase difference θdtis decreased by a step RS. At that point, the phase delay control code D-code for calibration of the delay compensator has been determined and is then stored into the second register144-9.

Referring back to step S20if the output of the comparator S20is at the second logic state, the phase delay control code D-code is decreased (step S41ofFIG. 7) such that the phase difference θdtis decreased by the step RS. Thereafter, the code controller144-5determines whether the output of the comparator144-3is at the first logic state or the second logic state (step S43ofFIG. 7). If the output of the comparator144-3is at the second logic state at step S43, the phase delay control code D-code is further decreased with a return to step S41.

Steps S43and S41are repeated until the output of the comparator144-3is at the high logic state when the phase delay control code D-code is increased (step S45) such that the phase difference θdtis increased by a step RS. At that point, the phase delay control code D-code for calibration of the delay compensator has been determined and is then stored into the second register144-9.

In this manner, note that the phase delay control code D-code is determined substantially near the point M3when cos(θdt) is at a maximum inFIG. 6. In that case, the delay difference through the signal paths for the in-phase and quadrature-phase signals within the phase compensator140is minimized.

After calibration of the offset compensator and the delay compensator, the main controller146configures the phase compensator140as illustrated inFIG. 8for normal operation of the phase compensator140for phase error compensation (step S55inFIG. 11). In that case, the main controller146generates the first control signal C1for controlling the switch portion142-1to couple the in-phase signal Ip and/or In to the first delay unit142-3and to couple the quadrature-phase signal Qp and/or Qn to the second delay unit142-5.

In addition, the main controller146generates the second control signal C2for controlling the first bypass switch142-9A to be open. Furthermore, the main controller146generates the third control signal C3for controlling the second bypass switch144-1A to be closed for bypassing the differentiator144-1.

Note that during normal operation of the phase compensator140inFIG. 8, the first and second delays θd2and θd1of the first and second delay units142-3and142-5have been set according to the phase delay control code D-code from calibration of the delay compensator in step S54. In addition during such normal operation of the phase compensator140inFIG. 8, the offset compensation portion142-9has been set according to the offset control code O-code from calibration of the offset compensator in step S52.

Assume that the in-phase signal Ip and/or In is expressed as cos(wt) and that the quadrature-phase signal Qp and/or Qn is expressed as sin(wt+θerr) with θerrbeing a phase error. The phase difference between the in-phase and quadrature-phase signals is desired to be 90°. The phase error θerrindicates the level of deviation of the phase difference from the desired 90°. The mixer142-7mixes such signals cos(wt) and sin(wt+θerr), and the offset compensation portion142-9adjusts the output of the mixer142-7to compensate for the offset voltage according to the offset control code O-code as stored in the first register144-7. The low pass filter142-11filters the output of the offset compensation portion142-9to generate a signal expressed as A·sin(θerr) as illustrated inFIG. 9.

The output of the low pass filter142-11A·sin(θerr) is desired to be minimized such that the phase θerris removed to zero. The phase error code C-code is adjusted by the code controller144-5until the output of the low pass filter142-11A·sin(θerr) is minimized such as point E1to E3inFIG. 9similarly as described with reference toFIG. 7(step S56inFIG. 11). The C-code of N bits with N being a natural number when the output of the low pass filter142-11A·sin(θerr) is minimized to remove the phase error θerris then stored into the third register144-11.

In this manner, the offset voltage and the phase delay within the phase compensator140have been compensated during normal operation of the phase compensator140for phase error compensation of the in-phase and quadrature-phase signals. Thus, the signal generation apparatus generates the in-phase signal Ip and/or In and the quadrature-phase signal Qp and/or Qn having the desired phase difference of 90°.

Accordingly, the frequency converting apparatus100has enhanced signal-to-noise ratio and image compensation rate. Also, the receiver or transmitter including the frequency converting apparatus100in a communication system has an improved receiving or transmitting sensitivity.

The present invention is limited only as defined in the following claims and equivalents thereof.