Two-dimensional interpolation architecture for motion compensation in multiple video standards

The present invention provides an apparatus for interpolation which is able to process input data with multiple video standards without sacrificing chip area. The interpolation unit comprises: a first interpolation unit for interpolating input data; a second interpolation unit for interpolating input data; a filter indicator for providing information to the first interpolation unit and the second interpolation unit; and an output unit for multiplexing and averaging output from the first interpolation unit and the second interpolation unit. The present invention also provides a motion compensation unit and a decoder for processing multiple video standards.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit of Chinese patent application number 200710308372.0, filed Dec. 29, 2007, which is herein incorporated by reference.

FILED OF INVENTION

The present invention relates to motion compensation for multiple video standards, and, more specifically, to a two-dimensional interpolation architecture of motion compensation to comply with multiple video standards.

BACKGROUND

Digital video streams are typically encoded using one of many different encoding standards. There are currently a large number of video encoding standards, and new standards are frequently emerging. Examples of current video encoding standards include JPEG (Joint Photographic Experts Group), MPEG (Moving Pictures Experts Group), MPEG-2, MPEG-3, MPEG-4, H.263, H.263+, H.264, and proprietary standards such as Real Video and Windows Media. In order to fully realize the benefits of digital video, a user requires access to encoder and/or decoder that are capable of processing all common encoding standards.

Currently, motion compensation in a video encoding/decoding process for each video standard requires different pipelines, so that a large chip area is occupied in order to achieve motion compensation for multiple video standards. However, chip area is limited, and what is needed is a motion compensation apparatus that is able to process different video standards and also meet chip area requirement.

SUMMARY OF INVENTION

To solve the above problems, an embodiment of the present invention provides an apparatus for interpolation. The apparatus for interpolation comprises a first interpolation unit for interpolating input data; a second interpolation unit for interpolating input data; a filter indicator for providing information to the first interpolation unit and the second interpolation unit; and an output unit for multiplexing and averaging output from the first interpolation unit and the second interpolation unit.

Another embodiment of the present invention provides an apparatus for motion compensation. The apparatus for motion compensation comprises an interpolation unit for interpolation of reference data into input data; a discrete cosine transform (DCT) unit for performing discrete cosine transform of output of the interpolation unit; a quantization unit for performing quantization of output of the DCT unit; and a feedback unit. The interpolation unit therein further comprises a first interpolation unit for interpolating input data; a second interpolation unit for interpolating input data; a filter indicator for providing information to the first interpolation unit and the second interpolation unit; and an output unit for multiplexing and averaging output from the first interpolation unit and the second interpolation units.

Another embodiment of the present invention provides a video decoder with motion compensation. The video decoder comprises an inverse DCT unit for performing inverse DCT of input data; an inverse quantization unit for performing inverse quantization of output of the inverse DCT unit; a frame memory for storing frame output of the inverse quantization unit; and a motion compensation unit for performing motion compensation of data stored in the frame memory and feeding an output into an adder which adds output of the inverse quantization unit to output of the motion compensation. The motion compensation unit therein comprises an interpolation unit for interpolation of reference data into input data, the interpolation unit further comprising a first interpolation unit for interpolating input data; a second interpolation unit for interpolating input data; a filter indicator for providing information to the first interpolation unit and the second interpolation unit; and an output unit for multiplexing and averaging output from the first interpolation unit and the second interpolation unit.

DETAILED DESCRIPTION OF THE INVENTION

The following discloses preferred embodiments of the unified inverse discrete cosine transform (IDCT) microcode processor engine, which are able to facilitate IDCT of various video standards without sacrificing speed. The video standards include, without limitation, ISO/IEC 13253 (also known as MPEG-2), ISO/IEC 14496 (also known as MPEG-4), ISO/IEC 14496-10 (also known as H.264/AVC) and SMPTE 421M (also known as VC-1).

FIG. 1illustrates a simplified block diagram of an interpolation unit100according to an embodiment of the present invention. The interpolation unit100comprises a filter indicator110, a vertical filter120, a buffer130, a horizontal140, a FIFO buffer150, a buffer160, a horizontal filter170and an output unit180. As shown inFIG. 1, filter indicator110receives filter parameters and provides information required by vertical filter120, buffers130and140, FIFO150, horizontal filters140and170, and output unit180. Vertical filter120performs vertical filtering on input data and the filtered input data is then stored in buffer130. Horizontal filter140performs horizontal filtering140on data stored in buffer130. FIFO150manipulates input data into the first-in first-out order and stores them in buffer160. Subsequently, horizontal filter170performs horizontal filtering on data stored in buffer160. Output unit180multiplexes and averages output from horizontal buffers140and170.

Interpolation unit100is able to facilitate video interpolation for VC1, H264 and MPEG-2 standards. For MPEG-4 standard, the input data need to be transposed before they are fed into the two pipelines, since the interpolation of MPEG-4 input data need to be horizontally filtered.FIG. 2illustrates a simplified block diagram of an interpolation unit200according to another embodiment of the present invention. As shown inFIG. 2, interpolation unit200further comprises a transpose buffer290and a multiplexer295, which are configured to facilitate input data of MPEG-4 standards. As a result, interpolation unit200is able to interpolate input data of VC1, H264, MPEG-2 and MPEG-4 standards.

FIG. 3illustrates a simplified block diagram of an interpolation unit300according to yet another embodiment of the present invention. Interpolation unit300is also able to facilitate VC1, H264, MPEG-2 and MPEG-4 standards. Input data of H264, MPEG-2 and MPEG-4 standards are not transposed before they are fed into the two pipelines, meaning that input data of H264, MPEG-2 and MPEG-4 standards are fed into horizontal filter320and FIFO350without transposing. Input data of VC1 standard is transposed by transpose buffer390before they are fed into the two pipelines.

To build a vertical filter for multiple video standards, a common vertical filter equation is formed by merging multiple filter equations. Vertical filter equations of the video standards are 2-tap (bilinear), 4-tap (bicubic), 6-tap and 8-tap. Each one of the vertical filter equations is displayed below.

r is mux(0,2,4);

h is mux(0,1,2,4);

t is mux(0,1,2);

q is mux(0,4);

u is mux(0,1,2);

v is mux(2,4);

v is mux(2,4);

w is mux(0,1);

s is mux(3,5,6,0);

The common vertical filter equation obtained can be realized by shifters, adders, subtracters and multiplexers.FIG. 4illustrates example architecture of vertical filters120,220,340and370, which is a realization of the common vertical filter equation.

Similarly, a common horizontal filter equation is obtained by merging horizontal filter equations of multiple video standards. The filter equations are shown below.

By merging the horizontal filter equations, the common horizontal filter equation is obtained as shown below.
H=Clip1((r*(h+t)*(a[0]+a[1])−(w+u)*(a[2]+a[3])+v*(p*a[4]+w*a[5])+a[6]+a[7]+frnd( )>>s)

The common horizontal filter equation can also be realized by shifters, adders, subtracters and multiplexers.FIG. 5illustrates example architecture of horizontal filters140,170,240,270and320which is a realization of the common horizontal filter equation.

Horizontal filters170and270can be used for H264 standard only. Therefore, the architecture in such case need only to realize 6-tap horizontal filter equation to limit the logic used and area occupied.

Filter indicators110,210and310provide information needed for vertical filters120,220,340and370; horizontal filters140,170,240,270and320; and output units180,280and380during each pipeline stage. Filter indicators110,210and310have the same stage number so that the corresponding information is fed into each stage of each filter or output unit. The information is also transferred to the next stage like a pipeline.

FIG. 6illustrates a simplified block diagram of a motion compensation unit600according to another embodiment of the present invention. Motion compensation unit600comprises an interpolation unit610, a discrete cosine transform (DCT) unit620, a quantization unit630, an inverse quantization unit640and an inverse DCT unit650. Input data and reference data are fed into interpolation unit610. Data after interpolation is then transformed by DCT unit620before being fed into quantization unit630for quantizing. Quantized data is output for further processing. A motion vector is also output by interpolation unit610also for further processing. Inverse quantization unit640and inverse DCT unit650form a feedback track, so that output data undergo inverse quantization and inverse DCT before being fed back to become the reference data. Motion compensation unit600is able to facilitate multiple video standards by applying interpolation unit610with interpolation units100,200and300described above. Therefore, a multiple video standard motion compensation unit is achieved without sacrificing chip area requirements.

FIG. 7illustrates a simplified block diagram of a decoder700according to another embodiment of the present invention. Decoder700comprises an inverse DCT unit710, an inverse quantization unit720, a frame memory730and a motion compensation unit740. Input data, i.e. compressed data, is inversely transformed by inverse DCT unit710and subsequently inversely quantized by inverse quantization unit720. Motion compensation factors output from motion compensation unit740are added to after inverse quantization. Output data is fed into motion compensation unit740through frame memory730, and motion compensation unit740outputs motion compensation factors to be added to the next frame. Decoder700is able to facilitate multiple video standards by applying motion compensation unit740with motion compensation unit600described above. Therefore, a multiple video standards decoder is achieved without sacrificing chip area requirements.

EXAMPLE

The prediction values for the chroma component in H.264 are always obtained by bilinear interpolation, as shown inFIG. 8, the positions labeled with A, B, C, and D represent chroma samples at full-sample locations inside the given two-dimensional array of chroma samples, and the sample values at sub-sample positions labeled as P are derived as follows:
P=(8−xFrac)*((8−yFrac)*A+yFrac*C)+xFrac*((8−yFrac)*B+yFrac*D)+32)>>6

In the proposed architecture, the vertical filter would calculate
((8−yFrac)*A+yFrac*C) and ((8−yFrac)*B+yFrac*D),

and then horizontal filter would accomplish the next calculation for P.

Filter parameters are passed along the pipeline, and are used to control the parameters in vertical/horizontal filters together with the selector at the end of the pipeline, which contains multiplexers and averagers.

The above architecture accomplishes 2D interpolation in one unified method for multi-standard motion compensation. While consuming a small area, this simple and unified architecture of 2D interpolation, could achieve the same performance as the separated design, and thus meet the performance requirement of video standards. In view of hardware realization of the original algorithm, the improvement is significant.