Semiconductor device and manufacturing method thereof

This invention is directed to offer a package type semiconductor device that can realize a smaller size device and its manufacturing method as well as a small stacked layer type semiconductor device and its manufacturing method. A device component 1 and a pad electrode 4 electrically connected with the device component 1 are formed on a semiconductor substrate 2. A supporting member 7 is bonded to a surface of the semiconductor substrate 2 through an adhesive layer 6. There is formed a through-hole 15 in the supporting member 7 penetrating from its top surface to a back surface. Electrical connection with another device is made possible through the through-hole 15. A depressed portion 12 is formed in a partial region of the top surface of the supporting member 7. Therefore, all or a portion of another device or a component can be disposed utilizing a space in the depressed portion 12. When a stacked layer type semiconductor device is formed, stacking is made by fitting a portion of a semiconductor device 50 in an upper layer to an inside of the depressed portion 12.

REFERENCE TO RELATED APPLICATIONS

This application is a national stage application under 35 USC 371 of International Application No. PCT/JP2007/065575, filed Aug. 2, 2007, which claims priority from Japanese Patent Application No. 2006-220100, filed Aug. 11, 2006, the contents of which are incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates to a semiconductor device, specifically to a package type semiconductor device and its manufacturing method.

DESCRIPTION OF THE RELATED ART

A CSP (Chip Size Package) has received attention in recent years as a new packaging technology. The CSP means a small package having about the same outside dimensions as those of a semiconductor die.

A BGA (Ball Grid Array) type semiconductor device has been known as a kind of CSP. The BGA type semiconductor device is provided with a plurality of ball-shaped conductive terminals that are electrically connected with pad electrodes disposed on a semiconductor substrate.

When the BGA type semiconductor device is mounted on electronic equipment, the semiconductor die is electrically connected with an external circuit on a printed circuit board by bonding the conductive terminals to wiring patterns on the printed circuit board.

Such BGA type semiconductor devices are widely used because they have advantages in providing a large number of conductive terminals and in reducing size over other CSP type semiconductor devices such as an SOP (Small Outline Package) and a QFP (Quad Flat Package), which have lead pins protruding from their sides.

FIG. 16is a cross-sectional view showing an outline structure of a conventional BGA type semiconductor device110. A device component101such as a CCD (Charge Coupled Device) type image sensor or a CMOS type image sensor is formed in a top surface of a semiconductor substrate100made of silicon or the like, and a pad electrode102is formed in addition through a first insulation film103. A glass substrate104, for example, is bonded to the top surface of the semiconductor substrate100through an adhesive layer105made of epoxy resin or the like. A second insulation film106made of a silicon oxide film or a silicon nitride film is formed on a side surface and a back surface of the semiconductor substrate100.

A wiring layer107electrically connected with the pad electrode102is formed on the second insulation film106. The wiring layer107is formed over the side surface and the back surface of the semiconductor substrate100. A protection layer108made of solder resist or the like is formed to cover the second insulation film106and the wiring layer107. Openings are formed in the protection film108on the wiring layer107at predetermined regions, and there are formed ball-shaped conductive terminals109electrically connected with the wiring layer107through the openings.

The technology mentioned above is disclosed in Japanese Patent Publication No. 2005-072554, for example.

The device incorporating the package type semiconductor device as described above is required to reduce its thickness and size as a whole.

When a stacked layer structure of completed semiconductor devices is implemented, it is also required to reduce a height of the stacked structure as much as possible to reduce size of the device as a whole. When the stacked layer type semiconductor device is formed by stacking a plurality of conventional semiconductor devices, however, there is a problem that the device as a whole becomes too large.

SUMMARY OF THE INVENTION

Thus, this invention is directed to offering a package type semiconductor device that can realize a reduced size device and its manufacturing method as well as a small stacked layer type semiconductor device and its manufacturing method.

This invention is directed to solving the problems addressed above and has following features. A semiconductor device of this invention is characterized by having a semiconductor substrate on a top surface of which an electronic component is formed, a supporting member a back surface of which faces the semiconductor substrate and is bonded to the semiconductor substrate through an adhesive layer and an electrode formed below the supporting member and electrically connected with the electronic component, wherein a depressed portion is formed in a partial region of a top surface of the supporting member.

Also, the semiconductor device of this invention is characterized by that there is formed a through-hole penetrating through the supporting member from the top surface to the back surface and that the electrode can be electrically connected with an electrode of another device through the through-hole.

Also, a semiconductor device of this invention is characterized by comprising a semiconductor substrate on a top surface of which an electronic component is formed, a supporting member a back surface of which faces the semiconductor substrate and is bonded to the semiconductor substrate through an adhesive layer, an electrode formed below the supporting member and electrically connected with the electronic component and a plurality of through-holes penetrating from a top surface of the supporting member to the back surface, wherein the plurality of through-holes comprises a through-hole that is provided in its hole with a first conductive terminal electrically connected with the electrode and a through-hole that is not provided with the first conductive terminal and is used to house a portion or all of another device.

Also, a semiconductor device of this invention is a stacked layer type semiconductor device that is formed by stacking a plurality of semiconductor devices, each of which comprises a semiconductor substrate on a top surface of which an electronic component is formed and a supporting member bonded to the surface of the semiconductor substrate through an adhesive layer, and is characterized by that the supporting member in the semiconductor device in a lower layer has a depressed portion or a through-hole in a partial region of its top surface and that all or a portion of the semiconductor device in an upper layer is housed in the depressed portion or in the through-hole.

Also, the semiconductor device of this invention is characterized by that the supporting member of the semiconductor device in the lower layer has a through-hole for connection with the electrode and that the semiconductor device in the lower layer is electrically connected with the semiconductor device in the upper layer through a conductive material formed in the through-hole for connection with the electrode.

Also, a manufacturing method of a semiconductor device of this invention is characterized by comprising providing a semiconductor substrate on a top surface of which an electronic component and an electrode electrically connected with the electronic component are formed, a process step to bond a supporting member to the top surface of the semiconductor substrate through an adhesive layer and a process step to form a depressed portion in a partial region of a top surface of the supporting member.

Also, the manufacturing method of the semiconductor device of this invention is characterized by comprising a process step to form a through-hole penetrating through the supporting member from its top surface to its back surface so as to expose a top surface of the electrode on a side of the supporting member and a process step to form a first conductive terminal electrically connected with the electrode.

Also, a manufacturing method of a semiconductor device of this invention is a method to manufacture a stacked layer type semiconductor device including a process step to vertically stack a plurality of semiconductor devices each of which comprises a semiconductor substrate on a top surface of which an electronic component and an electrode electrically connected with the electronic component are formed and a supporting member bonded to the top surface of the semiconductor substrate through an adhesive layer, and characterized by comprising a process step to form a depressed portion or a through-hole in a partial region of a top surface of the supporting member of the semiconductor device that makes a lower layer and a process step to stack an upper layer semiconductor device and the lower layer semiconductor device by housing all or a portion of the upper layer semiconductor device in the depressed portion or in the through-hole in the supporting member.

In this invention, the depressed portion or the through-hole is formed in the top surface of the supporting member that is bonded to the semiconductor substrate. As a result, all or a portion of another device or a component can be disposed utilizing a space in the depressed portion or the through-hole to reduce a thickness and a size of the device as a whole.

Also, the stacked layer type semiconductor device smaller than the conventional one can be obtained by using the semiconductor device having the depressed portion or the through-hole formed in its supporting member and by stacking so that all or a portion of the semiconductor device in the upper layer semiconductor device is housed in the depressed portion or the through-hole in the supporting member of the lower layer semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

A first embodiment of this invention will be explained hereafter referring to the drawings.FIG. 1throughFIG. 7are plan views and cross-sectional views presented in the order of manufacturing process steps.

First, as shown inFIG. 1, there is provided a semiconductor substrate2, made of silicon (Si) or the like, on a top surface of which a device component1(a CCD, a light-receiving component such as an infrared sensor, a light-emitting component or other semiconductor component, for example) is formed. The semiconductor substrate2is about 300-700 μm thick, for example. A first insulation film3(a silicon oxide film formed by thermal oxidation or CVD, for example) of a thickness of 2 μm, for example, is formed on the top surface of the semiconductor substrate2.

Next, a metal layer made of aluminum (Al), aluminum alloy or copper (Cu), for example, is formed by a sputtering method, a plating method or other film forming method, and thereafter the metal layer is etched using a resist layer (not shown) as a mask to form pad electrodes4of a thickness of 1 μm, for example, on the first insulation film3. The pad electrodes4make electrodes for external connections, which are electrically connected with the device component1and its peripheral component through interconnections (not shown). Although the pad electrodes4are disposed on both sides of the device component1inFIG. 1, their locations are not restricted and they may be disposed above the device component1.

Next, a passivation film5(a silicon nitride film formed by CVD, for example) that covers all or a portion of the pad electrode4is formed over the top surface of the semiconductor substrate2. The passivation film5shown inFIG. 1is formed so as to cover a portion of the pad electrode4.

Next, a supporting member7is bonded to top the surface of the semiconductor substrate2including the pad electrodes4through an adhesive layer6made of epoxy resin, polyimide (photosensitive polyimide, for example), resist, acryl or the like. Out of surfaces of the supporting member7, a principal surface facing the semiconductor substrate2is called a back surface, and another principal surface on the opposite side is called a top surface. The supporting member7may be a film-shaped protection tape, may be a rigid substrate made of glass, quartz, ceramics, metal or the like, or may be made of resin. It is preferable that the supporting member7is a rigid substrate for the purpose of firmly supporting the semiconductor substrate2that is to be reduced in thickness and accommodating hands-free automatic transfer. The supporting member7has a function of supporting the semiconductor substrate2as well as protecting a surface of the component. When the device component1is a light-receiving component or a light-emitting component, the supporting member7is to be made of a transparent or semitransparent material to permit light to pass through.

Next, back grinding using a back surface grinding apparatus (grinder) is applied to a back surface of the semiconductor substrate2to reduce the thickness of the semiconductor substrate2to a predetermined thickness (50 μm, for example). The back grinding may be replaced with etching, or with a combination of grinding and etching. The back grinding is not required in some cases, depending on usage or specifications of the finished product or an initial thickness of the semiconductor substrate2being provided.

Next, predetermined regions of the semiconductor substrate2corresponding to the pad electrodes4are selectively etched off from a side of the back surface of the semiconductor substrate2to expose portions of the first insulation film3, as shown inFIG. 2. The exposed portions are hereafter referred to as openings8.

The selective etching of the semiconductor substrate2is explained referring toFIGS. 3A and 3B.FIGS. 3A and 3Bare brief plan views looked from below (from a side of the semiconductor substrate2).FIG. 2corresponds to a cross-sectional view of a section X-X inFIGS. 3A and 3B.

The semiconductor substrate2may be etched to a shape which is roughly a rectangle that is narrower than a width of the supporting member7, as shown inFIG. 3A. Or, the semiconductor substrate2may be shaped to have a rugged periphery by etching off the semiconductor substrate2only from regions, in which the pad electrodes4are formed, as shown inFIG. 3B. The latter has larger overlapping area between the semiconductor substrate2and the supporting member7, and leaves the semiconductor substrate2extended closer to a periphery of the supporting member7. Therefore, a structure of the latter is more preferable in terms of enhancing the strength of the supporting member7to bolster the semiconductor substrate2. Also, cracks and separation of the semiconductor substrate2can be prevented since warping of the supporting member7due to a difference in a coefficient of thermal expansion between the semiconductor substrate2and the supporting member7can be prevented with the latter structure. It is also possible to design the semiconductor substrate2in a shape different from either of the planar shapes shown inFIGS. 3A and 3B.

Although the semiconductor substrate2is etched in a way that sidewalls of the semiconductor substrate2are tapered so that a width of the semiconductor substrate2is increased toward the top surface in this embodiment, the semiconductor substrate2may also be etched in a way that the sidewalls of the semiconductor substrate2are perpendicular to a principal surface of the supporting member7to keep the width of the semiconductor substrate2constant.

Next, the first insulation film3is selectively etched using the semiconductor substrate2as a mask, as shown inFIG. 4. The first insulation film3in a region between an edge of the semiconductor substrate2and a predetermined dicing line is removed by the etching to expose a surface (a surface of the side of the semiconductor substrate2) of the pad electrode4at a bottom of the opening8. A resist layer may be formed to be used as the mask in the etching.

Next, a metal layer9is formed on the exposed surface of the pad electrode4, as shown inFIG. 5. The metal layer9is made of stacked layers of a nickel (Ni) layer and a gold (Au) layer, for example, and is formed by a lift-off method, that is, sputtering these metals sequentially using a resist layer as a mask followed by removing the resist layer, or by a plating method.

The materials to form the metal layer9may be modified as appropriate. That is, the metal layer9may be made of a titanium (Ti) layer, a tungsten (W) layer, a copper (Cu) layer, a tin (Sn) layer or the like, other than the nickel layer and the gold layer. The metal layer9may be made of any material as long as the material has functions to electrically connect the pad electrode4with a conductive terminal25, which is to be described, or with an electrode of another device and to protect the pad electrode4, and may be made of a single layer or stacked layers. Examples of the stacked layers are nickel/gold layers, titanium/nickel/copper layers, titanium/nickel-vanadium/copper layers and the like.

Next, portions of the supporting member7are removed from the side of the semiconductor substrate2by a dicing blade or etching to form V-shaped grooves (notches)10along the dicing lines DL. In some cases, the V-shaped grooves10are not formed.

Next, there is formed a protection layer11of a thickness of 10 μm, for example, having openings at locations corresponding to the pad electrode4and the metal layer9. The opening is formed on a principal surface of the pad electrode4on the side of the semiconductor substrate2.

The protection layer11is formed as described below, for example. First, an organic material such as polyimide resin, solder resist or the like is applied over the entire surface by a coating method and a thermal treatment (pre-bake) is performed. Then, the applied organic material is exposed to light and developed to form the openings that expose a surface of the metal layer9. After that, another thermal treatment (post-bake) is performed to obtain the protection layer11having the openings at the locations corresponding to the pad electrode4and the metal layer9. When the V-shaped grooves10are formed, portions (side surface) of the supporting member7are also covered with the protection layer11. As a result, infiltration of corrosive material is reduced.

Next, a depressed portion12that is roughly horizontal at its bottom is formed in a partial region of the top surface of the supporting member7, as shown inFIG. 6. To be more specific, a resist layer (not shown) having an opening in the region where the depressed portion12is to be formed is formed on the supporting member7, and the top surface of the supporting member7is dry-etched in the direction of thickness using the resist layer as a mask to form the depressed portion12, for example. Or, the depressed portion12may be formed by removing the top surface of the supporting member7by laser irradiation, wet etching or micro-blasting. The micro-blasting is a method to process an object by blasting the object with fine particles of alumina, silica or the like. The depressed portion12does not penetrate through the supporting member7and its bottom is located partway through the thickness of the supporting member7.

Although a depth, a width and a horizontal shape of the depressed portion12are arbitrary, it is preferable for obtaining a stacked layer type semiconductor device of a minimum size that the depressed portion12is formed so that all of the semiconductor substrate2including the protection layer12is housed in the depressed portion12. This point will be explained later.

Also, as will be explained later, since an electronic device (a MEMS component, for example) or a component (a filter or a lens, for example) can be also disposed on the bottom of the depressed portion12utilizing its space, the depth, the width and the like of the depressed portion12are adjusted to what is disposed there in that case.

Next, through-holes15that penetrate through the supporting member12and expose the pad electrodes4from a side of the supporting member7are formed at locations corresponding to the pad electrodes4in regions where the depressed portion12is not formed. To be more specific, a resist layer (not shown) that has openings in the regions where the through-holes15are to be formed is formed on the supporting member7. Then, the supporting member7is selectively etched using the resist layer as a mask to expose the adhesive layer6, followed by etching of the adhesive layer6to form the through-holes15. The through-holes15may be formed by dip-etching using hydrofluoric acid (HF) as an etching solution. Or, the through-holes15may be formed by dry-etching, laser irradiation, micro-blasting or the like.

The through-hole15is roughly a square in shape with each side of about 100 μm, for example, when looked from above. In this embodiment, the through-hole15is formed in a region that is displaced toward inside by a predetermined distance from the dicing line DL. As a result, a periphery of the through-hole15is surrounded by the supporting member7after dicing. The through-hole15may also be formed adjacent the dicing line DL so that it is exposed to outside of the supporting member7after the dicing.

Next, a metal layer16is formed on the pad electrode4exposed at the bottom of the through-hole15(on a surface of the pad electrode4on the side of the supporting member7). The metal layer16is similar in the structure to the metal layer9that has been described previously, and is made of a nickel (Ni) layer and a gold (Au) layer stacked consecutively, for example. As a result, each of the metal layers9and16is formed on each of two principal surfaces of the pad electrode4, respectively.

Next, a conductive material (solder, for example) is screen-printed on the metal layer16in the through-hole15, and conductive terminals17are formed by subsequent thermal treatment to reflow the conductive material, as shown inFIG. 7. The conductive terminals17are formed at locations corresponding to the pad electrodes4along the periphery of the supporting member7. Also, the conductive terminals17are formed to be higher than a height of the supporting member7and make electrodes protruding in a vertical direction from the top surface-side of the supporting member7. Mounting after completion is made easier by making the conductive terminals17protruding from the top surface-side of the supporting member7as described above. In the case where the pad electrodes4are formed above the device component1, the through-holes15and the conductive terminals17may be formed in regions overlapping with the semiconductor substrate2.

The conductive terminal17is not limited to being formed by the method described above, and may be formed by an electrolytic plating method using the metal layer16as a plating electrode or by a so-called dispense method (coating method) in which the solder or the like is applied using a dispenser. Also, the conductive terminal17may be made of gold, copper or nickel, and its material is not specifically limited.

Next, the supporting member7is cut along the dicing lines DL and separated into individual semiconductor devices50. The method to separate into the individual semiconductor devices50includes a dicing method, an etching method, a laser cutting method and the like.

The completed semiconductor device50is mounted on another device on which external electrodes are formed in a pattern. For example, the conductive terminals17are directly connected to external electrodes21on a circuit board20such as a printed circuit board, as shown inFIG. 8. Although not shown in the drawing, there are cases in which the conductive terminal17is indirectly connected with an electrode of another device through a conductive material such as a bonding wire, a wiring or the like. In the case where protruding electrodes are formed in the other device, the connection may be made without forming the conductive terminals17and by placing the protruding electrode of the other device in the through-hole15as if the protruding electrode is buried in the through-hole15. Also, the metal layer9may be connected with the electrode of the other device.

Since the depressed portion12is formed in the top surface of the supporting member7in the structure, there is a free space22above the bottom surface of the depressed portion12. Therefore, a device in which the semiconductor device50is mounted can be reduced as a whole in thickness as well as in size, by utilizing the space22in the depressed portion12. When the device component1is a light-receiving component, for example, the device as a whole can be reduced in size by disposing a filter material (a color filter or a filter that allows only specific wavelength of light to pass through, for example) or a lens on the bottom of the depressed portion12.

It is also possible to dispose an electronic device such as a MEMS (Micro Electro Mechanical Systems) component on the bottom of the depressed portion12. The MEMS means a device in which a mechanical component, a sensor, an actuator and an electronic circuit are integrated on a semiconductor substrate.

InFIG. 8, the adhesive layer6is partially formed and a cavity23is formed between the supporting member7and the semiconductor substrate2. The cavity23is formed by applying a material to form the adhesive layer6in a ring-shape on the semiconductor substrate2, for example.

Also, there is a case in which a conductive terminal25is formed on the metal layer9exposed in the opening in the protection layer11, as shown inFIG. 9. The conductive terminal25has the similar composition to the conductive terminal17described previously, and is made of solder or gold, for example. Also, the conductive terminal25may be formed by the screen-printing method, the plating method or the dispense method, as in the case of the conductive terminal17. The conductive terminals25are formed in a semiconductor device51, as shown inFIG. 9.

The semiconductor device51may be mounted through the conductive terminals25on a circuit board on which external electrodes are formed in a pattern. For example, the conductive terminals25are directly connected to external electrodes27on a circuit board26such as a printed circuit board, as shown inFIG. 9. Although not shown in the drawing, there are cases in which the conductive terminal25is indirectly connected with an external electrode through a conductive material such as a bonding wire or a wiring.

The wiring layer107and the second insulation film16extended over the side surface and the back surface of the semiconductor substrate in the conventional semiconductor device (FIG. 16) are not formed in the semiconductor devices50and51. The reason is that it is preferable in terms of simplifying the manufacturing process to improve the productivity as well as suppressing the manufacturing cost compared with the structure in which the wiring layer and the insulation film are formed.

When the conductive terminals25are formed, it is preferable to form the conductive terminal25at neighboring outside of the sidewall of the semiconductor substrate2, as shown in the semiconductor device51inFIG. 9. It is because the semiconductor device can be reduced in thickness and size compared with the case in which the conductive terminals are formed on the back surface of the semiconductor substrate as in the conventional semiconductor device (FIG. 16).

Next, a stacked layer type semiconductor device in which a plurality of the completed semiconductor devices is vertically stacked will be explained referring to the drawings. The same components as those shown in the preceding drawings are denoted by the same symbols, and explanations on them are omitted or simplified.

FIG. 10is a cross-sectional view showing a stacked layer type semiconductor device60in which one semiconductor device51, two semiconductor devices50and one semiconductor device52are stacked in the order as mentioned. The semiconductor device52has the same structure as the semiconductor device50except that the depressed portion12, the through-hole15and the conductive terminal17are not formed in the supporting member7.

The stacked layer type semiconductor device60is manufactured by a process described bellow after each of the semiconductor devices50,51and52are completed. In order to obtain the stacked layer type semiconductor device of the minimum size, the width and the depth of the depressed portion12is adjusted so that all of the semiconductor substrate2including the protection layer11of the upper layer semiconductor device can be practically housed inside of the depressed portion12.

First, the completed semiconductor devices (51,51and52) are superposed onto each other so that each of the conductive terminals17is aligned to corresponding each of the metal layers9, respectively. The upper layer semiconductor device is superposed onto the lower layer semiconductor device and fixed to it so that a portion of the upper layer semiconductor device is closely fitted into the space in the depressed portion12of the lower layer semiconductor device. And the stacked layer structure is completed by connecting the conductive terminals17with the metal layers9by a thermo-compression bonding method, for example. In the stacked layer type semiconductor device60, the conductive terminals25of the semiconductor device51in the lowest layer are directly connected with the external electrodes62on the circuit board61, for example.

In the stacked layer type semiconductor device according to this embodiment, the upper layer semiconductor device is electrically connected with the lower layer semiconductor device through the through-holes15provided in the supporting member7, as described above. In addition, the portion of the upper layer semiconductor device is housed in the depressed portion12that is formed in the supporting member7. As a result, a height of the stacked layer structure can be minimized.

The larger the number of layers in the stacked layer structure is, the greater the effect of the reduction in the thickness is. For example, when the thickness of the supporting member7is 100 μm and the thickness of the semiconductor substrate2is 50 μm, a total thickness of four layers of the conventional structure (FIG. 16) is about 600 (100×4+50×4) μm at least. On the other hand, when four layers are stacked in the structure of the embodiment, its total thickness is about 450 (100×4+50×1) μm.

Also, workability and efficiency are high because the semiconductor devices50,51and52are ready to be stacked as soon as they are completed.

In addition, a manufacturing cost can be suppressed while productivity is improved, because process steps to form the wiring layer107and the second insulation film106that are required in the conventional art are not necessary in the embodiment. Furthermore, since the top surface of the semiconductor substrate2is protected with the supporting member7, the device component1and its peripheral components formed on the top surface are prevented from deterioration, and reliability of the semiconductor device can be enhanced.

Next, a second embodiment of this invention will be explained referring to the drawings. The same structures as those already explained are denoted by the same symbols and explanations on them are omitted.FIG. 11is a cross-sectional view showing a semiconductor device65according the second embodiment of this invention.

In the first embodiment, the depressed portion12is formed in the partial region of the top surface of the supporting member7. In the second embodiment, on the other hand, it is characteristic of it that a through-hole66penetrating through the supporting member7from the top surface to the back surface is formed in a partial region of the supporting member7. The through-hole66is different from the through-hole15that serves for electrically connection with another device, and offers a space to house all or a portion of another device.

The through-hole66for housing is formed by process steps similar to the process steps to form the depressed portion12in the first embodiment, for example. It may be formed simultaneously with the through-hole15. To be more specific, it is formed by forming a resist layer on the supporting member7in a region where the through-hole66is to be formed, and dry-etching the top surface of the supporting member7in the direction of thickness using the resist layer as a mask, for example. Or, it may be formed by removing the top surface of the supporting member7by laser irradiation, wet etching or micro-blasting. A partial region of the adhesive layer6is exposed to outside by forming the through-hole66.

Although not shown in the drawing, the exposed portion of the adhesive layer6may be removed after the through-hole66is formed. Or, the adhesive layer6may be formed at the time of its formation so that the adhesive layer6is not formed in the region where the through-hole66is to be formed. In some cases, operation quality of the semiconductor device is improved by not forming the adhesive layer6on the device component1. When the device component is a light-receiving component or a light-emitting component, for example, its operation quality is improved because of the absence of unnecessary intervening material.

A stacked layer structure as shown inFIG. 12can be formed by forming the through-holes66in the supporting member7as described above.FIG. 12is a cross-sectional view showing a stacked layer type semiconductor device69in which one semiconductor device67, two semiconductor devices65and one semiconductor device68are stacked in the order as mentioned. The semiconductor device67has the same structure as the semiconductor device65except that the conductive terminals25are formed. The semiconductor device68has the same structure as the semiconductor device65except that the through-hole66, the through-hole15and the conductive terminal17are not formed in the supporting member7.

Therefore, a device in which the semiconductor devices are mounted or stacked can be reduced as a whole in thickness as well as in size, by utilizing the space in the through-hole66.

This invention is not limited to the embodiments described above and may be modified within the scope of the invention.

For example, although the through-holes15, the metal layers16and the conductive terminals17are formed in the supporting member7at the locations corresponding to the pad electrodes4, the locations are not limited to the above and they may be formed at any locations as long as they could serve as the connections with the electrodes of another device disposed above the semiconductor device.

The depressed portion12and the through-hole66may be formed into any shape. Also, a plurality of them may be formed. Therefore, stacking semiconductor devices different from each other in function or size is also possible. The upper layer device is not necessarily fitted tightly into the depressed portion12or the through-hole66, and there may be a space between them. When the semiconductor devices different in size from each other are stacked, they can be stacked so that all of the upper layer semiconductor device is housed in the depressed portion12or in the through-hole66.

Although an edge of the semiconductor substrate2and an edge of the pad electrode4are apart from each other in the explanation described above, it is also possible to etch the semiconductor substrate2so that the edge of the pad electrode4is disposed on a portion of the top surface of the semiconductor substrate2.

Also, the surface of the supporting member7facing the semiconductor substrate2, that is, the surface opposite to the surface on which the depressed portion12is formed, may be processed by etching, laser beam irradiation, micro-blasting or the like to form a depressed portion70, as shown inFIG. 13. In this case, however, careful attention has to be paid to the process so that the supporting member7would not be destroyed by making the depressed portion70and the depressed portion12contiguous, for example. By forming the depressed portion70in the surface facing the semiconductor substrate2, the space between the semiconductor substrate2and the supporting member7in the region where the depressed portion70is formed can be extended. InFIG. 13, the adhesive layer6is formed not uniformly but partially, and a cavity71is formed between the supporting member7and the semiconductor substrate2. It is also possible to form a MEMS component72on the semiconductor substrate2through the insulation film3utilizing the cavity71. At that time, the MEMS component72can be electrically connected with the pad electrode4through a wiring.

It is also possible that a depressed portion73as shown inFIG. 14is formed in the top surface of the semiconductor substrate2by etching, laser beam irradiation or the like and that various components including the MEMS component are formed on a bottom surface of the depressed portion73. A thicker device can be formed on the semiconductor substrate2in the structure described above compared with the structure in which the depressed portion73is not formed in the semiconductor substrate2, since the space between the semiconductor substrate2and the supporting member7is extended by a height of a step of the depressed portion73. It is also possible to freely adjust the space between the supporting member7and the semiconductor substrate2by combining an adjustment to the height of step of the depressed portion73with an adjustment to the thickness of the adhesive layer6and the depressed portion70in the back surface of the supporting member7.

Note thatFIG. 13andFIG. 14show the structure in which the metal layer9is not formed and the protection layer11covers the pad electrodes4.

Also, openings80may be formed as shown inFIG. 15by changing the etching pattern of the semiconductor substrate2and the locations of the dicing lines. The openings80are surrounded by the semiconductor substrate2. The conductive terminals25are formed in the openings80. The conductive terminals25in a semiconductor device85according to a modified example are exposed to a back surface-side of the semiconductor device85but not exposed to a side surface-side. As a result, infiltration of contaminating material and mechanical damage are reduced to improve the reliability of the semiconductor device. Although not shown in the drawing, it is possible as a matter of course that the through-hole15or the through-hole66is formed in the supporting member7in the structure having the openings80shown inFIG. 15. It is also possible to form a stacked layer type semiconductor device as shown inFIG. 10andFIG. 12using the semiconductor device85.

Although BGA (Ball Grid Array) type semiconductor devices are explained in the explanations described above, this invention may be applied to LGA (Land Grid Array) type semiconductor devices, other CSP type semiconductor devices and flip chip type semiconductor devices.