Microelectronic devices with active source/drain contacts in trench in symmetrical dual-block structure, and related systems and methods

Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

TECHNICAL FIELD

Embodiments of the disclosure relate to the field of microelectronic device design and fabrication. More particularly, the disclosure relates to microelectronic devices (e.g., memory devices, such as 3D NAND memory devices) having a tiered stack of vertically alternating conductive structures and insulative structures, slits dividing the tiered stack into dual-block structures, and a series of stadiums defined in each block of the dual-block structure. The disclosure also relates to methods for forming such devices and to systems incorporating such devices.

BACKGROUND

Memory devices provide data storage for electronic systems. A Flash memory device is one of various memory device types and has numerous uses in modern computers and other electrical devices. A conventional Flash memory device may include a memory array that has a large number of charge storage devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In a NAND architecture type of Flash memory, memory cells arranged in a column are coupled in series, and a first memory cell of the column is coupled to a data line (e.g., a bit line). In a “three-dimensional NAND” memory device (which may also be referred to herein as a “3D NAND” memory device), a type of vertical memory device, not only are the memory cells arranged in row and column fashion in a horizontal array, but tiers of the horizontal arrays are stacked over one another (e.g., as vertical strings of memory cells) to provide a “three-dimensional array” of the memory cells. The stack of tiers vertically alternate conductive materials with insulating (e.g., dielectric) materials. The conductive materials function as control gates for, e.g., access lines (e.g., word lines) of the memory cells. Vertical structures (e.g., pillars comprising channel structures and tunneling structures) extend along the vertical string of memory cells. A drain end of a string is adjacent one of the top and bottom of the vertical structure (e.g., pillar), while a source end of the string is adjacent the other of the top and bottom of the pillar. The drain end is operably connected to a bit line, while the source end is operably connected to a source line. A 3D NAND memory device also includes electrical connections between, e.g., access lines (e.g., word lines) and other conductive structures of the device so that the memory cells of the vertical strings can be selected for writing, reading, and erasing operations.

One method of forming such electrical connections includes forming a so-called “staircase” structure having “steps” (or otherwise known as “stairs”) at edges (e.g., adjacent ends) of the tiers of the stack structure. The steps define contact regions of conductive structures of the device, such as access lines (e.g., word lines), which may be formed by the conductive materials of the tiered stack. Contact structures may be formed in physical contact with the steps to provide electrical access to the conductive structures (e.g., word lines) associated with the steps. The contact structures may be in electrical communication, via conductive routing lines, to additional contact structures that communicate to a source/drain region.

Continued goals in the microelectronic device fabrication industry are to scale device features to smaller sizes while increasing device density and increasing “efficiency” (e.g., the percentage of a device's horizontal footprint that is occupied by “active” features of the device, namely, features with active involvement in writing, reading, or erasing operations). As features are scaled to increase device density, reliable and consistent fabrication of the features generally becomes more challenging, and reduced feature sizes tend to present challenges to fabrication and to maintaining sufficient performance characteristics of the device. For example, efforts to scale device features may negatively impact other aspects of device design and fabrication, such as the fabrication of relatively-small features leading to structure bending during fabrication, which may negatively impact subsequent fabrication stages and performance characteristics. Accordingly, designing and fabricating microelectronic devices, such as 3D NAND memory devices, with decreased feature sizes, increased device density, and increased efficiency and without negative impacts to fabrication (e.g., structure bending) and device performance continues to present challenges.

DETAILED DESCRIPTION

Structures (e.g., microelectronic device structures), apparatuses (e.g., microelectronic devices), and systems (e.g., electronic systems), according to embodiments of the disclosure, include a stack of vertically alternating conductive structures and insulative structures arranged in tiers and with slit structures dividing the stack into a series of dual-block structures. A series of opposing stadiums is formed in the dual-block structures. The stadiums include staircase structures having steps defined by ends (e.g., surfaces adjacent sidewalls) of at least some of the conductive structures of the tiers of the stack. The dual-block structures are substantially symmetrically structured about a trench that extends along a width of the series of stadiums, between opposing stadiums of the dual-block structures. “Active” source/drain contacts are positioned within the trench. The trench and the adjacent stadiums together form substantially a “T” shape, with the “stem” of the “T” provided by the trench between the opposing stadiums and with the “crossbars” (or “shoulders”) of the “T” provided by the steps of the staircases in the opposing stadiums. The substantial symmetrical design of the dual-block structures may be maintained during significant stages of fabrication to lessen or avoid material stress and/or strain imbalances that may otherwise cause block bending. By avoiding block bending, the features of the microelectronic device structure may be more reliably and consistently fabricated. Moreover, by locating the active source/drain contacts within the trench between opposing stadiums of a dual-block structure-rather than, e.g., within more distal areas like so-called “crests”—the distal areas may be formed to occupy a relatively smaller footprint, more active source/drain contacts may be included within a given block, and/or conductive routing lines communicating with the active source/drain contacts may be less crowded and less complex. In some embodiments, a “step drop” may be included on each side of the trench to effectively multiply (e.g., double) the number of opposing staircases and the number of step contacts included in a given stadium, which may enable additional device scaling by facilitating fewer stadiums in a dual-block structure without lessening the number of steps (e.g., the number of contactable conductive structures of the tiered stack).

As used herein, the term “active,” when used in reference to a contact or other conductive structure, means and includes a contact or other conductive structure configured to be functionally involved in at least one electrical or storage operation of features of the microelectronic device, such as electrical communication to other conductive component(s) and/or writing, reading, and/or erasing operations of the device. In contrast, a “non-active,” “support,” or “dummy” structure means and refers to a structure not functionally involved in at least one electrical or storage operation of features of the microelectronic device.

As used herein, a feature referred to with the adjective “source/drain” means and refers to the feature being configured for association with either or both the source region and the drain region of the device that includes the “source/drain” feature. A “source region” may be otherwise configured as a “drain region” and vice versa without departing from the scope of the disclosure.

As used herein, the term “opposing”—when referring to two features—means and includes the features facing one another from opposite directions. For example, “opposing staircases” may include a descending staircase and an ascending staircase with steps extending laterally toward one another and with the descending staircase descending toward a base of the ascending staircase. As another example, “opposing stadiums” may include stadiums with steps extending longitudinally toward one another from respective bridges.

As used herein, the terms “opening,” “trench,” “slit,” “recess,” and “void” mean and include a volume extending through or into at least one structure or at least one material, leaving a gap in that at least one structure or at least one material, or a volume extending between structures or materials, leaving a gap between the structures or materials. Unless otherwise described, an “opening,” “trench,” “slit,” and/or “recess” is not necessarily empty of material. That is, an “opening,” “trench,” “slit,” or “recess” is not necessarily void space. An “opening,” “trench,” “slit,” or “recess” formed in or between structures or materials may comprise structure(s) or material(s) other than that in or between which the opening is formed. And, structure(s) or material(s) “exposed” within an opening, trench, slit, or recess is/are not necessarily in contact with an atmosphere or non-solid environment. Structure(s) or material(s) “exposed” within an opening, trench, slit, or recess may be adjacent or in contact with other structure(s) or material(s) that is/are disposed within the opening, trench, slit, or recess. In contrast, unless otherwise described, a “void” may be substantially or wholly empty of material. A “void” formed in or between structures or materials may not comprise structure(s) or material(s) other than that in or between which the “void” is formed. And, structure(s) or material(s) “exposed” within a “void” may be in contact with an atmosphere or non-solid environment.

As used herein, the terms “trench” and “slit” mean and include an elongate opening, while the terms “opening,” “recess,” and “void” may include one or more of an elongate opening, an elongate recess, an elongate void, a non-elongate opening, a non-elongate recess, or a non-elongate void.

As used herein, the term “elongate” means and includes a geometric shape including a dimension (e.g., a width, as defined below) in a first horizontal direction (e.g., a lateral direction, as defined below) that is greater than an additional dimension (e.g., a length, as defined below) in a second horizontal direction (e.g., a longitudinal direction, as defined below) orthogonal to the first horizontal direction, or vice versa.

As used herein, the terms “substrate” and “base structure” mean and include a base material or other construction upon which components, such as those within memory cells, are formed. The substrate or base structure may be a semiconductor substrate, a base semiconductor material on a supporting structure, a metal electrode, or a semiconductor substrate having one or more materials, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates or silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si1-xGex, where x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), among others. Furthermore, when reference is made to a “substrate” or “base structure” in the following description, previous process stages may have been utilized to form materials, structures, or junctions in the base semiconductor structure, base structure, or other foundation.

As used herein, the terms “insulative” and “insulating,” when used in reference to a material or structure, means and includes a material or structure that is electrically insulative or electrically insulating. An “insulative” or “insulating” material or structure may be formed of and include one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)), and/or air. Formulae including one or more of “x,” “y,” and/or “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and/or “z” atoms of an additional element (if any), respectively, for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material or insulative structure may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including insulative material.

As used herein, the term “sacrificial,” when used in reference to a material or structure, means and includes a material or structure that is formed during a fabrication process but which is removed (e.g., substantially removed) prior to completion of the fabrication process.

As used herein, the term “horizontal” means and includes a direction that is parallel to a primary surface of the substrate on which the referenced material or structure is located. The “width” and “length” of a respective material or structure may be defined as dimensions in a horizontal plane. With reference to the figures, the “horizontal” direction may be perpendicular to an indicated “Z” axis, may be parallel to an indicated “X” axis, and may be parallel to an indicated “Y” axis.

As used herein, the term “lateral” means and includes a direction in a horizontal plane parallel to a primary surface of the substrate on which a referenced material or structure is located and substantially perpendicular to a “longitudinal” direction. The “width” of a respective material or structure may be defined as a dimension in the lateral direction of the horizontal plane. With reference to the figures, the “lateral” direction may be parallel to an indicated “X” axis, may be perpendicular to an indicated “Y” axis, and may be perpendicular to an indicated “Z” axis.

As used herein, the term “longitudinal” means and includes a direction in a horizontal plane parallel to a primary surface of the substrate on which a referenced material or structure is located, and substantially perpendicular to a “lateral” direction. The “length” of a respective material or structure may be defined as a dimension in the longitudinal direction of the horizontal plane. With reference to the figures, the “longitudinal” direction may be parallel to an indicated “Y” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Z” axis.

As used herein, the term “vertical” means and includes a direction that is perpendicular to a primary surface of the substrate on which a referenced material or structure is located. The “height” of a respective material or structure may be defined as a dimension in a vertical plane. With reference to the figures, the “vertical” direction may be parallel to an indicated “Z” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Y” axis.

As used herein, the term “width” means and includes a dimension, along an indicated “X” axis in a horizontal plane (e.g., at a certain elevation, if identified), defining a maximum distance, along such “X” axis in the horizontal plane, of the material or structure in question.

As used herein, the term “length” means and includes a dimension, along an indicated “Y” axis in a horizontal plane (e.g., at a certain elevation, if identified), defining a maximum distance, along such “Y” axis in the horizontal plane, of the material or structure in question.

As used herein, the terms “thickness” or “thinness” are spatially relative terms that mean and include a dimension in a straight-line direction that is normal to the closest surface of an immediately adjacent material or structure that is of a different composition or that is otherwise distinguishable from the material or structure whose thickness, thinness, or height is discussed.

As used herein, the term “between” is a spatially relative term used to describe the relative disposition of one material or structure relative to at least two other materials or structures. The term “between” may encompass both a disposition of one material or structure directly adjacent the other materials or structures and a disposition of one material or structure indirectly adjacent to the other materials or structures.

As used herein, the term “proximate” is a spatially relative term used to describe disposition of one material or structure near to another material or structure. The term “proximate” includes dispositions of indirectly adjacent to, directly adjacent to, and internal to.

As used herein, the term “neighboring,” when referring to a material or structure, is a spatially relative term that means and refers to a next, most proximate material or structure of an identified composition or characteristic. Materials or structures of other compositions or characteristics than the identified composition or characteristic may be disposed between one material or structure and its “neighboring” material or structure of the identified composition or characteristic. For example, a structure of material X “neighboring” a structure of material Y is the first material X structure, e.g., of multiple material X structures, that is most proximate to the particular structure of material Y. The “neighboring” material or structure may be directly adjacent or indirectly adjacent the structure or material of the identified composition or characteristic.

As used herein, the term “consistent”—when referring to a parameter, property, or condition of one structure, material, feature, or portion thereof in comparison to the parameter, property, or condition of another such structure, material, feature, or portion of such same aforementioned structure, material, or feature—is a relative term that means and includes the parameter, property, or condition of the two such structures, materials, features, or portions being equal, substantially equal, or about equal, at least in terms of respective dispositions of such structures, materials, features, or portions. For example, two structures having “consistent” thickness as one another may each define a same, substantially same, or about the same thickness at Y longitudinal distance from a feature, despite the two structures being at different elevations along the feature.

As used herein, the term “substantially,” when referring to a parameter, property, or condition, means and includes the parameter, property, or condition being equal to or within a degree of variance from a given value such that one of ordinary skill in the art would understand such given value to be acceptably met, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be “substantially” a given value when the value is at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, or even at least 99.9 percent met.

As used herein, the terms “on” or “over,” when referring to an element as being “on” or “over” another element, are spatially relative terms that mean and include the element being directly on top of, adjacent to (e.g., laterally adjacent to, horizontally adjacent to, longitudinally adjacent to, vertically adjacent to), underneath, or in direct contact with the other element. It also includes the element being indirectly on top of, adjacent to (e.g., laterally adjacent to, horizontally adjacent to, longitudinally adjacent to, vertically adjacent to), underneath, or near the other element, with other elements present therebetween. In contrast, when an element is referred to as being “directly on” or “directly adjacent to” another element, there are no intervening elements present.

As used herein, the terms “level” and “elevation” are spatially relative terms used to describe one material's or feature's relationship to another material(s) or feature(s) as illustrated in the figures, using—as a reference point—the lowest illustrated surface of the structure that includes the materials or features. As used herein, a “level” and an “elevation” are each defined by a horizontal plane parallel to a primary surface of the substrate or base structure on or in which the structure (that includes the materials or features) is formed. “Lower levels” and “lower elevations” are relatively nearer to the bottom-most illustrated surface of the respective structure, while “higher levels” and “higher elevations” are relatively further from the bottom-most illustrated surface of the respective structure.

As used herein, the term “depth” is a spatially relative term used to describe one material's or feature's relationship to another material(s) or feature(s) as illustrated in the figures, using—as a reference point—the highest illustrated surface of the structure that includes the materials or features. As used herein, a “depth” is defined by a horizontal plane parallel to the highest illustrated surface of the structure that includes the materials or features.

Unless otherwise specified, any spatially relative terms used in this disclosure are intended to encompass different orientations of the materials in addition to the orientation as depicted in the figures. For example, the materials in the figures may be inverted, rotated, etc., with the “upper” levels and elevations then illustrated proximate the bottom of the page, the “lower” levels and elevations then illustrated proximate the top of the page, and the greatest “depths” extending a greatest vertical distance upward.

As used herein, the terms “comprising,” “including,” “having,” and grammatical equivalents thereof are inclusive, open-ended terms that do not exclude additional, unrecited elements or method steps. These terms also include more restrictive terms “consisting of” and “consisting essentially of” and grammatical equivalents thereof. Therefore, a structure described as “comprising,” “including,” and/or “having” a material may be a structure that, in some embodiments, includes additional material(s) as well and/or a structure that, in some embodiments, does not include any other material(s). Likewise, a material (e.g., composition) described as “comprising,” “including,” and/or “having” a species may be a material that, in some embodiments, includes additional species as well and/or a material that, in some embodiments, does not include any other species.

As used herein, “and/or” means and includes any and all combinations of one or more of the associated listed items.

As used herein, a “(s)” at the end of a term means and includes the singular form of the term and/or the plural form of the term, unless the context clearly indicates otherwise.

As used herein, the terms “configured” and “configuration” mean and refer to a size, shape, material composition, orientation, and arrangement of a referenced material, structure, assembly, or apparatus so as to facilitate a referenced operation or property of the referenced material, structure, assembly, or apparatus in a predetermined way.

The illustrations presented herein are not meant to be actual views of any particular material, structure, sub-structure, region, sub-region, device, system, or stage of fabrication, but are merely idealized representations that are employed to describe embodiments of the disclosure.

Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as limited to the particular shapes or structures as illustrated but may include deviations in shapes that result, for example, from manufacturing techniques. For example, a structure illustrated or described as box-shaped may have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the materials, features, and structures illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a material, feature, or structure and do not limit the scope of the present claims.

The following description provides specific details, such as material types and processing conditions, to provide a thorough description of embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, a person of ordinary skill in the art will understand that the embodiments of the apparatus and methods may be practiced without employing these specific details. Indeed, the embodiments of the apparatus and methods may be practiced in conjunction with conventional semiconductor fabrication techniques employed in the industry.

The fabrication processes described herein do not form a complete process flow for processing apparatus (e.g., devices, systems) or the structures thereof. The remainder of the process flow is known to those of ordinary skill in the art. Accordingly, only the methods and structures necessary to understand embodiments of the present apparatus (e.g., devices, systems) and methods are described herein.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art.

Unless the context indicates otherwise, the removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization, or other known methods.

In referring to the drawings, like numerals refer to like components throughout. The drawings are not necessarily drawn to scale.

With reference toFIG.1A,FIG.1B, andFIG.1C, illustrated are structures102a,102b, and102c, respectively, in elevational cross-sectional view at various points along a width of a microelectronic device structure100illustrated in top plan view inFIG.1D. The elevational views ofFIG.1A,FIG.1B, andFIG.1Ccorrespond to section lines A-A, B-B, and C-C, respectively, ofFIG.1D. The top plan view ofFIG.1Dcorresponds to the elevation indicated by section line D-D inFIG.1A,FIG.1B, andFIG.1C. For ease of illustration,FIG.1Ddoes not illustrate dielectric material(s)104substantially filling space around other features of the microelectronic device structure100.

The microelectronic device structure100—and the structures102ato102cthereof—includes a stack106(which may be otherwise referred to herein as a “stack structure” or as a “tiered stack”) of vertically alternating (e.g., vertically interleaved) insulative structures108and conductive structures110arranged in tiers112. Each tier112may include one insulative structure108and one conductive structure110.

WhileFIG.1AtoFIG.1Cillustrate about thirty (30) tiers112(e.g., thirty (30) conductive structures110) in the stack106, the disclosure is not so limiting. For example, a microelectronic device structure, in accordance with embodiments of the disclosure, may include a different quantity of the tiers112(e.g., and of the conductive structures110) in the stack106. In some embodiments, a number (e.g., quantity) of the tiers112—and therefore of the conductive structures110—of the stack106is within a range of from thirty-two of the tiers112(and of the conductive structures110) to three-hundred or more of the tiers112(and of the conductive structures110). In some embodiments, the stack106includes one-hundred twenty-eight of the tiers112(and of the conductive structures110). However, the disclosure is not so limited, and the stack106may include a different number of the tiers112(and of the conductive structures110).

The conductive structures110may be formed of and include (e.g., each be formed of and include) one or more conductive materials, such as one or more of: at least one metal (e.g., one or more of tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold), at least one alloy (e.g., an alloy of one or more of the aforementioned metals), at least one metal-containing material that includes one or more of the aforementioned metals (e.g., metal nitrides, metal silicides, metal carbides, metal oxides, such as a material including one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), alloys thereof), at least one conductively-doped semiconductor material (e.g., conductively-doped silicon, conductively-doped germanium, conductively-doped silicon germanium), polysilicon, and at least one other material exhibiting electrical conductivity. In some embodiments, the conductive structures110include at least one of the aforementioned conductive materials along with at least one additional of the aforementioned conductive materials formed as a liner. Some or all of the conductive structures110may have the same (e.g., consistent) or different thicknesses (e.g., heights) as one another.

The insulative structures108may be formed of and include (e.g., each be formed of and include) at least one insulative material, such as a dielectric oxide material (e.g., silicon dioxide). In this and other embodiments described herein, the insulative material of the insulative structures108may be substantially the same as or different than other insulative material(s) of the microelectronic device structure100. Some or all of the insulative structures108may have the same (e.g., consistent) or different thicknesses (e.g., heights) as one another. In some embodiments, some of the insulative structures108(e.g., an uppermost, a lowest, and/or intermediate insulative structures108) may be relatively thicker than others of the insulative structures108in the stack106.

The stack106is supported on (e.g., above) a source/drain region114on or within a base structure. The source/drain region114may be formed of and include, for example, one or more semiconductor materials (e.g., polycrystalline silicon (polysilicon)) doped with one or more P-type conductivity chemical species (e.g., one or more of boron, aluminum, and gallium) or one or more N-type conductivity chemical species (e.g., one or more of arsenic, phosphorous, and antimony).

In addition to the source/drain region114, the base structure may include other base material(s) or structure(s), such as conductive regions for making electrical connections with other conductive structures of the device that includes the microelectronic device structure100. In some such embodiments, CMOS (complementary metal-oxide-semiconductor) circuitry is included in a CMOS region below the source/drain region114, which region may be characterized as a so-called “CMOS under Array” (“CuA”) region.

Slit structures116extend through the stack106(e.g., through a full height of the stack106, from lowest surface of the stack106to an uppermost surface of the stack106) and to or into the source/drain region114to divide the stack106into dual-block structures118. The dual-block structures118are further divided into a pair of blocks120by a trench122that extends to or into the source/drain region114, as further discussed below. The trench122may be relatively narrow, compared to the slit structures116. In some embodiments, the trench122may span a distance, between edges and sidewalls of the opposing blocks120, of less than about 1600 nm (less than about 1.6 μm), e.g., less than about 1300 nm (less than about 1.3 μm). A critical dimension (CD) at a base of the trench122may be greater than about 400 nm. The longitudinal (e.g., Y-axis) dimension of the trench122may be less than (e.g., less than half) a longitudinal (e.g., Y-axis) dimension of one of the slit structures116. The trench122may be substantially parallel to and substantially equidistant from the slit structures116bordering the dual-block structure118.

At least one (e.g., one, some, or all) of the slit structures116may include one or more insulative liners124(e.g., formed of and including any one or more of the aforementioned insulative material(s)) and nonconductive fill material126(e.g., formed of and including any one or more of the aforementioned insulative material(s) and/or a semiconductive material(s), such as polysilicon). In some embodiments, sidewalls of the conductive structures110are laterally recessed, relative to the insulative structures108, proximate the slit structures116. In such embodiments, the insulative liner124of the slit structures116may laterally extend in correspondence with the lateral recesses of the conductive structures110of the tiers112.

Other portions of the microelectronic device structure100(e.g., portions horizontally disposed relative to the portions illustrated in the figures) may include array(s) of pillars (e.g., including channel material and memory material) extending through the stack106and to and/or into the doped material of the source/drain region114. The pillars may effectuate the formation of strings of memory cells of a memory device (e.g., a memory device including any of the microelectronic device structures described or illustrated herein). The conductive structures110of the tiers112may be coupled to, or may form control gates of, the memory cells effectuated by the pillars. For example, each conductive structure110may be coupled to one memory cell of a particular string (e.g., effectuated by a particular pillar) of memory cells.

To facilitate electrical communication to particular selected conductive structures110within the stack106, conductive contact structures extend from and physically contact the conductive structures110of the tiers112. Each such conductive contact structure is positioned to physically contact a particular one of the conductive structures110within a respective block120of the microelectronic device structure100. The conductive contacts physically contact the respective conductive structures110at steps128(e.g., landing areas provided by exposed upper surfaces of the conductive structures110). These conductive contact structures physically contacting the steps128may be referred to herein as “step contacts130.”

To provide one step128for each of the conductive structures110of the stack106, the stack106is patterned (e.g., etched) to expose, in a respective block120, one upper surface area portion of each conductive structure110. That is, the tiers112in upper elevations of the stack106are selectively patterned to remove portions that leave exposed an area of a next lowest conductive structure110, which exposed area provides a particular step128for the exposed conductive structure110.

Because each conductive structure110in the stack106occupies a different elevation, the steps128are formed at the various elevations of the conductive structures110. The step contacts130extend downward the various depths to the respective elevations of the respective steps128. The microelectronic device structure100may include, in each respective block120, at least one step contact130per step128and, therefore, at least one step contact130per conductive structure110in the stack106.

The structure102aillustrated inFIG.1Acorresponds to a first lateral position (section line A-A ofFIG.1D) of one dual-block structure118of the microelectronic device structure100. The structure102billustrated inFIG.1Bcorresponds to a second lateral position (section line B-B of FIG. JD) of the same dual-block structure118. The structure102cillustrated inFIG.1Ccorresponds to a third lateral position (section line C-C ofFIG.1D) of the same dual-block structure118.

The two blocks120of a respective dual-block structure118are substantially symmetrically structured, relative to one another, about the trench122. Accordingly, for each step128exposing one conductive structure110, another step128exposing the same conductive structure110is disposed across the trench122and opposite the first step128. The opposing steps128provide what may be referred to herein as the “shoulders” or “cross-bars” of the “T” shape for which the trench122forms a “stem.” In other words, the opposing steps128of the stack106are provided by a plateau of an upper surface of one conductive structure110, with the plateau substantially equally divided by the trench122. In some embodiments, such as that illustrated inFIG.1AtoFIG.1F, each block120includes a single series of steps128to each longitudinal side of the trench122. In other embodiments, such as those described further below, each block120includes multiple series of steps128to each longitudinal side of the trench122.

Vertically, the trench122extends through lower elevations of the stack106, from respective steps128to the base of the stack106, to expose a portion of the source/drain region114at the bottom of the trench122. Accordingly, while the slit structures116may extend through and are at least partially defined by a full height of the stack106, the trenches122extend through and are defined by a partial height of the stack, e.g., the combined height of the tiers112of the stack106from respective steps128to the source/drain region114. Moreover, the slit structures116may each be bordered by at least a portion of each tier112of the stack106and may define a consistent height along a width of the microelectronic device structure100. In contrast, and as described further below, the height of the trench122may vary, across the width of the microelectronic device structure100, in light of the steps128—that border and define a top opening of the trench122—being at different elevations in the stack106.

A pair of the step contacts130, one pair for each opposing pair of steps128of the dual-block structure118, extends an appropriate depth so that each step contact130physically contacts a respective step128. Therefore, each of the structures102athrough102cillustrate a pair of the step contacts130extending a same depth in the respective structure102ato102c, respectively, (e.g., a depth relative to an upper surface of the slit structures116or a depth relative to an upper surface of the stack106). For example, relative to an upper surface of the stack106, the structure102aofFIG.1Aincludes a pair of step contacts130(one for each block120of the dual-block structure118) extending to respective steps128at depth132, the structure102bofFIG.1Bincludes step contacts130extending to respective steps128at depth134, and the structure102cofFIG.1Cincludes step contacts130extending to respective steps128at depth136.

To electrically connect the step contacts130to the source/drain region114, each step contact130may be in electrical communication with a respective additional conductive contact structure that extends to the source/drain region114, namely, an active source/drain contact138. The electrical connection between one of the step contacts130and one of the active source/drain contacts138may be facilitated by conductive routing lines140extending from and between the step contact130and a conductive plug142on (e.g., directly on) the active source/drain contact138.

One or more dielectric material(s)104(e.g., dielectric oxide(s), such as silicon dioxide; dielectric nitride(s), such as silicon nitride) may be formed to fill other space of the dual-block structure118. The dielectric material(s)104may be directly adjacent and may horizontally surround the step contacts130and the active source/drain contacts138. Accordingly, in some embodiments, the step contacts130and the active source/drain contacts138do not further include an insulative liner horizontally about conductive material of these contact structures. In other embodiments, some or all of any of the step contacts130and/or the active source/drain contacts138may further include an insulative liner horizontally surrounding the conductive material of these contacts.

The dielectric material(s)104may substantially fill space—not otherwise occupied by the stack106, the step contacts130, the active source/drain contacts138, and/or other conductive features of the dual-block structure118. In some embodiments, the dielectric material(s)104may extend above and over the upper surface of the stack106. The dielectric material(s)104may be formed in one or more distinctive regions or may be formed in a unitary region within a respective dual-block structure118. For ease of illustration the dielectric material(s)104is not illustrated in the views ofFIG.1D,FIG.1E, andFIG.1F.

As illustrated inFIG.1D,FIG.1E, andFIG.1F, the steps128may be formed and grouped in so-called “stadiums” (e.g., stadium144a, stadium144b, and stadium144c). The microelectronic device structure100may include as many stadiums (e.g., stadium144ato144c), within a respective block120, as necessary to include at least one step128per conductive structure110of the stack106(FIG.1B). Each step128illustrated in a respective block120ofFIG.1D,FIG.1E, andFIG.1Fis at a different elevation (e.g., conductive structure110(FIG.1A)) of the stack106(FIG.1B), as further described below. Like the steps128, each respective stadium (e.g., stadium144a) of a respective block120may have an opposing and symmetrically structured stadium (e.g., stadium144a) of the other block120of the respective dual-block structure118. Accordingly, pairs of opposing stadiums (e.g., opposing stadiums144a, opposing stadiums144b, and opposing stadiums144c) may be symmetrically structured, relative to one another, about the trench122. In other words, the series of stadiums144ato144cof one block120may be substantially symmetrically structured relative to the opposing series of stadiums144ato144cof the other block120.

Non-patterned portions of the stack106(FIG.1B) forming so-called “crests” (e.g., crests146) are laterally interposed between neighboring stadiums (e.g., one crest146between stadium144aand stadium144b; another crest146between stadium144band stadium144c, etc.) and may be laterally adjacent the first and last stadiums (e.g., stadium144aand stadium144c, respectively) of the series in a respective block120.

Another non-patterned portion of the stack106(FIG.1B), forming a so-called “bridge”148, may remain against the sidewall, of the block120, that is defined by the slit structure116. The bridges148are included so that distal portions of a given conductive structure110remain in electrical communication along the width of the conductive structure110in the block120.

The bridges148and crests146may be the result of patterning (e.g., etching) stages that form the slit structures116and the steps128while leaving at least one portion of the full height of the stack106extending substantially a full width of the block120(e.g., to form the bridge148) and while leaving portions of the full height of the stack106extending substantially a full length of the block120(e.g., to form the crests146). Accordingly, both the crests146and the bridges148may include portions of the stack106at the full height of the stack106. The steps128of the block120may longitudinally extend toward the trench122from a respective bridge148and laterally extend toward an opposing step128from a respective crest146.

As illustrated inFIG.1D, the active source/drain contacts138are disposed within the trench122that divides each dual-block structure118into two blocks120and about which opposing stadiums (e.g., stadiums144a) may be substantially symmetrically structured. In some embodiments, all active source/drain contacts138(e.g., all source/drain contacts that are in operative communication with step contacts130) are disposed in the trench122. With such placement, the active source/drain contacts138may be relatively closer to (e.g., with relatively less horizontal distance to) the step contacts130with which they are in operative communication than if, e.g., the active source/drain contacts138were formed in the crests146that separate neighboring stadiums (e.g., stadiums144aand144b) of a respective block120. Accordingly, the crests146may be formed with a relatively smaller horizontal footprint and area than if the active source/drain contacts138were positioned in the crests146. The disposition of the active source/drain contacts138in the trench122, longitudinally between opposing stadiums (e.g., opposing stadiums144a), may save footprint space of the microelectronic device structure100, facilitating device scaling and increased efficiency. In other embodiments, at least one of the active source/drain contacts138is disposed in at least one crest146while others of the active source/drain contacts138are disposed in the trench122.

The active source/drain contacts138in the trench122may extend substantially wholly and vertically through the dielectric material(s)104(FIG.1AtoFIG.1C), rather than through portions of the stack106(FIG.1B) that includes conductive structures110. Therefore, an additional dielectric material (e.g., a dielectric liner) may be omitted from horizontally surrounding the active source/drain contacts138, and the active source/drain contacts138may be in direct physical contact with the dielectric material(s)104. The lack of a dielectric liner surrounding the active source/drain contacts138may further promote feature scaling and increased efficiency. In other embodiments, dielectric liner(s) may be included around the active source/drain contacts138.

FIG.1Eis another top plan view of the microelectronic device structure100with additional features of the microelectronic device structure100illustrated, such as features not illustrated inFIG.1Dfor ease of illustration therein. The view ofFIG.1Emay be a view corresponding to a top-down view from above the stack106of the structures102ato102cofFIG.1AtoFIG.1C, with added conductive routing lines140and without the dielectric material(s)104illustrated, for ease of illustration. The section A-A, section B-B, and section C-C lines are omitted fromFIG.1E, for ease of illustration, but would rightly be disposed in the same relative positions as inFIG.1D.

As illustrated inFIG.1E, conductive routing lines140may be included to electrically connect a respective active source/drain contact138to a respective step contact130. For example, each conductive routing line140may extend from an area of physical contact with one step contact130to an area of physical contact with the conductive plug142atop a respective active source/drain contact138. Accordingly, a respective one of the conductive routing lines140may extend substantially longitudinally (e.g., parallel to the indicated Y-axis or at an angle relative to the Y-axis, but, in at least some embodiments, not laterally parallel to the indicated X-axis) from an area above a respective one of the steps128to an area above the trench122. The disposition of the active source/drain contacts138within the trench122, longitudinally between opposing stadiums (e.g., stadiums144a), may facilitate an arrangement of the conductive routing lines140that is relatively more direct and less crowded than if, e.g., the active source/drain contacts138were disposed in the crests146and the conductive routing lines140extended from step contacts130in the stadiums144ato144claterally to a respective one of the crests146.

FIG.1Eillustrates one possible arrangement of conductive routing lines140between step contacts130and respective active source/drain contacts138, but the disclosure is not limited to this illustrated arrangement. Nonetheless, the disposition of the active source/drain contacts138within the trench122may accommodate a less complex and less crowded arrangement of the conductive routing lines140. With less complexity and less crowding, fabrication of the conductive routing lines140according to a particular arrangement may be more reliable. Moreover, fabrication reliability may also be facilitated by inhibiting block bending, as described further below.

In some embodiments, non-active (e.g., “dummy” or “support”) contacts may also be included in the microelectronic device structure100. For example, support contacts150of substantially the same materials as the active source/drain contacts138may be included at various points along the width and length of the blocks120of the dual-block structure118, whether of the same or different cross-sectional shape or area as that of the active source/drain contacts138. In some such embodiments, the support contacts150are included in the crests146and/or in the trench122(e.g., between opposing crests146), as illustrated inFIG.1E. However, unlike the active source/drain contacts138, the support contacts150need not be in physical or operational contact with conductive plugs142and/or conductive routing lines140(e.g., above and/or below). The illustrated arrangement of support contacts150inFIG.1Eis just one example, but the disclosure is not limited to this particular illustrated arrangement.

With reference toFIG.1F, illustrated, in elevational and lateral cross-section is the microelectronic device structure100in correspondence to section line F-F ofFIG.1D.FIG.1Fillustrates, as described above, that each step128of the stadiums144ato144cis provided by a different one of the conductive structures110of the stack106. A single stadium (e.g., stadium144a) includes a pair of opposing staircases152, each providing steps128at various (e.g., different) elevations of the conductive structures110. However, the opposing staircases152are at least somewhat vertically offset from one another so that the conductive structures110exposed by the steps128of one of the staircases152(e.g., a descending staircase) are not the same conductive structures110exposed by the steps128of the opposing staircase152(e.g., an ascending staircase). The steps128of a respective stadium (e.g., stadium144ato144c) may be grouped according to similar elevations, with a first stadium (e.g., stadium144a) providing steps128in staircases152in uppermost elevations of the stack106, a second stadium (e.g., stadium144b) defining steps128and staircases152in elevations just below the upper most elevations of the stack106, and so on until a final stadium (e.g., stadium144c) defines steps128and staircases152in the lowest elevations of the stack106. According to the illustrated microelectronic device structure100, in the structure102aofFIG.1A, the illustrated steps128at depth132may correspond steps128within the first stadium (e.g., stadium144a) ofFIG.1F; in the structure102bofFIG.1B, the illustrated steps128at depth134may correspond to steps128within the second stadium (e.g., stadium144b) ofFIG.1F; and, in the structure102cofFIG.1C, the illustrated steps128at depth136may correspond to steps128within the third stadium (e.g., stadium144c) ofFIG.1F. It should be understood that any other step128and/or stadium (e.g., stadium144ato144c) ofFIG.1Fcould be illustrated as in any ofFIG.1A,FIG.1B, orFIG.1Cbut with the steps128and base of the step contacts130at the appropriate different elevation, in accordance with the various depths illustrated inFIG.1F.

Accordingly, disclosed is a microelectronic device comprising a stack structure. The stack structure comprises a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. The microelectronic device also comprises a dual-block structure including a first and a second series of stadiums defined in the stack structure. The first series of stadiums is defined in the stack structure within a first block of the dual-block structure. The second series of stadiums is defined in the stack structure within a second block of the dual-block structure. The first series of stadiums and the second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first series and the second series of stadiums. The stadiums—of the first series and of the second series of stadiums—have opposing staircase structures comprising steps at ends of the conductive structures of the stack structure. Conductive source/drain contact structures are in the trench and extend substantially vertically from a source/drain region at a floor of the trench.

With reference toFIG.2AthroughFIG.15C, illustrated are various stages for a method of forming a microelectronic device, such as one including the microelectronic device structure100ofFIG.1D,FIG.1E, andFIG.1F, and also including the structures102ato102cofFIG.1AtoFIG.1C.

With reference toFIG.2A,FIG.2B, andFIG.2C, a stack202(otherwise referred to herein as a “stack structure” or “tiered stack”) is formed on a base structure that includes the source/drain region114. The stack202is formed to include a vertically alternating sequence of the insulative structures108and sacrificial structures204arranged in tiers206. The sacrificial structures204may be formed at elevations of the stack202that will eventually be replaced with or otherwise converted into the conductive structures110(e.g.,FIG.1A).

Sacrificial material(s) of the sacrificial structures204may be selected or otherwise formulated to be selectively removable (e.g., selectively etchable) relative to the insulative structures108. In some embodiments, the insulative structures108comprise (e.g., each comprise) silicon dioxide and the sacrificial structures204comprise (e.g., each comprise) silicon nitride.

To form the stack202, formation (e.g., deposition) of the insulative structures108may be alternated with formation (e.g., deposition) of the sacrificial structures204. In some embodiments, the stack202may be formed, at this stage, to include as many tiers206with sacrificial structures204as there will be tiers112(FIG.1A) with conductive structures110(FIG.1A) in the final structure (e.g., the structures102ato102cofFIG.1AtoFIG.1Cand the microelectronic device structure100ofFIG.1DtoFIG.1F). One or more masks (e.g., hardmasks) may also be included on (e.g., above) the stack202and utilized in subsequent material-removal (e.g., etching, patterning) processes.

With reference toFIG.3A,FIG.3B,FIG.3C, andFIG.3D, the stack202is patterned to define a stadium opening302(e.g., an initial stadium opening) in the footprint area of each stadium to be formed (e.g., stadiums144ato144cof, e.g.,FIG.1F). Areas of the stack202for the crests146(FIG.1F) and the bridges148(FIG.1D) may not be etched so that they retain the full height of the stack202.

As used herein the term “stadium opening” (e.g., as in the stadium openings302ofFIG.3AtoFIG.3D) means and includes an opening, defined by at least one pair of opposing staircases152with each staircase152including steps128at incrementally different elevations, defining the stadium opening to have incrementally changing (e.g., narrowing) horizontal lengths (e.g., Y-axis dimension) with incrementally deeper tier (e.g., tier206) elevations.

The stadium opening302formed for each stadium (e.g., stadiums144ato144cofFIG.1F) to be formed may have substantially the same staircase152elevational profile (e.g., elevational profile along the X-axis as illustrated inFIG.3D) as the final staircase152elevational profiles (e.g., elevational profile along the X-axis as illustrated inFIG.1F) for the respective stadiums. For example, as illustrated inFIG.3D, each stadium opening302may be formed to include one pair of opposing staircases152, each with some number (e.g., five) of steps128, a consistent between-step rise of some number (e.g., two) of the sacrificial structures204(e.g., and, subsequently, the conductive structures110(FIG.1A)), and with the descending staircase152offset from the ascending staircase152by an offset of some number (e.g., one) of sacrificial structures204(e.g., and, subsequently, the conductive structures110(FIG.1A)). This may be the same staircase152, step128number, rise number, and offset number as in the staircases152of the final stadium (e.g., stadium144aofFIG.3DandFIG.1F, and stadiums144band144cofFIG.1F).

Except for the shallowest stadium (e.g., stadium144a) of the series of stadiums for a respective block120(FIG.1D), the stadium openings302and their staircase152structures and elevational profiles will be subsequently lowered to their final elevations, as described further below. In forming the initial stadium openings302in the same upper elevations of the stack202, the same stadium opening302and staircase152profile may be defined in substantially the same upper elevations of the stack202for each stadium (e.g., stadiums144ato144c(FIG.1F)) to be formed. Therefore, for example and as illustrated inFIG.3AtoFIG.3D, in forming the initial stadium openings302, a last step128of a descending staircase152of each stadium opening302may be formed at about the same depth (e.g., depth132). Likewise, each third step in the ascending staircase152may be formed, in its respective initial stadium opening302, at about the same depth, etc. Accordingly, the stadium openings302may be initially formed in substantially the same upper elevations of the stack202before being extended downward (e.g., except for the shallowest stadium144a, which may not be any deeper than its initial stadium opening302)—while substantially maintaining the elevational profile of the initially formed stadium openings302, staircases152, and steps128—to final depths to complete the series of stadiums144ato144c(FIG.1F) at their different depths, as described further below.

With reference toFIG.4A,FIG.4B, andFIG.4C, photoresist material(s)402may be formed (e.g., deposited) in each of the stadium openings302. The photoresist material(s)402may then be patterned (e.g., etched) to define a narrow opening404exposing an area406at the floor of the stadium openings302. The area406may have substantially the horizontal dimensions of the trench122(FIG.1AtoFIG.1C) to be formed. For example, like the final trench122to be formed (seeFIG.1AtoFIG.1C), the narrow opening404may extend substantially the width of the series of stadiums144ato stadiums144c(FIG.1D) to be formed.

The narrow opening404may then be extended, as illustrated in inFIG.5A,FIG.5B,FIG.5C, andFIG.5D, a first extension distance502—by etching further down into the stack202, to form a first extended narrow opening504in the area406that will become the trench122(FIG.1D). The first extended narrow opening504includes a partial trench506extending through some elevations of the stack202while an upper portion of the first extended narrow opening504extends through the photoresist material(s)402.

Forming the first extended narrow opening504with its partial trench506separates each pair of opposing steps128in the stadium openings302. In some embodiments, the partial trench506may be formed along the center the stadium openings302to divide what may otherwise be one step128into two opposing steps128. In the narrowest stadium (e.g., stadium144aofFIG.1F), the steps128may already be at their final depths (e.g., depth132for the steps128of the structure102aofFIG.1A).

Because the stadium openings302were formed with the elevational profile of the staircases152across the floor of each stadium opening302, extending the narrow opening404(FIG.4AtoFIG.4C) to form the first extended narrow opening504and its partial trench506may maintain the same staircase152elevational profile in the area406at a narrow trench floor508. Therefore, the narrow trench floor508of the first extended narrow opening504(and of the partial trench506) may also have the staircase152elevational shape, as indicated by the dashed line of the narrow trench floor508inFIG.5D. In the area406for the trench122(seeFIG.1D), each step128may be about the first extension distance502lower than a corresponding step128in the stadium openings302remaining on the longitudinal sides of the partial trench506.

With reference toFIG.6A,FIG.6B, andFIG.6C, in the not-yet-complete stadium areas (e.g., areas with stadium openings302not yet including steps128at their final depths), the photoresist material(s)402may be removed from the respective stadium openings302to form T-shaped openings602with the stadium openings302connecting to the partial trench506. The photoresist material(s)402may remain in the completed stadium areas, e.g., areas of the stack202patterned with steps128already at their final depths (e.g., depth132for the steps128illustrated inFIG.6A). In other embodiments, the photoresist material(s)402may be wholly removed from the structure and then reformed and re-patterned to provide the first extended narrow opening504in the completed stadium areas and the T-shaped openings602in the not-yet-completed stadium areas.

With the stack202exposed in the T-shaped openings602(both in the stadium openings302and in the partial trench506) and in the first extended narrow opening504(including in the partial trench506), the etching process may be continued to etch deeper into the stack202where the stack202is exposed (e.g., not covered by the photoresist material(s)402), as illustrated inFIG.7A,FIG.7B,FIG.7C, andFIG.7D. The stack202may be consistently etched a second extension distance702, carrying the staircases152elevational profile, already formed in previous stages, to deeper elevations of the stack202. Along the width of the stack202in the area406of the partial trench506, the narrow trench floor508—with its staircases152elevational profile—may be lowered the second extension distance702, retaining the staircases152and elevational profile previously formed in the area406in the stage illustrated inFIG.5AtoFIG.5D. In the already-completed stadiums (e.g., stadium144a), with staircases152and steps128already formed at their final depths (e.g., depth132for the steps128illustrated in the structure102aofFIG.1A), the stack202etching is extended only in the area406of the partial trench506, forming a second extended narrow opening704as illustrated inFIG.7A. In the areas for the not-yet-completed stadiums (e.g., stadiums144band144c(FIG.1F)), the stadium openings302are also lowered the second extension distance702, forming extended T-shaped stadium openings706that retain the staircases152elevational profile initially formed in the stage illustrated inFIG.3BtoFIG.3D. Forming the extended T-shaped stadium openings706may complete the formation of the second shallowest stadium (e.g., stadium144b) with its steps128at depth134.

The stages ofFIG.5AtoFIG.7Dmay be repeated for each remaining stadium to be completed. For example, as illustrated inFIG.8A,FIG.8B, andFIG.8C, as stadiums are completed with their staircases152and steps128at their final depths, the photoresist material(s)402may be re-formed as needed in the completed stadiums and the photoresist material(s)402again patterned to expose only the area406(e.g., the partial trench506) for the trench122(FIG.1AtoFIG.1C) to be formed. The concurrently, the area of not-yet-complete stadiums (e.g., stadium areas with staircases152and steps128not yet at their final depths, such as for stadium144cofFIG.1F) may be re-exposed through the photoresist material(s)402(e.g., as illustrated inFIG.8C) to re-form extended T-shaped stadium opening(s) (e.g., extended T-shaped stadium opening706).

Then, as illustrated inFIG.9AtoFIG.9D, the stadium openings302(in the exposed not-yet-complete stadium areas) and the partial trench506(in both complete and not-yet-complete stadium areas) are extended downward, forming further extended T-shaped stadium openings902and second extended narrow openings904, respectively, by etching further into the stack202another distance to lower the staircases152and their steps128to the elevations of the next stadium to be completed.

When forming the final stadium (e.g., stadium144c(FIG.1FandFIG.9D)), the stadium opening302may be extended downward a final extension distance906, which may be at least a distance708(FIG.7D) between the last highest elevation of the narrow trench floor508and the source/drain region114. In area406, the remaining portions of the stack202may be substantially wholly removed by this final extension, lowering and completing the trench122by removing the remaining stack106height of the final extension distance906or whatever portion908thereof previously remained. Therefore, in the final extension stage, all remaining portions of the stack202in the area406may be removed, forming the trench122with the narrow trench floor508exposing the source/drain region114and extending substantially the whole width of the series of stadiums (e.g., stadiums144ato144c).

The first extension distance502(FIG.5AtoFIG.5C), used to form the initial partial trench506, may have been selected or otherwise tailored to facilitate the final extension stage (e.g., the stage illustrated inFIG.9AtoFIG.9D) to wholly clear the area406of the stack202while lowering the stadium opening302of the final stadium area to its final depths to complete the final stadium (e.g., stadium144cincluding, e.g., the steps128at depth136of the structure102cofFIG.1C).

Methods according to the stages illustrated inFIG.4AtoFIG.9Dinclude forming the partial trench506(e.g.,FIG.5B) (and subsequently the trench122(e.g.,FIG.9B)) after forming the initial stadium openings302(e.g.,FIG.3AtoFIG.3D) in the upper elevations of the stack202, but before extending the stadium openings302downward in repeated stages to form deeper and deeper stadiums (e.g., stadium144bofFIG.7Dthen stadium144cofFIG.9D). Accordingly, in the initial stage of forming the partial trench506(e.g.,FIG.5AtoFIG.5D), the stack202may be etched—in the area406for the trench122—a consistent vertical distance (e.g., first extension distance502(FIG.5A)) along the entire width of the area406that will become the trench122. Then, the trench122may be extended as the deeper stadiums (e.g., stadiums144bto144c) are formed.

In other embodiments, the stadium openings302may be formed and extended downward—in the series of stages to lower the stadium openings302to lower and lower depths (e.g., as illustrated in stagesFIG.6AtoFIG.9D)—before the partial trench506(e.g.,FIG.5B) (or any other portion of the trench122(e.g.,FIG.9B)) is formed (e.g., etched) in the area406of the stack202. In such embodiments, the partial trench506(e.g.,FIG.5B) may be formed (e.g., etched) and then the trench122may be completed (e.g., etching down to the source/drain region114) in the area406of the stack202after the series of stadiums144ato144cis otherwise etched.

With all the stadiums (e.g., stadiums144ato144cofFIG.1F) and the trench122formed (e.g., etched), remaining photoresist material(s)402may be removed from the structure. As illustrated inFIG.10A,FIG.10B, andFIG.10C, the dielectric material(s)104may then be formed (e.g., deposited) to substantially fill the T-shaped trenches154(e.g., both the stadium openings302and the trench122). The dielectric material(s)104may be formed above the stack202as well.

With reference toFIG.11A,FIG.11B, andFIG.11C, the active source/drain contacts138are formed in the trench122. In some embodiments, discrete openings are formed (e.g., etched) through the dielectric material(s)104to the source/drain region114at the narrow trench floor508at the base of the trench122. One or more conductive materials (e.g., one or more metals, such as tungsten) may be formed (e.g., deposited, conformally deposited) in the discrete openings to form the active source/drain contact138in physical contact with, and extending substantially vertically from, the source/drain region114. Because the active source/drain contacts138may be formed through substantially only the dielectric material(s)104, in some embodiments no additional dielectric liner(s) are formed to horizontally surround the active source/drain contacts138.

In embodiments in which the structure further includes support contacts150(FIG.1E), the support contact150may be formed concurrently with, before, or after forming the active source/drain contacts138. For example, additional discrete openings may be formed (e.g., through the dielectric material(s)104, through the stack202, or both) and additional conductive material (e.g., additional one or more metals, such as tungsten) formed (e.g., deposited, conformally deposited) to form the support contacts150. Some, all, or none of the support contacts150may include a dielectric liner horizontally surrounding the conductive material(s) of the support contacts150.

With reference toFIG.12A,FIG.12B, andFIG.12C, a slit1202is formed (e.g., etched) for each slit structure116(FIG.1D) of the microelectronic device structure100(e.g.,FIG.1D). Each slit1202is formed to extend through the stack202and to or into source/drain region114and/or other base material(s) below the stack202. Forming the slits1202divides the stack202into the dual-block structures118. In each dual-block structure118, a pair of opposing blocks120is substantially symmetrically arranged and structured, relative to one another, about the trench122.

Prior to formation of the slits1202, the features of the structure (e.g., the etched portions of the stack202) may be substantially symmetrically structured about the trench122in each respective dual-block structure118area. Accordingly, when the slits1202are formed, the material stresses and strains within the dual-block structure118may also be substantially symmetrically distributed across the dual-block structure118, rather than imbalanced with more stress or stress to one side of the trench122than to the other. Therefore, upon forming the slits1202, block bending (e.g., structural leaning away from vertical) of the dual-block structure118may be lessened or avoided.

Avoiding block bending may facilitate forming the slits1202and further features in their respective desired footprint area, rather than offset or misaligned from a target footprint area due to bending of the structure below. Accordingly, the slits1202may be formed in a manner that consistently retains a sufficient length of, e.g., the shortest (e.g., least Y-axis horizontal dimension) conductive structures110(e.g., conductive rails156) in the bridges148at the sidewalls of the dual-block structure118. Therefore, forming conductive rails156of relatively small longitudinal lengths may be accomplished with relatively more reliability and consistency across the series of dual-block structures118, than if imbalanced structures and material strains and stresses were not lessened or avoided. It is also contemplated that the horizontal lengths and widths of other features (e.g., the steps128) may also be scaled to relatively smaller dimensions and still be relatively more reliability and consistently formed due to the avoidance of material stress and strain imbalances in the design of the dual-block structure118.

In the slits1202, ends of the sacrificial structures204and ends of the insulative structures108are exposed. A “replacement gate” process may be performed, via the slits1202, to at least partially (e.g., substantially) exhume the sacrificial material(s) of the sacrificial structures204, leaving voids1302(e.g., void spaces, gaps)—as illustrated inFIG.13AFIG.13B, andFIG.13C—vertically between the insulative structures108.

In the voids1302, the conductive material(s) of the conductive structures110are formed, as illustrated inFIG.14A,FIG.14B, andFIG.14C, to form the tiers112of the stack106. For example, one or more conductive material(s) (e.g., a single conductive material, a conductive liner and then another conductive material) may be formed in the voids1302(FIG.13AtoFIG.13C) directly on the insulative structures108and directly horizontally adjacent the dielectric material(s)104in the T-shaped trenches154(e.g., in the stadium openings302and in the trench122).

In the slits1202, the material(s) of the slit structures116(FIG.1AtoFIG.1E) may be formed to complete the slit structures116, as illustrated inFIG.15A,FIG.15B, andFIG.15C. For example, the insulative liner124may be formed (e.g., deposited) on sidewalls of the tiers112of the stack106(e.g., the sidewalls, of the dual-block structure118, that extend in the X-axis direction). The insulative liner124may also be formed on the source/drain region114at the bottom of the slits1202(FIG.14AtoFIG.14C). The nonconductive fill material126may be formed (e.g., deposited) to fill or substantially fill a remaining volume between the insulative liner124to complete the slit structures116.

Before or after completing the slit structures116, the step contacts130are formed to extend through the dielectric material(s)104in the stadium openings302to respective steps128at their respective depths (e.g., depths132,134, and136).

The conductive plugs142(FIG.1AtoFIG.1CandFIG.1E) may be formed in physical contact on (e.g., atop) the active source/drain contacts138(but not in physical contact with any support contacts150(FIG.1E)). The conductive routing lines140(FIG.1E) may be formed to bring the active source/drain contacts138into operative communication with their respective step contacts130. Accordingly, the microelectronic device structure100(FIG.1DtoFIG.1F) and its structures102ato102c(FIG.1AtoFIG.1C, respectively) are formed.

Accordingly, disclosed is a method of forming a microelectronic device. The method comprises forming a tiered stack on a base structure. The tiered stack comprises a vertically alternating sequence of insulative structures and other structures. A series of stadiums is formed in the tiered stack. A trench is formed through the tiered stack to the base structure to divide the series of stadiums into a first series of stadiums and a second series of stadiums substantially symmetrically structured relative to one another about the trench. Conductive contact structures are formed in the trench. The conductive contact structures extend vertically from the base structure.

In accordance with embodiments of the disclosure, the microelectronic devices and their structures (e.g., the microelectronic device structure100ofFIG.1DtoFIG.1Fand the structures102ato102cofFIG.1AtoFIG.1C) are formed with features and material stresses and strains substantially symmetrically arranged, in each respective dual-block structure118, across a lateral (e.g., X-axis) centerline of the dual-block structure118(e.g., a centerline along which the trench122extends). Therefore, the devices and structures (e.g., the microelectronic device structure100(FIG.1DtoFIG.1F) and structures102ato102c(FIG.1AtoFIG.1C, respectively)) may be formed by method(s) configured to avoid or at least lessen the risk of block bending, which also facilitates relatively more reliable and consistent fabrication of features, including relatively small-scaled features. Still further, the horizontal proximity of the active source/drain contacts138to the steps128and stadiums144ato144c(FIG.1D) may facilitate an arrangement of the conductive routing lines140(FIG.1E) that is relatively more direct, shorter, less crowded, and more reliably formed and operated than if the active source/drain contacts138were disposed horizontally further from the steps128of the stadiums (e.g., stadiums144ato144c(FIG.1E)), e.g., in the crests146(FIG.1E). In some embodiments, the lessened complexity and crowding of the conductive routing lines140(FIG.1E) may also facilitate including a greater quantity of active source/drain contacts138and respective step contacts130and steps128in each stadium144ato144c(FIG.1E), which may enable scaling of the series of stadiums144ato144c(FIG.1E).

With reference toFIG.16A,FIG.16B,FIG.16C,FIG.16D,FIG.16E, andFIG.16F, illustrated are structures1602a(FIG.16A),1602b(FIG.16B), and1602c(FIG.16C) of a microelectronic device structure1600(FIG.16DtoFIG.16F) in which the number of steps128in a single stadium is effectively multiplied by including at least one step drop1604(e.g., a lateral division with one step128of one conductive structure110elevation at the upper end of the step drop1604and one step128of one conductive structure110elevation at the lower end of the step drop1604). Steps128(e.g., in a first pair of opposing staircases152) on the upper end of the step drop1604may be longitudinally recessed relative to the trench122, extending from the bridge148to the step drop1604. Steps128(e.g., in a second pair of opposing staircases152) on the lower end of the step drop1604may extend from the step drop1604to the trench122.

In some embodiments, more than one step drop1604may be included per stadium1606ato1606bto further multiply the number of steps128in the stadium1606ato1606b. In other words, each step drop1604effectively adds an additional pair of opposing staircases152within a respective stadium1606ato1606b.

In some embodiments, such as illustrated inFIG.16AtoFIG.16C, the step drop1604may provide a step-to-step drop of a height of one tier112. In other embodiments, the height of the step drop1604may be greater than one tier112.

With the step drop1604, at the cross-bar (or shoulders) of the T-shaped trench154(e.g., where the stadium openings302(e.g.,FIG.16B) meets the trench122), there are multiple steps128(e.g., two steps128) to each longitudinal side of the trench122. Each step128is associated with a respective one of the step contacts130. As in the microelectronic device structure100ofFIG.1AtoFIG.1F, the blocks120of the dual-block structure118are substantially symmetrically structured, relative to one another, about the trench122.

With the multiplied (e.g., doubled) number of steps128in each stadium1606ato1606b, and therefore the multiplied (e.g., doubled) number of step contacts130in each stadium1606ato1606b, the number of active source/drain contacts138in the trench122may also be multiplied (e.g., doubled). The active source/drain contacts138may be arranged in multiple lines or in other patterns along the trench122. With reference toFIG.16E, conductive routing lines140may be included to electrically connect one step contact130with its respective active source/drain contact138. As with the microelectronic device structure100ofFIG.1AtoFIG.1F, the disposition of the active source/drain contacts138in the trench122, between opposing stadiums1606ato1606band horizontally proximate the step contacts130, may facilitate an arrangement of the conductive routing lines140that is relatively more direct, less complex, and less crowded than if the active source/drain contacts138were disposed, e.g., in the crests146.

The inclusion of the step drop1604to effectively multiply (e.g., double) the number of steps128in a given stadium (e.g., stadium1606a, stadium1606b) may enable including fewer stadiums (e.g., stadiums1606ato1606b) for a given number of conductive structures110in the stack106. For example, if a stadium without a step drop1604(e.g., stadium144a,144b, or144cofFIG.1F) includes ten steps128(e.g., five steps128per staircase152), a stadium with a step drop1604(e.g., stadium1606aor1606bofFIG.16F) includes twenty steps128(e.g., ten steps128above the step drop1604and ten more steps128below the step drop1604, or, in other words, ten steps128in each of two pairs of opposing staircases152). Accordingly, the inclusion of at least one step drop1604may facilitate scaling the series of stadiums1606ato1606b.

The staircases152of the stadiums1606ato1606bmay be relatively steeper than the staircases152of the microelectronic device structure100(seeFIG.1F). For example, the staircases152including the step drop1604may have a rise—between laterally neighboring steps128of a respective staircase152—of greater than two tiers112. The greater number of tiers in the rise of the staircase152accounts for the step drop1604providing steps128for the conductive structures110of two vertically adjacent tiers112. Therefore, a rise of at least two-times the number of step drops1604in the staircase152may facilitate each step128of the stadium (e.g., stadium1606a) being formed at a different conductive structure110elevation of the stack106.

As with the microelectronic device structure100ofFIG.1E, the microelectronic device structure1600may further include support contacts150(not illustrated inFIG.16Efor ease of illustration) in any arrangement. Unlike the active source/drain contacts138in the trenches122, the support contacts150may not be in contact with conductive plugs142(FIG.16AtoFIG.16C) and may not be in operational contact with conductive routing lines140(FIG.16E).

Accordingly, disclosed is a microelectronic device comprising a stack structure comprising insulative structures vertically interleaved with conductive structures and arranged in tiers. A pair of slit structures extends through the stack structure to a source/drain region below the stack structure. A trench is between the first slit structure and a second slit structure of the pair of slit structures. The trench extends through the stack structure to the source/drain region. A first series of staircased stadiums is defined in the stack structure between the first slit structure and the trench. A second series of staircased stadiums is defined in the stack structure between the second slit structure and the trench. Conductive contact structures are disposed in the trench and extend from the source/drain region. The first series of staircased stadiums is substantially symmetrically structured to the second series of staircased stadiums.

With reference toFIG.17AtoFIG.21D, illustrated are various stages for forming a microelectronic device, such as one including the microelectronic device structure1600ofFIG.16DtoFIG.16Fand also including the structures1602ato1602cofFIG.16AtoFIG.16C. The stage illustrated inFIG.17A,FIG.17B,FIG.17C, andFIG.17Dmay follow that illustrated inFIG.2AtoFIG.2C, e.g., formation of the stack202.

The stack202is patterned to define the stadium openings302in a manner similar to that described above with regard to the stage illustrated inFIG.3AtoFIG.3D. However, the stadium openings302formed according to this embodiment may be of a relatively greater Y-axis dimension to accommodate the multiplication of the steps128(FIG.16C) by the step drop1604(FIG.16C), and the staircases152provided by the stadium openings302may be relatively steeper, as described above.

The stadium openings302are formed—in the upper elevations of the stack202for each stadium to be formed—to initially exhibit the elevational profile of the staircases152that will be above the step drop1604(FIG.16C) in the shallowest stadium1606a(FIG.16F) of the stadium series. For example, in the initially-formed stadium openings302, a third step128of a descending staircase152in the stadium area1702afor the shallowest stadium1606a(FIG.16F) may be formed at depth1704as illustrated inFIG.17AandFIG.17D; a bottom (e.g., first) step128of an ascending staircase152in the stadium area1702amay be formed at depth1706as illustrated inFIG.17BandFIG.17D; and a fourth step128(from the bottom, or second step128from the top) of an ascending staircase152in the stadium area1702bfor the stadium1606bmay be formed at depth1708as illustrated inFIG.17CandFIG.17D.

With reference toFIG.18A,FIG.18B, andFIG.18C, the photoresist material(s)402may be formed in the stadium openings302in a manner substantially similar to that described above with regard to the stage illustrated inFIG.4AtoFIG.4C. However, the photoresist material(s)402may be patterned, in each stadium area1702ato1702b(FIG.17D) to define an opening1802with a length (e.g., Y-axis dimension) substantially equal to the distance between the step drops1604(FIG.16C) to be formed in opposing stadiums (e.g., stadium1606ain a first and second block120ofFIG.16D).

The opening1802may be extended downward a depth of about one tier206to form extended openings1902, as illustrated inFIG.19A,FIG.19B,FIG.19C, andFIG.19D. For example, the stack202may be etched for a relatively short time period to remove substantially only one level of sacrificial structure204and one level of insulative structure108to form the step drops1604with a drop of one tier206at both longitudinal sides of the extended openings1902. This provides the steps128on the upper end of the step drop1604and a plateau for the steps128on the lower end of the step drop1604. In forming the step drop1604, substantially the same staircase152elevational profile may be consistently lowered the height of about one tier206, across the width of each extended opening1902, as illustrated in by the dashed lines ofFIG.19D. In subsequent extensions of this elevational profile in the stadium openings302, the one-tier step drop1604may be maintained as the elevational profiles are extended to lower and lower depths for forming deeper and deeper stadiums (e.g., stadium1606bofFIG.16F).

After defining the step drop1604, formation of the trench122(FIG.16AtoFIG.16C) may be initiated to divide the plateau on the lower end of the step drop1604into opposing steps128of opposing stadiums (e.g., opposing stadiums1606a(FIG.16D)). For example, as illustrated inFIG.20A,FIG.20B, andFIG.20C, the photoresist material(s)402may be reformed and re-patterned, as necessary, to define the narrow openings404in the area406to become the trench122(FIG.16AtoFIG.16C), in a manner substantially similar to that described above with respect to the stage illustrated inFIG.4AtoFIG.4C. The narrow openings404may be extended to form the first extended narrow opening504—as illustrated inFIG.21A,FIG.21B, andFIG.21C—and to form the partial trench506with the narrow trench floor508in the area406that will become the trench122(FIG.16AtoFIG.16E)—as illustrated inFIG.21D—in a manner substantially similar to that described above with respect to the stage illustrated inFIG.5AtoFIG.5D.

The method for completing the formation of the microelectronic device structure1600ofFIG.16DtoFIG.16Fand the structures1602ato1602cofFIG.16AtoFIG.16Cmay continue in substantially the same way as described above with regard to the stages illustrated inFIG.6AtoFIG.15C, including lowering the elevational profile of the stadium openings302and the partial trench506deeper and deeper for not-yet-completed stadium areas. As with the formation of the microelectronic device structure100ofFIG.1DtoFIG.1F, the substantially symmetrical structure of the blocks120(and opposing stadiums1606ato1606b) of the dual-block structures118of the microelectronic device structure1600may avoid block bending during fabrication, facilitating more reliable feature formation and scaling of structure features.

Accordingly, disclosed is a method of forming a microelectronic device. The method comprises forming—on a base structure—a stack of insulative structures vertically interleaved with other structures and arranged in tiers. In upper elevations of the stack, a series of stadium openings is formed. The stadium openings define opposing staircases. The opposing staircases of each stadium opening of the series has an elevational profile substantially the same as that of other opposing staircases of the stadium openings of the series. A trench is formed through additional elevations of the stack and extends along the series of stadium openings to divide the series of stadium openings into a first series of stadiums and a second series of stadiums. The second series of stadiums is substantially symmetrically structured relative to the first series of stadiums. At least some stadiums of the first series and the second series are extended to different depths in the stack. The at least some stadiums substantially retain the elevational profile of the opposing staircases after the extending. While extending at least some stadiums, the trench is extended to expose the base structure between the first series of stadiums and the second series of stadiums. A series of conductive contact structures is formed in the trench. The conductive contact structures extend from the base structure. A pair of slits is formed through the stack. The slits are formed to be substantially parallel to the trench. Each slit of the pair of slits is spaced from a neighboring one of the first series of stadiums and the second series of stadiums by a bridge portion of the stack.

FIG.22shows a block diagram of a system2200, according to embodiments of the disclosure, which system2200includes memory2202including arrays of vertical strings of memory cells adjacent microelectronic device structure (e.g., microelectronic device structure100ofFIG.1DtoFIG.1Fand including structures102ato102cofFIG.1AtoFIG.1C; microelectronic device structure1600ofFIG.16DtoFIG.16Fand including structures1602ato1602cofFIG.16AtoFIG.16C). Therefore, the architecture and structure of the memory2202may include one or more device structures according to embodiments of the disclosure and may be fabricated according to one or more of the methods described above (e.g., with reference toFIG.2AtoFIG.15Cand/orFIG.17AtoFIG.21D).

The system2200may include a controller2204operatively coupled to the memory2202. The system2200may also include another electronic apparatus2206and one or more peripheral device(s)2208. The other electronic apparatus2206may, in some embodiments, include one or more of the microelectronic device structure100ofFIG.1DtoFIG.1F(including structures102ato102cofFIG.1AtoFIG.1C) or the microelectronic device structure1600ofFIG.16DtoFIG.16F(including structures1602ato1602cofFIG.16AtoFIG.16C), according to embodiments of the disclosure and fabricated according to one or more of the methods described above. One or more of the controller2204, the memory2202, the other electronic apparatus2206, and the peripheral device(s)2208may be in the form of one or more integrated circuits (ICs).

A bus2210provides electrical conductivity and operable communication between and/or among various components of the system2200. The bus2210may include an address bus, a data bus, and a control bus, each independently configured. Alternatively, the bus2210may use conductive lines for providing one or more of address, data, or control, the use of which may be regulated by the controller2204. The controller2204may be in the form of one or more processors.

The other electronic apparatus2206may include additional memory (e.g., with one or more of the microelectronic device structure100ofFIG.1DtoFIG.1F(including structures102ato102cofFIG.1AtoFIG.1C) or the microelectronic device structure1600ofFIG.16DtoFIG.16F(including structures1602ato1602cofFIG.16AtoFIG.16C), according to embodiments of the disclosure and fabricated according to one or more of the methods described above). Other memory structures of the memory2202and/or the other electronic apparatus2206may be configured in an architecture other than 3D NAND, such as dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), synchronous graphics random access memory (SGRAM), double data rate dynamic ram (DDR), double data rate SDRAM, and/or magnetic-based memory (e.g., spin-transfer torque magnetic RAM (STT-MRAM)).

The peripheral device(s)2208may include displays, imaging devices, printing devices, wireless devices, additional storage memory, and/or control devices that may operate in conjunction with the controller2204.

The system2200may include, for example, fiber optics systems or devices, electro-optic systems or devices, optical systems or devices, imaging systems or devices, and information handling systems or devices (e.g., wireless systems or devices, telecommunication systems or devices, and computers).

Accordingly, disclosed is an electronic system comprising a three-dimensional memory device, at least one processor in operable communication with the three-dimensional memory device, and at least one peripheral device in operable communication with the at least one processor. The three-dimensional memory device comprises a stack structure comprising conductive structures vertically alternating with insulative structures and arranged in tiers. Slit structures extend through the stack structure to a source/drain region. The slit structures divide the stack structure into dual-block structures. At least one of the dual-block structures comprises a pair of blocks defining a series of stadiums having opposing staircase structures. The series of stadiums of the pair of blocks is substantially symmetrically structured relative to one another about a trench. The trench extends through the stack structure to the source/drain region. A series of conductive contact structures is in the trench and extends to the source/drain region.

While the disclosed structures, apparatus (e.g., devices), systems, and methods are susceptible to various modifications and alternative forms in implementation thereof, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure encompasses all modifications, combinations, equivalents, variations, and alternatives falling within the scope of the disclosure as defined by the following appended claims and their legal equivalents.