Patterning method

An example embodiment includes a patterning method comprising: forming a layer stack comprising a target layer, a lower memorization layer and an upper memorization layer, forming above the upper memorization layer a first mask layer, patterning a set of upper trenches in the upper memorization layer, forming a first block pattern, the first block pattern comprising a set of first blocks, patterning a first set of lower trenches in the lower memorization layer, patterning the patterned upper memorization layer to form a second block pattern comprising a set of second blocks, forming above the patterned lower memorization layer and the second block pattern a second mask layer, patterning a second set of lower trenches in the patterned lower memorization layer, the patterning comprising using the second mask layer, the spacer layer and the second block pattern as an etch mask.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a non-provisional patent application claiming priority to European Patent Application No. 18191776.6, filed on Aug. 30, 2018, the contents of which are hereby incorporated by reference.

FIELD OF THE DISCLOSURE

The present disclosure relates to a patterning method.

BACKGROUND

Semiconductor device fabrication of today frequently involves forming of various patterns, such as lines or trenches in a layer, for instance in a hard mask layer, a dielectric layer, a metal layer or a semiconductor layer.

In lithographically based patterning techniques (i.e. “litho-etch”), a photoresist layer may be formed above the layer which is to be patterned. The photoresist layer may be lithographically patterned (i.e. exposed and developed) and the pattern in the photoresist layer may then be transferred into the underlying layer by etching while using the patterned photoresist layer as an etch mask. Lithographically based patterning techniques may also involve transferring the pattern in the photoresist layer into a mask layer (typically a hard mask layer) in one or more etching steps, and thereafter using the mask layer in a final pattern transfer step into an underlying layer.

In spacer-assisted multiple patterning techniques (also known as self-aligned multiple patterning techniques) such as SADP or SAQP, grating-like patterning layers of mandrel lines and spacer lines may be used to form tight pitch line patterns in an underlying layer. Multiple patterning may be combined with block techniques to enable forming of interrupted or discontinuous lines.

The minimum critical dimensions (CDs) of litho-etch based patterning is limited by among others the wavelength of the light used for exposing photoresist. Although extreme ultraviolet lithography (EUVL) enables forming patterns with reduced CDs compared to current technologies based on for instance 193i, edge placement errors (EPE) still imposes a limit on the minimum attainable CD. Meanwhile, SADP and SAQP enables forming of comparably tighter pitch patterns. However, while lithographically based patterning techniques allows forming of patterns of various shapes, self-aligned multiple patterning techniques are typically limited to forming regular and repeating line-based patterns.

SUMMARY

In light of the above, there is in accordance with an aspect of the present disclosure provided a patterning method comprising: forming a layer stack comprising in a bottom-up direction a target layer, a lower memorization layer and an upper memorization layer, forming above the upper memorization layer a first mask layer, wherein a set of trenches are formed in the first temporary mask layer using lithography and etching, patterning a set of upper trenches in the upper memorization layer, the patterning comprising using the first mask layer as an etch mask, forming a spacer layer on sidewalls of the upper trenches, forming a first block pattern, the first block pattern comprising a set of first blocks, each first block extending across an upper trench in the upper memorization layer, patterning a first set of lower trenches in the lower memorization layer, the patterning comprising using the patterned upper memorization layer, the spacer layer and the first block pattern as an etch mask, wherein at least a subset of the first lower trenches are interrupted by a trench interruption, each trench interruption being formed by a portion of the lower memorization layer preserved under a respective one of the first blocks, patterning the patterned upper memorization layer to form a second block pattern comprising a set of second blocks, each second block being formed of a respective remaining portion of the upper memorization layer, forming above the patterned lower memorization layer and the second block pattern a second mask layer, wherein a set of trenches are formed in the second mask layer using lithography and etching, wherein each trench of the set of trenches is formed over a respective remaining portion of the patterned lower memorization layer, patterning a second set of lower trenches in the patterned lower memorization layer, the patterning comprising using the second mask layer, the spacer layer and the second block pattern as an etch mask, wherein at least a subset of the second lower trenches are interrupted by a trench interruption, each trench interruption being formed by a portion of the lower memorization layer preserved under a respective one of the second blocks, and wherein the method further comprises patterning in the target layer a first set of target trenches under the first set of lower trenches and a second set of target trenches under the second set of lower trenches.

The disclosed method enables an increased flexibility for the shape of the patterns than provided by conventional self-aligned multiple patterning techniques. Additionally, the method enabling forming of patterns with smaller CD than provided by conventional lithographical patterning techniques.

The disclosed method is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method may hence be referred to as a “SALELE” patterning process.

Employing two LE processes, allows comparably tight pitch patterns to be formed by combining two relaxed pitch patterns. This may be particularly beneficial if the trenches in the first mask layer are formed using EUVL which otherwise is a technique prone to stochastic failures if used to directly form aggressively scaled patterns. Relaxed printing may provide corresponding benefits also in 193i applications.

Since the trenches in the first and second mask layers are formed by LE, the trench patterns may be designed in a relatively free manner. For instance, the trenches may be formed with various widths, various spacing and various directions in different regions of the first mask layer, rather than in a regular, fixed single pitch trench pattern. A further benefit over self-aligned multiple patterning techniques is that formation of dummy lines may be avoided.

The disclosed method is enabled by the combined use an upper and lower memorization layer. The upper memorization layer has a double function. The upper memorization layer is first patterned to memorize the pattern of upper trenches, which pattern later is used for patterning the lower memorization layer. The (patterned) upper memorization layer is then again patterned to memorize the second block pattern, which is used to define trench interruptions for the second set of lower trenches in the lower memorization layer. Meanwhile, the lower memorization layer allows the first set of lower trenches and the second set of lower trenches to be sequentially memorized therein, prior to patterning the target layer.

By forming the spacer layer on the sidewalls of the upper trenches in the upper memorization layer, spacer lines may be defined along the sidewalls of each upper trench. Using the spacer layer/spacer lines as an etch mask in subsequent patterning steps makes it possible to ensure an at least minimum separation between adjacent trenches which are to be formed in the target layer. A sidewall spacer layer may be reliably formed with uniform thickness in the upper trenches and may hence reduce process variability.

Meanwhile, the first and second block patterns enable forming of interrupted trenches with smaller tip-to-tip separation than would be achievable by directly patterning interrupted trenches in the first and second mask layers. Since the second block pattern is formed by patterning the already once patterned upper memorization layer, the second block pattern may be self-aligned with respect to the first set of lower trenches and consequently reliably be aligned with the second set of lower trenches.

By a first feature such as a layer, a mask or other structure, being formed “above” a second feature such as a layer, a mask or other structure, is hereby meant that the first feature is formed above the second feature (as seen) in a normal direction to the main surface or in-plane extension of the feature, e.g. layer or level, or in the normal direction to the target layer. If the layer stack is formed above a substrate, above may accordingly refer to the normal direction to the substrate.

A first feature such as a layer, a mask or other structure, formed “on” a second feature such as a layer, a mask or other structure, may either be formed directly on the second feature (i.e. in abutment with the second feature), or indirectly on the second feature, with one or more structures intermediate the first and the second feature (i.e. not in direct contact with the first feature).

By a “trench” in a layer (e.g. in a mask/memorization/target layer) is hereby meant a recess or opening in the layer. A trench may, at least along a portion thereof, extend in a straight line and present a uniform width.

By the terminology “using a layer as an etch mask” is hereby meant that one or more underlying layers are etched while the layer counteracts etching of the underlying layer(s) in regions covered by the layer. The underlying layer(s) are hence etched selectively to the layer acting as an etch mask.

By etching or removal of a feature “A”, selectively to a feature “B”, is hereby meant that a feature A arranged adjacent to a feature B may be removed while preserving the feature B. This may be achieved by selecting a material of feature A and a material of feature B as a combination of materials presenting different etch rates in a given etch process. The preservation of the feature B following the etch process may be complete (in the sense that the feature B is not affected appreciably during the etch process) or at least partial (in the sense that the feature B remains at least to the extent that it may serve its intended function during subsequent process steps). A ratio of an etch rate of the material of feature A compared to an etch rate of the material of feature B may be 2:1 or higher, 10:1 or higher, or even 40:1 or higher.

The patterning of the first set of target trenches may be performed prior to patterning of the second set of target trenches. More specifically, the patterning of the first set of target trenches may comprise using the once patterned lower memorization layer and the spacer layer as an etch mask. Subsequently, the patterning of the second set of target trenches may comprise using the twice patterned lower memorization layer as an etch mask. Thereby, the first and second sets of target trenches may be formed in different and subsequent patterning steps.

This sequential patterning approach simplifies the process since it does not require the patterning of the second block pattern in the patterned upper memorization layer to employ an etch with a considerably greater selectivity towards the material of the upper memorization layer than of the target layer. Moreover, forming the first and second sets of target trenches simultaneously may complicate the target layer patterning since the regions of the target layer exposed in, respectively, the first and second lower sets of trenches of the lower memorization layer then would have been exposed to different etching processes, modifying the respective surface regions of the target layer differently. Differently modified surface regions may respond differently to etching during the patterning of the target layer and in turn have an adverse impact on the fidelity of the target layer patterning.

The first set of target trenches may be formed during the patterning of the second block pattern in the once patterned upper memorization layer and prior to forming the second mask layer.

Postponing patterning of the first set of target trenches until forming the second block pattern makes it possible to preserve the mask budget of the (once) patterned upper memorization layer for the second block pattern. More specifically, a second block mask comprising a set of second mask blocks may counteract etching of the portions of the once patterned upper memorization layer (which portions are to form the second blocks of the second block pattern). The etching employed during the patterning of the first set of target trenches could otherwise attack also these portions of the patterned upper memorization layer.

According to an embodiment, trenches of at least a subset of the second set of lower trenches are arranged alternatingly with trenches of at least a subset of the first set of lower trenches. Hence, the subsets of first lower trenches and second lower trenches may together define a tight pitch trench pattern.

The spacer layer may define first and second spacer lines along each upper trench. Accordingly, each trench of the at least a subset of the second set of lower trenches may be spaced from an adjacent trench of the at least a subset of the first set of lower trenches by a thickness portion of the lower memorization layer preserved under a respective one of the spacer lines a respective one of the spacer lines. Thereby, the subsets of first and second trenches may be formed with a uniform spacing matching a line width of the spacer lines (i.e. the thickness of the spacer layer).

According to an embodiment, forming the set of trenches in the first mask layer comprises: forming a photoresist layer above the first mask layer and lithographically patterning a set of trenches in the photoresist layer, and patterning the set of trenches in the first mask layer, the patterning comprising using the patterned photoresist layer as an etch mask.

Accordingly, a trench pattern may first be lithographically defined in the photoresist layer and subsequently trenches may be patterned in the first mask layer.

The patterning of the set of trenches in the first mask layer may comprise transferring the set of trenches in the photoresist layer into the first mask layer by etching, thereby forming the set of trenches in the first mask layer.

The patterning of the set of trenches may however also comprise a sequential transferring of trench patterns:

A transfer layer may be formed above the first mask layer. The first photoresist layer may be formed above the transfer layer. The patterning of the set of trenches in the first mask layer may comprise: transferring the set of trenches in the photoresist layer into the transfer layer by etching, thereby forming a set of trenches in the transfer layer, subjecting the patterned transfer layer to an etch step thereby forming a trimmed trench pattern in the transfer layer, and thereafter transferring the trimmed trench pattern into the first mask layer by etching, thereby forming the set of trenches in the first mask layer.

Hence, the trench pattern formed in the first mask layer may be trimmed in relation to the original lithographically patterned trench pattern in the photoresist layer. The trimming may comprise a lateral etch back of the portions of the patterned transfer layer surrounding the trenches formed therein. In other words, the trimming may result in a widening of the trenches in the patterned transfer layer.

Subsequent to the transfer of the trimmed trench pattern into the first mask layer, the first mask layer may be used as an etch mask in the patterning of the upper trenches in the upper memorization layer.

According to an alternative, the method may comprise subjecting the patterned upper memorization layer (with the upper trenches formed therein) to a trimming step, thereby forming a trimmed trench pattern in the upper memorization layer. The trimming may comprise an etch step. The trimming may comprise an oxidation of an outer thickness portion of the upper memorization layer to form an oxide layer on the upper memorization layer and subsequently removing the oxide layer formed on the upper memorization layer by etching.

According to an embodiment, the second mask layer is formed to cover the patterned lower memorization layer and the second block pattern, and wherein forming the set of trenches in the second mask layer comprises: forming a photoresist layer above the second mask layer and lithographically patterning a set of trenches in the photoresist layer, and patterning the set of trenches in the second mask layer, the patterning comprising using the patterned photoresist layer as an etch mask.

Accordingly, a trench pattern may first be lithographically defined in the photoresist layer and subsequently trenches may be patterned in the second mask layer.

The patterning of the set of trenches in the second mask layer may comprise transferring the set of trenches in the photoresist layer into the second mask layer by etching, thereby forming the set of trenches in the second mask layer.

The patterning of the set of trenches may however also comprise a sequential transferring of trench patterns:

A transfer layer may be formed above the second mask layer. The second photoresist layer may be formed above the transfer layer. The patterning of the set of trenches in the second mask layer may comprise: transferring the set of trenches in the second photoresist layer into the transfer layer by etching, thereby forming a set of trenches in the transfer layer, and thereafter transferring the set of trenches in the transfer layer into the second mask layer by etching, thereby forming the set of trenches in the second mask layer.

Subsequent to the transfer of the trench pattern into the second mask layer, the second mask layer may be used as an etch mask in the patterning of the second set of lower trenches in the lower memorization layer.

According to an embodiment, forming the first block pattern comprises: forming a first block mask layer covering the patterned upper memorization layer, forming a photoresist layer above the first block mask layer and lithographically patterning the photoresist layer to define a photoresist block mask comprising a set of resist blocks, each resist block extending across an upper trench in the upper memorization layer, and patterning the first block mask layer to form the second block pattern, the patterning comprising using the photoresist block mask as an etch mask.

Accordingly, blocks may first be lithographically defined in the photoresist layer and subsequently the first block pattern may be patterned in the first block mask layer.

According to an embodiment, patterning the patterned upper memorization layer to form a second block pattern comprises: forming a second block mask layer covering the patterned lower and upper memorization layers, forming a photoresist layer above the second block mask layer and lithographically patterning the photoresist layer to define a photoresist block mask comprising a set of resist blocks, each resist block being formed over a respective remaining portion of the upper memorization layer, patterning the second block mask layer to form a second block mask comprising a set of second mask blocks, the patterning comprising using the photoresist block mask as an etch mask, and patterning the patterned upper memorization layer to form the second block pattern, the patterning comprising using the second block mask as an etch mask.

Depositing a second block mask layer covering the patterned lower and upper memorization layers allows providing a planar surface, thus facilitating a lithographic patterning of a block pattern in the photoresist layer.

The patterning of the second block mask layer may comprise etching the second block mask layer to form the second block mask comprising the set of second mask blocks and such that portions of the second block mask layer remain in the first set of lower trenches, wherein during the patterning of the patterned upper memorization layer to form the second block pattern, the portions of the second block mask layer remaining in the first set of lower trenches masks the target layer within the first set of lower trenches, and wherein the method further comprises: removing the second block mask and the portions of the second block mask layer subsequent to forming the second block pattern.

By patterning the second block mask layer such that portions of the block mask layer are preserved in the first set of lower trenches, an upper surface of the target layer may be covered during the patterning of the patterning to form the second block pattern (i.e. the patterning of the patterned upper memorization layer). Thus during the patterning to form the second block pattern, etching of the target layer may be counteracted by the portions of the block mask layer remaining within the first set of lower trenches and by the (once) patterned lower memorization layer outside of the first set of lower trenches. This allows limiting exposure of the target layer to etchants prior to patterning of the target layer. This in turn facilitates a simultaneous patterning of the first and second sets of target trenches.

Accordingly, the method may comprise patterning the first set of target trenches and the second set of target trenches simultaneously, the patterning comprising using the (twice) patterned lower memorization layer (comprising the first and second lower sets of trenches) as an etch mask. Thereby, the first and second sets of target trenches may be formed simultaneously in a same patterning step.

The target layer may be a hard mask layer. The method may accordingly be used for the purpose of patterning a hard mask layer, which in turn may be used for patterning an underlying layer.

According to one combination, the target layer may be a TiN layer, the lower memorization layer may be a SiN layer and the upper memorization layer may be an a-Si (amorphous silicon) layer.

More specifically, the first and second set target trenches may be transferred into an underlying layer using the target layer as an etch mask.

The underlying layer may be a dielectric layer. Accordingly the method may be used for forming trenches in a dielectric layer, which subsequently may be filled with a conductive material to form a pattern of conductive paths of an interconnect structure. As the method makes it possible to avoid forming of dummy trenches in the target layer and dielectric layer, it follows that unused conductive dummy lines may be avoided in the dielectric layer. Such dummy lines could otherwise adversely affect RC delay and/or power consumption in a final circuit.

All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

A method for patterning a target layer will now be described with reference toFIGS. 1-21. The method will be described in connection with patterning a target layer22in the form of a hard mask layer, which in turn may be used for the purpose of patterning trenches in a dielectric layer stack10. It is however noted that the method has a more general applicability for patterning trenches in any target layer, such as in a semiconductor a layer or a metal layer.

With reference toFIG. 1there is shown, in perspective, a section of a semiconductor structure or intermediate device. The structure may extend laterally or horizontally beyond the illustrated section. The illustrated planes of section extending through the structure are common to all the figures unless stated otherwise. It is noted that the relative dimensions of the shown elements, in particular the relative thickness of the layers, is merely schematic and may, for the purpose of illustrational clarity, differ from a physical structure. InFIG. 1, directions X and Y indicates a first and a second horizontal direction, respectively, (parallel to the main plane of extension of the layers) and Z indicates a vertical direction (normal to the main surface of the layers).

The structure includes in a bottom-up direction a substrate1, for instance a semiconductor substrate. An active device layer including semiconductor devices such as transistors may be fabricated on a main surface of the substrate1. The active device layer may also be referred to as a front-end-of-line portion (FEOL-portion).

A dielectric layer stack10is formed above the substrate1. The dielectric layer stack10may comprise a low-k dielectric layer12, an interface layer14and an oxide capping layer16. More generally, the dielectric layer stack10may be of any conventional type used in back-end-of-line (BEOL) interconnect structures.

A layer stack20is formed above the dielectric layer stack10. The layer stack20comprises in a bottom-up direction (i.e. parallel to the vertical direction Z) a target layer22, a lower memorization layer24and an upper memorization layer26. As may be understood from the following, the memorization layers24,26may through patterning be used to “memorize” or “store” one or more parts of a final pattern that is to be transferred to the target layer. Alternatively, the lower and upper memorization layers24,26may be referred to as the lower and upper patterning layers24,26. The target layer22may be a TiN layer. The lower memorization layer24may be a SiN layer. The upper memorization layer26may be an a-Si layer. However, other material combinations allowing etching of each one of the layers22,24,26of the stack20, selective to the other two layers of the stack20may also be used. More generally, the target layer may be formed of a first material. The lower memorization layer may be formed of a second material different from the first material. The upper memorization layer may be formed of a third material different from the first material and the third material.

FIGS. 2-5illustrate process steps for forming a first mask layer31and forming a set of trenches40therein using lithography and etching.

InFIG. 2a first lithographic layer stack30has been formed on the layer stack20. The lithographic layer stack30comprises the first mask layer31and a photoresist layer38. The first mask layer31may for instance be formed by a carbon-based patterning film, for instance an amorphous carbon film, or some other conventional organic or non-organic patterning film allowing high-fidelity pattern transfer when used in a lithographic layer stack. As shown, the layer stack30may additionally comprise one or more transfer layers32,34,36intermediate the first mask layer31and the photoresist layer38. The layer stack30may comprise an anti-reflective coating32, for instance in the form of a silicon-including layer such as SiOC. The layer stack30may comprise an organic spin-on layer34, such as a spin-on-carbon (SOC) layer. The layer stack may further comprise an additional anti-reflective coating36, for instance in the form of a spin-on-glass (SOG) layer or a silicon-including layer.

A trench pattern comprising a set of trenches39have been lithographically patterned in the photoresist layer38. Each trench of the set of trenches39is formed over a region of the target layer22where a trench of a first set of target trenches100is to be formed. As shown, the trenches39may be formed with various widths (along the first horizontal direction X) and various longitudinal dimensions (along the second horizontal direction Y). The trenches39may extend in parallel to each other.

InFIG. 3the trench pattern comprising the set of trenches39have been transferred into the transfer layers32and34to form a set of trenches35therein. The pattern transfer may comprise first transferring the trench pattern comprising the set of trenches39into the transfer layer36by etching the layer36while using the photoresist layer38as an etch mask. The transfer layer34may then be etched through the trenches in the transfer layer36. If the transfer layer34is formed by an organic material (such as a SOC), the photoresist layer38may be consumed during the etching. Thus, mainly the transfer layer36may act as an etch mask during the patterning of the transfer layer34. The trenches35in the transfer layer34may then be further transferred into the transfer layer32by etching. During the etching the transfer layer36may be consumed. Thus, mainly the transfer layer34may act as an etch mask during the patterning of the transfer layer32.

FIG. 4illustrates an optional trimming step which may be performed prior to patterning the first mask layer31. The patterned transfer layers32,34may be subjected to a short isotropic etch step, trimming the lateral dimensions of the layers32,34thus forming a trimmed trench pattern37. By trimming the lateral dimensions of the layers32,34(i.e. along the horizontal plane defined by the X and Y directions) the critical dimensions of the lithographically defined trench pattern may be reduced to the desired values prior to patterning the upper memorization layer26. Consequently, the trimming results in increasing the widths of the trenches35to form the widened trenches37in the transfer layers32,34.

InFIG. 5, the trimmed trench pattern37has been transferred into the first mask layer31to form a pattern comprising a set of trenches40. The set of trenches40extend in parallel to each other. The set of trenches40exposes an upper surface of the upper memorization layer26. The set of trenches40may be formed by etching the first mask layer31while using at least the transfer layer32, possibly also the transfer layer34(depending on etch selectivities), as an etch mask.

In an alternative approach, the lithographic layer stack30may comprise only the first mask layer31and the photoresist layer38. The set of trenches39may be lithographically patterned in the photoresist layer38. The set of trenches40may subsequently be patterned in the first mask layer31using the patterned photoresist layer38as an etch mask.

In any case, the various steps of patterning the layer stack30may use conventional etching techniques. For instance, a SOG or SiOC layer may be etched using fluorine based etching chemistries (e.g. CF4, CH3F, CHF3, CH2F2, C4F8or C4F6), a SOC or carbon-based patterning film may be etched using N2/H2or O2based etching chemistries (e.g. O2, CO2, SO2optionally supplemented with HBr or CH4).

InFIG. 6, a set of upper trenches, commonly referenced44, have been patterned in the upper memorization layer26. The set of upper trenches44comprises for instance trenches46,47and48. The set of upper trenches44extend in parallel to each other. The patterning may comprise etching the upper memorization layer26using the first mask layer as an etch mask. The pattern comprising the set of trenches40in first mask layer31have accordingly been memorized in the upper memorization layer26. A conventional etching process, such as a dry etching process, compatible with the materials forming the first mask layer31and the upper memorization layer26may be used. For instance, an a-Si layer may be etched through an carbon-based etch mask using Cl2or fluorine-based etching chemistries such as SF6.

As an alternative to the afore-mentioned trimming step, a trimming step may be applied to upper memorization layer26subsequent to patterning the upper trenches44therein. The trimming may comprise oxidizing the upper memorization layer26to form an oxide layer covering the upper memorization layer26and thereafter removing the oxide layer from the upper memorization layer26in an etch step, for instance using dHF. This technique may be applied provided the upper memorization layer26is formed of a material which may be oxidized in a controlled manner, for instance a-Si.

InFIG. 7a spacer layer has been formed on sidewalls of the upper trenches. The spacer layer50may be an oxide layer, such as silicon oxide SiO2or a metal oxide layer such as titanium oxide TiOx. A SiN layer may also be used provided SiN is not used to form the lower memorization layer24. More generally, the spacer layer50may be formed of a fourth material different from each one of the first through third materials forming the target layer22, the lower memorization layer24and the upper memorization layer26. The spacer layer50may be formed by depositing a conformal spacer layer covering the patterned upper memorization layer26, for instance in an atomic layer deposition (ALD) process. A vertical anisotropic etch may then be performed such that portions of the conformally deposited spacer layer on horizontally oriented surfaces are removed, while portions deposited on the vertically oriented sidewalls of the upper trenches44are preserved to form the final spacer layer50. As shown inFIG. 7, the spacer layer50thus defines a pair of spacer lines extending along each upper trench44, such as spacer lines50a,50balong the upper trench47and spacer lines50c,50dalong the upper trench48. As shown inFIG. 7, the spacer layer50may also form on end walls of the trenches44. The end wall portions layer50accordingly connect the spacer lines50a,50band50c,50dformed on the mutually opposite trench sidewalls.

FIG. 8-9illustrate forming of a first block pattern58above the lower memorization layer24. The first block pattern58comprises a set of first blocks60,62. Each first block60,62extends across an upper trench46,48in the upper memorization layer26.

InFIG. 8a first block mask layer52has been formed to cover the patterned upper memorization layer26. The first block mask layer52may be formed by a SOC layer or some other organic spin-on layer. A photoresist layer has been formed above the first block mask layer52and lithographically patterned to define a photoresist block mask comprising a set of resist blocks54,56. Each resist block54,56extends across an upper trench46,47in the upper memorization layer26(c.f.FIG. 7).

InFIG. 9, the first block mask layer52has been patterned to form the first block pattern58. The patterning may comprise etching the first block mask layer52using the photoresist block mask54,56as an etch mask. Accordingly, a set of first blocks60,62may be patterned in the first block mask layer52. Following pattering of the first block mask layer52, the resist blocks54,56may be stripped from the first blocks60,62. Similar to the patterning of the first mask layer31, the patterning of the first block mask layer52may comprise a number of transfer steps into one or more transfer layers intermediate the layers52and the photoresist layer (such as anti-reflective coating(s) of SOG and/or SiOC or another silicon-including layer).

InFIG. 10a first set of lower trenches, commonly referenced64, have been patterned in the lower memorization layer24and comprising for instance trenches66,67,68. The patterning may comprise etching the lower memorization layer24while using the patterned upper memorization layer26, the spacer layer50and the first block pattern58as an etch mask. The first lower trenches64exposes an upper surface of the target layer22. An etching process, such as a dry etching process, allowing etching of the lower memorization layer24selectively to the first blocks60,62, the spacer layer50and the upper memorization layer26may be used. For instance, a SiN layer may be etched selectively to SOC, a-Si and an oxide such as a silicon or metal oxide (e.g. SiO2or TiOx) using fluorine-based etching chemistries.

As is more clearly visible inFIG. 11, where the first blocks60,62have been removed, at least a subset of the lower trenches64, such as first lower trenches66,67are interrupted by a respective trench interruption. The trench interruptions are formed by the portions24a,24bof the lower memorization layer24preserved under the first blocks60,62. Accordingly the trench66forms an interrupted or discontinuous trench formed by two trench portions66a,66b. Correspondingly, the trench67forms an interrupted or discontinuous trench formed by two trench portions67a,67b.As may be seen fromFIG. 11, interrupted trenches with more relaxed tip-to-tip separation may be formed without relying on a block-based technique, i.e. by being directly lithographically defined and etched into the first mask layer31.

FIG. 12-14illustrate forming of a second block pattern82above the (once) patterned lower memorization layer24. The second block pattern82is formed by again patterning the (already once patterned) upper memorization layer26. As may be seen inFIG. 14the second block pattern82comprises a set of second blocks26a,26b,each second block being formed by a respective portion26a,26bof the upper memorization layer26remaining after the second block patterning.

InFIG. 12, a second block mask layer70has been formed to cover the patterned lower and upper memorization layers24,26. The second block mask layer70fills the first set of lower trenches64in the lower memorization layer24and the upper trenches44in the upper memorization layer26. The second block mask layer70may be formed by a SOC layer or some other organic spin-on layer. A photoresist layer has been formed above the second block mask layer70and lithographically patterned to define a photoresist block mask comprising a set of resist blocks72,74. Each resist block72,74is formed over a respective portion26a,26bof the upper memorization layer26.

InFIG. 13, the second block mask layer70has been patterned to form a second block mask78. The second block mask78comprises a set of second mask blocks79,80. The patterning may comprise etching the second block layer70using the photoresist block mask72,74as an etch mask. The etching may be stopped when the upper surface of the target layer22is exposed in the lower trenches64. Accordingly, following the patterning of the second block mask layer70, the upper surface of the target layer22is again exposed in the lower trenches64in the lower memorization layer. The patterning of the second block mask layer70may proceed in a similar fashion as the above described patterning of the first block mask layer52.

InFIG. 14, the (once patterned) upper memorization layer26has been patterned to form the second block pattern82. The patterning may comprise etching the remaining portions of the upper memorization layer26using the second block mask78as an etch mask. The second block pattern82is formed by the portions26a,26bof the upper memorization layer26preserved under the second mask blocks79,78. Following pattering of the second block mask layer70, the resist blocks79,78may be stripped from the second blocks26a,26b.The upper memorization layer26may be etched using any of the etching chemistries discussed in connection with the first patterning of the upper memorization layer26.

Still with reference toFIG. 14, a first set of target trenches, commonly referenced100, have been patterned in the target layer22under the first set of lower trenches64. The first set of lower trenches64exposes an upper surfaces of an underlying layer, i.e. in the illustrated process flow formed by an upper surface of the dielectric layer stack10. The first set of target trenches100correspond to the first set of lower trenches64. The first set of target trenches100extend in parallel to each other. The first set of target trenches100comprises for instance first target trenches102and104. As may be more clearly seen inFIG. 15, the first target trench102is formed by two trench portions102a,and102binterrupted by a trench interruption formed by a portion of the target layer22preserved under the portion24bof the lower memorization layer24.

The patterning of the first set of target trenches100may comprise etching the target layer22through the first set of lower trenches64in the lower memorization layer26. Accordingly, the (once) patterned lower memorization layer26and the spacer layer50may be used as a combined etch mask during the patterning of the target layer22. The etching may be tuned such that the second block mask78and/or at least the second block pattern82are at least partially preserved following formation of the first set of target trenches100. Depending on the materials of the target layer22and the upper memorization layer26, and the etching chemistry used during the second patterning of the upper memorization layer26, the first set of target trenches100and the upper memorization layer26may be etched simultaneously, i.e. by the same etching chemistry, and selectively to the spacer layer50and the lower memorization layer24. For instance, a-Si and TiN may be etched simultaneously and selectively to an oxide such as a silicon or metal oxide (e.g. SiO2or TiOx) and SiN using an Cl2-based etching chemistry.

Following patterning of the first set of target trenches100the second block mask78(or remaining portions thereof) may be removed from the second block pattern82by etching. The resulting structure is shown inFIG. 15.

FIGS. 16-17illustrate process steps for forming a second mask layer86and forming a set of trenches92therein using lithography and etching.

InFIG. 16a second lithographic layer stack84has been formed above the patterned lower memorization layer24and the second block pattern82. The lithographic layer stack84comprises the second mask layer86and a photoresist layer90. The second mask layer86may be formed by a SOC layer or some other organic spin-on-layer. As shown, the layer stack30may additionally comprise one or more transfer layers88intermediate the second mask layer86and the photoresist layer90, such as an anti-reflective coating, for instance of SOG or SiOC.

A trench pattern comprising a set of trenches91have been lithographically patterned in the photoresist layer90. Each trench of the set of trenches91is formed over a respective remaining portion of the (once patterned) lower memorization layer24. Moreover, each trench of the set of trenches91is formed over a region of the target layer22where a trench of a second set of target trenches106is to be formed. As shown, the trenches91may be formed with various widths (along the first horizontal direction X) and various longitudinal dimensions (along the second horizontal direction Y). The trenches39may extend in parallel to each other. The trenches39may further extend in parallel to the first set of lower trenches64already formed in the lower memorization layer24.

InFIG. 17, the trench pattern comprising the set of trenches91have been transferred into the transfer layer88and the second mask layer86to form a set of trenches92. The set of trenches92comprises for instance trenches93,94. The set of trenches92exposes an upper surface of the remaining portions of the (once patterned) lower memorization layer24. At least a subset of the trenches92, such as trenches93,94may be formed to expose and extend along one or more spacer lines50b,50c,50d.At least a subset of the trenches, such as the trench94, may be formed to expose one or more second blocks26a,26bof the second block pattern82.

The pattern transfer may comprise first transferring the trench pattern comprising the set of trenches91into the transfer layer88by etching the layer88while using the photoresist layer90as an etch mask. The second mask layer86may then be etched through the trenches in the transfer layer88. If the second mask layer86is formed by an organic material, the photoresist layer90may be consumed during the etching. Thus, mainly the SOG transfer layer88may act as an etch mask during the patterning of the second mask layer86. Optionally, trimming of the trench pattern may be performed, analogous to the trimming of the trenches in the mask layer stack30.

InFIG. 18, a second set of lower trenches96have been patterned in the (once patterned) lower memorization layer24. The patterning may comprise etching the lower memorization layer24using the second mask layer86, the spacer layer50and the second block pattern82as an etch mask. The second set of lower trenches96exposes an upper surface of the (once patterned) target layer22. Any of the etching processes mentioned in connection with the patterning of the first set of lower trenches64may be used for etching the second set of lower trenches96.

As is visible inFIG. 18at least a subset of the second lower trenches96, such as the second lower trench98, are interrupted by one or more trench interruptions24c,24d,each trench interruption24c,24dbeing formed by a portion24c,24dof the lower memorization layer24preserved under a respective one of the second blocks78,80. Accordingly the trench98forms an interrupted or discontinuous trench formed by three trench portions98a,98b,98c.

FIG. 19is a plan view along line A-A indicated inFIG. 18, showing more clearly the alternating arrangement of the first set of lower trenches64and the second set of lower trenches96. The trenches67,68of the first set of lower trenches64and the trenches97,98of the second set of lower trenches96are arranged alternatingly. Each trench of this subset of trenches67,68,97,98is separated from a neighboring one of this subset by a distance defined by the thickness of the spacer layer50.

InFIG. 20a second set of target trenches106have been patterned in the target layer22under the second set of lower trenches96. The second set of target trenches106exposes an upper surfaces of the underlying layer, i.e. in the illustrated process flow formed by the upper surface of the dielectric layer stack10. As may be seen inFIG. 20, the target trenches102,104of the first set100and the target trenches108,110of the second set106forms a subset of target trenches which are arranged alternatingly. Each trench of this subset of trenches67,68,97,98is separated from a neighboring one of this subset by a distance defined by the thickness of the spacer layer50.

The patterning of the second set of target trenches106may comprise etching the target layer22through the second set of lower trenches96in the lower memorization layer26. Accordingly, the (twice) patterned lower memorization layer26and the spacer layer50may be used as a combined etch mask during the second patterning of the target layer22. Any of the etching processes mentioned in connection with the patterning of the first set of target trenches100may be used for etching the second set of target trenches106.

Following patterning of the second set of target trenches106the remaining portions of the lower memorization layer26and the spacer layer50may be removed from the patterned target layer22by etching. The resulting structure is shown inFIG. 21.

The method may then proceed with patterning the dielectric layer stack10using the target layer22as an etch mask to form a set of trenches in the dielectric layer. The dielectric layer trenches may subsequently be filled with a conductive material to form a pattern of conductive paths of an interconnect structure.

In the above, the disclosure has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the disclosure, as defined by the appended claims.

For instance, according to an alternative process flow, the first and second sets of target trenches100,106in the target layer22may instead of being patterned in a sequential approach, be patterned simultaneously:

The alternative process may proceed as disclosed with reference toFIGS. 1-12above. The second block mask layer70has accordingly been formed to cover the patterned lower and upper memorization layers24,26and accordingly fill the first set of lower trenches64. However, as shown inFIG. 22, the patterning of the second block mask layer70may comprises etching the second block mask layer70to form the second block mask78comprising the set of second mask blocks79,80and such that portions170of the second block mask layer70remain in the first set of lower trenches64of the lower memorization layer24. The etching of the second block mask layer70may be stopped when an upper surface of the patterned upper memorization layer26is exposed. A thickness portion of the second block mask layer70may accordingly remain also in regions exposed by the resist block mask72,74, thereby forming the portions170filling the first set of lower trenches64.

InFIG. 23the (once) patterned upper memorization layer26has been patterned to form the second block pattern82comprising second blocks26a,26b.The patterning may, like inFIG. 14, comprise etching the remaining portions of the upper memorization layer26using the second block mask78as an etch mask. During the patterning, the portions170of the second block mask layer70remaining in the first set of lower trenches64may mask the target layer22, thus counteracting etching of the target layer22through the first set of lower trenches64.

InFIG. 24, the second block mask78and the portions of the second block mask layer70have been removed subsequent to forming the second block pattern82. The target layer22is thereby exposed in the first set of lower trenches64. The process may thereafter proceed in the manner disclosed in connection withFIGS. 16-17(forming the second mask layer86and the set of trenches92),FIG. 18(patterning the second set of lower trenches96in the lower memorization layer24). However, instead of thereafter merely patterning the second set of target trenches102in the target layer22, the first and second set of target trenches100,106may be patterned simultaneously in the target layer22by etching the target layer22and using the (twice) patterned lower memorization layer24as an etch mask. Following patterning of the first and second sets of target trenches100,102the remaining portions of the lower memorization layer26and the spacer layer50may be removed from the patterned target layer22by etching to arrive at the resulting structure shown inFIG. 21.