Method of manufacturing a package

Provided is an ESD protection circuit for CDM capable of preventing a high current from flowing and preventing breakage when a battery is connected with reverse polarity. The ESD protection circuit employs a circuit configuration in which transistor elements are interposed in series to OFF transistors (11 and 13) included in the ESD protection circuit for CDM so that parasitic diodes of the transistor elements are connected to parasitic diodes of the OFF transistors in a reverse direction.

RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2011-072736 filed on Mar. 29, 2011, the entire content of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electro-static discharge (ESD) protection element for preventing a high current from flowing and preventing breakage even when a battery is connected with reverse polarity by mistake.

2. Description of the Related Art

As a conventional input circuit for a semiconductor integrated circuit (hereinafter, referred to as IC), a circuit as illustrated inFIG. 4has been known (see, for example, Japanese Patent Application Laid-open No. Hei 7-153846 (FIG. 1)).

The IC includes a positive (plus) power supply terminal121, a negative (minus) power supply terminal122, and at least one input terminal120. The positive power supply terminal121is connected to a plus terminal of a battery101and the negative power supply terminal122is connected to a minus terminal of the battery101. Between the input terminal120and the negative power supply terminal122, a main ESD protection circuit100is normally disposed in the vicinity of a pad of the IC.

An internal circuit (inverter)130that receives a signal of the input terminal120is provided. As charged device model (CDM) measures for protecting a gate thereof from electro-static discharge (ESD), an ESD protection circuit110is disposed near the internal circuit130. The ESD protection circuit110includes an N-channel transistor11, a P-channel transistor13, and a resistor15. Drains of the N-channel transistor11and the P-channel transistor13are connected to the gate of the internal circuit130. A gate, a source, and a substrate of the N-channel transistor11are connected to VSS. A gate, a source, and a substrate of the P-channel transistor13are connected to VDD. The N-channel transistor11and the P-channel transistor13are in an OFF state (high impedance state). In a normal operating state, the presence or absence of the N-channel transistor11and the P-channel transistor13does not affect the operation of the internal circuit. The resistor15for ESD protection may be a resistor having a given value (for example, about 1 kΩ) interposed by design, or may be a parasitic resistance of wiring of the IC.

In a CDM, in the state in which the IC is charged to a high voltage, when the voltage is discharged from the input terminal120, electric charges of the internal circuit130on the substrate side are generally discharged rapidly via the substrate and the main ESD protection circuit100. On the other hand, electric charges of the gate of the internal circuit130are discharged slowly because of the resistor15. As a result, a high voltage is applied instantaneously between the gate and the substrate of the internal circuit130, and the breakage of the gate of the internal circuit may occur. In order to prevent the breakage, the OFF transistors11and13are interposed between the gate of the internal circuit and the positive power supply terminal121and the negative power supply terminal122, respectively, so that the OFF transistors11and13are broken down before a high voltage is applied between the gate of the internal circuit and the respective power supply terminals. In this way, the gate of the internal circuit can be prevented from being applied with a high voltage, and the breakage in the CDM can be prevented.

FIG. 5illustrates an example of an image diagram of IC layout. There are three pads of a VDD PAD connected to the VDD terminal, an IN PAD connected to the IN terminal, and a VSS PAD connected to the VSS terminal. In the vicinity of the IN PAD, the main ESD protection circuit100is laid out. The internal circuit130is laid out inside the IC, and, in the vicinity thereof, the ESD protection circuit110for CDM measures is laid out.

FIG. 5illustrates only three pads, but a normal IC includes a larger number of pads and circuits.

The conventional protection circuit, however, has the following problem. When the battery is connected with reverse polarity, the parasitic diodes of the respective ESD protection elements are biased in the forward direction, and a current flows to generate heat.

SUMMARY OF THE INVENTION

Therefore, it is an object of the present invention to solve the conventional problem and provide an ESD protection circuit capable of preventing a current from flowing and preventing breakage even when a battery is connected with reverse polarity.

The present invention solves the above-mentioned problem by employing a circuit configuration in which transistor elements are interposed in series to OFF transistors included in an ESD protection circuit for CDM so that parasitic diodes of the transistor elements are connected to parasitic diodes of the OFF transistors in a reverse direction.

According to the ESD protection circuit of the present invention described above, a high current can be prevented from flowing to an IC and the breakage can be prevented even when a battery is connected with reverse polarity.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to the drawings, embodiments of the present invention are described.

FIG. 1is a circuit diagram of an electro-static discharge (ESD) protection circuit according to a first embodiment of the present invention. An ESD protection circuit110according to the first embodiment of the present invention includes an N-channel transistor11, P-channel transistors12,13, and14, and a resistor15. The resistor15is similar to the conventional one, and may be provided by design or may be a parasitic resistance of wiring.

A gate, a source, and a substrate of the N-channel transistor11are connected to VSS, and a drain thereof is connected to a source and a substrate (well) of the P-channel transistor12. A gate of the P-channel transistor12is connected to VSS, and a drain thereof is connected to a gate of an internal circuit130, the resistor15, a drain of the P-channel transistor13, and a gate of the P-channel transistor14. A drain of the P-channel transistor14is connected to VDD, and a source and a substrate (well) thereof are connected to a source and a substrate (well) of the P-channel transistor13. A gate of the P-channel transistor13is connected to VDD, and a drain thereof is connected to the gate of the internal circuit130, the resistor15, the drain of the P-channel transistor12, and the gate of the P-channel transistor14. Reference symbols11D,12D,13D, and14D represent parasitic diodes of the N-channel transistor11and the P-channel transistors12,13, and14, respectively.

Comparing with the conventional ESD protection circuit ofFIG. 4, the N-channel transistor11and the P-channel transistor13function as OFF transistors similarly to the conventional ones and the P-channel transistors12and14are added.

Next, the operations performed when a battery is normally connected and when the battery is connected with reverse polarity are described.FIG. 1illustrates the state in which the battery is normally connected. In this state, each of the N-channel transistor11and the P-channel transistor13functions as an OFF transistor similarly to the conventional ones and the impedance thereof is high. Therefore, even if the P-channel transistors12and14are added, the operation is not affected.

Next, in a CDM, in the state in which an IC is charged to a high voltage, when the voltage is discharged from the input terminal120, even if the gate of the internal circuit130tries to have a higher potential than that of the VSS terminal, the P-channel transistor12is turned ON so that a gate voltage of the internal circuit130is applied to the drain of the N-channel transistor11. Accordingly, the N-channel transistor11is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit130and VSS. On the other hand, even if the gate of the internal circuit130tries to have a lower potential than that of the VSS terminal, the parasitic diode11D of the N-channel transistor11is turned ON so that substantially the same voltage as that of the VSS terminal is applied to the source of the P-channel transistor12. Accordingly, the P-channel transistor12is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit130and VSS.

Similarly, even if the gate potential of the internal circuit130tries to be higher than that of the VDD terminal, the P-channel transistor13is turned ON so that the voltage of the VDD terminal is applied to the source and the substrate (well) of the P-channel transistor14. Accordingly, the P-channel transistor14is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit130and VDD. On the other hand, even if the gate of the internal circuit130tries to have a lower potential than that of the VDD terminal, the P-channel transistor14is turned ON so that the voltage of the VDD terminal is applied to the drain of the P-channel transistor13. Accordingly, the P-channel transistor13is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit130and VDD.

In other words, the ESD protection circuit for CDM functions similarly to the conventional one.

On the other hand, when the battery is connected with reverse polarity, no path in which diodes are connected in the forward direction is formed between VDD and VSS (because diodes in the reverse direction are always connected in series), and hence no current flows as opposed to the conventional case. Further, even when the input terminal120is connected to VDD or VSS, no path in which diodes are connected in the forward direction is formed between the input terminal120and VDD or VSS (because diodes in the reverse direction are always connected in series), and hence no current flows.

FIG. 2illustrates a cross-sectional diagram of the N-channel transistor11and the P-channel transistors12,13, and14. The transistors are connected to the input terminal120(IN) via the resistor15, but, inFIG. 2, the resistor15is omitted. On a P-substrate, a first N-well and a second N-well are provided. The P-channel transistors13and14are manufactured in the first N-well, and the P-channel transistor12is manufactured in the second N-well.

As described above, the N-channel transistor11and the P-channel transistor12have an effect to the CDM between VSS and the gate input of the internal circuit130, and the P-channel transistors13and14have an effect to the CDM between VDD and the gate input of the internal circuit130. Therefore, it is apparent that the effect to the CDM can be obtained even only with the transistors between the internal circuit and one of VDD and VSS.

FIG. 3illustrates an ESD protection circuit according to a second embodiment of the present invention. The difference fromFIG. 2resides in that the P-channel transistors13and14switch their positions between VDD and the input gate of the internal circuit. In other words, the gate, the source, and the substrate (well) of the P-channel transistor13are connected to VDD, and the drain thereof is connected to the drain of the P-channel transistor14, and the source, the substrate (well), and the gate of the P-channel transistor14are connected to the drain of the P-channel transistor12, the resistor15, and the gate of the internal circuit130.

Similarly to the first embodiment, in the state in which the battery is normally connected (state ofFIG. 3), the transistors13and14are turned OFF (in high impedance state) and therefore do not affect the operation.

Next, in a CDM, in the state in which an IC is charged to a high voltage, when the voltage is discharged from the input terminal120, even if the gate of the internal circuit130tries to have a higher potential than that of the VDD terminal, substantially the same voltage as that of the VDD terminal is applied to the drain of the P-channel transistor14because the parasitic diode13D of the P-channel transistor13is in the forward direction. Accordingly, the P-channel transistor14is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit130and VDD. On the other hand, even if the gate of the internal circuit130tries to have a lower potential than that of the VDD terminal, substantially the same voltage as that of the gate of the internal circuit130is applied to the drain of the P-channel transistor13because the parasitic diode14D of the P-channel transistor14is in the forward direction. Accordingly, the P-channel transistor13is broken down as an OFF transistor, and a high voltage difference is not applied between the gate of the internal circuit130and VDD.

When the battery is connected with reverse polarity, similarly to the first embodiment, no path in which diodes are connected in the forward direction is formed between VDD and VSS (because diodes in the reverse direction are always connected in series), and hence no current flows. Further, even when the input terminal120is connected to VDD or VSS, no path in which diodes are connected in the forward direction is formed between the input terminal120and VDD or VSS (because diodes in the reverse direction are always connected in series), and hence no current flows.

Further, the N-channel transistor11and the P-channel transistors12,13, and14serving as ESD protection elements for CDM have the purpose of dissipating electric charges of the gate of the internal circuit130, and hence, even when the W lengths (transistor widths) of the N-channel transistor11and the P-channel transistors12,13, and14are smaller than the W length of the main ESD protection element100, a sufficient effect can be obtained. The W lengths may be 50 μm or less.