Lateral high-side and low-side high-voltage devices with low specific on-resistances are made in a first and in a second surface voltage-sustaining region, respectively. In the on-state of high-side MOST (the right portion of the figure), the voltage across its source and its drain is very low and only layer 5 (p-type) is depleted to a large extent, layer 6 and layer 7 remain neutral and can serve as drift region(s) of electrons and/or holes. The drift region can be used for a single n-MOST or p-MOST, or even a parallel connection of n-MOST and p-MOST as shown in the figure. In the off-state of the high-side MOST, the voltage across its source and its drain is very large, but the voltage across its drain and the substrate 1 can be very low, and all of the layers in the first surface voltage-sustaining region are depleted, the depleted layer 5 produces an optimum variation lateral density of charge.The low-side MOST (the left portion of the figure) is similar to the high-side MOST.

TECHNICAL FIELD

The present invention relates to semiconductor high-voltage devices and high-power devices, more particularly to surface voltage-sustaining structure for lateral high-side and low-side high-voltage and high-power devices in High-Voltage Integrated Circuits (HVICs) and Power Integrated Circuits (PICs).

BACKGROUND OF THE INVENTION

As shown inFIG. 1, a conventional HVIC includes four portions: a low-voltage control circuit, a low-side driver connected to ground, a high-voltage level shifter and a high-side driver. The voltage of the tub shown in this figure can be varied from the voltage of the ground up to the voltage of the bus, which has a high-voltage related to the ground.

In Ref. [1], the BCD techniques are presented for implementing the four circuits shown in the block ofFIG. 1. However, DI and JI techniques must be used in BCD techniques. Therefore, the technologies employed are normally incompatible with conventional CMOS and BiCMOS technologies. Furthermore, the areas of the high-voltage devices made by BCD technologies are normally large. As a result, the costs of such HVICs or PICs are high.

In Ref. [2] and [3], the present inventor proposed techniques to implement high-side and low-side high-voltage devices by taking advantage of optimum variation lateral doping. The techniques are CMOS and/or BiCMOS technologically compatible, so that high-side and low-side high voltage devices as well as high-side drivers can be realized on a single chip with lower cost.

However, the lateral power MOSTs, especially the lateral high-side power MOST made by such techniques has a large specific on-resistance. This can be illustrated byFIG. 2, the middle portion of which schematically shows the structure of a high-side n-MOST. When a high voltage related to the substrate is applied on the drain electrode DH, the n-layer of the first surface voltage-sustaining region is depleted in a large extent, remains a small part of it to be neutral. That means it offers a high specific on-resistance.

OBJECT OF THE INVENTION

The object of this invention is to provide a surface voltage-sustaining structure for obtaining both high-side and low-side lateral devices having specific on-resistances lower than those given by U.S. Pat. No. 6,310,365 B1 with other advantages of that patent remaining unchanged.

SUMMARY OF THE INVENTION

According to the present invention, a surface voltage-sustaining structure for semiconductor devices is provided. It consists of two surface voltage-sustaining regions formed on the top of an n-type semiconductor substrate. The first voltage-sustaining region is in an area of a p-type layer on the substrate. The middle of this area is the largest voltage terminal of the high-side device, wherein the largest voltage means a highest negative potential with the potential of the substrate taken as zero. The edge(s) of this area has (have) a floating voltage. The p-layer is covered with thin n-type layer except those areas around the middle of said area. The average ionized acceptor density of p-layer subtracted by the donor density of the n-layer decreases gradually or stepwise from a value of NBWppat the middle to a very small value at the edge(s), where NBstands for the doping concentration of the n-type substrate, Wppstands for the depletion width of a one-sided abrupt parallel plane junction made by the same substrate under its breakdown voltage. The applied breakdown voltage, VB, across the middle and the edge is a negative value. It is required that the acceptor density of this p-layer should by close to 2NBWppat the place close to the middle.

The n-layer covered on the p-layer can be again covered by a p-layer and even a multiple alternately covering n-layer and p-layer can be used. In calculation of the average effective ionized acceptor density, all the ionized impurities should be taken into account.

In the case of the voltage of the floating terminal equals to that of the largest voltage terminal, then, except the lowest p-layer, all the n-layer and p-layer in the surface voltage-sustaining region are only depleted very small parts of them, because they are equi-potential and a negligibly small parts of them to be depleted are enough to support the built-in voltage (Vbi) between each neighboring n-layer and each p-layer. The first surface voltage-sustaining region and the substrate is then a plane junction alike.

The voltage between the floating terminal and the substrate is sustained by the second surface voltage-sustaining region. The second surface voltage-sustaining region has the same structure as the first surface voltage-sustaining region. The end of the n+-region of this region is connected to the substrate, that is, they have the same potential. This potential is assigned to be zero in this patent. The doping density of the lowest p-layer in the second surface voltage-sustaining region can be set as the same as the first region, but can also be different to the first region. However, the maximum acceptor density near the floating voltage terminal should not be smaller NBWpp.

In both regions, a decrease of the effective average density of the ionized acceptor from the position of the largest voltage to the position of the smallest voltage must be realized. There are lots of methods to realize the variation of the effective charge density as described in Ref. [2] and Ref. [3]. Attention should be paid that in this patent, the real variation of the effective charge density is not due to a variation of the compensation of an n-layer on its top, but due to a variation of the density of the lowest p-layer itself. Not to mention, such a variation can also be realized by using some layout mentioned in Ref. [3].

The majority lateral devices using this invention has a advantage that the carriers used in the on-state are the electrons in the n-layer and/or the holes in the p-layer above the bottom p-layer. The bottom p-layer serves for sustaining the voltage to the substrate, whereas the layers above the bottom p-layer serves for the drifting of the carriers, due to that they are neutral in the conduction-state. Therefore, it provides a much smaller specific on-resistance.

The p-type and n-type semiconductor stated above can be exchanged and then the largest voltage means a high positive voltage.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A reverse-biased p-n junction (diode) is the basis of most semiconductor devices, such as BJT, JFET and MOSFET. Therefore, the description of this invention is introduced by an explanation of the surface voltage-sustaining structures of the diode shown inFIG. 3andFIG. 4.

Under a reverse biased condition, the diode shown inFIG. 3sustains the voltage by a depletion region in the n-type substrate1. The p-type layer2has a corresponding depletion region with opposite charges. The depletion region has a maximum width in the middle, i.e., on the dotted-dash line under the anode A, and a very small width under the cathode K. According to Ref. [4] and [5], the largest breakdown voltage can be achieved is 95% of that of a parallel plane abrupt junction by making the depleted acceptor density of p-layer2subtracted by the depleted donor density of n-layer3being a proper function of the distance from A (towards K).

The same argument can be applied toFIG. 4. The difference of this figure andFIG. 3is only that here another p-layer4is on the n-layer3. The effective ionized acceptor is the result of ionized density of p-layer2plus that of p-layer4minus that of n-layer3.

It is required that, to get the maximum breakdown voltage, p-layer2and the layers above it must be fully depleted, except the areas in small portions around anode A and cathode K. All the fully depleted layers (except the substrate) together construct a surface voltage-sustaining region.

The structure shown inFIG. 3andFIG. 4can not only form low-side diodes but also can form high-side diodes, as shown inFIG. 5,FIG. 6,FIG. 7andFIG. 8. If the p-layer5and n-layer6inFIG. 5are made the same as the p-layer2and n-layer3inFIG. 3respectively, then the high-side diode can have the same breakdown voltage as the low-side diode. Note that the potential of the cathode KHmay have the same potential as the substrate, but may also have a potential close to that of the anode AH. The latter case occurs when the high-side diode is in conduction. Therefore, a second surface voltage-sustaining region must exist between KHand the edge at the surface, since the potential at the edge is the same as the substrate (“ground”). This region is constructed by layer2and layer3, as shown inFIG. 5.

The subscripts H and L of the symbols representing electrodes refer to the electrode of the high-side device in the first surface voltage-sustaining region and the electrode of the low-side device in the second surface voltage-sustaining region respectively.

Note that there is a region to separate p-layer5and p-layer2and to separate n-layer6and n-layer3. This region is made to avoid direct connection of AHand KHand direct connection of KHand the substrate, and called as isolation region in this patent.

FIG. 6shows a high-side diode and a low-side diode by using the basic structure ofFIG. 3. Due to that there is an isolation region between KHand AL, these two electrodes can have a different potential, of course, they can be also made to be equal potential by an outer connection, if necessary.

FIG. 7shows a high-side diode by using the basic structure ofFIG. 4. The second surface voltage-sustaining region, which includes p-layer4, n-layer3and p-layer2, can be used to make a low-side diode, as shown inFIG. 8p-layer5, p-layer7and n-player6should be the same as p-layer2, p-layer4and n-layer3, if one wants the high-side diode have the same breakdown voltage as that of the low-side diode.

As stated before, once one can make a high-voltage diode, then it can be used to realize a high-voltage transistor.FIG. 9shows a low-side MOST by using the basic structure ofFIG. 3. The source-body of this MOST is connected to the middle of p-layer2, it has a negative high voltage to the substrate, which is connected to the drain D. The right part of this figure shows the symbol of this device, where D is the drain electrode, S is the source electrode and G is the gate electrode. The shaded area10stands for the gate oxide or gate insulator. S is connected both to the n+-source region8and source-body region through p+-region9. The difference of this lateral MOST to that presented in Ref. [2] is: p-layer2is for sustaining the voltage to the substrate, but not for making a drift region, the latter is made by n-layer3. Assume that the surface voltage-sustaining region should contribute a charge density corresponding to a dose D0to obtain the maximum reverse voltage, where D0stands for NBWpp, then, the dose D0, the effective number of ionized acceptors in unit area, should decrease as the lateral distance increases from the middle line, which is through the source S, and eventually approaches to zero.

One method to realize such a dose is as follows. The dose of p-layer2starts from a value of 2D0at a certain lateral distance from the middle line (dotted-dash line in the figure), starts decreasing gradually from the left edge of gate electrode G according to the lateral distance, and eventually becomes a value of D0. The dose of n-layer3is a constant, D0. Thus, when a voltage close to the breakdown voltage is applied, the effective depleted acceptor density under the left edge of G is D0, since half of acceptor density in p-layer2has been offset by 1D0of donor density of n-layer3. At the end of the surface voltage-sustaining region (close to the drain electrode), the effective acceptor density is zero, since 1D0of p-layer2is totally offset by 1D0of n-layer3.

A high-side high-voltage MOST can be used by similar method as shown inFIG. 10, where SH, DHand GHstand for the electrodes of source, drain and gate of the high-side MOST respectively. SHis connected to n+-region11and p+-region12, the latter is connected to source-body, layer13is the gate oxide or gate insulator. The advantage of this high-side MOST compared to that of Ref. [3] is obvious. The specific on-resistance here is much lower than that in Ref. [3]. This is because, when the high-side MOST is in conduction-state, DHhas almost the same potential of that of SH, the latter has a reverse voltage −VRto the substrate. The depleted dose for supporting this voltage relies on p-layer5and has nothing to do with n-layer6, which is now a neutral drift region, all the electrons in this region are the carriers for conduction. p-layer5and n-layer6together construct the first surface voltage-sustaining region, and p-layer2and n-layer3together construct the second surface voltage-sustaining region. There is a p-region between the two voltage-sustaining regions, to separate n-layer6and n-layer3to avoid electrons flowing directly from the substrate to DH.

The second voltage-sustaining region shown inFIG. 10can also be used to form a low-side MOST.FIG. 11shows such a case. An n-region between p-region14and p-region15is set to avoid direct connection of the source of the low-side device, SL, to the source of the high-side device, SH. It should be mentioned that DHisn't necessary to be directly connected with SL. A small voltage difference between them is allowable. However, in most practical cases, they are connected together and form a tub. The right portion ofFIG. 11is the circuit's symbols of the devices.

In order to further reduce the on-resistance of the high-side MOST, the voltage-sustaining region can be made having multiple layers.FIG. 12shows a structure of 3-layers. One of the design methods is like this. The top p-layer4has a dose of D0, n-layer3has a dose close to D0, the bottom p-layer2has a dose of D0at the place of the largest voltage and a dose of zero at the place close to D. Thus, in conduction state, n-layer3is neutral, providing a small specific on-resistance.

However, there is still another method can produce a further small specific on-resistance. The dose of p-layer2at the place of the maximum voltage is set to be 2D0, at the place of the minimum voltage is set to be D0. The dose of p-layer4is D0and the dose of n-layer3is 2D0. Thus, in conduction state, the dose of available carriers (electrons) in n-layer is almost 2D0.

Note that in Ref. [3], the variation of charge density in the off-state is due to a compensation of flux from a variation of the charge density of the upper layers. However, in this invention, although a dose of D0of the bottom layer is compensated by the upper layers, the variation of average dose is due to the remaining dose of the bottom itself.

The dose of n-layer3should not be larger than 2D0. Since when n-layer3is fully depleted, half of its dose produces a flux upwards and terminated by charge of p-layer4, the remaining half produces a flux downwards and terminated by the charge of p-layer2. These two fluxes correspond a field of qD0/εseach, where q is the electron charge and εsis the permittivity of the semiconductor. This field is already the critical field of breakdown, Ecrit.

Actually, as stated in Ref. [4], there is another lateral field parallel to the surface, which has a maximum value of about Ecrit/3. Therefore, the component of the field perpendicular to the surface should not exceed 0.94Ecrit. As a consequent, the allowable dose of n-layer3is less than 1.88D0. Furthermore, if any layer is made by interdigitated layout, then a field perpendicular to both of the above-stated components occurs. In that case, the dose of n-layer3should be less than 1.8D0.

FIG. 13shows a high-side MOST by using the basic structure ofFIG. 7, where the left portion is the second voltage-sustaining region and the right portion is the first voltage-sustaining region.

FIG. 14shows a high-side MOST and a low-side MOST by using the basic structure ofFIG. 7. In the conduction-state of the high-side MOST, n-layer6and p-layer7are neutral due to the potential difference between DHand SHare very small. Thus, unlike the techniques provided by Ref. [3], the specific on-resistance of this patent is very small.

A high-voltage CMOS can also be made by using the two surface voltage-sustaining regions.FIG. 15shows one of the examples. The source SHof the high-side n-MOST is connected to the largest (negative) voltage and the source SLof the low-side p-MOST is connected to the smallest voltage, i.e., the substrate. The source region of the low-side p-MOST is p+-region17, which is connected to the source-body via the electrode SLand n+-region16. The gate oxide or gate insulator is shown as the shaded area18. The symbols of circuits of the CMOS are shown in the right portion of the figures, where the dash lines are the outer connection if it is necessary.

FIG. 16shows another example of high-voltage CMOS, where the high-side is a p-MOST and the low-side is an n-MOST. The drain-electrode DHof high-side p-MOST is connected to the maximum (negative) voltage and the drain-electrode DLof low-side n-MOST is connected to the smallest voltage, i.e., the substrate. The source electrode SHof the high-side p-MOST is connected to a source p+-region and source body via n+-region20. The shaded area21is the gate oxide or gate insulator. The symbols of circuits of this CMOS are shown in the right portion of the figure.

The specific on-resistance of the high-side p-MOST is larger than that of the low-side n-MOST, due to that the dose of p-layer7is not very large and the mobility of holes is normally lower than that of electrons. In order to overcome this drawback, it is proposed a method in this invention as shown inFIG. 17. In this figure, a p-MOST is built by a gate GHbetween a p+-source region19and a p+-drain region22. The p+-region22is connected through a floating ohmic contact (FOC) to n+-region23. In the on-state of this p-MOST, the hole current can then transfer to an electron current by FOC, flowing in n-type layer6. At another place, there is an n-MOST made by an n-type source region11, a gate GHH. The electron current can flow when this n-MOST is in on-state. If the n-MOST keeps in on-state, then the current in the high-side device is controlled by the p-MOST, but the drift region is n-layer6, which produces a very low specific on-resistance. Such device is called a pseudo-p-MOST (p-pMOST) in this invention. According to the same mechanism, one can also make pseudo-n-MOST (p-nMOST), where the first symbol p refers to “pseudo”. The structure of the second surface voltage-sustaining region is not shown inFIG. 17, since it has been described hitherto many times.

The source n+-region8inFIG. 16is made in p-layer4. In case of layer4is very shallow and its dose is not large enough, the n+-region8may cause the p-layer4there disappear or produces parasitic BJT effect. For this reason, the active region can be made to be a p-MOST shown asFIG. 18. This is again an example of a pseudo-MOST (p-pMOST), where the source is p+-region22made on n-layer3and connected to the n-layer3via a FOC and n+-region23. The p-pMOST has a drift region, n-layer3, providing a low specific on-resistance.

The source electrode SHinFIG. 16contacts both p+-source region19and n-source-body20. Actually, a contact to source body is not necessary in some cases. This is because, there is a neutral region under region19due to the existence of the second surface-sustaining region, causing no biasing effect by the source-body.FIG. 19shows a high-side p-MOST, without a contact between source and source-body.

As mentioned before, many high-voltage devices can be built by using the high-voltage sustaining p-n-junction. Lateral MOST is only one kind.FIG. 20shows a high-side LIGBT. The right portion of this figure shows its symbol of circuit.

The surface voltage-sustaining region proposed in this invention can also be used to a make a fast turn-off LIGBT. In a conventional IGBT, a turn-off process has a long tail. For instance, in the turn-off transient, the electrons flow from n-layer6to the p+-region19induces an injection of holes to layer6. This is the reason that a long tail exists. However, by using a structure shown inFIG. 21, this effect can be eliminated. The feature of this structure is that it contains an auxiliary p-MOST, the drain of which is an FOC, connected to both p+-region22and n+-region23, the anode AH Of IGBT serves as the source electrode. And a gate, GHX, for this auxiliary p-MOST covers on an oxide or insulator layer21, which in turn covers on the area between p+-region19and p+-region22. In the on-state stage, a voltage larger than the threshold voltage of the n-MOST is applied to the normal gate, GH. But a voltage smaller than the threshold voltage of the p-MOST is applied to the auxiliary gate GHX, making the auxiliary p-MOST do not play any role. Therefore, the on-state is the same as a conventional LIGBT. In the turn-off stage, the voltages applied to the two gates are reversed, making n-MOST to be off and p-MOST to be on. Thus, the holes in the voltage-sustaining region flow to KHvia p+-region12, and the electrons flow to n+-region23then becomes a hole current by FOC. No holes are injected by the anode region19, so far as the voltage drop across region19and region22is lower than a certain value, 0.6V for silicon device. The gate GHXis called as an extract gate.

This invention also provides a device using both electrons and holes as majority carriers for conduction. The upper portion ofFIG. 22shows such devices of high-side and of low-side. Where GHnand GHpare the gate electrodes of high-side n-MOST and p-MOST respectively. Electrons can flow from SH, via n+-region11, the inversion layer under the gate GHnwhen it has a voltage higher than the threshold voltage of the n-MOST, n-layer6, n+-region20and eventually reaches the electrode DH. Similarly, holes can flow following the way: DH, p+-region19, inversion layer under GHp, p-layer7, SH. The bottom portion of this figure shows the symbols of the circuits, where the right part is for the high-side device. The left part is for the low-side device. The function of the low-side device is similar to the high-side device. The symbols S and D are for the n-MOST. Actually, from the point of view of the p-MOST, these two symbols should be exchanged.

A low-side and/or High-side Bipolar junction transistor (BJT) can also be made by using the surface voltage-sustaining regions of this invention.FIG. 23shows one example, where B, C and E stand for the electrodes of base, collector and emitter respectively. E is connected to n+-region24(or25) which in turn formed in p-layer4(or7) for low-side BJT (or high-side BJT). When the emitter to base has a positive bias, electrons can be injected from n+-region24(or25) to the base region p-layer4(or7), and reach n-layer3(or6), eventually collected by the collector CL(or CH).

The second surface voltage-sustaining region shown inFIG. 17,FIG. 20andFIG. 21can be used to form low-side device. The device can be the same as that of the high-side. However, it can also be a different device. For instance the high-side device can be an LIGBT and the low-side device can be a MOST, etc.

The isolation between the first surface voltage-sustaining region and the second surface voltage-sustaining region has many methods to realize except stated above. For instance, an n−-region between p-layer5and p-layer2like shown inFIG. 5,FIG. 6,FIG. 7andFIG. 8.FIG. 24shows a high-side MOST and a low-side MOST, where there is a narrow p-region30between p-layer5and p-layer2, instead of an n-region. The drain DHof the high-side MOST connected to the p+-region9and the n+-region8on the p-layer4through an outer connection. The place to be connected is the “tub”. The source of the low-side MOST is made in p-layer4for preventing a direct connection of the source SHof the high-side and the source SLof the low-side through the bottom p-layer.

If p-layer5and n-layer6inFIG. 24are not very thin, then layer3of the low-side drift region may have high on-resistance due to it has been depleted in a large extent. This is because, the voltage of the tub is small when the low-side is on, but the voltage of p-layer5is large, making a large reverse voltage between p-layer2and n-layer3. To avoid the large potential difference between them, a method is shown inFIG. 25, where there is an oxide or insulator layer31on the top of p-region30covered by an electrode, which is connected to the tub.

Naturally, the surface voltage-sustaining region proposed in this invention can be made on a substrate through a thin insulator (SIS).FIG. 26shows an insulator (I) layer32, which is located between the substrate and the two surface voltage-sustaining regions ofFIG. 8. The two regions are isolated each other by a p-region30. It should be mentioned here, that the substrate must be connected to the cathode KLof the low-side diode by outer connection. Because according to Ref. [4], the optimum surface doping density is referred to sustain a voltage which has applied across the largest potential terminal on the surface and the substrate.

FIG. 27shows a LIGBT which isFIG. 21alike but has an insulator layer (32) between the diode and the substrate. It should be pointed out here, that an electron flow from n-layer6through p-layer5to the substrate occurs probably inFIG. 21in case of the p-layer5being too thin. InFIG. 27, this flow is not going to exist due to the insulator layer32.

According to this invention, insulator layers can also be set between each neighboring p-layer and n-layer.FIG. 28shows that there are insulator layers to separate the regions having different conductivity type (layer2, layer3, layer4, layer5, layer6and layer7). Besides, an insulator layer33is set between the two surface voltage-sustaining regions and serves as an isolation region of these two regions.

It should be pointed out that, sometimes only one low-side or one high-side is more convenient in technology.FIG. 29shows a low-side n-MOST formed by many interdigitated celles connected in parallel. The figure shows four of them.FIG. 30shows a high-side n-MOST formed by many interdigitated celles connected in parallel. The figure shows three of them. A second surface voltage-sustaining region is shown on the left. The advantage of such a high-side device is that the isolation for the two surface voltage-sustaining regions can be saved.

Low voltage devices taking the maximum voltage of the high-side device or the maximum voltage of the low-side device as reference is readily to realize by using this patent.FIG. 31shows a low voltage CMOS inverter formed on the place having maximum voltage, i.e., the middle portion of p-layer5of high-side device. The source region, n+-region35, of the n-MOST in the low voltage CMOS is connected by an electrode to the maximum voltage, −VR. The gate of the n-MOST is connected to the gate of the p-MOST by outer connection, which serves also the input terminal of the CMOS. The p-MOST of the low voltage CMOS is made in an n-region,40. The source of the p-MOST, p+-region37, is connected to the n-region40through a electrode, which is applied with a voltage source having a positive voltage to −VR. The right portion of this figure shows the symbols of these devices.

In practical application, it often encounters that a current should flow in the reverse direction to the normal current of the high-side and/or the low-side device. This current is normally diverted by a freewheeling element, shown as the two diodes D1and D2in the lower portion ofFIG. 32. In the reverse conduction situation of the high-side device, the drain (DH) voltage to the source (SH) voltage of the device shown inFIG. 11(orFIG. 14, orFIG. 15) makes n-layer6and p-layer5to be forward biased. Then, a parasitic bipolar with n−-substrate1as collector, n-layer6as emitter and p-layer5as base, is going to be on. The reverse current may flow to the substrate instead of the high-side source SH.

One method to avoid such parasitic BJT effects is to use a low voltage auxiliary MOST with the gate short circuited to the drain, and this MOST is in series connection with the high-voltage device. In the normal conduction mode of the high-voltage device, the low-voltage MOST has only a very small voltage drop due to that it is conducting and its channel length is very short. In the mode of a small reverse biasing voltage is applied to the series connected device. The low-voltage auxiliary MOST turns to be in off-state and can sustain a reverse voltage, which is normally only in an order of one volt due to the freewheeling diode connected in parallel to the series connected high-voltage device and low-voltage device.FIG. 32shows a structure by using auxiliary MOSTs to prevent the parasitic BJT effect of the high-side and the low-side n-MOSTs during a flywheel time. In the high-side part (right portion of the structure), the structure is almost the same as that shown inFIG. 27, except that now GHxis connected to FOC, the latter serves as the drain electrode of the low-voltage p-MOST. The electrode marked with “OUT” is for the output of the totem pole. In the low-side part (left portion of the structure), a low-voltage n-MOST is made on the area having largest voltage of the low-side n-MOST. The low-side high-voltage device is the same as shown inFIG. 14, where the n+-source region,8, and the p+-source body region,29, are the same as8and9inFIG. 14. The auxiliary n-MOST has an n+-drain region,27, an n+-source region26. The gate28is connected to the drain, which is in turn connected to the source electrode (SL) of the low-side high-voltage n-MOST. The low portion ofFIG. 32shows the symbols of circuits of the device.

Another method is shown inFIG. 33. A diode formed by p+-region43and n-region42is connected in series with the high-side n-MOST. In the reverse conduction situation, this diode is reverse biased, so that no current flows to the high-side device. The p-region41is connected to DHand to n-region42to avoid a direct connection of42with the n-substrate1.

In the low-side device ofFIG. 33, a flow of electrons from n−-substrate1into p-layer2and a flow of holes from the latter into the former may occur when the low-side device is positively biased. These two flows maybe slow down the response of the device due to they injected minorities. To avoid this effect, a diode D4can be made in series connection with the source electrode SLof the low-side device, as shown in the low portion ofFIG. 34. The diode D4is formed by a p-region44, an n-region45in the p-region44and a p+-region46in the n-region45.

Many examples of the application of this invention have been demonstrated. It is obvious for a person skilled in the art that the technique of the present invention can be used to a p−-substrate without any difficulty. Also, a lot of applications without any difficulty in the spirit of this invention can be made.