System and method for test precondition generation based on factory-formatted state of memory device

A system and associated method for generating a test precondition. The system includes a test device and a storage device including user data blocks and system blocks. The test device reads, from the system blocks, an initial system data snapshot stored and represents a factory format; erases the system blocks and the user data blocks; writes data to selected user data blocks; generates system tables associated with the erasing and writing of the selected user data blocks; replaces the initial system data snapshot with the system tables; writes the replaced system tables to the system blocks; and performs one or more tests on the storage device.

BACKGROUND

Embodiments of the present disclosure relate to a test system.

2. Description of the Related Art

The computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having a memory device(s), that is, a data storage device(s). The data storage device is used as a main memory device or an auxiliary memory device of the portable electronic devices.

Memory systems using memory devices provide excellent stability, durability, high information access speed, and low power consumption, since the memory devices have no moving parts. Examples of memory systems having such advantages include universal serial bus (USB) memory devices, memory cards having various interfaces such as a universal flash storage (UFS), and solid state drives (SSDs). Memory systems may be tested using various test tools.

SUMMARY

Aspects of the present invention include a system and a method for generating a test precondition based on a factory-formatted state of a data storage device.

In one aspect of the present invention, a test system includes a test device and a storage device including a plurality of system blocks and a plurality of user data blocks, the system blocks configured to store an initial system data snapshot. The test device is configured to: read the initial system data snapshot from the system blocks of the storage device, in which the initial system data snapshot is stored and represents a factory format of the storage device; erase the system blocks and the user data blocks; writing data to one or more user data blocks selected from among the user data blocks based on a set precondition such that the storage device is preconditioned; generate one or more system tables associated with the erasing and writing of the selected user data blocks; replace the initial system data snapshot with the system tables associated with the erasing and writing of the selected user data blocks; write the replaced system tables to the system blocks; and perform one or more tests on the preconditioned storage device to determine if errors exist at least in writing the data to the storage device.

In another aspect of the present invention, a method for testing a storage device including a plurality of system blocks and a plurality of user data blocks, the system blocks storing an initial system data snapshot, includes: reading the initial system data snapshot from the system blocks of the storage device, in which the initial system data snapshot is stored and represents a factory format of the storage device; erasing the system blocks and the user data blocks; writing data to one or more user data blocks selected from among the user data blocks based on a set precondition such that the storage device is preconditioned; generating one or more system tables associated with the erasing and writing of the selected user data blocks; replacing the initial system data snapshot with the system tables associated with the erasing and writing of the selected user data blocks; writing the replaced system tables to the system blocks; and performing one or more tests on the preconditioned storage device to determine if errors exist at least in writing the data to the storage device.

Additional aspects of the present invention will become apparent from the following description.

DETAILED DESCRIPTION

Various embodiments of the present invention are described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and thus should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure conveys the scope of the present invention to those skilled in the art. Moreover, reference herein to “an embodiment,” “another embodiment,” or the like is not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s). The term “embodiments” as used herein does not necessarily refer to all embodiments. Throughout the disclosure, like reference numerals refer to like parts in the figures and embodiments of the present invention.

The present invention can be implemented in numerous ways, including as a process; an apparatus; a system; a computer program product embodied on a computer-readable storage medium; and/or a processor, such as a processor suitable for executing instructions stored on and/or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the present invention may take, may be referred to as techniques. In general, the order of the operations of disclosed processes may be altered within the scope of the present invention. Unless stated otherwise, a component such as a processor or a memory described as being suitable for performing a task may be implemented as a general device or circuit component that is configured or otherwise programmed to perform the task at a given time or as a specific device or circuit component that is manufactured to perform the task. As used herein, the term ‘processor’ or the like refers to one or more devices, circuits, and/or processing cores suitable for processing data, such as computer program instructions.

If implemented at least partially in software, the controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators and other signal generating and signal processing features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device.

A detailed description of embodiments of the present invention is provided below along with accompanying figures that illustrate aspects of the present invention. The present invention is described in connection with such embodiments, but the present invention is not limited to any specific embodiment. The present invention encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the present invention. These details are provided for the purpose of example; the present invention may be practiced according to the claims without some or all of these specific details. For clarity, technical material that is known in technical fields related to the present invention has not been described in detail so that the present invention is not unnecessarily obscured.

FIG.1is a block diagram illustrating a data processing system2in accordance with one embodiment of the present invention.

ReferringFIG.1, the data processing system2may include a host device5and a memory system10. The memory system10may receive a request from the host device5and operate in response to the received request. For example, the memory system10may store data to be accessed by the host device5.

The host device5may be implemented with any of various types of electronic devices. In various embodiments, the host device5may be an electronic device such as for example a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and/or a digital video recorder and a digital video player. In various embodiments, the host device5may be a portable electronic device such as for example a mobile phone, a smart phone, an e-book, an MP3 player, a portable multimedia player (PMP), and/or a portable game player.

The memory system10may be implemented with any of various types of storage devices such as a solid state drive (SSD) and a memory card. In various embodiments, the memory system10may be provided as one of various components in an electronic device such as for example a computer, an ultra-mobile personal computer (PC) (UMPC), a workstation, a net-book computer, a personal digital assistant (PDA), a portable computer, a web tablet PC, a wireless phone, a mobile phone, a smart phone, an e-book reader, a portable multimedia player (PMP), a portable game device, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device of a data center, a device capable of receiving and transmitting information in a wireless environment, a radio-frequency identification (RFID) device, as well as one of various electronic devices of a home network, one of various electronic devices of a computer network, one of electronic devices of a telematics network, or one of various components of a computing system.

The memory system10may include a memory controller100and a semiconductor memory device200. The memory controller100may control overall operations of the semiconductor memory device200.

The semiconductor memory device200may perform one or more erase, program, and read operations under the control of the memory controller100. The semiconductor memory device200may receive through input/output lines a command CMD, an address ADDR, and data DATA. The semiconductor memory device200may receive power PWR through a power line and a control signal CTRL through a control line. The control signal CTRL may include for example a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, as well as other operational signals depending on design and configuration of the memory system10.

The memory controller100and the semiconductor memory device200may be integrated in a single semiconductor device such as a solid state drive (SSD). The SSD may include a storage device for storing data therein. In one embodiment of the invention, where the semiconductor memory system10is used in an SSD, operation speed of a host device (e.g., host device5ofFIG.1) coupled to the memory system10may remarkably improve.

The memory controller100and the semiconductor memory device200may be integrated in a single semiconductor device such as a memory card. For example, the memory controller100and the semiconductor memory device200may be integrated to configure a personal computer (PC) card of personal computer memory card international association (PCMCIA), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a reduced-size multimedia card (RS-MMC), a micro-size version of MMC (MMCmicro), a secure digital (SD) card, a mini secure digital (miniSD) card, a micro secure digital (microSD) card, a secure digital high capacity (SDHC), and/or a universal flash storage (UFS).

FIG.2is a block diagram illustrating a memory system in accordance with another embodiment of the present invention. For example, the memory system ofFIG.2may depict the memory system10shown inFIG.1.

Referring toFIG.2, the memory system10may include a memory controller100and a semiconductor memory device200. The memory system10may operate in response to a request from a host device (e.g., a request from host device5ofFIG.1), and in particular, store data to be accessed by the host device.

The memory device200may store data to be accessed by the host device.

The controller100may control storage of data in the memory device200. For example, the controller100may control the memory device200in response to a request from the host device. The controller100may provide data read from the memory device200to the host device, and may store data provided from the host device into the memory device200.

The controller100may include a storage110, a control component120which may be implemented as a processor such as for example a central processing unit (CPU), an error correction code (ECC) component130, a host interface (I/F)140and a memory interface (I/F)150, which are coupled through a bus160.

The storage110may serve as a working memory of the memory system10and the controller100, and storage110may store data for driving the memory system10and the controller100. When the controller100controls operations of the memory device200, the storage110may store data used by the controller100and the memory device200for such operations as read, write, program and erase operations.

The storage110may be implemented with a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the storage110may store data used by the host device in the memory device200for the read and write operations. To store the data, the storage110may include a program memory, a data memory, a write buffer, a read buffer, a map buffer, and the like.

The control component120may control general operations of the memory system10, and a write operation or a read operation for the memory device200in response to a write request or a read request from the host device. The control component120may drive firmware or other program instructions, which can be referred to as a flash translation layer (FTL), to control operations of the memory system10. For example, the FTL may perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and/or bad block handling. The L2P mapping is known as logical block addressing (LBA).

The ECC component130may detect and correct errors in the data read from the memory device200during a read operation. In one embodiment, the ECC component130may not correct error bits when the number of the error bits is greater than or equal to a threshold number of correctable error bits, but instead may output an error correction fail signal indicating failure in correcting the error bits.

In various embodiments, the ECC component130may perform an error correction operation based on a coded modulation such as for example a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a turbo product code (TPC), a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), or a Block coded modulation (BCM). However, error correction is not limited to these techniques. As such, the ECC component130may include any and all circuits, systems or devices suitable for error correction operation.

The host interface140may communicate with the host device through one or more of various communication standards or interfaces such as for example a universal serial bus (USB), a multi-media card (MMC), a peripheral component interconnect express (PCI-e or PCIe), a small computer system interface (SCSI), a serial-attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

The memory interface150may provide an interface between the controller100and the memory device200to allow the controller100to control the memory device200in response to a request from the host device. The memory interface150may generate control signals for the memory device200and process data under the control of the control component120. In one embodiment where the memory device200is a flash memory such as a NAND flash memory, the memory interface150may generate control signals for the memory and process data under the control of the control component120.

The memory device200as shown for example inFIG.2may include a memory cell array210, a control circuit220, a voltage generation circuit230, a row decoder240, a page buffer250which may be in the form of an array of page buffers, a column decoder260, and an input and output (input/output) circuit270. The memory cell array210may include a plurality of memory blocks211which may store data. The voltage generation circuit230, the row decoder240, the page buffer array250, the column decoder260and the input/output circuit270may form a peripheral circuit for the memory cell array210. The peripheral circuit may perform program, read, or erase operations of the memory cell array210. The control circuit220may control the peripheral circuit.

The voltage generation circuit230may generate operational voltages of various levels. For example, in an erase operation, the voltage generation circuit230may generate operational voltages of various levels such as an erase voltage and a pass voltage.

The row decoder240may be in electrical communication with the voltage generation circuit230, and the plurality of memory blocks211. The row decoder240may select at least one memory block among the plurality of memory blocks211in response to a row address generated by the control circuit220, and transmit operation voltages supplied from the voltage generation circuit230to the selected memory blocks.

The page buffer250may be coupled with the memory cell array210through bit lines BL (shown inFIG.3). The page buffer250may precharge the bit lines BL with a positive voltage, transmit data to and receive data from, a selected memory block in program and read operations, or temporarily store transmitted data in response to page buffer control signal(s) generated by the control circuit220.

The column decoder260may transmit data to and receive data from the page buffer250or may transmit and receive data to and from the input/output circuit270.

The input/output circuit270may transmit to the control circuit220a command and an address, received from an external device (e.g., the memory controller100ofFIG.1), transmit data from the external device to the column decoder260, or output data from the column decoder260to the external device through the input/output circuit270.

The control circuit220may control the peripheral circuit in response to the command and the address.

FIG.3is a circuit diagram illustrating a memory block of a semiconductor memory device in accordance with still another embodiment of the present invention. For example, the memory block ofFIG.3may be any of the memory blocks211of the memory cell array210shown inFIG.2.

Referring toFIG.3, the memory block211may include a plurality of word lines WL0to WLn−1, a drain select line DSL, and a source select line SSL coupled to the row decoder240. These lines may be arranged in parallel, with the plurality of word lines between the DSL and SSL.

The memory block211may further include a plurality of cell strings221respectively coupled to bit lines BL0to BLm−1. The cell string of each column may include one or more drain selection transistors DST and one or more source selection transistors SST. In the illustrated embodiment, each cell string has one DST and one SST. In a cell string, a plurality of memory cells or memory cell transistors MC0to MCn−1 may be serially coupled between the selection transistors DST and SST. Each of the memory cells may be formed as a multiple level cell. For example, each of the memory cells may be formed as a single level cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-level cell (MLC) storing 2 bits of data. Each of the memory cells may be formed as a triple-level cell (TLC) storing 3 bits of data. Each of the memory cells may be formed as a quadruple-level cell (QLC) storing 4 bits of data.

The source of the SST in each cell string may be coupled to a common source line CSL, and the drain of each DST may be coupled to the corresponding bit line. Gates of the SSTs in the cell strings may be coupled to the SSL, and gates of the DSTs in the cell strings may be coupled to the DSL. Gates of the memory cells across the cell strings may be coupled to respective word lines. That is, the gates of memory cells MC0are coupled to corresponding word line WL0, the gates of memory cells MC1are coupled to corresponding word line WL1, etc. The group of memory cells coupled to a particular word line may be referred to as a physical page. Therefore, the number of physical pages in the memory block211may correspond to the number of word lines.

The page buffer array250may include a plurality of page buffers251that are coupled to the bit lines BL0to BLm−1. The page buffers251may operate in response to page buffer control signals. For example, the page buffers251may temporarily store data received through the bit lines BL0to BLm−1 or sense voltages or currents of the bit lines during a read or verify operation.

In various embodiments of the present invention, the memory blocks211may include a NAND-type flash memory cell. However, the memory blocks211are not limited to such cell type, but may include NOR-type flash memory cell(s). Memory cell array210may be implemented as a hybrid flash memory in which two or more types of memory cells are combined, or one-NAND flash memory in which a controller is embedded inside a memory chip.

FIG.4is a diagram illustrating distributions of states or program voltage (PV) levels for different types of cells of a memory device in accordance with one embodiment of the present invention.

Referring toFIG.4, each of the memory cells may be implemented with a specific type of cell, for example, a single level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a triple-level cell (TLC) storing 3 bits of data, or a quadruple-level cell (QLC) storing 4 bits of data. Usually, all memory cells in a particular memory device are of the same type, but that is not a requirement.

An SLC may include two states P0and P1. P0may indicate an erase state, and P1may indicate a program state. Since the SLC can be set in one of two different states, each SLC may program or store 1 bit according to a set coding method. An MLC may include four states P0, P1, P2and P3. Among these states, P0may indicate an erase state, and P1to P3may indicate program states. Since the MLC can be set in one of four different states, each MLC may program or store two bits according to a set coding method. A TLC may include eight states P0to P7. Among these states, P0may indicate an erase state, and P1to P7may indicate program states. Since the TLC can be set in one of eight different states, each TLC may program or store three bits according to a set coding method. A QLC may include 16 states P0to P15. Among these states, P0may indicate an erase state, and P1to P15may indicate program states. Since the QLC can be set in one of sixteen different states, each QLC may program or store four bits according to a set coding method.

Referring back toFIGS.2and3, the memory device200may include a plurality of memory cells (e.g., NAND flash memory cells). The memory cells are arranged in an array of rows and columns as shown inFIG.3. The cells in each row are connected to a word line (e.g., WL0), while the cells in each column are coupled to a bit line (e.g., BL0). These word and bit lines are used for read and write operations. During a write operation, the data to be written (‘1’ or ‘0’) is provided at the bit line while the word line is asserted. During a read operation, the word line is again asserted, and the threshold voltage of each cell can then be acquired from the bit line. Multiple pages may share the memory cells that belong to (i.e., are coupled to) the same word line. When the memory cells are implemented with MLCs, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cells are implemented with TLCs, the multiple pages include an MSB page, a center significant bit (CSB) page and an LSB page. When the memory cells are implemented with QLCs, the multiple pages include an MSB page, a center most significant bit (CMSB) page, a center least significant bit (CLSB) page and an LSB page. The memory cells may be programmed for example using a coding scheme (e.g., Gray coding) in order to increase the capacity of the memory system10such as SSD.

FIG.5is a diagram illustrating a test system2in accordance with another embodiment of the present invention.

Referring toFIG.5, the test system500may include a test device510and a storage device520. In various embodiments of the present invention, the test device510may be a real host device (e.g., the host device5ofFIG.1) or a virtual host device (i.e., a host simulator), which is communicatively coupled to the storage device520.

The storage device520may include a controller100and a memory device200. The memory device200may include a plurality of memory cells (e.g., NAND flash memory cells). The memory cells in memory device200are arranged in an array of rows and columns as shown inFIG.3. The cells in a particular row are connected to a word line (e.g., WL0), while the cells in a particular column are coupled to a bit line (e.g., BL0). These word and bit lines are used for read and write operations. During a write operation, the data to be written (‘1’ or ‘0’) is provided at the bit line while the word line is asserted. During a read operation, the word line is again asserted, and the threshold voltage of each cell can then be acquired from the bit line. Multiple pages may share the memory cells that belong to (i.e., are coupled to) the same word line.

The controller100may include firmware (FW) or other program instructions which define a specific class of software for controlling various operations (e.g., read, write, and erase operations) for the memory device200. In various embodiments of the present invention, the firmware may reside in the storage110and may be executed by the control component120, inFIG.2. The firmware may include a host interface layer (HIL) controlling communication with the test device510, a flash translation layer (FTL) controlling communication between the test device510and the memory device200, and a flash interface layer (FIL) controlling communication with the memory device200.

The storage device520may be tested through various test approaches (e.g., black box, white box and unit tests). The storage device520for the test may be a hardware (HW) platform (i.e., a real storage device) or a simulator (i.e., a personal computer (PC)). Testing the storage device520may include sending, by the test device510, some commands to the storage device520and checking the expected results.

In various embodiments of the present invention, the storage device520may be a solid state drive (SSD) implemented with a NAND flash device. A capacity of a NAND flash device is becoming so large that it takes too much time to create a precondition in a simulation environment using a scheme of merely running arbitrary IO workloads (i.e., commands). For example, it may take hours or days to write the entire capacity of the NAND flash device.

Alternatively, a precondition generation scheme may be used for the storage device520. Generating and making a precondition for a test means turning the storage device520into specific predefined states. This precondition generation scheme may make the precondition creation time irrelevant to the precondition complexity. However, the firmware can be so complicated that it would be too difficult to support all data structures of firmware. Accordingly, embodiments of the present invention provide a scheme for effectively creating a precondition to be used for testing a storage device. In particular, embodiments of the present invention provide a test system for generating a test precondition for a storage device based on a factory-formatted state of a storage device.

Referring back toFIG.5, the test device510may generate a test precondition for the storage device520and provide the generated test precondition to the storage device520such that the storage device520(e.g., the memory device200) would be preconditioned based on the test precondition. Further, the test device510may run (perform) one or more tests on the preconditioned storage device520. In particular, the test device510may generate a precondition based on a state after a factory format of the storage device520including data structures have been already dumped into the storage device520. In one embodiment of the present invention, a precondition may be generated to be used in a simulation system (i.e., a NAND flash device simulator) and the entire preconditioning process may be performed on a virtual platform as described below.

FIG.6is a diagram illustrating a memory device200of a storage device520in accordance with still another embodiment of the present invention.

Referring toFIG.6, the memory device200may include a plurality of system blocks610and a plurality of user data blocks620. The plurality of user data blocks620may include blocks for storing user data (e.g., write data). The plurality of system blocks610may include one or more firmware blocks612, one or more system data blocks614for storing system data, and one or more system-tables blocks616for storing system tables.

FIG.7is a diagram illustrating preconditioning and testing processes for a storage device520in accordance with yet another embodiment of the present invention.

Referring toFIG.7, the preconditioning and testing processes may be performed on the storage device520(e.g., a NAND flash device). These processes may be performed by the test device510. In one embodiment of the present invention, the test device510may be a real host device or a virtual host device.

First, the NAND flash device520may have an empty state (710). Second, a factory format procedure may be executed over the NAND flash device520with the empty state (715). This factory format procedure may happen in factory conditions before the NAND flash device520comes to the user. A particular FW code may be used for a factory format. The same FW code for the factory format may be used on the simulator platform as it is used for the same purposes on the hardware platform.

As a result of the factory format procedure, an initial snapshot (i.e., version) of system data structures (hereafter referred to as initial system data snapshot) may appear in the NAND flash device520(720) and thus the state of the NAND flash device520may be altered. For example, the state of the NAND flash device520after the factory format procedure is illustrated in snapshot810ofFIG.8. In the illustrated example, user data blocks may be still empty.

The test device510may obtain the initial system data snapshot. In various embodiments of the present invention, the initial system data snapshot may be obtained in the simulation environment using the original FW code for the factory format procedure. Alternatively, the initial system data snapshot may be obtained from the hardware platform. In this embodiment with the initial system data snapshot obtained from the hardware platform, the test device510may include special means to get NAND contents (i.e., the initial system data snapshot) from a real NAND flash device520. For example, vendor-unique commands (VUC) may be used to extract NAND contents from the NAND flash device520(e.g., SSD) to the test device510.

The test device510may generate a test precondition based on the initial system data snapshot (725) and provide the generated test precondition to the NAND flash device520. The storage device520may be preconditioned based on the test precondition (730). For example, the state of the preconditioned NAND flash device520is illustrated in snapshot820ofFIG.8. The test device510may run one or more tests (e.g., black box, white box and unit tests) on the preconditioned storage device520(735).

FIG.8is a diagram illustrating an example of generating a test precondition for a storage device520in accordance with one embodiment of the present invention.

InFIG.8,810represents a state (or snapshot) of the storage device (e.g., a NAND flash device)520after a factory format procedure. In the illustrated example, firmware block612, system data blocks614, and system-tables blocks616of the storage device520may be written to have particular default settings through the factory format procedure (715). The system data blocks614may include N system data blocks. The system-tables blocks616may include K system-tables blocks. Each system-tables block may include (M+1) mapping table chunks, an erase counts table, a read counts table and other system tables. The mapping table chunks may be an address mapping table storing a mapping relationship between a logical block address (LBA) and a physical block address (PBA). LBA may be an address associated with a particular operation (e.g., a write operation) on the memory device200, which is received from the host device5ofFIG.1or the test device510ofFIG.5. PBA may be an address indicating a particular memory region (e.g., a page) of the user data blocks620in the memory device200.

820inFIG.8represents a state (or snapshot) of the storage device520after a precondition generation (725). In the illustrated example, some of the system-tables blocks616and some of the user data blocks620of the storage device520may be preconditioned to have a particular state as shown in820. In the first system-tables block, (M+1) mapping table chunks, and an erase counts table may be preconditioned. As shown inFIG.8, state820shows that 15 user data blocks of the user data blocks620are preconditioned.

FIG.9is a diagram illustrating an operation of generating a test precondition for a storage device520in accordance with another embodiment of the present invention. The operation ofFIG.9may be performed by the test device510ofFIG.5.

Referring toFIG.9, the test device510may generate a test precondition for one or more of the system-tables blocks of the system block as shown inFIG.8. When user data is in user data blocks, system tables may be written to the storage device520. As the initial snapshot of system tables is already in the storage device520as shown in810ofFIG.8, the test device510may update system tables according to a read-modify-write procedure. The read-modify-write procedure may be applied to system data only because user data is written to empty (erased) user data blocks. The read-modify-write procedure is described as following.

At910inFIG.9, the test device510may read the entire system blocks from a system block610to get an initial system data snapshot. In one embodiment of the present invention, the test device510may obtain the initial system data snapshot from either a PC (if the simulation environment is used) or a hardware platform (if a real NAND flash device is used). The read system blocks (i.e., initial system data snapshot) may be stored to a memory (e.g., a random access memory (RAM)).

Then, the test device510may allocate system tables in the memory. In various embodiments of the present invention, the test device510may allocate an address mapping table, an erase counts table and a read counts table. Further, the test device510may erase system blocks and user data blocks.

At920inFIG.9, the test device510may write data to one or more user data blocks620selected from among the user data blocks based on a set precondition type such that the storage device520is preconditioned. Based on the desired precondition type (or data writing precondition), logical block addresses (LBAs) may be spread among user data blocks. In various embodiments of the present invention, the set precondition type may include a sequential precondition for a sequentially written storage device, a random precondition for a randomly written storage device, and a sustained precondition for a storage device in a sustained state. The sustained state means that the entire capacity of the storage device520has been written so many times that write amplification index (WAI) became stable without big varying. After LBAs have been spread among user data blocks, system tables such as an address mapping table and other system tables may be filled.

In one embodiment, for the sequential precondition, the test device510may write the user data blocks620with sequentially increasing LBAs. That is, the test device520may sequentially write data to the user data blocks620, which are sequentially selected based on the sequential precondition. In another embodiment, for the random/sustained precondition, the test device510may write the user data blocks620with random LBAs and write some invalid data. That is, the test device520may randomly write data to the user data blocks620, which are randomly selected based on the random/sustained precondition. For the random/sustained precondition, all valid data in the user data blocks may be at its beginning part of the user data blocks, and all invalid data may be at the end part of the user data blocks such that garbage collection (GC) is not influenced. In some embodiments, for the random/sustained precondition, each user block may be written not to have 100% full of valid pages. For example, each user block may be written to have 90% valid data and 10% invalid (dummy) data. Alternatively, valid and invalid data may be evenly mixed within the user data blocks.

At930inFIG.9, the test device510may generate one or more system tables associated with the erasing and writing of the user data blocks. In one embodiment, the test device510may generate an address mapping table. As shown inFIG.10, after a user data block N is written to a particular page (e.g., a physical address (N, M)) associated with a particular logical block address (e.g., LBA X), mapping information between the logical address and the physical address may be stored (updated) in the address mapping table. In another embodiment, the test device510may generate a chipkill parity associated with encoding of each mapping table chunk. For example, the chipkill parity may be generated by performing an exclusive OR (XOR) calculation on bits of each mapping table chunk. For another example, when write data has a regular structure for the sequential precondition, the address mapping table may be generated without XOR calculation. In another embodiment, the test device510may generate an erase counts table associated with the erasing of the user data blocks.

At940inFIG.9, the test device510may replace the obtained system tables (i.e., initial system data snapshot) with the generated system tables in the memory. That is, the initial system data snapshot may be modified. In one embodiment, the initial erase counts snapshot may be replaced by the generated erased counts table data. For the sequential/random precondition, erase counters for all written user data blocks may be set to a particular value (e.g., “1”). For the sustained precondition, erase counters for all written user data blocks may be set to a predefined value depending on overprovisioning (OP) or any other (arbitrary) values. In another embodiment, the initial mapping table snapshot may be replaced by the generated mapping table data. As noted above, chipkill parity for the mapping table data may be generated.

At950inFIG.9, the test device510may write the modified system tables (i.e., initial system data snapshot) to the system block610.

The read-modify-write procedure above may be performed for one FTL. If there are multiple FTL instances, operations920to950may be repeatedly performed for each FTL. After the read-modify-write procedure above is performed, the test device510may run one or more tests using the generated precondition.

Experiments were conducted to measure performance of the described precondition generation scheme in accordance with embodiments of the present invention and a straightforward scheme (without using the precondition generation scheme). 1 TB 3D TLC 8CH SSD simulator was used for experiments. The results show that the precondition generation scheme of the present invention can improve precondition generation time in comparison to the straightforward scheme, which is indicated in LIST1 below.

As described above, embodiments of the present invention provide a scheme for generating test precondition based on factory-formatted state of a data storage device. This scheme may reduce generation time of a test precondition to be used for testing the data storage device.

Although the foregoing embodiments have been illustrated and described in some detail for purposes of clarity and understanding, the present invention is not limited to the details provided. There are many alternative ways of implementing the invention, as one skilled in the art will appreciate in light of the foregoing disclosure. The disclosed embodiments are thus illustrative, not restrictive. The present invention embraces all modifications and alternatives. Furthermore, the embodiments may be combined to form additional embodiments.