Interconnect with self-forming wrap-all-around barrier layer

The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

FIELD OF THE INVENTION

The present invention relates to interconnect technology, and more particularly, to interconnects with self-forming wrap-all-around graphene barrier layer.

BACKGROUND OF THE INVENTION

Traditionally, copper (Cu) has been used as the main interconnect conducting metal. However, as device dimensions shrink, the resistance of Cu-based interconnects becomes very high.

Further, Cu interconnects require the use of a barrier layer to prevent diffusion of the Cu into the surrounding dielectric. Use of conventional barrier materials like titanium nitride (TiN), tantalum nitride (TaN), however, unduly limits the amount of Cu in the interconnect, thereby further increasing the resistance.

Cobalt (Co) or other alternative metals can be used to replace Cu as the main interconnect conducting metal due to thinner or no liner requirements and shorter mean free path. However, metals like Co can still diffuse into the surrounding dielectric. Thus, a barrier is needed for reliability time-dependent dielectric breakdown (TDDB) and this barrier needs to be very thin to achieve low line resistance. For performance, surface scattering needs improvement to reduce line resistance.

Therefore, improved interconnect designs and techniques for the fabrication thereof would be desirable.

SUMMARY OF THE INVENTION

The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect of the invention, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect.

For instance, a graphene layer can be deposited on top of the interconnect. The interconnect and the graphene layer can be annealed under conditions sufficient to diffuse carbon atoms from the graphene layer to form a buried graphene layer at an interface between the dielectric and the interconnect, wherein the graphene layer and the buried graphene layer form the wrap-all-around graphene barrier layer surrounding the interconnect. Alternatively, a graphene layer on top of the interconnect and a buried graphene layer at an interface between the dielectric and the interconnect can be formed concurrently, wherein the graphene layer and the buried graphene layer form the wrap-all-around graphene barrier layer surrounding the interconnect.

Also, a metal liner can be deposited into and lining the at least one trench; a conformal carbon layer can be deposited onto the metal liner; a fill metal can be deposited into the at least one trench over the metal liner, wherein the metal liner and the fill metal form the interconnect in the at least one trench; a second dielectric can be deposited over the interconnect; and the interconnect and the conformal carbon layer can be annealed under conditions sufficient to diffuse carbon atoms from the conformal carbon layer to form graphene layers at an interface between the dielectric and the interconnect, and at an interface between the second dielectric and the interconnect, wherein the graphene layers form the wrap-all-around graphene barrier layer surrounding the interconnect.

Further, a metal liner can be deposited into and lining the at least one trench; graphene can be formed concurrently above and below the metal liner; a fill metal can be deposited into the at least one trench over the metal liner, wherein the metal liner and the fill metal form the interconnect in the at least one trench; a second dielectric can be deposited over the interconnect; and the interconnect and the graphene can be annealed under conditions sufficient to diffuse carbon atoms from the graphene to form a graphene layer at an interface between the second dielectric and the interconnect, wherein the graphene below the metal liner and the graphene layer form the wrap-all-around graphene barrier layer surrounding the interconnect.

Yet further, a metal liner can be deposited into and lining the at least one trench; graphene can be formed concurrently above and below the metal liner; the graphene above metal liner can be removed; a fill metal can be deposited into the at least one trench over the metal liner, wherein the metal liner and the fill metal form the interconnect in the at least one trench; and a graphene layer can be deposited on top of the interconnect, wherein the graphene below the metal liner and the graphene layer form the wrap-all-around graphene barrier layer surrounding the interconnect.

In another aspect of the invention, an interconnect structure is provided. The interconnect structure includes: at least one interconnect embedded in a dielectric; and a wrap-all-around graphene barrier surrounding the interconnect.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Provided herein are (e.g., cobalt (Co), ruthenium (Ru), etc.) interconnect structures with self-forming, wrap-all-around graphene barrier layer that surrounds the interconnect and techniques for the fabrication thereof. The interconnects are completely wrapped with a thin graphene layer. This graphene layer serves as a metal barrier and improves the interface scattering and resistance.

Several different process flows are provided herein to form the present interconnects with a wrap-all-around graphene barrier layer. For instance, in a first exemplary embodiment described by way of reference toFIGS. 1-4, carbon deposited on top of the interconnect is diffused to all buried metal-dielectric interfaces to form a thin graphene barrier layer that completely wraps around the interconnect.

Namely, as shown inFIG. 1, the process begins with a dielectric102. Suitable dielectric materials include, but are not limited to, oxide materials such as silicon oxide (SiOx) and/or organosilicate glass (SiCOH) and/or ultralow-κ interlayer dielectric (ULK-ILD) materials, e.g., having a dielectric constant K of less than 2.7. By comparison, silicon dioxide (SiO2) has a dielectric constant K value of 3.9. Suitable ultralow-κ dielectric materials include, but are not limited to, porous organosilicate glass (pSiCOH).

A damascene process is then employed to form a metal interconnect in the dielectric102. Generally, a damascene process involves pattering a feature(s) (e.g., a trench, via, etc.) in the dielectric102, filling the feature(s) with a conductive material (e.g., a metal such as Co, Ru, etc.) and then polishing the deposited metal to remove the overburden using, e.g., a process such as chemical-mechanical polishing (CMP). Namely, as shown inFIG. 1, at least one trench104is patterned in the dielectric102. Standard lithography and etching techniques can be used to pattern the trench104in the dielectric102. A directional (anisotropic) etching process such as reactive ion etching (RIE) can be used for the trench etch.

As shown inFIG. 1, the trench104extends partway through the dielectric102. That way, when the metal interconnect is formed in the trench104dielectric102will be present along the bottom and sidewalls of the interconnect.

A metal is then deposited into and filling the trench104, followed by a polishing process such as CMP to remove the overburden. The result is the formation of a metal interconnect202in trench104. SeeFIG. 2. Suitable metals for interconnect202include, but are not limited to, Co and/or Ru. The metal can be deposited into the trench104using a process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plating, evaporation, sputtering, etc.

A graphene layer302is then deposited on the top surfaces of the dielectric102/interconnect202. SeeFIG. 3. See, for example, U.S. Patent Application Publication Number 2011/0303899 by Padhi et al., entitled “Graphene Deposition” (hereinafter “U.S. Patent Application Publication Number 2011/0303899”). As described in U.S. Patent Application Publication Number 2011/0303899, graphene can be grown on a metallic layer (e.g., Co) using a CVD-based process and a carbon precursor such as acetylene.

The interconnect202/graphene layer302are then annealed under conditions sufficient to diffuse carbon atoms from the graphene layer302, through the interconnect202, to form a buried graphene layer402at the interface between dielectric102and interconnect202. SeeFIG. 4. According to an exemplary embodiment, graphene layers302and402each includes from about 1 monolayer (i.e., a single monolayer) to about 5 monolayers of graphene. A graphene ‘monolayer’ is a one atom thick layer of graphene.

Advantageously, the graphene layer402acts as a metal barrier layer between the interconnect202and the dielectric102, and improves interface scattering and resistance. As described, for example, in Kwak et al., “Near room-temperature synthesis of transfer-free graphene films,” nature communications, 3:645 (January 2012) (7 pages) (hereinafter “Kwak”), the contents of which are incorporated by reference as if fully set forth herein, the carbon from a solid carbon source (in this case carbon layer302) can be effectively diffused through a metal (in this case interconnect202) and crystallize as graphene at the metal-substrate interface, and also form a layer of graphene on top of the metal. Notably, as described in Kwak this process can be carried out at temperatures of less than or equal to about 260° C. As such, these low temperatures will prevent damaging structures such as the dielectric102(which can occur at temperatures exceeding 600° C.).

Namely, according to an exemplary embodiment, the annealing conditions include, but are not limited to, a temperature of less than about 600° C., e.g., from about 25° C. to about 260° C. and ranges therebetween, and a duration of from about 1 minute to about 30 minutes and ranges therebetween. Further, as will be described in detail below, the present techniques can also be employed to form a graphene barrier both above and below the metal at the same time, thereby combining the carbon deposition and diffusion into a single step.

As shown inFIG. 4, the result is a (e.g., Co and/or Ru) interconnect202embedded in the dielectric102having a wrap-all-around graphene barrier layer (i.e., graphene layers302and402). As provided above, this wrap-all-around graphene layer acts as a barrier to prevent diffusion of metal ions from the interconnect202into the dielectric102, and also improves interface scattering and resistance.

As highlighted above, an alternate process can instead be employed to form the wrap-all-around graphene barrier layer (i.e., graphene layers302and402) both above and below the interconnect202concurrently. For instance, as described, for example, in Lo et al., “BEOL Compatible 2D Layered Materials as Ultra-Thin Diffusion Barriers for Cu Interconnect Technology,” 2017 75thAnnual Device Research Conference (DRC) (June 2017) (2 pages) (hereinafter “Lo”), the contents of which are incorporated by reference as if fully set forth herein, direct graphene growth by plasma-enhanced chemical vapor deposition (PECVD) on a metal layer can be used to form graphene layers both on top of the metal layer and below the metal layer at the metal-dielectric interface. Advantageously, as described in Lo, this process can be carried out at a temperature of 400° C.

Thus, according to an alternative embodiment, graphene is grown directly on the interconnect202, using a process such as PECVD, to concurrently form i) graphene layer402at the dielectric102/interconnect202interface and ii) graphene layer302on top of the interconnect202. The result is the same as that depicted inFIG. 4, namely a (e.g., Co and/or Ru) interconnect202embedded in the dielectric102having a wrap-all-around graphene barrier layer (i.e., graphene layers302and402). In this case, the intermediate step shown inFIG. 3is skipped since the graphene growth occurs both above and below the interconnect202at the same step.

In another exemplary embodiment, only a thin (e.g., Co and/or Ru) metal liner is initially deposited prior to growing the carbon layer. That way, the carbon layer is placed in closer proximity to the metal liner-dielectric interface. See, for example,FIGS. 5-10. This alternative process flow begins in the same manner as described in accordance with the description ofFIG. 1above, with the patterning of the at least one trench104in the dielectric102. Accordingly, what is shown inFIG. 5follows fromFIG. 1, and like structures are numbered alike in the drawings.

Referring toFIG. 5, a conformal metal liner502is then deposited into and lining the trench104. Suitable metals for liner502include, but are not limited to, Co and/or Ru, which can be deposited into trench104using a process such as PVD, CVD, plating, evaporation, sputtering, etc. According to an exemplary embodiment, metal liner502is formed having a thickness of from about 5 nanometers (nm) to about 20 nm and ranges therebetween. As will be described in detail below, a fill metal (e.g., also Co and/or Ru) will later be deposited over the metal liner502, filling the trench104, to form the interconnect. According to an exemplary embodiment, the same metal as metal liner502will be used to fill the trench104, e.g., both the fill metal and metal liner502are Co or Ru. However, this is not a requirement, and embodiments are contemplated herein where the metal liner502and the fill metal include different metals and/or different combinations of metals. For instance, to use an illustrative, non-limiting example, the metal liner502can be formed from Co, while the fill metal is Ru, and vice versa.

A conformal carbon layer602is then deposited onto the metal liner502. SeeFIG. 6. According to an exemplary embodiment, carbon layer602includes amorphous carbon. However, embodiments are also contemplated herein where carbon layer302includes carbon in other forms including, but not limited to, crystalline graphene.

A fill metal702is then deposited over the carbon layer602and filling the trench104. SeeFIG. 7. Along with metal liner502, this fill metal702forms an interconnect704embedded in the dielectric102. The fill metal702can be deposited using a process such as PVD, CVD, plating, evaporation, sputtering, etc. As provided above, the same metal as metal liner502can be used for the fill metal702, e.g., both metal liner502and fill metal702are Co or Ru. However, this is not a requirement, and embodiments are contemplated herein where the metal liner502and the fill metal702are different metals and/or different combinations of metals. For instance, by way of example only, the metal liner502can be formed from Co, while the fill metal702is Ru, and vice versa.

The fill metal702is then polished using a process such as CMP to remove the overburden. SeeFIG. 8. As shown inFIG. 8, this polishing step also serves to remove the metal liner502and carbon layer602from the top surface of dielectric102, providing a flat, planar surface for the deposition of a second dielectric.

Namely, as shown inFIG. 9, a second dielectric902(where dielectric102is the first dielectric) is deposited onto the dielectric102covering the carbon layer602/interconnect704. Suitable dielectrics902include, but are not limited to, oxide materials such as SiOx and/or SiCOH and/or ultralow-κ interlayer dielectric materials such as pSiCOH. The placement of (second) dielectric902provides an interface at the top of the interconnect704for diffusion of carbon from carbon layer602to form a graphene barrier on the top of the interconnect704.

Namely, the interconnect704and carbon layer602are then annealed under conditions sufficient to diffuse carbon from the carbon layer602, through the metal liner502/metal fill702, to form graphene layer1002at i) the interface between interconnect704and dielectric102and ii) at the interface between interconnect704and dielectric902. SeeFIG. 10. As described above, and in Kwak, a low-temperature anneal can be used to diffuse the carbon from a solid carbon source (in this case carbon layer602) through a metal (in this case metal liner502/metal fill702) and crystallize as graphene (in this case graphene layer1002) at the metal-substrate interfaces (in this case the metal liner502-dielectric102/metal fill702-dielectric902interfaces). If formed from the same material (see above), the metal liner502/metal fill702components of interconnect704would no longer be distinct from one another. As such, dotted lines are used inFIG. 10to distinguish the metal liner502from the metal fill702. However, as provided above, embodiments are also contemplated herein where the metal liner502/metal fill702have different compositions.

As shown inFIG. 10, the result is a (e.g., Co and/or Ru) interconnect704embedded in dielectrics102and902. A wrap-all-around graphene barrier layer (i.e., graphene layer1002) surrounds the interconnect.

According to an exemplary embodiment, the graphene layer1002includes from about 1 monolayer (i.e., a single monolayer) to about 5 monolayers of graphene. By way of example only, the annealing conditions include, but are not limited to, a temperature of less than about 600° C., e.g., from about 25° C. to about 260° C. and ranges therebetween, and a duration of from about 1 minute to about 30 minutes and ranges therebetween.

Alternatively, the above-described one-step graphene growth process both above and below the metal liner502can be employed. See, for example,FIGS. 11-13. This alternative process flow begins in the same manner as described above with the patterning of at least one trench104in the dielectric102, and the deposition of the conformal metal liner502into and lining the trench104. SeeFIG. 5. Accordingly, what is shown inFIG. 11follows fromFIG. 5, and like structures are numbered alike in the drawings.

In this case, however, graphene is grown directly on the metal liner502, using a process such as PECVD, to concurrently form i) graphene layer1102at the dielectric102/metal liner502interface and ii) graphene layer1104on top of metal liner502. SeeFIG. 11. For instance, as described above, and in Lo, direct graphene growth by PECVD on a metal layer can be used to form graphene layers both on top of the metal layer and below the metal layer at the metal-dielectric interface.

A fill metal1202is then deposited (e.g., using PVD, CVD, plating, evaporation, sputtering, etc.) over the graphene layer1104and filling the trench104, followed by polishing process such as CMP to remove the overburden (which also serves to remove the metal liner502and graphene layers1102and1104from the top surface of dielectric102, providing a flat, planar surface for the deposition of a second dielectric). As provided above, the same metal as metal liner502can be used for the fill metal1202, e.g., both metal liner502and fill metal1202are Co or Ru. However, this is not a requirement, and embodiments are contemplated herein where the metal liner502and the fill metal1202are different metals and/or different combinations of metals. For instance, by way of example only, the metal liner502can be formed from Co, while the fill metal1202is Ru, and vice versa. Along with metal liner502, this fill metal1202forms an interconnect1204embedded in the dielectric102.

In the same manner as described above, a second dielectric1206(where dielectric102is the first dielectric) is deposited onto the dielectric102covering the graphene layers1102and1104/interconnect1204. As provided above, suitable dielectrics1206include, but are not limited to, oxide materials such as SiOx and/or SiCOH and/or ultralow-κ interlayer dielectric materials such as pSiCOH. The placement of (second) dielectric1206provides an interface at the top of the interconnect1204for diffusion of carbon from graphene layers1102and1104to form a graphene barrier on the top of the interconnect1204.

The interconnect1204and graphene layers1102and1104are then annealed under conditions sufficient to diffuse carbon from the graphene layers1102and1104, through the metal liner502/metal fill1202, to form graphene layer1302at the interface between interconnect1204and dielectric1206. SeeFIG. 13. As described above, and in Kwak, a low-temperature anneal can be used to diffuse the carbon from a solid carbon source (in this case graphene layers1102and1104) through a metal (in this case metal liner502/metal fill1202) and crystallize as graphene (in this case graphene layer1302) at the metal-substrate interfaces (in this case the metal fill1202-dielectric1206interface). If formed from the same material (see above), the metal liner502/metal fill1202components of interconnect1204would no longer be distinct from one another. As such, dotted lines are used inFIG. 13to distinguish the metal liner502from the metal fill1202. However, as provided above, embodiments are also contemplated herein where the metal liner502/metal fill1202have different compositions.

As shown inFIG. 13, the result is a (e.g., Co and/or Ru) interconnect1204embedded in dielectrics102and1206. A wrap-all-around graphene barrier layer (i.e., graphene layers1102and1302) surrounds the interconnect.

According to an exemplary embodiment, graphene layers1102and1302each includes from about 1 monolayer (i.e., a single monolayer) to about 5 monolayers of graphene. By way of example only, the annealing conditions include, but are not limited to, a temperature of less than about 600° C., e.g., from about 25° C. to about 260° C. and ranges therebetween, and a duration of from about 1 minute to about 30 minutes and ranges therebetween.

In a variation to the process flow ofFIG. 11-13, a surface carbon burn out is performed to remove the graphene layer above the metal liner, and a separate graphene growth step is employed to form the barrier layer on top of the interconnect. See, for example,FIGS. 14-17. This alternative process flow begins in the same manner as described in accordance with the description ofFIG. 11above, with the patterning of at least one trench104in the dielectric102, depositing a conformal metal liner502(e.g., Co and/or Ru) into and lining the trench104, and forming a graphene layer at the dielectric102/metal liner502interface. As such, what is shown inFIG. 14follows fromFIG. 7, and like structures are numbered alike in the drawings.

Using the embodiment depicted inFIG. 11as an example, direct growth of graphene on the metal liner502can be employed to concurrently form the graphene layer1102at the dielectric102/metal liner502interface. Namely, as described above and in Lo, direct graphene growth by PECVD on a metal layer can be used to form graphene layers both on top of the metal layer and below the metal layer at the metal-dielectric interface.

Here, however, the next task is to remove the graphene layer that is on top of the metal liner502. SeeFIG. 14. Namely, comparingFIG. 11toFIG. 14, it can be seen that the graphene layer1104on top of metal liner502has been removed. According to an exemplary embodiment, graphene layer1104is removed using a surface carbon burn out process. Namely, the carbon in graphene layer1104can react with oxygen, hydrogen and/or fluorine in plasma or thermal reaction to form a volatile gas, such as CO2, CH4and CxFy, that is removed. This reaction can occur at a wide range of temperatures and thermal reaction will occur at temperatures such as 200° C. and above. By this process, the graphene layer1104is removed from the structure in the form of a gas. The graphene layer1102, which is buried beneath the metal liner502, is unaffected by this surface burn out procedure.

Next, as shown inFIG. 15, a fill metal1502is deposited (e.g., using PVD, CVD, plating, evaporation, sputtering, etc.) onto the metal liner502and filling the trench104. Along with metal liner502, this fill metal1502forms an interconnect1504embedded in the dielectric102. As provided above, the same metal as metal liner502can be used for the fill metal1502, e.g., both metal liner502and fill metal1502are Co or Ru. As such, dotted lines are used inFIG. 15to distinguish the metal liner502from the fill metal1502. However, this is not a requirement, and embodiments are contemplated herein where the metal liner502and the fill metal1502are different metals and/or different combinations of metals. For instance, by way of example only, the metal liner502can be formed from Co, while the fill metal1502is Ru, and vice versa.

The fill metal1502is then polished using a process such as CMP to remove the overburden. SeeFIG. 16. As shown inFIG. 16, this polishing step also serves to remove the metal liner502and graphene layer1102from the top surface of dielectric102, providing a flat, planar surface for further processing.

A graphene layer1702is then deposited on top of the interconnect1504. SeeFIG. 17. As described in U.S. Patent Application Publication Number 2011/0303899, graphene can be grown on a metallic layer (e.g., Co) using a CVD-based process and a carbon precursor such as acetylene. According to an exemplary embodiment, graphene layers1102and1702each includes from about 1 monolayer (i.e., a single monolayer) to about 5 monolayers of graphene.

Finally, a second dielectric1704(where dielectric102is the first dielectric) is deposited onto the dielectric102covering the interconnect1504/graphene layer1702. As provided above, suitable dielectrics1704include, but are not limited to, oxide materials such as SiOx and/or SiCOH and/or ultralow-κ interlayer dielectric materials such as pSiCOH.

As shown inFIG. 17, the result is a (e.g., Co and/or Ru) interconnect1504embedded in dielectrics102and1704. A wrap-all-around graphene barrier layer (i.e., graphene layers1102and1702) surrounds the interconnect.