Simulation apparatus, simulation method, and program to perform simulation on design data of a target circuit

A simulation apparatus that performs simulation of design data of a verification target circuit including a logic circuit that operates as a multi-cycle path of N cycles in synchronization with a clock signal, the simulation apparatus includes a design data generation section that generates design data of a multi-cycle verification circuit for selectively providing an undefined value signal in place of a signal in a multi-cycle part in the verification target circuit; a logical simulation section that performs logical simulation, without delay, on the basis of design data of the verification target circuit and the design data of the multi-cycle verification circuit; and a comparison section that compares the signal of the verification target circuit with a signal of an expected value in the verification target circuit in the logical simulation.

CROSS REFERENCES TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-74077 filed on Mar. 21, 2008, the entire contents of which are incorporated herein by reference.

BACKGROUND

Aspects in accordance with the present invention relate to a simulation apparatus, a simulation method, and a program.

2. Description of the Related Art

FIG. 2illustrates a test bench for simulating a clock synchronization logic circuit that includes two flip-flops103and104and a combinational circuit112connected between the flip-flops. A test bench101is a system that includes a verification target circuit102and a test description.

A simple example of the verification target circuit102is described using the clock synchronization logic circuit including the two flip-flops103and104and the combinational circuit112connected between the flip-flops. Such a clock synchronization logic circuit is commonly used in semiconductor integrated circuits.

FIG. 3is a timing chart illustrating an examplary operation of the verification target circuit102. The number of cycles denotes the number of cycles of a clock signal CLK. In a cycle1, the first flip-flop103holds data input into an input terminal DI in synchronization with a rise of the clock signal CLK, and outputs data FF1DO from an output terminal DO. The data FF1DO, in the cycle1, reaches an input terminal DI of the second flip-flop104as data FF2DI via the combinational circuit112. That is, in the one cycle, the output data FF1DO of the first flip-flop103reaches the input terminal DI of the second flip-flop104as the data FF2DI. Such a circuit is referred to as a single cycle path. In the single cycle path, data delay between the flip-flop103and the flip-flop104is within one cycle.

In a cycle2, when a write-enable signal FF2WE is at a high level, the second flip-flop104holds the data FF2DI input into the input terminal DI in synchronization with a rise of the clock signal CLK, and outputs data FF2DO from an output terminal DO. The second flip-flop104, when the write-enable signal FF2WE is at a low level, holds the data without writing the data, and outputs the held data from the output terminal DO as the data FF2DO.

In the verification target circuit102, if data delay is within N cycles at a maximum, any delay may be permitted. Such a state is referred to as a multi-cycle path. Here, N is a natural number more than one.

FIG. 4Ais a timing chart for a situation where the verification target circuit102inFIG. 2is a multi-cycle path of N cycles. Similarly to the above case, in the cycle1, the first flip-flop103holds data input into the input terminal DI in synchronization with a rise of the clock signal CLK, and outputs the data FF1DO from the output terminal DO. In response to the operation, since the input data FF2DI of the second flip-flop104is permitted to vary to a new value at a timing of any one of cycles1to4, in the cycles1to4, the value is an undefined value (undefined value of zero or one). The second flip-flop104is required to perform correct circuit operation even if the input data FF2DI varies during any one of the cycles1to4.

When the write-enable signal FF2WE is at the high level, the second flip-flop104holds the data FF2DI input into the input terminal DI in synchronization with a rise of the clock signal CLK, and outputs the data FF2DO from the output terminal DO. Accordingly, the output data FF2DO has an undefined value during cycles2to4.

In the circuit, the output data FF1DO of the first flip-flop103in the cycle1reaches the input terminal DI of the second flip-flop104as the data FF2DI in any one of the cycles1,2,3, to N. In order to use the circuit as a multi-cycle path, it is necessary to design the circuit such that even if the input data FF2DI of the second flip-flop104varies in any one of the cycles1,2,3, to N, the circuit correctly operates.

Generally, the multi-cycle path is intentionally designed by a circuit designer. In the description below, it is assumed that paths of the multi-cycle path are described in timing constraint information (Design Constraints) or the like that is used as standard input information in circuit specifications, logic synthesis, layout, wiring, and static timing analysis that are development flows after logic verification.

In the description, the development of the semiconductor integrated circuit is implemented in accordance with steps of, as a first step, implementing design of a logic circuit at a register transfer level (hereinafter, referred to as RTL) (logic design), as a second step, verifying validity of the logic circuit (logic verification), as a third step, synthesizing the verified logic circuit to a gate level (logic synthesis), as a fourth step, laying out and wiring the synthesized circuit (layout and wiring), and as a fifth step, implementing timing verification (static timing analysis (STA)). Further, in the specification, gate level simulation that includes delay is described. It is assumed that the gate level simulation is implemented as a sixth step after the static timing analysis is completed.

Now, problems where the multi-cycle path is verified at RTL are described. When the circuit designer verifies operation of the multi-cycle path as a logic circuit, with respect to a signal defined as a multi-cycle path, and additionally verifies whether the signal can actually be used as the multi-cycle path it is necessary to verify the logic circuit operation in consideration of delay.

This is because, in the multi-cycle path, it is necessary to check whether the operation of the multi-cycle path is normal even if data delay in a period, when the output data FF1DO of the first flip-flop103reaches the input terminal DI of the second flip-flop104as the data FF2DI, is in any one of the cycles1,2,3, to N.

Normally, the operation verification in the logical verification is implemented at RTL without delay. If the delay is not included, it is difficult to verify whether the multi-cycle path of N cycles operates normally even when the data delay is at any one of the cycles1,2,3, to N. Hereinafter, the reason is described.

FIG. 4Bis a timing chart where logical verification of a multi-cycle path is implemented at RTL. At RTL, gate delay and wiring delay between the flip-flop103and the flip-flop104is not considered. Accordingly, if the output data FF1DO of the first flip-flop103varies in the cycle1, the input data FF2DI of the second flip-flop104also varies in the same cycle1. In the next cycle2, the output data FF2DO of the second flip-flop104is fixed to a new value.

If the timing chart inFIG. 4Bis compared to the timing chart of the single cycle path inFIG. 3, it is understood that, in both cases, the operation of the second flip-flop104at the rise timing of the clock signal CLK is the same. This means that, in both cases, the operation is the same as verification of the single cycle path. Further, if the timing chart inFIG. 4Bis compared to the operational view of the multi-cycle path of N cycles inFIG. 4A, it is understood that, in the operation of the second flip-flop104, at the rise timing of the clock signal CLK, the values are different from values originally expected in the multi-cycle path in cycles2to4. Accordingly, it is understood that it is not possible to correctly verify the multi-cycle path in the logical simulation at RTL.

As the method to perform verification of operation of a logic circuit in consideration of delay, two methods described below have been known.

In the first method, the verification is performed by gate level simulation that is performed after the circuit is laid out and wired. In the gate level simulation to be performed after the circuit is laid out and wired actual gate delay and wiring delay is contained. Accordingly, it is possible to consider data delay in the multi-cycle path.

The first method is excellent in verifying that the specific semiconductor integrated circuit correctly operates. However, the verification is performed in the state that the gate delay and the wiring delay have values unique to the semiconductor integrated circuit. Accordingly, in the verification, the operation (FIG. 4A) of the multi-cycle path of N cycles, where the data variation is in any one of the cycles1,2,3, to N, the correct operation of the multi-cycle path is not verified.

Further, to perform the logical simulation with the gate delay and the wiring delay, it is necessary to perform the simulation after the logic synthesis, the layout, the wiring, the static timing analysis (STA), and the like. These are the development flows performed after the logic verification is performed. Accordingly, a large amount of additional man-hours are required for returning to the job when a malfunction is found in specifying the multi-cycle path. Especially, in the development of current semiconductor integrated circuits that are growing in scale, a loss of efficiency during the development period is very serious.

As the second method, in Japanese Patent Application Laid-Open Publication No. 2006-318121, a method to intentionally apply delay to a target part in RTL verification is described. In the RTL description, it is possible to add a delay value to a specific signal. The function can be used in many simulation apparatuses. Accordingly, it is possible to reproduce pseudo logical verification with consideration of delay.

However, in the second method, the delay value that can be applied in one logical simulation is a constant value. Accordingly, similar to the first method, in the second method, in order to verify that the multi-cycle path of N cycles operates correctly (FIG. 4A) when the data variation is at any one of the cycles1,2,3, to N, it is necessary to perform logical simulation at least N times with respect to one multi-cycle path, and it is not efficient.

For example, in a case where a plurality of multi-cycle paths of N cycles exist in a circuit, and the paths are operationally associated with each other, it may be necessary to consider combinations of delay values to be applied to the individual multi-cycle paths. As a result, the number of combinations necessary for the verification becomes enormous.

Further, as a third method, in Japanese Patent Application Laid-Open Publication No. 2001-273351, a technique to analyze a circuit configuration at RTL or a gate level and provide a part that can be defined as a multi-cycle path has been described. The method is effective to exhaustively search for multi-cycle paths including a multi-cycle path unintentionally made by the circuit designer.

However, in the multi-cycle paths in the circuit, in addition to a multi-cycle path defined by the circuit configuration, many parts that can be defined as multi-cycle paths by reasons depending on the specification, or the other logical circuits exist. Accordingly, it is difficult to determine whether multi-cycle part information described in the circuit specification or the like is really correct using only this technique.

SUMMARY

According to aspects in accordance with an embodiment, a simulation apparatus is provided that performs simulation of design data of a verification target circuit including a logic circuit that operates as a multi-cycle path of N cycles in synchronization with a clock signal, the simulation apparatus includes a design data generation section that generates design data of a multi-cycle verification circuit for selectively providing an undefined value signal in place of a signal in a multi-cycle part in the verification target circuit, a logical simulation section that performs logical simulation without delay on the basis of design data of the verification target circuit and the design data of the multi-cycle verification circuit, and a comparison section that compares the signal of the verification target circuit with a signal of an expected value in the verification target circuit in the logical simulation.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIG. 13is a block diagram illustrating an example of a configuration of a computer included in the simulation apparatus according to aspects in accordance with a first embodiment. The computer can generate RTL design data and net list design data by computer-aided design (CAD), and perform simulation.

To a bus1301, a central processing unit (CPU)1302, a read-only memory (ROM)1303, a random access memory (RAM)1304, a network interface1305, an input device1306, an output device1307, and an external storage device1308are connected.

The CPU1302performs processing of data and calculation, and controls the above-described configuration unit that is connected via the bus1301. In the ROM1303, a boot program is stored in advance. By implementing the boot program by the CPU1302, the computer is started up. In the external storage device1308, a computer program is stored. The computer program is copied into the RAM1304, and the program is implemented by the CPU1302. The computer can perform simulation and multi-cycle verification described below by implementing the computer program.

The external storage unit1308is, for example, a hard disk storage device. Even if power source of the device1308is turned off, the memory content is not lost. The external storage unit1308can record a computer program, RTL design data, and the like in a recording medium, and read the computer program or the like from the recording medium.

The network interface1305can input or output a computer program, RTL design data, or the like to a network. The input device1306is, for example, a keyboard or a pointing device (mouse). Using the input device1306, it is possible to perform various specifying operations or inputting operations. The output device1307is a display, a printer, or the like. The output device1307can display or print.

The embodiment can be realized by implementing the program by the computer. Further, means for providing the program to the computer, for example, a computer-readable recording medium such as a compact disc read only memory (CD-ROM) that records the program and a transmission medium such as the Internet that transmits the program can be applied as embodiments. Further, a computer program product such as the computer-readable recording medium that records the program can be applied as an embodiment. The program, the recording medium, the transmission medium, and the computer program product can be included in the scope of the present invention. As the recording medium, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, and the like can be used.

FIG. 1is a schematic view illustrating a test bench of a simulation apparatus according to aspects of the embodiment. A test bench401is a system that includes a verification target circuit402and a test description. The test bench401is software (program) for performing simulation. The test bench401includes the verification target circuit402and a multi-cycle verification section414. The verification target circuit402and the multi-cycle verification section414are circuit data described in RTL design data. In a simulation apparatus inFIG. 13, the test bench401is installed. By implementing the test bench401, simulation is performed.

The verification target circuit402is, for example, a clock synchronization logic circuit that includes two flip-flops403and404and a combinational circuit412connected between the flip-flops. The combinational circuit412is connected between an output terminal DO of the first flip-flop403and an input terminal DI of the second flip-flop404. The multi-cycle verification section414includes a control section415, an X signal output section416, and a switch417. The switch417, in response to an output signal SWS of the control section415, outputs an output signal of the X signal output section416to the input terminal DI of the second flip-flop404. The X signal output section416outputs an X signal (undefined value signal). The X signal shows an undefined value that is not defined as zero or one.

It is assumed that a circuit from the output terminal DO of the first flip-flop403to the input terminal DI of the second flip-flop404is defined by the circuit designer that the circuit can be considered as a multi-cycle path of N cycles.

In the embodiment, in addition to the verification target circuit402, the multi-cycle verification section414is added. The multi-cycle verification section414, in an M cycle satisfying 1≦M<N, forcibly substitutes the X value output by the X signal output section416in place of an output signal S of the combinational circuit412.

The control section415outputs a control signal SWS depending on multi-cycle part information about a signal to be a multi-cycle target, the number of multi-cycles that permit maximum delay, and a clock to be a reference or a control signal. The switch417, in response to the control signal SWS, outputs the X signal as a signal SWO in a cycle where the output signal S of the combinational circuit412has an undefined value.

FIG. 5is a timing chart illustrating an exemplary operation of the simulation apparatus according to aspects of the first embodiment. The simulation apparatus performs simulation at RTL. The number of cycles shows the number of cycles of a clock signal CLK. Hereinafter, operation of a multi-cycle path of N cycles is described. N is, for example, four.

In a cycle1, the first flip-flop403holds data input into the input terminal DI in synchronization with rising of the clock signal CLK, and outputs data FF1DO from the output terminal DO. Since RTL does not include delay, the combinational circuit412inputs the signal FF1DO and outputs a signal S without delay. In the multi-cycle path of N (for example, four) cycles, input data FF2DI of the second flip-flop404is permitted to vary to a new value in any one of the cycles1to4. Accordingly, the control section415, on the basis of multi-cycle part information (for example, the signal S), the number of multi-cycles (for example, four), and the clock signal CLK associated with the multi-cycle path, outputs an ON control signal SWS in the cycles1to3, and outputs an OFF control signal SWS in the other cycles.

When the control signal SWS is on, the switch417is turned on. Then, an output signal SWO of the switch417becomes the X signal output from the X signal output section416, and the input signal FF2DI of the second flip-flop404also becomes the X signal output from the X signal output section416. When the control signal SWS is off, the switch417is turned off. Then, the output signal SWO of the switch417becomes a high impedance state, and the input signal FF2DI of the second flip-flop404becomes the same signal as the output signal S of the combinational circuit412.

When a write-enable signal FF2WE is at a high level, the second flip-flop404holds the data FF2DI input into the input terminal DI in synchronization with a rise of the clock signal CLK, and outputs data FF2DO from the output terminal DO. Accordingly, the output data FF2DO has an undefined value X in the cycles2to4.

In the M cycle satisfying 1≦M<N, that is, in cycles1to N−1, the switch417is turned on. Accordingly, the input signal FF2DI of the second flip-flop404has an undefined value X. After the operation, the switch417is turned off, and the input signal FF2DI of the second flip-flop404has the same signal as the signal S in the cycle N.

Now, the timing chart inFIG. 5is compared with the timing chart of the multi-cycle path of N cycles inFIG. 4A. InFIG. 4A, the input signal FF2DI of the second flip-flop104varies at any one of the cycles1to N. This means that in the cycles1to N−1, the value is an undefined value X. The input signal FF2DI of the second flip-flop104is fixed to a new value in the cycle N.

On the other hand, if the timing charts inFIGS. 4A and 5are compared with each other, operation of the second flip-flops104and404at the rising timing of the clock signals CLK corresponds to each other. That is, the timing chart obtained by the simulation apparatus according to aspects of the embodiment is the same operation as that expected in the multi-cycle path of N cycles.

Accordingly, the simulation apparatus according to aspects of the embodiment can easily reproduce the operation of the multi-cycle path of N cycles at RTL that is the early stage in the circuit design. Further, it is possible to verify the multi-cycle path of N cycles by one simulation without the problems described above, where “the data delay is fixed to a constant value” and “it is necessary to perform simulation a plurality of times”.

FIG. 6is a flow chart illustrating an exemplary operation of the simulation apparatus according to aspects of the first embodiment. In the embodiment, operation of the multi-cycle path of N cycles can be verified.

To the simulation apparatus, multi-cycle part information601is input as input information600, in addition to a test bench602including a verification target circuit (logic circuit) that is necessary for the logical verification, and a verification pattern (test pattern)603. All of the input information600is read into the simulation apparatus, and simulation is implemented.

The multi-cycle part information601can be used as a multi cycle defined by the circuit designer. It is assumed that the multi-cycle part information601includes a signal name in the multi-cycle part, a flip-flop name, the number of multi cycles, and information about other signals in an associated logic circuit. The test bench602corresponds to the test bench401inFIG. 1. The verification pattern603is input test data of the verification target circuit402.

A logical simulation device604is formed by software processing in steps605and606. In step S605, as illustrated inFIG. 1, on the basis of the multi-cycle part information601and the test bench602, the simulation apparatus generates design data of the multi-cycle verification section414, and installs the multi-cycle verification section414at a specified part. Then, in step S606, as illustrated inFIG. 5, the simulation apparatus performs logical simulation without delay on the basis of the test bench (including the multi-cycle verification section414)602and the verification pattern603, and outputs a simulation result607. The simulation result607is an output signal of the verification target circuit402generated in the logical simulation.

The logical simulation in the simulation apparatus is different from a normal logical simulation in performing the logical simulation step606after reading the multi-cycle part information601and installing the circuit of the multi-cycle verification section414inFIG. 4.

An expected value608is a signal of an expected value generated as a result of the simulation of the verification target circuit402when the operation of the verification target circuit402is correct. In step S609, the simulation apparatus compares the simulation result607with the expected value608that is provided in advance.

If the simulation result607differs from the expected value608, the processing proceeds to step S611. In step S611, the simulation apparatus determines there is a problem in the verification result of the multi-cycle part. This means that the multi-cycle part does not operate as expected. The reason of the malfunction may be that the multi-cycle part information601is not correct, that the verification target circuit (logic circuit)402is not configured to correspond to the multi-cycle path, or the like.

In step S612, the simulation apparatus reviews the test bench602, the verification pattern603, and the multi-cycle part information601that are the input information600, and corrects the verification target circuit (logic circuit)402. After the correction, the above processing is repeated until the simulation result607corresponds to the expected value608.

If the simulation result607corresponds to the expected value608, the processing proceeds to step S610. In step S610, the simulation apparatus can determine as described below. That is, first, it is possible to verify that the logical operation, considering the delay in the multi-cycle part, is correct. Secondly, it can be understood that the contents of the multi-cycle part information601used as the input information600are correct.

In the development of the semiconductor integrated circuit, as the first step, design of the logic circuit at RTL is implemented (logic design), as the second step, the validity of the logic circuit inFIG. 6is verified (logic verification), as the third step, the verified logic circuit is synthesized to the gate level (logic synthesis), as the fourth step, the synthesized circuit is actually laid out and wired (layout and wiring), and as the fifth step, the timing verification is implemented (static timing analysis (STA)). Further, as the sixth step, the gate level simulation with delay is implemented.

As described above, according to the embodiment, the multi-cycle path can be verified at the early stage (RTL stage) of the design. Previously, in order to check whether the operation of the multi-cycle path is correct or not, it was necessary to perform the gate level simulation with wiring delay and gate delay, the simulation is the development step to be implemented after the logical verification. However, by using the simulation apparatus according to aspects of the embodiment, it is possible to check the operation at RTL at an early stage of the circuit design.

Further, in aspects of the embodiment, the multi-cycle path can be exhaustively verified. Further, in aspects of the embodiment, it is possible to verify the operation equivalent to the operation of the multi-cycle path of N cycles by the one simulation in the RTL verification without the previous problems in the multi-cycle path verification that “the data delay is fixed to a constant value” and “it is necessary to perform simulation a plurality of times”.

Further, in aspects of the embodiment, it is possible to check the validity of the multi-cycle path intentionally designed by the designer. Using the simulation apparatus according to aspects of the embodiment, in the multi-cycle path defined by the circuit designer, it is possible to check whether the part defined as the multi-cycle path by the circuit designer can really be used as the multi-cycle path.

Second Embodiment

FIG. 7is a schematic view illustrating a test bench of a simulation apparatus according to aspects of a second embodiment. In the second embodiment (FIG. 7), aspects are similar to the first embodiment (FIG. 1). Hereinafter, only the differences for the second embodiment are described.

In aspects of the second embodiment, when the test bench401is installed in the simulation apparatus, the signal S and the signal FF2DI are disconnected. The signal S is transmitted to the signal FF2DI via the multi-cycle verification section414. After simulation is completed, the multi-cycle verification section414is deleted, and the signal S is directly connected to the signal FF2DI by a signal line725.

The multi-cycle verification section414includes a signal variation observation section715that observes variation of the signal S, a counter CNT that calculates the number of cycles to drive an X signal on the basis of the number of multi-cycles N, an X signal output section717that outputs an X signal, and a selector718that selectively provides the X signal or the signal S to the input terminal DI of the second flip-flop404.

FIG. 8is a timing chart illustrating an exemplary operation of the simulation apparatus according to aspects of the second embodiment. In a cycle1, the output signal FF1DO of the first flip-flop403varies, and the variation reaches the signal S. Then, the signal variation observation section715in the multi-cycle verification section414detects the variation of the multi-cycle signal S, and outputs a detection signal OBSOUT as a pulse signal to the counter CNT. Here, the signal S that is a target to be verified is information given as a verification pattern by the circuit designer.

Then, in the cycle1, in response to input of the pulse of the detection signal OBSOUT, the counter CNT sets the number of multi-cycle N−1 (for example, three), starts down count in synchronization with the clock signal CLK, and sets a control signal SELS to a low level. In a cycle4, when the count value becomes zero, the counter CNT sets the control signal SELS to a high level. Here, the multi-cycle signal S and the number of multi-cycles N are information set by the circuit designer.

The selector718selects the signal S when the control signal SELS is at the high level, selects the X signal when the control signal SELS is at the low level, and outputs the selected signal as a signal SELO to the input terminal DI of the second flip-flop404. As a result, the input signal FF2DI of the second flip-flop404has an undefined value X in the cycles1to3, and becomes the same signal as the signal S in the cycle4.

Now, the timing chart inFIG. 8is compared with the timing chart of the multi-cycle path of N cycles inFIG. 4A. InFIG. 4A, the input signal FF2DI of the second flip-flop104varies at timing any one of the cycles1to N. This means that in the cycles1to N−1, the value has an undefined value X. The input signal FF2DI of the second flip-flop104is fixed to a new value in the cycle N.

On the other hand, if the timing charts inFIGS. 8 and 4Aare compared with each other, operation of the second flip-flops104and404at the rising timing of the clock signals CLK corresponds to each other. That is, the timing chart obtained by the simulation apparatus according to aspects of the embodiment is the same operation as that expected in the multi-cycle path of N cycles.

FIG. 9is a flow chart illustrating a simulation method in the simulation apparatus according to aspects of the second embodiment. The second embodiment (FIG. 9) differs from the first embodiment (FIG. 6) in that timing constraint information901is used in place of the multi-cycle part information601. The test bench602corresponds to the test bench401inFIG. 7.

The timing constraint information901is defined by the circuit designer, and generated by formatting information including a list of a multi-cycle part exiting in the verification target circuit402, for example, an Synopsys Design Constraint (SDC) file. The timing constraint information901is normally used in logic synthesis, layout and wiring, and STA that are development flows implemented after logical verification. Normally, the information about a multi-cycle path includes, in addition to a signal name to be a multi-cycle target, and information about an associated flip-flop name, clock information associated with the number of multi cycles. Accordingly, the timing constraint information901is the optimum information to be used as the multi-cycle part information.

In step S605, as illustrated inFIG. 7, on the basis of the timing constraint information (including multi-cycle part information)901and the test bench602, the simulation apparatus generates design data of the multi-cycle verification section414, and installs the multi-cycle verification section414at a specified part. Then, in step S606, as illustrated inFIG. 8, the simulation apparatus performs simulation without delay on the basis of the test bench (including the multi-cycle verification section414)602and the verification pattern603, and outputs the simulation result607.

In step S609, the simulation apparatus compares the simulation result607with the expected value608. When the simulation result607differs from the expected value608, it means that the operation in the multi-cycle part is not the expected operation. Then, the processing proceeds to step S611As the reason of the malfunction of the multi-cycle path, it can be considered that the timing constraint information901is not correct, the circuit is not configured to correspond to the multi-cycle path, or the like. In such a case, in step S612, the simulation apparatus reviews the test bench602, the verification pattern603, and the timing constraint information901that are the input information600, and corrects the verification target circuit (logic circuit)402. After the correction, the processing inFIG. 9is repeated until the simulation result607corresponds to the expected value608.

When the simulation result607corresponds to the expected value608, the processing proceeds to step S610. Then, the simulation apparatus can operate as described below. That is, first, it is possible to verify that the logical operation considering the delay in the multi-cycle part is correct. Secondly, it can be understood that the contents of the timing constraint information901used as the input information600are correct.

Especially, when the simulation apparatus according to aspects of the second embodiment is used, it is important that the verification of the timing constraint information901can be performed. Since the timing constraint information901is used as standard input information in the logic synthesis, the layout and the wiring, and the STA that are development flows implemented after the logical verification, by designing the circuit on the basis of the information, it is possible to ensure the operation of the circuit in the gate level simulation with delay after the layout and wiring.

Third Embodiment

FIG. 10is a schematic view illustrating a test bench of a simulation apparatus according to aspects of a third embodiment. In the third embodiment (FIG. 10), similar to the first embodiment (FIG. 1), a specific example of the multi-cycle verification section414is described. Hereinafter, only the different points of the third embodiment are described.

The multi-cycle verification section414includes an X signal output section1016, an a switch SW. The X signal output section1016outputs an X signal. A write enable signal FF2WE is a control signal that shows valid or invalid of writing of an input signal FF2DI into the second flip-flop404. The switch SW, depending on the write enable signal FF2WE, connects or disconnects a terminal of an output signal of the X signal output section1016and a terminal of the signal FF2DI.

The use of the write enable signal FF2WE as the control signal of the switch SW is one of the simplest simulation methods for enabling the signal S to be used as a multi-cycle path. Because, by varying the write enable signal FF2WE depending on the number of multi cycles, in a cycle that has an undefined value, writing of data into the second flip-flop404can be inhibited.

FIG. 11is a timing chart illustrating an example of operation of the simulation apparatus according to aspects of the third embodiment. The write enable signal FF2WE is set to a low level at a cycle the signal S has an undefined value X.

In the cycle1, the output signal FF1DO of the first flip-flop403varies, and the variation reaches the signal S. However, in the cycle1, the write enable signal FF2WE is at the low level. Accordingly, the switch SW is turned on, and the switch SW outputs the X signal as a signal SWO to the input terminal DI of the second flip-flop404. As a result, the input signal FF2DI of the second flip-flop404has an undefined value X similarly to the signal SWO. The second flip-flop404, when the write enable signal FF2WE is at the low level, does not perform the writing of data, and outputs data held in the second flip-flop404as a signal FF2DO. That is, the signal FF2DO is the same data as the previous data, and the data is not changed.

In a cycle N (for example, four), when the write enable signal FF2WE is at the high level, the switch SW is turned off. Then, the output signal SWO of the switch SW becomes a high impedance state. As a result, the input signal FF2DI of the second flip-flop404becomes the same signal as the signal S. The second flip-flop404, when the write enable signal FF2WE is at the high level, writes and holds the input signal FF2DI, and outputs the held data as the signal FF2DO.

To a write enable terminal WE of the second flip-flop404, if a correct write enable signal FF2WE is connected, the output signal FF2WO of the second flip-flop404becomes a correct signal not depending on the X signal. However, to the write enable terminal WE of the second flip-flop404, if an incorrect write enable signal FF2WE is connected, the X signal is transmitted to the output signal FF2WO of the second flip-flop404, and a malfunction occurs in the operation of the verification target circuit402.

Now, the timing chart inFIG. 11is compared with the timing chart of the multi-cycle path of N cycles inFIG. 4A. InFIG. 4A, the input signal FF2DI of the second flip-flop104varies at timing any one of the cycles1to N. This means that in the cycles1to N−1, the input signal FF2DI has an undefined value X. The input signal FF2DI is fixed to a new value in the cycle N.

On the other hand, if the timing charts inFIGS. 11 and 4Aare compared with each other, operation of the second flip-flops104and404at the rising timing of the clock signals CLK corresponds to each other. That is, the timing chart obtained by the simulation apparatus according to aspects of the embodiment is the same operation as that expected in the multi-cycle path of N cycles.

FIG. 12is a flow chart illustrating a simulation method in the simulation apparatus according to aspects of the third embodiment. The third embodiment (FIG. 12) differs from the first embodiment (FIG. 6) in that a list1201is used in place of the multi-cycle part information601. The test bench602corresponds to the test bench401inFIG. 10. Hereinafter, the points of the third embodiment that are different from those in the first embodiment are described.

The list1201includes a multi-cycle signal name (for example, signal S) and a signal (for example, write enable signal FF2WE) that shows valid or invalid for the signal. The list1201is set by the designer.

In step S605, as illustrated inFIG. 10, on the basis of the list1201and the test bench602, the simulation apparatus generates design data of the multi-cycle verification section414, and installs the multi-cycle verification section414at a specified part. Then, in step S606, as illustrated inFIG. 11, the simulation apparatus performs logical simulation without delay on the basis of the test bench (including the multi-cycle verification section414)602and the verification pattern603, and outputs the simulation result607.

In step S609, the simulation apparatus compares the simulation result607with the expected value608. When the simulation result607differs from the expected value608, it means that the operation at the multi-cycle part is not the expected operation. Then, the processing proceeds to step S611. The reason of the malfunction in the multi-cycle path can be considered to be that the operation cycle of the write enable signal FF2WE is not the expected operation, or the like. In such a case, in step S612, the simulation apparatus reviews the list1201, the test bench602, and the verification pattern603that are the input information600, and corrects the verification target circuit (logic circuit)402. After the correction, the processing inFIG. 12is repeated until the simulation result1207corresponds to the expected value608.

By the simulation apparatus according to aspects of the third embodiment, the input signal FF2DI of the second flip-flop404is fixed to a value only in the period the write enable signal FF2WE shows the high level. When the connection between the write enable terminal WE of the second flip-flop404and the write enable signal FF2WE or the operation of the write enable signal FF2WE is wrong, an undefined value X is input into the second flip-flop404, and the signal FF2DO has the undefined value X. Accordingly, the simulation result607differs from the expected value608. Thus, it is possible to find the malfunction of the verification target circuit402.

When the simulation result607corresponds to the expected value608, the processing proceeds to step S610. Then, the simulation apparatus can determine as described below. That is, first, it is possible to verify that the logical operation considering the delay in the multi-cycle part is correct. Secondly, the list1201used as the input information600is correct.

As described above, according to aspects of the first to third embodiments, the multi-cycle path can be verified at an early stage (RTL stage) of the design. Previously, in order to check whether the operation of the multi-cycle path is correct or not, it was necessary to perform the gate level simulation with wiring delay and gate delay, the simulation is the development step to be implemented after the logical verification. However, by using the simulation apparatus according to aspects of the embodiments, it is possible to check the operation at RTL at an early stage of the circuit design.

Further, in aspects of the embodiments, the multi-cycle path can be exhaustively verified. Further, in aspects of the embodiments, it is possible to verify the operation equivalent to the operation of the multi-cycle path of N cycles by the one simulation in the RTL verification without the problems in the multi-cycle path verification that “the data delay is fixed to a constant value” and “it is necessary to perform simulation a plurality of times”.

Further, in aspects of the embodiments, it is possible to check the validity of the multi-cycle path intentionally designed by the designer. Using the simulation apparatus according to aspects of the embodiments, in the multi-cycle path defined by the circuit designer, it is possible to check whether the part defined as the multi-cycle path by the circuit designer can really be used as the multi-cycle path.

Especially, in the case of aspects of the second embodiment, not only ensuring the operation as the verification target circuit402, but the validity of the timing constraint information901can be checked, and it is very effective.

Further, using the timing constraint information901verified in aspects of the second embodiment as standard input information in the layout, the wiring, and the STA that are to be implemented after the logic verification, the operation in the gate level simulation implemented after the layout and the wiring can be ensured at an early stage of the design. The feature reduces man-hours by preventing the need to return to the designing phase when a malfunction is found in the timing constraint information901, thereby drastically increasing the design efficiency.

The simulation apparatus according to aspects of the first to third embodiments performs simulation of design data of the verification target circuit402including the logic circuit that operates as the multi-cycle path of N cycles in synchronization with a clock signal. The simulation apparatus includes the design data generation means (step S605inFIG. 6, etc.) that generates design data of the multi-cycle verification circuit (multi-cycle verification section)414for selectively providing an undefined value signal (X signal) in place of a signal in a multi-cycle part in the verification target circuit402, the logical simulation means (step S606inFIG. 6, etc.) that performs logical simulation without delay on the basis of the design data of the verification target circuit402and the design data of the multi-cycle verification circuit414, and the comparison means (step S609inFIG. 6, etc.) that compares the signal607of the verification target circuit with the signal608of the expected value in the verification target circuit in the logical simulation.

InFIG. 7, the multi-cycle verification circuit414includes the signal variation detection circuit (signal variation observation section)715that detects variation of the signal in the multi-cycle part in the verification target circuit402. After variation of the signal is detected, during an M cycle that satisfies 1≦M<N, the multi-cycle verification circuit414provides an undefined value signal in place of the signal in the multi-cycle part in the verification target circuit402.

Further, inFIG. 7, the multi-cycle verification circuit414includes the counter CNT that starts counting in response to the detection of variation of the signal by the signal variation observation circuit715.

Further, inFIG. 7, the multi-cycle verification circuit414includes the selector718that selects the undefined value signal in the M cycle depending on the count value of the counter CNT, selects the signal in the multi-cycle part in the other cycles, and outputs the selected signal to an output destination (for example, the input terminal DI of the second flip-flop404) of the signal in the multi-cycle part.

In step S605inFIG. 9, the design data generation means generates design data of the multi-cycle verification circuit on the basis of multi-cycle part information in the SDC file (timing constraint information)901.

InFIG. 10, the multi-cycle verification circuit414provides an undefined value signal in place of the signal in the multi-cycle part in the verification target circuit402depending on a control signal indicating valid or invalid of the signal in the multi-cycle part in the verification target circuit402. For example, the control signal is the write enable signal FF2WE.

Further, inFIG. 10, the logic circuit in the verification target circuit402includes the second flip-flop404into which the signal S in the multi-cycle part and the write enable signal FF2WE are input.

If logical simulation without delay is to be performed, the design data of the verification target circuit402and the design data of the multi-cycle verification circuit414may be RTL design data or net list design data. However, it is preferable that the data is the RTL design data.

In aspects of the first to third embodiments, the verification of the logic circuit that operates as the multi-cycle path of N cycles can be performed by the simple method at the early stage of the circuit design. Further, in the clock synchronization logic circuit, it is possible to check whether a part defined as a multi-cycle path by the circuit designer can really be used as the multi cycle.

While aspects in accordance with the present invention have been described with reference to the specific embodiments, it is to be understood that the invention is not limited to the embodiments. That is, it is to be understood that various modifications may be employed without departing from the technical idea or the primary features of the invention.