Vertical metal oxide semiconductor transistor and fabrication method thereof

A vertical MOS transistor includes a substrate having therein a first source/drain region and a first ILD layer. A nanowire is disposed in the first ILD layer. A lower end of the nanowire is in direct contact with the first source/drain region, and an upper end of the nanowire is coupled with a second source/drain region. The second source/drain region includes a conductive layer. A gate electrode is disposed in the first ILD layer. The gate electrode surrounds the nanowire. A contact hole is disposed in the first ILD layer. The contact hole exposes a portion of the first source/drain region. A contact plug is disposed in the contact hole. A second ILD layer covers the first ILD layer.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the priority from CN application No. 201710816267.1, filed Sep. 12, 2017, which is included in its entirety herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of semiconductor technology. More particularly, the present invention relates to a vertical metal-oxide-semiconductor (MOS) transistor with a nanowire and a method for fabricating the same.

2. Description of the Prior Art

Vertical transistors are known in the art. In a vertical transistor, a vertical nanowire formed of a semiconductor material, is formed over a substrate, which may be a bulk semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. A gate dielectric and a gate electrode are formed to encircle the nanowire, with the encircled portion of the nanowire forming the channel of the respective vertical transistor. A source and a drain are formed, with one underlying the channel, and the other overlying the channel. The vertical transistor has a gate-all-around structure since the gate may fully encircle the channel. With the all-around gate structure, the drive current of the vertical transistor is high and short-channel effects are minimized.

However, the conventional method for fabricating the vertical transistor with nanowire is too complicated. In addition, the process window is insufficient when the metal-on-diffusion (MD) contact hole is made. This is because the depth of the contact hole at the upper end of the nanowire is different from the depth of the contact hole at the source/drain region in the substrate.

SUMMARY OF THE INVENTION

The main object of the present invention is to provide an improved vertical metal-oxide-semiconductor (MOS) transistor which can solve the above-mentioned drawbacks and shortcomings of the prior art.

Another object of the present invention is to provide a method for manufacturing a vertical MOS transistor which can be compatible with the conventional Si FinFET process.

According to one embodiment of the invention, a method for fabricating a vertical MOS transistor is provided. A substrate having therein a first source/drain region and a first inter-layer dielectric (ILD) layer covering the first source/drain region is provided. An opening is formed in the first ILD layer so as to expose a portion of the first source/drain region. A nanowire is epitaxially grown in the opening. A top surface of the nanowire is recessed in the opening thereby forming a recess atop the nanowire. A contact hole is formed in the first ILD layer. The contact hole exposes a portion of the first source/drain region. A conductive layer is formed in the recess and a contact plug is formed in the contact hole. The conductive layer acts as a second source/drain region. The conductive layer is capped with a first mask layer and the contact plug is capped with a second mask layer. A top surface of the first mask layer, a top surface of the second mask layer, and a top surface of the first ILD layer are coplanar. A gate trench is formed in the first ILD layer surrounding the nanowire. A gate electrode is formed in the gate trench.

According to one aspect of the invention, a vertical MOS transistor includes a substrate having therein a first source/drain region and a first ILD layer. A nanowire is disposed in the first ILD layer. A lower end of the nanowire is in direct contact with the first source/drain region, and an upper end of the nanowire is coupled with a second source/drain region. The second source/drain region includes a conductive layer. A gate electrode is disposed in the first ILD layer. The gate electrode surrounds the nanowire. A contact hole is disposed in the first ILD layer. The contact hole exposes a portion of the first source/drain region. A contact plug is disposed in the contact hole. A second ILD layer covers the first ILD layer.

DETAILED DESCRIPTION

The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale.

As described in the embodiments herein, steps such as deposition, patterning or etching of various films (including conductive films, metals, dielectric layers, etc.) can be accomplished using known processes such as chemical vapor deposition, physical vapor deposition, sputtering, atomic layer deposition, optical lithography processes, plasma dry etching, wet etching, reactive ion etching, and the like, the details of which will not be repeated.

Referring toFIG. 1, there is shown a schematic view of a vertical metal-oxide-semiconductor (MOS) transistor according to an embodiment of the present invention. As shown inFIG. 1, the vertical MOS transistor1comprises a substrate100, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, or any other semiconductor substrates. On the substrate100is provided a first source/drain region101and a trench insolation structure102surrounding the first source/drain region101. According to an embodiment of the present invention, the first source/drain region101may be an N++heavily doped region, but is not limited thereto. The trench isolation structure102may be a shallow trench isolation (STI) structure.

According to an embodiment of the present invention, a first interlayer dielectric (ILD) layer110, such as a silicon oxide layer, is provided on the main surface100aof the substrate100, covering the first source/drain region101and the trench isolation structure102. According to an embodiment of the present invention, an etch stop layer112, such as a silicon nitride layer, may be provided between the substrate100and the first ILD layer110.

According to an embodiment of the present invention, a nanowire200is provided in the first ILD layer110and the etch stop layer112. The lower end portion200aof the nanowires200is in direct contact with the first source/drain region101. An upper end portion200bof the nanowires200is coupled to a second source/drain region201disposed in the first ILD layer110. The second source/drain region201comprises a conductive layer210directly situated on the upper end portion200bof the nanowire200.

According to an embodiment of the present invention, the vertical MOS transistor1further comprises a gate electrode300disposed in the first ILD layer110and on the etch stop layer112. The gate electrode300surrounds the nanowires200and is provided corresponding to a gate channel region of the nanowire200. According to an embodiment of the present invention, the gate electrode300is located between the first source/drain region101and the second source/drain region201and continuously surrounds the nanowires200to form an all-around-gate (AAG) structure. The etch stop layer112is interposed between the gate electrode300and the first source/drain region101so that the gate electrode300is electrically insulated from the first source/drain region101.

According to an embodiment of the present invention, the gate electrode300may comprise a plurality of layers of metal including, but not limited to, barrier layers, work function layers, low resistance metal layers, or the like. According to an embodiment of the present invention, a high dielectric constant (high-k) dielectric layer310, such as a dielectric layer having a dielectric constant greater than 3.9, may be provided between the gate electrode300and the etch stop layer112and between the gate electrode300and the nanowire200.

According to an embodiment of the present invention, in the first ILD layer110, a contact hole401is provided adjacent to the nanowire200. The contact hole401exposes a portion of the first source/drain region101. A contact plug410is provided in the contact hole401. The contact plug410has a top surface410awhich is flush with a top surface210aof the conductive layer210.

According to an embodiment of the present invention, a second interlayer dielectric (ILD) layer120, such as a silicon oxide layer, is deposited on the first ILD layer110. According to an embodiment of the present invention, a contact etch stop layer122may be provided between the first ILD layer110and the second ILD layer120.

According to an embodiment of the present invention, the vertical MOS transistor1further comprises a first metal-on-diffusion (MD) contact element522provided in the second ILD layer120and the contact etch stop layer122. The first MD contact element522is in direct contact with the conductive layer210.

According to an embodiment of the present invention, the vertical MOS transistor1further comprises a second MD contact element524disposed in the second ILD layer120, the contact etch stop layer122, and the first ILD layer110. The second MD contact element524is in direct contact with the contact plug410.

According to an embodiment of the present invention, the vertical MOS transistor1further comprises a metal-on-poly (MP) contact element526disposed in the second ILD layer120and the contact etch stop layer122. The MP contact element526is in direct contact with the gate electrode300.

According to an embodiment of the present invention, the vertical MOS transistor1further comprises a first silicide layer220disposed between the conductive layer210and the nanowires200. According to an embodiment of the present invention, the vertical MOS transistor1further comprises a second silicide layer420disposed between the contact plug410and the first source/drain region101.

FIGS. 2 to 15illustrate a method of manufacturing a vertical MOS transistor. First, as shown inFIG. 2, a substrate100, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, or any other semiconductor substrates is provided. On the substrate100is provided a first source/drain region101and a trench isolation structure102surrounding the first source/drain region101. According to an embodiment of the present invention, the first source/drain region101may be an N++heavily doped region, but is not limited thereto.

Next, on the main surface100aof the substrate100, an etch stop layer112, such as a silicon nitride layer, is deposited to cover the first source/drain region101and the trench isolation structure102. A first interlayer dielectric (ILD) layer110, such as a silicon oxide layer, is deposited on the etch stop layer112.

As shown inFIG. 3, an opening110ais formed in the first ILD layer110and the etch stop layer112, and the first source/drain region101is partially exposed. According to an embodiment of the present invention, optionally, referring toFIGS. 16 to 18, the width of the opening110amay be reduced at this time. As shown inFIG. 16, an opening110ahaving a width W1is formed in the first ILD layer110and the etch stop layer112. As shown inFIG. 17, a thin film layer111, for example, a silicon oxide layer, is conformally deposited on the first ILD layer110and in the opening110aby atomic layer deposition. As shown inFIG. 18, the thin film layer111is subjected to anisotropic dry etching and an opening110bhaving a width W2is formed.

As shown inFIG. 4, a nanowire200is grown in an epitaxial manner in the opening110a. The nanowires200may contain silicon, silicon germanium semiconductors, but is not limited thereto. According to an embodiment of the present invention, the lower end portion200aof the nanowires200is in direct contact with the first source/drain region101.

As shown inFIG. 5, an etching process is performed to recess an upper end portion200bof the nanowire200into the opening110a, thereby forming a recess250atop the nanowires200.

As shown inFIG. 6, a contact hole260is formed in the first ILD layer110and the etch stop layer112. The contact hole260exposes a portion of the first source/drain region101.

As shown inFIG. 7, after forming the contact hole260in the first ILD layer110and the etch stop layer112, a first silicide layer220and a second silicide layer420are formed in the recess250and the contact hole260, respectively. The first silicide layer220and the second silicide layer420may comprise titanium silicide (TiSix), but are not limited thereto. A barrier layer610, such as titanium, titanium nitride, or a combination thereof, is deposited on the top surface of the first ILD layer110and in the recess250and the contact hole260. A metal layer612, such as a tungsten layer, is then deposited on the barrier layer610. The recess250and the contact hole260are completely filled with the barrier layer610and the metal layer612.

As shown inFIG. 8, a chemical mechanical polishing (CMP) process is performed to planarize the metal layer612and the barrier layer610, so as to form a conductive layer210and a contact plug410in the recess250and the contact hole260, respectively. The conductive layer210serves as a second source/drain region.

As shown inFIG. 9, the conductive layer210is capped with a first mask layer622and the contact plug410is capped with a second mask layer624. A top surface622aof the first mask layer622, a top surface624aof the second mask layer624and a top surface110cof the first ILD layer110are coplanar. According to an embodiment of the present invention, the first mask layer622and the second mask layer624may be silicon nitride layers. The manner of forming the first mask layer622and the second mask layer624includes etching back the conductive layer210and the contact plug410, depositing a dielectric layer, such as a silicon nitride layer, and applying a planarization process.

As shown inFIG. 10, agate trench630surrounding the nanowire200is formed in the first ILD layer110. According to an embodiment of the present invention, the depth of the gate trench630is approximately equal to the thickness of the first ILD layer110. According to an embodiment of the present invention, the bottom surface of the gate trench630is the top surface of the etch stop layer112. According to an embodiment of the present invention, optionally, a surface repair process, for example, in-situ steam generation (ISSG) process, may be performed on the surface of the nanowires200to form a silicon oxide surface layer230.

As shown inFIG. 11, a high dielectric constant (high-k) dielectric layer310is conformally deposited in the gate trench630as a gate dielectric layer, and a gate electrode300is formed on the high-k dielectric layer310. The gate electrode300is then planarized by a chemical mechanical polishing process so that the gate electrode300is located only in the gate trench630. At this point, the top surface of the gate electrode300is approximately flush with the top surface110cof the first ILD layer110.

As shown inFIG. 12, the recess etching process of the gate electrode300is performed so that the top surface of the gate electrode300is lower than the top surface110cof the first ILD layer110. According to an embodiment of the present invention, the above-described recess etching process causes the top surface of the gate electrode300to be lower than the bottom of the first silicide layer220. In addition, the upper end of the high-k dielectric layer310may be higher than the top surface of the gate electrode300. At this point, an annular recessed area633is formed on the gate electrode300.

As shown inFIG. 13, a contact etch stop layer122is then deposited, conformally covering the top surface of the first ILD layer110and the annular recessed region633. According to an embodiment of the present invention, the contact etch stop layer122is in direct contact with the first mask layer622, the conductive layer210, the first silicide layer220, the second mask layer624, and the first ILD layer110.

As shown inFIG. 13, after the contact etch stop layer122is deposited on the top surface of the first ILD layer110and the annular recessed region633, a second ILD layer120is deposited on the contact etch stop layer122, such as a silicon oxide layer, and the second ILD layer120is filled into the annular recessed region633.

As shown inFIG. 14, after the second ILD layer120is deposited on the contact etch stop layer122, a first contact hole etching process is performed, including etching the second ILD layer120, the contact etch stop layer122and the first mask layer622so as to form a first metal-on-diffusion (MD) contact hole722, which exposes the conductive layer210, and etching the second ILD layer120, the contact etch stop layer122and the second mask layer624so as to form a second MD contact hole724, which exposes the contact plug410. The first MD contact hole722and the second MD contact hole724have the same depth.

Subsequently, a second contact hole etching process is performed to etch the second ILD layer120and the contact etch stop layer122so as to form a metal-on-poly (MP) contact hole726, which exposes the top surface of the gate electrode300. The above-mentioned first and second contact hole etching processes may include a lithography process and an etching process.

As shown inFIG. 15, a first MD contact element522, a second MD contact elements524, and a MP contact element526are formed in the first MD contact hole722, the second MD contact hole724, and the MP contact hole726, respectively. The first MD contact element522is formed in the second ILD layer120and the contact etch stop layer122, and is in direct contact with the conductive layer210. The second MD contact element524is formed in the second ILD layer120, the contact etch stop layer122, and the first ILD layer110, and is in direct contact with the contact plug410. The MP contact element526is formed in the second ILD layer120and the contact etch stop layer122and directly contacts the gate electrode300.