Electronic apparatus having data retention protection and operating method thereof

An electronic apparatus includes a storage device having a plurality of memory blocks including a first memory block; and a controller configured to control the storage device to perform a read operation for the first memory block in response to a read request of a host. The controller controls the storage device to perform a refresh operation for the first memory block based on whether there is a difference value between a current pass read voltage and a previous pass read voltage which were applied to the first memory block when performing the read operation, and whether there is a difference between a current erase/write count and a previous erase/write count for the first memory block.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2018-0146727, filed on Nov. 23, 2018, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments of the present disclosure generally relate to an electronic apparatus. Particularly, the embodiments relate to an electronic apparatus including a data storage device and an operating method thereof.

2. Related Art

Recently, the paradigm for the computer environment has changed to ubiquitous computing in which computer systems can be used anytime and anywhere. As a result, the use of portable electronic appliances such as mobile phones, digital cameras, and notebook computers has rapidly increased. Such portable electronic appliances use an electronic apparatus including a data storage device, to store data.

An electronic apparatus including a data storage device provides advantages in that, since there is no mechanical driving part, stability and durability are excellent, and information access speed is high while power consumption is low. Electronic apparatuses include a universal serial bus (USB) memory device, memory cards having various interfaces, a universal flash storage (UFS) device, and a solid state drive (SSD). However, in the current state of the art, data retention characteristics of memory blocks which are included in data storage devices, can deteriorate over time which decreases the reliability and lifetime of a data storage device, and render the data storage device unusable. Therefore, a data storage device having data retention protection which increases the reliability and lifetime of the data storage device, is needed.

SUMMARY

Various embodiments are directed to an electronic apparatus capable of preventing the loss of data and an operating method thereof.

In an embodiment, an electronic apparatus may include: a storage device having a plurality of memory blocks including a first memory block; and a controller configured to control the storage device to perform a read operation for the first memory block in response to a read request of a host. The controller controls the storage device to perform a refresh operation for the first memory block based on whether there is a difference value between a current pass read voltage and a previous pass read voltage which were applied to the first memory block when performing the read operation, and whether there is a difference between a current erase/write count and a previous erase/write count for the first memory block.

In an embodiment, a memory system may include: a memory device including a memory block; and a controller configured to store a previous pass read voltage, a current erase/write count, and a previous erase/write (EW) count of the memory block; and control the memory device to perform a refresh operation to the memory block when a difference between the current pass read voltage and the previous pass read voltage is greater than a predetermined threshold and the current EW count and the previous EW count are equal.

In an embodiment, an electronic apparatus may include: a data storage device including a plurality of memory blocks; and a controller including a retention manager, and configured to control the data storage device to perform a read operation on a first memory block among the plurality of memory blocks in response to a read request from a host. The retention manager compares a pass read voltage applied to the first memory block in the current read operation with a stored previous pass read voltage applied to the first memory block during a last previous read operation to determine a voltage difference value when a current read operation is determined to be a success. The retention manager determines a current erase/write count for the first memory block and compares the current erase/write count with a stored previous erase/write count for the first memory block when the voltage difference value is greater than or equal to a preset voltage threshold value, and performs a refresh operation for the first memory block when the current erase/write count is equal to the stored previous erase/write count.

In an embodiment, a method for operating an electronic apparatus, the method may include: performing a read operation for a first memory block in response to a read request from a host; determining whether there is a difference value between a current pass read voltage and a previous pass read voltage which were applied to the first memory block by the read operation, and whether there is a difference between a current erase/write count and a previous erase/write count for the first memory block; and performing a refresh operation for the first memory block depending on a determination result.

In an embodiment, an operating method of a controller for controlling a memory device including a memory block, the operating method may include: storing a previous pass read voltage, a current erase/write count (EW), and a latest previous erase/write (EW) count of the memory block when a current read operation is performed on the memory block; and controlling the memory device to perform a refresh operation to the memory block when a difference value between a current pass read voltage and the previous pass read voltage is greater than a predetermined threshold, and the current and latest previous EW counts are equal.

In an embodiment, a method for data retention protection in an electronic apparatus, the method may include: performing a current read operation, by a data storage device having a plurality of memory blocks and controlled by a controller which includes a retention manager, in response to a read request from a host; comparing by the retention manager, a pass read voltage which is applied in the current read operation to a first memory block among the plurality of memory blocks, with a stored previous pass read voltage applied to the first memory block during a last previous read operation to determine a voltage difference value, when the current read operation is determined to be a success; determining by the retention manager, a current erase/write count for the first memory block; comparing by the retention manager, the current erase/write count with a stored previous erase/write count for the first memory block, when the voltage difference value is greater than or equal to a preset voltage threshold value; and performing a refresh operation for the first memory block, by the retention manager when the current erase/write count is equal to the stored previous erase/write count.

According to the embodiments of the disclosure, based on the difference between a previous pass read voltage and a current pass read voltage for the same memory block, it is possible to determine whether to perform a refresh operation for the same memory block and then, if necessary, perform the refresh operation. Due to this fact, it is possible to prevent the data stored in the memory block from entering into an unrecoverable state.

Moreover, if it is determined to perform a refresh operation for at least one memory block, a scan operation for checking whether to perform a refresh operation for the remaining memory blocks may be performed in a background operation, and if necessary, the refresh operation may be performed, whereby the lifetime of an electronic apparatus may be increased.

DETAILED DESCRIPTION

Various embodiments of the present invention are described below in more detail with reference to the accompanying drawings. We note, however, that the present invention may be embodied in different forms and variations, and should not be construed as being limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the present invention to those skilled in the art to which this invention pertains. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

It is noted that reference to “an embodiment,” “another embodiment” or the like does not necessarily mean only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s).

As used herein, singular forms may include the plural forms as well and vice versa, unless the context clearly indicates otherwise. The articles ‘a’ and ‘an’ as used in this application and the appended claims should generally be construed to mean ‘one or more’ unless specified otherwise or clear from context to be directed to a singular form.

Hereinafter, an electronic apparatus and an operating method thereof will be described below with reference to the accompanying drawings through various examples of embodiments.

FIG. 1is a block diagram illustrating a configuration of an electronic apparatus10in accordance with an embodiment of the disclosure. In the present embodiment, the electronic apparatus10may store data to be accessed by a host (not illustrated) such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game machine, a TV and an in-vehicle infotainment system. The electronic apparatus10may also be referred to as a memory system.

The electronic apparatus10may be manufactured as any one of various types of storage devices according to a host interface which is a transmission protocol for the host. For example, the electronic apparatus10may be configured as any one of various types of storage devices such as a solid state drive (SSD), a multimedia card in the form of an MMC, an eMMC, an RS-MMC and a micro-MMC, a secure digital card in the form of an SD, a mini-SD and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnection (PCI) card type storage device, a PCI express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card and a memory stick.

The electronic apparatus10may be manufactured as any one among various package types. For example, the electronic apparatus10may be manufactured as any one of package types such as a package-on-package (POP), a system-in-package (SIP), a system-on-chip (SOC), a multi-chip package (MCP), a chip-on-board (COB), a wafer-level fabricated package (WFP) and a wafer-level stack package (WSP).

Referring toFIG. 1, the electronic apparatus10may include a storage device100and a controller200.

The storage device100may operate as the storage medium of the electronic apparatus10. The storage device100may include a non-transitory machine-readable storage medium. The storage device100may be configured by using any one of various types of nonvolatile memory devices such as a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase change random access memory (PRAM) using a chalcogenide alloy, and a resistive random access memory (RERAM) using a transition metal compound.

FIG. 2Ais a diagram illustrating a configuration of the storage device100,FIG. 2Bis a diagram illustrating the configuration of any one among the plurality of nonvolatile memory devices NVM1to NVMi shown inFIG. 2A, andFIG. 2Cis a diagram illustrating the configuration of any one among the plurality of memory blocks BLK1to BLKj shown inFIG. 2B.

Referring toFIG. 2A, the storage device100may include a plurality of nonvolatile memory devices NVM1to NVMi. A number of channels CH (not shown) corresponding to the number of nonvolatile memory devices NVM1to NVMi included in the storage device100are coupled with the controller200. However, the embodiment is not specifically limited thereto. Furthermore, each of the nonvolatile memory devices NVM1to NVMi may be coupled with the controller200through one channel CH, but the embodiment is not specifically limited thereto.

Referring toFIGS. 2B and 2C, each nonvolatile memory device NVM may include a plurality of memory blocks BLK1to BLKj. Each memory block BLK may include a data region where data such as user data is stored, and a spare region where metadata related with the data are stored. For example, an erase/write (E/W) count may be stored in the spare region. While not specifically illustrated inFIG. 2C, each memory block BLK may include a plurality of pages.

While not specifically illustrated inFIG. 2B, each nonvolatile memory device NVM may include a memory cell array (not illustrated) which has a plurality of memory cells respectively disposed at regions where a plurality of bit lines (not illustrated) and a plurality of word lines (not illustrated) intersect with each other. Each memory cell of the memory cell array may be a single level cell (SLC) storing one bit, a multi-level cell (MLC) capable of storing 2-bit data, a triple level cell (TLC) capable of storing 3-bit data or a quadruple level cell (QLC) capable of storing 4-bit data. The memory cell array may include at least one of single level cells, multi-level cells, triple level cells and quadruple level cells. For example, the memory cell array may include memory cells of a two-dimensional horizontal structure or memory cells of a three-dimensional vertical structure.

Referring back to figureFIG. 1, the controller200may include a host interface210, a retention manager220, a processor230, a memory240and a memory interface250. The memory240may include a block state table245.

The host interface210may interface the host and the electronic apparatus10. For example, the host interface210may communicate with the host by using any one of standard transmission protocols such as universal serial bus (USB), universal flash storage (UFS), multimedia card (MMC), parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI) and PCI express (PCI-E) protocols.

The retention manager220may be driven under the control of the processor230. The retention manager220may be realized by hardware, software or a combination of hardware and software. The retention manager220may determine whether to perform a refresh operation for each of the memory blocks BLK1to BLKj of the storage device100, and may provide a determination result to the processor230.

For example, depending on whether an error correct code (ECC) decoding of data read out from a memory block read-requested from the host, is a pass or a fail, the retention manager220may determine whether to perform a refresh operation for that memory block.

If the ECC decoding of the data read out from the memory block read-requested from the host is a fail, the retention manager220may provide the processor230with a signal indicating that a refresh operation for that memory block is necessary. Based on the signal received from the retention manager220, the processor230may control the storage device100to perform a series of processes of reading out data stored in the memory block, correcting error bits of the read-out data, and storing error bit-corrected data in another memory block.

If the ECC decoding of the data read out from the memory block read-requested from the host is a pass, the retention manager220may compare a current read voltage level (hereinafter, referred to as a ‘pass read voltage’) used in reading out the data which passed the ECC decoding with a previous pass read voltage used for the same memory block, and may determine whether the difference between the read voltages is less than, equal to, or greater than a preset threshold value. If the difference between the read voltages is less than the preset threshold value, the retention manager220may determine that a refresh operation for that memory block is not necessary, and no signal is provided to the processor230.

If the difference between the read voltages is equal to or greater than the preset threshold value, the retention manager220may determine a current erase/write count for the memory block and compare the current erase/write (E/W) count for that memory block and a previous erase/write (E/W) count corresponding to the previous pass read voltage for that memory block, and may determine whether the erase/write (E/W) count has increased. If the erase/write count has increased, the retention manager220may determine that the memory block is a memory block in which new data is stored after the memory block was erased, and no signal is provided to the processor230.

Conversely, if the current erase/write count and the previous erase/write count of the corresponding memory block are equal, the retention manager220may determine that the retention characteristic of that memory block has deteriorated, and may provide the processor230with a signal indicating that a refresh operation for that memory block is necessary.

The retention manager220may provide the processor230with a signal indicating that it is necessary to perform a refresh operation for the memory block, and at the same time, may provide the processor230with a signal indicating that it is necessary to perform a retention scan operation for each of the remaining memory blocks except for the memory block which is being refreshed.

The retention scan operation for each of the remaining memory blocks may be performed as a background operation while the electronic apparatus10is in an idle state, is booted, or an operation such as garbage collection (GC) is performed in the storage device100. However, the embodiment is not specifically limited thereto.

The processor230may be configured by a micro control unit (MCU) or a central processing unit (CPU). The processor230may process a request received from the host. In order to process the request received from the host, the processor230may drive a code type instruction or algorithm, that is, software which is loaded in the memory240, and may control internal function blocks and the storage device100.

The electronic apparatus10starts a boot-up process when supplied with power or is rebooted. For example, the electronic apparatus10reads out a bootloader from a read only memory (ROM) (not illustrated), and loads the bootloader in the memory240. The electronic apparatus10may complete the boot-up process by reading out code type instructions from the storage device100and loading the code type instructions in the memory240, using the bootloader. The code type instructions loaded in the memory240may control the operations of the various function blocks in the controller200and of the storage device100.

When an ECC decoding for data read out from the storage device100in response to a read request from the host is a pass or a fail, the processor230may drive the retention manager220to determine whether to perform a refresh operation for the memory block read-requested from the host. Based on the determination result, the retention manager220may or may not perform the refresh operation for that memory block.

The memory240may be configured by a dynamic random access memory (DRAM) or a static random access memory (SRAM). The memory240may include a region in which software (that is, code type instructions) is loaded which will be driven by the processor230. Furthermore, the memory240may include a region where metadata necessary to drive the software is stored. Namely, the memory240may operate as a working memory of the processor230.

The memory240may include a region which temporarily stores data to be transmitted from the host to the storage device100, or data to be read out from the storage device100and then transmitted to the host. That is, the memory240may operate as a buffer memory, and may also be referred to as a temporary storage device.

The block state table245stored in the memory240may be configured to include state information for the respective memory blocks included in the storage device100.

FIG. 3is a diagram illustrating the block state table245.

Referring toFIG. 3, the block state table245may be configured to store a current erase/write (E/W) count, a previous pass read voltage, and a previous erase/write (E/W) count for each memory block. The current erase/write count may be increased at a time when an erase operation and a program operation for a memory block allocated as an open block (that is, a block to be used in a write operation), are performed.

The previous pass read voltage may represent a read voltage which is applied to read out data, when an ECC decoding of the data read out from a memory block is a pass during the previous read operation on the memory block. That is, the previous pass read voltage may represent the latest pass read voltage applied for the previous read operation on a memory block prior to the current read operation.

The previous erase/write (E/W) count may represent an erase/write count of the memory block at a time when the previous pass read voltage is applied. That is, the previous E/W count may indicate the E/W count at a time when the previous pass read voltage was applied (i.e., at a time of a successful previous read operation to the memory block).

The current erase/write (E/W) count, the previous pass read voltage, and the previous erase/write (E/W) count of the block state table245may be updated in real time. The updated block state table245may be backed up in the storage device100. Upon booting of the electronic apparatus10, the block state table245backed up in the storage device100may be loaded in the memory240.

The memory interface250may control the storage device100under the control of the processor230. The memory interface250may also be referred to as a memory controller. The memory interface250may provide control signals to the storage device100. The control signals may include a command for controlling the storage device100to perform an operation corresponding to a request received from the host. The command may include an operation code (for example, information on the type of the operation to be performed), address information on a region where the operation is to be performed, and so forth, but the embodiment is not specifically limited thereto. The memory interface250may provide data to the storage device100, or may be provided with data from the storage device100. The memory interface250may be coupled with the storage device100through one or more channels CH.

FIG. 4is a diagram illustrating threshold voltage distributions41to43that are changed due to deteriorations in a retention characteristic. While one threshold voltage distribution is illustrated as an example inFIG. 4, other threshold voltage distributions may be formed. Depending on which storage scheme is used, e.g., the SLC scheme, the MLC scheme, the TLC scheme or the QLC scheme, a minimum of 2 threshold voltage distributions may be formed.

After a program operation is performed for memory cells, if access to the programmed memory cells is not made for a long time, the charges stored in the programmed memory cells leak due to the lapse of time. As a result, a threshold voltage distribution may be changed as illustrated inFIG. 4.

InFIG. 4, a first threshold voltage distribution41represents an initial state in which memory cells are programmed. At this time, when a first read voltage Vr1is applied, an ECC decoding of first data read out from the memory cells will be a pass.

A second threshold voltage distribution42represents a state which is shifted towards the left due to the leakage of charges occurring during the lapse of a first amount of time and is relatively wide in its width. At this time, the number of error bits included in the first data read out by the first read voltage Vr1may be greater than the number of correctable error bits, and as a result, an ECC decoding of the first data will be a fail. Therefore, data is read out again from the memory cells by applying a changed read voltage, that is, a second read voltage Vr2. The number of error bits (corresponding to the hatched portion) included in read-out second data may be less than the number of correctable error bits, and as a result, an ECC decoding of the second data will be a pass.

A third threshold voltage distribution43represents a state which is further shifted towards the left due to the leakage of charges occurring during the lapse of a second amount of time greater than the first amount of time, and is further wider in its width. At this time, the number of error bits included in the second data read out by the second read voltage Vr2as the latest previous pass read voltage may be substantially greater than the number of correctable error bits, and as a result, an ECC decoding of the second data will be a fail. Therefore, data is read out again from the memory cells by applying a changed read voltage, that is, a third read voltage Vr3. The number of error bits (corresponding to the hatched portion) included in read-out third data may be less than the number of correctable error bits, and as a result, an ECC decoding of the third read data will be a pass.

While only the three read voltages Vr1, Vr2and V3are illustrated inFIG. 4, it will be apparent to a person skilled in the art to change a read voltage until an ECC decoding of read data is passed, or to change the read voltage a predetermined number of times and then to repeatedly read out data from memory cells by using the changed read voltage.

As illustrated inFIG. 4, it can be seen that the difference ΔV2between the second read voltage Vr2and the third read voltage Vr3is substantially greater than the difference ΔV1between the first read voltage Vr1and the second read voltage Vr2. That is, the difference between a previous pass read voltage and a current pass read voltage may represent the retention characteristic of memory cells. For example, if the difference between a previous pass read voltage and a current pass read voltage increases, it may indicate that the retention characteristic of the memory cells has deteriorated.

Thus, in the present embodiment, the retention manager220compares the difference between a previous pass read voltage and a current pass read voltage with a preset threshold value. The retention manager then determines, when the difference is equal to or greater than the preset threshold value, that the retention characteristic of a memory block has deteriorated, and provides a signal to the processor230such that a refresh operation is performed for the memory block before the retention characteristic further deteriorates. By performing a refresh operation in advance before the retention characteristic of a memory block deteriorates to such an extent that it cannot be recovered, it is possible to improve the reliability of data and increase the lifetime of the storage device100.

FIG. 5Ais a diagram illustrating a state in which a program operation for a first memory block BLK1is completed,FIG. 5Bis a diagram illustrating the block state table245in which a corresponding value is changed as the program operation for the first memory block BLK1is completed, andFIG. 5Cis a diagram illustrating the block state table245in which a corresponding value is changed when a read operation for the first memory block BLK1being in a programmed state is a pass. Furthermore, the first memory block BLK1is allocated for the first amount of time as an open block.

While not specifically illustrated inFIG. 5A, an erase operation for the first memory block BLK1which is allocated as an open block, may be performed first. However, the embodiment is not specifically limited thereto. When data corresponding to a write request from the host is stored in the data region of the first memory block BLK1which is in an erased state, an erase/write count ‘1’ may be stored in the spare region of the first memory block BLK1. At this time, as illustrated inFIG. 5B, ‘1’ is stored as a current erase/write count for the first memory block BLK1, in the block state table245.

Thereafter, if an ECC decoding of data read out from the first memory block BLK1by the first read voltage Vr1(seeFIG. 4) in response to a read request received from the host, is a pass, as illustrated inFIG. 5C, ‘Vr1’ is stored as a previous pass read voltage for the first memory block BLK1and ‘1’ is stored as a previous erase/write count, in the block state table245.

FIG. 6Ais a diagram illustrating a first charge leakage state for the first memory block BLK1after a first amount of time elapses, andFIG. 6Bis a diagram illustrating the block state table245in which a corresponding value is changed when a read operation is a pass for the first memory block BLK1being in the first charge leakage state.

If the first amount of time elapses after programming, as charges gradually leak from the memory cells of the first memory block BLK1, a state similar to the second threshold voltage distribution42illustrated inFIG. 4may result. When a read request for the first memory block BLK1is received from the host, data is read out from the first memory block BLK1by using a previous pass read voltage first. If an ECC decoding of the read-out data is a fail, data is read out again from the first memory block BLK1by changing the read voltage. For example, if an ECC decoding of data read out by the first read voltage Vr1(seeFIG. 4), which is the previous pass read voltage, is a fail and an ECC decoding of data read out by the changed second read voltage Vr2(seeFIG. 4) is a pass, as illustrated inFIG. 6B, the previous pass read voltage for the first memory block BLK1may be updated to ‘Vr2’ and a previous erase/write count may not be changed, in the block state table245.

At this time, the retention manager220may calculate the difference value between the second read voltage Vr2as the current pass read voltage and the first read voltage Vr1as the previous pass read voltage, and may determine whether the calculated difference value is less than, equal to, or greater than a preset threshold value. If the difference value is less than the threshold value, it is determined that it is not necessary to perform a refresh operation. If the difference value is equal to or greater than the threshold value, the necessity to perform a refresh operation may be determined depending on whether a current erase/write count has increased in comparison with the previous erase/write count.

FIG. 7is a diagram illustrating a second charge leakage state for the first memory block BLK1after a second amount of time elapses.

If the second amount of time, which is greater than the first amount of time, elapses after programming, as charges gradually leak from the memory cells of the first memory block BLK1, a state like the third threshold voltage distribution43illustrated inFIG. 4may result. If a read request for the first memory block BLK1is received from the host, data is read out from the first memory block BLK1by using a previous pass read voltage first. If an ECC decoding of the read-out data is a fail, data is read out again from the first memory block BLK1by changing the read voltage. For example, if an ECC decoding of the read data read out by the second read voltage Vr2as the previous pass read voltage is a fail and an ECC decoding of the read data read out by the changed third read voltage Vr3(seeFIG. 4) is a pass, the previous pass read voltage for the first memory block BLK1may be updated to ‘Vr3’ in the block state table245.

The retention manager220may calculate the difference value between the third read voltage Vr3as the current pass read voltage and the second read voltage Vr2as the previous pass read voltage, and may determine whether the calculated difference value is less than, equal to, or greater than a preset threshold value. If the difference value is less than the threshold value, it is determined that it is not necessary to perform a refresh operation. If the difference value is equal to or greater than the threshold value, the necessity to perform a refresh operation may be determined depending on whether a current erase/write count has increased in comparison with a previous erase/write count.

For example, since the current erase/write count is the same as the previous erase/write count inFIG. 7, the retention manager220may determine that it is necessary to perform a refresh operation.

FIG. 8Ais a diagram illustrating an invalidated state of the data stored in the first memory block BLK1,FIG. 8Bis a diagram illustrating a state when a program operation is completed after an erase operation for the reallocated first memory block BLK1, andFIG. 8Cis a diagram illustrating the block state table245in which a corresponding value is changed as the program operation for the reallocated first memory block BLK1is completed.

If a write request including logical addresses corresponding to data stored in the first memory block BLK1is received from the host, the data is stored in another memory block other than the first memory block BLK1, and the data already stored in the first memory block BLK1becomes invalid data as illustrated inFIG. 8A. The first memory block BLK1including the invalid data may be classified as a ‘free block’ indicating that the block is a usable block.

FIG. 8Billustrates a state in which the first memory block BLK1classified as a free block is programmed after being reallocated as an open block. While not specifically illustrated inFIG. 8B, the reallocated first memory block BLK1may be programmed after it becomes an erased state by an erase operation. Since the erase operation and the program operation have been performed sequentially for the first memory block BLK1, as illustrated inFIG. 8C, a current erase/write count for the first memory block BLK1is updated to ‘2’ in the block state table245.

FIG. 9is a diagram illustrating a second charge leakage state for the reallocated first memory block BLK1after a second amount of time elapses.

If the second amount of time elapses after programming, the memory cells of the first memory block BLK1may have a state like the third threshold voltage distribution43illustrated inFIG. 4. An ECC decoding of data read out by the second read voltage Vr2as a previous pass read voltage, in response to a read request for the first memory block BLK1received from the host, may be a fail, and an ECC decoding of data read out by the changed third read voltage Vr3(seeFIG. 4) may be a pass.

The retention manager220may calculate the difference value between the third read voltage Vr3as the current pass read voltage and the second read voltage Vr2as the previous pass read voltage, and may determine whether the calculated difference value is less than, equal to, or greater than a preset threshold value. If the difference value is less than the threshold value, it is determined that it is not necessary to perform a refresh operation. If the difference value is equal to or greater than the threshold value, the necessity to perform a refresh operation may be determined depending on whether a current erase/write count has increased in comparison with a previous erase/write count.

For example, since the current erase/write count is increased in comparison with the previous erase/write count inFIG. 9, the retention manager220may determine that it is not necessary to perform a refresh operation. Since the increase in erase/write count means that data is newly stored in the corresponding memory block, it is determined that a change in read voltage is not due to a deterioration in a retention characteristic.

FIG. 10is a flow chart of a method for operating an electronic apparatus in accordance with an embodiment of the disclosure. In describing the method for operating the electronic apparatus10in accordance with the present embodiment with reference toFIG. 10, reference may also be made to at least one amongFIGS. 1 to 9.

At step S1001, a read request may be received from the host. The read request received from the host is a read request for the first memory block BLK1(seeFIG. 2B).

At step S1003, the processor230of the controller200may control the operation of the storage device100to perform a read operation for the first memory block BLK1, in response to the read request from the host. The storage device100may read out data from the first memory block BLK1and transmit the read-out data to the controller200, under the control of the processor230.

At step S1005, the processor230may perform an ECC decoding for the read data received from the storage device100, by using an ECC (error correction code) engine (not illustrated). The ECC engine may provide the processor230with a signal indicating whether the ECC decoding for the read data is a pass (that is, a success) or a fail (that is, a failure). The processor230may determine whether the ECC decoding of the read data is a success, based on the signal provided from the ECC engine. If the ECC decoding of the read data is a success (that is, ‘Yes’ at step S1005), the process may proceed to step S1011. Conversely, if the ECC decoding of the read data is a failure (that is, ‘No’ at step S1005), the process may proceed to step S1007.

At the step S1007, the processor230may determine whether a read operation count for the first memory block BLK1is equal to or greater than a threshold count. If the read operation count is equal to or greater than the threshold count (that is, ‘Yes’ at step S1007), the process may proceed to step S1017. If the read operation count is less than the threshold count (that is, ‘No’ at step S1007), the process may proceed to step S1009.

At the step S1009, the storage device100may change a read voltage under the control of the processor230, may read out data again from the first memory block BLK1by applying the changed read voltage to the first memory block BLK1, and may provide the processor230with the data read out again.

At the step S1011, the processor230may drive the retention manager220to calculate the difference value between a current pass read voltage and a previous pass read voltage for the first memory block BLK1.

At step S1013, the retention manager220may compare the difference value calculated at the step S1011and a preset threshold value, and may determine whether the difference value is equal to or greater than the threshold value. If the difference value is less than the threshold value (that is, ‘No’ at step S1013), the read operation for the first memory block BLK1may end. If the difference value is equal to or greater than the threshold value that is, ‘Yes’ at step S1013), the process may proceed to step S1015.

At the step S1015, the retention manager220may determine whether a current erase/write count and a previous erase/write count for the first memory block BLK1are equal, by referring to the block state table245. If the current erase/write count and the previous erase/write count are not equal (that is, ‘No’ at step S1015), the read operation for the first memory block BLK1may end. If the current erase/write count and the previous erase/write count are equal (that is, ‘Yes’ at step S1015), the process may proceed to the step S1017.

At the step S1017, the retention manager220determines that it is necessary to perform a refresh operation for the first memory block BLK1, and provides the processor230with a signal indicating a determination result. Also, the retention manager220determines that it is necessary to scan retention states for all of the remaining memory blocks except the first memory block BLK1, and provides the processor230with a signal indicating a determination result.

The processor230may control the operation of the storage device100to perform a refresh operation for the first memory block BLK1, based on the signals provided from the retention manager220. Moreover, the processor230may control the operation of the storage device100to perform a retention state scan operation for the remaining memory blocks, while the electronic apparatus10is in an idle state, is booted, or garbage collection (GC) is performed in the storage device100.

FIG. 11is a diagram illustrating a data processing system including a solid state drive (SSD) in accordance with an embodiment of the present disclosure. Referring toFIG. 11, the data processing system2000may include a host apparatus2100and the SSD2200.

The SSD2200may include a controller2210, a buffer memory device2220, nonvolatile memory devices2231to223n,a power supply2240, a signal connector2250, and a power connector2260.

The controller2210may control overall operation of the SSD2220.

The buffer memory device2220may temporarily store data in the nonvolatile memory devices2231to223n.The buffer memory device2220may temporarily store data read from the nonvolatile memory devices2231to223n.The data temporarily stored in the buffer memory device2220may be transmitted to the host apparatus2100or to the nonvolatile memory devices2231to223naccording to control of the controller2210.

The nonvolatile memory devices2231to223nmay be used as a storage medium of the SSD2200. The nonvolatile memory devices2231to223nmay be coupled to the controller2210through a plurality of channels CH1to CHn. One or more nonvolatile memory devices may be coupled to one channel. The nonvolatile memory devices coupled to the same channel may be coupled to the same signal bus and the same data bus.

The power supply2240may provide power PWR input through the power connector2260to components within the SSD2200. The power supply2240may include an auxiliary power supply2241. The auxiliary power supply2241may supply the power so that the SSD2200is properly terminated even when sudden power-off occurs. The auxiliary power supply2241may include large capacity capacitors capable of charging the power PWR.

The controller2210may exchange a signal SGL with the host apparatus2100through the signal connector2250. The signal SGL may include a command, an address, data, and other related information such as metadata, count values, and command priority data. The signal connector2250may be configured as any of various types of connectors according to an interfacing method between the host apparatus2100and the SSD2200.

FIG. 12is a diagram illustrating a controller, such as that illustrated inFIG. 11, in accordance with an embodiment of the present disclosure. Referring toFIG. 12, the controller2210may include a host interface2211, a control component2212, a random access memory (RAM)2213, an error correction code (ECC) component2214, and a memory interface2215.

The host interface2211may perform interfacing between the host apparatus2100and the SSD2200according to a protocol of the host apparatus2100. For example, the host interface2211may communicate with the host apparatus2100through any one among a secure digital protocol, a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, an embedded MMC (eMMC) protocol, a personal computer memory card international association (PCMCIA) protocol, a parallel advanced technology attachment (PATA) protocol, a serial advanced technology attachment (SATA) protocol, a small computer system interface (SCSI) protocol, a serial attached SCSI (SAS) protocol, a peripheral component interconnection (PCI) protocol, a PCI Express (PCI-e or PCIe) protocol, and a universal flash storage (UFS) protocol. The host interface2211may perform a disc emulation function such that the host apparatus2100recognizes the SSD2200as a general-purpose data storage apparatus, for example, a hard disc drive HDD.

The control component2212may analyze and process the signal SGL input from the host apparatus2100. The control component2212may control operations of internal functional blocks according to firmware and/or software for driving the SDD2200. The RAM2213may be operated as a working memory for driving the firmware or software.

The ECC component2214may generate parity data for the data to be transferred to the nonvolatile memory devices2231to223n.The generated parity data may be stored in the nonvolatile memory devices2231to223ntogether with the data. The ECC component2214may detect errors for data read from the nonvolatile memory devices2231to223nbased on the parity data. When detected errors are within a correctable range, the ECC component2214may correct the detected errors.

The memory interface2215may provide a control signal such as a command and an address to the nonvolatile memory devices2231to223naccording to control of the control component2212. The memory interface2215may exchange data with the nonvolatile memory devices2231to223naccording to control of the control component2212. For example, the memory interface2215may provide data stored in the buffer memory device2220to the nonvolatile memory devices2231to223nor provide data read from the nonvolatile memory devices2231to223nto the buffer memory device2220.

FIG. 13is a diagram illustrating a data processing system including an electronic apparatus in accordance with an embodiment. Referring toFIG. 13, the data processing system3000may include a host apparatus3100and the data storage apparatus3200.

The host apparatus3100may be configured in a board form such as a printed circuit board (PCB). Although not shown inFIG. 13, the host apparatus3100may include internal functional blocks configured to perform functions of the host apparatus3100.

The host apparatus3100may include a connection terminal3110such as a socket, a slot, or a connector. The data storage apparatus3200may be mounted on the connection terminal3110.

The data storage apparatus3200may be configured in a board form such as a PCB. The data storage apparatus3200may refer to a memory module or a memory card. The data storage apparatus3200may include a controller3210, a buffer memory device3220, nonvolatile memory devices3231to3232, a power management integrated circuit (PMIC)3240, and a connection terminal3250.

The controller3210may control overall operation of the data storage apparatus3200. The controller3210may be configured the same or substantially the same as the controller2210illustrated inFIG. 12.

The buffer memory device3220may temporarily store data in the nonvolatile memory devices3231and3232. The buffer memory device3220may temporarily store data read from the nonvolatile memory devices3231and3232. The data temporarily stored in the buffer memory device3220may be transmitted to the host apparatus3100or the nonvolatile memory devices3231and3232, according to control of the controller3210.

The nonvolatile memory devices3231and3232may be used as a storage medium of the data storage apparatus3200.

The PMIC3240may provide power input through the connection terminal3250to components within the data storage apparatus3200. The PMIC3240may manage the power of the data storage apparatus3200according to control of the controller3210.

The connection terminal3250may be coupled to the connection terminal3110of the host apparatus3100. Power and a signal such as a command, an address, and data may be transmitted between the host apparatus3100and the data storage apparatus3200through the connection terminal3250. The connection terminal3250may be configured in any of various forms according to an interfacing method between the host apparatus3100and the data storage apparatus3200. The connection terminal3250may be arranged in or on any side of the data storage apparatus3200.

FIG. 14is a diagram illustrating a data processing system including an electronic apparatus in accordance with an embodiment. Referring toFIG. 14, the data processing system4000may include a host apparatus4100and the data storage apparatus4200.

The host apparatus4100may be configured in a board form such as a printed circuit board (PCB). Although not shown inFIG. 14, the host apparatus4100may include internal functional blocks configured to perform functions of the host apparatus4100.

The data storage apparatus4200may be configured in a surface mounting packaging form. The data storage apparatus4200may be mounted on the host apparatus4100through a solder ball4250. The data storage apparatus4200may include a controller4210, a buffer memory device4220, and a nonvolatile memory device4230.

The controller4210may control overall operation of the data storage apparatus4200. The controller4210may be configured the same or substantially the same as the controller2210illustrated inFIG. 12.

The buffer memory device4220may temporarily store data in the nonvolatile memory device4230. The buffer memory device4220may temporarily store data read from the nonvolatile memory device4230. The data temporarily stored in the buffer memory device4220may be transmitted to the host apparatus4100or the nonvolatile memory device4230through control of the controller4210.

The nonvolatile memory device4230may be used as a storage medium of the data storage apparatus4200.

FIG. 15is a diagram illustrating a network system5000including a data storage apparatus in accordance with an embodiment. Referring toFIG. 15, the network system5000may include a server system5300and a plurality of client systems5410to5430which are coupled through a network5500.

The server system5300may serve data in response to requests from the plurality of client systems5410to5430. For example, the server system5300may store data provided from the plurality of client systems5410to5430. In another example, the server system5300may provide data to the plurality of client systems5410to5430.

The server system5300may include a host apparatus5100and a data storage apparatus5200. The data storage apparatus5200may include the electronic apparatus10ofFIG. 1, the data storage apparatus2200ofFIG. 11, the data storage apparatus3200ofFIG. 13, or the data storage apparatus4200ofFIG. 14.

FIG. 16is a block diagram illustrating a nonvolatile memory device included in a storage device of an electronic apparatus in accordance with an embodiment. Referring toFIG. 16, the nonvolatile memory device100may include a memory cell array110, a row decoder120, a column decoder140, a data read/write block130, a voltage generator150, and a control logic160.

The memory cell array110may include memory cells MC arranged in regions in which word lines WL1to WLm and bit lines BL1to BLn cross to each other.

The row decoder120may be coupled to the memory cell array110through the word lines WL1to WLm. The row decoder120may operate through control of the control logic160. The row decoder120may decode an address provided from an external apparatus (not shown). The row decoder120may select and drive the word lines WL1to WLm based on a decoding result. For example, the row decoder120may provide a word line voltage provided from the voltage generator150to the word lines WL1to WLm.

The data read/write block130may be coupled to the memory cell array110through the bit lines BL1to BLn. The data read/write block130may include read/write circuits RW1to RWn corresponding to the bit lines BL1to BLn. The data read/write block130may operate according to control of the control logic160. The data read/write block130may operate as a write driver or a sense amplifier according to an operation mode. For example, the data read/write block130may operate as the write driver configured to store data provided from an external apparatus in the memory cell array110in a write operation. In another example, the data read/write block130may operate as the sense amplifier configured to read data from the memory cell array110in a read operation.

The column decoder140may operate though control of the control logic160. The column decoder140may decode an address provided from an external apparatus (not shown). The column decoder140may couple the read/write circuits RW1to RWn of the data read/write block130corresponding to the bit lines BL1to BLn, and data input/output (I/O) lines (or data I/O buffers) based on a decoding result.

The voltage generator150may generate voltages used for an internal operation of the nonvolatile memory device100. The voltages generated through the voltage generator150may be applied to the memory cells of the memory cell array110. For example, a program voltage generated in a program operation may be applied to word lines of memory cells in which the program operation is to be performed. In another example, an erase voltage generated in an erase operation may be applied to well regions of memory cells in which the erase operation is to be performed. In another example, a read voltage generated in a read operation may be applied to word lines of memory cells in which the read operation is to be performed.

The control logic160may control overall operation of the nonvolatile memory device100based on a control signal provided from an external apparatus. For example, the control logic160may control an operation of the nonvolatile memory device100such as a read operation, a write operation, and an erase operation of the nonvolatile memory device100.

While various embodiments have been described above, it will be understood to those skilled in the art that various changes and modifications may be made to the described embodiments without departing from the spirit and scope of the invention as defined in the following claims.