Circuit and method for digital delay and circuits incorporating the same

A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the first signal and the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal based on the at least one selected version of the second signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.

TECHNICAL FIELD

This disclosure is generally directed to digital circuits and more specifically to a circuit and method for digital delay and circuits incorporating the same.

BACKGROUND

Many types of circuits often need to delay digital signals in order to operate properly. For example, duty cycle correction circuits often delay one or more digital signals in order to produce a clock signal having a duty cycle of approximately fifty percent. This may be useful in various applications, such as in synchronous dynamic random access memories (SDRAMs) and delay locked loops (DLLs), where both rising and falling edges of a clock signal are used.

Conventional circuits that delay digital signals often suffer from various problems. For example, the accuracy of conventional duty cycle correction circuits is often proportional to the “lock time” needed to reach the appropriate duty cycle. Higher accuracy typically requires longer lock times, and shorter lock times typically require lower accuracy. Also, conventional circuits that delay digital signals often suffer from process, voltage, and temperature (PVT) variations. Because of this, the behaviour of the conventional circuits typically varies based on changes or variations in manufacturing processes, operating voltages, and operating temperatures.

DETAILED DESCRIPTION

FIGS. 1 through 19, discussed below, and the various embodiments described in this patent document are by way of illustration only and should not be construed in any way to limit the scope of this disclosure. Those skilled in the art will understand that the principles described in this disclosure may be implemented in any suitably arranged device or system.

In general,FIGS. 1 through 19illustrate various circuits and methods that delay digital signals. The circuits and methods operate by dynamically adjusting an amount of time that one or more digital signals are delayed. This functionality is useful in a wide variety of applications. For example, as shown in the following figures, digital delay may be used in duty cycle correction circuits to accurately produce clock signals having a duty cycle of approximately fifty percent. Digital delay may also be used in clock frequency multiplier circuits to accurately multiply the frequency of clock signals. In addition, digital delay may be used in digital multiphase oscillator circuits to produce multiple clock signals having accurate phase differences.

FIGS. 1 through 3illustrate a first example duty cycle correction circuit according to one embodiment of this disclosure. In particular,FIG. 1illustrates a duty cycle correction circuit100, andFIGS. 2 and 3illustrate example operations of the duty cycle correction circuit100.

As shown inFIG. 1, the duty cycle correction circuit100includes two delay lines102–104, three multiplexors106–110, an XOR gate112, three registers114–118, and an N-bit up-down counter120.

Each of the delay lines102–104receives an input signal and produces multiple delayed versions of the input signal. For example, the delay line102receives a clock signal CK1and produces multiple delayed versions of the clock signal CK1, which are delayed by different amounts and provided at different tap points in the delay line102. The delay line104receives a clock signal CLK and produces multiple delayed versions of the clock signal CLK, which are delayed by different amounts and provided at different tap points in the delay line104. Each of the delay lines102–104represents any suitable structure for producing multiple delayed versions of an input signal. In this example, each of the delay lines102–104is formed from multiple delay cells122, and a tap point exists after each delay cell122. Each delay cell122could represent one or more buffers, inverters, or other structures capable of delaying a signal. In some embodiments, the delay lines102–104represent coarse delay lines, where each delay cell122provides a relatively larger amount of delay (such as when each delay cell122is formed from sixteen buffers or inverters). In particular embodiments, the delay lines102–104are identical to one another. “Tap points” generally represent points in a delay line where signals delayed by different amounts are provided.

Each of the multiplexors106–110receives multiple input signals and a control signal and selects one of the input signals for output based on the control signal. For example, the multiplexor106may receive 2Ninput signals from tap points in the delay line102and select one signal for output based on an N-bit control signal. The multiplexor108may receive 2Nsignals from tap points in the delay line104and select one signal for output based on an N-bit control signal. The multiplexor110may receive 2Nsignals (the clock signal CLK and 2N-1 delayed versions of the clock signal CLK from tap points in the delay line104) and select one signal for output based on an N-bit control signal. The value N may represent the number of bits in a signal produced by the N-bit up-down counter120. Each of the multiplexors106–110represents any suitable structure for receiving multiple signals and outputting a selected one of the signals.

The XOR gate112receives two input signals and performs logical XOR operations. In this example, the XOR gate112receives the clock signal CK1output by the register114and a clock signal CK2output by the multiplexor106. The XOR gate112produces the clock signal CLK, which is output by the duty cycle correction circuit100. The XOR gate112represents any suitable structure capable of performing logical XOR operations.

Each of the registers114–118samples an input signal and outputs the sampled value. For example, the register116receives and samples a signal CLKB from the multiplexor108to produce a signal incb. The register118receives and samples a signal CLKBP from the multiplexor110to produce a signal dec. The register114receives and samples its own inverted output signal and is clocked by the input clock signal CK, thereby producing the clock signal CK1. Each of the registers114–118represents any suitable structure for sampling an input signal. The registers114–118could, for example, represent D flip-flops.

The N-bit up-down counter120represents a counter capable of incrementing and decrementing an N-bit counter value, where the counter value is output as an N-bit control signal cnt1c. For example, the counter120may use the signals incb and dec from the registers116–118to determine whether to increment the counter value, decrement the counter value, or leave the counter value unchanged. As a particular example, the counter120could implement the following logic:if (˜incb & dec) then cnt1c=cnt1celse if (incb) then cnt1c=cnt1c−1else if (˜dec) then cnt1c=cnt1c+1else cnt1c=cnt1c
where “&” represents a logical AND operation and “˜” represents a logical NOT operation. The counter120represents any suitable structure capable of incrementing and decrementing a counter value.

In one aspect of operation, the duty cycle correction circuit100adjusts the output of the multiplexors106–110so that the output clock signal CLK achieves a duty cycle of approximately fifty percent. Various components shown inFIG. 1are used as a locking mechanism to achieve a duty cycle of approximately fifty percent in the output clock signal CLK. The locking mechanism could, for example, include the registers116–118and the counter120. Among other things, the locking mechanism generates the control signal cnt1c, and the control signal cnt1ccontrols which signals are output by the multiplexors106–110. By adjusting the operation of the multiplexors106–110, the locking mechanism controls the amount of delay provided by the delay lines102–104. Selecting an appropriate delay allows the duty cycle correction circuit100to generate an output clock signal CLK having a duty cycle of approximately fifty percent.

Example operations of the duty cycle correction circuit100are shown inFIGS. 2 and 3. InFIG. 2, “Delay1” corresponds to the delay provided by the delay line102at the tap point selected by the multiplexor106, “Delay2A” corresponds to the delay provided by the delay line104at the tap point selected by the multiplexor108, and “Delay2B” corresponds to the delay provided by the delay line104at the tap point selected by the multiplexor110. In this example, Delay1and Delay2A are approximately equal, and Delay2B is shorter than Delay1and Delay2A by an amount equal to the delay associated with one delay cell122.

As shown inFIG. 2, the duty cycle correction circuit100generally operates to divide a period T of the input clock signal CK in half. The period T of the input clock signal CK could, for example, represent the time period between two rising edges in the input clock signal CK. The counter120increments or decrements the counter value forming the control signal cnt1cuntil the end of period T occurs within a range defined by (i) the combined value of Delay1and Delay2A and (ii) the combined value of Delay1and Delay2B. As a particular example, the counter value may be adjusted until a rising edge in the clock signal CLK occurs between rising edges in the clock signals CLKB and CLKBP. At this point, the counter value of the counter120is associated with particular tap points in the delay lines102–104, and the particular tap points can be used to generate a clock signal CLK having a duty cycle of approximately fifty percent.

As shown inFIG. 3, the input clock signal CK received by the duty cycle correction circuit100may represent an asymmetric clock signal. The register114effectively divides the frequency of the clock signal CK by two and produces the clock signal CK1, which has a duty cycle of approximately fifty percent. The delay line102and the multiplexor106provide a delayed version of the clock signal CK1as clock signal CK2to the XOR gate112. The XOR gate112produces the clock signal CLK using clock signals CK1and CK2. As shown inFIG. 3, the duty cycle of the clock signal CLK may generally increase due to the counter120varying its counter value. Eventually, the clock signal CLK reaches a duty cycle of approximately fifty percent.

The fifty percent duty cycle is achieved by the counter120varying its counter value to satisfy the condition shown inFIG. 2. The multiplexor108provides a delayed version of the clock signal CLK as clock signal CLKB to the register116, and the multiplexor110provides a delayed version of the clock signal CLK as clock signal CLKBP to the register118. As shown inFIG. 3, the clock signal CLKBP leads the clock signal CLKB (by one delay cell delay). The CLKB and CLKBP signals are used by the registers116–118to produce the incb and dec signals, which are used by the counter120to increment or decrement its counter value.

In this example, the pulses in the clock signals CLK, CLKB, and CLKBP shown inFIG. 3generally widen as the counter120adjusts its counter value. At a lock time, a rising edge in the clock signal CLK occurs at or between a rising edge in the clock signal CLKB and a rising edge in the clock signal CLKBP. This condition could be indicated, for example, by the signal incb having a high value and the signal dec having a low value. At this point, the clock signal CLK has a duty cycle of approximately fifty percent, even though the clock signal CK is asymmetric and even though the delay lines102–104may suffer from process, voltage, and temperature (PVT) variations. In some embodiments, the multiplexors106–110initially output the signals received at their “0” inputs, and the multiplexors106–110output different signals as the value provided by the counter120changes.

FIGS. 4 and 5illustrate a second example duty cycle correction circuit according to one embodiment of this disclosure. In particular,FIG. 4illustrates a duty cycle correction circuit400, andFIG. 5illustrates example operations of the duty cycle correction circuit400.

As shown inFIG. 4, the duty cycle correction circuit400includes four delay lines402–408, three multiplexors410–414, an XOR gate416, three registers418–422, and an M-bit up-down counter424. In this example embodiment, the delay lines402and406represent offset delay lines, and the delay lines404and408represent fine delay lines. The offset delay lines402and406represent delay lines each capable of providing a known and relatively fixed amount of delay, although the amount of delay may be subject to PVT or other variations. The fine delay lines404and408represent delay lines formed from delay cells capable of providing a relatively smaller amount of delay (such as when each delay cell is formed from one or several buffers or inverters). In some embodiments, the delay lines402and406are identical to one another, and the delay lines404and408are identical to one another.

The duty cycle correction circuit100ofFIG. 1uses coarse tuning (delay cells with larger delay increments) to identify the appropriate tap points for the delay lines102–104. The duty cycle correction circuit400ofFIG. 4uses a combination of (i) relatively fixed delays provided by the offset delay lines402and406and (ii) fine tuning (delay cells with smaller delay increments in the delay lines404and408) to identify the appropriate tap points for the delay lines402–408. This may be useful, for example, when the offset delay lines402and406can provide delays that are generally close to the delays needed to produce a clock signal CLK with a duty cycle of approximately fifty percent. The fine delay lines404and408may then be used to compensate for PVT variations and to provide whatever additional delays are needed to produce a clock signal CLK with a duty cycle of approximately fifty percent. As a particular example, this may be useful when the frequency of an input clock signal CK and PVT variations can be known or estimated ahead of time.

As shown inFIG. 4, the delay lines402–404are used to produce the delayed version of the clock signal CK1provided to the XOR gate416(as clock signal CK3). The delay lines406–408are used to produce the clock signals CLKB and CLKBP, which the registers420–422use to generate signals incb and dec. The multiplexors410–414are each capable of receiving 2Minput signals and an M-bit control signal, where M represents the number of bits used by the counter424. The counter424generates an M-bit control signal cnt1f, which controls the operation of the multiplexors410–414and allows fine tuning using the delay lines404and408. In some embodiments, the multiplexors410–414initially output the signals received at their “0” inputs, and the multiplexors410–414output different signals as the value provided by the counter424changes. As a particular example, the counter424could implement the following logic:if (˜incb & dec) then cnt1f=cnt1felse if (incb) then cnt1f=cnt1f−1else if (˜dec) then cnt1f=cnt1f+1else cnt1f=cnt1f.

Various components shown inFIG. 4implement the same type of locking mechanism described above with respect toFIG. 1. The locking mechanism could, for example, include the registers420–422and the counter424. Among other things, the locking mechanism generates the control signal cnt1f, which adjusts the operation of the multiplexors410–414to achieve a duty cycle of approximately fifty percent in the output clock signal CLK.

The duty cycle correction circuit400shown inFIG. 4may provide a relatively fast lock time while remaining relatively accurate. In this example, the output clock signal CLK may be generated initially with a duty cycle relatively close to fifty percent. This is due to the delays provided by the offset delay lines402and406. The output clock signal CLK then moves relatively quickly to a duty cycle of approximately fifty percent using the fine delay lines404and408.

Example operations of the duty cycle correction circuit400are shown inFIG. 5. InFIG. 5, “D1” corresponds to the delay provided by the delay line402, “D2” corresponds to the delay provided by the delay line404at the tap point selected by the multiplexor410, and “D3” corresponds to the delay provided by the delay line406. Also, “D4A” corresponds to the delay provided by the delay line408at the tap point selected by the multiplexor412, and “D4B” corresponds to the delay provided by the delay line408at the tap point selected by the multiplexor414. In this example, D1and D3are approximately equal, D2and D4A are approximately equal, and D4B is shorter than D2and D4A by an amount equal to the delay associated with one delay cell in the delay line408.

As shown inFIG. 5, the counter424increments or decrements the counter value forming the control signal cnt1funtil the end of period T occurs within a range defined by (i) the combined value of D1, D2, D3, and D4A and (ii) the combined value of D1, D2, D3, and D4B. In this example, however, the delay provided by the offset delay lines402and406in the duty cycle correction circuit400may vary (such as PVT variations). Delays502include longer delays D1and D3, meaning the offset delay lines402and406provide longer delays. As a result, the delays D2, D4A, and D4B associated with the fine delay lines404and408are shorter. Delays504include shorter delays D1and D3, meaning the offset delay lines402and406provide shorter delays. Because of this, the delays D2, D4A, and D4B associated with the fine delay lines404and408are longer.

FIGS. 6 and 7illustrate an alternate embodiment of the second example duty cycle correction circuit according to one embodiment of this disclosure. In particular,FIG. 6illustrates a duty cycle correction circuit600, andFIG. 7illustrates example operations of the duty cycle correction circuit600.

The duty cycle correction circuit600ofFIG. 6is similar to the duty cycle correction circuit400ofFIG. 4. The duty cycle correction circuit600ofFIG. 6is different because it uses a different locking mechanism to achieve an output clock signal CLK having a duty cycle of approximately fifty percent. In this example, the duty cycle correction circuit600includes a register620in place of the register420and a counter624in place of the counter424, and the duty cycle correction circuit600omits the multiplexor414and the register422. The register620uses the clock signal CLKB to produce a signal det1. The counter624uses the signal det1to determine whether to vary a counter value provided as the control signal cnt1f. As a particular example, the counter624could implement the following logic:if (˜f_lock & det1) then cnt1f={1′b0, cnt1f}else if (˜f_lock & ˜det1) then cnt1f=cnt1f+1else cnt1f=cnt1f
where “cnt1f={1′b0, cnt1f}” represents a binary shift right one position operation, “{ }” represents a concatenation operation, and f_lock represents a signal produced by a control signal blocker650.

The control signal blocker650blocks the control signal cnt1ffrom reaching the multiplexor410. In this example, the control signal blocker650includes a finite state machine652and a multiplexor654. The finite state machine652uses the signal det1to produce the signal f_lock, which controls the multiplexor654. Based on the signal f_lock, the multiplexor654outputs either a low logic value or the control signal cnt1fas a control signal cnt2f, which controls the multiplexor410. The signal f_lock is also used by the counter624as shown above. In this example, the finite state machine652includes an OR gate and a register formed from a D flip-flop with reset.

Example operations of the duty cycle correction circuit600are shown inFIG. 7. InFIG. 7, “D1”–“D4” correspond to the delays provided by the delay lines402–408, respectively. In this example, D1and D3are approximately equal, and D2and D4are approximately equal after locking.

Initially, the signal det1is low, and the finite state machine652outputs a low logic value to the multiplexor654. This causes the multiplexor654to output a low logic value to the multiplexor410. As a result, the multiplexor410outputs the signal received at its “0” input as the signal CK3, where the signal CK3has been delayed by a single delay cell in the delay line404(denoted “D2=1” inFIG. 7). The counter624may then adjust the counter value forming the signal cnt1f. The signal cnt1fis provided to the multiplexor412, which outputs signals from different tap points in the delay line408. The signal cnt1fis not provided to the multiplexor410by virtue of the multiplexor654.

Eventually, the signal cnt1fidentifies the amount of delay in the delay line408needed to produce an output clock signal CLK having a duty cycle of approximately fifty percent. The various delays D1–D4at this point are identified as delays702in shown inFIG. 7. D4is shown as being variable since its actual value may depend on various factors, such as PVT variations in the duty cycle correction circuit600.

When the needed amount of delay in the delay line408is identified, the signal det1goes high. This may occur, for example, when a rising edge in the clock signal CLKB occurs during a falling edge of the clock signal CLK. This causes the counter624to divide its current counter value in half (a right shift by one operation). It also causes the finite state machine654to output a high signal f_lock to the multiplexor654, allowing the counter624to provide the divided counter value to both of the multiplexors410–412. The high signal f_lock then causes the counter624to maintain the divided counter value as an output. In effect, the counter624identifies the needed amount of delay using the delay line408, and the counter624then divides this amount of delay equally between the delay lines404and408. As represented by the delays704inFIG. 7, the delay lines402–404and the delay lines406–408should therefore provide a relatively equal amount of delay.

FIG. 8illustrates a third example duty cycle correction circuit800according to one embodiment of this disclosure. As shown inFIG. 8, the duty cycle correction circuit800represents a combination of several previous duty cycle correction circuits. In this example, the duty cycle correction circuit800includes four delay lines802–808, six multiplexors810–820, an XOR gate822, five registers824–832, an N-bit up-down counter834, an M-bit up-down counter836, and a mutual exclusion lock generator838. The delay lines802and806represent coarse delay lines, and the delay lines804and808represent fine delay lines. In particular embodiments, the delay lines802and806are identical to one another, and the delay lines804and808are identical to one another.

The duty cycle correction circuit800ofFIG. 8uses both coarse tuning (delay cells with larger delay increments) and fine tuning (delay cells with smaller delay increments) to identify the appropriate tap points for the delay lines802–808. In some embodiments, coarse tuning is performed using the delay lines802and806, and tap points in the delay lines802and806are selected. After that, fine tuning is performed using the delay lines804and808, and tap points in the delay lines804and808are selected. The selected tap points may then be used to generate an output clock signal CLK having a duty cycle of approximately fifty percent. This may be useful, for example, when offset delay lines cannot be used because the fixed amount of delay is not known ahead of time.

As shown inFIG. 8, the delay lines802–804are used to produce the delayed version of the clock signal CK1provided to the XOR gate822(as clock signal CK3). The registers826–828operate to produce signals c_incb and c_dec, which are provided to the counter834. The delay lines806–808are used to delay the output clock signal CLK produced by the XOR gate822. Outputs of the multiplexors818–820are provided, via two AND gates840–842, to the registers830–832. The registers830–832operate to produce signals f_incb and f_dec, which are provided to the counter836.

The mutual exclusion lock generator838generates a lock signal c_lock. The mutual exclusion lock generator838helps to ensure that fine tuning (using the delay lines804and808) does not occur during coarse tuning (using the delay lines802and806). In this example, the mutual exclusion lock generator838includes an AND gate with one inverted input, an OR gate, and a register formed from a D flip-flop with reset. The mutual exclusion lock generator838uses the signals c_incb and c_dec to determine when coarse tuning of the duty cycle correction circuit800is complete. The signal c_lock prevents fine tuning of the duty cycle correction circuit800until coarse tuning is complete. Once coarse tuning is complete, the mutual exclusion lock generator838alters the signal c_lock to allow fine tuning of the duty cycle correction circuit800. As a particular example, when coarse tuning is occurring, the signal c_lock may prevent the counter836from changing the value of the control signal cnt1fand prevent the registers830–832from outputting non-zero values in signals f_incb and f_dec (via the AND gates840–842).

As with the previous duty cycle correction circuits shown inFIGS. 1 and 4, various components shown inFIG. 8are used as a locking mechanism, such as the registers826–832and the counters834–836. Among other things, the locking mechanism generates the control signals cnt1cand cnt1f, which identify the signals to be output by the multiplexors810–820. By adjusting the operation of the multiplexors810–820, the locking mechanism controls the amount of delay provided by the delay lines802–808so that the output clock signal CLK achieves a duty cycle of approximately fifty percent.

FIG. 9illustrates an alternate embodiment of the third example duty cycle correction circuit according to one embodiment of this disclosure. In particular,FIG. 9illustrates a duty cycle correction circuit900similar to the duty cycle correction circuit800ofFIG. 8, where the duty cycle correction circuit900uses a locking mechanism similar in nature to the locking mechanism shown inFIG. 7.

As shown inFIG. 9, the duty cycle correction circuit900uses two registers930–932to generate two signals det1and det2. The signals det1and det2are used by two counters934–936to generate the control signals cnt1cand cnt1f. As a particular example, the counter934could implement the following logic:if (˜c_lock & det1) then cnt1c=cnt1c−1else if (˜c_lock & ˜det1) then cnt1c=cnt1c+1else if (˜f_lock & det2) then cnt1c={1′b0, cnt1c}else cnt1c=cnt1c.
where c_lock and f_lock represent signals produced by two finite state machines950–952. As another particular example, the counter936could implement the following logic:if (˜f_lock & det2) then cnt1f={1′b0, cnt1f}else if (˜f_lock & ˜det2) cnt1f=cnt1f+1else cnt1f=cnt1f.

The duty cycle correction circuit900also includes the finite state machines950–952and two multiplexors954–956, which act as control signal blockers to block the control signals cnt1cand cnt1ffrom reaching the multiplexors810and812, respectively. In this example, the finite state machine950includes an OR gate and a register formed from a D flip-flop with reset. The finite state machine950uses the signal det1to produce the signal c_lock. The finite state machine952includes an AND gate, an OR gate, and a register formed from a D flip-flop with reset. The finite state machine952uses the signal det2and the output of the finite state machine950to produce the signal f_lock. The signals c_lock and f_lock are used by the counters934–936as shown above, by the multiplexors954–956, and by an AND gate958to control the input to the register932.

Initially, the multiplexor810may output the signal at its “0” input during coarse tuning, and the counter934varies the control signal cnt1cuntil the appropriate delay is identified using the multiplexor816. At that point, the signal det1goes high, causing the counter934to divide its counter value in half (thereby dividing the identified delay between the delay lines802and806) and causing the signal c_lock to become high. During fine tuning, the multiplexor812outputs the signal at its “0” input, and the counter936varies the control signal cnt1funtil the appropriate delay is identified using the multiplexor818. At that point, the signal det2goes high, causing the counter936to divide its counter value in half (thereby dividing the identified delay between the delay lines804and808) and causing the signal f_lock to become high. At the completion of fine tuning, the delay provided by the delay lines802–804is approximately equal to the delay provided by the delay lines806–808.

AlthoughFIGS. 1 through 9have illustrated several duty cycle correction circuits, various changes may be made toFIGS. 1 through 9. For example, while shown as containing specific logic (such as XOR gates or D flip-flops), other logic that performs the same or similar functions could be used in the duty cycle correction circuits.

FIGS. 10 through 12illustrate an example odd-number clock frequency multiplier according to one embodiment of this disclosure. In particular,FIG. 10illustrates an odd-number clock frequency multiplier1000, andFIGS. 11 and 12illustrate example operations of the odd-number clock frequency multiplier1000.

As shown inFIG. 10, the clock frequency multiplier1000is similar in structure to the duty cycle correction circuit100. In this example, the clock frequency multiplier1000includes three delay lines1002–1006, two inverters1008–1010, four multiplexors1012–1018, an XOR gate1020, two registers1022–1024, an N-bit up-down counter1026, and a clock combiner1028. In some embodiments, the delay lines1002–1006represent coarse delay lines. In particular embodiments, the delay lines1002–1006are identical to one another.

In this example, the delay line1002receives a clock signal CK and produces multiple delayed versions of the clock signal CK. The multiplexor1012selects and outputs one of the delayed versions of the clock signal CK as a clock signal CK2. The XOR gate1020uses the clock signals CK and CK2to produce an output clock signal CLK.

The clock signal CLK is also inverted by the inverter1008, and the delay line1004produces multiple delayed versions of the inverted clock signal CLK. The multiplexor1014selects and outputs one of the delayed versions of the inverted clock signal CLK as a clock signal CLKB. The inverter1010inverts the clock signal CLKB, and the delay line1006produces multiple delayed versions of the inverted clock signal CLKB. The multiplexor1016selects and outputs one of the delayed versions of the inverted clock signal CLKB as a clock signal CLK2. The multiplexor1018selects and outputs either the inverted clock signal CLKB or one of the delayed versions of the inverted clock signal CLKB as a clock signal CLK2P.

The clock signal CLK2is sampled by the register1022, which outputs a signal incb. The clock signal CLK2P is sampled by the register1024, which outputs a signal dec. The signals incb and dec are used by the counter1026to adjust a counter value, which is output as a control signal cnt1c. The counter1026may, for example, operate in the same manner as the counter120ofFIG. 1. The control signal cnt1ccontrols which signals are output by the multiplexors1012–1018.

The combiner1028merges pulses in the clock signals CLK, CLKB, and CLK2based on the input clock signal CK. In this example, the combiner1028includes three AND gates and one OR gate, where one of the AND gates has two inverted inputs. The combiner1028generates an output clock signal CLK3, which has three times the frequency of the input clock signal CK after locking.

Various components shown inFIG. 10implement the same type of locking mechanism described above with respect toFIG. 1. The locking mechanism could, for example, include the registers1022–1024and the counter1026, which generate the control signal cnt1c. The control signal cnt1cadjusts the operation of the multiplexors1012–1018until the appropriate output clock signal CLK3is generated.

Example operations of the clock frequency multiplier1000are shown inFIGS. 11 and 12. InFIG. 11, “Delay1” corresponds to the delay provided by the delay line1002at the tap point selected by the multiplexor1012, and “Delay2” corresponds to the delay provided by the delay line1004at the tap point selected by the multiplexor1014. “Delay3A” corresponds to the delay provided by the delay line1006at the tap point selected by the multiplexor1016, and “Delay3B” corresponds to the delay provided by the delay line1006at the tap point selected by the multiplexor1018. Delay1, Delay2, and Delay3A are approximately equal, and Delay3B is shorter than Delay1, Delay2, and Delay3A by an amount equal to the delay associated with one delay cell in the delay line1006.

As shown inFIG. 11, the clock frequency multiplier1000generally operates to divide the period T of the input clock signal CK into thirds. The counter1026increments or decrements the counter value forming the control signal cnt1cuntil the end of the period T occurs within a range defined by (i) the combined value of Delay1, Delay2, and Delay3A and (ii) the combined value of Delay1, Delay2, and Delay3B. When this condition is satisfied, the tap points selected for the delay lines1002–1006are used to produce the output clock signal CLK3, which has approximately three times the frequency as the input clock signal CK.

As shown inFIG. 12, the input clock signal CK received by the clock frequency multiplier1000has a duty cycle of approximately fifty percent. The multiplexor1012provides a delayed version of the clock signal CK as the clock signal CK2to the XOR gate1020. The XOR gate1020produces the clock signal CLK. As shown inFIG. 12, the duty cycle of the clock signal CLK generally increases until the clock signal CLK has a pulse width that is approximately one third the pulse width of the input clock signal CK.

This pulse width is achieved by the counter1026adjusting which signals are output by the multiplexors1012–1018. The inverter1008, delay line1004, and multiplexor1014use the clock signal CLK to generate the clock signal CLKB. As shown inFIG. 12, the clock signal CLKB represents an inverted version of the clock signal CLK that lags the clock signal CLK. The duty cycle of the clock signal CLKB generally increases until the clock signal CLKB has a pulse width that is approximately two thirds the pulse width of the input clock signal CK.

The inverter1010, delay line1006, and multiplexors1016–1018use the clock signal CLKB to generate the clock signals CLK2and CLK2P. As shown inFIG. 12, the clock signal CLK2represents a delayed version of the clock signal CLK. The clock signal CLK2P would therefore represent a similar signal that leads the clock signal CLK2by one delay cell delay.

The clock signals CLK2and CLK2P are used to produce the signals incb and dec, which are used by the counter1026to increment or decrement a counter value. Through operation of the counter1026, the pulses in the clock signals CLK, CLKB, and CLK2are eventually used to divide each period of the clock signal CK into thirds. By combining the pulses, the combiner1028effectively triples the frequency of the clock signal CK in the clock signal CLK3, and the clock signal CLK3achieves a duty cycle of approximately fifty percent. In some embodiments, the multiplexors1012–1018initially output the signals received at their “0” inputs, and the multiplexors1012–1018output different signals as the value provided by the counter1026changes.

While the clock frequency multiplier1000shown inFIG. 10is used to multiply the frequency of the input clock signal CK by three, the clock frequency multiplier1000ofFIG. 10could be extended to multiply the frequency of the clock signal CK by any higher odd number. For example, to multiply the frequency of the clock signal CK by five, the elements shown in box1030ofFIG. 10could be duplicated two additional times, providing (among other things) three delay lines1004and five delay lines in total. Also, the combiner1028could be extended to include five AND gates and one OR gate. Similarly, to multiply the frequency of the clock signal CK by seven, the elements shown in box1030ofFIG. 10could be duplicated four additional times, providing five delay lines1004and seven delay lines total. Also, the combiner1028could be extended to include seven AND gates and one OR gate.

FIG. 13illustrates an example even-number clock frequency multiplier1300according to one embodiment of this disclosure. In this example embodiment, the clock frequency multiplier1300includes four delay lines1302–1308, five multiplexors1310–1318, an XOR gate1320, two registers1322–1324, an N-bit up-down counter1326, and a clock combiner1328. In particular embodiments, the delay lines1302–1308are identical to one another.

The delay line1302produces multiple delayed versions of an input clock signal CK, and one version is output by the multiplexor1310as a clock signal CK2. The XOR gate1320generates a clock signal CLK1using the clock signals CK and CK2. The delay line1304and multiplexor1312generate a clock signal CLK2using the clock signal CLK1. The delay line1306and the multiplexor1314generate a clock signal CLK3using the clock signal CLK2. The delay line1308and the multiplexors1316–1318generate clock signals CLK4and CLK4P using the clock signal CLK3.

The clock signals CLK4and CLK4P are used by the registers1322–1324to generate signals incb and dec. The signals incb and dec are used by the counter1326to increment or decrement a counter value and generate a control signal cnt1c, which controls the multiplexors1310–1318. The counter1326may, for example, operate in the same manner as the counter120ofFIG. 1. In some embodiments, the multiplexors1310–1318output the signals received at their “0” inputs, and the multiplexors1310–1318output different signals as the value provided by the counter1326changes.

The combiner1328merges pulses in two of the clock signals CLK1–CLK4to generate an output clock signal CLK. Each of the clock signals CLK1–CLK4has a pulse width that is approximately one-fourth the pulse width of the input clock signal CK. Also, each of the clock signals CLK1–CLK4has two pulses during each cycle of the clock signal CK. By combining either the clock signals CLK1and CLK3or the clock signals CLK2and CLK4, the output clock signal CLK has four times the frequency of the input clock signal CK. In this example, the combiner1328includes one OR gate that combines the clock signals CLK1and CLK3. In other embodiments, the combiner1328could combine the clock signals CLK2and CLK4.

Various components shown inFIG. 13implement the same type of locking mechanism described above with respect toFIG. 1. Among other things, these components generate the signals incb and dec, which are used by the counter1326to increment or decrement the control signal cnt1cand generate the appropriate output clock signal CLK.

While the clock frequency multiplier1300shown inFIG. 13is used to multiply the frequency of an input clock signal CK by four, the clock frequency multiplier1300ofFIG. 13could be extended to multiply the frequency of the clock signal CK by any higher even number. For example, to multiply the frequency of the clock signal CK by six, the elements shown in box1330ofFIG. 13could be duplicated two additional times, providing (among other things) three delay lines1304and six delay lines in total. Similarly, to multiply the frequency of the clock signal CK by eight, the elements shown in box1330ofFIG. 13could be duplicated four additional times, providing five delay lines1304and eight delay lines total. In either case, the combiner1328could include a single OR gate or multiple OR gates to combine the signals produced by at least some of the delay lines.

AlthoughFIGS. 10 through 13have illustrated several clock frequency multipliers, various changes may be made toFIGS. 10 through 13. For example, while shown as containing specific logic (such as XOR gates or D flip-flops), other logic that performs the same or similar functions could be used in the duty cycle correction circuits. Also, as noted above, the clock frequency multipliers could be expanded to multiply a clock frequency by different amounts.

FIGS. 14 and 15illustrate an example multiplexor according to one embodiment of this disclosure. In particular,FIG. 14illustrates an example multiplexor1400, andFIG. 15illustrates an example decoder used in the multiplexor1400. The multiplexor1400shown inFIGS. 14 and 15could be used as any of the multiplexors in any of the preceding figures.

As shown inFIG. 14, the multiplexor1400receives sixteen input signals M0–M15and produces an output signal OUT. The output signal OUT generally represents a selected one of the input signals M0–M15. The multiplexor1400may generally operate to block all but one of the input signals M0–M15from the output signal OUT.

In this example, the multiplexor1400includes multiple tri-state buffers1402a–1402pand a decoder1404. Based on control signals S0–S15from the decoder1404, each of the tri-state buffers1402a–1402peither allows one of the input signals M0–M15to pass or enters a high impedance state. During operation, the decoder1404typically allows different tri-state buffers1402a–1402pto output their associated input signals in the output signal OUT, thereby controlling which input signals are blocked and which input signal is allowed to pass.

In this example, the decoder1404receives four input control signals SI0–SI3, a clock signal CK, and a reset signal RESET. The decoder1404generates the control signals S0–S15using the input control signals SI0–SI3, and logic in the decoder1404is clocked by the clock signal CK. As shown inFIG. 15, one embodiment of the decoder1404uses combinatorial logic or other circuitry to generate intermediate signals SO0–SO15. The intermediate signals SO0–SO15are provided to registers1502a–1502p, respectively. In this example, the register1502arepresents a D flip-flop with set and the registers1502b–1502prepresent D flip-flops with reset. The registers1502a–1502psample the intermediate signals SO0–SO15to produce the output signals S0–S15.

AlthoughFIGS. 14 and 15illustrate one example of a multiplexor1400, various changes may be made toFIGS. 14 and 15. For example, the multiplexor1400could be modified to handle any number of input signals in place of signals M0–M15(such as 2Ninput signals) and any number of input control signals in place of SI0–SI3(such as N control signals). Also, the circuits shown inFIGS. 1 through 13could use any other suitable multiplexor or multiplexors and need not use the specific multiplexor1400shown inFIGS. 14 and 15.

FIGS. 16 through 18illustrate an example digital multiphase oscillator according to one embodiment of this disclosure. In particular,FIG. 16illustrates an example digital multiphase oscillator1600,FIG. 17illustrates an example control signal generator in the digital multiphase oscillator1600, andFIG. 18illustrates an example phase generator in the digital multiphase oscillator1600.

As shown inFIG. 16, the digital multiphase oscillator1600includes a pulse generator1602, a control signal generator1604, and a phase generator1606. The pulse generator1602receives a reference clock signal REF and generates four clock signals CLK1–CLK4. In this example, each of the clock signals CLK1–CLK4contains two pulses for every pulse in the reference clock signal REF. Once locked, the clock signals CLK1–CLK4also have a pulse width equal to one-fourth the pulse width of the reference clock signal REF. Collectively, the clock signals CLK1–CLK4contain eight pulses for each pulse in the reference clock signal REF. The pulse generator1602could, for example, represent the clock frequency multiplier1300ofFIG. 13(without the clock combiner1328).

The control signal generator1604uses the clock signals CLK1–CLK4and the reference clock signal REF to generate control signals S1–S4and R1–R4. As shown inFIG. 17, the control signal generator1604could include an inverter1702and multiple AND gates1704. The inverter1702inverts the reference clock signal REF. Each AND gate1704performs a logical AND operation using one of the clock signals CLK1–CLK4and either the reference clock signal REF or the inverted reference clock signal REF. The control signals S1–S4and R1–R4are used to control the operation of the phase generator1606.

The phase generator1606receives the control signals S1–S4and R1–R4from the control signal generator1604. As shown inFIG. 18, the phase generator1606may be formed from multiple registers1802a–1802h. In this example, each of the registers1802a–1802hrepresents a D flip-flop with set and reset, where the clock input and D input for each register is grounded. Each of the registers1802a–1802hreceives a different one of the control signals D1–D4and R1–R4as its set (S) input, and each of the registers1802a–1802hreceives a different one of the control signals D1–D4and R1–R4as its reset (R) input. Each of the registers1802a–1802houtputs a high logic value when its set input is high and a low logic value when its reset input is high.

Because the control signals S1–S4and R1–R4are based on accurate clock signals CLK1–CLK4produced by the pulse generator1602, the registers1802a–1802hproduce output signals P1–P8that represent equally-spaced out-of-phase signals. For example, the output signals P1–P8may represent different out-of-phase versions of the reference clock signal REF. As a particular example, the output signal P1may be approximately in-phase with the reference clock signal REF, and each of the remaining output signals P2–P8may be approximately 45° out-of-phase with respect to the previous output signal. In this example, the output signal P2may be 45° out-of-phase with respect to the reference clock signal REF, the output signal P3may be 90° out-of-phase with respect to the reference clock signal REF, the output signal P5may be 180° out-of-phase with respect to the reference clock signal REF, and the output signal P7may be 270° out-of-phase with respect to the reference clock signal REF.

The digital multiphase oscillator1600ofFIG. 16could be used in a wide variety of applications. For example, the digital multiphase oscillator1600could be used in phase locked loops (PLLs), clock/data recovery (CDR) circuits, and clock generators. As a particular example, in clock/data recovery circuits, the digital multiphase oscillator1600could be used to recover data or clock signals while reducing or eliminating PVT variations, which typically cause jitter or other problems in conventional clock/data recovery circuits.

AlthoughFIGS. 16 through 18illustrate one example of a digital multiphase oscillator1600, various changes may be made toFIGS. 16 through 18. For example, the pulse generator1602could represent any suitable circuit that uses digital delay to accurately provide multiple clock signals. Also, the embodiments of the control signal generator1604and phase generator1606shown inFIGS. 17 and 18are for illustration only. Other embodiments of the control signal generator1604and phase generator1606could be used. In addition, the pulse generator1602, control signal generator1604, and phase generator1606could each produce any suitable number of outputs.

FIG. 19illustrates an example method1900for digital delay according to one embodiment of this disclosure. For ease of explanation, the method1900is described with respect to the various circuits shown in the preceding figures. The same or similar method could be used with any other suitable circuit.

Multiple versions of an input signal are generated using one or more first delay lines at step1902. This may include, for example, the delay line102, the delay lines402–404, the delay line802–804, the delay line1002, or the delay line1302generating multiple delayed versions of an input clock signal CK. The multiple versions of the input signal are generated at multiple tap points in at least one of the first delay lines.

At least one of the delayed versions of the input signal is selected at step1904. This may include, for example, the multiplexor106, the multiplexor410, the multiplexors810–812or810–814, the multiplexor1012, or the multiplexor1310selecting and outputting at least one of the delayed versions of the input clock signal CK. Initially, each multiplexor may output the signal received at its “0” input.

An output signal is generated using the selected delayed version(s) of the input signal at step1906. This may include, for example, the XOR gate112, the XOR gate416, the XOR gate822, the XOR gate1020, or the XOR gate1320generating an output clock signal (such as signal CLK or signal CLK1). The XOR gate could generate the output signal using the input signal and a delayed version of the input signal.

Multiple versions of the output signal are generated using one or more second delay lines at step1908. This may include, for example, the delay line104, the delay lines406–408, the delay lines806–808, the delay lines1004–1006, or the delay lines1304–1308generating multiple delayed versions of the output clock signal CLK or CLK1. The multiple versions of the output signal are generated at multiple tap points in at least one of the second delay lines.

At least one of the delayed versions of the output signal is selected at step1910. This may include, for example, the multiplexors108–110, the multiplexor412or the multiplexors412–414, the multiplexors816–818or the multiplexors816–820, the multiplexors1014–1018, or the multiplexors1312–1318selecting and outputting at least one of the delayed versions of the output clock signal. Initially, each multiplexor may output the signal received at its “0” input.

A determination is made as to whether the output signal is acceptable using the selected version(s) of the output signal at step1912. This may include, for example, using multiple selected versions of the output signal to determine if the output signal has a duty cycle of approximately fifty percent. This may also include using multiple selected versions of the output signal to determine if the output signal is a frequency multiple of the input signal. This may further include using a single selected version of the output signal to determine if the output signal has a duty cycle of approximately fifty percent and/or is a frequency multiple of the input signal.

If the output signal is not acceptable at step1914, the method1900returns to step1904to repeat steps1904–1912using different selected versions of the delayed input and output signals. This may include, for example, incrementing or decrementing one of one or more counter values to alter the outputs of the multiplexors106–110, the multiplexors410–414, the multiplexors810–820, the multiplexors1012–1018, or the multiplexor1310–1318.

If the output signal is acceptable at step1914, the output signal is generated using specified settings of the one or more first delay lines and the one or more second delay lines at step1916. This may include, for example, using one or more current counter values to control the outputs of the multiplexors. This may also include altering one or more current counter values (such as dividing a counter value in half) to control the outputs of the multiplexors.

AlthoughFIG. 19illustrates one example of a method1900for digital delay, various changes may be made toFIG. 19. For example, various steps inFIG. 19could be repeated to identify the appropriate settings for multiple delay lines. This may occur when various steps inFIG. 19are used during coarse tuning and then repeated during fine tuning.