Mounting substrate and electronic apparatus

There is provided a mounting substrate that makes a seam more inconspicuous when a plurality of mounting substrates are tiled, and an electronic apparatus including the mounting substrate.The mounting substrate includes a wiring substrate, a plurality of pixels (11) arranged in a matrix in a pixel region of the wiring substrate, and a plurality of drivers (14A) that are disposed in the pixel region and select the pixels in units of two or more pixels. Each of the pixels includes an optical element that emits or receives light, and a pixel circuit that controls light emission or light reception of the optical element. One or more of the plurality of drivers are assigned to each pixel row or every plurality of pixel rows.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a National Stage of International Application No. PCT/JP2015/057849, filed in the Japanese Patent Office as a Receiving office on Mar. 17, 2015, which claims priority to Japanese Patent Application Number 2014-074842, filed in the Japanese Patent Office on Mar. 31, 2014, each of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present technology relates to a mounting substrate including a driver on a wiring substrate and an electronic apparatus including the mounting substrate.

BACKGROUND ART

COG (Chip On Glass) and COF (Chip On Film) are known as techniques of mounting a driver that selects a display pixel (refer to Patent Literatures 1 and 2, for example).

CITATION LIST

Patent Literature

Patent Literature 1: Japanese Unexamined Patent Application Publication No. 2007-188079Patent Literature 2: Japanese Unexamined Patent Application Publication No. 2012-042567

SUMMARY

When COG is used, it is necessary to provide space for mounting of a connection terminal of an FPC on a top surface end of a mounting substrate. When COF is used, it is necessary to provide space for mounting of a driver on a top surface end of a mounting substrate. This means that in either of the techniques, space is necessary on the top surface end of the mounting substrate. Accordingly, it is necessary to provide a frame region in which display pixels are not allowed to be disposed. However, providing such a frame region causes an issue that when a plurality of mounting substrates are tiled, a seam is clearly visible in a displayed image.

Note that such an issue may occur not only in the field of display units but also in the field of illumination units and light receivers.

It is therefore desirable to provide a mounting substrate that makes a seam more inconspicuous when a plurality of mounting substrates are tiled, and an electronic apparatus including the mounting substrate.

A mounting substrate according to an embodiment of the present technology includes: a wiring substrate; a plurality of pixels arranged in a matrix in a pixel region of the wiring substrate; and a plurality of drivers that are disposed in the pixel region and select the plurality of pixels in units of two or more pixels. Each of the pixels includes an optical element and a pixel circuit. The optical element emits or receives light. The pixel circuit controls light emission or light reception of the optical element. One or more of the plurality of drivers are assigned to each pixel row or every plurality of pixel rows.

An electronic apparatus according to an embodiment of the present technology includes one or more mounting substrates mentioned above, and a control circuit that controls the one or more mounting substrates.

In the mounting substrate and the electronic apparatus according to the embodiments of the present technology, the plurality of drivers are disposed in the pixel region, and one or more of the drivers are assigned to each pixel row or every plurality of pixel rows. Accordingly, it is not necessary to provide the plurality of drivers on a top surface end of the mounting substrate, and it is not necessary to provide a connection terminal of an FPC including the plurality of drivers on the top surface end of the mounting substrate.

According to the mounting substrate and the electronic apparatus according to the embodiments of the present technology, the plurality of drivers are disposed in the pixel region, and one or more of the drivers are assigned to each pixel row or every plurality of pixel rows, which makes a seam more inconspicuous when a plurality of mounting substrates are tiled.

EMBODIMENTS FOR CARRYING OUT THE INVENTION

In the following, some embodiments of the present technology are described in detail with reference to the drawings. It is to be noted that description is given in the following order.

5. Modification Examples Common to Respective Embodiments

1. First Embodiment

FIG. 1illustrates an example of a perspective configuration of a display unit1according to a first embodiment of the present technology. The display unit1is a so-called LED display that uses LEDs as display pixels. The display unit1may include, for example, a display panel module10and a controller20that controls the display panel module10(more specifically, a plurality of cells12E to be described later) as illustrated inFIG. 1. The display panel module10may include, for example, a display panel12and circuits (such as a source driver13and a gate driver14) that are provided around the display panel12. Each of the cells12E corresponds to a specific example of a “mounting substrate” of the present technology. The controller20corresponds to a specific example of a “control circuit” of the present technology.

The display panel12includes a plurality of pixels11that are arranged in a matrix in an entire pixel region12aof the display panel12. The pixels11correspond to a specific example of “pixels” of the present technology. The pixel region12acorresponds to a region (display region) where an image is displayed on the display panel1. The controller20drives the respective pixels11by active matrix driving, which causes the display panel12to display an image on the basis of image signals Vsig1to VsigN in the display region. The image signals Vsig1to VsigN are phase-developed image signals.

The display panel12includes a plurality of gate lines Gate and a plurality of data lines Sig. The gate lines Gate extends along a row direction, and the data lines Sig extend along a column direction. The data lines Sig correspond to a specific example of “signal lines” of the present technology. The gate lines Gate correspond to a specific example of “selection lines” of the present technology. One of the pixels11is provided at a corresponding one of intersections between the data lines Sig and the gate lines Gate. Each of the data lines Sig is coupled to an output terminal of the source driver13. Each of the gate lines Gate is coupled to an output terminal of the gate driver14.

FIG. 2illustrates an example of a perspective configuration of the display panel12. The display panel12is a panel configured by stacking the mounting substrate12A and a counter substrate12B. A surface of the counter substrate12B serves as an image display surface, and has a display region in its central portion. For example, the counter substrate12B may be disposed at a position facing the mounting substrate12A with a predetermined gap in between. Moreover, the counter substrate12B may be in contact with a top surface of the mounting substrate12A. The counter substrate12B may have, for example, a light-transmissive substrate that allows visible light to pass therethrough, such as a glass substrate, a transparent resin substrate, and a transparent resin film.

FIG. 3illustrates an example of a perspective configuration of the mounting substrate12A. For example, the mounting substrate12A may be configured of a plurality of unit substrates12C that are tiled as illustrated inFIG. 3.FIG. 4illustrates an example of a perspective configuration of the unit substrate12C. Each of the unit substrates12C may include, for example, a plurality of cells12E that are tiled and a supporting substrate12D that supports the cells12E. Each of the unit substrates12C may further include a control substrate (not illustrated). The control substrate may be electrically coupled to the cells12E through electrode pads34to be described later. The supporting substrate12D may be configured of, for example, but not limited to, a metal frame or a wiring substrate. In a case in which the supporting substrate12D is configured of a wiring substrate, it is possible for the supporting substrate12D to also serve as a control substrate. At this occasion, one or both of the supporting substrate12D and the control substrate are electrically coupled to the cells12E (or a wiring substrate30to be described later) through the electrode pads34. The supporting substrate12D corresponds to a specific example of a “supporting substrate” of the present technology. The foregoing wiring substrate corresponds to a specific example of a “wiring substrate” of the present technology. The electrode pad34corresponds to a specific example of an “electrode pad” of the present technology.

(Circuit Configuration of Cell12E)

FIG. 5illustrates an example of a schematic configuration of a circuit in the cell12E.FIG. 5illustrates a plurality of data lines Sig and a plurality of gate lines Gate that are main wiring lines, a plurality of pixels11, and a plurality of gate driver ICs14A. The gate driver ICs14A corresponds to a specific example of “drivers” of the present technology. Note that the gate driver ICs14A are described later.FIG. 6illustrates an example of a specific configuration of the circuit in the cell12E.

The cell12E includes the plurality of data lines Sig and the plurality of gate lines Gate in the foregoing pixel region12a. The data lines Sig extends along the column direction, and the gate lines Gate extends along the row direction. The data lines Sig and the gate lines Gate may be made of copper, for example. The cell12E may further include the plurality of pixels11that are arranged in a matrix in the foregoing pixel region12a. Each of the pixels11includes a light-emitting element15and a drive IC16that controls light emission of the light-emitting element15. The light-emitting element15corresponds to a specific example of an “optical element” or a “light-emitting element” of the present technology. The drive IC16corresponds to a specific example of a “pixel circuit” of the present technology.

The cell12E may further include, for example, a plurality of sawtooth voltage lines Saw, a plurality of power source lines VDD1and VDD2, a plurality of reference voltage lines Ref1and Ref2, and a plurality of ground lines GND in the pixel region12a. The sawtooth voltage lines Saw may extend along a predetermined direction (more specifically, the row direction), for example. The power source lines VDD1, the power source lines VDD2, the reference voltage lines Ref1, the reference voltage lines Ref2, and the ground lines GND may extend along a predetermined direction (more specifically, the column direction), for example. It is possible to omit one or more of the sawtooth voltage lines Saw, the power source lines VDD1and VDD2, the reference voltage lines Ref1and Ref2, and the ground lines GND, depending on a driving mode. The sawtooth voltage lines Saw, the power source lines VDD1and VDD2, the reference voltage lines Ref1and Ref2, and the ground lines GND may be made of copper, for example. As used herein, the data lines Sig, the power source lines VDD1, the power source lines VDD2, the reference voltage lines Ref1, the reference voltage lines Ref2, and the ground lines GND are collectively referred to as column wiring lines. Moreover, as used herein, the gate lines Gate and the sawtooth voltage lines Saw are collectively referred to as row wiring lines.

Each of the data lines Sig is a wiring line to which a signal corresponding to an image signal is to be inputted by the source driver13. The signal corresponding to the image signal may be, for example, a signal for control of light emission luminance of the light-emitting element15. The plurality of the data lines Sig may be configured of, for example, wiring lines of a number of kinds corresponding to the number of emission colors of the light-emitting element15. In a case in which the light-emitting element15has three emission colors, the plurality of data lines Sig may include, for example, a plurality of data lines SigR, a plurality of data lines SigG, and a plurality of data lines SigB. Each of the data lines SigR is a wiring line to which a signal corresponding to a red image signal is to be inputted by the source drive13. Each of the data lines SigG is a wiring line to which a signal corresponding to a green image signal is to be inputted by the source driver13. Each of the data lines SigB is a wiring line to which a signal corresponding to a blue image signal is to be inputted by the source driver13. At this occasion, the image signals Vsig1to VsigN may include, for example, a red image signal, a green image signal, and a blue image signal.

The number of emission colors of light-emitting element15is not limited to three, and may be four or more. In a case in which the plurality of data lines Sig include the plurality of data line SigR, the plurality of data lines SigG, and the plurality of data lines SigB, one set of the data lines Sig configured of one data line SigR, one data line SigG, and one data line SigR may be assigned to each pixel column, for example. In other words, three of the plurality of data lines Sig may be assigned to each pixel column, for example.

Each of the gate lines Gate is a wiring line to which a signal for selection of the light-emitting element15is to be inputted by the gate driver14. The signal for selection of the light-emitting element15may be, for example, a signal to start sampling a signal inputted to the data line Sig and to allow the sampled signal to be inputted to the light-emitting element15, thereby starting light emission of the light-emitting element15. One of the plurality of gate lines Gate may be assigned to each pixel row, for example.

Each of the sawtooth voltage lines Saw is a wiring line to which a signal having a sawtooth waveform is to be inputted by the controller20. The signal having the sawtooth waveform is compared with a sampled signal. For example, the sampled signal is inputted to the light-emitting element15only in a period in which a peak value of the signal having the sawtooth waveform is higher than a peak value of the sampled signal. One of the sawtooth voltage lines Saw may be assigned to every two pixel rows, for example.

Each of the power source lines VDD2is a wiring line to which a drive current to be supplied to the light-emitting element15is to be inputted by the controller20. One of the power source lines VDD2may be assigned to every two pixel columns, for example. Each of the power source lines VDD1, the reference voltage lines Ref1, the reference voltage lines Ref2, and the ground lines GND is a wiring line to which a fixed voltage is to be inputted by the controller20. A ground potential is inputted to each of the ground lines GND. One of the power source lines VDD1may be assigned to every two pixel columns, for example. One of the reference voltage lines Ref1may be assigned to every two pixel columns, for example. One of the reference voltage lines Ref2may be assigned to every two pixel columns, for example. One of the ground lines GND may be assigned to every two pixel columns, for example.

FIG. 7illustrates an example of a planar configuration of the light-emitting element15. A symbol in a square inFIG. 7indicates that a terminal adjacent to the symbol is electrically coupled to a terminal adjacent to a symbol identical thereto inFIG. 8to be described later. The light-emitting element15is a chip-like component that emits light of a plurality of colors. In a case in which the number of emission colors of the light-emitting element15is three, the light-emitting element15may include, for example, a light-emitting element15R that emits red light, a light-emitting element15G that emits green light, and a light-emitting element15B that emits blue light. The light-emitting elements15R,15G, and15B may be covered with a protector15imade of a resin or any other material, for example.

Each of the light-emitting elements15R,15G, and15B may be an LED chip, for example. Herein, the foregoing LED chip has a micrometer-order chip size, and may have several tens of μm square, for example. The LED chip may include, for example, a semiconductor layer and two electrodes disposed on a common surface (same surface) where the semiconductor layer is disposed. The semiconductor layer may have a stacked configuration in which an active layer is interposed between semiconductor layers of different conductive types. The light-emitting elements15R,15G, and15B may be chips separate from each other, or may form a common single chip.

The light-emitting element15may include, for example, six electrode pads15ato15f. In the light-emitting element15G, one of the electrodes is electrically coupled to an electrode pad16mof the drive IC16through the electrode pad15aand a wiring line17(refer toFIGS. 5 and 6), and the other electrode is electrically coupled to the ground line GND through the electrode pad15band the wiring line17. In the light-emitting element15R, one of the electrodes is electrically coupled to an electrode pad16oof the drive IC16through the electrode pad15cand the wiring line17, and the other electrode is electrically coupled to the ground line GND through the electrode pad15dand the wiring line17. In the light-emitting element15B, one of the electrodes is electrically coupled to an electrode pad16pof the drive IC16through the electrode pad15eand the wiring line17, and the other electrode is electrically coupled to the ground line GND through the electrode pad15fand the wiring line17.

The wiring line17may be, for example, a wiring line that electrically couples the pixel11to one of the data line Sig, the gate line Gate, the power source line VDD1, the power source line VDD2, the reference voltage line Ref1, the reference voltage line Ref2, the sawtooth voltage line Saw, and the ground line GND. The wiring line17may be, for example, a wiring line that electrically couples the light-emitting element15to the drive IC16in the pixel11as well. The wiring line17may be formed by sputtering or plating, for example. Some of a plurality of wiring lines17directly couple the pixel11to any of the foregoing various row wiring lines or the foregoing various column wiring lines. Each of the other wiring lines17of the plurality of wiring lines17is made up of a plurality of partial wiring lines that are discretely formed. In each of the wiring lines17made up of the plurality of partial wiring lines, partial electrodes may be coupled through one or a plurality of relay wiring lines that are formed on a top surface (for example, a wiring layer32E to be described later) of the wiring substrate30. The relay wiring line may be made of copper, for example.

FIG. 8illustrates an example of a planar configuration of the drive IC16. A wiring line name in a square inFIG. 8represents the name of a wiring line electrically coupled to a terminal adjacent to this wiring line name. The drive IC16controls light emission of the light-emitting element15. The drive IC16may include 14 electrode pads16a,16b,16c,16d,16e,16f,16g,16h,16i,16k,16m,16n,16o, and16p.

The electrode pads16a,16b, and16care respectively electrically coupled to the data lines SigG, SigR, and SigB through the wiring lines17. The electrode pads16dand16eare respectively electrically coupled to the power source lines VDD1and VDD2through the wiring lines17. The electrode pads16fand16gare respectively electrically coupled to the reference potential lines Ref1and Ref2through the wiring lines17. The electrode pad16his electrically coupled to the ground line GND through the wiring line17. The electrode pad16iis electrically coupled to the gate line Gate through the wiring line17. The electrode pad16kis electrically coupled to the sawtooth voltage line Saw through the wiring line17. The electrode pads16m,16o, and16nare electrically coupled to the electrode pads15a,15c, and15eof the light-emitting element15through the wiring lines17. The electrode pad16pis not coupled to the wiring line17.

Next, description is given of the source driver13, the gate driver14, and the gate driver IC14C with reference toFIGS. 1, 5, and 6.

The source driver13supplies the respective pixels11with analog image signals Vsig1to VsigN as signal voltages for one horizontal line inputted from the controller20. More specifically, the source driver13supplies the respective pixels11configuring one horizontal line selected by the gate driver14with the analog image signals Vsig1to VsigN for one horizontal line through the data lines Sig.

The gate driver14selects the pixels11as driving targets in response to a timing pulse TP inputted from the controller20. The timing pulse TP may include, for example, a shift signal and a clock signal. More specifically, the gate driver14selects, as driving targets, one row of the pixels11of the plurality of pixels arranged in a matrix by application of a selection signal to the drive IC16through the gate line Gate. Thereafter, these selected pixels11perform display of one horizontal line on the basis of the signal voltages supplied from the source driver13. Thus, the gate driver14performs line-sequential scanning in units of one horizontal line in a time-divisional manner to cause the display panel12to perform display on the entire pixel region12a.

The gate driver14is configured of the plurality of gate driver ICs14A. One of the plurality of the gate driver ICs14A is assigned to every plurality of pixel rows. For example, one of the gate driver ICs14A is assigned to every two pixel rows as illustrated inFIGS. 5 and 6. Accordingly, two gate lines Gate are coupled to each of the gate driver ICs14A.

Each of the gate driver ICs14A outputs the selection signal to the gate lines Gate on the basis of the shift signal and the clock signal to control a timing of sampling a data signal (i.e., light emission start timing) in the drive IC16. At this occasion, each of the drive ICs16performs sampling of the data signal inputted through the data line Sig on the basis of the selection signal inputted through the gate lines Gate. When the selection signal is outputted to a second one of the gate lines Gate, each of the gate driver ICs14A outputs a shift signal to the following gate driver IC14A in synchronization with an output timing of the selection signal. When each of the gate driver ICs14A outputs the selection signal to a first one of the gate lines Gate, the gate driver IC14A continuously outputs the selection signal to the second one of the gate lines Gate. Therefore, each of the gate driver ICs14A does not output the shift signal at this occasion.

The shift signal and the clock signal are inputted from the controller20to the gate driver IC14A (i.e., a first gate driver IC14A) assigned to a first pixel row and a second pixel row. In other words, the controller20directly outputs the shift signal and the clock signal to the first gate driver IC14A. Signal exchange between the controller20and the first gate driver IC14is performed through a shift line SFT and a clock line CLK.

In contrast, the shift signal and the clock signal are inputted to second and later gate driver ICs14A from their respective previous gate driver ICs14A. In other words, each of the second and later gate driver ICs14A outputs the shift signal and the clock signal to the following gate driver IC14A. Note that the clock signal may be inputted to each of the gate driver ICs14A directly and not through other gate driver ICs14A. In other words, the controller20may directly output the clock signal to each of the gate driver ICs14A. Signal exchange between the gate driver IC14A and the following gate driver IC14A is performed through the foregoing wiring line17.

Each of the gate driver ICs14A has a function for two pixel rows in the gate driver14. Accordingly, a chip size of each of the gate driver ICs14A is extremely smaller than a chip size of an IC generally used as the gate driver14, and is sufficiently smaller than a pitch of the pixels11. Therefore, each of the gate driver ICs14A is disposed adjacent to the pixel11without disturbing arrangement of the pixels11in the pixel region12a. For example, a thickness of each of the gate driver ICs14A may be substantially equal to or smaller than thicknesses of the light-emitting element15and the drive IC16. The thickness of each of the gate driver ICs14A may be 20 μm or less, for example.

FIG. 9illustrates an example of a cross-sectional configuration of the cell12E.FIG. 9illustrates an example of a cross-sectional configuration of a portion of the cell12E. In the portion, the light-emitting element15, the drive IC16, the data line Sig, and the clock line CLK are formed.

The cell12E may include, for example, the wiring substrate30, a fine L/S layer40, and a plurality of pixels11. The fine L/S layer40is formed in contact with the top surface of the wiring substrate30, and the pixels11are arranged in a matrix on a top surface of the fine L/S layer40. The wiring substrate30has a role as an intermediate substrate in relation to the wiring substrate12D.

The cell12E may further include, for example, an embedding layer44, a light-shielding layer45, and an insulating layer50. A surface including the pixels11is covered with the embedding layer44. The light-shielding layer45is formed in contact with the embedding layer44. The insulating layer50is formed in contact with a rear surface of the wiring substrate30. The embedding layer44is made of a light-transmissive material that allows visible light to pass therethrough. The light-shielding layer45includes a visible-light absorbing material. The insulating layer50may be made of an ultraviolet curable resin or a thermosetting resin.

The light-shielding layer45has an opening45A at a position facing each of the light-emitting elements15. Light emitted from each of the light-emitting elements15is outputted to outside through each of the openings45A. The insulating layer50has an opening50A at a position facing each of the electrode pads34serving as an external connection terminal of the cell12E. Accordingly, each of the electrode pads34is exposed on a rear surface of the cell12E (the wiring substrate30) through the opening50A. The electrode pad34and the wiring substrate12D may be electrically coupled to each other through, for example, a metal bump or a solder bump provided in the opening50A.

The wiring substrate30is a multilayer substrate utilizing via-bonding. The wiring substrate30includes a plurality of electrode pads34serving as external connection terminals on the rear surface of the wiring substrate30. One or more of the plurality of electrode pads34are provided for at least each of the gate driver ICs14A, and one or more of the electrode pads34may be provided for each of the gate driver ICs14A, the data lines Sig, the power source lines VDD1, the reference voltage lines Ref1, the reference voltage lines Ref2, and the sawtooth voltage lines Saw.

The wiring substrate30electrically couples the plurality of wiring lines17routed in the fine L/S layer40to the plurality of electrode pads34. The wiring substrate30includes a plurality of through wiring lines17that electrically couple the plurality of wiring lines17to the plurality of electrode pads34. Each of the through wiring lines17is a wiring line that penetrates the wiring substrate30in a thickness direction. Some of the through wiring lines17each include the data line Sig and a plurality of vias. The data line Sig extends along the column direction in the wiring substrate30. The plurality of vias penetrate one or more of layers in the wiring substrate30. Some of the through wiring lines17each include the clock line CLK and a plurality of vias. The clock line CLK extends in the column direction in the wiring substrate30. The plurality of vias penetrate one or more of the layers in the wiring substrate30.

Some of the through wiring lines17each include the power source line VDD1and a plurality of vias. The power source line VDD1extends along the column direction in the wiring substrate30. The plurality of vias penetrate one or more of the layers in the wiring substrate30. Some of the through wiring lines17each include the reference voltage line Ref1and a plurality of vias. The reference voltage line Ref1extends along the column direction in the wiring substrate30. The plurality of vias penetrate one or more of the layers in the wiring substrate30. Some of the through wiring lines17each include the reference voltage line Ref2and a plurality of vias. The reference voltage line Ref2extends along the column direction in the wiring substrate30. The plurality of vias penetrate one or more of the layers in the wiring substrate30. Some of the through wiring lines17include the sawtooth voltage line Saw and a plurality of vias. The sawtooth voltage line Saw extends along the column direction in the wiring substrate30. The plurality of vias penetrate one or more of the layers in the wiring substrate30.

Incidentally, as described above, for example, the plurality of pixels11are arranged at equal intervals along the row direction and the column direction as illustrated inFIG. 5. At this occasion, a pitch of the pixels11may be preferably equal not only in each of the cells12E but also in two adjacent cells12E. In each of the cells12E, a plurality of electrode pads34are provided as external connection terminals of each of the cells12E on the rear surface of the cell12E. This makes it possible to omit or minimize a frame region that is not usable for arrangement of the pixels11, for example, in a case in which an external connection terminal is provided on an outer edge of a top surface of a mounting surface. Accordingly, in a case in which such a frame region is omitted from each of the cells12E, or in a case in which such a frame region is minimized in each of the cells12E, it is possible for the pitch of the pixels11to be equal even in two adjacent cells12E.

The wiring substrate30may be, for example, a build-up substrate including a core substrate31, a build-up layer32, and a build-up layer33. The build-up layer32is formed in contact with a top surface of the core substrate31. The build-up layer33is formed in contact with a rear surface of the core substrate31.

The core substrate31ensures rigidity of the cell12E, and may be a glass epoxy substrate, for example. The build-up layer32includes one or more wiring layers. The build-up layer32may include, for example, a wiring layer32A, an insulating layer32B, a wiring layer32C, an insulating layer32D, and a wiring layer32E in this order from the top surface of the core substrate31, as illustrated inFIG. 9. The build-up layer33includes one or more wiring layers. The build-up layer33may include, for example, a wiring layer33A, an insulating layer33B, a wiring layer33C, an insulating layer33D, and an insulating layer33E in this order from the rear surface of the core substrate31, as illustrated inFIG. 9. The wiring layers32A,32C,32E,33A,33C, and33E may be made of copper, for example. The insulating layers32B,32D,33B, and33D may be made of an ultraviolet curable resin or a thermosetting resin.

Each of the data lines Sig may be formed in the wiring layer32C, for example. Each of the gate lines Gate are formed in a layer different from the data line Sig, and may be formed in the wiring layer32E that is a wiring layer on the top surface of the wiring substrate30, for example. Each of the clock lines CLK and the shift lines SFT may be formed in the same layer as the gate line Gate, and may be formed in the wiring layer32E. Each of the electrode pads34is formed in the build-up layer33, and may be formed in the same layer as the wiring layer33E, for example. The foregoing relay wiring line may be formed in the wiring layer32E, for example.

The fine L/S layer40includes a wiring layer42and an insulating layer41. The insulating layer41is provided between the wiring layer42(each of the wiring lines17) and the top surface of the wiring substrate30. The insulating layer41is in contact with the wiring layer42(each of the wiring lines17) and the top surface of the wiring substrate30. The insulating layer41may has an opening41A at a position facing a top surface of each of the gate line Gate, the clock line CLK, and the shift line STF, for example. For example, a portion of each of the gate line Gate, the clock line CLK, and the shift line STF may be exposed on a bottom surface of the opening41A. The insulating layer41may be made of VPA, for example. VPA is generally used as a resist. For example, VPA manufactured from Nippon Steel Chemical Co., Ltd. has been introduced on the market. In a case in which the insulating layer41is made of VPA, for example, selective light-exposure and development of VPA may make it possible to form the opening41in the VPA.

The wiring layer42(each of the wiring lines17) may include, for example, a seed layer42A and a plating layer42B. The seed layer42A is in contact with the top surface of the wiring substrate30including the bottom surfaces and side surfaces of the openings41A. The plating layer42B is in contact with a top surface of the seed layer42A. The seed layer42A serves as a plating growth surface when the plating layer42B is formed by plating in a manufacturing process. The seed layer42A is in contact with the bottom surfaces of the openings41A, and may be electrically coupled to the gate line Gate, the clock line CLK, and the shift line STF, for example. The seed layer42A may be made of copper, for example. The plating layer42B is formed by a plating process using the seed layer42as the plating growth surface in the manufacturing process. Note that the wiring layer42(each of the wiring lines17) may be a layer formed by sputtering, for example.

As described above, the wiring layer42(each of the wiring lines16) is formed in contact with the top surface of the insulating layer41. In contrast, electrodes of the pixels11are formed in contact with the top surface of the seed layer42A. Therefore, the light-emitting elements15and the drive ICs16are formed on the same surface (the top surface of the seed layer42A). To be exact, the light-emitting elements15and the drive ICs16are formed on a different surface from a surface (the top surface of the insulating layer41) where the wiring layer42(each of the wiring lines16) is formed. However, in terms of mounting of the pixels11, a surface including the top surface of the insulating layer41and the top surface of the seed layer42A serves as a mounting surface41S. Accordingly, the wiring layer42(each of the wiring lines16) is formed on the mounting surface41S for the pixels11, and is formed in a surface substantially common to the pixels11.

The wiring layer42(each of the wiring lines17) may be bonded to, for example, the gate driver ICs14A and members exposed in the openings41A (for example, the gate line Gate, the clock line CLK, and the shift line STF) by plating. When the wiring layer42(each of the wiring lines17) is formed by plating, bonding between the wiring layer42(each of the wiring lines17), and the gate driver ICs14A and the foregoing members exposed in the opening41A may be performed together in a process of forming the wiring layer42(each of the wiring lines17). The wiring layer42(each of the wiring line17) may be bonded to, for example, the pixels11(the light-emitting elements15and the drive ICs16) by plating. When the wiring layer42(each of the wiring lines17) is formed by plating, bonding between the wiring layer42(each of the wiring lines17) and the pixels11may be performed together in the process of forming the wiring layer42(each of the wiring lines17).

An L/S (line and space) of the fine L/S layer40is smaller than an L/S of the wiring substrate30. The L/S indicates the narrowest wiring pitch in a plane. The L/S of the fine L/S layer40is smaller than those of the plurality of signal lines Sig, the plurality of gate lines Gate, the plurality of voltage lines VDD1, the plurality of reference voltage lines Ref1, the plurality of reference voltage lines Ref2, and the sawtooth voltage lines Saw. The L/S of the fine L/S layer40may be about 25 μm, for example. In contrast, the L/S of the wiring substrate30may be about 75 μm, for example.

Next, description is given of an example of a method of manufacturing the cell12E with reference toFIGS. 10 to 14.FIGS. 10 to 14illustrate an example of a procedure of manufacturing the cell12E in order of processes.

First, the wiring substrate30is prepared. Next, the insulating layer41is formed on the top surface of the wiring substrate30, and thereafter, the openings41A are formed in the insulating layer41by a predetermined method (seeFIG. 10). Subsequently, the seed layer42A is formed on the top surface of the wiring substrate30including the bottom surfaces and the side surfaces of the openings41A (seeFIG. 11).

Next, a fixing layer43A that temporarily fixes the light-emitting elements15, the drive ICs16, and the gate driver ICs14A (hereinafter referred to as “the light-emitting elements15and the other components”) is formed by a process such as coating an entire surface with an insulating glue (refer toFIG. 12). A layer of an adhesive as typified by a silicone-based adhesive and an acrylic adhesive may be formed as the fixing layer43A instead of the glue. Subsequently, the light-emitting elements15and the other components are temporarily fixed by the fixing layer43A (seeFIG. 12). At this occasion, the electrode pads of the light-emitting elements15and the other components are disposed close enough to be connectable to a metal body (the plating layer42B) that is to be grown in a plating process to be described later.

Next, the fixing layer43A excluding portions that temporality fixes the light-emitting elements15and the other components (portions present on the bottom surfaces of the light-emitting element15and the other components) is removed. As a result, the fixing layer43A remains only on the bottom surfaces of the light-emitting elements15and the other components (seeFIG. 13). InFIG. 13, the remaining fixing layer43A is illustrated as a fixing layer43. In removing the fixing layer43A, it may be possible to perform, for example, dry etching or organic solvent immersion. Note that the insulating glue may be applied beforehand only to positions where the light-emitting elements15and the other components are to be temporarily fixed.

Thereafter, the plating process is performed with use of the seed layer42A as the plating growth surface to form the plating layer42B on the top surface of the seed layer42A (seeFIG. 14). Thus, the wiring layer42(each of the wiring lines17) is formed. At this occasion, bonding between the wiring layer42(each of the wiring lines17), and the light-emitting element15and the other components is performed together in the process of forming the wiring layer42(each of the wiring lines17). Moreover, bonding between the wiring layer42(each of the wiring lines17) and the foregoing members exposed in the openings41A is performed together in the process of forming the wiring layer42(each of the wiring lines17). After that, the light-emitting elements15and the other components are embedded in the embedding layer43, and thereafter, the light-shielding layer45is formed (refer toFIG. 9). Thus, the cell12E is manufactured.

Next, description is given of workings and effects of the display unit1. In the present embodiment, the plurality of gate driver ICs14A are disposed in the pixel region12a, and one of the gate driver ICs14A is assigned to every plurality of pixel rows. Accordingly, it is not necessary to provide the plurality of gate driver ICs14A on a top surface end of the cell12E and it is not necessary to provide a connection terminal of a FPC including the plurality of gate driver ICs14A on the top surface end of the cell12E. As a result, it is possible to make a seam in a displayed image more inconspicuous when the plurality of unit substrates12C are tiled.

2. Modification Examples

Modification Example 1

In the foregoing embodiment, one set of the data lines Sig is assigned to each pixel column. In other words, three of the plurality of data lines Sig are assigned to each pixel column. Alternatively, the foregoing set of the data lines Sig may be replaced with a single data line Sig, depending on a driving mode.

Modification Example 2

In the foregoing embodiment, one of the plurality of gate driver ICs14A is assigned to every plurality of pixel rows. Alternatively, one of the plurality of gate driver ICs14A may be assigned to each pixel row.

Modification Example 3

Moreover, in the foregoing embodiment, one set of the data lines Sig may be assigned to every plurality of pixel columns. In other words, two or more of the plurality of the data lines Sig may be assigned to every plurality of pixel columns. For example, one set of the data lines Sig may be assigned to every two pixel columns as illustrated inFIG. 15. In other words, three of the plurality of the data lines Sig may be assigned to every two pixel columns. Note that even in the present modification example, the foregoing one set of the data lines Sig may be replaced with a single data line Sig, depending on the a driving mode. In this case, one of the plurality of the data lines Sig is assigned to every plurality of pixel columns.

At this occasion, when pixel rows are separated into groups of a number of pixel rows equal to the number of pixels sharing one or more of the data lines Sig in one pixel row, a number of the gate lines Gate equal to the square of the number of pixels sharing the one or more of the data lines Sig in one pixel row are assigned to each of the groups. For example, when the pixel rows are separated into groups of two pixel rows, the square of two, i.e. four of the plurality of the gate lines Gate are assigned to each of the groups, as illustrated inFIG. 15.

One of the gate lines Gate assigned to each of the foregoing groups is assigned to each of the pixels11to which the shared one or more data lines Sig are assigned in each pixel row. For example, one of two gate lines Gate assigned to each of the foregoing groups may be assigned to pixels11in odd-numbered columns, and the other one may be assigned to pixels11in even-numbered columns, as illustrated inFIG. 15.

A number of the gate driver ICs14A equal to the number of pixel rows included in each of the foregoing groups is assigned. For example, two of the plurality of gate driver ICs14A may be assigned to each of the foregoing groups, as illustrated inFIG. 15.

In the present modification example, the plurality of gate driver ICs14A are disposed in the pixel region12a. Moreover, while the data line(s) Sig is shared by two or more of the pixels11included in one pixel row, a number of the gate driver ICs14A equal to the number of the pixel rows included in each of the foregoing groups are assigned to each of the foregoing groups. Accordingly, when the pixels11have the same pitch as that in the foregoing embodiment, it is possible to provide a larger space region in the pixel region12athan that in the foregoing embodiment. Hence, even in a case in which the pitch of the pixels11is narrower than the pitch of the pixels11in the foregoing embodiment, it is possible to dispose the respective gate driver ICs14in the pixel region12a. This makes it possible to narrow the pitch of the pixels11and make a seam in a displayed image more inconspicuous when the plurality of cells12E or the plurality of unit substrates12C are tiled.

Modification Example 4

Further, in the foregoing modification example 3, two gate lines Gate are coupled to each of the gate driver ICs14A; however, three or more gate lines Gate may be coupled to each of the gate driver ICs14A. For example, four gate lines Gate may be coupled to each of the gate driver ICs14A as illustrated inFIG. 16. In this case, each of the gate driver ICs14A outputs the shift signal to the following gate driver IC14C in synchronization with an output timing of the selection signal only when the selection signal is outputted to the last one of the four gate lines Gate. When each of the gate driver ICs14A outputs the selection signal to the gate lines Gate excluding the last gate line Gate, each of the gate driver ICs14A continues to output the selection signal to the following gate line Gate. Accordingly, each of the gate driver ICs14A does not output the shift signal at this occasion.

It is possible to couple three or more gate lines Gate to each of the gate driver ICs14A, which makes it possible to assign one of the plurality of gate driver ICs14A to each of the foregoing groups. For example, in a case in which it is possible to couple, to each of the gate driver ICs14A, a number of the gate lines Gate equal to the number of pixel rows included in each of the foregoing groups, one of the plurality of the gate driver ICs14A is assigned to each of the foregoing groups. For example, in a case in which it is possible to couple each of the gate driver ICs14A to four gate lines Gate, the plurality of gate lines Gate are separated into groups of four, and one of the gate driver ICs14A is assigned to each of the foregoing groups, as illustrated inFIG. 16.

Even in the present modification example, as with the foregoing modification example 3, it is possible to narrow the pitch of the pixels11and make a seam in a displayed image more inconspicuous when the plurality of cells12E or the plurality of unit substrates12C are tiled.

Modification Example 5

In the foregoing embodiment, the light-emitting element15and the drive IC16may be integrally formed to configure the pixel11.

Modification Example 6

Moreover, in the foregoing embodiment and the modification examples 1 to 6, the light-emitting elements15may have a single emission color. In this case, the cell12E may include, for example, a color filter for a plurality of colors in the opening45A.

3. Second Embodiment

FIG. 17illustrates an example of a schematic configuration of an illumination unit2according to a second embodiment of the present technology. The illumination unit2corresponds to the display unit1according to any of the foregoing first embodiment and the modification examples thereof (the modification examples 1 to 6), except that a signal to be inputted to the data line Sig does not change momently like the image signal, but has a fixed value corresponding to brightness of illumination light. For example, the illumination unit2may include an illumination panel module60and a controller70as illustrated inFIG. 17. The controller controls the illumination panel module60. The illumination panel module60may include, for example, an illumination panel62and circuits (such as the source driver13and the gate driver14). The circuits are provided around the illumination panel62.

The illumination panel62includes a plurality of pixels61arranged in a matrix in an entire pixel region of the illumination panel62. The pixel region corresponds to a region (a light emission region) where illumination light is emitted in the illumination panel62. The controller70drives the respective pixels61by active matrix driving, which causes the illumination panel62to emit illumination light on the basis of a signal Vsig having a fixed value corresponding to brightness of illumination light. The illumination panel62includes a plurality of gate lines Gate and a plurality of data lines Sig. The gate lines Gate extend along the row direction, and the data lines Sig extend along the column direction. One of the pixels61is provided at a corresponding one of intersections between the data lines Sig and the gate lines Gate.

FIG. 18illustrates an example of a perspective configuration of the illumination panel62. The illumination panel62is a panel configured by stacking a mounting substrate62A and a counter substrate62B. A surface of the counter substrate62B serves as a light emission surface. For example, the counter substrate62B may be disposed at a position facing the mounting substrate62A with a predetermined gap in between. Moreover, the counter substrate62B may be in contact with a top surface of the mounting substrate62A. The counter substrate62B may have, for example, a light-transmissive substrate that allows visible light to pass therethrough, such as a glass substrate, a transparent resin substrate, and a transparent resin film.

For example, the mounting substrate62A may be configured of a plurality of unit substrates that are tiled as illustrated inFIG. 2. Each of the unit substrates may include, for example, a plurality of cells that are tiled and a supporting substrate that supports the respective cells. Each of the unit substrates may further include a control substrate (not illustrated). The control substrate may be electrically coupled to the cells through the electrode pads34. The foregoing supporting substrate may be configured of, for example, but not limited to, a metal frame or a wiring substrate. In a case in which the supporting substrate is configured of a wiring substrate, it is possible for the supporting substrate to also serve as a control substrate. In each of the cells, wiring lines that are unnecessary for driving of the pixels61in a case in which a signal to be inputted to the data line Sig has a fixed value may be omitted as appropriate inFIGS. 5, 6, 9, 15, and 16, for example.

Next, description is given of workings and effects of the illumination unit2. In the present embodiment, as with the display unit1according to any of the foregoing first embodiment and the modification examples thereof, the plurality of gate drivers ICs14A are disposed in the pixel region (the light emission region), and are assigned according to a predetermined rule. Accordingly, it is not necessary to provide the plurality of gate driver ICs14A on a top surface end of the mounting substrate, and it is not necessary to provide a connection terminal of an FPC including the plurality of gate driver ICs14A on the top surface end of the mounting substrate. As a result, it is possible to make a seam in illumination light more inconspicuous when a plurality of mounting substrates are tiled.

FIG. 19illustrates an example of a schematic configuration of a light receiver3according to a third embodiment of the present technology. The light receiver3corresponds to the display unit1according to any of the foregoing first embodiment and the modification examples thereof (the modification examples 1 to 6), except that a signal to be inputted to the data line Sig does not vary momently like the image signal, but has a fixed value. Moreover, the light receiver3corresponds to the display unit1according to the foregoing first embodiment and modification examples thereof (the modification examples 1 to 4), except that light-receiving elements are provided in place of the pixels11.

The light receiver3may include, for example, a light-receiving panel module80and a controller90as illustrated inFIG. 19. The controller90controls the light-receiving panel module80. The light-receiving panel module80may include, for example, a light-receiving panel82and circuits (such as a readout circuit83and the gate driver14). The circuits are provided around the light-receiving panel82.

The light-receiving panel82includes a plurality of pixels81arranged in a matrix in an entire pixel region of the light-receiving panel82. The pixel region corresponds to a region (a light entry region) where outside light enters in the light-receiving panel82. The controller90drives the respective pixels81by active matrix driving, which causes the light-receiving panel82to detect a signal change on the basis of entry of outside light with use of the readout circuit83in a state in which a fixed signal Vsig is inputted from the readout circuit83. The light-receiving panel82includes a plurality of gate lines Gate and a plurality of data lines Sig. The gate lines Gate extend along the row direction, and the data lines Sig extend along the column direction. One of the pixels81is provided at a corresponding one of intersections between the data lines Sig and the gate lines Gate.

FIG. 20illustrates an example of a perspective configuration of the light-receiving panel82. The light-receiving panel82is a panel configured by stacking a mounting substrate82A and a counter substrate82B. A surface of the counter substrate82B serves as a light entry surface. For example, the counter substrate82B may be disposed at a position facing the mounting substrate82A with a predetermined gap in between. Moreover, the counter substrate82B may be in contact with a top surface of the mounting substrate82A. The counter substrate82B may have, for example, a light-transmissive substrate that allows visible light to pass therethrough, such as a glass substrate, a transparent resin substrate, and a transparent resin film.

For example, the mounting substrate82A may be configured of a plurality of unit substrates that are tiled as illustrated inFIG. 2. Each of the unit substrates may include, for example, a plurality of cells that are tiled and a supporting substrate that supports the respective cells. Each of the unit substrates may further include a control substrate (not illustrated). The control substrate may be electrically coupled to the cells through the electrode pads34. The foregoing supporting substrate may be configured of, for example, but not limited to, a metal frame or a wiring substrate. In a case in which the supporting substrate is configured of a wiring substrate, it is possible for the supporting substrate to also serve as a control substrate. In each of the cells, wiring lines that are unnecessary for driving of the pixels81in a case in which a signal to be inputted to the data line Sig has a fixed value are omitted as appropriate inFIGS. 5, 6, 9, 15, and 16, for example.

Next, description is given of workings and effects of the light receiver3. In the present embodiment, as with the display unit according to any of the foregoing first embodiment and the modification examples thereof, the plurality of gate drivers ICs14A are disposed in the pixel region (the light entry region), and are assigned according to a predetermined rule. Accordingly, it is not necessary to provide the plurality of gate driver ICs14A on a top surface end of the mounting substrate, and it is not necessary to provide a connection terminal of an FPC including the plurality of gate driver ICs14A on the top surface end of the mounting substrate. As a result, it is possible to make a seam in a light-received image more inconspicuous when a plurality of mounting substrates are tiled.

5. Modification Example Common to Respective Embodiments

In the foregoing respective embodiments and the modification examples thereof, the light-shielding layer45may be disposed on a rear surface of any of the counter substrates12B,62B, and82B (a surface facing any of the mounting substrates12A,62A, and82A).

In the foregoing respective embodiments and the modification examples thereof, for example, the counter substrates12B,62B, and82B may be omitted as illustrated inFIGS. 21 to 23. Moreover, in the foregoing respective embodiments and the modification examples thereof, one counter substrate12B, one counter substrate62B, or one counter substrate82B may be provided for each of the unit substrates12C or each of the cells12E.

In the foregoing respective embodiments and the modification examples thereof, the light-shielding layer45may be omitted.

Further, in the foregoing respective embodiments and the modification examples thereof, the pixels11,61, or81are bonded to the wiring layer42(each of the wiring lines17) by plating. Alternatively, for example, the pixels11,61, or81may be bonded to the wiring layer42(each of the wiring lines17) by soldering. For example, solder bumps may be provided on the electrode pads of the pixels11,61, or81, and thereafter, the pixels11,61, or81may be disposed on the wiring lines17. Thereafter, a reflow may be performed. This makes it possible to bond the pixels11,61, or81to the wiring lines17by soldering.

Moreover, the present technology may have any of the following configurations.

(1) A mounting substrate including:

a wiring substrate;

a plurality of pixels arranged in a matrix in a pixel region of the wiring substrate; and

a plurality of drivers that are disposed in the pixel region and select the plurality of pixels in units of two or more pixels,

wherein each of the pixels includes an optical element and a pixel circuit, the optical element that emits or receives light, and the pixel circuit that controls light emission or light reception of the optical element, and

one or more of the plurality of drivers are assigned to each pixel row or every plurality of pixel rows.

(2) The mounting substrate according to (1), wherein

the wiring substrate includes a plurality of selection lines extending along a row direction and a plurality of signal lines extending along a column direction,

each of the pixel circuits performs sampling of a data signal to be inputted through the signal line on the basis of a selection signal to be inputted through the selection line, and

each of the drivers outputs the selection signal to the selection lines on the basis of a shift signal and a clock signal to control a timing of sampling of the data signal in the pixel circuit and to output the shift signal to the following driver in synchronization with an output timing of the selection signal.

(3) The mounting substrate according to (1) or (2), wherein

the wiring substrate includes a plurality of electrode pads that are electrically coupled to the drivers and are exposed on a rear surface of the wiring substrate, one or more of the electrode pads being provided for each of the drivers, and

the clock signal is inputted from outside through one or more of the electrode pads.

(4) The mounting substrate according to any one of (1) to (3), wherein

one or more of the signal lines are assigned to each pixel column,

one of the selection lines is assigned to each pixel row, and

one of the drivers is assigned to each pixel row.

(5) The mounting substrate according to any one of (1) to (3), wherein

one or more of the signal lines are assigned to every plurality of pixel columns,

when pixel rows are separated into groups of a number of pixel rows equal to the number of pixels sharing the one or more signal lines in one pixel row, a number of the selection lines equal to the square of the number of pixels sharing the two or more the signal lines in one pixel row are assigned to each of the groups,

one of the selection lines assigned to each of the groups is assigned to each of the pixels to which the shared two or more signal lines are assigned in each pixel row, and

one of the plurality of drivers or a number of the plurality of drivers equal to the number of pixel rows included in each of the groups are assigned to each of the groups.

(6) An electronic apparatus including:

a plurality of mounting substrates; and

a control circuit that controls the plurality of mounting substrates,

each of the mounting substrates including:

a wiring substrate,

a plurality of pixels arranged in a matrix in a pixel region of the wiring substrate, and

a plurality of drivers that are disposed in the pixel region and select the plurality of pixels in units of two or more pixels,

wherein each of the pixels includes an optical element and a pixel circuit, the optical element that emits or receives light, and the pixel circuit that controls light emission or light reception of the optical element, and

one or more of the plurality of drivers are assigned to each pixel row or every plurality of pixel rows.

(7) The electronic apparatus according to (6), further including:

a supporting substrate that supports the plurality of mounting substrates; and

a control substrate that controls the plurality of mounting substrates,

wherein the plurality of mounting substrates are tiled on the supporting substrate,

each of the wiring substrates includes a plurality of electrode pads that are electrically coupled to the drivers and are exposed on a rear surface of the wiring substrate, one or more of the electrode pads being provided for each of the drivers, and

one or both of the supporting substrate and the control substrate are electrically coupled to the wiring substrates through the electrode pads.

This application claims the benefit of Japanese Priority Patent Application No. JP 2014-074842 filed with the Japan patent office on Mar. 31, 2014, the entire contents of which are incorporated herein by reference.