RAIL-TO-RAIL INPUT STAGE CIRCUIT AND OPERATIONAL AMPLIFIER

A rail-to-rail input stage circuit including a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first processing circuit, a second processing circuit, a first voltage adjustment circuit, and a second voltage adjustment circuit is provided. The first P-type transistor and the first N-type transistor are coupled to a first input terminal. The second P-type transistor and the second N-type transistor are coupled to a second input terminal. In response to the voltage of the first terminal being higher than a first threshold value, the first voltage adjustment circuit controls the operation of the first processing circuit. In response to the voltage of the first terminal being lower than a second threshold value, the second voltage adjustment circuit controls the operation of the second processing circuit.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of Taiwan Patent Application No. 112112981, filed on Apr. 7, 2023, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an input stage circuit, and, in particular, to the input stage circuit of an operational amplifier.

Description of the Related Art

The operational amplifier is a common element. To obtain a high swing in a full voltage range, the operational amplifier needs to process an input voltage in the common mode of a rail-to-rail circuit. When receiving different input voltages, the gain of the operational amplifier must be maintained at a fixed value to ensure the efficiency of the operational amplifier.

BRIEF SUMMARY OF THE INVENTION

In accordance with an embodiment of the disclosure, a rail-to-rail input stage circuit is coupled to an output stage circuit. The output stage circuit comprises an output terminal. The voltage level of the output terminal is related to the voltage levels of the first input terminal and the second input terminal. The rail-to-rail input stage circuit comprises a first current source, a second current source, a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first processing circuit, a second processing circuit, a first voltage adjustment circuit, and a second voltage adjustment circuit. The first current source provides a first current. The second current source provides a second current. The first P-type transistor is coupled between the first current source and the output stage circuit and is coupled to the first input terminal. The second P-type transistor is coupled between the first current source and the output stage circuit and is coupled to the second input terminal. The first N-type transistor is coupled between the second current source and the output stage circuit and is coupled to the first input terminal. The second N-type transistor is coupled between the second current source and the output stage circuit and is coupled to the second input terminal. The first processing circuit generates a third current based on a first control voltage in response to the voltage level of the first input terminal being higher than a first threshold value. The sum of currents passing through the first N-type transistor and the second N-type transistor is equal to the sum of the first current and the third current. The second processing circuit generates a fourth current based on a second control voltage in response to the voltage level of the first input terminal being lower than a second threshold value. The sum of currents passing through the first P-type transistor and the second P-type transistor is equal to the sum of the second current and the fourth current. The first voltage adjustment circuit adjusts the first control voltage in response to the voltage level of the first input terminal being higher than the first threshold value. The second voltage adjustment circuit adjusts the second control voltage in response to the voltage level of the first input terminal being lower than the second threshold value.

In accordance with another embodiment of the disclosure, an operational amplifier comprises an input stage circuit and an output stage circuit. The input stage circuit comprises a first current source, a second current source, a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a first processing circuit, a second processing circuit, a first voltage adjustment circuit, and a second voltage adjustment circuit. The first current source provides a first current. The second current source provides a second current. The first P-type transistor is coupled between the first current source and a first node and is coupled to a first input terminal. The second P-type transistor is coupled between the first current source and a second node and is coupled to a second input terminal. The first N-type transistor is coupled between the second current source and a third node and is coupled to the first input terminal. The second N-type transistor is coupled between the second current source and a fourth node and is coupled to the second input terminal. The first processing circuit generates a third current based on a first control voltage in response to the voltage level of the first input terminal being higher than a first threshold value. The sum of currents passing through the first transistor and the second N-type transistor is equal to the sum of the first current and the third current. The second processing circuit generates a fourth current based on a second control voltage in response to the voltage level of the first input terminal being lower than a second threshold value. The sum of currents passing through the first P-type transistor and the second P-type transistors is equal to the sum of the second current and the fourth current. The first voltage adjustment circuit adjusts the first control voltage in response to the voltage level of the first input terminal being higher than the first threshold value. The second voltage adjustment circuit adjusts the second control voltage in response to the voltage level of the first input terminal being lower than the second threshold value. The output stage circuit generates an output voltage based on the voltage levels of the first node, the second node, the third node, and the fourth node.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.

FIG.1is a schematic diagram of an exemplary embodiment of an operational amplifier according to various aspects of the present disclosure. The operational amplifier100is coupled between the power rails130and140and comprises an input stage circuit110and an output stage circuit120. The input stage circuit110and the output stage circuit120are coupled between the power rails130and140. In this embodiment, the power rail130receives an operation voltage VDD. The power rail140receives a ground voltage GND. In this case, the operation voltage VDD is higher than the ground voltage GND. For example, the operation voltage VDD is about 5V, and the ground voltage GND is about 0V.

The input stage circuit110is coupled between the power rails130and140. Therefore, the input stage circuit110is referred to as a rail-to-rail input stage circuit. In this embodiment, the input stage circuit110comprises current sources IB3and IB4, P-type transistors P1and P2, N-type transistors N1and N2, processing circuits150and160, and voltage adjustment circuits170and180.

The current source IB3provides a current Iref1. The current source IB4provides a current Iref2. In one embodiment, the current Iref1is about equal to the current Iref2. In this embodiment, the current source IB3is coupled between the power rail130and the source of the P-type transistor P1. The current source IB4is coupled between the source of the N-type transistor N1and the power rail140.

The P-type transistor P1is coupled between the current source IB3and the node ND1and coupled to the input terminal V+. In this embodiment, the source of the P-type transistor P1is coupled to the current source IB3. The drain of the P-type transistor P1is coupled to the node ND1. The gate of the P-type transistor P1is coupled to the input terminal V+.

The P-type transistor P2is coupled between the current source IB3and the node ND2and coupled to the input terminal V−. In this embodiment, the source of the P-type transistor P2is coupled to the current source IB3. The drain of the P-type transistor P2is coupled to the node ND2. The gate of the P-type transistor P2is coupled to the input terminal V−.

The N-type transistor N1is coupled between the current source IB4and the node ND3and coupled to the input terminal V+. In this embodiment, the source of the N-type transistor N1is coupled to the current source IB4. The drain of the N-type transistor N1is coupled to the node ND3. The gate of the N-type transistor N1is coupled to the input terminal V+.

The N-type transistor N2is coupled between the current source IB4and the node ND4and coupled to the input terminal V−. In this embodiment, the source of the N-type transistor N2is coupled to the current source IB4. The drain of the N-type transistor N2is coupled to the node ND4. The gate of the N-type transistor N2is coupled to the input terminal V−.

The processing circuit150is coupled to the current source IB3. When the voltage level of the input terminal V+ is gradually increased (e.g., from 0V to 5V), the P-type transistors P1and P2are gradually turned off. Therefore, the currents passing through the P-type transistors P1and P2are gradually reduced. When the voltage level of the input terminal V+ is higher than a first threshold value, a portion of the current Iref1passes through the processing circuit150. The processing circuit150generates a current Io1based on a control voltage CONP. In this embodiment, when the voltage level of the input terminal V+ is higher than a first threshold value, the sum of the currents passing through the N-type transistors N1and N2is equal to the sum of the currents Iref1and Io1. In one embodiment, current Io1is three times current Iref1. In some embodiments, the first threshold value is about the same as the difference between the voltage level of the power rail130and the threshold voltage of the P-type transistor P1.

The structure of processing circuit150is not limited in the present disclosure. In one embodiment, the processing circuit150comprises transistors T1˜T3. In this case, the transistor T1is a P-type transistor, and the transistors T2and T3are N-type transistors. In one embodiment, the transistor T1is referred to as a compensation transistor to compensate the effect caused by the P-type transistors P1and P2which are not turned on. Therefore, the gain (gm) of the operational amplifier100is maintained. As shown inFIG.1, the source of the transistor T1is coupled to the current source IB3. The drain of the transistor T1is coupled to the drain of the transistor T2. The gate of the transistor T1receives the control voltage CONP.

The drain and the gate of the transistor T2are coupled to the drain of the transistor T1. The source of the transistor T2is coupled to the power rail140. The gate of the transistor T3is coupled to the gate of the transistor T2. The drain of the transistor T3is coupled to the source of the N-type transistor N1. The source of the transistor T3is coupled to the power rail140. In this embodiment, the transistors T2and T3constitute a current mirror. When the current passing through the transistor T1enters the transistor T2, the current Io1(referred to as a third current) passes through the transistor T3. In one embodiment, the current Io1is three times current Iin1. In some embodiments, the size of the channel of the transistor T3is three times the size of the channel of the transistor T2.

The processing circuit160is coupled to the current source IB4. When the voltage level of the input terminal V− is gradually reduced (e.g., from 5V to 0V), the N-type transistors N1and N2are gradually turned off. When the voltage level of the input terminal V− is lower than a second threshold value, the processing circuit160generates a current Io2based on a control voltage CONN. In one embodiment, the second threshold value is lower than the first threshold value. In some embodiments, the second threshold value is about equal to the threshold voltage of the N-type transistor N1. In this embodiment, when the voltage level of the input terminal V1is lower than the second threshold value, the sum of the currents passing through the P-type transistors P1and P2is equal to the sum of the currents Iref2and Io2. In one embodiment, current Io2is three times current Iref2.

The structure of processing circuit160is not limited in the present disclosure. In one embodiment, the processing circuit160comprises transistors T5˜T7. In this case, the transistor T5is a N-type transistor, and the transistors T6and T7are P-type transistors. In one embodiment, the transistor T5is referred to as a compensation transistor to compensate the effect caused by the N-type transistors N1and N2which are not turned on. Therefore, the gain of the operational amplifier100is maintained. As shown inFIG.1, the source of the transistor T5is coupled to the current source IB4. The drain of the transistor T5is coupled to the drain of the transistor T6. The gate of the transistor T5receives the control voltage CONN.

The drain and the gate of the transistor T6are coupled to the drain of the transistor T5. The source of the transistor T6is coupled to the power rail130. The gate of the transistor T7is coupled to the gate of the transistor T6. The drain of the transistor T7is coupled to the source of the P-type transistor P1. The source of the transistor T7is coupled to the power rail130. In this embodiment, the transistors T6and T7constitute another current mirror. When the current Iin2passes through the transistor T6, the current Io2passes through the transistor T7.

The voltage adjustment circuit170provides and adjusts the control voltage CONP. When the voltage level of the input terminal V+ is higher than a first threshold value, the voltage adjustment circuit170adjusts the control voltage CONP based on the current Iin1passing through the transistor T1. In this embodiment, since the transistor T1is a P-type transistor, when the voltage adjustment circuit170reduces the control voltage CONP, more current passes through the transistor T1. Therefore, the current Io1quickly triples the current Iref1. The present disclosure does not limit how the voltage adjustment circuit170detects the current Iin1passing through the transistor T1. In one embodiment, the voltage adjustment circuit170is coupled to the gate of the transistor T2. When the voltage of the gate of the transistor T2is increased, this indicates that the P-type transistors P1and P2are gradually turned off such that a portion of current Iref1enters the transistor T1. Therefore, the voltage adjustment circuit170reduces the control voltage CONP to increase the current Iin1passing through the transistor T1.

The voltage adjustment circuit180adjusts the control voltage CONN based on the current Iin2which passes through the transistor T5. When the voltage level of the input terminal V− is lower than a second threshold value, the voltage adjustment circuit180adjusts the control voltage CONN such that the current Iin2quickly increases. Therefore, the current Io2can quickly triple the current Iref2. In one embodiment, the voltage adjustment circuit180is coupled to the gate of the transistor T6. When the voltage of the gate of the transistor T6is increased, this indicates that the N-type transistors N1and N2are gradually turned off. Therefore, the voltage adjustment circuit180increases the control voltage CONN to increase the current Iin2passing through the transistor T5.

In some embodiments, when the voltage adjustment circuit170adjusts the voltage (i.e., the control voltage CONP) of the gate of the transistor T1, the voltage adjustment circuit180stops adjusting the voltage (i.e., the control voltage CONN) of the gate of the transistor T5. In this case, when the voltage adjustment circuit180adjusts the voltage (i.e., the control voltage CONN) of the gate of the transistor T5, the voltage adjustment circuit170stops adjusting the voltage (i.e., the control voltage CONP) of the gate of the transistor T1.

The output stage circuit120generates an output voltage Vo based on the voltage levels of the nodes ND1˜ND4. The structure of output stage circuit120is not limited in the present disclosure. In one embodiment, the output stage circuit120comprises output transistors TO1˜TO6and current sources IB1and IB2. The output transistors TO1, TO2, TO4, and TO5are P-type transistors, and the output transistors TO3and TO6are N-type transistors.

The source of the output transistor TO1is coupled to the power rail130. The gate of the output transistor TO1is coupled to the gate of the output transistor TO4. The drain of the output transistor TO1is coupled to the node ND3. The source of the output transistor TO2is coupled to the drain of the output transistor TO1. The gate of the output transistor TO2is coupled to the gate of the output transistor TO5. The drain of the output transistor TO2is coupled to the gate of the output transistor TO1. The drain of the output transistor TO3is coupled to the drain of the output transistor TO2. The gate of the output transistor TO3is coupled to the gate of the output transistor TO6. The source of the output transistor TO3is coupled to the node ND2. The current source IB1is coupled between the source of the output transistor TO3and the power rail130.

The source of the output transistor TO4is coupled to the power rail130. The gate of the output transistor TO4is coupled to the gate of the output transistor TO1. The drain of the output transistor TO4is coupled to the node ND4. The source of the output transistor TO5is coupled to the drain of the output transistor TO4. The gate of the output transistor TO5is coupled to the gate of the output transistor TO2. The drain of the output transistor TO5is coupled to the node ND5. The node ND5is served as an output terminal to provide the output voltage Vo. The drain of the output transistor TO6is coupled to the drain of the output transistor TO5. The gate of the output transistor TO6is coupled to the gate of the output transistor TO3. The source of the output transistor TO6is coupled to the node ND1. The current source IB2is coupled to the source of the output transistor TO6and the power rail140.

FIG.2is a schematic diagram of an exemplary embodiment of the voltage adjustment circuit170according to various aspects of the present disclosure. The voltage adjustment circuit170comprises an impedance element RP and a transistor T4. The impedance element RP is coupled between a voltage source VB3and the gate of the transistor T1and configured to provide the control voltage CONP. In one embodiment, the impedance element RP is a resistor. The transistor T4is serially coupled to the impedance element RP and coupled to the gate of the transistor T2. In this embodiment, the transistor T4is a N-type transistor. The gate of the transistor T4is coupled to the gate of the transistor T2. The drain of the transistor T4is coupled to the gate of the transistor T1and the impedance element RP. The source of the transistor T4is coupled to the power rail140.

In some embodiments, the transistors T2and T4constitute a current mirror. In this case, when the current Iin1enters the transistor T2, the transistor T4is turned on. At this time, the current passing through the transistor T4is about equal to the current Iin1. The impedance element RP generates a voltage drop to reduce the control voltage CONP. Therefore, the current Iin1passing through the transistor T1is increased.

For example, assume that the voltage level provided by the voltage source VB3is 4V, the resistance of the impedance element RP is 40 KΩ, and the current Iin1is 10 uA. In this case, when the current Iin1enters the transistor T2, the current passing through the impedance element RP is equal to 10 uA. Therefore, the voltage drop of the impedance element RP is about 400 mA (40K×10u) so that the control voltage CONP reduces to 3.6V.

In one embodiment, the voltage level of the voltage source VB3is equal to the first threshold value. In this case, when the voltage level of the input terminal V+ is increased and higher than the voltage level of the voltage source VB3, the current Iin1enters the transistor T2. Therefore, the impedance element RP generates a voltage drop to reduce the control voltage CONP.

FIG.3is a schematic diagram of an exemplary embodiment of the voltage adjustment circuit180according to various aspects of the present disclosure. The voltage adjustment circuit180comprises an impedance element RN and a transistor T8. The impedance element RN is coupled between a voltage source VB4and the gate of the transistor T5and configured to provide the control voltage CONN. The voltage level of the voltage source VB4may be lower than the voltage level of the voltage source VB3. In one embodiment, the impedance element RN is a resistor. In this case, the resistance of the impedance element RN is similar to the resistance of the impedance element RP.

The transistor T8is serially coupled to the impedance element RN and coupled to the gate of the transistor T6. In this embodiment, the transistor T8is a P-type transistor. The gate of the transistor T8is coupled to the gate of the transistor T6. The drain of the transistor T8is coupled to the gate of the transistor T5and the impedance element RN. The source of the transistor T8is coupled to the power rail130.

In some embodiments, the transistors T6and T8constitute a current mirror. In this case, the current passing through the transistor T8is about equal to the current Iin2of the transistor T6. When a current enters the transistor T8, the impedance element RN causes a voltage rise. Therefore, the control voltage CONN is increased so that the current Iin2increases. In one embodiment, the second threshold value is equal to the voltage level of the voltage source VB4.

FIG.4is a schematic diagram of an exemplary embodiment of an input stage circuit according to various aspects of the present disclosure. Some elements which are shown inFIG.1are omitted. The input stage circuit comprises a control circuit190, switches MPS and MNS. The switch MPS is coupled between the impedance element RP and the transistor T4of the voltage adjustment circuit170. In this embodiment, the switch MPS is a P-type transistor T9. The source of the P-type transistor T9is coupled to the impedance element RP and the gate of the transistor T1. The drain of the P-type transistor T9is coupled to the drain of the transistor T4. The gate of the P-type transistor T9receives a switching signal SWP.

The switch MNS is coupled between the impedance element RN and the transistor T8of the voltage adjustment circuit180. In this embodiment, the switch MNS is a N-type transistor T10. The source of the N-type transistor T10is coupled to the impedance element RN and the gate of the transistor T5. The drain of the N-type transistor T10is coupled to the drain of the transistor T8. The gate of the N-type transistor T10receives a.

The control circuit190controls the switching signals SWN and SWP to prevent the voltage adjustment circuits170and180from being turned on at the same time. For example, when a current (e.g., Iin1) passes through the transistor T1, the control circuit190turns on the switch MPS and turns off the switch MNS. However, a current (e.g., Iin2) passes through the transistor T5, the control circuit190turns on the switch MNS and turns off the switch MPS. In other embodiments, the control circuit190may turn off the switches MNS and MPS simultaneously.

The structure of control circuit190is not limited in the present disclosure. In this embodiment, the control circuit190comprises transistors T11˜T14. The transistors T11and T12are N-type transistors, and the transistors T13and T14are P-type transistors. In this case, the gate of the transistor T11is coupled to the gate of the transistor T4. The source of the transistor T11is coupled to the power rail140. The drain of the transistor T11is coupled to the gate of the transistor T9.

In one embodiment, the transistors T11and T2constitute a current mirror. When the current Iin1enters the transistor T2, the transistor T11is turned on so that the level of the switching signal SWP is equal to the voltage level (e.g., 0V) of the power rail140. Therefore, the transistor T9is turned on. Since the impedance element RP causes a voltage drop so that the current passing through the transistor T1is increased and the current Io1quickly reaches the target value (e.g., three times the current Iref1).

The gate of the transistor T12is coupled to the gate of the transistor T4. The source of the transistor T12is coupled to the power rail140. The drain of the transistor T12is coupled to the gate of the transistor T10. In one embodiment, the transistors T12and T2constitute a current mirror. When the current Iin1enters the transistor T2, the transistor T12is turned on so that the level of the switching signal SWN is equal to the voltage level (e.g., 0V) of the power rail140. Therefore, the transistor T10is turned off so that the transistor T5is turned off.

The gate of the transistor T13is coupled to the gate of the transistor T8. The source of the transistor T13is coupled to the power rail130. The drain of the transistor T13is coupled to the gate of the transistor T9. In one embodiment, the transistors T13and T6constitute a current mirror. When the current Iin2enters the transistor T6, the transistor T13is turned on so that the level of the switching signal SWP is equal to the voltage level (e.g., 5V) of the power rail130. Therefore, the transistor T19is turned off.

The gate of the transistor T14is coupled to the gate of the transistor T8. The source of the transistor T14is coupled to the power rail130. The drain of the transistor T14is coupled to the gate of the transistor T10. In one embodiment, the transistors T14and T6constitute a current mirror. When the current Iin2enters the transistor T6, the transistor T14is turned on so that the level of the switching signal SWN is equal to the voltage level (e.g., 5V) of the power rail130. Therefore, the transistor T10is turned on. Since the impedance element RN causes a voltage rise so that the current passing through the transistor T5is increased and the current Io2quickly reaches the target value (e.g., three times the current Iref2).

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.