Multi-protocol bus circuit

A multi-protocol bus circuit is provided. The multi-protocol bus circuit includes multiple master circuits each configured to communicate a respective master bus command(s) via a respective one of multiple master buses based on a respective one of multiple master bus protocols, and a slave circuit(s) configured to communicate a slave bus command(s) via a slave bus based on a slave bus protocol that is different from any of the master bus protocols. To enable bidirectional bus communications between the master circuits and the slave circuit(s), the multi-protocol bus circuit further includes a multi-protocol bridge circuit configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols. As a result, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal impact on cost and/or footprint.

FIELD OF DISCLOSURE

The technology of the disclosure relates generally to a hybrid bus apparatus incorporating heterogeneous communication buses.

BACKGROUND

Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

The redefined user experience requires higher data rates offered by wireless communication technologies, such as Wi-Fi, long-term evolution (LTE), and fifth-generation new-radio (5G-NR). To achieve the higher data rates in a mobile communication device, a radio frequency (RF) signal(s) may first be modulated by a transceiver circuit(s) based on a selected modulation and coding scheme (MCS) and then amplified by a power amplifier(s) prior to being radiated from an antenna(s). In many wireless communication devices, the power amplifier(s) and the antenna(s) are typically located in an RF front-end (RFFE) circuit communicatively coupled to the transceiver circuit(s) via an RFFE bus based on an RFFE protocol as defined in the MIPI® alliance specification for radio frequency front-end control interface, version 2.1 (hereinafter referred to as “RFFE specification”).

In this regard,FIG.1is a schematic diagram of an exemplary RFFE bus apparatus10as defined in the RFFE specification. The RFFE bus apparatus10includes an RFFE master12coupled to a number of RFFE slaves14(1)-14(M) over an RFFE bus16. According to the RFFE specification, the RFFE bus16is a two-wire serial bus that includes a data line18and a clock line20for communicating a bidirectional data signal SDATA and a clock signal SCLK, respectively. The RFFE bus16operates at a first data rate.

However, not all communications require a two-wire serial bus like the RFFE bus16. In some cases, a single-wire serial bus may be sufficient or even desired for carrying out certain types of communications between circuits. In this regard,FIG.2is a schematic diagram of an exemplary conventional hybrid bus apparatus22in which a single-wire bus (SuBUS) bridge circuit24is configured to bridge communications between the RFFE master12inFIG.1with one or more SuBUS slaves26(1)-26(N). Common elements betweenFIGS.1and2are shown therein with common element numbers and will not be re-described herein.

The SuBUS bridge circuit24is coupled to the SuBUS slaves26(1)-26(N) over a SuBUS28having a single data wire30. Accordingly, the SuBUS28is configured to operate at a second data rate that can be faster or slower than the first data rate of the RFFE bus16. The SuBUS bridge circuit24may be coupled to the RFFE master12via the RFFE bus16. In this regard, the SuBUS bridge circuit24and the SuBUS slaves26(1)-26(N) are also RFFE slaves, such as the RFFE slaves14(1)-14(M) coupled to the RFFE master12in the RFFE bus apparatus10ofFIG.1.

Notably, the SuBUS28differs from the RFFE bus16in several aspects. First, the RFFE bus16includes the data line18and the clock line20, while the SuBUS28includes only the single data wire30. Second, the SuBUS bridge circuit24is configured to communicate with the SuBUS slaves26(1)-26(N) based on SuBUS command sequences, which may be compatible but different from the RFFE command sequences communicated over the RFFE bus16. In this regard, the SuBUS bridge circuit24may perform command conversion between the RFFE command sequences and the SuBUS command sequences to facilitate communications between the RFFE bus16and the SuBUS28. Third, the RFFE bus16may be configured to operate at the first data rate and the SuBUS28may be configured to operate at the second data rate, which is different from the first data rate. In this regard, the SuBUS bridge circuit24may buffer SuBUS data payloads prior to communicating over the RFFE bus16to help compensate for a difference between the first data rate and the second data rate.

Besides the power amplifier(s) and the antenna(s), the SuBUS slaves26(1)-26(N) can also include other types of active or passive circuits (e.g., audio circuits) that need to communicate with other types of masters via the SuBUS28. Given that the SuBUS bridge circuit24in the conventional hybrid bus apparatus22is only capable of bridging the SuBUS slaves26(1)-26(N) with a single RFFE master12based exclusively on the RFFE protocol, it may be necessary to employ additional SuBUS bridge circuits to bridge the SuBUS slaves26(1)-26(N) to additional types of masters. As a result, the conventional hybrid bus apparatus22may occupy a larger footprint and/or become more expensive.

SUMMARY

Aspects disclosed in the detailed description include a multi-protocol bus circuit. The multi-protocol bus circuit includes multiple master circuits each configured to communicate a respective master bus command(s) via a respective one of multiple master buses based on a respective one of multiple master bus protocols, and a slave circuit(s) configured to communicate a slave bus command(s) via a slave bus based on a slave bus protocol that is different from any of the master bus protocols. To enable bidirectional bus communications between the master circuits and the slave circuit(s), the multi-protocol bus circuit further includes a multi-protocol bridge circuit configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols. As a result, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal impact on cost and/or footprint.

In one aspect, a multi-protocol bus circuit is provided. The multi-protocol bus circuit includes multiple master circuits each coupled to a respective on of multiple master buses. The multiple master circuits are each configured to communicate a respective one or more master bus commands based on a respective one of multiple master bus protocols. Each of the master bus protocols is different from at least another one of the master bus protocols. The multi-protocol bus circuit also includes one or more slave circuits each coupled to a slave bus. The slave circuits are each configured to communicate a respective one or more slave bus commands based on a slave bus protocol different from any of the master bus protocols. The multi-protocol bus circuit also includes a multi-protocol bridge circuit coupled to the master buses and the slave bus. The multi-protocol bridge circuit is configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols.

In another aspect, a multi-protocol bridge circuit is provided. The multi-protocol bridge circuit includes multiple master bus ports each coupled to a respective one of multiple master circuits configured to communicate a respective one or more master bus commands via a respective one of multiple master buses based on a respective one of multiple master bus protocols. Each of the master bus protocols is different from at least another one of the master bus protocols. The multi-protocol bridge circuit also includes a slave bus port coupled to one or more slave circuits. The slave circuits are each configured to communicate a respective one or more slave bus commands based on a slave bus protocol different from any of the master bus protocols. The multi-protocol bridge circuit also includes a control circuit. The control circuit is configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols.

DETAILED DESCRIPTION

Aspects disclosed in the detailed description include a multi-protocol bus circuit. The multi-protocol bus circuit includes multiple master circuits each configured to communicate a respective master bus command(s) via a respective one of multiple master buses based on a respective one of multiple master bus protocols, and a slave circuit(s) configured to communicate a slave bus command(s) via a slave bus based on a slave bus protocol that is different from any of the master bus protocols. To enable bidirectional bus communications between the master circuits and the slave circuit(s), the multi-protocol bus circuit further includes a multi-protocol bridge circuit configured to perform a bidirectional conversion between the slave bus protocol and each of the master bus protocols. As a result, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal impact on cost and/or footprint.

In this regard,FIG.3is a schematic diagram of an exemplary multi-protocol bus circuit32configured according to embodiments of the present disclosure to support bidirectional bus communications between multiple master circuits34(1)-34(M) and one or more slave circuits36(1)-36(N) based on heterogeneous bus protocols. Herein, the bidirectional bus communications refer to bus communications originated from any of the master circuits34(1)-34(M) and destined to any of the slave circuits36(1)-36(N) (a.k.a. forward communication), and bus communications originated from any of the slave circuits36(1)-36(N) and destined to any of the master circuits34(1)-34(M) (a.k.a. reverse communication).

The master circuits34(1)-34(M) are coupled to multiple master buses38(1)-38(M), respectively. Each of the master circuits34(1)-34(M) is configured to communicate a respective one or more master bus commands40(1)-40(K) based on a respective one of multiple master bus protocols PM1-PMM. In some embodiments, all of the master bus protocols PM1-PMMare different bus protocols. In this regard, each of the master bus protocols PM1-PMMis different from any other one of the master bus protocols PM1-PMM. In some other embodiments, only a subset of the master bus protocols PM1-PMMare different bus protocols. In this regard, each of the master bus protocols PM1-PMMis different from at least another one of the master bus protocols PM1-PMM.

The slave circuits36(1)-36(N) are each coupled to a slave bus42and configured to communicate a respective one or more slave bus commands44(1)-44(L) based on a slave bus protocol PSthat is different from any of the master bus protocols PM1-PMM. In a non-limiting example, the slave bus42is a single-wire bus (SuBUS) that is functionally equivalent to the SuBUS28inFIG.2. Accordingly, each of the slave circuits36(1)-36(N) can be functionally equivalent to the SuBUS slaves26(1)-26(N) inFIG.2.

To enable the bidirectional bus communications based on the heterogeneous bus protocols, the multi-protocol bus circuit is further configured to include a multi-protocol bridge circuit46. In an embodiment, the multi-protocol bridge circuit46includes multiple master ports48(1)-48(M), each coupled to a respective one of the master buses38(1)-38(M). The multi-protocol bridge circuit46also includes a slave bus port50coupled to the slave bus42. As discussed in further detail below, the multi-protocol bridge circuit46can be configured to perform a bidirectional conversion between the slave bus protocol PSand each of the master bus protocols PM1-PMM. Herein, the bidirectional conversion refers to converting the master bus commands40(1)-40(K) from any of the master bus protocols PM1-PMMinto the slave bus commands44(1)-44(L) in accordance with the slave bus protocol PS, and vice versa. By bridging the master circuits34(1)-34(M) with the slave circuits36(1)-36(N) using the multi-protocol bridge circuit46, it is possible to support bidirectional bus communications based on heterogeneous bus protocols with minimal cost and/or footprint impact on the multi-protocol bus circuit32.

In an embodiment, the multi-protocol bridge circuit46includes a control circuit52, which can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. To enable the forward communication, the control circuit52can be configured to receive the respective master bus commands40(1)-40(K) from any of the master circuits34(1)-34(M) via a respective one of the master ports48(1)-48(M). Notably, the respective master bus commands40(1)-40(K) may be destined to any of the slave circuits36(1)-36(N) or to the multi-protocol bridge circuit46itself. In this regard, the control circuit52may be configured to first determine whether the respective master bus commands40(1)-40(K) are destined to at least one of the slave circuits36(1)-36(N). If the control circuit52determines that the respective master bus commands40(1)-40(K) are indeed destined to any of the slave circuits36(1)-36(N), the control circuit52will then convert the respective master bus commands40(1)-40(K) into the respective slave bus commands44(1)-44(L) and provide the respective slave bus commands44(1)-44(L) to any of the slave circuits36(1)-36(N) to which the respective master bus commands40(1)-40(K) are destined.

To enable the reverse communication, the control circuit52is configured to receive the respective slave bus commands44(1)-44(L) from any of the one or more slave circuits36(1)-36(N) via the slave bus port50. Notably, the respective slave bus commands44(1)-44(L) may be destined to any of the master circuits34(1)-34(M) or to the multi-protocol bridge circuit46itself. In this regard, the control circuit52may be configured to first determine whether the respective slave bus commands44(1)-44(L) are destined to at least one of the master circuits34(1)-34(M). If the control circuit52determines that the respective slave bus commands44(1)-44(L) are indeed destined to any of the master circuits34(1)-34(M), the control circuit52will then convert the respective slave bus commands44(1)-44(L) into the respective master bus commands40(1)-40(M) and provide the respective master bus commands40(1)-40(M) to any of the master circuits34(1)-34(N) to which the respective slave bus commands44(1)-44(L) are destined.

In an embodiment, the control circuit52can include at least one encoder-decoder circuit54(denoted as “CODEC”). Specifically, the encoder-decoder circuit54can be configured to convert the respective master bus commands40(1)-40(M) into the respective slave bus commands44(1)-44(L) in the forward communication, and to convert the respective slave bus commands44(1)-44(L) into the respective master bus commands40(1)-40K) in the reverse communication.

In an embodiment, the multi-protocol bridge circuit46may simultaneously receive the respective master bus commands40(1)-40(M) from more than one of the master circuits34(1)-34(M). In this regard, upon converting the respective master bus commands40(1)-40(M) received from each of the master circuits34(1)-34(M) into the respective slave bus commands44(1)-44(L), the control circuit52needs to determine an order for providing the respective slave bus commands44(1)-44(L) to some or all of the slave circuits36(1)-36(N).

For example, the control circuit52can provide the respective slave bus commands44(1)-44(L), which are converted from the respective master bus commands40(1)-40(M) received simultaneously from more than one of the master circuits34(1)-34(M), to any of the slave circuits36(1)-36(N) based on a predefined priority of the master circuits34(1)-34(M). In this regard, the respective slave bus commands44(1)-44(L) converted from the respective master bus commands40(1)-40(M) received from a higher priority one of the master circuits34(1)-34(M) will be sent to the slave bus port50before the respective slave bus commands44(1)-44(L) converted from the respective master bus commands40(1)-40(M) are received from a lower priority one of the master circuits34(1)-34(M).

In a non-limiting example, the control circuit52can include a data buffer56that functions as a first-in first-out (FIFO) queue. In this regard, the control circuit52may be configured to enqueue the respective slave bus commands44(1)-44(L) based on the predefined priority of the master circuits34(1)-34(M). In other words, the control circuit52will enqueue the respective slave bus commands44(1)-44(L) that are converted from the respective master bus commands40(1)-40(M) received from the higher priority one of the master circuits34(1)-34(M) in the data buffer56before enqueuing the respective slave bus commands44(1)-44(L) that are converted from the respective master bus commands40(1)-40(M) received from the lower priority one of the master circuits34(1)-34(M).

In an embodiment, the data buffer56may be utilized only for the forward communication. As for the reverse communication, the respective slave bus commands44(1)-44(L) received from any of the slave circuits36(1)-36(N) are directly routed to the encoder-decoder circuit54from the slave bus port50. Accordingly, the encoder-decoder circuit54is configured to convert the respective slave bus commands44(1)-44(L) destined to any of the master circuits34(1)-34(M) on a first come first serve basis.

In an embodiment, the multi-protocol bridge circuit46can include a storage circuit58(denoted as “REGMAP”), which can be a register bank, or a flash storage circuit, as an example. The storage circuit58may be programmed to store the predefined priority among the master circuits34(1)-34(M).

As previously mentioned, the respective master bus commands40(1)-40(K) originated from any of the master circuits34(1)-34(M) can be destined to the multi-protocol bridge circuit46, as opposed to any of the slave circuits36(1)-36(N). In this regard, the respective master bus commands40(1)-40(K), which are originated from any of the master circuits34(1)-34(M) and destined to the multi-protocol bridge circuit46, may be utilized to program (dynamically or statically) the predefined priority in the storage circuit58.

In an embodiment, each of the master circuits34(1)-34(M) may be configured to communicate the respective master bus commands40(1)-40(K) by asserting a respective one of multiple master bus voltages VM1-VMMon the respective one of the master buses38(1)-38(M). In contrast, each of the slave circuits36(1)-36(N) is configured to communicate the respective slave bus commands44(1)-44(L) based on a slave bus voltage VSthat is different from at least one of the master bus voltages VM1-VMM. Notably, any mismatch between the master bus voltages VM1-VMMand the slave bus voltage VScan cause potential damage to the slave circuits36(1)-36(N), particularly when the slave bus voltage VSis lower than any mismatched master bus voltage among the master bus voltages VM1-VMM.

In this regard, the multi-protocol bridge circuit46can be further configured to perform a bidirectional voltage conversion between the slave bus voltage VSand any of the master bus voltages VM1-VMM. In a non-limiting example, the multi-protocol bridge circuit46can further include multiple master bus interface circuits60(1)-60(M), each coupled to a respective one of the master ports48(1)-48(M). More specifically, each of the master bus interface circuits60(1)-60(M) can include a respective voltage conversion circuit62, which can be a capacitor-based or an inductor-based buck-boost converter, or a level shifter, as an example, for carrying out the bidirectional voltage conversion between the slave bus voltage VSand any of the master bus voltage VM1-VMM.

As a non-limiting example, the multi-protocol bridge circuit46can include a radio-frequency front-end (RFFE) master circuit (e.g., the master circuit34(1)) and an inter-integrated circuit (I2C) master circuit (e.g., the master circuit34(M)). In this regard, the RFFE master circuit34(1) is configured to communicate one or more RFFE bus commands40(1)-40(K) over the RFFE bus38(1) based on an RFFE bus protocol and by asserting a respective one of the master bus voltage VM1-VMMon the RFFE bus38(1), and the I2C master circuit34(M) is configured to communicate one or more I2C bus commands40(1)-40(K) over the I2C bus38(M) based on a I2C bus protocol and by asserting a respective one of the master bus voltage VM1-VMMon the I2C bus38(M). Each of the slave circuits36(1)-36(N), on the other hand, is a SuBUS slave circuit configured to communicate the respective SuBUS slave bus commands44(1)-44(N) over the SuBUS42based on the SuBUS protocol.

Accordingly, the multi-protocol bridge circuit46is configured to perform the bidirectional conversion between the RFFE bus protocol, the I2C bus protocol, and the SuBUS bus protocol. In addition, the multi-protocol bridge circuit46may also perform the bidirectional voltage conversion should there be a mismatch between the RFFE master bus voltage VM1, the I2C master bus voltage VMM, and the SuBUS slave bus voltage VS.

The multi-protocol bridge circuit46can further include a second RFFE master circuit (e.g., the master circuit34(2)), which is configured to communicate a respective one or more RFFE bus commands40(1)-40(K) over a respective one of the master buses (e.g., the master bus38(2)) based on the RFFE bus protocol. However, the second RFFE master circuit is configured to assert a different master bus voltage from the respective master bus voltage asserted by the RFFE master circuit38(1).