Semiconductor process

A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor process.

2. Description of Related Art

With advancement of technologies, the level of integration of electronic devices tends to be raised, so as to comply with current demands for lightness, thinness, shortness, and smallness. In order to improve the level of integration, not only dimensions of semiconductor devices can be reduced, but also the distance between semiconductor components can be decreased. Nevertheless, either the size reduction of the semiconductor devices or the decrease in the distance between the semiconductor components may result in certain issues.

In general, in the fabrication of the gates, an ion implantation process is applied to define a spacer oxide layer or a gate oxide layer. For example, after an opening is formed in a material layer, the surface of the opening is doped by an ion implantation process. Then, a converting process (i.e. an oxidation process) is performed on the surface of the opening to form a converting layer (i.e. an oxide layer) thereon, and a conductive material is filled in the opening to form a gate. However, the scattering effect is likely to occur in the ion implantation process due to the decrease of the dimensions of the opening, and therefore the doping profile is difficult to control. That is, in the side wall of the opening fabricated as described above, the doping depth of an upper portion and a lower portion is different. Therefore, the converting layer subsequently formed on the side wall of the opening may have non-uniform thickness, and the insulation effect of the converting layer is negatively affected.

SUMMARY OF THE INVENTION

The invention is directed to a semiconductor process which can form a converting layer with superior insulation effect on a surface of the opening.

The invention provides a semiconductor fabricating process. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. By using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening of the mask layer, and the side wall is covered by the mask layer. By using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion of the second opening through the first opening. A conversion process is performed on the substrate, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.

According to an embodiment of the invention, the dry etching process includes an in-situ widening etching process.

According to an embodiment of the invention, the side wall of the second opening is covered by the mask layer during the vertical ion implantation process.

According to an embodiment of the invention, a plurality of conductive patterns is formed in the substrate before the mask layer is formed, and the second opening is formed between the conductive patterns.

According to an embodiment of the invention, the mask layer is removed before the converting process.

According to an embodiment of the invention, a conductive layer is formed in the second opening after the converting process.

According to an embodiment of the invention, the first opening includes a slit.

According to an embodiment of the invention, the converting layer on the side wall substantially has an uniform thickness.

According to an embodiment of the invention, the vertical ion implantation process includes an n-type ion implantation process.

According to one embodiment of the present invention, the converting process includes an oxidation process.

Based on the above, in the semiconductor process of the invention, the mask layer used to form the opening covers the side wall of the formed opening. Thus, the mask layer is also used as a mask in the vertical ion implantation process, so as to implant the bottom portion of the opening rather than the side wall of the opening. As such, the thickness of the converting layer subsequently formed on the side wall of the opening is larger than the thickness of the converting layer subsequently formed on the bottom portion of the opening. Therefore, the converting layer on the side wall of the opening provides a superior insulation effect.

DESCRIPTION OF EMBODIMENTS

FIG. 1AtoFIG. 1Eare schematic top views illustrating a semiconductor process according to an embodiment of the invention.FIG. 2AtoFIG. 2Eare schematic cross-sectional views taken along a line I-I′ depicted inFIG. 1AtoFIG. 1E.FIG. 3AtoFIG. 3Eare schematic cross-sectional views taken along a line II-II′ depicted inFIG. 1AtoFIG. 1E. With reference toFIG. 1A,FIG. 2A, andFIG. 3A, a mask layer120is formed on the substrate100, wherein the mask layer120has a first opening122exposing a portion of the substrate100. In this embodiment, a plurality of conductive patterns110is formed in the substrate100before forming the mask layer120, and the first opening122of the mask layer120exposes the substrate100between the conductive patterns110, for example. The first opening122is a slit, for example. A dielectric layer112is formed on a surface of the substrate100and between a portion of the conductive patterns110and the substrate100, and dielectric patterns114are formed between a portion of the conductive patterns110and the substrate100, for example, as shown inFIG. 2AandFIG. 3A. In this embodiment, the substrate100is, for example, a silicon substrate. The mask layer120can include carbonate. The conductive patterns110are capacitor pillars, for example. A material of the conductive patterns110is polysilicon, for example. A material of the dielectric layer112is silicon oxide, and a material of the dielectric patterns114is spin-on dielectric (SOD), for example.

With reference toFIG. 1B,FIG. 2B, andFIG. 3B, then, by using the mask layer120as a mask, a dry etching process is performed on the substrate100to form a second opening130therein. The second opening130has a bottom portion132and a side wall134extending upwards and outwards from the bottom portion132, wherein the bottom portion132is exposed by the first opening122of the mask layer120, and the side wall134is covered by the mask layer120. In this embodiment, the mask layer120includes a main body and the first openings disposed in the main body, the side wall134is covered by the main body of the mask layer120, and the bottom portion132is exposed by the first opening122. Here, the dry etching process is, for example, an in-situ widening etching process or others. In other words, the substrate100is etched vertically and horizontally by the dry etching process through the first opening122of the mask layer120, so as to form a second opening130having a width larger than that of the first opening122. As such, the bottom portion132of the second opening130is exposed by the first opening122of the mask layer120, while the side wall134of the second opening130is covered by the main body of the mask layer120. In detail, the bottom portion132of the second opening130exposes a portion of the substrate100, and the side wall134of the second opening130exposes a portion of the substrate100surrounding the upper portions of the conductive patterns110, a portion of the dielectric layer112surrounding the top portions of the conductive patterns110, and a portion of the dielectric patterns114surrounding the upper portions of the conductive patterns110, for example. In this embodiment, when a material of the substrate100includes silicon, the in-situ widening etching process is performed by using the etching gas with an increased ratio of hydrogen bromide (HBr) and a reduced ratio of oxide, such as the etching gas including 100˜200 sccm HBr/20˜40 sccm Cl2/0˜15 sccm CF4/0˜15 sccm NF3/0˜10 sccm O2.

With reference toFIG. 1C,FIG. 2C, andFIG. 3C, after that, by using the mask layer120as a mask, a vertical ion implantation process DP is performed on the bottom portion132of the second opening130through the first opening122, so as to form a doped bottom portion132aand keep the side wall134undoped. In this embodiment, the vertical ion implantation process DP is an n-type ion implantation process, and the doping ions are nitrogen ions, for example. In detail, the side wall134of the second opening130is covered by the main body of the mask layer120, and thus only the substrate100at the bottom portion132, exposed by the first opening122of the mask layer120, is doped by the vertical ion implantation process DP. Contrarily, the material layers including the substrate100, the dielectric layer112, and the dielectric patterns114at the side wall134, covered by the main body of the mask layer120, are not doped. In other words, by utilizing the mask layer120and the vertical ion implantation process DP cooperatively, a desired doping profile is easily obtained, and not affected by the scattering effect. Besides, the non-uniformity of implantation on the side wall of the opening is improved.

With reference toFIG. 1D,FIG. 2D, andFIG. 3D, the mask layer120is removed after the vertical ion implantation process DP. After that, a conversion process CP is performed on the substrate100, so as to form converting layers142,144on the side wall134and the bottom portion132aof the second opening130, wherein a thickness t1of the converting layer144on the side wall134is larger than a thickness t2of the converting layer142on the bottom portion132a. In this embodiment, the conversion process CP is an oxidation process, and a material of the converting layers142,144is oxide, for example. Notes that the substrate100at the bottom portion132of the second opening130is doped to form a doped bottom portion132aand the material layers at the side wall134of the second opening130is undoped in the preceding step, and thus the thickness t1of the converting layer144formed on the side wall134is consequentially larger than a thickness t2of the converting layer142formed on the bottom portion132ain the conversion process CP. Besides, since the material layers at the side wall134of the second opening130is substantially undoped, the thickness t1of the converting layer144formed on the side wall134of the second opening130is substantially uniform.

With reference toFIG. 1E,FIG. 2E, andFIG. 3E, afterwards, a conductive layer150is formed on the substrate100, wherein the conductive layer150is filled in the second opening130. In this embodiment, the conductive layer150is a gate layer, and a material of the conductive layer150is polysilicon, for example. Particularly, in this embodiment, the conductive layer150and the conductive patterns110are electrically insulated from each other by the converting layer142and the converting layer144which has a substantially uniform thickness.

In the semiconductor process of the present embodiment, by utilizing the in-situ widening etching process, the side wall134of the formed opening130is covered by the mask layer120which is used to form the opening130. Then, the vertical ion implantation process DP is performed on the bottom portion132of the opening130by using the same mask layer120as a mask. Since the side wall134of the opening130is covered by the mask layer120, the side wall134of the opening130is substantially kept undoped. As such, the thickness t1of the converting layer144subsequently formed on the side wall134of the opening130is consequentially larger than the thickness t2of the converting layer142subsequently formed on the bottom portion132of the opening130, and the thickness t1of the converting layer144formed on the side wall134of the opening130which is undoped is substantially uniform. Therefore, the converting layer144disposed on the side wall134of the opening130provides a superior insulation effect.

In this embodiment, by using the mask layer as a mask to form the opening and perform the implantation process to cover the side wall of the opening, the bottom portion of the opening is doped while the side wall of the opening is undoped. Namely, in the semiconductor process of the embodiment, it is not required to prepare another mask layer or other additional tools to cover the side wall of the opening in the implantation process, and thus the overall process is simplified and the cost of the semiconductor process is reduced. Moreover, the converting layer with an increased thickness is uniformly formed on the side wall of the opening, and therefore the converting layer provides a superior insulation effect between the conductive layer subsequently formed in the opening and the conductive patterns disposed between the openings. Accordingly, the characteristics of the semiconductor device are improved.

It should be noted that in the embodiment, the opening is formed in the substrate having complex structure (i.e. conductive patterns110, dielectric layer112, and dielectric patterns114) as shown inFIG. 2AandFIG. 3A, but the invention is not limited thereto. In other words, the invention can be applied to other semiconductor processes to form an opening having a bottom portion and a side wall which have different doping properties.

In light of the foregoing, in the semiconductor process of the invention, the mask layer used to form the opening covers the side wall of the formed opening. Thus, the mask layer is also used as a mask in the vertical ion implantation process, so as to implant the bottom portion of the opening rather than the side wall of the opening. As such, the thickness of the converting layer subsequently formed on the side wall of the opening is larger than the thickness of the converting layer subsequently formed on the bottom portion of the opening, and thus the converting layer on the side wall of the opening provides a superior insulation effect. Accordingly, the overall process to fabricate the semiconductor device is simplified and the cost of the semiconductor process is greatly reduced. Moreover, the insulation effect and the characteristics of the semiconductor devices are improved.