SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

A small semiconductor device is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a p-channel first transistor containing silicon in a channel formation region. The second layer includes an n-channel second transistor containing a metal oxide in a channel formation region. The first transistor and the second transistor form a CMOS circuit. A channel length of the first transistor is longer than a channel length of the second transistor.

TECHNICAL FIELD

One embodiment of the present invention relates to a semiconductor device and an electronic device.

BACKGROUND ART

In recent years, semiconductor devices have been developed; an LSI, a CPU (Central Processing Unit), a memory, and the like have been mainly used for semiconductor devices. A CPU is an assembly of semiconductor elements; the CPU includes an integrated circuit (including at least a transistor and a memory) formed into a chip by processing a semiconductor wafer, and is provided with an electrode serving as a connection terminal.

An integrated circuit (IC) of an LSI, a CPU, a memory, or the like is mounted on a circuit board, for example, a printed wiring board, to be used as one of components of a variety of electronic devices.

A technique by which a transistor is formed using a semiconductor thin film formed over a substrate having an insulating surface has been attracting attention. The transistor is used in a wide range of electronic devices such as an integrated circuit and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to the transistor and further, an oxide semiconductor has been attracting attention as another material.

It is known that a transistor using an oxide semiconductor has an extremely low leakage current in a non-conduction state. For example, Patent Document 1 discloses a low-power-consumption CPU utilizing a feature of a low leakage current of the transistor using an oxide semiconductor. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored contents for a long time by utilizing a feature of a low leakage current of the transistor using an oxide semiconductor.

REFERENCES

Patent Documents

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

An object of one embodiment of the present invention is to provide a small semiconductor device. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the description of these objects does not preclude the presence of other objects. In one embodiment of the present invention, there is no need to achieve all of these objects. Note that objects other than these can be derived from the descriptions of the specification, the drawings, the claims, and the like.

Means for Solving the Problems

One embodiment of the present invention is a semiconductor device including a first layer and a second layer over the first layer; the first layer includes a p-channel first transistor containing silicon in a first channel formation region; the second layer includes an n-channel second transistor containing a metal oxide in a second channel formation region; the first transistor and the second transistor form a CMOS circuit; and a channel length of the first transistor is longer than a channel length of the second transistor.

In the above embodiment, the channel length of the first transistor may be greater than or equal to 15 nm, and the channel length of the second transistor may be less than 15 nm.

In the above embodiment, the channel length of the first transistor may be greater than or equal to 15 nm and less than or equal to 40 nm, and the channel length of the second transistor may be greater than or equal to 3 nm and less than 15 nm.

In the above embodiment, the first layer may include a single crystal silicon substrate, and the first transistor may include the first channel formation region in the single crystal silicon substrate.

In the above embodiment, the second layer may include a memory circuit.

In the above embodiment, the memory circuit may include a third transistor, a fourth transistor, and a capacitor; one of a source and a drain of the third transistor may be electrically connected to a gate of the fourth transistor; and the gate of the fourth transistor may be electrically connected to one electrode of the capacitor.

In the above embodiment, the third transistor and the fourth transistor may each contain the metal oxide of the second channel formation region.

An electronic device including the semiconductor device of one embodiment of the present invention and a display portion is also one embodiment of the present invention.

Effect of the Invention

According to one embodiment of the present invention, a small semiconductor device can be provided. According to another embodiment of the present invention, a highly reliable semiconductor device can be provided. According to another embodiment of the present invention, a novel semiconductor device can be provided.

Note that the description of these effects does not preclude the presence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these can be derived from the descriptions of the specification, the drawings, the claims, and the like.

MODE FOR CARRYING OUT THE INVENTION

Note that ordinal numbers such as “first” and “second” in this specification and the like are used in order to avoid confusion among components and do not denote the priority or the order such as the order of steps or the stacking order. A term without an ordinal number in this specification and the like may be provided with an ordinal number in the SCOPE OF CLAIMS in order to avoid confusion among components. Furthermore, a term with an ordinal number in this specification and the like may be provided with a different ordinal number in the SCOPE OF CLAIMS. As another example, even when a term is provided with an ordinal number in this specification, the ordinal number might be omitted in the SCOPE OF CLAIMS.

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, they are not limited to the illustrated scale. Note that the drawings schematically show ideal examples, and embodiments of the present invention are not limited to shapes, values, and the like shown in the drawings.

Furthermore, unless otherwise specified, off-state current in this specification and the like refers to drain current of a transistor in an off state (also referred to as a non-conduction state or a cutoff state). Unless otherwise specified, an off state refers to, in an n-channel transistor, a state where a voltage Vgsbetween its gate and source is lower than a threshold voltage Vth(in a p-channel transistor, higher than Vth).

In this specification and the like, a metal oxide is an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, in the case where a metal oxide is used in an active layer of a transistor, the metal oxide is referred to as an oxide semiconductor in some cases. That is, an OS transistor can also be called a transistor including a metal oxide or an oxide semiconductor.

An integrated structure with the above-described oxide semiconductor (OS) may be referred to as an OSLSI.

An oxide semiconductor used for an OSLSI contains at least indium (In) and oxygen (O). Typical examples include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO (registered trademark)), and indium oxide (IO). Furthermore, the oxide semiconductor may contain hydrogen as an impurity.

In this embodiment, a semiconductor device of one embodiment of the present invention is described with reference to drawings.

One embodiment of the present invention relates to a semiconductor device including a first layer and a second layer over the first layer. A transistor containing silicon in a channel formation region (hereinafter also referred to as a Si transistor or a SiFET) is provided in the first layer. Specifically, the first layer includes a single crystal silicon substrate, and the Si transistor can include the channel formation region in the single crystal silicon substrate. A transistor containing a metal oxide in a channel formation region (hereinafter also referred to as an OS transistor or an OSFET) is provided in the second layer. When the semiconductor device has a stacked-layer structure as described above, the number of transistors provided in one layer can be reduced and the area occupied by the semiconductor device can be reduced. Thus, the semiconductor device of one embodiment of the present invention can be reduced in size.

In this specification and the like, a transistor containing single crystal silicon in a channel formation region is referred to as a single crystal Si transistor. For example, a transistor including a channel formation region in a single crystal silicon substrate is a single crystal Si transistor.

In the semiconductor device of one embodiment of the present invention, a first transistor that is a p-channel Si transistor provided in the first layer and a second transistor that is an n-channel OS transistor provided in the second layer form a CMOS (Complementary Metal Oxide Semiconductor) circuit. Here, when the channel lengths, the channel widths, and the like are equal to each other, the mobility of the Si transistor, for example, a single crystal Si transistor is higher than the mobility of the OS transistor. Meanwhile, when the difference between the mobility of the p-channel transistor and the mobility of the n-channel transistor that form the CMOS is large, the CMOS circuit is not driven normally in some cases.

Thus, in one embodiment of the present invention, the channel length of the first transistor that is a Si transistor is longer than the channel length of the second transistor that is an OS transistor. As the channel length becomes longer, the electric resistance between the source and the drain becomes higher and the mobility becomes lower; thus, when the channel length of the first transistor is longer than the channel length of the second transistor, the difference in the mobility between the first transistor and the second transistor can be smaller than when the channel lengths of the first transistor and the second transistor are equal to each other. Accordingly, the difference in the on-state current between the first transistor and the second transistor can be small; thus, even when the first transistor that is a Si transistor and the second transistor that is an OS transistor form the CMOS circuit, the CMOS circuit can be driven normally.

Specifically, in consideration of easy fabrication of the second transistor, it is preferable that the channel length of the first transistor be greater than or equal to 15 nm and the channel length of the second transistor be less than 15 nm, for example. Alternatively, it is preferable that the channel length of the first transistor be greater than or equal to 15 nm and less than or equal to 40 nm and the channel length of the second transistor be greater than or equal to 3 nm and less than 15 nm. The channel length of the second transistor can be typically greater than or equal to 5 nm and less than or equal to 8 nm.

Note that when each of the channel lengths of the first transistor and the second transistor is within the above range, the off-state current (Ioff) of the second transistor (OSFET) can be designed to be lower than that of the first transistor (SiFET) by greater than or equal to 4 to 5 orders of magnitude. With this design, the on-state current (Ion) can be low.

The semiconductor device of one embodiment of the present invention includes a memory portion, and memory circuits are arranged in a matrix in the memory portion. The memory circuit includes a writing transistor, a reading transistor, and a selection transistor. For example, one of a source and a drain of the writing transistor is electrically connected to a gate of the reading transistor, and one of a source and a drain of the reading transistor is electrically connected to one of a source and a drain of the selection transistor.

The writing transistor has a function of a switch for controlling writing and retention of data to the memory circuit. Data is written to the memory circuit by turning on the writing transistor, and data is retained in the memory circuit by turning off the writing transistor. The reading transistor has a function of amplifying and reading data retained in the memory circuit. The selection transistor has a function of a switch for selecting a memory circuit from which data is read. When the selection transistor is turned on, data retained in the memory circuit is read. Specifically, when the selection transistor is turned on, current corresponding to data retained in the memory circuit flows between the drain and the source of the reading transistor and the drain and the source of the selection transistor; this allows data to be amplified and read.

A transistor with a low off-state current is preferably used as the writing transistor, in which case data can be retained in the memory circuit for a long period of time. As such a transistor, an OS transistor can be given. A transistor with a high on-state current is preferably used as the reading transistor and the selection transistor, in which case data can be read at a high speed from the memory circuit. As such a transistor, a Si transistor can be given.

As described above, the reading transistor and the selection transistor are provided in the first layer where the Si transistor is provided and the writing transistor is provided in the second layer where the OS transistor is provided, whereby data can be retained in the memory circuit for a long period of time and data can be read at a high speed from the memory circuit. Note that all the writing transistor, the reading transistor, and the selection transistor can be n-channel transistors.

Meanwhile, when the channel length, the channel width, and the like of the Si transistor provided in the first layer and the channel length, the channel width, and the like of the OS transistor provided in the second layer are equal to each other, a potential supplied to a gate of a transistor functioning as a switch needs to be different for each kind of transistor. For example, a potential supplied to a gate of a writing transistor in bringing the writing transistor that is an OS transistor functioning as a switch into an on state needs to be higher than a potential supplied to a gate of a selection transistor in bringing the selection transistor that is a Si transistor functioning as a switch into an on state.

In one embodiment of the present invention, the channel length of the Si transistor provided in the first layer is longer than the channel length of the OS transistor provided in the second layer as described above. Thus, a potential supplied to the gate of the Si transistor in bringing the Si transistor functioning as a switch into an on state and a potential supplied to the gate of the OS transistor in bringing the OS transistor functioning as a switch into an on state can be equal to each other. Furthermore, a potential supplied to the gate of the Si transistor in bringing the Si transistor functioning as a switch into an off state and a potential supplied to the gate of the OS transistor in bringing the OS transistor functioning as a switch into an off state can be equal to each other. Thus, a gate potential of the Si transistor functioning as a switch and a gate potential of the OS transistor functioning as a switch can be supplied from the same power source.

In the case where the channel length of the Si transistor provided in the first layer is longer than the channel length of the OS transistor provided in the second layer, the integration degree of transistors in the second layer can be lower than the integration degree of transistors in the first layer. For example, in the memory portion in which the memory circuits are arranged in a matrix, the integration degree of transistors in the second layer can be lower than the integration degree of transistors in the first layer.

FIG.1is a block diagram illustrating a structure example of a semiconductor device10of one embodiment of the present invention. The semiconductor device10includes a memory portion20, a word line driver circuit31, a bit line driver circuit32, a control circuit33, a communication circuit34, and an input/output circuit35.

Although a block diagram in which components are classified by their functions and shown as independent blocks is shown in the drawing attached to this specification, it is difficult to completely separate actual components according to their functions and one component can relate to a plurality of functions.

In the memory portion20, memory circuits21are arranged in a matrix. Each of the memory circuits21functions as a memory element.

In this specification and the like, a semiconductor device including a memory portion is referred to as a memory device in some cases. For example, the semiconductor device10can be referred to as a memory device.

Various memory systems can be used for the memory portion20. For example, a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), a phase-change memory (PCM), a resistive random access memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), an antiferroelectric memory, or the like may be used.

In addition, a NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory) or a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) may be used as the memory portion20, for example.

“NOSRAM (registered trademark)” is an abbreviation for “Nonvolatile Oxide Semiconductor Random Access Memory (RAM)”. A NOSRAM is a memory in which its memory circuit is a 2-transistor (2T) or 3-transistor (3T) gain cell, and its access transistor is an OS transistor. Current flowing between a source and a drain in an off state, that is, leakage current, is extremely low in an OS transistor. The NOSRAM is capable of reading retained data without destruction (non-destructive reading).

“DOSRAM (registered trademark)” is an abbreviation of “Dynamic Oxide Semiconductor RAM”, which indicates a RAM including 1T (transistor) 1C (capacitor)-type memory circuit. The DOSRAM, as well as the NOSRAM, is a memory utilizing a low off-state current of an OS transistor.

The word line driver circuit31is electrically connected to the memory circuits21through word lines. For example, the memory circuits21in the same row can be electrically connected to the same word line. The word line driver circuit31has a function of supplying a signal to the memory circuit21to which data is written and the memory circuit21from which data is read. That is, the word line driver circuit31has a function of generating a selection signal that is a signal for selecting the memory circuit21to which data is written and the memory circuit21from which data is read.

The bit line driver circuit32is electrically connected to the memory circuits21through bit lines. For example, the memory circuits21in the same column can be electrically connected to the same bit line. The bit line driver circuit32has a function of generating data to be written to the memory circuit21. Specifically, data generated by the bit line driver circuit32is written to the memory circuit21selected by a selection signal generated by the word line driver circuit31. The bit line driver circuit32has a function of amplifying and reading data retained in the memory circuit21. Specifically, data retained in the memory circuit21selected by the selection signal generated by the word line driver circuit31is amplified and read by the bit line driver circuit32.

The control circuit33has a function of controlling the driving of the word line driver circuit31and the bit line driver circuit32. Specifically, the control circuit33can supply control signals to the word line driver circuit31and the bit line driver circuit32by processing signals such as enable signals that are supplied from the outside of the semiconductor device10to the control circuit33. Note that the control circuit33may have a function of controlling the driving of the communication circuit34and the input/output circuit35. The control circuit33can include a CPU, for example.

The communication circuit34has a wireless or wired communication function. In particular, the communication circuit34preferably has a wireless communication function, in which case the number of parts such as a connection cable can be decreased.

In the case where the communication circuit34has a wireless communication function, the communication circuit34can perform communication via an antenna. As a communication protocol or a communication technology, a communications standard such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), or W-CDMA (registered trademark), or an IEEE communications standard such as Wi-Fi (registered trademark), Bluetooth (registered trademark), or ZigBee (registered trademark) can be used.

The communication circuit34can perform input/output of information by connecting the semiconductor device10to another device via a computer network such as the Internet, which is an infrastructure of the World Wide Web (WWW), an intranet, an extranet, a PAN (Personal Area Network), a LAN (Local Area Network), a CAN (Campus Area Network), a MAN (Metropolitan Area Network), a WAN (Wide Area Network), or a GAN (Global Area Network).

The input/output circuit35has a function of supplying a signal, which is supplied from the outside of the semiconductor device10to the semiconductor device10, to a circuit included in the semiconductor device10. For example, the input/output circuit35has a function of receiving a signal from the outside of the semiconductor device10and supplying the signal to the control circuit33. The input/output circuit35may have a function of supplying a signal, which is supplied to the communication circuit34, to a circuit included in the semiconductor device10such as the control circuit33.

The input/output circuit35also has a function of outputting a signal generated by a circuit included in the semiconductor device10to the outside of the semiconductor device10. For example, the input/output circuit35has a function of outputting a data signal representing data read from the memory circuit21by the bit line driver circuit32to the outside of the semiconductor device10. The input/output circuit35may have a function of supplying a signal generated by a circuit included in the semiconductor device10to the communication circuit34. The signal supplied to the communication circuit34can be output to the outside of the semiconductor device10.

FIG.2is a perspective view illustrating a structure example of a semiconductor device10A, which is a kind of the semiconductor device10. As illustrated inFIG.2, the semiconductor device10A includes a layer11and a layer12over the layer11.

Si transistors are provided in the layer11. Specifically, the layer11includes a silicon substrate, and the Si transistors are provided such that channel formation regions are formed in the silicon substrate. The Si transistor can be a single crystal Si transistor, for example. For example, when a single crystal silicon substrate is provided in the layer11and transistors are provided such that channel formation regions are formed in the single crystal silicon substrate, single crystal Si transistors can be provided in the layer11. Note that a transistor containing polycrystalline silicon in a channel formation region (hereinafter also referred to as a polycrystalline Si transistor) may be provided in the layer11, for example.

N-channel transistors are provided in the layer12, and, for example, OS transistors are provided. Specifically, an interlayer insulating film is provided over the layer11, and the OS transistors can be provided over the interlayer insulating film.

An OS transistor has characteristics of an extremely low off-state current. Thus, when an OS transistor is used as a transistor provided in the memory circuit21, data that is written to the memory circuit21can be retained for a long period of time.FIG.2illustrates an example in which the memory portion20including the memory circuits21is provided in the layer12.

A metal oxide that can be used for an OS transistor is an In oxide, a Zn oxide, a Zn—Sn oxide, a Ga—Sn oxide, an In—Ga oxide, an In—Zn oxide, an In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), and the like. The use of a metal oxide containing Ga as M for the OS transistor is particularly preferable because the electrical characteristics such as field-effect mobility of the transistor can be made excellent by adjusting a ratio of elements. In addition, an oxide containing indium and zinc may contain one or more kinds selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

A variety of circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, and a logic circuit can be used as the word line driver circuit31, the bit line driver circuit32, the control circuit33, the communication circuit34, and the input/output circuit35illustrated inFIG.1. These circuits each include a CMOS circuit.

As described above, the OS transistor provided in the layer12can be an n-channel transistor. Thus, in the semiconductor device10A, among the transistors that form CMOS circuits, n-channel transistors are provided in the layer12and p-channel transistors are provided in the layer11. In the semiconductor device10A, a word line driver circuit31p, a bit line driver circuit32p, a control circuit33p, a communication circuit34p, and an input/output circuit35pthat are each provided with a p-channel transistor are provided in the layer11, and a word line driver circuit31n, a bit line driver circuit32n, a control circuit33n, a communication circuit34n, and an input/output circuit35nthat are each provided with an n-channel transistor are provided in the layer12.

The word line driver circuit31pand the word line driver circuit31nform the word line driver circuit31. The bit line driver circuit32pand the bit line driver circuit32nform the bit line driver circuit32. The control circuit33pand the control circuit33nform the control circuit33. The communication circuit34pand the communication circuit34nform the communication circuit34. The input/output circuit35pand the input/output circuit35nform the input/output circuit35.

The layer11includes a plurality of Si transistors and the layer12includes a plurality of OS transistors. Thus, the layer11can be regarded as having a Si transistor group and the layer12can be regarded as having an OS transistor group. Here, all Si transistors included in the layer11may be collectively referred to as one Si transistor group, and all OS transistors included in the layer12may be collectively referred to as one OS transistor group, for example.

Alternatively, the layer11may be regarded as including a plurality of Si transistor groups and the layer12may be regarded as including a plurality of OS transistor groups. For example, the circuits may have different transistor groups from each other. For example, the word line driver circuit31pand the bit line driver circuit32pmay be regarded as having different Si transistor groups from each other, and the word line driver circuit31nand the bit line driver circuit32nmay be regarded as having different OS transistor groups from each other. In the case where the layer11includes the plurality of Si transistor groups and the layer12includes the plurality of OS transistor groups, it can be said one Si transistor group and one OS transistor group form a circuit having one or more functions.

FIG.3is a circuit diagram illustrating an example of a CMOS circuit included in the semiconductor device10A.FIG.3illustrates an inverter as an example of the CMOS circuit.

As illustrated inFIG.3, a transistor41pprovided in the layer11and a transistor41nprovided in the layer12can form the inverter. The transistor41pis a p-channel Si transistor and the transistor41nis an n-channel OS transistor.

A gate of the transistor41pand a gate of the transistor41nare electrically connected to a terminal IN. One of a source and a drain of the transistor41pand one of a source and a drain of the transistor41nare electrically connected to a terminal OUT. A potential VDD is supplied to the other of the source and the drain of the transistor41p. A potential VSS is supplied to the other of the source and the drain of the transistor41n.

The potential VDD and the potential VSS can be power supply potentials. The potential VDD is also referred to as a high potential or a high-level-side power supply potential, and the potential VSS is also referred to as a low potential or a low-level-side power supply potential.

The inverter illustrated inFIG.3has a function of inverting a logic value represented by a digital signal input to the terminal IN and outputting it from the terminal OUT. Specifically, in the case where a digital signal with a logic value of “0” is input to the terminal IN, a digital signal with a logic value of “1” is output from the terminal OUT. In the case where a digital signal with a logic value of “1” is input to the terminal IN, a digital signal with a logic value of “0” is output from the terminal OUT. Specifically, in the case where a low-potential signal is input to the terminal IN as a digital signal with a logic value of “0”, the transistor41pis turned on and the transistor41nis turned off, and a high-potential signal is output from the terminal OUT as a digital signal with a logic value of “1”, for example. Meanwhile, in the case where a high-potential signal is input to the terminal IN, the transistor41pis turned off and the transistor41nis turned on, and a low-potential signal is output from the terminal OUT as a digital signal with a logic value of “0”.

The p-channel transistors are provided in the layer11and the n-channel transistors are provided in the layer12. That is, when the p-channel transistors and the n-channel transistors are stacked, the number of transistors provided in the layer11can be reduced, for example. Accordingly, the area occupied by the semiconductor device can be reduced. Thus, the semiconductor device10A can be a downsized semiconductor device. Note that all the n-channel transistors included in the semiconductor device10A are not necessarily provided in the layer12. For example, an n-channel transistor that does not form the CMOS circuit may be provided in the layer11.

Here, when the channel lengths, the channel widths, and the like are equal to each other, the mobility of the Si transistor is higher than the mobility of the OS transistor. In particular, when a Si transistor using silicon having higher crystallinity than amorphous silicon in a channel formation region, such as a single crystal Si transistor or a polycrystalline Si transistor, is used as the Si transistor, the mobility of the Si transistor is higher than the mobility of the OS transistor. Meanwhile, when the difference between the mobility of the p-channel transistor and the mobility of the n-channel transistor that form the CMOS is large, the CMOS circuit is not driven normally in some cases. For example, when the difference between the mobility of the transistor41pand the mobility of the transistor41nillustrated inFIG.3is large, the difference between the on-state current of the transistor41pand the on-state current of the transistor41nis large; thus, the inverter is not driven normally in some cases. For example, a digital signal with a logic value of “0” is not output from the terminal OUT in some cases.

Thus, in the semiconductor device10A, among the transistors that form the CMOS circuit, the channel length of the Si transistor provided in the layer11is longer than the channel length of the OS transistor provided in the layer12. For example, the channel length of the transistor41pis longer than the channel length of the transistor41n. As the channel length becomes longer, the electric resistance between the source and the drain becomes higher and the mobility becomes lower; thus, when the channel length of the transistor41pis longer than the channel length of the transistor41n, for example, the difference in the mobility between the transistor41pand the transistor41ncan be smaller than when the channel lengths of the transistor41pand the transistor41nare equal to each other. For example, the mobility of the transistor41pcan be lower than or equal to 300 times, lower than or equal to 100 times, lower than or equal to 50 times, lower than or equal to 30 times, or lower than or equal to 10 times the mobility of the transistor41n.

As described above, the difference in on-state current between the transistor41pand the transistor41ncan be small, whereby the inverter serving as a CMOS circuit can be driven normally. Specifically, both a digital signal with a logic value of “0” and a digital signal with a logic value of “1” can be output from the terminal OUT. Even in a CMOS circuit other than the inverter, the channel length of the Si transistor provided in the layer11is longer than the channel length of the OS transistor provided in the layer12, whereby driving can be performed normally.

In the inverter illustrated inFIG.3as an example of a CMOS circuit, specific examples of the channel length of the transistor41pthat is a Si transistor provided in the layer11and the channel length of the transistor41nthat is an OS transistor provided in the layer12are described below.

For example, in consideration of easy fabrication of the transistor41n, it is preferable that the channel length of the transistor41pbe greater than or equal to 15 nm and the channel length of the transistor41nbe less than 15 nm. Alternatively, it is preferable that the channel length of the transistor41pbe greater than or equal to 15 nm and less than or equal to 40 nm and the channel length of the transistor41nbe greater than or equal to 3 nm and less than 15 nm. The channel length of the transistor41ncan be typically greater than or equal to 5 nm and less than or equal to 8 nm.

Furthermore, the integration degree of transistors in the layer12can be lower than the integration degree of transistors in the layer11. For example, the integration degree of transistors in the layer11including Si transistors can be higher than or equal to 50/μm2, preferably higher than or equal to 100/μm2. Meanwhile, the integration degree of transistors in the layer12including OS transistors can be lower than 50/μm2. The integration degree of transistors in the layer12can be higher than or equal to 0.01 and lower than 1 of the integration degree of transistors in the layer11. In particular, in the case where an n-channel transistor that does not form the CMOS circuit is provided in the layer11, the integration degree of transistors in the layer12can be lower than the integration degree of transistors in the layer11, for example.

In this specification and the like, the integration degree of transistors refers to the number of transistors per unit area. The integration degree of transistors can also be referred to as a density of transistors. Note that the integration degree of transistors may be referred to as the integration degree of a transistor group.

An OS transistor including a metal oxide in a channel formation region is likely to change its electrical characteristics when oxygen vacancies (VO) exist in the channel formation region, which may degrade the reliability. In some cases, hydrogen in the vicinity of an oxygen vacancy forms a defect that is the oxygen vacancy into which hydrogen enters (hereinafter sometimes referred to as VOH), which generates an electron serving as a carrier. When VOH is formed in the metal oxide, a low-resistance region or an n-type region is formed in some cases. Furthermore, in the metal oxide, indium (In) and VOH are bonded to each other to form InVOH in some cases. The InVOH functions as part of an n-type region (also referred to as an n-type conductive region). In that case, it is preferable that the metal oxide include a region where a channel is formed and an n-type region and the region where the channel is formed have less oxygen vacancies (VO) than the n-type region.

More specifically, when the region of the metal oxide where a channel is formed includes oxygen vacancies, the transistor tends to have normally-on characteristics (even when no voltage is applied to the gate electrode, the channel exists and current flows through the transistor). Therefore, oxygen vacancies and VOH are preferably reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the region of the metal oxide where a channel is formed have a reduced carrier concentration and be of i-type (intrinsic) or substantially i-type.

As a countermeasure for the above, oxygen is supplied to the channel formation region of the metal oxide in the manufacturing process of the OS transistor, whereby oxygen vacancies and VoH can be reduced. For example, an insulator containing oxygen that is released by heating (hereinafter referred to as excess oxygen in some cases) is provided in the vicinity of the metal oxide so that oxygen can be supplied from the insulator to the metal oxide when heat treatment is performed.

The semiconductor device of one embodiment of the present invention can have a structure in which the channel lengths of the OS transistors are short and the integration degree of the OS transistors is low. Thus, particularly in the case where oxygen is supplied from an insulator containing excess oxygen to a metal oxide, the amount of oxygen supplied per unit area to the metal oxide increases. Specifically, when the channel lengths of the OS transistors are shorter than the channel lengths of the Si transistors and the integration degree of the OS transistors is lower than the integration degree of the Si transistors, the amount of oxygen supplied per unit area to the metal oxide can be favorably increased. In the above manner, oxygen vacancies and VoH in the metal oxide can be favorably reduced, and the semiconductor device of one embodiment of the present invention can have high reliability.

<Structure Example of Memory Circuit>

Here, structure examples of the memory circuit21will be described with reference toFIG.4AtoFIG.4H. Note that a memory circuit21A to a memory circuit21H illustrated inFIG.4AtoFIG.4Hare memory circuits using OS transistors, which can be roughly classified into NOSRAMs inFIG.4A to4Fand DOSRAMs inFIG.4GandFIG.4H.

FIG.4Aillustrates a circuit structure example applicable to the memory circuit21. Here, the memory circuit21A is a 2-transistor (2T) gain cell. The memory circuit21A includes a transistor MW1, a transistor MRT, and a capacitor CST. One of a source and a drain of the transistor MW1is electrically connected to a gate of the transistor MRT, and the gate of the transistor MRT is electrically connected to one electrode of the capacitor CST. The transistor MW1and the transistor MRT can be OS transistors. The transistor MW1is a writing transistor and the transistor MRT is a reading transistor.

The other of the source and the drain of the transistor MW1is electrically connected to a bit line WBL. A gate of the transistor MW1is electrically connected to a word line WWL. One of a source and a drain of the transistor MR1is electrically connected to a bit line RBL. The other of the source and the drain of the transistor MR1is electrically connected to a source line SL. A back gate of the transistor MW1and a back gate of the transistor MR1are electrically connected to a wiring BGL.

The writing transistor has a function of a switch for controlling writing and retention of data to the memory circuit21. Data is written to the memory circuit21by turning on the writing transistor, and data is retained in the memory circuit21by turning off the writing transistor. The reading transistor has a function of amplifying and reading data retained in the memory circuit21.

The memory circuit21A includes an OS transistor as the writing transistor and thus does not consume power for data retention. Thus, the memory circuit21A is a low-power memory circuit that can retain data for a long period of time, and the memory portion20can be used as a non-volatile memory device.

The memory circuit21B illustrated inFIG.4Bis a 3T gain cell and includes a transistor MW2, a transistor MR2, a transistor MS2, and a capacitor CS2. The transistor MW2, the transistor MR2, and the transistor MS2are a writing transistor, a reading transistor, and a selection transistor, respectively. A back gate of the transistor MW2, a back gate of the transistor MR2, and a back gate of the transistor MS2are electrically connected to the wiring BGL. The memory circuit21B is electrically connected to a word line RWL, the word line WWL, the bit line RBL, the bit line WBL, a capacitor line CDL, and a power supply line PL. For example, a potential GND (low-level-side power supply potential) is input to the capacitor line CDL and the power supply line PL.

The selection transistor has a function of a switch for selecting the memory circuit21from which data is read. When the selection transistor is turned on, data retained in the memory circuit21is read. Specifically, when the selection transistor is turned on, current corresponding to data retained in the memory circuit21flows between the drain and the source of the reading transistor and the drain and the source of the selection transistor; this allows data to be amplified and read.

FIG.4CandFIG.4Dillustrate other structure examples of 2T gain cells. The memory circuit21C illustrated inFIG.4Cincludes an n-channel Si transistor as the reading transistor. The memory circuit21C illustrated inFIG.4Dincludes a p-channel Si transistor as the reading transistor. As illustrated inFIG.4CandFIG.4D, the transistors in the memory circuit may be a combination of an OS transistor and a Si transistor.

FIG.4EandFIG.4Fillustrate other structure examples of 3T gain cells. The memory circuit21E illustrated inFIG.4Eincludes a transistor MW3, a transistor MR3, a transistor MS3, and a capacitor CS3. The transistor MW3, the transistor MR3, and the transistor MS3are a writing transistor, a reading transistor, and a selection transistor, respectively. The memory circuit21E includes n-channel Si transistors as the reading transistor and the selection transistor. In the example inFIG.4E, the potential VSS is input to the power supply line PL. The memory circuit21F illustrated inFIG.4Fincludes p-channel Si transistors as the reading transistor and the selection transistor. In the example inFIG.4F, the potential VDD is input to the power supply line PL.

In the case where the memory circuit21includes Si transistors as illustrated inFIG.4CtoFIG.4F, the transistors can be provided in the layer11. Thus, the memory circuit21can include Si transistors provided in the layer11and OS transistors provided in the layer12.

In the above-described gain cells, a bit line serving as both the bit line RBL for reading and the bit line WBL for writing may be provided.

FIG.4GandFIG.4Hillustrate examples of 111C (capacitor) memory circuits. The memory circuit21G illustrated inFIG.4Gis electrically connected to a word line WL, a bit line BL, the capacitor line CDL, and the wiring BGL. The memory circuit21G includes a transistor MW4and a capacitor CS4. A back gate of the transistor MW4is electrically connected to the wiring BGL. The memory circuit21H illustrated inFIG.4Hillustrates a structure of a ferroelectric memory using a capacitor containing a ferroelectric material as the capacitor CS4. For example, HfZrOXcan be used as the ferroelectric material.

FIG.5is a perspective view illustrating a structure example of a semiconductor device10B, which is a kind of the semiconductor device10. A structure of the semiconductor device10B that is different from that of the semiconductor device10A is mainly described below.

In the semiconductor device10B, a memory portion20ris provided in the layer11and circuits21rare arranged in a matrix in the memory portion20r. A memory portion20wis provided in the layer12and circuits21ware arranged in a matrix in the memory portion20w. The memory portion20includes the memory portion20rand the memory portion20wand the memory circuit21includes the circuit21rand the circuit21w.

In the semiconductor device10B, any of the structures illustrated inFIG.4CtoFIG.4Fcan be employed for the memory circuit21. For example, in the case where the memory circuit21includes a writing transistor and a reading transistor, the reading transistor is provided in the circuit21rand the writing transistor is provided in the circuit21w. In the case where the memory circuit includes a selection transistor, the selection transistor is provided in the circuit21r.

When the memory portion20is formed in both the layer11and the layer12as illustrated inFIG.5, the area occupied by the memory portion20can be reduced as compared with the case where all components of the memory portion20are formed in the layer11or the layer12, for example. Accordingly, the area occupied by the semiconductor device can be reduced. Thus, the semiconductor device10B can be a downsized semiconductor device.

Note that in the semiconductor device10B, the word line driver circuit31, the bit line driver circuit32, the control circuit33, the communication circuit34, and the input/output circuit35are not necessarily formed in both the layer11and the layer12, for example. For example, the components of the word line driver circuit31, the bit line driver circuit32, the control circuit33, the communication circuit34, and the input/output circuit35can be formed only in the layer11and are not necessarily formed in the layer12. In that case, all the transistors included in the word line driver circuit31, the bit line driver circuit32, the control circuit33, the communication circuit34, and the input/output circuit35can be Si transistors.

FIG.6is a circuit diagram illustrating an example of the memory circuit21included in the semiconductor device10B.FIG.6illustrates an example of the memory circuit21having the structure illustrated inFIG.4E.

As illustrated inFIG.6, the memory circuit21included in the semiconductor device10B includes the layer11and the layer12over the layer11. The transistor MR3and the transistor MS3are provided in the layer11. The transistor MW3and the capacitor CS3are provided in the layer12. All of the transistor MR3, the transistor MS3, and the transistor MW3can be n-channel transistors. Note that the capacitor CS3may be provided in a layer other than the layer12. For example, the capacitor CS3can be provided in a layer above the layer12.

One of a source and a drain of the transistor MR3is electrically connected to one of a source and a drain of the transistor MS3. A gate of the transistor MR3is electrically connected to one of a source and a drain of the transistor MW3. One of the source and the drain of the transistor MW3is electrically connected to one electrode of the capacitor CS3.

The other of the source and the drain of the transistor MR3is electrically connected to the power supply line PL. The other of the source and the drain of the transistor MS3is electrically connected to the bit line RBL. A gate of the transistor MS3is electrically connected to the word line RWL. The other of the source and the drain of the transistor MW3is electrically connected to the bit line WBL. A gate of the transistor MW3is electrically connected to the word line WWL. A back gate of the transistor MW3is electrically connected to the wiring BGL. The other electrode of the capacitor CS3is electrically connected to the capacitor line CDL.

Since the transistor MR3and the transistor MS3are provided in the layer11, the transistors can be Si transistors. Since the transistor MW3is provided in the layer12, the transistor can be an OS transistor. As described above, when the channel length, the channel width, and the like of a Si transistor, particularly a single crystal Si transistor, a polycrystalline Si transistor, and the like are equal to the channel length, the channel width, and the like of an OS transistor, the mobility of the Si transistor is higher than that of the OS transistor, and thus the on-state current of the Si transistor is higher than that of the OS transistor. Accordingly, when the Si transistor is used as the transistor MR3and the transistor MS3, data can be read from the memory circuit21at a high speed as compared with the case where the OS transistor is used as the transistor MR3and the transistor MS3, for example. Meanwhile, the OS transistor has a lower off-state current than the Si transistor. Accordingly, when the OS transistor is used as the transistor MW3, data can be retained in the memory circuit21for a long period of time as compared with the case where the Si transistor is used as the transistor MW3, for example.

Meanwhile, when the channel length, the channel width, and the like of the Si transistor provided in the layer11and the channel length, the channel width, and the like of the OS transistor provided in the layer12are equal to each other, a potential supplied to a gate of a transistor functioning as a switch needs to be different for each kind of transistor. For example, a potential supplied to the word line WWL in bringing the transistor MW3that is an OS transistor functioning as a switch into an on state needs to be higher than a potential supplied to the word line RWL in bringing the transistor MS3that is a Si transistor functioning as a switch into an on state.

In the semiconductor device10B, among the transistors that form the memory circuit21, the channel length of the Si transistor provided in the layer11is longer than the channel length of the OS transistor provided in the layer12. For example, each of the channel lengths of the transistor MR3and the transistor MS3is longer than the channel length of the transistor MW3. Thus, a potential supplied to the word line RWL in bringing the transistor MS3into an on state and a potential supplied to the word line WWL in bringing the transistor MW3into an on state can be equal to each other, for example. Furthermore, a potential supplied to the word line RWL in bringing the transistor MS3into an off state and a potential supplied to the word line WWL in bringing the transistor MW3into an off state can be equal to each other, for example. Accordingly, the potential supplied to the word line RWL and the potential supplied to the word line WWL can be supplied from the same power source, for example. Note that even in transistors functioning as switches that are provided in a circuit other than the memory portion20in the semiconductor device10B, when the channel length of the Si transistor is longer than the channel length of the OS transistor, a potential supplied to the gate of the n-channel Si transistor and a potential supplied to the gate of the OS transistor can be supplied from the same power source.

In this specification and the like, a potential supplied to the word line WWL in bringing the transistor MW3into an on state is sometimes referred to as a first potential, a potential supplied to the word line WWL in bringing the transistor MW3into an off state is sometimes referred to as a second potential, a potential supplied to the word line RWL in bringing the transistor MS3into an on state is sometimes referred to as a third potential, and a potential supplied to the word line RWL in bringing the transistor MS3into an off state is sometimes referred to as a fourth potential, for example. Note that the ordinal numbers “first” to “fourth” may be interchanged with one another as appropriate.

Specific examples of the channel lengths of the transistor MR3and the transistor MS3that are Si transistors provided in the layer11and the channel length of the transistor MW3that is an OS transistor provided in the layer12in the memory circuit21illustrated inFIG.6will be described below.

For example, in consideration of easy fabrication of the transistor MW3, it is preferable that the channel length of each of the transistor MR3and the transistor MS3be greater than or equal to 15 nm and the channel length of the transistor MW3be less than 15 nm. Alternatively, it is preferable that the channel length of each of the transistor MR3and the transistor MS3be greater than or equal to 15 nm and less than or equal to 40 nm and the channel length of the transistor MW3be greater than or equal to 3 nm and less than 15 nm. The channel length of the transistor MW3can be typically greater than or equal to 5 nm and less than or equal to 8 nm.

Here, in the case where the memory circuit21has the structure illustrated inFIG.6, two transistors are provided in the circuit21rillustrated inFIG.5, and one transistor is provided in the circuit21w, for example. Thus, in the semiconductor device10B, the integration degree of transistors in the memory portion20wcan be lower than the integration degree of transistors in the memory portion20r, for example. For example, the integration degree of transistors in the memory portion20rcan be higher than or equal to 50/μm2, preferably higher than or equal to 100/μm2. Meanwhile, the integration degree of transistors in the memory portion20wcan be lower than 50/μm2. As described above, since the channel length of the transistor MW3is shorter than the channel length of the transistor MR2, even when the memory circuit21does not include the transistor MS3, the integration degree of transistors in the memory portion20wcan be lower than the integration degree of transistors in the memory portion20r, for example.

As described above, the semiconductor device of one embodiment of the present invention can have a structure in which the channel lengths of the OS transistors are short and the integration degree of the OS transistors is low. Thus, particularly in the case where oxygen is supplied from an insulator containing excess oxygen to a metal oxide, the amount of oxygen supplied per unit area to the metal oxide increases. Specifically, when the channel lengths of the OS transistors are shorter than the channel lengths of the Si transistors and the integration degree of the OS transistors is lower than the integration degree of the Si transistors, the amount of oxygen supplied per unit area to the metal oxide can be favorably increased. In the above manner, oxygen vacancies and VoH in the metal oxide can be favorably reduced, and the semiconductor device of one embodiment of the present invention can have high reliability.

<Structure Examples of Transistors>

FIG.7Ais a top view illustrating a structure example of a transistor200, which is an OS transistor, and its periphery included in the semiconductor device of one embodiment of the present invention.FIG.7B,FIG.7C, andFIG.7Dare cross-sectional views illustrating a structure example of the transistor200and its periphery. Here,FIG.7Bis a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2inFIG.7A, and is a cross-sectional view of the transistor200in the channel length direction.FIG.7Cis a cross-sectional view of a portion indicated by the dashed-dotted line A3-A4inFIG.7A, and is a cross-sectional view of the transistor200in the channel width direction.FIG.7Dis a cross-sectional view of a portion indicated by the dashed-dotted line A5-A6inFIG.7A. Note that for clarity of the drawing, some components are omitted in the top view ofFIG.7A.

The transistor200can be provided in the layer12illustrated inFIG.2,FIG.3,FIG.5, andFIG.6. For example, the transistor200can be used as the transistor41nillustrated inFIG.3and as the transistor MW3illustrated inFIG.6.

The semiconductor device of one embodiment of the present invention includes an insulator212over a substrate (not illustrated), an insulator214over the insulator212, the transistor200over the insulator214, an insulator280over the transistor200, an insulator282over the insulator280, an insulator283over the insulator282, an insulator274over the insulator283, and an insulator285over the insulator283and the insulator274. The insulator212, the insulator214, the insulator280, the insulator282, the insulator283, the insulator285, the insulator274, and the insulator285function as interlayer films. A conductor240aand a conductor240bthat are electrically connected to the transistor200and function as plugs are also included. An insulator241ais provided in contact with the side surface of the conductor240a, and an insulator241bis provided in contact with the side surface of the conductor240b.

In this specification and the like, a plurality of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases. Moreover, in this specification and the like, a wiring and a plug connected to the wiring may be a single component. That is, part of a conductor functions as a wiring in some cases and part of a conductor functions as a plug in other cases.

A conductor246athat is electrically connected to the conductor240aand functions as a wiring is provided over the insulator285and the conductor240a, and a conductor246bthat is electrically connected to the conductor240band functions as a wiring is provided over the insulator285and the conductor240b. The insulator283is in contact with part of the top surface of the insulator214, the side surface of the insulator280, and the side surface and the top surface of the insulator282.

The insulator241ais provided in contact with an inner wall of an opening formed in the insulator280, the insulator282, the insulator283, and the insulator285, and the conductor240ais provided in contact with the side surface of the insulator241a. The insulator241bis provided in contact with an inner wall of an opening formed in the insulator280, the insulator282, the insulator283, and the insulator285, and the conductor240bis provided in contact with the side surface of the insulator241b. Each of the insulator241aand the insulator241bhas a structure in which a first insulator is provided in contact with the inner wall of the opening and a second insulator is provided on the inner side of the first insulator. The conductor240ahas a structure in which a first conductor is provided in contact with the side surface of the insulator241aand a second conductor is provided on the inner side of the first conductor. The conductor240bhas a structure in which a first conductor is provided in contact with the side surface of the insulator241band a second conductor is provided on the inner side of the first conductor. The top surface of the conductor240acan be substantially level with the top surface of the insulator285in a region overlapping with the conductor246a. Moreover, the top surface of the conductor240bcan be substantially level with the top surface of the insulator285in a region overlapping with the conductor246b.

Although each of the insulator241aand the insulator241bhas a structure in which the first insulator and the second insulator are stacked in the transistor200, the present invention is not limited thereto. For example, each of the insulator241aand the insulator241bmay have a single-layer structure or a stacked-layer structure of three or more layers. Note that although each of the conductor240aand the conductor240bhas a structure in which the first conductor and the second conductor are stacked in the transistor200, the present invention is not limited thereto. For example, each of the conductor240aand the conductor240bmay have a single-layer structure or a stacked-layer structure of three or more layers. In the case where a component has a stacked-layer structure, layers may be distinguished by ordinal numbers given corresponding to the formation order.

The transistor200includes an insulator216over the insulator214, a conductor205(a conductor205aand a conductor205b) placed to be embedded in the insulator216, an insulator222over the insulator216and the conductor205, an insulator224over the insulator222, a metal oxide230aover the insulator224, a metal oxide230bover the metal oxide230a, a conductor242aover the metal oxide230b, an insulator271aover the conductor242a, a conductor242bover the metal oxide230b, an insulator271bover the conductor242b, an insulator252over the metal oxide230b, an insulator250over the insulator252, an insulator254over the insulator250, a conductor260(a conductor260aand a conductor260b) positioned over the insulator254and overlapping with part of the metal oxide230b, and an insulator275placed over the insulator222, the insulator224, the metal oxide230a, the metal oxide230b, the conductor242a, the conductor242b, the insulator271a, and the insulator271b. Here, as illustrated inFIG.7BandFIG.7C, the insulator252is in contact with at least parts of the top surface of the insulator222, the side surface of the insulator224, the side surface of the metal oxide230a, the side surface and the top surface of the metal oxide230b, side surfaces of the conductor242aand the conductor242b, side surfaces of the insulator271aand the insulator271b, the side surface of the insulator275, the side surface of the insulator280, and the bottom surface of the insulator250. The top surface of the conductor260is placed to be substantially level with the uppermost portion of the insulator254, the uppermost portion of the insulator250, the uppermost portion of the insulator252, and the top surface of the insulator280. The insulator282is in contact with at least parts of the top surfaces of the conductor260, the insulator252, the insulator250, the insulator254, and the insulator280.

Hereinafter, the metal oxide230aand the metal oxide230bare collectively referred to as the metal oxide230in some cases. The conductor242aand the conductor242bare collectively referred to as the conductor242in some cases. The insulator271aand the insulator271bare collectively referred to as the insulator271in some cases.

An opening reaching the metal oxide230bis provided in the insulator280and the insulator275. That is, the opening includes a region overlapping with the metal oxide230b. It can be said that the insulator275includes an opening overlapping with an opening included in the insulator280. The insulator252, the insulator250, the insulator254, and the conductor260are placed in the opening that is provided in the insulator280and the insulator275and reaches the metal oxide230b. That is, the conductor260includes a region overlapping with the metal oxide230bwith the insulator252, the insulator250, and the insulator254therebetween. The conductor260, the insulator252, the insulator250, and the insulator254are provided between the insulator271aand the conductor242a, and the insulator271band the conductor242bin the channel length direction of the transistor200. The insulator254includes a region in contact with the side surface of the conductor260and a region in contact with the bottom surface of the conductor260.

The metal oxide230preferably includes the metal oxide230aplaced over the insulator224and the metal oxide230bplaced over the metal oxide230a. Including the metal oxide230aunder the metal oxide230bmakes it possible to inhibit diffusion of impurities into the metal oxide230bfrom components formed below the metal oxide230a.

Although a structure in which two layers, the metal oxide230aand the metal oxide230b, are stacked as the metal oxide230in the transistor200is described, the present invention is not limited thereto. For example, the metal oxide230may be provided as a single layer of the metal oxide230bor as stacked-layer structure of three or more layers, or the metal oxide230aand the metal oxide230bmay each have a stacked-layer structure.

The conductor260functions as a first gate (also referred to as a top gate) electrode, and the conductor205functions as a second gate (also referred to as a back gate) electrode. The insulator252, the insulator250, and the insulator254function as a first gate insulator, and the insulator222and the insulator224function as a second gate insulator. Note that the gate insulator is also referred to as a gate insulating layer or a gate insulating film in some cases. The conductor242afunctions as one of a source and a drain, and the conductor242bfunctions as the other of the source and the drain. At least part of a region of the metal oxide230overlapping with the conductor260functions as a channel formation region.

FIG.8Ais an enlarged view of the vicinity of the channel formation region inFIG.7B. Supply of oxygen to the metal oxide230bforms the channel formation region in a region between the conductor242aand the conductor242b. As illustrated inFIG.8A, the metal oxide230bincludes a region230bcfunctioning as the channel formation region of the transistor200and a region230baand a region230bbthat function as a source region and a drain region. As illustrated inFIG.8A, the region230baand the region230bbare provided so as to sandwich the region230bctherebetween. At least part of the region230bcoverlaps with the conductor260. In other words, the region230bcis provided between the conductor242aand the conductor242b. The region230bais provided to overlap with the conductor242a, and the region230bbis provided to overlap with the conductor242b.

The region230bcfunctioning as the channel formation region has a smaller amount of oxygen vacancies or a lower impurity concentration than those of the region230baand the region230bb, and thus is a high-resistance region with a low carrier concentration. Thus, the region230bccan be regarded as being i-type (intrinsic) or substantially i-type.

The region230baand the region230bbfunctioning as the source region and the drain region include a large amount of oxygen vacancies or have a high concentration of an impurity such as hydrogen, nitrogen, or a metal element, and thus are each a low-resistance region with an increased carrier concentration. In other words, the region230baand the region230bbare each an n-type region having a higher carrier concentration and a lower resistance than the region230bc.

The carrier concentration in the region230bcfunctioning as the channel formation region is preferably lower than or equal to 1×1018cm−3, further preferably lower than 1×1017cm−3, still further preferably lower than 1×1016cm−3, yet further preferably lower than 1×1013cm−3, yet still further preferably lower than 1×1012cm−3. Note that the lower limit of the carrier concentration in the region230bcfunctioning as the channel formation region is not particularly limited and can be, for example, 1×10−9cm−3.

Between the region230bcand the region230baor the region230bb, a region having a carrier concentration that is lower than or substantially equal to the carrier concentrations in the region230baand the region230bband higher than or substantially equal to the carrier concentration in the region230bcmay be formed. That is, the region functions as a junction region between the region230bcand the region230baor the region230bb. The hydrogen concentration in the junction region is lower than or substantially equal to the hydrogen concentrations in the region230baand the region230bband higher than or substantially equal to the hydrogen concentration in the region230bcin some cases. The amount of oxygen vacancies in the junction region is smaller than or substantially equal to the amounts of oxygen vacancies in the region230baand the region230bband larger than or substantially equal to the amount of oxygen vacancies in the region230bcin some cases.

AlthoughFIG.8Aillustrates an example where the region230ba, the region230bb, and the region230bcare formed in the metal oxide230b, the present invention is not limited thereto. For example, the above regions may be formed not only in the metal oxide230bbut also in the metal oxide230a.

In the metal oxide230, the boundaries between the regions are difficult to detect clearly in some cases. The concentration of a metal element and an impurity element such as hydrogen or nitrogen, which is detected in each region, may be not only gradually changed between the regions but also continuously changed in each region. That is, the region closer to the channel formation region preferably has a lower concentration of a metal element and an impurity element such as hydrogen or nitrogen.

In the transistor200, a metal oxide functioning as a semiconductor (such a metal oxide is hereinafter also referred to as an oxide semiconductor) is preferably used for the metal oxide230(the metal oxide230aand the metal oxide230b) including the channel formation region.

The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or higher, further preferably 2.5 eV or higher. With use of a metal oxide having a wide bandgap, the off-state current of the transistor can be reduced.

As the metal oxide230, it is preferable to use, for example, a metal oxide such as an In-M-Zn oxide containing indium, an element M, and zinc (the element M is one or more kinds selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like). Alternatively, an In—Ga oxide, an In—Zn oxide, or an indium oxide may be used as the metal oxide230.

The metal oxide230preferably has a stacked-layer structure of a plurality of oxide layers with different chemical compositions. For example, the atomic ratio of the element M to a metal element that is a main component of the metal oxide used as the metal oxide230ais preferably greater than the atomic ratio of the element M to a metal element that is a main component of the metal oxide used as the metal oxide230b. Moreover, the atomic ratio of the element M to In in the metal oxide used as the metal oxide230ais preferably greater than the atomic ratio of the element M to In in the metal oxide used as the metal oxide230b. With this structure, impurities and oxygen can be inhibited from diffusing into the metal oxide230bfrom the components formed below the metal oxide230a.

Furthermore, the atomic ratio of In to the element M in the metal oxide used as the metal oxide230bis preferably greater than the atomic ratio of In to the element M in the metal oxide used as the metal oxide230a. With this structure, the transistor200can have a high on-state current and high frequency characteristics.

When the metal oxide230aand the metal oxide230bcontain a common element as the main component besides oxygen, the density of defect states at an interface between the metal oxide230aand the metal oxide230bcan be made low. Thus, the influence of interface scattering on carrier conduction is small, and the transistor200can have a high on-state current and excellent frequency characteristics.

Specifically, as the metal oxide230a, a metal oxide with a composition of In:M:Zn=1:3:4 [atomic ratio] or in the neighborhood thereof, or a composition of In M:Zn=1:1:0.5 [atomic ratio] or in the neighborhood thereof is used. As the metal oxide230b, a metal oxide with a composition of In:M:Zn=1:1:1 [atomic ratio] or in the neighborhood thereof, a composition of In:M:Zn=1:1:1.2 [atomic ratio] or in the neighborhood thereof, a composition of In:M:Zn=1:1:2 [atomic ratio] or in the neighborhood thereof, or a composition of In:M:Zn=4:2:3 [atomic ratio] or in the neighborhood thereof can be used. Note that a composition in the neighborhood includes the range of ±30% of an intended atomic ratio. Gallium is preferably used as the element M. In the case where a single layer of the metal oxide230bis provided as the metal oxide230, a metal oxide that can be used as the metal oxide230amay be used as the metal oxide230b.

When the metal oxide is deposited by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide and may be the atomic ratio of a sputtering target used for depositing the metal oxide.

The metal oxide230bpreferably has crystallinity. It is particularly preferable to use a CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the metal oxide230b.

The CAAC-OS is a metal oxide having a dense structure with high crystallinity and a small amount of impurities and defects (for example, oxygen vacancies). In particular, after the formation of a metal oxide, heat treatment is performed at a temperature at which the metal oxide does not become a polycrystal (e.g., higher than or equal to 400° C. and lower than or equal to 600° C.), whereby a CAAC-OS having a dense structure with higher crystallinity can be obtained. When the density of the CAAC-OS is increased in such a manner, diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

A clear crystal grain boundary is difficult to observe in the CAAC-OS; thus, it can be said that a reduction in electron mobility due to the crystal grain boundary is less likely to occur. Thus, a metal oxide including a CAAC-OS is physically stable. Therefore, the metal oxide including a CAAC-OS is resistant to heat and has high reliability.

When an oxide having crystallinity, such as CAAC-OS, is used as the metal oxide230b, oxygen extraction from the metal oxide230bby the source electrode or the drain electrode can be inhibited. This can reduce oxygen extraction from the metal oxide230beven when heat treatment is performed; thus, the transistor200is stable with respect to high temperatures in a manufacturing process (what is called thermal budget).

If impurities and oxygen vacancies exist in a region of an oxide semiconductor where a channel is formed, a transistor using the oxide semiconductor may have variable electrical characteristics and poor reliability. In some cases, hydrogen in the vicinity of an oxygen vacancy forms a defect that is the oxygen vacancy into which hydrogen enters (hereinafter sometimes referred to as VOH), which generates an electron serving as a carrier. Therefore, when the region of the oxide semiconductor where a channel is formed includes oxygen vacancies, the transistor tends to have normally-on characteristics (even when no voltage is applied to the gate electrode, the channel exists and current flows through the transistor). Thus, impurities, oxygen vacancies, and VOH are preferably reduced as much as possible in the region of the oxide semiconductor where a channel is formed. In other words, it is preferable that the region of the oxide semiconductor where a channel is formed have a reduced carrier concentration and be of an i-type (intrinsic) or substantially i-type.

As a countermeasure to the above, an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) is provided in the vicinity of the oxide semiconductor and heat treatment is performed, so that oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and VOH. However, supply of an excess amount of oxygen to the source region or the drain region might cause a decrease in the on-state current or field-effect mobility of the transistor200. Furthermore, a variation of the amount of oxygen supplied to the source region or the drain region in the substrate plane leads to a variation in characteristics of the semiconductor device including the transistor. When oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as the gate electrode, the source electrode, or the drain electrode, the conductor might be oxidized and the conductivity might be impaired, for example, so that electrical characteristics and reliability of the transistor might be adversely affected.

Therefore, the region230bcfunctioning as the channel formation region in the oxide semiconductor is preferably an i-type or substantially i-type region with reduced carrier concentration, whereas the region230baand the region230bbfunctioning as the source region and the drain region are preferably n-type regions with high carrier concentrations. That is, it is preferable that oxygen vacancies and VOH in the region230bcof the oxide semiconductor be reduced and the region230baand the region230bbnot be supplied with an excess amount of oxygen. For example, oxidation of the conductor260, the conductor242a, and the conductor242b, and the like is preferably inhibited.

Thus, in this embodiment, the semiconductor device has a structure in which oxygen is efficiently supplied to the region230bcand oxidation of the conductor242a, the conductor242b, and the conductor260is inhibited.

An insulator that is likely to transmit oxygen is preferably used as the insulator250to supply oxygen to the region230bc. In particular, an insulator containing excess oxygen is preferably used as the insulator280. This structure enables oxygen contained in the insulator280to be supplied to the region230bcthrough the insulator250.

Furthermore, in order to inhibit oxidation of the conductor242a, the conductor242b, and the conductor260, an insulator having a function of inhibiting diffusion of oxygen is preferably provided in the vicinity of each of the conductor242a, the conductor242b, and the conductor260. In the semiconductor device described in this embodiment, the insulator corresponds to the insulator252, the insulator254, and the insulator275, for example.

The insulator252preferably has a barrier property against oxygen. The insulator252is provided between the insulator250and the conductor242aand between the insulator250and the conductor242b. Thus, oxygen contained in the insulator250can be inhibited from diffusing into the conductor242aand the conductor242b, and oxidation of the conductor242aand the conductor242bcan be inhibited. Alternatively, the amount of oxygen diffused into the conductor242aand the conductor242bfrom the insulator250is reduced, and a layer formed on the side surfaces of the conductor242aand the conductor242b(corresponding to a layer244aand a layer244bdescribed later) can be thin. The insulator252is provided between the insulator250and the metal oxide230b. Thus, release of oxygen from the region230bcof the metal oxide230bin heat treatment can be inhibited, for example.

Note that the thickness of the insulator252is preferably small. For example, the insulator252preferably includes a region having a thickness smaller than the thickness of the insulator250. The insulator250includes a region in contact with the top surface of the metal oxide230b. When the thickness of the insulator252is small, oxygen contained in the insulator250can be supplied to the region230bcof the metal oxide230b, and oxygen contained in the insulator250can be inhibited from being excessively supplied. The insulator252is provided between the insulator280and the insulator250and includes a region in contact with a sidewall of the opening included in the insulator280. When the thickness of the insulator252is small, oxygen contained in the insulator280can be supplied to the insulator250, and oxygen contained in the insulator280can be inhibited from being excessively supplied.

The insulator254preferably has a barrier property against oxygen. The insulator254is provided between the insulator250and the conductor260. Thus, diffusion of oxygen contained in the insulator250into the conductor260can be prevented, so that oxidation of the conductor260can be inhibited. Note that the insulator254is less permeable to oxygen than at least the insulator250is.

As the insulator275, an insulator having a function of inhibiting passage of oxygen is preferably used. The insulator275is provided between the insulator280and the conductor242aand between the insulator280and the conductor242b. The structure can inhibit diffusion of oxygen contained in the insulator280into the conductor242aand the conductor242b. Accordingly, oxidation of the conductor242aand the conductor242bby oxygen contained in the insulator280can be inhibited, so that an increase in resistivity and a reduction in on-state current can be inhibited. The insulator275is less permeable to oxygen than at least the insulator250is.

With the above structure, the region230bcfunctioning as the channel formation region can be an i-type or substantially i-type region, the region230baand the region230bbfunctioning as the source region and the drain region can be n-type regions, and thus a semiconductor device with favorable electrical characteristics can be provided. The semiconductor device with the above structure can have favorable electrical characteristics even when being miniaturized or highly integrated. For example, the semiconductor device can have favorable electrical characteristics even when a gate length is less than or equal to 20 nm, less than or equal to 15 nm, less than or equal to 10 nm, or less than or equal to 7 nm and greater than or equal to 2 nm, greater than or equal to 3 nm, or greater than or equal to 5 nm. Note that the gate length will be described later.

Furthermore, miniaturization of the transistor200can improve high-frequency characteristics. Specifically, a cutoff frequency can be improved. When the gate length is within the above range, the cutoff frequency of the transistor can be greater than or equal to 50 GHz or greater than or equal to 100 GHz at room temperature, for example.

A conductive material that is less likely to be oxidized, a conductive material having a function of inhibiting diffusion of oxygen, or the like is preferably used for the conductor242a, the conductor242b, and the conductor260. Examples of the conductive material include a conductive material containing nitrogen, a conductive material containing oxygen, and the like. Thus, a decrease in conductivity of the conductor242a, the conductor242b, and the conductor260can be inhibited. In the case where a conductive material containing metal and nitrogen is used for the conductor242a, the conductor242b, and the conductor260, the conductor242a, the conductor242b, and the conductor260contain at least metal and nitrogen.

Any one or more of the conductor242a, the conductor242b, and the conductor260may have a stacked-layer structure. For example, in the case where the conductor242aand the conductor242beach have a stacked-layer structure, a conductive material that is not easily oxidized, a conductive material having a function of inhibiting diffusion of oxygen, or the like is preferably used for a layer in contact with the metal oxide230b. For example, in the case where the conductor260has a stacked-layer structure of the conductor260aand the conductor260bas illustrated inFIG.7B, a conductive material that is less likely to be oxidized, a conductive material having a function of inhibiting diffusion of oxygen, or the like is preferably used for the conductor260a.

As the metal oxide230b, an oxide having crystallinity, such as a CAAC-OS, is preferably used. As the oxide, a metal oxide that can be used as the metal oxide230described above is preferably used. Specifically, a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin is preferably used. The CAAC-OS is an oxide including a crystal, and the c-axis of the crystal is substantially perpendicular to the surface of the oxide or a formation surface. This can inhibit the conductor242aor the conductor242bfrom extracting oxygen from the metal oxide230b. Furthermore, it is possible to inhibit a reduction in the conductivity of the conductor242aand the conductor242b.

The insulator282provided over the insulator280is preferably formed by a method in which oxygen can be added to the insulator280. Thus, excess oxygen can be contained in the insulator280.

In addition to the above structure, the semiconductor device of this embodiment has a structure in which hydrogen is inhibited from entering the transistor200. For example, an insulator having a function of inhibiting diffusion of hydrogen is provided to cover the transistor200. In the semiconductor device described in this embodiment, the insulator corresponds to, for example, the insulator212and the insulator283.

As the insulator212, an insulator having a function of inhibiting diffusion of hydrogen is preferably used. This can inhibit diffusion of hydrogen into the transistor200from below the insulator212.

As the insulator283, an insulator having a function of inhibiting diffusion of hydrogen is preferably used. This can inhibit diffusion of hydrogen into the transistor200from above the insulator283. Moreover, diffusion of hydrogen contained in the insulator274into the transistor200can be inhibited.

FIG.9is an enlarged view of the vicinity of the channel formation region inFIG.7B. The solid arrows illustrated inFIG.9visualize a state where oxygen diffuses. The dotted arrows illustrated inFIG.9visualize a state where hydrogen diffuses. With the above structure, oxygen can be efficiently supplied to the region230bcand oxidation of the conductor242a, the conductor242b, and the conductor260can be inhibited. Moreover, entry of hydrogen into the transistor200can be inhibited.

In this embodiment, microwave treatment is performed in an atmosphere containing oxygen in a state where the conductor242aand the conductor242bare provided over the metal oxide230bso that oxygen vacancies and VOH in the region230bcare reduced. Here, the microwave treatment refers to, for example, treatment using an apparatus including a power source that generates high-density plasma with the use of a microwave.

The microwave treatment in an oxygen-containing atmosphere converts an oxygen gas into plasma using a high-frequency wave such as a microwave or RF and activates the oxygen plasma. At this time, the region230bccan be irradiated with the high-frequency wave such as a microwave or RF. By the effect of the plasma, the microwave, and the like, VOH in the region230bccan be divided into an oxygen vacancy and hydrogen; the hydrogen can be removed from the region230bcand the oxygen vacancy can be filled with oxygen. As a result, the hydrogen concentration, oxygen vacancies and VOH of the region230bccan be reduced to lower the carrier concentration.

In the microwave treatment in an oxygen-containing atmosphere, the high-frequency wave such as the microwave or RF, the oxygen plasma, or the like is blocked by the conductor242aand the conductor242band does not affect the region230banor the region230bb. In addition, the effect of the oxygen plasma can be reduced by the insulator271and the insulator280that are provided to cover the metal oxide230band the conductor242. Hence, a reduction in VOH and supply of an excess amount of oxygen do not occur in the region230baor the region230bbin the microwave treatment, preventing a decrease in carrier concentration.

Microwave treatment is preferably performed in an oxygen-containing atmosphere after deposition of an insulating film to be the insulator252or after deposition of an insulating film to be the insulator250. By performing the microwave treatment in an oxygen-containing atmosphere through the insulator252or the insulator250in such a manner, oxygen can be efficiently supplied into the region230bc. In addition, the insulator252is placed to be in contact with the side surface of the conductor242and the surface of the region230bc, thereby inhibiting oxygen more than necessary from being supplied to the region230bcand inhibiting the side surface of the conductor242from being oxidized. Furthermore, the side surface of the conductor242can be inhibited from being oxidized when the insulating film to be the insulator250is deposited.

The oxygen supplied into the region230bchas any of a variety of forms such as an oxygen atom, an oxygen molecule, and an oxygen radical (an O radical, an atom or a molecule having an unpaired electron, or an ion). Note that the oxygen supplied into the region230bchas any one or more of the above forms, particularly preferably an oxygen radical. Furthermore, the film quality of the insulator252and the insulator250can be improved, leading to higher reliability of the transistor200.

In the above manner, oxygen vacancies and VOH can be selectively removed from the region230bcof the oxide semiconductor, whereby the region230bccan be an i-type or substantially i-type region. Furthermore, supply of an excess amount of oxygen to the region230baand the region230bbfunctioning as the source region and the drain region can be inhibited and the state of the n-type regions before the microwave treatment is performed can be maintained. As a result, a change in the electrical characteristics of the transistor200can be inhibited, and thus a variation in the electrical characteristics of the transistors200in the substrate plane can be inhibited.

With the above structure, a semiconductor device with a small variation in transistor characteristics can be provided. A semiconductor device with favorable reliability can also be provided. A semiconductor device having favorable electrical characteristics can be provided. Alternatively, a semiconductor device that can be miniaturized or highly integrated can be provided.

As illustrated inFIG.7C, a curved surface may be provided between the side surface of the metal oxide230band the top surface of the metal oxide230bin a cross-sectional view of the transistor200in the channel width direction. In other words, an end portion of the side surface and an end portion of the top surface may be curved (hereinafter referred to as rounded).

The radius of curvature of the curved surface is preferably greater than 0 nm and less than the thickness of the metal oxide230bin a region overlapping with the conductor242, or less than half of the length of a region that does not have the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than or equal to 20 nm, preferably greater than or equal to 1 nm and less than or equal to 15 nm, and further preferably greater than or equal to 2 nm and less than or equal to 10 nm. Such a shape can improve the coverage of the metal oxide230bwith the insulator252, the insulator250, the insulator254, and the conductor260.

For example, as illustrated inFIG.7C, the insulator252formed using aluminum oxide or the like is provided in contact with the top surface and the side surface of the metal oxide230, whereby indium contained in the metal oxide230is unevenly distributed, in some cases, at the interface between the metal oxide230and the insulator252and in its vicinity. Accordingly, the vicinity of the surface of the metal oxide230has an atomic ratio close to that of an indium oxide or that of an In—Zn oxide. Such an increase in the atomic ratio of indium in the vicinity of the surface of the metal oxide230, especially the vicinity of the surface of the metal oxide230b, can increase the field-effect mobility of the transistor200.

At least one of the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285preferably functions as a barrier insulating film, which inhibits diffusion of impurities such as water and hydrogen from the substrate side or above the transistor200into the transistor200. Thus, for at least one of the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285, it is preferable to use an insulating material having a function of inhibiting diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, or NO2), or copper atoms (an insulating material through which the impurities are less likely to pass). Alternatively, it is preferable to use an insulating material having a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (an insulating material through which the oxygen is less likely to pass).

Note that in this specification, a barrier insulating film refers to an insulating film having a barrier property. A barrier property in this specification means a function of inhibiting diffusion of a targeted substance (also referred to as having low permeability). In addition, a barrier property in this specification means a function of capturing and fixing (also referred to as gettering) a targeted substance.

An insulator having a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen is preferably used for the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285; for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride or the like, which has a higher hydrogen barrier property, is preferably used for the insulator212, the insulator275, and the insulator283. For example, aluminum oxide, magnesium oxide, or the like, which has a function of capturing or fixing hydrogen well, is preferably used for the insulator214, the insulator271, the insulator282, and the insulator285. In this case, impurities such as water and hydrogen can be inhibited from diffusing to the transistor200side from the substrate side through the insulator212and the insulator214. Impurities such as water and hydrogen can be inhibited from diffusing to the transistor200side from an interlayer insulating film and the like which are provided outside the insulator285. Alternatively, oxygen contained in the insulator224and the like can be inhibited from diffusing to the substrate side through the insulator212and the insulator214. Alternatively, oxygen contained in the insulator280and the like can be inhibited from diffusing above the transistor200through the insulator282and the like. In this manner, it is preferable that the transistor200be surrounded by the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285, which have a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen.

Here, an oxide having an amorphous structure is preferably used for the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285. For example, a metal oxide such as AlOx(x is a given number greater than 0) or MgOy(y is a given number greater than 0) is preferably used. In such a metal oxide having an amorphous structure, an oxygen atom has a dangling bond and sometimes has a property of capturing or fixing hydrogen with the dangling bond. When such a metal oxide having an amorphous structure is used as the component of the transistor200or provided around the transistor200, hydrogen contained in the transistor200or hydrogen around the transistor200can be captured or fixed. In particular, hydrogen contained in the channel formation region of the transistor200is preferably captured or fixed. The metal oxide having an amorphous structure is used as the component of the transistor200or provided around the transistor200, whereby the transistor200and a semiconductor device which have favorable characteristics and high reliability can be manufactured.

Although each of the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285preferably has an amorphous structure, a region having a polycrystalline structure may be partly formed. Alternatively, each of the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285may have a multilayer structure in which a layer having an amorphous structure and a layer having a polycrystalline structure are stacked. For example, a stacked-layer structure in which a layer having a polycrystalline structure is formed over a layer having an amorphous structure may be employed.

The insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285can be deposited by a sputtering method, for example. Since a sputtering method does not need to use a molecule containing hydrogen as a deposition gas, the hydrogen concentrations in the insulator212, the insulator214, the insulator271, the insulator275, the insulator282, the insulator283, and the insulator285can be reduced. Note that the deposition method is not limited to a sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like may be used as appropriate.

The resistivities of the insulator212, the insulator275, and the insulator283are preferably low in some cases. For example, by setting the resistivities of the insulator212, the insulator275, and the insulator283to approximately 1×1013Ωcm, the insulator212, the insulator275, and the insulator283can sometimes reduce charge up of the conductor205, the conductor242, the conductor260, or the conductor246in treatment using plasma or the like in the manufacturing process of a semiconductor device. The resistivities of the insulator212, the insulator275, and the insulator283are preferably higher than or equal to 1×1010Ωcm and lower than or equal to 1×1015Ωcm.

The insulator216, the insulator274, the insulator280, and the insulator285each preferably have a lower permittivity than the insulator214. When a material with a low permittivity is used for an interlayer film, parasitic capacitance generated between wirings can be reduced. For the insulator216, the insulator274, the insulator280, and the insulator285, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like is used as appropriate, for example.

In this specification and the like, silicon oxynitride refers to a material that contains oxygen at a higher proportion than nitrogen, and silicon nitride oxide refers to a material that contains nitrogen at a higher proportion than oxygen. Moreover, in this specification, aluminum oxynitride refers to a material that has a higher oxygen content than a nitrogen content, and aluminum nitride oxide refers to a material that has a higher nitrogen content than an oxygen content.

The conductor205is placed to overlap with the metal oxide230and the conductor260. Here, the conductor205is preferably provided to be embedded in an opening formed in the insulator216. Part of the conductor205is embedded in the insulator214in some cases.

The conductor205includes the conductor205aand the conductor205b. The conductor205ais provided in contact with the bottom surface and the sidewall of the opening. The conductor205bis provided to be embedded in a depressed portion formed in the conductor205a. Here, the top surface of the conductor205bis substantially level with top surfaces of the conductor205aand the insulator216.

Here, for the conductor205a, it is preferable to use a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, or the like), and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like).

When the conductor205ais formed using a conductive material having a function of inhibiting diffusion of hydrogen, impurities such as hydrogen contained in the conductor205bcan be prevented from diffusing into the metal oxide230through the insulator216, the insulator224, and the like. When the conductor205ais formed using a conductive material having a function of inhibiting diffusion of oxygen, the conductivity of the conductor205bcan be inhibited from being lowered because of oxidation. As the conductive material having a function of inhibiting diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Thus, the conductor205amay be a single layer or a stacked layer of the above conductive materials. For example, titanium nitride is used for the conductor205a.

Moreover, the conductor205bis preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. For example, tungsten is used for the conductor205b.

The conductor205sometimes functions as a second gate electrode. In that case, by changing a potential applied to the conductor205out of synchronization with and independently of a potential applied to the conductor260, the threshold voltage (Vth) of the transistor200can be controlled. In particular, Vth of the transistor200can be higher in the case where a negative potential is applied to the conductor205, and the off-state current can be reduced. Thus, a drain current at the time when a potential applied to the conductor260is 0 V can be lower in the case where a negative potential is applied to the conductor205than in the case where the negative potential is not applied to the conductor205.

The electric resistivity of the conductor205is designed in consideration of the potential applied to the conductor205, and the thickness of the conductor205is determined in accordance with the electric resistivity. The thickness of the insulator216is substantially equal to that of the conductor205. The conductor205and the insulator216are preferably as thin as possible in the allowable range of the design of the conductor205. When the thickness of the insulator216is reduced, the absolute amount of impurity such as hydrogen contained in the insulator216can be reduced, inhibiting the diffusion of the impurity into the metal oxide230.

As illustrated inFIG.7A, the conductor205is preferably provided to be larger than a region of the metal oxide230that does not overlap with the conductor242aor the conductor242b. As illustrated inFIG.7C, it is particularly preferable that the conductor205extend to a region outside end portions of the metal oxide230aand the metal oxide230bin the channel width direction. That is, the conductor205and the conductor260preferably overlap with each other with the insulators therebetween on the outer side of the side surface of the metal oxide230in the channel width direction. With this structure, the channel formation region of the metal oxide230can be electrically surrounded by the electric field of the conductor260functioning as a first gate electrode and the electric field of the conductor205functioning as the second gate electrode. In this specification, a transistor structure in which a channel formation region is electrically surrounded by electric fields of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

In this specification and the like, a transistor having the S-channel structure refers to a transistor having a structure in which a channel formation region is electrically surrounded by an electric field of one or the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like has a structure that is different from a Fin-type structure and a planar structure. Meanwhile, the S-channel structure disclosed in this specification and the like can also be regarded as a kind of the Fin-type structure. Note that in this specification and the like, the Fin-type structure refers to a structure in which a gate electrode is placed so as to cover at least two or more surfaces (specifically, two surfaces, three surfaces, four surfaces, or the like) of a channel. With the Fin-type structure and the S-channel structure, resistance to a short-channel effect can be enhanced, that is, a transistor in which a short-channel effect is less likely to occur can be provided.

When the transistor200becomes normally-off and has the above-described S-Channel structure, the channel formation region can be electrically surrounded. Accordingly, the transistor200can be regarded as having a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. When the transistor200has the S-Channel structure, the GAA structure, or the LGAA structure, the channel formation region that is formed at the interface between the metal oxide230and the gate insulator or in the vicinity of the interface can be formed in the entire bulk of the metal oxide230. Accordingly, the density of current flowing in the transistor can be improved, and it can be expected to improve the on-state current of the transistor or increase the field-effect mobility of the transistor.

Note that althoughFIG.7AtoFIG.7Dillustrate an example of a transistor with an S-channel structure as the transistor200, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, a transistor structure that can be used in one embodiment of the present invention is one or more selected from a planar structure, a Fin-type structure, and a GAA structure.

Furthermore, as illustrated inFIG.7C, the conductor205is extended to function as a wiring as well. However, without limitation to this structure, a structure in which a conductor functioning as a wiring is provided below the conductor205may be employed. In addition, the conductor205is not necessarily provided in each transistor. For example, the conductor205may be shared by a plurality of transistors.

Although the transistor200having a structure in which the conductor205is a stack of the conductor205aand the conductor205bis illustrated, the present invention is not limited thereto. For example, the conductor205may be provided to have a single-layer structure or a stacked-layer structure of three or more layers.

The insulator222and the insulator224function as a gate insulator.

It is preferable that the insulator222have a function of inhibiting diffusion of hydrogen (e.g., at least one of a hydrogen atom, a hydrogen molecule, and the like). In addition, it is preferable that the insulator222have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like). For example, the insulator222preferably has a function of inhibiting diffusion of one or both of hydrogen and oxygen more than the insulator224.

As the insulator222, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material, is preferably used. For the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Alternatively, an oxide containing hafnium and zirconium, e.g., a hafnium-zirconium oxide is preferably used. In the case where the insulator222is formed using such a material, the insulator222functions as a layer that inhibits release of oxygen from the metal oxide230to the substrate side and diffusion of impurities such as hydrogen from the periphery of the transistor200into the metal oxide230. Thus, providing the insulator222can inhibit diffusion of impurities such as hydrogen into the transistor200and inhibit generation of oxygen vacancies in the metal oxide230. Moreover, the conductor205can be inhibited from reacting with oxygen contained in the insulator224and the metal oxide230.

For example, a single layer or stacked layers of an insulator(s) containing what is called a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium-zirconium oxide may be used for the insulator222. As miniaturization and high integration of transistors progress, a problem such as a leakage current may arise because of a thinner gate insulator. When a high-k material is used for the insulator functioning as a gate insulator, a gate potential at the time of the operation of the transistor can be reduced while the physical thickness is maintained. Furthermore, a substance with a high permittivity such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3(BST) may be used for the insulator222.

Silicon oxide or silicon oxynitride, for example, can be used as appropriate for the insulator224that is in contact with the metal oxide230.

In the manufacturing process of the transistor200, heat treatment is preferably performed with the surface of the metal oxide230exposed. For example, the heat treatment is performed at higher than or equal to 100° C. and lower than or equal to 600° C., preferably higher than or equal to 350° C. and lower than or equal to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This can supply oxygen to the metal oxide230to reduce oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for oxygen released, after heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere successively after heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.

Note that by supplying oxygen to the metal oxide230, the amount of oxygen vacancies in the metal oxide230can be repaired. Furthermore, hydrogen remaining in the metal oxide230reacts with supplied oxygen, so that the hydrogen can be removed as H2O (dehydration). This can inhibit recombination of hydrogen remaining in the metal oxide230with oxygen vacancies and formation of VOH.

Note that the insulator222and the insulator224may each have a stacked-layer structure of two or more layers. In that case, without limitation to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed. The insulator224may be formed into an island shape so as to overlap with the metal oxide230a. In this case, the insulator275is in contact with the side surfaces of the insulator224and the top surface of the insulator222. Note that in this specification and the like, the term “island shape” refers to a state where two or more layers formed using the same material in the same step are physically separated from each other.

The conductor242aand the conductor242bare provided in contact with the top surface of the metal oxide230b. Each of the conductor242aand the conductor242bfunctions as a source electrode or a drain electrode of the transistor200.

For the conductor242(the conductor242aand the conductor242b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. As another example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are each a conductive material that is not easily oxidized or a material that maintains the conductivity even after absorbing oxygen.

Note that hydrogen contained in the metal oxide230bor the like diffuses into the conductor242aor the conductor242bin some cases. In particular, when a nitride containing tantalum is used for the conductor242aand the conductor242b, hydrogen contained in the metal oxide230bor the like is likely to diffuse into the conductor242aor the conductor242b, and the diffused hydrogen is bonded to nitrogen contained in the conductor242aor the conductor242bin some cases. That is, hydrogen contained in the metal oxide230bor the like is absorbed by the conductor242aor the conductor242bin some cases.

No curved surface is preferably formed between the side surface of the conductor242and the top surface of the conductor242. When no curved surface is formed in the conductor242, the conductor242can have a large cross-sectional area in the channel width direction as illustrated inFIG.7D. Accordingly, the conductivity of the conductor242is increased, so that the on-state current of the transistor200can be increased.

When heat treatment is performed in the state where the conductor242a(conductor242b) and the metal oxide230bare in contact with each other, the sheet resistance of the metal oxide230bin a region overlapping with the conductor242a(conductor242b) is decreased in some cases. Furthermore, the carrier concentration is sometimes increased. Thus, the resistance of the metal oxide230bin the region overlapping with the conductor242a(conductor242b) can be lowered in a self-aligned manner.

The insulator271ais provided in contact with the top surface of the conductor242a, and the insulator271bis provided in contact with the top surface of the conductor242b. The insulator271preferably functions as at least a barrier insulating film against oxygen. Thus, the insulator271preferably has a function of inhibiting oxygen diffusion. For example, the insulator271preferably has a function of inhibiting diffusion of oxygen more than the insulator280. As the insulator271, an insulator such as silicon nitride, aluminum oxide, or magnesium oxide is used, for example.

The insulator275is provided to cover the insulator224, the metal oxide230a, the metal oxide230b, the conductor242, and the insulator271. Specifically, the insulator275includes a region in contact with the side surface of the metal oxide230b, the side surface of the conductor242a, and the side surface of the conductor242b. The insulator275preferably has a function of capturing and fixing hydrogen. In that case, the insulator275preferably includes silicon nitride, or a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide or magnesium oxide. Alternatively, for example, a stacked-layer film of aluminum oxide and silicon nitride over the aluminum oxide may be used as the insulator275.

When the above insulator271and the insulator275are provided, the conductor242can be surrounded by the insulators having a barrier property against oxygen. That is, oxygen contained in the insulator224and the insulator280can be prevented from diffusing into the conductor242. As a result, the conductor242can be inhibited from being directly oxidized by oxygen contained in the insulator224and the insulator280, so that an increase in resistivity and a reduction in on-state current can be inhibited.

The insulator252functions as part of the gate insulator. As the insulator252, a barrier insulating film against oxygen is preferably used. As the insulator252, an insulator that can be used as the insulator282described above is preferably used. An insulator containing an oxide of one or both of aluminum and hafnium may be used as the insulator252. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In this embodiment, aluminum oxide is used for the insulator252. In this case, the insulator252contains at least oxygen and aluminum.

As illustrated inFIG.7C, the insulator252is provided in contact with the top surface and the side surface of the metal oxide230b, the side surface of the metal oxide230a, the side surface of the insulator224, and the top surface of the insulator222. That is, the regions of the metal oxide230a, the metal oxide230b, and the insulator224that overlap with the conductor260are covered with the insulator252in the cross section in the channel width direction. With this structure, the insulator252having a barrier property against oxygen can prevent release of oxygen from the metal oxide230aand the metal oxide230bat the time of heat treatment, for example. This can inhibit formation of oxygen vacancies in the metal oxide230aand the metal oxide230b. Therefore, oxygen vacancies and VOH formed in the region230bccan be reduced. Thus, the transistor200can have favorable electrical characteristics and higher reliability.

Even when an excess amount of oxygen is contained in the insulator280, the insulator250and the like, oxygen can be inhibited from being excessively supplied to the metal oxide230aand the metal oxide230b. Thus, the region230baand the region230bbare inhibited from being excessively oxidized by oxygen through the region230bc; a reduction in on-state current or field-effect mobility of the transistor200can be inhibited.

As illustrated inFIG.7B, the insulator252is provided in contact with the side surfaces of the conductor242, the insulator271, the insulator275, and the insulator280. This can inhibit formation of an oxide film on the side surfaces of the conductor242by oxidization of the side surfaces. Accordingly, a reduction in on-state current or field-effect mobility of the transistor200can be inhibited.

Furthermore, the insulator252needs to be provided in an opening formed in the insulator280and the like, together with the insulator254, the insulator250, and the conductor260. The thickness of the insulator252is preferably thin for miniaturization of the transistor200. The thickness of the insulator252is greater than or equal to 0.1 nm and less than or equal to 5.0 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm, further preferably greater than or equal to 1.0 nm and less than 3.0 nm. In this case, at least part of the insulator252preferably includes a region having the above-described thickness. The thickness of the insulator252is preferably smaller than that of the insulator250. In this case, at least part of the insulator252preferably includes a region having a thickness smaller than that of the insulator250.

To form the insulator252having a small thickness as described above, an ALD method is preferably used for deposition. Examples of an ALD method include a thermal ALD method, in which a precursor and a reactant react with each other only by a thermal energy, and a PEALD (Plasma Enhanced ALD) method, in which a reactant excited by plasma is used. The use of plasma in a PEALD method is sometimes preferable because deposition at a lower temperature is possible.

An ALD method, which enables an atomic layer to be deposited one by one has advantages such as deposition of an extremely thin film, deposition on a component with a high aspect ratio, deposition of a film with a small number of defects such as pinholes, deposition with excellent coverage, and low-temperature deposition. Therefore, the insulator252can be deposited on the side surface of the opening formed in the insulator280, for example, to have a small thickness like the above-described thickness and to have favorable coverage.

Note that some of precursors usable in an ALD method contain carbon, for example. Thus, in some cases, a film provided by an ALD method contains impurities such as carbon in a larger amount than a film provided by another deposition method. Note that impurities can be quantified by secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or auger electron spectroscopy (AES).

Note that appropriate adjustment of the deposition condition of the insulating film to be the insulator250, the microwave treatment condition in an oxygen-containing atmosphere, the amount of oxygen added to the insulator280by deposition of the insulator282, and the like can reduce oxygen vacancies and VOH formed in the region230bcand inhibit excess oxidation of the region230baand the region230bbin some cases. In such a case, the structure without the insulator252enables simplification of the manufacturing process and the improvement in productivity of the semiconductor device.

The insulator250functions as part of the gate insulator. The insulator250is preferably placed in contact with the top surface of the insulator252. The insulator250can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like. In particular, silicon oxide and silicon oxynitride, which are thermally stable, are preferable. The insulator250in this case is an insulator containing at least oxygen and silicon.

As in the insulator224, the concentration of impurities such as water and hydrogen in the insulator250is preferably reduced. The thickness of the insulator250is preferably greater than or equal to 1 nm and less than or equal to 20 nm, further preferably greater than or equal to 0.5 nm and less than or equal to 15 nm. In particular, in order to form a minute transistor (e.g., a transistor with a gate length less than or equal to 10 nm), the thickness of the insulator250is preferably greater than or equal to 0.5 nm and less than or equal to 10 nm, further preferably greater than or equal to 0.5 nm and less than or equal to 5 nm. In this case, at least part of the insulator250preferably includes a region having the above-described thickness.

AlthoughFIG.7AtoFIG.7DandFIG.8Aillustrate a single-layer structure of the insulator250, the present invention is not limited to this structure, and a stacked-layer structure of two or more layers may be employed. For example, as illustrated inFIG.8B, the insulator250may have a stacked-layer structure including two layers of an insulator250aand an insulator250bover the insulator250a.

Note that the insulator252, the insulator250, and the insulator254function as a gate insulating film (also referred to as a top gate insulating film or TGI) of the transistor. The thickness of the gate insulating film is preferably within a range of 1.3 nm to 10 nm inclusive, further preferably 1.5 nm to 5 nm inclusive. Note that the thickness of the gate insulating film in the above transistor is an equivalent oxide thickness (EOT). Note that the equivalent oxide thickness is a value obtained by converting the physical thickness of a film to the electrical thickness equivalent for silicon oxide.

For example, when aluminum oxide, silicon oxide, and silicon nitride are used for the insulator252, the insulator250, and the insulator254, respectively, the total thickness of the insulator252, the insulator250, and the insulator254is converted into the equivalent oxide thickness.

When the thickness of the gate insulating film is within the above-described range, a subthreshold swing value (S value) which is one of the characteristics of a transistor can be reduced. For example, when a channel length L of an OSFET is within a range of 3 nm to 10 nm inclusive and the thickness of a gate insulating film of the OSFET is within a range of 1.5 nm to 5 nm inclusive, the S value of the OSFET can be greater than or equal to 60 mV/dec. and less than or equal to 200 mV/dec., preferably greater than or equal to 60 mV/dec. and less than or equal to 100 mV/dec., further preferably greater than or equal to 60 mV/dec. and less than or equal to 80 mV/dec. When the thickness of the gate insulating film in the OSFET is within the above range, the frequency characteristics (f characteristics) of a transistor is improved in some cases. In the case of the above-described OSFET, the transistor can operate at a drain voltage (Vd) and agate voltage (Vg) that are each within a range of 0.5 V to 3 V inclusive.

In the case where the insulator250has a stacked-layer structure of two layers as illustrated inFIG.8B, it is preferable that the insulator250ain a lower layer be formed using an insulator that is likely to transmit oxygen and the insulator250bin an upper layer be formed using an insulator having a function of inhibiting oxygen diffusion. With such a structure, oxygen contained in the insulator250acan be inhibited from diffusing into the conductor260. That is, a reduction in the amount of oxygen supplied to the metal oxide230can be inhibited. In addition, oxidation of the conductor260due to oxygen contained in the insulator250acan be inhibited. For example, it is preferable that the insulator250abe provided using any of the above-described materials that can be used for the insulator250and the insulator250bbe provided using an insulator containing an oxide of one or both of aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In this embodiment, hafnium oxide is used as the insulator250b. In this case, the insulator250bcontains at least oxygen and hafnium. The thickness of the insulator250bis greater than or equal to 0.5 nm and less than or equal to 5.0 nm, preferably greater than or equal to 1.0 nm and less than or equal to 5.0 nm, further preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm. In that case, at least part of the insulator250bpreferably includes a region having the above-described thickness.

In the case where silicon oxide, silicon oxynitride, or the like is used for the insulator250a, the insulator250bmay be formed using an insulating material that is a high-k material having a high relative permittivity. The gate insulator having a stacked-layer structure of the insulator250aand the insulator250bcan be thermally stable and can have a high relative permittivity. Accordingly, a gate potential applied during the operation of the transistor can be reduced while the physical thickness of the gate insulator is maintained. In addition, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. Therefore, the withstand voltage of the insulator250can be increased.

The insulator254functions as part of a gate insulator. As the insulator254, a barrier insulating film against hydrogen is preferably used. This can prevent diffusion of impurities such as hydrogen contained in the conductor260into the insulator250and the metal oxide230b. As the insulator254, an insulator that can be used as the insulator283described above may be used. For example, silicon nitride deposited by a PEALD method may be used as the insulator254. In this case, the insulator254contains at least nitrogen and silicon.

Furthermore, the insulator254may have a barrier property against oxygen. Thus, diffusion of oxygen contained in the insulator250into the conductor260can be inhibited.

Furthermore, the insulator254needs to be provided in an opening formed in the insulator280and the like, together with the insulator252, the insulator250, and the conductor260. The thickness of the insulator254is preferably small for miniaturization of the transistor200. The thickness of the insulator254is greater than or equal to 0.1 nm and less than or equal to 5.0 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm, further preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm. In this case, at least part of the insulator254preferably includes a region having the above-described thickness. The thickness of the insulator254is preferably smaller than that of the insulator250. In this case, at least part of the insulator254preferably include a region having a thickness that is smaller than that of the insulator250.

Note that in the case where the insulator250has a stacked-layer structure of two layers as illustrated inFIG.8B, an insulator having a function of inhibiting the passage of oxygen and impurities such as hydrogen, e.g., hafnium oxide, is used as the insulator250b, whereby the insulator250bcan also have the function of the insulator254. In such a case, the structure without the insulator254enables simplification of the manufacturing process and the improvement in productivity of the semiconductor device.

The conductor260functions as the first gate electrode of the transistor200. The conductor260preferably includes the conductor260aand the conductor260bplaced over the conductor260a. For example, the conductor260ais preferably placed to cover the bottom surface and the side surface of the conductor260b. Moreover, as illustrated inFIG.7BandFIG.7C, the top surface of the conductor260is substantially level with the top surface of the insulator250. Although the conductor260has a two-layer structure of the conductor260aand the conductor260binFIG.7BandFIG.7C, the conductor260may have a single-layer structure or a stacked-layer structure of three or more layers.

For the conductor260a, a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule, and a copper atom is preferably used. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like).

In addition, when the conductor260ahas a function of inhibiting diffusion of oxygen, the conductivity of the conductor260bcan be inhibited from being lowered because of oxidation due to oxygen contained in the insulator250. As the conductive material having a function of inhibiting diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

The conductor260also functions as a wiring and thus is preferably formed using a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used for the conductor260b. The conductor260bmay have a stacked-layer structure; for example, a stacked-layer structure of the conductive material and titanium or titanium nitride may be employed.

In the transistor200, the conductor260is formed in a self-aligned manner to fill the opening formed in the insulator280, for example. The formation of the conductor260in this manner allows the conductor260to be placed properly in a region between the conductor242aand the conductor242bwithout alignment.

As illustrated inFIG.7C, in the channel width direction of the transistor200, with reference to the bottom surface of the insulator222, the level of the bottom surface of the conductor260in a region where the conductor260and the metal oxide230bdo not overlap with each other is preferably lower than the level of the bottom surface of the metal oxide230b. When the conductor260functioning as the gate electrode covers the side surface and the top surface of the channel formation region of the metal oxide230bwith the insulator250, for example, therebetween, the electric field of the conductor260can easily act on the entire channel formation region of the metal oxide230b. Thus, the on-state current of the transistor200can be increased and the frequency characteristics of the transistor200can be improved. With a reference to the bottom surface of the insulator222, the difference between the level of the bottom surface of the conductor260in a region where the conductor260do not overlap with the metal oxide230aor the metal oxide230band the level of the bottom surface of the metal oxide230bis greater than or equal to 0 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm, further preferably greater than or equal to 5 nm and less than or equal to 20 nm.

The insulator280is provided over the insulator275, and the opening is formed in a region where the insulator250and the conductor260are to be provided. In addition, the top surface of the insulator280may be planarized.

The insulator280functioning as an interlayer film preferably has a low permittivity. When a material with a low permittivity is used for an interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator280is preferably provided using a material similar to that for the insulator216, for example. In particular, silicon oxide and silicon oxynitride, which are thermally stable, are preferable. In particular, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferably used, in which case a region containing oxygen released by heating can be easily formed.

The concentration of impurities such as water and hydrogen in the insulator280is preferably reduced. An oxide containing silicon, such as silicon oxide or silicon oxynitride, is used as appropriate for the insulator280, for example.

The insulator282preferably functions as a barrier insulating film that inhibits impurities such as water and hydrogen from diffusing into the insulator280from above and preferably has a function of capturing impurities such as hydrogen. The insulator282preferably functions as a barrier insulating film that inhibits passage of oxygen. For the insulator282, a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide can be used. In this case, the insulator282contains at least oxygen and aluminum. The insulator282, which has a function of capturing impurities such as hydrogen, is provided in contact with the insulator280in a region interposed between the insulator212and the insulator283, whereby impurities such as hydrogen contained in the insulator280, for example, can be captured and the amount of hydrogen in the region can be constant. It is preferable to use, in particular, aluminum oxide having an amorphous structure for the insulator282, because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor200and a semiconductor device which have favorable characteristics and high reliability can be manufactured.

As the insulator282, aluminum oxide is preferably deposited by a sputtering method, further preferably, aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas. The use of the pulsed DC sputtering method can achieve more uniform film thickness and improve the sputtering rate and film quality. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen implanted to a layer below the insulator282can be controlled depending on the amount of the RF power applied to the substrate. For example, the amount of oxygen implanted into the layer below the insulator282is smaller as the RF power is lower, and the amount of oxygen is easily saturated even when the insulator282has a small thickness. Moreover, the amount of oxygen implanted into the layer below the insulator282is larger as the RF power is higher.

The RF power is higher than or equal to 0 W/cm2and lower than or equal to 1.86 W/cm2, for example. In other words, an appropriate amount of oxygen for the transistor characteristics can be changed and implanted by RF power used for the formation of the insulator282. Accordingly, an appropriate amount of oxygen for improving the reliability of the transistor can be supplied.

The RF frequency is preferably greater than or equal to 10 MHz. The typical frequency is 13.56 MHz. The higher the RF frequency is, the less damage the substrate gets.

The insulator283is in contact with part of the top surface of the insulator214, the side surface of the insulator216, the side surface of an insulator222, the side surface of an insulator275, the side surface of the insulator280, and the side surface and the top surface of the insulator282.

The insulator283functions as a barrier insulating film that inhibits impurities such as water and hydrogen from diffusing into the insulator280from above. The insulator283is placed over the insulator282. The insulator283is preferably formed using a nitride containing silicon such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by a sputtering method may be used for the insulator283. When the insulator283is deposited by a sputtering method, a high-density silicon nitride film can be formed. To obtain the insulator283, silicon nitride deposited by a PEALD method or a CVD method may be stacked over silicon nitride deposited by a sputtering method.

For the conductor240aand the conductor240b, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used. The conductor240aand the conductor240bmay each have a stacked-layer structure.

In the case where the conductor240has a stacked-layer structure, a conductive material having a function of inhibiting passage of impurities such as water and hydrogen is preferably used for a first conductor placed in the vicinity of the insulator285, the insulator283, the insulator282, the insulator280, the insulator275, and the insulator271. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. The conductive material having a function of inhibiting passage of impurities such as water and hydrogen may be used as a single layer or stacked layers. Moreover, impurities such as water and hydrogen contained in a layer above the insulator283can be inhibited from entering the metal oxide230through the conductor240aand the conductor240b.

For the insulator241aand the insulator241b, a barrier insulating film that can be used for the insulator275or the like may be used. For the insulator241aand the insulator241b, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator241aand the insulator241bare provided in contact with the insulator283, the insulator282, and the insulator271, impurities such as water and hydrogen contained in the insulator280or the like can be inhibited from entering the metal oxide230through the conductor240aand the conductor240b. In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Furthermore, oxygen contained in the insulator280can be prevented from being absorbed by the conductor240aand the conductor240b.

When the insulator241aand the insulator241beach have a stacked-layer structure illustrated inFIG.7B, a first insulator in contact with an inner wall of the opening formed in the insulator280and the like and a second insulator on the inner side of the first insulator are preferably formed using a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

For example, aluminum oxide deposited by an ALD method may be used as the first insulator and silicon nitride deposited by a PEALD method may be used as the second insulator. With this structure, oxidation of the conductor240can be inhibited, and hydrogen can be inhibited from entering the conductor240.

The conductor246(the conductor246aand the conductor246b) functioning as a wiring may be placed in contact with the top surface of the conductor240aand the top surface of the conductor240b. The conductor246is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Furthermore, the conductor may have a stacked-layer structure and may be a stacked layer of titanium or titanium nitride and the conductive material, for example. Note that the conductor may be formed so as to be embedded in an opening provided in an insulator.

FIG.10AandFIG.10Bare cross-sectional views illustrating a structure example of the transistor200and its periphery, which is a modification example of the structure illustrated inFIG.7BandFIG.7C.FIG.10Aillustrates a structure example of the transistor200in the channel length direction, andFIG.10Billustrates a structure example of the transistor200in the channel width direction. The structure illustrated inFIG.10AandFIG.10Bis different from the structure illustrated inFIG.7BandFIG.7Cin that the conductor205functioning as the second gate electrode of the transistor200is not provided.

Since the conductor205is not provided in the transistor200illustrated inFIG.10AandFIG.10B, neither the insulator222nor the insulator224functions as a gate insulator. Here, since the metal oxide230in which the channel formation region of the transistor200is formed is provided over the insulator224, it can be said that the transistor200is provided over the insulator224. Thus, the insulator224can be referred to as a base insulator.

The insulator224can be separated for each transistor. Thus, a plurality of insulators224are provided in the semiconductor device including a plurality of transistors200. The plurality of insulators224are collectively referred to as a base insulator group in some cases.

As illustrated inFIG.10B, the conductor260functioning as the gate electrode of the transistor200covers the top surfaces of the metal oxide230and the insulator224and the side surfaces of the metal oxide230and the insulator224in the channel width direction with the insulator252, the insulator250, and the insulator254functioning as the gate insulator of the transistor200therebetween. For example, the conductor260covers the top surfaces of the metal oxide230and the insulator224, the entire side surface of the metal oxide230in the channel width direction of the transistor200, and at least part of the side surface of the insulator224in the channel width direction of the transistor200with the insulator252, the insulator250, and the insulator254therebetween. That is, the transistor200illustrated inFIG.10Bcan be referred to as a Fin-type transistor.

The effective channel width is increased in the transistor200that is an OS transistor, whereby the on-state characteristics of the transistor200can be improved. In addition, contribution of the electric field of the gate electrode can be increased, so that the off-state characteristics of the transistor200can be improved.

FIG.11AandFIG.11Bare cross-sectional views illustrating a structure example of a transistor300, which is a Si transistor included in the semiconductor device of one embodiment of the present invention, and its periphery. Here,FIG.11Ais a cross-sectional view of the transistor300in the channel length direction andFIG.11Bis a cross-sectional view of the transistor300in the channel width direction.

The transistor300can be provided in the layer11illustrated inFIG.2,FIG.3,FIG.5, andFIG.6. For example, the transistor300can be used as the transistor41pillustrated inFIG.3and as the transistor MR3and the transistor MS3illustrated inFIG.6.

The transistor300is provided on a substrate310and includes an element isolation layer312, a conductor316, an insulator315, a semiconductor region313that is part of the substrate310, and a low-resistance region314aand a low-resistance region314bfunctioning as a source region and a drain region. The semiconductor region313can be a channel formation region of the transistor300. The insulator315functions as a gate insulator of the transistor300, and the conductor316functions as a gate electrode of the transistor300.

A silicon substrate, for example, a single crystal silicon substrate is used as the substrate310. The substrate310may contain Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. For the substrate310, a structure using silicon whose effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor300may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like for the substrate310.

As illustrated inFIG.11B, the semiconductor region313that is a part of the substrate310has a convex portion. In the transistor300, the top surface and the side surface in the channel width direction of the semiconductor region313are covered with the conductor316with the insulator315therebetween. Such a Fin-type transistor300can have an increased effective channel width, and thus the transistor300can have improved on-state characteristics. In addition, contribution of the electric field of the gate electrode can be increased, so that the off-state characteristics of the transistor300can be improved.

The low-resistance region314aand the low-resistance region314bcontain an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, in addition to the semiconductor material used in the semiconductor region313.

For the conductor316functioning as a gate electrode, a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, or a conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

Note that since the work function of a conductor depends on the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Moreover, in order to ensure both conductivity and embeddability, it is preferable to use stacked layers of metal materials such as tungsten or aluminum for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

The element isolation layer312is provided to separate a plurality of transistors formed on the substrate310from each other. The element isolation layer can be formed by, for example, a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa isolation method, or the like.

Over the transistor300, an insulator320, an insulator322, an insulator324, and an insulator326are stacked in this order from the substrate310side.

For the insulator320, the insulator322, the insulator324, and the insulator326, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used, for example.

The insulator322may have a function of a planarization film for planarizing a level difference caused by the transistor300or the like covered with the insulator320and the insulator322. For example, the top surface of the insulator322may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method to improve planarity.

As the insulator324, it is preferable to use a film having a barrier property that prevents diffusion of hydrogen, impurities, and the like from the substrate310, the transistor300, or the like into a region where the transistor200that can be an OS transistor is provided. As described above, the transistor300is provided in the layer11illustrated inFIG.2,FIG.3,FIG.5, andFIG.6, and the transistor200is provided in the layer12over the layer11.

For the film having a barrier property against hydrogen, silicon nitride deposited by a CVD method can be used, for example. Here, diffusion of hydrogen to an OS transistor such as the transistor200degrades the characteristics of the transistor in some cases. Therefore, a film that inhibits hydrogen diffusion is preferably provided between the transistor200and the transistor300. The film that inhibits hydrogen diffusion is specifically a film from which a small amount of hydrogen is released.

The amount of released hydrogen can be analyzed by thermal desorption spectroscopy (TDS), for example. The amount of hydrogen released from the insulator324that is converted into hydrogen atoms per unit area of the insulator324is less than or equal to 10×1015atoms/cm2, preferably less than or equal to 5×1015atoms/cm2in TDS analysis in a film-surface temperature range of 50° C. to 500° C., for example.

Note that the permittivity of the insulator326is preferably lower than that of the insulator324. For example, the relative permittivity of the insulator326is preferably lower than 4, further preferably lower than 3. The relative permittivity of the insulator326is, for example, preferably 0.7 times or less, further preferably 0.6 times or less the relative permittivity of the insulator324. When a material with a low permittivity is used for an interlayer film, the parasitic capacitance generated between wirings can be reduced.

Moreover, a conductor328, a conductor330, and the like are embedded in the insulator320, the insulator322, the insulator324, and the insulator326. Note that the conductor328and the conductor330each function as a plug or a wiring.

As a material for each of the conductor328and the conductor330, a single layer or stacked layers of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

FIG.12Ais a cross-sectional view in the channel length direction illustrating a structure example of the gate electrode of the transistor200, which is an OS transistor, and its periphery.FIG.12Bis a cross-sectional view in the channel length direction illustrating a structure example of the gate electrode of the transistor300, which is a Si transistor, and its periphery.

InFIG.12A, the channel length of the transistor200is denoted by a distance LOS. The distance LOScan be, for example, the distance between a lower end portion of the conductor242aand a lower end portion of the conductor242b. InFIG.12B, the channel length of the transistor300is denoted by a distance LSi. The distance LSican be, for example, the distance between an upper end portion of the low-resistance region314aand an upper end portion of the low-resistance region314b.

For example, in a silicon transistor, a semiconductor process node (e.g., a 5 nm node) and the channel length of an actual product do not correspond to each other in many cases. For example, when a transistor is formed in a 5-nm semiconductor process node, the channel length is greater than or equal to 14 nm and less than or equal to 16 nm, a line (L) is greater than or equal to 5 nm and less than or equal to 7 nm, and a space (S) is greater than or equal to 30 nm and less than or equal to 35 nm in some cases. Note that the line (L) represents the minimum line width of the transistor, and the space (S) represents the minimum pitch width of the transistor. Accordingly, the numerical value of the semiconductor process node is a mere indicator which indicates the degree of miniaturization. Thus, in the semiconductor device of one embodiment of the present invention, comparison between the distance LOSthat is the channel length of the transistor200and the distance LSithat is the channel length of the transistor300as illustrated inFIG.12AandFIG.12Bis an important component.

Note that a channel width (W) of the transistor depends on the on-state current (Ion) of the required transistor in circuit design. Thus, an optimal range of the channel width (W) of the transistor may be selected as appropriate by a practitioner.

In the case where the transistor200illustrated inFIG.12Aand the transistor300illustrated inFIG.12Bform a CMOS circuit, the distance LSiis longer than the distance LOS, whereby the difference between the mobility of the transistor200and mobility of the transistor300can be small as described above. Thus, even when the transistor200that is an OS transistor and the transistor300that is a Si transistor form the CMOS circuit, the CMOS circuit can be driven normally.

When the transistor200illustrated inFIG.12Aand the transistor300illustrated inFIG.12Bform the memory circuit21, the distance LSiis longer than the distance LOS, whereby a potential supplied to a gate of the transistor200and a potential supplied to a gate of the transistor300can be supplied from the same power source as described above.

As described above, it is preferable that the distance LOSbe less than 15 nm and the distance LSibe greater than or equal to 15 nm. Alternatively, it is preferable that the distance LOSbe greater than or equal to 3 nm and less than 15 nm, and the distance LSibe greater than or equal to 15 nm and less than or equal to 40 nm. The distance LOScan be typically greater than or equal to 5 nm and less than or equal to 8 nm.

A gate length of the transistor200that is an OS transistor is described below.

FIG.13Ais an enlarged view of the vicinity of the channel formation region inFIG.7B.FIG.13Ais a cross-sectional view of the transistor200in the channel length direction. As described above, the insulator252, the insulator250, and the insulator254function as the first gate insulator.

Hereinafter, the insulator252, the insulator250, and the insulator254are collectively referred to as an insulator256in some cases. In this case, the insulator256includes the insulator252, the insulator250over the insulator252, and the insulator254over the insulator250. The insulator256serves as the first gate insulator.

FIG.13Bis a cross-sectional view in which the insulator252, the insulator250, and the insulator254included inFIG.13Aare replaced with the insulator256. InFIG.13B, the conductor260is illustrated as a single layer for simplification of the drawing. Note that as described above, the conductor260may have a stacked-layer structure of the conductor260aand the conductor260bor a stacked-layer structure of three or more layers.

A width Lg illustrated inFIG.13AandFIG.13Bis the width of the bottom surface of the conductor260in a region overlapping with the metal oxide230bin a cross-sectional view in the channel length direction. Hereinafter, the bottom surface of the conductor260in the region overlapping with the metal oxide230bin a cross-sectional view in the channel length direction is simply referred to as the bottom surface of the conductor260in the region overlapping with the metal oxide230bin some cases. That is, the bottom surface of the conductor260in the region overlapping with the metal oxide230bdescribed later can be rephrased as the bottom surface of the conductor260in the region overlapping with the metal oxide230bin a cross-sectional view in the channel length direction in some cases.

The gate length refers to the length of a gate electrode in a direction in which carriers move inside a channel formation region during operation of the transistor and to the width of the bottom surface of the gate electrode in a top view of the transistor. In this specification and the like, the gate length is the width of the bottom surface of the conductor260in the region overlapping with the metal oxide230bin a cross-sectional view in the channel length direction. That is, the gate length is the width Lg illustrated inFIG.13AandFIG.13B. Note that the conductor260is provided in the opening included in the insulator275and the insulator280. The sidewall of the opening is perpendicular to a substrate surface or inclined to the substrate surface. In particular, in the case where the angle formed between the sidewall of the opening and the substrate surface is less than or equal to 90°, the minimum width of the conductor260in the region overlapping with the metal oxide230bis the width Lg. Thus, the conductor260can be regarded as having a region with the width Lg in a cross-sectional view in the channel length direction.

The bottom surface of the conductor260in the region overlapping with the metal oxide230bpreferably includes a flat region. As illustrated inFIG.13AandFIG.13B, in the case where the bottom surface of the conductor260in the region overlapping with the metal oxide230bincludes a flat region, the width Lg is the width of the flat region. When the bottom surface of the conductor260in the region overlapping with the metal oxide230bincludes the flat region, an electric field can be uniformly generated in the channel formation region of the metal oxide230.

AlthoughFIG.13AandFIG.13Beach illustrate a structure in which the bottom surface of the conductor260in the region overlapping with the metal oxide230bincludes the flat region, the present invention is not limited thereto. In a cross-sectional view in the channel length direction, the bottom surface of the conductor260in the region overlapping with the metal oxide230bmay have a curve.

FIG.13Cillustrates a modification example of the transistor200inFIG.13B.FIG.13Cis a cross-sectional view of the transistor200in the channel length direction. For example, as illustrated inFIG.13C, the bottom surface of the conductor260in the region overlapping with the metal oxide230bmay include a flat region and a region having a curve. Note that the region having a curve is positioned at an end portion of each side of the bottom surface. Here, a point where the curve of the bottom surface on the conductor242aside is in contact with the side surface of the conductor260on the conductor242aside is referred to as a point Qa. A point where the curve of the bottom surface on the conductor242bside is in contact with the side surface of the conductor260on the conductor242bside is referred to as a point Qb. In this structure, the width Lg is the length of a line segment connecting the point Qa and the point Qb.

FIG.13Dillustrates a modification example of the transistor200inFIG.13B.FIG.13Dis a cross-sectional view of the transistor200in the channel length direction. For example, as illustrated inFIG.13D, the bottom surface of the conductor260may have an arc shape. Note that the arc has a radius r and a curvature center P is positioned in the conductor260. In this structure, the width Lg is the width of a region where a straight line that includes the curvature center P and is parallel to the bottom surface of the metal oxide230boverlaps with the conductor260. In other words, the width Lg is twice as long as the radius r. Note that the straight line indicated by a dashed line inFIG.13Dis the straight line that includes the curvature center P and is parallel to the bottom surface of the metal oxide230b.

Note that in the case where the radius r is large (e.g., the case where the radius r is larger than the channel length) in the shape of the bottom surface of the conductor260illustrated inFIG.13D, the distance becomes large from the curvature center P to the channel formation region of the metal oxide230b. At this time, the width Lg illustrated inFIG.13Cmay be applied as the gate length of the shape. That is, the width Lg may be calculated by determining the point Qa and the point Qb in the shape of the bottom surface of the conductor260illustrated inFIG.13D.

It is sometimes difficult to determine the point Qa and the point Qb in the shape of the bottom surface of the conductor260illustrated inFIG.13C. At this time, the width Lg illustrated inFIG.13Dmay be applied as the gate length of the shape. That is, the width Lg may be calculated by determining the curvature center P in the shape of the bottom surface of the conductor260illustrated inFIG.13C.

The above is the description of the gate length. Next, the channel length is described.

As described above, the channel length of the transistor200is denoted by the distance LOS. The distance LOScan be, for example, the distance between the lower end portion of the conductor242aand the lower end portion of the conductor242b.

In the above structure, the channel length is set in accordance with a material used for the conductor260, the gate length, a material used for the first gate insulator, the thickness of the first gate insulator, and the like. In the case where the gate length is within the above range, the channel length can be less than or equal to 60 nm, less than or equal to 50 nm, less than or equal to 40 nm, or less than or equal to 30 nm and greater than or equal to 10 nm, greater than or equal to 15 nm, or greater than or equal to 20 nm, for example.

Although details will be described later, in forming an opening in the insulator280and the insulator275, an upper portion of the metal oxide230bin a region overlapping with the opening is removed in some cases. In that case, as illustrated inFIG.13E, the thickness of a region of the metal oxide230bthat overlaps with the conductor260is smaller than the thickness of a region of the metal oxide230bthat overlaps with the conductor242a. Note that the transistor200illustrated inFIG.13Eis a modification example of the transistor200illustrated inFIG.13B.FIG.13Eis a cross-sectional view of the transistor200in the channel length direction.

Here, the difference between the thickness of the region of the metal oxide230bthat overlaps with the conductor260and the thickness of the region of the metal oxide230bthat overlaps with the conductor242ais referred to as a difference Lt (seeFIG.13E). When the difference Lt is small, the distance between the lower end portion of the conductor242aand the lower end portion of the conductor242bmay be regarded as the channel length, for example.

In the case where the insulator252is formed to have a small thickness as described above, the layer244ais sometimes formed between the conductor242aand the insulator256as illustrated inFIG.13F. In a similar manner, the layer244bis sometimes formed between the conductor242band the insulator256. In other words, the transistor200may include the layer244apositioned between the conductor242aand the insulator256and the layer244bpositioned between the conductor242band the insulator256. Note that the transistor200illustrated inFIG.13Fis a modification example of the transistor200illustrated inFIG.13E.FIG.13Fis a cross-sectional view of the transistor200in the channel length direction.

Each of the layer244aand the layer244bis formed by oxidation of the side surfaces of the conductor242aand the conductor242b. Thus, the layer244acontains an element contained in the conductor242aand oxygen. Furthermore, the layer244bcontains an element contained in the conductor242band oxygen. For example, in the case where the conductor242aand the conductor242beach contain a metal and nitrogen, the layer244aand the layer244beach contain the metal and oxygen.

The layer244ahas lower conductivity than the conductor242a. Furthermore, the layer244bhas lower conductivity than the conductor242b. Accordingly, even in the case where the transistor200includes the layer244aand the layer244b, the distance L between the lower end portion of the conductor242aand the lower end portion of the conductor242bmay be regarded as the channel length. That is, when the layer244aand the layer244bare formed, the channel length can be increased. Accordingly, the source-drain withstand voltage of the transistor200can be improved, so that the transistor can be highly reliable.

Note that in the cross-sectional view in the channel length direction, the length in the channel length direction of the layer244ais a length Lo (seeFIG.13F). Note that the length in the channel length direction of the layer244bis equal to or substantially equal to the length Lo. The length Lo is preferably small. For example, the length Lo is preferably smaller than the width Lg. Specifically, the length Lo is preferably greater than or equal to 1 nm and less than 8 nm, further preferably greater than or equal to 2 nm and less than 5 nm. With this structure, even when the gate length is within the above range, the transistor200can have favorable electrical characteristics.

FIG.14is a cross-sectional view illustrating a structure example of a semiconductor device including the transistor200and the transistor300.FIG.14illustrates an example in which the n-channel transistor200and the p-channel transistor300form an inverter. That is, in the example illustrated inFIG.14, the transistor200corresponds to the transistor41nillustrated inFIG.3and the transistor300corresponds to the transistor41pillustrated inFIG.3.FIG.14illustrates an example in which the transistor200has the structure illustrated inFIG.7Band the transistor300has the structure illustrated inFIG.11A.

A wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the components. A plurality of wiring layers can be provided in accordance with design. Here, a plurality of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, part of a conductor functions as a wiring in some cases and part of a conductor functions as a plug in other cases.

For example, the insulator320, the insulator322, the insulator324, and the insulator326are sequentially stacked over the transistor300as interlayer films. Moreover, the conductor328, the conductor330, and the like are embedded in the insulator320, the insulator322, the insulator324, and the insulator326. Note that the conductor328and the conductor330function as plugs or wirings.

The insulators functioning as interlayer films may also function as planarization films that cover uneven shapes therebelow. For example, the top surface of the insulator322may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method to improve planarity.

A wiring layer may be provided over the insulator326and the conductor330. For example, inFIG.14, an insulator350, an insulator352, and an insulator354are stacked in this order. Furthermore, the conductor356is formed in the insulator350, the insulator352, and the insulator354. The conductor356functions as a plug or a wiring.

Similarly, a conductor218, the conductor (the conductor205) included in the transistor200, and the like are embedded in an insulator210, the insulator212, the insulator214, and the insulator216. Note that the conductor218has a function of a plug or a wiring. An insulator150is provided over a conductor112.

Here, like the insulator241described in the above embodiment, an insulator217is provided in contact with the side surface of the conductor218functioning as a plug. The insulator217is provided in contact with an inner wall of an opening formed in the insulator210, the insulator212, the insulator214, and the insulator216. That is, the insulator217is provided between the conductor218and each of the insulator210, the insulator212, the insulator214, and the insulator216. Note that the conductor205and the conductor218can be formed in parallel; thus, the insulator217is sometimes formed in contact with the side surface of the conductor205.

As the insulator217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator217is provided in contact with the insulator210, the insulator212, the insulator214, and the insulator222, entry of an impurity such as water and hydrogen into the metal oxide230through the conductor218from the insulator210, the insulator216, or the like can be inhibited. In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Moreover, oxygen contained in the insulator210or the insulator216can be prevented from being absorbed by the conductor218.

The insulator217can be formed in a manner similar to that of the insulator241. For example, silicon nitride can be deposited by a PEALD method and an opening reaching the conductor356can be formed by anisotropic etching.

Examples of an insulator that can be used as an interlayer film include an insulating oxide, an insulating nitride, an insulating oxynitride, an insulating nitride oxide, an insulating metal oxide, an insulating metal oxynitride, and an insulating metal nitride oxide.

For example, when a material with a low relative permittivity is used for the insulator functioning as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Thus, a material is preferably selected depending on the function of an insulator.

For example, for the insulator150, the insulator210, the insulator352, the insulator354, and the like, an insulator having a low relative permittivity is preferably used. For example, the insulator preferably includes silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or a resin. Alternatively, the insulator preferably has a stacked-layer structure of a resin and silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide. When silicon oxide and silicon oxynitride, which are thermally stable, are combined with a resin, the stacked-layer structure can have thermal stability and a low relative permittivity. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, or the like), polyimide, polycarbonate, and acrylic.

When a transistor using an oxide semiconductor is surrounded by an insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stable. Thus, the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen can be used as the insulator214, the insulator212, the insulator350, and the like.

An insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen can be formed to have a single layer or a stacked layer including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, as the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; silicon nitride oxide; silicon nitride; or the like can be used.

As the conductor that can be used for a wiring or a plug, a material containing one or more kinds of metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. A semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus may be used. Silicide such as nickel silicide may be used.

For example, for the conductor328, the conductor330, the conductor356, the conductor218, the conductor112, and the like, a single-layer structure or a stacked-layer structure using a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material that is formed using the above materials can be used. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[Wiring or Plug in Layer Including Oxide Semiconductor]

In the case where an oxide semiconductor is used in the transistor200, an insulator including an excess-oxygen region is provided in the vicinity of the oxide semiconductor in some cases. In that case, an insulator having a barrier property is preferably provided between the insulator including the excess-oxygen region and a conductor provided in the insulator including the excess-oxygen region.

For example, the insulator241is preferably provided between the insulator280containing excess oxygen and the conductor240inFIG.14. Since the insulator241is provided in contact with the insulator222, the insulator282, and the insulator283, the insulator224and the transistor200can be sealed with the insulators having a barrier property.

That is, the insulator241can inhibit excess oxygen included in the insulator224and the insulator280from being absorbed by the conductor240. In addition, providing the insulator241can inhibit diffusion of hydrogen, which is an impurity, into the transistor200through the conductor240.

Note that an insulating material having a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen is preferably used for the insulator241. For example, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like is preferably used. In particular, silicon nitride is preferable because of its high blocking property against hydrogen. Alternatively, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can be used, for example.

As described in the above embodiment, the transistor200may be sealed with the insulator212, the insulator214, the insulator282, and the insulator283. Such a structure can inhibit entry of hydrogen contained in the insulator274, the insulator150, or the like into the insulator280, for example.

Here, the conductor240penetrates the insulator283and the insulator282, and the conductor218penetrates the insulator214and the insulator212; however, as described above, the insulator241is provided in contact with the conductor240, and the insulator217is provided in contact with the conductor218. This can reduce the amount of hydrogen entering the inside of the insulator212, the insulator214, the insulator282, and the insulator283through the conductor240and the conductor218. In this manner, the transistor200is sealed with the insulator212, the insulator214, the insulator282, the insulator283, the insulator241, and the insulator217, so that impurities such as hydrogen contained in the insulator274or the like can be inhibited from entering from the outside.

A dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) which is provided when a large-sized substrate is divided into semiconductor elements so that a plurality of semiconductor devices are each taken as a chip is described below. Examples of a dividing method include the case where a groove (a dicing line) for dividing the semiconductor elements is formed on the substrate, and then the substrate is cut along the dicing line to divide (split) it into a plurality of semiconductor devices.

Here, for example, as illustrated inFIG.14, a region in which the insulator283and the insulator214are in contact with each other is preferably designed to overlap with the dicing line. That is, an opening is provided in the insulator282, the insulator280, the insulator275, the insulator224, the insulator222, and the insulator216in the vicinity of a region to be the dicing line that is provided on an outer edge of the memory circuit including the plurality of transistors200.

That is, in the opening provided in the insulator282, the insulator280, the insulator275, the insulator224, the insulator222, and the insulator216, the insulator214is in contact with the insulator283.

For example, an opening may be provided in the insulator282, the insulator280, the insulator275, the insulator224, the insulator222, the insulator216, and the insulator214. With such a structure, in the opening provided in the insulator282, the insulator280, the insulator275, the insulator224, the insulator222, the insulator216, and the insulator214, the insulator212is in contact with the insulator283. In that case, the insulator212and the insulator283may be formed using the same material, and the insulator212and the insulator283may be formed by the same method. When the insulator212and the insulator283are formed using the same material and the same method, the adhesion therebetween can be increased. For example, silicon nitride is preferably used.

With the structure, the transistors200can be surrounded by the insulator212, the insulator214, the insulator282, and the insulator283. Since at least one of the insulator212, the insulator214, the insulator282, and the insulator283has a function of inhibiting diffusion of oxygen, hydrogen, and water, even when the substrate is divided into circuit regions each of which is provided with the semiconductor elements described in this embodiment to be processed into a plurality of chips, entry and diffusion of impurities such as hydrogen and water from the direction of the side surface of the divided substrate into the transistor200can be prevented.

With the structure, excess oxygen in the insulator280and the insulator224can be prevented from diffusing to the outside. Accordingly, excess oxygen in the insulator280and the insulator224is efficiently supplied to the oxide where the channel is formed in the transistor200. The oxygen can reduce oxygen vacancies in the oxide where the channel is formed in the transistor200. Thus, the oxide where the channel is formed in the transistor200can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, the transistor200can have a small variation in the electrical characteristics and higher reliability.

FIG.15is a cross-sectional view illustrating a structure example of a semiconductor device, which is a modification example of the structure illustrated inFIG.14. The semiconductor device illustrated inFIG.15has a structure of the transistor200illustrated inFIG.10A.

FIG.16is a cross-sectional view in the channel width direction of the transistor200and the transistor300of the semiconductor device illustrated inFIG.15. As illustrated inFIG.16, it is preferable that both the transistor200and the transistor300be Fin-type transistors, in which case both the transistor200and the transistor300can be transistors with high on-state characteristics and high off-state characteristics.

The transistor300is not necessarily a Fin-type transistor.FIG.17illustrates an example in which the transistor300is a planar type, which is a modification example of the semiconductor device illustrated inFIG.15. When the transistor300is a planar type, the manufacturing process of the transistor300can be simplified.

FIG.18is a cross-sectional view illustrating a structure example of a semiconductor device including the transistor200and the transistor300. InFIG.18, the transistor200corresponds to, for example, the transistor MW3illustrated inFIG.6, and the transistor300corresponds to, for example, the transistor MR3illustrated inFIG.6.FIG.18illustrates an example in which a capacitor100is provided above the transistor200. The capacitor100corresponds to, for example, the capacitor CS3illustrated inFIG.6.FIG.18illustrates an example in which the transistor200has the structure illustrated inFIG.7Band the transistor300has the structure illustrated inFIG.11A.

The capacitor100is provided above the transistor200. The capacitor100includes a conductor110functioning as one of a pair of electrodes, a conductor120functioning as the other of the pair of electrodes, and an insulator130functioning as a dielectric. Here, for the insulator130, the insulator that can be used as the insulator283described above is preferably used.

For example, the conductor112and the conductor110provided over the conductor240can be formed in parallel. Note that the conductor112functions as a plug or a wiring that is electrically connected to the capacitor100, the transistor200, or the transistor300.

Although an example in which the conductor112and the conductor110having a single-layer structure is illustrated inFIG.18, the structure is not limited thereto; a stacked-layer structure of two or more layers may be employed. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor that is highly adhesive to the conductor having a barrier property and the conductor having high conductivity may be formed.

For the insulator130, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like may be used. A stack or a single layer including any of these materials can be provided in the insulator130.

For example, for the insulator130, a stacked-layer structure of a material with high dielectric strength such as silicon oxynitride and a high permittivity (high-k) material is preferably used. With this structure, electrostatic breakdown can be inhibited while sufficient capacitance of the capacitor100is maintained.

Examples of the high permittivity material (a material having a high relative permittivity) include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium. Alternatively, for the insulator130, the above-described high permittivity material may be stacked. Examples of the stack include a three-layer structure of zirconium oxide, aluminum oxide over the zirconium oxide, and zirconium oxide over the aluminum oxide.

Examples of a material with high dielectric strength (a material having a low relative permittivity) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin.

FIG.19is a cross-sectional view illustrating a structure example of a semiconductor device, which is a modification example of the structure illustrated inFIG.18. The semiconductor device illustrated inFIG.19has a structure of the transistor200illustrated inFIG.10A. Here, the cross sections of the transistor200and the transistor300in the channel width direction can have the structure illustrated inFIG.16. Each of the transistor200and the transistor300illustrated inFIG.19is a Fin-type transistor. As described above, it is preferable that both the transistor200and the transistor300be Fin-type transistors, in which case both the transistor200and the transistor300can be transistors with high on-state characteristics and high off-state characteristics.

As described above, the transistor300is not necessarily a Fin-type transistor.FIG.20illustrates an example in which the transistor300is a planar type, which is a modification example of the semiconductor device illustrated inFIG.19. As described above, when the transistor300is a planar type, the manufacturing process of the transistor300can be simplified.

At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with other embodiments, an example, and the like described in this specification.

In this embodiment, an example of a chip1200on which the semiconductor device of the present invention is mounted will be described with reference toFIG.21AandFIG.21B. A plurality of circuits (systems) are mounted on the chip1200. A technique for integrating a plurality of circuits (systems) into one chip is referred to as system on chip (SoC) in some cases.

As illustrated inFIG.21A, the chip1200includes a CPU1211, a GPU1212, one or more analog arithmetic units1213, one or more memory controllers1214, one or more interfaces1215, one or more network circuits1216, and the like.

A bump (not illustrated) is provided on the chip1200, and as illustrated inFIG.21B, the chip1200is connected to a first surface of a package board1201. In addition, a plurality of bumps1202are provided on a rear side of the first surface of the package board1201, and the package board1201is connected to a motherboard1203.

Memory devices such as DRAMs1221and a flash memory1222may be provided over the motherboard1203. For example, the DOSRAM described in the above embodiment can be used as the DRAM1221. In addition, for example, the NOSRAM described in the above embodiment can be used as the flash memory1222.

The CPU1211preferably includes a plurality of CPU cores. In addition, the GPU1212preferably includes a plurality of GPU cores. Furthermore, the CPU1211and the GPU1212may each include a memory for temporarily storing data. Alternatively, a common memory for the CPU1211and the GPU1212may be provided in the chip1200. The NOSRAM or the DOSRAM described above can be used as the memory. Moreover, the GPU1212is suitable for parallel computation of a number of data and thus can be used for image processing or product-sum operation. When an image processing circuit or a product-sum operation circuit using an oxide semiconductor of the present invention are provided in the GPU1212, image processing and product-sum operation can be performed with low power consumption.

In addition, since the CPU1211and the GPU1212are provided on the same chip, a wiring between the CPU1211and the GPU1212can be shortened, and the data transfer from the CPU1211to the GPU1212, the data transfer between memories included in the CPU1211and the GPU1212, and the transfer of arithmetic operation results from the GPU1212to the CPU1211after the arithmetic operation in the GPU1212can be performed at a high speed.

The analog arithmetic unit1213includes one or both of an A/D (analog/digital) converter circuit and a D/A (digital/analog) converter circuit. Furthermore, the product-sum operation circuit may be provided in the analog arithmetic unit1213.

The memory controller1214includes a circuit functioning as a controller of the DRAM1221and a circuit functioning as an interface of the flash memory1222.

The interface1215includes an interface circuit for an external connection device such as a display device, a speaker, a microphone, a camera, or a controller. Examples of the controller include a mouse, a keyboard, and a game controller. As such an interface, a USB (Universal Serial Bus) and an HDMI (registered trademark) (High-Definition Multimedia Interface) can be used, for example.

The network circuit1216includes a network circuit such as a LAN (Local Area Network). The network circuit1216may further include a circuit for network security.

The circuits (systems) can be formed in the chip1200through the same manufacturing process. Therefore, even when the number of circuits needed for the chip1200increases, there is no need to increase the number of steps in the manufacturing process; thus, the chip1200can be manufactured at low cost.

The motherboard1203provided with the package board1201on which the chip1200including the GPU1212is mounted, the DRAMs1221, and the flash memory1222can be referred to as a GPU module1204.

The GPU module1204includes the chip1200using SoC technology, and thus can have a small size. In addition, the GPU module1204is excellent in image processing, and thus is suitably used in a portable electronic device such as a smartphone, a tablet terminal, a laptop PC, or a portable (mobile) game machine. Furthermore, the product-sum operation circuit using the GPU1212can perform a method such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), or a deep belief network (DBN); hence, the chip1200can be used as an AI chip or the GPU module1204can be used as an AI system module.

At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with other embodiments, an example, and the like described in this specification.

Shown in this embodiment are examples of electronic components and electronic devices in which the memory device, for example, described in the above embodiment is incorporated.

First, examples of an electronic component including a memory device720are described with reference toFIG.22AandFIG.22B.

FIG.22Ais a perspective view of an electronic component700and a substrate (circuit board704) on which the electronic component700is mounted. The electronic component700inFIG.22Aincludes the memory device720in a mold711.FIG.22Aomits part of the electronic component to show the inside of the electronic component700. The electronic component700includes a land712outside the mold711. The land712is electrically connected to an electrode pad713, and the electrode pad713is electrically connected to the memory device720via a wire714. The electronic component700is mounted on a printed circuit board702, for example. A plurality of such electronic components are combined and electrically connected to each other on the printed circuit board702, which forms the circuit board704.

The memory device720includes a driver circuit layer721and a memory circuit layer722.

FIG.22Bis a perspective view of an electronic component730. The electronic component730is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component730, an interposer731is provided over a package board732(printed circuit board) and a semiconductor device735and a plurality of memory devices720are provided over the interposer731.

The electronic component730using the memory device720as a high bandwidth memory (HBM) is illustrated as an example. An integrated circuit (a semiconductor device) such as a CPU, a GPU, or an FPGA can be used as the semiconductor device735.

As the package board732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer731, a silicon interposer, a resin interposer, or the like can be used.

The interposer731includes a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer731has a function of electrically connecting an integrated circuit provided on the interposer731to an electrode provided on the package board732. Accordingly, the interposer is referred to as a “redistribution substrate” or an “intermediate substrate” in some cases. A through electrode may be provided in the interposer731to be used for electrically connecting the integrated circuit and the package board732. In a silicon interposer, a TSV (Through Silicon Via) can also be used as the through electrode.

A silicon interposer is preferably used as the interposer731. A silicon interposer can be manufactured at lower cost than an integrated circuit because it is not necessary to provide an active element. Meanwhile, since wirings of a silicon interposer can be formed through a semiconductor process, formation of minute wirings, which is difficult for a resin interposer, is easy.

In order to achieve a wide memory bandwidth, many wirings need to be connected to an HBM. Therefore, formation of minute and high-density wirings is required for an interposer on which an HBM is mounted. For this reason, a silicon interposer is preferably used as the interposer on which an HBM is mounted.

In a SiP, an MCM, and the like using a silicon interposer, a decrease in reliability due to a difference in expansion coefficient between an integrated circuit and the interposer is less likely to occur. Furthermore, the surface of a silicon interposer has high planarity, so that a poor connection between the silicon interposer and an integrated circuit provided on the silicon interposer is less likely to occur. It is particularly preferable to use a silicon interposer for a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer.

A heat sink (radiator plate) may be provided to overlap with the electronic component730. In the case of providing a heat sink, the heights of integrated circuits provided on the interposer731are preferably the same. In the electronic component730of this embodiment, the heights of the memory device720and the semiconductor device735are preferably the same, for example.

An electrode733may be provided on the bottom portion of the package board732to mount the electronic component730on another substrate.FIG.22Billustrates an example in which the electrode733is formed of a solder ball. Solder balls are provided in a matrix on the bottom portion of the package board732, whereby a BGA (Ball Grid Array) can be achieved. Alternatively, the electrode733may be formed of a conductive pin. When conductive pins are provided in a matrix on the bottom portion of the package board732, a PGA (Pin Grid Array) can be achieved.

The electronic component730can be mounted on another substrate by various mounting methods not limited to BGA and PGA. For example, a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be employed.

At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with other embodiments, an example, and the like described in this specification.

In this embodiment, application examples of the memory device using the semiconductor device described in the above embodiment are described. The semiconductor device described in the above embodiment can be applied to, for example, memory devices of a variety of electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), video recording/reproducing devices, and navigation systems). Here, the computers refer not only to tablet computers, notebook computers, and desktop computers, but also to large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment is applied to a variety of removable memory devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives).FIG.23AtoFIG.23Eschematically illustrate some structure examples of removable memory devices. The semiconductor device described in the above embodiment is processed into a packaged memory chip and used in a variety of storage devices and removable memories, for example.

FIG.23Ais a schematic view of a USB memory. A USB memory1100includes a housing1101, a cap1102, a USB connector1103, and a substrate1104. The substrate1104is held in the housing1101. The substrate1104is provided with a memory chip1105and a controller chip1106, for example. The semiconductor device described in the above embodiment can be incorporated in the memory chip1105, for example.

FIG.23Bis a schematic external view of an SD card, andFIG.23Cis a schematic view of the internal structure of the SD card. An SD card1110includes a housing1111, a connector1112, and a substrate1113. The substrate1113is held in the housing1111. The substrate1113is provided with a memory chip1114and a controller chip1115, for example. When the memory chip1114is also provided on the back side of the substrate1113, the capacity of the SD card1110can be increased. In addition, a wireless chip with a radio communication function may be provided on the substrate1113. With this, data can be read from and written in the memory chip1114by radio communication between a host device and the SD card1110. The semiconductor device described in the above embodiment can be incorporated in the memory chip1114, for example.

FIG.23Dis a schematic external view of an SSD, andFIG.23Eis a schematic view of the internal structure of the SSD. An SSD1150includes a housing1151, a connector1152, and a substrate1153. The substrate1153is held in the housing1151. The substrate1153is provided with a memory chip1154, a memory chip1155, and a controller chip1156, for example. The memory chip1155is a work memory of the controller chip1156, and a DOSRAM chip can be used, for example. When the memory chip1154is also provided on the back side of the substrate1153, the capacity of the SSD1150can be increased. The semiconductor device described in the above embodiment can be incorporated in the memory chip1154, for example. At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with other embodiments, an example, and the like described in this specification.

The semiconductor device of one embodiment of the present invention can be used as a chip or a processor such as a CPU or a GPU.FIG.24AtoFIG.24Hillustrate specific examples of electronic devices including a chip or a processor such as a CPU or a GPU of one embodiment of the present invention.

<Electronic Device and System>

The GPU or the chip of one embodiment of the present invention can be mounted on a variety of electronic devices. Examples of electronic devices include a digital camera, a digital video camera, a digital photo frame, an e-book reader, a mobile phone, a portable game machine, a portable information terminal, and an audio reproducing device in addition to electronic devices provided with a relatively large screen, such as a television device, a monitor for a desktop or notebook information terminal or the like, digital signage, and a large game machine like a pachinko machine. When the GPU or the chip of one embodiment of the present invention is provided in the electronic device, the electronic device can include artificial intelligence.

The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, the electronic device can display a video, information, or the like on a display portion. When the electronic device includes the antenna and a secondary battery, the antenna may be used for contactless power transmission.

FIG.24Aillustrates a mobile phone (smartphone), which is a type of information terminal. An information terminal5100includes a housing5101and a display portion5102. As input interfaces, a touch panel is provided in the display portion5102and a button is provided in the housing5101.

When the chip of one embodiment of the present invention is applied to the information terminal5100, the information terminal5100can execute an application utilizing artificial intelligence. Examples of the application utilizing artificial intelligence include an application for recognizing a conversation and displaying the content of the conversation on the display portion5102; an application for recognizing letters, figures, or the like input to the touch panel of the display portion5102by a user and displaying them on the display portion5102; and an application for performing biometric authentication using fingerprints, voice prints, or the like.

FIG.24Billustrates a notebook information terminal5200. The notebook information terminal5200includes a main body5201of the information terminal, a display portion5202, and a keyboard5203.

Like the information terminal5100described above, when the chip of one embodiment of the present invention is applied to the notebook information terminal5200, the notebook information terminal5200can execute an application utilizing artificial intelligence. Examples of the application utilizing artificial intelligence include design-support software, text correction software, and software for automatic menu generation. Furthermore, with use of the notebook information terminal5200, novel artificial intelligence can be developed.

Note that althoughFIG.24AandFIG.24Billustrate a smartphone and a notebook information terminal, respectively, as examples of the electronic device in the above description, an information terminal other than a smartphone and a notebook information terminal can be used. Examples of information terminals other than a smartphone and a notebook information terminal include a PDA (Personal Digital Assistant), a desktop information terminal, and a workstation.

FIG.24Cillustrates a portable game machine5300as an example of a game machine. The portable game machine5300includes a housing5301, a housing5302, a housing5303, a display portion5304, a connection portion5305, an operation key5306, and the like. The housing5302and the housing5303can be detached from the housing5301. When the connection portion5305provided in the housing5301is attached to another housing (not illustrated), an image to be output to the display portion5304can be output to another video device (not illustrated). In that case, the housing5302and the housing5303can each function as an operating unit. Thus, a plurality of players can play a game at the same time. The chip described in the above embodiment can be incorporated into the chip or the like provided on a substrate in the housing5301, the housing5302and the housing5303.

FIG.24Dillustrates a stationary game machine5400as an example of a game machine. A controller5402is wired or connected wirelessly to the stationary game machine5400.

Using the GPU or the chip of one embodiment of the present invention in a game machine such as the portable game machine5300and the stationary game machine5400achieves a low-power-consumption game machine. Moreover, heat generation from a circuit can be reduced owing to low power consumption; thus, the influence of heat generation on the circuit itself, a peripheral circuit, and a module can be reduced.

Furthermore, when the GPU or the chip of one embodiment of the present invention is applied to the portable game machine5300, the portable game machine5300including artificial intelligence can be achieved.

In general, the progress of a game, the actions and words of game characters, and expressions of an event and the like occurring in the game are determined by the program in the game; however, the use of artificial intelligence in the portable game machine5300enables expressions not limited by the game program. For example, it becomes possible to change expressions such as questions posed by the player, the progress of the game, time, and actions and words of game characters.

In addition, when a game requiring a plurality of players is played on the portable game machine5300, the artificial intelligence can create a virtual game player; thus, the game can be played alone with the game player created by the artificial intelligence as an opponent.

Although the portable game machine and the stationary game machine are shown as examples of game machines inFIG.24CandFIG.24D, the game machine using the GPU or the chip of one embodiment of the present invention is not limited thereto. Examples of the game machine to which the GPU or the chip of one embodiment of the present invention is applied include an arcade game machine installed in entertainment facilities (a game center, an amusement park, and the like), and a throwing machine for batting practice installed in sports facilities.

The GPU or the chip of one embodiment of the present invention can be used in a large computer.

FIG.24Eis a diagram illustrating a supercomputer5500as an example of a large computer.FIG.24Fis a diagram illustrating a rack-mount computer5502included in the supercomputer5500.

The supercomputer5500includes a rack5501and a plurality of rack-mount computers5502. The plurality of computers5502are stored in the rack5501. The computer5502includes a plurality of substrates5504on which the GPU or the chip shown in the above embodiment can be mounted.

The supercomputer5500is a large computer mainly used for scientific computation. In scientific computation, an enormous amount of arithmetic operation needs to be processed at a high speed; hence, power consumption is large and chips generate a large amount of heat. Using the GPU or the chip of one embodiment of the present invention in the supercomputer5500achieves a low-power-consumption supercomputer. Moreover, heat generation from a circuit can be reduced owing to low power consumption; thus, the influence of heat generation on the circuit itself, a peripheral circuit, and a module can be reduced.

Although a supercomputer is shown as an example of a large computer inFIG.24EandFIG.24F, a large computer using the GPU or the chip of one embodiment of the present invention is not limited thereto. Other examples of large computers in which the GPU or the chip of one embodiment of the present invention is usable include a computer that provides service (a server) and a large general-purpose computer (a mainframe).

The GPU or the chip of one embodiment of the present invention can be applied to an automobile, which is a moving vehicle, and the periphery of a driver's seat in the automobile.

FIG.24Gillustrates an area around a windshield inside an automobile, which is an example of a moving vehicle.FIG.24Gillustrates a display panel5701, a display panel5702, and a display panel5703that are attached to a dashboard and a display panel5704that is attached to a pillar.

The display panel5701to the display panel5703can provide a variety of kinds of information by displaying a speedometer, a tachometer, mileage, a fuel gauge, a gear state, air-condition setting, or the like. In addition, the content, layout, and the like of the display on the display panels can be changed as appropriate to suit the user's preference, so that the design quality can be increased. The display panel5701to the display panel5703can also be used as lighting devices.

The display panel5704can compensate for view obstructed by the pillar (a blind spot) by showing an image taken by an imaging device (not illustrated) provided for the automobile. That is, displaying an image taken by the imaging device provided outside the automobile leads to compensation for the blind spot and an increase in safety. Display of an image that complements for the area that cannot be seen makes it possible to confirm safety more naturally and comfortably. The display panel5704can also be used as a lighting device.

Since the GPU or the chip of one embodiment of the present invention can be applied to a component of artificial intelligence, the chip can be used for an automatic driving system of the automobile, for example. The chip can also be used for a system for navigation, risk prediction, or the like. A structure may be employed in which the display panel5701to the display panel5704display navigation information, risk prediction information, or the like.

Note that although an automobile is described above as an example of a moving vehicle, the moving vehicle is not limited to an automobile. Examples of the moving vehicle include a train, a monorail train, a ship, and a flying vehicle (a helicopter, an unmanned aircraft (a drone), an airplane, and a rocket), and these moving vehicles can each include a system utilizing artificial intelligence when the chip of one embodiment of the present invention is applied to each of these moving vehicles.

FIG.24Hillustrates an electric refrigerator-freezer5800as an example of a household appliance. The electric refrigerator-freezer5800includes a housing5801, a refrigerator door5802, a freezer door5803, and the like.

When the chip of one embodiment of the present invention is applied to the electric refrigerator-freezer5800, the electric refrigerator-freezer5800including artificial intelligence can be achieved. Utilizing the artificial intelligence enables the electric refrigerator-freezer5800to have a function of automatically making a menu based on expiration dates of foods stored in the electric refrigerator-freezer5800and a function of automatically adjusting temperature to be appropriate for the foods stored in the electric refrigerator-freezer5800, for example.

Although the electric refrigerator-freezer is described in this example as a household appliance, examples of other household appliances include a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, a heating-cooling combination appliance such as an air conditioner, a washing machine, a drying machine, and an audio visual appliance.

The electronic devices, the functions of the electronic devices, the application examples of artificial intelligence, their effects, and the like described in this embodiment can be combined as appropriate with the description of another electronic device.

At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with other embodiments, an example, and the like described in this specification.

The semiconductor device of one embodiment of the present invention can be suitably used for a processor using power gating that reduces unnecessary power consumption, for example. Furthermore, the semiconductor device of one embodiment of the present invention can be suitably used in a memory using an OSFET (also referred to as an OS memory). More specific structures will be described with reference toFIG.25AandFIG.25B.

Power gating is known for reducing unnecessary power consumption by temporarily stopping power supply to an arithmetic circuit that is not operating. A processor using power gating is referred to as a “normally-off processor” or an “Noff processor” in some cases. In a normally-off processor, data necessary in restoration needs to be saved to a nonvolatile memory before power supply is stopped and read in restoration.

As a nonvolatile memory, a flash memory, a ferroelectric memory (FeRAM), and the like are known. These have low access speed and a limited number of times of rewriting, and thus the memories thereof are unsuitable as a nonvolatile memory used for a normally-off processor. Examples of the nonvolatile memory used for the normally-off processor include a magnetoresistive memory (MRAM) including an MTJ element, a resistive random access memory (ReRAM), and a phase change memory (PCM).

An OS memory is suitably used as a nonvolatile memory used for the normally-off processor. An OS memory is a memory element using an OS transistor. As the OS memory, DOSRAM (registered trademark) and NOSRAM (registered trademark) are known.

An OS memory can retain written data for a period of one year or longer, or ten years or longer even after power supply is stopped. In an OS memory, written charge amount is less likely to change over a long period of time; hence, the OS memory can hold multilevel (multibit) data or analog value data as well as binary (1-bit) data.

In the OS memory, charge is written to a node through the OS transistor; hence, a high voltage, which is required for a conventional flash memory, is unnecessary and a high-speed writing operation is possible, for example. The OS memory does not need electric charge injection and electric charge extraction into/from a charge trap layer, which are performed in a flash memory and is not accompanied with a structure change at the atomic level as in an MRAM, a ReRAM, or the like. Thus, the OS memory enables substantially unlimited number of times of data writing and reading, and deteriorates less than the above memories, offering high reliability.

FIG.25AandFIG.25Bare diagrams showing changes in power consumption of normally-off processors. InFIG.25AandFIG.25B, the horizontal axis represents time and the vertical axis represents power consumption. InFIG.25AandFIG.25B, the operation period and the stop period (sleep period) of an arithmetic circuit are shown as a period Tact and a period Tslp, respectively.

InFIG.25AandFIG.25B, electric power consumed in reading saved data when power supply is restarted is referred to as restoration electric power910, electric power consumed by the arithmetic circuit in normal operation is referred to as active electric power920, electric power consumed by leakage current in the normal operation is referred to as leakage electric power930, and electric power consumed by saving data immediately before the period Tslp is referred to as saving electric power940. In normal operation, the active electric power920and the leakage electric power930are consumed. Note that the restoration electric power910may be referred to as rising electric power.

FIG.25Ashows changes in power consumption when an MTJ element is used for the nonvolatile memory used for the normally-off processor.FIG.25Bshows changes in power consumption when an OS memory is used for the nonvolatile memory used for the normally-off processor.

Since the MTJ element cannot retain multi-level data and analog data, more time is needed for restoration (i.e., the rise time is long) and more restoration electric power910is necessary than the normally-off processor using the OS memory, which is capable of retaining multi-level data and analog data. By contrast, in the normally-off processor using the OS memory, data can be restored in a short time (i.e., the rise time is short) and a high voltage is not necessary for data reading and writing. With use of the OS memory, a normally-off processor with lower power consumption can be achieved.

Example

A field-effect OS transistor (hereinafter, referred to as a CAAC-OS FET) that can be provided in the semiconductor device of one embodiment of the present invention has low temperature dependence and can operate stably even in a high-temperature environment. In this example, an experiment on high-temperature characteristics of the CAAC-OS FET and the results thereof will be described.

The CAAC-OS FET can be manufactured by a BEOL (Back End Of Line) process in a semiconductor manufacturing process for CMOS or the like. Thus, stacking with a Si transistor (in this example, among Si transistors, a field-effect Si transistor is also referred to as a “Si FET”) is possible. For example, a circuit that requires high-speed operation can be formed by a Si FET process, and a circuit that requires low leakage current can be formed by a CAAC-OS FET process.

The off-state current of the Si FET increases as the temperature increases, whereas the off-state current of the CAAC-OS FET is always below the measurement limit. Accordingly, the temperature characteristics of the off-state current of a Si FET with L (channel length)/W (channel width)=60 nm/120 nm and the off-state current of a CAAC-OS FET with L/W=21 nm/25 nm were compared. The off-state current of both FETs was measured using the circuit illustrated inFIG.26.

A circuit illustrated inFIG.26includes an FET serving as a DUT (Device Under Test), a writing transistor WFET, and a read circuit SF. The writing transistor WFET is a CAAC-OS FET. The read circuit SF includes CAAC-OS FETs connected in series. A terminal S of the FET serving as the DUT functions as a terminal to which a source voltage is input. Note that a CAAC-OS FET including a top gate TG and a back gate BG is illustrated as the DUT inFIG.26. In practice, 20000 CAAC-OS FETs were connected in parallel as the DUT. Note that in the case where the DUT is a Si FET, the structure is not limited thereto.

In the case where a Si FET was the DUT inFIG.26, the measurement conditions of the off-state current of the Si FET were as follows: a gate voltage VG=−0.4 V, a source voltage VS=0 V, a drain voltage VD=1.2 V, and a body voltage VB=0 V. In the case where a CAAC-OS FET was the DUT inFIG.26, the measurement conditions of the off-state current of the CAAC-OS FET were as follows: the gate voltage VG=−1.0 V, the source voltage VS=0 V, the drain voltage VD=1.2 V, and a back gate voltage VBG=−5.0 V.FIG.27shows the measurement results. InFIG.27, the horizontal axis represents 1000/absolute temperature (Temp.), and the vertical axis represents off-state current (offleak current). Note that inFIG.27, a broken line denoted by 1.0×10−13A/μm is a lower measurement limit of a normal measurement device.

As shown inFIG.27, the off-state current of the Si FET was approximately 3.1×10−11A/μm at a measurement temperature of 144° C. In a measurement temperature of 150° C., the off-state current of the CAAC-OS FET was approximately 2.5×10−18A/μm. The CAAC-OS FET can maintain a low off-state current even in a high-temperature environment. By adjusting the back gate voltage, the off-state current can be further reduced.

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