Diode and signal output circuit including the same

A diode includes: a p-type semiconductor substrate; an n-type semiconductor layer; a p-type isolation region formed to surround a predetermined region of the n-type semiconductor layer on the p-type semiconductor substrate; an n-type buried layer formed across the p-type semiconductor layer and the n-type semiconductor layer within the predetermined region; an n-type collector wall formed in the n-type semiconductor layer; a p-type anode region and a plurality of n-type cathode regions formed in a diode formation region; and a p-type guard ring formed to surround the diode formation region in a region between the diode formation region of the surface layer of the n-type semiconductor layer and the p-type isolation region. A transistor for reducing a leakage current is formed by the p-type anode region, the p-type guard ring, and an n-type semiconductor between the p-type anode region and the p-type guard ring.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japan Patent Applications No. 2013-254396, filed on Dec. 9, 2013, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a diode and a signal output circuit including the same.

BACKGROUND

A conventional diode used in a signal output device of a vehicle-mounted network has been known. Such a diode includes a p-type semiconductor substrate, an n-type semiconductor layer formed on the p-type semiconductor substrate, p-type isolation regions formed to surround a certain region of the n-type semiconductor layer on the p-type semiconductor substrate, an n-type buried layer formed across the p-type semiconductor substrate and the n-type semiconductor layer within the certain region, an n-type collector wall formed on the-type semiconductor layer and standing on a peripheral edge of an upper surface of the n-type buried layer toward a surface of the n-type semiconductor layer, and a p-type anode region and an n-type cathode region formed in a diode formation region within a region surrounded by the n-type collector wall of a surface layer of the n-type semiconductor layer.

In the foregoing conventional diode, a longitudinal PNP parasitic transistor is formed by an n-type semiconductor including the p-type anode region to which an anode is connected, the p-type semiconductor substrate, and the n-type buried layer between the p-type anode region and the p-type semiconductor substrate. In addition, a transverse PNP parasitic transistor is formed by an n-type semiconductor including the p-type anode region to which the anode is connected, the p-type isolation region, and the collector wall between the p-type anode region and the p-type isolation region. Since a current path is formed by such parasitic transistors, a leakage current flows in the p-type semiconductor substrate.

SUMMARY

The present disclosure provides some embodiments of a diode having a reduced amount of leakage current and a signal output circuit including the same.

According to one embodiment of the present disclosure, there is provided a diode including a p-type semiconductor substrate; an n-type semiconductor layer formed on the p-type semiconductor substrate; a p-type isolation region formed to surround a predetermined region of the n-type semiconductor layer on the p-type semiconductor substrate; an n-type buried layer formed across the p-type semiconductor layer and the n-type semiconductor layer within the predetermined region and having an impurity concentration higher than an impurity concentration of the n-type semiconductor layer; an n-type collector wall formed in the n-type semiconductor layer, standing on the n-type buried layer toward a surface of the n-type semiconductor layer to surround the predetermined region of the n-type semiconductor layer, and having an impurity concentration higher than the impurity concentration of the n-type semiconductor layer; a p-type anode region and a plurality of n-type cathode regions formed in a diode formation region, which is defined within a region surrounded by the n-type collector wall in a surface layer of the n-type semiconductor layer; and a p-type guard ring formed to surround the diode formation region in a region between the diode formation region of the surface layer of the n-type semiconductor layer and the p-type isolation region, and electrically connected to the cathode region. In addition, a transistor for reducing a leakage current is formed by the p-type anode region, the p-type guard ring, and an n-type semiconductor between the p-type anode region and the p-type guard ring.

In this configuration, a PNP transistor for reducing a leakage current is formed by the p-type anode region, the p-type guard ring, and an n-type semiconductor formed between the p-type anode region and the p-type guard ring. The p-type guard ring is connected to a cathode electrode such that a current flowing in the PNP transistor for reducing a leakage current is collected by the cathode electrode. The p-type guard ring, which serves as a collector of the PNP transistor for reducing a leakage current, is disposed at an inner side of the p-type isolation region. Thus, currents that intend to flow from within the diode formation region toward the p-type isolation region are mostly collected by the cathode electrode by means of the PNP transistor for reducing a leakage current. As a result, a diode having a reduced amount of leakage current can be realized.

In one embodiment, the p-type guard ring is formed to surround the diode formation region in a region between the diode formation region of the surface layer of the n-type semiconductor layer and the n-type collector wall, and the n-type semiconductor includes the n-type semiconductor layer.

In one embodiment, the p-type guard ring is formed to surround the diode formation region in a region between the n-type collector wall and the p-type isolation region, and the n-type semiconductor includes the n-type semiconductor layer and the n-type collector wall.

In one embodiment, a longitudinal parasitic PNP transistor is formed by the p-type anode region, the p-type semiconductor substrate, and the n-type semiconductor layer and the n-type buried layer between the p-type anode region and the p-type semiconductor substrate, and a transverse parasitic PNP transistor is formed by the p-type anode region, the p-type isolation region, and the n-type semiconductor layer and the n-type collector between the p-type anode region and the p-type isolation region.

A current amplification factor of the longitudinal PNP parasitic transistor may be easily lowered by setting a high impurity concentration of the n-type buried layer. On the other hand, since the n-type collector wall extends in a longitudinal direction (i.e., a normal direction of the surface of the p-type semiconductor substrate), it may be difficult to set a high impurity concentration across the entire region. Thus, if the current amplification factor of the longitudinal PNP parasitic transistor is sought to be reduced, a current amplification factor of the transverse parasitic PNP transistor becomes higher than that of the longitudinal PNP parasitic transistor. Accordingly, a leakage current by the transverse PNP parasitic transistor is greater than a leakage current by the longitudinal PNP parasitic transistor.

In this configuration, the p-type guard ring, which serves as a collector of the PNP transistor for reducing a leakage current, is disposed at an inner side of the p-type isolation region, which serves as a collector of the transverse parasitic PNP transistor. Thus, currents that intend to flow from within the diode formation region toward the p-type isolation region are mostly collected in the cathode electrode by means of the PNP transistor for reducing a leakage current. Accordingly, a current flowing in the transverse parasitic PNP transistor can be suppressed such that a diode having a reduced amount of leakage current can be realized.

In one embodiment, a current amplification factor of the transverse parasitic PNP transistor is higher than a current amplification factor of the longitudinal parasitic PNP transistor.

In one embodiment, a current amplification factor of the transistor for reducing a leakage current is higher than a current amplification factor of the longitudinal parasitic PNP transistor.

In one embodiment, a diode structure including the p-type anode region and the n-type cathode regions is formed in the diode formation region, and the diode structure has an n-channel DMIS transistor structure.

In one embodiment of the present disclosure, the diode structure includes the p-type anode region formed in the surface layer of the n-type semiconductor layer; an n-type region and a p-type contact region formed in a surface layer of the p-type anode region; the n-type cathode regions formed in the surface layer of the n-type semiconductor layer and disposed to be spaced apart from both sides of the p-type anode region; an n-type contact region formed in surface layers of the n-type cathode regions; a gate insulating film formed on a surface of the n-type semiconductor layer in a region between the n-type region and the n-type contact region; and a gate electrode formed on the gate insulating film, and electrically connected to the anode region.

In another embodiment, provided is a signal output circuit, including an output terminal; the diode; and a switching element connected between a cathode of the diode and a ground. An anode of the diode is connected to the output terminal. With this configuration, since a leakage current of the diode is small, a current flowing from an output terminal to a ground through the diode can be suppressed when a switching element is turned off. Accordingly, when the switching element is turned off, the output terminal can output an appropriate output signal.

DETAILED DESCRIPTION

FIG. 1illustrates an electric circuit diagram of a signal output circuit employing a diode, according to a first embodiment of the present disclosure. A signal output circuit1is, for example, a signal output circuit used in a controller area network (CAN), which is a type of a vehicle-mounted network. The signal output circuit1includes a high-side output unit2, a low-side output unit3, a resistance dividing circuit4, a high-side output terminal5, and a low-side output terminal6.

The high-side output unit2includes a driving transistor7, a backflow prevention diode8connected in series to the driving transistor7, and a protection transistor9connected in series to the backflow prevention diode8. In this embodiment, the driving transistor7and the protection transistor9may be configured as p-type MOS transistors (PMOS). A source of the driving transistor7is connected to a first power source VCC1. A drain of the driving transistor7is connected to an anode of the backflow prevention diode8. A cathode of the backflow prevention diode8is connected to a source of the protection transistor9. A drain of the protection transistor9is connected to the high-side output terminal5. A gate of the protection transistor9is grounded.

The low-side output unit3includes a backflow prevention diode10, a protection transistor11connected in series to the backflow prevention diode10, and a driving transistor12connected in series to the protection transistor11. In this embodiment, the protection transistor11and the driving transistor12may be configured as n-type MOS transistors (NMOS). An anode of the backflow prevention diode10is connected to the low-side output terminal6. A cathode of the backflow prevention diode10is connected to a drain of the protection transistor11. A gate of the protection transistor11is connected to a first power source VCC1. A source of the protection transistor11is connected to a drain of the driving transistor12. A source of the driving transistor12is grounded.

The resistance dividing circuit4includes a first resistor13having one end connected to the high-side output terminal5and a second resistor14having one end connected to the other end of the first resistor13. The other end of the second resistor14is connected to the low-side output terminal6. A second power source VCC2is connected to a connection point between the first resistor13and the second resistor14. The high-side output terminal5is connected to a first bus line, and the low-side output terminal6is connected to a second bus line. A termination resistor15is connected between the first bus line and the second bus line.

A control signal is given to a gate of the driving transistor7, and an inversion signal of the control signal is given to a gate of the driving transistor12. When the control signal has a low (L) level, both driving transistors7and12are turned on. Thus, a bus signal CANH having 3.5V (standard value) is output at the high-side output terminal5, and a bus signal CANL having 1.5 V (standard value) is output at the low-side output terminal6(dominant state). On the other hand, when the control signal has a high (H) level, both driving transistors7and12are turned off. Thus, a bus signal CANH having 2.5 V (standard value) is output at the high-side output terminal5, and a bus signal CANL having 2.5 V (standard value) is output at the low-side output terminal (recessive state).

The backflow prevention diode10of the low-side output unit3may be configured as a diode of the first embodiment of the present disclosure. When a large amount of leakage current is flowing from the backflow prevention diode10, a current flows from the low-side output terminal6to a ground through the backflow prevention diode10, even though the driving transistor12is turned off. As such, the bus signals CANH and CANL may deviate from the standard values. Thus, a diode of this embodiment that generates a small amount of leakage current may be used as the backflow prevention diode10of the low-side output unit3. A structure of the backflow prevention diode10(hereinafter, “diode10”) will be described in detail below.

FIG. 2illustrates a schematic plan view indicative of a structure of the diode10, according to a first embodiment of the present disclosure.FIG. 3illustrates a cross-sectional view taken along line III-III ofFIG. 2. As shown inFIG. 2, for example, the diode10has a quadrangular chip shape in a plan view. The diode10includes a p-type semiconductor substrate (P-SUB)21. An n-type epitaxial layer (N-epi)22is stacked as an n-type semiconductor layer on the surface of the p-type semiconductor substrate21. In addition, a p-type isolation region23, which has a quadrangular annular shape and surrounds the n-type epitaxial layer22, is formed on the surface of the p-type semiconductor substrate21.

The p-type isolation region23includes a lower isolation region (1stL/I (Low Isolation))24connected to the p-type semiconductor substrate21, a middle isolation region (L/I)25formed on the lower isolation region24, and an upper isolation region (HV P-well)26formed on the middle isolation region25. A p+-type substrate contact region27is formed in an upper layer of the upper isolation region26. A grounded substrate electrode51is connected to the p+-type substrate contact region27.

In a boundary between the n-type epitaxial layer22and the p-type semiconductor substrate21, an n-type buried layer (B/L)28having an impurity concentration higher than that of an n-type epitaxial layer22is formed across the p-type semiconductor substrate21and the n-type epitaxial layer22. Also, an n-type collector wall29, which stands on a peripheral edge of an upper surface of the n-type buried layer28toward a surface of the n-type epitaxial layer22and has an impurity concentration higher than that of the n-type epitaxial layer22, is formed in the n-type epitaxial layer22.

The n-type collector wall29includes a lower collector wall (C/W)30connected to the p-type semiconductor substrate21, and an upper collector wall (2ndC/W)31formed on the lower collector wall30. An n+-type layer32is formed in an upper layer of the upper collector wall (2ndC/W)31. A diode formation region33, which has a quadrangular shape as illustrated in the plan view ofFIG. 2, is defined within a region (n-type epitaxial layer22) surrounded by the n-type buried layer28and the n-type collector wall29. Also, a p-type well34is formed in a surface layer of the n-type epitaxial layer22as a p-type guard ring to surround the diode formation region33in a region between the diode formation region33and the n-type collector wall29. A p+-type cathode contact region35is formed in a surface layer of the p-type well34.

As shown inFIG. 2, a plurality of diode structures40, each of which has the same structure, is formed in a surface layer of the n-type epitaxial layer22within the diode formation region33. Each of the diode structures40extends in a predetermined direction (a vertical direction on the paper ofFIG. 2), as illustrated in the plan view ofFIG. 2. The plurality of diode structures40extends to be parallel with each other while being spaced apart from each other by a predetermined interval. Thus, such diode structures40are formed in a stripe shape, as illustrated in the plan view ofFIG. 2. In the first embodiment, each of the diode structures40has an n-channel DMIS transistor structure.FIG. 3is illustrated with only a single diode structure40, which may be located at one end of the diode formation region33, among the plurality of diode structures40.

As shown inFIG. 3, the diode structure40includes a p-type well (P-BASE)41formed in a surface layer of the n-type epitaxial layer22as an anode region (p-type body region), and two n-type wells (N-well)42formed to be spaced apart from both sides of the p-type well41as cathode regions (n-type drift layers), respectively. The p-type well41and the n-type wells42are formed in a quadrangular shape elongated in a length direction of the diode structure40in the plan view.

A p+-type anode contact region43and n+-type regions44disposed on both sides of the p+-type anode contact region43are formed in a surface layer of the p-type well41. N+-type cathode contact regions45are formed in surface layers of the n-type wells42. A surface of the n-type epitaxial layer22is covered with field oxide films46, except for the p+-type substrate contact region27, the n+-type layer32, the p+-type cathode contact region35, the n+-type cathode contact regions45, portions close to the p-type well41in the upper surface of each of the n-type wells42, and a region between the n-type wells42.

The diode structure40additionally includes gate insulating films47and gate electrodes48. The gate insulating films47are formed on a surface of the n-type epitaxial layer22in a region between each of the field oxide films46, which are disposed between the n+-type cathode contact regions45of the n-type wells42and the p-type well41, and each of the n+-type regions44within the p-type well41that is close to the associated field oxide film46. The gate electrodes48are formed to cover the gate insulating films47and a portion of the field oxide films46disposed between the gate insulating films47and the n+-type cathode contact regions45.

The p+-type anode contact region43of the p-type well41and the gate electrodes48are connected to an anode electrode52. The n+-type cathode contact regions45of the n-type wells42and the p+-type cathode contact region35within the p-type well (p-type guard ring)34are connected to a cathode electrode53. A PN junction diode Di1is formed by the p-type well41, the n-type well42adjacent to one side of the p-type well41, and the n-type epitaxial layer22between the p-type well41and the n-type well42, while a PN junction diode Di2is formed by the p-type well41, the n-type well42adjacent to the other side of the p-type well41, and the n-type epitaxial layer22between the p-type well41and the n-type well42. Also, a PNP transistor Tr1for reducing a leakage current is formed by the p-type well41, the p-type guard ring (p-type well)34, and the n-type epitaxial layer22between the p-type well41and the p-type guard ring (p-type well)34.

When a forward bias is applied between the anode electrode52and the cathode electrode53, a current flows from the anode electrode52to the cathode electrode53through the PN junction diodes and the PNP transistor Tr1for reducing a leakage current. This diode10may be manufactured by a BiCDMOS (Bipolar CMOS DMOS) process. The p-type well34may be formed as a p-type guard ring through a process identical to that of the upper isolation region26of the p-type isolation region23. In addition, the p+-type cathode contact region35within the p-type well34may be formed through a process identical to that of the p+-type substrate contact region27within the upper isolation region26.

In the diode10, a longitudinal parasitic PNP transistor Tr2is formed by the p-type well41, the p-type semiconductor substrate21, and the n-type semiconductor (the n-type epitaxial layer22and the n-type buried layer28) between the p-type well41and the p-type semiconductor substrate21. Additionally, a transverse parasitic PNP transistor Tr3is formed by the p-type well41, the p-type isolation region23, and the n-type epitaxial layer22between the p-type well41and the p-type isolation region23.

An impurity concentration of the n-type buried layer28having a small thickness in a longitudinal direction may be set to be high. Thus, a current amplification factor hfe of the longitudinal PNP parasitic transistor Tr2may be lowered such that a leakage current through the longitudinal PNP parasitic transistor Tr2can be easily reduced. On the other hand, since the n-type collector wall29extends in a longitudinal direction (i.e., a normal direction of the surface of the p-type semiconductor substrate21), it may be difficult to set a high impurity concentration across the entire region. Thus, a current amplification factor of the transverse PNP parasitic transistor Tr3is higher than that of the longitudinal PNP parasitic transistor Tr2such that a leakage current by the transverse PNP parasitic transistor Tr3is greater than a leakage current by the longitudinal PNP parasitic transistor Tr2. Given those, in order to realize a diode having a small amount of leakage current, it is important to suppress a current, which flows in the transverse PNP parasitic transistor Tr3.

The PNP transistor Tr1for reducing a leakage current is formed in the diode10, separately from the longitudinal PNP parasitic transistor Tr2and the transverse PNP parasitic transistor Tr3. In one embodiment, a current amplification factor of the PNP transistor Tr1for reducing a leakage current is greater than that of the longitudinal PNP parasitic transistor Tr2. The p-type guard ring (p-type well)34is connected to the cathode electrode53, and thus, a current, which flows in the PNP transistor Tr1for reducing a leakage current, is collected in the cathode electrode53.

The p-type guard ring (p-type well)34, which has an annular shape as illustrated in the plan view and becomes a collector of the PNP transistor Tr1for reducing a leakage current, is disposed on an inner side of the p-type isolation region23, which has an annular shape as illustrated in the plan view and becomes a collector of the transverse parasitic PNP transistor Tr3. Thus, in the n-type epitaxial layer22, currents that intend to flow from within the diode formation region33toward the p-type isolation region23are mostly collected in the cathode electrode53by means of the PNP transistor Tr1for reducing a leakage current. Accordingly, a current flowing in the transverse parasitic PNP transistor Tr3can be suppressed such that a diode having a small amount of leakage current can be realized.

FIG. 4Aillustrates a waveform view showing a result of measuring an output signal waveform of the signal output circuit1ofFIG. 1. InFIG. 4A, CANH represents a bus signal waveform output at the high-side output terminal5, while CANL represents a bus signal waveform output at the low-side output terminal6. InFIG. 4A, COMMON represents a common voltage (i.e., CANH+CANL/2). If both driving transistors7and12are in an ON state, a value of the bus signal CANH becomes a value approximate to 3.5V of the standard value and a value of the bus signal CANL becomes a value approximate to 1.5V of the standard value. On the other hand, if the driving transistors7and12are in an OFF state, values of the bus signal CANH and the bus signal CANH become values approximating to 2.5V of the standard value. In addition, a difference between a common voltage COMMON in an ON state of the driving transistors7and12and a common voltage COMMON in an OFF state of the driving transistors7and12is small.

A diode, which has a structure formed by removing the p-type guard ring (p-type well)34from the diode10illustrated inFIG. 3, will be used as a comparative example. Output signal waveforms were measured based on the comparative example, instead of the diode10in the signal output circuit1ofFIG. 1.FIG. 4Billustrates a waveform view showing the measurement results in case of the comparative example. InFIG. 4B, it can be seen that the bus signals deviate from the standard values. In particular, it can be seen that the bus signals in an OFF state of the driving transistors7and12are significantly reduced relative to the standard value (2.5V), reaching a value approximate to 1.5V.

FIG. 5illustrates a schematic plan view indicative of a structure of a diode10A according to a second embodiment of the present disclosure, andFIG. 6illustrates a cross-sectional view taken along line VI-VI ofFIG. 5. InFIGS. 5 and 6, the same reference numerals as those ofFIGS. 2 and 3will be used for components corresponding to those ofFIGS. 2 and 3as described above. When compared with the diode10inFIGS. 2 and 3of the first embodiment, in the diode10A of the second embodiment of the present disclosure, relative positional relations of the p-type well34serving as a p-type guard ring and the n-type collector wall29are reversed. Except for this, the diode10A is identical to the diode10. Specifically, in the diode10of the first embodiment, the p-type well34is formed as a p-type guard ring in a region between the diode formation region33and the n-type collector wall29to surround the diode formation region33. On the other hand, in the diode10A of the second embodiment, the p-type well34is formed as a p-type guard ring in a region between the n-type collector wall29and the p-type isolation region23to surround the diode formation region33(n-type collector wall29) in an outer side of the n-type collector wall29.

In the diode10A of the second embodiment, a diode having a small amount of leakage current can be realized through an operation identical to that of the diode10of the first embodiment. As can be seen from the first and second embodiments described above, it may be desirable for the p-type well34to be formed as a p-type guard ring in a region between the diode formation region33and the p-type isolation region23for surrounding the diode formation region33.

FIG. 7is a schematic cross-sectional view indicative of a structure of a diode10B according to a third embodiment of the present disclosure. InFIG. 7, the same reference numerals as those ofFIG. 3will be used for components corresponding to those ofFIG. 3described above. The diode10B of the third embodiment is similar to the diode10of the first embodiment inFIGS. 2 and 3. The diode10B of the third embodiment is identical to the diode10of the first embodiment, except for a configuration of a diode structure40A.

The diode structure40A of the diode10B in the third embodiment includes a p-type well (P-BASE)41formed in a surface layer of the n-type epitaxial layer22as an anode region and two n-type wells (N-wells)42formed to be spaced apart from both sides of the p-type well41as cathode regions, respectively, in the same configuration as the diode structure40of the diode10in the first embodiment,. The p+-type anode contact region43is formed in a surface layer of the p-type well41. The p+-type anode contact region43is connected to the anode electrode52. The n+-type cathode contact regions45are formed in surface layers of the n-type wells42. The n+-type cathode contact regions45are connected to the cathode electrode53.

On the other hand, in the diode structure40A of the diode10B in the third embodiment, the n+-type regions44, which are described in the first embodiment, are not formed in the surface layer of the p-type well41. Additionally, the gate insulating films47and the gate electrodes48, which are described in the first embodiment, are not installed in the diode structure40A of the diode10B. The diode10B of the third embodiment can also realize a diode having a small amount of leakage current through an operation identical to that of the diode10in the first embodiment.

FIG. 8is a schematic cross-sectional view indicative of a structure of a diode10C, according to a fourth embodiment of the present disclosure. InFIG. 8, the same reference numerals as those ofFIG. 3will be used for components corresponding to those ofFIG. 3described above. The diode10C of the fourth embodiment is similar to the diode10A according to the second embodiment inFIGS. 5 and 6. The diode10C of the fourth embodiment is identical to the diode10A of the second embodiment, except for a configuration of a diode structure40B. The diode structure40B of the diode10C in the fourth embodiment has a configuration identical to that of the diode structure40A of the diode10B in the third embodiment described above with reference toFIG. 7.

That is, the diode structure40B of the diode10C in the fourth embodiment includes a p-type well (P-BASE)41formed in a surface portion of the n-type epitaxial layer22as an anode region, and two n-type wells (N-wells)42formed to be spaced apart from both sides of the p-type well41as cathode regions, respectively. The p+-type anode contact region43is formed in a surface layer of the p-type well41. The p+-type anode contact region43is connected to the anode electrode52. The n+-type cathode contact regions45are formed in surface layers of the n-type wells42. The n+-type cathode contact regions45are connected to the cathode electrode53.

On the other hand, in the diode structure40B of the diode10C in the fourth embodiment, the n+-type regions44, which are described in the first embodiment, are not formed in the surface layer of the p-type well41. Additionally, the gate insulating films47and the gate electrodes48, which are described in the first embodiment, are not installed in the diode structure40B of the diode10C. The diode10C of the fourth embodiment may also realize a diode having a small amount of leakage current through an operation identical to that of the diode10A in the second embodiment.

As described above, the embodiments in case that the present disclosure is applied to the diodes for a signal output circuit used in a CAN have been described, but the present disclosure may also be applied to a diode for a signal output circuit used in any other vehicle-mounted network (e.g., a local interconnect network (LIN), FlexRay, and the like), a diode for a vehicle-mounted switch IC, a diode for a DC/DC converter, etc. In addition, the present disclosure may be applied to a diode used in a circuit other than a vehicle-mounted circuit, etc.

FIG. 9is an electrical circuit diagram showing an example in case that the present disclosure is applied to a signal output circuit used in a LIN. The signal output circuit101includes a resistor102, an output terminal103, a backflow prevention diode104, a protection transistor105, and a driving transistor106. One end of the resistor102is connected to a third power source VCC3, and the other end of the resistor102is connected to the output terminal103. An anode of the backflow prevention diode104is connected to the output terminal103, and a cathode of the backflow prevention diode104is connected to a drain of the protection transistor105. A source of the protection transistor105is connected to a drain of the driving transistor106. A source of the driving transistor106is grounded. A base of the protection transistor105is connected to a fourth power source VCC4. The output terminal103is connected to a bus line.

When the driving transistor106is turned on, a low level bus signal is output at the output terminal103. On the other hand, when the driving transistor106is turned off, a high level bus signal is output at the output terminal103. When there is much leakage current from the backflow prevention diode104, a current flows from the output terminal103to a ground through the backflow prevention diode104, even though the driving transistor106is turned off. As such, a voltage output at the output terminal103deviates from a standard value. Thus, the diodes in the embodiments described above are used as the backflow prevention diode104.