Data storage device, operating method of the same, and electronic system including the same

A data storage device, a method of operating the data storage device, and an electronic system including the data storage device are provided. The data storage device includes a controller mounted on a substrate, and a plurality of memory packages configured to be controlled by the controller and to transmit and receive data to and from the controller via M channels (where M is an integer of 1 to 16). When the data storage device is used, a phenomenon in which heat generation is concentrated locally may be mitigated.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2017-0026474, filed on Feb. 28, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

FIELD

The inventive concept relates to a data storage device, a method of operating the data storage device, and an electronic system including the data storage device, and more particularly, to a data storage device for preventing a phenomenon in which heat generation is concentrated locally, a method of operating the data storage device, and an electronic system including the data storage device.

BACKGROUND

Data storage devices, such as solid state drives (SSDs), are increasingly in demand as the data storage devices have the ability to quickly input and output large amounts of data thereto and therefrom. An SSD includes a controller and many non-volatile memory packages, and thus, device damage and performance degradation may occur in the SSD due to heat generation. Therefore, much research has been conducted into a method of reducing the amount of heat generated in the SSD.

SUMMARY

The inventive concept provides a data storage device which may exhibit improved data storage performance and reduced damage to a semiconductor device, as a phenomenon in which heat generation is concentrated locally is mitigated.

The inventive concept also provides a method of operating a data storage device which may exhibit improved data storage performance and reduced damage to a semiconductor device, as a phenomenon in which heat generation is concentrated locally is mitigated.

The inventive concept also provides an electronic system including a data storage device which may exhibit improved data storage performance and reduced damage to a semiconductor device, as a phenomenon in which heat generation is concentrated locally is mitigated.

According to an aspect of the inventive concept, there is provided a data storage device including: a controller mounted on a substrate; and a plurality of memory packages each having at least one semiconductor die, the memory packages being configured to be controlled by the controller and to transmit and receive data to and from the controller via M channels (where M is a first integer of 1 to 16). Each of the M channels includes N ways (where N is a second integer of 2 to 128), and semiconductor dies belonging to one channel are each configured to transfer a write operation to another semiconductor die belonging to the one channel when a write operation transfer condition is satisfied.

According to another aspect of the inventive concept, there is provided a data storage device including: a controller mounted on a substrate; and a plurality of memory packages, wherein the plurality of memory packages are configured to transmit and receive data to and from the controller via M channels (where M is a first integer of 1 to 16), wherein each of the M channels includes N ways (where N is a second integer of 2 to 128) and P memory packages (where P is a third integer of 2 to 64), and the controller is configured such that the numbers of ways respectively corresponding to the P memory packages are equal to each other when a write operation of data is performed through one channel.

According to another aspect of the inventive concept, there is provided a method of operating a data storage device including a controller and a plurality of memory packages configured to be controlled by the controller and to transmit and receive data to and from the controller via M channels (where M is a first integer of 1 to 16), each of which includes N ways (where N is a second integer of 2 to 128), each of the memory packages having at least one semiconductor die. The method includes: performing a write operation on a semiconductor die included in one of a plurality of memory packages belonging to one channel; determining whether a package switching condition is satisfied; and performing a next write operation on another semiconductor die included in another memory package belonging to the one channel when it is determined that the package switching condition is satisfied.

According to another aspect of the inventive concept, there is provided an electronic system including: a host; and a data storage device configured to write data therein in response to a write command input from the host, wherein the data storage device includes a controller and a plurality of memory packages configured to be controlled by the controller and to transmit and receive data to and from the controller via M channels (where M is a first integer of 1 to 16), each of which includes N ways (where N is a second integer of 2 to 128), each of the memory packages having at least one semiconductor die, wherein semiconductor dies belonging to one channel are each configured to transfer a write operation to another semiconductor die in the one channel when a write operation transfer condition is satisfied, and are each configured such that transfer of the write operation between packages is performed on a semiconductor die of another memory package in the one channel when a package switching condition is satisfied.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The circuit configuration and operation of a data storage device according embodiment of the inventive concept will be described as an example below, and the data storage device may be variously changed and modified without departing from the technical idea of the inventive concept. For example, among semiconductor memory devices, a solid state drive (SSD) employing a NAND flash memory as a main storage device will be described as the data storage device. However, this is merely an example to which the inventive concept is applied, and the data storage device and a data storage method thereof may be applied to various types of data storage devices as well as SSDs.

FIG. 1is a block diagram conceptually illustrating the configuration of a memory system1including a data storage device10according to an embodiment of the inventive concept.

Referring toFIG. 1, memory system1may include data storage device10, which is an SSD, and a host20. Data storage device10may include a controller100, a buffer memory200, and a data storage unit300.

Data storage unit300is main data storage of data storage device10and stores data by using semiconductor memory dies instead of a platter of a hard disk drive (HDD). Data storage unit300may include a non-volatile memory or a volatile memory, and a plurality of channels, for example, M channels CH0, CH1, . . . , CH(M−1) (seeFIG. 2), may be provided between controller100and data storage unit300. Each of the plurality of channels may be provided with a plurality of ways, for example, N ways. M may be a first integer from 1 to 16 and N may be a second integer from 2 to 128. However, the inventive concept is not limited thereto.

Here, a ‘channel’ is a unit for which a data write operation may be independently performed. Thus, a write operation for each channel may be performed in parallel (i.e., overlapping). A ‘way’ may be one or more memories that share a command channel and a data channel.

Hereinafter, data storage unit300will be described as including a non-volatile memory. However, it will be understood by those skilled in the art that a memory to be applied to data storage unit300may be configured in various forms without being limited to specific types and specific forms. For example, the memory applied to data storage unit300may include a non-volatile memory, such as a flash memory, a vertical NAND (VNAND) memory, a magnetoresistive random-access memory (MRAM), a phase-change RAM (PRAM) memory, or a resistive RAM (ReRAM) memory. In addition, the memory applied to data storage unit300may include a volatile memory such as DRAM. In some embodiments, data storage unit300may include a combination of at least one non-volatile memory and at least one volatile memory. In some embodiments, data storage unit300may include a combination of at least two types of non-volatile memories.

The number of data bits stored in each memory cell of the flash memories provided in data storage unit300may be variously configured. For example, the flash memories may include single-level flash memory cells, each of which stores one bit of data. In some embodiments, the flash memories may include multi-level flash memory cells, each of which stores a plurality of bits of data (e.g., two bits of data, four bits of date, etc.). In the case of a multi-level flash memory cell, a program time may vary depending on whether a least significant bit (LSB) or a most significant bit (MSB) is written. In addition, the program time may be variously configured according to a configuration manner of different flash memory cells, such as FN35, FN42, and FN51 which may have different channel widths.

Furthermore, the flash memories may be configured with various types of memory cells. For example, the flash memories may include at least one of a NAND flash memory, a NOR flash memory, and a One_NAND flash memory (e.g., a flash memory in which a flash memory core and a memory control logic are implemented as a single chip), or may be configured in a hybrid form in which at least two types of flash memories are combined. In addition, the structure of a charge storage layer in each of the memory cells of the flash memories may also be configured in various forms. For example, the charge storage layer of the memory cell may include conductive polycrystalline silicon or the like, or may include an insulating film such as a Si3N4, Al2O3, HfAlO, or HfSiO film. A flash memory having a structure using, as the charge storage layer, an insulating film such as a Si3N4, Al2O3, HfAlO, or HfSiO film may be referred to as a charge trap flash (CTF) memory.

Buffer memory200may temporarily store data transmitted and received between controller100and data storage unit300and data transmitted and received between controller100and host20. In controller100, a buffer memory control function for controlling a data input/output operation of buffer memory200may be provided. This may mean that the data input/output operation of buffer memory200may be performed through controller100. Buffer memory200may be provided outside controller100, as shown inFIG. 1, or may be provided inside controller100in another embodiment. Buffer memory200may be random access memory (RAM) such as DRAM or SRAM.

Controller100may control an operation of writing data to data storage unit300or reading data from data storage unit300in response to a command input from host20. Controller100controls all operations of the SSD and is also referred to as an SSD controller. Controller100may include one or more central processing units (CPUs) or cores for controlling the operation of controller100.

Controller100may perform a function of queuing a plurality of commands to be executed by data storage unit300and a function of controlling operation periods (particularly, a read period of a read command and a data transmission period) of queued commands Native command queuing (NCQ), tagged command queuing (TCQ), or the like may be used for queuing a plurality of commands to be performed.

As will be described in more detail below, controller100may control a write operation to be physically and/or temporally substantially evenly distributed between memory packages corresponding to each channel. As a result, heat generated from each memory package may be more evenly distributed without being locally concentrated. Accordingly, the operation of the SSD may be smoothly performed without deteriorating the overall performance of the SSD.

FIG. 2is a block diagram illustrating a detailed configuration of controller100in data storage device10shown inFIG. 1, according to an embodiment of the inventive concept.

Referring toFIG. 2, controller100may include a central processing unit (CPU)110, an internal memory120, a buffer memory control unit130, a host interface170, and a flash interface180. CPU110, internal memory120, buffer memory control unit130, host interface170, and flash interface180may be electrically connected to each other via a CPU bus.

CPU110may control various operations of controller100. In controller100, one or more CPUs110may be provided. A case where one CPU or core is provided is referred to as a single core processor, and a case where a plurality of CPUs or cores are provided is referred to as a multi-core processor. CPU110, internal memory120, and buffer memory control unit130may form a control circuit. The control circuit formed of CPU110, internal memory120, and buffer memory control unit130may be configured as a single chip based on system on chip (SoC) technology.

The control circuit formed of CPU110, internal memory120, and buffer memory control unit130may be driven by firmware installed in controller100. Additional information (e.g., mapping information and the like) processed by the firmware may be stored in a data area of internal memory120or may be stored in data storage unit300. Internal memory120may be provided inside CPU110or may be provided outside CPU110.

Host interface170may exchange commands, addresses, and data with host20inFIG. 1under the control of CPU110. Host interface170may support one of various interface protocols, such as a Universal Serial Bus (USB) interface, a MultiMediaCard (MMC) interface, a PCI Express (PCI-E) interface, a Serial Advanced Technology Attachment (SATA) interface, a Parallel Advanced Technology Attachment (PATA) interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), an Enhanced Small Disk Interface (ESDI), and an Integrated Drive Electronics (IDE) interface. Buffer memory control unit130may control write, read, and erase operations of internal memory120and buffer memory200in response to the control of CPU110. Flash interface180may perform data transmission and reception between internal memory120and/or buffer memory200and data storage unit300.

When a read command is input from host20, read data read from data storage unit300may be temporarily stored in buffer memory200through flash interface180and buffer memory control unit130. The read data temporarily stored in buffer memory200may be output to the outside (or host20) through buffer memory control unit130and host interface170.

A write command input from host20may be performed in two steps, i.e., first and second steps. In the first step, write data input through host interface170is temporarily stored in buffer memory200through buffer memory control unit130. In the second step, the write data temporarily stored in buffer memory200is programmed into data storage unit300through buffer memory control unit130and flash interface180. The first step may be referred to as a buffer memory write operation, and the second step may be referred to as a NAND program job (NPJ) or a flash program operation. The NPJ may be performed in parallel through a plurality of channels (e.g., M channels) provided in data storage unit300.

A function of temporarily storing read/write data may be performed using a data area of internal memory120in addition to buffer memory200. As the size of the read/write data increases, the function of temporarily storing the read/write data may be performed mainly in buffer memory200, rather than in internal memory120.

In an exemplary embodiment, while executing the write command, CPU110may provide a signal indicating the end of a write command to host20via host interface170when simply a buffer memory write operation is completed. An NPJ that has not yet been processed may be internally performed in data storage device10at an appropriate time when CPU110is not busy.

A plurality of channels (e.g., M channels) CH0, CH1, . . . , CH(M−1) may be formed between controller100and data storage unit300. A plurality of memory packages310,320, . . . ,330may be electrically connected to the plurality of channels CH0, CH1, . . . , CH(M−1), respectively. Each of memory packages310,320, . . . ,330may include a plurality of semiconductor dies. The plurality of semiconductor dies may be stacked and be electrically interconnected via bonding wires, solder bumps, and/or through silicon vias (TSVs).

The channels CH0, CH1, . . . , CH(M−1) may denote buses capable of sending and receiving commands and data to memory packages310,320, . . . ,330, respectively. Memory packages310,320, . . . ,330connected to the different channels CH0, CH1, . . . , CH(M−1) may each operate independently. Memory packages310,320, . . . ,330connected to the channels CH0, CH1, . . . , CH(M−1), respectively, may each configure a plurality of ways Way0, Way1, . . . , Way(N−1). N or more semiconductor dies may be connected to N ways configured in each channel. For example, (N+1) to 16N semiconductor dies may be provided for N ways configured in each channel.

For example, memory package310may configure N ways Way0, Way1, . . . , Way(N−1) in the channel CH0. More semiconductor dies than N ways may be connected to the channel CH0. The correspondence between the channel and the memory package may be equally applied to other channels CH1, . . . , CH(M−1).

FIGS. 3A and 3Bare flowcharts illustrating a method of operating a data storage device, according to embodiments of the inventive concept.FIGS. 4A and 5Aare timing diagrams illustrating a scheme in which a write operation is performed on semiconductor dies via each way through an arbitrary channel of data storage unit300ofFIG. 2.FIGS. 4B and 5Bare conceptual diagrams showing the operation of the scheme.FIG. 4Cis a timing diagram more specifically showing each component of the timing diagram ofFIG. 4A.

Referring toFIGS. 3A, 4A, and 4B, two packages, that is, a first memory package PKG1and a second memory package PKG2, may correspond to the channel CH0. Eight semiconductor dies may be included in each of the first memory package PKG1and the second memory package PKG2. It will be understood by one of ordinary skill in the art that less or more than eight semiconductor dies may be included in each of the first memory package PKG1and the second memory package PKG2. The channel CH0may be electrically connected to the first memory package PKG1and the second memory package PKG2, and whether to use the first memory package PKG1and the second memory package PKG2may be determined by a first chip enable pin CEP1and a second chip enable pin CEP2, respectively. In some embodiments, one memory package may include a plurality of chip enable pins. The number of ways corresponding to one chip enable pin CEP1or CEP2may be less than the number of semiconductor dies corresponding to the one enable pin CEP1or CEP2. The number of chip enable pins corresponding to one channel may be less than the number of ways in the one channel.

Each component of the timing diagram shown inFIG. 4Ais more specifically shown inFIG. 4C. Referring toFIG. 4C, operations such as “command”510, “data”512, and “program”514may be performed in order for data to be written in a semiconductor die. A part indicated by program514may be a period during which data is actually written to the semiconductor die.

In controller100, data and commands may exist for each of the channels CH0, CH1, . . . , CH(M−1). Thus, write operations for the channels CH0, CH1, . . . , CH(M−1) may be completely overlapped and performed in parallel. Therefore, only the channel CH0will be described here, and description of other channels will be omitted.

In the 0thto 3rdways Way0, Way1, Way2, and Way3of the channel CH0, the operations, such as command510, data512, and program514, may not completely overlap. That is, the operations of command510and data512may be performed only in one way at a time in the order of the ways. Meanwhile, the operation of program514may be performed in parallel in the 0thto 3rdways Way0, Way1, Way2, and Way3, and the program operation514performed in one way may also be performed in parallel with a command operation510and a data operation512of another way.

Command510and data512may be transferred through the 0thway Way0, and then the operation of program514may be performed. When a write operation transfer condition described later is satisfied, command510and data512may be transferred through the 1stway Way1, and then the operation of program514may be performed. A write operation may be performed through the 2ndway Way2and the 3rdway Way3in the same manner.

As shown inFIG. 4C, the write operation transfer condition is whether or not command510and data512have been transferred through a corresponding way. That is, when command510and data512have been transferred through a corresponding way, then a next write operation may be performed through the next way.

As described above, the operation of program514may be performed in parallel and thus the transfer of command510and data512via the next way may be allowed even if the operation of program514in the previous way is not terminated.

For example, Δt (seeFIG. 4A), which is a specified time interval between a write operation through the 0thway Way0and a next write operation through 1stway Way1, may correspond to a transfer time of command510and data512through the 0thway Way0inFIG. 4C. However, the inventive concept is not limited thereto.

Referring back toFIG. 4A, semiconductor dies D11, D12, . . . , D18, D21, D22, . . . , D28belonging to the 0thchannel CH0may be configured so that a next write operation is sequentially transferred to another semiconductor die in the same channel when a write operation transfer condition is satisfied. For example, at time t1, a first write operation is performed on the semiconductor die D11of the first memory package PKG1through the 0thway Way0(Operation S110). Then, it is determined whether or not a write operation transfer condition is satisfied (Operation S130). When the write operation transfer condition is satisfied at time t2, a next write operation may be performed on the semiconductor die D12of the first memory package PKG1through the 1stway Way1(Operation S170). Here, the write operation transfer condition may be that a time interval of writing data to the semiconductor die D11of the first memory package PKG1corresponds to the specified time interval Δt or the size of data to the semiconductor die D11of the first memory package PKG1written between times t1and t2corresponds to a threshold amount of data.

A write operation may be transferred such that a next write operation on the next semiconductor die is performed after a previous write operation on the previous semiconductor die is stopped or terminated, or may be transferred such that the next write operation on the next semiconductor die is started while the previous write operation on the previous semiconductor die continues.

Likewise, as write operation transfer conditions are successively satisfied, write operations may be sequentially transferred to the semiconductor die D23and the semiconductor die D24of the second memory package PKG2through the 2ndway Way2and the 3rdway Way3, respectively.

As shown inFIG. 4B, when a write operation switching condition is satisfied after a write operation is performed through the 1stway Way1, a next write operation may be performed on a semiconductor die in another package. This may be in accordance with the satisfaction of a package switching condition.

That is, the transfer of a write operation may be sequentially performed on other semiconductor dies in the same memory package until the package switching condition is satisfied, and when the package switching condition is satisfied, then a next write operation may be transferred to a semiconductor die in another memory package.

FIG. 3Bis a flowchart illustrating a method of operating a data storage device according to this embodiment.

Referring toFIGS. 3B, 4A, and 4B, it is determined whether a write operation transfer condition is satisfied after a write operation is performed on the semiconductor die D11through the 0thway Way0(Operation S130). If it is determined that the write operation transfer condition is not satisfied, the write operation on the semiconductor die D11is continued. On the other hand, if it is determined that the write operation transfer condition is satisfied, it is determined whether a package switching condition is satisfied (Operation S150). Here, the package switching condition is whether or not the number of semiconductor dies to which write operations have been successively transferred in a memory package is greater than or equal to a package switching reference value (e.g., where the package switching reference value is 2).

It may be understood by one of ordinary skill in the art that the package switching condition may be variously set as needed. For example, in some embodiments, when the number of memory packages corresponding to one channel is P (where P is 2), the package switching reference value may be defined as (N/P). In this case, since the number N of ways is 4 and the number P of memory packages is 2, the package switching reference value may be selected as 2. When the value of (N/P) is not an integer, another integer value closest to (N/P) may be selected as the package switching reference value. For example, the package switching reference value may be a selected integer from 1 to 8. The number P of memory packages may be any third integer from 2 to 64.

Since the number of semiconductor dies to which write operations are successively transferred in the first memory package PKG1is still 1, the package switching condition is not satisfied. Accordingly, a next write operation may be started on the next semiconductor die (e.g., the semiconductor die D12) in the current package (i.e., the first memory package PKG1) via the 1stway Way1to perform the next write operation on the next semiconductor die (Operation S174).

Subsequently, when the write operation transfer condition is satisfied again (Operation S130), it is again determined whether or not the package switching condition is satisfied (Operation S150). In this case, since the number of semiconductor dies to which write operations are successively transferred in the first memory package PKG1is 2, the package switching condition is satisfied.

Accordingly, a next write operation may be transferred to the semiconductor die D23of the next package (i.e., the second memory package PKG2) through the 2ndway Way2(Operation S172). AlthoughFIG. 4Bshows an example in which the next write operation is transferred to the semiconductor die D23, the next write operation may be transferred to any semiconductor die in the second memory package PKG2.

When the write operation transfer condition is satisfied while the write operation is performed on the semiconductor die D23(Operation130), the next write operation may be transferred to the next semiconductor die, that is, the semiconductor die D24through the 3rdway Way3.

In this case, since the number of the semiconductor dies to which write operations are successively transferred in the second memory package PKG2is equal to or greater than the package switching reference value (where the package switching reference value is 2), the package switching condition is satisfied. When the write operation transfer condition is satisfied while a write operation is performed on the semiconductor die D24, the package switching condition is also satisfied, and therefore, a next write operation through the 0thway Way0is transferred to a semiconductor die in the first memory package PKG1again. This will be described in detail with reference toFIGS. 3B, 5A and 5B.

Although an example in which a time interval between times t5and t4is greater than Δt is shown inFIG. 4A, the time interval between the times t5and t4may be less than Δt. Furthermore, although the time t5is shown to be after the time t4, the time t5may be earlier than the time t4or earlier than the time t3.

Referring toFIGS. 3B, 5A and 5B, when a write operation on the semiconductor die D11through the 0thway Way0ends at the time t5(seeFIG. 4A) and a write operation transfer condition for a next write operation of the semiconductor die D24is satisfied (seeFIG. 3B), the next write operation may be transferred to the semiconductor die D15. In addition, when a write operation on the semiconductor die D12through the 1stway Way1ends at time t6and a write operation transfer condition for a next write operation of the semiconductor die D15is satisfied, the next write operation may be transferred to the semiconductor die D16.

InFIG. 5B, write operations are sequentially transferred to the semiconductor die D15and the semiconductor die D16. Various methods may be used to determine to which semiconductor die in the first memory package PKG1write operations are transferred. In some embodiments, a semiconductor die (e.g., the semiconductor die D15) next to a semiconductor die (e.g., the semiconductor die D12) used in the most recent previous write operation for the first memory package PKG1may be preferentially used. Here, “next” may denote a physically adjacent location, and may denote the next in a certain order for the entire set of semiconductor dies in a memory package. Accordingly, a next write operation may be transferred to the semiconductor die D13or the semiconductor die D17instead of being transferred to the semiconductor die D15.

Furthermore, a semiconductor die to which a next write operation is transferred when a write operation transfer condition is satisfied while the write operation is performed on the semiconductor die D15may be the semiconductor die D16, or may also be any one of the semiconductor dies (e.g., the semiconductor dies D13, D14, and D16to D18) other than semiconductor dies (e.g., the semiconductor dies D11and D12) used for the most recent previous write operations on the first memory package PKG1. In other words, one (or more) of semiconductor dies that have not been used in the most recent previous write operations on the first memory package PKG1may be preferentially used for transfer of a next write operation following the write operation on the semiconductor die D15.

As described above, when a write operation is performed on the semiconductor die D15and the semiconductor die D16and a write operation transfer condition is satisfied, the transfer of a next write operation between packages is performed in a manner similar to that described with reference toFIGS. 4A and 4B. As a result, the next write operation may be transferred to a semiconductor die of the second memory package PKG2. A semiconductor die (e.g., the semiconductor die D27) next to a semiconductor die (e.g., the semiconductor die D24) used for the most recent previous write operation on the second memory package PKG2may be preferentially used. In addition, a semiconductor die to which a next write operation is transferred when a write operation transfer condition is satisfied while a previous write operation is performed on the semiconductor die D27may be the semiconductor die D28.

FIGS. 6 and 7are conceptual diagrams for additionally illustrating an operating method that may be performed subsequent to the method of operating a data storage device which has been described with reference toFIGS. 3B, 4A, 4B, 5A, and 5B.

Referring toFIG. 6, after the write operation ofFIG. 5B, write operations may be sequentially performed on the semiconductor die D13through the 0thway Way0and on the semiconductor die D14through the 1stway Way1. In addition, when a package switching condition is satisfied, write operations may be sequentially performed on the semiconductor die D25through the 2ndway Way2and on the semiconductor die D26through the 3rdway Way3.

Similarly, referring toFIG. 7, after the write operation ofFIG. 6, write operations may be sequentially performed on the semiconductor die D17through the 0thway Way0and on the semiconductor die D18through the 1stway Way1. In addition, when a package switching condition is satisfied, write operations may be sequentially performed on the semiconductor die D21through the 2ndway Way2and on the semiconductor die D22through the 3rdway Way3.

As can be understood fromFIGS. 4B, 5B, 6, and 7, write operations through the 0thway Way0and the 1stway Way1in the first memory package PKG1may be performed in the order of the semiconductor dies D11, D12, D15, D16, D13, D14, D17, and D18. Similarly, write operations through the 2ndway Way2and the 3rdway Way3in the second memory package PKG2may be performed in the order of the semiconductor dies D23, D24, D27, D28, D25, D26, D21, and D22. It will be understood by one of ordinary skill in the art that the order of performing the write operations described above may be changed.

In other words, since write operations are sequentially performed on the semiconductor dies D11, D12, . . . , and D18in the first memory package PKG1, there may be no other semiconductor die in which a write operation is performed more than twice as compared to any one of the semiconductor dies D11, D12, . . . , and D18in the first memory package PKG1. This is also true for the second memory package PKG2and there may be no other semiconductor die in which a write operation is performed more than twice as compared to any one of the semiconductor dies D21, D22, . . . , and D28.

Although the above description has been made for the 0thchannel CH0, the above description of the 0thchannel CH0may be similarly applied to the 1stchannel CH1to (M−1)thchannel CH(M−1).

FIG. 8is a conceptual diagram illustrating an example of implementing a data storage device10according to an embodiment of the inventive concept.

Referring toFIG. 8, a controller100and a data storage unit300may be mounted on a substrate11. Substrate11may be, for example, a printed circuit board (PCB) or a flexible PCB substrate.

A terminal12, which may be connected to a host, may be provided on one side of the substrate11. Terminal12may be configured to be connected in a manner conforming to an SATA standard, a PATA standard, or an SCSI standard. The SATA standard covers all STAT-related standards such as SATA-2, SATA-3, and external SATA (e-SATA) as well as SATA-1. The PATA standard covers all IDE-related standards such as integrated drive electronics (IDE) and enhanced-IDE (E-IDE).

Controller100may be electrically connected to memory packages through channels CH0, CH1, . . . , and CH(M−1). Although buffer memory200shown inFIG. 1is not shown inFIG. 8, buffer memory200may be mounted on substrate11with a connection relationship as shown inFIGS. 1 and 2.

A first memory package PKG1and a second memory package PKG2, connected to the channel CH0, may be mounted on the upper surface and the lower surface of substrate11, respectively. A third memory package PKG3and a fourth memory package PKG4, connected to the channel CH1, may be mounted on the upper surface and the lower surface of substrate11, respectively.

When write operations are concentrated on any one memory package connected to one channel (e.g., the channel CH0), heat generation is concentrated on the memory package and thus sufficient performance may not be obtained.

However, as described with reference toFIGS. 3A to 7, since write operations are performed by being distributed substantially equally to the first memory package PKG1and the second memory package PKG2, heat generated in the first memory package PKG1and heat generated in the second memory package PKG2may be distributed very uniformly. In other words, controller100may allow all packages belonging to one channel to always use the same number of semiconductor dies according to the control method described above, so that heat generated in the packages is evenly distributed to each package in the channel. Therefore, when a data storage device according to an embodiment of the inventive concept is used, sufficient performance may be obtained with relatively low heat generation.

In embodiments described above, M, which is the number of channels, may be a first integer of 1 to 16, and N, which is the number of ways of each channel, may be a second integer of 2 to 128. The number of semiconductor dies present in the data storage device10may be greater than M×N and less than 4096.

Although, inFIG. 8, the first memory package PKG1and the third memory package PKG3are shown as separate packages separated from each other, the first memory package PKG1and the third memory package PKG3may be arranged adjacent to each other side-by-side and be provided integrally in a single encapsulating resin. Likewise, the second memory package PKG2and the fourth memory package PKG4may be arranged adjacent to each other side-by-side and be provided integrally in a single encapsulating resin. Also, the first memory package PKG1and the third memory package PKG3may be combined into a single package, and the second memory package PKG2and the fourth memory package PKG4may be combined into a single package.

FIG. 9is a block diagram illustrating an example in which three or more memory packages, e.g., first to fourth memory packages PKG1, PKG2, PKG3, and PKG4, are connected to one channel CH0.FIGS. 4B, 5B, 6 and 7show an example in which two memory packages PKG1and PKG2are connected to one channel CH0.

Referring toFIG. 9, each of the first to fourth memory packages PKG1, PKG2, PKG3, and PKG4may include a plurality of semiconductor dies D11, D21, D31, and D41and may be configured to transmit and receive data through the channel CH0. Whether the first memory package PKG1, the second memory package PKG2, the third memory package PKG3, and the fourth memory package PKG4will transmit or receive data may be determined through a first chip enable pin CEP1, a second chip enable pin CEP2, a third chip enable pin CEP3, and a fourth chip enable pin CEP4, respectively.

The channel CH0may have N ways, and N, which is the number of ways, may be greater than the number of chip enable pins (where the number of chip enable pins is 4). When the number of memory packages corresponding to the channel CH0is P (where P is 4), a package switching reference value may be (N/4). When (N/4) is not an integer, the package switching reference value may be another integer closest to (N/4). Then, after write operations are performed through (N/4) semiconductor dies in each of the memory packages PKG1, PKG2, PKG3, and PKG4, the next write operation may be transferred between packages.

Specifically, write operations may be performed on the first memory package PKG1. In this case, after the write operations are sequentially performed on (N/4) semiconductor dies among a plurality of semiconductor dies in the first memory package PKG1, the next write operation may be transferred to the second memory package PKG2. Then, write operations may be sequentially performed on (N/4) semiconductor dies among a plurality of semiconductor dies in the second memory package PKG2. Then, the next write operations may be sequentially transferred to the third memory package PKG3and the fourth memory package PKG4in the same manner That is, the transfer of the write operations between packages may be sequentially performed on all of the memory packages PKG1, PKG2, PKG3, and PKG4connected to the channel CH0. Therefore, in the process in which the write operations are sequentially transferred to the first to fourth memory packages PKG1, PKG2, PKG3, and PKG4and then transferred to the first memory package PKG1again, there may be no missing memory package among the second through fourth memory packages PKG2, PKG3, and PKG4.

As described above, since a write operation is performed by being distributed substantially equally to the first to fourth memory packages PKG1, PKG2, PKG3, and PKG4, heat generated in the memory packages PKG1, PKG2, PKG3, and PKG4may be distributed evenly to the memory packages PKG1, PKG2, PKG3, and PKG4. Therefore, damage of a semiconductor device due to overheating resulting from concentration of write operations on any one memory package may be mitigated. In addition, when the temperature of a memory package excessively rises, the operation speed thereof is intentionally limited in order to prevent damage to a device including the memory package, and in this case, such performance deterioration may be prevented in advance and thus excellent data storage performance may be maintained.

FIGS. 10A to 10Dare conceptual diagrams illustrating a method of operating the data storage device10, according to an embodiment of the inventive concept. The conceptual diagrams ofFIGS. 10A to 10Dshow the operation of data storage unit300ofFIG. 2, by focusing on the channel CH0.FIG. 11is a graph showing a temperature profile of each memory package as a result of the operation.

Referring toFIGS. 10A and 11, write operations may be performed on the semiconductor die D11to the semiconductor die D14through the 0thway Way0to the 3rdway Way3, respectively. In particular, the write operations may be concentrated on the first memory package PKG1and the write operations may not be performed on the second memory package PKG2. When the write operations are concentrated on the first memory package PKG1for a predetermined time or more, heat generation in the first memory package PKG1may be excessive.

More specifically, since the write operations are concentrated on the first memory package PKG1, the temperature of the first memory package PKG1rises until time t11. Since the write operations are not performed on the second memory package PKG2, the temperature of the second memory package PKG2does not rise. When the temperature of the first memory package PKG1rises above a critical temperature Tc, the first memory package PKG1may be damaged. Also, as one of operations for lowering temperature to prevent damage to the data storage device10, the overall performance may be deteriorated by intentionally limiting an operation speed.

Referring toFIGS. 10B and 11, in order to prevent the excessive heat generation, write operations performed on the first memory package PKG1may be stopped at time t11before the temperature of the first memory package PKG1rises excessively. Then write operations may be performed on the semiconductor die D21to the semiconductor die D24of the second memory package PKG2through the 0thway Way0to the 3rdway Way3, respectively.

Then, the temperature of the second memory package PKG2rises, and the temperature of the first memory package PKG1is lowered. When the write operations continue for the second memory package PKG2for a predetermined time or more, heat generation in the second memory package PKG2may be excessive. If the temperature of the second memory package PKG2rises above the critical temperature Tc, the second memory package PKG2may be damaged similar to the problem as described above for the first memory package PKG1.

Referring toFIGS. 10C and 11, the write operations on the second memory package PKG2may be stopped at time t12to prevent excessive heat generation in the second memory package PKG2. The write operations may be performed on the semiconductor die D15to the semiconductor die D18of the first memory package PKG1through the 0thway Way0to the 3rdway Way3, respectively. Likewise, when the write operations are concentrated on the first memory package PKG1for a predetermined time or more, heat generation in the first memory package PKG1may be excessive.

Referring toFIG. 10DandFIG. 11, the write operations on the first memory package PKG1may be stopped to prevent excessive heat generation in the first memory package PKG1. The write operations may be performed on the semiconductor die D25to the semiconductor die D28of the second memory package PKG2through the 0thway Way0to the 3rdway Way3.

As described above, the switching of the write operations to the first memory package PKG1and the second memory package PKG2may be performed according to the package switching condition of time. In other words, after the write operations are performed on the first memory package PKG1for a reference time period Δt1, the write operations on the first memory package PKG1may be stopped and the next write operation may be performed on the second memory package PKG2. After the reference time period Δt1has elapsed, the write operations on the second memory package PKG2may be stopped and the next write operation may be performed on the first memory package PKG1again.

In other words, the switching of the write operation between the first memory package PKG1and the second memory package PKG2may be performed after every reference time period Δt1. The reference time period Δt1may be, for example, about 0.2 milliseconds (ms) to about 10 seconds. When the reference time period Δt1is too long, the temperature of a memory package may rise to the critical temperature Tc. On the contrary, when the reference time period Δt1is too short, the storage of data in data storage unit300may be inefficient due to too frequent transfer of the write operation between packages.

AlthoughFIG. 11shows an example in which the temperatures of the first memory package PKG1and the second memory package PKG2rise and fall with time, this temperature change may be exaggerated for clarity.

The reference time period Δt1may be set to be sufficiently less than the thermal time constant of the first memory package PKG1and/or the thermal time constant of the second memory package PKG2. The thermal time constant is a unique value according to thermal characteristics of each of the memory packages and may be defined as, in response to a temperature change, a time taken for the memory package to reach a temperature of 63.2% of the temperature change.

When the reference time period Δt1is set to be sufficiently less than the thermal time constant, for example, from about 0.2 ms to about 10 seconds, from about 0.5 ms to about 3 seconds, or from about 0.7 ms to about 0.5 seconds, it is possible to prevent heat generation from being concentrated on any one of the first and second memory packages PKG1and PKG2. This is because even if write operation through different ways is concentrated on any one of the first and second memory packages PKG1and PKG2, the ways are forcibly switched to other memory packages within a short time (e.g., after the reference time period Δt1has elapsed).

In other words, even if write operations through the 0thway Way0to the 3rdway Way3is concentrated on the first memory package PKG1(this case corresponds toFIGS. 10A and 10C), the write operation through the 0thway Way0to the 3rdway Way3may be switched to the second memory package PKG2after the reference time period Δt1that is sufficiently less than the thermal time constant has elapsed (seeFIGS. 10B and 10D). Therefore, a phenomenon in which excessive temperature rise occurs when the write operations are concentrated only on the first memory package PKG1may be prevented.

It is also possible to keep the temperatures of the first memory package PKG1and the second memory package PKG2substantially constant by sufficiently shortening the reference time period Δt1.

In the embodiment described with reference toFIGS. 10A to 10DandFIG. 11, the case where the package switching condition is time is exemplified. In some embodiments, the package switching condition may be a data size.

FIG. 12is a graph showing a temperature profile of each memory package when the package switching condition is a data size.

Referring toFIGS. 10A and 12, a write operation may be performed on the semiconductor die D11to the semiconductor die D14through the 0thway Way0to the 3rdway Way3, respectively. The temperature of the first memory package PKG1rises as described with reference toFIG. 11, and when the write operations are concentrated on the first memory package PKG1for a predetermined time or more, heat generation in the first memory package PKG1may be excessive.

In order to prevent such excessive heat generation, when data has been written to the first memory package PKG1up to a predetermined reference data size (ΔG), writing to the first memory package PKG1may be stopped at that point t21and writing to the second memory package PKG2may be started.

Referring toFIGS. 10B and 12, write operations can be performed on the semiconductor die D21to the semiconductor die D24of the second memory package PKG2through the 0thway Way0to the 3rdway Way3, respectively. The temperature of the second memory package PKG2rises as the write operations progress, as described with reference toFIG. 11, and when the writing of data having a size greater than the reference data size is concentrated on the second memory package PKG2, heat generation in the second memory package PKG2may be excessive.

In order to prevent this phenomenon, when data has been written to the second memory package PKG2up to the reference data size (ΔG), writing to the second memory package PKG2may be stopped at that point t22and writing to the first memory package PKG1may be started.

Referring toFIGS. 10C, 10D, and 12, write operations may be performed on the semiconductor die D15to the semiconductor die D18of the first memory package PKG1and the semiconductor die D25to the semiconductor die D28of the second memory package PKG2, similar to the case described with reference toFIG. 11. The write operations may be continued until data of the reference data size ΔG is written, and the transfer of the write operation between packages may be performed because a package switching condition is satisfied when data of the reference data size ΔG is written.

The reference data size ΔG that results in the package switching condition may be, for example, about 4 kilobytes (KB) to about 300 megabytes (MB). When the reference data size ΔG is too large, the temperature of a memory package may rise to the critical temperature Tc. On the other hand, when the reference data size ΔG is too small, the storage of data in data storage unit300may be inefficient due to too frequent transfer of the write operation between packages.

The data size ΔG may be appropriately set in consideration of the thermal time constant described above and a write speed (Gb/sec). For example, the reference data size ΔG may be a data size that is writable within a time that is sufficiently shorter than the thermal time constant.

When the reference data size ΔG is sufficiently small so that a time taken to write the data size ΔG is sufficiently shorter than the thermal time constant, for example, when the data size ΔG is about 4 KB to about 300 MB, about 4 KB to about 50 MB, or about 8 KB to 10 MB, it is possible to prevent heat generation from being concentrated on any one of the first and second memory packages PKG1or PKG2. This is because even if write operations through different ways are concentrated on any one of the first and second memory packages PKG1and PKG2, the ways are forcibly switched to other memory packages after a short time taken to write data having the reference data size ΔG has elapsed.

In other words, even if write operations through the 0thway Way0to the 3rdway Way3are concentrated on the first memory package PKG1(this case corresponds toFIGS. 10A and 10C), the write operations through the 0thway Way0to the 3rdway Way3may be switched to the second memory package PKG2after a short time (this time is sufficiently shorter than the thermal time constant) taken to write data having the data size ΔG has elapsed (seeFIGS. 10B and 10D). Therefore, a phenomenon in which excessive temperature rise occurs as the write operations are concentrated only on the first memory package PKG1may be prevented.

It is also possible to keep the temperatures of the first memory package PKG1and the second memory package PKG2substantially constant by setting the reference data size ΔG to be sufficiently small.

When the data storage device according to the embodiment of the inventive concept is used, a phenomenon in which heat generation is concentrated locally may be mitigated.

Damage to a semiconductor device may be reduced or prevented since the phenomenon in which heat generation is concentrated locally is mitigated.

In addition, since the frequency of application of the performance limitation due to temperature rise (e.g., reducing an operating speed) is reduced, it is possible to provide better data storage performance.

FIG. 13is a diagram illustrating a configuration of an electronic system2according to an embodiment of the inventive concept.

Referring toFIG. 13, the electronic system2according to the embodiment of the inventive concept may include a data storage device10, a modem600, a user interface800, and a microprocessor900, electrically connected to a bus. Modem600may include a baseband chipset or a baseband system-on-chip (SoC).

When electronic system2is applied to a mobile device, a battery700for supplying the operating voltage of electronic system2may additionally be provided. Although not shown inFIG. 13, electronic system2may be further provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like.

Data storage device10may include a controller100and a data storage unit300. Data storage device10shown inFIG. 13may be configured with the SSD shown inFIGS. 1, 2, and 8. However, this case is merely an example of configuring data storage device10, and data storage device10may be configured in various forms as well as with an SSD. For example, data storage device10may be configured with a memory card and/or a memory card system.

Controller100may be electrically connected to the microprocessor900and the data storage unit300. Controller100may access the data storage unit300in response to a request from microprocessor900. For example, the controller100may control read, write, and erase operations of data storage unit300. Controller100may provide an interface between microprocessor900and the data storage unit300. Controller100may drive firmware for controlling data storage unit300.

Controller100may include well known components such as an internal memory, a CPU, a host interface, and a memory interface, as shown inFIG. 2. Controller100may also include a buffer memory for temporarily storing data transmitted and received between controller100and data storage unit300and data transmitted and received between controller100and microprocessor900. The buffer memory may be provided outside controller100or may be provided inside controller100. The buffer memory and the internal memory may be configured with a random access memory such as DRAM or SRAM. The CPU may control all operations of controller100. The buffer memory and/or the internal memory may be used as an operation memory of the CPU.

The host interface may provide a protocol for performing data exchange between microprocessor900(which in some embodiments may be a host) and controller100. Since this has been described in detail with reference toFIG. 2, an additional description will be omitted.

Data storage unit300in data storage device10may be used as a main storage device for storing a large amount of data. In some embodiments, i-bit data (i is an integer equal to or greater than 1) to be processed or processed by microprocessor900may be stored in data storage unit300through SSD controller100. Data storage unit300may include a non-volatile memory that supports a plurality of channels and a plurality of ways. According to an exemplary embodiment, data storage unit300may include a flash memory, especially a NAND flash memory, among non-volatile memories.

The flash memory may include a memory cell array for storing data, a read and write circuit for writing and reading data to and from the memory cell array, an address decoder for decoding an address transmitted from the outside and transmitting the decoded address to the read and write circuit, and a control logic for controlling all operations of the flash memory.

In an exemplary embodiment, flash memory cells of the flash memory may be implemented using one of various cell structures having a charge storage layer. A cell structure having the charge storage layer may be formed by using a charge trap flash structure using a charge trap layer, a stack flash structure in which arrays are stacked in multiple layers, a flash structure without a source and a drain, a fin-type flash structure, and a vertical NAND (VNAND) structure in which a channel layer extends in the vertical direction and word lines extend in the horizontal direction. In addition, in an exemplary embodiment, the read and write circuit may include a page buffer circuit having a plurality of page buffers.

Although not shown inFIG. 13, data storage device10may additionally include an error correction block. The error correction block may detect and correct errors in data read from data storage unit300. As an example, the error correction block may be provided as a component of controller100. As another example, the error correction block may be provided as a component of data storage unit300.

Controller100and data storage unit300may be integrated into a single semiconductor device. In an exemplary embodiment, controller100and data storage unit300may be integrated into a single semiconductor device to form a memory card. For example, controller100and data storage unit300may be integrated into a single semiconductor device to form a personal computer memory card international association (PCMCIA) card, a compact flash (CF) card, a smart media card (SMC), a memory stick, a multimedia card (MMC, RS-MMC, or MMCmicro), an SD card (SD, miniSD, microSD, or SDHC), or a universal flash memory device (UFS).

As another example, controller100and data storage unit300may be integrated into a single semiconductor device to form a solid state drive (SSD) as shown inFIGS. 1, 2, and 8.

As another example, data storage device10may be applied to a computer, a portable computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital camera, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, and one of various electronic devices constituting a home network. Data storage device10may also be applied to one of various electronic devices constituting a computer network, and may be applied to one of various electronic devices constituting a telematics network. In addition, data storage device10may be applied to a radio frequency identification (RFID) device and one of various components (e.g., a semiconductor drive such as SSD, a memory card, etc.) constituting an electronic system.

Data storage unit300and/or data storage device10may be implemented in various types of packages. For example, data storage unit300and/or data storage device10may be implemented in a Package on Package (PoP), a Ball Grid Array (BGA), a Chip Scale Package (CSP), a Plastic Leaded Chip Carrier (PLCC), a Plastic Dual In-Line Package (PDIP), a Die in Waffle Pack, a Die in Wafer Form, a Chip On Board (COB), a Ceramic Dual In-Line Package (CERDIP), a Plastic Metric Quad Flat Pack (MQFP), a Thin Quad Flatpack (TQFP), a Small Outline (SOIC), a Shrink Small Outline Package (SSOP), a Thin Small Outline (TSOP), a Thin Quad Flatpack (TQFP), a System In Package (SIP), a Multi Chip Package (MCP), a Wafer-level Fabricated Package (WFP), a Wafer-Level Processed Stack Package (WSP), or the like.

The inventive concept may also be embodied as computer readable codes on a tangible computer readable recording medium. The computer readable recording medium is any data storage device that can store data which can be thereafter read by a computer system. Examples of the computer readable recording medium include read-only memory (ROM), random-access memory (RAM), CD-ROMs, flash memories, USB memories, magnetic tapes, floppy disks, hard disks, optical data storage devices, SSDs, etc. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.