Semiconductor device and manufacturing method thereof

A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and an invisible region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the visible region and the alignment mark is located in the invisible region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark.

CROSS REFERENCE TO RELATED APPLICATIONS

This Non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No(s). 201510019256.1 filed in People's Republic of China on Jan. 14, 2015, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

Field of Invention

Embodiments described herein relate generally to a semiconductor device and a manufacturing method thereof.

Related Art

A photo engraving process (PEP) is often applied to the process of manufacturing semiconductor. One photo engraving process generally comprises deposition, development, etching, and so on. A gate, a drain, a source, a channel, an etching stop layer, a passivation layer, a pixel electrode, or the like are generally formed by the photo engraving process in a process of manufacturing thin film transistor (TFT) substrate. However, the manufacturing process is complex and the issue of alignment tolerance is also difficult to be solved.

Generally, during the first photo engraving process, an alignment mark is disposed in an non-display region on a substrate at the same time (e.g. the alignment mark is formed while a gate is formed) so the photo mask can precisely form the required stack structure by aligning the alignment mark in the following photo engraving processes. However, after repeated etching steps, the alignment mark is easily etched away due to the excessively thin membrane of stack in the non-display region. Thus, the alignment can't be successfully retained in the following photo engraving processes.

Therefore, what is needed is to provide a semiconductor device and a manufacturing method thereof which can protect the alignment mark from etching for the alignment in the following processes.

SUMMARY OF THE INVENTION

An aspect of the disclosure is to provide a semiconductor device and a manufacturing method thereof which can prevent the alignment mark from etching in the following processes.

A method for manufacturing a semiconductor device according to the disclosure comprises the steps of: providing a transparent substrate having a display region and an non-display region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the display region and the alignment mark is located in the non-display region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark.

A method for manufacturing a semiconductor device according to the disclosure comprises the steps of: providing a transparent substrate having a display region and an non-display region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the display region and the alignment mark is located in the non-display region; forming a gate insulation layer to cover the gate and cover the alignment mark; and forming an oxide semiconductor layer on the gate insulation layer above the gate and the alignment mark.

In one embodiment, the method further comprises a step of forming an etching stop layer on the oxide semiconductor layer above the gate and the alignment mark.

In one embodiment, the step of forming the etching stop layer comprises: forming a to-be-etched layer to cover the gate and cover the alignment mark; forming a photoresist layer on the to-be-etched layer above the gate and the alignment mark; and removing the portion of the to-be-etched layer which is not shielded by the photoresist layer, and the remaining portion of the to-be-etched layer which is shielded by the photoresist layer is serving as a shield to form the etching stop layer.

In one embodiment, the method further comprises a step of forming a buffer layer on the oxide semiconductor layer above the gate and the alignment mark.

In one embodiment, the method further comprises the steps of: forming a source/drain; forming a protective layer to cover at least a part of the source/drain; and forming a conductive layer to be electrically connected to the source/drain.

In one embodiment, the protective layer extends to cover the alignment mark in the step of forming the protective layer.

A semiconductor device according to the disclosure comprises a transparent substrate, a gate, at least an alignment mark, a gate insulation layer, an oxide semiconductor layer, and an etching stop layer. The transparent substrate has a display region and an non-display region. The gate is formed on the transparent substrate and located in the display region. The alignment mark is formed on the transparent substrate and coplanar with the gate in the non-display region. The gate insulation layer covers the gate and the alignment mark. The oxide semiconductor layer is formed on the gate insulation layer above the gate. The etching stop layer is formed above the gate and the alignment mark.

A semiconductor device according to the disclosure comprises a transparent substrate, a gate, at least an alignment mark, a gate insulation layer, and an oxide semiconductor layer. The transparent substrate has a display region and an non-display region. The gate is formed on the transparent substrate and located in the display region. The alignment mark is formed on the transparent substrate and coplanar with the gate in the non-display region. The gate insulation layer covers the gate and the alignment mark. The oxide semiconductor layer is formed on the gate insulation layer above the gate and the alignment mark.

In one embodiment, the semiconductor device further comprises an etching stop layer formed on the oxide semiconductor layer above the gate and the alignment mark.

In one embodiment, the semiconductor device further comprises a protective layer covering the alignment mark.

In one embodiment, the semiconductor device further comprises a buffer layer formed on the oxide semiconductor layer above the gate and the alignment mark.

In one embodiment, the material of the gate insulation layer comprises silicon oxide, silicon nitride, silicon oxynitride, or polyimide (PI).

In one embodiment, the material of the oxide semiconductor layer comprises indium gallium zinc oxide (IGZO) or amorphous silicon (a-Si).

In one embodiment, the material of the conductive layer comprises indium tin oxide (ITO), indium zinc oxide (IZO), aluminum doped zinc oxide (AZO), fluorine doped tin oxide (FTO), gallium doped zinc oxide (GZO), or a combination thereof.

In summary, the semiconductor device and its manufacturing method according to the disclosure are to form the etching stop layer or the oxide semiconductor layer on the alignment mark. Therefore, the alignment mark will not be removed due to the etching process and alignment functionality can be retained in the following manufacturing processes.

DETAILED DESCRIPTION OF THE INVENTION

The embodiments of the invention will be apparent from the following detailed description, which proceeds with reference to the accompanying drawings, wherein the same references relate to the same elements. It is to be understood that the following disclosure provides different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate a relationship between various embodiments and/or configurations discussed.

FIG. 1Ais a flow chart of the steps of the method for manufacturing a semiconductor device according to the first embodiment.FIG. 1Bis a top view of the semiconductor device according to the first embodiment.FIG. 1Cis a sectional schematic diagram along the line A-A ofFIG. 1B. Referring toFIG. 1A,FIG. 1BandFIG. 1C, the semiconductor device1may be a thin film transistor (TFT) substrate, a display panel, a touch panel, a touch display panel, or an electronic device using this semiconductor device. A TFT substrate is taken for example in this embodiment.

The method for manufacturing the semiconductor device1according to the embodiment comprises the steps of: providing a transparent substrate having a display region and an non-display region (S110); forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the display region and the alignment mark is located in the non-display region (S120); forming a gate insulation layer to cover the gate and cover the alignment mark (S130); forming an oxide semiconductor layer on the gate insulation layer above the gate (S140); and forming an etching stop layer above the gate and the alignment mark (S150). In this embodiment, the semiconductor device1comprises a transparent substrate11, a gate12, at least an alignment mark13, a gate insulation layer14, an oxide semiconductor layer15, and an etching stop layer16.

In the step S120, the gate12is formed on the transparent substrate11and located in the region111. For example, a metal layer may be deposited on the transparent substrate11by sputtering, printing, or the like, and the metal layer is covered with a photoresist. Then, exposure, development, etching, and other processes are performed on the photoresist by using a photo mask to form the the gate12. The material of the gate12may comprise tantalum (Ta), neodymium (Nd), chromium (Cr), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), or their combination.

Moreover, the alignment mark13and the gate12are formed coplanarly on the transparent substrate11, and the alignment mark13is located in the non-display region112. The disposition of the alignment mark13contributes to the alignment of the photo mask in the following photo engraving process (PEP) of the semiconductor device1. Accordingly, the stack structure can precisely be formed on the transparent substrate11by the photo mask to reduce the tolerance of the manufacturing process. In the embodiment, the alignment mark13and the gate12use the same material, and they are formed on the the transparent substrate11by the same manufacturing process simultaneously. Furthermore, the shape of the alignment mark13is not limited and may be a cross, triangle, square, round shape, ellipse, or other geometric shapes. This embodiment is illustrated by taking two cross-shaped alignment marks13for example.

In the step S130, the gate insulation layer14covers the gate12and the alignment marks13. For example, the gate insulation layer14may be formed on the transparent substrate11by chemical vapor deposition (CVD) and cover the gate12and the alignment marks13. Moreover, the material of the gate insulation layer14may comprise silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), aluminum nitride (AlNx), or polyimide (PI).

In the step S140, the oxide semiconductor layer15is formed on the gate insulation layer14above the gate12. In detail, the oxide semiconductor layer15may comprise indium gallium zinc oxide (IGZO). A layer of indium gallium zinc oxide (IGZO) may be deposited on the gate insulation layer14by sputtering, coating, or the like, and the indium gallium zinc oxide (IGZO) is covered by a photoresist. Then, exposure, development, etching, and other processes are performed on the photoresist by using a photo mask to form an indium gallium zinc oxide (IGZO) layer (namely the oxide semiconductor layer15). Here, the oxide semiconductor layer15may serve as a channel region of the transistor.

In the step S150, the etching stop layer16is formed above the gate12and the alignment marks13. Referring toFIG. 1A,FIG. 1C, andFIGS. 2A to 2D,FIG. 2Ais a flow chart of the steps of forming the etching stop layer, andFIGS. 2B to 2Dare schematic diagrams showing the manufacturing process of the etching stop layer. In the embodiment, the etching stop layer16is formed by the following steps of: forming a to-be-etched layer EL to cover the gate12and cover the alignment marks13(step S151as shown inFIG. 2B); forming a photoresist layer PR on the to-be-etched layer EL above the gate12and the alignment marks13(step S152as shown inFIG. 2C); and removing the portion of the to-be-etched layer EL which is not shielded by the photoresist layer PR, and the remaining portion of the to-be-etched layer EL which is shielded by the photoresist layer PR is serving as a shield to form the etching stop layer16(step S153as shown inFIG. 2D). In the step S153, the portion of the to-be-etched layer EL which is not shielded by the photoresist layer PR is removed by dry etching, and the portion of the to-be-etched layer EL which is shielded by the photoresist layer PR is the etching stop layer16. Hence, the disposition of the etching stop layer16above the gate12contributes to the following formation of the source/drain. Finally, the step S154is to remove the photoresist layer PR (as shown inFIG. 1C). However, in some embodiments, the photoresist layer PR may be retained but not removed. Therefore, the step S154may be omitted.

While the etching stop layer16is formed, the photoresist layer PR is formed above the gate12and the alignment marks13simultaneously. Accordingly, the to-be-etched layer EL above the alignment marks13can be retained to form the etching stop layer16during dry etching. As a result, the gate insulation layer14and the etching stop layer16have the stack structure which can serve as protection for the alignment marks13. Therefore, the alignment marks13will not be removed due to the etching process, and alignment can be retained in the following manufacturing process of the source/drain.

FIG. 3Ais a flow chart of the steps of forming the source/drain of the semiconductor device, andFIG. 3Bis a sectional schematic diagram showing the semiconductor device provided with the source/drain according to the first embodiment. As shown inFIG. 3AandFIG. 3B, in the following manufacturing processes, the method may further comprise the steps of: forming a source/drain (S160); forming a protective layer to cover at least a part of the source/drain (S170); and forming a conductive layer to be electrically connected to the source/drain (S180). In this embodiment, the semiconductor device1further comprises a source/drain17, a protective layer18, and a conductive layer19.

In the step S160, the source/drain17is formed on the gate insulation layer14and connected to the oxide semiconductor layer15. Thus, a transistor is formed by the gate12, the oxide semiconductor layer15, and the source/drain17.

In the step S170, the material of the protective layer18is an insulation material which may comprise silicon oxide, silicon nitride, silicon oxynitride, or polyimide (PI) to avoid the electrical influence due to the source/drain17in contact with an external conductor. In the embodiment, the protective layer18has an opening communicating with the source/drain17. Moreover in the step S180, the conductive layer19is electrically connected to the source/drain17via this opening.

In the embodiment, the conductive layer19is a pixel electrode. Its material may comprise indium tin oxide (ITO), indium zinc oxide (IZO), aluminum doped zinc oxide (AZO), fluorine doped tin oxide (FTO), gallium doped zinc oxide (GZO), or a combination thereof.

Moreover, in the embodiment, the protective layer18extends to cover the alignment marks13. In other embodiments, the protective layer18may be only formed in the display region111but not cover the alignment marks13.

FIG. 4is a top view of the base material of the semiconductor device. Referring toFIG. 4, the implementation of manufacturing the above-mentioned semiconductor device1is to arrange numerous semiconductor devices1on one base material B. In short, numerous semiconductor devices1are manufactured simultaneously and then divided into numerous semiconductor devices1by cutting. For example, 9 semiconductor devices1are obtained by cutting along the dotted lines as shown inFIG. 4. One or more alignment marks M may also be disposed in the non-display region B1on the base material B to facilitate the alignment of the photo engraving process. The stack structure on the the alignment marks M may refer to the above embodiment.

FIG. 5Ais a flow chart of the steps of the method for manufacturing the semiconductor device according to the second embodiment, andFIG. 5Bis a sectional schematic diagram showing the semiconductor device according to the second embodiment. Referring toFIG. 5AandFIG. 5B, in this embodiment the method comprises the steps of: providing a transparent substrate having a display region and an non-display region (S210); forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the display region and the alignment mark is located in the non-display region (S220); forming a gate insulation layer to cover the gate and cover the alignment mark (S230); and forming an oxide semiconductor layer on the gate insulation layer above the gate and the alignment mark (S240). In the embodiment, the semiconductor device2comprises a transparent substrate21, a gate22, at least an alignment mark23, a gate insulation layer24, and an oxide semiconductor layer25.

In detail, in the step S240, the oxide semiconductor layer25may similarly comprise indium gallium zinc oxide (IGZO). A layer of indium gallium zinc oxide (IGZO) may be deposited on the gate insulation layer24by sputtering, coating, or the like, and the indium gallium zinc oxide (IGZO) is covered with a photoresist. Then, exposure, development, etching, and other processes are performed on the photoresist by using a photo mask to form an indium gallium zinc oxide (IGZO) layer (namely the oxide semiconductor layer25). Here, the oxide semiconductor layer25according to the embodiment are formed above not only the gate22but the alignment marks23. As a result, the gate insulation layer24and the oxide semiconductor layer25have the stack structure which can serve as protection for the alignment marks23. Therefore, the alignment marks23will not be removed due to the etching process, and alignment can be retained in the following manufacturing process of the source/drain.

Moreover, in some embodiments, the shape of the oxide semiconductor layer25above the alignment marks23may match the shape of the alignment marks23. For example, they may be crosses, triangles, squares, round shapes, ellipses, or other geometric shapes in the same shape and size to facilitate their utilities of alignment in the following manufacturing process.

The semiconductor device2may further comprise an etching stop layer which is formed above the gate22, and then the following manufacturing process of the source/drain may be performed to form the transistor and the pixel electrode. In some embodiments, the semiconductor device2further comprises a source/drain, a protective layer, and a conductive layer through the manufacturing process of the source/drain. Here, the protective layer covers the alignment marks23. Actually, the manufacturing process of the source/drain may refer to theFIG. 3AandFIG. 3B.

FIG. 6Ais a flow chart of the steps of the method for manufacturing the semiconductor device according to the third embodiment, andFIG. 6Bis a sectional schematic diagram showing the semiconductor device according to the third embodiment. Referring toFIG. 6AandFIG. 6B, the difference between this embodiment and the second embodiment is that the method further comprises the step of: forming an etching stop layer on the oxide semiconductor layer above the gate and the alignment mark (S310) after the step S240. In this embodiment, the semiconductor device3comprises a transparent substrate31, a gate32, at least an alignment mark33, a gate insulation layer34, an oxide semiconductor layer35, and an etching stop layer36.

In the step S310, for example, as shown inFIG. 2A, the to-be-etched layer is formed on the gate insulation layer34to cover the gate32and cover the alignment marks33. Then, a photoresist layer is formed on the to-be-etched layer above the gate32in the display region311and above the alignment marks33in the non-display region312. Finally, the portion of the to-be-etched layer which is not shielded by the photoresist layer is removed, and the remaining portion of the to-be-etched layer which is shielded by the photoresist layer is serving as a shield to form the etching stop layer36. Thus, the disposition of the gate insulation layer34, the oxide semiconductor layer35and the etching stop layer36above the alignment marks33may contribute to preventing the alignment marks33from being removed due to the etching process and alignment can be retained in the following manufacturing process of the source/drain.

Moreover, the semiconductor device3may further comprise a buffer layer. Referring toFIG. 7, it is a sectional schematic diagram showing the semiconductor device according to the fourth embodiment. In the embodiment, the buffer layer37is formed on the oxide semiconductor layer35above the gate32and the alignment marks33. For example, the buffer layer37may be an aluminum oxide (AlOx) film and its alloy. Moreover, some elements which can improve heat resistance may be added into the aluminum oxide (AlOx) film, and the element may comprise Nd, Y, Fe, Ti, V, Zr, Nb, Mo, Hf, Ta, Mg, Cr, Mn, Ru, Rh, Pd, Ir, Pt, La, Gd, Tb, Dy, Sr, Sm, Ge, Bi, or a combination thereof.

The semiconductor device3may further comprise a source/drain, a protective layer, or a conductive layer to form the transistor and the pixel electrode. Actually, the manufacturing process of the source/drain may refer toFIG. 3AandFIG. 3B.

In summary, the semiconductor device and its manufacturing method according to the disclosure are to form the etching stop layer or the oxide semiconductor layer on the alignment mark, so the alignment mark will not be removed due to the etching process, and its alignment can be retained in the following manufacturing processes.