CMOS buffer with reduced ground bounce

A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

FIELD OF THE INVENTION

The present invention relates to the field of integrated circuits, and, more particularly, to a CMOS buffer.

BACKGROUND OF THE INVENTION

In integrated circuits, output buffers are used for interfacing core logic with external devices. One prominent problem in output buffers is “ground bounce.” More particularly, one basic property of an inductor is that the change of current therethrough produces a voltage across the inductor, which is directly proportional to the rate of change of current through the inductor. This may be represented as:
dV=LdI/dT,
where dV is the voltage generated, L is the inductance, and dI/dT is the rate of change of the current.

Thus, it may be said that the voltage across the inductor bounces. When considered at the ground pin, this is referred to as ground bounce. Ground bounce occurs as a result of parasitic inductance of the integrated circuit and packaging interconnections. Ground bounce occurs when the pull down transistor switches from an off to an on state.

Referring toFIG. 1, when the pull down transistor N116is turned ON, the potential developed across the capacitor C122is coupled by the transistor N116to the inductor L120. As a result, a transient is generated across inductor L120. A sudden increase of current flows from the output terminal O112through the pull-down transistor N116and through the parasitic inductance L120to ground.

Due to the above noted properties of an inductor, the voltage at the source of the pull down transistor rises. This decreases the gate-source voltage of the pull down transistor. In the case where this rise in source voltage is very large, it can cause ringing, which is reflected in the output of other buffers which are connected to the same ground pin and whose outputs are stable at a low level. The worst case is when all of the buffers, except one whose output is stable at a low level, are connected between the same supply pins and switch from high to low, which may lead to false triggering if the ground bounce is not kept within certain limits. This, in turn, imposes a limit on the number of output buffers that can be connected to a single ground pin, thus increasing the number of ground pins on a chip.

Various techniques have been used to reduce ground bounce. For example, U.S. Pat. No. 5,124,579 discloses the use of a resistive device for delaying the turn-on time of the output transistors to limit the rate of increase of ground current. Yet, this method is limited in its ability to dynamically adjust to changing output conditions. Furthermore, the delays produced are manufacturing process dependent.

Another approach is disclosed in U.S. Pat. No. 5,148,056, in which feedback is taken from the output terminal of the buffer. However, this technique has poor sensitivity to the actual ground bounce, especially when it is produced by the switching of other buffers. Further, U.S. Pat. No. 5,604,453 teaches an approach which relies on the matching of the geometries of various individual devices rather than feedback. As a result, this approach is incapable of dynamically adjusting to changing output conditions. Mismatches arising out of process variations would also influence the effectiveness of this approach.

SUMMARY OF THE INVENTION

An object of the present invention is to overcome the above drawbacks and to provide a CMOS buffer with reduced ground bounce.

These and other objects, features, and advantages in accordance with the invention are provided by a CMOS buffer with reduced ground bounce which may include feedback means or a circuit for sensing the ground bounce voltage at a ground terminal. The feedback circuit may be connected to the input of a controlling means or control circuit for dynamically adjusting the rate of increase of the ground current in a manner that reduces the sensed ground bounce voltage to a level below a threshold while maintaining a desired speed of operation.

The feedback circuit may include an amplifier that amplifies the difference between the sensed output ground voltage and an internal reference ground voltage. The controlling circuit may include a slew-rate controlling circuit, for example. In particular, the slew-rate controlling circuit may dynamically adjust the gate voltage of the output NMOS transistor to limit the rate of increase of the current through the ground terminal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIG. 2, three output buffers BUFFER11, BUFFER22, and BUFFER33in accordance with the invention are connected between common supplies VDD and GND through package inductances on the VDD and GND pins illustratively represented as inductors L218and L220, respectively. The inputs to the buffers are IN11, IN22, and IN33, respectively, and the outputs are OP11, OP22, and OP33, respectively. Each buffer BUFFER11, BUFFER22, and BUFFER33has its input connected to its pull-down transistor through a respective control element CE11, CE22, and CE33.

One configuration of a control element is illustrated in FIG.3. Here, only BUFFER11is considered for clarity of illustration. Input IN11is connected to one end of the slew rate control element305, while it receives its other input302from an amplifier304. The amplifier304receives as its input301feedback from the inductor L220. The voltage at the input301varies dynamically according to ground bounce. This voltage is used to keep the bounce under control and at a selected level.

When the ground bounce at input301increases to a specific level, it increases the slew of the output signal on output303provided to the pull-down transistor N11. Further, when the ground bounce is not present, the input signal IN11passes through the control element CE11without any changes and reaches the gate of pull-down transistor N11.

An alternate control element configuration is illustrated in FIG.4. The output303of control element CE11is processed according to a given formula which depends upon the type of package and technology used.

A steady state condition will now be considered with reference toFIG. 2where the input signal IN11of the BUFFER11is low, the input signal IN22of the BUFFER22is high, and the input signal IN33of the BUFFER33is also high. The pull-up transistor P11is ON, P22is OFF, and P33is OFF. The pull-down transistor N11is OFF, N22is ON, and N33is ON. The output of control element CE11is low, as at this moment there is no bounce at the inductor L220. This pulls up the node OP11high and also charges the load connected thereto. As the pull-down transistors N22and N33are ON, OP22and OP33are pulled down and stable at a low level.

Now we will consider the case when the input IN11is switching from a low to high state. During this switching, as the bounce is produced in the inductor L220it is fed back to the control element CE11. After the feedback has reached a particular selected level, the control element CE11circuitry controls the output provided to the pull-down transistor N11by increasing the slew of the signal on the output303, thus regulating the current therethrough which decreases the ground bounce at L220. Due to this decrease in ground bounce, feedback magnitude also decreases and the input to the gate of the transistor N11rises faster (i.e., with decreased slew), which again increases ground bounce. This cycle is repeated until the voltage at IN11reaches its high state.

The above will be further understood with reference to the flow diagram of FIG.5. The selected level of feedback (which is low as compared to the maximum tolerable ground bounce) at which the control element circuitry becomes active is determined based upon the delay of the control element circuitry. This configuration decreases the sensitivity of the circuitry to process parameters, as well as different voltages and temperatures, because it mainly depends on the feedback from the package inductance. If process models are slow, the bounce at the inductor L220will be low and the circuit will be faster. Yet, if the process models are fast, the bounce at the inductor L220will be greater, and the circuit will be slower, thus trying to neutralize the effect of process conditions on propagation delays.

It will be appreciated by those skilled in the art that the circuitry explained above is for reducing ground bounce. It will also be appreciated that similar circuitry may be used for controlling VDDBUMP, bounce at the VDD pin, and the inductance L218in accordance with the present invention. “

A more detailed embodiment of an output buffer and control circuit according to the present invention will now be described with reference toFIGS. 6-8.FIG. 6illustrates a CMOS output buffer, including a pre-driver102, a pad driver circuit100, a control circuit101for controlling ground bounce and an AND gate A1. The output buffer also includes IO PAD103. One input of A1is connected to configuration bit CB while other input is connected to NIN3which is coming from pre driver102. Output driver100includes PMOS P1with it's drain connected to the output pad103and source connected to power supply VDD. Output driver100also includes NMOSs N1and N2with their drains connected to output pad103and their sources connected to C2. The NMOS transistors are sized in a binary-weighted sequence. C2is connected to ground GND via parasitic inductor L1. PIN1and NIN1are coming from predriver102and connected to the gates of transistor P1and N1respectively. NIN3is coming from predriver102which is connected to one of the inputs of AND gate A1. NIN2is gate voltage for N2coming from control circuit101.”

More specifically, the output buffer as shown inFIG. 7includes pad driver100, Pre-driver102, control circuit101, AND gate A1and pad103. Control circuit101includes NMOSs N3, N4, N5and inverter G1. The source of N4is connected to ground while it's drain is connected to NIN2. The gate of N4is connected to line FB. The output of inverter G1is connected to the gate of N3. The source of N3is connected to NIN2while it's drain is connected to line CC. Drain of N5is connected to node C2. Gate of N5is connected to VDD and its source is connected to line FB. The input of inverter G1is connected to line FB while it's output is connected to the gate of N3. Feedback is taken from node C2which is connected to line FB via N5. N5is used to protect the gates of G1and N4from any occasional high voltage noise at C2. N5will never allow a voltage greater than VDD−Vt(N5) to pass through it.

Vmtp is maximum tolerable peak voltage. This is the maximum amplitude of ground bounce pulse that can be tolerated for a particular pulse width. Vtrip(G1) is the trip point voltage of inverter G1. Depending on the current sinking capability required either N1is conducting or both N1and N2are conducting. This is decided by configuration bit CB. It is presumed that for lower sinking capability (CB=0) i.e when only N1is conducting, ground bounce remains in acceptable limits. With CB=0 line CC remains at 0V.

With only N1ON, voltage at node C2is low enough (lower than Vtrip(G1)) to keep the gate of N3at logic 1. This keeps NIN2at 0V and hence N2OFF. For higher sinking capability CB=1 Where both N1and N2are ON. In this case the current flowing through inductor L1is high which raises the voltage at C2above tolerable limit. The control circuit101controls the voltage at C2so that it always remains within tolerable limits. Considering a stable condition when output from pre driver102i.e NIN1, PIN1and NIN3are all 0V. With CB=1 and NIN3=0V line CC remains at 0V. NIN1is 0V which makes N1OFF. Node C2and line FB remains at 0V. The input to G1is 0V while its output which is connected to the gate of N3is at VDD. This makes N3ON and hence makes NIN20V. The gate of N4is connected to 0V which makes N4OFF. With PIN1=0V P1is ON, keeping PAD103at VDD. Now considering NIN1, PIN1and NIN3all makes a transition from logic low to high. This makes P1OFF. Sizing of Predriver is such that slew rate of voltage (dV/dt) at NIN3is much faster than NIN1. Sinking is faster as the control circuitry never allows ground bounce to exceed Vmtp. Also sinking capability of N1is such that if only N1is ON ground bounce never exceeds beyond maximum tolerable value Vmtp.

Now voltage at NIN3and NIN1starts increasing. Increase in voltage at NIN1turns ON N1. At the same time the voltage at NIN3also starts increasing and increases at a rate faster than NIN1. This makes line CC to go at logic 1. With N3ON the voltage at line CC is transmitted to NIN2. This makes N2ON. Now N1and N2both are ON to pull down PAD103. This increases the current flowing through L1. Because of this voltage at C2starts increasing the current flowing through inductor L1is not constant therefore the voltage at point C2is given by V(C2)=L1[di(t)/dt] i(t) is the current flowing through L1.

Depending on the maximum tolerable peak voltage (Vmtp) at C2the trip point of G1is adjusted. The threshold voltage of N4is less as compare to the trip point of G1. As mentioned earlier Vmtp will be defined for a particular noise pulse width. The size of N4is small in comparison to that of N3. As the voltage at C2approaches threshold voltage of N4, it starts conducting. N4tries to slow down the increase in voltage at NIN2. Now depending on the operating conditions and the type of models used two things can happen.

Firstly, under best operating conditions when both N1and N2starts conducting, the voltage at C2starts increasing. The trip point of G1is higher than that of threshold voltage of N4. Increase in the voltage at C2first of all turns N4ON. Now both N4and N3are ON. But the size of N4is much smaller than that of N3. Conducting N4slightly reduces the voltage slew rate (dv/dt) at NIN2. But still the slew rate is enough high and the voltage at C2is still increasing. As the voltage at C2reaches to the trip point of G1, the output of G1becomes zero which makes N3OFF. With N3OFF and N4ON the magnitude of voltage at NIN2starts decreasing. This will reduce the conductivity of N2and hence the voltage at C2also starts decreasing. Reduction in voltage at C2again trips G1which again turns ON N3and voltage at NIN2starts increasing. This will again increase current through inductor L1. If the voltage at C2again exceeds the trip point of G1, the above explained process is repeated again. “

FIG. 8shows the voltage waveforms at different nodes. NIN2starts increasing from 0V at time T0. As N2becomes ON ground bounce starts increasing. At time T1V(C2) crosses the threshold level of N4. This will reduce the slew rate of NIN2. Reduction in the slew rate of NIN2can be seen from time T1to T2. Even with the reduction in slew rate ground bounce (V(C2)) still increasing. At time (T2−dt) G1trips and makes N3OFF. At time T2voltage at line NIN2starts falling because of N4. This reduces the current flowing through L1because of which voltage at node C2starts decreasing. At time (T2+dt) G1again trips making N3ON. NIN2doesn't start increasing instantaneously as N3has some delay and also N4is still conducting to stop NIN2from increasing. At T3NIN2starts increasing which again results in increase in the ground bounce. But this time the magnitude of voltage at V(C2) remains well below Vtrip(G1). The control circuit is working on feedback principle so it never allows ground bounce to cross Vmtp,

Secondly, under worst operating conditions magnitude of voltage at C2is less than Vtrip(G1). The output of G1always remains VDD and hence N3always remains ON. During slow operating conditions its N4which slightly reduces the slew rate at NIN2. The above explained circuitry not only controls the ground bounce but it also tries to equalize delays under different operating conditions. Under fast operating conditions as the bounce approaches Vmtp, N3becomes OFF which controls the bounce from further increase. With N3OFF and N4ON, the voltage at NIN2actually starts falling as shown in FIG.8. This reduces the current flowing through L1because of which voltage at node C2starts decreasing. This makes N4less conducting. After a time 2dt N3again turns ON but voltage at NIN2starts increasing only after a delay of T3−(T2+dt) as shown inFIG. 8whereas under slow operating conditions N3is always ON and a slight reduction in the slew rate by N4is sufficient to control the bounce. Thus in best operating conditions the bounce is controlled by actually decreasing the voltage at NIN2whereas in worst operating conditions the bounce is controlled by slightly reducing the slew rate of voltage at NIN2.”