Semiconductor devices, and related control logic assemblies, control logic devices, electronic systems, and methods

A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.

TECHNICAL FIELD

Embodiments of the disclosure relate to the field of semiconductor device design and fabrication. More specifically, embodiments of the present disclosure relate to control logic devices including shared gate electrodes, to control logic assemblies and semiconductor devices including the control logic devices, to methods of forming the control logic devices, to methods of operating the semiconductor devices, and to electronic systems including the semiconductor devices.

BACKGROUND

Semiconductor device designers often desire to increase the level of integration or density of features within a semiconductor device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, semiconductor device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.

One example of a semiconductor device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many types of memory including, but not limited to, random-access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), Flash memory, and resistance variable memory. Non-limiting examples of resistance variable memory include resistive random access memory (ReRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin-torque-transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.

A typical memory cell of a memory device includes one access device, such as a transistor, and one memory storage structure, such as a capacitor. Modern applications for semiconductor devices can employ significant quantities of memory cells, arranged in memory arrays exhibiting rows and columns of the memory cells. The memory cells may be electrically accessed through digit lines (e.g., bit lines) and word lines (e.g., access lines) arranged along the rows and columns of the memory cells of the memory arrays. Memory arrays can be two-dimensional (2D) so as to exhibit a single deck (e.g., a single tier, a single level) of the memory cells, or can be three-dimensional (3D) so as to exhibit multiple decks (e.g., multiple levels, multiple tiers) of the memory cells.

Control logic devices within a base control logic structure underlying a memory array of a memory device have been used to control operations (e.g., access operations, read operations, write operations) on the memory cells of the memory device. An assembly of the control logic devices may be provided in electrical communication with the memory cells of the memory array by way of routing and interconnect structures. However, as the number of decks of a 3D memory array increases, electrically connecting the memory cells of the different decks of the 3D memory array to the assembly of control logic devices within the base control logic structure can create sizing and spacing complications associated with the increased quantities and dimensions of routing and interconnect structures required to facilitate the electrical connection. In addition, the quantities, dimensions, and arrangements of the different control logic devices employed within the base control logic structure can also undesirably impede reductions to the size of a memory device, increases to the storage density of the memory device, and/or reductions in fabrication costs.

It would, therefore, be desirable to have improved semiconductor devices, control logic assemblies, and control logic devices facilitating higher packing densities, as well as methods of forming the semiconductor devices, control logic assemblies, and control logic devices.

DETAILED DESCRIPTION

Semiconductor devices including stack structures having TFT control logic levels in decks thereof are described, as are CMOS devices for inclusion in one or more of the TFT control logic levels, methods of forming the CMOS devices, methods of operating the semiconductor devices, and electronic systems including the semiconductor devices. In some embodiments, a semiconductor device includes a base control logic structure, and a stack structure on or over the base control logic structure including multiple decks (e.g., tiers) each individually including a TFT control logic level, an access device level on or over the TFT control logic level, and a memory element level on or over the access device level. The TFT control logic level of each individual deck of the stack structure is in electrical communication with the access device level and the memory element level of the individual deck, as well as the base control logic structure of the semiconductor device. The TFT control logic level of each of the decks of the stack structure includes TFT control logic devices and circuitry for controlling different operations of the memory element level and the access device level associated therewith. The TFT control logic devices and circuitry included in the TFT control logic level of each of the decks of the stack structure are different than additional control logic devices and circuitry included in the base control logic structure of the semiconductor device. The additional control logic devices and circuitry included in the base control logic structure work in conjunction with the TFT control logic devices and circuitry included in the TFT control logic level of each of the decks of the stack structure to facilitate desired operations (e.g., access operations, read operations, write operations) of the semiconductor device. In addition, the TFT control logic devices included in the TFT control logic level of at least one deck of the stack structure include at least one CMOS device including one or more gate electrodes shared between transistors (e.g., vertical transistors, such as vertical P-type metal-oxide-semiconductor (PMOS) transistors, vertical N-type metal-oxide-semiconductor (NMOS) transistors) thereof. The devices, structures, systems, and methods of the disclosure may facilitate increased efficiency, performance, simplicity, and durability in semiconductor devices (e.g., 3D memory devices) that rely on high packing density.

The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art will understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a semiconductor device (e.g., a memory device). The semiconductor device structures described below do not form a complete semiconductor device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form the complete semiconductor device from the semiconductor device structures may be performed by conventional fabrication techniques. Also note, any drawings accompanying the application are for illustrative purposes only, and are thus not drawn to scale. Additionally, elements common between figures may retain the same numerical designation.

As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” are in reference to a major plane of a substrate (e.g., base material, base structure, base construction, etc.) in or on which one or more structures and/or features are formed and are not necessarily defined by earth's gravitational field. A “lateral” or “horizontal” direction is a direction that is substantially parallel to the major plane of the substrate, while a “longitudinal” or “vertical” direction is a direction that is substantially perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate.

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, at least 99.9% met, or even 100.0% met.

As used herein, the term “NMOS” transistor means and includes a so-called metal-oxide transistor having a P-type channel region. The gate of the NMOS transistor may comprise a conductive metal, another conductive material, such as polysilicon, or a combination thereof. As used herein, the term “PMOS” transistor means and includes a so-called metal-oxide transistor having an N-type channel region. The gate of the PMOS transistor may comprise a conductive metal, another conductive material, such as polysilicon, or a combination thereof. Accordingly, the gate structures of such transistors may include conductive materials that are not necessarily metals.

FIG. 1shows a simplified side elevation view of a semiconductor device100(e.g., a 3D memory device), in accordance with embodiments of the disclosure. As shown inFIG. 1, the semiconductor device100includes a base control logic structure102, and a stack structure103overlying the base control logic structure102. As described in further detail below, the stack structure103includes decks104(e.g., tiers) each individually including a thin film transistor (TFT) control logic level, an access device level over the TFT control logic level, a memory element level over the access device level, and interconnect structures extending between the TFT control logic level and each of the access device level and the memory element level. Each TFT control logic level of the decks104may individually include one or more control logic devices (e.g., CMOS devices) exhibiting gate electrodes shared between neighboring transistors (e.g., NMOS transistors, PMOS transistors) thereof, as also described in further detail below. The base control logic structure102is in electrical communication with one or more (e.g., each) of the decks104of the stack structure103by way of interconnect structures112extending between the base control logic structure102and one or more levels (e.g., the TFT control logic level) of the one or more decks104of the stack structure103.

The base control logic structure102may include devices and circuitry for controlling various operations of the stack structure103. The devices and circuitry included in the base control logic structure102may be selected relative to devices and circuitry included in the TFT control logic levels of the decks104of the stack structure103. The devices and circuitry included in the base control logic structure102may be different than the devices and circuitry included in the TFT control logic levels of the decks104of the stack structure103, and may be used and shared by different decks104of the stack structure103to facilitate desired operation of the stack structure103. By way of non-limiting example, the base control logic structure102may include one or more (e.g., each) of charge pumps (e.g., VCCPcharge pumps, VNEGWLcharge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuitry (e.g., ring oscillators), drain supply voltage (Vdd) regulators, and various chip/deck control circuitry. The devices and circuitry included in the base control logic structure102may employ different conventional CMOS devices (e.g., conventional CMOS inverters, conventional CMOS NAND gates, conventional CMOS transmission pass gates, etc.), which are not described in detail herein. In turn, as described in further detail below, the devices and circuitry included in the TFT control logic level of each of the decks104of the stack structure103may not be shared by different decks104of the stack structure103, and may be dedicated to effectuating and controlling various operations (e.g., access device level operations, and memory element level operations) of the deck104associated therewith not encompassed within the functions of the devices and circuitry included in the base control logic structure102.

With continued reference toFIG. 1, the stack structure103may include any desired number of the decks104. For clarity and ease of understanding of the drawings and related description,FIG. 1shows the stack structure103as including three (3) decks104. A first deck106may include a first TFT control logic level106A, a first access device level106B on or over the first TFT control logic level106A, a first memory element level106C on or over the first access device level106B, and first interconnect structures106D extending between and electrically coupling the first TFT control logic level106A to each of the first access device level106B and the first memory element level106C. A second deck108may overlie the first deck106and may include a second TFT control logic level108A, a second access device level108B on or over the second TFT control logic level108A, a second memory element level108C on or over the second access device level108B, and second interconnect structures108D extending between and electrically coupling the second TFT control logic level108A to each of the second access device level108B and the second memory element level108C. A third deck110may overlie the second deck108and may include a third TFT control logic level110A, a third access device level110B on or over the third TFT control logic level110A, a third memory element level110C on or over the third access device level110B, and third interconnect structures110D extending between and electrically coupling the third TFT control logic level110A to each of the third access device level110B and the third memory element level110C. In additional embodiments, the stack structure103includes a different number of decks104. For example, the stack structure103may include greater than three (3) decks104(e.g., greater than or equal to four (4) decks104, greater than or equal to eight (8) decks104, greater than or equal to sixteen (16) decks104, greater than or equal to thirty-two (32) decks104, greater than or equal to sixty-four (64) decks104), or may include less than three (3) decks104(e.g., two (2) decks104).

The memory element levels (e.g., the first memory element level106C, the second memory element level108C, the third memory element level110C) of the each of the decks104(e.g., the first deck106, the second deck108, the third deck110) of the stack structure103may each individually include an array of memory elements. The array may, for example, include rows of the memory elements extending in a first lateral direction, and columns of the memory elements extending in a second lateral direction perpendicular to the first lateral direction. In additional embodiments, the array may include a different arrangement of the memory elements, such as hexagonal close packed arrangement of the memory elements. The memory elements of the array may comprise RAM elements, ROM elements, DRAM elements, SDRAM elements, Flash memory elements, resistance variable memory elements, or another type of memory element. In some embodiments, the memory elements comprise DRAM elements. In additional embodiments, the memory elements comprise resistance variable memory elements. Non-limiting examples of resistance variable memory elements include ReRAM elements, conductive bridge RAM elements, MRAM elements, PCM memory elements, PCRAM elements, STTRAM elements, oxygen vacancy-based memory elements, and programmable conductor memory elements.

The access device levels (e.g., the first access device level106B, the second access device level108B, the third access device level110B) of the each of the decks104(e.g., the first deck106, the second deck108, the third deck110) of the stack structure103may each individually include an array of access devices (e.g., TFT access devices). The access devices of the access device level (e.g., the first access device level106B, the second access device level108B, the third access device level110B) of a given deck104(e.g., the first deck106, the second deck108, the third deck110) may be operatively associated with the memory elements of the memory element level (e.g., the first memory element level106C, the second memory element level108C, the third memory element level110C) of the given deck104. The quantity and lateral positioning of the access devices of the access device level of the given deck104may, for example, correspond to the quantity and lateral positioning of the memory elements of the memory element level of the given deck104. The access devices of the access device level may underlie (or overlie) and be in electrical communication with the memory elements of the memory element level. Together the access devices of the access device level and the memory elements of the memory element level operatively associated therewith may form memory cells for each of the decks104of the stack structure103. The access devices may, for example, each individually include a channel region between a pair of source/drain regions, and a gate configured to electrically connect the source/drain regions to one another through the channel region. The access devices may comprise planar access devices (e.g., planar TFT access devices) or vertical access devices (e.g., vertical TFT access devices). Planar access devices can be distinguished from vertical access devices based upon the direction of current flow between the source and drain regions thereof. Current flow between the source and drain regions of a vertical access device is primarily substantially orthogonal (e.g., perpendicular) to a primary (e.g., major) surface of a substrate or base (e.g., the base control logic structure102) thereunder, and current flow between source and drain regions of a planar access device is primarily parallel to the primary surface of the substrate or base thereunder. In additional embodiments, the access device levels (e.g., the first access device level106B, the second access device level108B, the third access device level110B) are omitted (e.g., absent) from the decks104(e.g., the first deck106, the second deck108, the third deck110) of the stack structure103. For example, in place of the access device levels separate from the memory element levels (e.g., the first memory element level106C, the second memory element level108C, the third memory element level110C), each of the decks104of the stack structure103may include a single (e.g., only one) level including memory elements and access devices.

The TFT control logic levels (e.g., the first TFT control logic level106A, the second TFT control logic level108A, the third TFT control logic level110A) of the each of the decks104(e.g., the first deck106, the second deck108, the third deck110) of the stack structure103may include devices and circuitry for controlling various operations of the memory element level (e.g., the first memory element level106C, the second memory element level108C, the third memory element level110C) and the access device level (e.g., the first access device level106B, the second access device level108B, the third access device level110B) (or of a single level including memory elements and access devices) of the deck104not encompassed (e.g., effectuated, carried out, covered) by the devices and circuitry of the base control logic structure102. By way of non-limiting example, the TFT control logic levels may each individually include one or more (e.g., each) of decoders (e.g., local deck decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), word line (WL) drivers, repair circuitry (e.g., column repair circuitry, row repair circuitry), I/O devices (e.g., local I/O devices), test devices, array multiplexers (MUX), error checking and correction (ECC) devices, and self-refresh/wear leveling devices. As described in further detail below, the devices and circuitry included in the TFT control logic levels may employ TFT CMOS devices (e.g., CMOS inverters, CMOS NAND gates, CMOS pass gates, etc.) including gate electrodes shared between transistors (e.g., PMOS transistors, NMOS transistors) thereof. The devices and circuitry of the TFT control logic level of each of the decks104may only be utilized to effectuate and control operations within a single (e.g., only one) deck104of the stack structure103(e.g., may not be shared between two or more of the decks104), or may be utilized to effectuate and control operations within multiple (e.g., more than one) decks104of the stack structure103(e.g., may be shared between two or more of the decks104). In addition, each of the TFT control logic levels (e.g., the first TFT control logic level106A, the second TFT control logic level108A, and the third TFT control logic level110A) of the stack structure103may exhibit substantially the same configuration (e.g., substantially the same components and component arrangements), or at least one of the TFT control logic levels of the stack structure103may exhibit a different configuration (e.g., different components and/or a different component arrangement) than at least one other of the TFT control logic levels.

Thus, a semiconductor device according to embodiments of the disclosure comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof.

FIG. 2is a block diagram of a configuration of a TFT control logic level200for use in one or more of the decks104(FIG. 1) of the stack structure103(FIG. 1) of the semiconductor device100shown inFIG. 1. The TFT control logic level200may include a variety of control logic devices and circuits that would otherwise be included in off-deck circuitry (e.g., circuitry not presented within the TFT control logic level200), such as circuitry within a base control logic structure (e.g., the base control logic structure102shown inFIG. 1). For example, as shown inFIG. 2, an assembly of control logic devices and circuits present within the TFT control logic level200may include one or more (e.g., each) of a local deck decoder202, multiplexers (MUX)204(illustrated inFIG. 2as a first MUX204a, second MUX204b, and a third MUX204c), a column decoder206, a row decoder208, sense amplifiers210, local I/O devices212, word line (WL) drivers214, a column repair device216, a row repair device218, a memory test device222, an ECC device220, and a self-refresh/wear leveling device224. One or more of the control logic devices and circuits may exhibit a gate electrode shared by neighboring vertical transistors thereof, as described in further detail below. The assembly of control logic devices and circuits present within the TFT control logic level200may be operatively associated with (e.g., in electrical communication with) off-deck devices236(e.g., a controller, a host, global I/O devices) located outside of the TFT control logic level200, such as within the base control logic structure102shown inFIG. 1. The off-deck devices236may send a variety signals to the TFT control logic level200, such as a deck enable signal226, a column address signal232, a row address signal230, a global clock signal234; and may also receive a variety of signals from the TFT control logic level200, such as a global data signal228. WhileFIG. 2depicts a particular configuration of the TFT control logic level200, one of ordinary skill in the art will appreciate that different control logic assembly configurations, including different control logic devices and circuits and/or different arrangements of control logic devices and circuits, are known in the art which may be adapted to be employed in embodiments of the disclosure.FIG. 2illustrates just one non-limiting example of the TFT control logic level200.

Thus, in accordance with embodiments of the disclosure, a method of operating a semiconductor device comprises controlling functions of a stack structure having multiple decks each comprising memory cells using control logic levels of the multiple decks. The control logic levels each comprise at least one control logic device exhibiting a gate electrode shared by neighboring vertical transistors thereof. Additional functions of the stack structure are controlled using a base control logic structure in electrical communication with the control logic levels of the stack structure.

As shown inFIG. 2, one or more off-deck devices236located outside of the TFT control logic level200(e.g., in the base control logic structure102shown inFIG. 1) may be configured and operated to convey signals (e.g., a deck enable signal226, a row address signal230, a column address signal232) to different devices of the TFT control logic level200. For example, the off-deck devices236may send a deck enable signal226to the local deck decoder202, which may decode the deck enable signal226and activate one or more of the MUX204(e.g., the first MUX204a, the second MUX204b, and/or the third MUX204c) of the TFT control logic level200. As described in further detail below, when activated, the MUX204may individually be configured and operated to select one of several input signals and then forward the selected input into a single line.

The first MUX204a(e.g., a row MUX) of the TFT control logic level200may be in electrical communication with the local deck decoder202and the row decoder208of the TFT control logic level200. The first MUX204amay be activated by signal(s) from the local deck decoder202, and may be configured and operated to selectively forward at least one row address signal230from the off-deck devices236to the row decoder208. The row decoder208may be configured and operated to select particular word lines of a deck (e.g., one of the first deck106, the second deck108, and the third deck110shown inFIG. 1) including the TFT control logic level200based on the row address signal230received thereby.

With continued reference toFIG. 2, the row repair device218of the TFT control logic level200may be in electrical communication with the row decoder208, and may be configured and operated to substitute a defective row of memory elements of a memory element array of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with (e.g., within the same deck104shown inFIG. 1) the TFT control logic level200for a spare, non-defective row of memory elements of the memory element array of the memory element level. The row repair device218may transform a row address signal230directed to the row decoder208(e.g., from the first MUX204a) identifying the defective row of memory elements into another row address signal identifying the spare, non-defective row of memory elements. Defective rows (and columns) of memory elements may, for example, be determined using the memory test device222of the TFT control logic level200, as described in further detail below.

The WL drivers214of the TFT control logic level200may be in electrical communication with the row decoder208, and may be configured and operated to activate word lines of a deck (e.g., one of the first deck106, the second deck108, and the third deck110shown inFIG. 1) including the TFT control logic level200based on word line selection commands received from the row decoder208. The memory elements of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with the TFT control logic level200may be accessed by way of access devices of an access device level (e.g., one of the access device levels106B,108B,110B shown inFIG. 1) operatively associated with the TFT control logic level200for reading or programming by voltages placed on the word lines using the WL drivers214.

The self-refresh/wear leveling device224of the TFT control logic level200may be in electrical communication with the row decoder208, and may be configured and operated to periodically recharge the data stored in memory elements of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with (e.g., within the same deck104shown inFIG. 1) the TFT control logic level200. During a self-refresh/wear leveling operation, the self-refresh/wear leveling device224may be activated in response to an external command signal, and may generate different row address signals that may be forwarded to the row decoder208. The row decoder208may then select particular word lines of a deck (e.g., one of the first deck106, the second deck108, and the third deck110shown inFIG. 1) including the TFT control logic level200based on the different row address signals received from the self-refresh/wear leveling device224. The row decoder208may then communicate with the WL drivers214to activate the selected word lines, and charges accumulated in capacitors of memory elements operatively associated with the selected word lines may then be amplified by a sense amplifier and then stored in the capacitors again.

Still referring toFIG. 2, the second MUX204b(e.g., a column MUX) of the TFT control logic level200may be in electrical communication with the local deck decoder202and the column decoder206of the TFT control logic level200. The second MUX204bmay be activated by signal(s) from the local deck decoder202, and may be configured and operated to selectively forward at least one column address signal232from the off-deck devices236to the column decoder206. The column decoder206may be configured and operated to select particular digit lines (e.g., bit lines) of a deck (e.g., one of the first deck106, the second deck108, and the third deck110shown inFIG. 1) including the TFT control logic level200based on the column address selection signal received thereby.

The column repair device216of the TFT control logic level200may be in electrical communication with the column decoder206, and may be configured and operated to substitute a defective column of memory elements of a memory element array of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with (e.g., within the same deck104shown inFIG. 1) the TFT control logic level200for a spare, non-defective column of memory elements of the memory element array of the memory element level. The column repair device216may transform a column address signal232directed to the column decoder206(e.g., from the second MUX204b) identifying the defective column of memory elements into another column address signal identifying the spare, non-defective column of memory elements. As previously discussed, defective columns (and rows) of memory elements may, for example, be determined using the memory test device222of the TFT control logic level200, as described in further detail below.

The ECC device220of the TFT control logic level200may be configured and operated to generate an ECC code (also known as “check bits”). The ECC code may correspond to a particular data value, and may be stored along with the data value in a memory element of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with (e.g., within the same deck104shown inFIG. 1) the TFT control logic level200. When the data value is read back from the memory element, another ECC code is generated and compared with the previously-generated ECC code to access the memory element. If non-zero, the difference in the previously-generated ECC code and the newly-generated ECC code indicates that an error has occurred. If an error condition is detected, the ECC device220may then be utilized to correct the erroneous data.

The memory test device222of the TFT control logic level200may be configured and operated to identify defective (e.g., faulty) memory elements of a memory element array of a memory element level (e.g., one of the memory element levels106C,108C,110C shown inFIG. 1) operatively associated with (e.g., within the same deck104shown inFIG. 1) the TFT control logic level200. The memory test device222may attempt to access and write test data to memory elements at different addresses (e.g., different column addresses, different row addresses) within the memory element array. The memory test device222may then attempt to read data stored at the memory elements, and compare the read data to the test data expected at the memory elements. If the read data is different than the expected test data, the memory test device222may identify the memory elements as defective. The defective memory elements (e.g., defective rows of memory elements, defective columns of memory elements) identified by the memory test device222may then be acted upon and/or avoided by other components (e.g., the row repair device218, the column repair device216) of the TFT control logic level200.

With continued reference toFIG. 2, the local I/O devices212of the TFT control logic level200may be configured and operated to receive data from digit lines selected by the column decoder206during read operations, and to output data to digit lines selected by the column decoder206during write operations. As shown inFIG. 2, the local I/O devices212may include sense amplifiers210configured and operated to receive digit line inputs from the digit lines selected by the column decoder206and to generate digital data values during read operations. During write operations, the local I/O devices212may program data into memory elements of a memory element level operatively associated with the TFT control logic level200by placing proper voltages on the digit lines selected by the column decoder206. For binary operation, one voltage level is typically placed on a digit line to represent a binary “1” and another voltage level to represent a binary “0”.

The third MUX204cof the TFT control logic level200may be in electrical communication with the local I/O devices212and the local deck decoder202. The third MUX204cmay be activated by signal(s) received from the local deck decoder202, and may be configured and operated to receive digital data values generated by the local I/O devices212and to generate a global data signal228therefrom. The global data signal228may be forwarded to one or more off-deck devices236(e.g., a controller).

In accordance with embodiments of the disclosure, one or more of the components (e.g., one or more of the local deck decoder202, the MUX204(the first MUX204a, the second MUX204b, the third MUX204c), the column decoder206, the row decoder208, the sense amplifiers210, the local I/O devices212, the WL drivers214, the column repair device216, the row repair device218, the ECC device220, the memory test device222, the self-refresh/wear leveling device224) of the TFT control logic level200may employ one or more TFT CMOS devices exhibiting gate electrodes shared between neighboring vertical transistors (e.g., vertical NMOS transistors, vertical PMOS transistors) thereof. Accordingly, one or more components of at least one of the TFT control logic levels (e.g., the first TFT control logic level106A, the second TFT control logic level108A, the third TFT control logic level110A) of one or more of the decks104(e.g., the first deck106, the second deck108, the third deck110) of the stack structure103of the semiconductor device100previously described with reference toFIG. 1may include one or more TFT CMOS devices exhibiting gates shared between neighboring vertical transistors thereof. Non-limiting examples of such TFT CMOS devices are described in further detail below with reference toFIGS. 3 through 9B.

Thus, a control logic assembly according to embodiments of the disclosure comprises control logic devices selected from the group comprising decoders, sense amplifiers, word line drivers, repair devices, memory test devices, multiplexers, error checking and correction devices, and self-refresh/wear leveling devices. At least one of the control logic devices comprises at least one device exhibiting one or more gate electrodes is shared by neighboring vertical transistors thereof.

FIG. 3shows a simplified cross-sectional view of a CMOS inverter300, in accordance with embodiments of the disclosure. The CMOS inverter300includes a CMOS circuit302comprising a vertical NMOS transistor304and a vertical PMOS transistor306. The vertical NMOS transistor304includes a first semiconductive pillar308including an N-type source region308A, an N-type drain region308C, and a P-type channel region308B vertically between the N-type source region308A and the N-type drain region308C. The vertical PMOS transistor306includes a second semiconductive pillar310including a P-type source region310A, a P-type drain region310C, and an N-type channel region310B vertically between the P-type source region310A and the P-type drain region310C. The vertical NMOS transistor304and the vertical PMOS transistor306of the CMOS circuit302further include gate electrodes312, including a first gate electrode312A shared by the vertical NMOS transistor304and the vertical PMOS transistor306, and second gate electrodes312B not shared by the vertical NMOS transistor304and the vertical PMOS transistor306. The CMOS inverter300also includes a ground (GND) structure314connected to the N-type source region308A of the vertical NMOS transistor304; a supply voltage (Vcc) structure316connected to the P-type source region310A of vertical PMOS transistor306; an output structure318connected to the N-type drain region308C of the vertical NMOS transistor304and the P-type drain region310C of the vertical PMOS transistor306; and an input structure connected to each of the gate electrodes312(e.g., the first gate electrode312A and the second gate electrodes312B).

As shown inFIG. 3, the first gate electrode312A may be disposed laterally (e.g., horizontally) between the P-type channel region308B of the vertical NMOS transistor304and the N-type channel region310B of the vertical PMOS transistor306. The first gate electrode312A may be the only (e.g., sole) gate electrode laterally disposed between the P-type channel region308B of the vertical NMOS transistor304and the N-type channel region310B of the vertical PMOS transistor306, such that the first gate electrode312A is shared between the vertical NMOS transistor304and the vertical PMOS transistor306. Sharing the first gate electrode312A between the vertical NMOS transistor304and the vertical PMOS transistor306may improve one or more of semiconductor device scaling, electrical coupling effects, shorts margins, short channel effects, floating body effects, and cross talk as compared to conventional configurations including multiple, non-shared gate electrodes between neighboring vertical NMOS and PMOS transistors.

With continued reference toFIG. 3, the vertical NMOS transistor304may include one of the second gate electrodes312B laterally adjacent a side of the P-type channel region308B thereof opposing another side laterally adjacent the first gate electrode312A; and the vertical PMOS transistor306may include another of the second gate electrodes312B laterally adjacent a side of the N-type channel region310B opposing another side laterally adjacent the first gate electrode312A. The second gate electrodes312B may be unshared by the vertical NMOS transistor304and the vertical PMOS transistor306. Each of the vertical NMOS transistor304and the vertical PMOS transistor306may be considered to be “double-gated” in that two of the gate electrodes312(e.g., the first gate electrode312A, and one of the second gate electrodes312B) are disposed laterally adjacent opposing sides of the P-type channel region308B of the vertical NMOS transistor304; and two other of the gate electrodes312(e.g., the first gate electrode312A, and another of the second gate electrodes312B) are disposed laterally adjacent opposing sides of the N-type channel region310B of the vertical PMOS transistor306.

The gate electrodes312, including the first gate electrode312A and the second gate electrodes312B, may each individually be formed of and include electrically conductive material including, but not limited to, a metal (e.g., tungsten, titanium, nickel, platinum, gold), a metal alloy, a metal-containing material (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), a conductively-doped semiconductor material (e.g., conductively-doped silicon, conductively-doped germanium, conductively-doped silicon germanium, etc.), or combinations thereof. By way of non-limiting example, the gate electrodes312may each individually comprise at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), elemental titanium (Ti), elemental platinum (Pt), elemental rhodium (Rh), elemental aluminum (Al), elemental copper (Cu), elemental iridium (Ir), iridium oxide (IrOx), elemental ruthenium (Ru), ruthenium oxide (RuOx), alloys thereof, or combinations thereof. In some embodiments, the gate electrodes312are formed of TiN.

The P-type channel region308B of the vertical NMOS transistor304may be formed of and include at least one P-type conductivity material. The P-type conductivity material may, for example, comprise polysilicon doped with at least one P-type dopant (e.g., boron ions). In addition, the N-type source region308A and the N-type drain region308C of the vertical NMOS transistor304may each individually be formed of and include at least one N-type conductivity material. The N-type conductivity material may, for example, comprise polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorous ions, antimony ions). The first semiconductive pillar308including the N-type source region308A, the P-type channel region308B, and the N-type drain region308C may exhibit any desired dimensions (e.g., channel width, channel thickness, channel length) and shape (e.g., a rectangular column shape, a cylindrical column shape, a combination thereof). By way of non-limiting example, a channel thickness (laterally extending in the X-direction) of the first semiconductive pillar308may be within a range of from about 10 nanometers (nm) to about 50 nm, a channel width (laterally extending perpendicular to the channel thickness) of the first semiconductive pillar308may be within a range of from 20 nm to about 200 nm, and a channel length (vertically extending in the Z-direction) of the first semiconductive pillar308may within a range of from about 50 nm to about 200 nm.

The N-type channel region310B of the vertical PMOS transistor306may be formed of and include at least one N-type conductivity material. The N-type conductivity material may, for example, comprise polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorous ions, antimony ions). In addition, the P-type source region310A and the P-type drain region310C of the vertical PMOS transistor306may each individually be formed of and include at least one P-type conductivity material. The P-type conductivity material may, for example, comprise polysilicon doped with at least one P-type dopant (e.g., boron ions). The second semiconductive pillar310including the P-type source region310A, the N-type channel region310B, and the P-type drain region310C may exhibit any desired dimensions (e.g., width, length, height) and shape (e.g., a rectangular column shape, a cylindrical column shape, a combination thereof). The second semiconductive pillar310including the P-type source region310A, the N-type channel region310B, and the P-type drain region310C may exhibit any desired dimensions (e.g., channel width, channel thickness, channel length) and shape (e.g., a rectangular column shape, a cylindrical column shape, a combination thereof). By way of non-limiting example, a channel thickness (laterally extending in the X-direction) of the second semiconductive pillar310may be within a range of from about 10 nanometers (nm) to about 50 nm, a channel width (laterally extending perpendicular to the channel thickness) of the second semiconductive pillar310may be within a range of from 20 nm to about 200 nm, and a channel length (vertically extending in the Z-direction) of the second semiconductive pillar310may within a range of from about 50 nm to about 200 nm. The dimensions of the second semiconductive pillar310may be substantially the same as or different than the dimensions of the first semiconductive pillar308.

The GND structure314, the Vccstructure316, the output structure318, and the input structure of the CMOS inverter300may exhibit conventional configurations (e.g., conventional dimensions, conventional shapes, conventional conductive material compositions, conventional material distributions, conventional orientations, conventional arrangements), which are not described in detail herein.

FIGS. 4A through 9Bshow simplified cross-sectional (e.g.,FIGS. 4A, 5A, 6A, 7A, 8A, and 9A) and plan (e.g.,FIGS. 4B, 5B, 5C, 6B, 6C, 7B, 7C, 8B, and 9B) views of additional TFT CMOS devices according to embodiments of the disclosure that may be included in TFT control logic levels (e.g., the TFT control logic level200shown inFIG. 2; one or more of the first TFT control logic level106A, the second TFT control logic level108A, and the third TFT control logic level110A shown inFIG. 1) of the disclosure. ThroughoutFIGS. 4A through 9Band the written description associated therewith, functionally similar features (e.g., structures) are referred to with similar reference numerals incremented by 100. To avoid repetition, not all features shown inFIGS. 4A through 9Bare described in detail herein. Rather, unless described otherwise below, throughoutFIGS. 4A through 9B(and the written description associated therewith), a feature designated by a reference numeral that is a 100 increment of the reference numeral of a previously-described feature (whether the previously-described feature is first described before the present paragraph, or is first described after the present paragraph) will be understood to be substantially similar to the previously-described feature.

FIG. 4Ashows a simplified cross-sectional view of a two-input NAND gate400, in accordance with embodiments of the disclosure. The two-input NAND gate400includes a CMOS circuit402, an additional CMOS circuit422, a GND structure414, a Vccstructure416, an interconnect structure420, an output structure418, an input structure434(seeFIG. 4B), and an additional input structure436(seeFIG. 4B).FIG. 4Bshows a plan view of the two-input NAND gate400shown inFIG. 4A.

As shown inFIG. 4A, the CMOS circuit402of the two-input NAND gate400includes a vertical NMOS transistor404and a vertical PMOS transistor406. The vertical NMOS transistor404includes a first semiconductive pillar408including an N-type source region408A, an N-type drain region408C, and a P-type channel region408B vertically between the N-type source region408A and the N-type drain region408C. The vertical PMOS transistor406includes a second semiconductive pillar410including a P-type source region410A, a P-type drain region410C, and an N-type channel region410B vertically between the P-type source region410A and the P-type drain region410C. The vertical NMOS transistor404and the vertical PMOS transistor406further include gate electrodes412, including a first gate electrode412A shared by the vertical NMOS transistor404and the vertical PMOS transistor406, and second gate electrodes412B not shared by the vertical NMOS transistor404and the vertical PMOS transistor406. The first gate electrode412A may be disposed laterally (e.g., horizontally) between the P-type channel region408B of the vertical NMOS transistor404and the N-type channel region410B of the vertical PMOS transistor406. The first gate electrode412A may be the only (e.g., sole) gate electrode laterally disposed between the P-type channel region408B of the vertical NMOS transistor404and the N-type channel region410B of the vertical PMOS transistor406, such that the first gate electrode412A is shared between the vertical NMOS transistor404and the vertical PMOS transistor406. In addition, the vertical NMOS transistor404may include one of the second gate electrodes412B laterally adjacent a side of the P-type channel region408B thereof opposing another side laterally adjacent the first gate electrode412A; and the vertical PMOS transistor406may include another of the second gate electrodes412B laterally adjacent a side of the N-type channel region410B opposing another side laterally adjacent the first gate electrode412A. The second gate electrodes412B may be unshared by the vertical NMOS transistor404and the vertical PMOS transistor406of the CMOS circuit402.

The additional CMOS circuit422includes an additional vertical NMOS transistor424and an additional vertical PMOS transistor426. The additional vertical NMOS transistor424includes a first additional semiconductive structure428including an additional N-type source region428A, an additional N-type drain region428C, and an additional P-type channel region428B vertically between the additional N-type source region428A and the additional N-type drain region428C. The additional vertical PMOS transistor426includes a second additional semiconductive structure430including an additional P-type source region430A, an additional P-type drain region430C, and an additional N-type channel region430B vertically between the additional P-type source region430A and the additional P-type drain region430C. The additional vertical NMOS transistor424and the additional vertical PMOS transistor426further include additional gate electrodes432, including a first additional gate electrode432A shared by the additional vertical NMOS transistor424and the additional vertical PMOS transistor426, and second additional gate electrodes432B not shared by the additional vertical NMOS transistor424and the additional vertical PMOS transistor426. The first additional gate electrode432A may be disposed laterally (e.g., horizontally) between the additional P-type channel region428B of the additional vertical NMOS transistor424and the additional N-type channel region430B of the additional vertical PMOS transistor426. The first additional gate electrode432A may be the only (e.g., sole) gate electrode laterally disposed between the additional P-type channel region428B of the additional vertical NMOS transistor424and the additional N-type channel region430B of the additional vertical PMOS transistor426, such that the first additional gate electrode432A is shared between the additional vertical NMOS transistor424and the additional vertical PMOS transistor426. In addition, the additional vertical NMOS transistor424may include one of the second additional gate electrodes432B laterally adjacent a side of the additional P-type channel region428B thereof opposing another side laterally adjacent the first additional gate electrode432A; and the additional vertical PMOS transistor426may include another of the second additional gate electrodes432B laterally adjacent a side of the additional N-type channel region430B opposing another side laterally adjacent the first additional gate electrode432A. The second additional gate electrodes432B may be unshared by the additional vertical NMOS transistor424and the additional vertical PMOS transistor426of the additional CMOS circuit422.

With continued reference toFIG. 4A, regarding the additional components of the two-input NAND gate400, the GND structure414may be connected to the N-type source region408A of the vertical NMOS transistor404; the Vccstructure416may be connected to each of the P-type source region410A of the vertical PMOS transistor406and the additional P-type source region430A of the additional vertical PMOS transistor426; the interconnect structure420may be connected to and extend between the additional N-type source region428A of the additional vertical NMOS transistor424and the N-type drain region408C of the vertical NMOS transistor404; the output structure418may be connected to the P-type drain region410C of the vertical PMOS transistor406, the additional N-type drain region428C of the additional vertical NMOS transistor424, and the additional P-type drain region430C of the additional vertical PMOS transistor426; the input structure434may be connected to each of the gate electrodes412(e.g., the first gate electrode412A and the second gate electrodes412B) of the CMOS circuit402; and the additional input structure436may be connected to each of the additional gate electrodes432(e.g., the first additional gate electrode432A and the second additional gate electrodes432B) of the additional CMOS circuit422. The GND structure414, the Vccstructure416, the interconnect structure420, the output structure418, the input structure434, and the additional input structure436of the two-input NAND gate400may exhibit conventional configurations (e.g., conventional dimensions, conventional shapes, conventional conductive material compositions, conventional material distributions, conventional orientations, conventional arrangements), which are not described in detail herein.

FIG. 5Ashows a simplified cross-sectional view of a balanced CMOS inverter500, in accordance with embodiments of the disclosure. The balanced CMOS inverter500includes a CMOS circuit502, a GND structure514, a Vccstructure516, an output structure518, and an input structure534(seeFIG. 5B).FIG. 5Bshows a plan view of the balanced CMOS inverter500shown inFIG. 5A.FIG. 5Cshows a plan view of an alternative configuration of the balanced CMOS inverter500shown inFIG. 5A, in accordance with additional embodiments of the disclosure.

As shown inFIG. 5A, the balanced CMOS inverter500may be similar to the CMOS inverter300previously described with reference toFIG. 3, except that the CMOS circuit502includes a single vertical NMOS transistor504and multiple (e.g., more than one) vertical PMOS transistors506. Multiple vertical PMOS transistors506may be employed to balance the driving strengths of the different transistors (e.g., the vertical NMOS transistor504, the vertical PMOS transistors506) of the CMOS circuit502so as to maximize noise margins and obtain symmetrical characteristics. As depicted inFIG. 5A, in some embodiments, the CMOS circuit502includes a single (e.g., only one) vertical NMOS transistor504, and three (3) vertical PMOS transistors506. In additional embodiments, the CMOS circuit502includes a different number of vertical PMOS transistors506. For example, the CMOS circuit502may include a single (e.g., only one) vertical NMOS transistor504and two (2) vertical PMOS transistors506.

The vertical NMOS transistor504of the CMOS circuit502includes a first semiconductive pillar508including an N-type source region508A, an N-type drain region508C, and a P-type channel region508B vertically between the N-type source region508A and the N-type drain region508C. In addition, each of the vertical PMOS transistors506of the CMOS circuit502individually includes a second semiconductive pillar510including a P-type source region510A, a P-type drain region510C, and an N-type channel region510B vertically between the P-type source region510A and the P-type drain region510C. The vertical NMOS transistor504and the vertical PMOS transistors506further include gate electrodes512, including first gate electrodes512A shared by neighboring vertical transistors (e.g., the vertical NMOS transistor504and the vertical PMOS transistor506closest thereto, neighboring vertical PMOS transistors506), and second gate electrodes512B not shared by neighboring vertical transistors. For example, as shown inFIG. 5A, the CMOS circuit502may include three (3) first gate electrodes512A and two (2) second gate electrodes512B. One of the first gate electrodes512A may be disposed laterally (e.g., horizontally) between the P-type channel region508B of the vertical NMOS transistor504and the N-type channel region510B of a first of the vertical PMOS transistors506closest thereto. The one of the first gate electrodes512A may be the only gate electrode laterally disposed between the P-type channel region508B of the vertical NMOS transistor504and the N-type channel region510B of the first of the vertical PMOS transistors506. Another of the first gate electrodes512A may be disposed laterally between the N-type channel region510B of the first of the vertical PMOS transistors506and the N-type channel region510B of a second of the vertical PMOS transistors506neighboring the first of the vertical PMOS transistors506. The another of the first gate electrodes512A may be the only gate electrode laterally disposed between the N-type channel region510B of the first of the vertical PMOS transistors506and the N-type channel region510B of the second of the vertical PMOS transistors506. Yet another of first gate electrodes512A may be disposed laterally between the N-type channel region510B of the second of the vertical PMOS transistors506and the N-type channel region510B of a third of the vertical PMOS transistors506neighboring the second of the vertical PMOS transistors506. The yet another of the first gate electrodes512A may be the only gate electrode laterally disposed between the N-type channel region510B of the second of the vertical PMOS transistors506and the N-type channel region510B of the third of the vertical PMOS transistors506. In addition, the vertical NMOS transistor504may include one of the second gate electrodes512B laterally adjacent a side of the P-type channel region508B thereof opposing another side laterally adjacent the one of the first gate electrodes512A; and the third of the vertical PMOS transistors506may include another of the second gate electrodes512B laterally adjacent a side of the N-type channel region510B thereof opposing another side laterally adjacent the yet another of the first gate electrodes512A.

In some embodiments, the first semiconductive pillar508of the vertical NMOS transistor504and the second semiconductive pillars510of the vertical PMOS transistors506of the CMOS circuit502are all substantially laterally aligned with other another. For example, as shown inFIG. 5B, the first semiconductive pillar508of the vertical NMOS transistor504and each of the second semiconductive pillars510of the vertical PMOS transistors506may be positioned at substantially the same location in the Y-direction, such that the first semiconductive pillar508and each of the second semiconductive pillars510form a substantially straight line with one another in the X-direction. In additional embodiments, the first semiconductive pillar508of the vertical NMOS transistor504and the second semiconductive pillars510of the vertical PMOS transistors506are not all substantially laterally aligned with other another. For example, as shown inFIG. 5C, at least one of the second semiconductive pillars510of the vertical PMOS transistors506may be positioned at a different location in the Y-direction than the first semiconductive pillar508of the vertical NMOS transistor504and the other of the second semiconductive pillars510of the vertical PMOS transistors506, such that the first semiconductive pillar508and each of the second semiconductive pillars510do not form a substantially straight line with one another in the X-direction. In some such embodiments, the second semiconductive pillar510offset from the other semiconductive pillars of the CMOS circuit502in a first lateral direction (e.g., the Y-direction) is aligned with at least one of the other second semiconductive pillars510in a second, different lateral direction (e.g., the X-direction). For example, as also shown inFIG. 5C, the second semiconductive pillar510positioned at a different location in the Y-direction than the first semiconductive pillar508and the other second semiconductive pillars510may be positioned at substantially the same location in the X-direction as one of the other second semiconductive pillars510. As a result, one of the first gate electrodes512A may be shared by and laterally disposed between (e.g., in the X-direction) one of the vertical PMOS transistors506and two (2) other of the vertical PMOS transistors506. In addition, each of the two (2) other of the vertical PMOS transistors506may include one of the second gate electrodes512B laterally adjacent a side of the N-type channel region510B thereof opposing another side laterally adjacent the one of the first gate electrodes512A.

In additional embodiments, the second semiconductive pillar510positioned at a different location in the Y-direction than the other second semiconductive pillars510is disposed at a different location in the X-direction than that depicted inFIG. 5C. For example, the second semiconductive pillar510offset from the other second semiconductive pillars510may be provided laterally adjacent (e.g., in the X-direction) the first semiconductive pillar508of the vertical NMOS transistor504, such that one of the first gate electrodes512A is shared by and laterally disposed between (e.g., in the X-direction) the vertical NMOS transistor504and two (2) of the vertical PMOS transistors506, and another of the first gate electrodes512A is shared by and laterally disposed between (e.g., in the X-direction) the two (2) of the vertical PMOS transistors506and another of the vertical PMOS transistors506. In further embodiments, each of the second semiconductive pillars510of the vertical PMOS transistors506is positioned at a different location in the Y-direction than each other of the second semiconductive pillars510, and each of the second semiconductive pillars510is positioned at a substantially the same location in the X-direction as each other of the second semiconductive pillars510. For example, each of the second semiconductive pillars510of the vertical PMOS transistors506may be provided laterally adjacent (e.g., in the X-direction) the first semiconductive pillar508of the vertical NMOS transistor504, such that a single (e.g., only one) first gate electrode512A is shared by and laterally disposed between (e.g., in the X-direction) the vertical NMOS transistor504and each of the vertical PMOS transistors506.

With returned reference toFIG. 5A, regarding the additional components of the balanced CMOS inverter500, the GND structure514may be connected to the N-type source region508A of the vertical NMOS transistor504; the Vccstructure516may be connected to the P-type source region510A of each of the vertical PMOS transistors506; the output structure518may be connected to the N-type drain region508C of the vertical NMOS transistor504and the P-type drain region510C of each of the vertical PMOS transistors506; and the input structure534(FIG. 5B) may be connected to each of the gate electrodes512(e.g., the first gate electrodes512A and the second gate electrodes512B) of the CMOS circuit502. The GND structure514, the Vccstructure516, the output structure518, and the input structure534of the balanced CMOS inverter500may exhibit conventional configurations (e.g., conventional dimensions, conventional shapes, conventional conductive material compositions, conventional material distributions, conventional orientations, conventional arrangements), which are not described in detail herein.

FIG. 6Ashows a simplified cross-sectional view of a balanced CMOS transmission pass gate600, in accordance with embodiments of the disclosure. The balanced CMOS transmission pass gate600includes a CMOS circuit602, an output structure618, an input structure634, a first gate input structure638(seeFIG. 6B), and a second gate input structure640(seeFIG. 6B).FIG. 6Bshows a plan view of the balanced CMOS transmission pass gate600shown inFIG. 6A.FIG. 6Cshows a plan view of an alternative configuration of the balanced CMOS transmission pass gate600shown inFIG. 6A, in accordance with additional embodiments of the disclosure.

As shown inFIG. 6A, the CMOS circuit602of the balanced CMOS transmission pass gate600includes a vertical NMOS transistor604and multiple (e.g., more than one) vertical PMOS transistors606. The multiple vertical PMOS transistors606may be employed to balance the driving strengths of the different transistors (e.g., the vertical NMOS transistor604, the vertical PMOS transistors606) of the CMOS circuit602so as to maximize noise margins and obtain symmetrical characteristics. As depicted inFIG. 6A, in some embodiments, the CMOS circuit602includes a single (e.g., only one) vertical NMOS transistor604, and three (3) vertical PMOS transistors606. In additional embodiments, the CMOS circuit602includes a different number of vertical PMOS transistors606. For example, the CMOS circuit602may include a single (e.g., only one) vertical NMOS transistor604and two (2) vertical PMOS transistors606. In further embodiments, the CMOS circuit602includes a single (e.g., only one) vertical NMOS transistor604and a single (e.g., only one) vertical PMOS transistor606.

The vertical NMOS transistor604of the CMOS circuit602includes a first semiconductive pillar608including an N-type source region608A, an N-type drain region608C, and a P-type channel region608B vertically between the N-type source region608A and the N-type drain region608C. In addition, each of the vertical PMOS transistors606of the CMOS circuit602individually includes a second semiconductive pillar610including a P-type source region610A, a P-type drain region610C, and an N-type channel region610B vertically between the P-type source region610A and the P-type drain region610C. The vertical NMOS transistor604and the vertical PMOS transistors606further include gate electrodes612, including first gate electrodes612A shared by some neighboring vertical transistors (e.g., neighboring vertical PMOS transistors606), and second gate electrodes612B not shared by neighboring vertical transistors. For example, as shown inFIG. 6A, the CMOS circuit602may include two (2) first gate electrodes612A and four (4) second gate electrodes612B. One of the first gate electrodes612A may be disposed laterally between the N-type channel region610B of a first of the vertical PMOS transistors606and the N-type channel region610B of a second of the vertical PMOS transistors606neighboring the first of the vertical PMOS transistors606. The one of the first gate electrodes612A may be the only gate electrode laterally disposed between the N-type channel region610B of the first of the vertical PMOS transistors606and the N-type channel region610B of the second of the vertical PMOS transistors606. Another of the first gate electrodes612A may be disposed laterally between the N-type channel region610B of the second of the vertical PMOS transistors606and the N-type channel region610B of a third of the vertical PMOS transistors606neighboring the second of the vertical PMOS transistors606. The another of the first gate electrodes612A may be the only gate electrode laterally disposed between the N-type channel region610B of the second of the vertical PMOS transistors606and the N-type channel region610B of the third of the vertical PMOS transistors606. In addition, the vertical NMOS transistor604may include two (2) of the second gate electrodes612B laterally adjacent opposing sides of the P-type channel region608B thereof (e.g., such that the vertical NMOS transistor604does not share a gate electrode with any of the vertical PMOS transistors606); the first of the vertical PMOS transistors606may include another of the second gate electrodes612B laterally adjacent a side of the N-type channel region610B thereof opposing another side laterally adjacent the one of the first gate electrodes612A; and the third of the vertical PMOS transistors606may include yet another of the second gate electrodes612B laterally adjacent a side of the N-type channel region610B thereof opposing another side laterally adjacent the another of the first gate electrodes612A.

In some embodiments, the first semiconductive pillar608of the vertical NMOS transistor604and the second semiconductive pillars610of the vertical PMOS transistors606of the CMOS circuit602are all substantially laterally aligned with other another. For example, as shown inFIG. 6B, the first semiconductive pillar608and each of the second semiconductive pillars610may be positioned at substantially the same location in the Y-direction, such that the first semiconductive pillar608and each of the second semiconductive pillars610form a substantially straight line with one another in the X-direction. In additional embodiments, the first semiconductive pillar608of the vertical NMOS transistor604and the second semiconductive pillars610of the vertical PMOS transistors606are not all substantially laterally aligned with other another. For example, as shown inFIG. 6C, at least one of the second semiconductive pillars610may be positioned at a different location in the Y-direction than the first semiconductive pillar608and the other second semiconductive pillars610, such that the first semiconductive pillar608and the second semiconductive pillars610do not form a substantially straight line with one another in the X-direction. In some such embodiments, the second semiconductive pillar610offset from the other semiconductive pillars of the CMOS circuit602in a first lateral direction (e.g., the Y-direction) is aligned with at least one other of the second semiconductive pillars610in a second, different lateral direction (e.g., the X-direction). For example, as also shown inFIG. 6C, the second semiconductive pillar610positioned at a different location in the Y-direction than the first semiconductive pillar608and the other of the second semiconductive pillars610, and may be positioned at substantially the same location in the X-direction as one of the other of the second semiconductive pillars610. As a result, one of the first gate electrodes612A may be shared by and laterally disposed between (e.g., in the X-direction) one of the vertical PMOS transistors606and two (2) other of the vertical PMOS transistors606. In addition, each of the two (2) other of the vertical PMOS transistors606may include one of the second gate electrodes612B laterally adjacent a side of the N-type channel region610B thereof opposing another side laterally adjacent the one of the first gate electrodes612A. In further embodiments, the second semiconductive pillar610positioned at a different location in the Y-direction than the other of the second semiconductive pillars610is positioned at a different location in the X-direction than that depicted inFIG. 6C. For example, the second semiconductive pillar610offset from the other second semiconductive pillars610may be provided laterally adjacent (e.g., in the X-direction) the first semiconductive pillar608of the vertical NMOS transistor604.

With returned reference toFIG. 6A, regarding the additional components of the balanced CMOS transmission pass gate600, the output structure618may be connected to the N-type source region608A of the vertical NMOS transistor604and the P-type source region610A of each of the vertical PMOS transistors606; the input structure634may be connected to N-type drain region608C of the vertical NMOS transistor604and the P-type drain region610C of each of the vertical PMOS transistors606; the first gate input structure638(FIG. 6B) may be connected to the second gate electrodes612B adjacent opposing sides of the vertical NMOS transistor604; and the second gate input structure640(FIG. 6B) may be connected to the first gate electrodes612A, and the second gate electrodes612B adjacent sides of the vertical PMOS transistors606. The output structure618, the input structure634, the first gate input structure638, and the second gate input structure640of the balanced CMOS transmission pass gate600may exhibit conventional configurations (e.g., conventional dimensions, conventional shapes, conventional conductive material compositions, conventional material distributions, conventional orientations, conventional arrangements), which are not described in detail herein.

FIG. 7Ashows a simplified cross-sectional view of a balanced two-input NAND gate700, in accordance with embodiments of the disclosure. The balanced two-input NAND gate700includes a CMOS circuit702, an additional CMOS circuit722, a GND structure714, a Vccstructure716, an interconnect structure720, an output structure718, an input structure734(seeFIG. 7B), and an additional input structure736(seeFIG. 7B).FIG. 7Bshows a plan view of the balanced two-input NAND gate700shown inFIG. 7A.FIG. 7Cshows a plan view of an alternative configuration of the balanced two-input NAND gate700shown inFIG. 7A, in accordance with additional embodiments of the disclosure.

As shown inFIG. 7A, the balanced two-input NAND gate700may be similar to the two-input NAND gate400previously described with reference toFIG. 4, except that the CMOS circuit702includes a single vertical NMOS transistor704and multiple (e.g., more than one) vertical PMOS transistors706, and the additional CMOS circuit722includes a single additional vertical NMOS transistor724and multiple additional vertical PMOS transistors726. As depicted inFIG. 7A, in some embodiments, the CMOS circuit702includes one vertical NMOS transistor704, and three (3) vertical PMOS transistors706; and the additional CMOS circuit722includes one additional vertical NMOS transistor724, and three (3) additional vertical PMOS transistors726. In additional embodiments, the CMOS circuit702includes a different number of vertical PMOS transistors706, and/or the additional CMOS circuit722includes a different number of additional vertical PMOS transistors726. For example, the CMOS circuit702may include one vertical NMOS transistor704and two (2) vertical PMOS transistors706, and/or the additional CMOS circuit722may include one additional vertical NMOS transistor724and two (2) additional vertical PMOS transistors726.

The vertical NMOS transistor704of the CMOS circuit702includes a first semiconductive pillar708including an N-type source region708A, an N-type drain region708C, and a P-type channel region708B vertically between the N-type source region708A and the N-type drain region708C. In addition, each of the vertical PMOS transistors706of the CMOS circuit702individually includes a second semiconductive pillar710including a P-type source region710A, a P-type drain region710C, and an N-type channel region710B vertically between the P-type source region710A and the P-type drain region710C. The vertical NMOS transistor704and the vertical PMOS transistors706further include gate electrodes712, including first gate electrodes712A shared by neighboring vertical transistors (e.g., the vertical NMOS transistor704and the vertical PMOS transistor706closest thereto, neighboring vertical PMOS transistors706), and second gate electrodes712B not shared by neighboring vertical transistors. For example, as shown inFIG. 7A, the CMOS circuit702may include three (3) first gate electrodes712A and two (2) second gate electrodes712B. One of the first gate electrodes712A may be disposed laterally (e.g., horizontally) between the P-type channel region708B of the vertical NMOS transistor704and the N-type channel region710B of a first of the vertical PMOS transistors706closest thereto. The one of the first gate electrodes712A may be the only gate electrode laterally disposed between the P-type channel region708B of the vertical NMOS transistor704and the N-type channel region710B of the first of the vertical PMOS transistors706. Another of the first gate electrodes712A may be disposed laterally between the N-type channel region710B of the first of the vertical PMOS transistors706and the N-type channel region710B of a second of the vertical PMOS transistors706neighboring the first of the vertical PMOS transistors706. The another of the first gate electrodes712A may be the only gate electrode laterally disposed between the N-type channel region710B of the first of the vertical PMOS transistors706and the N-type channel region710B of the second of the vertical PMOS transistors706. Yet another of first gate electrodes712A may be disposed laterally between the N-type channel region710B of the second of the vertical PMOS transistors706and the N-type channel region710B of a third of the vertical PMOS transistors706neighboring the second of the vertical PMOS transistors706. The yet another of the first gate electrodes712A may be the only gate electrode laterally disposed between the N-type channel region710B of the second of the vertical PMOS transistors706and the N-type channel region710B of the third of the vertical PMOS transistors706. In addition, the vertical NMOS transistor704may include one of the second gate electrodes712B laterally adjacent a side of the P-type channel region708B thereof opposing another side laterally adjacent the one of the first gate electrodes712A; and the third of the vertical PMOS transistors706may include another of the second gate electrodes712B laterally adjacent a side of the N-type channel region710B thereof opposing another side laterally adjacent the yet another of the first gate electrodes712A.

The additional vertical NMOS transistor724of the additional CMOS circuit722includes a first additional semiconductive pillar728including an N-type source region728A, an N-type drain region728C, and a P-type channel region728B vertically between the N-type source region728A and the N-type drain region728C. In addition, each of the additional vertical PMOS transistors726of the additional CMOS circuit722individually includes a second additional semiconductive pillar730including a P-type source region730A, a P-type drain region730C, and an N-type channel region730B vertically between the P-type source region730A and the P-type drain region730C. The additional vertical NMOS transistor724and the additional vertical PMOS transistors726further include additional gate electrodes732, including first additional gate electrodes732A shared by neighboring vertical transistors (e.g., the additional vertical NMOS transistor724and the additional vertical PMOS transistor726closest thereto, neighboring additional vertical PMOS transistors726), and second additional gate electrodes732B not shared by neighboring vertical transistors. For example, as shown inFIG. 7A, the additional CMOS circuit722may include three (3) first additional gate electrodes732A and two (2) second additional gate electrodes732B. One of the first additional gate electrodes732A may be disposed laterally (e.g., horizontally) between the P-type channel region728B of the additional vertical NMOS transistor724and the N-type channel region730B of a first of the additional vertical PMOS transistors726closest thereto. The one of the first additional gate electrodes732A may be the only gate electrode laterally disposed between the P-type channel region728B of the additional vertical NMOS transistor724and the N-type channel region730B of the first of the additional vertical PMOS transistors726. Another of the first additional gate electrodes732A may be disposed laterally between the N-type channel region730B of the first of the additional vertical PMOS transistors726and the N-type channel region730B of a second of the additional vertical PMOS transistors726neighboring the first of the additional vertical PMOS transistors726. The another of the first additional gate electrodes732A may be the only gate electrode laterally disposed between the N-type channel region730B of the first of the additional vertical PMOS transistors726and the N-type channel region730B of the second of the additional vertical PMOS transistors726. Yet another of the first additional gate electrodes732A may be disposed laterally between the N-type channel region730B of the second of the additional vertical PMOS transistors726and the N-type channel region730B of a third of the additional vertical PMOS transistors726neighboring the second of the additional vertical PMOS transistors726. The yet another of the first additional gate electrodes732A may be the only gate electrode laterally disposed between the N-type channel region730B of the second of the additional vertical PMOS transistors726and the N-type channel region730B of the third of the additional vertical PMOS transistors726. In addition, the additional vertical NMOS transistor724may include one of the second additional gate electrodes732B laterally adjacent a side of the P-type channel region728B thereof opposing another side laterally adjacent the one of the first additional gate electrodes732A; and the third of the additional vertical PMOS transistors726may include another of the second additional gate electrodes732B laterally adjacent a side of the N-type channel region730B thereof opposing another side laterally adjacent the yet another of the first additional gate electrodes732A.

In some embodiments, the semiconductive pillars of the CMOS circuit702and the additional semiconductive pillars of the additional CMOS circuit722are all substantially laterally aligned with other another. For example, as shown inFIG. 7B, the first semiconductive pillar708of the CMOS circuit702, each of the second semiconductive pillars710of the CMOS circuit702, the first additional semiconductive pillar728of the additional CMOS circuit722, and each of the second additional semiconductive pillars730of the additional CMOS circuit722may be positioned at substantially the same location in the Y-direction. In additional embodiments, one or more of the semiconductive pillars of the CMOS circuit702and/or one or more of the additional semiconductive pillars of the additional CMOS circuit722are not substantially laterally aligned with one another. For example, as shown inFIG. 7C, one or more of the second semiconductive pillars710of the vertical PMOS transistors706of the CMOS circuit702may be positioned at a different location in the Y-direction than one or more other of the semiconductive pillars (e.g., the first semiconductive pillar708, one or more other of the second semiconductive pillars710) of the CMOS circuit702and the additional semiconductive pillars (e.g., the first additional semiconductive pillar728, one or more of the second additional semiconductive pillars730) of the additional CMOS circuit722; and/or one or more of the second additional semiconductive transistors726of the additional vertical PMOS transistors726of the additional CMOS circuit722may be positioned at a different location in the Y-direction than one or more other of the semiconductive pillars (e.g., the first semiconductive pillar708, one or more of the second semiconductive pillars710) of the CMOS circuit702and the additional semiconductive pillars (e.g., the first additional semiconductive pillar728, one or more other of the second additional semiconductive pillars730) of the additional CMOS circuit722. In some embodiments, one of the second semiconductive pillars710is offset from the other second semiconductive pillars710of the CMOS circuit702in a first lateral direction (e.g., the Y-direction), and is aligned with at least one of the other second semiconductive pillars710in a second, different lateral direction (e.g., the X-direction); and one of the second additional semiconductive pillars730is offset from the other additional semiconductive pillars of the additional CMOS circuit722in the first lateral direction, and is aligned with at least one of the other second additional semiconductive pillars730in the second, different lateral direction. As a result, one of the first gate electrodes712A may be shared by and laterally disposed between (e.g., in the X-direction) one of the vertical PMOS transistors706and two (2) other of the vertical PMOS transistors706; and one of first additional gate electrodes732A may be shared by and laterally disposed between (e.g., in the X-direction) one of the additional vertical PMOS transistors726and two (2) other of the additional vertical PMOS transistors726. In addition, each of the two (2) other of the vertical PMOS transistors706may include one of the second gate electrodes712B laterally adjacent a side of the N-type channel region710B thereof opposing another side laterally adjacent the one of the first gate electrodes712A; and each of the two (2) other of the additional vertical PMOS transistors726may include one of the second additional gate electrodes732B laterally adjacent a side of the N-type channel region730B thereof opposing another side laterally adjacent the one of the first additional gate electrodes732A.

In additional embodiments, the second semiconductive pillar710positioned at a different location in the Y-direction than the other of the second semiconductive pillars710is positioned at a different location in the X-direction than that depicted inFIG. 7C; and/or the second additional semiconductive pillar730positioned at a different location in the Y-direction than the other of the second additional semiconductive pillars730is positioned at a different location in the X-direction than that depicted inFIG. 7C. For example, the second semiconductive pillar710offset from the other second semiconductive pillars710may be provided laterally adjacent (e.g., in the X-direction) the first semiconductive pillar708, such that one of the first gate electrodes712A is shared by and laterally disposed between (e.g., in the X-direction) the vertical NMOS transistor704and two (2) of the vertical PMOS transistors706, and another of the first gate electrodes712A is shared by and laterally disposed between (e.g., in the X-direction) the two (2) of the vertical PMOS transistors706and another of the vertical PMOS transistors706. As another example, the second additional semiconductive pillar730offset from the other second additional semiconductive pillars730may be provided laterally adjacent (e.g., in the X-direction) the first additional semiconductive pillar728, such that one of the first additional gate electrodes732A is shared by and laterally disposed between (e.g., in the X-direction) the additional vertical NMOS transistor724and two (2) of the additional vertical PMOS transistors726, and another of the first additional gate electrodes732A is shared by and laterally disposed between (e.g., in the X-direction) the two (2) of the additional vertical PMOS transistors726and another of the additional vertical PMOS transistors726. In further embodiments, each of the second semiconductive pillars710is positioned at a different location in the Y-direction than each other of the second semiconductive pillars710, and each of the second semiconductive pillars710is positioned at a substantially the same location in the X-direction as each other of the second semiconductive pillars710; and/or each of the second additional semiconductive pillars730is positioned at a different location in the Y-direction than each other of the second additional semiconductive pillars730, and each of the second additional semiconductive pillars730is positioned at a substantially the same location in the X-direction as each other of the second additional semiconductive pillars730. For example, each of the second semiconductive pillars710may be provided laterally adjacent (e.g., in the X-direction) the first semiconductive pillars708, such that a single (e.g., only one) first gate electrode712A is shared by and laterally disposed between (e.g., in the X-direction) the vertical NMOS transistor704and each of the vertical PMOS transistors706; and/or each of the second additional semiconductive pillars730may be provided laterally adjacent (e.g., in the X-direction) the first additional semiconductive pillars728, such that a single first additional gate electrode732A is shared by and laterally disposed between (e.g., in the X-direction) the additional vertical NMOS transistor724and each of the additional vertical PMOS transistors726.

With returned reference toFIG. 7A, regarding the additional components of the balanced two-input NAND gate700, the GND structure714may be connected to the N-type source region708A of the vertical NMOS transistor704; the Vccstructure716may be connected to the P-type source region710A of each of the vertical PMOS transistors706, and the P-type source region730A of each of the additional vertical PMOS transistors726; the interconnect structure720may be connected to and extends between the N-type source region728A of the additional vertical NMOS transistor724and the N-type drain region708C of the vertical NMOS transistor704; the output structure718may be connected to the P-type drain region710C of each of the vertical PMOS transistors706, the N-type drain region728C of the additional vertical NMOS transistor724, and the P-type drain region730C of each of the additional vertical PMOS transistors726; the input structure734may be connected to each of the gate electrodes712(e.g., the first gate electrodes712A and the second gate electrodes712B) of the CMOS circuit702; and the additional input structure736may be connected to each of the additional gate electrodes732(e.g., the first additional gate electrodes732A and the second additional gate electrodes732B) of the additional CMOS circuit722. The GND structure714, the Vccstructure716, the interconnect structure720, the output structure718, the input structure734, and the additional input structure736of the balanced two-input NAND gate700may exhibit conventional configurations (e.g., conventional dimensions, conventional shapes, conventional conductive material compositions, conventional material distributions, conventional orientations, conventional arrangements), which are not described in detail herein.

FIG. 8Ashows a simplified cross-sectional view of another balanced two-input NAND gate800, in accordance with additional embodiments of the disclosure. The balanced two-input NAND gate800includes a CMOS circuit802, an additional CMOS circuit822, dummy (e.g., inactive) semiconductive pillars D, a GND structure814, a Vccstructure816, at least one interconnect structure820, an output structure818, an input structure834(seeFIG. 8B), and an additional input structure836(seeFIG. 8B).FIG. 8Bshows a plan view of the balanced two-input NAND gate800shown inFIG. 8A. As shown inFIG. 8B, the balanced two-input NAND gate800may be similar to the balanced two-input NAND gate700previously described with reference toFIG. 7, except that the CMOS circuit802includes multiple (e.g., more than one) vertical NMOS transistors804and multiple vertical PMOS transistors806associated with each of the vertical NMOS transistors804; the additional CMOS circuit822includes multiple additional vertical NMOS transistors824and multiple additional vertical PMOS transistors826associated with each of the additional vertical NMOS transistors824; and the balanced two-input NAND gate800also includes dummy (e.g., inactive) semiconductive pillars D.

Referring toFIG. 8B, in some embodiments, the CMOS circuit802includes two (2) vertical NMOS transistors804, and six (6) vertical PMOS transistors806; and the additional CMOS circuit822includes two (2) additional vertical NMOS transistors824, and six (6) additional vertical PMOS transistors826. Accordingly, a ratio of vertical NMOS transistors804to vertical PMOS transistors806in the CMOS circuit802may be 1:3; and a ratio of additional vertical NMOS transistors824to additional vertical PMOS transistors826in the additional CMOS circuit822may be 1:3. In additional embodiments, the CMOS circuit802includes a different number of vertical NMOS transistors804and vertical PMOS transistors806and/or a different ratio of vertical NMOS transistors804and vertical PMOS transistors806; and/or the additional CMOS circuit822includes a different number of additional vertical NMOS transistors824and additional vertical PMOS transistors826and/or a different ratio of additional vertical NMOS transistors824to additional vertical PMOS transistors826. For example, the CMOS circuit802may exhibit a 1:3 ratio of vertical NMOS transistors804to additional vertical PMOS transistors826, and may include more than two (2) vertical NMOS transistors804(e.g., three (3) vertical NMOS transistors804, five (5) vertical NMOS transistors804, ten (10) vertical NMOS transistors804, greater than or equal to twenty-five (25) vertical NMOS transistors804). As another example, the CMOS circuit802may exhibit a 1:2 ratio of vertical NMOS transistors804to additional vertical PMOS transistors826, and may include greater than or equal to two (2) vertical NMOS transistors804. As an additional example, the additional CMOS circuit822may exhibit a 1:3 ratio of additional vertical NMOS transistors824to additional vertical PMOS transistors826, and may include more than two (2) additional vertical NMOS transistors824(e.g., three (3) additional vertical NMOS transistors824, five (5) additional vertical NMOS transistors824, ten (10) additional vertical NMOS transistors824, greater than or equal to twenty-five (25) additional vertical NMOS transistors824). As a further example, the additional CMOS circuit822may exhibit a 1:2 ratio of additional vertical NMOS transistors824to additional vertical PMOS transistors826, and may include more than greater than or equal to two (2) additional vertical NMOS transistors804.

Each of the vertical NMOS transistors804of the CMOS circuit802individually includes a first semiconductive pillar808including an N-type source region808A, an N-type drain region808C, and a P-type channel region808B vertically between the N-type source region808A and the N-type drain region808C. In addition, each of the vertical PMOS transistors806of the CMOS circuit802individually includes a second semiconductive pillar810including a P-type source region810A, a P-type drain region810C, and an N-type channel region810B vertically between the P-type source region810A and the P-type drain region810C. The first semiconductive pillars808of the vertical NMOS transistors804may be substantially aligned with one another in a first lateral direction (e.g., the Y-direction), and each of the first semiconductive pillars808of the vertical NMOS transistors804may individually be substantially aligned with three (3) of the second semiconductive pillars810of the vertical PMOS transistors806in a second direction (e.g., the X-direction) substantially perpendicular to the first direction. In addition, the vertical NMOS transistors804and the vertical PMOS transistors806further include gate electrodes812, including first gate electrodes812A shared by neighboring vertical transistors adjacent opposing sides (e.g., in the X-direction) of the first gate electrodes812A, and second gate electrodes812B not shared by neighboring vertical transistors. As shown inFIG. 8B, one of the first gate electrodes812A may be disposed laterally between the first semiconductive pillars808of the vertical NMOS transistors804and a first pair of the second semiconductive pillars810of the vertical PMOS transistors806closest thereto; another of the first gate electrodes812A may be disposed laterally between the first pair of the second semiconductive pillars810and a second pair of the second semiconductive pillars810neighboring the first pair of the second semiconductive pillars810; and yet another of the first gate electrodes812A may be disposed laterally between the second pair of the second semiconductive pillars810and a third pair of the second semiconductive pillars810neighboring the second pair of the second semiconductive pillars810.

Each of the additional vertical NMOS transistors824of the additional CMOS circuit822individually includes a first additional semiconductive pillar828including an N-type source region828A, an N-type drain region828C, and a P-type channel region828B vertically between the N-type source region828A and the N-type drain region828C. In addition, each of the additional vertical PMOS transistors826of the additional CMOS circuit822individually includes a second additional semiconductive pillar830including a P-type source region830A, a P-type drain region830C, and an N-type channel region830B vertically between the P-type source region830A and the P-type drain region830C. The first additional semiconductive pillars828of the additional vertical NMOS transistors824may be substantially aligned with one another in a first lateral direction (e.g., the Y-direction), and each of the first additional semiconductive pillars828of the additional vertical NMOS transistors824may individually be substantially aligned with three (3) of the second additional semiconductive pillars830of the additional vertical PMOS transistors826in a second direction (e.g., the X-direction) substantially perpendicular to the first direction. In addition, the additional vertical NMOS transistors824and the additional vertical PMOS transistors826further include additional gate electrodes832, including first additional gate electrodes832A shared by neighboring additional vertical transistors adjacent opposing sides (e.g., in the X-direction) of the first additional gate electrodes832A, and second additional gate electrodes832B not shared by neighboring vertical transistors. As shown inFIG. 8B, one of the first additional gate electrodes832A may be disposed laterally between the first additional semiconductive pillars828of the additional vertical NMOS transistors824and a first pair of the second additional semiconductive pillars830of the additional vertical PMOS transistors826closest thereto; another of the first additional gate electrodes832A may be disposed laterally between the first pair of the second additional semiconductive pillars830and a second pair of the second additional semiconductive pillars830neighboring the first pair of the second additional semiconductive pillars830; and yet another of the first additional gate electrodes832A may be disposed laterally between the second pair of the second additional semiconductive pillars830and a third pair of the second additional semiconductive pillars830neighboring the second pair of the second additional semiconductive pillars830.

Referring collectively toFIGS. 8A and 8B, the dummy (e.g., inactive) semiconductive pillars D may laterally surround the active semiconductive pillars (e.g., the first semiconductive pillars808of the vertical NMOS transistors804, the second semiconductive pillars810of the vertical PMOS transistors806, the first additional semiconductive pillar828of the additional vertical NMOS transistors824, the second additional semiconductive pillars830of the additional vertical PMOS transistors826) of the CMOS circuit802and the additional CMOS circuit822. The dummy semiconductive pillars D may, for example, be employed to isolate the CMOS circuit802and the additional CMOS circuit822, to equalize pattern density across the balanced two-input NAND gate800, and/or to ensure proper printing of the active semiconductive pillars. The dummy semiconductive pillars D do not contribute to control logic functions of the balanced two-input NAND gate800.

The dummy semiconductive pillars D may each individually be substantially similar to the active semiconductive pillars laterally adjacent thereto. For example, shown inFIG. 8A, those dummy semiconductive pillars D laterally adjacent the first semiconductive pillars808of the vertical NMOS transistors804may each individually exhibit substantially the same configuration (e.g., size, shape, material composition, material distribution, orientation) as the first semiconductive pillars808; those dummy semiconductive pillars D laterally adjacent the second semiconductive pillars810of the vertical PMOS transistors806may each individually exhibit substantially the same configuration as the second semiconductive pillars810; those dummy semiconductive pillars D laterally adjacent the first additional semiconductive pillars828of the additional vertical NMOS transistors824may each individually exhibit substantially the same configuration as the first additional semiconductive pillars828; and those dummy semiconductive pillars D laterally adjacent the second additional semiconductive pillars830of the additional vertical PMOS transistors826may each individually exhibit substantially the same configuration as the second additional semiconductive pillars830.

Regarding the additional components of the balanced two-input NAND gate800, the GND structure814may be connected to the N-type drain region808C of each of the vertical NMOS transistors704; the Vccstructure816may be connected to the P-type source region810A of each of the vertical PMOS transistors806, and the P-type source region830A of each of the additional vertical PMOS transistors826; the interconnect structure820may be connected to and extends between the N-type source region828A of each of the additional vertical NMOS transistors824and the N-type source region808A of each of the vertical NMOS transistors804; the output structure818may be connected to the P-type drain region810C of each of the vertical PMOS transistors806, the N-type drain region828C of each of the additional vertical NMOS transistors824, and the P-type drain region830C of each of the additional vertical PMOS transistors826; the input structure834(FIG. 8B) may be connected to each of the gate electrodes812(e.g., the first gate electrodes812A and the second gate electrodes812B); and the additional input structure836(FIG. 8B) may be connected to each of the additional gate electrodes832(e.g., the first additional gate electrodes832A and the second additional gate electrodes832B). The GND structure814, the Vccstructure816, the interconnect structure820, the output structure818, the input structure834, and the additional input structure836of the balanced two-input NAND gate800may exhibit conventional configurations (e.g., conventional dimensions, conventional shapes, conventional conductive material compositions, conventional material distributions, conventional orientations, conventional arrangements), which are not described in detail herein.

Thus, a control logic device according to embodiments of the disclosure comprises a vertical transistor and another vertical transistor. The vertical transistor comprises a semiconductive structure and a shared gate electrode. The another vertical transistor comprises another semiconductive structure and the shared gate electrode. The semiconductive structure comprises a source region, a drain region, and a channel region between the source region and the drain region. The another semiconductive structure comprises another source region, another drain region, and another channel region between the another source region and the another drain region. The shared gate electrode laterally intervenes between the channel region of the semiconductive structure and the another channel region of the another semiconductive structure.

FIGS. 9A through 23Bare simplified partial cross-sectional (i.e.,FIGS. 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, and 23A) and simplified partial plan (i.e.,FIGS. 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, and 23B) views illustrating embodiments of a method of forming a TFT CMOS control logic device including one or more gate electrode(s) shared between vertical transistors (e.g., vertical PMOS transistors, vertical NMOS transistors) thereof. With the description as provided below, it will be readily apparent to one of ordinary skill in the art that the process described herein may be used in various applications. In other words, the process may be used whenever it is desired to form a semiconductor device structure including one or more gates electrode(s) shared between transistors (e.g., PMOS transistors, NMOS transistors) thereof.

Referring to collectively toFIGS. 9A and 9B, a TFT CMOS control logic device structure1000includes an N-type structure1004formed on or over a substrate1002(FIG. 9A). The substrate1002may comprise any base material or construction upon which additional materials may be formed. The substrate1002may be a semiconductor substrate, a base semiconductor material on a supporting structure, a metal electrode, or a semiconductor substrate having one or more materials, structures, or regions formed thereon. The substrate1002may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (SOI) substrates, such as silicon-on-sapphire (SOS) substrates and silicon-on-glass (SOG) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate1002may be doped or undoped. By way of non-limiting example, a substrate1002may comprise one or more of silicon, silicon dioxide, silicon with native oxide, silicon nitride, a carbon-containing silicon nitride, glass, semiconductor, metal oxide, metal, titanium nitride, carbon-containing titanium nitride, tantalum, tantalum nitride, carbon-containing tantalum nitride, niobium, niobium nitride, carbon-containing niobium nitride, molybdenum, molybdenum nitride, carbon-containing molybdenum nitride, tungsten, tungsten nitride, carbon-containing tungsten nitride, copper, cobalt, nickel, iron, aluminum, and a Noble metal.

The N-type structure1004may be formed of and include at least one N-type conductivity material. By way of non-limiting example, the N-type conductivity material may comprise polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorous ions, antimony ions). The N-type conductivity material may form channel regions of transistors (e.g., PMOS transistors) subsequently formed from the N-type structure1004, as described in further detail below. In addition, in some embodiments, the N-type structure1004further includes P-type conductivity materials above and below the N-type conductivity material. By way of non-limiting example, the P-type conductivity materials may comprise polysilicon doped with at least one P-type dopant (e.g., boron ions). The N-type structure1004may, for example, be formed to comprise a stack including a first P-type conductivity material on or over the substrate1002, an N-type conductivity material on or over the first P-type conductivity material, and a second P-type conductivity material on or over the N-type conductivity material.

The N-type structure1004may be formed on or over the substrate1002using conventional processes and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, at least one semiconductive material (e.g., polysilicon) may be conventionally formed (e.g., through one or more of in situ growth, spin-on coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and physical vapor deposition (PVD)) on or over the substrate1002and doped (e.g., through ion-implantation) to form the N-type structure1004.

Referring next toFIG. 10A, portions of the N-type structure1004(FIGS. 9A and 9B) may be selectively removed to form N-type line structures1006separated from one another by trenches1008(e.g., apertures, openings). As shown inFIG. 10A, the N-type line structures1006may each continuously extend in a first lateral direction (e.g., a Y-direction), and may be spaced apart from one another in a second lateral direction (an X-direction) perpendicular to the first lateral direction. The trenches1008intervening N-type line structures1006may continuously extend parallel to the N-type line structures1006in the first lateral direction (e.g., the Y-direction), and may longitudinally extend (e.g., in a Z-direction) to and expose (e.g., uncover) an upper surface of the substrate1002. The N-type line structures1006and the trenches1008may each individually be formed to exhibit any desired dimensions and spacing. The dimensions and spacing of the N-type line structures1006and the trenches1008may be selected at least partially based on desired dimensions and desired spacing of the additional structures to be formed from the N-type line structures1006and/or to be formed within the trenches1008, as described in further detail below.FIG. 10Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 10A.

The N-type line structures1006(and, hence, the trenches1008) may be formed using conventional processes (e.g., conventional photolithographic patterning processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, a mask structure may be provided on or over the N-type structure1004(FIGS. 9A and 9B), and portions of the N-type structure1004remaining unmasked (e.g., uncovered, exposed) by the mask structure may be selectively recessed and removed using at least one etching process (e.g., at least one dry etching process, such as at least one of a reactive ion etching (RIE) process, a deep RIE process, a plasma etching process, a reactive ion beam etching process, and a chemically assisted ion beam etching process; at least one wet etching process, such as at least one of a hydrofluoric acid etching process, a buffered hydrofluoric acid etching process, and a buffered oxide etching process).

Referring to next toFIG. 11A, linear spacer structures1009may be formed on or over opposing sidewalls of each of the N-type line structures1006. The linear spacer structures1009may partially fill the trenches1008, such that the linear spacer structures1009on neighboring N-type line structures1006are separated from one another by remainders of the trenches1008. The linear spacer structures1009may be formed of and include at least one dielectric material, such as one or more of an oxide material (e.g., silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide, a combination thereof), a nitride material (e.g., silicon nitride), and an oxynitride material (e.g., silicon oxynitride). In some embodiments, the linear spacer structures1009are formed of silicon dioxide. In addition, dimensions and spacing of the linear spacer structures1009(and, hence, the dimensions and spacing of remaining portions of the trenches1008) may be selected to provide desired dimensions and spacing to additional structures to be formed in the remaining portions of the trenches1008. By way of non-limiting example, the linear spacer structures1009may be sized and spaced to facilitate the formation of P-type line structures exhibiting dimensions and spacing substantially similar to those of the N-type line structures1006within the remaining portions of the trenches1008, as described in further detail below. In additional embodiments, the linear spacer structures1009are not formed on or over opposing sidewalls of each of the N-type line structures1006(e.g., the formation of the linear spacer structures1009is omitted, such that the opposing sidewalls of the N-type line structures1006remain free of any linear spacer structures1009formed thereon or thereover).FIG. 12Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 11A.

The linear spacer structures1009(if any) may be formed using conventional processes and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, a spacer material may be conformally formed (e.g., deposited through one or more of a PVD process, a CVD process, an ALD process, and a spin-coating process) over exposed surfaces of the N-type line structures1006and the substrate1002, and then an anisotropic etching process may be performed to remove the spacer material from upper surfaces of the N-type line structures1006and from portions of the upper surface of substrate1002underlying central portions of the trenches1008, while maintaining the spacer material on the opposing sidewalls of the N-type line structures1006to form the linear spacer structures1009.

Referring next toFIG. 12A, a P-type structure1010may be formed on or over exposed surfaces of the substrate1002, the N-type line structures1006, and the linear spacer structures1009(if any). As shown inFIG. 12A, the P-type structure1010may substantially fill remaining portions of the trenches1008(FIG. 11A), such as portions of the trenches1008(FIG. 11A) unoccupied by the linear spacer structures1009, and may exhibit a non-planar upper surface1014defined by elevated regions and recessed regions of the P-type structure1010. The elevated regions of the P-type structure1010may overlie the N-type line structures1006and the linear spacer structures1009(if any), and the recessed regions of the P-type structure1010may overlie regions of the substrate1002not covered by the N-type line structures1006and the linear spacer structures1009(if any).FIG. 12Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 12A.

The P-type structure1010may be formed of and include at least one P-type conductivity material. By way of non-limiting example, the P-type conductivity material may comprise polysilicon doped with at least one P-type dopant (e.g., boron ions). The P-type conductivity material may form channel regions of transistors (e.g., NMOS transistors) subsequently formed from the P-type structure1010, as described in further detail below. In addition, in some embodiments, the P-type structure1010further includes N-type conductivity materials above and below the P-type conductivity material. By way of non-limiting example, the N-type conductivity materials may comprise polysilicon doped with at least one N-type dopant (e.g., arsenic ions, phosphorous ions, antimony ions). The P-type structure1010may, for example, be formed to comprise a stack including a first N-type conductivity material on or over surfaces of the substrate1002, the N-type line structures1006, and the linear spacer structures1009(if any); a P-type conductivity material on or over the first N-type conductivity material, and a second N-type conductivity material on or over the P-type conductivity material.

The P-type structure1010may be formed using conventional processes and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, at least one semiconductive material (e.g., polysilicon) may be conventionally formed (e.g., through one or more of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD) on or over the substrate1002, the N-type line structures1006, and the linear spacer structures1009(if any); and then the semiconductive material may be doped (e.g., through ion-implantation) to form the P-type structure1010.

Referring next toFIG. 13A, at least one material removal process (e.g., at least one planarization process, such as at least one chemical-mechanical planarization (CMP) process) may be used to at least remove portions of the P-type structure1010(FIG. 12A) overlying upper surfaces of the N-type line structures1006, and the linear spacer structures1009(if any) and form P-type line structures1012. In some embodiments, the material removal process substantially only removes portions of the P-type structure1010(FIG. 12A) overlying the upper surfaces of the N-type line structures1006and the linear spacer structures1009(if any), such that the N-type line structures1006and the linear spacer structures1009remain substantially unmodified by the material removal process. In additional embodiments, the material removal process removes portions of the P-type structure1010(FIG. 12A) overlying the upper surfaces of the N-type line structures1006and the linear spacer structures1009(if any), and also removes upper portions of the N-type line structures1006and the linear spacer structures1009(if any) and additional portions of the P-type structure1010(FIG. 12A) laterally neighboring the N-type line structures1006and/or the linear spacer structures1009(if any). Accordingly, the material removal process may reduce thicknesses of the N-type line structures1006and the linear spacer structures1009(if any). As shown inFIG. 13A, the material removal process may form a substantially planar surface1018including substantially coplanar upper surfaces of the P-type line structures1012, the N-type line structures1006, and the linear spacer structures1009(if any). The P-type line structures1012may continuously extend parallel to the N-type line structures1006in the first lateral direction (e.g., the Y-direction), and may be spaced apart from one another in the second lateral direction (an X-direction) perpendicular to the first lateral direction. The dimensions and the spacing of the P-type line structures1012may respectively be substantially the same as the dimensions and the spacing of N-type line structures1006, or one or more of the dimensions and the spacing of the P-type line structures1012may be different than the dimensions and the spacing of the N-type line structures1006. In some embodiments, the dimensions and the spacing of the P-type line structures1012are respectively substantially the same as the dimensions and the spacing of N-type line structures1006.FIG. 13Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 13A.

Next, referring toFIG. 14A, a first mask structure1019may be provided on or over exposed upper surfaces of the P-type line structures1012, the N-type line structures1006, and the linear spacer structures1009(if any). The first mask structure1019may be formed of and include at least one material (e.g., at least one hard mask structure material) suitable for use as an etch mask structure to pattern portions of the P-type line structures1012, the N-type line structures1006, and the linear spacer structures1009(if any), as described in further detail below. By way of non-limiting example, the first mask structure1019may be formed of and include at least one of amorphous carbon, silicon, a silicon oxide, a silicon nitride, a silicon oxycarbide, aluminum oxide, and a silicon oxynitride. The first mask structure1019may be homogeneous (e.g., may comprise a single material layer), or may be heterogeneous (e.g., may comprise a stack exhibiting at least two different material layers).FIG. 14Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 14A.

The first mask structure1019exhibits a desired pattern to be transferred to the combination of the P-type line structures1012, the N-type line structures1006, and the linear spacer structures1009(if any). For example, referring toFIG. 14B, the first mask structure1019may include first linear structures1020, and first linear apertures1021(e.g., openings) laterally intervening (e.g., in the Y-direction) between the first linear structures1020. The first linear structures1020and the first linear apertures1021may individually exhibit lateral dimensions, shapes, positions, and orientations facilitating desired lateral dimensions, shapes, positions, and orientations of features and openings to be subsequently formed from and in the combination of the P-type line structures1012, the N-type line structures1006, and the linear spacer structures1009(if any). As shown inFIG. 14B, in some embodiments, each of the first linear structures1020exhibits substantially the same lateral dimensions (e.g., width, length), shape, spacing, and orientation as each other of the first linear structures1020. Accordingly, each of the first linear apertures1021may also exhibit substantially the same lateral dimensions (e.g., width, length), shape, spacing, and orientation as each other of the first linear apertures1021. In additional embodiments, one or more of the first linear structures1020exhibits one or more of different lateral dimensions (e.g., a different width, a different length), a different shape, different spacing, and/or a different orientation than one or more of the first linear structures1020. Accordingly, one or more of the first linear apertures1021may also exhibit one or more of different lateral dimensions (e.g., a different width, a different length), a different shape, different spacing, and/or a different orientation than one or more other of the first linear apertures1021.

The first mask structure1019, including the first linear structures1020and the first linear apertures1021thereof, may be formed and positioned by conventional processes (e.g., conventional deposition processes, such as at least one of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD; conventional photolithography processes; conventional material removal processes; conventional alignment processes) and conventional processing equipment, which are not described in detail herein.

Referring next toFIG. 15A, portions of the P-type line structures1012(FIGS. 14A and 14B), the N-type line structures1006(FIGS. 14A and 14B), and the linear spacer structures1009(FIGS. 14A and 14B) remaining uncovered by the first linear structures1020(FIGS. 14A and 14B) of the first mask structure1019(FIGS. 14A and 14B) may be subjected to at least one material removal process to respectively form first P-type pillar structures1013, first N-type pillar structures1007, and spacer structures1011. The material removal process may transfer or extend a pattern defined by the first linear apertures1021(FIG. 14B) in the first mask structure1019(FIGS. 14A and 14B) into the P-type line structures1012(FIGS. 14A and 14B), the N-type line structures1006(FIGS. 14A and 14B), and the linear spacer structures1009(FIGS. 14A and 14B) to form the first P-type pillar structures1013, the first N-type pillar structures1007, and the spacer structures1011. In addition, as shown inFIG. 15A, following the formation of the first P-type pillar structures1013, the first N-type pillar structures1007, and the spacer structures1011, remaining portions of the first mask structure1019(FIGS. 14A and 14B) may be removed to expose upper surfaces of the first P-type pillar structures1013, the first N-type pillar structures1007, and the spacer structures1011.FIG. 15Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 15A.

As shown inFIG. 15B, the material removal process forms first linear openings1015laterally intervening between (e.g., in the Y-direction) and separating neighboring first P-type pillar structures1013formed from the same P-type line structure1012(FIGS. 14A and 14B), neighboring first N-type pillar structures1007formed from the same N-type line structure1006(FIGS. 14A and 14B), and neighboring spacer structures1011formed from the same linear spacer structures1009(FIGS. 14A and 14B). The first linear openings1015may exhibit substantially the same lateral dimensions (e.g., in the Y-direction and the X-direction), shapes, spacing, and orientations as the first linear apertures1021(FIG. 14B) in the first mask structure1019(FIGS. 14A and 14B), and may longitudinally extend (e.g., in the Z-direction shown inFIG. 15A) to the substrate1002.

The material removal process employed to form the first P-type pillar structures1013, the first N-type pillar structures1007, the spacer structures1011, and the first linear openings1015may comprise a conventional anisotropic etching process, which is not described in detail herein. For example, the material removal process may comprise exposing portions of the P-type line structures1012(FIGS. 14A and 14B), the N-type line structures1006(FIGS. 14A and 14B), and the linear spacer structures1009(FIGS. 14A and 14B) remaining uncovered by the first linear structures1020(FIGS. 14A and 14B) of the first mask structure1019(FIGS. 14A and 14B) to one or more of anisotropic dry etching (e.g., reactive ion etching (RIE), deep RIE, plasma etching, reactive ion beam etching, chemically assisted ion beam etching) and anisotropic wet etching (e.g., hydrofluoric acid (HF) etching, a buffered HF etching, buffered oxide etching). In addition, remaining portions of the first mask structure1019(FIGS. 14A and 14B) (if any) may be selectively removed following the formation of the first P-type pillar structures1013, the first N-type pillar structures1007, the spacer structures1011, and the first linear openings1015using at least one other conventional material removal process (e.g., a conventional wet etching process, a conventional dry etching process), which are not described in detail herein.

Next, referring collectively toFIGS. 16A and 16B, first linear dielectric liner structures1024may be formed on or over surfaces within the first linear openings1015(FIG. 15B), and first linear isolation structures1022may be formed on or over surfaces of the first linear dielectric liner structures1024. The first linear dielectric liner structures1024may be formed on or over portions of the substrate1002exposed within the first linear openings1015(FIG. 15B), and on or over opposing sidewalls of neighboring first P-type pillar structures1013, opposing sidewalls of neighboring first N-type pillar structures1007, and opposing sidewalls neighboring spacer structures1011exposed within the first linear openings1015(FIG. 15B). In additional embodiments, the first linear dielectric liner structures1024on or over one or more surfaces within the first linear openings1015(FIG. 15B) may, optionally, be omitted (e.g., such that the first linear isolation structures1022are formed directly on surfaces of the substrate1002, the first P-type pillar structures1013, and the spacer structures1011are exposed within the first linear openings1015(FIG. 15B). The first linear dielectric liner structures1024formed within the first linear openings1015may be substantially confined within horizontal boundaries and vertical boundaries of the first linear openings1015. Accordingly, uppermost surfaces of the first linear dielectric liner structures1024may be substantially coplanar with a plane shared by the upper surfaces of the first P-type pillar structures1013, the N-type pillar structures1007, and the spacer structures1011.

The first linear dielectric liner structures1024(if any) may be formed of and include at least one dielectric material, such as one or more of an dielectric oxide material (e.g., silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide, a combination thereof), a dielectric nitride material (e.g., silicon nitride (SiN)), a dielectric oxynitride material (e.g., silicon oxynitride (SiON)), a dielectric carbonitride material (e.g., silicon carbonitride (SiCN)), and a dielectric carboxynitride material (e.g., silicon carboxynitride (SiOCN)). In some embodiments, the first linear dielectric liner structures1024comprise silicon dioxide. Each of the first linear dielectric liner structures1024may be formed to exhibit any desirable thickness. By way of non-limiting example, a thickness of each of the first linear dielectric liner structures1024may be less than or equal to about 1 nm, less than or equal to about 50 Angstroms (Å), less than or equal to about 25 Å, or less than or equal to about 10 Å. In some embodiments, the thickness of each of the first linear dielectric liner structures1024is within a range of from about 3 Å to about 10 Å. The thickness of each of the first linear dielectric liner structures1024may be substantially uniform, or at least one region of one or more of the first linear dielectric liner structures1024(e.g., a region extending across the upper surface of the substrate1002) may have a different thickness than at least one other region of one or more of the first linear dielectric liner structures1024(e.g., regions extending across the opposing sidewalls of neighboring first P-type pillar structures1013, the opposing sidewalls of neighboring first N-type pillar structures1007, and/or the opposing sidewalls neighboring spacer structures1011).

With continued reference toFIG. 16B, the first linear isolation structures1022may fill remaining spaces (e.g., spaces not occupied by the first linear dielectric liner structures1024) of the first linear openings1015(FIG. 15B). The first linear isolation structures1022may be formed on or over surfaces of the first P-type pillar structures1013, the first N-type pillar structures1007, the spacer structures1011, and the substrate1002(e.g., on surfaces of the first linear dielectric liner structures1024, if any). As shown inFIG. 16B, the first linear isolation structures1022may laterally intervene between neighboring first P-type pillar structures1013, neighboring first N-type pillar structures1007, and neighboring spacer structures1011in the Y-direction. The first linear isolation structures1022may electrically isolate the neighboring first P-type pillar structures1013from one another, and may also electrically isolate the neighboring first N-type pillar structures1007from one another. The first linear isolation structures1022formed within the first linear openings1015(FIG. 15B) may be substantially confined within the horizontal boundaries and the vertical boundaries of the first linear openings1015(FIG. 15B). Accordingly, upper surfaces of the first linear isolation structures1022may be substantially coplanar with a plane shared by the upper surfaces of the P-type pillar structures1013, N-type pillar structures1007, and the spacer structures1011.

The first linear isolation structures1022may be formed of and include a dielectric material, such as one or more of an dielectric oxide material (e.g., silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide, a combination thereof), a dielectric nitride material (e.g., SiN), a dielectric oxynitride material (e.g., SiON), a dielectric carbonitride material (e.g., SiCN), and a dielectric carboxynitride material (e.g., SiOCN). The dielectric material of the first linear isolation structures1022may be the same as or different than that of the first linear dielectric liner structures1024(if any). In some embodiments, each of the first linear isolation structures1022is formed of and includes a silicon oxide (e.g., silicon dioxide).

The first linear dielectric liner structures1024(if any) and the first linear isolation structures1022may be formed using conventional processes (e.g., conventional deposition processes and conventional material removal processes) and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, a first dielectric liner material may be formed (e.g., through one or more of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD) on exposed surfaces of the first P-type pillar structures1013, the first N-type pillar structures1007, the spacer structures1011(if any), and the substrate1002inside and outside of the first linear openings1015(FIG. 15B); a first dielectric material may be formed (e.g., through one or more of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD) on exposed surfaces of the first dielectric liner material inside and outside of the first linear openings1015(FIG. 15B); and then at least portions of the first dielectric liner material and first dielectric material outside of the first linear openings1015(FIG. 15B) may be removed (e.g., through at least one planarization process, such as at least one CMP process) to form the first linear dielectric liner structures1024from the first dielectric liner material, and the first linear isolation structures1022from the first dielectric material.

Next, referring toFIG. 17A, a second mask structure1025may be provided on or over exposed upper surfaces of the first P-type pillar structures1013, the first N-type pillar structures1007, the spacer structures1011(if any), the first linear dielectric liner structures1024(FIG. 17B)(if any), and the first linear isolation structures1022(FIG. 17B). The second mask structure1025may be formed of and include at least one material (e.g., at least one hard mask structure material) suitable for use as an etch mask structure to pattern portions of the first P-type pillar structures1013, the first N-type pillar structures1007, the spacer structures1011(if any), the first linear dielectric liner structures1024(if any), and the first linear isolation structures1022, as described in further detail below. By way of non-limiting example, the second mask structure1025may be formed of and include at least one of amorphous carbon, silicon, a silicon oxide, a silicon nitride, a silicon oxycarbide, aluminum oxide, and a silicon oxynitride. The second mask structure1025may be homogeneous (e.g., may comprise a single material layer), or may be heterogeneous (e.g., may comprise a stack exhibiting at least two different material layers). The material composition of the second mask structure1025may be substantially the same as or may be different than that of the first mask structure1019(FIG. 14B).FIG. 17Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 17A.

The second mask structure1025exhibits a desired pattern to be transferred to the combination of the first P-type pillar structures1013, the first N-type pillar structures1007, the spacer structures1011(if any), the first linear dielectric liner structures1024(if any), and the first linear isolation structures1022. For example, referring toFIG. 17B, the second mask structure1025may include second linear structures1026, second linear apertures1027(e.g., openings) laterally intervening (e.g., in the Y-direction) between some of the second linear structures1026, and, optionally, third linear apertures1028(e.g., openings) laterally intervening (e.g., in the Y-direction) between other of the second linear structures1026. The second linear structures1026, the second linear apertures1027, and the third linear apertures1028(if any) of the second mask structure1025may be oriented (e.g., laterally extend) in a lateral direction substantially perpendicular to that of the first linear structures1020(FIG. 14B) and the first linear apertures1021(FIG. 14B) of the first mask structure1019(FIG. 14B). For example, as shown inFIG. 17B, the second linear structures1026, the second linear apertures1027, and the third linear apertures1028(if any) of the second mask structure1025may laterally extend in the Y-direction substantially perpendicular to the X-direction in which the first linear structures1020(FIG. 14B) and the first linear apertures1021(FIG. 14B) of the first mask structure1019(FIG. 14B) laterally extend.

The second linear structures1026, the second linear apertures1027, and the third linear apertures1028(if any) of the second mask structure1025may individually exhibit lateral dimensions, shapes, positions, and orientations facilitating desired lateral dimensions, shapes, positions, and orientations of features and openings to be subsequently formed from and in the combination of the first P-type pillar structures1013, the first N-type pillar structures1007, the spacer structures1011(if any), the first linear dielectric liner structures1024(if any), and the first linear isolation structures1022. If present, the third linear apertures1028may be wider (e.g., in the X-direction) than the second linear apertures1027. For example, as shown inFIGS. 17A and 17B, the second mask structure1025may exhibit one or more regions1030, wherein the second linear structures1026are absent and/or non-uniformly spaced so as to form the third linear apertures1028to be relatively wider that the second linear apertures1027, and such that neighboring second linear structures1026laterally separated (e.g., in the X-direction) from one another by the third linear apertures1028are spaced apart by a greater distance than some other neighboring second linear structures1026laterally separated (e.g., in the X-direction) from one another by the second linear apertures1027. The third linear apertures1028may correspond to locations where neighboring structures subsequently formed from the first P-type pillar structures1013and the first N-type pillar structures1007do not share gate electrodes, as described in further detail below. In additional embodiments, the third linear apertures1028may be omitted, such that only the second linear apertures1027laterally intervene between the second linear structures1026. Each of the second linear structures1026may exhibit substantially the same lateral dimensions (e.g., width, length), shape, spacing, and orientation as each other of the second linear structures1026, or one or more of the second linear structures1026may exhibit one or more of different lateral dimensions (e.g., a different width, a different length), a different shape, different spacing, and/or a different orientation than one or more of the second linear structures1026. In addition, each of the second linear apertures1027may exhibit substantially the same lateral dimensions (e.g., width, length), shape, spacing, and orientation as each other of the second linear apertures1027, or one or more of the second linear apertures1027may exhibit one or more of different lateral dimensions (e.g., a different width, a different length), a different shape, different spacing, and/or a different orientation than one or more of the second linear apertures1027. Furthermore, each of the third linear apertures1028(if any) may exhibit substantially the same lateral dimensions (e.g., width, length), shape, spacing, and orientation as each other of the third linear apertures1028, or one or more of the third linear apertures1028may exhibit one or more of different lateral dimensions (e.g., a different width, a different length), a different shape, different spacing, and/or a different orientation than one or more of the third linear apertures1028.

The second mask structure1025, including the second linear structures1026, the second linear apertures1027, and the third linear apertures1028(if any) thereof, may be formed and positioned by conventional processes (e.g., conventional deposition processes, such as at least one of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD; conventional photolithography processes; conventional material removal processes; conventional alignment processes) and conventional processing equipment, which are not described in detail herein.

Next, referring collectively toFIGS. 18A and 18B, the spacer structures1011(FIGS. 17A and 17B) (if any) and portions of the first P-type pillar structures1013(FIGS. 17A and 17B), the first N-type pillar structures1007(FIGS. 17A and 17B), the first linear dielectric liner structures1024(FIG. 17B) (if any), and the first linear isolation structures1022(FIG. 17B) may be subjected to at least one additional material removal process to form second P-type pillar structures1032, second N-type pillar structures1034, first dielectric liner structures1033(if the first linear dielectric liner structures1024were present), and first isolation structures1035. The additional material removal process may transfer or extend a pattern defined by the third linear apertures1028(FIG. 17B) in the second mask structure1025(FIGS. 17A and 17B) into the combination of first P-type pillar structures1013(FIGS. 17A and 17B), the first N-type pillar structures1007(FIGS. 17A and 17B), the spacer structures1011(FIG. 17B) (if any), the first linear dielectric liner structures1024(FIG. 17B) (if any), and the first linear isolation structures1022(FIG. 17B) to form the second P-type pillar structures1032, the second N-type pillar structures1034, the first dielectric liner structures1033(if any), and the first isolation structures1035. In additional embodiments, the first linear dielectric liner structures1024(FIGS. 17A and 17B) (if any) and the first linear isolation structures1022(FIGS. 17A and 17B) may remain following the additional material removal process, such that the first dielectric liner structures1033and first isolation structures1035are not formed. In addition, as shown inFIGS. 18A and 18B, following the formation of the second P-type pillar structures1032, the second N-type pillar structures1034, the first dielectric liner structures1033(if any), and the first isolation structures1035, remaining portions of the second mask structure1025(FIGS. 17A and 17B) may be removed to expose upper surfaces of the second P-type pillar structures1032, the second N-type pillar structures1034, the first dielectric liner structures1033(if any), and the first isolation structures1035.

As shown inFIG. 18B, the additional material removal process may form second linear openings1036and third linear openings1037that may individually laterally intervene between (e.g., in the X-direction) and separate neighboring second P-type pillar structures1032formed from the same first P-type pillar structure1013(FIGS. 17A and 17B), neighboring second N-type pillar structures1034formed from the same first N-type pillar structure1007(FIGS. 17A and 17B), neighboring first dielectric liner structures1033(if any) formed from the same first linear dielectric liner structure1024(FIGS. 17A and 17B) (if any), and neighboring first isolation structures1035formed from the same first linear isolation structure1022(FIGS. 17A and 17B). The third linear openings1037may be relatively wider (e.g., in the X-direction) than the second linear openings1036. The second linear openings1036may exhibit substantially the same lateral dimensions (e.g., in the Y-direction and the X-direction), shapes, spacing, and orientations as the second linear apertures1027(FIG. 17B) in the second mask structure1025(FIGS. 17A and 17B), and may longitudinally extend (e.g., in the Z-direction shown inFIG. 18A) to the substrate1002. In addition, the third linear openings1037may exhibit substantially the same lateral dimensions (e.g., in the Y-direction and the X-direction), shapes, spacing, and orientations as the third linear apertures1028(FIG. 17B) in the second mask structure1025(FIGS. 17A and 17B), and may longitudinally extend (e.g., in the Z-direction shown inFIG. 18A) to the substrate1002. In additional embodiments wherein the third linear apertures1028(FIG. 17B) are omitted from the second mask structure1025(FIGS. 17A and 17B), the third linear openings1037may be absent, such that only the second linear openings1036laterally intervene between (e.g., in the X-direction) and separate neighboring second P-type pillar structures1032formed from the same first P-type pillar structure1013(FIGS. 17A and 17B), neighboring second N-type pillar structures1034formed from the same first N-type pillar structure1007(FIGS. 17A and 17B), neighboring first dielectric liner structures1033(if any) formed from the same first linear dielectric liner structure1024(FIGS. 17A and 17B) (if any), and neighboring first isolation structures1035formed from the same first linear isolation structure1022(FIGS. 17A and 17B).

The additional material removal process employed to form the second P-type pillar structures1032, the second N-type pillar structures1034, the first dielectric liner structures1033(if any), the first isolation structures1035, the second linear openings1036, and the third linear openings1037(if any) may comprise a conventional anisotropic etching process, which is not described in detail herein. For example, the additional material removal process may comprise exposing the spacer structures1011(FIGS. 17A and 17B) (if any) and portions of the first P-type pillar structures1013(FIGS. 17A and 17B), the first N-type pillar structures1007(FIGS. 17A and 17B), the first linear dielectric liner structures1024(FIGS. 17A and 17B) (if any), and the first linear isolation structures1022(FIGS. 17A and 17B) remaining uncovered by the second linear structures1026(FIGS. 17A and 17B) of the second mask structure1025(FIGS. 17A and 17B) to one or more of anisotropic dry etching (e.g., RIE, deep RIE, plasma etching, reactive ion beam etching, chemically assisted ion beam etching) and anisotropic wet etching (e.g., HF etching, a buffered HF etching, buffered oxide etching). In addition, remaining portions of the second mask structure1025(FIGS. 17A and 17B) (if any) may be selectively removed following the formation of the second P-type pillar structures1032, the second N-type pillar structures1034, the first dielectric liner structures1033(if any), the first isolation structures1035, the second linear openings1036, and the third linear openings1037(if any) using at least one other conventional material removal process (e.g., a conventional wet etching process, a conventional dry etching process), which is not described in detail herein.

Next, referring toFIG. 19A, a gate dielectric material1038may be formed (e.g., conformally formed) on or over exposed surfaces of the second P-type pillar structures1032, the second N-type pillar structures1034, the first dielectric liner structures1033(if any), the first isolation structures1035, and the substrate1002. The gate dielectric material1038may be formed of and include a dielectric oxide material (e.g., silicon dioxide; phosphosilicate glass; borosilicate glass; borophosphosilicate glass; fluorosilicate glass; aluminum oxide; high-k oxides, such as hafnium oxide (HfOx); a combination thereof), a dielectric nitride material (e.g., silicon nitride (SiN)), a dielectric oxynitride material (e.g., silicon oxynitride (SiON)), a dielectric carbonitride material (e.g., silicon carbonitride (SiCN)), and a dielectric carboxynitride material (e.g., silicon carboxynitride (SiOCN)), and amphorous carbon. In some embodiments, the gate dielectric material1038comprises silicon dioxide. The gate dielectric material1038may be formed at any suitable thickness. The thickness of the gate dielectric material1038may be selected (e.g., tailored) to provide a desired lateral offset (e.g., space, distance) between the second P-type pillar structures1032, the second N-type pillar structures1034, and one or more gate electrodes to be subsequently formed laterally adjacent thereto, and to provide a desired longitudinal offset (e.g., space, distance) between the subsequently-formed gate electrodes and the substrate1002. By way of non-limiting example, the thickness of the gate dielectric material1038may be less than or equal to about 100 Angstroms (Å), less than or equal to about 50 Å, less than or equal to about 25 Å, or less than or equal to about 10 Å. In some embodiments, the thickness of the gate dielectric material1038is within a range of from about 5 Å to about 10 Å. The thickness of the gate dielectric material1038may be substantially uniform, or at least one region of the gate dielectric material1038may have a different thickness than at least one other region of the gate dielectric material1038.FIG. 19Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 19A, wherein the gate dielectric material1038is depicted as transparent to show the other components of the TFT CMOS control logic device structure1000provided thereunder.

The gate dielectric material1038may be formed on or over the exposed surfaces of the second P-type pillar structures1032, the second N-type pillar structures1034, the first dielectric liner structures1033(if any), the first isolation structures1035, and the substrate1002using conventional processes (e.g., one or more of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD) and conventional processing equipment, which are not described in detail herein.

Referring next toFIG. 20A, a gate material1040may be formed (e.g., conformally formed) on or over exposed surfaces of the gate dielectric material1038. The gate material1040may be formed of and include an electrically conductive material including, but not limited to, a metal (e.g., W, Ti, Ni, Pt, Au), a metal alloy, a metal-containing material (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), a conductively-doped semiconductor material (e.g., conductively-doped silicon, conductively-doped germanium, conductively-doped silicon germanium, etc.), or combinations thereof. By way of non-limiting example, the gate material1040may comprise at least one of TiN, TaN, WN, TiAlN, elemental Ti, elemental Pt, elemental Rh, elemental Ir, iridium oxide (IrOx), elemental Ru, ruthenium oxide (RuOx), alloys thereof, or combinations thereof. In some embodiments, the gate material1040comprises TiN.FIG. 20Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 19A, wherein the gate material1040is depicted as transparent and the gate dielectric material1038(FIG. 20A) is omitted to show the other components of the TFT CMOS control logic device structure1000provided thereunder.

As shown inFIG. 20A, the gate material1040may substantially (e.g., completely) fill remaining spaces (e.g., spaces not occupied by the gate dielectric material1038) of the second linear openings1036, and may only partially (e.g., less than completely) fill remaining spaces of the third linear openings1037(if any). As described in further detail below, each of the second linear openings1036substantially filled with the gate material1040may individually facilitate the formation of a single (e.g., only one), shared gate electrode between neighboring (e.g., in the X-direction) second P-type pillar structures1032, neighboring (e.g., in the X-direction) second N-type pillar structures1034, or a second P-type pillar structure1032neighboring (e.g., in the X-direction) a second N-type pillar structure1034. In turn, as also described in further detail below, each third linear opening1037(if any) only partially filled with the gate material1040may individually facilitate the formation of two, unshared gate electrodes between neighboring (e.g., in the X-direction) second P-type pillar structures1032, neighboring (e.g., in the X-direction) second N-type pillar structures1034, or a second P-type pillar structure1032neighboring (e.g., in the X-direction) a second N-type pillar structure1034.

The gate material1040may be formed on or over the exposed surfaces of the gate dielectric material1038using conventional processes (e.g., one or more of spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD) and conventional processing equipment, which are not described in detail herein.

Referring to next toFIG. 21A, the gate material1040(FIG. 20A) may be subjected to at least one material removal process to form shared gate electrodes1042and non-shared gate electrodes1044. The shared gate electrodes1042may be provided in the second linear openings1036, and the non-shared gate electrodes1044may be provided in the third linear openings1037. Each of the second linear openings1036may exhibit a single (e.g., only one) shared gate electrode1042, and each of the third linear openings1037may exhibit two (2) non-shared gate electrodes1044. Each shared gate electrode1042may substantially extend across the lateral dimensions of a remainder of the second linear opening1036associated therewith in the X-direction and the Y-direction, whereas each non-shared gate electrode1044may only partially extend across the lateral dimensions of a remainder of the third linear opening1037associated therewith in the X-direction.FIG. 21Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 21A.

As shown inFIGS. 21A and 21B, each shared gate electrode1042continuously extends in a first lateral direction (e.g., the Y-direction), and may intervene between and be shared by at least two (2) neighboring second P-type pillar structures1032in a second lateral direction (e.g. the X-direction), at least two (2) neighboring second N-type pillar structures1034in the second lateral direction, or at least one second P-type pillar structure1032neighboring at least one second N-type pillar structure1034in the second lateral direction. Opposing lateral sides of each shared gate electrode1042in the second lateral direction may, for example, be provided directly adjacent portions of the gate dielectric material1038intervening between the neighboring second P-type pillar structures1032, the neighboring second N-type pillar structures1034, or the second P-type pillar structure1032neighboring the second N-type pillar structure1034. Accordingly, neighboring shared gate electrodes1042may be separated from one another in the second lateral direction by one or more second P-type pillar structures1032, or one or more second N-type pillar structures1034.

As also shown inFIGS. 21A and 21B, each non-shared gate electrode1044continuously extends in the first lateral direction (e.g., the Y-direction, and may be positioned between another non-shared gate electrode1044and one or more second P-type pillar structures1032in the second lateral direction (e.g. the X-direction), or between another non-shared gate electrode1044and one or more second N-type pillar structures1034in the second lateral direction. Accordingly, neighboring non-shared gate electrodes1044may be separated from one another in the X-direction by a remainder of the third linear openings1037in which the neighboring non-shared gate electrodes1044are mutually disposed within. In additional embodiments, such as embodiments wherein the third linear openings1037are not formed, the non-shared gate electrodes1044are omitted (e.g., only shared gate electrodes1042are formed).

The shared gate electrodes1042and the non-shared gate electrodes1044may be formed from the gate material1040(FIG. 20A) using conventional material removal processes (e.g., conventional etching processes) and conventional material removal equipment, which are not described in detail herein. For example, to form the shared gate electrodes1042and the non-shared gate electrodes1044, the gate material1040(FIG. 20A) may be subjected to a conventional anisotropic etching process (e.g., a conventional anisotropic dry etching process) to remove portions of the gate material1040(FIG. 20A) overlying upper surfaces of the second P-type pillar structures1032, upper surfaces of the second N-type pillar structures1034, and portions of the upper surface of the substrate1002underlying the third linear openings1037, while maintaining other portions of the gate material1040(FIG. 20A) overlying sidewalls of the second P-type pillar structures1032and the second N-type pillar structures1034.

Next, referring toFIG. 22A, a second dielectric liner material1046may be formed (e.g., conformally formed) on or over exposed surfaces of the second P-type pillar structures1032, the second N-type pillar structures1034, the first dielectric liner structures1033(if any), the first isolation structures1035, the shared gate electrodes1042, and the non-shared gate electrodes1044; and a second dielectric material1048may be formed on or over exposed surfaces of the second dielectric liner material1046. As shown inFIG. 22A, the second dielectric liner material1046and the second dielectric material1048may substantially fill remaining portions of the second linear openings1036(FIG. 21A) and the third linear openings1037(FIG. 21A), such as portions of the second linear openings1036(FIG. 21A) and the third linear openings1037(FIG. 21A) unoccupied by the shared gate electrodes1042and non-shared gate electrodes1044. For example, the second dielectric liner material1046may substantially fill remaining portions of the second linear openings1036(FIG. 21A) overlying the shared gate electrodes1042, and may partially fill remaining portions of the third linear openings1037(FIG. 21A) overlying and laterally adjacent the non-shared gate electrodes1044; and the second dielectric material1048may substantially fill further remaining portions of the third linear openings1037(FIG. 21A) unoccupied by the non-shared gate electrodes1044and the second dielectric liner material1046.FIG. 22Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 22A, wherein the second dielectric material1048is depicted as transparent to show the other components of the TFT CMOS control logic device structure1000provided thereunder.

The second dielectric liner material1046may be formed of and include at least one dielectric material, such as one or more of an dielectric oxide material (e.g., silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide, a combination thereof), a dielectric nitride material (e.g., SiN), a dielectric oxynitride material (e.g., SiON), a dielectric carbonitride material (e.g., SiCN), and a dielectric carboxynitride material (e.g., SiOCN). The dielectric material of the second dielectric liner material1046may be the same as or different than that of one or more of the first linear isolation structures1022, and the first linear dielectric liner structures1024(if any). In some embodiments, the second dielectric liner material1046comprises a silicon oxide (e.g., silicon dioxide). In addition, the second dielectric liner material1046may be formed to exhibit any desirable thickness. By way of non-limiting example, a thickness of the second dielectric liner material1046may be less than or equal to about 120 Å, less than or equal to about 50 Å, less than or equal to about 25 Å, or less than or equal to about 10 Å. In some embodiments, the thickness of the second dielectric liner material1046is within a range of from about 30 Å to about 120 Å. The thickness of the second dielectric liner material1046may be substantially uniform, or at least one region of the second dielectric liner material1046may have a different thickness than at least one other region of the second dielectric liner material1046.

The second dielectric material1048may be formed of and include a dielectric material, such as one or more of an dielectric oxide material (e.g., silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide, a combination thereof), a dielectric nitride material (e.g., SiN), a dielectric oxynitride material (e.g., SiON), a dielectric carbonitride material (e.g., SiCN), and a dielectric carboxynitride material (e.g., SiOCN). The dielectric material of the second dielectric material1048may be the same as or different than that of one or more of the first linear isolation structures1022, the first linear dielectric liner structures1024(if any), and the second dielectric liner material1046. In some embodiments, the second dielectric material1048comprises a silicon oxide (e.g., silicon dioxide). As shown inFIG. 22A, the second dielectric material1048may exhibit a substantially planar upper surface. In additional embodiments, the second dielectric material1048may exhibit a non-planar upper surface defined by elevated regions and recessed regions.

The second dielectric liner material1046and the second dielectric material1048may be formed using conventional processes (e.g., conventional deposition processes) and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, the second dielectric liner material1046may be formed (e.g., through one or more of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD) on exposed surfaces of the second P-type pillar structures1032, the second N-type pillar structures1034, the first dielectric liner structures1033(if any), the first isolation structures1035, the shared gate electrodes1042, and the non-shared gate electrodes1044; and then the second dielectric material1048may be formed (e.g., through one or more of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD) on exposed surfaces of the second dielectric liner material1046.

Referring next toFIG. 23A, portions of at least the second dielectric liner material1046(FIG. 22A) and the second dielectric material1048(FIG. 22A) may be removed to form second linear dielectric liner structures1050and second linear isolation structures1052. In addition, as shown inFIG. 23A, portions of the gate dielectric material1038overlying upper surfaces of the second P-type pillar structures1032and the second N-type pillar structures1034may also be removed to facilitate subsequent electrical contact with the P-type pillar structures1032and the second N-type pillar structures1034. The second linear dielectric liner structures1050and the second linear isolation structures1052may be substantially confined within horizontal boundaries and vertical boundaries of the second linear openings1036(FIG. 21A) and the third linear openings1037(FIG. 21A). Accordingly, uppermost surfaces of the second linear dielectric liner structures1050and second linear isolation structures1052may be substantially coplanar with a plane shared by the upper surfaces of the second P-type pillar structures1032, the second N-type pillar structures1034, the first dielectric liner structures1033(if any), and the first isolation structures1035. As shown inFIG. 23A, in some embodiments, uppermost surfaces of the shared gate electrodes1042and the non-shared gate electrodes1044are covered by at least the second linear dielectric liner structures1050. In additional embodiments, uppermost surfaces of the shared gate electrodes1042and the non-shared gate electrodes1044are not covered by the second linear dielectric liner structures1050. Furthermore, as also shown inFIG. 23A, the second linear isolation structures1052(as well as some of the second linear dielectric liner structures1050(if any)) may laterally intervene (e.g., in the X-direction) between neighboring non-shared gate electrodes1044. The second linear isolation structures1052may electrically isolate the neighboring non-shared gate electrodes1044from one another.FIG. 23Bis a simplified plan view of the TFT CMOS control logic device structure1000at the process stage depicted inFIG. 23A.

The second linear dielectric liner structures1050and second linear isolation structures1052may be formed using conventional processes (e.g., conventional material removal processes, such as conventional etching processes and/or conventional CMP processes) and conventional processing equipment, which are not described in detail herein. For example, at least the second dielectric liner material1046(FIG. 22A) and the second dielectric material1048(FIG. 22A) may be subjected to at least one CMP process to at least remove portions of the second dielectric liner material1046(FIG. 22A) and the second dielectric material1048(FIG. 22A) outside of the second linear openings1036(FIG. 21A) and the third linear openings1037(FIG. 21A) and form the second linear dielectric liner structures1050and second linear isolation structures1052. The CMP process may expose drain regions of the second P-type pillar structures1032(e.g., upper p+regions) and the second N-type pillar structures1034(e.g., upper n+regions). Optionally, the CMP process may also remove upper portions of one or more of the second P-type pillar structures1032, the second N-type pillar structures1034, the first dielectric liner structures1033(if any), and the first isolation structures1035.

Following the formation of the second linear dielectric liner structures1050and second linear isolation structures1052, the TFT CMOS control logic device structure1000may be subjected to additional processing to form a TFT CMOS control logic device. By way of non-limiting example, the TFT CMOS control logic device structure1000may subsequently be subjected to additional processing to form one or more of contacts (e.g., source side contacts, drain side contacts, gate contacts), interconnects, and routing structures. Such additional processing may be conventional, and is not described in detail herein.

Thus, in accordance with embodiments of the disclosure, a method of forming a control logic device comprises forming N-type line structures extending over a substrate in a first lateral direction. P-type line structures extending over the substrate in the first lateral direction and intervening between the N-type line structures in a second lateral direction perpendicular to the first lateral direction are formed. Portions of the N-type line structures and the P-type line structures are removed to form first N-type pillar structures, first P-type pillar structures, and first linear trenches extending over the substrate in the second lateral direction. First linear isolation structures are formed within the first linear trenches. Portions of the first N-type pillar structures, the first P-type pillar structures, and the first linear isolation structures are removed to form second N-type pillar structures, second P-type pillar structures, first isolation structures, and second linear trenches extending over the substrate in the first lateral direction. Gate electrodes are formed in the second linear trenches, some of the second linear trenches including only one of the gate electrodes and other of the second linear trenches including more than one of the gate electrodes. Second linear isolation structures are formed in portions of the second linear trenches remaining after forming the gate electrodes.

Semiconductor devices (e.g., the semiconductor device100previous described with reference toFIG. 1) including semiconductor device structures (e.g., the stack structure103and the base control logic structure102previous described with reference toFIG. 1) in accordance with embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure. For example,FIG. 24is a block diagram of an illustrative electronic system2400according to embodiments of disclosure. The electronic system2400may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPad® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system2400includes at least one memory device2402. The at least one memory device2402may include, for example, an embodiment of a semiconductor device previously described herein (e.g., semiconductor device100previously previous described with reference toFIG. 1), wherein different decks (e.g., the decks104) of a stack structure (e.g., the stack structure102) of the semiconductor device each include a control logic level (e.g., the TFT control logic level200previously described with reference toFIG. 2) comprising an assembly of control logic devices, at least one of the control logic devices including at least one device (e.g., a TFT CMOS device) exhibiting one or more gate electrodes shared by neighboring vertical transistors thereof. The electronic system2400may further include at least one electronic signal processor device2404(often referred to as a “microprocessor”). The electronic signal processor device2404may, optionally, include an embodiment of a semiconductor device previously described herein (e.g., semiconductor device100previously previous described with reference toFIG. 1). The electronic system2400may further include one or more input devices2406for inputting information into the electronic system2400by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system2400may further include one or more output devices2408for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device2406and the output device2408may comprise a single touchscreen device that can be used both to input information to the electronic system2400and to output visual information to a user. The one or more input devices2406and output devices2408may communicate electrically with at least one of the memory device2402and the electronic signal processor device2404.

Thus, in accordance with embodiments of the disclosure, an electronic system comprises a semiconductor device comprising a stack structure. The stack structure comprises decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof.

The devices, structures, systems, and methods of the disclosure advantageously facilitate improved semiconductor device performance, reduced costs (e.g., manufacturing costs, material costs), increased miniaturization of components, and greater packaging density as compared to conventional devices, conventional structures, conventional systems, and conventional methods. The devices, structures, systems, and methods of the disclosure may also improve performance, scalability, efficiency, and simplicity as compared to conventional device, conventional structures, conventional systems, and conventional methods.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalents.