Image sensor having multiple sensing layers

An image sensor includes a first sensor layer having a first array of pixels and a second sensor layer having a second array of pixels. Each pixel of the first and second arrays has a photodetector for collecting charge in response to incident light, a charge-to-voltage conversion mechanism, and a transfer gate for selectively transferring charge from the photodetector to the charge-to-voltage mechanism. The first and second sensor layers each have a thicknesses to collect light with a first and second preselected ranges of wavelengths, respectively. A circuit layer is situated below the first sensor layer and has support circuitry for the pixels of the first and second sensor layers, and interlayer connectors are between the pixels of the first and second layers and the support circuitry.

FIELD OF THE INVENTION

The invention relates generally to the field of image sensors, and more particularly to a stacked image sensor construction.

BACKGROUND OF THE INVENTION

A typical Complementary Metal Oxide Semiconductor (CMOS) image sensor has an image sensing portion that includes a photodiode for collecting charge in response to incident light and a transfer gate for transferring charge from the photodiode to a charge-to-voltage conversion mechanism, such as a floating diffusion. Usually, the sensing portion is fabricated within the same material layer and with similar processes as the control circuitry for the image sensor. In an effort to increase the number of pixels provided in an image sensor, pixel size has been decreasing.

However, as the pixel size shrinks, the illuminated area of the photodetector is also typically reduced, in turn decreasing the captured signal level and degrading performance.

Thus, a need exists for an improved image sensor structure.

SUMMARY OF THE INVENTION

An image sensor includes a first sensor layer having a first array of pixels. Each pixel of the first array has a photodetector for collecting charge in response to incident light, a charge-to-voltage conversion mechanism, and a transfer gate for selectively transferring charge from the photodetector to the charge-to-voltage mechanism. The first sensor layer has a thickness to collect light with a first preselected range of wavelengths. A second sensor is layer situated over the first sensor layer, and has a second array of pixels. Each pixel includes a photodetector for collecting charge in response to incident light, a charge-to-voltage conversion, and a transfer gate for selectively transferring charge from the photodetector to the charge-to-voltage mechanism. The second sensor layer has a thickness to collect light with a second preselected range of wavelengths. A circuit layer is situated below the first sensor layer and has support circuitry for the pixels of the first and second sensor layers, and interlayer connectors are between the pixels of the first and second layers and the support circuitry.

The present invention has the advantage of providing an improved image sensor structure.

DETAILED DESCRIPTION OF THE INVENTION

Turning now toFIG. 1, a block diagram of an image capture device shown as a digital camera embodying aspects of the present disclosure is illustrated. Although a digital camera is illustrated and described, the present invention is clearly applicable to other types of image capture devices. In the disclosed camera, light10from a subject scene is input to an imaging stage11, where the light is focused by a lens12to form an image on an image sensor20. The image sensor20converts the incident light to an electrical signal for each picture element (pixel). In some embodiments, the image sensor20is an active pixel sensor (APS) type (APS devices are often referred to as CMOS sensors because of the ability to fabricate them in a Complementary Metal Oxide Semiconductor process).

The amount of light reaching the sensor20is regulated by an iris block14that varies the aperture and the neutral density (ND) filter block13that includes one or more ND filters interposed in the optical path. Also regulating the overall light level is the time that the shutter block18is open. The exposure controller block40responds to the amount of light available in the scene as metered by the brightness sensor block16and controls all three of these regulating functions.

This description of a particular camera configuration will be familiar to one skilled in the art, and it will be apparent to such a skilled person that many variations and additional features are present. For example, an autofocus system is added, or the lens is detachable and interchangeable. It will be understood that the present disclosure applies to various types of digital cameras where similar functionality is provided by alternative components. For example, the digital camera is a relatively simple point and shoot digital camera, where the shutter18is a relatively simple movable blade shutter, or the like, instead of the more complicated focal plane arrangement. Aspects of the present invention can also be practiced on imaging components included in non-camera devices such as mobile phones and automotive vehicles.

An analog signal from the image sensor20is processed by an analog signal processor22and applied to an analog to digital (A/D) converter24. A timing generator26produces various clocking signals to select rows and pixels and synchronizes the operation of the analog signal processor22and the A/D converter24. The image sensor stage28includes the image sensor20, the analog signal processor22, the A/D converter24, and the timing generator26. The components of the image sensor stage28can be separately fabricated integrated circuits, or they could be fabricated as a single integrated circuit as is commonly done with CMOS image sensors. The resulting stream of digital pixel values from the A/D converter24is stored in a memory32associated with the digital signal processor (DSP)36.

The digital signal processor36is one of three processors or controllers in the illustrated embodiment, in addition to a system controller50and an exposure controller40. Although this partitioning of camera functional control among multiple controllers and processors is typical, these controllers or processors are combined in various ways without affecting the functional operation of the camera and the application of the present invention. These controllers or processors can comprise one or more digital signal processor devices, microcontrollers, programmable logic devices, or other digital logic circuits. Although a combination of such controllers or processors has been described, it should be apparent that one controller or processor can be designated to perform all of the needed functions. All of these variations can perform the same function and fall within the scope of this invention, and the term “processing stage” will be used as needed to encompass all of this functionality within one phrase, for example, as in processing stage38inFIG. 1.

In the illustrated embodiment, the DSP36manipulates the digital image data in its memory32according to a software program permanently stored in program memory54and copied to the memory32for execution during image capture. The DSP36executes the software necessary for practicing image processing. The memory32includes of any type of random access memory, such as SDRAM. A bus30comprising a pathway for address and data signals connects the DSP36to its related memory32, A/D converter24and other related devices.

The system controller50controls the overall operation of the camera based on a software program stored in the program memory54, which can include Flash EEPROM or other nonvolatile memory. This memory can also be used to store image sensor calibration data, user setting selections and other data which must be preserved when the camera is turned off. The system controller50controls the sequence of image capture by directing the exposure controller40to operate the lens12, ND filter13, iris14, and shutter18as previously described, directing the timing generator26to operate the image sensor20and associated elements, and directing the DSP36to process the captured image data. After an image is captured and processed, the final image file stored in memory32is transferred to a host computer via an interface57, stored on a removable memory card64or other storage device, and displayed for the user on an image display88.

A bus52includes a pathway for address, data and control signals, and connects the system controller50to the DSP36, program memory54, system memory56, host interface57, memory card interface60and other related devices. The host interface57provides a high speed connection to a personal computer (PC) or other host computer for transfer of image data for display, storage, manipulation or printing. This interface is an IEEE1394 or USB2.0 serial interface or any other suitable digital interface The memory card64is typically a Compact Flash (CF) card inserted into a socket62and connected to the system controller50via a memory card interface60. Other types of storage that are utilized include, for example, PC-Cards, MultiMedia Cards (MMC), or Secure Digital (SD) cards.

Processed images are copied to a display buffer in the system memory56and continuously read out via a video encoder80to produce a video signal. This signal is output directly from the camera for display on an external monitor, or processed by the display controller82and presented on an image display88. This display is typically an active matrix color liquid crystal display (LCD), although other types of displays are used as well.

The user interface, including all or any combination of viewfinder display70, exposure display72, status display76and image display88, and user inputs74, is controlled by a combination of software programs executed on the exposure controller40and the system controller50. User inputs74typically include some combination of buttons, rocker switches, joysticks, rotary dials or touchscreens. The exposure controller40operates light metering, exposure mode, autofocus and other exposure functions. The system controller50manages the graphical user interface (GUI) presented on one or more of the displays, for example, on the image display88. The GUI typically includes menus for making various option selections and review modes for examining captured images.

The exposure controller40accepts user inputs selecting exposure mode, lens aperture, exposure time (shutter speed), and exposure index or ISO speed rating and directs the lens and shutter accordingly for subsequent captures. The brightness sensor16is employed to measure the brightness of the scene and provide an exposure meter function for the user to refer to when manually setting the ISO speed rating, aperture and shutter speed. In this case, as the user changes one or more settings, the light meter indicator presented on viewfinder display70tells the user to what degree the image will be over or underexposed. In an automatic exposure mode, the user changes one setting and the exposure controller40automatically alters another setting to maintain correct exposure. For example, for a given ISO speed rating when the user reduces the lens aperture, the exposure controller40automatically increases the exposure time to maintain the same overall exposure.

The image sensor20shown inFIG. 1typically includes a two-dimensional array of light sensitive pixels fabricated on a silicon substrate that provide a way of converting incoming light at each pixel into an electrical signal that is measured. Referring toFIG. 2, portions of an embodiment of the image sensor20are conceptually illustrated.

InFIG. 2, the image sensor20is a Complementary Metal Oxide Semiconductor (CMOS) image sensor that includes a first sensor layer101having a first array of pixels111. A second sensor layer102is situated over the first sensor layer101, which has a second array of pixels112. A circuit layer120is situated below the first sensor layer101, with support circuitry122for the pixel arrays111,112of the first and second sensor layers101,102. Interlayer connectors130between the pixels111,112of the first and second layers101,102and the support circuitry122provide electrical connections between the respective layers. The first sensor layer101has a thickness T1to collect light with a first preselected range of wavelengths and the second sensor layer has a thickness T2to collect light with a second preselected range of wavelengths. Regular silicon wafers, silicon on insulator (SOI) wafers or silicon on sapphire (SOS) wafers are all suitable materials for manufacture of the sensor layers101,102.

FIG. 3is a block diagram conceptually portions of a pixel110of the pixel arrays111,112. The pixel110includes a photodetector, such as a photodiode140and a transfer mechanism, such as a transfer gate142. The photodetector140collects charge in response to incident light and the transfer gate142functions to transfer charge from the photodetector140to a charge-to-voltage mechanism, such as a floating diffusion sense node144, which receives the charge from the photodetector140and converts the charge to a voltage signal. As noted above, the pixels110are typically configured in arrays of rows and columns. A row select transistor is coupled to a column bus, and the readout of charge from the pixels110is accomplished by selecting the desired row of the array by activating the proper row select transistor, and the information is read out from the columns of the selected row.

In some embodiments, the pixels110of the first and second pixel arrays111,112are organized into pixel kernels150.FIGS. 4A and 4Billustrate examples of some pixel kernel configurations. InFIG. 4A, four photodiodes140share a common floating diffusion144via respective transfer gates142, and inFIG. 4B, two photodiodes140share a common floating diffusion144. In the embodiments illustrated inFIGS. 4A and 4B, the interlayer connectors130are coupled to the floating diffusions144of the pixel kernels150.

FIG. 5is a cross-section view showing further aspects of an embodiment of an image sensor having two sensor layers101,102and a circuit layer120. Each of the sensor layers101,102and the circuit layer120include a silicon portion152and one or more metal layers154. The support circuitry122of the circuit layer120includes a floating diffusion144corresponding to each pixel kernel150, and coupled to the corresponding pixel kernel by the interlayer connectors130. The structure illustrated inFIG. 5has an extra metal layer154(the metal layer corresponding to the transfer gate142) and the wafer interconnection130is done through the floating diffusions144. This allows binning the pixels onto the same floating diffusion144.

Among other things, the support circuitry122also includes a reset gate124, a voltage supply VDD, and a source follower input and output126,128for each pixel kernel150. In embodiment illustrated inFIG. 5, the interlayer connectors130electrically connect the respective floating diffusions nodes144on sensing layer T2, sensing layer T1, and the circuit wafer to form a collective floating diffusion144.

In general, reducing the thickness of the silicon portion152can result in optical interference, which in turn can degrade quantum efficiency. To mitigate this effect and improve quantum efficiency, antireflection coatings are used on both sides of each of the sensing layers and on top on the circuit layer in some embodiments. Such antireflection coatings are known, and are used, for example, for single layer structures such as ONO stacks (silicon oxide-silicon nitride-silicon oxide) or hafnium oxide-magnesium oxide stacks. Other suitable antireflection coatings could also be used. These antireflection coatings can be deposited using any typical deposition technique before the sensing and the circuit layer are bonded together.

FIG. 6illustrates another embodiment where the interlayer connections130are implemented by row and column interconnects, which connect the pixels111to the circuit layer120via row and column circuitry132. An extra two metal layers154are included and the wafer interconnections130are done through row and column interconnects placed at the periphery of the imager area. Thus, each output signal and timing line on the sensor layers are electrically coupled with the interconnects130to the column or row circuitry132on the circuit layer120. In the illustrated embodiments, standard CMOS digital and analog circuitry is situated outside the image area on sensor layers101,102and/or the circuit wafer120.

In the embodiments illustrated inFIGS. 5 and 6, a color filter array (CFA)160is situated over the top sensor layer102. The silicon portions152or the first and second sensor layers101,102have different thicknesses T1,T2so that each layer collects light with in a predetermined range of wavelengths. For instance, the thickness of the sensor layers can be about 0.5 μm to collect predominantly blue light, about 1.3 μm to collect predominantly green light, and/or about 3.0 μm to collect predominantly red light. By using the first and second thicknesses T1, T2set to collect two predetermined colors, the need for some layers of the CFA160are eliminated.

More specifically, the embodiments illustrated inFIGS. 5 and 6having two sensor layers101,102with layer thicknesses T1, T2eliminates the need for two of the layers of the CFA160.FIGS. 7 and 8illustrate examples of two complementary CFAs160, where Y stands for yellow, M stands for magenta and P stands for panchromatic. The silicon thickness T2of the top sensor layer102is about 2 μm in the illustrated embodiments.

The embodiments illustrated inFIGS. 9 and 10each include an additional sensor layer103. InFIG. 9, the interlayer connections130connect the floating diffusions144, and inFIG. 10, the interlayer connections130are made using the row and column circuitry132. InFIGS. 9 and 10, the silicon thickness T3of the third sensor layer is about 0.5 μm so that it collects predominantly blue light, the silicon thickness T2of the second sensor layer102is about 1.3 μm so that it collects predominantly green light, and the silicon thickness T1of the first sensor layer is about 3 μm so that it collects predominantly red light. Such a sensor does not require wavelength selective filters to detect color, which are known to decrease quantum efficiency.

This structure also allows multiple ways of binning pixels onto a common floating diffusion. Depending on the number of photodiodes140within each pixel kernel150, three or more photodiodes140can be connected to the same electrical interconnect130. This allows multiple ways of binning the pixels110. For example, as illustrated inFIG. 11, the transfer gates142for photodiodes B1, G1, and R1can be activated to transfer charge onto the common floating diffusion142and produce a binned panchromatic signal. Similarly, on a single color layer, transfer gates142for each photodiode110in the pixel kernel150can be activated to bin all of the color signals and produce a higher sensitivity output at lower spatial resolution. For example, binning all four of the red pixels R1+R2+R3+R4functions like a single large (high sensitivity) red pixel. The option also exists to sacrifice spatial resolution for color response in one color plane, but not others. For example, the four red pixels could be binned together, but individual photodiode data preserved in the green channel. Another option would be to bin all photodiodes (for example using all 12 photodiodes inFIG. 11(four blue pixels B1-B4, four green pixels G1-G4, and four red pixels R1-R4) onto the shared floating diffusion144. This would produce a high sensitivity, low spatial resolution panchromatic signal for the stacked kernel. Color separation in this case would be accomplished by preserving color separation in nearby kernels.

FIG. 12illustrates another embodiment that includes two sensor layers101,102and a circuit layer120that also contains sensing elements. This structure requires one less wafer as compared to the embodiments illustrated inFIGS. 9 and 10while still providing three sensor layers. Thus, the circuit layer120includes pixels110in addition to support circuitry. The silicon thickness T1,T2,T3circuit layer120and the two sensor layers101,102are such that each layer collects light with predetermined ranges of wavelengths. InFIG. 12, the interlayer connections130are made through the row and column circuitry132, though in similar embodiments the connections are made through the floating diffusions144.

FIG. 13illustrates an embodiment having one sensor layer101and a circuit layer120that also includes sensing elements. The embodiment illustrated inFIG. 113has interlayer connections130through the floating diffusions144, though the connections can alternatively be made through the row and column circuitry as disclosed in other embodiments herein. The sensor layer101and the circuit layer120each have silicon thicknesses T1,T2to layer collect light with predetermined ranges of wavelengths. As with the embodiments illustrated inFIGS. 5 and 6, a complementary CFA160such as illustrated inFIGS. 7 and 8is provided for filtering the third color.

FIG. 14conceptually illustrates another embodiment having more than three sensing layers101-N, with each layer having a predetermined thickness for collecting light having corresponding ranges of wavelengths. This structure allows the extension of sensitivity beyond the visible spectrum. The top three layers will be responsible for capturing the light in the visible frequency range as described, for example, in the embodiments illustrated inFIGS. 9 and 10, while the extra layers N may be used to capture infrared light

PARTS LIST