Poly-silicon thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display device

A poly-silicon thin film transistor and its manufacturing method, an array substrate and its manufacturing method, and a display device are provided. The method for manufacturing a poly-silicon thin film transistor includes forming a poly-silicon layer on a base substrate so that the poly-silicon layer includes a first poly-silicon area, second poly-silicon areas located at the both sides of the first poly-silicon area and third poly-silicon areas located at a side of the second poly-silicon areas away from the first poly-silicon area; forming a barrier layer between a gate electrode and a gate insulation layer by a dry etching method so that the barrier layer corresponds to the first poly-silicon area; and with the barrier layer as a mask doping the second poly-silicon areas to form lightly doped areas. By this method, the lightly doped areas may have the same length, and thus the problem of excessive leakage current is avoided.

TECHNICAL FIELD

At least one embodiment of the present invention relates to a poly-silicon thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device.

BACKGROUND

A low temperature poly-silicon thin film transistor (LTPS-TFT) display has advantages such as high resolution, quick response, high brightness, high aperture ratio, and so on. LTPS has high electron mobility due to its characteristics. In addition, peripheral driving circuits can be prepared on a glass substrate at the same time, realizing system integration, saving space and costs for driving ICs, and reducing the product defect rate.

Currently, the method for manufacturing a low temperature poly-silicon thin film field effect transistor includes the following steps:

S101, as shown inFIG. 1, forming a poly-silicon layer20on a base substrate10. The poly-silicon layer20includes a first poly-silicon area201, second poly-silicon areas located at the both sides of the first poly-silicon area201, and third poly-silicon areas203located at a side of each second poly-silicon area202away from the first poly-silicon area201.

S102, as shown inFIG. 2, subsequently forming a gate insulation layer30, a gate metal film and a photoresist film on the base substrate on which the poly-silicon layer20has been formed, exposing and developing the photoresist film to obtain a photoresist fully retained portion401, a photoresist half retained portion402and a photoresist fully removed portion. The photoresist fully retained portion401corresponds to the first poly-silicon area201, the photoresist half retained portion402corresponds to the second poly-silicon areas202, and the photoresist fully removed portion corresponds to the rest areas. The gate metal film on the photoresist fully removed portion is removed by a wet etching method, so as to obtain the gate metal film50acorresponding to the photoresist fully retained portion401and the photoresist half retained portion402.

S103, as shown inFIG. 3, with the photoresist fully retained portion401and the photoresist half retained portion402as a mask, performing N+ doping into the exposed third poly-silicon areas203to form heavily doped areas203a.

S104, as shown inFIG. 4, removing the photoresist in the photoresist half retained portion402by an ashing process, and performing wet etching with respect to the exposed gate metal film to form a gate electrode50.

S105, as shown inFIG. 5, with the gate electrode50as a mask, performing light doping into the exposed second poly-silicon areas202to form lightly doped areas202a. In the case shown inFIG. 5, the first poly-silicon area201, the lightly doped areas202a, the heavily doped areas203aconstruct an active layer20a.

S106, as shown inFIG. 6, forming a protection layer60as well as a source electrode701, a drain electrode702, etc. on the base substrate on which the above steps have been completed.

SUMMARY

At least one embodiment of the present invention provides a poly-silicon thin film transistor and its manufacturing method, an array substrate and its manufacturing method, and a display device, by which the lightly doped areas located at the both sides of the first poly-silicon area can have the same length, the problem of excessive leakage current incurred by inconsistent lightly doped areas can be avoided.

In one aspect, at least one embodiment of the present invention provides a method for manufacturing a poly-silicon thin film transistor, the method includes: forming an active layer on a base substrate, and a gate insulation layer and a gate electrode above the active layer so that the active layer includes a first poly-silicon area, light doping areas located at the both sides of the poly-silicon area, and heavily doped areas located at a side of the lightly doped area away from the first poly-silicon area. Forming the lightly doped areas of the active layer includes: forming a poly-silicon layer on the base substrate so that the poly-silicon layer includes the first poly-silicon area, second poly-silicon areas located at the both sides of the first poly-silicon area, and third poly-silicon areas located at a side of the second poly-silicon areas away from the first poly-silicon area; forming a barrier layer between the gate electrode and the gate insulation layer by a dry etching method so that the barrier layer corresponds to the first poly-silicon area; and doping the second poly-silicon areas with the barrier layer covering the first poly-silicon area as a mask to form the lightly doped areas.

In another aspect, at least one embodiment of the present invention provides a method for manufacturing an array substrate, and the method includes forming a thin film transistor on a base substrate. The thin film transistor is made by using the above method for manufacturing a poly-silicon thin film transistor.

In still another aspect, at least one embodiment of the present invention provides a poly-silicon thin film transistor, the poly-silicon thin film transistor includes a base substrate, an active layer provided on the base substrate, and a gate insulation and a gate electrode provided above the active layer. The active layer includes a first poly-silicon area, lightly doped areas provided at the both sides of the first poly-silicon area, and heavily doped areas provided at a side of the lightly doped areas away from the first poly-silicon area. The poly-silicon thin film transistor further includes a barrier layer provided between the gate insulation layer and the gate electrode and corresponding to the first poly-silicon area.

In still another aspect, at least one embodiment of the present invention provides an array substrate including the above poly-silicon thin film transistor and a pixel electrode.

In still another aspect, at least one embodiment of the present invention provides a display device including the above poly-silicon thin film transistor or the above array substrate.

DESCRIPTION OF THE REFERENCE NUMERALS

DETAILED DESCRIPTION

The inventors of the present application have noted that in the manufacturing method as shown inFIG. 1toFIG. 6, before performing lightly doping, it is necessary to remove the photoresist in the photoresist half retained portion402by an ashing process, and it is necessary to perform wet etching onto the exposed gate metal film. The wet etching and the ashing processes are both isotropic, and thus after forming the gate electrode50and performing the lightly doping with the gate electrode50as a mask, it is possible to cause the lightly doped areas located at the both sides of the first poly-silicon area201have different lengths, and thus it is possible to cause excessive leakage current, and hence influence the performance of the resultant thin film transistor.

At least one embodiment of the present invention provides a method for manufacturing a poly-silicon thin film transistor, the method includes: forming an active layer on a base substrate, and a gate insulation layer, a gate electrode, a source electrode and a drain electrode that are located above the active layer. The active layer includes a first poly-silicon area, lightly doped areas located at the both sides of the first poly-silicon area, heavily doped areas located at a side of the lightly doped areas away from the first poly-silicon area. The method further includes forming a barrier layer between the gate electrode and the gate insulation layer by a dry etching method so that the barrier layer corresponds to the first poly-silicon area.

In one embodiment, forming of the lightly doped areas of the active layer includes: forming a poly-silicon layer on the base substrate so that the poly-silicon layer includes a first poly-silicon area, second poly-silicon areas located at the both sides of the first poly-silicon area, and third poly-silicon areas located at a side of the second poly-silicon areas away from the first poly-silicon area; doping the second poly-silicon areas with the barrier layer covering the first poly-silicon area as a mask to form the lightly doped areas.

It is noted that firstly, the heavily doped area may be an N type heavily doped area, and in this case, for example, boron ions are doped. Of course, the heavily doped area may also be a P type heavily doped area, and in this case, for example, phosphorus ions are doped.

Secondly, in selecting the material for the barrier layer, selection ratio of it to an underlying material, e.g., the material of the gate insulation layer in the embodiment of the present invention, should be taken into consideration. That is to say, when the pattern of the barrier layer is formed by a dry etching method, it will not influence the underlying gate insulation layer. It is preferred to use the dry etching method because compared with a wet etching method, by a dry etching method, the side wall profile of the barrier layer can be well controlled, and thus the problem that the resultant lightly doped areas have inconsistent length caused by the laterally indentation of the side profile at both sides of the barrier layer can be avoided.

Thirdly, the barrier layer corresponding to the first poly-silicon area means that the barrier layer is fully overlapped with the poly-silicon area along the direction perpendicular to the base substrate.

Fourthly, there is no limitation on the sequence for forming the heavily doped areas, as long as the third poly-silicon areas can be formed into the heavily doped areas by the doping process.

Fifthly, the above doping process may be an ion injection process or diffusion process. Since the ion injection process has advantages such as being able to dope various kinds of impurities into different semiconductors at a relatively low temperature, precisely controlling the concentration distribution and injection depth of doped ions, achieving evenly doping over a large area, and so on; in one embodiment, the doping process is an ion injection process.

Sixthly, all the accompanying drawings in the present application only schematically depict the pattern layers related to the subject matter of the present invention, and will not show or only partially show the pattern layers unrelated with the subject matter of the present invention.

An embodiment of the present invention provides a method for manufacturing a poly-silicon thin film transistor, and the method includes forming an active layer on a base substrate and a gate insulation layer, a gate electrode, a source electrode and a drain electrode above the active layer. The active layer includes a first poly-silicon area, lightly doped areas located at the both sides of the first poly-silicon area, and heavily doped areas located at a side of the lightly doped areas away from the first poly-silicon area. The method further includes: forming a barrier layer corresponding to the first poly-silicon area between the gate electrode and the gate insulation layer. In one embodiment, forming the lightly doped areas of the active layer includes: forming a poly-silicon layer on the base substrate, wherein the poly-silicon layer includes a first poly-silicon area, second poly-silicon areas located at the both sides of the first poly-silicon area, third poly-silicon areas located at a side of the second poly-silicon areas away from the first poly-silicon area; doping the second poly-silicon areas with the barrier layer covering the first poly-silicon area as a mask to form the lightly doped areas.

In the embodiment of the present invention, since the barrier layer corresponding to the first poly-silicon area is formed by a dry etching method, and by the dry etching method, the side wall profile of the barrier layer can be well controlled, that is to say, the side walls at both sides of the barrier layer can be controlled to be perpendicular to the base substrate; in this way, after doping the second poly-silicon areas with the barrier layer as a mask, the resultant lightly doped areas can have the same length, and thus the problem of excessive leakage current incurred by inconsistent lengths of the lightly doped areas can be avoided, and hence the influence on the performance of the thin film transistor can be avoided.

Considering the material for the gate insulation layer is generally silicon nitride, silicon oxide, or the like, in order to avoid influencing the gate insulation layer and even the poly-silicon layer upon forming the barrier layer, in a different embodiment, the material for the barrier layer may be an oxide, e.g., a metal oxide, such as Al2O3, or non-metal oxide, such as SiO2, and so on.

In one embodiment, forming of the heavily doped areas can be performed by doping the third poly-silicon areas with a film layer covering the first poly-silicon area and the second poly-silicon area as a mask before the lightly doped areas are formed.

It is noted that the film layer covering the first poly-silicon area and the second poly-silicon areas will not be limited herein, it can be a photoresist film layer separately formed above the gate insulation layer, or it can also be a photoresist film layer located on a gate metal film during the gate electrode is formed, there is no limitation herein.

Thereby, forming of the heavily doped areas, e.g., can be performed by the following method, that is, on the base substrate on which the poly-silicon layer and the gate insulation layer have been formed, a first photoresist pattern is formed to cover the first poly-silicon area and the second poly-silicon areas, and with the first photoresist pattern as a mask, the third poly-silicon areas are doped to form the heavily doped areas.

Base on the above, in an embodiment, the barrier layer corresponding to the first poly-silicon area can be formed on the gate insulation layer by a dry etching method, and with the barrier layer as a mask, the second poly-silicon areas are doped to form the lightly doped areas.

In a different embodiment, doping of the second poly-silicon areas can be performed after the barrier layer is formed and before the gate electrode located above the barrier layer is formed, or may also be formed after the gate electrode located above the barrier layer is formed.

Based on the above embodiment, forming of the poly-silicon thin film transistor, for example, can be achieved by the steps as follows:

S201, depositing a silicon film on the base substrate10, performing a process of poly-crystallization to form a poly-silicon film, and by a patterning process, to form the poly-silicon layer20, as shown inFIG. 7.

In one embodiment, the poly-silicon layer20includes the first poly-silicon area201, the second poly-silicon areas202located at the both sides of the first poly-silicon area201, and the third poly-silicon areas203located at a side of the second poly-silicon areas away from the first poly-silicon area201.

In one embodiment, forming of the poly-silicon film may include: depositing a layer of amorphous silicon film on the base substrate10by plasma enhanced chemical vapor deposition (PECVD). For example, the amorphous silicon film is subjected to a dehydrogenation process by using a high temperature oven to prevent a hydrogen exploration phenomenon during the crystallization process and to prevent the defect state density inside the film after the crystallization from reducing. After the dehydrogenation process is completed, a low temperature poly-silicon (LTPS) process is performed, for example, the amorphous silicon film is subjected to a crystallization process with an excimer laser annealing (ELA) process, a metal-induced crystallization (MIC) process or a solid phase crystallization (SPC) process, and so on, to form the poly-silicon film on the base substrate. The thickness of the poly-silicon film may be e.g., 300 Å˜500 Å.

S202, as shown inFIG. 7, on the basis of the step S201, forming the gate insulation layer30, and forming the first photoresist pattern403covering the first poly-silicon area201and the second poly-silicon areas202on the gate insulation layer30.

Considering that the thickness of the gate insulation30will influence the energy required for ion injection in the subsequent process, in the present step, the thickness of the gate insulation layer30may be 700 Å·1100 Å.

For example, the gate insulation layer30may include SiO2 with a thickness of 400 Å˜600 Å and SiNx with a thickness of 300 Å˜500 Å on it.

S203, as shown inFIG. 8, on the basis of step202, with the first photoresist pattern403as a mask, doping the third poly-silicon areas203, to form the heavily doped areas203a, and removing the first photoresist pattern403.

In one embodiment, the heavily doped areas203amay be an N-type, and the doped ions e.g., are boron ions.

S204, on the basis of step S203, sequentially forming a barrier layer film and a photoresist film, exposing and developing the photoresist film formed on the base substrate by using a normal mask plate to form a photoresist fully retained portion and a photoresist fully removed portion. The photoresist fully retained portion corresponds to the first poly-silicon area201, and the photoresist fully removed portion corresponds to the remaining portion. The barrier layer film in the photoresist fully removed portion is removed by a dry etching method, to form the barrier layer80corresponding to the first poly-silicon area201, as shown inFIG. 9.

The material for the barrier layer80for example is SiO2, and the thickness thereof is 200 Å˜400 Å.

S205, as shown inFIG. 10, on the basis of the step S204, doping the second poly-silicon areas202with the barrier layer80as a mask to form the lightly doped areas202a. Here, by forming the lightly doped areas202a, the leakage current can be suppressed. The first poly-silicon area201, the lightly doped areas202a, and the heavily doped areas203aform the active layer20a.

S206, as shown inFIG. 11, on the basis of the step S205, forming the gate electrode50. The material for the gate electrode50for example may be Mo, AL/Mo, Cu, and so on, and the thickness thereof may be 2200 Å˜3400 Å.

S207, as shown inFIG. 12, on the basis of the step S206, forming the protection layer60as well as the source electrode701and the drain electrode702. The source electrode701and the drain electrode702contact the heavily doped areas203athrough via holes formed in the protection layer60and the gate insulation layer30.

The protection layer60for example may include SiO2having the thickness of 1500 Å˜2500 Å and SiNx having the thickness of 2500 Å˜3500 Å.

The material for the source electrode701and the drain electrode702for example may be Mo, Mo/Al/Mo, Cu, and so on, and the thickness thereof may be 2200 Å˜3800 Å.

Of course, after the above steps S201to S204and before the step S207, the lightly doped areas202aand the gate electrode50may also be fonned according to the steps as follows:

S208, on the basis of the step S204, forming the gate electrode50on the barrier layer80.

S209, on the basis of the step S208, with the barrier layer80as a mask, doping the second poly-silicon areas202to form the lightly doped areas202a.

In one embodiment, forming of the above mentioned poly-silicon thin film transistor for example may be conducted by the steps as follows.

S301, as shown inFIG. 13, on the basis of the step S201, forming the gate insulation layer30.

S302, on the basis of the step S301, sequentially forming the barrier layer and a photoresist film, exposing the photoresist film formed on the base substrate by using a normal mask plate to form the photoresist fully retained portion and the photoresist fully removed portion after development. The photoresist fully retained portion corresponds to the first poly-silicon area201, and the photoresist fully removed portion corresponds to the remaining portion. The barrier layer film in the photoresist fully removed portion is removed by a dry etching method, to form the barrier layer80corresponding to the first poly-silicon area201, as shown inFIG. 13.

S303, as shown inFIG. 14, on the basis of the step S302, sequentially forming the gate metal film and a photoresist film, exposing the photoresist film formed on the base substrate by using a half tone mask or a grey tone mask, to form the photoresist fully retained portion401, the photoresist fully removed portion and a photoresist half retained portion402after development. The photoresist fully retained portion401corresponds to the first poly-silicon area201, and the photoresist half retained portion402corresponds to the second poly-silicon areas202. The photoresist fully retained portion401and the photoresist half retained portion402constitute a second photoresist pattern403′, and the gate metal film located below the second photoresist pattern403′ constitutes a gate metal pattern50′.

S304, as shown inFIG. 15, on the basis of the step303, with the second photoresist pattern as a mask, doping the third poly-silicon areas203to form the heavily doped areas203a.

S305, as shown inFIG. 16, on the basis of the step S304, removing the photoresist in the photoresist half retained portion402by an ashing process and removing the exposed gate metal film by a wet etching process, to form the gate electrode50.

S306, referring toFIG. 11, on the basis of the step S305, with the barrier layer80below the gate electrode50as a mask, doping the second poly-silicon areas202to form the lightly doped areas202a. The first poly-silicon area201, the lightly doped areas202aand the heavily doped areas203aconstitute the active layer20a. Herein, the photoresist fully retained portion401on the gate electrode50may be removed after the lightly doped areas202ahas been formed.

S307, referring toFIG. 12, on the basis of the step S306, forming the protection layer60as well as the source electrode701and the drain electrode702. The source electrode701and the drain electrode702contact with the heavily doped areas203athrough via holes formed in the protection layer60and the gate insulation layer30.

Based on the above, considering the glass base substrate may include damaging impurities, such as alkali metal ions, which will influence the performance of the poly-silicon layer, and therefore, as shown inFIG. 17, in one embodiment of the present invention, before forming the poly-silicon layer20, a buffer layer90is formed on the base substrate10.

At least one embodiment of the present invention further provides a method for manufacturing an array substrate, and the method includes forming a poly-silicon thin film transistor. The poly-silicon thin film transistor may be formed by any method provided by any one of the above embodiments. Thereby, the method may include the steps as follows:

S401, as shown inFIG. 18, on the basis of the step S207or S307, forming a planarization layer100, and forming a pixel electrode110electrically connected with the drain electrode702on the planarization layer100.

In a different embodiment, the material for the planarization layer100for example may be a photosensitive resin material or non-photosensitive resin material and may have a thickness of 1.5 μm to 5 μm. In addition, the planarization layer100may also reduce the parasite capacitance between the pixel electrode110and the source/drain electrode.

The material for the pixel electrode110may be ITO and may have a thickness of 400 Å˜700 Å.

Based on above, the method further includes:

S402, as shown inFIG. 19, on the basis of the above step S401, forming a passivation layer120, and forming a common electrode130on the passivation layer120.

An embodiment of the present invention provides a poly-silicon thin film transistor, as shown inFIG. 12. The poly-silicon thin film transistor includes a base substrate10, an active layer20aprovided on the base substrate10, a gate insulation layer30and a gate electrode50provided above the active layer20a, and a source electrode701and a drain electrode702provided above the gate electrode50. The active layer20aincludes a first poly-silicon area201, lightly doped areas202aprovided at the both sides of the first poly-silicon area, and heavily doped area203aprovided at a side of the lightly doped areas away from the first poly-silicon area. In one embodiment, the poly-silicon thin film transistor further includes a barrier layer80provided between the gate insulation layer30and the gate electrode50and corresponding to the first poly-silicon area201.

It is noted that firstly, the heavily doped area may be an N type heavily doped area, and in this case, for example, boron ions are doped.

Secondly, when selecting the material for the barrier layer80, it is necessary to consider the selection ratio of it to an underlying material, for example, the material for the gate insulation layer30in the embodiment of the present invention, that is, when forming the pattern for the barrier layer80by a dry etching method, no impact will be invoked with respect to for example the underlying gate insulation layer30.

An embodiment of the present invention provides a poly-silicon thin film transistor comprising a base substrate10, an active layer20aprovided on the base substrate10, a gate insulation layer30and a gate electrode50provided above the active layer20a, and a source electrode701and a drain electrode702provided above the gate electrode50. The active layer20aincludes a first poly-silicon area201, lightly doped areas202aprovided at the both sides of the first poly-silicon area, and heavily doped areas203aprovided at a side of the lightly doped areas away from the first poly-silicon area. In an embodiment, the poly-silicon thin film transistor further includes a barrier layer80provided between the gate insulation layer30and the gate electrode50and corresponding to the first poly-silicon area201.

Since the barrier layer80corresponding to the first poly-silicon area201is formed by a dry etching method, by which the sidewall profile of the barrier layer80can be well controlled, that is, the sidewalls at both sides of the barrier layer80can be controlled to be perpendicular to the base substrate10; in this way, after the second poly-silicon areas202are doped with the barrier layer80as a mask, the resultant lightly doped areas202amay have the same length, thus the problem of excessive leakage current incurred due to inconsistent lengths of the lightly doped areas202acan be avoided, and thus the influence on the performance of the thin film transistor can also be avoided.

Considering that the gate insulation layer generally employs the material such as silicon nitride, silicon oxide, and so on, in order to avoid influence on the gate insulation layer and even the poly-silicon layer when forming the barrier layer, in a different embodiment, the material for the barrier layer may be an oxide, for example, metal oxide, such as Al2O3, or non-metal oxide, such as SiO2, and so on.

In one embodiment, the barrier layer80may have a thickness of 200 Å˜400 Å.

In one embodiment, considering the glass base substrate may include damaging impurities, such as alkali metal ions, which will influence the performance of the poly-silicon layer, and therefore, as shown inFIG. 17, in an embodiment of the present invention, the thin film transistor may further include a buffer layer90provided on the upper surface of the base substrate10.

At least one embodiment of the present invention provides an array substrate, as shown inFIG. 18, the array substrate includes the above described poly-silicon thin film transistor and a pixel electrode110. Of course, the array substrate further includes gate lines, data lines, and so on, and will not further described in detail.

Thereby, as shown inFIG. 19, the array substrate may also include a common electrode130. For example, for an In-Plane Switch (IPS) array substrate, the pixel electrode110and the common electrode130are provided in the same layer at an interval, and both are stripe electrodes. For example, for an Advanced-super Dimensional Switching (ADS) array substrate, as shown inFIG. 19, the pixel electrode110and the common electrode130are provided at different layers, for example, the upper electrode is a stripe electrode and the lower electrode is a plate electrode.

Of course, the array substrate provided by an embodiment of the present invention is also suitable for an OLED display, it will not further described in detail.

At least one embodiment of the present invention also provides a display device comprising the poly-silicon thin film transistor as described in any one of the above embodiments or the array substrate as described in any one of the above embodiments. The display device may be any product or component having display function, such as mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, and so on. The implementation of the display device may be done with reference to the above poly-silicon thin film transistor embodiments and the above array substrate embodiments, and will not further described in any detail.

What has been described above is only the specific embodiment of the present invention, and the protection scope of the present invention will not be limited thereto. It is apparent to the person skilled in the art that various of modification and variation can be made to the present invention within the scope disclosed by the present invention, and the modification and variation should fall within the protection scope of the present invention. Thus, the protection scope of the present invention is defined only by the claims.

The present application claims the priority of Chinese Patent Application No. 201410171565.6 filed on Apr. 25, 2014, the Chinese Patent Application is entirely incorporated herein as a part of the present application by reference.