Ferro-electric memory device and method of manufacturing the same

A ferro-electric memory device includes a first ferro-electric capacitor which is selectively formed on a first insulating film and has a first lower electrode, a first ferro-electric film, and a first upper electrode, a first hydrogen barrier film which has first to third portions, the first portion being formed on the first insulating film, the second portion covering the side surfaces of the first lower electrode, first ferro-electric film, and first upper electrode, and the third portion being formed on the upper surface of the first upper electrode, a first interlayer formed on the second portion, and a second hydrogen barrier film which has fourth to sixth portions, the fourth portion having a first contact portion which comes into contact with at least part of the first portion, the fifth portion being formed on the first interlayer, and the sixth portion being formed on the third portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2004-077679, filed Mar. 18, 2004, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a ferro-electric memory device having a hydrogen barrier film and a method of manufacturing the same.

2. Description of the Related Art

In recent years, ferro-electric memory devices (FeRAM: Ferro-electric Random Access Memory) using a ferro-electric capacitor have received a great deal of attention as a kind of nonvolatile semiconductor memory.

FIG. 50is a sectional view of a conventional ferro-electric memory device. As shown inFIG. 50, in the conventional ferro-electric memory device, a MOSFET15having a gate electrode13and source/drain diffusion layers14aand14bis formed on a semiconductor substrate11. An interlayer dielectric film16is formed on the MOSFET15. A ferro-electric capacitor22is formed on the interlayer dielectric film16. The ferro-electric capacitor22includes a lower electrode18, ferro-electric film19, and upper electrode20. The upper electrode20is connected to a plate line (PL)30through a contact28. The lower electrode18is connected to one source/drain diffusion layer14aof the MOSFET15through a contact17a. A bit line (BL)34is connected to the other source/drain diffusion layer14bof the MOSFET15through contacts29and33. In this ferro-electric memory device, the ferro-electric capacitor22is covered with a hydrogen barrier film23to prevent invasion of hydrogen into the ferro-electric capacitor22.

However, the hydrogen barrier film23may deform by recrystallization in annealing after the ferro-electric capacitor22is processed or, deform by migration of the fence substance at a portion where a fence used in processing the ferro-electric capacitor22remains. Accordingly, the hydrogen barrier film23may have breaks. In this case, hydrogen invades from the contact29or the like near the ferro-electric capacitor22into it. The hydrogen invaded from breaks in the hydrogen barrier film23may degrade the capacitor characteristic.

A prior-art reference associated with the present invention is as follows.

BRIEF SUMMARY OF THE INVENTION

A ferro-electric memory device according to a first aspect of the present invention comprises a semiconductor substrate, a first transistor which is formed on the semiconductor substrate and has a first gate electrode, a first diffusion layer, and a second diffusion layer, a first insulating film which is formed on the semiconductor substrate and the first transistor, a first ferro-electric capacitor which is selectively formed on the first insulating film and has a first lower electrode, a first ferro-electric film, and a first upper electrode, a first hydrogen barrier film which has a first portion, a second portion, and a third portion, which are continuously formed, the first portion being formed on the first insulating film, the second portion covering a side surface of the first lower electrode, a side surface of the first ferro-electric film, and a side surface of the first upper electrode, and the third portion being formed on an upper surface of the first upper electrode, a first interlayer which is formed on the second portion, and a second hydrogen barrier film which has a fourth portion, a fifth portion, and a sixth portion, which are continuously formed, the fourth portion having a first contact portion which comes into contact with at least part of the first portion, the fifth portion being formed on the first interlayer, and the sixth portion being formed on the third portion.

A method of manufacturing a ferro-electric memory device according to a second aspect of the present invention comprises forming, on a semiconductor substrate, a first transistor which has a first gate electrode, a first diffusion layer, and a second diffusion layer, forming a first insulating film on the semiconductor substrate and the first transistor, forming, on the first insulating film, a first ferro-electric capacitor which has a first lower electrode, a first ferro-electric film, and a first upper electrode, forming a first hydrogen barrier film on the first ferro-electric capacitor and the first insulating film, forming a first interlayer on the first hydrogen barrier film on a side surface of the first ferro-electric capacitor, and forming a second hydrogen barrier film on the first interlayer and the first hydrogen barrier film and forming a first contact portion by bringing at least part of the first hydrogen barrier film and at least part of the second hydrogen barrier film into contact with each other on the first insulating film.

DETAILED DESCRIPTION OF THE INVENTION

The embodiments of the present invention will be described below with reference to the accompanying drawing. The same reference numerals denote the same parts throughout the drawing.

Ferro-electric memory devices according to the first and second embodiments are examples of COP type memory cells.

[1] First Embodiment

The first embodiment is a COP type memory cell, in which the upper electrode, ferro-electric film, and lower electrode in a ferro-electric capacitor are processed by using one mask.

[1—1] First Basic Example

FIG. 1is a schematic plan view of a ferro-electric memory device according to the first basic example of the first embodiment of the present invention.FIG. 2is a sectional view of the ferro-electric memory device taken along a line II—II inFIG. 1. The structure according to the first basic example of the first embodiment will be described below.

As shown inFIGS. 1 and 2, an element isolation region12which isolates an element region is formed in a semiconductor substrate11. A MOSFET15having a gate electrode13and source/drain diffusion layers14aand14bis formed in the element region. An interlayer dielectric film16is formed on the MOSFET15.

A ferro-electric capacitor22is formed on the interlayer dielectric film16. The ferro-electric capacitor22includes a lower electrode18, ferro-electric film19, and upper electrode20. The three layers including the lower electrode18, ferro-electric film19, and upper electrode20are processed for each cell by using one mask. For this reason, the side surfaces of the three layers are almost flush with each other. The three layers have planar sizes that become large downward or almost equal.

The ferro-electric capacitor22is covered with a first hydrogen barrier film23. The first hydrogen barrier film23has first, second, and third portions23a,23b, and23cwhich are continuously formed. The first portion23ais formed on the interlayer dielectric film16. The second portion23bcovers the side surfaces of the lower electrode18, ferro-electric film19, and upper electrode20. The third portion23cis formed on an insulting film21which is formed on the upper electrode20.

The first hydrogen barrier film23is covered with a second hydrogen barrier film25. The second hydrogen barrier film25has fourth, fifth, and sixth portions25a,25b, and25cwhich are continuously formed. The fourth portion25ais formed on the first portion23aof the first hydrogen barrier film23. The fifth portion25bis formed on an interlayer24which is formed on the second portion23bof the first hydrogen barrier film23. The sixth portion25cis formed on the third portion23cof the first hydrogen barrier film23.

The first and second hydrogen barrier films23and25come into contact with each other and therefore have a first contact portion and a second contact portion. The first contact portion is a region from the lower edge portion of the lower electrode18to the upper surface of the interlayer dielectric film16. At the first contact portion, the first portion23aand fourth portion25acome into contact with each other. The second contact portion is a region above the upper electrode20. At the second contact portion, the third portion23cand sixth portion25ccome into contact with each other. The first contact portion surrounds the ferro-electric capacitor22of each cell (FIG. 1).

The upper electrode20of the ferro-electric capacitor22is connected to a plate line (PL)30through a contact28. The lower electrode18of the ferro-electric capacitor22is connected to one source/drain diffusion layer14aof MOSFET15through a contact17. A bit line (BL)34is connected to the other source/drain diffusion layer14bof the MOSFET15through contacts29and33and an interconnection60.

The thickness of the second hydrogen barrier film25is preferably almost equal to or larger than that of the first hydrogen barrier film23. The interlayer24can be formed by using various materials such as an insulating material or conductive material. The interlayer24is preferably formed from an insulating material.

FIGS. 3 to 11are sectional views showing steps in manufacturing the ferro-electric memory device according to the first basic example of the first embodiment of the present invention. A manufacturing method according to the first basic example of the first embodiment will be described below.

First, as shown inFIG. 3, the element isolation region12having an STI (Shallow Trench Isolation) structure for element isolation is formed in the semiconductor substrate11. After that the gate electrode13is formed on the semiconductor substrate11. The source/drain diffusion layers14aand14bare formed on both sides of the gate electrode13. In this way, the MOSFET15is formed.

As shown inFIG. 4, the interlayer dielectric film16is deposited on the semiconductor substrate11and MOSFET15. The upper surface of the interlayer dielectric film16is planarized by, e.g., CMP (Chemical Mechanical Polishing). Examples of the material of the interlayer dielectric film16are BPSG (Boron Phosphorous Silicate Glass) and P-TEOS (Plasma-Tetra Ethoxy Silane). The contact17connected to the source/drain diffusion layer14ais formed in the interlayer dielectric film16.

As shown inFIG. 5, the lower electrode18, ferro-electric film19, upper electrode20, and insulting film21are sequentially deposited on the interlayer dielectric film16and contact17. The lower electrode18is made of a material containing, e.g., Ir, IrO2, Ru, RuO2, or Pt. Examples of the material of the ferro-electric film19are PZT and SBT. Examples of the material of the upper electrode20are Pt, Ir, IrO2, SRO, Ru, and RuO2.

As shown inFIG. 6, the insulting film21, upper electrode20, ferro-electric film19, and lower electrode18are patterned. With this process, the ferro-electric capacitor22is formed for each cell.

As shown inFIG. 7, the first hydrogen barrier film23having insulting properties is formed on the upper surface of the interlayer dielectric film16, the side surfaces of the ferro-electric capacitor22, and the upper and side surfaces of the insulting film21by sputtering or CVD (Chemical Vapor Deposition). Examples of the material of the first hydrogen barrier film23are Al2O3, SiN, SiON, TiO2, and PZT. The interlayer24is deposited on the first hydrogen barrier film23. Examples of the material of the interlayer24are P-TEOS, O3-TEOS, SOG, Al2O3, SiN, SiON, PZT, and SBT as insulating materials and TiAlN as a conductive material.

As shown inFIG. 8, the interlayer24is etched back until the first hydrogen barrier film23is exposed. The interlayer24remains only on the side surfaces of the first hydrogen barrier film23.

As shown inFIG. 9, the second hydrogen barrier film25is formed on the interlayer24and first hydrogen barrier film23. Accordingly, the first hydrogen barrier film23and second hydrogen barrier film25come into contact with each other near the lower edge portion of the lower electrode18and above the upper electrode20.

As shown inFIG. 10, an interlayer dielectric film26is deposited on the second hydrogen barrier film25. The upper surface of the interlayer dielectric film26is planarized. A contact hole27to which the upper electrode20is exposed is formed. After that, high-temperature annealing is executed, e.g., at 650° C. in an oxygen atmosphere for 1 hr to recover the damage of the ferro-electric capacitor22.

As shown inFIG. 11, the contact hole27is filled with a metal material containing, e.g., Ti, TiN, or W. The upper surface of the metal material is planarized. Accordingly, the contact28connected to the upper electrode20is formed. Next, the contact29connected to the source/drain diffusion layer14bis formed. To fill a contact hole such as the contact29having a high aspect ratio, it is filled with a metal material by using plasma CVD.

Next, as shown inFIG. 2, the plate line30and interconnection60, which are made of, e.g., W, Cu, Al, or TiN, are formed. Interlayer dielectric films31and32are formed. The contact33connected to the interconnection60is formed. After that, the bit line34connected to the contact33is formed. A ferro-electric memory device is thus formed.

According to the first basic example of the first embodiment of the present invention, the first portion23aof the first hydrogen barrier film23and the fourth portion25aof the second hydrogen barrier film25come into contact with each other between the ferro-electric capacitor22and the contact29near the lower edge portion of the lower electrode18. Hence, the first contact portion which surrounds the ferro-electric capacitor22is present. The first contact portion can prevent invasion of hydrogen from the contact29to the ferro-electric capacitor22through the interlayer24. For this reason, any degradation of the ferro-electric capacitor22can be prevented, and a highly reliable ferro-electric memory device can be provided.

The second portion23bof the first hydrogen barrier film23formed on the side surfaces of the ferro-electric capacitor22is covered with the interlayer24and the second hydrogen barrier film25formed on it. For this reason, even when the first hydrogen barrier film23is partially broken during the manufacturing process, the second hydrogen barrier film25can prevent invasion of hydrogen from the breaks of the first hydrogen barrier film23into the ferro-electric capacitor22.

[1-2] First Modification

In the first modification to the first embodiment, the contact29near the ferro-electric capacitor in the first basic example is formed from a plurality of contacts.

FIG. 12is a sectional view of a ferro-electric memory device according to the first modification to the first embodiment of the present invention. The structure according to the first modification to the first embodiment will be described below.

As shown inFIG. 12, the first modification to the first embodiment is different from the first basic example in that the contact located near the ferro-electric capacitor22is formed from, e.g., two contacts29-1and29-2. The contact29-1is formed simultaneously with the contact17. The contact29-2is formed after formation of the contact28.

According to the first modification to the first embodiment, the same effect as in the first basic example can be obtained. In addition, formation and filling of the contacts29-1and29-2are easier than in the first basic example.

[1-3] Second Modification

In the second modification to the first embodiment, the first contact portion in the first basic example is modified.

FIG. 13is a schematic plan view of a ferro-electric memory device according to the second modification to the first embodiment of the present invention.FIG. 14is a sectional view of the ferro-electric memory device taken along a line XIV—XIV inFIG. 13. The structure according to the second modification to the first embodiment will be described below.

As shown inFIGS. 13 and 14, the second modification to the first embodiment is different from the first basic example in that the first contact portion where the first portion23aof the first hydrogen barrier film23and the fourth portion25aof the second hydrogen barrier film25come into contact with each other has a smaller area.

That is, instead of bringing the first portion23aand fourth portion25ainto contact with each other all over the surfaces, as in the first basic example, only a boundary portion X between the fourth portion25aand the fifth portion25bof the second hydrogen barrier film25comes into contact with the first portion23aof the first hydrogen barrier film23at the lower edge portion of the lower electrode18. The interlayer24is present between the first portion23aand the fourth portion25a.

FIG. 15is a sectional view showing steps in manufacturing the ferro-electric memory device according to the second modification to the first embodiment of the present invention. The manufacturing method according to the second modification to the first embodiment will be described below.

First, with the steps shown inFIGS. 3 to 7, the first hydrogen barrier film23and interlayer24are deposited to cover the ferro-electric capacitor22, as in the first basic example.

Next, as shown inFIG. 15, the interlayer24is etched back. At this time, etching progresses near the lower edge portion of the lower electrode18, and the first hydrogen barrier film23at this portion is exposed. The etching is stopped at this stage. Accordingly, the interlayer24remains not only on the second portion23bbut also on the first portion23a.

Then, as shown inFIG. 14, the second hydrogen barrier film25is deposited on the first hydrogen barrier film23and interlayer24. Accordingly, the boundary portion X between the fourth portion25aand the fifth portion25bof the second hydrogen barrier film25comes into contact with the first hydrogen barrier film23. Subsequent manufacturing steps are the same as in the first basic example, and a description thereof will be omitted.

According to the second modification to the first embodiment, the same effect as in the first basic example can be obtained.

In the second modification, the interlayer24made of the same material as that between the second portion23band the fifth portion25bis formed between the first portion23aand the fourth portion25a. Hence, when the interlayer24is formed from a low-stress insulating film, stress on the hydrogen barrier films can be relaxed even at the first portion23aand fourth portion25a. For this reason, any defect formation due to breaks in the hydrogen barrier film can be suppressed.

As shown inFIG. 16, at the boundary portion X between the fourth portion25aand the fifth portion25b, the second hydrogen barrier film25may penetrate the first hydrogen barrier film23and reach the interlayer dielectric film16under it.

[1-4] Third Modification

In the third modification to the first embodiment, the second contact portion in the first basic example is not present.

FIG. 17is a schematic plan view of a ferro-electric memory device according to the third modification to the first embodiment of the present invention.FIG. 18is a sectional view of the ferro-electric memory device taken along a line XVIII—XVIII inFIG. 17. The structure according to the third modification to the first embodiment will be described below.

As shown inFIGS. 17 and 18, the third modification to the first embodiment is different from the first basic example in that the first hydrogen barrier film23and second hydrogen barrier film25do not come into contact with each other above the upper electrode20. That is, the interlayer24is present between the third portion23cof the first hydrogen barrier film23and the sixth portion25cof the second hydrogen barrier film25.

FIG. 19is a sectional view showing steps in manufacturing the ferro-electric memory device according to the third modification to the first embodiment of the present invention. The manufacturing method according to the third modification to the first embodiment will be described below.

First, with the steps shown inFIGS. 3 to 7, the first hydrogen barrier film23and interlayer24are deposited to cover the ferro-electric capacitor22, as in the first basic example.

Next, as shown inFIG. 19, only the interlayer24on the first portion23aof the first hydrogen barrier film23is etched by using a mask layer40. Accordingly, the interlayer24remains only on the side surfaces and upper surface of the ferro-electric capacitor22.

Then, as shown inFIG. 18, the second hydrogen barrier film25is deposited on the first hydrogen barrier film23and interlayer24. Accordingly, the third portion23cof the first hydrogen barrier film23and sixth portion25cof the second hydrogen barrier film25do not come into contact with each other. Subsequent manufacturing steps are the same as in the first basic example, and a description thereof will be omitted.

According to the third modification to the first embodiment, the same effect as in the first basic example can be obtained.

In the third modification, the interlayer24is present between the second portion23band the fifth portion25band between the third portion23cand the sixth portion25c, which cover the ferro-electric capacitor22. For this reason, the influence of stress of the second hydrogen barrier film25on the ferro-electric capacitor22can be reduced.

[1-5] Fourth Modification

In the fourth modification to the first embodiment, the position of the bit line34in the first basic example is changed.

FIG. 20is a sectional view of a ferro-electric memory device according to the fourth modification to the first embodiment of the present invention. The structure according to the fourth modification to the first embodiment will be described below.

As shown inFIG. 20, the fourth modification to the first embodiment is different from the first basic example in that the bit line34is arranged under the ferro-electric capacitor22. That is, the bit line34is formed in the interlayer dielectric film16under the ferro-electric capacitor22and connected to the source/drain diffusion layer14bthrough a contact.

According to the fourth modification to the first embodiment, the same effect as in the first basic example can be obtained.

FIG. 20illustrates no contact near the ferro-electric capacitor22. A contact is sometimes present adjacent to a cell in a sense amplifier or decoder. Hence, the structure according to the fourth modification to the first embodiment can effectively be used against hydrogen invasion from such a contact.

[2] Second Embodiment

The second embodiment is a COP type memory cell, in which the upper electrode, ferro-electric film, and lower electrode in a ferro-electric capacitor are processed by using two masks.

[2-1] Second Basic Example

FIG. 21is a sectional view of a ferro-electric memory device according to the second basic example of the second embodiment of the present invention. The structure according to the second basic example of the second embodiment will be described below.

As shown inFIG. 21, the second basic example of the second embodiment is different from the first basic example of the first embodiment in the structure of a ferro-electric capacitor22. In the first basic example, the ferro-electric capacitor22is formed by using one mask. In the second basic example, the ferro-electric capacitor22is formed by using two masks. In the second basic example, since a ferro-electric film19and upper electrode20are formed by using a mask different from that used for a lower electrode18, the ferro-electric film19and upper electrode20have a planar shape different from that of the lower electrode18.

More specifically, the lower electrode18has a larger planar size than the ferro-electric film19and upper electrode20. The side surface of the ferro-electric film19is almost flush with that of the upper electrode20. The planar size of the ferro-electric film19is larger than or almost equal to that of the upper electrode20.

FIGS. 22 to 25are sectional views showing steps in manufacturing the ferro-electric memory device according to the second basic example of the second embodiment of the present invention. A manufacturing method according to the second basic example of the second embodiment will be described below.

First, with the steps shown inFIGS. 3 and 4, a MOSFET15and contact17are formed, as in the first basic example of the first embodiment.

Next, as shown inFIG. 22, the lower electrode18, ferro-electric film19, and upper electrode20are sequentially deposited on an interlayer dielectric film16and the contact17. A first mask layer41is deposited on the upper electrode20and patterned.

As shown inFIG. 23, the ferro-electric film19and upper electrode20are patterned by using the first mask layer41. After that, the first mask layer41is removed.

As shown inFIG. 24, a second mask layer42is deposited on the upper electrode20and lower electrode18and patterned.

As shown inFIG. 25, the lower electrode18is patterned by using the second mask layer42. With this process, the ferro-electric capacitor22processed by using the two masks is formed.

Next, as shown inFIG. 21, a first hydrogen barrier film23is deposited on the second mask layer42and interlayer dielectric film16. Subsequent manufacturing steps are the same as in the first basic example of the first embodiment, and a description thereof will be omitted.

In the above description, the second mask layer42remains even after the lower electrode18is processed. However, the second mask layer42may be removed.

According to the second basic example to the second embodiment, the same effect as in the first basic example of the first embodiment can be obtained. In addition, the risk to short-circuit the upper electrode20and lower electrode18can be suppressed as compared to the first basic example.

[2—2] First Modification

In the first modification to the second embodiment, a contact29near the ferro-electric capacitor in the second basic example is formed from a plurality of contacts.

FIG. 26is a sectional view of a ferro-electric memory device according to the first modification to the second embodiment of the present invention. The structure according to the first modification to the second embodiment will be described below.

As shown inFIG. 26, the first modification to the second embodiment is different from the second basic example in that the contact located near the ferro-electric capacitor22is formed from, e.g., two contacts29-1and29-2. The contact29-1is formed simultaneously with the contact17. The contact29-2is formed after formation of a contact28.

According to the first modification to the second embodiment, the same effect as in the second basic example can be obtained. In addition, formation and filling of the contacts29-1and29-2are easier than in the second basic example.

[2-3] Second Modification

In the second modification to the second embodiment, the first contact portion in the second basic example is modified.

FIG. 27is a sectional view of a ferro-electric memory device according to the second modification to the second embodiment of the present invention. The structure according to the second modification to the second embodiment will be described below.

As shown inFIG. 27, the second modification to the second embodiment is different from the second basic example in that the first contact portion where a first portion23aof the first hydrogen barrier film23and a fourth portion25aof a second hydrogen barrier film25come into contact with each other has a smaller area.

That is, instead of bringing the first portion23aand fourth portion25ainto contact with each other all over the surfaces, as in the second basic example, only a boundary portion X between the fourth portion25aand a fifth portion25bof the second hydrogen barrier film25comes into contact with the first portion23aof the first hydrogen barrier film23at the lower edge portion of the lower electrode18. An interlayer24is present between the first portion23aand the fourth portion25a.

According to the second modification to the second embodiment, the same effect as in the second basic example can be obtained.

In the second modification, the interlayer24made of the same material as that between a second portion23band the fifth portion25bis formed between the first portion23aand the fourth portion25a. Hence, when the interlayer24is formed from a low-stress insulating film, stress on the hydrogen barrier films can be relaxed even at the first portion23aand fourth portion25a. For this reason, any defect formation due to breaks in the hydrogen barrier film can be suppressed.

As shown inFIG. 28, at the boundary portion X between the fourth portion25aand the fifth portion25b, the second hydrogen barrier film25may penetrate the first hydrogen barrier film23and reach the interlayer dielectric film16under it.

[2-4] Third Modification

In the third modification to the second embodiment, the second contact portion in the second basic example is not present.

FIG. 29is a sectional view of a ferro-electric memory device according to the third modification to the second embodiment of the present invention. The structure according to the third modification to the second embodiment will be described below.

As shown inFIG. 29, the third modification to the second embodiment is different from the second basic example in that the first hydrogen barrier film23and second hydrogen barrier film25do not come into contact with each other above the upper electrode20. That is, the interlayer24is present between a third portion23cof the first hydrogen barrier film23and a sixth portion25cof the second hydrogen barrier film25.

According to the third modification to the second embodiment, the same effect as in the second basic example can be obtained.

In the third modification, the interlayer24is present between the second portion23band the fifth portion25band between the third portion23cand the sixth portion25c, which cover the ferro-electric capacitor22. For this reason, the influence of stress of the second hydrogen barrier film25on the ferro-electric capacitor22can be reduced. When the connection portion between the first hydrogen barrier film23and the second hydrogen barrier film25is made robust, defective connection points can largely be decreased.

[2-5] Fourth Modification

In the fourth modification to the second embodiment, the position of the bit line in the second basic example is changed.

FIG. 30is a sectional view of a ferro-electric memory device according to the fourth modification to the second embodiment of the present invention. The structure according to the fourth modification to the second embodiment will be described below.

As shown inFIG. 30, the fourth modification to the second embodiment is different from the second basic example in that a bit line34is arranged under the ferro-electric capacitor22. That is, the bit line34is formed in the interlayer dielectric film16under the ferro-electric capacitor22and connected to a source/drain diffusion layer14bthrough a contact.

According to the fourth modification to the second embodiment, the same effect as in the second basic example can be obtained.

B. Offset Type

The third embodiment is an offset type memory cell, in which the upper electrode, ferro-electric film, and lower electrode in a ferro-electric capacitor are processed by using two masks.

[3-1] Third Basic Example

FIG. 31is a schematic plan view of a ferro-electric memory device according to the third basic example of the third embodiment of the present invention.FIG. 32is a sectional view of the ferro-electric memory device taken along a line XXXII—XXXII inFIG. 31. The structure according to the third basic example of the third embodiment will be described below.

As shown inFIGS. 31 and 32, the third basic example of the third embodiment is different from the second basic example of the second embodiment in the connection method between a lower electrode18of the ferro-electric capacitor22and a source/drain diffusion layer14a.

In the second basic example of the second embodiment, the contact17is arranged immediately under the ferro-electric capacitor22. In the third basic example of the third embodiment, a contact17is arranged not immediately under the ferro-electric capacitor22but in a region except the region under the lower electrode. The lower electrode18runs parallel to the running direction of a bit line34. The lower electrode18is connected to the source/drain diffusion layer14ain a region where neither an upper electrode20nor a ferro-electric film19is present.

This structure will be described in more detail. The lower electrode18has a planar size larger than those of the ferro-electric film19and upper electrode20. For this reason, the lower electrode18has a first region where the ferro-electric film19and upper electrode20are present and a second region where the ferro-electric film19and upper electrode20are not present. A contact62is formed on the lower electrode18in the second region. An interconnection61is formed on the contact62to be flush with a plate line30. The interconnection61runs in a direction (e.g., the word line direction) perpendicular to the running direction of the bit line34while projecting from the lower electrode18. In this projecting region, the interconnection61is connected to the source/drain diffusion layer14athrough the contact17and the like. In this way, the lower electrode18is electrically connected to the source/drain diffusion layer14athrough the contacts62and17and the interconnection61.

According to the third basic example to the third embodiment, the same effect as in the second basic example of the second embodiment can be obtained.

In addition, in the third basic example, since no oxygen preventing capability is required of the lower electrode18, the number of steps difference needed to form the ferro-electric capacitor22can be reduced.

[3-2] First Modification

In the first modification to the third embodiment, a contact29near the ferro-electric capacitor in the third basic example is formed from a plurality of contacts.

FIG. 33is a sectional view of a ferro-electric memory device according to the first modification to the third embodiment of the present invention. The structure according to the first modification to the third embodiment will be described below.

As shown inFIG. 33, the first modification to the third embodiment is different from the third basic example in that the contact located near the ferro-electric capacitor22is formed from, e.g., two contacts29-1and29-2. The contact29-1is formed simultaneously with the contact17. The contact29-2is formed after formation of a contact28.

According to the first modification to the third embodiment, the same effect as in the third basic example can be obtained. In addition, formation and filling of the contacts29-1and29-2are easier than in the third basic example.

[3—3] Second Modification

In the second modification to the third embodiment, the first contact portion in the third basic example is modified.

FIG. 34is a sectional view of a ferro-electric memory device according to the second modification to the third embodiment of the present invention. The structure according to the second modification to the third embodiment will be described below.

As shown inFIG. 34, the second modification to the third embodiment is different from the third basic example in that the first contact portion where a first portion23aof a first hydrogen barrier film23and a fourth portion25aof a second hydrogen barrier film25come into contact with each other has a smaller area.

That is, instead of bringing the first portion23aand fourth portion25ainto contact with each other all over the surfaces, as in the third basic example, only a boundary portion X between the fourth portion25aand a fifth portion25bof the second hydrogen barrier film25comes into contact with the first portion23aof the first hydrogen barrier film23at the lower edge portion of the lower electrode18. An interlayer24is present between the first portion23aand the fourth portion25a.

According to the second modification to the third embodiment, the same effect as in the third basic example can be obtained.

In the second modification, the interlayer24made of the same material as that between a second portion23band the fifth portion25bis formed between the first portion23aand the fourth portion25a. Hence, when the interlayer24is formed from a low-stress insulating film, stress on the hydrogen barrier films can be relaxed even at the first portion23aand fourth portion25a. For this reason, any defect formation due to breaks in the hydrogen barrier film can be suppressed.

As shown inFIG. 35, at the boundary portion X between the fourth portion25aand the fifth portion25b, the second hydrogen barrier film25may penetrate the first hydrogen barrier film23and reach the interlayer dielectric film16under it.

[3-4] Third Modification

In the third modification to the third embodiment, the second contact portion in the third basic example is not present.

FIG. 36is a sectional view of a ferro-electric memory device according to the third modification to the third embodiment of the present invention. The structure according to the third modification to the third embodiment will be described below.

As shown inFIG. 36, the third modification to the third embodiment is different from the third basic example in that the first hydrogen barrier film23and second hydrogen barrier film25do not come into contact with each other above the upper electrode20. That is, the interlayer24is present between a third portion23cof the first hydrogen barrier film23and a sixth portion25cof the second hydrogen barrier film25.

According to the third modification to the third embodiment, the same effect as in the third basic example can be obtained.

In the third modification, the interlayer24is present between the second portion23band the fifth portion25band between the third portion23cand the sixth portion25c, which cover the ferro-electric capacitor22. For this reason, the influence of stress of the second hydrogen barrier film25on the ferro-electric capacitor22can be reduced.

[3-5] Fourth Modification

In the fourth modification to the third embodiment, the position of the bit line in the third basic example is changed.

FIG. 37is a sectional view of a ferro-electric memory device according to the fourth modification to the third embodiment of the present invention. The structure according to the fourth modification to the third embodiment will be described below.

As shown inFIG. 37, the fourth modification to the third embodiment is different from the third basic example in that the bit line34is arranged under the ferro-electric capacitor22. That is, the bit line34is formed in the interlayer dielectric film16under the ferro-electric capacitor22and connected to a source/drain diffusion layer14bthrough a contact.

According to the fourth modification to the third embodiment, the same effect as in the third basic example can be obtained.

C. TC Parallel Unit Series-Connected Type

Ferro-electric memory devices according to the fourth and fifth embodiments are examples of TC parallel unit series-connected type memory cells. In a TC parallel unit series-connected type memory cell, the two terminals of a capacitor (C) are connected between the source and the drain of a memory cell transistor (T) to form a unit cell, and a plurality of unit cells are connected in series.

The fourth embodiment is a TC parallel unit series-connected type memory cell, in which the upper electrode, ferro-electric film, and lower electrode in a ferro-electric capacitor are processed by using one mask.

[4-1] Fourth Basic Example

FIG. 38is a schematic plan view of a ferro-electric memory device according to the fourth basic example of the fourth embodiment of the present invention.FIG. 39is a sectional view of the ferro-electric memory device taken along a line XXXIX—XXXIX inFIG. 38. The structure according to the fourth basic example of the fourth embodiment will be described below.

As shown inFIGS. 38 and 39, the fourth basic example of the fourth embodiment is different from the first basic example of the first embodiment in that the memory cell has a TC parallel unit series-connected type cell structure. More specifically, the fourth basic example has the following structure.

The first cell includes a MOSFET15aand a ferro-electric capacitor22a. In the first cell, a lower electrode18of the ferro-electric capacitor22ais electrically connected to a source/drain diffuse layer14a. An upper electrode20of the ferro-electric capacitor22ais electrically connected to a source/drain diffusion layer14bthrough a contact29and an interconnection50. Accordingly, the source/drain diffusion layers14aand14bof the MOSFET15aand the upper electrode20and lower electrode18of the ferro-electric capacitor22aare connected in parallel.

The second cell includes a MOSFET15band a ferro-electric capacitor22b. In the second cell, the lower electrode18of the ferro-electric capacitor22bis electrically connected to a source/drain diffuse layer14c. The upper electrode20of the ferro-electric capacitor22bis electrically connected to the source/drain diffusion layer14bthrough the contact29and interconnection50. Accordingly, the source/drain diffusion layers14band14cof the MOSFET15band the upper electrode20and lower electrode18of the ferro-electric capacitor22bare connected in parallel.

The first and second cells share the connection portion between the source/drain diffusion layer14band the upper electrode20. Hence, the first and second cells are connected in series to form one block.

The number of cells of one block is not limited to two. One block may be formed by connecting a plurality of cells in series. Although not illustrated, a block select transistor to select a block is arranged at the end portion of the block. One of the source and drain of the block select transistor is connected to the block, and the other is connected to a bit line.

According to the fourth basic example of the fourth embodiment, the same effect as in the second basic example of the second embodiment can be obtained.

Additionally, in the fourth basic example, since the number of memory cells connected to the bit line in an active state decreases, the parasitic capacitance of the bit line decreases, and the signal amount becomes large. For this reason, the signal increase amount that can be obtained by the damage preventing effect can be increased.

[4-2] First Modification

In the first modification to the fourth embodiment, the contact29near the ferro-electric capacitor in the fourth basic example is formed from a plurality of contacts.

FIG. 40is a sectional view of a ferro-electric memory device according to the first modification to the fourth embodiment of the present invention. The structure according to the first modification to the fourth embodiment will be described below.

As shown inFIG. 40, the first modification to the fourth embodiment is different from the fourth basic example in that the contact located near the ferro-electric capacitors22aand22bis formed from, e.g., two contacts29-1and29-2. The contact29-1is formed simultaneously with a contact17. The contact29-2is formed after formation of a contact28.

According to the first modification to the fourth embodiment, the same effect as in the fourth basic example can be obtained. In addition, formation and filling of the contacts29-1and29-2are easier than in the fourth basic example.

[4-3] Second Modification

In the second modification to the fourth embodiment, the first contact portion in the fourth basic example is modified.

FIG. 41is a sectional view of a ferro-electric memory device according to the second modification to the fourth embodiment of the present invention. The structure according to the second modification to the fourth embodiment will be described below.

As shown inFIG. 41, the second modification to the fourth embodiment is different from the fourth basic example in that the first contact portion where a first portion23aof a first hydrogen barrier film23and a fourth portion25aof a second hydrogen barrier film25come into contact with each other has a smaller area.

That is, instead of bringing the first portion23aand fourth portion25ainto contact with each other all over the surfaces, as in the fourth basic example, only a boundary portion X between the fourth portion25aand a fifth portion25bof the second hydrogen barrier film25comes into contact with the first portion23aof the first hydrogen barrier film23at the lower edge portion of the lower electrode18. An interlayer24is present between the first portion23aand the fourth portion25a.

According to the second modification to the fourth embodiment, the same effect as in the fourth basic example can be obtained.

In the second modification, the interlayer24made of the same material as that between a second portion23band the fifth portion25bis formed between the first portion23aand the fourth portion25a. Hence, when the interlayer24is formed from a low-stress insulating film, stress on the hydrogen barrier films can be relaxed even at the first portion23aand fourth portion25a. For this reason, any defect formation due to breaks in the hydrogen barrier film can be suppressed.

As shown inFIG. 42, at the boundary portion X between the fourth portion25aand the fifth portion25b, the second hydrogen barrier film25may penetrate the first hydrogen barrier film23and reach an interlayer dielectric film16under it.

[4—4] Third Modification

In the third modification to the fourth embodiment, the second contact portion in the fourth basic example is not present.

FIG. 43is a sectional view of a ferro-electric memory device according to the third modification to the fourth embodiment of the present invention. The structure according to the third modification to the fourth embodiment will be described below.

As shown inFIG. 43, the third modification to the fourth embodiment is different from the fourth basic example in that the first hydrogen barrier film23and second hydrogen barrier film25do not come into contact with each other above the upper electrode20. That is, the interlayer24is present between a third portion23cof the first hydrogen barrier film23and a sixth portion25cof the second hydrogen barrier film25.

According to the third modification to the fourth embodiment, the same effect as in the fourth basic example can be obtained.

In the third modification, the interlayer24is present between the second portion23band the fifth portion25band between the third portion23cand the sixth portion25c, which cover the ferro-electric capacitor22. For this reason, the influence of stress of the second hydrogen barrier film25on the ferro-electric capacitor22can be reduced.

The fifth embodiment is a TC parallel unit series-connected type memory cell, in which the upper electrode, ferro-electric film, and lower electrode in a ferro-electric capacitor are processed by using two masks.

[5-1] Fifth Basic Example

FIG. 44is a sectional view of a ferro-electric memory device according to the fifth basic example of the fifth embodiment of the present invention. The structure according to the fifth basic example of the fifth embodiment will be described below.

As shown inFIG. 44, the fifth basic example of the fifth embodiment is different from the fourth basic example of the fourth embodiment in the structure of ferro-electric capacitors22aand22b. In the fourth basic example, each of the ferro-electric capacitors22aand22bis formed by using one mask. In the fifth basic example, each of the ferro-electric capacitors22aand22bis formed by using two masks. In the fifth basic example, since a ferro-electric film19and upper electrode20are formed by using a mask different from that used for a lower electrode18, the ferro-electric film19and upper electrode20have a planar shape different from that of the lower electrode18.

More specifically, the lower electrode18has a larger planar size than the ferro-electric film19and upper electrode20. The side surface of the ferro-electric film19is almost flush with that of the upper electrode20. The planar size of the ferro-electric film19is larger than or almost equal to that of the upper electrode20.

According to the fifth basic example to the fifth embodiment, the same effect as in the fourth basic example of the fourth embodiment can be obtained. In addition, the risk to short-circuit the upper electrode20and lower electrode18can be suppressed as compared to the fourth basic example.

[5-2] First Modification

In the first modification to the fifth embodiment, a contact29near the ferro-electric capacitor in the fifth basic example is formed from a plurality of contacts.

FIG. 45is a sectional view of a ferro-electric memory device according to the first modification to the fifth embodiment of the present invention. The structure according to the first modification to the fifth embodiment will be described below.

As shown inFIG. 45, the first modification to the fifth embodiment is different from the fifth basic example in that the contact located near the ferro-electric capacitor22ais formed from two contacts29a-1and29a-2, and the contact located near the ferro-electric capacitor22bis formed from two contacts29b-1and29b-2. The contacts29a-1and29b-1are formed simultaneously with a contact17. The contacts29a-2and29b-2are formed after formation of contacts28aand28b.

According to the first modification to the fifth embodiment, the same effect as in the fifth basic example can be obtained. In addition, formation and filling of the contacts29a-1,29a-2,29b-1, and29b-2are easier than in the fifth basic example.

[5-3] Second Modification

In the second modification to the fifth embodiment, the first contact portion in the fifth basic example is modified.

FIG. 46is a sectional view of a ferro-electric memory device according to the second modification to the fifth embodiment of the present invention. The structure according to the second modification to the fifth embodiment will be described below.

As shown inFIG. 46, the second modification to the fifth embodiment is different from the fifth basic example in that the first contact portion where a first portion23aof a first hydrogen barrier film23and a fourth portion25aof a second hydrogen barrier film25come into contact with each other has a smaller area.

That is, instead of bringing the first portion23aand fourth portion25ainto contact with each other all over the surfaces, as in the fifth basic example, only a boundary portion X between the fourth portion25aand a fifth portion25bof the second hydrogen barrier film25comes into contact with the first portion23aof the first hydrogen barrier film23at the lower edge portion of the lower electrode18. An interlayer24is present between the first portion23aand the fourth portion25a.

According to the second modification to the fifth embodiment, the same effect as in the fifth basic example can be obtained.

In the second modification, the interlayer24made of the same material as that between a second portion23band the fifth portion25bis inserted between the first portion23aand the fourth portion25a. Hence, when the interlayer24is formed from a low-stress insulating film, stress on the hydrogen barrier films can be relaxed even at the first portion23aand fourth portion25a. For this reason, any defect formation due to breaks in the hydrogen barrier film can be suppressed.

As shown inFIG. 47, at the boundary portion X between the fourth portion25aand the fifth portion25b, the second hydrogen barrier film25may penetrate the first hydrogen barrier film23and reach an interlayer dielectric film16under it.

[5-4] Third Modification

In the third modification to the fifth embodiment, the second contact portion in the fifth basic example is not present.

FIG. 48is a sectional view of a ferro-electric memory device according to the third modification to the fifth embodiment of the present invention. The structure according to the third modification to the fifth embodiment will be described below.

As shown inFIG. 48, the third modification to the fifth embodiment is different from the fifth basic example in that the first hydrogen barrier film23and second hydrogen barrier film25do not come into contact with each other above the upper electrode20. That is, the interlayer24is present between a third portion23cof the first hydrogen barrier film23and a sixth portion25cof the second hydrogen barrier film25.

According to the third modification to the fifth embodiment, the same effect as in the fifth basic example can be obtained.

In the third modification, the interlayer24is present between the second portion23band the fifth portion25band between the third portion23cand the sixth portion25c, which cover the ferro-electric capacitor22. For this reason, the affect of stress of the second hydrogen barrier film25on the ferro-electric capacitor22can be reduced.

The present invention is not limited to the above embodiments, and various changes and modifications can be made within the spirit and scope of the present invention. For example, as shown inFIG. 49, the first portion23aof the first hydrogen barrier film23may be located on the lower side of the lower edge portion of the lower electrode18. The structure shown inFIG. 49is implemented when, e.g., over-etching occurs in processing the ferro-electric capacitor22, and the upper surface of the interlayer dielectric film16is etched.