SEMICONDUCTOR PACKAGE

A semiconductor package including a first semiconductor device including a semiconductor chip; an interposer including silicon and electrically connected to the first semiconductor device, wherein the first semiconductor is provided on the interposer; a second semiconductor device; and a substrate, wherein the interposer and the second semiconductor device, are provided on the substrate apart from each other, and wherein the interposer is electrically connected to the second semiconductor device; wherein a first volume of a first shape, in which the first semiconductor device overlaps an upper surface of the substrate, is less than or equal to a second volume of a second shape, in which the interposer overlaps an upper surface of the substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No. 10-2022-0115105, filed on Sep. 13, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

The disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including an interposer.

With the rapid development of the electronic industry and the needs of users, electronic products are becoming smaller and lighter, and to this end, semiconductor packages mounted on electronic products may be required to include various functions while at the same time having a smaller volume. Accordingly, semiconductor devices including a plurality of semiconductor chips are being developed.

SUMMARY

One or more example embodiments includes mounting a semiconductor package on package substrates by reducing the effect of warpage of semiconductor devices, improve the bandwidths of the semiconductor packages, and miniaturize the semiconductor packages.

According to an aspect of an example embodiment, a semiconductor package includes a first semiconductor device comprising a semiconductor chip; an interposer comprising silicon and electrically connected to the first semiconductor device, wherein the first semiconductor device is provided on the interposer; a second semiconductor device; and a substrate, wherein the interposer and the second semiconductor device, are provided on the substrate apart from each other, and wherein the interposer is electrically connected to the second semiconductor device; wherein a first volume of a first shape, in which the first semiconductor device overlaps an upper surface of the substrate, is less than or equal to a second volume of a second shape, in which the interposer overlaps the upper surface of the substrate.

According to an aspect of an example embodiment, a semiconductor package includes: a first printed circuit board (PCB) substrate electrically connected to the outside; a memory package comprising the first printed circuit board (PCB) substrate and memory chips stacked on the first printed circuit board (PCB) substrate; a silicon interposer electrically connected to the first printed circuit board (PCB) substrate; a logic chip spaced apart from the memory package and the silicon interposer; and a second printed circuit board (PCB) substrate having the silicon interposer and the logic chip provided thereon, and electrically connected to the silicon interposer and the logic chip.

According to an aspect of an example embodiment, a semiconductor package includes: a first printed circuit board (PCB) substrate; a memory package comprising the first printed circuit board (PCB) substrate and memory chips stacked on the first printed circuit board (PCB) substrate; a silicon interposer electrically connected to the first printed circuit board (PCB) substrate; a logic chip spaced apart from the memory package and the silicon interposer; and a second printed circuit board (PCB) substrate comprising the silicon interposer and the logic chip mounted thereon, and electrically connected to the silicon interposer and the logic chip, wherein a plurality of first connection terminals configured to be electrically connected to the first PCB substrate are provided on an upper surface of the silicon interposer, and a plurality of third connection terminals configured to be electrically connected to the second PCB substrate are provided under a lower surface of the silicon interposer, and wherein a curvature of the first printed circuit board (PCB) substrate is equal to or different from a curvature of the second printed circuit board (PCB) substrate, and a curvature of the silicon interposer is less than the curvature of the first printed circuit board (PCB) substrate and the curvature of the second printed circuit board (PCB) substrate.

DETAILED DESCRIPTION OF EMBODIMENTS

Example embodiments will be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Embodiments described herein are provided as examples, and thus, the present disclosure is not limited thereto, and may be realized in various other forms. Each embodiment provided in the following description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the present disclosure. It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. By contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression, “at least one of a, b, and c,” should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Although the terms first, second, and the like may be used herein to describe various elements, components, steps and/or operations, these terms may be used only to distinguish one element, component, step or operation from another element, component, step, or operation.

Identical reference numerals are used for the same constituent elements in the drawings, and duplicate descriptions thereof are omitted.

FIG.1is a cross-sectional view of a semiconductor package1according to an embodiment.

Referring toFIG.1, the semiconductor package1may include a package substrate400, an interposer300mounted on the package substrate400, a first semiconductor device100mounted on the interposer300, and a second semiconductor device200. The first semiconductor device100may be mounted on an upper surface401of the package substrate400. The second semiconductor device200may be mounted on the upper surface401of the package substrate400, while being horizontally apart from the first semiconductor device100and the interposer300. For example, a distance between the first semiconductor device100and the second semiconductor device200may be the substantially the same as a distance between the interposer300and the second semiconductor device200.

The package substrate400may include a printed circuit board (PCB). For example, the package substrate400may include a multi-layer PCB. A package substrate layer410may include at least one of a phenol resin, epoxy resin, or a polyimide material. The package substrate layer410may include at least one material of, for example, flame retardant 4 (FR4), tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimide triazine (BT), thermount, cyanate ester, polyimide, and liquid crystal polymer.

A solder resist layer (not illustrated) exposing a plurality of first pads461, a plurality of second pads462, and a plurality of external connection pads440, each of which is arranged on an upper surface of a package substrate layer410, may be formed on each of the upper and a lower surface of the package substrate layer410. A plurality of first connection terminals172may be attached to a plurality of first pads461, a plurality of second connection terminals220may be attached to a plurality of second pads462, and a plurality of external connection terminals450may be attached to the plurality of external connection pads440. The plurality of external connection terminals450may include, for example, solder balls.

The package substrate400may include substrate wirings420and430, which electrically connect a plurality of upper connection pads462, which may be referred to as second pads462, to the plurality of external connection pads440. The substrate wirings420and430may be arranged on the upper surface, the lower surface, and/or the inside of the package substrate layer410. The substrate wirings420and430may include, for example, electronically deposited (ED) copper, a rolled-annealed (RA) copper foil, a stainless steel foil, an aluminum foil, an ultra-thin copper foil, sputtered copper, an copper alloy, etc.

The first semiconductor device100may be mounted on the interposer300. A plurality of lower pads171may be arranged on a lower surface of the first semiconductor device100. The plurality of lower pads171may be electrically connected to the semiconductor chips of the first semiconductor device100. The plurality of lower pads171may be respectively electrically connected to a plurality of upper pads360on an upper surface of the interposer300. The plurality of lower pads171may be electrically connected to the plurality of upper pads360through a plurality of first connection terminals172, respectively.

The interposer300may include an interposer substrate320and a plurality of through electrodes330. In addition, the interposer300may further include a redistribution layer310.

A plurality of lower pads340may be on a lower surface of the interposer300, and may be electrically connected to the plurality of first pads461on the upper surface of the package substrate400. For example, a plurality of connection terminals350may be between the plurality of lower pads340and the plurality of first pads461, and electrically connect the plurality of lower pads340to the plurality of first pads461.

The interposer substrate320may include, for example, a semiconductor material or an insulating material. In some embodiments, the interposer substrate320may include silicon, germanium, silicon-germanium, gallium-arsenide (GaAs), glass, ceramic, etc. The interposer300may include the plurality of through electrodes330penetrating the interposer substrate320. The plurality of lower pads340and the plurality of connection terminals350may be provided for electrical connection with an external device, for example, a PCB.

The plurality of through electrodes330may be respectively electrically connected to the plurality of upper pads360so that other semiconductor devices may be mounted on the upper surface of the interposer300. Each of the plurality of through electrodes330may protrude above the upper surface of the interposer substrate320. InFIG.1, for convenience of illustration, a shape, in which the plurality of through electrodes330protrudes above the upper surface of the interposer substrate320, is not illustrated. The plurality of through electrodes330may include one or more of, for example, aluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co), copper (Cu), hafnium (Hf), indium (In), magnesium (Mg), manganese (Mn), molybdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tin (Sn), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), zinc (Zn), and zirconium (Zr).

The interposer300may further include the redistribution layer310, and the redistribution layer310may be on the upper surface of the interposer substrate320. The redistribution layer310may include contact plugs (not illustrated) and metal horizontal wirings311. The contact plugs may respectively electrically connect the metal horizontal wirings311to the plurality of upper pads360, which are vertically adjacent to each other. The redistribution layer310may further include an interlayer insulating layer312to electrically insulate components included therein. The interlayer insulating layer312may include silicon oxide, silicon nitride, silicon oxynitride, polymer, or a combination thereof.

The second semiconductor device200may be electrically connected to a plurality of lower pads210attached to the lower surface of the second semiconductor device200via the plurality of second pads462on the package substrate400. For example, the plurality of lower pads210may be electrically connected to the plurality of second pads462via the plurality of second connection terminals220. The pitch indicating an interval between the plurality of second connection terminals220may be about 50 μm or more, and about 100 μm or less, for example.

A first underfill material layer (not illustrated) surrounding the plurality of first connection terminals172may be arranged between the first semiconductor device100and the package substrate400. A second underfill material layer (not illustrated) surrounding the plurality of second connection terminals220may be arranged between the second semiconductor device200and the package substrate400.

The first semiconductor device100may include a first semiconductor chip160and a plurality of second semiconductor chips110sequentially stacked on the first semiconductor chip160. In some embodiments, four or eight second semiconductor chips110may be stacked on one first semiconductor chip160. In some embodiments, each of the plurality of second semiconductor chips110may include a memory semiconductor chip including a memory device, and the first semiconductor chip160may include a logic semiconductor chip including circuits for controlling a memory device, such as a dynamic random access memory (DRAM) device or a flash memory device.

The first semiconductor chip160may be referred to as a base die, a base chip, a controller die, a controller chip, a buffer die, or a buffer chip. The second semiconductor chip110may be referred to as a memory die, a memory chip, a core die, or a core chip. In some embodiments, when the second semiconductor chip110includes a DRAM device, the second semiconductor chip110may be referred to as a DRAM die or a DRAM chip. In some embodiments, when the second semiconductor chip110includes a flash memory device, the second semiconductor chip110may be referred to as a flash memory die or a flash memory chip.

The first semiconductor chip160may include a first semiconductor substrate161, on which a first semiconductor device162is formed on an active surface thereof, and a wiring layer163arranged on the active surface of the first semiconductor substrate161. The first semiconductor chip160may have a face down arrangement, in which the active surface of the first semiconductor substrate161faces downward.

In an embodiment, an upper surface and a lower surface of a semiconductor chip may refer to an upper side surface and a lower side surface, as shown in the drawings, and a front surface and a rear surface of the semiconductor chip may refer to an active side surface and an inactive side surface of a semiconductor substrate, respectively. For example, inFIG.1, an upper surface of the first semiconductor chip160may be a rear surface, and a lower surface thereof may be a front surface

The first semiconductor substrate161may include, for example, a semiconductor material, such as silicon (Si) or germanium (Ge). Alternatively, the first semiconductor substrate161may include compound semiconductor materials, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphate (InP). The first semiconductor substrate161may include a conductive region, for example, a well doped with impurities. The first semiconductor substrate161may have various device isolation structures such as a shallow trench isolation (STI) structure.

The first semiconductor substrate161may include a first semiconductor device162including a plurality of individual devices of various types formed on the active surface of the first semiconductor substrate161. The plurality of individual devices may include various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET), such as a complementary metal-insulator-semiconductor (CMOS) transistor, system large scale integration (LSI), an active device, a passive device, etc. The plurality of individual devices may be electrically connected to the conductive region of the first semiconductor substrate161. The first semiconductor device162may further include a conductive wiring or a conductive plug electrically connecting at least two of the plurality of individual devices, or the plurality of individual devices to the conductive region of the first semiconductor substrate161. In addition, each of the plurality of individual devices may be electrically isolated from another adjacent individual device by an insulating layer.

The wiring layer163may include a plurality of conductive wiring patterns (not illustrated) and an inter-wiring insulating layer (not illustrated) around and surrounding the plurality of conductive wiring patterns. The plurality of conductive wiring patterns may include wiring lines and wiring vias. In some embodiments, a plurality of conductive wiring patterns may have multilayer wiring structures including wiring lines and wiring vias at different vertical levels, and an inter-wiring insulating layer may have a multilayer structure, in which a plurality of insulating layers are stacked corresponding to the multilayer wiring structure of the plurality of conductive wiring patterns. The plurality of conductive wiring patterns may include a metal material, such as at least one of aluminum, copper, and tungsten.

The plurality of first connection terminals172may be attached onto the plurality of lower pads171. In some embodiments, the plurality of first connection terminals172may include solder balls. The plurality of first connection terminals172may electrically connect the first semiconductor device100and an external device.

The plurality of second semiconductor chips110may be sequentially stacked on the first semiconductor chip160. The plurality of second semiconductor chips110may be sequentially stacked on an inactive surface of the first semiconductor substrate161. The plurality of second semiconductor chips110may be sequentially stacked on the first semiconductor chip160in the vertical direction (+Z axis direction). The plurality of second semiconductor chips110may be stacked to overlap each other in the vertical direction (+Z axis direction). Edges of each of the plurality of second semiconductor chips110may be aligned with each other in the vertical direction (+Z axis direction). Each of a plurality of second semiconductor chips110may have a face up arrangement in which an active surface of a second semiconductor substrate111faces upward.

Each of a plurality of second semiconductor chips110may include a die adhesive film150, attached to a lower surface thereof, between the plurality of second semiconductor chips110, and may include the die adhesive film150attached to a structure thereunder. For example, the lowest second semiconductor chip110among the plurality of second semiconductor chips110may be attached onto the first semiconductor chip160thereof, with the die adhesive film150therebetween, and the others of the plurality of second semiconductor chips110may be attached onto the other different second semiconductor chip110on the lower side thereof, with the die adhesive film150therebetween. The second semiconductor chip110and the die adhesive film150attached to the lower surface of the second semiconductor chip110may have the substantially the same horizontal width and horizontal area.

In some embodiments, the horizontal width and the horizontal area of the second semiconductor chip110may be less than a horizontal width and a horizontal area of the first semiconductor chip160. For example, as shown inFIG.2, the plurality of second semiconductor chips110may be stacked on the first semiconductor chip160without departing from a plane extending from a side surface of the first semiconductor chip160. The plurality of second semiconductor chips110may have substantially the same horizontal width and horizontal area.

The second semiconductor chip110may include the second semiconductor substrate111, on which a second semiconductor device112is formed on an active surface thereof, and a plurality of chip pads120arranged on an upper surface thereof. The plurality of chip pads120may include edge pads arranged adjacent to edges of an upper surface of the second semiconductor device200. Because the second semiconductor substrate111and the second semiconductor device112are generally similar to the first semiconductor substrate161and the first semiconductor device162, respectively, duplicate descriptions thereof may be omitted. The second semiconductor chip110may also include a wiring layer similar to the wiring layer163of the first semiconductor chip160, but the wiring layer may be omitted for convenience of illustration.

The second semiconductor device112may include, for example, a memory device. For example, the second semiconductor device112may include DRAM or a flash memory.

One end of a plurality of bonding wires130may be attached to a chip pad120of the plurality of second semiconductor chips110, and the other end of the plurality of bonding wires130may be attached to a plurality of rear surface pads140. The plurality of bonding wires130may directly connect the plurality of chip pads120of each of the plurality of second semiconductor chips110corresponding to each other to the plurality of rear surface pads140of the first semiconductor chip160. Each of the plurality of second semiconductor chips110may be electrically connected to the first semiconductor chip160via different bonding wires130among the plurality of bonding wires130.

The plurality of rear surface pads140of the first semiconductor chip160may be referred to as first chip connection pads, and the chip pad120of the second semiconductor chip110may be referred to as a second chip connection pad. The bonding wire130may connect the first chip connection pad to the second chip connection pad, and may extend from the first chip connection pad to the second chip connection pad.

The die adhesive film150may be disposed on and cover the plurality of chip pads120of the second semiconductor chip110thereunder. One end portion of the plurality of bonding wires130respectively connected to the plurality of chip pads120may be embedded in the die adhesive film150. The die adhesive film150may include, for example, an inorganic adhesive or a polymer adhesive. The polymer adhesive may include, for example, thermosetting polymer or thermoplastic polymer. In addition, the polymer adhesive may be a hybrid type polymer adhesive manufactured by mixing thermosetting resin or thermoplastic resin.

The plurality of second semiconductor chips110may be attached to a portion of the first semiconductor chip160vertically overlapping the plurality of second semiconductor chips110, and the plurality of rear surface pads140respectively connected to the plurality of bonding wires130may be arranged in the remaining portion of the first semiconductor chip160not vertically overlapping with the plurality of second semiconductor chips110.

Some of the plurality of chip pads120included in each of the plurality of second semiconductor chips110may include data pads for transmitting a data DQ signal. For example, the number of the data pads of each of the plurality of second semiconductor chips110may be about sixteen (16) to about sixty-four (64). In other words, the width of a data bus of each of the plurality of second semiconductor chips110may be in a range of from about 16 bits to about 64 bits.

Some of the plurality of rear surface pads140of the first semiconductor chip160may include data connection pads connected to the data pads of the plurality of second semiconductor chips110. The data pads of the plurality of second semiconductor chips110may be respectively connected to the data connection pads of the first semiconductor chip160in a one-to-one manner via different bonding wires130. That is, the number of data connection pads of the first semiconductor chip160may be a result of multiplying the number of the plurality of second semiconductor chips110stacked on the first semiconductor chip160by the number of data pads of each of the plurality of second semiconductor chips110. For example, the number of the data connection pads of the first semiconductor chip160may be in a range of from about 64 to about 256, and the width of the data bus of the semiconductor package1may correspondingly be in a range of about 64 bits to about 256 bits.

In the first semiconductor device100, the plurality of chip pads120of the plurality of second semiconductor chips110may be electrically connected to the plurality of rear surface pads140of the first semiconductor chip160via the plurality of bonding wires130, and the plurality of rear surface pads140may be electrically connected to the first semiconductor device162via a plurality of through electrodes (not illustrated). The first semiconductor device162may transmit and/or receive data so as to transceive data to and from the outside of the first semiconductor device162via the plurality of first connection terminals172.

The first semiconductor device100may further include a molding layer180covering the upper surface of the first semiconductor chip160and surrounding the plurality of second semiconductor chips110and the plurality of bonding wires130. The molding layer180may include, for example, an epoxy mold compound (EMC). In some embodiments, a horizontal width and a horizontal area of the molding layer180may be the same as the horizontal width and the horizontal area of the first semiconductor chip160. For example, the sidewall of the first semiconductor chip160and the sidewall of the molding layer180may be vertically aligned such that they are coplanar and form a plane.

Each of the plurality of second semiconductor chips110may include a memory cell array. The first semiconductor chip160may include a physical layer and a direct access region. The physical layer of the first semiconductor chip160may include interface circuits for communication with an external host device, and may be electrically connected to the second semiconductor device200via the package substrate400. The first semiconductor device100may receive signals from the second semiconductor device200or transmit signals to the second semiconductor device200via the physical layer. The signals and/or data received via the physical layer of the first semiconductor chip160may be transmitted to the plurality of second semiconductor chips110.

The second semiconductor device200may include, for example, a system on chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

The second semiconductor device200may execute applications, supported by the semiconductor package, by using the first semiconductor device100. For example, the second semiconductor device200may execute calculations, such as specialized calculations, by including at least one of a CPU, an AP, a GPU, a neural processing unit (NPU), a tensor processing unit (TPU), a vision processing unit (VPU), an image signal processing unit (ISP), and a digital signal processor (DSP).

The second semiconductor device200may include the physical layer and a memory controller. The physical layer of the second semiconductor device200may include input/output circuits for transceiving signals to and from the physical layer of the first semiconductor device100. The second semiconductor device200may provide various signals to the physical layer of the first semiconductor device100via the physical layer. The memory controller may control the overall operation of the first semiconductor device100. The memory controller may transmit signals for controlling the first semiconductor device100to the first semiconductor device100via metal substrate wirings420and430of the package substrate400.

The second semiconductor device200may transmit/receive (transceiver) electrical signals to/from the first semiconductor device100electrically connected thereto via the package substrate400. A connection wiring470inFIG.1schematically illustrates a path, through which the first semiconductor device100and the second semiconductor device200transmit and receive electrical signals to and from each other.

The semiconductor package1may further include a package molding layer500for molding the first semiconductor device100, the second semiconductor device200, and the interposer300. The package molding layer500may include, for example, EMC. In some embodiments, the package molding layer500may cover a side surface and an upper surface of the first semiconductor device100, a side surface of the second semiconductor device200, and the upper surface401of the package substrate400, but may not cover the upper surface of the second semiconductor device200.

FIG.3is a diagram of the semiconductor package1according to an embodiment, viewed from above in the −Z axis direction.

Referring toFIG.3, the second semiconductor device200may be mounted on the package substrate400as described above. The second semiconductor device200may be electrically connected to the plurality of lower pads210attached to the lower surface of the second semiconductor device200via the plurality of second pads462on the package substrate400. For example, the plurality of lower pads210may be electrically connected to the plurality of second pads462via the plurality of second connection terminals220. For example, the plurality of second connection terminals220may be solder balls.

The second semiconductor device200may transmit/receive electrical signals to/from the first semiconductor device100electrically connected thereto via the package substrate400and the interposer300. The electrical signal may be transmitted to the outside via the plurality of first connection terminals172below the lower surface of the first semiconductor device100. The electrical signals passing through a plurality of first connection terminals172may reach the second semiconductor device200via the connection wiring470. The electrical signals input/output to/from the second semiconductor device200may pass through a physical layer (PHY) interface230for signal connection with the outside. At least some of the plurality of first connection terminals172may be electrically connected to the PHY interface230. However, an electrical connection between the plurality of first connection terminals172and the PHY interface230is not limited thereto.

A shape, in which the first semiconductor device100overlaps the upper surface401of the package substrate400, may be referred to as a first shape. A shape, in which the interposer300overlaps the upper surface401of the package substrate400, may be referred to as a second shape. For example, as illustrated inFIG.3, the second shape may have a rectangular shape. InFIG.3, the second shape is represented by a dashed line inside the periphery of the first semiconductor chip160. In an embodiment, the second shape and the first shape may both be rectangular shapes and in some embodiments the first shape and the second shape may be the same or substantially similar rectangular shapes. In an embodiment, the first shape and the second shape may have the same or a substantially similar size.

As described above, the first semiconductor device100and the second semiconductor device200may transceive electrical signals. The electrical signal may be transmitted to the outside via the plurality of first connection terminals172below the lower surface of the first semiconductor device100. The electrical signals passing through a plurality of first connection terminals172may reach the second semiconductor device200via the connection wiring470. The electrical signals input/output to/from the second semiconductor device200may pass through the PHY interface230for signal connection with the outside. At least some of the plurality of first connection terminals172may be electrically connected to the PHY interface230. However, in embodiments, an electrical connection between the plurality of first connection terminals172and the PHY interface230is not limited thereto.

The plurality of first connection terminals172may be spaced apart from each other and may be below the lower surface of the first semiconductor device100. As to be described below with reference toFIG.5, in a conventional semiconductor package, the plurality of first connection terminals172may be spaced apart from each other and may be below the lower surface of the first semiconductor device100. In a conventional semiconductor package ofFIG.5, the plurality of first connection terminals172may be apart from each other at a first x-axis pitch Px_1in the x-axis direction, and the plurality of first connection terminals172may be apart from each other at a first y-axis pitch Py_1in the y-axis direction.

In the embodiment ofFIG.3the plurality of first connection terminals172may be apart from each other at a second x-axis pitch Px_2, and the plurality of first connection terminals172may be apart from each other at a second y-axis pitch Py_2. In an embodiment, the second x-axis pitch Px_2may be constant, and the second y-axis pitch Py_2may also be constant. Alternatively, the second x-axis pitch Px_2and the second y-axis pitch Py_2may be the same. In an embodiment, the second x-axis pitch Px_2or the second y-axis pitch Py_2may be about 100 μm or more, and about 200 μm or less. The pitch between the plurality of connection terminals350arranged in the interposer300may be about 50 μm or more, and about 100 μm or less. In an embodiment, the pitch between the plurality of second connection terminals220under the lower surface of the second semiconductor device200may be substantially the same as the pitch between the plurality of connection terminals350. The connection terminals350may also be referred to as a plurality of third connection terminals.

Compared to the pitch between the plurality of first connection terminals172inFIGS.4and5to be described below, the pitch between the plurality of first connection terminals172inFIGS.1through3, which are embodiments of the present application, may be less. Similarly, compared to the width of the plurality of first connection terminals172inFIGS.4and5, the width of the plurality of first connection terminals172inFIGS.1through3, which are embodiments of the present application, may be less. For example, a plurality of first connection terminals172may include solder balls. In the case of a solder ball, the width thereof may mean the diameter of the solder ball.

The plurality of first connection terminals172of the first semiconductor device100may serve as input/output (I/O) ports. When the number of I/O ports in a semiconductor device is increased, a wider bus may be used, and thus, the bandwidth of the semiconductor device may be increased. When the number of the plurality of first connection terminals172is increased, the bandwidth between the first semiconductor device100and the second semiconductor device200may be increased. Comparison of a semiconductor package of an example embodiment with a conventional semiconductor package with respect to bandwidth improvement is described below.

The semiconductor package1according to an embodiment ofFIGS.1-3is compared with a conventional semiconductor package ofFIG.5, which is described below. In the conventional semiconductor package ofFIG.5, the first semiconductor device100may be directly electrically connected to the package substrate400. In the semiconductor package1according to an embodiment ofFIGS.1-3, the first semiconductor device100may be mounted on the interposer300, and may be electrically connected to the package substrate400via the interposer300.

The warpage may occur in the first semiconductor device100and a package substrate400. The warpage of semiconductor devices may be determined by thermal expansion coefficient, and configurations and arrangements of elements constituting a device. When the warpage occurs in a semiconductor device, the shape of the warpage of the semiconductor device may have a concave or smile shape, in which a center portion of the semiconductor device is lower than the periphery portion thereof. Alternatively, the shape of the warpage of the semiconductor device may have a convex or cry shape, in which the central portion of the semiconductor device is higher than the periphery portion thereof.

When the warpage occurs in the semiconductor device, a curvature may occur due to bending of the semiconductor device. The curvature may mean a rate of change indicating the degree of bending of a curve or a curved surface. In the case of a curve, when the curvature of the curve is large, the curve may be more bent. That the curvature of the semiconductor device, in which the warpage occurs, is large may mean that the degree of warpage of the semiconductor device is large. As described above, because the degree of warpage may vary depending on the semiconductor device, the curvature of the semiconductor device may also vary.

The semiconductor device may have a particular thermal expansion coefficient. When the thermal expansion coefficient is large, more expansion may occur with respect to the same temperature increase. When the value of the thermal expansion coefficient in at least a portion of the semiconductor device is different from that of the other portion of the semiconductor, the semiconductor device may have the warpage.

As described above, different shapes or different degrees of warpage may occur depending on the semiconductor device. For example, the warpage of the first semiconductor device100may occur in a different manner from that of the package substrate400. Alternatively, the thermal expansion coefficient of the first semiconductor device100may be different from the thermal expansion coefficient of the package substrate400. Accordingly, the configuration and shape of the first semiconductor device100may be limited. For example, it may be difficult to reduce the pitches of the plurality of first connection terminals172of the first semiconductor device100. It may be difficult to reduce the sizes of the plurality of first connection terminals172of the first semiconductor device100.

Even though the first semiconductor device100may be produced in a smaller size, because a certain level of bandwidth needs to be secured, it may be difficult to reduce the number of the plurality of first connection terminals172. In addition, due to the occurrence of the warpage described above, it may be limited to reduce the pitch or size of the plurality of first connection terminals172. In other words, due to issues, such as warpage arising from the connection between the first semiconductor device100and the package substrate400, and the need to maintain performance, it may be difficult to manufacture a relatively small semiconductor device and mount the semiconductor device on the semiconductor substrate.

In an embodiment of the present application, such as shown inFIGS.1-3, the first semiconductor device100may be mounted on the interposer300. In an embodiment, the interposer300may include a silicon interposer. Interposers of silicon single crystals may generate less warpage than substrates. In addition, the silicon interposer may be manufactured more planar than the PCB. In other words, the silicon interposer may have a smaller curvature due to warpage than the first semiconductor device100and the package substrate400. The difference in the degree of coverage between the interposer300, the package substrate400, and the interposer300, and the first semiconductor device100may be reduced, compared to the difference in the degree of coverage between the first semiconductor device100and the package substrate400. Accordingly, when the interposer300is used, the pitch between the connection terminals due to the warpage effect may be reduced compared to the case, in which the interposer300is not used, and thus, the pitch between the connection terminals may be reduced and the size of the connection terminal may be reduced. At the same time, an electrical connection between the first semiconductor device100and the package substrate400may be maintained via the interposer300.

In other words, according to embodiments of the present application, including the embodiment shown and described with respect toFIGS.1-3, the pitch between the plurality of first connection terminals172may be reduced, and the width of the plurality of first connection terminals172may be used. In other words, the second x-axis pitch Px_2may be less than the first x-axis pitch Px_1, and the second y-axis pitch Py_2may be less than the first y-axis pitch Py_1. When the pitch of the plurality of first connection terminals172is reduced, and the number of the plurality of first connection terminals172is the same, the area, in which the plurality of first connection terminals172are arranged, may be reduced.

Because the pitch of the plurality of first connection terminals172is reduced, when the area of the lower surface of the first semiconductor device100is the same, more numbers of the plurality of first connection terminals172may be arranged. The increase of the number of the connection terminals may mean the increase of the I/O ports of the first semiconductor device100. The increase of the I/O ports of the first semiconductor device100may mean higher bandwidths between the first semiconductor device100and the second semiconductor device200, which are electrically connected to each other.

As described above, the electrical signals passing through the plurality of first connection terminals172may reach the PHY interface230via the connection wirings470. In an embodiment of the present application, such as shown inFIGS.1-3, the number of the plurality of first connection terminals172corresponding to the I/O port of the first semiconductor device100in the embodiment ofFIGS.1-3may be greater than that of the conventional semiconductor package ofFIG.5. The number of the plurality of first connection terminals172, which have distance from the second semiconductor device200less than a certain distance, may be greater than the number of a conventional semiconductor package. The certain distance may be set according to the needs of a user, and embodiments of the present application are not limited thereto. In other words, the electrical connection distance between the second semiconductor device200and the first semiconductor device100may be reduced, compared to a conventional semiconductor package. In other words, the average distance between at least some of the plurality of first connection terminals172and the PHY interface230of the semiconductor package1of an embodiment of the present application as shown, for example, inFIGS.1-3, may be less than that of the conventional semiconductor package ofFIG.5. When an electrical connection distance between the semiconductor device is decreased, signal integrity (SI) may be improved. Accordingly, the semiconductor package1according to an embodiment may improve the SI between the first semiconductor device100and the second semiconductor device200.

FIG.4is a side view of a typical semiconductor package.

Referring toFIG.4, a conventional semiconductor package may include the package substrate400, the first semiconductor device100mounted on the package substrate400, and the second semiconductor device200. The first semiconductor device100may be mounted on the upper surface401of the package substrate400, and the second semiconductor device200may be mounted on the upper surface401of the package substrate400while being apart from the first semiconductor device100in the horizontal direction.

The first semiconductor device100may be mounted on the package substrate400. A plurality of lower pads171may be arranged on the lower surface of the first semiconductor device100. The plurality of lower pads171may be electrically connected to the semiconductor chips of the first semiconductor device100. A plurality of lower pads171may be electrically connected to the plurality of first pads461on the upper surface of the package substrate400.

The second semiconductor device200may be electrically connected to the plurality of lower pads210attached to the lower surface of the second semiconductor device200via the plurality of second pads462on the package substrate400.

The second semiconductor device200may transmit/receive electrical signals to/from the first semiconductor device100electrically connected thereto via the package substrate400. The connection wiring470inFIG.1schematically illustrates a path, through which the first semiconductor device100and the second semiconductor device200transceive electrical signals to and from each other. The semiconductor package1may further include the package molding layer500for molding the first semiconductor device100and the second semiconductor device200.

FIG.5is a view of a conventional semiconductor package ofFIG.4, viewed from above in the −Z axis direction. Referring toFIG.5, the plurality of first connection terminals172below the lower surface of the second semiconductor chip110included in the first semiconductor device100are illustrated by circular dashed lines. The second semiconductor chip110of the first semiconductor device100is illustrated by a dashed line.

As described above, the plurality of first connection terminals172may be apart from each other, and may be below the lower surface of the first semiconductor device100. In the embodiment, the plurality of first connection terminals172may be apart from each other at the first x-axis pitch Px_1, and the plurality of first connection terminals172may be apart from each other at the first y-axis pitch Py_1.

FIG.6is a cross-sectional view of a semiconductor package1a, according to an example embodiment of the present application.FIG.7is a diagram of the semiconductor package1aaccording to an embodiment, viewed from above in the −Z axis direction. Duplicate descriptions given above are omitted.

Referring toFIGS.6and7, the plurality of first connection terminals172may be spaced apart from each other, and may be below the lower surface of the first semiconductor device100. In the embodiment, the plurality of first connection terminals172may be apart from each other at a third x-axis pitch Px_3, and the plurality of first connection terminals172may be apart from each other at a third y-axis pitch Py_3. In an embodiment, the third x-axis pitch Px_3may be constant, and the third y-axis pitch Py_3may also be constant. Alternatively, the third x-axis pitch Px_3and the third y-axis pitch Py_3may have the same value. In an embodiment, the third x-axis pitch Px_3or the third y-axis pitch Py_3may be about 100 μm or more, and about 200 μm or less. The pitch between the plurality of connection terminals350arranged in the interposer300may be about 50 μm or more, and about 100 μm or less. However, the numerical values of the third x-axis pitch Px_3and the third y-axis pitch Py_3are not limited thereto.

The number of the plurality of first connection terminals172inFIG.7may be the same as the number of the plurality of first connection terminals172inFIG.2. InFIG.7, because the number of connection terminals is maintained, the number of I/O ports of the first semiconductor device100may be maintained. Accordingly, the bandwidth of the second semiconductor device200electrically connected to the first semiconductor device100may be maintained.

As described above with reference toFIG.2, in embodiments of the present application, the pitch between the plurality of first connection terminals172may be reduced, and the size of the plurality of first connection terminals172may be reduced, by using example embodiments. In other words, the third x-axis pitch Px_3may be less than the first x-axis pitch Px_1, and the third y-axis pitch Py_3may be less than the first y-axis pitch Py_1. When the pitch of the plurality of first connection terminals172is reduced, and the number of the plurality of first connection terminals172is the same, the area, in which the plurality of first connection terminals172are arranged, may be reduced. In other words, the area or size of the first shape may be reduced in the embodiment ofFIGS.6-7. Alternatively, the area of a cross-section or the size of the cross-section on an X-Y plane of the first semiconductor device100may be reduced. In other words, inFIG.7, the first shape may be less than the first shape inFIG.5. On the X-Y plane, the size of the cross-section of the first semiconductor device100inFIG.7may be less than the size of the cross-section of the first semiconductor device100inFIG.5.

Because the area or size of the first shape of an example embodiment is decreased while the bandwidth is maintained, the size or area of the package substrate400, on which the first semiconductor device100is mounted, may also be decreased. Because the size or area of the package substrate400is reduced, the size or area of the cross-section of the semiconductor package1aaccording an embodiment of the present application may be reduced.

FIG.8is a side view of a semiconductor package1baccording to an embodiment.FIG.9is a diagram of a semiconductor package according to an embodiment, viewed from above in the −Z axis direction. Duplicate descriptions given above may be omitted.

Referring toFIGS.8and9, the plurality of first connection terminals172may be apart from each other at a fourth x-axis pitch Px_4, and the plurality of first connection terminals172may be apart from each other at a fourth y-axis pitch Py_4.

A shape, in which the interposer300overlaps the upper surface401of the package substrate400, may be referred to as the second shape. The second shape is represented by a dashed line outside the periphery of the first semiconductor chip160. In an embodiment, like illustrated inFIG.5, the second region may have the same rectangular shape as the second shape and the first shape described above. The area of the second shape may be greater than the area of the first shape. The length of a side in parallel with the X-axis of the second shape may be greater than or equal to the length of a side in parallel with the X-axis of the first shape. The length of a side in parallel with the Y-axis of the second shape may be greater than or equal to the length of a side in parallel with the Y-axis of the first shape. Alternatively, the outer edge of the second shape may include or be the same as the outer edge of the first shape.

As described above, in the embodiment ofFIGS.8and9, the fourth x-axis pitch Px_4may be less than the first x-axis pitch Px_1. The fourth y axis pitch Py_4may be less than the first y axis pitch Py_1. As described with reference toFIG.2, because the pitch between the plurality of first connection terminals172are reduced compared to a conventional semiconductor package, the bandwidth between the second semiconductor device200and the first semiconductor device100, which are electrically connected to each other, may be increased.

Because in the embodiment ofFIGS.8and9, the second shape is greater than the first shape, the outer edge of the interposer300may be greater or wider than the outer edge of the first semiconductor device100. The cross-sectional area on the X-Y plane of the interposer300inFIG.8may be greater than the cross-sectional area on the X-Y plane of the interposer300inFIG.5. Alternatively, the size on the X-Y plane of the interposer300inFIG.8may be greater than the size on the X-Y plane of the interposer300inFIG.5. Accordingly, the number of a plurality of connection terminals350arranged below the lower surface of the interposer300may be greater than that inFIG.2.