Flash memory and associated programming method

A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage.

FIELD OF THE INVENTION

The present invention relates to a flash memory, and more particularly to a flash memory and associated programming method for simultaneously programming multiple bits of data.

BACKGROUND OF THE INVENTION

A flash memory is a non-volatile data storage device that can be electrically programmed (or rewritten). Consequently, the flash memory is widely used to store data.

FIG. 1is a schematic circuit diagram illustrating a conventional flash memory. As shown inFIG. 1, the flash memory comprises a memory array10and a path control circuit18. The memory array10comprises plural memory units. For clarification and brevity, only two memory units11and12are shown. Each of the memory units11and12comprises a select transistor and a storage transistor. For example, the storage transistor is a metal-oxide-semiconductor transistor comprising a gate terminal, a drain terminal, a source terminal and a charge storage structure (e.g. a floating gate). The storage transistor Ma of the first memory unit11and the storage transistor Mb of the second memory unit12can store data (e.g. one bit of data).

Please refer toFIG. 1again. The first memory unit11comprises a select transistor Pa and a storage transistor Ma. The second memory unit12comprises a select transistor Pb and a storage transistor Mb. The select transistors Pa and Pb are p-channel metal-oxide-semiconductor transistors. The storage transistors Ma and Mb are p-channel metal-oxide-semiconductor transistors with charge storage structures. The source terminals of the select transistors Pa and Pb are connected to a power source voltage V1. The gate terminals of the select transistors Pa and Pb are connected to a node n0, and further connected to a select voltage Vsel. The gate terminals of the storage transistors Ma and Mb are connected to a node n1 (i.e. a control line terminal) through a control line and further connected to a program voltage Vpgm. The drain terminals of the storage transistors Ma and Mb are connected to the path control circuit18.

During the process of programming the first memory unit11, the first memory unit11is enabled by the path control circuit18, but the other memory units are disabled. According to the settings, the select transistor Pa is turned on in response to the select voltage Vsel. Consequently, a first programming current Ipgm1 flows through the drain terminal and the source terminal of the storage transistor Ma according to the program voltage Vpgm. When the first programming current Ipgm1 flows through the storage transistor Ma, charges (e.g. electrons) are injected into the floating gate of the storage transistor Ma. Consequently, the threshold voltage of the storage transistor Ma is changed, and the storage transistor Ma is programmed.

After the first memory unit11is programmed, the process of programming the second memory unit12is continuously done. Similarly, during the process of programming the second memory unit12, the second memory unit12is enabled by the path control circuit18, but the other memory units are disabled. According to the settings, the select transistor Pb is turned on in response to the select voltage Vsel. Consequently, a second programming current (not shown) flows through the drain terminal and the source terminal of the storage transistor Mb according to the program voltage Vpgm. When the second programming current flows through the storage transistor Mb, charges (e.g. electrons) are injected into the floating gate of the storage transistor Mb. Consequently, the threshold voltage of the storage transistor Mb is changed, and the storage transistor Mb is programmed.

The above procedures are repeatedly done until all of the memory units are programmed.

From the above discussions, the memory units of the conventional flash memory should be sequentially programmed one by one. That is, only one bit of data can be programmed at each time. Moreover, different storage transistors usually have different properties. During the programming process, the magnitude of the program voltage Vpgm should be adjusted according to the properties of respective storage transistors. Since the conventional flash memory is unable to program multiple bits of data simultaneously, the programming time period of the conventional flash memory is very long.

SUMMARY OF THE INVENTION

The present invention provides a flash memory for simultaneously programming multiple bits of data in order to effectively reduce the programming time period.

An embodiment of the present invention provides a flash memory. The flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units are used for receiving the constant program voltage or the dynamically-adjustable program voltage, and outputting plural drain currents and plural data line voltages to plural data lines. The current limiter is connected to the plural data lines for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. The multi-bit program control unit is connected to the plural data lines. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage.

An embodiment of the present invention provides a method for simultaneously programming multiple bits of a flash memory having a plurality of memory units comprising: providing an initial program voltage to the plurality of memory units; determining a specified memory unit which has a minimum threshold voltage level among the plurality of memory units; adjusting a program voltage which is for simultaneously programming the plurality of memory units dynamically according to a data line voltage of the specific memory unit.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereinafter, a circuit for programming a single memory unit will be illustrated with reference toFIG. 2A.FIG. 2Ais a schematic circuit diagram illustrating a programming circuit for programming a single memory unit according to the present invention. The programming circuit is applied to a flash memory. As shown inFIG. 2A, the flash memory comprises a memory unit22, a program voltage generator26, and a current limiter24. The memory unit22is included in a memory array of the flash memory. The memory unit22comprises a select transistor Pa and a storage transistor Ma. The select transistor Pa is a p-channel metal-oxide-semiconductor transistor. The storage transistor Ma is a p-channel metal-oxide-semiconductor transistor with a charge storage structure. The charge storage structure is a floating gate.

The source terminal of the select transistor Pa is connected to a power source voltage VSL. The gate terminal of the select transistor Pa is connected to a select voltage Vzwl. In a case that the select voltage Vzwl is 0V, it means that this select transistor Pa is selected to be turned on. The gate terminal of the storage transistor Ma is connected to a program voltage Vzcl along a control line. The drain terminal of the storage transistor Ma is connected to a node n1 along a data line. The data line is also referred as a bit line.

During the process of programming the storage transistor Ma, the select transistor Pa is turned on. Consequently, a programming current Ipg flows through the drain terminal and the source terminal of the storage transistor Ma according to the program voltage Vzcl.

The current limiter24is connected to the node n1 to receive the programming current Ipg. The current limiter24comprises two transistors N1a, N2a(e.g. n-channel metal-oxide-semiconductor transistors) and an amplifier25(e.g. an operational amplifier). The gate terminal, the drain terminal and the source terminal of the transistor N1aare connected to an output terminal of the amplifier25, a node n2 and a ground voltage Vss, respectively. A reference current Iref is provided to the node n2. The gate terminal, the drain terminal and the source terminal of the transistor N2aare connected to the output terminal of the amplifier25, the node n1 and the ground voltage Vss, respectively. Moreover, two input terminals of the amplifier25are connected to the node n2 and a reference voltage Vref, respectively.

The program voltage generator26comprises an amplifier27(e.g. a differential amplifier). The amplifier27is connected to a supply voltage VZCLI. Moreover, a positive end, a negative end and an output terminal of the amplifier27are connected to the node n1, the reference voltage Vref, and the gate terminal of the storage transistor Ma, respectively.

In the current limiter24, a virtual short circuit between the two input terminals of the amplifier25is used to correlate the reference current Iref of the transistor N1awith the reference voltage Vref. In this embodiment, both of the reference current Iref and the reference voltage Vref are maintained constant during the program cycle. Consequently, a current mirror defined by the transistors N1aand N2amay limit the magnitude of the programming current Ipg to be close to the magnitude of the reference current Iref.

In the program voltage generator26, a feedback voltage VFB from the node n1 may reflect the magnitude of the programming current Ipg. As the storage transistor Ma is gradually programmed, the magnitude of the programming current Ipg is increased and the magnitude of the feedback voltage VFB is increased. Consequently, the voltage difference between the feedback voltage VFB and the reference voltage Vref is increased. In other words, since the magnitude of the program voltage Vzcl is gradually increased by the amplifier27, the magnitude of the programming current Ipg is gradually decreased.

FIG. 2Bschematically illustrates the changes of the programming current Ipg, the feedback voltage VFB and the program voltage Vzcl during the program cycle. In the beginning of the program cycle, the magnitude of a drain current of the storage transistor Ma (i.e. the programming current Ipg) abruptly rises up to a higher level. Correspondingly, the magnitude of the feedback voltage VFB rises up to a higher level. As the magnitude of the feedback voltage VFB is increased, a gate voltage of the storage transistor Ma (i.e. the program voltage Vzcl) is increased by the program voltage generator26. As the program voltage Vzcl is increased, the turning on conduction of the storage transistor Ma is limited. Consequently, the magnitude of the programming current Ipg is decreased to be close to the magnitude of the reference current Iref. Moreover, as the programming current Ipg is decreased, the magnitude of the feedback voltage VFB is decreased to be close to the magnitude of the reference voltage Vref. Moreover, since the threshold voltage of the storage transistor Ma is continuously changed during the program cycle, the magnitude of the program voltage Vzcl is gradually increased to maintain a fixed programming current Ipg. At the time when the feedback voltage VFB is close to the reference voltage Vref and the program voltage Vzcl is close to the supply voltage VZCLI, the program cycle is terminated.

For example, for programming the flash memory ofFIG. 2A, the magnitudes of the power source voltage VSL, the supply voltage VZCLI and the reference voltage Vref are respectively set as 5.7V, 8.5V and 0.3V, and the reference current Iref is set as 12 microamperes. During the program cycle, the program voltage Vzcl is increased from 2.7V to 8.3V by the amplifier27. Consequently, the programming current Ipg is decreased from 13.3 microamperes to 12 microamperes, and the feedback voltage VFB is decreased from 1.6V to 0.3V.

Based on the architecture ofFIG. 2A, the present invention provides a flash memory for simultaneously programming multiple bits of data. During a detecting cycle before the program cycle, a storage unit of a memory unit with the minimum threshold voltage is selected from plural memory units. The storage transistor with the minimum threshold voltage is referred as a slow-bit storage transistor.

From the above discussions, when a program voltage is provided to plural memory units, the magnitude of the drain current generated by the slow-bit storage transistor is lower than the magnitudes of the drain currents of other storage transistors. Consequently, the program voltage for programming the slow-bit storage transistor can successfully program the storage transistors of other memory units. In other words, the program voltage for programming the slow-bit storage transistor can be used for programming all storage transistors simultaneously.

In accordance with the present invention, a data line voltage generated by the slow-bit storage transistor is used as a feedback voltage in the beginning of the program cycle. According to the feedback voltage, a dynamically-adjustable program voltage is generated by the program voltage generator to program all memory units. Consequently, the purpose of for simultaneously programming multiple bits of data is achievable. Hereinafter, a method for simultaneously programming eight memory units (i.e. a byte program) will be illustrated. It is noted that the number of memory units to be simultaneously programmed may be varied according to the practical requirements.

FIG. 3is a schematic circuit block diagram illustrating a flash memory according to an embodiment of the present invention. As shown inFIG. 3, the flash memory comprises a memory array310, a program voltage generator320, a multi-bit program control unit330, and a current limiter340. The memory array310at least comprises eight memory units (not shown). The program voltage generator320is used for generating a program voltage Vzcl. The program voltage Vzcl is transmitted to the eight memory units simultaneously. The eight memory units are connected to the current limiter340through eight data lines, respectively. The data line voltages of respective data lines are indicated as DL<0>˜DL<7>.

Moreover, the multi-bit program control unit330are connected to the eight data lines in order to receive the data line voltages DL<0>˜DL<7>. In this embodiment, the multi-bit program control unit330comprises a minimum voltage detector332, a feedback voltage selector334, and a finish condition check unit336. Moreover, during a detecting cycle, the minimum voltage detector332determines a memory unit with the slow-bit storage transistor according to the data line voltages DL<0>˜DL<7>, and issues corresponding switching signals SW<0>˜SW<7> to the feedback voltage selector334. In this context, the slow-bit storage transistor denotes the memory unit whose storage transistor has the minimum threshold voltage.

During the program cycle, the feedback voltage selector334selects one of the eight data line voltages DL<0>˜DL<7> as the feedback voltage VFB, and sends the feedback voltage VFB to the program voltage generator320. According to the feedback voltage VFB, the program voltage generator320generates the program voltage Vzcl.

The finish condition check unit336is used for monitoring the changes of the eight data line voltages DL<0>˜DL<7> and the program voltage Vzcl. Moreover, the finish condition check unit336determines whether the eight memory units (i.e. one byte) have been programmed according to the changes of the eight data line voltages DL<0>˜DL<7> and the program voltage Vzcl. After the program finish is confirmed, the finish condition check unit336issues a finish signal FINISH. In response to the finish signal FINISH, the program voltage generator320and the current limiter340are disabled.

FIGS. 4A˜4Care schematic circuit diagrams illustrating the operations of the flash memory according to an embodiment of the present invention.

As shown inFIG. 4A, the memory array410comprises eight memory units410˜417. These memory units410˜417comprise respective select transistors Pa0˜Pa7and respective storage transistors Ma0˜Ma7. The source terminals of the select transistors Pa0˜Pa7are all connected to a power source voltage VSL. The gate terminals of the select transistors Pa0˜Pa7are all connected to a select voltage Vzwl. In a case that the select voltage Vzwl is 0V, it means that all select transistor Pa0˜Pa7are selected to be turned on. Moreover, the source terminals of the storage transistors Ma0˜Ma7are connected to the drain terminals of respective select transistors Pa0˜Pa7. The gate terminals of the storage transistors Ma0˜Ma7are all connected to a program voltage Vzcl along a control line. The drain terminals of the storage transistors Ma0˜Ma7are connected to respective data lines.

The current limiter440comprises nine transistors Na0˜Na8(e.g. n-channel metal-oxide-semiconductor transistors) and an amplifier442(e.g. an operational amplifier). The gate terminals of the transistors Na0˜Na8are all connected to an output terminal of the amplifier442. The source terminals of the transistors Na0˜Na8are all connected to a ground voltage Vss. The drain terminals of the transistors Na0˜Na8are connected to respective data lines. A first input terminal of the amplifier442is connected to the drain terminal of the transistor Na8and receives a reference current Vref. A second input terminal of the amplifier442receives a reference voltage Vref.

The program voltage generator420comprises a first switch PW1, an amplifier422(e.g. a differential amplifier), and a second switch PW2. In a case that the first switch PW1is in a close state, the magnitude of the program voltage Vzcl has a constant value, which is equal to an initial voltage VPGM_INI. The amplifier422is connected to a supply voltage VZCLI. The amplifier422comprises a positive input terminal to receive a feedback voltage VFB, a negative input terminal receiving the reference voltage Vref, and an output terminal. In a case that the second switch PW2is in a close state, the program voltage Vzcl is dynamically adjusted. It is noted that the first switch PW1and the second switch PW2are not simultaneously in the close state.

The multi-bit program control unit430is used to receive the eight data line voltages DL<0>˜DL<7> and the program voltage Vzcl. After the program cycle is terminated, the multi-bit program control unit430issues a finish signal FINISH. In response to the finish signal FINISH, the program voltage generator420and the current limiter440are disabled.

In this embodiment, the first switch PW1of the program voltage generator420is in the close state during the detecting cycle. Consequently, the magnitude of the program voltage Vzcl is constant and equal to the initial voltage VPGM_INI. Since the threshold voltages of the storage transistors Ma0˜Ma7of the memory units410˜417are not identical, the magnitudes of the drain currents Ipg0˜Ipg7generated according to the initial voltage VPGM_INI are different. Generally, the slow-bit storage transistor has the minimum drain current. In other words, the data line voltage corresponding to the slow-bit storage transistor is the minimum.

During the detecting cycle, the multi-bit program control unit430determines the slow-bit storage transistor according to the minimum value of the eight data line voltages DL<0>˜DL<7>. Then, during the program cycle, the data line voltage corresponding to the slow-bit storage transistor is used as the feedback voltage VFB. According to the feedback voltage VFB, the program voltage generator420generates the program voltage Vzcl.

As shown inFIG. 4B, the minimum voltage detector432is used to determine the minimum value of the eight data line voltages DL<0>˜DL<7>, and the feedback voltage selector434selects the minimum value of the eight data line voltages DL<0>˜DL<7> as the feedback voltage VFB.

For example, if the fifth data line voltage DL<5> has the minimum value during the detecting cycle, the fifth data line voltage DL<5> is used as the feedback voltage VFB during the program cycle. In addition, the program voltage generator420generates the program voltage Vzcl according to the feedback voltage VFB.

During the program cycle, the second switch PW2of the program voltage generator420is in the close state. In addition, the minimum data line voltage (i.e. the fifth data line voltage DL<5>) is used as the feedback voltage VFB, and transmitted from the multi-bit program control unit430to the program voltage generator420. Consequently, the amplifier422issues the program voltage Vzcl to the eight memory units410˜417according to the correlation between the reference voltage Vref and the feedback voltage VFB. As previously described inFIG. 2B, during the program cycle, the magnitude of the program voltage Vzcl is gradually increased to maintain the programming current (e.g. the fifth programming current Ipg5) to be close to the magnitude of the reference current Iref. In addition, the magnitude of the feedback voltage VFB is gradually decreased to be close to the magnitude of the reference voltage Vref.

During the program cycle, the magnitude of the feedback voltage VFB is gradually decreased to be close to the magnitude of the reference voltage Vref. In addition, the magnitudes of other data line voltages are also gradually decreased to be close to the magnitude of the reference voltage Vref. Consequently, the multi-bit program control unit430may continuously monitor the eight data line voltages DL<0>˜DL<7> and the program voltage Vzcl. In a case that the magnitudes of the eight data line voltages DL<0>˜DL<7> are all smaller than a first predetermined value and the program voltage Vzcl is larger than a second predetermined value, it is confirmed that the eight memory units410˜417have been programmed. Meanwhile, the multi-bit program control unit430issues the finish signal FINISH. In response to the finish signal FINISH, the program voltage generator420and the current limiter440are disabled.

The detailed architecture of the multi-bit program control unit430will be illustrated with reference toFIGS. 4B and 4C. The multi-bit program control unit430comprises the minimum voltage detector432, the feedback voltage selector434, and the finish condition check unit436. The architecture of the multi-bit program control unit430as shown inFIGS. 4B and 4Cis presented herein for purpose of illustration and description only. Those skilled in the art will readily observe that numerous modifications and alterations may be made while retaining the teachings of the invention. That is, the architecture of the multi-bit program control unit430is not restricted as long as the functions of the minimum voltage detector432, the feedback voltage selector434and the finish condition check unit436are achievable.

As shown inFIG. 4B, the minimum voltage detector432comprises an 8-bit winner-take-all circuit433(also referred as a WTA circuit). The WTA circuit433is one type of the known analog circuits, and the detailed operating principle thereof is not redundantly described herein. In the minimum voltage detector432, the gate terminals of eight transistors T0˜T7are connected to the eight data line voltages DL<0>˜DL<7>, respectively. The source terminals of the eight transistors T0˜T7are connected to another supply voltage Vdd. The drain terminals of the eight transistors T0˜T7are connected to eight input terminals in0˜in7of the WTA circuit433, respectively. Moreover, eight resistors R are connected between the supply voltage Vdd and eight output terminals o0˜o7of the WTA circuit433, respectively.

After the eight data line voltages DL<0>˜DL<7> are inputted into the WTA circuit433, only one of the output terminals o0˜o7of the WTA circuit433corresponding to the minimum data line voltage can generate the output current, which is equal to a bias current Ibias. Whereas, the magnitudes of the output currents of the other output terminals are all zero. For example, if the fifth data line voltage DL<5> is the minimum among the eight data line voltages, the fifth output voltage I5is equal to the bias current Ibias, but the other output currents I0˜I4and I6˜I7are all zero. Under this circumstance, the voltage levels of the output signals V<0>˜V<4> and V<6>˜V<7> are all equal to the magnitude of the supply voltage Vdd. Whereas, only the voltage level of the output signal V<5> (i.e. about Vdd−R×Ibias) is smaller than the voltage Vdd.

The minimum voltage detector432further comprises eight comparators C0˜C7for comparing the correlations between the eight output signals V<0>˜V<7> and the magnitude (Vdd−0.2), thereby outputting respective switching signals SW<0>˜SW<7>. Since the fifth data line voltage DL<5> is the minimum, only the fifth switching signal SW<5> is at a high level state, but the other switching signals SW<0>˜V<4> and SW<6>˜V<7> are all at a low level state.

Please refer toFIG. 4Bagain. The feedback voltage selector434comprises eight AND gates A0˜A7. The eight switching signals SW<0>˜SW<7> are received by first input terminals of the eight AND gates A0˜A7, respectively. An inverted finish signalFINISHis received by all of second input terminals of the eight AND gates A0˜A7. These AND gates A0˜A7perform AND operations. In a case that the finish signal FINISH is at the low level state and the fifth switching signal SW<5> is at the high level state but the other switching signals SW<0>˜V<4> and SW<6>˜V<7> are all at the low level state, the transistor m5of the feedback voltage selector434is turned on. Consequently, the fifth data line voltage DL<5> is used as the feedback voltage VFB.

Unless the programming task is failed, in the final stage of the program cycle, the magnitudes of the eight data line voltages DL<0>˜DL<7> will be decreased to be near the reference voltage Vref, and the program voltage Vzcl will be increased to be near the supply voltage VZCLI. Moreover, when the program voltage Vzcl is reached and constrained at the level of the supply voltage VZCLI during the program cycle, the magnitudes of the eight data line voltages DL<0>˜DL<7> will be then increased in response to the constrained program voltage Vzcl.

Consequently, in the finish condition check unit436as shown inFIG. 4C, eight comparators c0˜c7(also referred as a first comparing circuit) are used to determine the correlations between the eight data line voltages DL<0>˜DL<7> and the magnitude (Vref+0.2), and an additional comparator c8(also referred as a second comparing circuit) is used to determine the correlation between the program voltage Vzcl and the magnitude (VZCLI−0.3). When the magnitudes of the eight data line voltages DL<0>˜DL<7> are all larger than the magnitude (Vref+0.2), an AND gate437generates a high-level detection pass signal DET_PASS. Moreover, when the program voltage Vzcl is larger than the magnitude (VZCLI−0.3), the second comparing circuit generates a high-level program voltage pass signal ZCL_PASS. After the high-level detection pass signal DET_PASS and the high-level program voltage pass signal ZCL_PASS are received by an AND gate438, a high-level finish signal FINISH is generated after delayed by a delaying unit439. Meanwhile, the finish condition check unit436issues the finish signal FINISH to notify the program voltage generator420and the current limiter440of disabling the program cycle.

For example, for programming the flash memory ofFIGS. 4A˜4C, the magnitudes of the power source voltage VSL, the supply voltage VZCLI and the reference voltage Vref are respectively set as 5.7V, 8.5V and 0.3V, and the reference current Iref is set as 12 microamperes. During the program cycle, the program voltage Vzcl is increased from 2.7V to 8.3V by the amplifier27. Consequently, the programming current Ipg is decreased from 13.3 microamperes to 12 microamperes, and the DL<0>˜DL<7> are decreased from 1.6V to 0.3V, then increased to a level higher than 0.5V (Vref+0.2V).

As shown inFIG. 5, it is a flow chart showing a method for simultaneously programming multiple bits of a flash memory according to the present invention. Firstly, provide an initial program voltage to the plurality of memory units (S502). Then, determine a specified memory unit which has the minimum threshold voltage level among the plurality of memory units (S504). Then, adjust a program voltage which is for simultaneously programming the plurality of memory units dynamically according to a data line voltage of the specific memory unit (S506).

From the above discussions, the present invention provides a flash memory and associated programming method. During a detecting cycle, a memory unit with a slow-bit storage transistor is searched and the slow-bit storage transistor is included in the specified memory unit described in step504. Then, in the beginning of a program cycle, a data line voltage generated by the slow-bit storage transistor is used as a feedback voltage. The feedback voltage is transmitted to a program voltage generator. According to the feedback voltage, the program voltage generator generates a dynamically-adjustable program voltage to program all memory units. Then, all memory units are programmed by the dynamically-adjustable program voltage. Consequently, the purpose of for simultaneously programming multiple bits of data is achievable, and the programming time period is largely reduced.