Display device and driving method thereof

A display device includes a first unit pixel disposed in a first pixel column and a first pixel row, and a second unit pixel disposed in the first pixel column and a second pixel row adjacent to the first pixel row, and first and second gate lines extending in a row direction and having gate voltage input pads at a terminal portion thereof. First and second data lines extend in a column direction and are connected to the first unit pixel and the second unit pixel, respectively. A first charge control line extends in the row direction and has a charge control gate voltage input pad disposed at a terminal portion thereof. The first gate line is connected to the first unit pixel and the second gate line is connected to the second unit pixel. The first gate line and the second gate line simultaneously receive a same gate pulse.

This application claims priority to Korean Patent Application No. 10-2008-0078252, filed on Aug. 11, 2008, and all the benefits accruing therefrom under 35 U.S.C. §119, the contents of which in its entirety are herein incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a display apparatus. More particularly, the present invention relates to a display apparatus having reduced afterimages and improved display quality, and a method of driving the same.

2. Description of the Related Art

Liquid crystal display (“LCD”) devices are being actively developed to improve advantages such as small size, light weight and large screen size relative to other types of display devices, such as cathode ray tubes (“CRTs”), for example. In general, the LCD displays an image using a plurality of unit pixels, each unit pixel thereof including a thin film transistor (“TFT”) and a liquid crystal capacitor.

More specifically, the liquid crystal capacitor typically includes a pixel electrode, a common electrode and a liquid crystal layer disposed therebetween. In operation of the LCD, an electric field is developed between the pixel electrode and the common electrode by supplying external charges, e.g., a gradation signal, to the pixel electrode though the TFT. Changing the electric field changes an orientation of liquid crystal molecules in the liquid crystal layer, and a quantity of light transmitted through the liquid crystal layer is thereby changed to display a desired image. However, the LCD of the prior art suffers from poor visibility due to afterimages, for example, caused by inherent characteristics of the liquid crystal molecules.

Resolution of the LCD is proportional to a number of the unit pixels provided in a unit area. More particularly, as the number of the unit pixels per unit area increases, the resolution increases. However, as the resolution increases, a number of required scanning lines, e.g., gate lines, increases, and a time available to charge the external charges, e.g., the gradation signal, into one pixel electrode is thereby decreased, further hampering the LCD of the prior art in displaying the desired image.

BRIEF SUMMARY OF THE INVENTION

A display device according to an exemplary embodiment of the present invention includes: a plurality of unit pixels arranged in a matrix having pixel columns and pixel rows, the plurality of unit pixels comprising a first unit pixel disposed in a first pixel column and a first pixel row and a second unit pixel disposed in the first pixel column and a second pixel row adjacent to the first pixel row; a first gate line and a second gate line extending in a substantially row direction and each having a gate voltage input pad disposed at a terminal portion thereof; a first data line and a second data line extending in a substantially column direction and connected to the first unit pixel and the second unit pixel, respectively; and a first charge control line extending in substantially the row direction and having a charge control gate voltage input pad disposed at a terminal portion thereof. The first gate line is connected to the first unit pixel and the second gate line is connected to the second unit pixel, and the first gate line and the second gate line simultaneously receive a same gate pulse.

The first unit pixel is connected to the first data line, and the second unit pixel is connected to the second data line.

The first unit pixel includes a first sub pixel and a second sub pixel, the first gate line is electrically connected to the first sub pixel and the second sub pixel, and the first charge control line is electrically connected to at least one of the first sub pixel and the second sub pixel.

The first sub pixel includes a first pixel electrode and a first thin film transistor (“TFT”) configured to apply a signal of the first data line to the first pixel electrode based on a gate turn-on voltage supplied to the first TFT by the first gate line.

The second sub pixel includes a second pixel electrode, a second TFT configured to apply the signal of the first data line to the second pixel electrode based on the gate turn-on voltage supplied to the second TFT by the gate line, a charge control electrode and a charge control transistor configured to electrically connect the second pixel electrode to the charge control electrode based on charge control gate turn-on voltage of the first charge control line.

The display device may further include a second charge control line electrically connected to the second unit pixel.

The charge control transistor is electrically connected to a charge down capacitor, a first electrode of which is the charge control electrode, and the first sub pixel and the second sub pixel are charged with different voltages based on an operation of the charge down capacitor.

The unit pixel includes a storage line extending in substantially the column direction, and the storage line includes a protruding portion which overlaps at least a portion of the charge control electrode.

The first gate line may be disposed on the first unit pixel.

A first area of the first gate line overlaps a portion of the first pixel electrode and a second area of the second gate line overlaps a portion of the second pixel electrode. A size of the first area is equal to a size of the second area.

The first sub pixel and the second sub pixel include a plurality of domain regions, and orientations of liquid crystals in domain regions of the plurality of domain regions are different.

The first unit pixel may include a thin film transistor which includes: a gate electrode; a gate insulation layer and an active layer disposed on the gate electrode; and one of a source electrode and a drain electrode disposed on the active layer. The active layer is disposed under the first data line, and a shape of the active layer is substantially the same as a shape of the first data line.

In accordance with an alternative exemplary embodiment of the present invention, a method of driving a display device is provided. The display device includes: a plurality of unit pixels arranged in a matrix having pixel columns and pixel rows, the plurality of unit pixels comprising a first unit pixel disposed in a first pixel column and a first pixel row, and a second unit pixel disposed in the first pixel column and a second pixel row adjacent to the first pixel row. The display device further includes a first gate line and a second gate line extending in a substantially row direction and each having gate voltage input pads at respective terminal portions thereof, a first data line and a second data line extending in a substantially column direction and connected to the first unit pixel and the second unit pixel, respectively, and a charge control line extending in the row direction, having a charge control gate voltage input pad disposed at a terminal portion thereof and being electrically connected to the first unit pixel. The method includes simultaneously applying a gate turn-on voltage to the first gate line and the second gate line, charging the first unit pixel with a gray voltage supplied by the first data line, applying a gate turn-off voltage to the first gate line and the second gate line and changing a value of the gray voltage charged into a first sub pixel of the first unit pixel by applying a charge control gate turn-on voltage to charge control line.

The simultaneously applying the gate turn-off voltage to first gate line and the second gate line and the applying the charge control gate turn-on voltage to the charge control line may be performed at the same time.

The applying the gate turn-on voltage to charge control lines may be performed after the simultaneously applying the gate turn-off voltage to the first gate line and the second gate line by a predetermined time.

The charging the first unit pixel with the gray voltage supplied by the first data line may include charging a same gray voltage level to the first sub pixel and a second sub pixel of the first unit pixel.

The changing the value of the gray voltage charged into the first sub pixel may include electrically connecting a charge down capacitor to the first sub pixel by turning on a charge control transistor connected to the charge control line.

DETAILED DESCRIPTION OF THE INVENTION

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top” may be used herein to describe one element's relationship to other elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on the “upper” side of the other elements. The exemplary term “lower” can, therefore, encompass both an orientation of “lower” and “upper,” depending upon the particular orientation of the figure. Similarly, if the device in one of the figures were turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.

Hereinafter, exemplary embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

FIG. 1is a schematic plan view of a display device according to an exemplary embodiment of the present invention, andFIG. 2is a schematic circuit diagram of the display device according to the exemplary embodiment of the present invention shown inFIG. 1.

Referring toFIG. 1, the display device according to an exemplary embodiment of the present invention includes unit pixels500disposed in a substantially matrix pattern, a plurality of gate lines, e.g., gate lines100-1a,100-2a,100-3a,100-1b, and100-2b, a plurality of first data lines, e.g., first data lines200-1a,200-2a,200-3a,200-4a,200-5aand200-6a, a plurality of second data lines, e.g., second data lines200-1b,200-2b,200-3b,200-4b,200-5band200-6b, and a plurality of charge control lines, e.g., charge control lines300-1a,300-2a,300-3a,300-1b,300-2band300-3b. The display device according to an exemplary embodiment of the present invention further includes gate voltage input pads110-1a,110-1b,110-2a,110-2band110-3a, as well as charge control gate voltage input pads, e.g., charge control input pads310-1a,310-1b,310-2a,310-2band310-3a, as shown inFIG. 1.

As shown inFIG. 1, the matrix (hereinafter referred to as a “pixel matrix”) includes a plurality of the unit pixels500. Specifically the pixel matrix includes pixel columns aligned in a first direction, e.g., a column direction, and a pixel rows aligned in a second direction, e.g., a row direction substantially perpendicular to the first direction. In an exemplary embodiment, the unit pixels500emit red, green and blue light and are sequentially arranged in the pixel row direction, but alternative exemplary embodiments of the present invention are not limited thereto. For example, in an alternative exemplary embodiment, the unit pixels500which emit red, green and blue light may be sequentially arranged in the pixel column direction.

Two unit pixels500of the plurality of unit pixels500will now be described in further detail with reference toFIG. 2. More specifically, inFIG. 2, an odd-numbered pixel500-Odd connected to the data line200-1a(FIG. 1), hereinafter referred to, for purposes of convenient description, as a “first data line 200-Da” or a “left-hand data line 200-Da” and an even-numbered pixel500-Even is connected to the data line200-1b(FIG. 1), hereinafter referred to as a “second data line 200-Db” or a “right-hand data line 200-Db”. In addition, the odd-numbered unit pixel500-Odd and the even-numbered unit pixel500-Even each includes a first sub pixel501and a second sub pixel502, but alternative exemplary embodiments are not limited thereto. Alternatively, for example, more than two sub pixels may be provided in each of odd-numbered unit pixel500-Odd and the even-numbered unit pixel500-Even. In addition, it will be understood that, for purposes of illustration, only two unit pixels500are shown inFIG. 2, but exemplary embodiments are not limited thereto. Instead exemplary embodiments of the present invention include additional columns and/or rows of unit-pixels, alternately labeled even and odd, as shown inFIG. 1.

Still referring toFIG. 2, the first sub pixel501of the odd-numbered pixel500-odd includes a first thin film transistor (“TFT”)601-a, a first liquid crystal capacitor Clc1and a first storage capacitor Cst1. A gate terminal, e.g., a gate electrode, of the first TFT601-ais connected to the gate line100-1a(FIG. 1), hereinafter referred to as a “first gate line100-Ga”.

In addition, a source terminal of the first thin film transistor601-ais connected to the first data line200-Da. A drain terminal of the first thin film transistor601-ais connected to the first liquid crystal capacitor Clc1and the first storage capacitor Cst1, as shown inFIG. 2.

The first sub pixel501of the even-numbered pixel500-Even includes a first TFT601-b, a first liquid crystal capacitor Clc1and a first storage capacitor Cst1. A gate terminal of the first TFT601-bis connected to the gate line100-1b(FIG. 1), hereinafter referred to as a “second gate line 100-Gb”.

A source terminal of the first TFT601-bis connected to the second data line200-Db. A drain terminal of the first thin film transistor601-bis connected to it's the first liquid crystal capacitor Clc1and the first storage capacitor Cst1of the first sub pixel501of the even-numbered unit pixel500-Even, as shown inFIG. 2.

The second sub pixel502of the odd-numbered pixel500-Odd includes a second TFT602-a, a charge control transistor701-a, a second liquid crystal capacitor Clc2, a second storage capacitor Cst2and a charge down capacitor Cdown. A gate terminal of the second TFT602-ais connected to the first gate line100-Ga. A source terminal of the second TFT602-ais connected to the first data line200-Da. A drain terminal of the first TFT602-ais connected to the second liquid crystal capacitor Clc2and the second storage capacitor Cst2. A gate terminal of the charge control transistor701-ais connected to the charge control line300-1a(FIG. 1), hereinafter referred to as a “first charge control line 300-Ca”. A source terminal of the charge control transistor701-ais connected to the second liquid crystal capacitor Clc2and it's a drain terminal thereof is connected to the charge down capacitor Cdown, as shown inFIG. 2.

The second sub pixel502of the even-numbered pixel500-Even includes a second TFT602-b, a charge control transistor701-b, a second liquid crystal capacitor Clc2, a second storage capacitor Cst2and a charge down capacitor Cdown. A gate terminal of the second TFT602-bis connected to the second gate line100-Gb. A source terminal of the second TFT602-bis connected to the second data line200-Db. A drain terminal of the second TFT602-bis connected to the second liquid crystal capacitor Clc2and the second storage capacitor Cst2. A gate terminal of the charge control transistor701-bis connected to the charge control line300-1b(FIG. 1), hereinafter referred to as a “second charge control line 300-Cb”. A source terminal of the charge control transistor701-bis connected to the second liquid crystal capacitor Clc2and it's a drain terminal thereof is connected to the charge down capacitor Cdown, as shown inFIG. 2.

In an alternative exemplary embodiment of the present invention, the odd-numbered unit pixel500-Odd and the even-numbered unit pixel500-Even may each further include a charge-up capacitor (not shown). In this case, the drain terminals of each of the charge control transistor701-1and the charge control transistor701-b, respectively, may be connected to a first electrode of the charge-up capacitor Cup. A second electrode of the charge-up capacitor Cup may be connected to the drain terminals of each of the first TFT601-aand the first TFT601-b, respectively.

Referring again toFIG. 1, the gate lines100-1a,100-2aand100-3a,100-1b,100-2band100-3bextend substantially in the row direction of the pixel matrix. In addition, the gate lines100-1a,100-2a,100-3a,100-1b,100-2band100-3bare connected to corresponding unit pixels500in pixel rows of the pixel matrix. More specifically, one of the gate lines100-1a,100-2aand100-3a,100-1b,100-2band100-3bis connected to a corresponding one of the pixel rows. As a result, each of the gate lines100-1a,100-2aand100-3a,100-1b,100-2band100-3bis disposed to pass through a unit pixel region, as illustrated inFIG. 1. More specifically, each of the gate lines100-1a,100-2a,100-3a,100-1b,100-2band100-3boverlaps at least a portion of each of the unit pixel regions, but alternative exemplary embodiments are not limited thereto. Alternatively, for example, each of the gate lines100-1a,100-2aand100-3a,100-1b,100-2band100-3bmay extend along an outer periphery of each of the unit pixel regions.

Still referring toFIG. 1, the data lines200-1a,200-2a,200-3a,200-4a,200-5a,200-6a,200-1b,200-2b,200-3b,200-4b,200-5band200-6bextend substantially in the column direction of the pixel matrix. Further, the data lines200-1a,200-2a,200-3a,200-4a,200-5a,200-6a,200-1b,200-2b,200-3b,200-4b,200-5band200-6bare connected to associated pixel columns of the pixel matrix. Specifically, two data lines are both connected to a given pixel column. More specifically, one of the first data lines200-1a,200-2a,200-3a,200-4a,200-5aand200-6ais connected to a given pixel column, while one of the second data lines200-1b,200-2b,200-3b,200-4b,200-5band200-6bis also connected to the given pixel column. For example, as best shown inFIG. 2, the first data line200-Da (e.g., the left-hand data line200-Da, corresponding to the data line200-1aofFIG. 1) and the second data line200-Db (e.g., the right-hand data line200-Db corresponding to the data line200-1bofFIG. 1) are both connected to unit pixels500in the pixel column including the odd-numbered unit pixel500-Odd and the even-numbered pixel column500-Even, as shown inFIG. 2

Thus, as illustrated inFIG. 1and in the context of the more detailed description above with reference toFIG. 2, in an exemplary embodiment of the present invention, one first data line200-1a,200-2a,200-3a,200-4a,200-5aand200-6aof a plurality of first data lines200-1a,200-2a,200-3a,200-4a,200-5aand200-6ais disposed at a left side of a corresponding pixel column, while one second data line200-1b,200-2b,200-3b,200-4b,200-5band200-6bof a plurality of second data lines200-1b,200-2b,200-3b,200-4b,200-5band200-6bis disposed at an opposite right side of the corresponding pixel column. Further, Odd-numbered unit pixels500in the corresponding pixel column are connected to the first data lines200-1a,200-2a,200-3a,200-4a,200-5aand200-6aor, alternatively, to the second data lines200-1b,200-2b,200-3b,200-4b,200-5band200-6b. Likewise, even-numbered unit pixels500of the corresponding pixel column are connected to remaining data lines, e.g., to data lines to which the odd-numbered unit pixels500are not connected.

In an exemplary embodiment of the present invention, same gate driving pulse is applied to adjacent gate lines (e.g., to the first gate line100-Ga and the second gate line100-Gb ofFIG. 2) which are connected to adjacent unit pixels500.

As a result, an amount of time allocated to each gate line for applying a gate turn-on voltage is substantially increased for each gate line, even when a number of gate lines is increased to improve resolution. More specifically, in an exemplary embodiment of the present invention in which the resolution increases from 1,920×1,080 to 4,096×2,160, for example, 1,080 gate lines are required to realize 1,920×1,080 resolution. In contrast, 2,160 gate lines are required to realize 4,096×2,160 resolution. However, an amount of time allocated time for displaying one image frame is identical in both cases. For purposes of illustration, both cases will be described based on an assumption that the amount of time allocated for displaying one image frame is, for example, 1 (one) second. In the case of the display device having 1,080 gate lines, the gate turn-on voltage is applied for one second to all the gate lines, e.g., 1,080 gate lines, and, accordingly, the amount of time allocated to a single gate line for applying the gate turn-on voltage is 1/1,080 second. In the case of the display device having 2,160 gate lines, however, the gate turn-on voltage is applied for one second to all of the 2,160 gate lines, and accordingly the time allocated to one gate line for applying the gate turn-on voltage is decreased to 1/2,160 second. That is, if the resolution is doubled, the amount of time allocated for applying the gate turn-on voltage to one gate line is reduced by half

However, in an exemplary embodiment of the present invention, the gate turn-on voltage is simultaneously applied to two gate lines, e.g., to a first gate line100-1aand a second gate line100-1b(FIG. 1), and an amount of time allocated to one gate line e.g., to the first gate line100-1aor the second gate line100-1b, for applying the gate turn-on voltage is thereby not reduced, even when a number of gate lines is increased.

Since the gate turn-on voltage is simultaneously applied to the two gate lines, e.g., to the first gate line100-1aand the second gate line100-1b, which are adjacent to each other, two pixel rows connected to the two gate lines, e.g., to the first gate line100-1aand the second gate line100-1boperate at the same time. As a result, the first TFT601and the second TFT602in two unit pixels500vertically adjacent to each other are simultaneously turned on. In this case first TFT601and the second TFT602, a resolution of a display device cannot be increased because the vertically adjacent two unit pixels display a same image. Accordingly, in the display device according to an exemplary embodiment of the present invention, the first TFT601and the second TFT602are disposed in an upper unit pixel500, for example, are connected to one of the first data lines200-1a,200-2a,200-3a,200-4a,200-5aand200-6a, while the first TFT601and the second TFT602disposed in an adjacent lower unit pixel500are connected to one of the second data lines200-1b,200-2b,200-3b,200-4b,200-5band200-6b. As a result, different gradation signals, e.g., different charges, are applied to the associated first data line200-1a,200-2a,200-3a,200-4a,200-5a,200-6a, and the associated second data line200-1b,200-2b,200-3b,200-4b,200-5band200-6b, respectively. Consequently, the vertically adjacent two unit pixels500display different images, and a resolution of the display device is thereby substantially enhanced.

As described above, the display device according to an exemplary embodiment includes the charge control lines300-1a,300-2a,300-1band300-2bfor controlling an amount of charges in each of the first sub pixel501and the second sub pixel502of the unit pixel500. More specifically, the charge control lines300-1a,300-2a,300-1band300-2bextend substantially in the row direction of the pixel matrix, and are connected to pixel rows thereof. The charge control lines300-1a,300-2a,300-1band300-2bare electrically insulated from the gate lines100-1a,100-2a,100-3a,100-1b,100-2band100-3b.

In an exemplary embodiment, the gate turn-on voltage is applied to the gate lines100-1a,100-2a,100-3a,100-1b,100-2bor100-3bto accumulate substantially the same charges in the first sub pixel501and the second sub pixel502. As a result, when a gate turn-off voltage is applied to the gate lines100-1a,100-2a,100-3a,100-1b,100-2bor100-3b, the gate turn-on voltage, which turns on the charge control transistor701, is also applied to the charge control lines300-1a,300-2a,300-1band300-2b. Therefore,an amount of charges in at least one of the first sub pixel501and the second sub pixel502changes. Specifically, in an exemplary embodiment, an amount of charge in the second sub pixel502is reduced to thereby substantially improve visibility.

In an exemplary embodiment, the gate turn-on voltage to turn on the charge control transistor701is applied to the charge control lines300-1a,300-2a,300-1band300-2bwhen the gate turn-off voltage is applied to the gate lines100-1a,100-2a,100-3a,100-1b,100-2bor100-3b, but alternative exemplary embodiments are not limited thereto. For example, in an alternative exemplary embodiment of the present invention, the gate turn-on voltage may be applied to the charge control transistor701some time after the gate turn-off voltage is applied to the gate lines100-1a,100-2a,100-3a,100-1b,100-2bor100-3b.

Referring now toFIG. 2, the first gate line100-Ga and the second gate line100-Gb, as well as the first charge control line300-Ca and the second charge control line300-Cb, extend in substantially the row direction. In addition, the first gate line100-Ga and the second gate line100-Gb, as well as the first charge control line300-Ca and the second charge control line300-Cb, each have a gate voltage input pad disposed at one terminal thereofFIG. 3is a plan view of the display device according to the exemplary embodiment of the present invention shown inFIG. 1andFIG. 4is a partial cross-sectional view taken along line IV-IV′ ofFIG. 3.

Referring toFIGS. 3 and 4, the display device according to an exemplary embodiment of the present invention includes a TFT substrate1000as a lower substrate1000, a common electrode substrate2000disposed opposite to, e.g., facing, the TFT substrate1000as an upper substrate2000, and liquid crystals30disposed between TFT substrate1000and the common electrode substrate2000.

An alignment layer (not shown) may be disposed on surfaces of the lower substrate1000and/or the upper substrate2000to align liquid crystals molecules of the liquid crystals30.

In an exemplary embodiment of the present invention, an alignment mode of the liquid crystals30may be a vertical alignment mode, e.g., the liquid crystals30may be vertically aligned with respect to the upper substrate2000and the lower substrate100, but alternative exemplary embodiments are not limited thereto.

The TFT substrate1000includes a transparent insulation substrate10. The transparent insulation substrate10may include, for example, glass or transparent plastic, but alternative exemplary embodiments are not limited thereto.

The TFT substrate1000according to an exemplary embodiment includes the first gate line100-Ga and the second gate line100-Gb, described in greater detail above with reference toFIG. 2, extending in substantially the row direction on the transparent insulation substrate10. Portions of the first gate line100-Ga and the second gate line100-Gb protrude in substantially the second, e.g., column, direction to form a first gate terminal and a second gate terminal, respectively, of the first TFT601and the second TFT602, respectively. In an exemplary embodiment, the first gate line100-Ga and the second gate line100-Gb may have a monolayer structure or, alternatively, a multilayered structure including two or more layers. In a case where the first gate line100-Ga and the second gate line100-Gb have a multilayered structure with two or more layers, one layer may be formed of a low-resistance material and other layers may be formed of a material having good contact characteristics with other materials. For example, the first gate line100-Ga and the second gate line100-Gb according to an exemplary embodiment of the present invention may include a first layer of chromium (Cr) and a second layer of aluminum (Al) (or Al alloy) or, alternatively, a bi-layer including a first layer of Al (or Al alloy) and a second layer of molybdenum (Mo), but alternative exemplary embodiments are not limited thereto. Alternatively, for example, the first gate line100-Ga and the second gate line100-Gb may include various metal and/or conductive materials.

The TFT substrate1000according to an exemplary embodiment of the present invention includes the first charge control line300-Ca and the second charge control line300-Cb extending in substantially the same direction, e.g., in the row direction, as the first gate line100-Ga and the second gate line100-Gb. Portions of the first charge control line300-Ca and the second charge control line300-Cb protrude in substantially the column direction to form a gate terminal711of the charge control transistor701. In an exemplary embodiment of the present invention, the first charge control line300-Ca and the second charge control line300-Cb are formed of substantially the same material as the first gate line100-Ga and the second gate line100-Gb, as well as on substantially the same plane defined thereby.

The first gate line100-Ga, the second gate line100-Gb, the first charge control line300-Ca and the second charge control line300-Cb have gate voltage input pads110,310, respectively, disposed at a terminal of respective gate lines and charge control line, as shown inFIG. 3. More specifically, a first gate voltage input pad110-Ga and a second gate voltage input pad110-Gb are disposed at ends of the first gate line100-Ga and the second gate line100-Gb, respectively. Likewise, a first charge control gate voltage input pad310-Ca and a second charge control gate voltage input pad310-Cb are disposed at ends of the first charge control line300-Ca and the second charge control line300-Cb, respectively.

Further, the gate voltage input pads110,310are formed in an outer peripheral region of the TFT substrate1000and, during operation, provide a gate voltage which is inputted from the external circuit (not shown) to the first gate line100-Ga, the second gate line100-Gb, the first charge control line300-Ca and the second charge control line300-Cb.

As described above in further detail with reference toFIGS. 1 and 2, the gate voltage is inputted from the external circuit such that after a gate turn-on voltage is applied to adjacent gate lines connected to two adjacent unit pixels, the gate turn-on voltage for turning on associated charge control transistors is applied to adjacent charge control lines connected to the two adjacent unit pixels.

Still referring toFIGS. 3 and 4, the TFT substrate1000according to an exemplary embodiment of the present invention includes the first data line200-Da and the second data line200-Db which intersect the first gate line100-Ga and the second gate line100-Gb. The first data line200-Da and the second data line200-Db are disposed substantially adjacent to the left and the right sides of the pixel column of the pixel matrix, as described above in greater detail with reference toFIGS. 1 and 2. Portions of the first data line200-Da and the second data line200-Db protrude to form a first source terminals631and a second source terminal641, respectively, of the first TFT601and the second TFT602, respectively. The first data line200-Da and the second data line200-Db according to an exemplary embodiment of the present invention may have a monolayer structure or, alternatively, a multilayered structure including two or more layers having different physical properties. In an exemplary embodiment wherein the first data line200-Da and the second data line200-Db are formed to have the multilayered structure with two or more layers, one layer may include a low-resistance material (to reduce a delay of a data signal and/or a voltage drop), while other layers may be formed of a material having good contact characteristics with other materials. Although the first data line200-Da and the second data line200-Db are illustrated inFIG. 3to have a substantially rectilinear shape, alternative exemplary embodiments of the present invention are not limited thereto. For example, the first data line200-Da and the second data line200-Db according to an alternative exemplary embodiment of the present invention may have shapes which include, but are not limited to, a straight line having periodically alternating bends therein or, alternatively, a curved line.

The TFT substrate1000according to an exemplary embodiment of the present invention further includes a plurality of storage lines400extending through a region substantially defined between the first data line200-Da and the second data line200-Db. More specifically, storage lines400of the plurality of storage lines400extend substantially parallel to the first data line200-Da and the second data line200-Db. The storage line400according to an exemplary embodiment of the present invention may be formed of substantially the same material as the first data line200-Da and the second data line200-Db and on substantially the same plane defined therewith. The storage line400is used as electrode terminals of the first storage capacitor Cst1and the second storage capacitor Cst2. As illustrated inFIG. 3, a portion of the storage line400protrudes in substantially the row direction to form a protrusion410. In an exemplary embodiment, the protrusion410is used as an electrode terminal of the charge down capacitor Cdown.

The storage line400may pass through a central region of the unit pixel in substantially the column direction. The first TFT601and the second TFT602in each of the unit pixels500arranged in the column direction are alternately arranged at a left side and a right side of the storage line400. Thus, when there are two unit pixels500in a same pixel column, as illustrated inFIG. 3, the first TFT601and the second TFT602in an upper unit pixel are disposed at the right side of the storage line400, while the first TFT601and the second TFT602in a lower unit pixel500are disposed at the left side of the storage line400.

The TFT substrate1000includes a first pixel electrode510and a second pixel electrode520. The first pixel electrode510is an electrode terminal ofthe first liquid crystal capacitor Clc1and the first storage capacitor Cst1, and the second pixel electrode520is an electrode terminal of the second liquid crystal capacitor Clc2and the second storage capacitor Cst2. The first pixel electrode510and the second pixel electrode520are formed of a transparent conductive material such as indium tin oxide (“ITO”) or indium zinc oxide (“IZO”), for example. The first pixel electrode510and the second pixel electrode520are provided in each unit pixel region. The first pixel electrode510and the second pixel electrode520are spaced apart from each other by a cut-out portion, as shown inFIG. 3. In an exemplary embodiment of the present invention, the cut-out portion may have a shape of a “V”, as illustrated inFIG. 3. In addition, the first pixel electrode510is disposed at an upper side of the unit pixel region, and the second pixel electrode520is disposed at a lower side of the unit pixel region. The first pixel electrode510and the second pixel electrode520include a plurality of domains. Cut-out patterns and/or protrusions are used to divide, e.g., to separate, domains of the plurality of domains.

In an exemplary embodiment of the present invention, the first pixel electrode510and the second pixel electrode520may be symmetrically arranged with respect to, e.g., mirrored about, the storage line400. In an exemplary embodiment of the present invention, an insulation layer (not shown) is disposed between the first pixel electrode510and the second pixel electrode520and underlying structures, e.g., the first TFT601, the second TFT602, the first gate line100-Ga, the second gate line100-Gb, the first data line200-Da, the second data line200-Db and/or the storage line400. An organic layer and/or an inorganic layer may be used as the insulation layer.

In an exemplary embodiment, the first gate line100-Ga and the second gate line100-Gb are disposed to cross a region between the first pixel electrode510and the second pixel electrode520, e.g., the cut-out region, in the substantially row direction, as illustrated inFIG. 3. As the first gate line100-Ga and the second gate line100-Gb are disposed inside the unit pixel region, an overlapping area between the first gate line100-Ga and the second gate line100-Gb and the first pixel electrode510and the second pixel electrode520becomes uniform. Thus, parasitic capacitance occurring in the overlapping area is substantially reduced and/or effectively eliminated.

Thus, the TFT substrate1000according to an exemplary embodiment of the present invention includes the first TFT601and the second TFT602connected to one of the first data line200-Da and the second data line200-Db, respectively, and one of the first gate line100-Ga and the second gate line100-Gb, respectively.

Still referring toFIGS. 3 and 4, the first TFT601according to an exemplary embodiment of the present invention includes a first gate terminal611, a first source terminal631and a first drain terminal651. Likewise, the second TFT602includes a second gate terminal621, a second source terminal641and a second drain terminal661. The first TFT601further includes a gate insulating layer612on the first gate terminal611, an active layer613on the gate insulating layer612and an ohmic contact layer614. The second TFT602also further includes a gate insulating layer622on the second gate terminals621, an active layer623on the gate insulating layer622and an ohmic contact layer624. As illustrated inFIGS. 3 and 4, the first gate terminal611and the second gate terminal621are formed as a single body. The gate insulating layers612and622according to an exemplary embodiment of the present invention may include a silicon nitride layer or, alternatively, a silicon oxide layer. The active layers613and623are disposed on the first gate terminal611and the second gate terminal621, respectively. The first source terminal631and the second source terminal641are formed on the active layers613and623, respectively. The first drain terminal651is connected to the first pixel electrode510through a first pixel contact hole652. The second drain terminal661is connected to the second pixel electrode520through a second pixel contact hole662.

In an exemplary embodiment of the present invention, the active layers613and623are positioned only the first gate terminal611and the second gate terminal621, respectively, and may also be positioned proximate to the first drain terminal651and the second drain terminal661, respectively. Specifically, the active layers613and623may be positioned a lower regions of the first data line200-Da and the second data line200-Db. In this case, the active layers613and623are disposed under the first data line200-Da and the second data line200-Db, and the first data line200-Da and the second data line200-Db, as well as the active layers613ad623have substantially the same planar shape.

The charge control transistor701includes the gate terminal711connected to the first charge control line300-Ca and the second charge control line300-Cb, a gate insulating layer (not shown) disposed on the gate terminal711, an active layer713disposed on the gate insulating layer over the gate terminal711, a source terminal721and a drain terminal731disposed on the active layer713. The source terminal721is connected to the second pixel electrode520through a source contact hole722. The drain terminal731is connected to a charge control electrode800through a drain contact hole732. The charge control electrode800is used as an electrode terminal of the charge down capacitor Cdown. Thus, a portion of the charge control electrode800overlaps the protrusion410of the storage line400, as shown inFIG. 3. As a result, when the charge control transistor701is turned on, charge which has accumulated in the second pixel electrode520is transferred to the charge control electrode800via the charge control transistor701. The charge control electrode800is formed between each of the first pixel electrode510and the second pixel electrode520. Specifically, the charge control electrode800is disposed in the cut-out region at the lower side of the second pixel electrode520, and the charge control transistor701is disposed in a region adjacent to the cut-out region at the lower side of the second pixel electrode520. Thus, a required length of an interconnection for connecting the charge control electrode700to the charge control transistor701and/or the first pixel electrode510and the second pixel electrode520is substantially reduced and/or effectively minimized, thereby substantially reducing an aperture ratio of the display device according to an exemplary embodiment of the present invention.

Still referring toFIGS. 3 and 4, in an exemplary embodiment of the present invention, the common electrode substrate2000includes a light transmitting insulating substrate20, a light shielding pattern910, color filters920, an overcoat layer930disposed on the light shielding pattern910and the color filters920, and a common electrode940disposed on the overcoat layer930. In an exemplary embodiment of the present invention, the color filters920include red, green and/or blue color filters920. The light shielding pattern910prevents light leakage and/or light interference between the adjacent unit pixel regions. In an exemplary embodiment of the present invention, a black matrix910is used as the light shielding pattern910. In addition, the overcoat layer930according to an exemplary embodiment includes an organic material. The common electrode940is formed of a transparent conductive material such as ITO or IZO, for example.

A plurality of cut-out patterns941are provided in the common electrode940for controlling the domains (described in greater detail above), but alternative exemplary embodiments of the present invention are not limited thereto. Alternatively, protrusions, for example, may be employed to control the domains.

The common electrode940is an electrode terminal of each of the first liquid crystal capacitor Clc1and the second liquid crystal capacitor Clc2. Specifically, in the first liquid crystal capacitor Clc1, the first pixel electrode510is an upper electrode, the common electrode940is a lower electrode, and the liquid crystals30act as a dielectric therebetween. Similarly, in the second liquid crystal capacitor Clc2, the second pixel electrode520is an upper electrode, the common electrode940is a lower electrode, and the liquid crystals30act as a dielectric therebetween.

The TFT substrate1000and the common electrode substrate2000are attached to each other with the liquid crystals30interposed therebetween to manufacture a base panel of the display device according to an exemplary embodiment of the present invention. In addition, the display device may further include a polarization film, a backlight and an optical plate/sheet, for example, disposed at sides of the base panel.

Thus, in an exemplary embodiment, the gate turn-on voltage is applied to the first gate line100-Ga and the second gate line100-Gb adjacent thereto. As a result, a charging time, e.g., a gate turn-on time of a TFT, can be prevented from being reduced, even when the resolution is increased. In addition, a unit pixel can be manufactured to include the first sub pixel and the second sub pixel, and a charge controller which is driven based a next gate turn-on voltage, e.g., a temporally subsequent and adjacent gate turn-on voltage, thus controls an amount of charge in the second sub pixel. In an exemplary embodiment of the present invention, the first sub pixel is a main pixel representing a high gradation, while the second sub pixel is a sub pixel representing a low gradation. Therefore, a visibility, e.g., a display quality, of the display device according to an exemplary embodiment of the present invention is substantially improved.

Hereinafter, a method of fabricating the display device according to an exemplary embodiment of the present invention will be described in further detail.

FIGS. 5 through 7are plan views illustrating steps of a method of fabricating a TFT substrate according to an exemplary embodiment of the present invention.FIG. 8is a partial cross-sectional view taken along line VIII-VIII′ ofFIG. 5,FIG. 9is a partial cross-sectional view taken along line IX-IX′ ofFIG. 6, andFIG. 10is a partial cross-sectional view taken along line X-X′ ofFIG. 7. The same reference characters inFIGS. 5-9refer to the same or like components as inFIGS. 1-4, and any repetitive detailed description thereof will hereinafter be omitted.

Referring toFIGS. 5 and 8, a first conductive layer is formed on a substrate10. The first conductive layer (not fully shown) is patterned to form the first gate line100-Ga, the second gate line100-Gb, the first charge control line300-Ca and the second charge control line300-Cb. The gate voltage input pads110and the charge control gate voltage input pads310are formed at respective terminals of the first gate line100-Ga, the second gate line100-Gb, the first charge control line300-Ca and the second charge control line300-Cb. Gate terminals611and621of first and second TFTs and a gate terminal711of a charge control transistor (described in greater detail above with reference toFIGS. 1-4) are simultaneously formed.

In an exemplary embodiment of the present invention, the first conductive layer may include at least one of Cr, MoW, Cr/Al, Cu, Al (Nd), Mo/Al, Mo/Al (Nd), Cr/Al (Nd), Mo/Al/Mo and combinations thereof, but alternative exemplary embodiments of the present invention are not limited thereto. For example, the first conductive layer may include at least one of Al, Nd, Ag, Cr, Ti, Ta, Mo and combinations thereof, or an alloy including at least one of the foregoing elements. Further, the first conductive layer may be formed to have a monolayer or, alternatively, a multilayered structure. Specifically, the first conductive layer may be a bi-layer structure or, alternatively, a tri-layer structure including a metal layer having good physical and chemical properties, such as Cr, Ti, Ta and Mo, for example, and a metal layer having low specific resistivity, such as an Al-based metal or an Ag-based metal, for example. After forming the first conductive layer on a surface of the substrate, a photoresist layer is formed thereon and a lithography process is performed using a mask to form a photoresist mask pattern. An etch process is performed using the photoresist mask pattern as an etch mask. As a result, the first gate line100-Ga and the second gate line100-Gb and the gate terminals611and621, respectively, are formed, as illustrated inFIGS. 5 and 8. The first charge control line300-Ca and the second charge control line300-Cb are formed, and the gate terminal711of the charge control transistor701(FIG. 3) is formed on the first charge control line300-Ca and the second charge control line300-Cb.

Referring now toFIGS. 6 and 9, gate insulating layers612and622, a thin film for an active layer and a thin film for an ohmic contact layer are sequentially formed on the substrate10where the first gate line100-Ga and the second gate line100-Gb are formed. Then, the thin film for the active layer and the thin film for the ohmic contact layer are patterned to form active layers613,623and713, and ohmic contact layers614and624.

In an exemplary embodiment of the present invention, the gate insulating layers612and622may include an inorganic insulating material such as silicon oxide or silicon nitride, for example. An amorphous silicon layer is used as the thin film for the active layer. A silicide or, alternatively, an amorphous silicon layer heavily doped with n-type impurities, is used as the thin film for the ohmic contact layer.

Next, a second conductive layer is formed patterned to form the first data line200-Da and the second data line200-Db, source terminals631,641and721, drain terminals651,661and731and the storage line400. The second conductive layer according to an exemplary embodiment of the present invention may include a single layer or, alternatively, a multi-layer, which may be formed of one or more of Mo, Al, Cr, Ti and combinations thereof, for example. In an exemplary embodiment, the second conductive layer may be formed of substantially the same material used for the first conductive layer.

Thus, the first TFT601and the second TFT602, as well as the charge control transistor701are fabricated, each of which includes gate terminals611,621and711, respectively, source terminals631,641and721, respectively, and drain terminals651,661and731, respectively.

Referring now toFIGS. 7 and 10, a passivation layer530is disposed on the substrate10where the first TFT601, the second TFT602and the charge control transistor701are formed. The passivation layer530is partially removed by an etch process using a photoresist mask pattern, for example, to form the first pixel contact hole652and the second pixel contact hole662which expose portions of the drain terminals651and661, respectively, of the first TFT601and the second TFT602, respectively. In addition, a source contact hole722is formed to expose a portion of the source terminal721of the charge control transistor701, and a drain contact hole732is formed to expose a portion of the drain terminal731of the charge control transistor701.

A third conductive layer is then formed on the passivation layer530proximate to the abovementioned contact holes. The third conductive layer is patterned using a photoresist mask pattern to form the first pixel electrode510and the second pixel electrode520having the cut-out patterns formed therebetween.

In an exemplary embodiment of the present invention, the third conductive layer may include a transparent conductive layer such as ITO or IZO, for example. The first pixel electrode510is connected to the drain terminal651of the first TFT601through the first pixel contact hole652. The second pixel electrode520is connected to the drain terminal661of the second TFT602through the second pixel contact hole662, and is connected to the source terminal721of the charge control transistor700through the source contact hole722. The charge control electrode800is connected to the drain terminal731of the charge control transistor700through the drain contact hole732.

After forming the first pixel electrode510and the second pixel electrode520, a first alignment layer (not shown) is formed thereon, thereby completing a lower substrate, e.g., the TFT substrate.

In an exemplary embodiment of the present invention, a common electrode substrate (not shown) is prepared by sequentially forming a black matrix, color filters, an overcoat layer, protrusive patterns, a transparent common electrode and a second alignment layer over a transparent insulation substrate. Thereafter, the TFT substrate and the common electrode substrate are attached to each other with a spacer (not shown) interposed therebetween. Subsequently, a liquid crystal layer is formed by injecting liquid crystal material into a space formed by the spacer between the TFT substrate and the common electrode substrate, thus completing the LCD according to an exemplary embodiment of the present invention.

Although the TFT substrate according to an exemplary embodiment of the present is formed using five sheet masks, as described herein, the masking process is not limited thereto. For example, the TFT substrate according to an alternative exemplary embodiment of the present invention may be formed using more than five sheet masks or, alternatively, less than five sheet masks.

According to exemplary embodiments of the present invention as described herein, a unit pixel has a first sub pixel and a second sub pixel, and adjusts an amount of charges in the first sub pixel and the second sub pixel. Further, an upper pixel and a lower pixel, vertically adjacent to each other, are simultaneously driven.