Two-step GC etch for GC profile and process window improvement

A method for manufacturing a semiconductor device that comprises defining a semiconductor substrate, forming a gate oxide on the semiconductor substrate, forming a polycrystalline silicon layer over the gate oxide, forming a tungsten silicide layer over the polycrystalline silicon layer; providing a mask over the tungsten silicide layer, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, annealing the tungsten silicide layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.

DESCRIPTION OF THE INVENTION

1. Field of the Invention

This invention pertains in general to semiconductor fabrication, and, more particularly, to a method of forming gate electrodes in manufacturing semiconductor devices.

2. Background of the Invention

In recent years, the gate electrode of a metal-oxide-semiconductor field effect transistor (“MOSFET”) generally is comprised of a multi-layer structure rather than a single-layer structure. The multi-layer structure may include a polycrystalline silicon layer doped with phosphorus, and a metal silicide layer, for example, a tungsten silicide layer, formed over the polycrystalline silicon layer.

A conventional technique for forming a two-layer gate electrode is shown inFIGS. 1A to 1D. Referring toFIG. 1A, a gate oxide layer12, a polycrystalline silicon layer14, a tungsten silicide layer16, and a mask layer18are sequentially formed over a semiconductor substrate10. Mask layer18is defined and patterned by a photolithography process. Unmasked portions of tungsten silicide layer16and portions of polycrystalline silicon layer14underneath the unmasked portions of tungsten silicide layer16are sequentially removed by etching processes. The resultant structure is shown inFIG. 1B. In the etching process for tungsten silicide layer16, tungsten silicide may be removed by low etch selective to polycrystalline silicon. In addition, due to the loading effect, etch rates are different at regions where gate densities are different. Typically, the etch rate at a high-density region, or the array region, is smaller than that of a low-density region, or the periphery region. As a result, some tungsten silicide may remain at the array region when tungsten silicide at the periphery region is removed.

Referring toFIG. 1C, tungsten silicide layer16is over-etched to remove the remaining tungsten silicide at the array region. The over-etch results in non-uniform thickness of polycrystalline silicon layers between the array and periphery regions. However, the thickness control of a polycrystalline silicon layer becomes increasingly important in view of the continued demand for scaled-down device size and high-integration of semiconductor integrated circuits. The non-uniform thickness of polycrystalline silicon layers also may cause failure in an end point detection in an etching process.

Referring toFIG. 1D, the conventional technique then employs a rapid thermal annealing (“RTA”) process to anneal tungsten silicide layer16, and then a rapid thermal oxidation (“RTO”) process to form sidewall spacers20on tungsten silicide layers16and polycrystalline silicon layers14. However, to ameliorate the non-uniformity defect described above, the thermal stress generated by the RTA followed by the RTO may cause a deformed profile of polycrystalline silicon layer14, or an over-extrusion of tungsten silicide layer16, which in turn results in short-circuiting of adjacent contacts.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to methods that obviate one or more of the problems due to limitations and disadvantages of the related art.

To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided a method for manufacturing a semiconductor device that comprises defining a semiconductor substrate, forming a gate oxide on the semiconductor substrate, forming a polycrystalline silicon layer over the gate oxide, forming a tungsten silicide layer over the polycrystalline silicon layer; providing a mask over the tungsten silicide layer, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, annealing the tungsten silicide layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.

In one aspect of the present invention, the annealing of the tungsten silicide layer further comprises a rapid thermal annealing process.

In another aspect of the present invention, the oxidizing of sidewalls of the tungsten silicide layer further comprises a rapid thermal oxidization process.

Also in accordance with the present invention, there is provided a method for manufacturing a semiconductor device that comprises defining a semiconductor substrate, forming a gate oxide on the semiconductor substrate, forming a polycrystalline silicon layer over the gate oxide, forming a tungsten silicide layer over the polycrystalline silicon layer, providing a mask over the tungsten silicide layer, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, annealing the tungsten silicide layer, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.

Still in accordance with the present invention, there is provided a method of forming a gate structure of a semiconductor device that comprises defining a semiconductor substrate, forming a gate electrode over the semiconductor substrate, the gate electrode comprising a gate oxide, a polycrystalline silicon layer formed over the gate oxide, and a tungsten silicide layer formed over the polycrystalline silicon layer, providing a mask over the gate electrode, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, annealing the tungsten silicide layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.

Yet still in accordance with the present invention, there is provided a method of forming a gate structure of a semiconductor device that comprises defining a semiconductor substrate, forming a gate electrode over the semiconductor substrate, the gate electrode comprising a gate oxide, a polycrystalline silicon layer formed over the gate oxide, and a tungsten silicide layer formed over the polycrystalline silicon layer, providing a mask over the gate electrode, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, annealing the tungsten silicide layer, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.

DESCRIPTION OF THE EMBODIMENTS

FIGS. 2A to 2Fshow a method of forming a gate electrode in accordance with one embodiment of the present invention. Referring toFIG. 2A, the method begins with defining a semiconductor substrate30, which may include cleaning and doping a semiconductor wafer. A gate oxide layer32, for example, a silicon dioxide (SiO2) layer, is formed on semiconductor substrate30. Next, a layered gate structure including a polycrystalline silicon layer34and a tungsten silicide layer36formed over polycrystalline silicon layer34is formed on gate oxide layer32. A mask layer38, for example, a silicon nitride layer, is formed over tungsten silicide layer36. Mask layer38is defined and patterned by a conventional photolithography technique.

FIG. 2Bis a cross-sectional view of the array region. FIG.2B′ is a cross-sectional view of the periphery region. Referring to FIGS.2B and2B′, unmasked portions of tungsten silicide layer36are etched by a first etchant. In one embodiment, the first etchant includes a gas selected from HCl, Cl2and He/O2. Due to the loading effect, when tungsten silicide at the periphery region is removed where gate density is relatively low (FIG.2B′), some tungsten silicide36′ remains at the array region where gate density is relatively high (FIG. 2B).

Referring toFIG. 2C, an etch back step with a second etchant is performed to remove the remaining tungsten silicide36′. In one embodiment, the second etchant includes a base such as NH4OH/H2O2. The etch back process based on the second etchant is performed at a temperature ranging from approximately 55° C. to 75° C. With respect to the second etchant, tungsten silicide is etched selectively relative to polycrystalline silicon. The etch-back step reduces sidewalls36-2of tungsten silicide layer36.

Referring toFIG. 2D, a first heat treatment, for example, a rapid thermal annealing (“RTA”) process, is performed to anneal tungsten silicide layer36. The first heat treatment induces a phase transition in tungsten silicide, and increases sidewalls36-2of tungsten silicide layer36by regrowing tungsten silicide thereon.

Referring toFIG. 2E, unmasked portions of polycrystalline silicon layer34are removed by an etching process. Next, referring toFIG. 2F, a second heat treatment, for example, a rapid thermal oxidization (“RTO”) process, is performed to form spacers40on sidewalls of tungsten silicide layer36and polycrystalline silicon layer34. Since the first and second heat treatments are separated in time from each other by the etching process of polycrystalline silicon layer34, thermal stress against polycrystalline silicon layer34and tungsten silicide layer36is alleviated, as compared to the thermal stress generated by the conventional technique.

In one embodiment according to the present invention, the step of performing a first heat treatment (FIG. 2D) is conducted before the step of etching the remaining tungsten silicide36′ (FIG. 2C). This embodiment reduces the risk of short-circuiting between adjacent contacts due to over-extrusion of tungsten silicide layer36.