Metal oxide semiconductor field-effect transistor having a gate oxide layer with portions of different thicknesses and associated methods

A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.

FIELD OF THE INVENTION

The present invention relates to metal oxide semiconductor field-effect transistors (MOSFETs).

BACKGROUND OF THE INVENTION

For the purposes of the present invention, the expression “metal oxide semiconductor field-effect transistors” (MOSFET) denotes various field-effect transistor structures, each including a wafer of semiconductor material, also called the substrate or body, a drain region and a source region integrated in the wafer, and a gate structure including a layer of conductive material separated from the wafer by a layer of insulating material (typically an oxide, such as silicon dioxide). It should be noted that the expression “metal oxide semiconductor” (MOS) is also used for transistors in which the layer of conductive material of the gate is formed by a layer of doped polysilicon, instead of metal. It should also be mentioned that metal oxide semiconductor transistors are also called insulated-gate field-effect transistors (IGFET, insulated-gate FET), to emphasize that the gate electrode is electrically insulated from the wafer or body.

For example, for the purposes of the present invention the term MOSFET is applied not only to transistors having the standard structure, such as the conventional NMOS and PMOS transistors, but also lateral double-diffusion MOSFETs (LDDMOSFET or LDMOSFET), or other possible MOSFET structures comprising a different number of diffused regions and/or a different arrangement thereof in the substrate, as well as different combinations of the dopants. It is known that an LDMOSFET, referred to for brevity below as an LDMOS transistor, comprises, in addition to the drain and gate regions, a body region which is also diffused under the gate oxide and a drift region associated with the drain.

As is known, one of the parameters characterizing a MOSFET is the breakdown voltage BV. With reference to LDMOS transistors for example, the breakdown voltage BV is the voltage of the drain electrode at which the junction between the drain and body is subject to an avalanche effect (avalanche breakdown). The breakdown voltage BV is correlated with the dopants of the drain (or drift) and body regions and with the curvature and denser spacing of the lines of potential induced by the gate electrode. In the known art, two different methods are used to obtain sufficiently high values of breakdown voltage (BV) in MOS or LDMOS transistors.

In the first method, the doping of the drain and body regions is appropriately determined, and, in particular, the doping of the drain region is reduced. This method has the disadvantage of decreasing the performance of the transistor, causing an increase in its series resistance (Ron). The second conventional method proposes the use of a relatively thick gate oxide layer. This approach has the disadvantage of reducing the transconductance Gm and the current-carrying capacity of the LDMOS transistor, thus decreasing the performance of the transistor in terms of gain.

In the known art, therefore, in the case of LDMOS transistors, the doping and thickness of the gate oxide must be determined in such a way as to provide a compromise between the requirements of a suitable breakdown voltage, a convenient gain and an adequate series resistance, and this compromise cannot be considered to be wholly satisfactory.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a metal oxide semiconductor field-effect transistor which overcomes the limitations of conventional transistors.

An object of the present invention is achieved by a metal oxide semiconductor integrated in a wafer of semiconductor material and comprising a gate structure located on one surface of the wafer and including a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness.

Another object of the present invention is to provide a method for manufacturing such a metal oxide semiconductor field-effect transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the figures to which the following description refers, the same numerical references will be used to indicate identical or similar elements.

With reference toFIGS. 1ato4, a description will be given of a particular example of a process of manufacturing an LDMOS transistor integrated in a wafer30of semiconductor material according to the invention. Preferably, the LDMOS transistor of this example is of a type which can be used for radio-frequency power applications. However, as mentioned above and as will be evident to persons skilled in the art, the teachings of the present invention are also applicable to MOSFETs of types other than those described here by way of example.

According to the example, the wafer30is of the P+-P−type, in other words of the type normally used for CMOS platforms, and comprises a P+-type silicon substrate1and a P−-type epitaxial layer2grown on the substrate by conventional methods. The epitaxial layer2forms a separating surface10abetween the substrate1and an outer surface10bopposed to it. The epitaxial layer2has a conductivity of the same type as that of the substrate1, but smaller than this. For example, in terms of resistivity, the silicon substrate1has a resistivity in the range from 1 to 100 mΩ/cm and a thickness in the range from 10 μm to 1000 μm. In a particular example, at the end of the production process the thickness of the substrate1is 200 μm. The epitaxial layer2has a resistivity which is, for example, in the range from 1 to 100 Ω/cm, and has a thickness which is, for example, in the range from 1 to 10 μm.

The method according to the invention comprises the formation of an insulating gate layer3on the surface10b. The insulating gate layer3can be made from any suitable dielectric material. For example, the insulating gate layer3can be an oxide, particularly silicon dioxide. The gate oxide3has a non-uniform thickness and comprises a first portion4having a thickness t1 and a second portion5having a thickness t2 which is different from the thickness t1. As is shown clearly inFIG. 1b, the “thickness of the gate oxide” denotes the distance between the surface of the gate oxide facing the surface10bof the wafer30and the opposite surface of the gate oxide. InFIG. 1b, the first portion4and the second portion5are located on opposite sides of an ideal separating surface S.

In particular, the thickness t1 of the first portion4is greater than the thickness t2 of the second portion5. For example, the thickness t1 is in the range from 20 Å to 500 Å and the thickness t2 is in the range from 10 to 250 Å. Preferably, for radio-frequency power applications, the thickness t1 is in the range from 100 Å to 300 Å and the thickness t2 is in the range from 25 to 150 Å. In one particular example, the thickness t1 is approximately 180 Å and the thickness t2 is approximately 70 Å.

A description is given below (FIGS. 2a-2e) of a particularly advantageous method which can be used, starting with the wafer30ofFIG. 1a, to form a gate structure, a body region and a drift region of the LDMOS transistor. In particular, according to the example, the gate structure includes the gate oxide3and a layer of conductive gate material such as, preferably, a layer of polysilicon. A first layer of oxide6, having a thickness t3 in the range from t2 to t1 for example, is formed, preferably by growing, on the surface10bof the epitaxial layer2. According to the values given above, the layer6can have, for example, a thickness of t3=160 Å.

The ideal surface S for separating the two portions4and5of the gate oxide3is then identified in the surface6. The surface S ideally separates the first layer of oxide6in a first region6alocated above the part of the surface10bon which the first portion4of the gate oxide3will lie, and a second region6blocated above the part of the surface10bon which the second portion4of the gate oxide3will lie. The region6bof the layer6is then removed. This removal can be carried out, for example, by a conventional photolithographic method comprising a stage of forming a photoresist mask and a stage of chemical etching. In greater detail, the forming of the photoresist mask requires the use of a layer of photoresist (not shown) placed on a surface9of the layer of oxide6and the partial irradiation of this photoresist with electromagnetic waves (ultraviolet waves or X-rays, for example) which pass through a suitable photomask (not shown). The irradiation of the photoresist polymerizes the portion of the photoresist lying above the first region6aof the oxide6which is not to be removed.

Chemical etching is then carried out to remove the non-polymerized portion of the photoresist and the underlying second region6bof the oxide layer6in such a way as to expose a surface8of the wafer30. Finally, the removal of the photoresist is completed. A layer of oxide7is then grown on the surface8of the wafer30and on a surface9of the second region6a. This growing stage is carried out in such a way that the portion of the layer of oxide7present on the surface8has a thickness of t2 and the portion of the layer7grown on the surface9is such that the layers6aand7have a combined thickness of approximately t1. A layer of polysilicon500, suitably doped, is then deposited on top of the oxide layer7, as shown inFIG. 2d, in order to make it conductive. A portion of this polysilicon layer500is designed to form the gate polysilicon of the transistor.

A first layer of masking made from photoresist501, or more briefly a photoresist mask, is then formed on top of the polysilicon layer500. This first photoresist mask501is produced from a layer of photoresist placed on the polysilicon layer500and suitably irradiated with electromagnetic waves which pass through a suitable photomask in such a way as to cause the polymerization of some of the portions of the layer. With the aid of this first photoresist mask501, the polysilicon layer500is etched, by conventional methods for example, to remove the portion of the polysilicon which is not covered by the polymerized portions of this mask501. As shown inFIG. 2a, this etching makes it possible to form a lateral wall W-S (facing the source side, for example) of the polysilicon gate layer of the transistor. It should be noted that, after the chemical etching, the first photoresist mask501and the polysilicon layer500have an aperture which exposes a surface S1of the oxide layer7having a thickness t2 in the proximity of the lateral wall W-S.

According to the example, the method continues with a stage of forming a P-type body region12which is developed within the epitaxial layer2. In particular, the region12is formed by ion implantation. Preferably, boron ions are implanted with an ion beam F1of suitable energy and density (shown schematically by arrows inFIG. 2a) which strikes the surface S1exposed by the photoresist mask501, passing through the oxide layer7.

Advantageously, an inclined implantation is carried out; in other words, the wafer30is inclined at a suitable angle to the ion beam F1in such a way that the beam of ions can also pass obliquely through the polysilicon layer500, but at the same time this polysilicon layer is shielded by the first photoresist mask501. It should be noted that, advantageously, the first photoresist mask501is automatically aligned with the underlying polysilicon500because it is the product of the same stage of masking (and, in particular, of the same photomask) and etching as that carried out to form the wall W-S.

This provides a highly accurate alignment between the layers500and501, which could not be obtained by forming a separate photoresist layer on the remaining portion of the polysilicon layer500after a stage of etching carried out to form the polysilicon500. The correct alignment of the overlapping layers500and501makes the execution of the inclined implantation highly accurate. This inclined implantation is used to form a body region12extending over the desired length (generally fractions of a μm) under the polysilicon layer500. On completion of the implantation, the first photoresist mask501is removed.

A second layer of masking made from photoresist502, or more briefly a second photoresist mask502, is then formed on top of the polysilicon layer500(FIG. 3a). This second photoresist mask502is produced from a layer of photoresist placed on the polysilicon layer500and suitably irradiated with electromagnetic waves which pass through a suitable photomask in such a way as to cause the polymerization of some of the portions of the layer.

With the aid of this second photoresist mask502, the polysilicon layer500is etched, by conventional methods for example, to remove the portion of the polysilicon which is not covered by the polymerized portions of this mask502. As shown inFIG. 3a, this etching makes it possible to form a lateral wall W-D (facing the drain side, for example) of the polysilicon gate layer of the transistor. This second etching of the polysilicon layer500forms a polysilicon gate layer11. It should be noted that, after etching, the second photoresist mask502and the polysilicon layer500have an aperture which exposes a surface S2of the oxide layer7having a thickness t1 in the proximity of the lateral wall W-D. Additionally, the photoresist layer502shields the gate polysilicon11and the surface of the oxide layer7having a thickness t2.

According to the example, the method continues with a stage of forming an N-type drift region16which is developed within the epitaxial layer2. In particular, the region16is formed by ion implantation. Preferably, phosphorus ions are implanted with an ion beam F2of suitable energy and density (shown schematically by arrows inFIG. 3a) which strikes the surface S2exposed by the photoresist mask502, passing through the oxide layers7and6a. In particular, an inclined implantation is carried out in a similar way to that described for the body region12, in such a way that the ion beam F2can pass obliquely through the gate polysilicon11, but at the same time this polysilicon layer is shielded by the second photoresist mask502. Thus the implanted ions can occupy a region extending for several fractions of a μm under the gate polysilicon11. It should be noted that, advantageously and similarly to the process described for the formation of the body region12, the implantation of the drift region16is carried out with the same photoresist mask502as that made for the forming of the polysilicon gate layer11, and therefore with a mask automatically aligned with the layer11.

After the two stages of implantation of the body region12and the drift region16, a stage of heat treatment is advantageously carried out to enable the corresponding dopants to be fully diffused and activated. It should be noted that this heat treatment can be identical to one of those already specified by the VLSI (Very Large Scale Integration) CMOS platform (carried out, for example, at less than 1000° C. and in particular at approximately 900° C.), and can therefore be such that there is no effect on the electrical characteristics of the CMOS components which can be formed on the said wafer30. It should be noted that, in the conventional manufacture of LDMOS transistors not integrated with CMOS devices, the drift and body regions are produced by a diffusion process which requires heat treatment at a high temperature, generally above 1000° C. In the particular method described above according to the invention, the use of inclined implantation enables the body region12and drift region16to be extended under the polysilicon11even without the heat treatment.

According to a preferred example of embodiment of the invention, CMOS devices (not shown), such as conventional N- and P-channel MOSFETs, are formed on the wafer in addition to the LDMOS transistor. It is clear from the above description that the method according to the invention is compatible with the parallel formation of CMOS devices on the same wafer30. It should also be noted that the advantages offered by inclined implantation and those offered by using the same photoresist layers for forming the polysilicon11and the subsequent implantation are also considerable in the manufacture of an LDMOS with a gate oxide layer having a uniform thickness.

FIG. 3bshows the polysilicon gate layer11, produced by the definition of the layer500, and the gate oxide3produced after a stage of removal of the photoresist502and of the layers of oxide (7and6a) not lying under the polysilicon gate layer11. In one embodiment of the invention, the body region12has a concentration of dopant impurities in the range from 1016to 1019ions/cm3.

According to the example described, and as shown inFIG. 3b, the N−-type region18is then formed, as is usually done for CMOS devices, in other words as an N-type region indicated conventionally by the symbol Nldd (region of weak doping) and having, in the example, a doping in the range from 1015to 1019ions/cm3. The region18can be formed in a conventional way, by the formation of photoresist masks, followed by ion implantation.

Lateral spacers13aand13b, illustrated inFIG. 4, are preferably formed on the lateral walls of the polysilicon gate layer11and of the gate oxide3. These lateral spacers are formed by using prior art technologies comprising stages of chemical vapor phase deposition (CVD) of a suitable material, followed by a stage of reactive ion etching. The lateral spacers13aand13bcan consist of any suitable insulating material such as silicon oxide, polysilicon, or, preferably, silicon nitride. As is known, lateral spacers are commonly used in CMOS processes to create less doped areas of the source and drain regions at the body/drain and body/source junctions, to reduce the electrical fields, and more doped areas of the source and drain regions, automatically aligned with the former areas via the spacers, for more resistive contacting.

A source region14and a drain region15, both of the N+type, are then formed within the regions18and16respectively, by ion implantation through a photoresist mask, as is usually done for the source and drain regions of CMOS devices. For example, the source region14, the drain region15and the drift region16have a conductivity in the range from 1015to 1019ions/cm3or, preferably, in the range from 1016to 1018. Typically, the region18located on the source side is more heavily doped than the drift region16on the drain side.

A body contact region17, of the p+type for example, is formed within the source region14in a similar way to that described above. It should be noted that the signs of the P/N conductivity of the regions1,2,12,14,17,19and15,16and the intensity of the corresponding doping, expressed by the symbols +/−, can differ from those indicated above by way of example and shown in the figures. Moreover, the teachings of the present invention are also applicable to LDMOS transistors having a structure different from that of the CMOS platform described, such as a structure comprising P or N substrates with or without buried layers.

It is important to note that the method described above for manufacturing an N-channel LDMOS transistor on a CMOS platform also enables P-channel LDMOS transistors to be manufactured in parallel on the same wafer30. In other words, the method according to the present invention can be used to form complementary LDMOS transistors on a VLSI CMOS platform. A P-channel LDMOS transistor600which can be formed by the method described above is shown in FIG.8. It will be noted that its layout is similar to that of the transistor ofFIG. 4, except for the sign of the conductivity of some doped regions. In greater detail, the transistor600comprises an N+body region12′, a P+source region14′, an N+source contact region17′, a weakly doped Nldd region18′, a P−drift region16′, and a P+drain region15′.

In particular, the body region12′ and drift region16′ can be produced with the same masks and implantation as those used for the body and drain regions12and16of the N-channel transistor of FIG.4. It should be noted that the method according to the invention which makes use of inclined implantation enables the doping and the lengths of the body and drift regions to be defined in such a way as to optimize the performance of the N-channel or P-channel LDMOS.

We shall now return to the transistor ofFIG. 4, indicated as a whole by100, in which we can distinguish a first active region26and a second active region27, which extend from the surface of the epitaxial layer2towards the interior of the said layer. The first active region26comprises the drain region15and the drift region16. The second active region27comprises the body region12, the source region14, the body contact region17and the N-type region18located under the source spacer13a. The first and second active regions are spaced apart from a region25included in the epitaxial layer2in which part of the transistor's conducting channel will be developed.

It should be noted that the gate oxide layer3extends partially over the separating regions25and that its first portion4is close to the first active region26and its second portion5is close to the second active region27. In other words, the first portion4is located on the “drain side” of the transistor100, and the second portion5is located on the “source side” of the said transistor. In particular, the first portion4and the second portion5are superimposed, respectively, on at least one part of the first active region26and at least one part of the second active region27.

In greater detail, the first portion4of the gate oxide3extends in such a way that it is superimposed on the separating region25and on one part of the drift region16, and the second portion5of the gate oxide3extends in such a way that it is superimposed on at least one part of the body region12. It should be noted that the first portion4of the gate oxide3, close to the drain region15, has a thickness t1 which can be specified in such a way as to obtain a desired breakdown voltage BV. In particular, the breakdown voltage can be increased by increasing the thickness t1. The breakdown voltage can always be varied by the selection of the thickness t1, provided that the doping of the drain and body regions is not such that the value of the breakdown voltage is predetermined.

The increase of the breakdown voltage is correlated with an increase in the distance between the gate polysilicon layer11and the first active region26. As this distance increases, there is a decrease in the electrical field responsible for the breakdown which can occur in the surface area of the epitaxial layer2facing the gate oxide3and corresponding to a portion of the polysilicon layer11close to the drain region16.

Advantageously, the present invention can be used in the field of radio-frequency power applications to obtain a breakdown voltage BV which is higher than that obtainable with conventional LDMOS transistors having uniform oxide. For example, for low-voltage applications, with the values of the thicknesses t1 and t2 indicated above (180 Å and 70 Å), and where the doping of the body region12and drift region16is of the order of 1017ions/cm3, breakdown voltages BV in the range from 16-20 V have been obtained. For conventional LDMOS transistors with uniform gate oxide, having a thickness of 70 Å, and doping comparable to that indicated above, a breakdown voltage of approximately 10 V is obtained, in other words one considerably lower than that obtainable by applying the teachings of the present invention.

Additionally, the increase in the thickness t1, by permitting a limitation of the surface electrical field, reduces the undesired generation of “hot carriers” and enables the gate-drain feedback capacity to be reduced, with a consequent improvement in the performance of the transistor at high frequency. It should be noted that the second portion5of the gate oxide3has a thickness t2 which can be selected in such away as to obtain a predetermined value of the transconductance Gm of the LDMOS transistor. The value of this transconductance is proportional to the gate-body capacity Cox, which is inversely proportional to the distance between the gate electrode and the body region, in other words to the thickness t2 of the second portion5. In particular, decreasing the thickness of this portion5produces an increase in the transconductance Gm and, therefore, an improvement in the performance of the transistor in terms of amplification gain. For example, with thicknesses t1 and t2 of 180 and 70 Å respectively, a Gm of approximately 200 mS/mm was obtained, as against approximately 80 mS/mm which is obtainable with a uniform thickness according to the prior art, and equal to 180 Å=t1=t2 with equal breakdown voltage.

The possibility of selecting the thicknesses of the first portion4and second portion5of the gate oxide3according to the present invention is particularly advantageous. This is because this possibility enables transistors to be produced with a high breakdown voltage BV and a high transconductance, or, at any rate, makes it unnecessary to accept a decrease of the transconductance Gm of the transistor to achieve desired values of the breakdown voltage. By applying the teachings of the invention, it is possible to achieve a dual function of increasing the transconductance Gm while maintaining the breakdown voltage BV at satisfactory levels.

Advantageously, the method according to the invention provides stages of formation of silicide on suitable surfaces of the wafer30of FIG.4. InFIG. 4, the reference numbers19and20indicate a first and a second area respectively, corresponding, respectively, to the surface of the first active region26and that of the second active region27.FIG. 5shows a transistor200with a structure similar to that of the transistor100. The transistor200comprises surface layers of silicide21,22and23, formed, respectively, on the surface of the gate polysilicon11, on the first active area19and on the second active area20. The surface layers21,22and23are, for example, formed from titanium silicide (TiSi2), cobalt silicide (CoSi2) or tungsten silicide (WSi2).

The siliciding of the surfaces of the gate11and of the active areas19and20has the advantage of decreasing their surface resistivity while improving the performance of the transistor. Preferably, the siliciding is carried out by the conventional method known as self-aligned siliciding, or formation of a “salicide” (acronym of “self-aligned silicide”) which permits the formation of layers of silicide aligned with the underlying regions of silicon or polysilicon (salicidizing). For example, the layers of silicide21,22and23are formed by a stage of deposition (by spraying or “sputtering”, for example) of a thin layer of a refractory metal over the whole surface of the wafer30, and in particular over the active areas19and20and on the surface of the polysilicon layer11.

The wafer30is then subjected to heating, allowing a chemical reaction to take place between the deposited metal and the underlying silicon, resulting in the formation of the three regions of silicide21,22and23. Preferably, the metal used for siliciding is titanium or cobalt. For tungsten silicide, direct deposition of WSi2on the polysilicon11can be used, instead of the self-aligned silicide method. It should be noted that the transistor200, provided with the three layers of silicide21,22and23, has a particularly good performance, since the resistances of the gate, source and drain electrodes are significantly reduced. It should also be noted that the transistor200can have a sufficiently high breakdown voltage BV as a result of being designed with a suitable thickness t1, without significant losses in terms of transconductance.

FIG. 6shows a transistor300according to a further embodiment of the invention. In the transistor300, the first active area19of the first active region26is only partially silicidized. In greater detail, the transistor300comprises a layer of silicide24extending over the drain region15but not over the portion of the drift region16closest to the gate structure. The transistor ofFIG. 6provides a breakdown voltage BV, for the same thickness of the first portion4, greater than that obtainable with the transistor200. This is due to the fact that the siliciding of the first active region is only partial, and therefore increases the “distance” between the surface of the gate polysilicon11and the more conductive area of the first active region26, thus reducing the value of the electrical field which can be formed in the epitaxial layer2in the proximity of the gate oxide layer3on the side of the drain16, for the same applied voltage. The increase in the breakdown voltage BV due to the partial siliciding is possible if the doping of the drift region is not so high as to impose a value of the breakdown voltage BV which cannot be modified.

The structure ofFIG. 6not only provides a high breakdown voltage, but also offers high performance (a high transconductance Gm for example), since the resistance of the layers of silicide21,22and24is reduced in any case. It should be noted that the considerable advantages in terms of breakdown and performance offered by partial siliciding as shown in the solution ofFIG. 6can also be obtained for LDMOS transistors which use a gate oxide layer of the conventional type, in other words one of uniform thickness.

The transistor300can be produced from the transistor100by forming a protective or shielding element36. In particular, the shielding element36is formed from electrically insulating material such as an oxide, and preferably a silicon oxide. For example, the forming of the element36comprises the formation of an oxide layer (not shown) over the surface of the transistor100, the forming of a layer of photoresist positioned over this oxide layer, and the partial irradiation of this photoresist with ultraviolet rays through a suitable photomask to cause its polymerization.

Chemical etching is then carried out to remove suitable portions of the layer of photoresist and of the underlying oxide. The chemical etching forms the oxide element36which is positioned in such a way as to shield at least the part of the first active area19which is to be kept free of silicide. In particular, the precision achievable by the oxide masking process described above is such that it is possible to prevent the oxide from covering only the desired portion of the first active region19. In this case, as shown inFIG. 6, the oxide element36also extends over part of the surface of the gate polysilicon11.

After the formation of the oxide element26, the layers of silicide21,22and24are formed in a similar way to that described above with reference to the transistor20(sputtering of the metal, followed by heat treatment). The oxide element36shields the underlying portion of the first active area19, which is therefore not covered by the refractory metal during the sputtering. The oxide element36also acts as a lateral spacer. It should be noted that the method described above for the partial siliciding of the active area19for the LDMOS transistor is particularly advantageous where the LDMOS transistor300is integrated in the wafer30with CMOS devices. This is because, for conventional CMOS devices, there is a known method of using total siliciding of the active area and of the gate polysilicon. The aforementioned method, in which the protective element36is used, enables the total siliciding of the CMOS devices to be carried out simultaneously with the partial siliciding for the LDMOS device formed in the same wafer.

Additionally, it is possible to apply in an advantageous way the process of total or partial siliciding of active areas19′ and20′ (similar to the active areas19and20) and of the polysilicon layer11′ to the P-channel LDMOS transistor600ofFIG. 8, in a similar way to that described with reference toFIGS. 5 and 6. In particular, in the partial siliciding of the active area19′, the portion of the active area26′ close to the polysilicon layer11′ is kept free of silicide, via a protective element similar to the element36.

Additionally, computer simulation was used to compare the performance in terms of saturation current Ids and transconductance Gm of an N-channel LDMOS transistor similar to that ofFIG. 6(in other words, having partial siliciding) with that of a P-channel LDMOS transistor, similar to that ofFIG. 8, having partial siliciding of the active area19′. With reference to this comparison,FIG. 9shows the variation of the gate-source voltage (Vgs) due to the simulation of the transconductance of the N-channel transistor (curve Gm-N), the transconductance of the P-channel transistor (curve Gm-P), the Ids current of the N-channel transistor (curve Ids-N), and the Ids current of the P-channel transistor (curve Ids-P). These variations were obtained for a drain-source voltage (Vds) of 5 V.

It should be noted that the threshold voltages Vt for both transistors are very similar, being approximately 0.5 V in each case. An N-channel transistor of the type shown inFIG. 6was also constructed and tested, showing a performance closely matching that found by the simulations. In particular, a cut-off frequency of more than 20 GHz was measured. For the P-channel transistor, since the cut-off frequency is correlated with the maximum transconductance and the gate capacities, which can be considered similar to those of the N-channel transistor, the cut-off frequency for the P-channel transistor can be estimated as approximately 14-15 GHz. Additionally, since the same parameters for the implantation of the doped regions were assumed for the simulation which was conducted, the P-channel transistor can be considered to have a breakdown voltage of 15 V, in other words a value similar to that of the N-channel transistor.

As stated above, the present invention is also applicable to conventional P-channel or N-channel MOS transistors which can be formed on the same wafer30or on a different wafer. In relation to the above, inFIG. 7the number400indicates an example of an N-channel MOS transistor according to the present invention. The transistor400comprises the wafer30, a first and a second active region33and34, a gate oxide layer32formed over a surface45of the epitaxial layer2, a layer of conductive material35(polysilicon or metal, for example) and two lateral spacers36aand36b. The first active region33comprises a drain region37which is strongly doped (N+) and a region38which is weakly doped (N−). The second active region34comprises a source region39which is strongly doped (N+) and a region40which is weakly doped (N−).

The gate oxide layer32has a first portion41having a first thickness T1 and a second portion42having a second thickness T2 which is different from the thickness T1. In particular, the first portion41is close to the first active region33, and its thickness T1 is greater than the thickness T2. The first portion41of the gate oxide32advantageously has a thickness such that it is possible to obtain breakdown voltages higher than those of conventional MOS transistors using a gate oxide with uniform thickness. With reference to the transconductance Gm of the transistor400, it should be noted that by using different thicknesses of the gate oxide the value of the breakdown voltage can be increased at a cost in terms of transconductance which is smaller than the cost incurred when the uniform thickness is increased with the thickness of the gate oxide in a conventional MOS.

Additionally, the process of siliciding the polysilicon layer35, a first active area33including the surfaces of the regions37and38, and a second active area34including the surfaces of the regions39and40can also be applied to the transistor400, in a similar way to that described with reference toFIGS. 5 and 6. In particular, it is possible to arrange for the first active area33to be only partially silicidized. For example, the weakly doped region38can be kept free of silicide by using a protective oxide element (not shown) similar to the element36of FIG.6.

The method of manufacturing the transistors100,200,300, and400is completed with the formation of suitable metallic contacts (not shown) on the corresponding drain and source regions, and on the body contact region if present. Clearly, a person skilled in the art may further modify and vary the method and transistors according to the present invention, in order to meet contingent and specific requirements, all such modifications and variations being included within the scope of protection of the invention as defined by the following claims.