SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a first spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the first SOT layer, forming a second SOT layer on the IMD layer, forming a first hard mask on the second SOT layer, patterning the first hard mask along a first direction, and then patterning the first hard mask along a second direction.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for fabricating semiconductor device, and more particularly to a method for fabricating magnetoresistive random access memory (MRAM).

2. Description of the Prior Art

Magnetoresistance (MR) effect has been known as a kind of effect caused by altering the resistance of a material through variation of outside magnetic field. The physical definition of such effect is defined as a variation in resistance obtained by dividing a difference in resistance under no magnetic interference by the original resistance. Currently, MR effect has been successfully utilized in production of hard disks thereby having important commercial values. Moreover, the characterization of utilizing GMR materials to generate different resistance under different magnetized states could also be used to fabricate MRAM devices, which typically has the advantage of keeping stored data even when the device is not connected to an electrical source.

The aforementioned MR effect has also been used in magnetic field sensor areas including but not limited to for example electronic compass components used in global positioning system (GPS) of cellular phones for providing information regarding moving location to users. Currently, various magnetic field sensor technologies such as anisotropic magnetoresistance (AMR) sensors, GMR sensors, magnetic tunneling junction (MTJ) sensors have been widely developed in the market. Nevertheless, most of these products still pose numerous shortcomings such as high chip area, high cost, high power consumption, limited sensibility, and easily affected by temperature variation and how to come up with an improved device to resolve these issues has become an important task in this field.

SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a first spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the first SOT layer, forming a second SOT layer on the IMD layer, forming a first hard mask on the second SOT layer, patterning the first hard mask along a first direction, and then patterning the first hard mask along a second direction.

According to another aspect of the present invention, a semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, an inter-metal dielectric (IMD) layer around the first SOT layer, and a second SOT layer on the IMD layer. Preferably, a first corner of the second SOT layer includes a right angle in a top view.

DETAILED DESCRIPTION

Referring toFIGS.1-8,FIGS.1-8illustrate a method for fabricating a MRAM device according to an embodiment of the present invention. As shown inFIG.1, a substrate12made of semiconductor material is first provided, in which the semiconductor material could be selected from the group consisting of silicon (Si), germanium (Ge), Si—Ge compounds, silicon carbide (SiC), and gallium arsenide (GaAs), and a MRAM region14and a logic region16are defined on the substrate12.

Active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and an interlayer dielectric (ILD) layer18could also be formed on top of the substrate12. More specifically, planar MOS transistors or non-planar (such as FinFETs) MOS transistors could be formed on the substrate12, in which the MOS transistors could include transistor elements such as gate structures (for example metal gates) and source/drain regions, spacers, epitaxial layers, and contact etch stop layer (CESL). The ILD layer18could be formed on the substrate12to cover the MOS transistors, and a plurality of contact plugs could be formed in the ILD layer18to electrically connect to the gate structure and/or source/drain region of MOS transistors. Since the fabrication of planar or non-planar transistors and ILD layer is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

Next, metal interconnect structures20,22are sequentially formed on the ILD layer18on the MRAM region14and the logic region16to electrically connect the aforementioned contact plugs, in which the metal interconnect structure20includes an inter-metal dielectric (IMD) layer24and metal interconnections26embedded in the IMD layer24, and the metal interconnect structure22includes a stop layer28, an IMD layer30, and metal interconnections32embedded in the stop layer28and the IMD layer30.

In this embodiment, each of the metal interconnections26from the metal interconnect structure20preferably includes a trench conductor and the metal interconnection32from the metal interconnect structure22on the MRAM region14includes a via conductor. Preferably, each of the metal interconnections26,32from the metal interconnect structures20,22could be embedded within the IMD layers24,30and/or stop layer28according to a single damascene process or dual damascene process. For instance, each of the metal interconnections26,32could further include a barrier layer34and a metal layer36, in which the barrier layer34could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer36could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. In this embodiment, the metal layers36in the metal interconnections26are preferably made of copper, the metal layer36in the metal interconnections32is made of tungsten, the IMD layers24,30are preferably made of silicon oxide such as tetraethyl orthosilicate (TEOS), and the stop layer28is preferably made of nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or combination thereof.

Next, a selective bottom electrode (not shown), a MTJ stack40or stack structure, a selective top electrode (not shown), a first spin orbit torque (SOT) layer44, and a hard mask68are formed on the metal interconnect structure22. In this embodiment, the formation of the MTJ stack40could be accomplished by sequentially depositing a pinned layer, a barrier layer, and a free layer on the bottom electrode. In this embodiment, the selective bottom electrode and top electrode could be made of conductive material including but not limited to for example Ta, Pt, Cu, Au, Al, or combination thereof. The pinned layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB) or cobalt-iron (CoFe). Alternatively, the pinned layer could also be made of antiferromagnetic (AFM) material including but not limited to for example ferromanganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), or combination thereof, in which the pinned layer is formed to fix or limit the direction of magnetic moment of adjacent layers. The barrier layer could be made of insulating material including but not limited to for example oxides such as aluminum oxide (AlOx) or magnesium oxide (MgO). The free layer could be made of ferromagnetic material including but not limited to for example iron, cobalt, nickel, or alloys thereof such as cobalt-iron-boron (CoFeB), in which the magnetized direction of the free layer could be altered freely depending on the influence of outside magnetic field. Preferably, the first SOT layer44is serving as a channel for the MRAM device as the first SOT layer44could include metals such as tantalum (Ta), tungsten (W), platinum (Pt), or hafnium (Hf) and/or topological insulator such as bismuth selenide (BixSe1-x). The hard mask68preferably includes conductive material or metal such as ruthenium (Ru), but not limited thereto.

Next, as shown inFIG.2, one or more etching process could be conducted to by using a patterned mask (not shown) as mask to remove part of the hard mask68, part of the first SOT layer44, part of the MTJ stack40, and part of the IMD layer30to form a MTJ48on the MRAM region14, and the patterned mask is removed thereafter. It should be noted that a reactive ion etching (RIE) process or an ion beam etching (IBE) process could be conducted at this stage to remove the MTJ stack40and the IMD layer30in this embodiment for forming the MTJ48. Due to the characteristics of the IBE process, the top surface of the remaining IMD layer30is slightly lower than the top surface of the metal interconnections32after the IBE process and the top surface of the IMD layer30also reveals a curve or an arc. It should also be noted that as the IBE process is conducted to remove part of the IMD layer30, part of the metal interconnection32could be removed at the same time to form inclined sidewalls on the surface of the metal interconnection32immediately adjacent to the MTJ48.

Next, a cap layer50is formed on the MTJ48while covering the surface of the IMD layer30on the MRAM region14and the logic region16. In this embodiment, the cap layer50preferably includes silicon nitride, but could also include other dielectric material including but not limited to for example silicon oxide, silicon oxynitride (SiON), or silicon carbon nitride (SiCN).

Referring toFIG.3, the left portion ofFIG.3illustrates a top view for fabricating the MRAM device in the MRAM region14followingFIG.2, the top right portion ofFIG.3illustrates a cross-section view for fabricating the MRAM device taken along the X-direction arrow from the left portion, and the bottom right portion ofFIG.3illustrates a cross-section view for fabricating the MRAM device taken along the Y-direction arrow from the left portion. As shown inFIG.3, it would be desirable to first follow the processes conducted inFIGS.1-2by forming an array made of a plurality of MTJs48on the MRAM region14and then conduct an etching process with or without using a patterned mask such as patterned resist to remove part of the cap layer50for forming a spacer66on sidewalls of the MTJ48, the first SOT layer44, and the hard mask68, in which the spacer66has a substantially L-shape cross-section. Next, a deposition process such as an atomic layer deposition (ALD) process is conducted to form an inter-metal dielectric (IMD) layer52on the hard mask68, the spacer66, and the IMD layer30, and a planarizing process such as chemical mechanical polishing (CMP) process or etching back process is conducted to remove part of the IMD layer52so that the top surface of the remaining IMD layer52is even with the top surface of the spacer66and hard mask68.

Next, a second SOT layer70, a hard mask72, and another hard mask74are formed on the IMD layer52to cover the hard mask68and spacer66. In this embodiment, the second SOT layer70preferably includes metal nitride such as TiN, the hard mask72includes metal such as Ta, and the hard mask74includes conductive or dielectric material such as TiN or silicon oxide, but not limited thereto. It should be noted that the second SOT layer70could also be serving as a channel for the MRAM device as the second SOT layer70and the first SOT layer44could be made of same or different material. For instance, even though the second SOT layer70preferably includes TiN in this embodiment, the second SOT layer70could also include tantalum (Ta), tungsten (W), platinum (Pt), or hafnium (Hf) and/or topological insulator such as bismuth selenide (BixSe1-x).

Next, a photo-etching process could be conducted by using a patterned mask (not shown) such as patterned resist as mask to remove part of the hard mask74for forming an opening76exposing the top surface of the hard mask74. It should be noted that the etching process conducted at this stage is preferably carried out along a first direction such as Y-direction to pattern or remove part of the hard mask74so that the opening76formed according to the top right portion ofFIG.3is preferably extending along the Y-direction in the patterned hard mask74and exposing the top surface of the hard mask72.

Referring toFIG.4, the left portion ofFIG.4illustrates a top view for fabricating the MRAM device in the MRAM region14followingFIG.3, the top right portion ofFIG.4illustrates a cross-section view for fabricating the MRAM device taken along the X-direction arrow from the left portion, and the bottom right portion ofFIG.4illustrates a cross-section view for fabricating the MRAM device taken along the Y-direction arrow from the left portion. As shown inFIG.4, another photo-etching process could be conducted by using another patterned mask (not shown) such as patterned resist as mask to remove part of the hard mask74once more for forming an opening78exposing the top surface of the hard mask72. In contrast to the aforementioned photo-etching process conducted along the Y-direction for patterning the hard mask74, the photo-etching process conducted at this stage is carried out along a second direction such as an X-direction perpendicular to the first direction so that the opening78shown in the bottom right portion ofFIG.4is therefore formed extending along the X-direction in the patterned hard mask74and exposing the top surface of the hard mask72. The opening76shown on the top right portion ofFIG.4on the other hand is still extending along the Y-direction and exposing the top surface of the hard mask72. As shown in the left portion ofFIG.4taken along the top view perspective, the hard mask74after being patterned by two photo-etching processes along two different directions is now divided into a plurality of rectangles or rectangular blocks not contacting each other directly instead of rectangular strips extending along the Y-direction shown in previous figures.

Referring toFIG.5, the left portion ofFIG.5illustrates a top view for fabricating the MRAM device in the MRAM region14followingFIG.4, the top right portion ofFIG.5illustrates a cross-section view for fabricating the MRAM device taken along the X-direction arrow from the left portion, and the bottom right portion ofFIG.5illustrates a cross-section view for fabricating the MRAM device taken along the Y-direction arrow from the left portion. As shown inFIG.5, another photo-etching process is then conducted by using the patterned hard mask74as mask to remove part of the hard mask72and part of the second SOT layer70through the openings76and78formed previously and then expose the top surface of the IMD layer52. It should be noted that at this stage the pattern of the hard mask74is preferably transferred to the hard mask72and second SOT layer70underneath so that the hard mask72and second SOT layer70now include same pattern as the hard mask74if viewed under a top view perspective.

Referring toFIG.6, the left portion ofFIG.6illustrates a top view for fabricating the MRAM device in the MRAM region14followingFIG.5, the top right portion ofFIG.6illustrates a cross-section view for fabricating the MRAM device taken along the X-direction arrow from the left portion, and the bottom right portion ofFIG.6illustrates a cross-section view for fabricating the MRAM device taken along the Y-direction arrow from the left portion. As shown inFIG.6, one or more etching process could be conducted to remove the hard mask74and hard mask72to expose the top surface of the second SOT layer70. As shown in the left portion ofFIG.6, after being patterned by two photo-etching process in both X-direction and Y-direction, the second SOT layer70viewed under the top view perspective preferably includes a plurality of rectangles or rectangular blocks, in which each of the four corners of the second SOT layer70includes a right angle or more specifically a 90 degrees included angle.

Next, as shown inFIG.7, another IMD layer56is formed on the second SOT layer70and the IMD layer52. In this embodiment, each of the IMD layer52and IMD layer56preferably includes an ultra low-k (ULK) dielectric layer including but not limited to for example porous material or silicon oxycarbide (SiOC) or carbon doped silicon oxide (SiOCH). Next, a planarizing process such as chemical mechanical polishing (CMP) process or etching back process is conducted to remove part of the IMD layer56while the top surface of the remaining IMD layer56is still higher than the top surface of the second SOT layer70.

Next, a pattern transfer process is conducted by using a patterned mask (not shown) to remove part of the IMD layer56, part of the IMD layer52, part of the IMD layer30, and part of the stop layer28on the MRAM region14and logic region16to form contact holes (not shown) exposing the metal interconnections26underneath and conductive materials are deposited into the contact hole afterwards. For instance, a barrier layer selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and metal layer selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP) could be deposited into the contact holes, and a planarizing process such as CMP could be conducted to remove part of the conductive materials including the aforementioned barrier layer and metal layer to form metal interconnections58in the contact holes electrically connecting the metal interconnections26.

Next, as shown inFIG.8, a stop layer60is formed on the MRAM region14and logic region16to cover the IMD layer56and metal interconnections58, an IMD layer62is formed on the stop layer60, and one or more photo-etching process is conducted to remove part of the IMD layer62, part of the stop layer60, and part of the IMD layer56on the MRAM region14and logic region16to form contact holes (not shown). Next, conductive materials are deposited into each of the contact holes and a planarizing process such as CMP is conducted to form metal interconnections64connecting the MTJ48and metal interconnections58underneath, in which the metal interconnections64on the MRAM region14directly contacts the second SOT layer70underneath while the metal interconnections64on the logic region16directly contacts the metal interconnections58on the lower level.

In this embodiment, the stop layers60and28could be made of same or different materials, in which the two layers60,28could all include nitrogen doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or combination thereof. Similar to the metal interconnections formed previously, each of the metal interconnections64could be formed in the IMD layer62through a single damascene or dual damascene process. For instance, each of the metal interconnections64could further include a barrier layer and a metal layer, in which the barrier layer could be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) and the metal layer could be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl), and cobalt tungsten phosphide (CoWP). Since single damascene process and dual damascene process are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.