Mitigation of readout error in a quantum computation

Embodiments are provided for error mitigation in quantum programs. In some embodiments, a system can include a processor that executes computer-executable components stored in memory. The computer-executable components include a compilation component that causes encoding of one or more qubits according to a circular repetition code at a time after operations on the one or more qubits and before readout.

BACKGROUND

One or more embodiments of the invention relate to mitigation of readout error in a quantum computation.

Quantum computers are constructed from quantum devices coupled to an environment that may decohere and relax quantum information contained in the quantum device. Thus, such devices may be subject to external noise. As a result, a quantum processor formed by quantum devices may be noisy and errors may be present in quantum computations using the quantum processor. Such noise and errors may be present irrespective of the architecture of the quantum devices.

Readout error may arise from a quantum measurement of the quantum devices utilized in a quantum computation, after the quantum devices have been manipulated according to the operations defining the quantum computation. Accordingly, improved technologies for mitigation of readout error may be desired.

SUMMARY

According to an embodiment, a system is provided. The system includes a processor that executes computer-executable components stored in memory. The computer-executable components include a compilation component that cause encoding of one or more qubits according to a circular repetition code at a time after operations on the one or more qubits and before readout. Thus, measurements defining the readout are the only operations acting on encoded qubit state(s), whereas all other operations describing the preparation of the joint state of the one or more qubits can be implemented without encoding. Therefore, by encoding the one or more qubits using a circular repetition code, readout errors can be reduced in a quantum computation involving the encoded qubit(s).

In addition, or in other embodiments, the computer-executable components also include a branch identification component that identifies a first chain of ancilla qubits coupled to a particular qubit of the one or more qubits, a second chain of ancilla qubits coupled to the particular qubit, and a flag qubit joining the first chain of ancilla qubits and the second chain of ancilla qubits. The encoding of the one or more qubits includes encoding the particular qubit by encoding the first chain of ancilla qubits using repetition coding, and encoding the second chain of ancilla qubits using the repetition encoding.

According to another embodiment, a computer-implemented method is provided. The computer-implemented method includes causing, by a processor, encoding of one or more qubits according to a circular repetition code at a time after operations on the one or more qubits and before readout.

According to a further embodiment, a computer program product for mitigation of readout errors in a quantum computation. The computer program product includes a computer-readable storage medium having program instructions embodied therewith. The program instructions are executable by a processor to cause the processor to cause encoding of one or more qubits using a circular repetition code at a time after operations on the multiple qubits and before readout.

DETAILED DESCRIPTION

Embodiments of this disclosure address the issue of readout error mitigation in a quantum computation. To that end, embodiments of this disclosure utilize an exemplary form of a quantum repetition code that leverage redundancy to protect quantum information from the effects of noise. Specifically, embodiments of this disclosure cause the encoding of the respective states of one or several qubit devices according to a circular repetition encoding. Those encoded state(s) are encoded at a time after operations on the one or more qubit devices are performed and before readout. Accordingly, measurements defining the readout are the only operations acting on the encoded qubit state(s), whereas all other operations defining the quantum computation can be implemented without encoding. The circular repetition encoding leverages closed-loop chains of qubit devices. A qubit device in such a chain is identified for encoding. That qubit device is referred to as a root qubit. First and second chains of ancilla qubit devices are identified in the close-loop chain. Each of those chains of ancilla qubit devices are coupled to the root qubit. Another qubit device, referred to as a flag qubit, also is identified. The flag qubit joins the first and second chain of ancilla qubits.

A sequence of controlled NOT (CNOT) gates define a repetition encoding in each one of the first and second chain of ancilla qubits. A CNOT gate also couples a qubit device at an end of the first chain of ancilla qubits. Another CNOT gate further couples the flag qubit to a qubit device at the end of the second chain of ancilla qubits. In both cases, the flag qubit is the target of such CNOT gates. Accordingly, the repetition encoding of both chains of ancilla qubits in conjunction with the respective coupling of those chains to the flag qubit constitute the circular repetition encoding. By measuring the single-qubit state of the flag qubit the quality of the encoding can be detected. A non-faulty encoding can result in a majority-vote evaluation that provide an error-mitigated outcome for the single-qubit state of the root qubit.

The exemplary circular repetition encoding described herein can be applied in various types of quantum computations. Results of quantum computation of electronic structure and time propagation of model Hamiltonians reveal that the circular repetition encoding yields greater accuracy relative to commonplace techniques for readout error mitigation.

Exemplary embodiments of the disclosure may provide several advantages relative to commonplace approaches to mitigation of readout errors, such as readout calibration matrices, non-circular repetition codes, and small stabilizer codes. As an example, embodiments of this disclosure avoid imposing constraints on the quantum circuit to be encoded and can be utilized to encode the single-qubit state of any number of qubit devices. In sharp contrast, commonplace stabilizer codes can only encode the single-qubit states of two qubit devices, and can be applied to a limited set of logical gates. As another example, by reducing readout errors, embodiments of this disclosure can yield more accurate estimates from a quantum computation. As a result, embodiments described herein can be used to approach to chemical accuracy and better estimation of expectation values and dynamics of physical observables. To that point, not only can the embodiments of this disclosure be applied to variational algorithms, but the embodiments also can be applied in simulations that involve measurement of observables in a certain wavefunction generated by a quantum circuit. As yet another example, embodiments of this disclosure do not scale exponentially, in sharp contrast to classical post-measurement readout error mitigation. Accordingly, circular repetition encoding of many qubits can be implemented, with ensuing reduction of readout error and associated improved accuracy of quantum computations that utilize the encoded qubits.

Some exemplary embodiments of this disclosure are described with reference to qubit devices and quantum circuits simply for the sake of illustration. The disclosure, however, is not limited in that respect. Indeed, the principles of this disclosure can be applied to any representation of quantum operations and any type of quantum devices (such as qudit devices) utilized in a physical implementation of a quantum computer. Further, simply as an illustration, the improvements afforded by the circular repetition strength of this disclosure are shown for quantum computations of electronic structure calculations and time propagation of model Hamiltonians. Again, the principles of this disclosure are not limited to those types of quantum computations. Indeed, the circular repetition encoding of this disclosure can be broadly applied in quantum computations in a wide variety of disciplines, such as physics, chemistry, materials science, cybersecurity, bioinformatics, and the like.

With reference to the drawings,FIG.1illustrates a non-limiting example of an operational environment100for readout error mitigation in a quantum computation, in accordance with one or more embodiments described herein. The operational environment100includes a user device110(e.g., a classical computer) operatively coupled to a compiler system120. The user device110can send data defining a quantum program112to a compiler system120for compilation. The quantum program112can define one or several quantum algorithms. Thus, the quantum program112can include a group of quantum circuits114that represents at least a portion of the quantum program112. The group of quantum circuits114includes one or multiple quantum circuits. In some cases, the group of quantum circuits114includes particular quantum circuits representing a quantum algorithm (such as a variational quantum algorithm) included in the quantum program112.

Each quantum circuit in the group of quantum circuits114can include one or several of various quantum gates. Those quantum gates can include, for example, a Pauli gate (X gate or Y gate, for example) representing a Pauli operator; a Hadamard gate; a rotation gate (Rzgate and phase shift gate, for example); a controlled-phase shift gate; a CNOT gate; a Toffoli (or controlled-controlled-NOT) gate; a swap gate; a Fredkin gate; among many other gates. The data defining the quantum program112can include, in some embodiments, first data defining one or several first quantum gates that constitute a first quantum circuit of the group of quantum circuits114. The data defining the quantum program112also can include second data defining one or several second quantum gates that constitute a second quantum circuit of the group of quantum circuits114. In addition, or in some embodiments, rather than defining particular quantum gates, the data defining the quantum program112can include first data defining one or several general unitary matrices U constituting at least one of the group of quantum circuits114.

The compiler system120can receive the data defining the quantum program112. In some embodiments, as is illustrated inFIG.2, the compiler system120can include an ingestion component210that can receive the data defining the quantum program112. As is also illustrated inFIG.2, the compiler system120also can include other components, one or several processors260, and one or several memory devices270(referred to as memory270). The processor(s)260and the memory270can be electrically, optically, and/or communicatively coupled to one another.

Back to referring toFIG.1, the compiler system120can then compile the quantum program112for execution on quantum hardware130. In some embodiments, the quantum hardware130embodies, or includes, a cloud-based quantum computer. In other embodiments, the quantum hardware130embodies, or includes, a local quantum computer. Regardless of its spatial footprint, the quantum hardware130can include multiple qubit devices140arranged in a particular layout. Qubit devices can be solid-state devices of one of several types. Each qubit device of the qubit devices140is coupled to an environment that decoheres and relaxes quantum information contained in the qubit device. Thus, the quantum hardware130can be noisy. Simply as an illustration, qubit devices can be Josephson junction devices, semiconductor quantum-dots, or defects in a semiconductor material (such as vacancies in Si and Ge). In other embodiments, the qubit devices can include atomic qubits assembled in an ion-trap. For instance, the atomic qubits can be embodied in a calcium ion, an ytterbium ion, or similar ions. In one embodiment, the quantum hardware130includes multiple qubit devices124, each embodied in a transmon.

In some cases, the particular layout of the multiple qubit devices140can exhibit heavy hexagonal connectivity. Such a layout includes one or several chains of qubits devices forming a closed-loop chain. Accordingly, the qubit devices in such a chain are said to have circular connectivity. Diagram300inFIG.3schematically depicts a closed-loop chain of qubit devices. In some cases, the particular layout of the multiple qubit devices140can exhibit connectivity that supports several closed-loop chains of qubits. Each one of those several closed-loop chains of qubits can permit encoding a qubit according to the circular repetition encoding described herein.

With further reference toFIG.1, the compiler system120can leverage the circular connectivity of qubit devices included in the qubit devices140during compilation of the quantum program112. Specifically, the compiler system120can cause the encoding of one or more qubits within a closed-loop chain according to a circular repetition (CR) encoding.

Because the dominant source of inaccuracies affecting readout operations in the quantum hardware130can be represented by bit flips in the computational basis, the compiler system120can implement repetition encoding schemes specifically designed to detect and correct that form of readout errors. Specifically, consider a particular qubit device in a closed-loop chain of qubit devices that is given in a generic state a|0+b|1. That particular qubit device is herein referred to as a root qubit. By using nrepadditional qubit devices initially prepared in state |0, the following mapping can be represented as:
(a|0+b|1)|0 . . . 0a|0 . . . 0+b|1 . . . 1.  (1)
The nrepadditional qubit devices are herein referred to as ancilla qubits. In the example shown in diagram350inFIG.3, the root qubit is denoted by q and the ancilla qubits are shown as white circles. A first subset of the ancilla qubits forms a first repetition branch. Qubit devices in the first repetition branch are denoted by a1, a2, . . . , aN−1, and aN, with N=nrep/2. A second subset of the ancilla qubits forms a second repetition branch. Qubit devices in the second repetition branch are denoted by b1, b2, . . . , bN−1, and bN. For simplicity of explanation, embodiments of this disclosure are described with respect to repetition codes for which nrep+1 is odd.

The foregoing mapping represents a repetition encoding and can be formally generated by nrepstabilizers {Z0Z1; Z1Z2, . . . , Znrep−1Znref}, where Ziis a Pauli σzquantum gate applied to qubit device i. The root qubit is associated with index i=0. It is noted that the state a|0 . . . 0+b|1 . . .is not equivalent to nrep+1 copies of the state a|0+b|1, as this would in general violate the no-cloning theorem, and only the eigenvalues associated with the Z operator of the original single-qubit state are stored redundantly. As a result, errors caused by the bit flip channel, which are associated with the Pauli X operator, can be detected and mitigated with such a repetition encoding.

The compiler system120can implement the circular repetition encoding at a time after operations on one or more qubits and before quantum measurements (referred to as readout). That is, those measurements are the only operations acting on encoded states. All other operations describing the preparation of the joint state of one or more root qubits can be implemented without encoding. Such other operations represent at least a portion of a particular quantum computation and can be generically represented by a unitary U acting on one or more root qubits being encoded. Therefore, that unitary can be followed by one or more second unitaries, each representing the operations pertaining to circular repetition encoding of a respective one of the root qubit(s) being encoded. In addition, in some embodiments, each of the one or more second unitaries has the same structure of encoding operations. Accordingly, a same encoding unitary can be utilized to encode each qubit in a set of multiple qubits being encoded. Accordingly, each one of multiple root qubits can be encoded individually, resulting in the circular repetition encoding of the multiple root qubits.

As an illustration,FIG.4Apresents a schematic quantum circuit400depicting the temporal relationship between a unitary410, denoted by U, representing a one-qubit computation and a second unitary420, denoted by Uencoding, representing the operations pertaining to the circular repetition encoding of a root qubit q. Measurements are schematically depicted as dial icons on the right-hand side inFIG.4A.

As another illustration,FIG.4Bpresents a schematic quantum circuit450depicting the temporal relationship between a unitary460, denoted by U, representing a two-qubit computation and two unitaries each representing the operations pertaining to the circular repetition encoding of a respective root qubits. A first unitary470, denoted by U(0)encoding, encodes a first root qubit q0by operating of two first repetition branches A0and B0and a flag qubit f0. Repetition branch A0includes ancilla qubits denoted by a01, a02, . . . , a0N−1, and a0N, and repetition branch B0includes ancilla qubits denoted by b01, b02, b0N−1, and b0N. A second unitary470, denoted by U(1)encoding, encodes a second root qubit q1by operating of two repetition branches A1and B1and a flag qubit f1. Repetition branch A1includes ancilla qubits denoted by a11, a12, . . . , a1N−1, and a1N, and repetition branch B1includes ancilla qubits denoted by b11, b12, . . . , b1N−1, and b1N. Thus, root qubits q0and q1are encoded individually (e.g., independently from one another) and in parallel. Further, U(0)encodingand U(1)encodinghave the same structure of encoding operations. After q0and q1are encoded individually, each of those encoded qubits can be placed in a network of encoded qubits provided that circular connectivity is present in a layout of qubits including q0and q1. Measurements are again schematically depicted as dial icons on the right-hand side inFIG.4B.

A circular repetition encoding can be performed by applying, for example, nrepCNOT gates targeting nrepancilla qubits. To the end, in some embodiments, the compiler system120can include a branch identification component220(FIG.2) that can identify two sets of ancilla qubits, each set having nrepqubit devices. Each one of those sets constitutes a repetition branch. The branch identification component220also can identify a root qubit (e.g., q inFIG.3) and another qubit device that is connected to both set of ancilla qubit devices. That other qubit device serves as a flag qubit (denoted by f in diagram350inFIG.3).

As mentioned, a unitary Uencodingrepresents the circular repetition encoding. The unitary Uencodingmaps each root qubit to its encoded version by operating on an ancillary register corresponding to first and second repetition branches respectively defined by the first and second sets of ancilla qubits. That unitary Uencodingcan be applied to encode each qubit in a set of multiple qubits being encoded. As described above, for two qubits, U(0)encoding(FIG.4B) is the same as Uencodingand U(1)encoding(FIG.4B) also is the same as Uencoding.

In some cases, Uencodingincludes an arrangement of CNOT) operations that define the encoding. Such an arrangement can correspond to a sequence of CNOT operations that sequentially target ancilla qubits (seeFIG.2for an example). The compiler system120can configure Uencoding. To that end, in some embodiments, the compiler system120can include a compilation component230that can receive data defining a first repetition branch, a second repetition branch, a flag qubit, and a root qubit. In some cases, such data can be received from the branch identification component220. In other cases, the compilation component220can load such data from layout(s)272. The compilation component230can then configure Uencodingusing the received data.

The circular repetition encoding utilizes a split-repetition layout in which the first repetition branch and the second repetition branch are connected by the flag qubit that is initialized in state |0. Each one of the first repetition branch and the second repetition branch has a same number of qubit devices (nrep, as is described above) and connects to the flag qubit by a CNOT gate, where the flag qubit is the target in both cases. The flag qubit is denoted by f in diagram350inFIG.3. Because circular repetition encoding relies on repetition branches of auxiliary/ancillary/ancilla qubits, sensitivity to error-propagation can be reduced relative to repetition encoding using a single chain of 2N ancilla qubits. Further, many of the CNOT gates in Uencodingcan be executed in parallel, thus reducing the effective encoding circuit depth.

FIG.5Aillustrates a non-limiting example of Uencoding, in accordance with aspects described herein. A unitary510embodies Uencoding. The unitary510includes a first sequence of CNOT gates that operate on respective ancilla qubits of the first repetition branch. The unitary510also includes a second sequence of CNOT gates that operate on respective ancilla qubits of the second repetition branch. As is illustrated inFIG.5A, the first sequence of CNOT gates includes a first CNOT gate520(1) coupling the root qubit and a1, with the root qubit being the control and a1being the target; a second CNOT gate520(2) coupling a1and a2, with a1being the control and a2being the target; continuing in similar succession (depicted by a broken CNOT gate) up to a CNOT gate520(N) coupling aN−1and aN, with aN−1being the control and aNbeing the target. Further, the second sequence of CNOT gates includes a first CNOT gate540(1) coupling the root qubit and b1, with the root qubit being the control and b1being the target; a second CNOT gate540(2) coupling b1and b2, with b1being the control and b2being the target; continuing in similar succession (depicted by a broken CNOT gate) up to a CNOT gate540(N) coupling bn−1and bN, with bN−1being the control and bNbeing the target. Because the repetition encoding is a circular repetition encoding, a CNOT gate530couples the flag qubit to ancilla qubits aN, with aNbeing the control and the flag qubit being the target. In addition, a CNOT gate550also couples the flag qubit to ancilla qubits bN, with bNbeing the control and the flag qubit being the target.

Although inFIG.5Athe second repetition branch is used after the first repetition branch in the circular repetition encoding, the disclosure is not limited in that respect. Indeed, one of the strengths of circular repetition encoding is the parallel execution of CNOT gates in the first repetition branch and CNOT gates in the second repetition branch. In such a scenario, for example, the CNOT gate520(2) and the CNOT gate540(2) would be aligned inFIG.5A.

FIG.5Bpresents a schematic quantum circuit560depicting the temporal relationship between a unitary562, denoted by U, representing a two-qubit computation and two unitaries each representing the operations pertaining to the circular repetition encoding of respective root qubits q0and q1. The two unitaries include U(0)encodingand U(1)encodingfor encoding of two qubits, in accordance with aspects described herein. A unitary565embodies U(0)encoding. The unitary565includes a first sequence of CNOT gates that operate on respective ancilla qubits of the first repetition branch A0. The unitary565also includes a second sequence of CNOT gates that operate on respective ancilla qubits of the second repetition branch B0. As mentioned, each of those branches are coupled to root qubit q0. As is illustrated inFIG.5B, the first sequence of CNOT gates includes a first CNOT gate570(1) coupling the root qubit q0and a01, with the root qubit being the control and a01being the target; continuing in succession up to a CNOT gate570(N) coupling a0N−1and a0N, with a0N−1being the control and a0Nbeing the target. Further, the second sequence of CNOT gates includes a first CNOT gate576(1) coupling the root qubit q0and b01, with the root qubit being the control and b01being the target; continuing in succession up to a CNOT gate576(N) coupling b0n−1and b0N, with b0N−1being the control and b0Nbeing the target. Because the repetition encoding is a circular repetition encoding, a CNOT gate572couples the flag qubit f0to ancilla qubits a0N, with a0Nbeing the control and the flag qubit f0being the target. In addition, a CNOT gate574also couples the flag qubit f0to ancilla qubits b0N, with b0Nbeing the control and the flag qubit being the target.

A unitary590embodies U(1)encoding. The structure of operations in the unitary590is the same as in the unitary565. Specifically, the unitary590includes a first sequence of CNOT gates that operate on respective ancilla qubits of the first repetition branch A1. The unitary590also includes a second sequence of CNOT gates that operate on respective ancilla qubits of the second repetition branch B1. As mentioned, each of those branches are coupled to root qubit q1. As is illustrated inFIG.5B, the first sequence of CNOT gates includes a first CNOT gate580(1) coupling the root qubit q1and a11, with the root qubit being the control and a11being the target; continuing in succession up to a CNOT gate580(N) coupling a1N−1and a1N, with a1N−1being the control and a1Nbeing the target. Further, the second sequence of CNOT gates includes a first CNOT gate586(1) coupling the root qubit q1and b11, with the root qubit being the control and b01being the target; continuing in succession up to a CNOT gate586(N) coupling b1n−1and b1N, with b1N−1being the control and b1Nbeing the target. Because the repetition encoding is a circular repetition encoding, a CNOT gate582couples the flag qubit f1to ancilla qubits a1N, with a1Nbeing the control and the flag qubit f1being the target. In addition, a CNOT gate574also couples the flag qubit f1to ancilla qubits b1N, with b1Nbeing the control and the flag qubit being the target.

As mentioned, U(0)encodingand U(1)encodinghave the same structure of encoding operations. As such, the unitary590and the unitary565have the same structure of encoding operations, and, thus, can be referred to as symmetrical relative to one another. Again, although inFIG.5Bthe second repetition branches B0and B1are used after first repetition branches A0and A1in their respective circular repetition encoding, the disclosure is not limited in that respect. As mentioned, one of the strengths of circular repetition encoding is the parallel execution of CNOT gates in a first repetition branch and CNOT gates in a second repetition branch. To that point, the unitary565and the unitary590can be implemented concurrently, resulting in the circular repetition encoding of the root qubit q0and the root qubit q1in parallel and independently from one another.

As in the general case, the initial unencoded state of a root qubit can be expressed as (a|0+b|1)|0 . . . 0|0 . . . 0|0, where the first qubit device and the last qubit device correspond to the root qubit and flag qubit, respectively, and the two sets of qubits in between constitute the two repetition branches, e.g., {a1, a2, . . . , aN−1, aN} and {b1, b2, . . . , bN−1, bN}. See, e.g.,FIG.3.

In the absence of error during the split repetition encoding, the state after Uencoding can be expressed as (a|0|0 . . . 0|0 . . . 0+b|1|1 . . . 1|1 . . . 1)|0. Indeed, the last CNOT gates (e.g., gate430and gate450inFIG.5) targeting the flag qubit from each branch leave the flag qubit in |0because both control qubit devices (aNand bN) are in the same state. However, if one qubit flips on one of the repetition branches, e.g., the first repetition branch, the state becomes (a|0|0 . . . 0|0 . . . 1+b|1|1 . . . 0|1 . . . 1)|1). Therefore, a state |1observed of the flag qubit detects an error during the encoding; e.g., detects faulty encoding. In such case, the associated outcome bit string can be discarded. Conversely, the flag qubit being in state |0represent non-faulty encoding. Results under non-faulty encoding are retained and a majority vote evaluation is performed on the other qubits. In some embodiments, the monitoring component240can determine the state of the flag qubit and, in response, can either discard or retain the outcome bit string. The evaluation component150can perform a majority-vote evaluation when the outcome bit stream is retained.

For qubit devices140arranged in a layout that includes multiple replicas of a closed-loop chain of qubits, or an arrangement that has circular connectivity (seeFIG.3for an example), multiple root qubits corresponding to respective replicas can be encoded individually (e.g., independently from one another) and in parallel with one another. Because the circular repetition encoding of multiple qubits can be performed for each one of the multiple qubits and in parallel with one another, the circular repetition encoding is scalable. Each of these encoded root qubits and associated closed-loop chain of qubits can be leveraged in a multi-qubit quantum computation using the qubit devices140.

After one or more instances of Uencodinghave been configured for respective one or more qubits, the compiler system120can generate a compiled version of the quantum program112. The compiled version includes one or several compiled quantum circuits124including a CR repetition unitary128(e.g., Uencoding). The compiler system120can cause the execution of a compiled version of the quantum program112. Causing the execution of the compiled version of the quantum program112can include sending the one or more compiled quantum circuits124for execution by the quantum hardware130. Causing the execution of the one or more compiled quantum circuits124can include causing execution of operations in a quantum computation defined by the quantum program112, and also causing encoding of one or more qubits according to a circular repetition code at a time after the execution of the operations, on the one or more qubits, and before readout. Further, causing the execution of the compiled version of the quantum program112also includes causing measurement, in the computational basis, of all qubit devices represented in the compiled quantum circuits124. In other words, part of the execution of the compiled version of the quantum program112includes measuring all qubit devices utilized in the quantum computation defined by the quantum program112and second qubit devices utilized in the circular repetition encoding. In some embodiments, the compiler system120can include a monitoring component240(FIG.2) that causes measurement, in the computational basis, of all such qubit devices.

The compiler system120can receive readout data resulting from those measurements and can then implement a majority vote evaluation in order to recover the measurement values for the root qubit(s). More specifically, error-mitigated readout results can be recovered for individual root qubits via the majority vote evaluation as applied in a postprocessing stage on the outcome bit strings. In particular, any bit string b0b1. . . bnrepresulting from a quantum measurement in the computational basis is decoded as 0 or 1 depending on which of the two values appears more often in the nrep+1 output bits. The decoding is successful when less than (nrep+1)=2 bit values were flipped by noise. To that end, the compiler system120can receive readout data from root qubit(s), flag qubit(s), and ancilla qubits. The compiler system120can then implement the majority vote evaluation using the received readout data. In some embodiments, as is illustrated inFIG.2, the compiler system120can include an evaluation component250that can receive the readout data and can retain the readout data in the memory270. The readout data can be retained in one or several records276(referred to as readout data276). The evaluation component250can then perform the majority-vote procedure described above.

There are several layouts of the qubit devices140(FIG.1) that can include a group of multiple qubit devices having circular connectivity. Quantum computations that use such layouts can utilize the circular repetition encoding described herein. Simply for the purpose of illustration,FIG.6Apresents a non-limiting example of a layout600of qubit devices140, in accordance with one or more embodiments described herein. In the layout600, 20 qubit devices are arranged in a geometry that exhibits many closed-loop chains of qubit devices. Each one of the 20 qubit devices is indexed with a number from 0 to 19. In one example, the 20 qubit devices are embodied in 20 transmon devices.

FIG.6Billustrates a non-limiting example of a closed-loop chain650that is present in the layout600shown inFIG.6A. The closed-loop chain650includes four ancilla qubit devices (e.g., ancilla qubits), split into two branches that can be used as repetition branches: A first repetition branch including a1and a2, and a second repetition branch including b1and b2. Each one of the branches is coupled at one end with a root qubit and is further coupled with a flag qubit at the other end. A replica of the closed-loop chain650also is present in the layout600inFIG.6A. Both closed-loop chains of qubit devices can be utilized in two-qubit quantum computations. One example of the closed-loop chain650includes qubit devices11and16as the first repetition branch; qubit devices18and13as the second repetition branch; qubit device17as the flag qubit; and qubit device12as the root qubit. In that case, the replica includes qubit devices1and6as the first repetition branch; qubit devices8and3as the second repetition branch; qubit device2as the flag qubit; and qubit device7as the root qubit. The foregoing numbers denoting qubit devices correspond to respective indices shown inFIG.6A.

Simply as another illustration,FIG.7Apresents a non-limiting example of a layout700of the qubit devices140. In the layout700, 65 qubit devices are arranged in a geometry that exhibits many closed-loop chains of qubit devices. Each one of the 65 qubit devices is indexed with a number from 0 to 64. In one example, the 65 qubit devices are embodied in 65 transmon devices.

FIG.7Billustrates a non-limiting example of a closed-loop chain750that is present in the layout700shown inFIG.7A. The closed-loop chain750includes 10 ancilla qubit devices, split into two branches that can be used as repetition branches: A first repetition branch including a1, a2, a3, a4, and a5, and a second repetition branch including b1, b2, b3, b4, and b5, Each one of the branches is coupled at one end with a root qubit and is further coupled with a flag qubit at the other end. One example of the closed-loop chain750includes qubit devices32,31,39,45,46as the first repetition branch; qubit devices48,49,40,35, and34as the second repetition branch; qubit device33as the root qubit; and qubit device47as the flag qubit. The foregoing numbers denoting qubit devices correspond to respective indices shown inFIG.7A.

A replica of the layout750can be utilized for circular repetition encoding of two qubits. To that end, as an example,FIG.7Cillustrates two closed-loop chains that can be utilized for such an encoding: a first closed-loop chain including qubit devices33,32,31,39,45,46,47,48,49,40,35, and34, and a second closed-loop chain including qubit devices19,20,21,12,8,7,6,5,4,11,17, and18. The second closed-loop chain is coupled to the first closed-loop chain by qubit device25. In that arrangement, the root qubits being encoded are qubit device19and qubit device33, and the flag qubits are qubit device47and qubit device6. Ancilla qubits are represented by white circles. The foregoing numbers denoting qubit devices correspond to respective indices shown inFIG.7A.

FIG.8is a block diagram of a non-limiting example of the compiler system120for readout error mitigation in a quantum program/computation, in accordance with one or more embodiments described herein. As is illustrated inFIG.8, the compiler system120can include one or several processors810and one or several memory devices830(referred to as memory830). In some embodiments, the processor(s)810can be arranged in a single computing apparatus (a blade server device or another type of server device, for example). In other embodiments, the processor(s)810can be distributed across two or more computing apparatuses (e.g., multiple blade server devices or other types of server devices).

The processor(s)810can be operatively coupled to the memory830via one or several communication interfaces820, for example. The communication interface(s)820can be suitable for the particular arrangement (localized or distributed) of the processor(s)810. In some embodiments, the communication interface(s)820can include one or many bus architectures, such an Ethernet-based industrial bus, a controller area network (CAN) bus, a Modbus, other types of fieldbus architectures, or the like. In addition, or in other embodiments, the communication interface(s) can include a wireless network and/or a wireline network having respective footprints.

The memory830can retain or otherwise store therein machine-accessible components (e.g., computer-readable and/or computer-executable components) and data in accordance with this disclosure. As such, in some embodiments, machine-accessible instructions (e.g., computer-readable and/or computer-executable instructions) embody or otherwise constitute each one of the machine-accessible components within the memory830. The machine-accessible instructions can be encoded in the memory830and can be arranged to form each one of the machine-accessible components. The machine-accessible instructions can be built (e.g., linked and compiled) and retained in computer-executable form within the memory830or in one or several other machine-accessible non-transitory storage media. Specifically, as is shown inFIG.8, in some embodiments, the machine-accessible components include the ingestion component210, the branch identification component220, the compilation component230, the monitoring component240, and the evaluation component250. The memory830also can include data (not depicted inFIG.8) that permits various of the functionalities described herein. In some embodiments, the compilation component230can include one or a combination of the branch identification component220, the monitoring component240, and the evaluation component250. As is illustrated inFIG.9, the memory930can retain the layouts(s)272and the readout data276.

The machine-accessible components, individually or in a particular combination, can be accessed and executed by at least one of the processor(s)810. In response to execution, each one of the machine-accessible components can provide the functionality described herein in connection with readout error mitigation in a quantum computation. Accordingly, execution of the computer-accessible components retained in the memory830can cause the compiler system120to operate in accordance with aspects described herein. More concretely, at least one of the processor(s)810can execute the machine-accessible components to cause the compiler system120to encode one or more qubit devices (e.g., qubit device(s) or qudit device(s)) using a circular repetition code, adding an encoding unitary Uencoding to the a sequence of quantum gates corresponding to each one of the qubit device(s) during compilation of a quantum program to be executed in quantum hardware including the qubit device(s), in accordance with aspects of this disclosure.

Although not illustrated inFIG.8, the compiler system120also can include other types of computing resources that can permit or otherwise facilitate the execution of the machine-accessible components retained in the memory830. Those computing resources can include, for example, central processing units (CPUs), graphics processing units (GPUs), tensor processing units (TPUs), memory, disk space, incoming bandwidth, and/or outgoing bandwidth, interface(s) (such as I/O interfaces); controller devices(s); power supplies; and the like. For instance, the memory830also can include programming interface(s) (such as APIs); an operating system; software for configuration and or control of a virtualized environment; firmware; and similar.

The circular repetition encoding of this disclosure can be applied in quantum computations using quantum hardware130(FIG.1) having circular connectivity. Those quantum computations can include electronic structure calculations and simulations of time propagation of model Hamiltonians, for example. Other types of quantum computations in chemistry and physics also can be implemented. It is also noted that this disclosure is not limited to those types of quantum computations. Indeed, the circular repetition encoding of this disclosure can be generally applied to any quantum computation.

Noisy quantum computers can permit, for example, implementing efficient quantum computations of electronic structure properties of chemical compounds. In some cases, such computations can rely on adaptive quantum circuits. For instance, a variational quantum eigensolver (VQE) algorithm relies on quantum resources to approximate electronic eigenstates and their corresponding energy expectation valuesΨ|H|Ψ. Here, H is the electronic molecular Hamiltonian describing the chemical compound and |Ψis a parameterized wavefunction ansatz encoded on a qubit register.

As mentioned, the circular repetition encoding of this disclosure can mitigate readout errors. Accordingly, by implementing the VQE algorithm using the quantum hardware130, the effect of such an encoding on the readout of energy expectation values can be analyzed. As an illustration, the VQE algorithm is implemented for the model systems HeH+and H2. To that end, for HeH+, perturbations to the Hartree-Fock (HF) ground state determinant are prepared for with a 2-qubit quantum circuit900shown inFIG.9. Here, a, b, and c are variational parameters and

The quantum circuit900essentially corresponds to a Unitary Coupled-Cluster Single and Double (UCCSD) ansatz, and is used as an approximation to the reference HF dissociation curve for different interatomic distances.

The quantum circuit900was executed on the qubit devices140, in an embodiment in which the qubit devices140include the qubit layout700(FIG.7A). The quantum circuit900was executed both with circular repetition encoding and without circular repetition encoding. Results of quantum computations at respective interatomic distances are shown in diagram1010. Same two qubit devices (labeled as qJand qKinFIG.9, simply for the sake of nomenclature) are used for computations without circular repetition encoding (labeled “Uncoded” inFIG.10andFIG.11) and as root qubits for computations with (4+1+1)-qubit circular repetition encoding. Hence, gate errors during the state preparation stage can be consistent, and the results can only differ in the quality of the readout measurements, thus emphasizing the effect of the circular repetition encoding for readout error mitigation. As is shown inFIG.10, including circular repetition encoding in the quantum computations leads to an average decrease of the total error—defined as the difference from the reference energy values—by approximately 43% with respect to the unencoded quantum computations in this example. Reference energy values are shown as a solid trace1015(labeled “Exact”) and are obtained using an unrestricted Hartree-Fock (UHF) classical calculation.

In connection with electronic structure of H2, an (10+1+1)-qubit quantum chemistry experiment was performed on the quantum layout700(FIG.7A), implementing a single-qubit VQE computation. Such a computation utilizes a 2-qubit reduction to the qubit-Hamiltonian obtained by parity-mapping results in a 2-qubit Hamiltonian HH2(1q)=h0II+h1IZ+h2ZI+h3ZZ+h4XX, with |01and |10as ground state and excited state, respectively. Here, the coefficients h0, h1, and h2are defined by respective one-body integrals, and coefficient h3and h4are defined by respective two-body integrals. The equivalent 1-qubit Hamiltonian used in this disclosure has the following form:
HH2(1q)=(h0−h3)I+(h2−h1)Z+h4X.(3)

In these computations, numerically optimized ansatz parameters of no-noise simulations are used to sample energy estimates beyond the reference HF results. Results of the computations are shown in diagram1110inFIG.11. As illustrated inFIG.11, the improved effect of circular repetition encoding is clearly visible in diagrams1110and1120in this additional example. Reference energy values are shown as a solid trace1115(labeled “Exact”) and are obtained using a UHF classical calculation.

In order to illustrate the performance of circular repetition encoding described herein on deeper circuits, a digital quantum simulation of a 2-spin transverse field Ising model can be implemented. Such an Ising model is represented by the following Hamiltonian:
H=αZ1Z2+β(X1+X2)  (4)
The dynamical evolution of the system can be provided by the real time propagator(t)=e−iHt, which operator can be approximated by the Suzuki-Trotter product formula:

(t)≈(e-itn⁢α⁢Z1⁢Z2⁢e-itn⁢β⁡(X1+X2))n=[n(t)]n.(5)
Each Trotter stepn(t) can be implement using the combination of single-qubit rotations and CNOT gates shown in the quantum circuit1200inFIG.12. Concatenation of n such quantum circuits can provide a digital simulation of the time dynamics of the transverse field Ising model (Eq. (4)].

FIG.13illustrates the results from the implementation of the n=5 case on a quantum processor having the qubit layout600illustrated inFIG.6A. The results depict the time evolution of the total spin component along adirection—σz(1)+σz(2). Similar to electronic structure computations described above, the same pair of qubit devices (indices 7 and 12 on the qubit layout600) has been used both for the unencoded computation and as root qubits in the 4+1+1-circular repetition encoding. Results from such an uncoded computation are labeled as “Unencoded” inFIG.13. Another pair of qubit devices (indices 15 and 16 on the qubit layout600) also has been used in an uncoded computation as a reference computation because that pair of qubit devices exhibits the lowest readout error calibration data. Such reference results are labeled “Unencoded (A)” inFIG.13. The results of the quantum computation using circular repetition encoding outperforms both unencoded quantum computations as shown in this additional example.

FIG.14is a flowchart of a non-limiting example of a computer-implemented method1400for mitigating readout error in quantum programs/computations, in accordance with one or more embodiments of this disclosure. As mentioned, readout error mitigation can be accomplished using circular repetition encoding. While described with reference to qubit devices, the example method1400also can be implemented for other types of quantum devices, such as qudit devices. A computing system can implement, at least partially, the computer-implemented method1400. Implementing the computer-implemented method1400can include compiling or executing, or both, one or several of the blocks included in the computer-implemented method1400, for example. The computing system can include and/or can be operatively coupled to one or several processors, one or several memory devices, other types of computing resources (such as communication interface(s), bus architectures, etc.), a combination thereof, or other similar resources. In some embodiments, the computing system can be embodied in, or can constitute, the compiler system120in accordance with the various embodiments described herein.

At block1410, the computing system can configure a quantum computation to be executed in a quantum processor. To the end, the computing system can receive, via the ingestion component210, for example, data defining a quantum program including one or several quantum circuits. The quantum program defining the quantum computation.

At block1420, the computing system can configure one or more encoding unitaries using respective closed-loop chains of qubit devices (e.g., qubit devices140(FIG.1)) in the quantum processor. The one or more unitaries can be configured by the compilation component230, for example. Each encoding unitary (Uencoding) of the one or more encoding unitaries defines a circular repetition encoding of a qubit device involved in the quantum computation. As mentioned, the encoded qubit device is referred to as a root qubit. For example, in a two-qubit computation, the one or more unitaries being configured can be U(0)encodingand U(1)encodingshown inFIG.5B.

At block1430, the computing system can cause execution of the quantum computation in the quantum processor. The compilation component230(FIG.2) can cause the execution of the quantum computation.

At block1440, the computing system can cause circular repetition encoding of one or more qubit devices (root qubit(s)) in the quantum processor using the one or more encoding unitaries. The compilation component230(FIG.2) can cause the execution of the quantum computation. Causing the circular repetition encoding can include, for example, causing a translation of the operations defined in the one or more unitaries to pulse schedules, and further causing one or several components of the quantum hardware130to apply those scheduled to perform the circular repetition encoding. In some case, such a translation can be performed by the computing system, via the compilation component230, for example. In other cases, the translation can be performed by quantum hardware130.

At block1450, the computing system can cause measurement of qubit devices involved in the quantum computation and other qubit devices in closed-loop chains. Those other qubit devices includes ancilla qubits and flag qubits. The monitoring component240can cause such measurements, for example.

At block1460, the computing system can determine that a flag bit corresponding to the circular repetition encoding for a particular qubit device (e.g., particular root qubit) is in a state indicative of non-faulty encoding. The monitoring component240can cause such measurements, for example.

At block1470, the computing system can perform a majority vote evaluation using data from the measurements. Such an evaluation can provide a readout-error-mitigated single-qubit state for the particular qubit. The evaluation component250can implement the majority vote evaluation, for example.

In order to provide a context for the various aspects of the disclosed subject matter,FIG.15as well as the following discussion are intended to provide a general description of a suitable environment in which the various aspects of the disclosed subject matter can be implemented.FIG.15illustrates a block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity. A suitable operating environment1500for implementing various aspects of this disclosure can include a computer1512. The computer1512can also include a processing unit1514, a system memory1516, and a system bus1518. The system bus1518can operably couple system components including, but not limited to, the system memory1516to the processing unit1514. The processing unit1514can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit1514. The system bus1518can be any of several types of bus structures including the memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire, and Small Computer Systems Interface (SCSI). The system memory1516can also include volatile memory1520and nonvolatile memory1522. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer1512, such as during start-up, can be stored in nonvolatile memory1522. By way of illustration, and not limitation, nonvolatile memory1522can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM). Volatile memory1520can also include random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM.

Computer1512can also include removable/non-removable, volatile/non-volatile computer storage media.FIG.15illustrates, for example, a disk storage1524. Disk storage1524can also include, but is not limited to, devices like a magnetic disk drive, floppy disk drive, tape drive, Jaz drive, Zip drive, LS-100 drive, flash memory card, or memory stick. The disk storage1524also can include storage media separately or in combination with other storage media including, but not limited to, an optical disk drive such as a compact disk ROM device (CD-ROM), CD recordable drive (CD-R Drive), CD rewritable drive (CD-RW Drive) or a digital versatile disk ROM drive (DVD-ROM). To facilitate connection of the disk storage1524to the system bus1518, a removable or non-removable interface can be used, such as interface1526.FIG.15also depicts software that can act as an intermediary between users and the basic computer resources described in the suitable operating environment1500. Such software can also include, for example, an operating system1528. Operating system1528, which can be stored on disk storage1524, acts to control and allocate resources of the computer1512. System applications1530can take advantage of the management of resources by operating system1528through program modules1532and program data1534, e.g., stored either in system memory1516or on disk storage1524. It is to be appreciated that this disclosure can be implemented with various operating systems or combinations of operating systems. A user enters commands or information into the computer1512through one or more input devices1536. Input devices1536can include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices can connect to the processing unit1514through the system bus1518via one or more interface ports1538. The one or more Interface ports1538can include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). One or more output devices1540can use some of the same type of ports as input device1536. Thus, for example, a USB port can be used to provide input to computer1512, and to output information from computer1512to an output device1540. Output adapter1542can be provided to illustrate that there are some output devices1540like monitors, speakers, and printers, among other output devices1540, which require special adapters. The output adapters1542can include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device1540and the system bus1518. It should be noted that other devices and/or systems of devices provide both input and output capabilities such as one or more remote computers1544.

Computer1512can operate in a networked environment using logical connections to one or more remote computers, such as remote computer1544. The remote computer1544can be a computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device or other common network node and the like, and typically can also include many or all of the elements described relative to computer1512. For purposes of brevity, only a memory storage device1546is illustrated with remote computer1544. Remote computer1544can be logically connected to computer1512through a network interface1548and then physically connected via communication connection1550. Further, operation can be distributed across multiple (local and remote) systems. Network interface1548can encompass wire and/or wireless communication networks such as local-area networks (LAN), wide-area networks (WAN), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL). One or more communication connections1550refers to the hardware/software employed to connect the network interface1548to the system bus1518. While communication connection1550is shown for illustrative clarity inside computer1512, it can also be external to computer1512. The hardware/software for connection to the network interface1548can also include, for exemplary purposes only, internal and external technologies such as, modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

In some embodiments, the compiler system120described herein can be associated with a cloud computing environment. For example, the compiler system120can be associated with a cloud computing environment1650included in the operational environment1600illustrated inFIG.16, and/or with one or more functional abstraction layers described herein with reference toFIG.17(e.g., hardware and software layer1760, virtualization layer1770, management layer1780, and/or workloads layer1790).

Characteristics are as follows:

Service Models are as follows:

Deployment Models are as follows:

Referring now toFIG.16an illustrative cloud computing environment1650is depicted. As shown, cloud computing environment1650includes one or more cloud computing nodes1610with which local computing devices used by cloud consumers, such as, for example, personal digital assistant (PDA) or cellular telephone1654A, desktop computer1654B, laptop computer1654C, and/or automobile computer system1654N may communicate. Although not illustrated inFIG.16, cloud computing nodes1610can further comprise a quantum platform (e.g., quantum computer, quantum hardware, quantum software, and/or another quantum platform) with which local computing devices used by cloud consumers can communicate. Nodes1610may communicate with one another. They may be grouped (not shown) physically or virtually, in one or more networks, such as Private, Community, Public, or Hybrid clouds as described hereinabove, or a combination thereof. This allows cloud computing environment1650to offer infrastructure, platforms and/or software as services for which a cloud consumer does not need to maintain resources on a local computing device. It is understood that the types of computing devices1654A-N shown inFIG.16are intended to be illustrative only and that computing nodes1610and cloud computing environment1650can communicate with any type of computerized device over any type of network and/or network addressable connection (e.g., using a web browser).

Referring now toFIG.17, a set of functional abstraction layers provided by cloud computing environment1650(FIG.16) is shown. It should be understood in advance that the components, layers, and functions shown inFIG.17are intended to be illustrative only and embodiments of the invention are not limited thereto. As depicted, the following layers and corresponding functions are provided:

Hardware and software layer1760include hardware and software components. Examples of hardware components include: mainframes1761; RISC (Reduced Instruction Set Computer) architecture based servers1762; servers1763; blade servers1764; storage devices1765; and networks and networking components1766. In some embodiments, software components include network application server software1767, database software1768, quantum platform routing software (not illustrated inFIG.17), and/or quantum software (not illustrated inFIG.17).

Virtualization layer1770provides an abstraction layer from which the following examples of virtual entities may be provided: virtual servers1771; virtual storage1772; virtual networks1773, including virtual private networks; virtual applications and operating systems1774; and virtual clients1775.

Workloads layer1790provides examples of functionality for which the cloud computing environment may be utilized. Non-limiting examples of workloads and functions which may be provided from this layer include: mapping and navigation1791; software development and lifecycle management1792; virtual classroom education delivery1793; data analytics processing1794; transaction processing1795; and vulnerability risk assessment software1796.