A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.

BACKGROUND

The present invention relates to transistors, and more specifically, to implantation formed metal-insulator-semiconductor (MIS) contacts in transistors.

A field effect transistor (FET) generally includes three terminals: a source, a drain, and a gate. A critical factor in the performance of a FET is the external source-drain resistance (Rext) or the resistance at the source and drain contacts. Silicide (silicon bonded to metal) has been used for the source and drain contacts, but silicide contact resistance is a significant contributor to Rext. Metal-insulator-semiconductor (MIS) contacts have been considered as an alternative to silicide. MIS contacts are formed by depositing an insulating layer between the source and drain contacts and the respective source and drain regions. In theory, MIS contacts provide lower resistance based on a thin enough insulating layer.

SUMMARY

According to one embodiment of the present invention, a method of forming a metal-insulator-semiconductor (MIS) contact includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region; implanting metal ions at a selected depth within the upper surface of the semiconductor region; converting the upper surface of the semiconductor region to a metal oxide insulating layer; and forming a metal layer on the insulating layer.

According to another embodiment, a transistor includes a source terminal; a source contact formed on the source terminal; a drain terminal separated from the source terminal by a gate terminal; and a drain contact formed on the drain terminal, wherein the source contact and the drain contact are metal-insulator-semiconductor (MIS) contacts, and the insulator of the MIS contacts is formed via oxidation of an upper surface of the source terminal and the drain terminal, respectively, following implantation of metal ions into the upper surface.

According to yet another embodiment, a metal-insulator-silicon (MIS) contact for a terminal of a transistor includes the terminal formed from a semiconductor material; an insulating layer formed through oxidation of a surface portion of the terminal following implantation of metal ions; and a metal layer.

DETAILED DESCRIPTION

As noted above, Rext is a critical factor in transistor performance. On the one hand, silicide contact resistance reduction has proven challenging, in that traditional silicides such as nickel silicide (NiSi) and titanium silicide (TiSi) may not be able to provide the desired contact resistance. On the other hand, the lower resistance for MIS contacts that is predicted in theory has been difficult to achieve in practice. The higher resistance seen from MIS contact formation is thought to be related to conventional deposition techniques with respect to the insulating layer, suggesting that the resulting thickness of the insulating layer is too great to achieve the desired results. Accordingly, disclosed herein are embodiments of methods and corresponding structures for lowering Rext by forming MIS contacts based on implantation of metal in a thin insulating layer rather than deposition of metal over a thicker insulating layer.

Referring generally now to the figures,FIG. 1is a cross-sectional view of an FET100with a source contact110, drain contact120, and gate contact130according to embodiments of the invention. The contacts110,120,130are not detailed inFIG. 1. Instead, an overall arrangement of the transistor100structure is provided, noting that the processes detailed below are not limited to any particular type of transistor. In addition, while epitaxially grown source115and drain125are used in the exemplary figures, the processes discussed herein apply, as well, to implanted source and drain regions. The three FET terminals shown for the exemplary transistor100, i.e., the source115, the drain125, and the gate135have the source contact110, the drain contact125, and the gate contact135associated with them, respectively. The source and drain terminals115,125may be formed over a semiconductor substrate140. The formation of the source contact110and drain contact120as implantation-formed MIS contacts is detailed below.

FIGS. 2-6are cross-sectional views illustrating process steps involved in fabricating the source contact110and drain contact120according to an embodiment of the invention. It will be appreciated that the present embodiments apply to a planar FET structure or a three-dimensional FET structure (e.g., finFET). The intermediate structure200shown inFIG. 2includes a source115and a drain125formed on the substrate140. In the illustrated embodiment, the source115and drain125may be elevated (i.e., raised) by growing a selective epitaxial silicon on the substrate140. It will also be appreciated that the source115and drain120may be formed by other processes, such as implanting dopant atoms into a semiconductor substrate, for example. An oxide layer210(e.g., silicon dioxide (SiO2)) is formed over the source115and drain125, as well as over a gate stack220. A silicon nitride (SiN) layer230is formed over the oxide layer210as an etch and ion implantation mask.

FIG. 3illustrates a cross-sectional view of an intermediate structure300resulting from etching a source contact opening310and a drain contact opening320in the structure200shown inFIG. 2. The two contact openings310,320are etched through a dry etching process such as a reactive ion etch (RIE) process to expose a top surface of the source115and drain125. The etch may extend partially into the semiconductor material of the source115and drain125as well. The contact openings310,320may be etched simultaneously. Alternately, based on alignment issues arising from formation of multiple devices, for example, the RIE process may be performed separately to obtain each contact opening310,320.FIG. 4illustrates the intermediate structure400and shows a key process in the formation of the source contact110and drain contact120according to the embodiment detailed herein. Metal ions410are implanted into an upper region of the source115and drain125. The metal ions410may be aluminum (Al), lanthanum (La), zinc (Zn), or titanium (Ti), for example. The metal ion410implantation depth may be tuned. The result of the tuning is a very thin insulating layer510(FIG. 5) that results in low Rext. The metal ion410implantation may be performed in a vacuum.

FIG. 5shows the intermediate structure500resulting from the metal ion410implantation shown inFIG. 4, followed by oxidation to convert the implanted upper region of the source115and drain125to a thin metal oxide insulating layer510. The oxidation, according to one embodiment, is achieved from exposure to air and may be aided, optionally, by implantation of oxygen or deposition of oxygen plasma, for example. Thermal treatment (thermal anneal) may be used after the metal ion410implantation to aid in the formation of the oxide as well. Depending on the metal ion410that was implanted, aluminum oxide (Al2O3), lanthanum oxide (LaOx), zinc oxide (ZnO2), or titanium dioxide (TiO2) may be formed. The result of the oxidation is a metal oxide insulating layer510and an intermixing layer520below it. When the metal ions410are first implanted, they exist interstitially at the top surface of the source115and drain125. Through the oxidation process, the insulating layer510is formed. As a result of diffusion, the intermixing layer520, between the oxide and semiconductor (source115or drain125), may also result. As a result of the metal ion410implantation, the resulting insulating layer510is thinner than the thickness (˜2 nanometers (nm)) of a typical insulating layer of an MIS contact. The insulating layer510according to the embodiment discussed herein may be less than 1 nm thick.

FIG. 6shows the MIS contacts110,120formed following the metal ion410implantation and conversion of the ions to the metal oxide insulating layer510. In addition to the insulating layer510, the structure600shown inFIG. 6also includes a metal liner610and a metal fill620, formed by metal fill process as known in the art. AsFIG. 6shows, the metal liner610is conformally deposited on the surfaces of the openings310,320and on the insulating layer510. The metal liner610may be Ti and titanium nitride (TiN), for example. A metal fill620(e.g., tungsten (W)) is then deposited in the openings310,320over the metal liner610. A chemical-mechanical polishing (CMP) process is also performed to the structure600shown inFIG. 6following deposition of the metal fill620. This completes formation of the source contact110and drain contact120. As noted above, Rext is reduced in the source contact110and drain contact120, which are MIS contacts formed by implantation of metal ions420in the insulating layer410rather than deposition of a metal layer over an insulating layer. The resulting MIS contact110,120is comprised of the metal fill620(metal), insulating layer510(insulator), and source115or drain125semiconductor surfaces (semiconductor).

FIG. 7is a cross-sectional view illustrating a process step involved in fabricating the source contact110and drain contact125according to another embodiment of the invention.FIG. 7illustrates an intermediate structure700that shows an alternate embodiment of the process shown inFIG. 4. Specifically, the metal liner610is conformally deposited in the source contact opening310and in the drain contact opening320prior to implantation of the metal ions410and conversion to a metal oxide insulating layer510. Following the metal fill620and CMP process, the structure600that includes the source contact110and drain contact120, as shown inFIG. 6, is obtained from the structure700ofFIG. 7. Again, the metal ion410implantation depth is selected to create a thin insulating layer510. Also, thermal treatment may be applied to help the formation of an oxide (e.g., Al2O3, LaOx, ZnO2, TiO2).