Semiconductor structure and method for manufacturing semiconductor structure

A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a semiconductor base, a bit line and a word line. The semiconductor base includes a substrate and an isolation structure. The isolation structure is arranged above the substrate and configured to isolate a plurality of active regions from each other. The bit line is arranged in the substrate and connected to the plurality of active regions. The word line is arranged in the isolation structure, intersects with the plurality of active regions and surrounds the plurality of active regions. The substrate is a Silicon-On-Insulator (SOI) substrate.

TECHNICAL FIELD

The disclosure relates to the technical field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure.

BACKGROUND

With the increase of the integration in a semiconductor manufacturing process, it is a tendency to improve the integration density of a memory.

A dynamic random access memory (DRAM) is a semiconductor memory, which includes an array region consisting of a plurality of memory cells and a peripheral region constituted by a control circuit. Each memory cell includes a transistor electrically connected to a capacitor, and the transistor controls storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuit may be located to each memory cell to control the access of the data thereof through a word line (WL) and a bit line (BL) which span across the array region and are electrically connected to each memory cell.

In an existing DRAM art, an embedded type WL structure is mainly adopted, which is greater in unit configuration size and limited in control ability.

SUMMARY

The disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure.

According to a first aspect of the disclosure, a semiconductor structure is provided, including a semiconductor base, a bit line and a word line.

The semiconductor base includes a substrate and an isolation structure. The isolation structure is arranged above the substrate and configured to isolate a plurality of active regions from each other.

The bit line is arranged in the substrate and connected to the plurality of active regions.

The word line is arranged in the isolation structure, intersects with the plurality of active regions and surrounds the plurality of active regions.

The substrate is a Silicon-On-Insulator (SOI) substrate.

According to a second aspect of the disclosure, a method for manufacturing a semiconductor structure is provided, including the following operations.

A substrate is formed. The substrate is a Silicon-On-Insulator (SOI) substrate.

A bit line is formed in the substrate.

An isolation structure is formed on the substrate.

A word line and a plurality of active regions are formed in the isolation structure. The word line intersects with the plurality of active regions and surrounds the plurality of active regions.

Reference numerals are illustrated as follows.

DETAILED DESCRIPTION

Typical embodiments that embody the features and advantages of the disclosure will be described in detail in the following description. It is to be understood that the disclosure can be changed in different embodiments without departing from the scope of the disclosure, and that the description and drawings are illustrative in nature and are not intended to limit the disclosure.

In the following description of different exemplary embodiments of the disclosure, reference is made to the accompanying drawings, which form a part of the disclosure, and in which different exemplary structures, systems, and operations for implementing various aspects of the disclosure are shown by way of an example. It is to be understood that other specific solutions of a part, a structure, an exemplary device, a system, and an operation may be utilized, and a structural and functional modification may be made without departing from the scope of the disclosure. Moreover, although terms “above”, “between”, “within”, and the like may be used in the specification to describe different exemplary features and elements of the disclosure, these terms are used herein for convenience only, for example, according to a direction of the example in the drawings. Any content in the specification should not be construed as requiring a specific three-dimensional direction of the structure to fall within the scope of the disclosure.

An embodiment of the disclosure provides a method for manufacturing a semiconductor structure. Referring toFIG.1, the method for manufacturing the semiconductor structure includes the following operations.

S103, a bit line20is formed in the substrate12.

S105, an isolation structure13is formed in the substrate12.

S107, a word line30and a plurality of active regions11are formed in the isolation structure13. The bit line20is connected to the plurality of active regions11. The word line30intersects with the plurality of active regions11and surrounds the plurality of active regions11.

According to the method for manufacturing the semiconductor structure in an embodiment of the disclosure, the embedded type bit line20is formed in the substrate12, and the active regions11and the word line30are formed in the isolation structure13. The word line30is connected to the active regions11and the word line30intersects with the active regions11, so that bit line contact holes for connecting the bit line20to the active regions11are omitted. The unit configuration size on the substrate12is small, i.e., the size of the semiconductor structure may be further reduced, and the control ability of the embedded type bit line20is stronger, so that the performance of the semiconductor structure is improved.

It should be noted that, a vertical type memory transistor is formed on an overlapped area in which the bit line20spatially intersects with the word line30, and the vertical type memory transistor is arranged on the bit line20and connected to the bit line20. One overlapped area corresponds to one vertical type memory transistor. The vertical type memory transistor includes active regions11.

In a related art, the width size of one memory transistor in a direction perpendicular to the word line is 3F, and the width size of one memory transistor in a direction perpendicular to the bit line is 2F. The area of one memory transistor that needs to be configured on the substrate is 6F2 (3F*2F, namely a 3×2 embedded type word line structure), in which F is the minimum feature size. That is, the minimum line width size and the minimum line spacing size may be obtained based on the resolution of a current lithography apparatus. The minimum linear width size and the minimum linear spacing size are equal. Based on the resolution of the current lithography apparatus, the unit size of the manufactured memory transistor may only be 6F2, which may not be further reduced.

The unit configuration size refers to the unit configuration size, which needs to be configured on a substrate, for a memory cell. The unit configuration size includes a size actually occupied by one memory cell on the substrate, and a spacing size needing to be reserved between the memory cell and an adjacent memory cell. For example, if the size occupied by N memory transistors on the substrate is M, the unit configuration size of one memory transistor on the substrate is N/M. For the vertical type memory transistor based on a vertical structure, the word line and the bit line spatially intersect with each other and have an overlapped area, and one overlapped area corresponds to one vertical type memory transistor.

According to the semiconductor structure manufactured in the embodiment, the bit line20with the minimum feature size F and the word line30with the minimum feature size F may be formed according to related preparation processes, and both the line spacing between the formed adjacent bit lines20and the line spacing between the formed adjacent word lines30is greater than or equal to the minimum feature size F, so that the width size of one vertical type memory transistor in the direction perpendicular to the bit lines is 2F and the width size of one vertical type memory transistor in a direction perpendicular to the word lines is also 2E As a result, the unit configuration size of the vertical type memory transistor may be 4F2 accordingly (2F*2F, namely a 2×2 embedded type bit line structure). That is, the unit configuration size of the vertical type memory transistor is greater than or equal to 4 times the square of the minimum feature size. Compared with 3×2 embedded type word line structure, the unit configuration size is smaller, namely stacking density is higher.

In an embodiment, the operation that the substrate12is formed includes the following operations. A first semiconductor layer121is provided, an oxide insulation layer122is formed on the first semiconductor layer121, and a second semiconductor layer123is formed on the oxide insulation layer122.

Specifically, the first semiconductor layer121may be made of a silicon-containing material. The first semiconductor layer121may be made of any suitable material, for example including at least one of silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polysilicon germanium and carbon doped silicon.

The oxide insulation layer122may include materials such as Silicon Dioxide (SiO2) and Silicon Oxycarbide (SiOC).

The second semiconductor layer123may be made of a silicon-containing material. The second semiconductor layer123may be made of any suitable material, for example including at least one of silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polysilicon germanium and carbon doped silicon.

It is to be noted that, the first semiconductor layer121, the oxide insulation layer122and the second semiconductor layer123form the Silicon-On-Insulator (SOI) in which the bit line20is arranged.

In an embodiment, the thickness of the oxide insulation layer122is greater than 100 nm, and the thickness of the second semiconductor layer123ranges from 18 nm to 22 nm.

In an embodiment, the operation that the bit line20is formed includes the following operations. An opening40is formed in the substrate12, in which a bottom surface of the opening40is arranged in the oxide insulation layer122. The bit line20is formed in the opening40. A top end of the bit line20is not higher than a lower surface of the second semiconductor layer123, namely the bit line20is embedded into the oxide insulation layer122.

In an embodiment, in combination withFIG.2, a mask layer is covered on the SOI formed through the first semiconductor layer121, the oxide insulation layer122and the second semiconductor layer123, and a mask pattern is formed on the mask layer. The mask pattern corresponds to an area where the bit line20is located (a three-dimensional type space, that is, upper and lower spaces are areas where the bit line20is located based on a plane where the bit line20is located). The opening40is formed by etching the area where the mask pattern is located, with reference toFIG.3andFIG.4. The bit line20is finally formed in the opening40, with reference toFIG.5andFIG.6.

In an embodiment, the mask layer includes an oxide layer45, a nitride layer46and photoresist47. In combination withFIG.2, the oxide layer45is formed on the second semiconductor layer123, the nitride layer46is formed on the oxide layer45, and the photoresist47is formed on the nitride layer46. The opening40is formed by photoetching. The opening40does not penetrate through the oxide insulation layer122, and the depth of the opening40in the oxide insulation layer122ranges from 40 nm to 70 nm and the width of the opening40in the oxide insulation layer122ranges from 30 nm to 70 nm.

It is to be noted that, the oxide insulation layer122, the oxide layer45, the nitride layer46and the photoresist47may be formed through a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process.

In an embodiment, the bit line20includes a bit line isolation layer21arranged in the oxide insulation layer122, a barrier layer22covering an inner surface of the bit line isolation layer21, and a conductive layer23arranged in the barrier layer22. The barrier layer22covers an upper surface of the conductive layer23, and the barrier layer22is connected to the active regions11.

In combination withFIG.5andFIG.6, the bit line isolation layer21covering the inner surface of the opening40is formed in the opening40. The barrier layer22covering the inner surface of the bit line isolation layer21is formed in the opening40. The conductive layer23is filled in the opening40. The barrier layer22covers the upper surface of the conductive layer23. The barrier layer22may only cover the upper surface of the conductive layer23, that is to say, the upper surface of the bit line isolation layer21is exposed. Certainly, the barrier layer22may completely cover the upper surface of the conductive layer23and the upper surface of the bit line isolation layer21.

Specifically, the bit line isolation layer21may include materials such as Silicon Nitride (SiN) and Nitrogen Silicon Carbide (SiCN). The barrier layer22may include at least one of Tungsten Silicide (WSi), Titanium Nitride (TIN) and Titanium (TI), and the conductive layer23may include Tungsten (W).

It is to be noted that, the bit line isolation layer21, the barrier layer22and the conductive layer23may be formed through a PVD process, a CVD process, an ALD process, a remote plasma nitridization (RPN) process, a thermal oxidization process, and the like, which may be not limited herein.

In an embodiment, the operation that the active regions11are formed includes the following operations. A drain region111is formed on the bit line20; a source channel112is formed on the drain region111; and a source region113is formed on the drain channel111. That is to say, the drain region111, the source channel112and the source region113are sequentially arranged in the vertical direction to form three-dimensional type active regions11.

In an embodiment, the operation that the active regions11are formed includes the following operations. A third semiconductor layer41covering an upper surface of the bit line20is formed on the second semiconductor layer123. A portion of the second semiconductor layer123and a portion of the third semiconductor layer41are etched, in which a remaining portion of the second semiconductor layer123and a remaining portion of the third semiconductor layer41form the drain region111.

Specifically, after the bit line20is formed, the mask layer covering the second semiconductor layer123is removed, and the third semiconductor layer41is formed on the second semiconductor layer123. As shown inFIG.7andFIG.8, the third semiconductor layer41covers the bit line20, and the second semiconductor layer123and the third semiconductor layer41may be made of the same material.

The third semiconductor layer41is covered with the mask layer, and a mask pattern is formed on the mask layer and corresponds to an area where the drain region111is located. The second semiconductor layer123and the third semiconductor layer41outside the mask pattern are etched, and a remaining portion of the second semiconductor layer123and a remaining portion of the third semiconductor layer41form a plurality of drain regions111which are spaced apart from each other as shown inFIG.9andFIG.10. In the embodiment, the width of the drain region111is greater than the width of the bit line20. Further, the width of the drain region111is greater than the width of the bit line20by 3 nm to 10 nm.

In an embodiment, the operation that the word line30is formed further includes the following operations. A first insulating dielectric layer131covering a side wall of the drain region111is formed on the oxide insulation layer122. A first oxide layer48is formed on the first insulating dielectric layer131and the drain region111. A conductive material layer44is formed on the first oxide layer48. A second oxide layer49is formed on the conductive material layer44. The second oxide layer49, the conductive material layer44and the first oxide layer48outside an area where the word line30is located are etched, to expose the first insulating dielectric layer131. A second insulating dielectric layer133is formed on the first insulating dielectric layer131to cover the first oxide layer48, the conductive material layer44and the second oxide layer49. The first insulating dielectric layer131and the second insulating dielectric layer133form the isolation structure13. A portion of the second insulating dielectric layer133, a portion of the second oxide layer49, a portion of the conductive material layer44and a portion of the first oxide layer48in an area where the drain region111is located are etched, to form a first opening50and expose the drain region111, in which a remaining portion of the conductive material layer44forms the word line30.

Specifically, on the basis ofFIG.9andFIG.10, after the drain region111is formed, the first insulating dielectric layer131covering the side wall of the drain region111is formed on the oxide insulation layer122as shown inFIG.11andFIG.12.

On the basis ofFIG.11andFIG.12, the first oxide layer48, the conductive material layer44and the second oxide layer49are sequentially formed on the first insulating dielectric layer131and the drain region111as shown inFIG.13andFIG.14. A mask layer is formed on the second oxide layer49, and a mask pattern which corresponds to an area where the word line30is located is formed on the mask layer. The area outside the mask pattern is etched to form a structure as shown inFIG.15andFIG.16.

On the basis ofFIG.15andFIG.16, the second insulating dielectric layer133is formed. The second insulating dielectric layer133fills a gap above the first insulating dielectric layer131and covers the second oxide layer49, as shown inFIG.17andFIG.18. A mask layer is formed on the second insulating dielectric layer133, and a mask pattern which corresponds to the area where the drain region111is located is formed on the mask layer. The first opening50as shown inFIG.19andFIG.20is formed by etching, that is, a plurality of word lines30spaced apart from each other are formed.

In an embodiment, the conductive material layer44may include Tungsten (W), and the first insulating dielectric layer131and the second insulating dielectric layer133may be made of an insulating material, for example, SiO2, SiOC, SiN, SiCN and the like, which may be not limited herein. It is to be noted that, the first insulating dielectric layer131, the first oxide layer48, the conductive material layer44, the second oxide layer49and the second insulating dielectric layer133may be formed through a PVD process, a CVD process, an ALD process, a RPN process, a thermal oxidization process, an In-Situ Steam Generation (ISSG) process, a spin on dielectric (SOD) process and the like, which may be not limited herein.

In an embodiment, the operation that the active regions11are formed further include the following operations. The second insulating dielectric layer133in an area where the drain region111is located is etched, to form a second opening51and expose the second oxide layer49. The third oxide layer52is formed on a wall of the first opening50, in which the first oxide layer48, the second oxide layer49and the third oxide layer52form a gate oxide layer132. A fourth semiconductor layer42is formed in the first opening50and the second opening51. The fourth semiconductor layer42forms the source channel112and the source region113, and the drain region111, the source channel112and the source region113form the active regions11.

On the basis ofFIG.19andFIG.20, a sacrificial layer53is formed in the first opening50as shown inFIG.21andFIG.22. A mask layer is formed above the second insulating dielectric layer133and the sacrificial layer53, and a mask pattern which corresponds to the area where the drain region111is located is formed on the mask layer. The second insulating dielectric layer133in the area where the mask pattern is located is etched and the sacrificial layer53is removed to form the structure as shown inFIG.23andFIG.24, namely a damascene structure. After the third oxide layer52is formed in the damascene structure, the fourth semiconductor layer42is formed. As shown inFIG.25andFIG.26, the top end of the second insulating dielectric layer133is provided with a hole for connecting the source region113to a memory element (for example a memory capacitor).

In an embodiment, the gate oxide layer132may be an insulating material, for example, SiO2, SiOC, SiN, SiCN and the like, which may be not limited herein. In the embodiment, the first oxide layer48, the second oxide layer49and the third oxide layer52which form the gate oxide layer132may be made of SiO2.

It is to be noted that, the third oxide layer52may be formed through a PVD process, a CVD process, an ALD process, a thermal oxidization process, an In-Situ Steam Generation (ISSG) process, and the like, which may be not limited herein.

In an embodiment, the second semiconductor layer123and the third semiconductor layer41may be made of monocrystalline silicon. The drain region111is formed by in-situ doping the monocrystalline silicon or implanting ions to the monocrystalline silicon after the third semiconductor layer41is formed on the second semiconductor layer123through an epitaxial growth (Epi) process, that is, after the second semiconductor layer123and the third semiconductor layer41form the monocrystalline silicon. The second semiconductor layer123may be formed through an Epi process.

In an embodiment, the fourth semiconductor layer42is made of monocrystalline silicon, and the source channel112and the source region113are formed by in-situ doping said monocrystalline silicon or implanting ions to said monocrystalline silicon after said monocrystalline silicon is formed based on the drain region111through an Epi process.

In the embodiment, the Epi process may be a selective Epi process.

It is to be noted that, the drain region111, the source channel112and the source region113respectively form a drain, a trench region and a source of a vertical type memory transistor. Each of the drain region111, the source channel112and the source region113includes first doping, second doping and third doping, the first doping and the third doping are first conductive type doping, and the second doping is second conductive type doping contrary to the first conductive type doping. The first conductive type doping may be P type and the second conductive type doping may be N type; or the first conductive type doping many be N type and the second conductive type doping may be P type. The source region113is configured to be connected to a memory element (for example, a memory capacitor).

It is to be noted that, a Chemical Mechanical Polishing (CMP) process is a general process which be matched with formation of a semiconductor structure. For example, the formed third semiconductor layer41may be ground and polished through the CMP process. Correspondingly, the first insulating dielectric layer131and the second insulating dielectric layer133also may be ground and polished through the CMP process, which may be not limited herein and may be selected according to the specific needs.

An embodiment of the disclosure further provides a semiconductor. Referring toFIG.25andFIG.26, the semiconductor structure includes a semiconductor base10, a bit line20and a word line30. The semiconductor base10includes a substrate12and an isolation structure13arranged above the substrate12. The isolation structure13is configured to isolate a plurality of active regions11from each other. The bit line20is arranged in the substrate12and connected to the plurality of active regions11. The word line30is arranged in the isolation structure13, intersects with the plurality of active regions11and surrounds the plurality of active regions11. The substrate12is a SOI substrate. The word line30surrounds the plurality of active regions11, and the substrate12is a SOI substrate.

According to the semiconductor structure in an embodiment of the disclosure, the bit line20is arranged in the SOI substrate, and connected to the plurality of active regions11. The word line30and the plurality of active regions11are arranged in the isolation structure13. The word line30intersects with the plurality of active regions11and surrounds the plurality of active regions11. In such a manner, the unit configuration size on the semiconductor base10is small, that is, the size of the semiconductor structure is further reduced, and the control ability of the embedded type bit line20is stronger, so that the performance of the semiconductor structure is improved.

In an embodiment, as shown inFIG.26, the bit line20includes a bit line isolation layer21arranged in the substrate12, a barrier layer22covering the inner surface of the bit line isolation layer21, and a conductive layer23arranged in the barrier layer22. The barrier layer22covers the upper surface of the conductive layer23, and the barrier layer22is connected to the active regions11.

In an embodiment, the semiconductor structure includes a plurality of bit lines20extending in a first preset direction and a plurality of word lines30extending in a second preset direction. The first preset direction is perpendicular to the second preset direction.

In an embodiment, a part of the active regions11are formed through the SOI substrate or none of the active regions11include the SOI substrate.

In an embodiment, the substrate12includes a first semiconductor layer121, an oxide insulation layer122arranged on the first semiconductor layer121, and a second semiconductor layer123arranged on the oxide insulation layer122. The bit line20is arranged in the oxide insulation layer122. The isolation structure13is arranged on the oxide insulation layer122and covers the second semiconductor layer123. The active regions11include the second semiconductor layer123.

It is to be noted that, the first semiconductor layer121, the oxide insulation layer122and the second semiconductor layer123form the SOI in which the bit line20is arranged. During the manufacture of the semiconductor structure, a portion of the second semiconductor layer123is removed, and the remaining portion of the second semiconductor layer123forms the active regions11.

In an embodiment, a bottom end of the bit line20is in contact with the oxide insulation layer122, that is, the bit line20is arranged in the oxide insulation layer122so as to guarantee reliable isolation of the bit line20.

In an embodiment, a top end of the bit line20is not higher than a lower surface of the second semiconductor layer123. That is, the top end of the bit line20may be flush with the upper surface of the oxide insulation layer122, or the top end of the bit line20may be arranged below the upper surface of the oxide insulation layer122.

In an embodiment, the thickness of the oxide insulation layer122in a first direction is greater than 100 nm, in which the first direction is perpendicular to the first semiconductor layer121.

In an embodiment, the thickness of the bit line20in the first direction ranges from 40 nm to 70 nm.

In an embodiment, the thickness of the bit line20in a second direction ranges from 30 nm to 70 nm, in which the first direction is perpendicular to the second direction.

It is to be noted that, the first direction may be understood as a vertical direction, and the second direction may be understood as a horizontal direction. Moreover, it may be further explained that the second direction is a horizontal direction parallel to the longitudinal section of the semiconductor structure in combination withFIG.26.

In an embodiment, as shown inFIG.26, each active region11includes: a drain region111connected to the bit line20, in which at least a portion of the drain region111is formed through an Epi process; a source channel112arranged above the drain region111; and a source region113arranged above the source channel112, in which a part of the drain region111is formed through the substrate12.

Specifically, the active region11includes the drain region111, the source channel112and the source region113. The drain region111, the source channel112and the source region113respectively form a drain, a trench region and a source of a vertical type memory transistor. The drain region111, the source channel112and the source region113are vertically arranged in a height direction, and the drain region111is arranged above the bit line20and connected to the bit line20. That is to say, a bit line contact hole for connecting the bit lines20with each other is omitted. The unit configuration size of the vertical type memory transistor on the substrate12is small (for example, the unit configuration size is 4F2), and therefore the size of a memory may be further reduced.

In an embodiment, the thickness of the drain region111in the second direction is greater than the thickness of the bit line20in the second direction. In the embodiment, the thickness of the drain region111in second first direction is greater than the thickness of the bit line20in the second direction by 3 nm to 10 nm.

In an embodiment, the thickness of the drain region111in the second direction is greater than the thickness of the source channel112in the second direction, the thickness of the source region113in the second direction is greater than the thickness of the source channel112in the second direction. The word line30intersects with the source channel112, that is, in terms of a spatial concept, the word line30is arranged between the drain region111and the source region113, and the thickness of the word line30in the second direction may not be increased in the presence of the source channel112.

It is to be noted that, each word line30intersects with the plurality of active regions11. Here, each word line30spatially intersects with the plurality of active regions11, that is, the word line30is not in contact with the plurality of active regions11.

In an embodiment, as shown inFIG.26, the semiconductor structure further includes a gate oxide layer132arranged on the drain region111and covering the top end of the drain region111, the side wall of the source channel112and the bottom end of the source region113. The gate oxide layer132is arranged between the word line30and the source channel112. The active regions11are isolated from the word line30through the gate oxide layer132. The gate oxide layer132which may be an oxide layer, that is, the gate oxide layer132forms an annular gate oxide layer for isolating the active regions11from the word line30.

In an embodiment, as shown inFIG.26, the isolation structure13includes: a first insulating dielectric layer131and a second insulating dielectric layer133. The first insulating dielectric layer131is arranged on the substrate12and covers the side wall of the drain region111. The second insulating dielectric layer133is arranged on the first insulating dielectric layer131. The source channel112, the source region113and the word line30are arranged in the second insulating dielectric layer133, and the second insulating dielectric layer133covers the side wall of the source region113. The drain region111is encased in the first insulating dielectric layer131, the active regions11are isolated from the word line30through the gate oxide layer132which may be an oxide layer. The second insulating dielectric layer133isolates the adjacent two word lines30from each other, that is, the word lines30and the active regions11are embedded into the isolation structure13.

Specifically, the gate oxide layer132is arranged between the source channel112and the word line30. The second insulating dielectric layer133is in direct contact with the first insulating dielectric layer131, and the second insulating dielectric layer133directly covers the side wall of the source region113to expose the top end of the source region113. The top end of the source region113is connected to a memory element (for example, a memory capacitor).

In an embodiment, a vertical type memory transistor is formed on an overlapped area in which the bit line20spatially intersects with the word line30, the vertical type memory transistor is arranged on the bit line20and connected to the bit line20, and one overlapped area corresponds to one vertical type memory transistor. The unit configuration size of the vertical type memory transistor on the semiconductor base10is greater than or equal to 4 times the square of the minimum feature size.

In an embodiment, a vertical type memory transistor is formed on an overlapped area in which the bit line20spatially intersects with the word line30, and the vertical type memory transistor is arranged on the bit line20and connected to the bit line20. The width size D1of one vertical type memory transistor in a direction perpendicular to the bit line20is twice the minimum feature size, and the width size D2of one vertical type memory transistor in a direction perpendicular to the word line30is twice the minimum feature size.

It is to be noted that, the formed bit line20and the word line30have the minimum feature size F, and line spacing between adjacent bit lines20and line spacing between adjacent word lines30are greater than or equal to the minimum feature size F. The width size of one vertical type memory transistor in the direction perpendicular to the bit line is 2F, and the width size of one vertical type memory transistor in the direction perpendicular to the word line is also 2F. Therefore, the unit configuration size of the vertical type memory transistor may be correspondingly 4F2 (2F*2F, namely a 2×2 embedded type bit line structure). That is, the unit configuration size of the vertical type memory transistor is greater than or equal to 4 times the square of the minimum feature size. Compared with a 3×2 embedded type word line structure, the unit configuration size is smaller, namely stacking density is higher.

In an embodiment, a semiconductor structure may be obtained through the method for manufacturing the semiconductor structure described above.

It is to be noted that, the material of each structure layer of the semiconductor structure may refer to a material as described in the method for manufacturing the semiconductor structure, which may be not described again herein.

Other embodiments of the disclosure will be apparent to those skilled in the art after consideration of the specification and practice of the disclosure disclosed here. The disclosure is intended to cover any variations, uses, or adaptations of the disclosure, and the variations, uses, or adaptations follow the general principles of the disclosure and include common general knowledge or conventional technical means in the art undisclosed by the disclosure. The specification and examples are considered as examples only, and a true scope and spirit of the disclosure are indicated by the foregoing claims.

It will be appreciated that the disclosure is not limited to the exact structure that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the disclosure is only limited by the appended claims.