Manufacturing method of a semiconductor memory device

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2019-0051780, filed on May 2, 2019, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device including a memory cell array and a peripheral circuit.

2. Related Art

A semiconductor memory device may include a memory cell array including a plurality of memory cells. A substrate including the memory cell array and a substrate including a peripheral circuit to operate the memory cell array may be separately processed, and then the memory cell array and the peripheral circuit may be coupled.

During the process of coupling the memory cell array and the peripheral circuit, a process failure may occur.

SUMMARY

According to an embodiment, a method of manufacturing a semiconductor memory device may include processing a first substrate and processing a second substrate. Processing of the first substrate may include disposing a peripheral circuit and a first conductive contact pattern coupled to the peripheral circuit over a first region of the first substrate, embedding a sacrificial material in a second region of the first substrate, and disposing a first align mark over the sacrificial material. Processing of the second substrate may include disposing a second align mark, a memory cell array, and a second conductive contact pattern coupled to the memory cell array over the second substrate. The method may also include orientating the first substrate and the second substrate such that the first conductive contact pattern and the second conductive contact pattern face each other, and coupling the first conductive contact pattern to the second conductive contact pattern by checking alignment of the first align mark with the second align mark.

According to an embodiment, a method of manufacturing a semiconductor memory device may include processing a first substrate. Processing the first substrate may include embedding a sacrificial material in the first substrate, disposing a first align mark over the sacrificial material, and disposing a first structure on a first surface of the first substrate. The method may also include exposing the sacrificial material by removing a part of the first substrate from a rear surface of the first substrate opposite the first surface of the first substrate and removing the sacrificial material. The method may further include processing a second substrate. Processing of the second substrate may include disposing a second align mark and a second structure at a surface of the second substrate. The method may additionally include disposing the first substrate over the second substrate such that the second structure and the first structure face each other, and coupling the first structure and the second structure by checking alignment of the first align mark with the second align mark through a region from which the sacrificial material was removed.

According to an embodiment, a method of manufacturing a semiconductor memory device may include forming a first align mark and a peripheral circuit over a first substrate, forming a second align mark and a memory cell array over a second substrate, orientating the first substrate and the second substrate such that the peripheral circuit and the memory cell array face each other, and aligning and coupling the peripheral circuit with the memory cell array. Aligning the peripheral circuit with the memory cell array includes measuring capacitance between the first align mark and the second align mark.

DETAILED DESCRIPTION

Various embodiments are directed to a manufacturing method of a semiconductor memory device capable of improving the process stability.

FIGS. 1A, 1B, 2A, 2B, and 3are cross-sectional diagrams illustrating a method of manufacturing a semiconductor memory device according to an embodiment.

FIG. 1Aillustrates processing a first substrate101.

Referring toFIG. 1A, the first substrate101may be a single crystal semiconductor layer. For example, the first substrate101may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial film formed by a selective epitaxial growth method.

The first substrate101may include a first region A11and a second region A12. The first substrate101may be processed such that a first structure ST11may be disposed on a surface Sa of the first substrate101, a sacrificial material105may be embedded in the first substrate101, and a first align mark107may be disposed on the sacrificial material105.

The first structure ST11may include a memory cell array or a peripheral circuit. The memory cell array may include memory cells arranged in three dimensions or memory cells arranged in two dimensions. The first structure ST11may be formed over the first region A11of the first substrate101.

The sacrificial material105may be embedded in the second region A12of the first substrate101. The sacrificial material105may protrude farther than the surface Sa of the first substrate101and may be covered by an insulating structure103. The insulating structure103may include one or more insulating layers. The sacrificial material105may include a different material from the insulating structure103. For example, the sacrificial material105may include a material having a different etch rate from the insulating structure103. According to an embodiment, the insulating structure103may include an oxide layer, and the sacrificial material105may include a nitride layer.

The first align mark107may be simultaneously formed with a part of elements that constitute the first structure ST11when the first structure ST11is formed. The first align mark107may include a conductive material. The first align mark107may be embedded in the insulating structure103and covered by a protective layer109.

The protective layer109may include a material that prevents the first align mark107from being oxidized. For example, the protective layer109may include a nitride layer.

The first substrate101may include a rear surface Sb facing opposite direction to the surface Sa. A first thickness D1may be defined between the rear surface Sb and the surface Sa of the first substrate101.

Referring toFIG. 1B, the second substrate151may be a single crystal semiconductor layer. For example, the second substrate151may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial film formed by a selective epitaxial growth method.

The second substrate151may include a first region A11′ and a second region A12′. The second substrate151may be processed such that a second structure ST12and an insulating structure153are disposed on a surface Sc of the second substrate151and a step may be defined between a second align mark157and the insulating structure153. The insulating structure153may include one or more insulating layers.

The second structure ST12may include a memory cell array or a peripheral circuit. For example, when the first structure ST11shown inFIG. 1Aincludes a peripheral circuit, the second structure ST12may include a memory cell array. In another example, when the first structure ST11shown inFIG. 1Aincludes a memory cell array, the second structure ST12may include a peripheral circuit. The second structure ST12may be formed over the first region A11′ of the second substrate151.

The insulating structure153may cover the second region A12′ of the second substrate151.

The second align mark157may be simultaneously formed with a part of elements that constitute the second structure ST12when the second structure ST12is formed. The second align mark157may include patterns protruding farther than a surface of the insulating structure153and may be spaced apart from each other to define a step between the second align mark157and the insulating structure153. The patterns included in the second align mark157may include a conductor or a nonconductor. The second align mark157may be distinguished by the step.

FIGS. 2A and 2Billustrate exposing the first align mark107.

Referring toFIG. 2A, the first substrate101may be partially removed from the rear surface Sb of the first substrate101described with reference toFIG. 1Ato expose the sacrificial material105. Accordingly, a first substrate101A having a second thickness D2smaller than the first thickness D1shown inFIG. 1Amay be formed. The first substrate101may be ground from the rear surface Sb of the first substrate101described with reference toFIG. 1Ato form the first substrate101A having the second thickness D2. Because the first substrate101A is not completely removed but remains to have the second thickness D2, a crack due to stress which is caused during a subsequent process to couple a memory cell array and a peripheral circuit may be prevented.

Subsequently, the exposed sacrificial material105may be selectively removed. When the sacrificial material105includes a nitride layer, phosphoric acid may be used to selectively remove the sacrificial material105. A groove G exposing the first align mark107may be defined by removing the sacrificial material105as shown inFIG. 2B.

Referring toFIG. 2B, an auxiliary groove AG may be defined by removing the protective layer109shown inFIG. 2Awhen the sacrificial material105shown inFIG. 2Ais removed to form the groove G. The groove G and the auxiliary groove AG may expose the first align mark107from opposite directions.

FIG. 3illustrates aligning the first substrate101A and the second substrate151to couple the first structure ST11and the second structure ST12.

Referring toFIG. 3, the first substrate101A having the second thickness may be aligned over the second substrate151such that the first structure ST11faces the second structure ST12. The arrangement of the first substrate101A having the second thickness and the second substrate151in the vertical direction may be reversed.

A degree of alignment may be checked by detecting alignment of the first align mark107and the second align mark157to correctly align the first structure ST11and the second structure ST12. When the first align mark107and the second align mark157are correctly aligned, the first structure ST11and the second structure ST12may be coupled to each other.

The alignment of the first align mark107and the second align mark157may be detected through the groove G. According to an embodiment, the first align mark107and the second align mark157may be detected through the groove G without interruption of the first substrate101A. According to this embodiment, the accuracy of a detection signal regarding the first align mark107and the second align mark157may be improved.

FIG. 4is a plan view illustrating alignment of the first align mark107and the second align mark157according to an embodiment.

Referring toFIG. 4, the first structure ST11and the second structure ST12shown inFIG. 3may be coupled when the first align mark107and the second align mark157are aligned to form a predetermined pattern as shown inFIG. 4or to be within a margin of error. The first align mark107and the second align mark157are not limited to the shape shown inFIG. 4, but may be variously changed.

FIGS. 5A to 5Care cross-sectional diagrams illustrating a method of manufacturing a semiconductor memory device according to an embodiment.

Referring toFIG. 5A, a first structure ST21and a first align mark207may be formed on a first substrate201. The first substrate201may include the same material as the first substrate101described above with reference toFIG. 1A. The first substrate201may include a first region A21and a second region A22.

The first structure ST21may include a memory cell array or a peripheral circuit and may be formed over the first region A21of the first substrate201as described above with reference toFIG. 1A. The second region A22of the first substrate201may be covered by an insulating structure203. The insulating structure203may include a single insulating layer or multilayer insulting layers. The first align mark207may include first capacitor electrodes207aspaced apart from each other.

Although not illustrated inFIG. 5A, a contact pad and a contact plug may be electrically coupled to each of the first capacitor electrodes207ato apply an electrical signal to the first capacitor electrodes207afrom a rear surface side of the first substrate201. The contact pad may be embedded in the first substrate201and the contact plug may pass through the insulating structure203to be coupled to the contact pad and the corresponding first capacitor electrode. Embodiments of structures of the contact pad and the contact plug are described below with reference toFIGS. 15D and 16E.

Referring toFIG. 5B, a second structure ST22and a second align mark257may be formed on a second substrate251. The second substrate251may include the same material as the second substrate151described above with reference toFIG. 1B. The second substrate251may include a first region A21′ and a second region A22′.

The second structure ST22may include a memory cell array or a peripheral circuit and may be formed over the first region A21′ of the second substrate251as described above with reference toFIG. 1B. The second region A22′ of the second substrate251may be covered by an insulating structure253. The insulating structure253may include a single insulating layer or multilayer insulting layers. The second align mark257may include second capacitor electrodes257aspaced apart from each other.

Although not illustrated inFIG. 5B, a contact pad and a contact plug may be electrically coupled to each of the second capacitor electrodes257ato apply an electrical signal to the second capacitor electrodes257afrom a rear surface side of the second substrate251. The contact pad may be embedded in the second substrate251and the contact plug may pass through the insulating structure253to be coupled to the contact pad and the corresponding second capacitor electrode. Embodiments of structures of the contact pad and the contact plug are described below with reference toFIGS. 15D and 16E.

Referring toFIG. 5C, the first substrate201and the second substrate251may be aligned such that the first structure ST21faces the second structure ST22.

Capacitance C1and C2between the first align mark207and the second align mark257may be measured to correctly align the first structure ST21and the second structure ST22. For example, the first capacitor electrodes207aof the first align mark207and the second capacitor electrodes257aof the second align mark257may be alternately arranged in a horizontal direction. First capacitance C1and second capacitance C2between one of the first capacitor electrodes207aand the second capacitor electrodes257aadjacent thereto may be measured. When the first capacitance C1and the second capacitance C2are measured and have values within margin of error, the first structure ST21and the second structure ST22may be coupled to each other.

FIGS. 6A to 6Care cross-sectional diagrams illustrating a method of manufacturing a semiconductor memory device according to an embodiment.

Referring toFIG. 6A, a first structure ST31and a first align mark307may be formed on a first substrate301. The first substrate301may include the same material as the first substrate101described above with reference toFIG. 1A. The first substrate301may include a first region A31and a second region A32.

The first structure ST31may include a memory cell array or a peripheral circuit and may be formed over the first region A31of the first substrate301as described above with reference toFIG. 1A. The second region A32of the first substrate301may be covered by an insulating structure303. The insulating structure303may include a single insulating layer or multilayer insulting layers. The first align mark307may be formed in the insulating structure303. The first align mark307may include a conductive material.

Although not illustrated inFIG. 6A, a contact pad and a contact plug may be electrically coupled to the first align mark307to apply an electrical signal to the first align mark307from a rear surface side of the first substrate301. The contact pad may be embedded in the first substrate301and the contact plug may pass through the insulating structure303to be coupled to the contact pad and to be coupled to the first align mark307. Embodiments of structures of the contact pad and the contact plug are described below with reference toFIGS. 18C and 19C.

Referring toFIG. 6B, a second structure ST32and a second align mark357may be formed on a second substrate351. The second substrate351may include the same material as the second substrate151described above with reference toFIG. 1B. The second substrate351may include a first region A31′ and a second region A32′.

The second structure ST32may include a memory cell array or a peripheral circuit and may be formed over the first region A31′ of the second substrate351as described above with reference toFIG. 1B. The second region A32′ of the second substrate351may be covered by an insulating structure353. The insulating structure353may include a single insulating layer or multilayer insulting layers. The second align mark357may be formed in the insulating structure353. The second align mark357may include a conductive material.

Although not illustrated inFIG. 6B, a contact pad and a contact plug may be electrically coupled to the second align mark357to apply an electrical signal to the first align mark357from a rear surface side of the second substrate351. The contact pad may be embedded in the second substrate351and the contact plug may pass through the insulating structure353to be coupled to the contact pad and to be coupled to the second align mark357. Embodiments of structures of the contact pad and the contact plug are described below with reference toFIGS. 18C and 19C.

Referring toFIG. 6C, the first substrate301and the second substrate351may be orientated such that the first structure ST31faces the second structure ST32.

Vertical capacitance VC between the first align mark307and the second align mark357may be measured to correctly align the first structure ST31and the second structure ST32. When the measured vertical capacitance VC has a reference value, the first structure ST31and the second structure ST32may be coupled to each other.

The first align mark illustrated inFIGS. 1A, 5A, and 6Amay be simultaneously formed with a part of elements included in the first structure. The second align mark illustrated inFIGS. 1B, 5B, and 6Bmay be simultaneously formed with a part of elements included in the second structure. Accordingly, embodiments of the present teachings may increase the alignment accuracy between the first structure and the second structure using the first align mark and the second align mark as described above. The second region of the first substrate at which the first align mark is formed and the second region of the second substrate at which the second align mark is formed may couple the first structure and the second structure and may be cut.

Hereinafter, embodiments in which the alignment between the first structure and the second structure is controlled are described in detail with an example in which the first structure includes a peripheral circuit and the second structure includes a three-dimensional memory cell array. Embodiments are not limited to the presented embodiments described herein. For example, the first structure described below may be replaced by a three-dimensional memory cell array and the second structure may be replaced by a peripheral circuit.

FIGS. 7A to 7Care cross-sectional diagrams illustrating a semiconductor memory device according to an embodiment.

Referring toFIG. 7A, a first structure STa and a second structure STb may be disposed between a first substrate401and a second substrate501.

FIG. 7Bis an enlarged view of region X shown inFIG. 7A.

Referring toFIG. 7B, the first structure STa may include a peripheral circuit including transistors TR, a first insulating structure IS1covering the peripheral circuit, connection structures417,419,423, and429passing through the first insulating structure IS1, a second insulating structure IS2covering the connection structures417,419,423, and429, and first conductive contact patterns433passing through the second insulating structure IS2.

The transistors TR may be separated from each other by isolation layers403disposed in the first substrate401. Active regions may be defined by the isolation layers403in the first substrate401. Each of the transistors TR may include a gate insulating layer411formed over the active region, a gate electrode413formed on the gate insulating layer411, impurity regions405formed at both sides of the gate electrode413in the first substrate401. The impurity regions405may include an n-type or p-type dopant and serve as a source region or a drain region. The transistors TR may be connected to a memory cell array CAR illustrated inFIG. 7Aand may control operations of the memory cell array CAR.

The first insulating structure IS1may include one or more insulating layers415and421. According to an embodiment, the first insulating structure IS1may include at least one first etch stop layer425. For example, the first insulating structure IS1may include the first insulating layer415formed on the first substrate401to cover the transistors TR, the second insulating layer421formed on the first insulating layer415, and the first etch stop layer425formed on the second insulating layer421. A stacked structure of the first insulating structure IS1is not limited to the embodiment illustrated inFIG. 7Bbut may be variously changed. The first etch stop layer425may include a material having a different etch rate from the second insulating layer421. For example, the first insulating layer415and the second insulating layer421may include oxide layers and the first etch stop layer425may include a nitride layer.

The connection structures417,419,423, and429may include the contact plugs417and423and the conductive pads419and429. For example, the connection structures417,419,423, and429may include the first contact plugs417, the first conductive pads419each having a greater width than each of the first contact plugs417, the second contact plugs423connected to the first conductive pads419, and the second conductive pads429each having a greater width than each of the second contact plugs423. The first contact plugs417may pass through the first insulating layer415to be connected to the impurity regions405and the gate electrode413of the transistors TR. The first conductive pads419may be disposed in the second insulating layer421and coupled to the first contact plugs417. The second contact plugs423may be disposed in the second insulating layer421and coupled to the first conductive pads419. The second conductive pads429may pass through the first etch stop layer425to be coupled to the second contact plugs423.

The connection structures417,419,423, and429are not limited to the embodiment illustrated inFIGS. 7A and 7Bbut may be variously changed. The connection structures417,419,423, and429may include various conductive materials.

The second insulating structure IS2may include a third insulating layer427and a second etch stop layer431. The second etch stop layer431may be omitted in some embodiments. The third insulating layer427may include a material having a different etch rate from the second etch stop layer431. For example, the third insulating layer427may include an oxide layer and the second etch stop layer431may include a nitride layer.

The first conductive contact patterns433may pass through the second insulating structure IS2and may be electrically coupled to a peripheral circuit. For example, the first conductive contact patterns433may pass through the second etch stop layer431and the third insulating layer427to be connected to the second conductive pads429. Accordingly, the first conductive contact patterns433may be coupled to the transistors TR via the connection structures417,419,423, and429.

Coupling between the first conductive contact patterns433and the peripheral circuit is not limited to the embodiment described above, but may be variously changed.

Each of the first conductive contact patterns433may include a protrusion433P protruding farther than a surface of the second insulating structure IS2.

Referring toFIG. 7A, the second structure STb may include the memory cell array CAR, a third insulating structure IS3, bit lines BL, connection structures527,529,535,537, and541, supports523, a source contact structure SCT, and second conductive contact patterns543. The third insulating structure IS3may overlap the memory cell array CAR. The bit lines BL, the connection structures527,529,535,537, and541, the supports523, the source contact structure SCT, and the second conductive contact patterns543may be embedded in the third insulating structure IS3.

The memory cell array CAR may include memory strings STR coupled between a source region503and the bit lines BL. The source region503may be formed in the second substrate501and may include an impurity. The impurity of the source region503may include an n-type dopant.

FIG. 7Cis an enlarged cross-sectional diagram of one of the memory strings STR.

Referring toFIG. 7C, gate electrodes of the memory strings STR may be coupled to conductive patterns513of a gate stacked structure GST.

The gate stacked structure GST may include interlayer insulating layers511and the conductive patterns513stacked alternately with each other over the second substrate501shown inFIG. 7A. The gate stacked structure GST may be penetrated by channel structures CH.

The channel structures CH may serve as channel regions of the memory strings STR. The channel structures CH may include semiconductor layers. A central region of each of the channel structures CH may be filled with a core insulating layer CO. One end of each of the channel structures CH may be coupled to the source region503. The other end of each of the channel structures CH may be coupled to a doped pattern DP that overlaps the core insulating layer CO. The doped pattern DP may include an impurity, for example, an n-type dopant. The doped pattern DP may serve as a drain region.

A memory layer ML may be disposed between the corresponding conductive pattern513and the corresponding channel structure CH and may store data. The memory layer ML may include a tunnel insulating layer TI, a data storage layer DL, and a blocking insulating layer BI stacked on a sidewall of the corresponding channel structure CH towards a sidewall of the gate stacked structure GST. The tunnel insulating layer TI may include a silicon oxide enabling charge tunneling. The data storage layer DL may include a charge trap layer, a material layer including conductive nanodots, or a phase-change material layer. For example, the data storage layer DL may include silicon nitride, enabling charge trapping. The blocking insulating layer BI may include an oxide capable of blocking charges.

According to the structure described above, a source select transistor, memory cells, and a drain select transistor may be formed at intersections of the conductive patterns513and the channel structures CH. The source select transistor, the memory cells, and the drain select transistor may be coupled in series and may form the memory string STR corresponding thereto. A gate electrode of the source select transistor may be coupled to a source side conductive pattern adjacent to the source region503among the conductive patterns513. A gate electrode of the drain select transistor may be coupled to a bit line side conductive pattern adjacent to the bit lines BL shown inFIG. 7Aamong the conductive patterns513. Gate electrodes of the memory cells may be coupled to intermediate conductive patterns among the conductive patterns513. The intermediate conductive patterns may be disposed between the source side conductive pattern and the bit line side conductive pattern.

Referring toFIG. 7A, the source contact structure SCT may pass through the gate stacked structure GST and transmit an electrical signal to the source region503. The source contact structure SCT may be a single conductive layer or include two or more conductive layers. The source contact structure SCT and the gate stacked structure GST may be insulated from each other by a sidewall insulating layer505interposed therebetween.

The conductive patterns513of the gate stacked structure GST may include a contact region having a stepped structure. The contact region having the stepped structure may be penetrated by the plurality of supports523.

The third insulating structure IS3may include one or more insulating layers521,525, and533. According to an embodiment, the third insulating structure IS3may include a third etch stop layer531. For example, the third insulating structure IS3may include the fourth insulating layer521, the fifth insulating layer525, the third etch stop layer531, and the sixth insulating layer533. The fourth insulating layer521may be disposed over one surface of the second substrate501to cover the stepped structure of the gate stacked structure GST. The fifth insulating layer525, the third etch stop layer531, and the sixth insulating layer533may be sequentially stacked between the fourth insulating layer521and the first structure STa. The third insulating structure IS3is not limited to the embodiment illustrated inFIG. 7Abut may be variously changed. The third etch stop layer531may include a material having a different etch rate from the fourth, fifth, and sixth insulating layers521,525, and533. For example, the fourth, fifth, and sixth insulating layers521,525, and533may include oxide layers and the third etch stop layer531may include a nitride layer.

The connection structures527,529,535,537, and541may include the contact plugs527,529, and541and the conductive pads535and537that are embedded in the third insulating structure IS3. For example, the connection structures527,529,535,537, and541may include the gate contact plugs527, the drain contact plugs529, the gate pads535each having a greater width than each of the gate contact plugs527, the source pad537having a greater width than the source contact structure SCT, and the pad contact plugs541.

The gate contact plugs527may contact the conductive patterns513of the gate stacked structure GST described above with reference toFIG. 7Cand may extend to pass through the fourth insulating layer521and the fifth insulating layer525. The source contact structure SCT may extend to pass through the fifth insulating layer525. The drain contact plugs529may be coupled to the memory strings STR and may pass through the fifth insulating layer525.

The gate pads535may contact the gate contact plugs527. The source pad537may contact the source contact structure SCT. The bit lines BL may contact the drain contact plugs529. The gate pads535, the source pad537, and the bit lines BL may pass through the third etch stop layer531and extend into the sixth insulating layer533.

The pad contact plugs541may contact the gate pads535, the source pad537, and the bit lines BL and extend to pass through the sixth insulating layer533.

The connection structures527,529,535,537, and541are not limited to the embodiment illustrated inFIG. 7Abut may be variously changed. The connection structures527,529,535,537, and541may include various conductive materials.

The second conductive contact patterns543may contact the pad contact plugs541and may be embedded in an upper insulating layer545. The second conductive contact patterns543may be coupled to the memory cell array CAR via the connection structures527,529,535,537, and541. The upper insulating layer545may include a plurality of grooves551opening the second conductive contact patterns543. The upper insulating layer545may be disposed between the first structure STa and the second structure STb.

The first structure STa and the second structure STb may be coupled to each other via the first conductive contact patterns433and the second conductive contact patterns543. The protrusion433P of the first conductive contact pattern433corresponding to the each of the grooves551may be aligned in each of the grooves551of the upper insulating layer545. The first conductive contact patterns433and the second conductive contact patterns543may be coupled to each other via conductive adhesive patterns561filling the grooves551. The conductive adhesive patterns561may include a cured material of silver epoxy resin or a cured material of a complex having silver nanoparticles, boron nitride, and epoxy.

The coupling between the first conductive contact patterns433and the second conductive contact patterns543might not be limited to the embodiment illustrated inFIG. 7A. For example, the first conductive contact patterns433and the second conductive contact patterns543may directly contact each other.

FIGS. 8A to 8G, 9, and 10are cross-sectional diagrams illustrating a method of manufacturing a semiconductor memory device according to an embodiment. In diagrams described below, detailed explanation of the first structure and the second structure is the same as that described above with reference toFIGS. 7A, 7B, and 7Cand is therefore not repeated.

FIGS. 8A to 8Gare cross-sectional diagrams illustrating processing a first substrate to have a first structure and a first align mark.

Referring toFIG. 8A, a first substrate400may include the same material as the first substrate101described above with reference toFIG. 1A. The first substrate400may include a first region A1aand a second region A2a.

A peripheral circuit including the transistors TR may be formed over the first region A1aof the first substrate400. The transistors TR may be insulated from each other by the isolation layers403formed in the first substrate400. The peripheral circuit including the transistors TR may be covered by the first insulating structure IS1. The first and second contact plugs417and423and the first conductive pads419may be embedded in the first insulating structure IS1.

The first insulating layer415, the second insulating layer421, and the first etch stop layer425which constitute the first insulating structure IS1may extend to cover the second region A2aof the first substrate400.

Subsequently, the first insulating structure IS1and the second region A2aof the first substrate400may be etched to form the first groove G in the second region A2aof the first substrate400.

Referring toFIG. 8B, the first groove G may be filled with a sacrificial material473. A first protective layer471may be formed on a surface of the first groove G before the first groove G is filled with the sacrificial material473. The sacrificial material473may include a material having a different etch rate from the first protective layer471, the first insulating layer415, and the second insulating layer421. For example, each of the first protective layer471, the first insulating layer415, and the second insulating layer421may include an oxide layer and the sacrificial material473may include a nitride layer.

Referring toFIG. 8C, the second conductive pads429passing through the first etch stop layer425of the first insulating structure IS1and coupled to the second contact plugs423may be formed.

Subsequently, the second insulating structure IS2extending to cover the second conductive pads429and the sacrificial material473may be formed on the first insulating structure IS1. The second insulating structure IS2may include a stacked structure of the third insulating layer427, the second etch stop layer431, and the sacrificial insulating layer451. The sacrificial insulating layer451may include an oxide layer.

Subsequently, the first conductive contact patterns433and a first align mark475that pass through the second insulating structure IS2may be formed. The first align mark475may be formed using a process of forming the first conductive contact patterns433. For example, forming the first conductive contact patterns433and the first align mark475may include forming a mask pattern (not illustrated) on the second insulating structure IS2, etching the second insulating structure IS2by an etching process using the mask pattern as an etching barrier, filling regions where the second insulating structure IS2is etched by a conductive material, and removing the mask pattern.

The first conductive contact patterns433may contact the second conductive pads429to be coupled to the peripheral circuit. The first align mark475may contact the sacrificial material473.

Referring toFIG. 8D, the auxiliary groove AG may be formed by etching a part of the sacrificial insulating layer451to expose the first align mark475shown inFIG. 8C. Subsequently, a first align mark with a reduced length475P as shown inFIG. 8Dmay be formed by removing an end portion of the first align mark475which is exposed by the auxiliary groove AG. The first align mark with the reduced length475P may have a smaller length than each of the first conductive contact patterns433.

A probability that the shape of the first align mark475P, having a low aspect ratio due to the reduced length, is changed by effects of a subsequent process may be low. Therefore, according to an embodiment, the accuracy of measurement of degree of alignment may be improved using the first align mark with the reduced length475P.

Referring toFIG. 8E, a second protective layer477may be formed on a surface of the auxiliary groove AG. The second protective layer477may include a material layer having a different etch rate from the sacrificial insulating layer451. For example, the second protective layer477may include a nitride layer.

Subsequently, another part of the sacrificial insulating layer451disposed over the first region A1aof the first substrate400may be removed. Accordingly, the second etch stop layer431may be exposed and end portions of the first conductive contact patterns433may be exposed. The exposed end portions of the first conductive contact patterns433may be defined as protrusions433P.

Subsequently, a part of the first substrate400may be etched from a rear surface of the first substrate400. Accordingly, the sacrificial material473may be exposed and a first substrate with a reduced thickness401may remain as shown inFIG. 8F.

Referring toFIG. 8G, the first groove G may be opened by removing the sacrificial material473shown inFIG. 8F. When the sacrificial material473is removed, the second protective layer477shown inFIG. 8Fmay be removed. Accordingly, the first align mark with the reduced length475P may be exposed by the first groove G and the auxiliary groove AG.

FIG. 9is a cross-sectional diagram illustrating a second substrate including a second structure and a second align mark.

Referring toFIG. 9, the second substrate501may be processed to include the second structure STb described above with reference toFIGS. 7A and 7C. The second substrate501may include a first region A1a′ and a second region A2a′.

The second structure STb may be formed over the first region A1a′ of the second substrate501. The fourth insulating layer521, the fifth insulating layer525, the third etch stop layer531, and the sixth insulating layer533included in the third insulating structure IS3of the second structure STb may extend over the second region A2a′ of the second substrate501.

A second align mark575may be formed over the second region A2a′ of the second substrate501when the second conductive contact patterns543of the second structure STb are formed. Accordingly, the second align mark575may be formed from the same material as the second conductive contact patterns543.

The second conductive contact patterns543may be embedded in the upper insulating layer545including the second grooves551and may be exposed by the second grooves551. The second align mark575may be covered by a seventh insulating layer579conformally formed along a step defined by the second align mark575.

FIG. 10is a cross-sectional diagram illustrating aligning the first substrate with the reduced thickness401and the second substrate501with each other.

Referring toFIG. 10, the second grooves551may be filled with a conductive adhesive material561A. The conductive adhesive material561A may be a flowable material for which the viscosity can be controlled by a solvent such as acetone or alcohol. For example, the conductive adhesive material561A may include silver epoxy resin or a complex having silver nanoparticles, boron nitride, and epoxy. A height of the conductive adhesive material561A having fluidity may be controlled such that the conductive adhesive material561A does not overflow the second grooves551into an outside region during a subsequent process. For example, the height of the conductive adhesive material561A may be adjusted to be less than a depth of each of the second grooves551.

Subsequently, the first substrate with the reduced thickness401and the second substrate501may be orientated such that the first conductive contact patterns433face the second conductive contact patterns543. The alignment of the first align mark with the reduced length475P and the second align mark575may be detected through the first groove G. When the first align mark with the reduced length475P and the second align mark575are correctly aligned, the upper insulating layer545may be adhered to the second insulating structure IS2to dispose the protrusions433P of the first conductive contact patterns433in the second grooves551and the conductive adhesive material561A may be cured by heat. Accordingly, the first structure STa and the second structure STb coupled by the conductive adhesive pattern561shown inFIG. 7Amay be formed.

After the first structure STa and the second structure STb are coupled to each other by the conductive adhesive pattern561, the second region A2aof the first substrate401and the second region A2a′ of the second substrate501shown inFIG. 10may be removed by a cutting process as illustrated inFIG. 7A.

FIG. 11is a cross-sectional diagram illustrating a semiconductor memory device according to an embodiment.

Referring toFIG. 11, a first structure STa′ and a second structure STb′ may be disposed between a first substrate601and a second substrate701.

As described above with reference toFIGS. 7A and 7B, the first structure STa′ may include a peripheral circuit including the transistors TR, a first insulating structure IS1′ covering the peripheral circuit, connection structures617,619, and623passing through the first insulating structure IS1′, a second insulating structure IS2′ covering the connection structures617,619, and623, and first conductive contact patterns633passing through the second insulating structure IS2′.

The first insulating structure IS1′ may include one or more insulating layers. For example, the first insulating structure IS1′ may include a first insulating layer615and a second insulating layer621. Each of the first and second insulating layers615and621may include an oxide layer.

The connection structures617,619, and623may include the contact plugs617and623and the conductive pads619that pass through the first insulating structure IS1′. For example, the connection structures617,619, and623may include the first contact plugs617, the conductive pads619each having a greater width than each of the first contact plugs617, and the second contact plugs623connected to the conductive pads619. The first contact plugs617and the second contact plugs623may have the same structures as the first contact plugs417and the second contact plugs423described above with reference toFIG. 7B. The conductive pads619may have the same structure as the first conductive pads419described above with reference toFIG. 7B.

The second insulating structure IS2′ may include at least one insulating layer. For example, the second insulating structure IS2′ may include a third insulating layer627. The third insulating layer627may include an oxide layer.

The first conductive contact patterns633may pass through the second insulating structure IS2′ and may be electrically coupled to the peripheral circuit. For example, the first conductive contact patterns633may pass through the third insulating layer627to contact the second contact plugs623. Accordingly, the first conductive contact patterns633may be coupled to the transistors TR via the connection structures617,619, and623.

The second structure STb′ may include the memory cell array CAR, a third insulating structure IS3′, the bit lines BL, connection structures727,729,735,737, and741, supports723, the source contact structure SCT, and second conductive contact patterns743. The third insulating structure IS3′ may overlap the memory cell array CAR. The bit lines BL and the connection structures727,729,735,737, and741may be embedded in the third insulating structure IS3′. The supports723and the source contact structure SCT may pass through the gate stacked structure GST. The second conductive contact patterns743may be coupled to the memory cell array CAR.

The memory cell array CAR may include the memory strings STR coupled between a source region703and the bit lines BL as described above with reference toFIG. 7A. The memory strings STR may have the same structure as the memory string STR illustrated inFIG. 7C.

As described above with reference toFIG. 7A, the source contact structure SCT may pass through the gate stacked structure GST and transmit an electrical signal to the source region703. The source contact structure SCT and the gate stacked structure GST may be insulated from each other by a sidewall insulating layer705interposed therebetween.

The gate stacked structure GST and the supports723may have the same structures as the gate stacked structure GST and the supports523described above with reference toFIG. 7A.

The third insulating structure IS3′ may include one or more insulating layers as described above with reference toFIG. 7A. For example, the third insulating structure IS3′ may include a fourth insulating layer721, a fifth insulating layer725, and a sixth insulating layer733.

The connection structures727,729,735,737, and741may include the contact plugs727,729,741and the conductive pads735and737that are embedded in the third insulating structure IS3′ as described above with reference toFIG. 7A.

The second conductive contact patterns743may contact the pad contact plugs741among the contact plugs727,729, and741and may be embedded in an upper insulating layer745. The second conductive contact patterns743may be coupled to the memory cell array CAR via the connection structures727,729,735,737, and741.

The first structure STa′ and the second structure STb′ may be coupled to each other via the first conductive contact patterns633and the second conductive contact patterns743by direct contact between the first conductive contact patterns633and the second conductive contact patterns743. The first conductive contact patterns633and the second conductive contact patterns743may include copper.

FIGS. 12A to 12G, 13, and 14are cross-sectional diagrams illustrating a method of manufacturing a semiconductor memory device according to an embodiment. In diagrams described below, detailed explanation of the first structure and the second structure is the same as that described above with reference toFIG. 11and is therefore not repeated.

FIGS. 12A to 12Gare cross-sectional diagrams illustrating processing a first substrate to have a first structure and a first align mark.

Referring toFIG. 12A, a first substrate600may include the same material as the first substrate101described above with reference toFIG. 1A. The first substrate600may include a first region A1band a second region A2b.

A peripheral circuit including the transistors TR may be formed over the first region A1bof the first substrate600. The peripheral circuit including the transistors TR may be covered by the first insulating structure IS1′. The first and second contact plugs617and623and the conductive pads619may be embedded in the first insulating structure IS1′.

The first and second insulating layers615and621which constitute the first insulating structure IS1′ may extend to cover the second region A2bof the first substrate600.

Subsequently, the first insulating structure IS1′ and the second region A2bof the first substrate600may be etched to form a groove G′ in the second region A2bof the first substrate600.

Referring toFIG. 12B, the groove G′ may be filled with a sacrificial material673. A first protective layer671may be formed on a surface of the groove G′ before the groove G′ is filled with the sacrificial material673. The sacrificial material673and the first and second insulating layers615and621may include the same material. For example, each of the sacrificial material673and the first and second insulating layers615and621may include an oxide layer. The first protective layer671may include a material having a different etch rate from the sacrificial material673and the first and second insulating layers615and621. For example, the first protective layer671may include a nitride layer.

Subsequently, the second insulating structure IS2′ extending to cover the sacrificial material673may be formed on the first insulating structure IS1′. The second insulating structure IS2′ may include the third insulating layer627. The third insulating layer627may include an oxide layer.

Subsequently, a part of the second insulating structure IS2′ may be etched to expose the sacrificial material673. Subsequently, a region from which the second insulating structure IS2′ is etched may be filled with a second protective layer675. The second protective layer675may include a material having a different etch rate from the sacrificial material673. For example, the second protective layer675may include a nitride layer.

Referring toFIG. 12C, the first conductive contact patterns633passing through the second insulating structure IS2′ and a first align mark683passing through the second protective layer675may be formed. The first conductive contact patterns633and the first align mark683may be simultaneously formed using the processes described above with reference toFIG. 8C. The first conductive contact patterns633may include copper.

The first conductive contact patterns633may contact the second contact plugs623to be coupled to the peripheral circuit. The first align mark683may contact the sacrificial material673.

Referring toFIG. 12D, a third protective layer685may be formed to cover the first conductive contact patterns633and the first align mark683. The third protective layer685may include a material having a different etch rate from the sacrificial material673. For example, the third protective layer685may include a nitride layer.

Subsequently, a part of the third protective layer685formed over the second region A1bof the first substrate600may be etched to form an auxiliary groove AG′ exposing the first align mark683. Subsequently, the auxiliary groove AG′ may be filled with a fourth protective layer687. The fourth protective layer687may include the same material as the sacrificial material673. For example, the fourth protective layer687may include an oxide layer.

Subsequently, a part of the first substrate600may be etched from a rear surface of the first substrate600. Accordingly, the sacrificial material673may be exposed and a first substrate601with a reduced thickness may remain as illustrated inFIG. 12E.

Referring toFIG. 12F, the groove G′ may be opened by removing the sacrificial material673shown inFIG. 12E. When the sacrificial material673is removed, the fourth protective layer687shown inFIG. 12Emay be removed and the auxiliary groove AG′ may be opened. Accordingly, the first align mark683may be exposed by the groove G′ and the auxiliary groove AG′. When the sacrificial material673is removed, the second insulating structure IS2′ may be protected by the third protective layer685.

Referring toFIG. 12G, the first conductive contact patterns633may be exposed by removing the third protective layer685shown inFIG. 12F.

FIG. 13is a cross-sectional diagram illustrating a second substrate including a second structure and a second align mark.

Referring toFIG. 13, the second substrate701may be processed to include the second structure STb′ described above with reference toFIG. 11. The second substrate701may include a first region A1b′ and a second region A2b′.

The second structure STb′ may be formed over the first region A1b′ of the second substrate701. The fourth, fifth, and sixth insulating layers721,725, and733included in the third insulating structure IS3′ of the second structure STb′ may extend over the second region A2b′ of the second substrate701.

A second align mark775may be formed over the second region A2b′ of the second substrate701when second conductive contact patterns743of the second structure STb′ are formed. Accordingly, the second align mark775may be formed of the same material as the second conductive contact patterns743. For example, the second conductive contact patterns743may include copper.

The second conductive contact patterns743may be embedded in the upper insulating layer745and one surface of each of the second conductive contact patterns743may be exposed. The second align mark775may be covered by a seventh insulating layer779conformally formed along a step defined by the second align mark775.

FIG. 14is a cross-sectional diagram illustrating aligning the first substrate601with the reduced thickness and the second substrate701with each other.

Referring toFIG. 14, the first substrate601with the reduced thickness and the second substrate701may be orientated such that the first conductive contact patterns633and the second conductive contact patterns743face each other. The alignment of the first align mark683and the second align mark775may be detected through the groove G′. When the first align mark683and the second align mark775are correctly aligned, the first conductive contact patterns633may contact the second conductive contact patterns743. Subsequently, the first structure STa′ and the second structure STb′ coupled to each other by contact between the first conductive contact patterns633and the second conductive contact patterns743as illustrated inFIG. 11may be formed by applying heat to the first conductive contact patterns633and the second conductive contact patterns743that are in contact with each other.

After the first structure STa′ and the second structure STb′ are coupled to each other as illustrated inFIG. 11, the second region A2bof the first substrate601and the second region A2b′ of the second substrate701shown inFIG. 14may be removed by a cutting process.

FIGS. 15A to 15D, 16A to 16E, and 17are cross-sectional diagrams illustrating a method of manufacturing a semiconductor memory device according to an embodiment. In diagrams described below, detailed explanation of the first structure and the second structure is the same as that described above with reference toFIG. 11and is therefore not repeated.

FIGS. 15A to 15Dare cross-sectional diagrams illustrating processing a first substrate to have a first structure and a first align mark.

Referring toFIG. 15A, the first substrate600may include the same material as the first substrate101described above with reference toFIG. 1A. The first substrate600may include the first region A1band the second region A2b.

A first groove Ga may be formed at the first substrate600by etching the second region A2bof the first substrate600. Subsequently, a first lower etch stop layer801may be formed along a surface of the first groove Ga. Subsequently, first contact pads803may be formed on the first lower etch stop layer801.

Subsequently, a first gap-fill insulating layer805covering the first contact pads803and filling the first groove Ga may be formed. Subsequently, first lower contact plugs807passing through the first gap-fill insulating layer805to be coupled to the first contact pads803may be formed.

The first lower etch stop layer801and the first gap-fill insulating layer805may have different etch rates. For example, the first gap-fill insulating layer805may include an oxide layer and the first lower etch stop layer801may include a nitride layer.

The first contact pads803and the first lower contact plugs807may include conductive materials.

Referring toFIG. 15B, a peripheral circuit including the transistors TR may be formed over the first region A1bof the first substrate600. Subsequently, the first insulating layer615may be formed over the first substrate600. The first insulating layer615may extend to cover the peripheral circuit including the transistors TR and the first lower contact plugs807.

Subsequently, the first contact plugs617and first upper contact plugs811that pass through the first insulating layer615may be formed. The first contact plugs617may be coupled to the transistors TR. The first upper contact plugs811may be coupled to the first lower contact plugs807.

The first upper contact plugs811and the first contact plugs617may be formed at the same time. The first contact plugs617and the first upper contact plugs811may include conductive materials.

Referring toFIG. 15C, the conductive pads619coupled to the first contact plugs617may be formed. Subsequently, the second insulating layer621may be formed on the first insulating layer615. Accordingly, the first insulating structure IS1′ including the first insulating layer615and the second insulating layer621may be formed.

The second insulating layer621may extend to cover the conductive pads619and the first upper contact plugs811. Subsequently, the second contact plugs623and second upper contact plugs821that pass through the second insulating layer621may be formed. The second contact plugs623may be coupled to the conductive pads619. The second upper contact plugs821may be coupled to the first upper contact plugs811.

The second upper contact plugs821and the second contact plugs623may be formed at the same time. The second contact plugs623and the second upper contact plugs821may include conductive materials.

Subsequently, the second insulating structure IS2′ may be formed on the first insulating structure IS1′. The second insulating structure IS2′ may include the third insulating layer627and the third insulating layer627may include an oxide layer. The second insulating structure IS2′ may extend to cover the second contact plugs623and the second upper contact plugs821.

Subsequently, the first conductive contact patterns633and first capacitor electrodes823that pass through the second insulating structure IS2′ may be formed. The first capacitor electrodes823may constitute a first align mark and may be spaced apart from each other. The first conductive contact patterns633and the first capacitor electrodes823may be formed at the same time using the processes described above with reference toFIG. 8C. The first conductive contact patterns633may include copper.

The first conductive contact patterns633may contact the second contact plugs623to be coupled to the peripheral circuit. The first capacitor electrodes823may contact the second upper contact plugs821.

Subsequently, a part of the first substrate600may be etched from the rear surface of the first substrate600. Accordingly, the first contact pads803may be exposed and the first substrate601with the reduced thickness may remain as illustrated inFIG. 15D.

FIGS. 16A to 16Eare cross-sectional diagrams illustrating processing a second substrate to have a second structure and a second align mark.

Referring toFIG. 16A, a second substrate700may include the same material as the second substrate151described above with reference toFIG. 1B. The second substrate700may include the first region A1b′ and the second region A2b′.

A second groove Gb may be formed in the second substrate700by etching the second region A2b′ of the second substrate700. Subsequently, a second lower etch stop layer851may be formed along a surface of the second groove Gb. Subsequently, second contact pads853may be formed on the second lower etch stop layer851.

Subsequently, a second gap-fill insulating layer855covering the second contact pads853and filling the second groove Gb may be formed. Subsequently, second lower contact plugs857passing through the second gap-fill insulating layer855to be coupled to the second contact pads853may be formed.

The second lower etch stop layer851and the second gap-fill insulating layer855may have different etch rates. For example, the second gap-fill insulating layer855may include an oxide layer and the second lower etch stop layer851may include a nitride layer.

The second contact pads853and the second lower contact plugs857may include conductive materials.

Referring toFIG. 16B, the memory cell array CAR including the memory strings STR coupled to the source region703may be formed over the first region A1b′ of the second substrate700. The source region703may be formed by injecting a source dopant into the first region A1b′ of the second substrate700. The memory strings STR may have the same structure as the memory strings STR described above with reference toFIG. 11.

The gate stacked structure GST coupled to the memory strings STR may be penetrated by the supports723and may include a stepped end portion. The stepped end portion of the gate stacked structure GST may be covered by the fourth insulating layer721. The fourth insulating layer721may extend over the second region A2b′ of the second substrate700to cover the second gap-fill insulating layer855and the second lower contact plugs857.

Subsequently, the fifth insulating layer725may be formed to cover the memory strings STR. The fifth insulating layer725may be formed on the fourth insulating layer721and may extend over the second region A2b′ of the second substrate700. The fifth insulating layer725may be penetrated by the source contact structure SCT. The source contact structure SCT may pass through the gate stacked structure GST to contact the source region703. The sidewall insulating layer705may be formed between the source contact structure SCT and the gate stacked structure GST.

Subsequently, third upper contact plugs861, the gate contact plugs727, and the drain contact plugs729that pass through at least one of the fifth insulating layer725and the fourth insulating layer721may be formed. Forming the third upper contact plugs861, forming the gate contact plugs727, and forming the drain contact plugs729may be separately performed. The third upper contact plugs861, the gate contact plugs727, and the drain contact plugs729may include conductive materials.

The third contact plugs861may extend to contact the second lower contact plugs857. The gate contact plugs727may extend to contact the conductive patterns713of the gate stacked structure GST. The drain contact plugs729may extend to contact the doped patterns DP of the memory strings STR.

Referring toFIG. 16C, the gate pads735each having a greater width than each of the gate contact plugs727, the source pad737having a greater width than the source contact structure SCT, and the bit lines BL may be formed on the fifth insulating layer725. The gate pads735may be coupled to the gate contact plugs727, the source pad737may be coupled to the source contact structure SCT, and the bit lines BL may be coupled to the drain contact plugs729.

Subsequently, the sixth insulating layer733covering the gate pads735, the source pad737, and the bit lines BL may be formed. The sixth insulating layer733may extend over the second region A1b′ of the second substrate700. Accordingly, the third insulating structure IS3′ including the fourth, fifth, and sixth insulating layers721,725,733may be formed.

Subsequently, fourth upper contact plugs871and the pad contact plugs741that pass through the sixth insulating layer733may be formed. The fourth upper contact plugs871and the pad contact plugs741may be formed by the same process and may include the same conductive material. The fourth upper contact plugs871may extend to contact the third upper contact plugs861. The pad contact plugs741may extend to contact the gate pads735, the source pad737, and the bit lines BL.

Referring toFIG. 16D, the upper insulating layer745may be formed on the third insulating structure IS3′. Subsequently, the second conductive contact patterns743and second capacitor electrodes881that pass through the upper insulating layer745may be formed. The second capacitor electrodes881may constitute a second align mark and may be spaced apart from each other. The second conductive contact patterns743and the second capacitor electrodes881may be formed by the same process and may include the same conductive material. The second conductive contact patterns743may include copper.

The second capacitor electrodes881may extend to contact the fourth upper contact plugs871. The second conductive contact patterns743may extend to contact the pad contact plugs741.

Subsequently, a part of the second substrate700may be etched from a rear surface of the second substrate700. Accordingly, the second contact pads853may be exposed and the second substrate701with a reduced thickness may remain as illustrated inFIG. 16E.

FIG. 17is a cross-sectional diagram illustrating aligning the first substrate601with the reduced thickness and the second substrate701with the reduced thickness with each other.

Referring toFIG. 17, the first substrate601with the reduced thickness and the second substrate701with the reduced thickness may be orientated such that the first conductive contact patterns633and the second conductive contact patterns743face each other. Capacitance between the first capacitor electrodes823forming the first align mark and the second capacitor electrodes881forming the second align mark may be measured.

The first capacitor electrodes823and the second capacitor electrodes881may be alternately aligned in a horizontal direction as shown. When capacitances between the first capacitor electrodes823and the second capacitor electrodes881that neighbor each other is measured and have values within margin of error and it is determined that the first substrate601and the second substrate701are correctly aligned, the first conductive contact patterns633may be coupled to the second conductive contact patterns743. Accordingly, the first structure STa′ and the second structure STb′ coupled to each other via the first conductive contact patterns633and the second conductive contact patterns743may be formed as illustrated inFIG. 11. The first conductive contact patterns633and the second conductive contact patterns743may be treated by heat to couple the first structure STa′ and the second structure STb′.

Capacitances between the first capacitor electrodes823and the second capacitor electrodes881may be measured by applying electrical signals through the first contact pads803and the second contact pads853. The signal applied to the first contact pads803may be applied to the first capacitor electrodes823via the first lower contact plugs807, the first upper contact plugs811, and the second upper contact plugs821. The signal applied to the second contact pads853may be applied to the second capacitor electrodes881via the second lower contact plugs857, the third upper contact plugs861, and the fourth upper contact plugs871. In an alternative embodiment, alignment between the first structure STa′ and the second structure STb′ may be checked by determining whether there is a bridged pair of the first capacitor electrode823and the second capacitor electrode881. The bridged pair of the first capacitor electrode823and the second capacitor electrode881may be measured by determining a current between each pair of the first contact pad803and the second contact pad853.

After the first structure STa′ and the second structure STb′ are coupled to each other, the second region A2bof the first substrate601and the second region A2b′ of the second substrate701may be removed by a cutting process.

Although not illustrated in detail, a manufacturing method consistent with embodiments described above with reference toFIGS. 15A to 15D, 16A to 16E, and 17may be used to form the semiconductor memory device shown inFIGS. 7A to 7C.

FIGS. 18A to 18C, 19A to 19C, and 20are cross-sectional diagrams illustrating a method of manufacturing a semiconductor memory device according to an embodiment. In diagrams described below, detailed explanation of the first structure and the second structure is the same as that described above with reference toFIG. 11and is therefore not repeated.

FIGS. 18A to 18Care cross-sectional diagrams illustrating processing a first substrate to have a first structure and a first align mark.

Referring toFIG. 18A, the first substrate600may include the same material as the first substrate101described above with reference toFIG. 1A. The first substrate600may include the first region A1band the second region A2b.

A first groove Ga′ may be formed in the second region A2bof the first substrate600. A first lower etch stop layer901, a first contact pad903, a first gap-fill insulating layer905, and a first lower contact plug907may be disposed in the first groove Ga′. The first groove Ga′, the first lower etch stop layer901, the first contact pad903, the first gap-fill insulating layer905, and the first lower contact plug907may be formed using the processes described above with reference toFIG. 15A.

Subsequently, the first insulating layer615may be formed on the first substrate600after a peripheral circuit including the transistors TR at the first region A1bof the first substrate600. The first insulating layer615may extend to cover the peripheral circuit including the transistors TR and the first lower contact plug907.

Subsequently, the first contact plugs617and a first upper contact plug911that pass through the first insulating layer615may be formed. The first contact plugs617may be coupled to the transistors TR. The first upper contact plug911may be coupled to the first lower contact plug907. The first contact plugs617and the first upper contact plug911may be formed at the same time and may be formed of the same conductive material.

Subsequently, the conductive pads619, the second contact plugs623, and a first align mark923that are embedded in the second insulating layer621may be formed. The first insulating layer615and the second insulating layer621may be included in the first insulating structure IS1′.

The second insulating layer621, the conductive pads619, and the second contact plugs623may be formed using the processes described above with reference toFIG. 15C. The first align mark923may pass through the second insulating layer621to be coupled to the first upper contact plug911.

The first align mark923and the second contact plugs623may be formed at the same time. The second contact plugs623and the first align mark923may include conductive materials.

Referring toFIG. 18B, the second insulating structure IS2′ may be formed on the first insulating structure IS1′. The second insulating structure IS2′ may include the third insulating layer627and the third insulating layer627may include an oxide layer. The second insulating structure IS2′ may extend to cover the second contact plugs623and the first align mark923.

Subsequently, the first conductive contact patterns633passing through the second insulating structure IS2′ may be formed. The first conductive contact patterns633may be formed using the processes described above with reference toFIG. 8C. The first conductive contact patterns633may include copper.

Subsequently, a part of the first substrate600may be etched from the rear surface of the first substrate600. Accordingly, the first contact pad903may be exposed and the first substrate601with the reduced thickness may remain as illustrated inFIG. 18C.

FIGS. 19A to 19Care cross-sectional diagrams illustrating processing a second substrate to have a second structure and a second align mark.

Referring toFIG. 19A, the second substrate700may include the same material as the second substrate151described above with reference toFIG. 1B. The second substrate700may include the first region A1b′ and the second region A2b′.

A second groove Gb′ may be formed at the second region A2b′ of the second substrate700. A second lower etch stop layer951, a second contact pad953, a second gap-fill insulating layer955, and a second lower contact plug957may be disposed in the second groove Gb′. The second lower etch stop layer951, the second contact pad953, the second gap-fill insulating layer955, and the second lower contact plug957may be formed using the processes described above with reference toFIG. 16A.

As described above with reference toFIG. 16B, the memory cell array CAR including the memory strings STR coupled to the source region703may be formed over the first region A1b′ of the second substrate700.

Subsequently, the supports723, the fourth insulating layer721, the fifth insulating layer725, the source contact structure SCT, the gate contact plugs727, and the drain contact plugs729described above with reference toFIG. 16Bmay be formed.

A second upper contact plug959passing through the fourth insulating layer721and the fifth insulating layer725disposed at the second region A2b′ of the second substrate700may be formed. The second upper contact plug959may extend to contact the second lower contact plug957. The second upper contact plug959may include a conductive material.

Subsequently, the gate pads735, the source pad737, and the bit lines BL may be formed on the fifth insulating layer725in the same manner as described above with reference toFIG. 16C.

Subsequently, the sixth insulating layer733covering the gate pads735, the source pad737, and the bit lines BL may be formed. The sixth insulating layer733may extend over the second region A2b′ of the second substrate700. Accordingly, the third insulating structure IS3′ including the fourth, fifth, and sixth insulating layers721,725, and733may be formed.

Subsequently, a second align mark971and the pad contact plugs741that pass through the sixth insulating layer733may be formed. The second align mark971and the pad contact plugs741may be formed by the same process and may include the same conductive material. The second align mark971may extend to contact the second upper contact plug959. The pad contact plugs741may extend to contact the gate pads735, the source pad737, and the bit lines BL.

Referring toFIG. 19B, the upper insulating layer745may be formed on the third insulating structure IS3′. Subsequently, the second conductive contact patterns743passing through the upper insulating layer745may be formed as described above with reference toFIG. 16D.

Subsequently, a part of the second substrate700may be etched from the rear surface of the second substrate700. Accordingly, the second contact pad953may be exposed and the second substrate701with the reduced thickness may remain as illustrated inFIG. 19C.

FIG. 20is a cross-sectional diagram illustrating aligning the first substrate601with the reduced thickness and the second substrate701with the reduced thickness with each other.

Referring toFIG. 20, the first substrate601with the reduced thickness and the second substrate701with the reduced thickness may be orientated such that the first conductive contact patterns633and the second conductive contact patterns743face each other. Capacitance between the first align mark923and the second align mark971may be measured.

The first align mark923and the second align mark971may be aligned to overlap each other. When capacitance between the first align mark923and the second align mark971is measured to have a reference value, such that it is determined that the first substrate601and the second substrate701are correctly aligned, the first conductive contact patterns633may be coupled to the second conductive contact patterns743. Accordingly, the first structure STa′ and the second structure STb′ coupled to each other via the first conductive contact patterns633and the second conductive contact patterns743may be formed as illustrated inFIG. 11. The first conductive contact patterns633and the second conductive contact patterns743may be treated by heat to couple the first structure STa′ and the second structure STb′.

Capacitance between the first align mark923and the second align mark971may be measured by applying electrical signals through the first contact pad903and the second contact pad953. The signal applied to the first contact pad903may be applied to the first align mark923via the first lower contact plug907and the first upper contact plug911. The signal applied to the second contact pad953may be applied to the second align mark971via the second lower contact plug957and the second upper contact plug959.

After the first structure STa′ and the second structure STb′ are coupled to each other, the second region A2bof the first substrate601and the second region A2b′ of the second substrate701may be removed by a cutting process.

Although not illustrated in detail, a manufacturing process consistent with embodiments described above with reference toFIGS. 18A to 18C, 19A to 19C, and 20may be used to form the semiconductor memory device shown inFIGS. 7A to 7C.

FIG. 21is a block diagram illustrating the configuration of a memory system1100according to an embodiment.

Referring toFIG. 21, the memory system1100may include a memory device1120and a memory controller1110.

The memory device1120may be a multi-chip package including a plurality of flash memory chips. The memory device1120may include one of the semiconductor memory devices illustrated inFIGS. 7A to 7C and 11.

The memory controller1110may be configured to control the memory device1120and include Static Random Access Memory (SRAM)1111, a CPU1112, a host interface1113, an error correction block1114, and a memory interface1115. The SRAM1111may serve as an operating memory of the CPU1112, the CPU1112may perform a control operation for data exchange of the memory controller1110, and the host interface1113may include a data exchange protocol of a host accessing the memory system1100. In addition, the error correction block1114may detect and correct errors included in the data read from the memory device1120, and the memory interface1115may perform interfacing with the memory device1120. In addition, the memory controller1110may further include Read Only Memory (ROM) for storing code data for interfacing with the host.

The memory system1100having the above-described configuration may be a Solid State Drive (SSD) or a memory card in which the memory device1120and the memory controller1110are combined. For example, when the memory system1100is an SSD, the memory controller1110may communicate with an external device (e.g., a host) through one of the interface protocols including a Universal Serial Bus (USB), a MultiMedia Card (MMC), Peripheral Component Interconnection-Express (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), a Small Computer Small Interface (SCSI), an Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

FIG. 22is a block diagram illustrating the configuration of a computing system1200according to an embodiment.

Referring toFIG. 22, the computing system1200may include a CPU1220, Random Access Memory (RAM)1230, a user interface1240, a modem1250, and a memory system1210that are electrically coupled to a system bus1260. In addition, when the computing system1200is a mobile device, a battery for supplying an operating voltage to the computing system1200may be further included, an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further included.

According to the present teachings, alignment accuracy between a first substrate and a second substrate may be improved by using a first align mark included with the first substrate and a second align mark included with the second substrate. Accordingly, the alignment stability between a memory cell array and a peripheral circuit may be increased when the memory cell array formed on one substrate and the peripheral circuit formed on another substrate are coupled.