Method of manufacturing interconnect

A method of manufacturing an interconnect. A first conductive layer is formed on the wafer. Portions of the first conductive layer are removed to form a wire in the interior region and to expose the surface of the wafer in the edge region, simultaneously. An insulating layer is formed on the wire and the wafer. An opening is formed to penetrate through the insulating layer and exposes the wire. A second conductive layer is formed on the insulating layer and fills the opening.

CROSS-REFERENCE TO RELATED APPLICATION
 This application claims the priority benefit of Taiwan application serial
 no. 88103923, filed Mar. 15, 1999, the full disclosure of which is
 incorporated herein by reference.
 BACKGROUND OF THE INVENTION
 1. Field of the Invention
 The present invention relates to a method of manufacturing a semiconductor
 device. More particularly, the present invention relates to a method of
 manufacturing an interconnect.
 2. Description of the Related Art
 Due to the increasingly high integration of ICs, chips simply cannot
 provide sufficient area for manufacturing interconnections. Therefore, in
 accord with the increased interconnect manufacturing requirements of
 miniaturized MOS transistors, it is increasingly necessary for IC
 manufacturing to adopt a design with more than two metal layers. In
 particular, a number of multi-function products, such as microprocessors,
 even require 4 or 5 metal layers to complete the internal connections
 thereof. Generally, an inter-metal dielectric (IMD) layer is used to
 electrically isolate two adjacent metal layers from each other.
 In order to perform an interconnection more easily and to transfer the
 pattern more precisely, it is important to have a wafer with an even
 topography. Since the probability of inaccuracy of the alignment system
 can be reduced by using a wafer with a relatively even topography, the
 fine pattern can be transferred more accurately.
 FIGS. 1A through 1B are schematic, cross-sectional views of the
 conventional pattern transfer process.
 As shown in FIG. 1A, a substrate having a conductive layer 120, wires 120a
 and 120b and a insulating layer 122 formed thereon is provided. A dotted
 line I--I divides a wafer (not shown) into two parts. One side of the
 dotted line I--I, denoted as region 116, is the interior region of the
 wafer, wherein the interior region has effective dies. The other side of
 the dotted line I--I, denoted as region 118, is the edge region of the
 wafer. The dies in the region 118 are incompletely formed, so that the
 region 118 is a region having ineffective dies. Since the distribution
 density of the conductive layer 120 is higher than that of the wires 120a
 and 120b, the ability of portions of the insulating layer 122 in the
 region 118 to resist the planarization step is higher than that in the
 region 118. Hence, portions of the insulating layer 122 in the region 116
 are thicker than the portions of the insulating layer 122 in the region
 116 after chemical-mechanical polishing (CMP). Because the region 118 is
 higher than the region 116, a sloped surface 124 of the insulating layer
 122 above the wire 120a is shown in the region 116 adjacent to the region
 118. In highly integrated ICs, the interconnection is more than one layer,
 so that the step height between the regions 118 and 116 is increasingly
 larger. Similarly, as shown in FIG. 1C, the scumming may also happens at a
 photoresist 134 formed on a conductive layer 132 subsequently formed over
 the insulating layer.
 As shown in FIG. 1B, a photoresist 128 is formed on the insulating layer
 122. Photolithography is performed to form openings 130a and 130b in the
 photoresist 128, respectively aligned with the wires 120a and 120b. The
 opening 130b may be formed to expose the underlying dielectric layer 122
 since the photoresist 128 is within the range of depth of focus (DOF). The
 DOF range is from the optimum focus BF to the maximum AF at both sides of
 the optimum focus BF. As the portion of the photoresist 128 over the wire
 120a is higher and beyond the DOF, so that an error occurs for the
 photolithography process. As a consequence, the opening 130a fails to
 expose by the dielectric layer 122. This is called scumming. Additionally,
 the defocusing happens since a conductive layer subsequently formed on the
 region 118 is relatively high and beyond the DOF. Therefore, the
 conductive layer caves.
 Generally, the step height of the photoresist caused by the profile of only
 one conductive layer is about 1000-3000 angstroms, which is an allowable
 error range. In other words, difference between the photoresist 128 in the
 region 118 and in the region 116 is about 1000-3000 angstroms. However,
 the step height increases as the number of the conductive layers
 increases. Therefore, the step height is more than 4000-5000 angstroms
 beyond the tolerable range. Hence, the scumming easily happened and it is
 difficult to accurately transfer a fine pattern from the photomask to the
 wafer.
 SUMMARY OF THE INVENTION
 The invention provides a method of manufacturing an interconnect. By using
 the invention, the problem of scumming can be overcome and the throughput
 can be greatly enhanced.
 To achieve these and other advantages and in accordance with the purpose of
 the invention, as embodied and broadly described herein, the invention
 provides a method of manufacturing an interconnect. A wafer having an edge
 region and an interior region is provided. A first conductive layer is
 formed on the wafer. Portions of the first conductive layer are removed to
 form a wire in the interior region and to expose the surface of the wafer
 in the edge region, simultaneously. An insulating layer is formed on the
 wire and the wafer. An opening is formed to penetrate through the
 insulating layer and exposes the wire. A second conductive layer is formed
 on the insulating layer and filling the opening. Since the insulating
 layer in the edge region of the wafer is lower than that in the interior
 region of the wafer and the sloped surface of the insulating layer is in
 an edge region, a fine pattern can be more accurately transferred from the
 photomask to the insulating layer. The problem of scumming can be also
 overcome. Moreover, the throughput can be greatly enhanced by using the
 invention.
 It is to be understood that both the foregoing general description and the
 following detailed description are exemplary, and are intended to provide
 further explanation of the invention as claimed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS
 Reference will now be made in detail to the present preferred embodiments
 of the invention, examples of which are illustrated in the accompanying
 drawings. Wherever possible, the same reference numbers are used in the
 drawings and the description to refer to the same or like parts.
 FIGS. 2A through 2J are schematic, cross-sectional views of the process for
 manufacturing an interconnect in a preferred embodiment according to the
 invention.
 As shown in FIG. 2A, a substrate 200 having a conductive layer 212 is
 provided. The material of the conductive layer 212 can be metal or
 polysilicon and the thickness of the conductive layer 212 is about 5000
 angstroms, for example. A photoresist 214 is formed on the conductive
 layer 212. The photoresist layer 214 can be a positive photoresist, for
 example. A dotted line II--II divides a wafer (not shown) into two parts.
 One side of the dotted line II--II denoted as region 216, is the interior
 region of the wafer, wherein the interior region has effective dies. The
 other side of the dotted line II--II, denoted as region 218, is the edge
 region of the wafer. The dies in the region 218 are incomplete and the
 region 218 is a region having ineffective dies.
 As shown in FIG. 2B, a first exposure step is performed to expose a portion
 of the photoresist 214 in the region 216 by a light 217a in a stepper with
 a photomask 215. The pattern is replicated from the photomask 215 into the
 photoresist 214 through the first exposure step.
 As shown in FIG. 2C, a second exposure step is performed to expose the
 photoresist 214 in the region 218 by a light 217b in a stepper. In this
 example, the region 218 can be exposed without using a mask or by using a
 blank mask. The second exposure step and the first exposure step can be
 performed in the different steppers, for example.
 As shown in FIG. 2D, a development step is performed on the photoresist 214
 and the pattern on the photomask 215 is replicated into the photoresist
 214 in the region 216. Therefore, portions of the photoresist 214 in the
 regions 216 and 218 are removed to expose portions of the conductive layer
 212 in the regions 216 and 218 and the patterned photoresist 214 is
 denoted as photoresist 214a.
 As shown in FIG. 2E, portions of the conductive layer 212 in the region 216
 are removed to form wires 220a and 220b by using the photoresist 214a as
 an etching mask until portions of the substrate 200 are exposed by the
 wires 220a and 220b. Simultaneously, the portion of the conductive layer
 212 in the region 218 is removed to expose a portion of the substrate 200
 in the region 218. The photoresist 214 is removed to expose the wires 220a
 and 220b.
 As shown in FIG. 2F, an insulating layer 224 with low permittivity is
 formed over the substrate 200. The insulating layer 224 can be formed by
 chemical vapor deposition, for example. Preferably, the method of forming
 the insulating layer 224 can be high density plasma chemical vapor
 deposition (HDPCVD). Since the insulating layer 224 has low permittivity,
 it can provide a good isolation effect between wires 220a and 220b.
 Because the wires 220a and 220b are slightly higher than the surface of
 the substrate 200, the surface of the insulating layer 224 is not smooth.
 An insulating layer 226 is formed on the insulating layer 224. The
 insulating layer 226 can be formed by chemical vapor deposition, for
 example. Preferably, the method of forming the insulating layer 226 can be
 plasma enhancement chemical vapor deposition (PECVD). The insulating
 layers 224 and 226 together form an insulating layer 222. Since the
 portion of the insulating layer 224 above the wires 220a and 220b are
 relatively thick, the topography of the insulating layer 224 is rough.
 Therefore, the topography of the insulating layer 226 formed on the
 insulating layer 224 is uneven.
 As shown in FIG. 20, a planarization step is performed to planarize the
 insulating layer 226. The planarization step can be CMP. Since there is no
 conductive layer on a portion of the substrate 200 in the region 218 and
 there are wires 220a and 220b in the region 216, the structure of the
 region 216 is denser than that of the region 218. Hence, the resistance
 ability to the planarization step of the region 216 is higher than that of
 the region 218. Therefore, a slope surface 226a of the insulating layer
 222 is shown in the regions 218 adjacent to the region 216 after the
 planarization step. In the other words, the portion of the insulating
 layer 226 above the wires 220a and 220b is very even.
 As shown in FIG. 2H, a patterned photoresist 228 having openings 230a and
 230b is formed on the insulating layer 222. The openings 230a and 230b are
 respectively aligned with the wires 220a and 220b. Because of the very
 even insulating layer 226 above the wires 220a and 220b, a portion of the
 photoresist 228 above the wires 220a and 220b is in the DOF range and the
 scumming does not happen. Hence, the openings 230a and 230b are vertical
 to the insulating layer 222 and expose a portion of the insulating layer
 222 above the wires 220a and 220b.
 As shown in FIG. 2I, a portion of the insulating layer 222 is removed to
 form openings 232a and 232b by using the patterned photoresist 228 as an
 etching mask. The openings 232a and 232b penetrate through the insulating
 layer 222 and respectively expose the wires 220a and 220b. The openings
 232a and 232b can be via holes or node contact holes, for example. The
 patterned photoresist 228 is removed.
 As shown in FIG. 2J, a conductive layer 234 is formed on the insulating
 layer 222 and fills the openings 232a and 232b.
 In the invention, when other interconnection layers are formed on the
 conductive layer 234, the process of forming the interconnection layers is
 the same as the process shown from FIGS. 2A through 2J. In the other
 words, a portion of the conductive layers above the conductive layer 234
 in the region 218 is removed, which is the same as the formation of the
 wires 220a and 220b. In this example, the method of removing a portion of
 the conductive layer in the region 218 can be used at the alternate
 conductive layers.
 In the invention, since the insulating layer in the edge region of the
 wafer is lower than that in the interior region of the wafer and the slope
 surface of the insulating layer and the photoresist is in edge region, the
 insulating layer in the edge region is in the DOF range. Therefore, a fine
 pattern can be transferred from the photomask to the insulating layer more
 accurately and the problem of scumming is overcome. Moreover, the loss
 ratio of effective dies in the interior region of the wafer by using the
 conventional method is about 15 percent. However, by using the invention,
 the throughput can be greatly enhanced by about 20 percent.
 It will be apparent to those skilled in the art that various modifications
 and variations can be made to the structure of the present invention
 without departing from the scope or spirit of the invention. In view of
 the foregoing, it is intended that the present invention cover
 modifications and variations of this invention provided they fall within
 the scope of the following claims and their equivalents.