Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same

The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same. In one illustrative embodiment, an integrated circuit is provided that comprises a plurality of voltage supply structures formed above a substrate, the plurality of voltage supply structures being at differing voltage levels, and a guard band comprised of at least one doped region formed in the substrate under each of the plurality of voltage supply regions, each of the guard bands being comprised of a plurality of fingers extending from each end of the guard bands.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This present invention is generally directed to the field of integrated circuits and semiconductor processing, and, more particularly, to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same.

2. Description of the Related Art

There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.

Complementary metal oxide (CMOS) technology is widely used in various integrated circuit products, such as logic circuits, memory circuits, application-specific integrated circuits, etc., due to various performance characteristics associated with CMOS devices, e.g., lower power consumption. In general, CMOS integrated circuits are comprised of P-channel (PMOS) and N-channel (NMOS) transistors which are formed on the same semi-conducting substrate. As a result of such structures, parasitic bipolar transistors (of both the PNP type and the NPN type) are formed in the CMOS integrated circuit. For example, a PNP parasitic transistor is formed where an N-type substrate, which serves as its base, is formed within a P-well, which serves as its collector. The source or drain of a PMOS transistor serves as the emitter of the parasitic PNP transistor. At the same time, an NPN parasitic transistor is possible where the P-well, which serves as the base, is formed within the N-type substrate, which serves as the collector. The source or drain of the NMOS transistor serves as the emitter for the NPN parasitic transistor.

When such a CMOS structure forms an output circuit of an integrated circuit device, a ground voltage (VSS) and a power supply voltage (VCC) are typically supplied to the sources of the NMOS and PMOS transistors, respectively. The drains of the NMOS and PMOS transistors are used for an output terminal of the output circuit. If the output terminal accidentally receives a triggering voltage which is generally higher than the power supply voltage (VCC) or lower than the ground voltage (VSS), the parasitic transistors begin to conduct since the junctions between the base and emitter are forward biased. Once both parasitic transistors become conducting, a current continues to flow in a direction from the power supply voltage (VCC) to the ground voltage (VSS) without any further triggering voltage to the output terminal. This situation is known in the industry as “latch-up.” When latch-up occurs, the CMOS circuits are often permanently damaged by the resulting high currents.

In modern CMOS integrated circuits, the most likely source for the undesirable triggering voltage that may cause latch-up are the pad drivers, where large voltage transients and large currents are present.FIG. 1Ais a schematic depiction of various I/O (input/output) voltage supply regions that may be found on a modern integrated circuit10employing CMOS technology. As shown therein, the integrated circuit10is generally comprised of a core region12wherein the various circuits, comprised of PMOS and NMOS transistors, may be formed. In general, there are four types of power rings depicted in FIG.1A—VDD, GND, VDDIO and GNDIO. Both VDD (14) and GND (16) are connected to the core logic power supply. VDDIO and GNDIO are the supply voltages to the I/O buffers, which drive heavy loads. In the particular embodiment depicted inFIG. 1A, three cuts18A,18B,18C are made in the VDDIO and GNDIO rings to thereby define three separate power supply structures or power domains20A (VDDIO1),20B (VDDIO2) and20C (VDDIO3). Separation of the power supply structures enables chip designers to isolate the various power domains and/or to use different voltage levels for different input/output buffers. As will be understood by those skilled in the art, the depiction of three voltage domains inFIG. 1Ais by way of example only, as there may be more or fewer voltage domains on the integrated circuit device, and the magnitudes of the voltages of the various power domains may vary depending upon the particular integrated circuit.

Generally, in an effort to avoid or reduce the possibility of latch-up, a doped region or guard band13is formed in the substrate17under each of the various power supply structures, e.g., VDDIO1, VDDIO2and VDDIO3.FIGS. 1B and 1Care, respectively, a plan view and a cross-sectional view of an illustrative power supply structure10, e.g., VDDIO3, and a simplified version of such a doped region or guard band13. The illustrative guard band13is depicted inFIGS. 1B and 1Cis a relatively deep N-well doped region that is formed by implanting the appropriate dopant atoms into the substrate17. A contact15is provided to the guard band13so that a voltage may be applied to the guard band13.FIG. 1Dis a cross-sectional view of a guard band13comprised of multiple doped regions formed in the substrate17. More specifically, in the illustrative example depicted inFIG. 1D, the guard band13is comprised of, in one embodiment, an N+active region13A, an N-well13B and a deep buried N-well13C. A layer of insulating material10A is positioned between the voltage supply structure10and the substrate17. Unfortunately, using such prior art structures, the areas defined by each of the cuts18A–C in the voltage supply structures still define possible paths for triggering currents and voltages that may enter the core region12and cause the latch-up phenomenon to occur.

The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.

SUMMARY OF THE INVENTION

The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same. In one illustrative embodiment, an integrated circuit is provided that comprises a plurality of voltage supply structures formed above a substrate, the plurality of voltage supply structures being at differing voltage levels, and a guard band comprised of at least one doped region formed in the substrate under each of the plurality of voltage supply regions, each of the guard bands being comprised of a plurality of fingers extending from each end of the guard bands.

In another illustrative embodiment, an integrated circuit is provided that comprises a plurality of voltage supply structures formed above a substrate, the plurality of voltage supply structures being at differing voltage levels, and a guard band comprised of at least one doped region formed in the substrate under each of the voltage supply regions, each of the guard bands being comprised of a plurality of fingers extending from each end of the guard bands, wherein the plurality of fingers on a first of the guard bands nests with the plurality of fingers on a second guard band positioned proximate the first guard band.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2is a plan view of a power grid layout for an illustrative integrated circuit11in accordance with one embodiment of the present invention. In general, the circuits that comprise the integrated circuit11are formed in the core region12of the integrated circuit11. Various power domains or voltage supply structures19A–19E are positioned around the periphery of the chip15. The voltage levels V1–V5may all be at different levels. The power supply structures19A–19E are typically comprised of one or more layers of metal, e.g., aluminum, formed above the substrate. A guard band25comprised of at least one doped region is formed in the substrate and positioned, at least partially, under each of the power supply structures19A–19E. Each of the guard bands25is comprised of a plurality of fingers on each end of the guard band25. The fingers are adapted to nest or mesh with corresponding fingers of a guard band25positioned under an adjacent voltage supply structure19. The meshed or interdigitized fingers of the guard bands25positioned under adjacent power supply structures, e.g., structures19A and19B, serve to reduce or eliminate a path for undesirable triggering voltages and/or currents to enter the core region12of the integrated circuit. Compare the region12A depicted inFIG. 2, comprised of the meshed fingers of the guard bands25, with the openings or cuts18A–C depicted in the prior art structure ofFIG. 1A. In effect, the intermeshed fingers of the guard bands25provide a tortuous path that unwanted currents must pass before they can enter the core region12of the integrated circuit11.

Also depicted inFIG. 2are isolated regions21,23formed on the periphery of the chip15. In some cases, such isolated regions21,23may contain the necessary circuitry to drive various input/output buffers. Thus, in some cases, the guard bands25of the present invention may be provided on such isolated regions21,23. In such cases, the guard bands25around the isolated regions21,23may mesh or nest with the guard bands25of adjacent power supply regions.

FIG. 3is a plan view of a portion of a first guard band25A and a portion of a second guard band25B. The first guard band25A is positioned under a first voltage supply structure19A (V1), and the second guard band25B is positioned under a second voltage supply structure19B (V2), wherein V1and V2may be of different magnitudes and/or polarity. As will be understood by those skilled in the art after a complete reading of the present application, only portions of the guard bands25A,25B are depicted. That is, the guard band25A will normally be positioned under the entirety of the voltage supply structure19A (V1), although that is not depicted inFIG. 3. As described more fully below, the guard bands25A,25B are comprised of one or more doped regions that are formed in a semiconducting substrate50by performing known ion implantation processes.

FIGS. 4A–4Bare cross-sectional side views taken along the lines indicated inFIG. 3. As shown inFIG. 4A, a single doped region25A is formed in the substrate50under the first voltage supply structure19A. A contact39A is provided to the doped region25A such that a voltage may be applied to the doped region. A layer of insulating material, e.g., silicon dioxide, BPSG, etc., is positioned between the substrate50and the power supply structure19A. The doped region25A has a depth45A and a width47A that may vary depending upon the application. The size of the doped region25A relative to the size of the voltage supply structure19A may also vary depending upon the application. Typically, the width47A of the doped region25A will be wider than the width49A of the voltage supply structure19A. In one embodiment, the doped region25A, as implanted, will extend by a distance51of approximately 0.2–2.0 μm beyond the voltage supply structure19A. That is, in some embodiments, the doped region25A is sized and configured such that the surface area defined by the doped region25A is greater than the surface area defined by the voltage supply structure19A, and the voltage support structure19A is positioned above the doped region25A within the area defined by the doped region25A.

The type and species of dopant material implanted into the region25A and the dopant concentration level for such region may vary depending upon the particular application. In one illustrative embodiment, the width47A of the doped region25A may vary from approximately 0.4–8.0 μm, the depth45A of the doped region25A may vary from approximately 0.05–5 μm and the distance51may be approximately 0.2–4.0 μm. Moreover, the doped region25A may be implanted with an N-type dopant material, such as arsenic. This results in the doped region25A having a dopant concentration level of approximately 5e19–2e20ions/cm3.

FIG. 4Bis a cross-sectional view of the doped region25B positioned under the voltage supply structure19B. The doped region25B also has a depth45B and a length47B. The doped region25B may extend beyond the width49B of the voltage supply19B by a distance51B. The doped regions25A and25B may be symmetrical in nature in that they both may have the same or similar physical dimensions, e.g., the width47A,47B and depth45A,45B may be approximately the same. However, the present invention may be employed in situations where the physical dimensions and positioning of the doped regions25A and25B may be different from one another. Thus, the particular details depicted in the attached drawings should not be considered a limitation of the present invention unless such limitations are clearly set forth in the appended claims.

As shown inFIG. 3, each of the guard bands25A,25B has a plurality of fingers27,29, respectively, formed on an end of the guard bands25A,25B. The physical dimensions of the doped regions that define the guard bands25A,25B and the fingers27,29, and the spacing between the fingers27,29may vary. As shown inFIG. 3, the fingers27,29have a length34that ranges from approximately 5–30 μm, a width36that ranges from approximately 3–20 μm, an end spacing38that ranges from approximately 5–10 μm and a lateral spacing40that ranges from approximately 5–10 μm.

As depicted inFIG. 3, the fingers27of the first guard band25A mesh or nest with the fingers29of the second guard band25B. More particularly, the fingers29of the second guard band25B are positioned within the recesses35formed between adjacent fingers27of the first guard band25A. Similarly, the fingers27of the first guard band25A are positioned within recesses37formed between adjacent fingers29of the second guard band25B. Although the meshed or nested fingers27,29inFIG. 3are depicted in a symmetrical arrangement, after a complete reading of the present application those skilled in the art will understand that such symmetry is not required in all embodiments of the present invention. Moreover, the fingers27,29need not have uniform physical characteristics, i.e., the number of fingers, the width36, length34and/or spacing38,40may be varied on each of the guard bands25A,25B as desired. Thus, the physical dimensions recited herein for the fingers27,29, the spacing between and positioning of such fingers27,29should not be considered a limitation of the present invention unless such limitations are expressly recited in the appended claims.

FIG. 4Cis a cross-sectional view taken along the line4C—4C inFIG. 3. As shown therein, in one illustrative embodiment, the fingers27,29are comprised of doped regions formed in the semiconducting substrate50. In one embodiment, the fingers27,29have a depth44that ranges from approximately 0.05–5.0 μm. Although the fingers27,29exhibit a rectangular cross-sectional configuration inFIG. 4C, the cross-sectional configuration of the fingers27,29may vary.

In the embodiments described previously, the guard bands25are comprised of single doped regions (25A,25B) formed in the substrate50. The fingers27,29are also comprised of single doped regions formed in the substrate. However, in further embodiments of the present invention, the guard bards25positioned under the voltage supply structures19may be comprised of multiple doped regions. These intermeshing fingers27,29may also exhibit this multiple doped region configuration.

FIG. 5is a cross-sectional view of an illustrative guard band25comprised of multiple doped regions52A,52B and52C formed in the substrate50under the illustrative voltage supply structure19that is separated from the substrate50by the insulating layer42. As will be recognized by those skilled in the art after a complete reading of the present application, the size and doping levels of the illustrative doped regions52A,52B and52C may vary depending upon the particular application. The number of doped regions and their configuration may also vary.

For example, in one illustrative embodiment, the doped region52A is an N+active region having a dopant concentration level of approximately 5e19–2e20ions/cm3, the doped region52B is an N-well region having a dopant concentration level of approximately 2e16–8e17ions/cm3, and the doped region52C is a deep (buried) N-well having a dopant concentration of approximately 2e16–8e17ions/cm3. The doped regions52A,52B,52C may vary in size and configuration. In one illustrative embodiment, the doped region52A has a depth64of approximately 0.05–5.0 μm and a width65of approximately 0.3–8.0 μm. The doped region52B has a depth62of approximately 1–5 μm and a width63of approximately 1–10 μm. The doped region52C may have a depth60of approximately 0.5–3.0 μm and a width61of approximately 0.8–10.0 μm. Of course, these representative dimensions are provided by way of example only.

In the situation where the guard bands25are comprised of multiple doped regions, like the doped regions52A,52B and52C depicted inFIG. 5, the intermeshing fingers27,29of adjacent guard bands25A,25B may also exhibit such a multiple doped region configuration.FIG. 6is a cross-sectional view depicting such an illustrative configuration. As shown therein, the fingers27,29are comprised of corresponding doped regions52A,52B and52C similar to that depicted inFIG. 5. However, the physical dimensions of the doped regions that comprise these fingers27,29would be scaled down to fit within the overall width36and depth44of the fingers27,29. However, it should be understood that the number of doped regions that comprise the fingers27,29need not necessarily correspond to the number of doped regions used to form the bulk of doped regions positioned under the voltage supplies19. For example, the main portion of the guard bands25may be comprised of multiple doped regions52A,52B and52C while the fingers27,29are only comprised of a single doped region, e.g., an extension of the doped region52B only.

In general, the guard bands25that are positioned under the power domain structures are formed by performing known ion implantation processes using appropriate masking layers. The implant steps used to form the guard bands25may be performed at any time that is convenient during the process flow used to form the integrated circuit product. Typically, the guard bands25may be implanted with a dopant material, such as arsenic or phosphorous, and the resulting guard bands25may have a dopant concentration level of approximately 2e19–4e20ions/cm3. The implant dose and energy level used during the ion implant process may vary depending upon the type of dopant material implanted and the desired depth44of the guard bands25.

The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of making same. In one illustrative embodiment, an integrated circuit is provided that comprises a plurality of voltage supply structures19formed above the substrate50, the plurality of voltage supply structures19being at differing voltage levels, and a guard band25comprised of at least one doped region formed in the substrate50under each of the plurality of voltage supply structures19, each of the guard bands25being comprised of a plurality of fingers extending from each end of the guard bands25. In further embodiments, the guard band25is comprised of a plurality of doped regions52A,52B and52C.

In another illustrative embodiment, an integrated circuit is provided that comprises a plurality of voltage supply structures19formed above the substrate50, the plurality of voltage supply structures19being at differing voltage levels, and a guard band25comprised of at least one doped region formed in the substrate50under each of the voltage supply structures19, each of the guard bands25being comprised of a plurality of fingers extending from each end of the guard bands, wherein the plurality of fingers on a first of the guard bands nests with the plurality of fingers on a second guard band positioned proximate the first guard band. In further embodiments, the guard bands may also be comprised of a plurality of doped regions formed in the substrate.

The present invention is also directed to a novel method. In one illustrative embodiment, the method comprises forming a masking layer above a substrate wherein the masking layer defines an exposed region of the substrate in which a guard band having a plurality of fingers on each end of the guard band will be formed. The method further comprises performing at least one ion implantation process to implant dopant atoms into said substrate to thereby define the guard band in the substrate.

Through use of the present invention, the occurrences of latch-up in integrated circuits may be prevented or the number of such occurrences may be reduced. As a result, device reliability and performance may be improved. Similarly, modern devices incorporating such features may function more reliably and for a longer duration as compared to such devices made using integrated circuits comprised of the prior art structures described in the background section of the application.