Balanced debounce circuit with noise filter for digital system

A circuit and method for debouncing an electrical signal are disclosed. A representative embodiment of the present invention may be set to remove (i.e., filter) noise or glitches in the low and high portions of an input signal, where the width of the noise or glitches while in the high or low state may be set using a programming interface. The filtering is done in a manner that results in a clean, debounced output signal having a low portion approximately equal to the low portion of the input signal, and a high portion approximately equal to the high portion of the input signal. Noise or glitches of less than programmable high or low glitch widths are filtered from the input signal and do not appear in the output signal.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

BACKGROUND OF THE INVENTION

In general, electronic devices having mechanical switches as input signals must cope with the erratic signal behavior that typically occurs when the switch is activated and deactivated. For example, a keypad button for a cellular handset typically generates a bouncing signal while the keypad button is being pressed and released. The length of the period during which the bouncing occurs varies depending upon the switch or button and may, for example, range from several microseconds, to fifty milliseconds or more. For instance, the keypad button used in a cellular phone typically generates a signal that bounces for approximately 20 milliseconds. In most electronic devices, the bouncing or “glitching” of the keypad button signal must be filtered, because the keypad button or switch input is used to trigger digital logic such as, for example, a processor interrupt. If the bouncing or “glitching” is not removed, the processor may operate erratically, producing unexpected results. The process of removing or filtering the bounces or “glitches” from the button signal is typically referred to as “debouncing”. By debouncing the signal from a switch or button, the electronic device is able to base its operation upon a clean version of the user input.

Many different methods are used to debounce input signals from mechanical switches. Most debouncing is done using an analog circuit such as, for example, a capacitor, and a gate with a Schmitt input. This type of analog method has drawbacks including, for example, the need for additional discrete components (e.g., a capacitor), a lack of flexibility, and the added cost of the components. Electronic devices having a processor sometimes use software algorithms to filter inputs with bouncing signals. Such debounce software may use a significant amount of the processor capacity, may degrade system performance, and may cause the failure of the entire software system of the electronic device. Digital debounce filters are sometimes used, but are typically inflexible regarding debounce parameters, may only filter signal bounce in one direction, are susceptible to noise, and are difficult to test using design simulation tools.

BRIEF SUMMARY OF THE INVENTION

A circuit and method for debouncing an input signal having at least a first state and a second state, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

These and other advantages, aspects, and novel features of the present invention, as well as details of illustrated embodiments, thereof, will be more fully understood from the following description and drawings.

DETAILED DESCRIPTION OF THE INVENTION

Aspects of the present invention are related to the processing of real-world signals for use in electronic circuitry. More specifically, aspects of the present relate to a method of removing bounce or glitches from the signals of mechanical switches, to produce a clean or debounced version of the input signal. Although reference is made herein to the debouncing of signals produced by mechanical switches, the present invention is not limited in this regard. Various embodiments of the present invention may have application in the debouncing of signals, or the filtering of noise, from other sources as well.

FIG. 1shows a block diagram of an electronic device100having a mechanical switch110generating a signal120that may exhibit bounces or glitches, in which a representative embodiment of the present invention may be practiced. The switch110illustrated inFIG. 1may comprise, for example, any type of switch using, for example, mechanical contacts, optical interrupter, or other form of electrical switch producing a signal120that bounces or glitches during activation or deactivation of the switch. The system140may comprise, for example, an electrical circuit for sensing the active or inactive state of the signal120of the switch110. The system140may react to the states and/or transitions of the signal120of the switch110, and may produce an output signal160that may represent, for example, one or more of an audible output, a visual output, a signal controlling a mechanical actuator, motor, solenoid, etc, and a data signal.

FIG. 2Ais a block diagram of an exemplary debounce circuit200for processing an input signal DI220to produce an output signal260, in accordance with a representative embodiment of the present invention. As illustrated inFIG. 2A, the debounce circuit200comprises a high phase glitch width register242, a high phase counter244, a low phase glitch width register246, and a low phase counter248. In the debounce circuit200illustrated inFIG. 2A, the high phase counter244comprises an up-counter, while the low phase counter248comprises a down-counter. The high phase glitch width register242and the low phase glitch width register246receive the value of the high phase glitch width and low phase glitch width, respectively, via a programming interface228. The debounce circuit200in the illustration ofFIG. 2Aaccepts three input signals in addition to the raw, unmodified input signal DI220to be processed, and the programming interface228. The EN signal226acts to enable the operation of the debounce circuit200. When the EN signal226is at a low logic level (inactive), the multiplexer259is configured to route the input signal DI220directly to the output of the debounce circuit200, the output signal DO260. In addition, when signal EN226is in the inactive state (low), the high phase counter244, the low phase counter248, the high phase comparator245, and the low phase comparator249are stopped from activity to save power. The RSTN signal222ofFIG. 2Aacts as an active-low reset signal to the high phase counter244, the low phase counter248, flip-flop FF1253, and flip-flop FF2254. In one representative embodiment of the present invention, the reset of the high phase counter244sets the value of the high phase counter244to “all-zeros”, while resetting the low phase counter248sets the value of the low phase counter248to “all ones”. Signal CLK224acts as a clock input to the high phase counter244, the low phase counter248, flip-flop FF1253, and flip-flop FF2254. In the illustration ofFIG. 2A, the output A243represents the current value of the high phase counter244, and the output C247represents the current value of the low phase counter248.

In the debounce circuit200illustrated inFIG. 2A, when signal RSTN222is at a high logic level (inactive), the high logic level of the input signal DI220permits the high phase counter244to begin counting upward from the “all zeros” state. At the same time, the high logic level of the input signal DI220holds the low phase counter248in a reset condition (i.e., all ones). A low logic level at the input signal DI220permits the low phase counter248to begin counting downward from the “all ones” state, and simultaneously holds the high phase counter244in a reset condition (i.e., all zeros). The output A243of the high phase counter244is compared by the high phase comparator245with the high phase glitch width value in the high phase glitch width register242. In a similar fashion, the output C247of the low phase counter248is compared by low phase comparator249with the low phase glitch width value in the low phase glitch width register246. As described above, the values in the high phase glitch width register242and the low phase glitch width register246may be loaded via the programming interface228.

As shown in the illustration ofFIG. 2A, the high phase counter244increments at every rising edge of the clock signal CLK224, when the raw (i.e., not debounced) input signal DI220is at a high logic level, signal EN226is active (high), and signal RSTN is inactive (high). When the value in the high phase counter244matches the value in the high phase glitch width register242, the output B250of the high phase comparator245is set to an active high logic level. That is, when the value243at the “B”0input of high phase comparator245is equal to the value240at the “A” input, the output B250of the high phase comparator245is set to a high logic level. Additionally, the signal B250stops the high phase counter244from incrementing, and the high phase counter244remains at the value in the high phase glitch width register242until a reset of the high phase counter244is caused by the input signal DI220, or by the reset signal RSTN222. The high logic level of output B250is latched into the FF1253upon the next rising edge of the clock signal CLK224, and triggers the output H258of the flip-flop FF3257to a high logic level at next second rising edge of the clock signal CLK224that is passed to debounced output DO260. In a representative embodiment of the present invention, positive glitches in the input signal DI220that are smaller in duration than the value in the high phase glitch width register242will not trigger the output H258of the flip-flop FF3257to a high logic level. In addition, the return of the input signal DI220to a low logic level will reset the high phase counter244and force signal B250to logic low level (inactive). The low logic level of signal B250is latched into the FF1253after one clock cycle. This transition of signal E255to a logic low level does not trigger the state of output H258of FF3257to a low logic level, because FF3257cannot be triggered by the high to low transition of signal E255. By operating as described above, the debounce circuit200removes from the output DO260any positive glitches of the input signal DI220having a duration shorter than the value stored in the high phase glitch width register242.

The debounce circuit200illustrated inFIG. 2Aoperates in a similar fashion when operating upon an input signal DI220that is active when at a low logic level. While the input signal DI220is at a high logic level, the low phase counter248is held in reset (i.e., “all ones”). When the input signal DI220is at a low logic level, the low phase counter248is enabled to decrement at every rising edge of the clock signal CLK224when signal EN226is active (high) and signal RSTN is inactive (high). When the low phase counter248matches the value in the low phase glitch width register246, the output D251of the low phase comparator249is set to an active low logic level. That is, when the value241at the “B” input of the low phase comparator249is equal to the value C247at the “A” input, the output D251of the low phase comparator249is set to a low logic level. That value is latched into the flip-flop FF2254at the next rising edge of the clock signal CLK224. Additionally, the signal B251stops the low phase counter248from decrementing, and the low phase counter248remains at the value in the low phase glitch width register246until a reset of the low phase counter248is caused by the input signal DI220, or by the reset signal RSTN222. The output F256of the flip-flop FF2254then changes to a low logic level, and the flip-flop FF3257is reset, forcing the output H258of the flip-flop FF3257to a low logic level that is passed to debounced output DO260. If the duration of a low logic level portion (i.e., a “negative glitch”) of the input signal DI220is shorter than the value in the low phase glitch width register246, the value of low phase counter248will never match the value of the low phase glitch width register246, and the output D of the comparator249will not go to a low logic level. Therefore, the flip-flop FF2254will not be reset, and will not reset the state of the flip-flop FF3257. The output H258of the flip-flop FF3257will remain at a high logic level, and that value will be passed to the output signal DO260by multiplexer259. Any change of input signal DI220to a high logic level will reset the low phase counter248to the “all ones” condition, forcing signal B251to a high logic level. The high logic level of signal B251is latched into flip-flop FF2254after one clock cycle. The high logic level of the output signal F256of FF2254does not trigger the reset of flip-flop FF3257because the high logic level of signal F256cannot reset flip-flop FF3257. In this manner, any negative glitches (i.e., low logic level portion) in the input signal DI220having a duration of less than the value of the low phase glitch width register246will not be passed to the output DO260.

Although the above discussion of the circuit ofFIG. 2Adescribes the high phase counter244as an up-counter and the low phase counter248as a down-counter, this does not necessarily represent a limitation of the present invention. For example, either or both of the high phase counter244and low phase counter248may be up-counters or down-counters, without departing from the spirit and scope of the present invention. In another representative embodiment of the present invention, both the low phase counter248and the high phase counter244may be up-counters, and the low phase counter248and the high phase counter244may be reset to the “all-zeros” condition, during that portion of the input signal DI220that is in the low logic level and a high logic level, respectively. In such an embodiment, the inputs to the low phase comparator249may be swapped, and the high phase counter244and low phase counter248may count until their values equal the high phase glitch width register242and the low phase glitch width register246, respectively.

The selection of the frequency of the clock signal CLK224depends upon the bounce or glitch characteristics of the input signal DI220, and the width in bits of the high phase counter244and the low phase counter248. For example, using a clock signal CLK224of 32.768 KHz, and a high phase counter244and low phase counter248having 10 bits, the debounce circuit illustrated inFIG. 2Ais able to filter (i.e., remove) noise (i.e., glitches) up to 210/32768=31.25 milliseconds (ms.) in length from the input signal DI220. In an embodiment of the present invention, the frequency of the clock signal CLK224and the number of bits of both the high and low phase counters244,248and the high and low phase glitch width registers242,246may, for example, be increased to filter out (i.e., debounce) noise and glitches of greater width.

FIG. 2Bis a block diagram of another exemplary debounce circuit200for processing an input signal DI220to produce an output signal260, in accordance with a representative embodiment of the present invention. As illustrated inFIG. 2B, the debounce circuit200comprises a high phase glitch width register242, a high phase counter244, a low phase glitch width register246, and a low phase counter248. Although in the debounce circuit200illustrated inFIG. 2B, both the high phase counter244and the low phase counter248comprise up-counters, this does not represent a limitation of the present invention. The high phase glitch width register242and the low phase glitch width register246receive the value of the high phase glitch width and low phase glitch width, respectively, via the programming interface228. The debounce circuit200in the illustration ofFIG. 2Baccepts three input signals in addition to the raw, unmodified input signal DI220to be processed, and the host interface228. The EN signal226acts to enable the operation of the debounce circuit200. When the EN signal226is at a low logic level, the multiplexer259is configured to route the input signal DI220directly to the output of the debounce circuit200, the output signal DO260. In addition, when signal EN226is at a low logic level (inactive), the high phase counter244, the low phase counter248, the high phase comparator245, and the low phase comparator249are stopped from activity to save power. The RSTN signal222ofFIG. 2Bacts as an active-low reset signal to the high phase counter244, the low phase counter248, flip-flop FF1253, and flip-flop FF2254. In the representative embodiment of the present invention shown in Fib.2B, the reset of the high phase counter244sets the value of the high phase counter244to “all-zeros”, and resetting the low phase counter248sets the value of the low phase counter248to “all-zeros”. Signal CLK224acts as a clock input to the high phase counter244, the low phase counter248, flip-flop FF1253, and flip-flop FF2254. In the illustration ofFIG. 2B, the output A243represents the current value of the high phase counter244, and the output C247represents the current value of the low phase counter248.

In the debounce circuit200illustrated inFIG. 2B, when signal RSTN222is at a high logic level (inactive), the high logic level of the input signal DI220permits the high phase counter244to begin counting upward from the “all-zeros” state. At the same time, the high logic level of the input signal DI220holds the low phase counter248in a reset condition (i.e., all-zeroes). A low logic level at the input signal DI220permits the low phase counter248to begin counting upward from the “all-zeros” state, and simultaneously holds the high phase counter244in a reset condition (i.e., all-zeros). The output A243of the high phase counter244is compared by the high phase comparator245with the high phase glitch width value in the high phase glitch width register242. In a similar fashion, the output C247of the low phase counter248is compared by low phase comparator249with the low phase glitch width value in the low phase glitch width register246. As described above, the values in the high phase glitch width register242and the low phase glitch width register246may be loaded via the programming interface228.

As shown in the illustration ofFIG. 2B, the high phase counter244increments at every rising edge of the clock signal CLK224, when the raw (i.e., not debounced) input signal DI220is at a high logic level, the signal EN226is active (high), and the signal RSTN is inactive (high). When the value in the high phase counter244matches the value in the high phase glitch width register242, the output B250of the high phase comparator245is set to an active high logic level. That is, when the value A243at the “B” input of the high phase comparator245is equal to the value240at the “A” input, the output B250of the high phase comparator245is set to high logic level. The high logic level of output B250is latched into the flip-flop FF1253upon the next rising edge of the clock signal CLK224, and triggers the output H258of the flip-flop FF3257to a high logic level following the second rising edge of clock signal CLK224. Additionally, the signal B250stops the high phase counter244from incrementing, and the high phase counter244remains at the value in the high phase glitch width register242until a reset of the high phase counter244is caused by the input signal DI220, or the reset signal RSTN222. In a representative embodiment of the present invention, positive glitches in the input signal DI220that are smaller in duration than the value in the high phase glitch width register242will not trigger the output H258of the flip-flop FF3257to a high logic level and will not be appear at debounced output DO260. In addition, the return of the input signal DI220to a low logic level will reset the high phase counter244and force signal B250to a low logic level. That low logic level will be latched into FF1253after one clock cycle. The transition of the output signal E255to a low logic level does not trigger the state of flip-flop FF3257to a low logic level, because the high to low transition of signal E255cannot trigger FF3257. By operating as described above, the debounce circuit200removes from the output DO260any positive glitches of the input signal DI220having a duration shorter than the value stored in the high phase glitch width register242.

The debounce circuit200illustrated inFIG. 2Boperates in a similar fashion when operating upon an input signal DI220that is active when at a low logic level. While the input signal DI220is at a high logic level, the low phase counter248is held in reset (i.e., “all-zeros” ). When the input signal DI220is at a low logic level, the low phase counter248is enabled to increment at every rising edge of the clock signal CLK224, when signal EN226is active (high) and signal RSTN is inactive (high). When the low phase counter248matches the value in the low phase glitch width register246, the output D251of the low phase comparator249is set to an active low logic level. That is, when the value C247at the “B” input of the low phase comparator249is equal to the value241at the “A” input, the output D251of the low phase comparator249is set to a low logic level. Additionally, the signal D251stops the low phase counter248from decrementing, and the low phase counter248remains at the value in the low phase glitch width register246until a reset of the low phase counter248is caused by the input signal DI220, or by the reset signal RSTN222. The value of signal D251is latched into the flip-flop FF2254at the next rising edge of the clock signal CLK224. The output F256of the flip-flop FF2254then changes to a low logic level, and the flip-flop FF3257is reset, forcing the output H258of the flip-flop FF3257to a low logic level and passed to debounced output DO260. If the duration of a low logic level portion (i.e., a “negative glitch”) of the input signal DI220is shorter than the value in the low phase glitch width register246, the value of low phase counter248will never match the value of the low phase glitch width register246, and the output D251of the comparator249will not go to a low logic level. Therefore, the output F256of flip-flop FF2254will not be set to a low logic level, and will not reset the state of the flip-flop FF3257. The output H258of the flip-flop FF3257will remain at a high logic level, and the value of the output H258will be passed to the output signal DO260by multiplexer259. Any change of input signal DI220to a high logic level resets the low phase counter248to the “all-zeros” condition and forces signal D251to a high logic level. The high logic level of signal D251is latched into flip-flop FF2254after one clock cycle, but the output signal F256of flip-flop FF2254does not trigger the state of flip-flop FF3257to a high logic level, because the high logic level of signal F256cannot reset flip-flop FF3257. In this manner, any negative glitches (i.e., low logic level portion) in the input signal DI220having a duration of less that the value of the low phase glitch width register246will not be passed to the output DO260.

In a representative embodiment of the present invention, flip-flop FF1253and flip-flop FF2254are used to synchronize output B250and output D251of the high phase comparator245and the low phase comparator249, respectively, to avoid generating any new glitches in the output signal DO260. Although the illustrations ofFIGS. 2A and 2Binclude flip-flops FF1253and FF2254, these components may not be necessary in all representative embodiments of the present invention. For example, the use of flip-flops FF1253and FF2254may be avoided when the comparators245,249do not generate glitches. An example of such a technique may be the use of only one bit of the output of counters244,248in the comparison with the high/low phase glitch width registers242,246, respectively. More specifically, such a technique may use the values of the high/low phase glitch width registers242,246to select different bits of the counters244,248to trigger the signals B250or D251, respectively. In such an embodiment, the one selected bit of the output from the high and/or low phase counters244,248should not have glitches, and may not necessitate the use of flip-flops FF1253and/or FF2254.

FIG. 2Cis a block diagram of another exemplary debounce circuit200for processing an input signal DI220to produce an output signal DO260, in accordance with a representative embodiment of the present invention. The circuit ofFIG. 2Cis similar to that shown inFIG. 2B, with the exception that flip-flop FF1253and flip-flop FF2254ofFIG. 2Bhave been eliminated. A representative embodiment of the present invention as illustrated inFIG. 2Cmay be employed when comparators245,249do not produce glitches. The operation of the circuit shown inFIG. 2Chas been modified from that inFIG. 2B, in that the outputs of comparators245,249are not latched by the signal CLK224into the flip-flop FF1253and flip-flop FF2. Instead, the rising edge of signal B250causes the output H258of flip-flop FF3257to transition to a high logic level. This transition is possible because the low phase counter248is in a reset state, which causes the output D251of the comparator249to be at a high logic level. The output H258of flip-flop FF3is reset to a low logic level when the output D251of the comparator249changes to a low logic level. The output H258of flip-flop FF3257is then passed to the output DO260. The behavior of the circuitry generating output B250and output D251of comparators245,249, respectively, is described above with respect toFIG. 2A,2B.

FIG. 2Dis a block diagram of another exemplary debounce circuit200for processing an input signal DI220to produce an output signal DO260, in accordance with a representative embodiment of the present invention. The circuit ofFIG. 2Dis similar to that shown inFIG. 2B, with the exception that flip-flop FF3257is now operated as a set-reset flip-flop rather than the edge-triggered flip-flop shown inFIGS. 2A,2B,2C. In the embodiment illustrated inFIG. 2D, the output E255of flip-flop FF1253now comes from the inverted output of FF1253, and is passed to the active low set input SN of flip-flop FF3257. The output B250of comparator245is latched into the flip-flop FF1253as described above with respect toFIGS. 2A,2B. However, in the illustration ofFIG. 2Dit is the low logic level rather than the rising edge of the output E255that causes the output258of flip-flop FF3257to change to a high logic level. Flip-flop FF3257is reset in the same fashion described above with respect toFIGS. 2A,2B, when the output D251of comparator249changes to a high logic level.

FIG. 2Eis a block diagram of another exemplary debounce circuit200for processing an input signal DI220to produce an output signal DO260, in accordance with a representative embodiment of the present invention. In a representative embodiment of the present invention, the values provided by the high phase glitch width register242and the low phase glitch width register246ofFIGS. 2A,2B2C,2D, may instead be provided by a single merged high/low phase glitch width register242, as shown inFIG. 2E. This arrangement may be employed when both the high and low phase counters244,248count in the same direction (i.e., up or down), and when the expected high and low state bounce/glitch characteristics of the input signal DI220are similar. In a representative embodiment in which the high and low phase counters244and248count in different directions, the filtering behavior for positive-going and negative-going glitches may not be the same. As shown inFIG. 2E, such an embodiment avoids the use of separate high and low phase glitch width registers, saving integrated circuit chip area and reducing chip cost.

FIG. 2Fis a block diagram of another exemplary debounce circuit200for processing an input signal DI220to produce an output signal DO260, in accordance with a representative embodiment of the present invention. In a representative embodiment of the present invention, the values provided by the high phase glitch width register242and the low phase glitch width register246ofFIGS. 2A,2B2C,2D, may instead be set to fixed values, as shown inFIG. 2F. This arrangement may be employed when both the high and low phase counters244,248count in the same direction (i.e., up or down), or in different directions, and when the bounce/glitch characteristics of the input signal DI220are well known and programmability of the operation of the debounce circuit200is not desirable. As shown inFIG. 2F, such an embodiment avoids the use of high and low phase glitch width registers242,246, and the circuitry used to allow programming of the high and low phase glitch width registers242,246. The use of such a representative embodiment of the present invention saves integrated circuit chip area and cost when the flexibility of the other arrangements described above with respect toFIGS. 2A,2B,2C,2D, and2E are not desired.

FIG. 3shows exemplary waveforms of signals RSTN322, EN326, B350, D351, and DO360, that may correspond, for example, to signals RSTN222, EN226, B250, D251, and output signal DO260of the debounce circuit200ofFIG. 2Ain the presence of an active high input signal DI320that may correspond, for example, to the input signal DI220ofFIG. 2A, in accordance with a representative embodiment of the present invention. The waveforms shown inFIG. 3provide a graphical representation of the behavior described above with respect to the debounce circuit200ofFIG. 2A. In the illustration ofFIG. 3, the signal B350is set to an active high logic level after signal DI320remains at a high logic level for a time interval302. The time interval302may be determined, for example, by the value stored in the high phase glitch width register242of the debounce circuit200ofFIG. 2A. The level of signal B350later triggers output DO360to a high logic level after two clock cycles, at time304. The level of signal D351is set low after signal DI320remains at a low logic level for a time period310. The duration of the time period310may be determined, for example, by the value stored in the low phase glitch width register246of the debounce circuit200ofFIG. 2A. The fall of signal D351later triggers output DO360to a low logic level after one clock cycle, at time312. In this manner, the signal DO360is output as a clean signal, without the glitches that appear during leading and trailing portions of the signal DI320shown inFIG. 3. The duration of the low and high portions of the signal DO360closely approximates the duration of the low and high portions of the signal DI320. In addition, although a noise spike306appears in the mid-portion of the signal DI320, the logic low duration of the noise spike306is shorter than the time period310that is set in the low phase glitch width register246ofFIG. 2Aand, therefore, does not appear in the signal DO360.

FIG. 4shows exemplary waveforms of signals RSTN422, EN426, B450, D451, and DO460, that may correspond, for example, to signals RSTN222, EN226, B250, D251, and output signal DO260of the debounce circuit200ofFIG. 2Ain the presence of an active low input signal DI420that may, for example, correspond to the input signal DI220ofFIG. 2A, in accordance with a representative embodiment of the present invention. The waveforms shown inFIG. 4provide a graphical representation of the behavior described above with respect to the debounce circuit200ofFIG. 2A. In the illustration ofFIG. 4, the signal B450is set to an active low logic level at400following the first negative transition of the input signal DI420. The signal D451changes to a low logic level once the input signal DI420remains at a low logic level for a time period402that maybe determined by, for example, the value stored in the low phase glitch width register246ofFIG. 2A. That change in signal D451later appears at signal DO460after one clock cycle, at time404. The signal B450transitions to a high logic level after the signal DI420remains at a high logic level for time period410that may be determined by, for example, the value stored in the high phase glitch width register242ofFIG. 2A. The rise of signal B450propagates to force the signal DO460to a logic high state after two clock cycles, at time412. The signal DI420is processed to produce a clean signal DO460without the noise spikes (i.e., glitches) that appear at the leading and trailing portions of the waveform of the DI420signal. The length of the low logic level portion of signal DO460is approximately the same as the length of the low logic level portion of signal DI420, resulting in a balanced debouncing action. Although a positive noise spike406appears in the mid-portion of the signal DI420, the logic high duration of the noise spike406is shorter than the time period410that is set in the high phase glitch width register242ofFIG. 2Aand, therefore, does not appear in the signal DO460.

FIG. 5shows the waveforms of signals CLK524, RSTN522, EN526, High Phase Glitch Width540, DI520, A543, B550, E555, H558, and DO560, that may correspond, for example, to the signals CLK224, RSTN222, EN226, High Phase Glitch Width240, DI220, A243, B250, E255, H258, and DO260of the debouncing circuit200ofFIG. 2A, illustrating the operation of a high phase counter that may correspond, for example, to the high phase counter244ofFIG. 2A, in accordance with a representative embodiment of the present invention. In order to clarify the operation of a representative embodiment of the present invention, the following description makes references to the elements ofFIG. 2A. As shown inFIG. 5, any glitches on signal DI520may be propagated to signal DO560during the time period when signal EN526is at a low logic level (inactive), such as, for example, at time500. After signal EN526is set to a high logic level (active), however, the high logic level of signal DI520permits the high phase counter244to increment at every rise edge of the clock signal CLK524, beginning at time502. At time504, signal DI520transitions to a low logic level, causing the high phase counter244to be immediately reset to the “all zeros” state. Following a change in signal DI520to a high logic level at506, the high phase counter244once again begins incrementing at each rising edge of the CLK524, until a match with the value in the high phase glitch width register242(shown inFIG. 5as signal value “n”) occurs at508. At that point, signal B550changes to a high logic level, and the value of signal B550then propagates to the signal DO560after two clock cycles, at510. Although there is a negative noise spike in signal DI520at512, the noise spike is of too short a duration to trigger the transition of signal DO560to a low logic level as described above.

FIG. 6shows the waveforms of signals CLK624, RSTN622, EN626, Low Phase Glitch Width641, DI620, C647, D651, F656, H658, and DO660, that may correspond, for example, to the signals CLK224, RSTN222, EN226, Low Phase Glitch241, DI220, C247, D251, F256, H258, and DO260of the debouncing circuit200ofFIG. 2A, illustrating the operation of a low phase counter that may correspond, for example, to the low phase counter248ofFIG. 2A, in accordance with a representative embodiment of the present invention. In order to clarify the operation of a representative embodiment of the present invention, the following description makes references to the elements ofFIG. 2A. As shown inFIG. 6, any glitches on signal DI620may be propagated to signal DO660during the time period when signal EN626is at a low logic level (inactive), such as, for example, at time600. After signal EN626is set to a high logic level (active), however, the low logic level of signal DI620permits the low phase counter248to decrement at every rise edge of the clock signal CLK624, beginning at time602. At time604, signal DI620transitions to a high logic level, causing the low phase counter248to be immediately reset to the “all ones” state. Following a change in signal DI620to a low logic level, the low phase counter248once again begins at606to decrement at each rising edge of the CLK624, until a match with the value in the low phase glitch width register246(shown inFIG. 6as signal value “n”) occurs at608. At that point, signal D651changes to a low logic level, and the value of signal D651then propagates to the signal DO660after the next rising edge of the clock CLK624, at610. Although there is a positive noise spike in signal DI620at612, the noise spike is of too short a duration to trigger the transition of signal DO660to a high logic level.

FIG. 7is a flowchart700illustrating an exemplary method of debouncing an input signal that produces a debounced output signal in accordance with a representative embodiment of the present invention. Although the method ofFIG. 7is shown as having a start and an end, this is for reasons of clarity. In a representative embodiment of the present invention, the method shown inFIG. 7may be performed on a repeated and/or continuous basis and never stopped, for example, once power-up of a system employing the method has occurred, beginning at the start (block710). An input signal is received (block714) and it is determined whether the input signal is in a first state (block714). If the input signal is determined to be in the first state (block714), a measurement of a first time period may be made (block716), and a second time period may be reset to a second predetermined value (block718). It is then determined whether the first time period is greater than or equal to a first predetermined time period (block720). If the first time period is not greater than or equal to the first predetermined time period (block720), the method then finishes (block732). If the first time period is greater than or equal to the first predetermined time period (block720), then a debounced output signal may be set to the first state (block722), and the method finishes (block732). As stated above, the method illustrated inFIG. 7may be performed in a continuous, concurrent, and never ending fashion. The illustration ofFIG. 7terminates at an end (block732) solely for reasons of clarity.

If the input signal is determined not to be in the first state (block714), it may be considered to be in a second state, and a measurement of a second time period may be made (block724). In addition, the first time period may be reset to a first predetermined value (block726). It is then determined whether the second time period is greater than or equal to a second predetermined time period (block728). If the second time period is not greater than or equal to the second predetermined time period (block728), the method finishes (block732). If the second time period is greater than or equal to the second predetermined time period (block728), then the debounced output signal may be set to the second state (block730), and the method finishes (block732). As described above, the method illustrated inFIG. 7may be performed in a continuous, concurrent, and never-ending fashion. The illustration ofFIG. 7terminates at an end (block732) solely for reasons of clarity.

The present invention overcomes many of the drawbacks of conventional and traditional approaches. First, a representative embodiment of the present invention uses digital circuitry to replace analog components typically used to perform filtering. It is thus easy to integrate into a digital system, and may be implemented as software in a computer system. Second, a representative embodiment of the present invention uses two sets of complementary counters and comparators to filter both positive and negative going bounces or “both directions of glitches” from an input signal. This results in a debounced output signal having a length substantially equal to that of the input signal, and from which glitches have been filtered in addition to any noise that may be present in the leading and trailing portions of the input signal. In addition, any glitches having a width that is smaller than the predetermined setting will be filtered out. Third, a representative embodiment of the present invention supports programming of the width of any signal bounce to be filtered. This provides flexibility for use with difference switches having a wide variety of bounce characteristics.

Aspects of the present invention may be found in a circuit for debouncing an input signal having at least a first state and a second state. In a representative embodiment of the present invention, the circuit may comprise a first counter responding to a clock signal while the input signal is in the first state, and maintained at a first reset value while the input signal is in the second state, the first counter producing an output. Such an embodiment may also comprise a second counter that responds to the clock signal while the input signal is in the second state, and is maintained at a second reset value while the input signal is in the first state, where the second counter produces an output. Such a circuit may comprise a first comparator that produces an output indicating whether a match of the first output to a first predetermined value exists, and a second comparator that produces an output indicating whether a match of the second output to a second predetermined value exists. In addition, such a circuit may comprise a latch having an output that is set to the first state when a match of the first output to a first predetermined value exists, and that is set to the second state when a match of the second output to a second predetermined value exists. A representative embodiment in accordance with the present invention may also comprise a second latch for storing the output of the first comparator, based upon the clock signal, and a third latch for storing the output of the second comparator, based upon the clock signal.

A representative embodiment of the present invention may comprise a first register for holding the first predetermined value, and a second register for holding the second predetermined value, and a multiplexer for selecting one of the input signal and the output of the third latch based upon a second input signal. The first counter and the second counter may be enabled to count based upon a second input signal. In a representative embodiment of the present invention, each of the first counter and the second counter may be maintained in one of at least one predetermined state based upon a third input signal. In one representative embodiment of the present invention, the first counter may be an up-counter and the second counter may be a down-counter. In another representative embodiment of the present invention, the first counter and the second counter may be up-counters. In yet another representative embodiment of the present invention, the first counter and the second counter may be down-counters.

Additional aspects of the present invention may be seen in a debouncing circuit for filtering an input signal having at least a first state and a second state. A representative embodiment in accordance with the present invention may comprise a first timing circuit for measuring a first time period while the input signal is in the first state, where the first timing circuit is responsive to a clock input while the input signal is in the first state, and where the first timing circuit is held at a first reset value while the input signal is in the second state. Such an embodiment may also comprise a second timing circuit for measuring a second time period while the input signal is in the second state, where the second timing circuit is responsive to the clock input while the input signal is in the second state, and where the second timing circuit is held at a second reset value while the input signal is in the first state. Such an embodiment may also comprise a deglitching circuit that produces, in response to the clock input, an output signal taking the first state when the first time period is at least a first predetermined value, and taking the second state when the second time period is at least a second predetermined value.

In a representative embodiment of the present invention, the input signal may be passed essentially unchanged to the output signal depending upon a state of a second input signal. A representative embodiment of the present invention may also comprise an interface for receiving at least one of the first predetermined value and the second predetermined value. In addition, such an embodiment may comprise a first register for storing the first predetermined value, and a second register for storing the second predetermined value. At least a portion of the circuit may be powered down depending upon a state of one of the second input signal and a third input signal.

Yet other aspects of the present invention may be observed in a method of debouncing an input signal having at least a first state and a second state to produce an output signal. Such a method may comprise measuring a first time period and resetting a second time period, while the input signal is in the first state, and measuring the second time period and resetting the first time period, while the input signal is in the second state. A method in accordance with the present invention may also comprise setting the output signal to the first state, if the first time period is at least a first predetermined time period, and setting the output signal to the second state, if the second time period is at least a second predetermined time period. Measuring the first time period, measuring the second time period, setting the output signal to the first state, and setting the output signal to the second state may be based upon a common clock signal. In addition, the input signal may be reproduced essentially unchanged at the output signal depending upon a state of a second input signal.

Still other aspects of the invention may be found in a machine-readable storage, having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the method described above.

Yet other aspects of the present invention may be observed in a digital circuit for debouncing an input signal having a first state and a second state and producing an output. The circuit may be disposed entirely within an integrated circuit device and may function at least to communicate to the output only changes of input signal state occurring at least a predetermined period of time after the most recent previous change of input signal state. The predetermined period of time in a representative embodiment of the present invention, may be programmable, and may comprise a first predetermined period of time used when the input signal is in the first state, and a second predetermined period of time used when the input signal is in the second state. The input signal may be passed essentially unchanged to the output based upon a second input signal, and changes in the output may be responsive to a clock signal.

Additional aspects of the present invention may be seen in a digital circuit for debouncing an input signal having a first state and a second state. The circuit may be disposed within an integrated circuit device. The circuit may function at least to produce an output signal having a predetermined minimum period of time between output state transitions without the use of at least one of an resistor and a capacitor for setting the predetermined minimum period of time. The predetermined minimum period of time may be programmable, and comprise a first period of time corresponding to the first input state and a second period of time corresponding to the second input state. The predetermined minimum period of time may beis based upon a clock signal, and the input signal may be passed essentially unchanged to the output signal based upon a second input signal.