Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

BACKGROUND

A latch (or flip-flop) is an electronic circuit that can store state information. The state information stored by the latch can be changed by control signals provided via control inputs.

DETAILED DESCRIPTION

Due to the nature of logic gates, the output of a latch may not change instantaneously in response to changes in control input signals. As a result, the input-to-output propagation of a latch signal may incur a propagation delay as it passes through each logic gate. As an example, the input-to-output propagation of a set-reset (SR) NAND latch signal may incur two propagation delays, one delay for each cross-coupled NAND gate.

Examples disclosed herein provide SR latch circuits and methods for manufacturing the same. The disclosed SR latch circuits and manufacturing methods may, among other things, reduce input-to-output propagation delays in SR latches.

In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of PFETs for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of n-channel field-effect transistors (NFETs) for control circuitry. The NFETs may include first and second NFETs connected to a first node of the inverter storage loop, and third and fourth NFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth NFETs may be connected to a first control input, and gate terminals of the second and third NFETs may be connected to a second control input.

FIG. 1is a block diagram of an example SR latch100circuit. As shown inFIG. 1, SR latch100circuit may include an inverter storage loop110and a plurality of PFETs120-150. The number and arrangement of these components is an example only and provided for purposes of illustration. Other arrangements and numbers of components may be utilized without departing from the examples of the present disclosure.

As shown inFIG. 1, inverter storage loop110may include a pair of cross-coupled inverters, inverter111and inverter112. In some examples, inverter111and inverter112may be complementary metal-oxide semiconductor (CMOS) inverters in that inverter111and inverter112may each include a PFET and an NFET. Inverter storage loop110may store state information for SR latch100circuit.

PFETs120-150may be connected to inverter storage loop110. PFETs120-150may be control circuitry that may be used to control the state information stored by inverter storage loop110. PFETs120-150may be p-channel metal-oxide semiconductor FETs (pMOSFETs), p-channel junction FETs (pJFETs), another type of p-channel field-effect transistor, or a combination thereof.

PFET120and PFET130may be connected to a first node of inverter storage loop110, slat (or Set Latch). The source terminal of PFET120may be connected to a voltage source, VDD, whereas the drain terminal of PFET120may be connected to the first node of inverter storage loop110, slat. When a conductive channel is formed between the source terminal and drain terminal of PFET120, the output of inverter storage loop110at first node slat may be pulled up to VDD.

The drain terminal of PFET130may be connected to a voltage drain, Vss, whereas the source terminal of PFET130may be connected to the first node of inverter storage loop110, slat. When a conductive channel is formed between the source terminal and drain terminal of PFET130, the output of inverter storage loop110at first node slat may be pulled down to VSS.

PFET140and PFET150may be connected to a second node of inverter storage loop110, rlat (or Reset Latch). The source terminal of PFET140may be connected to a voltage source, VDD, whereas the drain terminal of PFET140may be connected to the second node of inverter storage loop110, rlat. When a conductive channel is formed between the source terminal and drain terminal of PFET140, the output of inverter storage loop110at second node rlat may be pulled up to VDD.

The drain terminal of PFET150may be connected to a voltage drain, VSS, whereas the source terminal of PFET150may be connected to the second node of inverter storage loop110, rlat. When a conductive channel is formed between the source terminal and drain terminal of PFET150, the output of inverter storage loop110at second node rlat may be pulled down to VSS.

The gate terminals of PFETs120-150may be connected to control inputs. The control inputs may be used to control PFETs120-150(i.e., by turning PFETs120-150on and off) to change the state information stored by inverter storage loop110. As shown inFIG. 1, the gate terminals of PFET120and PFET150may be connected to a first control input, sx (or Set), whereas the gate terminals of PFET130and PFET140may be connected to a second control input, rx (or Reset). The gate terminals of PFETs120-150may be active-low inputs in that when control inputs sx and rx are asserted low (i.e., logic 0) on the gate terminals to which control inputs sx and rx are connected, a conducting channel is formed between the associated source and drain terminals. Conversely, when control inputs sx and rx are asserted high (i.e., logic 1), a conducting channel is not formed between the associated source and drain terminals.

In SR latch100circuit operation, when the sx control inputs are asserted low (logic 0) and the rx control inputs are asserted high (logic 1), conductive channels are formed between the source and drain terminals of PFET120and PFET150whereas no conductive channels are formed between the source and drain terminals of PFET130and PFET140. PFET120and PFET150are therefore turned on and conducting whereas PFET130and PFET140are turned off and not conducting. PFET120pulls the output of inverter storage loop110at first node slat up to VDD(logic 1). PFET150pulls the output of inverter storage loop110at second node rlat down to VSS(logic 0).

In some implementations, a minimum threshold voltage (VTP) may be used to form the conductive channel between the source and drain terminals of PFET150. PFET150may therefore initially pull the output of inverter storage loop110at second node rlat down to VSS+VTP. However, inverter112may invert the VSS+VTPoutput at second node rlat to VDDat slat and inverter111may invert the VDDat slat to VSSat rlat. Accordingly, the cross-coupled nature of inverter storage loop110may rectify the initial VSS+VTPoutput at second node rat to VSS.

When the sx control inputs are asserted high (logic 1) and the rx control inputs are asserted low (logic 0), conductive channels are formed between the source and drain terminals of PFET130and PFET140whereas no conductive channels are formed between the source and drain terminals of PFET120and PFET150. PFET130and PFET140are therefore turned on and conducting whereas PFET120and PFET150are turned off and not conducting. PFET130pulls the output of inverter storage loop110at first node slat down to VSS(logic 0) (initially VSS+VTPbut rectified to VSSby cross-coupled inverters111and112). PFET140pulls the output of inverter storage loop110at second node rat up to VDD(logic 1).

The resulting logic table for example SR latch100circuit illustrated inFIG. 1. may be as follows:

sxrxslatrlatState00XXNot Allowed0110Set1001Reset11slatrlatHold
Due to the structure of SR latch100circuit, each state change for SR latch100circuit results in a single input-to-output propagation delay. For example, to change the state of SR latch100circuit from Set to Reset (i.e., slat/rlat from 1/0 to 0/1), a single input-to-output propagation delay is incurred by PFETs120-150to pull slat down to 0 and rlat up to 1. Similarly, to change the state of SR latch100circuit from Reset to Set (i.e., slat/rlat from 0/1 to 1/0), a single input-to-output propagation delay is incurred by PFETs120-150to pull slat up to 1 and rlat down to 0.

SR latch100circuit may be manufactured at various processing nodes. In some examples, SR latch100circuit may be manufactured at processing nodes 16 nm or less. At processing nodes greater than 16 nm, NFET switching may be faster than PFET switching due to the differences in electron mobility and hole mobility. Electron and hole mobility (collectively referred to as carrier mobility) may quantify the ability of a carrier (electron or hole) to move through a medium such as a metal or semiconductor. The quicker a carrier can move through the medium, the higher the carrier's mobility.

NFETs are n-channel devices that use electrons as carriers to form conductive channels between source and drain terminals. PFETs are p-channel devices that use holes as carriers to form conductive channels between source and drain terminals. At manufacturing processes greater than 16 nm, NFET switching may be as much as two times faster than PFET switching. However, as processing nodes shrink, so does the difference in mobility between electrons and holes. At 16 nm, electron mobility and hole mobility (and thus NFET and PFET switching speeds) may be at or near parity.

FIG. 2is a block diagram of an example SR latch circuit200. As shown inFIG. 2, SR latch circuit200may include an inverter storage loop210and a plurality of PFETs220-250. The number and arrangement of these components is an example only and provided for purposes of illustration. Other arrangements and numbers of components may be utilized without departing from the examples of the present disclosure. SR latch circuit200may be similar to SR latch100circuit ofFIG. 1, except that the detail of the cross-coupled inverters of inverter storage loop210is illustrated inFIG. 2.

Inverter loop210may include a PFET211, a NFET212, a PFET213, and a NFET214. PFET211and NFET212may form one of the two cross-coupled inverters included in inverter storage loop210, whereas PFET213and NFET214may form the second of the two cross-coupled inverters included in inverter storage loop210.

FIG. 3is a block diagram of an example SR latch circuit300. As shown inFIG. 3, SR latch circuit300may include an inverter storage loop310and a plurality of NFETs320-350. The number and arrangement of these components is an example only and provided for purposes of illustration. Other arrangements and numbers of components may be utilized without departing from the examples of the present disclosure. SR latch circuit300may be manufactured at various processing nodes such as, for example, 16 nm, less than 16 nm, and greater than 16 nm.

As shown inFIG. 3, inverter storage loop310may include a pair of cross-coupled inverters, inverter311and inverter312. In some examples, inverter311and inverter312may be CMOS inverters in that inverter311and inverter312may each include a PFET and a NFET. Inverter storage loop310may store state information for SR latch circuit300.

NFETs320-350may be connected to inverter storage loop310. NFETs320-350may be control circuitry that may be used to control the state information stored by inverter storage loop310. NFETs320-150may be n-channel metal-oxide semiconductor FETs (nMOSFETs), n-channel junction FETs (nJFETs), another type of n-channel field-effect transistor, or a combination thereof.

NFET320and NFET330may be connected to a first node of inverter storage loop310, slat (or Set Latch). The drain terminal of NFET320may be connected to a voltage source, VDD, whereas the source terminal of NFET320may be connected to the first node of inverter storage loop310, slat. When a conductive channel is formed between the source terminal and drain terminal of NFET320, the output of inverter storage loop310at first node slat may be pulled up to VDD.

The source terminal of NFET330may be connected to a voltage drain, Vss, whereas the drain terminal of NFET330may be connected to the first node of inverter storage loop310, slat. When a conductive channel is formed between the source terminal and drain terminal of NFET330, the output of inverter storage loop310at first node slat may be pulled down to VSS.

NFET340and NFET350may be connected to a second node of inverter storage loop310, rlat (or Reset Latch). The drain terminal of NFET340may be connected to a voltage source, VDD, whereas the source terminal of NFET340may be connected to the second node of inverter storage loop310, rlat. When a conductive channel is formed between the source terminal and drain terminal of NFET340, the output of inverter storage loop310at second node flat may be pulled up to VDD.

The source terminal of NFET350may be connected to a voltage drain, VSS, whereas the drain terminal of NFET350may be connected to the second node of inverter storage loop310, rlat. When a conductive channel is formed between the source terminal and drain terminal of NFET350, the output of inverter storage loop310at second node rlat may be pulled down to VSS.

The gate terminals of NFETs320-350may be connected to control inputs. The control inputs may be used to control NFETs320-350(i.e., by turning NFETs320-350on and off) to change the state information stored by inverter storage loop310. As shown inFIG. 3, the gate terminals of NFET320and NFET350may be connected to a first control input, s (or Set), whereas the gate terminals of NFET330and PFET340may be connected to a second control input, r (or Reset). The gate terminals of NFETs320-350may be active-high inputs in that when control inputs s and rare asserted high (i.e., logic 1) on the gate terminals to which control inputs s and r are connected, a conducting channel is formed between the associated source and drain terminals. Conversely, when control inputs s and r are asserted low (i.e., logic 0), a conducting channel is not formed between the associated source and drain terminals.

In SR latch circuit300operation, when the s control inputs are asserted high (logic 1) and the r control inputs are asserted low (logic 0), conductive channels are formed between the source and drain terminals of NFET320and NFET350whereas no conductive channels are formed between the source and drain terminals of NFET330and NFET340. NFET320and NFET350are therefore turned on and conducting whereas NFET330and NFET340are turned off and not conducting. NFET320pulls the output of inverter storage loop310at first node slat up to VDD(logic 1). NFET350pulls the output of inverter storage loop310at second node rlat down to VSS(logic 0).

In some implementations, a minimum threshold voltage (VTN) may be used to form the conductive channel between the source and drain terminals of NFETs320-350. NFET350may therefore initially pull the output of inverter storage loop310at second node rlat down to VSS+VTN. However, inverter312may invert the VSS+VTNoutput at second node rlat to VDDat slat and inverter311may invert the VDDat slat to VSSat rlat. Accordingly, the cross-coupled nature of inverter storage loop310may rectify the initial VSS+VTNoutput at second node rlat to VSS.

When the s control inputs are asserted low (logic 0) and the r control inputs are asserted high (logic 1), conductive channels are formed between the source and drain terminals of NFET330and NFET340whereas no conductive channels are formed between the source and drain terminals of NFET320and NFET350. NFET330and NFET340are therefore turned on and conducting whereas NFET320and NFET350are turned off and not conducting. NFET330pulls the output of inverter storage loop310at first node slat down to VSS(logic 0) (initially VSS+VTNbut rectified to VSSby cross-coupled inverters311and312). NFET340pulls the output of inverter storage loop310at second node rlat up to VDD(logic 1).

The resulting logic table for example SR latch circuit300illustrated inFIG. 3. may be as follows:

srslatrlatState00slatrlatHold0101Reset1010Set11XXNot Allowed
Due to the structure of SR latch circuit300, each state change for SR latch circuit300results in a single input-to-output propagation delay. For example, to change the state of SR latch circuit300from Set to Reset (i.e., slat/rlat from 1/0 to 0/1), a single input-to-output propagation delay is incurred by NFETs320-350to pull slat down to 0 and rlat up to 1. Similarly, to change the state of SR latch circuit300from Reset to Set (i.e., slat/rlat from 0/1 to 1/0), a single input-to-output propagation delay is incurred by NFETs320-350to pull slat up to 1 and rlat down to 0.

FIG. 4is a block diagram of an example SR latch circuit400. As shown inFIG. 4, SR latch circuit400may include an inverter storage loop410and a plurality of NFETs420-450. The number and arrangement of these components is an example only and provided for purposes of illustration. Other arrangements and numbers of components may be utilized without departing from the examples of the present disclosure. SR latch circuit400may be similar to SR latch circuit300ofFIG. 3, except that the detail of the cross-coupled inverters of inverter storage loop410is illustrated inFIG. 4.

Inverter loop410may include a PFET411, a NFET412, a PFET413, and a NFET414. PFET411and NFET412may form one of the two cross-coupled inverters included in inverter storage loop410, whereas PFET413and NFET414may form the second of the two cross-coupled inverters included in inverter storage loop410.

FIG. 5is a flowchart depicting an example method500for manufacturing a SR latch circuit. Method500may, for example, be used to manufacture SR latch circuit100circuit ofFIG. 1and SR latch circuit200ofFIG. 2. In some examples, steps of method500may be executed substantially concurrently or in a different order than shown inFIG. 5. In some examples, method500may include more or less steps than are shown inFIG. 5. In some examples, some of the steps of method500may be ongoing or repeat.

At block502, method500may include forming an inverter storage loop for storing state information, such as inverter storage loop110ofFIG. 1and inverter storage loop210ofFIG. 2.

At block504, method500may include forming first and second PFETs connected to a first node of the inverter storage loop, such as PFET120and PFET130ofFIG. 1, and PFET220and PFET230ofFIG. 2.

At block506, method500may include forming third and fourth PFETs connected to a second node of the inverter storage loop, such as PFET140and PFET150ofFIG. 1, and PFET240and PFET250ofFIG. 2.

FIG. 6is a flowchart depicting an example method600for manufacturing a SR latch circuit. Method600may, for example, be used to manufacture SR latch100circuit ofFIG. 1and SR latch circuit200ofFIG. 2. In some examples, steps of method600may be executed substantially concurrently or in a different order than shown inFIG. 6. In some examples, method600may include more or less steps than are shown inFIG. 6. In some examples, some of the steps of method600may be ongoing or repeat.

At block602, method600may include forming a cross-coupled first inverter and second inverter, such as inverter111ofFIG. 1and inverter112ofFIG. 1. The cross-coupled first inverter and second inverter may each include a PFET and an NFET, such as PFET211and NFET212, and PFET213and NFET214ofFIG. 2. The cross-coupled first inverter and second inverter may form an inverter storage loop for storing state information, such as inverter storage loop110ofFIG. 1, and inverter storage loop210ofFIG. 2.

At block604, method600may include forming first and second PFETs connected to a first node of the inverter storage loop, such as PFET120and PFET130ofFIG. 1, and PFET220and PFET230ofFIG. 2.

At block606, method600may include forming third and fourth PFETs connected to a second node of the inverter storage loop, such as PFET140and PFET150ofFIG. 1, and PFET240and PFET250ofFIG. 2.

At block608, method600may include connecting gate terminals of the first and fourth PFETs to a first control input, such as sx ofFIG. 1andFIG. 2.

At block610, method600may include connecting gate terminals of the second and third PFETs to a second control input, such as rx ofFIG. 1andFIG. 2.

FIG. 7is a flowchart depicting an example method700for manufacturing a SR latch circuit. Method700may be used, for example, to manufacture SR latch circuit300ofFIG. 3and SR circuit latch400ofFIG. 4. In some examples, steps of method700may be executed substantially concurrently or in a different order than shown inFIG. 7. In some examples, method700may include more or less steps than are shown inFIG. 7. In some examples, some of the steps of method700may be ongoing or repeat.

At block702, method700may include forming an inverter storage loop for storing state information, such as inverter storage loop310ofFIG. 3and inverter storage loop410ofFIG. 4.

At block704, method700may include forming first and second NFETs connected to a first node of the inverter storage loop, such as NFET320and NFET330ofFIG. 3, and NFET420and NFET430ofFIG. 4.

At block706, method700may include forming third and fourth NFETs connected to a second node of the inverter storage loop, such as NFET340and NFET350ofFIG. 3, and NFET440and NFET450ofFIG. 4.

FIG. 8is a flowchart depicting an example method800for manufacturing a SR latch circuit. Method800may, for example, be used to manufacture SR latch circuit300ofFIG. 3and SR latch circuit400ofFIG. 4. In some examples, steps of method800may be executed substantially concurrently or in a different order than shown inFIG. 8. In some examples, method800may include more or less steps than are shown inFIG. 8. In some examples, some of the steps of method800may be ongoing or repeat.

At block802, method800may include forming a cross-coupled first inverter and second inverter, such as inverter311ofFIG. 3and inverter312ofFIG. 3. The cross-coupled first inverter and second inverter may each include a PFET and an NFET, such as PFET411and NFET412, and PFET413and NFET414ofFIG. 4. The cross-coupled first inverter and second inverter may form an inverter storage loop for storing state information, such as inverter storage loop310ofFIG. 3and inverter storage loop410ofFIG. 4.

At block804, method800may include forming first and second NFETs connected to a first node of the inverter storage loop, such as NFET320and NFET330ofFIG. 3, and NFET420and NFET430ofFIG. 4.

At block806, method800may include forming third and fourth NFETs connected to a second node of the inverter storage loop, such as NFET340and NFET350ofFIG. 3, and NFET440and NFET450ofFIG. 4.

At block808, method800may include connecting gate terminals of the first and fourth NFETs to a first control input, such as s ofFIG. 3andFIG. 4.

At block810, method800may include connecting gate terminals of the second and third NPFETs to a second control input, such as r ofFIG. 3andFIG. 4.

The example SR latch circuits described inFIGS. 1-4, and the SR latch circuits manufactured according to the methods illustrated inFIGS. 5-8, may be used to form various circuits and other structures.FIG. 9illustrates an example SR latch multiplexer (MUX) circuit900that includes a plurality of SR latch circuits (i.e., SR latch circuit910and SR latch circuit920) that may be implemented by SR latch circuit100illustrated inFIG. 1. SR latch MUX circuit900may also include a plurality of FETs, including PFET931,932,941, and942; and NFET933,934,943, and944. The number and arrangement of these components is an example only and provided for purposes of illustration. Other arrangements and numbers of components may be utilized without departing from the examples of the present disclosure. For example, SR latch circuits910and920may be implemented by SR latch circuit200ofFIG. 2, SR latch circuit300ofFIG. 3, SR latch circuit400ofFIG. 4, or a combination thereof.

As shown inFIG. 9, the source terminals of PFET931,932,941, and942may be connected to VDD; and the source terminals of NFET933,934,943, and944may be connected to VSS. The drain terminals of PFET931,932,941, and942may be connected to the source terminals of PFET912,914,922, and924respectively. The drain terminals of NFET933,934,943, and944may be connected to the drain terminals of PFET913,915,923, and925respectively. The gate terminals of NFET933and934and PFET941and942may be connected to the Enable (EN) input of SR latch MUX circuit900. The gate terminals of PFET931and932and NFET943and944may be connected to the Enable B (ENB) input of SR latch MUX circuit900. First nodes Q of inverter storage loops911and921may be connected to each other and second nodes QB inverter storage loops911and921may be connected to each other.

In operation, PFET931,932,941, and942; and NFET933,934,943, and944act as qualifiers for SR latch circuit910and920's operation. For example, when ENB is asserted low and EN is asserted high, PFET931and932and NFET933and934are activated, thereby allowing SR latch circuit910to operate as described above in reference toFIGS. 1-4. In contrast, NFET941and942and PFET943and944are deactivated, thereby deactivating SR latch circuit920. As another example, when ENB is asserted high and EN is asserted low, PFET931and932and NFET933and934are deactivated, thereby deactivating SR latch circuit910. In contrast, NFET941and942and PFET943and944are activated, thereby allowing SR latch circuit920to operate as described above in reference toFIGS. 1-4.

FIG. 10is a flowchart depicting an example method1000for manufacturing a SR latch MUX circuit. Method1000may, for example, be used to manufacture SR latch MUX circuit900ofFIG. 9. In some examples, steps of method1000may be executed substantially concurrently or in a different order than shown inFIG. 10. In some examples, method1000may include more or less steps than are shown inFIG. 10. In some examples, some of the steps of method1000may be ongoing or repeat.

At block1002, method1000may include forming first and second SR latch circuits. The first and second SR latch circuits may be any of the example SR latch circuits described inFIGS. 1-4or the SR latch circuits manufactured according to the methods illustrated inFIGS. 5-8.

At block1004, method1000may include forming fifth and sixth PFETs connected to the first and third PFETs of the first SR latch circuit, such as PFET931and932ofFIG. 9. The fifth and sixth PFETs may further be connected to VDDand ENB inputs.

At block1006, method1000may include forming seventh and eighth PFETs connected to the first and third PFETs of the second SR latch circuit, such as PFET941and942ofFIG. 9. The seventh and eighth PFETs may further be connected to VDDand EN inputs.

At block1008, method1000may include forming first and second NFETs connected to the second and fourth PFETs of the first SR latch circuit, such as PFET933and934ofFIG. 9. The first and second NFETs may further be connected to VSSand EN inputs.

At block1010, method1000may include forming third and fourth NFETs connected to the second and fourth PFETs of the second SR latch circuit, such as PFET943and944ofFIG. 9. The third and fourth NFETs may further be connected to VSSand ENB inputs.

At block1012, method1000may include connecting the first node of the inverter storage loop of the first SR latch circuit with the first node of the inverter storage loop of the second SR latch circuit.

At block1014, method1000may include connecting the second node of the inverter storage loop of the first SR latch circuit with the second node of the inverter storage loop of the second SR latch circuit.

FIG. 11illustrates an example SR latch MUX circuit1100that includes a plurality of SR latch circuits (i.e., SR latch circuit1110and SR latch circuit1120) that may be implemented by SR latch100circuit illustrated inFIG. 1. SR latch MUX circuit1100may also include a plurality of FETs, including PFET1131and1141and NFET1132and1142. The number and arrangement of these components is an example only and provided for purposes of illustration. Other arrangements and numbers of components may be utilized without departing from the examples of the present disclosure. For example, SR latch circuit1110and1120may be implemented by SR latch circuit200ofFIG. 2, SR latch circuit300ofFIG. 3, SR latch circuit400ofFIG. 4, or a combination thereof. As another example, PFET1131and1141may be implemented as NFETs and NFET1132and1142may be implemented as PFETs.

As shown inFIG. 11, the source terminal of PFET1131may be connected to the drain terminal of PFET1112and the source terminal of PFET1113, and the drain terminal of PFET1131may be connected to first node Q of inverter storage loop1111. The source terminal of NFET1132may be connected to the drain terminal of PFET1114and the source terminal of PFET1115, and the drain terminal of NFET1132may be connected to second node QB of inverter storage loop1111. The gate terminal of PFET1131may be connected to an ENB input while the gate terminal of NFET1132may be connected to an EN input.

The source terminal of PFET1141may be connected to the drain terminal of PFET1122and the source terminal of PFET1123, and the drain terminal of PFET1141may be connected to first node Q of inverter storage loop1121. The source terminal of NFET1142may be connected to the drain terminal of PFET1124and the source terminal of PFET1125, and the drain terminal of NFET1142may be connected to second node QB of inverter storage loop1121. The gate terminal of PFET1141may be connected to an EN input while the gate terminal of NFET1142may be connected to an ENB input.

First nodes Q of inverter storage loops1111and1121may be connected to each other and second nodes QB inverter storage loops1111and1121may be connected to each other.

In operation, PFET1131and1141and NFET1132and1142act as qualifiers for SR latch circuit1110and1120's operation. For example, when ENB is asserted low and EN is asserted high, PFET1131and NFET1132are activated, thereby allowing SR latch circuit1110to operate as described above in reference toFIGS. 1-4. In contrast, PFET1141and NFET1142are deactivated, thereby deactivating SR latch circuit1120. As another example, when ENB is asserted high and EN is asserted low, PFET1131and NFET1132are deactivated, thereby deactivating SR latch circuit1110. In contrast, PFET1141and NFET1142are activated, thereby allowing SR latch circuit1120to operate as described above in reference toFIGS. 1-4.

FIG. 12is a flowchart depicting an example method1200for manufacturing a SR latch MUX circuit. Method1200may, for example, be used to manufacture SR latch MUX circuit1100ofFIG. 11. In some examples, steps of method1200may be executed substantially concurrently or in a different order than shown inFIG. 12. In some examples, method1200may include more or less steps than are shown inFIG. 12. In some examples, some of the steps of method1200may be ongoing or repeat.

At block1202, method1200may include forming first and second SR latch circuits. The first and second SR latch circuits may be any of the example SR latch circuits described inFIGS. 1-4or the SR latch circuits manufactured according to the methods illustrated inFIGS. 5-8.

At block1204, method1200may include forming a fifth PFET between the first node of the inverter storage loop of the first SR latch circuit and the first and second PFETs of the first SR latch circuit, such as PFET1131ofFIG. 11. The fifth PFET may further be connected to an ENB input.

At block1206, method1200may include forming a sixth PFET between the first node of the inverter storage loop of the second SR latch circuit and the first and second PFETs of the second SR latch circuit, such as PFET1141ofFIG. 11. The sixth PFET may further be connected to an EN input.

At block1208, method1200may include forming a first NFET between the second node of the inverter storage loop of the first SR latch circuit and the third and fourth PFETs of the first SR latch circuit, such as NFET1132ofFIG. 11. The first NFET may further be connected to an EN input.

At block1210, method1200may include forming a second NFET between the second node of the inverter storage loop of the second SR latch circuit and the third and fourth PFETs of the second SR latch circuit, such as NFET1142ofFIG. 11. The second NFET may further be connected to an ENB input.

At block1212, method1200may include connecting the first node of the inverter storage loop of the first SR latch circuit with the first node of the inverter storage loop of the second SR latch circuit.

At block1214, method1200may include connecting the second node of the inverter storage loop of the first SR latch circuit with the second node of the inverter storage loop of the second SR latch circuit.

The foregoing disclosure describes a number of example implementations of SR latch circuits. The disclosed examples may include SR latch circuits and methods for manufacturing the same. For purposes of explanation, certain examples are described with reference to the components illustrated inFIGS. 1-12. The functionality of the illustrated components may overlap, however, and may be present in a fewer or greater number of elements and components. Moreover, the disclosed examples may be implemented in various environments and are not limited to the illustrated examples.

Further, the sequence of operations described in connection withFIGS. 5-8, 10, and 12are an examples and are not intended to be limiting. Additional or fewer operations or combinations of operations may be used or may vary without departing from the scope of the disclosed examples. Furthermore, implementations consistent with the disclosed examples need not perform the sequence of operations in any particular order. Thus, the present disclosure merely sets forth possible examples of implementations, and many variations and modifications may be made to the described examples. All such modifications and variations are intended to be included within the scope of this disclosure and protected by the following claims.