Cyclic pipeline analog to digital converter with enhanced accuracy

A cyclic pipeline analog to digital converter includes a sample/hold module, a sub-analog/digital converting module, and an alternate digital/analog converting module. The sample/hold module generates a sample signal according to an analog-input signal and a residue signal. The sub-analog/digital converting module generates a first control signal and a second control signal alternately in different time according to the converting result of the sample signal. The alternate digital/analog converting module decides to receive a first reference signal and a second reference signal separately according to the first control signal and the second control signal. The alternate digital/analog converting module generates a first transfer signal according to at least the sample signal among the sample signal, the first reference signal and a first feedback signal, and generates a second transfer signal according to at least the sample signal among the sample signal, the second reference signal and a first feedback signal. The alternate digital/analog converting module generates the first feedback signal and the residue signal according to one of the first transfer signal and the second transfer signal.

BACKGROUND OF THE INVENTION

1. Field of Invention

The invention relates to a cyclic pipeline analog to digital converter, and more particularly to a cyclic pipeline analog to digital converter with highly enhanced accuracy.

2. Related Art

Analog to digital converters have been widely used in various digital electrical products, such as digital cameras, digital voice recorders, and the like. In the conventional converters, the pipeline analog to digital converter and the cyclic pipeline analog to digital converter are frequently used now.

Referring toFIG. 1, the pipeline analog to digital converter1includes a sample/hold module11, a converting module12and a delay digital correction module13. The sample/hold module11samples an input signal111and then generates a sample signal112. The converting module12includes N-th stages of sub-converting units121to129. The first stage of sub-converting unit121generates a first transfer signal121T and a first output signal121P according to the sample signal112. The second stage of sub-converting unit122generates a second transfer signal122T and a second output signal122P according to the sample signal121P. Similarly, the (N−1)-th stage of sub-converting unit12N generates an (N−1)-th transfer signal12NT and an output signal12NP according to a previous stage of output signal, wherein (N−1) is a positive integer greater than 1. The N-th stage of sub-converting unit generates an N-th transfer signal129T only according to a previous stage of output signal. Finally, the delay digital correction module13properly corrects each stage of transfer signal121T to129T and thus generates a digital signal131. However, each stage of sub-converting unit of the pipeline analog to digital converter1has similar functions, so the stages of sub-converting units may be integrated into a single stage of cyclic pipeline analog to digital converter by way of cyclic design.

As shown inFIG. 2, the conventional cyclic pipeline analog to digital converter2includes a sample/hold module21, a sub-analog/digital converting module22, a digital/analog converting module23and a delay digital correction module24.

The sample/hold module21samples an input signal211and generates a sample signal213according to the input signal211and a residual signal212. The sub-analog/digital converting module22generates a digital conversion signal221to223according to the sample signal213. The digital/analog converting module23firstly receives the sample signal213, and then decides to receive reference signals251to253according to the digital conversion signals221to223, respectively. Finally, the updated residual signal212is generated, and the sample/hold module21updates the sample signal213according to the updated residual signal212in the cyclic processing manner until the designed cyclic number of the converter2is reached. Then, the delay digital correction module24properly corrects the digital conversion signals221to223, which are generated at different time during the cyclic process, and thus generates a digital signal241.

Referring toFIG. 3, the digital/analog converting module23includes a plurality of switches231to236, a capacitor237, a capacitor238and an amplifier239. The switches234and235are simultaneously ON to make the capacitors237and238receive the sample signal213and be charged, respectively. At this time, the switches231to233and the switch236are OFF. Then, the switches234and235are simultaneously OFF to make the capacitors237and238output a transfer signal237A and a transfer signal238A to the amplifier239, respectively. Meanwhile, one of the switches231to233and the switch236are simultaneously ON to make the amplifier239and the capacitor238become a feedback circuit. At this time, the switches231to233are decided to be ON to input one of the reference signals251to253to the capacitor237and to charge the capacitor237according to the digital conversion signals221to223, respectively. The amplifier239generates the residual signal212according to the transfer signals237A and238A. At this time, the voltage relationship among the feedback signal of the amplifier239and the capacitor238, the sample signal213and one of the reference signals251to253is described by Equation 1:

Wherein, Vfeedbackis the voltage of the feedback signal, V213is the voltage of the sample signal213, V25is the voltage of one of the reference signals251to253, C237and C238are capacitances of the capacitor237and the capacitor238, respectively, and the voltage of the residual signal212is the same as the voltage Vfeedbackof the feedback signal.

The cyclic pipeline analog to digital converter2can rapidly convert an analog signal into a digital signal. As shown in Equation 1, however, the matching between the capacitor237and the capacitor238may influence the generation of the residual signal212, the residual signal212may influence the generation of the sample signal213, the sample signal213may influence the processing results of the sub-analog/digital converting module22and the digital/analog converting module23, and then influence the residual signal212in the digital/analog converting module23. Such a vicious circle deteriorates the precision of the converter2.

Consequently, it is an important subject of the invention to provide a cyclic pipeline analog to digital converter in order to ease the influence of the element matching in the digital/analog converting module, and thus enhance the precision of the analog to digital converter.

SUMMARY OF THE INVENTION

In view of the foregoing, the invention is to provide a cyclic pipeline analog to digital converter capable of easing the influence of element matching problem in the analog to digital converter.

To achieve the above, a cyclic pipeline analog to digital converter of the invention includes a sample/hold module, a sub-analog/digital converting module and an alternate digital/analog converting module. In the invention, the sample/hold module generates a sample signal according to an analog-input signal and a residue signal. The sub-analog/digital converting module generates a first control signal and a second control signal alternately in different time according to the converting result of the sample signal. The alternate digital/analog converting module decides to receive a first reference signal and a second reference signal separately according to the first control signal and the second control signal. The alternate digital/analog converting module generates a first transfer signal according to at least the sample signal among the sample signal, the first reference signal and a first feedback signal, and generates a second transfer signal according to at least the sample signal among the sample signal, the second reference signal and a first feedback signal. The alternate digital/analog converting module generates the first feedback signal and the residue signal according to one of the first transfer signal and the second transfer signal.

As mentioned above, in the cyclic pipeline analog to digital converter of the invention, the sub-analog/digital converting module alternately generates the first control signal and the second control signal at different time, so the alternate digital/analog converting module can alternately generate the residual signal according to the first control signal and the second control signal. Thus, the influence of the element matching in the digital/analog converting module may be eased such that the analog to digital converting result may be correctly generated.

DETAILED DESCRIPTION OF THE INVENTION

A cyclic pipeline analog to digital converter of the invention includes a sample/hold module, a sub-analog/digital converting module and an alternate digital/analog converting module. In the invention, the sample/hold module generates a sample signal according to an analog-input signal and a residue signal. The sub-analog/digital converting module generates a first control signal and a second control signal alternately in different time according to the converting result of the sample signal. The alternate digital/analog converting module decides to receive a first reference signal and a second reference signal separately according to the first control signal and the second control signal. The alternate digital/analog converting module generates a first transfer signal according to at least the sample signal among the sample signal, the first reference signal and a first feedback signal, and generates a second transfer signal according to at least the sample signal among the sample signal, the second reference signal and a first feedback signal. The alternate digital/analog converting module generates the first feedback signal and the residue signal according to one of the first transfer signal and the second transfer signal.

Referring toFIG. 4, a cyclic pipeline analog to digital converter3according to the embodiment of the invention includes a sample/hold module31, a sub-analog/digital converting module32and an alternate digital/analog converting module4.

In this embodiment, the sample/hold module31generates a sample signal Vshaccording to an analog-input signal Vinand a residual signal Vresidue. The sub-analog/digital converting module32generates first control signals Sc11to Sc13and second control signals Sc21to Sc23alternately according to a digital converting result at different time of the sample signal Vsh.

The alternate digital/analog converting module4decides to receive first reference signals Vref11to Vref13and second reference signals Vref21to Vref23according to the first control signals Sc11to Sc13and the second control signals Sc21to Sc23, generates a first transfer signal St1according to at least the sample signal Vshamong the sample signal Vsh, the first reference signals Vref11to Vref13and a first feedback signal Sfb1, generates a second transfer signal St2according to at least the sample signal Vshamong the sample signal Vsh, the second reference signals Vref11to Vref13and the first feedback signal Sfb1, and further generates the first feedback signal Sfb1and the residual signal Vresidueaccording to one of the first transfer signal St1and the second transfer signal St2.

In other words, the alternate digital/analog converting module4can generate the first transfer signal St1at first time according to the sample signal Vsh, respectively receive the second reference signals Vref21to Vref23according to the second control signals Sc21to Sc23, generate the second transfer signal St2according to one of the second reference signals Vref21to Vref23and the sample signal Vsh, generate the first feedback signal Sfb1and the residual signal Vresidueaccording to the first transfer signal St1and the second transfer signal St2, and further generate the first transfer signal St1according to first feedback signal Sfb1.

At the second time, the alternate digital/analog converting module4generates the second transfer signal St2according to the sample signal Vsh, receives the first reference signals Vref11to Vref13according to the first control signals Sc11to Sc13, respectively, generates the first transfer signal St1according to one of the first reference signals Vref11to Vref13and the sample signal Vsh, generates the first feedback signal Sfb1and the residual signal Vresidueaccording to the first transfer signal St1and the second transfer signal St2, and further generates the second transfer signal St2according to the first feedback signal Sfb1.

In this embodiment, the alternate digital/analog converting module4includes a first converting unit41, a second converting unit42and an amplifying unit43. The first reference signal Vref11and the second reference signal Vref21may be coupled to the same positive power, the first reference signal Vref12and the second reference signal Vref22may be coupled to the same negative power, and the first reference signal Vref13and the second reference signal Vref23may be coupled to the same grounding power.

The first converting unit41decides to receive the first reference signals Vref13to Vref13according to the first control signals Sc11to Sc13, respectively, and generates the first transfer signal St1according to at least the sample signal Vshamong the sample signal Vsh, the first reference signals Vref11to Vref13and the first feedback signal Sfb1.

In addition, the second converting unit42decides to receive the second reference signals Vref21to Vref23according to the second control signal Sc21to Sc23, respectively, and generates the second transfer signal St2according to at least the sample signal Vshamong the sample signal Vsh, the second reference signals Vref21to Vref23and the first feedback signal Sfb1.

Furthermore, the amplifying unit43generates the first feedback signal Sfb1and the residual signal Vresidueaccording to one of the first transfer signal St1and the second transfer signal St2. Herein, the first feedback signal Sfb1is inputted to one of the first converting unit41and the second converting unit42.

As shown inFIG. 5, the first converting unit41of this embodiment includes a capacitor411, a sampling switch412, a feedback switch413and a plurality of capacitor switches414to416. The sampling switch412controls the capacitor411to receive the sample signal Vsh. The capacitor switches414to416decides whether the capacitor411has to receive the first reference signals Vref11to Vref13according to the first control signals Sc11to Sc13, respectively. The feedback switch413controls the capacitor411to receive the feedback signal Sfb1. The capacitor411generates the first transfer signal St1according to at least the sample signal Vshamong the sample signal Vsh, the first reference signals Vref11to Vref13and the first feedback signal Sfb1. The capacitor411coupled to the amplifying unit43outputs the first transfer signal St1to the amplifying unit43.

In this embodiment, the second converting unit42may include a capacitor421, a sampling switch422, a feedback switch423and a plurality of capacitor switches424to426. The second sampling switch422controls the second capacitor421to receive the sample signal Vsh. The capacitor switches424to426decides whether the capacitor421has to receive the second reference signals Vref21to Vref23according to the second control signals Sc21to Sc23, respectively. The feedback switch423controls the capacitor421to receive the first feedback signal Sfb1. The capacitor421generates the second transfer signal St2according to at least the sample signal Sfb1among the sample signal Vsh, the second reference signals Vref1to Vref23and the first feedback signal Sfb1. The capacitor421electrically connected to the amplifying unit43outputs the second transfer signal St2to the amplifying unit43.

In this embodiment, the amplifying unit43may include an amplifier431and a grounding switch432. The amplifier431generates the first feedback signal Sfb1and the residual signal Vresidueaccording to one of the first transfer signal St1and the second transfer signal St2, and the grounding switch432decides to ground the capacitor411and the capacitor421.

Referring again toFIGS. 4 and 5, the cyclic pipeline analog to digital converter3of this embodiment further includes a clock generating module33and a delay digital correction module34.

The clock generating module33generates an input clock signal Clkin, a grounding clock signal Clkground, a first clock signal Clk1and a second clock signal Clk2. In this case, the first clock signal Clk1and the second clock signal Clk2are enabled at different time.

The sub-analog/digital converting module32generates a digital conversion signal Vdtaccording to the sample signal Vsh, and further generates the first control signals Sc11to Sc13according to the first clock signal Clk1and the digital conversion signal Vdt, or generates the second control signals Sc21to Sc23according to the second clock signal Clk2and the digital conversion signal Vdt.

The delay digital correction module34properly corrects the digital conversion signal Vdt, which is generated at different time during the cyclic process, and thus generates a digital signal Vout.

As shown inFIGS. 5 and 6, when the grounding clock signal Clkgroundis enabled, the grounding switch432in the alternate digital/analog converting module4is ON such that the capacitor411and the capacitor421are grounded.

When the input clock signal Clkinis enabled, the sampling switch412and the sampling switch422in the alternate digital/analog converting module4enable the capacitor411and the capacitor421to receive the sample signal Vshand be charged. On the contrary, when the input clock signal Clkinis not enabled, the first transfer signal St1and the second transfer signal St2, which are respectively generated by the capacitor411and the capacitor421, discharge the amplifier431.

At this time, however, the first clock signal Clk1or the second clock signal Clk2is enabled. If the first clock signal Clk1is enabled, the feedback switch423is ON to make the capacitor421receive the first feedback signal Sfb1. Meanwhile, one of the first control signals Sc11to Sc13is enabled due to the first clock signal Clk1. Thus, one of the capacitor switches414to416is ON to make the capacitor411receive one of the first reference signals Vref11to Vref13. At this time, the voltage relationship among the first feedback signal Sfb1, one of the first reference signals Vref11to Vref13, and the sample signal Vshis described by Equation 2:

Wherein, Vsfb1is the voltage of the feedback signal Sfb1, Vvshis the voltage of the sample signal Vsh, Vref1is one of the voltages of the reference signals Vref11to Vref13, C411and C421are respectively the capacitances of the capacitor411and capacitor421, and the voltage of the residual signal Vresidueis the same as the voltage Vsfb1of the feedback signal Sfb1.

On the other hand, if the second clock signal Clk2is enabled, the feedback switch413is ON to make the capacitor411receive the first feedback signal Sfb1. Meanwhile, one of the second control signals Sc21to Sc23is enabled due to the second clock signal Clk2, so one of the capacitor switches424to426is ON to make the capacitor421receive one of the second reference signals Vref21to Vref23. At this time, the voltage relationship among the first feedback signal Sfb1, one of the second reference signals Vref21to Vref23, and the sample signal Vshis described by Equation 3:

Wherein, Vsfb1is the voltage of the feedback signal Sfb1, Vvshis the voltage of the sample signal Vsh, Vref2is the voltage of one of the reference signals Vref21to Vref23, C411and C421are respectively the capacitances of the capacitor411and the capacitor421, and the voltage of the residual signal Vresidueis the same as the voltage Vsfb1of the feedback signal Sfb1.

Comparing the Equations 1 to 3, the alternate digital/analog converting module4of this embodiment enables the first feedback signal Sfb1to be alternately fed back to one of the first converting unit41and the second converting unit42(i.e., to be alternately fed back to the capacitor411and the capacitor421), and enables one of the first reference signals Vref11to Vref13and one of the second reference signals Vref21to Vref23to be inputted to the capacitor411and capacitor421at different time according to the first control signals Sc11to Sc13and the second control signals Sc21to Sc23, respectively. Thus, the voltage of the residual signal Vresiduecan be generated at different time according to the matching of different first reference signals Vref11to Vref13, different second reference signals Vref21to Vref23, and different capacitors, so as to the problem of matching between the capacitor411and the capacitor421may be eased.

As shown inFIG. 7, the sample/hold module31of this embodiment generates a sample signal Vsh+and a sample signal Vsh−according to an analog-input signal Vin+, an analog-input signal Vin−, a residual signal Vresidue+and a residual signal Vresidue−.

The sub-analog/digital converting module32respectively generates a plurality of first control signals Sc11to Sc13according to the digital conversion signals Vdt1to Vdt3and the first clock signal Clk1, wherein the digital conversion signals Vdt1to Vdt3are generated by the sample signal Vsh+and the sample signal Vsh−, according to the first clock signal Clk1and the digital conversion signals Vdt1to Vdt3, and respectively generates a plurality of second control signals Sc21to Sc23according to the second clock signal Clk2and the digital conversion signals Vdt1to Vdt3.

The delay digital correction module34properly corrects the digital conversion signals Vdt1to Vdt3generated by the converter3at different time during the cyclic process and thus generates the digital signal Vout.

In detail, the alternate digital/analog converting module4of this embodiment includes a first converting unit41, a second converting unit42, an amplifying unit43, a third converting unit44and a fourth converting unit45, as shown inFIG. 8.

The first converting unit41decides to receive a first reference signal Vref1+and a first reference signal Vref1−according to the first control signal Sc11and the first control signal Sc12, respectively, and generates the first transfer signal St1according to at least the sample signal Vsh+among the sample signal Vsh+, the first reference signal Vref1+, the first reference signal Vref1−and the first feedback signal Sfb1.

The second converting unit42decides to receive a second reference signal Vref2+and a second reference signal Vref2−according to the second control signal Sc21and the second control signal Sc22, respectively, and generates the second transfer signal St2according to at least the sample signal Vsh+among the sample signal Vsh+, the second reference signal Vref2+, the second reference signal Vref2−and the first feedback signal Sfb1.

The third converting unit44decides to receive a third reference signal Vref3−and a third reference signal Vref3+according to the first control signal Sc11and the first control signal Sc12, respectively, and generates a third transfer signal St3according to at least the sample signal Vsh−among the sample signal Vsh−, the third reference signal Vref3+, the third reference signal Vref3−and a second feedback signal Sfb2.

The fourth converting unit45decides to receive a fourth reference signal Vref4−and a fourth reference signal Vref4+according to the second control signal Sc21and the second control signal Sc22, respectively, and generates a fourth transfer signal St4according to at least the sample signal Vsh−among the sample signal Vsh−, the fourth reference signal Vref4+, the fourth reference signal Vref4−and the second feedback signal Sfb2.

The amplifying unit43generates the first feedback signal Sfb1according to one of the first transfer signal St1and the second transfer signal St2, generates the second feedback signal Sfb2according to one of the third transfer signal St3and the fourth transfer signal St4, and generates the residual signal Vresidue+and the residual signal Vresidue−according to the first feedback signal Sfb1and the second feedback signal Sfb2, respectively. In this case, the second feedback signal Sfb2is inputted to one of the third converting unit44and the fourth converting unit45.

In addition, the first converting unit41of this embodiment may include a capacitor411, a sampling switch412, a feedback switch413and a plurality of capacitor switches415and416. The second converting unit42may include a capacitor421, a sampling switch422, a feedback switch423and a plurality of capacitor switches425and426. The third converting unit44may include a capacitor441, a sampling switch442, a feedback switch443and a plurality of capacitor switches444to446. The fourth converting unit45may include a capacitor451, a sampling switch452, a feedback switch453and a plurality of capacitor switches454to456.

The amplifying unit43may include a differential amplifier433and a transistor switch434. The differential amplifier433generates the second feedback signal Sfb2according to one of the third transfer signal St3and the fourth transfer signal St4, and generates the residual signal Vresidue+and the residual signal Vresidue−according to the first feedback signal Sfb1and the second feedback signal Sfb2, respectively. Herein, the second feedback signal Sfb2is inputted to one of the third converting unit44and the fourth converting unit45.

As shown inFIGS. 6 and 8, when the grounding clock signal Clkgroundis enabled, the transistor switch434of the alternate digital/analog converting module4enables the capacitor411, the capacitor421, the capacitor441and the capacitor451to be grounded.

When the input clock signal Clkinis enabled, the sampling switch412and the sampling switch422of the alternate digital/analog converting module4are ON to make the capacitor411and the capacitor421receive the sample signal Vsh+, and the sampling switch442and the sampling switch452are ON to make the capacitor441and the capacitor451receive the sample signal Vsh−.

When the input clock signal Clkinis not enabled, the sampling switch412, the sampling switch422, the sampling switch442and the sampling switch452are OFF. At this time, however, one of the first clock signal Clk1and the second clock signal Clk2is enabled.

If the first clock signal Clk1is enabled, the feedback switch423is ON to make the capacitor421receive the first feedback signal Sfb1, and the feedback switch453is ON to make the capacitor451receive the second feedback signal Sfb2. Meanwhile, if the first control signal Sc11is enabled, the capacitor switch415and the capacitor switch445are ON to make the capacitor411and the capacitor441receive the first reference signal Vref1+and the third reference signal Vref3−, respectively. In addition, if the first control signal Sc12is enabled, the capacitor switch416and the capacitor switch446are ON to make the capacitor411and the capacitor441receive the first reference signal Vref1−and the third reference signal Vref3+, respectively. Furthermore, if the first control signal Sc13is enabled, the capacitor411is directly electrically connected to the capacitor441.

On the other hand, if the second clock signal Clk2is enabled, the feedback switch413is ON to make the capacitor411receive the first feedback signal Sfb1, and the feedback switch443is ON to make the capacitor441receive the second feedback signal Sfb2. Meanwhile, if the second control signal Sc21is enabled, the capacitor switch425and the capacitor switch455are ON to make the capacitor421and the capacitor451receive the second reference signal Vref2+and the fourth reference signal Vref4−, respectively. In addition, if the second control signal Sc22is enabled, the capacitor switch426and the capacitor switch456are ON to make the capacitor421and the capacitor451receive the second reference signal Vref2−and the fourth reference signal Vref4+, respectively. Furthermore, if the second control signal Sc23is enabled, the capacitor421is directly electrically connected to the capacitor451.

In addition, the first reference signal Vref1+, the second reference signal Vref2+, the third reference signal Vref3+and the fourth reference signal Vref4+may be generated according to the same reference signal, or the same signal coupled to each converting unit. Similarly, the first reference signal Vref1−, the second reference signal Vref2−, the third reference signal Vref3−and the fourth reference signal Vref4−may be generated according to the same reference signal, or the same signal coupled to each converting unit.

In this embodiment, the first converting unit41and the third converting unit44are symmetrical circuits, and the second converting unit42and the fourth converting unit45are symmetrical circuits. The first converting unit41, the second converting unit42, the third converting unit44and the fourth converting unit45are electrically connected to the differential amplifier433. Thus, the alternate digital/analog converting module4can ease the influence of the common mode noise.

In summary, in the cyclic pipeline analog to digital converter of the invention, the sub-analog/digital converting module alternately generates the first control signal and the second control signal at different time, so the alternate digital/analog converting module can alternately generate the residual signal according to the first control signal and the second control signal. Thus, the influence of the element matching in the digital/analog converting module may be eased such that the analog to digital converting result may be correctly generated.