Circuit structure having islands between source and drain

A circuit structure includes a substrate, an unintentionally doped gallium nitride (UID GaN) layer over the substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. A number of islands are over the donor-supply layer between the gate structure and the drain. The gate structure disposed between the drain and the source. The gate structure is adjoins at least a portion of one of the islands and/or partially disposed over at least a portion of at least one of the islands.

TECHNICAL FIELD

This disclosure relates generally to semiconductor circuit manufacturing processes and, more particularly, to a group-III group-V (III-V) compound semiconductor based transistor.

BACKGROUND

Group-III group-V compound semiconductors (often referred to as III-V compound semiconductors), such as gallium nitride (GaN) and its related alloys, have been under intense research in recent years due to their promising applications in power electronic and optoelectronic devices. The large band gap and high electron saturation velocity of many III-V compound semiconductors also make them excellent candidates for applications in high temperature, high voltage, and high-speed power electronics. Particular examples of potential electronic devices employing III-V compound semiconductors include high electron mobility transistor (HEMT) and other heterojunction bipolar transistors.

During operation, a HEMT forms a large surface electric field around the gate edge, which affects the depletion region curve between the gate structure and the drain. While large electric field is one of the benefits of HEMT for use in power applications, the distribution of the depletion region during operation can negatively affect the breakdown voltage for the device. When negative bias is applied to the gate of the HEMT, depletion region curve is formed directly under the gate and causes high surface electric field around the gate edge. The high electric field concentration around the gate reduces breakdown voltage for the device.

In order to improve breakdown voltage (i.e., to increase it), a metallic field plate is sometimes added over or next to the gate structure over the passivation layer between the gate structure and the drain. The field plate modulates the surface electric field distribution reducing the peak electric field, and thus increases the breakdown voltage. However, new structures with high breakdown voltage for III-V compound semiconductor based transistors and methods for forming them continue to be sought.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative of specific ways to make and use the disclosed embodiments and do not limit the scope of the disclosure.

A novel structure for group-III to group-V (referred to as III-V hereinafter) semiconductor based transistors and methods for forming the structures are provided. Throughout the description, the term “III-V compound semiconductor” refers to compound semiconductor materials comprising at least one group III element and one group-V element. The term “III-N compound semiconductor” refers to a III-V compound semiconductor in which the group V element is nitrogen. Example stages of manufacturing an illustrative embodiment of the present disclosure are discussed. Those skilled in the art will recognize that other manufacturing steps may take place before or after the described stages in order to produce a complete device. Other stages of manufacturing that may substitute some of the example stages may be discussed. Those skilled in the art will recognize that other substitute stages or procedures may be used. Throughout the various views and illustrative embodiments of the present disclosure, like reference numbers are used to designate like elements.

The present disclosure provides a structure and a method to form III-V compound semiconductor based transistors having high breakdown voltage.FIG. 1Ashows an example power transistor device100according to various embodiments of the present disclosure. The power transistor100may be a high-electron mobility transistor (HEMT). The HEMT includes a substrate101, a bulk layer GaN layer109over the substrate101, an active layer111over the bulk GaN layer109, and source115, drain117, and gate119over the active layer111. An interface of active layer111and bulk GaN layer109is a high-electron mobility region113, also known as a channel layer. In a drift region107between the gate119and the drain117, a number of islands103and105are formed over the active layer. Each of these transistor elements are discussed further below together with methods for forming them.

FIG. 1Bshows a flowchart150of a method of making the power transistor device100ofFIG. 1A. In operation151, a substrate101is provided, as shown inFIG. 1A. Although silicon wafers are used, other suitable substrates include silicon carbide and sapphire. A number of layers are grown over the substrate101using an epitaxial process. The layers may include a nucleation layer of aluminum nitride, a buffer, and a bulk gallium nitride layer109grown over the buffer layer. The bulk gallium nitride layer109is a channel layer for the power transistor device100.

The bulk layer of undoped gallium nitride109is epitaxially grown over the substrate, which may include a buffer layer (not shown) in operation153ofFIG. 1B. The bulk layer of gallium nitride109does not include any dopant, but may include contaminants or impurities that are incorporated in the film unintentionally. The bulk layer of gallium nitride may be referred to as unintentionally doped gallium nitride (UID GaN) layer. The UID GaN layer is about 0.5 microns to about 5 micron thick. The bulk GaN layer is grown under high temperature conditions. The process may be metal organic CVD (MOCVD), metal organic vapor phase epitaxy (MOVPE), plasma enhanced CVD (PECVD), remote plasma enhanced CVD (RP-CVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), chloride vapor-phase epitaxy (Cl-VPE), and liquid phase epitaxy (LPE). The metal organic vapor phase epitaxy (MOVPE) process uses gallium-containing precursor and nitrogen-containing precursor. The gallium-containing precursor includes trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemical. The nitrogen-containing precursor includes ammonia (NH3), trimethylalaluminum (TMA), phenyl hydrazine, or other suitable chemical.

FIG. 1Ashows an active layer111on top of the bulk GaN layer109. The active layer111, also referred to as donor-supply layer, is grown on the channel layer109in operation155ofFIG. 1B. An interface is defined between the channel layer109and the donor-supply layer111. A carrier channel113of two-dimensional electron gas (2-DEG) is located at the interface, which is discussed in further detail below. In at least one embodiment, the donor-supply111refers to an aluminum gallium nitride (AlGaN) layer (also referred to as the AlGaN layer111). The AlGaN layer111has a formula of AlxGa(1-x)N. It has a thickness in a range from about 5 nanometers to about 50 nanometers, wherein x varies between about between about 10% to 100%. In other embodiments, the donor-supply layer111may include an AlGaAs layer or AlInP layer.

Referring back toFIG. 1A, a band gap discontinuity exists between the AlGaN layer111and the GaN layer109. The electrons from a piezoelectric effect in the AlGaN layer111drop into the GaN layer109, creating a very thin layer113of highly mobile conducting electrons in the GaN layer109. This thin layer113is referred to as a two-dimensional electron gas (2-DEG), forming a carrier channel (also referred to as the carrier channel113). The thin layer113of 2-DEG is located at an interface of the AlGaN layer111and the GaN layer109. Thus, the carrier channel has high electron mobility because the GaN layer109is undoped or unintentionally doped, and the electrons can move freely without collision or substantially reduced collision with the impurities.

According to various embodiments of the present disclosure, a gate structure119partially overlaps one or more islands103formed over the AlGaN layer111between the gate structure119and a drain117or at least adjoins at least a portion of one of the islands. The region between the gate structure119and the drain117is the drift region107on which the islands103and105are formed. The islands103and105are formed before the gate structure119but may be formed before or after a source115and drain117.

In certain embodiments, a portion of the gate structure119overlaps a part of the one or more islands103, as shown inFIG. 1A. In other embodiments, the gate structure119covers the entirety of the one or more islands103while a portion of the bottom of the gate structure119does not contact the one or more islands. In other words, the gate structure119, the one or more islands103, or both can partially overlap the other. In still other embodiments, the gate structure119adjoins a portion of one or more of the islands without overlapping each other.

According to certain embodiments, the islands103and105are p-type doped islands. Referring toFIG. 1B, in operation157a p-type doped GaN film is grown epitaxially over the AlGaN layer111. The islands may be p-type doped gallium nitride or aluminum gallium nitride islands. The p-type doping may occur by adding a dopant during the epitaxial growth process. P-type dopant candidates include carbon, iron, magnesium, calcium, beryllium, and zinc. The p-type doping may also be performed by other processes such as ion implantation; however, care must be taken not to incorporate the dopant in underlying layers, which may adversely affect the electrical property of the transistor. The dopant concentration may be about from 1E15/cm3to 1E17/cm3.

In other examples, the islands103and105may also be deposited, for example, using a metal chemical vapor deposition (MCVD) process or a sputtering process, and defined on the AlGaN layer111. The islands may be p-type doped nickel oxide or zinc oxide. The p-type doping may occur by adding a dopant during the deposition process. P-type dopant candidates include carbon, iron, magnesium, calcium, beryllium, and zinc. The p-type doping may also be performed by other processes such as ion implantation; however, care must be taken not to incorporate the dopant in underlying layers, which may adversely affect the electrical property of the transistor. Note that while the dopant candidates may be the same for the epitaxially grown islands and the deposited islands, but the chemicals used may be different. The dopant concentration may be from about 1E15/cm3to 1E17/cm3.

Referring toFIG. 1B, the p-type doped film is deposited in operation157. Thereafter, a photolithographic process is employed to protect the island portions of the p-type doped film. The p-type doped film is etched into islands in operation159. In at least one embodiment, a plasma etch process is used to removed unwanted portions of the p-type doped film. In one example, the plasma etch process is a reactive ion etch process employing chlorine containing etchants. In some embodiments, care is taken to not overetch into the donor-supply layer111.

The light p-type doping of the islands creates p-n junctions at the AlGaN layer111surface. During operation, the p-n junctions modulates the surface electric field and reduce effective peak electric field at the gate edge. The lower peak electric field results in a higher breakdown voltage.

According to some embodiments, the islands103and105are formed of Schottky materials, such as titanium, tungsten, titanium nitride, or titanium tungsten. Other Schottky materials may include nickel, gold, or copper. These materials may be deposited using physical vapor deposition (PVD) processes such as sputtering or electron gun, or using MCVD processes. The materials may be deposited first and then unwanted parts are defined and etched away or be deposited over defined film such as a photoresist and then unwanted parts lifted off with the defined film.

A thickness of the islands103and105may be about 3 nm to about 100 nm. In some cases, the thickness of the islands103and105may be about 10 nm or be about 20 nm. The thickness of the islands103and105depends on the electrical properties and the physical dimensions of the semiconductor structure100. For example, thin islands103and105may be used when the bulk gallium nitride layer109is thick and the drift region107is very large as compared to the region between the gate structure119and the source115. In these circumstances, the breakdown voltage is naturally high and little modulation of the surface electric field may be sufficient for reaching a predetermined breakdown voltage. On the other hand, when the bulk gallium nitride layer109is thin or when the bulk layer is of a material with a low critical electrical field (Ec) value, the island103and105may be thicker. During operation when the drain is subjected to a high voltage, the depletion region formed may extend past a thin gallium nitride layer109and interact with the underlying substrate. Similar rationale applies when the distance between the gate structure119and the drain117is small. During operation when the drain is subjected to a high voltage, the depletion region curve may extend past a short drift region107. Thus thicker islands103and105may be used to effectively modulate the surface electrical field. According to various embodiments, island thickness between about 3 nm to 100 nm and a drift region that is at least half the size of the device, i.e., half of the donor-supply layer, form a HEMT with good breakdown voltage at or over 600 volts.

The source115, drain117, and gate structures119are formed in operation161ofFIG. 1B. The source feature115and a drain feature117are disposed on the AlGaN layer111and configured to electrically connect to the carrier channel113. Each of the source feature115and the drain feature117comprises a corresponding intermetallic compound. The intermetallic compound is at least partially embedded in the AlGaN layer111and may be embedded in a top portion of the GaN layer109. In one example, the intermetallic compound comprises Al, Ti, or Cu. In another example, the intermetallic compound comprises AlN, TiN, Al3Ti or AlTi1N.

The intermetallic compound may be formed by constructing a patterned metal layer in a recess of the AlGaN layer111. Then, a thermal annealing process may be applied to the patterned metal layer such that the metal layer, the AlGaN layer111and the GaN layer109react to form the intermetallic compound. The intermetallic compound contacts the carrier channel113located at the interface of the AlGaN layer111and the GaN layer109. Due to the formation of the recess in AlGaN layer111, the metal elements in the intermetallic compound may diffuse deeper into the AlGaN layer111and the GaN layer109. The intermetallic compound may improve electrical connection and form ohmic contacts between the source/drain features115or117and the carrier channel113. In one example, the intermetallic compound is formed in the recess of the AlGaN layer111thereby the intermetallic compound has a non-flat top surface. In another example, intermetallic compound overlies a portion of the AlGaN layer111.

The semiconductor structure100also includes a gate structure119disposed on the AlGaN layer111between the source115and drain117features. The gate119includes a conductive material layer which functions as the gate electrode configured for voltage bias and electrical coupling with the carrier channel113. In various examples, the conductive material layer may include a refractory metal or its compounds, e.g., tungsten (W), titanium nitride (TiN) and tantalum (Ta). Other commonly used metals in the conductive material layer include nickel (Ni) and gold (Au). The gate structure may include one or many layers.

FIGS. 2A to 2Dare example top views of various islands in accordance with various embodiments of the present disclosure.FIG. 2Ashows a total of four islands203and205in the drift region, between source215and drain217, with island203being partially covered by the gate219. The edge of island203covered by the gate structure219is shown as a dotted line. As shown inFIG. 2A, three islands205are dispersed between the island203and drain217, although fewer or more islands may be used.

InFIG. 2A, the first island203that is partially under the gate structure219is the largest island. Islands205have the same size. Each island has a width. Island203has a width221. Islands205have widths223. The distance between island203and the adjacent island205is distance222. The distances between the islands205are distances224. Finally, a distance between the drain217and adjacent island205is distance225. Adequate distance225must be maintained to ensure isolation of the drain217from an adjacent island205.

According to certain embodiments, a largest of the islands203and205is partially disposed under the gate structure119. While not required for the present disclosure to reduce breakdown voltage of the transistor100, the island material has the largest effect to modulate surface electric field at the gate edge. Thus, embodiments having larger islands at least partially under the gate structure119results in greater reductions of breakdown voltages.

In some embodiments, the islands203and205are the same sizes and may be equally spaced. In some examples, the widths of adjacent island and drift region207not occupied by an island may be between about 3:1 to about 1:3. For example, a ratio of distance221to distance222may be about 3:1, while a ratio of distance222to distance223may be about 1:2. A ratio of distance223to distance224may be about 1:1.

In other embodiments, a sum of total island widths may be compared to the total drift region207width. A total island width may be about 40% to about 75% of the total drift region207width. In other words a sum of widths221and223smay be compared to the total width of the drift region207.

In yet other embodiments, a total island area is compared to the drift region area. InFIG. 2A, the features all have the same length so that the widths are a proxy for area. However, the islands need not have same lengths, shapes or sizes. A total island area may be about 40% to about 75% of the total drift region area.

FIG. 2Bshows checkered pattern islands203and205as another example. The islands203are again larger than islands205(width221is larger than width223), but not all of the gate structure edge overlaps an island203. This design may be used to smooth the surface electric field. A ratio of an island and adjacent drift region (such as221/222or223/222) that is not occupied by an island may be about 3:1 to about 1:3. Thus, the checkers need not be the same size. As shown inFIG. 2B, the ratio is about 1:1.

FIG. 2Cshows trapezoidal islands203and205as another example. The trapezoidal islands203and205have a shorter width, such as width220, and a longer width, such as width221. The gate structure edge overlaps a portion of the trapezoidal island203.

FIG. 2Dshows an irregular island distribution. The various islands229and231are all differently shaped and may be irregularly shaped. In this example the overall island area, shown as cross hatched regions, is compared to the total drift region area. A total island area may be about 40% to about 75% of the total drift region area. Another comparison is the total island area, shown as cross hatched regions, to the drift region that is not occupied by an island, shown as hatched regions. This ratio may be about 30% to about 300%.

FIG. 2Eshows yet another example where the islands203and205have different shapes. Island203adjoins the gate structure219without overlapping each other. In other words, no part of island203is under a portion of the gate structure219. Islands203and205are located within drift region207, which starts at the gate structure edge. With non-overlapping embodiments, the width221of the adjoining island203may be larger to have the same effect as the “disposed under” island203ofFIGS. 2A to 2D.

The various islands shown inFIGS. 2A to 2Dare merely examples. The islands may be polygons, such as quadrilaterals such as those inFIGS. 2A,2B, and2C. The islands may have more than four sides or may be circular or irregular, such as those inFIG. 2D.

FIGS. 3A to 3Care cross-sectional views of a HEMT structure and depletion regions formed during various operations for a III-V semiconductor material based transistor without the islands of the present disclosure.FIG. 3Ashows a small depletion region301under the gate structure311when the gate voltage is greater than the threshold voltage (a negative value), with no bias applied to the drain313. The device ofFIG. 3Ais in an on state (normally on) and a current flows along the 2-DEG carrier channel315.

InFIG. 3B, a gate voltage less than the threshold voltage is applied, with no bias at the drain313, such that a larger depletion region303is formed. The depletion region303crosses the 2-DEG carrier channel boundary so that no current flows through the 2-DEG carrier channel315. The device ofFIG. 3Bis in an off state.

FIG. 3Cshows a device with a gate voltage less than the threshold voltage and bias at the drain so that the drain voltage is greater than zero. A much larger depletion region305is formed, the size of which correspond to the bias at the drain313. When the drain313bias is sufficiently large, for example, larger than the breakdown voltage of the device, a large enough electric field is formed that is greater than a critical electrical field (Ec) of the material, either the bulk layer317or the donor-supply layer319. The device can breakdown or pop and be rendered inoperable.

FIGS. 4A to 4Care cross-sectional views of a HEMT structure and depletion regions formed during various operations for a III-V semiconductor material based transistor with the islands of the present disclosure.FIG. 4Ashows a small depletion region401under the gate structure411when the gate voltage is greater than the threshold voltage (a negative value), with no bias applied to the drain413. Small depletion regions402are also shown under the islands421. Note that the depletion region401under the gate411incorporates the effect of island423. The device ofFIG. 4Ais in an on state (normally on) and a current flows along the 2-DEG carrier channel415because none of the depletion regions401and402crosses the 2-DEG carrier channel415.

InFIG. 4A, a gate voltage less than the threshold voltage is applied, with no bias at the drain313, such that a larger depletion region403and smaller depletion regions402are formed. The depletion region403cross the 2-DEG carrier channel boundary so that no current flows through the 2-DEG carrier channel415. The device ofFIG. 4Bis in an off state.

FIG. 4Cshows a device with a gate voltage less than the threshold voltage and bias at the drain so that the drain voltage is greater than zero. A much larger depletion region405is formed combining the smaller depletion regions under the islands421. In some embodiments, depletion region405extends into the bulk layer417through the 2-DEG carrier channel415and the donor-supply layer419. The size of depletion region405corresponds to the bias at the drain413. For the same bias at the drain413, the maximum depth of the depletion region405is smaller than that of depletion region305fromFIG. 3Cbecause the depletion region405is more distributed across the drift region.

FIG. 5is a plot of simulated peak surface electric field as a function of distance on the HEMT structures in accordance with various embodiments of the present disclosure. Electric field in volts per centimeter is plotted against a distance along line across the HEMT. The simulation models a gate voltage of −5 volts and drain bias of 600 volts. The peak corresponds to the gate structure edge closest to the drain. Line501is a simulated result for a HEMT without the islands as disclosed herein. The peak electric field for line501is about 6E6 V/cm. Line503is a simulated result for a HEMT having three islands between the gate structure and the drain. The peak electric field for line503is about 5E6 V/cm, for a reduction of about 20%. This simulated result shows that the island structures disclosed herein do indeed reduce peak surface electric field in the HEMT. While the peak electric field value would vary depending on the structure modeled in the simulation, the relative effect of the islands is clear.

The embodiments of the present disclosure may have other variations. For example, the islands may include more than one material, such as a layer of nickel oxide over a layer of gallium nitride. Certain embodiments of the present disclosure have several advantageous features. The use of various doping species allows fine-tuning of the islands, and hence the breakdown voltage, while minimizing adverse effects to other electrical properties, such as maximum forward current or leakage current.

In one aspect, the present disclosure pertains to a circuit structure having a substrate, an unintentionally doped gallium nitride (UID GaN) layer over the substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer, and a plurality of islands over the donor-supply layer between the gate structure and the drain. The gate structure disposed between the drain and the source. The gate structure is partially disposed over at least a portion of at least one of the plurality of islands. The islands are p-type doped islands or Schottky material islands.

In another aspect, the present disclosure pertains to a circuit structure having a substrate, a III-V compound semiconductors layer over the substrate, a donor-supply layer over the III-V compound semiconductors layer, a plurality of p-type doped islands over a drift portion of the donor-supply layer, a gate structure adjoining at least portion of one of the plurality of p-type doped islands at an edge of the drift portion, a drain over the donor-supply layer at an opposite edge of the drift portion from the gate structure, the drain being isolated from the plurality of p-type doped islands, and a source over the donor-supply layer, the gate structure being positioned between the source and the drain away from the drift portion and closer to the gate structure than the drain. The drift portion region of the donor-supply layer occupies at least 50% of the donor-supply layer.

In yet another aspect, the present disclosure pertains to a method for making the circuit structure. The method includes providing a substrate, epitaxially growing an UID GaN layer over the substrate, epitaxially growing an undoped AlGaN layer over the UID GaN layer, forming one or more islands over a portion of the undoped AlGaN layer, and forming source/drain and gate structure. The islands may be formed by epitaxially growing a p-type doped film and etching to a pattern, depositing suitable p-type material and etching to a pattern, or depositing suitable Schottky metal and etching to a pattern.