Method for manufacturing a contact structure used to electrically connect a semiconductor device

A method for manufacturing contact structure includes the steps of: providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device includes a gate structure and a source/drain region; forming a patterned mask layer with a stripe hole on the substrate, and concurrently forming a stripe-shaped mask layer on the substrate; forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed right above the source/drain region; and forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask, and the source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a method of manufacturing a contact structure in an integrated circuit, and more particularly to a method of manufacturing a contact structure in a sparse region of an integrated circuit.

2. Description of the Prior Art

Field effect transistors are important electronic devices in the fabrication of integrated circuits. As the sizes of the semiconductor devices becomes smaller and smaller, the fabrication of the transistors also has to be improved so as to fabricate transistors with smaller sizes and higher quality.

For a static random access memory (SRAM) comprised of transistors, the transistors are often electrically connected with one another through contacts and metal lines. By electrically connecting a portion of one transistor to a portion of another transistor, every six of the transistors can constitute a latch circuitry as well as a unit cell of the SRAM. Also, as the size of the SRAM continues to shrink, there is also a need to dispose contacts between the transistors and the metal lines of the SRAM, and these contacts are sometimes called M0contacts. Generally, M0contacts are formed on or above source/drain regions of the transistors and are often used to provide a short-distance electrical connection. However, because the densities of the M0contacts are varied from region to region, the resolution of the corresponding photolithographic process for manufacturing the M0contacts is often lowered by this non-uniform contact density.

Accordingly, there is still a need to provide a modified method for manufacturing contact structures, especially M0contacts, in order to overcome the above-mentioned drawbacks.

SUMMARY OF THE INVENTION

According to one embodiment of the present invention, a method for manufacturing contact structure electrically connecting a semiconductor device is disclosed and includes the steps of: providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device includes a gate structure and a source/drain region; forming a patterned mask layer with a stripe hole on the substrate, and the stripe hole is disposed right above the source/drain region; concurrently forming a stripe-shaped mask layer on the substrate, and the stripe-shaped mask layer is spaced apart from the source/drain region during the step of forming the patterned mask layer; forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed right above the source/drain region; and forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask. The source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed.

DETAILED DESCRIPTION

To provide a better understanding of the present invention to users skilled in the technology of the present invention, preferred embodiments are detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the contents and effects to be achieved.

Please note that the figures are only for illustration and the figures may not be to scale. The scale may be further modified according to different design considerations. When referring to the words “up” or “down” that describe the relationship between components in the text, it is well known in the art and should be clearly understood that these words refer to relative positions that can be inverted to obtain a similar structure, and these structures should therefore not be precluded from the scope of the claims in the present invention.

FIG. 1is a schematic top view showing a modified design layout received by a computer readable storage device. As shown inFIG. 1, a modified design layout100includes at least two sub-layouts: sub-layout100aand sub-layout100b, which respectively represent the layouts used to construct structures in different regions of a semiconductor device. These sub-layouts100aand100brespectively include at least a plurality of fin-shaped patterns106, a plurality of gate patterns104, a plurality of slot contact patterns112, and mask patterns108. As can be seen inFIG. 1, both the gate patterns104and the slot contact patterns112are arranged in a first orientation Y, and the slot contact patterns112are spaced apart from the gates patterns104. One feature of the embodiment of the present invention is that some or portions of the slot contact patterns112overlap the mask patterns108. In other words, there are overlapped regions110between the slot contact patterns112and the mask patterns108. In detail, for the sub-layouts100a, the mask patterns108overlap all dummy slot contacts112bbut are spaced apart from a slot contact112a. For the sub-layouts100b, the mask patterns108overlap dummy slot contacts112b. That is, for and100b, the overlapped regions110of the sub-layouts100abetween the slot contact patterns112and the mask patterns108may include regions of entire dummy slot contacts112b, and the overlapped regions110of the sub-layouts100bmay include regions between the ends of the two adjacent slot contacts112a.

For the sake of clarity, a method for generating the above-mentioned modified design layout100is further disclosed in the following paragraphs. Similar to the layout shown inFIG. 1, an original design layout (not shown), including the gate patterns104and slot contact patterns, is provided to the computer readable storage device. The slot contact patterns at this processing stage may only include slot contact112a. That is, the dummy slot contact112bis not generated at this time. Afterwards, in order to increase the resolution of the subsequent photolithographic process, a plurality of dummy slot contacts112bis generated next to the sides of the slot contact112aor between the distal ends of two adjacent slot contacts112a. By inserting the dummy slot contacts112binto the original design layout, the density of the slot contact patterns112may become more uniform, and the resolution of the corresponding photolithographic process may therefore become higher. However, because these dummy slot contacts112bare unnecessary components for the final semiconductor device, they should be removed once the photolithographic process for manufacturing the slot contact patterns is completed. Therefore, the mask patterns108overlapping all of the dummy slot contacts112bare then generated according to the positions of the dummy slot contacts112b. Preferably, the mask patterns108may include rectangle patterns or stripe patterns, and the size of the mask patterns108is greater than or equal to the size of the dummy slot contacts112baccording to the embodiment of the present invention.

The corresponding manufacturing method is further disclosed in the following paragraphs in order to enable persons having ordinary skill in the art to make and use the above-mentioned contact structure.

Please refer toFIGS. 2-10, which are schematic diagrams illustrating a manufacturing method of contact structures according to a preferred embodiment of the present invention.FIG. 2is across section diagram of a semiconductor device at the beginning of the fabrication process. As shown inFIG. 2, a substrate10is first provided, wherein the substrate10comprises a plurality of gate structures12arranged along a first orientation Y, and at least one fin structure16arranged along a second orientation X, where the gate structures12cross over the fin structure16. Preferably, the first direction and second direction are orthogonal, so each fin structure16and each gate structure12are arranged orthogonally, but not limited thereto. When viewed in top view, the gate structures12are preferably stripe-shaped, and arranged parallel to each other, but not limited thereto. A plurality of source/drain regions (S/D regions) is disposed on two sides of the gate structure12, and is preferably disposed in epitaxial layers15disposed on the fin structures16. In this embodiment, the gate structure12preferably comprises metal materials, and the S/D regions can be formed on the fin structure16disposed at two sides of the gate structure12. The method of the present invention further comprises forming a shallow trench isolation (STI)17on the substrate10to isolate the electric elements on the substrate10from each other. In this embodiment, some of the gate structures12cover and cross the fin structure16(such as the gate structure12ashown inFIG. 2), and other of the gate structures12are directly disposed on the STI17(such as the gate structure12bshown inFIG. 2). These gate structures12bmay be used as passing gates. Still other of the gate structures12are disposed on the distal ends of the fin structure16to protect the fin structure16from damage by the following process and may be used as dummy gates (such as the gate structure12cshown inFIG. 2).

Afterwards, a spacer18and a contact etching stop layer (CESL) (not shown) may be formed on two sides of the gate structure12. An interlayer dielectric (ILD)22is then formed on the substrate10, and is disposed between each gate structure12. Subsequently, a replacement metal gate (RMG) process is carried out. Through the RMG process, silicon-based gate structures can be replaced with metal based-gate structures. Then, a planarization process, such as a chemical mechanical polishing (CMP), is performed to have the top surface of the gate structure12aligned with the top surface of the ILD22. Subsequently, a hard mask24is selectively formed and replaces the upper portion of each of the gate structures12. Afterwards, another planarization process is performed to remove the extra hard mask24on the top surface of the ILD22. In other words, the hard mask24is disposed only on the top portions of the gate structure12, and the top surface of the hard mask24is aligned with the top surface of the ILD22. Besides, since the hard mask24replaces portions of the gate metal23of the gate structures12, the hard mask24is therefore disposed only on the gate metal23and between the spacers18. In addition, since parts of the spacer18and parts of the CESL are removed during another planarization process, the spacer18and the CESL have a truncated top surface. In the present embodiment, the spacer18, the CESL and the hard mask24are mainly made of silicon nitride, and the ILD22is mainly made of silicon oxide, but not limited thereto. These elements and the manufacturing methods thereof are well known to persons of ordinary skill in the art and the details will not be described here.

Afterwards, please refer toFIG. 2. Another ILD26and hard mask layer27are then formed on the ILD22, and a first photoresist layer28is then formed on the hard mask layer27. According to the preferred embodiment, the first photoresist layer28includes an organic dielectric layer (ODL)28a, a silicon-containing hard mask bottom anti-reflecting coating (SHB)28band a photoresist (PR) layer28cfrom bottom to top. In short, the first photoresist layer28is a tri-layered structure consisting of an ODL/SHB/PR structure, but not limited thereto. Afterwards, the mask patterns108of the modified design layout100ashown inFIG. 1are transferred to the first photoresist layer28during a suitable photolithographic process, and a region A is therefore defined in the photoresist layer28c.

Afterwards, please refer toFIG. 3, at least an etching process E1is performed to transfer the pattern in the first photoresist layer28to the underlying layer. In detail, the etching process E1etches the SHB28b, the ODL28aand the hard mask layer27in sequence, until exposing the ILD26. It is noteworthy that when viewed in cross section view, as shown inFIG. 3, an opening30or stripe hole is formed in the hard mask layer27. The pattern in the hard mask layer27may be used to define the positions of slot contacts formed in the following process. Besides, portions of the hard mask layer27may have the shape of stripe when viewed from a top down perspective (as shown in the right side ofFIG. 4). The etching process E1of the present invention preferably uses etching gases, which may comprise per fluorocarbon gases, such as tetrafluoromethane (CF4), fluoroform (CHF3), hexafluorobutadiene (C4F6), and further comprises oxygen and argon, but not limited thereto. The etching process may also comprise a wet-etching process.

Afterwards, another photoresist layer is coated on the patterned hard mask layer27. For example, a second photoresist layer is disposed on the ILD26and the patterned hard mask layer27, wherein the material of the photoresist layer may be the same as the material of the first photoresist layer28, comprising an organic dielectric layer (ODL), a silicon-containing hard mask bottom anti-reflecting coating (SHB) and a photoresist layer. Then, a suitable photolithographic process is carried out to transfer the slot contact patterns112shown inFIG. 1to the photoresist layer. The corresponding structures are shown inFIGS. 4-6.FIG. 4is a schematic top view showing a patterned photoresist with a plurality of slot holes.FIGS. 5 and 6are schematic cross-section diagrams respectively taken along line A-A′ and lines B-B′ inFIG. 4. As shown inFIG. 4, a plurality of slot holes40are formed on a first region202and a second region204of the substrate10. It should be noted that the design layouts of the structures within the first region202and the second region204are respectively defined by those shown inFIG. 1. In detail, as shown inFIGS. 5 and 6, a patterned photoresist layer38may include a patterned photoresist layer38cwith slot holes40, a silicon-containing hard mask bottom anti-reflecting coating (SHB)38band an organic dielectric layer (ODL)38afrom top to bottom. It should be noted that the width of the slot holes40is preferably less than the size of the stripe hole30of the patterned hard mask layer27. In addition, the position of the slot holes40may be disposed corresponding to the position of the space between two adjacent gate structures12, but not limited thereto. Besides, referring toFIG. 4andFIG. 5, at least one of the slot holes40in the first region202is laterally spaced apart from the patterned hard mask layer27.

FIG. 7is a schematic cross-section diagram corresponding to the structure taken along line A-A′ inFIG. 4. As shown inFIG. 7, an etching process E2is then performed by using the patterned photoresist layer38and the patterned hard mask layer27as etch masks. In detail, at the beginning of the etching process E2, the slot holes40defined in the patterned photoresist layer38care sequentially transferred to the underlying ODL38aand patterned hard mask layer27. Because the patterned hard mask layer27is made of materials with relatively low etching rate, such as titanium nitride or other suitable metal compounds, the patterned hard mask layer27exposed from the bottom of the patterned ODL38amay only be slightly removed. In contrast, the ILD26and22not covered by the patterned hard mask layer27may be etched completely until the corresponding S/D regions or epitaxial layers15are exposed. As a result, at least a contact hole32is formed in the ILD26and22. Besides, parts of the etched hard mask layer27still remain on the ILD26. Similar to the etching process E1mentioned above, the etching process E2preferably uses etching gases, which may comprise per fluorocarbon gases, such as tetrafluoromethane (CF4), fluoroform (CHF3), hexafluorobutadiene (C4F6), and further comprises oxygen and argon, but not limited thereto. The etching process E2may also comprise a wet-etching process.

It is noteworthy that the patterned photoresist layer38cand the patterned hard mask layer27are used as an etch mask during the etching process E2. That is, only the layers not covered by the patterned photoresist layer38cand the patterned hard mask layer27are etched. Therefore, each contact hole32is disposed between two adjacent gate structures12without contacting the gate structures12after the etching process E2. In addition, when viewed in top view, each contact hole32is stripe-shaped and arranged parallel to each gate structure12.

FIG. 8is a schematic diagram showing a semiconductor device with contact holes taken along line C-C′ inFIG. 4. The structure corresponds to the second region204ofFIG. 4after the above-mentioned etching process E2is shown inFIG. 8. As can be seen inFIG. 8, because of the existence of the patterned hard mask layer27, the entire pattern defined by the slot hole40may not be fully transferred down to the ILD22. That is, only the ILD22not covered by the ODL38aand the patterned hard mask layer27can be etched during the etching process E2. In detail, when the etching process E2is completed, the epitaxial layers15may be respectively exposed from the bottom32aof contact holes32. Additionally, as shown inFIG. 8, the distal ends32bof the two adjacent contact holes32are aligned with the sidewalls of the patterned hard mask layer27.

Then, the ODL38aand the patterned hard mask layer27are then removed to expose the top surface of the ILD26. Afterwards, as shown inFIG. 9, a self-aligned silicide (salicide) process is performed to thereby form a salicide layer34on the epitaxial layers15at the bottom of the contact holes32. The salicide process includes the steps of filling a metal layer (not shown) in each contact hole32, and performing an annealing process to form a salicide layer34on the interface between the metal layer and the epitaxial layers15. Afterwards, the metal layer disposed in the contact holes32is then removed. It is noteworthy that the salicide layer34may be formed at the surface of the epitaxial layers15, on the fin structure16, on the epitaxial layer15or on the substrate10, but it is preferably not formed on the STI17.

As shown inFIG. 10, a barrier layer44and a conductive layer46are filled in each trench32simultaneously, wherein the barrier layer44may comprise titanium nitride (TiN), tantalum nitride (TaN) or Ti/TiN multiple barrier layers to improve the adhesivity between the inner surface of each trench32and the conductive layer formed in the following steps. The conductive layer46preferably comprises tungsten (W) that has better gap fill performance. A planarization process is then performed to remove the extra barrier layer and the conductive layer disposed on the top surface of the ILD26to form a plurality of contact structures52in the ILD22and in the ILD26. In addition, since the contact structures52is filled with the conductive layer46, each contact structure52is a monolithically formed structure.FIG. 10is the schematic diagram showing the top view structure of the semiconductor device after the contact structure52is formed. As shown inFIG. 9, because the contact hole32is formed between every two adjacent gate structures12without directly contacting the gate structure12, the contact structure52, which is obtained by filling up the contact hole32with the conductive layer46, can also be spaced apart from the gate structures12. It is noteworthy that since the top portion of each of the gate structures12is also protected by the hard mask layer27, the step of forming the hard mask24mentioned above may be omitted. In other words, the hard mask24is selectively formed in the present invention.