Low leakage current operation of integrated circuit using scan chain

An integrated circuit (IC) having a low leakage current mode of operation has a number of modules for running respective applications. The modules have respective cells and respective test scan chain elements. The IC also has a controller for configuring an active module to operate in a functional mode and a selected inactive module to operate in a low leakage current mode. Configuring the selected inactive module to operate in low leakage current mode includes enabling scan mode of the selected inactive module, and applying a low leakage vector of input signals from the controller to the cells of the inactive module using the scan chain. Functional data outputs of the inactive module are disabled during low leakage current mode. In the meantime, the active modules continue to operate in the functional mode.

BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits and more particularly, to reducing leakage current of an integrated circuit while the integrated circuit is performing tasks.

Integrated circuit (IC) power consumption includes dynamic power consumption by active modules of the IC and static power consumption by both the active and inactive modules of the IC. Dynamic power consumption can be reduced by techniques such as frequency and voltage scaling for the active modules and by gating (turning off) the clock signals for inactive modules. Although static power consumption can represent a significant proportion of the total power consumption of an IC, these techniques do not reduce static power consumption.

Most ICs these days include built-in methods for testing the cells and modules from which the IC is constructed. One well known method is known as “scan” or scan-set testing. In scan-set testing, flip-flops or latches of the IC are connected in one or more daisy chains. A test vector is then propagated from the first latch in the chain to the last latch in the chain and then to an output pad. Passing various test vectors through the scan chain allows much of the logic or circuitry of the IC to be tested. An example of scan chain technology is the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture, commonly known as Joint Test Action Group (JTAG). In a normal, functional mode of operation, the latches receive and store values depending on the applications being executed by the IC, while in scan mode, input and output latches of the cells are connected so that, at each clock cycle, the latches store the next functional data input or output of the cell so that during scan testing, the test vectors can be propagated through the scan chains, with the first and last latches of the chain connected to an externally accessible JTAG port. Test input data, known as a test vector, is then applied to the JTAG port and shifted through the chain of registers under the control of test clock signals. Once the test signals for each latch are correctly positioned in the scan chain, the circuit is placed in normal operating mode for a defined number of operating clock cycles. The circuit is then returned to test mode and the states of the output latches are shifted through the scan chain and recovered at the JTAG port as test results. Typically, the same clock gating logic that controls the functional clock signals is used to control the application of test scan clock signals during scan testing, controlled by the automatic test equipment (ATE).

The leakage currents of gates can vary considerably as a function of the values (‘0’ or ‘1’) of the voltage signals applied to the gates. For example, a gate that receives a value of ‘1’ may have greater leakage current than if the same gate was receiving a value of ‘0’. The leakage currents of cells of ICs vary considerably as a function of the voltages applied to the cell inputs.FIG. 1illustrates a basic NAND gate100as an example of a conventional standard cell. The NAND gate100has two PMOS transistors102and104whose source-drain paths are connected in parallel between a positive supply rail VDDand an output node106and two NMOS transistors108,110whose source-drain paths are connected in series between the output node106and ground. Input voltages A are applied to the gates of the transistors102and110and input voltages B are applied to the gates of the transistors104and108. The assertion of both the input voltages A and B at positive values leads to the greatest leakage current in the NAND gate, since the NMOS transistors108and110are switched ON and the leakage current flows through the resistance of the two OFF PMOS transistors102and104in parallel. A smaller leakage current is obtained if one of the input voltages A and B is asserted and the other de-asserted, since one of the PMOS transistors102and104is ON and the leakage current corresponds to the resistance of the single one of the NMOS transistors108and110, which is OFF. The smallest leakage current is obtained if both the input voltages A and B are de-asserted, since the leakage current corresponds to the resistances of both the OFF NMOS transistors108and110in series. Table 1 shows typical values obtained.

Statistically the leakage current of the NAND gate100can be reduced, by a factor of up to 23 by applying voltages A=0, B=0 to the inputs of the NAND gate when it is not currently active, instead of leaving the inputs at the values (such as A=1, B=1) that they had after the last active state of the gate. Major reductions in leakage current can similarly be obtained for other types of cells such as NOR gates, XOR gates or multiplexers.

FIG. 2illustrates a conventional electronic module200in an IC having individual data processing cells202and respective input and output latches204. The latches204can also be connected in a test scan chain. In this example, each of the test scan chain elements includes a multiplexer206in addition to its latches204. Each of the multiplexers206has an output connected to an input of the associated latch204and a first input connected to the output of the latch of the previous test scan chain element, except for the first and last test scan chain elements. The first input of the multiplexer of the first input test scan chain element receives a test data input signal TEST IN from the test access port. The output of the latch of the last test scan chain element provides a test data output signal TEST OUT to the test access port. The multiplexers receive from the test access port control signals TEST, comprising test mode and scan enable signals. Each of the input latches204has an output connected to a data input of the associated cell202and a second input of the associated multiplexer206connected to receive a functional data signal D. Each of the output latches204has its output connected to provide a data output signal D′, and a second input of the associated multiplexer206connected to a data output of the associated cell202. The latches change state in response to the functional or test clock signals they receive, which also synchronize the operation of the associated cells202.

In functional mode, the test enable signals set the multiplexers206to pass the data input and output signals D and D′ to and from the active latches204and data processing cells202without affecting the operation of the cells. The test mode signals set the clock gating logic to receive the functional clock signals. The operation of the active latches204and data processing cells202is synchronized by the functional system clock signals CLK. The functional clock signals for the inactive latches204and data processing cells202are gated, so that the latches, and the cells, do not change state, saving dynamic power consumption.

In test mode, the test mode signals set the clock gating logic to receive the test clock signals, which replace the functional clock signals CLK. The clock gating logic applies the test clock signals at the appropriate periods to the relevant latches which form the scan chain. The test enable signals set the multiplexers206to connect the scan chain elements in a scan chain, forming a shift register. Test data input signals TEST IN forming a test vector are then shifted through the shift register in synchronization with the test clock signals. Simultaneously, test data output signals TEST OUT are shifted through the shift register and can be recovered at the test access port. Once the test vector is correctly positioned in the scan chain, the scan chain is placed in normal operating mode for one (or more) cycles of the functional clock signals CLK. The circuit is then returned to test mode and the states of the output latches are shifted through the scan chain by the test clock signals and recovered at the test access port as test results.

The electronic module200may have a full boundary scan chain or the scan chain may cover only some of the inputs and outputs. Each scan chain element may connect with an individual cell or may connect with traces having more than one cell. The electronic module200also may include more than one scan chain and the scan chain or chains of more than one module may be connected in series to form a single scan chain. The test signals TEST and TEST IN may be provided by an ATE (not shown). The test signals may include test instruction codes to modify interconnections between scan chains.

It is possible to use the scan chain to introduce a low leakage vector (LLV) having the voltages for the inputs of the different cells of the circuit that place the cells in low leakage current configuration, as proposed by Abdollahi et al. in their paper “Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains”, Proceedings Fourth International Symposium on Quality Electronic Design, 2003; Page(s): 49-54. Abdollahi et al. propose scanning in the LLV while the IC is in a sleep or low power mode. While this is a good improvement in reducing static power consumption, it does not reduce static power consumption while the IC is in normal, functional mode.

It would be advantageous to reduce the leakage power of an IC even while the IC is performing tasks.

According to the present invention, the leakage current of an IC is reduced substantially by applying suitable low leakage vectors (‘LLVs’) through scan chains to the inputs of inactive cells, instead of leaving the inputs at the values that they had after their last active state, while the IC is operating in a normal, functional mode. The LLVs preferably are stored in an off-chip memory and, as discussed below, provided to the chip via software and an LLV controller.

Referring now toFIGS. 3 to 5, an IC300including circuitry320having a low leakage current mode of operation in accordance with one embodiment of the invention, given by way of example, is illustrated. The circuitry320includes a plurality of modules302-316(modules identified with even numbers) that implement specific logic functions and/or for running respective applications. Each of the modules302-316comprises respective cells and respective test scan chain elements. The circuitry320also includes a low leakage vector controller318for configuring at least one active module of the plurality of modules302-316to operate in a functional mode and at least one selected inactive module of the plurality of modules302-316to operate in a low leakage current mode. Configuring the selected inactive module to operate in low leakage current mode comprises enabling the scan chain elements of the selected inactive module, and applying a low leakage vector of input signals from the controller318to the cells of the inactive module by way of the scan chain.

In one embodiment of the present invention, the power supply for the modules302-316is not interrupted when a selected inactive module is configured in low leakage current mode. The active module or modules of the plurality of modules302-316can therefore continue normal operation without switching the power supply to the inactive module or modules. The input signals of the low leakage vector are chosen as a function of the configuration of the selected inactive module so as to maintain the selected inactive module in a state with a low and preferably the lowest, or one of the lowest, leakage currents based on the different possible combinations of cell input signals.

The modules302-316may be like the modules200shown inFIG. 2, for example, having respective functional data inputs and outputs. The controller318can disable the functional data outputs of the inactive module or modules during operation in the low leakage current mode. In the preferred embodiment, the modules302-316have respective gates303-317for disabling (‘gating’) the functional data outputs of the associated inactive module.

The IC300also has a test access port322coupled to the controller318. During scan testing, the test access port322communicates with the scan chain elements of the modules302-316, as shown by dotted lines. The scan test communication with the scan chain elements may comply with the JTAG protocols, although other test procedure communication protocols may be used. The controller318includes memory and a processing unit for accessing the memory and reading stored low leakage current vectors for the modules302-316, enabling the modules302-316to operate in functional mode or low leakage current mode, and enabling the gates303-317to gate the output signals of the modules302-316. In functional mode, the controller318generates a low leakage mode select signal LL MODE SELECT, a low leakage data input vector signal LL DATA IN, and a low leakage clock signal LL CLOCK and receives from the scan chains of the modules302-316a low leakage data output signal LL DATA OUT. The signals LL MODE SELECT, LL DATA IN, LL CLOCK and LL DATA OUT are similar in format and protocol to the scan test procedure signals TEST MODE SELECT, TEST DATA IN, TEST CLOCK and TEST DATA OUT. The signals LL MODE SELECT, LL DATA IN, LL CLOCK and LL DATA OUT are stored in the memory of the controller318and define the low leakage vector and control or configuration parameters for different combinations of inactive modules. The low leakage vector may be loaded into the memory of the controller318, in one or multiple iterations, from an off-IC memory depending on the length of the scan chain and controller's low leakage vector memory depth.

As shown inFIG. 4, in this example, the memory of the controller318is configurable via software and includes a control register400and a low leakage vector register402, which in this case is 32-bits. The control register400controls disabling of the outputs of the inactive modules302-316using the gates303-317, selective gating of the functional clocks for the inactive modules, and the scan configuration (i.e., scan enabled or disabled) of the inactive modules. The low leakage vector register402stores low leakage data input signals LL DATA IN corresponding to different low leakage vectors for each of the modules302-316and for different combinations of the modules. The controller318also includes a register404for storing the length LLV LENGTH of the low leakage vectors. The controller318also has a clock generator406that provides the low leakage scan clock signal LL CLOCK by scaling the frequency of the functional system clock signal CLK. The controller318also has a finite state machine (FSM)408.

The low leakage data input signal LL DATA IN is a serialized form of the low leakage vector of the scan chains of the inactive modules. The FSM408selects the inactive module or modules that are to be configured in low leakage mode and the corresponding low leakage vectors as a function of indications from the system controller (not shown). Based on the configuration in the control register400, the FSM408causes the functional system clock signal CLK for the inactive module or modules to be interrupted and also enables the scan chains of the inactive module or modules for communication of the signals LL DATA IN and LL DATA OUT with the controller318, instead of with the functional data inputs and outputs. If the length of the low leakage data input signal LL DATA IN is greater than the capacity of the low leakage vector register402, in this case 32-bits, two or more iterations may be necessary to shift in the whole low leakage data input signal LL DATA IN. However, if the length of the low leakage data input signal LL DATA IN is less than or equal to the capacity of the low leakage vector register402, the low leakage data input signal LL DATA IN can be shifted in in a single operation.

FIG. 5illustrates an example of the circuitry320, in which the modules302and304are part of a first specific application500and the modules306,308and310are part of a second specific application502. The first and second applications500and502can be configured temporarily or for extensive periods of time in low leakage mode. The modules312,314and316are part of a third basic application504such that the modules312-316cannot be configured in low leakage current mode.

InFIG. 5, the controller318is connected to scan control logic elements506,508and510, which control the scan chains of the modules being used for the applications500,502and504respectively. The scan chains of the modules used by the applications500,502and504are connected in series, with the scan input of the first scan chain of the application and the scan output of the last scan chain of the application connected to the respective scan control logic element506,508or510. The scan chains and scan control logic elements506,508and510used for the low leakage mode are the same as for scan test operations.

FIG. 5shows an example of partial low leakage operation of the circuitry320and the controller318in which the applications500and504are active and are supplied with the functional system clock CLK and normal power supply. However, the application502is inactive, and therefore the functional system clock CLK for the modules306and308is interrupted because these modules are inactive and for this example, designated for low leakage mode. In this embodiment, the normal power supply is provided to the modules306and308, which simplifies the hardware of the circuitry320. The scan chains, shown in dotted lines, of the modules executing the applications500and504are inactive, while the scan chain, shown in dashed lines, of the modules306,308,310that are executing application502is active (and these modules are inactive) and communicates with the controller318through the scan control logic element508. The low leakage mode select signal LL MODE SELECT, the low leakage data input signal LL DATA IN, the low leakage clock signal LL CLOCK, and the low leakage data output signal LL DATA OUT are transmitted between the scan control logic elements506,508and510as shown in dotted lines. Accordingly, the controller318can configure the inactive modules306-310of the application502in low leakage mode and the modules of the active applications500and504in functional mode.

In this example, the scan chains of the inactive modules302-316are connected together as a single scan chain and respective low leakage vectors of input signals are applied to the cells of each of the inactive modules through the single scan chain. However, in an alternative embodiment, the low leakage vectors for each of the inactive modules that are placed in the low leakage mode are issued separately to each module using just the scan chain of the respective module. That is, the controller318can access the scan chain of each of the modules302-316individually.

In this example, the functional data outputs F DATA OUT of the inactive module placed in the low current mode are disabled using the respective gate303-317of the inactive module. However, in an alternative embodiment of the invention, multiplexers of the scan chain elements of the inactive module or modules302-316interrupt the functional data outputs, thereby providing the same effect.

In this example, the controller318recovers the output signals LL DATA OUT from the scan chain while applying the low leakage vector of input signals to the cells of the inactive module designated for low leakage current mode. The output signals LL DATA OUT are representative of functional input signals during a previous active state of the inactive module. When the inactive module is switched from the low leakage current mode to active, functional mode, the controller318restores the inactive module to the functional mode, and re-applies the output signals LL DATA OUT representative of a previous active state of the module to the inputs of the inactive module. However, in another embodiment, restoration of the inactive module to a previous active state is omitted, notably if the selected inactive module is of a type that does not require such restoration.

The invention may be implemented partially in a computer program for running on a computer system, at least including code portions for performing steps of a method according to the invention when run on a programmable apparatus, such as a computer system or enabling a programmable apparatus to perform functions of a device or system according to the invention. A computer program is a list of instructions such as a particular application program and/or an operating system. The computer program may for instance include one or more of: a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, source code, object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system. Such programmed instructions also could be implemented in firmware, as will be understood by those of skill in the art.

The computer program may be stored internally on computer readable storage medium or transmitted to the computer system via a computer readable transmission medium. All or some of the computer program may be provided on computer readable media permanently, removably or remotely coupled to an information processing system. The computer readable media may include, for example and without limitation, any number of the following: magnetic storage media including disk and tape storage media; optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; nonvolatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memories; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, etc.; and data transmission media including computer networks, point-to-point telecommunication equipment, and carrier wave transmission media, just to name a few.

Each signal described herein may be designed as positive or negative logic. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein can be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals. The terms “assert” or “set” and “negate” (or “de-assert” or “clear”) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.

Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermediate components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.

Furthermore, those skilled in the art will recognize that boundaries between the above described operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. Also for example, the examples, or portions thereof, may implemented as soft or code representations of physical circuitry or of logical representations convertible into physical circuitry, such as in a hardware description language of any appropriate type.