CPU/GPU DCVS co-optimization for reducing power consumption in graphics frame processing

Systems, methods, and computer programs are disclosed for minimizing power consumption in graphics frame processing. One such method comprises: initiating graphics frame processing to be cooperatively performed by a central processing unit (CPU) and a graphics processing unit (GPU); receiving CPU activity data and GPU activity data; determining a set of available dynamic clock and voltage/frequency scaling (DCVS) levels for the GPU and the CPU; and selecting from the set of available DCVS levels an optimal combination of a GPU DCVS level and a CPU DCVS level, based on the CPU and GPU activity data, which minimizes a combined power consumption of the CPU and the GPU during the graphics frame processing.

DESCRIPTION OF THE RELATED ART

Portable computing devices (e.g., cellular telephones, smart phones, tablet computers, portable digital assistants (PDAs), and portable game consoles) continue to offer an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, such devices have become more powerful, more complex. Portable computing devices now commonly include system-on-chips (SoCs) and/or multiple microprocessor cores embedded on a single substrate (e.g., a central processing unit (CPU), graphics processing unit (GPU), etc.), allowing users to execute complex and power intensive software applications. However, increased performance and functionality requirements present significant design and operational challenges for managing battery life and power consumption.

Existing methods for managing power consumption of multiprocessor devices may involve dynamic clock and voltage scaling (DCVS) techniques. DCVS involves selectively adjusting the frequency and/or voltage applied to the processors, hardware devices, etc. to yield the desired performance and/or power efficiency characteristics. Conventional DCVS solutions exhibit a number of performance problems, and implementing an effective DCVS method that correctly scales frequency/voltage for each core of multicore processor system is an important and challenging design criterion. For example, DCVS techniques for multiprocessor systems (e.g., systems comprising a CPU and a GPU) require that each processor include a separate DCVS module/process and/or adjust the processor frequency/voltage independent of other processors. Furthermore, when performing graphics frame processing, the separate CPU and/or GPU DCVS algorithms are designed to optimize performance within the constraints presented by frame processing deadlines without regard to power efficiency optimization.

Accordingly, there remains a need in the art for improved systems and methods for optimizing DCVS for power efficiency in multiprocessor systems.

SUMMARY OF THE DISCLOSURE

Systems, methods, and computer programs are disclosed for minimizing power consumption in graphics frame processing. One such method comprises: initiating graphics frame processing to be cooperatively performed by a central processing unit (CPU) and a graphics processing unit (GPU); receiving CPU activity data and GPU activity data; determining a set of available dynamic clock and voltage/frequency scaling (DCVS) levels for the GPU and the CPU; and selecting from the set of available DCVS levels an optimal combination of a GPU DCVS level and a CPU DCVS level, based on the CPU and GPU activity data, which minimizes a combined power consumption of the CPU and the GPU during the graphics frame processing.

Another embodiment comprises a system for minimizing power consumption in graphics frame processing. One such system comprises a system on chip (SoC) including a central processing unit (CPU), a graphics processing unit (GPU), and a dynamic clock voltage and scaling (DCVS) controller in communication with the GPU and the CPU. A CPU/GPU DCVS co-optimization module is configured to determine an optimal combination of a GPU DCVS level and a CPU DCVS level for the DCVS controller, based on CPU and GPU activity data. The optimal combination of the GPU and CPU DCVS levels are selected to minimize a combined power consumption of the CPU and the GPU during graphics frame processing.

DETAILED DESCRIPTION

In this description, the terms “communication device,” “wireless device,” “wireless telephone”, “wireless communication device,” and “wireless handset” are used interchangeably. With the advent of third generation (“3G”) wireless technology and four generation (“4G”), greater bandwidth availability has enabled more portable computing devices with a greater variety of wireless capabilities. Therefore, a portable computing device may include a cellular telephone, a pager, a PDA, a smartphone, a navigation device, or a hand-held computer with a wireless connection or link.

FIG. 1illustrates a system100for co-optimizing dynamic clock and voltage/frequency scaling (DCVS) levels of a central processing unit (CPU)106and a graphics processing unit (GPU)104during graphics frame processing (referred to as “CPU/GPU DCVS co-optimization”). The graphics frame processing may involve any workload in which the CPU106and the GPU104cooperatively perform the frame processing. For example, the graphics frame processing may involve a CPU/GPU serialized workload and/or a CPU/GPU parallelized workload. As known in the art, a CPU/GPU serialized workload involves consecutive processing by the CPU106and the GPU104for each graphics frame. For each frame, the CPU106starts the processing and provides output to the GPU104, which performs additional processing. The GPU104transfers the resulting output to the display110via, for example, a mobile display processor.

One of ordinary skill in the art will appreciate that a CPU/GPU parallelized workload involves parallel processing by the CPU106and the GPU104. The CPU106starts processing for a frame (n) and stores the resulting output in a frame buffer128of a memory126. During the next period, the GPU104retrieves the output stored in the frame buffer128and performs additional processing for frame (n) while the CPU106processes a frame (n+1) and stores the corresponding output in the frame buffer128. The process repeats for each subsequent frame. While this process results in a single frame delay, it provides performance advantages due to CPU/GPU parallel processing.

It should be appreciated that the term CPU/GPU DCVS co-optimization refers to jointly optimizing a DCVS level for both the GPU104and the CPU106such that the combined power consumption of the GPU104and the CPU106is minimized. In other words, the system100determines an optimal combination of a GPU DCVS level and a CPU DCVS level for the DCVS controller112, which provides the lowest overall CPU and GPU power consumption during the graphics frame processing.

The system100may be implemented in any multiprocessor computing device, including a personal computer, a workstation, a server, a portable computing device (PCD), such as a cellular telephone, a portable digital assistant (PDA), a portable game console, a palmtop computer, or a tablet computer. In an embodiment, one or more of the system components illustrated inFIG. 1may be incorporated on a system on chip (SoC) coupled to a memory system (e.g., dynamic random access memory (DRAM)) or other types of memory. As illustrated inFIG. 1, the system100comprises one or more processing devices, units, or cores (e.g., CPU106, GPU104). The system100may further comprise any other general or specific-purpose hardware devices, such as, for example, digital signal processor(s), mobile display processor, video encoders, etc.

The CPU106, the GPU104, and any other hardware devices108may be connected to a respective hardware driver114. As known in the art, the hardware drivers114provides a software interface to the respective hardware devices, enabling operating systems and other computer programs to access hardware functions without needing to know precise details of the hardware being used. The hardware drivers114are electrically coupled to a DCVS controller112. The DCVS controller112is configured to implement the system DCVS techniques by controlling the frequency and/or voltage provided to the CPU106, the GPU104, and the hardware devices108. The DCVS controller112may adjust the frequency and/or voltage at which the devices operate via interfaces to, for example, one or more clocks116, a power management integrated circuit (PMIC)118, etc.

As mentioned above, during graphics frame processing, the DCVS controller112may interface with the CPU/GPU DCVS co-optimization module(s)102to jointly optimize DCVS levels for both the GPU104and the CPU106to provide the lowest overall CPU and GPU power consumption. In the embodiment ofFIG. 1and as described below in more detail, the CPU/GPU DCVS co-optimization module(s)102comprise a graphics workload type detection module120, which is configured to determine whether the graphics workload comprises a CPU/GPU serialized workload or a CPU/GPU parallelized workload. If the graphics workload is serialized, CPU/GPU DCVS co-optimization is performed by module(s)122. If the graphics workload is parallelized, CPU/GPU DCVS co-optimization is performed by module(s)124.

FIG. 2is a flowchart of an embodiment of a method200implemented in the system ofFIG. 1for controlling various CPU/GPU DCVS co-optimization algorithms according to a detected graphics workload type. At block202, the system100may initiate graphics frame processing. At block204, the graphics workload type detection module120detects a workload type associated with the graphics frame processing. In an embodiment, the workload type detection may be performed by a GPU driver. The detected workload type may comprise a CPU/GPU serialized workload or a CPU/GPU parallelized workload. The workload type may be detected in various ways. In one embodiment, a GPU driver may determine whether a frame buffer object (FBO) has been created. If a FBO is created, the system100may determine that the graphics workload type is CPU/GPU serialized. If a FBO is not created, the system may determine that the graphics workload type is CPU/GPU parallelized.

Another detection method may involve investigating profile frame processing. If it is determined that processing for a frame (n+1) only starts after frame (n) processing is completed, the system100may determine that the graphics workload type is CPU/GPU serialized. This may be assumed where, for example, the start time for frame (n+1) is approximately equal to the end time of frame (n) processing. If, however, processing for the frame (n+1) can start regardless of the status of frame (n) processing, the system100may determine that the graphics workload type is CPU/GPU parallelized. This may be assumed where, for example, the start time for frame (n+1) occurs before the end time of frame (n) processing.

The workload type may also be determined based on graphics performance benchmarks. For example, a data table may specify that certain types of benchmarks or performance and/or usage scenarios should be associated with CPU/GPU serialized workloads while others associated with CPU/GPU parallelized workloads.

Regardless the workload type detection method, the module120controls (decision block206) which CPU/GPU DCVS co-optimization algorithm should be applied. For serialized workloads, one of a set of CPU/GPU serialized DCVS co-optimization algorithms may be applied (block208). For parallelized workloads, one of a set of CPU/GPU parallelized DCVS co-optimization algorithms may be applied (block210).

FIG. 3is a block diagram illustrating exemplary data inputs used by the CPU/GPU DCVS co-optimization module(s)102for jointly optimizing the GPU and CPU DCVS levels to minimize the combined power consumption of the CPU106and the GPU104during graphics frame processing. As described below in more detail, the various types of data are used to determine an optimal operating point (i.e., GPU and CPU DCVS levels) for the lowest combined CPU and GPU power consumption while observing frame deadline(s). In an embodiment, the CPU/GPU DCVS co-optimization module(s)102may be configured to determine the optimal operating point constrained by the conditions in Equations 1-4.
CPU active time+GPU active<frame period=1/frames per second (FPS)  Equation 1
CPUFmin<CPU frequency<CPUFmax;  Equation 2wherein Fmin is a minimum CPU frequency; andFmax is a maximum CPU frequency
GPUFmin<GPU frequency<GPUFmax;  Equation 3wherein Fmin is a minimum GPU frequency; andFmax is a maximum GPU frequency
Minimal Total Avg. SoC Power Consumption=CPU power+GPU power+others  Equation 4

Referring toFIG. 3, the CPU/GPU DCVS co-optimization module(s)102may obtain various types of activity data from the CPU106and the GPU104(i.e., referred to as CPU activity data and GPU activity data, respectively). The activity data may be received from the CPU activity profiler302and the GPU activity profiler304. As known in the art, the activity profilers302and304may obtain relevant data from, for example, respective CPU and GPU drivers, counters, registers, other hardware, etc. The activity data may include any of the following, or other, types of data related to CPU and/or GPU activity: workload, active time, idle time, waiting time, etc. The CPU/GPU DCVS co-optimization module(s)102may determine possible low power modes associated with the CPU106(CPU low power modes306) and the GPU104(GPU low power modes308). The low power modes may comprise a list or table of respective DCVS levels or operating frequencies, etc. It should be appreciated that the CPU low power modes may involve any of the following functions, features, or variables: clock gating modes, retention with lower voltage, power gating, etc. The GPU low power modes may involve, for example, spatial peak temporal peak (SPTP) power collapse, GFX power collapse, etc.

As further illustrated inFIG. 3, CPU/GPU DCVS co-optimization may also incorporate temperature data from CPU temperature sensor(s)312and GPU temperature sensor(s)310, as well as quiescent state supply current (IDDQ) leakage data associated with the CPU (IDDQ leakage data314) and the GPU (IDDQ leakage data316). One of ordinary skill in the art will appreciate that the optimal CPU/CPU operating point for minimizing the combined CPU and GPU power consumption may be determined based on one or more of the data illustrated inFIG. 3. The CPU/GPU DCVS co-optimization module102provides the optimal CPU/GPU operating point to the DCVS controller112, which adjusts the CPU106and the GPU104via, for example, the clocks116and/or the PMIC118(FIG. 1).

FIG. 4is a flowchart illustrating an embodiment of a method400implemented in the system100for co-optimizing CPU and GPU DCVS to minimize power consumption during graphics frame processing. At block402, GPU and CPU activity data are received from, for example, the CPU activity profiler302and the GPU activity profiler304. The CPU/GPU DCVS co-optimization module(s)102may determine possible low power modes for the CPU106and the GPU104(block404) and/or respective DCVS levels, operating frequencies, etc. (block406) or as otherwise described above. At block408, the CPU/GPU DCVS co-optimization module(s)102may receive temperature data and/or IDDQ leakage data for the CPU106and the GPU104. Based one or more of the data received and/or determined in blocks402,404,406, and408, the CPU/GPU DCVS co-optimization module(s)102selects the appropriate co-optimization algorithms according to the graphics workload type, and determines (block410) an optimal combination of a CPU DCVS level and a GPU DCVS level that minimizes the combined power consumption of the CPU106and the GPU104during graphics frame processing. At block412, the optimal operating point (e.g., DCVS setting(s)) are transmitted to the DCVS controller112, which controls the adjustments to the frequency and/or voltage of the CPU106and the GPU104for processing the graphics workload within the frame deadlines (block414).

FIGS. 5a-5care a series of timing diagrams for illustrating an embodiment of a CPU/GPU DCVS co-optimization method for a CPU/GPU serialized graphics workloads.FIGS. 5a&5billustrate conventional methods for minimizing overall CPU/GPU power consumption by independently optimizing CPU DCVS and GPU DCVS.FIG. 5aillustrates a first scenario comprising the lowest CPU frequency and the lowest GPU frequency.

As illustrated inFIG. 5a, the CPU frequency is 800 MHz and the GPU frequency is 579 MHz. The serialized workload is illustrated for the first three frames associated with the workload (i.e., frame n, frame (n+1), and frame (n+2) identified as frames500,502, and504, respectively). Reference numerals506a1,506a2, and506a3illustrate the CPU processing in the respective frames500,502, and504, respectively, while reference numerals508a1,508a2, and508a3illustrate the GPU processing. As illustrated inFIG. 5a, in frame500, the GPU processing508a1occurs after the CPU processing506a1. When GPU processing508a1is completed, the output is provided to the display110. In frame502, the GPU processing508a2occurs after the CPU processing506a2. When GPU processing508a2is completed, the output is provided to the display110. In frame504, the GPU processing508a3occurs after the CPU processing506a3. When GPU processing508a3is completed, the output is provided to the display110. Simulated power consumption data for scenario1inFIG. 5ademonstrates that the total power consumption=CPU (559 mW)+GPU (1205 mW)=1764 mW.

FIG. 5billustrates a second scenario comprising the highest CPU frequency and the highest GPU frequency. As illustrated inFIG. 5b, the CPU frequency is 2200 MHz and the GPU frequency is 625 MHz. Again, the serialized workload is illustrated for the first three frames500,502,504. Reference numerals506b1,506b2, and506b3illustrate the CPU processing in the respective frames500,502, and504, respectively, while reference numerals508b1,508b2, and508b3illustrate the GPU processing. Simulated power consumption data for scenario2inFIG. 5bdemonstrates that the total power consumption=CPU (783 mW)+GPU (1206 mW)=1988 mW. By comparison toFIG. 5a, it should be appreciated that the width of the respective blocks is proportional to the amount of processing time. Compared to the blocks inFIG. 5a(which are processed at the lowest frequency), the blocks inFIG. 5buse less processing time due to the higher frequency. The simulated data shows scenario1(FIG. 5a) better optimizes power consumption than scenario2(FIG. 5b).

FIG. 5cillustrates the same three frames500,502,505of the serialized workload in an exemplary implementation of the system100. In this third scenario, the CPU frequency and the GPU frequency are jointly optimized, as described above.FIG. 5cillustrates that a co-optimization approach, as described above, provides a lower overall power consumption than the conventional approaches illustrated inFIG. 5a(i.e., lowest frequency of both CPU and GPU) andFIG. 5b(i.e., highest frequency of both CPU and GPU). In the example ofFIG. 5c, the overall power consumption is minimized wherein the CPU frequency is 1000 MHz and the GPU frequency is 475 MHz. The simulated power consumption data for scenario3inFIG. 5cdemonstrates that the total power consumption=CPU (554 mW)+GPU (1204 mW)=1757 mW. This co-optimization approach in scenario3(FIG. 5c) results in the lowest power consumption compared to conventional methods in the scenarios1and2(FIGS. 5aand 5b).

FIGS. 6-8comprise data tables illustrating estimated GPU and CPU power consumption for various combinations of GPU and CPU DCVS levels in an exemplary serialized workload. It should be appreciated that the data tables illustrate that the combined CPU/GPU power consumption is a non-linear, convex relationship in the exemplary CPU/GPU frequency space. Each data table shows estimated average CPU and GPU power according to various combinations of frequency and activity times.FIG. 6illustrates a first example in which the temperature of the CPU106and the GPU104are approximately 55 degrees Celsius.FIG. 7illustrates a second example in which the temperature of the CPU106and the GPU104are approximately 85 degrees Celsius.FIG. 8illustrates a third example in which the temperature of the CPU106is approximately 55 degrees Celsius and the temperature of the GPU104is approximately 80 degrees Celsius.

In each ofFIGS. 6-8, the GPU combinations are listed in the three columns on the left of each table, and the CPU combinations are listed in the three rows on the top of each table. The greyed-out cells illustrate the estimated total CPU and GPU power according to the various combinations. The blacked-out cell in each table identifies the optimal operating point in the CPU/GPU frequency space for minimizing the combined CPU and GPU power consumption.FIGS. 6-8show that that the optimal operating point varies depending on CPU and GPU temperature changes, and this is the reason why the method inFIG. 3andFIG. 4utilizes IDDQ (leakage) and temperature information to determine the optimal operating point of the CPU and the GPU.

It should be appreciated that the CPU/GPU DCVS co-optimization module(s)102may be configured to estimate respective CPU and GPU power within any desirable frequency space and based on any of the input data described above. Furthermore, the various optimization algorithms may be employed.FIG. 9illustrates an exemplary implementation of a gradient descent search method. CPU operating frequency (DCVS) levels are represented along the x-axis902by vertical dashed lines906. GPU operating frequency (DCVS) levels are represented along the y-axis904by horizontal dashed lines908. The intersection of lines908and906define available operating points for co-optimizing the CPU and GPU DCVS levels.

In the example ofFIG. 9, operating point910(illustrated as a black circle) represents a current operating point of the CPU106and the GPU104. The optimization algorithm may be configured to estimate power consumption of adjacent DCVS operating points to determine if there is a lower-power operating point. It may be determined that operating points912(illustrated with an X) yield lower overall power consumption but do not meet frame deadlines and, therefore, are not considered. The triangular bounded area represents combinations of CPU/GPU DCVS levels that would meet the frame processing deadlines. Operating points914(illustrated with a white circle) may be determined to yield lower overall power consumption and meet frame deadlines. However, an operating point916(illustrated with a greyed-out circle) may be identified as an optimal new operating point because it not only meets frame deadlines but yields the lowest overall combined CPU/GPU power consumption of all adjacent operating points. One of ordinary skill in the art will appreciate that other optimization methods may be implemented including, for example, branch and bound tree search or any other desirable method.

FIG. 10is a flowchart illustrating an embodiment of a method1000implemented in the system ofFIG. 1for co-optimizing CPU and GPU DCVS levels for CPU/GPU parallelized graphics workloads. At block1002, the CPU/GPU DCVS co-optimization module(s)102detect a parallelized workload in the manner described above. At block1004, the optimal combination of CPU and GPU DCVS levels may be determined based on any of the input data (FIG. 3) that minimizes the combined power consumption of the CPU106and the GPU104for the parallelized workload. The system100may also determine appropriate DCVS levels or other operating conditions for increasing the idle time of common hardware resources (hardware devices118—FIG. 1). As illustrated inFIG. 11b, the parallelized CPU/GPU workload and processing for the common hardware resources may be synchronized according to a vertical synchronization (Vsync) signal1109from a display driver for display110.FIG. 11aillustrates a comparative example in which vertical synchronization is employed for a serialized workload rather than a parallelized workload. It should be appreciated that by including vertical synchronization with a co-optimized CPU/GPU parallelized workload (as illustrated inFIG. 11b) the idle time of the common hardware resources may be significantly increased, yielding a much more efficient usage of the common hardware resources with the co-optimized CPU/GPU DCVS levels.

Referring toFIGS. 11aand 11b, CPU processing during frames1102,1104,1106, and1108is represented by reference numerals1110a,1110b,1110c, and1110d. GPU processing inFIG. 11a(serialized workload) is represented by reference numerals1112a,1112b,1112c, and1112d. GPU processing inFIG. 11b(parallelized workload) is represented by reference numerals1112a,1112b, and1112c, accounting for the one frame delay inherent in parallelized workloads. Processing for the common hardware resources during frames1102,1104,1106, and1108is represented by reference numerals1114a,1114b,1114c, and1114d, respectively.FIG. 11bshows that by combining vertical synchronization with a CPU/GPU parallelized workload, the idle time of the common hardware resources may be increased (illustrated by the narrower processing blocks inFIG. 11bthan inFIG. 11a).

As mentioned above, the system100may be incorporated into any desirable computing system.FIG. 12illustrates the system100incorporated in an exemplary portable computing device (PCD)1200. It will be readily appreciated that certain components of the system100(e.g., CPU/GPU DCVS co-optimization module(s)102, CPU106, GPU104) may be included on the SoC322(FIG. 12) while other components (e.g., memory126, display110) may be external components coupled to the SoC322. The SoC322may include a multicore CPU1202. The multicore CPU1202may include a zeroth core1210, a first core1212, and an Nth core1214. One of the cores may comprise GPU104with one or more of the others comprising the CPU106.

A display controller328and a touch screen controller330may be coupled to the CPU1202. In turn, the touch screen display1206external to the on-chip system322may be coupled to the display controller328and the touch screen controller330.

FIG. 12further shows that a video encoder334(e.g., a phase alternating line (PAL) encoder, a sequential color a memoire (SECAM) encoder, or a national television system(s) committee (NTSC) encoder) is coupled to the multicore CPU1202. Further, a video amplifier336is coupled to the video encoder334and the touch screen display1206. Also, a video port338is coupled to the video amplifier336. As shown inFIG. 12, a universal serial bus (USB) controller340is coupled to the multicore CPU1202. Also, a USB port342is coupled to the USB controller340. Memory104and a subscriber identity module (SIM) card346may also be coupled to the multicore CPU1202. Memory104may reside on the SoC322or be coupled to the SoC322. The memory104may comprise a DRAM memory system.

Further, as shown inFIG. 12, a digital camera348may be coupled to the multicore CPU1202. In an exemplary aspect, the digital camera348is a charge-coupled device (CCD) camera or a complementary metal-oxide semiconductor (CMOS) camera.

As further illustrated inFIG. 12, a stereo audio coder-decoder (CODEC)350may be coupled to the multicore CPU1202. Moreover, an audio amplifier352may coupled to the stereo audio CODEC350. In an exemplary aspect, a first stereo speaker354and a second stereo speaker356are coupled to the audio amplifier352.FIG. 12shows that a microphone amplifier358may be also coupled to the stereo audio CODEC350. Additionally, a microphone360may be coupled to the microphone amplifier358. In a particular aspect, a frequency modulation (FM) radio tuner362may be coupled to the stereo audio CODEC350. Also, an FM antenna364is coupled to the FM radio tuner362. Further, stereo headphones366may be coupled to the stereo audio CODEC350.

FIG. 12further illustrates that a radio frequency (RF) transceiver368may be coupled to the multicore CPU1202. An RF switch370may be coupled to the RF transceiver368and an RF antenna372. A keypad204may be coupled to the multicore CPU1202. Also, a mono headset with a microphone376may be coupled to the multicore CPU1202. Further, a vibrator device378may be coupled to the multicore CPU1202.

FIG. 12also shows that a power supply380may be coupled to the SoC322. In a particular aspect, the power supply380is a direct current (DC) power supply that provides power to the various components of the PCD1200that require power. Further, in a particular aspect, the power supply is a rechargeable DC battery or a DC power supply that is derived from an alternating current (AC) to DC transformer that is connected to an AC power source.

FIG. 12further indicates that the PCD1200may also include a network card388that may be used to access a data network (e.g., a local area network, a personal area network, or any other network). The network card388may be a Bluetooth network card, a WiFi network card, a personal area network (PAN) card, a personal area network ultra-low-power technology (PeANUT) network card, a television/cable/satellite tuner, or any other network card well known in the art. Further, the network card388may be incorporated into a chip (i.e., the network card388may be a full solution in a chip, and may not be a separate network card388).

As depicted inFIG. 12, the touch screen display1206, the video port338, the USB port342, the camera348, the first stereo speaker354, the second stereo speaker356, the microphone360, the FM antenna364, the stereo headphones366, the RF switch370, the RF antenna372, the keypad374, the mono headset376, the vibrator378, and the power supply380may be external to the SoC322.

It should be appreciated that one or more of the method steps described herein may be stored in the memory as computer program instructions, such as the modules described above. These instructions may be executed by any suitable processor in combination or in concert with the corresponding module to perform the methods described herein.

Certain steps in the processes or process flows described in this specification naturally precede others for the invention to function as described. However, the invention is not limited to the order of the steps described if such order or sequence does not alter the functionality of the invention. That is, it is recognized that some steps may performed before, after, or parallel (substantially simultaneously with) other steps without departing from the scope and spirit of the invention. In some instances, certain steps may be omitted or not performed without departing from the invention. Further, words such as “thereafter”, “then”, “next”, etc. are not intended to limit the order of the steps. These words are simply used to guide the reader through the description of the exemplary method.

Additionally, one of ordinary skill in programming is able to write computer code or identify appropriate hardware and/or circuits to implement the disclosed invention without difficulty based on the flow charts and associated description in this specification, for example.

Therefore, disclosure of a particular set of program code instructions or detailed hardware devices is not considered necessary for an adequate understanding of how to make and use the invention. The inventive functionality of the claimed computer implemented processes is explained in more detail in the above description and in conjunction with the Figures which may illustrate various process flows.

Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (“DSL”), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.

Disk and disc, as used herein, includes compact disc (“CD”), laser disc, optical disc, digital versatile disc (“DVD”), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

Alternative embodiments will become apparent to one of ordinary skill in the art to which the invention pertains without departing from its spirit and scope. Therefore, although selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims.