Instrument for measuring true-RMS A.C. voltage and A.C. voltage fluctuations

A line voltage monitor which can measure d.c. and RMS a.c. voltage and frequency, maximum and minimum RMS voltage, which displays input voltage, and computes and displays % regulation from the measured maximum and minimum voltage values. Analog input circuitry attenuates and squares the input voltage. A voltage-to-frequency converter produces logic pulses at a rate proportional to the squared signal. A 16-bit counter integrates V.sup.2 by accumulating pulses from the voltage-to-frequency converter. A second 16-bit counter increments at a 1 MHz rate to determine the cycle period T of the input. A microcomputer divides the .intg.V.sup.2 value by the period T and then takes the square root, yielding the RMS value of the input voltage. The microcomputer can be switched to determine the % regulation and the input frequency, and can be used to enable display of V.sub.max, V.sub.RMS (t) or V.sub.min, as well as the regulation.

FIELD OF THE INVENTION 
This invention relates to devices for measuring fluctuations in alternating 
current voltage, and more particularly to instruments for measuring 
true-RMS line voltages, frequency and percent regulation in connection 
with measurements required in the testing of diagnostic X-ray equipment 
and similar apparatus. 
BACKGROUND OF THE INVENTION 
Under P.L. 90-602, "The Radiation Control for Health and Safety Act of 
1968", there is a need for suitable portable equipment for making 
measurements connected with the testing of diagnostic X-ray equipment for 
compliance with this Act, for example, measurements to test the ability of 
the AC power supply to meet the equipment's minimum requirements, as 
specified by the manufacturer. Specifically, there is a need to measure 
accurately the true-RMS voltage, frequency, and percent regulation of the 
AC power supply, and to obtain clear displays of this information. 
Previously employed measuring equipment suffered from lack of adequate 
resolution and accuracy, limited voltage range, lack of means to compute 
percent regulation, and degradation of voltage accuracy with variation of 
the input frequency. Thus, there is a need for portable measuring 
equipment which can record small voltage changes, for example, as small as 
0.1 volt, which can accurately compute percent regulation, and which can 
measure inputs at least from about 16 Hz to about 1.6 kHz. 
A preliminary search of the prior art revealed the following prior U.S. 
Pat. Nos. of interest: 
Wright, 3,205,347, 
Platzer et al, 3,423,578, 
Plante, 3,657,528, 
Engel, 3,743,949, 
Allen, 3,840,813, 
Silberberg, 4,006,413, 
Funk, 4,080,568, 
Buhlmann, 4,125,895. 
SUMMARY OF THE INVENTION 
The instrument of the present invention may be employed for examining AC 
supply performance through determination of line voltage regulation, as 
specified for example in 21 CFR 1020.30, "Performance Standards for 
Electronic Products: Diagnostic X-ray Systems and their Major Components", 
promulgated under P.L. 90-602, "The Radiation Control for Health and 
Safety Act of 1968". The instrument is intended to provide the measurement 
capability required for the enforcement of this performance standard, but 
may be employed for a wide range of general-purpose applications. 
The instrument of the present invention can be constructed so as to be 
capable of measuring DC voltage and AC voltage and frequency over a 
relatively wide frequency range, for example, 16 to 1600 Hz; with input 
signals between 60 and 600 volts, the maximum voltage error can be held to 
.+-.0.2 volt over this frequency range; from 16 to 100 Hz, the instrument 
can compute the RMS value of the input voltage for each cycle with a 
frequency error of less than .+-.0.1 Hz. The instrument can measure the 
maximum and minimum RMS voltage over the measurement interval employing a 
general procedure described in FDA report #FDA 74-8025, "A line Voltage 
Monitor for Determining AC Supply Regulation to a Diagnostic X-ray 
Source". In addition, the instrument can provide an on-line display of the 
input voltage and compute and display percent regulation from the measured 
maximum and minimum voltage values. 
The instrument incorporates analog and digital circuitry and microcomputer 
(.mu.C) hardware and software to achieve high accuracy, high speed, and 
minimal loss of data. The instrument comprises a microcomputer and 
remaining circuitry serving in input data to an output data from said 
microcomputer. Analog input circuitry attenuates and squares the input 
voltage. A voltage-to-frequency (V/F) converter produces logic pulses at a 
rate proportional to the squared signal. A 16-bit counter integrates 
V.sup.2 by accumulating pulses from the V/F converter. 
A second 16-bit counter increments at a 1 MHz rate to determine the cycle 
period of the input in microseconds. The dedicated microcomputer (.mu.C) 
divides .intg.V.sup.2 by the period and then takes the square root, 
yielding the RMS value of the input voltage. A switch may be set so that 
the .mu.C inverts the cycle period to determine the input frequency rather 
than the RMS voltage. 
The AC input signal is assumed to exhibit two zero-crossings per cycle. 
(Processing of DC signals will be explained later). A comparator detects 
negative zero-crossings of the input and triggers a timing control. When 
this occurs, the timing control first causes the contents of both 16-bit 
counters to be stored in latches and then resets the counters. At the same 
time the counters are reset, the .mu.C is interrupted and responds by 
reading the contents of both 16-bit latches. The latch on the signal 
channel will contain 
##EQU1## 
and the other latch will contain nT, a multiple of the signal period. 
Possible values of n are 1, 2, 4, 8, and 16, determined by the setting of 
a switch, as will be later explained. 
The .mu.C maintains four storage locations for percent regulation (percent 
REG), maximum RMS voltage (VMAX), minimum RMS voltage (VMIN), and on-line 
RMS voltage (V.sub.RMS.sup.(t)). The RMS value computed every n cycles is 
stored in the V.sub.RMS.sup.(t) location. VMAX is updated whenever the new 
V.sub.RMS.sup.(t) value is greater than the previous VMAX, and VMIN is 
updated whenever the new V.sub.RMS.sup.(t) value is less than the previous 
VMIN. The percent regulation is determined as follows: Percent 
REG=[(VMAX-VMIN)/VMIN] (100 percent). This value is recomputed each time 
that data is read from the latches whether or not VMAX or VMIN has been 
updated. 
Approximately four times a second the .mu.C reads the setting of a front 
panel switch which instructs it to display either percent REG, VMAX, 
V.sub.RMS.sup.(t), or VMIN. The .mu.C then stores the appropriate 
numerical value in the display drivers. The data is normally displayed in 
a four-digit format, with one digit to the right of the decimal point. 
Accordingly, a main object of the invention is to provide a novel and 
improved instrument for measuring true-RMS line voltage, frequency, 
percentage regulation, and other required data, the instrument overcoming 
the deficiencies and disadvantages of prior art devices heretofore 
employed for such measurements. 
A further object of the invention is to provide an improved portable 
apparatus for measuring true-RMS voltage, frequency and percent regulation 
of AC power supplies, the instrument being compact in size, being light in 
weight, being safe to use, and being capable of measuring AC voltage with 
a very low percent error over a wide range of voltages and frequency. 
A still further object of the invention is to provide an improved line 
voltage monitor apparatus which is capable of measuring DC voltage and AC 
voltage and frequency over a wide range of frequency and voltages, which 
accurately measures maximum and minimum RMS voltage over a measurement 
interval, which has high resolution, which provides an on-line display of 
input voltage, and which computes and displays percent regulation from the 
measured maximum and minimum voltage values. 
A still further object of the invention is to provide an improved line 
voltage monitoring apparatus which accurately measures maximum and minimum 
RMS voltage over a measurement interval, which incorporates improved 
analog and digital circuitry and microcomputer hardware and software to 
achieve high accuracy, high speed and minimum loss of data, which can 
measure DC voltage and AC voltage and frequency over a relatively wide 
range of voltage and frequency, and which accurately computes and displays 
percent regulation from measured maximum and minimum voltage values, as 
well as providing an on-line display of input voltage. 
A still further object of the invention is to provide an improved line 
voltage monitor for determining AC supply regulation for diagnostic X-ray 
equipment and similar apparatus. 
A still further object of the invention is to provide an improved line 
voltage monitoring instrument which is highly accurate, has high 
resolution and has a rapid response. 
A still further object of the invention is to provide an improved AC line 
monitoring instrument which measures, computes and stores true-RMS line 
voltages and which measures and computes all necessary information for 
determining the adequacy of a power source to be used with diagnostic 
X-ray equipment, the instrument having means to provide a clear display of 
the information.

DESCRIPTION OF A PREFERRED EMBODIMENT 
Referring to the drawings, and more particularly to FIG. 1, the line 
voltage monitor is designated generally at 12. The monitor has input 
terminals 13, 14 leading to a differential amplifier 15 which derives the 
voltage signal V.sub.3. The output of amplifier 15 is supplied to a 
squaring multiplier 16 and one input terminal of a comparator 17, the 
other input terminal thereof being grounded. The multiplier 16 derives the 
squared voltage signal V.sup.2, which is furnished to a 
voltage-to-frequency converter 18 which produces a logic pulse train 
signal f(V.sup.2) which is fed to a first 16-bit counter 19. The logic 
pulses of the signal f(V.sup.2) are produced at a rate proportional to the 
squared voltage signal V.sup.2. The 16-bit counter 19 integrates the 
V.sup.2 signal by accumulating the pulses from the V/F converter 18. A 
second 16-bit counter 20 is incremented at a 1 MHz rate by a 1 MHz 
oscillator 21 to determine the cycle period of the input in microseconds. 
The reset line for the counters 19, 20 is shown at 22. 
The first 16-bit counter 19 has a binary output 25 which is supplied to a 
16-bit latch 23, time-controlled by comparator 17 via a timing control 
circuit 24, also reset from line 22. The second 16-bit counter 20 has a 
binary output 26 which is supplied to a 16-bit latch 27. 
The binary output 28 of the 16-bit latch 23, representing the integrated 
V.sup.2 value, and the binary output 29 of the second 16-bit latch 27, 
representing the cycle period T, are furnished to a dedicated 
microcomputer 30, which divides the integrated V.sup.2 value by the period 
T and then takes the square root, yielding the RMS value of the input 
voltage in binary form. This value is then output at 70 and is 
subsequently displayed in the LCD display assembly, shown at 33, via 
display drivers, shown generally at 34. The address output at 31 is 
decoded by an address decoder 32 to supervise and control the flow of data 
on the data bus. 
INPUT CIRCUITRY 
Referring to FIGS. 1, 2, 3 and 3A, it will be seen that the input circuitry 
comprises means to process the input signal, convert it to digital 
(binary) form, and to place the binary data on the microcomputer data bus 
28 when requested by the microprocessor circuitry. The analog circuitry is 
shown in detail in FIG. 2. The differential amplifier 15 of FIG. 1 
comprises operational amplifiers A.sub.1 and A.sub.2. The input resistance 
seen by V.sub.1 and V.sub.2 is greater than 900K. The output of amplifier 
A.sub.1 is (-1/81.8)V.sub.1. With switch S.sub.4a open (300-volt scale), 
the output of A.sub.2 is V.sub.3, where V.sub.3 =(-1/40.9)V.sub.2 
-2(1/81.8)V.sub.1 =(V.sub.1 -V.sub.2)/40.9. With switch S.sub.4a closed 
(600-volt scale), V.sub.3 =(-1/81.8)V.sub.2 -(-1/81.8)V.sub.1 =(V.sub.1 
-V.sub.2)/81.8. Amplifiers A.sub.1 and A.sub.2 are contained in a single 
SN72747 package. Not shown in FIG. 2 are respective offset adjustment 
trimpots for A.sub.1 and A.sub.2, which are adjusted to minimize the 
offset voltage of the amplifiers. 
The output V.sub.3 of the differential amplifier is squared by a Burr-Brown 
4204K multiplier 16. The trim procedure used to adjust the offset and 
feedthrough of the multiplier is shown in FIG. 2. The output of the 
multiplier, which is V.sub.3 /10).sup.2, is converted to a train of 
TTL-compatible logic pulses approximately 350 nsec wide, having a 
frequency proportional to (V.sub.3 /10).sup.2. This conversion is 
performed by a Teledyne-Philbrick Model 4705 V/F converter 18. The 200 ohm 
trimpot 37 is used to adjust the gain of the V/F converter 18, and a 
trimpot, not shown, is used to adjust the offset for best performance. 
Amplifier A.sub.3 (an MC1456 operational amplifier), diode D.sub.1, two 
resistors, and one capacitor comprise the low-noise comparator 17. When 
the input signal (V.sub.1 -V.sub.2) is positive, the timing reference is a 
logic "1". When the input signal is negative, the timing reference is a 
logic "0". The timing reference, as well as the V/F converter output 
(f(V.sup.2)) are connected to the circuitry of FIG. 3, which comprises the 
digital portion of the input circuitry. 
Data input to the microcomputer 30 each sample period (nT) includes the 
contents of the two 16-bit counters 19, 20 and the settings of panel 
switches S.sub.9 and S.sub.3 -S.sub.6 (FIGS. 2 and 3A). When switch 
S.sub.7 (the AC/DC switch, FIG. 3) is in the AC position, the sample 
period is derived from the timing reference signal generated by the 
circuitry of FIG. 2. For the measurement of DC signals (when switch 
S.sub.7 is in the DC position), a timing reference of 61 Hz is provided by 
the Q.sub.14 output of a 14-bit binary counter 35(MC14020 in FIG. 3) which 
is clocked by .phi..sub.1 of the microcomputer clock 57 (FIG. 8). This 
frequency is generated to drive the liquid crystal display and thus is 
available. Conveniently, 61 Hz is within the 1 cycle-per-sample range (see 
Table I below). 
The timing reference selected by switch S.sub.7 (FIG. 3A) clocks a 4-bit 
binary counter 38 (1/2 MC14520) which provides frequency division by 2, 4, 
8, and 16. The setting of the cycles-per-sample switch S.sub.8 (FIG. 3A) 
determines the number of cycles (n) of the input signal in each sample 
period by triggering a one-shot, OS.sub.1, at 1, 1/2, 1/4, 1/8, or 1/16 
times the frequency of the input signal. As a result, the microcomputer 30 
computes the RMS voltage of the input signal every n cycles. Selection of 
n greater than 1 enables the instrument to measure RMS voltage at 
frequencies greater than 100 Hz (up to 1.6 kHz for the maximum selected 
value of n). 
The frequency range over which the instrument operates properly for each 
setting of switch S.sub.8 is listed below in Table I. For each entry, the 
lower frequency limit prevents overflow of the period counter and the 
upper limit assures adequate resolution in the .intg.V.sup.2 counter for 
.+-.0.2 volt accuracy above 60 volts on the 300-volt scale and 120 volts 
on the 600-volt scale. Observation of the upper frequency limit will also 
insure the normal rate of data output to the liquid crystal display from 
the microcomputer. An input signal frequency below the lower limit of a 
range will cause overflow in the period counter. A signal frequency above 
the upper limit will cause the display to update very infrequently, or not 
at all. 
TABLE I 
______________________________________ 
S.sub.8 setting 
Recommended 
(Cycles per sample) 
frequency range (Hz) 
______________________________________ 
1 16-100 
2 32-200 
4 65-400 
8 125-800 
16 350-1600 
______________________________________ 
The signal selected by switch S.sub.8 triggers the one-shot OS.sub.1 (FIG. 
3) on each negative transition. The output pulse of OS.sub.1, which is 
approximately 1 microsecond wide, signals an end to the most recent 
measurement period by stopping the two 16-bit counters 19, 20 
(.intg.V.sup.2 and nT) and storing the counter contents in the latches 23, 
27. The one-shot OS.sub.2 is triggered by the falling edge of the Q output 
of OS.sub.1. The output pulse of OS.sub.2, approximately 1.5 microseconds 
wide, signals the beginning of a new sample period by resetting the 16-bit 
counters 19, 20. In addition, an interrupt latch flipflop 39 (1/2 CD4013, 
FIG. 3) is set to signal the processor that data is ready for input. 
The settings of switches S.sub.3 -S.sub.6 and S.sub.9, and the state of the 
overflow flipflop 40 (FIG. 4) are latched by latches 41, 42 (FIG. 3A) each 
microprocessor clock cycle so that the signals read by the microcomputer 
do not change during data input. The codes corresponding to the positions 
of switches S.sub.3 -S.sub.6 and S.sub.9 are listed below in Table II. The 
codes for switch S.sub.6 are generated using the diode-resistor logic 
shown at 43 in FIG. 3A. 
TABLE II 
______________________________________ 
Switch Code Function 
______________________________________ 
S.sub.3 Sample/Hold 
0 Hold 
1 Sample 
S.sub.4b Scale 
0 300 v. scale 
1 600 v. scale 
S.sub.5 Test Display 
0 Test display 
1 Normal display 
S.sub.6 Display 
00 Display VMIN 
01 Display V(t) 
10 Display VMAX 
11 Display percent REG 
S.sub.9 Compute 
0 Compute Voltage 
1 Compute Frequency 
______________________________________ 
It is to be noted that S.sub.4a -S.sub.4b is a ganged two-pole switch. One 
pole controls the gain of the differential amplifier 15 and the other 
instructs the microcomputer to compensate for the frontend gain 
accordingly. 
The overflow signal is produced by the circuit of FIG. 4 from negative 
transitions of the most significant bits of the 16-bit counters 19, 20 
(voltage and time overflow). The voltage and time overflow bits may 
exhibit negative transitions under normal conditions during reset of the 
16-bit counters 19, 20. To distinguish between normal and overflow 
transitions, the signal used to clear the counters is inverted and applied 
to the clear inputs of one-shots OS.sub.3 and OS.sub.4. In this manner, 
only an actual counter overflow will trigger the corresponding one-shot 
and set the overflow flip-flop 40. The overflow flipflop 40 is cleared 
when the microcomputer is reset by switch S.sub.2 (see below). 
Data is input into the microcomputer 30 from the circuitry of FIG. 3 by 
enabling the tri-state output of the MC14076B latches (shown at 23, 27), 
which places the data on the microcomputer data bus 28, 29. The B-series 
CMOS used has sufficient output current to drive the data bus. The latch 
outputs are enabled by the M5000 . . . M5004 signals, which are generated 
by the address decoder 32. "500X" corresponds to the address output by the 
microcomputer when reading in the data. An address of 5005, which is put 
out by the microcomputer to acknowledge that the interrupt is being 
handled, resets the interrupt latch 39. 
DISPLAY CIRCUITRY 
The liquid crystal display 33 is driven by and displays the contents of a 
driver assembly 34 comprising two CD4054 LCD drivers 44 and four CD4056 
LCD drivers 45 (see FIG. 5). The backplane is driven between +5 and -10 
volts at the 61 Hz driving frequency generated by the MC14020 14-bit 
counter 35 shown in FIG. 3. Segments of the display are transparent when 
driven in phase and are opaque when driven out of phase with the backplane 
drive signal. The 45D7R03 LCD display 33 provides good legibility with low 
power consumption. 
The four least significant digits of the display are output two digits at a 
time when the processor stores data in the CD4056 drivers 45, configured 
at locations 9001 and 9002. This is accomplished using a CMOS replica of 
the microcomputer data bus (CD.sub.0 . . . CD.sub.7) generated by 74LS367 
buffers 46(FIG. 5A) and 1000-ohm pullup resistors 47. The CD4056 drivers 
45 each contains a 4-bit latch for storing 1 BCD digit, and a 
binary-to-seven segment decoder for driving the display. When location 
9001 or 9002 is addressed by the microcomputer 30, a store pulse is 
generated by the address decoder 32 to strobe the appropriate latches, via 
a line 47 in FIG. 1. The decimal point location, minus sign, overflow 
indication, and half-digit are all coded in location 9000, as shown in 
FIG. 6. Data output by the microcomputer 30 to the CD4054 drivers, 
configured at location 9000, is stored in the internal latches of the 
CD4054 display drivers 44. 
A display request is generated approximately four times a second by the 
circuitry shown in FIG. 7. The 61 Hz driver frequency (DF) signal is 
divided by 16, using a MC14520 binary counter 48. Each negative-going 
transition of the Q.sub.4 output of the counter 48 triggers a simple 
one-shot comprising a NAND gate 49, a NOR gate 50, and a capacitor 51. 
This in turn sets the display request latch comprising two NOR gates 52, 
53, causing the display request signal to go high. The display request is 
cleared (reset) when data is subsequently stored in location 9000. In 
addition to the states of switches S.sub.9 and S.sub.3 -S.sub.6 and of the 
overflow flipflop 40, the state of the display request is made available 
to the microcomputer 30 when it reads location 5004. Under the constraints 
of Table I, each display request is serviced by the microcomputer. 
MICROCOMPUTER HARDWARE 
Referring to FIGS. 8 and 8A, the microcomputer 30 comprises an M68B00 
microprocessor 54; an MCM68B10L 128.times.8 random access memory (RAM), 
shown at 55; 2 K.times.8 programmable, read-only memory (PROM), shown at 
56; and an MC6870A 1 MHz crystal oscillator 57. The address (A.sub.0 . . . 
A.sub.15), data D.sub.0 . . . D.sub.7) and control lines are connected 
according to the correspondingly labelled terminals in FIGS. 8 and 8A. The 
halt line of the processor 54 is tied high, with a pull-up resistor 58, so 
that the processor may be halted by a clip-on logic analyzer probe during 
trouble shooting. The interrupt signal from the interrupt latch 39 (FIG. 
3) is inverted by a single transitor stage 59 to provide the proper signal 
polarity and sink current for the IRQ input of the microprocessor. An RC 
circuit on the reset input of the processor holds the reset line low for 
multiple machine cycles after either a power-up or depression of switch 
S.sub.2. The RC stage is buffered by CMOS inverters 60, 61 to reduce 
loading effects on the time constant and to square up the signal. 
ADDRESS DECODER 
Referring to FIG. 8A, the address decoder 32 comprises 74LS139 and 74LS138 
decoders 62, 63 and several gates 64, 65. Low-power schottky (LS) TTL is 
used rather than CMOS for speed in address decoding. 1000-ohm pull-up 
resistors 66 are used wherever the microprocessor or any LSTTL circuitry 
drives CMOS, such as the outputs of the 1-of-8 decoder 63. 
Half of the 74LS139 (dual 1-of-4) decoder 62 is used to partition the 
memory into 4 segments: RAM, input, output, and PROM (see FIG. 9). When 
A.sub.15 A.sub.14 is 01 (binary), Y.sub.1 goes low, enabling the 74LS138 
(1-of-8) decoder 63. The 74LS138 decoder 63 subsequently decodes the three 
least significant address bits to select an 8-bit byte or to reset the 
interrupt latch. 
When A.sub.15 A.sub.14 is 11, Y.sub.3 goes low, enabling the PROM 56. When 
A.sub.15 A.sub.14 is 10, Y.sub.2 goes low. Y.sub.2 is subsequently gated 
with the .phi..sub.2 clock and "read/write" (R/W) to enable the second 
half of 1-of-4 decoder 62. Store pulses are then generated for the three 
bytes of display latches (S9000 . . . S9002) as determined by the A.sub.0 
and A.sub.1 address lines. The MCM68B10L (RAM 55) contains sufficient 
decoding logic to detect the 00 state of A.sub.15 A.sub.14. Thus, it is 
not necessary to use the Y.sub.0 output of the first 1-of-4 decoder 62. 
The addresses are assigned so that there would be no interference with 
memory resident in the software development facility used in writing and 
testing the line voltage monitor program. For this reason, several 
"don't-care" bits are assigned to logic "1" in the input, output, and PROM 
address designations (FIG. 10). Hexadecimal notation is used throughout in 
referring to the address of memory locations. 
MICROCOMPUTER SOFTWARE 
The line voltage monitor program occupies 13/4 k of ROM, the majority of 
which consists of general-purpose library subroutines. Less than 1/2 k of 
ROM is occupied by the software specific to the line voltage monitor. 
General-purpose subroutines provide such functions as basic arithmetic, 
square-root, the format conversion. The LVM-specific routines read data 
from the latches designated M5000 through M5004, process the data, and 
store the results in the display circuitry located from S9000 through 
S9002. 
When the processor is interrupted at the end of each sample period (nT), it 
responds within 1 msec under normal conditions. In response, the processor 
first sets the interrupt mask so that it can process one sample completely 
before reading in another. This is a preventive measure only. Successive 
samples do not interfere under the voltage and frequency constraints of 
Table I. After setting the interrupt mask, the microprocessor acknowledges 
the interrupt by addressing location 5005. The setting of the sample/hold 
switch (S.sub.3) is then read from location 5004. If S.sub.3 is set to 
hold, the sample is not processed and the microprocessor resumes the 
display routine described below. If S.sub.3 is set to sample, however, the 
microprocessor proceeds by reading .intg.V.sup.2 from locations 5000 and 
5001 as a 16-bit integer and converting it to a floating-point binary 
number. 
The floating-point format used is shown in FIG. 11, and some examples are 
listed in Table III, below. Three bytes are used to represent each number: 
one byte for the two's complement exponent, one sign bit, and 15 bits for 
the straight-binary mantissa. The mantissa is always normalized such that 
the most significant bit is a "1" except for the number zero, which is 
represented as 80 0000(+0) or 80 0000(-0). The binary point is assumed to 
be to the left of the most significant mantissa bit. As a result, the 
(nonzero) mantissa alone represents a fraction between 0.50 and 0.99997 
(decimal). This floating-point format provides a dynamic range of 
10.sup.-38 to 10.sup.+38 and a resolution of 0.00305 percent (1 part in 
32,768). 
TABLE III 
______________________________________ 
Floating-point notation 
Decimal equivalent 
______________________________________ 
80 0000 0.0000 
01 4000 1.0000 
01 C000 -1.0000 
00 4000 0.5000 
00 6000 0.7500 
FA 51EC 0.0100 
FO 53E3 1.0000 .times. 10.sup.-5 
04 5000 10.000 
07 6400 100.00 
22 4A81 1.0000 .times. 10.sup.10 
______________________________________ 
After .intg.V.sup.2 is converted to floating point, the period nT is read 
from locations 5002 and 5003 and also converted to floating point. The 
setting of S.sub.9 is then read drom location 5004. If S.sub.9 is a logic 
"1", the period nT is inverted to determine F/n, the frequency of the 
input signal divided by n. In this mode, the values displayed by the LVM 
are actually FMIN, F(t), FMAX, and % REG of the frequency. FMIN, FMAX, and 
% REG of the frequency are determined in a manner analogous to the 
determination of VMIN, VMAX, and % REG of voltage (see below). 
If S.sub.9 is a logic "0", the LVM continues the calculation of RMS voltage 
by performing the division .intg.V.sup.2 /nT and then taking the square 
root. The setting of the scale switch S.sub.4b is read from location 5004. 
The result of the square-root operation is multiplied by 409 is S.sub.4b 
is set to the 300 volt scale, and by 818 if S.sub.4b is set to the 600 
volt scale. This compensates for the division by 10 performed by the 4204K 
multiplier 16 of FIG. 2 and the attenuation by 1/40.9 (for the 300 volt 
scale) or 1/81.8 (for the 600 volt scale). This completes the computation 
of the RMS value of one sample of the input voltage. 
The RMS value computed from the input sample is stored in a location 
reserved for V(t) in the RAM 55. V(t) is then compared to the previous 
maximum and minimum. If V.sub.RMS (t) is larger than the previous maximum 
or smaller than the previous minimum, that value is replaced by storing 
V.sub.RMS (t) in the appropriate RAM location reserved for VMAX or VMIN. 
If V.sub.RMS (t) is between VMIN and VMAX, the previous values remain 
unchanged. The percent regulation is computed from VMAX and VMIN, using 
the formula previously given above, and stored in a RAM location reserved 
for percent REG. 
After computing percent regulation, the processor clears the interrupt mask 
and resumes its normal activity, the output of data to the display. The 
microprocessor monitors location 5004, awaiting a display request. When 
one is detected, the state of the test display switch S.sub.5 is read from 
location 5004. If S.sub.5 is a "1", the display test sequence is not 
executed. If S.sub.5 is a "0", the display is tested by first turning on 
and then off all segments of interest. A display of .rarw.1.8.8.8.8 is 
produced by storing FF 8888 in locations 9000 . . . 9002. Then the display 
is blanked by storing OO FFFF in the same location. The display test 
sequence executes in approximately two seconds when the processor is in 
the hold mode or the input frequency is close to the lower limit of Table 
I. The same sequence can require over 8 seconds for execution when the 
input frequency is close to the upper limit of Table I. 
Whether S.sub.5 was in a "0" or "1" state, the processor proceeds by 
reading the display code generated by S.sub.6 from location 5004. The 
quantity selected for display is read from its reserved location in RAM 55 
and converted from floating-point-binary to binary-coded-decimal (BCD) 
notation. The status of the overflow flipflop 40 is then read from 
location 5004. If counter overflow has occurred, an overflow indication is 
added to the display code (FIG. 6). The BCD number is then stored in the 
latches of the display drivers at locations 9000, 9001 and 9002 (FIG. 5). 
Again, storage of data in location 9000 resets the display request latch. 
The processor returns to monitoring location 5004 for the next display 
request. 
In displaying numerical data, a distinction is made between numerical 
overflow and counter overflow. Although the overflow indication (arrow) is 
displayed in either case, conversion of a number larger than 9999 to BCD 
results in a display of .rarw.19999. Counter overflow can occur when the 
frequency of the input signal is below the lower limits presented in Table 
I. This condition is latched; therefore, loss of several cycles of the 
input signal (as from power line irregularities or intermittent 
connections) can cause an overflow indication to be displayed along with a 
valid VMAX or V.sub.RMS (t). In general, however, counter overflow may be 
displayed along with a valid or invalid numerical value. Once the input 
frequency has been restored to within the limits of Table I, resetting the 
instrument will clear the overflow indication. 
Actuation of the reset switch S.sub.2 at any time resets the microprocessor 
and prevents execution of any instructions. When S.sub.2 is released, VMIN 
is initialized to the largest number representable in the floating-point 
format and the VMAX is initalized to zero. This assures that the first 
sample after a reset will replace both the initialized VMAX and VMIN. The 
effect of subsequent samples has been described above. 
From the above description it will be seen that the incorporation of a 
microprocessor into an instrument for measuring AC voltage can provide 
greatly improved accuracy as over previous versions of such instruments, 
greatly expanded frequency range over which such accuracy can be obtained, 
and permits the inclusion of such features as display test, overflow 
indication, frequency measurement, and computation of percent regulation. 
Another key feature is fast response. The bandwidth of the front end is 
greater than 2.5 kHz, and the instrument is capable of computing frequency 
or RMS voltage for each cycle of the input signal from 16 to 100 Hz, 60 to 
600 volts. The instrument is also capable of measuring DC voltage from 60 
to 800 volts. The instrument can be packaged in a relatively small 
carrying case and is relatively light is weight. 
Although the instrument has been configured to measure AC line voltage, 
changing the gain of the differential amplifier 15 and the corresponding 
correction factor would permit its use over a wide range of input 
voltages. Also, it would be a relatively simple matter to output the data 
bus and the S9000, S9001 and S9002 lines to a digital printer for hard 
copy of the measured data. The instrument could easily be adapted to 
measure AC current or, with the proper transducer, any physical quantity 
for which maximum, minimum, or percent change information is of interest. 
Attached hereto is a listing of the programs embodied in the program memory 
of the invention.