Circuit module, semiconductor integrated circuit, and inspection apparatus and method thereof

A circuit module includes a shift register constituting part of a scan chain within a semiconductor integrated circuit, a control unit for controlling an operation of the shift register using a control signal generated within the semiconductor integrated circuit and a selection unit for selecting between a short-circuit path through which a scan signal is loaded and an ordinary path through which the scan signal is loaded after being made to go through the shift register, where the ordinary path is selected when the operation of the shift register is permitted by the control signal and the short-circuit path is selected when the operation of the shift register is not permitted.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2009-072182 filed on Mar. 24, 2009, the entire contents of which are incorporated herein by reference.

BACKGROUND

Various embodiments described herein relate to a circuit module used to perform a scan test, a semiconductor integrated circuit, and an inspection apparatus used to inspect scan data and method of implementing same.

2. Description of the Related Art

Typically, as a means for achieving the low power consumption of a semiconductor integrated circuit, there has been known a technique to control a clock signal supplied to data-retaining elements constituting a sequential circuit, such as flip-flops and latches. The technique to control a clock signal is intended to, for example, stop the operation of each circuit module within the semiconductor integrated circuit for which data is not updated according to the operation thereof, by not supplying a clock signal to the circuit module. In the technique to control a clock signal, the clock signal is controlled by a clock gating circuit having at least a control signal and a clock signal as the inputs thereof. The control signal for controlling the supply of the clock signal is generated within the semiconductor integrated circuit.

For example, if the control signal input to the clock gating circuit permits a supply of the clock signal, then the clock gating circuit outputs the clock signal. In contrast, if the control signal does not permit a supply of the clock signal, then the clock gating circuit outputs data fixed to, for example, 0 or 1.

In addition, as a means for achieving the low power consumption of a semiconductor integrated circuit, there has been known a technique to control a power supply voltage (hereinafter referred to as power). The technique to control power is intended to, for example, stop the operation of a circuit module for which data is not updated according to the operation of the semiconductor integrated circuit, by not supplying power to the circuit module. In the technique to control power, power is controlled by a power gating circuit having at least a control signal and power as the inputs thereof. The control signal is generated by a control signal generation circuit within the semiconductor integrated circuit.

Furthermore, as a technique to make easy a test of a semiconductor integrated circuit, there has been a typical scan test. The scan test is a technique to control or observe the interior portion of a semiconductor integrated circuit using only a small number of I/O (Input/Output) terminals external to the semiconductor integrated circuit. In the scan test, data-retaining elements within the semiconductor integrated circuit are replaced with data-retaining elements for scan testing in order to constitute a shift register.

Next, in test mode, a shift register is formed by serially connecting data-retaining elements for scan testing. Thus, there is configured a scan chain whereby the data-retaining elements for scan testing may be controlled or observed from I/O terminals external to the semiconductor integrated circuit.

Still furthermore, as a means for reducing the scan test time of a semiconductor integrated circuit, there has been a typical technique to switch the output of each module including data-retaining elements constituting a scan chain, using a selection circuit (U.S. Pat. No. 2,676,169). A selection is made using the selection circuit, as to whether the output data of a shift register within the module in question is output to other circuit modules or a scan signal is output to other circuit modules without letting the scan signal go through the shift register.

SUMMARY

In accordance with an aspect of embodiments, a circuit module and method thereof is provided. The circuit module includes a shift register constituting part of a scan chain within a semiconductor integrated circuit, a control unit for controlling an operation of the shift register using a control signal generated within the semiconductor integrated circuit, and a selection unit for selecting between a short-circuit path through which a scan signal is loaded and an ordinary path through which the scan signal is loaded after being made to go through the shift register, where the ordinary path is selected when the operation of the shift register is permitted by the control signal and the short-circuit path is selected when the operation of the shift register is not permitted.

DETAILED DESCRIPTION OF EMBODIMENTS

At a time of scan-testing a semiconductor integrated circuit, circuit modules including data-retaining elements constituting a scan chain are all connected to one another and, therefore, must always be brought into operation. Accordingly, at the time of scan-testing a semiconductor integrated circuit including a clock/power gating circuit for controlling the above-described operation, modules are enabled irrespective of control by the clock/power gating circuit. Thus, there is the problem that extra labor is required in a scan test.

Another problem is that it is unknown what scan data is output in a shift register within a circuit module which need not be enabled depending on a type of scan test. Therefore, a designer needs to ascertain what data is going to be output. Thus, there has been the problem that a scan test is difficult to perform. In addition, there is the need to ascertain, for example, whether the scan data of other circuit modules constituting the scan chain is affected by any unneeded circuit modules. Thus, there is the problem that debugging is difficult to perform.

Furthermore, in a technique to switch the output of each circuit module using a selection circuit, there has been the problem that in the case of a semiconductor integrated circuit including a gating circuit for controlling operation, there arises such extra labor as performing control from the outside on the basis of information provided by a control signal input to the gating circuit. In addition, a designer must ascertain whether the control signal is input from an input terminal with a precise timing. Thus, there is the problem that a scan test is difficult to perform.

Furthermore, the technique to switch the output of each circuit module using a selection circuit requires an input terminal for inputting a control signal to each circuit module. Thus, there is the problem that shortage occurs in input terminals for inputting the control signal.

In order to solve the above-described and other problems involved in the related art, examples of the present disclosed technique are intended to provide a circuit module, a semiconductor integrated circuit, and an inspection apparatus capable of promoting the efficiency of a scan test and reducing a test time by diverting an operation-controlling control signal generated within the semiconductor integrated circuit.

Hereinafter, preferred embodiments of a circuit module, a semiconductor integrated circuit and an inspection apparatus in accordance with the present disclosed technique will be described in detail with reference to the accompanying drawings. In the present embodiment, an explanation will be made by using a circuit module in which a path is selected by a control signal for controlling a supply of a clock signal to a shift register. Note that no explanation will be made of the way a path is selected by a control signal for controlling a supply of power to the shift register.

In an embodiment, either a short-circuit path for loading a scan signal or an ordinary path for loading the scan signal by letting the scan signal go through the shift register is selected on the basis of a control signal for controlling the operation of the shift register. Consequently, by diverting the control signal generated within the semiconductor integrated circuit, it is possible to promote the efficiency of a scan test. It is also possible to reduce a scan test time.FIGS. 1A to 1Cillustrate the semiconductor integrated circuit and the circuit module in accordance with an embodiment.

FIG. 1Ais an explanatory drawing illustrating a semiconductor integrated circuit and a circuit module in accordance with an embodiment. A semiconductor integrated circuit100is comprised of a circuit module M constituting a scan chain, a plurality of circuit modules (dotted arrows indicate that the plurality of circuit modules is included) constituting the scan chain, a control signal generation circuit101, an input terminal104, and an output terminal105. Note that the direction of arrows indicates the direction of data flow.

In the present embodiment, the control signal generation circuit101generates a control signal for controlling whether or not to supply a clock signal. Note that, as described above, an explanation will be made by taking a clock gating circuit as an example in the present embodiment, and an explanation in which a power gating circuit is taken as an example will not be made. A control signal of the circuit module M for controlling whether or not to supply the clock signal is denoted by EN_M.

The circuit module M is comprised of a clock gating circuit102, FFs (Flip-Flops)7to12, and a selection circuit103. In the present embodiment, an explanation will be made by using the FFs as data-retaining elements. The FFs7to12form a shift register constituting part of the scan chain within the semiconductor integrated circuit. A scan signal is shifted in synchronization with the clock signal from the FF7to the FF8, from the FF8to the FF9, and so on.

Signals EN_M and CLK are input to the clock gating circuit102. The reference character CLK denotes the clock signal. If the control signal EN_M is 0, then the clock gating circuit102does not supply the clock signal to the FFs7TO12. If the control signal EN_M is 1, then the clock gating circuit102supplies the clock signal to the FFs7to12. Accordingly, the state of the control signal EN_M being 0 means that the operation of the shift register is not permitted. In contrast, the state of the control signal EN_M being 1 means that the operation of the shift register is permitted.

Next, the control signal EN_M, the scan signal and the output data of the FF12are input to the selection circuit103. If the control signal EN_M is 0, then the selection circuit103selects a path through which the scan signal is output. If the control signal EN_M is 1, then the selection circuit103selects a path through which the output data of the FF12is output. The former path is referred to as a short-circuit path and the latter path is referred to as an ordinary path. An ordinary path will be illustrated usingFIG. 1Band a short-circuit path will be illustrated usingFIG. 1C.

FIG. 1Bis an explanatory drawing illustrating an ordinary path. If the control signal EN_M is 1, then an ordinary path is selected by the selection circuit103. In the ordinary path, the clock signal is supplied to the shift register. Accordingly, the scan signal input to the circuit module M goes through the shift register (denoted by thick-line arrows). The output data of the FF12is selected by the selection circuit103and is output from the circuit module M. Next, the short-circuit path will be illustrated usingFIG. 1C.

FIG. 1Cis an explanatory drawing illustrating a short-circuit path. If the control signal EN_M is 0, then the short-circuit path is selected by the selection circuit103. In the short-circuit path, the clock signal is not supplied to the shift register. Accordingly, the scan signal input to the circuit module M is selected by the selection circuit103without being made to go through the shift register, and is output from the circuit module M. Next, a plurality of circuit modules constituting the scan chain will be illustrated usingFIGS. 2A and 2B.

FIG. 2Ais an explanatory drawing illustrating a plurality of circuit modules constituting a scan chain. A semiconductor integrated circuit200is comprised of a circuit module L, a circuit module M, a circuit module N, a plurality of other circuit modules (dotted-line arrows indicate that a plurality of circuit modules is included), a control signal generation circuit201, an input terminal104, and an output terminal105. The circuit module M within the semiconductor integrated circuit200is the same in configuration as the circuit module M within the semiconductor integrated circuit100.

The circuit module L is comprised of a clock gating circuit202, a selection circuit203, and FFs1to6. The FFs1to6form a shift register constituting part of a scan chain within the semiconductor integrated circuit200. A control signal for controlling the operation of the shift register within the circuit module L is denoted by EN_L.

The circuit module N is comprised of a clock gating circuit204, a selection circuit205, and FFs13to18. The FFs13to18form a shift register constituting part of the scan chain within the semiconductor integrated circuit200. A control signal for controlling the operation of the shift register within the circuit module N is denoted by EN_N. An example of a scan data string output from the output terminal105will be illustrated usingFIG. 2B.

FIG. 2Bis an explanatory drawing illustrating an example of a scan data string output from the semiconductor integrated circuit200. A scan data string example1shows part of a scan data string output from the output terminal105when the control signal EN_L is 1, the control signal EN_M is 1, and the control signal EN_N is 1. If the control signal EN_L is 1, the control signal EN_M is 1, and the control signal EN_N is 1, then the selection circuit205within the circuit module N, the selection circuit103within the circuit module M, and the selection circuit203within the circuit module L select an ordinary path. Accordingly, in the scan data string example1, the scan data string of the circuit module N, the scan data string of the circuit module M, and the scan data string of the circuit module L are arrayed in the named order in the direction of an arrow (indicating an output sequence).

A scan data string example2shows part of a scan data string output from the output terminal105when the control signal EN_L is 1, the control signal EN_M is 0, and the control signal EN_N is 1. If the control signal EN_L is 1, the control signal EN_M is 0, and the control signal EN_N is 1, then the selection circuit205within the circuit module N and the selection circuit203within the circuit module L select an ordinary path, whereas the selection circuit103within the circuit module M selects a short-circuit path. Accordingly, in the scan data string example2, the scan data string of the circuit module N and the scan data string of the circuit module L are arrayed in the named order in the direction of an arrow (indicating an output sequence).

Consequently, by diverting the control signal for controlling the operation of circuit modules for use as a control signal for selecting a path, it is possible to promote the efficiency of a scan test. In addition, it is possible to shorten scan data and thereby reduce a test time.

In an embodiment to be described next, a circuit module includes a retaining circuit which retains a value of a control signal if a scan operation signal for controlling the operation of a scan test does not permit the scan test. In contrast, the retaining circuit outputs the value of the control signal to a selection circuit if the scan operation signal permits the scan test. Consequently, the control signal input to the selection circuit during the scan test does not change. Note that constituent elements identical to those explained in the above-described embodiment are denoted by like reference numerals and characters and will not be explained again. Circuit modules including retaining circuits will be illustrated usingFIG. 3.

FIG. 3is an explanatory drawing illustrating circuit modules including retaining circuits. A semiconductor integrated circuit300is comprised of a control signal generation circuit301, a circuit module M, a circuit module N, a plurality of other circuit modules (dotted-line arrows indicate that a plurality of circuit modules is included), an input terminal104, and an output terminal105.

The circuit module M is comprised of FFS7to12, a clock gating circuit102, a selection circuit103, and a retaining circuit302. The circuit module N is comprised of FFs13to18, a clock gating circuit204, a selection circuit205, and a retaining circuit303. The state of a control signal EN_M for controlling the operation of a shift register within the circuit module M is determined by the output data of the FF14within the circuit module N. Consequently, if a scan test is in progress, the output data of the FF14changes due to the shift operation of the scan chain. Therefore, if the control signal EN_M is input to the selection circuit103, a short-circuit path and an ordinary path switch to each other during a scan test, according to a scan signal.

As the result that the value of the control signal EN_M in a state of the scan test being not in progress is retained and that the retained value of the control signal EN_M is input to the selection circuit103in a state of the scan test being in progress, it is possible to prevent a path from being switched unnecessarily. The value of the control signal EN_M is retained by the retaining circuit302.

The retaining circuit302is comprised of, for example, a two-input AND circuit304and an FF19. A clock signal CLK and a scan operation signal are input to the AND circuit304. The operation of a scan test is controlled by the scan operation signal. For example, if the scan operation signal is 1, then the operation of the scan test is permitted and a scan chain is configured. Thus, a scan test is carried out when the clock signal is input. If the scan operation signal is 0, then the operation of the scan test is not permitted and, therefore, the scan chain is not configured.

Going back to the explanation of the retaining circuit302, if the scan operation signal is 0, then the AND circuit304supplies a clock signal to the FF19. If the scan operation signal is 1, then the AND circuit304does not supply the clock signal to the FF19. Consequently, the FF19retains the value of the control signal EN_M if the scan operation signal is 0. The FF19does not retain the value of the control signal EN_M, however, if the scan operation signal is 1. The retaining circuit303is comprised of a two-input AND circuit305and an FF20. The retaining circuit303is the same in configuration as the retaining circuit302.

Consequently, if the scan operation signal does not permit scan operation, then the value of a control signal is retained by the retaining circuit. If the scan operation signal permits scan operation, then the value of the control signal retained by the retaining circuit is output to the selection circuit. Accordingly, a path is fixed during the scan test, thereby making it possible to promote the efficiency of the scan test.

In an embodiment to be described next, the circuit modules explained in the above embodiment(s) include an appending circuit for adding path selection information indicating which path, between a short-circuit path and an ordinary path, has been selected by a selection circuit. Consequently, it is possible to make debugging easy. Note that constituent elements identical to those explained in the above embodiment(s) are denoted by like reference numerals and characters and will not be explained again. A circuit module including an appending circuit will be illustrated usingFIGS. 4A and 4B.

FIG. 4Ais an explanatory drawing illustrating a circuit module including an appending circuit. A semiconductor integrated circuit400is comprised of a circuit module M, a plurality of other circuit modules (dotted-line arrows indicate that a plurality of circuit modules is included), a control signal generation circuit401, an input terminal104, and an output terminal105. The circuit module M is comprised of FFs7to12, a clock gating circuit102, a selection circuit103, a retaining circuit302, and an appending circuit402.

The appending circuit402adds selection information indicating which path, between an ordinary path and a short-circuit path, has been selected to the head of the scan data string of the circuit module M, and outputs the scan data string. The appending circuit402is comprised of an FF_M and a selection circuit403. The selection circuit403selects the output data of the selection circuit103or the value of a control signal EN_M according to a scan operation signal.

If the scan operation signal is 0 (i.e., if a scan test is not permitted), then the selection circuit403selects the value of the control signal EN_M. If the scan operation signal is 1 (i.e., if a scan test is permitted), then the selection circuit403selects the output data of the selection circuit103. The data selected by the selection circuit403is retained by the FF_M in synchronization with a clock signal CLK and is output from the circuit module M.

If the scan operation signal is 0, then the value of the control signal EN_M is retained by the FF_M and thereby the value of control signal EN_M is appended to the head of the scan signal from the selection circuit103. Scan data which is the first data item of a scan data string within each circuit module output from the output terminal105is referred to as path selection information. The scan data string output from the output terminal105will be illustrated usingFIG. 4B.

FIG. 4Bis an explanatory drawing illustrating an example of the scan data string output from the semiconductor integrated circuit400. Assume that the semiconductor integrated circuit400is configured so as to further include a circuit module N and a circuit module L. Also assume that each circuit module includes an appending circuit. A scan data string example3shows part of the scan data string output from the output terminal105. The path selection information of the circuit module N has a value of 1. Therefore, an ordinary path is selected by the selection circuit205within the circuit module N.

The path selection information of the circuit module M has a value of 1. Therefore, an ordinary path is selected by the selection circuit103within the circuit module M. The path selection information of the circuit module L has a value of 1. Therefore, an ordinary path is selected by the selection circuit203within the circuit module L. The scan data string example3includes the scan data string of the circuit module N, the scan data string of the circuit module M, and the scan data string of the circuit module L.

Next, a scan data string example4shows part of a scan data string output from the output terminal105. The path selection information of the circuit module N has a value of 1. Therefore, an ordinary path is selected by the selection circuit205within the circuit module N.

The path selection information of the circuit module M has a value of 0. Therefore, a short-circuit path is selected by the selection circuit103within the circuit module M. The path selection information of the circuit module L has a value of 1. Therefore, an ordinary path is selected by the selection circuit203within the circuit module L. The scan data string example4includes the scan data string of the circuit module N and the scan data string of the circuit module L. Consequently, by observing the value of scan data, a user (designer or inspector) may determine which path each circuit module has selected. Accordingly, it is possible to promote the efficiency of a scan test. In addition, it is possible to make debugging easy.

In an embodiment to be described next, a scan data string output from a semiconductor integrated circuit is acquired to register the path selection information of circuit modules whose path selection information is unknown, according to the scan data string. Then, scan data strings corresponding to respective circuit modules and the identification information of the circuit modules are associated with one another and then output. Consequently, debugging may be made easy. A control signal generation circuit within a semiconductor integrated circuit under inspection supplies the output data of an FF included in a shift register within a circuit module, as a control signal, to other circuit modules the output data of which is output later than that of the former circuit module. Note that constituent elements identical to those explained in the above embodiment(s) are denoted by like reference numerals and characters and will not be explained again.

FIG. 5is an explanatory drawing illustrating a semiconductor integrated circuit targeted by the inspection apparatus of the above described embodiment. A semiconductor integrated circuit500is comprised of a circuit module L constituting a scan chain, a circuit module M constituting the scan chain, a circuit module N constituting the scan chain, a plurality of other circuit modules constituting the scan chain, (dotted-line arrows indicate that a plurality of circuit modules is included), a control signal generation circuit501, an input terminal104, and an output terminal105.

The circuit module N lets a scan signal go through a shift register and be output to the output terminal105. The output data of an FF14included in the shift register of the circuit module N is supplied to the circuit module M as a control signal. The output data of an FF15included in the shift register of the circuit module N is supplied to the circuit module L as a control signal.

FIG. 6Ais an explanatory drawing showing path selection information indicating which path each circuit module has selected. A path selection list600is comprised of a circuit module name601and path selection information602. A value 1 of the path selection information602shows that an ordinary path is selected. In contrast, a value of 0 indicates that a short-circuit path is selected. For example, if the circuit module name601is the circuit module N, then the path selection information602has a value of 1. It is therefore known that an ordinary path is selected in the circuit module N.

In the case of a circuit module supplied with a control signal from another circuit module constituting a scan chain, the path selection information602is unknown and therefore a value of 1 is set in the path selection information602. Consequently, the unknown path selection information602is registered by checking the scan data string. Note that the path selection list600is stored in a memory unit or in the memory unit of an accessible external computer.

FIG. 6Bis an explanatory drawing showing circuit modules which are the output destinations of FFs included in shift registers. Output destination information603is comprised of an FF name604and a circuit module name605. The output data of an FF is supplied as a control signal to a circuit module which is subsequent in the order of output to a circuit module including the FF. For example, the output destination of the FF14is the circuit module M. Note that the output destination information603is stored in a memory unit or in the memory unit of an accessible external computer.

FIG. 6Cis an explanatory drawing illustrating an example of output sequence information and an example of a scan data string in accordance with the above-described embodiment. Output sequence information606is information indicating the output sequence of data-retaining elements included in the shift registers of circuit modules within the semiconductor integrated circuit500which constitute a scan test. The output sequence information606is comprised of a circuit module name607and an FF name608. The direction of an arrow shows an output sequence.

Note that the output sequence information606is stored in a memory unit or in the memory unit of an accessible external computer. A scan data string example5shows one example of a scan data string output from the semiconductor integrated circuit500.

FIG. 7is a block diagram illustrating the hardware configuration of an inspection apparatus in accordance with an embodiment. InFIG. 7, the inspection apparatus includes a CPU (Central Processing Unit)701, a ROM (Read-Only Memory)702, a RAM (Random Access Memory)703, a magnetic disk drive704, a magnetic disk705, an optical disk drive706, an optical disk707, a display708, an I/F (Interface)709, a keyboard710, a mouse711, a scanner712, a printer713, and an I/F715dedicated to JTAG or scan testing. In addition, the respective components are connected to one another through a bus700.

Here, the CPU701governs the control of the inspection apparatus as a whole. The ROM702stores programs, such as a boot program. The RAM703is used as a work area of the CPU701. The magnetic disk drive704controls data read/write operation on the data magnetic disk705according to control by the CPU701. The magnetic disk705stores data written by the control of the magnetic disk drive704.

The optical disk drive706controls data read/write operation on the optical disk707according to control by the CPU701. The optical disk707, for example, stores data written according to control by the optical disk drive706and makes data stored in the optical disk707read by a computer.

The display708displays a cursor and icons or toolboxes, as well as documents, images, and data such as function information. For this display708, it is possible to adopt, for example, a CRT, a TFT liquid crystal display, or a plasma display.

The interface709is connected to a network714, such as a LAN (Local Area Network), a WAN (Wide Area Network) or the Internet, through a communications line, and is further connected to other equipment through this network714. The I/F709governs an interface between the network714and the internal network of the inspection apparatus, and controls the input/output of data from external equipment. For the I/F709, it is possible to adopt, for example, a modem or a LAN adapter.

The I/F715dedicated to JTAG or scan testing acquires a scan data string output from the output terminal of the semiconductor integrated circuit. Alternatively, a scan signal may be input from the input terminal of the semiconductor integrated circuit using the I/F715dedicated to JTAG or scan testing.

The keyboard710includes keys for inputting letters, numerals, various commands and the like, whereby data input is performed. A touch-panel input pad, a tenkey numeric keypad, or the like may be used instead. The mouse711is used to, for example, move the cursor, select a range, and move or resize windows. A trackball, a joystick or the like may be used instead, if as a pointing device, the trackball, the joystick or the like has the same functions as the mouse.

The scanner712optically reads images and loads them into the inspection apparatus. Note that the scanner712may have an Optical Character Reader (OCR) function. The printer713prints image data and document data. For the printer713, it is possible to adopt, for example, a laser printer or an ink-jet printer.

Next, an explanation will be made of the functional configuration of an inspection apparatus.FIG. 8is a block diagram illustrating the functional configuration of an inspection apparatus in accordance with an embodiment. An inspection apparatus800is comprised of an acquisition section801, a storage section802, a specification section803, a determination section804, a setting section805, a detection section806, a registration section807, an association section808, and an output section809. Specifically, functions (acquisition section801to output section809) which serve as a control section of the inspection apparatus800are realized by, for example, letting a program stored in a memory unit, such as the ROM702, the RAM703, the magnetic disk705or the optical disk707illustrated inFIG. 7be executed by the CPU701, or by using the I/F709.

First, the acquisition section801acquires a scan data string output from the output terminal of a semiconductor integrated circuit. Specifically, for example, the CPU701acquires the scan data string example5output from the output terminal105of the semiconductor integrated circuit500through the I/F715dedicated to JTAG or scan testing. Note that the acquired scan data string example5is stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.

The storage section802stores the output sequence of circuit modules, output sequence information indicating the output sequence of FFs of each circuit module, and output destination information capable identifying a circuit module, which is an output destination, for each information capable of identifying an FF. In addition, the storage section802stores a path selection list in which path selection information indicating which path has been selected within each circuit module and information capable of identifying a circuit module are associated with each other.

The information capable identifying an FF refers to, for example, an FF name given to each FF within a semiconductor integrated circuit. The information capable of identifying a circuit module refers to, for example, a circuit module name given to each circuit module within the semiconductor integrated circuit. Specifically, for example, output sequence information606, output destination information603and a path selection list601are stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.

Next, the specification section803specifies circuit modules, among a plurality of circuit modules, in the order in which data is output therefrom as scan data strings. Specifically, for example, the CPU701gains access to the memory unit and reads the output sequence information606. Then, the CPU701specifies circuit modules, in the order of output, out of the circuit module name607in the output sequence information606. First, the circuit module N is selected.

The determination section804determines which path, between an ordinary path and a short-circuit path, the path selection information of a circuit module specified by the specification section803indicates. Specifically, for example, the CPU701gains access to the memory unit and reads the path selection list600. Then, the CPU701reads the path selection information602from the path selection list600on the basis of the specified circuit module name601. Then, the CPU701determines which path, between a short-circuit path and an ordinary path, the read-out path selection information602indicates. For example, the path selection information602of the circuit module N has a value of 1. Consequently, the path selection information602indicates that an ordinary path has been selected in the circuit module N.

Next, if a determination is made by the determination section804that the path selection information of a circuit module indicates an ordinary path, then the setting section805sets as many scan data strings, among given scan data strings, as the number of FFs included in a shift register within the circuit module in a target scan data string.

Specifically, for example, the CPU701sets as many scan data strings as the number of FFs included in the shift register within the circuit module in the target scan data string, according to the scan data string example5. For example, the number of FFs included in a shift register within the circuit module N is 6. The circuit module N is the first one, among a plurality of circuit modules constituting a scan chain, for which a scan signal is output in the first place. For example, the CPU701sets the first to sixth scan data of the scan data string example5in the target scan data string, as the scan data string of the circuit module N.

Next, from the target scan data string set by the setting section805, the detection section806detects the path selection information of a circuit module whose path selection information indicating which path has been selected is unknown. Specifically, for example, the CPU701gains access to the memory unit and reads the output destination information603. Then, from the FF name604, the CPU701detects FFs constituting the shift register within the specified circuit module. Then, the CPU701detects the circuit module name605which is an output destination of the detected FF name604. The detected circuit module and the target scan data string are associated with each other. Note that the results of detection are stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.

For example, according to the output destination information603, the FF14and FF15constituting the shift register within the circuit module N are detected from the FF name604. The circuit module M, which is the output destination of the FF14, is read out. In addition, the circuit module L, which is the output destination of the FF15, is read out. The scan data fifth from the first scan data and corresponding to the FF14in the scan data string example5is 0. The scan data fourth from the first scan data and corresponding to the FF15in the scan data string example5is 1.

The registration section807registers path selection information on the basis of detection results provided by the detection section806. Specifically, for example, the CPU701gains access to a memory unit and reads out the detection results. The CPU701gains access to the memory unit and reads out the path selection list600. Then, the CPU701searches the detected circuit module name605out of the circuit module name601of the path selection list600. Next, the CPU701registers the scan data string of the circuit module name605, as new path selection information602, with the path selection information602of the searched-out circuit module name601. Note that registration results are stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.FIG. 9illustrates the registered path selection list600.

FIG. 9is an explanatory drawing illustrating the registered path selection list600. The path selection information602of the circuit module M is registered as 0. In this way, the path selection information602of a circuit module whose path selection information is unknown is registered as the result of a scan data string being inspected by the inspection apparatus800.

Next, referring back toFIG. 8, the association section808associates target scan data strings with the identification information of circuit modules. Specifically, for example, the CPU701associates target scan data strings with circuit module names.

The output section809outputs target scan data strings and the identification information of circuit modules associated with each other by the association section808. Specifically, for example, the CPU701outputs the target scan data strings and the circuit module names. Examples of output forms include display on the display708, output to the printer713for printing, and transmission to external equipment through the I/F709. Alternatively, the results of association may be stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.FIG. 10illustrates an output example.

FIG. 10is an explanatory drawing illustrating one example of output provided by the inspection apparatus800. An output example1000is comprised of a circuit module name1001, an FF name1002, and scan data1003. For example, the scan data of an FF6included in a shift register within the circuit module L is 0.

Next, an explanation will be made of the inspection processing procedure of an inspection apparatus800in accordance with an embodiment.FIG. 11is a flowchart showing the inspection processing procedure of the inspection apparatus800in accordance with an embodiment. First, a scan data string is acquired by the acquisition section801(operation S1101). For example, the acquired scan data string is a scan data string example5. The condition “i=1, j=1” is set by the specification section803(operation S1102) and a determination is made as to whether or not “j≦the total number of circuit modules” holds true (operation S1103).

If a determination is made that “j≦the total number of circuit modules” holds true (operation S1103: Yes), then the path selection information of a jth circuit module is acquired from a path selection list stored by the storage section802(operation S1104). The path selection list refers to the path selection list600. The path selection information refers to the path selection information602. The condition “X=the number of FFs within jth circuit module” is set (operation S1105) and a determination is made by the determination section804as to whether or not a circuit module including a jth FF in the output sequence information is a short-circuit path (operation S1106). The output sequence information refers to the output sequence information606and is stored by the storage section802.

If a determination is made that the circuit module including the jth FF in the output sequence information is a short-circuit path (operation S1106: Yes), then the condition “j=j+1” is set by the specification section803(operation S1107) and the system goes back to operation S1103.

On the other hand, if a determination is made that the circuit module including the jth FF in the output sequence information is not a short-circuit path (operation S1106: No), then jth to (i+X−1)th scan data are retrieved (operation S1108). The retrieved scan data string is set in a target scan data string by the setting section805(operation S1109), and registration processing is executed (operation S1110). The target scan data string is associated with the jth circuit module by the association section808and is stored (operation S1111). Then, the condition “j=j+1, i=i+X” is set by the specification section803(operation S1112), and the system goes back to operation S1103.

On the other hand, if a determination is made that “j≦the total number of circuit modules” does not hold true (operation S1103: No), then the associated and stored information is output by the output section809(operation S1113) and a series of processes terminates.

Next, an explanation will be made of the above-described registration processing (operation S1110).FIG. 12is a flowchart showing a registration processing procedure. First, the condition “k=1” is set (operation S1201) and a determination is made whether or not k≦X holds true (operation S1202). If a determination is made that k≦X holds true (operation S1202: Yes), then a determination is made by the detection section806as to whether or not there is a circuit module which is the output destination of a kth FF (operation S1203). If a determination is made that there is the circuit module which is the output destination of the kth FF (operation S1203: Yes), then a determination is made as to whether or not “scan data corresponding to the kth FF=0” holds true (operation S1204).

If a determination is made that “scan data corresponding to the kth FF=0” holds true (operation S1204: Yes), then the path selection information602of the circuit module, which is an output destination, is registered as a short-circuit path by the registration section807(operation S1205). Then, the condition “k=k+1” is set (operation S1206) and the system goes back to operation S1202. On the other hand, if a determination is made that there is no circuit module which is the output destination of the kth FF (operation S1203: No) or that “scan data corresponding to the kth FF=0” does not hold true (operation S1204: No), then the system goes to operation S1206.

On the other hand, if a determination is made that k≦X does not hold true (operation S1202: No), then the system goes to operation S1111.

In an embodiment, scan data strings output from the semiconductor integrated circuit explained in above-identified embodiment are inspected. Consequently, it is possible to make debugging easy. In the present embodiment, scan data strings output from a semiconductor integrated circuit400will be taken as an example to explain an inspection apparatus. Note that constituent elements identical to those explained in above-identified embodiment(s) are denoted by like reference numerals and characters and will not be explained again.

FIG. 13is an explanatory drawing illustrating an example of output sequence information and an example a scan data string in accordance with an embodiment. Output sequence information1300is comprised of a circuit module name1301and an FF name1302. For example, FF names included in a shift register within a circuit module whose circuit module name1301is a circuit module N are an FF_N and FFs13to18. Note that the output sequence information1300is stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.

A scan data string example6shows an example of a scan data string. The scan data string example6is output from the semiconductor integrated circuit400in the order of output denoted by an arrow. Assume that the semiconductor integrated circuit400has the configuration ofFIG. 4Aand is further comprised of a circuit module N and a circuit module L. Also assume that the circuit module N and the circuit module L respectively include a retaining circuit and an appending circuit.

Next, an explanation will be made of the functional configuration of an inspection apparatus.FIG. 14is a block diagram illustrating the functional configuration of an inspection apparatus in accordance with an embodiment. An inspection apparatus1400is comprised of an acquisition section1401, a storage section1402, a specification section1403, an extraction section1404, a determination section1405, an association section1406, and an output section1407.

Specifically, functions (acquisition section1401to output section1407) which serve as a control section of the inspection apparatus1400are realized by, for example, letting a program stored in a memory unit, such as the ROM702, the RAM703, the magnetic disk705or the optical disk707illustrated inFIG. 7be executed by the CPU701, or by using the I/F709.

First, the acquisition section1401acquires a scan data string output from a semiconductor integrated circuit. Specifically, for example, the CPU701acquires a scan data string example6output from the output terminal105of the semiconductor integrated circuit400through the I/F715dedicated to JTAG or scan testing. Note that the acquired scan data string example6is stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.

The storage section1402stores output sequence information in which pieces of information capable of identifying FFs are arrayed in the order of output. Specifically, for example, output sequence information1300is stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.

Next, the specification section1403specifies circuit modules, among a plurality of circuit modules, in the order in which data is output therefrom as a scan data string. Specifically, for example, the CPU701gains access to the memory unit and reads out the output sequence information1300. Then, the CPU701specifies circuit modules, in the order of output, out of the circuit module name1301in the output sequence information1300. Assume that a circuit module N is selected here. Note that the results of specification are stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.

Next, according to the output sequence information1300, the extraction section1404extracts scan data corresponding to path selection information within the circuit module specified by the specification section1403from the scan data string acquired by the acquisition section1401. Specifically, for example, the CPU701reads out the FF name1302of a first FF from among a plurality of FFs included in the shift register within the specified circuit module. In the case of the circuit module N, for example, the first FF name1302is an FF_N. The first scan data, among scan data strings of respective circuit modules output from the semiconductor integrated circuit400, is the path selection information.

Then, for example, the CPU701extracts scan data corresponding to the FF_N from the scan data string example6. Note that the results of extraction are stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.

The determination section1405determines which path, between an ordinary path and a short-circuit path, the scan data which is path selection information extracted by the extraction section1404indicates. Specifically, for example, the CPU701determines whether the value of the extraction results is 1 or 0. For example, the path selection information of the circuit module N has a value of 1. Consequently, the path selection information indicates that an ordinary path has been selected in the circuit module N. Note that the results of determination are stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.

Next, if a determination is made by the determination section1405that the path selection information indicates an ordinary path, then the association section1406associates as many scan data strings, among given scan data strings, as the number of FFs included in the shift registers within the circuit modules with the identification information of the circuit modules. Specifically, if the path selection information indicates, for example, an ordinary path, then the CPU701associates as many scan data strings as the number of FFs included in the shift register within the specified circuit module with circuit module names, according to the scan data string example6.

The output section1407outputs the results of association provided by the association section1406. Specifically, for example, the CPU701outputs the scan data strings and the circuit module names associated with each other. Examples of output forms include display on the display708, output to the printer713for printing, and transmission to external equipment through the I/F709. Alternatively, the results of association may be stored in a memory unit, such as the RAM703, the magnetic disk705, or the optical disk707.FIG. 15illustrates an output example.

FIG. 15is an explanatory drawing illustrating one example of output provided by an inspection apparatus1400. An output example1500is comprised of a circuit module name1501, an FF name1502, and a scan data string1503. For example, if the circuit module name1501is a circuit module M, only FF_M is associated with a scan data string. The FF_M is the path selection information of the circuit module M. The FF_M has a scan data value of 0. Accordingly, a short-circuit path is selected in the circuit module M and, therefore, only the FF_M is associated with scan data.

Now, an explanation will be made of the inspection processing procedure of the inspection apparatus1400in accordance with an embodiment.FIG. 16is a flowchart showing the inspection processing procedure of the inspection apparatus1400in accordance with an embodiment. First, a scan data string is acquired by the acquisition section1401(operation S1601). For example, the scan data string is the scan data string example6. Next, the condition “n=1, m=1” is set by the specification section1403(operation S1602). This operation specifies an mth circuit module in the output sequence information1300stored by the storage section1402. Then, a determination is made as to whether or not “m≦the total number of circuit modules” holds true (operation S1603).

If a determination is made that “m≦the total number of circuit modules” holds true (operation S1603: Yes), then nth scan data is extracted by the extraction section1404as the path selection information of the mth circuit module (operation S1604). Then, the condition “n=n+1” is set (operation S1605) and a determination is made by the determination section1405as to whether or not the extracted path selection information indicates an ordinary path (operation S1606).

If a determination is made that the extracted path selection information indicates a ordinary path (operation S1606: Yes), then the condition “X=the number of FFs within mth circuit module” is set (operation S1607). In addition, nth to (n+X)th scan data and an mth circuit module name are associated with each other by the association section1406and the results of association are stored (operation S1608). The condition “m=m+1, n=n+X” is set by the specification section1403(operation S1609), and the system goes back to operation S1603.

On the other hand, if the extracted path selection information is determined as not indicating an ordinary path (operation S1606: No), then the system goes to operation S1609. If a determination is made that “m≦the total number of circuit modules” does not hold true (operation S1603: No), then the associated and stored information is output by the output section1407(operation S1610) and a series of processes terminates.

As has been described heretofore, according to the circuit modules and the semiconductor integrated circuit, it is possible to promote the efficiency of scan tests by diverting a control signal for controlling the operation of circuit modules for use as a control signal for selecting a path. In addition, it is possible to shorten scan data and thereby reduce a test time. Furthermore, a test may be performed irrespective of the number of terminals.

If the operation of a scan test is not permitted by a scan operation signal, then the control signal is retained. If the operation of the scan test is permitted, then the control signal is output to a selection circuit. Consequently, a path is fixed during a scan test, thereby making it possible to promote the efficiency of the scan test.

In addition, path selection information indicating which path, between an ordinary path and a short-circuit path, has been selected is added to a scan signal for each circuit module. Consequently, by observing the value of scan data, a user (designer or inspector) may determine which path each circuit module has selected. Accordingly, it is possible to promote the efficiency of a scan test. It is also possible to make debugging easy.

The output data of FFs included in a shift register within a circuit module is supplied as a control signal to circuit modules the output data which is output later than that of the former circuit module. Consequently, by observing the scan data values of other modules, a user may determine which path has been selected. Accordingly, it is possible to promote the efficiency of a scan test and make debugging easy.

As has been described heretofore, according to the inspection apparatus, a scan data string output from the semiconductor integrated circuit is acquired, the path selection information of circuit modules whose path selection information is unknown is registered, and scan data corresponding to each circuit module and the identification information thereof are associated with each other and then output. Consequently, a determination is made automatically as to which FF, among FFs constituting a scan chain, each scan data within the scan data string corresponds to. Thus, it is possible to make debugging easy.

As has been described heretofore, according to the inspection apparatus, a scan data string output from the semiconductor integrated circuit is acquired, the path selection information of each circuit module is extracted out of the scan data string, and a determination is made as to which path has been selected. If the selected path is determined to be an ordinary path, then scan data corresponding to each circuit module and the identification information thereof are associated with each other according to the scan data string, and then output.

Consequently, a determination is made automatically as to which FF, among FFs constituting a scan chain, each scan data within the scan data string corresponds to. Thus, it is possible to make debugging easy. In addition, since path selection information is included in the scan data string, there is no need for lists of output destination information, path selection information, and the like. Thus, it is possible to perform debugging only by using scan data strings and output sequence information.

Note that the inspection method explained in the present embodiment may be realized by executing a previously prepared program on a computer, such as a personal computer or a workstation.

The inspection program is recorded on a computer-readable recording medium, such as a hard disk, a flexible disk, a CD-ROM, an MO or a DVD and is executed as the result of being read out from the recording medium by the computer. The inspection program may be distributed through a network, such as the Internet.

In addition, the inspection apparatus800and the inspection apparatus1400explained in the above-described embodiment may also be realized by using ICs intended for specific applications (hereinafter simply referred to as “ASICs”), such as standard cells and structured ASICs (Application Specific Integrated Circuits), or by using PLDs (Programmable Logic Devices), such as FPGAs. Specifically, for example, by functionally defining the function(s) of the above-described inspection apparatus800(acquisition section801to output section809) or the functions of the inspection apparatus1400(acquisition section1401to output section1407) using an HDL description, logically synthesizing the HDL description, and providing the HDL description to ASICs or PLDs, it is possible to manufacture the inspection apparatus800or the inspection apparatus1400.

As such, the embodiments can be implemented in computing hardware (computing apparatus) and/or software, such as (in a non-limiting example) any computer that can store, retrieve, process and/or output data and/or communicate with other computers. The results produced can be displayed on a display of the computing hardware. A program/software implementing the embodiments may be recorded on computer-readable media comprising computer-readable recording media. The program/software implementing the embodiments may also be transmitted over transmission communication media. Examples of the computer-readable recording media include a magnetic recording apparatus, an optical disk, a magneto-optical disk, and/or a semiconductor memory (for example, RAM, ROM, etc.). Examples of the magnetic recording apparatus include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape (MT). Examples of the optical disk include a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc-Read Only Memory), and a CD-R (Recordable)/RW. An example of communication media includes a carrier-wave signal.

Further, according to an aspect of the embodiments, any combinations of the described features, functions and/or operations can be provided.