Method for manufacturing mach-zehnder modulator, method for manufacturing optical waveguide, and optical waveguide

A method for manufacturing a Mach-Zehnder modulator includes the steps of forming a stacked semiconductor layer, the stacked semiconductor layer including a first conductivity type semiconductor layer, a core layer and a second conductivity type semiconductor layer, forming a waveguide mesa, the waveguide mesa having a first portion, a second portion and a third portion arranged between the first and second portions; forming a buried region on the waveguide mesa; forming an opening in the buried region on the third portion by etching the buried region using a mask; etching the second conductivity type semiconductor layer in the third portion through the buried region as a mask; and removing the buried region after etching the second conductivity type semiconductor layer. In the step of etching the second conductivity type semiconductor layer, the buried region covers a side surface of the third portion of the waveguide mesa.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing a Mach-Zehnder modulator, a method for manufacturing an optical waveguide, and an optical waveguides.

2. Description of the Related Art

SUMMARY OF THE INVENTION

Mach-Zehnder modulators have optical waveguides for generating optical signals which are modulated in accordance with high-frequency electric signals. An RF electrode and a DC electrode are disposed on the optical waveguide. The RF electrode is used to supply a high-frequency electric signal to the optical waveguide. The DC electrode is used, for example, to control the phase of light propagating in the optical waveguide or to control the operating point of the modulator. These electrodes are disposed on different portions of the optical waveguide, respectively. The DC bias is applied from the DC electrode to one portion of the optical waveguide. The electric field resulting from the DC bias leaks into another portion of the optical waveguide in which input light is modulated in response to a high-frequency electric signal supplied via the RF electrode. This leakage of the electric field affects the modulation bandwidth of the Mach-Zehnder modulator. To avoid influences due to such leakage, it is necessary to electrically isolate the optical waveguide portion operating in response to an electric signal from the RF electrode from the optical waveguide portion operating in response to a voltage from the DC electrode.

Isolation may be established by disposing an isolating waveguide portion between the optical waveguide portion operating in response to an electric signal from the RF electrode and the optical waveguide portion operating in response to a voltage from the DC electrode. In this isolating waveguide portion, an upper cladding layer disposed on a core layer is removed by etching. An optical waveguide including the isolating waveguide portion without an upper cladding layer may be manufactured by any of the following two approaches. The first is to remove the semiconductor portion for the upper cladding layer prior to the manufacturing of the waveguide mesa. The second is to remove part of the upper cladding layer after the waveguide is manufactured.

In the first approach, the waveguide is manufactured after the upper cladding layer is removed. Accordingly, the removal of the semiconductor layer defining the upper cladding layer produces an unevenness or step on the surface of the epitaxial wafer. This unevenness or step hinders the afterward formation of a pattern of the waveguide using, for example, a photolithography method, resulting in a deterioration in the accuracy of pattern alignment. Further, in the process of the pattern alignment, simultaneous focusing on the upper and lower levels at the elevation change on the wafer is infeasible. This causes a change in shape or size of the pattern at the location of the unevenness in a resist mask. If the semiconductor layers are etched using this resist mask to form a waveguide, the width of the waveguide will be varied at the location of the unevenness, resulting in increasing a loss of light propagating in the optical waveguide.

On the other hand, in the second approach of removing the upper cladding layer after the fabrication of the waveguide, change of the width of the waveguide does not occur. However, in the second approach of removing the upper cladding layer, the following manufacturing defect occurs. The upper cladding layer of the waveguide mesa is removed by, for example, wet etching through a mask including a pattern having an opening across the waveguide mesa. However, the lower cladding layer of the waveguide mesa frequently is composed of the same material as that of the upper cladding layer. Thus, when the upper cladding layer is etched by wet etching, the lower cladding layer exposed in the opening across the waveguide mesa is also etched. In addition, when the upper cladding layer of the waveguide mesa is removed by, for example, dry etching, not only the top surface but also the side surfaces of the waveguide mesa exposed in the opening across the waveguide mesa are etched. As a result, the width of the waveguide is reduced.

A method for manufacturing a Mach-Zehnder modulator according to the present invention includes the steps of (a) forming a stacked semiconductor layer on a substrate, the stacked semiconductor layer including a first conductivity type semiconductor layer, a core layer and a second conductivity type semiconductor layer; (b) forming a waveguide mesa by etching the stacked semiconductor layer, the waveguide mesa having a first portion, a second portion and a third portion arranged between the first and second portions, the waveguide mesa extending in a direction of a waveguide axis; (c) forming a first buried region on a top surface and a side surface of the waveguide mesa and on the substrate; (d) forming a mask on the first buried region, the mask having an opening on the third portion of the waveguide mesa; (e) forming an opening in the first buried region by etching the first buried region using the mask to expose a top surface of the third portion of the waveguide mesa through the opening in the first buried region; (f) after removing the mask, etching the second conductivity type semiconductor layer in the third portion of the waveguide mesa through the first buried region as a mask; and (g) removing the first buried region after etching the second conductivity type semiconductor layer. In the step of forming the opening in the first buried region, the first buried region covers a side surface of the third portion of the waveguide mesa.

According to the method for manufacturing a Mach-Zehnder modulator, an opening is formed in the first buried region on the third portion of the waveguide mesa with use of the mask having an opening on the third portion of the waveguide mesa. During this process, the first buried region covers the side surfaces of the third portion of the waveguide mesa, and thus can protect the side surfaces of the third portion of the waveguide mesa. After the opening is formed in the first buried region, the second conductivity type semiconductor layer in the third portion of the waveguide mesa is selectively etched while using the first buried region as a mask. During this etching, the first conductivity type semiconductor layer is not exposed to the etchant. Through these steps, a waveguide mesa having an isolation region in the third portion is manufactured.

The method for manufacturing a Mach-Zehnder modulator according to the present invention may further include the steps of, after forming the waveguide mesa, forming an insulating layer on the top surface and the side surface of the waveguide mesa and on the substrate; and, after forming the opening in the first buried region, forming an opening in the insulating layer on the third portion of the waveguide mesa by etching the insulating layer through the mask to form an insulating mask from the insulating layer. The second conductivity type semiconductor layer is preferably etched through the insulating mask after removing the mask. In the step of forming the insulating mask, the first buried region covers the side surface of the third portion of the waveguide mesa. The first buried region is made of a material different from a material of the insulating layer.

According to the method for manufacturing a Mach-Zehnder modulator, the insulating layer is formed on the substrate after the formation of the waveguide mesa so as to cover the top surface and the side surfaces of the waveguide mesa. Further, after the formation of the opening in the first buried region on the third portion of the waveguide mesa, an opening is formed in the insulating layer on the third portion of the waveguide mesa through the mask, and thereby the insulating layer is fabricated into an insulating mask. During the fabrication of the insulating mask, the first buried region covers the side surfaces of the third portion of the waveguide mesa. With this configuration, in forming the insulating mask, the insulating layer on the side surfaces of the third portion of the waveguide mesa is protected with the first buried region. Further, the insulating layer on the top surface of the third portion of the waveguide mesa is selectively etched. By the use of the thus-fabricated insulating mask, the second conductivity type semiconductor layer in the third portion of the waveguide mesa is etched selectively. During this etching, the first conductivity type semiconductor layer is not exposed to the etchant. Through these steps, a waveguide mesa having an isolation region in the third portion is manufactured.

The method for manufacturing a Mach-Zehnder modulator according to the present invention may further include the steps of, after removing the first buried region, forming a second buried region on the top surface and the side surface of the waveguide mesa and on the substrate; forming a first electrode opening in the second buried region on the first portion of the waveguide mesa; forming a second electrode opening in the second buried region on the second portion of the waveguide mesa; forming a first electrode in the first electrode opening, the first electrode being electrically connected to a top surface of the first portion of the waveguide mesa through the first electrode opening; and forming a second electrode in the second electrode opening, the second electrode being electrically connected to a top surface of the second portion of the waveguide mesa through the second electrode opening. According to the method for manufacturing a Mach-Zehnder modulator, the second electrode is electrically isolated from the first electrode because the isolation structure is formed in the waveguide mesa. Specifically, the third portion constituting the isolation structure is formed between the first portion and the second portion.

In the method for manufacturing a Mach-Zehnder modulator according to the present invention, the first buried region may be made of spin-on-glass. The mask may be made of resist. In addition, the opening of the mask may have a width larger than a width of the third portion of the waveguide mesa. According to the method for manufacturing a Mach-Zehnder modulator, the first buried region is made of spin-on-glass (SOG). Therefore, the first buried region is easily removed after etching the second conductivity type semiconductor layer.

In the method for manufacturing a Mach-Zehnder modulator according to the present invention, preferably, the step of forming the first buried region includes a step of applying a resist onto the top surface and the side surfaces of the waveguide mesa, and a step of baking the resist to form a cured resist. The first buried region includes the cured resist. The mask is made of resist. In addition, the opening of the mask has a width larger than a width of the third portion of the waveguide mesa. According to the method for manufacturing a Mach-Zehnder modulator, the first buried region includes the cured resist. The cured resist is resistant to the developer used in the step of forming the mask made of resist on the first buried region of the cured resist.

A method for manufacturing a Mach-Zehnder modulator according to the present invention includes the steps of (a) forming a stacked semiconductor layer on a substrate, the stacked semiconductor layer including a first conductivity type semiconductor layer, a core layer and a second conductivity type semiconductor layer; (b) forming a waveguide mesa by etching the stacked semiconductor layer, the waveguide mesa having a first portion, a second portion and a third portion arranged between the first and second portions, the waveguide mesa extending in a direction of a waveguide axis; (c) forming a first buried region on a top surface and a side surface of the waveguide mesa and on the substrate, the first buried region including an insulating layer made of a dielectric material; (d) forming a mask on the first buried region, the mask having an opening on the third portion of the waveguide mesa; (e) forming an insulating mask by etching the first buried region using the mask, the insulating mask having an opening on the third portion of the waveguide mesa; (f) after removing the mask, etching the second conductivity type semiconductor layer in the third portion of the waveguide mesa through the insulating mask; and (g) removing the insulating mask after the etching the second conductivity type semiconductor layer. In the step of forming an insulating mask, the first buried region covers a side surface of the third portion of the waveguide mesa. In addition, in the step of etching the second conductivity type semiconductor layer, the insulating mask covers the side surface of the third portion of the waveguide mesa.

According to the method for manufacturing a Mach-Zehnder modulator, an opening is formed in the first buried region on the third portion of the waveguide mesa with use of the mask having an opening on the third portion of the waveguide mesa, and thereby the first buried region is fabricated into an insulating mask. During the fabrication of the insulating mask, the first buried region covers the side surfaces of the third portion of the waveguide mesa. Thus, the side surfaces of the third portion of the waveguide mesa can be protected with the insulating mask. Further, the insulating layer on the top surface of the third portion of the waveguide mesa is etched selectively. With the use of the insulating mask fabricated in the above manner, the second conductivity type semiconductor layer in the third portion of the waveguide mesa is selectively etched. During this etching, the first buried region (the insulating mask) protects the first conductivity type semiconductor layer from being exposed to the etchant. Through these steps, a waveguide mesa having an isolation region in the third portion is manufactured.

In the method for manufacturing a Mach-Zehnder modulator according to the present invention, preferably, the insulating layer includes a silicon dioxide film. The step of forming the first buried region includes a step of forming the silicon dioxide film on the top surface and the side surface of the waveguide mesa and on the substrate and a step of planarizing the silicon dioxide film.

According to the method for manufacturing a Mach-Zehnder modulator, the silicon dioxide film that buries the top surface and the side surfaces of the waveguide mesa is planarized to form the first buried region, and thereafter an opening is formed in the first buried region on the third portion of the waveguide mesa. Through these steps, the opening is formed in the first buried region on the third portion of the waveguide mesa while protecting the side surfaces of the first conductivity type semiconductor layer in the third portion of the waveguide mesa.

A method for manufacturing an optical waveguide according to the present invention includes the steps of (a) forming stacked semiconductor layers on a substrate, the stacked semiconductor layers including a first conductivity type semiconductor layer, a core layer and a second conductivity type semiconductor layer, (b) forming a waveguide mesa by etching the stacked semiconductor layer, the waveguide mesa having a first portion, a second portion and a third portion arranged between the first and second portions, the waveguide mesa extending in a direction of a waveguide axis; (c) forming an insulating layer on the top surface and the side surface of the waveguide mesa and on the substrate; (d) forming a first buried region on the insulating layer formed on the top surface and the side surface of the waveguide mesa and on the substrate, the first buried region including a material different from a material of the insulating layer; (e) forming a mask on the first buried region, the mask having an opening on the third portion of the waveguide mesa; (f) forming an insulating mask by etching the first buried region and the insulating layer using the mask, the insulating mask having an opening on the third portion of the waveguide mesa; (g) after removing the mask, etching the second conductivity type semiconductor layer in the third portion of the waveguide mesa through the insulating mask; and (h) removing the insulating mask after etching the second conductivity type semiconductor layer. In the step of forming the insulating mask, the first buried region covers a side surface of the third portion of the waveguide mesa. In addition, in the step of etching the second conductivity type semiconductor layer, the insulating mask covers the side surface of the third portion of the waveguide mesa.

According to the method for manufacturing an optical waveguide, an opening is formed in the first buried region on the third portion of the waveguide mesa with use of the mask having an opening on the third portion of the waveguide mesa, and thereby the insulating mask is fabricated from the first buried region. During the fabrication of the insulating mask, the first buried region covers the side surfaces of the third portion of the waveguide mesa. Thus, the side surfaces of the third portion of the waveguide mesa can be protected with the first buried region, and the first buried region on the top surface of the third portion of the waveguide mesa is etched selectively. With the use of the insulating mask fabricated in the above manner, the second conductivity type semiconductor layer in the third portion of the waveguide mesa is selectively etched. During this etching, the first buried region (the insulating mask) serves as a protective film that prevents the first conductivity type semiconductor layer from being exposed to the etchant. Through these steps, a waveguide mesa having an isolation region in the third portion is manufactured.

An optical waveguide according to the present invention includes a waveguide mesa having a first portion, a second portion and a third portion arranged between the first and second portions, the waveguide mesa extending in a direction of a waveguide axis; a buried region disposed on the top surface and the side surface of the waveguide mesa; a first electrode opening in the buried region on the first portion of the waveguide mesa; a second electrode opening in the buried region on the second portion of the waveguide mesa; a first electrode in the first electrode opening, the first electrode being electrically connected to a top surface of the first portion of the waveguide mesa through the first electrode opening; and a second electrode in the second electrode opening, the second electrode being electrically connected to a top surface of the second portion of the waveguide mesa through the second electrode opening. The first portion and the second portion of the waveguide mesa include a first conductivity type semiconductor layer, an i-type core layer and a second conductivity type semiconductor layer stacked sequentially on a substrate. The third portion of the waveguide mesa includes the first conductivity type semiconductor layer and the core layer stacked sequentially on the substrate. The third portion of the waveguide mesa does not include the second conductivity type semiconductor layer on the core layer. The second conductivity type semiconductor layers in the first portion and the second portion of the waveguide mesa are physically and electrically isolated from each other. In addition, the first conductivity type semiconductor layer and the core layer in the waveguide mesa have a side surface extending continuously in the direction of the waveguide axis from the first portion to the second portion of the waveguide mesa. Furthermore, the buried region may be formed of a benzocyclobutene (BCB) resin.

In the optical waveguide, the side surfaces of the first conductivity type semiconductor layer in the third portion of the waveguide mesa do not have a substantial change in elevation at the boundary between the first conductivity type semiconductor layer and the core layer, and are connected continuously to the side surfaces of the i-type core layer in the third portion of the waveguide mesa. The side surfaces of the first conductivity type semiconductor layer do not have any elevation changes in the vicinity of the boundary between the first portion and the third portion of the waveguide mesa as well as in the vicinity of the boundary between the second portion and the third portion of the waveguide mesa.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A method for manufacturing a Mach-Zehnder modulator, a method for manufacturing an optical waveguide, and an optical waveguide according to the present invention will be described with reference to the attached drawings. Where possible, the same reference signs will be used for identical features.

First, a Mach-Zehnder modulator11illustrated inFIG. 1will be described. The Mach-Zehnder modulator11includes a first optical coupler12, a first arm waveguide13, a second arm waveguide14and a second optical coupler15. The first optical coupler12has a first port12aand a second port12boptically connected to a waveguide16aand a waveguide16b, respectively, as well as has a third port12cand a fourth port12doptically connected to the first arm waveguide13and the second arm waveguide14, respectively. The second optical coupler15has a first port15aand a second port15boptically connected to a waveguide17aand a waveguide17b, respectively, as well as has a third port15cand a fourth port15doptically connected to the first arm waveguide13and the second arm waveguide14, respectively. An n-side electrode18is disposed between the first arm waveguide13and the second arm waveguide14. A first p-side electrode (DC electrode) and a second p-side electrode (AC electrode) are disposed on the first arm waveguide13. The first p-side electrode (DC electrode) is connected to a first portion13aof the first arm waveguide13. The second p-side electrode (AC electrode) is connected to a second portion13bof the first arm waveguide13. A third portion13cof the first arm waveguide13is disposed between the first portion13aof the first arm waveguide13and the second portion13bof the first arm waveguide13. The third portion13cisolates an upper cladding layer of the first portion13afrom an upper cladding layer of the second portion13b. The optical waveguides constituting the Mach-Zehnder modulator11include a lower cladding layer, an i-type core layer and an upper cladding layer sequentially disposed on a substrate. Specifically, the first portion13aand the second portion13bof the first arm waveguide13include a lower cladding layer, an i-type core layer and an upper cladding layer, whilst the third portion13cincludes the lower cladding layer and the i-type core layer. Because of the absence of the upper cladding layer in the third portion13c, the first portion13aand the second portion13bare electrically isolated from each other. The second arm waveguide14has a similar structure to the first arm waveguide13.

First Embodiment

Next, a method for manufacturing a Mach-Zehnder modulator and a method for manufacturing an optical waveguide will be described with reference toFIGS. 2A to 9I.

As illustrated inFIGS. 2A and 2B, a stacked semiconductor layer20is formed on a substrate21. The stacked semiconductor layer20includes a first cladding layer23, a core layer25and a second cladding layer27that are sequentially grown on the substrate21by a metal-organic vapor phase epitaxy (MOVPE) method.FIGS. 2A,2C,2E and2G are plan views.FIGS. 2B,2D,2F and2H are sectional views taken along the line I-I inFIG. 2A. The substrate21is made of a III-V group compound semiconductor such as InP. Preferably, the substrate21is made of semi-insulating semiconductor such as Fe-doped InP. The first cladding layer23includes a first conductivity type semiconductor, and is, for example, an n-type InP layer (thickness 1.5 μm). The core layer25includes an i-type semiconductor. For example, the core layer25is composed of a multi quantum well (MQW) structure in which AlGaInAs well layers (thickness 12 nm) and AlInAs barrier layers (thickness 8 nm) are stacked alternately. The second cladding layer27includes a second conductivity type semiconductor, and is, for example, a p-type InP layer (thickness 1.3 μm).

Next, waveguide mesa structures that constitute the first arm waveguide13and the second arm waveguide14are formed. As illustrated inFIGS. 2C and 2D, an insulating layer29is formed on the stacked semiconductor layer20. The insulating layer29is made of a dielectric material such as SiO2, SiON, or SiN. The insulating layer29is formed by a chemical vapor deposition (CVD) method, for example. Thereafter, as illustrated inFIGS. 2E and 2F, a resist31is applied on the insulating layer29. For example, the resist31is formed on the entire surface of the insulating layer29by a spin coating method. A resist mask31awhich has a pattern for forming the waveguide of the Mach-Zehnder modulator is formed by photolithography, as illustrated inFIGS. 2G and 2H.

As illustrated inFIGS. 3A and 3B, the insulating layer29is etched through the resist mask31a, thereby transferring the resist pattern to the insulating layer. In this manner, a mask29ais formed. Thereafter, as illustrated inFIGS. 3C and 3D, the resist mask31ais removed by washing with an organic solvent and oxygen (O2) plasma ashing. Next, as illustrated inFIGS. 3E and 3F, the stacked semiconductor layer20is etched through the mask29ato form a waveguide mesa33by, for example, a reactive ion etching (RIE) method. The waveguide mesa33extends in a direction of a waveguide axis. In the RIE process, hydrogen chloride (HCl) gas or hydrogen iodide (HI) gas is used as the etching gas. In the formation of the waveguide mesa33, the second cladding layer27, the core layer25and a portion of the first cladding layer23are etched by the dry etching method with the mask29a. As a result of this etching, the waveguide mesa33including a second cladding layer27a, a core layer25aand a first cladding layer23ais formed on the substrate21. Subsequently, as illustrated inFIGS. 3G and 3H, the mask29ais removed by, for example, wet etching with buffered hydrofluoric acid (BHF).

Next, where necessary, a mesa structure for isolating elements (element-isolating mesa) is formed. A portion of the first cladding layer23awhich is exposed on the substrate21by etching the stacked semiconductor layer20is etched to form a first cladding layer22a. As a result of this, the semi-insulating InP substrate is exposed. The principal surface of the substrate21then has a portion covered with the first cladding layer22aon which the waveguide mesa33is formed, and a portion defined by the surface of the semi-insulating InP substrate. Specifically, first, an insulating layer is formed for use as an etching mask on the substrate21on which the waveguide mesa33has been formed. For example, this insulating layer is made of a dielectric material such as SiO2, SiON, or SiN. Next, a resist mask having a pattern for forming the element-isolating mesa structure is formed on the insulating layer. Through this resist mask, the insulating layer is etched by, for example, a RIE method with CF4gas to form an insulating mask. Thereafter, the resist layer is removed by washing with an organic solvent and oxygen (O2) plasma ashing. While using this insulating mask as the etching mask, portions of the first cladding layer23aon the substrate21are etched by, for example, a RIE method. In this manner, an island-shaped element-isolating mesa structure is formed. The element-isolating mesa structure includes the first cladding layer22aon which the waveguide mesa33is formed. Then, the insulating mask is removed with BHF.

Next, an insulating layer35is formed on the substrate21having the waveguide mesa33so as to cover the waveguide mesa33. For example, the insulating layer35is made of a dielectric material such as SiO2, SiN or SiON. In the embodiment, the insulating layer35is made of SiON.

After the insulating layer35is formed, as illustrated inFIGS. 4A and 4B, a dummy buried region (also referred to as a masking buried region)37is formed on a top surface and a side surface of the waveguide mesa33covered with the insulating layer35to bury the waveguide mesa33. In the embodiment, the dummy buried region (masking buried region)37serves as a first buried region. In this embodiment, the dummy buried region37is composed of, for example, spin-on-glass (SOG). By embedding the waveguide mesa33in the dummy buried region37of SOG, a top surface of the dummy buried region37is planarized. Therefore, the dummy buried region37has a flat surface. In this embodiment, the dummy buried region37is formed by applying SOG and baking the SOG (for example, at 100° C. for 2 minutes and at 200° C. for 2 minutes). Further, the SOG is subjected to a curing process (for example, at 300° C. for 2 minutes).

Next, an isolation structure to separate two portions of the waveguide electrically and physically is manufactured. An example will be discussed based on the Mach-Zehnder modulator11illustrated inFIG. 1. In the following description, the waveguide mesa33refers to the first arm waveguide13. The second arm waveguide14has a similar structure as the first arm waveguide13, and thus the description thereof will be omitted. As already described, the waveguide mesa33is configured such that a first portion (the first portion13ainFIG. 1) and a second portion (the second portion13binFIG. 1) are electrically isolated from each other by a third portion (the third portion13cinFIG. 1) disposed between the first portion (the first portion13ainFIG. 1) and the second portion (the second portion13binFIG. 1). The third portion (the third portion13cinFIG. 1) allows these portions to be isolated from each other.

Such a third portion is produced in the waveguide mesa33. First, steps are performed to expose the top surface of the waveguide mesa33. As illustrated inFIGS. 4C and 4D, a resist39for forming a mask is applied on the substrate21and the top surface and side surface of the waveguide mesa33to cover the waveguide mesa33in a manner similar to that described above. As illustrated inFIGS. 4E and 4F, a resist mask39ais formed on the flat surface of the dummy buried region37. This resist mask39ahas an opening39babove the third portion of the waveguide mesa33. The width W1 of the opening39bis larger than the width WG of the waveguide mesa33. The waveguide mesa33is buried with SOG, and the surface of the SOG has been planarized. As mentioned above, the resist39is applied on the flat surface of the dummy buried region37. The resist39having a thin and uniform thickness can be used. Therefore, the resist mask39ahaving a high-accuracy pattern is formed.

While using the resist mask39a, the dummy buried region37and the insulating layer35are etched. Consequently, as illustrated inFIGS. 4G and 4H, an insulating mask41is formed. In this etching, the SOG is removed by RIE with CF4gas using the resist mask39ato form a patterned SOG. The insulating layer35is exposed in the opening39bof the resist mask39athrough the patterned SOG. Further, the insulating layer35made of, for example, SiON is etched using the patterned SOG as an etching mask. As a result, the insulating mask41is formed. In this manner, the top of the waveguide mesa33is selectively exposed. The insulating mask41includes an insulating layer35aand a dummy buried region37a.

Thereafter, as illustrated inFIGS. 5A and 5B, the resist mask39ais removed by washing with an organic solvent and oxygen (O2) plasma ashing. The insulating mask41has an opening41bcorresponding to the opening39bof the resist mask39a. The insulating mask41covers the side surfaces and the top surfaces of a first portion33aand a second portion33bof the waveguide mesa33, as well as covers the side surfaces of a third portion33cof the waveguide mesa33. The dummy buried region37ahas an opening37bcorresponding to the opening39bof the resist mask39a. The insulating layer35acovers the side surfaces and the top surfaces of the first portion33aand the second portion33bof the waveguide mesa33, as well as covers the side surfaces of the third portion33cof the waveguide mesa33. Further, the dummy buried region37acovers the side surfaces and the top surfaces of the first portion33aand the second portion33bof the waveguide mesa33, as well as covers the side surfaces of the third portion33cof the waveguide mesa33. The insulating layer35ahas an opening35bcorresponding to the opening39bof the resist mask39a. The opening37band the opening35bare located on the third portion33cof the waveguide mesa33. The top surface of the waveguide mesa33is exposed in the opening37band the opening35b.

As illustrated inFIGS. 5C and 5D, the second cladding layer of the waveguide mesa33is etched by, for example, RIE with HCl gas or HI gas through the insulating mask41to expose the top surface of the core layer25a. In this embodiment, for example, the waveguide mesa33is etched through the SOG and the SiON layer as the mask until the top surface of the core layer25ais exposed. Because the insulating layer35ahas the opening35bonly on the top surface of the third portion33cof the semiconductor waveguide mesa33, the first cladding layer22aand the element-isolating mesa structure located under the core layer25aof the waveguide mesa33are not etched.

After the waveguide mesa33is etched using insulating mask41, a protrusion38of the semiconductor layer may remain on the core layer25aalong the interface between the waveguide mesa and the dielectric film of SiON as illustrated inFIG. 5E. Where necessary, as illustrated inFIG. 5F, the protrusion38of the semiconductor layer is removed by etching with diluted hydrochloric acid after the etching of the waveguide mesa33. In the step of etching the waveguide mesa33, the semiconductor layer that is exposed in the third portion33cof the waveguide mesa33is the core layer (MQW composed of AlGaInAs/AlInAs). These materials constituting the core layer are negligibly etched with diluted hydrochloric acid. Thus, the protrusion of the semiconductor layer is selectively removed by etching with diluted hydrochloric acid while the core layer exposed in the third portion33cof the waveguide mesa33is not substantially etched.

After etching the second cladding layer in the third portion of the waveguide mesa33, the insulating mask41is removed as illustrated inFIGS. 5G and 5H. In this embodiment, the dummy buried region37aand the insulating layer35aare removed by etching. For example, this removal is performed as described below. As a result of the removal, the second cladding layer defines the uppermost layer in the first and second portions of the waveguide mesa33, and the core layer defines the uppermost layer in the third portion of the waveguide mesa (the waveguide mesa43inFIG. 6A). In this third portion of the waveguide mesa, the i-type core layer is exposed as the top surface. Thus, the second cladding layer in the first portion of the waveguide mesa33is physically and electrically isolated from the second cladding layer in the second portion.

The dummy buried region37amade of SOG is removed by etching with a mixed gas including CF4and O2. The etching exposes the insulating layer35amade of a dielectric film of SiON, for example. After the removal of the dummy buried region37a, the insulating layer35ais removed by etching with hydrofluoric acid (such as BHF).

In this embodiment, the insulating layer35is formed as the protective layer covering the waveguide mesa33. Thereafter, the dummy buried region37and the insulating layer35are etched through the resist mask39ato form the insulating mask41. Further, the second cladding layer of the semiconductor waveguide mesa33is etched through the insulating mask41. Alternatively, the dummy buried region37may be formed directly on the waveguide mesa without the formation of the insulating layer35, and the dummy buried region37may be etched through the resist mask39a, thereby forming a mask composed of the dummy buried region37. In this case, the second cladding layer of the semiconductor waveguide mesa33may be etched using the dummy buried region37aas a mask which has an opening37bcorresponding to the opening39bof the resist mask39a. In this case too, the dummy buried region37acovers the side surfaces and the top surfaces of the first portion33aand the second portion33bof the waveguide mesa33, as well as covers the side surfaces of the third portion33cof the waveguide mesa33. Because the dummy buried region37ahas the opening37bonly on the top surface of the third portion33cof the waveguide mesa33, the first cladding layer22aand the element-isolating mesa structure located under the core layer25aof the waveguide mesa33are appropriately protected from etching.

Next, as illustrated inFIGS. 6A and 6B, an insulating layer45is formed on a top surface and a side surface of a waveguide mesa43which corresponds to the waveguide mesa33. For example, the insulating layer45is made of a dielectric material such as SiO2, SiON, or SiN. The waveguide mesa43includes a first portion43a, a third portion43cand a second portion43barranged sequentially along the direction of the waveguide axis.

After the insulating layer45is formed as the protective film, as illustrated in FIGS.6C and6D, a buried region47is formed on the side surfaces and the top surface of the waveguide mesa43as well as on the substrate21. In the embodiment, the buried region47serves as a second buried region. In this embodiment, the buried region47is formed of, for example, a benzocyclobutene (BCB) resin. The thickness of the BCB resin is preferably not less than 2 μm on the waveguide mesa43.

Next, the formation of p-side electrodes and n-side electrode will be described. As illustrated inFIGS. 6E and 6F, a resist49is formed on the flat surface47aof the buried region47. In this embodiment, openings for p-side electrodes are formed first.

As illustrated inFIGS. 7A and 7B, the procedures described hereinabove are repeated to form a resist mask51having a perforated pattern for the formation of p-side electrodes. In this embodiment, the resist mask51has an opening51aabove the first portion43a, and an opening51babove the second portion43bof the waveguide mesa43. On the other hand, the resist mask51covers an area above the third portion43cof the waveguide mesa43.

As illustrated inFIGS. 7C and 7D, the buried region47is etched through the resist mask51to form openings47aand47bin the buried region47. In this embodiment, the BCB resin is etched by RIE with a mixed gas including CF4and O2.

As illustrated inFIGS. 7E and 7F, the insulating layer45is etched through the resist mask51to form openings45aand45bin the insulating layer45. In this embodiment, the insulating layer45formed of, for example, SiO2is etched by RIE with CF4gas. A top surface43aof the waveguide mesa43is exposed through the openings45aand45bformed on the first portion43aand the second portion43bof the waveguide mesa43, respectively. As illustrated inFIGS. 7G and 7H, the resist mask51is removed with an organic solvent, for example.

Next, an opening for the formation of n-side electrode is formed. As illustrated inFIGS. 8A and 8B, a resist53is formed on the surface47aof the buried region47and on the top surface43aof the waveguide mesa43through the openings45aand45b. As illustrated inFIGS. 8C and 8D, the procedures described hereinabove are repeated to form a resist mask55having a perforated pattern for the formation of n-side electrode. In this embodiment, the resist mask55covers the top surface extending from the first portion43ato the second portion43bof the waveguide mesa43. Further, the resist mask55has an opening55con the element-isolating mesa structure connected to the waveguide mesa43.

As illustrated inFIGS. 8E and 8F, the buried region47is etched through the resist mask55to form an opening47cin the buried region47. In this embodiment, the buried region47formed of, for example, a BCB resin is etched by RIE with a mixed gas including CF4and O2.

As illustrated inFIGS. 8G and 8H, the insulating layer45is etched through the resist mask55to form an opening45cin the insulating layer45. In this embodiment, the insulating layer45formed of, for example, SiO2is etched by RIE with CF4gas. A top surface22bof the first cladding layer22aof the element-isolating mesa structure is exposed through the opening45cin the insulating layer45. As illustrated inFIGS. 9A and 9B, the resist mask55is removed with an organic solvent, for example.

As illustrated inFIGS. 9C and 9D, p-side electrodes57are formed on the first portion and the second portion of the waveguide mesa43. The p-side electrodes57are formed by, for example, depositing Ti/Pt/Au by a vacuum deposition method. In forming the p-side electrodes57, a lift-off method is preferably used to obtain a patterned electrode. After forming the p-side electrodes57, annealing is performed, for example, at 320° C. for 3 minutes in order to obtain good ohmic contact.

As illustrated inFIGS. 9E and 9F, an n-side electrode59is formed on the element-isolating mesa structure. The n-side electrode59is formed by, for example, depositing AuGeNi/Au by a vacuum deposition method. In forming the n-side electrode59, a lift-off method is preferably used to obtain a patterned electrode. After forming the n-side electrode59, annealing is performed, for example, at 300° C. for 3 minutes in order to obtain good ohmic contact.

As illustrated inFIGS. 9G,9H and9I, plating layers are formed on the p-side and n-side electrodes,57and59. Thereafter, the back surface of the substrate21is polished to reduce the thickness of the substrate to, for example, 100 μm. Through these steps described hereinabove, a Mach-Zehnder modulator11according to this embodiment is manufactured.

Second Embodiment

Next, a method for manufacturing a Mach-Zehnder modulator and a method for manufacturing an optical waveguide will be described with reference toFIGS. 10A to 10FandFIGS. 11A to 11H. While the first embodiment involves SOG in the dummy buried region, the SOG may be replaced by a hard-baked resist. The second embodiment utilizes a dummy buried region including a resist instead of the dummy buried region37in the first embodiment.

Next, steps for exposing the top surface of the waveguide mesa33will be described. In the first embodiment, after the element-isolating mesa structure is formed, the insulating mask29ais removed as illustrated inFIGS. 3G and 3H, and the insulating layer35(such as SiON) is formed as the protective layer covering the waveguide mesa33as illustrated inFIGS. 3I and 3J. In the second embodiment, the formation of the insulating layer35is followed by the following steps. As illustrated inFIGS. 10A and 10B, a dummy buried region (also referred to as a masking buried region)63is formed on the waveguide mesa33covered with the insulating layer35. In this embodiment, a first resist (referred to as resist63) is applied for forming the dummy buried region63. After the resist63is applied, as illustrated inFIGS. 10C and 10D, a portion of the resist63is removed by etching over the entire surface uniformly by an ashing process until the insulating layer35covering the top of the waveguide mesa33is exposed. Thereafter, the resist63is baked to form a cured resist63a. For example, the baking treatment for the resist63is performed at 160° C. for 30 minutes. The cured resist63adefines the dummy buried region. (Hereinafter, the cured resist63awill be also referred to as the dummy buried region.)

Next, as illustrated inFIGS. 10E and 10F, a second resist65is formed on the cured resist63a. As illustrated inFIGS. 11A and 11B, the second resist65is exposed and developed through a photomask or a reticle, and then a patterned second resist65ais formed. Because the cured resist63ahas been hard-baked, the shape of the cured resist63ais not substantially changed during developing the second resist65. The patterned second resist65ahas an opening65bon the third portion of the waveguide mesa33. The width of the opening65bis larger than the width of the waveguide mesa33. In the opening65bof the patterned second resist65a, the insulating layer35covering the top of the third portion of the waveguide mesa33is exposed.

As illustrated inFIGS. 11C and 11D, the insulating layer35covering the top of the third portion33cof the waveguide mesa33is etched using the patterned second resist65aas a mask, thereby forming an insulating layer35a. As a result of this etching of the insulating layer35, the top of the third portion33cof the waveguide mesa33is exposed.

Except a portion of the waveguide mesa33, the side surfaces and the top surface of the waveguide mesa33are covered with the insulating layer35a. Specifically, the portion of the waveguide mesa33exposed from the insulating layer35ais the top surface of the third portion33cof the waveguide mesa33that is visible through the opening65bof the patterned second resist65a. After the top of the third portion33cof the waveguide mesa33is exposed, as illustrated inFIGS. 11E and 11F, the patterned second resist65aand the cured resist63aare removed. Through these steps, an insulating mask61is formed. The patterned second resist65aand the cured resist63aare removed by washing with an organic solvent and oxygen (O2) plasma ashing. In this embodiment, the insulating mask61includes the insulating layer35a.

As illustrated inFIGS. 11G and 11H, the second cladding layer of the waveguide mesa33that is exposed in the opening35bof the insulating layer35ais etched through the insulating mask61. As a result of this etching, the top of the core layer is exposed. In this embodiment, the insulating layer35aconstituting the insulating mask61is made of SiON. In this etching of the waveguide mesa33, the insulating layer35ahas an opening only on the top surface of the third portion33cof the waveguide mesa33. Thus, the first cladding layer and the element-isolating mesa structure located under the core layer of the waveguide mesa33are not etched.

As already mentioned, in etching the waveguide mesa33, a protrusion of the semiconductor layer may remain on the core layer along the interface between the waveguide mesa and the dielectric film of SiON (seeFIG. 5E). Where necessary, the protrusion of the semiconductor layer is etched away with diluted hydrochloric acid after etching the waveguide mesa33. In the etching of the waveguide mesa33through the insulating mask61, the semiconductor layer that is exposed in the third portion of the waveguide mesa33is the core layer (MQW composed of AlGaInAs/AlInAs). These materials constituting the core layer are negligibly etched with diluted hydrochloric acid. Thus, the protrusion of the semiconductor layer is etched away with diluted hydrochloric acid while the core layer exposed in the third portion of the waveguide mesa33is not substantially etched. After etching the semiconductor layer (second cladding layer) in the third portion of the waveguide mesa33, the insulating mask61is removed (seeFIGS. 5G and 5H). Because the cured resist63adefining the dummy buried region has been removed in this embodiment, the insulating layer35ais removed in the step of removing the insulating mask61. When the insulating layer35ais made of SiON, the insulating layer35ais etched with, for example, hydrofluoric acid (such as BHF). As a result of this etching, the second cladding layer defines the uppermost surface in the first portion43aand the second portion43bof the waveguide mesa43(seeFIG. 6A), and the core layer defines the uppermost surface in the third portion43cof the waveguide mesa43. That is, the i-type core layer is exposed as the top surface in the third portion43cof the waveguide mesa43. Thus, the second cladding layer in the first portion43aof the waveguide mesa43is physically and electrically isolated from the second cladding layer in the second portion43b.

The formation of a buried region to bury the waveguide mesa and the subsequent steps are performed in the same manner as in the first embodiment.

Third Embodiment

A method for manufacturing a Mach-Zehnder modulator and a method for manufacturing an optical waveguide will be described with reference toFIGS. 12A to 12FandFIGS. 13A to 13H. The first embodiment involves SOG in the dummy buried region37, and the second embodiment involves the cured resist63aas the dummy buried region63. In the third embodiment, an insulating layer may be used instead of the SOG or the cured resist. The third embodiment involves a dummy buried region (also referred to as a masking buried region)71instead of the dummy buried region37in the first embodiment or the dummy buried region63in the second embodiment.

In this embodiment, after the element-isolating mesa structure is formed, the insulating mask29ais removed as illustrated inFIGS. 3G and 3H. In this embodiment, the insulating layer35is not provided. As illustrated inFIGS. 12A and 12B, a silicon dioxide film (SiO2film)71is formed so as to bury the waveguide mesa33. The silicon dioxide film is formed by the following method. For example, an organic silane compound such as tetraethylorthosilicate (TEOS) is applied by a spin coating method with a thickness larger than the height of the waveguide mesa33, and is thereafter heated with, for example, a hot plate to form a silicon dioxide film71. Alternatively, the silicon dioxide film may be formed by a CVD method using TEOS and oxygen as raw material gases. The use of TEOS as a raw material facilitates the formation of the silicon dioxide film with a large thickness. The silicon dioxide film71is formed over the waveguide mesa33in conformity to the shape of the waveguide mesa33.

Next, as illustrated inFIGS. 12C and 12D, the surface of the silicon dioxide film71is planarized. For example, the planarization is performed by a chemical mechanical polishing (CMP) method. The chemical mechanical polishing is terminated before the top surface of the waveguide mesa33is exposed, thus forming a planarized silicon dioxide film71a. The silicon dioxide film71adefines a dummy waveguide region.

As illustrated inFIGS. 12E and 12F, a resist73is formed on a surface71bof the planarized silicon dioxide film71a. Next, the resist73is treated by a conventional photolithography method to form a pattern for the formation of an opening on the top surface of the waveguide mesa33. Consequently, as illustrated inFIGS. 13A and 13B, a resist mask73ais formed. The resist mask73ahas an opening73babove the top surface of the waveguide mesa33. The width of the opening73bis larger than the width of the waveguide mesa33. The waveguide mesa33is buried with the dummy buried region or the masking buried region. With this configuration, the thickness of the resist73may be reduced. Consequently, the resist mask73awith highly accurate pattern is formed.

The planarized silicon dioxide film71ais etched through the resist mask73a. By this etching process, an insulating mask75(the etched silicon dioxide film) is formed as illustrated inFIGS. 13C and 13D. The insulating mask75has an opening75acorresponding to the position of the waveguide mesa33. The top surface of the waveguide mesa33is exposed in the opening75aof the insulating mask75. The side surfaces of the waveguide mesa33are covered with the insulating mask75. The silicon dioxide film71ais etched by dry etching (RIE) with CF4gas. After the insulating mask75is formed, as illustrated inFIGS. 13E and 13F, the resist mask73ais removed by washing with an organic solvent and oxygen (O2) plasma ashing.

As illustrated inFIGS. 13G and 13H, the uppermost semiconductor layer (the second cladding layer) in the waveguide mesa33is etched by, for example, a dry etching process through the insulating mask75. As a result of this etching, the core layer in the third portion of the waveguide mesa33is exposed. Because the insulating mask75has an opening only on the top surface of the third portion of the waveguide mesa33, the layers located under the core layer of the waveguide mesa are not etched. In etching of the waveguide mesa33, a protrusion of the semiconductor layer may remain on the side surfaces of the insulating mask75(the dummy buried region or the masking buried region). The protrusion of the semiconductor layer is removed by etching with diluted hydrochloric acid after the second cladding layer on the core layer is etched away. The uppermost layer in the waveguide mesa that is exposed by the etching of the second cladding layer is the core layer (MQW composed of AlGaInAs/AlInAs). These materials constituting the core layer are negligibly etched with diluted hydrochloric acid. Thus, the protrusion of the semiconductor layer is etched away with diluted hydrochloric acid while the core layer exposed in the third portion of the waveguide mesa33is not substantially etched. By etching the semiconductor layer (the second cladding layer) in the third portion of the waveguide mesa33, an isolation region is formed between the first portion and the second portion of the waveguide mesa33. Thereafter, the insulating mask75(the dummy buried region or the masking buried region) is removed by etching with, for example, hydrofluoric acid (such as BHF). As a result of the etching, the second cladding layer defines the uppermost surface in the first portion43aand the second portion43bof the waveguide mesa43as illustrated inFIGS. 6A and 6B, and the core layer defines the uppermost surface in the third portion43cof the waveguide mesa43. Because the i-type core layer is exposed as the top surface in the third portion43cof the waveguide mesa43, the second cladding layer in the first portion43aof the waveguide mesa43is isolated from the second cladding layer in the second portion43b.

The formation of a buried region to bury the waveguide mesa and the subsequent steps are performed in the same manner as in the first embodiment.

According to the aforementioned manufacturing method, the dummy buried region71is formed on the waveguide mesa33. Further, an opening is formed in the dummy buried region71aon the top surface of the third portion33cof the waveguide mesa33with use of the mask73ahaving an opening on the third portion33cof the waveguide mesa33, thereby fabricating the insulating mask75including the dummy buried region71a. During the fabrication of the insulating mask75, the side surfaces of the third portion33cof the waveguide mesa33are covered with the insulating mask75. Thus, the side surfaces of the third portion33cof the waveguide mesa33are protected by the insulating mask75. Further, the dummy buried region71aon the top surface of the third portion33cof the waveguide mesa33is selectively etched. By the use of the insulating mask75fabricated in this manner, the second conductivity type semiconductor layer (the second cladding layer)27ain the third portion33cof the waveguide mesa33is selectively etched. During this etching, the first conductivity type semiconductor layer (the first cladding layer)23ais covered with the dummy buried region71a. The first conductivity type semiconductor layer (the first cladding layer)23ais thus not etched. Through these steps, a waveguide mesa having an isolation region is manufactured.

Referring back toFIG. 1, waveguide devices having an isolation region manufactured in the first embodiment, the second embodiment and the third embodiment is described.FIG. 1illustrates a Mach-Zehnder modulator as an example of the waveguide devices having the isolation region. The waveguide device having the isolation region includes waveguide mesas (waveguide mesas43) that have a first portion13a(14a), a third portion13c(14c) and a second portion13b(14b) arranged along the direction of the waveguide axis. The third portion13c(14c) is disposed between the first portion13a(14a) and the second portion13b(14b). The first portion13a(14a) and the second portion13b(14b) of the waveguide mesa43include a first conductivity type semiconductor layer, a core layer and a second conductivity type semiconductor layer stacked sequentially on the substrate. The third portion13c(14c) of the waveguide mesa43includes the first conductivity type semiconductor layer and the core layer stacked sequentially on the substrate. The side surfaces of the first conductivity type semiconductor layer and the side surfaces of the core layer in the waveguide mesa43extend continuously in the direction of the waveguide axis from the first portion13a(14a) to the second portion13b(14b) of the waveguide mesa43via the third portion13c(14c).

According to the manufacturing methods in the first embodiment, the second embodiment and the third embodiment, an opening is formed in the dummy buried region (the masking buried region)37,63, or71aon the top surface of the third portion33cof the waveguide mesa33with use of the resist mask39a,65a, or73a. While using the resist mask39a,65a, or73a, an opening is formed in the insulating layer35or71aon the top surface of the third portion33cof the waveguide mesa33. The insulating layer and dummy buried region (the masking buried region) having the opening constitute the insulating mask41. During the fabrication of the insulating mask41, the dummy buried region (the masking buried region)37,63, or71acovers the side surfaces of the first portion33aand the second portion33bof the waveguide mesa33as well as covers the side surfaces of the third portion33cof the waveguide mesa33. With this configuration, the side surfaces of the third portion33cof the waveguide mesa33can be protected by the dummy buried region or the masking buried region when an opening is formed in the dummy buried region (the masking buried region). Further, the above configuration allows for selective etching of the insulating layer35,71aon the top surface of the third portion33cof the waveguide mesa33. By using the insulating mask41, the second conductivity type semiconductor layer27ain the third portion33cof the waveguide mesa33is etched selectively. During this etching, the first conductivity type semiconductor layer22ais not exposed to the etchant. Through these steps, the waveguide mesa43having an isolation region in the third portion43cis manufactured.

Referring back toFIG. 1andFIGS. 9G,9H and9I, the waveguide mesa43(13) having an isolation region will be described. The waveguide mesa43(13) includes a first portion43a(13a), a third portion43c(13c) and a second portion43b(13b) arranged along the direction of the waveguide axis. The first portion43a(13a) and the second portion43b(13b) of the waveguide mesa43(13) include a first conductivity type semiconductor layer22a, a core layer25aand a second conductivity type semiconductor layer27astacked sequentially on the substrate21. The third portion43c(13c) of the waveguide mesa43(13) includes the first conductivity type semiconductor layer22aand the core layer25astacked sequentially on the substrate21. In the first portion43a(13a) and the second portion43b(13b) of the waveguide mesa43(13), the second conductivity type semiconductor layer27ais isolated from each other by forming the third portion43c(13c) between the first portion43a(13a) and the second portion43b(13b). The third portion43c(13c) serves as the isolation region. The side surfaces (22binFIG. 9) of the first conductivity type semiconductor layer22aand the side surfaces (25binFIG. 9) of the core layer25ain the waveguide mesa43(13) extend continuously in the direction of the waveguide axis from the first portion43a(13a) to the second portion43b(13b) of the waveguide mesa43(13) via the third portion43c(13c).

Specifically, in the embodiment, the side surfaces22bof the first conductivity type semiconductor layer22ain the third portion43c(13c) of the waveguide mesa43(13) do not have a substantial change in elevation at the boundary between the first conductivity type semiconductor layer22aand the core layer25a, and are connected continuously to the side surfaces25bof the i-type core layer25ain the third portion43c(13c) of the waveguide mesa43(13). The side surfaces22bof the first conductivity type semiconductor layer22ado not have any elevation changes in the vicinity of the boundary between the first portion43aand the third portion43cof the waveguide mesa43as well as in the vicinity of the boundary between the second portion43band the third portion43cof the waveguide mesa43.

The method for manufacturing the Mach-Zehnder modulator and the method for manufacturing the optical waveguide having the isolation region will be further described below.FIG. 14is a diagram illustrating primary steps in the method for manufacturing the Mach-Zehnder modulator and the method for manufacturing the optical waveguide having the isolation region. Where possible, the reference signs used in the aforementioned embodiments will be used in the description ofFIG. 14to facilitate understanding of the invention.

The method for manufacturing a Mach-Zehnder modulator11includes a step S101in which a stacked semiconductor layer20including a first conductivity type semiconductor layer23, a core layer25and a second conductivity type semiconductor layer27is formed on a substrate21. The core layer25includes an i-type (non-doped) semiconductor layer. In a step S102, a waveguide mesa33which extends in a direction of a waveguide axis is formed by etching the stacked semiconductor layer20using a stripe-shaped mask. The waveguide mesa33includes a first portion33a, a second portion33band a third portion33c. The first portion33a, the third portion33cand the second portion33bare arranged sequentially along the direction of the waveguide axis. In a step S103, an insulating layer35is formed on the substrate21so as to cover the top surface and the side surfaces of the waveguide mesa33. After the insulating layer35is formed, a step S104is performed in which a dummy buried region37or63is formed to bury the top surface and the side surfaces of the waveguide mesa33. In a step S105, a mask39aor65ais formed on the dummy buried region37or63. The mask has an opening on the third portion33cof the waveguide mesa33. The dummy buried region37or63is made of a different material from the insulating layer35. In a step S106, the dummy buried region37or63is etched through the mask39aor65ato form an opening37bor63b. Through the opening37bor63b, the insulating layer35on the third portion33cof the waveguide mesa33is exposed. After the opening is formed in the dummy buried region37or63, a step S107is performed in which an opening35bis formed in the insulating layer35on the top surface of the third portion33cof the waveguide mesa33with the use of the mask39aor65a. Consequently, the insulating layer35defines an insulating mask35a. The insulating mask35acovers the top surface and the side surfaces of the first portion33aas well as the top surface and the side surfaces of the second portion33bof the waveguide mesa33. During the fabrication of the insulating mask35afrom the insulating layer35, the dummy buried region37aor63acovers the side surfaces of the third portion33cof the waveguide mesa33. In a step S108, after the mask39aor65ais removed, the second conductivity type semiconductor layer27ain the third portion33cof the waveguide mesa33is etched through the insulating mask35a. Through this step S108, the second conductivity type semiconductor layer27ais removed. Next, the dummy buried region37aor63ais removed in a step S109. Where necessary, the dummy buried region37aor63amay be removed after removing the residue of the second conductivity type semiconductor layer27a. Alternatively, as required, the dummy buried region37aor63amay be removed before etching the second conductivity type semiconductor layer27ain the third portion43cof the waveguide mesa43. After etching the second conductivity type semiconductor layer27a, a step S110is performed in which the insulating mask35ais removed.

After the insulating mask35ais removed, an insulating layer45is formed in a step S111so as to cover the surface of the waveguide mesa33. After forming the insulating layer45, further, a buried region47is formed which buries the waveguide mesa33. In a step S112, the insulating layer45and the buried region47are processed to form a first electrode opening47atherein. As a result, the top surface of the first portion43aof the waveguide mesa43is exposed through the first electrode opening47a. After the first electrode opening47ais formed in the buried region47, a step S113is performed in which a first electrode57is formed in the first electrode opening47aso as to be electrically connected to the top surface of the first portion43aof the waveguide mesa43. In forming the first electrode opening47ain the insulating layer45and the buried region47, a second electrode opening47bmay be formed in the insulating layer45and the buried region47. The top surface of the second portion43bof the waveguide mesa43is exposed through the second electrode opening47b. Further, in forming the first electrode57, a second electrode57may be formed in the second electrode opening47b. The second electrode57is connected to the top surface of the second portion43bof the waveguide mesa43via the second electrode opening47b. According to this manufacturing method, the second electrode57is electrically isolated from the first electrode57because the isolation structure is formed in the waveguide mesa43. Specifically, the third portion43cconstituting the isolation structure is formed between the first portion43aand the second portion43b. The first portion43aand the second portion43bare physically and electrically isolated from each other.

In the first embodiment, preferably, the dummy buried region is made of SOG and the insulating layer35is an insulating layer made of a dielectric material such as SiO2, SiN or SiON. By using SOG as the material of the dummy buried region, the dummy buried region may be easily removed after the waveguide mesa burying step and the semiconductor etching step. In the first embodiment, the dummy buried region is removed after etching the second conductivity type semiconductor layer27ain the third portion43cof the waveguide mesa43.

Preferably, in the step S105(in which the dummy buried region is formed), a resist is applied to form the dummy buried region and the resist is then hard baked. That is, the dummy buried region is preferably composed of the cured resist. By being hard baked, the resist becomes resistant to the developer used in the patterning of the resist mask. When the dummy buried region is composed of the cured resist, the cured resist may be removed while ensuring that the semiconductors and the insulating mask will not be damaged. In the second embodiment, the dummy buried region is removed before etching the second conductivity type semiconductor layer27ain the third portion43cof the waveguide mesa43.

Further,FIG. 15shows a diagram illustrating primary steps in the method for manufacturing the Mach-Zehnder modulator and the method for manufacturing the optical waveguide having the isolation region. Where possible, the reference signs used in the aforementioned embodiments will be used in the description ofFIG. 15to facilitate understanding of the invention.

After the step of forming the waveguide mesa33from the stacked semiconductor layer20(the step S102) inFIG. 14, a step S114is performed in which a masking buried region (for example, a dummy buried region37,63a, or71a) is formed so as to bury the top surface and the side surfaces of the waveguide mesa33. For forming the masking buried region37or63a, an insulating layer35is formed. Here, the insulating layer35is in contact with the top surface and the side surfaces of the waveguide mesa33. Further, the dummy buried region37or63ais in contact with the top surface and the side surfaces of the insulating layer35on the waveguide mesa33. Alternatively, the masking buried region (the dummy buried region71a) may be formed without the formation of the insulating layer35. In this case, the masking buried region is in contact with the top surface and the side surfaces of the waveguide mesa33. In the embodiment, the masking buried region constitutes the insulating mask75which serves as an etching mask. The following description will use the reference signs in the second embodiment. In a step S115, a mask73ais formed. The mask73ais disposed on the waveguide mesa33, and has an opening on the third portion33cof the waveguide mesa33. In a step S16, an opening is formed in the masking buried region on the third portion33cof the waveguide mesa33with the use of the mask73a, and consequently the masking buried region defines an insulating mask75. In forming the insulating mask75from the masking buried region, the dummy buried region71acovers the side surfaces of the third portion33cof the waveguide mesa33. In a step S117, the mask73ais removed, and thereafter the second conductivity type semiconductor layer27ain the third portion33cof the waveguide mesa33is etched using the insulating mask75as an etching mask. The insulating mask75covers the side surfaces of the third portion33cof the waveguide mesa33. After etching the second conductivity type semiconductor layer27a, the step S118is performed in which the masking buried region (insulating mask75) is removed. After removing the insulating mask75, the step S111and the subsequent steps are performed.

The dummy buried region71aincludes silicon dioxide. In forming the dummy buried region71aso as to bury the top surface and the side surfaces of the waveguide mesa33, a silicon dioxide layer71is formed on the top surface and the side surfaces of the waveguide mesa33. The surface of this silicon dioxide layer71is planarized to form the dummy buried region71a. After the dummy buried region71ais formed, an opening is formed in the dummy buried region71aon the third portion33cof the waveguide mesa33. In forming the opening in the dummy buried region71a, the side surfaces of the first conductivity type semiconductor layer22ain the third portion33cof the waveguide mesa33are protected.

The scope of the present invention is not limited to the specific configurations disclosed in the aforementioned embodiments.