METHOD FOR REDUCING WAFER EDGE DEFECTS

A method for reducing wafer edge defects is provided. The method includes providing a wafer with a central region and an edge region, forming a hard mask layer on the wafer, forming a spacer pattern on the hard mask layer, forming a photoresist layer covering the spacer pattern, performing a wafer edge treatment process on the photoresist layer to form an annular photoresist pattern, using the annular photoresist pattern as an etching mask, and sequentially transferring the exposed spacer pattern to the hard mask layer and the wafer to form a plurality of trenches in the wafer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of Taiwan Patent Application No. 112130070 filed on Aug. 10, 2023, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to a semiconductor process, and in particular to method for reducing wafer edge defects.

Description of the Related Art

In the semiconductor manufacturing process, the wafer edge is usually not fully exposed due to limitations in the lithography process technology, and therefore the wafer edge is an invalid wafer region. In addition, wafer edges can also be affected by the uniformity of film deposition, uniformity of photoresist coating, exposure defocus, and etch loading. This makes the wafer edges a source of defects. Therefore, during the subsequent deposition or etching process, defects such as fragments or particles may be generated and released into the central region of the wafer, resulting in a lower product yield.

The lithography process has entered the generation of pattern disassembly, which means that the patterns in the array region and the peripheral region are exposed individually. In general, in order to prevent wafer edges from becoming a source of defects and to maintain the consistency of chemical mechanical polishing, an edge treatment process such as edge bead removal (EBR) or wafer edge exposure (WEE) is usually performed to remove or retain the photoresist in the edge region and reduce the effect of defects caused by incomplete exposure of the wafer edges. However, this may result in a ring of overlapping or non-overlapping portions at the junction of the array region and the peripheral region, which may cause either the film or the pattern to form an undesired height difference, as well as producing a large number of defects. The height difference may not be overcome in the planarization process (e.g., a chemical mechanical polishing treatment).

BRIEF SUMMARY OF THE INVENTION

An embodiment of the present disclosure provides a method for reducing edge defects, including: providing a wafer with a central region and an edge region, wherein the edge region includes a first edge region surrounding the central region, a second edge region surrounding the first edge region, and a third edge region surrounding the second edge region; forming a hard mask layer on the wafer; forming a spacer pattern on the hard mask layer; forming a photoresist layer covering the spacer pattern; performing a wafer edge treatment process on the photoresist layer to form an annular photoresist pattern, wherein the annular photoresist pattern selectively covers the spacer pattern located in at least one of the first edge region, the second edge region, and the third edge region and exposes the spacer pattern in the central region; and using the annular photoresist pattern as an etching mask, sequentially transferring the exposed spacer pattern to the hard mask layer and the wafer to form a plurality of trenches in the wafer.

DETAILED DESCRIPTION OF THE INVENTION

The present disclosure provides methods of combining an additional wafer edge treatment process at the lithography process step, which may form a multi-layered edge structure at current layer and eliminate the height differences at specific locations. Therefore, the problem of undesired defects at the wafer edge may be improved, and without performing an additional wafer edge bevel etching process or sacrificing process margins for subsequent planarization process.

FIG.1illustrates a top view of the wafer100.FIGS.2A and2Billustrate cross-sectional views along a line A-A′ of an edge region102ofFIG.1and along a line B-B′ of a central region104ofFIG.1, respectively. The wafer100has a central region104and an edge region102. The edge region102includes a first edge region102A surrounding the central region104, a second edge region102B surrounding the first edge region102A, and a third edge region102C surrounding the second edge region102B, but the number of the edge regions is not limited to it. Due to the properties of the lithography process, the edge region102of the wafer100may not be completely exposed, and therefore the edge region102is defined as an invalid wafer region. The width of each of the first edge region102A, the second edge region102B, and third edge region102C depends on the process margins of the subsequent wafer edge process. In one embodiment, the width of each of the first edge region102A, the second edge region102B, and third edge region102C is from about 0.5 mm to 1.5 mm. In one embodiment, the width of the edge region102is from about 3 mm to 3.5 mm.

Referring toFIGS.2A and2B, a hard mask layer106is formed on the wafer100. The hard mask layer106may be formed by chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process. The material of the hard mask layer106may include silicon oxide formed from tetraethylorthosilicate (TEOS), silicon nitride, or silicon oxynitride.

Referring toFIGS.3A and3B, a self-alignment double patterning (SADP) process is performed to form a spacer pattern on the hard mask layer106. In one embodiment, the SADP process includes forming a patterned mandrel108on the hard mask layer106. A spin-on coating process may be performed to form a mandrel layer (not shown) on the hard mask layer106, and then a lithography process and etching process may be performed to form the patterned mandrel108. Since the formation of the mandrel layer is affected by the uniformity of deposition of the film, the mandrel layer in the edge region102may have an uneven thickness decreasing towards the edges of the wafer100. As a result, the patterned mandrel108in the edge region102may also have an uneven height decreasing towards the edge of wafer100, while the patterned mandrel108in the center region104has the same height. In other embodiments, a trimming process may additionally be performed on the patterned mandrel108to further reduce the dimension of the patterned mandrel108. In one embodiment, the patterned mandrel108may be a single-layered structure or a multi-layered structure, and the material of the patterned mandrel108may include carbon, silicon oxynitride, bottom anti-reflective coating (BARC), or a combination thereof.

Referring toFIGS.4A and4B, the SADP process further includes conformally forming a spacer material layer110on the hard mask layer106and the patterned mandrel108. The spacer material layer110may be formed by CVD, ALD, or a combination thereof. The material of the spacer material layer110may be an oxide such as silicon oxide.

Referring toFIGS.5A and5B, the SADP process further includes performing an etching-back process112on the spacer material layer110to form a spacer pattern114and expose the top surface of the patterned mandrel108and the top surface of a portion of the hard mask layer106. The etching-back process112may include an anisotropic etching process (or directional etching process) such as reactive ion etching (RIE) process, plasma etching, inductively coupled plasma (ICP) etching, or dry etching processes of a combination thereof.

Referring toFIGS.6A and6B, the SADP process further includes removing the patterned mandrel108to remain a spacer pattern114on the hard mask layer106. Since the patterned mandrel108has an uneven height in the edge region102, the spacer pattern114originally located on the sidewalls of the patterned mandrel108also has an uneven height in the edge region102. The patterned mandrel108may be removed by ashing process, wet etching, dry etching, or a combination thereof.

Referring toFIGS.7A and7B, a photoresist layer116is formed to cover the spacer pattern114. The photoresist layer116may be formed by spin-on coating process. In the present disclosure, the photoresist layer116may be a positive photoresist or a negative photoresist. The positive photoresist is defined as the exposed portion is removed after the developing process (i.e., the photoresist becomes soluble after exposure), and the negative photoresist is defined as the exposed portion is remained after the developing process (i.e., the photoresist becomes insoluble after exposure).

Continuing referring toFIGS.7A,7B, and8, a wafer edge treatment process118is performed on the photoresist layer116to form an annular photoresist pattern120. In the present disclosure, depending on the uneven height distribution of the spacer pattern114in the edge region102, the annular photoresist pattern120may selectively cover the spacer pattern114located in at least one of the first edge region102A, the second edge region102B, and the third edge region102C, and expose the spacer pattern114located in the central region104. In some embodiments, the annular photoresist pattern120covers the spacer pattern114with a relatively low height in the edge region102to reduce damage to the edge region102from subsequent etching processes. In some embodiments, the annular photoresist pattern120is formed on only one of the first edge region102A, the second edge region102B, and the third edge region102C. In other embodiments, the annular photoresist pattern120is formed on two adjacent ones or two non-adjacent ones of the first edge region102A, the second edge region102B, and the third edge region102C. In one embodiment, the photoresist layer116is a negative photoresist. In the present disclosure, the wafer edge treatment process118includes a wafer edge exposure (WEE) process or an edge bead removal (EBR). In one embodiment, the WEE process is performed on the photoresist layer116(negative photoresist) on the second edge region102B to form the annular photoresist pattern120covering only the second edge region102B after the developing process. The photoresist layer116(negative photoresist) on the central region104, the first edge region102A, and the third edge region102C is not exposed and is therefore removed after the developing process.

Referring toFIGS.8,9A, and9B, the developing process is performed and the annular photoresist pattern120covering the second edge region102B is remained, while the photoresist layers116on the first edge region102A, the third edge region102C, and the central region104are removed after the developing process.

It should be noted that in other embodiments, the photoresist layer116may also be a positive photoresist and may also form the annular photoresist pattern120covering only the second edge region102B, except for the embodiments using the positive photoresist performs a WEE process on the photoresist layer116in the first edge region102A and the third edge region102C to remain the photoresist layer116(positive photoresist) that has not been exposed on the second edge region102B after the developing process.

Next, referring toFIGS.8,10A, and10B, after forming the annular photoresist pattern120over the second edge region102B, the annular photoresist pattern120is used as an etching mask, transferring the exposed spacer pattern114to the hard mask layer106and the wafer100to form a plurality of trenches126in the wafer100. The annular photoresist pattern120may protect the spacer pattern114that is covered by the annular photoresist pattern120, so that the subsequent pattern transferring process does not affect the region covered by the annular photoresist pattern120. In one embodiment, a first etching process122is performed to transfer the spacer pattern114to the hard mask layer106. In one embodiment, the first etching process122uses the spacer pattern114and the annular photoresist pattern120as an etching mask to etch the hard mask layer106and transfer the exposed spacer pattern114to the hard mask layer106. In one embodiment, the first etching process122may include dry etching process, wet etching process, or a combination thereof.

Subsequently, referring toFIGS.11A and11B, the annular photoresist pattern120and the spacer pattern114are removed. In one embodiment, the hard mask layer106on the second edge region102B covered by the annular photoresist pattern120is not affected by the first etching process122, and thus the hard mask layer106on the second edge region102B remains in a mesa-shaped structure after performing the first etching process122. In one embodiment, the annular photoresist pattern120and the spacer pattern114may be removed by ashing process, wet etching process, dry etching process, or a combination thereof.

Then, referring toFIGS.12A and12B, using the patterned hard mask layer106as an etching mask, a second etching process124is performed to transfer the pattern of the spacer pattern114from the hard mask layer106to the wafer100. In one embodiment, the second etching process124may include dry etching process, wet etching process, or a combination thereof.

Next, referring toFIGS.13A and13B, a dielectric material layer (not shown) may be formed on the wafer100and filling into the trenches126. A planarization process is then performed on the dielectric material layer to expose the top surface of the hard mask layer106on the wafer100to form a trench isolation structure128. It should be noted that a dielectric liner (not shown) may be conformally deposited on the trenches126prior to the formation of the dielectric material layer that fills the trenches126. The dielectric liner may improve the interfacial properties between the substrate of the wafer100and the dielectric material layer, and may serve as an etching-stop layer for subsequent planarization process to be performed. In some embodiments, the material of the dielectric liner is silicon oxide, silicon oxynitride, or a combination thereof. The dielectric material layer may be formed by CVD, ALD, spin-on coating process, or other suitable process.

After the formation of the trench isolation structure128, other semiconductor processes may be performed to form various components, which are not described herein.

In the prior art, in the process of forming the trench isolation structure128, due to the properties of the lithography process and etching process, a spacer pattern114with an uneven distribution of heights is formed in the edge region102, which prevents the complete formation of the trenches126in the edge region102. For example, an excessively low height of the spacer pattern114in the edge region102may cause subsequent etching processes to over etch the edge region102, resulting in the formation of the trenches126with a top surface that is lower than the central region104or an excessively large opening at the top of the trenches126. That is, during the deposition process or the etching process for forming the subsequent component, defects such as fragments or particles may easily be generated and released into the central region104of the wafer100, thereby affecting the yield of the product. In the present disclosure, the annular photoresist pattern120over the selected edge region102is formed to cover the spacer pattern114that has an uneven height or is susceptible to over etching due to the etching properties. In this way, over etching of the edge region102by subsequent etching processes may be avoided, reducing the possibility of generating defects such as fragments or particles in the invalid wafer region, thereby avoiding the impact on the components in the central region and maintaining the performance of the product.

FIG.14illustrates a top view of the wafer100after forming the annular photoresist pattern120according to another embodiment of the present disclosure.FIG.15illustrates a cross-sectional view along the line A-A′ of the edge region102ofFIG.14. This embodiment is similar to the previous embodiments, except for after performing the WEE process on the photoresist layer116(e.g., negative photoresist) over the second edge region102B and the third edge region102C, the developing process is performed and the annular photoresist pattern120is remained to cover the second edge region102B and the third edge region102C. The photoresist layer116on the first edge region102A and the central region104is removed after the developing process.

FIG.16illustrates a top view of the wafer100after forming the annular photoresist pattern120according to yet another embodiment of the present disclosure.FIG.17illustrates a cross-sectional view along the line A-A′ of the edge region102ofFIG.16. This embodiment is similar to the previous embodiments, except for after performing the WEE process on the photoresist layer116(e.g., negative photoresist) over the first edge region102A and the third edge region102C, the developing process is performed and the annular photoresist pattern120is remained to cover the first edge region102A and the third edge region102C. The photoresist layer116on the second edge region102B and the central region104is removed after the developing process.

FIGS.18,19,20, and21illustrate cross-sectional views along the line A-A′ of the edge region102ofFIG.1according to further embodiments of the present disclosure. This embodiment is similar to the previous embodiments, except for during the formation of the patterned mandrel108(e.g., the processes described inFIGS.3A and3B), another edge treatment process130is additionally performed on the edge region102in order to avoid the formation of the spacer pattern114in the edge region102. Referring toFIG.18, similar to the first embodiment described above, in this embodiment, after the hard mask layer106is formed, a mandrel layer132is formed on the hard mask layer106using, for example, a spin-on coating process. Subsequently, another photoresist layer134is formed on the mandrel layer132. In this embodiment, the photoresist layer134is a positive photoresist.

In this embodiment, a wafer edge treatment process130(e.g., a WEE process or an EBR process) is performed on the photoresist layer134over the third edge region102C to remove the photoresist layer134located over the third edge region102C, as shown inFIG.19. Next, the remaining photoresist layer134is patterned to form a mandrel photoresist pattern136on the mandrel layer132. Referring toFIG.20, the mandrel photoresist pattern136is transferred to the mandrel layer132by an etching process to form the patterned mandrel108. In this embodiment, the patterned mandrel108is formed only over the first edge region102A, the second edge region102B, and the central region104because the photoresist layer134over the third edge region102C is removed. Referring toFIG.21, the SADP process as described in the previous embodiments may be performed to form the spacer pattern114. In this embodiment, the spacer pattern114is similarly formed only over the first edge region102A, the second edge region102B, and the central region104. In this embodiment, after forming the spacer pattern114on the hard mask layer106, the process as described inFIGS.7A to13Aof the previous embodiment may be performed continuously. That is, to form the annular photoresist pattern120on the selected edge region102and further improve the defect problem of the trenches126of the edge region102, which will not be discussed herein.

It should be noted that although the above embodiments are shown with the formation of the trench isolation structure, the method of the present disclosure may also be applied to other processes that require the formation of a trench structure, such as an inline trench, a buried word line, a trench capacitor, and the like. Thus, although not shown in the figures, various components, such as doped regions, isolated regions, transistors, inline structures, etc., may also be formed on wafer100prior to the formation of the hard mask layer106.

In summary, the present disclosure may effectively improve the incomplete etching or over etching of the trenches formed in wafer edge and reduce the possibility of the formation of the defects such as fragments or particles in the edge region by using the SADP process with the formation of a ring-shaped photoresist pattern. Thus, the various embodiments described herein offer several advantages over the existing art. It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments, and other embodiments may offer different advantages.