Method and apparatus for detecting free page and a method and apparatus for decoding error correction code using the method and apparatus for detecting free page

A method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page are provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2008-0090490, filed on Sep. 12, 2008, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein.

BACKGROUND

The present disclosure relates to a method and apparatus for processing data in a memory device, and more particularly, to a method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page.

Generally, in a non-volatile memory device, a cell having a recorded ‘1’, as a default status can be changed to a cell having a recorded ‘0’ via a writing operation, but a cell having written ‘0’ cannot be changed to a cell having written ‘1’ via a writing operation. Accordingly, when data is written in a non-volatile memory device, a deleting operation is performed such that all bits in a block are reset, including the bits to write the data to have a recorded ‘1’. Areas that are simultaneously deleted via one deleting operation correspond to a block, and pages in a deleted block are called free pages.

Accordingly, a method of effectively determining whether a page read from a memory is a free page would be helpful for memory device operation.

SUMMARY

In accordance with an exemplary embodiment of the inventive concept a method of detecting a free page of memory is provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value.

The target codeword may be a codeword having all bits a logic value of 0.

Error correction code decoding may be performed when the amount of non-identical bits exceeds the initially set threshold value.

The amount of bits that are not identical may be reported as an amount of stuck bits when the page read from the memory is determined to be a free page.

In accordance with an exemplary embodiment of the inventive concept a method of detecting a free page is provided. Data read from a memory is inverted. The amount of bits of inverted data having a logic value of 1 in an initially set data size unit is detected. A page read from the memory is determined to be a free page when the amount of bits is equal to or less than an initially set threshold value.

Error correction code decoding may be stopped when the page read from the memory is determined to be a free page.

The amount of bits that have a logic value of 1 may be reported as an amount of stuck bits when the page read from the memory is a free page.

Error correction code decoding may be performed when the page read from the memory is not a free page.

In accordance with an exemplary embodiment of the inventive concept, a method of decoding an error correction code is provided. Data read from a memory is inverted. The number of bits of inverted data having a logic value of 1 in an initially set data size unit is detected and error detection on the inverted data is simultaneously performed on the inverted data based upon an error correction code; Error correction being performed according to the error correction code is stopped when a detected amount of bits that have a logic value of 1 is less than or equal to an initially set threshold value. Error correction according to the error correction code is performed when the amount of bits exceeds the initially set threshold value and an error is detected from the inverted data.

A determination may be made that a page read from the memory is a free page when the amount of bits is equal to or less than the initially set threshold value.

The amount of bits that have a logic value of 1 may be reported as an amount of stuck bits when the amount of bits is equal to or less than the initially set threshold value.

In accordance with an exemplary embodiment of the inventive concept a computer readable recording medium having recorded thereon a program may be provided that executes the above-described methods.

In accordance with an exemplary embodiment of the inventive concept an apparatus for detecting a free page includes an inverter that inverts data read from a memory, and a free page detector that detects an amount of bits having a logic value of 1 in an initially set data size unit from data output from the inverter, and that determines that a page read from the memory is a free page when the amount of bits is equal to or less than an initially set threshold value.

In accordance with an exemplary embodiment of the inventive concept an apparatus for decoding an error correction code is provided which includes a first inverter that inverts data read from a memory; a free page detector that detects an amount of bits having a logic value of 1 in an initially set data size unit from data output from the first inverter, and that generates a free page status signal when the amount of bits is equal to or less than an initially set threshold value, a data buffer that temporally stores the data read from the memory; a second inverter that inverts data read from the data buffer, and an error correction code decoder that detects an error based on an error correction code by inputting data output from the second inverter, that corrects a detected error and outputs a corrected error, and that, when the free page status signal is generated, stops detection and correction of the error.

In accordance with an exemplary embodiment of the inventive concept an apparatus for decoding an error correction code is provided which includes: a first inverter that inverts data read from a memory, a free page detector that detects an amount of bits having a logic value of 1 in an initially set data size unit from data output from the first inverter, and that generates a free page status signal when the amount of bits is less than or equal to an initially set threshold value, and an error correction code decoder that detects an error based on an error correction code by inputting data output from the first inverter, that stops correcting the error when the free page status signal is generated, and that corrects the error when the free page status signal is not generated.

In the exemplary embodiments the initially set data size may be set to the size of a codeword.

In the exemplary embodiments the error correction code decoding may be stopped when the page read from the memory is determined to be a free page.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

First, exemplary embodiments of a memory device in accordance with the inventive concept will be described.

As shown inFIG. 1, the memory device includes a memory110, an ECC encoding processor120, a free page detecting and ECC decoding processor130, and a controller140.

The memory110stores information and includes a non-volatile memory device. The memory110may be a flash memory.

In a flash memory as a non-volatile memory device, a cell having a written 1 as a default status can be converted into a cell having a written 0 via a writing operation, but a cell that has a written 0 cannot be converted into a cell having a written 1 via a writing operation. Accordingly, when data is to be written in the flash memory, all bits in a block including the bits to write the data are reset to have logic value of 1. A page where all bits are reset to have logic value of 1 is called a free page.

A free page of a flash memory can have an error bit generated via a writing operation on a related page, such as in a pair page of a multi level cell (MCL). A block of a free page having an error bit may be discarded by performing a run-time bad block on the block, but usable memory capacity decreases by doing so. An approach to address the error bit situation will be described in more detail below.

Due to physical characteristics of non-volatile memory, an error may be generated by the number of bits within a standard range while writing and reading data. Accordingly, the error may be corrected by using an ECC.

Accordingly, the ECC encoding processor120generates parity bits required while correcting an error with respect to received data DATA_IN, and outputs a codeword wherein the generated parity bits are added to the received data DATA_IN. The codeword output from the ECC encoding processor120is written in the memory110by a read/write control signal and an address signal generated according to a control command transmitted by the controller140.

When a control command directing a reading operation is received by the controller140, the controller140reads data from the memory110, and outputs the data to the free page detecting and ECC decoding processor130.

The free page detecting and ECC decoding processor130performs a function of determining whether the data read form the memory110is free page data, and a function of ECC decoding processing based on the result of the determination.

The free page detecting and ECC decoding processor130performs free page detection and ECC decoding as shown in a flowchart illustrated inFIG. 4.

A method of detecting a free page will now be described with reference toFIG. 4.

First, a conversion process of converting free page data into a predetermined codeword CW_test to be included as an element of an ECC field is set in operation S401. In other words, a process of converting free page data to be mapped to a codeword that can be error-correction processed in an ECC field is performed. For reference, a codeword having all bits having a logic value of 0 is included as an element of an ECC field. Accordingly, for example, to detect a free page, a conversion process of converting free page data having all bits having a logic value of 1 into a codeword having all bits having a logic value of 0 may be selected.

Then, data that is read from the memory110is converted by using the conversion process set in operation S401in operation S402. In other words, the data read from the memory110is converted into a codeword CW_trans by using a mapping process that converts free page data into a codeword CW_test included as an element of ECC field as the one including the predetermined codeword CW_test.

The codeword CW_trans converted in operation S402and the codeword CW_test set in operation S401are compared bit by bit in operation S403.

Based on the result of operation S403, a number Total_Bit_diff, that is, the total number of bits that are not identical is detected in operation S404.

Then, it is determined whether the number Total_Bit_diff detected in operation S404is equal to or less than a threshold value TH in operation S405. Here, the threshold value TH is an initially set value, and is set within an error correctable range of the ECC decoder according to an exemplary embodiment of the inventive concept.

When it is determined that the number Total_Bit_diff is less than or equal to the threshold value TH in operation S405, a page read from the memory110is determined as a free page and ECC decoding is stopped respectively in operations S406and S407.

When it is determined that the number Total_Bit_diff exceeds the threshold value TH in operation S405, normal ECC decoding is performed in operation S408.

As such, when the number of error bits in a free page is within an allowable range, the page read from the memory110is determined to be a free page, and when the page read from the memory110is determined to be a free page, ECC decoding is not required to be performed on free page data, and thus the ECC decoding is stopped.

When the conversion process of converting free page data having all bits having a logic value of 1 into a codeword having all bits having a logic value of 0 is used to detect a free page, a detailed structure of the free page detecting and ECC decoding processor130may be as shown inFIGS. 2 and 3. For reference, the free page detecting and ECC decoding processor130is also referred to as an apparatus for decoding ECC.

As shown inFIG. 2, an apparatus for decoding ECC according to an exemplary embodiment of the inventive concept includes a plurality of inverters IN1, IN2, a free page detector210, a data buffer220, and an ECC decoder230.

The inverter IN1inverts data DATA_READ read from the memory110, and then outputs the inverted data DATA_READ to the free page detector210.

The free page detector210detects the number of bits having a logic value of 1 in an initially set data size unit from the data output from the inverter IN1, and generates a free page status signal FP status when the detected number of the bits having a logic value of 1 is equal to or less than an initially set threshold value TH.

The data buffer220temporarily stores the data DATA_READ read from the memory110, and sequentially outputs the stored data after detecting a free page.

The inverter IN2inverts the data output from the data buffer220, and outputs the inverted data to the ECC decoder230.

The ECC decoder230receives the data output from the inverter IN2, detects an error in the received data based on an ECC, corrects the detected error and outputs the corrected error, and stops detecting and correcting an error when a free page status signal FP status is generated.

In more detail, the free page detector210and the ECC decoder230respectively detect a free page and perform ECC decoding based on the result of the detection, according to a method illustrated inFIG. 5. Operations of detecting a free page and performing ECC decoding will now be described with reference toFIG. 5.

First, a number Total_Bit_1, that is, a value stored in a register installed in the free page detector210, is reset to 0 in operation S501.

Then, the free page detector210reads an inverted decoder input in operation S502. The inverted decoder input corresponds to data output from the inverter IN1.

The number of bits having a logic value of 1 is counted from the inverted decoder input transmitted to the apparatus for decoding ECC for one cycle, and then outputs the counted number as a number Cur_Bit_1in operation S503.FIG. 7is a diagram illustrating a logic circuit for counting the number of bits having a logic value of 1 from the inverted decoder input when data to be processed by the ECC decoder230in each cycle is 8 bits.

As illustrated inFIG. 7, the number Cur_Bit_1of bits having a logic value of 1 from the inverted decoder input may be detected for one cycle by combining 4 full adders FA1through FA4and 3 half adders HA1through HA3. When data to be processed each cycle exceeds 8 bits, a logic circuit may be designed by using a plurality of the logic circuits ofFIG. 7and a binary adder. When the data to be processed is less than 8 bits, unused bits may be set to have a logic value of 0.

Then, the number Total_Bit_1is updated and stored by adding the number Total_Bit_1and the number Cur_Bit_1of operation S503in operation S504.

After operation S504, it is determined whether inputting data having an initially set unit data size to the apparatus is done in operation S505. Here, the initially set unit data size may be the size of a codeword.

When it is determined that the inputting of the data having the initially set unit data size is not done in operation S505, operation S502is performed for a next cycle.

When it is determined that the inputting of the data having the initially set unit data size is done in operation S505, the stored number Total_Bit_1is compared to a threshold value TH in operation S506.

When it is determined that the number Total_Bit_1is equal to or less than the threshold value TH, a free page flag is set to having a logic value of 1 to determine that a free page status is detected in operation S507.

After setting the free page flag to 1, the value of Total_Bit_1is reported as the number of stuck bits in operation S508. The stuck bits are bits having a hard error in a free page.

Then, ECC decoding is stopped in operation S509. In other words, when the free page flag is set to 1, the ECC decoder230stops detecting and correcting an error.

When it is determined that the number Total_Bit_1exceeds the threshold value TH, the free page flag is set to have logic value of 0 to determine that the free page status is not detected in operation S510.

When the free page flag is set to 0, the ECC decoder230performs normal error detection and correction in operation S511.

According to the method ofFIG. 5, ECC decoding is held back while determining a free page status, and when the free page status is determined, the ECC decoding is stopped, and when the free page status is not determined, the ECC decoding is normally performed.

FIG. 3is a diagram of an apparatus for decoding an ECC, according to an exemplary embodiment of the inventive concept. The apparatus illustrated inFIG. 2is performs ECC decoding after detecting a free page, whereas the apparatus illustrated inFIG. 3simultaneously detects a free page and performs ECC decoding.

Referring toFIG. 3, the apparatus includes an inverter IN3, a free page detector310, and an ECC decoder330.

The inverter IN3inverts data DATA_READ read from the memory110, and simultaneously outputs the inverted data to the free page detector310and the ECC decoder330.

The free page detector310detects the number of bits having a logic value of 1 in an initially set data size unit from the data output from the IN3, and generates a free page status signal FP Status when the number of the bits is equal to or less than an initially set threshold value TH.

The ECC decoder330receives the data output from the inverter IN3, detects an error in the received data based on an ECC, stops error correction when a free page status signal FP Status is generated, and normally performs error correction when a free page status signal FP Status is not generated.

In other words, the ECC decoder330detects an error and the free page detector310detects a free page, simultaneously. When the free page detector310determines a free page, the ECC decoder330stops the error correction. Also, when the free page detector310does not determine a free page, the ECC decoder330normally performs the error correction.

A method of detecting a free page and performing ECC decoding according to the structure ofFIG. 3will now be described with reference toFIG. 6.

First, data DATA_READ that is read from the memory110and input to the apparatus is inverted in operation S601.

Then, the number of bits having a logic value of 1 included in a unit data size is counted from the inverted data, and an ECC error is simultaneously detected from the inverted data in operation S602. Here, the unit data size may be the size of a codeword.

After counting the number of the bits having a logic value of 1 and detecting an ECC error, it is determined whether the number of the bits is equal to or less than a threshold value TH and whether the ECC error is detected in operation S603.

When it is determined that the number of the bits is equal to or less than the threshold value TH or that an ECC error is not detected in operation S603, error correction based on an ECC is stopped, and the number of the bits is reported as the number of stuck bits in operation S604.

When it is determined that the number of the bits exceeds the threshold value TH, and an ECC error is detected, ECC error correction is normally performed in operation S605.

Accordingly, a free page is detected and an ECC error is detected, simultaneously, and the ECC error correction is performed based on the result of detecting the free page and the ECC error.

The embodiments of the inventive concept can be implemented as a method, an apparatus, and a system. When the embodiments are implemented in software, its component elements are code segments that execute necessary operations. Programs or code segments can be stored in processor readable media. The processor readable medium can be any medium that can store or transmit data.