Power adjustment based on completion times in a parallel computing system

A method, apparatus, and program product optimize power consumption in a parallel computing system that includes a plurality of computing nodes by selectively throttling performance of selected nodes to effectively slow down the completion of quicker executing parts of a workload of the computing system when those parts are dependent upon or otherwise associated with the completion of other, slower executing parts of the same workload. Parts of the workload are executed on the computing nodes, including concurrently executing a first part on a first computing node and a second part on a second computing node. The first node is selectively throttled during execution of the first part to decrease power consumption of the first node and conform a completion time of for the first node in completing the first part of the workload with a completion time for the second node in completing the second part.

FIELD OF THE INVENTION

The present invention relates to computing systems, and more particularly throttling performance of computing nodes of a computing system of the type that includes a plurality of computing nodes.

BACKGROUND

Computing system technology has advanced at a remarkable pace recently, with each subsequent generation of computing system increasing in performance, functionality, and storage capacity, often at reduced cost. However, individual computing systems are still generally expensive and incapable of providing the raw computing power that is often required by modern requirements for computing power. One particular type of computing system architecture that generally fills this requirement is that of a parallel processing computing system. Each parallel processing computing system is often referred to as a “supercomputer.”

Generally, a parallel processing computing system comprises a plurality of computing nodes and is configured with a distributed application. Some parallel processing computing systems, which may also be referred to as massively parallel processing computing systems, may have hundreds or thousands of individual computing nodes, and provide supercomputer class performance. Each computing node is typically of modest computing power and generally includes one or more processing units, or computing cores. As such, each computing node may be a computing system configured with an operating system and distributed application. The distributed application provides work for each computing node and is operable to control the workload of the parallel processing computing system. Generally speaking, the distributed application provides the parallel processing computing system with a workload that can be divided into a plurality of tasks. Typically, each computing node, or each computing core, is configured to process one task and therefore process, or perform, a specific function. Thus, the parallel processing architecture enables the parallel processing computing system to receive a workload, then configure the computing nodes to cooperatively perform one or more tasks such that the workload supplied by the distributed application is processed.

Parallel processing computing systems have found application in numerous different computing scenarios, particularly those requiring high performance and fault tolerance. For instance, airlines rely on parallel processing to process customer information, forecast demand, and decide what fares to charge. The medical community uses parallel processing computing systems to analyze magnetic resonance images and to study models of bone implant systems. As such, parallel processing computing systems typically perform most efficiently on work that contains several computations that can be performed at once, as opposed to work that must be performed serially. The overall performance of the parallel processing computing system is increased because multiple computing cores can handle a larger number of tasks in parallel than could a single computing system. Other advantages of some parallel processing systems include their scalable nature, their modular nature, and their improved level of redundancy.

When processing a workload, computing nodes of a parallel processing computing system typically operate at their highest possible performance to process each task of the workload as fast as possible. These computing nodes typically consume a large amount of power as well as generate a large amount of heat. As such, large and complex air handling systems must be designed and installed to keep the room, or rooms, where a parallel processing computing system is installed at a set temperature. Conventional methods of reducing the consumed power and/or the generated heat have generally included limiting the power to the computing nodes such that they are forced to run at lower speeds or taking various nodes of the parallel processing computing system offline at various times to reduce the heat generated by the parallel processing computing system as a whole. However, both methods prevent parallel processing computing systems from operating at peak efficiency. Additionally, both methods typically increase the time required to process a workload, which is often an unacceptable solution in a modern business environment.

Consequently, there is a need to schedule parts of a workload of a parallel processing computing system in such a manner that reduces the amount of power consumed by computing nodes without reducing the overall processing capabilities of the parallel processing computing system.

SUMMARY OF THE INVENTION

Embodiments of the invention provide for a method, apparatus, and program product to address power consumption and heat generation issues that arise when scheduling parts of a workload across a parallel computing system. In particular, embodiments of the invention provide for selectively throttling performance of one or more computing nodes processing shorter running parts of a workload in order to decrease power consumption of the parallel computing system. Given the completion time of a multi-part workload is typically controlled by the longest running parts of the workload, for workloads where it is anticipated that the completion times of one or more parts of the workloads will be earlier than for other parts of the workloads, the performance of the computing nodes assigned to handle such earlier-completing parts of the workload may be selectively throttled to reduce the power consumption associated with processing those parts of the workload, and often with little or no effect on the completion time for the overall workload. Embodiments of the invention take advantage of the fact that certain computing nodes that process shorter running parts of a workload may, without throttling, complete their respective parts well prior to the completion of other parts of the workload. Thus, by throttling performance of such computing nodes, power consumption is lowered, while the completion times of the shorter running parts are delayed to conform more closely with the completion times of other parts of the workload.

In one embodiment consistent with aspects of the invention, the consumption of power is reduced by executing a plurality of parts of the workload on a plurality of computing nodes in the parallel computing system, including concurrently executing a first part of the workload on a first computing node and a second part of the workload on a second computing node. The performance of the first computing node is selectively throttled during the execution of the first part of the workload to conform a completion time for the first computing node in completing the first part of the workload with a completion time for the second computing node in completing the second part of the workload, thus decreasing power consumption of the first computing node.

In that embodiment, a first node completion time and a second node completion time may be generated. Each node completion time respectively indicates an estimated completion time for the first or second computing node to complete the first or second part of the workload at full performance. The first and second node completion times are compared, and in response to this comparison, the first computing node is selectively throttled to decrease execution of the first part of the workload to consume a portion of time that would otherwise exist between the first and second node completion times.

In some embodiments, the throttled performance of the first computing node may be overridden during execution of the first part of the workload to increase power consumption of the first computing node when there is work to be processed on the first computing node after completion of the first part of the workload. In other embodiments, the throttled performance of the first computing node may be overridden during execution of the first part of the workload to increase power consumption of the first computing node in response to determining that the first part of the workload will not be completed by the completion time for the second computing node in completing the second part of the workload.

These and other advantages will be apparent in light of the following figures, detailed description, and illustrative examples.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention include a method, apparatus, and program product to address power consumption issues that arise when processing a workload across computing nodes of a parallel processing computing system.

Parallel processing computing systems, such as the BlueGene/L system created by International Business Machines, often include a cellular node architecture. As discussed below in detail, the BlueGene/L system is built from blocks of node midplanes that may be connected through several inter- and intra-midplane networks. The system may be constructed incrementally, with midplane cells being added to build the larger, final system.

The primary point to point message passing network for BlueGene/L is a three dimensional torus network, where every node is connected to six other nodes in a mesh, forming a cube of (x,y,z) nodes. For example, a 512 node midplane torus consists of an 8×8×8 node arrangement. “Torus” implies that the nodes on the face of the cube wrap around to connect to nodes on the opposite face. This torus network can be extended in all three directions by connecting the faces of these logical cubes via link chips, which are essentially switches between midplanes. The link chips are connected via cables, while the internal torus is connected via circuitry within the midplane. Each node is configured with one or more computing cores.

The parallel processing computing system is configured to receive a workload and divide the workload into parts, or tasks, that are operable to be executed, or processed, by the nodes of the system. As such, the parallel processing computing system is configured to perform several computations at once. Each node may execute one task, or each computing core may execute one task, depending on the configuration of the parallel processing computing system. In one embodiment consistent with the invention to decrease power consumption of the parallel processing computing system, there is provided a method that throttles the performance of nodes during execution of parts of the workload. In one embodiment of the invention, a plurality of parts of the workload are respectively executed on a plurality of computing nodes in the parallel processing computing system. As such, a first part of the workload is executed on a first computing node from among the plurality of computing nodes concurrently with a second part of the workload executed on a second computing node from among the plurality of computing nodes.

The performance of the first computing node while executing the first part of the workload is selectively throttled to conform a completion time for the first computing node in completing the first part of the workload with a completion time for the second computing node in completing the second part of the workload. In particular, embodiments of the invention “conform” completion times of the first and second computing node by reducing performance of the first node such that the first computing node completes execution of the first part (or multiple parts assigned to the first computing node) closer to the completion time of the second computing node executing the second part than it would otherwise if the first computing node were run at full performance. As such, conforming the completion time may include consuming a portion of time that would otherwise be wasted between completing the first part at full performance and then completing the second part at full performance. When completion times are conformed, the completion time of the throttled computing node may be equal to that of the non-throttled computing node, or may still be earlier, albeit closer in time. In addition, in some embodiments the completion time of the throttled computing node may ultimately be later in time than that of the non-throttled computing node, but closer in absolute terms than if the throttled computing node operated at full performance.

Additionally, embodiments of the invention may selectively override performance throttling in response to another part of the workload, or a part of another workload, being scheduled on the first node, while attempting to conform the completion time of the first and third parts to the completion time of the second part. Embodiments of the invention may also selectively override performance throttling in response to determining that a first part of the workload that was previously throttled will not complete by the completion time of the second part. Selectively throttling a node may include running that node as slow as possible such that the node operates only when it needs to. Advantageously, conforming the completion times of computing nodes reduces power consumption, often with little or no effect on the overall completion time of the workload or overall system performance.

Hardware and Software Environment

Turning to the drawings, wherein like numbers denote like parts throughout several views,FIG. 1is a diagrammatic illustration showing a parallel processing computing system (system)10consistent with one embodiment of the invention. In particular, the system10may have an architecture consistent with a BlueGene® computer architecture, as developed by International Business Machines, Inc. (IBM) of Armonk, N.Y. For example, and in other embodiments, the architecture of the system10may be consistent with a BlueGene/L architecture, a BlueGene/C architecture, a BlueGene/P architecture, a BlueGene/Q architecture, another parallel processing system architecture, or combinations thereof. Therefore, it will be appreciated by one having ordinary skill in the art that the system10is representative of other parallel processing systems.

The system10may include a plurality of processing nodes (hereinafter, “nodes”). The nodes may include a plurality of computing nodes (“compute nodes”)12and a plurality of input/output nodes (“I/O nodes”)14. The compute nodes12may be arranged in a regular array or matrix and collectively perform the bulk of the work performed by the system10. Each compute node12includes one or more computing cores and a memory from which to store and execute tasks. The compute nodes12communicate with each other through a torus network or a tree network, as described more fully herein. A fully configured BlueGene/L system, in one specific embodiment, includes about 65,536 compute nodes12operable to process tasks and about 1,024 I/O nodes14operable to maintain an interface between the compute nodes12and other system components.

The I/O nodes14maintain an interface between the compute nodes12and front end nodes16, external resource servers18, service nodes20, and network22. The I/O nodes14may interface with the front end nodes16, external resource servers18, and service nodes20by way of the network22, which in a specific embodiment may be a gigabit Ethernet network. The I/O nodes14are operable to maintain communication for a group of compute nodes12from among the plurality of compute nodes12. In a specific embodiment, each I/O node14maintains communications for up to sixty-four compute nodes12. In this manner, each I/O node14provides access to resources of the system10and processes, programs, tasks, or data in other systems for a specific number of compute nodes12. The I/O nodes14may also be operable to perform process authentication and authorization, job accounting, debugging, troubleshooting, booting, and configurations. Thus, tasks for the compute nodes12are simplified and additional burdens on each compute node12that would present themselves by interfacing with vast numbers of I/O nodes14and other system components are avoided.

The front end nodes16may store compilers, linkers, loaders, and other programs to interact with the system10. The front end nodes16may be accessed by a user, who may submit one or more programs for compiling, tasks for execution, execution contexts, workloads, part of a workload, or jobs to the service nodes20. As such, the front end nodes16may be configured with user interfaces, such as user input devices and a display (neither shown). In alternate embodiments, the front end nodes16may interface with one or more workstations or other computing systems (not shown). The front end nodes16may each include a collection of processor and memory that performs certain auxiliary functions which, for reasons of efficiency or otherwise, are best performed outside compute nodes12, I/O nodes14, or service nodes20. For example, interactive data input, software code editing, software code compiling, and/or other user interface functions may be handled by front end nodes16.

The service nodes20may include databases and administrative tools for the system10. The databases may maintain state information for the computing nodes12, including the current performance throttling of each computing node12, while the administrative tools may control the scheduling and loading of programs, tasks, data, and jobs onto the compute nodes12, and in particular onto each computing core. As such, the service nodes20may, in some embodiments, gather a subset of compute nodes12from the plurality of compute nodes12(i.e., a “block” of two or more compute nodes12) and dispatch at least one task, job, application, execution context, or program to the block of compute nodes12for execution. Hereinafter, the at least one task, job, application, part of a workload, execution context, or program will be referred to as a “task” for the sake of brevity. A task may be communicated across the network22and through the I/O nodes14to a compute node12to be processed by a computing core of the compute node12. It will be appreciated by one having ordinary skill in the art that the functionality of the front end nodes16and service nodes20may be combined to form a control subsystem operable to manage, control, and schedule tasks for the compute nodes12.

Front end nodes16and service nodes20may each include of a block of compute nodes12and at least one I/O node14of the system10. In this way, front end nodes16and service nodes20may be internally connected to the compute nodes12and I/O nodes16through one or more of the plurality of networks described hereinafter. Alternately, front end nodes16and service nodes20may each include of a block of compute nodes12and at least one I/O node14separate from the system10(i.e., “stand-alone” nodes). The external resource servers18may be servers that provide interfaces to various data storage devices, such as, for example, disk drives19, or other I/O devices, resources, or components that may be accessed to complete a task.

In a typical embodiment, the compute nodes12are configured with a plurality of workloads24,26, and28. Each workload24,26, or28is generally split into individual tasks, each task being performed by one or more compute nodes12. As shown inFIG. 1, the first workload24is processed by “x” nodes, while the second workload26and third workload28are processed by “y” nodes and “z” nodes, respectively.

FIG. 2is a diagrammatic illustration30showing components32,42,44,46, and48of the system10consistent with embodiments of the invention. The system10comprises a highly scalable, cell-like architecture that can be replicated in a regular pattern as the system is scaled up.

The system10fundamentally includes the plurality of nodes, a node being shown generally at32(i.e., node32may be a compute node12, an I/O node14, a front end node16, or a service node20). Each node32typically comprises one or more computing cores34, an Ethernet adapter36, a torus network adapter37, a collective network adapter38, and a memory40, which may be a local and/or remote cache memory. About two nodes32may be mounted onto a card42. About seventeen cards42(i.e., in one specific embodiment, sixteen compute node12cards and one I/O node14card) are typically placed on a node board44. About sixteen node boards44comprise a midplane, or cell45, two of which may be positioned inside a cabinet46for a total of up to about one-thousand and twenty-four compute nodes12and up to about sixty-four I/O nodes14per cabinet46, or about five-hundred and twelve compute nodes12and about thirty-two I/O nodes14per cell25. The system10may include up to about sixty-four cabinets46as shown at48, and, thus, in some embodiments, over sixty-nine thousand nodes. In alternate implementations of the system10consistent with embodiments of the invention, there may be more or fewer cabinets46, cells45, boards44, cards42, and/or nodes34.

FIG. 3is a block diagram showing the hardware and software components of one embodiment of the node32of the system10ofFIG. 1andFIG. 2. Each node32includes one or more computing cores34that communicate with a memory40by way of a bus as at50managed by a bus adapter52. Each computing core34may include one or more processors, controllers, field programmable gate arrays, or application specific integrated circuit, while memory40may include random access memory devices (including synchronous dynamic random access memory), cache memories, non-volatile memories, and read-only memories. For example, and in one specific embodiment, each computing core34may be a microprocessor, such as a PowerPC microprocessor as produced by IBM. For example, and in another specific embodiment, each computing core34may be a multi-element architecture microprocessor that includes one general purpose processing element and a plurality of synergistic processing elements, such as a Cell Broadband Engine Architecture microprocessor as jointly developed by IBM, Sony Computer Entertainment of Tokyo, Japan, and Toshiba of Tokyo, Japan. As shown inFIG. 3, each node32includes two computing cores34. One having ordinary skill in the art will appreciate that each node32may include more or fewer computing cores34than those illustrated, and in one specific embodiment each node32includes four computing cores34.

Each node32is configured with an operating system54operable to execute an application56. The operating system54may be a simplified-function operating system that includes state data for maintaining the processing state(s) of the node32. In one specific embodiment, operating system54is operable to only support only one, or a few, tasks at a given time, as opposed to a multi-tasking operating system configured on a typical personal computing system. As such, operating system54may not, and advantageously does not, include certain functions normally associated with a multi-tasking operating system, including software, routines, components, or program code to support multi-tasking, various I/O devices, error diagnostics and recovery, etc. In one specific embodiment, the operating system54may include a simplified version of a Unix-like operating system, such as Linux. It will be appreciated by one having ordinary skill in the art that other operating systems may be used, and that it is not necessary that all nodes32employ the same operating system (i.e., the application56may be a “multi-platform” application operable to be installed across multiple and different operating systems or operating environments).

Application56is a copy of program code being executed by the node32, and may include a complete copy of program code being executed by the system10. Alternately, application56may be a subdivided portion of the program code being executed by the system10as a whole. As such, the application56may be a distributed application of the type that is operable to be configured across a plurality of nodes32(i.e., more than one node32) to process a workload25,26, or28. Application56, in one embodiment, is operable to configure one or more tasks for each computing core34on the node32upon which it is configured. Local copies of data for the application56, or data from the application56, may be reserved in some portion of memory40in a file cache (not shown). Memory40may also include an application stack (not shown) that includes data corresponding to the execution progress of a task by the application56.

Memory40may include a throttling module58configured to throttle the operations, clock speed, or overall processing speed of each computing node32and/or each computing core34of each computing node32. As such, each throttling module58is configured to decrease the power consumption of a node32by throttling that node's32performance as slow as possible while retaining the ability for that node32to conform its processing of its task by a required or desired completion time. The completion time, in a specific embodiment, is a specific range of time. For example, the completion time may be five minutes and three seconds, thus indicating that work should be completed in five minutes and three seconds. One having ordinary skill in the will appreciate that the completion time may be alternately defined without departing from the scope of the invention, and in one specific embodiment may be a specific time in the future. For example, and not intending to be limiting, an alternately defined completion time may be at 17:26:57. Thus, the node32attempts to conform its processing of its task by that alternately defined completion time.

In response to receiving a workload, a throttling module58may determine an estimated completion time for a workload (workload completion time) based on a number of factors, including historical data about a completion time of a previous workload processed by the system10. Additionally, the throttling module58may determine the workload completion time based on historical data about a previous workload completion time of parts of a workload across one or more nodes32and/or computing cores34, and this determination may further include a determination of the number of nodes32and/or computing cores34that were previously assigned to the workload and how many are currently assigned to the workload. Other factors that the throttling module58may use to determine the workload completion time may include the total data required to be processed to complete the workload, the total data required to be processed to complete a task or all the tasks of the workload, the time required to access a resource or resources by a node32to complete the workload and/or a task of the workload, and which of the nodes32and/or computing cores34are currently configured with tasks (those that are “busy”) and which are currently not configured with tasks (those that are “free”). In a specific embodiment, the workload completion time may correspond to the longest completion time that a node32of the system10may incur to complete a task of the workload.

In addition to determining the workload completion time, the throttling module58may be configured on each of the nodes32and determine a completion time for a task, or part, of a workload to be processed by that node32upon which it is configured. Thus, the throttling module58determines an estimated completion time for individual nodes32to complete a task (node completion time). The throttling module58may determine the node completion time based on a number of factors, including historical data about a previous node completion time of a previous task processed by that, or another, node32. Additionally, the throttling module58may determine the node completion time based on historical data that indicates the total data required to be processed to complete the task, the time required to access a resource or resources by that node32to complete the task, and whether that node32and/or computing core34is currently free. The determined workload completion time, and the determined node completion time, may be stored in a processing progress record59configured in the throttling module58.

Through a comparison of the workload completion time and the node completion time, and a subsequent determination of the throttling of the node32to conform the two times, individual nodes32of the system10may have their performance throttled to balance work processed by the system10, power consumption of the system10, and/or heat generated by the system10. For example, a node32may receive a task and a workload completion time. The throttling module58for that node32may determine a node completion time, determine the workload completion time, and determine a throttling of the computing nodes32sufficient to conform the node and workload completion times. All this data may be stored in the processing progress record59. As such, information from the processing progress record59, or the processing progress record59itself, may be communicated to nodes32, such as between one or more of the compute nodes12, I/O nodes14, front end nodes16, and service nodes20, to manage the throttling of the system10.

The computing cores34may communicate through the bus50to the bus adapter52. The bus adapter52maintains the integrity of data flow in the node32and manages the data communication of the computing cores34, network adapters36,37, and38, as well as memory40. The network adapters may include an Ethernet adapter36, a torus network adapter37, and a collective network adapter38. The Ethernet adapter36, torus network adapter37, and collective network adapter38interconnect each node32to provide multiple complimentary, high speed and low latency networks. These networks may include a private Ethernet network that provides access to any node32for configuration, booting, and/or diagnostics (i.e., through the Ethernet adapter36), as well as a three-dimensional torus network operable to provide peer-to-peer communication between the nodes32(i.e., through the torus network adapter37) and a collective network for collective messaging communication (i.e., through the collective network adapter38). Each node32may use part of one computing core34, or one or more computing cores34in their entirety, to manage the network connections and the network adapters36,37, and38of that node32.

One having ordinary skill in the art will appreciate that additional components, memory, communications adapters, network adapters, or interfaces may be provided for each node32without departing from the scope of the present invention. For example, and in a specific embodiment, each I/O node14may be further configured with additional adapters, such as another Ethernet adapter or other I/O hardware to communicate with the front end nodes16, external resource servers18, service nodes20, and/or network22. Additionally, in another specific embodiment, each I/O node14may be configured with an operating system54that includes additional I/O interface software or software that adds additional functionality, such as software that dedicates one or more computing cores34to I/O operations only. Furthermore, each I/O node14may be configured with additional components, such as a computing core34dedicated only to I/O operations and an additional external memory that provides the I/O node14additional resources to perform I/O tasks. In another specific embodiment, each node32may be further configured with an adapter to communicate to a JTAG master circuit, providing back-door access into the node32for testing and troubleshooting in a manner well known in the art.

The torus network adapter37provides each node32access to a point-to-point network configured as a three-dimensional torus where every node is connected to six other nodes in a mesh, forming a “cube” of (x,y,z) nodes. As such, each node32may communicate in one of six directions through the six bidirectional links shown coming from the torus network adapter37inFIG. 3.FIG. 4is a simplified block diagram showing the three-dimensional torus network60of a cell45of the system10ofFIG. 1andFIG. 2. As illustrated inFIG. 4and previously disclosed, each cell45may include an eight-by-eight matrix of five-hundred and twelve interconnected nodes32. Advantageously, each node32may be equally distant to its six neighbors, except for those on the “edges” or “faces” of the torus network60(i.e., the edges or faces of the three-dimensional matrix torus network60). Those nodes32on the edges or faces of the torus network60may communicate through communications links (i.e., wires, leads, network connections) that are “wrapped” around the network60.

Each node32includes a set of six node-to-node communications links. In the context of the present invention, and to illustrate communications in the torus network60, the cell45includes a node32awith the coordinates (7,0,0). This node32amay be a particular type of node32, such as a master compute node operable to control a subset of the compute nodes in the cell45. As illustrated, the node32amay communicate with any other node32in the torus network60by initially communicating to one of six “neighbor” nodes32b-glinked to the node32athrough direct inter-nodal communications paths (i.e., paths which do not have to traverse another compute node12). The coordinates of these neighbor nodes are (6,0,0) for node32b, (0,0,0) for node32c, (7,0,1) for node32d, (7,0,7) for compute node32e, (7,1,0) for compute node32f, and (7,7,0) for compute node32g. As shown inFIG. 4, the torus network60is “wrapped” at the edges. As such, for any given node32, it is possible to algorithmically determine the set of neighbors of that node32from the matrix structure and location of that node32in the torus network60.

It will be appreciated by one having skill in the art that the representative torus network60ofFIG. 4is merely illustrative, and that actual physical considerations may prevent the physical structure of the torus network60shown inFIG. 4. Moreover, a wide variety of interconnection types, network types, member types, etc., may be permitted to coexist with one another in an efficient and reliable manner in parallel computing system. As such, nodes32in a cell45may be arranged in a tree network, bus network, linear network, mesh network, style-7 network, or another suitable network as is well known in the art without departing from the scope of the invention. Individual nodes may thus not be physically located in close proximity with other nodes as is well known in the art (i.e., the individual nodes may be geographically separated from other nodes).

FIG. 5is a diagrammatic illustration of an alternate embodiment of a parallel processing computing system (“system”)62consistent with embodiments of the invention. In the illustrated embodiment ofFIG. 5, the nodes of the system62may include one or more computing systems66a-zand/or servers70. In this embodiment, there is a central administrators computer (“admin” computer)63connected to a network64. The admin computer63manages the processing of the system and dispatches workloads and/or tasks to the computing systems66a-zand/or servers70. A plurality of servers70may be configured in a plurality of server cabinets, shown at68a-z. Computing systems66a-zand servers70in cabinets68a-z, in specific embodiments, may be computers, computer systems, computing devices, servers, disk arrays, or programmable devices such as multi-user computers, single-user computers, handheld devices, networked devices (including computers in a cluster configuration), mobile phones, video game consoles (or other gaming systems), etc. As such, each of the computing systems66a-zand servers70may each include one or more processors coupled to memory, operating systems, and network interfaces. Thus, the system62ofFIG. 5may operate in much the same way to perform parallel processing as the parallel computing system10shown throughoutFIGS. 1-4. One having ordinary skill in the art will appreciate that the computing systems66a-zand servers70may perform substantially the same function as the nodes32of the system10. Each of the computing systems66a-zand servers70may be further configured with an application, throttling module, and processing progress record substantially similar to those shown inFIG. 3. Therefore, the system62ofFIG. 5may be used to throttle the processing performance of one or more of the computing systems66a-zand servers70consistent with embodiments of the invention.

WhileFIG. 1illustrates separate resource servers18and service nodes20, one having ordinary skill in the art will appreciate that the resource servers18may be service nodes20configured to maintain the resources of the system10. Similarly, whileFIG. 5illustrates a separate admin computer63from the computing systems66a-zand servers70, one having ordinary skill in the art will appreciate that the admin computer63may be incorporated into one or more of the computing systems66a-zand/or servers70. Additionally, while the node32ofFIG. 3comprises a specific hardware implementation having particular application within the context of an embodiment consistent with the invention, it is not intended to limit the scope of the invention. It should consequently be appreciated that the invention may be implemented in other computers and data processing systems, e.g., in single or multi-user computers such as workstations, desktop computers, portable computers, server computers and the like, or in other programmable electronic devices (e.g., incorporating embedded controllers and the like) operating as, or within, a parallel processing computing system.

Those skilled in the art will recognize that the environments illustrated inFIGS. 1-5are not intended to limit the present invention. In particular, while the nodes ofFIGS. 1-4are shown connected in a modular fashion, any combination of local area networks (LAN's), wide area networks (WAN's) and/or other networking topologies known in the art may alternatively be used to network computing processors comprising nodes. Indeed, those skilled in the art will recognize that other alternative hardware and/or software environments may be used without departing from the scope of the invention

For the sake of brevity, further discussion of embodiments consistent with the invention will be discussed in relation to the hardware and software implementation illustrated inFIGS. 1-4, and particularly in relation to nodes32of the system10. One having ordinary skill in the art will appreciate that the following descriptions are thus equally applicable to the computing cores34of each of the nodes32of the system10ofFIGS. 1-4, as well as the computing systems66a-zand servers70and processors therein of the system62ofFIG. 5. Thus, the discussion hereinafter will focus on the specific routines utilized in the above-described system10to throttle processing performance in one or more nodes32. The routines executed to implement the embodiments of the invention, whether implemented as part of an operating system or a specific application, component, program, object, module or sequence of instructions executed by one or more nodes32, computing cores34, or other processors, will be referred to herein as “computer program code,” or simply “program code.” However, the routines executed by the nodes32, computing cores34, or other processors consistent with processing a portion of a workload (i.e., normal processing of an execution context, task, application56, program, routine, process, object, etc), whether implemented as part of the operating system54, application56, component, program, object, module, or sequence of instructions executed by the node32will be referred to herein as “task.” The computer program code typically comprises one or more instructions that are resident at various times in various memory and storage devices in the system10, and that, when read and executed by one or more nodal or other processors of the system10, cause that system to perform the steps necessary to execute steps, elements, and/or blocks embodying the various aspects of the invention.

Moreover, while the invention has and hereinafter will be described in the context of fully functioning computers and computer systems, those skilled in the art will appreciate that the various embodiments of the invention are capable of being distributed as a program product in a variety of forms, and that the invention applies equally regardless of the particular type of computer readable signal bearing media used to actually carry out the distribution. Examples of computer readable signal bearing media include but are not limited to recordable type media such as volatile and nonvolatile memory devices, floppy and other removable disks, hard disk drives, optical disks (e.g., CD-ROM's, DVD's, etc.), among others, and transmission type media such as digital and analog communication links.

Performance Throttling

FIG. 6illustrates a flowchart for program code having blocks executable by the system10ofFIGS. 1-4to throttle the performance of at least one node32of the system10, decreasing the power consumption of that node32, and therefore the system10, consistent with embodiments of the invention. In block102, the system10receives a workload24,26,28(hereinafter, “workload”). The workload may be received at the front end nodes16, across the network22from an external source, as part of a programmed routine, or in any other manner generally known in the art. In block104, the program code estimates a workload completion time and stores it. As previously disclosed, the workload completion time may be determined with reference to historical data about previous workloads configured across a node32or nodes32, historical data about the number of nodes32previously configured to process workloads, the number of tasks in the workload, the time required to access a resource or resources to complete a task or tasks of the workload, the amount of data in the workload, the number of free nodes32, and/or the number of busy nodes32, including the number of busy nodes32that are near completion of their current tasks. In block106, the program code selects a node32or nodes32to process the workload. Advantageously, the program code attempts to select free nodes32to perform tasks of the workload.

In block108, the program code may divide the workload into a plurality of parts, or tasks. For example, and in one specific embodiment, the workload may be divided into five tasks that may be executed at five nodes32, or nodes32that (collectively) have five cores34operable to execute the five tasks. However, in some embodiments, the workload may not be divided (e.g., when the workload is one task that cannot be subdivided) and may be sent to one node32. In block110, each node32selected to process a task of the workload in block106processes, or otherwise receives, the task and the workload completion time. In one embodiment, in response to receiving a task, each of the selected nodes32generates a processing progress record59and stores the workload completion time in the processing progress record59in block110. In an alternate embodiment, the program code generates a processing progress record59that includes the workload completion time in block104, and that processing progress record59is subsequently received by the nodes32in block110.

In block112, the nodes32determine their performance throttling. In block112, in response to receiving a task, the throttling module58of the node32analyzes the task or tasks that node32has received and estimates a node completion time that indicates a time for that node32to complete the task or tasks with no performance throttling. As such, the throttling module58on the node32may determine the node completion time with reference to historical data about previous tasks similar to the current task, historical data about the time required to access a resource or resources to complete the task, the amount of data in the task, and/or whether the node32is currently configured with another task. The throttling module58then compares the node completion time to the workload completion time. When the workload completion time in the processing progress record is later, or greater, than the node completion time, the throttling module58determines a performance throttling for the node32to conform the node completion time to the workload completion time such that the node32is run as slow as possible while still completing the task by the required and/or desired workload completion time. In this manner, conforming the completion time may include consuming a portion of time that would otherwise be wasted between completing the first part at full performance and then completing the second part at full performance. As such, the throttling module58, in one embodiment, may lower the processing speed of the node32and/or the core34of the node32, thus selectively throttling the performance of the node32and/or core34. In an alternate embodiment, the throttling module58may configure the node32to access data from a resource of the system10that has a high latency (i.e., the data on that resource is associated with a large time delay to access, process, and/or retrieve that data), thus selectively throttling the performance of the node32. The performance throttling operates to reduce the power consumption of the node32. When the node completion time is later, or greater, than the workload completion time, the throttling module58does not selectively throttle performance of the node32and/or core34. As such, the throttling module58may execute the task with no performance throttling. Additionally, the program code may attempt to reschedule the task, or execute the task on the node32and attempt to conform the node completion time as closely as possible to the workload completion time.

In block112, the throttling module58may update the processing progress record59of the node32with the performance throttling for that node32and the node completion time. As such, the throttling module58may store the workload completion time, node completion time, performance throttling, and/or lack of performance throttling for a node32in the processing progress record59.

In block114, the program code initiates the execution of the workload by each node32configured with a task of the workload. Additionally in block114, the processing progress record59for each node32or the data related to the node completion time, performance throttling, and/or lack of performance throttling for each node configured with a task of the workload is transmitted to the nodes32that received the workload (hereinafter, “management nodes”), which may be the front end nodes16or service nodes20. In this way, the throttling of the nodes32may be monitored and/or managed at one location.

In block116, the program code analyzes the throttling and/or node completion time for each node32that received a task of the workload to determine whether to adjust the workload completion time of any of those nodes32. The program code may adjust the workload completion time of one or more nodes32, or even all the nodes32, in response to determining that the node completion time of one or more nodes32is greater than the workload completion time, that the one or more nodes32will complete their task too soon, or that one or more nodes32cannot complete a task of the workload with the current level of performance throttling by the workload completion time. The latter condition may occur after processing of a task has begun and be in response to a changed condition of a node32indicating that that node32cannot complete the task of the workload with the current level of performance throttling by the completion time. Alternately, the latter condition may occur in response to another changed condition of the system10(for example, such as one or more node32experiencing a failure, a resource attempting to be accessed by that node experiencing a failure, or a network of the system10experiencing a failure). In some embodiments, the program code may be configured to allow one or more nodes32to “miss” the workload completion time when the node completion time is later than the workload completion time. In those embodiments, the task on the nodes32that have a later node completion time than the workload completion time may be a less important, the task may be a execution intensive task that cannot be completed by the workload completion time, other system10processes may be performed while waiting for “late” nodes32, or the program code may determine that the later node completion time is not critical.

When the program code determines that the performance throttling of one or more nodes32should be adjusted, the program code re-estimates the workload completion time for the one or more nodes32in block118. In block120, the one or more nodes32receive the revised workload completion time and revise their processing progress records to include the revised workload completion. As such, the one or more nodes32may re-estimate their node completion times and revise their performance throttling in block122. In an alternate embodiment, the management nodes re-estimate the performance throttling of each node32and communicate the re-estimated workload completion time and revised performance throttling to each node32in block120. After block122, the program code may proceed back to block116.

When the program code determines not to adjust performance throttling, the program code determines whether to override the performance throttling for one or more nodes32in block124. The program code may override the performance throttling of a busy node32in response to determining that there is work, such as another task, waiting to be executed by that busy node32in block124, or the program code may override the performance throttling of the one or more nodes in response to determining that those one or more nodes32will not complete their task by the workload completion time. When the program code determines that overriding the performance throttling is appropriate, the program code clears the performance throttling for those nodes32(i.e., allows the nodes to use one-hundred percent of their processing capabilities) in block126. In block120, the processing progress records59may be revised and the nodes32that are overridden may revise their performance throttling (e.g., the nodes32that are overridden may determine that they have no performance throttling) in block122.

When the program code makes a determination not to override the throttling performance of the one or more nodes32, the program code determines whether the workload has completed in block128. When the workload is complete, the program code frees each task on nodes32that are finished processing tasks and do not have tasks waiting for execution, then returns the results of the workload to the management nodes in block130. As such, the program code may throttle each free node32to reduce the power consumed by those nodes32. When the workload has not completed, the program code returns to block116to continue processing the workload.

Further details and embodiments of the present invention will be described by way of the following examples.

No Performance Throttling

By way of example, the system10may include at least five cores34and receive a first and second workload. The first workload (workload “A”) may be divided into six tasks (illustrated as tasks A1-A6), while the second workload (workload “B”) may not be divided (e.g., workload B is a single task, illustrated as task B1).FIG. 7is a diagrammatic illustration140of how tasks A1-A6and task B1may be scheduled and executed across the five cores (labeled cores1-5) consistent with conventional parallel processing systems. As illustrated inFIG. 7, as well asFIG. 8andFIG. 9, the x-axis of each illustration diagrammatically illustrates time. As such, workload A is divided into six tasks (e.g., A1-A6) and scheduled across the five cores34, each core34operating to execute each task as quickly as possible. Workload B, which is received after workload A, is scheduled shortly after workload A. As shown inFIG. 7, workload A is time-limited by task A1, resulting in a significant wasted time after tasks A2, A3, and A5. Cores2,3, and4produce excess heat and consume excess power during execution of tasks A2, A3, and the combination of tasks A4and A5, respectively.

Performance Throttling

FIG. 8is a diagrammatic illustration150of how tasks A1-A6and task B1might be scheduled, and the performance of cores1-5throttled, consistent with embodiments of the invention. As shown inFIG. 8, the original workload completion time is indicated by a dashed line and may represent when the last of the tasks of the workload A are expected to be completed. This dashed line is also shown inFIG. 7, for illustrative purposes. Returning toFIG. 8, task A1is still the time limiting task. However, other cores34are throttled to conform the completion times of those cores34to the completion time of the core34executing task A1(i.e., core1). As such, task A2completes at substantially the same time as task A1, while task A3may complete at a time somewhat before the workload completion time for workload A. The combination of tasks A4and A5may complete at a time somewhat later than the workload completion time for workload A, which, though later, still conforms better with the workload completion time. As such, the completion times for task A3and the combination of tasks A4and A5are shown to conform with those of tasks A1and A2. It will be appreciated that conforming completion time of task A3and the combination of tasks A3and A4includes consuming a portion of time that would otherwise be wasted between completing tasks A3and the combination of tasks A4and A5at full performance. As shown inFIG. 8, task A6is completed at full performance in light of task B1. Thus, performance throttling may be overridden in response to a busy core (i.e., core5) being further configured to process a task (i.e., task B1) once freed. In this manner, the illustration150ofFIG. 8illustrates performance throttling cores of a parallel processing computing system consistent with embodiments of the invention to reduce the power consumption of that parallel processing computing system.

Levels of Performance Throttling

FIG. 9is a diagrammatic illustration160that shows the level of performance throttling for the cores34executed tasks A1-A6of workload A and task B1of workload B illustrated inFIG. 8. Again, the original workload completion time is indicated by a dashed line and may represent when the last of the tasks of the workload A are expected to be completed inFIG. 9. As illustrated inFIG. 9, core1operates at 100% of its full performance to execute task A1and complete that task by the workload completion time for workload A. However, core2is throttled to operate at 50% of its full performance to execute task A2and complete that task by the workload completion time. Core3undergoes two separate performance throttling adjustments consistent with embodiments of the invention. Program code may determine that core3can operate at 20% of its full performance to complete Task A3by the workload completion time. At some point in time, the program code may determine that core3will not complete task A3by the workload completion time, and may override the throttling of core3to operate core3at 100% of its full performance. Core4operates at 55% of its full performance to execute both tasks A4and A5. Core5operates at 100% of its full performance to execute both tasks A6and B1. As such, core5may have received both tasks A6and B1, then may have had any performance throttling overridden. In this manner, the illustration160ofFIG. 9illustrates aspects of performance throttling cores of a parallel processing computing system consistent with embodiments of the invention to reduce the power consumption of that parallel processing computing system

While the present invention has been illustrated by a description of the various embodiments and the examples, and while these embodiments have been described in considerable detail, it is not the intention of the applicants to restrict or in any way limit the scope of the appended claims to such detail. Additional advantages and modifications will readily appear to those skilled in the art. Thus, the invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method described. One having ordinary skill in the art will further appreciate that the disclosure of the present invention is suitable to implement performance throttling in nodes32, as well as in the computing cores34of nodes32. Thus, the invention in its broader aspects should not be limited to the specific flowchart illustratedFIG. 6. As such, the blocks ofFIG. 6may be re-ordered without departing from the scope of the invention. In addition, while the completion time of parts of a workload are conformed in the illustrated embodiments based upon calculations involving absolute or relative completion times, it will also be appreciated that duration calculations may alternatively be used to conform completion times of parts of a workload. Accordingly, departures may be made from such details without departing from the scope of applicants' general inventive concept.