Process for forming a self-aligned FET having a T-shaped gate structure

A process for formation of a GaAs MESFET for use in digital IC and MMIC is disclosed, the MESFET having a high operating speed and low noise characteristics. A multilayer resist comprising a nitride film, a photo resist, a titanium deposition layer, and a SiO layer made by SOG (spin-on-glass) is formed, and a gate which is formed in the length of 0.7-1 .mu.m by applying the photo transfer method is transcribed in the length of 0.3-0.5 .mu.m. The pattern of the gate is transcribed by etching it down to GaAs, and the place for the positioning of the T-shaped gate is defined by depositing tungsten silicide and by side-etching the photo resist. The T-shaped gate is manufactured by electroplating gold, and by lifting off the rest of the portions. The source and drain are then formed in a self-aligned manner by ion-implanting to a high concentration, and then a heat treatment is carried out to make active. A resistant contact is then formed by applying the photo transfer method and an etching, and is completed by depositing AuGe/Ni and by carrying out an alloy-treatment. A conventional metallization is then performed to complete the self-aligned gaAs MESFET having a T-shaped gate.

BACKGROUND OF THE INVENTION 
The present invention relates to a method for producing a self-aligned 
field effect transistor (FET) and, in particular, to a method for 
producing a self-aligned metal-semiconductor field effect transistor 
(MESFET) using III-IV compound semiconductors such as gallium arsenide 
(GaAs). 
Gallium arsenide MESFET devices are useful in digital integrated circuits 
and high-frequency applications, e.g., in the microwave range. In such 
applications, it is necessary to improve the low noise property while 
reducing the gate resistance and the source-gate capacitance. In addition, 
it is desired to reduce the source resistance and increase the drain 
breakdown voltage. Attempts have been made to reduce the gate resistance 
and gate capacitance by reducing the gate length. For example, FIG. 2 
shows a self-aligned N+-layer technology type field effect transistor 
produced using a dummy gate and multi-layer resist technology. In this 
structure, a semi-insulating gallium arsenide substrate 101b has an ion 
implanted active layer 102b therein. Through contact holes in an 
insulating layer 111b are formed source and drain contacts 116b and a 
Schottky gate contact 114b. However, using this technology, the oxide 
lift-off is difficult, and it is also difficult to reduce the gate length 
of the gate 114b less than 0.6 microns using conventional 
photolithographic and etching techniques. The capacitance between the gate 
and source is also undesirably large. 
FIG. 3 shows another attempt to reduce the gate length by forming a 
self-aligned field effect transistor having side walls 119e. As shown in 
FIG. 3 a semi-insulating gallium arsenide substrate 101c has formed 
therein an active layer with silicon ion implanted ohmic contact regions 
115c. An insulating region 111c is provided with source and drain contacts 
116b being insulated from the gate 114c by side walls 119e. As with the 
structure shown in FIG. 2, it is difficult to reduce the gate length of 
the gate 114c to less than 0.6 microns. It is also difficult to control 
the process to prevent reaction from occurring between the ohmic contact 
region 116b and the rectifying junction of the gate 114c. 
The structure shown in FIG. 4 has been developed in an attempt to reduce 
the length of the gate 114d to less than 0.5 microns using 
photolithography and etching. The structure shown in FIG. 4 has a 
semi-insulating gallium arsenide substrate 101d having an active layer 
102d and ohmic contact regions 115d. Source and drain contact 116c contact 
the ohmic contact regions 115d through holes in the insulating layer 111d. 
Intrinsic side wall spacers 120 separate the gate 114d from the source and 
drain ohmic contact regions 115d. However, the capacitance of the 
gate-source through the insulating film is large and parasitic currents 
exist. 
FIG. 5 shows a slant evaporation technique used in an attempt to reduce the 
gate length of the gate 114e to less than 0.5 microns. However, since it 
is difficult to control the slant evaporation, the reproducibility of the 
process in mass production is difficult. 
Accordingly, it is still desired to provide a method for producing a 
self-aligned FET in particular a gallium arsenide MESFET, having a gate 
length less than 0,6 microns, for example, in the range of 0.3 to 0.5 
microns, which is suitable for mass production and which achieves high 
reproducibility. 
SUMMARY OF THE INVENTION 
The present invention overcomes the above-described disadvantages and 
produces a self-aligned field effect transistor having an active layer in 
a substrate, a T-shaped gate electrode having a predetermined gate length 
over a portion of the active layer, and a source contact region and a 
drain contact region in the substrate on either side of the T-shaped gate. 
The T-shaped gate preferably has a gate length less than 0.6 microns, for 
example in a range of 0.3 to 0.5 microns. The method comprises providing a 
substrate having an active layer therein and forming a first resist layer 
over the substrate. A second resist layer is formed over the first resist 
layer and a patterned first masking layer is formed over the second resist 
layer. The second resist layer is etched using the patterned masking layer 
as a mask to leave a portion of the second resist layer in the form of a 
dummy gate having a predetermined gate length over the active layer. A 
second masking layer is deposited over portions of the first resist layer 
which are not covered by the second resist layer and over the second 
resist layer, and the second resist layer is etched to remove the dummy 
gate and the second masking layer overlying the dummy gate. The first 
resist layer is etched using the second masking layer as a mask and 
exposing a portion of the active layer which corresponds to the 
predetermined gate length. A conductive material is deposited over the 
portion of the active layer which corresponds to the predetermined gate 
length, and side portions of the first resist layer are etched using the 
second masking layer as a mask to leave portions of the second masking 
layer overhanging an opening in the first resist layer. Conductive 
material is deposited in the opening in the first resist layer to form the 
T-shaped gate, and the first resist layer is etched away. Using the 
T-shaped gate as a mask, the substrate is doped and the source contact 
region and the drain contact region are formed. 
The patterned first masking layer can have a pattern such that a portion of 
the first masking layer having a length of approximately 0.7 to 0.8 
microns is left overlying the second resist layer. The side walls of the 
second resist layer can then be ion etched, so that the pattern can be 
reduced to 0.3 to 0.5 microns in the second resist layer, thereby forming 
a dummy gate. The pattern of the dummy gate can be transferred to the 
first resist layer and subsequently a portion of the active layer 
corresponding to a gate length of 0.3 to 0.5 microns can be exposed. 
Preferably, a first conductive material such as tungsten silicide is 
deposited on the exposed surface of the active layer by, e.g., sputtering. 
The tungsten silicide layer protects the surface of the gallium arsenide 
during etching of the side wall in the first resist layer and during any 
high temperature process such as activation of ion implantation 
impurities. Preferably, titanium is then deposited on the tungsten 
silicide and the exposed titanium is plated with gold to form the T-type 
gate.

DETAILED DESCRIPTION OF THE INVENTION 
FIGS. 1A to 1I are cross-sectional views of various stages of the method of 
the present invention. As shown in FIG. IA, a semi-insulating gallium 
arsenide substrate 101 is provided with an active layer 102 appropriately 
doped to form an enhancement-type/depletion-type (E/D) field effect 
transistor. The active layer 102 is formed by providing a photoresist mask 
(not shown) on the semi-insulating gallium arsenide substrate 101 and 
implanting silicon ions at a dose of 1.times.10.sup.12 to 
1.times.10.sup.13 /cm.sup.2 and an energy of about 150 Kev. After removal 
of the photoresist mask, an insulating layer such as a nitride layer 103 
is deposited to a thickness of, e.g., 500 to 800 .ANG. by, e.g., plasma 
enhanced chemical vapor deposition. A metal layer, such as a titanium 
layer 104, may then be deposited on the nitride layer 103. The titanium 
layer 104 may be used in a later step of the process as an electrode for 
gold plating the T-shaped gate. The titanium layer 104 may be deposited by 
sputtering titanium to form a layer about 1,000 .ANG. thick. A photoresist 
layer 105 is deposited on the titanium layer 104. The photoresist layer is 
provided with a thickness approximately equal to the desired thickness of 
the T-shaped gate, e.g., 0.5 to 0.8 microns. The photoresist layer can be 
baked at about 110.degree. C. for about sixty minutes Subsequently, an 
insulating layer such as a nitride layer 106 is, e.g., sputtered to a 
thickness of about 0.1 micron. A second or intermediate photoresist layer 
107 is then deposited on the nitride layer 106. The second or intermediate 
photoresist layer 107 will eventually form the dummy gate and is 
preferably deposited with a thickness of about 0.1 to 2.0 microns. This 
layer can also be baked at about 110.degree. C. for twenty minutes. A 
masking layer, preferably a doped oxide layer such as spin-on-glass 108 is 
then deposited to a thickness of about 0.1 micron and is baked at about 
200.degree. C. for twenty minutes. The doped oxide layer 108 is useful to 
etch the second or intermediate photoresist layer 107. Subsequently, an 
upper layer photoresist 109 is deposited to form the structure shown in 
FIG. 1A. 
By conventional photolithographic techniques, the photoresist layer 109 is 
patterned to have a gate shape corresponding to a gate length of 
approximately 0.6 to 1.0 micron. The patterned photoresist layer 109 is 
used as a mask to etch the doped oxide layer 108 to have approximately the 
same gate shape. For example, the doped oxide layer can be etched at an 
applied voltage of 100 V and a power of 500 W under a pressure of 400 to 
500 mTorr at an etching rate of 0.1 to 0.2 .mu.m/minutes using a mixed gas 
of C.sub.2 F.sub.6 and CHF.sub.3 at 20 to 30 sccm (standard cubic 
centimeters per minute) and 30 to 50 sccm. Etching of the doped oxide 
layer 108 leaves a patterned doped oxide layer 108a as shown in FIG. 1B. 
The second or intermediate photoresist layer 107 is then etched including 
side wall etching of the photoresist layer 107. The side wall etching of 
the intermediate photoresist layer 107 is performed under a pressure of 
400 to 700 mTorr and a power of 800 to 1,500 W using a mixed gas of oxygen 
and SF.sub.6 at 70 sccm and 30 sccm. The layer is anisotropically etched 
at an etching rate of approximately 0.5 to 2.0 .mu.m/minute. Accordingly, 
the shape of the patterned doped oxide layer 108 is reduced and 
transferred to the photoresist layer 107. The patterned photoresist layer 
107a forms a dummy gate 111 having a shape corresponding to a gate length 
of 0.3 to 0.5 microns. As can be seen in FIG. 1B, the side etching of the 
photoresist layer 107 leaves the patterned doped oxide layer 108 
overhanging the dummy gate 111. 
A masking layer such as an oxide layer 110 is then deposited, e.g., by 
vapor deposition, to a thickness of about 2,000 to 3,000 .ANG., as shown 
in FIG. 1C. The oxide layer 110 forms over the exposed nitride layer 106 
which is over portions of the first photoresist layer 105 not covered by 
the dummy gate 111. The oxide layer 110 also forms over the patterned 
doped oxide layer 108a where it is separated from the portion formed over 
the nitride layer 106 due to the overhang of the patterned doped oxide 
layer 108a over the dummy gate 111. 
The dummy gate 111 is then lifted off to expose the nitride layer 106. The 
exposed nitride layer 106 is then etched under a pressure of 500 to 100 
mTorr and a voltage of 300 W at an etching rate of 0.2 .mu.m/minute using 
a mixed gas having a 10:1 ratio of CF.sub.4 and oxygen gas. Etching of the 
lower layer photoresist 105 is then performed under a pressure of 100 to 
400 mTorr and an applied voltage of 300 to 500 V at an etching rate of 0.3 
to 0.8 .mu.m/minute using a mixed gas having 20% of C.sub.2 ClF.sub.5 in 
oxygen. The titanium layer 104 is etched under a pressure of 28 mTorr at 
an etching rate of 200 .ANG./minute using CCl.sub.2 F.sub.2, and the 
nitride layer 103 exposed with the etching of the titanium layer 104 is 
etched under the same conditions as the etching of the nitride layer 106. 
The resulting structure is shown in FIG. 1D. 
As shown in FIG. lE, a conductive material such as tungsten silicide having 
good thermal resistance is deposited to a thickness of about 1,000 .ANG. 
by, e.g., sputtering. The tungsten silicide layer 113 protects the surface 
of the gallium arsenide substrate during subsequent side wall etching of 
the photoresist layer 105 and during high temperature processing such as 
activation of ion implanted impurities. The side walls of the lower 
photoresist layer 105 are then etched under the same conditions as etching 
of the second or intermediate layer photoresist 107. This etching controls 
the shape of the opening 112a in the lower photoresist layer 105 and, 
thus, the shape of the T-shaped gate 114. Thus, the process time is 
controlled to form the desired shape; for example, etching can be 
performed for about twenty minutes FIG. 1F shows the stage of the method 
after such etching. 
If desired, titanium may be deposited on the tungsten silicide by, e.g., 
vapor deposition. The deposited titanium, along with the exposed portion 
104a of the titanium layer 104 can be used as an electrode for gold 
plating under a temperature of 50.degree. C. and a growing rate of 0.1 
.mu.m/minute. The T-shaped gate 114 is then formed, as shown in FIG. 1G. 
Lift-off of the lower photoresist layer 105 can be accomplished using 
acetone and oxygen plasma, and removal of the photoresist using oxygen 
plasma etching at a power of 100 to 200 W under a pressure of 2 Torr for 
ten to twenty minutes flowing oxygen at 10 sccm. After removing the 
titanium layer 104 by dry etching, source and drain regions 115 can be 
formed using the T-shaped gate 114 and photolithographically patterned 
resist layer 105b as a mask. For example, silicon can be ion implanted 
using the T-shaped gate as a mask at an energy of 100 to 200 Kev and a 
dose of 1 to 5.times.10.sup.13 /cm.sup. 2. After activation of the 
implanted ions at, e.g a temperature of 800 to 900.degree. C. for three to 
thirty seconds in a hydrogen atmosphere, an N+ layer forming the ohmic 
contact region of the source and drain 115 are formed as shown in FIG. 1H. 
FIG. 1I shows a completed device. Contact holes are then formed in nitride 
layer 103 and ohmic contact metal 116a, 116b deposited and patterned to 
form source and drain ohmic contacts. The ohmic contact metal 116a, 116b 
may be AuGe/Ni having a thickness of 1,500 .ANG./400 .ANG.. The device may 
be heat-treated at a temperature of about 450.degree. C. for twenty 
minutes to form good ohmic contact. An insulating layer 117 such as 
polyimide may be deposited and metal connect lines 118 deposited and 
patterned. 
While we have shown and described various embodiments in accordance with 
the present invention, it is understood that the same is not limited 
thereto, but is susceptible of numerous changes and modifications as known 
to one having ordinary skill in the art. For example, it is possible to 
use materials other than those mentioned in connection with the specific 
embodiment described above for the various layers. We therefor do not wish 
to be limited to the details shown and described herein, but intend to 
cover all such modifications as are encompassed by the scope of the 
appended claims.