Display device including a sealing area overlapping transfer wirings

A display device includes: an array substrate including a pixel array disposed on a display area, a first transfer wiring disposed on a peripheral area adjacent to the display area and electrically connected to the pixel array, a second transfer wiring disposed on the peripheral area adjacent to the display area and electrically connected to the pixel array, and a barrier member disposed between the first transfer wiring and the second transfer wiring, the barrier member including an inorganic insulation material; and a sealing member disposed between the array substrate and an encapsulation substrate to combine the array substrate with the encapsulation substrate, the sealing member contacting at least a portion of the first transfer wiring and the second transfer wiring.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2019-0127254 filed on Oct. 14, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Exemplary embodiments of the present invention relate to a display device including a sealing area overlapping transfer wirings.

DISCUSSION OF THE RELATED ART

A display device includes an array substrate including an array of pixels. The array substrate may be combined with an opposing substrate or an encapsulation substrate to protect the array of pixels.

In order to combine the array substrate with the encapsulation substrate, a sealing material such as glass frit may be disposed between the encapsulation substrate and the array substrate and may be heated by a laser. However, the sealing area may contain metal wirings. When a metal wiring in a sealing area is heated by the laser, a metallic component of the metal wiring may melt thus reducing a space from an adjacent metal wiring. When a distance between adjacent metal wirings is decreased, a defect such as a short circuit may be caused.

SUMMARY

According to an exemplary embodiment of the present invention, a display device includes: an array substrate including a pixel array disposed on a display area, a first transfer wiring disposed on a peripheral area adjacent to the display area and electrically connected to the pixel array, a second transfer wiring disposed on the peripheral area adjacent to the display area and electrically connected to the pixel array, and a barrier member disposed between the first transfer wiring and the second transfer wiring, the barrier member including an inorganic insulation material; and a sealing member disposed between the array substrate and an encapsulation substrate to combine the array substrate with the encapsulation substrate, the sealing member contacting at least a portion of the first transfer wiring and the second transfer wiring.

The barrier member may have a multi-layered structure.

A height of the barrier member may be larger than a height of at least one of the first transfer wiring and a height of the second transfer wiring.

The first transfer wiring and the second transfer wiring may be spaced apart from the barrier member.

The array substrate may include at least one insulation layer disposed on the peripheral area, and the insulation layer may be partially removed in the peripheral area to form a first recess and a second recess, and the barrier member may be disposed between the first recess and the second recess.

A portion of the first transfer wiring may be disposed in the first recess, and a portion of the second transfer wiring may be disposed in the second recess.

A capping pattern may cover at least a portion of the first transfer wiring.

The capping pattern may include a material having a melting point higher than a melting point of the first transfer wiring.

The capping pattern may include silver, and the first transfer wiring may include aluminum.

The pixel array may include an organic light-emitting element, and the first transfer wiring and the second transfer wiring may provide a power voltage to the organic light-emitting element.

According to an exemplary embodiment of the present invention, a display device includes: an array substrate including a pixel array disposed on a display area, a first transfer wiring disposed on a peripheral area adjacent to the display area and electrically connected to the pixel array, a second transfer wiring disposed on the peripheral area adjacent to the display area and electrically connected to the pixel array, and a capping pattern at least partially covering at least one of the first transfer wiring and the second transfer wiring; and a sealing member disposed between the array substrate and an encapsulation substrate to combine the array substrate with the encapsulation substrate, the sealing member contacting at least a portion of the first transfer wiring and the second transfer wiring.

The capping pattern may include a material having a melting point higher than a melting point of at least one of the first transfer wiring and the second transfer wiring.

The capping pattern may include silver, and the first transfer wiring and the second transfer wiring may include aluminum.

The capping pattern may include: a first capping pattern covering at least a portion of the first transfer wiring; and a second capping pattern covering at least a portion of the second transfer wiring.

The pixel array may include a first electrode, a second electrode and an organic light-emitting layer disposed between the first and second electrodes, wherein the capping pattern may be formed from a same layer as the first electrode.

According to an exemplary embodiment of the present invention, a display device includes: an array substrate including a pixel array disposed on a display area, a first transfer wiring disposed on a peripheral area adjacent to the display area and electrically connected to the pixel array, and a second transfer wiring disposed on the peripheral area adjacent to the display area and electrically connected to the pixel array; an encapsulation substrate disposed on the array substrate, the encapsulation substrate including a transmittance-adjusting pattern overlapping at least a portion of the first transfer wiring and the second transfer wiring; and a sealing member disposed between the array substrate and the encapsulation substrate to combine the array substrate with the encapsulation substrate, the sealing member contacting at least a portion of the first transfer wiring and the second transfer wiring and overlapping the transmittance-adjusting pattern.

The transmittance-adjusting pattern may include a metal oxide.

The transmittance-adjusting pattern may include: a metal oxide layer; and metal patterns disposed on the metal oxide layer and spaced apart from each other.

The transmittance-adjusting pattern may include: metal oxide patterns; and metal patterns having a shape at least partially surrounding the metal oxide patterns, respectively.

An area of the encapsulation substrate, including the transmittance-adjusting pattern may have a laser transmittance lower than a laser transmittance of an area of the encapsulation substrate where the transmittance-adjusting pattern is not disposed by at least 5%.

DETAILED DESCRIPTION OF THE EMBODIMENTS

A display device according to exemplary embodiments of the present invention will be described hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown.

FIG.1is a plan view illustrating a display device according to an exemplary embodiment of the present invention.FIG.2is an enlarged plan view of region A ofFIG.1illustrating a sealing area of a display device according to an exemplary embodiment. Referring toFIG.1, a display device10according to an exemplary embodiment of the present invention includes a display area DA and a peripheral area at least partially surrounding the display area DA. The display area DA may generate a light or may adjust transmittance of a light provided by an external light source to display an image. The peripheral area may be defined by an area of the display device10not displaying an image.

In an exemplary embodiment of the present invention, the display device10may be an organic light-emitting display panel. For example, an array of pixels PX including a light-emitting element may be disposed in the display area DA to generate a light in response to a driving signal. A signal wiring and a power wiring may be disposed in the display area DA to transfer a driving signal and a power voltage to the pixels PX. For example, a gate line GL, a data line DL and a power line PL may be disposed in the display area DA. The gate line GL may extend along a first direction (e.g., the D1direction) and may provide a gate signal to the pixels PX. The data line DL may extend along a second direction (e.g., the D2direction) crossing the first direction (e.g., the D1direction) and may provide a data signal to the pixels PX. The power line PL may extend along the second direction (e.g., the D2direction) and may provide a power voltage to the pixels PX.

A transfer wiring, a circuit part or the like may be disposed in the peripheral area. The transfer wiring may transfer a driving signal or a power voltage to the display area DA. The circuit part may generate a driving signal. For example, a driver DR generating a gate signal, a control signal wiring DSL transferring a control signal to the driver DR, a fan-out wiring FL transferring a data signal to the data line DL, a first transfer wiring PBL1transferring a first power voltage to the pixels PX and a second transfer wiring PBL2transferring a second power voltage to the power line PL or the like may be disposed in the peripheral area.

In an exemplary embodiment of the present invention, the first transfer wiring PBL1may transfer the first power voltage to a cathode of an organic light-emitting diode. A constant voltage may be applied to the first transfer wiring PBL1and the second transfer wiring PBL2. However, the present invention is not limited thereto. The first transfer wiring PBL1and the second transfer wiring PBL2may also be referred to herein more generally as a first transfer wiring PBL1and a second transfer wiring PBL2, respectively.

The transfer wiring may be electrically connected to an external driving device such as a printed circuit board, a driving chip or the like to receive a driving signal, a control signal, a power or the like. The first transfer wiring PBL1may surround first and second parallel short sides and a first long side of the display area DA, and the second transfer wiring PBL2may surround a second long side of the display area DA parallel to the first long side.

In an exemplary embodiment of the present invention, the peripheral area includes a sealing area SA where a sealing member is disposed. The sealing area SA may have a shape surrounding the display area DA. The sealing member SA may be disposed between an outer edge of the peripheral area and the display area DA.

The first transfer wiring PBL1and the second transfer wiring PBL2may extend along the first direction (e.g., the D1direction) and the second direction (e.g., the D2direction) crossing the first direction (e.g., the D1direction), in the peripheral area.

In an exemplary embodiment of the present invention, at least a portion of the transfer wirings may overlap the sealing member SA. In an exemplary embodiment of the present invention, in the sealing area SA, at least a portion of the first transfer wiring PBL1and at least a portion of the second transfer wiring PBL2may extend along the first direction (e.g., the D1direction) and may be spaced apart from each other along the second direction (e.g., the D2direction). For example, the first transfer wiring PBL1may have first and second vertical portions extending in the second direction (e.g., the D2direction), the ends of which are displaced from one another in the first direction (e.g., the D1direction), and joined by a horizontal portion therebetween that extends in the first direction (e.g., the D1direction). The second transfer wiring PBL2may include a horizontal portion extending in the first direction (e.g., the D1direction) and vertical portions extending in the second direction (e.g., the D2direction) from opposite end regions of the horizontal portion of the second transfer wiring PBL2. An end of the horizontal portion of the first transfer wiring PBL1may overlap an end of the horizontal portion of the second transfer wiring PBL2.

FIG.3is a cross-sectional view illustrating a cross-section of a display area of a display device according to an exemplary embodiment of the present invention.FIG.4is a cross-sectional view taken along line I-I′ ofFIG.2illustrating a peripheral area of a display device according to an exemplary embodiment of the present invention.

Referring toFIG.3, a display device includes an array substrate100and an encapsulation substrate200. An array of pixels is disposed in a display area DA of the array substrate100. A pixel unit disposed in the display area DA may include a driving element disposed on a base substrate110and a light-emitting element electrically connected to the driving element. In an exemplary embodiment of the present invention, the light-emitting element may be an organic light-emitting diode.

A buffer layer120may be disposed on the base substrate110. An active pattern AP may be disposed on the buffer layer120.

For example, the base substrate110may include glass, quartz, sapphire, a polymeric material or the like. In an exemplary embodiment of the present invention, the base substrate110may include a transparent rigid material such as glass.

The buffer layer120may prevent or reduce permeation of impurities, humidity or external gas from underneath of the base substrate110, and may provide a planar upper surface of the base substrate110. For example, the buffer layer120may include an inorganic material such as oxide, nitride or the like.

A first gate metal pattern including a gate electrode GE may be disposed on the active pattern AP. A first insulation layer130may be disposed between the active pattern AP and the gate electrode GE. The first insulation layer130may also overlap side surfaces and at least a portion of an upper surface of the active pattern130.

A second gate metal pattern including a gate wiring pattern GP may be disposed on the gate electrode GE. The gate wiring pattern GP may include a capacitor electrode for forming a capacitor, a wiring for transferring various signals or the like.

A second insulation layer140may be disposed between the gate electrode GE and the gate wiring pattern GP. The second insulation layer140may also overlap side surfaces of the gate wiring pattern GP. A third insulation layer150may be disposed on the gate wiring pattern GP. The third insulation layer150may also overlap side surfaces of the gate wiring pattern GP.

For example, the active pattern AP may include silicon or a metal oxide semiconductor. In an exemplary embodiment of the present invention, the active pattern AP may include polycrystalline silicon (polysilicon), which may be doped with n-type impurities or p-type impurities.

In an exemplary embodiment of the present invention, an active pattern may include a metal oxide semiconductor. For example, the active pattern may include a two-component compound (ABx), a ternary compound (ABxCy) or a four-component compound (ABxCyDz), which contains indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr) and/or magnesium (Mg). For example, the active pattern may include zinc oxide (ZnOx), gallium oxide (GaOx), titanium oxide (TiOx), tin oxide (SnOx), indium oxide (InOx), indium-gallium oxide (IGO), indium-zinc oxide (IZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc tin oxide (ZTO), zinc zirconium oxide (ZnZrxOy), indium-gallium-zinc oxide (IGZO), indium-zinc-tin oxide (IZTO), indium-gallium-hafnium oxide (IGHO), tin-aluminum-zinc oxide (TAZO), indium-gallium-tin oxide (IGTO) or the like.

The first insulation layer130, the second insulation layer140and the third insulation layer150may include silicon oxide, silicon nitride, silicon carbide or a combination thereof. Furthermore, the first insulation layer130, the second insulation layer140and the third insulation layer150may include an insulating metal oxide such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide or the like. For example, the first insulation layer130, the second insulation layer140and the third insulation layer150may have a single-layered structure or a multi-layered structure including silicon nitride and/or silicon oxide, respectively, or may have different structures and materials from each other.

The gate electrode GE and the gate wiring pattern GP may include a metal, a metal alloy, a metal nitride, a conductive metal oxide or the like. For example, the gate electrode GE and the gate wiring pattern GP may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta) or an alloy thereof, and may have a single-layered structure or a multi-layered structure including different metal layers.

A first source metal pattern may be disposed on the third insulation layer150. The first source metal pattern may include a source electrode SE and a drain electrode DE, which electrically contact the active pattern AP. The source electrode SE and the drain electrode DE may pass through the first through third insulation layers130,140and150disposed thereunder to contact the active pattern AP, respectively.

The first source metal pattern may include a metal, a metal alloy, a metal nitride, a conductive metal oxide or the like. For example, the first source metal pattern may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta) or an alloy thereof, and may have a single-layered structure or a multi-layered structure including different metal layers. In an exemplary embodiment of the present invention, the first source metal pattern may have a multi-layered structure including an aluminum layer.

A fourth insulation layer160may be disposed on the first source metal pattern. The fourth insulation layer160may include an organic material. For example, the fourth insulation layer160may include an organic insulation material such as a phenol resin, an acryl resin, a polyimide resin, a polyamide resin, a siloxane resin, an epoxy resin or the like.

An organic light-emitting diode180may be disposed on the fourth insulation layer160. The organic light-emitting diode180may include a first electrode182electrically connected to the drain electrode DE, an organic light-emitting layer184disposed on the first electrode182and a second electrode186disposed on the organic light-emitting layer184. The organic light-emitting layer184of the organic light-emitting diode180may be disposed at least in an opening of a pixel-defining layer170disposed on the fourth insulation layer160. The first electrode182may be a lower electrode of the organic light-emitting diode180, and the second electrode186may be an upper electrode of the organic light-emitting diode180.

The first electrode182may function as an anode. For example, the first electrode182may be formed as a transmitting electrode or a reflecting electrode according to an emission type of the display device (a front emission type or a rear emission type). When the first electrode182is a transmitting electrode, the first electrode182may include indium tin oxide, indium zinc oxide, zinc tin oxide, indium oxide, zinc oxide, tin oxide or the like. When the first electrode182is a reflecting electrode, the first electrode182may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti) or a combination thereof, and may have a stacked structure further including the material that may be used for the transmitting electrode.

The pixel-defining layer170has an opening overlapping at least a portion of the first electrode182. For example, the pixel-defining layer170may include an organic insulating material.

The organic light-emitting layer184may include at least a light-emitting layer, and may further include at least one of a hole injection layer (HIL), a hole transporting layer (HTL), an electron transporting layer (ETL) and an electron injection layer (EIL). For example, the organic light-emitting layer184may include a low molecular weight organic compound or a high molecular weight organic compound.

In an exemplary embodiment of the present invention, the organic light-emitting layer184may emit a red light, a green light or a blue light. In an exemplary embodiment of the present invention, the organic light-emitting layer184may emit a white light. The organic light-emitting layer184emitting a white light may have a multi-layer structure including a red-emitting layer, a green-emitting layer and a blue-emitting layer, or a single-layer structure including a mixture of a red-emitting material, a green-emitting material and a blue-emitting material.

The second electrode186may be formed as a transmitting electrode or a reflecting electrode according to an emission type of the display device. For example, the second electrode186may include a metal, a metal alloy, a metal nitride, a metal fluoride, a conductive metal oxide or a combination thereof.

For example, the second electrode186may be formed as a common layer extending continuously over a plurality of pixels in the display area DA.

An encapsulation substrate200is disposed on the organic light-emitting diode180. For example, the encapsulation substrate200may include glass, quartz, sapphire, a polymeric material or the like. In an exemplary embodiment of the present invention, the encapsulation substrate200may include a transparent rigid material such as glass.

For example, a spacer may be disposed under the encapsulation substrate200to support the encapsulation substrate200. The spacer may be disposed between the encapsulation substrate200and the organic light-emitting diode180or between the pixel-defining layer170and the second electrode186of the organic light-emitting diode180.

According to an exemplary embodiment of the present invention, a space between the encapsulation substrate200and the organic light-emitting diode180may have a vacuum state or may be filled with a gas or a sealing member. The sealing member may include an organic layer, an inorganic layer or a combination thereof.

Referring toFIG.4, a first transfer wiring PBL1and a second transfer wiring PBL2are disposed in a peripheral area. At least one of the first transfer wiring PBL1and the second transfer wiring PBL2may overlap a sealing member SM. For example, at least a portion of the first transfer wiring PBL1and the second transfer wiring PBL2may contact the sealing member SM. The sealing member SM may be disposed between the first and second transfer wirings PBL1and PBL2and the encapsulation substrate200.

In an area where the sealing member SM is disposed, the first transfer wiring PBL1and the second transfer wiring PBL2may respectively extend along a first direction (e.g., the D1direction), and may be spaced apart from each other along a second direction (e.g., the D2direction) crossing the first direction (e.g., the D1direction).

The first transfer wiring PBL1and the second transfer wiring PBL2may be formed from a same layer as the first source metal pattern disposed in the display area DA that includes the source electrode SE and the drain electrode DE. Thus, the first transfer wiring PBL1and the second transfer wiring PBL2may be included in the first source metal pattern. However, exemplary embodiments of the present invention are not limited thereto. For example, when the array substrate100includes a second source metal pattern including a connection electrode electrically connecting the drain electrode of the driving element to the first electrode of the organic light-emitting diode, at least one of the first transfer wiring PBL1and the second transfer wiring PBL2may be included in the second source metal pattern.

A barrier member BA is disposed between the first transfer wiring PBL1and the second transfer wiring PBL2. The barrier member BA may have a single-layered structure or a multi-layered structure. For example, the barrier member BA may include a first barrier layer132, a second barrier layer142and a third barrier layer152. For example, the first barrier layer132may be formed from a same layer as the first insulation layer130disposed in the display area DA. The second barrier layer142may be formed from a same layer as the second insulation layer140disposed in the display area DA. The third barrier layer152may be formed from a same layer as the third insulation layer150disposed in the display area DA. In an exemplary embodiment of the present invention, the barrier member BA may have a single-layered structure formed from a same layer as the third insulation layer150disposed in the display area DA.

In an exemplary embodiment of the present invention, the barrier member BA may have a shape extending along the first direction (e.g., the D1direction). However, exemplary embodiments of the present invention are not limited thereto. In another area, the first transfer wiring PBL1and the second transfer wiring PBL2may extend along the second direction (e.g., the D2direction), and may be spaced apart from each other along the first direction (e.g., the D1direction).

In an exemplary embodiment of the present invention, the barrier member BA may substantially exclude an organic insulation material.

Referring toFIG.4, the first transfer wiring PBL1and the second transfer wiring PBL2are disposed on a buffer layer120. However, exemplary embodiments of the present invention are not limited thereto. A structure under the first transfer wiring PBL1and the second transfer wiring PBL2may be changed depending on an etching process or the like. For example, the first transfer wiring PBL1and the second transfer wiring PBL2may be disposed on a first insulation layer130or a second insulation layer140, which extends from the display area DA.

In an exemplary embodiment of the present invention, a height of the barrier member BA may be greater than a height of at least one of the first transfer wiring PBL1and a height of the second transfer wiring PBL2. For example, the third insulation layer150, which may form the barrier member BA, may be an interlayer insulation layer, which has a thickness larger than a thickness of the first source metal pattern forming the first and second transfer wirings PBL1and PBL2.

In an exemplary embodiment of the present invention, the barrier member BA is disposed between the first transfer wiring PBL1and the second transfer wiring PBL2. Thus, even if the first transfer wiring PBL1or the second transfer wiring PBL2is heated in the process of forming the sealing member SM, a short circuit due to melting of a metallic component may be prevented. Thus, reliability of a display device may be increased.

Furthermore, since defects may be prevented or reduced by the barrier member BA, a margin area for preventing defects may be reduced. Thus, a distance between the first transfer wiring PBL1and the second transfer wiring PBL2may be reduced, and a bezel of a display device10may be reduced.

Furthermore, the barrier member BA may be formed in the process of forming insulation layers of a display area DA. Thus, reliability of a display device10may be increased without performing an additional process.

FIGS.5A,5B,6A,6B,7A,7B,8A and8Bare cross-sectional views illustrating steps in a method for manufacturing a display device according to an exemplary embodiment of the present invention. Particularly,FIGS.5A,6A,7A and8Amay illustrate a driving element and a light-emitting element disposed in a display area, andFIGS.5B,6B,7B and8Bmay illustrate a peripheral area.

Referring toFIG.5A, a buffer layer120is formed on a base substrate110. An active pattern AP is formed on the buffer layer120. A first insulation layer130is formed on the active pattern AP. A first gate metal pattern including a gate electrode GE is formed on the first insulation layer130. A second insulation layer140is formed on the first gate metal pattern. A second gate metal pattern including a gate wiring pattern GP is formed on the second insulation layer140. A third insulation layer150is formed on the second gate metal pattern.

Referring toFIG.5B, the buffer layer120, the first insulation layer130, the second insulation layer140and the third insulation layer150may extend to a peripheral area.

Referring toFIG.6A, the insulation layers are patterned to form contact holes CH1and CH2exposing the active pattern AP. For example, the first insulation layer130, the second insulation layer140and the third insulation layer150may be partially removed to form the contact holes CH1and CH2.

Referring toFIG.6B, at least a portion of the insulation layers are removed in the peripheral area in the process of forming the contact holes CH1and CH2, to form a recess and a barrier member BA. For example, the insulation layers are partially removed in the peripheral area to form a first recess OP1and a second recess OP2, which are spaced apart from each other along a second direction (e.g., the D2direction). A portion of the insulation layers, which remains between the first and second recesses OP1and OP2, may define the barrier member BA.

For example, the barrier member BA may include a first barrier layer132, a second barrier layer142and a third barrier layer152which may be the same or different heights in a thickness direction perpendicular to a plane defined by the first direction (e.g., the D1direction) and the second direction (e.g., the D2direction). The first barrier layer132is formed from a same layer as the first insulation layer130disposed in the display area DA. The second barrier layer142is formed from a same layer as the second insulation layer140disposed in the display area DA. The third barrier layer152is formed from a same layer as the third insulation layer150disposed in the display area. For example, the first barrier layer132, the second barrier layer142and the third barrier layer152may include silicon oxide, silicon nitride, silicon carbide or a combination thereof. Furthermore, the first barrier layer132, the second barrier layer142and the third barrier layer152may include an insulating metal oxide such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide or the like. For example, the first barrier layer132, the second barrier layer142and the third barrier layer152may have a single-layered structure or a multi-layered structure including silicon nitride and/or silicon oxide, respectively, or may have different structures and materials from each other.

However, the present invention is not limited thereto. For example, the barrier layer BA may include various other inorganic insulating materials and/or may be comprised of a single layer.

In an exemplary embodiment of the present invention, the contact holes CH1and CH2and the first and second recesses OP1and OP2may be formed in a same photolithography process. However, exemplary embodiments of the present invention are not limited thereto. For example, the contact holes CH1and CH2and the first and second recesses OP1and OP2may be formed in different photolithography processes to adjust a depth of the first and second recesses OP1and OP2.

Referring toFIGS.7A and7B, a first source metal pattern is formed on the third insulation layer150. The first source metal pattern includes a source electrode SE, a drain electrode DE and a transfer wiring. The transfer wiring may include the first transfer wiring PBL1and/or the second transfer wiring PBL2. In an exemplary embodiment of the present invention, the source metal pattern may include an aluminum layer. For example, the first source metal pattern may have a multi-layered structure of titanium/aluminum/titanium.

At least a portion of the first transfer wiring PBL1is disposed in the first recess OP1. At least a portion of the second transfer wiring PBL2is disposed in the second recess OP2. Thus, the barrier member BA is disposed between the first transfer wiring PBL1and the second transfer wiring PBL2.

Referring toFIG.8A, a fourth insulation layer160is formed in the display area DA to cover the first source metal pattern. A pixel-defining layer170and an organic light-emitting diode180are disposed on the fourth insulation layer160.

Thereafter, an encapsulation substrate200is disposed on the array substrate100including the organic light-emitting diode180. For example, the encapsulation substrate200may be disposed over the organic light-emitting diode180with a gap therebetween.

Referring toFIG.8B, a sealing material FR is disposed between the array substrate100and the encapsulation substrate200in the sealing area SA.

For example, the sealing material FR is provided on a surface of the encapsulation substrate200. However, exemplary embodiments of the present invention are not limited thereto. For example, the sealing material FR may be provided on a surface of the array substrate100, and the encapsulation substrate200may be disposed on the sealing material FR. For example, a frit paste or the like may be coated in the sealing area SA of the array substrate100through a mask having an opening corresponding to the sealing area SA by a screen printing method to provide the sealing material FR on the array substrate100. In an exemplary embodiment of the present invention, the fourth insulation layer160and the pixel-defining layer170may not be disposed in the sealing area SA.

The sealing material FR is heated by heat, UV ray, laser or the like to contact the array substrate100. As a result, the array substrate100and the encapsulation substrate200are combined with each other, and the sealing material FR is sintered to form a sealing member SM.

For example, the sealing material FR may include a glass frit. For example, the glass fit may include an oxide power, a binder and a solvent. For example, the oxide powder may include lead oxide (PbO), silicon oxide (SiO2), zinc oxide (ZnO), bismuth oxide (Bi2O3), boron oxide (B2O3, B2O8), iron oxide (Fe2O3), aluminum oxide (Al2O3) or a combination thereof.

In an exemplary embodiment of the present invention, the barrier member BA is disposed between the first transfer wiring PBL1and the second transfer wiring PBL2. Thus, even if the transfer wiring is heated by laser or the like, a short circuit due to melting of a metallic component may be prevented.

Furthermore, the barrier member BA may be formed in the process of forming the insulation layers of the display area DA. Thus, reliability of a display device may be increased without performing an additional process.

FIGS.9,10,11and12are cross-sectional views illustrating cross-sections of a peripheral area of a display device according to exemplary embodiments of the present invention.

Referring toFIG.9, a sealing member SM is disposed between an array substrate100and an encapsulation substrate200in a peripheral area. In the peripheral area, insulation layers including a buffer layer may be disposed on a base substrate110of the array substrate100. For example, a buffer layer120, a first insulation layer130, a second insulation layer140and a third insulation layer150are disposed on the base substrate110. At least one of the buffer layer120, the first insulation layer130, the second insulation layer140and the third insulation layer150may be partially removed to form a first recess OP1and a second recess OP2.

The first recess OP1and the second recess OP2may extend along a first direction (e.g., the D1direction) and may be spaced apart from each other along a second direction (e.g., the D2direction) crossing the first direction (e.g., the D1direction). A portion of the insulation layers, which remains between the first and second recesses OP1and OP2, may define a barrier member BA.

The array substrate100includes a first transfer wiring PBL1and a second transfer wiring PBL2, which are disposed in the peripheral area. The first transfer wiring PBL1and the second transfer wiring PBL2may be spaced apart from each other along the second direction (e.g., the D2direction). A first portion of the first transfer wiring PBL1may be disposed in the first recess OP1, and a second portion may be disposed on the third insulation layer150adjacent to the first recess OP1. For example, the first portion of the first transfer wiring PBL1may be disposed on an upper surface of the buffer layer120including a gap between an end thereof and a side surface of the barrier member BA. The second portion of the first transfer wiring PBL2may extend along a side surface of the third insulation layer150and an upper surface of the third insulation layer150. A first portion of the second transfer wiring PBL2may be disposed in the second recess OP2, and a second portion may be disposed on the third insulation layer150adjacent to the second recess OP2.

The first transfer wiring PBL1and the second transfer wiring PBL2may be spaced apart from the barrier member BA. The sealing member SM may be disposed on the first transfer wiring PBL1and the second transfer wiring PBL2.

In an exemplary embodiment of the present invention, the first transfer wiring PBL1and the second transfer wiring PBL2may be spaced apart from each other by a barrier member BA. Furthermore, the first transfer wiring PBL1and the second transfer wiring PBL2may be partially disposed in a recess.

Referring toFIG.10, a sealing member SM is disposed between an array substrate100and an encapsulation substrate200in a peripheral area. In the peripheral area, insulation layers including a buffer layer may be disposed on a base substrate110of the array substrate100. For example, a buffer layer120, a first insulation layer130, a second insulation layer140and a third insulation layer150are disposed on the base substrate110.

The array substrate100includes a first transfer wiring PBL1and a second transfer wiring PBL2, which are disposed in the peripheral area. The first transfer wiring PBL1and the second transfer wiring PBL2may extend along a first direction (e.g., the D1direction) and may be spaced apart from each other along a second direction (e.g., the D2direction) crossing the first direction (e.g., the D1direction).

An end of at least one of the first transfer wiring PBL1and the second transfer wiring PBL2may be capped by a capping pattern CP. For example, the capping pattern CP may cover an end of the first transfer wiring PBL1, which is adjacent to the second transfer wiring PBL2. In an exemplary embodiment of the present invention, the capping pattern CP may partially cover the first transfer wiring PBL1in view of design margin and efficiency. However, exemplary embodiments are not limited thereto. In an exemplary embodiment of the present invention, the capping pattern CP may entirely cover the first transfer wiring PBL1in the sealing area.

According to an exemplary embodiment of the present invention, the capping pattern CP may cover a lateral surface and a partial upper surface of an edge region of the first transfer wiring PBL1facing the second transfer wiring PBL2.

In an exemplary embodiment of the present invention, the capping pattern CP includes a metal having a higher melting point than the transfer wirings. For example, at least one of the first and second transfer wirings PBL1and PBL2may include aluminum, and the capping pattern CP may include silver. The melting point (about 960° C.) of silver is higher than the melting point (about 660° C.) of aluminum. Thus, metal migration from the first and second transfer wirings PBL1and PBL2may be prevented by the capping pattern CP.

In an exemplary embodiment of the present invention, the capping pattern CP may be formed from a same layer as an anode of the display area. Thus, the capping pattern CP may have a stacked structure including a silver layer and a conductive oxide layer.

In an exemplary embodiment of the present invention, the capping pattern CP may cap one of the first transfer wiring PBL1and the second transfer wiring PBL2. For example, when an area irradiated by a laser is adjacent to the first transfer wiring PBL1, the capping pattern CP may cap only the first transfer wiring PBL1. When a plurality of capping patterns CP cover both of the first transfer wiring PBL1and the second transfer wiring PBL, a short circuit between the wirings may be caused, or a required distance between first transfer wiring PBL1and the second transfer wiring PBL2to be designed may be increased. However, exemplary embodiments of the present invention are not limited thereto. As illustrated inFIG.11, an array substrate100may include a first capping pattern CP1capping a first transfer wiring PBL1and a second capping pattern CP2capping a second transfer wiring PBL2.

Referring toFIG.12, a sealing member SM is disposed between an array substrate100and an encapsulation substrate200in a peripheral area. In the peripheral area, insulation layers including a buffer layer may be disposed on a base substrate110of the array substrate100. For example, a buffer layer120, a first insulation layer130, a second insulation layer140and a third insulation layer150are disposed on the base substrate110. At least one of the buffer layer120, the first insulation layer130, the second insulation layer140and the third insulation layer150may be partially removed to form a first recess OP1and a second recess OP2.

The first recess OP1and the second recess OP2may extend along a first direction (e.g., the D1direction) and may be spaced apart from each other along a second direction (e.g., the D2direction) crossing the first direction (e.g., the D1direction). A portion of the insulation layers, which remains between the first and second recesses OP1and OP2, may define a barrier member BA.

The array substrate100includes a first transfer wiring PBL1and a second transfer wiring PBL2, which are disposed in the peripheral area. The first transfer wiring PBL1and the second transfer wiring PBL2may be spaced apart from each other along the second direction (e.g., the D2direction). At least a portion of the first transfer wiring PBL1may be disposed in the first recess OP1, and at least a portion of the second transfer wiring PBL2may be disposed in the second recess OP2.

The array substrate100includes a capping pattern CP covering an end of at least one of the first transfer wiring PBL1and the second transfer wiring PBL2. The capping pattern CP may be disposed in the first recess OP1or in the second recess OP2.

FIG.13is a cross-sectional view illustrating a method for manufacturing a display device according to an exemplary embodiment of the present invention.FIG.14is a plan view illustrating a display device according to an exemplary embodiment of the present invention.FIGS.15and16are enlarged plan views illustrating a transmittance-adjusting pattern of the display device illustrated inFIG.14.

Referring toFIG.13, a sealing material FR is disposed between an encapsulation substrate200and an array substrate100including a first transfer wiring PBL1and a second transfer wiring PBL2. The sealing material FR is heated and sintered by irradiating laser through the encapsulation substrate200to form a sealing member combining the array substrate100with the encapsulation substrate200.

The encapsulation substrate200includes a transmittance-adjusting pattern RP. For example, the transmittance-adjusting pattern RP may be disposed on an upper surface of the encapsulation substrate200. However, exemplary embodiments of the present invention are not limited thereto. For example, the transmittance-adjusting pattern RP may be disposed on an lower surface of the encapsulation substrate200and may contact the sealing material FR or the sealing member.

An area where the transmittance-adjusting pattern RP is disposed has a laser transmittance lower than a laser transmittance of an area where the transmittance-adjusting pattern RP is not disposed. For example, the area where the transmittance-adjusting pattern RP is disposed may have a laser transmittance lower than a laser transmittance of the area where the transmittance-adjusting pattern RP is not disposed by at least 5%. Thus, melting of the first and second transfer wirings PBL1and PBL2may be prevented or reduced in the area where the transmittance-adjusting pattern RP is disposed.

The transmittance-adjusting pattern RP may be selectively disposed in a short-weak area in order to minimize efficiency decreased of a sealing process. For example, the transmittance-adjusting pattern RP may overlap an area, where the transfer wirings extend along a first direction (e.g., the D1direction) and are spaced apart from each other along a second direction (e.g., the D2direction) crossing the first direction (e.g., the D1direction), as illustrated inFIG.14. According to a design for reducing a bezel, a possibility of a short circuit by the sealing process may be relatively large in the area, since a distance between the first and second transfer wirings PBL1and PBL2is reduced in the area.

For example, the transmittance-adjusting pattern RP may include a metal, a metal alloy, a metal oxide, a metal nitride or a combination thereof.

In an exemplary embodiment of the present invention, the transmittance-adjusting pattern RP may include a metal oxide. For example, the metal oxide may include indium zinc oxide, indium tin oxide, indium oxide, zinc oxide, tin oxide or a combination thereof.

In an exemplary embodiment of the present invention, the transmittance-adjusting pattern RP may have a stacked structure including a metal oxide and a metal.

For example, the transmittance-adjusting pattern RP may include a metal oxide layer CL and metal patterns MP1disposed on the metal oxide layer CL1and spaced apart from each other at regular or irregular intervals. The metal oxide layer CL1may be a continuous layer in the area, where the transmittance-adjusting pattern RP is disposed. For example, the metal patterns MP1may be arranged in a matrix configuration, as illustrated inFIG.15. For example, the metal patterns MP1may be arranged in a staggered array.

The metal patterns MP1may further decrease a laser transmittance. The metal patterns MP1have a conductivity larger than a conductivity of the metal oxide. Thus, when a metal layer is formed continuously in the area, a problem due to static electricity may be caused. In an exemplary embodiment of the present invention, the metal patterns MP1spaced apart from each other are combined with the metal oxide layer CL1which may prevent the problem. For example, the metal patterns MP1may include molybdenum, and the metal oxide layer CL1may include indium tin oxide.

In an exemplary embodiment of the present invention, as illustrated inFIG.16, a transmittance-adjusting pattern RP′ may include metal oxide patterns CL2and metal patterns MP2having a shape at least partially surrounding the metal oxide patterns CL2, respectively, in a plan view.

In the above, exemplary embodiments of the present invention for preventing a short circuit between first and second transfer wirings PBL1and PBL2. However, exemplary embodiments of the present invention are not limited thereto. For example, if other transfer wirings such as a fan-out wiring include a bridge exposed to a sealing member SM, exemplary embodiments of the present invention may be applied to prevent a short circuit of the other transfer wirings.

The above exemplary embodiments of the present invention provide an organic-light emitting display device. However, exemplary embodiments of the present invention are not limited thereto. For example, exemplary embodiments of the present invention may be applied in a sealing structure of various display devices such as a liquid crystal display device, a electroluminescent display device, a micro LED display device or the like.

Exemplary embodiments of the present invention may be applied to various display devices. For example, exemplary embodiments of the present invention may be applied to vehicle-display device, a ship-display device, an aircraft-display device, portable communication devices, display devices for display or for information transfer, a medical-display device, etc.

Although exemplary embodiments of the present invention have been illustrated and described above, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.