Resuming write operations after suspension

Methods, systems, and devices for resuming write operation after suspension are described. A memory system may be configured to determine an upper limit of a threshold voltage of a page of a block at which a performance of a write operation was suspended based at least in part on an indication to resume the performance of the write operation that was previously suspended at a memory system; determine a difference between a first quantity of a first logic state stored in the page and a second quantity of the first logic state associated with an unsuspended write operation based at least in part on determining the upper limit of the threshold voltage; and resume the performance of the write operation based at least in part on determining the difference between the first quantity of the first logic state and the second quantity of the first logic state.

FIELD OF TECHNOLOGY

The following relates to one or more systems for memory, including resuming write operation after suspension.

BACKGROUND

Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component may write (e.g., program, set, assign) one or more memory cells within the memory device to corresponding states.

DETAILED DESCRIPTION

A sudden power loss event may occur at a memory system, for example, in response to power being lost suddenly or in response to a device being removed manually from a power source. This may occur while the memory system is performing a write operation, potentially resulting in the write operation being aborted. Some conventional memory systems handle sudden power loss events by aborting all ongoing write operations and transferring data into single level cell (SLC) blocks from the memory cells (e.g., triple level cells (TLCs)) that were aborted. If power resumes, the system may discard the data in the write-aborted pages. The system copies the data from the write-aborted pages to fresh blocks. The system then copies the data (which had been write-aborted) from the SLC blocks to the fresh blocks. This power loss handling technique may delay the power up stage of the device after a sudden power loss event because data that was already written to pages correctly may be re-written to new pages after power is restored. Further, because a write-abort may cause an extra program-erase (PE) cycle on the aborted blocks and may consume an extra PE cycle of the new blocks, this technique can reduce the endurance of the memory system.

Implementations described herein address the aforementioned shortcomings and other shortcomings by providing a memory system that determines the extent of a program during a write-abort condition and provides the information to the system to continue programming on the write-aborted page. This enables resuming of the program on the write-aborted page by reducing copying some of the data after power is restored and operations are resumed. In some examples, the last written page is identified using an erase-page-check feature, and the maximum threshold voltage (Vt max) applied to the write aborted page as part of the write operation is determined. The total number of logic 1 values at the Vt max may be determined. The total number of logic 1 values at the Vt max may be compared with a threshold quantity, which may represent quantity of logic 1 values that occur in a page after a write operation is complete. Based on this comparison, the extent of correctly written logic states in the write aborted block may be determined.

Features of the disclosure are initially described in the context of systems, devices, and circuits with reference toFIGS.1and2. Features of the disclosure are described in the context of determining an extent of a write operation and resuming a write operation after a write-abort event with reference toFIGS.3through6. These and other features of the disclosure are further illustrated by and described in the context of an apparatus diagram and a flowchart that relate to resuming write operation after suspension with reference toFIGS.7and8.

FIG.1illustrates an example of a system100that supports resuming write operation after suspension in accordance with examples as disclosed herein. The system100includes a host system105coupled with a memory system110.

The memory system controller115may also include a local memory120. In some cases, the local memory120may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) executable by the memory system controller115to perform functions ascribed herein to the memory system controller115. In some cases, the local memory120may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller115for internal storage or calculations, for example, related to the functions ascribed herein to the memory system controller115. Additionally or alternatively, the local memory120may serve as a cache for the memory system controller115. For example, data may be stored in the local memory120if read from or written to a memory device130, and the data may be available within the local memory120for subsequent retrieval for or manipulation (e.g., updating) by the host system105(e.g., with reduced latency relative to a memory device130) in accordance with a cache policy.

In some cases, planes165may refer to groups of blocks170, and in some cases, concurrent operations may take place within different planes165. For example, concurrent operations may be performed on memory cells within different blocks170so long as the different blocks170are in different planes165. In some cases, an individual block170may be referred to as a physical block, and a virtual block180may refer to a group of blocks170within which concurrent operations may occur. For example, concurrent operations may be performed on blocks170-a,170-b,170-c, and170-dthat are within planes165-a,165-b,165-c, and165-d, respectively, and blocks170-a,170-b,170-c, and170-dmay be collectively referred to as a virtual block180. In some cases, a virtual block may include blocks170from different memory devices130(e.g., including blocks in one or more planes of memory device130-aand memory device130-b). In some cases, the blocks170within a virtual block may have the same block address within their respective planes165(e.g., block170-amay be “block0” of plane165-a, block170-bmay be “block0” of plane165-b, and so on). In some cases, performing concurrent operations in different planes165may be subject to one or more restrictions, such as concurrent operations being performed on memory cells within different pages175that have the same page address within their respective planes165(e.g., related to command decoding, page address decoding circuitry, or other circuitry being shared across planes165).

In some cases, to update some data within a block170while retaining other data within the block170, the memory device130may copy the data to be retained to a new block170and write the updated data to one or more remaining pages of the new block170. The memory device130(e.g., the local controller135) or the memory system controller115may mark or otherwise designate the data that remains in the old block170as invalid or obsolete and may update a logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) for the data with the new, valid block170rather than the old, invalid block170. In some cases, such copying and remapping may be performed instead of erasing and rewriting the entire old block170due to latency or wearout considerations, for example. In some cases, one or more copies of an L2P mapping table may be stored within the memory cells of the memory device130(e.g., within one or more blocks170or planes165) for use (e.g., reference and updating) by the local controller135or memory system controller115.

In some cases, L2P mapping tables may be maintained and data may be marked as valid or invalid at the page level of granularity, and a page175may contain valid data, invalid data, or no data. Invalid data may be data that is outdated due to a more recent or updated version of the data being stored in a different page175of the memory device130. Invalid data may have been previously programmed to the invalid page175but may no longer be associated with a valid logical address, such as a logical address referenced by the host system105. Valid data may be the most recent version of such data being stored on the memory device130. A page175that includes no data may be a page175that has never been written to or that has been erased.

In some cases, a memory system controller115or a local controller135may perform operations (e.g., as part of one or more media management algorithms) for a memory device130, such as wear leveling, background refresh, garbage collection, scrub, block scans, health monitoring, or others, or any combination thereof. For example, within a memory device130, a block170may have some pages175containing valid data and some pages175containing invalid data. To avoid waiting for all of the pages175in the block170to have invalid data in order to erase and reuse the block170, an algorithm referred to as “garbage collection” may be invoked to allow the block170to be erased and released as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting a block170that contains valid and invalid data, selecting pages175in the block that contain valid data, copying the valid data from the selected pages175to new locations (e.g., free pages175in another block170), marking the data in the previously selected pages175as invalid, and erasing the selected block170. As a result, the quantity of blocks170that have been erased may be increased such that more blocks170are available to store subsequent data (e.g., data subsequently received from the host system105).

In some cases, a memory system110may utilize a memory system controller115to provide a managed memory system that may include, for example, one or more memory arrays and related circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller135). An example of a managed memory system is a managed NAND (MNAND) system.

The system100may include any quantity of non-transitory computer readable media that support resuming write operation after suspension. For example, the host system105(e.g., a host system controller106), the memory system110(e.g., a memory system controller115), or a memory device130(e.g., a local controller135) may include or otherwise may access one or more non-transitory computer readable media storing instructions (e.g., firmware, logic, code) for performing the functions ascribed herein to the host system105, the memory system110, or a memory device130. For example, such instructions, if executed by the host system105(e.g., by a host system controller106), by the memory system110(e.g., by a memory system controller115), or by a memory device130(e.g., by a local controller135), may cause the host system105, the memory system110, or the memory device130to perform associated functions as described.

In some implementations, the memory system110determines the extent of a program during a write-abort condition and provides information regarding the extent of the program to the system100to continue the write operation on the write-aborted page. This enables resuming of the program on the write-aborted page by reducing copying some of the data after power is restored and operations are resumed. In some implementations, the last written page may be identified using an erase-page-check feature, and the maximum threshold voltage (Vt max) applied to the write aborted page as part of the write operation is determined. The total number of logic 1 values at the Vt max may be determined. The total number of logic 1 values at the Vt max may be compared with a threshold quantity, which may represent a quantity of logic 1 values that occur in a page after a write operation is complete. Based on this comparison, the extent of correctly written logic states in the write aborted block is determined.

Because the disclosed subject matter does not involve copying data from write-aborted blocks to new blocks, it may facilitate faster return to a power up state of the device after a sudden power loss as compared with some conventional techniques. In addition, because no operations are performed during the power loss event, it may reduce or avoid delays as compared with some conventional techniques. Moreover, the disclosed subject matter may not consume an extra program-erase cycle on the write-aborted blocks and new blocks. Accordingly, there is no impact on device endurance, regardless of the number of sudden power loss events.

FIG.2illustrates an example of a system200that supports resuming write operation after suspension in accordance with examples as disclosed herein. The system200may be an example of a system100as described with reference toFIG.1or aspects thereof. The system200may include a memory system210configured to store data received from the host system205and to send data to the host system205, if requested by the host system205using access commands (e.g., read commands or write commands). The system200may implement aspects of the system100as described with reference toFIG.1. For example, the memory system210and the host system205may be examples of the memory system110and the host system105, respectively.

The memory system210may include memory devices240to store data transferred between the memory system210and the host system205, e.g., in response to receiving access commands from the host system205, as described herein. The memory devices240may include one or more memory devices as described with reference toFIG.1. For example, the memory devices240may include NAND memory, PCM, self-selecting memory, 3D cross point or other chalcogenide-based memories, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

The memory system210may include a storage controller230for controlling the passing of data directly to and from the memory devices240, e.g., for storing data, retrieving data, and determining memory locations in which to store data and from which to retrieve data. The storage controller230may communicate with memory devices240directly or via a bus (not shown) using a protocol specific to each type of memory device240. In some cases, a single storage controller230may be used to control multiple memory devices240of the same or different types. In some cases, the memory system210may include multiple storage controllers230, e.g., a different storage controller230for each type of memory device240. In some cases, a storage controller230may implement aspects of a local controller135as described with reference toFIG.1.

The memory system210may additionally include an interface220for communication with the host system205and a buffer225for temporary storage of data being transferred between the host system205and the memory devices240. The interface220, buffer225, and storage controller230may be for translating data between the host system205and the memory devices240, e.g., as shown by a data path250, and may be collectively referred to as data path components.

Using the buffer225to temporarily store data during transfers may allow data to be buffered as commands are being processed, thereby reducing latency between commands and allowing arbitrary data sizes associated with commands. This may also allow bursts of commands to be handled, and the buffered data may be stored or transmitted (or both) once a burst has stopped. The buffer225may include relatively fast memory (e.g., some types of volatile memory, such as SRAM or DRAM) or hardware accelerators or both to allow fast storage and retrieval of data to and from the buffer225. The buffer225may include data path switching components for bi-directional data transfer between the buffer225and other components.

The temporary storage of data within a buffer225may refer to the storage of data in the buffer225during the execution of access commands. That is, upon completion of an access command, the associated data may no longer be maintained in the buffer225(e.g., may be overwritten with data for additional access commands). In addition, the buffer225may be a non-cache buffer. That is, data may not be read directly from the buffer225by the host system205. For example, read commands may be added to a queue without an operation to match the address to addresses already in the buffer225(e.g., without a cache address match or lookup operation).

The memory system210may additionally include a memory system controller215for executing the commands received from the host system205and controlling the data path components in the moving of the data. The memory system controller215may be an example of the memory system controller115as described with reference toFIG.1. A bus235may be used to communicate between the system components.

In some cases, one or more queues (e.g., a command queue260, a buffer queue265, and a storage queue270) may be used to control the processing of the access commands and the movement of the corresponding data. This may be beneficial, e.g., if more than one access command from the host system205is processed concurrently by the memory system210. The command queue260, buffer queue265, and storage queue270are depicted at the interface220, memory system controller215, and storage controller230, respectively, as examples of a possible implementation. However, queues, if used, may be positioned anywhere within the memory system210.

Data transferred between the host system205and the memory devices240may take a different path in the memory system210than non-data information (e.g., commands, status information). For example, the system components in the memory system210may communicate with each other using a bus235, while the data may use the data path250through the data path components instead of the bus235. The memory system controller215may control how and if data is transferred between the host system205and the memory devices240by communicating with the data path components over the bus235(e.g., using a protocol specific to the memory system210).

If a host system205transmits access commands to the memory system210, the commands may be received by the interface220, e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol). Thus, the interface220may be considered a front end of the memory system210. Upon receipt of each access command, the interface220may communicate the command to the memory system controller215, e.g., via the bus235. In some cases, each command may be added to a command queue260by the interface220to communicate the command to the memory system controller215.

The memory system controller215may determine that an access command has been received based on the communication from the interface220. In some cases, the memory system controller215may determine the access command has been received by retrieving the command from the command queue260. The command may be removed from the command queue260after it has been retrieved therefrom, e.g., by the memory system controller215. In some cases, the memory system controller215may cause the interface220, e.g., via the bus235, to remove the command from the command queue260.

Upon the determination that an access command has been received, the memory system controller215may execute the access command. For a read command, this may mean obtaining data from the memory devices240and transmitting the data to the host system205. For a write command, this may mean receiving data from the host system205and moving the data to the memory devices240.

In either case, the memory system controller215may use the buffer225for, among other things, temporary storage of the data being received from or sent to the host system205. The buffer225may be considered a middle end of the memory system210. In some cases, buffer address management (e.g., pointers to address locations in the buffer225) may be performed by hardware (e.g., dedicated circuits) in the interface220, buffer225, or storage controller230.

To process a write command received from the host system205, the memory system controller215may first determine if the buffer225has sufficient available space to store the data associated with the command. For example, the memory system controller215may determine, e.g., via firmware (e.g., controller firmware), an amount of space within the buffer225that may be available to store data associated with the write command.

In some cases, a buffer queue265may be used to control a flow of commands associated with data stored in the buffer225, including write commands. The buffer queue265may include the access commands associated with data currently stored in the buffer225. In some cases, the commands in the command queue260may be moved to the buffer queue265by the memory system controller215and may remain in the buffer queue265while the associated data is stored in the buffer225. In some cases, each command in the buffer queue265may be associated with an address at the buffer225. That is, pointers may be maintained that indicate where in the buffer225the data associated with each command is stored. Using the buffer queue265, multiple access commands may be received sequentially from the host system205and at least portions of the access commands may be processed concurrently.

If the buffer225has sufficient space to store the write data, the memory system controller215may cause the interface220to transmit an indication of availability to the host system205(e.g., a “ready to transfer” indication), e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol). As the interface220subsequently receives from the host system205the data associated with the write command, the interface220may transfer the data to the buffer225for temporary storage using the data path250. In some cases, the interface220may obtain from the buffer225or buffer queue265the location within the buffer225to store the data. The interface220may indicate to the memory system controller215, e.g., via the bus235, if the data transfer to the buffer225has been completed.

Once the write data has been stored in the buffer225by the interface220, the data may be transferred out of the buffer225and stored in a memory device240. This may be done using the storage controller230. For example, the memory system controller215may cause the storage controller230to retrieve the data out of the buffer225using the data path250and transfer the data to a memory device240. The storage controller230may be considered a back end of the memory system210. The storage controller230may indicate to the memory system controller215, e.g., via the bus235, that the data transfer to a memory device of the memory devices240has been completed.

In some cases, a storage queue270may be used to aid with the transfer of write data. For example, the memory system controller215may push (e.g., via the bus235) write commands from the buffer queue265to the storage queue270for processing. The storage queue270may include entries for each access command. In some examples, the storage queue270may additionally include a buffer pointer (e.g., an address) that may indicate where in the buffer225the data associated with the command is stored and a storage pointer (e.g., an address) that may indicate the location in the memory devices240associated with the data. In some cases, the storage controller230may obtain from the buffer225, buffer queue265, or storage queue270the location within the buffer225from which to obtain the data. The storage controller230may manage the locations within the memory devices240to store the data (e.g., performing wear-leveling, garbage collection, and the like). The entries may be added to the storage queue270, e.g., by the memory system controller215. The entries may be removed from the storage queue270, e.g., by the storage controller230or memory system controller215upon completion of the transfer of the data.

To process a read command received from the host system205, the memory system controller215may again first determine if the buffer225has sufficient available space to store the data associated with the command. For example, the memory system controller215may determine, e.g., via firmware (e.g., controller firmware), an amount of space within the buffer225that may be available to store data associated with the read command.

In some cases, the buffer queue265may be used to aid with buffer storage of data associated with read commands in a similar manner as discussed with respect to write commands. For example, if the buffer225has sufficient space to store the read data, the memory system controller215may cause the storage controller230to retrieve the data associated with the read command from a memory device240and store the data in the buffer225for temporary storage using the data path250. The storage controller230may indicate to the memory system controller215, e.g., via the bus235, when the data transfer to the buffer225has been completed.

In some cases, the storage queue270may be used to aid with the transfer of read data. For example, the memory system controller215may push the read command to the storage queue270for processing. In some cases, the storage controller230may obtain from the buffer225or storage queue270the location within the memory devices240from which to retrieve the data. In some cases, the storage controller230may obtain from the buffer queue265the location within the buffer225to store the data. In some cases, the storage controller230may obtain from the storage queue270the location within the buffer225to store the data. In some cases, the memory system controller215may move the command processed by the storage queue270back to the command queue260.

Once the data has been stored in the buffer225by the storage controller230, the data may be transferred out of the buffer225and sent to the host system205. For example, the memory system controller215may cause the interface220to retrieve the data out of the buffer225using the data path250and transmit the data to the host system205, e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol). For example, the interface220may process the command from the command queue260and may indicate to the memory system controller215, e.g., via the bus235, that the data transmission to the host system205has been completed.

The memory system controller215may execute received commands according to an order (e.g., a first-in, first-out order, according to the order of the command queue260). For each command, the memory system controller215may cause data corresponding to the command to be moved into and out of the buffer225, as discussed herein. As the data is moved into and stored within the buffer225, the command may remain in the buffer queue265. A command may be removed from the buffer queue265, e.g., by the memory system controller215, if the processing of the command has been completed (e.g., if data corresponding to the access command has been transferred out of the buffer225). If a command is removed from the buffer queue265, the address previously storing the data associated with that command may be available to store data associated with a new command.

The memory system controller215may additionally be configured for operations associated with the memory devices240. For example, the memory system controller215may execute or manage operations such as wear-leveling operations, garbage collection operations, error control operations such as error-detecting operations or error-correcting operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., LBAs) associated with commands from the host system205and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices240. That is, the host system205may issue commands indicating one or more LBAs and the memory system controller215may identify one or more physical block addresses indicated by the LBAs. In some cases, one or more contiguous LBAs may correspond to noncontiguous physical block addresses. In some cases, the storage controller230may be configured to perform one or more of the described operations in conjunction with or instead of the memory system controller215. In some cases, the memory system controller215may perform the functions of the storage controller230and the storage controller230may be omitted.

In some implementations, the memory system controller215may determine the extent of a program during a write-abort condition and provides information regarding the extent of the program to the memory system210to continue the write operation on the write-aborted page. This enables resuming of the program on the write-aborted page by reducing copying some of the data after power is restored and operations are resumed. In some implementations, the last written page may be identified using an erase-page-check feature, and the maximum threshold voltage (Vt max) applied to the write aborted page as part of the write operation is determined. The total number of logic 1 values at the Vt max may be determined. The total number of logic 1 values at the Vt max may be compared with a threshold quantity, which may represent a quantity of logic 1 values that occur in a page after a write operation is complete. Based on this comparison, the extent of correctly written logic states in the write aborted block is determined.

Because the disclosed subject matter does not involve copying data from write-aborted blocks to new blocks, it may facilitate faster return to a power up of the device state after a sudden power loss as compared with some conventional techniques. In addition, because no operations are performed during the power loss event, it may reduce or avoid delays as compared with some conventional techniques. Moreover, the disclosed subject matter may not consume an extra program-erase cycle on the write-aborted blocks and new blocks. Accordingly, there is no impact on device endurance, regardless of the number of sudden power loss events.

FIG.3illustrates an example method300for detecting an extent of programming for write-abort and continuation of program on a write-aborted page that supports resuming write operation after suspension in accordance with examples as disclosed herein. As represented at block302, a power loss event may occur and the memory system may resume power after the power loss event. In some implementations, as represented at block304, the method300may include finding a write-aborted page, e.g., the last written page of a block being written at the time the power loss event occurs. For example, the last written page may be identified using an erase-page-check feature.

As represented by block306, in some implementations, a maximum threshold voltage Vt Max of the write-aborted page may be found. Some memory systems write data to the cells by writing different logic states to a page. For example, a memory system (that uses TLC) may write a state that corresponds to logic state ‘000’ into the various memory cells. Later, the memory system may write different states that correspond to other logic states. By finding the maximum threshold voltage written into the page, the memory system may identify an estimate of a position that the write operation was aborted.

As represented by block308, a total quantity of logic 1 values that occur at that Vt of the write-aborted page may be counted. This determination may refine the memory system's estimate of the position that the write operation was aborted. As represented by block310, this quantity may be compared with another quantity of logic 1 values that occur at the same Vt for a complete programmed page that may be used as a reference page. For example, a certain quantity of logic 1 values at a voltage level may be expected to be programmed into the block based on characterizations of writing data into the memory system. The quantity of logic 1 values in the block may be compared with an expected value of logic 1 values. This comparison may provide more granular information about the location that the write operation was aborted.

In some implementations, as represented by block312, the difference, or delta, between a first quantity of logic 1 values for the write-aborted page and a second expected quantity of logic 1 values the complete programmed page may be compared to a threshold (e.g., 40000). If the difference is less than the threshold, a write voltage Vpgm and a quantity of loops that was completed before the write operation was suspended may be determined, as represented by block314. The write voltage Vpgm and/or the quantity of loops may be determined based at least in part on reference data derived from a characterization of the memory system. This information may be sent to the memory system. In some implementations, the memory system may send this information to the memory device (e.g., NAND memory). As represented by block316, the memory device may then resume performing the write operation at the write-aborted page with a first offset and/or a second offset. For example, a first offset X may be associated with the write voltage Vpgm to apply in response to resuming the write operation. A second offset Y may be associated with the quantity of loops to apply in response to resuming the write operation. The offsets X and Y may be based at least in part on the difference between a first quantity of logic 1 values for the write aborted page and a second expected quantity of logic 1 values for the complete programmed page being less than the threshold difference (e.g., 40000). In some implementations, the performance of the write operation may be resumed using the first offset X and the second offset Y (e.g., {Vpgm_base+X, number of loops−Y}). In some implementations, the offsets X and Y may be based on a characteristic associated with the memory system.

In some implementations, as represented by block322, if the difference is greater than or equal to the threshold, the system may continue to find the cliff point of the write-aborted page. For example, a voltage amount may be decreased (e.g., decreasing the value of Vt by 500 mV, which may be referred to as a leftward shift) may be applied, and the processes represented by blocks308,310, and312may be repeated.

FIG.4illustrates an example memory system400configured to handle a sudden power loss event that supports resuming write operation after suspension in accordance with examples as disclosed herein. The example memory system400includes memory units logically organized into blocks402,404, each of which comprises a number of pages406. As illustrated inFIG.4, at a time t1, a write-abort event may occur, e.g., due to a sudden power loss. The write-abort event may cause a write operation to block404to be interrupted at a page406a. At a time t2, the memory system400may abort ongoing programming operations and flush data to be written into block404to a SLC) block, such as block402. If the block404is a TLC block, then the data write to the SLC block at block402may be take triple the quantity of memory cells to store. The memory system may flush data from the buffer into SLC blocks because SLC writes may be faster and more reliable than TLC writes and may be capable of being completed before power is lost completely, in some cases.

During the power loss event, no operations may be performed by the memory system400, in some examples. At a time t3, after power is restored, the memory system400may perform the process described herein in connection withFIG.3to determine the extent to which the write operation was completed before the write-abort event (e.g., determine the location408that the write operation was aborted). For example, a maximum threshold voltage Vt Max of the write-aborted page406amay be found. A total quantity of logic 1 values that occur at that Vt of the write-aborted page406amay be counted. This quantity may be compared with another quantity of logic 1 values that occur at the same Vt for a complete programmed page, e.g., a page406b.

The difference, or delta, between a first quantity of logic 1 values for the write-aborted page406aand a second expected quantity of logic 1 values for the complete programmed page406bmay be compared to a threshold (e.g., 40000). If the difference is less than the threshold, a write voltage Vpgm and a quantity of loops that was completed before the write operation was suspended may be determined. The write voltage Vpgm and/or the quantity of loops may be determined based at least in part on reference data derived from a characterization of the memory system. This information may be sent to the system. In some implementations, the system may send this information to the memory. At a time t4, the memory may then resume performing the write operation at the write-aborted page with a first offset and/or a second offset. For example, a first offset X may be associated with the write voltage Vpgm to apply in response to resuming the write operation. A second offset Y may be associated with the quantity of loops to apply in response to resuming the write operation. The offsets X and Y may be based at least in part on the difference between the first quantity of logic 1 values for the write-aborted page and a second expected quantity of logic 1 values for the complete programmed page being less than the threshold difference (e.g., 40000). In some implementations, the performance of the write operation may be resumed using the first offset X and the second offset Y. In some implementations, the offsets X and Y may be based on a characteristic associated with the memory system.

FIG.5illustrates example cell voltage distributions of a triple-level cell (TLC) program with various degrees of completeness that supports resuming write operation after suspension in accordance with examples as disclosed herein. For example, a voltage distribution502may represent a complete programmed page reference, which may represent a complete TLC program that may be used as a reference. In the voltage distribution502, states L1, L2, L3, L4, L5, L6, L7, and L8 may represent eight different memory states (e.g., corresponding to three bits of data stored by a TLC) that may be stored in a TLC cell, which may correspond to eight different threshold voltages of a completed write operation. The states L1-L8 may be mapped to any logic states (e.g., L1 may map to ‘000’ or ‘111’ or any other logic state). A voltage distribution504may represent an operation that was write-aborted at level 4. A voltage distribution506may represent an operation that was write-aborted at level 7. A voltage distribution508may represent an operation that was write-aborted at the beginning of a write operation (e.g., level 2). Level 1 may correspond to erase distribution. Portions of the figure show that different amounts of a state may be written. The memory system may determine the maximum voltage threshold (e.g., the state) at which the write operation was aborted, such as L4 in504, L7 in506, or L2 in508. The memory system may also determine are early or late in the process of writing the state the write operation was aborted by determining the quantity of logic 1 values at that threshold voltage (e.g., the quantity of logic 1 values written in the block for the L4 level for the distribution504).

FIG.6illustrates an example of the total number of logic 1 values600at different threshold voltages for write-aborted conditions for the write-abort conditions shown inFIG.5that supports resuming write operation after suspension in accordance with examples as disclosed herein. As illustrated inFIG.6, there may be a significant difference between a first quantity of logic 1 values written in write-aborted pages (e.g., as shown with curves604,606, and608) and a second quantity of logic 1 values written in a completed page (e.g., the right-most curve inFIG.6, curve602).

The y-axis of the graph inFIG.6represents the total number of memory cells that store a logic 1 value. The x-axis of the graph inFIG.6represents a threshold voltage written in the memory cells. In response to a write operation being aborted, the remaining portions of a write-aborted page may be written to logic 1 values. For example, the curve immediately to the left of curve602, curve604, represents a write-aborted page that was aborted at L7 level, at which time the quantity of logic 1 values in the write abort page gets higher, directly after the aborting of the write operation. The curve immediately to the left of curve604, curve606, represents a write-aborted page that was aborted at L4 level, at which time the quantity of logic 1 values in the write abort page gets higher, directly after the aborting of the write operation. The left-most curve, curve608, represents a write-aborted page that was aborted at L2 level, at which time the quantity of logic 1 values in the write abort page gets higher, directly after the aborting of the write operation.

In some cases, all of the states may have an equal number of cells, and this can be observed in the case of the curve602that represents the page that is completely written. However, in the case of a write-abort event, cells that are to be written to the higher states still have a lower threshold voltage. Accordingly, at the write-aborted instance (e.g., threshold voltage), a larger quantity of cells may be identified as having logic 1 values than the quantity of cells that have a logic 1 value in a page that is completely written.

FIG.7shows a block diagram700of a memory system720that supports resuming write operation after suspension in accordance with examples as disclosed herein. The memory system720may be an example of aspects of a memory system as described with reference toFIGS.1through6. The memory system720, or various components thereof, may be an example of means for performing various aspects of resuming write operation after suspension as described herein. For example, the memory system720may include a threshold voltage component725, a loop component730, a write component735, a suspension component740, a page component745, a logic state component750, a resume component755, an offset component760, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The threshold voltage component725may be configured as or otherwise support a means for determining an upper limit of a threshold voltage of a page of a block at which a performance of a write operation was suspended based at least in part on an indication to resume the performance of the write operation that was previously suspended at a memory system. The loop component730may be configured as or otherwise support a means for determining a difference between a first quantity of a first logic state stored in the page and a second quantity of the first logic state associated with an unsuspended write operation based at least in part on determining the upper limit of the threshold voltage. The write component735may be configured as or otherwise support a means for resuming the performance of the write operation based at least in part on determining the difference between the first quantity of the first logic state and the second quantity of the first logic state.

In some examples, the suspension component740may be configured as or otherwise support a means for identifying a second indication to suspend the performance of the write operation at the memory system. In some examples, the suspension component740may be configured as or otherwise support a means for suspending the performance of the write operation based at least in part on identifying the indication to suspend the performance, where determining the upper limit is based at least in part on suspending the performance. In some examples, the second indication corresponds to a power loss.

In some examples, the page component745may be configured as or otherwise support a means for determining the page of the block at which the performance of the write operation was suspended, where determining the upper limit is based at least in part on determining the page.

In some examples, the logic state component750may be configured as or otherwise support a means for determining the first quantity of the first logic state stored in the page based at least in part on determining the upper limit of the threshold voltage, where determining the difference is based at least in part on determining the first quantity.

In some examples, the logic state component750may be configured as or otherwise support a means for comparing the difference between the first quantity of the first logic state stored in the page and the second quantity of the first logic state associated with the unsuspended write operation with a threshold difference, where resuming the performance of the write operation is based at least in part on the comparison.

In some examples, to support resuming the performance of the write operation, the resume component755may be configured as or otherwise support a means for determining a write voltage and a quantity of loops completed before the write operation was suspended based at least in part on the difference between the first quantity and the second quantity being less than the threshold difference.

In some examples, the resume component755may be configured as or otherwise support a means for determining at least one of the write voltage or the quantity of loops completed before the write operation was suspended based at least in part on reference data derived from a characterization of the memory system.

In some examples, to support resuming the performance, the suspension component740may be configured as or otherwise support a means for providing the write voltage and the quantity of loops completed before the write operation was suspended to the memory system based at least in part on the difference between the first quantity and the second quantity being less than the threshold difference.

In some examples, to support resuming the performance of the write operation, the suspension component740may be configured as or otherwise support a means for providing the write voltage and the quantity of loops completed before the write operation was suspended to a nonvolatile memory device of the memory system based at least in part on the difference between the first quantity and the second quantity being less than the threshold difference.

In some examples, determining a first offset associated with the write voltage to apply in response to resuming the write operation and a second offset associated with the quantity of loops to apply in response to resuming the write operation based at least in part on the difference between the first quantity and the second quantity being less than the threshold difference. In some examples, where resuming the performance of the write operation further includes: resuming the performance of the write operation at the page using the first offset and the second offset. In some examples, the first offset and the second offset are based on a characteristic associated with the memory system.

In some examples, to support resuming the performance of the write operation, the logic state component750may be configured as or otherwise support a means for determining a third quantity of the first logic state stored in the page based at least in part on determining that a voltage is less than the upper limit of the threshold voltage based at least in part on the difference between the first quantity and the second quantity being greater than the threshold difference.

In some examples, to support resuming the performance, the logic state component750may be configured as or otherwise support a means for determining a second difference between the first quantity of the first logic state stored in the page and the third quantity of the first logic state based at least in part on the difference between the first quantity and the second quantity being greater than the threshold difference.

FIG.8shows a flowchart illustrating a method800that supports resuming write operation after suspension in accordance with examples as disclosed herein. The operations of method800may be implemented by a memory system or its components as described herein. For example, the operations of method800may be performed by a memory system as described with reference toFIGS.1through7. In some examples, a memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the memory system may perform aspects of the described functions using special-purpose hardware.

At805, the method may include determining an upper limit of a threshold voltage of a page of a block at which a performance of a write operation was suspended based at least in part on an indication to resume the performance of the write operation that was previously suspended at a memory system. The operations of805may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of805may be performed by a threshold voltage component725as described with reference toFIG.7.

At810, the method may include determining a difference between a first quantity of a first logic state stored in the page and a second quantity of the first logic state associated with an unsuspended write operation based at least in part on determining the upper limit of the threshold voltage. The operations of810may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of810may be performed by a loop component730as described with reference toFIG.7.

At815, the method may include resuming the performance of the write operation based at least in part on determining the difference between the first quantity of the first logic state and the second quantity of the first logic state. The operations of815may be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of815may be performed by a write component735as described with reference toFIG.7.

Aspect 1: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining an upper limit of a threshold voltage of a page of a block at which a performance of a write operation was suspended based at least in part on an indication to resume the performance of the write operation that was previously suspended at a memory system; determining a difference between a first quantity of a first logic state stored in the page and a second quantity of the first logic state associated with an unsuspended write operation based at least in part on determining the upper limit of the threshold voltage; and resuming the performance of the write operation based at least in part on determining the difference between the first quantity of the first logic state and the second quantity of the first logic state.

Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for identifying a second indication to suspend the performance of the write operation at the memory system and suspending the performance of the write operation based at least in part on identifying the indication to suspend the performance, where determining the upper limit is based at least in part on suspending the performance.

Aspect 3: The method, apparatus, or non-transitory computer-readable medium of aspect 2 where the second indication corresponds to a power loss.

Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 3, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining the page of the block at which the performance of the write operation was suspended, where determining the upper limit is based at least in part on determining the page.

Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 4, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining the first quantity of the first logic state stored in the page based at least in part on determining the upper limit of the threshold voltage, where determining the difference is based at least in part on determining the first quantity.

Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 5, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for comparing the difference between the first quantity of the first logic state stored in the page and the second quantity of the first logic state associated with the unsuspended write operation with a threshold difference, where resuming the performance of the write operation is based at least in part on the comparison.

Aspect 7: The method, apparatus, or non-transitory computer-readable medium of aspect 6 where resuming the performance of the write operation includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining a write voltage and a quantity of loops completed before the write operation was suspended based at least in part on the difference between the first quantity and the second quantity being less than the threshold difference.

Aspect 8: The method, apparatus, or non-transitory computer-readable medium of aspect 7, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining at least one of the write voltage or the quantity of loops completed before the write operation was suspended based at least in part on reference data derived from a characterization of the memory system.

Aspect 9: The method, apparatus, or non-transitory computer-readable medium of any of aspects 7 through 8 where resuming the performance, further includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for providing the write voltage and the quantity of loops completed before the write operation was suspended to the memory system based at least in part on the difference between the first quantity and the second quantity being less than the threshold difference.

Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any of aspects 7 through 9 where resuming the performance of the write operation, further includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for providing the write voltage and the quantity of loops completed before the write operation was suspended to a nonvolatile memory device of the memory system based at least in part on the difference between the first quantity and the second quantity being less than the threshold difference.

Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 7 through 10 where determining a first offset associated with the write voltage to apply in response to resuming the write operation and a second offset associated with the quantity of loops to apply in response to resuming the write operation based at least in part on the difference between the first quantity and the second quantity being less than the threshold difference and where resuming the performance of the write operation further includes: resuming the performance of the write operation at the page using the first offset and the second offset.

Aspect 12: The method, apparatus, or non-transitory computer-readable medium of aspect 11 where the first offset and the second offset are based on a characteristic associated with the memory system.

Aspect 13: The method, apparatus, or non-transitory computer-readable medium of any of aspects 7 through 12 where resuming the performance of the write operation, further includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining a third quantity of the first logic state stored in the page based at least in part on determining that a voltage is less than the upper limit of the threshold voltage based at least in part on the difference between the first quantity and the second quantity being greater than the threshold difference.

Aspect 14: The method, apparatus, or non-transitory computer-readable medium of aspect 13 where resuming the performance, further includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining a second difference between the first quantity of the first logic state stored in the page and the third quantity of the first logic state based at least in part on the difference between the first quantity and the second quantity being greater than the threshold difference.