Method and circuit for calculating multiple of unit value and generating a periodic function

In order to generate a multiple of a unit U, N times U, by a digital circuit is provided, where U is a rational number and N is a natural number, the method comprises the following steps (1) to (5). (1) Where A, B and C are natural numbers, A>1, B>C and U=A+C/B, the values A, B and C are stored. (2) A multiple of A, N times A, and a multiple of C, N times C are generated. (3) The multiple of C is compared with the denominator B. (4) The multiple of A is modified according to the result of the comparing step (3). (5) The modified multiple of A is output as the multiple of U.

BACKGROUND OF THE INVENTION

This invention relates to a technique for generating a periodic function based on digital signals and, in particular, to a technique for generating a periodic function with reference to a function table. Such techniques are being used in the fields of, for example, audio, video, or communication signals processing.

According to one of such techniques known by the inventor, a unit angle stored in a register is repeatedly added in order to calculate a multiple of the unit angle and the amplitude of a periodic function corresponding to the multiple is referred to a function table.

Hereinbelow, description will be made with reference toFIG. 1to a periodic function generating circuit based on such technique. First, a unit angle U, which is added to a multiple of the unit angle generated at previous clock, is stored in a register. Next, the unit angle U is added to a multiple S1of the unit angle U currently stored in an accumulator by an adder. Then, an updated multiple S2=S1+U is stored in the accumulator. After that, an amplitude corresponding to the updated multiple S2is referred to a function table previously stored in a function table ROM. These steps are repeatedly executed to generate a series of amplitude values, and finally, the periodic function shown inFIG. 2is generated.

According to the periodic function generating circuit, when the unit angle U is a mixed number, namely the sum of an integer and a fraction, each fraction of the multiples S1, S2, . . . , Snis dropped. Consequently, error of the multiple Sngradually stacks up and increases. Furthermore, a repeating decimal is unavailable for the unit angle U because of its indefinite digits. If it is intended to set the sum of an integer and a repeating decimal as the unit angle U, the sum of the integer and an approximate value of the fraction is actually set as the unit angle U. In this case, the multiple Snincludes an inevitable margin of error, This error is independent of the calculating accuracy of the adder.

As shown inFIG. 3, stacking of errors of the multiple Sncauses phase difference between theoretical and output waveforms. The theoretical waveform drawn as a dotted line shows calculated one in theory. The output waveform drawn as a solid line shows one actually output from the periodic function generating circuit. It is noted that, as time passes, the phase difference stacks up and increases.

In order to restrict amount of the phase difference, the accumulator may be reset. In this case, a permitted limit of the phase difference is predetermined. When the multiple Snstored in the accumulator is about to reach at the permitted limit, the accumulator is reset and the value stored in the accumulator is updated to zero. However, this causes discontinuity of phase at the reset point. As shown inFIG. 4, though the phase difference between the theoretical and output waveforms is canceled, the output waveform before the reset point is separated from the output waveform after the reset point nevertheless. Recently, considerable ones of digital circuit systems require strict management of phase for a long time. Therefore, to reset the accumulator is inappropriate for such recent systems.

Techniques related to the present invention are, for example, described in a Japanese Patent Publication (JP-B) No. H 7-43620, namely 43620/1995, and Japanese unexamined patent publications JP-A) numbers 2000-215029 and 200-196690, namely 215029/2000 and 196690/12000, respectively.

SUMMARY OF THE INVENTION

The present invention is made on the background mentioned above and provides methods and devices for generating a multiple of a unit U and for generating a dependent variable of a periodic function whose independent variable is a multiple of a unit U.

According to one aspect of the invention, a unit U is separated an integer and a fraction. For example, the digital circuit for generating a dependent variable of a periodic function comprises an integer integrating section and a fraction integrating section.

The integer integrating section generates a periodic function of a multiple of the integer of a unit. The fraction integrating section generates a multiple of the fraction in order to add one to the output of the integer integrating section when the multiple of the fraction is equal to or larger than one.

In the fraction integrating section, the fraction is operated as a fractional expression, not as a decimal fraction. Therefore, the sum of an integer and a repeating decimal can be operated in the digital circuit without an approximation. The difference between the theoretical and output waveforms is held to a minimum.

According to another aspect of the invention, a method of generating a multiple of a unit U, N times U, by a digital circuit is provided, where U is a rational number and N is a natural number. The method comprises the following steps (1) to (5). (1) Where A, B and C are natural numbers, A>1, B>C and U=A+C/B, the values A, B and C are stored, (2) A multiple of A, N times A, and a multiple of C, N times C are generated. (3) The multiple of C is compared with the denominator B. (4) The multiple of A is modified according to the result of the comparing step (3). (5) The modified multiple of A is output as the multiple of U.

According to the method, a unit U is divided between an integer A and a fraction C/B, and a multiple of the integer and a multiple of the fraction are generated independently of each other. Consequently, the method can restrain at a minimum the difference between a multiple of a unit U theoretically calculated and a multiple of the unit U generated by the digital circuit.

When the result of the comparing step (3) is that the multiple of C is equal to or larger than the denominator B, the modifying step (4) may comprise the following steps (6) and (7). (6) The multiple of A is modified. (7) The denominator B is subtracted from the multiple of C.

Alternatively, when the result of the comparing step (3) is that the multiple of C is equal to or larger than a value MB, where M is a predetermined natural number, the modifying step (3) may comprise the following steps (8) and (9). (8) The multiple of A is modified. (9) The value MB is subtracted from the multiple of C.

In particular, it is notable that the C/B can represent a repeating decimal.

According to another aspect of the invention, a method of generating a dependent variable of a periodic function whose independent variable is a multiple of a unit U, N times U, by a digital circuit, where U is a rational number and N is a natural number is provided. The method comprises the following steps (10) to (14). (10) Values A, B and C are stored, where A, B and C are natural numbers, A>1, B>C and U=A+C/B. (11) A multiple of A, N times A, and a multiple of C, N times C are generated. (12) The multiple of C is compared with the denominator B. (13) The multiple of A is modified according to the result of the comparing step (12). And (14) a value corresponding to the modified multiple of A is extracted from a function table as the dependent variable corresponding to the multiple of U. The function table represents relationship between the dependent and independent variables of the periodic function and is previously stored in a memory device.

When the result of the comparing step (12) is that the multiple of C is equal to or larger than the denominator B, the modifying step (13) may comprise the following steps (15) and (16). (15) The multiple of A is modified. (16) The denominator B is subtracted from the multiple of C.

Alternatively, when the result of the comparing step (12) is that the multiple of C is equal to or larger than a value MB, where M is a predetermined natural number, the modifying step (13) may comprise the following steps (17) and (18). (17) The multiple of A is modified. (18) The value MB is subtracted from the multiple of C.

In particular, it is notable that the C/B can represent a repeating decimal.

According to another aspect of the invention, a digital circuit for generating a multiple of a unit U, N times U; where U is a rational number and N is a natural number is provided. The digital circuit comprises first, second and third registers, first and second calculating circuits, a subtractor, and a modifying circuit. The first, second and third registers store values A, B and C, respectively, where A, B and C are natural numbers, A>1, B>C and U=A+C/B. The first and second calculating circuits generate a multiple of A, N times A, and a multiple of C, N times C, respectively. The subtractor generates a difference between the multiple of C and the denominator B. The modifying circuit modifies the multiple of A according to the output of the subtractor. The first calculating circuit outputs the modified multiple of A as the multiple of U.

The first calculating circuit may comprise an accumulator and an adder that adds the value stored in the first register to the value stored in the accumulator. In this case, the modifying circuit directs the adder to add +1 to its output when the output of the subtractor represents that the multiple of C is equal to or larger than the denominator B.

The first calculating circuit may comprise an accumulator and an adder. In this case, the modifying circuit may comprise an adjusting circuit for adjusting the value stored in the first register with reference to a predetermined value, and a selector for selecting one of the outputs of the adder and the adjusting circuit according to the output of the subtractor. Alternatively, the modifying circuit may comprise a fourth register for storing a value that is different from the value A, and a selector for selecting one of the values stored in the first and fourth registers according to the output of the subtractor. The adder adds the value stored in the accumulator to the output of the selector.

In particular, it is notable that the C/B can represent a repeating decimal.

According to another aspect of the invention, a digital circuit for generating a dependent variable of a periodic function whose independent variable is a multiple of a unit U, N times U, where U is a rational number and N is a natural number is provided. The digital circuit comprises first, second and third registers, first and second calculating circuits, a subtractor, a modifying circuit and a memory device. The first, second and third registers store values A, B and C respectively, where A, B and C are natural numbers, A>1, B>C and U=A+C/B. The first and second calculating circuits generate a multiple of A, N times A, and a multiple of C, N times C, respectively. The subtractor generates a difference between the multiple of C and the denominator B. The modifying circuit modifies the multiple of A according to the output of the subtractor, The memory device stores a function table which represents relationship between the dependent and independent variables of the periodic function, and outputes a value corresponding to the modified multiple of A on the function table as the dependent variable corresponding to the multiple of U.

The first calculating circuit may comprise an accumulator and an adder that adds the value stored in the first register to the value stored in the accumulator. In this case, the modifying circuit directs the adder to add +1 to its output when the output of the subtractor represents that the multiple of C is equal to or larger than the denominator B.

The first calculating circuit may comprise an accumulator and an adder. In this case, the modifying circuit may comprise an adjusting circuit for adjusting the value stored in the first register with reference to a predetermined value, and a selector for selecting one of the outputs of the adder and the adjusting circuit according to the output of the subtractor. Alternatively, the modifying circuit may comprise a fourth register for storing a value that is different from the value A, and a selector for selecting one of the values stored in the first and fourth registers according to the output of the subtractor. The adder adds the value stored in the accumulator to the output of the selector.

In particular, it is notable that the C/B can represent a repeating decimal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Description will be made about a basic idea of the present invention with reference to a first embodiment of the present invention, a periodic function generating circuit100. As shown inFIG. 5, the periodic function generating circuit100includes an integer integrating section110, a fraction integrating section120and a function table ROM1. The function table ROM1stores a function table represents relationship between dependent variables and independent variables of a periodic function.

According to the periodic function generating circuit100, each of dependent variables of a periodic function are generated as a multiple of a unit U, namely, N times U, where U is a rational number and N is a natural number.

Previously, the unit U is transformed into a sum of a natural number A and a fractional expression C/B, where values B and C are natural numbers.

In order to generate a multiple of the unit U, the integer integrating section110generates a series of multiples A,2A, . . . , NA, . . . and the fraction integrating section120synchronously generates a series of multiples C,2C, . . . , NC, . . . .

When the multiple of C is equal to or larger than a predetermined natural number, the fraction integrating section120directs the integer integrating section110to modify the corresponding multiple of A. In this case, the integer integrating section110outputs modified multiple of A as a multiple of the unit U.

On the other hand, when the multiple of C becomes less than the predetermined natural number, the integer integrating section110outputs the multiple A as a multiple of the unit U without modification.

In response to the multiple of the unit U, the function table ROM1outputs a independent variable corresponding to the multiple of the unit U.

Next, detailed description will be made about the first embodiment of the present invention, the periodic function generating circuit100.

The integer integrating section110includes a register2, an adder3and an accumulator4. The adder3usually generates a sum of a value stored in the register2and a value stored in the accumulator4, and updates the value stored in the accumulator4to the sum at every clock timing. The value stored in the accumulator4is provided to the function table ROM1in order to output the value corresponding to the value stored in the accumulator4.

The fraction integrating section120generates a multiple of the fraction of the unit U. The fraction is a number that can be represented in a fractional expression. When the multiple of the fraction is equal to or larger than a predetermined integer, the fraction integrating section120outputs a modification signal to the integer integrating section110.

The modification signal directs the integer integrating section110to modify the dependent variable. For example, when the multiple of the fraction is less than one, the adder3adds a value stored in the register2and a value stored in the accumulator4. On the other hand, when the multiple of the fraction is equal to or larger than one, the adder3adds a value stored in the register2, a value stored in the accumulator4and +1.

As a result, the integer integrating section110outputs a modified multiple of the unit U when the multiple of the fraction is equal to or larger than one, or outputs the multiple of the unit U when the multiple of the fraction is less than one. Consequently, errors of the dependent variables output by the periodic function generating circuit100can be restricted within the minimum bit available for the register2.

In this manner, the fraction integrating section120, which characterizes this embodiment, generates the modification signal to the integer integrating section110when phase difference between theoretical and generated waveforms grows equal to or larger than the minimum bit. Consequently, according to the periodic function generating circuit100, stack of the phase difference is avoidable.

Operation of the fraction integrating section120will be further described below with reference to FIG.6and FIG.7.

Previously, the unit U is expressed as a sum of an integer A and a fraction C/B that is less than one, where U is a rational number, A, B and C are natural numbers. The denominator B is set to the register5, the numerator C is set to the register7, and the accumulator10is reset (STEP S1). It is assumed that the denominator B=34 and the numerator C=5 to draw each rectangular wave shown in FIG.7. Numerals0,1,2, . . . ,19are given above rectangular pulses of the clock signal as a matter of convenience. Hereinafter, clock timings when rectangular pulses rise are called as 0th clock, 1st clock, 2nd clock, . . . , 19th clock.

The adder8adds the numerator C stored in the register7and the value stored in the accumulator10(STEP S2). The numerator C is equal to 5 and, at the 1st clock, the accumulator10stores 0. Consequently, the adder8outputs a sum 5+0=5.

On the other hand, the subtractor6subtracts the value stored in the register5from the output of the adder8(STEP S3), The register5stores the denominator B=34. The output of the adder8is 5 at the 1st clock. Consequently, the subtractor6generates the difference 5−34=29 at the 1st clock.

After STEP S3, if the output of the subtractor6is negative, then the output of the adder8is stored in the accumulator10(STEPS S4, S5). In this case, the inverter11outputs zero to the integer integrating section110, but does not output the modification signal.

While the subtractor6outputs negative at STEP S4, a loop operation between STEP1to5is repeatedly performed every clock. In the loop operation, the accumulator10stacks up the numerator C. The loop operation is performed from the 1st to 6th clocks in FIG.7. In these clocks, the accumulator10is stacking up the numerator C and stores0,5,10, . . . ,30one after another, as errors for generating a multiple of unit U.

After repeating the loop operation STEPS S1˜S5several times, the output of the adder8exceeds the denominator B stored in the register5and the output of the substractor6turns to positive. This means that the multiple of the fraction is larger than one. In this case, the selector9selects the subtractor6, instead of the adder8, in order to store the output of the subtractor6to the accumulator10(STEPS S4, S6). At the 7th clock inFIG. 7, since the adder8outputs 35, the subtractor6outputs 35−34=1>0. Simultaneously, the inverter11provides the modification signal to the integer integrating section110(STEP S7).

Next, operation of the integer integrating section110will be further described below with reference toFIG. 5, FIG.7and FIG.8.

First, the integer A is set to the register2and the accumulator4is reset (STEP T1). In the timing chart shown inFIG. 7, the integer A is 7 and the register2stores 7. The integer integrating section110performs the following operation every clock.

When the modification signal is not sent from the fraction integrating section120(STEP T2), the adder3generates a sum of the value stored in the register2and the value stored in the accumulator4(STEP T3), and updates the accumulator4to the sum (STEP T4). Since the register2stores 7 and the accumulator4stores zero at the 1st clock inFIG. 7, the adder3outputs 7+0=7. From the 2nd to 6th clock, the value stored in the accumulator4increases 7 per one clock.

On the other hand, when the modification signal is sent from the fraction integrating section120(STEP T2), the adder3generates a sum of the value stored in the register2, the value stored in the accumulator4, and a modifier (STEP T5). The modifier is predetermined as a natural number that is added at STEP T5in order to adjust the sum generated by the adder3.

In the case of this embodiment, the modifier is 1. For example, as shown inFIG. 7, the accumulator4stores 42 at the 6th clock. Therefore, the adder3generates the sum of 7+42+1=50 at the 7th clock. From the 1st to 6th clock, the value stored in accumulator4gains +7. On the other hand, at the 7th clock, the value gains +8. The modification mentioned above corrects error of the multiple of the unit U.

Accordingly, dependent variables output from the integer integrating section110to the function table ROM1is modified when the amount of the error exceeds one bit. As shown inFIG. 9, if the amount first exceeds one bit at a k-th clock (k is a natural number, and for example, is 7th clock in FIG.7), then from 1st to (k-1)th clock, the fraction integrating section120does not output the modification signal, and the integer integrating section110repeatedly generates a sum of the sum generated at previous clock and the value A. Further, at k-th clock, the fraction integrating section120outputs the modification signal to the integer integrating section110, and in response to the modification signal, the integer integrating section110generates a sum of the sum generated at previous clock and the integer A+1. Therefore, dependent variables referred by the function table ROM1is modified when the amount of the error exceeds one bit. Consequently, the periodic function generating circuit100can avoid stack of phase difference as shown in FIG.3and discontinuity of phase as shown in FIG.4.

In the periodic function generating circuit100, instead of immediately generating a multiple of a rational number, first, the rational number is expressed as a sum of an integer and a fraction which is less than one, next, a multiple of the integer and a multiple of the numerator of the fraction are generated, then the multiple of the integer is modified according to the multiple of the fraction and output as the multiple of the rational number.

Each of the multiple of the integer and the multiple of the numerator is free from errors. Therefore, the periodic function generating circuit100can generate the multiple of the rational number, namely a dependent variable, with error less than one.

Further, the integer is modified when the multiple of the fraction becomes larger than natural numbers. Therefore, the periodic function generating circuit100can avoid discontinuity of phase. Consequently, the periodic function generating circuit100can generate a periodic function with high accuracy for a long time.

Next, description will be made about a second embodiment of the present invention, a periodic function generating circuit200with reference to FIG.10.

According to the periodic function generating circuit100, the inverter11generates the modification signal when the multiple of the fraction becomes larger than a natural number. On the other hand, according to the periodic function generating circuit200, a flag generator21generates the modification signal when the multiple of the fraction becomes larger than a multiple of a natural number. For example, the flag generator21generates the modification signal when the multiple of the fraction becomes larger than 2, 4, 6, . . . if the natural number is two. In another embodiment, a multiple of another natural number, instead of the multiple of two, may be available for comparing with the multiple of the fraction.

According to the first embodiment, when the modification signal occurs, the adder3adds the modifier to a sum of the integer A and the value stored in the accumulator4at previous clock. On the other hand, according to the periodic function generating circuit200, a modification circuit20modifies the integer A in accordance with the output of the flag generator21. Then the adder3adds the modified integer A to the value stored in the accumulator4at previous clock. The modification circuit20executes addition or subtraction between the integer A stored in the register2and a modifier set from outside of the modification circuit20The modifier is referred when the modification signal occurs.

The amount of the modifier is decided according to the natural number whose multiple compared with the multiple of the fraction in order to generate the modification signal by the flag generator21.

Further, according to the periodic function generating circuit100, the modification signal is input to the adder3. On the other hand, according to the periodic function generating circuit200, the flag generator21generates modification signals and inputs the modification signal to the modification circuit20and a selector22. The selector22selects one of the outputs from the register2and from the modification circuit20in accordance with the modification signal.

As mentioned above, the periodic function generating circuit200modifies the multiple of the integer A when a multiple of the numerator C becomes larger than a multiple of two. As shown inFIG. 7, the inverter11generates a modification signal at 7th and 14th clocks. On the other hand, as shown inFIG. 11, the flag generator21generates a modification signal only at 14th clock.

At 14th clock inFIG. 11, the modification circuit20generates a sum of the integer A and the modifier (7+2=9), and the adder3adds the sum to the value stored in the accumulator4at the previous clock (91+9=100). Therefore, the value stored in the accumulator4grows 49−42=7 at 7th clock, and on the other hand, grows 100−91=9 at 14th clock.

Consequently, the periodic function generating circuit200generates a periodic function as shown in FIG.12. This shows that the second embodiment is useful when frequency of modification should be low.

Next, description will be made about a third embodiment of the present invention, a periodic function generating circuit300with reference to FIG.13.

According to the second embodiment, the modification circuit20generates the modified integer A at every clock when the modification signal occurs. If the frequency of the modification signal is predetermined, the amount of the modified integer A can thereby be predetermined and be fixed.

The periodic function generating circuit300includes a register30, instead of the modification circuit20. The register30stores the modified integer A The adder3receives the alternative of the integer A stored in the register2and the modified integer A stored in the register30. The alternative is selected by a selector22according to the inverter11. The periodic function generating circuit300includes the fraction integrating section120, which is the same one included in the periodic function generating circuit100. Therefore, one modification signal occurs when a multiple of the fraction is larger than a natural number.

According to the periodic function generating circuit100, the modified integer A is always larger than the integer A. On the other hand, according to the periodic function generating circuit300, the modified integer A is either smaller or larger than the integer A.

If the periodic function generating circuit300included the fraction integrating section220instead of the fraction integrating section120, the selector22would output the modified integer A when a multiple of the numerator C becomes larger than a multiple of two. In this case, the modified integer A stored in the register30should be decided in consideration to the frequency of the modification signal.

While this invention has thus far been described in conjunction with a few embodiments thereof, it will be readily possible for those skilled in the art to put the this invention into various other manners.