Backside via with a low-k spacer

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped structure extending from a front side of a substrate, recessing a source region of the fin-shaped structure to form a source opening, forming a semiconductor plug under the source opening, exposing the semiconductor plug from a back side of the substrate, selectively removing a first portion of the substrate without removing a second portion of the substrate adjacent to the semiconductor plug, forming a backside dielectric layer over a bottom surface of the workpiece, replacing the semiconductor plug with a backside contact, and selectively removing the second portion of the substrate to form a gap between the backside dielectric layer and the backside contact. By forming the gap, a parasitic capacitance between the backside contact and an adjacent gate structure may be advantageously reduced.

BACKGROUND

For example, as integrated circuit (IC) technologies progress towards smaller technology nodes, multi-gate devices are introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure, or portion thereof, disposed over more than one side of a channel region. Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. A FinFET has an elevated channel wrapped by a gate on more than one side (for example, the gate wraps a top and sidewalls of a “fin” of semiconductor material extending from a substrate). An MBC transistor has a gate structure that can extend, partially or fully, around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel regions, an MBC transistor may also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor. The channel region of an MBC transistor may be formed from nanowires, nanosheets, other nanostructures, and/or other suitable structures. The shapes of the channel region have also given an MBC transistor alternative names such as a nanosheet transistor or a nanowire transistor.

As the dimensions of the multi-gate devices shrink, packing all contact features on one side of a substrate is becoming more and more challenging. To ease the packing density, routing features may be moved to a backside of the substrate. Such routing features may include backside power rails or backside contacts. Capacitance between the backside contacts and adjacent gate structures may impact device performance. Therefore, while existing backside power rail formation processes may be generally adequate for their intended purposes, they are not satisfactory in all aspects.

DETAILED DESCRIPTION

The present disclosure is generally related to methods of forming a semiconductor device having a backside source/drain contact, and more particularly to methods of forming a backside source/drain contact that is spaced apart from adjacent structures by a gap.

Source/drain contacts and gate contacts of transistors on a substrate connect source/drain features of the transistors to an interconnect structure over a front side of the substrate. As the dimensions of IC devices shrink, the close proximity among the source/drain contacts and gate contacts may reduce process windows for forming these contacts and may increase parasitic capacitance among them. Backside power rail (BPR) structure is a modern solution to ease the crowding of contacts. In some contact schemes, backside source/drain contacts may be formed from a back side of the substrate and is coupled to a backside power rail. Due to proximity to adjacent gate structure, parasitic capacitance may exist between the backside source/drain contact and the gate structure. Such parasitic capacitance may impact device performance and reduce switching speed.

The present disclosure provides a method for forming a backside source/drain contact that is spaced apart from adjacent structures by a gap. In an exemplary method, a workpiece is received with its front side facing up. The workpiece includes a source feature and a drain feature over a substrate, a plurality of channel members disposed between the source feature and the drain feature, a gate structure wrapping around the plurality of channel members, and a sacrificial plug disposed in the substrate and directly under the source feature. After flipping over the workpiece and after exposing the sacrificial plug, a hard mask is formed directly over the sacrificial plug and a first portion of the substrate laterally adjacent to the sacrificial plug. The rest of the substrate not covered by the hard mask is replaced by a backside dielectric layer. The sacrificial plug is then replaced by a backside source contact, and the first portion of the substrate is removed to form a gap to space apart the backside source contact from the backside dielectric layer. By forming the gap, the parasitic capacitance between the backside source contact and the gate structure may be advantageously reduced.

The various aspects of the present disclosure will now be described in more detail with reference to the figures. In that regard,FIG.1is a flowchart illustrating method100of forming a semiconductor device according to embodiments of the present disclosure. Method100is described below in conjunction withFIGS.2-23, which are fragmentary cross-sectional views or fragmentary top views of a workpiece200at different stages of fabrication according to embodiments of method100. Method100is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated therein. Additional steps may be provided before, during, and/or after the method100, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method. Not all steps are described herein in detail for reasons of simplicity. Because the workpiece200will be fabricated into a semiconductor device200upon conclusion of the fabrication processes, the workpiece200may be referred to as the semiconductor device200as the context requires. For avoidance of doubts, the X, Y and Z directions inFIGS.2-23are perpendicular to one another and are used consistently throughoutFIGS.2-23. Throughout the present disclosure, like reference numerals denote like features unless otherwise excepted.

Referring toFIGS.1and2, method100includes a block102where a workpiece200is received. The workpiece200includes a substrate201. In an embodiment, the substrate201is a bulk silicon substrate (i.e., including bulk single-crystalline silicon). The substrate201may include other semiconductor materials in various embodiment, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AnnAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof, or other suitable materials. In some alternative embodiments, the substrate201may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. In this depicted embodiment, the substrate201is an SOI substrate and includes a carrier layer202, an insulator layer203on the carrier layer202, and a semiconductor layer204on the insulator layer203. In some embodiments, the semiconductor layer204may be silicon, silicon germanium, germanium, or other suitable materials and may be undoped or unintentionally doped with a very low dose of dopants. In this depicted example, the carrier layer202includes silicon, the insulator layer203includes silicon oxide, and the semiconductor layer204includes silicon (i.e., single-crystalline silicon).

The workpiece200includes a fin-shaped structure205disposed over the substrate201. The fin-shaped structure205extends lengthwise along the X direction and is divided into channel regions205C overlapped by dummy gate stacks210(to be described below), source regions205S, and drain regions205D. In this depicted example, two channel regions205C, one source region205S, and two drain regions205D are shown inFIG.2, but the workpiece200may include more source/drain regions and channel regions. The fin-shaped structure205may be formed from a portion of the semiconductor layer204and a vertical stack of alternating semiconductor layers206and208using a combination of lithography and etch steps. An exemplary lithography process includes spin-on coating a photoresist layer, soft baking of the photoresist layer, mask aligning, exposing, post-exposure baking, developing the photoresist layer, rinsing, and drying (e.g., hard baking). In some instances, the patterning of the fin-shaped structure205may be performed using double-patterning or multi-patterning processes to create patterns having pitches smaller than what is otherwise obtainable using a single, direct photolithography process. The etching process can include dry etching, wet etching, and/or other suitable processes. In the depicted embodiment, the vertical stack of alternating semiconductor layers206and208may include a plurality of channel layers208interleaved by a plurality of sacrificial layers206. Each of the channel layers208may be formed of silicon (Si) and each of the sacrificial layers206may be formed of silicon germanium (SiGe). The channel layers208and the sacrificial layers206may be epitaxially deposited on the substrate201using molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), and/or other suitable epitaxial growth processes.

While not explicitly shown inFIG.2, an isolation feature is also formed around the fin-shaped structure205to isolate the fin-shaped structure205from an adjacent fin-shaped structure. In some embodiments, the isolation feature is deposited in trenches that define the fin-shaped structure205. Such trenches may extend through the channel layers208and sacrificial layers206and terminate in the substrate201. The isolation feature may also be referred to as a shallow trench isolation (STI) feature. In an exemplary process, a dielectric material for the isolation feature is deposited over the workpiece200using CVD, subatmospheric CVD (SACVD), flowable CVD (FCVD), physical vapor deposition (PVD), spin-on coating, and/or other suitable process. Then the deposited dielectric material is planarized and recessed until the fin-shaped structure205rises above the isolation feature. The dielectric material for the isolation feature may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials.

Still referring toFIG.2, the workpiece200also includes dummy gate stacks210disposed over channel regions205C of the fin-shaped structure205. The channel regions205C and the dummy gate stack210also define source regions205S and drain regions205D that are not vertically overlapped by the dummy gate stacks210. Each of the channel regions205C is disposed between a source region205S and a drain region205D along the X direction. Two dummy gate stacks210are shown inFIG.2but the workpiece200may include more dummy gate stacks210. In this embodiment, a gate replacement process (or gate-last process) is adopted where the dummy gate stacks210serve as placeholders for functional gate structures. Other processes and configuration are possible. The dummy gate stack210includes a dummy dielectric layer211, a dummy gate electrode layer212over the dummy dielectric layer211, and a gate-top hard mask layer215over the dummy gate electrode layer212. The dummy dielectric layer211may include silicon oxide. The dummy gate electrode layer212may include polysilicon. The gate-top hard mask layer215may be a multi-layer that includes a silicon oxide layer213and silicon nitride layer214formed on the silicon oxide layer213. Suitable deposition process, photolithography and etching process may be employed to form the dummy gate stack210.

As shown inFIG.2, the workpiece200also includes a gate spacer layer216disposed over the workpiece200. In this depicted example, the gate spacer layer216includes a first gate spacer layer216aand a second gate spacer layer216bdeposited conformally over the workpiece200, including over top surfaces and sidewalls of the dummy gate stacks210and top surfaces of the fin-shaped structure205. The term “conformally” may be used herein for ease of description of a layer having a substantially uniform thickness over various regions. In some implementations, a dielectric constant of the second gate spacer layer216bis greater than that of the first gate spacer layer216a, and the second gate spacer layer216bis more etch resistant than the first gate spacer layer216a. In some embodiments, the first gate spacer layer216amay include silicon oxide, silicon oxycarbide, or a suitable low-k dielectric material. The second gate spacer layer216bmay include silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material. The first gate spacer layer216aand the second gate spacer layer216bmay be deposited over the dummy gate stacks210using processes such as, CVD, SACVD, FCVD, atomic layer deposition (ALD), PVD, or other suitable process.

Referring toFIGS.1and3, method100includes a block104where a source region205S and two drain regions205D of the fin-shaped structure205are recessed to form a source opening218S and two drain openings218D. In some embodiments, the source region205S and drain regions205D of the fin-shaped structures205that are not covered by the dummy gate stack210and the gate spacer layer216are anisotropically etched by a dry etch or a suitable etching process to form source opening218S and two drain openings218D. An exemplary dry etching process may implement an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBr3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. In embodiments represented inFIG.3, the source opening218S and drain openings218D extend through vertical stack of channel layers208and sacrificial layers206. The source opening218S and the drain openings218D may partially extend into the semiconductor layer204of the substrate201. As illustrated inFIG.3, sidewalls of the channel layers208and the sacrificial layers206are exposed in the source opening218S and drain openings218D.

Referring toFIGS.1and4-5, method100includes a block106where inner spacer features220are formed. After the formation of the source opening218S and the drain openings218D, the sacrificial layers206are exposed in the source opening218S and the drain openings218D. As shown inFIG.4, the sacrificial layers206are selectively and partially recessed to form inner spacer recesses219, while the exposed channel layers208are not significantly etched. In an embodiment where the channel layers208consist essentially of silicon (Si) and sacrificial layers206consist essentially of silicon germanium (SiGe), the selective and partial recess of the sacrificial layers206may include use of a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent at which the sacrificial layers206are recessed is controlled by duration of the etching process. After the formation of the inner spacer recesses219, an inner spacer material layer is deposited over the workpiece200, including in the inner spacer recesses219. The inner spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excessive inner spacer material layer over sidewalls of the channel layers208, thereby forming the inner spacer features220as shown inFIG.5. In some embodiments, the etch back process at block106may be a dry etching process and in a way similar to the dry etching process used in the formation of the source opening218S and drain openings218D.

Referring toFIGS.1and6, method100includes a block108where the source opening218S is selectively extended into the semiconductor layer204to form an extended opening226. In some embodiments, a mask film222is deposited over the workpiece200using CVD or ALD and then a photoresist layer224is deposited over the mask film222using spin-on coating or a suitable process. The photoresist layer224is patterned using photolithography process to form a patterned photoresist layer224. The patterned photoresist layer224is then applied as an etch mask in an etching process to pattern the mask film222. As shown inFIG.6, the patterned photoresist layer224and the patterned mask film222cover/protect the drain openings218D while the source opening218S is exposed. An etching process is then performed to extend the source opening218S into the semiconductor layer204to form an extended opening226. In some implementations, the etching process at block108may be a dry etching process and in a way similar to the dry etching process used in the formation of the source opening218S and drain openings218D. In some embodiments, the mask film222may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, or silicon oxycarbide.

Referring toFIGS.1and7, method100includes a block110where a semiconductor plug228is formed in the extended opening226. In some embodiments, operations at block110may include a pre-clean process to remove native oxide and the photoresist layer224. After the pre-clean process, with the mask film222still covering sidewalls of the drain openings218D, the semiconductor plug228may be selectively formed in the extended opening226using molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD)), and/or other suitable epitaxial growth processes. The composition of the semiconductor plug228is different from that of the semiconductor layer204such that the semiconductor layer204may be selectively removed in a subsequent process. For example, when the semiconductor layer204is formed of silicon, the semiconductor plug228may include SiGe, boron-doped silicon (Si:B), phosphorus-doped silicon (Si:P), boron-doped SiGe (SiGe:B), arsenic-doped silicon (Si:As) or other suitable material such that the semiconductor layer204may be selectively removed without substantially etching the semiconductor plug228. In an embodiment, the semiconductor layer204is formed of silicon and the semiconductor plug228is formed of SiGe. After the formation of the semiconductor plug228, the mask film222covering the drain openings218D is selectively removed using a suitable etching process.

Referring toFIGS.1and8, method100includes a block112where a source feature232S is formed in the source opening218S and a drain feature232D is formed in the drain opening218D. In this illustrated example, after removing the mask film222, an epitaxial semiconductor feature230is formed at the bottom of the source opening218S (and over the semiconductor plug228) and at the bottom of the drain openings218D to reduce or substantially prevent a leakage between the to-be-formed source/drain features232S/232D and the semiconductor layer204and/or features to be formed at the backside of the workpiece200. The epitaxial semiconductor feature230may be epitaxially and selectively formed from the exposed top surfaces of the semiconductor layer204or the semiconductor plug228by using an epitaxial process, such as an MBE process, a VPE process, an UHV-CVD process, an MOCVD process, and/or other suitable epitaxial growth processes. A bottom surface of the epitaxial semiconductor feature230generally tracks the shape of the bottom surface of the drain openings218D or the exposed top surface of the semiconductor plug228. Because surfaces of the inner spacer features220are not conducive to epitaxial deposition of the epitaxial semiconductor feature230, the epitaxial semiconductor feature230is formed in a bottom-up fashion from the exposed surface of the substrate201. A cross-sectional view of the epitaxial semiconductor feature230includes a crescent shape. Depending on the conductivity type of the source feature232S, the epitaxial semiconductor feature230may have different compositions. When the source feature232S is n-type, the epitaxial semiconductor feature230may include undoped silicon (Si), phosphorus-doped silicon (Si:P), or arsenic-doped silicon (Si:As). When the source feature232S is p-type, the epitaxial semiconductor feature230may include undoped silicon germanium (SiGe) or boron-doped silicon germanium (SiGe:B).

The source feature232S and the drain feature232D each may be then formed over the epitaxial semiconductor feature230by using an epitaxial process, such as VPE, UHV-CVD, MBE, and/or other suitable processes. The epitaxial process may use gaseous and/or liquid precursors, which interact with the composition of the epitaxial semiconductor feature230. The source feature232S and the drain feature232D are therefore coupled to the channel layers208in the channel regions205C of the fin-shape structure205. Depending on the conductivity type of the to-be-formed transistor, the source feature232S and the drain feature232D may be n-type source/drain features or p-type source/drain features. Exemplary n-type source/drain features may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable material and may be in-situ doped during the epitaxial process by introducing an n-type dopant, such as phosphorus, arsenic, or antimony, or ex-situ doped using a junction implant process. Exemplary p-type source/drain features may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable material and may be in-situ doped during the epitaxial process by introducing a p-type dopant, such as boron or gallium, or ex-situ doped using a junction implant process. In some embodiments, a lightly doped epitaxy semiconductor layer may be formed between the source/drain feature232S/232D and the corresponding epitaxial semiconductor feature230, and a doping concentration of the lightly doped epitaxy semiconductor layer is less than a doping concentration of the source/drain feature232S/232D.

Referring toFIGS.1and9, method100includes a block114where a contact etch stop layer (CESL)234and an interlayer dielectric (ILD) layer236are deposited over the workpiece200. The CESL234may include silicon nitride, silicon oxynitride, and/or other materials known in the art and may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. As shown inFIG.9, the CESL234may be deposited on top surfaces of the source feature232S, the drain features232D, and sidewalls of the gate spacer layer216. The ILD layer236is deposited by a PECVD process or other suitable deposition technique over the workpiece200after the deposition of the CESL234. The ILD layer236may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. In some embodiments, after formation of the ILD layer236, the workpiece200may be annealed to improve integrity of the ILD layer236.

Referring toFIGS.1and10, method100includes a block116where the dummy gate stacks210are replaced with the gate structures240. A planarization process, such a chemical mechanical polishing (CMP) process may be performed to the workpiece200to remove excessive materials and expose top surfaces of the dummy gate electrode layer212in the dummy gate stacks210. With the exposure of the dummy gate electrode layer212, block116proceeds to removal of the dummy gate stacks210. The removal of the dummy gate stacks210may include one or more etching process that are selective to the material in the dummy gate stacks210. For example, the removal of the dummy gate stacks210may be performed using a selective wet etch, a selective dry etch, or a combination thereof. After the removal of the dummy gate stacks210, the sacrificial layers206are selectively removed to release the channel layers208as channel members208in the channel regions205C. The selective removal of the sacrificial layers206may be implemented by a selective dry etch, a selective wet etch, or other selective etching process. In some embodiments, the selective wet etching includes an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture).

The gate structures240are deposited to wrap over the channel members208. Each of the gate structures240includes a gate dielectric layer242and a gate electrode layer244over the gate dielectric layer242. In some embodiments, the gate dielectric layer242includes an interfacial layer disposed on the channel members208and a high-k dielectric layer over the interfacial layer. Here, a high-k dielectric layer refers to a dielectric material having a dielectric constant greater than that of silicon dioxide, which is about 3.9. A low-k dielectric layer refers to a dielectric material having a dielectric constant no greater than that of silicon dioxide. In some embodiments, the interfacial layer includes silicon oxide. The high-k dielectric layer is then deposited over the interfacial layer using ALD, CVD, and/or other suitable methods. The high-k dielectric layer may include hafnium oxide. Alternatively, the high-k dielectric layer may include other high-k dielectrics, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, SrTiO3, BaTiO3, BaZrO, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, (Ba,Sr)TiO3(BST), silicon nitride, silicon oxynitride, combinations thereof, or other suitable material.

The gate electrode layer244is then deposited over the gate dielectric layer242using ALD, PVD, CVD, e-beam evaporation, or other suitable methods. The gate electrode layer244may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, the gate electrode layer244may include titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum aluminum, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, tantalum silicon nitride, copper, other refractory metals, or other suitable metal materials or a combination thereof. Further, where the semiconductor device200includes n-type transistors and p-type transistors, different gate electrode layers may be formed separately for n-type transistors and p-type transistors, which may include different work function metal layers (e.g., for providing different n-type and p-type work function metal layers).

Referring toFIGS.1and11, method100includes a block118where a first interconnect structure246is formed over the workpiece200. In some embodiments, the first interconnect structure246may include multiple intermetal dielectric (IMD) layers and multiple metal lines or contact vias in each of the IMD layers. In some instances, the IMD layers and the ILD layer236may share similar composition. The metal lines and contact vias in each IMD layer may be formed of metal, such as aluminum, tungsten, ruthenium, or copper. In some embodiments, the metal lines and contact vias may be lined by a barrier layer to insulate the metal lines and contact vias from the IMD layers and to prevent electro-migration. Because the first interconnect structure246is formed over the front side of the workpiece200, the first interconnect structure246may also be referred to as a frontside interconnect structure246.

Referring toFIGS.1and12, method100includes a block120where a carrier substrate250is bonded to the first interconnect structure246and the workpiece200is flipped over and planarized to expose the semiconductor plug228. In some embodiments, the carrier substrate250may be bonded to the workpiece200by fusion bonding, by use of an adhesion layer, or a combination thereof. In some instances, the carrier substrate250may include semiconductor materials (such as silicon), sapphire, glass, polymeric materials, or other suitable materials. In embodiments where fusion bonding is used, the carrier substrate250includes a bottom oxide layer and the first interconnect structure246includes a top oxide layer. After both the bottom oxide layer and top oxide layer are treated, they are placed in plush contact with one another for direct bonding at room temperature or at an elevated temperature. Once the carrier substrate250is bonded to the first interconnect structure246of the workpiece200, the workpiece200is flipped over. The back side of the workpiece200is then planarized to remove the carrier layer202, the insulator layer203, and a portion of the semiconductor layer204to expose the semiconductor plug228. As shown inFIG.12, the semiconductor layer204of the substrate201is disposed over the channel members208.

Referring toFIGS.1and13, method100includes a block122where the semiconductor plug228and the substrate201are partially and selectively etched to form a cap recess252. The cap recess252may be formed by performing one or more selective dry etching processes, one or more selective wet etching processes, and/or combinations thereof. In this present embodiment, a wet etching process is implemented to selectively remove an upper portion228aof the semiconductor plug228. By adjusting the concentration of the etchant implemented in this wet etching process, a first portion204aof the semiconductor layer204around the upper portion228aof the semiconductor plug228is also intentionally removed. It is noted that, the etchant solution etches the upper portion228aof the semiconductor plug228at a first rate greater than a second rate associated with the etching of the first portion204aof the semiconductor layer204.

In this depicted example, the semiconductor layer204is formed of silicon, the semiconductor plug228is formed of silicon germanium, and the wet etching process implements an etchant solution that includes a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O). The extent at which the semiconductor plug228is recessed may be controlled by duration of the etching process. In an embodiment, a concentration of the hydrogen peroxide (H2O2) in the etchant solution may be between about 5% and about 10% to intentionally remove the first portion204aof the semiconductor layer204. The process temperature may be between about 50° C. and about 60° C. It is noted that, due to the selection of the mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) and due to the lattice structure of silicon, the etchant solution etches silicon more slowly along the <111> crystal orientation than all the other crystal orientations (e.g., <110>, <100>) in the lattice. As a result, the partially etched semiconductor layer204(may also be referred to as semiconductor layer204′) includes a second portion204bhaving a curved surface204sand a third portion204chaving a substantially flat surface204t. After performing the wet etching process, the cap recess252that is defined by a top surface228tof the partially etched semiconductor plug228(may also be referred to as semiconductor plug228′) and the curved surface204sis formed. Other suitable chemicals that have a high selectivity between the semiconductor plug228and the semiconductor layer204may also be used to selectively etch the semiconductor plug228to form the cap recess252. It is noticed that, by employing the selective wet etching process, the cap recess252is formed without employing a lithography process.

In some implementations, other methods may be employed to form the cap recess252. For example, a first dry etching may be implemented to selectively recess the semiconductor plug228to form the semiconductor plug228′ without significantly etching the semiconductor layer204. The first dry etching process forms an opening with a uniform width along the Z direction. A bottom anti-reflective coating (BARC) layer may be deposited over the workpiece200. The BARC layer is then etched back (e.g., by a blanket etch) to expose the first portion204aof the semiconductor layer204while the semiconductor plug228′ is still protected by the BARC layer. A second dry etching may be then performed to remove the first portion204aof the semiconductor layer204to enlarge the opening to form the cap recess252. It is understood that, due to different characteristics of different etching processes, the shape of a cross-sectional view of the cap recess252may be slightly different, and cap recess252would still expose a satisfactory portion of the semiconductor layer204adjacent to the semiconductor plug228′.

Referring toFIGS.1and14, method100includes a block124where a self-aligned dielectric cap254is formed in the cap recess252. The formation of the dielectric cap254may include depositing a dielectric material on the workpiece200to fill the cap recesses252. The dielectric material may be deposited using high-density-plasma CVD (HDPCVD), PECVD, ALD, or a suitable deposition process. The dielectric material may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, or combinations thereof. A planarization process, such as a chemical mechanical planarization (CMP) process, may follow to remove excessive dielectric material over the surface204t, define a final shape of the dielectric cap254, and provide a planar surface. The dielectric cap254tracks the shape of the cap recess252. That is, the dielectric cap254includes a bottom surface in direct contact with the top surface228tof the semiconductor plug228′, a curved sidewall in direct contact with the curved surface204s, and a planar top surface254t. A center line (not shown) of the dielectric cap254aligns with a center line (not shown) of the semiconductor plug228′.

The top surface228tof the semiconductor plug228′ (and thus the bottom surface of the dielectric cap254) has a width W1along the X direction. The top surface254tof the dielectric cap254has a width W2along the X direction and is greater than W1. When viewed from the Y direction, besides being directly disposed over the semiconductor plug228′, the dielectric cap254is also disposed directly over the second portion204bof the semiconductor layer204′ that is laterally adjacent to and around the semiconductor plug228′. The distance between the edge of the top surface254tof the dielectric cap254and the sidewall of the semiconductor plug228′ is marked as W3, W3is equal to one half of the width difference between W2and W1. In other words, W3is equal to (W2−W1)/2. The dielectric cap254also has a thickness T1along the Z direction. In some instances, in order for the dielectric cap254to withstand the etching at block126, W1is between about 15 nm and about 25 nm, W2is between about 25 nm and about 35 nm, W3is between about 4 nm and about 6 nm, and T1is between about 10 nm and about 20 nm.

Referring toFIGS.1and15, method100includes a block126where the semiconductor layer204′ not covered by the dielectric cap254is selectively removed to form a dielectric opening256. In some embodiments, after the formation of the dielectric cap254, the third portion204cof the semiconductor layer204′ may be selectively removed to form the dielectric opening256by a selective etching process, such as a selective wet etching process or a selective dry etching process. An exemplary selective dry etching process may implement CF4, NF3, Cl2, HBr, other suitable gases and/or plasmas, and/or combinations thereof. As shown inFIG.15, the selective removal at block126does not substantially damage the semiconductor plug228′. The second portion204bof the semiconductor layer204′ under the dielectric cap254may be slightly etched during the selective removal of the semiconductor layer204′ but largely remains. The slightly etched portion204bof the semiconductor layer204′ may be referred to as the semiconductor layer204b′ or semiconductor liner204b′. The semiconductor liner204b′ extends along the sidewall of the semiconductor plug228′. After the etching process at block126, the semiconductor liner204b′ has a width W4along the X direction. The inner spacer feature220has a width W5along the X direction, and W5is greater than W4. That is, the semiconductor liner204b′ is disposed on inner spacer feature220and is not directly over the gate structure240. Therefore, in a subsequent etching process of removing the semiconductor liner204b′, the gate structure240would not be exposed and damaged. As semiconductor liner204b′ was part of the substrate and was laterally adjacent to the semiconductor plug228′, the semiconductor liner204b′ does not extend over the source feature232S, the semiconductor liner204b′ also steers clear from the source feature232S.

Referring toFIGS.1and16-17, method100includes a block128where a dielectric layer258is formed in the dielectric opening256and over the workpiece200. The dielectric layer258may be deposited over the back side of the workpiece200by FCVD, CVD, PECVD, spin-on coating, or a suitable process. In some instances, the dielectric layer258may include silicon oxide or have a composition similar to that of the ILD layer236. As shown inFIG.16, after the dielectric layer258is formed, the drain features232D are spaced apart from the dielectric layer258by the epitaxial semiconductor feature230. A planarization process, such as a CMP process, may be performed to planarize the back side of the workpiece200, remove excessive dielectric layer258over the dielectric cap254, remove the dielectric cap254, and expose the semiconductor plug228′ and the semiconductor liner204b′.FIG.17depicts an exemplary fragmentary top view of the workpiece200after the planarization process. In this present embodiment, a shape of a top view of the semiconductor plug228′ includes a substantially round shape and has a width W1(or diameter W1) along the X direction. A shape of a top view of the semiconductor liner204b′ includes or resembles a disc shape or a donut shape. The semiconductor liner204b′ has the width W4along the X direction and wraps around the semiconductor plug228′. It is understood that the shape of the top view of the semiconductor plug228′ is not limited to the substantially round shape and the shape of a top view of the semiconductor liner204b′ is not limited to the disc shape.

Referring toFIGS.1and18-20, method100includes a block130where the recessed semiconductor plug228′ is replaced with a backside source contact266. Referring toFIG.18, the semiconductor plug228′ is selectively removed without substantially damaging the dielectric layer258or the semiconductor liner204b′ by performing an etching process. The etching process is stopped when the semiconductor plug228′ is removed and the source feature232S is exposed in a backside source contact opening260from the back side of the workpiece200. The backside source contact opening260has a depth T3along the Z direction. A ratio of the thickness T1(shown inFIG.14) of the dielectric cap254to the depth T3of the backside source contact opening260is between about 0.1 and 0.2 such that the final semiconductor device200would provide a satisfactory backside source contact having a satisfactory height and would provide a satisfactory parasitic capacitance between the to-be-formed backside power rail270(shown inFIG.23) and the gate structure240.

The selective removal of the semiconductor plug228′ is self-aligned. In these embodiments, the selective removal of the semiconductor plug228′ may be performed using a selective wet etching process or a selective dry etching process. In an embodiment, the selective wet etching process employs the etchant solution that includes a mixture of ammonia hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) to selectively remove the semiconductor plug228′. To substantially prevent the semiconductor liner204b′ from being etched during this selective removal at block130, a concentration of the hydrogen peroxide (H2O2) is increased comparing to that of the hydrogen peroxide (H2O2) used in the formation of the cap recess252described with reference toFIG.13. In other words, the hydrogen peroxide (H2O2) at block130has a second concentration greater than a first concentration of the hydrogen peroxide (H2O2) at block122. By increasing the concentration of the hydrogen peroxide, the etch selectively between the semiconductor plug228′ and the semiconductor liner204′ is increased, and the etchant solution with more hydrogen peroxide etches the semiconductor plug228′ at a third rate greater than the first rate associated with the formation of the cap recess252. In some embodiments, the second concentration of the hydrogen peroxide (H2O2) is about 2 to about 5 times of the first concentration of the hydrogen peroxide (H2O2). In an embodiment, the second concentration of the hydrogen peroxide (H2O2) in the etchant solution may be between about 10% and about 30%. In some embodiments, the process temperature at block130may be between about 60° C. and about 70° C. and is higher than the process temperature at block122.

As shown inFIG.19, after the formation of the backside source contact opening260, in some embodiments, a dielectric barrier layer262is deposited over the workpiece200and is then etched back to only cover sidewalls of the backside source contact opening260and expose the source feature232S. The backside source contact opening260partially covered by the dielectric barrier layer262may be referred to as backside source contact opening260′. The backside source contact opening260′ has a width W6along the X direction. In the present implementation, a ratio of W3(shown inFIG.14) to W6is between about 0.3 and about 0.4 such that the dielectric cap254may protect enough semiconductor layer204′ from being etched in a subsequent etching process. A ratio of W4(shown inFIG.15) to W6is between about 0.2 and about 0.3 to form a satisfactory gap in the final semiconductor device200.

In some embodiments, the dielectric barrier layer262may include silicon nitride or other suitable materials. The dielectric barrier layer262extends along the semiconductor liner204b′ and disposed directly on the source feature232S. Operations at block130also includes forming a silicide layer264on the exposed surface of the source feature232S to reduce a contact resistance between the source feature232S and the to-be-formed backside source contact266. To form the silicide layer264, a metal layer (not explicitly shown) is deposited over the exposed surfaces of the source feature232S and an anneal process is performed to bring about silicidation reaction between the metal layer and the source feature232S. Suitable metal layer may include titanium, tantalum, nickel, cobalt, or tungsten. In embodiments where the metal layer includes nickel and the source feature232S includes silicon germanium, the silicide layer264includes nickel silicide, nickel germanide, and nickel germanosilicide. The silicide layer264generally tracks the shape of the exposed source feature232S. Excessive metal layer that does not form the silicide layer264may be removed.

As shown inFIG.20, after the formation of the silicide layer264, the backside source contact266may be formed in the backside source contact opening260′ and has a width W6. The backside source contact266may include aluminum, rhodium, ruthenium, copper, iridium, or tungsten. A planarization process, such as a CMP process, may follow to remove excessive materials and provide a planar surface. The backside source contact266is electrically coupled to the source feature232S by way of the silicide layer264. In other words, the silicide layer264is sandwiched between the source feature232S and the backside source contact266.

Referring toFIGS.1and21-22, method100includes a block132where the semiconductor liner204b′ is selectively removed to form a trench268. In some embodiments, after the formation of the backside source contact266, the semiconductor liner204b′ may be selectively removed using a selective wet etch process or a selective dry etch process to form the trench268. A suitable selective wet etch process or a suitable selective dry etch process may be performed during the selective removal. The selective removal of the semiconductor liner204b′ is self-aligned. When the semiconductor liner204b′ is formed of silicon (Si), a suitable selective dry etching process may include use of CF4, NF3, Cl2, HBr, other suitable gases and/or plasmas, and/or combinations thereof. As shown inFIG.21, the selective removal at block132does not substantially damage the dielectric layer258, the dielectric barrier layer262, or the backside source contact266.

Still referring toFIG.21, the removal of the semiconductor liner204b′ results in a trench268. The trench268tracks the sidewall of the dielectric barrier layer262that is in direct contact with the source feature and is disposed between the dielectric layer258and the dielectric barrier layer262along the X direction. In embodiments where the workpiece200doesn't include the dielectric barrier layer262, the trench268tracks the sidewall of the backside source contact266and is disposed between the dielectric layer258and the backside source contact266along the X direction, and a width W6of the backside source contact266is substantially equal to the width W1of the semiconductor plug228′. As the semiconductor liner204b′ does not extend into the source feature232S, the trench268also steers clear from the source feature232S. After the etching process at block132, a cross-sectional view of the trench268has a width W7along the X direction, a depth T3along the Z direction, and exposes a portion of the inner spacer feature220. That is, the trench268doesn't expose the gate structure240. A ratio of W7to the width W6of the backside source contact266is between about 0.1 and about 0.2 such that the trench268would not be substantially filled in a subsequent dielectric deposition process and a parasitic capacitance between the gate structure240and the backside source contact266may be advantageously reduced without damaging the gate structure240(e.g., induced by the dry etching at the block132) or inducing a threshold voltage shifting. In an embodiment, based on the packing density and the performance demand, the width W7of the trench268is between about 2 nm and about 4 nm. A ratio of the depth T3of the trench268to the depth T2of the backside source contact opening260′ is between about 0.8 and about 0.9 such that the parasitic capacitance between the gate structure240and the backside source contact266may be significantly reduced.

FIG.22depicts an exemplary fragmentary top view of the workpiece200after the formation of the trench268. In this present embodiment, a shape of a top view of the backside source contact266includes a substantially round shape. A shape of a top view of the dielectric barrier layer262includes or resembles a disc shape or a donut shape. The trench268tracks the sidewall of the dielectric barrier layer262and also includes a disc shape or a donut shape. It is understood that the shape of the top view of the backside source contact266is not limited to the substantially round shape and the shape of a top view of the dielectric barrier layer262or the trench268is not limited to the disc shape.

Referring toFIGS.1and23, method100includes a block134where a backside power rail270is formed. While not explicitly shown inFIG.23, the backside power rail270may be embedded in an insulation layer. In an exemplary process, an insulation layer having a composition similar to the ILD layer236may be deposited over the backside of the workpiece200, including over the dielectric layer258, the isolation feature, the backside source contact266, and the trench268. The trench268is thus sealed by the insulation layer. While not explicitly shown inFIG.23, during the deposition of the insulation layer, depending on the dimension of the trench268, a small portion of the insulation layer may penetrate into the upper portion of the trench268. The trench268may also be referred to as a gap268or a void268. The gap268may or may not include gaseous species. When the gap268includes gaseous species, it may also be referred to as an air gap268. Such gaseous species may be remnants of inert or unreacted gaseous species present during the deposition of the insulation layer269. A dielectric constant of the gap may be between about 1 and about 1.1. That is, the dielectric barrier layer262is spaced apart from the dielectric layer258by a low-k spacer (i.e., the gap268). In embodiments where the semiconductor device200doesn't include the dielectric barrier layer262formed in the contact opening260, the backside source contact266is spaced apart from the dielectric layer258by the low-k spacer (i.e., the gap268).

Then, a power rail trench may be patterned in the insulation layer. A barrier layer and a metal fill material are then deposited into the power rail trench to form the backside power rail270. In some embodiments, the barrier layer in the backside power rail270may include titanium nitride, tantalum nitride, cobalt nitride, nickel nitride, or tungsten nitride and the metal fill material in the backside power rail270may include titanium, ruthenium, copper, nickel, cobalt, tungsten, tantalum, or molybdenum. The barrier layer and the metal fill layer may be deposited using PVD, CVD, ALD, or electroless plating. A planarization process, such as a CMP process, may be performed to remove excessive materials over the insulation layer. A second interconnect structure272is formed and has a structure in a way similar to the first interconnect structure246. Because the second interconnect structure272is formed over the back side of the workpiece200, the second interconnect structure272may also be referred to as a backside interconnect structure272.

Embodiments of the present disclosure provide advantages. Methods of the present disclosure form a gap disposed between a backside contact and a backside dielectric layer. Because a dielectric constant of the gap is low, the presence of the gap reduces the parasitic capacitance between the backside contact and an adjacent gate structure. Therefore, performances of the semiconductor structure may be improved. In addition, the methods of the present disclosure use self-align technologies to form the gap with a small dimension without using lithography processes, which significantly reduces the cost associated with the fabrication of the above device.

The present disclosure provides for many different embodiments. Semiconductor structures and methods of fabrication thereof are disclosed herein. In one exemplary aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a top surface and a bottom surface. The workpiece includes a number of channel members disposed over a substrate, a gate structure wrapping around each of the number of channel members, and a source feature adjacent to the number of channel members. The source feature is disposed over a semiconductor plug extending into the substrate. The method also includes flipping over the workpiece, selectively removing a first portion of the substrate without removing a second portion of the substrate adjacent to the semiconductor plug and without substantially damaging the semiconductor plug, forming a backside dielectric layer over the bottom surface of the workpiece, replacing the semiconductor plug with a backside contact, and selectively removing the second portion of the substrate to form a gap between the backside dielectric layer and the backside contact.

In some embodiments, the method may also include, before the selectively removing of the first portion of the substrate, performing a first etching process to etch the semiconductor plug and the substrate to form a recess, and forming a dielectric capping layer in the recess. The first etching process may etch the semiconductor plug at a rate greater than etching the substrate. The dielectric capping layer may be disposed directly over the semiconductor plug and the second portion of the substrate.

In some embodiments, the first etching process may include using a wet etching process to selectively etch the semiconductor plug. In some embodiments, the wet etching process may include use of NH4OH and H2O2. In some embodiments, the dielectric capping layer may include silicon nitride, silicon oxide, or silicon oxynitride.

In some embodiments, the replacing of the semiconductor plug with the backside contact may include performing a second etching process to selectively remove the semiconductor plug without substantially damaging the second portion of the substrate to form a contact opening, and forming the backside contact in the contact opening. In some embodiments, the first etching process and the second etching process may implement an etchant, and a concentration of the etchant in the first etching process may be less than a concentration of the etchant in the second etching process.

In some embodiments, the selectively removing of the first portion of the substrate may include performing a third etching process, the selectively removing of the second portion of the substrate may include performing a fourth etching process, and the third etching process and the fourth etching process may include a dry etching process. In some embodiments, the dry etching process may include implementing CF4, Cl2, NF3, or HBr. In some embodiments, the method may include depositing an interlayer dielectric layer over the gap and forming a backside power rail in the interlayer dielectric layer.

In another exemplary aspect, the present disclosure is directed to a method. The method includes receiving a workpiece including a first active region and a second active region over a substrate, a source feature disposed between the first active region and the second active region along a direction, and a sacrificial plug disposed in the substrate and under the source feature. The method also includes flipping over the workpiece, forming a hard mask directly over the sacrificial plug and a first portion of the substrate laterally adjacent to the sacrificial plug, replacing a second portion of the substrate not covered by the hard mask with a backside dielectric layer, removing the hard mask to expose the sacrificial plug and the first portion of the substrate, replacing the sacrificial plug with a backside contact, and selectively removing the first portion of the substrate to form a gap between the backside dielectric layer and the backside contact.

In some embodiments, the replacing of the second portion of the substrate with the backside dielectric layer may include performing a dry etching process to selectively remove the second portion of the substrate without substantially damaging the hard mask to form an opening and depositing a backside dielectric layer in the opening.

In some embodiments, the method may also include, before the forming of the hard mask, performing a wet etching process to remove a portion of the sacrificial plug and a third portion of the substrate to form a recess that exposes the first portion of the substrate. The third portion of the substrate may be around the portion of the sacrificial plug. The wet etching process may etch the sacrificial plug at a rate greater than etching the substrate.

In some embodiments, the forming of the hard mask may include depositing a hard mask layer in the recess and performing a planarization process to remove excessive hard mask layer over the second portion of the substrate to form the hard mask. In some embodiments, the hard mask may include a top surface away from the sacrificial plug and a bottom surface adjacent to the sacrificial plug, the top surface may be wider than the bottom surface along the direction. In some embodiments, the wet etching process may include implementing ammonium hydroxide and hydrogen peroxide.

In yet another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a number of nanostructures, a source feature coupled to each of the number of nanostructures, a backside source contact disposed over the source feature, a liner disposed along sidewall of the backside source contact, a gate structure wrapping around each of the number of nanostructures, and a backside dielectric layer disposed over the gate structure. The backside source contact is spaced apart from the backside dielectric layer by the liner and a gap.

In some embodiments, the semiconductor device may also include a number of inner spacer features interleaving the number of nanostructures. A width of each of the number of inner spacer features may be greater than a width of the gap. In some embodiments, the semiconductor device may also include an interlayer dielectric layer disposed over a bottom surface of the backside source contact and a backside power rail disposed in the interlayer dielectric layer and electrically connected to the backside source contact. In some embodiments, the gap may wrap around a sidewall of the liner.