Accurate, high drive, zero offset voltage buffer

A low offset voltage buffer which comprises a first, second, third and fourth MOS device, each comprising a gate, a source and a drain; a current source coupled to the drains of the first and second MOS devices; a current sink coupled to the sources of the third and fourth MOS devices; an input coupled to the gate of the third MOS device and an output coupled to the source of the first MOS device. The source of the first MOS device is coupled to the drain of the third MOS device and the source of the second MOS device is coupled to the drain of the fourth MOS device. The voltage buffer can also be implemented in both NMOS and PMOS devices.

FIELD OF THE INVENTION

Embodiments of the present invention relate to the field of semiconductor devices, such as transistors. More specifically, embodiments of the present invention relate to circuit design in analog and hybrid signal processing chips.

BACKGROUND OF THE INVENTION

Modern electronic devices continue to shrink in size as they grow in capability. More and more tasks are being accomplished by fewer and fewer components.

The arena of analog and hybrid signal processing has special demands. Filters, voltage followers, and other analog and hybrid devices require analog functions that are not always easily accommodated in modern shrinking architecture. A limitation found in analog signal processing is the available die area and the power required for high speed operation. In even the best existing designs, filtering accuracy and gain come at the cost of decreasing speed and increasing complexity.

Prior fabrication techniques, too, have been unable to achieve some of the component combinations that help enable some analog and hybrid signal processing. The combination of n-channel and p-channel metal-oxide semiconductor (MOS) devices, especially transistors, has posed special challenges to fabrication.

One attribute associated with transistors is “threshold voltage,” generally defined as the input voltage at which the output logic level of the transistor changes state. Another definition of the term “threshold voltage” is the gate voltage above which the transistor becomes conductive in an enhancement mode field-effect transistor (FET) or nonconductive in a depletion mode FET. The operational speed of a transistor is a function of its threshold voltage. To increase speed, the threshold voltage is decreased. However, there is a tradeoff; with decreased threshold voltage, the drive current and leakage current of the transistors can be increased. Depending on the application of the transistor, a designer must select a particular threshold voltage for the transistor based on many factors, including speed and power consumption.

Types of transistors known in the art include those commonly referred to as NMOS (negative-channel metal-oxide semiconductor) devices and PMOS (positive-channel metal-oxide semiconductor) devices. The threshold voltage of these types of devices is dependent on the original doping concentration of the silicon substrate used as the foundation for forming the transistor.

For PMOS devices, the threshold voltage can be reduced by adjusting the original doping concentration using another, subsequent implantation of dopant into the substrate. In the case in which boron ions (or ions that include boron, such as BF2) are used as the dopant, this latter implantation is sometimes referred to as the “boron adjust.” More generally, it may be referred to as the “threshold adjust.” By adding dopant, particularly a p-type dopant that includes boron, the threshold voltage of a PMOS device is lowered.

As described above, NMOS devices having a particular threshold voltage can be fashioned by specifying the appropriate original doping concentration. However, according to the conventional art, a threshold adjust process for reducing the threshold voltage of such devices is lacking.

With the advent of techniques described in the above referenced application, low threshold NMOS and PMOS devices can be accommodated in a single chip. However, circuit design techniques required for hybrid and analog signal processing have not been developed to exploit low threshold NMOS and PMOS devices in the same chip.

SUMMARY OF THE INVENTION

Accordingly, embodiments of the present invention present a high-accuracy, high-drive, zero-offset, voltage buffer. Some embodiments can also be addressed as unity gain follower circuits. Embodiments have application in analog and hybrid signal processing devices and other applications requiring rapid slewing, at zero offset, following analog signals.

A low offset voltage buffer is presented which comprises a first, second, third and fourth MOS device, each comprising a gate, a source and a drain; a current source coupled to the drains of the first and second MOS devices; a current sink coupled to the sources of the third and fourth MOS devices; an input coupled to the gate of the third MOS device and an output coupled to the drain of the first MOS device. The source of the first MOS device is coupled to the drain of the third MOS device and the source of the second MOS device is coupled to the drain of the fourth MOS device. The voltage buffer can also be implemented in both NMOS and PMOS devices.

Embodiments of the present invention present a low offset follower that is a fast, low power, small area, buffer for use in amplifier output stages and advanced (buffer based) delta sigma modulators, such as used in ADCs; reconstruction filters, used in DACs and switched capacitor, or RC active, filters; and other analog and mixed signal functions. These embodiments of the present invention use an op-amp-free approach to unity gain filters. However, embodiments of the present invention have little or no systematic offset compared with state of the art source-follower buffers. In one embodiment, the low offset follower also gives improved slew rate and drive capability in both directions and low power operation capability compared with these buffers. The speed power product is thus improved compared with existing voltage followers or buffers. Furthermore, embodiments of the present invention employ manufacturing techniques presented in the above reference co-pending applications to efficiently fabricate these circuits in a single, high device density, chip.

These and other objects and advantages of the present invention will become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.

DETAILED DESCRIPTION

This application incorporates herein by reference the co-pending provisional patent application Ser. No. 60/334,139, entitled “Accurate, High Drive, Zero Offset Voltage Buffer (Unity Gain Follower Circuit)”, with filing date Nov. 28, 2001, assigned to the assignee of the present application and hereby incorporated by reference in its entirety. This application also incorporates herein by reference the co-pending patent application, Ser. No. 10/306,414, entitled “Process Providing High and Low Threshold N-Type and P-Type Transistors,” filed concurrently herewith, and assigned to the assignee of the present application.

FIG. 1illustrates a drain follower half circuit implemented in n-channel, metal-oxide semiconductor field-effect transistors (NMOSFETs), according to one embodiment of the present invention. It is noted that such a drain follower circuit can also be implemented in p-channel MOSFETs (PMOSFETs) as illustrated below inFIG. 2, etc.

The circuit illustrated inFIG. 1comprises n-channel MOSFETs101,102,103and104. The drains of MOSFETs101and102are supplied with a balanced current source. The gate of MOSFET102is connected to its drain and its substrate channel is connected to the gate of MOSFET101. The circuit input,120, is connected to the gate of MOSFET103and the circuit output110is connected to the drain of MOSFET103. Because the drain of MOSFET103and the source of MOSFET101are connected, the source of MOSFET101is also connected to the output110. MOSFET104is on the source of MOSFET102and, like MOSFET102, is gate/drain connected. The sources of MOSFETs103and104are connected together and to the current sink108.

The half circuit illustrated inFIG. 1, implemented in n-channel MOSFETs, provides active pull-up through MOSFET101. Active pull-down Is better provided in another embodiment of the present invention, the half circuit illustrated inFIG. 2, which is implemented in p-channel MOSFETS.

InFIG. 2, a common current source208feeds the sources of p-channel MOSFETs201and202. The gate of MOSFET201is coupled to the circuit input,220. The gate of MOSFET202is connected to its drain which is also connected to the source of MOSFET204. The drain of MOSFET201, which connects to the circuit output210, is also connected to the source of MOSFET203. The gate of MOSFET203is connected to the substrate bulk of MOSFET208, whose gate is connected to its drain. The drains of each MOSFET,203and204, connect to balanced current sinks206and207.

FIG. 3illustrates an embodiment of the present invention which uses PMOS and NMOS implementations to achieve good drive as well as fast slewing capability in both directions. The inputs of both half circuits are tied together,310, as are the outputs of both half circuits at320. The PMOS half circuit, comprising PMOSFETs301,302,303and304, provides active pull-down through PMOSFET303. The NMOS half circuit, comprising NMOSFETs311,312,323and314, provides active pull-up through NMOSFET311.

FIG. 3illustrates the “full” circuit implementation300, meaning a circuit employing both NMOS and PMOS half circuits, wherein the well, or substrate, ties are to the sources of the MOSFETs. In other embodiments, the source ties can be to a common substrate. The offset voltages of the MOSFET devices match, so the body effect is not a first order source of error with the embodiments of the present invention described here.

FIGS. 4A,4B,5and6illustrate an implementation of this embodiment of the present invention that provides improved gain accuracy and power supply rejection, according to various embodiments of the present invention. In this high accuracy variation of the present invention, the MOSFETs are implemented in cascode. A cascoded implementation of an NMOS device as illustrated inFIG. 4Aor a PMOS device as shown inFIG. 4B, improves the gain accuracy or the overall follower, and improves power supply rejection.

FIG. 4Aillustrates one implementation,400, of a cascoded NMOS device. NMOSFET402is gate connected,403, to NMOSFET401. NMOSFET401is a low threshold device. Current is supplied,404, to the drain of low threshold NMOSFET401. Current output,405, is via the source of NMOSFET402.

Similarly,FIG. 4Billustrates an implementation,450, of cascoded PMOS device. PMOSFET411is gate connected,413, to PMOSFET412. PMOSFET412is a low threshold device. Current is supplied,415, to the drain of low threshold PMOSFET412. Current output,414, is via the source of PMOSFET411.

InFIG. 5, a cascoded implementation of an NMOS half circuit,500, is illustrated. Cascoded half circuit500is shown with cascoded NMOSFETs in place of NMOS devices as shown in NMOS half circuit implementation100. As shown, each of the four NMOS devices of half circuit100is replaced with cascoded device pair to produce cascoded half circuit500. NMOSFET devices511and521replace NMOSFET101, NMOSFET devices512and522replace NMOSFET102, NMOSFET devices513and523replace NMOSFET103, and NMOSFET devices514and524replace NMOSFET104. While embodiments of the present invention may cascode any of the basic four NMOSFETs, the implementation illustrated inFIG. 5, in which all NMOSFET devices are replaced, provides an accurate unity gain drain follower with active pull-up. Current is supplied to cascoded half circuit500via balanced current supplies at506and507. Current is sunk in sink508. Device input is at510and device output is at520.

Similar to the cascoded device replacement ofFIG. 5,FIG. 6illustrates a cascoded implementation of a PMOS half circuit,600. Cascoded half circuit600is shown with cascoded PMOSFETs in place of PMOS devices as shown in PMOS half circuit implementation200. As shown, each of the four PMOS devices of half circuit200is replaced with cascoded device pair to produce cascoded half circuit600. PMOSFET devices611and621replace PMOSFET201, PMOSFET devices612and622replace PMOSFET202, PMOSFET devices613and623replace PMOSFET203, and PMOSFET devices614and624replace PMOSFET204. While embodiments of the present invention may cascode any of the basic four PMOSFETs, the implementation illustrated inFIG. 6, in which all PMOSFET devices are replaced, provides an accurate unity gain drain follower with active pull-down. Current is supplied to cascoded half circuit600via current source608. Current is sunk in balanced current sinks606and607. Device input is at610and device output is at620.

The cascading detailed above makes each of the circuits allows each circuit to act as a cascoded drain follower. InFIG. 7, the illustration of a full circuit cascoded implementation, all transistors are cascoded by composite N channel or composite P channel devices as shown inFIGS. 4A and 4B. Full cascoded follower circuit700comprises both cascoded NMOS half circuit500and cascoded PMOS half circuit600. The two half circuits are, similar to what is implemented in circuit300, connected together at input710and at output720. Current is supplied at supplies708,716and717. Current is sunk at current sinks706,707and718.

The cascoded implementation of both NMOS and PMOS half circuits provides a very accurate unity gain follower circuit, or buffer. With both NMOS and PMOS devices implemented, rapid, active pull-up and pull-down enable very accurate following. The embodiments of the present invention described here present a low offset follower that is a fast, low power, small area, buffer for use in amplifier output stages and advanced (buffer based) delta sigma modulators, such as used in ADCs; reconstruction filters, used in DACs and switched capacitor, or RC active, filters; and other analog and mixed signal functions. These embodiments of the present invention use an op-amp-free approach to unity gain filters. However, embodiments of the present invention have little or no systematic offset compared with state of the art source-follower buffers. In one embodiment, the low offset follower also gives improved slew rate and drive capability in both directions and low power operation capability compared with these buffers. The speed power product is thus improved compared with existing voltage followers or buffers. Furthermore, embodiments of the present invention employ manufacturing techniques presented in the above reference co-pending applications to efficiently fabricate these circuits in a single, high device density, chip.

Modern chip manufacturing techniques enable implementation of both PMOS and NMOS devices in proximity. By employing both p-channel and n-channel devices in the voltage follower, the advantages of both are put to good use to produce accuracy and speed that are unattainable in conventional analog or hybrid chip implementations.