Horizontal interconnects crosstalk optimization

A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.

BACKGROUND

Various features relate generally to apparatus comprising integrated circuit devices and more particularly to optimizing patterns of interconnects used to connect devices within the apparatus.

In higher speed semiconductor integrated circuit (IC) devices, the layout and configuration of horizontal interconnects, which carry signals to and from ICs mounted on a circuit board or chip carrier, can play a critical role in signal integrity and can limit achievable maximum frequencies associated with the semiconductor device. Signaling rates continue to increase to obtain performance improvements in certain classes of high-speed semiconductor devices. In one example, the Joint Electron Device Engineering Council (JEDEC) standards for consecutive generations of synchronous dynamic random-access memory (SDRAM), including double data rate (DDR) SDRAM typically provide for increases in speed for later generations. One generation of Low Power DDR (LPDDR) SDRAM defined by JEDEC may provide for speeds that are double the speed of one or more preceding generations of LPDDR. Crosstalk between adjacent interconnects increases as signaling rates increase.

Conventionally, semiconductor designers employ intuitive insight in the design of horizontal interconnect patterns, configurations and assignments for coupling high-speed semiconductor devices. This design process is typically iterative and time-consuming, and often yields less than optimal results. Conventional methods for interconnect pattern optimization are not scalable and/or require a-priori knowledge. For instance, some prior art approaches focus on a very small problem size (up to 2 signals only) and cannot generally be scaled to larger interconnect patterns (e.g., to a full DDR interface design). Conventional approaches do not account for variable numbers of signal and power/ground interconnects and gaps that are available for placement between interconnects. In some conventional systems, a-priori knowledge is required including, for example, a-priori knowledge of an inductance matrix in an interconnect pattern when optimizing for simultaneous switching noise.

Therefore, a solution is needed that optimizes interconnect patterns for minimum crosstalk for an arbitrary number of signal and power/ground interconnects.

SUMMARY

In an aspect of the disclosure, a method, a processor-readable storage medium, and an apparatus are provided that may be employed or adapted for optimizing interconnect patterns in a semiconductor device.

In an aspect of the disclosure, a plurality of interconnect patterns is generated for a set of horizontal interconnects. The interconnect patterns may be used for configuring a set of interconnects on one or more layers of a circuit board or chip carrier. Each interconnect pattern may be different from each of the other interconnect patterns. Each interconnect pattern may define a plurality of longitudinal slots. One or more of the longitudinal slots may be occupied by the set of interconnects.

In some embodiments, the set of longitudinal slots comprises at least one unoccupied longitudinal slot. The plurality of interconnect patterns may define pluralities of longitudinal slots provided on at least two substantially parallel planes within the one or more layers of the circuit board. The at least two substantially parallel planes may be provided between two substantially parallel reference planes. Two interconnect patterns may be considered to be different from one another if the two interconnect patterns assign at least one interconnect to different longitudinal slots.

In an aspect of the disclosure, a highest crosstalk is determined for each of the interconnect patterns. The highest crosstalk for the each interconnect pattern may correspond to one of the longitudinal slots. The highest crosstalk for each of the interconnect patterns may be determined for a plurality of frequencies. The highest crosstalk for each of the interconnect patterns may be determined for a range of frequencies. The highest crosstalk may be generated by the corresponding longitudinal slot. The corresponding longitudinal slot may be afflicted by the crosstalk calculated for the pattern of interconnects.

In some embodiments, the highest crosstalk for each of the interconnect patterns is determined by modeling the set of interconnects as microstrip or dual stripline transmission lines and the highest crosstalk for the each interconnect pattern may comprise far-end crosstalk.

In some embodiments, the highest crosstalk for each of the interconnect patterns is determined by modeling the set of interconnects as stripline transmission lines and the highest crosstalk for the each interconnect pattern may comprise near-end crosstalk.

In an aspect of the disclosure, a preferred interconnect pattern is selected from the plurality of interconnect patterns. The preferred interconnect pattern may provide a lower highest crosstalk than the highest crosstalk associated with each of the other interconnect patterns.

In an aspect of the disclosure, a set of horizontal interconnects may be formed on a substrate, chip carrier or circuit board in accordance with the preferred interconnect pattern. The horizontal interconnect pattern may control an arrangement of vertical interconnects that are substantially orthogonal to the one or more layers. The combination of the preferred interconnect pattern and the vertical interconnect pattern may be calculated to provide a lower highest crosstalk associated with the combination than the highest crosstalk associated with other combinations of horizontal and vertical interconnect patterns. The highest crosstalk associated with the combination may relate to crosstalk associated with one of a vertical interconnect or a horizontal interconnect.

In an aspect of the disclosure, an apparatus for optimizing interconnect patterns in a semiconductor device comprises a computer readable medium and a processing system configured to generate a plurality of interconnect patterns, determine a highest crosstalk for each of the interconnect patterns, and select a preferred interconnect pattern from the plurality of interconnect patterns. The plurality of interconnect patterns may be used to configure a set of interconnects on one or more layers of a circuit board. The preferred interconnect pattern may provide a lower highest crosstalk than the highest crosstalk associated with each of the other interconnect patterns. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define a plurality of longitudinal slots including longitudinal slots occupied by the set of interconnects. The highest crosstalk for the each interconnect pattern may correspond to one of the longitudinal slots.

In an aspect of the disclosure, an apparatus for optimizing interconnect patterns in a semiconductor device comprises means for generating a plurality of interconnect patterns, means for determining a highest crosstalk for each of the interconnect patterns, and means for selecting a preferred interconnect pattern from the plurality of interconnect patterns. The plurality of interconnect patterns may be used for configuring a set of interconnects on one or more layers of a circuit board. The preferred interconnect pattern may provide a lower highest crosstalk than the highest crosstalk associated with each of the other interconnect patterns. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define a plurality of longitudinal slots including longitudinal slots occupied by the set of interconnects. The highest crosstalk for the each interconnect pattern may correspond to one of the longitudinal slots.

In an aspect of the disclosure, a processor-readable storage medium has one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to generate a plurality of interconnect patterns, determine a highest crosstalk for each of the interconnect patterns, and select a preferred interconnect pattern from the plurality of interconnect patterns. The plurality of interconnect patterns may be used to configure a set of interconnects on one or more layers of a circuit board. The preferred interconnect pattern may provide a lower highest crosstalk than the highest crosstalk associated with each of the other interconnect patterns. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define a plurality of longitudinal slots including longitudinal slots occupied by the set of interconnects. The highest crosstalk for the each interconnect pattern may correspond to one of the longitudinal slots.

In an aspect of the disclosure, a semiconductor device comprises a chip carrier or a circuit board having one or more layers, and a plurality of longitudinal slots defined in at least one of the one or more layers, whereby the interconnect pattern is selected from a plurality of interconnect patterns when a maximum crosstalk power estimated or calculated for the interconnect pattern is lower than maximum crosstalk powers estimated or calculated for the other interconnect patterns. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define a plurality of longitudinal slots including longitudinal slots occupied by the set of interconnects. The highest crosstalk for the each interconnect pattern may correspond to one of the longitudinal slots.

DETAILED DESCRIPTION

As the demand for high performance devices implementing IC technology has increased so has the demand for increased functionality, speed, and portability of the devices. In connection with increasing performance and functionality of consumer electronics, maximum functional integration of the IC devices in an assembly having the smallest footprint, lowest profile, and lowest cost is desired. However, as functionality increases, the number of IC and passive electrical components in the assembly increases dramatically, thus threatening the objective of a smaller-sized assembly due to issues related to the frequencies, density and proximity of interconnecting signals within and between ICs. In one example, inductive and capacitive coupling between such higher density interconnects may be increased, leading to greater crosstalk between interconnecting signals. Crosstalk may be defined as any undesirable effect generated in a first interconnect or other circuit by transmission of a signal through a second interconnect or other circuit. Crosstalk is typically observed as a result of parasitic or stray capacitive, inductive, or conductive coupling from the first interconnect or circuit to the second interconnect or circuit.

In one example, interfaces associated with double data rate synchronous dynamic random-access memory (DDR SDRAM) devices commonly have bit widths that are multiples of 8 bits, including 16 bits, 32 bits, 64 bits, etc., and may support data rates that are at least double the data rates of core logic of the DDR SDRAM IC. The high data rates and demands for particular physical alignment of inputs and outputs (I/Os) create serious challenges to SDRAM designers and designers of other types of IC. Moreover, SDRAM devices typically have interfaces that are aligned with a desired physical assignment of I/O, and which may relate to a physical layout of a ball grid array (BGA), or copper pillar bumps of an IC. Examples of physical interfaces associated with SDRAM may be found on devices such as System-on-Chip (SoC) and Mobile Station Modem (MSM) integrated circuits. Such devices may include one or more processing subsystems and peripheral I/O such as radio transceivers, and may require large numbers of interface connections to external circuits. Accordingly, densities of interconnects associated with arrays of solder balls, bumps and pillars are continuously increasing while operating frequencies of the devices are also increasing.

FIG. 1illustrates a die100and flip-chip assembly120used for interconnecting an integrated circuit106provided on the die102to external circuitry using solder bumps, balls or posts (collectively solder bumps104and/or114) that have been deposited onto an upper surface of the die102. Solder bumps104,114may be formed during wafer processing to enable the die to be mounted to a circuit or chip carrier122. A chip-carrier122may provide pads136and138on a first surface130to receive and bond the solder bumps104and114. Chip-carrier122may provide pads144on a second surface128to connect the flip-chip assembly120to external circuitry (e.g., a circuit board or another chip or wafer). Chip-carrier122may provide electrical connections between two or more dice102mounted on the chip-carrier122. Connections may be made through circuits provided on a first surface130or the second surface128of the chip-carrier122. Surfaces128and130may have a conductive layer deposited thereon, and/or a plurality of conductive layers may be provided between a plurality of layers140a-140f.

Chip carrier122may provide a plurality of layers140a-140f, including conductive layers that form one or more circuits used for transmission of signals between devices, circuits and dice102mounted on the chip carrier122and/or external devices. In one example, chip-carrier122comprises a plurality of non-conductive layers140a-140f, each non-conductive layer140a-140fseparating a pair of thin conductive layers sandwiched between adjacent non-conductive layers140a-140f, and/or deposited on the surfaces of one or more non-conductive layers140a-140f. In another example, layers140a-140fcomprise alternating layers of conducting and non-conducting materials that are interleaved to provide electrically isolative separation between conductive layers.

Vias124,134may be provided through the chip-carrier122to connect circuitry and/or pads144on the second surface128to die102through pads136,138and solder bumps104,114on the first surface130. Vias124and134may interconnect circuits provided on conductive layers within the plurality of layers140a-140f. Vias126may also be provided on die102to solder bumps104to the integrated circuit106formed in one or more layers of a semiconductor substrate provided on die102.

FIG. 2is a simplified diagram200illustrating an arrangement of horizontal interconnects on a circuit board or chip carrier122. As can be seen from the cross-sectional view210, two substantially orthogonal sets of horizontal interconnects204and206may be provided on two or more interconnect layers220and222. The sets of interconnects204and206may connect one or more integrated circuit devices202with other circuits and devices. Interconnect layers220and222may be separated by insulating materials. Each interconnect layer220and222may be provided between conductive planes214,216and218. Planes214,216,218may carry system power, or be connected to ground and may be referred to as reference planes214,216,218. The cross-sectional view210depicts a plurality of longitudinal interconnect slots212a-212ethat carry the set of interconnects206in a first interconnect layer220, and a cross-section of one of a plurality of longitudinal slots that carry orthogonal interconnects208in a second interconnect layer222. In the depicted example, longitudinal interconnect slots212a,212cand212eare used for numerically designated signals (i.e. signals1-3), longitudinal slot212bcarries an unused trace, strip or other transmission line, and gap slot212dis left vacant.

In some embodiments, the sets of interconnects204and206may be formed and/or modeled using certain transmission line topologies, including microstrip and its variations, such as embedded microstrip. In some embodiments, the sets of interconnects204and206may be formed or modeled using stripline topologies and its variations, including asymmetrical stripline, dual stripline, edge coupled stripline and broadside coupled stripline. The maximum frequency (Fmax) of signals transmitted through the sets of interconnects204and206may determine the topology adopted for interconnects204and206, and may also influence the selection of patterns used to allocate signals to individual interconnects in the sets of interconnects204and206. Patterns of interconnects may be developed that minimize crosstalk and other transmission line effects that can seriously affect signal integrity and achievable Fmax.

Certain embodiments of the invention provide systems and methods for providing interconnect patterns that can optimize signal integrity and/or channel routing width, and that can identify and optimize bottleneck signal interconnects. The methods disclosed herein may employ one or more algorithms that optimize patterns of signal interconnects slots212a,212b,212c,212eand gap slots212dto obtain a minimized crosstalk for a predefined number of signals and available gap slots212d. Conventional interconnect patterns have typically been developed using intuitive insight and oversimplified rules based on generic signals, and conventional patterns often miss opportunities for performance improvement.

Algorithms disclosed herein permit optimization of a routing channel width on a device package and printed circuit board (PCB), and may thereby decrease the area, layer count and cost of the package or PCB. The selection of an interconnect pattern may be automated and a plurality of candidate patterns may be automatically selected from all possible patterns, enabling a circuit designer to eliminate manual, trial-and-error exploration of possible patterns.

Certain embodiments optimize interconnect layout in a pattern for a given number n of signal interconnects and a given number k of gap slots. Every possible configuration of the n signal interconnects and k gap slots may be identified and a set of patterns may be obtained. The set of patterns may include all possible patterns. According to certain aspects disclosed herein, the number of possible patterns is determinable as a number of ordered combinations of the n signal interconnects available using n+k slots. For example, when k=2, some patterns may be duplicative because the two gap slots and their effects are effectively identical in nature and effect, and one of two patterns may be eliminated when the patterns differ only because the two gap slots are transposed between the patterns. Similarly, certain interconnects may be treated as identical with respect to certain cross talk calculations when, for example, the interconnects are unused or carry low frequency signals, power or ground. In one example, a low-frequency signal may generate negligible crosstalk in a neighboring interconnect, although the low frequency interconnect may be afflicted by crosstalk generated by the neighboring interconnects.

FIG. 3is a schematic300illustrating interconnect patterns302,304,306,308,310and312for different values of k. In each instance, the pattern depicted is shown for illustrative purposes only, and other patterns may offer superior performance in some applications. Each pattern302,304,306,308,310and312defines n=11 numerically referenced longitudinal signal interconnect slots, including interconnect slots320and322, for example. All 11 signal interconnects are disposed within a single layer, consistent with stripline transmission lines, in one example. Patterns304,306,308,310and312are configured for a value of k that is non-zero, and each pattern304,306,308,310and312defines k gap slots shown as hatched boxes (including gap slot324) that are not available for signals. In some embodiments, no signal trace, strip or stripe is provided in gap slots324. In some embodiments, an unconnected interconnect is provided in gap slot324.

In certain embodiments, at least one “bottleneck signal interconnect”330a-330his determined for each of a plurality of patterns302,304,306,308,310and/or312. The plurality of patterns302,304,306,308,310and/or312may comprise all possible patterns for a given n and k. The bottleneck signal interconnect330a-330hfor each pattern may be an interconnect320which generates, or is afflicted by the highest crosstalk among all interconnects in the pattern302,304,306,308,310and/or312. In one example, crosstalk is computed as far-end crosstalk (FEXT) for microstrip and dual stripline, including edge-coupled and broadside-coupled dual stripline. In another example, crosstalk is computed as near-end crosstalk (NEXT) for stripline. The crosstalk computation may be selected based on the most relevant or critical type of crosstalk for the type of interconnect and their respective interconnect patterns302,304,306,308,310and/or312.FIG. 4illustrates an example of NEXT for the bottleneck signal interconnect of a plurality of stripline patterns. The graph400illustrates NEXT measured across a range of frequencies of interest for multiple patterns. The best NEXT performance, depicted as the lowest NEXT curve412, is obtained for a pattern402. The worst NEXT performance is shown as NEXT curve414, and is obtained for a pattern404.FIG. 5illustrates an example of FEXT for the bottleneck signal interconnect of a plurality of microstrip patterns. The graph500illustrates FEXT measured across a range of frequencies of interest for multiple patterns. The best FEXT performance is represented by curve512, and is obtained for a pattern502. The worst FEXT performance curve514corresponds to the pattern504.

Crosstalk may be calculated or estimated by modeling the interconnects as microstrip, stripline, dual stripline, edge-coupled dual stripline, and/or broadside-coupled dual stripline transmission lines. Crosstalk may be calculated or estimated using physical attributes of the interconnects, such as length, and separation from neighboring interconnects and/or reference planes. An equivalent circuit of the modeled interconnect may be based on estimates of resistive, capacitive and inductive coupling between adjacent interconnects and between an interconnect and reference planes may be used to obtain an equivalent circuit. Crosstalk may be calculated or estimated based on the response of the equivalent circuit to one or more frequencies or bands of frequencies. Crosstalk may be expressed using one or more of a peak voltage or power level induced in an interconnect320or reference plane326or328, and/or a ratio of peak-to-average noise power or voltage attributable to a bottleneck signal interconnect330a-330h. In some embodiments, crosstalk may be characterized in a band of frequencies or in multiple bands of frequencies.

In certain embodiments, a preferred interconnect pattern is selected. The preferred interconnect pattern typically has a minimum highest crosstalk associated with its bottleneck signal interconnect330a-330hthan other interconnect patterns. That is, the interconnect pattern which minimizes the crosstalk in the bottleneck signal interconnect330a-330his typically selected. In some embodiments, a pattern306and/or310may yield two or more bottleneck signal interconnects330c,330dand/or330f,330grespectively, that exhibit substantially equal crosstalk. In these examples, either interconnect330cor330dmay be randomly selected as a bottleneck signal interconnect for pattern306, and either interconnect330for330gmay be randomly selected as a bottleneck signal interconnect for pattern310. In certain embodiments, a preferred interconnect pattern is selected, based on crosstalk performance with respect to one or more thresholds.

FIG. 6is a schematic600illustrating interconnect patterns602,604,606,608,610and612for different values of k. In each instance, the pattern depicted is shown for illustrative purposes only, and other patterns may offer superior performance in some applications. Each pattern602,604,606,608,610and612defines n=11 numerically-referenced longitudinal interconnect slots (including slots or interconnects620and622for example) of the 11 slots allocated for high-frequency interconnect signals. Each pattern602,604,606,608,610and612is configured for a different non-zero value of k, and each pattern602,604,606,608,610and612defines k gap slots that are not available for signals, shown here as hatched boxes and including gap slot624. In some embodiments, no signal trace, strip or stripe is provided in gap slot624. In some embodiments, an unconnected interconnect is provided in gap slot624.

The k gap slots624and n signal interconnects620are divided between a top layer or plane614a-614fand a bottom layer or plane616a-616f. The number of the k gap slots624and n interconnects620in each layer may be arbitrarily determined. In some embodiments, patterns considered for crosstalk optimization may include all possible patterns, including patterns that correspond to different splits of the k gap slots624and n signal interconnects620between the layers. InFIG. 6, each example pattern602,604,606,608,610and612has 5 interconnects in the upper layer614a-614fand6interconnects in the lower layer616a-616f. In some embodiments, the gap slots624may be considered as identical with regard to crosstalk, and certain duplicative patterns may be eliminated from consideration. For example, two patterns may be considered duplicative if all signal interconnects620are located in the same longitudinal slots in the two patterns. The latter situation may occur when patterns differ only because the locations of two or more gap slots are exchanged between the patterns.

As discussed herein, one or more bottleneck signal interconnects630a-630gestimated or calculated for each pattern602,604,606,608,610and612may be an interconnect630a-630gwhich generates, or is afflicted by the highest crosstalk among all interconnects624,622in the pattern602,604,606,608,610and612. An interconnect pattern selected for use on a device may have a minimum highest crosstalk associated with its bottleneck signal interconnect616a-616f.

FIG. 7includes a graph700that illustrates an example of FEXT for the bottleneck signal interconnect of a plurality of dual stripline patterns. The graph700illustrates FEXT measured across a range of frequencies of interest for multiple patterns. The best FEXT performance is represented by the curve712, and is obtained for a pattern702. The worst FEXT performance curve714corresponds to the pattern704.

Crosstalk may be calculated using a simplified model, in which transmission lines are characterized as rectangular interconnects that behave as transmission lines. In some embodiments, the model may assume that the interconnects are provided between two infinite planes, formed by power and ground supplies, for example, and such that inductive coupling between interconnects is dominant. Certain embodiments employ more sophisticated transmission line models that can account for changes in direction of the interconnects, different cross-sectional profiles of the interconnects, and/or imperfect reference planes.

In some embodiments, one or more interconnect patterns302,304,306,308,310,312,602,604,606,608,610and/or612may be considered for use in a chip carrier based on an optimization that includes calculations of interactions with other interconnect planes and vertical interconnects between planes. Some tradeoff may be required to obtain optimized horizontal and vertical interconnects. For example, a horizontal interconnect pattern may dictate locations for placement of one or more vias, and their corresponding vertical interconnects, and may eliminate a best or optimal vertical interconnect pattern from use on the chip carrier.

With reference toFIG. 8, crosstalk may be further optimized by considering interactions between horizontal interconnects802and804and vertical interconnects806. The vertical interconnects806may be formed in accordance with one or more optimized patterns808and808′. While a plurality of patterns may be employed in an arrangement of vertical interconnects, a single base pattern808is used in the example depicted inFIG. 8. Pattern808′ is a rotated version of the base pattern808. The pattern808′ may be rotated or mirrored to minimize crosstalk between sets of vertical interconnects and, in the example, vertical interconnects806may be formed using three instances of pattern808and one instance of the rotated/mirrored pattern808′. In some examples, the pattern808′ may comprise a different base pattern instead of a mirrored or rotated copy of the base pattern808.

The vertical interconnects806may be located in close proximity to certain of the horizontal interconnects802and804, and some of the vertical interconnects806may be connected to a corresponding horizontal interconnects802and804. Crosstalk may occur between vertical interconnects806and horizontal interconnects802and804. Accordingly, certain embodiments may optimize the arrangement of vertical interconnects806with respect to the horizontal interconnects802and804, and vice versa, for use in a chip carrier, circuit board, substrate, or the like. Optimization may be performed based on calculations of electromagnetic interactions between vertical interconnects806and intersecting or proximately located horizontal interconnects802and804.

FIG. 9is a schematic diagram900illustrating the use of horizontal interconnects904on a layer of a substrate, circuit board, chip-carrier or the like. The horizontal interconnects904may include one or more horizontal interconnect slots910and one or more gap slots912, according to certain aspects described herein. The horizontal interconnect slots910may include signal conductors that carry signals to and from a set of vertical interconnects902. The one or more gap slots912may include unused traces, an insulator, or may be vacant interconnect positions. The set of vertical interconnects902may be associated with an integrated circuit or connector, for example. The set of vertical interconnects902may include interconnects such as vertical interconnect906that carries a signal between devices and/or connectors. The set of vertical interconnects902may include one or more power, ground and or other vertical interconnects908that may not connected on the illustrated layer.

An optimal horizontal interconnect pattern920may be determined using a horizontal interconnect optimization algorithm according to certain aspects described herein. In the example, the optimal horizontal interconnect pattern920may be determined for microstrip horizontal interconnects and may provide for 11 signals with 12 gap slots. The set of vertical interconnects902may be formed in accordance with an optimized vertical interconnect pattern. In the example ofFIG. 9, the horizontal interconnects904may be used to fan out 11 signals from the vertical interconnects902. Power and ground signals may be connected to one or more different layers using vias908. In some instances, the ideal horizontal interconnect pattern920may not be physically or electromagnetically compatible with the optimal vertical interconnect pattern used to form vertical interconnects902, and a non-optimal horizontal interconnect pattern922may be used to fan-out the 11 signals from the vertical interconnects902.

The specific location of the signals, power and ground in the optimized set of vertical interconnects902may dictate, to some degree, the location of the horizontal interconnect slots910and/or gap slots912. The configuration and number of signals to be carried in the set of vertical interconnects902results in 12 gap slots912remaining between outer horizontal interconnects914and916(as indicated by broken lines). The placement of the horizontal interconnect slots910may generate crosstalk between horizontal interconnects904and/or between horizontal interconnects904and vertical interconnects902. The placement of gap slots912and/or horizontal interconnect slots910may conflict with an optimum horizontal interconnect pattern920selected for the set of horizontal interconnects904or for the horizontal interconnects904. Accordingly, a previously selected arrangement of horizontal interconnect slots910and gap slots912and/or vertical interconnects902may not be achievable.

Tradeoffs and/or co-optimizations may be employed to obtain an optimized combination of horizontal interconnects904and vertical interconnects902across one or more planes. In one example, a vertical interconnect pattern may be used that causes one or more vias and/or vertical interconnects902to be be placed at locations that preclude the use of an optimum horizontal interconnect pattern920and may result in the use of a less than optimum or non-optimal horizontal interconnect pattern922for forming horizontal interconnects904on the chip carrier, circuit board, substrate, etc. In another example, the use of an optimum horizontal interconnect pattern920may restrict the location at which one or more vias and corresponding vertical interconnects can be placed, and may eliminate an optimum vertical interconnect pattern from consideration for use on the chip carrier, circuit board, substrate, etc. In such cases, a co-optimization process may be used to consider different combinations of vertical and horizontal interconnect patterns.

A combination of horizontal and vertical patterns may be selected that results in the lowest amount of crosstalk in one or more bottleneck interconnects, which may include vertical and/or horizontal interconnects. In one example, the horizontal interconnect may be the source of the majority of system crosstalk issues and, the best horizontal interconnect pattern may be selected before a compatible associated vertical interconnect pattern is selected. In another example, the vertical interconnect may be the source of a majority of the system crosstalk, in which case the best vertical interconnect pattern may be selected first, and an associated horizontal interconnect pattern compatible with the chosen vertical interconnect pattern may then be selected.

Referring again toFIG. 1, one or more of vias124,126and solder bump104may be substantially in vertical alignment, thereby forming a vertical interconnect132, represented as line. The relative contributions of vias124,126and solder bump104to the physical length of the vertical interconnect132may vary with application. Capacitive, inductive and/or resistive coupling between adjacent vertical interconnects and horizontal interconnects can introduce crosstalk between circuits within the flip-chip assembly120.

In an aspect of the disclosure, a method, a system and an algorithm are provided that may be employed to optimize interconnect patterns in order to minimize crosstalk for an arbitrary number of signals and power/ground interconnects in semiconductor devices.

FIG. 10includes a flowchart1000illustrating a method for optimizing interconnects in a semiconductor device. At step1002, a plurality of interconnect patterns is generated for configuring a set of interconnects to be formed on one or more layers of a circuit board, substrate or chip carrier. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define a plurality of longitudinal slots, including longitudinal slots occupied by the set of interconnects. The plurality of longitudinal slots may comprise at least one unoccupied longitudinal slot. For example, two interconnect patterns may be different from one another only when the two interconnect patterns assign at least one interconnect to different longitudinal slots.

In some embodiments, the plurality of interconnect patterns defines pluralities of longitudinal slots on at least two substantially parallel planes within the one or more layers of the circuit board. The at least two substantially parallel planes may be provided between two substantially parallel reference planes.

At step1004, a highest crosstalk is determined for each of the interconnect patterns. The highest crosstalk for each interconnect pattern may correspond to one of the longitudinal slots. In one example, the highest crosstalk for the each interconnect pattern may correspond to the highest crosstalk afflicting one of the longitudinal slots. In another example, the highest crosstalk for each interconnect pattern corresponds to the highest crosstalk generated by an interconnect occupying one of the longitudinal slots. The highest crosstalk for each of the interconnect patterns may be determined for a plurality of frequencies. The highest crosstalk for each of the interconnect patterns may be determined for a range of frequencies.

According to certain aspects described herein, the highest crosstalk for each of the interconnect patterns may be determined by modeling the set of interconnects as microstrip or dual stripline transmission lines. The highest crosstalk for each interconnect pattern may comprise far-end crosstalk. The highest crosstalk for each of the interconnect patterns may be determined by modeling the set of interconnects as stripline transmission lines. The highest crosstalk for each interconnect pattern may comprise near-end crosstalk.

At step1006, a preferred interconnect pattern is selected from the plurality of interconnect patterns. The preferred interconnect pattern may provide a lower highest crosstalk than the highest crosstalk associated with each of the other interconnect patterns.

FIG. 10includes a flowchart1020illustrating a method for co-optimizing vertical and horizontal interconnects in a semiconductor device. At step1022, a preferred horizontal interconnect pattern is selected using the optimization method illustrated in the flowchart1000.

At step1024, a vertical interconnect pattern is selected. The vertical interconnect pattern may control an arrangement of vertical interconnects orthogonal to one or more layers on a substrate, circuit board or chip carrier. A combination of the preferred interconnect pattern and the vertical interconnect pattern may be selected that is calculated to provide a lower highest crosstalk associated with the combination than the highest crosstalk associated with other combinations of horizontal and vertical interconnect patterns. The highest crosstalk associated with the combination may relate to crosstalk associated with one of a vertical interconnect or a horizontal interconnect.

At step1026, a set of interconnects may be formed on a chip carrier or circuit board in accordance with the preferred interconnect pattern.

FIG. 11is a conceptual block diagram illustrating an example of a hardware implementation for an apparatus1100employing a processing circuit1102. The processing circuit1102may be implemented using a bus architecture, represented generally by the bus1120. The bus1120may include any number of interconnecting buses and bridges depending on the specific application of the processing system1102and the overall design constraints. The bus1120links together various circuits including one or more processing devices and/or hardware modules, represented by the processor1116, the modules1104,1106,1108,1110, and the processor-readable storage medium1118. The bus1120may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further.

The processing circuit1102includes a processor1116coupled to a processor-readable storage medium1118. The processor1116is responsible for general processing, including the execution of software stored on the processor-readable storage medium1118. The software, when executed by the processor1116, causes the processing circuit1102to perform the various functions described supra for any particular apparatus1100. The processor-readable storage medium1118may also be used for storing data that is manipulated by the processor1116when executing software. The processing circuit1102further includes at least one of the modules1104,1106,1108and1110. The modules1104,1106,1108and1110may comprise software modules executed by the processor1116, resident/stored in the processor-readable storage medium1118, one or more hardware modules coupled to the processor1116, or some combination thereof.

In one configuration, an apparatus1100for wireless communication includes means1104for generating a plurality of interconnect patterns, means1106for determining a highest crosstalk for each of the interconnect patterns, means1108for selecting a preferred interconnect pattern from the plurality of interconnect patterns, and means1110for forming or causing to be formed a set of interconnects set of interconnects on a chip carrier or circuit board in accordance with the preferred interconnect pattern. The plurality of interconnect patterns may be used for configuring a set of interconnects on one or more layers of a circuit board, substrate or chip carrier. The preferred interconnect pattern may provide a lower highest crosstalk than the highest crosstalk associated with each of the other interconnect patterns. The preferred interconnect pattern may be used by the means1110to generate a configuration of interconnects to be formed on the one or more layers of a circuit board, substrate or chip carrier.

The aforementioned means may be one or more of the aforementioned modules of the apparatus1100and/or the processing circuit1102configured to perform the functions recited by the aforementioned means.

The terms wafer and substrate may be used herein to include any structure having an exposed surface with which to form an IC according to aspects of the present disclosure. The term “die” may be used herein to include an IC. A die may include one or more circuits. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during fabrication, and may include other layers that have been fabricated thereupon. The term substrate includes doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor, or semiconductor layers supported by an insulator, as well as other semiconductor structures well known to one skilled in the art.

One or more of the components, steps, features and/or functions illustrated inFIGS. 1-11may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from novel features disclosed herein. The apparatus, devices, and/or components illustrated inFIGS. 1-3,6,8,9and11may be configured to perform one or more of the methods, features, or steps described herein, including as illustrated in the methods illustrated inFIG. 10. The novel algorithms described herein may also be efficiently implemented in software and/or embedded in hardware.

Moreover, a storage medium may represent one or more devices for storing data, including read-only memory (ROM), random access memory (RAM), magnetic disk storage mediums, optical storage mediums, flash memory devices and/or other machine readable mediums for storing information. The terms “machine readable medium” or “machine readable storage medium” include, but is not limited to portable or fixed storage devices, optical storage devices, wireless channels and various other mediums capable of storing, containing or carrying instruction(s) and/or data.

The methods or algorithms described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executable by a processor, or in a combination of both, in the form of processing unit, programming instructions, or other directions, and may be contained in a single device or distributed across multiple devices. A software module may reside in RAM, flash memory, ROM, erasable programmable-ROM (EPROM), electrically erasable programmable-ROM (EEPROM), registers, hard disk, a removable disk, a compact Disk ROM (CD-ROM), or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

The various features of the invention described herein can be implemented in different systems without departing from the invention. It should be noted that the foregoing aspects of the disclosure are merely examples and are not to be construed as limiting the invention. The description of the aspects of the present disclosure is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.