Imaging apparatus and image signal generating apparatus

Disclosed is an imaging apparatus including an imaging element photo-electrically converting light from a subject to generate an electric signal, an output unit generating an image signal based on the electric signal output from the imaging element, a timing generator generating a clock for image signal processing to drive the imaging element and the output unit based on a reference clock externally input, a control unit controlling the imaging element, the output unit, and the timing generator. The imaging apparatus further includes a phase delaying unit delaying a phase of the clock for the image signal processing output from the timing generator to supply the clock to the control unit.

CROSS REFERENCE TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese Patent Application 2007-019846 filed in the Japanese Patent Office on Jan. 30, 2007, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an imaging apparatus and image signal generating apparatus suitable for use in image sensors such as an endoscope.

2. Description of the Related Art

Image sensors such as Charge Coupled Devices (CCDs) or Complementary Metal Oxide Semiconductor (CMOS) have widely been used in devices and instruments such as digital still cameras, mobile telephone terminals, and endoscopes. Some of these apparatuses incorporate so-called camera modules such as image sensors and analog front end (AFE) chips each formed as a circuit. The camera modules are usually located at a distance from a microcomputer that controls components of the apparatus incorporating the camera modules.

The devices and instruments having the camera modules usually has a long transmission line connecting between the camera modules and the microcomputer, and when all the instruction signals and data are transmitted simultaneously via the transmission line, a large amount of signals are transmitted via the transmission line, thereby causing extraneous emission noises to occur in the transmission line.

Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2005-536167 discloses a digital host apparatus having camera modules that includes a processor specific to the camera modules other than a processor for the digital host apparatus. In the digital host apparatus according to this publication, the processor utilized specific to the camera modules is provided on the camera module side.

SUMMARY OF THE INVENTION

A microcomputer utilized specific to camera modules is sometimes provided separately so as to translate instruction signals received from the microcomputer and assign the translated instructions to parts of the camera module. In this case, the microcomputer and the AFE circuits of the camera modules are closely located. In general, different clock sources are utilized between the image sensor or AFE circuit and the microcomputer, and hence the closer the distance between the image sensor or AFE circuit and the microcomputer is, the higher the probability the clock supplied to the microcomputer will interfere image synchronization clock supplied to the image sensor or AFE circuit. As a result, analog-to-digital converters (hereinafter called AD converter) include increased noises, and hence image finally displayed on a display unit are likely to contain beat noises.

Likewise, an apparatus configured to have a microcomputer located closely to AFE circuits for decreasing a size of the apparatus may exhibit a similar phenomenon.

Thus, this invention attempts to provide concepts for preventing beat noises due to a clock generated from the microcomputer that interferes an image synchronization clock.

An embodiment of the present invention includes an imaging element photo-electrically converting light from a subject to generate an electric signal, and an output unit generating an image signal based on the electric signal output from the imaging element. The present embodiment further includes a timing generator generating a clock for image signal processing to drive the imaging element and the output unit based on a reference clock externally input, a control unit controlling the imaging element, the output unit, and the timing generator, and a phase delaying unit delaying a phase of the clock for the image signal processing output from the timing generator to supply the clock to the control unit.

With this configuration, a clock driving the control unit or microcomputer is generated based on the clock for the image signal processing generated from the timing generator.

According to an embodiment of the present invention, since the clock driving the control unit is generated based on the clock for the image signal processing generated from the timing generator, it is possible to suppress beat noises due to a clock generated from the control unit that interferes an image synchronization clock.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described referring to accompanied drawings.

FIG. 1illustrates a configuration example of an imaging apparatus according to one embodiment of the present invention. An imaging apparatus100according to the present embodiment can be utilized for various applications such as a medical endoscope. The imaging apparatus100shown inFIG. 1employs a 3CCD imaging system, and hence has three imaging elements of CCD imagers (hereinafter called CCD)11G,11R, and11B. The CCDs11G,11R, and11B photo-electrically convert light of G (Green), R (Red), and B (Blue) colors, which are decomposed by a color separation prism (not shown), into charge and generate an electric signal. The imaging apparatus100further includes a vertical transmission driver20(hereinafter called V-driver) for vertically transmitting signal charge photo-electrically converted and accumulated by the individual CCDs11, and horizontal transmission drivers (hereinafter H-driver)14G,14R, and14B for horizontally transmitting the signal charge vertically transmitted by the V-driver20.

The V-driver20supplies vertical transmission pulses Vφ1to Vφ4to CCDs11G,11R, and11B, while the H-drivers14G,14R,14B supply horizontal transmission pulses H1and H2to the CCDs11G,11R, and11B. The H-drivers14G,14R, and14B individually supply reset pulses RGs to the CCDs11G,11R, and11B for resetting signal charge accumulated therein. The pulses applied to the CCDs11G,11R, and11B are generated in synchronization with an image synchronization clock (CAM_CLK) supplied from a timing generator19.

The timing generator19generates the image synchronization clock (CAM_CLK) for driving the CCDs11G,11R,11B; V-driver; H-drivers14G,14R,14B; later-described CDS circuits13G,13R,13G; analog-to-digital converters (hereinafter called AD converters)15G,15R,15B based on a reference clock (HCLK) supplied from a first control unit17controlling components of the imaging apparatus100. The generated image synchronization clock (CAM_CLK) is supplied to each component of the timing generator19. The image synchronization clock indicates a clock having a frequency for image signal processing in synchronization with horizontal and vertical frequencies of an image signal. In the present embodiment, the first control unit17supplies a clock signal having a frequency of 81 MHz, which is then divided into two to obtain a clock signal having a frequency of 40.5 MHz at the timing generator19.

The signal charge received by the CCDs11G,11R,11B are read via the V-driver20and H-drivers14G,14R,14B, then converted into voltage corresponding to the signal charge at an output circuit (not shown), and supplied to CDS (Correlated Double Sampling) circuits13G,13R,13B, respectively.

The CDS circuits13G,13R,13B lower a reset noise contained in the output signals received from the CCDs11G,11R, and11B. The output image signals from the CCDs11G,11R,11B are classified into the following three periods: a reset period P1; a field through level0-level period P2; and a signal period P3, as shown inFIG. 3A. The CDS circuits13G,13R,13B compute the difference between the field-through level L1and the field-through level L2while clamping the voltage in the field through level0-level period P2, and sampling and holding signals in the signal period P3. The CDS circuits13G,13R,13B then eliminate a reset noise based on the obtained difference.

The image signals output from the CDS circuits13G,13R,13B are adjusted to a certain signal level and supplied to the AD converters15G,15R,15B. The AD converters15G,15R,15B convert analog image signals into digital signals.

The aforementioned optical system, a camera block50incorporating the CCDs11G,11R,11B, the CDS circuits13G,13R,13B or AD converters15G,15R,15B, an image processor16configured to image process image signals output from the camera block50are individually placed on separate substrates. The resulting optical system, camera block50, and image processor16are each connected to a connector2aon the camera block50side and a connector2bon the image processor16. The image processor16carries out processing such as feedback clamping that clamps a black level OB (optical black) of the digital image signals supplied from the AD converters15G,15R,15B to a certain standard value, knee correction that compresses the image signals exceeding a certain level, γ correction that corrects the signals along the γ-curve configured with a certain level of the image signals, and white clip processing that adjusts while balance.

The connector2aof the camera block50is also connected with a first control unit17that controls components of an imaging apparatus100. The first control unit17includes the components such as a microcomputer. According to the present embodiment, the camera block50includes a second control unit18for reducing amounts of signals transmitted from the first control unit17to the components of the camera block50. The second control unit18translates some of the instructions for setting the components of the camera block50transmitted from the first control unit17and transmits the resulting signals to the components of the camera block50.

Examples of the controls conducted by the second control unit18includes variable-control of shutter speed on a timing generator19, gain control on the AD converters15G,15R,15B, and switching image rates (50i/60i). The second control unit18also individually controls switching to a standby mode or initializing settings of the components of the camera block50at certain cycles to suppress the power consumption of the imaging apparatus100.

The second control unit18initializes each component of the camera block50, in a case where images are caused to deform due to interference derived from static electricity, so as to sequentially refreshes each frame of the component for immediately eliminating such image deformation.FIG. 2shows a flowchart illustrating a processing example of initializing settings according to one embodiment of the present invention. The initialization includes the steps of initializing a G-channel output unit setting (12G inFIG. 1) having the CDS circuit12G and H driver14G (Step S1), initializing a G-channel AD converter15G setting per frame (Step S2), initializing an R-channel output unit12R setting (Step S3), initializing an R-channel AD converter15R setting (Step S4), initializing a B-channel output unit12B setting (Step S5), initializing a B-channel AD converter15B setting (Step S6), and initializing a timing generator19setting (Step S7). In the present embodiment, since the camera block includes seven components, initialization is conducted at seven frame cycles. Notice that the sequence of initialization steps is not limited to that of the steps illustrated inFIG. 2; however, the initialization can be conducted in any arbitrary sequence of the steps.

Accordingly, in a case where the camera block50is provided as an original Equipment Manufacturing (OEM), detailed parameters of the components in the camera block50can be concealed from the OEM supplier by incorporating the second control unit18for translation in the camera block50.

In this case, when a clock source for driving the second control unit18is separately provided in the camera block50, the clock supplied to the second control unit18interferes image synchronization clocks supplied to the CDS circuits13G,13R,13B or those supplied to the AD converters15G,15R,15B in the camera block50, thereby increasing the possibility of generating beat noises in displayed images. The present embodiment configured to generate a clock driving the second control unit18based on the image synchronization clocks supplied from the timing generator19to the CDS circuits13G,13R,13B or to the AD converters15G,15R,15B.

The present embodiment includes a phase delaying unit18configured to adjust a phase of the image synchronization clocks to be delayed so that the clock from the second control unit18will not interfere the image synchronization clocks supplied from the timing generator19to the CDS circuits13G,13R,13B or to the AD converters15G,15R,15B to cause noises. The present embodiment further includes a divider22dividing the image synchronization clocks. In the present embodiment, the divider22divides input clocks into four to thereby generate a clock of 10.125 MHz; that is, 40.5/4=10.125 MHz. The second control unit18operates based on the clock of 10.125 MHz.

FIGS. 3A to 3Cillustrate an example of phase delaying processing at a phase delaying unit21.FIG. 3Aillustrates a waveform of a signal output from the CCDs11G,11R,11B,FIG. 3Billustrates a waveform of an image synchronization clock supplied from the timing generator19to individual components of the camera block100, andFIG. 3Cillustrates a waveform of a clock supplied to the second control unit18. According to the present embodiment, when a change point C1of the clock transmitted via the second control unit18is controlled to appear around the reset period P1; that is, when the change point C1is controlled not to appear in the field-through period P2or in the signal period P3, noises will not occur in the image data output from the CDSs13G,13R,13B.

Specifically, the phase delaying unit21conducts processing to delay a predetermined amount of the phase of the clock supplied to the second control unit18. The amount of the delay controlled by the phase delaying unit21is determined in advance such that the change point C1of the clock from the second control unit18appears at an optimal position. The optimal position of the change point C1varies with a supply timing of the reset pulses or arrangements of the components on the substrate in the camera block50and hence it is preferable that the optimal position be figured out in advance according to design requirements or conditions. The phase delaying amount to be controlled by the phase delaying unit21is determined in advance according to the resulting optimal position. Alternatively, the amount of the phase delay by the phase delaying unit21is configured to be variable and optionally be controlled according to the requirements or conditions.

Accordingly, in a case where the camera block50is provided as an original Equipment Manufacturing (OEM), detailed parameters of the components in the camera block50can be concealed from the OEM supplier by incorporating the second control unit18for translation in the camera block50.

In the present embodiment, the image synchronization clock generated by the timing generator19is divided by the divider22and then supplied to the second control unit18. Thus, the present embodiment may not have to include the clock source specific to the second control unit18.

As described so far, the present embodiment includes no specific clock source to drive the second control unit18. As a result, the clock causing to operate the second control unit18will not interfere the image synchronization clocks supplied to the CDSs13G,13R,13B or the AD converters15G,15R,15B to thereby cause converter noises. Accordingly, the beat noises appearing on the images can be lowered by inhibiting the generation of such converter noises.

Further, in the present embodiment, since the phase of the clock input to the second control unit18is controlled based on a drive timing of the CCDs11G,11R,11B, signals sampled and held at the CDS circuits15G,15R,15B are relatively unaffected by the noises.

In the embodiment described so far, microcomputers are utilized to configure the first control unit17and second control unit18; however, a specific IC utilizing an Embedded Programmable Gate Array (EPGA) can also be used for the both control units.

Further, in the aforementioned embodiment, the clock input to the second control unit18is first supplied to the phase delaying unit21to delay a phase of the clock and then supplied to the divider22to divide the clock; however, the embodiment may optionally be configured such that the clock input to the control unit18may first be supplied to the divider22to divide the clock, and then supplied to the phase delaying unit21to delay the phase of the clock.

In the aforementioned embodiment, a CCD is utilized as an image sensor; however, other image elements such as a CMOS may optionally be employed as the image sensor.

According to the aforementioned embodiment, the phase delaying unit21delays the phase of the image synchronization clock output from the timing generator19, and the resulting clock is then supplied to the second control unit18. As a result, the clock from the second control unit18may not be a source of the noises interfering in the image synchronization signal. In contrast, the phase of the image synchronization clock may be delayed while the clock supplied to the second control unit18remained unchanged, as shown inFIG. 4.

FIG. 4illustrates an example of the imaging apparatus100having such a configuration. According to the configuration shown inFIG. 4, a phase delaying unit21′ delays the phase of the image synchronization clock output from the timing generator19, and the resulting clock is supplied as the image synchronization clock to the CCDs11G,11R,11B, the output units12G,12R,12B, and the AD converters15G,15R,15B. The image synchronization clock prior to being input to the phase delaying unit21are divided the divider22, and the resulting clock is then supplied to the second control unit18so as to drive the second control unit18. In the imaging apparatus having such a configuration, since the clock for driving the second control unit18is generated based on the image synchronization clock, the clock for driving the second control unit18and image synchronization clock will not mutually interfere. Further, since the phase delaying unit21′ delays the phase of the image synchronization clock supplied to the CCDs11G,11R,11B, the output units12G,12R,12B, and the AD converters15G,15R,15B, the position of the change point C1of the clock for driving the second control unit18can be adjusted based on the waveform of the output signals from the CCDs11G,11R,11B.

According to the aforementioned embodiment, the first control unit17located at a distance from the camera block50supplies the clock driving the components of the camera block50. However, the camera block50may be configured to include a separate clock source (clock generator) such that the components of the camera block50can be driven based on the clock generated by the separately provided clock source.FIG. 5shows a configuration example of the imaging apparatus100in which an oscillator23is provided with the timing generator19as a clock source.

FIG. 5shows a configuration in which the timing generator19divides a reference clock generated by the oscillator23to form an image synchronization clock, which is then supplied to the CCDs11G,11R,11B, the output units12G,12R,12B, and the AD converters15G,15R,15B. The phase delaying unit21delays the phase of the image synchronization clock, which is then divided by the divider22to form a clock for driving the second control unit18.

Alternatively, the camera block may include the oscillator23provided on the second control unit18side. The imaging apparatus100having such a configuration is illustrated inFIG. 6. According to the imaging apparatus100having the configuration shown inFIG. 6, the reference clock supplied from the oscillator23is supplied to the timing generator19via the second control unit18. In the timing generator19, a divider, not shown, divides the input reference clock, which is then supplied to the CCDs11G,11R,11B, the output units12G,12R,12B, and the AD converters15G,15R,15B as the image synchronization clock.

The second control unit18includes a divider22″, for generating a clock to drive the second control unit18per se, and the second control unit18drives itself based on the clock divided by the divider22″. Setting signals received from the second control unit18are supplied to the components of the camera block50via a phase delaying unit21″ having delayed the phase of the setting signals. Accordingly, although the camera block50includes the oscillator23, if the clock for driving the second control unit18and the image synchronization clocks supplied to other components of the camera block50are generated based on the same reference clock, generation of the converter noises can be suppressed.

Notice that the aforementioned delaying unit can be formed with elongating patterns of the circuit board, or formed by utilizing a cable. According to the aforementioned embodiment, the aforementioned delaying unit is utilized for an imaging apparatus; however, the delaying unit may also be employed for an image signal generating apparatus having no image sensor.