Memory device and method for fabricating the same

Provided is a memory device, including a plurality of gate pillar structures and a plurality of dielectric pillars. The gate pillar structures and the dielectric pillars are arranged alternately and separately along a first direction, and are arranged alternately and contact each other along a second direction. In addition, the gate pillar structures and the dielectric pillars are embedded in a stack layer along a third direction, thereby dividing the stack layer into a plurality of stack structures. A sidewall of each of the dielectric pillars in the second direction and a sidewall of the adjacent gate pillar structure in the second direction are not coplanar.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor device and a method for fabricating the same, and particularly relates to a memory device and a method for fabricating the same.

2. Description of Related Art

With the continuous development of science and technology, the demands to the storage capability also increases as the electronic products continue to improve. To improve the storage capability, memory devices become smaller and have a greater integrity. Thus, the industries now highly focus on three-dimensional memory devices.

However, as the integrity of three-dimensional memory devices continues to increase, the defects found in the fabricating process of vertical gates due to a high aspect ratio and stacking of composite films are more and more common. The defects include bit line channel bending, word line bridging, etc. Moreover, as the size of memory devices becomes smaller, an influence of the interference between adjacent memory cells on the performance of the memory cells or a memory cell array becomes more and more serious. Therefore, how to develop a memory device having a high integrity and a method for fabricating the same to avoid bit line channel bending and word line bridging has now become an important issue to be touched upon.

SUMMARY OF THE INVENTION

The invention provides a memory device and a method for fabricating the same capable of solving bit line channel bending and word line bridging in a fabricating process of vertical gates.

The invention provides a memory device and a method for fabricating the same capable of reducing interference between adjacent memory cells, thereby improving performance of the memory cells or a memory array.

The invention provides a memory device and a method for fabricating the same applicable to charge trapping memory, non-volatile memory, and embedded memory.

The invention provides a memory device, including a plurality of gate pillar structures and a plurality of dielectric pillars. The gate pillar structures and the dielectric pillars are arranged alternately and separately along a first direction, and are arranged alternately and contact each other along a second direction. In addition, the gate pillar structures and the dielectric pillars are embedded in a stack layer along a third direction, thereby dividing the stack layer into a plurality of stack structures. The first direction is different from the second direction, and is different from the third direction. A sidewall of each of the dielectric pillars in the second direction and a sidewall of the adjacent gate pillar structure in the second direction are not coplanar.

According to an embodiment of the invention, a width of each of the dielectric pillars in the first direction is greater than or equal to a width of the adjacent gate pillar structure in the first direction.

According to an embodiment of the invention, a contact area of each of the conductive pillars and the corresponding charge storage layer is greater than or equal to a contact area of the charge storage layer and the corresponding stack structure.

According to an embodiment of the invention, each of the stack structures comprises a plurality of insulating layers and a plurality of conductive layers, and the insulating layers and the conductive layers are stacked alternately along the third direction.

The invention provides a memory device including a substrate, a plurality of word lines, a plurality of isolation structures, a plurality of stack structures, a plurality of gate pillar structures, and a plurality of dielectric pillars. The substrate has a plurality of first regions, a plurality of second regions, and a plurality of third regions. The first regions and the second regions are arranged alternately along a first direction. Each of the third regions is located between the corresponding first region and second region. The plurality of word lines are located on the substrate. Each of the word lines extends along a first direction, and traverses the first regions, the second regions, and the third regions. The plurality of isolation structures are located on the substrate and between two adjacent word lines. Each of the isolation structures extends along a first direction, and traverses the first regions, the second regions, and the third regions. A plurality of stack structures are located on the substrate in the third regions. Each of the stack structures extends along the second direction, and traverses the word lines and the isolation structures. A plurality of gate pillar structures are located on the word lines. Each of the gate pillar structures extends along the third direction. Each of the gate pillar structures includes a plurality of conductive pillars and a plurality of charge storage layer. The conductive pillars are respectively electrically connected with the even word lines in the first regions and electrically connected with the odd word lines in the second regions. Each of the charge storage layers is located at a periphery of the corresponding conductive pillar to electrically isolate the corresponding stack structure and the conductive pillar. The first direction is different from the second direction, and is different from the third direction. The plurality of dielectric pillars are located on the word lines. Each of the dielectric pillars extends along the third direction, and the dielectric pillars contact the odd word lines in the first regions and contact the even word lines in the second regions.

According to an embodiment of the invention, a shape of a sidewall of the stack structure in the third region between the gate pillar structures and the dielectric pillars in each of the first regions and the gate pillar structures and the dielectric pillars in the adjacent second region comprises a sawtoothed shape or a serpentine shape.

According to an embodiment of the invention, each of the gate pillar structures and the adjacent dielectric pillar contacts each other on the corresponding isolation structure.

According to an embodiment of the invention, a width of each of the dielectric pillars in the first direction is greater than or equal to a width of the adjacent gate pillar structure in the first direction.

According to an embodiment of the invention, a contact area of each of the conductive pillars and the corresponding charge storage layer is greater than or equal to a contact area of the charge storage layer and the corresponding stack structure.

According to an embodiment of the invention, the third direction is perpendicular to the first direction and the second direction, and the first direction is perpendicular to the second direction.

According to an embodiment of the invention, each of the stack structures includes a plurality of insulating layers and a plurality of conductive layers, and the insulating layers and the conductive layers are stacked alternately along the third direction.

The invention provides a method for fabricating a memory device, including forming a stack layer on a substrate. A plurality of gate pillar structure and a plurality of dielectric pillars are formed in the stack layer. The gate pillar structures and the dielectric pillars are arranged separately and alternately along a first direction, arranged alternately and contact each other along a second direction, and are respectively embedded in the stack layer along a third direction, thereby dividing the stack layer into a plurality of stack structures extending along the second direction, The first direction is different from the second direction, and is different from the third direction. A sidewall of each of the dielectric pillars in the second direction and a sidewall of the adjacent gate pillar structure in the second direction are not coplanar.

According to an embodiment of the invention, the method for fabricating the memory device includes steps as follows. A substrate having a plurality of first regions, a plurality of second regions, and a plurality of third regions are provided. The first regions and the second regions are arranged alternately along a first direction. Each of the third regions is located between the corresponding first region and second region. Then, a plurality of word lines are formed on the substrate. Each of the word lines extends along a first direction, and traverses the first regions, the second regions, and the third regions. Then, an isolation structure is formed between two adjacent word lines. Each of the isolation structures extends along a first direction, and traverses the first regions, the second regions, and the third regions. The word lines and the isolation structures are alternately arranged along a second direction. A stack layer is formed on the substrate. A plurality of first holes are formed in the stack layer on the word lines, The first holes expose top surfaces of the even word lines in the first regions and expose top surfaces of the odd word lines in the second regions. A gate pillar structure is formed in each of the first holes. Each of the gate pillar structures includes a conductive pillar and a charge storage layer. The conductive pillars are respectively electrically connected with the even word lines in the first regions and electrically connected with the odd word lines in the second regions. Each of the charge storage layers is located at a periphery of the corresponding conductive pillar to electrically isolate the corresponding stack layer and the conductive pillar. A plurality of second holes are formed in the stack layer on the word lines. The second holes expose top surfaces of the odd word lines in the first regions and expose top surfaces of the even word lines in the second regions. The second holes and the gate pillar structures are alternately arranged along the first direction and the second direction. Each of the second holes contacts the adjacent gate pillar structure on the corresponding isolation structure, such that the stack layer is divided into the plurality of stack structures in the third regions. The stack structures extend along the second direction. A dielectric pillar is formed in each of the second holes.

According to an embodiment of the invention, the step of forming the corresponding gate pillar structure in each of the first holes is as follows. A charge storage material layer is formed on the substrate. The charge storage material layer covers a top surface of the stack layer, sidewalls of the first holes, and top surfaces of the word lines. A part of the charge storage material layer is removed by performing an anisotropic etching process to expose the top surfaces of the stack layer and the word lines, thereby forming a charge storage layer on the sidewall of each of the first holes. Then, a conductive pillar is formed in each of the first holes, such that each of the charge storage layers is located at the periphery of the corresponding conductive pillar.

According to an embodiment of the invention, the step of forming the corresponding dielectric pillar in each of the second holes is as follows. A dielectric material layer is formed on the substrate. The dielectric material layer is filled in the second holes. Then, a planarization process to the dielectric material layer is performed so as to expose the top surfaces of the gate pillar structures and the stack structures.

According to an embodiment of the invention, a shape of a sidewall of the stack structure in the third region between the gate pillar structures and the dielectric pillars in each of the first regions and the gate pillar structures and the dielectric pillars in adjacent second region comprises a sawtoothed shape or a serpentine shape.

According to an embodiment of the invention, a width of each of the dielectric pillars in the first direction is greater than or equal to a width of the adjacent gate pillar structure in the first direction.

According to an embodiment of the invention, a contact area of each of the conductive pillars and the corresponding charge storage layer is greater than or equal to a contact area of the charge storage layer and the corresponding stack structure.

According to an embodiment of the invention, the stack layer includes a plurality of insulating layers and a plurality of conductive layers. The insulating layers and the conductive layers are stacked alternately along the third direction.

According to an embodiment of the invention, the third direction is perpendicular to the first direction and the second direction, and the first direction is perpendicular to the second direction.

Based on the above, in the invention, by embedding the plurality of gate pillar structures and the plurality of dielectric pillars arranged alternately in the stack layer in the first regions and the second regions, the stack layer is divided into the plurality of stack structures (serving as bit lines, for example). In this way, the memory device and the method of fabricating the same according to the embodiments of the invention avoid the issue of bit line channel bending or word line bridging. In addition, the dielectric pillars electrically isolate the gate pillar structures and the stack structures. Therefore, the interference between the adjacent memory cells may be reduced, thereby improving the performance of the memory cells or the memory cell array.

DESCRIPTION OF THE EMBODIMENTS

FIGS. 1A to 1Eare top schematic view illustrating a method for fabricating a memory device according to an embodiment of the invention.FIGS. 2A to 2Eare cross-sectional schematic views along an A-A′ line inFIGS. 1A to 1E.

Referring toFIGS. 1A and 2Atogether, a substrate100is a semiconductor substrate, a semiconductor compound substrate, or a semiconductor over insulator (SOI) substrate, for example. The semiconductor is atoms of IVA Group, for example, such as silicon or germanium. The semiconductor compound is a semiconductor compound formed of atoms of IVA group, for example, such as silicon carbide or silicon germanium, or atoms of IIIA Group and VA Group, such as gallium arsenide. The substrate100has a plurality of first regions R1, a plurality of second regions R2, and a plurality of third regions R3. The first regions R1and the second regions R2are alternately arranged along the first direction D1. Each of the third regions R3is located between the corresponding first region R1and second region R2.

Then, a plurality of word lines104are formed on the substrate100. Each of the word lines104extends along a first direction D1, and traverses the first regions R1, the second regions R2, and the third regions R3. Specifically, an isolation material layer and a word line material layer (not shown) are sequentially formed on the substrate100. Then, a photolithography process and an etching process are performed to the isolation material layer and the word line material layer, so as to form a plurality of isolation layers102and the plurality of word lines104on the substrate100. Each of the isolation layers102and each of the word lines104extend along the first direction D1and traverse the first regions R1, the second regions R2, and the third regions R3. The etching process may be a dry etching process, for example, and the dry etching process may be a reactive ion etching (RIE) process, for example. In an embodiment, a material of the isolation layers102may include an insulating material, such as silicon oxide or a low dielectric constant material layer having a dielectric constant lower than 4. A method for forming the isolation layers102may be the chemical vapor deposition method or the thermal oxidation method. A material of the word lines104may include polysilicon, metal silicide, metal, or a combination thereof, and a method of forming the word lines104may be the chemical vapor deposition method. The metal silicide may be tungsten silicide, cobalt silicide, nickel silicide, titanium silicide, copper silicide, molybdenum silicide, tantalum silicide, erbium silicide, zirconium silicide, or platinum silicide, for example.

Then, an isolation structure105is formed between two adjacent word lines104. Each of the isolation structures105extends along the first direction D1and traverses the first regions R1, the second regions R2, and the third regions R3. Specifically, the isolation structure material layer (not shown) is formed on the substrate100, and then an etching back process is performed to the isolation structure material layer to form the isolation structure105between two adjacent word lines104. Each of the isolation structures105is disposed between two adjacent word lines, and the word lines104and the isolation structures105are alternately arranged in a second direction, such that each of the word lines104is electrically isolated from each other. A material of the isolation structures105includes silicon oxide or a low dielectric constant material layer having a dielectric constant lower than 4, and a method of forming the isolation structures105may be the chemical vapor deposition method.

Referring toFIGS. 1B and 2Btogether, a stack layer106is formed on the substrate100. The stack layers106includes a plurality of insulating layers106aand a plurality of conductive layers106b, and the insulating layers106aand the conductive layers106bare stacked alternately along a third direction D3. The third direction D3is different from the first direction D1and the second direction D2. In an embodiment, the third direction D3is substantially perpendicular to the first direction D1and the second direction D2, and the first direction D1is substantially perpendicular to the second direction D2.

In an embodiment, the number of layers of the conductive layers106bmay be 8, 16, 32, or more. Similarly, the insulating layer106ais disposed between two adjacent conductive layers160b, so the number of layers of the insulating layers106amay be 8, 16, 32, or more. In an embodiment, a material of the insulating layers106amay include silicon oxide, silicon nitride, or a combination thereof, and a method of forming the insulating layers106amay be the chemical vapor deposition method. A material of the conductive layers106bmay be doped polysilicon, undoped polysilicon, or a combination thereof, and a method of forming the conductive layers106bmay be the chemical vapor deposition method.

Referring toFIGS. 1C and 2Ctogether, a photolithography process and an etching process are performed to the stack layer106, so as to form a plurality of first holes10in the stack layer106on the word lines104in the first regions R1. The first holes10in the first regions R1and the first holes10in the second regions R2are alternately arranged with respect to each other. More specifically, the first holes10extend along a third direction D3and respectively expose the even word lines104in the first regions R1and the odd word lines104in the second regions R2. In an embodiment, a shape of the first holes10may be circular, square, rectangular, or an arbitrary shape, for example, as long as the first holes10penetrate the stack layer106to expose top surfaces of the corresponding word lines104after the photolithography process and the etching process. A size of each of the first holes10may be greater or equal to a width of the corresponding word line104, as long as the first hole10is not connected to any adjacent first hole10. The etching process may be a dry etching process, for example, and the dry etching process may be a reactive ion etching (RIE) process, for example. When the first holes10are formed in the stack layer106, portions of the remained stack layer106that the first holes10are not formed therein are structurally connected to each other, thereby supporting each other to avoid collapsing or bending.

Referring toFIGS. 1D and 2Dtogether, a gate pillar structure108is formed in each of the first holes10. The gate pillar structures108in the first regions R1and the gate pillar structures108in the second regions R2are alternately arranged. More specifically, each of the gate pillar structures108extends along the third direction D3, and includes a charge storage layer110and a conductive pillar112(serving as a control gate, for example). The conductive pillars112are respectively electrically connected with the even word lines104in the first regions R1and electrically connected with the odd word lines104in the second regions R2. Therefore, each of the conductive pillars112may serve as an extension of the corresponding word line104. Each of the charge storage layers110is located at a periphery of the corresponding conductive pillar112, such that the corresponding plurality of conductive layers106bin the stack layer106are electrically isolated from the conductive pillar112. Specifically, steps of forming the corresponding gate pillar structure108in each of the first holes10are described as follows. First of all, a charge storage material layer (not shown) is formed on the substrate100. The charge storage material layer covers a top surface of the stack layer106, a sidewall of the first hole10, and the top surface of the word line104. Then, a conductive material layer is formed on the charge storage material layer. Subsequently, a part of the charge storage material layer and a part of the conductive material layer are removed to expose the top surfaces of the stack layer106and the word line104by performing a chemical-mechanical polishing (CMP) process or an anisotropic etching process, such that the charge storage layer110and the conductive pillar112are formed on the sidewall of each of the first holes10. In an embodiment, a material of the charge storage material layer may include an oxide layer, a nitride layer, or a composite layer of an arbitrary combination thereof. The composite layer may include three or more layers, and the invention is not limited thereto. A method of forming the charge storage material layer may be the chemical vapor deposition method, the thermal oxidation method, etc. For example, the charge storage material layer may include a composite layer such as an oxide/nitride/oxide (ONO) layer, an oxide/nitride/oxide/nitride (ONON) layer, etc. In an embodiment, a material of the conductive material layer may include polysilicon, metal silicide, metal, or a combination thereof, and a method of forming the conductive material layer may be the chemical vapour deposition method. The metal silicide may be tungsten silicide or cobalt silicide, nickel silicide, titanium silicide, copper silicide, molybdenum silicide, tantalum silicide, erbium silicide, zirconium silicide, or platinum silicide, for example.

Referring toFIGS. 1E and 2Etogether, a plurality of dielectric pillars116are formed in the stack layer106. The dielectric pillars116in the first regions R1and the dielectric pillars116in the second regions R2are arranged alternately. More specifically, the dielectric pillars116are located on the odd word lines104in the first regions R1and the even word lines104in the second regions R2. Each of the dielectric pillars116extends along the third direction D3. Moreover, in the first direction D1, the dielectric pillars116and the gate pillar structures108are alternately arranged. In the second direction D2, the dielectric pillars116and the gate pillar structures108are alternately arranged and contact each other, such that the gate pillar structures108and stack structures114are electrically isolated from each other.

Specifically, first of all, a photolithography process and an etching process are performed to the stack layer106to form a plurality of second holes20in the stack layer106on the word lines104. The second holes20in the first regions R1and the second holes20in the second regions R2are alternately arranged with respect to each other. More specifically, the second holes20expose the top surfaces of the odd word lines104in the first regions R1, and expose the top surfaces of the even word lines104in the second regions R2. The second holes20and the gate pillar structures108are alternately arranged along the first direction D1and are alternately arranged along the second direction D2. A sidewall of each of the second holes20exposes the gate pillar structure108adjacent thereto. In an embodiment, a shape of the second holes20may be circular, square, rectangular, or an arbitrary shape, for example, as long as the second holes20penetrate the stack layer106to the expose top surfaces of the corresponding word lines104after the photolithography process and the etching process. A size of each of the second holes20may be greater than or equal to the width of the corresponding word line104, as long as each of the second holes20exposes the sidewalls of the corresponding gate pillar structures108. In an embodiment, the etching process may be a dry etching process, for example, and the dry etching process may be a reactive ion etching process, for example. When the second holes20are formed in the stack layer106in the embodiments of the invention, although the stack layer106is already patterned to form the stripe-shaped stack structures114, the stack structures114may be supported by the structurally connected gate pillar structures108, thereby avoiding collapsing or bending of the stack structures114.

Then, a dielectric material layer (not shown) is formed on the substrate100. The dielectric material layer is filled into the second holes20. A material of the dielectric material layer may include silicon oxide, silicon nitride, or a combination thereof, and a method of forming the dielectric material layer may be the chemical vapor deposition method. Subsequently, a planarization process is performed to the dielectric material layer to expose the top surfaces of the gate pillar structures108and the stack structures114, such that a plurality of the dielectric pillars116are formed in the second holes20. In an embodiment, the planarization process may be a chemical-mechanical polishing (CMP) process.

In the above embodiment, by embedding the dielectric pillars116and the gate pillar structures108in the stack layer106in the first regions R1and the second regions R2, the stack layer106may be divided into the plurality of stack structures114. The stack structures114extend along the second direction D2and are located in the third regions R3between the first regions R1and the second regions R2. In addition, the stack structures114traverse the plurality of word lines104and the plurality of isolation structures105. When any of the dielectric pillars116and the gate pillar structures108are not in a rectangular shape and are different in size, a sidewall of each of the dielectric pillars116in the second direction D2and a sidewall of the adjacent gate pillar structure108in the second direction D2are not coplanar, making sidewalls of the stack structures114not flat surfaces. Instead, a shape of the sidewalls thereof includes a sawtoothed shape or a serpentine shape.

In addition, each of the gate pillar structures108and the corresponding stack structure114form a memory cell string. For the memory cell strings, the dielectric pillar116is disposed between two adjacent memory cell strings in the first direction D1and between two adjacent memory cell strings in the second direction D2. Therefore, the dielectric pillars116may serve to electrically isolate the adjacent memory cells to reduce interference between the adjacent memory cells, thereby improving performance of the memory cells and a memory cell array.

In the above embodiment, it is described that the plurality of gate pillar structures that are alternately arranged are embedded in the stack layer, and then the plurality of dielectric pillars that are alternately arranged are embedded, so as to divide the stack layer into the plurality of stripe-shaped stack structures. However, the invention is not limited thereto. In other embodiments, it is also possible to embed the plurality of dielectric pillars that are alternately arranged in the stack layer first, and then embed the plurality of gate pillar structures that are alternately arranged, so as to divide the stack layer into the plurality of stripe-shaped stack structures.

Referring toFIGS. 1E and 2Etogether, the memory device of this embodiment of the invention includes the substrate100, the plurality of word lines104, the plurality of isolation structures105, the plurality of gate pillar structures108, the plurality of stack structures114(serving as a plurality of bit lines, for example), and the plurality of dielectric pillars116.

The substrate100has the plurality of first regions R1, the plurality of second regions R2, and the plurality of third regions R3. The first regions R1and the second regions R2are alternately arranged along the first direction D1. Each of the third regions R3is located between the corresponding first region R1and second region R2. The plurality of word lines104are located on the substrate100. Each of the word lines104extends along the first direction D1, and traverses the first regions R1, the second regions R2, and the third regions R3. The plurality of isolation structures105are located on the substrate100and between two adjacent word lines104. Each of the isolation structures105extends along the first direction D1and traverses the first regions R1, the second regions R2, and the third regions R3.

The plurality of stack structures114(serving as bit lines, for example), are located on the substrate110in the third regions R3. Each of the stack structures114extends along the second direction D2, and traverses the word lines104and the isolation structures105. Each of the stack structures114includes the plurality of insulating layers114aand the plurality of conductive layers114b. The insulating layers114aand the conductive layers114bare stacked alternately along the third direction D3, as shown inFIG. 2E. At two sides of each of the stack structures114, the gate pillar structure108and the dielectric pillar116opposite to each other are respectively disposed. In addition, the gate pillar structures108and the dielectric pillars106at any side of the stack structures114are alternately arranged.

The plurality of gate pillar structures108are alternately arranged and located on the word lines104in the first regions R1and the second regions R2at the two sides of the stack structures114. More specifically, each of the gate pillar structures108extends along the third direction D3, and each of the gate pillar structures108includes the charge storage layer110and the conductive pillar112(serving as a control gate, for example). The conductive pillars112in the first regions R1are disposed on the even word lines104and electrically connected thereto, and the conductive pillars112in the second regions R2are disposed on the odd word lines104and electrically connected thereto. Each of the charge storage layers110is located at the periphery of the corresponding conductive pillar112to electrically isolate the corresponding stack structure114and the conductive pillar112. The first direction D1is different from the second direction D2, and is different from the third direction D3. In an embodiment, the third direction D3is substantially perpendicular to the first direction D1and the second direction D2, and the first direction D1is substantially perpendicular to the second direction D2.

The plurality of dielectric pillars116are alternately arranged and located on the word lines104in the first regions R1and the second regions R2at the two sides of the stack structures114. More specifically, the dielectric pillars116extend along the third direction D3. The dielectric pillars116in the first regions R1are disposed on the odd word lines104and contact the odd word lines104, and the dielectric pillars116in the second region R2are disposed on the even word lines104and contact the even word lines104.

In the second direction D2, the gate pillar structures108and the dielectric pillars116are alternately arranged and contact each other. By using the dielectric pillars116, the adjacent gate pillar structures108are electrically isolated from each other. In the first direction D1, the gate pillar structures108and the dielectric pillars116are arranged alternately and separately. In other words, each of the gate pillar structures108is located between two adjacent dielectric pillars116, and the stack structures114are respectively disposed at two sides of the gate pillar structures108. Each of the gate pillar structures108and adjacent stack structure114may respectively form a memory cell string having a single gate structure. In other words, each of the memory cell strings in this embodiment may be controlled by the single gate structure.

Moreover, referring toFIG. 1E, in the embodiments of the invention, profiles of the dielectric pillars116may be controlled when forming the dielectric pillars116, such that contact surfaces of the dielectric pillars116and the gate pillar structures108have inclined or curved profiles. Here, a memory cell string M is described as an example. A contact area S1of each of the conductive pillars112and the corresponding charge storage layer110may be greater than or equal to a contact area S2of the charge storage layer110and the corresponding stack structure114. The greater contact area S1allows a preferable electrical control to the memory cell string M.

In view of the foregoing, in the embodiments of the invention, the plurality of gate pillar structures and the plurality of dielectric pillars that are alternately arranged are embedded in the stack layer, such that the stack layer is divided into the plurality of stripe-shaped stack structures. Since the gate pillar structures and the dielectric pillars are formed by forming holes and refilling the required materials, the same or different materials that the holes are not formed therein may provide support to each other when the holes are formed in the stack layer, thereby avoid collapsing or bending. In this way, the memory device and the method of fabricating the same according to the embodiments of the invention avoid the issue of bit line channel bending or word line bridging.

Furthermore, the dielectric pillars separate the adjacent gate pillar structures and the adjacent stack structures. In other words, the dielectric pillars may electrically isolate the adjacent memory cells. Thus, the interference between the adjacent memory cells is effectively reduced, and the performance of the memory cells or memory cell array is thus improved.

Furthermore, in the embodiments of the invention, the contact area of each of the conductive pillars and the corresponding charge storage layer is controlled to be greater than or equal to the contact area of the charge storage layer and the corresponding stack structure, thereby making the corresponding memory cell has a preferable electrical control.