Oscillator circuit with an inverter amplifier having reduced consumption

There is disclosed an inverter oscillator circuit delivering an alternating output signal and including a parallel arrangement, between an input terminal and output terminal, of an inverter amplifier means, a resonator, and a resistor, first and second load capacitors being respectively connected between said input and output terminals, on the one hand, and a supply potential, on the other hand. Control means for controlling the inverter amplifier means such that it has a so called start-up transconductance value during a start-up phase and a so-called reduced transconductance value, lower than said start-up transconductance value, in steady state at the end of said start-up phase. Means for smoothing an amplitude decrease in the output signal resulting from the passage of said start-up transconductance value to said reduced transconductance value is included.

BACKGROUND OF THE INVENTION

The present invention generally concerns an oscillator circuit with an inverter amplifier (herein after called an inverter oscillator circuit) having reduced consumption. More particularly, the present invention concerns a relatively low frequency inverter oscillator circuit preferably including a quartz resonator arranged to vibrate according to a torsional vibration mode.

There is already known from European Patent No. EP 1 111 770 A1, in the name of Eta SA Fabriques d'Ebauches and EM Microelectronic-Marin SA, a low frequency quartz oscillator device having improved thermal behaviour. This Application, which is incorporated herein by reference, discloses an inverter type oscillator including a specific quartz resonator arranged to vibrate according to a torsional vibration mode. This specific resonator, which is disclosed in the article by Messrs. Roger Bourquin and Philippe Truchot, “Barreau de quartz vibrant en mode de torsion, Application aux capteurs”, 6thEuropean Chronometry Congress, Bienne, 17–18 Oct. 1996 (cited and incorporated by reference in the aforementioned European Patent Application), has a single cut angle defined by a rotation about the crystallographic axis X of the quartz crystal, and includes, in particular, an undesired fundamental flexural vibration mode located at a first frequency and a desired torsional vibration mode located at a second frequency higher than the first frequency of the undesired flexural vibration mode.

The circuit for maintaining the resonator's oscillation is of the inverter type. In order to ensure that the resonator vibrates according to the desired fundamental torsional vibration mode, and not according to the undesired fundamental flexural vibration mode, the inverter circuit is designed to have a transconductance value such that the limit conditions for ensuring vibration (or minimum and maximum critical transconductance values) are satisfied for the fundamental torsional vibration mode and not for the fundamental flexural vibration mode.

The thermal behaviour of the oscillator device thus designed is therefore greatly improved with respect to conventional oscillator devices and has, in particular, similar thermal behaviour to circuits using AT cut resonators for a considerably lower operating frequency (typically 393 kHz for the torsional resonator compared to 4 MHz for the AT cut resonator) and thus a comparatively lower consumption.

SUMMARY OF THE INVENTION

Leaving aside the advantages in terms of thermal stability, the consumption of the oscillator circuit disclosed in the aforementioned European Patent Application remains, however, comparatively higher than those of conventional low frequency oscillator circuits. The main object of the present invention is thus to propose an oscillator circuit having a more reduced consumption, this oscillator circuit preferably, but not necessarily, including a torsional vibrating resonator of the aforementioned type.

It will be noted that a solution allowing the consumption of an oscillator circuit to be reduced is already known from Japanese Patent Application No. JP 60-64506 in the name of Fujitsu Ltd., filed on 20 Sep. 1983.FIGS. 1aand1bshow two functional diagrams of this inverter oscillator circuit, globally indicated by the reference numeral10. Globally, each of the oscillator circuits illustrated corresponds to a conventional inverter oscillator circuit including, in particular, the parallel arrangement, between input terminal A and output terminal B, of inverter amplifier means2,3, a resonator1and a resistive element4, called a feedback resistor, of value RF. First and second load capacitors5,6are respectively connected between input terminal A and output terminal B, on the one hand, and a supply potential, here VSS, on the other hand.

This oscillator circuit10further includes control means8and a switching means7for controlling inverter amplifier means2,3such that it has a first transconductance value during a start-up phase and a second transconductance value, lower than the first transconductance value, in steady state at the end of the start-up phase.

More precisely, oscillator circuit10ofFIG. 1aincludes a first inverter2having a first transconductance value, designated gm, and a second inverter3having a second transconductance value, designated Gm, higher than first transconductance value gm. Switching means7is arranged so as to selectively connect first inverter2or second inverter3between the input and output terminals A, B. During the start-up phase, switching means7is in position “1” so as to connect the second inverter between terminals A and B. As soon as the oscillations are stable, in steady state, switching means7passes into position “2” via the action of control means8.

Oscillator circuit10ofFIG. 1bis substantially similar to the circuit ofFIG. 1a. Second inverter3has here only an additional or complementary value, designated Δgm, which is added to transconductance value gmof first inverter2during the start-up phase. Switching means7is thus connected such that second inverter3is connected in parallel with first inverter2during the start-up phase (switching means7in position “1”) and disconnected from second inverter2in steady state (switching means7in position “2”).

It will be noted that the use of the solutions proposed in the aforementioned Japanese document may have several drawbacks. In particular, the effect of the decrease in transconductance value during switching at the end of the start-up phase is a decrease in current (and thus in consumption) which also results in an abrupt decrease in the amplitude of the oscillator's output signal. This switching of the oscillator circuit can, in particular, lead to significant damping of the resonator's oscillations, which may eventually lead to it stopping totally or to a modification in its vibration mode. In particular, the inventor has been able to observe that if the solution proposed in the aforementioned Japanese document were directly associated with the aforementioned resonator arranged to vibrate torsionally, it would lead either to the resonator stopping totally or to a modification in its vibration mode to the undesired fundamental flexural vibration mode.

It will also be noted that the abrupt decrease in amplitude in the oscillator's output signal can also be a drawback for the peripheral elements associated with the oscillator circuit.

The use of the principle set forth in the aforementioned Japanese Patent Application, in particular in association with the oscillator circuit of European Patent Application No. EP 1 111 770 A1 mentioned in the preamble, thus requires very particular care, given the specific conditions that the oscillator has to satisfy so that the resonator vibrates according to the desired vibration mode.

Another object of the present invention is thus to propose an oscillator circuit with reduced consumption which can easily be integrated in a global system, which does not generate disturbances to the system and which assures that the resonator's oscillations are adequately maintained. In particular, in the case in which the oscillator circuit employs a torsionally vibrating quartz resonator of the aforementioned type, a solution guaranteeing that the torsional vibration mode is maintained in addition to the reduction in consumption is desired.

Yet another object of the present invention is to push the reduction in consumption of the circuit further still and to propose a solution that consumes even less energy.

Another object of the present invention is to propose a method for maintaining the oscillations of a resonator of the aforementioned type guaranteeing, on the one hand, a reduction in consumption, and, on the other hand, that the oscillations of the resonator according to the desired fundamental torsional vibration mode are maintained.

The present invention thus concerns an inverter oscillator circuit whose features are set forth in the claims.

The present invention also concerns a method for maintaining the oscillations of a resonator of the aforementioned type whose features are set forth in the claims.

Advantageous embodiments of the present invention form the subject of the independent claims.

With reference to the aforementioned European Patent Application No. EP 1 111 770 A1, it will be noted as regards the specific resonator arranged to vibrate according to a torsional vibration mode, that the circuit maintaining the resonator's vibrations is arranged to force the resonator to vibrate according to the desired torsional vibration mode and that, in order to do this, the transconductance value of the inverter is chosen to be higher than the maximum transconductance value, designated gm,max, associated with the undesired flexural vibration mode. Since transconductance is normally representative of the current consumed by the circuit, it will thus be understood that the circuit consumes more when it is arranged to force the resonator to vibrate according to the torsional vibration mode than when the same circuit is arranged to vibrate according to the conventional flexural vibration mode.

However, according to the present invention, the inventor has been able to observe that the consumption of the circuit can be reduced once the oscillator circuit is started and its output signal is stable. In particular, it is possible to start the circuit such that the resonator vibrates according to the desired torsional mode satisfying the strict criteria determined by the critical transconductance values defined in the aforementioned European Patent Application, and, at the end of this start-up phase, to reduce consumption while guaranteeing that the resonator still vibrates according to this torsional vibration mode. This reduction in consumption is partially obtained by switching the circuit, during the so-called steady state phase following the start-up phase, into another state where the latter has a reduced transconductance value with respect to the initial transconductance value defined for the start-up.

Advantageously, the inventor has been able to observe that the transconductance value of the inverter may be reduced to a lower value than the critical transconductance value below which the resonator's oscillations in the torsional vibration mode are normally no longer guaranteed. The inventor has thus observed that the critical transconductance values are essentially determining during the resonator start-up phase. For the sake of security, it is nonetheless perfectly possible to envisage keeping the transconductance value of the circuit within a range of values preventing the resonator from vibrating according to the torsional vibration mode.

In addition to reducing consumption in steady state, the present invention also assures that the oscillator circuit starts quickly via the selection of a high transconductance value during this initial phase.

According to the invention, the oscillator circuit is also fitted with means allowing the alternating signal output amplitude to be smoothed during the passage from the start-up phase into steady state, i.e. when the circuit's transconductance value is reduced. This smoothing of the output signal amplitude limits the effects of switching the oscillator circuit's transconductance value and guarantees that the resonator's oscillations are not damped too abruptly in order to ensure that the resonator continues to vibrate according to its desired vibration mode. Moreover, this smoothing facilitates integration of the oscillation circuit into a global system, the disturbances caused by switching the oscillator circuit from one state to another being minimised.

According to other embodiments of the present invention, complementary means are used to reduce the oscillator circuit's consumption in steady state. According to a first of these embodiments, resistive elements are connected in series in the supply path of the inverter circuit. According to another of these embodiments of the invention, the circuit further includes a voltage regulator for lowering the supply voltage of the inverter circuit.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2shows a general functional diagram of an inverter type oscillator circuit constituting a preferred embodiment of the present invention. The inverter oscillator circuit10illustrated inFIG. 2typically includes the parallel arrangement, between input terminal A and output terminal B, of inverter amplifier means including first and second inverters2,3, a resonator1and a resistor4, first and second load capacitors5,6being respectively connected between said input and output terminals A, B, on the one hand, and a supply potential, here VSS, on the other hand. Oscillator circuit10may further include an additional resistive element40, of value R0, arranged between the output of inverters2,3, on the one hand, and resonator1as well as load capacitor6, on the other hand. This optional resistive element40is in particular intended for increasing the stability of the oscillator circuit.

The arrangement of the two inverters2,3is substantially similar to the arrangement illustrated inFIG. 1b, i.e. first inverter2is permanently connected between input and output terminals A and B, whereas second inverter3is able to be connected to or disconnected from these terminals A, B via the action of control circuit8. In this case, second inverter3is activated or deactivated using switching means (namely two switches7aand7bcontrolled by control circuit8) placed in the supply path of the inverter, between supply potentials VDDand VSS.

It will be noted that second inverter3could alternatively be connected to or disconnected from terminals A and B by means of a switch connected in series with this inverter, for example by means of a transmission gate including the parallel arrangement of an n-MOS transistor and a p-MOS transistor connected to each other via their drain and source terminals as is, for example, illustrated inFIG. 5of the Japanese document JP 60-64506 cited in the preamble.

Oscillator circuit10further includes means for smoothing the amplitude of the alternating output signal, designated SOSC, when the oscillator circuit is switched at the end of the start-up phase. These output signal amplitude smoothing means are advantageously made in the form of an amplitude control loop globally designated by the reference numeral9. This amplitude control loop9is connected, on the one hand, to one of the input and output terminals A, B of oscillator circuit10(in this example, input terminal A), and, on the other hand, to first inverter2.

Amplitude control loop9includes, on the one hand, an amplitude control circuit90and, on the other hand, at least one controlled current source91,92(preferably two) connected in the supply path of inverter2. In this example, an input terminal90aof amplitude control90is connected to the input terminal A of the oscillator circuit, and two output terminals90b,90care respectively connected to first and second controlled current sources91,92, placed on either side of inverter2in its supply path. By way of first improvement, each controlled current source91,92is further connected in parallel to a resistive element95,96respectively. We will return to the use of these resistive elements hereinafter.

With reference toFIGS. 3aand3b, the operating principle of the inverter oscillator circuit according to the present invention will now be briefly described.FIG. 3aillustrates schematically the evolution over time of the transconductance value of the oscillator circuit according to the invention. InFIG. 3a, the oscillation conditions are also illustrated in terms of minimum (gm,min—the lower oscillation condition) and maximum (gm,max—the upper oscillation condition) transconductance values for the fundamental flexural (at 74 kHz) and torsional (393 kHz) vibration modes of the resonator taken by way of example in the aforementioned European Patent Application No. EP 1 111 770 A1.FIG. 3billustrates schematically the corresponding evolution of the oscillator's alternating output signal SOSC.

During the start-up phase of the oscillator circuit (phase “1”), the two inverters2,3of the oscillator circuit are connected in parallel such that the circuit has a global so-called start-up transconductance value, designated Gm, of high value. It will be noted in this regard that the choice of a high transconductance value during the initial phase allows the start-up time of the oscillator circuit to be reduced.

In order to set the resonator into vibration according to the desired fundamental torsional vibration mode, the start-up transconductance value Gmof the circuit is selected such that the oscillation conditions of the desired mode (namely the fundamental torsional vibration mode) are satisfied. These conditions are satisfied, in the example illustrated, for a start-up transconductance value Gmcomprised between the higher critical value gm,maxof the undesired flexural vibration mode (at 74 kHz) and the higher critical value gm,maxof the desired torsional vibration mode (at 393 kHz).

By satisfying the aforementioned conditions, the resonator is set in vibration according to the desired torsional vibration mode. As illustrated inFIG. 3b, the amplitude of output signal SOSCgradually increases and the oscillation frequency tends towards a stable state. By convention, it will be said that the oscillations are stabilised at the end of a determined interval of time, designated TSTAB.

At the end of the start-up phase, as soon as the oscillations of the oscillation circuit are stabilised (in steady state, phase “2” in the Figures), second inverter3is deactivated so as to reduce the circuit's transconductance value to a so-called reduced value, designated gm, and thus to reduce the consumption of the circuit. For the sake of security, the reduced transconductance value gm, is preferably determined such that it still satisfies the strict oscillation conditions of the desired torsional vibration mode. The inventor has nonetheless been able to observe that the transconductance value can be reduced to a value that no longer strictly satisfies the aforementioned oscillation conditions. In the example ofFIG. 3a, it is, for example, possible to reduce the transconductance value of the circuit to a value comprised between the higher critical transconductance gm,maxof the undesired flexural vibration mode and the lower critical transconductance gm,minof the desired torsional vibration mode, this possibility being illustrated inFIG. 3aby the curve in dotted lines. It will thus be understood that the present invention allows the consumption of the inverter circuit to be reduced below the consumption level defined by the lower oscillation condition, i.e. the higher critical transconductance value gm,maxof the undesired flexural vibration mode (this value typically being higher than the lower critical transconductance value gm,minof the desired torsional vibration mode).

According to the present invention, the transition from the start-up transconductance value Gmto the reduced transconductance value gmdoes not occur abruptly, but gradually, owing to the addition of the amplitude control loop connected to the first inverter of the oscillator circuit. This results in a gentle and gradual decrease in the amplitude of output signal SOSCas illustrated inFIG. 3b.

With reference again toFIG. 2, it will be noted that the consumption of the oscillator circuit can be further reduced by adding a resistive element95,96in the supply path of first inverter2in parallel with each controlled current source91,92. The effect of the addition of these resistive elements is to limit the maximum current in the supply path of inverter2and thus to further reduce the consumption of the inverter oscillator circuit in steady state.

Also by way of improvement, it is possible to reduce the supply voltage at the terminals of the inverter oscillator circuit, i.e. to generate an intermediate supply potential, designated VR, comprised between supply potentials VDDand VSS.

FIG. 4shows a detailed embodiment of the inverter oscillator circuit ofFIG. 2. For the sake of clarity, resonator1(connected between terminals A and B) and load capacitors5and6(respectively connected to terminals A and B) have not been shown inFIG. 4.

The first and second inverters2,3are CMOS inverters each comprising a p-MOS transistor21,31respectively, whose drain is connected to the drain of an n-MOS transistor22,32respectively. The gates of transistors21,22,31and32are connected to the same node and form input terminal A of the oscillator circuit. The drains of transistors21,22,31,32are connected together to output terminal B, here via additional resistive element40. The feedback resistive element4is connected between the gate connection node and the drain connection node of transistors21,22,31,32. The oscillator circuit output signal (picked up in this example at terminal A) is applied in a typical manner to the input of a shaping stage100for delivering a square output signal.

The source of p-MOS transistor31of second inverter3is connected to high supply potential VDDvia another p-MOS transistor forming switch7a. Likewise, the source of n-MOS transistor32of second inverter3is connected to the low supply potential (here intermediate supply potential VR) via another n-MOS transistor forming switch7b. A control signal designated STARTUP is applied to the gate of n-MOS transistor7band to the gate of p-MOS transistor7a(via an inverter) in order to control their state of conduction and selectively activate or deactivate second inverter3.

The source of p-MOS transistor21of first inverter2is connected to high supply potential VDDvia another p-MOS transistor connected in a resistor configuration (gate potential brought to ground), this p-MOS transistor forming resistive element95ofFIG. 2. A p-MOS transistor forming first controlled current source91is also inserted between the source of p-MOS transistor21and high potential VDDin parallel with transistor95connected as a resistor. Likewise, the source of n-MOS transistor22is connected to low supply potential VRvia an n-MOS transistor connected in a resistor configuration (gate potential brought to high potential) and forms resistive element96ofFIG. 2. An n-MOS transistor forming the second controlled current source92is inserted between the source of n-MOS transistor22and low potential VRin parallel with transistor96connected as a resistor.

P-MOS transistor91and n-MOS transistor92forming the controlled current sources are controlled by amplitude control circuit90whose structure will now be briefly described. It will be noted that those skilled in the art could envisage other configurations for making this amplitude control circuit and that the configuration illustrated should consequently not be considered as a limitation of the invention.

Input terminal A of the oscillator circuit is applied to a terminal of a first capacitive element921, the other terminal of this capacitive element921being connected on the one hand, to the drain of a first p-MOS transistor901and, on the other hand, to the gate of a second p-MOS transistor902. The source of the latter is connected to high potential VDDwhereas its drain is connected to the source of first p-MOS transistor901as well as to the source of a third p-MOS transistor903. The gate and the drain of this third p-MOS transistor903are connected to the gate of first transistor901. The connection node between the drain of p-MOS transistor902and the sources of p-MOS transistors901and903is connected to the gate of a fourth p-MOS transistor904whose source is connected to high supply potential VDD. Second922and third923capacitive elements are also connected via one of their terminals respectively to the drain of p-MOS transistor902and to the drain of p-MOS transistor903, the other terminal of these capacitive elements922and923being connected to high supply potential VDD.

The gate of p-MOS transistor forming first controlled current source91is connected to the gate of fourth p-MOS transistor904, a fifth p-MOS transistor905connected in a capacitor configuration (drain and source terminals connected to high supply potential VDD) being connected via its gate to this same connection between p-MOS transistors91and904. The gate of the n-MOS transistor forming second controlled current source92is connected to the drain of fourth p-MOS transistor904.

The biasing of the transistors of amplitude control circuit90is assured by a biaising current IBPOSC which is mirrored in the branch comprising p-MOS transistor904by means of a current mirror including three n-MOS transistors910,911and912, transistors911and912of the first and second output branches of the current mirror being respectively connected in series with p-MOS transistor903and p-MOS transistor904.

FIG. 5ashows an embodiment example of control circuit8for generating control signal STARTUP intended for switches7aand7b. This control circuit8, made in digital form, essentially includes a bistable trigger circuit (or flip-flop) S-R80and a counter, or divider85. Counter85is clocked by a clock signal CLK (purely by way of illustrative and non-limiting example, a clock signal at 128 Hz derived from the oscillator circuit output signal). A zero reset signal RESET is applied to a zero reset terminal of counter85and to excitation terminal S of bistable trigger circuit80, via an inverter. The counter is arranged to count a determined number of pulses, purely by way of illustrative example, sixteen pulses, and thus defines an interval of time of 16×1/128=125 ms in this example.

As illustrated in the diagram ofFIG. 5b, the switching signal STARTUP thus passes to the high logic level during a determined time interval of duration TSTAB. During this time interval, the oscillator circuit ofFIG. 2is thus switched into the “high transconductance” mode facilitating the quick start-up of the oscillations. As soon as the time interval has elapsed, signal STARTUP passes to the low logic level, thus switching the oscillator circuit ofFIG. 2into the “low transconductance” mode thus reducing the consumption of the circuit.

It will be understood that various modifications and/or improvements evident to those skilled in the art can be made to the embodiment described in the present description without departing from the scope of the invention defined by the annexed claims. For example, the solution based on the principle ofFIG. 1acould also be applied insofar as the amplitude control loop avoids damping of the oscillations when the switch is switched.