Method for inducing strain in FinFET channels

FinFETs in which a swelled material within the fin, typically an oxide of the fin semiconductor, causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source and drain regions. For n-type FinFETs the swelled material is positioned underneath the channel region. The swelled material can be used with or without strain-inducing epitaxy on the source and drain areas and can provide greater strain than is achievable by strain-inducing epitaxy alone.

FIELD OF THE INVENTION

The present disclosure relates to FinFETs for integrated circuit devices and methods of manufacturing them.

BACKGROUND

The semiconductor industry's drive for higher device densities, better device performance, and lower cost has led to the development of integrated circuit transistors that are three-dimensional in the sense of making greater use of space perpendicular to the substrate surface. One such transistor is the multigate field-effect transistor, aka MuGFET, trigate FET, gate-all-around FET, pi-gate FET, omega-gate FET or FinFET. The name “FinFET” as used herein refers to all of these devices. A FinFET is a field effect transistor (FET) having a channel formed in a fin-like structure of semiconductor extending from a substrate surface. This channel geometry allows the gate to wrap around one or more sides of the channel and/or act on the channel from its sides. This improves control over the channel and reduces short channel effects in comparison to a more conventional structure in which a single plane separates the channel from its gate. The fin-like structure also allows the channel to be extended vertically, increasing its cross-sectional area and permitting a higher current without increasing the transistor's footprint.

Another way to permit a transistor to support a higher current without increasing its footprint is to induce strain in the channel. A compressive strain increases charge carrier mobility in a p-type metal oxide semiconductor field effect transistor (pMOS) channel and a tensile strain increases charge carrier mobility in an n-type metal oxide semiconductor field effect transistor (nMOS). Channel strain is typically induced by forming trenches in the source and drain regions adjacent the channel and epitaxially growing within the trenches a semiconductor having a lattice constant different from that of the channel. SiGe has a larger lattice constant than silicon and can be grown in the source and drain regions to induce compressive strain for silicon-based pMOS devices. SiP or SiC has a smaller lattice constant than silicon and can be grown in the source and drain regions to induce tensile strain for silicon-based nMOS devices.

DETAILED DESCRIPTION

The present disclosure provides integrated circuit devices in which a swelled material, typically an oxide, within a FinFET fin causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source and drain regions. For n-type FinFETs the swelled material is positioned underneath the channel region. The swelled material can be used with or without strain-inducing epitaxy on the source and drain areas and can provide greater strain than is achievable by strain-inducing epitaxy alone.

Stress on a solid material necessarily results in strain. The strain resulting from stress that reaches at least 0.5 GPa in any one direction at some point within the channel is generally sufficient to provide a significant increase in charge carrier mobility, provided the strain is compressive for a p-type FinFET and tensile for an n-type FinFET. These stresses correspond approximately to a 0.5% change in the distance between atomic planes, a distance that can be determined using high-resolution transmission electron microscopy (TEM).

FIG. 1provides an example of a p-type FinFET10provided by the present disclosure according to one embodiment.FIG. 3provides an example of a n-type FinFET20according to one embodiment. These two examples include many of the same elements. The description of elements included in p-type FinFET10generally applies to like numbered elements of n-type FinFET20except where differences are noted. A single integrated circuit device can contain many of either or both types of FinFETs. In one embodiment, an integrated circuit device contains p-type FinFETs10and n-type FinFETs20, both having stress-inducing swelled material as described herein.

The FinFET10include a semiconductor fin29on a semiconductor21. The fin29includes a source region33at one end, a drain region39at the other end, and a channel region45in between. These regions are in an upper portion44of the fin29. A gate42wraps around the channel region45.FIG. 1includes a cutaway37in which gate42and spacer31have been removed from the view to reveal part of the channel region45of the fin29. The gate42includes a dielectric layer43and a conductive layer41. Spacers31are formed to either side of the gate42.

A swelled material25is positioned within regions27in a lower portion46of the fin29. An upper portion44of the fin29overhangs the regions27. In the p-type FinFET10, the swelled material25is positioned under the source region33and the drain region39of the fin29, but is not present under the channel region45. As shown inFIG. 3, for the n-type FinFET20the situation is reversed in that the swelled material25is positioned under the channel region45but not under the source region33or the drain region39.

FIG. 2illustrates the stresses49and the resulting strains47caused by the swelled material25underneath the source region33and drain region39of the p-type FinFET10. The p-type FinFET10is generally one element in an array of like elements, which is why the direction of the stresses49becomes vertical at the left and right limits of the view provided inFIG. 2. The resulting strains47are compressive in the channel region45of the p-type FinFET10.

FIG. 4illustrates the stresses49and the resulting strains47caused by the swelled material25underneath the channel region45of the n-type FinFET20according to one embodiment. The stresses49produced by the swelled material25in the n-type FinFET20are upward into the channel region45and outward. The upward stresses are partially relieved by upward deformation (not shown) of the channel region45. The overall effect is that the stresses47in the channel region45of the n-type FinFET20are tensile.

A swelled material is one having undergone a chemical transformation subsequent to its emplacement, the chemical transformation being one that causes expansion. A swelled material in an integrated circuit device structure can be identified by its physical effect on surrounding structures and by a chemical composition consistent with the material having been swelled. In general, in one embodiment the swelled material is an oxidized form of a semiconductor and the chemical transformation is an oxidation reaction.

The present disclosure also provides a method of inducing strain in a FinFET's channel. The upper portion of the fin is masked through the entire fin length. A lower portion of the fin is also masked, but only through a first portion of the fin length that is less than the entire length of the fin. The lower portion of the fin is left exposed through a second portion of the fin length. The fin is oxidized where it is exposed. The oxidation produces an expansion of material within a portion of the fin that is within the second portion of the fin length and under the upper portion of the fin. The oxidation and resulting expansion proceeds to a degree that causes strain in the channel, the strain being sufficient to cause a significant increase in charge carrier mobility within the channel.

FIG. 5is a flow chart of an example process100that can be used to form an integrated circuit device that has p-type FinFETs10in pMOS regions and n-type FinFETs20in nMOS regions. The portions of the process100that produce the p-type FinFETs10can be used separately from the portions of the process100that produce the n-type FinFETs20. However, many of the acts that produce the p-type FinFETs10are the same as the acts that produce the n-type FinFETs20. In the following description, acts that are illustrated in terms of how they form the p-type FinFETs10are also applied to forming the n-type FinFETs20except as an optional alternative or where differences between the treatment of p-type and n-type FinFETs are noted.

The process100begins with a series of acts110that form the fin29. The first act111is providing and preparing the semiconductor21. Preparing the semiconductor21can include doping to provide separate n-doped and p-doped regions of the semiconductor21for the p-type FinFETs10and n-type FinFETs20respectively.

The semiconductor21can have any suitable composition. Examples of semiconductors that can be suitable include, without limitation, Si, Ge, SiC, GaAs, GaAlAs, InP, GaN, or other II-V compound semiconductors and SiGe. The semiconductor substrate21can be provided on any suitable substrate. A suitable substrate can be, for example, a single crystal semiconductor wafer or semiconductor on insulator (SOI) structure.

Act112forms a hard mask51over the semiconductor21. Act113is patterning the mask51according to the desired locations and dimensions for fins29. The resulting structure is illustrated byFIG. 7according to one embodiment. Patterning can be accomplished by any suitable process, but typically includes photolithography and etching. Act114is etching the semiconductor21to form fins29to the pattern of the mask51as shown inFIG. 8. Act115deposits a layer of field oxide23over and around the fins29. Act116planarizes the field oxide23to the height of the mask51, whereby the fins29are encased within the field oxide23as shown inFIG. 9. Planarization can be accomplished by any suitable process. A planarization process is typically chemical-mechanical polishing (CMP).

The process110can proceed directly with the series of acts120, which form a mask56that covers an upper portion44of the fins29. Alternatively, additional acts can be undertaken to provide fins29with multiple strata having differing compositions.FIG. 6provides a flow chart for an alternate fin formation process210that provides fins29with multiple strata. The example process210is a HARP (high aspect ratio) epitaxial process in which an upper portion of the fins29is removed and replaced with materials of differing composition according to one embodiment.

Process210ofFIG. 6begins to differ from process110with act216, planarization. In the case of process210, planarization216proceeds to the extent of removing the hard mask51to produce the structure shown inFIG. 10. Part of the fin29is then etched away in act217to lower the height fin29and provide a void52in the field oxide23as shown inFIG. 11.

Act218forms a first layer29A that approximately corresponds to the lower portion46of the fin29. The resulting structure is illustrated byFIG. 12. Act219forms a second layer29B that approximately corresponds to the upper portion44of the fin29. The resulting structure is illustrated byFIG. 13. The layers29A and29B can be formed by any suitable process, but are generally formed by epitaxial growth to provide continuity in the crystal structure of the fin29.

The layer29A is formed to a different composition from that of the semiconductor21and the upper layer29B. The composition can be selected to facilitate swelling. In some embodiments, the composition of the layer29A is selected to have a higher oxidation rate than that of the upper layer29B to allow oxidation to be carried out at a comparatively lower temperature. For example the layer29A can be SiGe while the upper layer29B is Si. SiGe oxidizes more than 10 times faster than Si. In some embodiments, the composition of the layer29A is selected to have a higher oxidation rate than the semiconductor21. The compositions can be separately determined for n-type and p-type FinFETS. nMOS regions of the semiconductor21can be masked while one or both the layers29A and29B are grown in pMOS regions of the semiconductor21and vice versa.

The process210continues with act220, planarizing such as chemical mechanical polishing. After CMP, an etch process can be used to form the recess32shown inFIG. 14. A hard mask layer55as shown inFIG. 15is then formed with act221followed by act222, planarization to remove the hard mask layer55except where it fills the recess32. The resulting structure, shown inFIG. 16, is essentially the same as the structure shown inFIG. 9except for the difference in composition of the fin29.

The process100ofFIG. 5continues with a series of acts120that form a mask over the upper portion44of the fin29. Act121is an etch that recesses the field oxide23to expose the upper portion44of the fin29while leaving the field oxide23at the height of the lower portion46of the fin29. Where the fin29has a stratified composition, the field oxide23is recessed to approximately the same height as the juncture between the layers29A and29B as illustrated inFIG. 17. Act122then forms a mask56covering the sides of the upper portion44of the fin29as show inFIG. 18. The mask56can be formed by any suitable process. A suitable process can be one otherwise used to form spacers, for example a blanket deposition of the spacer material followed by anisotropic etching. The mask56can have any suitable composition, but is typically a nitride, SiON for example.

After forming the mask56, act123further recesses the field oxide23to expose the lower portion46of the fin29as shown inFIG. 19. Act124forms a thin oxide layer57over the exposed portions of the fin29, which is also shown inFIG. 19. Thin oxide layer57protects the fin29, such as by providing an etch stop layer for when a dummy gate is later removed in a gate replacement process. The oxide layer57is too thin to cause significant strain in the channel region45of the fin29.

The process100continues with a series of acts130that form a dummy gate61over the channel region45of the fin29. Act131is forming a dummy gate stack. The dummy gate stack includes sacrificial material and optionally one or more additional layers. The additional layers can include interfacial layers, etch stop layers, and or dielectric layers. If n-type FinFETs20with strain-inducing expanded material25are not required, the dummy gate61can be a functional gate42or include one or more layers that will form part of the functional gate42, such as the dielectric layer43. The sacrificial material is typically polysilicon, but any suitable material can be used. Act132planarizes the dummy gate stack61and act133forms a mask layer59over the dummy gate stack61to provide the structure shown inFIG. 20. Act134patterns the dummy gate stack61to form the structure shown inFIG. 21.

Act134forms spacers31as shown inFIG. 22. Any suitable spacer formation process can be used. The spacer material also deposits on the sides of fin29in source areas33and the drain areas39.FIG. 22shows this as an extension of the mask56, although the mask56and the spacers31could be formed from different materials.

The process100ofFIG. 5continues with a series of acts140by which the swelled material25is formed under the source regions33and the drain regions39of the p-type FinFETs10. Swelled material at these locations is not desired for the n-type FinFETs20. Accordingly, act141is masking any nMOS regions of the semiconductor21. Act142is a third oxide recess to expose the fin29below the area that is masked by the spacer material as shown inFIG. 22A. Act142can take place before act141if this further oxide recess is desired for the n-type FinFETs20. Act143converts exposed material of the fin29into swelled material25via oxidation. The channel area45of fin29is masked by dummy gate61and spacers45. The upper portion44of the fin29is protected by masks55and56. The swelled material25forms only in the lower portion46of the fin29and only under the source regions33and the drain regions39of the fin29.

Act143is oxidation that converts semiconductor of the fin29to an oxidized form, which is the swelled material25as shown inFIG. 23. The swelled material25has greater volume than its reduced state. The expansion of this material within the body of fin29creates stresses and strain. Oxidation progresses through an appreciable portion of the thickness of the fin29. The regions27of the fin29in which the swelled material25forms generally penetrate at least 15% of the thickness of the fin29in order to provide an appreciable strain in the channel region45. The regions27can be viewed as hollows in the semiconductor of the fin29, hollows that are overhung by upper portions of the fin29and that are filled with swelled (oxide) material. In one embodiment, oxidation proceeds through the full thickness of the fin29, whereby the regions27on either side of the fin29meet, completely undercutting the source region33and the drain region39of the fin29. In another embodiment, however, oxidation proceeds less than 100% of the way through the thickness whereby the upper portion44of the fin29remains rigidly connected to the semiconductor21underneath through the entire lengths of the source region33and the drain region39. The height of the regions27is generally in the range from 5 nm to 10 nm.

The process100continues with a series of acts150that increase the area available for source and drain contacts through epitaxial growth. Act151removes the hard mask55and56from the source region33and the drain region39of the fin29as shown inFIG. 24. Acts151and152can be combined in a single etch step that removes both nitride caps and some of the source and drain semiconductor. Some semiconductor material is left above the swollen regions25produced by oxidation Act152creates recesses65within the fin29in the source region33and the drain region39as shown inFIG. 25. Act152generally leaves the upper fin44with at least 10 nm thickness remaining.

Act153is epitaxial growth of a semiconductor63on the source regions33and the drain regions39of p-type FinFETs10to provide a structure as shown inFIG. 26. Where the recesses65have been formed, the semiconductors63is generally selected to have a larger lattice constant than the semiconductor of the channel region45. For example, when the channel region45is silicon, the semiconductor63could be SiGe.

Act154is epitaxial growth of a semiconductor63on the source region33and the drain region39of n-type FinFETs20. Where the recesses65have been formed, the semiconductors63for the nMOS regions is generally selected to have a smaller lattice constant than the semiconductor of the channel region45. For example, when the channel region is silicon, the semiconductor63could be SiP or SiC for the nMOS regions. Where epitaxial growth in the source regions33and the drain regions39is not used to create additional stress in the channel regions45, acts153and154can be combined.

Act155deposits additional field oxide23. Act157planarizes the oxide to produce a structure as shown inFIG. 27. The additional field oxide23provides a level surface for forming mask layers in subsequent steps.

The process100continues with a series of acts160by which the swelled material25is formed under the channel regions45of the n-type FinFETs20. Swelled material at these locations is not desired for the p-type FinFETs10. Accordingly, act161is masking any pMOS regions of the semiconductor21. Act162removes the dummy gate stack61in the nMOS regions to produce a structure as shown inFIG. 28.FIG. 29is a side view of this same structure.

Act163converts exposed material of the fin29into swelled material25via oxidation. For act163, the source regions33and the drain regions39of fin29are masked by field oxide23and spacers45. The upper portion44of the fin29is protected by masks55and56. The swelled material25forms only in the lower portion46of the fin29and only under the channel region45. The resulting structure is shown inFIG. 30. The comments concerning the thickness and height of the regions27are the same as for the pMOS areas, although the particular values for these parameters, particularly the thickness to which the swelled material25is formed, may be selected separately for the pMOS and nMOS areas.

The process100continues with a series of acts170that complete the gate replacement process. Act171removes the masks55and56from the channel region45of the n-type FinFETs20as shown inFIG. 31. The replacement gate is then formed to produce the structure shown inFIG. 32. This is the same structure as shown byFIG. 3in a perspective view. The view ofFIG. 3omits an upper portion of the field oxide23or the epitaxial grown semiconductor63to provide a better view of the underlying structures. The structure ofFIG. 1is also arrived at following act173. It should be understood that additional processing generally occurs before, during, and after the illustrated actions of the process100to complete the device formation.

Computer simulations and experiments show that the FinFETs10produced by the process100can exhibit stresses of 2 GPa in the channel region45resulting in a 4% linear deformation. Stresses above 0.95 GPa could not be achieved without the swelled material25. In most embodiment of the present disclosure, the stress is greater than 1.0 GPa. In some embodiment of the present disclosure, the stress is greater than 2.0 GPa.

The field oxide23can be formed from any suitable dielectric and can include multiple layers of different dielectrics. A suitable dielectric for field oxide23can be, for example, silicon oxide derived from tetraethyl orthosilicate (TEOS) or silane. In some embodiments, the field oxide23is a low-k dielectric material. Examples of low-k dielectric materials include fluorinated silicon oxide, siloxane SOG (spin-on glass), and polyimides.

The dielectric layer43can be formed of any suitable dielectric and can include multiple layers of different dielectrics. SiO2can be used. In some embodiments, the dielectric layer43is a high-k dielectric layer. A high-k dielectric is one having a conductivity at least 5 times that of silicon dioxide. Examples of high-k dielectrics include hafnium-based materials such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, and HfO2—Al2O3alloy. Additional examples of high-k dielectrics include, without limitation, ZrO2, Ta2O5, Al2O3, Y2O3, La2O3, and SrTiO3.

The conductive layer41can also be made up of any suitable material and can include multiple layers of different materials. In some embodiments, particularly those in which a high-k dielectric is used, the conductive layer41is one or more metal layers. A metal layer41generally includes at least one layer of Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, and MoON. Additional examples of materials for conductive metal layers include ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, aluminum, and conductive carbides, oxides, and alloys of these metals.

An integrated circuit device is disclosed in which a swelled material, typically an oxide, is formed underneath the source region33and the drain region39of a p-type FinFET10. The device employs the swelled material to be disposed in such a way and swelled to such an extent that it stresses the channel region to the extent of causing a significant increase charge carrier mobility within the channel45.

An integrated circuit device in which the swelled material is formed underneath the channel region45of an n-type FinFET20is disclosed. The device employs the swelled material in such a way and swelled to such an extent that it stresses the channel region to the extent of causing a significant increase charge carrier mobility within the channel45.

A process by which an integrated circuit according to either above embodiment is disclosed. An upper portion44of a fin29is masked. A lower portion46of the fin29is also masked, but only along a portion of the fin length so as to leave the lower portion46exposed in some areas. The fin29is then oxidized where it is exposed, the oxidation causing a portion25of the material within the fin29to expand and exert stress on surrounding areas, including the channel region45of the fin29. The oxidation and expansion proceeds to a degree that causes strain within the channel45, the amount of strain being sufficient to cause a significant increase in charge carrier mobility within the channel45.

The invention as delineated by the following claims has been shown and/or described in terms of certain concepts, components, and features. While a particular component or feature may have been disclosed herein with respect to only one of several concepts or examples or in both broad and narrow terms, the components or features in their broad or narrow conceptions may be combined with one or more other components or features in their broad or narrow conceptions wherein such a combination would be recognized as logical by one of ordinary skill in the art. Also, this one specification may describe more than one invention and the following claims do not necessarily encompass every concept, aspect, embodiment, or example described herein.