Signal output adjustment circuit and display driver

A signal output adjustment circuit includes a decoder which decodes command data from a memory, a control register in which control data corresponding to first command data is set when the decoder determines that the command data is the first command data, a buffer in which the control data corresponding to second command data is stored when the decoder determines that the command data is the second command data, and an output adjustment circuit which reads the control data stored in the buffer and outputs the control data in synchronization with a data fetch signal, based on a value set in the control register. At least one of permission/rejection of inversion output of the data fetch signal and output timing of the data fetch signal is set based on the value set in the control register.

Japanese Patent Application No. 2003-310534, filed on Sep. 2, 2003, is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a signal output adjustment circuit and a display driver.

An electro-optical device represented by a liquid crystal display device includes an electro-optical panel which includes a plurality of data lines and a plurality of scan lines. A scan line of the electro-optical panel is scanned by a scan driver, and a data line of the electro-optical panel is driven by a data driver. The electro-optical device may include a power supply circuit which provides a power supply to the electro-optical panel, the data driver, and the scan driver. As described above, the electro-optical device is formed by a plurality of devices, and these devices are electrically connected through interconnects.

BRIEF SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided a signal output adjustment circuit which adjusts output of control data corresponding to command data, the signal output adjustment circuit comprising:

a decoder which decodes the command data read from a memory;

a control register in which control data corresponding to first command data is set when the decoder determines that the command data is the first command data for setting control data;

a buffer in which control data corresponding to second command data is stored when the decoder determines that the command data is the second command data for outputting control data; and

an output adjustment circuit which reads the control data stored in the buffer and outputs the read control data in synchronization with a data fetch signal, based on a value set in the control register,

wherein the output adjustment circuit sets at least one of permission/rejection of inversion output of the data fetch signal and output timing of the data fetch signal, based on the value set in the control register.

According to another aspect of the present invention, there is provided a signal output adjustment circuit which adjusts output of a clock signal, the signal output adjustment circuit comprising:

a decoder which decodes command data read from a memory;

a control register in which control data corresponding to the command data is set based on a decoding result of the decoder; and

an output adjustment circuit which outputs a clock signal based on a value set in the control register,

wherein the output adjustment circuit outputs the clock signal of which at least one of frequency, phase, permission/rejection of inversion output, and output timing is set based on the value set in the control register.

According to a further aspect of the present invention, there is provided a display driver which drives a data line of an electro-optical device based on display data, the display driver comprising:

a data register which fetches the display data based on a given dot clock signal, the display data being serially input in pixel units in synchronization with the dot clock signal;

a line latch which latches the display data fetched by the data register based on a horizontal synchronization signal which determines one horizontal scan period;

a data line driver circuit which drives the data line based on the display data latched by the line latch; and

one of the above described signal output adjustment circuits,

wherein one of the reference clock signals is one of the dot clock signal, the horizontal synchronization signal, and a vertical synchronization signal which determines one vertical scan period.

DETAILED DESCRIPTION OF THE EMBODIMENT

Embodiments of the present invention are described below. Note that the embodiments described below do not limit the scope of the invention defined by the claims laid out herein. In addition, not all of the elements of the embodiments described below should be taken as essential requirements of the present invention.

In the case where each device is formed as a semiconductor chip, the input or output interface specification generally differs depending on the manufacturer. Therefore, in the case of forming an electro-optical device using a plurality of devices, it is generally necessary to select devices manufactured by the same manufacturer so that the interface specification is the same. Therefore, it is desirable that the manufacturer of each device provides a device which can absorb the difference in the interface specification.

In the case of absorbing the difference in the interface specification, a timing adjustment circuit including a register which stores a timing regulation value, a counter, a comparison circuit, and a latch circuit may be used. In this timing adjustment circuit, the comparison circuit compares the counter value of the counter with the timing regulation value stored in the register. The latch circuit latches data output from the unit in the preceding stage based on the comparison result, and outputs the latched data. This enables timing regulation of data to be realized, whereby data can be transferred between two devices having different interface specifications without causing errors to occur.

However, the above-described timing adjustment circuit adjusts only the timing of data transferred between the two devices. The interface specification of the device specifies a positive logic or negative logic, phase, output timing, and the like other than DC characteristics dependent on the circuit. If even one of the interface specifications differs, data cannot be transferred without causing errors to occur. Therefore, the above-described timing adjustment circuit may not allow data to be transferred between two devices without causing errors to occur.

A data driver (display driver in a broad sense), a scan driver, and a power supply circuit for driving the electro-optical device are controlled by a display controller. In this case, the data driver may set control data to the scan driver or the power supply circuit based on command data read from an external memory or command data set by the display controller. Therefore, it is desirable that the data driver be able to absorb the difference in the interface specification between the data driver and the scan driver or the power supply circuit.

According to the following embodiments, a signal output adjustment circuit and a display driver for providing a generalized device by absorbing the difference in AC characteristics from other devices can be provided.

According to one embodiment of the present invention, there is provided a signal output adjustment circuit which adjusts output of control data corresponding to command data, the signal output adjustment circuit comprising:

a decoder which decodes the command data read from a memory;

a control register in which control data corresponding to first command data is set when the decoder determines that the command data is the first command data for setting control data;

a buffer in which control data corresponding to second command data is stored when the decoder determines that the command data is the second command data for outputting control data; and

an output adjustment circuit which reads the control data stored in the buffer and outputs the read control data in synchronization with a data fetch signal, based on a value set in the control register,

wherein the output adjustment circuit sets at least one of permission/rejection of inversion output of the data fetch signal and output timing of the data fetch signal, based on the value set in the control register.

In the embodiment of the present invention, the first command data and the second command data are stored in the memory in advance, and the first and second command data are read from the memory. The decoder decodes the command data, and sets the control data corresponding to the decoded command data in the control register or the buffer. The output adjustment circuit outputs the control data read from the buffer in synchronization with the data fetch signal of which at least one of permission/rejection of inversion output and output timing is set based on the value set in the control register. This enables the signal output adjustment circuit to change switching of the positive logic or negative logic and the output timing of the control data. Therefore, the control data can be supplied corresponding to the input interface specification of a circuit to which the control data is supplied. Therefore, a generalized device can be provided by changing the output interface specification of a device including the signal output adjustment circuit.

In the signal output adjustment circuit, the output adjustment circuit may include:

a data phase selection circuit which selects one of a plurality of phase clock signals of different phases based on the value set in the control register;

a data-signal-output-logic-level conversion circuit which outputs the one of the phase clock signals selected by the data phase selection circuit or an inverted signal of the selected phase clock signal, based on the value set in the control register; and

a data output control circuit which generates the data fetch signal by delaying output from the data-signal-output-logic-level conversion circuit for a period corresponding to the value set in the control register.

According to the embodiment of the present invention, the above-described effects can be obtained with a simple configuration.

In the signal output adjustment circuit, the data fetch signal may be a signal in synchronization with a given clock signal, and

the output adjustment circuit may output the clock signal of which at least one of frequency, phase, permission/rejection of inversion output, and output timing is set based on the value set in the control register.

In the embodiment of the present invention, the frequency, phase, permission/rejection of inversion output, and output timing of the clock signal with which the data fetch signal is in synchronization is set based on the value set in the control register, and the clock signal is output. This enables the output interface specification of the control data to be changed corresponding to the supply target of the clock signal, whereby a generalized device can be provided by changing the output interface specification of a device including the signal output adjustment circuit.

According to another embodiment of the present invention, there is provided a signal output adjustment circuit which adjusts output of a clock signal, the signal output adjustment circuit comprising:

a decoder which decodes command data read from a memory;

a control register in which control data corresponding to the command data is set based on a decoding result of the decoder; and

an output adjustment circuit which outputs a clock signal based on a value set in the control register,

wherein the output adjustment circuit outputs the clock signal of which at least one of frequency, phase, permission/rejection of inversion output, and output timing is set based on the value set in the control register.

In the embodiment of the present invention, the command data is stored in the memory in advance, and the command data is read from the memory. The decoder decodes the command data, and the control data corresponding to the decoded command data is set in the control register or the buffer. The output adjustment circuit sets at least one of the frequency, phase, permission/rejection of inversion output, and output timing of the clock signal based on the value set in the control register, and outputs the clock signal. This enables the timing of the clock signal to be changed corresponding to the supply target, whereby the device which includes the signal output adjustment circuit and supplies the clock signal of which the output is adjusted as described above can be generalized.

In the signal output adjustment circuit, the output adjustment circuit may include:

a clock phase selection circuit which selects one of a plurality of phase clock signals of different phases based on the value set in the control register;

a clock-output-logic-level conversion circuit which outputs the one of the phase clock signals selected by the clock phase selection circuit or an inverted signal of the selected phase clock signal, based on the value set in the control register; and

a clock output circuit which delays output from the clock-output-logic-level conversion circuit for a period corresponding to the value set in the control register, and outputs the delayed output as the clock signal.

According to the embodiment of the present invention, the above-described effects can be obtained with a simple configuration.

In the signal output adjustment circuit,

the output adjustment circuit may include:

a reference clock selection circuit which selects one of a plurality of reference clock signals having different frequencies based on the value set in the control register; and

an N-phase clock generation circuit (N is an integer of two or more) which generates N-phase clock signals of different phases based on a frequency-divided clock signal generated by dividing a frequency of the one of the reference clock signals selected by the reference clock selection circuit, and

the N-phase clock signals generated by the N-phase clock generation circuit may be supplied to the reference clock selection circuit or the data phase selection circuit.

According to the embodiment of the present invention, the N-phase clock signals can be generated with a simple configuration.

In the signal output adjustment circuit,

the N-phase clock generation circuit may generate the N-phase clock signals of different phases based on the frequency-divided clock signal generated by dividing the frequency of the one of the reference clock signals selected by the reference clock selection circuit at a dividing ratio which is set based on the value set in the control register.

According to the embodiment of the present invention, since the variation of the N-phase clock signals can be increased, the interface specification can be changed more minutely.

In the signal output adjustment circuit, the memory may be a nonvolatile memory.

According to the embodiment of the present invention, control can be simplified by performing the above-described output regulation by using the command data at the time of initialization or the like, whereby the device including the signal output adjustment circuit can be further generalized.

According to a further embodiment of the present invention, there is provided a display driver which drives a data line of an electro-optical device based on display data, the display driver comprising:

a data register which fetches the display data based on a given dot clock signal, the display data being serially input in pixel units in synchronization with the dot clock signal;

a line latch which latches the display data fetched by the data register based on a horizontal synchronization signal which determines one horizontal scan period;

a data line driver circuit which drives the data line based on the display data latched by the line latch; and

one of the above described signal output adjustment circuits,

wherein one of the reference clock signals is one of the dot clock signal, the horizontal synchronization signal, and a vertical synchronization signal which determines one vertical scan period.

In the display driver, the output adjustment circuit may output the control data or the clock signal to at least one of a power supply circuit which provides a power supply of the electro-optical device and a scan driver which scans a scan line of the electro-optical device.

According to the embodiment of the present invention, a display driver which can be applied to an electro-optical device on which a power supply circuit or scan driver is mounted irrespective of the input interface specification of the power supply circuit or the scan driver can be provided. This reduces cost of the display driver and also reduces cost of the electro-optical device to which the display driver is applied.

The embodiments of the present invention are described below in detail with reference to the drawings.

1. Signal Output Adjustment Circuit

FIG. 1shows a schematic diagram of the connection relationship of a signal output adjustment circuit in the present embodiment.

A signal output adjustment circuit100in the present embodiment adjusts output of control data or output of a clock signal which is generated based on command data based on the command data stored in a memory10. The control data is data corresponding to the command data. The adjusted control data or clock signal is supplied to a signal processing circuit20. The signal processing circuit20performs given processing based on the control data or clock signal supplied from the signal output adjustment circuit100. This enables the output interface specification of the signal output adjustment circuit100to conform to the input interface specification of the signal processing circuit20, whereby a semiconductor device (device or IC) including the signal output adjustment circuit100can be provided with versatility.

FIGS. 2A,2B,2C, and2D show schematic diagrams of a configuration example of a semiconductor device including the signal output adjustment circuit100. Sections the same as the sections shown inFIG. 1are denoted by the same symbols. Description of these sections is appropriately omitted.

InFIG. 2A, a semiconductor device30includes the signal output adjustment circuit100. In this case, the signal output adjustment circuit100is connected with the memory10and the signal processing circuit20provided outside the semiconductor device30. InFIG. 2B, a semiconductor device32includes the signal output adjustment circuit100and the memory10. In this case, the signal output adjustment circuit100is connected with the signal processing circuit20provided outside the semiconductor device32. InFIG. 2C, a semiconductor device34includes the signal output adjustment circuit100and the signal processing circuit20. In this case, the signal output adjustment circuit100is connected with the memory10provided outside the semiconductor device34. InFIG. 2D, a semiconductor device36includes the signal output adjustment circuit100, the memory10, and the signal processing circuit20. InFIGS. 2C and 2D, in the case where the signal processing circuit20is macronized and the interface specification is fixed, interface design can be simplified by using the signal output adjustment circuit100.

FIG. 3shows an outline of a configuration of the signal output adjustment circuit100in the present embodiment.

The signal output adjustment circuit100includes a decoder110, a control register120, a buffer130, and an output adjustment circuit140. The command data is stored in advance in the memory10connected with the signal output adjustment circuit100. The command data includes first command data for setting the control data in the signal output adjustment circuit100, and second command data for outputting the control data to the signal processing circuit20.

The decoder110decodes the command data read from the memory10. The control register120stores the control data corresponding to the first command data. In more detail, when the decoder110determines that the command data read from the memory10is the first command data, the control data corresponding to the first command data is set in the control register120.

The control data corresponding to the second command data is stored in the buffer130. In more detail, when the decoder110determines that the command data read from the memory10is the second command data, the control data corresponding to the second command data is set in the buffer130.

The output adjustment circuit140reads the control data stored in the buffer130based on the value set in the control register120, and outputs the control data to the signal processing circuit20. In this case, the control data stored in the memory region of the buffer130corresponding to the value set in the control register120is read. The output adjustment circuit140outputs the control data read from the buffer130to the signal processing circuit20in synchronization with a data fetch signal of which at least one of output timing and permission/rejection of inversion output is set based on the value set in the control register120.

The output timing of the data fetch signal may be referred to as a delay time from a reference point of time (reference timing). The delay time may be associated with the number of given clock signals. The delay time is set based on the value set in the control register120. The permission/rejection of inversion output of the data fetch signal means permission for non-inversion output of the data fetch signal or permission for inversion output of the data fetch signal. The output adjustment circuit140outputs the data fetch signal or its inverted signal based on the value set in the control register120. Therefore, in the case of outputting the control data in synchronization with the data fetch signal, the control data can be output in synchronization with the rising edge or falling edge of the data fetch signal.

The output adjustment circuit140can output a clock signal generated based on the value set in the control register120. In more detail, the output adjustment circuit140outputs the clock signal of which at least one of the frequency, phase, permission/rejection of inversion output, and output timing is set based on the value set in the control register120to the signal processing circuit20.

The frequency of the clock signal may be referred to as the number of cycles of the clock signal per unit time. The phase of the clock signal may be referred to as the temporal difference from a reference clock signal at a certain point. The permission/rejection of inversion output of the clock signal means permission for non-inversion output of the clock signal or permission for inversion output of the clock signal. The output timing of the clock signal may be referred to as a delay time from a reference point of time. The delay time may be associated with the number of clock signals. The delay time is set based on the value set in the control register120.

As described above, the signal output adjustment circuit100can adjust the output of the control data or clock signal to the signal processing circuit20based on the value set in the control register120. The value set in the control register120and the control data are data corresponding to the command data stored in the memory10. Therefore, the signal output adjustment circuit100may include a memory control circuit170for accessing the memory10.

The memory10is desirably a nonvolatile memory. The control data or the clock signal can be output corresponding to the interface specification of the signal processing circuit20by storing the command data corresponding to the signal processing circuit20in the memory10in advance, and reading the command data from the memory10each time initialization occurs. The following description illustrates the case of using an electrically erasable programmable read only memory (EEPROM) in which data can be electrically rewritten as the memory10.

FIG. 4shows an explanatory diagram of the EEPROM. An address/data division bus and a clock line are connected with the EEPROM. The address/data division bus and the clock line are connected with the signal output adjustment circuit100(memory control circuit170).

FIG. 5shows a timing diagram of an example of read control of the EEPROM.

The memory control circuit170outputs address data A to the address/data division bus and outputs one pulse of the clock signal to the clock line to set the address data A in the EEPROM. The address data A is the address on the memory space of the EEPROM in which the command data read by the memory control circuit170is stored.

The memory control circuit170then sequentially supplies the clock signal to the clock line. The EEPROM increments the fetched address data A in synchronization with the clock signal. The stored data (command data) corresponding to the address data A is output to the address/data division bus in synchronization with the clock signal on the clock line.

FIG. 6shows an example of the memory space of the EEPROM.

The memory space of the EEPROM is divided into a plurality of blocks. Each block is specified by a head address. The first block is specified by a head address AD1. The second block is specified by a head address AD2. At least one piece of command data is stored in each block.

The memory control circuit170performs read control of the command data in block units. In the case of reading the command data stored in the nth block (n is a positive integer) specified by the head address ADn as shown inFIG. 6, the memory control circuit170outputs the address data of the head address ADn to the address/data division bus and outputs one pulse of the clock signal to the clock line to set the head address ADn in the EEPROM. The memory control circuit170then sequentially supplies the clock signal to the clock line. The EEPROM increments the fetched address data of the head address ADn in synchronization with the clock signal. The command data stored in the nth block specified by the head address ADn is output to the address/data division bus in synchronization with the clock signal on the clock line.

The decoder110shown inFIG. 3sequentially decodes the command data read from the EEPROM by using the memory control circuit170.

FIG. 7shows a configuration example of the command data. In this example, the command data is read from the EEPROM in units of S bits (S is a positive integer).

FIG. 8shows an example of the command data.FIG. 8shows an example of the command data in the case where the signal output adjustment circuit100is applied to a display driver. Therefore, a power supply circuit or a scan driver may be considered as the signal processing circuit20.

The command data includes an output regulation command (first command data) for setting the control data in the signal output adjustment circuit100, and a signal output command (second command data) for outputting the control data to the signal processing circuit20. At least one parameter in predetermined bit units may be set subsequent to the output regulation command or the signal output command.

The signal output command includes various commands for outputting the control data to a power supply circuit connected with the display driver, for example. The operation mode of the power supply circuit or the like can be set by using the signal output command. As examples of the signal output command, a power supply output command for designating ON/OFF of power supply output of the power supply circuit, a VCOM setting command for designating change timing of voltage applied to a common electrode which faces a pixel electrode in order to change the polarity of voltage applied to a liquid crystal based on a given voltage, a power supply sleep setting command for setting the power supply circuit in a sleep state, a boost clock setting command for designating the frequency of a boost clock signal of the power supply circuit, and the like can be given.

As examples of the output regulation command, various commands for setting the control data in the control register120can be given. The control data can be set to a power supply circuit or scan driver manufactured by another manufacturer and having a different interface specification by using the output regulation command.

The decoder110analyzes the command data having the configuration shown inFIG. 7which is read from the EEPROM according to a command data table shown inFIG. 8and determines whether the command data is the output regulation command or the signal output command. When the decoder110determines that the command data is the output regulation command, the control data corresponding to the command data (or parameter of the command data) is set in a first address region. When the decoder110determines that the command data is the signal output command, the control data corresponding to the command data (or parameter of the command data) is set in a second address region.

Each memory region of the control register120and the buffer130is specified by the address. The memory region of the control register120is assigned to the first address region. The memory region of the buffer130is assigned to the second address region. Therefore, when the decoder110determines that the command data is the output regulation command, the control data corresponding to the command data (or parameter of the command data) is set in the memory region of the control register120. When the decoder110determines that the command data is the signal output command, the control data corresponding to the command data (or parameter of the command data) in the memory region of the buffer130.

FIG. 9shows an outline of a configuration of the control register120.

The control register120includes a reference clock selection register120-a, a frequency divided clock selection register120-b, a clock phase selection register120-c, a clock output logic level setting register120-d, a clock output setting register120-e, a data phase selection register120-f, a data fetch signal logic level setting register120-g, and a data output setting register120-h. An inherent address is assigned to each register in the first address region, and the control data corresponding to the command data is set based on the decode result of the decoder110.

For example, based on a reference clock setting command shown inFIG. 8, a value corresponding to the command or the parameter of the command is set in the reference clock selection register120-a. The setting command or the parameter of the command may be called the command data. The control register120outputs a reference clock selection signal RCLKSEL corresponding to the value set in the reference clock selection register120-a.

Based on a frequency divided clock setting command, a value corresponding to the command or the parameter of the command is set in the frequency divided clock selection register120-b. The control register120outputs a frequency divided clock selection signal DIV corresponding to the value set in the frequency divided clock selection register120-b.

Based on a clock phase selection command, a value corresponding to the command or the parameter of the command is set in the clock phase selection register120-c. The control register120outputs a clock phase selection signal CPSEL corresponding to the value set in the clock phase selection register120-c.

Based on a clock output logic level setting command, a value corresponding to the command or the parameter of the command is set in the clock output logic level setting register120-d. The control register120outputs a clock output logic level setting signal CLKPN corresponding to the value set in the clock output logic level setting register120-d.

Based on a clock output setting command, a value corresponding to the command or the parameter of the command is set in the clock output setting register120-e. The control register120outputs a clock output setting signal CCONT corresponding to the value set in the clock output setting register120-e.

Based on a data phase selection command, a value corresponding to the command or the parameter of the command is set in the data phase selection register120-f. The control register120outputs a data phase selection signal DPSEL corresponding to the value set in the data phase selection register120-f.

Based on a data fetch signal logic level setting command, a value corresponding to the command or the parameter of the command is set in the data fetch signal logic level setting register120-g. The control register120outputs a data fetch signal logic level setting signal DATAPN corresponding to the value set in the data fetch signal logic level setting register120-g.

Based on a data output setting command, a value corresponding to the command or the parameter of the command is set in the data output setting register120-h. The control register120outputs a data output setting signal DCONT corresponding to the value set in the data output setting register120-h.

The reference clock selection signal RCLKSEL, the frequency divided clock selection signal DIV, the clock phase selection signal CPSEL, the clock output logic level setting signal CLKPN, the clock output setting signal CCONT, the data phase selection signal DPSEL, the data fetch signal logic level setting signal DATAPN, and the data output setting signal DCONT are supplied to the output adjustment circuit140.

FIG. 10shows an outline of a configuration of the output adjustment circuit140.

The output adjustment circuit140includes a reference clock selection circuit142, an N-phase clock generation circuit144(N is an integer of two or more), a clock phase selection circuit146, a clock output logic level conversion circuit148, a clock output circuit150, a data phase selection circuit152, a data fetch signal logic level conversion circuit154, a data output control circuit156, and a data output circuit158.

The reference clock selection circuit142selects one of a plurality of reference clock signals having different frequencies based on the reference clock selection signal RCLKSEL (based on the value set in the control register120in a broad sense).

The N-phase clock generation circuit144generates N-phase clock signals of different phases based on a frequency-divided clock signal generated by dividing the frequency of the reference clock selected by the reference clock selection circuit142. The N-phase clock signals generated by the N-phase clock generation circuit144are supplied to the clock phase selection circuit146and the data phase selection circuit152.

The N-phase clock generation circuit144may generate N-phase clock signals of different phases based on a frequency-divided clock signal generated by dividing the frequency of the reference clock selected by the reference clock selection circuit142at a dividing ratio set based on the frequency divided clock selection signal DIV (based on the value set in the control register120in a broad sense).

The clock phase selection circuit146selects one of the phase clock signals of different phases based on the clock phase selection signal CPSEL (based on the value set in the control register120in a broad sense). In more detail, the clock phase selection circuit146selects one of the N-phase clock signals generated by the N-phase clock generation circuit144based on the clock phase selection signal CPSEL.

The clock output logic level conversion circuit148outputs the phase clock signal selected by the clock phase selection circuit146or its inverted signal based on the clock output logic level setting signal CLKPN (based on the value set in the control register120in a broad sense).

The clock output circuit150delays the phase clock signal selected by the clock phase selection circuit146or its inverted signal for a period corresponding to the clock output setting signal CCONT (for a period corresponding to the value set in the control register120in a broad sense), and outputs the delayed signal. The signal output from the clock output circuit150is the clock signal supplied to the power supply circuit (signal processing circuit20).

The data phase selection circuit152selects one of a plurality of phase clock signals of different phases based on the data phase selection signal DPSEL (based on the value set in the control register120in a broad sense). In more detail, the data phase selection circuit152selects one of the N-phase clock signals generated by the N-phase clock generation circuit144based on the data phase selection signal DPSEL.

The data fetch signal logic level conversion circuit154outputs the phase clock signal selected by the data phase selection circuit152or its inverted signal based on the data fetch signal logic level setting signal DATAPN (based on the value set in the control register120in a broad sense).

The data output control circuit156delays the phase clock signal selected by the data phase selection circuit152or its inverted signal for a period corresponding to the data output setting signal DCONT (for a period corresponding to the value set in the control register120in a broad sense), and outputs the delayed signal. The signal output from the data output control circuit156is the data fetch signal supplied to the data output circuit158.

The data output circuit158outputs the control data read from the buffer130in synchronization with the data fetch signal. The signal output from the data output circuit158is the control data supplied to the power supply circuit (signal processing circuit20).

In the output adjustment circuit140, a clock signal having a frequency corresponding to the value set in the control register120can be supplied to the signal processing circuit20by the reference clock selection circuit142. A clock signal having a phase corresponding to the value set in the control register120can be supplied to the signal processing circuit20by the clock phase selection circuit146. The non-inversion output or inversion output of the clock signal can be supplied to the signal processing circuit20by the clock output logic level conversion circuit148corresponding to the value set in the control register120. A clock signal which is delayed from the reference timing for a period corresponding to the value set in the control register120can be supplied to the signal processing circuit20by the clock output circuit150.

The control data in synchronization with the data fetch signal having a phase corresponding to the value set in the control register120can be supplied to the signal processing circuit20by the data phase selection circuit152. The control data in synchronization with the non-inversion output or inversion output of the data fetch signal corresponding to the value set in the control register120can be supplied to the signal processing circuit20by the data fetch signal logic level conversion circuit154. The control data which is delayed from the reference timing for a period corresponding to the value set in the control register120can be supplied to the signal processing circuit20by the data output control circuit156.

Therefore, a signal output adjustment circuit which generalizes the device by absorbing the difference in AC characteristics from other devices can be provided.

The output adjustment circuit140shown inFIG. 10may have a configuration in which some of the above-described circuits are omitted. In this case, the output of the control data or the clock signal can be adjusted by the remaining circuits.

2. Display Driver

The case where the signal output adjustment circuit100in the present embodiment is applied to a display driver is described below.

FIG. 11shows an outline of a configuration of a display driver to which the signal output adjustment circuit100in the present embodiment is applied. InFIG. 11, sections the same as the sections of the signal output adjustment circuit100shown inFIG. 3are denoted by the same symbols. Description of these sections is appropriately omitted.

A display driver200includes the signal output adjustment circuit100, a display data bus210, a data register220, a line latch230, a digital-to-analog converter (DAC)240(voltage selection circuit in a broad sense), a data line driver circuit250, and a control circuit260.

Display data for driving a data line is supplied to the display data bus210. The display data which is serially input in pixel units in synchronization with a given dot clock signal CPH is supplied to the display data bus210. The display data is supplied from a display controller.

The data register220fetches the display data on the display data bus210based on the dot clock signal CPH. The data register220is formed by shift registers. The data register220fetches the display data on the display data bus210in pixel units based on the dot clock signal CPH which specifies shift timing of the shift registers.

The line latch230latches the display data fetched by the data register220based on a horizontal synchronization signal HSYNC. The horizontal synchronization signal is a signal which determines one horizontal scan period.

The DAC240outputs a drive voltage (gray-scale voltage) corresponding to the display data from the line latch230in data line units from a plurality of reference voltages, each of which corresponds to the display data. In more detail, the DAC240decodes the display data from the line latch230, and selects one of the reference voltages based on the decode result. The reference voltage selected by the DAC240is output to the data line driver circuit250as the drive voltage.

The data line driver circuit250includes a plurality of data output sections, each of which is provided corresponding to one data line output terminal. The data output section of the data line driver circuit250drives the data line based on the drive voltage output from the DAC240. The data output section includes a voltage-follower-connected operational amplifier of which the output is connected with the data line.

The control circuit260has the function of the memory control circuit170, and controls the signal output adjustment circuit100, the data register220, the line latch230, the DAC240, and the data line driver circuit250. The control circuit260controls these circuits based on the value set in the control register120.

The control circuit260controls the data output section of the data line driver circuit250relating to ON/OFF of data line drive based on the value set in the control register120. The control circuit260controls the shift direction of the shift registers which make up the data register220based on the value set in the control register120to control the fetch direction of the display data. The value is set in the control register120based on the decode result of the command data read from the EEPROM in the same manner as described above.

The output adjustment circuit140of the signal output adjustment circuit100shown inFIG. 11uses a display system clock signal as a reference clock signal, and adjusts the output of the control data or the clock signal by using the reference clock signal. As the display system clock signal, the dot clock signal CPH, the horizontal synchronization signal HSYNC, and a vertical synchronization signal VSYNC which determines one vertical scan period can be given.

FIG. 12schematically shows the dot clock signal CPH, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC.

The dot clock signal CPH is a clock signal at several MHz, for example. The display controller which supplies the display data to the display driver200serially outputs the display data in pixel units in synchronization with the dot clock signal CPH.

The frequency of the horizontal synchronization signal HSYNC is determined depending on the number of data lines to be driven. The horizontal synchronization signal HSYNC is a clock signal at several KHz, for example. The vertical synchronization signal VSYNC is a clock signal at 60 Hz, for example.

A specific configuration example of the output adjustment circuit140of the signal output adjustment circuit100applied to the display driver200is described below. The following description is given on the assumption that the output adjustment circuit140uses the dot clock signal CPH, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC as the reference clock signals, and N is four.

FIG. 13shows a configuration example of the output adjustment circuit140. InFIG. 13, sections the same as the sections of the output adjustment circuit140shown inFIG. 10are denoted by the same symbols. Description of these sections is appropriately omitted.

InFIG. 13, the reference clock selection circuit142selects one of the dot clock signal CPH, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC based on the reference clock selection signal RCLKSEL, and outputs the selected signal as a selected reference clock signal CK. A 4-phase clock generation circuit144generates four phases of phase clock signals PH0to PH3of different phases based on a frequency-divided clock signal generated by dividing the frequency of the selected reference clock signal CK. The 4-phase clock generation circuit144uses the frequency-divided clock signal generated by dividing the frequency of the selected reference clock signal CK at a dividing ratio corresponding to the frequency divided clock selection signal DIV.

FIG. 14shows a configuration example of the 4-phase clock generation circuit144.

The 4-phase clock generation circuit144includes a frequency divider circuit300which divides the frequency of the selected reference clock signal CK by four, a frequency divided clock selection circuit310, and a phase generation circuit320.

The frequency divider circuit300includes four T flip-flops TFF1to TFF4. The T flip-flop TFF1outputs a ½ frequency-divided clock signal (CK/2) generated by dividing the frequency of the selected reference clock signal CK. The T flip-flop TFF2outputs a ¼ frequency-divided clock signal (CK/4) generated by dividing the frequency of the ½ frequency-divided clock signal (CK/2). The T flip-flop TFF3outputs a ⅛ frequency-divided clock signal (CK/8) generated by dividing the frequency of the ¼ frequency-divided clock signal (CK/4). The T flip-flop TFF4outputs a 1/16 frequency-divided clock signal (CK/16) generated by dividing the frequency of the ⅛ frequency-divided clock signal (CK/8). The selected reference clock signal CK and the frequency-divided clock signals (CK/2, CK/4, CK/8, CK/16) are supplied to the frequency divided clock selection circuit310.

The frequency divided clock selection circuit310selects first and second selected frequency-divided clock signals CLA and CLB based on the frequency divided clock selection signal DIV.

FIG. 15shows a truth table of an operation example of the frequency divided clock selection circuit310. The dividing ratio is determined by the frequency divided clock selection signal DIV. When the dividing ratio determined by the frequency divided clock selection signal DIV is one, the selected reference clock signal CK and the ¼ frequency-divided clock signal (CK/4) are selected as the first and second frequency-divided clock signals CLA and CLB, respectively. When the dividing ratio determined by the frequency divided clock selection signal DIV is two or four, the frequency-divided clock signals are selected as the first and second frequency-divided clock signals CLA and CLB as shown inFIG. 15.

InFIG. 14, the phase generation circuit320includes three D flip-flops DFF1to DFF3. The second frequency-divided clock signal CLB is the phase clock signal PH0. The D flip-flop DFF1generates the phase clock signal PH1by synchronizing the second frequency-divided clock signal CLB with the first selected frequency-divided clock signal CLA. The D flip-flop DFF2generates the phase clock signal PH2by synchronizing the phase clock signal PH1with the first selected frequency-divided clock signal CLA. The D flip-flop DFF3generates the phase clock signal PH3by synchronizing the phase clock signal PH2with the first selected frequency-divided clock signal CLA.

FIG. 16shows a timing diagram of an operation example of the 4-phase clock generation circuit shown inFIGS. 14 and 15.FIG. 16shows a timing diagram of four phases of phase clock signals PH0to PH3in the case where one, two, or four is determined by the frequency divided clock selection signal DIV.

As shown inFIG. 13, the four phases of phase clock signals PH0to PH3are supplied to the clock phase selection circuit146and the data phase selection circuit152.

A phase clock signal selected by the clock phase selection circuit146based on the clock phase selection signal CPSEL is supplied to the clock output logic level conversion circuit148. The clock output logic level conversion circuit148supplies non-inversion output or inversion output of the clock signal output from the clock phase selection circuit146to the clock output circuit150corresponding to the clock output logic level setting signal CLKPN.

The clock output circuit150may include latches350and352, a counter354, and a comparator356. The latch350latches the output from the clock phase selection circuit146based on a reference timing signal RT1. The counter354starts counting of the counter value based on the reference timing signal RT1, and counts the edges of an output CKO1from the clock phase selection circuit146. The comparator356compares the value determined by the clock output setting signal CCONT with the counter value of the counter354. The comparator356outputs a pulse when these values coincide. The latch352latches the output from the latch350based on the pulse. The output from the latch352is output to the signal processing circuit20as a clock signal.

FIG. 17shows a timing diagram of an operation example of the clock output circuit150. As shown inFIG. 17, the output from the clock output logic level conversion circuit148is delayed for a period until the value determined by the clock output setting signal CCONT coincides with the counter value of the counter354.

InFIG. 13, the phase clock signal selected by the data phase selection circuit152based on the data phase selection signal DPSEL is supplied to the data fetch signal logic level conversion circuit154. The data fetch signal logic level conversion circuit154supplies non-inversion output or inversion output of the clock signal output from the data phase selection circuit152to the data output control circuit156corresponding to the data fetch signal logic level setting signal DATAPN.

The data output control circuit156has the same configuration as that of the clock output circuit150. The data output control circuit156outputs the data fetch signal generated by delaying the output from the data fetch signal logic level conversion circuit154based on the reference timing signal RT2for a period until the value determined by the data output setting signal DCONT coincides with the counter value of the counter.

The data output circuit158is formed by a D flip-flop. The data output circuit158fetches the control data read from the buffer130in synchronization with the edge of the data fetch signal from the data output control circuit156, and outputs the control data to the signal processing circuit20.

The control data can be set to other devices having an interface specification differing from that of the display driver, such as the scan driver or the power supply circuit, based on the command data by providing a display driver having the function of the above-described signal output adjustment circuit, whereby system construction can be facilitated. Therefore, a generalized display driver which can absorb the difference in AC characteristics from other devices can be provided, whereby a reduction of cost can be achieved.

3. Application Example to Electro-Optical Device

An electro-optical device to which the display driver200shown inFIG. 11is applied is described below. The following description is given taking a liquid crystal device as an example of an electro-optical device.

FIG. 18shows an outline of a configuration of an electro-optical device. InFIG. 18, sections the same as the sections shown inFIGS. 1 and 11are denoted by the same symbols. Description of these sections is appropriately omitted.

An electro-optical device may be incorporated into various electronic instruments such as a portable telephone, portable information instrument (PDA, etc.), digital camera, projector, portable audio player, mass storage device, video camera, electronic notebook, or global positioning system (GPS).

InFIG. 18, an electro-optical-device610includes a liquid crystal display (LCD) panel620(display panel or electro-optical panel in a broad sense), a display driver200, a scan driver640(gate driver), an LCD controller650(display controller in a broad sense), and a power supply circuit660.

The electro-optical-device610does not necessarily include all of these circuit blocks. The electro-optical-device610may have a configuration in which some of the circuit blocks are omitted.

The LCD panel620includes a plurality of scan lines (gate lines), each of the scan lines being provided in one of the rows, a plurality of data lines (source lines) which intersect the scan lines, each of the data lines being provided in one of the columns, and a plurality of pixels, each of the pixels being specified by one of the scan lines and one of the data lines. Each of the pixels includes a thin-film transistor (hereinafter abbreviated as “TFT”) and a pixel electrode. The TFT is connected with the data line, and a pixel electrode is connected with the TFT.

In more detail, the LCD panel620is formed on a panel substrate such as a glass substrate. A plurality of scan lines GL1to GLM (M is an integer of two or more; M is desirably three or more), arranged in the Y direction shown inFIG. 18and extending in the X direction, and a plurality of data lines DL1to DLN (N is an integer of two or more), arranged in the X direction and extending in the Y direction, are disposed on the panel substrate. A pixel PEmn is disposed at a position corresponding to the intersecting point of the scan line GLm (1≦m≦M, m is an integer) and the data line DLn (1≦n≦N, n is an integer). The pixel PEmn includes the thin-film transistor TFTmn and the pixel electrode.

A gate electrode of the thin-film transistor TFTmn is connected with the scan line GLm. A source electrode of the thin-film transistor TFTmn is connected with the data line DLn. A drain electrode of the thin-film transistor TFTmn is connected with the pixel electrode. A liquid crystal capacitor CLmn is formed between the pixel electrode and a common electrode COM which faces the pixel electrode through a liquid crystal element (electro-optical material in a broad sense). A storage capacitor may be formed in parallel with the liquid crystal capacitor CLmn. The transmissivity of the pixel changes corresponding to the voltage applied between the pixel electrode and the common electrode COM. A voltage VCOM supplied to the common electrode COM is generated by the power supply circuit660.

The LCD panel620is formed by attaching a first substrate on which the pixel electrode and the TFT are formed to a second substrate on which the common electrode is formed, and sealing a liquid crystal as an electro-optical material between the two substrates.

The display driver200drives the data lines DL1to DLN of the LCD panel620based on display data for one horizontal scan period supplied in units of horizontal scan periods. In more detail, the display driver200drives at least one of the data lines DL1to DLN based on the display data.

The scan driver640scans the scan lines GL1to GLM of the LCD panel620. In more detail, the scan driver640sequentially selects the scan lines GL1to GLM in one vertical period, and drives the selected scan line.

The LCD controller650outputs control signals to the display driver200, the scan driver640, and the power supply circuit660according to the content set by a host such as a CPU (not shown). In more detail, the LCD controller650supplies an operation mode setting and a horizontal synchronization signal or a vertical synchronization signal generated therein to the display driver200and the scan driver640, for example. The horizontal synchronization signal specifies the horizontal scan period. The vertical synchronization signal specifies the vertical scan period. The LCD controller650controls the power supply circuit660relating to polarity reversal timing of the voltage VCOM applied to the common electrode COM by using a polarity reversal signal POL.

The power supply circuit660generates various voltages applied to the LCD panel620and the voltage VCOM applied to the common electrode COM based on a reference voltage supplied from the outside.

The display driver200reads the command data stored in advance in the memory10after initialization, adjusts the output of the control data and the clock signal, and outputs various clock signals or sets various types of control data to the scan driver640and the power supply circuit660. For example, the display driver200outputs the control data corresponding to at least one of the power supply output command, VCOM setting command, power supply sleep setting command, and boost clock setting command to the power supply circuit660to set the power supply circuit660.

InFIG. 18, the electro-optical device610is configured to include the LCD controller650. However, the LCD controller650may be provided outside the electro-optical device610. The host (not shown) may be included in the electro-optical device610together with the LCD controller650.

At least one of the scan driver640, the LCD controller650, and the power supply circuit660may be included in the display driver200.

Some or the entirety of the display driver200, the scan driver640, the LCD controller650, and the power supply circuit660may be formed on the LCD panel620. InFIG. 19, the display driver200and the scan driver640are formed on the LCD panel620. As described above, the LCD panel620may be configured to include a plurality of data lines, a plurality of scan lines, a plurality of pixels, each of the pixels being specified by one of the data lines and one of the scan lines, and a display driver which drives the data lines. The pixels are formed in a pixel formation region680of the LCD panel620.

The present invention is not limited to the above-described embodiment. Various modifications and variations are possible within the spirit and scope of the present invention. For example, the present invention can be applied not only to drive of the LCD panel, but also to drive of an electroluminescent or plasma display device.

Part of requirements of a claim of the present invention could be omitted from a dependent claim which depends on that claim. Moreover, part of requirements of any independent claim of the present invention could be made to depend on any other independent claim.