Semiconductor device having a particular structure allowing for voltage stress test application

Since the power-supply and/or signal-transmission wiring layers connected to the semiconductor chip regions are formed, each individual integrated circuit can be burned in on the semiconductor wafer and, in other words, an integrated circuit can be burned in on a wafer level. The integrated circuit can thus be burned in at the end of a wafer process. An assembled semiconductor device is subjected to a high temperature or a high humidity, for checking the reliability of the assembled device.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a semiconductor device comprising a 
semiconductor wafer having a plurality of IC chip regions and a method of 
burning in the same. 
2. Description of the Related Art 
There are two purposes of burning in a semiconductor integrated circuit. 
The first purpose is to positively find a latent defect (e.g., a defect in 
an oxide film) caused in a wafer process so that only a perfect product 
can be selected in the subsequent screening process. In the first purpose, 
a semiconductor integrated circuit is burned in by applying a great 
electrical stress, i.e., by applying a high voltage, under a high ambient 
temperature. The second purpose is to positively find a latent defect 
(e.g., a crack in sealing resin) caused in an assembly process so that 
only a perfect product can be selected in the subsequent screening 
process. In the second purpose, a semiconductor integrated circuit is not 
necessarily burned in by applying an electrical stress and it is subjected 
to an environmental stress such as a high temperature or a high humidity, 
for checking the reliability of the assembled device. 
Semiconductor integrated circuits have been conventionally burned in with 
each individual IC chip finished as a semiconductor device and, in other 
words, with each individual IC chip packaged. For this reason, a burn-in 
equipment is enlarged and complicated, and an investment for the burn-in 
equipment is increased and a cost of ensuring a place required for storing 
the burn-in equipment is heightened, which greatly increases the 
manufacturing costs of a semiconductor integrated circuit device. Since 
the burn-in operation is carried out with IC chips packaged, even a 
semiconductor integrated circuit such as a memory having a redundancy 
circuit suffers from the problem wherein latent defects cannot be 
eliminated and the yield of IC chips is difficult to be improved. 
SUMMARY OF THE INVENTION 
The present invention has been made in order to solve the above problem and 
its object is to provide a semiconductor device and a method of burning in 
the same wherein an integrated circuit can be burned in at the end of a 
wafer process. 
According to an aspect of the present invention, there is provided a 
semiconductor device comprising a semiconductor wafer having a plurality 
of IC chip regions, and a plurality of power-supply and/or 
signal-transmission wiring layers connected to the IC chip regions and 
formed on the semiconductor wafer. 
According to another aspect of the present invention, there is provided a 
method of burning in a semiconductor device comprising a plurality of IC 
chip regions and a semiconductor wafer including power-supply and/or 
signal-transmission wiring layers connected to the IC chip regions, 
wherein a power supply voltage and/or a signal is applied to the wiring 
layers. 
Since the power-supply and/or signal-transmission wiring layers connected 
to the semiconductor chip regions are formed, each individual integrated 
circuit can be burned in on the semiconductor wafer and, in other words, 
an integrated circuit can be burned in on a wafer level. The integrated 
circuit can thus be burned in at the end of a wafer process. An assembled 
semiconductor device is subjected to a high temperature or a high humidity 
for checking the reliability of the assembled device. 
A burn-in equipment can thus be simplified and miniaturized, and an 
investment for the burn-in equipment can be reduced and an area for 
installing it can be made small, which decreases the manufacturing costs 
of a semiconductor integrated circuit device. It is of course necessary to 
employ a new burn-in equipment capable of applying an electrical or 
thermal stress to the integrated circuit on the wafer. Such a new burn-in 
equipment is much simpler and smaller than a conventional burn-in 
equipment. Furthermore, manufacturing installing the device is small. If a 
burn-in operation is performed before dicing for separating the wafer into 
chips and then a screening test is carried out, a defective integrated 
circuit can be replaced with an auxiliary normal integrated circuit in a 
semiconductor integrated circuit device (e.g., memory) including a 
redundancy circuit and, in other words, a defective integrated circuit can 
be eliminated and thus the yield of IC chips is improved. 
Additional objects and advantages of the invention will be set forth in the 
description which follows, and in part will be obvious from the 
description, or may be learned by practice of the invention. The objects 
and advantages of the invention may be realized and obtained by means of 
the instrumentalities and combinations particularly pointed out in the 
appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Embodiments of the present invention will be described in detail when taken 
in conjunction with the accompanying drawings. 
FIG. 1 is a schematic view showing a semiconductor device according to the 
first embodiment of the present invention. In FIG. 1, semiconductor wafer 
10 has a plurality of IC chip (e.g., dynamic RAM chip) regions 11. A 
plurality of power supply wiring layers 12 and 13 is formed on 
semiconductor wafer 10 and connected to a power supply for driving 
circuits in IC chip regions 11. Wiring layers 12 and 13 are formed on 
dicing line regions between chip regions 11 in the longitudinal direction 
of FIG. 1. 
Wiring layers 12 and 13 are alternately arranged on the dicing line regions 
of the semiconductor wafer in the longitudinal direction of FIG. 1. 
Adjacent two wiring layers 12 and 13 are connected to a power supply 
terminal (not shown) of chip region 11 interposed between the wiring 
layers (FIG. 3). Signal (e.g., clock signal) transmission wiring layer 14, 
which is supplied with a signal for controlling the operation of a circuit 
of chip region 11, is formed on a dicing line region in a direction 
perpendicular to wiring layers 12 and 13, in other words, in a lateral 
direction of FIG. 1. Wiring layer 14 is connected to a signal terminal 
(not shown) of chip region 11 which is adjacent to wiring layer 14. 
Wiring layers 12, 13 and 14 are made of, e.g., aluminum and can be formed 
by the same patterning as that for a wiring layer formed in each of chip 
regions 11. 
A circuit (not shown) for generating a signal for controlling a chip 
operation during the burn-in process is formed on chip regions or on 
dicing line regions and is supplied with a power supply voltage from 
wiring layer 12 or 13. Contact terminals 12A and 13A are formed on the 
wafer. Contact terminal 12A is connected in common to plural wiring layers 
12 and contact terminal 13A is connected in common to plural wiring layers 
13. Contact terminals 12A and 13A receive power supply voltages V1 and V2 
from the outside of the wafer and apply these voltages to wiring layers 12 
and 13. Contact terminal 14A is formed on the wafer and connected to 
plural wiring layers 14. Contact terminal 14A receives a signal from the 
outside of wafer and supplies it to wiring layer 14. As illustrated in 
FIG. 1, contact terminals 12A and 13A are formed at both ends of the 
wafer. FIG. 8A shows an example of a cross-sectional view of the 
semiconductor device shown in FIG. 1. In FIG. 8A, the wiring layer 14 is 
formed on the semiconductor wafer 10, an insulation film is on the 
structure, and the wiring layers 12 and 13 are formed on the insulation 
film and separated from each other. Wiring layers 12 and 13 cross wiring 
layer 14, with the insulation film provided therebetween. 
FIG. 8B shows another example of a cross-sectional view of the 
semiconductor device shown in FIG. 1. In FIG. 8B, wiring layers 12 and 13 
are formed on the semiconductor wafer 10 and separated from each other. An 
insulation film (not shown) is formed on the structure, and the wiring 
layer 14 is formed on the insulation film. Wiring layers 12 and 13 cross 
wiring layer 14, with the insulation film provided therebetween. 
When an insulation film is interposed between wiring layers 12 and 13, 
these wiring layers can be arranged in parallel to each other as shown in 
FIG. 2A, and they can cross each other as shown in FIG. 2B. Wiring layer 
14 is formed on another insulation film which is formed on wiring layer 13 
(FIGS. 2A and 2B). Otherwise, wiring layer 14 can be formed on the 
lowermost layer of the wafer or on a layer between layers 12 and 13. In 
this multi-layered structure, a first, second and third wiring layers can 
be made of polysilicon, silicide and metal, respectively. All the wiring 
layers can be made of metal. The metal is preferably aluminum; however 
other kind of metal can be used. 
Each of chip regions 11 formed on wafer 10 shown in FIG. 1 is finally 
divided into chips after the burn-in process, and the chips are then 
assembled and finished as integrated circuits. Chip regions (e.g., chip 
regions for test elements required at the stage of development) to which 
neither power supply wiring layers nor signal transmission wiring layers 
are connected, can be formed on wafer 10. When different integrated 
circuits are formed between chip regions, a common wiring layer is 
connected to a chip regions for the same integrated circuit. 
In burning in integrated circuits 11 on wafer 10, wafer 10 is attached to a 
socket (not shown), and predetermined power supply voltage V.sub.1 and 
ground voltage V.sub.2 are externally applied to integrated circuits 11 
through contact pads 12A and 13A. If ordinary power supply voltage Vcc is 
used as V.sub.1 and ground voltage Vss is used as V.sub.2, a static 
burn-in operation can be performed and, in this case, no probe cards are 
needed. When the need arises, a power supply voltage can be directly 
applied to the semiconductor wafer. 
According to the first embodiment of the present invention, since the power 
supply wiring layer and the signal transmission wiring layer, which are 
connected to the chip regions, are formed, each individual integrated 
circuit can be burned in on the semiconductor wafer and, in other words, 
the burn-in of each integrated circuit can be performed on a wafer level. 
The integrated circuit can thus be burned in at the end of the wafer 
process. If the integrated circuits are assembled into a semiconductor 
device, it is subjected to a high temperature and a high humidity, for 
checking the reliability of the assembled device. 
Consequently, a burn-in equipment can be simplified and miniaturized, and 
an investment for the burn-in equipment can be reduced and an area for 
installing it can be made small, which decreases the manufacturing costs 
of a semiconductor integrated circuit device. It is of course necessary to 
employ a new burn-in equipment capable of applying an electrical or 
thermal stress to the integrated circuit on the wafer. Such a new burn-in 
equipment is much simpler and smaller than a conventional burn-in 
equipment. Furthermore, manufacturing costs of the new burn-in equipment 
are low and an area for installing the device is small. If a burn-in 
operation is performed before dicing for separating the wafer into chips 
and then a screening test is carried out, a defective integrated circuit 
can be replaced with an auxiliary normal integrated circuit in a 
semiconductor integrated circuit device (e.g., memory) including a 
redundancy circuit and, in other words, a defective integrated circuit can 
be saved and thus the yield of IC chips is improved. 
After the integrated circuit on the wafer is burned in, the wafer is diced 
and finally separated into a plurality of chips. The power supply and 
signal transmission wiring layers are thus cut on the dicing line regions. 
In a multi-layered structure, a short circuit may occur between the wiring 
layers into which an inter layer insulation film and the wiring layers 
(not shown) in the chips. In order to avoid the short circuit, it is 
desirable to separate the power supply and signal transmission wiring 
layers from the wiring layers in the chips before the dicing. One of 
specific methods of separating these layers is to cut the connection 
regions of the power supply and signal transmission wiring layers and the 
wiring layers in the chips. If these wiring layers are made of aluminum, 
the connection regions can be cut by irradiating a laser beam or a 
convergent ion beam. Another method is to use an element for electrically 
separating these wiring layers. As the simplest method of separating the 
wiring layers, if the power supply and signal transmission wiring layers 
are not necessarily required after the respective chips are finished as 
integrated circuit devices, these wiring layers are removed before the 
dicing. 
FIG. 4 is a schematic view showing a semiconductor device according to the 
second embodiment of the present invention. Since the second embodiment is 
the same as the first embodiment except in that power supply wiring layers 
12 and 13 are formed on each of dicing line regions in the longitudinal 
direction of a wafer in FIG. 4, the same reference numerals as those in 
FIG. 1 are added to FIG. 4. In FIG. 4, only one of a plurality of IC chip 
regions is shown for simplification of the drawing. 
In the second embodiment, an integrated circuit can be burned in on the 
wafer and thus the same effect as that of the first embodiment can be 
obtained. 
An example of the burn-in process will be described with reference to FIG. 
5. FIG. 5 illustrates a circuit (including dynamic type memory cell, word 
line, bit line) on an IC chip region such as a dynamic RAM chip region. 
Two power supply wiring layers 12 and 13 are connected to the circuit. In 
FIG. 5, reference numerals 41, 42 and 43 denote contact terminals on the 
dynamic RAM chip region; C, a cell capacitor; TR, a transfer gate MOS 
transistor; WL, a word line; BL, a bit line; and SW, switching MOS 
transistors inserted in series between word lines WL and power supply 
wiring layer 12. Power supply wiring layer 13 is connected to the gates of 
transistors SW. PR indicates a precharging MOS transistor inserted in 
series between bit line BL and bit line precharging power supply line 44. 
Precharging signal line .phi.PRE is connected to the gate of the 
precharging MOS transistor. 
In the normal operation of the dynamic RAM, word line drive potential WLD 
which is higher than ordinary power supply voltage Vcc, is applied to a 
selective word line WL. The highest reliability is therefore required for 
the transfer gate MOS transistor whose gate is connected to word line WL. 
It is necessary to drive a plurality of word lines in sequence to burn in 
transfer gate MOS transistors TR connected to the word lines. The number 
of word lines selected in one burn-in operation cycle is very small and 
usually each of the word lines is selected every 1000 cycles only. The 
efficiency of the burn-in operation is very low. It takes a very long time 
to burn in only one integrated circuit and the burn-in efficiency becomes 
much lower. 
According to the present invention, the burn-in time can be shortened by 
the use of a burn-in method wherein a stress is directly applied. The 
burn-in method of the present invention will be described with reference 
to the circuit shown in FIG. 5. Bit line precharge power supply line 44 
set at ground potential Vss and precharge signal line .phi.PRE is 
activated to turn on precharge MOS transistor PR. Power supply voltage 
V.sub.S which is substantially the same as word line drive potential WLD, 
is applied to power supply wiring layer 12, and power supply voltage 
V.sub.G which is higher than power supply voltage V.sub.S by more than the 
threshold voltage of transfer gate MOS transistor TR, is applied to power 
supply wiring layer 13. A direct voltage stress can thus be applied 
between power supply wiring layer 12 and the bit line BL. If MOS 
transistor TR is latently defective, it becomes perfectly defective by the 
direct voltage stress. If no voltage is applied to bit line precharge 
power supply line 44 or precharge signal line .phi.PRE and power supply 
voltages V.sub.S and V.sub.G are applied to power supply wiring layers 12 
and 13, respectively, a direct stress can be applied between power supply 
wiring layer 12 and the semiconductor substrate. Similarly, if MOS 
transistor TR is latently defective, it becomes perfectly defective by the 
direct stress. 
When two power supply wiring layers and two signal wiring layers are 
arranged, if power supply voltage Vcc, ground potential Vss, row address 
strobe signal RAS, and column address strobe signal CAS are supplied to 
these wiring layers, the burn-in operation can be carried out in CAS 
before RAS refresh mode. 
In the first and second embodiments, since power supply wiring layers 12 
and 13 and signal transmission wiring layer 14 are formed by the same 
patterning as that of the wiring layers formed in the chip regions, a 
manufacturing process can be simplified. These wiring layers are made of 
aluminum in the above embodiments; however, they can be made of 
polysilicon or silicide. 
In the first and second embodiments, the power supply and the signal 
transmission wiring layers and wiring layers used in the chip regions are 
formed by patterning the same wiring layer. However, the power supply and 
signal transmission wiring layers can be formed by patterning different 
wiring layers, and can be connected to wiring layers used in the chip 
regions through a contact hole or a bonding wire and, in this case, a 
wiring scheme can be achieved regardless of an element pattern of each of 
the chip regions. The power supply wiring layers can have a single-layered 
structure wherein they formed on the same insulation film or a 
multi-layered structure wherein they are separated by an interlayered 
insulation film. Further, it is possible to form a multi-layered structure 
consisting of the power supply and signal transmission wiring layers and 
the wiring layers used in the chip regions. It is also possible to form a 
wiring layer for exclusively performing a burn-in operation in an 
operation mode which cannot be executed in a packaged state or performing 
a burn-in operation so as to apply a stress to a part of the integrated 
circuit. 
Even when the wiring layer for exclusively performing the burn-in operation 
is formed, a short circuit may occur between the power supply and signal 
transmission wiring layers and the wiring layers in the chip regions, or 
between these wiring layers and the semiconductor substrate, when the 
integrated circuits on the wafer are separated. To prevent the short 
circuit, it is desirable that the power supply and signal transmission 
wiring layers are separated from the wiring layers in the chip regions 
before the dicing. The method of separating these wiring layers has been 
already described above. 
When a voltage is applied to a number of integrated circuits in the burn-in 
process and then a short circuit occurs between the Vcc and Vss power 
supplies in a chip, this short circuit affects a voltage which is applied 
to another integrated circuit for a burn-in operation. To eliminate this 
influence, it is desirable that a resistor having a proper value is 
arranged between the power supply and signal transmission wiring layers 
and the wiring layers formed in the chip regions. The resistance of the 
resistor is set to be higher, preferably much higher than a sheet 
resistance of each of the wiring layers. 
The resistance of the resistor will be described in detail with reference 
to FIGS. 6 and 7. FIG. 6 illustrates a circuit in which power supply 
wiring layers 12 and 13 are connected to Vcc and Vss power supplies, 
respectively to apply a voltage stress to a number of chips 11.sub.1, 
11.sub.2, . . . , 1.sub.1 n. In FIG. 6, R represents resistors of wiring 
layers 12 and 13. 
Assuming that there is a short circuit between the Vcc power supply and the 
Vss power supply in integrated circuit 11.sub.3, a great number of 
currents flow into integrated circuit 11.sub.3 and a voltage drops by 
resistance R of each of power supply wiring layers 12 and 13. Therefore, a 
voltage of a predetermined level for a burn-in operation is applied to 
neither integrated circuits 11.sub.1 and 11.sub.2 located farther than 
integrated circuit 11.sub.3 from power supplies Vcc and Vss nor integrated 
circuit 11.sub.4 located close to integrated circuit 11.sub.3 but nearer 
to the power supplies than integrated circuit 11.sub.3. 
To avoid the above, as illustrated in FIG. 7, a resistor r is interposed 
between each of power supply wiring layers 12 and 13 and wiring layer used 
in each of the chip regions. Even if there is a short circuit between 
power supplies Vcc and Vss in integrated circuit 11.sub.3, the currents 
flowing into integrated circuit 11 3 are restricted by resistor r. If the 
resistance of resistor r is much larger than resistance R of the power 
supply wiring layers, the voltage drop of the power supply wiring layers 
due to the currents flowing into integrated circuit 11.sub.3 is not so 
great and can be neglected. A voltage having a predetermined level for a 
burn-in operation is thus applied to integrated circuits 11.sub.1 and 
11.sub.2 located farther than integrated circuit 11.sub.3 from the power 
supplies and integrated circuit 11.sub.4 located close to integrated 
circuit 11.sub.3. 
In the above embodiments, since the power supply and signal transmission 
wiring layers are formed as wiring layers connected to a plurality of 
semiconductor chip regions, the integrated circuits can be easily burned 
in on the wafer level. Even when only one of the wiring layers is formed, 
the integrated circuits can be burned in on the wafer level. 
As described above, according to the semiconductor memory device of the 
present invention, an integrated circuit can be burned in on a wafer at 
the end of the wafer process. A burn-in equipment can be simplified and 
miniaturized, and an investment for the burn-in equipment can be reduced 
and an area for installing it can be made small, which decreases the 
manufacturing costs of a finally-finished semiconductor integrated circuit 
device. 
Additional advantages and modifications will readily occur to those skilled 
in the art. Therefore, the invention in its broader aspects is not limited 
to the specific details, representative devices, and illustrated examples 
shown and described herein. Accordingly, various modifications may be made 
without departing from the spirit or scope of the general inventive 
concept as defined by the appended claims and their equivalents.