Method of programming a memory device

The present invention is a method of programming a memory device, wherein different levels or magnitudes of current may be applied to and imposed on the memory device so that any one of a plurality of memory states may be realized. A read step indicates the so determined state of the memory device.

BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates generally to memory devices, and more particularly, to a memory device which is programmable to any of a plurality of states.

2. Background Art

The volume, use and complexity of computers and electronic devices are continually increasing. Computers consistently become more powerful, new and improved electronic devices are continually developed (e.g., digital audio players, video players). Additionally, the growth and use of digital media (e.g., digital audio, video, images, and the like) have further pushed development of these devices. Such growth and development has vastly increased the amount of information desired/required to be stored and maintained for computer and electronic devices.

Generally, information is stored and maintained in one or more of a number of types of storage devices. Storage devices include long term storage mediums such as, for example, hard disk drives, compact disk drives and corresponding media, digital video disk (DVD) drives, and the like. The long term storage mediums typically store larger amounts of information at a lower cost, but are slower than other types of storage devices. Storage devices also include memory devices, which are often, but not always, short term storage mediums. Memory devices tend to be substantially faster than long term storage mediums. Such memory devices include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), double data rate memory (DDR), flash memory, read only memory (ROM), and the like. Memory devices are subdivided into volatile and non-volatile types. Volatile memory devices generally lose their information if they lose power and typically require periodic refresh cycles to maintain their information. Volatile memory devices include, for example, random access memory (RAM), DRAM, SRAM and the like. Non-volatile memory devices maintain their information whether or not power is maintained to the devices. Non-volatile memory devices include, but are not limited to, ROM, programmable read only memory (PROM), erasable programmable read only memory (EPROM), flash memory and the like. Volatile memory devices generally provide faster operation at a lower cost as compared to non-volatile memory devices.

Memory devices generally include arrays of memory devices. Each memory device can be accessed or “read”, “written”, and “erased” with information. The memory devices maintain information in an “off” or an “on” state (e.g. are limited to 2 states), also referred to as “0” and “1”. Typically, a memory device is addressed to retrieve a specified number of byte(s) (e.g., 8 memory devices per byte). For volatile memory devices, the memory devices must be periodically “refreshed” in order to maintain their state. Such memory devices are usually fabricated from semiconductor devices that perform these various functions and are capable of switching and maintaining the two states. The devices are often fabricated with inorganic solid state technology, such as, crystalline silicon devices. A common semiconductor device employed in memory devices is the metal oxide semiconductor field effect transistor (MOSFET).

The use of portable computer and electronic devices has greatly increased demand for non-volatile memory devices. Digital cameras, digital audio players, personal digital assistants, and the like generally seek to employ large capacity non-volatile memory devices (e.g., flash memory, smart media, compact flash, and the like).

Because of the increasing demand for information storage, memory device developers and manufacturers are constantly attempting to increase storage capacity for memory devices (e.g., increase storage per die or chip). A postage-stamp-sized piece of silicon may contain tens of millions of transistors, each transistor as small as a few hundred nanometers. However, silicon-based devices are approaching their fundamental physical size limits. Inorganic solid state devices are generally encumbered with a complex architecture which leads to high cost and a loss of data storage density. The volatile semiconductor memories based on inorganic semiconductor material must constantly be supplied with electric current with a resulting heating and high electric power consumption in order to maintain stored information. Non-volatile semiconductor devices have a reduced data rate and relatively high power consumption and large degree of complexity. Typically, fabrication processes for such cells are also not reliable.

Therefore, there is a need to overcome the aforementioned deficiencies.

FIG. 1illustrates a type of memory device30which includes advantageous characteristics for meeting these needs. The memory device30includes, for example, a Cu electrode32, a superionic layer34such as Cu2S on the electrode32, an active layer36such as Cu2O and/or various polymers on the Cu2S layer34, and a Ti electrode38on the active layer36. Initially, assuming that the memory device30is unprogrammed, in order to program the memory device30, an increasingly negative voltage is applied to the electrode38, while the electrode32is held at ground, so that an increasing electrical potential is applied across the memory device30from a higher to a lower potential in the direction from electrode32to electrode38, until electrical potential Vpg(the “programming” electrical potential) is reached (seeFIG. 2, a plot of memory device current vs. electrical potential applied across the memory device30). This potential Vpgis sufficient to cause copper ions to be attracted from the superionic layer34toward the electrode38and into the active layer36, causing the active layer36(and the overall memory device30) to rapidly switch to a low-resistance or conductive state (A). Upon removal of such potential (B), the copper ions drawn into the active layer36during the programming step remain therein, so that the active layer36(and memory device30) remain in a conductive or low-resistance state, as indicated by the resistance characteristic (B).

In order to erase the memory device (FIG. 2), an increasingly positive voltage is applied to the electrode38, while the electrode32is held at ground, so that an increasing electrical potential is applied until electrical potential Ver(the “erase” electrical potential) is applied across the memory device30from a higher to a lower electrical potential in the reverse direction. This potential Veris sufficient to cause copper ions to be repelled from the active layer36toward the electrode32and into the superionic layer34, in turn causing the active layer36(and the overall memory device30) to be in a high-resistance or substantially non-conductive state. This state remains upon removal of such potential from the memory device30.

FIG. 2also illustrates the read step of the memory device30in its programmed (conductive) state and in its erased (nonconductive) state. An electrical potential Vr(the “read” electrical potential) is applied across the memory device30from a higher to a lower electrical potential in the same direction as the electrical potential Vpg. This electrical potential is less than the electrical potential Vpgapplied across the memory device30for programming (see above). In this situation, if the memory device30is programmed, the memory device30will readily conduct current (level L1), indicating that the memory device30is in its programmed state. If the memory device30is erased, the memory device30will not conduct current (level L2), indicating that the memory device30is in its erased state.

As will be seen, the memory device as thus far shown and described is capable of adopting two states, i.e., a first, conductive state, or “on” state, and a second, substantially non-conductive, or “off” state. Each memory device thus can include information as to the state of a single bit, i.e., either 0 or 1. However, it would be highly desirable to be able to provide a memory device which is capable of adopting any of a plurality of states, so that, for example, in the case where four different states of the memory device can be adopted, two bits of information can be provided as chosen (for example first state equals 00, second state equals 01, third state equals 10, fourth state equals 11).

Therefore, what is needed is an approach wherein a memory device may adopt each of a plurality of states, each relating to the information held thereby.

DISCLOSURE OF THE INVENTION

Broadly stated, the present invention is a method of programming a memory device which is capable of having any of a plurality of states, the method comprising applying a selected level of current to the memory device to provide that the memory device has one of the plurality of states.

Broadly stated, another aspect of the invention is a method of programming memory devices of a memory array comprising a first plurality of conductors, a second plurality of conductors, and a plurality of connecting structures, each connecting a conductor of the first plurality thereof with a conductor of the second plurality thereof, each connecting structure comprising a memory device, each memory device being capable of having any of a plurality of states, the method comprising applying a first selected level of current to a first memory device of the array to provide that the first memory device has a first of the plurality of states, and applying a second selected level of current to a second memory device of the array to provide that the second memory device has a second of the plurality of states.

The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there are shown and described embodiments of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.

BEST MODE(S) FOR CARRYING OUT THE INVENTION

Reference is now made in detail to a specific embodiment of the present invention which illustrates the best mode presently contemplated by the inventors for practicing the invention.

FIG. 3illustrate a memory device130similar to the memory device30. The memory device130includes, for example, a Cu electrode132, a superionic layer134such as Cu2S on the electrode132, an active layer136such as Cu2O and/or various polymers on the Cu2S layer134, and a Ti electrode138on the active layer136. Operatively connected to the memory device130is a current source140which is capable of imposing on and applying to the memory device130various selected levels of particular current in the same direction, as will be shown and described, i.e., for example, current level I1, current level I2(different from current level I1), and current level I3(different from current levels I1and I2), with in this particular example I3>I2>I1. The current source140may take any well-known form which is capable of providing this function.

FIG. 4illustrates the programming of the memory device130from its erased state to a first state. In this programming step, the current level I1is applied to and imposed on the memory device130by current source140in the direction from electrode132to electrode138. This current I1causes the active layer136(and the overall memory device130) to rapidly switch to a low-resistance or conductive state, the resistance characteristic of which is illustrated at J, this resistance characteristic being determined by the level of current I1applied to the memory device130. Upon removal of such current the active layer136(and memory device130) remain in a conductive or low-resistance state, as indicated by the resistance characteristic J.

FIG. 4also illustrates the read step of the memory device130programmed in accordance with thisFIG. 4. Application of a read voltage Vrfrom higher to lower potential in the forward direction of the memory device130(insufficient to affect the programming of the memory device130) causes a current level W to flow through the memory device130.

FIG. 5illustrates the programming of the memory device130from its erased state to a second state. In this programming step, the current level I2is applied to and imposed on the memory device130by current source140in the direction from electrode132to electrode138. This current I2causes the active layer136(and the overall memory device130) to rapidly switch to a low-resistance or conductive state (lower-resistance than in the first state), the resistance characteristic being illustrated at K, this resistance characteristic being determined by the level of current I2applied to the memory device130. Upon removal of such current, the active layer136(and memory device130) remain in a conductive or low-resistance state, as indicated by the resistance characteristic K.

FIG. 5also illustrates the read step of the memory device130programmed in accordance with thisFIG. 5. Application of the same read voltage Vrfrom higher to lower potential in the forward direction of the memory device130, i.e., from electrode132to electrode138, (again insufficient to affect the programming of the memory device130) causes a current level X to flow through the memory device130.

FIG. 6illustrates the programming of the memory device130from its erased state to a third state. In this programming step, the current level I3is applied to and imposed on the memory device130by the current source140in the direction from electrode132to electrode138. This current I3causes the active layer136(and the overall memory device130) to rapidly switch to a low-resistance or conductive state (lower-resistance than in the first state or the second state), the resistance characteristic being illustrated at L, this resistance characteristic being determined by the level of current I3applied to the memory device130. Upon removal of current the active layer136(and memory device130) remain in a conductive or low-resistance state, as indicated by the resistance characteristic L.

FIG. 6also illustrates the read step of the memory device130programmed in accordance with thisFIG. 6. Application of the same read voltage Vrfrom higher to lower potential in the forward direction of the memory device130, i.e., from electrode132to electrode138(again insufficient to affect the programming of the memory device130) causes a current level Y to flow through the memory device130.

FIG. 7illustrates the read step for the memory device130in its erased state. As shown therein, the same electrical potential Vris applied to the memory device130from higher to lower potential in the forward direction of the memory device130, i.e., from electrode132to electrode138. Again, this electrical potential Vris low enough so as to be insufficient to cause the memory device130to adopt a programmed state. The memory device130in its unprogrammed state provides a very high resistance, the resistance characteristic of the memory device130being illustrated at M, so that substantially no current (Z) flows through the memory device130.

The level of current applied to the memory device130by the current source140determines the resistance characteristic of the memory device130, in particular, determining the slope of the resistance characteristic. As will be seen, the higher the current level applied to the memory device130, the greater the slope of the resistance characteristic, and the lower resistance of the memory device130.

In the present example, the memory device130may adopt any of a plurality of states, in this case, any one of four distinct states, corresponding to four different and distinct resistance characteristics. The state of the memory device130can be read by applying a specific, particularly chosen read voltage Vras described above. With the memory device130in its first state (FIG. 4), application of read voltage Vrcauses current at level W-to flow through the memory device current level W being determined by the resistance characteristic J of the memory device130, which current level W is indicative of the memory device130being in its first state. The current level W can readily be observed.

With the memory device130in its second state (FIG. 5), application of the read voltage Vrcauses current at level X to flow through the memory device130(current level X being determined by the (lower) resistance characteristic K of the memory device130, so that current level X is greater than current level W). The current level X is indicative of the memory device being in its second state, and this current level can readily be observed.

With the memory device130in its third state (FIG. 6), application of the read voltage Vrcauses current at level Y to flow through the memory device130(current level Y determined by the (even lower) resistance characteristic L of the memory device130, so that current level Y is greater than current level X and current level W). The current level Y is indicative of the memory device130being in its third state, and this current level Y can readily be observed.

With the memory device in its erased state (FIG. 7), application of the read voltage Vrcauses substantially no current (indicated at Z) to flow through the memory device130, because of the very high resistance characteristic M (i.e., much higher resistance than in any of the previous examples) of the memory device130. This lack of current flow is indicative of the memory device130being in its erased, or fourth state, which can readily be observed.

FIG. 8is a composite ofFIGS. 4-7, illustrating the various states of the memory device130in one Figure. As will readily be seen, selection of one of a plurality of levels of current I1, I2, I3applied to the memory device130programs the memory device130and determines a corresponding resistance characteristic thereof. As noted above, each different level of current applied to the memory device130results in and determines a corresponding, different resistance characteristic of the memory device130. The resistance characteristic determines the level of current flow through the memory device130during the read step.

In the present example, the memory device130is shown and described as adopting any one of four distinct, individual states. As described above, these four different states of the memory device130can provide two bits of information.

FIG. 9illustrates a first embodiment of memory device array150which incorporates memory devices130of the type described above. As illustrated inFIG. 9, the memory device array150includes a first plurality152of parallel conductors (bit lines) BL0, BL1, . . . BLn, and a second plurality154of parallel conductors (word lines) WL0, WL1, . . . WLnoverlying and spaced from, orthogonal to, and crossing the first plurality of conductors152. A plurality of memory devices130of the type described above are included, each associated with a select diode160having a (forward) threshold Vtand a (reverse) breakdown voltage Vb, to form a memory device-diode structure162connecting a bit line and a word line. Each memory device130is connected in series with a select diode160between a conductor BL of the first plurality152thereof and a conductor WL of the second plurality154thereof at the intersection of those conductors, with the diode160oriented in a forward direction from the conductor BL of the first plurality152thereof to the conductor WL of the second plurality154thereof. For example, as shown inFIG. 9, memory device13000and diode16000in series connect conductor BL0of the first plurality of conductors152with conductor WL0of the second plurality of conductors154at the intersection of those conductors BL0, WL0, memory device13010and diode16010in series connect conductor BL1of the first plurality of conductors152with conductor WL0of the second plurality of conductors154at the intersection of those conductors BL1, WL0, etc. Programming of individual memory devices can be achieved by utilizing comparators as part of the external circuitry of the array150and associated with the memory devices. These comparators function to limit the level of programming current to the memory devices.

FIG. 10illustrates a second embodiment of memory device array250which incorporates memory devices130of the type described above. As illustrated inFIG. 10, the memory device array250includes a first plurality of parallel conductors (bit lines) BL0, BL1, . . . BLn, and a second plurality of parallel conductors (word lines) WL0, WL1, . . . WLn, overlying and spaced from, orthogonal to, and crossing the first plurality of conductors. A plurality of memory devices130of the type described above are included, each associated with a transistor260to form a memory device-transistor structure262connecting a bit line and ground (GND). Each memory device130is connected in series with a transistor260between a conductor BL of the plurality thereof and GND. Each word line is connected to the gates of a row of transistors. Programming of an individual memory device is achieved by utilizing the transistor associated with that device to limit the level of programming current to that device, the level of current being determined by the level of voltage applied to the gate of that transistor.

As examples, in each array, the memory device13000may be programmed to the first state, the memory device13001may be programmed to the second state, the memory device13002may be programmed to the third state, and the memory device1300nmay be in the erased state. Thus, each memory device of the array in the present example is capable of providing two bits of information.

It will be understood that the difference in current level I when programming the memory device130can be set more closely than in the present example, i.e., I1, I2, I3, so that the memory device130would be capable of adopting more than four individual states.

The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Other modifications or variations are possible in light of the above teachings.

The embodiments were chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill of the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally and equitably entitled.