Enhanced channel adapter

The system comprises a first processor, a second processor and non-volatile memory. The non-volatile memory stores messages being transferred between the first and second processors. The non-volatile memory is resettably and logically decoupled from first and second processors to preserve the state of the first and second processors and the messages in the event of a loss of communication or a processor reset. The non-volatile memory increases the rate of message transfer by transferring blocks of messages between the non-volatile memory and the second processor. The non-volatile memory includes status and control registers to store the state of messages being transferred, message queues, and first and second processors. The system may also include a local power source to provide power to the non-volatile memory.

DETAILED DESCRIPTION OF THE INVENTION A description of preferred embodiments of the invention follows. A message transfer unit (MTU) is used to transfer messages from mainframes to other systems by emulating a mainframe peripheral device, such as a tape drive. In typical tape drive manner, the messages being transferred are stored in queues. In this way, legacy application executed by the mainframe believe that they are merely storing data or messages on a tape or reading data or messages from a tape, as described in related U.S. Patent application filed concurrently herewith, Attorney Docket No. 2997.1004-001 , entitled “Message Queue Server System” by Graham G. Yarborough, the entire contents of which are incorporated herein by reference. Within the message transfer unit, there is at least one adapter card that is connected to respective communication link(s), which are connected to at least one mainframe. The adapter card receives/transmits messages from/to the mainframe(s) on a single-message by single-message basis. The messages inside the message transfer unit are transferred between the adapter card and memory. The principles of the present invention improve message transfer rates within the message transfer unit by allowing blocks of messages to be transferred within the MTU, rather than being transferred on a single-message by single-message basis, as is done, between the message transfer unit and the mainframe(s). The principles of the present invention also ensure message recoverability after a system reset or loss of communication by storing messages and the status of MTU devices, including the adapter, on non-volatile memory. This is shown and discussed in detail below. Referring now to FIG. 3 , the MTU 120 includes a plurality of first processors 210 - 1 , 210 - 2 , 210 - 3 , . . . 210 -N, second processors 230 - 1 , 230 - 2 , . . . 230 -N, and non-volatile memory 220 . Also included are communication links 150 - 1 , 150 - 2 , 150 - 3 , . . . 150 -N, first data buses 240 - 1 , 240 - 2 , 240 - 3 , . . . 240 -N, and second data buses 250 - 1 , 250 - 2 , 250 - 3 , . . . 250 -N. The first processors 210 may be MTU I/O channel processors, such as Enterprise Systems Connection (ESCON®) channel processors. Each I/O channel processor 210 performs I/O operations and executes message transfers to/from a mainframe system using a first data protocol. Each I/O channel processor 210 uses an associated communication link 150 to communicate with a mainframe computer ( FIG. 1 ). The communication links 150 may be fibre optic links, transferring messages at a rate of about 200 megabits/sec. The first data buses 240 are used to transfer messages between the first processors 210 and non-volatile memory 220 . The first data buses 240 may be a shared bus. The non-volatile memory 220 is coupled to the I/O channel processors 210 and second processors 230 . The non-volatile memory 220 should have a capacity of about 2 gigabytes or more to store messages being transferred between the I/O channel processors 210 and second processor 230 . In addition, the non-volatile memory 220 is shareable and may be accessed by the I/O channel processors 210 and second processors 230 . The second data buses 250 are used to transfer message between the non-volatile memory 220 and second processors 210 . Similar to the first data buses, the second data buses 250 also may be a shared bus. The second processors 230 may be message queue processors. The queue processors 230 include messaging middleware queues. When all the messages in a message queue 320 are received from the non-volatile memory 220 in a messaging middleware queue, the completion of the queue is indicated by an end of tape marker as discussed in related U.S. patent application filed concurrently herewith, entitled “Message Queue Server System” by Graham G. Yarbrough, the entire principles of which are incorporated herein by reference. In addition, the queue processors 230 have access to the non-volatile memory 220 . Although not shown in FIG. 3 , it is understood that one or more queue processors 230 may share the same queue of messages stored in the memory 220 . FIG. 4 is a block diagram depicting message transfers among the components of the message transfer unit 120 of FIG. 3 . As shown in FIG. 3 , the MTU 120 comprises a plurality of I/O channel processors 210 , non-volatile memory 220 , and a plurality of queue processors 230 . The MTU 120 also includes (i) first address/control buses 310 - 1 , 310 - 2 , 310 - 3 , . . . 310 -N between the I/O channel processors 210 and non-volatile memory 220 , and (ii) second address/control buses 330 - 1 , 330 - 2 , 330 - 3 , . . . 330 -N between the non-volatile memory 220 and queue processors 230 . In an outbound message transfer where messages are being transferred from the mainframe to the queue processors 230 , each I/O channel processor 210 receives messages from the mainframe using a first data transfer protocol over its fibre optic link 150 . In an ESCON communication system, the first data transfer protocol is single message by single message transfer since ESCON channels or fibre optic links operate on a single message by single message basis. Upon receipt of a message from the mainframe, using the first data transfer protocol, each I/O channel processor transfers the message 140 - 1 , 140 - 2 , . . . 140 -N over its first data bus 240 to in the non-volatile memory 220 . The message 140 is stored in the non-volatile memory 220 and subsequently, a positive acknowledgment is returned to the mainframe. When the mainframe receives the positive acknowledgment, the mainframe transfers the next message in the queue to the MTU 120 until all the messages in the queue are stored in the non-volatile memory 220 . In other words, the I/O channel processor 210 is not released for another message until the message is properly stored in the memory 220 . As the message 140 from I/O channel processors 210 is stored in the non-volatile memory 220 , the non-volatile memory 220 also receives address/control signals over the first address/control bus 310 for the message 140 . The message 140 is located and stored according to its address as indicated in the address/control signals. The address/control signals also indicate to which message queue 320 the message 140 belongs and the status of message queue. The messages of a queue 320 are stored one by one in its designated location in the non-volatile memory 220 . A message queue 320 is complete when all the messages to be transferred are stored in the queue 320 . As messages are received and stored in the non-volatile memory 220 , address/control signals may be sent over the second address/control buses 330 - 1 , 330 - 2 , . . . 330 -N to indicate that the messages are ready to be transferred to a messaging middleware queue on at least one queue processor 230 . The message are maintained in the non-volatile memory 220 until instructed to be deleted by the mainframe computer or one of the queue processors 230 to ensure message recoverability. As described above, the non-volatile memory 220 is shareable and may be accessed by queue processors 230 . Each queue processor 230 has access to all the message queues 320 in the non-volatile memory 220 . At any time, a queue processor 230 may access a message queue 320 and initiate transfer of messages in the queue 320 . Similarly, the queue processor 230 may disassociate itself from the message queue 320 and interrupt the transfer of messages. Thus, the non-volatile memory 320 is logically decoupled from the queue processors 230 . The queue processors 230 may be brought online and offline at unscheduled times. When a queue processor suddenly goes offline, the status of the queue processor 230 , message transfer, message queue 320 , and non-volatile memory are stored and maintained in the non-volatile memory 220 . The message queues 320 may be transferred from the non-volatile memory 220 to the queue processors 230 using a second data transfer protocol. The second data transfer protocol may be blocks of message transfers. A block of messages 340 may include up to about 100 messages. However, the block may include only one message. Some blocks of messages may contain a whole queue of messages 340 - 3 and transferred from the non-volatile memory 220 to the queue processor 230 -N. As illustrated certain blocks of messages may 340 - 1 and 340 - 2 contain a subset of messages from a message queue, such as a block of two to three messages 340 - 1 and 340 - 2 , and transferred over the second data bus 250 - 1 . Transferring blocks of messages between the non-volatile memory 220 and queue processors 230 improves the message transfer efficiency. The rate of message transfer resulting from a block transfer may be as much as five times faster than the rate of message transfer when done as single message by single message transfers. Two or more queue processors 230 - 1 and 230 - 2 may access the same message queue 320 - 1 and transfer different subsets of messages 340 - 1 and 340 - 2 in the same message queue 320 - 1 . As shown, the queue processor 230 - 1 is transferring a subset of messages 340 - 1 , including messages 1 and 2 of the message queue 320 - 1 . Another queue processor 230 - 2 is transferring a subset of messages 340 - 2 , including messages 3 and 4 of the same message queue 320 - 1 . It should be understood that in an inbound message transfer, messages are similarly transferred from the queue processor 230 to the mainframe as described above. Each queue processor 230 may have memory, usually volatile, to store and queue the messages received from the non-volatile memory 220 until they are processed. When one of the queue processors 230 loses communication with the non-volatile memory and where the queue processors 230 are using a shared bus, another queue processor 230 may recover the status of the messages being transferred. The queue processor 230 is allowed to continue transferring the messages that were interrupted by the loss of communication. For example, if the queue processor 230 - 1 was transferring a queue of messages 320 - 1 and loses communication after transferring and processing messages 1 and 2 of the queue 321 - 1 , then another queue processor 320 - 2 may continue the transfer of the rest of the messages in the queue 320 - 1 . To determine where to start the continued queue transfer, the queue processor 320 - 2 checks the state of the message queue 230 - 1 and the messages being transferred to determine the last message that was properly transferred to the queue processor 320 - 1 . The queue processor 320 - 2 may also check the state of the queue processor 320 - 1 as stored in status registers (not shown) in the memory 220 , and request transfer of the rest of the messages 3 , 4 , . . . N of the queue 320 - 1 . The state of the message queue 320 - 1 is changed in the status registers in the memory 220 so that the queue processor 320 - 1 is notified of the transfer of messages when it comes back online. FIG. 5 is a block diagram of an adapter 400 employing the principles of the present invention. The adapter 400 includes an I/O channel processor 210 , non-volatile memory 220 , reset register 420 , status and control registers 460 , local power source 430 , reset button 410 , relay circuit 440 , and processor reset detector 480 . The connectors 251 are communication ports on the adapter 400 connecting the non-volatile memory 220 to a plurality of queue processors 230 . Each queue processor bus 250 is associated to a connector 251 to access the non-volatile memory 220 . The adapter 400 is resettably decoupled from the I/O channel processors 210 and queue processors 230 . The adapter 400 is resettably isolated from the queue processor buses 250 - 1 to ignore a bus reset and loss of communication from any of the queue processors 230 . During a restart or reset of a queue processor 230 - 1 , the relay circuit 440 may be used to isolate the adapter 400 from a second data bus 240 - 1 . Thus, the message queues 230 are preserved in the non-volatile memory 220 during a reset or restart of the queue processor 230 . A programmable interface, such as control registers 460 , may permit the adapter 400 to honor a reset signal through a second processor reset line 470 when desired. Similarly, a manual reset button 410 is provided on the MTU 120 to allow manual system reboot along with a full adapter reset. The state and control structures of the adapter 400 , MTU devices, message queues and messages being transferred are maintained in the status and control registers 460 of the non-volatile memory 220 . At a power reset or reapplying power, a queue processor 230 begins executing a boot program. The queue processor 230 accesses the status and control registers 460 , in which data are stored indicative of (i) the operation and state of the queue processor 230 , (ii) the last message being transferred, and (iii) message queues. A local power source 430 , such as a battery 430 , preserves the non-volatile memory in the event of a power-off reset or power loss. The battery 430 provides power to the non-volatile memory to maintain message queues 320 and status and control registers 460 . The capacity of the local power source 430 is preferably sufficient enough so that power is provided to the non-volatile memory 220 until system power returns. A processor reset detector 480 determines when a queue processor 230 or I/O channel processor 210 resets. When the detector 480 determines that a queue processor 230 is resetting, then the non-volatile memory 220 is decoupled from second data buses 330 to maintain the messages 320 stored in the memory 220 . The state of the non-volatile memory 220 , second processors 220 , and message queues 320 are retained to ensure message recoverability. FIG. 6 is a flow diagram of a message recovery process 500 executed by the adapter 400 of FIG. 5 . After a reset or reapplying power, in step 510 , the queue processors 230 obtain access to the non-volatile memory 220 . In step 520 , the queue processors 230 read the status and control registers 460 to determine the status of the queue processors 230 and the messages being transferred before the reset or communication loss. The status and control registers 460 also provide the status information of the message queues 320 . In step 530 , the queue processor 230 determines the location of the last messages being transferred before the interruption. In step 540 , the status of the message queue 320 is checked. In step 550 , it is determined whether the message queue 320 is shareable. If the message queue is shareable, then the message queue status is checked at step 560 to determine whether another queue processor 220 has accessed the message queue during the interruption. In step 570 , the queue processor 230 determines whether the transfer of the messages in the queue 320 has been completed. If the transfer is completed, the queue processor starts to transfer the rest of the messages in the message queue 320 at step 590 . If so, the transfer of the message queue 320 has been completed by another queue processor and, thus, the message recovery process ends at step 595 . If the message queue is not shareable, then at step 580 , the queue processor 230 determines if the message queue 320 is disabled. The message queue 320 may be disabled by the mainframe computer or due to transfer errors. If disabled, then the message queue 320 may not be accessed by the queue processor 230 and the recovery process ends at step 595 . If not disabled, the rest of the messages are transferred at step 590 . The recovery process ends at step 595 . FIGS. 7A and 7B are flow diagrams of a message queue transfer process 600 executed by the system of FIG. 5 . In step 605 , the I/O channel processor 210 receives a single message from the mainframe computer. In step 610 , the message is written to the non-volatile memory 220 . In step 620 , the I/O channel processor and message status is written to the status and control registers 460 . In step 630 , the system determines whether all the messages in a message queues have been received. If the messages have been received, the queue status is written to the status and control registers 460 . If the messages have not been received, then steps 605 to 620 are repeated until all messages in the queue 320 are stored in the non-volatile memory 220 . In step 650 , after all the messages are stored in the non-volatile memory 220 , the queue processors 230 may obtain access to the queue. Depending on the status of the queue 320 , messages are transferred at step 660 to one or more queue processors 230 using a second data transfer protocol. In step 670 , after the transfer of each block of messages, the states of the queue processor and the message queue 320 are written into the status and control registers 460 . In step 680 , the queue processor confirms the receipt of messages. If all messages have been received, it is determined at step 690 whether all the messages in the queue have been transferred. If all the messages have not been received, steps 660 to 680 are repeated. The queue processor 230 returns to step 650 and repeats steps 650 to 690 to transfer another queue of messages. FIG. 8 is a flow diagram of a memory reset process 700 executed by the adapter 400 of FIG. 5 . As described above, a memory reset may be initiated by manually pushing the reset button 410 or programmed in the control register. In step 705 , the status of the non-volatile memory 220 and queue processors 230 are retained and updated in the status and control registers 460 . In step 710 , the adapter 400 receives a reset instruction. In step 715 , all the messages in the non-volatile memory are deleted. In step 720 , the status and control registers 460 are reseted. It should be understood that the processes of FIGS. 4 - 6 may be executed by hardware, software, or firmware. In the case of software, a dedicated or non-dedicated processor may be employed by the adapter 400 to execute the software. The software may be stored on and loaded from various types of memory, such as RAM, ROM, or disk. Whichever type of processor is used to execute the process, that processor is coupled to the components shown and described in reference to the various hardware configurations of FIGS. 3 - 5 , so as to be able to execute the processes as described above in reference to FIGS. 6 - 8 . While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.