Trench power semiconductor component and method of manufacturing the same

The present disclosure provides a trench power semiconductor component and a manufacturing method thereof. The trench gate structure of the trench power semiconductor component is located in the at least one cell trench that is formed in an epitaxial layer. The trench gate structure includes a shielding electrode, a gate electrode disposed above the shielding electrode, an insulating layer, an intermediate dielectric layer, and an inner dielectric layer. The insulating layer covers the inner wall surface of the cell trench. The intermediate dielectric layer interposed between the shielding electrode and the insulating layer has a bottom opening. The inner dielectric layer interposed between the shielding electrode and the intermediate dielectric layer is made of a material different from that of the intermediate dielectric layer, and fills the bottom opening so that the space of the cell trench beneath the shielding electrode is filled with the same material.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates to a trench power semiconductor component and a method of manufacturing the same; more particularly, to a trench power semiconductor component having a shielding electrode and a method of manufacturing the same.

2. Description of Related Art

Power loss in a conventional power metal oxide semiconductor field transistor (Power MOSFET) can be classified into two types, switching loss and conduction loss. Drain-to-gate capacitance is an important parameter in switching loss. A high drain-to-gate capacitance leads to the increase in switching loss, thereby limiting the switching rate of power MOSFETs. Therefore, a power MOSFET of high gate-to-drain capacitance is not suitable for high frequency circuits.

Power MOSFETs in the prior art include a shielding electrode located in the lower half part of the gate trench so as to reduce the gate-to-drain capacitance and increase the breakdown voltage without adversely affecting the on-resistance.

SUMMARY OF THE INVENTION

Accordingly, the present disclosure provides a trench power semiconductor component and a method of manufacturing the same decreasing the distribution density of the electric field at the bottom of the cell trench during a reverse bias is applied to the trench power semiconductor component by disposing an intermediate dielectric layer having a bottom opening in the cell trench and an inner dielectric layer filling the bottom opening.

One embodiment of the present disclosure provides a trench power semiconductor component including a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is disposed on the substrate, the epitaxial layer having at least one cell trench formed therein. The trench gate structure is located in the at least one cell trench. The trench gate structure includes a shielding electrode, a gate electrode, an insulating layer, an intermediate dielectric layer and an inner dielectric layer. The shielding electrode is located in the lower half part of the at least one cell trench, and the gate electrode is disposed on the shielding electrode and insulated from the shielding electrode. The insulating layer covers an inner wall surface of the at least one cell trench. The intermediate dielectric layer is interposed between the insulating layer and the shielding electrode, the intermediate dielectric layer having a bottom opening located at a bottom side of the at least one cell trench. The inner dielectric layer is interposed between the intermediate layer and the shielding electrode. The inner dielectric layer and the intermediate dielectric layer are made of different materials, and the inner dielectric layer fills the bottom opening so that the portions of the trench gate structure located under the shielding electrode are made of the same material.

Another embodiment of the present disclosure provides a method of manufacturing a trench power semiconductor component. The method includes: forming a cell trench in the epitaxial layer; and forming a trench gate structure in the cell trench. The step of forming the trench gate structure in the trench further includes: forming an insulating layer covering an inner wall surface; forming an intermediate dielectric layer and an inner dielectric layer in the cell trench, in which the intermediate dielectric layer has a bottom opening located at a bottom side of the cell trench, and the inner dielectric layer cover the intermediate dielectric layer and fills the bottom opening; forming a heavily-doped semiconductor material in a lower half part of the cell trench; performing a thermal oxidation process so that a top portion of the heavily-doped semiconductor material is oxidized to form an inter-electrode dielectric layer and another portions of heavily-doped semiconductor material without being oxidized form a shielding electrode; and forming a gate electrode in an upper half part of the cell trench, in which the gate electrode is isolated from the shielding electrode by the inter-electrode dielectric layer.

In summary, since the portions of the trench power semiconductor component of the present disclosure formed at the bottom of the cell trench and under the shielding electrode are made of the same material, the distribution density of the electric field at the bottom of the cell trench can be reduced during a reverse bias is applied to the trench power semiconductor component, thereby improving the breakdown voltage of the trench power semiconductor component adversely affecting the on-resistance.

For further understanding of the present disclosure, the following embodiments are provided along with illustrations to facilitate the disclosure of the present disclosure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The aforementioned illustrations and following detailed description are exemplary for the purpose of further explaining the scope of the present disclosure. Other objectives and advantages related to the present disclosure will be illustrated in the following description and appended drawings.

Referring toFIG. 1, the trench power semiconductor component T1includes a substrate10, an epitaxial layer11, and a trench gate structure13. The trench power semiconductor component T1can be a trench power MOSFET or a semiconductor component having Schottky diodes. In the embodiment shown inFIG. 1, a trench power MOSFET is taken as an example to describe.

As shown inFIG. 1, the substrate10is heavily doped with first conductivity-type impurities to serve as a drain region of the trench power semiconductor component. The aforementioned first conductivity-type impurities can be N-type or P-type impurities.

The trench power semiconductor component T1further includes a drain electrode14formed on the bottom side of the substrate10so as to be electrically connected to an external control circuit.

The epitaxial layer11is disposed on the substrate10, the epitaxial layer11having the same conductivity type as that of the substrate10, but the epitaxial layer11having lower doping concentration than that of the substrate10.

Furthermore, in the embodiment of theFIG. 1, by doping impurities with different conductivity types and doping concentrations, the epitaxial layer11can be divided into a drift region110, a base region111, and a source region112. The base region111and the source region112formed in the epitaxial layer11are adjacent to the sides of the trench gate structure13, and the drift region110formed in the epitaxial layer11is positioned nearer to a side of the substrate10. That is to say, the base region111and the source region112are located at an upper part of the epitaxial layer11, and the drift region110is located at a lower part of the epitaxial layer11.

Specifically, the base region111is formed by doping the second conductivity type impurities into the epitaxial layer11, and the source region112is formed by heavily doping the first conductivity type impurities in the base region111. The source region112is disposed above the base region111, and the base region111has lower doping concentration than that of the source region112.

Furthermore, in the present embodiment, the epitaxial layer11includes at least one cell trench12extending from a surface11S of the epitaxial layer11to the drift region110in a direction perpendicular to the surface11S. In the present disclosure, the cell trench12is substantially divided into an upper half part and a lower half part according to a reference level at which the bottom edge of the base region111is located.

As shown inFIG. 1, at least one trench gate structure13is disposed in the corresponding cell trench12. The trench gate structure13includes a shielding electrode130, a gate electrode131, an insulating layer132, an intermediate dielectric layer133, and an inner dielectric layer134.

The shielding electrode130is located in the lower half part of the cell trench12. The cell trench12is deep trench, the deep trench assisting the trench power semiconductor component T1in improving the breakdown voltage, but increasing the gate-to-drain capacitance and source/drain on resistance (Rdson). Accordingly, in the embodiment of the present disclosure, by disposing the shielding electrode130in the lower half part of the cell trench12, the gate-to-drain capacitance (Cgd) can be reduced, thereby reducing the switching loss.

The shielding electrode130can be electrically connected to the source electrode, electrically floating, or to be biased by variable bias voltages. When the trench power semiconductor component T1is operated in reverse bias, the shielding electrode130generates a pinch-off effect, such that the charge balance and the reduced surface field are generated, thereby improving the breakdown voltage. Accordingly, the doping concentration in the drift region110can be further increased, thereby reducing the on-resistance of the trench power semiconductor component.

The gate electrode131is disposed above and isolated from the shielding electrode130. The gate electrode131and the shielding electrode130are insulated from each other. The gate electrode131and the shielding electrode130can be made of heavily-doped polysilicon. The bottom end of the gate electrode131is located at a horizontal plane that is lower than a lower edge of the base region111. For example, in an NMOS transistor, when a positive bias larger than a threshold voltage is applied to the gate electrode131, electrons are induced to accumulate at the sidewalls of the cell trench12, thereby creating an inverse channel in the base region111and turning on the trench power semiconductor component T1. On the other hand, when a bias less than the threshold voltage is applied to the gate electrode131, the trench power semiconductor component T1is in OFF state.

The trench gate structure13further includes an inter-electrode dielectric layer135interposed between the shielding electrode130and the gate electrode131so as to isolate the gate electrode131from the shielding electrode130. The inter-electrode dielectric layer135can be made of oxide (e.g. silicon oxide), nitride (e.g. silicon nitride), or the other insulator, which is not limited to the examples provided herein.

The insulating layer132covers the inner wall surface of the cell trench12and has a contour that roughly matches that of the inner wall surface of the cell trench12. In the present embodiment, the gate electrode131is isolated from the base region111and the source region112by the insulating layer132. The insulating layer132has two opposite inner sidewall surfaces132aand a bottom surface132bconnected therebetween. The insulating layer132can be an oxide layer, such as silicon oxide, that is formed by a thermal oxidation process.

The intermediate dielectric layer133is disposed between the insulating layer132and the shielding electrode130. In the present embodiment, the intermediate dielectric layer133is located at the lower half part of the cell trench12and covers the two opposite inner sidewall surfaces132aof insulating layer132. Specifically, the intermediate dielectric layer133includes a first wall portion133aand a second wall portion133b, which are respectively located at two opposite sides of the shielding electrode130. A bottom end of the first wall portion133aand a bottom end of the second wall portion133bare separated from each other so as to form a bottom opening (not labeled).

In other words, the first wall portion133aand the second wall portion133brespectively cover the two inner sidewall surfaces132aof the insulating layer132; however, neither the first wall portion133anor the second wall portion133bcovers the bottom surface132bof the insulating layer132. In one preferred embodiment, a distance between the bottom end of the first wall portion133aand the bottom end of the second wall portion133bin a width direction of the cell trench12, i.e., the width D1of the bottom opening, in a direction parallel to a surface11S of the epitaxial layer11is greater than the width W of the shielding electrode130. That is to say, both the first wall portion133aand the second wall portion133bdo not have any portion beneath the shielding electrode130.

Furthermore, the thicknesses of the first and second wall portions133a,133bgradually decrease in a depth direction of the cell trench12. In another embodiment, the thicknesses of the first and second wall portions133a,133bare substantially the same, instead of gradually decreasing, in the depth direction of the cell trench12.

The inner dielectric layer134is positioned in the lower half part of the cell trench12and interposed between the intermediate dielectric layer133and the shielding electrode130. To be more specific, the inner dielectric layer134is in contact with and surrounds two opposite side surfaces and a bottom surface of the shielding electrode130. Furthermore, the inner dielectric layer134fills the bottom opening of the intermediate dielectric layer133, thereby separating the bottom portion of the shielding electrode130from the epitaxial layer11.

It is noting that the inner dielectric layer134and the insulating layer132are made of the same material that is different from the material of the intermediate dielectric layer133in the present embodiment. For example, the materials of the inner dielectric layer134and the insulating layer132can be silicon oxide, and the material of the intermediate layer133can be silicon nitride.

In other words, the space at the bottom of the cell trench12and beneath the shielding electrode130is filled with the same material. It is noting that when the trench power semiconductor component T1is operated in reverse bias, the electric field strength near the bottom of the cell trench12is higher due to the curved bottom surface of the cell trench12having a smaller radius of the curvature. If the material which is located at the bottom of the cell trench12, (i.e., the material between the curved bottom surface of the cell trench12and the shielding electrode130) is a composite material or a multi-layer including more than one materials, the electric field will be easily distorted, and thus reducing the breakdown voltage of the trench power semiconductor component T1.

Accordingly, in the embodiment of the present disclosure, the bottom ends of the first and second wall portions133a,133bof the intermediate dielectric layer133are separated from each other to form the bottom opening, and the inner dielectric layer134fills the bottom opening, such that the material near the curved bottom surface of the cell trench12can be simple, thereby decreasing the distribution density of the electric field at the bottom of the cell trench and then increasing the breakdown voltage. Since the breakdown voltage is increased, the doping concentration of the drift region110can be further optimized so as to reduce the on-resistance, thereby enhancing the switching efficiency of the trench power semiconductor component T1.

Furthermore, the trench power semiconductor component T1of the embodiment in the present disclosure further includes an interlayer dielectric layer15, a plurality of conductive posts16, and a conductive layer17.

Please refer toFIG. 1. The interlayer dielectric layer15is disposed on the surface11S of the epitaxial layer11to increase the flatness of the conductive layer17. The interlayer dielectric layer15can be made of the material selected from a group consisting of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), oxide, nitride and any combination thereo.

Furthermore, the interlayer dielectric layer15includes a plurality of source contact windows15hwhich extend from an upper surface of the interlayer dielectric layer15to the base region111. The conductive layer17covers the interlayer dielectric layer15and can be electrically connected to the source region112by the conductive posts16which are respectively disposed in the source contact windows15h. Furthermore, the conductive layer17can function as a source electrode of the trench power semiconductor component T1for electrically connecting to an external control circuit. In another embodiment, the conductive layer17can be electrically connected to the gate electrode131or the shielding electrode130.

Please refer toFIG. 2. The same reference numerals are given to the same elements of the trench power semiconductor component T1′ in the present embodiment corresponding to those inFIG. 1, and descriptions of the common portions are omitted. In trench power semiconductor component T1′ of the present embodiment, both the first wall portion133aand the second wall portion133bof the intermediate dielectric layer133extend from the upper half part to the lower half part of the cell trench12.

Accordingly, in the present embodiment, a part of the first wall portion133aand a part of the second wall portion133b, both of which are located at the upper half part of the cell trench12, are respectively located at two opposite sides of the gate electrode131. The first wall portion133aand the second wall portion133brespective cover two inner sidewall surfaces132aof the insulating layer132. Therefore, in the present embodiment, a part of the insulating layer132in conjunction with a part of the intermediate dielectric layer133located at the upper half part of the cell trench12function as a gate insulating layer.

In the present embodiment, the insulating layer132and the intermediate dielectric layer133are made of two different materials to function as the gate insulating layer so as to modify the work function difference between the gate electrode131and the base region111, thereby reducing the leakage current when the trench power semiconductor component T1′ is operated in a reverse bias.

Furthermore, in the embodiment shown inFIG. 1, the bottom surface132bof the insulating layer132is located above the bottom surface of the cell trench12, and the inner dielectric layer134covers the bottom surface132bof the insulating layer132, the inner dielectric layer134thus being spaced apart from the bottom surface of the cell trench12. However, in the present embodiment, the inner dielectric layer134is in contact with the bottom surface of the cell trench12. Accordingly, the bottom space of the cell trench12is filled with the inner dielectric layer134so as to decrease the electric field strength near the bottom of the cell trench12. Therefore, in the present embodiment, it is not necessary that the material of the inner dielectric layer is the same as that of the insulating layer132.

Please refer toFIG. 3andFIG. 4. Compared to the embodiments respectively shown inFIG. 1andFIG. 2, the cell trench12of the trench power semiconductor component T2has a larger width in a direction parallel to the surface11S of the epitaxial layer. Since the width of the cell trench12is larger, a curve-shaped bottom surface12S of the cell trench has a greater radius of curvature, which decreases the distribution density of the electric field at the bottom of the cell trench12. Through the technical solution mentioned above, the trench power semiconductor component T2of the present embodiment can withstand a higher voltage and operate under a higher voltage, which ranges approximately from 60 V to 250 V.

Furthermore, compared to the embodiments shown inFIGS. 1-3, the trench power semiconductor component T2ofFIG. 4has a shielding electrode130of a larger width W1, which contributes to a smaller gate-to-drain capacitance (Cgd). In the embodiments shown inFIG. 3andFIG. 4, the top surface of the inter-electrode dielectric layer135and the top surface the inner dielectric layer134are connected to each other and commonly forms a mountain-shaped curve S1, the peak of which is located right above the shielding electrode130.

Please referring toFIG. 5, in the present embodiment, the cell trench12′ has an open-end portion12aand a body portion12bconnected thereto. The inner surface of the open-end portion12ais a slope extending from the surface11S of the epitaxial layer11towards the body portion12b. More specifically, the width of the open-end portion12adecreases from the surface11S of the epitaxial layer11along the depth direction of the trench12′.

In this way, the cell trench12′ will not be closed by the thermal oxidation layer formed at the opening end12aof the cell trench12′ when a thermal oxidation process is performed before the step of forming the gate electrode131. Furthermore, in the present embodiment, an edge of the base region111and an edge of the source region112are inclined downward corresponding to an inclined direction of the slope of the open-end portion12a.

Please refer toFIG. 6. The method of the present disclosure at least includes a step S100of forming an epitaxial layer on a substrate; a step S200of forming a cell trench in the epitaxial layer; a step S300of forming a trench gate structure in the trench, and a step S400of forming a base region and a source region in the epitaxial layer, in which the source region is located above the base region.

It should be noted that the step S300of forming the trench gate structure according to the present disclosure can includes a plurality of steps, which will be explained in the following description.

In step S301, an insulating layer is formed on the inner wall surface of the cell trench. Subsequently, in step S302, an intermediate dielectric layer and an inner dielectric layer are formed in the cell trench to cover the insulating layer, in which the intermediate dielectric layer has a bottom opening, and the inner dielectric layer covers the intermediate dielectric layer and fills the bottom opening.

Please refer toFIGS. 7A to 7C, which show each process of the step S302of the method of manufacturing trench power semiconductor component according to an embodiment of the present disclosure.

As shown inFIG. 7A, an epitaxial layer11has been formed on the substrate10. Furthermore, a cell trench12has been formed in the epitaxial layer11, and the insulating layer132has been formed on the inner wall surface of the cell trench12, the insulating layer132having a contour that roughly matches that of the inner wall surface of the cell trench12. The insulating layer132has two opposite inner sidewall surfaces132aand a bottom surface132bconnected therebetween. In one embodiment, the insulating layer132is silicon oxide layer.

As shown inFIG. 7A, an initial intermediate dielectric layer133′ is formed, the initial intermediate dielectric layer133′ covering the surface11S of the epitaxial layer11, the inner sidewall surfaces132aand the bottom surface132bof the insulating layer132. The initial intermediate dielectric layer133′ is made of different material from that of the insulating layer132. In one embodiment, the initial intermediate dielectric layer133′ is a silicon nitride layer.

Furthermore, in one embodiment, the fabrication parameters of the initial intermediate dielectric layer133′ can be controlled so that the thickness of the initial intermediate dielectric layer133′ gradually decreases from the surface11S of the epitaxial layer11to a bottom of the cell trench12.

Subsequently, referring toFIG. 7B, a portion of the initial intermediate dielectric layer133′ that covers the bottom surface132bof the insulating layer132is removed so as to form the intermediate dielectric layer133having the bottom opening133h. In other words, the intermediate dielectric layer133includes a first wall portion133aand a second wall portion133brespectively covering the two opposite inner sidewall surfaces132a, and a bottom end of the first wall portion133aand a bottom end of the second wall portion133bare separated from each other to form the bottom opening133h.

It should be noting that since the thickness of a portion of the initial intermediate dielectric layer133′ located on the epitaxial layer11is greater than that of another portions located in the cell trench12, the portion of the initial intermediate dielectric layer133′ located on the epitaxial layer11would not be completely removed after a dry etching process, thereby forming the intermediate dielectric layer133having the bottom opening133h. In another embodiment, the dry etching process can be performed through a photo mask to etch the portion of the initial intermediate dielectric layer133′ that is predetermined to be removed.

In another embodiment, it is likely that a portion of the insulating layer132located at the bottom of the cell trench12is also removed during the step of removing the bottom portion of the initial intermediate dielectric layer133′ covering the bottom surface132b. That is to say, the portion of the insulating layer132located at the bottom of the cell trench12can be selectively removed or remained.

In one preferred embodiment, the width of the bottom opening133h, i.e., the distance between the bottom ends of the first and second wall portions133a,133b, at least allow the bottom surface132bof the insulating layer132or the bottom surface of the cell trench12to be exposed from the bottom opening133h.

Subsequently, as shown inFIG. 7C, an initial inner dielectric layer134′ is formed on the surface11S of the epitaxial layer11and in the cell trench12. Furthermore, the initial inner dielectric layer134′ fills the bottom opening133hof the intermediate dielectric layer133.

In the present embodiment, the material of the initial inner dielectric layer134′ is different from that of the intermediate dielectric layer133, but the same as that of the insulating layer132. In one embodiment, both the insulating layer132and the initial inner dielectric layer134′ are silicon oxide layers, and the intermediate dielectric layer133is silicon nitride layer. As such, the bottom space beneath the shielding electrode130of the cell trench12can be filled with the same material.

Please refer toFIG. 6andFIG. 7D. Subsequently, in step S303, a heavily doped semiconductor material is formed in the lower half part of the cell trench. As shown inFIG. 7D, the heavily doped semiconductor material130′ has been formed in the cell trench12. In one embodiment, a polycrystalline silicon layer can first be formed covering the epitaxial layer11and the cell trench12disposed therein, and then the polycrystalline silicon layer is etched back, in which only the polycrystalline silicon layer in the lower half part of the cell trench12is left un-etched so as to form the heavily doped semiconductor material130′. The heavily doped semiconductor material130′ can be doped poly-Si containing selected conductivity-determining impurities.

Thereafter, the method of manufacturing the trench power semiconductor component according to one embodiment of the present disclosure further includes a step of removing the initial inner dielectric layer134′ located in the upper half part of the cell trench12so as to form the inner dielectric layer134located in the lower half part of the cell trench12. In one embodiment, the initial inner dielectric layer134′ located in the upper half part of the cell trench12can be removed by performing a selective etching process with the intermediate dielectric layer133and the heavily doped semiconductor material130′ functioning as a mask.

Please refer toFIG. 6andFIG. 7E. In step S304, a thermal oxidation process is performed to oxidize a top portion of the heavily doped semiconductor material for forming an inter-electrode dielectric layer. As shown inFIG. 7E, after the thermal oxidation process, the top portion of the heavily doped semiconductor material130′ is oxidized to form the inter-electrode dielectric layer135. Furthermore, the portion of the heavily doped semiconductor material130′ that is left un-oxidized forms the shielding electrode130.

Please refer toFIG. 7F. In the present embodiment, parts of the first and second wall portions133a,133bthat is located in the upper half part of the cell trench12are removed, thereby forming the first wall portion133aand the second wall portion133bof the embodiment shown inFIG. 1. That is to say, the first and second wall portions133a,133bare respectively located at two opposite sides of the shielding electrode130and only cover the lower parts of the two inner sidewall surfaces132aof the insulating layer132, respectively. In one embodiment, a selective etching process can be performed to remove the parts of the first and second wall portions133a,133bthat is located in the upper half part of the cell trench12. It is noting that the step shown inFIG. 7Fcan be omitted in another embodiment.

Please refer toFIG. 6andFIG. 7G. Subsequently, in step S305, a gate electrode is formed in the upper half part of the cell trench. As shown inFIG. 7Gthe gate electrode131is formed in the cell trench12and disposed above the shielding electrode130.

Specifically, in the previous step shown inFIG. 7F, the insulating layer132, the intermediate dielectric layer133, the inner dielectric layer134and the inter-electrode dielectric layer135jointly define a groove h1in the cell trench12. Accordingly, in the step of forming the gate electrode131, a heavily doped polycrystalline silicon can first be formed covering the epitaxial layer11and the groove h1disposed therein, and then the heavily doped polycrystalline silicon is etched back so as to form the gate electrode131. By performing the abovementioned steps S301to S305, the trench gate structure13of the trench power semiconductor component T1shown inFIG. 1can be fabricated.

Please refer toFIG. 6andFIG. 7H. Thereafter, in step S400, a base region and a source region are formed in the epitaxial layer, in which the source region is located above the base region.

Specifically, a base doping process is performed on the epitaxial layer11to form a lightly-doped region in the epitaxial layer11, in which the lightly-doped region has a conductivity type opposite to that of the epitaxial layer11. Subsequently, a source doping region is performed on the lightly-doped region so as to form a highly-doped region having a conductivity type opposite to that of the lightly-doped region. A drive-in process is then performed so that the impurities in the lightly-doped region and the impurities in the highly-doped region diffuse, thereby forming the base region111and the source region112located above the base region111.

In the present embodiment, the lower edge of the base region111is located at a level that is higher than the top ends of the first and second wall portions133a,133b.

Next, a redistribution layer can be formed on the epitaxial layer11so that the source region112, the gate electrode131, and the shielding electrode130can be electrically connected to the external control circuit. The redistribution layer can be formed by any conventional technique, and the other details should be easily understood by one of ordinary skill in the art according to the abovementioned embodiments and then omitted herein.

Please refer toFIGS. 8A to 8F, which are partial sectional schematic views respectively illustrating each step of manufacturing a trench power semiconductor component according to another embodiment of the present disclosure. The steps respectively shown inFIGS. 8A to 8Fcan be performed after the step shown inFIG. 7Ato fabricate the trench power semiconductor component T1′ shown inFIG. 2.

In other words, before the step shown inFIG. 8A, the epitaxial layer11has been formed on the substrate10, and the cell trench12has been formed in the epitaxial layer11, as shown inFIG. 7A. Moreover, the insulating layer132and the initial intermediate dielectric layer133′ have been formed in the cell trench12, the initial intermediate dielectric layer133′ covering the surface11S of the epitaxial layer11, two opposite inner sidewall surfaces132aand the bottom surface132bof the insulating layer132.

In the present embodiment, the initial intermediate dielectric layer133′ does not vary in thickness along the depth direction of the cell trench12. In other words, the initial intermediate dielectric layer133′ has substantially the same thickness at the portion on the epitaxial layer11and another portions located in the bottom of the cell trench12.

Subsequently, as shown inFIG. 8A, the portion of the initial intermediate dielectric layer133′ covering the bottom surface132bof the insulating layer132is removed to form the intermediate dielectric layer133having the bottom opening133h. Meanwhile, the portion of the initial intermediate dielectric layer133′ disposed on the epitaxial layer11is removed.

In one embodiment, the portions of the initial intermediate dielectric layer133′ respectively disposed on the epitaxial layer11and covering the bottom surface132bof the insulating layer132are removed by performing a dry etching process. It is noting that since the dry etching process is an anisotropic etching process, in which the etching rate in the downward direction is far faster than that in the lateral direction, it ensures that the portions of the initial intermediate dielectric layer133′ which respectively cover the two inner sidewall surfaces132aof the insulating layer132can be left after the dry etching step, thereby forming the intermediate dielectric layer133having the bottom opening133h.

The intermediate dielectric layer133of the present embodiment, includes the first wall portion133aand the second wall portion133b, the first wall portion133aand the second wall portion133brespectively covering two opposite inner sidewall surfaces132a. Moreover, the bottom end of the first wall portion133aand the bottom end of the second wall portion133bare separated from each other so as to form the bottom opening133h.

It is worth noting that after the portion of the initial intermediate dielectric layer133′ which covers the bottom surface132bof the insulating layer132is removed by the dry etching process, the bottom portion of the insulating layer132that is located at the bottom of the cell trench12is further removed to expose the bottom surface of the cell trench12in the present embodiment.

Please refer toFIG. 8B. Next, the initial inner dielectric layer134′ is formed on the epitaxial layer11and in the cell trench12. The initial inner dielectric layer134′ fills the bottom opening133hof the intermediate dielectric layer133and covers the bottom surface of the cell trench12. The material of the initial inner dielectric layer134′ is different from that of the intermediate dielectric layer133, but the same as that of the insulating layer132.

Please refer toFIG. 8C. After the heavily doped semiconductor material130′ is formed in the lower half part of the cell trench12, portions of the initial inner dielectric layer134′ located on the epitaxial layer11and in the upper half part of the cell trench12are removed, in which the initial inner dielectric layer134′ in the lower half part of the cell trench12is left un-etched so as to form the inner dielectric layer134located in the lower half part of the cell trench12. In one embodiment, the abovementioned steps can be carried out by performing a selective etching process.

In the previous steps, the portion of the initial intermediate dielectric layer133′ on the epitaxial layer11has been removed, and the initial inner dielectric layer134′ and the insulating layer132are made of the same material. Accordingly, a portion of the insulating layer132and the portion of initial inner dielectric layer134′ both of which are located on the epitaxial layer11can be removed during the same removing step to expose the surface11S of the epitaxial layer11.

Please refer toFIG. 8D. Next, a thermal oxidation process is performed to oxidize the top portion of the heavily doped semiconductor material130′ so as to form the inter-electrode dielectric layer135. Furthermore, the part of the heavily doped semiconductor material130′ that is left un-oxidized forms the shielding electrode130. During the thermal oxidation process, the surface11S of the epitaxial layer11is oxidized simultaneously and thus forming a thermal oxide layer113.

Please refer toFIG. 8E. The gate electrode131is formed in the cell trench12and disposed above the shielding electrode130so as to form the trench gate structure13. In the present embodiment, after the thermal oxidation process, both of the parts of the first wall portion133aand the second wall portion133blocated in the upper half part of the cell trench12remain un-etched. In this way, the first wall portion133a(of the intermediate dielectric layer133), the second wall portion133btogether with the insulating layer132serve as a gate insulating layer separating the gate electrode131from the epitaxial layer11.

Please refer toFIG. 8F. Next, the base region111and the source region112are formed in the epitaxial layer11. It is worth noting that in the present embodiment, before the step of forming the base region111and the source region112, the thermal oxide layer113that has been formed on the epitaxial layer11can be thinned or completely removed so as to avoid any negative affect on the subsequent base doping process and the source doping process. Subsequently, the redistribution layer can be formed on the epitaxial layer11to form the trench power semiconductor component as shown inFIG. 2.

Please refer toFIGS. 9A to 9C, which are partial sectional schematic views respectively illustrating each step of manufacturing a trench power semiconductor component according to yet another embodiment of the present disclosure.

It should be noting that after performing the thermal oxidation process (the step S304shown inFIG. 6), the surface11S of the epitaxial layer11is also oxidized to form the thermal oxide layer113. If the thermal oxide layer113located at the opening end of the cell trench12is too thick, the opening of the cell trench12will be covered by the thermal oxide layer113, which may cause the gate electrode131to be difficultly formed in the cell trench12.

To solve the above-mentioned problem, in the embodiment shown inFIG. 9A, a thicker initial epitaxial layer11′ and a deeper initial cell trench12″ formed therein are first formed on the substrate. In one embodiment, the thickness of the initial epitaxial11is greater than that of the epitaxial layer11shown inFIG. 7AorFIG. 8Aby 0.5 μm.

Furthermore, after the thermal oxidation process is performed, the step of forming the trench gate structure further includes: removing the thermal oxide layer113disposed on the initial epitaxial layer11′ and a surface layer11L of the initial epitaxial layer11′.

In one embodiment, by performing a chemical mechanical planarization (CMP), the thermal oxide layer113disposed on the initial epitaxial layer11′ and a surface layer11L of the initial epitaxial layer11′ can be removed.

Please refer toFIG. 9B. The portions of the first and second wall portions133a,133blocated in the upper half part of the cell trench12can be removed by performing a selective etching step. Next, a dielectric layer136can be optionally formed to cover the surface11S of the epitaxial layer11and the inner sidewall surfaces132aof the insulating layer132. The dielectric layer136can be an oxide layer or a nitride layer. Referring toFIG. 9C, the gate electrode131is formed in the cell trench12to form the trench gate structure13. Subsequently, the base region111, the source region112and redistribution layer are sequentially formed.

In another embodiment, the gate electrode131is formed in the cell trench12under the situation that the portions of the first and second wall portions133a,133blocated in the upper half part of the cell trench12remain un-etched. In this case, the first wall portion133a, the second wall portion133btogether with the insulating layer132serve as a gate insulating layer so as to optimize the work function difference between the gate electrode131and the base region111, thereby reducing the leakage current during the operation of the trench power semiconductor component.

Please refer toFIG. 10AandFIG. 10B. In the present embodiment, the cell trench12′ has an open-end portion12aand a body portion12bconnected thereto. The inner surface of the open-end portion12ais a slope extending from the surface11S of the epitaxial layer11towards the body portion12b. More specifically, the width of the open-end portion12adecreases from the surface11S of the epitaxial layer11along the depth direction of the trench12′.

In this way, the cell trench12′ will not be covered by the thermal oxide layer113that is formed at the open-end portion12aof the cell trench12′ during the thermal oxidation process for forming the inter-electrode dielectric layer135.

Please refer toFIG. 10B. Next, the gate electrode131is formed in the cell trench12′, and then the base region111and the source region112are formed in the epitaxial layer11.

Specifically, after the gate electrode131is formed in the cell trench12′, the thermal oxide layer113formed on the epitaxial layer11and at the open-end portion12ais removed to expose the surface11S of the epitaxial layer11. The thermal oxide layer113can be removed by a wet etching process. Subsequently, the base doping process, the source doping process and the drive-in process are performed to form the base region111and the source region112in the epitaxial layer11, the source region112being located above the base region111.

Since the inner surface of the open-end portion12ais the slope, the doped regions formed by the base region doping process and the source region doping process will have a dopant profile that differs from that in the previous embodiments. More specifically, the lower edge of the base region111and that of the source region112incline downward as the slope incline towards the center of the trench gate structure.

Furthermore, in another embodiment, the inner dielectric layer134and the intermediate dielectric layer133can be formed by different steps. Please refer toFIGS. 11A to 11D, which are subsequent to the step shown inFIG. 7Aand respectively illustrate the detailed steps of forming the inner dielectric layer134and the intermediate dielectric layer133.

That is to say, before the step shown inFIG. 11A, the insulating layer132and the initial intermediate dielectric layer133′ have been formed in the cell trench12, in which the initial intermediate dielectric layer133′ covering the surface11S of the epitaxial layer11, two inner sidewall surfaces132aand the bottom surface132bof the insulating layer132.

Subsequently, as shown inFIG. 11A, the first dielectric layer134′ais formed to cover the surface of the initial intermediate dielectric layer133′. The part of the first dielectric layer134′alocated on the epitaxial layer11has a thickness greater than that of another parts located at the bottom of the cell trench12.

Next, referring toFIG. 11B, a part of the first dielectric layer134′aand a part of the initial intermediate dielectric layer133′, which are located at the bottom of the cell trench12, are removed so as to form the first dielectric layer134a having a bottom-side opening and the intermediate dielectric layer133having the bottom opening. In the present embodiment, the bottom portion of the insulating layer132located at the bottom of the cell trench12can be remained. The aforementioned steps can be carried out by performing a dry etching process.

Next, as shown inFIG. 11C, a second dielectric layer134bis formed to fill the bottom-end opening of the first dielectric layer134aand the bottom opening of the intermediate dielectric layer. Accordingly, the bottom portion of the second dielectric layer134bconnects the bottom surface132bof the insulating layer132. Furthermore, in the present embodiment, the first dielectric layer134a, the second dielectric layer134b, and the insulating layer132are made of the same material, such as silicon oxide.

Please refer toFIG. 11D. After the formation of the heavily doped semiconductor material130′ located in the lower half part of the cell trench12, an upper half portion of the first dielectric layer134aand an upper half portion of the second dielectric layer134bare removed, in which another parts of the first dielectric layer134aand the second dielectric layer134blocated in the lower half part of the cell trench12are left un-etched.

The detailed steps of forming the heavily doped semiconductor material130′ have been explained in the aforementioned paragraphs relative toFIG. 7Dand thus being omitted herein. It is noting that the first dielectric layer134atogether with the second dielectric layer134blocated in the lower half part of the cell trench12commonly form the inner dielectric layer134.

Furthermore, the first and second wall portions133a,133bof the intermediate dielectric layer113formed by the aforementioned steps respective have two bending portions R1, R2, the bending portions R1, R2extending from one toward the other of the inner sidewall surfaces132aand being opposite to each other. However, the two bending portions R1, R2are spaced apart from each other to form the bottom opening. Therefore, the two bending portions R1, R2do not extending toward a region beneath the shielding electrode130, and then overlap the shielding electrode130in the depth direction of the cell trench12.

Subsequently, the step of forming the inter-electrode dielectric layer135is performed and followed by the steps of forming the gate electrode131, the base region111, and the source region112.

Please refer toFIGS. 12A to 12C, which is subsequent to the step shown inFIG. 11A. As shown inFIG. 12A, after the formation of the first dielectric layer134a, the portion of the first dielectric layer134a, the portion of the initial intermediate dielectric layer133′ the bottom portion of the insulating layer132, which are located at the bottom of the cell trench12, are removed during the same etching process so as to expose the bottom surface of the cell trench12.

Please refer toFIG. 12B. Next, the second dielectric layer134bis formed so as to fill the bottom-end opening of the first dielectric layer134aand the bottom opening of the intermediate dielectric layer133and to cover the bottom surface of the cell trench12. Accordingly, the second dielectric layer134bcan be in contact with the bottom surface of the cell trench12.

Next, as shown inFIG. 12C, after the heavily doped semiconductor material130′ is formed in the lower half part of the cell trench12, the portions of the first and second dielectric layers134a,134blocated in the upper half part of the cell trench12are both removed.

Similar to the embodiment shown inFIG. 11D, in the present embodiment, the first and second dielectric layers134a,134blocated in the lower half part of the cell trench12commonly form the inner dielectric layer134.

In summary, the present disclosure provides the trench power semiconductor components T1, T1′, T2, T2′, T3and the method of manufacturing the same, in which the intermediate dielectric layer133and the inner dielectric layer134which are made of different materials surround the shielding electrode130, the intermediate dielectric layer133being interposed between the inner dielectric layer134and the insulating layer132. The intermediate dielectric layer133has the bottom opening133hlocated at the bottom side thereof, and the inner dielectric layer134fills the bottom opening133h. In this way, when the trench power semiconductor components T1, T1′, T2, T2′, T3are operated under a reverse bias, the bottom of the cell trench12will have a loose distribution of electric field due to the same material beneath the shielding electrode130, thereby increasing the breakdown voltage without adversely affecting the on-resistance.

When the breakdown voltage is increased, the doping concentration of the drift region110can be further optimized so as to reduce the on-resistance, thereby enhancing the switching efficiency of the trench power semiconductor components T1, T1′, T2, T2′, T3. Based on simulations, it has been proven that the trench power semiconductor components T1, T1′, T2, T2′, T3according to the embodiments of the present disclosure have smaller distribution densities and thus higher breakdown voltages. Therefore, the trench power semiconductor components T1, T1′, T2, T2′, T3according to the embodiments of the present disclosure can decrease the on-resistance by 50%.

Furthermore, in the trench power semiconductor component T1′ of the present disclosure, by using the insulating layer132together with the intermediate dielectric layer133which are respectively made of two different materials to function as the gate insulating layer, the work function difference between the gate electrode131and the base region111can be optimized, thereby reducing the leakage current when the trench power semiconductor component T1′ is operated in a reverse bias.

Furthermore, the method of manufacturing a trench power semiconductor component of the present disclosure can be integrated into the current semiconductor fabrication process so as to provide the trench power semiconductor components T1, T1′, T2, T2′, T3of the present disclosure.