Metal shield structures in backside illumination image sensor chips

A device includes a semiconductor substrate having a front side and a backside. An active image sensor pixel array is disposed on the front side of the semiconductor substrate. A metal shield is disposed on the backside of, and overlying, the semiconductor substrate. The metal shield has an edge facing the active image sensor pixel array. The metal shield has a middle width, and a top width greater than the middle width.

BACKGROUND

Backside Illumination (BSI) image sensor chips are replacing front-side illumination sensor chips for their higher efficiency in capturing photons. In the formation of the BSI image sensor chips, image sensors, such as photo diodes, and logic circuits are formed on a silicon substrate of a wafer, followed by the formation of an interconnect structure on a front side of the silicon chip.

The image sensors in the BSI image sensor chips generate electrical signals in response to the stimulation of photons. The magnitudes of the electrical signals (such as the currents) depend on the intensity of the incident light received by the respective image sensors. To achieve increased quantum efficiency of image sensors, it is desirable that more light is received by the image sensors.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A metal shield structure in a Backside Illumination (BSI) image sensor chip and the methods of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the metal shield structure are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIGS. 1 through 4illustrate the cross-sectional views of intermediate stages in the manufacturing of a metal shield in accordance with some exemplary embodiments.FIG. 1illustrates image sensor chip20, which may be a part of an un-sawed wafer22. Image sensor chip20includes semiconductor substrate26. Semiconductor substrate26may be a crystalline silicon substrate or a semiconductor substrate formed of other semiconductor materials. Throughout the description, surface26A is referred to a front surface of semiconductor substrate26, and surface26B is referred to as a back surface of semiconductor substrate26. Image sensors24(including24A and24B) are formed at surface26A of semiconductor substrate26. Image sensors24are configured to convert light signals (photons) to electrical signals, and may be photo-sensitive Metal-Oxide-Semiconductor (MOS) transistors or photo-sensitive diodes. Accordingly, the respective wafer22may be an image sensor wafer. The structures of image sensors24A and24B may be identical to each other.

Front-side interconnect structure28is formed on the front side of semiconductor substrate26, and is used to electrically interconnect the devices in image sensor chip20. Front-side interconnect structure28includes dielectric layers30, and metal lines32and vias34in dielectric layers30. Throughout the description, the metal lines32in a same dielectric layer30are collectively referred to as being a metal layer, and front-side interconnect structure28may include a plurality of metal layers. In some exemplary embodiments, dielectric layers30include low-k dielectric layers and passivation layers. The low-k dielectric layers have low k values, for example, lower than about 3.0. The passivation layers may be formed of non-low-k dielectric materials having k values greater than 3.9. In some embodiments, the passivation layers include a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.

Image sensor chip20includes active image sensor pixel region100and shielded region200. Active image sensor pixel region100includes active image sensors24A formed therein, which are used for generating electrical signals from the sensed light. Image sensors24A may form an active image sensor pixel array, which includes a plurality of image sensors arranged as rows and columns. Shielded region200includes black reference image sensors, which are illustrated as24B, formed therein. Black reference image sensors24B are used for generating reference black level signals for calibrating the signals of active image sensors24A. Furthermore, shielded region200may include logic devices (also illustrated as24B), which include Complementary MOS (CMOS) transistors. The logic devices may be used, for example, to process the electrical signals generated by the image sensors.

A backside grinding is performed to thin semiconductor substrate26, and the thickness of wafer22is reduced to smaller than about 30 μm, or smaller than about 5 μm, for example. With semiconductor substrate26having a small thickness, light can penetrate from back surface26B into semiconductor substrate26, and reach image sensors24A.

After the step of thinning, buffer layers40are formed on the back surface of semiconductor substrate26. In some exemplary embodiments, buffer layers40include Bottom Anti-Reflective Coating (BARC)36, and silicon oxide layer38over BARC layer36. It is appreciated that buffer layers40may have different structures, formed of different materials, and may have different number of layers other than illustrated. In some embodiments, silicon oxide layer38is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD), and hence is referred to as Plasma Enhanced (PE) oxide layer38.

Metal layer42is formed over buffer layers40. In some embodiments, the metal (or metals) in metal layer42include tungsten, aluminum, copper, and/or the like. For example, metal layer42may be formed of aluminum copper. The thickness of metal layer42may be greater than about 2 kÅ, and may be between about 2 kÅ and about 14 kÅ, for example. It is appreciated that the dimensions recited throughout the description are merely examples, and may be changed to different values. Photo resist44is formed over metal layer42, and is then patterned.

The patterned photo resist44is used as an etching mask to etch through metal layer42. Referring toFIG. 2, the remaining portions of metal layer42forms a metal grid in active image sensor pixel region100and metal shield48in shielded region200. The metal grid includes metal grid lines46. In some embodiments, as illustrated, metal grid lines46and metal shield48are formed using the same material, and are formed simultaneously. In alternative embodiments, grid lines46and metal shield48may be formed using different processes, and may comprise different materials. As shown inFIG. 9, metal grid lines46include a first plurality of grid lines parallel to each other, and a second plurality of grid lines parallel to each other. The first plurality of grid lines is perpendicular to the second plurality of grid lines46to form the grids. Grid openings47are formed between grid lines46. Each of grid openings47may be over and aligned to one of active image sensors24A.

Referring back toFIG. 2, metal shield48is formed over and aligned to devices24B, which may include the black reference image sensors and/or the logic devices. Metal shield48is sometimes referred to as an optical shield, which is used to prevent light from being received by devices24B.

In some embodiments, metal layer42comprises aluminum copper. The etching of metal layer42may be performed using chlorine (Cl2) and boron chloride (BCl3) as process gases. The flow rate of BCl3(denoted as F(BCl3) hereinafter) may be relatively high to incur more physical etching, and the flow rate of Cl2(denoted as F(Cl2) hereinafter) may be relatively low to incur less chemical etching. In some embodiments, the flow rate ratio F(Cl2)/F(BCl3) is in the range between about 1/1 and about 1/10, or in the rage between about 1/5 and about 1/10. In alternative embodiments, flow rate ratio F(Cl2)/F(BCl3) may be higher. During the etching process, plasma is generated from the process gases. It is realized that the optimum etching conditions are related to the composition (such as the elements and the percentage of the elements) of metal layer42. Depending on the process conditions and the composition of metal layer42, the flow rate ratio F(Cl2)/F(BCl3) may also be adjusted further to optimize the etch process.

As a result of the adjusted flow rate ratio and possibly some other optimized etching conditions, metal shield48may have a reversed trapezoid shape, wherein bottom width W1is smaller than top width W2. Furthermore, bottom width W1may also be smaller than middle width W3, which is measured at a middle level of metal layer42. In some embodiments, edges48A of metal shield48are substantially straight and tilted. Accordingly, the lower portions of edges48A are recessed from the respective upper portions. The tilt angle α of sidewalls48A is smaller than 90 degrees, and may be smaller than about 85 degrees. Furthermore, tilt angle α may be between about 45 degrees and about 80 degrees. Edges48A include inner edge48A1that faces active image sensor pixel region100and grid lines46. Edges48A also include outer edge48A2that is opposite inner edge48A1. When grid lines46and metal shield48are formed simultaneously, the profiles of the edges of grid lines46may be similar to the profile of edges48A. For example, edges of grid lines46may have tilt angles that are close to tilt angle α.

InFIG. 3, photo resist44is removed. Next, as shown inFIG. 4, dielectric layers50are formed. Dielectric layers50may include an oxide layer, which may be a silicon oxide layer formed using PECVD, for example. Dielectric layers50may further include a silicon nitride layer over the oxide layer. In some embodiments, a planarization step such as a Chemical Mechanical Polish (CMP) is performed to level the top surface of oxide layers50. In subsequent process steps, as also shown inFIG. 4, additional components such as color filters52and micro-lenses54are formed, with each of color filters52and micro-lenses54aligned to one of active image sensors24A.

When light56is projected to BSI image sensor chip20from the backside of substrate26, light56is received by active image sensors24A. The reverse trapezoid shape of metal shield48is used to collect more light for image sensors24A. For sample, with edge48A1facing image sensor pixel region100, light ray56A, which is tilted, is not blocked by metal shield48. The intensity of the light received by image sensors24A is thus increased.

FIG. 9illustrates a top view of regions100and200, wherein metal shield48is formed in shielded region200, and may form a ring encircling region100and grid lines46in some embodiments. The cross-sectional view shown inFIG. 4may be obtained from the plane crossing line4/8-4/8inFIG. 9.

FIGS. 5 through 8illustrate cross-sectional views of intermediate stages in the formation of a metal shield in accordance with alternative embodiments. Unless specified otherwise, the materials and formation methods of the components in these embodiments are essentially the same as the like components, which are denoted by like reference numerals in the embodiments shown inFIGS. 1 through 4. The details of the like components shown inFIGS. 5 through 8may thus be found in the discussion of the embodiments shown inFIGS. 1 through 4.

The initial steps of these embodiments are essentially the same as shown inFIG. 1. After the structure as inFIG. 1is formed, metal layer42is etched, and the resulting structure is shown inFIG. 5. In some embodiments, the etching of metal layer42is performed using Cl2and BCl3as process gases. During the etch step, plasma is generated from the process gases. In some embodiments, the flow rate ratio F(Cl2)/F(BCl3) may be lower than about 1/1, for example, although a higher flow rate ratio may also be used. Depending on the composition of metal layer42, the flow rate ratio F(Cl2)/F(BCl3) may also be adjusted to have different values. The resulting metal shield48may have a trapezoid shape, wherein the bottom width of metal shield48is greater than the respective top width. Alternatively, metal shield48may have substantially vertical edges48A (schematically illustrated using dashed lines), and the bottom width of metal shield48is substantially equal to the top width of metal shield48. Edges48A of metal shield48may be substantially straight.

During the etching of metal layer42, the end point is monitored to determine when metal layer42is etched through. At a time metal layer42is already etched through, metal shield48may have the edge profile similar to what is shown inFIG. 5. When the end point is detected, wherein metal layer42is etched through, and the underlying layer is exposed, the etching step is continued, and an over-etch is performed. In some embodiments, the over-etch is performed using. In some embodiments, the over-etch may have the duration between about 5 seconds and about 15 seconds, depending on thickness T1of metal layer42shield48.

The resulting profile of metal shield48is related to the duration of the over-etch. Referring toFIG. 6, the over-etch is performed long enough to result in edges48A of metal shield48to have a concave arc profile. With the concave arc profile, the middle portions of metal shield48are recessed more than the top and bottom portions of metal shield48. Furthermore, the middle portions of edges48A are recessed from the respective top portions and bottom portions. Middle width W3of metal shield48is smaller than bottom width W1and top width W2. Edges48A may also include smoothly transitioned arc portions. In some embodiments, width difference (W1−W3) is greater than about 0.25*T1, wherein T1is the thickness of metal shield48. Width difference (W1−W3) may also be greater than about 1 kÅ, for example, when thickness T1is about 4 kÅ. Width difference (W1−W3) may also be greater than about 0.25*T1. Width difference (W1−W3) may also be greater than about 1 kÅ, for example, when thickness T1is about 4 kÅ. Width difference (W1−W3) may also be greater than about 2 kÅ. Furthermore, top width W2may also be smaller than width W1, with both widths W1and W2being greater than width W3. Width difference (W2−W3) may also be greater than about 1 kÅ or 2 kÅ.

In accordance with alternative embodiments, after the etching step as shown inFIG. 5is performed, and the end point is detected, an over-etch is performed using process conditions that are different from the process conditions for etching through metal layer42. In some exemplary embodiments, during the over-etch, the plasma is turned off. The flow of BCl3is substantially turned off. Cl2is still used to further etch metal shield48. In some embodiments, during the over-etch, the etching temperature may be between about 55° C. and about 75° C., the flow rate of Cl2may be between about 60 sccm and about 270 sccm. The duration of the over-etch may be between about 5 seconds and about 20 seconds. In the embodiments shown inFIG. 6, since grid lines46and metal shield48are formed simultaneously, the edges of grid lines46may also have concave arc profiles.

Referring toFIG. 7, photo resist44is removed, for example, through an ashing process. Next, as shown inFIG. 8, dielectric layers50, color filters52, and micro-lenses54are formed. Each of color filters52and micro-lenses54is aligned to one of active image sensors24A. The top views of regions100and200, grid lines46, and metal shield48is also illustrated inFIG. 9, wherein the cross-sectional view shown inFIG. 8is obtained from the plane crossing line4/8-4/8inFIG. 9.

Referring back toFIG. 8, when light56is projected to BSI image sensor chip20, light56is received by active image sensors24A from the backside of substrate26. The concave arc shape of metal shield48is used to reflect more light to active image sensors24A. For sample, edge48A1, which is the edge of metal shield48facing image sensor pixel region100, may reflect light ray56A to image sensors24A. The intensity of the light received by active image sensors24A is thus increased.

In accordance with embodiments, a device includes a semiconductor substrate having a front side and a backside. An active image sensor pixel array is disposed on the front side of the semiconductor substrate. A metal shield is disposed on the backside of, and overlying, the semiconductor substrate. The metal shield has an edge facing the active image sensor pixel array. The metal shield has a middle width, and a top width greater than the middle width.

In accordance with other embodiments, a device includes a semiconductor substrate having a front side and a backside, a metal grid on the backside of the semiconductor substrate, and a plurality of photo-sensitive devices underlying and aligned to grid openings of the metal grid. The plurality of photo-sensitive devices is at the front side of the semiconductor substrate, and is configured to receive light from the backside of the semiconductor substrate and convert the light to electrical signals. A metal shield is disposed on the backside of, and overlying, the semiconductor substrate. The metal shield forms a ring encircling the metal grid, and an inner edge of the metal shield facing the metal grid is tilted, with a middle portion of the edge recessed from a respective top portion.

In accordance with yet other embodiments, a method includes forming a plurality of photo-sensitive devices on a front side of a semiconductor substrate, and forming a metal layer on a backside of the semiconductor substrate. The metal layer is over the semiconductor substrate. The method further includes etching the metal layer to form a metal shield that has an edge facing the active image sensor pixel array, wherein the metal shield has a middle width, and a top width greater than the middle width.