IMAGE FORMING SYSTEM FOR SUPPLYING VOLTAGE TO IMAGE FORMING APPARATUS EVEN WHEN DC-DC CONVERTER ON MAIN BOARD FAILS

An image forming system includes an image forming apparatus including an AC-DC converter and a main board, and a sub board having a sub connector connectable with a main connector of the main board. When the sub board is not connected with the main board, a main DC-DC converter on the main board converts a DC voltage from the AC-DC converter into a first DC voltage and output the first DC voltage to a circuit element for image formation. When the sub board is connected with the main board, the AC-DC converter outputs the DC voltage to a sub DC-DC converter on the sub board via the main connector and the sub connector, and the sub DC-DC converter converts the DC voltage from the AC-DC converter into a second DC voltage and output the second DC voltage to the circuit element via the sub connector and the main connector.

REFERENCE TO RELATED APPLICATIONS

This application claims priority from Japanese Patent Application No. 2023-056311 filed on Mar. 30, 2023. The entire content of the priority application is incorporated herein by reference.

BACKGROUND ART

An image forming apparatus has been known that includes a low-voltage power supply board, and a main board with a DC-DC converter and a main control circuit mounted thereon. In the known image forming apparatus, the low-voltage power supply board is configured to convert an AC voltage supplied from a commercial power supply into a 24 V DC and output the 24 V DC to the main board. It is noted that “AC” is an abbreviation for “alternating-current” and that “DC” is an abbreviation for “direct-current.” The DC-DC converter on the main board is configured to convert the 24 V DC from the low-voltage power supply board into a 3.3 V DC and supply the 3.3 V DC to the main control circuit.

SUMMARY

However, in the known image forming apparatus, when the DC-DC converter fails, the main board has to be replaced, which is accompanied by a high level of operational difficulty because there are many harnesses to be disconnected from the currently attached main board and connected with a new main board. In addition, there is concern that the disconnection/connection of the harnesses may cause other malfunctions as side effects, thus resulting in high hurdles for replacing the main board.

Aspects of the present disclosure are advantageous for providing one or more improved techniques that make it possible to supply voltage to an image forming apparatus without replacing a main board when a DC-DC converter on the main board fails.

According to aspects of the present disclosure, an image forming system is provided, which includes an image forming apparatus and a sub board. The image forming apparatus is configured to form an image on a sheet. The sub board is connectable with the image forming apparatus. The image forming apparatus includes an AC-DC converter configured to convert an alternating-current (AC) voltage from a power supply into a direct-current (DC) voltage. The image forming apparatus further includes a main board that includes a circuit element for image formation, a main DC-DC converter, and a main connector. The main DC-DC converter is configured to convert the DC voltage from the AC-DC converter into a first DC voltage for driving the circuit element. The sub board includes a sub DC-DC converter configured to convert the DC voltage from the AC-DC converter into a second DC voltage for driving the circuit element. The sub board further includes a sub connector configured to connect with the main board via the main connector. The main board is configured to switch to which of the main DC-DC converter and the sub DC-DC converter the DC voltage from the AC-DC converter is to be output, depending on whether the sub board is connected with the main board via the sub connector and the main connector. The main board is further configured to, when the sub board is not connected with the main board via the sub connector and the main connector, input the DC voltage from the AC-DC converter into the main DC-DC converter, and input the first DC voltage from the main DC-DC converter into the circuit element. The main board is further configured to, when the sub board is connected with the main board via the sub connector and the main connector, output the DC voltage from the AC-DC converter to the sub DC-DC converter via the main connector and the sub connector, thereby causing the sub DC-DC converter to output the second DC voltage to the circuit element via the sub connector and the main connector.

DESCRIPTION

Hereinafter, an illustrative embodiment according to aspects of the present disclosure will be described with reference to the accompanying drawings.

FIG.1is a cross-sectional side view schematically showing a configuration of a color laser printer1in an illustrative embodiment according to aspects of the present disclosure. The color laser printer1may be an example of an “image forming apparatus” according to aspects of the present disclosure. Hereinafter, the color laser printer1may be simply referred to as the printer1. The printer1includes an apparatus housing2, a conveyor3, an image forming engine4, and a fuser9. In the following description, for the sake of explanatory convenience, vertical directions (i.e., an upward direction and a downward direction) and front-rear directions (i.e., a frontward direction and a rearward direction) of the printer1are defined as indicated by arrows inFIG.1. In addition, a front side (i.e., a near side) and a back side (i.e., a far side) with respect to an image-drawn surface ofFIG.1are defined as a right side and a left side of the printer1, respectively. It is noted that hereinafter, one of the vertical directions (i.e., the upward direction and the downward direction) may be referred to as the “vertical direction” as a representative of the upward and downward directions when both of the upward and downward directions are acceptable, for the sake of explanatory simplicity. Likewise, one of the front-rear directions (i.e., the frontward direction and the rearward direction) may be referred to as the “front-rear direction.” Further, one of the left-right directions (i.e., the leftward direction and the rightward direction) may be referred to as the “left-right direction.”

The apparatus housing2has a front cover21, a rear cover12, a feed tray31, a discharge tray22, and first to third conveyance paths25to27. The front cover21is configured to open and close a front opening2A formed at a front portion of the apparatus housing2. The front cover21is attached to a front face of the apparatus housing2in an openable and closeable state. The rear cover12is configured to open and close a rear opening2B formed at a rear portion of the apparatus housing2. The rear cover12is attached to a rear face of the apparatus housing2in an openable and closeable state. The feed tray31is removably attached to a lower portion of the apparatus housing2. The feed tray31is configured to support sheets S placed thereon. The sheets S are fixed-size (e.g., A4-size) sheets. Examples of the sheets S may include, but are not limited to, paper media (e.g., plain paper and cardboard) and transparencies (e.g., OHP films). The discharge tray22is disposed at an upper portion of the apparatus housing2. The discharge tray22is configured to receive discharged sheets S with images formed thereon.

The conveyor3includes a pick-up roller33, a separation roller34, a registration roller35, a first conveyance roller36, a second conveyance roller37, a first switchback roller38, a second switchback roller39, a plurality of third conveyance rollers40, a flapper30and a main motor106(seeFIG.2). A part of the second conveyance path26is formed by the closed rear cover12.

The pick-up roller33is configured to pick up sheets S that are in the feed tray31and pushed upward by a sheet pressing plate32and to convey the picked-up sheets S toward the first conveyance path25. The separation roller34is configured to separate the sheets S picked up by the pick-up roller33on a sheet-by-sheet basis.

The registration roller35is disposed upstream of the image forming engine4in a conveyance direction, along the first conveyance path25. The registration roller35is configured to perform s skew correction for a sheet S and then convey the sheet S toward the image forming engine4. The conveyance direction in which the registration roller35conveys the sheet S is a direction from front to back.

With the rear cover12closed when the sheet S is conveyed out of the apparatus housing2, the conveyor3conveys the sheet S fed from the image forming engine4, by the first conveyance roller36, and guides the sheet S to the first conveyance path25by the flapper30(30A). Afterward, the conveyor3conveys the sheet S guided to the first conveyance path25, by the second conveyance roller37and the first switchback roller38, and discharges the sheet S onto the discharge tray22.

With the rear cover12opened when the sheet S is conveyed out of the apparatus housing2, the conveyor3conveys the sheet S fed from the image forming engine4, by the first conveyance roller36, guides the sheet S rearward by the flapper30(30B) that has swung to a position indicated by an imaginary line, and then discharges the sheet S through the rear opening2B onto the open rear cover12. The printer1is configured to perform image formation on the sheet S even when the rear cover12is open. The rear cover12is configured to, when opened, allow the sheet S with an image formed thereon to be discharged through the rear opening2B.

To convey the sheet S to the image forming engine4again, the conveyor3conveys the sheet S fed from the image forming engine4, by the first conveyance roller36, and guides the sheet S to the first conveyance path25or the second conveyance path26by the flapper30. When the sheet S has been guided to the first conveyance path25, the conveyor3conveys the sheet S in the first conveyance path25to the third conveyance path27by the second conveyance roller37and the first switchback roller38. When the sheet S has been guided to the second conveyance path26, the conveyor3conveys the sheet S in the second conveyance path26to the third conveyance path27by the second switchback roller39.

The sheet S conveyed to the third conveyance path27is again fed to the image forming engine4by the third conveyance roller40and the registration roller35. Then, the sheet S, after an image has been formed thereon by the image forming engine4, is discharged onto the discharge tray22by the conveyor3.

The image forming engine4is configured to form an image on the sheet S by transferring a toner image onto the sheet S. The image forming engine4includes an exposure unit5, a drum unit6, four developing cartridges7Y,7M,7C, and7K, and a transfer unit8.

The exposure unit5is disposed at an upper section in the apparatus housing2. The exposure unit5includes a light source, a polygon mirror, lenses, and a reflector, which are not shown in any drawings. The exposure unit5is configured to expose surfaces of photoconductive drums61by emitting a light beam, indicated by an alternate long and short dash line, onto the surface of each photoconductive drum61.

The drum unit6is disposed between the feed tray31and the exposure unit5in the apparatus housing2. The drum unit6includes the four photoconductive drums61, four chargers62, a pinch roller64, and a support frame65configured to support the photoconductive drums61. The drum unit6is configured to be attached to and removed from the apparatus housing2through the front opening2A in a state where the front cover11is open. The pinch roller64is disposed to face the registration roller35. The pinch roller64is configured to rotate in accordance with the rotation of the registration roller35and convey the sheet S together with the registration roller35.

The developing cartridges7Y,7M,7C, and7K correspond to the four colors yellow (Y), magenta (M), cyan (C), and black (K), respectively. The developing cartridges7Y,7M,7C, and7K are removably attached to the drum unit6and arranged in this order from the front to the rear of the printer1. Each of the developing cartridges7Y,7M,7C, and7K includes a developing roller71, a supply roller72, and a toner container73. The developing cartridges7Y,7M,7C, and7K have different toner colors but have substantially the same configuration other than the toner colors. Therefore, one of the developing cartridges7Y,7M,7C, and7K may hereinafter be referred to as the “developing cartridge7” as a representative of the developing cartridges7Y,7M,7C, and7K.

The transfer unit8is disposed between the feed tray31and the drum unit6in the apparatus housing2. The transfer unit8includes a driving roller81, a driven roller82, a conveyor belt83, and four transfer rollers84. The conveyor belt83is wound around the driving roller81and the driven roller82. An upward-facing surface of the conveyor belt83is in contact with the photoconductive drums61. The four transfer rollers84are disposed within a portion surrounded by the conveyor belt83in such a manner as to sandwich the conveyor belt83between each transfer roller84itself and a corresponding photoconductive drum61.

The fuser9is disposed rearward of the image forming engine4in the apparatus housing2. Specifically, the fuser9is located between the rear cover12in the closed state and the image forming engine4. The fuser9has a heating roller91and a pressurizing device92. The heating roller91is configured to heat the sheet S. The pressurizing device92is configured to sandwich the sheet S between the pressurizing device92itself and the heating roller91. In the illustrative embodiment, the heating roller91includes therein one or more heaters93configured to heat the heating roller91. The pressurizing device92includes an endless belt, a pressure pad, a holder, and a belt guide, which are shown with no reference numerals assigned. The pressure pad is configured to sandwich the endless belt between the pressure pad itself and the heating roller91. The holder is configured to support the pressure pad.

The image forming engine4is configured to uniformly charge the surface of each photoconductive drum61by a corresponding charger62and expose the surface of each photoconductive drum61by the exposure unit5, thereby forming an electrostatic latent image on the surface of each photoconductive drum61. The image forming engine4supplies toner stored in each toner container73to a corresponding supply roller72, thereby supplying the toner from the supply roller72to a corresponding developing roller71. The toner supplied to the developing roller71is carried on the developing roller71as the developing roller71rotates.

The image forming engine4supplies the electrostatic latent image formed on each photoconductive drum61with the toner carried on the corresponding developing roller71, thereby forming a toner image on the surface of each photoconductive drum61. Then, the image forming engine4transfers the toner image on each photoconductive drum61onto the sheet S as the conveyor3conveys the sheet S fed from the feed tray31between each photoconductive drum61and the conveyor belt83. Thereafter, the sheet S with the toner images transferred thereon is conveyed from the image forming engine4to the fuser9by the image forming engine4and the conveyor3.

The fuser9forms an image on the sheet S by fixing the transferred toner images onto the sheet S while conveying the sheet S between the heating roller91and the pressurizing device92.

The printer1further includes a fixing fan13and a fuser temperature sensor TH2in the apparatus housing2.

The fixing fan13is configured to, when driven, discharge air in the apparatus housing2out of the apparatus housing2.

The fuser temperature sensor TH2is configured to output a signal according to a temperature of the fuser9(more specifically, a temperature of the heating roller91). The fuser temperature sensor TH2is disposed at the fuser9and opposed to the heating roller91in a non-contact state. Practicable examples of the fuser temperature sensor TH2may include, but are not limited to, a non-contact thermistor.

Next, a control configuration of the printer1will be described with reference to FIG.2. As shown inFIG.2, the printer1further includes an ASIC105, a ROM102, a RAM103, an NVRAM104, an I/F group110, and a sensor group111. It is noted that “I/F” is an abbreviation for “interface.” The ASIC105, the ROM102, the RAM103, the NVRAM104, the I/F group110, a main DC-DC converter113, a main motor driver MD1, and a process motor driver MD2are mounted on the main board100.

The ASIC105includes a CPU101mounted thereon. The CPU101is configured to perform general control over individual elements included in the printer1. The ASIC105is electrically connected with the ROM102, the RAM103, the NVRAM104, the I/F group110, the sensor group111, the main DC-DC converter113, the main motor driver MID1, the process motor driver MD2, and the fixing fan13.

The ROM102stores various control programs and settings for controlling the printer1.

The RAM103is usable as a work area from which various control programs are read out and as a storage area for temporarily storing image data included in jobs. The CPU101is configured to control each of the elements included in the printer1according to the control programs read out from the ROM102and signals output from various sensors, while storing the processing results in the RAM103or NVRAM104.

The sensor group111includes, for instance, a supply sensor SE1(seeFIG.1), a pre-registration sensor SE2(seeFIG.1), and a post-registration sensor SE3(seeFIG.1).

The supply sensor SE1is disposed upstream of the pick-up roller33in the conveyance direction, along the first conveyance path25. The supply sensor SE1is configured to detect a sheet S passing therethrough. Practicable examples of the supply sensor SE1may include, but are not limited to, a sensor having an actuator swingable when coming into contact with the sheet S, and an optical sensor. Specifically, the supply sensor SE1is configured to output an ON signal when the sheet S is passing through the supply sensor SE1and output an OFF signal when there is no sheet S passing therethrough. The detection signal output from the supply sensor SE1is transmitted to the CPU101.

The pre-registration sensor SE2is disposed upstream of the registration roller35in the conveyance direction, along the first conveyance path25. The pre-registration sensor SE2is configured to detect a sheet S passes therethrough. The pre-registration sensor SE2has substantially the same configuration as the supply sensor SE1. The detection signal output from the pre-registration sensor SE2is transmitted to the CPU101.

The post-registration sensor SE3is disposed upstream of the fuser9in the conveyance direction, along the first conveyance path25, specifically, located between the registration roller35and (the most-upstream one of) the transfer rollers84in the conveyance direction. The post-registration sensor SE3is configured to detect a sheet S passing therethrough. The post-registration sensor SE3has substantially the same configuration as the supply sensor SE1. The detection signal output from the post-registration sensor SE3is transmitted to the CPU101.

The main motor106is connected with the main motor driver MD1. The ASIC105is configured to control the drive of the main motor106by outputting control signals to the main motor driver MD1. The main motor106is configured to drive the heating roller91and the roller group120of the fuser9. The roller group120includes the pick-up roller33, the separation roller34, the registration roller35, the first conveyance roller36, the second conveyance roller37, the first switchback roller38, the second switchback roller39, and the plurality of third conveyance rollers40.

A process motor107is connected with the process motor driver MD2. The ASIC105is further configured to control the drive of the process motor107by outputting control signals to the process motor driver MD2. The process motor107is configured to drive the four developing rollers71and the four photoconductive drums61.

The main DC-DC converter113is connected with an AC-DC power supply board112. The AC-DC power supply board112has an AC-DC converter112A. The AC-DC power supply board112is configured to receive an input of, e.g., 100 V AC supplied from a commercial power supply, convert the 100 V AC into, for instance, a 24 V DC through the AC-DC converter112A, and output the 24 V DC to the main DC-DC converter113. The main DC-DC converter113is configured to convert the 24 V DC output from the AC-DC power supply board112into, for instance, a 3.3 V DC (which may correspond to a “first DC voltage” according to aspects of the present disclosure), and output the 3.3 V DC to the ASIC105, the I/F group110, the sensor group111, the ROM102, the RAM103, and the NVRAM104. The ASIC105, the I/F group110, the sensor group111, the ROM102, the RAM103, and the NVRAM104may correspond to a “circuit element for image formation” according to aspects of the present disclosure.

Thus, the 3.3 V DC, which is the drive voltage for the circuit elements such as the ASIC105, is normally generated by the main DC-DC converter113mounted on the main board100, and is output to the circuit elements such as the ASIC105, as shown inFIG.3A. However, when the main DC-DC converter113fails, the main DC-DC converter113is unable to output the 3.3 V DC. Therefore, in this case, the circuit elements such as the ASIC105stop operating. To deal with this, in the illustrative embodiment, a sub board200with a sub DC-DC converter213mounted thereon is connected with the main board100, and is configured to output a 3.3 V DC (which may correspond to a “second DC voltage” according to aspects of the present disclosure) generated by the sub DC-DC converter213to the circuit elements such as the ASIC105. Thus, a printing system in the illustrative embodiment includes the printer1and the sub board200connectable with the main board100of the printer1.

FIG.3Bshows the main board100connected with the sub board200. In the example shown inFIG.3B, the main DC-DC converter113is out of order. As shown inFIG.3B, the main board100and the sub-board200are connected with each other by connecting a main connector100A on the main board100side and a sub connector200A on the sub board200side via a harness150. The main connector100A and the sub-connector200A may be connected directly without the harness150.

The 24 V DC generated by the AC-DC converter112A is input into the sub DC-DC converter213via the main connector100A, (the harness150), and the sub connector200A. Then, the sub DC-DC converter213converts the 24 V DC to the 3.3 V DC. Thereafter, the 3.3 V DC generated by the sub DC-DC converter213is input into the circuit elements such as the ASIC105via the sub connector200A, (the harness150), and the main connector100A.

FIG.4shows an example of a circuit configuration around the main DC-DC converter113when the sub board200is not connected with the main board100.

As shown inFIG.4, the 24 V DC output from the AC-DC power supply board112is supplied to a power input path L1on the main board100. A first source terminal115S of a first FET115(which may correspond to a “first switching element” according to aspects of the present disclosure) is connected with the power input path L1. A power relay path L2(which may correspond to an “input path” according to aspects of the present disclosure) is formed between a branch point B1on the way to the first FET115on the power input path L1, and a first terminal T1of the main connector100A. In addition, a first gate line L3is formed between a second terminal T2of the main connector100A and a first gate terminal115G of the first FET115. Furthermore, resistors R1and R2are connected in series between the power input path L1and the ground. A connection point CP1between the resistors R1and R2is connected with the first gate line L3. Hereinafter, a circuit that includes the resistors R1and R2, the wiring connecting the connection point CP1and the first gate line L3, and the first gate line L3may be referred to as a “first gate voltage application circuit CI1(which may correspond to a “first wiring circuit” according to aspects of the present disclosure). The first gate voltage application circuit CI1is configured to, when the main board100is not connected with the sub board200, apply a voltage of the 24 V DC divided by the resistors R1and R2to the first gate terminal115G of the first FET115. A first drain terminal115D of the first FET115is connected with an input side of the main DC-DC converter113.

A drive voltage output path L11for supplying the 3.3 V DC generated by and output from the main DC-DC converter113is formed between an output side of the main DC-DC converter113and a second source terminal116S of a second FET116(which may correspond to a “second switching element” according aspects of the present disclosure). A second gate line L13is formed between a second gate terminal116G of the second FET116and a third terminal T3of the main connector100A. Further, resistors R3and R4are connected in series between the drive voltage output path L11and the ground. A connection point CP2between the resistors R3and R4is connected with the second gate line L13. Hereinafter, a circuit that includes the resistors R3and R4, the wiring connecting the connection point CP2and the second gate line L13, and the second gate line L13may be referred to as a “second gate voltage application circuit CI2” (which may correspond to a “second wiring circuit” according aspects of the present disclosure). The second gate voltage application circuit CI2is configured to, when the sub board200is not connected with the main board100, apply a voltage of the 3.3 V DC (as generated by the main DC-DC converter113) divided by the resistors R3and R4to the second gate terminal116G of the second FET116. A drive voltage supply path L14is formed between a second drain terminal116D of the second FET116and the circuit elements such as the ASIC105. Furthermore, a drive voltage relay path L15(which may correspond to an “output path” according to aspects of the present disclosure) is formed to relay the 3.3 V DC generated by and output from the sub board200, between a junction J1(which may correspond to a “junction” according to aspects of the present disclosure) on the way to the circuit elements such as the ASIC105on the drive voltage supply path L14, and a fourth terminal T4of the main connector100A.

For instance, when the main DC-DC converter113is normally operating, and the main board100is not connected with the sub board200, the voltage applied to the first source terminal115S of the first FET115is higher than the voltage applied to the first gate terminal115G by the first gate voltage application circuit CI1. Therefore, the first FET115is turned on and outputs the 24 V DC applied to the first source terminal115S to the main DC-DC converter113in a subsequent stage. Thereby, the main DC-DC converter113generates and outputs the 3.3 V DC to the second source terminal116S of the second FET116through the drive voltage output path L11. The second gate voltage application circuit CI2turns on the second FET116in substantially the same manner as the first gate voltage application circuit CI1. Thus, the second FET116outputs the 3.3 V DC applied to the second source terminal116S to the circuit elements such as the ASIC105in a subsequent stage through the drive voltage supply path L14.

FIG.5shows an example of a circuit configuration around the main DC-DC converter113and the sub DC-DC converter213when the sub board200is connected with the main board100. Since the circuit configuration around the main DC-DC converter113inFIG.5is substantially the same as that inFIG.4, a detailed explanation thereof may be omitted as appropriate.

As shown inFIG.5, a power input path L21is formed between the terminal T11of the sub connector200A of the sub board200and an input side of the sub DC-DC converter213. A power branch path L22is formed between the power input path L21and the terminal T12of the sub connector200A. A drive voltage output path L23is formed between an output side of the sub DC-DC converter213and the terminal T14of the sub connector200A. A drive voltage branch path L24is formed between the drive voltage output path L23and the terminal T13of the sub connector200A.

When the sub board200is connected with the main board100, the main connector100A and the sub connector200A are connected with each other. In the example shown inFIG.3B, the main connector100A and the sub connector200A are connected with each other via the harness150. However, as mentioned above, the harness150is not an essential element. Therefore, inFIG.5, the main connector100A and the sub connector200A are connected directly with each other.

When the main connector100A and the sub-connector200A are connected with each other, the first to fourth terminals T1to T4of the main connector100A are connected with the terminals T11to T14of the sub connector200A, respectively. When the first terminal T1of the main connector100A is connected with the terminal T11of the sub connector200A, the 24 V DC output from the AC-DC power supply board112is applied to the input side of the sub DC-DC converter213through the power relay path L2on the main board100, the first terminal T1of the main connector100A, the terminal T11of the sub connector200A, and the power input path L21on the sub connector200A. At the same time, the 24 V DC applied to the input side of the sub DC-DC converter213is applied to the first gate terminal115G of the first FET115through the power branch path L22on the sub board200, the terminal T12of the sub connector200A, the second terminal T2of the main connector100A, and the first gate line L3on the main board100. Accordingly, the voltage applied to the first gate terminal115G of the first FET115is equal to or higher than the voltage applied to the first source terminal115S of the first FET115. Hence, the first FET115is turned off, and does not output the 24 V DC applied to the first source terminal115S to the main DC-DC converter113in the subsequent stage. Thus, the main DC-DC converter113stops generating the 3.3 V DC even when the main DC-DC converter113is normally operating.

On the other hand, the sub DC-DC converter213starts operating based on the 24 V DC input as described above, and generates and outputs the 3.3 V DC. The 3.3 V DC from the sub DC-DC converter213is supplied to the circuit elements such as the ASIC105through a specific path as follows. The specific path is formed to join the drive voltage supply path L14at the junction J1via the drive voltage output path L23on the sub board200, the terminal T14of the sub connector200A, the fourth terminal T4of the main connector100A, and the drive voltage relay path L15on the main board100. At the same time, the 3.3 V DC output from the sub DC-DC converter213is applied to the second gate terminal116G of the second FET116through the drive voltage branch path L24on the sub board200, the terminal T13of the sub connector200A, the third terminal T3of the main connector100A, and the gate line L13on the main board100. Accordingly, the voltage applied to the second gate terminal116G of the second FET116is equal to or higher than the voltage applied to the second source terminal116S. Hence, the second FET116is turned off, and does not output the voltage applied to the second source terminal116S to the circuit elements such as the ASIC105in the subsequent stage. Nonetheless, at this time, since the main DC-DC converter113is stopped and does not output an effective 3.3 V DC, the second FET116does not need to be turned off, but is turned off just in case.

When the sub board200is connected with the main board100, the voltage applied to the second drain terminal116D of the second FET116is higher than the voltage applied to the second source terminal116S of the second FET116. Therefore, due to a body diode of the second FET116, an electric current may flow back in a direction from the second drain terminal116D to the second source terminal116S. In view of this, it is preferable to use a FET with a reverse current prevention function as the second FET116. Likewise, it is preferable to use a FET with a reverse current prevention function as the first FET115.

As described above, the printing system in the illustrative embodiment includes the printer1configured to form an image on a sheet S, and the sub board200. The printer1includes the AC-DC converter112A configured to convert an AC voltage (e.g., 100 V AC) from a commercial power supply into a DC voltage (e.g., 24 V DC). The printer1further includes the main board100. The main board100includes the ASIC105for image formation, the main DC-DC converter113configured to convert the DC voltage into a first DC voltage (e.g., 3.3 V DC) that is a drive voltage for the ASIC105, and the main connector100A.

The sub board200includes the sub DC-DC converter213configured to convert a DC voltage into a second DC voltage (e.g., 3.3 V DC) that is a drive voltage for the ASIC105. The sub board200further includes the sub connector200A configured to connect with the main board100via the main connector100A. When the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A, the main DC-DC converter113outputs the first DC voltage to the ASIC105. When the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A, the AC-DC converter112A outputs the DC voltage to the sub DC-DC converter213via the main connector100A and the sub-connector200A, and the sub DC-DC converter213outputs the second DC voltage to the ASIC105via the sub connector200A and the main connector100A.

Thus, according to the printer1in the illustrative embodiment, when the main DC-DC converter113on the main board100fails, simply connecting the sub board200with the main board100via the connectors100A and200A makes it possible to output the second DC voltage (i.e., the drive voltage) from the sub DC-DC converter213to the circuit elements such as the ASIC105. Namely, it is possible to output the drive voltage to the circuit elements such as the ASIC105without replacing the main board100.

The main board100further includes the first FET115configured to switch whether the DC voltage from the AC-DC converter112A is to be output to the main DC-DC converter113. Specifically, the first FET115outputs the DC voltage to the main DC-DC converter113when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A. Meanwhile, the first FET115does not output the DC voltage to the main DC-DC converter113when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A.

Thereby, when the sub board200is not connected with the main board100, the first FET115outputs the DC voltage from the AC-DC converter112A to the main DC-DC converter113. Meanwhile, when the sub board200is connected with the main board100, the DC voltage from the AC-DC converter112A is output to the sub DC-DC converter213. Namely, it is convenient that it is automatically selected to which of the main DC-DC converter113and the sub DC-DC converter213the DC voltage from the AC-DC converter112A is to be output, by an operator simply selecting whether to connect the sub board200with the main board100.

The main board100has the power relay path L2that diverges from the branch point B1in the middle of the power input path L1extending from the AC-DC converter112A to the first FET115and leads to the main connector100A. The AC-DC converter112A is configured to output the DC voltage to the sub DC-DC converter213via the power relay path L2, the main connector100A, and the sub connector200A when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A.

Thereby, when the sub board200is connected with the main board100, the first FET115does not output the DC voltage from the AC-DC converter112A to the main DC-DC converter113. In this case, the DC voltage from the AC-DC converter112A is output to the sub DC-DC converter213. In response, the sub DC-DC converter213converts the DC voltage to a second DC voltage and outputs the second DC voltage to the circuit elements such as the ASIC105. Thus, the operator only needs to connect the sub board200with the main board100to supply the drive voltage to the circuit elements such as the ASIC105.

The first FET115is a field effect transistor having the first gate terminal115G, the first source terminal115S, and the first drain terminal115D. The first source terminal115S is configured to receive an input of DC voltage. The first drain terminal115D is connected with the main DC-DC converter113. The main board100further includes the first gate voltage application circuit CI1having the first gate line L3to connect the first gate terminal115G with the main connector100A. The first gate voltage application circuit CI1is configured to, when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A, input such a voltage based on the DC voltage as to turn on the first FET115into the first gate terminal115G via the first gate line L3. The first gate voltage application circuit CI1is further configured to, when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A, input such a voltage based on the DC voltage as to turn off the first FET115into the first gate terminal115G via the first gate line L3. The first FET115is configured to be electrically conductive between the first source terminal115S and the first drain terminal115D when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A. The first FET115is further configured to be electrically blocked between the first source terminal115S and the first drain terminal115D when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A.

Thereby, when the sub board200is not connected with the main board100, the first FET115is electrically conductive between the first source terminal115S and the first drain terminal115D. In this case, the DC voltage from the AC-DC converter112A is output to the main DC-DC converter113. Meanwhile, when the sub board200is connected with the main board100, the first FET115is electrically blocked between the first source terminal115S and the first drain terminal115D. In this case, the DC voltage from the AC-DC converter112A is output to the sub DC-DC converter213. Thus, it is convenient that it is automatically selected to which of the main DC-DC converter113and the sub DC-DC converter213the DC voltage from the AC-DC converter112A is to be output, by the operator simply selecting whether to connect the sub board200with the main board100.

The first FET115has the reverse current prevention function to prevent an electric current from flowing reversely from the output side to the input side of the first FET115.

Thereby, when the voltage applied to the first drain terminal115D of the first FET115is higher than the voltage applied to the first source terminal115S, the body diode of the first FET115makes it possible to prevent the electric current from flowing reversely from the output side (i.e., the first drain terminal115D side) to the input side (i.e., the first source terminal115S side) of the first FET115.

The main board100further includes the second FET116configured to switch whether the first DC voltage from the main DC-DC converter113is to be output to the ASIC105. Specifically, the second FET116outputs the first DC voltage to the ASIC105when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A. Meanwhile, the second FET116does not output the first DC voltage to the ASIC105when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A.

Thus, it is convenient that it is automatically selected whether the first DC voltage from the main DC-DC converter113is to be output to the circuit elements such as the ASIC105, by the operator simply selecting whether to connect the sub board200to the main board100.

Further, the main board100has the drive voltage relay path L15extending from the main connector100A, at the junction J1in the middle of the drive voltage supply path L14extending from the second FET116to the ASIC105. The sub DC-DC converter213is configured to output the second DC voltage to the ASIC105via the sub connector200A, the main connector100A, and the drive voltage relay path L15when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A.

Thereby, when the sub board200is connected with the main board100, the second DC voltage from the sub DC-DC converter213is applied to the junction J1on the drive voltage supply path L14via the sub connector200A, the main connector100A, and the drive voltage relay path L15, to be output to the circuit elements such as the ASIC105. Thus, it is possible to drive the circuit elements such as the ASIC105with an appropriate drive voltage.

The second FET116is a field effect transistor having the second gate terminal116G, the second source terminal116S, and the second drain terminal116D. The second source terminal116S is connected with the output side of the main DC-DC converter113. The second drain terminal116D is connected with the ASIC105. The main board100further includes the second gate voltage application circuit CI2having the second gate line L13to connect the second gate terminal116G with the main connector100A. The second gate voltage application circuit CI2is configured to, when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A, input such a voltage based on the first DC voltage as to turn on the second FET116into the second gate terminal116G via the second gate line L13. The second gate voltage application circuit CI2is further configured to, when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A, input such a voltage based on the first DC voltage as to turn off the second FET116into the second gate terminal116G via the second gate line L13. The second FET116is configured to be electrically conductive between the second source terminal116S and the second drain terminal116D when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A. The second FET116is further configured to be electrically blocked between the second source terminal116S and the second drain terminal116D when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A.

Thereby, when the sub board200is not connected with the main board100, the second FET116is electrically conductive between the second source terminal116S and the second drain terminal116D. In this case, the first DC voltage from the main DC-DC converter113is output to the circuit elements such as the ASIC105. Meanwhile, when the sub board200is connected with the main board100, the second FET116is electrically blocked between the second source terminal116S and the second drain terminal116D. In this case, the second DC voltage from the sub DC-DC converter213is output to the circuit elements such as the ASIC105. Thus, it is convenient that it is automatically selected which of the first DC voltage from the main DC-DC converter113and the second DC voltage from the sub DC-DC converter213is to be output to the circuit elements such as the ASIC105, by the operator simply selecting whether to connect the sub board200with the main board100.

The second FET116has the reverse current prevention function to prevent an electric current from flowing reversely from the output side to the input side of the second FET116.

Thereby, when the voltage applied to the second drain terminal116D of the second FET116is higher than the voltage applied to the second source terminal116S, the body diode of the second FET116makes it possible to prevent the electric current from flowing reversely from the output side (i.e., the second drain terminal116D side) to the input side (i.e., the second source terminal116S side) of the second FET116.

The main board100further includes the first FET115and the second FET116. The first FET115is configured to switch whether the DC voltage from the AC-DC converter112A is to be output to the main DC-DC converter113. The second FET116is configured to switch whether the first DC voltage from the main DC-DC converter113is to be output to the ASIC105. Specifically, the first FET115outputs the DC voltage to the main DC-DC converter113when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A. Meanwhile, the first FET115does not output the DC voltage to the main DC-DC converter113when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A. The second FET115outputs the first DC voltage to the ASIC105when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A. Meanwhile, the second FET115does not output the first DC voltage to the ASIC105when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A.

Thus, it is convenient that it is automatically selected which of the main DC-DC converter113and the sub DC-DC converter213is used as a DC-DC converter to output the drive voltage to the circuit elements such as the ASIC105, by the operator simply selecting whether to connect the sub board200with the main board100.

Further, the main board100has the power supply relay path L2and the drive voltage relay path L15. The power supply relay path L2diverges from the branch point B1in the middle of the power input path L1extending from the AC-DC converter112A to the first FET115and leads to the main connector100A. The drive voltage relay path L15extends from the main connector100A to the junction J1in the middle of the drive voltage supply path L14extending from the second FET116to the ASIC105. The AC-DC converter112A is configured to output the DC voltage to the sub DC-DC converter213via the power relay path L2, the main connector100A, and the sub connector200A when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A. The sub DC-DC converter213is configured to output the second DC voltage to the ASIC105via the sub connector200A, the main connector100A, and the drive voltage relay path L15when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A.

Thereby, when the sub board200is connected with the main board100, the DC voltage from the AC-DC converter112A is output to the sub DC-DC converter213via the power relay path L2, the main connector100A, and the sub connector200A. Then, the second DC voltage into which the DC voltage has been converted by the sub DC-DC converter213is output to the circuit elements such as the ASIC105via the sub connector200A, the main connector100A, and the drive voltage relay path L15. Thus, even when the sub board200is connected with the main board100, it is possible to drive the circuit elements such as the ASIC105with an appropriate drive voltage.

The first FET115is a first field effect transistor having a first gate terminal, a first source terminal, and a first drain terminal. The first FET115has the first source terminal115S configured to receive an input of the DC voltage, and the first drain terminal115D connected with the input side of the main DC-DC converter113. The second FET116is a second field effect transistor having a second gate terminal, a second source terminal, and a second drain terminal. The second FET116has the second source terminal116S connected with the output side of the main DC-DC converter113, and the second drain terminal116D connected with the ASIC105. The main board100further includes the first gate voltage application circuit CI1and the second gate voltage application circuit CI2. The first gate voltage application circuit CI1has the first gate line L3connecting the first gate terminal115G and the main connector100A with each other. The first gate voltage application circuit CI1is configured to, when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A, input such a voltage based on the DC voltage as to turn on the first FET115into the first gate terminal115G via the first gate line L3. The first gate voltage application circuit CI1is further configured to, when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A, input such a voltage based on the DC voltage as to turn off the first FET115into the first gate terminal115G via the first gate line L3. The second gate voltage application circuit CI2has the second gate line L13connecting the second gate terminal116G and the main connector100A with each other. The second gate voltage application circuit CI2is configured to, when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A, input such a voltage based on the first DC voltage as to turn on the second FET116into the second gate terminal116G via the second gate line L13. The second gate voltage application circuit CI2is further configured to, when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A, input such a voltage based on the first DC voltage as to turn off the second FET116into the second gate terminal116G via the second gate line L13. The first FET115is configured to be electrically conductive between the first source terminal115S and the first drain terminal115D when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A. The first FET115is further configured to be electrically blocked between the first source terminal115S and the first drain terminal115D when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A. The second FET116is configured to be electrically conductive between the second source terminal116S and the second drain terminal116D when the main board100and the sub board200are not connected with each other via the main connector100A and the sub connector200A. The second FET116is further configured to be electrically blocked between the second source terminal116S and the second drain terminal116D when the main board100and the sub board200are connected with each other via the main connector100A and the sub connector200A.

Thus, it is convenient that it is automatically selected into which of the main DC-DC converter113and the sub DC-DC converter213the DC voltage from the AC-DC converter112A is to be output and which of the first DC voltage from the main DC-DC converter113and the second DC voltage from the sub DC-DC converter213is to be output to the circuit elements such as the ASIC105, by the operator simply selecting whether to connect the sub board200with the main board100.

The printer1further includes the AC-DC power supply board112having the AC-DC converter112A. In the printer1, the DC voltage is input into the main board100through a connection line connecting the AC-DC power supply board112and the main board100with each other.

Thus, the main board100is enabled to receive an input of DC voltage from outside the main board100.

The ASIC105for image formation is a controller configured to control operations of the printer1.

The ASIC105is enabled to receive an input of drive voltage from the main DC-DC converter113when the main DC-DC converter113is normally operating and to receive an input drive voltage from the sub DC-DC converter213when the main DC-DC converter113is abnormally operating.

While aspects of the present disclosure have been described in conjunction with various example structures outlined above and illustrated in the drawings, various alternatives, modifications, variations, improvements, and/or substantial equivalents, whether known or that may be presently unforeseen, may become apparent to those having at least ordinary skill in the art. Accordingly, the example embodiment(s), as set forth above, are intended to be illustrative of the technical concepts according to aspects of the present disclosure, and not limiting the technical concepts. Various changes may be made without departing from the spirit and scope of the technical concepts according to aspects of the present disclosure. Therefore, the disclosure is intended to embrace all known or later developed alternatives, modifications, variations, improvements, and/or substantial equivalents. Some specific examples of potential alternatives, modifications, or variations according to aspects of the present disclosure are provided below.

Modifications

FIGS.6and7show circuit configurations, different from the circuit configurations shown inFIGS.4and5, in a modification according to aspects of the present disclosure.FIG.6shows a case in which the main DC-DC converter113generates a 3.3 V DC as inFIG.4.FIG.7shows a case in which the sub DC-DC converter213generates a 3.3 V DC as inFIG.5. The circuits inFIGS.6and7are configured by partially modifying the circuits inFIGS.4and5, respectively. Therefore, inFIGS.6and7, substantially the same configurations as inFIGS.4and5are provided with the same reference characters as inFIGS.4and5, and detailed explanations thereof may be omitted as appropriate.

InFIG.6, on a main board100′, a first blocking element125and a second blocking element126are used instead of the first FET115and the second FET116on the main board100inFIG.4. Each of the first and second blocking elements125and126is configured to always not output a voltage applied to the input side thereof to the output side. Practicable examples of the first and second blocking elements125and126may include, but are not limited to, a high resistor and an off-state switching element. Practicable examples of the off-state switching element may include, but are not limited to, the first and second FETs115and116in the off state, and an off-state relay.

FIG.6shows a circuit configuration of the main board100′ not connected with the sub board200′ (seeFIG.7). As shown inFIG.6, the output side of the first blocking element125and the input side of the main DC-DC converter113are connected with each other through the power supply path L4. The junction J11on the power supply path L4and the second terminal T2of the main connector100A are connected with each other through a bypass path L5(which may correspond to a “first output path” according to aspects of the present disclosure).

The drive voltage output path L11is formed between the output side of the main DC-DC converter113and the input side of the second blocking element126. A second bypass path L12(which may correspond to a “second input path” according to aspects of the present disclosure) is formed between a branch point B2on the drive voltage output path L11and the third terminal T3of the main connector100A.

When the sub board200′ is not connected with the main board100′, a connector300is connected with the main connector100A. The connector300has terminals T21to T24. The terminals T21to T24are connected with the terminals T1to T4of the main connector100A, respectively. The terminals T21and T22are connected with each other through a first cable CA1. The terminals T23and T24are connected with each other through a second cable CA2.

When the connector300is connected with the main connector100A, the 24V DC from the AC-DC power board112is applied to the junction J11on the power supply path L4via the power relay path L2(which may correspond to a “first input path” according to aspects of the present disclosure) on the main board100′, the first terminal T1of the main connector100A, the terminal T21of the connector300, the first cable CA1, the terminal T22of the connector300, the second terminal T2of the main connector100A, and the bypass path L5on the main board100′. Thus, the 24V DC from the AC-DC power board112is applied to the main DC-DC converter113. Thereby, the main DC-DC converter113generates the 3.3 V DC and outputs the generated 3.3 V DC to the input side of the blocking element126via the drive voltage output path L11.

Then, the 3.3 V DC from the main DC-DC converter113is applied to the junction J1on the drive voltage supply path L14via the second bypass path L12on the main board100′, the third terminal T3of the main connector100A, the terminal T23of the connector300, the second cable CA2, the terminal T24of the connector300, and the drive voltage relay path L15(which may correspond to a “second output path” according to aspects of the present disclosure) on the main board100′. Thus, the 3.3 V DC from the main DC-DC converter113is supplied to the circuit elements such as the ASIC105.

FIG.7shows a circuit configuration of the main board100′ with the sub board200′ connected therewith. As shown inFIG.7, in substantially the same manner as the connection between the main board100and the sub board200, the connection between the main board100′ and the sub board200′ is made by connecting the main connector100A and the sub connector200A with each other. However, in the connection between the main board100′ and the sub board200′, unlike the connection between the main board100and the sub board200, no connection lines are connected with the terminals T12and T13of the sub connector200A on the sub board200′. Therefore, the main connector100A is open both between the first terminal T1and the second terminal T2and between the third terminal T3and the fourth terminal T4.

When the sub board200′ is connected with the main board100′, the 24 V DC from the AC-DC converter112A is applied to the input side of the sub DC-DC converter213via the branch point B1on the power input path L1on the main board100′, the power relay path L2, the first terminal T1of the main connector100A, the terminal T11of the sub connector200A, and the power input path L21on the sub board200′. The sub DC-DC converter213converts the input 24 V DC into a 3.3 V DC. The 3.3 V DC from the sub DC-DC converter213is applied to the junction J1on the drive voltage supply path L14via the drive voltage output path L23on the sub board200′, the terminal T14of the sub connector200A, the fourth terminal T4of the main connector100A, and the drive voltage relay path L15on the main board100′. Thus, the 3.3 V DC from the sub DC-DC converter213is supplied to the circuit elements such as the ASIC105.

As described above, the printer1in the modification is configured to form an image on a sheet S, and includes the AC-DC converter112A configured to convert an AC voltage (e.g., 100 V AC) from a commercial power supply into a DC voltage (e.g., 24 V DC). The printer1in the modification further includes the main board100′. The main board100′ includes the ASIC105for image formation, the main DC-DC converter113, and the main connector100A. The main DC-DC converter113is configured to convert the DC voltage into a first DC voltage (e.g., 3.3 V DC) that is a drive voltage for the ASIC105. The main connector100A is disposed at the main board100′ side and configured to connect with the sub board200′.

The sub board200′ includes the sub DC-DC converter213and the sub connector200A. The sub DC-DC converter213is configured to convert the DC voltage into a second DC voltage (e.g., 3.3 V DC) that is a drive voltage for the ASIC105. The sub connector200A is disposed at the sub board200′ side and configured to connect with the main board100′. When the main board100′ and the sub board200′ are not connected with each other via the main connector100A and the sub connector200A, the main DC-DC converter113outputs the first DC voltage to the ASIC105. Meanwhile, when the main board100′ and the sub board200′ are connected with each other via the main connector100A and the sub connector200A, the AC-DC converter112A outputs the DC voltage to the sub DC-DC converter via the main connector100A and the sub connector200A. In this case, the sub DC-DC converter213outputs the second DC voltage to the ASIC105via the sub connector200A and the main connector100A.

Thus, even with the printer1in the modification, when the main DC-DC converter113on the main board100′ fails, simply connecting the sub-board200′ to the main board100′ via the connectors100A and200A makes it possible to output the drive voltage from the sub DC-DC converter213to the circuit elements such as the ASIC105. Thus, it is possible to output the drive voltage to the circuit elements such as the ASIC105without replacing the main board100′.

The main board100′ further includes the power relay path L2and the bypass path L5. The power relay path L2extends from the AC-DC converter112A to the main connector100A. The detour path L5extends from the main connector100A to the main DC-DC converter113. The main connector100A includes the first terminal T1connected with the power relay path L2, and the second terminal T2connected with the bypass path L5. When the main board100′ and the sub board200′ are not connected with each other via the main connector100A and the sub connector200A, the first cable CA1configured to connect the first terminal T1and the second terminal T2with each other is attached to the main connector100A. In this case, the AC-DC converter112A outputs the DC voltage to the main DC-DC converter113via the power relay path L2, the first terminal T1, the first cable CA1, the second terminal T2, and the bypass path L5. Meanwhile, when the main board100′ and the sub board200′ are connected with each other via the main connector100A and the sub connector200A, the first cable CA1is not attached to the main connector100A. Therefore, in this case, the main connector100A is open between the first terminal T1and the second terminal T2.

Thus, when the sub board200′ is not connected with the main board100′, the DC voltage from the AC-DC converter112A is output to the main DC-DC converter113. Meanwhile, when the sub board200′ is connected with the main board100′, the DC voltage from the AC-DC converter112A is output to the sub DC-DC converter213. Namely, it is convenient that it is automatically selected to which of the main DC-DC converter113and the sub DC-DC converter213the DC voltage from the AC-DC converter112A is to be output, by the operator simply selecting whether to connect the sub board200′ with the main board100′.

The main board100′ further includes the second bypass path L12and the drive voltage relay path L15. The second bypass path L12extends from the main DC-DC converter113to the main connector100A. The drive voltage relay path L15extends from the main connector100A to the ASIC105. The main connector100A includes the third terminal T3connected with the second bypass path L12, and the fourth terminal T4connected with the drive voltage relay path L15. When the main board100′ and the sub board200′ are not connected with each other via the main connector100A and the sub connector200A, the second cable CA2connecting the third terminal T3and the fourth terminal T4with each other is attached to the main connector100A. In this case, the main DC-DC converter113outputs the first DC voltage to the ASIC105via the second bypass path L12, the third terminal T3, the second cable CA2, the fourth terminal T4, and the drive voltage relay path L15. Meanwhile, when the main board100′ and the sub board200′ are connected with each other via the main connector100A and the sub connector200A, the second cable CA2is not attached to the main connector100A. Therefore, in this case, the main connector100A is open between the third terminal T3and the fourth terminal T4.

Thus, when the sub board200′ is not connected with the main board100′, the first DC voltage from the main DC-DC converter113is output to the circuit elements such as the ASIC105via the second bypass path L12, the third terminal T3, the second cable CA2, the fourth terminal T4, and the drive voltage relay path L15. Meanwhile, when the sub board200′ is connected with the main board100′, the DC voltage from the AC-DC converter112A is output to the sub DC-DC converter213and converted into the second DC voltage by the sub DC-DC converter213. Thereby, the second DC voltage is output from the sub DC-DC converter213to the circuit elements such as the ASIC105. Accordingly, it is possible to drive the circuit elements such as the ASIC105with an appropriate drive voltage both when the sub board200′ is not connected with the main board100′ and when the sub board200′ is connected with the main board100′.

The main board100′ further includes the power relay path L2, the bypass path L5, the second bypass path L12, and the drive voltage relay path L15. The power relay path L2extends from the AC-DC converter112A to the main connector100A. The bypass path L5extends from the main connector100A to the main DC-DC converter113. The second bypass path L12extends from the main DC-DC converter113to the main connector100A. The drive voltage relay path L15extends from the main connector100A to the ASIC105. The main connector100A has the first terminal T1, the second terminal T2, the third terminal T3, and the fourth terminal T4. The first terminal T1is connected with the power relay path L2. The second terminal T2is connected with the bypass path L5. The third terminal T3is connected with the second bypass path L12. The fourth terminal T4is connected with the drive voltage relay path L15. When the main board100′ and the sub board200′ are not connected with each other via the main connector100A and the sub connector200A, the first cable CA1connecting the first terminal T1and the second terminal T2with each other and the second cable CA2connecting the third terminal T3and the fourth terminal T4with each other are attached to the main connector100A. In this case, the AC-DC converter112A outputs the DC voltage to the main DC-DC converter113via the power relay path L2, the first terminal T1, the first cable CA1, the second terminal T2, and the bypass path L5. Further, in this case, the main DC-DC converter113outputs the first DC voltage to the ASIC105via the second bypass path L12, the third terminal T3, the second cable CA2, the fourth terminal T4, and the drive voltage relay path L15. Meanwhile, when the main board100′ and the sub board200′ are connected with each other via the main connector100A and the sub connector200A, none of the first and second cables CA1and CA2is attached to the main connector100A. Therefore, in this case, the main connector100A is open both between the first terminal T1and the second terminal T2and between the third terminal T3and the fourth terminal T4.

Thus, when the sub board200′ is not connected with the main board100′, the DC voltage from the AC-DC converter112A is output to the main DC-DC converter113via the power relay path L2, the first terminal T1, the first cable CA1, the second terminal T2, and the bypass path L5. Further, in this case, the first DC voltage from the main DC-DC converter113is output to the circuit elements such as the ASIC105via the second bypass path L12, the third terminal T3, the second cable CA2, the fourth terminal T4, and the drive voltage relay path L15. Meanwhile, when the sub board200′ is connected with the main board100′, the DC voltage from AC-DC converter112A is output to the sub DC-DC converter213and converted into the second DC voltage by the sub DC-DC converter213. Thereby, the second DC voltage is output from the sub DC-DC converter213to the circuit elements such as the ASIC105. Accordingly, it is possible to drive the circuit elements such as the ASIC105with an appropriate drive voltage both when the sub board200′ is not connected with the main board100′ and when the sub board200′ is connected with the main board100′.

In the aforementioned illustrative embodiment and modification, both the main DC-DC converter113and the sub DC-DC converter213are configured to convert the input 24 V DC into a 3.3 V DC. However, both the input voltage and the output voltage are just examples, and practicable examples thereof are not limited to the above examples. Further, in addition to the main DC-DC converter113and the sub DC-DC converter213, one or more additional main DC-DC converters and sub DC-DC converters may be connected in parallel. In this case, the 24 V DC may be converted into a voltage (e.g., 5 V DC or 7 V DC) other than the 3.3 V DC. Further, in this case, the voltage input into each main DC-DC converter may be different from the voltages input into the other main DC-DC converters. Namely, respective different voltages may be input into the individual main DC-DC converters. Likewise, in this case, the voltage input into each sub DC-DC converter may be different from the voltages input into the other sub DC-DC converters. Namely, respective different voltages may be input into the individual sub DC-DC converters.

In the aforementioned illustrative embodiment and modification, the color laser printer1has been described as an example of an “image forming apparatus” according to aspects of the present disclosure. However, practicable examples of the “image forming apparatus” are not limited to this, but may include a monochrome laser printer. Further, practicable examples of the “image forming apparatus” are not limited to printers, but may include a multi-function peripheral and a copy machine.

The following shows examples of associations between elements illustrated in the aforementioned illustrative embodiment(s) and modification(s), and elements claimed according to aspects of the present disclosure. For instance, the printer1may be an example of an “image forming apparatus” according to aspects of the present disclosure. Each of the sub boards200and200′ may be an example of a “sub board” according to aspects of the present disclosure. The printing system including the printer1and the sub board200or200′ may be an example of an “image forming system” according to aspects of the present disclosure. The AC-DC converter112A may be an example of an “AC-DC converter” according to aspects of the present disclosure. Each of the main boards100and100′ may be an example of a “main board” according to aspects of the present disclosure. The ASIC105, the I/F group110, the sensor group111, the ROM102, the RAM103, and the NVRAM104may be included in examples of a “circuit element for image formation” according to aspects of the present disclosure. The main DC-DC converter113may be an example of a “main DC-DC converter” according to aspects of the present disclosure. The main connector100A may be an example of a “main connector” according to aspects of the present disclosure. The sub DC-DC converter213may be an example of a “main connector” according to aspects of the present disclosure. The sub connector200A may be an example of a “main connector” according to aspects of the present disclosure. The first FET115may be an example of a “first switching element” according to aspects of the present disclosure. The first FET115may be an example of a “first field effect transistor” according to aspects of the present disclosure. The first gate terminal115G may be an example of a “first gate terminal” according to aspects of the present disclosure. The first source terminal115S may be an example of a “first source terminal” according to aspects of the present disclosure. The first drain terminal115D may be an example of a “first drain terminal” according to aspects of the present disclosure. The second FET116may be an example of a “second switching element” according to aspects of the present disclosure. The second FET116may be an example of a “second field effect transistor” according to aspects of the present disclosure. The second gate terminal116G may be an example of a “second gate terminal” according to aspects of the present disclosure. The second source terminal116S may be an example of a “second source terminal” according to aspects of the present disclosure. The second drain terminal116D may be an example of a “second drain terminal” according to aspects of the present disclosure. The power relay path L2may be an example of an “input path” according to aspects of the present disclosure. The power relay path L2may be an example of a “first input path” according to aspects of the present disclosure. The second bypass path L12may be an example of a “second input path” according to aspects of the present disclosure. The drive voltage relay path L15may be an example of an “output path” according to aspects of the present disclosure. The bypass path L5may be an example of a “first output path” according to aspects of the present disclosure. The drive voltage relay path L15may be an example of a “second output path” according to aspects of the present disclosure. The first gate voltage application circuit CI1may be an example of a “first wiring circuit” according to aspects of the present disclosure. The second gate voltage application circuit CI2may be an example of a “second wiring circuit” according to aspects of the present disclosure. The first gate line L3may be an example of a “first gate line” according to aspects of the present disclosure. The second gate line L13may be an example of a “second gate line” according to aspects of the present disclosure. The first terminal T1may be an example of a “first terminal” according to aspects of the present disclosure. The second terminal T2may be an example of a “second terminal” according to aspects of the present disclosure. The third terminal T3may be an example of a “third terminal” according to aspects of the present disclosure. The fourth terminal T4may be an example of a “fourth terminal” according to aspects of the present disclosure. The AC-DC power supply board112may be an example of a “power supply board” according to aspects of the present disclosure. The power input path L1may be an example of a “connection line” according to aspects of the present disclosure. The first cable CA1may be an example of a “first cable” according to aspects of the present disclosure. The second cable CA2may be an example of a “second cable” according to aspects of the present disclosure. The 3.3 V DC from the main DC-DC converter113may be an example of a “first DC voltage” according to aspects of the present disclosure. The 3.3 V DC from the sub DC-DC converter213may be an example of a “second DC voltage” according to aspects of the present disclosure. The junction J1may be an example of a “junction” according to aspects of the present disclosure.