An analog-to-digital converter (200) has a first stage (207) to integrate and quantize the difference between a feedback signal (R) and an input signal (X) to a first intermediate signal (Y.sub.1) with a first resolution (M.sub.1), a second stage (208) to integrate and quantize the first intermediate signal (Y.sub.1) to a second intermediate signal (Y.sub.2) with a second, lower resolution (M.sub.2), a feedback stage (260) to convert the second intermediate signal (Y.sub.2) to the feedback signal (R), and a third stage (206, 270, 280, 285) to differentiate the first intermediate signal (Y.sub.1) to a third intermediate signal (W.sub.1), to delay the second intermediate signal (Y.sub.2) to a fourth intermediate signal (W.sub.2), and to add the third and fourth intermediate signals (W.sub.1, W.sub.2) to an output signal (Y) having a resolution that results from the sum of the first (M.sub.1) and second (M.sub.2) resolutions.

FIELD OF THE INVENTION
 The present invention relates to data converters and, in particular,
 relates to an analog-to-digital converter (ADC) with delta-sigma
 modulation.
 BACKGROUND OF THE INVENTION
 By modern electronics, useful information (for example voice, measurement
 data, music, control commands, etc.) is transmitted, processed or
 otherwise manipulated by signals in analog (A) form or digital (D) form.
 Signal conversion between analog (A) and digital (D) signals in both
 directions is thereby often required. The quality of analog-to-digital
 converters (ADC) and digital-to-analog converters (DAC) and other
 electronic circuits can be expressed by, for example, a signal-to-noise
 ratio (SNR) indicating how useful signals are separated from unwanted
 signals.
 Sigma-delta modulators serving as analog-to digital converters are well
 known in the art and had been described in a variety of publications. They
 are also known under the term "delta-sigma modulators".
 For the application of sigma-delta modulators and for prior art designs,
 the following references are useful: (REF 1) Temes, G. C: "Delta-Sigma
 Data Converters", chapter 10 on pages 317-339 of the following: "Franca,
 J. E., Tsividis, Y. (editors): `Design of Analog-Digital VLSI Circuits for
 Telecommunications and Signal Processing`, Second Edition, Prentice Hall,
 Englewood Cliffs, 1994, ISBN 0-13-203639-8"; (REF 2) Carley, R. L.,
 Schreier R., Temes, G. C.: "Delta-Signal ADCs with Multibit Internal
 Converters", chapter 8 on pages 244-281 of the following: "Norsworthy, S.
 R., Schreier, R., Temes, G. C. (editors): `Delta-Sigma Data Converters`,
 IEEE Press, New York, 1997, ISBN 0-7803-1045-4"; and (REF 3) Proakis, J.
 G., Manolakis, D. G. : "Digital Signal Processing", Third Edition,
 Prentice Hall, Englewood Cliffs, 1996, ISBN 0-13-373-762-4, chapter 9.2.
 "Analog-to-Digital Conversion", on pages 748-762, and chapter 3.1.
 "Z-Transform", on pages 151-160.
 FIG. 1 illustrates a simplified block diagram of prior art delta-sigma
 converter 100 providing a multilevel digital output signal Y. Converter
 100 comprises adder 105, analog integrator 110, multibit quantizer 120
 (i.e. ADC), and multibit digital-to-analog converter 130 (DAC). Adder 105
 receives input signal X from analog input 101; quantizer 120 provides
 multilevel digital output signal Y (e.g., 2.sup.M different magnitude
 levels) to digital output 102; DAC 130 feeds back Y via feedback lines 121
 (e.g., M bit) and 131 (analog) to adder 105. The feedback forces the
 average value of signal Y to track the average signal X. Any difference
 between X and Y accumulates in integrator 110 and eventually corrects
 itself. However, the linearity of DAC 130 limits the linearity of the
 complete converter 100.
 FIG. 2 illustrates a simplified time diagram of digital output signal Y of
 the converter of FIG. 1 for an assumed ramping input signal X.
 Conveniently, FIG. 2 also illustrates sampling time intervals T.sub.S. In
 the example, Y has a M=3 bit resolution with magnitude levels "000" for
 level 0, "001" for level 1, "010" for level 2, "011" for level 3, etc.
 Signal X has a maximum frequency of F. Quantizer 120 operates at sampling
 frequency F.sub.S (signal from input 103, F.sub.S =1/T.sub.S) that is,
 preferably, an oversampling frequency in respect to F. The quantization
 noise introduced by quantizer 120 has a first order shape. The signal
 noise ratio of the output signal is estimated as follows:
EQU SNR=k*(F/F.sub.S).sup.-1.5 *(2.sup.M -1) (1)
 where k is a constant factor. The SNR can be improved by increasing M, i.e.
 having a higher bit resolution in quantizer 120 and DAC 130. However, this
 is not desirable due to higher manufacturing costs.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
 Unless specified otherwise, digital signals (such as Y.sub.1, Y.sub.2,
 W.sub.1, W.sub.2, Y, Q.sub.1, Q2) have a sampling rate F.sub.S that
 corresponds to the sampling time interval T.sub.S =1/F.sub.S (cf. FIG. 2).
 For the convenience of explanation, transfer functions of functional
 blocks are indicated by well-known Z-operators described, for example, in
 reference (REF 3). In block diagrams, arrows .fwdarw. on the lines
 indicate a preferred signal flow direction. Bold lines are multibit lines
 for digital signals with M.sub.1 or M.sub.2 bit. Preferably, the multibit
 lines carry the bits in parallel.
 A person of skill in the art is able, based on the description herein, to
 implement the present invention by, for example, active and passive
 electronic components (e.g., transistors, connections or the like). Such
 persons are also able to provide power supplies, reference signals, clock
 signals (e.g., at F.sub.S) and others which are not shown for simplicity.
 FIG. 3 illustrates a simplified block diagram of delta-sigma
 analog-to-digital converter 200 according to the present invention.
 Converter 200 converts analog input signal X at input 201 to digital
 output signal Y at output 202. As illustrated in FIG. 3, converter 200
 preferably comprises adder 205, analog integrator 210, first quantizer
 220, digital integrator 230, amplifier 240, adder 245, second quantizer
 250, digital-to-analog converter (DAC) 260, digital differentiator 270,
 delay unit 280, and adder 285.
 Adder 205 sends the difference X-R between analog input signal X and analog
 feedback signal R to integrator 210. Integrator 210 integrates X-R to
 signal Q. Quantizer 220 outputs first digital intermediate signal Y'.sub.1
 having a resolution of M.sub.1 bit (e.g., 2.sup.M1 magnitude levels).
 Considering quantization noise E.sub.1 (i.e. an "error signal"), the first
 intermediate signal is written as Y.sub.1 =Y'.sub.1 +E.sub.1. Integrator
 230 integrates signal Y.sub.1 to signal Q.sub.1, for example, by providing
 an accumulation of Y.sub.1. Amplifier 240 amplifies signal Y.sub.1 with a
 gain G to signal Q.sub.2 (e.g., G.apprxeq.2). Adder 245 forwards the sum
 Q.sub.1 +Q.sub.2 to second quantizer 250. Quantizer 250 quantizes Q.sub.1
 +Q.sub.2 to second digital intermediate signal Y'.sub.2 having a
 resolution of M.sub.2 bit (2.sup.M2 magnitude levels). Again considering
 quantization by adding noise E.sub.2, the second intermediate signal is
 written as Y.sub.2 =Y'.sub.2 +E.sub.2.
 Preferably, quantizer 220 is implemented by a flash converter. Quantizer
 220 uses convenient values for bit resolution M.sub.1 between
EQU 2.ltoreq.M.sub.1.ltoreq.8 (2)
 and provides Y.sub.1 in a first signal range with a maximum Y.sub.1 MAX and
 a minimum Y.sub.1 MIN. For convenience of explanation, it is assumed that
 the maximum Y.sub.1 MAX is represented by all M.sub.1 bits being "1", i.e.
 the numerical value of 2.sup.M1 -1; and the minimum Y.sub.1 MIN is
 represented by all bits being "0", i.e. the numerical value zero. A
 quantization step .DELTA.Y.sub.1 of quantizer 220 is estimated as
EQU .DELTA.Y.sub.1 =(Y.sub.1 MAX -Y.sub.1 MIN)/(2.sup.M1 -1)
EQU =Y.sub.1 MAX /(2.sup.M1) (3)
 (2.sup.M1 -1) is the number of steps. In other words, adjacent levels of
 Y.sub.1 are spaced by .DELTA.Y.sub.1. A definition of maximum and minimum
 values having equal amount but different sign (i.e., (Y.sub.1 MAX
 =-Y.sub.1 MIN) is also convenient.
 Quantizer 250 uses convenient values for bit resolution M.sub.2 between
EQU 2.ltoreq.M.sub.2.ltoreq.8 (4)
 and provides Y.sub.2 in a second signal range having a maximum Y.sub.2 MAX
 and a minimum Y.sub.2 MIN. Quantization step .DELTA.Y.sub.2 for signal
 Y.sub.2 is defined accordingly.
 Preferably, first and second signal ranges are related according to
 ##EQU1##
 wherein, preferably, real factor p is larger than or equal to 1 or smaller
 than or equal to 4 (1.ltoreq.p.ltoreq.4). A preferred value for p is p
 .apprxeq.2. In other words, the signal ranges relate to each other
 proportionally, wherein the number of steps (2.sup.M2 1) of quantizer 250
 participates in the proportional factor between the ranges. Preferably,
 the first signal range (Y.sub.1 MAX -Y.sub.1 MIN) is smaller than the
 second signal range (Y.sub.2 MAX -Y.sub.2 MIN) but larger than the second
 quantization step .DELTA.Y.sub.2.
 Preferably, the signal ranges and bit resolutions are selected such that
 the quantization steps are different .DELTA.Y.sub.1.noteq..DELTA.Y.sub.2,
 preferably, .DELTA.Y.sub.1 &lt;.DELTA.Y.sub.2. In other words, quantizer
 220 provides a fine quantization and quantizer 250 provides a rough
 quantization.
 Analog integrator 210 has the following equivalent transfer function:
 ##EQU2##
 Using digital terminology is convenient; transferring into the z-area is
 well known.
 Digital integrator 230, amplifier 240 and adder 245 have the following
 transfer function:
 ##EQU3##
 DAC 260 feeds back signal Y.sub.2 that is - in analog form as signal R-
 subtracted from input signal X by adder 205. DAC 260 has a similar M.sub.2
 bit resolution as quantizer 250.
 Digital module 206 (dashed frame) with differentiator 270, adder 285 and
 delay unit 280 combines intermediate signals Y.sub.1 and Y.sub.2 to output
 signal Y. Preferably, differentiator 270 differentiates signal Y.sub.1 to
 signal W.sub.1 by the following transfer function:
EQU W.sub.1 =Y.sub.1 *H.sub.3 *Z.sup.-N (8)
 where Z.sup.-N indicates a delay by N sample time intervals T.sub.S
 (T.sub.S =1/F.sub.S). H.sub.3 stands for the inverse of the integrating
 function H.sub.1 of integrator 210 (cf. FIG. 4), that is
EQU H.sub.3 =1/H.sub.1 (9).
 Delay unit 280 delays signal Y.sub.2 by N sample time intervals T.sub.S to
 W.sub.2, that is
EQU W.sub.2 =Y.sub.2 *Z.sup.-N (10)
 Adder combines W.sub.1 and W.sub.2 to output signal Y, that is
EQU Y=W.sub.1 +W.sub.2 (11)
 It is an important advantage of the present invention that the resolution
 of output signal Y substantially corresponds to the sum of the resolutions
 of quantizers 220 and 250 (i.e. M.sub.1 +M.sub.2 -1). This allows to
 simplify the design of each quantizer in comparison to the prior art.
 In the following, the SNR of Y in converter 200 according to the present
 invention is estimated and compared to the prior art solution in converter
 100. For convenience, integrator 210 and quantizer 220 are referred to as
 first stage 207 (dashed frame); and integrator 230, amplifier 240,
 quantizer 250 are referred to as second stage 208 (dashed frame).
 FIG. 4 illustrates a simplified transfer function diagram ("equivalent
 circuit") of the converter of FIG. 3. In FIG. 4, square 307 symbolizes the
 transfer function H.sub.1 of stage 207 (cf. FIG. 3); square 308 symbolizes
 the transfer function H.sub.2 of stage 208 (cf. FIG. 3); the minus symbol
 305 symbolizes that intermediate signal Y.sub.2 is subtracted from input
 signal X; and the plus symbol 325, 355 symbolize the introduction of
 quantization noise E.sub.1 and E.sub.2, respectively, as described above.
 For simplicity, the transfer functions of quantizers 220 and 250 are
 considered as being 1, so that H.sub.1 and H.sub.2 are substantially
 provided by integrator 210 and integrator 230/amplifier 240, respectively,
 as explained above in connection with equations (6) and (7).
 Intermediate signal Y.sub.1 comprises the application of transfer function
 H.sub.1 to input signal X (first term), the negative application of
 transfer function H.sub.1 to intermediate signal Y.sub.2 as feedback
 (second term), and noise E.sub.1 (third term), that is:
EQU Y.sub.1 =H.sub.1 *X-H.sub.1 *Y.sub.2 +E.sub.1 (12)
 Intermediate signal Y.sub.2 comprises the application of transfer function
 H.sub.2 to intermediate signal Y.sub.1 and noise E.sub.2, that is:
EQU Y.sub.2 -H.sub.2 *Y.sub.1 +E.sub.2 (13)
 Intermediate signal Y.sub.2 can be obtained by inserting Y.sub.1 of
 equation (12) into equation (13), that is:
EQU Y.sub.2 H.sub.2 *[H.sub.1 *X-H.sub.1 *Y.sub.2 +E.sub.1 ]+E.sub.2 (14)
EQU Y.sub.2 =H.sub.1 *H.sub.2 *X-H.sub.1 *H.sub.2 *Y.sub.2 +H.sub.2 *E.sub.1
 +E.sub.2 (15)
EQU Y.sub.2 *(1+H.sub.1 *H.sub.2)=H.sub.1 *H.sub.2 *X+H.sub.2 *E.sub.1 +E.sub.2
 (16)
 ##EQU4##
 Intermediate signal Y.sub.1 can be calculated by inserting Y.sub.2 into
 equation (12), that is:
 ##EQU5##
 ##EQU6##
 Further, considering the functions of differentiator 270, delay unit 280
 and adder 285 (cf. module 206 in FIG. 3, not illustrated in FIG. 4), the
 output signal Y is estimated as follows:
 ##EQU7##
 Conveniently, taken N=1, equation (24) is simplified to
EQU Y=Z.sup.-1 *X+E.sub.1 *(1-Z.sup.1) (25)
 Thus, converter 200 provides first-order noise shaping similar to converter
 100 of the prior art. The SNR is estimated as
EQU SNR=k*(F/F.sub.S).sup.-1.5 *(2.sup.M1+M2-1 -1) (26)
 In comparison to converter 100 (cf. equation (1)), the present invention
 allows to achieve the same SNR by splitting the resolution M into first
 M.sub.1 &lt;M and second M.sub.2 &lt;M resolutions of first (220) and
 second (250) quantizers, respectively. Implementing low resolution
 quantizers is cost saving. This advantage can also be used to provide
 converter 200 having a higher SNR than prior art converter 100. In other
 words, the numbers of magnitude levels (2.sup.M1, 2.sup.M2) of each
 quantizer substantially add to each other to an overall number of
 magnitude levels (i.e., resolution) of analog-to-digital converter 200.
 FIGS. 5-8 illustrate simplified time diagrams of input signal X (FIG. 5),
 first digital intermediate signal Y.sub.1 (FIG. 6), second digital
 intermediate signal Y.sub.2 (FIG. 7), and digital output signal Y (FIG. 8)
 of converter 200 by way of example. FIGS. 5-8 share a common time axis
 with sampling time intervals T.sub.S (cf. FIG. 6).
 The magnitude of input signal X continuously decreases from +2 to -2.
 Intermediate signal Y.sub.1 assumes magnitudes between Y.sub.1 MAX =0.75
 and Y.sub.1 MIN =-1 spaced by step .DELTA.Y.sub.1 =0.25 (cf. equation (3),
 M.sub.1 =3). In other words, Y.sub.1 has a first plurality of magnitude
 levels: 0.75, 0.5, 0.25, 0, -0.25, -0.5, -0.75, and -1. Intermediate
 signal Y.sub.2 assumes magnitudes between Y.sub.2 MAX =3 and Y.sub.2 MIN
 =-4 spaced by .DELTA.Y.sub.2 =1 (M.sub.2 =3). As mentioned above,
 .DELTA.Y.sub.2 is different from .DELTA.Y.sub.1 ; here .DELTA.Y.sub.2
 &gt;.DELTA.Y.sub.1. In other words, Y.sub.2 has a second plurality of
 magnitude levels: 3, 2, 1, 0, -1, -2, -3, and -4.
 Output signal Y follows input signal X. As mentioned above, the combination
 of Y.sub.1 and Y.sub.2 to Y substantially adds the magnitudes of Y.sub.1
 and Y.sub.2 so that the overall accuracy expressed by the number of
 magnitude levels of Y is higher than for Y.sub.1 and Y.sub.2.
 FIG. 9 illustrates a simplified method flow chart diagram of method 400 for
 converting analog signal X to digital signal Y according to the present
 invention. In FIGS. 9 and 3, reference numbers 420/220, 450/250, 406/206,
 470/270, 480/280 and 485/285 stand for method steps and corresponding
 elements that perform these steps in the embodiment illustrated.
 In first quantizing step 420, a first integral of the difference between
 feedback signal R and input signal X is quantized to first intermediate
 digital signal Y.sub.1 that has a first plurality of magnitude levels (cf.
 FIG. 6).
 In second quantizing step 450, a second integral Q.sub.1 +Q.sub.2 of first
 intermediate digital signal Y.sub.1 is quantized to second intermediate
 digital signal Y.sub.2 that has a second plurality of magnitude levels
 (cf. FIG. 7).
 In combining step 406, intermediate digital signals Y.sub.1 and Y.sub.2 are
 combined to output signal Y so that the first and second pluralities of
 magnitude levels substantially add to an overall plurality of magnitude
 levels of the output signal Y (cf. FIG. 8).
 Preferably, combining step 406 comprises the following sub-steps:
 differentiating 470 first intermediate signal Y.sub.1 to third
 intermediate signal W.sub.1, delaying 480 second intermediate signal
 Y.sub.2 to fourth intermediate signal W.sub.2, and adding 485 third
 intermediate signal W.sub.1 and fourth intermediate signal W.sub.2 to
 digital output signal Y.
 Preferably, in differentiating step 470, Y.sub.1 is differentiated by
 transfer function H.sub.3 that is inverse to the transfer function H.sub.1
 by which first integral is obtained in quantizing step 420 (cf. equation
 (9)).
 Preferably, in quantizing step 420, adjacent magnitude levels of Y.sub.1
 are spaced by quantization step .DELTA.Y.sub.1, in quantizing step 450,
 adjacent magnitude levels of Y.sub.2 are spaced by quantization step
 .DELTA.Y.sub.2 that is different from quantization step .DELTA.Y.sub.1
 (cf. equation (5), e.g., .DELTA.Y.sub.1 &lt;.DELTA.Y.sub.2).
 Having described the present invention with detail above, the invention is
 now summarized as analog-to-digital converter (e.g., converter 200) that
 comprises:
 a first stage (e.g., 207 with integrator 210 and quantizer 220) to
 integrate and quantize the difference between a feedback signal (R) and an
 input signal (X) to a first intermediate signal (Y.sub.1) with a first
 resolution (M.sub.1);
 a second stage (e.g., 208 with integrator 230 and quantizer 250) to
 integrate and quantize the first intermediate signal (Y.sub.1) to a second
 intermediate signal (Y.sub.2) with a second, lower resolution; and
 a feedback stage (e.g., DAC 260) to convert the second intermediate signal
 (Y.sub.2) to the feedback signal (R); and
 a third stage (e.g., module 206 with differentiator 270, delay unit 280,
 adder 285) to differentiate the first intermediate signal (Y.sub.1) to a
 third intermediate signal (W.sub.1), to delay the second intermediate
 signal (Y.sub.2) to a fourth intermediate signal (W.sub.2), and to add the
 third and fourth intermediate signals (W.sub.1, W.sub.2) to an output
 signal (Y) having a resolution that results from the sum of the first
 (M.sub.1) and second (M.sub.2) resolutions.
 While the invention has been described in terms of particular structures,
 devices and methods, those of skill in the art will understand based on
 the description herein that it is not limited merely to such examples and
 that the full scope of the invention is properly determined by the claims
 that follow.