DLL circuit and semiconductor device having the same

A DLL circuit includes a delay line that generates an internal clock signal by delaying an external clock signal CLK, a counter circuit that sets a delay amount of the delay line, a phase detecting circuit that generates a phase determination signal based on a phase of the external clock signal, and an antialiasing circuit that prohibits the counter circuit to update a count value based on the phase determination signal, in response to a fact that a jitter component included in the external clock signal is equal to or higher than a predetermined frequency. With this configuration, a problem that the internal clock signal is continuously controlled to a wrong direction due to malfunction of aliasing does not occur.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a DLL circuit and a semiconductor device including the same, and more particularly relates to a DLL circuit suitable for application when a clock signal includes a jitter component, and a semiconductor device including the DLL circuit.

2. Description of Related Art

In recent years, a synchronous memory operating synchronously with a clock is widely used as a main memory of a personal computer or the like. Among synchronous memories, a DDR (Double Data Rate) synchronous memory needs to accurately synchronize input and output data with an external clock signal. Therefore, a DLL circuit for generating an internal clock synchronous with the external clock signal is essential (Japanese Patent Application Laid-open No. 2008-217947).

The external clock signal sometimes includes a jitter component. The jitter component is a fluctuation of a clock frequency, and the fluctuation has a predetermined frequency. Therefore, when the external clock signal includes a jitter component, the DLL circuit needs to cause the internal clock signal to follow the jitter of the external clock signal.

However, due to a sampling principle, an adjustment frequency of an internal clock signal, that is, a frequency exceeding a half of a sampling frequency cannot be regenerated. This means that when a jitter component included in the external clock signal exceeds one half of the sampling frequency, an internal clock signal generated by the DLL circuit cannot be caused to follow the jitter.

Further, when the jitter component exceeds one half of the sampling frequency, aliasing is generated. When the jitter component is close to an integral multiple of the sampling frequency, the DLL circuit continuously controls the internal clock signal to a wrong direction. Consequently, there was a problem that a phase of the internal clock signal is deviated greatly from a desired phase.

FIG. 6is a waveform diagram for explaining a phenomenon that an internal clock is continuously controlled to a wrong direction.

In the example shown inFIG. 6, when a sampling frequency is fSand also when a jitter frequency is fJ, fJ>fS/2 is obtained. Further, the sampling frequency fSand the jitter frequency fJare close to each other. In this case, a “phase delay” is determined continuously from sampling points S1to S12, and a “phase advance” is determined continuously from a sampling point S13until a sampling point (not shown). However, as shown inFIG. 6, a jitter component of about 11 cycles appears during an actual sampling period from the sampling points S1to S12, and the determination of the “phase delay” for 12 consecutive times is wrong. This similarly applies to determination for the sampling point S13and after, and the determination of the “phase advance” for a plurality of consecutive times is wrong. When the malfunction occurs, the DLL circuit continuously controls a control direction of the internal clock signal to a wrong direction. As a result, the phase is deviated greatly from a desired phase.

To solve the above problem, it is effective to take a high sampling frequency. However, adjustment of the internal clock signal requires a certain level of time, and therefore there is a limit to the sampling frequency. There is also a problem that, when the sampling frequency is set high, power consumption increases.

SUMMARY OF THE INVENTION

As explained above, according to conventional DLL circuits, it is difficult to prevent the occurrence of malfunction due to aliasing without increasing power consumption. Therefore, a DLL circuit capable of preventing the occurrence of malfunction due to aliasing while restricting the increase of power consumption has been desired.

A DLL circuit according to the present invention includes: a first delay line generating a second clock signal by delaying a first clock signal; a first counter circuit setting a delay amount of the first delay line; a phase detecting circuit generating a phase determination signal based on a phase of the first clock signal; and an antialiasing circuit prohibiting the first counter circuit to update a count value based on the phase determination signal, in response to a fact that a jitter component included in the first clock signal is a predetermined frequency or more.

A semiconductor device according to the present invention includes: the above DLL circuit: an output buffer outputting an external output signal synchronously with the second clock signal; and a replica buffer having substantially the same circuit configuration as that of the output buffer, and outputting a third clock signal synchronously with the second clock signal, wherein the phase detecting circuit determines a phase of the first clock signal by comparing the first clock signal and the third clock signal.

As explained above, according to the present invention, the counter circuit is prohibited to perform an update when a condition having a possibility of generating malfunction due to the aliasing is detected. Therefore, a problem that the second clock signal output from the DLL circuit is continuously controlled in a wrong direction goes away without increasing of a sampling frequency. Further, when the counter circuit is prohibited to perform the update, power consumption due to updating is not generated. Consequently, total power consumption can be decreased.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a block diagram showing a configuration of a semiconductor device10according to a first embodiment of the present invention.

As shown inFIG. 1, the semiconductor device10according to the first embodiment includes an internal circuit11that outputs an internal output signal DR, an output buffer12that outputs an external output signal DQ based on the internal output signal DR, and a DLL circuit100that controls an operation timing of the output buffer12. The internal circuit11is different depending on a kind of the semiconductor device10. For example, when the semiconductor device10according to the first embodiment is a DRAM, the internal circuit11includes a memory cell array, a column switch, a read amplifier or the like.

The output buffer12is a circuit that outputs the external output signal DQ to the outside via an output terminal13. An output timing of the external output signal DQ needs to be synchronous with an external clock signal CLK (a first clock signal) input via a clock terminal14. An operation timing of the output buffer12is controlled by the DLL circuit100. A configuration of the DLL circuit is explained in detail below.

As shown inFIG. 1, the DLL circuit100includes a delay line110, a frequency dividing circuit120, a counter circuit130, a phase detecting circuit140, and an antialiasing circuit200.

The delay line110is a circuit that generates an internal clock signal LCLK (a second clock signal) by delaying the external clock signal CLK. While not particularly limited, the delay line110preferably includes a coarse delay line that delays the external clock signal at a relatively coarse adjustment pitch, and a fine delay line that delays the external clock signal at a relatively fine adjustment pitch.

As shown inFIG. 1, the internal clock signal LCLK is supplied to the output buffer12and a replica buffer15. The output buffer12is a circuit that receives the internal output signal DR supplied from the internal circuit11, and supplies the signal to the output terminal13as the external output signal DQ, as described above. On the other hand, the replica buffer15is a circuit that has substantially the same circuit configuration as that of the output buffer12, and outputs a replica clock signal RCLK (a third clock signal) synchronously with the internal clock signal LCLK. With this configuration, a phase of the replica clock signal RCLK correctly coincides with a phase of the external output signal DQ. However, a size of a transistor constituting the replica buffer15does not need to be the same as that of a transistor constituting the output buffer12. A shrunk transistor can be used for the transistor constituting the replica buffer15, so long as impedances are substantially the same.

The frequency dividing circuit120is a circuit that generates a sampling clock signal SYNCLK by dividing the external clock signal CLK. The sampling clock SYNCLK is supplied to the counter circuit130and the antialiasing circuit200, and is used as a synchronization signal indicating a sampling timing. The frequency dividing circuit120is used because the update by the counter circuit130and the change of a delay amount by the delay line110require a certain period of time, and also because it is difficult for the counter circuit130to perform the update and for the delay line110to update the delay amount at each cycle of the external clock signal CLK. Further, when the update of the counter circuit130and the change of the delay amount of the delay line110are frequently performed more than necessary, power consumption increases substantially. While not particularly limited, in the first embodiment, a frequency number N of the frequency dividing circuit120is set to 8. That is, when a frequency of the external clock signal CLK is fCLK, and also when a frequency of the sampling clock signal SYNCLK, namely a sampling frequency, is fS, fS=fCLK/8 is obtained.

The counter circuit130sets a delay amount of the delay line110, and updates a count value synchronously with the sampling clock signal SYNCLK. Increase or decrease of the count value is determined based on an up/down signal UPDN supplied from the antialiasing circuit200. That is, when the up/down signal UPDN indicates up-count, the counter circuit130up-counts the count value synchronously with the sampling clock signal SYNCLK, thereby increasing the delay amount of the delay line110. On the other hand, when the up/down signal UPDN indicates down-count, the counter circuit130down-counts the count value synchronously with the sampling clock signal SYNCLK, thereby decreasing the delay amount of the delay line110.

The counter circuit130is permitted or prohibited to update the count value by a counter enable signal CEN supplied from the antialiasing circuit200. That is, even when an active edge of the sampling clock signal SYNCLK appears, update of the count value is prohibited when the counter enable signal CEN is in a disable state. Therefore, update of the count value is permitted when the active edge of the sampling clock signal SYNCLK appears, and is limited to a case where the counter enable signal CEN is in the enable state.

The phase detecting circuit140detects a difference between a phase of the external clock signal CLK and a phase of the replica clock signal RCLK. As described above, the delay line110adjusts a phase of the replica clock signal so that the phase coincides with a phase of the external output signal DQ. However, both phases always change based on a variation of parameters such as a voltage and a temperature affecting a delay amount of the delay line110, and based on a variation of a frequency of the external clock signal CLK itself. The phase detecting circuit140detects the change, and determines whether the replica clock signal RCLK is advanced or delayed from the external clock signal CLK. The phase detecting circuit140performs the determination at each cycle of the external clock signal CLK, and supplies a determination result to the antialiasing circuit200as a phase determination signal PD0. The phase determination signal PD0is used for the counter circuit130to update the count value.

The antialiasing circuit200receives the external clock signal CLK, the sampling clock signal SYNCLK, and the phase determination signal PD0, and generates the up/down signal UPDN and the counter enable signal CEN based on these received signals.

A basic operation of the antialiasing circuit200is as follows. The antialiasing circuit200monitors the phase determination signal PD0during one sampling cycle. When the antialiasing circuit200determines that the replica clock signal RCLK is advanced as a result of the monitoring, the circuit sets the up/down signal UPDN to an up-count state, thereby increasing a delay amount of the delay line110. On the other hand, when the antialiasing circuit200determines that the replica clock signal RCLK is delayed as a result of the monitoring, the circuit sets the up/down signal UPDN to a down-count state, thereby decreasing a delay amount of the delay line110. Further, the antialiasing circuit200determines whether a jitter component included in the external clock signal CLK is equal to or higher than a predetermined frequency. When a frequency of the jitter is lower than a predetermined frequency as the determination result, the antialiasing circuit200sets the counter enable signal CEN to an enable state. On the other hand, when a frequency of the jitter is equal to or higher than a predetermined frequency as the determination result, the antialiasing circuit200sets the counter enable signal CEN to a disable state.

Based on the above operation, the counter circuit130is prohibited to perform the update when the jitter component included in the external clock signal CLK is equal to or higher than a predetermined frequency. The antialiasing circuit200is explained in detail below.

FIG. 2is a circuit diagram of the antialiasing circuit200.

As shown inFIG. 2, the antialiasing circuit200has a reset pulse generating unit210that generates a reset pulse RST in response to a rising edge of the sampling clock signal SYNCLK. The reset pulse generating unit210includes a delay element211, an inverter212, and a NAND circuit213. The reset pulse generated by the reset pulse generating unit210is supplied in common to a reset input terminal of SR latches220and230.

The SR latch220has a configuration having NAND circuits221and222connected in circulation. An up-count signal UP0generated by a D-F/F circuit240, an inverter241, and a NAND circuit242is supplied to a set input terminal of the SR latch220. The D-F/F circuit240latches the phase determination signal PD0synchronously with the external clock signal CLK.

The SR latch230has a configuration having NAND circuits231and232connected in circulation. A down-count signal DN0generated by the D-F/F circuit240and a NAND circuit243is supplied to a set input terminal of the SR latch230.

An output UP of the SR latch220is supplied to a D-F/F circuit251, and an output of the D-F/F circuit251is used as the up/down signal UPDN. The D-F/F circuit251latches an output of the SR latch220synchronously with the sampling clock signal SYNCLK.

Further, outputs UP and DN of the SR latches220and230are supplied to an OR circuit260that includes an NOR circuit261and an inverter262. An output CEN0of the OR circuit260is supplied to a D-F/F circuit252. An output of the D-F/F circuit252is used as the counter enable signal CEN. The D-F/F circuit252latches the output CEN0of the OR circuit260synchronously with the sampling clock signal SYNCLK.

When the reset pulse RST is activated based on the above circuit configuration, the SR latches220and230are reset. As a result, the counter enable signal CEN becomes at a high level (an enable state), regardless of a level of the phase determination signal PD0. On the other hand, one of the SR latches220and230is set according to a level of the phase determination signal PD0. Therefore, a level of the up/down signal UPDN is determined according to the set. When a logic level of the phase determination signal PD0changes during the same sampling period, both SR latches220and230are set. Therefore, the counter enable signal CEN changes to a low level (a disable state).

As explained above, when the phase determination signal PD0changes during the same sampling period, the antialiasing circuit200operates to disable the counter enable signal CEN. Next, the operation of the antialiasing circuit200is explained in further detail with reference to a timing chart.

FIG. 3is a timing chart for explaining the operation of the antialiasing circuit200.

As shown inFIG. 3, the antialiasing circuit200activates the reset pulse RST at each eight cycles of the external clock signal CLK. This is because the sampling clock signal SYNCLK is a signal obtained by eight-frequency dividing the external clock signal CLK. In the example shown inFIG. 3, after the sampling clock signal SYNCLK is activated at a time t10, the phase determination signal PD0is at a high level when a first active edge of the external clock signal CLK arrives. Therefore, the up-count signal UP0is fixed to a high level, and the down-count signal DN0clocks. As a result the SR latch220holds a reset state, and the SR latch230is set. Therefore, the up/down signal UPDN becomes at a high level, and the counter enable signal CEN also becomes at a high level. Consequently, the counter circuit130is permitted to perform the update operation at a time t20, and the counter circuit130performs the up-count.

When the next sampling clock signal SYNCLK is activated at the time t20, the SR latches220and230are reset again. After the sampling clock signal SYNCLK is activated at the time t20, the phase determination signal PD0is at a low level when a first active edge of the external clock signal CLK arrives. Therefore, the down-count signal DN0is fixed to a high level, and the up-count signal UP0clocks. As a result, the SR latch230holds a reset state, and the SR latch220is set. However, in the example shown inFIG. 3, a level of the phase determination signal PD0changes at a time t21before a time t30when the next sampling clock signal SYNCLK is activated. Consequently, the counter enable signal CEN becomes at a low level, and the counter circuit130is prohibited to perform the update operation at the time t30.

As explained above, when a logic level of the phase determination signal PD0does not change during a sampling period, that is, when the phase determination signal PD0does not change during eight cycles of the external clock signal, the antialiasing circuit200sets the counter enable signal CEN to an enable state. On the other hand, when a logic level of the phase determination signal PD0changes during a sampling period, the antialiasing circuit200sets the counter enable signal CEN to a disable state. That a logic level of the phase determination signal PD0does not change during a sampling period means that the frequency fJof the jitter is equal to or smaller than one half of the sampling frequency fSeven when the external clock signal CLK includes the jitter.

FIG. 4AtoFIG. 4Dshow a relationship between the frequency fJof the jitter and the sampling frequency fS, whereFIG. 4Ashows a relationship of fJ>fS/2,FIG. 4BandFIG. 4Cshow a relationship of fJ=fS/2, andFIG. 4Dshows a relationship of fJ<fS/2.

As shown inFIG. 4A, when fJ>fS/2, change points X of a delay and an advance of the external clock signal CLK due to a jitter component are included in all sampling cycles T without exception. A jitter component of this frequency cannot be followed based on a sampling principle. Therefore, the antialiasing circuit200interrupts the jitter component.

Meanwhile, as shown inFIG. 4BandFIG. 4C, when fJ=fS/2, an appearance cycle of the change points X and the sampling cycle coincide with each other. Therefore, when the jitter has a phase as shown inFIG. 4B, each change point X and the sampling point S coincide with each other. When the jitter has a phase as shown inFIG. 4C, the change points X are included in all sampling cycles.

On the other hand, as shown inFIG. 4D, when fJ<fS/2, both a sampling cycle including the change point X and a sampling cycle not including the change point X are present in a mix without exception. Therefore, the counter circuit130is permitted to perform the update during a sampling cycle not including the change point X, and is prohibited to perform the update during a period including the change point X.

As explained above, when the external clock signal CLK includes a jitter component that the DLL circuit100cannot follow, the counter circuit130is prohibited to perform the update. Therefore, a malfunction due to the aliasing as shown inFIG. 6can be prevented.

However, as shown inFIG. 4D, even when the frequency fJof the jitter is equal to or smaller than one half of the sampling frequency fS, the change point X occurs in some sampling cycle without exception. Therefore, the counter circuit130is prohibited to perform the update in this sampling cycle. The sampling cycle occurs frequently when the frequency fJof the jitter is closer to one half of the sampling frequency fS. In this case, the counter circuit130is frequently prohibited to perform the update. Even in this case, the DLL circuit100can correctly hold a lock state. When this becomes a problem according to the type of application, the antialiasing circuit200can be configured to permit the counter circuit130to perform the update in a predetermined case even when the phase determination signal PD0changes within the same sampling cycle.

Specifically, the counter circuit130can be permitted to perform the update when the phase determination signal PD0during a sampling period keeps the same value at more than N/2 times consecutively. The N is a frequency dividing number of the frequency dividing circuit120, and it is 8 in the first embodiment. Therefore, in this case, when the phase determination signal PD0is the same value at five or more times consecutively, the counter circuit130is permitted to perform the update. Similarly, when the frequency dividing number N of the frequency dividing circuit120is 16, and also when the phase determination signal PD0is the same value at nine or more times consecutively, the counter circuit130is permitted to perform the update. Accordingly, the counter circuit130can frequently perform the update while preventing malfunction due to the aliasing to some extent. On the other hand, when the phase determination signal PD0is the same value at less than N/2 times consecutively during a sampling period, the counter circuit130should not be permitted to perform the update. In this case, when the counter circuit130is permitted to perform the update in this case, aliasing cannot be sufficiently removed.

Further, due to noise or the like, the phase determination signal PD0can be at a different logic level only once during the same sampling period. Therefore, when the counter circuit130is prohibited to perform the update in this case, it can become susceptible to noise. To solve this problem, when the phase determination signal PD0is at a different logic level only once during the same sampling period, this can be regarded as noise and ignored. That is, when the frequency dividing number N is 8, and also when the phase determination signal PD0has the same value at seven or more times, the counter circuit130can be permitted to perform the update, regardless of whether the same value is consecutive or non-consecutive. Similarly, when the frequency dividing number N is 16, and also when the phase determination signal PD0has the same value at 15 or more times, the counter circuit130can be permitted to perform the update, regardless of whether the same value is consecutive or non-consecutive.

When the frequency dividing number N is large, this can be also regarded as noise and ignored, when the phase determination signal PD0is at a different logic level only at two times (or more). For example, when the frequency dividing number N is 16, and also when the phase determination signal PD0has the same value at 14 or more times, the counter circuit130can be permitted to perform the update, regardless of whether the same value is consecutive or non-consecutive. When the frequency dividing number N is 32, and also when the phase determination signal PD0has the same value at 30 or more times, the counter circuit130can be permitted to perform the update, regardless of whether the same value is consecutive or non-consecutive. When the phase determination signals PD0becoming at different logic levels at two or more times are to be ignored, it is preferable to ignore these phase determination signals PD0subject to a condition that these phase determination signals PD0are generated discontinuously. This is because an inversion of the phase determination signal PD0due to noise is supposed to occur irregularly.

On the other hand, when the influence of the jitter needs to be more securely excluded, the phase determination signal PD0is monitored during a period exceeding the sampling cycle. When the phase determination signal PD0does not change during this period, the counter enable signal CEN is set to an enable state. Accordingly, while a condition for the counter enable signal CEN to become the enable state becomes severer, a lower frequency jitter component can be removed.

As explained above, according to the first embodiment, because the jitter that cannot be regenerated due to the sampling principle is interrupted, an error of the internal clock signal LCLK output from the DLL circuit100can be decreased without increasing the sampling frequency. Further, because the counter circuit130does not unnecessarily perform the update, power consumption can be decreased.

A second embodiment of the present invention is explained next.

FIG. 5is a block diagram of a configuration of a semiconductor device20according to the second embodiment.

As shown inFIG. 5, the semiconductor device20according to the second embodiment further includes a delay line160, a counter circuit170, and a duty detecting circuit180. A signal combiner190combines outputs of the two delay lines110and160, thereby generating the internal clock signal LCLK. Other features of the semiconductor device are basically the same to those of the semiconductor device10according to the first embodiment, and therefore like elements are denoted by like reference numerals and redundant explanations thereof will be omitted.

The delay line160and the counter circuit170constitute a duty correction circuit that corrects a duty of the external clock signal CLK inverted by an inverter250. Specifically, the delay line160adjusts a duty of the internal clock signal LCLK by adjusting a position of a falling edge of the external clock signal CLK. The counter circuit170determines the adjustment amount. On the other hand, the delay line110adjusts a position of a rising edge of the external clock signal CLK, thereby adjusting a phase of the internal clock signal LCLK. As a result, both the phase and the duty of the internal clock signal LCLK generated by the signal combiner190are correctly adjusted.

The counter circuit170sets a delay amount of the delay line160, and updates a count value synchronously with the sampling clock signal SYNCLK. Increase and decrease of the count value are determined based on an up/down signal UPDN1supplied from the duty detecting circuit180. That is, when the up/down signal UPDN1indicates up-count, the counter circuit170up-counts a count value synchronously with the sampling clock signal SYNCLK, thereby increasing a delay amount of the delay line160. On the other hand, when the up/down signal UPDN1indicates down-count, the counter circuit170down-counts a count value synchronously with the sampling clock signal SYNCLK, thereby decreasing a delay amount of the delay line160.

The duty detecting circuit180detects a duty of the internal clock signal LCLK based on the delay lines110and160.

The counter circuit170is permitted or prohibited to update a count value based on the counter enable signal CEN supplied from the antialiasing circuit200. That is, when the counter enable signal CEN becomes in a disable state, not only the counter circuit130but also the counter circuit170is prohibited to update a count value. As a result, also in a duty adjusting side, a problem that a duty is continuously adjusted in a wrong direction due to the influence of the jitter that cannot be followed goes away.