Semiconductor integrated circuit device

When an operation of a specified one of monitor circuits is defective or any of elements forming a ring oscillator in each of the monitor circuits has characteristic abnormality, if voltage control is performed based on a result from the monitor operating at a lowest speed, a required voltage may be overestimated. This results in an increase in power consumption, and also causes an accuracy reduction when the average value of detection results from the multiple monitors is calculated. The multiple monitor circuits are provided. Of the detection results therefrom, any detection result falling outside a predetermined range is ignored, and the average value of the remaining monitor results is used as a final monitor detection value.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2010-82458 filed on Mar. 31, 2010 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a monitor circuit for detecting a characteristic of an internal circuit.

In a semiconductor integrated circuit using a CMOS logic gate, as a method for reducing electric power, DVFS (Dynamic Voltage and Frequency Scaling) for controlling a power source voltage depending on a required speed is effective.

Representatives of a method for controlling a power source voltage include a method based on a delay monitor. Since there are characteristic variations in a chip, performance obtained by subtracting a certain degree of margin from chip performance detected with the delay monitor is lowest performance in a real chip. The voltage needs to be controlled such that the lowest performance satisfies the required speed. Here, when the accuracy of the chip performance detected by the delay monitor is low, it is necessary to overestimate the margin, and consequently the power source voltage is controlled to be high, resulting in increased power consumption. Accordingly, by, e.g., disposing multiple monitors in the chip, and retrieving a result from the monitor operating at a lowest speed, the margin to be estimated can be reduced.

FIG. 1is a block diagram schematically showing a configuration of a semiconductor integrated circuit device according to a prior art technology. The semiconductor integrated circuit device ofFIG. 1includes a power supply circuit and a chip. Here, the chip includes multiple monitor circuits, a detection circuit, and a control circuit. The multiple monitor circuits detect a characteristic of the chip at mutually different positions, and output the results of detection toward the detection circuit. The detection circuit outputs an overall result obtained by combining the multiple detection results transmitted from the multiple monitor circuits toward the control circuit. The control circuit generates a control signal in accordance with the overall result. The power supply circuit adjusts a power source voltage VDDin accordance with the control signal, and supplies the adjusted power source voltage VDDto the chip.

In the semiconductor integrated circuit device ofFIG. 1, when the characteristic variations in the chip are of a known magnitude, the average value of the detection results from the multiple monitors is calculated, and the variations are subtracted therefrom to allow the lowest performance in the chip to be estimated.

With regard to the foregoing, Japanese Unexamined Patent Publication No. 2009-10344 discloses a description related to a semiconductor integrated circuit. The semiconductor integrated circuit includes a power source voltage supply means for supplying a power source voltage to one or more internal circuits. The semiconductor integrated circuit has the following characteristic feature. That is, the circuit includes multiple process monitor means disposed at multiple locations over the circuit to operate in accordance with the power source voltage, and detect monitor data on the individual locations. The power source voltage supply means generates power source voltages in accordance with the multiple monitor data items mentioned above, and supplies the power source voltages to the internal circuits.

SUMMARY

When an operation of a specified one of the monitor circuits is defective, or any of elements forming a ring oscillator in the monitor circuit has characteristic abnormality, if voltage control is performed based on the result from the monitor operating at the lowest speed, a required voltage may be overestimated. This results in an increase in power consumption, and also reduces accuracy when the average value of the detection results from the multiple monitors is calculated.

Hereinbelow, a means for addressing the problem will be described using reference numerals used in DESCRIPTION OF THE PREFERRED EMBODIMENTS. The reference numerals are added to define the correspondence relationship between the description in WHAT IS CLAIMED and DESCRIPTION OF THE PREFERRED EMBODIMENTS. However, the numerals should not be used for the interpretation of the technical scope of the invention described in WHAT IS CLAIMED.

A semiconductor integrated circuit device (1) according to the present invention includes multiple delay elements (204,20(i)), a group of monitor circuits (2(i),2), a control circuit (3), and a summing circuit (4). Here, the multiple delay elements (204,20(i)) are individually disposed at multiple locations in the same semiconductor chip, and have respective characteristics in accordance with the multiple locations. The group of monitor circuits (2,2(i)) measures the characteristics of the multiple delay elements (204,20(i)). The control circuit (3) controls the group of monitor circuits (2(i),2). The summing circuit (4) sums the results of the measurement, and calculates an overall characteristic of the semiconductor chip. The control circuit (3) excludes, from a target of summation, any of the multiple delay elements (204,20(i)) which show the result of the measurement falling outside a predetermined range.

The semiconductor integrated circuit device of the present invention allows high monitor detection accuracy to be obtained. This is because the multiple monitor circuits are provided and, of the detection results therefrom, those falling outside the predetermined range are ignored, while the average value of the remaining monitor results is used as a final monitor detection value. That is, even when there is a defect in any of the monitor circuits, the influence thereof can be removed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to the accompanying drawings, embodiments for implementing a semiconductor integrated circuit device according to the present invention will be described hereinbelow.

First Embodiment

FIG. 2is a block diagram showing a configuration of a semiconductor integrated circuit device1according to a first embodiment of the present invention. A description will be given of the components of the semiconductor integrated circuit device1ofFIG. 2. The semiconductor integrated circuit device1ofFIG. 2includes the total of N monitor circuits2(1),2(2), . . . , and2(N), a control circuit3, and a summing circuit4. Here, N represents any integer of 2 or more. Note that each of the monitor circuits2(1) to2(N) has the same configuration, and therefore any integer included in the range of 1 to N will be hereinafter represented by “i”, and expressed in a generalized form such as “2(i)” in the description given below.

Each of the N monitor circuits2(i) includes a RESET signal input portion, an ENABLE signal input portion, a G(i) signal input portion, and a C(i) signal output portion. The control circuit3includes a C(i) signal input portion, a RESET signal output portion, an ENABLE signal output portion, N G(i) signal output portions, and an M signal output portion. The summing circuit4includes a C(i) signal input portion, an M signal input portion, and a Coutsignal output portion. The respective functions of a RESET signal, an ENABLE signal, a G(i) signal, a C(i) signal, an M signal, and a Coutsignal will be described later.

A description will be given of coupling relations between the components of the semiconductor integrated circuit device1ofFIG. 2. In each of the N monitor circuits2(i), the RESET signal input portion, the ENABLE signal input portion, and the G(i) signal input portion are respectively coupled to the RESET signal output portion, the ENABLE signal output portion, and the corresponding G(i) signal output portion of the control circuit3, while the C(i) output portion is coupled to the C(i) signal input portion of the control circuit3and to the C(i) signal input portion of the summing circuit4. The M signal output portion of the control circuit3is coupled to the M signal input portion of the summing circuit4.

A description will be given of an operation of the semiconductor integrated circuit device1ofFIG. 2. Each of the monitor circuits2(i) evaluates the performance of the semiconductor integrated circuit device1independently of each other. The summing circuit4collects evaluations from the monitor circuits2(i) to accurately evaluate the performance of the semiconductor integrated circuit device1. The control circuit3controls the monitor circuits2(i) and the summing circuit4.

FIG. 3is a block diagram showing a configuration of each of the monitor circuits2(i) according to the first embodiment of the present invention. A description will be given of the components of the monitor circuit2(i) ofFIG. 3. Each of the monitor circuits2(i) includes a ring oscillator202, a counter203, and an AND gate201. Here, the ring oscillator202includes a NAND gate205and a delay element204. Note that, inFIG. 3, only one delay element204is shown but, in an actual situation, multiple the delay elements204coupled in series may also be used. This is for sufficiently reducing the influence given by random variations in a characteristic that each of the delay elements204can have to a delay time.

Here, as the delay element204, there may be used, e.g., a buffer circuit, an even number of NOT gates coupled in series, or the like. As the delay element204, an odd number of NOT gates coupled in series may also be used but, in this case, the NAND gate205needs to be replaced with an AND gate.

The NAND gate205includes a first input portion, the ENABLE signal input portion, and an output portion. The delay element204includes an input portion and an output portion. The counter203includes a first input portion and the RESET signal input portion. The AND gate201includes a first input portion, the G(i) signal input portion, and the C(i) signal output portion.

The RESET signal input portion, the ENABLE signal input portion, and the G(i) signal input portion of the monitor circuit2(i) are respectively coupled to the RESET signal input portion of the counter203, the ENABLE signal input portion of the NAND gate205, and the G(i) signal input portion of the AND gate201. The output portion of the NAND gate205is coupled to the input portion of the delay element204. The output portion of the delay element204is coupled to the first input portion of the counter203and to the first input portion of the NAND gate205. The output portion of the counter203is coupled to the first input portion of the AND gate201. The C(i) signal output portion of the AND gate201is coupled to the C(i) signal output portion of the monitor circuit2(i).

A description will be given of an operation of each of the monitor circuits2(i) ofFIG. 3. First, the ring oscillator202oscillates in a predetermined cycle only during a period during which the ENABLE signal is in a HIGH state (i.e., “1”). The cycle will be hereinafter represented by “TROSC(i)”. That is, a ROOUT signal outputted from the ring oscillator202is in a LOW state (i.e., “0”) during a period during which the ENABLE signal is in the LOW state. However, during the period during which the ENABLE signal is in the HIGH state, the ROOUT signal is alternately and repeatedly brought into the LOW state and into the HIGH state. The period TROSC(i) is determined by the characteristics of the delay element204and the NAND circuit205.

Next, the counter203receives the ROOUT signal, and measures the number of times that the ring oscillator202oscillated, i.e., the pulse number of the ROOUT signal. Here, the counter203needs to reset the measured number of times before starting counting of the number of pulses outputted from the ring oscillator202. By receiving the RESET signal, the counter203performs the resetting. When it is assumed that a period during which the ENABLE signal shifts from the LOW state to the HIGH state, and returns to the LOW state is T, an output signal from the counter203has a binary value equal to a quotient obtained by dividing T by TROSC(i). The quotient will be hereinafter represented by “T/TROSC(i)”, though, to be strict, it is necessary to truncate the digits after the decimal point, i.e., ignore the remainder. The output signal from the counter203remains the same until next time the RESET signal shifts to the HIGH state.

Finally, the AND gate201outputs T/TROSC(i) as C(i) when the G(i) signal is in the HIGH state, or outputs 0 as C(i) when the G(i) signal is in the LOW state. In other words, the G(i) signal functions as a gating signal for enabling or disabling an output of the monitor circuit2(i). Here, it is assumed that each of the ROOUT signal and the C(i) signal is outputted as a binary value representing T/TROSC (i) with m digits or m bits, where m is a predetermined integer. Accordingly, the AND gate201is required to handle a m-bit value. For example, m AND gates may be used appropriately in parallel. However, in the present invention, the ROOUT signal and the C(i) signal need not be limited to such a form, and another form may also be used after various circuits are appropriately modified.

FIG. 4is a block diagram showing a configuration of the control circuit3according to the first embodiment of the present invention. A description will be given of the components of the control circuit3ofFIG. 4. The control circuit3ofFIG. 4includes a control signal generation circuit31and a defect detection circuit32. Here, the defect detection circuit means a circuit having a function of detecting a monitor which does not operate normally. The defect detection circuit32includes a register323, a selector320, a selector321, and a comparison circuit322.

The register323includes a MAX signal output portion and a MIN signal output portion. The selector320includes a MAX signal input portion, a MIN signal input portion, a CMP signal input portion, and an output portion. The selector321includes N C(i) signal input portions, a SEL signal input portion, and an output portion. The comparison circuit322includes first and second input portions and an output portion. The control signal generation circuit31includes an input portion, a CMP signal output portion, a SEL signal output portion, a RESET signal output portion, an ENABLE signal output portion, and N G(i) signal output portions.

A description will be given of coupling relations between the components of the control circuit3ofFIG. 4. The MAX signal output portion and the MIN signal output portion in the register322are respectively coupled to the MAX signal input portion and the MIN signal input portion in the selector320. The N C(i) signal input portions of the control circuit3are respectively coupled to the N C(i) signal input portions of the selector321. The output portion of the selector320is coupled to the first input portion of the comparison circuit322. The output portion of the selector321is coupled to the second input portion of the comparison circuit322. The output portion of the comparison circuit322is coupled to the input portion of the control signal generation circuit31. The CMP signal output portion of the control signal generation circuit31is coupled to the CMP signal input portion of the selector320. The SEL signal output portion of the control signal generation circuit31is coupled to the SEL signal input portion of the selector321. The RESET signal output portion, the ENABLE signal output portion, and the G(i) signal output portion in the control signal generation circuit31are respectively coupled to the RESET signal output portion, the ENABLE signal output portion, and the G(i) signal output portion in the control circuit3.

A description will be given of an operation of the control circuit3ofFIG. 4. The register323stores a predetermined maximum value and a predetermined minimum value in the inside thereof. The register323outputs a MAX signal representing the maximum value and a MIN signal representing the minimum value toward the selector320. The control signal generation circuit31outputs a selection signal CMP for selecting the maximum value or the minimum value toward the selector320. The selector320outputs the MIN signal toward the comparison circuit322when the CMP signal is in the LOW state, or outputs the MAX signal toward the comparison circuit322when the CMP signal is in the HIGH state.

The control signal generation circuit31outputs a SEL signal toward the selector321. The selector321selects any one of the N C(i) signals inputted from the N monitor circuits2(i) in accordance with the SEL signal, and outputs the selected C(i) signal toward the comparison circuit322.

The comparison circuit322compares the MAX signal or the MIN signal inputted thereto from the selector320with the C(i) signal inputted thereto from the selector321, and outputs the result thereof toward the control signal generation circuit31.

The control signal generation circuit31varies each of the CMP signal and the SEL signal in a predetermined range to check whether or not each of the N C(i) signals is not more than the predetermined maximum value and not less than the predetermined minimum value. Here, when MIN<C(i)<MAX is satisfied, the i-th monitor2(i) is determined to be normally operating. Otherwise, the i-th monitor2(i) is determined to be defective. The control signal generation circuit31outputs G(i) in the HIGH state when the i-th monitor2(i) is normal, or outputs G(i) in the LOW state when the i-th monitor2(i) is defective. The control signal generation circuit31also outputs the RESET signal and the ENABLE signal.

FIG. 5is a block diagram showing a configuration of the summing circuit4according to the first embodiment of the present invention. A description will be given of the components of the summing circuit4ofFIG. 5. The summing circuit4ofFIG. 5includes (N−1) adders4(1) to4(N−1) and an averaging circuit401. Each of the (N−1) adders4(i) includes first and second input portions and an output portion. The averaging circuit401includes a first input portion, an M signal input portion, and a Coutsignal output portion. Note that, here, N is a power-of-2 number, and an exponent therefor is represented by k. That is, a description will be given of the case where N=2^k is satisfied, and k is an integer of 0 or more. Other cases will be described later.

A description will be given of coupling relations between the components of the summing circuit4ofFIG. 5. The (N−1) adders4(1) to4(N−1) are coupled in a positional relation of nodes forming a complete binary tree. Specifically, to start with, the first and second input portions of the first adder4(1) are respectively coupled to the C(1) signal input portion and the C(2) signal input portion of the summing circuit4. The first and second input portions of the second adder4(2) are respectively coupled to the C(3) signal input portion and the C(4) signal input portion of the summing circuit4. Subsequently, in the same manner as described above, the first and second input portions of the N/2-th adder4(N/2) are respectively coupled to the C(N−1) signal input portion and the C(N) signal input portion of the summing circuit4. The first to N/2-th adders4(1) to4(N/2) correspond to the leaves of the complete binary tree.

Next, the first and second input portions of the (N/2+1)-th adder4(N/2+1) are coupled to the respective output portions of the first and second adders4(1) and4(2). The first and second input portions of the (N/2+2)-th adder4(N/2+2) are coupled to the respective output portions of the third and fourth adders4(3) and4(4). Subsequently, in the same manner as described above, the first and second input portions of the adder4(N/2+N/4) are coupled to the respective output portions of the (N−1)-th and N-th adders4(N−1) and4(N). The (N/2+1)-th to (N/2+N/4)-th adders4(N/2) to4(N/2+N/4) correspond to the nodes having the leaves of the complete binary tree.

Subsequently, in the same manner as described above, the (N/2+N/4+1)-th to (N−2)-th adders4(N/2+N/4+1) to4(N−2) correspond to the nodes of the complete binary tree. Finally, the first and second input portions of the (N−1)-th adder4(N−1) are coupled to the output portions of the (N−3)-th and (N−2)-th adders4(N−3) and4(N−2). The (N−1)-th adder4(N−1) corresponds to the root of the complete binary tree.

The first input portion, the M signal input portion, and the Coutsignal output portion of the averaging circuit401are respectively coupled to the output portion of the (N−1)-th adder4(N−1), the M signal input portion of the summing circuit4, and the Coutsignal output portion of the summing circuit4.

A description will be given of an operation of the components of the summing circuit4. Each of the adders4(i) receives two data items, performs an addition therebetween, and outputs the result thereof. Since each of the C(i) signals inputted to the first to N/2-th adders4(1) to4(N/2) has a binary value represented by m bits, a signal outputted therefrom has a (m+1)-bit binary value. Likewise, each of the (N/2+1)-th to (N/2+N/4)-th adders4(N/2+1) to4(N/2+N/4) outputs a (m+2)-bit binary value, and the (N−1)-th adder4(N−1) outputs a (m+k)-bit binary value. At this time, the (m+k)-bit binary value outputted from the (N−1)-th adder4(N−1) is equal to the total sum of C(1) to C(N).

The averaging circuit401receives the (m+k)-bit binary value, shifts the received binary value to lower-order positions by k bits, and outputs an m-bit binary value. At this time, the m-bit binary value outputted from the averaging circuit401is equal to a quotient obtained by dividing the total sum of C(1) to C(N) by N. To be strict, the remainder of the division of the total sum of C(1) to C(N) by N is ignored, but this falls within an error range. Even when a Coutsignal thus obtained is assumed to be the average value of C(1) to C(N), there is substantially no problem.

The foregoing is the description of the operation of the summing circuit4when the total number of the effective C(i) signals is a power-of-2 number. When the total number of the effective C(i) signals is not a power-of-2 number, any of the effective C(i) signals is intentionally disabled to adjust the total number of the effective C(i) signals to a power-of-2 number. By setting the value of each of the disabled C(i) signals to 0, it is possible to eliminate influence on the total sum of C(1) to C(N). In addition, the number of bits by which the binary value is shifted to lower-order positions when the average value is calculated may be changed appropriately. Note that the number of bits by which the binary value is shifted is transmitted as the M signal representing the number of effective monitors from the control circuit3toward the averaging circuit401. Here, the number of effective monitors means the number of monitors which are not determined to be defective, that is, the number of monitors which operate normally. It is preferable that which one of the effective C(i) signals is to be disabled is selectively determined by the control signal generation circuit31for generating the G(i) signals. However, the present invention need not necessarily be limited in such a manner.

For still another configuration of the summing circuit4, a typical division circuit may also be used. In this case, the configuration of the summing circuit4is complicated, but an average value using all the effective monitor circuits2(i) can be obtained.

FIG. 6is a time chart for illustrating an example of the operation of the semiconductor integrated circuit device1according to the first embodiment of the present invention. Along the time chart ofFIG. 6, the example of the operation of the semiconductor integrated circuit device1according to the first embodiment of the present invention will be described.

The time chart ofFIG. 6shows graphs representing respective time variations in the RESET signal, the ENABLE signal, the ROOUT signal, the C(i) signal, the G(i) signal, the SEL signal, and the CMP signal in a descending order. In the time chart ofFIG. 6, the abscissa axis represents elapsed time, and the ordinate axis represents the intensity of each of the signals.

The time t0shows an initial state. At the time t0, RESET=0, ENABLE=0, and G(i)=1 are satisfied.

At the time t1, the RESET signal shifts to the HIGH state, and returns to the LOW state at the time t2. During the time period therebetween, the counter203is reset.

At the time t3, the ENABLE signal shifts to the HIGH state, and returns to the LOW state at the time t4. The time period from the time t3to the time t4is assumed to be T. During the time period, the ring oscillator202oscillates, the ROOUT signal are repeatedly and periodically brought into the LOW state and into the HIGH state, and the counter203measures the number of times that the ROOUT signal shifts to the HIGH state.

By performing the foregoing operation between the times t1and t4once, the C(i) signals are simultaneously determined in all the N monitor circuits2(i).

During the time period from the time t5to the time t6, the C(i) signals are sent to the selector321, the CMP signal is repeatedly and alternately brought into the LOW state and into the HIGH state, and the SEL signal successively selects C(1) to C(N) to determine the effectiveness of each of the C(i) signals. As a result, when any of the monitor circuits2(i) is determined to be defective, the corresponding G(i) signal shifts to the LOW state and, at the time t7, the C(i) signal is disabled, i.e., fixed to 0.

Thereafter, all the C(i) signals are sent to the summing circuit4, and the summing circuit4outputs the average value of the effective C(i) signals.

Thus, by using the semiconductor integrated circuit device1according to the first embodiment of the present invention, the value obtained by averaging performance variations in the chip can be detected. This is because the multiple monitor circuits2(i) disposed at mutually different locations in the chip perform performance evaluation independently of each other. In addition, since the monitor circuits2(i) remaining after the exclusion of the monitor circuits2(i) each showing an abnormal value perform monitor operations, the performance of the chip can be monitored with high accuracy.

Note that, heretofore, the average value of the C(i) signals outputted from the multiple monitor circuits2(i) has been used, but it is also possible to use the minimum value of the C(i) signals instead. For this purpose, the configuration of the summing circuit4may be modified appropriately as follows.

FIG. 7is a block diagram showing another configuration of the summing circuit4according to the first embodiment of the present invention. A description will be given of the components of the summing circuit4ofFIG. 7. The summing circuit4ofFIG. 7includes (N−1) comparison circuits41(i) and (N−1) selectors42(i). Each of the (N−1) comparison circuits41(i) includes first and second input portions and an output portion. Each of the (N−1) selectors42(i) includes first to third input portions and an output portion.

A description will be given of coupling relations between the components of the summing circuit4ofFIG. 7. The first and second input portions of each of the first comparison circuits41(i) respectively receive the C(1) signal and the C(2) signal. The first, second, and third input portions of the first selector42(1) respectively receive the C(1) signal, the C(2) signal, and an output signal from the first comparison circuit41(1).

The first input portion of the second comparison circuit41(2) receives an output signal from the first selector42(1). The second input portion of the second comparison circuit41(2) receives the C(3) signal. The first input portion of the second selector42(2) receives an output signal from the first selector42(1). The second input portion of the second selector42(2) receives the C(3) signal. The third input portion of the second selector42(2) receives an output signal from the second comparison circuit41(2).

A generalized description will be given below in the range of 2<i<N−1. The first input portion of the i-th comparison circuit41(i) receives an output signal from the (i−1)-th selector42(i−1). The second input portion of the i-th comparison circuit41(i) receives the C(i+1) signal. The first input portion of the i-th selector42(i) receives an output signal from the (i−1)-th selector42(i−1). The second input portion of the i-th selector42(i) receives the C(i+1) signal. The third input portion of the i-th selector42(i) receives an output signal from the second comparison circuit41(i).

A description will be given of an operation of the summation circuit4ofFIG. 7. Each of the (N−1) comparison circuits41(i) compares the two signals inputted thereto, and outputs a signal representing the smaller one of the two signals as the result thereof toward the selector42(i) having the same number. Each of the (N−1) selectors42(i) responds to the signal inputted from the corresponding comparison circuit41(i) to the third input portion thereof, and outputs the smaller one of the two signals inputted to the first and second input portions thereof toward the comparison circuit41(i+1) having the next number. However, each of the selectors42(i) needs to ignore the C(i) signal that has been disabled to satisfy C(i)=0, and select the other C(i) signal.

In the case of using the summing circuit4ofFIG. 7, the semiconductor integrated circuit device1is allowed to detect the worst performance of the chip as the Coutsignal. Alternatively, each of the selectors42(i) may also be adapted to output the larger value based on an output of the corresponding comparison circuit41(i). This allows the maximum performance of the chip to be detected.

Second Embodiment

FIG. 8is a block diagram showing a configuration of the semiconductor integrated circuit device1according to a second embodiment of the present invention. The semiconductor integrated circuit device ofFIG. 8is equivalent to the semiconductor integrated circuit device of the first embodiment of the present invention to which the following modification is added. That is, the summing circuit4does not include the C(i) signal input portions, and the C(i) signal output portions of the monitor circuits2(i) are coupled only to the C(i) signal input portion of the control circuit3. The control circuit3does not include the RESET signal output portion, and each of the monitor circuits2(i) does not include the RESET signal input portion. The control circuit3includes a CNT signal output portion, and the summing circuit4includes a CNT signal input portion. The CNT signal output portion of the control circuit3is coupled to the CNT signal input portion of the summing circuit4. The other components, coupling relations, and operations are the same as in the case of the first embodiment of the present invention, and therefore a further description is omitted.

FIG. 9is a block diagram showing a configuration of each of the monitor circuits2(i) according to the second embodiment of the present invention. The monitor circuit2(i) ofFIG. 9is equivalent to each of the monitor circuits2(i) according to the first embodiment of the present invention to which the following modification is added. That is, the counter203is omitted, and the ROOUT signal output portion of the delay element204is coupled to the first input portion of the AND gate201. The other components, coupling relations, and operations in the monitor circuit2(i) ofFIG. 9are the same as in the case of the first embodiment of the present invention, and therefore a further description is omitted.

FIG. 10is a block diagram showing a configuration of the control circuit3according to the second embodiment of the present invention. The control circuit3ofFIG. 10is equivalent to the control circuit3according to the first embodiment of the present invention to which the following modification is added. That is, between the output portion of the selector321and the second input portion of the comparison circuit322, a counter325is additionally provided. Here, the counter325includes a first input portion, a RESET signal input portion, and an output portion, similarly to the counter203according to the first embodiment of the present invention. The output portion of the selector321is coupled to the first input portion of the counter325. The RESET signal output portion of the control signal generation circuit31is coupled to the RESET signal input portion of the counter325. The output portion of the counter325is coupled to the second input portion of the comparison circuit322and to the CNT signal output portion of the control circuit3.

The counter325has two functions. The first function of the counter325is the measurement of the number of times that the ROOUT signal outputted from the ring oscillator202shifts to the HIGH state, similarly to the function of the counter203according to the first embodiment of the present invention. The counter325performs the first function, while checking the effectiveness of each of the C(i) signals, i.e., whether or not MIN<C(i)<MAX is satisfied. The second function of the counter325is the calculation of the total sum of the C(i) signals. After the effectiveness of each of the C(i) signals is checked, for the calculation of the average value of the effective C(i) signals, the total sum thereof is needed. The control signal generation circuit31successively specifies only the C(i) signals corresponding to all the G(i) signals that are in the HIGH state with the SEL signal, thereby allowing the counter325to calculate the total sum of the effective C(i) signals. The counter325outputs the total sum of the effective C(i) signals as a CNT signal toward the summing circuit4. The other components, coupling relations, and operations are the same as in the case of the first embodiment of the present invention, and therefor a further description is omitted.

The summing circuit4according to the second embodiment of the present invention is equivalent to the summing circuit4according to the first embodiment of the present invention from which the comparison circuits41(i) and the selectors42(i) are removed. That is, the summing circuit4according to the second embodiment of the present invention is equivalent to the averaging circuit401according to the first embodiment of the present invention. The configuration thereof is so simple that the depiction thereof is omitted. The summing circuit4according to the second embodiment of the present invention, i.e., the averaging circuit401receives the CNT signal at the first input portion thereof. The other coupling relations and operations are the same as in the first embodiment, and therefor a further description is omitted.

FIG. 11is a time chart for illustrating an operation of the semiconductor integrated circuit device1according to the second embodiment of the present invention. Along the time chart ofFIG. 11, an example of the operation of the semiconductor integrated circuit device1according to the second embodiment of the present invention will be described.

The time chart ofFIG. 11shows graphs representing respective time variations in the RESET signal, the ENABLE signal, the SEL signal, and the CNT signal in a descending order. In the time chart ofFIG. 11, the abscissa axis represents elapsed time, and the ordinate axis represents the intensity of each of the signals.

The time t0shows an initial state. At the time t0, RESET=0 and ENABLE=0 are satisfied. At this time, the G(i) signal not shown is preferably in the HIGH state.

At the time t1, the RESET signal shifts to the HIGH state, and returns to the LOW state at the time t2. During the time period therebetween, the counter325is reset to satisfy CNT=0.

Before the time t3, the control signal generation circuit outputs the SEL signal for selecting any of the monitor circuits2(i).

At the time t3, the ENABLE signal shifts the HIGH state, and returns to the LOW state at the time t4. During the time period from the time t3to the time t4, the ring oscillator202oscillates in each of the monitor circuit2(i). The ROOUT signal outputted from the ring oscillator202is outputted as the C(i) signal from the monitor circuit2(i) via the AND gate201to which the G(i) signal in the HIGH state is inputted. At this time, only the C(i) signal outputted from the one monitor circuit2(i) selected with the SEL signal has the pulse number thereof measured by the counter325.

At the time t4, the oscillation of the ring oscillator202ends, and the number of counts of the counter325becomes T/TROSC, where T represents the time period from the time t3to the time t4, and TROSC represents the oscillation period of the ring oscillator202.

After the time t4, the control signal generation circuit31switches the LOW state and the HIGH state of the CMP signal to allow the comparison circuit322to compare the C(i) signal with MIN or MAX. When the result of MAX<C(i) or C(i)<MIN is obtained, the monitor circuit2(i) that has outputted the C(i) signal is determined to be defective. To disable the monitor circuit2(i) determined to be defective, the control signal generation circuit31brings the G(i) signal into the LOW sate.

Subsequently, the control signal generation circuit31appropriately changes the SEL signal to repeat the defect detection described above for each of the monitor circuits2(i). For example, the times t5and t6respectively correspond to the times t1and t3.

Next, at the time t7, the control signal generation circuit31brings the RESET signal into the HIGH state to reset the counter325. Note that, at the time t8and thereafter, there is no need to bring the RESET signal into the HIGH state. Thereafter, the control signal generation circuit31selects each of the monitor circuits2(i) one by one with the SEL signal, while repeatedly switching the HIGH state and the LOW state of the ENABLE signal. While the ENABLE signal remains in the HIGH state only for the same period T as mentioned above, each of the ring oscillators202oscillates, and the counter325counts the pulse number of the C(i) signal of the monitor circuit selected with the SEL signal. Finally, the pulse number of the C(i) signal of each of the monitor circuits2(i) determined to be effective, i.e., the G(i) signal of which remains in the HIGH state is counted. During the counting, the counter325is not reset halfway so that the CNT signal outputted from the counter235becomes equal to the total sum of the pulse numbers of the C(i) signals of the effective monitor circuits2(i).

Finally, the summing circuit4divides the value of the CNT signal by the value of the M signal representing the total sum of the effective monitor circuits2(i) to provide the average value of the C(i) signals of the effective monitor circuits2(i). Here, in the same manner as in the first embodiment, a shift operation may also be performed instead of the division by targeting only those of the M effective monitor circuits2(i) the total number of which is a power-of-number, and ignoring the other effective monitor circuits2(i).

In the second embodiment of the present invention also, in the same manner as in the first embodiment of the present invention, the monitor circuits disposed at multiple locations in a chip can allow a value obtained by averaging performance variations in the chip to be detected. In the same manner as in the first embodiment of the present invention, since the monitor circuits2(i) remaining after the exclusion of the monitor circuits2(i) each showing an abnormal value perform monitor operations, the performance of the chip can be monitored with high accuracy. Additionally, in the second embodiment of the present invention, the number of the counter325that is needed is only one. Therefore, compared with the case of the first embodiment of the present invention, the area of the semiconductor integrated circuit device1can be saved.

Third Embodiment

FIG. 12is a block diagram showing a configuration of the semiconductor integrated circuit device1according to a third embodiment of the present invention. The semiconductor integrated circuit device1ofFIG. 12is equivalent to the semiconductor integrated circuit device1according to the first embodiment of the present invention to which the following modification is added. That is, the control circuit does not include the M signal output portion, and the summing circuit4does not include the M signal input portion. The control circuit3includes a Coutsignal input portion, and the Coutsignal output portion of the summing circuit4is coupled to the Coutsignal input portion of the control circuit3. The other components, coupling relations, and operations are the same as in the case of the first embodiment of the present invention, and therefore a further description is omitted.

A configuration of each of the monitor circuits2(i) according to the third embodiment of the present invention is the same as in the case of the first embodiment of the present invention, and therefore a further description and depiction are omitted.

FIG. 13is a block diagram showing a configuration of the control circuit3according to the third embodiment of the present invention. The control circuit3ofFIG. 13is equivalent to the control circuit3according to the first embodiment of the present invention to which the following modification is added. That is, the control circuit3according to the third embodiment of the present invention further includes a shifter324A and a shifter324B. The shifter324A includes a Coutsignal input portion and a MAX signal output portion. The shifter324B includes a Coutsignal input portion and a MIN signal output portion. The register323further includes a MAX signal input portion and a MIN signal input portion.

The Coutsignal input portions of the shifter324A and the shifter324B are coupled to the Coutsignal input portion of the control circuit3. The MAX signal input portion of the shifter324A is coupled to the MAX signal input portion of the register323. The MIN signal input portion of the shifter324B is coupled to the MIN signal input portion of the register323.

In the first and second embodiments of the present invention, the values of the MAX signal and the MIN signal stored in the register323are fixed values. However, in the third embodiment of the present invention, the values of the MAX signal and the MIN signal vary in accordance with the value of the Coutsignal outputted from the summing circuit4.

Here, by way of example, it is assumed that MAX=2×Coutand MIN=Cout/2 are satisfied. Since the Coutsignal has a binary value, the shifter324A can generate the MAX signal by shifting the Coutsignal to a 1-digit higher-order position. Likewise, the shifter324B can generate the MIN signal by shifting the Coutsignal to a 1-digit lower-order position. The other components, coupling relations, and operations are the same as in the case of the first embodiment of the present invention, and therefore a further description is omitted.

Note that the values of the MAX signal and the MIN signal may also be other than double the value and half the value of the Coutsignal. However, in that case, the shifter324A and the shifter324B need to be replaced with typical arithmetic circuits or the like.

FIG. 14is a time chart for illustrating an operation of the semiconductor integrated circuit device1according to the third embodiment of the present invention. The time chart ofFIG. 14includes graphs representing respective time variations in the RESET signal, the ENABLE signal, the ROOUT signal, the C(i) signal, the G(i) signal, the SEL signal, the CMP signal, and the Coutsignal in a descending order. In each of the graphs of the time chart ofFIG. 14, the horizontal direction indicates elapsed time, and the vertical direction indicates the intensity of each of the signals.

In the time chart ofFIG. 14, an operation from the time t0to the time t7is the same as in the case of the first embodiment of the present invention. During the time period therebetween, when any of the monitor circuits2(i) is determined to be defective to satisfy G(i)=0, the value of the Coutsignal also undergoes a change so that the operation from the time t0to the time t7is repeated from the time t8. Finally, the value of the Coutsignal when no more change occurs is assumed to the average value of the values of the C(i) signals of the effective monitor circuits.

Thus, by using the semiconductor integrated circuit device1according to the third embodiment of the present invention, the value obtained by averaging performance variations in the chip can be detected. This is because the multiple monitor circuits2(i) disposed at mutually different locations in a chip perform performance evaluation independently of each other. In addition, since the monitor circuits2(i) remaining after the exclusion of the monitor circuits2(i) each showing an abnormal value perform monitor operations, the performance of the chip can be monitored with high accuracy. Moreover, since a threshold value for determining a defect is calculated from the average value of the values of the signals from the individual monitor circuits, there is no need to predetermine the threshold value.

Fourth Embodiment

FIG. 15is block diagram showing a configuration of the semiconductor integrated circuit device1according to a fourth embodiment of the present invention. A description will be given of the components of the semiconductor integrated circuit device1ofFIG. 15. The semiconductor integrated circuit device1ofFIG. 15includes a monitor circuit2and the control circuit3. The monitor circuit2includes a RESET signal input portion, an ENABLE signal input portion, m BPSEL(i) signal input portions, and a CNT signal output portion. The control circuit3includes a CNT signal input portion, a RESET signal output portion, an ENABLE signal output portion, and m BPSEL(i) signal output portions. Note that m is a predetermined integer of 2 or more, and the meaning thereof will be described later. Here, “i” is assumed to be any integer included in the range of 1 to m.

The semiconductor integrated circuit device1ofFIG. 15preferably further includes the summing circuit4not shown. A configuration of the summing circuit4is preferably the same as in the case of the third embodiment of the present invention.

A description will be given of coupling relations in the semiconductor integrated circuit device ofFIG. 15. The RESET signal output portion, the ENABLE signal output portion, and the m BPSEL(i) signal output portions of the control circuit3are respectively coupled to the RESET signal input portion, the ENABLE signal input portion, and the m BPSEL(i) signal input portions of the monitor circuit2. The CNT signal output portion of the monitor circuit2is coupled to the CNT signal input portion of the control circuit3.

The CNT signal output portion of the monitor circuit2is preferably coupled to the CNT signal input portion of the summing circuit4not shown.

FIG. 16is a block diagram showing a configuration of the monitor circuit2according to the fourth embodiment of the present invention. A description will be given of the components of the monitor circuit2ofFIG. 16. The monitor circuit2ofFIG. 16includes the ring oscillator202and the counter203. The ring oscillator202includes an ENABLE signal input portion, the NAND gate205, m delay elements20(i), m rear selectors21(i), m front selectors22(i), and a ROOUT signal output portion. The counter203includes a ROOUT signal input portion, a RESET signal input portion, and a CNT signal output portion. The NAND gate205includes an ENABLE signal input portion, a ROOUT signal input portion, and an output portion. Each of the front selectors22(i) includes a first input portion, a BPSEL (i) signal input portion, and first and second output portions. Each of the delay elements20(i) includes an input portion and an output portion. Each of the rear selectors21(i) includes first and second input portions, a BPSEL (i) signal input portion, and an output portion.

A description will be given of coupling relations in the monitor circuit2ofFIG. 16. The ENABLE signal input portion of the monitor circuit2is coupled to the ENABLE signal input portion of the ring oscillator202. The ENABLE signal input portion of the ring oscillator202is coupled to the ENABLE signal input portion of the NAND gate205. The output portion of the NAND gate205is coupled to the first input portion of the first front selector22(1). The first output portion of the first front selector22(1) is coupled to the first input portion of the first rear selector21(1). The second output portion of the first front selector22(1) is coupled to the input portion of the first delay element20(1). The output portion of the first delay element20(1) is coupled to the second input portion of the first rear selector21(1). The output portion of the first rear selector21(1) is coupled to the first input portion of the second front selector22(2).

In the same manner as described above, a generalized description will be given below using a suffix i The first output portion of the i-th front selector22(i) is coupled to the first input portion of the i-th rear selector21(i). The second output portion of the i-th front selector22(i) is coupled to the input portion of the i-th delay element20(i). The output portion of the i-th delay element20(i) is coupled to the second input portion of the i-th rear selector21(i). The output portion of the i-th rear selector21(i) is coupled to the first input portion of the (i+1)-th front selector22(i+1). The respective BPSEL(i) signal input portions of the i-th front selector22(i) and the i-th rear selector21(i) are each coupled to the BPSEL(i) signal input portion of the monitor circuit2.

Finally, the first output portion of the m-th front selector22(m) is coupled to the first input portion of the m-th rear selector21(m). The second output portion of the m-th front selector22(m) is coupled to the input portion of the m-th delay element20(m). The output portion of the m-th delay element20(m) is coupled to the second input portion of the m-th rear selector21(m). The output portion of the m-th rear selector21(m) is coupled to the ROOUT signal output portion of the ring oscillator202and to the ROOUT signal input portion of the NAND gate205. The ROOUT signal output portion of the ring oscillator202is coupled to the ROOUT signal input portion of the counter203. The RESET signal input portion of the counter203is coupled to the RESET signal input portion of the monitor circuit2. The CNT signal output portion of the counter203is coupled to the CNT signal output portion of the semiconductor integrated circuit device1.

A description will be given of an operation of the monitor circuit2ofFIG. 16. Between each of the front selectors22(i) and the corresponding rear selector21(i), there are a first path passing through the corresponding delay element20(i) and a second path bypassing the delay element20(i). The front selector22(i) and the rear selector21(i) switch the couplings of the input portions and the output portions thereof in accordance with a BPSEL(i) signal to thereby switch the first and second paths. Specifically, when the BPSEL(i) signal is in the HIGH state, the path passing through the delay element20(i) is selected and, when the BPSEL(i) signal is in the LOW state, the delay element20(i) is bypassed.

As will be described later, the BPSEL(i) signal shifts to the LOW state with only one i at a time, and shifts to the HIGH state with the other i's. That is, the delay element20(i) bypassed at a time is only one. When the ENABLE signal shifts to the HIGH state, the ring oscillator202oscillates in a state where the remaining (m−1) delay elements20(i) are coupled in series.

The counter203counts the pulse number of the ROOUT signal outputted from the ring oscillator202. The count of the counter203is reset by the shifting of the RESET signal to the HIGH state.

FIG. 17is a block diagram showing a configuration of the control circuit3according to the fourth embodiment of the present invention. The control circuit3ofFIG. 17is equivalent to the control circuit3according to the first embodiment of the present invention to which the following modification is added. That is, the control signal generation circuit31does not include the SEL signal output portion or the G(i) signal output portion, but includes a BPSEL(i) signal output portion instead. The defect detection circuit32does not include the selector321. The comparison circuit322does not include the second input portion, but includes a CNT signal input portion instead.

The control signal generation circuit31switches the BPSEL(i) signal to thereby successively switch the delay element20(i) to be bypassed. The comparison circuit322receives the CNT signal, compares the MAX signal or the MIN signal inputted thereto from the selector320with the CNT signal, and outputs the result thereof toward the control signal generation circuit31. The other components, coupling relations, and operations of the control circuit3ofFIG. 17are the same as in the case of the first embodiment of the present invention, and therefore a further description is omitted.

FIG. 18is a time chart for illustrating an operation of the semiconductor integrated circuit device1according to the fourth embodiment of the present invention. The time chart ofFIG. 18shows the respective graphs of the RESET signal, the ENABLE signal, the ROOUT signal, the CNT signal, the BPSEL(i) signal, and the CMP signal in a descending order. In each of the graphs ofFIG. 18, the abscissa axis represents elapsed time, and the ordinate axis represents the intensity of each of the signals.

The time t0shows an initial state, in which RESET=0 and ENABLE=0 are satisfied. At the time t1, the RESET signal shifts to the HIGH state to reset the count of the counter203. At the time t2, the RESET signal returns to the LOW state.

During the time period T from the time t3to the time t4, the ENABLE signal shifts to the HIGH state, and the ring oscillator202oscillates only during the time period. When the oscillation period of the ring oscillator202is assumed to be TROSC, the count of the counter203at the time t4becomes a quotient obtained by dividing T by TROSC. However, in the same manner as in the case of the first embodiment of the present invention, the remainder of the division is ignored, and the quotient will be hereinafter represented by T/TROSC.

The count of the counter203is sent as the CNT signal to the comparison circuit322. The selector320transmits either of the MAX signal and the MIN signal supplied from the register323to the comparison circuit322. When the CMP signal outputted from the control signal generation circuit31is in the LOW state, the MIN signal is transmitted to the comparison circuit322. When the CMP signal outputted from the control signal generation circuit31is in the HIGH state, the MAX signal is transmitted to the comparison circuit322. The comparison circuit322compares the value of the MAX signal or the MIN signal with the value of the CNT signal, and outputs the result thereof toward the control signal generation circuit31.

Here, when MIN>CNT or CNT>MAX is obtained as the comparison result, it follows that the delay elements20(i) that have operated as the ring oscillator202include a defective item. In this case, the control signal generation circuit31switches the value of the PSEL(i) signal to thereby switch the delay element20to be bypassed in the ring oscillator202.

Thereafter, until the comparison result satisfies MIN<CNT<MAX, the operation from the time t1to the time t6is repeated, while the delay element20(i) to be bypassed is switched.

The time t7shows a time point when the BPSEL(i) signal no more switches, i.e., when the comparison result satisfies MIN<CNT<MAX. The value of the CNT signal at this time serves as a monitor output.

Thus, by using the semiconductor integrated circuit device1according to the fourth embodiment of the present invention, it is possible to bypass any of the multiple delay elements20(i) included in the ring oscillator202of the monitor circuit2that shows an abnormal delay time. As a result, the performance of a chip can be monitored with high accuracy.

FIG. 19is a block diagram showing another configuration of the monitor circuit2according to the fourth embodiment of the present invention. The monitor circuit2ofFIG. 19is equivalent to the monitor circuit2ofFIG. 17according to the fourth embodiment of the present invention to which the following modification is added. That is, the front selectors22(i) are removed, and the output portion of the NAND gate205and the output portion of each of the rear selectors21(i) except for that in the rearmost stage are constantly coupled to the input portions of the selector (i+1) and the delay element (i+1) each in the frontmost stage or in the next frontmost stage. The other components, coupling relations, and operations are the same as in the case ofFIG. 17, and therefore a further description is omitted.

In the case ofFIG. 19, the bypassed delay element20(i) also operates so that power consumption increases accordingly. However, a chip area can be reduced by an area corresponding to the omitted front selectors22(i). Further, as the total number m of the delay elements20(i) is larger, the proportion of the overhead of power consumption can be reduced.

Note that, in the description given above, the number of the delay element20(i) that can be bypassed at a time is assumed to be one. However, it is also possible to provide a configuration in which the control signal generation circuit31outputs BPSEL(i) as necessary to thereby allow multiple the delay elements20(i) to be bypassed.

Fifth Embodiment

FIG. 20is a block diagram showing a configuration of the semiconductor integrated circuit device1according to a fifth embodiment of the present invention. The semiconductor integrated circuit device1ofFIG. 20is equivalent to the semiconductor integrated circuit device1according to the fourth embodiment of the present invention to which the following modification is added. That is, the control circuit further includes a TEST signal output portion and a SEL signal output portion. The monitor circuit2further includes a TEST signal input portion and a SEL signal input portion. The TEST signal output portion and the SEL signal output portion of the control circuit3are respectively coupled to the TEST signal input portion and the SEL signal input portion of the monitor circuit2. The other components, coupling relations, and operations are the same as in the case of the fourth embodiment of the present invention, and therefore a further description is omitted.

Note that, in the semiconductor integrated circuit device1according to the fifth embodiment of the present invention also, in the same manner as in the case of the fourth embodiment of the present invention, the same summing circuit4as in the third embodiment of the present invention, which is not shown, is preferably coupled in the state subsequent to the CNT signal output portion of the monitor circuit2.

FIG. 21is a block diagram showing a configuration of the monitor circuit2according to the fifth embodiment. A description will be given of the components of the monitor circuit2ofFIG. 21. The monitor circuit2ofFIG. 21includes the NAND gate205, N ring oscillators23(i), the selector201, and the counter203. Note that, here, “i” also indicates an integer included in the range of 1 to N.

The N ring oscillators23(i) include respective NAND gates205(i), the respective front selectors22(i), and the respective rear selectors21(i).

Each of the NAND gate205and the NAND gates205(i) has a first input portion, an ENABLE signal input portion, and an output portion. Each of the front selectors22(i) includes first and second input portions, a TEST signal input portion, and an output portion. Each of the delay elements20(i) includes an input portion and an output portion. Each of the rear selectors21(i) includes first and second input portions, a BPSEL(i) signal input portion, and an output portion. The selector201includes N i-th input portions, a SEL signal input portion, and an output portion. The counter203includes a first input portion, a RESET signal input portion, and a CNT signal output portion.

A description will be given of coupling relations in the monitor circuit2ofFIG. 21. The ENABLE signal input portions of the NAND gate205and the NAND gates205(i) are each coupled to the ENABLE signal input portion of the monitor circuit2. The SEL signal input portion of the selector201is coupled to the ENABLE signal input portion of the monitor circuit2. The RESET signal input portion and the CNT signal output portion of the counter203are respectively coupled to the RESET signal input portion and the CNT signal output portion of the monitor circuit2. The respective ENABLE signal input portions of the N NAND gates205(i) are each coupled to the ENABLE signal input portion of the monitor circuit2. The respective TEST signal input portions of the N front selectors22(i) are each coupled to the TEST signal input portion of the monitor circuit2. The respective BPSEL(i) signal input portions of the N rear selectors21(i) are each coupled to the BPSEL(i) signal input portion of the monitor circuit2.

The output portion of the NAND gate205is coupled to the first input portion of the first front selector22(1). The output portion of the first NAND gate205(1) is coupled to the second input portion of the first front selector22(1). The output portion of the first front selector22(1) is coupled to the input portion of the first delay element20(1) and to the first input portion of the first rear selector21(1). The output portion of the first delay element20(1) is coupled to the second input portion of the first rear selector21(1). The output portion of the second rear selector21(2) is coupled to the first input portion of the first NAND gate205(1), to the first input portion of the selector201, and to the first input portion of the second front selector22(2).

In the same manner as described above, a generalized description will be given below using i included in the range of 2 to N−1. The output portion of the i-th NAND gate205(i) is coupled to the second input portion of the i-th front selector22(i). The output portion of the i-th front selector22(i) is coupled to the input portion of the i-th delay element20(i) and to the first input portion of the i-th rear selector21(i). The output portion of the i-th delay element20(i) is coupled to the second input portion of the i-th rear selector21(i). The output portion of the i-th rear selector21(i) is coupled to the first input portion of the i-th NAND gate205(i), to the first input portion of the selector201, and to the first input portion of the (i+1)-th front selector22(i+1).

Finally, the output portion of the N-th NAND gate205(N) is coupled to the second input portion of the N-th front selector22(N). The output portion of the N-th front selector22(N) is coupled to the input portion of the N-th delay element20(N) and to the first input portion of the N-th rear selector21(N). The output portion of the N-th delay element20(N) is coupled to the second input portion of the N-th rear selector21(N). The output portion of the N-th rear selector21(N) is coupled to the first input portion of the N-th NAND gate205(N), to the first input portion of the selector201, and to the first input portion of the first front selector22(1). The output portion of the selector201is coupled to the first input portion of the counter203.

A description will be given of an operation of the monitor circuit2ofFIG. 21. The monitor circuit2ofFIG. 21has two states switched in accordance with a TEST signal, i.e., a test state and a monitor state. In the semiconductor integrated circuit device1according to the fifth embodiment of the present invention, the test state and the monitor state are defined as follows.

First, when the TEST signal is in the HIGH state, the second input portion and the output portion of each of the front selectors22(i) become conductive, and the output portion of the corresponding delay element20(i) is coupled to the input portion via the corresponding NAND gate205(i) so that the N ring oscillators23(i) independently operate. This state of the monitor circuit2ofFIG. 21is called the test state.

Next, when the TEST signal is in the LOW state, the first input portion and the output portion of each of the front selectors22(i) become conductive so that the N delay elements20(i) are coupled in series in a numerical order. The N delay elements20(i) are further coupled into ring shape via the NAND gate205to operate as a single ring oscillator. This state of the monitor circuit2ofFIG. 21is called a monitor state.

In the monitor state, each of the N delay elements20(i) is independently bypassed in accordance with the corresponding BPSEL(i) signal. That is, when the BPSEL(i) signal is in the LOW state, the first input portion and the output portion of the corresponding rear selector21(i) are coupled, i.e., the output portion of the corresponding front selector22(i) is coupled to the output portion of the corresponding rear selector21(i). Conversely, when the BPSEL(i) is in the HIGH state, the second input portion and the output portion of the corresponding rear selector21(i) are coupled, i.e., the output portion of the corresponding delay element20(i) is coupled to the corresponding rear selector21(i).

FIG. 22is a block diagram showing a configuration of the control circuit3according to the fifth embodiment of the present invention. The control circuit3ofFIG. 22is equivalent to the control circuit3according to the fourth embodiment of the present invention to which the following modification is added. That is, the control signal generation circuit31further includes a SEL signal output portion and a TEST signal output portion, and further generates a SEL signal and the TEST signal. The other components, coupling relations, and operations in the control circuit3ofFIG. 22are the same as in the case of the fourth embodiment of the present invention, and therefore a further description is omitted.

FIG. 23is a flow chart for illustrating an operation of the semiconductor integrated circuit device1according to the fifth embodiment of the present invention. The flow chart ofFIG. 23has graphs representing respective time variations in the RESET signal, the ENABLE signal, the ROOUT signal, the CNT signal, the BPSEL(i) signal, the SEL signal, and the TEST signal in a descending order. In each of the graphs, the abscissa axis represents elapsed time, and the ordinate axis represents the intensity of each of the signals.

The time t0shows an initial state, in which RESET=0, ENABLE=0, and TEST=1 are satisfied. Hereinafter, until the TEST signal shifts to the LOW state at the time t8, the semiconductor integrated circuit device1according to the fifth embodiment of the present invention operates in the test state. Each of the i's included in the range of 1 to N satisfies BPSEL(i)=1.

At the time t1, the RESET signal shifts to the HIGH state to reset the count of the counter203. At the time t2, the RESET signal returns to the LOW state.

At the time t3, the value of the SEL signal becomes 1. This specifies the first ring oscillator23(1) from among the N ring oscillators23(i). During the time period T from the time t3to the time t4, the ENABLE signal is in the HIGH state and, only during the time period, the ring oscillator23(1) oscillates. Here, it may also be possible that the other ring oscillators23(i) simultaneously oscillate.

An output signal from the ring oscillator23(1) is supplied to the counter203via the selector201. The counter203counts the number of oscillations in the output signal from the ring oscillator23(1), and outputs the counted number as the CNT signal. Here, when the oscillation period of the ring oscillator23(1) is assumed to be TROSC1, the value of the CNT signal at the time t5becomes a quotient obtained by dividing T by TROSC1. However, in the same manner as in the case of the first embodiment of the present invention, the remainder of the division is ignored, and the quotient will be hereinafter represented by T/TROSC1.

The CNT signal is sent to the defect detection circuit32, and compared with each of the MAX signal and the MIN signal in the same manner as in the other embodiments of the present invention. When the value of the CNT signal is determined to be defective, at the time t6, the BPSEL(1) signal shifts to the LOW state.

Also at the time t6, the value of the SEL signal becomes 2 to specify the second ring oscillator23(2). Subsequently, in the same manner as described above, the SEL signal successively switches and, for each of the N ring oscillators23(i), the operation from the time t1to the time t6is repeated.

When the determination for each of the ring oscillators23(i) is completed, at the time t7, the value of the SEL signal is set to N. Thereafter, at the time t8, the TEST signal shifts to the LOW state, and the semiconductor integrated circuit device1according to the fifth embodiment of the present invention shifts to the monitor state. During the period from the time t9to the time t10, for one ring oscillator with which BPSEL(i) is in the HIGH state, i.e., in which all the delay elements20(i) determined to be effective are coupled in series, the operation from the time t1to the time t5is performed.

At the time t10and thereafter, the CNT signal outputted from the counter203and the M signal representing the number of the BPSEL(i) signals in the HIGH state, i.e., the total number of the effective delay elements20(i) are supplied to the summing circuit4not shown. The summing circuit4calculates and outputs CNT/M.

Thus, by using the semiconductor integrated circuit device1according to the fifth embodiment of the present invention, any of the delay elements20(i) showing an abnormal delay time is excluded from the ring oscillators included in the monitor circuit2. This allows the performance of a chip to be monitored with high accuracy. In addition, in the fifth embodiment of the present invention, each of the delay elements20(i) is individually determined in advance to be normal or defective. Therefore, even when there are the multiple delay elements20(i) each showing an abnormal characteristic, it is possible to easily detect and exclude a defective portion.

FIG. 24is a block diagram showing another configuration of the monitor circuit2according to the fifth embodiment of the present invention. The monitor circuit2ofFIG. 24is equivalent to the monitor circuit2ofFIG. 21to which the following modification is added. That is, the counter203disposed in the stage subsequent to the selector201is removed and, instead, N counters230(i) are disposed between the respective output portions of the ring oscillators23(i) and the input portion of the selector201.

The arrangement allows delay times in the N delay elements20(i) to be simultaneously measured.FIG. 25is a time chart for illustrating an operation of the semiconductor integrated circuit device1according to the fifth embodiment of the present invention in the case of using the monitor circuit2ofFIG. 24. The time chart ofFIG. 25is equivalent to the time chart ofFIG. 23to which the following modification is added. That is, in the case of the time chart ofFIG. 25, from the time t3to the time t4, ENABLE=1 is satisfied. Then, from the time t6to the time t7, mere switching of the SEL signal allows the individual delay elements20(i) to be successively subjected to defect determination to allow a reduction in evaluation time.

The other components, coupling relations, and operations of the monitor circuit2ofFIG. 24and in the time chart ofFIG. 25are the same as in the cases ofFIGS. 21 and 23, and therefore a further description is omitted.

Sixth Embodiment

FIG. 26is a block diagram showing a configuration of the semiconductor integrated circuit device1according to a sixth embodiment of the present invention. The semiconductor integrated circuit device1ofFIG. 26is equivalent to the semiconductor integrated circuit device1according to the first embodiment of the present invention to which the following modification is added. That is, the semiconductor integrated circuit device1according to the sixth embodiment of the present invention includes a chip, a voltage control circuit5, and a voltage supply circuit6. Here, the chip includes the components of the semiconductor integrated circuit device1according to the first embodiment of the present invention.

The chip includes a voltage input portion and a Coutsignal output portion. The voltage control circuit5includes a Coutsignal input portion and a control signal output portion. The voltage supply circuit6includes a control signal input portion and a voltage output portion.

The Coutsignal output portion of the summing circuit4is coupled to the Coutsignal output portion of the chip. The Coutsignal output portion of the chip is coupled to the Coutsignal input portion of the voltage control circuit5. The control signal output portion of the voltage control circuit5is coupled to the control signal input portion of the voltage supply circuit6. The voltage output portion of the voltage supply circuit6is coupled to the voltage input portion of the chip. The voltage input portion of the chip is coupled to the voltage input portion of each of the components in the chip, which is not shown.

The other components and coupling relations of the semiconductor integrated circuit device1according to the sixth embodiment of the present invention are the same as in the case of the first embodiment of the present invention, and therefore a further description is omitted.

FIG. 27is a block diagram showing a configuration of the voltage control circuit5according to the sixth embodiment of the present invention. A description will be given of the components of the voltage control circuit5ofFIG. 27. The voltage control circuit5ofFIG. 27includes a register52and a comparison circuit51.

The register52includes a reference value signal output portion. The comparison circuit51includes a reference value signal input portion, a Coutsignal input portion, and a control signal output portion.

A description will be given of coupling relations in the voltage control circuit5ofFIG. 27. The reference value signal output portion of the register52is coupled to the reference value signal input portion of the comparison circuit51. The Coutsignal input portion of the comparison circuit51is coupled to the Coutsignal input portion of the voltage control circuit5. The control signal output portion of the comparison circuit51is coupled to the control signal output portion of the voltage control circuit5.

A description will be given of an operation of the voltage control circuit5ofFIG. 27. The register52stores therein a reference value for a monitor output. As an example of the reference value, there is used a value to be outputted as the CNT signal from the summing circuit4when a process for the chip in which the monitor circuits2(i) are mounted, a voltage supplied to the chip, the temperature of the chip, and the like satisfy specified conditions.

The comparison circuit51receives a reference value signal showing the reference value and the CNT signal, compares the magnitudes of the two signals, and outputs the result thereof as a control signal. Here, when the value of the CNT signal is larger than the reference value, the comparison circuit51according to the sixth embodiment of the present invention generates a control signal for reducing a power source voltage VDD, and outputs the control signal toward the power supply circuit6. Conversely, when the value of the CNT signal is smaller than the reference value, the comparison circuit51according to the sixth embodiment of the present invention generates a control signal for increasing the power source voltage VDD, and outputs the control signal toward the power supply circuit6. The power supply circuit6increases or reduces the power source voltage VDDin accordance with the control signal inputted thereto from the comparison circuit51.

The CNT signal inputted to the comparison circuit51is obtained as a result of a process in which the monitor circuits2(i), the control circuit3and the summing circuit4are supplied with the power source voltage VDD, and complete a sequence of monitor operations. By repeating the monitor operations and the control operation for the voltage supply circuit6, an output value of the summing circuit4finally converges to the reference value.

Thus, by using the semiconductor integrated circuit device of the present embodiment, a value obtained by averaging performance variations in the chip can be detected using the monitor circuits disposed at multiple locations in the chip. Moreover, since the monitor circuits remaining after the exclusion of the monitor circuits each showing an abnormal value perform the monitor operations, the performance of the chip can be monitored with high accuracy.

Using the monitor circuits disposed at the multiple locations in the chip, the value obtained by averaging performance variations in the chip can be detected. Additionally, since the oscillation periods of the ring oscillators in the individual monitor circuits can be accurately equalized, the performance of the chip can be monitored with high accuracy. Furthermore, by performing voltage control in accordance with the monitor result, the performance of the chip can accurately be brought closer to a target value.

Note that, in the present embodiment, only one reference value is used and compared with the output value of the summing circuit, but it may also be possible to store the maximum reference value MAX and the minimum reference value MIN in the register52, control the voltage supply circuit6so as to reduce the power source voltage VDDwhen the monitor output value is larger than MAX or increase the power source voltage VDDwhen the monitor output value is smaller than MIN, and perform a control operation such that the output value of the summing circuit is finally between MAX and MIN. By such a control operation, the control operation for the power source voltage stops at the time when the performance of the chip falls within a predetermined range. Therefore, it is possible to constantly prevent fluctuations in power source voltage.

In the present embodiment, the power source voltage VDDto the circuit is controlled in accordance with the output value of the summing circuit. However, instead of the power supply voltage, a substrate bias may also be controlled. In this case, the voltage control circuit6supplies the substrate bias to the circuit, and controls the substrate bias so as to deepen the substrate bias when the output value of the summing circuit is larger than the reference value or shallow the substrate bias when the output value of the summing circuit is smaller than the reference value. By performing such control, the power source voltage is constantly held constant so that, even when signal transmission/reception is performed with another chip, it is basically unnecessary to use a level shifter.

Also in the present embodiment, as the reference value, the value to be outputted from the summing circuit when the process for the chip in which the monitor circuits are mounted, the voltage, and the temperature are under specified conditions is used. However, the reference value may also be an arbitrary value determined based on design or the result of testing a real chip.

The description has been given heretofore of the multiple embodiments of the present invention. It will be appreciated that the configurations and operations of the semiconductor integrated circuit devices1according to the multiple embodiments can be freely combined within a technically consistent scope. For example, the configuration of the semiconductor integrated circuit device1according to the third embodiment of the present invention in which the reference value for defect determination is dynamically calculated in accordance with the output signal from the summing circuit can be easily combined with the configuration of any of the other embodiments.