Single polysilicon process for DRAM

A method of fabricating a DRAM cell, comprising the following steps. A substrate is provided. An isolation structure is formed within the substrate. The substrate is patterned to form nodes adjacent the isolation structure. Doped regions are formed with the substrate adjacent the nodes. A gate dielectric layer is formed over the patterned substrate, lining the nodes. A conductive layer is formed over the gate dielectric layer, filling the nodes. The conductive layer is patterned to form: a top electrode capacitor within the nodes; and respective word lines over the substrate adjacent the top electrode capacitor; each word line having exposed side walls. Source/drain regions are formed adjacent the word lines.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor fabrication and more specifically to fabrication of DRAM structures.

BACKGROUND OF THE INVENTION

There are always three to four polysilicon (poly-Si or poly) layers required for commodity dynamic random access memory (DRAM). It is not very friendly for LOGIC foundry fabrication and it is very difficult to merge with high performance LOGIC process for so-called system-on-chip (SOC).

U.S. Pat. No. 6,177,697 B1 to Cunningham describes a single polysilicon process for a DRAM using a trench capacitor formed from poly 1— same as the gate.

U.S. Pat. No. 4,907,047 to Kato et al. describes a memory device having a trench capacitor.

U.S. Pat. No. 5,793,075 to Alsmeier et al. describes an integrated circuit capacitor that achieves a high capacitance by using an inversion layer in the substrate as the plate counter electrode for the capacitor.

U.S. Pat. No. 5,574,621 to Sakamoto et al. describes a capacitor for an integrated circuit having a conductive trench disposed below a bottom electrode layer that electrically connects to the bottom electrode layer to a semiconductor substrate.

U.S. Pat. No. 5,208,657 to Chatterjee et al. describes a DRAM cell and array of cells, together with a method of fabrication, wherein the cell includes one field effect transistor (FET) and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate.

SUMMARY OF THE INVENTION

Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of

Other objects will appear hereinafter.

It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate is provided. An isolation structure is formed within the substrate. The substrate is patterned to form nodes adjacent the isolation structure. Doped regions are formed with the substrate adjacent the nodes. A gate dielectric layer is formed over the patterned substrate, lining the nodes. A conductive layer is formed over the gate dielectric layer, filling the nodes. The conductive layer is patterned to form: a top electrode capacitor within the nodes; and respective word lines over the substrate adjacent the top electrode capacitor; each word line having exposed side walls. Source/drain regions are formed adjacent the word lines.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Substrate10is preferably a silicon (Si), germanium (Ge) or gallium arsenide (GaAs) substrate, is more preferably a silicon substrate, and is understood to possibly include a semiconductor wafer or substrate.

A P well14and N well16are then formed within substrate10. P well14is formed preferably using boron (B) ions to a concentration of preferably from about 1012to 1013atoms/cm2and more preferably from about 5E12 to 1E13 atoms/cm2. N well 16 is formed preferably using P31ions to a concentration of preferably from about 1012to 1013atoms/cm2and more preferably from about 5E12 to 1E13 atoms/cm2.

As shown inFIG. 2, substrate10is patterned to form nodes18,20adjacent STI12and within NMOS transistor region11. Nodes18,20are preferably from about 3000 to 10,000 Å wide and more preferably from about 5000 to 8000 Å wide, and are preferably from about 3000 to 20,000 Å deep and more preferably from about 5000 to 10,000 Å deep.

A doped silicon glass (DSG) layer22is then formed over patterned substrate10, filling nodes18,20. Doped silicon glass layer22is preferably comprised of arsenic (As) silicon glass (ASG) or phosphorous (P) silicon glass (PSG) and is more preferably PSG silicon glass.

Partial Etch Back of DSG Layer22and Thermal Drive-In—FIG. 3

As shown inFIG. 3, DSG layer22is partially etched back to form respective DSG node plugs22,24within nodes18,20.

A thermal drive-in step is them performed to form respective N diffusion regions26,28within substrate10proximate DSG nodes plugs22,24. N diffusion regions26,28are formed by diffusion of the dopants, either As or P, from the DSG material comprising DSG node plugs22,24into the adjacent substrate by the thermal drive-in step.

N diffusion regions26,28have a thickness of preferably from about 1000 to 5000 Å and more preferably from about 1500 to 2000 Å.

N diffusion regions26,28are thus self-aligned and are formed by a solid phase diffusion process and avoids implant induced crystal defects. No extra masking step is required.

The thermal drive-in step is conducted at a temperature of preferably from about 900 to 1200° C. and more preferably from about 1000 to 1100° C. for preferably from about 10 to 60 minutes and more preferably from about 20 to 40 minutes.

Wet Strip of DSG Node Plugs22,24, Optional Sacrificial Oxide Layer Growth and Gate Oxide Layer30—FIG. 4

As shown inFIG. 4, DSG node plugs22,24are removed from nodes18,20by a wet stripping process. The wet strip process preferably uses HF or BOE and more preferably HF and is conducted under the following conditions:temperature: preferably from about 25 to 100° C. and more preferably from about 25 to 60° C.; andtime: preferably from about 60 to 180 seconds and more preferably from about 60 to 120 seconds.

An optional sacrificial oxide layer (not shown) may then be formed over patterned substrate10, lining nodes18,20to a thickness of preferably from about 50 to 150 Å and more preferably from about 70 to 120 Å. If formed, the optional sacrificial oxide layer is removed before the growth of gate oxide layer30.

Gate dielectric layer30, preferably comprised of gate oxide as will be used hereafter for illustrative purposes, is then grown over patterned substrate10, lining nodes18,20to a thickness of preferably from about 15 to 200 Å and more preferably from about 70 to 100 Å.

As shown inFIG. 5, a conductive layer32, preferably comprised of poly-1 (polysilicon-1) as will be used hereafter for illustrative purposes, is formed over gate oxide layer30, lining nodes18,20. Poly-1 layer32is formed to a thickness of preferably from about 3000 to 10,000 Å and more preferably from about 4000 to 8000 Å.

Poly-1 layer32may then be optionally planarized by a chemical mechanical polishing (CMP) process to a thickness of preferably from about 1000 to 3000 Å and more preferably from about 1500 to 2000 Å.

Cell LDD implants40are then formed within patterned substrate10preferably using P31ions to a concentration of preferably from about 1013to 1014atoms/cm2and more preferably from about 3E13 to 7E13 atoms/cm2.

As shown inFIG. 7, N-LDD implants41are formed within patterned substrate10preferably using P ions to a concentration of preferably from about 1013to 1014atoms/cm2and more preferably from about 3E13 to 7E13 atoms/cm2. The NLDD could be either the same or different cell LDD. It is for periphery NMOS.

As shown inFIG. 7, P-LDD implants43are formed within patterned substrate10preferably using B or BFC ions to a concentration of preferably from about 1013to 1014atoms/cm2and more preferably from about 3E13 TO 5E13 atoms/cm2.

N-LDD and P-LDD implants41,43are formed before formation of sidewall spacers35,37,39.

Respective sidewall spacers35,37,39are then formed over the exposed side walls of word lines34,36and top electrode capacitor38to a lower width of preferably from about 500 to 2000 Å and more preferable from about 1000 to 1500 Å. Sidewall spacers35,37,39are preferably comprised of silicon oxide (SiO2), silicon nitride (Si3N4), SiON or a composite (SiO2/Si3N4/SiO2) and are more preferably silicon oxide or silicon nitride.

Optional N minus (N−) source/drain (N−S/D) implants42adjacent sidewall spacers39of top electrode capacitor and inner sidewall spacers35,37of word lines34,36and N−S/D implants44outboard of outer sidewall spacers35,37of word lines34,36may then be formed within patterned substrate10. N+S/D implants46preferably have a concentration of from about 1014to 1015atoms/cm2.

A subsequent activation process may employ rapid thermal oxidation (RTO) or furnace processes.

As shown inFIG. 8, interlevel dielectric (ILD) layer50is formed over patterned substrate10, word lines34,36and top electrode capacitor38to a thickness of preferably from about 5000 to 10,000 Å and more preferably from about 7000 to 8000 Å.

ILD layer50and gate oxide layer30are then patterned to form, for example, first contact openings52exposing the outboard S/Ds44of word lines34,36and second contact opening54exposing a portion of top electrode capacitor38. Respective first and second metal contacts56,58are then formed within first and second contact openings52,54. First and second metal contacts56,58are preferably comprised of tungsten copper or aluminum and are more preferably tungsten.

A metal-1 layer is then formed and pattered over ILD layer50to form: bit lines62over, and in electrical contact with, first metal contacts56; and metal structure60to Vcc/2 (half of chip operation voltage) over, and in electrical contact with, second metal contact58. Bit lines62and metal structure60are preferably comprised of copper, aluminum or AlCu and are more preferably AlCu.

Further processing may then proceed.

Advantages of the Present Invention

The advantages of one or more embodiments of the present invention include:1. single poly and gate oxide process are inexpensive and are completely compatible with high performance LOGIC;2. efficiently increase capacitor for DRAM cell instead of gate oxide—the gate oxide is very thin than that of capacitor dielectric of commodity DRAM; 3. a very friendly process for a LOGIC foundry fabrication, i.e. less poly furnace;4. embedded DRAM is very cost effective;5. only one extra mask is required to manufacture 1T1C (one transistor, one capacitor) DRAM as compared to LOGIC process;6. the cell size is only one-sixth of a 6T SRAM fabricated by a LOGIC process—i.e. 1T1C fabricated in accordance with the present invention=1.39×0.5=0.695 μm2while6T fabricated by a LOGIC process=1.84×2.53=4.655 μm2;7. for a 1T SRAM application, the cell size if only one-half of that of a LOGIC process because unit capacitance is higher than planar structure of 1TSRAM; and8. the process of the present invention is shrinkable beyond the 0.18 μm generation, even for a 1T SRAM application as the depth of the capacitor trench can overcome the planar area shrinkage.

While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.