SANDWICH PACKAGE FOR MICROELECTRONICS

A transistor configured for higher power can be constructed using multiple transistor dies coupled in parallel. This approach of distributing power and heat over multiple transistor dies can allow each transistor die to be made smaller, which can be helpful in improving yield. This is especially true for emerging technologies, such as silicon carbide (SiC). Power modules for power conversion may require a plurality of these multi-die transistors in a package. A package that accommodates the numerous connections required for a multi-die power module is disclosed. The package utilizes a lead frame to provide a three-dimensional sandwich structure in which multiple dies are positioned between two direct bonded copper (DBC) substrates.

FIELD OF THE DISCLOSURE

The present disclosure relates to a package for a microelectronic circuit, and more specifically, to a sandwich package that facilitates the use of multiple, interconnected dies to implement the microelectronic circuit.

BACKGROUND

A microelectronic circuit (or device) may be implemented on a single die or a plurality of dies. Implementing the microelectronic circuit (or device) on a plurality of dies may have advantages related to heat dissipation and cost but the implementation requires more interconnections.

SUMMARY

In at least one aspect, the present disclosure generally describes a package for a microelectronic circuit (or device) with a three-dimensional structure (i.e., sandwich structure) in which a first portion of a plurality of dies are bonded to an upper direct bonded metal (i.e., DBM) substrate (i.e., upper DBM) and a second portion of the plurality of dies are bonded to a lower DBM substrate (i.e., lower DBM). Electrical connections are made to the plurality of dies by a lead frame which is positioned between (i.e., sandwiched between) the upper DBM and the lower DBM. Accordingly, the package may be referred to as a sandwich package based on the spatial relationship of the dies and lead frame between the upper DBM and the lower DBM.

In some aspects, the techniques described herein relate to a microelectronic package including: an upper direct bonded metal (DBM) substrate; a lower DBM substrate aligned with and spaced apart from the upper DBM substrate, the lower DBM substrate and the upper DBM substrate defining an interior of the microelectronic package between the lower DBM substrate and the upper DBM substrate, an upper set of dies coupled the upper DBM substrate in the interior of the microelectronic package; a lower set of dies coupled to the lower DBM substrate in the interior of the microelectronic package; and a lead frame extending from outside the interior of the microelectronic package to inside the interior of the microelectronic package; the lead frame including: a signal tab having a plurality of upward clips coupled to the upper set of dies and a plurality of downward clips coupled to the lower set of dies; and an output tab having a bidirectional clip coupled to the upper DBC substrate and the lower DBC substrate.

In some aspects, the techniques described herein relate to a half-bridge circuit including: a package including: an upper direct bonded copper (DBC) substrate including an upper high-side conductor and an upper low-side conductor; a lower DBC substrate spaced apart from the upper DBC substrate, the lower DBC substrate including a lower high-side conductor and a lower low-side conductor, an output tab including a first bidirectional clip that supports and positions the upper DBC substrate apart from the lower DBC substrate, the first bidirectional clip electrically connecting the upper low-side conductor and the lower low-side conductor to the output tab; a power tab including a second bidirectional clip that supports and positions the upper DBC substrate apart from the lower DBC substrate, the second bidirectional clip electrically connecting the upper high-side conductor and the lower high-side conductor to the power tab; a high-side transistor including: a first group of transistor-dies, wherein a first portion of the first group of transistor-dies are directly connected to the upper high-side conductor and a second portion of the first group of transistor-dies are directly connected to the lower high-side conductor; and a low-side transistor including: a second group of transistor-dies, wherein a first portion of the second group of transistor-dies are directly connected to the upper low-side conductor and a second portion of the second group of transistor-dies are directly connected to the lower low-side conductor.

In some aspects, the techniques described herein relate to a method for packaging a transistor, the method including: connecting an upper set of transistor dies to an upper direct bonded copper (DBC) substrate; connecting a lower set of transistor dies to a lower DBC substrate; positioning a lead frame between the lower DBC substrate and the upper DBC substrate to create a stack-up assembly, the positioning including: positioning bidirectional clips of the lead frame between pads on the lower DBC substrate and pads on the upper DBC substrate, the bidirectional clips configured to electrically couple the lower DBC and the upper DBC and to space the upper DBC substrate apart from the lower DBC substrate; positioning upward clips of the lead frame at pads on the upper set of transistor dies; and positioning downward clips of the lead frame at pads on the lower set of transistor dies; and heating the stack-up assembly to connect the bidirectional clips, the upward clips, and the downward clips to their respective pads in order to electrically couple the upper set of transistor dies and the lower set of transistor dies in parallel.

The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.

DETAILED DESCRIPTION

It may be advantageous to implement a microelectronic circuit (or device) using a plurality of dies. For example, a metal oxide semiconductor field effect transistor (MOSFET) may be implemented as a plurality of MOSFETs connected in parallel (i.e., gates connected, sources connected, and drains connected), where each MOSFET is implemented on a separate die. The parallel MOSFETs may increase an overall current carrying capacity of the device due to their current channels being connected in parallel. Further, distributing the conducted current between the plurality of MOSFETs can distribute the thermal heating over the plurality of dies, which may make cooling more efficient. Moreover, the use of multiple dies may lead to a reduction in cost by reducing a potential yield loss for each die. The approach of using multiple dies to implement a device (e.g., MOSFET) may be especially useful for silicon carbide (SIC) technology, which is relatively new and more expensive than standard Si processing.

A MOSFET implemented using a plurality of parallel-connected MOSFET dies may be referred to as a multi-die MOSFET. A plurality of multi-die MOSFETs can be interconnected in a microelectronic package to form a power module. For example, a power module may be implemented as a half-bridge circuit. The half-bridge circuit can include a high-side (H/S) MOSFET, implemented using a plurality (e.g., 4) MOSFET dies connected in parallel. The half-bridge circuit can further include a low-side (L/S) MOSFET, implemented using a plurality (e.g., 4) MOSFET dies connected in parallel.

The H/S MOSFET and the L/S MOSFET may be connected in series between an upper rail and a lower rail of a power supply. The H/S MOSFET of the half-bridge circuit may be configured to switch an upper rail voltage (i.e., P1) to a switching node (i.e., Output1) and a L/S MOSFET of the half-bridge circuit configured to switch a lower-rail voltage (i.e., N1) to the switching node (i.e., Output1). These switching operations may be part of a power conversion (e.g., buck conversion) or power inversion (i.e., DC to AC) process.

A technical problem in using multiple dies to implement the transistors in the half-bridge circuit described above, is the high number of connections that must be made in a conveniently sized package footprint (e.g., <3 cm2). A microelectronic package is disclosed in which the dies are distributed between an upper direct bonded metal (e.g., direct bonded copper (DBC)) substrate (i.e., upper DBC substrate) and a lower direct bonded copper substrate (i.e., lower DBC substrate). The package further includes a lead frame that is (sandwiched) between the upper DBC substrate and the lower DBC substrate. The lead frame is configured to space the DBC substrates apart and to connect the dies to the terminals (e.g., P1, N1, Output1) of the microelectronic package.

The disclosed microelectronic package may have a few technical advantages. For example, the three-dimensional (i.e., upper/lower) structure can provide distributed cooling and versatility, such as in the number of dies (e.g., 4, 8, etc.) used for each device, which may be different. Further, the lead frame, which may be formed from a unibody material, may simultaneously provide the function of electrical connection and mechanical spacing.

FIG.1is a side cross-sectional view of a microelectronic package according to a possible implementation of the present disclosure. The microelectronic package (i.e., package100) includes an upper DBC substrate110and a lower DBC substrate120, which are spaced apart to define an interior106of the package100. For the discussion, a horizontal plane105is defined as bisecting the interior106.

Relative positions of elements/features of the package may be described in terms of their position relative to the horizontal plane105. For example, the upper DBC substrate110can be considered above the lower DBC substrate120because the upper DBC substrate110is above the horizontal plane105, while the lower DBC substrate is below the horizontal plane105. Accordingly, the terms upper, up, upward, above, over, and the like may refer to elements/features that are further in a positive direction103than other elements/features, while the terms lower, down, downward, below, under, and the like may refer to elements/features that are further in a negative direction102than other elements/features.

For the discussion, elements may be considered as facing the interior106of the package. For example, a first copper layer111of the upper DBC substrate110may be referred to as being on a front side of the upper DBC substrate110, while a second copper layer113of the upper DBC substrate110may be referred to as being on a back side of the upper DBC substrate110. The upper DBC substrate110includes an upper substrate112(e.g., ceramic slab) separating the first copper layer111and the second copper layer113of the upper DBC substrate110. Likewise, a first copper layer121of the lower DBC substrate120may be referred to as being on a front side of the lower DBC substrate120, while a second copper layer123of the lower DBC substrate120may be referred to as being on a back side of the lower DBC substrate. The lower DBC substrate120includes a lower substrate122(e.g., ceramic slab) separating the first copper layer121and the second copper layer123of the lower DBC substrate120.

The package100includes a lead frame130that is positioned between (e.g., halfway between) the upper DBC substrate110and the lower DBC substrate120. In a possible implementation, the lead frame130is in the horizontal plane105. As shown, the lead frame130includes a plurality of upward clips150coupled to an upper set of dies140by connections on a front surface of each of the upper set of dies140. The connections in the package can be any type that provides electrical and mechanical coupling, such as solder connections, sinter connections, or the like. The lead frame130further includes a plurality of downward clips151coupled to a lower set of dies141by connections (e.g., solder connections, sinter connection) on a front surface of each of the lower set of dies141. The lead frame130may include a first portion within molding material101of the package and a second portion outside the molding material101of the package.

The first copper layer111of the upper DBC substrate110and the first copper layer121of the lower DBC substrate120may be coupled to the lead frame130by a bidirectional clip132.

Each of the upper set of dies140is coupled by connections (e.g., solder connection, sinter connection) on a back surface (of each die) to the first copper layer111of the upper DBC substrate110. Each of the lower set of dies141is coupled by connections (e.g., solder connection, sinter connection) on a back surface (of each die) to the first copper layer121of the lower DBC substrate120.

Each of the dies in the upper set of dies140and the lower set of dies141may be substantially identical. For example, each die may include a transistor (e.g., SiC MOSFET transistor). The transistors of the upper set of dies140and the transistors of the lower set of dies141may be connected in parallel to form a transistor with an overall current carrying capability (i.e., power rating) that is higher than could be obtained individually using the same size die.

A transistor (e.g., SiC MOSFET) for a circuit may include a group of transistor-dies (e.g., 4 dies), with a first portion (e.g., 2 dies) of the group directly connected to the upper DBC substrate110and a second portion (e.g., 2 dies) of the group directly connected to the lower DBC substrate120. Dividing the dies between the upper DBC substrate110and the lower DBC substrate120may improve cooling by distributing the heating between the upper DBC substrate110and the lower DBC substrate120. For example, an upper heat sink (not shown) may be coupled to the second copper layer113(i.e., back side) of the upper DBC substrate110and a lower heat sink (not shown) may be coupled to the second copper layer123(i.e., back side) of the lower DBC substrate120. The cooling may be useful for circuits used in power applications, such as the half-bridge circuit. While not required, upper dies and lower dies may alternate along the lead frame130in order to maximize their spacing, which can help their cooling. For example, as shown inFIG.1, moving in a direction160along the lead frame130, the lead frame includes a first upward clip connected to a first upper die, followed by a first downward clip connected to a first lower die, followed by a second upward clip connected to a second upper die, and followed by a second downward clip connected to a second lower die.

FIG.2is a schematic of a half-bridge circuit according to a possible implementation of the present disclosure. The half-bridge circuit200includes a first transistor (e.g., high-side (H/S) transistor220). The H/S transistor220is coupled at a drain terminal (D1) to an upper-rail voltage (P1) (i.e., upper-rail supply) and at a source terminal (S1) to an output (OUT1) of the circuit. The H/S transistor may be configured ON (i.e., conducting) or OFF (i.e., not conducting) based on a switching signal (e.g., pulse width modulation (PWM) signal) at a gate terminal (G1) of the H/S transistor220. The half-bridge circuit200further includes a second transistor (e.g., low-side (L/S) transistor210). The L/S transistor210is coupled at a drain terminal (D2) to the output (OUT1) and at a source terminal (S2) to a lower-rail voltage (N1) (i.e., lower-rail supply). The L/S transistor may be configured ON (i.e., conducting) or OFF (i.e., not conducting) based on a switching signal at a gate terminal (G2) of the L/S transistor210.

As discussed, the H/S transistor220may be implemented using a group of dies (e.g., four transistor dies) connected in parallel. Likewise, the L/S transistor210may be implemented using a plurality of dies (e.g., four transistor dies) connected in parallel. The disclosed package may be configured to include both groups of transistors.

The package for the half-bridge circuit includes tabs (i.e., leads, pins, etc.) for electrical connection with external circuitry. These tabs may be classified as power tabs or signal tabs based on the amount of current each is expected to carry, with power tabs being larger than signal tabs. The package may include a P1power tab for connection to an upper rail voltage (e.g., positive voltage), a N1power tab for connection to a lower-rail voltage (e.g., negative voltage), and an OUT1power tab for connection to an output of the circuit. The package may further include a D1signal tab for connection to the drain of the H/S transistor220, a G1signal tab for connection to the gate of the H/S transistor220, and an S1signal tab for connection to the source of the H/S transistor220. The package may further include a D2signal tab for connection to the drain of the L/S transistor210, a G2signal tab for connection to the gate of the L/S transistor210, and an S2signal tab for connection to the source of the L/S transistor210. As shown inFIG.2, the D1signal tab may be electrically connected to the P1power tab and the S2signal tab may be electrically connected to the N1power tab. Additionally, the S1signal tab and the D2signal tab may be electrically connected to the OUT1power tab.

FIG.3is a perspective view of an upper DBC substrate310and a lower DBC substrate320prior to assembly into a package including the half-bridge circuit200shown inFIG.2. An upper DBC substrate310includes an upper gap313that is made (e.g., etched, machined) into the upper conductor (e.g., see first copper layer111ofFIG.1). The upper gap313electrically isolates (i.e., insulates) an upper high-side (H/S) conductor311and an upper low-side (L/S) conductor312. The lower DBC substrate320includes a lower gap323that is made (e.g., etched, machined) into the lower conductor (e.g., see first copper layer121ofFIG.1). The lower gap323insulates a lower low-side (L/S) conductor321and a lower high-side (H/S) conductor322.

As part of an assembly process, the upper DBC substrate310may be flipped, as shown (dotted lines), so that the upper H/S conductor311is aligned with and faces the lower H/S conductor322, and so that the upper L/S conductor312faces the lower L/S conductor321. A lead frame (not shown) positioned between the upper DBC substrate310and the lower DBC substrate320may be configured (e.g., by clips) to support the DBC substrates and space them apart to define an interior106of the package. The lead frame may extend from outside the interior to inside the interior to make electrical connections to the dies, the (upper/lower) H/S conductors, and the (upper/lower) L/S conductors.

In the flipped condition, the two upper H/S transistor dies301on the upper H/S conductor311and the two lower H/S transistor dies302on the lower H/S conductor322alternate (e.g., upper-to-lower-to-upper-to-lower) along a direction (e.g., seeFIG.1, horizontal plane105). Likewise, the two upper L/S transistor dies303on the upper L/S conductor312and the two lower L/S transistor dies304on the lower L/S conductor321alternate (e.g., upper-to-lower-to-upper-to-lower) along a direction (e.g.,FIG.1, horizontal plane105).

FIG.4is a perspective view of an upper DBC, substrate, lower DBC substrate, and a lead frame in a package assembly process according to a possible implementation of the present disclosure. The lead frame410may include power tabs (e.g., N1, P1) for coupling higher-power electrical signals to power the circuit of the package. The lead frame may also include an output tab (OUT1) for coupling a higher-power electrical signal output by the circuit of the package. The lead frame may also include signal tabs to couple lower power electrical signals to control the circuit of the package and/or to provide testing/monitoring of signals at points in the circuit. The signal tabs may be smaller than the power tabs because they may carry less current.

As shown inFIG.4, the lead frame410can (initially) be unibody, such as being formed (e.g., cut, stamped, machined, etc.) from a plate of metal (e.g., copper). The tabs of the unibody can be separated by a trimming process prior to use.

The upper DBC substrate310and the lower DBC substrate320may be identical except for the placement of solder pads for connections with the lead frame410. The upper H/S conductor of the upper DBC substrate310may include a first solder pad401for solder (or sinter) connection to a first bidirectional clip411of the power tab (P1) and a second solder pad402for a solder (or sinter) connection to a second bidirectional clip412of a first drain tab (D1). The bidirectional clips electrically connect the upper H/S conductor, lower H/S conductor, the P1tab and the D1tab. Drain pads of the plurality of dies comprising the H/S transistor are coupled to either the H/S conductor or the lower H/S conductor.

The upper L/S conductor of the upper DBC substrate310may include a third solder pad403for solder (or sinter) connection to a third bidirectional clip413of the output tab (OUT1) and a fourth solder pad404for a solder (or sinter) connection to a fourth bidirectional clip414of a second drain tab (D2). The bidirectional clips electrically connect the upper L/S conductor, lower L/S conductor, the OUT1tab and the D2tab. Drain pads of the plurality of dies comprising the L/S transistor are coupled to either the L/S conductor or the lower L/S conductor.

An upper set of dies are coupled at drain pads to the upper H/S conductor. The upper set of dies may include source pads405for solder (or sinter) connection to upward clips415A of a portion of the lead frame coupled to the output tab (OUT1). Likewise, a lower set of dies are coupled at drain pads to the lower H/S conductor. The lower set of dies may include source pads for solder (or sinter) connection to downward clips415B of a portion of the lead frame coupled to the output tab (OUT1) so that the source (S1) of the H/S transistor is coupled to the output of the half-bridge circuit200.

The upper set of dies, coupled at drain pads to the upper H/S conductor, may further include gate pads406for solder (or sinter) connection to upward clips of a gate tab416. Likewise, the lower set of dies, coupled at drain pads to the lower H/S conductor, include gate pads for solder (or sinter) connection to downward clips of the gate tab416so that the gate (G1) of the H/S transistor is coupled to gate tab416.

Similar connections may be made for the upper set of dies coupled to the upper L/S conductor and the lower set of dies coupled to the lower L/S conductor. For example, the upper set of dies, which are coupled at drain pads to the upper L/S conductor may include source pads407for solder (or sinter) connection to upward clips417of a portion of the lead frame coupled to the (negative) power tab N1. Likewise, a lower set of dies are coupled at drain pads to the lower L/S conductor may include source pads for solder (or sinter) connection to downward clips of the portion of the lead frame coupled to the (negative power) tab (N1) so that the source (S2) of the L/S transistor is coupled to the lower rail voltage of the half-bridge circuit200.

FIG.5is a magnified view of the lead frame ofFIG.4. As shown inFIG.5, an upward clip511of the gate tab416includes an upward (e.g., from the horizontal plane105) bend to an upper step that is configured to fit flush with a gate pad of a transistor die of an upper set of dies.FIG.6Aillustrates a cross-sectional profile of an upward clip of the lead frame according to a possible implementation of the present disclosure. The upward clip includes an upward bend610and an upper step620. The upper step may be configured to substantially match a size of a solder pad on a transistor die. Accordingly, an upper step for a gate pad may be smaller than an upper step for a source pad.

As shown inFIG.5, a downward clip512of the gate tab416includes a downward (e.g., from the horizontal plane105) bend to a lower step that is configured to fit flush with a gate pad of a transistor die of a lower set of dies.FIG.6Billustrates a cross-sectional profile of a downward clip of the lead frame according to a possible implementation of the present disclosure. The downward clip includes a downward bend630and a lower step640. The lower step may be configured to substantially match a size of a solder pad on a transistor die. Accordingly, a lower step for a gate pad may be smaller than a lower step for a source pad.

As shown inFIG.5, the first bidirectional clip411includes a downward (e.g., from the horizontal plane105) bend to a lower step that is configured to fit flush with the lower H/S conductor of the lower DBC substrate. The first bidirectional clip411further includes an upward bend to an upper step that is configured to fit flush with the upper H/S conductor of the upper DBC substrate.FIG.6Cillustrates a cross-sectional profile of a bidirectional clip of the lead frame according to a possible implementation of the present disclosure. The bidirectional clip includes a downward bend650, a lower step660, an upward bend670to an upper step680. The lower step660may be configured to substantially match a size of a solder pad on a conductor of the lower DBC substrate and the upper step680may be configured to substantially match a size of a solder pad on a conductor of the upper DBC substrate. A height690between the lower step660and the upper step680can create space between the upper DBC substrate110and the lower DBC substrate120in the package. The space (i.e., separation, gap, height, etc.) can provide clearance for an upper set of dies and a lower set of dies.

FIG.7is a top view of a lead frame according to a possible implementation of the present disclosure. As shown, the unibody lead frame700has been trimmed to separate the tabs. Also shown is an L/S area710corresponding to the upper and L/S conductors of the DBC substrates when viewed from above, and a H/S area720corresponding to the upper and lower H/S conductors of the DBC substrates when viewed from above.

The lead frame700includes a lower rail tab (N1). The lower rail tab (N1) includes a first downward source clip711for connection to a source pad of a first lower L/S die, a first upward source clip712for connection to a source pad of a first upper L/S die, a second downward source clip713for connection to a source pad of a second lower L/S die, and a second upward source clip714for connection to a source pad of a second upper L/S die.

The first lower L/S die is coupled at a drain terminal to the lower L/S conductor, the first upper L/S die is coupled at a drain terminal to the upper L/S conductor, the second lower L/S die is coupled at a drain terminal to the lower L/S conductor, and the second upper L/S die is coupled at a drain terminal to the upper L/S conductor. Accordingly, the lead frame700further includes a second drain tab (D2) for connection to a drain terminal of the L/S transistor of the half-bridge circuit (seeFIG.2). The second drain tab (D2) includes a bidirectional drain clip719for connection to the upper L/S conductor and the lower L/S conductor.

The lead frame700further includes a second gate tab (G2) for a L/S transistor. The second gate tab (G2) includes a first downward gate clip715for connection to a gate pad of the first lower L/S die, a first upward gate clip716for connection to a gate pad of the first upper L/S die, a second downward gate clip717for connection to a gate pad of the second lower L/S die, and a second upward gate clip718for connection to a gate pad of the second upper L/S die.

The lead frame700further includes a second source tab (S2) for a L/S transistor. The second source tab (S2) is connected to the lower rail tab (N1), which includes the upward and downward source clips for the L/S transistor.

The lead frame700includes an output tab (OUT1). The output tab (OUT1) includes a first upward source clip721for connection to a source pad of a first upper H/S die, a first downward source clip722for connection to a source pad of a first lower H/S die, a second upward source clip723for connection to a source pad of a second upper H/S die, and a second downward source clip724for connection to a source pad of a second lower L/S die.

The second drain terminal (D2) of the L/S transistor is further coupled to the output of the half-bridge circuit. Accordingly, the output tab (OUT1) further includes a bidirectional clip730for connection to the upper L/S conductor and the lower L/S conductor.

The lead frame700further includes a first source tab (S1) for a H/S transistor. The first source tab (S1) is connected to the output tab (OUT1), which includes the upward and downward source clips for the H/S transistor.

The lead frame700further includes a first gate tab (G1) for a H/S transistor. The first gate tab (G1) includes a first upward gate clip725for connection to a gate pad of the first upper H/S die, a first downward gate clip726for connection to a gate pad of the first lower H/S die, a second upward gate clip727for connection to a gate pad of the second upper H/S die, and a second downward gate clip728for connection to a gate pad of the second lower H/S die.

The first lower H/S die is coupled at a drain terminal to the lower H/S conductor, the first upper H/S die is coupled at a drain terminal to the upper H/S conductor, the second lower H/S die is coupled at a drain terminal to the lower H/S conductor, and the second upper H/S die is coupled at a drain terminal to the upper H/S conductor. Accordingly, the lead frame700further includes a first drain tab (D1) for connection to a drain terminal of the H/S transistor of the half-bridge circuit (seeFIG.2). The first drain tab (D1) includes a bidirectional drain clip729for connection to the upper H/S conductor and the lower H/S conductor.

The drain terminal of the H/S transistor in the half-bridge circuit is coupled to an upper rail voltage. Accordingly, the lead frame further includes an upper rail tab (P1). The upper rail tab (P1) includes a bidirectional clip740for connection to the upper H/S conductor and the lower H/S conductor.

FIG.8is a perspective view of the package of a half-bridge circuit according to a possible implementation of the present disclosure. The package800includes molding material801, which contains the dies, the upward clips, and the downward clips. A portion of the upper DBC may be not covered by the molding material810(i.e., exposed) to provide a surface for a heat sink (not shown) to be mounted. Similarly, a portion of the lower DBC may be exposed to provide a surface for a heat sink. A portion of the lead frame is contained in the molding material801, while power tabs (N1, P1, OUT1) of the lead frame and signal tabs (D1, G1, S1, S2, G2, D2) of the lead frame from extend outside the molding material801for connection to external circuitry (not shown).

FIG.9is a flowchart of a method for packaging a transistor according to a possible implementation of the present disclosure. The method900includes soldering910(or sintering) an upper set of transistor dies to an upper DBC substrate and soldering920(or sintering) a lower set of transistor dies to a lower DBC substrate. The method900further includes positioning a lead frame between the lower DBC substrate (with the lower set of dies) and the upper DBC substrate (with the upper set of ides) to create930a stack-up assembly (e.g., seeFIG.4). At this step of the method900, the lead frame may be a unibody lead frame, in which tabs of the package are mechanically connected. In particular, creating930the stack-up assembly includes positioning933bidirectional clips of the lead frame between solder pads of the upper DBC and the lower DBC. The creating930further includes positioning936upward clips of the lead frame at solder pads of the upper set of transistor dies, and positioning939downward clips of the lead frame at solder pads of the lower set of transistor dies.

After the stack-up assembly is created, the method900includes heating940the stack-up assembly to solder (or sinter) the bidirectional clips to the upper/lower DBC, to solder (or sinter) the upward clips to the upper set of dies, and to solder (or sinter) the downward clips to the lower set of dies. These connections electrically connect the transistors of the upper/lower set of transistor dies in parallel.

The method900includes molding950the stack-up assembly. The molding can be injection molding and can provide stability and protection to the electrical connections and circuitry. The injection molding may include providing an area on the upper/lower DBC for connection of a heat sink and can allow the tabs to be exposed for connection to other circuitry.

Finally, the method900can include trimming960the lead frame to separate tabs coupled to the parallel-connected transistor(s).

Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), Silicon Carbide (SiC) and/or so forth.