3D CTF integration using hybrid charge trap layer of sin and self aligned SiGe nanodot

Provided are an improved memory device and a method of manufacturing the same. In one embodiment, the memory device may include a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of nanostructures formed on the nitride layer. The nanostructures may be a group IV semiconductor compound such as silicon germanium (SiGe).

FIELD

Embodiments of the present disclosure generally relate to an improved memory device and a method of manufacturing the same.

BACKGROUND

Non-volatile memory devices are semiconductor memory devices that may preserve stored data even when there is no supply of power. One example of non-volatile memory devices is flash memory device. Each of a plurality of memory cells constituting flash memory may include a cell transistor having a gate structure in which a floating gate storing charges, and a control gate controlling the floating gate may be sequentially stacked.

In order to satisfy the demand for expanding the memory capacity of the flash memory device, the size of the memory cells has been reduced. In addition, a height of the floating gate in a vertical direction has been reduced. However, the size of the floating gate may limit the reduction in the size of the flash memory device. In order to deal with this limitation, a charge trap flash (CTF) memory device including a charge trap layer instead of a floating gate has been developed. The CTF memory device may utilize a shifting threshold voltage as charges are trapped in the charge trap layer. The CTF memory device may be smaller than a flash memory device that stores charges in a floating gate.

However, CTF memory devices are reported to have charge retention issues because their charge retention capability are sensitive to defects in a tunneling dielectric layer that is typically disposed underneath the charge trapping layer. Defects that are present in the tunneling dielectric layer can allow charges to leak from a floating gate transistor. Thus, further scaling of devices by reducing the thickness of the tunnel dielectric layer can increase the risk of defects in the tunneling dielectric layer and accordingly decrease charge retention capabilities of the charge trapping layer.

Therefore, there is a need in the art to provide an improved CTF memory device that addresses the above-mentioned issues.

SUMMARY

Embodiments of the present disclosure provide an improved memory device and a method of manufacturing the same. In one embodiment, the memory device includes a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of nanostructures formed on the nitride layer. The nanostructures may be a group IV semiconductor compound such as silicon germanium (SiGe).

In another embodiment, a method of fabricating a memory cell includes forming a channel region through a vertical stack of alternating oxide layer and nitride layer, selectively growing a plurality of group IV semiconductor nanostructures on the nitride layer inside channel region of the vertical stack, and forming a gate oxide layer on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of group IV nanostructures formed on the nitride layer.

In yet another embodiment, the memory device includes a channel layer formed over a substrate, a first oxide layer formed on the channel layer, wherein the first oxide layer having a plurality of group IV semiconductor nanostructures disposed thereon, a second oxide layer formed on the first oxide layer, the second oxide layer having a trench extended through the second oxide layer to expose the plurality of group IV semiconductor nanostructures, a nitride layer conformally formed on exposes surfaces of the second oxide layer and the plurality of group IV semiconductor nanostructures, wherein the plurality of group IV semiconductor nanostructures are embedded between the nitride layer and the first oxide layer, a third oxide layer conformally formed on the nitride layer, and a metal gate layer formed on the third oxide layer within the trench.

DETAILED DESCRIPTION

FIG. 1depicts a flow chart of a method100for manufacturing a memory device according to embodiments of the disclosure.FIG. 1is illustratively described with reference toFIGS. 2A-2K, which show perspective views of a simplified, conceptual memory device during various stages of fabrication according to the flow chart ofFIG. 1. Those skilled in the art will recognize that the structuresFIGS. 2A-2K, while generally drawn to illustrate approximate relative sizes or dimensions for ease of understanding, are not drawn to scale. Those skilled in the art will further recognize that the well-known processes for forming a transistor circuit and the associated structures are not illustrated in the drawings or described herein. Instead, for simplicity and clarity, only so much of a process for forming a transistor circuit and the associated structures as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described. In addition, although various steps are illustrated in the drawings and described herein, no limitation regarding the order of such steps or the presence or absence of intervening steps is implied. Steps depicted or described as sequential are, unless explicitly specified, merely done so for purposes of explanation without precluding the possibility that the respective steps are actually performed in concurrent or overlapping manner, at least partially if not entirely.

The method100begins at block102by providing a multilayer structure of dielectric film202, as shown inFIG. 2A. The multilayer structure of dielectric film202may have a vertical stack of alternating oxide layer203and nitride layer205, forming an oxide-nitride-oxide-nitride-oxide (“ONO”) structure. The oxide and nitride layers may be any suitable oxides and nitrides. In one embodiment as shown, the oxide layer203is silicon oxide and the nitride layer205is silicon nitride. While not shown, it is contemplated that the multilayer structure of dielectric film202can have any desired number of oxide and nitride layers, such as 12 or more pairs of alternating oxide layer and nitride layer pairs, for example 16 or more pairs of alternating oxide layer and nitride layer pairs.

At block104, the multilayer structure of dielectric film202is etched anisotropically to form a vertical channel region204therethrough, as shown inFIG. 2B.

At block106, the nitride layer205is partially removed using an etch process that is selective to the nitride layer205over the oxide layer203. Upon completion of etching the nitride layer205, the nitride layer205is slightly recessed laterally as compared to the oxide layer203, as shown inFIG. 2C.

At block108, an optional pre-clean process is performed to remove impurities such as native oxides from the exposed surfaces of the channel region204. The pre-clean process can be performed by using a cleaning solution such as dilute hydrofluoric acid (DHF), or a SPM solution including sulfuric acid (H2SO4), hydrogen peroxide (H2O2), and deionized water (DI water).

At block110, a selective growth process is performed to form a plurality of nanodots206on the nitride layer205, as shown inFIG. 2D. The nanodots206may be evenly distributed on the exposed surface of the nitride layer205. For clarity purposes, only a portion of the multilayer structure of dielectric film202is depicted inFIG. 2D. The nanodots206herein refer to nanostructures having a size of a nanometer order. Nanodots may also be referred to as nanoparticles, quantum dots (nanostructure with quantum confinement), or nanocrystals (having a crystalline structure). These nanostructures are small particles in any shape that can be formed with charge-storing capabilities. As device dimensions continue to be scaled-down, the small size of nanostructures makes them suitable for forming charge storage regions, such as the floating gates for non-volatile memory cells. The nanodots206may have a characteristic dimension that is less than about 100 μm, for example less than 10 μm, or even less than 1 μm. In some embodiments, each of these nanodots206may have a dimension less than 10 μm. While nanodots are described in this disclosure, it is contemplated that other nanostructures, such as, for example, nanowires, nanotubes, or nanotetrapods etc., may also be used to replace the nanodots. In this disclosure, nanostructures can be, for example, substantially crystalline, substantially mono-crystalline, poly-crystalline, amorphous or a combination thereof.

The nanodots206, as shown inFIG. 2D, are comprised of substantially spherical nanostructures. The nanodots206can be comprised of essentially any material. In various embodiments, the nanodots206may be a group IV semiconductor compound, a group II-VI semiconductor compound, a group III-V semiconductor compound, a metal or a metal alloy, or a high-K material. The nanodots206may be formed using a low-pressure chemical vapor deposition (LPCVD), a chemical vapor deposition (CVD), an atomic layer deposition (ALD), a physical vapor deposition (PVD), or any other suitable process such as ion implantation.

In one embodiment, the nanodots206are silicon germanium (SiGe), either in substantially crystalline or amorphous. Optionally, an amorphous silicon layer may be firstly deposited on the exposed surfaces of the multilayer structure of dielectric film202inside the channel region204to promote deposition of SiGe on the nitride layer205over the oxide layer203. It has been observed that due to germanium intermixing with the amorphous silicon layer, agglomeration of amorphous silicon and silicon germanium would result in only formation of the nanodots206on the nitride layer205, with minimum or zero deposition of nanodots206on the oxide layer203. The preferential agglomeration to the nitrides than oxides may be due to nitride with more dangling bonds available, providing better nucleation site than the oxide surface. The concentration of germanium in SiGe may be above 20%, for example about 30% or more, such as about 45% or more. Different germanium concentrations can be obtained by varying the germanium-containing precursor gas flow rates with a constant silicon-containing precursor gas flow. The kinetics of intermixing is more prominent as Ge concentrations increase and the adjacent amorphous silicon layer thickness are thinner (e.g., less than 50 angstrom, such as 30 angstrom or less). In one exemplary embodiment, the SiGe nanodots are formed using a chemical vapor deposition process where a silicon-containing precursor gas and a germanium-containing precursor gas are reacted at a temperature of about 400° C. to about 650° C., for example about 550° C., and a chamber pressure of about 20 Torr to about 100 Torr, for example about 50 Torr, to selectively deposit SiGe on the nitride layer205.

Suitable silicon-containing precursor gas may include one or more of silanes, halogenated silanes or organosilanes. Silanes may include silane (SiH4) and higher silanes with the empirical formula SixH(2x+2), such as disilane (Si2H6), trisilane (Si3H5), and tetrasilane (Si4H10), or other higher order silane such as polychlorosilane. Halogenated silanes may include compounds with the empirical formula X′ySixH(2x+2−y), where X′=F, Cl, Br, or I, such as hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), dichlorosilane (Cl2SiH2) and trichlorosilane (Cl3SiH). Organosilanes may include compounds with the empirical formula RySixH(2x+2−y), where R=methyl, ethyl, propyl or butyl, such as methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4) and hexamethyldisilane ((CH3)6Si2). Suitable germanium-containing gases may include, but are not limited to germane (GeH4), digermane (Ge2H6), trigermane (Ge3H5), or a combination of two or more thereof.

At block112, a gate dielectric or gate oxide layer208is formed on exposed surfaces of the multilayer structure of dielectric film202inside the channel region204, as shown inFIG. 2E. The gate oxide layer208may be a thin layer conformally covering the nanodots206formed on the nitride layer205. Therefore, the nanodots206is embedded or encapsulated within the gate oxide layer208. The gate oxide layer208separates or electrically isolates a sequentially formed charge trapping layer (i.e., the charge trapping layer212having nanodots206embedded therein, seeFIG. 2H) from a channel region (not shown) of the memory device disposed between source and drain regions. The gate oxide layer208may be made of silicon oxide, silicon dioxide or any other materials having high dielectric constant (K). The gate oxide layer208may be formed by an ALD process or any suitable process such as a thermal oxidation process. The gate oxide layer208may have a thickness of about 800 μm or less, for example about 500 μm or less, or even 200 μm or less. A thinner gate oxide layer permits the use of lower programming and erasing voltages, allowing for better charge retention as compared to conventional floating-gate electrically erasable programmable read-only memory devices.

At block114, a channel layer210is formed on the gate oxide layer208, as shown inFIG. 2F. The channel layer210may be made of any group IV semiconductor such as silicon or germanium, any group III-V compounds, such as gallium nitride (GaN), any group II-VI semiconductor compound, or any group III-V semiconductor compound. In one embodiment as shown, the channel layer210is a polycrystalline silicon layer.

At block116, after the channel layer210is formed, the nitride layer205is selectively removed from the backside (i.e., a side opposing the channel region204). The nitride layer205may be removed by using a slit photolithography process that is selective to the nitride layer205over the oxide layer203, followed by an etch process using a diluted hydrofluoric acid (HF) solution to remove the nitride layer205and expose portions of the nanodots206disposed between the nitride layer (now removed) and the gate oxide layer208, as shown inFIG. 2G.

At block118, a conformal charge trapping layer212is formed on exposed surfaces of oxide layer203and the exposed nanodots206on the back side of the multilayer structure of dielectric film202, as shown inFIG. 2H. The nanodots206are embedded in the charge trapping layer212as a result of formation of the charge trapping layer212. The charge trapping layer212may be silicon nitride formed by a LPCVD process or an ALD process using a silicon-containing precursor gas, such as a dichlorosilane (SiH2Cl), and a nitrogen-containing precursor gas, such as ammonia (NH3). The charge trapping layer212may have a thickness of about 1 μm to about 10 μm, for example about 5 μm.

At block120, a conformal block oxide layer214is formed on the charge trapping layer212, as shown inFIG. 2H. The block oxide layer214may be a silicon oxide layer. In some embodiments, the block oxide layer214may be made of materials including metal oxide, such as aluminum oxide. The block oxide layer214may be formed by a LPCVD process or any other suitable deposition process. The block oxide layer214may have a thickness of about 1 μm to about 10 μm, for example about 5 μm.

At block122, a metal deposition process is performed to form a metal gate layer216on the block oxide layer214, as shown inFIG. 2J. The metal gate layer216may have a thickness of about 100 μm to about 350 μm, for example about 200 μm. The metal gate layer216may be any electrically conductive material, such as metal or a metal alloy. Examples of a metal or metal alloy for use as a metal gate layer216may include, but is not limited to, aluminum, copper, tungsten, tantalum, titanium, cobalt, and any combinations thereof, and alloys of tungsten, aluminum, copper, cobalt and any combinations thereof. Thereafter, the metal gate layer216outside the trench218is removed to separate the metal gate layer from that of other memory cells, as shown inFIG. 2K.

After block122, a plurality of fabrication techniques may be employed to complete the memory device. For example, a lithography/etching process may be performed to pattern the metal gate layer216, the block oxide layer214, the charge trapping layer212, and the gate oxide layer208. A plurality of successive ion implantation processes may then be carried out to form a source/drain region (not shown) in or adjacent the channel layer210. Subsequently, the source/drain region is activated by a laser annealing process.

Benefits of the present disclosure include an improved charge trap flash (CTF) memory device having silicon germanium (SiGe) nanodots selectively grown on nitrides of oxide-nitride-oxide-nitride-oxide (“ONO”) structure. The use of charge trapping layer having SiGe nanodots embedded therein increase charge retention capability of the charge trapping layer, and reduces the issues of charge retention loss encountered in conventional floating-gate electrically erasable programmable read-only memory devices. It also allows for thinner gate oxide layer to be disposed underneath the charge trapping layer and, thereby, allowing for smaller operating voltages, better endurance and retention, and faster program/erase speed.