Switched current-cell with intermediate state

Representative implementations of devices and techniques provide digital-to-analog conversion of signals while minimizing switching related errors. Digital to analog converter (DAC) cells may be arranged to include one or more operating states in addition to binary output states, and may employ a switching technique to “dump” the DAC cell between binary outputs. Further, an array of DAC cells may include a partial set of redundant DAC cells for implementation of the switching technique.

BACKGROUND

Digital-to-analog converters (DACs, D/A-converters) constitute a basic building block in modern integrated-circuit (IC) design, since they form the ubiquitous digital-to-analog interface in digital transceivers and digitally aided control loops. Current steering DACs are used whenever a certain minimum sampling speed is required.

In general, a current-steering DAC responds to a digital input code by outputting a current that is proportional to the digital representation. Thus, the magnitude of the output current changes with changes to the digital input code. Moreover, in certain current-steering DACs that implement multiple current cells, any of the current cells may switch output states in response to a digital input code, producing a variable current output from a varying digital input.

In contrast to, for example, switched-capacitor realizations, standard implementations of current-steering DACs are be transparent for non-ideal error signals that are generated during code changes, i.e. when the DAC switches from one input code to the next. These errors may include switch injection, asymmetries in the ON/OFF transitions, settling of internal nodes, and other non-ideal effects generated during switching of the current cells. Because the number of current cells that switch during a transition is dependent on the input code sequence, nonlinear distortion may result from these effects.

DETAILED DESCRIPTION

Overview

Representative implementations of devices and techniques provide digital to analog conversion of signals while minimizing switching related errors. Digital to analog converter (DAC) cells may be arranged to include one or more operating states in addition to binary output states. This may be accomplished by adding one or more switched outputs to the DAC cell that have access to the output of the current source of the DAC cell. The additional operating states may include a “dump” state arranged to allow a modification to the internal capacitance charge or to the voltage at the output of the current source between binary output states. For example, a switching technique can be used to switch a DAC cell to a dump state before switching the polarity of the DAC cell from a positive state (e.g., “ON”) to a negative state (e.g., “OFF”), or vice versa. While in the dump state, the DAC cell may be discharged, pre-charged, reset, or the like.

Further, an array of DAC cells may be arranged to include a partial set of redundant DAC cells. With the addition of the redundant DAC cells, the switching algorithm can be applied on some or all of the DAC cells in the array, switching a DAC cell to a “dump” state before switching the polarity of the DAC cell between binary output states. In some implementations, a limited number of redundant cells is used in combination with the switching technique, resulting in “partial return-to-zero” functionality.

Various implementations for minimizing switching errors, including techniques and devices, are discussed with reference to the figures. The techniques and devices discussed may be applied to any of various DAC designs, circuits, and devices and remain within the scope of the disclosure.

Implementations are explained in more detail below using a plurality of examples. Although various implementations and examples are discussed here and below, further implementations and examples may be possible by combining the features and elements of individual implementations and examples.

Example DAC Cell

FIG. 1is schematic of an example DAC cell100in which the techniques in accordance with the present disclosure may be implemented. While the example DAC cell100is illustrated as a current-steering DAC cell and the disclosure discusses current-steering type DAC cells, various other types of DAC cells may employ techniques and/or devices discussed herein. Accordingly, the generic term “DAC cell” is used throughout.

The example DAC cell100ofFIG. 1is comprised of three switches (102,104, and106), illustrated as PMOS transistors. However, NMOS transistors, or other transistor types, may also be used to implement the switches (102,104, and106). The switches are also marked inFIG. 1according to their polarity. Switch102(“P”) is a positive (e.g., “ON”) state switch, switch104(“N”) is a negative (e.g., “OFF”) state switch, and switch106(“D”) is a “dump” state switch. In alternate implementations, as discussed further below, a DAC cell100may have additional switches as well.

The switches (102,104, and106) control the current output from the DAC cell100. Each of the switches (102,104, and106) is coupled at a first terminal (the source of the transistor, for example in the case of a PMOS transistor) to the output of a current source108. (The common node at the output of the current source108is shown inFIG. 1as node110.) Switches102and104are coupled at the second terminal (the drain of the transistor, for example in the case of a PMOS transistor) of the switches to the positive output (outp)112of the DAC cell100and the negative output (outn)114of the DAC cell100, respectively. Closing one of the switches102or104(based on a signal at the gate of the switch) couples the output of the current source108to outp112or outn114respectively, causing current to flow through the respective output and determining the output state (or output mode) of the DAC cell100.

Switch106is coupled at the second terminal (the drain of the transistor, for example) of the switch to a dump node116. In one implementation, switch106is arranged to discharge the parasitic capacitance118connected at the output of the current source108when closed. In alternate implementations, as will be discussed, switch106may be arranged to pre-charge or reset node110when closed. Thus, switch106may be used in conjunction with switching techniques to reset, normalize, pre-charge, discharge, etc. the DAC cell100between polarity changes to the DAC cell100.

As shown inFIG. 1, an internal capacitance (“Cs”)118associated with the current source108may exist in the DAC cell100. In an example, the capacitance Cs118is charged to a voltage that is dependent on the voltage at the drain of the transistor switch (102or104) that is active (e.g., closed, passing current). When the DAC cell100is switched from one output to the other output (i.e., outputs112and114), the voltage across the capacitance Cs118changes and the stored charge may flow into the active output, generating a signal dependent error that can limit the dynamic linearity of the DAC.

In one implementation, the capacitance Cs118is reset prior to the DAC cell100switching polarity. For example, Cs118may be discharged or pre-charged in order to make the charge flowing into the active output after the polarity change of the DAC cell100signal independent. In an implementation, discharging or pre-charging the DAC cell100comprises disconnecting (i.e., deactivating) both outputs (outp112and outn114) and connecting (i.e., activating) an intermediate output, i.e, the dump node116, before changing the DAC cell100output polarity. In other words, the switch106may be arranged to discharge a voltage at the output of the current source108(i.e., discharge Cs118) prior to one of switch102or switch104toggling when the other of switch102or switch104has toggled (i.e., a change in polarity of the DAC cell100). Alternately, the switch106may be arranged to pre-charge a voltage at the output of the current source108(i.e., pre-charge Cs118) prior to one of switch102or switch104toggling when the other of switch102or switch104has toggled.

FIG. 2is a schematic diagram illustrating one example of applying a switching technique to the DAC cell100ofFIG. 1. As illustrated inFIG. 2, in one example, the DAC cell100is discharged (or pre-charged) prior to changing a polarity of the DAC cell100from a positive output state to a negative output state. In the first (leftmost) step ofFIG. 2, switch102is closed and switches104and106are open. Current flows from the output of the current source108through switch102(as shown by the dashed arrow) and to outp112. The DAC cell100is in a positive output state.

In an implementation, information is received indicating that the DAC cell100is to change to the negative output state. As shown in the second (middle) step ofFIG. 2, switches102and104are open, and switch106closes. In this intermediate step, any charge associated with Cs118discharges through switch106(as shown by the dashed arrow) and to dump node116, assuming a constant potential at dump node116. In an alternate implementation, dump node and switch106may be used to pre-charge Cs118, as will be discussed further below. After this intermediate step, the charge on Cs118is no longer proportional to the voltage on outp112but rather to the voltage on the dump node116.

In the third (rightmost) step ofFIG. 2, switch104is closed and switches102and106are open. Current flows from the output of the current source108through switch104(as shown by the dashed arrow) and to outn114. The DAC cell100is now in a negative output state, having changed polarity. Any charge flowing from Cs118into the output outn114is now proportional to the voltage difference v(outn)−v(dump node) instead of v(outn)−v(outp). Thus, a reduced, if not eliminated, switching related charge error is associated with outn114.

Without the intermediate dump step, the dynamic charge error can be described as Q(k)=r·Cs·(vout(k)−vout(k−1)), where k is the switching instance, r is a factor to account for attenuation from the output to the source node110of the switches (102,104, and106) vout(k) is the voltage at the drain of the active switch at switching instance k and vout(k−1) is the voltage at the drain of the active switch at the last switching instance. If the DAC cell100does not change polarity at a switching instance, this error is zero. If the DAC cell100is switching, without the intermediate dump step, the error will be a function of the voltage difference of the output nodes and is signal dependent.

With the intermediate dump step, the dynamic error when connecting a DAC cell100to an output node via a switch is changed to Q(k)=r·Cs·(vout(k)−vdump). As long as (vout(k)−vdump)<(vout(k)−vout(k−1)), the dynamic error is reduced. This condition can be fulfilled if vdumpis the midscale voltage of the DAC cell100(i.e., the average of the voltages of outp112and outn114). The voltage difference at the switching instance is then half of what it is without the intermediate dump step.

In one implementation, the dynamic error is reduced further when the dump node116is arranged to follow the voltage of the next output node (e.g., outp112, outn114) to which the DAC cell100will activate. For example, if the DAC cell100is to make a polarity change from outn114to outp112in a next switching cycle, the dump node116is charged to the voltage at outp112prior to the polarity switch. The voltage difference at the switching instance can then be reduced to substantially zero, and no dynamic charge error is injected into the output node outp112. In some implementations, the dump node116voltage is generated such that the resulting charge error is signal independent, resulting in improved dynamic linearity of the DAC.

In one implementation, the DAC cell100includes a fourth switch (seeFIG. 6, “D2”) controlling a second dump node. The fourth switch D2is also arranged to have a first terminal coupled to the output of the current source108to discharge (or pre-charge) a voltage at the output of the current source108prior to one of switch102or switch104toggling when the other of switch102or switch104has toggled, or switch106has toggled. The fourth switch D2is discussed further below (with reference toFIGS. 6 and 7). In various implementations, the DAC cell100may alternately or additionally include other switches.

Example Switching Control

FIG. 3is a schematic of the example DAC cell100ofFIG. 1, implemented with control functionality. In an implementation, as shown inFIG. 3, a DAC cell100may be applied with a data decoder302arranged to determine timing for each of the switches (102,104, and106) to toggle. For example, a data decoder302may receive binary data or digital code, and may direct one or more of the switches102,104, and106to toggle based on the data received. In one implementation, the data decoder302may send control signals or the like to the switches102,104, and106to direct one or more of them to toggle. In the implementation illustrated inFIG. 3, signal lines connect the data decoder302to the gates of the switches102,104, and106, providing a path for control signals or the like.

In one implementation, the data decoder302directs the switch106to toggle after directing one of switch102or switch104to toggle and prior to directing the other of switch102or switch104to toggle. In other words, the data decoder302directs the DAC cell100to the dump state prior to directing the DAC cell100to change output polarity states.

In an implementation, as shown inFIG. 3, a DAC cell100may be applied with a voltage generator304. As illustrated, the voltage generator is coupled to an output terminal of switch106, i.e., the dump node. In an implementation, the voltage generator304is arranged to pre-charge node110at the output of the current source108. For example, the voltage generator304may pre-charge node110to a voltage substantially equal to an average of the voltage at output outp112and the output outn114, as discussed above. In another implementation, the voltage generator304may pre-charge node110to a voltage substantially equal to the voltage of the next output node (e.g., outp112, outn114) to which the DAC cell100will activate, as also discussed above. In various implementations to be discussed below, the voltage generator304may pre-charge node110to other voltages according to the applied switching technique.

In an implementation, as shown inFIG. 3, a DAC cell100may be applied with an optional digital processing component306. In various implementations, the digital processing component306may provide information to the voltage generator304regarding a “next output node” that the DAC cell100will be activating. For example, the digital processing component306may communicate to the voltage generator304that the DAC cell100will change output polarity in the next switching cycle. In one implementation, the digital processing component306may monitor the incoming data.

In various implementations, one or more of the data decoder302, voltage generator304, and digital processing component306, as well other components, may be implemented in hardware, firmware, software, or the like, or in combinations thereof.

Example DAC Cell Arrays

In an implementation, a DAC cell array may comprise a number of DAC cells100arranged in an array. In one implementation, the DAC cell array includes a first quantity of primary DAC cells and a second quantity of redundant DAC cells. In one implementation, the number of redundant DAC cells is a fraction of the number of primary DAC cells. Generally, the number of primary DAC cells is based on the type of signals processed by the DAC cell array, and the resolution desired. For example, a 5-bit DAC may have 25=32 DAC cells100, giving 32 possible output levels.

FIG. 4is an illustration showing how an example switching technique may be applied according to one implementation using an array of DAC cells100. The illustration shows a thermometer coded segment502representing an array of 40 DAC cells100. In the example, 31 of the 40 DAC cells100are primary DAC cells, representative of a 5-bit DAC. The other 9 DAC cells are redundant DAC cells for implementing a switching technique that uses a dump state, as discussed above. In various implementations, at least a portion of the DAC cells100in an array is in the dump state during each switching cycle. In the illustration, the array of 40 DAC cells100is shown in six different cases (A-F) for six different digital input codes d(n).

As shown in the example illustration ofFIG. 4, each of the primary DAC cells and the redundant DAC cells are in either a positive (“ON”) output state, a negative (“OFF”) output state, or a dump state. In one implementation, as seen inFIG. 4, the DAC cells100are linearly arranged so that the DAC cells100in the dump state are in between DAC cells100that are “ON” and DAC cells that are “OFF.” In the implementation, a switching technique (i.e., order) can be applied whereby a DAC cell100is switched to a dump state rather than being switched directly to an opposite polarity state, and a redundant DAC cell100that was previously in a dump state is switched to the opposite polarity state instead.

For example, if additional DAC cells100are needed in the positive state, based on a digital input in a next switching cycle, DAC cells100that were in a dump state in the previous switch cycle are set to the “ON” state. The same quantity of DAC cells100that were in the “OFF” state are switched to the dump state. Alternately, if fewer DAC cells100are needed in the positive state, based on the digital input in a next switching cycle, DAC cells100that were in a “ON” state in the previous switch cycle are set to the dump state. The same quantity of DAC cells100that were in the dump state are switched to the “OFF” state. Thus, in one implementation, the combined quantity of DAC cells100that is “ON” and “OFF” during any switch cycle stays constant. Also, in an implementation, the quantity of DAC cells100in the dump state remains constant for each switch cycle.

Referring toFIG. 4, at line A, a digital input value of 3 is represented by three “ON” state DAC cells100in the thermometer coded segment502. They are followed by nine “dump” state DAC cells and 28 “OFF” state DAC cells100. At line B, a digital input value of 12 is represented. To transition from the arrangement of line A to the arrangement of line B, nine DAC cells100that were in the dump state are switched to the “ON” state, making a total of 12 DAC cells100in the “ON” state. Additionally, nine DAC cells100that were in the “OFF” state are switched to the dump state, making a total of 31 DAC cells100that are “ON” and “OFF,” and a total of nine DAC cells100in the dump state.

At line C ofFIG. 4, a digital input value of 7 is represented. To transition from the arrangement of line B to the arrangement of line C, five DAC cells100that were in the “ON” state are switched to the dump state, making a total of seven DAC cells100in the “ON” state. Additionally, five DAC cells100that were in the dump state are switched to the “OFF” state, making a total of 31 DAC cells100that are “ON” and “OFF,” and a total of nine DAC cells100in the dump state. This technique continues for the other lines D-F.

In the implementation discussed, the DAC cells100in a given state are grouped in sets, and the sets are linearly arranged so that the DAC cells100in the dump state are in logically between DAC cells100that are “ON” and DAC cells100that are “OFF.” In this implementation, the DAC cells100that switch from “ON” to “dump” are those that are closest to the dump state DAC cells (the last ones in the “ON” set in the illustration). Additionally, the DAC cells100that switch from “dump” to “OFF” are those that are closest to the “OFF” state DAC cells (the first ones in the “OFF” set in the illustration). This technique generally prevents a DAC cell100from making a direct polarity switch without an intermediate step in a “dump” state and minimizes dynamic switch errors, provided that the digital input code step is smaller or at most equal to the number of redundant DAC cells in the array. Otherwise, there is an error related to the direct polarity switch of DAC cells, but it will be smaller than with the non-redundant standard implementation of a DAC-array.

The number of redundant DAC cells needed for full functionality of the discussed switching technique is max(d(k)−d(k−1))/dcellwhere d(k) is the digital input word at the sampling instance k and dcellis the normalized value of one DAC cell100in the array. In other words, the necessary number of redundant DAC cells100is related to the maximum derivative of the signal. For a known signal and a given DAC architecture, the number of redundant DAC cells100can be calculated.

In an alternate implementation, if the signal change is bigger than the number of available DAC cells100currently in the dump state, the additional number of DAC cells100that are needed may be switched directly to the opposite polarity, without an intermediate step. New “dump” DAC cells100that were “OFF” DAC cells100or “ON” DAC cells100are appended after the DAC cells100in the “ON” state, maintaining a constant quantity of combined “ON” and “OFF” DAC cells100and a constant quantity of “dump” state DAC cells100. In such an implementation, this is a partial fulfillment of the switching technique and, therefore, results in a partial charge error reduction.

Example Implementations

FIG. 5is a block diagram of a system500that includes a DAC cell array502(“array502”) and control functionality, according to an example implementation. The array502may be comprised of one or more DAC cells100(shown as DAC cells0to N inFIG. 5) as discussed above. Further, the switching techniques discussed above with reference toFIG. 4may be applied to the array502and one or more components of system500.

In one implementation, the system500may include an array502of DAC cells100comprising a first quantity of primary DAC cells and a second quantity of redundant DAC cells, where the second quantity is a fraction of the first quantity, as discussed above. In an implementation, each of the primary DAC cells and the redundant DAC cells are in one of a positive output state, a negative output state, or a dump state. Additionally, the array502may include one or more control components arranged to determine an output state for the DAC cells100during a switching cycle. For example, the control component(s) may be arranged to direct a DAC cell100to switch to the dump state prior to directing the DAC cell100to switch to one of the positive output state or the negative output state from the other of the positive output state or the negative output state. In one implementation, the control component(s) direct one or more DAC cells100to refrain from switching states during a switching cycle, at least for economic purposes.

In one implementation, as illustrated inFIG. 5, a control component is a data decoder302, as discussed above. Accordingly, the data decoder302may be arranged to generate control signals for the DAC cells100according to a digital input word (e.g., binary data). The control signals generated determine an output state for the DAC cells100during a switching cycle.

In one implementation, the system500may include a voltage digital-to-analog converter (VDAC)502, as illustrated inFIG. 5, or another type of voltage generator (such as voltage generator304). For the purposes of discussion regardingFIGS. 3-5and7of this disclosure, the terms VDAC502and voltage generator304are interchangeable, as describing a component that generates a signal applied at one or more dump nodes (such as dump node116). Accordingly, a voltage generator304may be arranged to apply a dump signal at an output of the DAC cells100associated with the dump state, as discussed above.

In an implementation, the voltage generator304is arranged to generate a dump signal based on an input signal to the array and/or an output signal of the array. For example, the dump signal may be based on data received from the data decoder302or from the dump node116. Accordingly, in various implementations, the dump signal generated may have different forms.

In one implementation, the dump signal voltage is substantially equal to a voltage to be output by the one or more DAC cells100during a next switching cycle. In another implementation, the voltage generator304is arranged to output a constant signal substantially equal to an average of a voltage output by a DAC cell100while in the positive state and a voltage output by the DAC cell100while in the negative state.

In a further implementation, the voltage generator304is arranged to generate a random dump signal applied at an output of the DAC cells100associated with the dump state. Alternately, the dump signal has a preset varying waveform. In further implementations, the voltage generator304may be arranged to generate other types and forms of dump signals that serve to reduce the dynamic switch error to greater or lesser degrees.

In the example illustrated inFIG. 5, the system500includes a dump data decoder504. In an implementation, the dump data decoder504may perform the functions of the digital processing component306as described with reference toFIG. 3. Optionally, the system500may include other control components such as a buffer506. A unity gain buffer506, or the like, may be used to improve the driving capability of the voltage generator304(or VDAC502) as to the properties of a dump signal to be generated.

FIGS. 6 and 7are block diagrams of a system600comprising an array602of DAC cells100. System600is functionally similar to system500described above, and may contain many or all of the same control components and/or functionality. Array602is functionally similar to array502, except the DAC cells100of array602are comprised of four or more switches and four or more outputs as described above with reference toFIG. 2. As mentioned above, DAC cells100of array602include at least dump switches D and D2. Accordingly there are at least two dump nodes (604and606).

In an implementation, the data decoder302determines which dump switch (D or D2) to use in a switching cycle. In one implementation, one dump switch (“D”) is used in association with the “ON” state of the DAC cell100and one dump switch (“D2”) is used in association with the “OFF” state of the DAC cell100. In another implementation, the dump node (604or606) with the voltage to which a DAC cell100is to be switched next is used for the dump operation in a switch cycle. In one implementation, both of the dump switches may be used in a switching cycle. For example, the DAC cell100may change from one output polarity to the other only after both dump nodes (604and606) are activated as intermediate states, either concurrently or consecutively.

The diagrams ofFIGS. 6 and 7show two possible approaches using a system600and an array602. In various implementations, the two approaches may be mixed, or another approach may be used to accomplish error reduction goals. In the approach ofFIG. 6, the dump node voltages are generated by buffering the output voltages of the DAC.

In the approach ofFIG. 7, a dual dump node design, for example, can also be realized with a voltage DAC504. In an implementation, the VDAC504is controlled by the data decoder302, generating dump node voltages that follow the output voltages. Thus, the DAC cells100are dumped to the dump node (604or606) that follows the voltage of the output to which they will be switched next.

In alternate implementations, one or more of the above techniques may be employed concurrently, or another technique may be used to accomplish the same or similar results. Further, in various implementations, one or more of the above techniques may be applied once each switching cycle or according to another timing scheme.

Representative Processes

FIG. 8illustrates a representative process800for implementing switching techniques for a DAC cell (such as the DAC cell100). The described techniques may also be used with an array (such as array500or600) of DAC cells100. An example process800comprises including an intermediate state when changing an output polarity of a DAC cell100, to minimize dynamic switch error. The process800is described with reference toFIGS. 1-7.

At block802, the process includes determining a present output mode of a DAC cell based on extant input data. For example, the DAC cell may be set to a positive, negative, or dump state, based on the input data currently being applied.

At block804, the process includes receiving next data directing the DAC cell to switch from the present output mode to a next output mode during a subsequent switching cycle. In some cases the next output mode may be the same as the present output mode. In other cases, the next output mode may be an opposite polarity mode.

At block806, the process includes switching the DAC cell to a third output mode if the next output mode is an opposite polarity mode. The third output mode comprises an intermediate state that is applied rather than directly changing the output polarity of the DAC cell. In one implementation, the process includes deactivating a positive output of the DAC cell and a negative output of the DAC cell and activating an intermediate output of the DAC cell prior to changing an output polarity of the DAC cell.

In one implementation, where there are at least two dump nodes associated with a DAC cell, the process includes deactivating the intermediate output of the DAC cell and activating a second intermediate output of the DAC cell prior to changing an output polarity of the DAC cell.

At block808, the process includes modifying a charge on an interior capacitance of the DAC cell based on the next data. For example, modifying the charge may include one of resetting, discharging, or pre-charging the interior capacitance of the DAC cell based on the next data. In one implementation, the process includes monitoring a signal derivative of the next data, and modifying the charge on the interior capacitance of the DAC cell based on the signal derivative.

In an implementation, the process includes pre-charging the interior capacitance of the DAC cell to a voltage that is substantially equal to half of a difference between a voltage at the positive output of the DAC cell and a voltage at the negative output of the DAC cell. Alternately, the process may include pre-charging the interior capacitance of the DAC cell to a voltage that is substantially equal to a voltage at an output of the DAC cell associated with the next output mode. Accordingly, some information regarding the next output mode may be provided by one or more control components, as discussed above.

At block810, the process includes switching the DAC cell to the next output mode. Once the intermediate step is accomplished, and the interior capacitance charge is modified if desired, the DAC cell may be switched with reduced error.

FIG. 9illustrates a representative process900for implementing switching techniques for an array (such as array500or600) of DAC cells100. An example process900comprises the use of redundant DAC cells100when including an intermediate state to change an output polarity of a DAC cell100. The process900is described with reference toFIGS. 1-7.

At block902, the process includes arranging a first quantity of primary DAC cells and a second quantity of redundant DAC cells in an array. In one example, the second quantity is a fraction of the first quantity. In one implementation, the second quantity is based on a maximum derivative of a signal being processed by the array of DAC cells.

At block904, the process includes setting each of the DAC cells in one of a positive output state, a negative output state, or a dump state based on a first digital word. Each bit of the first digital word is represented by at least one DAC cell. In one implementation, a quantity of DAC cells in the dump state remains constant during each switching cycle and/or a combination sum of DAC cells in the “ON” and “OFF” states is constant during each switching cycle.

At block906, the process includes receiving a next digital word during a switching cycle. The next digital word informs the DAC cells as to the next output state of the DAC cells. In response to receiving the next digital word, the process includes switching one or more DAC cells from the positive output state to the dump state, from the negative output state to the dump state, or from the dump state to one of the positive output state or the negative output state, based on the next digital word.

In one implementation, the process includes detecting the next digital word prior to the next switching cycle, and discharging or pre-charging the one or more DAC cells based on the next digital word prior to the next switching cycle.

At block908, the process includes switching one or more DAC cells to the dump state prior to switching the one or more DAC cells to an opposite polarity state in response to the next digital word.

In an implementation, the process includes arranging the array of DAC cells in a linear order comprising: a first set comprising positive output state DAC cells; a next set comprising dump state DAC cells; and a last set comprising negative output state DAC cells. When switching an output state of one or more positive output state DAC cells, the process includes switching the positive output state DAC cells within the first set in an order from last to first. Also or alternatively, when switching an output state of one or more negative output state DAC cells, the process may include switching the negative output state DAC cells within the last set in an order from first to last.

The order in which the processes800and900are described is not intended to be construed as a limitation, and any number of the described process blocks can be combined in any order to implement the processes, or alternate processes. Additionally, individual blocks may be deleted from the processes without departing from the spirit and scope of the subject matter described herein. Furthermore, the processes can be implemented in any suitable hardware, software, firmware, or a combination thereof, without departing from the scope of the subject matter described herein.

In alternate implementations, other techniques may be included in the processes800and900in various combinations, and remain within the scope of the disclosure.

CONCLUSION

Although the implementations of the disclosure have been described in language specific to structural features and/or methodological acts, it is to be understood that the implementations are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing the invention.