Apparatus and associated methods relate to quasi-adiabatic logic gates in which at least one supply terminal receives a periodic power signal. The quasi-adiabatic logic gate is configured to perform a specific logic function operative upon one or more input signals. When the quasi-adiabatic logic gate switches the output from one logic state to another logic state, the transient switching portion of the output signal substantially tracks the periodic supply signal. Such a periodic supply signal can be one that transitions gradually between low and high voltage levels. Such periodic supply signals results in a transient switching portion of the logic signal having lower frequency components than have traditional CMOS logic gate transients. The quasi-adiabatic logic gate has a periodic clock signal that is not in phase with the periodic power signal.

BACKGROUND

Conventional CMOS logic circuits are powered between two DC power buses. The CMOS logic circuits are configured to perform specific logic functions based on input signals received thereby. When the input signals change such that the output signal indicative of the logic function operating on such signals must change, the output rapidly changes states. Such rapid transient portions of the output signal can cause pulses of current with high peak magnitudes. Such high peak current magnitudes can cause the supplies to momentarily collapse. Furthermore, during the transient portions of switching, both pullup and pulldown circuitry can be conductively providing a path for current to flow directly from one supply to another supply. Such current is sometimes called crowbar current. Crowbar current is wasted, in that such current is not used to charge parasitic capacitance of the subsequent logic gates.

SUMMARY

Apparatus and associated methods relate to a quasi-adiabatic logic gate. The quasi-adiabatic logic gate includes first and second clock input terminals configured to receive complementary first and second periodic clock signals, respectively. The quasi-adiabatic CMOS logic gate includes one or more logic input terminals configured to receive one or more corresponding logic input signals. The quasi-adiabatic CMOS logic gate includes a logic output terminal configured to output a logic output signal. The quasi-adiabatic CMOS logic gate includes a pullup network including one or more pullup transistors configured to perform a pullup logic function. Each of the one or more pullup transistors of the pullup network has a control node coupled to a corresponding one of the logic input terminals. The pullup network is configured to modulate conductivity between a first supply node and an intermediate pullup node based on the pullup logic function that the pullup network is configured to perform and the logic input signals received on the logic input terminals. The quasi-adiabatic CMOS logic gate includes a pulldown network having one or more pulldown transistors configured to perform a pulldown logic function that is the complement of the pullup logic function performed by the pullup network. Each of the one or more pulldown transistors of the pulldown network has a control node coupled to a corresponding one of the logic input terminals. The pulldown network is configured to modulate conductivity between a second supply node and an intermediate pulldown node based on the pulldown logic function that the pulldown network is configured to perform and the logic input signals received on the logic input terminals. The quasi-adiabatic CMOS logic gate includes a pullup clocking transistor having a pullup control node coupled to the first clock terminal. The pullup clocking transistor has a control node coupled to the first clock input terminal. The pullup clocking transistor is configured to modulate conductivity, based on the first periodic clock signal received on the first clock terminal, between the intermediate pullup node and a logic output terminal. The quasi-adiabatic CMOS logic gate includes a pulldown clocking transistor having a pulldown control node coupled to the second clock terminal. The pulldown clocking transistor has a control node coupled to the second clock input terminal. The pulldown clocking transistor is configured to modulate conductivity, based on the second periodic clock signal received on the second clock terminal, between the intermediate pulldown node and a logic output terminal. The first supply node is periodically driven by a first supply signal in a lagging phase relation with the second periodic clock signal. The second supply node is periodically driven by a second supply signal in a lagging phase relation with and the first clock signal.

DETAILED DESCRIPTION

Apparatus and associated methods relate to quasi-adiabatic logic gates in which at least one supply terminal receives a periodic power signal. The quasi-adiabatic logic gate is configured to perform a specific logic function operative upon one or more input signals. When the quasi-adiabatic logic gate switches the output from one logic state to another logic state, the transient switching portion of the output signal substantially tracks the periodic supply signal. Such a periodic supply signal can be one that transitions gradually between low and high voltage levels. Such periodic supply signals results in a transient switching portion of the logic signal having lower frequency components than have traditional CMOS logic gate transients. The quasi-adiabatic logic gate has a periodic clock signal that is not in phase with the periodic power signal.

FIG.1is a schematic diagram of a quasi-adiabatic CMOS inverter. InFIG.1, quasi-adiabatic inverter10has first and second clock input terminals12and14, logic input terminal16, and logic output terminal18. Quasi-adiabatic inverter10includes pullup network20, pulldown network22, pullup clocking device24, and pulldown clocking device26. Capacitor28can represent parasitic capacitances associated with logic output terminal18, such as, for example, drain capacitances associated with pullup and pulldown clocking devices24and26, metallization capacitances, and gate capacitances associated with logic gates connected to logic output terminal18. Also depicted are complementary sinusoidal supplies30and32.

Pullup network20and pulldown network22are simply a PMOS and NMOS Field Effect Transistor (FET), respectively. Such PMOS and NMOS devices are configured to provide an inverter logic function. Because logic gate10is configured to invert a logic signal, control nodes (e.g., gates of the PMOS and NMOS devices) for both pullup and pulldown networks20and22are conductively coupled to input logic terminal16. For more complicated logic functions, pullup and pulldown networks20and22can include more than a single FET. For example, a two input NAND gate could be realized using two parallel connected NMOS FETs for pulldown network22and two series connected PMOS FETs for pullup network20. Pullup and pulldown networks20and22are complementary, in that either one or the other, but not both, provides a conduction path between output terminal18and its respective supply node NS1or NS2.

Pullup network20is configured to modulate conductivity between first supply node NS1and intermediate pullup node NINT1based on the pullup logic function that pullup network20is configured to perform and the logic input signals received on logic input terminal16. Similarly, pulldown network22is configured to modulate conductivity between second supply node NS2and intermediate pulldown node NINT2based on the pulldown logic function that pulldown network22is configured to perform and the logic input signals received on logic input terminal16.

Pullup clocking device24has a pullup control node (e.g., the gate of the depicted PMOS device) coupled to first clock input terminal12. Pullup clocking device24is configured to modulate conductivity, based on a first sinusoidal clock signal received on first clock input terminal12, between intermediate pullup node NINT1and logic output terminal18. Pulldown clocking device26has a pulldown control node (e.g., the gate of the depicted NMOS device) coupled to second clock input terminal14. Pulldown clocking device26is configured to modulate conductivity, based on a second sinusoidal clock signal received on second clock input terminal14, between intermediate pulldown node NINT2and logic output terminal18.

What renders the above described logic gate10a quasi-adiabatic logic gate is the non-DC supply signal applied to either or both of supply nodes NS1and NS2. As depicted inFIG.1, complementary sinusoidal supply signals are generated by complementary sinusoidal supplies30and32. First supply node NS1is sinusoidally driven by a first supply signal in phase with the second sinusoidal clock signal received on second clock input terminal14. In some embodiments, first supply node NS1can be conductively coupled to second clock input terminal14. Second supply node NS2is sinusoidally driven by a second supply signal in phase with and the first clock signal received on first clock input terminal12. In some embodiments, second supply node NS2can be conductively coupled to first clock input terminal12.

In some embodiments the first and second supply signals can be complementary in that each of the first and second supply signals sinusoidally oscillate between the same DC voltage levels (e.g., VDD and VSS), but are approximately 180 degrees out of phase with one another. In some embodiments, only the first supply signal is non-DC. In other embodiments, only the second supply signal is non-DC. In some embodiments, first and second supply signals are sinusoids that are approximately 180 degrees out of phase with one another, but oscillate between voltage levels that are different for each of the first and second supply signals. For example the first supply signal can oscillate between VDD and a mid-level supply (e.g., the mean voltage between VDD and VSS). The second supply signal can then oscillate between the mid-level supply and VSS.

In some embodiments, the non-DC signal can be something other than sinusoidal. For example, in some embodiments, a non-DC signal can be created in a step-wise fashion. The stepwise signal can mimic a sinusoid or some other non-DC waveform. In some embodiments, a triangular or trapezoidal waveform can be used to provide power to quasi-adiabatic logic gates.

In some embodiments, the bodies of the devices of pullup network20and pullup clocking device24can be conductively coupled to first supply node NS1as depicted. In other embodiments, the bodies of the devices of pullup network20and pullup clocking device24can be conductively coupled to another biasing node. For example, the bodies of the devices of pullup network20and pullup clocking device24can be conductively coupled to VDD. In other embodiments the bodies of the devices of pullup network20and pullup clocking device24can be conductively coupled via diodes to both first supply node NS1and output logic terminal18. Such a diode connection can ensure that the bodies of the devices of pullup network20and pullup clocking device24are not more than one diode voltage level below the voltage level of whichever of first supply node NS1and output logic terminal18that has the more positive voltage level.

Similarly, the bodies of the devices of pulldown network22and pulldown clocking device26can be conductively coupled via diodes to both second supply node NS2and output logic terminal18. Such a diode connection can ensure that the bodies of the devices of pulldown network22and pulldown clocking device26are not more than one diode voltage level above the voltage level of whichever of second supply node NS2and output logic terminal18that has the more negative voltage level.

FIG.2is a graph of input and output signals of two series-connected quasi-adiabatic CMOS inverters, such as is depicted inFIG.1and connected as shown inFIG.6. Each of the two series-connected quasi-adiabatic CMOS inverters10-1and10-2are provided sinusoidal supply signals and sinusoidal clock signals that are out of phase with one another. For example, the first sinusoidal clock signal is provided to first clock terminal12of the first of the two series-connected quasi-adiabatic CMOS inverters, but to second clock terminal14of the second of the two series-connected quasi-adiabatic CMOS inverters. Conversely, the second sinusoidal clock signal is provided to second clock terminal14of the first of the two series-connected quasi-adiabatic CMOS inverters, but to first clock terminal12of the second of the two series-connected quasi-adiabatic CMOS inverters.

Similarly, the first supply signal is provided to first supply node NS1of the first of the two series-connected quasi-adiabatic CMOS inverters, but to second supply node NS2of the second of the two series-connected quasi-adiabatic CMOS inverters. Lastly, the second supply signal is provided to second supply node NS2of the first of the two series-connected quasi-adiabatic CMOS inverters, but to first supply node NS1of the second of the two series-connected quasi-adiabatic CMOS inverters. In this way, the second of the two series-connected quasi-adiabatic CMOS inverters transitions between logic states 180 degrees after the first of the two series-connected quasi-adiabatic CMOS inverters transitions between logic states.

InFIG.2, graph40includes horizontal axis42, vertical axis44, and voltage/time relations46,48,50and52. Horizontal axis42is indicative time, and vertical axis44is indicative of voltage. Voltage/time relation46is indicative of a first sinusoidal supply signal, that oscillates between VDD and VSS (2.0 volts and zero volts, respectively, in the graph depicted). Voltage/time relation48is indicative of a second sinusoidal supply signal, that oscillates between VDD and VSS. Voltage/time relations46and48are complementary in that they are 180 degrees out of phase with one another.

Voltage/time relation50is indicative of the output voltage of a first of the two series-connected quasi-adiabatic CMOS inverters. Voltage/time relation52is indicative of the output voltage of a second of the two series-connected quasi-adiabatic CMOS inverters. As is depicted inFIG.2, the output logic signal indicated by voltage/time relation50is sufficient to cause the second of the series-connected quasi-adiabatic CMOS inverters to produce a proper output signal.

FIG.3is a schematic diagram of a quasi-adiabatic unipolar inverter. InFIG.3, inverter60includes clock input terminals62and63, logic input terminal64, and logic output terminal66. First clock input terminal62is configured to receive a clock signal. Logic input terminal64is configured to receive a logic input signal of a binary logical nature. Logic output terminal66is configured to output a logic output signal of a binary logical nature. Inverter60also includes logic network68that, in the depicted embodiment (i.e. for an inverter) includes a single device of a unipolar type. Logic network68is configured to perform the inverter logic function. The devices of logical network68has a control node (e.g., gate) coupled to logic input terminal64. Logic network68is configured to modulate conductivity, based on the configured logic function (e.g., inverter) and the logic input signal received on logic input terminal64, between second supply node NS2(e.g., GND) and pre-evaluation net NPRE. Also depicted are complementary sinusoidal supplies30and32.

Inverter60includes logic clocking device70of the unipolar type having an input node (e.g., source/drain) coupled to pre-evaluation net NPRE, a control node (e.g., gate) conductively coupled to first clock input terminal62, and an output node (e.g., source/drain) coupled to logic output terminal66. Logic clocking device70is configured to modulate conductivity, based on the received clock signal on first clock input terminal62, between pre-evaluation net NPREand logic output terminal66.

Inverter60includes logic-complement clocking device72of the unipolar type having an input node (e.g., source/drain) coupled to first supply node NS1(e.g., VDD), a control node (e.g., gate) capacitively coupled, via capacitor74, to second clock input terminal63and conductively coupled to pre-evaluation net NPRE, and an output node (e.g., source/drain) coupled to logic output terminal66, logic-complement clocking device72configured to modulate conductivity, based on the received clock signal on second clock input terminal63, between second supply node NS2and logic output terminal66.

In the depicted embodiment, pre-evaluation net NPREcan be charged to a voltage substantially above a voltage of second supply node NS2when the clock signal received on second clock input terminal63transitions from low to high and the conductivity of the logic network is low. If, however, the conductivity of the logic network is high or the clock signal received on second clock input terminal63transitions from high to low, the voltage of the pre-evaluation net will be not significantly above second supply node NS2. If the unipolar type of the depicted devices68,70, and72is N-type, pre-evaluation net must have a voltage significantly above a voltage of second supply node NS2for logic-complement clocking device72to turn on and to provide a high conductivity path between first supply node VS1and logic output terminal66.

What renders the above described logic gate60a quasi-adiabatic logic gate is the non-DC supply signal applied to either or both of supply nodes NS1and NS2. As depicted inFIG.3, complementary sinusoidal supply signals are generated by complementary sinusoidal supplies30and32. First supply node NS1is sinusoidally driven by a first supply signal in phase with a first sinusoidal clock signal received on first clock input terminal62. In some embodiments, first supply node NS1can be conductively coupled to first clock input terminal62. Second supply node NS2is sinusoidally driven by a second supply signal in phase with the second clock signal received on second clock input terminal63. In some embodiments, second supply node NS2can be conductively coupled to second clock input terminal63.

In some embodiments the first and second supply signals can be complementary in that each of the first and second supply signals sinusoidally oscillate between the same DC voltage levels (e.g., VDD and VSS), but are approximately 180 degrees out of phase with one another. In some embodiments, only the first supply signal is non-DC. In other embodiments, only the second supply signal is non-DC. In some embodiments, first and second supply signals are sinusoids that are approximately 180 degrees out of phase with one another, but oscillate between voltage levels that are different for each of the first and second supply signals. For example the first supply signal can oscillate between VDD and a mid-level supply (e.g., the mean voltage between VDD and VSS). The second supply signal can then oscillate between the mid-level supply and VSS.

In some embodiments, the first and second clock signals provided to first and second clock terminals62and63, respectively will oscillate between VDD and VSS, while the first and second supply signals will oscillate between the mid-level supply and the respective supply voltage VDD or VSS.

In some embodiments, the bodies of one or more of unitary devices68,70and72can be conductively coupled to second supply node NS2or NS1as depicted. In other embodiments, the bodies of unitary devices68,70and72can be conductively coupled to another biasing node. For example, the bodies of unitary devices68,70and72can be conductively coupled to VSS. In other embodiments, unitary devices68,70and72can be conductively coupled via diodes to both second supply node NS2and output logic terminal18. Such a diode connection can ensure that the bodies of the devices of pulldown network22and pulldown clocking device26are not more than one diode voltage level above the voltage level of whichever of second supply node NS2and output logic terminal18that has the more negative voltage level.

FIG.4is a graph of input and output signals of a quasi-adiabatic unipolar inverter, such as is depicted inFIG.3, and connected as shown inFIG.7. As was the case for the two series-connected adiabatic CMOS inverters above, series-connected quasi-adiabatic unipolar inverters60-1and60-2are alternately provided sinusoidal supply signals that are complementary to adjacent logic gates. For example, the first sinusoidal clock signal is provided to first clock terminal62of a first of two series-connected quasi-adiabatic unipolar inverters, but to second clock terminal63of a second of the two series-connected quasi-adiabatic unipolar inverters. Conversely, the second sinusoidal clock signal is provided to second clock terminal63of the first of the two series-connected quasi-adiabatic unipolar inverters, but to first clock terminal62of the second of the two series-connected quasi-adiabatic unipolar inverters.

Similarly, the first supply signal is provided to first supply node NS1of the first of the two series-connected quasi-adiabatic unipolar inverters, but to second supply node NS2of the second of the two series-connected quasi-adiabatic unipolar inverters. Lastly, the second supply signal is provided to second supply node NS2of the first of the two series-connected quasi-adiabatic unipolar inverters, but to first supply node NS1of the second of the two series-connected quasi-adiabatic unipolar inverters. In this way, the second of the two series-connected quasi-adiabatic unipolar inverters transitions between logic states 180 degrees after the first of the two series-connected quasi-adiabatic unipolar inverters transitions between logic states.

InFIG.4, graph80includes horizontal axis82, vertical axis84, and voltage/time relations86,88,90and92. Horizontal axis82is indicative time, and vertical axis84is indicative of voltage. Voltage/time relation86is indicative of a first sinusoidal supply signal, that oscillates between VDD and mid-level voltage (0.8 volts and 0.4 volts, respectively, in the graph depicted). Voltage/time relation88is indicative of a second sinusoidal clock signal, that oscillates between mid-level voltage and VSS. Voltage/time relations86and88are complementary in that they are 180 degrees out of phase with one another, even though they oscillate between different voltage levels from one another.

Voltage/time relation90is indicative of the logic input voltage of quasi-adiabatic unipolar inverter. Voltage/time relation92is indicative of the output voltage of the quasi-adiabatic unipolar inverter. As is depicted inFIG.4, the output logic signal indicated by voltage/time relation50is sufficient to cause any subsequently-connected quasi-adiabatic unipolar inverters to produce a proper output signal.

FIG.5is a schematic diagram depicting sinusoidally driven power provided to a quasi-adiabatic logic gate via inductors. InFIG.5, adiabatic system100includes first sinusoidal power generator102, second sinusoidal power generator104, logic circuitry106, and inductors108and110. Logic circuitry106has first and second supply nodes NS1and NS2, logic input terminals A and B, clock input terminal φ, and logic output terminal V0. First and second sinusoidal power generators generate power that is out of phase with one another. Such complementary power signals are provided to logic circuitry106via inductors108and110. Inductors108and110effectively create a tank circuit with capacitance C, which represents the parasitic capacitance of all internal nodes that are switched in response to one or more clock signals provided to clock input terminal φ. Inductors108and110can be tuned to match capacitance C and the switching frequency of the one or more clock signals provided to clock input terminal φ, so as to conserve charge.

In some embodiments, only one inductor will be used to provide power to only one of first and second supply nodes NS1and NS2. In some embodiments, capacitance C and/or inductors108and110can be tuned so as to minimize power consumption of adiabatic system100.

FIG.6is a schematic diagram of two quasi-adiabatic CMOS inverters connected in series. InFIG.6, each of quasi-adiabatic inverters10-1and10-2has first and second clock input terminals12and14, logic input terminal16, and logic output terminal18. Each of quasi-adiabatic inverter10-1and10-2includes pullup network20, pulldown network22, pullup clocking device24, and pulldown clocking device26. Capacitors28can represent parasitic capacitances associated with logic output terminal18, such as, for example, drain capacitances associated with pullup and pulldown clocking devices24and26, metallization capacitances, and gate capacitances associated with logic gates connected to logic output terminal18. Also depicted are complementary sinusoidal supplies30and32.

Pullup networks20and pulldown networks22are simply PMOS and NMOS Field Effect Transistors (FET), respectively. Such PMOS and NMOS devices are configured to provide an inverter logic function. Because logic gates10-1and10-2are configured to invert a logic signal, control nodes (e.g., gates of the PMOS and NMOS devices) for both pullup and pulldown networks20and22are conductively coupled to input logic terminal16. For more complicated logic functions, pullup and pulldown networks20and22can include more than a single FET. For example, a two input NAND gate could be realized using two parallel connected NMOS FETs for pulldown network22and two series connected PMOS FETs for pullup network20. Pullup and pulldown networks20and22are complementary, in that either one or the other, but not both, provides a conduction path between output terminal18and its respective supply node NS1or NS2of each of quasi-adiabatic CMOS inverters10-1and10-2. In such embodiments, the phase of the supply signals applied to quasi-adiabatic CMOS inverters10-1and10-2are 180 degrees out of phase with each other.

Pullup networks20are configured to modulate conductivity between first supply nodes NS1and intermediate pullup nodes NINT1based on the pullup logic function that pullup networks20are configured to perform and the logic input signals received on logic input terminals16. Similarly, pulldown networks22are configured to modulate conductivity between second supply nodes NS2and intermediate pulldown nodes NINT2based on the pulldown logic functions that pulldown networks22are configured to perform and the logic input signals received on logic input terminal16.

Pullup clocking devices24have a pullup control node (e.g., the gate of the depicted PMOS device) coupled to first clock input terminal12. Pullup clocking devices24are configured to modulate conductivity, based on first sinusoidal clock signals received on first clock input terminals12, between intermediate pullup nodes NINT1and logic output terminals18. Pulldown clocking device26have a pulldown control node (e.g., the gate of the depicted NMOS device) coupled to second clock input terminals14. Pulldown clocking devices26are configured to modulate conductivity, based on second sinusoidal clock signals received on second clock input terminals14, between intermediate pulldown nodes NINT2and logic output terminals18.

What renders the above-described logic gates10-1and10-2quasi-adiabatic logic gates is the non-DC supply signal applied to either or both of supply nodes NS1and NS2. Above, with regard toFIGS.1and3, the phases of the supply signals and the clock signals were described as in phase with each other. With regard to theFIGS.6and8embodiments, phase differences between the supply signals and the clock signals will be described. As in the embodiment depicted inFIG.1, complementary sinusoidal supply signals are generated by complementary sinusoidal supplies30and32. First supply node NS1of first quasi-adiabatic logic gate10-1is sinusoidally driven by first supply signal CLK-PS lagging in phase by a predetermined phase difference to the second sinusoidal clock signal CLK-A received on second clock input terminal14. Second supply node NS2is sinusoidally driven by a second supply signalCLK-PS, which is 180 degrees out of phase with first supply signal CLK-PS and lagging in phase by a predetermined phase difference to the second sinusoidal clock signalCLK-Areceived on first clock input terminal12. Phase timing between the supply signals CLK-PS andCLK-PSand the clock signals CLK-A andCLK-Acan be used to optimize the response time of quasi-adiabatic logic gates10-1and10-2. Second quasi-adiabatic logic gate10-2has supply signals and clock signals that are 180 degrees out of phase with those used for quasi-adiabatic logic gate10-1. Adjacent quasi-adiabatic logic gates are configured to receive such complementary supply signals and clocking signals. Thus, a series of series of logic gates will be provided power signals and clock signals in an alternating fashion, with first, third, fifth, etc. gates receiving power signals and clock signals in a first configuration and second, fourth, sixth, etc. gates receiving power signals and clock signals in a second configuration complementary to the first configuration.

The phase difference between the leading clock signals and the lagging supply signals can optimize response time of quasi-adiabatic logic gates10-1and10-2. By advancing clock signals provided to clock input terminals14and12, so as to lead supply signals provided to supply terminals NS1and NS2, respectively, the response times of quasi-adiabatic logic gates10-1and10-2can be optimized. By advancing the clock signals provided to clock input terminals14and12with respect to the supply signals provided to supply terminals NS1and NS2, pullup clocking device24and pulldown clocking device26can transition from sub-threshold operation to super-threshold operation more quickly than if the clock and supply signals are in phase with one another. Because of this, the output signal is presented at an earlier time, with regard to the supply signal, when the clock signal leads the supply signal within a range of leading phase-shift values. In some embodiments, a phase difference between the leading clock signals and their corresponding supply signals can be between 2 and 50% if a period. In other embodiments, such a phase difference can be between 5 and 30% or between 10 and 20%, for example.

In some embodiments, the first and second supply signals can be complementary in that each of the first and second supply signals sinusoidally oscillate between the same DC voltage levels (e.g., VDD and VSS), but are approximately 180 degrees out of phase with one another. In some embodiments, only the first supply signal is non-DC. In other embodiments, only the second supply signal is non-DC. In some embodiments, first and second supply signals are sinusoids that are approximately 180 degrees out of phase with one another, but oscillate between voltage levels that are different for each of the first and second supply signals. For example, the first supply signal can oscillate between VDD and a mid-level supply (e.g., the mean voltage between VDD and VSS). The second supply signal can then oscillate between the mid-level supply and VSS.

In some embodiments, the non-DC signal can be something other than sinusoidal. For example, in some embodiments, a non-DC signal can be created in a step-wise fashion or piecewise linear fashion. The stepwise or piecewise linear signal can mimic a sinusoid or some other non-DC waveform. In some embodiments, a triangular or trapezoidal waveform can be used to provide power to quasi-adiabatic logic gates.

In some embodiments, the bodies of the devices of pullup network20and pullup clocking device24can be conductively coupled to first supply node NS1as depicted. In other embodiments, the bodies of the devices of pullup network20and pullup clocking device24can be conductively coupled to another biasing node. For example, the bodies of the devices of pullup network20and pullup clocking device24can be conductively coupled to VDD. In other embodiments the bodies of the devices of pullup network20and pullup clocking device24can be conductively coupled via diodes to both first supply node NS1and output logic terminal18. Such a diode connection can ensure that the bodies of the devices of pullup network20and pullup clocking device24are not more than one diode voltage level below the voltage level of whichever of first supply node NS1and output logic terminal18that has the more positive voltage level.

Similarly, the bodies of the devices of pulldown network22and pulldown clocking device26can be conductively coupled via diodes to both second supply node NS2and output logic terminal18. Such a diode connection can ensure that the bodies of the devices of pulldown network22and pulldown clocking device26are not more than one diode voltage level above the voltage level of whichever of second supply node NS2and output logic terminal18that has the more negative voltage level.

Additional performance improvements can be achieved by optimizing the body bias of pullup network20, pulldown network22, pullup clocking device24, and pulldown clocking device26. PMOS devices of such networks can have bodies biased at voltages different than a voltage of first supply signal applied to first supply terminal NS1. As the voltage of such body biasing increases with respect to the voltage of first supply signal applied to first supply terminal NS1, the PMOS devices become more conductive. Therefore, the speed can improve when the biasing of such PMOS devices is of a voltage that exceeds the voltage of first supply signal. Similarly, as the voltage of body biasing decreases with respect to the voltage of second supply signal applied to second supply terminal NSs, NMOS devices of pulldown network22and pulldown clocking device26become more conductive.

Even further performance improvements can be made by increasing the supply voltages, with respect to the threshold voltages of the PMOS and NMOS devices. Quasi-adiabatic logic, as disclosed herein, can be operated at higher relative voltages (i.e., with respect to threshold voltages) than non-adiabatic logic, without incurring as much of a power cost. In some embodiments, a difference between the first and second DC voltages can be greater than two, five, of ten times a threshold voltage of the PMOS pullup and/or NMOS pulldown transistors.

FIG.7is a schematic diagram of two quasi-adiabatic unipolar inverters connected in series. InFIG.7, each of inverters60-1and80-2includes clock input terminals62and63, logic input terminal64, and logic output terminal66. Each of first clock input terminals62is configured to receive a clock signal. Each of logic input terminals64is configured to receive a logic input signal of a binary logical nature. Logic output terminals66are configured to output logic output signals of a binary logical nature. Each of inverters60-1and60-2also includes logic network68that, in the depicted embodiment (i.e. for an inverter) includes a single device of a unipolar type. Each of logic networks68is configured to perform the inverter logic function. The device of each of logical networks68has a control node (e.g., gate) coupled to logic input terminal64. Each of logic networks68is configured to modulate conductivity, based on the configured logic function (e.g., inverter) and the logic input signal received on logic input terminal64, between second supply node NS2(e.g., GND) and pre-evaluation net NPRE. Also depicted are complementary sinusoidal supplies30and32.

Each of inverters60-1and60-2includes logic clocking device70of the unipolar type having an input node (e.g., source/drain) coupled to pre-evaluation net NPRE, a control node (e.g., gate) conductively coupled to first clock input terminal62, and an output node (e.g., source/drain) coupled to logic output terminal66. Logic clocking device70is configured to modulate conductivity, based on the received clock signal on first clock input terminal62, between pre-evaluation net NPREand logic output terminal66.

Inverter60includes logic-complement clocking device72of the unipolar type having an input node (e.g., source/drain) coupled to first supply node NS1(e.g., VDD), a control node (e.g., gate) capacitively coupled, via capacitor74, to second clock input terminal63and conductively coupled to pre-evaluation net NPRE, and an output node (e.g., source/drain) coupled to logic output terminal66, logic-complement clocking device72configured to modulate conductivity, based on the received clock signal on second clock input terminal63, between second supply node NS2and logic output terminal66.

In the depicted embodiment, pre-evaluation net NPREcan be charged to a voltage substantially above a voltage of second supply node NS2when the clock signal received on second clock input terminal63transitions from low to high and the conductivity of the logic network is low. If, however, the conductivity of the logic network is high or the clock signal received on second clock input terminal63transitions from high to low, the voltage of the pre-evaluation net will be not significantly above second supply node NS2. If the unipolar type of the depicted devices68,70, and72is N-type, pre-evaluation net must have a voltage significantly above a voltage of second supply node NS2for logic-complement clocking device72to turn on and to provide a high conductivity path between first supply node VS1and logic output terminal66.

What renders the above-described logic gates60-1and60-2quasi-adiabatic logic gates is the non-DC supply signal applied to either or both of supply nodes NS1and NS2. As in the embodiment depicted inFIG.3, complementary sinusoidal supply signals are generated by complementary sinusoidal supplies30and32. First supply node NS1of quasi-adiabatic unipolar logic gate60-1is sinusoidally driven by first supply signal CLK-PS1lagging in phase to first sinusoidal clock signalCLK-Areceived on first clock input terminal62. Second supply node NS2is sinusoidally driven by second supply signalCLK-PS2, which is 180 degrees out of phase with first supply signal CLK-PS1. Phase timing between such supply signals and clock signals can be used to optimize the response time of quasi-adiabatic logic gates60-1and60-2. Second quasi-adiabatic logic gate60-2has supply signals and clock signals that are 180 degrees out of phase with those used for quasi-adiabatic logic gate60-1. Adjacent quasi-adiabatic logic gates are configured to receive such complementary supply signals and clocking signals.

The phase difference between the leading clock signals and the lagging supply signals can optimize response time of quasi-adiabatic logic gates60-1and60-2. By advancing clock signals provided to clock input terminal62, so as to lead supply signals provided to NS1, the response times of quasi-adiabatic logic gates60-1and60-2can be optimized. By advancing the clock signals provided to clock input terminal62with respect to the supply signal provided to NS1, pulldown clocking device70goes from sub-threshold operation to super-threshold operation more quickly than if the clock and supply signals are in phase with one another. Because of this, the output signal is presented at an earlier time, with regard to the supply signal, when the clock signal leads the supply signal. In some embodiments, a phase difference between the leading clock signals and their corresponding supply signals can be between 2 and 50% if a period. In other embodiments, such a phase difference can be between 5 and 20% or between 10 and 20%, for example.

In some embodiments the first and second supply signals can be complementary in that each of the first and second supply signals sinusoidally oscillate between the same DC voltage levels (e.g., VDD and VSS), but are approximately 180 degrees out of phase with one another. In some embodiments, only the first supply signal is non-DC. In other embodiments, only the second supply signal is non-DC. In some embodiments, first and second supply signals are sinusoids that are approximately 180 degrees out of phase with one another, but oscillate between voltage levels that are different for each of the first and second supply signals. For example the first supply signal can oscillate between VDD and a mid-level supply (e.g., the mean voltage between VDD and VSS). The second supply signal can then oscillate between the mid-level supply and VSS.

In some embodiments, the first and second clock signals provided to first and second clock terminals62and63, respectively will oscillate between VDD and VSS, while the first and second supply signals will oscillate between the mid-level supply and the respective supply voltage VDD or VSS.

In some embodiments, the bodies of one or more of unitary devices68,70and72can be conductively coupled to second supply node NS2or NS1as depicted. In other embodiments, the bodies of unitary devices68,70and72can be conductively coupled to another biasing node. For example, the bodies of unitary devices68,70and72can be conductively coupled to VSS. In other embodiments, unitary devices68,70and72can be conductively coupled via diodes to both second supply node NS2and output logic terminal18. Such a diode connection can ensure that the bodies of the devices of pulldown network22and pulldown clocking device26are not more than one diode voltage level above the voltage level of whichever of second supply node NS2and output logic terminal18that has the more negative voltage level.

FIG.8is a graph of the input and output signals of a quasi-adiabatic CMOS inverter, such as is depicted inFIG.1and inFIG.6.FIG.8is a graph of the simulated input and output signals of an embodiment created using a 130 nm process quasi-adiabatic CMOS inverter, such as is depicted inFIG.1and inFIG.6. In such circuits, CLK-A and NS1can be identical (i.e., in phase with one another); additionally CLK-A NOT and NS2can be identical (i.e., in phase with one another). The waveforms depicted inFIG.8use such in-phase waveforms to show the resulting performance of such in-phase quasi-adiabatic logic where Vout is about 0.14 ns (D1) after the NS1and NS2midpoints are located. The delay between input (e.g., clock) and output is due to the time it takes for the threshold voltages on the first and second pull-up transistors20and24increase enough to turn the transistors on. Furthermore, note that the voltage on the Output18does not match the voltage rise of NS1very well. Both output18and supply NS1are both going up, but NS1is delayed, requiring much more power. In this simulation, the voltage is sinusoidal between ground and 1V. It is the product of the current and the voltage between the two signals that determines the power required. Furthermore, the body bias voltages94and95on the pull up transistors20and24can be provided independent of the supply signals. Similarly, body bias voltages96and97on the pull-down transistors22and26can be independent. The body bias voltages94,95,96and97, can be provided by a body biasing circuit.

FIG.9is a graph of the input and output signals of a quasi-adiabatic CMOS inverter, such as is depicted inFIG.1and inFIG.6.FIG.9is a graph of the simulated input and output signals of an embodiment created using a 130 nm process quasi-adiabatic CMOS inverter, such as is depicted inFIG.1and inFIG.6. In this circuit, CLK-A and NS1are not identical to one another; additionally, CLK-A NOT and NS2are not identical to one another. This waveform shows the speed up from3different methods for increasing the speed of the Quasi-Adiabatic circuits. The first method is to lower the threshold voltage on the transistors20,24,22, and26. This can be accomplished by a body bias circuit attached to the body of the transistors. The second method is to move the timing on CLK-A and CLK-A NOT to precede the supply voltages on NS1and NS2. This enables the signals to be “ready” to switch the Output18to match NS1or NS2depending on the value of the Input16. The third method is to increase the maximum supply voltage across on NS1and NS2. In this simulation, the voltage is sinusoidal between ground and 3V. This reduces the effect of the threshold voltage Vth on speed and power because Vth becomes a smaller percentage of the maximum power supply voltage difference. Note that from the crossover point of NS1and NS2the output signal crosses the midpoint only 0.025 ns (D2) later. Also observe that the output signal and the trap signal match very closely as they both rise. Note that the power equation (i.e., P=V*I, Power=Voltage times Current) depends upon the difference of the voltage between those two signals. This has the effect of lowering the power in particular when the “VDD” is high. The power penalty for a higher voltage is almost completely eliminated while the speed increase is quite visible.