Methods and systems for packaging integrated circuits with integrated passive components

A method is described for packaging integrated circuit dice such that each package includes a die with an integrated passive component mounted to the active surface of the die.

TECHNICAL FIELD

The present invention relates generally to the packaging of integrated circuits (ICs). More particularly, methods and systems are described for producing IC packages that include integrated passive components.

BACKGROUND OF THE INVENTION

There are a number of conventional processes for packaging integrated circuit (IC) dice. By way of example, many IC packages utilize a metallic leadframe that has been stamped or etched from a metal sheet to provide electrical interconnects to external devices. The die may be electrically connected to the leadframe by means of bonding wires, solder bumps or other suitable electrical connections. In general, the die and portions of the leadframe are encapsulated with a molding material to protect the delicate electrical components on the active side of the die while leaving selected portions of the leadframe exposed to facilitate electrical connection to external devices.

The resultant IC packages are often mounted onto printed circuit boards (PCBs). The PCB is used to mechanically support and electrically connect electronic components including the IC package using conductive pathways, or traces, typically etched from copper sheets laminated onto a non-conductive substrate. In many applications, it is desirable to position various non-active (or passive) components along some of the traces to interrupt certain signal transmission paths between the die and an external device or power supply. By way of example, one or more of resistors, capacitors and/or inductors are often mounted onto the PCB. A bypass capacitor, for instance, is often used to decouple one part of the circuit from another. More specifically, a bypass capacitor may be used to bypass the power supply or other high impedance component of the circuit.

Unfortunately, the extended lengths of the signal transmission paths themselves lead to increased parasitic resistances and inductances in the circuit. By way of example, in applications utilizing leadframes with bonding wires, the path length of a given signal is roughly equal to the sum of the lengths of the bonding wire, the length of the lead, the length of the trace coupling the lead to a passive component(s), the length of the passive component(s) and the length of the trace coupling the passive component(s) to an external device. Higher resistance and increased inductance are particularly problematic in high speed applications such as high speed analog to digital converters (ADCs) in which it is desirable to maximize the operating frequency and minimize the time delay.

While existing arrangements and methods for packaging IC devices work well, there are continuing efforts to both miniaturize the size of IC devices and improve the electrical performance of IC devices.

SUMMARY OF THE INVENTION

In one aspect, a method is described for packaging integrated circuit dice such that each package includes a die with an integrated passive component mounted thereon. A wafer is first provided that includes a multiplicity of integrated circuit dice. The active surface of each die includes a first set of bond pads and a second set of bond pads. A first conductive layer is deposited over the active surfaces of the dice. Subsequently, a second conductive barrier layer is then deposited over the first conductive layer. A third solder-wettable conductive layer is then deposited over the second conductive barrier layer. Portions of the first conductive layer, second conductive barrier layer and third solder-wettable conductive layer that do not overlie the first set of bond pads or the second set of bond pads of each die are then removed. Subsequently, portions of the second conductive barrier layer and the third solder-wettable conductive layer that overlie the second set of bond pads of each die are removed. A layer of solder is then deposited over portions of the third solder-wettable conductive layer that overlie the first set of bond pads of each die. A non-active or passive electrical component is then positioned over the active surface of each die such that electrodes from the non-active electrical component are positioned adjacent solder deposited over ones of the first set of bond pads of the die. The solder is then reflowed to electrically and physically connect the electrodes of the non-active electrical component with the ones of the first set of bond pads. The wafer may then be singulated to provide individual integrated circuit dice each having an integrated passive component mounted on the surface of the die.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

The present invention relates generally to the packaging of integrated circuits (ICs). More particularly, methods and systems are described for producing IC packages that include integrated passive components.

In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to avoid unnecessary obscuring of the present invention.

The following description focuses on the production of an IC package that includes a die having both a first set of solder-wettable bond pads as well as a second set of bond pads arranged for electrical connection with bonding wires. The first set of solder-wettable bond pads are arranged for direct connection with electrodes (or leads) from a non-active (passive) electrical component (or components) via solder joints while the second set of bond pads are connected via bonding wires with leads or other contacts from a suitable substrate such as a leadframe that facilitates connection with an external device. Various embodiments of the present invention will be described with reference toFIGS. 1-9.

Referring initially toFIG. 1, and further in view ofFIGS. 2-3, a process100for preparing IC dice for packaging in accordance with particular embodiments of the present invention will be described. Initially, a semiconductor wafer200that includes a large number of dice is fabricated. As is well known in the art, most wafers and dice are formed of silicon (Si), although any other appropriate semiconductor material can also be used.FIG. 2illustrates a diagrammatic top view of a suitable wafer200. While the wafer200diagrammatically illustrated inFIG. 2shows only a few IC dice202, it will be appreciated by those familiar with the art that state of the art wafers will typically have several hundred to several thousand dice formed therein and it is expected that even higher device densities will be attained in future wafers. The dice202are generally formed into a two-dimensional array of rows and columns with each row/column being separated from immediately adjacent rows/columns by scribe lines203(also known as saw streets). Each die202will become an IC component after it is singulated from the wafer200.

An IC die202generally has multiple metallization layers that overlie active circuits formed within the semiconductor substrate of the die. Intermediate dielectric layers are typically interposed between the metallization layers to physically and electrically separate the metallization layers. Electrically conductive vias are formed in the dielectric layers at appropriate locations in order to electrically connect specific portions of the metallization layers in desired locations. The various metallization layers may be used as ground/power planes and/or as signal routing interconnects within the IC die. A variety of materials may be used to form the dielectric and metallization layers. By way of example, aluminum (Al) and copper (Cu) are often used materials for the metallization layers and (in Si based devices) silicon dioxide, silicon nitride and/or other oxides and nitrides are commonly used to form the dielectric layers. Selected portions of the topmost metallization layer are left exposed through various openings in the outermost dielectric or passivation layer on the active surface204of each die202to form a plurality of bond pads (hereinafter also referred to as “I/O pads”)206and208that serve as electrical contacts for the die (collectively the active surfaces204of the dice202form the active surface of the wafer). In the illustrated embodiment, each die202includes 6 inner bond pads206and16peripheral bond pads208; however, the number, size and layout of the bond pads206and208may vary widely according to the needs of a particular application. Additionally, although the exposed portions of the inner bond pads206and peripheral bond pads208are illustrated as having square geometries, it will be appreciated by those of skill in the art that the bond pads may assume other geometries as well, such as for example rectangles or circles.

As will be appreciated by those familiar with the art, the I/O pads used with solder-bumped and wire-bonded dice may be the original bond pads on the original active surface of the die, but may also be bond pads that have been redistributed from the original bond pads using conventional redistribution techniques. More particularly, the original bond pads are often distributed around the perimeter of the die at a prescribed distance from the peripheral edges of the die. This bond pad configuration is generally suitable for most wire-bonded applications; however, it may be advantageous to redistribute some or all of the original bond pads using metal redistribution lines to form a desired final array layout of I/O bond pads206and208.

At102, a first metallic layer310is deposited onto the active surface of the wafer200.FIGS. 3A and 3Billustrate diagrammatic cross-sectional side views of a portion of a die202before and after the deposition of the metallic layer310, respectively. The metallic layer310preferably covers the entire active surface of the wafer200, or at least the portions of the wafer that form the active surfaces of the dice202. The thickness of the metallic layer310is preferably on the order of approximately 1 μm, although both thinner and thicker metallic layers may be suitable and are permitted. In one particular embodiment, the thickness of the metallic layer310is approximately 1.0 μm. Although any suitable process may be used to deposit the metallic layer310, such as for example sputtering or evaporation, in one preferred embodiment the metallic layer is sputtered onto the active surface of the wafer200. In the illustrated embodiment, the inner bond pads206and peripheral bond pads208are formed from aluminum and the metallic layer310is formed from aluminum or a suitable aluminum alloy. By way of example, the aluminum alloy may be an alloy of approximately 99.5% aluminum and 0.5% copper, although other aluminum and copper alloys as well as other materials may be suitable as well.

Following application of the metallic layer310, a second metallic layer312is deposited at104over the first metallic layer310. Again, in one preferred embodiment, the metallic layer312is sputtered onto the metallic layer310. In the illustrated embodiment, the metallic layer312entirely covers the metallic layer310. The metallic layer312serves as a diffusion barrier layer having material properties and a thickness that are suitable to prevent the diffusion or migration of metallic ions through the metallic layer312. By way of example, it one embodiment the thickness of the metallic layer312is approximately 0.8 μm although, again, thinner and thicker metallic layers may be suitable and are permitted. One suitable material for use as the metallic barrier layer312is, by way of example, an alloy of nickel and vanadium (NiV). The purpose of the metallic layer312will become more apparent from the following discussion.

At106, a third solder-wettable metallic layer314is deposited over the second barrier layer312. The solder-wettable layer314is preferably sputtered onto the barrier layer312such that it entirely covers the barrier layer312. A solder-wettable layer thickness of approximately 0.3 μm has been shown to work well. The solder-wettable layer314is preferably formed of a material that is wettable to a variety of solder materials (e.g., tin and lead). By way of example, in the illustrated embodiment, the solder-wettable layer314is formed from copper.

In general, suitable thicknesses for all of the aforementioned metallic layers310,312and314will depend upon the materials used to form the respective layers.

In one embodiment, a photoresist mask316is deposited over the active surface of the wafer200at108. In the illustrated embodiment, the photoresist mask316is patterned such that only the bond pads206and208are covered by the mask, as illustrated inFIG. 3C. The metallic layers310,312and314are then etched at110in regions not covered by the mask316as illustrated inFIG. 3D. The remaining portions of the mask316(i.e., the portions covering the bond pads206and208) are then removed at112. In this way, only the bond pads206and208remain covered by the metallic layers310,312and314. Here it should be noted that the stack of metallic layers310,312and314formed over each inner bond pad206serve as an underbump metallurgy stack (UBM)318suitable to receive solder and to facilitate the formation of a solder joint connection with an associated contact. As such, the UBMs318are preferably patterned so as to be circular as viewed from above the active surfaces204of the dice202.

At114a second photoresist mask320is deposited and patterned over the active surface of the wafer such that only the peripheral bond pads208are uncovered by the mask320as illustrated inFIG. 3E. The portions of the metallic layers312and314over the peripheral bond pads208are then etched and removed at116. In the embodiment illustrated inFIG. 3F, a small amount of the first metallic layer310may also be removed to ensure that the metallic layers312and314are entirely removed from the bond pads208. By way of example, in one embodiment, approximately 0.2 μm of the metallic layer310covering each bond pad208is etched and removed. Subsequently, the remaining portions of the mask320are removed at118from the active surface of the wafer.

As illustrated inFIG. 4, the resulting wafer200includes dice202each having a number of inner bond pads206that are covered by solder-wettable UBMs318as well as a number of peripheral bond pads208each having surfaces suitable for wire bonding. Solder bumps322are deposited at120over the UBM stacks318as illustrated inFIG. 3G. The solder bumps322may be deposited with any suitable means and are generally formed of a mixture of tin (Sn) and lead (Pb). By way of example, the solder bumps may be applied in the form of a solder paste using a needle dispenser. Solder pastes generally include a mixture of solder as well as flux, which further facilitates the spread of solder across the bonding surfaces of the UBMs318.

According to various embodiments, one or more surface-mountable passive electrical components324are then positioned over the active surfaces204of each die202. By passive it is meant that the components are not active; that is, the passive components are incapable of power gain. Suitable passive components324may include, by way of example: capacitors, resistors, inductors and crystals (such as quartz for timing purposes) among others. By positioning the passive components324directly onto the surface of each die202, the signal transmission path between the die and an associated external device after mounting to a PCB can be significantly reduced. As described earlier, it is generally desirable to minimize the lengths of the signal transmission paths to and from the die and external devices and other contacts. Conventionally, passive components are positioned outside the IC package on the PCB. However, according to the embodiments of the present invention, various passive components are positioned directly onto the surface of the die202(prior to packaging the die) effectively eliminating virtually the entire transmission path length from the die to the passive components324. During operation, various signals may be routed through the passive component(s) on the surface of the die202prior to transmission out of the IC package via the peripheral bond pads208or, conversely, signals coming into the die via the peripheral bond pads may be routed through the passive components prior to being routed to the active circuits within the die.

In the illustrated embodiment, a single passive component324is positioned over the active surface204of each die at122. More particularly, lead contacts326are positioned over corresponding inner bond pads206. The solder bumps322are reflowed at124to form solder joints328that physically and electrically connect the passive components324to their respective dice202. In one embodiment, during reflow, the solder-wettable metallic layer314diffuses into the solder joint. This is a result of the affinity of the copper in the metallic layer314for the tin in the solder. The metallic barrier layer314remains adhered to the solder and prevents further diffusion as well as detachment of the solder joints328from their respective bond pads206.

Although only a single passive component324is positioned onto the active surface of each die202in the illustrated embodiment, it should be noted that in other embodiments, two or more passive components may be positioned onto the active surface of each die. Furthermore, the passive components positioned onto each die may assume a wide variety of shapes and sizes. As such, the layout and geometry of the bond pads206may be widely varied based on the requirements of a particular application.

The wafer200may then be singulated at126to yield individual dice202. The wafer200may be singulated with any suitable means. By way of example, the wafer200may be singulated using sawing, gang-cutting (sawing), laser cutting or plasma cutting along the scribe lines203.

A process500for packaging the dice202will now be described with reference toFIGS. 5-7. Each singulated die202may be positioned and attached within a die attach area of a suitable substrate. By way of example, in the illustrated embodiment, each die202is positioned onto a leadframe panel at502.

With respect toFIGS. 6A-C, an exemplary leadframe panel600suitable for use in packaging integrated circuits according to various embodiments of the present invention will be described.FIG. 6Aillustrates a diagrammatic top view of a leadframe panel600arranged in the form of a strip. The leadframe panel600can be configured as a metallic structure having a number of two-dimensional arrays602of device areas. By way of example, leadframe panel600may be formed from copper or a suitable copper alloy. As illustrated in the successively more detailedFIGS. 6B-C, each two-dimensional array602includes a plurality of device areas604, each configured for use in a single IC package, and each connected by fine tie bars606.

Each device area604includes a number of leads608, each supported at one end by the tie bars606. In the illustrated embodiment, each device area604includes sixteen leads608, four of which extend from each of four sides of a die attach pad610(those familiar with the art will recognize this configuration as a typical leadless leadframe package (LLP) configuration). The die attach pad610is partly supported by die attach pad support bars612that extend from the corners of the die attach pad to tie bars606. Each lead608includes a conductive wire bonding surface614on the top surface of the leadframe and a package contact surface616on the bottom (back) surface of the leadframe. The leads608may be etched, half-etched, or otherwise thinned relative to the package contact surfaces, so as to provide electrical connection to contacts on a PCB while limiting the exposed conductive areas on the bottom surface of the leadframe as well as providing a mold locking feature. In some embodiments, it may also be desirable to etch or otherwise thin the top surface of the leadframe as well. Additionally, an adhesive tape may be attached to the bottom surface of the leadframe panel600. The tape may serve to provide structural support for the leadframe features and additionally aid during encapsulation of the leadframe panel600with molding material.

It will be appreciated by those skilled in the art that, although a specific leadframe panel600has been described and illustrated, the described methods may be applied in packaging dice202utilizing an extremely wide variety of other leadframe panel or strip configurations as well as other substrates, such as substrates used in ball-grid array (BGA) package configurations. Additionally, although described with references to top and bottom surfaces of the leadframe panel600, it should be appreciated that this context is intended solely for use in describing the structure and in no way defines or limits the orientation of the leadframe relative to other package components.

FIGS. 7A-Cillustrate diagrammatic cross-sections of one device area604of the leadframe panel600at various steps during process500. In the embodiment illustrated inFIG. 7A, the die202is physically attached to the die attach pad610by means of a suitable die attach material730such as, by way of example, an epoxy or adhesive film. In embodiments in which die attach pads are not used, each die202is positioned directly onto an adhesive tape736.

After attaching the dice202to the leadframe panel600, the peripheral bond pads208on the active surface of the dice are electrically connected at504to the leads608by means of metallic (e.g., gold) bonding wires732. It should be noted that, while aspects of the present invention are particularly well-suited for use in packaging dice that utilize bonding wires, any suitable electrical connections may be used.

At506the bonding wires732, dice202, passive components324and portions of the leadframe panel600are encapsulated with a molding material (compound)734. The molding compound is generally a non-conductive plastic or resin having a low coefficient of thermal expansion. In a preferred embodiment, the entire populated leadframe panel600is placed in the mold and encapsulated substantially simultaneously. In another embodiment, the mold may be configured such that each two-dimensional array602is encapsulated as a single unit. However, it should be appreciated that a lesser number of dice202may also be encapsulated at any one time. It should additionally be appreciated that virtually any molding system may be used to encapsulate the attached dice202and leadframe panel600. By way of example, a film assisted molding (FAM) system may be used to encapsulate the attached dice202and passive components324. The adhesive film prevents molding compound intrusion over the back surfaces of the die attach pads610and the package contact surfaces616on the bottom surfaces of the leads608.

Subsequently, the molding compound734may be cured in a heated oven (e.g., if the molding compound is a thermosetting plastic) and the adhesive tape736may be removed. After curing the molding compound734, the package contact surfaces616may be solder plated to facilitate connection with corresponding contact surfaces on a PCB or other substrate. In some embodiments, the back surfaces of the die attach pads610are also solder plated to facilitate external connection to PCBs.

The encapsulated leadframe panel600may then be singulated at508to yield a multiplicity of individual IC packages738, such as that illustrated inFIG. 7C. Again, the encapsulated leadframe panel600may be singulated with any suitable means. By way of example, the leadframe panel600may be singulated using sawing, gang-cutting (sawing), laser cutting or plasma cutting along the tie bars606to produce individual IC packages738. Upon package singulation, the IC packages738may be inspected and/or tested before being attached to PCBs or other substrates. Those of skill in the art will recognize that the described method may be used to produce a leadless leadframe package (LLP) or quad-flat-pack-no-lead (QFN) package. However, many other package types, such as for example dual inline packages (DIPs) may be produced as well.

FIGS. 8A-Cillustrate steps in an alternate embodiment in which the metallic layers310,312and314are deposited over an additional passivation layer840.FIG. 8Aillustrates the same cross-section of the wafer200illustrated inFIG. 3A. In the alternate embodiment, the additional passivation layer840is deposited over the active surface of the wafer200prior to the deposition of the metallic layers310,312and314as illustrated inFIG. 8B. By way of example, a passivation layer840formed of benzocyclobutene (BCB) may be spun-on or otherwise deposited and patterned over the active surface of the wafer in regions surrounding the bond pads206and208. In the embodiment illustrated inFIG. 8B, the BCB layer840is deposited such that it overlies and covers the peripheral edges of each of the bond pads206and208. The metallic layers310,312and314are then deposited as before over the BCB layer840as illustrated inFIG. 8C. The process may then continue as outlined in process100.

FIGS. 9A-Fillustrate steps in still another embodiment. The process begins as before with a suitable wafer200as illustrated inFIG. 9A. In this alternate embodiment, however, a conductive seed layer942is first deposited over the entire active surface of the wafer200as illustrated in the cross-section ofFIG. 9B. The seed layer942is utilized for a subsequent electroplating step. Any suitable materials can be used to form the seed layer942. By way of example, in one embodiment, the seed layer942is formed from a titanium-copper-titanium layer stack. A mask944is then deposited and patterned over the active surface of the wafer is regions surrounding the bond pads206and208, as illustrated inFIG. 9C. Subsequently, as illustrated inFIG. 9D, the active surface of the wafer is electroplated to deposit a conductive layer946of copper or other suitable metal over the bond pads206and208. The thickness of the layer946may vary according to the particular application, but a thickness in the range of approximately 5-15 μm has been shown to work well. It should be noted that, in some applications, the copper layer946may be advantageously patterned so as to redistribute some or all of the bond pads206and208. In embodiments in which some or all of the bond pads206or208are to be redistributed, the mask is patterned such that the copper layer946forms a conductive trace from the bond pads206and/or208to desired redistributed locations. By way of example, in the embodiment illustrated inFIG. 9D, the mask944is patterned so as to allow the deposition of a copper trace segment948extending from an inner bond pad206to a redistributed bond pad location950.

The mask944and portions of the seed layer942not overlying the bond pads206and208or the traces948and redistributed bond pad locations950are then removed as illustrated inFIG. 9E. In the illustrated embodiment, a BCB passivation layer952is then deposited in regions surrounding the copper layers946. In the embodiment illustrated inFIG. 9F, the BCB layer952extends over peripheral portions of the bond pad950and also covers the associated trace948and bond pad206.

After deposition of the passivation layer952, the exposed surfaces of the bond pads206(or bond pads950if redistributed) may then be solder plated. The thickness of the copper layers946is sufficient such that only a small proportion of the copper is absorbed into the solder thereby preventing detachment of the resultant solder joints from the bond pads206or950. In other embodiments, the process may continue as outlined in process100ofFIG. 1. More specifically, in these other embodiments the metallic layers310,312and314may be deposited over the copper layers946and passivation layer952rather than directly over the bond pads206and208as was the case in the embodiment illustrated inFIGS. 3A-H.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.