Wafer backside particle mitigation

A method of particle mitigation which includes obtaining a semiconductor wafer having a nonfunctional backside and a functional frontside on which semiconductor devices are formed by one or more lithography processes; coating the backside with a layer comprising silicon or amorphous carbon; planarizing the coated backside by a planarizing process; placing the semiconductor wafer onto a wafer chuck such that the wafer chuck makes direct contact with the coated backside; and while maintaining the coated backside in direct contact with the wafer chuck, performing a first lithographic process on the frontside.

RELATED APPLICATION

This application is related to U.S. patent application Ser. No. 14/459,809, entitled “WAFER BACKSIDE PARTICLE MITIGATION”, filed even date herewith.

BACKGROUND

The present exemplary embodiments relate to mitigating particle contamination on the backside of a semiconductor wafer, and more particularly, relate to mitigating particle contamination by providing a coating on the backside of the semiconductor wafer to encapsulate the contaminating particles and fill any scratches.

Particulate matter may be generated from wafer handling devices (such as pics, pins and pads) as the semiconductor wafers travel through a multitude of tools in the line. Some particulate matter, and especially scratches and dents, are inevitable, regardless of any sort of preemptive cleaning or wiping methods.

The semiconductor wafers are typically handled with a so-called wafer chuck, one example of a wafer chuck being an electrostatic wafer chuck, which secures the semiconductor wafer during processing. However, conventional electrostatic chucks maintain a high percent point of contact with the backside of the semiconductor wafer. This large area of contact is highly susceptible to semiconductor wafer backside particulate manner and scratches, which can create wafer topography during lithography exposure and lead to “hot spots”. A hot spot in the present context is a lithography term for a localized pattern distortion (i.e., defocus) of which one cause is wafer topography.

BRIEF SUMMARY

The various advantages and purposes of the exemplary embodiments as described above and hereafter are achieved by providing, according to a first aspect of the exemplary embodiments, a method of particle mitigation which includes obtaining a semiconductor wafer having a nonfunctional backside and a functional frontside on which semiconductor devices are formed by one or more lithography processes; coating the backside with a mitigating layer comprising silicon or amorphous carbon; planarizing the coated backside by a planarizing process; placing the semiconductor wafer onto a wafer chuck such that the wafer chuck makes direct contact with the coated backside; and while maintaining the coated backside in direct contact with the wafer chuck, performing a first lithographic process on the frontside.

According to a second aspect of the exemplary embodiments, there is provided a method of particle mitigation which includes obtaining a semiconductor wafer having a nonfunctional backside and a functional frontside on which semiconductor devices are formed by one or more lithography processes; coating the backside with a mitigating layer comprising silicon or amorphous carbon; planarizing the coated backside by a planarizing process; placing the semiconductor wafer onto an electrostatic wafer chuck such that the electrostatic wafer chuck makes direct contact with the coated backside; and while maintaining the coated backside in direct contact with the electrostatic wafer chuck, performing an extreme ultraviolet (EUV) lithographic process on the frontside.

According to a third aspect of the exemplary embodiments, there is provided a method of particle mitigation which includes obtaining a semiconductor wafer having a nonfunctional backside and a functional frontside on which semiconductor devices are formed by one or more lithography processes; coating the backside with a mitigating layer comprising silicon or a carbon-like material; planarizing the coated backside by a planarizing process; coating the mitigating layer with a stop layer that is compositionally different than the mitigating layer; coating the stop layer with another mitigating layer comprising silicon or carbon-like material; planarizing the coated backside by a planarizing process; repeating, a predetermined number of times, coating the mitigating layer with the stop layer that is compositionally different than the mitigating layer, coating the stop layer with another mitigating layer comprising silicon or amorphous carbon, and planarizing the coated backside by the planarizing process; placing the semiconductor wafer onto a wafer chuck such that the wafer chuck makes direct contact with the coated backside; and while maintaining the coated backside in direct contact with the wafer chuck, performing a lithographic process on the frontside.

DETAILED DESCRIPTION

Semiconductor technology is well known. Through semiconductor fabrication processes, semiconductor devices are formed on a semiconductor wafer. A typical semiconductor wafer has a back, nonfunctional side (hereafter “backside”) and a front, functional side (hereafter “frontside”). The semiconductor fabrication processes such as front end of the line processes to form transistors and back end of the line processes to form interconnects occur on the frontside of the semiconductor wafer. Lithography may be used in many of these semiconductor fabrication processes to pattern the frontside. Optical lithography, immersion lithography, ultraviolet (UV) lithography and extreme ultraviolet (EUV) lithography being examples of types of lithographic processes that may be utilized.

During these semiconductor fabrication processes, the semiconductor wafer may be supported by a wafer chuck such as an electrostatic wafer chuck. Electrostatic wafer chucks employ a platen with integral electrodes which are biased with high voltage to establish an electrostatic holding force between the platen and wafer, thereby “chucking” the wafer. The semiconductor wafer is typically placed backside down on the wafer chuck since the backside has no semiconductor devices and is thus nonfunctional.

As noted previously, particulate matter and scratches on the backside can cause problems such as lithographic “hotspots” and so it is desirable to mitigate the harmful effect of such particulate matter and scratches.

Referring to the Figures in more detail, and particularly referring toFIG. 1, there is illustrated a semiconductor wafer10having a coating12on the backside of the semiconductor wafer. The coating12may also be referred to as a mitigating layer.

It may be desirable to have the semiconductor10undergo a cleaning process prior to applying the coating12in order to remove as many particulate matter as possible. This cleaning process may be a conventional cleaning process such as a wet cleaning process or a dry cleaning process where the wafer may be wiped to remove the particulate matter. It is believed that in many cases, encapsulation by applying the coating12may be desirable since there may be incomplete removal of the particulate matter during any cleaning process and in any case, scratches may not be removed by cleaning. In one exemplary embodiment, the particulate matter and scratches may be characterized before applying the coating12to determine if the coating12is desirable.

FIG. 2is a cross sectional view ofFIG. 1in the direction of arrows2-2shown inFIG. 1. Semiconductor wafer10may have particulate matter14and/or scratches16on the backside18of the semiconductor wafer10. The frontside of the semiconductor wafer is indicated by reference number20.

A coating12has been applied to the backside18so as to encapsulate the particulate matter14and fill scratches16that may be present on the backside18. Coating12may have a thickness that may be selected to be on the order of at least about two times the size of the maximum targeted particle size. For example, typical particle sizes range from 0-10 um so the layer thickness may be on the order of 20 um. The coating12may be deposited or applied by a spin on film process. In one exemplary embodiment the coating12may be silicon, such as amorphous silicon. In an alternative embodiment, the coating12may be an amorphous carbon film. Both of the silicon and amorphous carbon films may be planarized and may also be removed selectively using a wet process or a dry process such as a reactive ion etching process or some combination thereof. In one exemplary embodiment, TEOS (tetraethyl orthosilicate) for the silicon film or acetylene, ethylene or propylene for the amorphous carbon film may be applied by a spin on process at a temperature that is compatible with any frontside films, for example, 250 to 600° C. to turn the spin on film into silicon or amorphous carbon. For backside deposition, the processing should be performed in a single wafer chamber. It is noted that the surface22of the coating12may be uneven due to the presence of particulate matter14and scratch16. Accordingly, the coating12may undergo a planarizing process to planarize the surface22of the coating12. For purposes of illustration and not limitation, the planarizing process may be a chemical-mechanical planarizing process (CMP). The coating12after planarization is shown inFIG. 3.

Referring now toFIG. 4, the semiconductor wafer10is flipped over so as to be supported on a wafer chuck24, such as an electrostatic chuck. Frontside surface20(now facing up) of the semiconductor wafer10may then undergo a lithographic process such as by lithographic tool28. Most preferably, the lithographic process is an EUV process in which extreme ultraviolet light (around 13.5 nanometers in wavelength) is used for exposing a photoresist. Surface22of coating12is now in direct contact with surface26of wafer chuck24. It is noted that since the particulate matter14and scratch16are fully encapsulated by coating12, and there is even topography due to the planarizing described with respect toFIG. 3, the semiconductor wafer10may be processed without fear of hotspots.

Later in the process flow, the coating12may be removed by conventional means such as by reactive ion etching, wet etching or chemical-mechanical polishing, depending on the specific film chosen.

Referring now toFIGS. 5 to 7, another exemplary embodiment will be described. In this exemplary embodiment, a protective coating30may be applied to the frontside20of the semiconductor wafer10to avoid any possible harm to the frontside20when the backside coating12is applied. In a preferred exemplary embodiment, a protective coating may not be required, but if it is required (for instance when the exposed frontside cannot be mechanically contacted to the wafer chuck without damaging the frontside film stack), then the protective coating30may need to be applied, and the material for such protective coating may need to be chosen with special consideration with respect to the choice of backside pattern material as chosen above, so as to allow selective removal in subsequent processes. The protective coating30may also be silicon or amorphous carbon. The protective coating30may be the same or different than the backside coating12.

As shown inFIG. 5, protective coating30has been applied to the frontside20of the semiconductor wafer10. The backside18may contain particulate matter14and/or scratch16which may need to be encapsulated.

Coating12may be applied as described previously to the backside18to encapsulate the particulate matter14and fill scratch16, as shown inFIG. 6, followed by planarizing to result in the structure shown inFIG. 7.

Another exemplary embodiment is illustrated inFIG. 8. In the exemplary embodiment illustrated inFIG. 8, multiple layers of coating12may be applied to the backside18. The coating12may be applied and planarized, as described previously, to encapsulate the particulate matter14and fill scratch16. Thereafter, a stop layer32such as an oxide may be applied to the coating12and planarized. Stop layer32may have a thickness of about 20 to 100 nm. The stop layer32provides a method of removing the exposed coated layer selective to another coated layer deeper in the stack. The stop layer32stops the removal of one coated layer selective to the stop layer. Any material that is compatible with being deposited alternately with the coating12as well as providing a selective stop against the coating12may be used as the stop layer32. For example, if the coating12is silicon, then the stop layer32may be an oxide or nitride if the removal process of the silicon is reactive ion etching. If using a wet etching process, hot ammonia will etch silicon selective to oxide, for example. Then the stop layer32may be removed by a process selective to the underlying coating12. For example, if the coating12is silicon and the stop layer32is oxide, then the oxide stop layer32may be removed, for example, by a fluorine-based reactive ion etching process or dilute HF.

Then another coating12′ may be applied to the stop layer32and planarized. This process sequence may be repeated until subsequent stop layer32′ and coating12″ have been formed as shown inFIG. 8. Additional stop layers and coatings may be applied until the desired number of stop layers and coatings have been added. All of the stop layers32,32′ may comprise the same material or different materials. Similarly, all of the coatings12,12′,12″ may comprise the same material or different materials.

The method of alternating coated layers separated by stop layers provides a stack of “pre-built” films that may be iteratively removed as needed, without the need to go through as many iterative deposition steps. That is, the last coating12,12′ or12″ may be removed followed by removal of the last stop layer32′ or32so that the next coating12or12′ is a clean and flat backside layer for the next lithographic process, such as an EUV process. There may be cases where one is prohibited from depositing such a coated layer prior to EUV exposure due to exposed films, etc. where having several “pre-built” layers can serve the needed purpose of having a clean and flat backside layer before each lithographic process.

The frontside protective coating30, while shown inFIG. 8, is optional and may be dispensed with if desired.

Referring now toFIG. 9, there is illustrated a process flow for the various exemplary embodiments. The process begins by obtaining a semiconductor wafer, box40.

In an optional process, the backside of the semiconductor wafer may be cleaned to remove as many particulate matter as possible, box42. Optionally also, the backside of the semiconductor wafer may be characterized to determine if an encapsulating coating is desirable.

In another optional process, the frontside of the semiconductor wafer may receive a protective coating to protect the frontside during subsequent application of the backside coating, box44. The frontside protective coating would have to be removed prior to performing any lithographic process on the frontside.

The backside of the semiconductor wafer may be coated, box46, by any of the processes and materials described previously.

The backside coating may then be planarized, box48.

It is then determined if more backside layers are to be applied, box50. The additional backside layers may be those described with respect toFIG. 8. If more layers are to be applied, a stop layer may be applied such as stop layer32inFIG. 8, box60, then the process returns to box46to apply additional coating layers. If no more layers are to be applied, the process proceeds to place the coated semiconductor wafer on the wafer chuck, box52. It is preferred that the wafer chuck be an electrostatic wafer chuck. The backside coating is placed in direct contact on the wafer chuck.

If the semiconductor wafer has a frontside protective coating, the frontside coating may be removed, box54, before or after the semiconductor wafer is placed on the wafer chuck. In any event, the frontside protective coating must be removed before a lithographic process is performed.

A lithographic process is next performed on the frontside, box56. It is most preferred that the backside coating be present when the semiconductor wafer undergoes an EUV process as this process most likely leads to hotspots.

When lithographic processing is completed, or at least when EUV lithographic processing is completed, the backside coating may be removed, box58.