FIELD REPLACEABLE FAN ASSEMBLIES FOR PERIPHERAL PROCESSING UNITS AND RELATED SYSTEMS AND METHODS

Example field replaceable fan assemblies for peripheral processing units and related systems and methods are disclosed. An example apparatus includes a temperature sensor; a fan having a base; at least one memory; machine readable instructions; and processor circuitry to execute operations corresponding to the machine readable instructions to determine a first temperature based on an output of the temperature sensor; and cause the base of the fan to move based on the first temperature.

FIELD OF THE DISCLOSURE

This disclosure relates generally to peripheral processing units and, more particularly, to field replaceable fan assemblies for peripheral processing units and related systems and methods.

BACKGROUND

Peripheral processing units such as infrastructure processing units (IPUs) or graphics cards including graphic processing units generate heat during operation. A peripheral processing unit can include a heat sink to absorb the heat and facilitate dissipation of the heat to regulate the temperature of the hardware. Some peripheral processing units include fans to increase airflow at the heat sink and, thus, the dissipation of the heat.

As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other.

DETAILED DESCRIPTION

A peripheral processing unit such as an infrastructure processing units (IPUs), processor circuitry, graphics cards including one or more graphic processing units (GPUs), and/or other types of peripherals such as peripheral component interconnect express (PCIe) cards generate heat during operation. The PCIe card can include a heat sink to absorb heat and facilitate dissipation of the heat to regulate the temperature of the electronic components of the PCIe card (e.g., processor circuitry such as an FPGA, a microprocessor, a controller, etc.). Some PCIe cards include fans to increase airflow at the heat sink and, thus, the dissipation of the heat. Some PCIe cards are disposed in a server chassis that includes fans.

Cooling at a known PCIe card is typically affected by the fan speed and the number of fans in the card. Also, the fan(s) of known PCIe cards are typically fixed with respect to location in the PCIe card (e.g., fixed on the heat sink). Thus, the fan(s) can provide for increased cooling at the location(s) where the fan(s) are located. However, power consumption and, thus, the amount of heat generated by the electronic components of the PCIe card can vary during operation of the PCIe card based on, for instance, a work load that is offloaded or accelerated on, for example, an IPU, a GPU, etc. In particular, during operation of the PCIe card, certain areas of the PCIe card may be associated with increased temperature relative to other areas of the PCIe card based on performance of the electronic components at those areas. Such areas of increased temperature are referred to herein as “hot spots.” If a fixed fan of the PCIe card is not proximate to the hot spot, the hot spot may not be efficiently cooled, which can affect performance of the electronic components associated with the increased thermal power. Also, if the fixed fan fails, the PCIe card is powered down to remove and replace the fan, which can substantially disrupt performance of the server including the PCIe card. Thus, the fixed fan can be a point of failure for a peripheral.

Disclosed herein are example fan assemblies that provide for increased airflow in a peripheral (e.g., a peripheral processing unit such as a PCIe card) while enabling a fan carried by the fan assembly to be removed from the peripheral (e.g., from the PCIe card) without disrupting operation of the peripheral (e.g., the PCIe card). Example fan assemblies disclosed herein include a tray that carries a fan. The tray can be removably inserted in peripheral (e.g., the PCIe card) via an opening formed in the card. As a result, the tray including the fan can be removed (e.g., for fan maintenance) without affecting or substantially affecting the operation of the other electronic components of the peripheral (e.g., the PCIe card). In other words, the fan is field replaceable or hot swappable). Some examples disclosed herein generate alerts to inform, for instance, a data center operator that a fan may need maintenance based on monitoring of fan performance (e.g., fan speed).

Some example fan assemblies disclosed herein enable the fan to translate or move (e.g., slide) relative to the tray to dynamically position the fan at two or more different locations relative to the heat sink. Examples disclosed herein monitor changes in temperature at the peripheral (e.g., the PCIe card) to detect areas of increased temperature, or hot spots, indicative of increased amounts of heat generated by certain electronic components. Examples disclosed herein cause the fan to translate (e.g., cause a base of the fan to move) to a location relative to the heat sink that is proximate to the hot spot. As a result, some examples disclosed herein provide dynamic, location-targeted augmented cooling during operation of the peripheral (e.g., the PCIe card). Some examples disclosed herein dynamically adjust operating parameters of the fan such as rotational speed and rotational direction based on the temperature of the peripheral (e.g., the PCIe card), performance of two or more fans in the peripheral (e.g., the PCIe card), etc. Thus, examples disclosed herein provide for augmented cooling of peripherals such as peripheral processing units to mitigate hot spots.

FIG.1illustrates one or more example environments in which teachings of this disclosure may be implemented. The example environment(s) ofFIG.1can include one or more central data centers102. The central data center(s)102can store a large number of servers used by, for instance, one or more organizations for data processing, storage, etc. As illustrated inFIG.1, the central data center(s)102include a plurality of immersion tank(s)104to facilitate cooling of the servers and/or other electronic components stored at the central data center(s)102. The immersion tank(s)104can provide for single-phase immersion cooling or two-phase immersion cooling.

The example environments ofFIG.1can be part of an edge computing system. For instance, the example environments ofFIG.1can include edge data centers or micro-data centers106. The edge data center(s)106can include, for example, data centers located at a base of a cell tower. In some examples, the edge data center(s)106are located at or near a top of a cell tower and/or other utility pole. The edge data center(s)106include respective housings that store server(s), where the server(s) can be in communication with, for instance, the server(s) stored at the central data center(s)102, client devices, and/or other computing devices in the edge network. Example housings of the edge data center(s)106may include materials that form one or more exterior surfaces that partially or fully protect contents therein, in which protection may include weather protection, hazardous environment protection (e.g., EMI, vibration, extreme temperatures), and/or enable submergibility. Example housings may include power circuitry to provide power for stationary and/or portable implementations, such as AC power inputs, DC power inputs, AC/DC or DC/AC converter(s), power regulators, transformers, charging circuitry, batteries, wired inputs and/or wireless power inputs. As illustrated inFIG.1, the edge data center(s)106can include immersion tank(s)108to store server(s) and/or other electronic component(s) located at the edge data center(s)106.

The example environment(s) ofFIG.1can include buildings110for purposes of business and/or industry that store information technology (IT) equipment in, for example, one or more rooms of the building(s)110. For example, as represented inFIG.1, server(s)112can be stored with server rack(s)114that support the server(s)112(e.g., in an opening of slot of the rack114). In some examples, the server(s)112located at the buildings110include on-premise server(s) of an edge computing network, where the on-premise server(s) are in communication with remote server(s) (e.g., the server(s) at the edge data center(s)106) and/or other computing device(s) within an edge network.

The example environment(s) ofFIG.1include content delivery network (CDN) data center(s)116. The CDN data center(s)116of this example include server(s)118that cache content such as images, webpages, videos, etc. accessed via user devices. The server(s)118of the CDN data centers116can be disposed in immersion cooling tank(s) such as the immersion tanks104,108shown in connection with the data centers102,106.

In some instances, the example data centers102,106,116and/or building(s)110ofFIG.1include servers and/or other electronic components that are cooled independent of immersion tanks (e.g., the immersion tanks104,108) and/or an associated immersion cooling system. That is, in some examples, some or all of the servers and/or other electronic components in the data centers102,106,116and/or building(s)110can be cooled by air and/or liquid coolants without immersing the servers and/or other electronic components therein. Thus, in some examples, the immersion tanks104,108ofFIG.1may be omitted. Further, the example data centers102,106,116and/or building(s)110ofFIG.1can correspond to, be implemented by, and/or be adaptations of the example data center200described in further detail below in connection withFIGS.2-16.

Although a certain number of cooling tank(s) and other component(s) are shown in the figures, any number of such components may be present. Also, the example cooling data centers and/or other structures or environments disclosed herein are not limited to arrangements of the size that are depicted inFIG.1. For instance, the structures containing example cooling systems and/or components thereof disclosed herein can be of a size that includes an opening to accommodate service personnel, such as the example data center(s)106ofFIG.1, but can also be smaller (e.g., a “doghouse” enclosure). For instance, the structures containing example cooling systems and/or components thereof disclosed herein can be sized such that access (e.g., the only access) to an interior of the structure is a port for service personnel to reach into the structure. In some examples, the structures containing example cooling systems and/or components thereof disclosed herein are be sized such that only a tool can reach into the enclosure because the structure may be supported by, for a utility pole or radio tower, or a larger structure.

FIG.2illustrates an example data center200in which disaggregated resources may cooperatively execute one or more workloads (e.g., applications on behalf of customers). The illustrated data center200includes multiple platforms210,220,230,240(referred to herein as pods), each of which includes one or more rows of racks. Although the data center200is shown with multiple pods, in some examples, the data center200may be implemented as a single pod. As described in more detail herein, a rack may house multiple sleds. A sled may be primarily equipped with a particular type of resource (e.g., memory devices, data storage devices, accelerator devices, general purpose processors), i.e., resources that can be logically coupled to form a composed node. Some such nodes may act as, for example, a server. In the illustrative example, the sleds in the pods210,220,230,240are connected to multiple pod switches (e.g., switches that route data communications to and from sleds within the pod). The pod switches, in turn, connect with spine switches250that switch communications among pods (e.g., the pods210,220,230,240) in the data center200. In some examples, the sleds may be connected with a fabric using Intel Omni-Path™ technology. In other examples, the sleds may be connected with other fabrics, such as InfiniBand or Ethernet. As described in more detail herein, resources within the sleds in the data center200may be allocated to a group (referred to herein as a “managed node”) containing resources from one or more sleds to be collectively utilized in the execution of a workload. The workload can execute as if the resources belonging to the managed node were located on the same sled. The resources in a managed node may belong to sleds belonging to different racks, and even to different pods210,220,230,240. As such, some resources of a single sled may be allocated to one managed node while other resources of the same sled are allocated to a different managed node (e.g., first processor circuitry assigned to one managed node and second processor circuitry of the same sled assigned to a different managed node).

A data center including disaggregated resources, such as the data center200, can be used in a wide variety of contexts, such as enterprise, government, cloud service provider, and communications service provider (e.g., Telco's), as well in a wide variety of sizes, from cloud service provider mega-data centers that consume over 200,000 sq. ft. to single- or multi-rack installations for use in base stations.

In some examples, the disaggregation of resources is accomplished by using individual sleds that include predominantly a single type of resource (e.g., compute sleds including primarily compute resources, memory sleds including primarily memory resources). The disaggregation of resources in this manner, and the selective allocation and deallocation of the disaggregated resources to form a managed node assigned to execute a workload, improves the operation and resource usage of the data center200relative to typical data centers. Such typical data centers include hyperconverged servers containing compute, memory, storage and perhaps additional resources in a single chassis. For example, because a given sled will contain mostly resources of a same particular type, resources of that type can be upgraded independently of other resources. Additionally, because different resource types (processors, storage, accelerators, etc.) typically have different refresh rates, greater resource utilization and reduced total cost of ownership may be achieved. For example, a data center operator can upgrade the processor circuitry throughout a facility by only swapping out the compute sleds. In such a case, accelerator and storage resources may not be contemporaneously upgraded and, rather, may be allowed to continue operating until those resources are scheduled for their own refresh. Resource utilization may also increase. For example, if managed nodes are composed based on requirements of the workloads that will be running on them, resources within a node are more likely to be fully utilized. Such utilization may allow for more managed nodes to run in a data center with a given set of resources, or for a data center expected to run a given set of workloads, to be built using fewer resources.

Referring now toFIG.3, the pod210, in the illustrative example, includes a set of rows300,310,320,330of racks340. Individual ones of the racks340may house multiple sleds (e.g., sixteen sleds) and provide power and data connections to the housed sleds, as described in more detail herein. In the illustrative example, the racks are connected to multiple pod switches350,360. The pod switch350includes a set of ports352to which the sleds of the racks of the pod210are connected and another set of ports354that connect the pod210to the spine switches250to provide connectivity to other pods in the data center200. Similarly, the pod switch360includes a set of ports362to which the sleds of the racks of the pod210are connected and a set of ports364that connect the pod210to the spine switches250. As such, the use of the pair of switches350,360provides an amount of redundancy to the pod210. For example, if either of the switches350,360fails, the sleds in the pod210may still maintain data communication with the remainder of the data center200(e.g., sleds of other pods) through the other switch350,360. Furthermore, in the illustrative example, the switches250,350,360may be implemented as dual-mode optical switches, capable of routing both Ethernet protocol communications carrying Internet Protocol (IP) packets and communications according to a second, high-performance link-layer protocol (e.g., PCI Express) via optical signaling media of an optical fabric.

It should be appreciated that any one of the other pods220,230,240(as well as any additional pods of the data center200) may be similarly structured as, and have components similar to, the pod210shown in and disclosed in regard toFIG.3(e.g., a given pod may have rows of racks housing multiple sleds as described above). Additionally, while two pod switches350,360are shown, it should be understood that in other examples, a different number of pod switches may be present, providing even more failover capacity. In other examples, pods may be arranged differently than the rows-of-racks configuration shown inFIGS.2and3. For example, a pod may include multiple sets of racks arranged radially, i.e., the racks are equidistant from a center switch.

FIGS.4-6illustrate an example rack340of the data center200. As shown in the illustrated example, the rack340includes two elongated support posts402,404, which are arranged vertically. For example, the elongated support posts402,404may extend upwardly from a floor of the data center200when deployed. The rack340also includes one or more horizontal pairs410of elongated support arms412(identified inFIG.4via a dashed ellipse) configured to support a sled of the data center200as discussed below. One elongated support arm412of the pair of elongated support arms412extends outwardly from the elongated support post402and the other elongated support arm412extends outwardly from the elongated support post404.

In the illustrative examples, at least some of the sleds of the data center200are chassis-less sleds. That is, such sleds have a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, the rack340is configured to receive the chassis-less sleds. For example, a given pair410of the elongated support arms412defines a sled slot420of the rack340, which is configured to receive a corresponding chassis-less sled. To do so, the elongated support arms412include corresponding circuit board guides430configured to receive the chassis-less circuit board substrate of the sled. The circuit board guides430are secured to, or otherwise mounted to, a top side432of the corresponding elongated support arms412. For example, in the illustrative example, the circuit board guides430are mounted at a distal end of the corresponding elongated support arm412relative to the corresponding elongated support post402,404. For clarity ofFIGS.4-6, not every circuit board guide430may be referenced in each figure. In some examples, at least some of the sleds include a chassis and the racks340are suitably adapted to receive the chassis.

The circuit board guides430include an inner wall that defines a circuit board slot480configured to receive the chassis-less circuit board substrate of a sled500when the sled500is received in the corresponding sled slot420of the rack340. To do so, as shown inFIG.5, a user (or robot) aligns the chassis-less circuit board substrate of an illustrative chassis-less sled500to a sled slot420. The user, or robot, may then slide the chassis-less circuit board substrate forward into the sled slot420such that each side edge514of the chassis-less circuit board substrate is received in a corresponding circuit board slot480of the circuit board guides430of the pair410of elongated support arms412that define the corresponding sled slot420as shown inFIG.5. By having robotically accessible and robotically manipulable sleds including disaggregated resources, the different types of resource can be upgraded independently of one other and at their own optimized refresh rate. Furthermore, the sleds are configured to blindly mate with power and data communication cables in the rack340, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. As such, in some examples, the data center200may operate (e.g., execute workloads, undergo maintenance and/or upgrades, etc.) without human involvement on the data center floor. In other examples, a human may facilitate one or more maintenance or upgrade operations in the data center200.

It should be appreciated that the circuit board guides430are dual sided. That is, a circuit board guide430includes an inner wall that defines a circuit board slot480on each side of the circuit board guide430. In this way, the circuit board guide430can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to the rack340to turn the rack340into a two-rack solution that can hold twice as many sled slots420as shown inFIG.4. The illustrative rack340includes seven pairs410of elongated support arms412that define seven corresponding sled slots420. The sled slots420are configured to receive and support a corresponding sled500as discussed above. In other examples, the rack340may include additional or fewer pairs410of elongated support arms412(i.e., additional or fewer sled slots420). It should be appreciated that because the sled500is chassis-less, the sled500may have an overall height that is different than typical servers. As such, in some examples, the height of a given sled slot420may be shorter than the height of a typical server (e.g., shorter than a single rank unit, referred to as “1U”). That is, the vertical distance between pairs410of elongated support arms412may be less than a standard rack unit “1U.” Additionally, due to the relative decrease in height of the sled slots420, the overall height of the rack340in some examples may be shorter than the height of traditional rack enclosures. For example, in some examples, the elongated support posts402,404may have a length of six feet or less. Again, in other examples, the rack340may have different dimensions. For example, in some examples, the vertical distance between pairs410of elongated support arms412may be greater than a standard rack unit “1U”. In such examples, the increased vertical distance between the sleds allows for larger heatsinks to be attached to the physical resources and for larger fans to be used (e.g., in the fan array470described below) for cooling the sleds, which in turn can allow the physical resources to operate at increased power levels. Further, it should be appreciated that the rack340does not include any walls, enclosures, or the like. Rather, the rack340is an enclosure-less rack that is opened to the local environment. In some cases, an end plate may be attached to one of the elongated support posts402,404in those situations in which the rack340forms an end-of-row rack in the data center200.

In some examples, various interconnects may be routed upwardly or downwardly through the elongated support posts402,404. To facilitate such routing, the elongated support posts402,404include an inner wall that defines an inner chamber in which interconnects may be located. The interconnects routed through the elongated support posts402,404may be implemented as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to the sled slots420, power interconnects to provide power to the sled slots420, and/or other types of interconnects.

The rack340, in the illustrative example, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Such optical data connectors are associated with corresponding sled slots420and are configured to mate with optical data connectors of corresponding sleds500when the sleds500are received in the corresponding sled slots420. In some examples, optical connections between components (e.g., sleds, racks, and switches) in the data center200are made with a blind mate optical connection. For example, a door on a given cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable approaches or enters the connector mechanism. Subsequently, the optical fiber inside the cable may enter a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism.

The illustrative rack340also includes a fan array470coupled to the cross-support arms of the rack340. The fan array470includes one or more rows of cooling fans472, which are aligned in a horizontal line between the elongated support posts402,404. In the illustrative example, the fan array470includes a row of cooling fans472for the different sled slots420of the rack340. As discussed above, the sleds500do not include any on-board cooling system in the illustrative example and, as such, the fan array470provides cooling for such sleds500received in the rack340. In other examples, some or all of the sleds500can include on-board cooling systems. Further, in some examples, the sleds500and/or the racks340may include and/or incorporate a liquid and/or immersion cooling system to facilitate cooling of electronic component(s) on the sleds500. The rack340, in the illustrative example, also includes different power supplies associated with different ones of the sled slots420. A given power supply is secured to one of the elongated support arms412of the pair410of elongated support arms412that define the corresponding sled slot420. For example, the rack340may include a power supply coupled or secured to individual ones of the elongated support arms412extending from the elongated support post402. A given power supply includes a power connector configured to mate with a power connector of a sled500when the sled500is received in the corresponding sled slot420. In the illustrative example, the sled500does not include any on-board power supply and, as such, the power supplies provided in the rack340supply power to corresponding sleds500when mounted to the rack340. A given power supply is configured to satisfy the power requirements for its associated sled, which can differ from sled to sled. Additionally, the power supplies provided in the rack340can operate independent of each other. That is, within a single rack, a first power supply providing power to a compute sled can provide power levels that are different than power levels supplied by a second power supply providing power to an accelerator sled. The power supplies may be controllable at the sled level or rack level, and may be controlled locally by components on the associated sled or remotely, such as by another sled or an orchestrator.

Referring now toFIG.7, the sled500, in the illustrative example, is configured to be mounted in a corresponding rack340of the data center200as discussed above. In some examples, a give sled500may be optimized or otherwise configured for performing particular tasks, such as compute tasks, acceleration tasks, data storage tasks, etc. For example, the sled500may be implemented as a compute sled900as discussed below in regard toFIGS.9and10, an accelerator sled1100as discussed below in regard toFIGS.11and12, a storage sled1300as discussed below in regard toFIGS.13and14, or as a sled optimized or otherwise configured to perform other specialized tasks, such as a memory sled1500, discussed below in regard toFIG.15.

As discussed above, the illustrative sled500includes a chassis-less circuit board substrate702, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate702is “chassis-less” in that the sled500does not include a housing or enclosure. Rather, the chassis-less circuit board substrate702is open to the local environment. The chassis-less circuit board substrate702may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative example, the chassis-less circuit board substrate702is formed from an FR-4 glass-reinforced epoxy laminate material. Other materials may be used to form the chassis-less circuit board substrate702in other examples.

As discussed in more detail below, the chassis-less circuit board substrate702includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate702. As discussed, the chassis-less circuit board substrate702does not include a housing or enclosure, which may improve the airflow over the electrical components of the sled500by reducing those structures that may inhibit air flow. For example, because the chassis-less circuit board substrate702is not positioned in an individual housing or enclosure, there is no vertically-arranged backplane (e.g., a back plate of the chassis) attached to the chassis-less circuit board substrate702, which could inhibit air flow across the electrical components. Additionally, the chassis-less circuit board substrate702has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-less circuit board substrate702. For example, the illustrative chassis-less circuit board substrate702has a width704that is greater than a depth706of the chassis-less circuit board substrate702. In one particular example, the chassis-less circuit board substrate702has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, an airflow path708that extends from a front edge710of the chassis-less circuit board substrate702toward a rear edge712has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled500. Furthermore, although not illustrated inFIG.7, the various physical resources mounted to the chassis-less circuit board substrate702in this example are mounted in corresponding locations such that no two substantively heat-producing electrical components shadow each other as discussed in more detail below. That is, no two electrical components, which produce appreciable heat during operation (i.e., greater than a nominal heat sufficient enough to adversely impact the cooling of another electrical component), are mounted to the chassis-less circuit board substrate702linearly in-line with each other along the direction of the airflow path708(i.e., along a direction extending from the front edge710toward the rear edge712of the chassis-less circuit board substrate702). The placement and/or structure of the features may be suitable adapted when the electrical component(s) are being cooled via liquid (e.g., one phase or two phase immersion cooling).

As discussed above, the illustrative sled500includes one or more physical resources720mounted to a top side750of the chassis-less circuit board substrate702. Although two physical resources720are shown inFIG.7, it should be appreciated that the sled500may include one, two, or more physical resources720in other examples. The physical resources720may be implemented as any type of processor, controller, or other compute circuit capable of performing various tasks such as compute functions and/or controlling the functions of the sled500depending on, for example, the type or intended functionality of the sled500. For example, as discussed in more detail below, the physical resources720may be implemented as high-performance processors in examples in which the sled500is implemented as a compute sled, as accelerator co-processors or circuits in examples in which the sled500is implemented as an accelerator sled, storage controllers in examples in which the sled500is implemented as a storage sled, or a set of memory devices in examples in which the sled500is implemented as a memory sled.

The sled500also includes one or more additional physical resources730mounted to the top side750of the chassis-less circuit board substrate702. In the illustrative example, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Depending on the type and functionality of the sled500, the physical resources730may include additional or other electrical components, circuits, and/or devices in other examples.

The physical resources720are communicatively coupled to the physical resources730via an input/output (I/O) subsystem722. The I/O subsystem722may be implemented as circuitry and/or components to facilitate input/output operations with the physical resources720, the physical resources730, and/or other components of the sled500. For example, the I/O subsystem722may be implemented as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, waveguides, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative example, the I/O subsystem722is implemented as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDR5 data bus.

In some examples, the sled500may also include a resource-to-resource interconnect724. The resource-to-resource interconnect724may be implemented as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative example, the resource-to-resource interconnect724is implemented as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem722). For example, the resource-to-resource interconnect724may be implemented as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.

The sled500also includes a power connector740configured to mate with a corresponding power connector of the rack340when the sled500is mounted in the corresponding rack340. The sled500receives power from a power supply of the rack340via the power connector740to supply power to the various electrical components of the sled500. That is, the sled500does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of the sled500. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-less circuit board substrate702, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate702as discussed above. In some examples, voltage regulators are placed on a bottom side850(seeFIG.8) of the chassis-less circuit board substrate702directly opposite of processor circuitry920(seeFIG.9), and power is routed from the voltage regulators to the processor circuitry920by vias extending through the circuit board substrate702. Such a configuration provides an increased thermal budget, additional current and/or voltage, and better voltage control relative to typical printed circuit boards in which processor power is delivered from a voltage regulator, in part, by printed circuit traces.

In some examples, the sled500may also include mounting features742configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled700in a rack340by the robot. The mounting features742may be implemented as any type of physical structures that allow the robot to grasp the sled500without damaging the chassis-less circuit board substrate702or the electrical components mounted thereto. For example, in some examples, the mounting features742may be implemented as non-conductive pads attached to the chassis-less circuit board substrate702. In other examples, the mounting features may be implemented as brackets, braces, or other similar structures attached to the chassis-less circuit board substrate702. The particular number, shape, size, and/or make-up of the mounting feature742may depend on the design of the robot configured to manage the sled500.

Referring now toFIG.8, in addition to the physical resources730mounted on the top side750of the chassis-less circuit board substrate702, the sled500also includes one or more memory devices820mounted to a bottom side850of the chassis-less circuit board substrate702. That is, the chassis-less circuit board substrate702is implemented as a double-sided circuit board. The physical resources720are communicatively coupled to the memory devices820via the I/O subsystem722. For example, the physical resources720and the memory devices820may be communicatively coupled by one or more vias extending through the chassis-less circuit board substrate702. Different ones of the physical resources720may be communicatively coupled to different sets of one or more memory devices820in some examples. Alternatively, in other examples, different ones of the physical resources720may be communicatively coupled to the same ones of the memory devices820.

Referring now toFIG.9, in some examples, the sled500may be implemented as a compute sled900. The compute sled900is optimized, or otherwise configured, to perform compute tasks. As discussed above, the compute sled900may rely on other sleds, such as acceleration sleds and/or storage sleds, to perform such compute tasks. The compute sled900includes various physical resources (e.g., electrical components) similar to the physical resources of the sled500, which have been identified inFIG.9using the same reference numbers. The description of such components provided above in regard toFIGS.7and8applies to the corresponding components of the compute sled900and is not repeated herein for clarity of the description of the compute sled900.

In the illustrative compute sled900, the physical resources720include processor circuitry920. Although only two blocks of processor circuitry920are shown inFIG.9, it should be appreciated that the compute sled900may include additional processor circuits920in other examples. Illustratively, the processor circuitry920corresponds to high-performance processors920and may be configured to operate at a relatively high power rating. Although the high-performance processor circuitry920generates additional heat operating at power ratings greater than typical processors (which operate at around 155-230 W), the enhanced thermal cooling characteristics of the chassis-less circuit board substrate702discussed above facilitate the higher power operation. For example, in the illustrative example, the processor circuitry920is configured to operate at a power rating of at least 250 W. In some examples, the processor circuitry920may be configured to operate at a power rating of at least 350 W.

In some examples, the compute sled900may also include a processor-to-processor interconnect942. Similar to the resource-to-resource interconnect724of the sled500discussed above, the processor-to-processor interconnect942may be implemented as any type of communication interconnect capable of facilitating processor-to-processor interconnect942communications. In the illustrative example, the processor-to-processor interconnect942is implemented as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem722). For example, the processor-to-processor interconnect942may be implemented as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.

The compute sled900also includes a communication circuit930. The illustrative communication circuit930includes a network interface controller (NIC)932, which may also be referred to as a host fabric interface (HFI). The NIC932may be implemented as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, or other devices that may be used by the compute sled900to connect with another compute device (e.g., with other sleds500). In some examples, the NIC932may be implemented as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some examples, the NIC932may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC932. In such examples, the local processor of the NIC932may be capable of performing one or more of the functions of the processor circuitry920. Additionally or alternatively, in such examples, the local memory of the MC932may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels.

The communication circuit930is communicatively coupled to an optical data connector934. The optical data connector934is configured to mate with a corresponding optical data connector of the rack340when the compute sled900is mounted in the rack340. Illustratively, the optical data connector934includes a plurality of optical fibers which lead from a mating surface of the optical data connector934to an optical transceiver936. The optical transceiver936is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector934in the illustrative example, the optical transceiver936may form a portion of the communication circuit930in other examples.

In some examples, the compute sled900may also include an expansion connector940. In such examples, the expansion connector940is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to the compute sled900. The additional physical resources may be used, for example, by the processor circuitry920during operation of the compute sled900. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-less circuit board substrate702discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.

Referring now toFIG.10, an illustrative example of the compute sled900is shown. As shown, the processor circuitry920, communication circuit930, and optical data connector934are mounted to the top side750of the chassis-less circuit board substrate702. Any suitable attachment or mounting technology may be used to mount the physical resources of the compute sled900to the chassis-less circuit board substrate702. For example, the various physical resources may be mounted in corresponding sockets (e.g., a processor socket), holders, or brackets. In some cases, some of the electrical components may be directly mounted to the chassis-less circuit board substrate702via soldering or similar techniques.

As discussed above, the separate processor circuitry920and the communication circuit930are mounted to the top side750of the chassis-less circuit board substrate702such that no two heat-producing, electrical components shadow each other. In the illustrative example, the processor circuitry920and the communication circuit930are mounted in corresponding locations on the top side750of the chassis-less circuit board substrate702such that no two of those physical resources are linearly in-line with others along the direction of the airflow path708. It should be appreciated that, although the optical data connector934is in-line with the communication circuit930, the optical data connector934produces no or nominal heat during operation.

The memory devices820of the compute sled900are mounted to the bottom side850of the of the chassis-less circuit board substrate702as discussed above in regard to the sled500. Although mounted to the bottom side850, the memory devices820are communicatively coupled to the processor circuitry920located on the top side750via the I/O subsystem722. Because the chassis-less circuit board substrate702is implemented as a double-sided circuit board, the memory devices820and the processor circuitry920may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate702. Different processor circuitry920(e.g., different processors) may be communicatively coupled to a different set of one or more memory devices820in some examples. Alternatively, in other examples, different processor circuitry920(e.g., different processors) may be communicatively coupled to the same ones of the memory devices820. In some examples, the memory devices820may be mounted to one or more memory mezzanines on the bottom side of the chassis-less circuit board substrate702and may interconnect with a corresponding processor circuitry920through a ball-grid array.

Different processor circuitry920(e.g., different processors) include and/or is associated with corresponding heatsinks950secured thereto. Due to the mounting of the memory devices820to the bottom side850of the chassis-less circuit board substrate702(as well as the vertical spacing of the sleds500in the corresponding rack340), the top side750of the chassis-less circuit board substrate702includes additional “free” area or space that facilitates the use of heatsinks950having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate702, none of the processor heatsinks950include cooling fans attached thereto. That is, the heatsinks950may be fan-less heatsinks. In some examples, the heatsinks950mounted atop the processor circuitry920may overlap with the heatsink attached to the communication circuit930in the direction of the airflow path708due to their increased size, as illustratively suggested byFIG.10.

Referring now toFIG.11, in some examples, the sled500may be implemented as an accelerator sled1100. The accelerator sled1100is configured, to perform specialized compute tasks, such as machine learning, encryption, hashing, or other computational-intensive task. In some examples, for example, a compute sled900may offload tasks to the accelerator sled1100during operation. The accelerator sled1100includes various components similar to components of the sled500and/or the compute sled900, which have been identified inFIG.11using the same reference numbers. The description of such components provided above in regard toFIGS.7,8, and9apply to the corresponding components of the accelerator sled1100and is not repeated herein for clarity of the description of the accelerator sled1100.

In the illustrative accelerator sled1100, the physical resources720include accelerator circuits1120. Although only two accelerator circuits1120are shown inFIG.11, it should be appreciated that the accelerator sled1100may include additional accelerator circuits1120in other examples. For example, as shown inFIG.12, the accelerator sled1100may include four accelerator circuits1120. The accelerator circuits1120may be implemented as any type of processor, co-processor, compute circuit, or other device capable of performing compute or processing operations. For example, the accelerator circuits1120may be implemented as, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), neuromorphic processor units, quantum computers, machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.

In some examples, the accelerator sled1100may also include an accelerator-to-accelerator interconnect1142. Similar to the resource-to-resource interconnect724of the sled700discussed above, the accelerator-to-accelerator interconnect1142may be implemented as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative example, the accelerator-to-accelerator interconnect1142is implemented as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem722). For example, the accelerator-to-accelerator interconnect1142may be implemented as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some examples, the accelerator circuits1120may be daisy-chained with a primary accelerator circuit1120connected to the NIC932and memory820through the I/O subsystem722and a secondary accelerator circuit1120connected to the MC932and memory820through a primary accelerator circuit1120.

Referring now toFIG.12, an illustrative example of the accelerator sled1100is shown. As discussed above, the accelerator circuits1120, the communication circuit930, and the optical data connector934are mounted to the top side750of the chassis-less circuit board substrate702. Again, the individual accelerator circuits1120and communication circuit930are mounted to the top side750of the chassis-less circuit board substrate702such that no two heat-producing, electrical components shadow each other as discussed above. The memory devices820of the accelerator sled1100are mounted to the bottom side850of the of the chassis-less circuit board substrate702as discussed above in regard to the sled700. Although mounted to the bottom side850, the memory devices820are communicatively coupled to the accelerator circuits1120located on the top side750via the I/O subsystem722(e.g., through vias). Further, the accelerator circuits1120may include and/or be associated with a heatsink1150that is larger than a traditional heatsink used in a server. As discussed above with reference to the heatsinks950ofFIG.9, the heatsinks1150may be larger than traditional heatsinks because of the “free” area provided by the memory resources820being located on the bottom side850of the chassis-less circuit board substrate702rather than on the top side750.

Referring now toFIG.13, in some examples, the sled500may be implemented as a storage sled1300. The storage sled1300is configured, to store data in a data storage1350local to the storage sled1300. For example, during operation, a compute sled900or an accelerator sled1100may store and retrieve data from the data storage1350of the storage sled1300. The storage sled1300includes various components similar to components of the sled500and/or the compute sled900, which have been identified inFIG.13using the same reference numbers. The description of such components provided above in regard toFIGS.7,8, and9apply to the corresponding components of the storage sled1300and is not repeated herein for clarity of the description of the storage sled1300.

In the illustrative storage sled1300, the physical resources720includes storage controllers1320. Although only two storage controllers1320are shown inFIG.13, it should be appreciated that the storage sled1300may include additional storage controllers1320in other examples. The storage controllers1320may be implemented as any type of processor, controller, or control circuit capable of controlling the storage and retrieval of data into the data storage1350based on requests received via the communication circuit930. In the illustrative example, the storage controllers1320are implemented as relatively low-power processors or controllers. For example, in some examples, the storage controllers1320may be configured to operate at a power rating of about 75 watts.

In some examples, the storage sled1300may also include a controller-to-controller interconnect1342. Similar to the resource-to-resource interconnect724of the sled500discussed above, the controller-to-controller interconnect1342may be implemented as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative example, the controller-to-controller interconnect1342is implemented as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem722). For example, the controller-to-controller interconnect1342may be implemented as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.

Referring now toFIG.14, an illustrative example of the storage sled1300is shown. In the illustrative example, the data storage1350is implemented as, or otherwise includes, a storage cage1352configured to house one or more solid state drives (SSDs)1354. To do so, the storage cage1352includes a number of mounting slots1356, which are configured to receive corresponding solid state drives1354. The mounting slots1356include a number of drive guides1358that cooperate to define an access opening1360of the corresponding mounting slot1356. The storage cage1352is secured to the chassis-less circuit board substrate702such that the access openings face away from (i.e., toward the front of) the chassis-less circuit board substrate702. As such, solid state drives1354are accessible while the storage sled1300is mounted in a corresponding rack304. For example, a solid state drive1354may be swapped out of a rack340(e.g., via a robot) while the storage sled1300remains mounted in the corresponding rack340.

The storage cage1352illustratively includes sixteen mounting slots1356and is capable of mounting and storing sixteen solid state drives1354. The storage cage1352may be configured to store additional or fewer solid state drives1354in other examples. Additionally, in the illustrative example, the solid state drives are mounted vertically in the storage cage1352, but may be mounted in the storage cage1352in a different orientation in other examples. A given solid state drive1354may be implemented as any type of data storage device capable of storing long term data. To do so, the solid state drives1354may include volatile and non-volatile memory devices discussed above.

As shown inFIG.14, the storage controllers1320, the communication circuit930, and the optical data connector934are illustratively mounted to the top side750of the chassis-less circuit board substrate702. Again, as discussed above, any suitable attachment or mounting technology may be used to mount the electrical components of the storage sled1300to the chassis-less circuit board substrate702including, for example, sockets (e.g., a processor socket), holders, brackets, soldered connections, and/or other mounting or securing techniques.

As discussed above, the individual storage controllers1320and the communication circuit930are mounted to the top side750of the chassis-less circuit board substrate702such that no two heat-producing, electrical components shadow each other. For example, the storage controllers1320and the communication circuit930are mounted in corresponding locations on the top side750of the chassis-less circuit board substrate702such that no two of those electrical components are linearly in-line with each other along the direction of the airflow path708.

The memory devices820(not shown inFIG.14) of the storage sled1300are mounted to the bottom side850(not shown inFIG.14) of the chassis-less circuit board substrate702as discussed above in regard to the sled500. Although mounted to the bottom side850, the memory devices820are communicatively coupled to the storage controllers1320located on the top side750via the I/O subsystem722. Again, because the chassis-less circuit board substrate702is implemented as a double-sided circuit board, the memory devices820and the storage controllers1320may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate702. The storage controllers1320include and/or are associated with a heatsink1370secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate702of the storage sled1300, none of the heatsinks1370include cooling fans attached thereto. That is, the heatsinks1370may be fan-less heatsinks.

Referring now toFIG.15, in some examples, the sled500may be implemented as a memory sled1500. The storage sled1500is optimized, or otherwise configured, to provide other sleds500(e.g., compute sleds900, accelerator sleds1100, etc.) with access to a pool of memory (e.g., in two or more sets1530,1532of memory devices820) local to the memory sled1300. For example, during operation, a compute sled900or an accelerator sled1100may remotely write to and/or read from one or more of the memory sets1530,1532of the memory sled1300using a logical address space that maps to physical addresses in the memory sets1530,1532. The memory sled1500includes various components similar to components of the sled500and/or the compute sled900, which have been identified inFIG.15using the same reference numbers. The description of such components provided above in regard toFIGS.7,8, and9apply to the corresponding components of the memory sled1500and is not repeated herein for clarity of the description of the memory sled1500.

In the illustrative memory sled1500, the physical resources720include memory controllers1520. Although only two memory controllers1520are shown inFIG.15, it should be appreciated that the memory sled1500may include additional memory controllers1520in other examples. The memory controllers1520may be implemented as any type of processor, controller, or control circuit capable of controlling the writing and reading of data into the memory sets1530,1532based on requests received via the communication circuit930. In the illustrative example, the memory controllers1520are connected to corresponding memory sets1530,1532to write to and read from memory devices820(not shown) within the corresponding memory set1530,1532and enforce any permissions (e.g., read, write, etc.) associated with sled500that has sent a request to the memory sled1500to perform a memory access operation (e.g., read or write).

In some examples, the memory sled1500may also include a controller-to-controller interconnect1542. Similar to the resource-to-resource interconnect724of the sled500discussed above, the controller-to-controller interconnect1542may be implemented as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative example, the controller-to-controller interconnect1542is implemented as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem722). For example, the controller-to-controller interconnect1542may be implemented as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some examples, a memory controller1520may access, through the controller-to-controller interconnect1542, memory that is within the memory set1532associated with another memory controller1520. In some examples, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled1500). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge) technology). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some examples, the memory controllers1520may implement a memory interleave (e.g., one memory address is mapped to the memory set1530, the next memory address is mapped to the memory set1532, and the third address is mapped to the memory set1530, etc.). The interleaving may be managed within the memory controllers1520, or from CPU sockets (e.g., of the compute sled900) across network links to the memory sets1530,1532, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.

Further, in some examples, the memory sled1500may be connected to one or more other sleds500(e.g., in the same rack340or an adjacent rack340) through a waveguide, using the waveguide connector1580. In the illustrative example, the waveguides are 74 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Tx (i.e., transmit) lanes. Different ones of the lanes, in the illustrative example, are either 16 GHz or 32 GHz. In other examples, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets1530,1532) to another sled (e.g., a sled500in the same rack340or an adjacent rack340as the memory sled1500) without adding to the load on the optical data connector934.

Referring now toFIG.16A, a system for executing one or more workloads (e.g., applications) may be implemented in accordance with the data center200. In the illustrative example, the system1610includes an orchestrator server1620, which may be implemented as a managed node including a compute device (e.g., processor circuitry920on a compute sled900) executing management software (e.g., a cloud operating environment, such as OpenStack) that is communicatively coupled to multiple sleds500including a large number of compute sleds1630(e.g., similar to the compute sled900), memory sleds1640(e.g., similar to the memory sled1500), accelerator sleds1650(e.g., similar to the memory sled1000), and storage sleds1660(e.g., similar to the storage sled1300). One or more of the sleds1630,1640,1650,1660may be grouped into a managed node1670, such as by the orchestrator server1620, to collectively perform a workload (e.g., an application1632executed in a virtual machine or in a container). The managed node1670may be implemented as an assembly of physical resources720, such as processor circuitry920, memory resources820, accelerator circuits1120, or data storage1350, from the same or different sleds500. Further, the managed node may be established, defined, or “spun up” by the orchestrator server1620at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. In the illustrative example, the orchestrator server1620may selectively allocate and/or deallocate physical resources720from the sleds500and/or add or remove one or more sleds500from the managed node1670as a function of quality of service (QoS) targets (e.g., a target throughput, a target latency, a target number of instructions per second, etc.) associated with a service level agreement for the workload (e.g., the application1632). In doing so, the orchestrator server1620may receive telemetry data indicative of performance conditions (e.g., throughput, latency, instructions per second, etc.) in different ones of the sleds500of the managed node1670and compare the telemetry data to the quality of service targets to determine whether the quality of service targets are being satisfied. The orchestrator server1620may additionally determine whether one or more physical resources may be deallocated from the managed node1670while still satisfying the QoS targets, thereby freeing up those physical resources for use in another managed node (e.g., to execute a different workload). Alternatively, if the QoS targets are not presently satisfied, the orchestrator server1620may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., the application1632) while the workload is executing. Similarly, the orchestrator server1620may determine to dynamically deallocate physical resources from a managed node if the orchestrator server1620determines that deallocating the physical resource would result in QoS targets still being met.

Additionally, in some examples, the orchestrator server1620may identify trends in the resource utilization of the workload (e.g., the application1632), such as by identifying phases of execution (e.g., time periods in which different operations, having different resource utilizations characteristics, are performed) of the workload (e.g., the application1632) and pre-emptively identifying available resources in the data center200and allocating them to the managed node1670(e.g., within a predefined time period of the associated phase beginning). In some examples, the orchestrator server1620may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center200. For example, the orchestrator server1620may utilize a model that accounts for the performance of resources on the sleds500(e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, the orchestrator server1620may determine which resource(s) should be used with which workloads based on the total latency associated with different potential resource(s) available in the data center200(e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled500on which the resource is located).

In some examples, the orchestrator server1620may generate a map of heat generation in the data center200using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds500and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center200. Additionally or alternatively, in some examples, the orchestrator server1620may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center200and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. The orchestrator server1620may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center200. In some examples, the orchestrator server1620may identify patterns in resource utilization phases of the workloads and use the patterns to predict future resource utilization of the workloads.

To reduce the computational load on the orchestrator server1620and the data transfer load on the network, in some examples, the orchestrator server1620may send self-test information to the sleds500to enable a given sled500to locally (e.g., on the sled500) determine whether telemetry data generated by the sled500satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). The given sled500may then report back a simplified result (e.g., yes or no) to the orchestrator server1620, which the orchestrator server1620may utilize in determining the allocation of resources to managed nodes.

FIG.16Bis a block diagram of an example infrastructure processing unit (IPU)1672. The example IPU1672includes integrated circuit(s)1674. The integrated circuit(s)1674can include, for example, Field Programmable Gate Arrays (FPGAs) and/or Application Specific Integrated Circuits (ASICs). The example IPU1672includes processor circuitry1676such as a central processing unit (CPU).

FIG.16Cis a block diagram of an example graphics processing unit (GPU) accelerator1678. The GPU accelerator1678includes one or more GPUs1680to perform graphics-related workloads.

The IPU1672and the GPU accelerator1678can be peripherals or plug-in systems (e.g., card(s) plugged into slot(s) of, for instance, a server. During operation of the server, workloads can be performed by one or more of the integrated circuit(s)1674, the processor circuitry1676, and/or the GPUs1680of the GPU accelerator1678. Power consumed by, for instance, the IPU1672and the GPU accelerator1678can be proportional to the workload(s) performed by these peripherals.

FIG.17illustrates an example peripheral1700including a field replaceable fan assembly in accordance with teachings of this disclosure. In the example ofFIG.17, the peripheral1700is a peripheral interconnect express (PCIe) card that implements an infrastructure processing unit (IPU). In the foregoing discussion ofFIG.17, the PCIe card1700will be referred to as the IPU1700. However, other types of PCIe cards could be used in connection with the example ofFIG.17, such as a graphics processing unit (GPU), a data processing unit (DPU), a smart network interface card (NIC), an Open Compute Project (OCP) add-in card, etc.

The IPU1700includes a substrate or board1702(e.g., a printed circuit board) including electronic components1704of the IPU1700such as, for example, processor circuitry such as microprocessor(s) and/or field-programmable gate array(s) (FPGA), memory, etc. The example IPU1700ofFIG.17includes a housing1706(e.g., a cover) to at least partially enclose a heat sink1714, which is proximate (e.g., in contact with) the electronic component(s)1704of the IPU1700. For illustrative purposes, the housing1706is shown as uncoupled from the IPU1700inFIG.17to show an interior of the IPU1700. The housing1706includes an aperture or opening1708defined therein to enable air to enter the IPU1700. A shape and/or size of the housing1706and/or the opening1708can differ from the example shown inFIG.17.

The example IPU1700also includes a side panel1710(e.g., an I0bracket) that further services to at least partially enclose the electronic components1704of the IPU1700. As shown inFIG.17, the side panel1710includes a plurality of apertures or openings1712defined therein to facilitate air flow through the IPU1700. A shape and/or size of the side panel1710and/or the openings1712can differ from the example shown inFIG.17.

The electronic components1704generate heat during operation of the IPU1700. To absorb and dissipate the heat generated by the electronic components1704, the IPU1700includes one or more heat sinks1714. The heat sink(s)1714can include a thermally conductive material such as aluminum or copper. The heat sink(s)1714include plates or fins that receive heat transferred from the electronic components1704and dissipate the heat into air flowing through the fins. In the example ofFIG.17, the heat sink1714of the IPU1700includes first fins1716having a first height and a second fins1718having a second height different than (e.g., greater than) the first fins1716. The heat sink1714and/or the fins1716,1718can have different sizes and/or shapes that the examples shown inFIG.17. In some examples, the fins1716,1718have the same height.

The heat sink1714is disposed over one or more of the electronic components1704such as a FPGA and a processor (e.g., a microprocessor) of the IPU1700. Put another way, in the example orientation of the IPU1700shown inFIG.17, the heat sink1714is above one or more of the electronic components1704.

In the example ofFIG.17, a fan tray1720including a fan1722is removably coupled to the IPU1700to facilitate airflow over the heat sink1714(i.e., the fan1722provides means for circulating air). Although examples disclosed herein refer to fans to facilitate circulation of air, the fans can facilitate circulation of other mediums such as other types of gases (e.g., inert gases such nitrogen, helium, noble gases, etc.). For instance, the fans could facilitate flow of gases having a lower temperature than ambient temperature to cool the compute devices, where the low temperature gases can include air and/or other types of gases. The fan tray1720(also sometimes referred to herein as a fan assembly1720) can be slidingly inserted or removed from the IPU1700via a slot1724defined in the side panel1710of the IPU1700. In the example ofFIG.17, the fan tray1720can be moved (e.g., slid) over the portion of the heat sink1714including the first fins1716. As disclosed herein, the example first fins1716ofFIG.17have a lower height than the second fins1718of the heat sink1714. Thus, in some examples, the lower height first fins1716define a travel path for the fan tray1720in the IPU1700.

The slot1724can be defined in the side panel1710based on the location of the heat sink1714in the IPU1700. Although the example IPU1700ofFIG.17includes one slot1724to receive one fan assembly1720, in some examples, the IPU1700can include one or more additional slots and/or slots sized to receive more than one fan assembly1720. The number of slots1724and, thus, the number of fan assemblies1720carried by the IPU1700, can be based on, for example, a size of the IPU1700, an arrangement of the electronic components1704in the IPU1700, a size and/or position of the heat sink(s)1714of the IPU1700, etc.

The fan tray1720includes a first frame1726that defines a perimeter of the fan tray1720. As disclosed herein, the first frame1726supports a second frame, housing, or shuttle1738including the fan1722. As disclosed herein, the shuttle1738serves as means for transporting the fan1722in the PCIe card1700. For example, the shuttle1738can use mechanical means or electromagnetic means to translate the fan1722. The first frame1726can include a metal, a plastic, etc. A size and/or shape of the first frame1726can differ from the example shown inFIG.17. The width and/or length of the first frame1726can be selected based on a size of the IPU1700(e.g., a six inch PCIe card, a 12 inch PCIe card).

The IPU1700includes electrical connectors that facilitate alignment of the fan tray1720in the IPU1700while providing power to the fan1722and/or other electronic components of the fan tray1720disclosed herein. In the example ofFIG.17, the electrical connectors include magnetic pogo pin connectors. For example, a first end1728of the first frame1726of the fan tray1720includes a connector or socket1730. The IPU1700includes pins1732to couple with the connector1730. As shown inFIG.17, the pins1732can be coupled to a portion of the heat sink1714including the second fins1718. In the example ofFIG.17, the pins1732include magnetic pogo pin contacts. Magnetic forces generated by the magnetic pogo pin contacts1732guide or facilitate alignment of the first frame1726in the IPU1700as the first frame1726is slid into the IPU1700. Electrical connections (e.g., power connections) are established between the IPU1700and the electronic components of the fan tray1720when the magnetic pogo pin contacts1732are coupled to the connector1730of the fan tray1720. For instance, power is provided to the fan1722based on the electrical coupling between the magnetic pogo pin contacts1732and the connector of the first frame1726(e.g., via cables or wires carried by the first frame1726and coupled to, for instance, a motor of the fan1722).

A second end1734of the first frame1726includes one or more fasteners1736to further facilitate alignment and/or coupling of the fan tray1720to the IPU1700. For example, the fastener(s)1736can include magnet(s) to mate with magnets on the side panel1710. In some examples, fastener(s)1736include mechanical fastener(s) (e.g., screws, latches) to removably couple the first frame1726to the side panel1710.

In the example ofFIG.17, the magnetic pogo pin connection and the fastener(s)1736are quick release connectors that permit the fan assembly1720to be removed from the IPU1700without affecting or substantially affecting an operational status of the electronic components1704of the IPU1700(e.g., without affecting operation of a processor of the IPU1700). For example, the fan tray1720can be removed from the IPU1700to repair or replace the fan1722without disrupting or substantially disrupting performance of the IPU1700. Rather than powering off the IPU1700to remove the fan1722, the first frame1726of the fan tray1720can be pulled from the IPU1700via the slot1724defined in the side panel1710of the IPU1700. Thus, the example fan tray1720ofFIG.17provides for field replacement (e.g., “hot swapping”) of the fan1722without interfering or substantially interfering with operation of the IPU1700, operation of the host server, etc.

In some examples, the IPU1700could additionally or alternatively include tracks disposed along the travel path of the fan tray1720in the IPU1700to facilitate movement and alignment of the fan tray1720. In such examples, one or more exterior surfaces of the first frame1726could include, for instance, rollers to move along the tracks.

When the fan tray1720is disposed in the IPU1700and the fan1722is operating such that blades1740of the fan1722are rotating, the fan1722pulls in air from the ambient environment via the opening1708in the housing1706and the openings1712in the side panel1710(e.g., an IO bracket) to increase airflow over and/or through the heat sink1714. The blades1740of the fane1722can have a paddle board shape to push air through the IPU1700. A size and/or shape of the fan1722or the fan blades1740can differ from the example shown inFIG.17.

The fan1722is carried by the second frame or shuttle1738of the fan tray1720. A transverse material or base1800(FIG.18) extends across a portion of a width of the shuttle1738support the fan1722. As disclosed herein, the shuttle1738is moveable (e.g., slidable) relative to the first frame1726of the fan tray1720to enable the base1800of the fan1722to be positioned (e.g., moved or translated along an X-Y plane) and, thus, the fan1722to positioned, at different locations along the heat sink1714(e.g., the portion of the heat sink1714) including the first fins1716. In particular, the fan1722can be positioned at location(s) relative to area(s) of the heat sink1714for which increased airflow would enhance cooling of the electronic component(s)1704of the IPU1700.

The example fan tray1720includes means for moving the shuttle1738and, thus, the fan1722(i.e., the base1800of the fan1722). In the example ofFIG.17, the fan tray1720includes an actuator1742to move the shuttle1738. The actuator1742can include a linear actuator, a stepper motor, a servo motor, etc. A portion of the first frame1726of the fan tray1720supports a base1744to support the actuator1742. The actuator1742can push or pull the shuttle1738to position the fan1722(e.g., the base1800of the fan1722) at particular locations relative to the heat sink1714. For instance, an interior surface1746of the first frame1726can include tracks (e.g., power rails) along which the shuttle1738slides. In some examples, an opposing exterior surface1748of the shuttle1738includes rollers to move along the tracks on the first frame1726to facilitate movement of the shuttle1738via the actuator1742. In some examples, the tracks of the first frame1726include electromagnets that generate a magnetic field in response to current provided by the coupling of magnetic pogo contacts1732with the connector1730of the first frame1726. The electromagnets can be selectively activated or deactivated to cause the shuttle1738to move based on attractive magnetic forces in addition to or as an alternative to the actuator1742.

Although the example fan tray1720ofFIG.17includes one fan1722, the fan tray1720could include more than one fan1722. For instance, two fans1722could be carried by the shuttle1738. The number of fans1722of the fan assembly1720can be selected based on a size of the IPU1700, a size of the heat sink1714, etc. Also, a size and/or shape of the fan shuttle1738can differ from the example shown inFIG.17.

The example IPU1700includes fan control circuitry1750. The fan control circuitry1750generates instructions to control operational parameters of the fan1722such as speed at which the fan rotates. In the example ofFIG.17, the fan control circuitry1750generates instructions to cause the actuator1742to move the shuttle1738and, thus, the fan1722relative to the heat sink1714. The fan control circuitry1750can be implemented by processor circuitry (e.g., dedicated processor circuitry) of the IPU1700. The fan control circuitry1750can communicate with the components of the fan tray1720(e.g., a motor of the fan1722, the actuator1742) via wireless or wired communication protocols (e.g., wired connections established between the IPU1700and the fan tray1720as a result of the magnetic pogo pin coupling).

The example IPU1700includes temperature sensors1752to monitor a temperature of the electronic component(s)1704of the IPU1700such as a FPGA, a microprocessor, etc. The temperature sensors1752can be carried by the board1702, can be coupled to or integral with the electronic component(s)1704and/or the heat sink1714, etc. In some examples, the temperature sensor(s)1752are carried by one or more of the first frame1720or the second frame1738of the tray1720. In some examples, the temperature sensors1752are carried by the board1702and/or the tray1720such that the temperature sensors1752are in communication with the electronic component(s)1704and/or the heat sink1714(e.g., detect air temperature of an area including the electronic component(s)1704and/or the heat sink1714). Power consumption and, thus, heat generated, can increase based on workloads performed by, for instance, the FPGA, the processors, etc. of the IPU1700. The fan control circuitry1750analyzes the signals output by the temperature sensors1752indicative of temperatures at different locations of the IPU1700. In some examples, the signals output by the temperature sensor(s)1752are indicative of local temperature associated with the IPU1700(e.g., a temperature of a particular electronic component1704, a temperature of a portion of the IPU1700). In some examples, the signals output by the temperature sensor(s)1752can be used to determine a bulk temperature of the IPU1700. In some examples, the fan control circuitry1750determines a temperature gradient across the portion of the IPU board1702covered by the heat sink1714(e.g., which can include the portion of the board1702that carries the FPGA and/or the processor(s)) based on outputs of the temperature sensors1752. The fan control circuitry1750identifies area(s) of the IPU1700associated with increased temperature (i.e., heat) relative to other area(s) of the IPU1700. The area(s) of the example peripheral card(s) disclosed herein (e.g., the IPU1700) that are associated with increase temperature relative to other area(s) of the peripheral card(s) are sometimes referred to herein as hot spot(s).

The fan control circuitry1750generates instructions to cause the actuator1742to move the shuttle1738to position the fan1722(e.g., the base1800of the fan1722) relative to the area(s) of the heat sink1714that are proximate to (e.g., disposed over) the electronic components1704of the IPU1700that are responsible for the increased heat. In some examples, the fan control circuitry1750instructs the actuator1742to position the fan1722at a particular location relative to the heat sink1714in response to determining that certain area(s) of the IPU1700are associated with a temperature that exceeds a temperature threshold (e.g., a predefined temperature threshold). When the fan1722is located proximate to the hot spot(s), the fan1722augments airflow over the heat sink1714at those locations, thereby providing for increased cooling of the electronic component(s)1704associated with the hot spot(s).

In some examples, the fan tray1720includes one or more fan operating parameters sensors1754to output signals indicative of operating parameters of the fan1722. The fan operating parameters sensor(s)1754can include, for instance, a tachometer to measure rotational speed of the fan1722. The fan operating parameters sensor(s)1754can include, for instance, position sensor(s) to identify a location of the fan1722relative to the IPU1700. The fan control circuitry1750can generate instructions to control the rotational speed of the fan1722based on outputs from the fan operating parameters sensor(s)1754and in view of, for instance, the temperature measurements for the IPU1700.

The fan control circuitry1750monitors changes in temperature at the IPU1700over time and determines if the rotational speed of the fan1722and/or the location of the fan1722relative to the heat sink1714should be adjusted. For example, the fan control circuitry1750can detect changes in the area(s) of the IPU board1702associated with increased heat due to workloads performed by the electronic component(s)1704of the IPU1700at those area(s). Thus, the fan control circuitry1750detects changes in the locations of the hot spots at the IPU1700over time. In some examples, the fan control circuitry1750determines average temperatures of different areas of the IPU1700over time and selects a location(s) for the fan1722to be positioned at based on the average temperatures. The fan control circuitry1750outputs instructions to cause the actuator1742to move (e.g., reposition) the shuttle1738and, thus, the fan1722, based on changes in the location(s) of the hot spot(s). Additionally or alternatively, the fan control circuitry1750can instruct the fan1722to move to different location relative to the heat sink1714based on a duration of time for which the fan1722has been at particular location.

The example fan control circuitry1750can also control a direction of rotation of the fan1722to maximize airflow through the IPU1700. In some examples, the IPU1700can be coupled to a server supported by a rack (e.g., the IPU1700is inserted into a slot or card receiver of the server). The rack can include fan(s) to cool the server. In some examples, based on the mounting configuration of the IPU1700in the server and/or the rotational direction of the rack fan(s), air is pulled into the IPU1700via the openings1712of the side panel1710(e.g., a front panel) and travels across the IPU1700in a first direction. In some examples, air enters via a side (e.g., a rear panel, not shown) of the IPU1700opposite the side panel1710and travels across the IPU1700in a second direction opposite the first direction.

The IPU1700can include the temperature sensors1752located proximate to the side panel1710(e.g., the front panel) of the IPU1700and at the opposite side (e.g., the rear panel). Based on the outputs of the temperature sensors1752, the fan control circuitry1750detects a direction of the airflow through the IPU1700. For example, when a temperature gradient across the IPU board1702indicates that the temperature of the IPU1700at the front or side panel1710(is lower than the temperature of the IPU1700at the rear panel, the fan control circuitry1750determines that the air is being pulled into the IPU170via the openings1712in the side panel1710. The fan control circuitry1750outputs instructions to cause the blades1740of the fan1722to rotate in a particular direction (e.g., clockwise or counter clockwise) based on the direction of airflow through the IPU1700. The rotational direction of the blades1740of the fan1722can be selected to enable the fan blades1740to guide the flow of air through the IPU1700rather than move against the direction of airflow. The instructions for rotational directional control can be executed by, for instance, the motor and/or rotor drive circuitry of the fan1722. In some examples, the fan control circuitry1750additionally or alternatively controls rotational speed of the fan1722based on the airflow direction.

The fan control circuitry1750can monitor a performance of the fan1722over time. For example, based on the outputs of the fan operating parameter sensor(s)1754(e.g., the tachometer) and/or the temperature sensor(s)1752, the fan control circuitry1750can detect a failure state or a potential failure state of the fan1722(e.g., if the blades1740of the fan1722re not rotating, or are rotating at a speed below a threshold speed, and if the temperature of the component(s) of the peripheral1700proximate to the fan1722is increasing when cooling by the fan1722is otherwise expected). To prevent the fan1722from hindering airflow when the fan1722is in a failed state or potential failed state, the fan control circuitry1750generates instructions to cause the fan1722(e.g., the fan motor) to stop operating. The fan control circuitry1750can also instruct the actuator1742to move the fan1722(e.g., translate the fan base1800) to a location at which the fan1722interferes the least with the flow of ambient air into the IPU1700. For example, the fan control circuitry1750can instruct the actuator1742to move the shuttle1738so that the fan1722is located proximate to one of the ends of the opening1708of the housing1706(rather than in the middle of the opening1708) to maximize airflow through the opening1708.

In some examples, if the fan control circuitry1750detects that the fan1722has failed or at risk of failing, the fan control circuitry1750can cause power and/or electrical connections provided to the fan tray1720to cease. As such, the electrical couplings between the fan tray1720and the IPU1700are disrupted and the fan tray1720can be removed from the IPU1700(e.g., slid out of the IPU1700via the slot1724).

In examples which the fan control circuitry1750detects that the fan1722has failed or at risk of failing, the fan control circuitry1750can cause alert(s) (e.g., audio alerts, visual alerts) to be output to inform, for instance, a data center operator of the potential for fan maintenance. In some such examples, the fan control circuitry1750communicates with the electronic component(s)1704of the IPU (e.g., FPGA, the processor(s)) to cause power consumption by the IPU1700to be reduced or capped to lower the amount of heat generated by the component(s)1704until the fan1722is repaired or replaced. Thus, the IPU1700can continue to operate without the airflow augmentation provided by the fan1722, which provides for substantially less disruption than if the IPU1700was powered down to address the failed fan1722.

FIGS.18and19illustrate movement of the shuttle1738of the example fan tray1720ofFIG.17and, thus, the fan1722carried by the shuttle1738. For illustrative purposes, the IPU1700is not shown inFIG.17. The fan1722is supported by the base1800. The base1800can have a different shape and/or size than shown inFIGS.18and19. As illustrated inFIGS.18and19, the actuator1742causes the shuttle1738to move relative to (e.g., along a length of) the first frame1726of the fan tray1720. For instance, inFIG.18, the actuator1742has pushed the shuttle1738away from the second end1734of the first frame1726and toward the first end1728of the first frame1726. In the example ofFIG.19, the actuator1742has pulled the shuttle1738toward to the second end1734of the first frame1726and away from the first end1728of the first frame1726. As disclosed herein, in some examples, the shuttle1738slides along the rails or tracks of the first frame1726.

FIGS.20and21are top views of the example IPU1700ofFIG.17including the example fan assembly or tray1720ofFIGS.17-19disposed therein. In particular,FIG.20illustrates the fan1722(e.g., the fan base1800) of the fan assembly1720in a first position relative to the heat sink1714. The first position of the fan1722can be selected by the fan control circuitry1750based on a location of a hot spot of the IPU700, or an area of increased heat generated at the IPU1700due to performance of the electronic component(s)1704(e.g., the FPGA) of the IPU1700located at or proximate to the area.

FIG.21illustrates the fan1722(e.g., the fan base1800) of the fan tray1720in a second position relative to the heat sink1714different than the first position shown inFIG.20. The fan control circuitry1750can cause the fan1722to move from the first position ofFIG.20to the second position ofFIG.21based on changes in the temperature of various location in the IPU1700(e.g., changes in locations of hot spots at the IPU1700). For example, the fan control circuitry1750can instruct the actuator1742to move the shuttle1738to cause the base1800(FIG.18) of the fan1722to move from the first position ofFIG.20to the second position ofFIG.21in response to an increase in heat generated by the electronic component(s)1704of the IPU1700that are proximate to the location of fan1722inFIG.21as compared to the amount of heat generated by the electronic component(s)1704of the IPU1700that are proximate to the fan1722at the location of the fan1722inFIG.20.

FIG.22illustrates another example peripheral2200including a field replaceable fan assembly in accordance with teachings of this disclosure. In the example ofFIG.22, the peripheral2200is a component interconnect express (PCIe) card that implements a graphics card including a graphics processing unit (GPU). In the foregoing discussion ofFIG.22, the PCIe card2200will be referred to as the graphics card2200. Although the example ofFIG.22is disclosed in connection with the graphic card2200, the example ofFIG.22could be used with other types of PCIe cards.

FIG.22is a top view of the graphics card2200. For illustrative purposes, a housing of the graphics card2200(e.g., the housing1706ofFIG.17) is not shown inFIG.22. The graphics card2200include a board2202that supports electronic components of the graphics card2200(e.g., the GPU). The electronic component(s) of the graphics card2200generate heat during operation of the component(s). The example graphics card2200includes a heat sink2204to absorb and dissipate the heat generated by the electronic component(s).

The example graphics card2200ofFIG.2includes fans to augment airflow over the heat sink2204to increase cooling. A first fan tray2206(also referred to as a fan assembly2206) is disposed over a first portion of the heat sink2204. The first fan tray2206includes a fan2208. The first fan tray2206includes a first frame2210and a second frame or shuttle2212moveable relative to the first frame2210of the first fan tray2206. The first shuttle2212carries the first fan2208as substantially as disclosed in connection withFIG.17. For instance, the first fan2208can be supported by the base1800(FIG.18).

A second fan assembly or fan tray2214is disposed over a second portion of the heat sink2204different than the first portion over which the first fan tray2206is located. The second fan tray2214includes a fan2216. The second fan tray2214includes a first frame2218and a second frame or shuttle2220moveable relative to the first frame2218of the second fan tray2214. The first shuttle2220carries the fan2216as substantially as disclosed in connection withFIG.17(e.g., via the fan base1800).

A location of the first fan tray2206and/or the second fan tray2214relative to the heat sink2204can differ from the example locations shown inFIG.22. Also, although in the example ofFIG.22, the trays2206,2214substantially extend a length of the heat sink2204, in other example, a size and/or shape of the respective fan trays2206,2214can differ from the example shown inFIG.22. Also, a size and/or shape of the fans2208,2216can differ from the examples shown inFIG.22. The graphics card2200can include additional fan trays2206,2214and/or fans2208,2216than shown inFIG.22based on, for instance, a size of the heat sink2204of the graphics card2200.

The fan trays2206,2214can be removably coupled to the graphics card2200via opening(s) formed in a housing of graphics card2200(e.g., a slot formed in a side panel of the graphics card2200as disclosed in connection with the example ofFIG.17). The fan trays2206,2214can include power pin sockets or connectors to mate with corresponding contacts (e.g., pogo pins) in the graphics card2200. As such, electrical connections can be formed between the fan trays2206,2214and the graphics card2200to provide, for instance, power to the fans2208,2216substantially as disclosed in connection with the example ofFIG.17.

In the example ofFIG.22, the first tray2206includes a track2222and the second tray2214includes a second track2224. The shuttle2212of the first fan tray2206is moveable along the track2222to translate the fan2208(e.g., move the fan base1800) of the first fan tray2206relative to the heat sink2204. Also, the shuttle2220of the second fan tray2214is moveable along the track2224of the second fan tray2214to translate the fan2216(e.g., move the fan base1800) of the second fan tray2214relative to the heat sink2204. In the example ofFIG.22, the respective shuttles2212,2220move in response to instructions output by the fan control circuitry1750of the graphics card2200. The fan control circuitry1750can communicate with the components of the fan trays2206,2214via wireless or wired communication protocols.

In some examples, each of the tracks2222,2224is a single rail and the corresponding shuttles2212,2220are slidingly coupled to the rail (e.g., via rollers, via an extruded channel formed in a bottom of the fan shuttle2212,2220that mates with the rail). In some examples, each of the tracks2222,2224include two rails and the corresponding shuttles2212,2220are slidingly coupled to the two rails. In some examples, the tracks2222,2224(e.g., power rails) carry power to the fans2208,2216and/or include cables to establish electrical connections between the fan control circuitry1750and the fans2208,2216(e.g., motors of the fans2208,2216). In some examples, one or more portions of the tracks2222,2224include openings or channels extending through the tracks2222,2224. The channels can help direct airflow generated by the fans2208,2216.

In the example ofFIG.22, the first frame2210of the first fan tray2206includes a first tray magnet2226coupled to a first interior end2228of the first frame2210and a second tray magnet2230coupled to a second interior end2232of the frame2210opposite the first interior end2228. In the example ofFIG.22, the tray magnets2226,2230are located on an interior surface of the first frame2210of the first tray2206such a surface2234of the first tray magnet2226faces the first fan2208and a surface2236of the second tray magnet2230each face the shuttle2212of the first fan tray2206. The first and second tray magnets2226,2230can include electromagnets.

Also, the shuttle2212of the first fan tray2206includes a first shuttle magnet2238coupled to a first end2240of the shuttle2212and a second shuttle magnet2242coupled to a second end2244of the shuttle2212opposite the first end2240. A surface2246of the first shuttle magnet2238faces the surface2234of the first tray magnet2226. The surface2246of the first shuttle magnet2238is associated with a first polarity. A surface2248of the second shuttle magnet2242faces the surface2236of the second tray magnet2230. The surface2248of the second shuttle magnet2242is associated with a second polarity opposite the first polarity of the surface2246of the first shuttle magnet2238.

The first frame of the second fan tray2214includes a first tray magnet2250and a second tray magnet2252as disclosed above in connection with the first fan tray2206. The first and second tray magnets2250,2252can include electromagnets. Also, the shuttle2220of the second fan tray2214includes a first shuttle management2254and a second shuttle magnet2256as disclosed above in connection with the first fan tray2206.

In the example ofFIG.22, the fan control circuitry1750of the graphics card2200controls a polarity of the respective tray magnets2226,2230of the first fan tray2206to cause the shuttle2212and, thus, the first fan2208, to translate or move along the first track2222based on attractive or repelling magnetic forces between the respective tray magnets2226,2230of the first frame2210and the corresponding shuttle magnets2238,2242. Also, the fan control circuitry1750controls a polarity of the respective tray magnets2250,2252of the second fan tray2214to cause the shuttle2220to translate or move the second fan2216along the second track2224based on attractive or repelling magnetic forces between the respective tray magnets2250,2254of the first frame2218of the second fan tray2214and the corresponding shuttle magnets2254,2256. Put another way, in the example ofFIG.22, the tray magnets2226,2230,2250,2252serve as actuators to cause the shuttles2212,2220to move.

The graphics card2200include the temperature sensors1752to measure the temperature of the graphics card2200at different locations in the graphics card2200. The fan control circuitry1750analyzes the temperature data corresponding to the outputs of the temperature sensors1752to identify hot spots at the graphics card2200. For example, the fan control circuitry1750can determine, based on the temperature sensor data, that an electronic component of the graphics card2200proximate to the second end2232of the first frame2210of the first fan tray2206is generating an increased amount of heat relative to other electronic components associated with the portion of the heat sink2204over which the first fan tray2206extends. As such, the fan control circuitry1750outputs instructions to cause the shuttle2212to move to the second end2232of the first frame2210so that the first fan2208can increase airflow over the portion of the heat sink2204proximate to the second end2232of the first frame2212.

In particular, in the example ofFIG.22, the fan control circuitry1750causes the second tray magnet2230of the first fan tray2206to have a polarity that is opposite a polarity of the second shuttle magnet2242of the shuttle2212(e.g., by affecting a direction of a current provided to the second magnet2230). Due to the opposing polarities, the second shuttle magnet2242of the shuttle2212is attracted to the second tray magnet2230. The shuttle2212including the first fan2208is pulled along the first track2222toward the second tray magnet2230due to attracting magnetic forces between the tray and shuttle magnets2230,2242. As a result, the second shuttle magnet2242couples with the second tray magnet2230and the first fan2208is located proximate to the hot spot.

In some examples, when the second shuttle magnet2242is coupled with the second tray magnet2230, the fan control circuitry1750determines, based on temperature sensors1752of the graphics card2200that an electronic component proximate to the first end2228of the first frame2210of the first fan tray2206is generating an increased amount of heat relative to other electronic components over which the heat sink2204extends. In this example, the fan control circuitry1750can cause a polarity of the first tray magnet2226of the first frame2210to have a polarity that is opposite the polarity of the first shuttle magnet2238of the shuttle2212(e.g., by affecting a direction of current flowing through the first tray magnet2226). Also, the fan control circuitry1750can cause a polarity of the second tray magnet2230of the first frame2210of the first fan tray2206to have a polarity that is the same as the polarity of the second shuttle magnet2242of the shuttle2212. As a result, the second tray magnet2230and the second shuttle magnet2242repel each other. Thus, the second shuttle magnet2242uncouples from the second tray magnet2230. Put another way, the second end2244of the first shuttle2212is pushed away from the second tray magnet2230along the track2222due to repelling magnetic forces. Also, the first end2240of the shuttle2212including the first shuttle magnet2238is pulled along the track2222toward the first tray magnet2226by the attracting magnetic forces between the first tray and first shuttle magnets2226,2238. The first shuttle magnet2238couples with the first tray magnet2226and the first fan2208is located proximate to the first end2228of the first frame2210to provide for increased cooling.

In some examples, the fan control circuitry1750causes current to the second tray magnet2230to turn off, rather than change polarity. When the second tray magnet2230is turned off, the second tray magnet2230no longer generates the magnetic field. As a result, the second shuttle magnet2242uncouples from the second tray magnet2230and the shuttle2212can be pulled toward the second tray magnet2226.

Thus, in the example ofFIG.22, the fan control circuitry1750causes the first fan2208to be moved proximate to area(s) of the graphics card2200associated with increased heat (i.e., hot spots) by controlling attracting or repelling magnetic forces between the respective ones of the tray magnets2226,2230and corresponding ones of the shuttle magnets2238,2230. The shuttle2212and, thus, the first fan2208of the first fan tray2206is selectively pushed and/or pulled along the track2222due to the magnetic forces.

In some examples, the first fan2208(e.g., the fan base1800) can be positioned along intermediate positions of the track2222between the first and second ends2228,2232of the first frame2210. For example, the fan control circuitry1750can adjust a polarity of the first and second tray magnets2226,2230of the first fan tray2206such that (a) the first tray magnet2226and the first shuttle magnet2238of the shuttle2212are opposite polarities and (b) the second tray magnet2230and the second shuttle magnet2242of the shuttle2212are opposite polarities. The fan control circuitry1750can adjust a strength of the current flowing through the tray magnets2226,2230and, thus, a strength of the magnetic forces generated by the magnets2226,2230. As a result of (a) the opposing magnetic forces between the first tray magnet2226and the first shuttle magnet2238and (b) the opposing magnetic forces between the second tray magnet2230and the second shuttle magnet2242, the shuttle2212and, thus, the fan2208, can be held by the magnetic forces at a particular intermediate position along the track2222.

In some examples, the track2222of the first fan tray2206includes electromagnets disposed along a length of the track2222. The fan control circuitry1750can cause the electromagnets to be selectively activated or deactivated to cause the shuttle2212to move along the track2222and be held at certain intermediate positions along the track2222based on the locations of the hot spots of the graphics card2200. In some such examples, the shuttle2212can include magnets disposed along a surface of the shuttle2212that faces the track2222and are attracted or repelled from the track magnets.

The shuttle2220carrying the second fan2216can move along the second track2224of the second fan tray2214in the same or substantially the same manner as disclosed above in connection with the shuttle2212of the first fan tray2206based on control of magnetic forces between the tray magnets2250,2252and corresponding ones of the shuttle magnets22254,2256. For example, when the fan control circuitry1750determines that a hot spot is located at the portion of the graphics card2200over which the second fan tray2214is located, the fan control circuitry1750can cause the shuttle2220of the second fan tray2214to move along the second track22224to provide increased airflow over the heat sink2204at the hot spot location.

Thus, the locations of the first and second fans2208,2216can be selected to maximize or substantially maximize airflow over the heat sink2204to target hot spots at the graphics card2200. In some examples, the fan control circuitry1750causes the first fan2208to move relative to the second fan2216or vice versa. The fan control circuitry1750monitors changes in the temperature of the graphics card2200due to heat generated by the electronic components of the graphics card2200over time to identify changes in the locations of the hot spots and to cause the first fan2208and/or the second fan2216to translate (e.g., move the respective fan bases1800) to provide for increased cooling at the identified locations. In some examples, the fan control circuitry1750causes the fans2208,2216to move based on a duration of time for which the fans2208,2216have been at a particular location relative to the heat sink2204to provide for dynamic increases in cooling provided by the fans2208,2216across the heat sink2204during operation of the graphics card2200. In some examples, the fan control circuitry1750causes the shuttles2212,2220of the respective fan trays2206,2214to move at the same time or substantially the same time. In some examples, the fan control circuitry1750causes the shuttles2212,2220to move at different times.

In some examples, when the first fan2208is located proximate to, for instance, the first end2228of the first frame2210of the first fan tray2206(e.g., the first tray magnet2226is coupled to the first shuttle magnet2238), the fan control circuitry1750generates instructions to cause the shuttle2220of the second fan tray2214to move the second fan2216(e.g., the fan base1800) to the end of the second tray2214that is opposite the end at which the first fan2208is located in the first fan tray2206(i.e., cause the second tray magnet2252of the second fan tray2214to couple with the second shuttle magnet2256of the shuttle2220). In such examples, the first fan2208and the second fan2216are located diagonally or substantially diagonally across the heat sink2204. As a result of the opposite locations of the fans2208,2216, relative to the heat sink2204, airflow over the heat sink2204is increased across an area of the heat sink2204as compared to if both fans2208,2216, were located on the same side of the heat sink2204. The fan control circuitry1750can identify or track the locations of the fans2208,2216based on outputs from the fan operating parameters sensor(s)1754(e.g., position sensors).

The fan control circuitry1750can generate instructions to control a rotational speed of blades of each of the fans2208,2216and communicate the instructions to, for instance, drive circuitry and/or a motor of the respective fans2208,2216. The fan control circuitry1750can detect when the rotational speed of the blades of the respective fans2208,2216, is below a threshold based on outputs of the fan operating parameter sensor(s)1754, which can indicate a failure state of one or more of the fans2208,2216(e.g., in some instance, in connection with increase in temperature at the peripheral1700). In such examples, the fan control circuitry1750can cause an alert (e.g., an audio alert, a visual alert) to be output to notify, for instance, a data center operator that the fan(s)2208,2216may need to be repaired or replaced. For example, each of the fan trays2206,2214can include a light emitting diode (LED)2258and the fan control circuitry1750can cause the LED to be activated when the fan2208,2216of a particular tray2206,2214, is rotating below a threshold RPM speed to provide a visual alert as to the operational status of the fan2208,2216.

The fan control circuitry1750can generate instructions to control a rotational direction of the blades of each of the fans2208,2216and communicate the instructions to, for instance, drive circuitry and/or a motor of the respective fans2208,2216. In some examples, the fan control circuitry1750instructs the blades of the first fan2208to rotate in a first direction and the blades of the second fan2216to rotate in a second or counter direction. As a result, the first fan2208can, for instance, pull cool air from the ambient environment into the graphics card2200and the second fan2216can push hot air generated in the graphics card2200out of the graphics card2200. Thus, temperature gradients across the graphics card2200(e.g., across the heat sink2204) are minimized. In other examples, the fan control circuitry1750can cause both fans2208,2216to rotate in the same direction.

FIG.23illustrates another example peripheral2300including a field replaceable fan assembly in accordance with teachings of this disclosure. In the example ofFIG.23, the peripheral2300is a component interconnect express PCIe card that implements a graphics card including a graphics processing unit (GPU). In the foregoing discussion ofFIG.23, the PCIe card2300will be referred to as the graphics card2300. Although the example ofFIG.23is disclosed in connection with the graphic card2300, the example ofFIG.23could be used with other types of PCIe cards.

FIG.23is a top view of the graphics card2300. For illustrative purposes, a housing of the graphics card2300(e.g., the housing1706ofFIG.17) is not shown inFIG.23. The graphics card2300include a board2302that supports electronic components of the graphics card2300(e.g., the GPU). The electronic component(s) of the graphics card2300generate heat during operation of the component(s). The example graphics card2300includes a heat sink2304to absorb and dissipate the heat generated by the electronic component(s).

The graphics card2300includes a first card magnet2306, a second card magnet2308, and a third card magnet23010. The card magnets2306,2308,2310can be supported by, for instance, the board2302, an interior surface of the housing of the graphics card2300(e.g., an interior surface of a sidewall defining the housing), etc. The card magnets2306,2308,2310can include pole bar magnets, where each card magnet2306,2308,2310has a first pole2312having a first polarity and a second pole2314having a second polarity opposite the first polarity. In some examples, the card magnets2306,2308,2310include electromagnets.

As shown inFIG.23, the card magnets2306,2308,2310are located proximate to an edge of the heat sink2304. As disclosed herein, the card magnets2306,2308,2310are positioned in the graphics card2300relative to the heat sink2304such that a tray including a fan can be slid over the heat sink2304and coupled to one of the card magnets2306,2308,2310to provide for increased airflow over the heat sink2304.

In the example ofFIG.23, each of the card magnets2306,2308,2310include one or more power supply pins2316. For example, inFIG.23, each of the card magnets2306,2308,2310includes six power supply pins2316. However, the card magnets2306,2308,2310could include additional or fewer power supply pins2316. Also, a shape and/or size of the card magnets2306,2308,2310can differ from the examples shown in FIG.

In the example ofFIG.23, each of the magnets2306,2308,2310provide means for aligning a tray including a fan in the graphics card2300. As shown inFIG.23, a first fan assembly or tray2318includes a first fan2320. A second fan assembly of tray2322includes a second fan2324. A third fan assembly or tray2326includes a third fan2328. The trays2318,2322,2326and/or the fans2320,2324,2328can have different sizes and/or shapes than the examples ofFIG.23. The fans2320,2324,2328can be supported in the trays2318,2322,2326by respective bases (e.g., the base1800ofFIG.18) as disclosed in connection withFIGS.17-22. The example graphics card2300can include additional or fewer fan trays2318,2322,2326and corresponding card magnets2306,2308,2310to support the trays in the graphics card2300.

The first fan tray2318will be disclosed in detail with the understanding that the second fan tray2322and the third fan tray2326are the same or substantially the same as the first fan tray2318. An exterior surface2327of the first fan tray2318includes a tray magnet2330coupled thereto. The tray magnet2330includes power pin sockets2332to receive corresponding ones of the power supply pins2316of any of the first card magnet2306, the second card magnet2308, or the third card magnet2310of graphics card2300.

The tray magnet2330includes a first pole2334having a first polarity and a second pole2336having a second polarity opposite the first polarity. In particular, the first polarity of the first pole2334is opposite the first polarity of the first pole2312of the respective ones of the card magnets2306,2308,2310. The second polarity of the second pole2336is opposite the second polarity of the second pole2314of the respective ones of the card magnets2306,2308,2310. The first fan tray2318can be slid into the graphics card2300over the heat sink2304(e.g., via an opening in a sidewall of the housing such as the slot1724ofFIG.17). For instance, the first fan tray2318can be slid over a first portion of the heat sink2304proximate to the first card magnet2306. When the first fan tray2318is inserted into the graphics card2300and slid over the heat sink2304, the first pole2334of the first tray magnet2330is attracted to the first pole2312of the first card magnet2306(due the opposing polarities). Also, the second pole2336of the first tray magnet2330is attracted to the second pole2314of the first card magnet2306(due the opposing polarities). The first pole2312of the first tray magnet2330couples to the first pole2312of the first card magnet2306. Also, the second pole2336of the first tray magnet2330couples to the second pole2314of the first card magnet2306. Thus, the first card magnet2306facilitates alignment of the first fan tray2318in the graphics card2300based on magnetic forces between the first card magnet2306and the first tray magnet2330.

When the first tray magnet2330and the first card magnet2306couple to one another, the power supply pins2316of the first card magnet2306are received in corresponding ones of the power pin sockets2332of the first tray magnet2330. As a result, power is supplied to the first fan2320by the graphics card2300(e.g., via electrical cables carried by the first fan tray2318to a motor of the first fan2320). When the first fan230is operating, the first fan2320provides for increased airflow over the first portion of the heat sink2304to increase cooling of electronic components of the heat sink2304proximate to the first portion of the heat sink2304.

The second fan tray2322can be inserted into the graphics card2300and coupled to the second card magnet2308via a second tray magnet2338to provide for increased airflow over a second portion of the heat sink2304as disclosed in connection with the first fan tray2318. Also, the third fan tray2326can be inserted into the graphics card2300and coupled to the third card magnet2310via a third tray magnet2340to provide for increased airflow over a third portion of the heat sink2304as disclosed in connection with the first fan tray2318. Thus, when the first, second, and third fans2320,2324,2328are disposed in the graphics card2300, the fans2320,2324,2328provide for increased airflow over or substantially over an area of the heat sink2304.

In the example ofFIG.23, the speed and/or rotational direction of blades of the fans2320,2324,2328of the respective fan trays2318,2322,2326is controlled by the fan control circuitry1750based on outputs of the fan operating parameter sensors1754substantially as disclosed in connection withFIGS.17and22. For instance, the speed of the blades of the fans2320,2324,2328can be adjusted in response to the fan control circuitry1750identifying hot spots at the graphics card2300based on analysis of temperature data for the card. The locations of the hot spots can be identified based on outputs of the temperature sensors1752substantially as disclosed in connection withFIGS.17and22. The fan control circuitry1750can also monitor a performance of the fans2320,2324,2328and generate alerts when, for instance, the speed (e.g., RPM) of one or more of the fans2320,2324,2328falls below a threshold and the temperature of the peripheral2300is increasing at location(s) proximate to the fan(s)2320,2324,2328. For instance, each of the fan trays2318,2322,2326can include a light emitting diode (LED) (e.g., the LED2258ofFIG.22). When the fan control circuitry1750determines that one of the fans2320,2324,2328is not operating at the threshold fan speed, the fan control circuitry1750can output instructions to cause the LED of the corresponding fan tray2318,2322,2326to activate to alert, for instance, a data center operator. In some examples, if one of the fans2320,2324,2328is not operating at an expected performance speed due to maintenance issues, the fan control circuitry1750can generate instructions to cause a rotational speed of the other fans2320,2324,2328to be adjusted (e.g., increased) compensate for the fan2320,2324,2328that is experiencing maintenance issues. The instructions from the fan control circuitry1750can be transmitted to, for instance, drive circuitry and/or a motor of the respective fans2320,2324,2328via wired or wireless communication protocols.

In the example ofFIG.23, the magnetic coupling between the tray magnets2330,2338,2340of the respective fan trays2318,2322,2326and the corresponding card magnets2306,2308,2310enables each of the fan trays2318,2322,2326to be selectively removed from the graphics card2300to undergo maintenance or to be replaced without affecting operation of the graphics card2300or the other ones of the fans2320,2324,2328. For instance, if the fan control circuitry1750determines that the second fan2324should be repaired or replaced, the fan control circuitry1750can affect (e.g., disrupt) the magnetic coupling between the second card magnet2308and the second tray magnet2338. In some examples, the fan control circuitry1750can cause a current flowing through the second card magnet2308to be adjusted to adjust a polarity of the poles2312,2314of the second tray magnet2308such that the second card magnet2308repels rather than attracts the second tray magnet2338. As result, the second fan tray2322can be removed from the graphics card2300. In some examples, the second fan tray2322can be removed from the graphics card2300via mechanical actuation. For example, a housing of the graphics card2300can include a spring that is loaded when the second fan tray2322is inserted into the housing and a button that, when pressed by a user, causes the spring to release to eject the second fan tray2322.

Thus, the second fan tray2322including the second fan2324can be removed from the graphics card2300while the graphics card2300remains plugged into a slot of, for instance, a server, and while the first fan2320and the third fan2328continue to operate to provide airflow over the heat sink2304. Therefore, the removable coupling of the individual trays2318,2322,2326to the card magnets2306,2308,2310minimizes disruption to the operation of the graphics card2300. The individual fan trays2318,2322,2326can be removed (e.g., field replaceable or hot swapped) during operation of the graphics card2300without powering down the graphics card2300. Also, the isolated nature of each fan2320,2324,2328in a respective tray2318,2322,2326enables the fans2320,2324,2328to be individually removed from the graphics card2300without affecting operation of the other fans2320,2324,2328. As a result, the fans2320,2324,2328continue to provide for increased cooling of the electronic components of the graphics card2300while one (or more) of the fans2320,2324,2328is removed from the graphics card2300for maintenance or replacement.

FIG.24is a block diagram of the example fan control circuitry1750ofFIGS.17,22, and/or23to control one or more parameters (e.g., location, rotational speed, rotational direction) of the example fans1722,2208,2216,2320,2324,2328disclosed in connection withFIGS.17-23. The fan control circuitry1750ofFIG.24may be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc.) by processor circuitry such as a central processing unit executing instructions. Additionally or alternatively, the fan control circuitry1750ofFIG.24may be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc.) by an ASIC or an FPGA structured to perform operations corresponding to the instructions. It should be understood that some or all of the circuitry ofFIG.24may, thus, be instantiated at the same or different times. Some or all of the circuitry may be instantiated, for example, in one or more threads executing concurrently on hardware and/or in series on hardware. Moreover, in some examples, some or all of the circuitry ofFIG.24may be implemented by microprocessor circuitry executing instructions to implement one or more virtual machines and/or containers.

The example fan control circuitry1750ofFIG.24includes temperature analysis circuitry2402, fan location determination circuitry2404, actuator control circuitry2406, fan rotation control circuitry2408, performance monitoring circuitry2410, and interface communication circuitry2412. In some examples, the temperature analysis circuitry2402is instantiated by processor circuitry executing temperature analysis instructions and/or configured to perform operations such as those represented by the flowchart ofFIG.25. In some examples, the fan location determination circuitry2404is instantiated by processor circuitry executing fan location determination instructions and/or configured to perform operations such as those represented by the flowchart ofFIG.25. In some examples, the actuator control circuitry2406is instantiated by processor circuitry executing actuator control instructions and/or configured to perform operations such as those represented by the flowchart ofFIG.25. In some examples, the fan rotation control circuitry2408is instantiated by processor circuitry executing fan rotation control instructions and/or configured to perform operations such as those represented by the flowchart ofFIG.25. In some examples, the performance monitoring circuitry2410is instantiated by processor circuitry executing performance monitoring instructions and/or configured to perform operations such as those represented by the flowchart ofFIG.25. In some examples, the interface communication circuitry2412is instantiated by processor circuitry executing interface communication instructions and/or configured to perform operations such as those represented by the flowchart ofFIG.25.

In the example ofFIG.24, the fan control circuitry1750accesses peripheral temperature data2414corresponding to signals output by the temperature sensors1752of the PCIe card(s)1700,2220,2300. The temperature data2414can include temperatures of the PCIe card and/or the electronic components thereof at different locations on the card1700,2200,2300based on the locations of the temperature sensors1752. The temperature data2414can be stored in a memory2416. In some examples, the fan control circuitry1750includes the memory2416. In some examples, the memory2416is located external to the fan control circuitry2406in a location accessible to the fan control circuitry1750as shown inFIG.24.

In the example ofFIG.24, the fan control circuitry1750accesses fan operating data2418. The fan operating data2418can include properties of operating parameters of the fans1722,2208,2216,2320,2324,2328, such as a power state, a rotational speed, a rotational direction, and/or a location of the fans1722,2208,2216,2320,2324,2328. The fan operating data2418can correspond to signals output by, for instance, the fan operating parameter sensor(s)1754(e.g., position sensor(s), tachometer(s)). The fan operating data2418can be stored in the memory2416.

The temperature analysis circuitry2402analyzes the peripheral temperature data2414to identify areas of the PCIe card1700,2200,2300including electronic components (e.g., FPGA, processor circuitry) generating increased amounts of heat relative to other electronic components of the card1700,2200,2300. For instance, the temperature analysis circuitry2402can generate temperature gradients for the PCIe card1700,2200,2300and identify areas of increased temperature or hot spots at a given time based on the temperature gradient. In some examples, the temperature analysis circuitry2402compares the temperature data2414to temperature threshold data2420stored in the memory2416. The temperature threshold data2420can include user defined temperature classifications identifying temperatures or ranges of temperatures that are indicative of hot spots.

The fan location determination circuitry2404of the fan control circuitry uses the locations of the hot spots identified by the temperature analysis circuitry2402to determine a location (e.g., an optimal location) of the fan(s)1722,2208,2216,2320,2324,2328(e.g., the fan base(s)1800) relative to the heat sink1714,2204,2304of the PCIe card1700,2200,2300to provide for increased airflow over the area(s) of the heat sink1714,2204,2304that are proximate to the hot spots. For example, the fan location determination circuitry2404can use mapping reference data2422stored in the memory2416to identify a current location of the fan(s)1722,2208,2216,2320,2324,2328relative to the hot spots. The mapping reference data2422can identify the locations of the electronic components on the PCIe card1700,2200,2300. The fan location determination circuitry2404can determine a location to which the fan(s)1722,2208,2216,2320,2324,2328(e.g., the fan base(s)1800) should be moved to locate the fan(s)1722,2208,2216,2320,2324,2328proximate to the portion of the heat sink1714,2204,2304associated with the hot spot(s).

In some examples, the fan location determination circuitry2404determines that the fan(s)1722,2208,2216of the example fan assemblies1720,2206,2214ofFIGS.17-22should be translated if the fan(s)1722,2208,2216have been at a particular location relative to the heat sink1714,2204,2304for a particular duration of time. For example, fan location duration threshold data2424stored in the memory2416can indicate a duration of time for which the fan(s)1722,2208,2216should remain at particular locations relative to the heat sink1714,2204. The fan location duration threshold data2424can be defined based on user inputs and, for instance, expected cooling times for the electronic components of the PCIe card1700,2200based on temperature, fan speed, operational characteristics of the electronic components, etc.

In some examples, if the fan location determination circuitry2404determines that the fan(s)1722,2208,2216should be translated to address hot spots on the PCIe card1700,2200, the actuator control circuitry2406generates fan location instruction(s)2426to cause the actuators1742,2226,2230,2250,2252to translate the fan(s)1722,2208,2216(e.g., the fan shuttle(s)1738,2212,2220) to the location(s) identified by the fan location determination circuitry2404. In some examples, the fan location instruction(s)2426cause the linear actuator1742of the fan tray1720ofFIG.23to move the shuttle1738to a particular location in the IPU1700. In some examples, the fan instruction(s)2426cause a current flowing through the tray magnets2226,2230,2250,2252of the respective fan trays2206,2214ofFIG.22to be adjusted (e.g., reversed) to affect a polarity of the tray magnets2226,2230,2250,2252. As disclosed in connection withFIG.22, the polarity of the tray magnets2226,2230,2250,2252can cause the shuttle2212,2220ofFIG.22to move along the track2222,2224as a result of pushing or pulling forces due to attraction or repelling between the tray magnets2226,2230,2250,2252and the corresponding shuttle magnets2238,2242,2254,2256.

The fan rotation control circuitry2408monitors a speed of the blades1740of the fan(s)1722,2208,2216,2320,2324,2328of the fan assemblies1720,2206,2214,2318,2322,2326ofFIGS.17-23based on the fan operating data2418. In some examples, the fan rotation control circuitry2408generates fan speed instruction(s)2428to cause a rotational speed (e.g., RPMs) of the blades1740of the fan(s)1722,2208,2216,2320,2324,2328to be adjusted based on the temperature(s) of the hot spot(s) identified by the temperature analysis circuitry2402.

In some examples, the fan rotation control circuitry2408determines a direction in which the blades1740of the fan(s)1722,2208,2216,2320,2324,2328should rotate to affect a direction of airflow through the PCIe card1700,2200,2300. In some examples, the fan rotation control circuitry2408determines the direction of airflow through the PCIe card1700,2200,2300based on the temperature gradient generated by the temperature analysis circuitry2402, where cooler temperatures can indicate that air from the ambient environment is entering the PCIe card1700,2200,2300proximate to the temperature sensors1752detecting the cooler temperatures. The fan rotation control circuitry2408can generate fan rotation direction instruction(s)2430to cause the blades1740of the fan(s)1722,2208,2216,2320,2324,2328to rotate in a particular direction to facilitate air flow through the PCIe card1700,2200,2300. In some examples, the fan rotation control circuitry2408instructs the blades1740of a first fan1722,2208,2216,2320,2324,2328to rotate in a first direction and the blades1740of a second fan1722,2208,2216,2320,2324,2328to rotate in a second direction to pull cool air into the card1700,2200,2300and push hot air out.

The performance monitoring circuitry2410monitors the fan(s)1722,2208,2216,2320,2324,2328to detect potential failure states of the fan(s)1722,2208,2216,2320,2324,2328or other indicators that the fan(s)1722,2208,2216,2320,2324,2328may need to be repaired or replaced. The performance monitoring circuitry2410compares the rotational blade speed of the fan(s)1722,2208,2216,2320,2324,2328to fan speed threshold data2432stored in the memory2416. The fan speed threshold data2432can define minimum rotational speeds and/or ranges of speeds for which the blades1740of the fan(s)1722,2208,2216,2320,2324,2328should be rotating. The performance monitoring circuitry2410and/or the temperature analysis circuitry2402can also analyze the temperature data2414in response to the change in fan performance to confirm that the change is due to, for instance, decreased workloads at the PCIe card1700,2200,2300that cause less heat to be generated by the PCIe card components, and not because of a failed fan1722,2208,2216,2320,2324,2328that should otherwise be satisfying performance thresholds for cooling. For instance, if the performance monitoring circuitry2410determines that the temperature of the components of the PCIe card1700,2200,2300proximate to the location(s) of the fan(s)1722,2208,2216,2320,2324,2328are increasing in response to the change in fan performance, the performance monitoring circuitry2410can determine that the fan(s)1722,2208,2216,2320,2324,2328may have failed or are failing. If the performance monitoring circuitry2408determines that the fan(s)1722,2208,2216,2320,2324,2328do not satisfy the fan speed threshold data2432and that temperature of the PCIe card1700,2200,2300is increasing when cooling is expected, the performance monitoring circuitry2410generates alert output instruction(s)2434to cause alert(s) to be presented to inform a user (e.g., a data center operator) of the failed state or potential failed state of the fan(s). For instance, the alert output instruction(s)2434can cause an LED on a tray1720,2206,2214,2318,2322,2326to be activated to provide a visual alert.

In some examples, if the performance monitoring circuitry2410detects a failed fan state, the performance monitoring circuitry2410communicates with, for instance, the fan location determination circuitry2404and/or the fan rotation control circuitry2408to determine if adjustments should be made to compensate for the failed fan state. For instance, the fan location determination circuitry2404can determine that the fan1722ofFIG.17(e.g., the fan base1800) should be moved an end of the tray1720to prevent the failed fan1722from interfering with airflow into the PCIe card1700. In some examples, the fan rotation control circuitry2408generates fan speed instruction(s)2428to cause a rotational speed (e.g., RPMs) of the blades1740of the fan(s)1722,2208,2216,2320,2324,2328to be adjusted if one or more of the fans1722,2208,2216,2320,2324,2328have been removed from the PCIe card2200,2300for maintenance.

The interface communication circuitry2412outputs the fan location instruction(s)2426, the fan speed instruction(s)2428, the fan rotation direction instruction(s)2430, and/or the alert output instruction(s)2434to cause the instructions to be implemented by, for instance, the fan(s)1722,2208,2216,2320,2324,2328, the actuator(s)1742,2226,2230,2250,2252, etc. of the example fan assemblies ofFIGS.17-23.

In some examples, the fan control circuitry1750includes means for analyzing temperature. For example, the means for analyzing temperature may be implemented by the temperature analysis circuitry2402. In some examples, the temperature analysis circuitry2402may be instantiated by processor circuitry such as the example processor circuitry2612ofFIG.26. For instance, the temperature analysis circuitry2402may be instantiated by the example microprocessor2700ofFIG.27executing machine executable instructions such as those implemented by at least blocks2504,2506ofFIG.25. In some examples, the temperature analysis circuitry2402may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry2800ofFIG.28structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the temperature analysis circuitry2402may be instantiated by any other combination of hardware, software, and/or firmware. For example, the temperature analysis circuitry2402may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the fan control circuitry1750includes means for determining a fan location. For example, the means for determining a fan location may be implemented by the fan location determination circuitry2404. In some examples, the fan location determination circuitry2404may be instantiated by processor circuitry such as the example processor circuitry2612ofFIG.26. For instance, the fan location determination circuitry2404may be instantiated by the example microprocessor2700ofFIG.27executing machine executable instructions such as those implemented by at least blocks2508,2510,2522,2524ofFIG.25. In some examples, the fan location determination circuitry2404may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry2800ofFIG.28structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the fan location determination circuitry2404may be instantiated by any other combination of hardware, software, and/or firmware. For example, the fan location determination circuitry2404may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the fan control circuitry1750includes means for controlling an actuator. For example, the means for controlling an actuator may be implemented by the actuator control circuitry2406. In some examples, the actuator control circuitry2406may be instantiated by processor circuitry such as the example processor circuitry2612ofFIG.26. For instance, the actuator control circuitry2406may be instantiated by the example microprocessor2700ofFIG.27executing machine executable instructions such as those implemented by at least blocks2512ofFIG.25. In some examples, the actuator control circuitry2406may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry2800ofFIG.28structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the actuator control circuitry2406may be instantiated by any other combination of hardware, software, and/or firmware. For example, the actuator control circuitry2406may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the fan control circuitry1750includes means for controlling rotation of a fan. For example, the means for controlling rotation of a fan may be implemented by the fan rotation control circuitry2408. In some examples, the fan rotation control circuitry2408may be instantiated by processor circuitry such as the example processor circuitry2612ofFIG.26. For instance, the fan rotation control circuitry2408may be instantiated by the example microprocessor2700ofFIG.27executing machine executable instructions such as those implemented by at least blocks2514,2516,2522,2524ofFIG.25. In some examples, the fan rotation control circuitry2408may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry2800ofFIG.28structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the fan rotation control circuitry2408may be instantiated by any other combination of hardware, software, and/or firmware. For example, the fan rotation control circuitry2408may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the fan control circuitry1750includes means for monitoring performance. For example, the means for monitoring performance may be implemented by the performance monitoring circuitry2410. In some examples, the performance monitoring circuitry2410may be instantiated by processor circuitry such as the example processor circuitry2612ofFIG.26. For instance, the performance monitoring circuitry2410may be instantiated by the example microprocessor2700ofFIG.27executing machine executable instructions such as those implemented by at least blocks2518,2520ofFIG.25. In some examples, the performance monitoring circuitry2410may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry2800ofFIG.28structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the performance monitoring circuitry2410may be instantiated by any other combination of hardware, software, and/or firmware. For example, the performance monitoring circuitry2410may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the fan control circuitry1750includes means for interfacing. For example, the means for interfacing may be implemented by the interface communication circuitry2412. In some examples, the interface communication circuitry2412may be instantiated by processor circuitry such as the example processor circuitry2602ofFIG.26. For instance, the interface communication circuitry2412may be instantiated by the example microprocessor2700ofFIG.27executing machine executable instructions such as those implemented by at least blocks2518,2520ofFIG.25. In some examples, the interface communication circuitry2412may be instantiated by hardware logic circuitry, which may be implemented by an ASIC, XPU, or the FPGA circuitry2800ofFIG.28structured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the interface communication circuitry2412may be instantiated by any other combination of hardware, software, and/or firmware. For example, the interface communication circuitry2412may be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an ASIC, an XPU, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

While an example manner of implementing the fan control circuitry1750ofFIGS.17,22, and/or23is illustrated inFIG.24, one or more of the elements, processes, and/or devices illustrated inFIG.24may be combined, divided, re-arranged, omitted, eliminated, and/or implemented in any other way. Further, the example temperature analysis circuitry2402, the example fan location determination circuitry2404, the example actuator control circuitry2406, the example fan rotation control circuitry2408, the example performance monitoring circuitry2410, the example interface communication circuitry2412, and/or, more generally, the example fan control circuitry1750ofFIG.24, may be implemented by hardware alone or by hardware in combination with software and/or firmware. Thus, for example, any of the example temperature analysis circuitry2402, the example fan location determination circuitry2404, the example actuator control circuitry2406, the example fan rotation control circuitry2408, the example performance monitoring circuitry2410, the example interface communication circuitry2412, and/or, more generally, the example fan control circuitry1750, could be implemented by processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), and/or field programmable logic device(s) (FPLD(s)) such as Field Programmable Gate Arrays (FPGAs). Further still, the example fan control circuitry1750ofFIGS.17,22, and/or23may include one or more elements, processes, and/or devices in addition to, or instead of, those illustrated inFIG.24, and/or may include more than one of any or all of the illustrated elements, processes, and devices.

FIG.25is a flowchart representative of example machine readable instructions and/or example operations2500that may be executed and/or instantiated by processor circuitry to control one or more parameter(s) (e.g., location, rotational speed, rotational direction) of the fan(s)1722,2208,2216,2320,2324,2328of a peripheral1700,2200,2300(e.g., a PCIe card). The machine readable instructions and/or the operations2500ofFIG.25begin at block2502, at which the interface communication circuitry2412of the fan control circuitry1750accesses peripheral temperature data2414and fan operating data2418from, for instance, the temperature sensors1752and the fan operating parameter sensor(s)1754of the peripheral1700,2200,2300.

At block2504, the temperature analysis circuitry2402analyzes the temperature data2414to identify areas of the peripheral1700,2200,2300that are associated with increased temperature relative to other areas of the peripheral1700,2200,2300, thereby indicating that increased amount of heat is being generated by the electronic components of the peripheral1700,2200,2300at those areas. If, at block2506, the temperature analysis circuitry2402identifies areas of increased temperature (i.e., hot spots) at the peripheral1700,2200,2300, then the fan control circuitry1750generates instructions to provide for increased airflow over the heat sink1714,2204,2304at portions of the heat sink1714,2204,2304corresponding to the areas of increased temperature.

If the fan assembly1720,2206,2214includes location-adjustable fans1722,2208,2216as disclosed in connection withFIGS.17-22(block2508), then at block2510, the fan location determination circuitry2404determines a location to which the fan(s)1722,2208,2216(e.g., the fan base(s)1800) should be moved based on the locations of the hot spots. At block2512, the actuator control circuitry2406generates fan location instruction(s)2426for transmission by the interface communication circuitry2412to cause the actuator(s)1742,2226,2230,2250,2252, to translate or move the fan(s)1722,2208,2216(e.g., the fan base(s)1800) via, for instance, the fan shuttles1738,2212,2220to the identified locations. In some examples, the fan location instruction(s)2426cause the linear actuator1742to move the shuttle1738including the fan1722supported by the base1800as disclosed in connection withFIG.17. In some examples, the fan location instruction(s)2426cause a polarity of the tray magnets2226,2230,2250,2252to be adjusted (e.g., reversed, turned on) to cause the shuttle2212,2220to be pushed and/or pulled along the track2222,2224to particular locations relative to the heat sink2204as disclosed in connection withFIG.22.

At block2518, the performance monitoring circuitry2410detects if changes in fan performance such as rotational blade speed (e.g., reduced RPMs or no rotation). In some examples, the rotational parameters of the fan(s)1722,2208,2216,2320,2324,2328may change (e.g., reduce RPMs, stop rotation) in view of, for instance, decreased workloads by the component(s) of the peripheral1700,2200,2300and, thus, less heat generated over time, acoustic considerations, etc. Thus, to verify whether the change in fan performance is indicative of a failed state of the fan(s)1722,2208,2216,2320,2324,2328or a potential failed state (e.g., rotational speed below a threshold), at block2519, the performance monitoring circuitry2410determines whether the temperature of the peripheral1700,2200,2300is increasing proximate to the location(s) of the fan(s)1722,2208,2216,2320,2324,2328(e.g., based on the temperature data2414). The increase in temperature proximate to the fan location can indicate that the fan1722,2208,2216,2320,2324,2328is failing to operate as expected to cool the component(s). If the performance monitoring circuitry2410detects the change in fan performance as well as an increase in temperature of the peripheral100,2200,2300proximate to at the location(s) of the fan(s)1722,2208,2216,2320,2324,2328, at block2520, the performance monitoring circuitry2410generates alert output instruction(s)2434for transmission by the interface communication circuitry2410to cause alert(s) to be output to inform a user of the failed fan state (e.g., activation of an LED at the fan tray1720,2206,2214,2318,2322,2326).

In some examples, at block2522, the fan location determination circuitry2404and/or the fan rotation control circuitry2408adjust the location(s) and/or rotational parameters of the fan(s)1722,2208,2216,2320,2324,2328to compensate for the failed fan1722,2208,2216,2320,2324,2328(e.g., to cause the failed fan1722,2208,2216,2320,2324,2328to move to prevent interference with airflow, to cause a rotational speed of the other fan(s)1722,2208,2216,2320,2324,2328to increase). In some examples, the actuator control circuitry2406generates instructions to enable the tray1720,2206,2214,2318,2322,2326including the failed fan1722,2208,2216,2320,2324,2328to be removed from the peripheral1700,2200,2300(e.g., by reversing polarity of the magnets2226,2230,2250,2252,2306,2308,2310to uncouple fan assembly1720,2206,2214,2318,2322,2326from the PCIe card1700,2200,2300).

In some examples, at block2524, the fan location determination circuitry2404and/or the fan rotation control circuitry2408detects a replaced fan based on, for instance, the fan operating data2418.

The example instructions2500continue to monitor the fan operating data2418and/or the temperature data2414to determine if the parameter(s) (e.g., location, rotational speed, rotational direction) of the fan(s)1722,2208,2216,2320,2324,2328should be adjusted. The example instructions2500end when the peripheral1700,2200,2300is powered off (blocks2526,2528).

FIG.26is a block diagram of an example processor platform2600structured to execute and/or instantiate the machine readable instructions and/or the operations ofFIG.25to implement the fan control circuitry1750ofFIG.24. The processor platform2600can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad™), a personal digital assistant (PDA), an Internet appliance, or any other type of computing device.

The processor platform2600of the illustrated example includes processor circuitry2612. The processor circuitry2612of the illustrated example is hardware. For example, the processor circuitry2612can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The processor circuitry2612may be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the processor circuitry2612implements the example temperature analysis circuitry2402, the example fan location determination circuitry2404, the example actuator control circuitry2406, the example fan rotation control circuitry2408, the example performance monitoring circuitry2410, the example interface communication circuitry2412, and/or, more generally, the example fan control circuitry1750.

The processor circuitry2612of the illustrated example includes a local memory2613(e.g., a cache, registers, etc.). The processor circuitry2612of the illustrated example is in communication with a main memory including a volatile memory2614and a non-volatile memory2616by a bus2618. The volatile memory2614may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The non-volatile memory2616may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory2614,2616of the illustrated example is controlled by a memory controller2617.

The processor platform2600of the illustrated example also includes interface circuitry2620. The interface circuitry2620may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and/or a Peripheral Component Interconnect Express (PCIe) interface.

In the illustrated example, one or more input devices2622are connected to the interface circuitry2620. The input device(s)422permit(s) a user to enter data and/or commands into the processor circuitry2612. The input device(s)2622can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, an isopoint device, and/or a voice recognition system.

The processor platform2600of the illustrated example also includes one or more mass storage devices2628to store software and/or data. Examples of such mass storage devices2628include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid state storage devices such as flash memory devices and/or SSDs, and DVD drives.

The machine readable instructions2632, which may be implemented by the machine readable instructions ofFIG.25, may be stored in the mass storage device2628, in the volatile memory2614, in the non-volatile memory2616, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.

FIG.27is a block diagram of an example implementation of the processor circuitry2612ofFIG.26. In this example, the processor circuitry2612ofFIG.26is implemented by a microprocessor2700. For example, the microprocessor2700may be a general purpose microprocessor (e.g., general purpose microprocessor circuitry). The microprocessor2700executes some or all of the machine readable instructions of the flowchart ofFIG.25to effectively instantiate the circuitry ofFIG.24as logic circuits to perform the operations corresponding to those machine readable instructions. In some such examples, the circuitry ofFIG.24is instantiated by the hardware circuits of the microprocessor2700in combination with the instructions. For example, the microprocessor2700may be implemented by multi-core hardware circuitry such as a CPU, a DSP, a GPU, an XPU, etc. Although it may include any number of example cores2702(e.g.,1core), the microprocessor2700of this example is a multi-core semiconductor device including N cores. The cores2702of the microprocessor2700may operate independently or may cooperate to execute machine readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores2702or may be executed by multiple ones of the cores2702at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more of the cores2702. The software program may correspond to a portion or all of the machine readable instructions and/or operations represented by the flowchart ofFIG.25.

The cores2702may communicate by a first example bus2704. In some examples, the first bus2704may be implemented by a communication bus to effectuate communication associated with one(s) of the cores2702. For example, the first bus2704may be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus2704may be implemented by any other type of computing or electrical bus. The cores2702may obtain data, instructions, and/or signals from one or more external devices by example interface circuitry2706. The cores2702may output data, instructions, and/or signals to the one or more external devices by the interface circuitry2706. Although the cores2702of this example include example local memory2720(e.g., Level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor2700also includes example shared memory2710that may be shared by the cores (e.g., Level 2 (L2 cache)) for high-speed access to data and/or instructions. Data and/or instructions may be transferred (e.g., shared) by writing to and/or reading from the shared memory2710. The local memory2720of each of the cores2702and the shared memory2710may be part of a hierarchy of storage devices including multiple levels of cache memory and the main memory (e.g., the main memory2614,2616ofFIG.26). Typically, higher levels of memory in the hierarchy exhibit lower access time and have smaller storage capacity than lower levels of memory. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.

Each core2702may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each core2702includes control unit circuitry2714, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU)2716, a plurality of registers2718, the local memory2720, and a second example bus2722. Other structures may be present. For example, each core2702may include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitry2714includes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core2702. The AL circuitry2716includes semiconductor-based circuits structured to perform one or more mathematic and/or logic operations on the data within the corresponding core2702. The AL circuitry2716of some examples performs integer based operations. In other examples, the AL circuitry2716also performs floating point operations. In yet other examples, the AL circuitry2716may include first AL circuitry that performs integer based operations and second AL circuitry that performs floating point operations. In some examples, the AL circuitry2716may be referred to as an Arithmetic Logic Unit (ALU). The registers2718are semiconductor-based structures to store data and/or instructions such as results of one or more of the operations performed by the AL circuitry2716of the corresponding core2702. For example, the registers2718may include vector register(s), SIMD register(s), general purpose register(s), flag register(s), segment register(s), machine specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. The registers2718may be arranged in a bank as shown inFIG.27. Alternatively, the registers2718may be organized in any other arrangement, format, or structure including distributed throughout the core2702to shorten access time. The second bus2722may be implemented by at least one of an I2C bus, a SPI bus, a PCI bus, or a PCIe bus

FIG.28is a block diagram of another example implementation of the processor circuitry2612ofFIG.26. In this example, the processor circuitry2612is implemented by FPGA circuitry2800. For example, the FPGA circuitry2800may be implemented by an FPGA. The FPGA circuitry2800can be used, for example, to perform operations that could otherwise be performed by the example microprocessor2700ofFIG.27executing corresponding machine readable instructions. However, once configured, the FPGA circuitry2800instantiates the machine readable instructions in hardware and, thus, can often execute the operations faster than they could be performed by a general purpose microprocessor executing the corresponding software.

In the example ofFIG.28, the FPGA circuitry2800is structured to be programmed (and/or reprogrammed one or more times) by an end user by a hardware description language (HDL) such as Verilog. The FPGA circuitry2800ofFIG.28, includes example input/output (I/O) circuitry2802to obtain and/or output data to/from example configuration circuitry2804and/or external hardware2806. For example, the configuration circuitry2804may be implemented by interface circuitry that may obtain machine readable instructions to configure the FPGA circuitry2800, or portion(s) thereof. In some such examples, the configuration circuitry2804may obtain the machine readable instructions from a user, a machine (e.g., hardware circuitry (e.g., programmed or dedicated circuitry) that may implement an Artificial Intelligence/Machine Learning (AI/ML) model to generate the instructions), etc. In some examples, the external hardware2806may be implemented by external hardware circuitry. For example, the external hardware2806may be implemented by the microprocessor2700ofFIG.27. The FPGA circuitry2800also includes an array of example logic gate circuitry2808, a plurality of example configurable interconnections2810, and example storage circuitry2812. The logic gate circuitry2808and the configurable interconnections2810are configurable to instantiate one or more operations that may correspond to at least some of the machine readable instructions ofFIG.25and/or other desired operations. The logic gate circuitry2808shown inFIG.28is fabricated in groups or blocks. Each block includes semiconductor-based electrical structures that may be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., And gates, Or gates, Nor gates, etc.) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate circuitry2808to enable configuration of the electrical structures and/or the logic gates to form circuits to perform desired operations. The logic gate circuitry2808may include other electrical structures such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

The storage circuitry2812of the illustrated example is structured to store result(s) of the one or more of the operations performed by corresponding logic gates. The storage circuitry2812may be implemented by registers or the like. In the illustrated example, the storage circuitry2812is distributed amongst the logic gate circuitry2808to facilitate access and increase execution speed.

The example FPGA circuitry2800ofFIG.28also includes example Dedicated Operations Circuitry2814. In this example, the Dedicated Operations Circuitry2814includes special purpose circuitry2816that may be invoked to implement commonly used functions to avoid the need to program those functions in the field. Examples of such special purpose circuitry2816include memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special purpose circuitry may be present. In some examples, the FPGA circuitry2800may also include example general purpose programmable circuitry2818such as an example CPU2820and/or an example DSP2822. Other general purpose programmable circuitry2818may additionally or alternatively be present such as a GPU, an XPU, etc., that can be programmed to perform other operations.

AlthoughFIGS.27and28illustrate two example implementations of the processor circuitry2612ofFIG.26, many other approaches are contemplated. For example, as mentioned above, modern FPGA circuitry may include an on-board CPU, such as one or more of the example CPU2820ofFIG.28. Therefore, the processor circuitry2612ofFIG.26may additionally be implemented by combining the example microprocessor2700ofFIG.27and the example FPGA circuitry2800ofFIG.28. In some such hybrid examples, a first portion of the machine readable instructions represented by the flowchart ofFIG.25may be executed by one or more of the cores2702ofFIG.27, a second portion of the machine readable instructions represented by the flowchart ofFIG.25may be executed by the FPGA circuitry2800ofFIG.28, and/or a third portion of the machine readable instructions represented by the flowchart ofFIG.25may be executed by an ASIC. It should be understood that some or all of the circuitry ofFIG.24may, thus, be instantiated at the same or different times. Some or all of the circuitry may be instantiated, for example, in one or more threads executing concurrently and/or in series. Moreover, in some examples, some or all of the circuitry ofFIG.24may be implemented within one or more virtual machines and/or containers executing on the microprocessor.

In some examples, the processor circuitry2612ofFIG.26may be in one or more packages. For example, the microprocessor2700ofFIG.27and/or the FPGA circuitry2800ofFIG.28may be in one or more packages. In some examples, an XPU may be implemented by the processor circuitry2612ofFIG.26, which may be in one or more packages. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in yet another package, and an FPGA in still yet another package.

A block diagram illustrating an example software distribution platform2905to distribute software such as the example machine readable instructions2632ofFIG.26to hardware devices owned and/or operated by third parties is illustrated inFIG.29. The example software distribution platform2905may be implemented by any computer server, data facility, cloud service, etc., capable of storing and transmitting software to other computing devices. The third parties may be customers of the entity owning and/or operating the software distribution platform2905. For example, the entity that owns and/or operates the software distribution platform2905may be a developer, a seller, and/or a licensor of software such as the example machine readable instructions2632ofFIG.26. The third parties may be consumers, users, retailers, OEMs, etc., who purchase and/or license the software for use and/or re-sale and/or sub-licensing. In the illustrated example, the software distribution platform2905includes one or more servers and one or more storage devices. The storage devices store the machine readable instructions2632, which may correspond to the example machine readable instructions2500ofFIG.25, as described above. The one or more servers of the example software distribution platform2905are in communication with an example network2910, which may correspond to any one or more of the Internet and/or any of the example networks2626described above. In some examples, the one or more servers are responsive to requests to transmit the software to a requesting party as part of a commercial transaction. Payment for the delivery, sale, and/or license of the software may be handled by the one or more servers of the software distribution platform and/or by a third party payment entity. The servers enable purchasers and/or licensors to download the machine readable instructions2632from the software distribution platform2905. For example, the software, which may correspond to the example machine readable instructions2500ofFIG.25, may be downloaded to the example processor platform400, which is to execute the machine readable instructions2632to implement the fan control circuitry1750. In some examples, one or more servers of the software distribution platform2905periodically offer, transmit, and/or force updates to the software (e.g., the example machine readable instructions2632ofFIG.26) to ensure improvements, patches, updates, etc., are distributed and applied to the software at the end user devices.

From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed that provide for field replaceable fan(s) to augment cooling at a peripheral (e.g., a peripheral processing unit such as a PCIe card) while enabling the fan(s) to be removed from the peripheral compute device (e.g., for maintenance) without disrupting or substantially interrupting operation of the device. Some example fan assemblies disclosed herein include fan(s) that can be moved relative to a heat sink (e.g., a heat sink on which the fan assembly is disposed). Example disclosed herein dynamically adjust the location(s) of (e.g., move) the fan(s) based on the identification of hot spots, or areas of increased temperature in the peripheral due to performance of the electronic components. Some examples disclosed herein dynamically adjust and/or monitor rotational parameters of the fan(s), such as fan speed, to optimize fan performance and, thus, performance of the electronic components through cooling.

Example field replaceable fan assemblies for peripheral processing units and related systems and methods are disclosed herein. Further examples and combinations thereof include the following:

Example 1 includes an apparatus comprising a temperature sensor; a heat sink; a fan having a base; at least one memory; machine readable instructions; and processor circuitry to execute operations corresponding to the machine readable instructions to determine a first temperature based on an output of the temperature sensor; and cause the base of the fan to move relative to the heat sink based on the first temperature

Example 2 includes the apparatus of example 1, further including a heat sink, the base of the fan moveable relative to the heat sink.

Example 3 includes the apparatus of examples 1 or 2, wherein the temperature sensor is in communication with the heat sink.

Example 4 includes the apparatus of any of examples 1-3, further including a tray to support the fan, the tray including a first frame; and a second frame, the second frame to carry the first frame, the first frame moveable relative to the second frame.

Example 5 includes the apparatus of any of examples 1-4, further including an actuator, the processor circuitry to cause the actuator to move the first frame.

Example 6 includes the apparatus of any of examples 1-5, wherein the first frame includes a first magnet and the second frame includes a second magnet, the second magnet to couple with the first magnet when the base of the fan is at a first location relative to the heat sink.

Example 7 includes the apparatus of any of examples 1-6, wherein the processor circuitry is to cause a polarity of the first magnet to be adjusted to cause the second frame to move.

Example 8 includes the apparatus of any of examples 1-7, wherein the fan is a first fan and further including a second fan, the second fan having a base that is moveable relative to the first fan.

Example 9 includes the apparatus of any of examples 1-8, wherein the processor circuitry is to cause blades of the first fan to rotate in a first direction and blades of a second fan to rotate in a second direction, the first direction opposite the second direction.

Example 10 includes the apparatus of any of examples 1-9, wherein the processor circuitry is to determine a rotational speed of the fan blades; and cause an alert to be output based on the rotational speed.

Example 11 includes an electronic peripheral comprising a housing; a heat sink to dissipate heat generated by the peripheral; a frame proximate the heat sink; and a fan supported by the frame, the housing to cover the heat sink and the frame, the frame from the housing via translation.

Example 12 includes the electronic peripheral of example 11, wherein the fan is translatable relative to the heat sink.

Example 13 includes the electronic peripheral of examples 11 or 12, further including a track supported by the frame, the fan to translate via the track.

Example 14 includes the electronic peripheral of any of examples 11-13, wherein the frame is a first frame and further including a second frame, the second frame to move relative to the first frame.

Example 15 includes the electronic peripheral of any of examples 11-14, further including a socket carried by the frame, the socket to couple to a power source to provide power to the fan.

Example 16 includes the electronic peripheral of any of examples 11-15, wherein the frame is a first frame, the fan is a first fan, and further including a second frame and a second fan, the second fan supported by the second frame.

Example 17 includes the electronic peripheral of any of examples 11-16, wherein the first fan is translatable relative to the first frame and the second fan is translatable relative to the second frame.

Example 18 includes the peripheral processing unit of any of examples 11-17, further including a first magnet and a second magnet, the second magnet carried by the frame, the first magnet to couple with the second magnet.

Example 19 includes a non-transitory machine readable storage medium comprising instructions to cause processor circuitry to at least detect a first temperature associated with a first portion of peripheral card; detect a second temperature associated with a second portion of the peripheral card; perform a comparison of the first temperature and the second temperature; and cause a fan to move from a first location to a second location of the peripheral card based on the comparison.

Example 20 includes the non-transitory machine readable storage medium of example 19, wherein the instructions cause the processor circuitry to cause a linear actuator to move the fan from the first location to the second location.

Example 21 includes the non-transitory machine readable storage medium of examples 19 or 20, wherein the instructions cause the processor circuitry to cause an electromagnet to activate to move the fan.

Example 22 includes the non-transitory machine readable storage medium of any of examples 19-21, wherein the instructions cause the processor circuitry to cause a rotational speed of blades of the fan to be adjusted based on the comparison.

Example 23 includes the non-transitory machine readable storage medium of any of examples 19-22, wherein the fan is a first fan, the peripheral card includes a second fan, and the instructions cause the processor circuitry to cause the blades the first fan to rotate in a first direction and blades of the second fan to rotate in a second direction, the first direction opposite the second direction.

Example 24 includes the non-transitory machine readable storage medium of any of examples 19-23, wherein the instructions cause the processor circuitry to compare a value representative of a rotational speed of blades of the fan to a threshold; and cause an alert to be output based on the comparison.

Example 25 includes the non-transitory machine readable storage medium of any of examples 19-24, wherein the instructions cause the processor circuitry to determine a temperature gradient for the peripheral card; and select a rotational directional for blades of the fan based on the temperature gradient.

Example 26 includes the apparatus of example 19, wherein the peripheral card is a peripheral component interconnect express (PCIe) card.

Example 27 includes an apparatus comprising means for detecting a temperature associated with a peripheral; means for circulating air; and means for controlling an actuator, the actuator controlling means to cause the air circulating means to translate based on the temperature.

Example 28 includes the apparatus of example 27, further including means for performance monitoring to detect a failure state of the air circulating means.

Example 29 includes the apparatus of examples 27 or 28, further including means for transporting, the actuator controlling means to cause the transporting means to move the air circulating means.

Example 30 includes the apparatus of any of examples 27-29, wherein the air circulating means is separately removable from the peripheral.

Example 31 includes an apparatus comprising interface circuitry to access temperature data for a peripheral; and processor circuitry including one or more of at least one of a central processor unit, a graphics processor unit, or a digital signal processor, the at least one of the central processor unit, the graphics processor unit, or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus; a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and the plurality of the configurable interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations; or Application Specific Integrated Circuitry (ASIC) including logic gate circuitry to perform one or more third operations; the processor circuitry to perform at least one of the first operations, the second operations, or the third operations to instantiate temperature analysis circuitry to identify a hot spot at the peripheral; fan location determination circuitry to determine a location to which a fan of the peripheral should move relative to a heat sink to cool the hot spot; and actuator control circuitry to cause a base of the fan to move to the location.

Example 32 includes the apparatus of example 31, wherein the peripheral is a peripheral component interconnect express (PCIe) card.