Amplifier with reduced idle power loss using single-ended loops

A method of audio signal processing includes receiving a first audio input signal (first input signal) at an input of a first integrating amplifier of a first single-ended (SE) closed loop channel, and second input signal with a polarity reversed relative to the first input signal at an input of a second integrating amplifier configured of a second SE closed loop channel. During audio signal processing a common-mode (CM) reference voltage level applied to a current source coupled to an input of the first and second integrating amplifiers is dynamically changed including whenever a level of the input signals is below a predetermined low level, reducing the CM reference voltage level for implementing low duty cycle (LDC) PWM operation, and whenever the level is above a level that corresponds to an onset of clipping, increasing the CM reference voltage level for at least reducing the clipping to lower crossover distortion.

FIELD

Disclosed embodiments relate to Class D power amplifiers.

BACKGROUND

A class-D power amplifier is an electronic amplifier in which the amplifying devices (typically MOSFETs to limit power loss) operate as electronic switches, instead of as linear gain devices as in other amplifiers. The signal received to be amplified is a train of constant amplitude pulses, so the active devices in the amplifier rapidly switch back and forth between a fully conductive (ON) and fully non-conductive (OFF) state.

The analog signal to be amplified is converted to a series of pulses (output pulse train) by pulse width modulation (PWM), pulse density modulation or other similar method before being applied to the amplifier. After amplification, the output pulse train can be converted back to an analog signal by passing the output pulse train through a passive low pass filter (LPF). The major advantage of a class-D amplifier is generally that it can be more efficient than analog amplifiers, with less power being dissipated as heat in the active devices.

Two single-ended channels can be used to create 1 bridge-tied load (BTL) output channel, where a BTL is an output configuration for audio amplifiers that implements a form of impedance bridging. The two channels of a stereo amplifier are fed the same monaural audio signal, with one channel's electrical polarity reversed relative to the other. A loudspeaker is connected between the two amplifier outputs, bridging the output terminals. BTL can double the voltage swing at the load as compared with the same amplifier used without bridging.

Ternary or 1 sinusoidal pulse width (SPW) modulation can reduce idle loss by creating a PWM waveform with a modified duty cycle at idle that is <a 50% duty cycle. The modified duty cycle idle condition reduces inductor ripple current. A low duty cycle (LDC) PWM generally referred to as LDC idle PWM is known to reduce power loss in class-D amplifiers. However, known methods for implementing LDC idle PWM require fully differential loop architectures in closed-loop class D audio amplifiers that need relatively large chip areas because known single-ended configurations result in the audio performance (such as crossover distortion) generally being unacceptable for most user' applications.

SUMMARY

This Summary briefly indicates the nature and substance of this Disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Disclosed embodiments recognize true single-ended (SE) loop architectures for class-D power amplifiers are more area efficient for systems that support 4×(4 channel) SE, 2.1 and 2.0 bridge-tied load (BTL) configurations. In these highly configurable device configurations, BTL channels are created by combining SE loops. However, it is recognized that the SE loops cannot suppress the crossover distortion resulting from use of modulations including ternary modulation, and the resulting audio performance due to crossover distortion is generally not acceptable. A way of achieving a low idle loss PWM that is compatible with SE loops is needed which provides good audio performance including low crossover distortion, which is provided by disclosed power amplifiers.

Disclosed power amplifiers include at least two channels together with a common-mode (CM) control block for dynamically changing a CM reference voltage level applied to a current source that is coupled to one of the inputs of the integrating amplifiers of the respective channels. The reference voltage level controls the amount of current pulled from the input of the integrating amplifier it is coupled to, which functions to effect the output level of the power amplifier.

Whenever a level of the input signal is below a predetermined low level, the CM level applied to the current source coupled to an input (inverting or non-inverting) of the integrating amplifiers is reduced which implements low duty cycle (LDC) PWM operation, and whenever the level is above a level that corresponds to an onset of clipping, the CM level is increased to the current source prior to clipping for at least reducing (and generally avoiding) clipping to lower crossover distortion. A CM control block implements disclosed dynamic CM reference voltage level adjusting. Disclosed power amplifiers thus provide the benefits of LDC PWM without the complexity of a fully differential loop structure.

DETAILED DESCRIPTION

Also, the terms “coupled to” or “couples with” (and the like) as used herein without further qualification are intended to describe either an indirect or direct electrical connection. Thus, if a first device “couples” to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal but may adjust its current level, voltage level, and/or power level.

As noted above, known methods for implementing LDC idle PWM for reducing idle power loss require fully differential loop architectures in closed-loop class D audio amplifiers or the audio performance including crossover distortion is generally unacceptable. Disclosed power amplifiers having disclosed dynamic CM reference voltage level adjusting implement LDC PWM with SE closed loop architectures. SE loop architectures reduce the die area for highly configurable class D amplifier designs. Disclosed power amplifiers thus address the need for reduced idle power loss with SE closed-loop analog channels, where two SE channels are used to create a differential pair.

FIG. 1shows example top level circuit architecture for a disclosed power amplifier100that has dynamic CM reference voltage level adjusting for implementing reduced idle power loss PWM using SE loop structures, according to an example embodiment. Power amplifier100is shown as a chip formed on a substrate105having a semiconductor surface, such as comprising silicon. Power amplifier100includes a first SE closed loop channel110for receiving a first audio input signal (first input signal)111shown at an inverting input112aof at least a first amplifier112. Although generally shown herein coupled to inverting inputs of the amplifiers, input signals for disclosed embodiments can alternatively be received at the non-inverting inputs of the amplifiers.

The first amplifier112is configured as an integrating amplifier having an integrating feedback capacitor shown as Cint which is coupled in sequence to a first comparator113, a first pulse width modulation (PWM) logic and pulse inject block114a, a gate driver and Isense block (gate driver block)114band a first output stage115. Gate driver block114bis shown receiving a boost voltage shown as BST A as an input. The first output stage115and other output stages are shown comprising series connected power NMOS devices. However, other output stages may be used, such as comprising PMOS devices, or other power devices such as insulated-gate bipolar transistors (IGBTs).

A first signal output115aof the first output stage is fed back across a feedback resistor shown as Rfb to the inverting input112aof the first amplifier112. The PWM logic and pulse inject block114afunctions as the pre-clipping indicator for power amplifier100.

A second SE closed loop channel120is for receiving a second audio input signal (second input signal)121with a polarity reversed relative to the first input signal at an inverting input122aof at least a second amplifier122. The second amplifier122is also configured as an integrating amplifier having an integrating feedback capacitor shown as Cint which is coupled in sequence with a second comparator123, a second PWM logic and pulse inject block124aand gate driver block124band a second output stage125, wherein a second signal output125aof the second output stage is fed back to the input122aof the second amplifier122. Gate driver block124bis shown receiving a boost voltage shown as BST B as an input.

A CM control (CMC) block130(seeFIG. 2described below for an example CMC block130embodiment) has an input coupled to receive an output from the first PWM logic and pulse inject block114aand from the second PWM logic and pulse inject block124a. CMC block130dynamically controls the CM reference voltage level for changing an amount of level shifting current provided by the first current sources118and second current source128which are coupled to, and thus pull current from the inverting inputs112aand122aof the integrating amplifiers112and122to control the output level of the amplifiers.

AVDDis the positive power supply voltage for the analog channels, and the AVDD/2 level is shown applied to the non-inverting inputs of amplifier112and122which can be generated by a simple resistor divider. The AVDD/2+0.5 V level is shown applied to the inverting inputs of the comparators113and123. The level of AVDD/2 shown can be varied with the voltage level to be convenient for the particular application. For power amplifier100, the output voltage level of the integrating amplifiers112and122relative to the inverting inputs of comparators113and123determines the PWM pulse width, which is controlled by the feedback loop shown.

The difference between the level at the non-inverting and inverting input112aand122aof the integrating amplifiers112and122is what leads to the LDC PWM at the outputs OUTA and OUTB of the power amplifier100. When the level at the non-inverting and inverting inputs112aand122aof the integrating amplifiers112and122are the same, a 50% DC is obtained. Although the CMC block130is shown controlling the reference voltage applied to the current sources118and128coupled to the inverting inputs112aand122aof the integrating amplifiers112and122, the current sources118and128can alternatively be coupled to the non-inverting inputs of the integrating amplifiers112and122. In one embodiment, the voltage difference between the CM reference voltage level after reducing the CM level and after increasing the CM reference voltage level to the nominal level is at least 1 V. However, exact reference voltage levels will generally be changed depending on the power supply used.

When the input signal level of the first and second input signals111,121is low, the CM reference voltage level applied to the current sources118and128associated with the integrating amplifiers112and122is reduced to create an LDC PWM. The CM reference voltage level is increased when the input signal level of first input signal111and second input signal121increases above a higher level that corresponds to an onset of clipping. This CM reference voltage level increase thus occurs prior to clipping and avoids the crossover distortion introduced by known methods as evidenced in the simulation data shown inFIG. 3described below.

A startup and shutdown control (SSC) block140has an input140acoupled to an output130bof the CMC block130, wherein an output140bof the SSC block140is coupled to modulate the amount of level shifting current generated by the current source118connected between the inverting input112aof the first amplifier112and ground and the current source128connected between the inverting input122aof the second amplifier122and ground. Other arrangements can be used for dynamically changing the reference voltage level to control the amount of current pulled from an input of the amplifiers112and122to effectuate changing the output level of the power amplifier.

An input/output (I/O) and protection logic block150is shown coupled to PWM logic and pulse inject blocks114aand124a. I/O and protection logic block150is shown receiving a power supply voltage shown as Vdd. SSC block140is shown receiving a positive power supply shown as PVDD AB which is also used as the positive power supply for the first output stage115and second output stage125which generate the power amplifier outputs OUTA and OUTB, respectively. The CM reference voltage level output by CMC block130scales with PVDD. PVDD_AB is not a supply for the CMC block130, but is instead a reference level. GVDD AB shown is the positive power supply for the FET gate driver circuitry in the gate driver blocks114band124b.

During audio signal processing the CMC block130is configured for dynamically changing a CM reference voltage level which is applied by the SSC block140to the current sources118and128that are shown coupled to inverting inputs112aand122aof the first amplifier112and the second amplifier122. The dynamically changing of the CM reference voltage level includes whenever a level of the first input signal111or second input signal121(which are normally at the same level) is below a predetermined low level, reducing the CM reference voltage level applied to the current sources118and128associated with the first amplifier112and the second amplifier122for implementing LDC PWM operation, and whenever the signal level is above a level that corresponds to an onset of clipping where one side of the BTL pair would clip, increasing the CM reference voltage level to the current sources118and128associated with the first amplifier112and the second amplifier122for at least reducing clipping to lower crossover distortion. Texas Instruments Incorporated (TI) commercially supplies TAS56xx power stages which have a pre-clipping indicator block that detects the onset of clipping.

The CM reference voltage level is increased to accommodate full range operation as necessary. An attack and release circuit within the CMC block130can be used to return to LDC operation after the input signal level is reduced to below the predetermined low level. An attack and release circuit is for rapidly raising the CM reference voltage level in response to the pre-clip indicator detecting missing pulses so that signal clipping can be detected and corrected for before distortion is caused, and for returning the CM reference voltage level slowly to the low level after the input signal level is reduced to below the predetermined low level.

In the TI′ TAS56xx family of power amplifier devices, a pre-clipping indicator is designed to be used for supply level adjust to implement Class-G power supply control. The PWM logic and pulse inject blocks114aand124afunction as the clip detector/indicator which monitors the output of the comparators113,123in the respective SE closed loop channels110and120. As the comparator's PWM output reaches full modulation, the clip indicator is activated. The clip detector can look for missing pulses. However, one can set the minimum pulse width that can be detected as a clip indicator. As a result, signal clipping can be detected and corrected for before distortion is caused.

The clip detector itself is a known circuit and can be implemented using other approaches. For example, with traditional analog input class D amplifiers that use a triangular carrier wave to generate PWM, one can compare the output of the integrating amplifier to the ramp height to ensure clipping is not entered. In the TI′ TAS56xx family of devices sold commercially, with TI being the assignee of this application, there is a pre-clipping detector designed to be used for Class-G power supply control. The clip indicator monitors the output of the PWM comparator in the channels. As the comparator PWM output reaches full modulation, the clip indicator is activated.

FIG. 2shows an example CM control circuit130′ configured as a control loop is coupled to the first SE closed loop channel110shown inFIG. 1, according to an example embodiment. CM control circuit130′ is shown including a clip latch and timer block131having an input coupled to receive a/CLIP output from the PWM logic and pulse inject block114ashown as a “PWM logic block” that is coupled to a Vreference select block132which selects between a nominal CM VREF level (e.g., 2.7 V) and a low CM VREF level (e.g., 1 V). The output of the Vreference select block132is coupled to an op am133connected as a voltage follower that has an output which is coupled to drive an input of the current source118.

Common-mode control circuit130′ together with current source118acts to control the amount of level-shifting current generated by current sources118and128pulled from the inverting input112aacting as a summing node for the first amplifier112. VREF_LOW is chosen to provide LDC PWM operation responsive to low input signal levels/CLIP activates VREF_NOM and thus dynamically increases the CM reference voltage level applied to the current source118responsive to higher input signal levels. The implementation of CM control circuit130′ shown inFIG. 2is based a PWM input design, however disclosed CM control circuits can also be applied to analog input class D designs.

EXAMPLES

Disclosed embodiments are further illustrated by the following specific Examples, which should not be construed as limiting the scope or content of this Disclosure in any way.

Good audio performance including low total harmonic distortion (THD) has been confirmed up to clipping with a low CM reference voltage level used with the TI′ TAS5632 power amplifier implementing an external version of disclosed CM reference voltage level control. Simulations performed showed that the CM reference voltage level can be changed without introducing pop/click problems. Listening tests with the TAS5632 also confirmed this result.

FIG. 3shows the simulated transient response responsive to a CM reference voltage level change for power amplifier100showing the loop filter CM reference voltage level and resulting power amplifier outputs OUTA and OUTB as a function of time, according to an example embodiment. The external positive power supply VDD was 12V, and the power amplifier100had internal voltage regulators to create AVDD=7.75V and DVDD=3.3V from VDDA. The low CM reference voltage level used was 1 V resulting in LDC PWM operation provided for the first 100 μs with a Duty Cycle of about 15%, and with a nominal 2.7 V CM reference voltage level that provides a DC of about 50% which is at a level high enough to eliminate clipping to lower crossover distortion beginning at a time shown of about 126 μs. No clipping is shown inFIG. 3.

FIG. 4Ashows measured transient response and duty cycle for a disclosed power amplifier with external CM reference voltage level control implementing a nominal CM reference voltage level of 2.7 V andFIG. 4Bshows the measured transient response and duty cycle for the disclosed power amplifier implementing a reduced CM reference voltage level of 1 V for implementing LDC PWM operation. The idle power dissipation can be seen to be reduced from 3.23 W using a nominal CM reference voltage level of 2.7 V to 1.73 W during LDC PWM operation, with no significant change to THD or idle channel noise during LDC PWM operation.

Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.