Reduction of power consumption in flash memory

Technologies are generally described for systems, devices and methods effective to reduce power consumption in flash memory. In some examples, a bit error rate estimator module may estimate two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. A voltage setup module may be configured to be in communication with the bit error rate estimator module. The voltage setup module may be configured to select a voltage to read from the memory. The voltage may be selected based on the two or more bit error rates and based on an error correction level. The error correction level may be a tolerance level available to correct read errors from the memory.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a U.S. National Stage filing under 35 U.S.C. §371 of International Application No. PCT/US13/057516, entitled “REDUCTION OF POWER CONSUMPTION IN FLASH MEMORY,” filed on Aug. 30, 2013, the entirety of which is hereby incorporated by reference.

BACKGROUND

Flash-based solid state data storage devices may be used to handle intensive data access workloads. A flash memory system may include a multitude of transistors controlled by a solid state memory controller. Each transistor within the flash memory system may be configured to store one bit of data. The solid state memory controller may be configured to control access to data stored within transistors of the flash memory system. Transistors in flash memory may have a limited number of program/erase cycles.

SUMMARY

In one example, a memory controller is generally described. The memory controller may include a bit error rate estimator module. The bit error rate estimator module may be configured to estimate two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. The memory controller may further include a voltage setup module. The voltage setup module may be configured to be in communication with the bit error rate estimator module. The voltage setup module may be further configured to select a voltage to read from the memory. The voltage may be selected based on the two or more bit error rates and based on an error correction level. The error correction level may be a tolerance level available to correct read errors from the memory.

In one example, a method to operate a memory is generally described. The method may include estimating two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. The method may further include identifying an error correction level available to correct read errors from the memory. The method may further include selecting a voltage to read from the memory. The voltage may be selected based on the estimated two or more bit error rates and the identified error correction level.

In one example, a computer readable storage medium is generally described. The computer readable storage medium may include one or more controller executable instructions stored thereon. In response to execution by a controller, the one or more controller-executable instructions may adapt the controller to perform or cause to be performed estimation of two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. In response to execution by a controller, the one or more controller-executable instructions may adapt the controller to perform or cause to be performed an identification of an error correction level available to correct read errors from the memory. In response to execution by a controller, the one or more controller-executable instructions may adapt the controller to perform or cause to be performed a selection of a voltage to read from the memory. The voltage may be selected based on the two or more bit error rates and the error correction level.

DETAILED DESCRIPTION

This disclosure is generally drawn to, inter alia, methods, apparatus, systems, devices, and computer program products related to reduction of power consumption in flash memory.

Briefly stated, technologies are generally described for systems, devices and methods effective to reduce power consumption in flash memory. In some examples, a bit error rate estimator module may estimate two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. A voltage setup module may be configured to be in communication with the bit error rate estimator module. The voltage setup module may be configured to select a voltage to read from the memory. The voltage may be selected based on the two or more bit error rates and based on an error correction level. The error correction level may be a tolerance level available to correct read errors from the memory.

FIG. 1illustrates an example system that can be utilized to implement reduction of power consumption in flash memory arranged in accordance with at least some embodiments described herein. An example memory device100may include a memory controller102. Memory device100may include one or more chips. Memory controller102may be a dedicated chip or may be integrated into another chip, such as a microprocessor. Memory controller102may control reads of one or more flash memory chips120,122. A read may include the detection and/or transmission of one or more bits stored at a location in flash memory chips120,122.

Memory controller102may include a bit error rate estimator module106. A bit error rate may be the probability of experiencing a detection bit error or transmission bit error. Bit error rate estimator module106may estimate the bit error rate of flash memory detect operations associated with different applied flash memory core supply voltages (“VCC”). Additionally, bit error rate estimator module106may estimate the transmission bit error rate of data transferred from flash memory chips120,122to memory controller102with different input/output supply voltages (“VCCQ”).

Memory controller102may include voltage setup module104. Voltage setup module104may be configured to select voltages VCCand/or VCCQto reduce power consumption of memory device100. Voltage setup module104may send an output/signal to a voltage regulator114. Voltage regulator114may be configured to control application of different voltages to one or more flash memory chips120,122. Two flash memory chips (120and122) are depicted, though any number of flash memory chips may be used. Flash memory chips120,122may be NAND flash memory or NOR flash memory and/or other types of flash memory. Flash memory chips120,122may be erasable and reprogrammable. Flash memory chips120,122may communicate with memory controller102via link128. Link128may be, for example, a bus.

Memory controller102may include a flash status monitor108. Flash status monitor108may be configured to determine a level of degradation of flash memory chips120,122. For example, flash status monitor108may determine the level of degradation of flash memory chip120by determination of a number of program and/or erase cycles performed by flash memory chip120. As flash memory degrades, the flash memory may be more susceptible to detection bit errors and/or transmission bit errors.

To correct detection and/or transmission bit errors, memory controller102may include an error correction code module110. Detection bit errors may include errors in detecting data out of flash memory chips120,122. Transmission bit errors may include errors in transmitting data from flash memory chips120,122, over link128to memory controller102. Error correction code module110may be configured to correct detection or transmission errors within memory device100. Error correction code module110may correct errors by, for example, adding redundant data (or “parity” data) to a string of bits. Adding redundant data may allow a bit to be recovered even when a number of errors were introduced during bit detection and/or transmission. The various modules and other components of memory device100may be operatively coupled to each other, for example via link128and/or other structure that couples two or more components together.

FIG. 2illustrates the example system ofFIG. 1with additional details relating to a bit error rate estimator module (such as bit error rate estimator module106) arranged in accordance with at least some embodiments described herein. Those components inFIG. 2that are labeled identically to components ofFIG. 1will not be described again for the purposes of clarity and brevity.

In an example, memory controller102may generate a table of voltages and bit error rates that can be used to select a voltage. For example, memory controller102may receive a request to detect data stored in flash memory chip120. A request to detect data may be, for example, application of voltage Vcc to acquire data stored in gates of flash memory chip120. Detected data may then be transmitted from the respective chip to memory controller102.

To detect stored data, memory controller102may call one or more flash translation layer functions to determine the physical memory page location that may store the requested data. In this example, the physical memory page may be page230, at a location on flash memory chip120. Flash status monitor108may provide bit error rate estimator module106with a level of degradation of page230of flash memory chip120. The level of degradation may be determined by, for example, using program/erase cycling information and/or a record of latest detect bit error statistics for page230. Program/erase cycling information may include the number of times a particular page of flash memory has been written to, erased, and then rewritten. Based on the provided level of degradation of page230, bit error rate estimator module106may generate a detect error estimation table224. Detect error estimation table224may be, for example, a data structure stored in bit error rate estimator module106or in another memory.

Detect error estimation table224may include estimations of detect bit error rates relating to detection of data in pages in flash memory chips120,122for application of different possible values of VCC. For example, with reference to the first row of detect error estimation table224, at a VCCvalue of 1.8 V, page230may be estimated to have a detect bit error rate of 1×10−6. In another example with reference to row 2 of detect error estimation table224, at a VCCvalue of 1.7 V, page230may be estimated to have a detect bit error rate of 1×10−5. Voltage setup module104may have access to data stored in detect error estimation table224.

Continuing with the above example, error correction code module110may provide voltage setup module104with an error correction level. Error correction level232may be, for example, an approximate percentage of errors which the error correction code is configured to correct. In another example, error correction level may be a tolerance level available to correct read errors from the memory. Such a tolerance level may be a maximum percentage of errors, for a given amount of data, that error correction code module110is able to correct. Based on error correction level232and detect error estimation table224, voltage setup module104may be configured to select a particular voltage, VCC′ that is usable to obtain a target bit error rate that represents a reduced number of bit errors. VCC′ may be the lowest value of VCCin table224with an associated detect bit error rate less than error correction level232. A signal corresponding to particular voltage VCC′ may be sent to voltage regulator114. Voltage regulator114may control application of particular voltage VCC′ to flash memory chip120and/or flash memory chip122. In the instant example, error correction level232of memory controller102may be 5×10−4(or 0.05%). Based on detect error estimation table224, voltage setup module104may select particular voltage VCC′ of 1.6V, as 1.6V is the lowest voltage with an associated detect bit error rate less than error correction level232(e.g. 1×10−4<5×10−4).

In a further example, at some future point in time, the level of degradation of page230may have increased as may be detected by flash status monitor108. As such, when bit error rate estimator module106generates a new or revised detect error estimation table224, the detect bit error rates for each respective voltage may have increased. This change in detection bit error rates may cause voltage setup module104to select a higher voltage VCC′ (relative to previous values of VCC′) so that the detect bit error rate remains less than error correction level232.

FIG. 3depicts the example system ofFIG. 1illustrating an example relating to transmission of data arranged in accordance with at least some embodiments described herein. Those components inFIG. 3that are labeled identically to components ofFIGS. 1 and 2will not be described again for the purposes of clarity and brevity.

In an example, memory controller102may receive a request to transmit data stored in flash memory chip122. Memory controller102may call one or more flash translation layer functions to determine the physical memory page location that may store the requested data. In an example, the physical memory page may be page332at a location on flash memory chip122. The requested data may be detected from page332of flash memory chip122.

A transmission error estimation table326, which may be generated and/or maintained by bit error rate estimation module106in a manner somewhat similar to detect error estimation table224described above, may include estimations of transmission bit error rates relating to transmission between flash memory chips and memory controller102associated with different possible values of VCCQ. For example, with reference to the first row of transmission error estimation table326, at a VCCQvalue of 1.8 V, flash memory chip122may be estimated to have a transmission bit error rate of 1×10−6. In another example with reference to row 2 of transmission error estimation table326, at a VCCQvalue of 1.7 V, flash memory chip122may be estimated to have a transmission bit error rate of 2×10−5. Voltage setup module104may have access to data stored in transmission error estimation table326.

Continuing with the above example, error correction code module110may provide voltage setup module104with error correction level232Based on error correction level232and transmission error estimation table326, voltage setup module104may be configured to select a particular voltage, VCCQ′. VCCQ′ may be the lowest value of VCCQin table326with an associated transmission bit error rate less than error correction level232. A signal corresponding to particular voltage VCCQ′ may be sent to voltage regulator114. Voltage regulator114may control application of particular voltage VCCQ′ to flash memory chip120and/or flash memory chip122. In the instant example, error correction level232of memory controller102may be 3×10−4(or 0.03%). Based on transmission error estimation table326, voltage setup module104may select particular voltage VCCQ′ of 1.7V, as 1.7V is the lowest voltage with an associated transmission bit error rate less than error correction level232(e.g. 2×10−5<3×10−4).

In a further example, at some future point in time, respective transmission bit error rates for different values of VCCQmay have increased as may be detected by flash status monitor108. Bit error rate estimator module106may generate a new transmission error estimation table326(or update an existing transmission error estimation table326). The increase of the bit error rates may cause voltage setup module104to select a higher voltage VCCQ′ (relative to previous values of VCCQ′) so that the transmission bit error rate remains less than error correction level232.

FIG. 4depicts the example system ofFIG. 1illustrating an example relating to transmission and detection of data arranged in accordance with at least some embodiments described herein. Those components inFIG. 4that are labeled identically to components ofFIGS. 1, 2 and 3will not be described again for the purposes of clarity and brevity.

Voltages VCC′ and VCCQ′ may be simultaneously and/or separately (such as in sequence) adjusted to reduce power consumption in flash memory chips. In an example, memory controller102may receive a request to read data in flash memory chip122. Memory controller102may call one or more flash translation layer functions to determine the physical memory page location that stores the requested data. In an example, the physical memory page may be page432located on flash memory chip122. The requested data may be detected from page432of flash memory chip122.

A transmission error estimation table428may include an estimation of the transmission bit error rate of transmission between flash memory chips and memory controller102associated with different possible values of VCCQ. For example, with reference to the first row of transmission error estimation table428, at a VCCQvalue of 3.3V, flash memory chip122may be estimated to have a transmission bit error rate of 1×10−6. In another example with reference to row 2 of transmission error estimation table428, at a VCCQvalue of 3.2V, page432may be estimated to have a transmission bit error rate of 2×10−5. Voltage setup module104may have access to data stored in transmission error estimation table428.

Contemporaneously or otherwise, memory controller102may receive a request to read data stored in flash memory chip120. Memory controller102may call one or more flash translation layer functions to determine the physical memory page location that may store the requested data. In this example, the physical memory page may be page430, located in flash memory chip120. Flash status monitor108may provide bit error rate estimator module106with a level of degradation of page430of flash memory chip120. Based on the provided level of degradation of page430, bit error rate estimator module106may generate (or update) a detect error estimation table424. Detect error estimation table424may be, for example, a data structure stored in bit error rate estimator module106or in another memory.

Detect error estimation table424may include estimations of detect bit error rates for detection of page430in flash memory chip120for different possible values of VCC. For example, with reference to the first row of detect error estimation table424, at a VCCvalue of 1.8V, page430may be estimated to have a detect bit error rate of 1×10−6. In another example with reference to row 2 of detect error estimation table424, at a VCCvalue of 1.7V, page430may be estimated to have a detect bit error rate of 1×10−5. Voltage setup module104may have access to data stored in detect error estimation table424.

Continuing with the above example, error correction code module110may provide voltage setup module104with error correction level232of error correction code module110. Error correction level232may be, for example, a percentage of errors which the error correction code is configured to correct. Based on error correction level232, detect error estimation table424and transmission error estimation table428, voltage setup module104may be configured to select particular voltages, VCC′ and VCCQ′. VCC′ and VCCQ′ may be the lowest combination value of VCCand VCCQin tables424and428with a combined associated bit error rate (detect bit error rate+transmission bit error rate) less than error correction level232. In examples where there are multiple combinations of VCCand VCCQin tables424and428which may sum to the same lowest combination value, voltage setup module104may examine available possible combinations of VCCand VCCQ, and choose the combination VCC′+VCCQ′ that leads to the lowest overall power consumption. Signals corresponding to particular voltages VCC′ and VCCQ′ may be sent to voltage regulator114. Voltage regulator114may control application of particular voltages VCC′ and VCCQ′ to flash memory chip120and/or flash memory chip122. In the instant example, error correction level232of memory controller102may be 3×10−4(or 0.03%). Based on detect error estimation table424and transmission error estimation table428, voltage setup module104may select particular voltage VCC′ of 1.6V and particular voltage VCCQ′ of 3.2V. 1.6V and 3.2V may represent the lowest voltages with a combined associated bit error rate less than error correction level232(e.g. 1×10−4+2×10−5=1.2×10−4<3×10−4).

According to the above example, voltage setup module104may send signals corresponding to the particular voltages VCCQ′ and VCC′ to voltage regulator114. Voltage regulator114may control application of the specified VCC′ and/or VCCQ′ voltages to flash memory chip120and/or flash memory chip122.

Among other possible features, a system in accordance with the disclosure may leverage error correction code strength to reduce energy consumption of flash memory detection and transmit operations. Additionally, a system in accordance with the disclosure may realize such power saving benefits without compromising the integrity of data detect/transfer operations. A system may leverage the extra error correction code tolerance that may be available when a memory device is relatively new and has experienced little degradation. Reduction of power consumption may have particular relevance for mobile devices using flash based memory systems.

FIG. 5depicts a flow diagram for example processes to implement reduction of power consumption in flash memory arranged in accordance with at least some embodiments described herein. In some examples, the process inFIG. 5could be implemented using memory device100discussed above and could be used to reduce power consumption in flash memory. An example process may include one or more operations, actions, or functions as illustrated by one or more of blocks S2, S4, and/or S6. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. The process inFIG. 5may be used by a memory device that includes a memory controller, such as memory controller102. In some embodiments, additional blocks representing further other operations, actions, or functions may be provided. The memory controller may be configured in communication with one or more flash memory chips.

Processing may begin at block S2, “Estimate two or more bit error rates, the bit error rates associated with application of respective voltages to read from a memory.” At block S2, two or more bit error rates may be estimated. The bit error rates may be associated with application of respective voltages to read from a memory. A bit error rate estimator (such as bit error rate estimator module106) may estimate the two or more bit error rates. In an example, the bit error rate estimator may be configured to estimate the two or more bit error rates based on a level of degradation of one or more flash memory locations. A flash status monitor (such as flash status monitor108) may be effective to determine the level of degradation. The level of degradation may be based on a number of program and/or erase cycles of the one or more flash memory locations. In an example, the two or more bit error rates may relate to detection of data from a location in the memory. In another example, the two or more bit error rates may relate to transmission of data from a location in the memory to the memory controller. In another example, the two or more bit error rates may relate to both detection of data from a location in the memory and transmission of the data from the location in the memory to the memory controller.

Processing may continue from block S2to block S4, “Identify an error correction level available to correct read errors from the memory.” At block S4, an error correction level may be identified. The error correction level may be available to correct read errors from the memory.

Processing may continue from block S4to block S6, “Select a voltage to read from the memory based on the two or more bit error rates and the error correction level.” At block S6, a voltage may be selected to read from the memory. The voltage may be selected by a voltage setup module (such as voltage setup module104). The voltage may be selected based on the two or more bit error rates and the error correction level. In an example, the voltage setup module may be configured to select the voltage by selection of a lowest respective voltage with an associated bit error rate less than the error correction level. In another example, the voltage setup module may be configured to select the voltage by selection of a lower (but not necessarily the lowest) respective voltage with an associated bit error rate less than the error correction level. In yet another example, the voltage setup module may be configured to select the voltage based on a first bit error rate related to detection of data from a location in the memory, a second bit error rate related to transmission of the data from the location in the memory to the memory controller, and the error correction level.

FIG. 6illustrates an example computer program product600that can be utilized to implement reduction of power consumption in flash memory arranged in accordance with at least some embodiments described herein. Computer program product600may include a signal bearing medium602. Signal bearing medium602may include one or more instructions604that, in response to execution by, for example, a processor, may provide the features described above with respect toFIGS. 1-5. Thus, for example, referring to memory device100, voltage setup module104may undertake one or more of the blocks shown inFIG. 6in response to instructions604conveyed to memory device100by signal bearing medium602.

In some implementations, signal bearing medium602may encompass a non-transitory computer-readable medium606, such as, but not limited to, a hard disk drive (HDD), a Compact Disc (CD), a Digital Video Disk (DVD), a digital tape, memory, etc. In some implementations, signal bearing medium602may encompass a recordable medium608, such as, but not limited to, memory, read/write (R/W) CDs, R/W DVDs, etc. In some implementations, signal bearing medium602may encompass a communications medium610, such as, but not limited to, a digital and/or an analog communication medium (e.g., a fiber optic cable, a waveguide, a wired communication link, a wireless communication link, etc.). Thus, for example, computer program product600may be conveyed to one or more modules of the memory device100by an RF signal bearing medium602, where the signal bearing medium602is conveyed by a wireless communications medium610(e.g., a wireless communications medium conforming with the IEEE 802.11 standard).

FIG. 7is a block diagram illustrating an example computing device700that is arranged to implement reduction of power consumption in flash memory arranged in accordance with at least some embodiments described herein. In a very basic configuration702, computing device700typically includes one or more processors704and a system memory706. A memory bus708may be used for communicating between processor704and system memory706.

Depending on the desired configuration, processor704may be of any type including but not limited to a microprocessor (μP), a microcontroller (μC), a digital signal processor (DSP), or any combination thereof. Processor704may include one or more levels of caching, such as a level one cache710and a level two cache712, a processor core714, and registers716. An example processor core714may include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP core), or any combination thereof. An example memory controller718may also be used with processor704, or in some implementations memory controller718may be an internal part of processor704Memory controller718may be memory controller102fromFIGS. 1-4. Alternatively, memory controller718may be a different memory controller.

Depending on the desired configuration, system memory706may be of any type including but not limited to volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.) or any combination thereof. System memory706may include an operating system720, one or more applications722, one or more programmable circuits766and program data724. Application722may include a reduction in power consumption in flash memory algorithm726that is arranged to perform the operations as described herein including those described with respect to memory device100ofFIGS. 1-6. Program data724may include reduction of power consumption in flash memory data728that may be useful to implement reduction of power consumption in flash memory as is described herein. In some embodiments, application722may be arranged to operate with program data724on operating system720such that reduction of power consumption in flash memory may be provided. This described basic configuration702is illustrated inFIG. 7by those components within the inner dashed line.

Computing device700may have additional features or functionality, and additional interfaces to facilitate communications between basic configuration702and any required devices and interfaces. For example, a bus/interface controller730may be used to facilitate communications between basic configuration702and one or more data storage devices732via a storage interface bus734. Data storage devices732may be removable storage devices736, non-removable storage devices738, or a combination thereof. Examples of removable storage and non-removable storage devices include magnetic disk devices such as flexible disk drives and hard-disk drives (HDDs), optical disk drives such as compact disk (CD) drives or digital versatile disk (DVD) drives, solid state drives (SSDs), and tape drives to name a few. Example computer storage media may include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data.

Computing device700may also include an interface bus740for facilitating communication from various interface devices (e.g., output devices742, peripheral interfaces744, and communication devices746) to basic configuration702via bus/interface controller730. Link128previously described above may be embodied in at least a portion of the bus(es) shown inFIG. 7. Example output devices742include a graphics processing unit748and an audio processing unit750, which may be configured to communicate to various external devices such as a display or speakers via one or more A/V ports752. Example peripheral interfaces744include a serial interface controller754or a parallel interface controller756, which may be configured to communicate with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device, etc.) or other peripheral devices (e.g., printer, scanner, etc.) via one or more I/O ports758. An example communication device746includes a network controller760, which may be arranged to facilitate communications with one or more other computing devices762over a network communication link via one or more communication ports764.