Power amplifier

A power amplifier includes an inverter amplification section configured to amplify AC components and remove DC components from at least one input signal, an impedance matching section configured to match an impedance of a transmission path of the at least one input signal amplified by the inverter amplification section, and an amplification section configured to amplify an impedance-matched signal from the impedance matching section according to a predetermined gain. The inverter amplification section includes at least one P-channel metal-oxide semiconductor field effect transistor (MOS FET) having a gate configured to receive the at least one input signal and at least one N-channel MOS FET having a gate configured to receive the at least one input signal. The at least one P-channel MOS FET and the at least one N-channel MOS FET are serially connected.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application No. 2009-0113233 filed on Nov. 23, 2009, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to power amplifiers, and more particularly, to a power amplifier that can increase power efficiency by preventing power consumption caused by DC components from an RF input signal.

2. Description of the Related Art

Mobile communications terminals have been widely used because they are easy to use. As the use of these mobile communications terminals has increased, it has become important to run various kinds of applications to meet consumer demand and allow for long-time use at the same time.

In order to extend the use time of a mobile communications terminal, it is important to increase battery capacity. However, the size of batteries is limited since small, lightweight, and thin mobile communications terminals are in demand in the market. Therefore, there is a need to increase the power efficiency of main elements inside a mobile communications terminal.

In order to transmit and receive RF signals, this mobile communications terminal uses a power amplifier. This power amplifier takes up a considerable portion of the overall power consumption of the mobile communication terminal.

Thus, the power efficiency of the power amplifier needs to be increased. However, as for a power amplifier being used in a mobile communications terminal according to the related art, DC current flows through the power amplifier at all times, which reduces power efficiency.

SUMMARY OF THE INVENTION

An aspect of the present invention provides a power amplifier that can increase power efficiency by preventing power consumption caused by DC components from an RF input signal.

According to an aspect of the present invention, there is provided a power amplifier including: an inverter amplification section configured to amplify AC components and remove DC components from at least one input signal; an impedance matching section configured to match an impedance of a transmission path of the input signal amplified by the inverter amplification section; and an amplification section configured to amplify an impedance-matched signal from the impedance matching section according to a gain set beforehand. The inverter amplification section includes at least one P-channel metal-oxide semiconductor field effect transistor (MOS FET) having a gate configured to receive the at least one input signal and at least one N-channel MOS FET having a gate configured to receive the at least one input signal, where the at least one P-channel MOS FET and the at least one N-channel MOS FET are serially connected.

The input signal may include balanced signals including an input signal having a positive level and an input signal having a negative level.

The inverter amplification section may include: a first inverter including a first P-channel MOS FET (metal-oxide-semiconductor field-effect transistor) having a drain receiving driving power, a gate receiving the input signal having the positive level, and a source connected to the impedance matching section, and a first N-channel MOS FET having a drain connected to the impedance matching section, connected to the source of the first P-channel MOS FET, a gate receiving the input signal having the positive level, and a source connected to a ground; and a second inverter including a second P-channel MOS FET having a drain being supplied with the driving power, a gate receiving the input signal having the negative level, and a source connected to the impedance matching section, and a second N-channel MOS FET having a drain connected to the impedance matching section, connected to the source of the P-channel MOS FET, a gate receiving the input signal having the negative level, and a source connected to a ground.

The impedance matching section may include: a first primary coil having one end receiving operating power and the other end connected to the source of the first P-channel MOS FET and the drain of the first N-channel MOS FET, the first primary coil receiving the amplified input signal having the positive level from the first inverter; a second primary coil having one end receiving the operating power and the other end connected to the source of the second P-channel MOS FET and the drain of the second N-channel MOS FET, the second primary coil receiving the amplified input signal having the negative level from the second inverter; a first secondary coil having one end receiving the operating power and the other end connected to the amplification section, the first secondary coil electromagnetically coupled with the first primary, and receiving the input signal having the positive level from the second primary coil to transmit the received input signal to the amplification section; and a second secondary coil having one end receiving the operating power and the other end connected to the amplification section, the second secondary coil electromagnetically coupled with the second primary coil and receiving the input signal having the positive level from the second primary coil to transmit the received input signal to the amplification section.

The amplification section may include a third N-channel MOS FET having a drain being supplied with the driving power, a gate receiving the input signal having the positive level from the other end of the first secondary coil, and a source connected to the ground, the third N-channel MOS FET amplifying the input signal having the positive level from the impedance matching section according to a gain set beforehand to thereby output the amplified input signal having the positive level; and a fourth N-channel MOS FET having a drain being supplied with the driving power, a gate receiving the input signal having the negative level from the other end of the second secondary coil, and a source connected to the ground, the N-channel MOS FET amplifying the input signal having the negative level from the impedance matching section according to a gain set beforehand to thereby output the amplified input signal having the negative level.

The power amplifier may further include an intermediate amplification section re-amplifying the input signals amplified by the inverter amplification section according to gains set beforehand, and transmitting the input signals being re-amplified to the impedance matching section.

The intermediate amplification section may include a first cascade amplification unit and a second cascade amplification unit each being supplied with the driving power from a driving power terminal, connected in parallel with each other, and receiving the input signal having the positive level and the input signal having the negative level from the inverter amplification section, respectively; and a first cascode amplification unit and a second cascode amplification unit connected in series between the first and second cascade amplification units and a ground terminal, connected in parallel with each other, and receiving the input signal having the positive level and the input signal having the negative level from the inverter amplification section, respectively, the first and second cascade amplification units may include third and fourth P-channel MOS FETs, respectively, while a gate of the third P-channel MOS FET receives the input signal having the positive level or the input signal having the negative level from the inverter amplification section, the gate of the third P-channel MOS FET being connected to that of the fourth P-channel MOS FET, and the first and second cascode amplification units may include third and fourth N-channel MOS FETs, respectively, while a gate of the third N-channel MOS FET receives the input signal having the positive level or the input signal having the negative level from the inverter amplification section, the gate of the fourth N-channel MOS FET being connected in common to that of the fourth N-channel MOS FET.

The impedance matching section may include a primary coil having one end electrically connected to a connection terminal between the first cascade amplification unit and the first cascode amplification unit and the other end electrically connected to a connection terminal between the second cascade amplification unit and the second cascode amplification unit, the primary coil receiving the input signal being re-amplified by the intermediate amplification section; and a secondary coil electromagnetically coupled with the primary coil and receiving the input signal being re-amplified from the primary coil.

The amplification section may include a third cascode amplification unit and a fourth cascode amplification unit connected in series between the driving power terminal and ground and connected in parallel with each other, the third and fourth cascode amplification units may include fifth and sixth N-channel MOS FETs, respectively, and a gate of the fifth N-channel MOS FET may receive an external gain control signal while a gate of the sixth N-channel MOS FET may receive the input signal having the positive level or the input signal having the negative level from the secondary coil of the impedance matching section.

The power amplifier may further include an intermediate amplification section re-amplifying the input signals, amplified by the inverter amplification section, according to gains set beforehand, and transmitting the re-amplified input signals to the impedance matching section.

The inverter amplification section may include a first inverter and a second inverter connected in series with each other between a driving power terminal supplying the driving power and ground, the first and second inverters each amplifying the input signal having the positive level according to an inverter method, and a third inverter and a fourth inverter connected in series between the driving power terminal and ground, and amplifying the input signal having the negative level according to an inverter method, the first inverter may include a first P-channel MOS FET having a drain being supplied with the driving power, a gate receiving the input signal having the positive level, and a source connected to the impedance matching section, while the second inverter may include a first N-channel MOS FET having a drain connected to the impedance matching section, connected to the source of the first P-channel MOS FET, a gate receiving the input signal having the positive level, and a source connected to a ground, and the third inverter may include a second P-channel MOS FET having a drain being supplied with the driving power, a gate receiving the input signal having the negative level, and a source connected to the impedance matching section, and the fourth inverter may include a second N-channel MOS FET having a drain connected to the impedance matching section, connected to the source of the second P-channel MOS FET, a gate receiving the input signal having the negative signal, and a source connected to the ground.

The intermediate amplification section may include a first cascade amplification unit and a second cascade amplification unit each being supplied with the power terminal from a driving power terminal supplying the driving power, connected in parallel with each other, and receiving the input signal having the positive level and the input signal having the negative level from the inverter amplification section, respectively, and the first and second cascade amplification units may include third and fourth P-channel MOS FETs, respectively, while a gate of the third P-channel MOS FET receives the input signal having the positive level or the input signal having the negative level from the inverter amplification section, the gate of the third P-channel MOS FET being connected in common to that of the fourth N-channel MOS FET, and the first and second cascode amplification units may include third and fourth N-channel MOS FETs, respectively, while a gate of the third N-channel MOS FET receives the input signal having the positive level or the input signal having the negative level from the inverter amplification section, the gate of the third N-channel MOS FET being connected in common to that of the fourth N-channel MOS FET.

The impedance matching section may include a primary coil having one end electrically connected to a connection terminal between the first cascade amplification unit and the first cascode amplification unit and the other end electrically connected to a connection terminal between the second cascade amplification unit and the second cascode amplification unit, the primary coil receiving the input signals re-amplified by the intermediate amplification section; and a secondary coil electromagnetically coupled with the primary coil and receiving the input signals being re-amplified from the primary coil.

The amplification section may include a third cascode amplification unit and a fourth cascode amplification unit connected in series with the driving power terminal and ground and connected in parallel with each other, the third and fourth cascode amplification units may include fifth and sixth N-channel MOS FETs, respectively, and a gate of the fifth N-channel MOS FET may include an external gain control signal while a gate of the sixth N-channel MOS FET may receive the input signal having the positive level or the input signal having the negative level from the secondary coil of the impedance matching section.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1is a schematic view illustrating the configuration of a power amplifier according to an exemplary embodiment of the invention.

Referring toFIG. 1, a power amplifier100according to this embodiment may include an inverter amplification section110, an impedance matching section120, and an amplification section130.

The inverter amplification section110may amplify an RF input signal according to an inverter method to thereby remove DC components therefrom.

The impedance matching section120matches the impedance of a transmission path of the RF input signal, amplified by the inverter amplification section110, to thereby transmit an impedance-matched signal to the amplification section130.

The amplification section130amplifies the impedance-matched signal from the impedance matching section120according to a gain set beforehand to thereby output the impedance-matched signal being amplified.

FIG. 2is a schematic circuit diagram illustrating the power amplifier as shown inFIG. 1.

Referring toFIGS. 1 and 2, the inverter amplification section110, which is included in the power amplifier100according to this embodiment, may include first and second inverters111and112.

The first inverter111may include a first P-channel MOS FET111aand a first N-channel MOS FET11b, which are connected in series with each other between a driving power terminal supplying driving power Vdd and a ground.

The first P-channel MOS FET111ahas a drain being supplied with the driving power Vdd, a gate receiving an input signal RFin+ having a positive level between RF input signals, and a source connected to the first N-channel MOS FET11b.

The first N-channel MOS FET11bhas a drain connected to the source of the first P-channel MOS FET111a, a gate receiving the input signal RFin+ having a positive level, and a source connected to a ground.

As described above, the first inverter111amplifies the input signal RFin+ having a positive level to thereby output an amplified output signal. The amplified output signal is output through a connection terminal between the first P-channel MOS FET111aand the first N-channel MOS FET11b. Therefore, the phase of the input signal RFin+ may be shifted such that the output signal has an inverse phase to the phase thereof on the basis of 0V. Therefore, while DC components, included in the input signal RFin+, are removed, AC components can be amplified.

Similarly, the second inverter112may include a second P-channel MOS FET112aand a second N-channel MOS FET112bthat are connected in series between the driving power terminal and ground. Like the configuration of the first inverter111, the second P-channel MOS FET112ahas a drain being supplied with the driving power Vdd, a gate receiving an input signal RFin− having a negative level between RF input signals, and a source connected to the second N-channel MOS FET112b. The second N-channel MOS FET112bhas a drain connected to the source of the second P-channel MOS FET112a, a gate receiving the input signal RFin− having a negative level, and a source connected to a ground.

In the same manner, the second inverter112removes DC components, included in the input signal RFin−, and amplifies AC components to thereby transmit an amplified output signal to the impedance matching section120.

The impedance matching section120may include a first primary coil P1, a second secondary coil P2, a first secondary coil S1, and a second secondary coil S2. The first primary coil P1receives the amplified output signal from the first inverter111. The second secondary coil P2receives the amplified output signal from the second inverter112. The first secondary coil S1performs the impedance matching of the amplified output signal according to a turns ratio, determined by electromagnetic coupling between the first primary and secondary coils P1and S1, to thereby transmit the impedance-matched signal to the amplification section130. The second secondary coil S2performs the impedance matching of the amplified output signal according to a turns ratio, determined by electromagnetic coupling between the second primary and secondary coils P2and S2to thereby transmit the impedance-matched signal to the amplification section130.

One end of the first primary coil P1is electrically connected to the second primary coil P2, and the other end of the first primary coil P1is electrically connected to the connection terminal between the first P-channel MOS FET111aand the first N-channel MOS FET11bof the first inverter111, so that the first primary coil P1can receive the output signal, obtained by amplifying the input signal RFin+ having a positive level, from the first inverter111.

One end of the second primary coil P2is electrically connected to one end of the first primary coil P1, and the other end of the second primary coil P2is connected to a connection terminal between the second P-channel MOS FET112aand the second N-channel MOS FET112bof the second inverter112, so that the second primary coil P2can receive the output signal, obtained by amplifying the input signal RFin− having a negative level, from the second inverter112.

One end of the first secondary coil S1receives operating power Vgate, and the other end thereof is electrically connected to the amplification section130, so that the first secondary coil S1can transmit the impedance-matched signal to the amplification section130. One end of the second secondary coil S2receives the operating power Vgate, and the other end thereof is electrically connected to the amplification section130, so that the second secondary coil S2can transmit the impedance-matched signal to the amplification section130.

The amplification section130may include a third N-channel MOS FET131and a fourth N-channel MOS FET132. The third and fourth N-channel MOS FETs131and132are connected in series between the driving power terminal and a ground and are connected in parallel with each other.

The third N-channel MOS FET131has a drain being supplied with the driving power Vdd, a gate receiving one of the impedance-matched signals, which has a positive level, from the impedance matching section120, and a source connected to the ground.

The fourth N-channel MOS FET132has a drain being supplied with the driving power Vdd, a gate receiving the other one having a negative level from the impedance matching section120, and a source connected to the ground.

Therefore, the amplification section130can amplify the impedance-matched signals with positive and negative levels from the impedance matching section120, separately, according to respective gains set beforehand to thereby output amplified signals.

FIG. 3is a schematic view illustrating the configuration of a power amplifier according to another exemplary embodiment of the invention.

Referring toFIG. 3, a power amplifier200according to this embodiment may include an inverter amplification section210, an intermediate amplification section220, an impedance matching section230, and an amplification section240.

The intermediate amplification section220may re-amplify signals, amplified by the inverter amplification section210, according to a gain set beforehand.

The functions of the inverter amplification section210, the impedance matching section230, and the amplification section240are similar with those of the inverter amplification section110, the impedance matching section120, and the amplification section130as described inFIG. 1. Thus, a detailed description thereof will be omitted.

FIG. 4is a schematic circuit diagram illustrating the power amplifier as shown inFIG. 4.

Referring toFIG. 4, the configurations of first and second P-channel MOS FETs211aand212a, included in the first inverter211, and first and second N-channel MOS FETs211band212b, included in the second inverter212, of the inverter amplification section210are the same as those of the inverter amplification section110. Thus, a detailed description thereof will be omitted.

The intermediate amplification section220may include first and second amplification units221and222that re-amplify signals having positive and negative levels, respectively, which are amplified by the inverter amplification section210.

The first amplification unit221may include first cascade amplification units221aand221band first cascode amplification units221cand221dthat are connected in series between a driving power terminal supplying driving power Vcc and ground. The second amplification unit222may include second cascade amplification units222aand222band second cascode amplification units222cand222dthat are connected in series between the driving power terminal and ground.

The first cascade amplification units221aand221bmay include third and fourth P-channel MOS FETs221aand221b, respectively, which are arranged in cascade configuration. The first cascode amplification units221cand221dmay include third and fourth N-channel MOS FETs221cand221d, respectively, which are arranged in cascode configuration.

The second cascade amplification units222aand222bmay include fifth and sixth P-channel MOS FETs222aand222b, respectively, which are arranged in cascade configuration. The second cascode amplification units222cand222dmay include fifth and sixth N-channel MOS FETs222cand222d, respectively, which are arranged in cascode configuration.

Since the above-described cascade configuration and cascode configuration are known in the art, a detailed description thereof will be omitted.

However, while one with a positive signal between the signals amplified by the inverter amplification section210, may be input to a gate of the third P-channel MOS FET221aof the first cascade amplification units221aand221band a gate of the fourth N-channel MOS FET221dof the first cascode amplification units221cand221d, the other signal with a negative signal between the signals, amplified by the inverter amplification section210, may be input to a gate of the fifth P-channel MOS FET222aof the second cascade amplification units222aand222band a gate of the sixth N-channel MOS FET222dof the second cascode amplification units222cand222d.

Furthermore, while a gate of the fourth P-channel MOS FET221bof the first cascade amplification units221aand221band a gate of the sixth P-channel MOS FET222bof the second cascade amplification units222aand222bmay be connected in common to each other, a gate of the third N-channel MOS FET221cof the first cascode amplification units221cand221dand a gate of the fifth N-channel MOS FET222cof the second cascode amplification units222cand222dmay be connected in common to each other.

The impedance matching section230may include a primary coil P and a secondary coil S. One end of the primary coil P is electrically connected to a connection node between the fourth P-channel MOS FET221band the third N-channel MOS FET221cand receives one of the re-amplified signals, which has a positive level. The other end of the primary coil P is electrically connected to a connection node between the sixth P-channel MOS FET222band the fifth N-channel MOS FET222cand receives the other one of the re-amplified signals, which has a negative level.

The secondary coil S may perform the impedance matching of the signals with positive and negative levels according to a turns ratio determined by electromagnetic coupling between the primary coil P and the secondary coil S to thereby transmit the impedance-matched signals to the amplification section.

The amplification section240may include third and fourth cascode amplification units241and242that are connected in series between the driving power terminal and ground and are connected in parallel with each other.

The third cascode amplification unit241may include seventh and eighth N-channel MOS FETs241aand241bthat are connected in cascode configuration between the driving power terminal and ground. The fourth cascode amplification unit242may include ninth and tenth N-channel MOS FETs242aand242bthat are connected in cascode configuration between the driving power terminal and ground.

Since the above-described cascode configuration is known in the art, a detailed description thereof will be omitted.

However, the seventh and ninth N-channel MOS FETs241aand242ahave gates that receive the impedance-matched signals having positive and negative levels, respectively, while the eighth and tenth N-channel MOS FETs241band242bhave gates that receive gain control signals VCG to control the gain.

FIG. 5is a schematic circuit diagram illustrating a power amplifier according to another exemplary embodiment of the invention.

Referring toFIGS. 4 and 5, the connections and configurations of an intermediate amplification section320having P-channel MOS FETs321a,321b,322a, and322, an impedance matching section330having N-channel MOS FETs321c,321d,322c,322d,341a,341b,342a, and342b, and an amplification section340having a primary coil P and a secondary coil S, which are included in a power amplifier according to this embodiment, are the same as those of the power amplifier, as shown inFIG. 4. Thus, a detailed description thereof will be omitted.

An inverter amplification section310may include a first inverter311and a second inverter312. The first inverter311may include first and second inverter amplification units311a,311b,311c, and311dthat are connected in series between the driving power terminal and ground. The second inverter312may include third and fourth inverter amplification units312a,312b,312c, and312dthat are connected in series between the driving power terminal and ground.

The first inverter amplification sections311aand311bmay include a first P-channel MOS FET311aand a first N-channel MOS FET311b, respectively. The second inverter amplification sections311cand311dmay include a second P-channel MOS FET311cand a second N-channel MOS FET311d, respectively.

The third inverter amplification sections312aand312bmay include a third P-channel MOS FET312aand a third N-channel MOS FET312b. The fourth inverter amplification sections312cand312dmay include a fourth P-channel MOS FET312cand a fourth N-channel MOS FET312d.

An input signal RFin+ having a positive level, among RF input signals, may be input to the first and second inverter amplification units. An input signal RFin− having a negative level, among the RF input signals, may be input to the third and fourth inverter amplification units.

The input signal RFin+ having a positive level may be input to individual gates of the first P-channel MOS FET311a, the first N-channel MOS FET311b, the second P-channel MOS FET311c, and the second N-channel MOS FET311d. The input signal RFin− having a negative level may be input to individual gates of the third P-channel MOS FET312a, the third N-channel MOS FET312b, the fourth P-channel MOS FET312c, and the fourth N-channel MOS FET312d.

Furthermore, a source of the first N-channel MOS FET311bmay be connected to a drain of the second P-channel MOS FET311c, and a source of the third N-channel MOS FET312bmay be connected to a drain of the fourth P-channel MOS FET312c.

Since other connections, except for these connections, are similar with those of the inverter amplification section110, as shown inFIG. 2, a detailed description thereof will be omitted.

As described above, according to the exemplary embodiments of the invention, an RF input signal is amplified according to an inverter method to remove DC components therefrom, thereby preventing power consumption caused by a DC signal, so that the efficiency of power, being consumed by a power amplifier, can be increased.

As set forth above, according to exemplary embodiments of the invention, power consumption caused by DC components of an RF input signal is prevented to thereby increase the power efficiency of a power amplifier.