Optical proximity correction method

An integrated circuit layout includes dense figures and at least one isolated figure. A plurality of dummy patterns are formed to surround the isolated figure, so as to reduce the difference in pattern density of the integrated circuit layout. A transmitted light of the dummy patterns provides a phase difference of 0 or 180 degrees relative to a transmitted light of the integrated circuit layout. The integrated circuit layout and the plurality of dummy patterns are formed on a photo-mask.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to an optical proximity correction (OPC) method, and more particularly, to an OPC method using dummy patterns to reduce the difference in pattern density.

2. Description of the Prior Art

In semiconductor manufacturing processes, in order to transfer an integrated circuit layout onto a semiconductor wafer, the integrated circuit layout is first designed and formed as a photo-mask pattern. The photo-mask pattern is then proportionally transferred to a photoresist layer positioned on the semiconductor wafer.

As the design pattern of integrated circuit becomes smaller and due to the resolution limit of the optical exposure tool, optical proximity effect will easily occur during the photolithographic process for transferring the photo-mask pattern with higher density. The optical proximity effect will cause defects when transferring the photo-mask pattern, such as right-angled corner rounding, line end shortening, and line width increasing/decreasing. U.S. Pat. No. 6,042,973 to Pierrat and U.S. Pat. No. 6,077,630 to Pierrat describe forming a subresolution grating composed of approximately circular contacts around the border of the primary patter of a photo-mask. As a result, resolution at the edges of the photo-mask pattern is improved when the pattern is printed on a wafer surface. However, the subresolution grating is not able to suppress the optical proximity effect when transferring the photo-mask pattern. Therefore, in order to avoid the above-mentioned defects caused by the optical proximity effect, the semiconductor process uses a computer system to perform an optical proximity correction (OPC) method of the integrated circuit layout. The corrected integrated circuit layout is then designed as a photo-mask pattern and is formed on a surface of the photo-mask.

Please refer toFIG. 1toFIG. 4.FIG. 1toFIG. 4are schematic diagrams of a prior art OPC method. As shown inFIG. 1, an original integrated circuit layout10comprises a plurality of lineFIG. 12for defining word lines. In order to avoid the defects of line end shortening and line width increasing/decreasing caused by the optical proximity effect when transferring the lineFIG. 12, a computer system is used to perform an OPC method of the integrated circuit layout10. As shown inFIG. 2, the photo-mask pattern14is a result of the integrated circuit layout10ofFIG. 1after correcting by the prior art OPC method. As well, as shown inFIG. 3, an original integrated circuit layout16comprises a plurality of rectangularFIG. 18for defining doped regions. In order to avoid the defects of right-angled corner rounding caused by the optical proximity effect when transferring the rectangularFIG. 18, a computer system is used to perform an OPC method of the integrated circuit layout16. As shown inFIG. 4, the photo-mask pattern20is a result of the integrated circuit layout16ofFIG. 3after correcting by the prior art OPC method.

The prior art OPC method only uses one OPC model to correct the whole integrated circuit layout, and the factor of different pattern density in local regions of the photo-mask resulting in overexposure or underexposure is not taken into consideration. Furthermore, as the system on chip (SOC) is developed, many different kinds of semiconductor devices (such as memory, logic circuits, Input/Output, and central processing unit) are integrated and formed on one chip for substantially reducing costs and improving speed. Therefore, the pattern density of integrated circuit layout is very different in local regions of the chip, and the prior art OPC method is not applicable.

SUMMARY OF INVENTION

It is therefore a primary objective of the claimed invention to provide an OPC method for solving the above-mentioned problems.

According to the claimed invention, an optical proximity correction (OPC) method is provided. The method first provides a predetermined integrated circuit layout. The integrated circuit layout is then formed on a surface of a photo-mask, and a plurality of transparent nonprintable dummy patterns are formed outside the integrated circuit layout on the surface of the photo-mask. The plurality of transparent dummy patterns are used to reduce the difference in pattern density on the surface of the photo-mask so as to modify optical proximity effect, and the dummy patterns are not transferred to a photoresist layer formed on a semiconductor wafer during a photolithography process because of a phase difference of 0 or 180 degrees between a transmitted light of the integrated circuit layout and a transmitted light of the dummy patterns.

It is an advantage over the prior art that the OPC method of the claimed invention forms a plurality of nonprintable dummy patterns around an integrated circuit layout predetermined to be transferred on a substrate. The dummy patterns are used to reduce the difference in pattern density of the integrated circuit layout for correcting optical proximity effect. Furthermore, the dummy patterns are designed by performing a simple operation according to conditions of a photolithographic process. Therefore, the time cost of a complicated operation performed by the prior art OPC method can be substantially reduced.

DETAILED DESCRIPTION

Please refer toFIG. 5andFIG. 6.FIG. 5andFIG. 6respectively depict the integrated circuit layouts10,16ofFIG. 1andFIG. 3after correcting by an OPC method according to the present invention method. As shown inFIG. 5, according to the present invention method, the integrated circuit layout10predetermined to be transferred to a substrate (not shown), such as a semiconductor wafer, is directly formed on a surface of a photo-mask (not shown). The integrated circuit layout10includes a plurality of figures, such as dense lineFIG. 12a, semi-dense lineFIG. 12band at least an isolated lineFIG. 12c. However, the integrated circuit layout10is not limited to include line figures only. The integrated circuit layout10can include figures in various shapes and in different pattern density according to the present invention.

Moreover, a plurality of dummy patterns30of rectangular figures are formed in a blank region outside the integrated circuit layout10on the surface of the photo-mask, and the integrated circuit layout10and the dummy patterns30together compose a photo-mask pattern32. The dummy patterns30are used to reduce the difference in pattern density of the integrated circuit layout10. For example, the dummy patterns30can be formed to surround the isolated lineFIG. 12c, the semi-dense lineFIG. 12b, or distributed in other blank regions. In other words, the present invention method first uses a computer system to perform an optical proximity correction of the integrated circuit layout10predetermined to be transferred to a substrate by forming a plurality of nonprintable dummy patterns30in the blank region outside the integrated circuit layout10. The integrated circuit layout10and the plurality of nonprintable dummy patterns30are then simultaneously fabricated on the surface of the photo-mask so as to reduce the difference in pattern density of the integrated circuit layout10. According to one embodiment of the present invention, the dummy patterns30are only fabricated around the integrated circuit layout10. According to another embodiment of the present invention, the dummy patterns30are fabricated and distributed over the blank region outside the integrated circuit layout10, as shown inFIG. 5.

As well, as shown inFIG. 6, the integrated circuit layout16predetermined to be transferred to a substrate is directly formed on a surface of a photo-mask. The integrated circuit layout16includes a plurality of figures, such as dense rectangularFIG. 18a, semi-dense rectangularFIG. 18band at least an isolated rectangularFIG. 18c. However, the integrated circuit layout16is not limited to include rectangular figures only. The integrated circuit layout16can include figures in various shapes and in different pattern density according to the present invention.

Moreover, a plurality of dummy patterns40of rectangular figures are formed outside the integrated circuit layout16on the surface of the photo-mask, and the integrated circuit layout16and the dummy patterns40together compose a photo-mask pattern42. The dummy patterns40are used to reduce the difference in pattern density of the integrated circuit layout16. For example, the dummy patterns40can be formed to surround the isolated rectangularFIG. 18c, the semi-dense rectangularFIG. 18b, or distributed in other blank regions on the photo-mask.

In another embodiment of the present invention method, a computer system is first used to perform a prior art OPC of the integrated circuit layouts10,16for preventing the pattern transferring defects, such as right-angled corner rounding, line end shortening, and line width increasing/decreasing. A plurality of nonprintable dummy patterns are then formed in a blank region outside the corrected integrated circuit layouts. Finally, the corrected integrated circuit layouts and the plurality of nonprintable dummy patterns are simultaneously fabricated on a surface of a photo-mask so as to reduce the difference in pattern density of the integrated circuit layouts10,16.

The integrated circuit layouts10,16ofFIG. 5andFIG. 6will be transferred from the photo-mask to a photoresist layer formed on a surface of the substrate by a pattern transferring process, such as a photolithographic process. Therefore, in a preferred embodiment of the present invention, the shapes, the dimensions and the numbers of the dummy patterns30,40are designed according to exposure wave length and numerical apertures of the pattern transferring process and the materials included in the photoresist layer for reducing the difference in pattern density of the integrated circuit layouts10,16and modifying the optical proximity effect. Another important design factor of the dummy patterns30,40is that a phase difference of 0 or 180 degrees is detected between a transmitted light of the integrated circuit layout10,16and a transmitted light of the dummy patterns30,40, and the dummy patterns30,40will not be transferred to the photoresist layer during the photolithographic process. InFIG. 5andFIG. 6for example, the edge length of dummy patterns30,40of rectangular figures is a multiple of exposure wave length, and the multiple is less than 0.6. The distance between each of the dummy patterns30,40is also a multiple of exposure wave length, and the multiple ranges between 0.3 and 2.0. As well, the least distance between the integrated circuit layout10,16and the dummy patterns30,40is a multiple of exposure wave length, and the multiple ranges between 0.4 and 2.0.

Briefly speaking, the OPC method of the claimed invention forms a plurality of nonprintable dummy patterns around an integrated circuit layout predetermined to be transferred to a substrate. The dummy patterns are used to reduce the difference in pattern density of the integrated circuit layout for modifying optical proximity effect. Comparing to the prior art OPC method, the dummy patterns of the present invention are designed by performing a simple operation according to conditions of a photolithographic process. Therefore, the time cost of a complicated operation performed by the prior art OPC method can be substantially reduced.

Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teaching of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.