Body effect amplifier

A circuit includes a transistor having a biased gate terminal and an input coupled to a bulk terminal. A voltage applied between the bulk terminal and the source terminal modulates the drain-source current. The transistor operates in a saturation region with a bias voltage applied to the gate terminal. The output current is received by a load resistor or an active load.

FIELD

This subject matter pertains to amplifiers and in particular, to amplifiers having a bulk input terminal.

BACKGROUND

The input pair of transistors in a traditional differential amplifier do not operate in the saturation region when the differential input signal has a common mode voltage level that exceeds the available power supply. When not in saturation, the gain of the input stage is low.

For these and other reasons, an improved amplifier is needed.

DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the present subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter, and it is to be understood that the embodiments may be combined, or that other embodiments may be utilized and that structural, mechanical, logical and electrical changes may be made without departing from the scope of the present subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present subject matter is defined by the appended claims and their equivalents.

FIG. 1Aincludes a cross-sectional view of transistor50according to one embodiment of the present subject matter. Transistor50, in various embodiments includes a field effect transistor such as an insulated gate field effect transistor or a metal oxide semiconductor field effect transistor.

In the figure, transistor50is illustrated as a p-type transistor, however, n-type transistors are also contemplated. Transistor50includes n-type substrate64having p+doped region60and p+doped region62. Regions60and62each are electrically coupled to metal electrodes52and56, respectively. In addition, polysilicon layer66is disposed between doped regions60and62and separated by gate oxide layer68. Gate oxide layer68, in a small transistor, is relatively thin and can degrade quickly upon exposure to high voltages.

An electrical connection to polysilicon layer66is provided by electrode54. An electrical connection to substrate64is provided by electrode58. Electrode54is commonly referred to as a gate terminal and electrode58is commonly referred to as a bulk terminal, n-well terminal or body terminal. For an n-type transistor, the bulk terminal may be connected to a p-well.

Electrodes52and56are electrically identical and each are sometimes referred to as a source/drain. In the context of an electrical circuit, one electrode is commonly designated as a source and the other is commonly designated as a drain. In the figures, the electrode nearest the arrow is referred to as the source.

In the present subject matter, an input signal is provided to the bulk terminal. Modulation of the input signal causes modulation of the current through the transistor. In one embodiment, a gate terminal is biased.

FIG. 1Billustrates amplifier circuit100having transistor120and transistor140. Transistors120and140, sometimes referred to as a pair, or as a differential pair, include field effect transistors such as that depicted by transistor50. Input node110and input node115are each separately coupled to a bulk terminal of transistor120and transistor140, respectively.

A gate terminal of transistor120and a gate terminal of transistor140are electrically coupled to node125. Node125is biased by a series combination of resistor180and voltage supply135. In one embodiment, node125is biased by a resistive voltage divider network or other voltage source. Other circuitry for biasing node125is also contemplated. The common gate terminal of transistors120and140establishes a bias point for each transistor.

The bias voltage on node125can be adjusted to compensate for device performance. For example, in one embodiment, the bias voltage is adjusted based on at least one of any combination of an operating temperature, a supply voltage, fabrication process and input common mode voltage.

The source terminal of transistor120and the source terminal of transistor140are electrically coupled to node105. In one embodiment, node105is biased by current source104coupled to a supply voltage at103, as shown atFIG. 1B. In one embodiment, node105is coupled directly to VDD. In one embodiment, the supply voltage at node103is VDD. A typical value for VDDis 1.8 volts DC with a range of values between 1.71 and 1.89 volts. Values higher or lower than these are also contemplated.

Output node130is coupled to the drain terminal of transistor120and output node145is coupled to the drain terminal of transistor140. Each of output nodes130and145are separately coupled to reference node170by a passive load. In the figure, reference node170is illustrated as an electrical ground, however, other reference levels are also contemplated. Output node130is coupled to reference node170by the parallel combination of resistor150and capacitor160. Output node145is coupled to reference node170by the parallel combination of resistor155and capacitor165. In one embodiment, the parallel combination of a resistor and a capacitor is replaced by an active load.

The resistance value of resistors150and155correspond to the output impedance of transistor120and transistor140, respectively. The capacitance of capacitors160and165is presented for simulation of the node and the next stage capacitance. In one embodiment, the capacitors are omitted since parasitic capacitance affects performance of the circuit at high frequency.

The variation of the threshold voltage of a transistor due to a variation of the substrate or bulk voltage is sometimes referred to as body effect. In accordance with the present subject matter, the voltage at the bulk terminal, VSB, is used to modulate the current through the transistor, Ids. The transconductance bulk-channel (gmbs) is a result of the modulation of the threshold voltage (VT) by the bulk-source voltage as describe in equations 1 and 2 below.

Where

ΦF=strong inversion surface potential

In one embodiment, transistors120and140operate in the saturation region because the bias voltage at node125is higher than the output common voltage at nodes130and145. Therefore transistors120and140have a high transconductance bulk-source (gmbs) and high output resistance (rds). Equations 1, 2 and 3 illustrate the amplification achieved as between the bulk voltage and the current through the transistor. In particular, equations 1, 2 and 3 illustrate the effect of VSBon threshold voltage VT.

The equations presented here depend on the DC operation point of the transistor. In various embodiments, the transistors are biased for operation in a saturation or linear mode. The transistors are operated in saturation region by tuning the bias voltage at node125.

In one embodiment, the junction between node105and node110is maintained in a reverse bias mode. For example, the voltage on node110is no lower than 0.7–0.8 volts below that of node105. If this junction is operated in a forward bias, then the transistor junction will open. In one embodiment, this junction is operated in a reverse bias mode by selection of predetermined operating voltages.

A circuit according toFIG. 1Bdemonstrated a minimum amplification gain of approximately −1.7 dB at VDDof 1.71 volts with a frequency of 800 Mhz and a common voltage at the input nodes of 2.35 volts over all corners and temperature. Amplification gain of −1.7 dB of the present subject matter compares favorably with a traditional differential amplifier having a gain of approximately −18 dB. Current consumption was demonstrated at about 200 μA. The dimensions of transistors120and140are approximately 8 microns in width by 0.36 microns in length.

FIG. 2illustrates amplifier200having a single ended output and an active load. In particular, the drain terminal of transistor120is coupled to node205. Node205is further coupled to both the drain terminal and a gate terminal of transistor210as well as a gate terminal of transistor220. A bulk terminal and a source terminal of transistor210are coupled to reference node170. A drain terminal of transistor140is coupled to output node245and also to a drain terminal of transistor220. A bulk terminal and a source terminal of transistor220are coupled to reference node170. A differential input signal is applied to input node110and input node115, each of which are coupled to bulk terminals of transistors120and140, respectively.

In one embodiment, node105, as shown inFIG. 2, is coupled to a supply voltage at node103by current source140. Current source140, in one embodiment, includes a transistor. In one embodiment, node105is coupled directly to VDD. In addition, node125is coupled to a voltage source (not shown), such as that ofFIG. 1B. Other voltage sources are also contemplated, including, for example, a voltage divider network.

The output current inFIG. 1Bflows through resistors150and155. In contrast toFIG. 1B, the output current in the circuit ofFIG. 2flows through a current mirror.

Effectively, the output current flows through a resistor (or active load) in parallel with the transistor output impedance. For a high gain, the transistor output resistance is selected to be high. The transistor output resistance, rds, is a measure of AC resistance between the source and the drain.

FIG. 3includes a schematic of single ended amplifier300according to one embodiment of the present subject matter. In the figure, the source terminal of transistor120is coupled to a supply voltage at node105. In one embodiment, the source terminal of transistor120is coupled to a current source at node105. The current source, in one embodiment, includes a transistor.

The drain terminal of transistor120is coupled to output node345and also resistor350to reference node170. In one embodiment, resistor350is replaced with an active load. Input node110is coupled to a bulk terminal of transistor120.

A voltage applied to node105biases transistor120. Node325is coupled to a bias voltage source by, for example, a voltage divider network.

The present subject matter can function as a stage of a multi-stage amplifier or a logical gate, such as an inverter, or other circuit. Representative of such other devices isFIG. 4which illustrates communication device400. In the figure, device400represents a radio frequency receiver such as, for example but not by way of limitation, that of a cellular telephone, pager, or other wireless device. In the figure, antenna402is coupled to preamplifier412by tuner414. Antenna402has an output terminal coupled to node404which is also coupled to the input of tuner414. An output signal from tuner414is coupled, at node416, to a bulk terminal of transistor120. In addition, output node345, coupled to a drain of transistor120, is also coupled to an input terminal of amplifier406. Amplifier406represents an intermediate stage or power amplifier for the low level signal provided by preamplifier412. Amplifier output terminal408is coupled to circuit410. In various embodiments, circuit410represents electrical circuitry, such as for example but not by way of limitation, an amplifier, a mixer, a multiplexer, a logic gate, a microprocessor, memory or other circuitry configured to perform a function as a communication device. Transistor120is biased at node105and node325. Load resistor350couples the drain of transistor120to reference node170.

FIG. 4illustrates a single ended amplifier however, it will be understood that a differential amplifier, as described herein, may also be used with an antenna. For example, with a dipole antenna, a first input of a differential pair is coupled to a first member of the antenna and a second input is coupled to a second member of the antenna.

Performance of the circuit according to the present subject matter can be adjusted by selecting operating voltages, currents, component values and properties and a particular configuration. Equations 1, 2 and 3 can be used to tailor the circuit performance for a particular application.

FIG. 4Bincludes a schematic of low voltage differential signaling interface418. In the figure, driver420includes transmitter amplifier426which provides a differential output signal at nodes428and430. Interconnect422provides an electrical coupling between driver420and receiver424. Receiver424includes differential amplifier436A having differential inputs at nodes432A and434A. Differential amplifier436A presents an input impedance represented by438A. In the figure, amplifier426and amplifier436A are each separately coupled to reference node444and reference node442, respectively. In addition, voltage supply440represents a ground potential delta between the respective amplifiers.

In various embodiments, driver420, interconnect422and receiver424are disposed on one or more circuit boards or substrates.

FIG. 4Cincludes a schematic of differential amplifier436B for an interface according to one embodiment of the present subject matter. In the figure, input node432B and complementary input node434B provide a differential input signal to amplifier436B. Node432B and node434B are coupled to a bulk terminal of transistor120and transistor140, respectively. Shunting node432B and434B is input resistor438B. Node105and node125are biased at voltage and current levels to allow the differential pair of transistors120and140to operate as a differential amplifier. A differential output signal is provided at nodes130and145. Resistors150and155couple the drain terminals of transistors120and140, respectively, to reference potential442. Other configurations for amplifier436B are also contemplated, including, for example, a single ended output using a current mirror or other active load.

FIG. 5illustrates a flow chart of a method500according to one embodiment of the present subject matter. At520, method500includes biasing a gate terminal of a transistor. The transistor is part of an amplifier circuit or a logic circuit. In various embodiments, the transistor includes an insulated gate field effect transistor or a metal oxide semiconductor field effect transistor. In various embodiments, biasing includes providing a bias voltage from a supply. For example, a resistive voltage divider network or a current source and a resistor can provide a bias voltage. At530, an input signal is provided to a bulk terminal of the transistor. In one embodiment, the input signal includes a first and second differential input signal. At540, an output signal is generated as a function of the signal on the bulk terminal and the bias on the gate terminal. In one embodiment, a single ended or differential output signal is generated where each output signal is a function of the corresponding input signal. The output signal is generated at the drain terminal of the circuit. In one embodiment, the output signal is derived from a particular terminal of the transistor for which the gate terminal is biased and the input is provided on the bulk terminal. In one embodiment, the output signal is derived from a particular terminal of a transistor that differs from the transistor for which the gate terminal is biased and the input is provided on the bulk terminal.

In one embodiment, method500includes biasing a source/drain terminal of the transistor. Biasing, for example, includes providing a supply voltage to the source/drain terminal or providing a current source. In one embodiment, the transistor is operating in a saturation mode.

ALTERNATIVE EMBODIMENTS

The figures illustrate a p-type transistor. However, it is understood that an n-type transistor is also suitable for use in the present subject matter with a complementary change in polarity.

This present subject matter can be used as an input stage for an amplifier. In addition, the present subject matter can be used to amplify an input signal having a common mode voltage in excess of the power supply voltage.

Transistors larger or smaller than 8 microns wide by 0.36 microns length are also contemplated. In general, a larger transistor reduces mismatch between adjacent stages of an amplifier.

CONCLUSION

The above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description.