Data frame interface network device

Disclosed herein is a system including a network interface arranged to receive a data frame from one or more communication networks. A frame filter is arranged to receive the data frame from the network interface, wherein the frame filter selectively outputs the data frame to at least one of a second network interface or a direct memory access (DMA) controller based on a data frame type. The DMA controller is arranged to store a received data frame to shared memory and transmit an interrupt signal to a media access control (MAC) driver after the received data frame is stored in the shared memory so that the MAC driver can initiate an interrupt handler in response to the interrupt signal to retrieve the stored data frame.

BACKGROUND

A satellite network allows traffic between devices, terminals, satellite(s), and gateways. For example, a device such as a mobile device or computer, connected through a local area network to a terminal, can communicate with another device, i.e., via a satellite uplink and/or downlink and one or more gateways.

DETAILED DESCRIPTION

Disclosed herein is a system including a network interface arranged to receive a data frame from one or more communication networks. A frame filter is arranged to receive the data frame from the network interface, wherein the frame filter selectively outputs the data frame to at least one of a second network interface or a direct memory access (DMA) controller based on a data frame type. The DMA controller is arranged to store a received data frame to shared memory and transmit an interrupt signal to a media access control (MAC) driver after the received data frame is stored in the shared memory so that the MAC driver can initiate an interrupt handler in response to the interrupt signal to retrieve the stored data frame.

In other features, the system includes the MAC driver arranged to retrieve the stored data frame after receiving the interrupt signal and provides the stored data frame to a kernel network stack.

In other features, the data frame type comprises at least one of a high-speed data frame, a protocol frame, or a management frame, wherein the high-speed data frame comprises a data frame transmitted up to a rate of at least one hundred gigabits per second (Gbit/s).

In other features, the frame filter is arranged to selectively output the data frame to the second network interface when the data frame type of the data frame is a high-speed data frame and to the DMA controller when the data frame type is at least one of a protocol frame or a management frame.

In other features, the frame filter comprises a plurality of comparators and an inverse multiplexer.

In other features, each comparator of the plurality of comparators includes an input and an output, wherein each input receives the data frame and compares one or more bits of the data frame to at least one configurable filter value and configurable filter mask.

In other features, the network interface receives the data frame from a terrestrial connection point.

In other features, the second network interface comprises a radio frequency transceiver (RFT) interface that receives data frames from a satellite.

In other features, the DMA controller inserts a header portion into the data frame, wherein the header portion comprises data indicative of a length to a next header field.

Further disclosed herein is a satellite communication system and a gateway that communicates with the satellite and surface-based communication networks. The gateway includes a network interface arranged to receive a data frame from one or more communication networks and a frame filter arranged to receive the data frame from the network interface. The frame filter selectively outputs the data frame to at least one of a second network interface or a direct memory access (DMA) controller based on a data frame type. The gateway also includes the DMA controller that is arranged to store a received data frame to shared memory and transmit an interrupt signal to a media access control (MAC) driver after the received data frame is stored in the shared memory so that the MAC driver can initiate an interrupt handler in response to the interrupt signal to retrieve the stored data frame

In other features, the gateway includes the MAC driver arranged to retrieve the stored data frame after receiving the interrupt signal and provides the stored data frame to a kernel network stack.

In other features, the data frame type comprises at least one of a high-speed data frame, a protocol frame, or a management frame, wherein the high-speed data frame comprises a data frame transmitted up to a rate of at least one hundred gigabits per second (Gbit/s).

In other features, the frame filter is arranged to selectively output the data frame to the second network interface when the data frame type of the data frame is a high-speed data frame and to the DMA controller when the data frame type is at least one of a protocol frame or a management frame.

In other features, the frame filter comprises a plurality of comparators and an inverse multiplexer.

In other features, each comparator of the plurality of comparators includes an input and an output, wherein each input receives the data frame and compares one or more bits of the data frame to at least one configurable filter value and configurable filter mask.

In other features, wherein the network interface receives the data frame from a terrestrial connection point.

In other features, the second network interface comprises a radio frequency transceiver (RFT) interface that receives data frames from the satellite.

Further disclosed herein is a method that includes receiving, at a network interface, a data frame from one or more communication networks and selectively outputting, via a frame filter, the data frame at least one of a second network interface or a direct memory access (DMA) controller based on a data frame type. The method also includes storing, via the DMA controller, a received data frame to shared memory and transmitting an interrupt signal to a media access control (MAC) driver after the received data frame is stored in the shared memory so that the MAC driver can initiate an interrupt handler in response to the interrupt signal to retrieve the stored data frame.

In other features, the method includes retrieving, via the MAC driver, the stored data frame after receiving the interrupt signal and provides the stored data frame to a kernel network stack.

In other features, the data frame type comprises at least one of a high-speed data frame, a protocol frame, or a management frame, wherein the high-speed data frame comprises a data frame transmitted up to a rate of at least one hundred gigabits per second (Gbit/s).

In embedded systems, handling the high throughput of a data frame, such as data link layer protocol data unit, transmitted from one hundred gigabit (100G) Ethernet interfaces can become infeasible for software to handle. In these instances, the embedded systems may require high-end processors, e.g., controllers, or specialized networking processors to process the data frames.

A gateway can include a frame filter such that high-speed data frames can be handled by a programmable logic portion of the embedded system and non-high-speed data frames can be handled by the processor system portion of the embedded system. For example, the programmable logic portion can cause the high-speed data frames to be stored in the memory, such as a dynamic random access (DRAM) portion of the memory, for network processing. As such, a controller within a processor system portion of the embedded system may be utilized for application centric processing. In an example implementation, the programmable logic portion of the embedded system may comprise a field-programmable gate array (FPGA) fabric.

FIG. 1illustrates a satellite communication system100capable of providing voice and data services. The satellite communication system100includes a satellite110that supports communications among one or, typically, more gateways120(only one shown) and multiple stationary satellite terminals140-A through140-N, where A and N are integers greater than or equal to one. Each stationary satellite terminal (or terminal)140can be configured for relaying traffic between its customer premise equipment (CPEs)142-A through142-N, and one or more surface-based communication networks, e.g., a public network150such as the internet, and/or a private network160. According to an exemplary implementation, the terminals140can be in the form of very small aperture terminals (VSATs) that are mounted on a structure, habitat, etc. According various implementations, the terminals140can be mounted on mobile platforms that facilitate transportation thereof from one location to another. Such mobile platforms can include, for example, cars, buses, boats, planes, etc. The terminals140can further be in the form of transportable terminals capable of being transported from one location to another. Such transportable terminals are operational only after arriving at a particular destination, and not while being transported.

As illustrated inFIG. 1, the satellite communication system100can also include a plurality of mobile terminals145that are capable of being transported to different locations by a user. In contrast to transportable terminals, the mobile terminals145remain operational while users travel from one location to another. The gateway120can be configured to route traffic from stationary, transportable, and mobile terminals (collectively terminals140) across the public network150and private network160as appropriate. The gateway120can be further configured to route traffic from the public internet150and private network160across the satellite link to the appropriate terminal140. The terminal140then routes the traffic to the appropriate customer premise equipment (CPE)142.

According to at least one implementation, the gateway120can include various components, implemented in hardware, software, or a combination thereof, to facilitate communication between the terminals140and external network150,160via the satellite110. According to an implementation, the gateway120components can include a radio frequency transceiver122(RFT), a programmable integrated circuit124, and a data storage device126(or storage device). As used herein, a transceiver is any type of antenna device used to transmit and receive signals, a transmitter, a receiver, etc. The RFT122can transmit and receive signals within a communication system such, as the satellite communication system100illustrated inFIG. 1. The data storage device126can be used, for example, to store and provide access to information pertaining to various operations in the satellite communication system100. According to other implementations, the gateway120can include multiple programmable integrated circuits124and multiple data storage devices126. The data storage device126can be, for example, a single drive, multiple drives, an array of drives configured to operate as a single drive, etc. Various implementations further provide for redundant paths for components of the gateway120. The redundant paths can be associated with backup components capable of being seamlessly or quickly switched in the event of a failure or critical fault of the primary component.

In various implementations, the data storage device126may be referred to as memory126. The memory126may include any non-transitory computer usable or readable medium, which may include one or more storage devices or storage articles. The memory126, as explained in greater detail below, can comprise shared memory126accessible by multiple systems. Exemplary non-transitory computer usable storage devices include conventional hard disk, solid-state memory, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), as well as any other volatile or non-volatile media. Non-volatile media include, for example, optical or magnetic disks and other persistent memory, and volatile media, for example, also may include dynamic random-access memory (DRAM). These storage devices are non-limiting examples; e.g., other forms of computer-readable media exist and include magnetic media, compact disc ROM (CD-ROMs), digital video disc (DVDs), other optical media, any suitable memory chip or cartridge, or any other medium from which a computer can read.

According to the illustrated implementation, the gateway120includes baseband components128that process signals being transmitted to, and received from, the satellite110. For example, the baseband components128can incorporate one or more modulator/demodulator devices, system timing equipment, switching devices, etc. The modulator/demodulator devices can be used to generate carriers that are transmitted into each spot beam and to process signals received from the terminals140. The system timing equipment can be used to distribute timing information for synchronizing transmissions from the terminals140.

The gateway120can further include a network interface132for establishing connections with a terrestrial connection point134from a service provider. Depending on the specific implementation, however, multiple terrestrial connection points134may be utilized. The terrestrial connection point134provides a connection to a communication network, such as the public network150and/or the private network160. A communication network150, for example, may be a local area network (LAN) configured in accordance with IEEE 802.3, e.g., Ethernet. The communication network150typically provides communication access to a public network160, e.g., including the Internet. The network interface132may be connected to the terrestrial connection point134via a wired connection or a wireless connection. In some instances, the terrestrial connection point134may connect the network interface132to networking hardware, such as a network switch.

FIG. 2illustrates an example of the programmable integrated circuit124on which the disclosed circuits and processes may be implemented. In one or more implementations, the programmable integrated circuit124can be used within the gateway120for the purposes of directing data packets to various portions of the programmable integrated circuit124.

As shown, the programmable integrated circuit124includes programmable logic202and a processor operating system204. It is understood that only a portion of the programmable logic202and the processor system204is illustrated as described herein. The programmable logic202and the processor system204may comprise a field-programmable gate array (FPGA), which may comprise an array of programmable logic blocks. The programmable logic202can comprise circuitry that implements the logic of a specific design using programmable components that may include, for example, function generators, registers, arithmetic logic, and so forth. The processor system204can comprise circuitry, including one or more controllers and/or drivers, that can execute program code.

As just mentioned and as discussed further herein, the programmable logic202is circuitry that may be programmed to perform specified functions. As an example, the programmable logic202may be implemented as field programmable gate array (FPGA) circuitry. The programmable logic202may include an array of programmable circuit blocks. Examples of programmable circuit blocks within the programmable logic202include, but are not limited to, configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), digital signal processing blocks (DSPs), clock managers, and/or delay lock loops (DLLs).

The processor system204can be implemented as hardwired circuitry that is fabricated as part of programmable integrated circuit124. The processor system204may be implemented as, or include, any of a variety of different processor, e.g., controller, types. For example, the processor system204may be implemented as an individual processor, e.g., a single core capable of executing program code. In another example, the processor system204may be implemented as a multi-core processor. In still another example, the processor system204may include one or more cores, modules, co-processors, interfaces, and/or other resources. The processor system204may be implemented using any of a variety of different types of architectures. Example architectures that may be used to implement the processor system204may include, but are not limited to, an ARM processor architecture, an x86 processor architecture, RISC architectures, a GPU architecture, a mobile processor architecture, a DSP architecture, or other suitable architecture that is capable of executing computer-readable instructions or program code. In some embodiments, the processor system204may have both low power domains (LPDs) and full power domains (FPDs).

The programmable integrated circuit124receives and/or transmits data via the network interface132from and/or to the terrestrial connection point134. The programmable integrated circuit124also receives and/or transmits data via an RFT interface201from and/or to the RFT122. The interfaces132,201may be referred to as communication network interfaces and provide for the programmable integrated circuit124to communicate with the terrestrial connection point134and/or the RFT122via the baseband components128, respectively. The processor system204may include an operating system (OS), which is executable by a controller205. A portion of the operating system, known as the kernel, may comprise protocol stacks for translating commands and data between the applications and a device driver specific to the network interface devices. The protocol stacks may be implemented using Transmission Control Protocol/Internet Protocol (TCP/IP). The protocol stacks may support address resolution protocols (ARPs), Internet Control Message Protocol version 6 (ICMPv6), and/or IPv6 stateless autoconfiguration. As used herein, a driver may refer to executable computer programs that operate or control a particular device

The programmable logic202can include a frame filter206, a modulator208, and a direct memory access (DMA) controller210. The frame filter206, which is described in greater detail below with respect toFIG. 4, receives one or more data frames from the network interface132. As described herein, the frame filter206filters the data frames based on a data frame type. The data frame types may include high-speed data frames, protocol frames, and management frames. Within the present disclosure, high-speed data frames may refer to data frames transmitted up to rates of one hundred (100) gigabits per second (Gbit/s). Based on the data frame type, the frame filter206can filter the data frame to another network interface or the DMA controller210. In an example implementation, high-speed data frames can be filtered to the modulator208to modulate the data frame for radio frequency transmission. The modulator208can provide the modulated data frame to the RFT interface201.

For example, high-speed data frames can be diverted such that the high-speed data frames are provided to the modulator208and non-high-speed data frames, e.g., protocol frames, management frames, are written to the shared memory. As discussed herein, non-high-speed data frames may be provided to a kernel network stack212of the processor system204for processing. In an example implementation, a data frame is a specified unit of data and may comprise an Ethernet frame, e.g., a data link layer protocol data unit.

The frame filter206can filter high-speed data frames such that the high-speed data frames are provided to the modulator208. The modulator208modulates the high-speed data frame and provides the modulated high-speed data frame to the RFT interface201. The non-high-speed data frames can be filtered to the DMA controller210such that the filtered non-high-speed data frames can be written to the shared memory126without waiting for the processor system204to request the non-high-speed data frames.

As described in greater detail below, once the filtered data frames are provided to the shared memory126, the DMA controller210generates and transmits an interrupt signal to a media access control (MAC) driver214of the processor system204. The interrupt signal can cause the MAC driver214to temporarily stop executing a program such that the MAC driver214can allow an interrupt handler to execute. For instance, the interrupt handler can execute an appropriate interrupt service routine to handle the interrupt signal.

The DMA controller210can include preloaded memory addresses such that data included in the filtered data frames is written to the shared memory126according to the preloaded memory addresses. The preloaded memory addresses represent memory addresses corresponding to allocated memory space within the shared memory126for storing filtered data. The DMA controller210can include a pointer that references a memory location within the shared memory126. For example, once data has been written to the shared memory126, the pointer can be updated with the next memory location within the preloaded memory addresses.

The programmable logic202can also include a demodulator209and an aggregator211. The programmable logic202can receive data from the RFT122via the RFT interface201. The demodulator209demodulates the received data such that the demodulated data can be transmitted via a communication network. The demodulated data is provided to the aggregator211, and the aggregator211can aggregate multiple data streams of data units into a single data stream for transmission. The aggregated data is then provided to the network interface132for transmission.

As shown inFIG. 2, the processor system204can include the kernel network stack212, the MAC driver214, and a programmable logic driver216. After receiving the interrupt signal, the MAC driver214can access the shared memory126to retrieve the data of the filtered data frames. The MAC driver214can receive memory address data from the programmable logic driver216. The memory address data can be provided to the programmable logic driver216via the DMA controller210. The memory address data can represent the location of the data that was written to the shared memory126by the DMA controller210. Using the memory address data, the MAC driver214accesses the stored data and provides the accessed data to the kernel network stack212for processing.

FIG. 3Aillustrates an example filtered data frame300. As shown, the data frame300includes a destination address portion304, a source address portion306, a type portion308, and a data portion310. After the DMA controller210receives the data frame300from the frame filter206, the DMA controller210determines a memory address to write the data frame300to within the shared memory126. As shown inFIG. 3B, the DMA controller210modifies the data frame300by inserting a header portion314. In an example implementation, the header portion314is inserted before the destination address portion304. The header portion314can provide data specifying a length to a next header field and can be used by the MAC driver214in the event the MAC driver214cannot handle an interrupt prior to a next interrupt signal being generated. For example, the header portion314can include data representing a location of the next memory address that will store the next filtered data frame.

FIG. 4illustrates an example frame filter206according to an example implementation. As shown, the frame filter206can include filters402-1through402-P, where P is an integer greater than or equal to one. In an example implementation, the filters402-1through402-P may comprise 512-bit comparators. The comparators are configurable such that the comparators can compare specific bits of the received data frames within the 512-bit range. Based on the comparison of the comparator, the filters402-1through402-P output filter matches to an inverse multiplexer404. The comparators can determine a data frame type based on the comparison of the respective bits with the filters. The filter matches can be concatenated to form an address provided to the inverse multiplexer404. As shown, the multiplexer404may comprise an inverse multiplexer. The input data frame is then forwarded to either the modulator208if the input data frame is a high-speed data frame or to the DMA controller210is a non-high-speed data frame.

The comparators can implement Boolean logic to compare the bits of the data frame to configurable filter values and configurable filter masks. The filter values and filter masks may be set based on the specific implementation of the filter frame206such that a data frame is diverted to the desired destination. For instance, each bit of the data frame may be compared to a filter value and a filter mask to generate a bit match value. The filter match output by the comparators402-1through402-P may be a logical AND output of the bit match values and the bits of the data frame.

FIG. 5illustrates an example process500for filtering a data frame, such as a data frame received from the network interface132. Blocks of the process500can be executed by one or more of the components of the gateway120. For example, the blocks of the process500can be executed by one or more components of the programmable logic202.

The process500begins at block505in which a determination is made whether data has been received at the network interface132. As described above, the data comprises a data link layer protocol data unit. If no data has been received, the process500returns to block505. If data has been received, the data is provided to the frame filter206at block510. At block515, a determination is made of whether the data is a high-speed data frame at the frame filter206. If the data is a high-speed data frame, the data is forwarded to the modulator208at block520, and the process500ends.

If the data is not a high-speed data frame, the data is transmitted to the DMA controller210at block525. As discussed above, the DMA controller210receives data from the frame filter206and includes the header portion214for writing the data to the shared memory126. At block530, the DMA controller210writes the data to the shared memory126and generates an interrupt signal that is sent to the MAC driver214, and the process500transitions to process600described below. The DMA controller210can write the shared memory126based on preloaded memory addresses that represent memory addresses corresponding to allocated memory space in the shared memory126.

FIG. 6illustrates an example process600for processing a data frame. Blocks of the process600can be executed by one or more of the components of the gateway120. For example, the blocks of the process600can be executed by one or more components of the processor system204.

The process600begins at block605in which the MAC driver214retrieves the data from the shared memory126and provides the data to the kernel network stack212for processing. The MAC driver214can retrieve the data from the shared memory126after receiving the interrupt signal. For example, the MAC driver214can initiate an interrupt handler in response to the interrupt signal such that current processes are suspended, and the MAC driver214can retrieve the stored data frame. The MAC driver214can initially access the data based on data received from the programmable logic driver216. For instance, the programmable logic driver216can receive the memory address of the stored data from the DMA controller210.

At block610, a determination is made whether additional data has been written to the shared memory126. If there is additional data stored, the process600returns to block605. The MAC driver214can determine there is additional data based on the receipt of additional interrupt signals and/or control signals provided by the programmable logic driver216. The MAC driver214may use the header portion314to determine the memory location of the next data frame stored in the shared memory126. If there is no additional data stored, the process600ends after block610.

FIG. 7illustrates an example process700for processing a data frame from a network stack, such as the kernel network stack212. Blocks of the process700can be executed by one or more of the components of the gateway120. For example, the blocks of the process700can be executed by one or more components of the processor system204.

The process700begins at block705in which a determination is made whether data, e.g., a data frame, has been received from the kernel network stack212. Once the kernel network stack212has processed a received data frame, the kernel network stack212can provide a data frame to the MAC driver214in response to the processed data frame. The MAC driver214can monitor whether data has been received from the kernel network stack212. If no data has been received, the process700returns to block705. If data has been received from the kernel network stack212, the MAC driver214writes the data to the shared memory126at block710.

At block715, the programmable logic driver216instructs the DMA controller210to retrieve data from the shared memory126. Once the MAC driver214writes the data to the shared memory126, the MAC driver214sends a signal to the programmable logic driver216indicating data can be retrieved. The signal can include a memory location within the shared memory126of where the data was written. In response to receiving the signal, the programmable logic driver216sends an instruction to the DMA controller210to retrieve data from the shared memory126at the memory location. At block720, a determination is made whether a data retrieve completion interrupt has been received from the DMA controller210. Once the MAC driver214sends the signal to the programmable logic driver, the MAC driver214can enter a monitoring state. For example, the MAC driver214can monitor whether the DMA controller210has generated and sent a data pull complete interrupt signal. The DMA controller210can generate the data pull complete interrupt signal once the DMA controller210has completed retrieving the data from the shared memory126. If the data pull complete interrupt signal has not been received, the process700returns to block725. Otherwise, the process700transitions to process800described below.

FIG. 8illustrates an example process800for providing retrieved data frames to the network interface132. Blocks of the process800can be executed by one or more of the components of the gateway120. For example, the blocks of the process800can be executed by one or more components of the programmable logic202.

The process800begins at block805in which the DMA controller210sends the retrieved data to the aggregator211using memory mapped addressing. Memory mapped addressing uses the same address space to address both the shared memory126and input/output (I/O) devices, e.g., network interface132. At block810, the data is provided to the network interface132by the aggregator211. The aggregator211can aggregate multiple data units received from the DMA controller210prior to providing aggregated data to the network interface132. The process800ends after block810.