Semiconductor device including bipolar transistor with step impurity profile having low and high concentration emitter regions

In a semiconductor device including a bipolar transistor having a base region formed in a collector region, and an emitter region formed in the base region, the emitter region comprises a high concentration region in contact with the base region, and a low concentration region provided between the base region and the high concentration region. The low concentration region is formed by introducing an impurity with a mask including a large opening. In addition, the high concentration region is formed by introducing an impurity with a mask including a small opening.

FIELD OF THE INVENTION 
This invention relates to a semiconductor device including a bipolar 
transistor and a method of manufacturing the same. 
BACKGROUND OF THE INVENTION 
FIGS. 9A and 9B are a plan view and a cross sectional view of an NPN type 
bipolar transistor (Bi-Tr) as a portion of a conventional semiconductor 
device, e.g., Bi-CMOS, respectively. This Bi-Tr is manufactured as 
follows. Namely, an N.sup.+ type buried layer 2 is formed on a P-type Si 
substrate 1 and an N-type collector region 3 is grown thereon. A P-type 
impurity (B or BF.sub.2, etc.) is ion-implanted into a region where the 
base is to be formed of the collector region 3. Thereafter, using a resist 
mark, an N-type impurity (e.g., As) is ion-implanted only into a region 
where the emitter is to be formed in the region where the base is to be 
formed. Heat treatment is then conducted. As a result, a P-type base 
region 4 is formed within the N-type collector region 3, and an N-type 
emitter region 5 is formed within the P-type base region 4. Thus, a Bi-Tr 
is provided. 
There are instances where a reverse bias may be applied to the junction 
portion between the emitter region 5 and the base region 4 of the Bi-Tr. 
Application of such a reverse bias leads to the difficulty that the 
emitter-base junction breakdown voltage is lowered and the current gain 
h.sub.FE is also lowered, resulting in considerably deteriorated device 
characteristics. 
SUMMARY OF THE INVENTION 
This invention has been made in view of the above, and its object is to 
provide a semiconductor device constructed so that the device 
characteristic is not lowered even when a reverse bias is applied to the 
junction portion between the emitter region and the base region, and a 
method of manufacturing such a semiconductor device. 
In the semiconductor device of this invention, the emitter region of the 
bipolar transistor is formed by two regions of the high concentration 
region and the low concentration region, and the interface between the 
high concentration region and the base region is surrounded by the low 
concentration region. Since such a structure is employed, the electric 
field at the edge portion of the emitter region is relaxed or reduced. 
Thus, even when a reverse bias is applied to the base-emitter junction 
portion, there is no possibility that the junction breakdown voltage and 
the current gain are lowered. 
In accordance with a manufacturing method according to this invention, 
there is provided a semiconductor device including a bipolar transistor of 
a structure such that the emitter region is constituted by two regions of 
the high concentration region and the low concentration region, and that 
the low concentration region surrounds the interface between the high 
concentration region and the base region, i.e., a bipolar transistor which 
performs the above-mentioned action. 
In accordance with this invention, even when a reverse bias is applied to 
the portion across the emitter region and the base region of the bipolar 
transistor, lowering of the device characteristic can be prevented.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIGS. 1A and 1B are a plan view and a cross sectional view of an NPN type 
Bi-Tr of a semiconductor device according to this invention, respectively. 
In this Bi-Tr, an N-type collector region 3 is formed on the side of the 
surface of an N.sup.+ buried layer 2 formed on a P-type semiconductor 
substrate 1. A P-type base region 4 is formed on the side of the surface 
of the collector region 3. Furthermore, an N-type emitter region 5 is 
formed on the side of the surface of the base region 4. This emitter 
region 5 is composed of two sections. One is a high concentration region 
(N.sup.+)5a having a small lateral cross section and a deep depth, and the 
other is a low concentration region (N.sup.-)5b having a large lateral 
cross section and a shallow depth. 
In the Bi-Tr of such a structure, an N-type impurity diffused region (5b) 
having a low concentration is formed at the edge portion of a so-called 
conventional emitter region (5a) formed by N-type impurity having a high 
concentration. Thus, an electric field at the edge portion is relaxed. 
Even when a reverse bias is applied to the junction portion between the 
base and the emitter, the junction breakdown voltage and the current gain 
are not lowered. Thus, a high reliability device is provided. 
The semiconductor device shown in FIGS. 1A and 1B is manufactured as 
follows. 
Namely, as shown in FIG. 2, e.g., Sb is ion-planted into a P-type Si 
substrate 1 (e.g., 2.OMEGA..multidot.cm) under the condition of 100 KeV, 
1.times.10.sup.15 cm.sup.-2. A thermal process step under the condition of 
1100.degree. C., 60 minutes is implemented. An N.sup.+ buried layer 2 is 
thus formed. Thereafter, the surface of the Si substrate 1 is epitaxially 
grown in the atmosphere including SiH.sub.2 Cl.sub.2. An N-type collector 
region 3 is thus formed. Then, device isolation regions 7, 7 are formed by 
LOCOS process. Thereafter, a silicon oxide film 8 having a thickness of 
approximately several ten to several hundred .ANG. is formed by an argon 
diluted oxidation process. Thereafter, a P-type impurity (e.g., boron or 
BF.sub.2) 6 is ion-implanted into a region where the base is to be formed 
under the condition of 25 KeV, 5.times.10.sup.13 cm.sup.-2. 
Subsequently, process steps shown in FIGS. 3A to 3D are implemented in 
succession. These FIGURES show only the surface portion of the substrate 
shown in FIG. 2. As seen from FIG. 3A, a silicon oxide film 9 is deposited 
on the oxide film 8 in a manner in close contact therewith by a CVD 
process so that its thickness is equal to, e.g., 1,000 .ANG.. Then, a 
resist (not shown) is coated on the silicon oxide film 9 in a manner in 
close contact therewith. By removing the portion of the resist, above a 
region where the emitter is to be formed, an opening is provided. Using 
this resist as a mask, by CDE (Chemical Dry Etching), openings 9a, 8a are 
provided in the silicon oxide films 9, 8, respectively. Then, that resist 
is exfoliated. Thus, the state shown in FIG. 3A results. Thereafter, using 
the silicon oxide films 9, 8 as a mask, an N-type impurity (e.g., As) 11 
is densely ion-implanted through the openings 9a, 8a under the condition 
of 40 KeV, 5.times.10.sup.15 cm.sup.-2 so as to result in the state of 
high concentration. 
Then, as seen from FIG. 3B, the openings 9a, 8a of the silicon oxide films 
9, 8 are widened, e.g., by 1,000 .ANG. by wet etching process. Thus, 
larger openings 9b, 8b are newly provided. 
Then, as seen from FIG. 3C, an N-type impurity (e.g., P) 12 is sparsely 
ion-implanted under the condition of 20 KeV, 3.times.10.sup.13 cm.sup.-2 
so as to result in the state of low concentration. 
Subsequently, as seen from FIG. 3D, a thermal diffusion process, e.g., a 
process having a temperature of 900.degree. C. and N.sub.2 annealing time 
of 60 minutes is implemented. Thus, an emitter region 5 including an 
N-type high concentration region 5a and an N-type low concentration region 
5b is formed within the P-type base region 4. 
At times subsequent thereto, in the same manner as in widely used 
semiconductor devices, metallization process and passivation process are 
implemented in succession. Thus, a semiconductor device is provided. 
A semiconductor device according to this invention may be manufactured by 
various methods described below in addition to the above-described method. 
Namely, a first modification will be first described. After undergoing the 
process shown in FIG. 2, as seen from FIG. 4A, a resist film 21 is coated 
on the upper surface of the oxide film 8 in a manner in close contact 
therewith. The portion, above the region where the emitter is to be 
formed, of the resist film 21 is removed. An opening 21a is thus provided. 
Then, an N-type (e.g., As) is densely ion-implanted under the condition of 
40 KeV, 5.times.10.sup.15 cm.sup.-2 so as to result in a state of high 
concentration. 
Then, as seen from FIG. 4B, the resist film 21 is etched by a wet etching 
process to further widen the opening 21a by 1,000 .ANG. to newly form a 
larger opening 21b. 
Then, as seen from FIG. 4C, an N-type impurity (e.g., P) 12 is sparsely ion 
implanted under the condition of 20 KeV, 3.times.10.sup.13 cm.sup.-2 so as 
to result in the state of low concentration. 
Subsequently, as seen from FIG. 4D, the entirety of the resist film 21 is 
exfoliated. A thermal process similar to the thermal process in FIG. 3D is 
implemented. Thus, an N-type emitter region 5 including a high 
concentration region 5a and a low concentration region 5b is formed within 
the P-type base region 4. 
Thereafter, a metallization process and a passivation process are 
implemented. Thus, a semiconductor device is provided. 
A second modified embodiment will now be described. 
After the process step in FIG. 2 and the process in FIG. 4A, the entirety 
of the resist film 21 is exfoliated. 
Then, as shown in FIG. 5, a resist film 24 is coated on the oxide film 8. 
An opening 24a having substantially the same dimension as that of the 
opening 21b shown in FIG. 4B is provided in the resist film 24. 
Thereafter, an N-type impurity (e.g., P) 12 is sparsely ion-implanted 
under the condition of 20 KeV, 3.times.10.sup.13 cm.sup.-2 so as to result 
in a state of low concentration. 
At times subsequent thereto, a semiconductor device is provided by 
executing the same process as that in FIG. 4D, the metallization process 
and the passivation process. 
A third modified embodiment will now be described. 
After the process step in FIG. 2, as seen from FIG. 6A, large openings 8b, 
9b are provided in the oxide films 8, 9, respectively, and an N-type 
impurity 12 is introduced sparsely through these openings 8b, 9b so as to 
result in a state of low concentration. Thereafter, as seen from FIG. 6B, 
a polycrystalline silicon oxide film 27 is deposited on the oxide films 8, 
9 in a manner in close contact therewith so that its thickness is equal 
to, e.g., 1,000 .ANG.. 
Then, as seen from FIG. 6C, a polycrystalline silicon oxide film 27a is 
left only within the openings 8b, 9b by anisotropic etching to form an 
opening 27b. Thereby, an opening 27b is formed. 
Then, as seen from FIG. 6D, using the polycrystalline silicon oxide film 
27a as a mask, an N-type impurity (e.g., P) 11 is densely ion-implanted 
under the condition of 40 KeV, 5.times.10.sup.15 cm.sup.-2 so as to result 
in the state of high concentration. 
Then, as seen from FIG. 6E, the remaining polycrystalline silicon oxide 
film 27a is removed by a dry etching process. 
Subsequently, process steps similar to those shown in FIG. 3D, i.e., the 
thermal process step, the metallization process step, and the passivation 
process step will be carried out. 
In the abovementioned third modified embodiment, a SiO.sub.2 film can be 
used instead of the polycrystalline silicon film 27. In this case, it is 
free that the remaining SiO.sub.2 film in the openings 8b, 9b may be 
either removed or left as it is. 
A fourth modified embodiment will now be described. 
After the process step shown in FIG. 2, as seen from FIG. 7A, a resist film 
29 is coated on the oxide film 8 in a manner in close contact therewith. 
Only the portion, above the region where the emitter is to be formed, of 
the resist film 29 is removed to provide a large opening 29a. Thereafter, 
an N-type impurity (e.g., P) 12 is sparsely ion-implanted through the 
opening 29a under the condition of 20 KeV, 3.times.10.sup.13 cm.sup.-2 so 
as to result in a state of low concentration. 
Then, as seen from FIG. 7B, after the entirety of the resist film 29 is 
exfoliated, a resist film 30 is coated. The portion, above the region 
where the high concentration region is to be formed, of the resist film 30 
is removed to provide a small opening 30a. Thereafter, an N-type impurity 
(e.g., As) 11 is densely ion-implanted under the condition of 40 KeV, 
5.times.10.sup.15 cm.sup.-2 so as to result in a state of high 
concentration. 
Then, as seen from FIG. 7C, the entirety of the resist film 30 is 
exfoliated. Thereafter, the thermal process, the metallization process and 
the passivation process are implemented. 
Finally, a fifth embodiment will be described. 
After the process step shown in FIG. 2, as seen from FIG. 8A, a silicon 
oxide film 32 is deposited on the oxide film 8 in a manner in close 
contact therewith by a CVD process so that its thickness is equal to, 
e.g., 1,000 .ANG.. A resist (not shown) is coated on the oxide film 32 in 
a manner in close contact therewith. Thereafter, only the portion, above 
the region where the emitter is to be formed, of the resist is removed to 
provide an opening. 
Then, using this opening as a mask, large openings 32a, 8a are provided in 
the silicon oxide film 32, 8 by CDE process, respectively. Thereafter, an 
N-type impurity (e.g., P) 12 is sparsely ion-implanted through these 
openings 32a, 8a under the condition of 20 KeV, 3.times.10.sup.13 
cm.sup.-2 so as to result in a state of low concentration. 
Then, as seen from FIG. 8B, after the oxide films 32, 8 are removed by wet 
etching process, another oxide film 34 is deposited by a CVD process so 
that its thickness is equal to 3,000 .ANG.. Thereafter, a second resist 
film 35 is coated on the oxide film 34. An exposure process is implemented 
thereto to form an opening 35a. 
Then, as seen from FIG. 8C, an opening 34a is provided in the oxide film 34 
by CDE process. Thereafter, the entirety of the resist 35 is exfoliated. 
Then, as seen from FIG. 8D, a polycrystalline silicon film 37 including an 
N-type impurity (e.g., P) is deposited on the silicon oxide film 34 in a 
manner in contact therewith so that its thickness is equal to, e.g., 2,000 
.ANG.. 
Then, as seen from FIG. 8E, the heat treatment process, the metallization 
process and the passivation process are implemented. In the 
above-mentioned heat treatment process, the N-type impurity in the 
polycrystalline silicon film 37 is diffused. A high concentration region 
5a is thus formed. 
As a mask in ion-implanting the N type impurity, a nitride film may be used 
instead of the above-mentioned silicon oxide film and resist film. 
As the N-type impurity, Sb may be used instead of the above-mentioned P and 
As. 
While a Bi-Tr including NPN transistor has been described above, Bi-Tr 
including PNP transistor may be obtained in the same manner as stated 
above by allowing the conductivity to be opposite to the above. Another 
embodiment of the present invention is shown in FIG. 1C. 
FIGS. 10 to 11B show the advantageous effects of the present invention. 
Especially, it will be understood from FIG. 11A that the emitter-base 
junction characteristics of the semiconductor device according to the 
present invention does not practically change even if the device is put 
into reverse bias stress conditions (V.sub.EBO= 5V, 1,000 sec), while the 
characteristics of the device according to the background art change 
widely. Furthermore, it will be understood from FIG. 11B that the current 
gain characteristics of the device according to the present invention 
changes only slightly if the device is put into the aforementioned 
conditions, while the characteristics of the device according to the 
background art changes greatly.