SWITCHING CONTROL CIRCUIT AND POWER SUPPLY CIRCUIT

A switching control circuit including: a command value output circuit that respectively outputs a command value indicating a first time period, and command values indicating second and third time periods, in first and second load states; a first driver circuit that, in the first load state, turns on a first transistor after a first inductor current reaches a first value, and subsequently turns off the first transistor when the first time period has elapsed; and a second driver circuit that, in the second load state, turns on a second transistor when a second inductor current reaches a second value, and subsequently turns off the second transistor when the third time period has elapsed. The first driver circuit, in the second load state, turns on the first transistor when the first inductor current reaches the first value, and subsequently turns off the first transistor when the second time period has elapsed.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority pursuant to 35 U.S.C. § 119 from Japanese patent application number 2023-053365 filed on Mar. 29, 2023, the entire disclosure of which is hereby incorporated by reference herein.

BACKGROUND

Technical Field

The present disclosure relates to a switching control circuit and a power supply circuit.

Description of the Related Art

A typical power factor correction circuit (hereinafter, referred to as power factor correction (PFC) circuit) configured to operate in a critical mode improves a power factor by shaping a waveform of peak values of an inductor current flowing through an inductor into a waveform similar to that of a rectified voltage obtained by rectifying an alternating current (AC) voltage. In this case, for example, a plurality of boost chopper circuits (e.g., two systems) may be configured as one PFC circuit, to thereby perform a parallel operation (for Japanese example, patent application publications Nos. 2022-041912, 2018-207732, 2020-127287).

In a PFC circuit that performs an interleaved operation, there are cases where when the load is in a light load state, only the boost chopper circuit of one system is operated, and when the load enters a heavy load state, the boost chopper circuits of two systems are operated in parallel.

However, in operating the boost chopper circuits of two systems in parallel, when the boost chopper circuit having been stopped is started to operate in the same state as in the chopper circuit having been already operating, the output current to the load may increase, so that an output voltage may rise.

Such a rise in the voltage is suppressed by modifying the operating state so that the voltage will reach a desired value under the condition that the two systems are operating with a voltage control system. However, until a steady state is brought about, the amplitude of the input current increases and decreases, which may cause a disturbance of the input current.

SUMMARY

A first aspect of the present disclosure is a switching control circuit for a power supply circuit that generates an output voltage at a target level from an alternating current (AC) voltage inputted thereto, the power supply circuit including a first inductor and a second inductor, the first and second inductors being configured to receive a voltage corresponding to the AC voltage, a first transistor configured to control a first inductor current flowing through the first inductor, and a second transistor configured to control a second inductor current flowing through the second inductor, the switching control circuit being configured to control switching of the first transistor and the second transistor, the switching control circuit comprising: a command value output circuit configured to, when a current value of a load current flowing through a load of the power supply circuit is smaller than a first predetermined value and the load is in a first state, output a first command value indicating a first time period corresponding to the output voltage, and when the current value of the load current is larger than a second predetermined value and the load is in a second state, output a second command value indicating a second time period corresponding to the output voltage, and a third command value indicating a third time period; a first driver circuit configured to, when the load is in the first state, receive the first command value, turn on the first transistor, after the first inductor current reaches a first value, and turn off the first transistor, in response to the first time period based on the first command value having elapsed since the first transistor is turned on; and a second driver circuit configured to, when the load is in the second state, receive the third command value, turn on the second transistor, in response to the second inductor current reaching a second value, and turn off the second transistor, in response to the third time period based on the third command value having elapsed since the second transistor is turned on, wherein the first driver circuit is further configured to, when the load is in the second state, receive the second command value, turn on the first transistor, in response to the first inductor current reaching the first value, and turn off the first transistor, in response to the second time period based on the second command value having elapsed since the first transistor is turned on.

A second aspect of the present disclosure is a switching control circuit for a power supply circuit that generates an output voltage at a target level from an alternating current (AC) voltage inputted thereto, the power supply circuit including a first inductor and a plurality of second inductors, each of the first and second inductors being configured to receive a voltage corresponding to the AC voltage, and a first transistor and a plurality of second transistors configured to respectively control first and a plurality of inductor currents flowing through the first inductor and the plurality of second inductors, the switching control circuit being configured to control switching of the first and second transistors, the switching control circuit comprising: a command value output circuit configured to, when a current value of a load current flowing through a load of the power supply circuit is smaller than a first predetermined value and the load is in a first state, output a first command value indicating a first time period corresponding to the output voltage, and when the current value of the load current is larger than a second predetermined value and the load is in a second state, output a second command value indicating a second time period corresponding to the output voltage and a third command value indicating a third time period; a first driver circuit configured to, when the load is in the first state, receive the first command value, turn on the first transistor in response to the first inductor current reaching a first value, and turn off the first transistor, in response to the first time period based on the first command value having elapsed since the first transistor is turned on, and a second driver circuit configured to, when the load is in the second state, receive the third command value, turn on the plurality of second transistors, after each of the plurality of inductor currents reaching a second value, and turn off the plurality of second transistors, in response to the third time period based on the third command value having elapsed since the plurality of second transistors are turned on, wherein the first driver circuit is further configured to, when the load is in the second state, receive the second command value, turn on the first transistor, in response to the first inductor current reaching the first value, and turn off the first transistor, in response to the second time period based on the second command value having elapsed since the first transistor is turned on.

A third aspect of the present disclosure is a power supply circuit configured to generate an output voltage at a target level from an alternating current (AC) voltage inputted thereto, the power supply circuit comprising: a first inductor and a second conductor, the first and second inductors being configured to receive a voltage corresponding to the AC voltage; a first transistor configured to control a first inductor current flowing through the first inductor; a second transistor configured to control a second inductor current flowing through the second inductor; a switching control circuit configured to control switching of the first transistor and the second transistor, the switching control circuit including a command value output circuit configured to, when a current value of a load current flowing through a load of the power supply circuit is smaller than a first predetermined value and the load is in a first state, output a first command value indicating a first time period corresponding to the output voltage, and when the current value of the load current is larger than a second predetermined value and the load is in a second state, output a second command value indicating a second time period corresponding to the output voltage, and a third command value indicating a third time period; a first driver circuit configured to, when the load is in the first state, receive the first command value, turn on the first transistor, in response to the first inductor current reaching a first value, and turn off the first transistor, in response to the first time period based on the first command value having elapse since the first transistor is turned on; and a second driver circuit configured to, when the load is in the second state, receive the third command value, turn on the second transistor, after the second inductor current reaches a second value, and turn off the second transistor, in response to the third time period based on the third command value having elapsed since the second transistor is turned on, wherein the first driver circuit is further configured to, when the load is in the second state, receive the second command value, turn on the first transistor, in response to the first inductor current reaching the first value, and turn off the first transistor, in response to the second time period based on the second command value having elapsed since the first transistor is turned on.

DETAILED DESCRIPTION

At least following matters will become apparent from descriptions of the present description and the accompanying drawings. It is assumed, hereinafter, that a “circuit” according to an embodiment of the present disclosure includes not only an analog circuit and a logic circuit of a wired logic type, but also a functional block (or means) that is included in a digital signal processor (DSP), a microcomputer, or the like, and that is capable of executing digital arithmetic processing.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The same or equivalent constituent elements, members, and the like illustrated in the drawings are given the same reference numerals, and repetitive description is omitted as appropriate.

Embodiments

FIG.1is a diagram illustrating a configuration of an AC-DC converter10which is an embodiment of the present disclosure. The AC-DC converter10is a boost power factor correction (PFC) circuit to generate an output voltage Vout at a target level from an alternating-current (AC) voltage Vac of a commercial power supply.

The AC-DC converter10includes a full-wave rectifier circuit20, capacitors21,22, transformers23a,23b, diodes24a,24b, a power factor correction IC25, NMOS transistors26a,26b, and resistors30,31. Note that the AC-DC converter10corresponds to a “power supply circuit”.

The full-wave rectifier circuit20full-wave rectifies the predetermined AC voltage Vac inputted thereto, and outputs a resultant voltage as an input voltage Vrec to a capacitor21, a main coil L1a(described later) of a transformer23a, and a main coil L2a(described later) of a transformer23b. Note that the AC voltage Vac is a voltage with an effective value in a range of 100 to 240 V and a frequency in a range of 50 to 60 Hz, for example. Hereinafter, in an embodiment of the present disclosure, voltages basically refer to a difference in potential relative to a reference point (GND inFIG.1), however, the AC voltage Vac refers to a voltage between terminals.

The capacitor21smooths the input voltage Vrec, and the capacitor22is an element to be charged with the output voltages of two boost chopper circuits. The main coil L1aof the transformer23a, the diode24a, and the NMOS transistor26aconfigure a first boost chopper circuit together with the capacitor22. Further, the main coil L2aof the transformer23b, the diode24b, and the NMOS transistor26bconfigure a second boost chopper circuit together with the capacitor22. Thus, the charge voltage of the capacitor22results in the direct current (DC) output voltage Vout.

The transformer23aincludes the main coil L1aand an auxiliary coil L1bmagnetically coupled to the main coil L1a. Note that the auxiliary coil L1baccording to an embodiment of the present disclosure is formed by winding a wire such that the voltage generated at the auxiliary coil L1bhas a polarity opposite to that of the voltage generated at the main coil L1a. Then, a voltage Vzcd1generated at the auxiliary coil L1bis applied to a terminal ZCD1of the power factor correction IC25. Further, it is assumed that when the inductor current IL1flows through the main coil L1ain the direction of an arrow, the direction in which the inductor current IL1flows is a positive direction, and when the inductor current IL1flows therethrough in a direction opposite to the direction of the arrow, the direction in which the inductor current IL1flows is a negative direction. Further, when the current value of the inductor current IL1reaches substantially zero, the voltage value of the voltage Vzcd1reaches a first predetermined voltage value. Note that the main coil L1acorresponds to a “first inductor”.

Similarly, the transformer23bincludes the main coil L2aand an auxiliary coil L2bmagnetically coupled to the main coil L2a. Note that the auxiliary coil L2baccording to an embodiment of the present disclosure is formed by winding a wire such that the voltage generated at the auxiliary coil L2bhas a polarity opposite to that of the voltage generated at the main coil L2a. Then, a voltage Vzcd2generated at the auxiliary coil L2bis applied to a terminal ZCD2of the power factor correction IC25. Further, it is assumed that when the inductor current IL2flows through the main coil L2ain the direction of an arrow, the direction in which the inductor current IL2flows is a positive direction, and when the inductor current IL2flows in the direction opposite to the direction of the arrow, the direction in which the inductor current IL2flows is a negative direction. Further, when the current value of the inductor current IL2reaches substantially zero, the voltage value of the voltage Vzcd2reaches a second predetermined voltage value. Note that the main coil L2acorresponds to a “second inductor”.

The power factor correction IC25is an integrated circuit to control switching of the NMOS transistors26a,26bsuch that the level of the output voltage Vout reaches a target level (e.g., 400 V) while improving the input power factor of the AC-DC converter10. Specifically, the power factor correction IC25drives the NMOS transistor26a, based on the inductor current IL1flowing through the main coil L1aand the output voltage Vout. Note that the inductor current IL1corresponds to a “first inductor current”.

Further, the power factor correction IC25drives the NMOS transistor26b, based on the inductor current IL2flowing through the main coil L2aand the ON period of the NMOS transistor26a. The power factor correction IC25has terminals ZCD1, ZCD2, FB, OUT1, OUT2, and CMD, and the details of the power factor correction IC25will be described later. Note that, in an embodiment of the present disclosure, other terminals (e.g., a ground terminal) other than the terminal ZCD1and the like of the power factor correction IC25are omitted for convenience. Further, the inductor current IL2corresponds to a “second inductor current”.

The NMOS transistors26a,26bare power transistors to control power to a load11of the AC-DC converter10. Note that in an embodiment of the present disclosure, the NMOS transistors26a,26bare n-type metal oxide semiconductor (NMOS) transistors, but they are not limited thereto, and may be other switching elements such as bipolar transistors or the like, for example. Further, the gate electrode of the NMOS transistor26ais coupled to the terminal OUT1, and the gate electrode of the NMOS transistor26bis coupled to the terminal OUT2. Note that the NMOS transistor26acorresponds to a “first transistor”, and the NMOS transistor26bcorresponds to a “second transistor”.

The resistors30,31configure a voltage divider circuit to divide the output voltage Vout, to thereby generate a feedback voltage Vfb that is used in switching the NMOS transistors26a,26b. Note that the feedback voltage Vfb generated at the node at which the resistors30and31are coupled is applied to the terminal FB.

A load detection circuit (LDET)12detects the state of the load11, and outputs a signal cmd of a low level (hereinafter, low or low level) when the load11is in a light load state (i.e., “first state”), based on a load current Iload flowing through the load11. Meanwhile, the load detection circuit12outputs a signal cmd at a high level (hereinafter, referred to as high or high level) when the load11is in a heavy load state (i.e., “second state”).

Note that in an embodiment of the present disclosure, the “light load” indicates, for example, that the current value of the load current Iload flowing through the load11is smaller than a first predetermined value, and the “heavy load” indicates that the current value of the load current Iload flowing through the load11is larger a second predetermined value. Further, the first predetermined value and the second predetermined value may be the same or different, for example, both the first predetermined value and the second predetermined value may be, for example, 5A, or the first predetermined value may be, for example, 1A and the second predetermined value may be, for example, 5A. Further, the phrase “the load11is in the light load state” refers to the case in which the state of the load11is smaller than a “first load”, and “the load11is in the heavy load state” refers to the case in which the state of the load11is greater than a “second load”. Further, the “first load” corresponds to the light load, and the “second load” corresponds to the heavy load. Furthermore, the load detection circuit12corresponds to a “first load detection circuit”.

==Configuration of Power Factor Correction IC25==

FIG.2is a diagram illustrating an example of the power factor correction IC25. The power factor correction IC25includes analog-to-digital converters (ADCs: AD converters)40to42, a switching control circuit43, and buffer circuits44,45. Note that the switching control circuit43includes a digital circuit.

The AD converter40converts the voltage Vzcd1into a digital value, the AD converter41converts the voltage Vzcd2into a digital value, and the AD converter42converts the feedback voltage Vfb into a digital value.

The switching control circuit43outputs driving signals Vq1, Vq2to drive the NMOS transistors26a,26b, based on the feedback voltage Vfb and the voltages Vzcd1and Vzcd2respectively corresponding to the inductor currents IL1and IL2. The switching control circuit43is a digital circuit configured with a logic circuit of a wired logic type to execute various arithmetic calculations, and includes, for example, a logic gate, a flip-flop, and a memory. However, the switching control circuit43may be a digital signal processor (DSP) or a microcomputer. Note that details of the switching control circuit43will be described later.

The buffer circuit44is a driver circuit to drive the NMOS transistor26ain response to the driving signal Vq1. Specifically, the buffer circuit44turns on the NMOS transistor26a, in response to the driving signal Vq1going high, and turns off the NMOS transistor26a, in response to the driving signal Vq1going low.

Similarly, the buffer circuit45is a driver circuit to drive the NMOS transistor26b, in response to the driving signal Vq2. Specifically, the buffer circuit45turns on the NMOS transistor26b, in response to the driving signal Vq2going high, and turns off the NMOS transistor26b, in response to the driving signal Vq2going low.

==Configuration of Switching Control Circuit43a==

FIG.3illustrates an example of a switching control circuit43awhich is an embodiment of the switching control circuit43.

The switching control circuit43aoutputs the driving signals Vq1, Vq2, based on the inductor currents IL1, IL2, the feedback voltage Vfb, and the signal cmd. Specifically, when the load11is in the light load state; the inductor current IL1decreases to substantially zero; and the voltage value of the voltage Vzcd1corresponding to the inductor current IL1reaches the first predetermined voltage, the switching control circuit43aoutputs the driving signal Vq1to turn on the NMOS transistor26a.

Then, after a lapse of an ON period Vy that is ON period Vx based on the feedback voltage Vfb, the switching control circuit43aoutputs the driving signal Vq1to turn off the NMOS transistor26a. Note that when the load11is in the light load state, the switching control circuit43aoutputs the driving signal Vq2to turn off the NMOS transistor26b.

Meanwhile, when the load11is in the heavy load state; the inductor current IL1decreases to substantially zero; and the voltage value of the voltage Vzcd1corresponding to the inductor current IL1reaches the first predetermined voltage value, the switching control circuit43aoutputs the driving signal Vq1to turn on the NMOS transistor26a. Further, when the load11is in the heavy load state; the inductor current IL2decreases to substantially zero; and the voltage value of the voltage Vzcd2corresponding to the inductor current IL2reaches the second predetermined voltage value, the switching control circuit43aoutputs the driving signal Vq2to turn on the NMOS transistor26b. Then, after a lapse of the ON periods Vy, Vz, obtained by multiplying the ON period Vx by a ratio (e.g., 0.5 in an embodiment of the present disclosure) for the two boost chopper circuits to supply power to the load11in a balanced manner, the switching control circuit43aoutputs the driving signals Vq1, Vq2to turn off the NMOS transistors26a,26b, respectively. The switching control circuit43aincludes a command value output circuit100and driving signal output circuits120,140.

The command value output circuit100outputs command values indicating the ON periods Vy, Vz of the NMOS transistors26a,26b, based on the signal cmd indicating the state of the load11and the feedback voltage Vfb. Specifically, when the load11is in the light load state, the command value output circuit100outputs the command value indicating the ON period Vy that is equal to the ON period Vx corresponding to the feedback voltage Vfb. Further, when the load11is in the light load state, the command value output circuit100outputs the command value indicating the ON period Vz of “0” so as to output the driving signal Vq2to turn off the NMOS transistor26b.

Meanwhile, when the load11is in the heavy load state, the command value output circuit100outputs the command values indicating the ON periods Vy, Vz according to the feedback voltage Vfb (i.e., the command values indicating ON periods Vy, Vz obtained by multiplying the ON period Vx by the ratio for the two boost chopper circuits to supply power to the load11in a balanced manner). The command value output circuit100includes subtractor circuits102,108, a voltage regulator circuit104, a ratio output circuit106, and multiplier circuits110,112. Note that the “command value” includes, for example, a voltage value, a digital value, and the like, and hereinafter, for example, the “command value indicating the ON period Vx” may be referred to as “ON period Vx”. The same applies to the command values indicating ON periods Vy, Vz, and the like.

The subtractor circuit102subtracts the feedback voltage Vfb from a reference voltage Vref, which is the reference for the output voltage Vout at a target level (e.g., 400 V), to thereby calculate an error E1between the reference voltage Vref and the feedback voltage Vfb.

The voltage regulator circuit104outputs, according to the error E1, the ON period Vx for causing the level of the feedback voltage Vfb to reach the level of the reference voltage Vref. Note the subtractor circuit102and the voltage regulator circuit104according to an embodiment of the present disclosure correspond to a so-called error amplifier circuit to perform amplification, integration, and the like of the error E1, for example. Further, the ON period Vx corresponds to a “first time period”, and the command value indicating the ON period Vx corresponds to a “first command value”.

The ratio output circuit106outputs a ratio ab of “0”, in response to the load11being in the light load state and the load detection circuit12outputting the low signal cmd. Meanwhile, the ratio output circuit106outputs the ratio ab of “0.5”, in response to the load11being in the heavy load and the load detection circuit12outputting the high signal cmd.

The subtractor circuit108subtracts the ratio ab from “1.0”, to thereby output a resultant as a ratio ca. The multiplier circuit110multiplies the ON period Vx by the ratio da, to thereby output a resultant as the ON period Vy. Further, the multiplier circuit112multiplies the ON period Vx by the ratio ab, to thereby output a resultant as the ON period Vz.

Accordingly, as illustrated inFIG.4, assuming that the ON period Vx is “100”, when the load11is in the light load state, the ratio ab is “0”, and thus the ratio da results in “1.0”, and the ON period Vy results in “100”, which is equal to the ON period Vx. Further, in this case, since the ratio ab is “0”, the ON period Vz results in “0”. Meanwhile, when the load11is in the heavy state, the ratio ab is “0.5”, and thus the ratio da results in “0.5”, and the ON period Vy results in “50”, which is a half of the ON period Vx. Similarly, the ON period Vz is a half of the ON period Vx.

Further, even if the ON period Vx is “100” when the load11changes from the light load state to the heavy load state, thereafter, when the power consumed by the load11becomes, for example, twice or more and the load current Iload becomes twice or more, the ON period Vx results in “200” or more. In this case, the ON periods Vy, Vz may become longer than the ON period Vx at the time when the load11changes from the light load state to the heavy load state. Note that the ON period Vy when the load11is in the heavy load state corresponds to a “second time period”, the command value indicating the ON period Vy corresponds to a “second command value”, the ON period Vz corresponds to a “third time period”, and the command value indicating the ON period Vz corresponds to a “third command value”.

The driving signal output circuit120outputs the driving signal Vq1to drive the NMOS transistor26a, based on the voltage Vzcd1corresponding to the inductor current IL1and the ON period Vy. Specifically, the driving signal output circuit120outputs the driving signal Vq1to turn on the NMOS transistor26a, in response to the inductor current IL1reaching substantially zero. Thereafter, the driving signal output circuit120outputs the driving signal Vq1to turn off the NMOS transistor26a, after a lapse of the ON period Vy. The driving signal output circuit120includes the comparator circuits122,128, an RS flip-flop circuit124, and a counter126.

The comparator circuit122detects the timing at which the NMOS transistor26ais turned on, in response to the current value of the inductor current IL1reaching a predetermined current value I0slightly larger than zero (e.g., several mA, i.e., substantially zero (hereinafter, “substantially zero” will be simply referred to as “0” (zero) as appropriate)).

Specifically, in response to the current value of the inductor current IL1becoming smaller than the current value I0and the voltage value of the voltage Vzcd1that indicates the current value of the inductor current IL1becoming smaller than the first predetermined value that indicates the current value I0, the comparator circuit122outputs the high signal Vc1. Meanwhile, in response to the voltage value of the voltage Vzcd1that indicates the current value of the inductor current IL1being larger than the first predetermined voltage value, the comparator circuit122outputs the low signal Vc1. Note that the current value I0corresponds to a “first value”.

The signal Vc1is inputted to an input S of the RS the flip-flop circuit124, and a signal Vc2from the comparator circuit128is inputted to an input R thereof. Thus, in response to the signal Vc1going high, the driving signal Vq1, which is an output Q of the SR flip-flop124, goes high. Meanwhile, in response to the signal Vc2going high, the driving signal Vq1goes low.

The counter126is a circuit to output a signal Vont1to determine the timing at which the NMOS transistor26ais turned off, and increment a count value from zero in response to a clock signal (not shown) when the driving signal Vq1goes high. That is, the counter126outputs a signal corresponding to the ramp wave in which the value of the signal Vont1increases in proportion to an elapsed time, when the driving signal Vq1goes high.

The comparator circuit (CMP)128compares the magnitude between the ON period Vy and the signal Vont1. Specifically, the comparator circuit128outputs the high signal Vc2when the signal Vont1is larger than the ON period Vy, and outputs the low signal Vc2when the signal Vont1is smaller than the ON period Vy. Note that the driving signal output circuit120and the buffer circuit44correspond to a “first driver circuit”.

The driving signal output circuit140outputs the driving signal Vq2to drive the NMOS transistor26b, based on the voltage Vzcd2corresponding to the inductor current IL2and the ON period Vz. Specifically, the driving signal output circuit140outputs the driving signal Vq2to turn on the NMOS transistor26b, in response to the inductor current IL2reaching zero. Thereafter, the driving signal output circuit140outputs the driving signal Vq2to turn off the NMOS transistor26b, after a lapse of the ON period Vz. The driving signal output circuit140includes the comparator circuits142,148, an RS flip-flop circuit144, and a counter146.

The comparator circuit142detects the timing at which the NMOS transistor26bis turned off, in response to the current value of the inductor current IL2reaching zero. Specifically, when the current value of the inductor current IL2becomes smaller than the current value I0, and the voltage value of the voltage Vzcd2indicating the current value of the inductor current IL2becomes smaller than the second predetermined voltage value indicating the current value I0, the comparator circuit142outputs a high signal Vc3. Meanwhile, when the voltage value of the voltage Vzcd2indicating the current value of the inductor current IL2is larger than the second predetermined voltage value, the comparator circuit142outputs the low signal Vc3. Note that the current value I0corresponds to a “second value”.

The signal Vc3is inputted to an input S of the RS flip-flop circuit144, and a signal Vc4from the comparator circuit148is inputted to an input R thereof. Thus, in response to the signal Vc3going high, the signal Vq2, which is an output Q of the SR flip-flop144, goes high. Meanwhile, in response to the signal Vc4going high, the signal Vq2goes low.

The counter146is a circuit to output a signal Vont2to determine the timing at which the NMOS transistor26bis turned off, and increment a count value from zero in response to a clock signal (not shown), when the driving signal Vq2goes high. That is, the counter146outputs a signal corresponding to the ramp wave in which the value of the signal Vont2increases in proportion to an elapsed time, when the driving signal Vq2goes high.

The comparator circuit148compares the magnitude between the ON period Vz and the signal Vont2. Specifically, the comparator circuit148outputs the high signal Vc4when the signal Vont2is larger than the ON period Vz, and outputs the low signal Vc4when the signal Vont2is smaller than the ON period Vz. Note that the driving signal output circuit140and the buffer circuit45correspond to a “second driver circuit”.

<<<Operation of Switching Control Circuit43awhen Load11is in Light Load State>>>

FIG.5is a diagram illustrating main waveforms of the switching control circuit43awhen the load11is in the light load state. When the load11is in the light load state, the command value output circuit100outputs the ON period Vy that is the ON period Vx corresponding to the feedback voltage Vfb, and the ON period Vz of “0”, and the driving signal output circuit140outputs the driving signal Vq2to turn off the NMOS transistor26b.

Accordingly, the following describes, with reference toFIG.5, the operation when the AC-DC converter10generates the output voltage Vout at the target level from the predetermined AC voltage Vac, and supplies power to the constant load.

At the same time, the following also describes the operation of the driving signal output circuit120outputting the driving signal Vq1to drive the NMOS transistor26a, based on the ON period Vy.

First, in response to the inductor current IL1decreasing to the current value I0at time t0, the comparator circuit122changes the signal Vc1to high. Then, in response to the signal Vc1going high, the RS flip-flop circuit124outputs the high signal Vq1.

In response to the driving signal Vq1going high, the NMOS transistor26ais turned on, and thus the inductor current IL1increases.

Further, in response to the driving signal Vq1going high, the count value of the counter126is incremented, and thus the signal Vont1increases as well. Then, in response to the level of signal Vont1exceeding that of the ON period Vy at time t1, the comparator circuit128changes the signal Vc2to high. As a result, the RS flip-flop circuit124is reset, and the driving signal Vq1goes low.

In response to the driving signal Vq1going low, the NMOS transistor26ais turned off. As a result, the inductor current IL1gradually decreases. Further, in response to the inductor current IL1decreasing to zero at time t2, the operation at time t0is repeated.

Here, when the AC-DC converter10is generating the output voltage Vout at the target level from the predetermined AC voltage Vac, the capacitance of the capacitor22is sufficiently large and the feedback voltage Vfb is substantially constant within the time period corresponding to about one period of Vac. As a result, the ON period Vy outputted from the command output circuit100also becomes substantially constant, and thus the time period during which the NMOS the transistor26ais on (e.g., the time period from time t0to t1) results in being substantially constant as well.

Further, when NMOS the transistor26ais turned on, the current value of the inductor current IL1increases with a rise in the level of the voltage Vrec obtained by rectifying the AC voltage Vac. As a result, the waveform of the peak values of the inductor current IL1results in being similar to the voltage Vrec, as illustrated inFIG.6.

As the level of the peak value of the inductor current IL1when the NMOS transistor26ais turned off rises, the time period for the inductor current IL1to reach zero when NMOS the transistor26ais off increases. Accordingly, when the level of voltage Vrec is low, the switching frequency of the NMOS transistor26arises, and when the level of voltage Vrec is high, the switching frequency of the NMOS transistor26adrops.

<<<Operation of Switching Control Circuit43awhen Load11Changes from Light Load State to Heavy Load State>>>

FIG.7is a diagram illustrating main waveforms of the switching control circuit43awhen the load11changes from the light load state to the heavy load state. It is assumed that before time t10, the load11is in the light load state, and thus the load detection circuit12outputs the low signal cmd, and the feedback voltage Vfb is such a voltage at which the voltage regulator circuit104outputs the ON period Vx of “100”. Further, the multiplier circuit110outputs the ON period Vy of “100” and the multiplier circuit112outputs the ON period Vz of “0”. Before time t10, the switching control circuit43ais performing the operation as described with reference toFIG.5.

Upon detecting that the load has changed from the light load state to the heavy load state at time t10, the load detection circuit12outputs the high signal cmd. In response to the load detection circuit12outputting the high signal cmd, the ratio output circuit106outputs the ratio αb of “0.5”. In response to the ratio αb of “0.5” being outputted, the subtractor circuit108outputs the ratio αa of “0.5”. In response to the ratios αa, αb of “0.5” being outputted, the multiplier circuits110,112output the ON periods Vy, Vz of “50”, respectively.

In response to the ON periods Vy, Vz of “50” being outputted, the driving signal output circuit140outputs the driving signal Vq2to turn on the NMOS transistor26b, since the inductor current IL2is zero. Upon turning on of the NMOS transistor26b, the inductor current IL2starts to increase.

At time t11at which the ON period of the NMOS transistor26bis the ON period Vz of “50”, the driving signal output circuit140outputs the driving signal Vq2to turn off the NMOS transistor26b. Thereafter, the inductor current IL2starts to decrease. Further, at time t11, in response to the inductor current IL1reaching zero, the driving signal output circuit120outputs the driving signal Vq1to turn on the NMOS transistor26a.

At time t12at which the inductor current IL2decreases to zero, the driving signal output circuit140outputs the driving signal Vq2to turn on the NMOS transistor26b. Thereafter, the driving signal output circuit140repeats the same operation.

At time t13at which the ON period of the NMOS transistor26ais the ON period Vy of “50”, the driving signal output circuit120outputs the driving signal Vq1to turn off the NMOS transistor26a. Thereafter, the inductor current IL1starts to decrease.

At time t14at which the inductor current IL1reaches zero, the driving signal output circuit120outputs the driving signal Vq1to turn on the NMOS transistor26a. Thereafter, the driving signal output circuit120repeats the same operation.

As such, when the load11is in the light load state, the switching control circuit43adrives only the NMOS transistor26awith the ON period Vy that is the ON period Vx based on the feedback voltage Vfb. Meanwhile, in response to the load11changing from the light load state to the heavy load state, the switching control circuit43adrives the NMOS transistors26a,26bwith the ON periods Vy, Vz each being a half of the ON period Vx. That is, the switching control circuit43acontrols the total of the ON periods Vy, Vz so as to be equal to the ON period Vx, thereby suppressing an increase in the input and output currents caused by an increase in the ON period and suppress a disturbance of the input current in association with a rise in the output voltage.

Accordingly, unlike the case where, while the NMOS transistor26ais driven with the ON period Vy that is the ON period Vx, the NMOS transistor26bstarts to be driven with the ON period of a value equal or close thereto, the total amount of the input current of the AC-DC converter10remains substantially unchanged. Thus, even if the load11enters the heavy load state and the two boost chopper circuits start operating, the AC-DC converter10does not supply an excessive output current to the load11, thereby suppressing a rise in the output voltage Vout causing a disturbance of the input current.

Further, here, in the case of using so-called soft start in which the ON period Vz is gradually increased from zero to a half of the ON period Vx, while the ON period Vy is gradually reduced from the ON period Vx to a half of the ON period Vx, it is possible to suppress a change in the amplitude of the input current and a rise in the output. However, by this method, the frequencies of the driving signals Vq1, Vq2do not match until the ON periods Vy, Vz become equal to each other.

Further, if the frequencies of the driving signals Vq1, Vq2are different even slightly, the NMOS transistors26a,26bcannot be turned on in a predetermined phase relationship such that the two boost chopper circuits perform an interleaved operation. Thus, the interleaved operation is not viable during a soft start period.

In particular, when the frequencies of the driving signals Vq1, Vq2are slightly different, a low frequency component, so-called beat frequency, is generated due to the difference in the frequencies, which causes a concern of occurrence of an unexpected disturbance of the input current due to resonance with a filter. Further, as will be described below, the same concern arise in the case where the NMOS transistor26bis stopped when the load11changes from the heavy load state to the light load state.

<<<Operation of Switching Control Circuit43awhen Load11Changes from Heavy Load State to Light Load State>>>

FIG.8is a diagram illustrating main waveforms of the switching control circuit43awhen the load11changes from the heavy load state to the light load state. It is assumed that before time t20, the load11is in the heavy load state, the load detection circuit12outputs the high signal cmd, and the feedback voltage Vfb is such a voltage at which the voltage regulator circuit104outputs the ON period Vx of “100”. Further, the multiplier circuit110outputs the ON period Vy of “50”, and the multiplier circuit112outputs the ON period Vz of “50”. Further, before time t20, the switching control circuit43aperforms the operation as described with reference toFIG.7.

Upon detecting that the load11has changed from the heavy load state to the light load state at time t20, the load detection circuit12outputs the low signal cmd. In response to the load detection circuit12outputting the low signal cmd, the ratio output circuit106outputs the ratio ab of “0”. In response to the ratio αb of “0” is outputted, the subtractor circuit108outputs the ratio αa of “1.0”. In response to the ratio αa of “1.0” and the ratio αb of “0” being outputted, the multiplier circuit110outputs the ON period Vy of “100”, and the multiplier circuit112outputs the ON period Vz of “0”.

Then, in response to the ON period Vy of “100” and the ON period Vz of “0” being outputted, the driving signal output circuit140outputs the driving signal Vq2to turn off the NMOS transistor26b. Further, in response to the ON period of the NMOS transistor26abeing the ON period Vy of “50”, the driving signal output circuit120outputs the driving signal Vq1to turn off the NMOS transistor26a. Thereafter, the inductor current IL1starts to decrease.

At time t21at which the inductor current IL1decreases to zero, the driving signal output circuit120outputs the driving signal Vq1to turn on the NMOS transistor26a.

At time t22at which the ON period of the NMOS transistor26abecomes the ON period Vy of “100”, the driving signal output circuit120outputs the driving signal Vq1to turn off the NMOS transistor26a. Thereafter, the inductor current IL1starts to decrease.

At time t23at which the inductor current IL1reaches zero, the driving signal output circuit120outputs the driving signal Vq1to turn on the NMOS transistor26a. Thereafter, the driving signal output circuit120repeats the same operation.

In this way, when the load11is the heavy load state, the switching control circuit43adrives the NMOS transistors26a,26bwith the ON periods Vy, Vz, which are equal to a half of the ON period Vx. Meanwhile, in response to the load11changes from the heavy load state to the light load state, the switching control circuit43adrives only the NMOS transistor26awith the ON period Vy that is the ON period Vx based on the feedback voltage Vfb.

Accordingly, the state in which the NMOS transistors26a,26bare driven with the ON periods Vy, Vz that are equal to a half of the ON period Vx is changed into the state in which only the NMOS transistor26ais driven with the ON period Vy that is the ON period Vx. This enables the switching control circuit43ato shift from the operation of two boost chopper circuits to the operation of one boost chopper circuit, without changing the total amount of the input current of the AC-DC converter10, thereby being able to suppress a drop in the output voltage Vout and a disturbance of the input current.

Other Embodiments

The above description focuses only on the ON period and the amplitudes of the inductor currents IL1, IL2with the ON period, however, in order for the two boost chopper circuits to perform the interleaved operation, a means of performing control such that the driving signals Vq1, Vq2have a predetermined phase relationship is needed.FIG.9, which will be described below, illustrates a switching control circuit43bin which the means of controlling the driving signals Vq1, Vq2so as to have the predetermined phase relationship is added to the switching control circuit43a.

==Configuration of Switching Control Circuit43b==

FIG.9is a diagram illustrating an example of the switching control circuit43b. The switching control circuit43boutputs the driving signals Vq1, Vq2, based on the inductor currents IL1, IL2, the feedback voltage Vfb, and the signal cmd, as with the switching control circuit43a. Specifically, the switching control circuit43boperates as with the switching control circuit43awhen the load11is in the light load state.

Meanwhile, when the load11is in the heavy load state, the switching control circuit43boutputs the driving signal Vq1to turn on the NMOS transistor26a, in response to the inductor current IL1reaching zero and the voltage Vzcd1corresponding to the inductor current IL1reaching the first predetermined voltage value. Meanwhile, when the load11is in the heavy load state, the switching control circuit43boutputs the driving signal Vq2to turn on the NMOS transistor26b, in response to the inductor current IL2reaching zero and the voltage Vzcd2corresponding to the inductor current IL2reaching the second predetermined voltage value. Thereafter, the switching control circuit43boutputs the driving signals Vq1, Vq2to turn off the NMOS transistors26a,26b, in response to the ON periods Vy, Vz having elapsed, respectively, which are obtained by multiplying the ON period Vx by the ratio (e.g.,0.5in an embodiment of the present disclosure) for the two boost chopper circuits to supply power to the load11in a balanced manner. Further, the switching control circuit43boutputs the driving signals Vq1, Vq2to drive the NMOS transistors26a,26bsuch that the two boost chopper circuits maintain the appropriate interleaved operation. The switching control circuit43bincludes the command value output circuit100, the driving signal output circuit120, a driving signal output circuit150, and an error output circuit160.

The driving signal output circuit150outputs the driving signal Vq2to drive the NMOS transistor26b, based on the voltage Vzcd2corresponding to the inductor current IL2, the ON period Vz, and the ON period Vlpf from the error output circuit160(described later). Note that the ON period Vlpf corresponds to the time difference TO between the on-timings of the NMOS transistors26a,26b, and, specifically, corresponds to an error between a predetermined value and a result obtained by dividing the time difference TO by the switching period Ta of the NMOS transistor26a, which will be described later in detail.

Specifically, when the load11is in the heavy load state, the driving signal output circuit150outputs the driving signal Vq2to turn on the NMOS transistor26bafter the inductor current IL2reaches zero. Thereafter, the driving signal output circuit150outputs the driving signal Vq2to turn off the NMOS transistor26bafter a lapse of an ON period Vu according to the ON periods Vz, Vlpf. The driving signal output circuit150includes the comparator circuits142,148, the RS flip-flop circuit144, the counter146, and an adder circuit152.

The adder circuit152adds the ON period Vlpf from the error output circuit160to the ON period Vz, to thereby output a result as the ON period Vu. Note that details of the error output circuit160will be described later. Further, the ON period Vu corresponds to a “fourth time period.”

The error output circuit160outputs the ON period Vlpf to adjust the ON period Vu, which is the ON period of the NMOS transistor26b, such that the two boost chopper circuits perform the appropriate interleaved operation, based on the on-timings of the NMOS transistors26a,26b.

Specifically, the error output circuit160outputs the positive ON period Vlpf when the on-timing of the NMOS transistor26badvances with respect to the on-timing of the NMOS transistor26a. This causes the ON period Vu to be longer than the ON period Vz, and the on-timing at which the NMOS transistor26bis turned on later is delayed.

Meanwhile, the error output circuit160outputs the negative ON period Vlpf, in response to the on-timing of the NMOS transistor26bbeing delayed with respect to the on-timing of the NMOS transistor26a. This causes the ON period Vu to be shorter than the ON period Vz, and the on-timing at which the NMOS transistor26bis turned on later becomes earlier.

The error output circuit160includes an RS flip-flop circuit162, a level shifter circuit164, a subtractor circuit166, a low-pass filter (LPF)168, and a multiplier circuit170.

Note that upon receiving a low signal enb, the multiplier circuit170outputs the ON period Vlpf of “0”, which will be described later in detail. Further, the on-timing of the NMOS transistor26acorresponds to a “first timing”, the on-timing of the NMOS transistor26bcorresponds to a “second timing”, and the ON period Vlpf corresponds to an “error”.

The RS flip-flop circuit162detects the time difference Tθ between the on-timings of the NMOS transistors26a,26band the switching period Ta of the NMOS transistor26a, to thereby output a signal Q bar indicating a ratio R between the time difference TO and the switching period Ta. Specifically, upon receiving the high signal Vc1, the RS flip-flop circuit162outputs the low signal Q bar, and upon receiving the high signal Vc3, the RS flip-flop circuit162outputs the high signal Q bar.

Thus, the RS flip-flop circuit162detects the time difference Tθ in the time period during which the signal Q bar is low, and detects the switching the period Ta every time the signal Q bar goes low. Accordingly, the signal Q bar from RS flip-flop circuit162is a signal indicating the duty (i.e., ratio) of the time difference TO between the inductor currents IL1and IL2with respect to the switching period Ta. Note that the ratio R corresponds to a “ratio”.

The level shifter circuit164levels-shifts the signal Q bar from the RS flip-flop circuit162in order to simplify the circuit configuration in an embodiment of the present disclosure, which will be described later in detail. Specifically, when the RS flip-flop circuit162operates with the power supply voltage Vdd, with the voltage level of the low signal Q bar from the RS flip-flop circuit162being maintained at the ground level, the level shifter circuit164causes the voltage level of the high signal Q bar to be twice the voltage level of Vdd.

The subtractor circuit166subtracts a value (e.g., “1.0” in an embodiment of the present disclosure) indicating the predetermined ratio (e.g., “50%” in an embodiment of the present disclosure) from the level of the signal from the level shifter circuit164, to thereby output a result as an error E2.

Thus, the subtractor circuit166causes the low-pass filter168to output the ON period Vlpf of “0”, when the ratio R between the time difference TO and the switching period Ta matches the predetermined ratio. Specifically, the subtractor circuit166subtracts the power supply voltage Vdd corresponding to the value “1.0” indicating the predetermined ratio, from the signal from the level shifter circuit164, which changes in a range from 0 V to (2×Vdd) V, to thereby output a result as the error E2.

This makes it possible that when the ratio R between the time difference Tθ and the switching period Ta matches the predetermined ratio, and the level shifter circuit164outputs such a signal that the ratio of a low period per one switching period Ta is 50%, the subtractor circuit166causes the low-pass filter168to output the ON period Vlpf of “0”. Further, as such, in an embodiment of the present disclosure, when the ratio R between the time difference TO and the switching period Ta matches the predetermined ratio by setting the value to be subtracted by the subtractor circuit166to the value “1.0” indicating the predetermined ratio, the subtractor circuit166can cause the low-pass filter168to output the ON period Vlpf of “0”, easily.

Note that an embodiment of the present disclosure describes the case of causing the two boost chopper circuits to perform the interleaved operation, case, the phase difference Δθ to perform the appropriate interleaved operation is 360 degrees/2=180 degrees in one switching period. Further, assuming that the phase difference40in one switching period Ta is 180 degrees, the predetermined ratio results in 50%.

Further, when the predetermined ratio is 50%, the subtractor circuit166subtracts the value of “1.0” indicating the predetermined ratio (50%) from the level-shifted signal. This enables the subtractor circuit166to cause the low-pass filter168to output the ON period Vlpf of zero, when the ratio R between the time difference Tθ and the switching period Ta matches the predetermined ratio.

Meanwhile, when n (n is 3 or more) the boost chopper circuits perform the interleaved operation, the phase difference40to perform the appropriate interleaved operation is 360 degrees/n in one switching period Ta. Further, assuming that the phase difference40in one switching period Ta is 360 degrees/n, the predetermined ratio is (100/n) %.

Further, when the predetermined ratio is (100/n) %, the subtractor circuit166subtracts a value (2/n) indicating the predetermined ratio (100/n) % from the level-shifted signal. Thus, when the ratio R between the time difference TO and the switching period Ta matches the predetermined ratio, the subtractor circuit166can cause the low-pass filter168to output the ON period Vlpf of zero.

Hereinabove, the case has been described in which the level shifter circuit164level-shifts the signal Q bar from the RS flip-flop circuit162to a signal of a voltage level of (2×Vdd) V. Meanwhile, when the level shifter circuit164level-shifts the signal Q bar from the RS flip-flop circuit162to a signal of a voltage level of (p×Vdd) V (where p is a positive real number), and when n the boost chopper circuits perform the interleaved operation, the subtractor circuit166subtracts a value (p/n) indicating the predetermined ratio from the level-shifted signal. This makes it possible that when the ratio R between the time difference Tθ and the switching period Ta match the predetermined ratio, the subtractor circuit166causes the low-pass filter168to output the ON period Vlpf of zero.

The low-pass filter (LPF)168integrates the error E2from the subtractor circuit166, to thereby output the ON period Vlpf.

When the signal enb is high, the multiplier circuit170multiplies the ON period Vlpf by “1”, to thereby output a result as the ON period Vlpf, and when the signal enb is low, the multiplier circuit170multiplies the ON period Vlpf by “0”, to thereby output a result as the ON period Vlpf. Note that the enable circuit (not illustrated) changes the signal enb to high after the driving signal output circuit150outputs the driving signal Vq2to turn on the NMOS transistor26bonce or more, and changes the signal enb to low in response to the load detection circuit12outputting the low signal cmd.

With the error output circuit160being configured as described above, even if the switching frequency of the NMOS transistor26adecreases, the switching frequency of the NMOS transistor26bremains high, and when the time difference Tθ decreases, the ratio R exceeds the predetermined ratio, and the ON period Vlpf becomes a positive value. In this case, the ON period Vu results in being longer than the ON period Vz.

Then, since the ON period Vu of the NMOS transistor26bincreases, the peak value of the inductor current IL2increases, the switching period of the NMOS transistor26bincreases, and the switching frequency drops. Further, with an increase in the switching period of the NMOS transistor26b, the timing at which the NMOS transistor26bis turned on next is delayed, and the ratio R decreases and approaches the predetermined ratio.

Meanwhile, even if the switching frequency of the NMOS transistor26arises, the switching frequency of the NMOS transistor26bremains low, and when the time difference Tθ increases, the ratio R decreases below the predetermined ratio, and the ON period Vlpf becomes a negative value. In this case, the ON period Vu results in being shorter than the ON period Vz.

Then, since the ON period Vu of the NMOS transistor26bdecreases, the peak value of the inductor current IL2decreases, the switching period of the NMOS transistor26bdecreases, and the switching frequency rises. Further, with a decrease in the switching period of the NMOS transistor26b, the timing at which the NMOS transistor26bis turned on next becomes earlier, and the ratio R increases and approaches the predetermined ratio.

As such, the adder circuit152of the driving signal output circuit150outputs the ON period Vu according to the ON period Vz and the ON period Vlpf, so that the switching control circuit43bcan control the switching of the NMOS transistor26bso as to maintain the appropriate interleaved operation, while following changes in the switching frequency of the NMOS transistor26a.

<<<Operation of Switching Control Circuit43bwhen Load11Changes from Light Load State to Heavy Load State>>>

FIG.10is a diagram illustrating main waveforms of the switching control circuit43bwhen the load11changes from the light load state to the heavy load state. It is assumed that before time t30, the load11is in the light load state, and thus the load detection circuit12outputs the low signal cmd, and the feedback voltage Vfb is such a voltage at which the voltage regulator circuit104outputs the ON period Vx of “100”. Further, the multiplier circuit110outputs the ON period Vy of “100”, and the multiplier circuit112outputs the ON period Vz of “0”. Further, before time t30, the switching control circuit43bperforms the operation as described with reference toFIG.5.

At time t30, in response to the load detection circuit12detecting that the load11changes from the light load state to the heavy load state, the load detection circuit12outputs the high signal cmd. In response to the load detection circuit12outputting the high signal cmd, the ratio output circuit106outputs the ratio ab of “0.5”. In response to the ratio αb of “0.5” being outputted, the subtractor circuit108outputs the ratio αa of “0.5”. In response to the ratios αa, αb of “0.5” being outputted, the multiplier circuits110,112output the ON periods Vy, Vz of “50”, respectively.

In response to the ON periods Vy, Vz of “50” being outputted, the driving signal output circuit150outputs the driving signal Vq2to turn on the NMOS transistor26b, since the inductor current IL2is zero. Upon turning on of the NMOS transistor26b, the inductor current IL2starts to increase.

Thereafter, since the NMOS transistor26bis turned on, the time difference Tθ starts to be detected, and thus the error E2changes from “−1” to “+1”. Upon a change in the error E2, the low-pass filter168starts to increase the ON period Vlpf.

The operation of the switching control circuit43bfrom time t31to t32is the same as the operation of the switching control circuit43afrom t11to t12inFIG.6, and thus the description thereof is omitted.

At time t33at which the ON period of the NMOS transistor26abecomes the ON period Vy of “50”, the driving signal output circuit120outputs the driving signal Vq2to turn off the NMOS transistor26b. Thereafter, the inductor current IL2starts to decrease. Further, the enable circuit (not illustrated) changes the signal enb to high because the driving signal output circuit150outputs the driving signal Vq2to turn on the NMOS transistor26bonce or more. Thereafter, the error output circuit160starts outputting the ON period Vlpf such that the two boost chopper circuits accurately perform the interleaved operation, and the driving signal output circuit150starts outputting the driving signal Vq2to drive the NMOS transistor26bwith the ON period Vu based on the ON period Vlpf and the ON period Vz.

At time t34at which the two boost chopper circuits start to accurately perform the interleaved operation, the low-pass filter168outputs the ON period Vlpf of “0”. Thereafter, the NMOS transistors26a,26bare driven such that the two boost chopper circuits accurately perform the interleaved operation.

As such, in response to the ON period Vlpf from the error output circuit160being outputted to the driving signal output circuit150after the load11enters the heavy load state, the two boost chopper circuits accurately perform the interleaved operation.

<<<Simulation Results of Switching Control Circuit43b>>>

FIG.11is a diagram illustrating simulation results of the switching control circuit43b. Here, the top diagram illustrates the results indicating changes in the signal cmd. The second diagram from the top illustrates the results indicating the inductor currents IL1, IL2. The third diagram from the top illustrates the results indicating the total current of the inductor currents IL1, IL2. Furthermore, the bottom diagram illustrates the results indicating the input current Iin.

First, referring to the top diagram, the load detection circuit12outputs the high signal cmd around Time=15 ms. Then, the load detection circuit12outputs the low signal cmd around Time=35 ms. Other simulation results will be described below in consideration of these changes in the signal cmd.

In Time=0 to 15 ms, the switching control circuit43bdrives only the NMOS transistor26abecause the load11is in the light load state. Accordingly, in this event, only the inductor current IL1flows. Thus, the total current of the inductor currents IL1, IL2also results in only the inductor current IL1. Although the AC voltage Vac and the rectified voltage Vrec are not illustrated, the switching control circuit43bin this time period performs the operation as described with reference toFIG.5, and performs the power factor correcting operation in the critical mode, and thus the input current Iin results in being substantially in phase with the AC voltage Vac.

In Time=15 to 35 ms, the switching control circuit43bdrives the NMOS transistors26a,26b, because the load11is in the heavy load state. Accordingly, in this event, the inductor currents IL1, IL2flow. Further, assuming that the feedback voltage Vfb does not change, the NMOS transistors26a,26bare driven with the ON period that is a half of the ON period of the NMOS transistor26aduring Time=0 to 15 ms.

Thus, the peak value of the inductor current IL1, IL2results in a half of the peak value of the inductor current IL1during Time=0 to 15 ms. Further, the switching control circuit43bdrives the NMOS transistors26a,26bsuch that the two boost chopper circuits perform the interleaved operation, and thus the total current of the inductor currents IL1, IL2has a waveform in which ripples are superimposed on the low frequency components and the amplitude of the ripples decreases, unlike during Time=0 to 15 ms.

The operation of the switching control circuit43bfrom Time=35 ms is the same as the operation during Time=0 to 15 ms, and thus the description thereof is omitted.

<<<Enlarged View of Simulation Results of Switching Control Circuit43b>>>

FIG.12is an enlarged view of a portion corresponding to Time=14.9 to 15.1 ms of the simulation results of the switching control circuit43binFIG.11. Furthermore, since the order in which the four simulation results are arranged is the same as inFIG.10, the description thereof is omitted. Further, inFIGS.11and12, the inductor current IL1is given by the solid line, and the inductor current IL2is given by the dashed line.

At Time=15 ms, in response to the load detection circuit12outputting the high signal cmd, the command value output circuit100outputs the ON periods Vy, Vz being a half of the ON period Vx. Then, the driving signal output circuit150starts driving the NMOS transistor26b. In response to the NMOS transistor26bstarting to be driven, the total current of the inductor currents IL1, IL2is disturbed, because the NMOS transistors26a,26bare not yet driven such that the two boost chopper circuits accurately perform the interleaved operation.

At Time=15.05 ms, the error output circuit160outputs the ON period Vlpf of “0”, and the NMOS transistors26a,26bare driven such that the two boost chopper circuits accurately perform the interleaved operation. In association therewith, the total current of the inductor currents IL1, IL2has a waveform in which ripples are superimposed on the low frequency components and the amplitude of the ripples decreases. Note thatFIG.12is an enlarged view of the time period during Time=14.9 to 15.1 ms, and thus the input current Iin hardly changes.

FIG.13is an enlarged view of a portion corresponding to Time=34.9 to 35.1 ms of the simulation results of the switching control circuit43binFIG.11. Furthermore, the order in which the four simulation results are arranged is the same as inFIG.11, and thus the description thereof is omitted.

At Time=35 ms, in response to the load detection circuit12outputting the low signal cmd, the command value output circuit100outputs the ON period Vy that is the ON period Vx, and the ON period Vz of “0”. Then, the driving signal output circuit150stops driving the NMOS transistor26b. In response to the driving of the NMOS transistor26bbeing stopped, the total current of the inductor currents IL1, IL2results in only the inductor current IL1.

As such, when the load11changes from the heavy load state to the light load state, the total current of the inductor currents IL1, IL2is not disturbed because only the driving of the NMOS transistor26bis stopped. Note thatFIG.13is an enlarged view of the time period during Time=34.9 to 35.1 ms inFIG.11, and thus the input current Iin hardly changes.

The operation of the switching control circuit43bhas been described above, and in the switching control circuit43b, the two boost chopper circuits can appropriately perform the interleaved operation as time passes. Furthermore, even immediately after the load11changes from the light load state to the heavy load state, the on-timing of the NMOS transistor26bis controlled such that the two boost chopper circuits appropriately perform the interleaved operation, and switching control circuit43cin which the two boost chopper circuits perform the interleaved operation to some extent will be described below.

==Configuration of Switching Control Circuit43c==

FIG.14is a diagram illustrating an example of the switching control circuit43c.

The switching control circuit43coutputs the driving signals Vq1, Vq2, based on the inductor currents IL1, IL2, the feedback voltage Vfb, and the signal cmd, as with the switching control circuits43a,43b.

Specifically, the switching control circuit43coutputs the driving signal Vq1to turn on the NMOS transistor26a, in response to the inductor current IL1reaching substantially zero, and the voltage Vzcd1corresponding to the inductor current IL1reaching the first predetermined voltage value, when the load11is in the heavy load state.

After that, the switching control circuit43coutputs the driving signal Vq2to turn on the NMOS transistor26b, in response to a half of the switching period Ta of the NMOS transistor26ahaving elapsed, the inductor current IL2reaching zero, and the voltage Vzcd2corresponding to the inductor current IL2reaching the second predetermined voltage value. The switching control circuit43cincludes the command value output circuit100, the driving signal output circuit120, a driving signal output circuit220, and a detection circuit200.

The detection circuit200detects the timing at which the NMOS transistor26bis to be turned on, in response to the driving signal Vq1. Specifically, the detection circuit200detects the switching period Ta of the NMOS transistor26aevery time the driving signal Vq1changes from low to high, and detects, from the above switching period Ta, the timing at which a half of the switching period Ta has elapsed since the NMOS transistor26ais turned on next. Then, the detection circuit200controls the timing at which the driving signal output circuit220turns on the NMOS transistor26b, based on the timing at which a half of the switching period Ta has elapsed. The detection circuit200includes a delay circuit202, a counter204, a sample-and-hold circuit206, a multiplier circuit208, a comparator circuit210, and an RS flip-flop circuit212.

The delay circuit (DELAY)202is a circuit to output a signal to reset the counter204, and outputs the signal to reset the counter204after a lapse of the predetermined time period, in response to the driving signal output circuit120outputting the high driving signal Vq1. Note that the predetermined time period is the time period that is sufficiently short such that the detection circuit200correctly operates.

The counter204is a circuit to count to measure the switching period Ta of the NMOS transistor26a, and after being reset by a reset signal from the delay circuit202, the counter204starts counting from “0” and continues counting until being reset. Note that the counter204corresponds to a “timer circuit”.

The sample-and-hold circuit (S/H)206is a circuit to hold the switching period Ta of the NMOS transistor26a, and in response to the driving signal output circuit120outputting the high driving signal Vq1, the sample-and-hold circuit206samples and holds the count value cnt of the counter204, to thereby output a result as a count value sont. Accordingly, the count value sont corresponds to the switching period Ta.

The multiplier circuit208is a circuit to output a count value ref indicating a half of the switching period Ta. Specifically, the multiplier circuit208multiplies the count value sont by “0.25”, at the first rising edge of the driving signal Vq1when the rising edge is counted from the input of the high signal cmd.

Further, in response to the load detection circuit12outputting the high signal cmd, the ON period Vy is halved and the switching period Ta is also halved, but at the first rising edge of the driving signal Vq1, the count value sont indicates the switching period Ta before the ON period Vy is halved (i.e., twice the switching period). Thus, at this timing, if the count value ref indicating a half of the switching period Ta is to be outputted, the count value sont needs to be multiplied by “0.25” to be outputted as the count value ref. This makes it possible that the multiplier circuit208outputs the count value ref indicating a half of the switching period Ta after the load detection circuit12outputs the high signal cmd.

Further, from the second rising edge of the driving signal Vq1when the rising edge is counted from the input of the high signal cmd, the count value sont indicates the switching period Ta after the ON period Vy is halved. Thus, the multiplier circuit208multiplies the count value sont by “0.5”, to thereby output a result as the count value ref. The count value ref in this case also indicates a half of the switching period Ta after the load detection circuit12outputs the high signal cmd.

Further, this enables the detection circuit200to maintain the timing at which the NMOS transistor26bis turned on, at the timing after substantially a half of the switching period Ta of the NMOS transistor26aor thereafter, which will be described later in detail. Accordingly, the switching control circuit43ccan drive the NMOS transistors26a,26bsuch that the two boost chopper circuits perform the interleaved operation to some extent. Note that when the multiplier circuit208receives the low signal cmd, the ON period Vz is “0” and the NMOS transistor26bis not turned on, and thus the multiplier circuit208may output the count value ref of “0”.

The comparator circuit210is a circuit to compare the count value cnt and the count value ref, to determine whether a half of the switching period Ta has elapsed since the NMOS transistor26ais turned on. Specifically, the comparator circuit210outputs a high signal to set the RS flip-flop circuit212, in response to the driving signal output circuit120outputting the high driving signal Vq1, the counter204starting to count, and the count value cnt exceeding the count value ref. Meanwhile, the comparator circuit210outputs a low signal when the count value cnt is smaller than the count value ref.

The RS flip-flop circuit212is a circuit to output a signal mask indicating the timing at which the NMOS transistor26bis to be turned on, based on the signal from the comparator circuit210and the driving signal Vq1. Specifically, the RS flip-flop circuit212outputs the low signal mask, in response to the driving signal output circuit120outputting the high driving signal Vq1, and outputs the high signal mask, in response to the comparator circuit210outputting the high signal.

As such, in response to a half of the switching period Ta of the NMOS transistor26ahaving elapsed since the NMOS transistor26ais turned on, the detection circuit200notifies, using the signal mask, the driving signal output circuit220of the timing at which the NMOS transistor26bis to be turned on. Then, the driving signal output circuit220outputs the driving signal Vq2to turn on the NMOS transistor26bin response to the signal mask, which will be described later in detail. This enables the switching control circuit43cto drive the NMOS transistors26a,26bsuch that the two boost chopper circuits perform the interleaved operation while operating in the critical mode, to some extent.

The driving signal output circuit220outputs the driving signal Vq2to drive the NMOS transistor26b, based on the voltage Vzcd2corresponding to the inductor current IL2, the ON period Vz, and the signal mask. Specifically, the driving signal output circuit220outputs the driving signal Vq2to turn on the NMOS transistor26b, in response to receiving the high signal mask from the detection circuit200, the inductor current IL2reaching zero, and the voltage Vzcd2corresponding to the inductor current IL2reaching the second predetermined voltage value. Thereafter, the driving signal output circuit220outputs the driving signal Vq2to turn off the NMOS transistor26b, in response to the time period corresponding to the ON period Vz having elapsed. The driving signal output circuit220includes the comparator circuits142,148, the RS flip-flop circuit144, the counter146, and an AND circuit222.

The AND circuit222is a circuit to determine the timing at which the NMOS transistor26bis turned on, and calculate the logical product of the signal Vc3from the comparator circuit142and the signal mask from the detection circuit200, to thereby output a result as a signal Vc5. Specifically, the AND circuit222outputs the high signal Vc5, in response to the detection circuit200outputting the high signal mask and the inductor current IL2reaching zero. This ensures that the timing at which the NMOS transistor26bis turned on is at or after the timing at which a half of the switching period Ta has elapsed since the NMOS transistor26ais turned on.

Note that the driving signal output circuit220outputs the driving signal Vq2to turn on the NMOS transistor26b, in response to the load11changing to the heavy load state, the time period of a quarter of the switching period Ta having elapsed after an occurrence of one rising edge of the driving signal Vq1, and a first condition that the inductor current IL2reaches zero being satisfied. Thereafter, the driving signal output circuit220outputs the driving signal Vq2to turn on the NMOS transistor26b, in response to the first condition being satisfied, the time period of a half of the switching period having elapsed after next occurrence of the rising edge of the driving signal Vq1, and a second condition that the inductor current IL2reaches zero being satisfied.

<<<Operation of Switching Control Circuit43cwhen the Load11Changes from Light Load State to Heavy Load State>>>

FIG.15is a diagram illustrating main waveforms of the switching control circuit43cwhen the load11changes from the light load state to the heavy load state. It is assumed that before time t40, the load11is in the light load state, and thus the load detection circuit12outputs the low signal cmd, and the feedback voltage Vfb is such a voltage at which the voltage regulator circuit104outputs the ON period Vx of “100”. Further, the multiplier circuit110outputs the ON period Vy of “100”, and the multiplier circuit112outputs the ON period Vz of “0”.

Further, before time t40, the switching control circuit43cperforms the operation as described with reference toFIG.5. It is assumed that the switching period Ta of the NMOS transistor26ais “120”, and the sample-and-hold circuit206outputs the count value sont of “120”. It is assumed that the switching period Ta of the NMOS transistor26ais “120”, and the sample-and-hold circuit206outputs the count value sont of “120”. Further, since the load detection circuit12is outputting the low signal cmd, the multiplier circuit208is outputting the count value ref of “0”.

At time t40, in response to the load detection circuit12detecting the load11has changed from the light load state to the heavy load state, the load detection circuit12outputs the high signal cmd. In response to the load detection circuit12outputting the high signal cmd, the ratio output circuit106outputs the ratio ab of “0.5”. In response to the ratio αb of “0.5” being outputted, the subtractor circuit108outputs the ratio αa of “0.5”. In response to the ratios αa, αb of “0.5” being outputted, the multiplier circuits110,112output the ON periods Vy, Vz of “50”, respectively.

At time t41, in response to the NMOS transistor26abeing turned on, the counter204outputs the count value cnt of “120”, and the sample-and-hold circuit206continues to output the count value sont of “120”. Since the NMOS transistor26ais turned on first after the load detection circuit12outputs the high signal cmd, the multiplier circuit208outputs the count value ref of “30” obtained by multiplying the count value sent by “0.25”.

At time t42at which the counter204outputs the count value cnt that is the same as the count value ref, the detection circuit200outputs the high signal mask. In response to the detection circuit200outputting the high signal mask, the AND circuit222outputs the high signal Vc5, and the driving signal output circuit220outputs the driving signal Vq2to turn on the NMOS transistor26b, because the inductor current IL2is zero.

At time t43at which the inductor current IL1reaches zero after the NMOS transistor26ais turned off, the ON period Vy of the NMOS transistor26ais a half of the ON period Vx, and thus the switching period Ta of the NMOS transistor26ais “60”. Thus, the sample-and-hold circuit206outputs the count value sont of “60”. Further, since the NMOS transistor26ais turned on at the second time after the load detection circuit12outputs the high signal cmd, the multiplier circuit208outputs the count value ref obtained by multiplying the count value sont by “0.5”. Further, in response to the NMOS transistor26abeing turned on, the detection circuit200outputs the low signal mask.

Thereafter, the detection circuit200repeats outputting the high signal mask in response to the count value cnt matching the count value ref, and outputting the low signal mask in response to the NMOS transistor26abeing turned on. This ensures that the timing at which the NMOS transistor26bis turned on is at or after the timing at which a half of the switching period Ta has elapsed since the NMOS transistor26ais turned on. Then, the switching control circuit43ccan drive the NMOS transistors26a,26bsuch that the two boost chopper circuits perform the interleaved operations to some extent.

The operation of the switching control circuit43chas been described above. Immediately after the load11enters the heavy load state, the switching control circuit43ccauses the two boost chopper circuits to operate the interleaved operation to some extent. However, due to variations in the circuit constants of the circuit elements configuring the AC-DC converter, changes in circuit constants due to temperature, and/or the like, the NMOS transistor26cmay not be driven in the critical mode in which the NMOS transistor26bis turned on immediately after the inductor current IL2reaches zero.

That is, in the above-described operation, depending on a condition, there may occur a waiting time from when the inductor current IL2reaches zero until the NMOS transistor26bis turned on. Thus, the above-mentioned phrase “the two boost chopper circuits perform the interleaved operation to some extent” means that in a strict sense, there may be a case in which the waveform of the inductor current IL2includes a time period of zero current and the NMOS transistor26bis driven in a discontinuous mode.

The following describes a switching control circuit43dincluding an error output circuit240that controls the ON period of the NMOS transistor26bbased on the switching period Ta of the NMOS transistor26aand the like such that the NMOS transistor26bis also driven in the critical mode.

==Configuration of Switching Control Circuit43d==

FIG.16is a diagram illustrating an example of the switching control circuit43d. The switching control circuit43doutputs the driving signals Vq1, Vq2, based on the inductor currents IL1, IL2, the feedback voltage Vfb, and the signal cmd, as with the switching control circuits43a,43b,43c. Specifically, the switching control circuit43doutputs the driving signal Vq1to turn on NMOS transistor26a, in response to the inductor current IL1reaching zero, and the voltage Vzcd1that corresponds to the inductor current IL1reaching the first predetermined voltage value, when the load11is in the heavy load state.

Thereafter, the switching control circuit43doutputs the driving signal Vq2to turn on the NMOS transistor26b, when a half of the switching period Ta of the NMOS transistor26ahas elapsed, the inductor current IL2reaches zero, and the voltage Vzcd2corresponding to the inductor current IL2reaches the second predetermined voltage value.

Further, the switching control circuit43ddrives the NMOS transistors26a,26bsuch that the interleaved operation is accurately performed, in response to the NMOS transistors26bbeing turned on twice or more. The switching control circuit43dincludes the command value output circuit100, the driving signal output circuit120, a driving signal output circuit260, the detection circuit200, and the error output circuit240.

The error output circuit240outputs an ON period Vv to adjust the ON period Vu, which is the ON period of the NMOS transistor26b, such that the two boost chopper circuits perform the interleaved operation based on the respective on-timings of the NMOS transistors26a,26b.

Specifically, the error output circuit240outputs the positive ON period Vv, in response to the on-timing of the NMOS transistor26badvancing with respect to the on-timing of the NMOS transistor26a. This causes a third ON period Vu to be longer than the ON period Vz, and the on-timing at which the NMOS transistor26bis turned on later is delayed.

Meanwhile, the error output circuit240outputs the negative ON period Vv, in response to the on-timing of the NMOS transistor26bbeing delayed with respect to the on-timing of the NMOS transistor26a. This causes the third ON period Vu to be shorter than the ON period Vz, and the on-timing at which the NMOS transistor26bis turned on later becomes earlier.

As described above, the principle of the error output circuit240is the same as that of the error output circuit160. The error output circuit240includes an RS flip-flop circuit242, a counter244, a divider circuit246, a subtractor circuit248, a voltage regulator circuit250, and a multiplier circuit252. Note that when the signal enb takes a value of “0”, the ON period Vv results in “0”, which will be described later in detail.

The RS flip-flop circuit242detects the time difference Tθ between the on timings of the NMOS transistors26a,26b. Specifically, upon receiving the high signal Vc1, the RS flip-flop circuit242outputs a high signal Q, and upon receiving the high signal Vc5, the RS flip-flop circuit242outputs a low signal Q. Accordingly, the RS flip-flop circuit242detects the time difference TO in the time period in which the signal Q is high.

The counter244counts the time period during which the signal Q from the RS flip-flop circuit242is high, that is, the time difference TO, and in response to the signal Q going low, the counter244outputs the time difference TO as the count value hcnt.

The divider circuit246is a circuit to calculate a ratio R. Specifically, the divider circuit246divides the count value hcnt by the count value sent from the sample-and-hold circuit206, that is, the switching period Ta of the NMOS transistor26a, to thereby output the ratio R as a signal div.

The subtractor circuit248calculates the difference between the ratio R and the predetermined ratio (i.e., “0.5”), to thereby output a result as an error E3.

The voltage regulator circuit250outputs the ON period Vv for the switching control circuit43dto implement the accurate interleaved operation, according to the error E3. Note the subtractor circuit248and the voltage regulator circuit250according to an embodiment of the present disclosure correspond to a so-called error amplifier circuit to perform amplification, integration, and the like of the error E3, for example.

When the signal enb is high, the multiplier circuit252multiplies the ON period Vv by “1”, to thereby output a result as the ON period Vv, and when the signal enb is low, the multiplier circuit252multiplies the ON period Vv by “0”, to thereby output a result as the ON period Vv. Note that the enable circuit (not illustrated) changes the signal enb to high, after the driving signal output circuit260outputs the driving signal Vq2to turn on the NMOS transistor26btwice or more, and changes the signal enb to low, in response to the load detection circuit12outputting the low signal cmd.

The driving signal output circuit260outputs the driving signal Vq2to drive the NMOS transistor26b, based on the voltage Vzcd2corresponding to the inductor current IL2, the ON periods Vz, Vv, and the signal mask. Specifically, the driving signal output circuit260outputs the driving signal Vq2to turn on the NMOS transistor26b, in response to the detection circuit200outputting the high signal mask, the inductor current IL2reaching zero, the voltage Vzcd2that corresponds to the inductor current IL2reaching the second predetermined value. Thereafter, the driving signal output circuit260outputs the driving signal Vq2to turn off the NMOS transistor26b, in response to the ON period Vu according to the ON periods Vz and Vv having elapsed. The driving signal output circuit260includes the comparator circuits142,148, the RS flip-flop circuit144, the counter146, the AND circuit222, and an adder circuit262.

The adder circuit262adds the ON period Vz from the command value output circuit100and the ON period Vv from the error output circuit240, to thereby output a result as the ON period Vu.

<<<Operation of Switching Control Circuit43dwhen the Load11Changes from Light Load State to Heavy Load State>>>

FIG.17is a diagram illustrating main waveforms of the switching control circuit43dwhen the load11changes from the light load state to the heavy load state. It is assumed that before time t50, the load11is in the light load state, and thus the load detection circuit12outputs the low signal cmd, and the feedback voltage Vfb is such a voltage at which the voltage regulator circuit104outputs the ON period Vx of “100. Further, the multiplier circuit110outputs the ON period Vy of “100”, and the multiplier circuit112outputs the ON period Vz of “0”.

Further, before time t50, the switching control circuit43dperforms the operation as described with reference toFIG.5. It is assumed that the switching period Ta of the NMOS transistor26ais “120”, and the sample-and-hold circuit206outputs the count value sont of “120”. Further, since the load detection circuit12is outputting the low signal cmd, the multiplier circuit208is outputting the count value ref of “0”.

At time t50, in response to the load detection circuit12detecting that the load11has changed from the light load state to the heavy load state, the load detection circuit12outputs the high signal cmd. In response to the load detection circuit12outputting the high signal cmd, the ratio output circuit106outputs the ratio ab of “0.5”. In response to the ratio ab of “0.5” being outputted, the subtractor circuit108outputs the ratio αa of “0.5”. In response to the ratios da, ab of “0.5” being outputted, the multiplier circuits110,112output the ON periods Vy, Vz of “50”, respectively.

At time t51, in response to the NMOS transistor26abeing turned on, the RS flip-flop circuit242outputs the high signal Q, and the counter244starts counting the time difference Tθ.

At time t52, in response to the NMOS transistor26bbeing turned on, the RS flip-flop circuit242outputs the low signal Q, and the counter244outputs the count value hcnt of “30”. Then, the divider circuit246outputs a signal div of “0.25”, based on the count value hcnt of “30” and the count value sont of “120”. However, the enable circuit is still outputting the low signal enb, and thus the ON period Vv remains “0”.

At time t53, in response to the NMOS transistor26abeing turned on, the sample-and-hold circuit206outputs the count value sont of “60”, and thus the divider circuit246outputs the signal div of “0.5”, based on the count value hcnt of “30” and the count value sont of “60”. Then, the voltage regulator circuit250outputs the ON period Vv of “0”.

At time t54after the NMOS transistor26bis turned on twice or more, the enable circuit outputs the high signal enb, and the error output circuit240outputs the ON period Vv of “0”.

Thereafter, the error output circuit240continues to output the ON period Vv based on the time difference TO and the switching period Ta. This enables the switching control circuit43dto drive the NMOS transistors26a,26bsuch that the two boost chopper circuits accurately perform the interleaved operation.

<<<Simulation Results of Switching Control Circuit43d>>>

FIG.18is a diagram illustrating simulation results of the switching control circuit43d. Here, the top diagram illustrates the results indicating changes in the signal cmd. The second diagram from the top illustrates the results indicating the inductor currents IL1, IL2. The third diagram from the top illustrates the results indicating the total current of the inductor currents IL1, IL2. Furthermore, the bottom diagram illustrates the results indicating the input current Iin. Note that the simulation results inFIG.18are the same as the simulation results inFIG.11, and thus the descriptions thereof are omitted.

<<<Enlarged View of Simulation Results of Switching Control Circuit43d>>>

FIG.19is an enlarged view of a portion corresponding to Time=14.9 to 15.1 ms of the simulation results of the switching control circuit43dinFIG.18. Further, the order in which the four simulation results are arranged is the same as that inFIG.18, and thus the description thereof is omitted. Further, inFIGS.19and20, the inductor current IL1is given by the solid line, and the inductor current IL2is given by the dashed line.

Around Time=15 ms, in response to the load detection circuit12outputting the high signal cmd, the command value output circuit100outputs the ON periods Vy, Vz of a half of the ON period Vx. Then, the driving signal output circuit140starts driving the NMOS transistor26b, in response to a quarter of the switching period Ta having elapsed since the NMOS transistor26ais turned on. The switching control circuit43ddrives the NMOS transistors26a,26bsuch that the two boost chopper circuits perform the interleaved operation, and thus the total current of the inductor currents IL1, IL2has a waveform in which ripples are superimposed on low frequency components and the amplitude of the ripples are small. Note that sinceFIG.19is an enlarged view of a time period corresponding to Time=14.9 to 15.1 ms, and thus the input current Iin hardly changes.

FIG.20is an enlarged view of a portion corresponding to Time=34.9 to 35.1 ms of the simulation results of the switching control circuit43dinFIG.18. Furthermore, the order in which the four simulation results are arranged is the same as inFIG.18, and thus the description thereof is omitted.

Around Time=35 ms, in response to the load detection circuit12outputting the low signal cmd, the command value output circuit100outputs the ON period Vy that is the ON period Vx, and the ON period Vz of “0”. Then, the driving signal output circuit260stops driving the NMOS transistor26b. In response to the driving of the NMOS transistor26bbeing stopped, the total current of the inductor currents IL1, IL2results in only the inductor current IL1. Note thatFIG.20is an enlarged view of a time period corresponding to Time=34.9 to 35.1 ms inFIG.18, and thus the input current Iin hardly changes.

A description has been given of an embodiment in which the load detection circuit12detects the state of the load11and the power factor correction IC25operates based on the signal cmd which is the detection result thereof. The method of detecting the state of the load11is not limited to the method of the load detection circuit12, and as will be described below, the state of the load11may be detected inside the power factor correction IC25.

FIG.21is a diagram illustrating a configuration of an AC-DC converter13which is an embodiment of the present disclosure. The AC-DC converter13is a boost power factor correction (PFC) circuit to generate the output voltage Vout at a target level from the AC voltage Vac of a commercial power supply, as with the AC-DC converter10. The AC-DC converter13is different from the AC-DC converter10in that there is no load detection circuit12to detect the state of the load11.

FIG.22is an example of a switching control circuit43e, which is an embodiment of the switching control circuit43. The switching control circuit43eis the same as the switching control circuit43aexcept that the signal cmd is generated internally instead of being received from the load detection circuit12. The switching control circuit43eincludes the command value output circuit100, the driving signal output circuits120,140, and a load detection circuit280.

The load detection circuit (LDET)280detects the state of the load11based on the ON period Vx. Specifically, in response to the ON period Vx decreasing below a third predetermined value corresponding to the first predetermined value, the load detection circuit280detects that the load11is in the light load state, to thereby output the low signal cmd, and in response to the ON period Vx exceeding a fourth predetermined value corresponding to the second predetermined value, the load detection circuit280detects that the load11is in the heavy load state, to thereby output the high signal cmd. Note that, as in the load detection circuit12, the third predetermined value and the fourth predetermined value for detecting that the load11is in the light load state or the heavy load state may be the same or different.

Further, the principle on which the load detection circuit280is able to detect the state of the load11as such is as follows. In response to the load11entering the light load state, the output voltage Vout rising, and the feedback voltage Vfb rising, the ON period Vx decreases because the ON period of at least one of the NMOS transistor26aor the NMOS transistor26bis reduced so as to lower the output voltage Vout. Thus, the load detection circuit280can detect that the load11is the light load state in response to the ON period Vx decreasing below the third predetermined value.

Meanwhile, in response to the load11entering the heavy load state, the output voltage Vout dropping, and the feedback voltage Vfb dropping, the ON period Vx increases because the ON period of at least one of the NMOS transistor26aor the NMOS transistor26bis increased so as to raise the output voltage Vout. Thus, the load detection circuit280can detect that the load11is in the heavy load state in response to the ON period Vx exceeding the fourth predetermined value. Note that the load detection circuit280corresponds to a “second overcurrent detection circuit”.

A description has been given of an embodiment in which the voltages Vzcd1, Vzcd2are converted into digital values by the AD converters40,41, and then they are compared to the predetermined value I0, to thereby generate the signals Vc1and Vc3indicating the timing at which the NMOS transistors26a,26bare turned on.

In the case of such an embodiment, when the frequencies of the voltages Vzcd1, Vzcd2are considered, the sampling frequency of the AC converter may result in being a high frequency, and the circuit scale of the AD converter may also result in being large. Thus, the following describes an embodiment using comparator circuits instead of the AD converters40,41.

<<<Example of Modification of Power Factor Correction IC25>>>

FIG.23is a diagram illustrating an example of the power factor correction IC25. In the power factor correction IC25, the AD converter40inFIG.2converts the voltage Vzcd1into a digital value, and then the comparator circuit122inFIG.3compares the voltage Vzcd1with the digital value corresponding to the current value I0, to thereby output the signal Vc1. Similarly, the AD converter41inFIG.2converts the voltage Vzcd2into a digital value, and then the comparator circuit142inFIG.3compares the voltage Vzcd2with a digital value corresponding to the current value I1, to thereby output the signal Vc3.

Meanwhile, the modification example of the power factor correction IC25includes the comparator circuits300,301that are analog circuits, instead of the AD converters40,41inFIG.2, a switching control circuit43f, instead of the switching control circuit43.

Further, the comparator circuit300compares the voltage Vzcd1with a reference voltage Vref0corresponding to the current value I0, to thereby output the high signal Vc1, in response to the voltage Vzcd1dropping below the reference voltage Vref0. Further, the comparator circuit300outputs the low signal Vc1, in response to the voltage Vzcd1exceeding the reference voltage Vref0.

Similarly, the comparator circuit301compares the voltage Vzcd2with the reference voltage Vref1corresponding to the current value I1, and the comparator circuit301outputs the high signal Vc3, in response to the voltage Vzcd2dropping below the reference voltage Vref1. Further, the comparator circuit301outputs the low signal Vc3, in response to the voltage Vzcd2exceeding the reference voltage Vref1.

The switching control circuit43foperates, as with the switching control circuit43a, based on the signal Vc1from the comparator circuit300and the signal Vc3from the comparator circuit301. As described above, in the modification example of the power factor correction IC25, the AD converter40and the comparator circuit122of the power factor correction IC25are replaced with the comparator circuit300, and the AD converter41and the comparator circuit142of the power factor correction IC25are replaced with the comparator circuit301.

In the case of the power factor correction IC25, the AD converters40,41need a sampling interval to capture the instantaneous value of the switching waveform that reaches several 100 kHz at the maximum, and thus need the sampling frequency of at least several MHz. However, the power factor correction IC25being deformed as described above negates the need for the sampling frequency of several MHz, thereby being able to save the area of the power factor correction IC25and reduce the power consumption of the integrated circuit.

A description has been given of an embodiment in which the power factor correction IC25drives the NMOS transistors26a,26b. However, it is apparent that the NMOS transistors driven by the power factor correction IC25are not limited to two, and may be multiple (e.g., three or more). Further, those skilled in the art who have been exposed to the above described explanation would have easily conceived of a power factor correction IC that drives a plurality of NMOS transistors.

A description has been given of the AC-DC converter10according to an embodiment of the present disclosure. The switching control circuit43aincludes the command value output circuit100, and the driving signal circuits120,140, and the buffer circuits44,45drive the NMOS transistors26a,26b, in response to the driving signals Vq1, Vq2from the driving signal output circuits120,140. The command value output circuit100is configured to, when the load11is in the light t load state, output only the ON period Vx corresponding to the output voltage Vout, and when the load11is in the heavy load state, the command value output circuit100outputs the ON periods Vy, Vz corresponding to the output voltage Vout. Further, the switching control circuit43adrives both the NMOS transistors26a,26bwith the ON period corresponding to the output voltage Vout so that the output voltage Vout does not fluctuate, when the current value of the load current Iload increases and the load11enters the heavy load state. This makes it possible to provide the switching control circuit that suppresses a disturbance of the input current caused by start of a parallel operation.

Further, the ON period Vy, Vz when the load11changes from the light load state to the heavy load state is shorter than the ON period Vx at a time when the load11is in the light load state immediately before changing. This enables the switching control circuit43ato suppress a rise in the output voltage Vout and suppress a disturbance of the input current caused by control of a direct current voltage control system based on fluctuations of the output voltage Vout.

Further, when the load11enters the heavy load state, the command value output circuit100outputs the ON periods Vy, Vz equal to a half of the ON period Vx. This enables the switching control circuit43ato suppress a rise in the output voltage, regardless of the magnitude of the current value of the load current Iload, even if the two boost chopper circuits perform a parallel operation.

The switching control circuit43cincludes the counter204, and the driving signal output circuit220outputs the driving signal Vq2to turn on the NMOS transistor26b, in response to a quarter of the switching period Ta before the load11enters the heavy load state having elapsed and the inductor current IL2reaching zero. This makes it possible that the switching control circuit43ccauses the two boost chopper circuit to perform the interleaved operation to some extent.

The driving signal output circuit220outputs the driving signal Vq2to turn on the NMOS transistor26b, in response to the load11entering the heavy load state, a half of the switching period Ta after the load11enters the heavy load state having elapsed after the NMOS transistor26bis turned on once, and the inductor current IL2reaching zero. This enables the switching control circuit43cto turn on the NMOS transistor26bin the vicinity of the middle of the switching period Ta after the load11changes from the light load state to the heavy load state.

The switching control circuits43b,43dinclude the error output circuits160,240, respectively. This makes it possible that the switching control circuits43b,43dcause the two boost chopper circuits to continue to accurately perform the interleaved operation, even if the circuit constants of the circuit elements change due to the heat generated by the operation of the AC-DC converter10.

The AC-DC converter10includes the load detection circuit12. This enables the switching control circuits43ato43dto determine the state of the load11, based on the signal cmd from the load detection circuit12.

The switching control circuit43eincludes the load detection circuit280. This enables the switching control circuit43eto determine the state of the load11, based on the ON period Vx corresponding to the output voltage Vout.

The present disclosure is directed to provision of a switching control circuit that suppresses a disturbance of an input current caused by start of a parallel operation.

According to the present disclosure, it is possible to provide a switching control circuit that suppresses a disturbance of an input current caused by start of a parallel operation.

An embodiment of the present disclosure described above is simply to facilitate understanding of the present disclosure and is not in any way to be construed as limiting the present disclosure. The present disclosure may variously be changed or altered without departing from its essential features and encompass equivalents thereof.