Non-volatile memory device, erasing method thereof, and memory system including the same

Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate.

BACKGROUND

The present disclosure herein relates to a semiconductor memory, and more particularly, to a nonvolatile memory device, an erasing method thereof, and a memory system including the same.

A semiconductor memory device is a memory device that is implemented with semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs) and indium phosphide (InP). Semiconductor memory devices may be largely divided into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored are erased when a power source is shut off. Examples of volatile memory devices include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM). A nonvolatile memory device is a memory device that retains stored data even when a power source is shut off. Examples of nonvolatile memory devices include Read-Only Memory (ROM), Programmable Read Only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), Electrical Erasable Programmable Read Only Memory (EEPROM), flash memory devices, Phase-change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Resistive Random Access Memory (RRAM) and Ferroelectric Random Access Memory (FRAM). Flash memory devices may be largely categorized into a NOR type and a NAND type.

SUMMARY

The present disclosure provides a nonvolatile memory device for example, having a 3-dimensional array structure, an erasing method thereof, and a memory system including the same.

Embodiments of inventive concepts provide an erasing method of a nonvolatile memory device having a memory string including a plurality of memory cells, a string selection transistor, and a ground selection transistor, the erasing method comprising applying a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applying a specific voltage to a ground selection line connected to the ground selection transistor, applying an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floating the ground selection line in response to a voltage change of the substrate.

In example embodiments, the applying of a specific voltage comprises applying a ground voltage to the ground selection line.

In example embodiments, the floating of the ground selection line is performed when the voltage level of the substrate reaches a target voltage level.

In example embodiments, the memory cells are stacked in a direction vertical to the substrate.

Embodiments of inventive concepts provide a nonvolatile memory device comprising a memory cell array comprising a plurality of memory cell strings which are provided onto a substrate, a reading and writing circuit connected to the memory cell strings through a plurality of bit lines, and configured to drive the bit lines, an address decoder connected to the memory cell strings through a plurality of word lines, a string selection line and a ground selection line, and configured to drive the word lines and the selection lines, and a substrate monitor circuit monitoring a voltage level of the substrate wherein the address decoder drives the ground selection line according to a monitored result in an erasing operation.

In example embodiments, when an erasing voltage for the erase operation is started to be applied to the substrate, the address decoder is configured to drive the ground selection line to a ground voltage.

In example embodiments, during the erasing operation, the address decoder is configured to float the ground selection line when a voltage level of the substrate reaches a target voltage level.

In example embodiments, the substrate monitor circuit comprises first and second trimmers connected between a ground node and a substrate node to which a voltage of the substrate is provided and a comparator configured to compare a target voltage and a voltage of a node between the first and second trimmers to output the monitored result.

Embodiments of inventive concepts provide an erasing method of nonvolatile memory device, the method comprising providing the nonvolatile memory device including a memory string perpendicular to a substrate of a first conductivity, the memory string including a string select transistor, a plurality of memory cells and a ground select transistor using a pillar active body of the first conductivity contacting the substrate, applying a word line erase voltage to a plurality of word lines connected to the plurality of memory cells, applying a voltage to a ground selection line connected to the ground select transistor, applying an erase voltage to the substrate, and floating the ground selection line in response to a voltage shift of the substrate.

Embodiments of inventive concepts provide a nonvolatile memory device, comprising a substrate, a memory string including a string select transistor, a plurality of memory cells and a ground select transistor using a pillar active body of a first conductivity contacting the substrate, an address decoder configured to apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells and apply a voltage to a ground selection line connected to the ground select transistor, a substrate bias circuit configured to apply an erase voltage to the substrate, and a substrate monitor circuit configured to sense a voltage shift of the substrate, wherein the address decoder floats the ground selection line in response to the voltage shift of the substrate.

Embodiments of inventive concepts provide An erasing method of a nonvolatile memory device including a substrate and a plurality of memory blocks, each including a plurality of memory strings in a two-dimensional array, each including a string selection transistor, a plurality of memory cells, and a ground selection transistor, the plurality of memory strings arranged in rows and columns, wherein columns of the plurality of memory strings are each connected to a corresponding bit line by the corresponding string selection transistor and rows of the plurality of memory strings are each connected to a corresponding string select line by the corresponding string selection transistor, the method comprising selecting one of the plurality of memory blocks for erasing, applying a word line erase voltage to a plurality of word lines connected to the plurality of memory cells of the selected memory block, applying a voltage to a ground selection line connected to the ground select transistor of the selected memory block and not to at least one unselected memory blocks, applying an erase voltage to the substrate, and floating the ground selection line of the selected memory block in response to a voltage shift of the substrate.

In example embodiments, the ground selection lines connected to the ground select transistors of the at least one unselected memory blocks are allowed to float.

In example embodiments, the voltage applied to the ground selection line connected to the ground select transistor of the selected memory block is a ground voltage.

In example embodiments, the voltage applied to the ground selection line connected to the ground select transistor of the selected memory block is allowed to float after the erase voltage reaches a threshold voltage.

In example embodiments, methods may further comprise monitoring a voltage of the substrate and when the voltage of the substrate reaches a threshold voltage, ceasing to apply the voltage to the ground selection line connected to the ground select transistor of the selected memory block.

In example embodiments, methods may further comprise floating the string selection lines connected to the string selection transistors for each of the plurality of memory blocks.

Embodiments of inventive concepts provide a nonvolatile memory device, comprising a substrate, a plurality of memory blocks, each including a plurality of memory strings in a two-dimensional array, each string including a string selection transistor, a plurality of memory cells, and a ground selection transistor, the plurality of memory strings arranged in rows and columns, wherein columns of the plurality of memory strings are each connected to a corresponding bit line by the corresponding string selection transistor and rows of the plurality of memory strings are each connected to a corresponding string select line by the corresponding string selection transistor, an address decoder configured to select one of the plurality of memory blocks for erasing, apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells of the selected memory block, apply a voltage to a ground selection line connected to the ground select transistor of the selected memory block and not to the unselected memory blocks, a substrate bias circuit configured to apply an erase voltage to the substrate, and a substrate monitor circuit configured to sense a voltage shift of the substrate, wherein the address decoder float the ground selection line floating in response to the voltage shift of the substrate.

In example embodiments, the address decoder allows the ground selection lines connected to the ground select transistors of the unselected memory blocks to float.

In example embodiments, the address decoder applies a ground voltage to the ground selection line connected to the ground select transistor of the selected memory block.

In example embodiments, the address decoder allows the voltage of the ground selection line connected to the ground select transistor of the selected memory block to float after the erase voltage reaches a threshold voltage.

In example embodiments, nonvolatile memory device may further comprise a substrate monitor circuit, adapted to monitor a voltage of the substrate and when the voltage of the substrate reaches a threshold voltage generate a ground enable signal, the address decoder ceasing to apply the voltage to the ground selection line connected to the ground select transistor of the selected memory block, in response to the ground enable signal and then floating the ground selection line.

In example embodiments, the substrate monitor circuit may further include first and second trimmers connected between a ground node and a substrate node to which the erase voltage of the substrate is provided and a comparator configured to compare a target voltage and a voltage of a node between the first and second trimmers and output a comparison result to the address decoder.

In example embodiments, if the comparison result indicates the voltage of the substrate has reached the threshold voltage, the address decoder stops applying the voltage to a ground selection line connected to the ground select transistor of the selected memory block.

In example embodiments, the address decoder may further float the string selection line for each of the plurality of memory blocks.

In example embodiments, the address decoder may further include at least two block word line drivers, each configured to generate a block selection signal, a string selection line driver, configured to drive a string selection line of the plurality of memory blocks in response to the block selection signal, a word line driver, configured to drive word lines of the plurality of memory blocks in response to the block selection signal, a ground selection line driver, configured to drive a ground select line of one of the plurality of memory blocks and to receive the ground enable signal from the substrate monitor circuit and a pass circuit, configured to transfer voltages driven by the string selection line driver, the word line driver, and the ground selection line driver to the corresponding lines of the selected one of the plurality of memory blocks in response to the block selection signal.

In example embodiments, the pass circuit includes a plurality of transistors, one to control each of the word lines, each of the string select lines, and each of the ground selection lines.

Embodiments of inventive concepts provide a nonvolatile memory device comprising a memory cell array comprising a plurality of memory cell strings which are provided onto a substrate, a reading and writing circuit connected to the memory cell strings through a plurality of bit lines, and configured to drive the bit lines, and an address decoder connected to the memory cell strings through a plurality of word lines, a string selection line and a ground selection line, and configured to drive the word lines and the selection lines; wherein the address decoder drives the ground selection line in an erasing operation by waiting a delay time before applying a voltage to the substrate.

In example embodiments, when an erasing voltage for the erase operation is started to be applied to the substrate, the address decoder is configured to drive the ground selection line to a ground voltage.

In example embodiments, during the erasing operation, the address decoder is configured to float the ground selection line when a voltage level of the substrate reaches a target voltage level.

Embodiments of inventive concepts provide a nonvolatile memory device, comprising a substrate, a memory string including a string select transistor, a plurality of memory cells and a ground select transistor using a pillar active body of a first conductivity contacting the substrate, an address decoder configured to apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells and apply a voltage to a ground selection line connected to the ground select transistor, a substrate bias circuit configured to apply an erase voltage to the substrate, and wherein the address decoder waits a delay time and then floats the ground selection line in response to the voltage shift of the substrate.

Embodiments of inventive concepts provide a nonvolatile memory device, comprising a substrate, a plurality of memory blocks, each including a plurality of memory strings in a two-dimensional array, each string including a string selection transistor, a plurality of memory cells, and a ground selection transistor, the plurality of memory strings arranged in rows and columns, wherein columns of the plurality of memory strings are each connected to a corresponding bit line by the corresponding string selection transistor and rows of the plurality of memory strings are each connected to a corresponding string select line by the corresponding string selection transistor, an address decoder configured to select one of the plurality of memory blocks for erasing, apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells of the selected memory block, apply a voltage to a ground selection line connected to the ground select transistor of the selected memory block and not to the unselected memory blocks, and a substrate bias circuit configured to apply an erase voltage to the substrate, wherein the address decoder waits a delay time and then floats the ground selection line in response to the voltage shift of the substrate.

In example embodiments, the address decoder allows the ground selection lines connected to the ground select transistors of the unselected memory blocks to float.

In example embodiments, the address decoder applies a ground voltage to the ground selection line connected to the ground select transistor of the selected memory block.

In example embodiments, the address decoder allows the voltage of the ground selection line connected to the ground select transistor of the selected memory block to float after the erase voltage reaches a threshold voltage.

In example embodiments, the address decoder may further float the string selection line for each of the plurality of memory blocks.

In example embodiments, the address decoder may further include at least two block word line drivers, each configured to generate a block selection signal, a string selection line driver, configured to drive a string selection line of the plurality of memory blocks in response to the block selection signal, a word line driver, configured to drive word lines of the plurality of memory blocks in response to the block selection signal, a ground selection line driver, configured to drive a ground select line of one of the plurality of memory blocks and to receive a time delay signal and a pass circuit, configured to transfer voltages driven by the string selection line driver, the word line driver, and the ground selection line driver to the corresponding lines of the selected one of the plurality of memory blocks in response to the block selection signal.

In example embodiments, the pass circuit includes a plurality of transistors, one to control each of the word lines, each of the string select lines, and each of the ground selection lines. address decoderaddress decoderaddress decoderaddress decoderaddress decoderaddress decoder

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments of inventive concepts will be described below in more detail with reference to the accompanying drawings. The inventive concepts may, however, be embodied in different forms and should not be construed as limited to example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of inventive concepts to those skilled in the art. Like reference numerals refer to like elements throughout. Similar reference numerals refer to similar elements throughout.

FIG. 1is a block diagram illustrating a nonvolatile memory device100according to example embodiments of inventive concepts.

Referring toFIG. 1, a nonvolatile memory device100according to an embodiment of the inventive concept includes a memory cell array110, an address decoder120(which also acts as an address decoder), a substrate monitor circuit130, a reading and writing circuit140, a control logic150, and/or a substrate bias circuit160.

The memory cell array110is connected to the address decoder120through selection lines that include word lines WL, string selection lines SSL and ground selection lines GSL. The memory cell array110is connected to the reading and writing circuit140through bit lines BL. The memory cell array110is connected to the substrate monitor circuit130. For example, a substrate which the memory cell array110is formed on is connected to the substrate monitor circuit130. The memory cell array110is connected to the substrate bias circuit160. For example, the substrate which the memory cell array110is formed on is connected to the substrate bias circuit160. For example, the substrate is a P type well formed in a N type well in a semiconductor substrate.

The memory cell array110includes a plurality of memory blocks. Each of the memory blocks includes a plurality of memory cell strings. For example, the each memory block includes a plurality of NAND strings. Each of the memory cell strings includes a plurality of memory cells and a plurality of selection transistors. For example, the each memory cell string may include at least one string selection transistor and at least one ground selection transistor.

Exemplarily, each of the memory cells arranged in the row direction are respectively connected to a corresponding one of the word lines WL. Memory cells arranged in the column direction in one string are connected to a corresponding one of the bit lines BL. For example, the memory cells arranged in the column direction may configure a plurality of cell groups (for example, a string). Furthermore, the plurality of cell groups are respectively connected to the bit lines BL. At least one string selection transistor is connected to the string selection lines SSL. At least one ground selection transistor is connected to the ground selection lines GSL. Exemplarily, the memory cell array110may store one or more bits in each cell.

The address decoder120is connected to the memory cell array110through the word lines WL, the string selection lines SSL and the ground selection lines GSL. The address decoder120operates according to the control of the control logic150. The address decoder120receives an address ADDR inputted from an external device.

The address decoder120decodes a row address of the received address ADDR. The address decoder120selects a memory block of the memory cell array110by using the decoded row address. Also, the address decoder120selects the word lines WL, string selection lines SSL and ground selection lines GSL of the selected memory block by using the decoded row address. The address decoder120additionally decodes a column address of the received address ADDR. The decoded column address, though not shown, is transferred to the reading and writing circuit140.

Exemplarily, the address decoder120receives a ground enable signal GE from the substrate monitor circuit130. In response to the received ground enable signal GE, the address decoder120controls an output voltage of signals on the WL, SSL and GSL. For example, the address decoder120operates in response to the ground enable signal GE during an erasing operation.

The substrate monitor circuit130is connected to the memory cell array110and the address decoder120. The substrate monitor circuit130operates according to the control of the control logic150. The substrate monitor circuit130monitors a substrate voltage Vsub of the substrate of the memory cell array110. The substrate monitor circuit130activates or deactivates the ground enable signal GE according to the level of the substrate voltage Vsub of the substrate of the memory cell array110. The ground enable signal GE is transferred to the address decoder120. For example, the substrate monitor circuit130is enabled for an erasing operation.

The reading and writing circuit140is connected to the memory cell array110through the bit lines BL. The reading and writing circuit140operates according to the control of the control logic150. The reading and writing circuit140receives the decoded column address from the address decoder120. The reading and writing circuit140selects some bit lines of the bit lines BL in response to the decoded column address.

Exemplarily, the reading and writing circuit140receives data DATA from an external device, for example, a controller and writes the received data DATA into the memory cell array110. The reading and writing circuit140reads the written data DATA from the memory cell array110and outputs the read data DATA to the outside. The reading and writing circuit140reads data from a first storage region of the memory cell array110and writes the read data in a second storage region of the memory cell array110. For example, the reading and writing circuit140performs a copy-back operation.

Exemplarily, the reading and writing circuit140includes elements such as a page buffer (or page register) and/or a column selection circuit. As another example, the reading and writing circuit140includes elements such as a sensing amplifier, a writing driver and/or a column selection circuit.

The control logic150is connected to the address decoder120, the substrate monitor circuit130and the reading and writing circuit140. For example, the control logic150may be additionally connected to the substrate bias circuit160. The control logic150controls the overall operation of the nonvolatile memory device100. The control logic150operates in response to a control signals CTRL from an external device.

The substrate bias circuit160operates according to the control of the control logic150. The substrate bias circuit160biases the substrate on which the memory cell array110is formed. For example, the substrate bias circuit160biases an erase voltage Vers to the substrate on which the memory cell array110is formed.

In other example embodiments, the substrate monitor circuit130may be omitted. In such example embodiments, the address decoder120drives the ground selection line GSL in an erasing operation by waiting a delay time before applying a voltage to the substrate of the memory cell array110. In example embodiments, the time delay may be predetermined. In example embodiments, the length of the time delay may be provided by the control logic150or an external device.

FIG. 2is a block diagram of the memory cell array110ofFIG. 1. Referring toFIG. 2, the memory cell array110includes a plurality of memory blocks BLK1to BLKz. Each of the memory blocks BLK has a three-dimensional structure (or vertical structure). For example, each memory block BLK includes structures extending in first to third directions. For instance, each memory block BLK includes a plurality of NAND strings NS extending in the second direction. For example, a plurality of NAND strings NS may be provided in the first and third directions, for example, in a two-dimensional array of NAND strings NS.

Each NAND string NS is connected to a bit line BL, a string select line SSL, a ground select line GSL, the word lines WL, and a common source line CSL. Each of the memory blocks is connected to the plurality of bit lines BL, the plurality of string select lines SSL, the plurality of ground select lines GSL, the plurality of word lines WL, and the common source line CSL. The memory blocks BLK1to BLKz will be more fully described with reference toFIG. 3.

The memory blocks BLK1to BLKz are selected by the address decoder120illustrated inFIG. 1. For instance, the address decoder120is configured to select at least one memory block BLK corresponding to the decoded row address among the memory blocks BLK1to BLKz.

FIG. 3is a perspective view illustrating example embodiments of one memory block BLKi of the memory blocks BLK1to BLKz inFIG. 2.FIG. 4is a cross-sectional view taken along line I-I′ of the memory block BLKi ofFIG. 3. Referring toFIGS. 3 and 4, the memory block BLKi includes structures extending in the first to third directions.

First, a substrate111is provided. The substrate111may be a well having a first type (e.g., first conductive type). For example, the substrate111may be a p-type well formed by implanting Group III elements such as boron (B). For example, the substrate111is a p-type pocket well provided in an n-type well. Hereinafter, it is assumed that the substrate111be a p-type well (or p-type pocket well). However, the conductive type of the substrate111is not limited to the p-type well.

A plurality of doping regions311to314extending in a first direction are provided on the substrate111. For example, the plurality of doping regions311to314may have a second type (e.g., second conductive type) differing from that of the substrate111. Hereinafter, it is assumed that the first to fourth doping regions311to314have an n-type. However, the conductive types of the first to fourth doping regions311to314are not limited to the n-type.

A plurality of insulation materials112extending in the first direction are sequentially provided in a second direction over a region of the substrate111between the first and second doping regions311and312. For example, the plurality of insulation materials112may be provided in the second direction such that they are spaced by a predetermined or desired distance. The insulation material112may include an insulator such as silicon oxide.

A plurality of pillars113are provided, which are disposed in the first direction on the region of the substrate111between the first and second doping regions311and312and penetrate the insulation materials112in the second direction. Exemplarily, the plurality of pillars113penetrate the insulation materials112to contact the substrate111.

Each of the pillars113may be composed of a plurality of materials. For instance, a surface layer114of each pillar113may include a silicon material having a first type. For example, the surface layer114of each pillar113may include a silicon material having the same type as the substrate111. Hereinafter, it is assumed that the surface layer114of each pillar113includes p-type silicon. However, the surface layer114of each pillar113is not limited to including p-type silicon.

An inner layer115of each pillar113is composed of an insulation material. For example, the inner layer115of each pillar113may include an insulation material such as silicon oxide. For example, the inner layer115of each pillar113may include an air gap. Also a void may be formed in the inner layer115.

In a region between the first and second doping regions311and312, an insulation layer116is provided along exposed surfaces of the insulation materials112, the pillars113, and the substrate111. Exemplarily, the insulation layer116provided on the exposed side of the last insulation material112disposed in the second direction may be removed along the second direction.

For example, the thickness of the insulation layer116may be less than a half of the distance between the insulation materials112. That is, a region, in which any material other than the insulation materials112and the insulation layer116may be disposed, may be provided between the insulation layer116provided on an undersurface of the first insulation material and the insulation layer116provided on a top surface of the second insulation material under the first insulation material of the insulation material112.

In the region between the first and second doping regions311and312, first conductive materials211to291are provided on an exposed surface of the insulation layer116. For example, the first conductive material211extending in the first direction is provided between the substrate111and the insulation layer adjacent thereto. More specifically, the first conductive material211extending in the first direction is provided between the substrate111and the insulation layer116disposed under the insulation material112adjacent to the substrate111. Between the insulation layer116on a top surface of a specific insulation material and the insulation layer disposed on an undersurface of an insulation layer provided on top of the specific insulation material among the insulation materials112, the first conductive material extending in the first direction is provided. Exemplarily, a plurality of first conductive materials221to281extending in the first direction are provided between the insulation materials112. Exemplarily, the first conductive materials211to291may be a metallic material. Exemplarily, the first conductive materials211to291may be a conductive material such as polysilicon.

A structure identical to a structure disposed on the first and second doping regions311and312is provided in a region between the second and third doping regions312and313. Exemplarily, the plurality of insulation materials112extending in the first direction, the plurality of pillars113which are sequentially arranged in the first direction and penetrate the plurality of insulation materials112in the third direction, the insulation layer116provided on the plurality of insulation materials112and the exposed surface of the plurality of pillars112, and the plurality of first conductive materials212to292extending in the first direction are provided in the region between the second and third doping regions312and313.

A structure identical to a structure disposed on the first and second doping regions311and312is provided in a region between the third and fourth doping regions313and314. Exemplarily, the plurality of insulation materials112extending in the first direction, the plurality of pillars113which are sequentially arranged in the first direction and penetrate the plurality of insulation materials112in the third direction, the insulation layer116provided on the plurality of insulation materials112and the exposed surface of the plurality of pillars113, and the plurality of first conductive materials213to293extending in the first direction are provided in the region between the third and fourth doping regions313and314.

Drains320are respectively provided on the plurality of pillars113. Exemplarily, the drains320may include a silicon material doped with a second type material. For example, the drains320may include a silicon material doped with an n-type material. Hereinafter, it is assumed that the drains320include a silicon material doped with an n-type material. However, the drains320are not limited to including n-type silicon materials.

Exemplarily, the width of each drain320may be greater than the width of the pillar113corresponding thereto. For example, each drain320may be provided in the shape of a pad on the top surface of the corresponding pillar113. Exemplarily, each of the drains320may extend up to a portion of the surface layer114of the corresponding pillar113.

Second conductive materials331to333extending in the third direction are provided on the drains320. The second conductive materials331to333are arranged in the first direction such that they are spaced apart from each other by a predetermine or desired distance. The second conductive materials331to333are respectively connected to the drains320in the corresponding region. Exemplarily, the drains320and the second conductive material333extending in the third direction may be connected to each other through respective contact plugs. Exemplarily, the second conductive materials331to333may be a metallic material. Exemplarily, the second conductive materials331to333may be a conductive material such as polysilicon.

Hereinafter, heights of the first conductive materials211to291,212to292, and213to293will be defined. The first conductive materials211to291,212to292, and213to293are defined to have first to ninth heights from the substrate111sequentially. That is, the first conductive materials211to213adjacent to the substrate111have the first height. The first conductive materials291to293adjacent to the second conductive materials331to333have the ninth height. As an order of the specific conductive materials of the first conductive materials211to291,212to292, and213to293increases from the substrate111, the height of the first conductive material increases.

InFIGS. 3 and 4, each of the pillars113forms a string together with the insulation layer116and the plurality of first conductive materials211to291,212to292, and213to293. For example, each pillar113, acting as a common active pillar, forms a NAND string NS together with a region adjacent to the insulation layer116and an adjacent region of the first conductive materials211to291,212to292, and213to293. The NAND string NS includes a plurality of transistor structures TS. The transistor structure TS will be more fully described with reference toFIG. 5. In example embodiments, a subset of the plurality of transistor structures TS in any given string may be referred to as a substring.

FIG. 5is a cross-sectional view illustrating the transistor structure TS ofFIG. 4. Referring toFIGS. 3 to 5, the insulation layer116includes first to third sub insulation layers117,118and119. The surface layer114of the pillar113containing p-type silicon may act as a body. The first sub insulation layer117adjacent to the pillar113may act as a tunneling insulation layer. For example, the first sub insulation layer117adjacent to the pillar113may include a thermal oxide layer.

The second sub insulation layer118may act as a charge storage layer. For example, the second sub insulation layer118may act as a charge trap layer. For example, the second sub insulation layer118may include a nitride layer or a metal oxide layer (e.g., aluminum oxide layer, hafnium oxide layer, etc.).

The third sub insulation layer119adjacent to the first conductive material233may act as a blocking insulation layer. Exemplarily, the third sub insulation layer119adjacent to the first conductive material133extending in the first direction may have a mono-layered or multi-layered structure. The third sub insulation layer119may be a high dielectric layer (e.g., aluminum oxide layer, hafnium oxide layer, etc.) having a higher dielectric constant than the first and second sub insulation layers117and118.

The first conductive material233may act as a gate (or control gate). That is, the first conductive material233acting as the gate (or control gate), the third sub insulation layer119acting as the blocking insulation layer, the second sub insulation layer118acting as the charge trap layer, the first sub insulation layer117acting as the tunneling insulation layer, and the surface layer114that contains p-type silicon and acts as the body, may form a transistor (or memory cell transistor structure). Exemplarily, the first to third sub insulation layers117to119may form an ONO structure (oxide-nitride-oxide). Hereinafter, the surface layer114of the pillar113containing p-type silicon is defined to act as the body in the second direction. In example embodiments, the angles between layers of the pillar113, the insulation layer116, and the first conductive material233may be right angles, acute angles or obtuse angles.

In the memory block BLKi, one pillar113corresponds to one NAND string NS. The memory block BLKi includes the plurality of pillars113. That is, the memory block BLKi includes the plurality of NAND strings NS. More specifically, the memory block BLKi includes a plurality of NAND strings NS extending in the second direction (or direction perpendicular to the substrate).

Each of the NAND strings NS includes the plurality of transistor structures TS which are stacked in the second direction. At least one of the plurality of transistor structures TS of each NAND string NS acts as a string select transistor SST. At least one of the plurality of transistor structures TS of each NAND string acts as a ground select transistor GST. In example embodiments, a substring of the plurality of transistor structures TS may omit the string select transistor SST and/or the ground select transistor GST.

The gates (or control gates) correspond to the first conductive materials211to291,212to292, and213to293extending in the first direction. That is, the gates (or control gates) form word lines WL extending in the first direction, and at least two select lines SL (for example, at least one string select line SSL and at least one ground select line GSL).

The second conductive materials331to333extending in the third direction are connected to one ends of the NAND strings NS. For example, the second conductive materials331to333extending in the third direction act as bit lines BL. That is, in one memory block BLKi, one bit line BL is connected to the plurality of NAND strings.

The second type doping regions311to314extending in the first direction are provided at the other ends of the NAND strings NS. The second type doping regions311to314extending in the first direction act as a common source line CSL.

In summary, the memory block BLKi includes the plurality of NAND strings NS extending in a direction (second direction) perpendicular to the substrate111, and operate as a NAND flash memory block (e.g., charge trap type) in which the plurality of NAND strings NS are connected to one bit line BL.

InFIGS. 3 to 5, it has been described that the first conductive materials211to291,212to292, and213to293are provided on nine layers. However, the first conductive materials211to291,212to292, and213to293are not limited to being provided on the nine layers. For example, the first conductive materials may be provided upon at least eight layers forming memory cells, and at least two layers forming select transistors. Also, the first conductive materials may be provided upon a plurality of layers forming memory cells, and at least two layers forming select transistors. For example, the first conductive materials may also be provided on a layer forming dummy memory cells.

InFIGS. 3 to 5, it has been described that three NAND strings NS are connected to one bit line BL. However, it is not limited that three NAND strings NS are connected to one bit line BL. Exemplarily, m number of NAND strings NS may be connected to one bit line BL in the memory block BLKi. Here, the number of the first conductive materials211to291,212to292, and213to293extending in the first direction, and the number of doping regions311to314acting as the common source line CSL may also be adjusted so as to correspond to the number of NAND strings NS connected to one bit line BL.

InFIGS. 3 to 5, it has been described that three NAND strings NS are connected to one of the first conductive materials extending in the first direction. However, it is not limited that three NAND strings NS are connected to one of the first conductive materials. For example, n number of NAND strings NS may be connected to one of the first conductive materials. Here, the number of the second conductive materials331to333extending in the third direction may also be adjusted to correspond to the number of NAND strings NS connected to one of the first conductive materials.

As illustrated inFIGS. 3 to 5, a sectional area of the pillar113in the first and third directions may be smaller as the pillar113gets closer to the substrate111. For example, the sectional area of the pillar113in the first and third directions may be varied due to process characteristics or errors.

Exemplarily, the pillar113is formed by filling a material such as silicon and insulating materials into a hole formed by etching. As the etched depth is greater, an area of the hole in the first and third directions which is formed by etching may be smaller. That is, the sectional area of the pillar113in the first and third directions may be smaller as the pillar113gets closer to the substrate111.

FIG. 6is a circuit diagram illustrating an equivalent circuit BLKi according to example embodiments of the memory block BLKi described with reference toFIGS. 3 to 5. Referring toFIGS. 3 to 6, NAND strings NS11to NS31are provided between a first bit line BL1and a common source line CSL. NAND strings NS12, NS22and NS32are provided between a second bit line BL2and the common source line CSL. NAND strings NS13, NS23and NS33are provided between a third bit line BL3and the common source line CSL. The first to third bit lines BL1to BL3respectively correspond to the second conductive materials331to333extending in the third direction.

A string select transistor SST of each NAND string NS is connected to the corresponding bit line BL. A ground select transistor GST of each NAND string NS is connected to the common source line CSL. Memory cells MC are provided between the string select transistor SST and the ground select transistor GST of each NAND string NS.

Hereinafter, the NAND strings NS are defined in units of rows and columns. The NAND strings NS commonly connected to one bit line form one column. For example, the NAND strings NS11to NS31connected to the first bit line BL1correspond to a first column. The NAND strings NS12to NS32connected to the second bit line BL2correspond to a second column. The NAND strings NS13to NS33connected to the third bit line BL3correspond to a third column.

The NAND strings NS connected to one string select line SSL form one row. For example, the NAND strings NS11to NS13connected to the first string select line SSL1form a first row. The NAND strings NS21to NS23connected to the second string select line SSL2form a second row. The NAND strings NS31to NS33connected to the third string select line SSL3form a third row.

A height is defined in each NAND string NS. Exemplarily, the height of the ground select transistor GST is defined as 1 in each NAND string NS. The height of the memory cell MC1adjacent to the ground select transistor GST is defined as 2. The height of the string select transistor SST is defined as 9. The height of the memory cell MC6adjacent to the string select transistor SST is defined as 7.

As an order of the memory cell MC increases from the ground select transistor GST, the height of the memory cell MC increases. That is, first to third memory cells MC1to MC3are defined to have second to fourth heights, respectively. Fourth to sixths memory cells MC4to MC6are defined to have fifth to seventh heights, respectively.

The NAND strings NS of the same row share the ground select line GSL. The NAND strings NS arranged in different rows share the ground select line GSL. The first conductive materials211to213having the first height are connected to each other to thereby form the ground select line GSL.

The memory cells MC having the same height in the NAND strings NS of the same row share the word line WL. The word lines WL of the NAND strings NS which have the same height and correspond to different rows are commonly connected. That is, the memory cells MC with the same height share the word line WL.

The first conductive materials221to223having the second height are commonly connected to form the first word line WL1. The first conductive materials231to233having the third height are commonly connected to form the second word line WL2. The first conductive materials241to243having the fourth height are commonly connected to form the third word line WL3. The first conductive materials251to253having the fifth height are commonly connected to form the fourth word line WL4. The first conductive materials261to263having the sixth height are commonly connected to form the fifth word line WL5. The first conductive materials271to273having the seventh height are commonly connected to form the sixth word line WL6. The first conductive materials281to283having the eighth height are commonly connected to form the seventh word line WL7.

The NAND strings NS of the same row share the string select line SSL. The NAND strings NS of different rows are connected to different string select lines SSL1, SSL2and SSL3, respectively. The first to third string select lines SSL1to SSL3correspond to the first conductive materials291to293having the ninth height, respectively.

Hereinafter, first string select transistors SST1are defined as the string select transistors SST connected to the first string select line SSL1. Second string select transistors SST2are defined as the string select transistors SST connected to the second string select line SSL2. Third string select transistors SST3are defined as the string select transistors SST connected to the third string select line SSL3.

The common source line CSL is commonly connected to all the NAND strings NS. For example, the first to fourth doping regions311to314are connected to each other to thereby form the common source line CSL.

As illustrated inFIG. 6, the word lines WL having the same height are commonly connected. Therefore, when the word line WL with a specific height is selected, all of the NAND strings NS connected to the selected word line WL are selected.

The NAND strings of different rows are connected to different string select lines SSL. Accordingly, among the NAND strings NS connected to the same word line WL, the NAND strings NS of the unselected row may be electrically isolated from the corresponding bit line and the NAND strings NS of the selected row may be electrically connected to the corresponding bit line by selecting and unselecting the string select lines SSL1to SSL3.

That is, by selecting and unselecting the string select lines SSL1to SSL3, the row of the NAND stings NS may be selected. A column of the NAND strings NS of the selected row may be selected.

Exemplarily, one of the string select lines SSL1to SSL3is selected during program and read operations. That is, the program and read operations are performed in units of rows of the NAND strings NS11to NS13, NS21to NS23, and NS31to NS33.

Exemplarily, a select voltage is applied to the selected word line of the selected row during the program or read operations, and an unselect voltage is applied to the unselected word lines and the dummy word line DWL. For example, the select voltage is a program voltage Vpgm or selection read voltage Vrd. For instance, the unselect voltage is a pass voltage Vpass or nonselection read voltage Vread. That is, the program and read operations are performed in units of word lines of the selected row of the NAND strings NS11to NS13, NS21to NS23, and NS31to NS33.

Exemplarily, among the first conductive materials211to291,212to292, and213to293, the thickness of the insulation material112provided between the first conductive material acting as the select lines and the first conductive material acting as the word lines may be greater than the thickness of other insulation materials112.

InFIGS. 3 to 6, the first conductive materials211,212and213having the first height operates as the ground select line GSL, and the first conductive materials291,292and293having the ninth height operates as the string select lines SSL1, SSL2and SSL3.

Here, the insulation materials112provided between the first conductive materials211,212and213having the first height and the first conductive materials221,222and223having the second height may be greater in thickness than the insulation materials112provided between the first conductive materials221,222and223having the second height and the conductive materials281,282and283having the eighth height.

Likewise, the insulation materials112provided between the first conductive materials281,282and283having the eighth height and the first conductive materials291,292and293having the ninth height may be greater in thickness than the insulation materials112provided between the first conductive materials221,222and223having the second height and the conductive materials281,282and283having the eighth height.

FIG. 7is a table showing example embodiments of a voltage condition in an erasing operation of the nonvolatile memory device ofFIG. 1. Exemplarily, an erasing operation may be performed in memory block units. Exemplarily, the erasing operation will be described below with reference to the memory block BLKi that has been described above with reference toFIGS. 3 to 6.

In the erasing operation, the string selection lines SSL1to SSL3are floated. A word line erase voltage Vwe is applied to word lines WL1to WL7. For example, the word line erase voltage Vwe may be a ground voltage Vss. The ground selection line GSL is floated. Furthermore, an erase voltage Vers is applied to the substrate111. The substrate111and the surface layer114acting as a second-direction body may be formed of a silicon material having the same type. Accordingly, the erase voltage Vers applied to the substrate111is transferred to the second-direction body114. Exemplarily, the erase voltage Vers may be a high voltage.

The ground selection line GSL and the string selection lines SSL1to SSL3are in a floated state. Therefore, when the voltage of the second-direction body114is shifted, a coupling effect is given to the ground selection line GSL and the string selection lines SSL1to SSL3. That is, when the voltage of the second-direction body114increases to the erase voltage Vers, the voltage of the ground selection line GSL and the voltages of the string selection lines SSL1to SSL3also increase. Accordingly, the ground selection transistors GST and the string selection transistors SST are prevented from being erased.

The word line erase voltage Vwe is applied to the word lines WL1to WL7. Exemplarily, the word line erase voltage Vwe is a low voltage. For example, the word line erase voltage Vwe may be the ground voltage Vss. By a voltage difference between the second-direction body114and the word lines WL1to WL7, Fowler-Nordheim tunneling occurs in the memory cells MC1to MC7. Accordingly, the memory cells MC1to MC7are erased.

When the erase voltage Vers is applied to the substrate111, coupling may occur between the substrate111and the ground selection line GSL. For example, when the voltage of the substrate111increases, the voltage of the ground selection line GSL may also increase by a coupling effect. When the voltage of the ground selection line GSL increases, ground selection transistors GST may be turned on. That is, a region corresponding to the ground selection transistors GST in the second-direction body114may be inverted.

FIG. 8is a cross-sectional view illustrating the NAND string NS12of the NAND strings NS11to NS13, NS21to NS23and NS31to NS33of the memory block BLKi which has been described above with reference toFIGS. 3 to 6. Exemplarily, a case where the ground selection transistor GST is turned on in an erasing operation is illustrated inFIG. 8.

Referring toFIGS. 3 to 8, the substrate111is p-type silicon. A region corresponding to the string selection transistor SST and the memory cells MC1to MC7in the second-direction body114maintains a p-type. On the other hand, a region N1corresponding to the ground selection transistor GST in the second-direction body114is inverted into an n-type. That is, the region corresponding to the string selection transistor SST and the memory cells MC1to MC7in the second-direction body114is electrically insulated from the substrate111. Accordingly, the erase voltage Vers applied to the substrate111is not transferred to the memory cells MC1to MC7in the second-direction body114, so the memory cells MC1to MC7are not erased. For preventing this problem, the nonvolatile memory device according to example embodiments of inventive concepts drives a ground selection line according to the voltage level of the substrate of the memory cell array110.

FIG. 9is a flowchart illustrating an erasing method in the nonvolatile memory device100ofFIG. 1, according to example embodiments of inventive concepts. Exemplarily, it is assumed that the memory block BLKi which has been described above with reference toFIGS. 3 to 6is erased. That is, it is assumed that a block word line driver123in the address decoder120selects the memory block BLKi

Referring toFIGS. 1 to 6and9, the word line erase voltage Vwe is applied to the word lines WL1to WL7in operation S110. For example, the word line erase voltage Vwe is a low voltage. For example, the word line erase voltage Vwe is the ground voltage Vss. For example, the word line erase voltage Vwe has a lower level than the ground voltage Vss. For example, the address decoder120drives the word lines WL1to WL7with the word line erase voltage Vwe.

A specific voltage Vpd is applied to the ground selection line GSL in operation S120. For example, the specific voltage Vpd is a voltage for turning off the ground selection transistor GST. For example, the specific voltage Vpd has a lower level than the threshold voltage of the ground selection transistor GST. For example, the specific voltage Vpd is the ground voltage Vss. For example, the specific voltage Vpd has a lower level than the ground voltage Vss. For example, the address decoder120drives the ground selection line GSL with the specific voltage Vpd.

The erase voltage Vers is applied to the substrate111in operation S130. For example, the erase voltage Vers is a high voltage. For example, the substrate bias circuit160may supply the erase voltage Vers to the substrate111.

The ground selection line GSL is floated according to the change of a substrate voltage in operation S140. For example, the substrate monitor circuit130monitors the voltage change of the substrate111of the memory cell array110. Based on the voltage change of the substrate111, the substrate monitor circuit130activates or deactivates a ground enable signal GE. In response to the ground enable signal GE, the address decoder120applies the specific voltage Vpd to the ground selection line GSL or floats the ground selection line GSL.

Though inFIG. 9operations S110to S130are executed in order, but exemplarily operations S110to S130may be performed at the same time. Exemplarily, operations S110and S120may be sequentially performed. Exemplarily, operations S110to S130may be performed in reverse order. Exemplarily, a string selection line driver125in S140may control the string selection lines SSL1to SSL3to be floated while operations5110to S130are being performed.

FIG. 10is an example table showing an erase voltage condition based on the erasing method ofFIG. 9.

Referring toFIGS. 1 to 6,9and10, the string selection lines SSL1to SSL3are floated in an erasing operation. In the erasing operation, the word line erase voltage Vwe is applied to the word lines WL1to WL7. When the erasing operation is started, the specific voltage Vpd is applied to the ground selection line GSL. Subsequently, the ground selection line GSL is floated. In the erasing operation, the erase voltage Vers is applied to the substrate111.

FIG. 11is an example timing diagram showing voltage change based on the erasing method ofFIG. 9and the voltage condition ofFIG. 10.

Referring toFIGS. 1 to 6,9to11, once erasing operation begins, the erase voltage Vers is applied to the substrate111at a first time t1. That is, the voltage of the substrate111begins to increase at the first time t1.

At this point, the specific voltage Vpd is applied to the ground selection line GSL. For example, the ground selection line GSL maintains the ground voltage Vss. Accordingly, the ground selection transistor GST maintains a turn-off state. Therefore, the voltage of the substrate111can be transferred to the second-direction body114. That is, the voltage of the second-direction body114increases together with the voltage of the substrate111.

The word line erase voltage Vwe is applied to the word lines WL1to WL7.

The string selection lines SSL1to SSL3are in a floated state. The voltage change of the second-direction body114causes a coupling effect to the string selection lines SSL1to SSL3. That is, when the voltage of the second-direction body114increases together with the substrate111, the voltages of the string selection lines SSL1to SSL3also increase.

At a second time t2, the voltage level of the substrate111reaches a threshold or target voltage level Vtar. Once the voltage level of the substrate111reaches the threshold or target voltage level Vtar, the ground selection line GSL is floated. For example, the ground selection line driver129inFIG. 14AorFIG. 14Bfloats the ground selection line GSL. After the second time t2, the voltage of the substrate111is increased to the level of the erase voltage Vers. As the voltage of the substrate111increases, the voltages of the string selection lines SSL1to SSL3increase. For example, the voltages of the string selection lines SSL1to SSL3may be increased to the level of a string selection line voltage Vss1.

Since the ground selection line GSL is floated from the second time t2, the voltage of the ground selection line GSL increases by a coupling effect after the second time t2. For example, the voltage of the ground selection line GSL may be increased to the level of a ground selection line voltage Vgs1. The voltages of the word lines WL1to WL7maintain the level of the word line erase voltage Vwe during the erasing operation. For example, the word line erase voltage Vwe may be the ground voltage Vss.

The erase voltage Vers is applied to the second-direction body114, and the word line erase voltage Vwe is applied to the word lines WL1to WL7. By a voltage difference between the second-direction body114and the word lines WL1to WL7, Fowler-Nordheim tunneling occurs in the memory cells MC1to MC7. Accordingly, the memory cells MC1to MC7are erased.

The erase voltage Vers is applied to the second-direction body114, and the string selection line voltage Vss1is in the string selection lines SSL1to SSL3. A voltage difference between the second-direction body114and the string selection lines SSL1to SSL3is not large enough to induce Fowler-Nordheim tunneling

The erase voltage Vers is applied to the second-direction body114, and a ground selection line voltage Vgs1is applied to the ground selection line GSL. The voltage of the substrate111reaches the target voltage level Vtar, and then the voltage of the ground selection line GSL begins to increase by the coupling effect. That is, the level of the ground selection line voltage Vgs1is affected by the level of the target voltage Vtar. When the level of the target voltage Vtar is controlled, the level of the ground selection line voltage Vgs1can be controlled.

Exemplarily, the level of the target voltage Vtar may be determined not to cause Fowler-Nordheim tunneling by the voltage difference between the erase voltage Vers and the ground selection line voltage Vgs1. For example, the level of the target voltage Vtar may be controlled so that the level of the ground selection line voltage Vgs1becomes one-half of the level of the erase voltage Vers. Accordingly, the ground selection transistors GST are prevented from being erased.

According to the erasing method according to example embodiments of inventive concepts, as described above, the voltage of the ground selection line GSL is controlled according to the voltage level of the substrate111. At a time when the erasing operation is started, the ground selection line GSL is applied to a specific voltage. The specific voltage is a voltage for not inverting the region corresponding to the ground selection transistor GST in the second-direction body114. When the voltage level of the substrate111reaches the level of the target voltage Vtar, the ground selection line GSL is floated. That is, the erase disturbance of the memory cells MC1to MC7is prevented, and the ground selection transistors GST are prevented from being erased. Accordingly, the reliability of the nonvolatile memory device100may be improved.

FIG. 12is an example block diagram illustrating the substrate monitor circuit130ofFIG. 1.

A substrate voltage Vsub of the substrate of the memory array is supplied to the up-trimmer131. The down-trimmer133is connected to a ground voltage. An intermediate node C between the up-trimmer131and the down-trimmer133is connected to the comparator135. The up-trimmer131and the down-trimmer133divide the substrate voltage Vsub. For example, the up-trimmer131and the down-trimmer133may have resistance values. That is, the substrate voltage Vsub that is divided by the up-trimmer131and the down-trimmer133is supplied to the comparator135.

Exemplarily, the up-trimmer131and the down-trimmer133may have variable resistance values. For example, the up-trimmer131may control a resistance value in response to a first code signal CODE1. The down-trimmer133may control a resistance value in response to a second code signal CODE2.

The comparator135compares the voltage of the intermediate node C and a reference voltage Vref. The comparator135activates or deactivates the ground enable signal GE according to the result of the comparison. The ground enable signal GE is transferred to the address decoder120. The address decoder120drives the ground selection line GSL of a selected memory block (for example, BLKi) in response to the ground enable signal GE. For example, as described above with reference toFIGS. 9 to 11, the address decoder120may drive the ground selection line GSL. That is, the level of the target voltage Vtar may be set according to a division ratio of the up-trimmer131and down-trimmer133and the level of the reference voltage Vref.

Moreover, the division ratio of the up-trimmer131and down-trimmer133is controlled by the code signals CODE1and CODE2. Therefore, the level of the target voltage Vtar may be varied based on the code signals CODE1and CODE2. These codes CODE1and CODE2may be set during a power-up sequence of the nonvolatile memory device using e-fuse data that are stored in the memory array.

InFIG. 12, it has been described above that the output of the comparator135is provided as the ground enable signal GE. However, a logic block which controls the output of the comparator135to output it as the ground enable signal GE may be additionally provided.

FIG. 13is an example circuit diagram illustrating the up-trimmer131ofFIG. 12.

Referring toFIG. 13, the up-trimmer131includes first to nth resistors R1to Rn, and first to nth switches T1to Tn. Exemplarily, the first to nth switches T1to Tn are illustrated as transistors, but they are not limited thereto.

The first to nth resistors R1to Rn are connected in series. The first to nth resistors R1to Rn and the first to nth transistors T1to Tn are connected in parallel, respectively. The first to nth transistors T1to Tn operate in response to the first code signal CODE1. Exemplarily, when the first transistor T1is turned on, a path detouring the first resistor R1is provided by the first transistor T1. Accordingly, the resistance value of the up-trimmer131decreases. When the first transistor T1is turned off, the path detouring the first resistor R1is not provided. Accordingly, the resistance value of the first resistor R1is reflected in that of the up-trimmer131. Except for that the second code signal CODE2is provided, the down-trimmer133ofFIG. 12may be configured like the up-trimmer131. Thus, the detailed description of the down-trimmer133will be omitted.

As described above, by performing control based on the first code signal CODE1, the resistance value of the up-trimmer131may be controlled. Also, by controlling the second code signal CODE2, the resistance value of the down-trimmer133may be controlled. Accordingly, by controlling the first and second code signals CODE1and CODE2, the level of the target voltage Vtar may be varied.

FIG. 14Ais an example block diagram illustrating the memory cell array110and address decoder120of the nonvolatile memory device ofFIG. 1. Exemplarily, the memory block BLKi of the memory cell array110is illustrated.

Referring toFIG. 14A, the address decoder120includes a pass circuit121, a block word line driver123, a string selection line driver125, a word line driver127, and a ground selection line driver129.

The voltage transferring pass circuit121transfers voltages on selection lines from the SSL driver, the WL driver, and the GSL driver in response to a BLKWL signal. The pass circuit121includes a plurality of switches. Exemplarily, the pass circuit121may include a plurality of transistors. Exemplarily, the pass circuit121may include a plurality of high voltage transistors.

The gates of the transistors of the pass circuit121are connected to a block word line BLKWL in common. Some of the transistors of the pass circuit121are connected between the string selection lines SSL1to SSL3and selection lines SS1to SS3, respectively. Some of the transistors of the pass circuit121are connected between the word lines WL1to WL7and the selection lines S1to S3, respectively. A portion of the transistors of the pass circuit121is connected between the ground selection line GSL and a selection line GS. That is, the pass circuit121connects the string selection lines SSL1to SSL3, the word lines WL1to WL7and the ground selection line GSL to the string selection line driver125, the word line driver127and the ground selection line driver129in response to the voltage level of the block word line BLKWL, respectively.

The block word line driver123drives the block word line BLKWL so that one of memory blocks BLK1to BLKi of the memory cell array110is selected. BLKWL. For example, when the memory block BLKi is selected, the block word line driver123applies a selection voltage to the block word line BLKWL. Exemplarily, the block word line driver123applies a high voltage Vpp to the block word line BLKWL in a programming operation and a reading operation. Exemplarily, the block word line driver123applies a power source voltage Vcc to the block word line BLKWL in an erasing operation.

The string selection line driver125is connected to the selection lines SS1to SS3. The selection lines SS1to SS3are connected to the string selection lines SSL1to SSL3through the pass circuit121. That is, the string selection line driver125drives the string selection lines SSL1to SSL3through the pass circuit121. For example, the string selection line driver125floats the string selection lines SSL1to SSL3in the erasing operation.

The word line driver127is connected to selection lines S1to S7. The selection lines S1to S7are connected to the word lines WL1to WL7through the pass circuit121, respectively. That is, the word line driver127drives the word lines WL1to WL7through the pass circuit121. Exemplarily, the word line driver127applies the word line erase voltage Vwe to the word lines WL1to WL7in the erasing operation.

The ground selection line driver129is connected to the selection line GS. The selection line GS is connected to the ground selection line GSL through the pass circuit121. That is, the ground selection line driver129drives the ground selection line GSL through the pass circuit121.

In the erasing operation, the ground selection line driver129operates in response to the ground enable signal GE. Exemplarily, when the erasing operation is started, the ground selection line driver129applies a specific voltage Vpd to the ground selection line GSL. The specific voltage Vpd is a voltage for not inverting the region corresponding to the ground selection transistor GST in the second-direction body114. When the logical value of the ground enable signal GE is changed, the ground selection line driver129floats the ground selection line GSL.

For example, when the ground enable signal GE is changed, the ground selection line driver129controls an output in order to float the ground selection line GSL. For example, the ground selection line driver129outputs a voltage having the same level as the voltage level of the block word line BLKWL. For example, when the power source voltage Vcc is applied to the block word line BLKWL in the erasing operation, the ground selection line driver129outputs the power source voltage Vcc according to the change of the ground enable signal GE. At this point, the gate voltage and drain (or source) voltage of the pass circuit121corresponding to the ground selection line GSL become the same. Thus, the transistor of the pass circuit121corresponding to the ground selection line GSL is turned off. That is, the ground selection line GSL is floated.

When the ground enable signal GE is changed, the ground selection line driver129is not limited to that it outputs a voltage having the same level as the voltage level of the block word line BLKWL. Also, when the ground enable signal GE is changed, the ground selection line driver129is not limited to that it outputs the power source voltage Vcc. Exemplarily, when the ground enable signal GE is changed, the ground selection line driver129outputs a voltage for turning off the transistor of the pass circuit121which corresponds to the ground selection line GSL. Exemplarily, when the ground enable signal GE is changed, the ground selection line driver129floats an output node.

As described above, the nonvolatile memory device100according to example embodiments of inventive concepts includes a transfer pass circuit121, a block word line driver123, a string selection line driver125, a word line driver127, and a ground selection line driver129for each memory block BLKi of the memory cell array110. As described above, the nonvolatile memory device100according to an embodiment of the inventive concept drives the ground selection line GSL with the change of the substrate voltage of the memory cell array110in the erasing operation. Accordingly, the erase disturbance of the memory cells MC1to MC7is prevented, and the ground selection transistor GST is prevented from being erased. That is, the reliability of the nonvolatile memory device100is improved.

FIG. 14Bis another example block diagram illustrating the memory cell array110and address decoder120′ of the nonvolatile memory device ofFIG. 1. Exemplarily, memory blocks BLK0and BLK1of the memory cell array110are illustrated.

Referring toFIG. 14B, in contrast to the address decoder120ofFIG. 14A, the address decoder120′ includes a transfer pass circuit1210,1211and a block word line driver1230,1231for each memory block BLK0and BLK1, and one common string selection line driver125, word line driver127, and ground selection line driver129for all the memory blocks BLKn.

The voltage transferring transfer pass circuits121ntransfer voltages on selection lines from the SSL driver125, the WL driver127, and the GSL driver129in response to a BLKWL signal from the corresponding block word line driver123n. The transfer pass circuits121ninclude a plurality of switches. Exemplarily, the transfer pass circuit121nmay include a plurality of transistors. Exemplarily, the transfer pass circuits121nmay include a plurality of high voltage transistors.

The gates of the transistors of each transfer pass circuit121nare connected to a block word line BLKWL in common. Some of the transistors of each transfer pass circuit121nare connected between the string selection lines SSL1to SSL3and selection lines SS1to SS3, respectively. Some of the transistors of each transfer pass circuit121nare connected between the word lines WL1to WL7and the selection lines S1to S3, respectively. A portion of the transistors of each transfer pass circuit121are connected between the ground selection line GSL and a selection line GS. That is, each transfer pass circuit121nconnects the string selection lines SSL1to SSL3, the word lines WL1to WL7and the ground selection line GSL to the string selection line driver125, the word line driver127and the ground selection line driver129in response to the voltage level of the block word line BLKWL, respectively.

Each block word line driver123ndrives the block word line BLKWL so that one of memory blocks BLK1to BLKi of the memory cell array110is selected. For example, when the memory block BLK0is selected, the block word line driver1230applies a selection voltage to the block word line BLKWL. Exemplarily, the block word line driver1230applies a high voltage Vpp to the block word line BLKWL in a programming operation and a reading operation. Exemplarily, the block word line driver1230applies a power source voltage Vcc to the block word line BLKWL in an erasing operation.

The string selection line driver125is connected to the selection lines SS1to SS3of each memory block BLKn. The selection lines SS1to SS3are connected to the string selection lines SSL1to SSL3through the corresponding transfer pass circuit121n. That is, the string selection line driver125drives the string selection lines SSL1to SSL3of each memory block BLKn through the corresponding transfer pass circuit121n. For example, the string selection line driver125floats the string selection lines SSL1to SSL3in the erasing operation.

The word line driver127is connected to selection lines S1to S7of each memory block BLKn. The selection lines S1to S7are connected to the word lines WL1to WL7through the corresponding transfer pass circuit121n, respectively. That is, the word line driver127drives the word lines WL1to WL7through the corresponding transfer pass circuit121n. Exemplarily, the word line driver127applies the word line erase voltage Vwe to the word lines WL1to WL7in the erasing operation.

The ground selection line driver129is connected to the selection line GS of each memory block BLKn. The selection line GS is connected to the ground selection line GSL through the corresponding transfer pass circuit121n. That is, the ground selection line driver129drives the ground selection lines GSL through the corresponding transfer pass circuit121n.

In the erasing operation, the ground selection line driver129operates in response to the ground enable signal GE. Exemplarily, when the erasing operation is started, the ground selection line driver129applies a specific voltage Vpd to the ground selection line GSL. The specific voltage Vpd is a voltage for not inverting the region corresponding to the ground selection transistor GST in the second-direction body114. When the logical value of the ground enable signal GE is changed, the ground selection line driver129floats the ground selection line GSL.

For example, when the ground enable signal GE is changed, the ground selection line driver129controls an output in order to float the ground selection line GSL. For example, the ground selection line driver129outputs a voltage having the same level as the voltage level of the block word line BLKWL. For example, when the power source voltage Vcc is applied to the block word line BLKWL in the erasing operation, the ground selection line driver129outputs the power source voltage Vcc according to the change of the ground enable signal GE. At this point, the gate voltage and drain (or source) voltage of the transfer pass circuit121corresponding to the ground selection line GSL become the same. Thus, the transistor of the transfer pass circuit121corresponding to the ground selection line GSL is turned off. That is, the ground selection line GSL is floated.

When the ground enable signal GE is changed, the ground selection line driver129is not limited to that it outputs a voltage having the same level as the voltage level of the block word line BLKWL. Also, when the ground enable signal GE is changed, the ground selection line driver129is not limited to that it outputs the power source voltage Vcc. Exemplarily, when the ground enable signal GE is changed, the ground selection line driver129outputs a voltage for turning off the transistor of the transfer pass circuit121nwhich corresponds to the ground selection line GSL. Exemplarily, when the ground enable signal GE is changed, the ground selection line driver129floats an output node.

As described above, the address decoder120′ includes a transfer pass circuit1210,1211and a block word line driver1230,1231for each memory block BLK0and BLK1, and one common string selection line driver125, word line driver127, and ground selection line driver129for all the memory blocks BLKn. As described above, the nonvolatile memory device100according to an embodiment of the inventive concept drives the ground selection line GSL with the change of the substrate voltage of the memory cell array110in the erasing operation. Accordingly, the erase disturbance of the memory cells MC1to MC7is prevented, and the ground selection transistor GST is prevented from being erased. That is, the reliability of the nonvolatile memory device100is improved.

FIG. 15is a circuit diagram illustrating an equivalent circuit BLKi_1of the memory block BLKi described with reference toFIGS. 3 and 5according to example embodiments of inventive concepts. Compared to the equivalent circuit described with reference toFIG. 6, a lateral transistor LTR is additionally provided at each NAND string NS of the memory block BLKi_1.

In each NAND string NS, the lateral transistor LTR is connected between a ground selection transistor GST and a common source line CSL. A gate (or a control gate) of the lateral transistor LTR and a gate (or control gate) of the ground selection transistor GST are connected to the ground selection line GSL.

As described with reference toFIGS. 3 through 6, the first conductive materials211,212, and213having the first height correspond to first to third ground selection lines GSL1to GSL3, respectively.

Once a specific voltage is applied to the first conductive materials211,212, and213having the first height, a channel is formed in a region of the surface layer114adjacent to the first conductive materials211,212, and213. Moreover, if a specific voltage is applied to the first conductive materials211,212, and213, a channel is formed in a region of the substrate111adjacent to the first conductive materials211,212, and213.

A first doping region311is connected to a channel in the substrate111, which is formed by a voltage of the first conductive material. The channel of the substrate111generated by a voltage of the first conductive material211is connected to a channel formed by voltage of the first conductive material211in the surface layer114operating as a body of the second direction.

Likewise, a channel is formed in the substrate111by a voltage of the first conductive materials211,212, and213. First to fourth doping regions311to314are respectively connected to the surface layers114operating as a body of the second direction through a channel formed by a voltage of the first conductive materials211,212, and213in the substrate111.

As described with reference toFIGS. 3 through 6, the first to fourth doping regions311to314are commonly connected to form a common source line CSL. The common source line CSL and the channels of the memory cells MC1to MC7are electrically connected through channels perpendicular and parallel to the substrate111, which are formed by a voltage of the ground selection line GSL.

That is, it is understood that transistors perpendicular and parallel to a substrate, driven by the ground selection line GSL, are provided between the common source line CSL and the first memory cells MC1. A transistor perpendicular to a substrate may be understood as a ground selection transistor GST and a transistor parallel to a substrate may be understood as a lateral transistor LST.

FIG. 16is a circuit diagram illustrating an equivalent circuit BLKi_1of the memory block BLKi described with reference toFIGS. 3 and 5according to example embodiments of inventive concepts. Compared to the equivalent circuit described with reference toFIG. 6, two ground selection transistors GST1and GST2may be provided between the memory cells MC1to MC6and the common source line CSL in each NAND string NS. The ground selection lines GSL1and GSL2corresponding to the ground selection transistor GST1or GST2having the same height may be commonly connected. Moreover, the ground selection lines GSL1and GSL2corresponding to the same NAND string NS may be commonly connected.

FIG. 17is a circuit diagram illustrating an equivalent circuit BLKi_2of the memory block BLKi described with reference toFIGS. 3 and 5according to example embodiments of inventive concepts. Compared to the memory block BLKi_1ofFIG. 16, two string selection transistors SSTa and SSTb may be provided between the memory cells MC1to MC5and the bit line BL.

In NAND strings in the same row, the string selection transistor SSTa or SSTb having the same height may share one string selection line SSL. For example, in the NAND strings NS11to NS13of a first row, the a string selection transistors SSTa share a1astring selection line SSL1a. The b string selection transistors SSTb share a1bstring selection line SSL1b.

In NAND strings NS21to NS23in the second row, the a string selection transistors SSTa share a2astring selection line SSL2a. The b string selection transistors SSTb share a2bstring selection line SSL2b.

In NAND strings NS21to NS23in the third row, the a string selection transistors SSTa share a3astring selection line SSL3a. The b string selection transistors SSTb share a3bstring selection line SSL3b.

FIG. 18is a circuit diagram illustrating an equivalent circuit BLKi_3of the memory block BLKi described with reference toFIGS. 3 and 5according to example embodiments of inventive concepts. Compared to the memory block BLKi_2ofFIG. 17, string selection lines SSL corresponding to the NAND strings NS of the same row are commonly connected.

FIG. 19is a circuit diagram illustrating an equivalent circuit BLKi_4of the memory block BLKi described with reference toFIGS. 3 and 5according to example embodiments of inventive concepts. Compared to the memory block BLKi ofFIG. 6, the dummy memory cell DMC is provided between the string selection transistor SST and the memory cells MC6in each NAND string NS. The dummy memory cells DMC1are commonly connected to the dummy word lines DWL. That is, the dummy word line DWL is provided between the string selection lines SSL1to SSL3and the word line WL6.

FIG. 20is a circuit diagram illustrating an equivalent circuit BLKi_5of the memory block BLKi described with reference toFIGS. 3 and 5according to example embodiments of inventive concepts. Compared to the memory block BLKi ofFIG. 6, the dummy memory cell DMC is provided between the ground selection transistor GST and the memory cell MC1in each NAND string NS. The dummy memory cells DMC are commonly connected to the dummy word lines DWL. That is, the dummy word line DWL is provided between the ground selection line GSL and the word lines WL1.

FIG. 21is a circuit diagram illustrating an equivalent circuit BLKi_6of the memory block BLKi described with reference toFIGS. 3 and 5according to example embodiments of inventive concepts. Compared to the memory block BLKi ofFIG. 6, a dummy memory cell DMC is provided between the ground selection transistor GST and the memory cell MC1and between the string select transistor SST and the memory cell MC6in each NAND string NS. The dummy memory cells DMC are commonly connected to the dummy word lines DWL1and DWL2. That is, the dummy word line DWL1is provided between the ground selection line GSL and the word line WL1and the DWL2is provided between the string select line SSL and the word line MC5.FIG. 22is a perspective view of one of the memory blocks BLK1-BLIKz according to example embodiments BLKi′ of inventive concepts. A cross-sectional view taken along the line I-I′ of the memory block BLKi′ is the same as that ofFIG. 3.

Compared to the memory block BLKi ofFIG. 3, in the memory block BLKi, pillars113′ has a square pillar form. Moreover, between the pillars113′ spaced from each other along the first direction by a specific distance, insulation materials101are provided. Exemplarily, the insulation materials101extend along the second direction and contact the substrate111.

The first conductive materials211to291,212to292, and213to293described with reference toFIG. 3are divided into first portions211ato291a,212ato292a, and213ato293aand second portions211bto291b,212bto292b, and213bto293bin a region including the insulation materials101.

In a region on first and second doping regions311and312, each pillar113′ forms the first portions211ato291aand insulation layer116of the first conductive materials and one NAND string NS and forms the second portions211bto291band insulation layer116of the first conductive materials and another NAND string NS.

In a region on second and third doping regions312and313, each pillar113′ forms the first portions212ato292aand insulation layer116of the first conductive materials and one NAND string NS and forms the second portions212bto292band insulation layer116of the first conductive materials and another NAND string NS.

In a region on third and fourth doping regions313and314, each pillar113′ forms the first portions213ato293aand insulation layer116of the first conductive materials and one NAND string NS and forms the second portions213bto293band insulation layer116of the first conductive materials and another NAND string NS.

That is, the first and second portions211ato291aand211bto291bof the first conductive materials provided at the both sides of each pillar113′ are separated using the insulation material101, such that each pillar113′ may form two NAND strings.

As described with reference toFIGS. 3 through 6, the first portions211ato291aand the second portions211bto291b,212bto292b, and213bto293bof the first conductive materials may correspond to ground selection lines GSL, word lines WL, and string selection lines SST, respectively. The word lines WL having the same height are commonly connected.

Exemplarily, an equivalent circuit of the memory block BLKi′ may be illustrated as the equivalent circuit BLKi_1shown inFIG. 6except the number of rows in the NAND strings NS. For example, the number of rows in the NAND strings NS of an equivalent circuit of the memory block BLKi′ may be two times that in the NAND strings NS of the equivalent circuit BLKi_1shown inFIG. 6.

Exemplarily, an equivalent circuit of the memory block BLKi′ may be illustrated as the equivalent circuits BLKi_2to BLKi_8shown inFIGS. 15 through 21except the number of rows in the NAND strings NS. For example, the number of rows in the NAND strings NS of an equivalent circuit of the memory block BLKi′ may be two times that in the NAND strings NS of the equivalent circuits BLKi_2to BLKi_8shown inFIGS. 15 through 21.

Each NAND string of the memory block BLKi′ may include a lateral transistor LTR. At least one dummy memory cell DMC may be provided between sub blocks of the memory block BLKi′. The number of memory cells DMC, which may be further provided between sub blocks of the memory block BLKi′, may vary.

In each NAND string, at least two string selection transistors SST may be provided. In each NAND sting, at least two ground selection transistors GST may be provided. In each NAND string, at least one dummy memory cell DMC may be provided between the memory cells MC and the string selection transistor SST. In each NAND string, at least one dummy memory cell DMC may be provided between the memory cells MC and the ground selection transistor GST.

FIG. 22is a block diagram illustrating a memory block BLKi ofFIG. 2according to example embodiments of inventive concepts.

Comparing with the memory block BLKi ofFIG. 3, in a memory block BLKi′, pillars113′ may be provided in a tetragonal pillar shape. Also, insulating materials101are provided between the pillars113′ that are disposed in the first direction. Exemplarily, the insulating materials101are expanded in the second direction and connected to the substrate111. Also, the insulating materials101are expanded in the first direction in a region other than a region to which the pillars113′ are provided. That is, the conductive materials211to291,212to292and213to293that are extended in the first direction and have been described above with reference toFIG. 3may be divided into two portions211ato291a,211bto291b,212ato292a,212bto292b,213ato293aand213bto293b, respectively. The divided portions211ato291a,211bto291b,212ato292a,212bto292b,213ato293aand213bto293bof the conductive materials may be electrically insulated.

In a region on the first and second doping regions311and312, each of the pillars113′, the portions211ato291aof the conductive materials extended in the first direction and the insulation layer116may form one NAND string NS, and each of the pillars113′, the portions211bto291bof the conductive materials extended in the first direction and the insulation layer116may form another NAND string NS.

In a region on the second and third doping regions312and313, each of the pillars113′, the portions212ato292aof the conductive materials extended in the first direction and the insulation layer116may form one NAND string NS, and each of the pillars113′, the portions212bto292bof the conductive materials extended in the first direction and the insulation layer116may form another NAND string NS.

In a region on the third and fourth doping regions313and314, each of the pillars113′, the portions213ato293aof the conductive materials extended in the first direction and the insulation layer116may form one NAND string NS, and each of the pillars113′, the portions213bto293bof the conductive materials extended in the first direction and the insulation layer116may form in another NAND string NS.

That is, by electrically insulating the conductive materials211ato291aand211bto291bwhich are provided to the both-side surfaces of the each pillar113′ and are extended in the first direction with the insulation layer101, the each pillar113′ may form two NAND strings NS.

A cross-sectional view taken along line I-I′ of the memory block BLKi′, which has been described above with reference toFIG. 22, is as illustrated inFIG. 4. Accordingly, a cross-sectional view of the memory block BLKi′ and its description will be omitted.

FIG. 23is a block diagram illustrating a memory system1000which includes the nonvolatile memory device100ofFIG. 1, according to example embodiments of inventive concepts.

Referring toFIG. 23, a memory system1000according to example embodiments of inventive concepts includes a nonvolatile memory device1100and a controller1200.

The nonvolatile memory device1100operates, as described above with reference toFIGS. 1 to 22. For example, the nonvolatile memory device1100applies a specific voltage to a ground selection line GSL in an erasing operation. With the voltage change of the substrate111of the nonvolatile memory device1100, the nonvolatile memory device1100floats the ground selection line GSL. Accordingly, erase disturbance is prevented, and reliabilities for the nonvolatile memory device1100and the memory system1000including the nonvolatile memory device1100are improved.

The controller1200is connected to a host and the nonvolatile memory device1100. In response to a request from the host, the controller1200accesses the nonvolatile memory device1100. For example, the controller1200controls the reading, writing, erasing and background operations of the nonvolatile memory device1100. The controller1200provides interface between the nonvolatile memory device1100and the host. The controller1200drives firmware for controlling the nonvolatile memory device1100.

Exemplarily, the controller1200may further include a RAM, a processing unit, a host interface, and a memory interface. The RAM is used as at least one of a working memory of the processing unit, a cache memory between the nonvolatile memory device1100and the host, and a buffer memory between the nonvolatile memory device1100and the host. The processing unit controls the overall operation of the controller1200.

The host interface includes a protocol for data exchange between the host and the controller1200. Exemplarily, the host interface communicates with external devices (for example, a host) through at least one of various interface protocols such as a Universal Serial Bus (USB) protocol, a Multimedia Card (MMC) protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial-ATA (SATA) protocol, a Parallel-ATA (PATA) protocol, a Small Component Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol and an Integrated Drive Electronics (IDE) protocol.

The memory system1000may further include an error correction block. The error correction block detects and corrects the error of data that is read from the nonvolatile memory device1100with an Error Correction Code (ECC). Exemplarily, the error correction block is provided as the element of the controller1200. The error correction block may be provided as the element of the nonvolatile memory device1100.

The controller1200and the nonvolatile memory device1100may be integrated as one semiconductor device. Exemplarily, the controller1200and the nonvolatile memory device1100are integrated as one semiconductor device to configure a memory card. For example, the controller1200and the nonvolatile memory device1100are integrated as one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMICA)), a compact flash card (CF), a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC) and a universal flash memory device (UFS).

The controller1200and the nonvolatile memory device1100are integrated as one semiconductor device to configure a semiconductor drive (Solid State Drive (SSD). The semiconductor drive (SSD) includes a storage unit for storing data in a semiconductor memory. When the memory system1000is used as the semiconductor drive (SSD), the operation speed of the host connected to the memory system1000is considerably improved.

As another example, the memory system1000is provided as one of various elements of electronic devices such as computers, Ultra Mobile PCs (UMPCs), workstations, net-books, Personal Digital Assistants (PDAs), portable computers, web tablets, wireless phones, mobile phones, smart phones, e-books, Portable Multimedia Players (PMPs), portable game machines, navigation devices, black boxes, digital cameras, Digital Multimedia Broadcasting (DMB) players, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, devices for transmitting/receiving information at a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, RFID devices and one of various elements configuring a computing system.

Exemplarily, the nonvolatile memory device1100or the memory system1000may be mounted as various types of packages. For example, the nonvolatile memory device1100or the memory system1000may be packaged in a package type such as Package on Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die In Waffle Pack (DIWP), Die In Wafer Form (DIWF), Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Package (SOP), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flat Pack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer Level Stack Package (WLSP), Die In Wafer Form (DIWF), Die On Waffle Package (DOWP), Wafer-level Fabricated Package (WFP) and Wafer-Level Processed Stack Package (WSP), thereby being mounted.

FIG. 24is a block diagram illustrating an application example of the memory system1000ofFIG. 23.

Referring toFIG. 24, a memory system2000includes a nonvolatile memory device2100and/or a controller2200. The nonvolatile memory device2100includes a plurality of nonvolatile memory chips. The plurality of nonvolatile memory chips are divided by groups. Each group of the nonvolatile memory chips is configured to communicate with the controller2200through one common channel. InFIG. 24, it is illustrated that the plurality of nonvolatile memory chips communicate with the controller2200through first to kth channels CH1to CHk. Each nonvolatile memory chip has same configuration as the nonvolatile memory device100described with reference toFIGS. 1 through 56.

Exemplarily, the controller2200is configured to control the nonvolatile memory device2100. For example, the controller2200is configured o control a refresh operation of the nonvolatile memory device2100. As described with reference toFIGS. 18 through 20, the controller2200controls a refresh operation of the nonvolatile memory device2100.

The controller2200communicates with a plurality of nonvolatile memory chips through a plurality of channels. Accordingly, when a refresh operation is performed in one nonvolatile memory chip connected to a specific channel, nonvolatile memory chips connected to another channel continue in a standby state. That is, while a refresh operation is performed in one nonvolatile memory chip connected to one channel, operations such as writing, reading, and erasing may be performed in the nonvolatile memory chip connected to another channel.

FIG. 25is a block diagram illustrating a computing system3000with the memory system2000described with reference toFIG. 24. Referring toFIG. 25, the computing system3000includes a central processing unit (CPU)3100, a random access memory (RAM)3200, a user interface3300, a power3400, a system bus3500and/or the memory system2000.

The memory system2000is electrically connected to the CPU3100, the RAM3200, and the power3400through the system bus3500. Data provided through a user interface3300or processed by the CPU3100are stored in the memory system2000. The memory system2000includes a controller2200and a nonvolatile memory device2100.

InFIG. 25, it is illustrated that the nonvolatile memory device2100is connected to the system bus3500through the controller2200. However, the nonvolatile memory device2100may be directly connected to the system bus3500. At this point, the CPU3100controls a refresh operation of the nonvolatile memory device2100.

InFIG. 25, it is described that the memory system200described withFIG. 24is provided. However, the memory system2000may be replaced with the memory system1000described withFIG. 23.

Exemplarily, the computing system3000may be configured to include all the memory systems1000and2000described with reference toFIGS. 1 and 24.

According to example embodiments of inventive concepts, erase disturbance by the activation of the ground selection transistor is prevented. Accordingly, the nonvolatile memory device, the erasing method thereof, and the memory system including the same may have improved reliability.