Antenna device

An antenna device is provided. The antenna device includes a first substrate, a first conductive layer, a first insulating structure, a second substrate, a second conductive layer and a liquid-crystal layer. The first conductive layer is disposed on the first substrate. The first insulating structure is disposed on the first conductive layer, and the first insulating structure includes a first region and a second region. The second substrate is disposed opposite to the first substrate. The second conductive layer is disposed on the second substrate. The liquid-crystal layer is disposed between the first conductive layer and the second conductive layer. The thickness of the first region is less than the thickness of the second region, and at least a portion of the first region is disposed in an overlapping region of the first conductive layer and the second conductive layer.

BACKGROUND

Technical Field

The present disclosure relates to an electronic device, and in particular it relates to an antenna having an insulating structure with varied thickness.

Description of the Related Art

Electronic products that come with a display panel, such as smartphones, tablets, notebooks, monitors, and TVs, have become indispensable necessities in modern society. With the flourishing development of such portable electronic products, consumers have high expectations regarding the quality, functionality, or price of such products. Such electronic products can generally be used as electronic modulation devices as well, for example, as antenna devices that can modulate electromagnetic waves.

Although currently existing antenna devices have been adequate for their intended purposes, they have not been satisfactory in all respects. The development of an antenna device that can effectively maintain capacitance modulation stability or operational reliability is still one of the goals that the industry currently aims for.

SUMMARY

In accordance with some embodiments of the present disclosure, an antenna device is provided. The antenna device includes a first substrate, a first conductive layer, a first insulating structure, a second substrate, a second conductive layer and a liquid-crystal layer. The first conductive layer is disposed on the first substrate. The first insulating structure is disposed on the first conductive layer, and the first insulating structure includes a first region and a second region. The second substrate is disposed opposite to the first substrate. The second conductive layer is disposed on the second substrate. The liquid-crystal layer is disposed between the first conductive layer and the second conductive layer. The thickness of the first region is less than the thickness of the second region, and at least a portion of the first region is disposed in an overlapping region of the first conductive layer and the second conductive layer.

DETAILED DESCRIPTION

The structure of the electronic device of the present disclosure and the manufacturing method thereof are described in detail in the following description. In the following detailed description, for purposes of explanation, numerous specific details and embodiments are set forth in order to provide a thorough understanding of the present disclosure. The specific elements and configurations described in the following detailed description are set forth in order to clearly describe the present disclosure. It will be apparent, however, that the exemplary embodiments set forth herein are used merely for the purpose of illustration, and the inventive concept may be embodied in various forms without being limited to those exemplary embodiments. In addition, the drawings of different embodiments may use like and/or corresponding numerals to denote like and/or corresponding elements in order to clearly describe the present disclosure. However, the use of like and/or corresponding numerals in the drawings of different embodiments does not suggest any correlation between different embodiments.

It should be noted that the elements or devices in the drawings of the present disclosure may be present in any form or configuration known to those with ordinary skill in the art. In addition, in the embodiments, relative expressions are used. For example, “lower”, “bottom”, “higher” or “top” are used to describe the position of one element relative to another. It should be appreciated that if a device is flipped upside down, an element that is “lower” will become an element that is “higher”. It should be understood that the descriptions of the exemplary embodiments are intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. The drawings are not drawn to scale. In addition, structures and devices are shown schematically in order to simplify the drawing.

The terms “about” and “substantially” typically mean+/−20% of the stated value, more typically +/−10% of the stated value, more typically +/−5% of the stated value, more typically +/−3% of the stated value, more typically +/−2% of the stated value, more typically +/−1% of the stated value and even more typically +/−0.5% of the stated value. The stated value of the present disclosure is an approximate value. When there is no specific description, the stated value includes the meaning of “about” or “substantially”. Furthermore, the phrase “in a range between a first value and a second value” or “in a range from a first value to a second value” indicates that the range includes the first value, the second value, and other values between them.

In addition, in some embodiments of the present disclosure, terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.

In accordance with some embodiments of the present disclosure, an electronic device (e.g., an antenna device) having an insulating structure with varied thickness is provided. Specifically, in accordance with some embodiments, the insulating structure may have a smaller thickness in a portion corresponding to the capacitance adjustable region, thereby maintaining stability of capacitance modulation or increasing operational reliability of the device. In accordance with some embodiments, the insulating structure may have a greater thickness in a portion other than the capacitance adjustable region, which may reduce the risk of corrosion of the conductive layer or diffusion of metal ions.

Refer toFIG. 1, which illustrates a top-view diagram of an electronic device10in accordance with some embodiments of the present disclosure. It should be understood that only some of the components of the electronic device10are shown inFIG. 1and other components are omitted for clarity of illustration. The structure of other components will be described in detail in the following figures. In accordance with some embodiments of the present disclosure, additional features may be added to the electronic device10described below.

As shown inFIG. 1, the electronic device10may include a first substrate102aand a plurality of electronic units100disposed on the first substrate102a. In accordance with some embodiments, the electronic device10may include an antenna device, a display device (e.g., a liquid-crystal display (LCD)), a light-emitting device, a detecting device, or another device for modulating electromagnetic waves, but it is not limited thereto. In some embodiments, the electronic device10mat be an antenna device, and the electronic unit100may be an antenna unit for modulating electromagnetic waves (e.g., microwaves). It should be understood that the arrangement of the electronic units100is not limited to the aspect shown inFIG. 1. In accordance with some other embodiments, the electronic units100may be arranged in another suitable manner.

In some embodiments, the material of the first substrate102amay include, but is not limited to, glass, quartz, sapphire, ceramic, polyimide (PI), liquid-crystal polymer (LCP) materials, polycarbonate (PC), photo sensitive polyimide (PSPI), polyethylene terephthalate (PET), other suitable substrate materials, or a combination thereof. In some embodiments, the first substrate102amay include a flexible substrate, a rigid substrate, or a combination thereof.

Next, refer toFIG. 2A, which illustrates a cross-sectional structural diagram of a portion of the electronic device10in accordance with some embodiments of the present disclosure. Specifically,FIG. 2Aillustrates an enlarged cross-sectional diagram of a region E of the electronic unit100shown inFIG. 1in accordance with some embodiments of the present disclosure. As shown inFIG. 2A, the electronic device10may include a first substrate102a, a second substrate102b, a first conductive layer104a, and a second conductive layer104b.

The second substrate102bmay be disposed opposite to the first substrate102a. In some embodiments, the material of the second substrate102bmay include, but is not limited to, glass, quartz, sapphire, ceramic, polyimide (PI), liquid-crystal polymer (LCP) materials, polycarbonate (PC), photo-sensitive polyimide (PSPI), polyethylene terephthalate (PET), other suitable substrate materials, or a combination thereof. In some embodiments, the second substrate102bmay include a flexible substrate, a rigid substrate, or a combination thereof. In some embodiments, the material of the second substrate102bmay be the same as or different from the material of the first substrate102a.

Moreover, the first conductive layer104amay be disposed on the first substrate102a. Specifically, the first conductive layer104amay be disposed on a first surface S1of the first substrate102a, and the first surface S1and a second surface S2of the first substrate102aare located on opposite sides. In addition, the second conductive layer104bmay be disposed on the second substrate102band located between the first substrate102aand the second substrate102b. Specifically, the second conductive layer104bmay be disposed on the first surface S1of the second substrate102b, and the first surface S1of the second substrate102bis adjacent to the first substrate102a.

As shown inFIG. 2A, in some embodiments, the first conductive layer104amay have an opening104p, and the opening104pmay overlap the second conductive layer104b. In accordance with the embodiments of the present disclosure, the opening104pmay be defined as a region that is exposed by the first conductive layer104a. That is, the opening104pmay substantially correspond to the region of the first surface S1of the first substrate102athat is not covered by the first conductive layer104a. In addition, the second conductive layer104bmay overlap the first conductive layer104a. In accordance with some embodiments of the present disclosure, the term “overlap” may include partial overlap or entire overlap in the normal direction of the first substrate102aor the second substrate102b(e.g., the Z direction shown in the figure).

Specifically, in some embodiments, the first conductive layer104amay be patterned to have an opening104p. In some embodiments, the second conductive layer104bmay also be patterned to have multiple regions (only a portion of the second conductive layer104bis illustrated in the figure). In some embodiments, multiple regions of the second conductive layer104bmay be connected to different circuits.

In some embodiments, the second conductive layer104bmay be electrically connected to a functional circuit (not illustrated). The functional circuit may include active components (e.g., thin film transistors and/or chips) or passive components. In some embodiments, the functional circuit may be located on the first surface S1of the second substrate102bas the second conductive layer104b. In some other embodiments, the functional circuit may be located on the second surface S2of the second substrate102b, and the functional circuit may be electrically connected to the second conductive layer104b, for example, through a via hole (not illustrated) that penetrates the second substrate102b, a flexible circuit board, or another suitable method for electrical connection, but it is not limited thereto.

In some embodiments, the first conductive layer104aand the second conductive layer104bmay include a conductive metal material. In some embodiments, the materials of the first conductive layer104aand the second conductive layer104bmay include, but are not limited to, copper, silver, tin, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, copper alloy, silver alloy, tin alloy, aluminum alloy, molybdenum alloy, tungsten alloy, gold alloy, chromium alloy, nickel alloy, platinum alloy, other suitable conductive materials or a combination thereof.

Moreover, the first conductive layer104amay have a thickness T′, and the second conductive layer104bmay have a thickness T″. In some embodiments, the thickness T′ of the first conductive layer104amay be in a range from 0.5 micrometers (μm) to 4 micrometers (μm) (i.e. 0.5 μm≤the thickness T′≤4 m), from 1.5 μm to 3.5 μm, or from 2 μm to 3 μm. In some embodiments, the thickness T″ of the second conductive layer104bmay be in a range from 0.5 μm to 4 μm (i.e. 0.5 μm≤the thickness T″≤4 μm), from 1.5 μm to 3.5 μm, or from 2 μm to 3 μm. Furthermore, the thickness T′ of the first conductive layer104amay be the same as or different from the thickness T″ of the second conductive layer104b.

In accordance with some embodiments of the present disclosure, the “thickness” of the first conductive layer104aor the second conductive layer104brefers to the maximum thickness of the first conductive layer104aor the second conductive layer104bin the normal direction of the first substrate102aor the second substrate102b(for example, the Z direction shown in the figure).

In some embodiments, the first conductive layer104aand the second conductive layer104bmay be formed by one or more deposition processes, photolithography processes, or etching processes. In some embodiments, the deposition process may include, but is not limited to, a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof. The physical vapor deposition process may include, but is not limited to, a sputtering process, an evaporation process, a pulsed laser deposition and so on. In addition, in some embodiments, the photolithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying, or another suitable process. In some embodiments, the etching process may include a dry etching process, a wet etching process, or another suitable etching process.

Moreover, as shown inFIG. 2A, the electronic device10may include a first insulating structure106. The first insulating structure106may be disposed on the first conductive layer104aso that the first conductive layer104amay be located between the first substrate102aand the first insulating structure106. In addition, the first insulating structure106may at least partially overlap a top surface104a′ and a side surface104sof the first conductive layer104a.

In some embodiments, the first insulating structure106may have a multi-layered structure. For example, in some embodiments, the first insulating structure106may include a first insulating layer106aand a second insulating layer106bdisposed on the first insulating layer106a, but the present disclosure is not limited thereto. In some embodiments, the second insulating layer106bmay expose a portion of the first insulating layer106a. In some other embodiments, the first insulating structure106may have a single layer structure.

In some embodiments, the electronic device10may further include a second insulating structure108. The second insulating structure108may be disposed on the second conductive layer104bso that the second conductive layer104bis located between the second substrate102band the second insulating structure108. Similarly, the second insulating structure108may also have a multi-layered structure or a single layer structure.

In addition, as shown inFIG. 2A, in some embodiments, the first insulating structure106may at least partially extend on the first surface S1of the first substrate102a. In other words, the first insulating structure106may at least partially overlap the opening104p. In some embodiments, the second insulating structure108may at least partially extend on the first surface S1of the second substrate102b.

In some embodiments, the first insulating structure106and the second insulating structure108may include an insulating material. In some embodiments, the first insulating structure106and the second insulating structure108may include, but are not limited to, an organic material, an inorganic material, or a combination thereof. The organic material may include, but is not limited to, polyethylene terephthalate (PET), polyethylene (PE), polyethersulfone (PES), polycarbonate (PC), polymethylmethacrylate (PMMA), polyimide (PI), photo-sensitive polyimide (PSPI) or a combination thereof. The inorganic material may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride or a combination thereof.

The material of the first insulating structure106may be the same as or different from the material of the second insulating structure108. In addition, in the embodiments in which the first insulating structure106or the second insulating structure108has a multi-layered structure, the materials of the layers may be the same or different.

In some embodiments, the first insulating structure106and the second insulating structure108may be formed by a chemical vapor deposition process, a sputtering process, a coating process, a printing process, or another suitable process, or a combination thereof. Furthermore, the first insulating structure106and the second insulating structure108may be patterned by one or more photolithography processes and etching processes.

In addition, the electronic device10may include a modulating material100M disposed between the first conductive layer104aand the second conductive layer104b. In accordance with some embodiments, a material that can be adjusted to have different properties (e.g., dielectric constants) by applying an electric field or another means can be used as the modulating material100M. In some embodiments, the transmission direction of the electromagnetic signals through the opening104pmay be controlled by applying different electric fields to the modulating material100M to adjust the capacitance.

In some embodiments, the modulating material100M may include, but is not limited to, liquid-crystal molecules (not illustrated) or microelectromechanical systems (MEMS). For example, in some embodiments, the electronic device10may include an electromagnetic element that can be used to emit or receive electromagnetic signals or a MEMS-based antenna unit, but it is not limited thereto. In accordance with some embodiments, the modulating material100M may include a liquid-crystal layer.

Specifically, in some embodiments, the functional circuit described above may apply a voltage to the second conductive layer104b, and change the properties of the modulating material100M between the first conductive layer104aand the second conductive layer104bby an electric field that is generated between the first conductive layer104aand the second conductive layer104b. Furthermore, the functional circuit may also apply another voltage to the first conductive layer104a, but it is not limited thereto. In some other embodiments, the first conductive layer104amay be electrically floating, grounded, or connected to another functional circuit (not illustrated), but it is not limited thereto.

It should be understood that one with ordinary skill in the art may adjust the number, shape or arrangement of the first conductive layer104a, the second conductive layer104band the corresponding opening104paccording to needs, and they are not limited to the aspect illustrated in the figure.

In addition, as shown inFIG. 2A, the thickness of the first insulating structure106on the first conductive layer104amay be varied in accordance with some embodiments. More specifically, in some embodiments, the thickness of the first insulating structure106on the top surface104a′ of the first conductive layer104amay be varied. In some embodiments, the first insulating structure106may include a first region106A and a second region106B. The first region106A may have a thickness TAand the second region106B may have a thickness TB. In some embodiments, the thickness TAof the first region106A may be less than a thickness TBof the second region106B, and at least a portion of the first region106A may be disposed in an overlapping region OA of the first conductive layer104aand the second conductive layer104b. In some embodiments, the first region106A may be entirely disposed in the overlapping region OA.

In some embodiments, the difference between the thickness TBof the second region106B and the thickness TAof the first region106A may be in a range from 0.1 μm to 3 μm (i.e. 0.1 μm≤the thickness TA≤3 μm), from 0.5 μm to 2.5 μm, or from 1 μm to 2 μm. It should be noted that if the difference between the thickness TAand the thickness TBis too large (for example, greater than 3 μm), the thicker insulating structure may affect the cell gap of the electronic device, thereby affecting the ability of the capacitance modulation. On the contrary, if the difference between TAand thickness TBis too small (for example, less than 0.1 μm), the ability to maintain the stability of capacitance modulation may not be significant.

It should be understood that, in accordance with some embodiments of the present disclosure, “the overlapping region OA of the first conductive layer104aand the second conductive layer104b” refers to the overlapping region of the bottom surface104a″ of the first conductive layer104aand the top surface104b′ of the second conductive layer104bin the normal direction of the first substrate102aor the second substrate102b(for example, the Z direction shown in the figure).

In addition, in accordance with some embodiments of the present disclosure, the “thickness” of the first region106A or the second region106B refers to the maximum thickness of the first region106A or the second region106B on the top surface104a′ of the first conductive layer104ain the normal direction of the first substrate102aor the second substrate102b(for example, the Z direction shown in the figure). In addition, the thicknesses of the first insulating layer106aand the second insulating layer106bdescribed below are also defined in the similar manner. Furthermore, in accordance with the embodiments of the present disclosure, the thickness of each component may be measured by using an optical microscopy (OM), a scanning electron microscope (SEM), a film thickness profiler (α-step), an ellipsometer, or another suitable method. Specifically, in some embodiments, after the modulating material100M is removed, a cross-sectional image of the structure can be taken using a scanning electron microscope, and the thickness of each component in the above image can be measured. Moreover, the maximum thickness as described above may be the maximum thickness in any cross-sectional image. In other words, the maximum thickness as described above may be the maximum thickness in a partial region of the electronic device10.

In accordance with some embodiments, the overlapping region OA may substantially define a capacitance adjustable region CA. Referring toFIG. 2Bat the same time,FIG. 2Billustrates the top-view diagram of a portion of the electronic device10in accordance with some embodiments of the present disclosure, andFIG. 2Ais the cross-sectional structure along the line segment A-A′ inFIG. 2B. It should be understood that only the second conductive layer104band the first insulating structure106are shown inFIG. 2Band other components are omitted in order to clearly illustrate the relationship between the overlapping region OA and the capacitance adjustable region CA.

Specifically, the first conductive layer104aand the second conductive layer104band the modulating material100M located therebetween may form a capacitor structure. The capacitance adjustable region CA of the capacitor structure may substantially correspond to the overlapping region OA and overlap with the overlapping region OA. However, the area where the electromagnetic signal is actually affected by the capacitance will be larger than the overlapping area OA. In accordance with some embodiments, the capacitance adjustable region CA is defined as an area extending outward from the edge of the overlapping region OA by a first distance d1. In some embodiments, the first distance d1may be about 1 mm.

As described above, in some embodiments, the first insulating structure106may include the first insulating layer106aand the second insulating layer106b. In some embodiments, the first region106A may include the first insulating layer106a, and the second region106B may include the first insulating layer106aand the second insulating layer106b. As shown inFIGS. 2A and 2B, in some embodiments, the second region106B may surround the first region106A, and the second region106B may be adjacent to the opening104p. Moreover, in some embodiments, the first region106A and the second conductive layer104bat least partially overlap.

Specifically, the first insulating layer106amay have a thickness T1, and the second insulating layer106bmay have a thickness T2. In some embodiments, the thickness T2of the second insulating layer106bmay be greater than the thickness T1of the first insulating layer106a. In some embodiments, the thickness T1of the first insulating layer106amay be in a range from 100 angstroms (Å) to 1500 angstroms (Å) (i.e. 100 Å≤the thickness T1≤1500 Å), from 300 Å to 1300 Å, or from 500 Å to 1000 Å, for example, 600 Å, 700 Å, 800 Å, or 900 Å. In some embodiments, the thickness T2of the second insulating layer106bmay be in a range from 500 Å to 3,000 Å (i.e. 500 Å≤the thickness T2≤3000 Å), from 1000 Å to 2500 Å, or from 1500 Å to 2,000 Å, for example, 1600 Å, 1700 Å, 1800 Å, or 1900 Å.

As described above, the first region106A may have a smaller thickness, and the overlapping region OA of the first conductive layer104aand the second conductive layer104bmay at least partially overlap with the first region106A so that the capacitance adjustable region CA may at least partially overlap with the first region106A. With such a configuration, the dielectric loss of the electromagnetic signals may be reduced, or the stability of the capacitance modulation can be maintained.

On the other hand, the second region106B may have a greater thickness, and is less likely to generate pinholes during the fabrication process, which may reduce the corrosion of the first conductive layer104aor reduce the diffusion of metal ions of the first conductive layer104into the modulating material100M. In addition, since the second region106B having a greater thickness is mostly located outside the capacitance adjustable region CA, it may have little effect on the dielectric loss of the electromagnetic signals.

In addition, in accordance with some embodiments, alignment layers (not illustrated) may be further disposed between the first insulating structure106and the modulating material100M, and between the second insulating structure108and the modulating material100M to control the alignment direction of the liquid-crystal molecules in the modulating material100M. In some embodiments, the material of the alignment layer may include, but is not limited to, an organic material, an inorganic material, or a combination thereof. For example, the organic material may include, but is not limited to, polyimide (PI), a photo-reactive polymer material, or a combination thereof. The inorganic material may include, for example, silicon oxide (SiO2), but it is not limited thereto.

In accordance with some embodiments, a buffer layer (not illustrated) may be further disposed between the first substrate102aand the first conductive layer104a, and between the second substrate102band the second conductive layer104b, so that the expansion coefficient of the first substrate102aand the first conductive layer104aand/or the expansion coefficient of the second substrate102band the second conductive layer104bmay be matched. In some embodiments, the material of the buffer layer may include, but is not limited to, an organic insulating material, an inorganic insulating material, a metal material, or a combination thereof.

The organic insulating material may include, but is not limited to, an organic compound of acrylic acid or methacrylic acid, an isoprene compound, a phenol-formaldehyde resin, benzocyclobutene (BCB), perfluorocyclobutane (PECB), polyimide, polyethylene terephthalate (PET), or a combination thereof. The inorganic material may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride or a combination thereof. The metal material may include, but is not limited to, titanium, molybdenum, tungsten, nickel, aluminum, gold, chromium, platinum, silver, copper, titanium alloy, molybdenum alloy, tungsten alloy, nickel alloy, aluminum alloy, gold alloy, chromium alloy, platinum alloy, silver alloy, copper alloy, another suitable material, or a combination thereof.

In addition, in accordance with some embodiments, the electronic device10may further include a spacer element (not illustrated) disposed between the first substrate102aand the second substrate102b. The spacer element may be disposed in the modulating material100M to enhance the structural strength of the electronic device10. In some embodiments, the spacer elements may have a ring-shaped structure. In some embodiments, the spacer elements may have columnar structures that are arranged in parallel.

In addition, the spacer element may include an insulating material or a conductive material, or a combination thereof. In some embodiments, the conductive material may include, but is not limited to, copper, silver, gold, copper alloy, silver alloy, gold alloy, or a combination thereof. In some other embodiments, the insulating material may include, but is not limited to, polyethylene terephthalate (PET), polyethylene (PE), polyethersulfone (PES), polycarbonate (PC), polymethylmethacrylate (PMMA), glass or a combination thereof.

Next, refer toFIG. 3, which illustrates the cross-sectional diagram of a portion of the electronic device10in accordance with some other embodiments of the present disclosure. Specifically,FIG. 3illustrates an enlarged cross-sectional diagram of the region E of the electronic unit100shown inFIG. 1in accordance with some other embodiments of the present disclosure. It should be understood that the same or similar components or elements in above and below contexts are represented by the same or similar reference numerals. The materials, manufacturing methods and functions of these components or elements are the same or similar to those described above, and thus will not be repeated herein.

The embodiment shown inFIG. 3is similar to the embodiment shown inFIG. 2A. The difference between them is that the second insulating structure108of the electronic device10shown inFIG. 3also has a greater thickness in a partial region. As shown inFIG. 3, the second insulating structure108may be disposed on the second conductive layer104band located between the second conductive layer104band the modulating material100M. In this embodiment, the second insulating structure108may include a third insulating layer108aand a fourth insulating layer108bdisposed on the third insulating layer108a. The material of the third insulating layer108amay be the same as or different from the material of the fourth insulating layer108b.

As shown inFIG. 3, the thickness of the second insulating structure108on the second conductive layer104bmay be varied. More specifically, the thickness of the second insulating structure108on the top surface104b′ of the second conductive layer104bmay be varied. In this embodiment, the second insulating structure108may include a third region108A and a fourth region108B, and the third region108A may have a thickness TCand the fourth region108B may have a thickness TD. In some embodiments, the thickness TCof the third region108A may be less than the thickness TDof the fourth region108B, and the fourth region108B may overlap the second conductive layer104b.

Furthermore, in some embodiments, at least a portion of the third region108A may be disposed in the overlapping region OA of the first conductive layer104aand the second conductive layer104b, and the fourth region108B having a greater thickness may be mostly located outside the overlapping region OA or the capacitance adjustable region CA. In some embodiments, the difference between the thickness TCof the third region108A and the thickness TDof the fourth region108B may be in a range from 0.1 μm to 3 μm (i.e. 0.1 μm≤the thickness TD≤3 μm), from 0.5 μm to 2.5 μm, or from 1 μm to 2 μm. In some embodiments, the thickness TCof the third region108A may be in a range from 0.1 μm to 3 μm (i.e. 0.1 μm≤the thickness TC≤3 μm), from 0.5 μm to 2.5 μm, or from 1 μm to 3 μm. In some embodiments, the thickness TDof the fourth region108B may be in a range from 0.1 μm to 3.5 μm (i.e. 0.1 μm≤the thickness TD≤3 μm), from 0.5 μm to 2.5 μm, from 1 μm to 3 μm, or from 1.5 μm to 3.5 μm.

Moreover, in accordance with some embodiments of the present disclosure, the “thickness” of the third region108A or the fourth region108B refers to the maximum thickness of the third region108A or the fourth region108B on the top surface104B′ of the second conductive layer104B in the normal direction of the first substrate102aor the second substrate102b(for example, the Z direction shown in the figure). In addition, the thicknesses of the third insulating layer108aand the fourth insulating layer108bdescribed below are also defined in the similar manner.

As described above, in some embodiments, the second insulating structure108may include the third insulating layer108aand the fourth insulating layer108b. In some embodiments, the third region108A may include the third insulating layer108a, and the fourth region108B may include the third insulating layer108aand the fourth insulating layer108b. In some embodiments, the third region108A may overlap with the first conductive layer104a. In some embodiments, the fourth insulating layer108bof the fourth region108B may partially overlap with the second insulating layer106bof the second region106B.

In addition, the third insulating layer108amay have a thickness T3, and the fourth insulating layer108bmay have a thickness T4. In some embodiments, the thickness T4of the fourth insulating layer108bmay be greater than the thickness T3of the third insulating layer108a. In some embodiments, the thickness T3of the third insulating layer108amay be in a range from 100 Å to 1500 Å (i.e. 100 Å≤the thickness T3≤1500 Å), from 300 Å to 1300 Å, or from 500 Å to 1000 Å, for example, 600 Å, 700 Å, 800 Å, or 900 Å. In some embodiments, the thickness T4of the fourth insulating layer108bmay be in a range from 500 Å to 3000 Å (i.e. 500 Å≤the thickness T4≤3000 Å), from 1000 Å to 2500 Å, or from 1500 Å to 2,000 Å, for example, 1600 Å, 1700 Å, 1800 Å, or 1900 Å.

Next, refer toFIG. 4AandFIG. 4B, which respectively illustrate the cross-sectional diagram of a portion of the electronic device10and the top-view diagram of a portion of the electronic device10in accordance with some other embodiments of the present disclosure, andFIG. 4Ais the cross-sectional structure along the line segment A-A′ inFIG. 4B. It should be understood that only the second conductive layer104band the first insulating structure106are shown inFIG. 4Band other components are omitted.

The embodiment shown inFIG. 4Ais similar to the embodiment shown inFIG. 2A. The difference between them is that the second insulating layer106bof the electronic device10shown inFIG. 4Adoes not extend into the opening104p. Specifically, in this embodiment, the second insulating layer106bmay be at least partially disposed on the side surface104sof the first conductive layer104athat is adjacent to the opening104p. Furthermore, as shown inFIGS. 4A and 4B, in some embodiments, a portion of the second insulating layer106bmay not overlap with the second conductive layer104b.

In this embodiment, the first region106A of the first insulating structure106may further extend adjacent the opening104p, and the first region106A may be adjacent to the opening104p. In addition, at least a portion of the first region106A may be disposed in the overlapping region OA of the first conductive layer104aand the second conductive layer104band the capacitance adjustable region CA. In some embodiments, the first region106A may be entirely disposed in the overlapping region OA.

As described above, the first region106A may have a smaller thickness, and the overlapping region OA of the first conductive layer104aand the second conductive layer104band the capacitance adjustable region CA may at least partially overlap with the first region106A. The stability of the capacitance modulation therefore may be maintained. On the other hand, the second region106B may have a larger thickness and is less likely to generate pinholes during the fabrication process, which may reduce the corrosion of the first conductive layer104aor reduce the diffusion of metal ions of the first conductive layer104into the modulating material100M.

Next, refer toFIG. 5, which illustrates the cross-sectional diagram of a portion of the electronic device10in accordance with some other embodiments of the present disclosure. The embodiment shown inFIG. 5is similar to the embodiment shown inFIG. 4A, except that the second insulating structure108of the electronic device10shown inFIG. 5also has a greater thickness in a partial region. That is, the thickness of the second insulating structure108may be varied. As shown inFIG. 5, the second insulating structure108may be disposed between the second conductive layer104band the modulating material100M. In this embodiment, the second insulating structure108may include the third insulating layer108aand the fourth insulating layer108bdisposed on the third insulating layer108a. The second insulating structure108in the embodiment shown inFIG. 5is similar to that ofFIG. 3, and thus will not be repeated herein.

To summarize the above, in the antenna device provided by the embodiments of the present disclosure, an insulating structure may have a smaller thickness in the portion corresponding to the capacitance adjustable region, thereby maintaining the stability of the capacitance modulation or improving the operational reliability of the antenna device. Furthermore, in accordance with some embodiments, the insulating structure may have a greater thickness in the portion other than the capacitance adjustable region, thereby the risk of corrosion of the conductive layer or diffusion of metal ions may be reduced.