Audio apparatus, switching power supply, and switching control method

When power is turned on and in a state in which a power supply voltage is not supplied from the switching power supply to the second clock generating section, the first clock generating section generates a first clock signal with a frequency that is preset in the first clock generating section, without using a third clock signal from the frequency dividing section, to cause the first switching section to operate. By the first switching section operating, a power supply voltage is supplied from the switching power supply to the second clock generating section. After the second clock generating section has started to operate, a third clock signal (a clock signal obtained by dividing the frequency of a second clock signal generated by the second clock generating section) is supplied from the frequency dividing section to the first clock generating section. The first clock generating section generates a first clock signal with a frequency that is synchronized with the frequency of the third clock signal, to cause the first switching section to operate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an audio apparatus that includes a switching amplifier and a switching power supply and controls the frequency of a clock signal that drives the switching power supply.

2. Description of the Related Art

Currently, an audio apparatus including a switching amplifier and a switching power supply is available. When combining a switching amplifier and a switching power supply, since clock signals that drive the two have different frequencies (also called carrier frequencies), interference (beat) occurs between the frequencies and falls down in an audible band, causing a big problem.

To suppress this, generation of clock signals of the switching amplifier and the switching power supply from the same source is considered. However, in the switching amplifier, in view of an influence on the audible band and an improvement in performance, the frequency of a clock signal is often set to a relatively high frequency (several hundred kHz or higher); on the other hand, in the switching power supply, in order to prevent an increase in switching loss, the frequency of a clock signal is set to a relatively low frequency. Thus, it is not realistic to set the same frequency for them.

To solve this problem, there is proposed a technique for suppressing occurrence of a beat by dividing the frequency of a clock signal that drives a switching amplifier at an arbitrary frequency division ratio and using a resultant frequency as the frequency of a clock signal that drives a switching power supply. With this technique, however, when power to an audio apparatus is turned on and in a state in which a power supply voltage from the switching power supply is not supplied to a clock generation circuit that generates a clock signal of the switching amplifier, a clock signal used to operate the switching amplifier cannot be generated. Thus, it is not also possible to generate a clock signal of the switching power supply by frequency-dividing a clock signal of the switching amplifier. Hence, there is a need to separately provide another power supply circuit (other than the switching power supply) for supplying, when power is turned on, a power supply voltage to a clock generation circuit for generating a clock signal of the switching amplifier, and cause the clock generation circuit to operate by a power supply voltage from another power supply circuit to generate a clock signal of the switching amplifier.

SUMMARY OF THE INVENTION

An object of the present invention is therefore to provide an audio apparatus that generates a clock signal of a switching power supply by dividing the frequency of a clock signal of a switching amplifier and is capable of causing the switching power supply to start to operate without separately providing another power supply circuit that supplies, when power is turned on, a power supply voltage to a clock generation circuit that generates a clock signal of the switching amplifier.

An audio apparatus as a preferred embodiment of the present invention comprises a switching power supply, a switching amplifier, and frequency dividing section, wherein the switching power supply includes: first switching section for outputting a power supply voltage to the switching amplifier by performing a switching operation; and first clock generating section for generating a first clock signal that causes the first switching section to perform a switching operation, the switching amplifier includes: pulse modulating section for generating a pulse modulated signal according to an input signal; second switching section that performs a switching operation by the pulse modulated signal; and second clock generating section caused to operate by the power supply voltage supplied from the switching power supply, to generate a second clock signal that drives the pulse modulating section, the frequency dividing section divides a frequency of the second clock signal supplied from the second clock generating section, to generate a third clock signal, in a state in which the third clock signal is not supplied from the frequency dividing section to the first clock generating section because a power supply voltage is not supplied from the switching power supply to the second clock generating section, the first clock generating section generates the first clock signal with a frequency that is preset in the first clock generating section, and in a state in which a power supply voltage is supplied from the switching power supply to the second clock generating section and thus the third clock signal is supplied from the frequency dividing section to the first clock generating section, the first clock generating section generates the first clock signal with a frequency that is synchronized with a frequency of the third clock signal.

When power is turned on and in a state in which a power supply voltage is not supplied from the switching power supply to the second clock generating section, the first clock generating section generates a first clock signal with a frequency that is preset in the first clock generating section, without using a third clock signal from the frequency dividing section, to cause the first switching section to operate. By the first switching section operating, a power supply voltage is supplied from the switching power supply to the second clock generating section. Accordingly, when power is turned on, too, the second clock generating section can be caused to start to operate by a power supply voltage from the switching power supply and thus there is no need to separately provide another power supply circuit for causing the second clock generating section to operate when power is turned on.

After the second clock generating section has started to operate, a third clock signal (a clock signal obtained by dividing the frequency of a second clock signal generated by the second clock generating section) is supplied from the frequency dividing section to the first clock generating section. The first clock generating section generates a first clock signal with a frequency that is synchronized with the frequency of the third clock signal, to cause the first switching section to operate. As used herein, the frequency that is synchronized with the frequency of the third clock signal refers to, for example, a frequency that is the same as the frequency of the third clock signal or a frequency obtained by further dividing the frequency of the third clock signal (e.g., by reducing the frequency to half). Accordingly, occurrence of a beat can be prevented by the first clock signal and the second clock signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although a preferred embodiment of the present invention will be described in detail below with reference to the drawings, the present invention is not limited thereto.FIG. 1is a schematic block diagram showing an audio apparatus1including a switching power supply101and a switching amplifier102, according to a preferred embodiment of the present invention. FIG.2is a circuit diagram showing a detailed configuration of the audio apparatus1.

As shown inFIG. 1, the audio apparatus1includes the switching power supply (DC/DC converter)101that supplies a power supply voltage to the switching amplifier102; the switching amplifier102that performs switching amplification on an input signal (audio signal) to be inputted from an external source and supplies the amplified signal to a speaker (not shown); and a frequency division circuit103that frequency-divides a clock signal that drives a pulse width modulation circuit of the switching amplifier102and supplies a resultant clock signal to the switching power supply101.

In the audio apparatus1, when power is turned on, the switching power supply101starts a switching operation based on a clock signal with a frequency that is preset in a first clock generation circuit104of the switching power supply101, and supplies a power supply voltage to the switching amplifier102. When the power supply voltage from the switching power supply101is supplied to the switching amplifier102, a second clock generation circuit105of the switching amplifier102starts to operate. The switching amplifier102performs a switching operation by a clock signal generated by the second clock generation circuit105. The clock signal generated by the second clock generation circuit105is frequency-divided by the frequency division circuit103and a resultant clock signal is supplied to the first clock generation circuit104of the switching power supply101. The first clock generation circuit104generates a clock signal having a frequency based on (i.e., synchronized with) the frequency of the clock signal from the frequency division circuit103and the switching power supply101performs a switching operation by the clock signal. Therefore, when power is tuned on, too, the second clock generation circuit105can be caused to start to operate by a power supply voltage from the switching power supply101and thus there is no need to separately provide another power supply circuit for causing the second clock generation circuit105to operate when power is turned on.

The switching power supply101performs a switching operation on switching elements for switching an input power supply voltage (direct-current voltage) E, by a clock signal with a frequency set in the first clock generation circuit104, for immediately after power is turned on; and performs a switching operation on the switching elements by a clock signal generated to be synchronized with a clock signal supplied from the frequency division circuit103, for after the switching amplifier102has started to operate.

As shown inFIG. 2, the switching power supply101includes a switching circuit11, a transformer T, a rectifier circuit12, a smoothing circuit13, and the first clock generation circuit104.

The switching circuit11switches an input voltage E which is a direct-current voltage and converts the input voltage E into an alternating voltage having a predetermined frequency. The switching circuit11includes first and second switching elements SW1and SW2composed of, for example, MOSFETs. The first switching element SW1is on/off operated by a clock signal CLK1supplied from the first clock generation circuit104and the second switching element SW2is on/off operated by a clock signal CLK2.

The transformer T increases a voltage value inputted to a primary winding to a predetermined voltage value and outputs the predetermined voltage value from a secondary winding. The rectifier circuit12rectifies an output from the secondary winding of the transformer T and includes, for example, a diode bridge circuit. The smoothing circuit13includes capacitors C1and C2and smoothes an output from the rectifier circuit12. An output from the smoothing circuit13is supplied, as a power supply voltage, to the switching amplifier102from an output terminal.

The first clock generation circuit104generates clock signals CLK1and CLK2for causing the first and second switching elements SW1and SW2to be on/off operated. The first clock generation circuit104includes a clock generating unit14and terminals104ato104e. To the terminals104aand104bare connected a resistor R1and a capacitor C3, respectively. By the resistor R1and the capacitor C3, the frequency (e.g., about 180 kHz) of a clock signal CLK0generated by the clock generating unit14when power is turned on is set. The terminal104cis connected to an output terminal of the frequency division circuit103. After the second clock generation circuit105has started to operate, a clock signal CLK4is supplied from the frequency division circuit103to the clock generating unit14.

When power is turned on and in a state in which a clock signal CLK4is not supplied from the frequency division circuit103to the terminal104c, the clock generating unit14generates a clock signal CLK0with a predetermined frequency (about 180 kHz) which is determined by the resistor R1and the capacitor C3. The first clock generation circuit104generates clock signals CLK1and CLK2whose frequencies are half (i.e., the frequencies are about 90 kHz) that of the clock signal CLK0generated by the clock generating unit14, and supplies the clock signals CLK1and CLK2to the first and second switching elements SW1and SW2, respectively, through the terminals104dand104e.

On the other hand, after the switching amplifier102has started to operate and in a state in which a clock signal CLK4is supplied from the frequency division circuit103to the terminal104c, the clock generating unit14generates a clock signal CLK0having the same frequency (about 200 kHz) as the clock signal CLK4. That is, the clock generating unit14generates a clock signal CLK0that is synchronized with the frequency of the clock signal CLK4. The first clock generation circuit104generates clock signals CLK1and CLK2whose frequencies are half (i.e., the frequencies are about 100 kHz) that of the clock signal CLK0generated by the clock generating unit14, and supplies the clock signals CLK1and CLK2to the first and second switching elements SW1and SW2, respectively, through the terminals104dand104e.

The switching amplifier102modulates the pulse width of an input signal in a pulse modulation circuit (e.g., a pulse width modulation circuit) and thereby generates a pulse width modulated signal, and performs on/off control of switching elements according to the pulse width modulated signal and thereby amplifies the input signal.FIG. 3is a schematic block diagram showing a configuration of the switching amplifier102. The switching amplifier102includes a pulse width modulation circuit21, a driver22, a switching output circuit23, an LPF (Low-Pass Filter)24, and the second clock generation circuit105. Note that inFIG. 2, the driver22, the switching output circuit23, and the LPF24are not described.

The pulse width modulation circuit21modulates the pulse width of an input signal based on a clock signal CLK3(the frequency is 400 kHz, for example) supplied from the second clock generation circuit105and thereby generates a first pulse width modulated signal OUT1and a second pulse width modulated signal OUT2. When one of the first pulse width modulated signal OUT1and the second pulse width modulated signal OUT2is a high-level signal, the other is a low-level signal. The driver22accepts as input the first pulse width modulated signal OUT1and the second pulse width modulated signal OUT2and outputs drive signals DRV1and DRV2for driving switching elements which will be described later.

The switching output circuit23is connected between a first power supply (e.g., a positive power supply +VD) and a second power supply (e.g., a negative power supply −VD) which are supplied from the switching power supply101, and outputs a positive power supply +VD or a negative power supply −VD in response to a drive signal. The switching output circuit23includes switching elements (e.g., MOSFETs) SW3and SW4.

The LPF24is connected between an output terminal of the switching output circuit23and an output terminal of the switching amplifier102. The LPF24removes a high-frequency component and outputs the resultant to a load such as a speaker. The LPF24includes a coil28and a capacitor29.

The second clock generation circuit105generates a clock signal CLK3for driving the pulse width modulation circuit21. As shown inFIG. 2, the second clock generation circuit105includes an oscillation device (e.g., CERALOCK)30, resistors R2and R3, capacitors C4and C5, and inverters31to33. A clock signal outputted from the oscillation device30is waveform-shaped by the resistors R2and R3, the capacitors C4and C5, and the inverters31and32, whereby a rectangular wave-shaped clock signal CLK3is generated. The frequency of the clock signal CLK3is 400 kHz, for example. The clock signal CLK3is supplied to the pulse width modulation circuit21. The inverter33inverts and buffers the clock signal CLK3and supplies the clock signal CLK3to the frequency division circuit103.

The frequency division circuit103generates a clock signal CLK4which is obtained by frequency-dividing a clock signal CLK3supplied from the second clock generation circuit105at a predetermined frequency division ratio, and supplies the clock signal CLK4to the first clock generation circuit104of the switching power supply101. As described above, when the first clock generation circuit104outputs clock signals CLK1and CLK2whose frequencies are half that of a clock signal CLK0generated by the clock generating unit14, in order to obtain clock signals CLK1and CLK2(about 100 kHz) which drive the switching power supply101by reducing the frequency (about 400 kHz) of a clock signal CLK3which drives the pulse width modulation circuit21to one-quarter, the frequency division ratio of the frequency division circuit103is set to 2. That is, the frequency division circuit103divides the frequency of the clock signal CLK3by two and thereby generates a clock signal CLK4whose frequency is half (about 200 kHz) that of the clock signal CLK3.

As shown inFIG. 2, the frequency division circuit103includes a frequency dividing unit (e.g., a flip-flop circuit)51that frequency-divides a clock signal CLK3from the second clock generation circuit105by half, an inverter52, an AND circuit53, a resistor R4, and a capacitor C6. To one input terminal of the AND circuit53is supplied an output from the frequency dividing unit51, and to an other input terminal is supplied a signal obtained by inverting the output from the frequency dividing unit103by the inverter52and making the rise and fall of the inverted output gradual by the resistor R4and the capacitor C6. As a result, a clock signal CLK4outputted from the AND circuit53is a clock signal obtained by dividing the frequency of the clock signal CLK3by half and shortening a high-level period. Such a clock signal CLK4is used by the clock generating unit14of the first clock generation circuit104to generate a clock signal CLK0having the same frequency as (synchronized with) the clock signal CLK4generated by the frequency division circuit103.

The operation of the audio apparatus1having the above-described configuration will be described. Note thatFIGS. 4A to 4Eshow waveform simulation results at various points. Immediately after power is turned on, a power supply voltage is not supplied from the switching power supply101to the switching amplifier102and thus the second clock generation circuit105cannot supply a clock signal CLK3to the pulse width modulation circuit21and the frequency division circuit103. Hence, a clock signal CLK4is not supplied from the frequency division circuit103to the clock generating unit14of the first clock generation circuit104of the switching power supply101.

When a power supply voltage E is supplied to the first clock generation circuit104, the clock generating unit14generates a clock signal CLK0with a frequency (about 180 kHz) that is preset by the resistor R1and the capacitor C3(seeFIG. 4A). The first clock generation circuit104outputs clock signals CLK1and CLK2whose frequencies are half that of the clock signal CLK0, to the switching elements SW1and SW2(seeFIG. 4B). Accordingly, the switching elements SW1and SW2switch the power supply voltage E, whereby the switching power supply circuit101supplies a power supply voltage to the switching amplifier102.

When the power supply voltage is supplied from the switching power supply circuit101to the switching amplifier102, the second clock generation circuit105generates a clock signal CLK3(about 400 kHz). By the clock signal CLK3, the switching amplifier102starts to operate. Specifically, the pulse width modulation circuit21generates a pulse width modulated signal which is modulated using an input signal based on the clock signal CLK3, and by the pulse width modulated signal the switching elements SW3and SW4perform a switching operation.

The clock signal CLK3from the second clock generation circuit105is supplied also to the frequency division circuit103. The frequency division circuit103generates a clock signal CLK4(the frequency is about 200 kHz) obtained by dividing the frequency of the clock signal CLK3by half and furthermore shortening a high-level period, and supplies the clock signal CLK4to the first clock generation circuit104(seeFIG. 4C).

When the clock signal CLK4is supplied to the first clock generation circuit104, the clock generating unit14generates a clock signal CLK0having the same frequency (about 200 kHz) as the clock signal CLK4(seeFIG. 4D). More specifically, the clock generating unit14generates a clock signal that rises to a high level in response to a rise of the clock signal CLK4to a high level and thereby generates a clock signal CLK0having the same frequency as the clock signal CLK4. The first clock generation circuit104outputs clock signals CLK1and CLK2whose frequencies are half (about 100 kHz) that of the clock signal CLK0, to the switching elements SW1and SW2(seeFIG. 4E). Accordingly, the switching power supply101is driven by the clock signals CLK1and CLK2with a frequency that is obtained by frequency-dividing the clock signal CLK3which drives the pulse width modulation circuit21of the switching amplifier102to one-quarter (frequency division by four). As a result, occurrence of a beat can be prevented by the clock signal CLK3and the clock signals CLK1and CLK2.

As described above, when power is turned on and the second clock generation circuit105of the switching amplifier102cannot generate a clock signal CLK3, the first clock generation circuit104generates clock signals CLK1and CLK2with a preset frequency to cause the switching elements SW1and SW2to perform a switching operation. Thus, there is no need to separately provide a power supply circuit for causing the second clock generation circuit105to operate when power is turned on. After the second clock generation circuit105has started to operate, the first clock generation circuit104generates clock signals CLK1and CLK2with a frequency obtained by dividing the frequency of a clock signal CLK3which drives the pulse width modulation circuit21, to cause the switching elements SW1and SW2to perform a switching operation. Accordingly, since in a steady state the clock signal CLK3and the clock signals CLK1and CLK2have an integral multiple relationship (are synchronized with each other), occurrence of a beat can be prevented.

Although the preferred embodiment of the present invention is described above, the present invention is not limited thereto. For example, the frequencies of clock signals CLK0to CLK4are not limited to those described above. Also, a pulse density modulation circuit may be used instead of a pulse width modulation circuit.