Redundancy circuit for memory array and method for disabling non-redundant wordlines and for enabling redundant wordlines

A redundancy circuit for a memory array and a method are provided for disabling non-redundant wordlines and for enabling redundant wordlines. A memory defect address is compared with a current address to be accessed. When there is a miscompare, the access to a non-redundant wordline is allowed to take place as normal. When the memory defect address matches the current address the entire wordline decoder is deactivated through a reset signal and the redundant wordline is activated.

FIELD OF THE INVENTION

The present invention relates generally to the data processing field, and more particularly, relates to a redundancy circuit for a memory array and a method for disabling non-redundant wordlines and for enabling redundant wordlines.

DESCRIPTION OF THE RELATED ART

In order to improve yield of memory arrays, the ability to utilize redundant words is a necessity. When a chip is manufactured, it is done on a wafer with many copies of the chip filling the surface area of the wafer. Many of these chips will have defects as a result of the manufacturing process. These defects can be such that connections on the chip are either permanently shorted together or permanently open such that there is no connection where there ought to be one. Typically such defects are detected in the manufacturing process and chips that contain them are discarded.

Memory arrays are very regular structures that take up vast amounts of space on a chip. Memory arrays, thus, are prone containing defects as a percentage of all the pieces that make up the chip. To mitigate this, a technique called redundancy was developed and is common in the industry.

Essentially, an array implemented with redundancy has extra groups of memory cells including rows (wordlines) or columns (bitlines) or both. If the array is determined by its array built-in self-test (ABIST) to not have any defects, then the redundant memory elements are not activated or used. If defects in a redundancy array are detected, the ABIST determines if the defect can be fixed by utilizing any of the redundant elements available. Some defects still cannot be fixed and these chips are discarded.

If a defect in a memory array can be fixed with a redundant wordline or bitline, then the redundancy method and apparatus particular to that specific memory array needs to be activated.

A need exists for an improved redundancy circuit for a memory array and a method for disabling non-redundant wordlines and for enabling redundant wordlines. It is desirable to provide such redundancy circuit for a memory array and a method for disabling non-redundant wordlines and for enabling redundant wordlines for use with an existing array design with no redundancy.

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide a redundancy circuit for a memory array and a method for disabling non-redundant wordlines and for enabling redundant wordlines. Other important objects of the present invention are to provide such redundancy circuit for a memory array and a method for disabling non-redundant wordlines and for enabling redundant wordlines substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.

In brief, a redundancy circuit for a memory array and a method are provided for disabling non-redundant wordlines and for enabling redundant wordlines. A memory defect address is compared with a current address to be accessed. When there is a miscompare, the access to a non-redundant wordline is allowed to take place as normal. When the memory defect address matches the current address the entire wordline decoder is deactivated through a reset signal and the redundant wordline is activated.

A miscompare detector compares a current address to be accessed with a defect address. The miscompare detector provides an enable redundant wordline signal responsive to a match of the compared addresses. A deactivate driver circuit coupled to the miscompare detector disables non-redundant wordlines responsive to the enable redundant wordline signal. A redundant driver coupled to the miscompare detector enables a redundant wordline responsive to the enable redundant wordline signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In accordance with features of the preferred embodiment, a new redundancy circuit and a method are provided for implementing redundancy for a memory array, for example, for use with an existing array that had been previously implemented without redundancy.

The redundancy method of the preferred embodiment assumes that the address bits referring to the memory section containing the defect are readily available signals. These signals could come from fuses or latches elsewhere on the chip that have been permanently activated as a part of the manufacturing process. It should be understood that the memory section with the defect could either be a bitline or a wordline, while the present descriptions refers to wordlines for simplicity.

In accordance with features of the preferred embodiment, a memory defect address or fuse address is compared with a current address to be accessed.FIG. 1illustrates an exemplary miscompare detector in accordance with the preferred embodiment. If there is a miscompare, the access is allowed to take place as normal. When the fuse address matches the current address the entire wordline decoder is deactivated through a reset signal and the redundant wordline is activated.FIG. 2illustrates an exemplary deactivate driver circuit for deactivating a non-redundant wordline decoder in accordance with the preferred embodiment.

Having reference now to the drawings, inFIG. 1, there is shown an exemplary miscompare detector generally designated by the reference character100of the preferred embodiment. Miscompare detector100is a dynamic circuit for comparing a current address to be accessed with a fuse address for enabling a redundant wordline with a match of the fuse address and disabling non-redundant wordlines in accordance with the preferred embodiment. The ACQUIRE and CLKOUT signals can be considered clocks. The combination of a pair of P-channel field effect transistors (PFETs)102and104form a precharge circuit coupled between a positive supply VDD and a common precharge node labeled COMMON PRECHARGE. A pair of N-channel field effect transistor (NFETS)106,108is coupled in series between the common precharge node and ground. The source drain connection of NFETs106,108is connected to a common discharge node labeled COMMON DISCHARGE. NFET108is a discharge device. An inverter formed of a PFET110and an NFET112is connected in series between the voltage supply VDD and ground. A common drain connection of PFET110and NFET112is connected to a gate of precharge PFET102at a node labeled NET. The ACQUIRE signal is applied to a gate input of PFET110and NFET112. The CLKOUT signal is applied to a gate input of precharge PFET104and discharge NFET108. An enable signal labeled nF_En is applied to a gate input of NFET106.

As shown, a plurality of compare NFETs (1-N)122,124,126,128,130,132,134and136are connected between the common precharge node and the common discharge node. A particular number N of compare NFETs is provided depending upon the number of address bits in the decoder being affected by the redundancy. A PFET138is connected between the voltage supply VDD and the common precharge node. A first series connected PFET140and NFET142and a second series connected PFET144and NFET146are connected between the voltage supply VDD and ground. A common gate connection of PFET140and NFET142is connected to the common precharge node. A common gate connection of PFET144and NFET146is connected to a gate of PFET138and to the common drain connection of PFET140and NFET142. A wordline driver output labeled WL_DRIVER is provided at the common drain connection of PFET144and NFET146.

When the ACQUIRE signal is high and the CLKOUT signal is low, the common precharge node is precharged to the positive supply VDD. When CLKOUT goes high, the common precharge node is able to either discharge to ground or maintain its precharged state. If any of the compare NFETs (1-N)122,124,126,128,130,132,134and136is activated, there has been a miscompare between the fuse address and the current address. In this case, the CMP<x> signal will be high, where x represents any of CMP<0> through CMP<7> and the common precharge node discharges through the discharge NFET108. The wordline driver output labeled WL_DRIVER signal tracks with Common_Precharge. When the common precharge node discharges, an access to the redundant wordline is prevented. In the case of match between the fuse address and the current address, then none of the compare NFETs (1-N)122,124,126,128,130,132,134and136is activated. In this case, the common precharge node maintains its precharged state, and thus, the access will go to the redundant wordline.

Referring now toFIGS. 2,3A,3B,3C, and3D, inFIG. 2there is shown an exemplary deactivate driver circuit to deactivate the non-redundant Wordline Decoder (WDEC) generally designated by the reference character200of the preferred embodiment.FIGS. 3A,3B,3C, and3D together illustrate an exemplary redundancy circuit for a memory array generally designated by the reference character300. The exemplary redundancy circuit300includes four miscompare detectors100ofFIG. 1with the deactivate driver circuit200ofFIG. 2in accordance with the preferred embodiment.

Deactivate circuit200includes a keeper circuit formed by a pair of PFETs201,202and an NFET204with PFET201coupled between voltage supply VDD and a reset common node labeled RESET COMMON. A gate input of PFET202and NFET204is connected to the reset common node and a gate input of PFET201is connected to the common drain connection of PFET202and NFET204. Deactivate circuit200includes a plurality of 2-high NFET stacks formed by respective pairs of NFETs208,210;212,214;216,218; and220,222, each pair coupled between the reset common node and ground. Deactivate circuit200includes a PFET224coupled between the voltage supply VDD and the reset common node with a gate input of a RESET_IN signal. A pair of PFETs226,228having a source connection to the voltage supply VDD and a respective gate connection to the RESET_IN signal and the reset common node. A pair of series connected NFETs230,232are connected between common drain connection of PFETs226,228and ground. A gate of NFET230is connected to the reset common node. A gate of NFET232is connected to the RESET_IN signal. The common drain connection of PFETs226,228provides a RESETN output. A series connected PFET234and NFET236is connected between the voltage supply VDD and ground having a common gate input of the RESET_IN signal. The common drain connection of PFET234and NFET236provides an inverted signal NRESET_IN signal.

Deactivate driver circuit200is also dynamic in nature and the RESET_IN signal acts as a clock in that through PFET224, when RESET_IN goes low, the reset common node is precharged to Vdd. Also, when RESET_IN goes low, the signals RESETN and NRESET_IN are pulled high and the reset common node is left to dynamically maintain its precharge state when RESET_IN goes high or be discharged through one of the four two-high NFET stacks made up of NFETs208,210;212,214;216,218; and220,222. A respective gate of NFETs208,212,216, and220is tied to PRECHARGE_READ0, PRECHARGE_WRITE0, PRECHARGE_WRITE1, PRECHARGE_READ01. Each of the gate inputs PRECHARGE_READ0, PRECHARGE_WRITE0, PRECHARGE_WRITE1, PRECHARGE_READ01is the common precharge port of an individual miscompare detector100as shown in FIG.1. As shown inFIGS. 3A and 3B, four miscompare detectors100are used with the deactivate driver circuit200. A gate input of NFETS210,218is connected to a CLKIR signal and a gate input of NFETS214,222is connected to a CLKIW signal.

The CLKIR and CLKIW signals are clocks that activate while RESET_IN is high. The combination of PFETs201,202, and NFET204form the keeper circuit common to dynamic circuits. While not necessary, PFETs201,202, and NFET204make the deactivate driver circuit200more robust in that while the dynamic node, RESET COMMON, is floating high, the keeper, specifically PFET201, will be weakly on and keep the dynamic node in a high state. When the reset common node discharges, then PFET201is shut off. Deactivate driver circuit200includes a saver PFET240coupled between the voltage supply VDD and the reset common node. Saver PFET240is a very small, weak PFET that is always on because its gate is tied to ground. Again, the saver PFET240is not necessary, but it also makes the deactivate driver circuit200robust in that PFET240helps keep the dynamic node high without providing much resistance when it is discharged. A reason for implementing this PFET240when there already is a keeper circuit is to insure that the dynamic reset common node always starts in a precharged state when the deactivate driver circuit200is powered on.

In the deactivate driver circuit200, there can be a variable number N of the 2-high NFET stacks. The number N depends on how many different addresses are being compared. In the example ofFIG. 2, there are two different addresses being compared. In other words in the example of the deactivate driver circuit200, there are two redundant wordlines available, Redundant Wordline0, and Redundant Wordline1. Each of the two redundant wordlines is able to replace a non-redundant wordline. The address of the redundant wordline is compare-detected in a miscompare detector100shown in FIG.1. Each redundant wordline can be compared for a read or a write operation. So for Redundant Wordline0, there is a read address compare and a write address compare; each requiring a separate implementation of the miscompare detector100of FIG.1. The same situation exists for Redundant Wordline1. Thus, there are four different NFET stacks made up of NFETs208,210;212,214;216,218; and220,222in the deactivate driver circuit200.

The RESETN signal output of PFETs226and228controls the WDEC for the non-redundant wordlines. If RESETN goes low, then this WDEC is enabled to select a wordline for access. If it remains high, the entire WDEC is disabled. Therefore, if the common precharge port of the four individual miscompare detectors100discharge, then the reset common node cannot discharge and, thus, the wordline being accessed is in the non-redundant wordlines. If one common precharge port of the miscompare detectors100does not discharge, then the reset common node discharges through the corresponding NFET stack. This keeps the RESETN output signal from dropping to disable the non-redundant wordlines.

The NRESET_IN signal is applied to a pair of redundant wordline drivers, as shown in FIG.3D. The NRESET_IN signal always tracks as the inverse of the RESET_IN signal and always enables the wordline drivers for the redundant wordlines when it drops. The redundant wordline drivers do not select their respective wordline for access, however; they are just enabled to do so. What is necessary is also the WL_driver signal from the respective miscompare detector100of FIG.1. This WL_DRIVER signal indicates, if it is high, that indeed a match has occurred and the non-redundant wordlines are being disabled. This WL_DRIVER signal also shows the match for the specific wordline and thus it can be used to select the redundant wordline replacing the non-redundant one.

As shown in FIG.3C and described with respect toFIG. 2, the PRECHARGE_WRITE0, PRECHARGE_READ0, PRECHARGE_WRITE1, and PRECHARGE_READ1signals from the respective miscompare detectors100ofFIGS. 3A and 3Bare applied to the deactivate driver circuit200. The clocks CLKIR, CLKWR and RESET_IN are applied to the deactivate driver circuit200and outputs NRESET_IN and RESETN are provided.

As shown inFIG. 4, each redundancy driver circuit400includes a write buffer formed by a first series connected PFET402and NFET404and a second series connected PFET406and NFET408connected between the voltage supply VDD and ground. A common gate connection of PFET402and NFET404is connected to the WRITE_REDUN signal. A common gate connection of PFET406and NFET408is connected to the common drain connection of PFET402and NFET404. A wordline driver output labeled FIRE_W is provided at the common drain connection of PFET406and NFET408. Each redundancy driver circuit400includes a read buffer formed by a first series connected PFET412and NFET414and a second series connected PFET416and NFET418connected between the voltage supply VDD and ground. A common gate connection of PFET412and NFET414is connected to the READ_REDUN signal. A common gate connection of PFET416and NFET418is connected to the common drain connection of PFET412and NFET414. A wordline driver output labeled FIRE_R is provided at the common drain connection of PFET416and NFET418.

Referring now toFIG. 5, there is a timing diagram illustrating operation of the exemplary redundancy circuit300ofFIGS. 3A,3B,3C, and3D in accordance with the preferred embodiment. Time is shown in nanoseconds for the illustrated graph of FIG.5. The illustrated waveforms include WL0, WL1, RWL1, the ACQUIRE and CLKOUT signals inFIG. 3A, NET corresponding to a NET node of the miscompare detector100ofFIG. 1, the PRECHARGE_READ1and the FIRE_READ1inFIG. 3B, the FIRE_R_1inFIG. 3D, the RESET_IN, NRESET_IN, CLKIR ofFIG. 3C, RESET_COMMON corresponding to the reset common node of the deactivate driver circuit200ofFIG. 2, and a RESET signal described below. Between 50 nsec and 70 nsec, there is a match between the fuse address and the address being read as indicated at a line RWL1. In this case, the redundant wordline should be selected. When ACQUIRE goes high and CLKOUT goes low, PRECHARGE_READ1goes high. When CLKOUT goes high, PRECHARGE_READ1stay high because the address match. This causes FIRE_READ1and thus FIRE_R_1to remain high. Also, since PRECHARGE_READ1is high, when CLKIR turns on, RESET_COMMON is caused to fall to zero. This causes RESET to go high. RESET stays high when RESET_IN drops, however RESET_IN dropping causes the RESET_COMMON node to return to Vdd. RESET stays high until RESET_IN returns to Vdd.

Three important signals are RESET, NRESET_IN, and FIRE_R_1. RESET disables all of the non-redundant wordline drivers when it is at Vdd. To implement this, one skilled in the art would be able to take RESET, invert it, and then AND it with a particular signal that would otherwise drive the wordline if redundancy were not being implemented.

In this specific illustrated implementation300and as shown inFIG. 5, the wordline driver will activate when CLKIR rises. It will not deactivate until RESET drops. In non-redundancy operation, RESET rises after CLKIR has risen. However, if RESET is already high, as in redundancy operation, the wordline drivers stay deactivated even when CLKIR rises. The other two signals, NRESET_IN and FIRE_R_1, are applied to the redundant wordline drivers.

FIG. 6illustrates a wordline driver or selector circuit for selecting a wordline to be accessed generally designated by the reference character600of the preferred embodiment. Wordline selector circuit600is dynamic in nature. Also, the illustrated wordline selector circuit600has separate parts for Read and Write operations as designated by the R and W after the signal names. This is necessary if there are different address buses for reads and writes that are available during the same cycle; that is, a read and a write can occur in the same cycle and can be to different addresses. If this is the case, then there will be separate comparisons for each address and thus different select signals.

Wordline selector circuit600includes a respective precharge PFET602,604coupled between the voltage supply VDD and a respective one of dynamic nodes DYN_W, DYN_R. A PFET606and an NFET608are connected in series between the voltage supply VDD and ground. The NRESET_IN signal is applied to a common gate input of PFET606and NFET608.

A stack of NFETs610,612,614is coupled between dynamic node DYN_W and ground. A stack of NFETs616,618,620is coupled between dynamic node DYN_R and ground. The common drain connection of PFET606and NFET608is connected to the gate of the precharge PFETs602,604, and to a gate input of discharge NFETs614,620. The CLKIW signal is applied to the gate of NFET610and the CLKIR signal is applied to the gate of NFET616. The FIRE_W signal is applied to the gate of NFET612and the FIRE_R signal is applied to the gate of NFET618.

A respective saver PFET622,624coupled between the voltage supply VDD and the respective one of dynamic nodes DYN_W, DYN_R. Saver PFETs622,624are very small, weak PFETs that are always on with their gates tied to ground insures that the dynamic nodes DYN_W, DYN_R start in a precharged state when the wordline selector circuit600is powered on.

Wordline selector circuit600includes a respective PFET626,628coupled between the voltage supply VDD and the respective one of dynamic nodes DYN_W, DYN_R. A respective PFET630,632has a source connected to the voltage supply VDD, and a gate input coupled to the respective one of dynamic nodes DYN_W, DYN_R. A series connected pair of NFETs634,636are connected between a common drain connection of PFETs630,632and ground. A gate of NFET634is connected to the dynamic node DYN_W. A gate of NFET636is connected to the dynamic node DYN_R. The common drain connection of PFETs630,632provides a wordline select signal WL. PFET626,628have a common gate connection to the wordline select signal WL.

Wordline selector circuit600is clocked by the NRESET_IN signal. NRESET_IN precharges the nodes DYN_W and DYN_R when NRESET_IN goes high and enables the nodes DYNW and DYNR to discharge when it is low. Clocks CLKIR and CLKIW are necessary because they designate when the Read and the Write actually occur. The FIRE_R and FIRE_W, buffered/renamed signals analogous to FIRE_R_1inFIG. 5, indicate that an address match has occurred between the address being accessed and the fuse address or redundant address.

When three conditions are met, NRESET_IN low, CLKIR or CLKIW high, and FIRE_R or FIRE_W high, then DYN_W or DYN_R will discharge and thus the output WL will go high. WL selects the wordline to be accessed.