Computer system and method for automatically overclocking based upon a signal standard and an I/O signal of overclocking element

A computer system for automatically overclocking includes an overclocking element, a detecting circuit and a basic input/output system (BIOS). The overclocking element has a signal standard. The detecting circuit is used for acquiring an I/O signal of the overclocking element. The BIOS is used for comparing the signal standard with the I/O signal to obtain a comparing result. The BIOS is further used for adjusting a reference signal according to the comparing result. The reference signal is an input signal of the overclocking element.

This application claims the benefit of Taiwan application Serial No. 97113384, filed Apr. 11, 2008, the subject matter of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a computer system and a method for automatically overclocking and, more particularly, to a computer system and a method for automatically overclocking utilizing a hard device.

2. Description of the Related Art

Manufacturers usually set a standard operating range for electronic components when the electronic components leave factories. Overclocking is a technique for improving clock speed of the electronic components and makes operating range of the electronic components above the standard operating range set by the manufacturers. For example, users can overclock a central processing unit (CPU) chipset from a standard operating range 2 GHz to 2.1 GHz. Therefore, overclocking improves the efficiency of the cheap electronic components close to the efficiency of the expensive electronic components to make the users feel the electronic components well worth the cost. Furthermore, the efficiency of computer system can be improved as the operating range of the electronic components is enlarged. Therefore, many users expect to overclock the electronic components to the best operating range to make the computer system achieve the best efficiency.

In conventional overclocking method, users need to make the computer system access into a basic input/output system (BIOS) during booting to self adjust related setup parameters. When users adjust the setup parameters to be ones that make the system crash, the BIOS will record the setup parameters before the system crashes. The computer system will operate according to the setup parameters when users reboot the computer system. Therefore, users can adjust the setup parameters again according to the setup parameters recorded in the BIOS. In this way, the setup parameters can be adjusted to the optimization by continuous trial and error. However, using the method depends on long-term accumulated experience of users and is very difficult for users who are unfamiliar with the computer system.

As a result, the industry develops overclocking software currently. The overclocking software increases frequency and tests stability of the computer system successively. If the computer system is stable after the frequency is increased, the overclocking software will increase frequency again and reboot the computer system. If the computer system crashes, an automatic recovery mechanism (for example, a watchdog timer is used for detecting whether timeout occurs, the occurrence of timeout means that the system crashes) will send a signal to the computer system to reboot the computer system and read the setup parameters before the system crashes. The overclocking software regards the setup parameters as the best parameters to accomplish automatic overclocking. However, in the method, the computer system has to crash at least once to achieve the best overclocking settings.

BRIEF SUMMARY OF THE INVENTION

The invention is related to a computer system and a method for automatically overclocking. In the method, a reference signal is adjusted according to a comparing result resulting from comparing a signal standard of an overclocking element with an I/O signal.

According to an aspect of the invention, a computer system for automatically overclocking is provided. The computer system includes an overclocking element, a detecting circuit and a BIOS. The overclocking element has a signal standard. The detecting circuit is used for acquiring an I/O signal of the overclocking element. The BIOS is used for comparing the signal standard with the I/O signal to obtain a comparing result. The BIOS is further used for adjusting a reference signal according to the comparing result. The reference signal is an input signal of the overclocking element.

According to another aspect of the invention, a method for automatically overclocking is provided. The method includes steps as below. A signal standard of an overclocking element is provided. An I/O signal of the overclocking element is acquired. The signal standard is compared with the I/O signal to get a comparing result, and a reference signal is adjusted according to the comparing result. The reference signal is an input signal of the overclocking element.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The invention relates to a computer system for automatically overclocking including an overclocking element, a detecting circuit and a BIOS. The overclocking element has a signal standard. The detecting circuit is used for acquiring an I/O signal of the overclocking element. The BIOS is used for comparing the signal standard with the I/O signal to obtain a comparing result. The BIOS is further used for adjusting a reference signal according to the comparing result. The reference signal is an input signal of the overclocking element. Embodiments will be illustrated in detail as follows.

FIG. 1is a block diagram showing a computer system for automatically overclocking according to a first embodiment of the invention. The computer system100for automatically overclocking has an AMD architecture. The computer system100includes a detecting circuit110and a BIOS120, a dynamic random access memory (DRAM)130, a chipset140, a CPU150and a clock generator160. The CPU150is coupled to the chipset140and the DRAM130, respectively.

In the embodiment, the DRAM130is an overclocking element and has a signal standard. The signal standard includes a rated setup time tDS2and a rated hold time tDH2of an I/O signal Ds of the DRAM130. The I/O signal Ds is a signal transmitted to the CPU150from the DRAM130or a signal received by the DRAM130from the CPU150.

The rated setup time tDS2and the rated hold time tDH2are the minimal setup time and hold time of the I/O signal Ds in the computer system100when the I/O signal Ds can be read correctly. Furthermore, the signal standard is corresponding to the I/O signal Ds. If the I/O signal Ds is a signal transmitted to the CPU150from the DRAM130, the rated setup time tDS2and the rated hold time tDH2recorded in the signal standard are the minimal setup time and hold time when the signal transmitted from the DRAM130can be read normally. Furthermore, if the I/O signal Ds is a signal received by the DRAM130from the CPU150, the rated setup time tDS2and the rated hold time tDH2recorded in the signal standard are the minimal setup time and hold time when the signal received by the DRAM130can be read normally.

The I/O signal Ds of the DRAM130is generated according to a reference signal Rs. The detecting circuit110is used for acquiring an I/O signal Ds of the DRAM130. In the embodiment, the detecting circuit110is a phase detecting circuit and is used for getting a phase difference according to the reference signal Rs and the I/O signal Ds. Furthermore, the detecting circuit110preferably includes a register112for storing the phase difference. The BIOS120is used for reading the phase difference from the register112of the detecting circuit110and works out an I/O setup time tDS1and an I/O hold time tDH1of the I/O signal Ds according to the phase difference.

The BIOS120compares the I/O setup time tDS1with the rated setup time tDS2and compares the I/O hold time tDH1with the rated hold time tDH2to obtain a comparing result. The BIOS120further adjusts the reference signal Rs according to the comparing result. In this case, the BIOS120controls the frequency of reference clock Rs according to the rated setup time tDS2, the rated hold time tDH2, the I/O setup time tDS1and the I/O hold time tDH1. Thereby, increasing frequency of data transmission from the DRAM130to the CPU150successively or increasing frequency of data transmission from the CPU150to the DRAM130successively can overclock the computer system100to the optimum state.

Preferably, the BIOS120adjusts the reference signal Rs next time according to the difference between the last rated setup time tDS2and the last I/O setup time tDS1, and the difference between the last rated hold time tDH2and the last I/O hold time tDH1. In this case, the BIOS120can adjust the reference signal Rs to make the I/O setup time tDS1close to the rated setup time tDS2but not less than the rated setup time tDS2. The BIOS120can also make the I/O hold time tDH1close to the rated hold time tDH2but not less than the rated hold time tDH2. In this way, the frequency of the reference signal Rs can be maximized. Meanwhile, the computer system100may finish overclocking without crash caused by failure of reading the I/O signal Ds correctly.

In general, the system crash often occurs when the I/O setup time tDS1and the I/O hold time tDH1of the I/O signal Ds are too small to be read. The computer system100will not crash so long as the I/O setup time tDS1and the I/O hold time tDH1of the I/O signal Ds are greater than the rated setup time tDS2and the rated hold time tDH2. In the embodiment, the reference signal Rs is adjusted to make the I/O setup time tDS1and the I/O hold time tDH1of the I/O signal Ds closest to the rated setup time tDS2and the rated hold time tDH2to maximize the frequency of the reference signal Rs as well as overclock the overclocking element to the optimal range. Meanwhile, computer system100is in a stable state without crash.

Furthermore, in the embodiment, the BIOS120includes a register122for storing a table recording the rated setup time tDS2and the rated hold time tDH2. Besides, the BIOS120transmits a control signal Cs to the clock generator160. The clock generator160outputs the reference signal Rs according to the control signal Cs to adjust the reference signal Rs. The control signal Cs is, for example, a clock control signal having successive multiple pulses.

In the embodiment, although the control signal Cs output by the clock generator160is the clock control signal which is taken as an example herein, the invention is not limited thereto. In another embodiment, the control signal Cs output by the clock generator160is a strobe control signal. The strobe control signal makes the reference signal Rs have pulses only when the I/O signal Ds needs to be acquired. Thereby, power consumed by the reference signal Rs in level conversion can be saved.

FIG. 2is a timing diagram according to a first embodiment. As shown inFIG. 2, signals of pin DQ and pin DQS of a memory DDR3-800 produced by SAMSUNG are taken as an example. The signal of the pin DQS is the reference signal Rs and the signal of the DQ is the I/O signal Ds. The signal of the DQS has rising edges at the time point t1and the time point t2, respectively. The I/O setup time tDS1of the I/O signal Ds is a time span from the time point t1to the level conversion before the time point t1, namely the time span |t0-t1|. The I/O hold time tDH1of the I/O signal Ds is a time span from the time point t2to the level conversion after the time point t2, namely the time span |t2-t3|. The rated setup time tDS2and the rated hold time tDH2are recorded in a data sheet provided by a manufacturer. The rated setup time tDS2is 250 picoseconds, and the rated hold time tDH2is 250 picoseconds. As a result, the signal of the pin DQ can be read normally when the I/O setup time tDS1and the I/O hold time tDH1of the signal of the pin DQ are greater than 250 picoseconds.

In the embodiment, the computer system100adopts an AMD architecture formed by the CPU150, the chipset140and the DRAM130coupled with the CPU150, respectively. The DRAM130may be an overclocking element, however, the invention is not limited thereto. In another embodiment, the computer system adopts an Intel architecture, and the chipset is respectively coupled with the CPU and the DRAM which is the overclocking element. The I/O signal is the signal transmitted to the chipset from the DRAM or the signal received by the DRAM from the chipset. The reference signal is the input signal of the DRAM.

Furthermore, the overclocking element also can be the CPU in the INTEL architecture. As shown inFIG. 3, it is a block diagram showing the computer system for automatically overclocking according to another embodiment of the invention. The difference between the computer system300in the embodiment and the computer system is that the chipset340of the computer system300for automatically overclocking is respectively coupled with the DRAM330and the CPU350. The I/O signal Ds is the signal transmitted to the chipset340from the CPU350or the signal received by the CPU350from the chipset340. The BIOS320compares the I/O signal Ds with the corresponding signal standard to get a comparing result for adjusting the reference signal Rs hereby. The reference signal Rs is the input signal of the CPU350. The parts which are the same with that of the computer system100are not described for concise purpose.

Besides, the overclocking element can also be the chipset. The I/O signal Ds is the signal transmitted to the CPU from the chipset or the signal received by the chipset from the CPU. The BIOS compares the I/O signal with the corresponding signal standard to get a comparing result for adjusting the reference signal hereby. The reference signal is the input signal of the chipset.

FIG. 4is a flow diagram of the method for automatically overclocking according to the embodiment of the invention. The steps of the method for automatically overclocking of the embodiment inFIG. 4are performed by the computer system100, but the invention is not limited thereto. Persons having ordinary skills in the art should understand the steps and sequences of the method for automatically overclocking and make various modifications and changes according to actual application status.

First, as shown in the step S410, the signal standard of the overclocking element (the DRAM130) is provided. In the embodiment, the signal standard includes the rated setup time tDS2and rated hold time tDH2of the I/O signal Ds of the DRAM130.

Second, as shown in the step S420, the I/O signal Ds of the overclocking element (the DRAM130) is acquired. The I/O signal Ds is the signal transmitted to the CPU150from the DRAM130or the signal transmitted to the DRAM130from the CPU150.

Third, as shown in the step S430, the phase difference is obtained through detecting the reference signal Rs and the I/O signal Ds by the phase detecting circuit110.

Fourth, as shown in the step S440, an I/O setup time tDS1and an I/O hold time tDH1of the I/O signal Ds are worked out by the BIOS120according to the phase difference. A comparing result is obtained by comparing the I/O setup time tDS1with the rated setup time tDS2and comparing the I/O hold time tDH1with the rated hold time tDH2.

Fifth, as shown in the step S450, the reference signal Rs is adjusted according to the comparing result. The reference signal Rs is the input signal of the overclocking element (DRAM130).

The method for automatically overclocking can be performed repeatedly to make the I/O setup time tDS1close to the rated setup time tDS2but not less than the rated setup time tDS2, and make the I/O hold time tDH1close to the rated hold time tDH2but not less than the rated hold time tDH2. In this way, the reference signal Rs can be overclocked to the best range to accomplish overclocking automatically.

In the computer system and method disclosed in the above embodiments of the invention, whether the I/O setup time and the I/O hold time of the I/O signal conform to the established rated setup time and the rated hold time is determined to adjust the frequency of the reference signal. The basis of adjusting reference signal is the difference between the rated setup time and the I/O setup time. The difference can also be between the rated hold time and the I/O hold time. In this way, the frequency of the reference signal can be added successively, to make the I/O setup time close to the rated setup time but not less than the rated setup time, and make the I/O hold time close to the rated hold time but not less than the rated hold time. In this way, the computer system can be automatically overclocked to the optimum state without the system crash. Thereby, it can further improve the efficiency of the computer system to make the users feel the computer system well worth the cost.