Method, apparatus, system for early page granular hints from a PCIe device

Aspects of the embodiments are directed to systems and methods for providing and using hints in data packets to perform memory transaction optimization processes prior to receiving one or more data packets that rely on memory transactions. The systems and methods can include receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

BACKGROUND

Modern server and client processing units can support a wide number of core & input/output (I/O) agents. Each core and I/O agent can vie for low latency and high bandwidth access to shared resources to achieve better performance characteristics. Such shared resources can include cache memory and storage.

The figures may not be drawn to scale Like reference numbers denote like elements across the different figures.

DETAILED DESCRIPTION

Although the following embodiments may be described with reference to energy conservation and energy efficiency in specific integrated circuits, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™. And may be also used in other devices, such as handheld devices, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency.

Referring toFIG. 1, an embodiment of a block diagram for a computing system including a multicore processor is depicted. Processor100includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SOC), or other device to execute code. Processor100, in one embodiment, includes at least two cores—core101and102, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor100may include any number of processing elements that may be symmetric or asymmetric.

Physical processor100, as illustrated inFIG. 1, includes two cores—core101and102. Here, core101and102are considered symmetric cores, i.e. cores with the same configurations, functional units, and/or logic. In another embodiment, core101includes an out-of-order processor core, while core102includes an in-order processor core. However, cores101and102may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a translated Instruction Set Architecture (ISA), a co-designed core, or other known core. In a heterogeneous core environment (i.e. asymmetric cores), some form of translation, such a binary translation, may be utilized to schedule or execute code on one or both cores. Yet to further the discussion, the functional units illustrated in core101are described in further detail below, as the units in core102operate in a similar manner in the depicted embodiment.

As depicted, core101includes two hardware threads101aand101b, which may also be referred to as hardware thread slots101aand101b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor100as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers101a, a second thread is associated with architecture state registers101b, a third thread may be associated with architecture state registers102a, and a fourth thread may be associated with architecture state registers102b. Here, each of the architecture state registers (101a,101b,102a, and102b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers101aare replicated in architecture state registers101b, so individual architecture states/contexts are capable of being stored for logical processor101aand logical processor101b. In core101, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block130may also be replicated for threads101aand101b. Some resources, such as re-order buffers in reorder/retirement unit135, ILTB120, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB115, execution unit(s)140, and portions of out-of-order unit135are potentially fully shared.

Processor100often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. InFIG. 1, an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core101includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer120to predict branches to be executed/taken and an instruction-translation buffer (I-TLB)120to store address translation entries for instructions.

Core101further includes decode module125coupled to fetch unit120to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots101a,101b, respectively. Usually core101is associated with a first ISA, which defines/specifies instructions executable on processor100. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic125includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below decoders125, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders125, the architecture or core101takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note decoders126, in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders126recognize a second ISA (either a subset of the first ISA or a distinct ISA).

In one example, allocator and renamer block130includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads101aand101bare potentially capable of out-of-order execution, where allocator and renamer block130also reserves other resources, such as reorder buffers to track instruction results. Unit130may also include a register renamer to rename program/instruction reference registers to other registers internal to processor100. Reorder/retirement unit135includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

Here, cores101and102share access to higher-level or further-out cache, such as a second level cache associated with on-chip interface110. Note that higher-level or further-out refers to cache levels increasing or getting further way from the execution unit(s). In one embodiment, higher-level cache is a last-level data cache—last cache in the memory hierarchy on processor100—such as a second or third level data cache. However, higher level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder125to store recently decoded traces. Here, an instruction potentially refers to a macro-instruction (i.e. a general instruction recognized by the decoders), which may decode into a number of micro-instructions (micro-operations).

In the depicted configuration, processor100also includes on-chip interface module110. Historically, a memory controller, which is described in more detail below, has been included in a computing system external to processor100. In this scenario, on-chip interface11is to communicate with devices external to processor100, such as system memory175, a chipset (often including a memory controller hub to connect to memory175and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus105may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

Memory175may be dedicated to processor100or shared with other devices in a system. Common examples of types of memory175include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Device180may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.

Recently however, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor100. For example in one embodiment, a memory controller hub is on the same package and/or die with processor100. Here, a portion of the core (an on-core portion)110includes one or more controller(s) for interfacing with other devices such as memory175or a graphics device180. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, on-chip interface110includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link105for off-chip communication. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory175, graphics processor180, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.

In one embodiment, processor100is capable of executing a compiler, optimization, and/or translator code177to compile, translate, and/or optimize application code176to support the apparatus and methods described herein or to interface therewith. A compiler often includes a program or set of programs to translate source text/code into target text/code. Usually, compilation of program/application code with a compiler is done in multiple phases and passes to transform hi-level programming language code into low-level machine or assembly language code. Yet, single pass compilers may still be utilized for simple compilation. A compiler may utilize any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

Larger compilers often include multiple phases, but most often these phases are included within two general phases: (1) a front-end, i.e. generally where syntactic processing, semantic processing, and some transformation/optimization may take place, and (2) a back-end, i.e. generally where analysis, transformations, optimizations, and code generation takes place. Some compilers refer to a middle, which illustrates the blurring of delineation between a front-end and back end of a compiler. As a result, reference to insertion, association, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes, as well as any other known phases or passes of a compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, etc. in one or more phases of compilation, such as insertion of calls/operations in a front-end phase of compilation and then transformation of the calls/operations into lower-level code during a transformation phase. Note that during dynamic compilation, compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution during runtime. As a specific illustrative example, binary code (already compiled code) may be dynamically optimized during runtime. Here, the program code may include the dynamic optimization code, the binary code, or a combination thereof.

Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and/or translate code. Therefore, reference to execution of code, application code, program code, or other software environment may refer to: (1) execution of a compiler program(s), optimization code optimizer, or translator either dynamically or statically, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (2) execution of main program code including operations/calls, such as application code that has been optimized/compiled; (3) execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software related operations, or to optimize code; or (4) a combination thereof.

Shared processor core fabrics attempt to balance traffic from I/O agents and rely on various techniques to optimize these competing accesses. To improve core performance, the fabric utilizes various methods including cache prefetch, differentiated caching policy, and memory bandwidth utilization optimizations, each of which may be based on predicting future core accesses based on current traffic pattern.

Hardware prefetch engines can help determine patterns and prefetch into a dedicated or a shared cache (mid-level cache or L2 cache or last level cache (LLC) prefetch). A hint or indication from the core itself on the traffic type can be used to aid in balancing competition for shared resources. Examples of such hints from the core include Dead Block Predictor, Non-Temporal hints, etc.

Characterizing I/O traffic into predictable patterns can be difficult because I/O traffic tends to have a wide variance depending on the type of device, application, and platform. I/O traffic also tends to not have non-uniform memory access (NUMA) affinity due to I/O and platform connectivity limitations. Thus, a hardware prefetch engine may suffer from inefficiency for I/O traffic. Also, unlike the core, I/O devices do not have a standard mechanism to send hints to the fabric to optimize for different traffic types. As a result, traditional methods for optimizing cache and memory bandwidth latency for cores have not been widely applicable to I/O.

This disclosure describes systems, methods, and devices to allow for I/O devices to send advance notice to the root complex on the nature of traffic that is about to be sourced from the device. The root complex can then use this information to make various decisions and optimizations about the traffic that it is expecting to receive. A PCIe connected device can provide a “hint” to the processor core as to the nature of the traffic that will be sources by the device. The processor core can use the hint to streamline the device's transaction with the shared resource.

FIG. 2is a schematic diagram of a system architecture200in accordance with embodiments of the present disclosure. The system architecture200can include a host system201and a plurality of devices220a-cconnected to the host system201through a PCIe-compliant switch fabric230. The system architecture200can include one or more processors202. The processors202can be coupled to the root complex by a link, such as a front-side bus. The processors202can include cache memory204. The cache memory204can temporarily store data from storage206.

The host system201can also include a root complex210. Root complex210can act as a controller hub for PCIe-compliant systems and devices. The root complex210connects the processor202and storage206to the PCIe-complaint switch fabric230composed of one or more switch devices. The root complex210also connects devices220a-cto the host system201through the switch fabric230.

In embodiments, the devices220a-ccan compete for processing and memory resources hosted by the host system201. The devices220a-ccan leverage existing PCIe packet architecture to transmit hints, or advanced information, to the root complex210to allow the root complex to perform certain optimization processes prior to receiving further data packets from the devices220a-c. The devices220a-ccan access the host system201for memory reads, writes, streaming writes, cacheable operations, atomic operations, partial operations, Data Direct I/O, etc. Other use cases include caching policy determination (including cache prefetch), page initialization, and security policy setup, as well as other processes. The PCIe-compliant packet architecture is shown in more detail inFIG. 3.

FIG. 3is an example PCIe-compliant data packet300in accordance with embodiments of the present disclosure. By using the data packet300to transmit a hint, the device exposes to the root complex the pages it intends to access in advance.

The example packet300shown inFIG. 3is an Address Translation Services (ATS) packet. ATS packets allow a device to send a Virtual Address (VA)/Guest Physical Address (GPA) to Host Physical Address (HPA) translation request to the root complex on a page granularity in advance of the actual memory access request (e.g., DMA request). The ATS packet is particularly useful for providing hints about future memory accesses by the device because the ATS packet is transmitted prior to data read/writes. Other types of data packets can be transmitted to achieve similar results. For example, a zero length write can be used for the processing hint bits by using unused or reserved bits in the zero length write data packet.

The data packet300can include reserved bits at various double words of the packet. The reserved bits can be leveraged to include hints of the memory accesses that the device intends to perform. Table 1 provides an example of how reserved bits and unused bits can be used to provide hints to the root complex.

Relating Table 1 toFIG. 3, the Transaction Hint (TH) bit304occupies DW 0, Byte 1, Bit0of the data packet300. The TH bit304can be used to signify to the root complex that the data packet carries a hint about an upcoming memory access. Hint bits302can DW 3, Byte 3, Bits [2:1]. For ATS packets, the hint bits302occupy bits that were formerly reserved.

Similarly, for a Zero Length Write, as defined in Table 1, the lower address bits, which are unused, are being used to provide the same hints as a Translation Request.

Hint bits302are used to convey the intended usage from the device's perspective. The hints bits302are optional and are enabled when the device sets the Transaction Hint (TH) bit304. Other reserved bits (e.g., reserved bits306) can be used to provide sub-page granularity. (Noteworthy is that even when hints are enabled, hints may be ignored by the root complex.)

FIG. 4is a process flow diagram400for a device to configure a data packet with hint bits in accordance with embodiments of the present disclosure. The device can determine an imminent memory transaction (402). The memory transaction can be a memory read or write, or other type of memory transaction. The determination of the imminent memory transaction can be to a certain page in memory that the device intends to access. The imminence of the memory transaction can include a memory transaction that will occur for the data stream the device is processing. The device can program a data packet that is to be sent to a root complex of a host system with a transaction hint (TH) bit (404). The TH bit can occupy a reserved bit of the data packet or a first portion of a reserved bit field of the data packet. For example, in an ATS packet, the TH bit can occupy DW0.byte 1.bit0, where DW0.byte 1.bits [1:0] are reserved bits. The device can program the data packet with processing hint bits (and in some embodiments, can set sub-page granularity bits) indicating the nature of the imminent memory transaction (406). The processing hint bits can occupy one or more reserved bits of the data packet. For example, processing hint bits can include 2 bits and can occupy DW3.byte 3.bits [2:1]. The encodings for the hint bits can be as follows:

Other reserved bits can also be used to provide sub-page granularity. For example, eight bits (DW3, Byte 3, Bits [7:3] and DW3, Byte 2, Bits [2:0]) are used to provide sub-page granularity. Thus, for a 4 KB page, these 8 bits provide a one-hot vector which then gives a 512B granularity for the hints. The processing hint bits can indicate a page granularity of the memory address space that will be accessed. Within a large page, the processing hints can pertain to a subset range of a page of the memory address space that will be accessed.

The device can then transmit the packet to the root complex (408).

FIG. 5is a process flow diagram500for a root complex to process a received data packet in accordance with embodiments of the present disclosure. The root complex can receive a data packet from a device from across a PCIe-compliant link (502). The root complex can determine that a transaction hint bit is set in a first portion of a reserved bit field of the received data packet (504). For example, the root complex can identify a TH bit set in a reserved bit field. The presence of a set bit in a specified bit or bit field can trigger the root complex to examiner other predetermined reserved portions of the received data packet. For example, the presence of a set bit in a predefined bit location can cause the root complex to identify a hint bit set in another predefined bit location of the data packet (506). The root complex can identify, from the hint bits, an optimization process to perform to prepare for an imminent memory transaction for the device (508).

When the root complex identifies advance information about how a device intends to use a given address range or page in memory, it can make various optimizations in a CPU-specific manner. Some examples of these optimizations are given below but this is not a comprehensive list.

Caching Behavior

There can be various caching optimizations that the root complex may choose to enable depending on the type of device and kind of hint received in the data packet. For example, the root complex may choose to prefetch ownership in response to receiving a hint for “Streaming Writes.” In embodiments, the root complex can prefetch and cache data in response to a hint for “Reads.” In embodiments, the root complex can prefetch ownership and data for “Atomics/Partial” or “Cacheable operations.”

Apart from prefetch, depending on type of device, the root complex may choose to make optimizations regarding cache allocation and replacement policies. For example, the root complex may choose to not enable DDIO for Streaming Writes (which causes cache thrash) or the root complex may choose a differentiated replacement policy in other cases (using a lower/higher LRU value).

Metadata Update & Page Initialization

Depending on the hint received in the received data packet, the root complex may choose to initialize a given page with specific characteristics. This initialization may include updating metadata stored with the page in memory. The metadata update may provide additional capabilities such as setting up security regions for the device.

The root complex can then receive a data packet for the memory transaction (510) and process the memory transaction using the optimization processes performed from the hint (512).

One interconnect fabric architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices. PCIe is a high performance, general purpose I/O interconnect protocol defined for a wide variety of future computing and communication platforms. Some PCI attributes, such as its usage model, load-store architecture, and software interfaces, have been maintained through its revisions, whereas previous parallel bus implementations have been replaced by a highly scalable, fully serial interface. The more recent versions of PCI Express take advantage of advances in point-to-point interconnects, Switch-based technology, and packetized protocol to deliver new levels of performance and features. Power Management, Quality Of Service (QoS), Hot-Plug/Hot-Swap support, Data Integrity, and Error Handling are among some of the advanced features supported by PCI Express.

Referring toFIG. 6, an embodiment of a fabric composed of point-to-point links that interconnect a set of components is illustrated. System600includes processor605and system memory610coupled to controller hub615. Processor605includes any processing element, such as a microprocessor, a host processor, an embedded processor, a co-processor, or other processor. Processor605is coupled to controller hub615through front-side bus (FSB)606. In one embodiment, FSB606is a serial point-to-point interconnect as described below. In another embodiment, link606includes a serial, differential interconnect architecture that is compliant with different interconnect standard.

System memory610includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system600. System memory610is coupled to controller hub615through memory interface616. Examples of a memory interface include a double-data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

In one embodiment, controller hub615is a root hub, root complex, or root controller in a Peripheral Component Interconnect Express (PCIe) interconnection hierarchy. Examples of controller hub615include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH) a southbridge, and a root controller/hub. Often the term chipset refers to two physically separate controller hubs, i.e. a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include the MCH integrated with processor605, while controller615is to communicate with I/O devices, in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported through root complex615.

The root complex615can receive a data packet from a connected device, such as an I/O device625. The data packet can include a hint bit set, which prompts the root complex to evaluate one or more reserved bits to determine whether a hint bit is present in the data packet. The hint bit can provide a hint or advanced information to the root complex about how the I/O device625intends on using an identified address range or page in memory. The root complex615can perform various optimizations on behalf of a processor core, as described above.

Here, controller hub615is coupled to switch/bridge620through serial link619. Input/output modules617and621, which may also be referred to as interfaces/ports617and621, include/implement a layered protocol stack to provide communication between controller hub615and switch620. In one embodiment, multiple devices are capable of being coupled to switch620.

Switch/bridge620routes packets/messages from device625upstream, i.e. up a hierarchy towards a root complex (e.g., controller hub615) and downstream, i.e. down a hierarchy away from a root controller, from processor605or system memory610to device625.

Switch620, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Device625includes any internal or external device or component to be coupled to an electronic system, such as an I/O device, a Network Interface Controller (NIC), an add-in card, an audio processor, a network processor, a hard-drive, a storage device, a CD/DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, and other input/output devices. Often in the PCIe vernacular, such as device, is referred to as an endpoint. Although not specifically shown, device625may include a PCIe to PCI/PCI-X bridge to support legacy or other version PCI devices. Endpoint devices in PCIe are often classified as legacy, PCIe, or root complex integrated endpoints. The device625can be coupled to the switch620by a serial link623.

Graphics accelerator630is also coupled to controller hub615through serial link632. In one embodiment, graphics accelerator630is coupled to an MCH, which is coupled to an ICH. Switch620, and accordingly I/O device625, is then coupled to the ICH. I/O modules631and618are also to implement a layered protocol stack to communicate between graphics accelerator630and controller hub615. Similar to the MCH discussion above, a graphics controller or the graphics accelerator630itself may be integrated in processor605.

Turning toFIG. 7an embodiment of a layered protocol stack is illustrated. Layered protocol stack700includes any form of a layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or other layered stack. Although the discussion immediately below in reference toFIGS. 6-12are in relation to a PCIe stack, the same concepts may be applied to other interconnect stacks. In one embodiment, protocol stack700is a PCIe protocol stack including transaction layer705, link layer710, and physical layer720. An interface, such as interfaces617,618,621,622,626, and631inFIG. 6, may be represented as communication protocol stack700. Representation as a communication protocol stack may also be referred to as a module or interface implementing/including a protocol stack.

PCI Express uses packets to communicate information between components. Packets are formed in the Transaction Layer705and Data Link Layer710to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side the reverse process occurs and packets get transformed from their Physical Layer720representation to the Data Link Layer710representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer705of the receiving device.

Transaction Layer

In one embodiment, transaction layer705is to provide an interface between a device's processing core and the interconnect architecture, such as data link layer710and physical layer720. In this regard, a primary responsibility of the transaction layer705is the assembly and disassembly of packets (i.e., transaction layer packets, or TLPs). The translation layer705typically manages credit-base flow control for TLPs. PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response.

In addition PCIe utilizes credit-based flow control. In this scheme, a device advertises an initial amount of credit for each of the receive buffers in Transaction Layer705. An external device at the opposite end of the link, such as controller hub115inFIG. 1, counts the number of credits consumed by each TLP. A transaction may be transmitted if the transaction does not exceed a credit limit. Upon receiving a response an amount of credit is restored. An advantage of a credit scheme is that the latency of credit return does not affect performance, provided that the credit limit is not encountered.

In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as 64-bit address. Configuration space transactions are used to access configuration space of the PCIe devices. Transactions to the configuration space include read requests and write requests. Message space transactions (or, simply messages) are defined to support in-band communication between PCIe agents.

Therefore, in one embodiment, transaction layer705assembles packet header/payload706. Format for current packet headers/payloads may be found in the PCIe specification at the PCIe specification website.

Quickly referring toFIG. 8, an embodiment of a PCIe transaction descriptor is illustrated. In one embodiment, transaction descriptor800is a mechanism for carrying transaction information. In this regard, transaction descriptor800supports identification of transactions in a system. Other potential uses include tracking modifications of default transaction ordering and association of transaction with channels.

Transaction descriptor800includes global identifier field802, attributes field1004and channel identifier field806. In the illustrated example, global identifier field802is depicted comprising local transaction identifier field808and source identifier field810. In one embodiment, global transaction identifier802is unique for all outstanding requests.

According to one implementation, local transaction identifier field808is a field generated by a requesting agent, and it is unique for all outstanding requests that require a completion for that requesting agent. Furthermore, in this example, source identifier810uniquely identifies the requestor agent within a PCIe hierarchy. Accordingly, together with source ID810, local transaction identifier808field provides global identification of a transaction within a hierarchy domain.

Attributes field804specifies characteristics and relationships of the transaction. In this regard, attributes field804is potentially used to provide additional information that allows modification of the default handling of transactions. In one embodiment, attributes field804includes priority field812, reserved field814, ordering field816, and no-snoop field818. Here, priority sub-field812may be modified by an initiator to assign a priority to the transaction. Reserved attribute field814is left reserved for future, or vendor-defined usage. Possible usage models using priority or security attributes may be implemented using the reserved attribute field.

In this example, ordering attribute field816is used to supply optional information conveying the type of ordering that may modify default ordering rules. According to one example implementation, an ordering attribute of “0” denotes default ordering rules are to apply, wherein an ordering attribute of “1” denotes relaxed ordering, wherein writes can pass writes in the same direction, and read completions can pass writes in the same direction. Snoop attribute field818is utilized to determine if transactions are snooped. As shown, channel ID Field806identifies a channel that a transaction is associated with.

Link Layer

Returning toFIG. 7, Link layer710, also referred to as data link layer710, acts as an intermediate stage between transaction layer705and the physical layer720. In one embodiment, a responsibility of the data link layer710is providing a reliable mechanism for exchanging Transaction Layer Packets (TLPs) between two components a link. One side of the Data Link Layer710accepts TLPs assembled by the Transaction Layer705, applies packet sequence identifier710, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 712, and submits the modified TLPs to the Physical Layer720for transmission across a physical to an external device.

Physical Layer

In one embodiment, physical layer720includes logical sub block721and electrical sub-block722to physically transmit a packet to an external device. Here, logical sub-block721is responsible for the “digital” functions of Physical Layer721. In this regard, the logical sub-block includes a transmit section to prepare outgoing information for transmission by physical sub-block722, and a receiver section to identify and prepare received information before passing it to the Link Layer1110.

Physical block722includes a transmitter and a receiver. The transmitter is supplied by logical sub-block721with symbols, which the transmitter serializes and transmits onto to an external device. The receiver is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is de-serialized and supplied to logical sub-block721. In one embodiment, an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received. Here, special symbols are used to frame a packet with frames723. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

As stated above, although transaction layer705, link layer710, and physical layer1020are discussed in reference to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not so limited. In fact, any layered protocol may be included/implemented. As an example, an port/interface that is represented as a layered protocol includes: (1) a first layer to assemble packets, i.e. a transaction layer; a second layer to sequence packets, i.e. a link layer; and a third layer to transmit the packets, i.e. a physical layer. As a specific example, a common standard interface (CSI) layered protocol is utilized.

Referring next toFIG. 9, an embodiment of a PCIe serial point to point fabric is illustrated. Although an embodiment of a PCIe serial point-to-point link is illustrated, a serial point-to-point link is not so limited, as it includes any transmission path for transmitting serial data. In the embodiment shown, a basic PCIe link includes two, low-voltage, differentially driven signal pairs: a transmit pair906/911and a receive pair912/907. Accordingly, device905includes transmission logic906to transmit data to device910and receiving logic907to receive data from device910. In other words, two transmitting paths, i.e. paths916and917, and two receiving paths, i.e. paths918and919, are included in a PCIe link.

A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or other communication path. A connection between two devices, such as device905and device910, is referred to as a link, such as link915. A link may support one lane—each lane representing a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported Link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

A differential pair refers to two transmission paths, such as lines916and917, to transmit differential signals. As an example, when line916toggles from a low voltage level to a high voltage level, i.e. a rising edge, line917drives from a high logic level to a low logic level, i.e. a falling edge. Differential signals potentially demonstrate better electrical characteristics, such as better signal integrity, i.e. cross-coupling, voltage overshoot/undershoot, ringing, etc. This allows for better timing window, which enables faster transmission frequencies.

Note that the apparatus', methods', and systems described above may be implemented in any electronic device or system as aforementioned. As specific illustrations, the figures below provide exemplary systems for utilizing the invention as described herein. As the systems below are described in more detail, a number of different interconnects are disclosed, described, and revisited from the discussion above. And as is readily apparent, the advances described above may be applied to any of those interconnects, fabrics, or architectures.

Referring now toFIG. 10, shown is a block diagram of an embodiment of a multicore processor. As shown in the embodiment ofFIG. 10, processor1000includes multiple domains. Specifically, a core domain1030includes a plurality of cores1030A-1030N, a graphics domain1060includes one or more graphics engines having a media engine1065, and a system agent domain1010.

In various embodiments, system agent domain1010handles power control events and power management, such that individual units of domains1030and1060(e.g. cores and/or graphics engines) are independently controllable to dynamically operate at an appropriate power mode/level (e.g. active, turbo, sleep, hibernate, deep sleep, or other Advanced Configuration Power Interface like state) in light of the activity (or inactivity) occurring in the given unit. Each of domains1030and1060may operate at different voltage and/or power, and furthermore the individual units within the domains each potentially operate at an independent frequency and voltage. Note that while only shown with three domains, understand the scope of the present invention is not limited in this regard and additional domains may be present in other embodiments.

As shown, each core1030further includes low level caches in addition to various execution units and additional processing elements. Here, the various cores are coupled to each other and to a shared cache memory that is formed of a plurality of units or slices of a last level cache (LLC)1040A-1040N; these LLCs often include storage and cache controller functionality and are shared amongst the cores, as well as potentially among the graphics engine too.

As seen, a ring interconnect1050couples the cores together, and provides interconnection between the core domain1030, graphics domain1060and system agent circuitry1010, via a plurality of ring stops1052A-1052N, each at a coupling between a core and LLC slice. As seen inFIG. 10, interconnect1050is used to carry various information, including address information, data information, acknowledgement information, and snoop/invalid information. Although a ring interconnect is illustrated, any known on-die interconnect or fabric may be utilized. As an illustrative example, some of the fabrics discussed above (e.g. another on-die interconnect, Intel On-chip System Fabric (IOSF), an Advanced Microcontroller Bus Architecture (AMBA) interconnect, a multi-dimensional mesh fabric, or other known interconnect architecture) may be utilized in a similar fashion.

As further depicted, system agent domain1010includes display engine1012which is to provide control of and an interface to an associated display. System agent domain1010may include other units, such as: an integrated memory controller1020that provides for an interface to a system memory (e.g., a DRAM implemented with multiple DIMMs; coherence logic1022to perform memory coherence operations. Multiple interfaces may be present to enable interconnection between the processor and other circuitry. For example, in one embodiment at least one direct media interface (DMI)1016interface is provided as well as one or more PCIe™ interfaces1014. The display engine and these interfaces typically couple to memory via a PCIe™ bridge1018. Still further, to provide for communications between other agents, such as additional processors or other circuitry, one or more other interfaces (e.g. an Intel® Quick Path Interconnect (QPI) fabric) may be provided.

Turning next toFIG. 11, an embodiment of a system on-chip (SOC) design in accordance with the inventions is depicted. As a specific illustrative example, SOC1100is included in user equipment (UE). In one embodiment, UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Often a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.

Here, SOC1100includes 2 cores—1106and1107. Similar to the discussion above, cores1106and1107may conform to an Instruction Set Architecture, such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters. Cores1106and1107are coupled to cache control1108that is associated with bus interface unit1109and L2 cache1110to communicate with other parts of system1100. Interconnect1110includes an on-chip interconnect, such as an IOSF, AMBA, or other interconnect discussed above, which potentially implements one or more aspects of the described invention.

Interface1110provides communication channels to the other components, such as a Subscriber Identity Module (SIM)1130to interface with a SIM card, a boot ROM1135to hold boot code for execution by cores1106and1107to initialize and boot SOC1100, a SDRAM controller1140to interface with external memory (e.g. DRAM1160), a flash controller1145to interface with non-volatile memory (e.g. Flash1165), a peripheral control1150(e.g. Serial Peripheral Interface) to interface with peripherals, video codecs1120and Video interface1125to display and receive input (e.g. touch enabled input), GPU1115to perform graphics related computations, etc. Any of these interfaces may incorporate aspects of the invention described herein.

In addition, the system illustrates peripherals for communication, such as a Bluetooth module1170, 3G modem1175, GPS1185, and WiFi1185. Note as stated above, a UE includes a radio for communication. As a result, these peripheral communication modules are not all required. However, in a UE some form a radio for external communication is to be included.

Referring now toFIG. 12, shown is a block diagram of a second system1200in accordance with an embodiment of the present invention. As shown inFIG. 12, multiprocessor system1200is a point-to-point interconnect system, and includes a first processor1270and a second processor1280coupled via a point-to-point interconnect1250. Each of processors1270and1280may be some version of a processor. In one embodiment,1252and1254are part of a serial, point-to-point coherent interconnect fabric, such as Intel's Quick Path Interconnect (QPI) architecture. As a result, the invention may be implemented within the QPI architecture.

While shown with only two processors1270,1280, it is to be understood that the scope of the present invention is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

Processors1270and1280are shown including integrated memory controller units1272and1282, respectively. Processor1270also includes as part of its bus controller units point-to-point (P-P) interfaces1276and1278; similarly, second processor1280includes P-P interfaces1286and1288. Processors1270,1280may exchange information via a point-to-point (P-P) interface1250using P-P interface circuits1278,1288. As shown inFIG. 12, IMCs1272and1282couple the processors to respective memories, namely a memory1232and a memory1234, which may be portions of main memory locally attached to the respective processors.

Processors1270,1280each exchange information with a chipset1290via individual P-P interfaces1252,1254using point to point interface circuits1276,1294,1286,1298. Chipset1290also exchanges information with a high-performance graphics circuit1238via an interface circuit1292along a high-performance graphics interconnect1239.

Chipset1290may be coupled to a first bus1216via an interface1296. In one embodiment, first bus1216may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As shown inFIG. 12, various I/O devices1214are coupled to first bus1216, along with a bus bridge1218which couples first bus1216to a second bus1220. In one embodiment, second bus1220includes a low pin count (LPC) bus. Various devices are coupled to second bus1220including, for example, a keyboard and/or mouse1222, communication devices1227and a storage unit1228such as a disk drive or other mass storage device which often includes instructions/code and data1230, in one embodiment. Further, an audio I/O1224is shown coupled to second bus1220. Note that other architectures are possible, where the included components and interconnect architectures vary. For example, instead of the point-to-point architecture ofFIG. 12, a system may implement a multi-drop bus or other such architecture.

The following paragraphs provide examples of various ones of the embodiments disclosed herein.

Example 1 is a method for performing a data prefetch to a cache memory, the method performed by a root complex compliant with a Peripheral Component Interconnect Express (PCIe) protocol, the method including receiving, from a device connected to the root complex across a PCIe-compliant link, a data packet; identifying from the received device a memory transaction hint bit; determining a memory transaction from the memory transaction hint bit; and performing an optimization process based, at least in part, on the determined memory transaction.

Example 2 may include the subject matter of example 1 or example 5, further comprising identifying a hint indication bit in the data packet, the hint indication bit indicating that a hint bit is set in the data packet.

Example 3 may include the subject matter of example 2, wherein identifying a hint indication bit in the data packet comprises reading a predetermined bit from a set of reserved bits, and determining that the predetermined bit indicates that a hint bit is set.

Example 4 may include the subject matter of any of examples 1-3, wherein identifying a memory transaction hint bit comprises reading a predetermined bit from a set of reserved bits; and determining that the predetermined bit indicates an imminent memory transaction.

Example 5 may include the subject matter of any of examples 1-4, wherein the received data packet comprises an address translation service request packet.

Example 6 may include the subject matter of example 5, wherein the memory transaction hint bit occupies at a packet location defined by DW0.byte3.bits[2:0].

Example 7 may include the subject matter of any of examples 5-6, further comprising identifying memory address location information from the received data packet, the memory address location information occupying a set of reserved bits defined by DW3, Byte 3, Bits [7:3] and DW3, Byte 2, Bits [2:0].

Example 8 may include the subject matter of any of examples 1-4, wherein the received data packet comprises a zero length write packet.

Example 9 may include the subject matter of example 8, wherein the memory transaction hint bit occupies unused lower address bits of the zero length write data packet.

Example 10 may include the subject matter of any of examples 1-9, wherein performing the optimization process comprises performing a caching behavior optimization process.

Example 11 may include the subject matter of any of examples 1-10, wherein the caching behavior optimization process comprises performing a prefetch of ownership in response to the memory transaction hint indicating a streaming write.

Example 12 may include the subject matter of any of examples 1-10, wherein the caching behavior optimization process comprises performing a prefetch of data and loading the data into a cache memory in response to the memory transaction hint indicating a read transaction.

Example 13 may include the subject matter of any of examples 1-10, wherein the caching behavior optimization process comprises performing a prefetch of ownership and data in response to the memory transaction hint indicating an atomics operation or a cacheable operation.

Example 14 may include the subject matter of any of examples 1-10, wherein performing the optimization process comprises initializing an identified page of memory that comprises predetermined characteristics.

Example 15 may include the subject matter of example 14, wherein initializing the identified page of memory comprises updating metadata stored with the page in memory.

Example 16 may include the subject matter of example 15, wherein updating metadata comprises adding capabilities to the page, the capabilities comprising security features for the memory transaction.

Example 17 is computer program product tangibly embodied on non-transitory computer-readable media, the computer program product comprising code that when executed cause a root complex hardware element to receive, from a device connected to the root complex across a PCIe-compliant link, a data packet; identify from the received device a memory transaction hint bit; determine a memory transaction from the memory transaction hint bit; and perform an optimization process based, at least in part, on the determined memory transaction.

Example 18 may include the subject matter of example 17, wherein the code, when executed, causes the root complex to identify a hint indication bit in the data packet, the hint indication bit indicating that a hint bit is set in the data packet.

Example 19 may include the subject matter of any of examples 17-18, wherein the code, when executed, causes the root complex to identify a memory transaction hint bit by reading a predetermined bit from a set of reserved bits; and determine that the predetermined bit indicates an imminent memory transaction.

Example 20 may include the subject matter of any of examples 17-19, wherein the optimization process comprises performing a caching behavior optimization process.

Example 21 may include the subject matter of example 20, wherein the caching behavior optimization process comprises performing a prefetch of ownership in response to the memory transaction hint indicating a streaming write, performing a prefetch of data and loading the data into a cache memory in response to the memory transaction hint indicating a read transaction, performing a prefetch of ownership and data in response to the memory transaction hint indicating an atomics operation or a cacheable operation.

Example 22 may include the subject matter of any of examples 17-21, the optimization process comprises initializing an identified page of memory that comprises predetermined characteristics.

Example 23 may include the subject matter of example 22, wherein initializing the identified page of memory comprises updating metadata stored with the page in memory.

Example 24 may include the subject matter of example 23, wherein updating metadata comprises adding capabilities to the page, the capabilities comprising security features for the memory transaction.

Example 25 is a method performed at a device connected to a root complex by a Peripheral Component Interconnect Express (PCIe)-compliant link, the method comprising determining an imminent memory transaction using a memory connected to the root complex; setting a hint indication bit in a first reserved bit of a data packet; setting a memory transaction bit in a second reserved bit of the data packet; transmitting the data packet to the root complex across the PCIe-compliant link.

Example 26 may include the subject matter of example 25, and can also include setting other reserved bits to add granularity to the memory transaction indication.

Example 27 is a root complex structure, the root complex structure coupled to a processor and a memory, the root complex structure connected to a plurality of connected devices by a switch fabric compliant with the PCIe protocol. The root complex can include logic implemented at least partially in hardware, to receive, from a device connected to the root complex across a PCIe-compliant link, a data packet; identify from the received device a memory transaction hint bit; determine a memory transaction from the memory transaction hint bit; and perform an optimization process based, at least in part, on the determined memory transaction.

Example 28 may include the subject matter of example 27, wherein the code, when executed, causes the root complex to identify a hint indication bit in the data packet, the hint indication bit indicating that a hint bit is set in the data packet.

Example 29 may include the subject matter of any of examples 27-28, wherein the code, when executed, causes the root complex to identify a memory transaction hint bit by reading a predetermined bit from a set of reserved bits; and determine that the predetermined bit indicates an imminent memory transaction.

Example 30 may include the subject matter of any of examples 27-29, wherein the optimization process comprises performing a caching behavior optimization process.

Example 31 may include the subject matter of example 30, wherein the caching behavior optimization process comprises performing a prefetch of ownership in response to the memory transaction hint indicating a streaming write, performing a prefetch of data and loading the data into a cache memory in response to the memory transaction hint indicating a read transaction, performing a prefetch of ownership and data in response to the memory transaction hint indicating an atomics operation or a cacheable operation.

Example 32 may include the subject matter of any of examples 27-31, the optimization process comprises initializing an identified page of memory that comprises predetermined characteristics.

Example 33 may include the subject matter of example 32, wherein initializing the identified page of memory comprises updating metadata stored with the page in memory.

Example 34 may include the subject matter of example 33, wherein updating metadata comprises adding capabilities to the page, the capabilities comprising security features for the memory transaction.