Methods for manufacturing an active matrix display device

The present invention is to carry out stable doping and to prevent the drastic pressure change in a treatment chamber by reducing degasification of resist during adding impurities. In the present invention, the stability of the impurity ion injection can be ensured by reducing degasification of resist by reducing the area (resist area proportion, that is, the ratio of the area of resist to the whole area of a substrate) of resist pattern which is used depending on the conditions such as acceleration voltage or current density of a doping process.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing a semiconductor apparatus. More specifically the present invention relates to technique for adding conductive impurities to a semiconductor over a substrate.

2. Related Art

In case of forming an impurity region such as a source or a drain region that is a component of a thin film transistor (TFT), various methods for adding impurities are adopted.

As a method for adding impurities, for example, ion implantation, ion doping, or the like is utilized. The ion implantation is the technique, that is, elements such as boron (B), phosphorus (P), or the like is ionized and mass-separated, then, only necessary ions are accelerated by an electric field, and then, doped to a semiconductor such as silicon. The ion doping is the technique, that is, ions are accelerated by an electric field and doped without mass separation.

In case of utilizing such technique, only desired regions can be added with impurities by means of masking the region where doping is not wanted to be carried out.

However, there are problems that resist which is generally used as a mask is degassed by ion beam irradiation, due to this, pressure in a treatment chamber is increased, and so ion beam becomes impossible to be irradiated, an injection amount of impurities has a margin of error, or the like.

As technique for reducing degasification of resist, it is known that heating resist previously to remove degasification during doping (See Reference 1: Unexamined Patent Publication No. 5-55159).

SUMMARY OF THE INVENTION

In view of the foregoing, it is an object of the present invention is to carry out stable doping and to prevent the drastic pressure change in a treatment chamber by reducing degasification of resist during adding impurities.

In the present invention, the stability of the impurity ion injection is ensured by reducing degasification of resist by reducing the area (resist area proportion, that is, the ratio of the area of resist to the whole area of a substrate) of resist pattern which is used depending on the conditions such as acceleration voltage or current density of a doping process.

Therefore, one of the constitutions of the present invention is: a method for manufacturing a semiconductor apparatus comprising the steps of:

forming a semiconductor over a substrate;

forming a mask formed of resist over the semiconductor to overlap with a portion of the semiconductor and heating the resulted mask; and

adding an impurity element by a doping method;

wherein an area of the mask is smaller than that of a mask which has an opening only in an impurity element doped region and in an adjusting margin over the semiconductor.

In the above-described constitution, the term “the adjusting margin” refers to a portion for misalignment of the mask when adding impurity elements on the semiconductor. Specifically, it is preferable that the distance from the edge of the semiconductor to the edge of the adjusting margin be at most 10 μm.

In the above constitution, it is preferable that the area of mask be at most 35% of the area of the substrate in case of reducing the area of the mask. Especially, it produces great effects in case of doping with the acceleration voltage of 80 kV.

In the above constitution, it is preferable that the area of mask be formed to be at most 15% of the area of substrate in case that the mask is not heated.

In the above constitution, it is preferable that the area of the mask be formed to be at most 35% of the area of substrate in case of doping with the acceleration voltage of at least 80 kV and the current density at least 540 μA/cm, however, it is preferable that the area of mask be formed to be at most 40% in case of doping with the current density of 450 μA/cm.

In the above constitution, it is preferable that the area of mask be at most 40% in case of doping with the acceleration voltage of 80 kV and the current density of at most 450 μA/cm

In addition, the amount of degassed gas increases not only when increasing the current density but also when increasing the acceleration voltage during doping. Therefore, as one of probable cases, the current density and the acceleration voltage of either impurity elements are increased in case that n-type impurity elements (phosphorus, etc.) and p-type impurity elements (boron, etc.) are added by ion implantation.

For example, in case of increasing the current density or the acceleration voltage at ion-implanting of the p-type impurity elements than those of the n-type impurity elements, it is necessary that an area of resist which is used for adding the p-type impurity elements is smaller than that for adding the n-type impurity elements. Specifically, it is preferable that the resist area proportion be at most 20% in case that the p-type impurity elements are added by ion implantation with the acceleration voltage of 60 kV and the current density of 15 μA/cm2, whereas it is preferable that the resist area proportion be at most 15% in case that the n-type impurity elements are added by ion implantation with the acceleration voltage of 80 kV and the current density of 15 μA/cm2.

Therefore, the constitution of the present invention in such a case is: a method for manufacturing a semiconductor apparatus comprising the steps of:

forming a semiconductor over a substrate;

forming a gate electrode over the semiconductor via an insulating film;

forming a first mask formed of resist in a position to overlap with a portion of the semiconductor;

adding an n-type impurity element by a doping method with current density of at least 15 μA/cm2and with acceleration voltage of at least 60 kV;

removing the first mask;

forming a second mask formed of resist in a position to overlap with a portion of the semiconductor; and

adding a p-type impurity element by a doping method with current density of at least 15 μA/cm2and with acceleration voltage of at least 80 kV;

wherein an area of the first mask is at most 20% of an area of the substrate, and an area of the second mask is at most 15% of an area of the substrate.

The present invention includes not only the structure that reduces an area of the resist but also that removes previously degasification of resist by heating the substrate before carrying out doping.

Thus, the constitution of the present invention in such a case is: a method for manufacturing a semiconductor apparatus comprising the steps of:

forming a semiconductor over a substrate;

forming a gate electrode over the semiconductor via an insulating film;

forming a first mask formed of resist in a position to overlap with a portion of the semiconductor and heating the resulted first mask;

adding an n-type impurity element by a doping method with current density of at least 15 μA/cm2and with acceleration voltage of at least 60 kV;

removing the first mask;

forming a second mask formed of resist in a position to overlap with a portion of the semiconductor and heating the resulted second mask; and

adding a p-type impurity element by a doping method with current density of at least 15 μA/cm2and with acceleration voltage of at least 80 kV;

wherein an area of the first mask is at most 40% of an area of the substrate, and an area of the second mask is at most 35% of an area of the substrate.

Further, the structure of a semiconductor apparatus manufactured by using the doping method according to the present invention is: a semiconductor apparatus including a plurality of an n-channel TFT or a p-channel TFT over a substrate, comprising:

an island like semiconductor including an n-type impurity region and an island like semiconductor including a p-type impurity region over the substrate;

an insulating film formed over the substrate to cover the island like semiconductor including the n-type impurity region and the island like semiconductor including the p-type impurity region; and

a gate electrode formed to overlap a portion of the island like semiconductor including the n-type impurity region and a portion of the island like semiconductor including the p-type impurity region via the insulating film;

wherein an impurity concentration of the insulating film is lower than that of another region in a position which is overlapping with the n-type impurity region.

Also, the structure of a semiconductor apparatus manufactured by using the doping method according to the present invention is: a display device including a plurality of pixel portions, and a plurality of an n-channel TFT or a p-channel TFT over a substrate, comprising:

an island like semiconductor including an n-type impurity region and an island like semiconductor including a p-type impurity region over the substrate;

an insulating film formed over the substrate to cover the island like semiconductor including the n-type impurity region and the island like semiconductor including the p-type impurity region; and

a gate electrode formed to overlap a portion of the island like semiconductor including the n-type impurity region and a portion of the island like semiconductor including the p-type impurity region via the insulating film;

wherein a part of the pixel portion contains a n-type impurity element and a p-type impurity element,

wherein a ratio of the part of the pixel portion containing impurity element to the pixel portion is no less than 80%,

wherein a concentration of the impurity element contained in a pixel part is the same grade as a TFT domain,

wherein the impurity element can be contained in any of layers which the pixel part comprises.

In addition, this invention is suitable for use in a process of using a large size substrate. For example, the area of the substrate is no less than 1 square meter.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the embodiment mode of the present invention will be described.

In Embodiment Mode 1, the results of forming resist patterns each of which has different area proportion over a substrate and implanting ions over a substrate by a doping device. Here, after resists are formed, the resulted resist are heated at 200° C. for 2 hours. The doping device has the structure in which a substrate is scanned at plural times from an ion generator to the position where ions are implanted. Ions are implanted to one position at the same number of times as the number of scanning. Specific structure of the doping device will be described in Embodiment Mode 2, so that explanation thereof is omitted here.

Firstly, the measurement of the pressure inside a treatment chamber (a doping chamber) during ion implantation gives the results that the pressure inside the treatment chamber is decreased according to decreasing the resist area proportion (%) as shown inFIG. 1(especially at the first scanning).FIG. 1shows that the pressure is measured from the first to the fourth scanning in case of implanting ions under the conditions of current density of 540 μA/cm and 450 μA/cm.

Secondly, the maximum value at every scanning during ion implantation is measured. In addition, the stability of ion implantation during doping can be evaluated from the variation of the maximum value of current density. Similarly, the maximum value of the current density in every condition is measured by changing the resist area required.FIG. 2shows the results. In addition, in any case of each current density (540 μA/cm and 450 μA/cm), the measurement shows the result that values between objective current density (540 μA/cm and 450 μA/cm) and actual maximum value of current density (especially, at the first scanning) are varied widely according to decreasing the resist area proportions (%). As shown inFIG. 2, ions are implanted in both cases of current density of 540 μA/cm and 450 μA/cm, and the maximum values of current density from the first to the fourth scanning are measured.

It is preferable that the variation of current density (maximum value) during doping be generally within 20%, so that it is preferable that the resist area proportions be at most 35% in case of acceleration voltage of 80 kV and current density of −540 μA/cm. Further, in case of acceleration voltage of 80 kV and current density of 450 μA/cm, it is preferable that the resist area proportions be at most 40%. Therefore, it is necessary that the resist area proportions are further reduced in such case that doping is carried out at high current density which makes resist be susceptible to be degassed. In addition, it is preferable that the resist area proportions be within 15% in case that the resist is not heated after forming the resist.

The pressure inside a treatment chamber can be at most 0.15 Pa as shown inFIG. 1by setting the resist area proportions at most 35%. In addition, ions can be implanted without generating abnormal electrical discharge (arcing) inside the treatment chamber under this conditions.

FIG. 3is a view showing the measurement result of pressure inside the treatment chamber in case not only of reducing the resist area proportions but also heating a substrate previous to doping.FIG. 4is a view of showing the measurement result of the maximum value of current density.

As shown inFIGS. 3 and 4, the measurements show that degasification of resist and variations of current density (maximum value) can be reduced by not only reducing resist area proportions but also heating a substrate previous to doping.

FIG. 5is a view showing the measurement result of the pressure inside a treatment chamber in case that the thicknesses of resist are different.FIG. 6is a view showing the measurement result of the maximum value of current density.

As shown inFIGS. 3 and 4, the measurements show that degasification of resist and variations of current density (maximum value) can be reduced.

In this embodiment mode, a method for doping according to the present invention will be described. The case that n-type impurity elements and p-type impurity elements are added respectively to one substrate by doping method using resist with minimal area proportions as a mask will be described.

InFIG. 7A, a base film702is formed to have a thickness of from 50 to 200 nm, which is formed of one kind or plural kinds selected from the group consisting of silicon nitride, silicon oxide, or silicon oxynitride, over a substrate701formed of glass, such as barium borosilicate glass or aluminum borosilicate, quartz, or the like, and semiconductor films703a,703bhaving shapes of islands are formed over the base film702. In the present invention, a silicon substrate can be used for the substrate701.

Next, a gate insulating film704is formed to have a thickness of 80 nm. The gate insulating film704is formed by plasma CVD or sputtering. A silicon oxynitride film formed of SiH4and N2O added with O2is preferable as a material for the gate insulating film704since the silicon oxynitride film704can be reduced the fixed charge density in the film. But not exclusively, the gate insulating film can be formed of a single insulating layer or a laminate insulating layer such as a silicon oxide film, a tantalum oxide film, or the like.

Then, a conductive film is formed over the gate insulating film704to form and a gate electrodes705a,705bby dry etching with masks. In addition, there is no limitation of kinds of a conductive film used, conductive materials such as Al, Ta, Ti, W, Mo, or the like or alloys of these materials are utilized. As the structure of the gate electrodes705a,705bformed by using such materials, a lamination structure, for example, a tantalum nitride or titanium nitride/W or Mo—W alloy; W/Al or Cu; Ti/Al—Si/Ti; TaN/Ti, or the like is utilized. In case of using Al, from 0.1 to 7 atom % of Ti, Sc, Nd, Si, Cu, or the like is added to the Al for improving the heat resistance. Further, the conductive film is formed to have approximately a thickness of from 300 to 500 nm (FIG. 7A).

N-type impurity elements are added by ion implantation (here, ion implantation without mass separation is used). In this case, a first mask formed of resist is formed in order to implant n-type impurity elements (phosphorus) into the portion so as not to overlap with the gate electrode705aof the semiconductor film703a. Phosphorus (dose amounts of 2×1015/cm2) is implanted under the conditions, that is, 20% of PH3is used as impurity gas; 15 μA/cm2of the current density; and 60 kV of the acceleration voltage. As shown inFIG. 7B, the first mask706is formed over not only over the semiconductor film703bwhere p-type impurity elements are implanted in the following process but also over a part of the gate insulating film704, however, there is no problem since the amount of degassed gas does not give adverse effects to the stability of doping in case of doping under such conditions of the current density and the acceleration voltage. It is preferable that the area proportions of the first mask706be at most 20%, whereas it is preferable that the area proportions of the first mask706be at most 40% in case that a mask is heated (for example, 200° C., 2 hours) after forming the mask and before doping.

After completing the phosphorus implantation, the first mask706is peeled off by ashing. The ashing is carried out in oxygen plasma and the resist can be peeled off for from 30 to 45 minutes.

Next, p-type impurity elements are added by ion implantation. In this case, a second mask707is formed in order to implant p-type impurity elements into the portion where the gate electrode705bof the semiconductor film703bis not overlapped. Boron (dose amounts of 8×1015/cm2) is implanted under the conditions, that is, B2H6of 15% is used as impurity gas; the current density of 10 μA/cm2; and the acceleration voltage of 80 kV. As shown inFIG. 7C, the second mask707is formed to overlap only the semiconductor film703aimplanted with n-type impurity elements so as to control the area proportions of the second mask707are small as much as possible. The reason is that the amount of degasification gives adverse effects on the stability of doping under the condition of the current density and the acceleration voltage for adding p-type impurity elements. It is preferable that the area proportions of the second mask707be at most 15%, whereas it is preferable the area proportions of the second mask707be at most 35% in case that a mask is heated (for example, 200° C., 2 hours) after forming the mask and before doping.

After completing the boron implantation, the second mask707is peeled by ashing. The ashing is carried out in oxygen plasma and the resist can be peeled off for from 30 to 45 minutes.

Then, as shown inFIG. 7D, a first insulating film708, which is formed of a silicon oxynitride film, a silicon nitride film, or a silicon nitride oxide film, is formed to have a thickness of 100 nm by plasma CVD.

Heat treatment is carried out for recovery and activation of crystallinity of semiconductor regions of n-type and p-type. The heat treatment can be carried out by rapid thermal annealing, laser annealing, or the like, in addition to furnace annealing oven. A second insulating film709is formed over the first insulating film708. The second insulating film709may be formed by organic insulating materials (including photosensitive materials or nonphotosensitive materials) such as polyimide, acrylic, or the like, and flattened its surface. The thickness of the second insulating film709is from 0.5 to 1 μm.

Next, contact holes are formed on the insulating film709to reach impurity regions (an n-type impurity region710, p-type impurity region711) of each semiconductor film to form wirings using Al, Ti, Ta, or the like. InFIG. 7D, each reference numerals712a,712b,713a,713bis a source line (electrode) or a drain line (electrode). Thus, an n-channel type TFT714and a p-channel type TFT715can be formed. Although each TFT is illustrated as a unit here, these TFT's can be formed into a CMOS circuit, an NMOS circuit, or a PMOS circuit.

Therefore, in case that an n-channel TFT and a p-channel TFT are formed by adding each n-type or p-type impurity elements to one substrate, the stability of doping can be obtained by controlling the resist area proportions as much as small if doping is carried out under the conditions causing the problem of degasification of resist.

A doping device used in the present invention will be described reference toFIG. 8in this embodiment mode.FIG. 8Ais a view showing a top-surface of the doping device.FIG. 8Bis a cross-sectional view of a doping chamber included in the doping device.

Main constitutions of the doping device are: a treatment chamber802having ion source801; a load lock chamber (1)803; a load lock chamber (2)804; a transporting chamber805; and an air displacement pump806. The treatment chamber802is a place for infecting ion while moving alternately a substrate in the direction of the arrow shown inFIG. 8Aand has a substrate stage807and a pressure gauge808.

Transportation of a substrate is start from the load lock chambers (1)803and (2)804into the treatment chamber802by an arm810provided with the transporting chamber805, or start from the treatment chamber802into the load lock chambers (1)803and (2)804.

The treatment chamber802and the transporting chamber805are constantly kept vacuum by the air displacement pump806whereas the load lock chambers (1)803and (2)804are discharged to the atmosphere for taking a substrate in and out and subsequently kept vacuum by the air displacement pump806. A dry pump, a mechanical booster pump, a turbo molecular pump, or the like can be used by combining appropriately themselves as the air displacement pump806.

In the treatment chamber shown inFIG. 8B, the ion source801is provided with a gas supplying system811for supplying gas including doping elements (hereinafter, doping gas) and a discharge electrode812for forming plasma.

An accelerating unit813is provided with electrodes such as a leading out electrode (a leading out electrode, an accelerating electrode, a suppressing electrode, and an earth electrode). A great number of openings are provided to these electrodes and ions are passing through the openings. Ions are accelerated by the leading out electrode that is applied with leading out voltage and an accelerated electrode that is applied with accelerated voltage. The suppressing electrode enhances the direction of the flow of ions by collecting dispersed ions.

PH3, B2H6, or the like is used as doping gas and diluted to approximately from 1 to 20% with hydrogen and inert gas. In case of using PH3, PHx+, P2Hx+, Hx+, or the like is generated as ion species, these ions are leaded out in the direction of the substrate by accelerating by the electrodes such as leading out electrodes in case of without mass separation. Ions are leaded out linearly as indicated by arrows inFIG. 8Bby the electrode in the accelerating unit813and irradiated on the substrate.

A substrate809that is transported into the treatment chamber802is provided with the resist that is for adding impurity elements to a desired position as described in Embodiment Mode 2. Further stable doping can be realized by adding n-type or p-type impurity elements to the substrate.

In case of manufacturing a plurality of TFT is formed in the pixel portion of a semiconductor apparatus, a mask pattern formed of resist that is used for adding n-type impurity elements and p-type impurity elements will be described in Embodiment Mode 4.

FIG. 9Ais a view showing a top-surface of a pixel portion over a substrate on which a mask pattern is formed for adding n-type impurity elements.FIG. 9Bis a cross-sectional view ofFIG. 9Ataken along the line of A-A′.

As shown inFIGS. 9A and 9B, a mask for adding an n-type impurity element907is formed by covering a semiconductor films903a, a semiconductor film903bformed over a substrate901, a gate electrode905b, and a gate signal line906.

In the semiconductor film903a, an n-type impurity region908can be formed in the portion where the gate electrode905is not overlapped by adding n-type impurity elements by the doping device described in Embodiment Mode 3.

In case of adding n-type impurity elements by ion implantation, phosphorus (dose amounts of 2×1015/cm2) is doped under the conditions, that is, PH3of 20% is used as impurity gas; the current density of 15 μA/cm2; and the acceleration voltage of 60 kV. As shown inFIGS. 9A and 9B, the mask for adding n-type impurity element907is formed not only over the semiconductor film903bbut also over the gate signal line906and a part of the gate insulating film904, however, there is no problem since the amount of degassed gas does not give adverse effects to the stability of doping in case of doping under such conditions of the current density and the acceleration voltage. In this case, the area proportions of the mask for adding n-type impurity element907to the whole substrate is 40%. The degasification can be suppressed if the area proportions of the mask for adding n-type impurity element907are reduced.

In case that light generated in a device formed in a pixel portion is emitted from a substrate, it is not preferable that unnecessary impurities are doped into the portion where pixels are formed in the following process since that will cause the problems of deterioration in transmittance.

After completing the phosphorus implantation, the mask for adding n-type impurity element907is peeled off by ashing. The ashing is carried out in oxygen plasma and the resist is peeled off for from 30 to 45 minutes.

Next, a mask is formed as shown inFIGS. 10A and 10B, and p-type impurity elements are doped.FIG. 10Ais a view showing a top-surface of a pixel portion over a substrate on which a mask pattern is formed for adding p-type impurity elements.FIG. 10Bis a cross-sectional view ofFIG. 10Ataken along the line of A-A′. ThroughFIG. 10, like components are denoted by like numerals as ofFIG. 9.

As shown inFIG. 10A, a mask for adding p-type impurity element1001is formed overlapping with the semiconductor film903a, the gate electrode905a, and a part of the gate signal line906that are formed on the substrate901.

By adding p-type impurity elements by the doping device described in Embodiment Mode 2, a p-type impurity region1002can be formed in the semiconductor film903bexcept the region where the gate electrode is not overlapped.

Further, in case of adding p-type impurity elements by ion implantation, boron (dose amounts of 8×1015/cm2) is implanted under the conditions, that is, B2H6of 15% is used as impurity gas; the current density of 10 μA/cm2; and acceleration voltage of 80 kV. In case ofFIGS. 10A and 10B, the mask for adding p-type impurity element1001is formed overlapping only the semiconductor film903aso as to control the area proportions of the mask to be small as much as possible inFIGS. 9A and 9B. The reason of that is the conditions of the current density and the acceleration voltage for adding p-type impurity elements cause a great deal of degasification and affect adversely on the stability of the doping compared with adding n-type impurity elements.

Although in case of adding n-type impurity elements the resist area proportions are designed to be comparatively large in view of decrease in the transmittance due to unnecessary impurities, in case of adding p-type impurity elements the resist area proportions are designed to be comparatively small since there are large adverse effects of degasification on the doping. In this case, the area proportions of the mask for adding p-type impurity element1001to the whole substrate are 7%. The degasification can be suppressed if the area proportions of the mask for adding p-type impurity element907are reduced.

After completing the phosphorus implantation, the mask for adding p-type impurity element1001is peeled off by ashing. The ashing is carried out in oxygen plasma and the resist can be peeled off for from 30 to 45 minutes.

FIG. 11is a view of a substrate on which the mask for adding p-type impurity element1001is removed, and each n-type impurity elements and p-type impurity elements are doped into the desired portion. An n-channel TFT and a p-channel TFT that are controlled sufficiently the amount of doped impurities can be manufactured over one substrate by combining the process described in Embodiment Mode 1 after forming each the n-type impurity region908and the p-type impurity region1002in the pixel portion of the semiconductor apparatus since prevention of the degasification and the stable doping can be realized by using the mask pattern described in this embodiment mode.

Among TFTs formed in the pixel portion, an n-channel TFT functions as a switching TFT and an erasing TFT, and a p-channel TFT functions as a current controlling TFT. Either the p-type impurity regions of the p-channel TFT connects electrically to a pixel electrode formed in the following process.

A light-emitting apparatus having a light-emitting device in a pixel portion among semiconductor apparatuses manufactured by a method for doping according to the present invention will be described in Embodiment Mode 5 with reference toFIG. 12.FIG. 12Ais a view showing a top surface of a light-emitting apparatus.FIG. 12Bis a cross-sectional view ofFIG. 12Ataken along the line A-A′. Reference numeral1201denotes a driver circuit portion (a source side driver circuit);1202, pixel portion;1203, a driver circuit portion (a gate side driver circuit);1204, a sealing substrate; and1205, a sealant. Reference numeral1207encircled by the sealant1205is a space.

Reference numeral1208denotes a lead wiring for transmitting signals inputted to the source side driver circuit1201and the gate side driver circuit1202. The lead wiring1208receives a video signal, a clock signal, a start signal, a reset signal, or the like from a FPC (flexible printed circuit)1209serving as an external input terminal. Although only the FPC1209is illustrated here, a printed wiring board (PWB) is attached to the FPC1209. The light-emitting apparatus described in this specification includes not only a main body of a light-emitting apparatus but also a light-emitting apparatus attached with a FPC or a PWB.

Next, a cross-sectional structure will be described with reference toFIG. 12B. A driver circuit portion and a pixel portion are formed over a device substrate1210. The source side driver circuit1201that is the driver circuit portion and the pixel portion1210are illustrated inFIG. 12B.

An n-channel TFT1223and a p-channel TFT1224are combined for forming a CMOS circuit as the source side driver circuit1201. A TFT for forming a driver circuit portion may be formed by a known CMOS circuit, PMOS circuit, or NMOS circuit. In this embodiment mode, a driver-integrated type in which a driver circuit is formed over a substrate is illustrated, but not exclusively, the driver circuit can be formed exteriorly.

Further, the pixel portion1202is formed of a plurality of pixel including a switching TFT1211, a current control TFT1212, and a pixel electrode1213connected electrically to the drain of the current control TFT1212. An insulator1214is formed by covering the edge portion of the pixel electrode1213. Here, the insulator1214is formed by using a positive type acrylic resin film.

In order to improve the deposition, the upper edge portion or the lower edge portion of an insulator1214is formed to have a curved surface having radius of curvature. For example, in case of using a positive type acrylic resin film, it is preferable that only an upper edge portion of the insulator1214has a curved surface having a radius of curvature (from 0.2 to 3 μm). As a material for forming the insulator1214, either a negative type that become an insoluble material in etchant according to light to which photosensitive material is exposed or a positive type that become a dissoluble material in etchant according to light to which photosensitive material is exposed can be used.

Each an electroluminescent layer1216and a counter electrode1217is formed over the pixel electrode1213. As a material for forming the pixel electrode1213serving as an anode, a material having large work function is preferable. For example, in addition to a single layered film such as an ITO (indium tin oxide) film, an IZO (indium zinc oxide) film, a titanium nitride film, a chrome film, a tungsten film, a Zn film, a Pt film, a lamination layered film stacked with a film containing titanium nitride and aluminum as its main component, three layered film of a titanium nitride film, a film containing aluminum as its main component, and a titanium nitride film, or the like can be used as the pixel electrode. In case of forming the anode to have a lamination structure, the electrode can be formed to have a low resistance as a wiring, have a good ohmic contact, and function as an anode.

The electroluminescent layer1216is formed by vapor deposition using an evaporation mask or ink jetting. As a material for forming the electroluminescent layer1216, a low molecular material or a polymer material can be used. Generally, there are many cases that an organic compound is used as a single layer or a lamination layer, however, the structure in which an inorganic compound is used as a part of a film composed of an organic compound is included in the present invention. Moreover, a known triplet material can be included.

As a material for forming the counter electrode (cathode)1217formed over the electroluminescent layer1216, a material having small work function (Al, Ag, Li, Ca, or alloy of these elements such as MgAg, MgIn, AlLi, CaF2, or CaN) can be used. In case that light generated in the electroluminescent layer1216is emitted through the counter electrode1217, a lamination of a metal thin film formed to have a thin thickness and a transparent conductive film (ITO (indium tin oxide), alloy of indium zinc oxide (In2O3—ZnO), zinc oxide (ZnO), or the like) can be used as the counter electrode1217.

A light-emitting device1218is formed in the space encircled by the device substrate1210, the sealing substrate1204, and the sealant1205by bonding the sealing substrate1204to the device substrate1210with the sealant1205. The space1207is filled with inert gas (nitride, argon, or the like) or the sealant1205.

It is preferable to use epoxy resin as the sealant1205. In addition, it is desired that these materials inhabit moisture and oxygen as much as possible. As a material for forming the sealing substrate1204, a plastic substrate formed of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Myler, polyester, acrylic, or the like be used in addition to a glass substrate or a quartz substrate.

Accordingly, a light-emitting apparatus that has a TFT as one of the components fabricated by using the doping method according to the present invention can be manufactured.

Embodiment Mode 5 can be implemented by freely combining with the structures described in Embodiment Modes 2 to 4.

Various electric appliances manufactured by using a semiconductor apparatus having a TFT manufactured by the doping method according to the present invention will be described in Embodiment Mode 6.

Given as examples of electric appliances employing a semiconductor apparatus fabricated by the doping method according to the present invention are: a video camera; a digital camera; a goggle type display (head mounted display); a navigation system; an audio reproducing device (car audio, an audio component, etc.); a laptop computer; a game machine; a portable information terminal (a mobile computer, a cellular phone, a portable game machine, an electronic book, etc.); and an image reproducing device (specifically, a device that is equipped with a display device for reproducing data in a recording medium such as a digital versatile disk (DVD)). Specific examples of the electric appliances are shown inFIGS. 13A to 13H.

FIG. 13Ashows a display device, which comprises a casing2001, a supporting base2002, a display unit2003, speaker units2004, a video input terminal2005, etc. The display device can be completed by using the semiconductor apparatus having the TFT fabricated by the doping method according to the present invention as the display unit2003. The term display device includes all of the display devices for displaying information such as one for a personal computer, one for receiving TV broadcasting, and one for advertisement. And the size of the display can be no less than 4 inches.

FIG. 13Bshows a laptop computer, which comprises a main body2201, a casing2202, a display unit2203, a keyboard2204, an external connection port2205, a pointing mouse2206, etc. The laptop computer can be completed by using the semiconductor apparatus having the TFT fabricated by the doping method according to the present invention as the display unit2203.

FIG. 13Cshows a mobile computer, which comprises a main body2301, a display unit2302, a switch2303, operation keys2304, an infrared ray port2305, etc. The mobile computer can be completed by using the semiconductor apparatus having the TFT fabricated by the doping method according to the present invention as the display unit2302.

FIG. 13Dshows a portable image-reproducing device equipped with a recording medium (a DVD player, to be specific). The device comprises a main body2401, a casing2402, a display unit A2403, a display unit B2404, a recording medium (DVD, or the like) reading unit2405, operation keys2406, speaker units2407, etc. The display unit A2403mainly displays image information whereas the display unit B2404mainly displays text information. The portable image reproducing device can be completed by using the semiconductor apparatus having the TFT fabricated by the doping method according to the present invention as the display units A2403and B2404. The term image-reproducing device equipped with a recording medium includes video game machines.

FIG. 13Eshows a goggle type display (head mounted display), which comprises a main body2501, display units2502, and arm units2503. The mobile computer can be completed by using the semiconductor apparatus having the TFT fabricated by the doping method according to the present invention as the display units2502.

FIG. 13Fshows a video camera, which comprises a main body2601, a display unit2602, a casing2603, an external connection port2604, a remote control receiving unit2605, an image receiving unit2606, a battery2607, an audio input unit2608, operation keys2609, an eye piece2610, etc. The video camera can be completed by using the semiconductor apparatus having the TFT fabricated by the doping method according to the present invention as the display unit2602.

FIG. 13Hshows a cellular phone, which comprises a main body2701, a casing2702, a display unit2703, an audio input unit2704, an audio output unit2705, operation keys2706, an external connection port2707, an antenna2708, etc. The video camera can be completed by using the semiconductor apparatus having the TFT fabricated by the doping method according to the present invention as the display unit2703. If the display unit2703displays white characters on a black background, power consumption of the cellular phone can be reduced.

As above described, the application range of the semiconductor apparatus having the TFT fabricated by the doping method according to the present invention is extremely wide so that the semiconductor apparatus can be applied to electric appliances in every field.

In the present invention, the stable doping without the drastic pressure change in a treatment chamber can be realized by reducing degasification of resist during doping by means of reducing area proportions of a mask, which is formed of resist and which is used for doping, to be smaller than the conventional one.