SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a semiconductor structure is provided. The method includes forming a fin structure protruding from a substrate, wherein the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method includes forming a dummy gate structure across the fin structure. The method includes forming a gate spacer on the sidewall of the dummy gate structure. The method includes removing the dummy gate structure to expose the fin structure. The method includes partially removing the second semiconductor material layers to form concave portions on sidewalls of the second semiconductor material layers. The method includes forming dielectric spacers in the concave portions. The method includes removing the first semiconductor material layers to form gaps. The method includes forming a gate structure in the gaps to wrap around the second semiconductor material layers and the dielectric spacers.

BACKGROUND

The electronics industry is experiencing ever-increasing demand for smaller and faster electronic devices that are able to perform a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). So far, these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such miniaturization has introduced greater complexity into the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.

Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). However, integration of fabrication of the multi-gate devices can be challenging.

DETAILED DESCRIPTION

The terms “about” and “substantially” typically mean+/−20% of the stated value, more typically +/−10% of the stated value, more typically +/−5% of the stated value, more typically +/−3% of the stated value, more typically +/−2% of the stated value, more typically +/−1% of the stated value and even more typically +/−0.5% of the stated value. The stated value of the present disclosure is an approximate value. When there is no specific description, the stated value includes the meaning of “about” or “substantially”.

Embodiments of semiconductor structures and methods for forming the same are provided. The semiconductor structures may include a gate structure formed over a substrate and a source/drain structure formed adjacent to the gate structure. A nanostructure may be wrapped by the gate structure, and a dielectric spacer may be formed adjacent to the nanostructure. Therefore, lower space is required between the nanostructure and the cut metal gate structure, so the critical dimension of the semiconductor structure may be reduced.

FIGS.1A to11illustrate perspective views of intermediate stages of manufacturing a semiconductor structure100(e.g. seeFIG.2H) in accordance with some embodiments. As shown inFIG.1A, first semiconductor material layers106and second semiconductor material layers108are formed over a substrate102in accordance with some embodiments.

The substrate102may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the substrate102may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GalnP, and/or GainAsP.

In some embodiments, the first semiconductor material layers106and the second semiconductor material layers108are alternately stacked over the substrate102. In some embodiment, the first semiconductor material layers106and the second semiconductor material layers108are made of different semiconductor materials. In some embodiments, the first semiconductor material layers106are made of SiGe, and the second semiconductor material layers108are made of silicon. It should be noted that although three first semiconductor material layers106and three second semiconductor material layers108are formed, the semiconductor structure may include more or fewer first semiconductor material layers106and second semiconductor material layers108. For example, the semiconductor structure may include two to five of the first semiconductor material layers106and the second semiconductor material layers. In some embodiments, the first semiconductor material layer106is disposed on the topmost layer of the semiconductor material stack.

In some embodiments, the first semiconductor material layers106and the second semiconductor material layers108may be formed by using low-pressure chemical vapor deposition (LPCVD), epitaxial growth process, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

After the first semiconductor material layers106and the second semiconductor material layers108are formed as a semiconductor material stack over the substrate102, the semiconductor material stack is patterned to form fin structures104A and104B, as shown inFIG.1Bin accordance with some embodiments. In some embodiments, the fin structures104A and104B includes a base fin structure105and the semiconductor material stack of the first semiconductor material layers106and the second semiconductor material layers108.

In some embodiments, a third semiconductor layer107may be disposed over the semiconductor stack and in contact with the first semiconductor material layer106. In some embodiments, the third semiconductor layer107is used for protecting the first semiconductor material layers106from subsequent processes, such as etching process. In some embodiments, the material of the third semiconductor layer107may include silicon. In some embodiments, the third semiconductor material layer107may be formed by using low-pressure chemical vapor deposition (LPCVD), epitaxial growth process, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

In some embodiments, the patterning process includes forming a mask structure110over the third semiconductor layer107and etching the semiconductor material stack and the underlying substrate102through the mask structure110. In some embodiments, the mask structure110is a multilayer structure including an oxide layer109, a nitride layer112formed over the oxide layer109, and an oxide layer114formed over the nitride layer112. The oxide layer109and the oxide layer114may be made of silicon oxide, which is formed by thermal oxidation or CVD, and the nitride layer112may be made of silicon nitride, which is formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD).

After the fin structures104A and104B are formed, an isolation structure116is formed around the fin structures104A and104B, and the mask structure110and the third semiconductor layer107are removed, as shown inFIG.1Cin accordance with some embodiments. The isolation structure116is configured to electrically isolate active regions (e.g. the fin structure104) of the semiconductor structure100and is also referred to as shallow trench isolation (STI) feature in accordance with some embodiments.

In some embodiments, the isolation structure116may be formed by depositing an insulating layer over the substrate102and recessing the insulating layer so that the fin structures104A and104B are protruded from the isolation structure116. In some embodiments, the isolation structure116is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, a dielectric liner115is formed before the isolation structure116is formed, and the dielectric liner115is made of silicon nitride and the isolation structure116formed over the dielectric liner115is made of silicon oxide.

In some embodiments, a dummy gate dielectric layer120is formed over the fin structures104A and104B and the isolation structure116. In some embodiments, the dummy gate dielectric layer120is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO2, HfZrO, HfSiso, HITIO, HfAlO, or a combination thereof. In some embodiments, the dummy gate dielectric layer120formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

After the isolation structure116and the dummy gate dielectric layers120are formed, dummy gate structures118are formed across the fin structure104and extend over the isolation structure116, as shown inFIG.1Din accordance with some embodiments. The dummy gate structures118may be used to define the source/drain regions and the channel regions of the resulting semiconductor structure100. In some embodiments, source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context.

In some embodiments, the dummy gate structures118include dummy gate dielectric layers120and dummy gate electrode layers122. In some embodiments, the dummy gate electrode layers122include polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metals, or a combination thereof. In some embodiments, the dummy gate electrode layers122are formed using CVD. PVD, or a combination thereof.

In some embodiments, a dielectric layer123and a dielectric layer124are formed over the dummy gate structures118to act as hard mask layers. In some embodiments, the dielectric layer123is silicon oxide, and the dielectric layer124is silicon nitride.

The formation of the dummy gate structures118may include conformally forming a dielectric material as the dummy gate dielectric layers120in accordance with some embodiments. Afterwards, a conductive material may be formed over the dielectric material as the dummy gate electrode layers122, and the dielectric layer123and the dielectric layer124may be formed over the conductive material in accordance with some embodiments. Next, the dielectric material and the conductive material may be patterned through the dielectric layer123and the dielectric layer124to form the dummy gate structures118in accordance with some embodiments. In some embodiments, the excess dummy gate dielectric layers120may be removed using a plasma dry etching, a dry chemical etching, and/or a wet etching.

After the dummy gate structures118are formed, gate spacers126are formed along and covering opposite sidewalls of the dummy gate structure118and fin spacers128are formed along and covering opposite sidewalls of the source/drain regions of the fin structures104A and104B, as shown inFIG.1Ein accordance with some embodiments.

The gate spacers126may be configured to separate source/drain structures from the dummy gate structure118and support the dummy gate structure118, and the fin spacers128may be configured to constrain a lateral growth of subsequently formed source/drain structure and support the fin structure104.

In some embodiments, the gate spacers126and the fin spacers128are made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), and/or a combination thereof. The formation of the gate spacers126and the fin spacers128may include conformally depositing a dielectric material covering the dummy gate structure118, the fin structure104, and the isolation structure116over the substrate102, and performing an anisotropic etching process, such as dry plasma etching, to remove the dielectric layer covering the top surfaces of the dummy gate structure118, the fin structures104A and104B, and portions of the isolation structure116.

After the gate spacers126and the fin spacers128are formed, the source/drain regions of the fin structure104are recessed to form source/drain recesses130, as shown inFIG.1Fin accordance with some embodiments. More specifically, the first semiconductor material layers106and the second semiconductor material layers108not covered by the dummy gate structures118and the gate spacers126are removed in accordance with some embodiments.

In some embodiments, the fin structures104A and104B are recessed by performing an etching process. The etching process may be an anisotropic etching process, such as dry plasma etching, and the dummy gate structure118and the gate spacers126are used as etching masks during the etching process. In some embodiments, the fin spacers128are also recessed to form lowered fin spacers128′. In some embodiments, the dielectric liner115may be recessed together. In some embodiments, the dielectric liner115may not be recessed when recessing the fin structures104A and104B, and the lowered fin spacers128′ may be formed over the dielectric liner115.

After the source/drain recesses130are formed, the first semiconductor material layers106exposed by the source/drain recesses130are laterally recessed to form notches132.

In some embodiments, an etching process is performed on the semiconductor structure to laterally recess the first semiconductor material layers106of the fin structures104A and104B from the source/drain recesses130to form the notches132. In some embodiments, during the etching process, the first semiconductor material layers106have a greater etching rate (or etching amount) than the second semiconductor material layers108, thereby forming the notches132between adjacent second semiconductor material layers108. In some embodiments, the etching process is an isotropic etching such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and/or a combination thereof.

Next, inner spacers134are formed in the notches132between the second semiconductor material layers108, as shown inFIG.1Gin accordance with some embodiments. The inner spacers134are configured to separate the source/drain structures and the gate structures formed in subsequent manufacturing processes in accordance with some embodiments. In some embodiments, the inner spacers134are made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof.

After the inner spacers134are formed, source/drain structures136A and136B are formed in the source/drain recesses130, as shown inFIG.1Hin accordance with some embodiments. In some embodiments, the source/drain structures136A and136B are formed using an epitaxial growth process, such as MBE, MOCVD, VPE, other applicable epitaxial growth process, or a combination thereof. In some embodiments, the source/drain structures136are made of any applicable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof.

In some embodiments, the source/drain structures136A and136B are in-situ doped during the epitaxial growth process. For example, the source/drain structures136A and136B may be the epitaxially grown SiGe doped with boron (B). For example, the source/drain structures136may be the epitaxially grown Si doped with carbon to form silicon:carbon (Si:C) source/drain features, phosphorous to form silicon: phosphor (Si:P) source/drain features, or both carbon and phosphorous to form silicon carbon phosphor (SiCP) source/drain features. In some embodiments, the source/drain structures136A and136B are doped in one or more implantation processes after the epitaxial growth process.

After the source/drain structures136are formed, a contact etch stop layer (CESL)138is conformally formed to cover the source/drain structures136and the lowered fin spacers128′, and an interlayer dielectric (ILD) layer140is formed over the contact etch stop layers138, as shown inFIG.1lin accordance with some embodiments.

In some embodiments, the contact etch stop layer138is made of a dielectric materials, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the contact etch stop layers138may be conformally deposited over the semiconductor structure by performing CVD, ALD, other application methods, or a combination thereof.

The interlayer dielectric layer140may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and/or other applicable low-k dielectric materials. The interlayer dielectric layer140may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or other applicable processes.

In some embodiments, a mask layer141may be provided on the interlayer dielectric layer140to serve as a mask for subsequent processes. In some embodiments, the material of the mask layer141may include SiN or SiCN. In some embodiments, the mask layer141may be formed by chemical vapor deposition (CVD), physical vapor deposition. (PVD), atomic layer deposition (ALD), or other applicable processes.

In some embodiments, after the contact etch stop layer138and the interlayer dielectric layer140are deposited on the semiconductor structure, a planarization process such as CMP or an etch-back process may be performed to remove the dielectric layer123and the dielectric layer124. Afterwards, the interlayer dielectric layer140is further lowered, and then the mask layer141is formed over the interlayer dielectric layer140in accordance with some embodiments.

FIGS.1J,1K, and2Aare perspective cross-sectional views of intermediate stages of manufacturing a semiconductor structure100illustrated along the line A-A inFIG.1Iin accordance with some embodiments.FIGS.1K-1and2A-1are cross-sectional views of intermediate stages of manufacturing a semiconductor structure respectively corresponding to the steps inFIGS.1K and2Aillustrated along the line A-A inFIG.1I. As shown inFIG.1JandFIG.1K, the dummy gate structures118are removed to expose the fin structures104A and104B. For example, when the dummy gate electrode layers122are polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layers122.

In some embodiments, as shown inFIGS.2A and2A-1, an etching process is performed to selectively form concave portions143on opposite sidewalls of the second semiconductor material layers108. In some embodiments, the base fin structure105exposed from the isolation structure116is also recessed to form concave portions143′. In some embodiments, the concave portions143and the concave portions143′ have different sizes (e.g. heights). In some embodiments, the concave portions143and the concave portions143′ may have a depth between about 2 nm and about 10 nm.

In some embodiments, the etching process may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. In some embodiments, the etching process may be anisotropic.

FIGS.2B,2C,2D.2E, and2F are cross-sectional views of intermediate stages of manufacturing a semiconductor structure illustrated along the line A-A inFIG.1Iin accordance with some embodiments.FIGS.2B-1,2C-1,2D-1,2E-1, and2F-1are enlarged views ofFIGS.2B,2C.2D,2E, and2F in accordance with some embodiments, respectively.

As shown inFIGS.2B and2B-1, a first dielectric layer145is conformally formed on the fin structures104A and104B and the isolation structure116to surround the fin structures104A and104B, and in the concave portions143and143′, in accordance with some embodiments. Afterwards, a second dielectric layer147is conformally formed on the first dielectric layer145to surround the first dielectric layer145, in accordance with some embodiments. In some embodiments, the second dielectric layer147does not fully fill the concave portions143, but gaps148may be formed on the second dielectric layer147and corresponding to the concave portions143, such as arranged with the concave portions143in a first direction. In some embodiments, the second dielectric layer147fully fills the concave portions143. In some embodiments, the first dielectric layer145or the second dielectric layer147may be selectively omitted, depending on design requirement. In some embodiments, the materials of the first dielectric layer145and the second dielectric layer147may include dielectric materials, such as material with dielectric constant greater than 7. In some embodiments, the materials of the first dielectric layer145and the second dielectric layer147may include SiO2, SiN, SiCN, SiOC, SiOCN, or other applicable materials. In some embodiments, the first dielectric layer145and the second dielectric layer147may include different materials.

In some embodiments, the formation methods of the first dielectric layer145and the second dielectric layer147may include Molecular-Beam Deposition (MBD), Atomic Layer Deposition (ALD), Chemical vapor deposition (CVD), and the like.

Next, as shown inFIG.2CandFIG.2C-1, the second dielectric layer147outside the concave portions143is removed to form second spacer elements147′ in the concave portions143in accordance with some embodiments. In some embodiments, each of the second spacer elements147′ has curved surfaces147A and147B. In some embodiments, the curved surface147A faces away from the second semiconductor material layers108, and the curved surface147B faces the second semiconductor material layers108and in contact with the first dielectric layer145. During the removal of the second dielectric layer147, the first dielectric layer145is not removed, in accordance with some embodiments.

In some embodiments, the removal process of the second dielectric layer147may include any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. In some embodiments, the etching process may be anisotropic.

In some embodiments, the first dielectric layer145outside the concave portions143and143′ are removed, and the remaining first dielectric layer145becomes first dielectric layer145′ in the concave portions143and143′ and between the second spacer elements147′ and the second semiconductor material layers108, as shown inFIGS.2D and2D-1. In some embodiments, each of the first semiconductor material layers106has sidewalls106A and106B, and the first dielectric layer145′ and the second spacer elements147′ may partially protrude from the sidewalls106A and106B.

In some embodiments, the removal process of the first dielectric layer145may include any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. In some embodiments, the etching process may be anisotropic.

Next, as shown inFIGS.2E and2E-1, the first semiconductor material layers106, a portion of the second semiconductor material layers108, and a portion of the first dielectric layer145′ are removed to form nanostructures150A and150B (or may be collectively referred to as nanostructures150) with the second semiconductor material layers108in accordance with some embodiments.

In some embodiments the nanostructures150A and150B are laterally aligned with each other in the first direction. In some embodiments, gaps are formed between the nanostructures150A and150B. In some embodiments, the nanostructures150A and150B extend in a second direction. The second direction is different from the first direction. In some embodiments, a portion of the first dielectric layer145′ is removed to form first spacer elements149attached on sidewalls of the nanostructures150A and150B. In some embodiments, the first spacer element149and the second spacer element147′ may be collectively called as a dielectric spacer, and the first spacer element149is between the nanostructure150A or150B and the second spacer element147′ in a first direction which the gate structure151A or151B extends. In some embodiments, the entire first dielectric layer145′ is removed. In some embodiments, the height of the first dielectric layer145′ is greater than the height of the second spacer element147′ before the removal, and the height of the first spacer element149is less than the height of the second spacer element147′ after the removal.

In some embodiments, the removal process may include one or more etching processes. The first semiconductor material layers106may be removed by performing a selective wet etching process, such as APM (e.g., ammonia hydroxide-hydrogen peroxide-water mixture) etching process. For example, the wet etching process uses etchants such as ammonium hydroxide (NH&OH), TMAH, ethylenediamine pyrocatechol (EDP), and/or potassium hydroxide (KOH) solutions.

After the nanostructures150A and150B are formed, gate structures151A and151B are formed to respectively wrap around the nanostructures150A and150B, as shown inFIGS.2F-1and2F-2in accordance with some embodiments. The gate structures151A and151B respectively wrap around the nanostructures150A and150B (e.g. formed in the gaps between the nanostructures150A and150B) to form gate-all-around transistor structures in accordance with some embodiments. In some embodiments, each of the gate structures151A and151B includes an interfacial layer152, a gate dielectric layer153, and a gate electrode layer154.

In some embodiments, the interfacial layers152are oxide layers formed around the nanostructures150A and150B and on the top of the base fin structure105. In some embodiments, the interfacial layers152are formed by performing a thermal process.

In some embodiments, the gate dielectric layers153are formed over the interfacial layers152, so that the nanostructures150A and150B are surrounded (e.g. wrapped) by the gate dielectric layers153. In some embodiments, the nanostructures150A and150B and the gate dielectric layers153are separated by the first spacer element149and the interfacial layers152. In some embodiments, the gate dielectric layers153and the first spacer element149are separated by the interfacial layer152.

In some embodiments, the gate dielectric layers153are made of one or more layers of dielectric materials, such as HfO2, HfSiso, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, another suitable high-k dielectric material, or a combination thereof. In some embodiments, the gate dielectric layers153are formed using CVD, ALD, another applicable method, or a combination thereof.

In some embodiments, the gate electrode layers154are formed on the gate dielectric layer153. In some embodiments, the gate electrode layer154of the gate structures151A and151B may be formed concurrently or formed in separate processes, and may include identical or different materials. In some embodiments, the gate electrode layers154are made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAL, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof. In some embodiments, the gate electrode layers154are formed using CVD, ALD, electroplating, another applicable method, or a combination thereof. Other conductive layers, such as work function metal layers, may also be formed in the gate structures151A and151B, although they are not shown in the figures.

FIG.2Gis a cross-sectional view of intermediate stages of manufacturing a semiconductor structure illustrated along the line A-A inFIG.1Iin accordance with some embodiments. In some embodiments, a conductive layer157is formed over the gate structures151A and151B, and then an isolation structure155is formed penetrating the conductive layer157and between the gate structures151A and151B to divide (e.g., cut or separate) the gate structures151A and151B into sub-metal gate structures151A and151B, as shown inFIG.2G. For example, an opening is formed between the gate structures151A and151B, and then dielectric material is filled into the opening to form the isolation structure155. In some embodiments, the isolation structure155includes SiO2, SiON, SiN, SiC, SiOC, SiOCN, or low-k materials as needed.

In some embodiments, a dielectric layer159and a dielectric layer161are formed over the conductive layer157. In some embodiments, the dielectric layer159and the dielectric layer161may be formed by suitable deposition processes, such as CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

Since the dielectric spacers (including the first spacer element149and the second spacer element147′) are provided on sidewalls of the nanostructures150A and150B, less space is needed between the isolation structure155and the fin structures104A and104B, and the device density may be therefore increased, in accordance with some embodiments of the present disclosure. As a result, the capacitance of the semiconductor structure may be reduced, and the power efficiency may be increased, in accordance with some embodiments of the present disclosure.

FIG.2His a perspective view of a semiconductor structure100,FIG.2H-1is a cross-sectional view of the semiconductor structure illustrated along the line A-A inFIG.2H,FIG.2H-2is an enlarged view ofFIG.2H-1.FIG.2H-3is a cross-sectional view of the semiconductor structure illustrated along the line B-B inFIG.2H,FIG.2H-4is a cross-sectional view of the semiconductor structure illustrated along the line C-C inFIG.2H, andFIG.2Iis a top view of the semiconductor structure, in accordance with some embodiments of the present disclosure.

In some embodiments, as shown inFIGS.2H,2H-1, and2H-4, contacts160A and160B are formed over the source/drain structures136A and136B, and vias162are formed over the gate structure151A. In some embodiments, the contacts160A and160B and vias162are made of a conductive material including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantulum (Ta), titanium nitride (TIN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantulum carbide (TaC), tantulum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials, or a combination thereof. In some embodiments, the contacts160A and160B and vias162may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition processes.

In some embodiments, as shown inFIG.2H-1, an additional gate structure is further shown, and the distance D1between the nanostructures150A and150B is between about 30 nm and about 46 nm. In some embodiments, the distance D2between the nanostructures150A and150B and the isolation structure155is less than about 7 nm. Therefore, space between the gate structures151A and151B and the space between the gate structure151A and151B and the isolation structure155may be reduced to enhance the performance of the semiconductor structure100.

In some embodiments, as shown inFIG.2H-2, the height H1of the first spacer element149in a third direction is between about 0.5 nm and about 2 nm. In some embodiments, the height H2of the second spacer element147′ in the third direction is between about 3 am and about 8 nm. In some embodiments, the third direction is different from the first direction and the second direction. In some embodiments, the height H3of the nanostructures150A or150B is between about 3 am and about 8 nm. In some embodiments, the height H2is less than the heights H1and H3. In some embodiments, the gate dielectric layer153includes extending portions153E extending between the first nanostructure150A or150B and the second spacer element147′, and a length LI of the extending portion153E is between about 1 nm and about 3 nm. In some embodiments, the length LI of the extending portion153E is less than 1 nm. In some embodiments, the first spacer element149is between two extending portions153E. In some embodiments, the extending portions153E may be used for short channel effect (SCE) control. In some embodiments, the thickness T1of the first spacer element149is between about 2 nm and about 5 nm. In some embodiments, the thickness T2of the second spacer element147′ is between about 2 nm and about 10 nm. In some embodiments, the thickness T3of the gate dielectric layer153is between about 0.5 nm and about 2 nm.

As shown inFIG.2I, the gate electrode layer154of the gate structures151A or151B extend in a first direction, and the nanostructures150and the isolation structures155extend in a second direction, and the first direction and the second direction are different (e.g. substantially perpendicular), in accordance with some embodiments of the present disclosure.

In some embodiments, the first spacer element149and the second spacer element147′ may be selectively formed on specific sides of the nanostructures150A or150B. For example,FIGS.3A and3Bare perspective cross-sectional views of intermediate stages of manufacturing a semiconductor structure illustrated along the line A-A inFIG.1Iafter the step shown inFIG.1Kin accordance with some embodiments.FIGS.3A-1,3B-1,3C,3D,3E,3F,3G, and3Hare cross-sectional views of intermediate stages of manufacturing a semiconductor structure illustrated along the line A-A inFIG.1Iafter the step inFIG.3Bin accordance with some embodiments.FIGS.3C-1,3D-1-3E-1,3F-1, and3G-1are enlarged views ofFIGS.3C,3D-3E,3F, and3G in accordance with some embodiments, respectively.

As shown inFIGS.3A and3A-1, a patterned photoresist layer163is formed on the fin structures104A and104B after removing the dummy gate dielectric layers120to cover a portion of the fin structures104A and104B. For example, the fin structure104A (including the first semiconductor material layers106and the second semiconductor material layers108) has a sidewall104A1facing away from the fin structure104B and a sidewall104A2facing the fin structure104B, and the fin structure104B has a sidewall104B1facing away from the fin structure104A and a sidewall104B2facing the fin structure104A, in accordance with some embodiments. In some embodiments, the patterned photoresist layer163covers the sidewalls104A1and104B2, and the sidewalls104A2and104B1are exposed from the patterned photoresist layer163. In some embodiments, the material of the patterned photoresist layer163may include SiN or SiCN. In some embodiments, the patterned photoresist layer163may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or other applicable processes.

In some embodiments, as shown inFIGS.3B and3B-1, an etching process is performed to selectively form concave portions143on sidewalls of the second semiconductor material layers108, such as recessing the second semiconductor material layers108from the sidewalls104A2and104B1. In some embodiments, the base fin structure105exposed from the isolation structure116is also recessed to form concave portions143A′ and143B′ on the fin structures104A and104B, respectively. In some embodiments, the concave portions143A and43B and the concave portions143A′ and143B′ have different sizes (e.g. heights). In some embodiments, the concave portions143A,143B,143A′, and143B′ may have a depth between about 2 am and about 10 nm.

In some embodiments, the etching process may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. In some embodiments, the etching process may be anisotropic.

In some embodiments, as shown inFIG.3CandFIG.3C-1, the patterned photoresist layer163is removed after recessing the second semiconductor material layers108from the sidewalls104A2and104B1, and then a first dielectric layer145is conformally formed on the fin structures104A and104B and the isolation structure116, and in the concave portions143A,143A′,143B, and143B′, in accordance with some embodiments. Afterwards, a second dielectric layer147is conformally formed on the first dielectric layer145, in accordance with some embodiments. In some embodiments, the second dielectric layer147does not fully fill the concave portions143A and143B, but gaps148may be formed on the second dielectric layer147and corresponding to the concave portions143A and143B, such as arranged with the concave portions143A and143B in the first direction. In some embodiments, the first dielectric layer145or the second dielectric layer147may be selectively omitted, depending on design requirement. In some embodiments, the materials of the first dielectric layer145and the second dielectric layer147may include dielectric materials, such as material with dielectric constant greater than 7. In some embodiments, the materials of the first dielectric layer145and the second dielectric layer147may include SiO2, SiN, SiCN, SiOC, SiOCN, or other applicable materials. In some embodiments, the first dielectric layer145and the second dielectric layer147may include different materials.

In some embodiments, the formation methods of the first dielectric layer145and the second dielectric layer147may include Molecular-Beam Deposition (MBD), Atomic Layer Deposition (ALD), Chemical vapor deposition (CVD), and the like.

Next, as shown inFIG.3DandFIG.3D-1, the second dielectric layer147outside the concave portions143A,143A′,143B, and143B′ is removed to form second spacer elements147′ in the concave portions143A,143A′,143B, and143B′ in accordance with some embodiments. In some embodiments, each of the second spacer elements147′ has curved surfaces147A and147B. In some embodiments, the curved surface147A faces away from the second semiconductor material layers108, and the curved surface147B faces the second semiconductor material layers108and in contact with the first dielectric layer145. During the removal of the second dielectric layer147, the first dielectric layer145is not removed, in accordance with some embodiments.

In some embodiments, the removal process of the second dielectric layer147may include any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. In some embodiments, the etching process may be anisotropic.

In some embodiments, the first dielectric layer145outside the concave portions143and143′ are removed, and the remaining first dielectric layer145becomes first dielectric layer145′ in the concave portions143and143′ and between the second spacer elements147′ and the second semiconductor material layers108, as shown inFIGS.3E and3E-1. In some embodiments, each of the first semiconductor material layers106has sidewalls106A and106B, and the first dielectric layer145′ and the second spacer elements147′ are partially protrude from the sidewall106A.

In some embodiments, the removal process of the first dielectric layer145may include any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. In some embodiments, the etching process may be anisotropic.

Next, as shown inFIGS.3F and3F-1, the first semiconductor material layers106are removed to form nanostructures150A and150B with the second semiconductor material layers108in accordance with some embodiments. In some embodiments, a portion of the first dielectric layer145′ is removed to form first spacer elements149. In some embodiments, the entire first dielectric layer145′ is removed. In some embodiments, the removal process may include one or more etching processes. The first semiconductor material layers106may be removed by performing a selective wet etching process, such as APM (e.g., ammonia hydroxide-hydrogen peroxide-water mixture) etching process. For example, the wet etching process uses etchants such as ammonium hydroxide (NH4OH), TMAH, ethylenediamine pyrocatechol (EDP), and/or potassium hydroxide (KOH) solutions.

After the nanostructures150A and150B are formed, gate structures151A and151B are formed to respectively wrap around the nanostructures150A and150B, as shown inFIGS.3G and3G-1in accordance with some embodiments. The gate structures151A and151B respectively wrap around the nanostructures150A and150B to form gate-all-around transistor structures in accordance with some embodiments. In some embodiments, each of the gate structures151A and151B includes an interfacial layer152, a gate dielectric layer153, and a gate electrode layer154.

In some embodiments, the interfacial layers152are oxide layers formed around the nanostructures150A and150B and on the top of the base fin structure105. In some embodiments, the interfacial layers152are formed by performing a thermal process.

In some embodiments, the gate dielectric layers153are formed over the interfacial layers152, so that the nanostructures150A and150B are surrounded (e.g. wrapped) by the gate dielectric layers153. In some embodiments, the nanostructures150A and150B and the gate dielectric layers153are separated by the first spacer element149and the interfacial layers152.

In some embodiments, the gate dielectric layers153are made of one or more layers of dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO. HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, another suitable high-k dielectric material, or a combination thereof. In some embodiments, the gate dielectric layers153are formed using CVD, ALD, another applicable method, or a combination thereof.

In some embodiments, the gate electrode layers154are formed on the gate dielectric layer153. In some embodiments, the gate electrode layer154of the gate structures151A and151B may be formed concurrently or formed in separate processes, and may include identical or different materials. In some embodiments, the gate electrode layers154are made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof. In some embodiments, the gate electrode layers154are formed using CVD. ALD, electroplating, another applicable method, or a combination thereof. Other conductive layers, such as work function metal layers, may also be formed in the gate structures151A and151B, although they are not shown in the figures.

FIG.3His a cross-sectional view of intermediate stages of manufacturing a semiconductor structure illustrated along the line A-A inFIG.1Iin accordance with some embodiments. In some embodiments, a conductive layer157is formed over the gate structures151A and151B, and then an isolation structure155is formed penetrating the conductive layer157and between the gate structures151A and151B to divide (e.g., cut or separate) the gate structures151A and151B into sub-metal gate structures151A and151B, as shown inFIG.3H. For example, an opening is formed between the gate structures151A and151B, and then dielectric material is filled into the opening to form the isolation structure155. In some embodiments, the isolation structure155includes SiO2, SiON, SiN, SiC, SiOC, SiOCN, or low-k materials as needed.

In some embodiments, a dielectric layer159and a dielectric layer161are formed over the conductive layer157. In some embodiments, the dielectric layer159and the dielectric layer161may be formed by suitable deposition processes, such as CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

Afterwards, in some embodiments, contacts160A and160B are formed over the source/drain structures136A and136B, and vias162are formed over the gate structure151A to form the semiconductor structure100, which is similar to the structure shown inFIG.2H, and the details are not repeated.

In some embodiments, the extending portions153E of the gate dielectric layer153may be omitted. For example,FIG.4is an enlarged view of the nanostructure150in accordance with some embodiments. As shown inFIG.4, the gate dielectric layer153does not extend between the second spacer element147′ and the nanostructure150, and the interfacial layer152surrounds the nanostructure150, in accordance with some embodiments.

In some embodiments, the dielectric spacer (including the first spacer element149and the second spacer element147′) may be formed on one of two adjacent fin structures (e.g. the fin structure104A), and does not form on another fin structure (e.g. the fin structure104B).FIG.5is a cross-sectional view of intermediate stages of manufacturing a semiconductor structure illustrated along the line A-A inFIG.1Iin accordance with some embodiments. Such structure may be obtained by forming the patterned photoresist layer163on the fin structures104A and104B (e.g. seeFIG.3A) to cover the sidewalls104A1,104B1, and104B2, and the sidewall104A2may be exposed from the patterned photoresist layer163, followed by subsequent processes inFIGS.3B-3H, in accordance with some embodiments of the present disclosure. As shown inFIG.5, the first spacer element149and the second spacer element147′ form on the nanostructures150A, rather than form on the nanostructures150B, in accordance with some embodiments. In such embodiment, the isolation structure155may be formed adjacent to the nanostructures150A. For example, the distance SI between the nanostructure150A (the fin structure104A) and the isolation structure155may be less than the distance S2between the nanostructure150B (the fin structure104B) and the isolation structure155, so the space between the nanostructure150A and the isolation structure155may be reduced for miniaturization, in accordance with some embodiments.

In summary, a semiconductor structure and a method for manufacturing the same are provided in some embodiments. By forming dielectric spacers in the concave portions of the nanostructures, the distance between the isolation structure and the nanostructure may be reduced, the capacitance may be reduced, and the device density and the power efficiency may be enhanced, in accordance with some embodiments of the present disclosure.

A method for manufacturing a semiconductor structure is provided in some embodiments of the present disclosure. The method includes forming a fin structure protruding from a substrate, wherein the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked, forming a dummy gate structure across the fin structure, forming a gate spacer on the sidewall of the dummy gate structure, removing the dummy gate structure to expose the fin structure, partially removing the second semiconductor material layers to form concave portions on sidewalls of the second semiconductor material layers, forming dielectric spacers in the concave portions, removing the first semiconductor material layers to form gaps, and forming a gate structure in the gaps to wrap around the second semiconductor material layers and the dielectric spacers.

A method for manufacturing a semiconductor structure is provided in some embodiments of the present disclosure. The method includes the following steps. The method includes alternately stacking first semiconductor material layers and second semiconductor material layers to form a semiconductor stack over a substrate. The method includes patterning the semiconductor stack to form a first fin structure and a second fin structure. The method includes recessing the second semiconductor material of the first fin structure and the second fin structure to form first concave portions in the first fin structure and second concave portions in the second fin structure. The method includes forming a first dielectric layer surrounding the first fin structure and the second fin structure. The method includes forming a second dielectric layer surrounding the first dielectric layer. The method includes partially removing the first dielectric layer and the second dielectric layer to form first dielectric spacers in the first concave portions and to form second dielectric spacers in the second concave portions. The method includes removing the first semiconductor material layers. The method includes forming a gate structure wrapped around the second semiconductor material layers and the dielectric spacers.

A semiconductor structure is provided in some embodiments of the present disclosure. The semiconductor structure includes a substrate, a gate structure, a first nanostructure, a source/drain structure, and a first dielectric spacer. The gate structure extends over the substrate in a first direction. The first nanostructure extends in a second direction, wherein the second direction is different from the first direction. The source/drain structure is formed adjacent to the gate structure over the substrate. The first dielectric spacer is attached to the sidewall of the first nanostructure. The first dielectric spacer includes a first spacer element in contact with the first nanostructure, and a second spacer element in contact with the first spacer element. In a cross-sectional view, the first spacer element is between the first nanostructure and the second spacer element in the first direction, and the height of the first spacer element is less than the height of the first nanostructure and the height of the second spacer element in the third direction. The third direction is different from the first direction and the second direction. The first nanostructure and the first dielectric spacer are wrapped by the gate structure.