Buffer amplifier

A buffer amplifier includes an input stage circuit, an output stage circuit and a bias circuit, providing a buffered output signal at an output terminal according to an input signal applied to a first input terminal. The input stage circuit generates four control signals in response to the input signal when the logic level of the buffered output signal is opposite to that of the input signal. The output stage circuit includes four output transistors, wherein the first and second output transistor of a first type are provided for discharge in response to a first control signal and a second control signal, and the third and fourth output transistor of a second type are provided for charge in response to a third control signal and a fourth control signal. The bias circuit is used for determining the first, second, third and fourth control signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a buffer amplifier, and more particularly to a buffer amplifier for use in a source driver of a display panel.

2. Description of the Related Art

Nowadays, flat display panels, such as liquid crystal display (LCD) panels, are widely used in electronic devices due to their characteristics of lightweight, thinness and low power consumption. Generally, gate drivers and source drivers are arranged to drive the liquid crystal display panels through a plurality of gate lines and source lines. The gate drivers provide turn-on voltages to respective gate lines sequentially, and then the source drivers supply gray-level voltages, which are associated with image data to be displayed, to corresponding source lines. Further, a source driver generally comprises an output buffer amplifier to drive each panel load, e.g., a load capacitor of a display panel, to a desired state of charge/discharge according to corresponding gray-level voltages.

However, as the display resolution of the display panel is increased, the increased capacitance of each load capacitor substantially deteriorates the charge/discharge capability of the output buffer amplifier, thereby resulting in an undesirable increase of the rising time and the falling time of the load capacitor. Thus, the degradation of the falling time may negatively influence the transition time required for charging/discharging of the load capacitor.

Accordingly, there is a need in the art for an improved and optimized buffer amplifier for use in a source driver of a large-scale display panel, so as to improve the driving capability of the source driver and shorten the rising time and the falling time required for charging/discharging each load capacitor.

BRIEF SUMMARY OF THE INVENTION

According to an embodiment, the invention provides a buffer amplifier having a first input terminal, a second input terminal and an output terminal comprises an input stage circuit, an output stage circuit and a bias circuit. The output terminal is coupled back to the second input terminal, providing a buffered output signal at the output terminal as according to an input signal applied to the first input terminal. The input stage circuit is coupled between the input terminals and the output terminal for generating a four control signals in response to the input signal when the logic level of the buffered output signal is at a logic level opposite to that of the input signal. The output stage circuit, which is coupled to the input stage circuit, comprises a first output transistor and a second output transistor of a first type and a third output transistor and fourth output transistor of a second type. The first output transistor and the second output transistor comprise sources coupled together to receive a first supply voltage, gates respectively coupled to receive a first control signal and a second control signal, and drains coupled together at the output terminal. The third output transistor and the fourth output transistor comprise sources coupled together to receive a second supply voltage, gates respectively coupled to receive a third control signal and a fourth control signal, and drains coupled together at the output terminal. The bias circuit, which is coupled between the input stage circuit and the output stage circuit, comprises a plurality of current mirror circuits for determining the first, second, third and fourth control signal.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a schematic diagram illustrating a display system10according to an embodiment of the invention.

As shown inFIG. 1, the display system10comprises a source driver102, a gate driver104, a timing controller120, and a display panel106, such as a thin-film transistor liquid crystal display (TFT-LCD) panel. According to this embodiment, the display panel106comprises a plurality of display units, e.g., a display unit108, arranged at intersections by columns of gate lines G1, G2. . . GM, and rows of source lines S1, S2. . . SN, to form a display matrix. During operation, the timing controller120provides timing signals132and134respectively for the source driver102and the gate driver104. For example, image data to be displayed is sequentially written to the display units row by row by the source driver102in response to the timing signal132involving a horizontal clock signal H_clock and a horizontal synchronization signal H_sync provided by the timing controller120.

In addition, the display unit108comprises a liquid crystal unit122, a thin film transistor TFT, and a storage capacitor CS.

As shown inFIG. 1, the gate and drain of the transistor TFT are respectively connected to a gate line GMand a source line SN. In this case, the transistor TFT serves as a switch controlled by a turn-on voltage applied from the gate driver104to the gate line GM, so as to allow a corresponding gray-level voltage from the source driver102to be written into the liquid crystal unit122. The gray-level voltages are associated with the image data to be displayed. The capacitor CSfunctions as a load capacitor for alternatively being charged or discharged in response to a voltage difference between the corresponding gray-level voltage of the source line SNand a common voltage VCOM. Further, the capacitor CSmay not be coupled to the common voltage VCOMaccording to other embodiments. The liquid crystal unit122is connected in parallel to the capacitor CS. As a result, the liquid crystal unit122displays the image data in response to the voltage difference.

FIG. 2is a schematic diagram illustrating a source driver202according to the embodiment ofFIG. 1.

Referring toFIG. 2, the source driver202comprises a shift register module216, a latch module218, a level shifter220, a digital-to-analog (D/A) converter222and a buffer amplifier230.

During operation, the shift register module216includes a plurality of shift registers for sequentially generating a shift pulse232required by a RGB signal214, which is associated with image data to be displayed, according to the timing signal132output from the timing controller120as shown inFIG. 1. According to the embodiment, the timing signal132includes the horizontal clock signal H_clock and the horizontal synchronization signal H_sync. The latch module218includes a set of sample latches for latching the RGB signal214in synchronization with the shift pulse232. Further, the latch module218includes a set of hold latches for latching the latched RGB signal214in synchronization with a hold signal234. Next, the level shifter220converts the level of the output from the latch module218from a digital signal with low voltage to a digital signal with high voltage. Then, the digital-to-analog (D/A) converter222generates an analog signal Sdatabased on the digital signal transmitted from the level shifter220. Following, the analog signal Sdatais supplied to the buffer amplifier230. The buffer memory118is arranged for receiving the image data to be displayed. The shift register module116provides a source line driving signal Sinputaccording to the image data from the buffer memory118and the timing signal from the timing controller120. During operation, the shift register module116comprises a plurality of shift registers for sequentially outputting a pulse to serve as the source line driving signal Sinput. The buffer amplifier230receives the signal Sdataand generates a buffered output signal Sout, which may applied to a corresponding source line, such as S1, S2. . . SN, as shown inFIG. 1.

Specifically, the buffer amplifier230is utilized to increases the driving capability of the analog signal Sdata, so as to successfully drive each panel load of the display unit to write the image data to be displayed.

According to an embodiment, the buffered output signal Soutis used to drive the display unit108inFIG. 1to a logic level substantially the same as the logic level of the signal Sdata. In this case, the display unit108may be at a high logic level, a low logic level or in transition between the logic levels. In particular, for a large-scale or high resolution display panel106, the buffer amplifier230allows the display unit108to be charged or discharged more rapidly during a low-to-high or high-to-low transition, so as to improve the falling time characteristics.

FIG. 3is a schematic diagram illustrating a buffer amplifier330according to the embodiment ofFIG. 2.

Referring toFIG. 3, the buffer amplifier330has a first input terminal INP, a second input terminal INN and an output terminal OUT. The output terminal OUT is coupled back to the second input terminal INN, providing a buffered output signal Soutat the output terminal OUT as according to a signal Sdataapplied to the first input terminal INN.

In this illustrated embodiment, the buffer amplifier330comprises an input stage circuit302, an output stage circuit304and a bias circuit306. Note that the buffer amplifier330is configured to function as a unity-gain buffer amplifier, i.e., the buffered output signal Soutis substantially equal to the signal Sdata, so as to economize unnecessary driving power.

As shown inFIG. 3, the input stage circuit302is coupled between the two input terminals INP and INN, and the output terminal OUT. When the logic level of the buffered output signal Soutat the output terminal OUT is at a logic level opposite to that of the signal Sdataat the first input terminal INP, the input stage circuit302generates four control signals310,312,314and316in response to the signal Sdataof the first input terminal INP.

Further, the input stage circuit302comprises three input PMOS transistors P1, P2and INVP1and three input NMOS transistors N1, N2and INVN2. During operation, the input transistors P1and INVP1are used for respectively operating the output transistors N10and DN10, and the two input NMOS transistors N1and INVN2are used for respectively operating the output transistors P10and DP10. The sources of the input transistors P1and INVP1are coupled together to receive the second supply voltage, e.g., VDD, gates thereof are coupled together to receive the signal Sdata, and drains thereof are respectively coupled to the gates of the output transistor N10and DN10. Similarly, the input transistors N1and INVN2comprise drains respectively coupled to the gates of the output transistors P10and DP10, gates coupled together to receive the signal Sdata, and sources coupled together to receive the first supply voltage, e.g., VSS. The sources of the input transistor N2and P2are respectively coupled to receive the first and second supply voltage, such as VSSand VDD, and the gates thereof are coupled to receive the buffered output signal Soutfrom the second input terminal INN.

It is noted that the input transistors P1and P2are of the same size (for example, length to width ratio), which is larger than the input transistor INVP1. In addition, the input transistors N1and N2are of the same size, which is larger than the input transistor INVN2.

Moreover, the output stage circuit304is coupled to the input stage circuit302. According to the embodiment ofFIG. 3, the output stage circuit304, which is a class AB-type push-pull amplification stage, has a first output NMOS transistor N10, a second output NMOS transistor DN10, a third output PMOS transistor P10and a fourth output PMOS transistor DP10.

More specifically, the NMOS transistors N10and DN10and the PMOS transistors P10and DP10are arranged in a push-pull configuration. In detail, the first and second output transistor N10and DN10comprise sources coupled together to receive a first supply voltage, gates respectively coupled to receive the first and second control signal310and312, and drains coupled together at the output terminal OUT. Similarly, the third and fourth output transistor P10and DP10comprise sources coupled together to receive a second supply voltage, gates respectively coupled to receive the third and fourth control signal314and316, and drains coupled together at the output terminal OUT.

Note that the first supply voltage defined by a lower-voltage supply rail, e.g., VSSinFIG. 3, is lower than the second supply voltage defined by an upper-voltage supply rail, e.g., VDD, so that the buffer amplifier330operates on rail-to-rail supply voltages.

Further, according to the illustrated embodiment ofFIG. 3, the bias circuit306coupled between the input stage circuit302and the output stage circuit304comprises a first current mirror circuit322and a second current mirror circuit324for determining the first, second, third and fourth control signal310,312,314and316. In this case, the current mirror circuits322and324are provided to modify the voltage at their respective output terminal.

In analyzing the bias circuit306, a set of NMOS transistors N4, N5and INVN1form the current mirror circuit324and another set of PMOS transistors P4, P5and INVP2form the current mirror circuit322. The sources of the transistors N4, N5and INVN1are coupled together to receive the first supply voltage, e.g., VSS, the gates thereof are coupled together to receive a bias voltage, and the drains thereof are respectively coupled to the drain of the input transistor P2, the drain of the input transistor P1at an output node VN, and the drain of the input transistor INVP1at an output node INV1. The sources of the transistors P4, P5and INVP2are coupled together to receive the second supply voltage, e.g., VDD, the gates thereof are coupled together to receive the bias voltage, and the drains thereof are respectively coupled to the drain of the input transistor N2, the drain of the input transistor N1at an output node INV2, and the drain of the input transistor INVN2at an output node VP.

Note that the bias voltage is supplied by a circuit consisting of PMOS transistors P8and P9and NMOS transistors N8and N9with external input voltages VBOP and VBON, thereby allowing the buffer amplifier330to operate over a different voltage range. Further, two transistors P3and N3supplied with external input voltages VBP and VBN are used to provide constant bias currents. In one embodiment, four transistors PD2, PD3, ND2and ND3may additionally provided as four switches for simultaneously activating or de-activating the input stage circuit302, the bias circuit306and the output stage circuit304according to two switch signals SW and SWB.

The detailed operation of the buffer amplifier330is described in the following.

According to an embodiment, assuming that the load capacitor of the display unit108is fully charged, then the buffered output signal Soutof a HIGH logic level at the output terminal OUT is fed to the second input terminal INN. When the signal Sdataof a relative LOW logic level is being applied to the first input terminal INP, the input transistors P1and INVP1are respectively turned ON. Then, the control signals310and312are respectively modified at the output nodes VN and INV1according to voltage drops across the transistors N5and INVN1coupled thereto. More specifically, the current flows through the transistor N5is increased, so as to increase the drain-source voltage VDSof the transistor N5. Similarly, the increased current flows through the transistor INVN1directs the drain-source voltage VDSof the transistor INVN1to increase substantially. The two output nodes VN and INV1are pulled high to the HIGH logic level. Accordingly, both of the output transistors N10and DN10are turned on to discharge the load capacitor of the display unit108. Thus, the two discharge paths result in a faster discharge of the load capacitor and improve the falling time characteristics of the buffer amplifier330. When the logic level of the load capacitor present on the output terminal OUT is gradually changed from HIGH to LOW, i.e., the discharge transition is accomplished, the input transistor P2is turned on. At this time, because the size of either the input transistor P1or P2is substantially larger than the input transistor INVP1, there will be less current flowing through the input transistor INVP1.

According to another embodiment, in the case where the load capacitor of the display unit108is being charged, the buffered output signal Soutis at the LOW logic level at the output terminal OUT and fed back to the second input terminal INN. The signal Sdataof the HIGH logic level at the first input terminal INP is activated to turn on the input transistors N1and INVN2. In this case, the control signals314and316are respectively adjusted at the output nodes VP and INV2according to voltage drops across the transistors P5and INVP2coupled thereto. More specifically, the input transistors N1and INVN2are turned on to increase the current flowing through the transistors P5and INVP2. At this time, the drain-source voltages VDSof the transistors P5and INVP2are increased. Thus, the two output nodes VP and INV2are pulled low to the LOW logic level due to the increased stored voltage across the transistors P5and INVP2. Accordingly, both of the output transistors P10and DP10are turned on to charge the load capacitor of the display unit108. As a result, the increased dynamic currents further minimize the rising time characteristics of the buffer amplifier330. When the logic level of the load capacitor present on the output terminal OUT is gradually changed from LOW to HIGH, i.e., the charge transition is accomplished, the input transistor N2is turned on. Because the size of either the input transistor N1or N2is substantially larger than the input transistor INVN2, there will be less current flowing through the input transistor INVN2.

As such, the buffer amplifier of the invention allows the load capacitor of the display unit to be charged/discharged more quickly during the charge/discharge transition. Thus, for a large-scale or high-resolution display panel, during the transition of the signal Sdata, the falling time and driving capability are significantly improved. Further, the buffer amplifier of the invention can also hinder unnecessary power consumption after the process of charging/discharging the load capacitor is completed.