BURIED BIT LINE STRUCTURE, METHOD FOR FABRICATING BURIED BIT LINE STRUCTURE, AND MEMORY

Embodiments disclose a buried bit line structure, a method for fabricating the buried bit line structure, and a memory. The buried bit line structure includes: a substrate having a bit line trench; a bit line metal filled in the bit line trench; and a bit line contact filled in the bit line trench and positioned on the bit line metal, where an arc-shaped contact surface is provided between the bit line contact and the bit line metal. By setting a contact surface between the bit line contact and the bit line metal to be the arc-shaped contact surface, a contact area between the bit line contact and the bit line metal is increased, electrical conductivity of the bit line structure is enhanced.

TECHNICAL FIELD

Embodiments of the present disclosure relate to the field of semiconductor manufacturing, and more particularly, to a buried bit line structure, a method for fabricating the buried bit line structure, and a memory.

BACKGROUND

With miniaturization of processes for fabricating a semiconductor device, a bit line structure may also be miniaturized. It is needed to form a bit line trench having a smaller line width by means of photoetching to implement miniaturization of the bit line structure, the bit line structure in the prior art not only easily leads to inclination and collapse of material layers on the bit line trench, but also easily leads to damage and poor contact of these material layers, thus resulting in final failure of the semiconductor device.

Therefore, it is a technical problem to be solved to provide a bit line structure which is not easily damaged in a manufacturing process and has a large conductive contact area, and a method for manufacturing the bit line structure.

SUMMARY

A technical problem to be solved by embodiments of the present disclosure is to provide a buried bit line structure, a method for fabricating the buried bit line structure, and a memory.

To solve the above problem, the embodiments of the present disclosure provide a buried bit line structure, which includes: a substrate having a bit line trench; a bit line metal filled in the bit line trench; and a bit line contact filled in the bit line trench and positioned on the bit line metal, where an arc-shaped contact surface is provided between the bit line contact and the bit line metal.

The embodiments of the present disclosure also provide a method for fabricating the buried bit line. The method comprises: providing a substrate and forming a bit line trench in the substrate; filling a bit line metal in the bit line trench; and forming a bit line contact on the bit line metal, where an arc-shaped contact surface is provided between the bit line contact and the bit line metal.

The embodiments of the present disclosure also provide a memory, which comprises a buried bit line structure. The buried bit line structure comprises: a substrate having a bit line trench; a bit line metal filled in the bit line trench; and a bit line contact positioned on the bit line metal, where an arc-shaped contact surface is provided between the bit line contact and the bit line metal.

DETAILED DESCRIPTION

The buried bit line structure, the method for fabricating the buried bit line structure, and the memory provided by embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

FIG.1is a schematic diagram of a buried bit line structure according to an embodiment of the present disclosure. The buried bit line structure comprises: a substrate1having a bit line trench2; a bit line metal3filled in the bit line trench2; and a bit line contact4filled in the bit line trench2and positioned on the bit line metal3, where an arc-shaped contact surface is provided between the bit line contact4and the bit line metal3. By increasing a contact area between the bit line contact4and the bit line metal3, electrical conductivity of the bit line structure is enhanced.

In some embodiments, the substrate1may be, for example, a semiconductor substrate such as a Si substrate, a Ge substrate, a SiGe substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, etc. The semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc. The semiconductor substrate may also be a stack structure, such as Si/SiGe, etc. The semiconductor substrate may also be other epitaxial structures, such as silicon germanium on insulator (SGOI), and so on. The substrate1may be a single substrate structure, and of course may also include other semiconductor structures, such as buried word lines, isolation structures, doped structures, etc., which are not particularly limited and may be adjusted according to required structures.

In some embodiments, the bit line trenches2are a plurality of grooves formed by means of downward etching along the substrate1. An etching width of each of these grooves may be 10 nm to 20 nm, such as 10 nm, 12 nm, or 18 nm. An etching depth of each of these grooves may be, for example, 1 to 2 times such as 1.5 times or 2 times the width of the groove. Further, for example, the etching depth when the bit line trench2is formed by means of downward etching may refer to that an insulating layer (not shown in the figure) on the substrate1such as the silicon (Si) substrate and the buried word line is etched downwards to a ½ to ⅘ position such as the ½ or ⅗ position of the insulating layer. Within the above range, the bit line metal3and the bit line contact4may be filled in the bit line trench2to form the buried bit line structure in the substrate1. In this way, the height of the bit line structure is reduced, and the stability of the bit line structure is improved, which may avoid the collapse due to a greater height of a material layer on the bit line trench2, extending outside the substrate1subsequently. A material of the bit line metal3may be, for example, tungsten, copper, aluminum, nickel, cobalt, etc. The bit line contact4leads out an electrical signal of the bit line metal3. The bit line contact4may be, for example, tungsten and/or polysilicon.

In some other embodiments, the width of the bit line metal is further expanded to avoid collapse of the material layer during the manufacturing processes.FIG.2is a schematic diagram of a buried bit line structure according to another embodiment of the present disclosure. The bit line trench2comprises: a first trench segment21, where the bit line metal3is filled in the first trench segment21; and a second trench segment22, where the bit line contact4is filled in the second trench segment22, the second trench segment22extends along a direction of the first trench segment21, and a cross-sectional area of the second trench segment22is smaller than a cross-sectional area of the first trench segment21. A projection of the bit line contact4on the substrate1is positioned within a projection of the bit line metal3on the substrate1.

FIG.3is a schematic diagram of a buried bit line structure according to yet another embodiment of the present disclosure. The buried bit line structure comprises: a substrate1having a bit line trench2; a bit line metal3filled in the bit line trench2; and a bit line contact4filled in the bit line trench2and positioned on the bit line metal3, where an arc-shaped contact surface is provided between the bit line contact4and the bit line metal3. In this embodiment, the buried bit line structure further includes: a first barrier layer6positioned in the bit line trench, and a second barrier layer5positioned on a surface of the first barrier layer6, where the bit line metal3covers a bottom wall and a side wall of the second barrier layer5. The barrier layer5or the barrier layer6may be arranged to prevent the bit line metal3from diffusing to the substrate1. A material of the first barrier layer6may be, for example, silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), and a low-dielectric-constant material. The second barrier layer5is positioned between the first barrier layer6and the bit line metal3, and a material of the second barrier layer6may be other metal nitrides such as titanium nitride (TiN) or tantalum nitride (TaN).

FIG.4is a schematic diagram of a buried bit line structure according to still another embodiment of the present disclosure. The buried bit line structure comprises: a substrate1having a bit line trench2; a bit line metal3filled in the bit line trench2; a bit line contact4filled in the bit line trench2and positioned on the bit line metal3, where an arc-shaped contact surface is provided between the bit line contact4and the bit line metal3; a first barrier layer6positioned in the bit line trench; and a second barrier layer5positioned on a surface of the first barrier layer6, where the bit line metal3covers a bottom wall and a side wall of the second barrier layer5. In this embodiment, the buried bit line structure further comprises a spacer7, which is filled in the bit line trench2and is positioned on the bit line contact4. The spacer7at least partially extends outside the substrate1, and the spacer7extends from inside the bit line trench2of the substrate1to outside the substrate1. The spacer7serves as an isolation layer for subsequently fabricating a capacitor contact wire. A height of the spacer7extending outside the substrate1neither should be too small, to avoid adversely affecting the fabrication of the capacitor contact wire, nor should not be too large, to prevent inclination or collapse of the spacer7due to a greater height of the spacer7. A height a of the spacer7extending outside the substrate1may be 3 to 8 times such as 4 times, 6 times, or 8 times a width b of the spacer7, and further, the height a may be 1 to 2 times such as 1.5 times or 2 times a pitch c between two adjacent spacers7. In some embodiments, the width of the spacer7is greater than or equal to the width of the bit line contact4positioned below the spacer. A material of the spacer7may be, for example, SiN. The spacer7may serve as the isolation layer for subsequently fabricating the capacitor contact wire.

In the above technical solutions, by setting the contact surface between the bit line contact4and the bit line metal3to be the arc-shaped contact surface, the contact area between the bit line contact4and the bit line metal3is increased, and thus the electrical conductivity of the bit line structure is enhanced. In some embodiments, expanding the width of the first trench segment21further expands the width of the bit line metal3, thereby avoiding collapse of the spacer7during the manufacturing processes. The bit line structure which is not easy to damage in manufacturing processes and has a larger conductive contact area is provided to adapt to failure of the bit line structure due to the miniaturization of the bit line structure.

FIG.5is a schematic diagram of a method for fabricating a buried bit line structure according to an embodiment of the present disclosure. The method for fabricating the buried bit line comprises: Step S101, providing a substrate1(shown inFIG.4), and forming a bit line trench2in the substrate1(shown inFIG.4); Step S102: filling a bit line metal3in the bit line trench2(shown inFIG.4); and Step S103: forming a bit line contact4on the bit line metal3(shown inFIG.4), where an arc-shaped contact surface is provided between the bit line contact4and the bit line metal3.

Referring toFIG.5, in Step S101, a substrate1is provided, and a bit line trench2is formed in the substrate1.FIG.6is a schematic diagram of a bit line trench2according to an embodiment of the present disclosure. Referring toFIG.6, a substrate1is provided, and a mask layer (not shown in the figure) such as SiO2is formed on the substrate1. The mask layer is patterned by means of a photolithography process, and the substrate1is continuously etched downward along the patterned mask layer, such that a bit line trench2is provided in the substrate1, where the bit line trench2serves as a bit line conductive layer to connect the bit line metal3.

FIG.7is a schematic diagram of a bit line trench2according to another embodiment of the present disclosure. Referring toFIG.7, before the filling the bit line metal3in the bit line trench2, the method further comprises: expanding a portion of the bit line trench2and forming a first trench segment21; and forming a second trench segment22on a remaining portion of the bit line trench2, where the second trench segment22extends along a direction of the first trench segment21, and a cross-sectional area of the second trench segment22is smaller than a cross-sectional area of the first trench segment21. The bit line trench2includes the first trench segment21and the second trench segment22. The first trench segment21has a larger volume, such that it may be filled with more bit line metal3. Moreover, the air gap is formed when the bit line metal3is filled, such that the arc-shaped surface may be formed by etching back the bit line metal3to the air gap, thereby improving the electrical conductivity. Furthermore, the wider spacer7may be formed by means of deposition via the first trench segment21and the second trench segment22, thereby preventing the spacer7from collapsing due to a higher depth-to-width ratio.

FIG.8is a schematic diagram of a method for forming the first trench segment21according to an embodiment of the present disclosure.FIG.9is a schematic diagram of a first dielectric layer8and a second dielectric layer9according to an embodiment of the present disclosure. Referring toFIG.8andFIG.9, the expanding the portion of the bit line trench2and forming the first trench segment21(shown inFIG.7) comprises: Step S201, depositing the first dielectric layer8in the bit line trench2, where the first dielectric layer8covers an inner wall of the bit line trench2; Step S202, depositing the second dielectric layer9on the first dielectric layer8; Step S203, etching back a portion of the second dielectric layer9and exposing a portion of the first dielectric layer8; Step S204, treating the exposed portion of the first dielectric layer8to form a third dielectric layer10, where the third dielectric layer10has different properties from the second dielectric layer8; Step S205, removing a remaining portion of the second dielectric layer9and a remaining portion of the first dielectric layer8, and exposing the substrate1; and Step S206, laterally etching the exposed portion of the substrate1to expand the portion of the bit line trench2and form the first trench segment21.

With continued reference toFIG.8, in Step S201, the first dielectric layer8(shown inFIG.9) is deposited in the bit line trench2(shown inFIG.9), and the first dielectric layer8covers the inner wall of the bit line trench2. In Step S202, the second dielectric layer9(shown inFIG.9) is deposited on the first dielectric layer8. Referring toFIG.9, the substrate1has a bit line trench2, and a first dielectric layer8is deposited in the bit line trench2. In this embodiment, the first dielectric layer8may be, for example, a SiN layer, where a thickness of the SiN layer is for example 3 to 5 nm, such as 3 nm, and the first dielectric layer8covers the inner wall of the bit line trench2. A second dielectric layer9is deposited on the first dielectric layer8. In this embodiment, the first dielectric layer8and the second dielectric layer9are formed by means of an atomic layer deposition technique, where the second dielectric layer9may be a SiO2layer. The atomic layer deposition can accurately control the thickness of the first dielectric layer8and the thickness of the second dielectric layer9. When the first dielectric layer8is within the above range, the substrate1may be effectively protected, and the subsequent processing of the first dielectric layer8may be ensured to completely obtain the third dielectric layer10, thereby obtaining the bit line trench2having an expected shape.

With continued reference toFIG.8, in Step S203, a portion of the second dielectric layer9is etched back, and a portion of the first dielectric layer8is exposed. In Step S204, the exposed portion of the first dielectric layer8is treated to form a third dielectric layer10(shown inFIG.10), where the third dielectric layer10has different properties from the second dielectric layer9. The first dielectric layer8is formed into the third dielectric layer10having different properties from the first dielectric layer, such that the first trench segment21and the second trench segment22may be formed separately. In this case, the depth of the portion of the second dielectric layer9etched back may be a preset height of the bit line metal2, i.e., the height of the first trench segment21.FIG.10is a schematic diagram of the third dielectric layer10according to an embodiment of the present disclosure. Referring toFIG.10, the portion of the second dielectric layer9is etched back and the exposed portion of the first dielectric layer8is treated to form the third dielectric layer10. In this embodiment, the exposed portion of the first dielectric layer8is treated with oxygen plasma to form the third dielectric layer10. The first dielectric layer8is nitride and is formed, via an oxidation reaction, into the third dielectric layer10, which is a nitride oxide. For example, when the first dielectric layer8is silicon nitride, the third dielectric layer10is silicon oxynitride. In some embodiments, the temperature of the plasma oxygen reduction process is 800° C. to 900° C. such as 800° C. or 852° C., a plasma strength thereof is 600 W to 2,000 W such as 700 W or 1,200 W, and a pressure thereof is 1 Pa to 10 Pa such as 4 Pa or 8 Pa. In the above environment, the exposed portion of the first dielectric layer8may be fully oxidized into the third dielectric layer10having different properties. Of course, the treatment process used in the embodiment of the present disclosure is not limited thereto, for example, other suitable process such as high-temperature furnace tube oxidation, inert ion implantation, or nitriding may also be used. It should be understood that any process by which the first dielectric layer8may be treated to form the third dielectric layer10having the different properties should be included within the scope of protection of the present disclosure.

With continued reference toFIG.8, in Step S205, a remaining portion of the second dielectric layer9and a remaining portion of the first dielectric layer8are removed, and the substrate1(shown inFIG.11) is exposed. In Step S206, the exposed portion of the substrate1is laterally etched to expand the portion of the bit line trench2and form the first trench segment21(shown inFIG.11).FIG.11is a schematic diagram of the first trench segment21according to an embodiment of the present disclosure. Referring toFIG.11, the exposed portion of the substrate1is laterally etched to enlarge a portion of the bit line trench2and to form the first trench segment21. In this case, a remaining portion of the bit line trench2serves as the second trench segment22(shown inFIG.7). In some embodiments, the first dielectric layer8or the second dielectric layer9is removed by means of sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, oxygen, argon, or a mixture of the above gases, where argon may be used as a protective gas during the etching process.

Referring back toFIG.5, in Step S102, the bit line trench2is filled with the bit line metal3.FIG.12is a schematic diagram of a first barrier layer and a second barrier layer according to an embodiment of the present disclosure. Referring toFIG.12, in some embodiments, before filling the bit line metal3in the bit line trench2, the method further comprises: forming a first barrier layer6in the bit line trench2, and/or, forming a second barrier layer5in the bit line trench2, where the second barrier layer5is positioned on a surface of the first barrier layer6, and the bit line metal3covers a bottom wall and a side wall of the second barrier layer5. In some embodiments, the substrate1in the bit line trench2is nitrided to form the first barrier layer6. The plasma nitriding gas used when nitriding the substrate1is the ammonia at the temperature of 600° C. to 800° C. such as 620° C. or 700° C., the plasma strength is 600 W to 2,000 W such as 600 W or 720 W, and the pressure is 1 Pa to 10 Pa such as 3 Pa or 7 Pa. In some other embodiments, the portion of the substrate1may also be oxidized to form the silicon oxide material as the first barrier layer6, and of course the first barrier layer6may also be formed directly by means of deposition. The second barrier layer5continues to be formed on the surface of the first barrier layer6by means of deposition, where the second barrier layer5may be, for example, a metal nitride layer. Of course, the second barrier layer5may be formed directly on the surface of the substrate1without arranging the first barrier layer6.

With continued reference toFIG.12, in some embodiments, the filling the bit line metal3in the bit line trench2comprises: filling a metal material11in the first trench segment21and the second trench segment22of the bit line trench2, where an air gap12is provided in the metal material11filled; and etching back a portion of the metal material11to the air gap12, such that a remaining portion of the metal material11has an arc-shaped surface, where the remaining portion of the metal material11constitutes the bit line metal3, as shown inFIG.3for example. In the embodiments of the present disclosure, the bit line trench2has the structure that is narrower at the top and wider at the bottom, such that the air gap12is formed in the process of depositing the metal material11. During control of etching back, the air gap may be exposed, such that the surface of the bit line metal3finally formed is a concave circular surface. In this way, a larger contact area is provided between the bit line contact4formed subsequently and the conductive metal3therebelow, which is advantageous to improving the electrical conductivity.

Referring back toFIG.5, in Step S103, the bit line contact4is formed on the bit line metal3, where an arc-shaped contact surface is provided between the bit line contact4and the bit line metal3. With continued reference toFIG.12andFIG.3, after removing the upper metal material11and simultaneously removing the third dielectric layer10on the side wall, a bit line contact4continues to be deposited on the bit line metal3, where the bit line contact4is electrically conductive between the bit line metal3and the substrate1. In some embodiments, for example, the bit line contact4may be made of a polysilicon material. For example, by means of a low-pressure chemical vapor deposition (LPCVD), a reaction gas may be silane (SiH4) and hydrogen phosphide (PH3) for doped deposition at the temperature of 480° C. to 520° C. such as 500° C. By mixing the SiH4and the PH3, the P-doped polysilicon is formed by means of LPCVD thermal composition. In this way, the bit line contact4formed may be electrically conductive.

In some embodiments, the method for fabricating the buried bit line structure further comprises: forming a spacer7(shown inFIG.4), where the spacer7is filled in the bit line trench2(shown inFIG.4) and is positioned on the bit line contact4(shown inFIG.4), and the spacer7at least partially extends into the substrate1(shown inFIG.4).FIG.4is a schematic diagram of a buried bit line structure according to an embodiment of the present disclosure. Referring toFIG.4, the buried bit line structure comprises: a substrate1having a bit line trench2; a bit line metal3filled in the bit line trench2; a bit line contact4filled in the bit line trench2and positioned on the bit line metal3, where an arc-shaped contact surface is provided between the bit line contact4and the bit line metal3; a first barrier layer6positioned in the bit line trench; and/or a second barrier layer5positioned on a surface of the first barrier layer6, where the bit line metal3covers a bottom wall and a side wall of the second barrier layer5. In this embodiment, the buried bit line structure further includes a spacer7filled in the bit line trench2and positioned on the bit line contact4, where the spacer7at least partially extends outside the substrate1. The bit line contact4in the bit line trench2does not completely fill the second trench segment22of the bit line trench2or the portion of the bit line contact4is etched back, such that the insulating material such as the SiN material is deposited in the remaining portion of the bit line trench2, where the SiN material may also be formed in the trench whose mask layer is not shown above. After the mask layer above is removed, the spacer7is formed, as shown inFIG.4. Next, for example, a side wall layer (not shown in the figure) such as SiN—SiO2—SiN may be formed on the surface of the spacer7. Because a material of the SiN—SiO2—SiN structure has the characteristic of low dielectric constant, it may be employed to fabricate the side wall having the low dielectric constant to enhance anti-breakdown capability of the side wall.

In the above technical solutions, by setting the contact surface between the bit line contact4and the bit line metal3to be the arc-shaped contact surface, the contact area between the bit line contact4and the bit line metal3is increased, and thus the electrical conductivity of the bit line structure is enhanced. In some embodiments, expanding the width of the first trench segment21further expands the width of the bit line metal, thereby avoiding collapse of the bit line structure in a subsequent etching process. The bit line structure which is not easy to damage in manufacturing processes and has a larger conductive contact area is provided to adapt to failure of the bit line structure due to the miniaturization of the bit line structure.

The embodiments of the present disclosure also provide a memory, which comprises a buried bit line structure. The buried bit line structure comprises: a substrate having a bit line trench; a bit line metal filled in the bit line trench; and a bit line contact positioned on the bit line metal, where an arc-shaped contact surface is provided between the bit line contact and the bit line metal.

In the above technical solutions of the present disclosure, by setting the contact surface between the bit line contact and the bit line metal to be the arc-shaped contact surface, the contact area between the bit line contact and the bit line metal is increased, and thus the electrical conductivity of the bit line structure is enhanced. In some embodiments, expanding the width of the first trench segment further expands the width of the bit line metal, thereby avoiding collapse of the bit line structure in a subsequent etching process. The bit line structure which is not easy to damage in manufacturing processes and has a larger conductive contact area is provided to adapt to failure of the bit line structure due to the miniaturization of the bit line structure, thereby reducing failure and damage of the memory caused by the failure of the bit line structure, and prolonging service life of the memory.

What is mentioned above merely refers to some embodiments of the present disclosure. It is to be pointed out that to those of ordinary skill in the art, various improvements and embellishments may be made without departing from the principle of the present disclosure, and these improvements and embellishments are also deemed to be within the scope of protection of the present disclosure.