Electronic device and method of manufacturing same

This application relates to a method of manufacturing an electronic device comprising placing a first chip on a carrier; applying an insulating layer over the first chip and the carrier; applying a metal ions containing solution to the insulating layer for producing a first metal layer of a first thickness; and producing a second metal layer of a second thickness on the insulating layer wherein at least one of the first metal layer and the second metal layer comprises at least a portion that is laterally spaced apart from the respective other metal layer.

TECHNICAL FIELD

The present invention relates to a semiconductor device and methods of manufacturing semiconductor devices.

BACKGROUND

In the wake of an ever increasing level of function integration in semiconductor devices, the number of input/output channels of semiconductor devices has been rising continuously. At the same time, there is a demand to shorten signal channel lengths for high frequency applications, improve heat dissipation, reduce internal ohmic resistance, improve robustness, and to decrease manufacturing costs. This represents significant challenges to the way by which silicon chips in the semiconductor devices are packaged.

SUMMARY

Accordingly, there is provided a method of manufacturing an electronic device comprising placing a first chip on a carrier; applying an insulating layer over the first chip and the carrier; applying a metal ions containing solution to the insulating layer for producing a first metal layer of a first thickness; and producing a second metal layer of a second thickness on the insulating layer wherein at least one of the first metal layer and the second metal layer comprises at least a portion that is laterally spaced apart from the respective other metal layer.

DETAILED DESCRIPTION

FIGS. 1A-1Dschematically disclose an embodiment of a method of manufacturing an electronic device by illustrating top views on the processed electronic device at various manufacturing steps.FIG. 1Adiscloses a carrier2, and a first chip6placed on the carrier. Carrier2may be of any type that is appropriate for carrying a chip. For example, carrier2may be a plate or structure to which chip2is attached, e.g. by gluing, or soldering. Carrier2may also be made of an electrically conducting material like, e.g. a metal like copper, of an electrically insulating material like, e.g., a ceramic or plastic, of a laminate that consists of alternating layers of electrically conducting and insulating layers, of a foil or tape, etc. Further, the shape of carrier2may be that of a plate, a tape, a leadframe strip, wafer, etc. Further, carrier2may consist of an array of individual carriers onto each of which one or several chips are placed. In this case, the method of manufacturing an electronic device can be carried out for each of the chips in parallel (batch mode). Various embodiments of electronic devices with various carrier types will be shown in more detail later.

Chip6may be any type of semiconductor chip. It may include, e.g. an integrated circuit, sensor elements like pressure sensor, acceleration sensor, gas sensor, optoelectronic elements like photodiodes, optically active elements like a laser, and the like. Also, as will be shown below, embodiments may include semiconductor chips that have power transistors for switching high electronic currents and/or high voltages. For example, chip6may include one or several Insulated Gate Bipolar Transistors (IGBT) that each have a source on one face of the chip and a drain on the opposite face of the chip. Such chips may be capable of controlling currents of 10 A or higher, and withstanding voltages up to 1000 V, or higher.

Depending on the application, the placement of chip6on carrier2may include gluing the chip to the carrier, soldering the chip to the carrier, or sintering the chip to the carrier. For example, if chip6comprises a power transistor for controlling a large current from a first face of the chip the opposite face of the chip, the chip may be soldered to the carrier in order provide a low ohmic resistance between the carrier2and the chip6.

FIG. 1Billustrates the electronic device ofFIG. 1Aafter having applied an insulating layer8over first chip6and carrier2. As can be seen in the figure, insulating layer8covers a region of carrier2, chip6, and the edge of chip6. For illustrational purposes, the position of chip6on carrier2underneath insulating layer8is indicated by dotted lines. As will be explained in more detail later, insulating layer8may be a layer made of an anorganic material, e.g., silicon oxide, silicon nitride, amorphous Si—O—H carbon, of ceramic compounds like silicone carbide, or of aluminum nitride. Alternatively, insulating layer may be made of an organic material, e.g., polymer like polyimide, epoxy resin, acrylate, Parylene, BCB. Depending on the type of insulating material, insulating layer8may be applied in traditional ways, e.g. from a liquid phase by needle dispensing, spin on or dip coating, or printing. Printing may include the known techniques of stencil print, screen print or inkjet print. Alternatively, insulating layer8may be deposited out of a gas phase via sputtering, spray coating or plasma gas phase deposition like chemical vapour deposition (CVD) or physical vapour deposition (PVD).

In one embodiment that will be explained later in more detail, insulating layer8is made of a polymer that contains metal particles, or metal complexes, that become exposed to the surface of the layer once the polymer is irradiated with electromagnetic radiation.

The thickness of insulating layer8may be chosen depending on the application and complexity of the structure on chip6. Generally, the thickness should not fall below a given minimum to make sure that insulating layer8withstands the voltages used during module operation. The minimum thickness also depends on the material used for insulating layer8. For example, if insulating layer8is made of an anorganic material, the minimum thickness should be larger than, say, 1 micrometers while, if insulating layer8is made of an organic material, the minimum thickness should be larger than 5 micrometers. Further, if chip6has several contact elements spaced apart at a pitch of less than 100 micrometers, it is useful to have the thickness of insulating layer8above chip6be of a similar size, or smaller, for securely accessing the contact elements from above through openings10b,10din insulating layer8. On the other hand, if the application involves high voltages, or if chip6comprises merely one transistor with two or three contact elements on top, the thickness of insulating layer8may be as large as 1 millimeter or more without jeopardizing a secure electronic access from above through insulating layer8. Note that insulating layer8may extend conformally over the chip, the carrier and the edge of the chip, or be planarized to provide a flat surface for the metal layers that are to be produced on insulating layer8.

In the embodiment ofFIG. 1B, insulating layer8comprises one large opening10ato contact carrier2from above, one large opening10bto contact chip6from above, one small opening10cto contact carrier2from above, and one small opening10dto contact chip6from above. The size of the openings may be chosen according to the size of the contact elements of the chip or carriers, and on the currents that are expected to flow through the respective openings. The openings10a,10b,10c,10dmay be produced in various known ways, e.g. by laser irradiation, by etching the insulating layer8selectively to a mask, etc.

FIG. 1Cdiscloses the electronic device ofFIG. 1Bafter a metal ions containing solution has been applied to insulating layer8for producing first metal layer14. In the present case, the metal ions containing solution has been applied such that first metal layer14forms a strip extending from large opening10aabove carrier2to large opening10babove chip6. This way, first metal layer14electrically connects chip6with carrier2. Note that first metal layer14has a large structure width in comparison to the minimum structure width of second metal layer18that will be produced later (seeFIG. 1D). The large structure width is intended to enable a low resistance connection between chip6and carrier2. A low resistance connection may, for example, be advantageous for applications where chip6comprises a power transistor intended for switching a large current. In this case, the large structure width makes sure that voltage drop caused by the switching of a high current kept small.

The metal ions containing solution may be applied to insulating layer8in several ways. In one embodiment, the metal ions containing solution is applied by selectively depositing the metal ions containing solution to desired regions on insulating layer8, e.g. with ink-jetting dispenser. In this case, after drying the metal ions containing solution, a first electrically conducting metal layer14has been formed in the regions where the metal ions containing solution was applied.

In the embodiment shown inFIG. 1C, first metal layer14is produced by first producing a first structure12(dotted line) on insulating layer8followed by applying the metal ions containing solution over insulating layer8. Since first structure12is capable of selectively interacting with the metal ions containing solution, the metal ions containing solution remains selectively in the region of the first structure12to form first structure12. The use of a structure12makes it obsolete to apply the metal ions containing solution selectively to insulating layer8. Rather, with structure12, it is sufficient to immerse insulating layer8into the metal comprising solution to obtain a desired structured first metal layer14.

In one embodiment, first structure12is made to serve as a seed layer for growing first metal layer14that is to electrically connect chip6to carrier2. The seed layer structure12may be produced in several ways, depending on the material of insulating layer8and on the required structure size. For example, if insulating layer8is made of metal particle containing polymer, seed layer structure12may be produced by irradiating insulating layer8with a laser beam until sufficient metal particles become exposed along the irradiated locations of insulating layer8to form the seed layer. In another embodiment, seed layer structure12may be produced by selectively applying a conducting liquid to insulating layer8that, after drying, forms the seed layer. In a further embodiment, seed layer structure12may be produced by applying an electroconductive layer over insulating layer8and, subsequently, selectively removing regions of the electroconductive layer by using, e.g., laser ablation or photolithographic processes. Techniques for applying the electroconductive layer include needle dispensing, spin on coating or dip coating. In this case, the remaining of the electroconductive layer forms the seed layer structure. Further known techniques for producing a seed layer structure on insulating layer8include ink-jetting with an electrically conductive ink, ink-jetting with a catalytic ink, tampon, screen or stencil printing an electrically conductive paste, selectively needle dispensing, selectively spray coating an electroconductive layer, etc.

After production of seed layer structure12, first metal layer14is produced in a process in which seed layer structure12is exposed to a solution containing solved metal ions to form, during an electrochemical process, first metal layer14on seed layer structure12. In one embodiment, for forming first metal layer14, insulating layer8may be completely immersed in, or covered by, the metal ions containing solution. In this case, due to the selectivity of the electrochemical process, the metal ions in the metal ions containing solution selectively adhere to seed layer structure12to form first metal layer14adapted to seed layer structure12. Further, if seed layer structure12forms a conducting region, a voltage may be applied between seed layer structure12and the metal ions containing solution to accelerate the electrochemical growth of first metal layer14. The choice of the metal in the solution, and the detailed electrochemical process parameters depend, among others, on the type of seed layer and on the type of the metal ions containing solution, as will be explained later in more detail. Generally, electrochemical growth of a metal structure on a seed layer is a technique well known in the art. If an external voltage is applied during the electrochemical growth of the metal layers, the technique is also known as Galvanization.

In one embodiment, the thickness of first metal layer14is designed to be large in comparison to the thickness of second metal layer18that will be produced later (seeFIG. 2A,2B). The larger thickness can be obtained by exposing insulating layer8to the metal ions containing solution for a longer time period. With a larger thickness, less lateral space is needed on insulating layer8for obtaining a desired minimum cross section area, which is given by the minimum structure width of first seed layer structure12times the thickness of first metal layer14. For example, if the minimum structure width of first structure12is ten times larger than the minimum structure width of second structure16, and if the thickness of first metal layer14is ten times larger than the thickness of second metal layer18, the cross section area of first metal layer14may be as large as, or larger than, 100 times the cross section area of second metal layer18.

FIG. 1Ddiscloses the electronic device ofFIG. 1Cafter production of first metal layer14and after production of a second metal layer18on insulating layer8. Like first metal layer14, second metal layer18has been produced by applying a metal comprising solution to insulating layer8in a strip-like region extending from small opening10cabove carrier2to small opening10dabove chip6. This way, second metal layer18provides a second connection electrically connecting chip6with carrier2. Note that second metal layer18has a small minimum structure width in comparison to the minimum structure width of first metal layer14. The small structure width can be used to save space on insulating layer8to facilitate complex circuitry on insulating layer8on the same insulating layer.

In the embodiment ofFIG. 1D, second metal layer18is produced by first producing a second structure16on insulating layer8and, thereafter, by applying the metal ions containing solution to insulating layer8. Like for first metal layer14, second structure16serves as a second seed layer for second metal layer18. In this embodiment, production of second seed layer structure16occurs after production of first metal layer14. This way, second metal layer18may be structured such that portions of second metal layer18are laterally spaced apart from first metal layer14.

Second structure16(second seed layer) and second metal layer18may be produced in any one of the ways mentioned for the design of first structure12and the production of first metal layer14. In particular, the metal ions containing solutions for producing first and second metal layers14,18may and may not be the same. In one embodiment, second metal layer18is produced by fully immersing the electronic device ofFIG. 1Cinto the metal ions containing solution. Note that in this case, second metal layer18grows on second seed layer structure16as well as on first metal layer14. In this case, first metal layer14fully overlaps second metal layer18while second metal layer18comprises portions that are laterally spaced apart from first metal layer14. Note that, if the thickness of second metal layer18is significantly smaller than the thickness of first metal layer14, the overlapping of second metal layer18with first metal layer14does not significantly increase the total cross section area of the combined first metal layer14and second metal layer18cross section areas.

Second structure16may also be produced in ways different from the production of first structure12. For example, if the minimum structure width of first structure12is in the range of a few millimeters, first structure12may be produced by using the tampon printing technique. The tampon printing technique is time saving when it comes to produce large structures. On the other hand, if the minimum structure width of second structure16is in a range below 10 micrometers, or less, second structure16may be produced by a laser beam that can be focused to a spot size smaller than, say, 10 micrometer in diameter.

It should be noted that the expression “first metal layer” and “second metal layer” in this application refer to structures that have a defined thickness. At the same time, first metal layer14and second metal layer18may have any shape or structure lateral to the plane of insulating layer8. Accordingly, due to their defined thickness, even though first metal layer14and second metal layer18may look like lines in an embodiment, they are referred to as a “layer”.

FIGS. 2A and 2Bschematically illustrate cross sections of the embodiment ofFIG. 1Dalong the two cross section lines2A-2A′ and2B-2B′ shown inFIG. 1D. The cross section ofFIG. 2Ais a cut orthogonal to carrier2along the line2A-2A′, whileFIG. 2Bis a cut orthogonal to carrier2along the line2B-2B′.FIG. 2Aindicates the way by which second metal layer18is connected to chip6through opening10din insulating layer8, and to carrier2through opening10c. Further,FIG. 2Aindicates that insulating layer8is conformally applied over chip6and carrier2. Note that this is not a requirement since insulating layer8may also be planar on the upper surface.FIG. 2Blooks likeFIG. 2Awith the difference that first metal layer14electrically connects chip6through large opening10bwith carrier2, and to carrier2through large opening10a. Further, the thickness of first metal layer14is at least twice as large as second metal layer18.

With the method described inFIGS. 1A-1Dand2A-2B, an electronic device1can be manufactured that includes a carrier2, a first chip6attached to the carrier2, an insulating layer8over carrier2and first chip6, a first metal layer14of a first metal layer thickness on insulating layer8, and a separate second metal layer18of a second metal layer thickness on insulating layer8. Further, due to the consecutive production of first metal layer14and second metal layer18on the same insulating layer8, the thicknesses of first metal layer14and second metal layer18can be freely chosen. This way, the thicknesses can be adapted to a given application without adding an additional insulating layer between first metal layer14and second metal layer18. Accordingly, a costly multi-layer design can be avoided, and circuitry with combined high voltage, high current, high speed and/or complex logic applications can be placed on the surface of an insulating layer8within a small area.

FIG. 3Aand the processing sequence ofFIGS. 3B-3Fillustrate a further embodiment for the production of a first metal layer114and a second metal layer118on an insulating layer108. In this embodiment, first metal layer114and second metal layer118are produced by producing consecutively a first seed layer structure112(first structure) and a second seed layer structure116(second structure) by a laser beam103.

FIG. 3Aillustrates an electronic device100, which may be the same as the one shown inFIG. 2A. For example, carrier102, chip106, and insulating layer108of electronic device100may be the same as carrier2, chip6and insulating layer8ofFIGS. 2A and 2B.FIG. 3Afurther discloses laser101that directs a laser beam103onto insulating layer108to produce first seed layer structure112and second seed layer structure116. By having laser beam103scan desired regions on insulating layer108, either by moving laser beam103with respect to carrier102or by moving carrier102with respect to laser beam103, laser beam103turns the surface on insulating layer8into a desired first seed layer structure112. Examples of lasers that can be used for forming structure112on insulating layer108are, e.g., KrF-, XeCl- or Nd-YAG-laser in a wavelength range 200-11000 nm. Generally, frequency and power of the laser are adapted to the type of insulating layer material.

FIG. 3Bdiscloses a schematic cross section through insulating layer108of embodiment ofFIG. 3Ain a plane perpendicular to the drawing plane. In the embodiment ofFIGS. 3B-3F, insulating layer108is made of a polymer that contains metal particles, metal particles covered with an insulating layer, metal ceramic particles, or metal complexes. Those particles are indicated inFIGS. 3B-3Fby the dots150. The thickness of insulating polymer layer108may be in the range of, e.g., 0.1 to 200 micrometer, depending on the application and polymer matrix.

If particles150are metal particles, they are typically made of copper, alumina, nickel, silver, gold and palladium. Typically, the diameter of the metal particles is in the range of 10 to 1000 nanometers, but may be up to several micrometers. The metal particles covered with insulating layer may be of the same size. The metal complexes may consist of one or more palladium-, copper-, aluminum-, nickel-, silver-, gold-atoms and organic molecules surrounding the metal atom.

It should be noted that for producing a conducting structure112by laser irradiation on insulating layer108, insulating layer108may also be made of inorganic materials like a ceramic, aluminum nitride, aluminum oxide, titan oxide, silicon oxide, or silicon.

FIG. 3Cdiscloses the schematic cross section ofFIG. 3Bafter irradiation of insulating layer108by laser beam103to produce first seed layer structure112. In the region where laser beam103has interacted with insulating layer108, the polymer molecules of insulating layer108evaporate and expose particles150to the surface. As indicated in theFIG. 3C, the evaporation of the polymer leaves a roughened surface in the irradiated region of insulating layer108. Further, if particles150are metal particles covered with a protecting insulating layer, or if the particles are metal complexes, the interaction with laser beam103may cause the insulating layer of the exposed particles150, or the metal complex bonds, to break. In both cases, “naked” metal particles with a conductive surface remain on the surface of insulating layer108. The naked metal particles150in turn may serve as a seed for electrochemically growing first metal layer114upon exposure to a metal ions containing solution.

In one embodiment, particles150in insulating layer108may be metal ceramic particles made of aluminium nitride. In this case, once laser beam103interacts with the exposed aluminium nitride particles, the electrically insulating aluminium nitride turns into electrically conducting aluminium and insulating aluminium oxide. In this case, the electrically conducting aluminium particles may serve as a seed112electrochemically growing first metal layer114from the metal ions containing solution. Note that the seed layer itself may not be conductive since there may be too few seed particles to form a macroscopically conducting layer.

In another embodiment, the particles150may be metal particles covered with a protecting insulating layer, e.g. an oxide layer, an silicon oxide layer, an Al2O3-layer, or an insulating organic layer. The protecting layers may be produced, e.g., by thermal metal oxidation, in a chemical vapour deposition process (CVD). The protecting insulating layer on the metal particles makes sure that insulating layer108is macroscopically electrically insulating. Only in regions where laser beam103interacts with insulating layer108, the laser may break the protecting layer to turn the insulating particles into electrically conducting particles. The electrically conducting particles in turn may serve as a seed112for electrochemically growing a metal layer.

In another embodiment, the particles are metal particles that are not covered with a protecting layer. In this case, it is sufficient to apply a laser beam for evaporating the surrounding polymer matrix in order to expose the metal particles to the surface to serve as a seed112.

For illustrational purposes,FIG. 3Calso shows an arrow whose length indicates a first structure width152of first structure112, i.e. the width of a conducting line that is, or is part of, first metal layer114. First structure width152is one parameter that determines the structure width of first metal layer114. The structure width of first metal layer114, in particular the minimum structure width of first metal layer114, determines the density of conducting lines into which first metal layer114can be structured. Another parameter that determines the minimum structure width of first metal layer114is the thickness of first metal layer114since during production of first metal layer114, the conducting lines of first metal layer114grow in vertical as well as in lateral directions (seeFIG. 3D). Accordingly, the minimum structure width of first metal layer114is the larger the larger the thickness of first metal layer114.

FIG. 3Ddiscloses the schematic cross section ofFIG. 3Cafter a metal ions containing solution has been applied to first seed layer structure112to form first metal layer114. Note that due to the first seed layer structure112, there is no need to apply the metal ions containing solution selectively to the first seed layer structure112since the metal ions containing solution interacts only with first seed layer structure112but not, or only little, with the remaining surface of polymer layer108. This represents a significant process simplification since it is possible to obtain the desired structure of first metal layer114by dipping the entire insulating layer8into a bath of the metal ions containing solution without any need to cover insulating layer8in the regions where no first metal layer114is grown.

The choice of the metal ions containing solution depends on the metal that is to be grown on the seed layer112. For example, solutions of copper ions, silver ions, nickel ions, or gold ions can be used (e.g. copper in alkaline potassic hydroxide solution or copper-sulphite, copper-cyanide solution). Generally, it is well known in the art what metal ions containing solution and what process parameters (solution concentration, temperature, etc) to use for a given application.

FIG. 3Ediscloses the schematic cross section ofFIG. 3Dafter a second seed layer structure116(second structure) has been produced on insulating layer108for producing second metal layer118. In this embodiment, second seed layer116is produced with the same laser103that was used for producing first seed layer structure112. Note that due to the high focusing capability of the laser beam, the minimum structure width of second seed layer116may be as small as 10 micrometer, or smaller. The small structure width makes it possible to place a complex circuitry on insulating layer108.

FIG. 3Fdiscloses the schematic cross section ofFIG. 3Eafter a second metal layer118has been produced on insulating layer108by applying a metal ions containing solution to insulating layer108. Since the metal ions containing solution interacts only with the second seed layer structure116and the first metal layer114, the second metal layer118grows only on second seed layer structure116and on first metal layer114. In this embodiment, the process for growing second metal layer118is significantly shorter than for growing first metal layer114(e.g. ten times shorter) to obtain a significantly smaller thickness of second metal layer118. With a smaller thickness, it is possible to produce a metal layer structure with a smaller structure width. Due to the small thickness of second metal layer118, the total cross section area of the combined cross section areas of first metal layer114and second metal layer118is hardly affected by the growth of the additional second metal layer118on top of first metal layer114. Note that in the process ofFIGS. 3B to 3F, the portion of second metal layer118that covers second structure116is laterally spaced apart from first metal layer114.

FIG. 4Aand the processing sequence ofFIGS. 4B-4Fillustrates a further embodiment demonstrating the production of first metal layer214and second metal layer218on insulating layer208by producing consecutively a first seed layer structure212(first structure) and a second seed layer structure216(second structure). In this embodiment, first seed layer structure212and second seed layer structure216are produced by selectively applying a conducting liquid203to the surface of insulating layer208.

FIG. 4Aillustrates an electronic device200that may be the same as the one shown inFIGS. 2A and 2B. For example, carrier202, chip206, and insulating layer208of electronic device200may be the same as carrier2, chip6and insulating layer108ofFIGS. 2A and 2B. Further, instead of being made of a polymer layer like inFIG. 3A, insulating layer208may also be made of an anorganic material, e.g. ceramic, aluminum nitride, aluminum oxide, titan oxide, silicon oxide, silicon, etc.FIG. 4Afurther discloses a dispenser201that is capable of selectively applying a conducting liquid to insulating layer208by dispensing the conducting liquid203to desired regions on insulating layer208.

The minimum structure width that dispenser201can create on insulating layer208may vary widely depending on the type of dispenser. For example, if ink-jet dispenser201is a micro-machined device with a jet nozzle opening smaller than 20 micrometers, the minimum structure width of the seed layers produced by the dispenser201may be as small as 20 micrometers. On the other hand, if the conducting liquid203is a paste that is dispensed by tampon printing, the minimum structure width may be larger than a millimeter.

FIG. 4Bdiscloses a schematic cross section through insulating layer208of the embodiment ofFIG. 4Ain a plane perpendicular to the drawing plane. As mentioned above, insulating layer208may be of organic or anorganic material. The thickness of insulating layer208may vary widely, depending on the application. Typical values for the thickness of insulating layer208are between 1 and 1000 micrometer.

FIG. 4Cdiscloses a schematic cross section like inFIG. 4Bafter conducting liquid203has been applied selectively to desired regions on insulating layer208by using dispenser201to form an electrically conducting first seed layer structure212(first structure) on insulating layer208. The thickness of first seed layer structure212may be of the range, e.g. between 100 and 10,000 nanometer. At the same time, in this embodiment, the minimum structure width of first seed layer212is chosen to be as large as one or two millimeters to produce a first metal layer214of large current capability. Conducting liquid203may be a conducting ink containing metal atoms e.g. like silver, gold, palladium and copper.

FIG. 4Ddiscloses a schematic cross section like inFIG. 4Cafter applying a metal ions containing solution to insulating layer208to produce a first metal layer214. Like in the previous embodiments, first metal layer214is produced by electrochemically growing the metal from the metal ions containing solution. Since first metal layer214is designed to carry large currents, the application of the metal ions containing solution to insulating layer208is conducted until first metal layer214has assumed a thickness as high as, say, 100 micrometers or more. Note that the electrochemical process can be carried out by applying an external voltage between the metal ions containing solution and first seed layer structure212.

FIG. 4Ediscloses a schematic cross section like inFIG. 4Dafter a conducting liquid is applied selectively to insulating layer208after production of first metal layer214. The selective application of the conducting liquid after production of first metal layer214may be used to produce a second seed layer structure216(second structure). Second seed layer structure216may be produced in the same way as first seed layer212with the difference that the minimum structure width of first seed layer structure212is larger than the minimum structure width of second seed layer structure216by a factor of 10 or more.

FIG. 4Fdiscloses a schematic cross section like inFIG. 4Eafter metal ions containing solution has been applied to insulating layer208to produce second metal layer218. Again, since the metal ions containing solution does only interact with the second seed layer structure216and with first metal layer214, second metal layer218selectively grows only on second seed layer structure216and on second metal layer218. Accordingly, there is no need to apply the metal ions containing solution selectively to the first seed layer structure112. Rather, it is possible to obtain the desired structure of first metal layer114by dipping the entire insulating layer8into a bath of the metal ions containing solution.

Note that the application of the metal ions containing solution according toFIG. 4Fis not required for the purpose of electrically connecting chip206with carrier202. In this case, if the application of metal ions containing solution is omitted, the second seed layer structure216itself may serve a second metal layer provided the thickness and conductivity of second seed layer structure216is sufficient for carrying a desired current. For example, if the second seed layer structure216is generated by a conducting liquid comprising gold, silver or copper-nano-inks, a further metallisation via an electrochemical process is not required.

In view that first metal layer214is designed to carry small currents, e.g. logical signals, the electrochemical process is carried out during a short period of time in comparison to the electrochemical process used for the production of first metal layer214. Otherwise, the production of second metal layer218may be the same as the production of first metal layer214. Note that, while the cross section of first metal layer214also expands due its exposure to the metal ions containing solution for second metal layer218, the effect is small due to the small thickness of second metal layer218.

The processing sequence ofFIGS. 5A-5Eillustrates a further embodiment schematically demonstrating the production of first metal layer314and second metal layer318on insulating layer308. Like in the previously described processing sequences, insulating layer308may be the insulating layer8of the electronic device1disclosed inFIGS. 2A and 2B.

In the present embodiment, there is only one seed layer structure312(first structure) that is used to generate a first metal layer314of a first thickness and a second metal layer318of a second thickness.

FIG. 5Aschematically discloses a cross section through insulating layer308that may be part of the embodiment ofFIG. 1Din a plane perpendicular to the drawing plane. Like before, insulating layer308may be an organic or anorganic layer. Further, the thickness of insulating layer308may vary widely, for example, between one micrometer and one millimeters depending on the application.

FIG. 5Afurther discloses two elements312a,312bof a seed layer structure312on insulating layer318. Seed layer structure312may be anyone of the seed layers described before, e.g. solidified conducting ink structure, a structured metal layer, or laser irradiated polymer layer with metal particles. Further, the two seed layer elements312a,312bmay have been applied simultaneously or one after the other. The two seed layer elements312a,312bmay, for example, have been produced by a laser, produced by dispensing a conducting liquid, by photo-lithographically etching a homogenous electro-conductive layer, or by other known ways. The thickness of seed layer312is of no critical importance and may be, depending on the seed layer type, in a range between a few nanometers and a few micrometers. If seed layer structure312has been produced by a laser, the seed layer may simply be a layer of conducting particles in the insulating polymer layer and exposed to the polymer layer surface. In the embodiment ofFIGS. 5A-5E, first seed layer element312ais chosen to have a large minimum structure width as a base for a metal layer318with a large structure width, e.g. for high current capability, while second seed layer element312bis chosen to have a small minimum structure width as a base for a metal layer314with a small structure width that requires less area on insulating layer308for any given circuitry.

FIG. 5Bdiscloses the two seed layer elements312a,312bafter applying a metal ions containing solution to insulating layer308to produce first metal layer314on the two seed layer elements312a,312bby electrochemically grow a first metal layer314on the two seed layer elements312a,312b. The thickness of the electrochemically grown first metal layer314is kept small, e.g. 0.1 to 10 micrometer, compared to the second metal layer318that is to be grown at a later stage. The small thickness of first metal layer314is to limit the minimum structure width of first metal layer314since during the electrochemical growth of first metal layer314, first metal layer314not only expands in a direction orthogonal to insulating layer308but also in a direction lateral to insulating layer308, as indicated inFIG. 5B.

FIG. 5Cdiscloses the cross section view ofFIG. 5Bafter a mask350is applied over insulating layer308that selectively covers first metal layer314. Mask350is used to cover the regions of those first metal layer elements314that are meant to maintain a small total metal layer thickness, i.e. a small minimum structure width. The mask may be applied to insulating layer308in known ways, e.g. by applying a photoresist (e.g. PMMA or polyimide or epoxy resin) to insulating layer308, and photo-lithographically structuring the photoresist layer.

FIG. 5Ddiscloses the cross section view ofFIG. 5Cafter a metal ions containing solution has been applied to insulating layer308. Due to mask350, the metal ions containing solution reaches only those regions of first metal layer314that are not covered by mask350. Accordingly, due to interaction with the metal ions containing solution, a second metal layer318is grown only on the first metal layer element that covers first seed layer element312a. As a result, due to the larger structure width of first seed layer element312aand the larger total thickness of the combined thickness of first metal layer314and second metal layer318, the cross section area for conducting a large current through second metal layer318is significantly larger than the cross sectional area of first metal layer elements314covered by mask350. Finally,FIG. 5Ediscloses the cross section view ofFIG. 5Dafter mask350has been removed, e.g. by washing it off or by ashing. Note that the removal of the mask is not a requirement since mask layer350may also remain in the package.

FIGS. 6A-6Eschematically disclose a further embodiment of manufacturing an electronic device wherein a first chip406and a second chip407are placed on a common carrier402. In one embodiment, first chip406may be a logic chip, e.g. a chip with a CMOS circuit, and second chip407may be a power chip, i.e. a chip that comprises at least one power transistor for switching a large current, e.g. a current in the range of 100 mA up to 100 A, or higher. As indicated inFIG. 6A, power chip407may be thinner than logic chip406. For example, power chip407may have been thinned to a range between, say, 20 to 200 micrometers while logic chip406may have a thickness of, say, 400 to 800 micrometers. The small thickness of power chip407is to reduce the On-Resistance of the power transistors. In addition to the thinning, both chips, due to their diverse functionalities, may have been produced by different manufacturing technology steps so that it may be difficult to integrate the functionalities of the two chips on one chip.

Further, power transistor of second chip407may be a vertical transistor that is capable of controlling a current flowing from the upper surface of the chip to the lower surface, or vice versa. Accordingly, second chip407may have a first electrode on the upper surface of second chip and a second electrode on the lower surface. In this case, carrier402may comprise a conductive chip island, and second chip407may be soldered, diffusion soldered, or with an electrically conducting glue attached to the chip island to provide an electroconductive connection to the chip island. First chip406, as a logic chip, may also be glued with an electrically insulation glue.

FIG. 6Afurther discloses an insulating layer408applied over logic chip406, carrier402and power chip407. Insulating layer408, in this embodiment, is a polymer layer that contains metal, metal complexes or ceramic particles, e.g. AlN-particles of a diameter up to several micrometers (seeFIGS. 3B-3F). However, in other embodiments, insulating layer408may be of any of the other materials mentioned before. The thickness of polymer layer408may be, for example, in the micrometer range. The polymer layer408may be deposited in any of the methods described above.

FIG. 6BdisclosesFIG. 6Aafter first openings440through polymer layer408(insulating layer) have been provided for accessing the high current aluminium contact pad (drain or source) of power chip407and high current contact pad of carrier402from the upper side of polymer layer408. The diameter of first openings440may be in the range of 150 micrometer or more to allow for a low ohmic connection between power chip407and carrier402. Further, a first structure412is shown inFIG. 6Bthat is produced between the two first openings440. First structure412serves as a first seed layer structure (first structure) for producing a first metal layer414. First seed layer structure412is indicated inFIG. 6Bby the fat line connecting the two first openings440. First seed layer structure412is produced by a laser beam directed onto polymer layer408to evaporate the polymer in the region of interaction and to break the AlN-particles into conducting Al-particles and other particles (seeFIG. 3C).

The first openings440may be produced in known ways, e.g. by an etching process selectively to a photo-lithographically structured mask (not shown). Alternatively, first openings440may be produced by a laser beam.

FIG. 6Cdiscloses the embodiment ofFIG. 6Bwith the difference that after production of first seed layer structure412, a metal ions containing solution is applied to insulating layer408to produce first metal layer414on first seed layer structure412, on the contact pad of power chip407and on the contact pads of carrier402underneath the first openings440. The contact pads are typically made of aluminium or copper. The application of the metal ions containing solution may be carried out by immersing the surface of polymer layer408into the metal ions containing solution. The metal ions containing solution may be one of the solutions mentioned above. Since first metal layer424is designed to carry large currents to or away from power chip407, the thickness of first metal layer414may be as large as 100 micrometers or larger.

FIG. 6Ddiscloses the embodiment ofFIG. 6Cwith the difference that after production of first metal layer414, several second openings442through polymer layer408have been produced above carrier402, above two contact pads of logic chip406and above a contact pad of power chip407. The second openings442have a small diameter, e.g. less than 100 micrometer, since they are meant to provide for logical signals only. The second openings442may be produced in the same way as the first openings440.

Further, a second seed layer structure416(second structure) is shown inFIG. 6Dthat is produced between one second openings442on carrier402and one second openings442on logic chip406, and between one second openings442on logic chip406and one second openings442on power chip407. Similar to first seed layer structure412, second seed layer structure416serves as a second seed layer structure416for a growing second metal layer418(seeFIG. 6E). The position of second seed layer416is indicated inFIG. 6Dby the two fat lines connecting the respective second openings442. Like first seed layer412, second seed layer416may be produced by a laser beam directed onto polymer layer408to evaporate the polymer in the region of interaction and to break conducting Al-particles out of the insulating AlN-particles (seeFIG. 3C).

FIG. 6Ediscloses the embodiment ofFIG. 6Dwith the difference that after production of second seed layer structure416, a metal ions containing solution is applied to insulating layer408to produce second metal layer418on second seed layer structure416, on first metal layer414, on the aluminium contact pads of logic chip406, on the aluminium contact pads of power chip407, and on the aluminium contact pads of carrier402underneath second openings442. Like for first metal layer414, second metal layer418may be produced by immersing the surface of polymer layer408into the metal ions containing solution. Since second metal layer418is designed to transport logic signals to or away from logic chip406and power chip407, the thickness of second metal layer18may be as small as 10 micrometers or even smaller.

FIG. 7Aand the sequence ofFIGS. 7B to 7Edisclose a multi-chip module500(electronic device) designed for a power application, and a method of producing the module using the process described inFIGS. 6A-6E.

Multi-chip module500ofFIG. 7Ais comprised of a carrier based on ceramic, polymer or epoxy compound plate, covered with a structured copper layer. The copper layer is structured to provide for external contact elements580, a first chip island582for attachment of controller chip506, second chip island584for attachment of the high-side power transistor chip507a, third chip island586for attachment of low-side power transistor chip507b, and power rail588. Controller chip506, high-side power transistor chip507aand low-side power transistor chip507bare each soldered to their respective island582,584,586.

For manufacturing multi-chip module500, the chips are soldered to their respective chip islands on carrier502(FIG. 7B). Further, carrier502and chips506,507a.507bare evenly covered with a polymer layer (not shown inFIG. 7AandFIG. 7B-7E) in a way as described inFIG. 6A. The thickness of the polymer layer is bigger than 5 micrometers. It follows a step wherein the polymer layer is structured a first time to produce large openings (not shown inFIG. 7AandFIG. 7B-7E) above the source contact pads of the high-side power transistor chip507a, the source contact pads of low-side power transistor chip507b, and the power rail588. Afterwards, a first seed layer structure512(first structure) comprised of two seed layer structure elements (seeFIG. 7B) is produced. The first seed layer structure elements512on the polymer layer extend from one the large opening to the other large opening in the insulating layer in a way as described inFIG. 6B. First seed layer structure512serves to define the structure of first metal layer514(seeFIG. 7AandFIG. 7C). As can be seen, the first seed layer structure elements512have about the same structure width, e.g. 100 micrometers or more.

As can be seen inFIG. 7B, one of first seed layer elements512extends from a respective large opening above power rail588to a respective large opening above the source of low-side power transistor chip507b, while the other element of first seed layer512extends from a large opening above third chip island586to a large opening above the source of high-side power transistor chip507a.

FIG. 7Cdiscloses carrier502after the polymer layer has been covered with a metal ions containing solution such that the metal ions of the metal ions containing solution can electrochemically interact with the first seed layer structure elements512and the exposed source contact pads to form first metal layer514. First metal layer514is comprised of the two first metal layer elements, as shown inFIGS. 7A and 7C. The lateral shape of first metal layer514is essentially the same as the lateral shape of the first seed layer structure elements512shown inFIG. 7B. The thickness of first metal layer514is chosen to be large in order to provide for large cross sections area connection between power rail588and the source of the low-side power transistor chip507b, and between the third chip island586and the source of high-side power transistor chip507a. The thickness of the first metal layer elements514may be the same as the first metal layer414described inFIGS. 6C-6E.

FIG. 7Ddiscloses carrier502ofFIG. 7Cafter the polymer layer is structured a second time to produce small openings (not shown inFIGS. 7A and 7D) above the gate contact pad of the high-side power transistor chip507a, above the gate contact pad of low-side power transistor chip507b, and above the contact pads of control chip506. In addition, a second seed layer structure516(second structure) is produced on the polymer layer (not shown inFIG. 7A) that connects the small openings in a way as described inFIG. 6D. Second seed layer structure516consists of fine line elements serving as a second seed layer to define the structure of second metal layer518. As can be seen inFIG. 7D, the minimum structure width of second seed layer516is much smaller than the minimum structure width of first seed layer512, e.g. 20 micrometers. The small structure width of second metal layer518makes it possible to place a complex wiring on the carrier. This way, complex modules containing as many components as controller chip506a, high-side power chip507a, and low-side power chip507b, multiple contact elements580, and more, can be interconnected on only one insulating layer.

FIG. 7Ediscloses carrier502ofFIG. 7Dafter a metal ions containing solution has been applied to polymer layer for a second time to produce second metal layer518by electrochemical interaction of the metal ions containing solution interact with the second seed layer elements516, and with the exposed contact pads. Due to the small structure width of the second seed layer elements516, the minimum structure width of the second metal layer elements518is small as well. The thickness of second metal layer518is chosen to be small as well, e.g. 10 micrometer, in order to maintain the minimum structure width of the first metal layer14small. Finally, after first metal layer514and second metal layer518have been produced, the multi-chip module may be moulded to mechanically and chemically protect the multi-chip module from external environment.

The method of manufacturing semiconductor devices can be applied to various packaging platforms. For example, while the embodiments ofFIGS. 7A to 7Eshows an electronic device500where the carrier502is made of an insulating material, the method of manufacturing can also be applied to a carrier made of a conducting material, e.g. on a copper sheet.

FIGS. 8A to 8Cdisclose a semiconductor device600where carrier602is a copper sheet element with a thickness of, say, 200 micrometer. Chip606may be soldered or glued to carrier602. Insulating layer608may be applied and structured in the same way as described in the embodiment ofFIG. 1A-1D.FIG. 8Afurther discloses first metal layer614electrically connecting chip606with carrier602via the two large through-holes10a,10bthrough insulating layer508. The embodiment may further include a second metal layer (not shown) having a different layer thickness. Generally, the embodiment ofFIGS. 8A-8Cmay be the same as ofFIG. 1A-1Dwith the only difference that carrier602is made of an electrically conducting material.

FIG. 8Bdiscloses the embodiment ofFIG. 8Aafter semiconductor device has been moulded with moulding material624to protect chip606, insulating layer608, first metal layer614and second metal layer from mechanical and chemical destruction by the environment.

FIG. 8Cdiscloses the embodiment ofFIG. 8Bafter copper carrier602has been structured to serve as external input/output connection pads20a,20bconnecting chip608to the outside world. The structuring of carrier602may be carried out by selectively etching the carrier, by sawing, or any other convenient method. The external connection pads20a,20bmay be used to solder semiconductor device600to a printed circuit board to connect semiconductor device600to the outside word. For example, if chip606is a vertical power transistor with a source and gate contact on the front side of chip602and a drain contact on the backside of chip602, external connection pad20amay connect the outside world to the source contact via first metal layer element614while external connection pad20bmay connect the outside world to the drain contact via the backside of chip602. Further external connection pads may be involved, at least one of them to connect the outside world to the gate contact on the chip front side.

Note that the manufacturing of an electronic device like the one shown inFIG. 8A-8Cis well suited to be carried out in the batch mode. In this case, an array of chips606may be soldered on a common carrier. Further, an insulating layer608may be applied over the common carrier and the chips. Afterwards, insulating layer608is structured to open the contacts of the chips and on the carrier. Further, a first metal layer614is produced over the array of chips and the common carrier to contact the chips with metal layer elements having a first layer thickness. Afterwards, a second metal layer618is produced over the array of chips and the common carrier to contact the chips with metal layer elements having a second layer thickness. Afterwards, moulding material624is applied over the array of chips and the common carrier. After moulding, the common carrier is structured to obtain individual external connection pads20a,20bfor each chip606. Finally, by etching or sawing through the moulding material, the array of chips is singulated to obtain multiple single devices600of the kind as shown inFIG. 8C.

FIGS. 9A-9Dillustrate a further embodiment that may be the same as the one shown inFIGS. 8A-8Dwith the difference that carrier702is not a copper sheet element but a tape or foil that later is removed from semiconductor device700.

FIG. 9Aillustrates an electronic device700like the one shown inFIG. 8A. The only difference is that chip706, insulating layer708, first metal layer714and second metal layer (not shown) are attached, or applied, to a flexible carrier702, e.g. a copper foil.

FIG. 9Cillustrates the process of removing the carrier702from semiconductor device700by pulling the copper foil from the moulding material724, the insulating layer708and the electrochemically grown first metal layer714and second metal layer. Afterwards, external contact elements20a,20bmay be applied to the exposed first metal layer714and second metal layer elements. The external contact elements may be solder balls, galvanically grown surface layer elements, or any other element whose production is well known in the art (FIG. 9D).