Photodiodes integrated into a BiCMOS process

Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.

BACKGROUND

The present invention relates to photonics chips and, more particularly, to structures including a photodiode and methods of fabricating such structures.

Light Detection and Ranging (LIDAR) is a laser-mapping technology that measures distance to a target by illuminating the target with pulsed laser light and measuring the reflected pulses with a sensor. LIDAR finds use, for example, in autonomous robots and self-driving cars. The sensor employed in a LIDAR system, and also in other infrared wavelength motion detection systems, is a germanium photodiode. Germanium possesses high absorption in the infrared wavelength range. Typically, a two-chip solution is used in which one chip includes one or more germanium photodiodes and a second chip includes a trans-impedance amplifier as well as associated logic and input/output. Each germanium photodiode converts impinging electromagnetic radiation into current as photons are absorbed. The trans-impedance amplifier amplifies the current generated by the photodiode and converts the current into a voltage.

Improved structures including a photodiode and methods of fabricating such structures are needed.

SUMMARY

In an embodiment of the invention, a structure includes a substrate having a top surface, a well, and a trench extending from the top surface to the well, and a photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. The structure further includes a bipolar junction transistor having an emitter positioned over the top surface of the substrate and a subcollector positioned below the top surface of the substrate. The subcollector of the bipolar junction transistor is provided by a second portion of the well.

In an embodiment of the invention, a method includes forming a well in a substrate, patterning a trench extending from a top surface of the substrate to the well, forming a photodiode in the trench, and forming a bipolar junction transistor having an emitter positioned over the top surface of the substrate and a subcollector positioned below the top surface of the substrate. The photodiode includes an electrode that is provided by a first portion of the well. The subcollector of the bipolar junction transistor is provided by a second portion of the well.

DETAILED DESCRIPTION

With reference toFIG. 1and in accordance with embodiments of the invention, a structure10includes a substrate12, shallow trench isolation regions14located in the substrate12, deep trench isolation regions16located in the substrate12, a shallow well18located in the substrate12, and a deep well20located in the substrate12. The deep trench isolation regions16define a region22of the substrate12that may be used to fabricate a photodiode, and a region24of the substrate12that may be used to fabricate a bipolar junction transistor26. An additional region (not shown) of the substrate12may be used to fabricate field-effect transistors as part of a BiCMOS process. The substrate12may be, for example, a bulk substrate composed of a single-crystal semiconductor material, such as a bulk single-crystal silicon substrate.

The shallow trench isolation regions14and deep trench isolation regions16may be formed in the substrate12by etching associated trenches of different depths in the substrate12and depositing a dielectric material, such as silicon dioxide, in the trenches. In the representative embodiment, the deep trench isolation regions16may extend from a top surface11of the substrate12to a portion of the substrate12beneath (i.e., under) the deep well20. In an alternative embodiment, the deep trench isolation regions16may extend from the top surface11of the substrate12into the substrate12and terminate within the deep well20. Portions of the deep well20are in direct contact with the dielectric material, which is solid, of the deep trench isolation regions16.

The shallow well18and the deep well20may be formed by respective ion implantations that introduce a dopant, such as an n-type dopant (e.g., arsenic (As) and/or phosphorus (P)), into the substrate12. The ions for each implantation may be generated from a suitable source gas and implanted into the substrate12with given implantation conditions using an ion implantation tool. The implantation conditions (e.g., ion species, dose, kinetic energy, tilt angle) may be selected to tune the characteristics (e.g., depth profile) of the different wells18,20. The deep well20is located at a greater depth in the substrate12than the shallow well18. The shallow well18may have a different dopant concentration than the deep well20. In an embodiment, the wells18,20contain semiconductor material having a conductivity type (i.e., n-type) of opposite polarity to the conductivity type of the substrate12, which may contain lightly-doped p-type semiconductor material.

The bipolar junction transistor26includes a base layer28located over the substrate12in region24and an emitter30that is located on a top surface of the base layer28. The base layer28may be composed of a semiconductor material, such as a silicon-germanium alloy with a content of silicon ranging from 95 atomic percent to 50 atomic percent and a content of germanium ranging from 5 atomic percent to 50 atomic percent. The semiconductor material of the base layer28may contain a dopant, such as a p-type dopant (e.g., boron) that provides p-type conductivity and, optionally, carbon to suppress the out-diffusion of the p-type dopant. The base layer28may be formed from a layer of semiconductor material deposited using a low-temperature epitaxial growth process, such as vapor phase epitaxy.

The emitter30may be composed of a different semiconductor material than the base layer28and may have an opposite conductivity type from the base layer28. For example, the emitter30may lack germanium that is present in at least a portion of the base layer28, and the emitter30may contain an n-type dopant. In a representative embodiment, the emitter30may be composed of a polycrystalline semiconductor material, such as polysilicon, deposited by chemical vapor deposition and the semiconductor material may be heavily doped with a concentration of an n-type dopant (e.g., phosphorus or arsenic) to provide n-type conductivity.

The bipolar junction transistor26includes a collector32and a subcollector34represented by different sections of the substrate12. Each of the different sections may contain a concentration of an n-type dopant (e.g., phosphorus or arsenic) to provide n-type conductivity. The collector32may be constituted by a portion of the shallow well18in region24that is isolated from the portion of the shallow well18in the region22of the substrate12by the deep trench isolation regions16. The subcollector34may be constituted by a portion of the deep well20. In an embodiment in which the deep trench isolation regions16penetrate through the deep well20, the subcollector34may be a portion of the deep well20that is isolated from the portion of the deep well20in the region22of the substrate12by the deep trench isolation regions16. In an embodiment in which the deep trench isolation regions16terminate within the deep well20, the portion of the deep well20providing the subcollector34may be electrically connected with the portion of the deep well20in the region22of the substrate12.

A doped region35may couple the subcollector34to the top surface11of the substrate12to provide a contact area at the top surface11in region24. Another doped region37may couple the deep well20to the top surface11of the substrate12to provide a contact area at the top surface11in region22. The doped regions35,37have the same conductivity type as the wells18,20and extend through the shallow well18to the deep well20. The doped regions35,37may be formed by a shared ion implantation or by separate ion implantations of a dopant, such as an n-type dopant (e.g., arsenic (As) and/or phosphorus (P)) that provides n-type conductivity. The ions used to form the doped regions35,37may be generated from a suitable source gas and implanted into the substrate12with given implantation conditions using an ion implantation tool. The implantation conditions (e.g., ion species, dose, kinetic energy, tilt angle) may be selected to tune the characteristics (e.g., depth profile) of the doped regions35,37. An implantation mask may be applied to the substrate12in order to localize the positions of the doped regions35,37. The implantation mask has a thickness sufficient to stop the energetic ions before reaching the substrate12. Following implantation, the implantation mask may be removed.

The base layer28includes an intrinsic base that is coextensive with the emitter30along a p-n junction and that is coextensive with the collector32along another p-n junction. Sections of the base layer28arranged peripheral to the intrinsic base and surrounding the emitter30may define an extrinsic base that provides a surface area for landing a contact to the base layer28. The bipolar junction transistor26may be characterized as a heterojunction bipolar transistor (HBT) if at least two or all three of the base layer28, the emitter30, and the collector32are composed of semiconductor materials with different bandgaps.

A conformal protection layer40may be deposited over the bipolar junction transistor26and over the surface of the substrate12in region22. A dielectric layer42may be blanket deposited over the conformal protection layer40. The conformal protection layer40may be composed of silicon dioxide or silicon nitride, and the dielectric layer42may be composed of, for example, borophosphosilicate glass (BPSG). The bipolar junction transistor26is coated by the conformal protection layer40and is buried in the dielectric layer42.

In an alternative embodiment, the bipolar junction transistor26may be replaced by a different type of device structure such as, for example, a field-effect transistor or an extended-drain field-effect transistor.

With reference toFIG. 2in which like reference numerals refer to like features inFIG. 1and at a subsequent fabrication stage, a trench44is patterned by lithography and etching processes in the region22of the substrate12. The lithography process may include forming an etch mask by applying a layer of an organic photoresist by a spin coating process, pre-baking, exposing the photoresist to electromagnetic radiation projected through a photomask, baking after exposure, and developing with a chemical developer to define an opening over the intended location of the trench44. One or more etching processes, such as reactive ion etching processes, may be used to form the trench44with the etch mask present. The trench44has sidewalls43that extend through the dielectric layer42, the conformal protection layer40, and the shallow well18to the deep well20. A portion of the deep well20is exposed at a bottom45of the trench44. In the representative embodiment, the trench44extends to, but does not penetrate into, the deep well20. In an alternative embodiment, the trench44may extend into, but not fully through, the deep well20. In an alternative embodiment, the trench44may extend fully through the deep well20and into the underlying portion of the substrate12.

The depth or height of the trench44may be selected according to the wavelength of the electromagnetic radiation to be detected by the photodiode subsequently formed in the trench44. The depths of the shallow trench isolation regions14and deep trench isolation regions16in the substrate12may be adjusted, as needed, in conjunction with the selected height of the trench44to supply suitable electrical isolation.

Sidewall spacers46are formed on the sidewalls43of the trench44. The sidewall spacers46may be composed of a dielectric material, such as silicon nitride, that is conformally deposited and then etched with an anisotropic etching process, such as reactive ion etching. The portion of the trench44in the substrate12is surrounded on all sides by the sidewall spacers46, which are arranged between the trench44and the semiconductor material of the shallow well18. The portion of the trench44in the dielectric layers40,42is also surrounded on all sides by the sidewall spacers46. The bottom of the trench44is cleared of dielectric material by the etching process such that a portion of the deep well20is revealed at the bottom of the trench44.

With reference toFIG. 3in which like reference numerals refer to like features inFIG. 2and at a subsequent fabrication stage, a photodiode48is formed inside the trench44. The photodiode48may be a p-n junction photodiode, a p-i-n junction photodiode, p-i-p-n (avalanche) junction photodiode, p-i-p-i-n (avalanche) junction photodiode, etc. The photodiode48has a top surface49that may be substantially coplanar or coplanar with a top surface of the dielectric layer42and, as a result, the top surface49of the photodiode48may be considered to be elevated or raised relative to a top surface11of the substrate12. The photodiode48may include multiple layers50,52,54,56of single-crystal semiconductor material that are epitaxially grown in a layer stack on the portion of the substrate12exposed at the base on the trench44, and then planarized with, for example, reverse mask planarization. Alternatively, the photodiode48may be formed by a selective epitaxial growth process that does not require reverse mask planarization. The doped regions37and the deep well20cooperate to couple the bottom layer52of the photodiode48to the top surface11of the substrate12.

The layer50may be composed of single-crystal silicon that is epitaxially grown from the single-crystal semiconductor material of the substrate12and then annealed to provide recrystallization. The layer52may be composed of single-crystal silicon that is epitaxially grown from the layer50. The layer54may be composed of single-crystal silicon-germanium that is epitaxially grown from the layer52. The sidewall spacers46prohibit epitaxial growth from the covered sidewalls43of the trench44within the substrate12. The growth temperatures for the layers50,52,54and the anneal temperature may be on the order of, for example, 600° C. In an embodiment, the layers50,52, and54may be a single layer composed of silicon-germanium with a graded germanium content starting at 0% and ending at 100%. The layer56may be composed of germanium that is epitaxially grown from the layer54at a growth temperature that is less than the growth temperatures for the layers50,52,54. For example, the growth temperature for the layer56may be less than 600° C. In an embodiment, the layer56may be composed of silicon-germanium instead of germanium. In an embodiment, the layer54may be undoped such that the constituent germanium is intrinsic. In an embodiment, the layer54may be lightly n-type doped such that the constituent germanium is substantially intrinsic.

With reference toFIG. 4in which like reference numerals refer to like features inFIG. 3and at a subsequent fabrication stage, the conformal protection layer40and dielectric layer42, which are sacrificial, are removed after the photodiode48is formed. The conformal protection layer40and dielectric layer42may be removed by an etching process selective to the sidewall spacers46. As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process. Upper portions of the sidewall spacers46and an upper portion of the layer56of the photodiode48project above the top surface11of the substrate12due to the removal of the layers40,42. The layers50,52,54and a lower portion of the layer56are located in the portion of the trench44in the substrate12that is at and below the top surface11of the substrate12.

An upper portion of the layer56of the photodiode48adjacent to its top surface49may be doped with a p-type dopant, such as boron, by a plasma doping technique, and the dopant may be optionally activated. The addition of the doped region proximate to the top surface49of the photodiode48defines a portion of a p-i-n (p-type/intrinsic/n-type) photodiode.

A silicide layer58may be formed over the layer56, as well as on portions of the bipolar junction transistor26such as the extrinsic base, collector contact, and emitter30of the bipolar junction transistor26, on the source, drain, gate, and body contact of a field-effect transistor in a different region of the substrate12, or on other active or passive devices. Silicide formation is followed by formation of an interconnect structure including an interlayer dielectric layer70and contacts72arranged in the interlayer dielectric layer70. Sections (not shown) of the silicide layer58may also form on the extrinsic base portion of the base layer28and the emitter30. A portion of the deep well20, doped regions37, and one or more of the contacts72may be used to contact the photodiode48. In addition, the doped regions35and one or more of the contacts72may be used to contact the subcollector34of the bipolar junction transistor26that is provided by another portion of the deep well20.

The substrate12may be diced to provide a single die or chip that monolithically integrates both the photodiode48and the bipolar junction transistor26. The photodiode48and the bipolar junction transistor26each utilize portions of the same deep well20for different purposes. In particular, the photodiode48utilizes a portion of the deep well20as an electrode and the bipolar junction transistor26utilizes a different portion of the deep well20as the subcollector34. These different portions are electrically isolated from each other.

With reference toFIG. 5in which like reference numerals refer to like features inFIG. 2and in accordance with alternative embodiments, the trench44may be formed to penetrate into, but not fully through, the deep well20. For example, after the initial etching process forms the trench44and the sidewall spacers46are formed, a wet chemical etching process with crystallographic selectivity may be used to etch the single-crystal semiconductor material of the substrate12exposed at the bottom of the trench44. The surfaces of the substrate12at the bottom45of the trench44below the sidewall spacers46may have inclined sections that extend inwardly to converge and define a chevron shape or V-shape. For example, the wet chemical etching process may etch along the (111) planes of single-crystal silicon.

With reference toFIG. 6in which like reference numerals refer to like features inFIG. 5and at a subsequent fabrication stage, processing continues as described in connection withFIGS. 3 and 4. In particular, the photodiode48is formed in the trench44as described in connection withFIG. 3. The lowest portion of the photodiode48has inclined lower surfaces60that match the chevron shape of the inclined surfaces of the substrate12at the bottom45of the trench44. Defects may be gettered and trapped in the lower portion of the photodiode48proximate to these inclined surfaces during epitaxial growth of the photodiode48.

With reference toFIG. 7in which like reference numerals refer to like features inFIG. 2and in accordance with alternative embodiments, the trench44may be formed to penetrate into, but not completely through, the deep well20in a different manner. For example, after the initial etching process forms the trench44and the sidewall spacers46are formed, the substrate12may be oxidized at the bottom of the trench44and a wet chemical etching process may be used to strip the oxide. The oxidation and oxide stripping, which may be iterated, may operate to remove damage to the substrate12resulting from the initial etching process forming the trench44in preparation for epitaxial growth of the photodiode48. The sidewalls43of trench44are extended in depth at the bottom45of the trench44below the sidewall spacers46.

With reference toFIG. 8in which like reference numerals refer to like features inFIG. 7and at a subsequent fabrication stage, processing continues as described in connection withFIGS. 3 and 4. In particular, the photodiode48is formed in the trench44as described in connection withFIG. 3. The lowest portion of the photodiode48is positioned in the portion of the trench44located in the deep well20instead of being located at the interface between the wells18,20.

With reference toFIG. 9in which like reference numerals refer to like features inFIG. 2and in accordance with alternative embodiments, the trench44may be formed to penetrate into, but not completely through, the deep well20in still a different manner. For example, after the initial etching process forms the trench44and the sidewall spacers46are formed, a wet chemical etching process with a lateral etching component may be used to widen and deepen the trench44. The widened and deepened lowest portion of the trench44is located in the deep well20and extends below and outwardly beneath the sidewall spacers46. The widened and deepened lower portion of the trench44includes additional sidewalls62that intersect the bottom45of the trench44.

With reference toFIG. 10in which like reference numerals refer to like features inFIG. 9and at a subsequent fabrication stage, processing continues as described in connection withFIGS. 3 and 4. In particular, the photodiode48is formed in the trench44as described in connection withFIG. 3. The lowest portion of the photodiode48is located in the widened and deepened lower portion of the trench44. The lower portion of the photodiode48is wider than an upper portion of the photodiode48, which is positioned interior of the sidewall spacers46. Defects may be gettered and trapped in the widened and deepened portion of the trench44during epitaxial growth of the photodiode48.

With reference toFIG. 11in which like reference numerals refer to like features inFIG. 3and in accordance with alternative embodiments, the photodiode48may be formed such that the top surface49of is coplanar or substantially coplanar with the top surface11of the substrate12. To that end, the dielectric layer42may be removed after forming the trench44and before forming the sidewall spacers46on the sidewalls43of the trench44. A patterned etchback to the level of the conformal protection layer40may be used to provide the coplanarity or substantial coplanarity, and may eliminate the need for a polishing process to provide planarization.

With reference toFIGS. 12-15in which like reference numerals refer to like features inFIG. 3and in accordance with alternative embodiments, an additional bipolar junction transistor74may be formed in the same manner as the bipolar junction transistor26. The bipolar junction transistors26,74may be wired with other passive elements (e.g., resistors) to construct a circuit68(FIG. 15) for a trans-impedance amplifier that is coupled to the photodiode48. The bipolar junction transistors26,74and the photodiode48, which may be placed in various different layouts, may form a pixel of a Light Detection and Ranging (LIDAR) array.

For example and as shown inFIG. 12, the bipolar junction transistor26may be arranged along one sidewall43of the trench44holding the photodiode48with its emitter30aligned substantially parallel to the sidewall43, and the bipolar junction transistor74may be arranged along a sidewall43of the trench44holding the photodiode48with its emitter30aaligned substantially relative to the sidewall43. The different sidewalls43meet at a corner of the trench44.

As another example and as shown inFIG. 13, the bipolar junction transistor26may be arranged along opposite sidewalls43of the trench44holding the photodiode48with emitters30aligned substantially parallel to the opposite sidewalls43, and the bipolar junction transistor74may be arranged along a different set of opposite sidewalls43of the trench44holding the photodiode48with emitters30aaligned relative to the different set of sidewalls43. The different sets of sidewalls43surround the trench44with the sidewalls43in each set alternating with each other

As another example and as shown inFIG. 14, the bipolar junction transistor26may be arranged along a sidewall43of the trench44holding the photodiode48with its emitter30aligned substantially parallel to the adjacent sidewall43, and the bipolar junction transistor74may be arranged along an opposite sidewall43of the trench44holding the photodiode48with its emitter30aaligned relative to the adjacent sidewall43.

With reference toFIG. 16in which like reference numerals refer to like features inFIG. 3and in accordance with alternative embodiments, an additional photodiode48athat is similar to photodiode48may be concurrently formed, as previously described in connection with photodiode48, using the same substrate12. The additional photodiode48amay be positioned inside a trench similar to trench44that extends to a different portion of the deep well20, but with a different trench depth to provide multiple photodiodes that are sensitive to electromagnetic radiation at different wavelengths. For example, the thickness of the photodiode48amay be greater than the thickness of the photodiode48. In an alternative embodiment, the trenches44afor the photodiode48amay extend to the same depth as the trench for the photodiode48, but the photodiode48amay project to a different height above the top surface11of the substrate12than the photodiode48.