Nonvolatile memory device and method for fabricating the same

A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2011-0145056, filed on Dec. 28, 2011, which is incorporated herein by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a 3D nonvolatile memory device including a plurality of memory cells stacked perpendicular to a surface of a substrate and a method for fabricating the same.

2. Description of the Related Art

A nonvolatile memory device maintains data stored therein although power is turned off. Currently, various nonvolatile memory devices, such as a flash memory, are widely used.

In particular, as the improvement in the degree of integration of 2D nonvolatile memory devices, including a plurality of memory cells formed in a single layer over a semiconductor substrate, approaches the limits, a 3D nonvolatile memory device, including a plurality of memory cells formed along a channel layer protruding perpendicularly from a surface of a semiconductor substrate, has been proposed.

FIG. 1is a cross-sectional view of a conventional 3D nonvolatile memory device.

Referring toFIG. 1, the 3D nonvolatile memory device may include a word line WL extending in one direction while surrounding a channel layer CH protruding vertically from a substrate.

Although not illustrated inFIG. 1, the word line WL may be formed by the following process: a plurality of sacrificial layers are removed from a structure in which a plurality of interlayer dielectric layers and the plurality of sacrificial layers are alternately stacked along the channel layer CH. A conductive material is deposited to such a thickness as to fill the space from which the sacrificial layers is were removed, and an etching process for etching the deposited conductive material for the respective layers is performed. At this time, line or dot-shaped voids may be formed in the word line WL, and may serve as a factor that increases the resistance of the word line WL.

In particular, during the etching process, the conductive material is further etched at a top word line WL than a bottom word line WL. Therefore, the top of the word line WL is formed to have a smaller volume than the bottom of the word line WL. Accordingly, the top of the word line WL has a relatively large resistance value. Furthermore, the conductive material may be excessively etched to open the word line WL (refer to symbol A), or the resistance of the word line WL may rapidly increase (refer to symbol B). Therefore, there is demand for the development of a structure capable of solving such concerns.

SUMMARY

An exemplary embodiment of the present invention is directed to a nonvolatile memory device and a method for fabricating the same, which is capable of increasing the volume of a gate electrode layer without an electrical bridge between gate electrode layers, thereby reducing the resistance of the gate electrode layer.

In accordance with an exemplary embodiment of the present invention, a nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.

In accordance with another embodiment of the present invention, a method for fabricating a nonvolatile memory device includes, alternately stacking a plurality of interlayer dielectric layers and a plurality of sacrificial layers over a substrate, forming a channel hole by selectively etching the plurality of interlayer dielectric layers and the plurality of sacrificial layers, forming a channel layer in the channel hole, forming a slit hole adjacent to the channel hole so that the slit hole passes through the plurality of interlayer dielectric layers and the plurality of sacrificial layers, removing the plurality of sacrificial layers exposed through the slit hole to form a plurality of spaces, forming a first gate electrode layer in each of the plurality of spaces, and forming a plurality of second gate electrode layers, each coupled to a corresponding first gate electrode layer, so that each of the plurality of second gate electrode layers protrudes from the plurality of interlayer dielectric layers.

DETAILED DESCRIPTION

FIGS. 2A to 2Fare cross-sectional views explaining a nonvolatile memory device and a method for fabricating the same in accordance with a first embodiment of the present invention. In particular,FIG. 2Fis a cross-sectional view of the nonvolatile memory device in accordance with the first embodiment of the present invention, andFIGS. 2A to 2Eare cross-sectional views illustrating intermediate processes for fabricating the nonvolatile memory device ofFIG. 2F.

Referring toFIG. 2A, a plurality of interlayer dielectric layers110and a plurality of sacrificial layers120are alternately stacked over a substrate100. The substrate100may include a semiconductor substrate such as single crystal silicon, and may have a given lower structure (not illustrated). Hereinafter, the structure in which the plurality of interlayer dielectric layers110and the plurality of sacrificial layers120are alternately stacked is referred to as a gate structure, for convenience of description.

Here, the interlayer dielectric layer110may be disposed at the lowermost part and the uppermost part of the gate structure, and may be formed of an oxide-based material such as silicon oxide (SiO2). Furthermore, the sacrificial layer120is removed during a subsequent process, and may provide a space in which a gate electrode layer (to be described below) is to be formed. The sacrificial layer120may be formed of a material (e.g., a nitride-based material) having an etching selectivity that is substantially the same as the etching selectivity of the interlayer dielectric layer110.FIG. 2Aillustrates four sacrificial layers120. However, this is only an example, and four or more sacrificial layers or three or less sacrificial layers may be formed.

Referring toFIG. 2B, the gate structure is selectively etched to form a channel hole H1exposing the substrate100. The channel hole H1may have a circular or elliptical shape, when seen from the top. In this embodiment of the present invention, a plurality of channel holes H1may be arranged in a matrix shape.

A memory layer130is formed on the sidewall of the channel hole H1, and a channel layer140is formed in the channel hole H1having the memory layer130formed therein.

Here, the memory layer130may be formed by sequentially depositing a charge blocking layer, a charge trap layer, and a tunnel insulation layer. The tunnel insulation layer serves to tunnel charges, and may be formed of oxide, for example. The charge trap layer serves to trap charges to store data, and may be formed of nitride, for example. The charge blocking layer serves to block the charges within the charge trap layer from moving to the outside, and may be formed of oxide, for example. That is, the memory layer130may have a triple layer structure of oxide-nitride-oxide (ONO).

Furthermore, the channel layer140may be formed of a semiconductor material, for example, polysilicon. Meanwhile, in this embodiment of the present invention, the channel layer140may be formed to such a thickness as to completely fill the channel hole H1, but the present invention is not limited thereto. In another embodiment of the present invention, the channel layer140may be formed to such a thickness as not to completely fill the channel hole H1.

Referring toFIG. 2C, the gate structure at both sides of the channel hole H1is selectively etched to form a slit hole T passing through the interlayer dielectric layers110and the sacrificial layers120(not shown). At this time, a plurality of slit holes T may be formed in a slit shape extending in a direction crossing the cross-section ofFIG. 2C, and arranged in parallel to each other.

The sacrificial layers120and interlayer dielectric layers110, exposed through the slit hole T, are removed using a wet etching process. The remaining interlayer dielectric layer110is referred to as an interlayer dielectric layer pattern110A.

Referring toFIG. 2D, a barrier metal layer150is formed along an inner wall of the slit hole T, in spaces formed when the sacrificial layers120were removed. The barrier metal layer150serves to improve interfacial characteristics between the interlayer dielectric layer pattern110A, the memory layer130, and a first gate electrode layer (to be described below). The barrier metal layer150may be formed by conformally depositing titanium nitride (TiN).

A first gate electrode conductive layer160is formed on the barrier metal layer150in the spaces formed when the sacrificial layers120were removed. The first gate electrode conductive layer160may be formed by depositing a conductive material, such as a metal, using, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD). For example, the first gate electrode conductive layer160may be formed by forming a tungsten (W) core and then depositing bulk tungsten.

Referring toFIG. 2E, the barrier metal layer150and the first gate electrode conductive layer160are separated into the respective layers by etching the barrier metal layer150and the first gate electrode conductive layer160in the slit hole T until side surfaces of the interlayer dielectric layer patterns110A are exposed.

Here, the volume of the barrier metal layer150, which has a relatively large resistance value, may be reduced as much as possible. The barrier metal layer150may be etched to a larger depth than the first gate electrode conductive layer160, based on a difference in etch rate between the barrier metal layer150and the first gate electrode conductive layer160. The etched barrier metal layer150and the etched first gate electrode conductive layer160, both of which remain between the interlayer dielectric layer patterns110A, are referred to as a barrier metal layer pattern150A and a first gate electrode layer160A, respectively.

Referring toFIG. 2F, a second gate electrode layer170is formed to cover the first gate electrode layer160A. The second gate electrode layer170protrudes from the interlayer dielectric layer pattern110A, and may have a larger width in a direction perpendicular to a surface of the substrate100than a width of the first gate electrode layer160A.

In particular, the second gate electrode layer170may include a metal or the like, and may be formed by selectively depositing bulk tungsten without tungsten nucleation. Specifically, when the first gate electrode layer160A is formed of tungsten, bulk tungsten is deposited on the already-formed tungsten layer, i.e., the first gate electrode layer160A. Therefore, a separate mask process or gate electrode separation process is not necessary. Furthermore, when the selective deposition is used, it is possible to prevent an electrical bridge, between the second gate electrode layers170, from being formed at minute intervals. Furthermore, influence by a loading effect may be minimized to uniformly deposit tungsten to the edge of a memory cell.

As the result of this process, a gate electrode layer, including the first gate electrode layer160A and the second gate electrode layer170coupled to the first gate electrode layer160A, is formed. In particular, as the second gate electrode layer170is formed, the volume reduction of the first gate electrode layer160A, which was caused by the etching in the gate electrode separation process may be compensated, and voids formed in the first gate electrode layer160A are filled with the second gate electrode layer170. Accordingly, the resistance of the gate electrode layer may be reduced without change in critical dimension.

The nonvolatile memory device in accordance with the first embodiment of the present invention, as illustrated inFIG. 2F, may be fabricated by the above-described fabrication method.

Referring toFIG. 2F, the nonvolatile memory device, in accordance with the first embodiment of the present invention includes the channel layer140that protrudes perpendicular to the surface of the substrate100, the plurality of interlayer dielectric layer patterns110A and gate electrode layers, both of which are alternately stacked along the channel layer140, the barrier metal layer patterns150A interposed between the interlayer dielectric layer patterns110A, the gate electrode layer, which may protrude from the interlayer dielectric layer patterns110A, and the memory layer130, interposed between the channel layer140and the gate electrode layers.

Here, each of the gate electrode layers may include the first gate electrode layer160A, which is positioned between the interlayer dielectric layer patterns110A, coupled to the second gate electrode layer170, which protrudes from the interlayer dielectric layer patterns110A. In particular, the second gate electrode layer170may be formed by selectively depositing tungsten, and may have a larger width in a direction perpendicular to the surface of the substrate100than the first gate electrode layer160A.

FIG. 3is a cross-sectional view explaining a nonvolatile memory device and a method for fabricating the same in accordance with a second embodiment of the present invention. In this embodiment of the present invention, the detailed descriptions of the same components as those of the first embodiment of the present invention will be omitted. First, the processes ofFIGS. 2A to 2Eare performed in the same manner as the first embodiment of the present invention, and a process ofFIG. 3is performed.

Referring toFIG. 3, the barrier metal layer pattern150A and the first gate electrode layer160A are partially etched, and a second gate electrode layer170is formed to cover the first gate electrode layer160A. The second gate electrode layer170may protrude from the interlayer dielectric layer pattern110A.

In particular, the second gate electrode layer170may include a metal or the like, and may be formed by selectively depositing bulk tungsten without tungsten nucleation. At this time, the second gate electrode layer170may have a larger volume than the first gate electrode layer160A, and the volume of the barrier metal layer pattern150A having a relatively large resistance value may be reduced as much as possible.

In the second embodiment of the present invention, the barrier metal layer pattern150A and the first gate electrode layer160A may be removed to a larger depth than in the first embodiment of the present invention, thereby increasing the volume of the second gate electrode layer170, which has a relatively small resistance value. Accordingly, the resistance of the gate electrode layer may be reduced more than in the first embodiment of the present invention.

FIGS. 4A and 4bare cross-sectional views explaining a nonvolatile memory device and a method for fabricating the same in accordance with a third embodiment of the present invention. In this embodiment of the present invention, the detailed descriptions of the same components, as identified in the first embodiment of the present invention, will be omitted. First, the processes ofFIGS. 2A to 2Eare performed in the same manner as the first embodiment of the present invention, and processes ofFIGS. 4A and 4Bare performed.

Referring toFIG. 4A, the interlayer dielectric layer patterns110A are partially removed to a given depth. As the result of this process, the first gate electrode layers160A may protrude from the interlayer dielectric layer patterns110A.

Referring toFIG. 4B, a second gate electrode layer170is formed to surround the protruding portion of the first gate electrode layer160A. The second gate electrode layer170may include a metal or the like, and may be formed by selectively depositing bulk tungsten without tungsten nucleation. At this time, since the width of the slit hole T is increased from CD1(as shown inFIG. 2F) to CD2by the process ofFIG. 4A, the volume of the second gate electrode layer170may be further increased.

In the third embodiment of the present invention, the first gate electrode layer160A is formed to protrude from the interlayer dielectric layer pattern110A, and the second gate electrode layer170is formed to surround the protruding portion of the first gate electrode layer160A. Because the width of the silt hole T has been increased from CD1to CD2, the volume of the second gate electrode layer170may be increased. This increase in volume of the second gate electrode layer170makes it possible to further reduce the resistance of the gate electrode layer than in the first embodiment of the present invention.

FIGS. 5A to 5Hare cross-sectional views explaining a nonvolatile memory device and a method for fabricating the same in accordance with a fourth embodiment of the present invention. In this embodiment of the present invention, the detailed descriptions of the same components, as identified in the first embodiment of the present invention, will be omitted.

Referring toFIG. 5A, a first pass gate electrode layer200is formed over a substrate100. The substrate100may include a semiconductor substrate such as single crystal silicon, and the first pass gate electrode layer200may be formed of a conductive material, for example, doped polysilicon or metal.

The first pass gate electrode layer200is selectively etched to form a groove, and a sacrificial layer pattern210is formed in the groove.

Here, the sacrificial layer pattern210is removed during a subsequent process, and provides a space where a sub-channel hole (to be described below) is to be formed. The sacrificial layer pattern210may be formed of a material having an etching selectivity that is substantially the same as the etching selectivity of the first and second pass gate electrode layers200and220and of an interlayer dielectric layer110and a sacrificial layer all of which will be described below. Furthermore, the sacrificial layer pattern210may be arranged in a matrix shape having a major axis in the cross-sectional direction ofFIG. 5Aand a minor axis in a direction crossing the cross-sectional direction.

The second pass gate electrode layer220is formed over the first pass gate electrode layer200and the sacrificial layer pattern210. The second pass gate electrode layer220may be formed of a conductive material, for example, doped polysilicon or metal. Meanwhile, the first and second pass gate electrode layers200and220may surround the sacrificial layer pattern210, and function as a gate electrode of a pass transistor.

Referring toFIG. 5B, a plurality of interlayer dielectric layers110and a plurality of sacrificial layers120are alternately stacked over the second pass gate electrode layer220.

Here, the interlayer dielectric layer110may be formed of an oxide-based material. The sacrificial layer120is removed during a subsequent process and provides a space where a gate electrode (to be described below) is to be formed. The sacrificial layer120may be formed of a material (e.g., a nitride-based material) having an etching selectivity that is substantially the same as the etching selectivity of the interlayer dielectric layer110.

Referring toFIG. 5C, the gate structure and the second pass gate electrode layer220are selectively etched to form a pair of channel holes H1exposing the sacrificial layer pattern210. The pair of channel holes H1provide a space in which a channel layer (to be described below) is to be formed, and may be arranged at each sacrificial layer pattern210.

The sacrificial layer pattern210, exposed by the pair of the channel holes H1, is removed. At this time, a wet etching process, using an etching selectivity that is substantially the same as the etching selectivity of the first and second pass gate electrode layers200and220, and the gate structure may be performed to remove the sacrificial layer pattern210. As the result of this process, a sub-channel hole H2, coupling the pair of channel holes H1, is formed in the space where the sacrificial layer pattern210was removed.

Referring toFIG. 5D, a memory layer130and a channel layer140are sequentially formed along the inner walls of the pair of channel holes H1and the sub channel hole H2.

Here, the memory layer130may be formed by sequentially depositing a charge blocking layer, a charge trap layer, and a tunnel insulation layer, and may have a triple layer structure of ONO. Meanwhile, the channel layer140may be divided into a main channel layer, which may be used as a channel of a memory cell or select transistor, and a sub channel layer used as a channel of a pass transistor. The channel layer140may be formed of a semiconductor material, such as polysilicon.

Referring toFIG. 5E, the gate structure at both sides of the channel hole H1is selectively etched to form a plurality of slit holes T passing through the interlayer dielectric layers110and the sacrificial layers120(not shown). The plurality of slit holes T may have a slit shape extending in a direction crossing the cross-section ofFIG. 5Eand may be arranged in parallel to each other.

The sacrificial layers120and the interlayer dielectric layers110, exposed through the slit holes T, are removed using a wet etching process. The remaining interlayer dielectric layer110is referred to as an interlayer dielectric layer pattern110A.

Referring toFIG. 5F, a barrier metal layer150is formed along the inner wall of the slit hole T, in the spaces formed when the sacrificial layers120were removed. The barrier metal layer150may be formed by conformally depositing TIN, for example.

A first gate electrode conductive layer160is formed on the barrier metal layer150, in the spaces formed when the sacrificial layers120were removed. The first gate electrode conductive layer160may be formed by depositing a conductive material, such as metal, using, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD).

Referring toFIG. 5G, the barrier metal layer150and the first gate electrode conductive layer160fromFIG. 5Fare separated into the respective layers by etching the barrier metal layer150and the first gate electrode conductive layer160in the slit hole T until the side surfaces of the interlayer dielectric layer patterns110A are exposed.

Here, the barrier metal layer150may be etched to a larger depth than the first gate electrode conductive layer160, based on a difference in etch rate between the barrier metal layer150and the first gate electrode conductive layer160. The etched barrier metal layer150and the etched first gate electrode conductive layer160, both of which remain between the interlayer dielectric layer patterns110A, are referred to as a barrier metal layer pattern150A and a first gate electrode layer160A, respectively.

Referring toFIG. 5H, a second gate electrode layer170is formed to cover the first gate electrode layer160A. The second gate electrode layer170protrudes from the interlayer dielectric layer pattern110A and may have a larger width in a direction perpendicular to the surface of the substrate100than the first gate electrode layer160A.

In particular, the second gate electrode layer170may include a metal or the like, and may be formed by selectively depositing bulk tungsten without tungsten nucleation. As the result of this process, a gate electrode layer, including the first gate electrode layer160A and the second gate electrode layer170coupled to the first gate electrode layer160A, is formed.

The fourth embodiment of the present invention, as shown inFIG. 5H, is different from the first embodiment of the present invention in that the pass gate electrode, including the first and second pass gate electrode layers200and220, is formed under the gate structure, and the pass gate electrode has the sub-channel layer coupling the pair of main channel layers.

FIG. 6is a cross-sectional view of the nonvolatile memory device in accordance with the embodiments of the present invention.FIGS. 7A and 7Bare graphs showing results obtained by measuring surface resistance Rs of a word line.

Referring toFIG. 6, as the second gate electrode layer is formed by selectively depositing a metal such as tungsten, the volume of the gate electrode layer of the memory cell, that is, the word line WL increases in an arrow direction. Accordingly, it is possible to prevent an opening or resistance increase of the word line WL, which was the problem of the conventional nonvolatile memory device.

Referring toFIGS. 7A and 7B, <a> indicates word line surface resistance Rs of the conventional nonvolatile memory device, <b> indicates word line surface resistance Rs of the nonvolatile memory device in accordance with the embodiments of the present invention, in which bulk tungsten is selectively deposited to a thickness of 75 Å, and <c> indicates word line surface resistance Rs of the nonvolatile memory device in accordance with the embodiments of the present invention, in which bulk tungsten is selectively deposited to a thickness of 150 Å.

Here, in the cases of <b> and <c>, a difference in surface resistance Rs between a top word line and a bottom word line is less than in the case of <a>. Specifically, the difference in surface resistance Rs is reduced by 38% in the case of <b> and 52% in the case of <c>, as compared with the case of <a>.

In accordance with the embodiments of the present invention, the volume of the gate electrode layer may be increased without an electrical bridge between the gate electrode layers, which makes it possible to reduce the resistance of the gate electrode layer.

While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without is departing from the spirit and scope of the invention as defined in the following claims.