TIME DOMAIN ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERTING METHOD

In analog-to-digital conversion, a plurality of stages configured in a sequence to sequentially decide a plurality of bits in successive-approximation, each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses; and a plurality of clock generating circuits respectively corresponding to a plurality of first stages among the plurality of stages, each of the plurality of clock generating circuit configured to generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2022-0161571 filed in the Korean Intellectual Property Office on Nov. 28, 2022, the entire contents of which are incorporated herein by reference.

BACKGROUND

The disclosure relates to a time domain analog-to-digital converter and an analog-to-digital converting method.

(b) Description of the Related Art

An analog-to-digital converter (ADC) receives an analog input voltage and converts it into a digital signal that can be sent to other devices. ADCs may be used in various signal processing devices.

A voltage domain ADC outputs the difference in input voltages as a digital value. This process may take a while due to a settling time of a capacitor and a decision time of a comparator.

SUMMARY

Some example embodiments may provide a time domain analog-to-digital converter and an analog-to-digital converting method for reducing a waiting time.

According to some example embodiments, an analog-to-digital converter may include a plurality of stages and a plurality of clock generating circuits. The plurality of stages may be configured in a sequence to sequentially decide a plurality of bits in a successive-approximation. Each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses, the plurality of positive pulses respectively input to the plurality of stages and the plurality of negative pulses respectively input to the plurality of stages. The plurality of clock generating circuits respectively correspond to a plurality of first stages among the plurality of stages. Each of the plurality of clock generating circuit may generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.

According to some example embodiments, an analog-to-digital converter may include a first time comparator, a first delay circuit, a clock generating circuit, a second time comparator, and a second delay circuit. The first time comparator may operate in response to a first clock and decide a first bit based on a first comparison result of comparing a first positive pulse and a first negative pulse. The first delay circuit may delay either one of the first positive pulse and the first negative pulse by a first reference time based on a value of the first comparison result. The clock generating circuit may generate a second clock in response to the first comparison result. The second time comparator may operate in response to the second clock and decide a second bit based on a second comparison result of comparing a second positive pulse and a second negative pulse output from the first delay circuit. The second delay circuit may delay either one of the second positive pulse and the second negative pulse by a second reference time based on a value of the second comparison result.

According to some example embodiments, an analog-to-digital converting method may be provided. The analog-to-digital converting method may include receiving a first positive pulse and a first negative pulse, comparing the first positive pulse and the first negative pulse in response to a first clock to generate a first comparison result, deciding a first bit based on a value of the first comparison result, outputting a second positive pulse and a second negative pulse by delaying either one of the first positive pulse and the first negative pulse by a first reference time based on a value of the first comparison result, generating a second clock in response to the first comparison result, comparing the second positive pulse and the second negative pulse in response to the second clock to generate a second comparison result, and deciding a second bit based on a value of the second comparison result.

DETAILED DESCRIPTION OF THE EXAMPLE EMBODIMENTS

Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. The sequence of operations or steps is not limited to the order presented in the claims or figures unless specifically indicated otherwise. The order of operations or steps may be changed, several operations or steps may be merged, a certain operation or step may be divided, and a specific operation or step may not be performed.

As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Although the terms first, second, and the like may be used herein to describe various elements, components, steps and/or operations, these terms are only used to distinguish one element, component, step or operation from another element, component, step, or operation.

FIG.1is a block diagram illustrating an example of an analog-to-digital converter according to some example embodiments.

Referring toFIG.1, an analog-to-digital converter100according to some example embodiments may include a voltage-to-time converter (VTC) circuit110and a time-to-digital converter (TDC) circuit120.

The VTC circuit110may receive an analog signal and convert the analog signal into a time domain to generate a pulse. The analog signal may include a differential input voltage Vinp and Vinn. The pulse may include a positive pulse (or non-inverting pulse) Tinp generated based on a positive input voltage (or non-inverting input voltage) Vinp of the differential input voltage and a negative pulse (or inverting pulse) Tinn generated based on a negative input voltage (or inverting input voltage) Vinn of the differential input voltage. A time difference between a start edge (e.g., a rising edge) of the positive pulse Tinp and a start edge (e.g., a rising edge) of the negative pulse Tinn may be decided based on a voltage difference (e.g., correspond to a voltage difference) between the positive input voltage Vinp and the negative input voltage Vinn.

The TDC circuit120may receive the pulses Tinn and Tinp as input values in a time domain, and sequentially decide a plurality of bits (e.g., n bits) D0to Dn-1from the pulses Tinn and Tinp in a successive-approximation. When deciding a bit Diin a stage, the TDC circuit120may generate a clock to be used in a next stage. Here, i is an integer between 1 and n). That is, each stage of the TDC circuit120may decide a bit Diin response to a clock generated according to an operation of a previous stage. In this case, the first stage (or a start stage) of the TDC circuit120may decide the first bit (e.g., the most significant bit among the plurality of bits) D0in response to an input clock.

FIG.2is a block diagram showing an example of a VDC circuit of an analog-to-digital converter according to some example embodiments,FIG.3is a circuit diagram illustrating an example of a sample/hold (S/H) and ramp generating circuit in a VDC circuit shown inFIG.2,FIG.4is a circuit diagram illustrating an example of a pulse generating circuit in a VDC circuit shown inFIG.2, andFIG.5is a diagram illustrating an example of a signal generated by a VDC circuit shown inFIG.2.

Referring toFIG.2, a VTC circuit110according to some example embodiments may include an S/H and ramp generating circuit111and a pulse generating circuit112.

The S/H and ramp generating circuit111may sample a positive input voltage Vinn and hold the sampled voltage at a predetermined (or alternatively, desired) point in time. Similarly, the S/H and ramp generating circuit111may sample a negative input voltage Vinp and hold the sampled voltage at a predetermined (or alternatively, desired) point in time. In some example embodiments, as shown inFIG.3andFIG.5, the S/H and ramp generating circuit111may close a switch SW in response to an ON level of a sampling control signal SC to sample an input voltage Vin to a capacitor Cs. In addition, the S/H and ramp generating circuit111may hold a voltage Vout sampled in the capacitor Cs by opening the switch SW in response to an OFF level of the sampling control signal SC. InFIG.3, the input voltage Vin may be the positive input voltage Vinp or the negative input voltage Vinn shown inFIG.2, and the sampled voltage Vout may be a positive voltage Voutp or a negative voltage Voutn shown inFIG.5.

The S/H and ramp generating circuit111may increase the voltage Voutp obtained from sampling the positive input voltage Vinp in a ramp form, and increase the voltage Voutn obtained from sampling the negative input voltage Vinn in a ramp form as well. In some example embodiments, as shown inFIG.4andFIG.5, the S/H and ramp generating circuit111may inject a current Ir into the capacitor Cs to increase the voltage Vout sampled in the capacitor Cs in the ramp form. InFIG.4, the voltage Vout may be the positive voltage Voutp or the negative voltage Voutn shown inFIG.5.

The pulse generating circuit112may generate a pulse Tinp having a predetermined (or alternatively, desired) level (or a first level) from a point in time at which the voltage Voutp, which increases in the ramp form, becomes a predetermined (or alternatively, desired) voltage Vt, and the voltage Voutp increases in a ramp form, and generate a pulse Tinn having the predetermined (or alternatively, desired) level from a point in time at which the voltage Voutn becomes the predetermined (or alternatively, desired) voltage Vt. The predetermined (or alternatively, desired) level may be, for example, a high level. In this case, the pulses Tinp and Tinn may be switched from a low level to the high level at the point in time when the voltages Voutp and Voutn, which increase in the ramp form, become the predetermined (or alternatively, desired) voltage Vt. InFIG.5, since the positive input voltage Vinp is higher than the negative input voltage Vinn, a start edge (e.g., a rising edge) of the pulse Vinp generated based on the positive input voltage Vinp may be earlier than a start edge (e.g., a rising edge) of the pulse Vinn generated based on the negative input voltage Vinn. Next, the pulse generating circuit112may reset the voltages Vinp and Vinn increasing in the ramp form at appropriate timings. When the voltages Vinp and Vinn fall below the predetermined (or alternatively, desired) voltage Vt, the pulses Tinp and Tinn may be switched to the low level (or a second level). Accordingly, the pulse generating circuit112may generate the pulses Tinp and Tinn in the time domain. In this case, the time difference between the start edge of the pulse Tinp and the start edge of the pulse Tinn may be determined based on the voltage difference between the input voltage Vinp and the input voltage Vinn.

FIG.6is a block diagram illustrating an example of a TDC circuit of an analog-to-digital converter according to some example embodiments, andFIG.7is a diagram illustrating an example of a signal generated by a TDC circuit shown inFIG.6.

Referring toFIG.6, a TDC circuit600according to some example embodiments may include a plurality of stages6100,6101,6102, and6103, and one or more clock generating circuits6201,6202, and6203. AlthoughFIG.6shows four stages6100to6103and three clock generating circuits6201to6203, the number of stages6100to6103and the number of clock generating circuits6201to6203are not limited thereto. The stages6100to6103are in a sequence with one of the clock generating circuits6201to6203between each of the stages. The clock generating circuits6201to6203may also be in a sequence. A next stage may refer to a stage which receives input from a previous stage in the sequence. Restated a previous stage may provide an input to a next stage. For example, when the TDC circuit600decide n bits, the TDC circuit600may include n stages and (n−1) clock generating circuits.

Each stage610imay receive a positive pulse Tinpiand a negative pulse Tinni. Here, i is an integer between 0 and 3. Each stage610imay compare the positive pulse Tinpiand the negative pulse Tinniin response to an input clock CLKiof a corresponding stage610i, and decide a bit Diof the corresponding stage610ibased on a comparison result. In some example embodiments, each stage610imay compare a start edge of the positive pulse Tinpiwith a start edge of the negative pulse Tinni, decide the bit Dias ‘1’ if the start edge of the positive pulse Tinpiis earlier than the start edge of the negative pulse Tinni, and decide the bit Dias ‘0’ if the start edge of the negative pulse Tinniis earlier than the start edge of the positive pulse Tinpi. When the TDC circuit600includes the four stages6100to6103, the TDC circuit600may decide four bits D0to D3. In this case, among the four bits, the first stage6100(or start stage) may decide the most significant bit D0the second stage6101may decide the second most significant bit D1, the third stage6102may decide the third most significant bit D2, and the fourth stage6103may decide the least significant bit D3. The start stage does not have a previous stage in the sequence of stages.

Each stage610imay output input pulses Tinpi+1and Tinni+1of a next stage610i+1by delaying either the positive pulse Tinpior the negative pulse Tinniby a reference time of the corresponding stage610ibased on the comparison result (e.g., the decided bit) and without delaying the other pulse by the reference time of the corresponding stage610i. In some example embodiments, the stage610imay delay two pulses Tinpiand Tinniby a basic delay value, and then output the input pulses Tinpi+1and Tinni+1of the next stage610i+1by delaying one pulse by the reference time of the corresponding stage610iand without delaying the other pulse. For example, when the comparison result indicates that the start edge of the positive pulse Tinpiis earlier than the start edge of the negative pulse Tinni(e.g., when the decided bit Diis ‘1’), the stage610imay output the pulse Tinpi+1by delaying the positive pulse Tinpiby the reference time, and output the pulse Tinni+1without delaying the negative pulse Tinni. When the comparison result indicates that the start edge of the negative pulse Tinniis earlier than the start edge of the positive pulse Tinpi(e.g., when the decided bit Diis ‘0’), the stage610imay output the pulse Tinpi+1without delaying the positive pulse Tinpi, and output the pulse Tinni+1by delaying the negative pulse Tinniby the reference time. In this case, the first stage6100may receive pulses input to the TDC circuit600(e.g., output pulses Tinp and Tinn of the VTC circuit shown inFIG.2) as the input pulses Tinp0and Tinn0. Further, since the last stage6103does not have a next stage, the last stage6103may not delay the input pulses Tinp3and Tinn3.

The TDC circuit600may use a binary search. Accordingly, each stage610i+1may use half of the reference time of the previous stage610ias its own reference time. In this case, the first stage6100may use half of a reference time Tref of the TDC circuit600as its own reference time Tref/2. Accordingly, the second stage6101may use Tref/4 as its own reference time, and the third stage6101may use Tref/8 as its own reference time.

The first stage6100may receive an input clock CLK0of the TDC circuit600as its own clock and decide the bit D0of the corresponding stage6100in response to the input clock CLK0. Each (or alternatively, at least one) of stages610iother than the first stage6100may decide the bit Diof the corresponding stage610iin response to a clock CLKigenerated by the corresponding clock generating circuit620i. Here, i is an integer between 1 and 3. The clock generating circuit620imay generate the clock CLKiof the corresponding stage620iin response to an operation of the previous stage620i−1. In some example embodiments, the clock generating circuit620imay generate a start edge (e.g., a rising edge) of the clock CLKiof the corresponding stage620iin response to the operation of the previous stage620i−1. In some example embodiments, the clock generating circuit620imay reset the clock CLKiof the corresponding stage620iin response to an operation of the corresponding stage620i. In some other example embodiments, the clock generating circuit620imay reset the clock CLKiof the corresponding stage620iwhen the clock CLKi+1is generated in the next clock generating circuit620i+1. In some example embodiments, the clock generating circuit620imay reset the clock CLKiby generating an end edge (e.g., a falling edge) of the clock CLKiof the corresponding stage620i.

In some example embodiments, the operation of the stage620imay be a comparison operation in the stage620i. In this case, the clock generating circuit620imay generate the clock CLKiof the corresponding stage620iin response to the comparison result (e.g., the decision result) of the previous stage620i−1. The clock generating circuit620imay reset the clock CLKiof the corresponding stage620iin response to the comparison result (e.g., the decision result) of the corresponding stage620i.

In some example embodiments, when the clock CLKiof the stage620iis reset, the comparison result of the corresponding stage620imay be reset for the next operation.

As shown inFIG.7, for example, a positive pulse Tinp0and a negative pulse Tinn0later than the positive pulse Tinp0may be input to the first stage6100. When the input clock CLK0has an active level (e.g., a high level as a logic level) by a start edge (e.g., a rising edge) of the input clock CLK0. the first stage6100may compare the positive pulse Tinp0and the negative pulse Tinn0. In an example shown inFIG.7, because the positive pulse Tinp0is earlier than the negative pulse Tinn0, the first stage6100may decide ‘1’ based on a comparison result. Further, because the positive pulse Tinp0is earlier than the negative pulse Tinn0, the first stage6100may output an input pulse Tinp1of the second stage6101by delaying the positive pulse Tinp0by half Tref/2 of the reference time Tref of the TDC circuit600, and output an input pulse Tinn1of the second stage6101without delaying the negative pulse Tinn0by half Tref/2 of the reference time Tref. The first clock generating circuit6201may activate a clock CLK1when the comparison is completed in the stage6100(e.g., when the comparison result is generated in the stage6100). The first clock generating circuit6201may activate the clock CLK1by generating a start edge (e.g., a rising edge) of the clock CLK1.

When the clock CLK1output from the clock generating circuit6201has the active level, the second stage6101may compare the positive pulse Tinp1and the negative pulse Tinn1input from the first stage6100. In the example shown inFIG.7, because the positive pulse Tinp1is earlier than the negative pulse Tinn1, the second stage6101may decide ‘1’ based on a comparison result. Further, because the positive pulse Tinp1is earlier than the negative pulse Tinn1, the second stage6101may output an input pulse Tinp2of the third stage6102by delaying the positive pulse Tinp1by half Tref/4 of the reference time Tref/2 of the previous stage6100, and output an input pulse Tinn2of the third stage6102without delaying the negative pulse Tinn1by half Tref/4 of the reference time Tref/2. The first clock generating circuit6201may deactivate the clock CLK1when the comparison is completed in the stage6101. The first clock generating circuit6201may deactivate the clock CLK1by generating an end edge (e.g., a falling edge) of the clock CLK1. Further, the second clock generating circuit6202may activate a clock CLK2when the comparison is completed in the stage6101.

When the clock CLK2output from the clock generating circuit6202has the active level, the third stage6102may compare the positive pulse Tinp2and the negative pulses Tinn2input from the second stage6101. In the example shown inFIG.7, because the positive pulse Tinp2is earlier than the negative pulse Tinn2, the third stage6102may decide ‘1’ based on a comparison result. Further, because the positive pulse Tinp2is earlier than the negative pulse Tinn2, the third stage6102may output an input pulse Tinp3of the fourth stage6103by delaying the positive pulse Tinp2by half Tref/8 of the reference time Tref/4 of the previous stage6101, and output an input pulse Tinn3of the fourth stage6103without delaying the negative pulse Tinn2by half Tref/8 of the reference time Tref/4. The second clock generating circuit6202may deactivate the clock CLK2when the comparison is completed in the stage6102. Further, the third clock generating circuit6203may activate a clock CLK3when the comparison is completed in the stage6102.

When the clock CLK2output from the clock generating circuit6202has the active level, the fourth stage6103may compare the positive pulse Tinp3and negative pulse Tinn3input from the third stage6102. In the example shown inFIG.7, because the negative pulse Tinn3is earlier than the positive pulse Tinp3, the fourth stage6103may decide ‘0’ based on a comparison result. The third clock generating circuit6203may deactivate the clock CLK3when the comparison is completed in the stage6103.

Through the above-described processes, the TDC circuit600may convert the input voltage into a digital signal D0to D3having “1110”.

If each stage610idoes not use its own clock CLKiand the plurality of stages6100to6103use the same clock, the clock should maintain the active level until the input pulse is propagated through the plurality of stages6100to6103. Therefore, because each stage610imay operate again in the next clock cycle after the decision at the plurality of stages6100to6103is completed, a waiting time of the stage610imay increase. However, according to the above-described example embodiments, each stage610imay operate in response to its own clock CLKiwithout waiting for the completion of the decision at the other stages, so that the waiting time may be reduced. That is, a pipelined successive-approximation TDC circuit may be provided.

Further, a method of generating a clock of a next stage by delaying the input clock CLK0may be used. This method may increase power consumption in a delay line for delaying the clock, and reset the comparator of the stage before the comparison is completed. However, since the pipelined successive-approximation TDC circuit described above does not use the delay line, power consumption can be reduced. Further, since a decision of a stage is completed and then a next stage operates in response to the clock, the comparator may not be reset before the operation is completed.

FIG.8is a block diagram illustrating an example of a stage in a TDC circuit of an analog-to-digital converter according to some example embodiments, andFIG.9is a diagram illustrating an example of a clock generating circuit in a TDC circuit of an analog-to-digital converter according to some example embodiments.

Referring toFIG.8, a stage800may include a time comparator810, and delay circuits820and830.

The time comparator810may compare an input positive pulse Tinpiand an input negative pulse Tinni. The time comparator810may compare a time of a start edge of the positive pulse Tinpiand a time of a start edge of the negative pulse Tinni, and output a comparison result CMPi. In some example embodiments, an output of the time comparator810may include the output CMPiand a complementary output CMPbihaving a complementary value of the output. In some example embodiments, the time comparator810may output ‘1’ as the output CMPiwhen the start edge of the positive pulse Tinpiis earlier than the start edge of the negative pulse Tinpi, and output ‘0’ as the output CMPiwhen the start edge of the positive pulse Tinpiis later slower than the start edge of the negative pulse Tinni. The time comparator810may output ‘0’ as the complementary output CMPbiwhen outputting ‘1’ as the output CMPi, and output ‘1’ as the complementary output CMPbiwhen outputting ‘0’ as the output CMPi. The output CMPiof the time comparator810may be a decision value of the stage800.

The delay circuit820may receive the positive pulse Tinpiand operate in response to the output CMPiof the time comparator810. When the output CMPiof the time comparator810has a first value (e.g., ‘1’), the delay circuit820may output an input pulse Tinpi+1of a next stage by delaying the positive pulse Tinpiby a reference time Tref/2i+1of the stage800. When the output CMPiof the time comparator810has a second value (e.g., ‘0’), the delay circuit820may output the input pulse Tinpi+1of the next stage without delaying the positive pulse Tinpiby the reference time Tref/2i+1of the stage800. In some example embodiments, the delay circuit820may include a delay circuit that operates in response to the output CMPiof the time comparator810and delays an input by the reference time Tref/2i+1, and a delay circuit822that operates in response to the complementary output CMPbiof the time comparator810and does not delays an input by the reference time Tref/2i+1.

The delay circuit830may receive the negative pulse Tinniand operate in response to the output CMPiof the time comparator810. When the output CMPiof the time comparator810has the second value, the delay circuit830may output an input pulse Tinni+1of the next stage by delaying the negative pulse Tinniby the reference time Tref/2i+1of the stage800. When the output CMPiof the time comparator810has the first value, the delay circuit820may output the input pulse Tinni+1of the next stage without delaying the negative pulse Tinniby the reference time Tref/2i+1of the stage800. In some example embodiments, the delay circuit830may include a delay circuit that operates in response to the complementary output CMPiof the time comparator810and delays an input by the reference time Tref/2i+1, and a delay circuit832that operates in response to the output CMPiof the time comparator810and does not delay an input by the reference time Tref/2i+1.

In some example embodiments, the delay circuits820and830may delay the pulses Tinpiand Tinniby a basic delay value, respectively.

Referring toFIG.9, a clock generating circuit900may include a logic circuit910and a clock control circuit920, and may receive a comparison result of a previous stage.

The logic circuit910may output a signal having a predetermined (or alternatively, desired) level when a comparison between a positive pulse and a negative pulse is completed in the previous stage. In some example embodiments, when the comparison in the previous stage is completed, either one of an output CMPi−1and a complementary output CMPbi−1may have ‘1’ and the other may have ‘0’ in a time comparator of the previous stage. Accordingly, the logic circuit910may be an exclusive OR (XOR) gate910. The XOR gate910may receive the output CMPi−1and the complementary output CMPbi−1in the time comparator of the previous stage, and output a signal having ‘1’ when the comparison is completed.

The clock control circuit920may generate a clock CLKiof a corresponding stage when the output of the logic circuit910has the predetermined (or alternatively, desired) level (e.g., action level, or action value) (e.g., the action value may be a high level (‘1’) as a logic level). In some example embodiments, the clock control circuit920may generate the clock CLKiby generating a start edge of the clock CLKiof the corresponding stage.

In some example embodiments, the clock control circuit920may further include a logic circuit930that outputs a signal having a predetermined (or alternatively, desired) level when a comparison between the positive pulse and the negative pulse is completed in the corresponding stage. The logic circuit930may be an XOR gate that receives an output CMPiand a complementary output CMPbiin a time comparator of the corresponding stage. Accordingly, the clock control circuit920may transfer a clock reset signal CLK_RST to the corresponding stage to reset the clock CLKiwhen an output of the logic circuit930has the predetermined (or alternatively, desired) level (e.g., the high level (‘1’) as a logic level).

In some other example embodiments, when the output of the logic circuit910has the predetermined (or alternatively, desired) level, the clock control circuit920may transfer the clock reset signal CLK_RST to the clock control circuit920corresponding to the previous stage. The clock control circuit920corresponding to the previous stage may reset the clock CLKi−1in response to the clock reset signal CLK_RST. In this case, the clock control circuit920may reset the clock CLKiin response to the clock reset signal CLK_RST transferred from the clock control circuit920corresponding to a next stage.

In some example embodiments, when the clock CLKiof a stage is reset, a time comparator (e.g.,810inFIG.8) of the corresponding stage may be reset for a next operation. When the time comparator810is reset, the time comparator810may output the same value (e.g., ‘0’) as the output CMPiand the complementary output CMPbi.

FIG.10is a block diagram illustrating an example of an analog-to-digital converter according to some example embodiments.

Referring toFIG.10, an analog-to-digital converter1000may include a VTC circuit1010, a first TDC circuit1020, and a second TDC circuit1030. The analog-to-digital converter1000may convert analog input voltages Vinp and Vinn into a digital signal having a plurality of bits (e.g., eight bits). In this case, the analog-to-digital converter1000may perform a fine decision after performing a coarse decision.

As described with reference toFIG.1, the VTC circuit1010may convert the input voltages Vinp and Vinn into time domain pulses Tinp and Tinn.

The first TDC circuit1020may perform the coarse decision. The first TDC circuit1020may decide a predetermined (or alternatively, desired) number (e.g., three) of the most significant bits D0to D2among the eight bits from the input pulses Tinp and Tinn, and output a positive pulse Tinpr and a negative pulse Tinnr as a residual signal corresponding to remaining bits (e.g., the lower five bits) D3to D7.

The second TDC circuit1030may perform the fine decision. The second TDC circuit1030may receive the residual signal Tinpr and Tinnr output from the first TDC circuit1020as input pulses, and decide the five bits D3to D7from the input pulses Tinpr and Tinnr.

In some example embodiments, both the first TDC circuit1020and the second TDC circuit1030may be implemented as a pipelined successive-approximation TDC described above.

In some other example embodiments, the second TDC circuit1030may be implemented as the pipelined successive-approximation TDC, and the first TDC circuit1020may be implemented as a faster TDC than the pipelined successive-approximation TDC. For example, the first TDC circuit1020may be implemented as a flash TDC.

FIG.11is a block diagram illustrating an example of a flash TDC circuit according to some example embodiments, andFIG.12is a diagram showing an example of a signal generated in a flash TDC circuit shown inFIG.11.

Referring toFIG.11, a flash TDC circuit1100may include a plurality of time comparators11101,11102,11103,11104,11105,11106, and11107, and a plurality of delay circuits11201,11202,11203,11204,11205, and11206. AlthoughFIG.11shows seven time comparators11101to11107and six delay circuits11201to11206, the number of time comparators11101to11107and the number of delay circuits11201to11206are not limited thereto. For example, if the flash TDC circuit1100decides n bits, the flash TDC circuit1100may include (2n−1) time comparators and (2n−2) delay circuits.

Each (or alternatively, at least one) of the delay circuits11201to11206may delay an input pulse by a reference time. When the flash TDC circuit1100decides the n bits, the reference time may be ½nof a reference time Tref of the flash TDC circuit1100. In an example shown inFIG.11andFIG.12, the reference time may be Tref/4. The delay circuit11201may output a negative pulse Tinn by delaying an input negative pulse Tinn by the reference time Tref/4, the delay circuit11202may output a negative pulse Tinn2by delaying the negative pulse Tinn1output from delay circuit11201by the reference time Tref/4, and the delay circuit11203may output a negative pulse Tinn3by delaying the negative pulse Tinn2output from delay circuit11202by the reference time Tref/4. Accordingly, the negative pulse Tinn2may be delayed by 2Tref/4 from the input negative pulse Tinn, and the negative pulse Tinn3may be delayed by 3Tref/4 from the input negative pulse Tinn. The delay circuit11204may output a positive pulse Tinp1by delaying an input positive pulse Tinp by the reference time Tref/4, the delay circuit11205may output a positive pulse Tinp2by delaying the positive pulse Tinp1output from delay circuit11204by the reference time Tref/4, and the delay circuit11206may output a positive pulse Tinp3by delaying the positive pulse Tinp2output from delay circuit11205by the reference time Tref/4. Accordingly, the positive pulse Tinp2may be delayed by 2Tref/4 from the input positive pulse Tinp, and the positive pulse Tinp3may be delayed by 3Tref/4 from the input positive pulse Tinp.

Each (or alternatively, at least one) of the time comparators11101to11107may compare a positive pulse and a negative pulse, and decide a corresponding one among bits C0to C6based on a comparison result. In some example embodiments, the time comparators11101to11107may compare a start edge of the positive pulse with a start edge of the negative pulse, decide ‘1’ if the start edge of the positive pulse is earlier than the start edge of the negative pulse, and decide ‘0’ if the start edge of the negative pulse is earlier than the start edge of the positive pulse.

The time comparators11101to11104may receive the input positive pulse Tinp as the positive pulse, and the time comparators11104to11107may receive the input negative pulse Tinn as the negative pulse. The time comparator11101may receive the negative pulse Tinn3output from the delay circuit11203as the negative pulse, the time comparator11102may receive the negative pulse Tinn2output from the delay circuit11202as the negative pulse, and the time comparator11103may receive the negative pulse Tinn1output from the delay circuit11201as the negative pulse. The time comparator11105may receive the positive pulse Tinp1output from the delay circuit11204as the positive pulse, the time comparator11106may receive the positive pulse Tinp2output from the delay circuit11205as the positive pulse, and the time comparator11107may receive the positive pulse Tinp3output from the delay circuit11206as the positive pulse.

As shown inFIG.12, for example, the input positive pulse Tinp and the input negative pulse Tinn may be input to the TDC circuit1200, and the input negative pulse Tinn may be later than the input positive pulse Tinp by a time longer than 2Tref/4 and shorter than 3Tref/4. Then, because the input positive pulse Tinp is earlier than the negative pulse Tinn3delayed by 3Tref/4 from the input negative pulse Tinn, the time comparator11101may decide the bit C0as ‘1’. Because the input positive pulse Tinp is earlier than the negative pulse Tinn2delayed by 2Tref/4 from the input negative pulse Tinn, the time comparator11102may also decide the bit C1as ‘1’. Because the input positive pulse Tinp is earlier than the negative pulse Tinn2delayed by Tref/4 from the input negative pulse Tinn, the time comparator11103may also decide the bit C2as ‘1’. Because the input positive pulse Tinp is earlier than the input negative pulse Tinn, the time comparator11104may also decide the bit C3as ‘1’. Because the positive pulse Tinp1delayed by Tref/4 from the input positive pulse Tinp is earlier than the input negative pulse Tinn, the time comparator11105may also decide the bit C4as ‘1’. Because the positive pulse Tinp1delayed by 2Tref/4 from the input positive pulse Tinp is earlier than the input negative pulse Tinn, the time comparator11106may also decide the bit C5as ‘1’. Because the positive pulse Tinp1delayed by 3Tref/4 from the input positive pulse Tinp is later than the input negative pulse Tinn, the time comparator11107may decide the bit C6as ‘0’.

Therefore, the flash TDC circuit1100may output a decision code C0to C6of “1111110”. The decision code C0to C6of “1111110” may be a thermometer code, and may correspond to “110” in a binary digital code. Since the flash TDC circuit1100may output all digital values in one clock cycle, it may operate faster than a pipelined successive-approximation TDC circuit.

As described above, in some example embodiments, when the flash TDC circuit is used as the first TDC circuit1020inFIG.10, the analog-to-digital converter may operate faster. In some example embodiments, when the pipelined successive-approximation TDC circuit is used as the first TDC circuit1020inFIG.10, the number of time comparators may be reduced. For example, for n-bit decision, n time comparators may be used in the pipelined successive-approximation TDC circuit, whereas (2n−1) time comparators may be used in the flash TDC circuit.

FIG.13is a flowchart illustrating an example of an analog-to-digital converting method according to some example embodiments.

Referring toFIG.13, an analog-to-digital converter may receive the ithpositive pulse and the ithnegative pulse at the ithstage in S1310. In some example embodiments, the first positive pulse and the first negative pulse of the first stage may be pulses generated by converting an input voltage into a time domain. In some example embodiments, the first positive pulse and the first negative pulse may be pulses that is remained after some bits (or alternatively, at least one bit) are decided from the pulses generated by converting the input voltage into the time domain.

In the ithstage, the analog-to-digital converter may generate the ithcomparison result by comparing the ithpositive pulse and the ithnegative pulse in response to the ithclock in S1320. The analog-to-digital converter may decide the ithbit based on the ithcomparison result in S1330. When the ithstage is the last stage (e.g., the nthstage) in S1340, the analog-to-digital converter may end the decision.

When the ithstage is not the last stage in S1340, the analog-to-digital converter may output the (i+1)thpositive pulse and the (i+1)thnegative pulse by delaying either one of the ithpositive pulse and the ithnegative pulse by the ithreference time based on a value of the ithcomparison result in S1350, S1360, and S1370. Further, the analog-to-digital converter may generate the (i+1)thclock in response to the ithcomparison result in S1380. In some example embodiments, the analog-to-digital converter may generate a first value (e.g., ‘1’) as the ithcomparison result if the ithpositive pulse is earlier than the ithnegative pulse, and generate a second value (e.g., ‘0’) different from the first value as the ithcomparison result if the ithnegative pulse is earlier than the ithpositive pulse. In some example embodiments, when the ithcomparison result has the first value in S1350, the analog-to-digital converter may delay the ithpositive pulse by the ithreference time in S1360. When the ithcomparison result has the second value in S1350, the analog-to-digital converter may delay the ithnegative pulse by the ithreference time in S1370.

Next, the analog-to-digital converter may perform a decision at the (i+1)thstage in S1390.

FIG.14is a block diagram illustrating an example of a computing device according to some example embodiments.

Referring toFIG.14, a computing device1400may include a host system1410and a memory system1420. The host system1410and the memory system1420may communicate through an interface. The memory system1420may include a memory controller1421and a memory device1422.

The memory controller1421may control a memory operation of the memory device1422by providing a signal to the memory device1422in response to a request from the host system1410. The signal may include a command and an address. The memory controller1421may read data from the memory device1422by providing a read signal to the memory device1422. Further, the memory controller1421may write data into the memory device1422by providing a write signal and the data to the memory device1422.

In some example embodiments, the memory device1422may include a volatile memory such as a dynamic random-access memory (DRAM). In some example embodiments, the memory device1422may include a non-volatile memory such as a flash memory, a phase-change memory, a resistive memory, a magnetoresistive memory, a ferroelectric memory, or a polymer memory. In some example embodiments, the memory device1422may be used as a system memory of host system1410. In this case, the memory controller1421may be provided as a separate chip from a processor of the host system1410, or may be provided as an internal component of the processor. In some example embodiments, the memory system1420may be used as a storage device for the host system1410.

An analog-to-digital converter described with reference toFIG.1toFIG.13may be included in the host system1410, the memory controller1421, and/or the memory device1422to convert an analog voltage into a digital signal.

FIG.15is a block diagram illustrating an example of a communication system according to some example embodiments.

Referring toFIG.15, a communication system1500may include a first device1510and a second device1520.

The first device1510may include a transmitter1511, a receiver1512, and a processor1513, and the second device1520may include a transmitter1521, a receiver1522, and a processor1523. The transmitter1511of the first device1510may transmit data to the second device1520, and the receiver1522of the second device1520may receive the data. Similarly, the transmitter1521of the second device1520may transmit data to the first device1510, and the receiver1512of the first device1510may receive the data. The processor1513may control operations of the transmitter1511and the receiver1512, and the processor1523may control operations of the transmitter1521and the receiver1522.

An analog-to-digital converter described with reference toFIG.1toFIG.13may be included in the transmitter1511, the receiver1512, the transmitter1521, and/or the receiver1522to convert an analog voltage into a digital signal.

AlthoughFIG.14andFIG.15shows the computing device and the communication system in which the analog-to-digital converter is used, a system or device to which the analog-to-digital converter is used is not limited thereto. The analog-to-digital converter may be used to convert an analog voltage to a digital signal in a variety of devices.

In some example embodiments, each (or alternatively, at least one) of the components, elements, modules, or units represented by a block as illustrated inFIG.1toFIG.12may be implemented as various numbers of hardware, software, and/or firmware structures that execute respective functions described above, according to some example embodiments. For example, at least one of these components, elements, modules, or units may include various hardware components including a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), or other circuitry using a digital circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc., that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Further, at least one of these components, elements, modules, or units may include a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses. Furthermore, at least one of these components, elements, modules, or units may further include or may be implemented by a processor that performs the respective functions. Functional aspects of example embodiments may be implemented in algorithms that execute on one or more processors.

Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the clock control circuit920and memory controller1421may be implemented as processing circuitry. The processing circuitry specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

Processor(s), controller(s), and/or processing circuitry may be configured to perform actions or steps by being specifically programmed to perform those action or steps (such as with an FPGA or ASIC) or may be configured to perform actions or steps by executing instructions received from a memory, or a combination thereof.