MEMORY SELECTOR

Embodiments include a method of forming a cross-point memory device, the method and device forming a multi-layered selector material. A first level of the multi-layered selector structure may include a subset of the elements of a second level of the multi-tiered selector structure. A gradient concentration of the switching elements may be found in the selector structure, first level including a substantially steady concentration of elements and the second level including a gradient of concentration for the elements in common as well as the elements unique to the first level.

BACKGROUND

Semiconductor memories are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. One type of semiconductor memory is phase-change random access memory (PCRAM), which involves storing values in phase change materials, such as chalcogenide materials. Phase change materials can be switched between an amorphous phase (in which they have a high resistivity) and a crystalline phase (in which they have a low resistivity) to indicate bit codes. A PCRAM cell typically includes a phase change material (PCM) element between two electrodes.

DETAILED DESCRIPTION

Embodiments utilize a selector layer structure of a memory cell which has multiple layers. The switching materials gradually increase in concentration percentage from the outside in, thereby resulting in better switching performance. There is less interference between the switching layers and nearby metal layers. Also, improved switching performance includes including sharper on/off switching profiles than would be realized in a single layer selector structures, and smaller cycle-to-cycle Vthvariation and smaller device-to-device Vthvariation. Memory cells may be formed using a variety of configurations of the multi-layer selector structure and memory elements.

FIG.1illustrates a perspective view of an array of cross-point or crossbar memory cells200in a memory array300, in accordance with some embodiments. The memory array300comprises bit lines12, word lines112, and memory cells200connected in a “cross-point” configuration, where addressing of a particular bit line12and a particular word line112together selects a particular memory cell200. In some embodiments, memory arrays300may be stacked to create a 3D memory array (not shown). The memory array300may be formed on a substrate (see, e.g., substrate2ofFIG.6), which may be a semiconductor substrate or another type of substrate. The substrate may include active and/or passive devices (e.g., transistors, diodes, capacitors, resistors, or the like), in some embodiments. The devices may be formed according to applicable manufacturing processes. In some embodiments, no devices are formed in the substrate. In some embodiments, the memory array300is formed in the metallization layers of an interconnect structure over the substrate. The memory array300may be electrically connected to one or more of the metallization layers. For example, in some embodiments, the word lines112and/or the bit lines12may be conductive lines of the metallization layers.

In the embodiment shown inFIG.1, each memory cell200comprises a bottom electrode24, a memory storage structure34, an intermediate layer44, a selector structure54, and a top electrode64. The elements between the top electrode64and bottom electrode24, including, for example, the memory storage structure34, intermediate layer44, and selector layer54may be referred to as the memory elements76. The bit lines12are electrically connected to the bottom electrodes24of respective columns of memory cells200in the memory array300. Each column of the memory array300has an associated bit line12(e.g., bit line12A,12B, or12C), and the memory cells200in a column are connected to the same bit line12for that column. The word lines112are connected to the top electrodes64of respective rows of memory cells200in the memory array300. Each row of the memory array300has an associated word line124(e.g., word line124A,124B,124C), and the memory cells200in a row are connected to the word line124for that row. In this manner, each memory cell200of the memory array300may be selected by the appropriate combination of word line124and bit line12. For example, a particular memory cell200B may be selected (e.g., for reading or writing operations) by accessing the single word line112B connected to the memory cell200B and also accessing the single bit line12B connected to the memory cell200. Other memory cells which are particularly labeled inFIG.1include200A,200C,200D, and200E, which are along the reference lines A-A (200A,200B,200C) and B-B (200D,200B,200E), which are utilized as cross-section reference lines in some of the proceeding figures.

In some embodiments, the resistance of the memory storage structure34of each memory cell200is programmable, and can be changed between a high-resistance state and a low-resistance state, which can correspond to the two states of a binary code. The memory storage structure34may utilize any appropriate technology, and this disclosure should not be limited to any particular type of memory storage technology. For example, the memory storage structure34may include phase-change material (PCM) for a PCRAM (phase-change random access memory) device, a two-state resistive material for an RRAM (resistive random access memory) device, a magnetic tunnel junction (MTJ) for an MRAM (magnetic random access memory) device. Other memory types may be used.

In some embodiments, the resistance state of the memory storage structure34of a memory cell200can be programmed (e.g., “written”) by applying an appropriate electrical voltage pulse across the memory cell200that generates a corresponding electrical current pulse across the memory storage structure34. The current necessary to alter the resistive state of the memory storage structure34is design specific. Because a larger percentage of the resistance of the memory cell200is provided by the memory storage structure34, the realized current pulse is dependent on the resistivity of the memory storage structure34. For example, in some embodiments, the magnitude of a programming current pulse may be in the range of about 50 μA to about 800 μA, though other currents are possible. The applied programming voltage also depends on the memory storage structure34. For example, the reading of a particular memory cell200may be forward biased and the writing may be reversed biased or vice versa. In some cases, the magnitude of a programming voltage pulse may be in the range of about 1 V to about 2 V, though other voltages are possible. In some embodiments, the state of a memory cell200may be read by applying a relatively small electrical current across the memory cell200that allows the resistance of the memory cell200to be measured without disturbing the resistance state of the memory storage structure34. Other types of memory or memory architecture may use different read schemes or magnitudes than this example.

The selector structure54of each memory cell200is used as a selector that allows the respective memory cell200to be accessed (e.g., written or read) individually. In this manner, a selector structure54of a memory cell200may also be referred to herein as “selector54.” The selector structure54may utilize ovonic threshold switching (OTS) or variations thereof, such as, mixed-ionic-electronic conduction (MIEC), and so forth. For simplicity, all such variations will also be referred to as OTS.

Referring toFIGS.2A and2B, an OTS selector material has a characteristic property called the threshold voltage (VTH). At applied voltages below VTH(e.g., at subthreshold voltages), the OTS selector material is in a high-resistance state, limiting current through the OTS selector material. At applied voltages greater than VTH, the OTS selector material is in a low-resistance state that creates a current path through the OTS selector material. When an OTS selector material is utilized in the memory elements76of the memory cell200, these properties of the OTS selector material may be used to activate a particular memory cell200without affecting neighboring memory cells for write or read operations. In this manner, write operations may be performed on a memory cell200only when the voltage across the selector structure54is greater than VTH.

FIG.2Aillustrates a simplified version of a memory array300, such as that illustrated inFIG.1. The memory array300inFIG.2Aincludes bit lines12, labelled BL(1)-BL(n)and word lines112, labelled WL(1)-WL(m), where n is the total number of bitlines and m is the total number of word lines in the memory array300, such that the number of memory cells200in the memory array is m×n. As illustrated inFIG.2A, a particular memory cell200(m,n)may be selected using the selector structure54by applying the voltage Vappliedto the word line WL(m)and applying a ground to the bit line BL(n), where Vappliedis greater than the VTHof the selector structure54of the memory cell200(n,m). The other bitlines12and word lines112can have applied a reference voltage equal to ½Vapplied, or some other voltage which causes the selector structure54to be in a high-resistance state.

The behavior of the selector structure54as described above is modeled inFIG.2B. The reference voltage Vrefmay be equal to the voltage VappliedfromFIG.2A. When the voltage VTHis reached, the selector structure54is “on” and thus exhibits a lower resistance state such that current can pass through the selector structure54. In contrast, when the voltage VTHis not reached, the selector structure54is “off” and thus exhibits a high resistance state such that little current can pass through the selector structure54. The reference voltage Vrefis above the threshold VTH, whereas the voltage ½Vrefis below the threshold VTH.

In some embodiments, the magnitude of the threshold voltage VTHis in the range of about 1 V to about 2 V, though other voltages are possible. In some cases, the threshold voltage VTHcan be tuned, for example, by adjusting the materials or thicknesses of the various layers.

FIG.3illustrates a circuit schematic view of the memory array300. Some elements have been removed for clarity. A bitline driver controls the voltage signals to the various conductive bitlines12and a word line driver controls the voltage signals to the various conductive word lines112. The memory cells200include the memory storage structure34and selector structure54. They may be in either order. When a reference voltage is supplied to activate a memory cell200, in a read operation the resulting current response may be read to determine whether the value was a ‘1’ or ‘0’. A write operation may depend on the type of memory storage structure34utilized. In some embodiments, for example, a large voltage bias may be applied, while in others a reverse voltage bias may be applied.

FIGS.4A,4B,4C, and4Dillustrate various configurations of the memory cell200. The various configurations result from the patterning processes used to form the pillars corresponding to the memory cells200. InFIG.4A, the memory cell200has a shape resembling a rectangular prism. The corners may be rounded in some embodiments or relatively squared off in other embodiments. InFIG.4B, the memory cell200has a cylindrical shape. InFIG.4C, the memory cell200has a pyramid shape. InFIG.4D, the memory cell200has a conical shape. The memory cells200inFIGS.4A,4B,4C, and4Dmay achieve such shapes by depositing each of the layers of the memory cells such as illustrated inFIG.7, and patterning the memory cells200through a mask using acceptable photolithographic processes. In such embodiments, the bitlines12are formed and separated prior to depositing the layers of the memory cells200, again using acceptable photolithographic processes and deposition techniques. After patterning the memory cells200, surrounding dielectric layers, including liner layers, may be deposited to laterally surround the memory cells200and then the word lines112formed and patterned. The memory cells200ofFIGS.4A and4Cmay instead be formed by the processes described below inFIGS.6through21, the etching processes may result, for example, in the side walls of the memory cells200to be angled such as illustrated inFIG.4Cor straight such as illustrated inFIG.4A.

FIGS.5A,5B,5C, and5Dillustrate various configurations of the memory elements76. It should be understood that each of these configurations may be utilized in the embodiments discussed below. In particular, even though the layout of the memory elements76illustrated inFIG.5Ais used in the remaining Figures for illustration purposes, any of the layouts illustrated inFIGS.5A,5B,5C, and5Dmay be substituted. It should also be understood that variations of these which are not specifically illustrated may also be used. For example, each of the memory structure34, intermediate layer44, and selector structure54constitute resistive elements arranged in a series formation. As such, the order of each of these (if utilized) does not significantly affect the operation of the memory cells200and the principles discussed in this disclosure.FIG.5Aillustrates that the memory structure34is formed at the base of the memory elements76, the selector structure54is formed at the top of the memory elements76, and that the intermediate layer44is interposed between the two.FIG.5Billustrates that the memory structure34is formed at the base of the memory elements76, the intermediate layer44is formed at the top of the memory elements76, and that the selector structure54is interposed between the two.FIGS.5C and5Domit the intermediate layer44. InFIG.5Cthe memory structure34is formed at the base of the memory elements76and the selector structure54is formed at the top of the memory elements76. InFIG.5D, these are reversed so that the selector structure54is formed at the base of the memory elements76and the memory structure34is formed at the top of the memory elements76.

FIGS.6through26B and30A through31Bprovide intermediate views of the formation of a memory array300, in accordance with some embodiments.FIGS.6,9,11,13,15, each illustrate a three-dimensional view of the intermediate processes of forming the memory array300. Some features have been omitted or simplified for clarity. Each of these views provides reference cross section lines A-A and B-B which correspond to those provided above with respect toFIG.1. Unless otherwise noted, the Figures which end in an A are along the A-A reference line and the Figures which end in a B are along the B-B reference line.

FIGS.6and7illustrate the formation of layers of the memory array300which will be subsequently patterned into memory cells200.FIG.7in this instance illustrates a view of a cross-section which applies both to the reference cross-section A-A and B-B ofFIG.6.

A substrate2is provided. The substrate2may be any one of a number of layers or a combination of layers, depending on where the memory array is being formed. As noted above, for example, the memory array may be formed in an interconnect structure. In such embodiments, the substrate2can be a combination of a semiconductor substrate with or without devices formed therein with any number of metallization layers formed thereover. In some embodiments, the substrate2may include a semiconductor material such as silicon, silicon germanium, or the like. In some embodiments, the substrate2includes a crystalline semiconductor substrate such as a crystalline silicon substrate, a crystalline silicon carbon substrate, a crystalline silicon germanium substrate, a III-V compound semiconductor substrate, or the like. In an embodiment the substrate2may include bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, or combinations thereof, such as silicon germanium on insulator (SGOI). Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates.

In other embodiments, the substrate2can be a carrier substrate, such as a glass carrier, a ceramic carrier, or the like, and the memory array300is formed on the carrier substrate.

A bitline layer10is formed over the substrate2. Any number of intervening layers and structures may be formed between the substrate2and the bitline layer10, including, for example, an interconnect of which the bitline layer10is located at an upper metallization layer thereof. In some embodiments, such intervening layers may include active and/or passive devices.

The bitline layer10may be formed of any suitable conductive material. In some embodiments, for example, the bitline layer10may be formed of copper, gold, aluminum, ruthenium, nickel, cobalt, titanium, tungsten, titanium nitride, tantalum, tantalum nitride, the like, and combinations thereof. The bitline layer10may be formed of multiple discreet layers, in some embodiments. The bitline layer10may be formed using any suitable process, such as by physical vapor deposition (PVD), chemical vapor deposition (CVD), plating, atomic layer deposition (ALD), sputtering, and so forth. Although the bitline layer10is illustrated as being a blanket deposition, the bitline layer10may be formed using other processes, such as damascene, dual-damascene, or another suitable process.

A bottom electrode layer20is deposited over the bitline layer10. The bottom electrode layer20may be formed of different or the same materials as the bitline layer10, using similar processes. The bottom electrode layer20will be patterned into a bottom electrode for the memory cells200in subsequent processes.

Next, over the bottom electrode layer20, the memory stack layers70are formed. These layers will be patterned in subsequent processes into the pillars74of the memory cells200. For the purposes of the discussion inFIGS.6and7, the memory stack layers70are shown as including the memory structure layers30, the interfacial layer40, and the selector layers50, however, it should be understood that the order and/or presence of these layers may depend on the specific implementation utilized. For example, as discussed above with respect toFIGS.5A,5B,5C, and5D, which illustrate the memory stack layers70after being patterned into the pillars74, corresponding memory structure34, intermediate layer44, and selector structure54may be arranged in a different order, and in some embodiments the intermediate layer44may be omitted. For simplicity, only the organization according toFIG.5Awill be shown, however, the others may readily be substituted.

The memory structure layers30may include any such appropriate layers for the memory technology which is utilized. For example, if the memory technology is PCRAM, then the memory structure layers30may include a barrier layer and a chalcogenide material layer. If the memory technology is MRAM, then the memory structure may include a free layer, a reference layer, and a pinned layer for switching the MRAM magnetic moment of the free layer. Other layers for these or other memory technologies may be utilized as appropriate. The formation of these layers may be performed using processes suitable for such layers, such as PVD, ALD, CVD, spin-on, and so forth.

The intermediate layer40is formed on the memory structure layers30. The intermediate layer40may be formed using materials or techniques similar to those described for the bottom electrodes20. The selector structure layers50are formed on the intermediate layer40. The formation and materials of the selector structure layers50are discussed in further detail with respect toFIGS.8A,8B,8C, and8D, below.

Following the formation of the selector structure layers50, a top electrode layer60is formed. The top electrode layer60may be formed using processes and materials similar to those used to form the bottom electrode layer20.

FIGS.8A,8B,8C, and8Dillustrate various configurations of the selector structure layers50, which are subsequently patterned into the selector structure54. As seen inFIGS.8A,8B,8C, and8D, each of the configurations of the selectors structure layers50includes at least two layers including a first ovonic threshold switching (OTS) material layer55and a second OTS material layer57.FIG.8Aillustrates a first OTS material layer55sandwiched between two second OTS material layers57. InFIG.8A, the two second OTS material layers57are composed of the same materials.FIG.8Billustrates the first OTS material layer55sandwiched between a second OTS material layer57and a third OTS material layer59.FIGS.8C and8Deach include the first OTS material layer55and only one second OTS material layer57, where the second OTS material layer57is disposed over (FIG.8C) or under (FIG.8D) the first OTS material layer55.

Utilizing a bi-layer or sandwich selector structure provides a gradual composition profile between the multiple layers, which provides more stable device performance. A single layer OTS material layer can have large cycle-to-cycle and device-to-device Vthvariation with a switching behavior which is not sharp. In contrast, the multi-layer structures of the embodiment selector structures54provide improved performance with less Vthvariation and sharper switching behavior. The switching behavior depends primarily on the first OTS material layer55, which has a higher resistance than the second OTS material layer57and (if used) the third OTS material layer59. As such, when applying voltage, most of the voltage drop is across the first OTS material layer55. The second OTS material layer57(and third OTS material layer59, if used) improves interference at the interface between the overlying or underlying metal layers while driving the switching by reducing or eliminating interference. This results in better switching behavior, such as sharp turn-on/turn-off, smaller cycle-to-cycle Vthvariation, and smaller device-to-device Vthvariation. The composition profiles of the selectors structure54is discussed in greater detail below, with respect toFIGS.28and29

The first OTS material layer55may be made of an alloy or composition of any suitable ovonic material, such as SiGeCTe, NSiGeCTe, NSnZnTe, SiSnTe, SiZnTe, and NSiZnSnTe, the like, or combinations thereof. The second OTS material layer57(and third OTS material layer59, if used) may be made of an alloy or composition of any suitable ovonic material, such as CTe, GeCTe, SiCTe, ZnTe, and SnTe, the like, or combinations thereof. It should be understood each of the listed OTS materials contemplates suitable and appropriate ratios for each of the listed elements and is not meant to convey a particular ratio.

In some embodiments, the second OTS material layer57(and/or third OTS material layer59, if used) may include a subset of the materials used in the first OTS material layer55. For example, if the second OTS material layer57or third OTS material layer59is CTe, the first OTS material layer55may be GeCTe, SiGeCTe, or NSiGeCTe. If the second OTS material layer57or third OTS material layer59is GCTe, the first OTS material layer55may be SiGeCTe or NSiGeCTe. If the second OTS material layer57or third OTS material layer59is SiCTe, the first OTS material layer55may be SiGeCTe or NSiGeCTe. If the second OTS material layer57or third OTS material layer59is ZnTe, the first OTS material layer55may be NSnZnTe, SiZnTe, or NSiZnSnTe. If the second OTS material layer57or third OTS material layer59is SnTe, the first OTS material layer55may be NSnZnTe, SiSnTe, or NSiZnSnTe.

In embodiments which utilize both the second OTS material layer57and the third OTS material layer59, either they may both be a subset of the first OTS material layer55or at least one may be a subset of the first OTS material layer55. For example, in embodiments where both the second and third OTS material layers57and59are subsets of the first OTS material layer55, if the first OTS material layer55is NSiGeCTe or SiGeCTe, then the second OTS material layer57and third OTS material layer59may be one of GeCTe, CTe, or SiCTe. If the first OTS material layer55is NSnZnTe, SiZnTe, NSiZnSnTe, then the second OTS material layer57and third OTS material layer59may be ZnTe or SnTe. In embodiments where only one of the second or third OTS material layers57or59is a subset of the first OTS material layer55and the other is allowed to have one or more additional elements, if the first OTS material layer55is NSiGeCTe or SiGeCTe, then one of the second OTS material layer57or third OTS material layer59may be ZnTe, SnTe, GeCTe, CTe, or SiCTe and the other may be GeCTe, CTe, or SiCTe. If the first OTS material layer55is NSnZnTe, SiZnTe, NSiZnSnTe, then one of the second OTS material layer57or third OTS material layer59may be ZnTe, SnTe, GeCTe, CTe, or SiCTe and the other may be ZnTe or SnTe. If the first OTS material layer55is SiSnTe, then one of the second OTS material layer57or third OTS material layer59may be ZnTe, SnTe, GeCTe, CTe, or SiCTe and the other may be SnTe. In some embodiments, both the second OTS material layer57and third OTS material layer59may have additional elements not found in the first OTS material layer55.

The first OTS material layer55, second OTS material layer57, and third OTS material layer59(if used) may be deposited using any suitable technique and in the order in which they are formed (see, e.g.,FIGS.8A,8B,8C, and8D). For example, these may be deposited using a suitable deposition process, such as PVD, CVD, plasma-enhanced CVD (PECVD), ALD, or the like.

The first OTS material layer55may be deposited to a thickness between about 5 nm and 15 nm. The second OTS material layer57may be deposited to a thickness between about 2.5 nm and 5 nm. When two layers of the second OTS material layer57are used on either side of the first OTS material layer55, such as illustrated inFIG.8A, then the two layers may have the same thicknesses or may have different thicknesses. The third OTS material layer59, such as illustrated inFIG.8Bmay be deposited to a thickness between about 2.5 nm and 5 nm. InFIG.8B, the thickness of the second OTS material layer57and the thickness of the third OTS material layer59may be the same or may be different.

InFIGS.9,10A, and10B, a hard mask layer84is formed over the memory stack layers70. The hard mask layer84may be formed of any suitable material, such as doped or undoped silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, doped silicate glass, flowable oxide, other high-k materials, low-k materials, the like, or combinations thereof. The hard mask layer84may be formed using any suitable process, such as by flowable CVD, spin-on, PVD, and so forth. After the hard mask layer84is formed, a photomask88is deposited over the hard mask layer84and patterned using acceptable photopatterning techniques.

InFIGS.11,12A, and12B, the pattern of the photomask88is used to pattern the hard mask layer84, thereby forming hard mask86. The hard mask86is then used as a mask to etch each of the layers of the memory stack layers70in turn followed by the bitline layer10. The etching processes used to etch each of the layers may using etching techniques suitable for the material of each of the layers being etched. For example, in some embodiments dry etching is used to etch each of the layers using suitable etchants. In other embodiments, reactive ion etching may be used. In other embodiments, wet etching may be used using suitable etchants. In other embodiments, a combination of etching techniques is used. As a result of the etching, bitline layer10is altered into the bit lines12, the bottom electrode layer20is altered into the bottom electrode layers22, the memory structure layers30are altered into the memory structure layers32, the interfacial layer40is altered into the interfacial layers42, the selector layers50are altered into the selector layers52, the top electrode layer60is altered into the bottom electrode layers62, and together the memory stack layers70are altered into the memory stack layers72. Following the patterning of the memory stack layers70, the memory cells200are partially etched, being separated into rows according to the rows in which the memory cells200align.

InFIGS.13,14A, and14B, a protection layer90may be conformally formed over the patterned memory stack layers72and a dielectric fill100deposited laterally surrounding and encapsulating the memory stack layers72. The protection layer90may include any suitable insulating material. In some embodiments, the protection layer90may include an extremely low-k material, for example, having a k value lower than about 4.0. In some embodiments, the protection layer90may include a multi-layer structure, including the extremely low-k material and a capping layer to help protect the low-k material. For example, in some embodiments, the low-k material may include silicon oxycarbonitride or silicon oxynitride and the capping layer may include silicon carbide or silicon nitride. These are merely examples; other suitable materials may be utilized instead. The dielectric fill100may be formed using any suitable insulating material by any suitable process. In some embodiments, the dielectric fill100may be silicon oxide or an insulating polymer. The dielectric100may be formed using any suitable process, such by spin-on, CVD, PVD, and the like, or combinations thereof. When the dielectric fill100includes silicon oxide, it may also be formed by a tetraethyl orthosilicate (TEOS) deposition process.

InFIGS.15,16A, and16B, a planarization process, such as a chemical mechanical polishing (CMP) process is used to level an upper surface of the dielectric fill100with the upper surface of the top electrode layer62.

InFIGS.17,18A, and18B, a word line layer110may be blanket deposited over the dielectric fill100and the memory stack layers72. The word line layer110may be formed using processes and materials similar to those used to form the bit line layer10.

InFIGS.19,20A, and20B, a hard mask layer114is formed over the word line layer110. The hard mask layer114may be formed using processes and materials similar to those described above with respect to the hard mask layer84. After the hard mask layer114is formed, a photomask118is deposited over the hard mask layer114and patterned using acceptable photopatterning techniques.

InFIGS.21,22A, and22B, the pattern of the photomask118is used to pattern the hard mask layer114, thereby forming hard mask116. The hard mask116is then used as a mask to etch the word line layer110followed by each of the layers of the memory stack layers72in turn. The etching processes used to etch each of the layers may using etching techniques suitable for the material of each of the layers being etched. For example, in some embodiments dry etching is used to etch each of the layers using suitable etchants. In other embodiments, reactive ion etching may be used. In other embodiments, wet etching may be used using suitable etchants. In other embodiments, a combination of etching techniques is used. As a result of the etching, word line layer110is altered into the word lines112, the top electrode layer62is altered into the top electrodes64, the selector layers50are altered into the selector structure54, the interfacial layer42is altered into the interfacial layers44, the memory structure layers32are altered into the memory structure34, the bottom electrode layers24are altered into the bottom electrodes24, and together the memory stack layers72are altered into the pillars74. Following the patterning of the pillars74, the memory cells200have been fully etched. When the bitlines12were formed, the memory cells200were separated into rows and when the word lines112were etched, the memory cells200are further separated into columns, thereby forming the full memory cells200, which include the memory elements76interposed between the top electrode64and bottom electrode22(seeFIGS.4A,4B,4C, and4D).

In some embodiments, the exposed areas of the dielectric fill100may be completely removed by the etching processes ofFIGS.21,22A, and22B, however, in some embodiments, a remnant100aof the dielectric fill100, with an upper surface approximately aligned to the upper surface of the bitlines12may remain behind following the etching processes.

InFIGS.23,24A, and24B, a protection layer120may be conformally formed over the patterned pillars74and a dielectric fill130deposited laterally surrounding and encapsulating the pillars74. The protection layer120may be formed using processes and materials similar to those used to form the protection layer90, and the dielectric fill130may be formed using processes and materials similar to those used to form the dielectric fill100.

Following the patterning and formation of the protection layer120, each of the pillars74is laterally encapsulated by a combination of the protection layer90and the protection layer120. Further, each of the pillars74is laterally encapsulated by a combination of the dielectric fill100and the dielectric fill130.

InFIGS.25,26A, and26B, a planarization process, such as a chemical mechanical polishing (CMP) process is used to level an upper surface of the dielectric fill100with the upper surface of the top electrode layer62. Thus, the memory cells200are formed, including for example, the memory cell200A,200B,200C,200D, and200E, such as illustrated inFIGS.25,26A, and26B.

It should be appreciated that other processes may be used to form the memory cells. For example, the bitlines12may be formed within a dielectric layer (e.g.,100a), the bitlines12leveled with the dielectric layer. Then, each of the memory stack layers70formed. Then, each of the memory stack layers70may be patterned to form pillars74. The pillars74may then be covered by a protection layer, such as the protection layer90or protection layer120. Then, the pillars74may be laterally encapsulated with a dielectric fill, such as the dielectric fill100or the dielectric fill130. Next, the dielectric fill may be planarized and leveled to the tops of the pillars74and then the word lines112may be formed.

InFIGS.27A and27B, the same structure ofFIGS.26A and26Bis illustrated, except that the pillars74are illustrated as having sloping or tapered sidewalls. In some embodiments, the pillars74may be different shapes, such as illustrated inFIGS.4A,4B,4C, and4D. InFIGS.27A and27B, when the layers (the bottom electrode24, the memory elements34, the interfacial layer44, the selector structure54, and the top electrode64) are etched from which the pillars are formed, the etching may produce sidewalls which are not vertical. In some embodiments, the sidewalls may be tapered outwardly, such as illustrated inFIGS.27A and27B, while in other embodiments, the sidewalls may be tapered inwardly, for example by flipping the shapes of the pillars74. These variations may be substituted in the other illustrations, but for the sake of simplicity are not separately illustrated otherwise.

FIGS.28and29illustrate several variations on the gradient profiles of the first OTS selector layer55and second OTS selector layer57. To the left of each figure is a representation of the selector structure54including the layout fromFIG.8A, with a first OTS selector layer55sandwiched between two second OTS selector layers57. These are part of the pillar76which includes the layers over the selector structure54and the layers under the selector structure54. These over and under layers may vary based on the layout, such as described above with respect toFIGS.5A,5B,5C, and5D.

To the right of each figure includes graphs with one axis being the depth profile for the selector structure54and the other axis being the atomic percentage concentration of materials in the selector structure54. The layer-to-layer demarcation between the first OTS selector layer55and the second OTS selector layers57have been extended from the left hand side through the graphs.

The lines labeled250A,250B, and250C represent the atomic percent concentration of the elements shared with both the first OTS selector layer55and the second OTS selector layer57. The lines labeled260A and260B represent the atomic percentage concentration of the elements specific to the just the first OTS selector layer55. As described above, the first OTS selector layer55includes a subset of elements in common with the second OTS selector layer57(and third OTS selector layer59) as well as additional elements specific to the first OTS selector layer55.

InFIG.28, the shared elements have a higher concentration than the non-shared elements. As such, the percent concentration of the shared elements is greater than the percent concentration of the elements specific to the first OTS selector layer55. InFIG.29, the elements specific to the first OTS selector layer55have a higher percent concentration than the shared elements. As such, the percent concentration of the specific elements is illustrated as being greater in the first OTS selector layer55than in the second OTS selector layer57.

InFIG.28, the line250A of the first graph illustrates that the shared elements in the first OTS selector layer55and second OTS selector layer57has a gradual increase through the lower second OTS selector layer57to the first OTS selector layer55, where the concentration flattens and is consistent through the thickness of the first OTS selector layer55. Then, the shared elements have another gradual decrease now through the upper second OTS selector layer57. The line250B of the second graph illustrates that the shared elements in the first OTS selector layer55and second OTS selector layer57has a two-slope increase through the lower second OTS selector layer57and into the first OTS selector layer55. The concentration flattens and is consistent through the thickness of the first OTS selector layer55. Then, the shared elements have another two-slope decrease through the third OTS selector layer57. The line250C of the third graph illustrates that the shared elements in the first OTS selector layer55and second OTS selector layer57has an increase through the lower second OTS selector layer57and into the first OTS selector layer55. Then, the shared elements decrease into the first OTS selector layer55. The concentration then flattens and is consistent through the thickness of the first OTS selector layer55. Then, the shared elements have an increase into the upper second OTS selector layer57followed by a decrease through the remaining portion of the upper second OTS selector layer57.

The lines260A of each of the first, second, and third graphs ofFIG.28illustrate that the elements specific to the first OTS selector layer55may actually gradually increase through a thickness of the lower second OTS selector layer57. For example, after deposition, the elements specific to the first OTS selector layer55may diffuse back into the adjoining second OTS selector layers57. For the thickness of the first OTS layer55, the concentration of the specific elements may be substantially steady. Then, for the upper second OTS layer57, the concentration of the specific elements (line260A) may decrease through a thickness of the upper second OTS layer57.

InFIG.29, for the lines250A,250B, and250C, the concentrations of the shared elements may have properties and characteristics similar to those discussed above with respect toFIG.28. The lines260B have concentration characteristics similar to the lines260A, except that the concentrations of the elements specific to the first OTS switching layer55are greater than the concentrations of the shared elements between the first OTS switching layer55and second OTS switching layer57.

FIGS.28and29illustrate where the second OTS switching layer57is used above and below the first OTS switching layer55. In some embodiments, the third OTS switching layer59may be used above or below the first OTS switching layer. In such embodiments, the concentration curves may be the same as presented inFIGS.28and29, though the second OTS switching layer57and third OTS switching layer59each have elements which are common to the first switching layer55, but not common to each other. In some embodiments, the second OTS switching layer57over or under the first OTS switching layer55may not be used. In such embodiments, the illustrated curves include the concentration gradients for the side/interface between the first OTS switching layer55and the second OTS switching layer57. The curves on the side of the first OTS switching layer55opposite the second OTS switching layer57are similar to those depicted but compressed. In such embodiments, the materials of the first OTS switching layer55diffuse to a lesser degree than when the abutting layer is the second OTS switching layer57. Instead, the curves are compressed into a depth distance about 10% to 25% of the illustrated depth.

FIGS.30A and30Billustrate the formation of vials150to couple to the word lines112and the bitlines12to a metallization. In some embodiments, the dielectric fill130may not be planarized and instead it may remain for forming the vias150. In other embodiments, a dielectric layer140is deposited over the word lines112and over the dielectric fill130. Then openings may be formed through the dielectric layer140and the dielectric layer130corresponding to the vias150. Then the vias150may be formed by depositing a conductive material in the openings. The vias150may be deposited by any suitable process, such as by ALD, CVD, plating, or the like. In some embodiments, a barrier layer may be formed between the dielectric layer140and the vias150.

InFIGS.31A and31Ba metallization170may be formed for forming metal pads over the vias150. The metallization170may be formed by first depositing an insulating layer160, such as an inter-layer dielectric (ILD) over the dielectric layer140and forming openings in the insulating layer160corresponding to the metallization pattern being formed. Then the contact170may be formed by any suitable process, such as by as by ALD, CVD, plating, or the like. In some embodiments, a barrier layer may be formed between the dielectric layer160and the contact170.

Embodiments achieve advantages. Using a multi-layer selector structure provides improved switching performance, including sharper on/off switching profiles than single layer selector structures, and smaller cycle-to-cycle Vthvariation and smaller device-to-device Vthvariation. Having a gradual composition of the OTS switching further enhances device selector performance by reducing or eliminating interference with adjacent metal layers. Memory cells may be formed using a variety of configurations of the multi-layer selector structure and memory elements.

One embodiment is a method including forming a memory structure of a memory cell, the memory structure interposed between an upper electrode and lower electrode. The method also includes forming a selector structure of the memory cell, the selector structure interposed between the upper electrode and the lower electrode, the selector structure including a first material disposed in a first layer and a second material disposed in a second layer, the first material may include the second material and an additional element, the first material may include an ovonic threshold switching material. The method also includes forming a word line over the selector structure, the word line having a lengthwise direction perpendicular to a lengthwise direction of a bitline, the bitline disposed under the selector structure.

In an embodiment, a concentration of the first material in the first layer is substantially even throughout an entire thickness of the first layer. In an embodiment, a concentration of the second material in the second layer has a gradient change of concentration throughout a thickness of the second layer. In an embodiment, the gradient change of concentration includes two different slopes. In an embodiment, a first slope increases concentration of the second material in the second layer and a second slope decreases concentration of the second material in the second layer. In an embodiment, the second layer includes the additional element of the first layer in a gradient of concentration that increases to an interface between the first layer and the second layer. In an embodiment, the selector structure is disposed over the memory structure. In an embodiment, the method may include: forming an interfacial layer between the memory structure and the selector structure. In an embodiment, the selector structure includes a third layer may include a third material, the first layer interposed between the second layer and the third layer. In an embodiment, the third material is different than the second material of the second layer, where the first layer further may include the third material.

Another embodiment is a method including forming a bitline metal. The method also includes depositing a bottom electrode metal. The method also includes depositing memory layers over the bottom electrode metal. The method also includes depositing selector layers over the bottom electrode metal. The method also includes depositing a top electrode metal over the selector layers. The method also includes forming a first mask over the top electrode metal and patterning the top electrode metal, selector layers, memory layers, and bottom electrode metal into a set of strips corresponding to the bitline metal. The method also includes depositing an insulating layer laterally surrounding the set of strips. The method also includes forming a word line metal over the insulating layer and top electrode metal. The method also includes forming a second mask over the word line metal and patterning the word line metal. The method also includes patterning the word line metal and patterning the top electrode metal, the selector layers, the memory layers, and the bottom electrode metal using the second mask into a set of pillars, each pillar corresponding to a memory cell.

In an embodiment, the method may include: depositing a first selector layer may include a first ovonic threshold switching (OTS) material; and depositing a second selector layer may include a second OTS material, where the second OTS material may include a subset of the first OTS material. In an embodiment, depositing the selector layers further may include: depositing a third selector of a third OTS material, where the first selector layer is interposed between the second selector layer and the third selector layer, the first selector layer having a first shared interface with the second selector layer and a second shared interface with the third selector layer, the third OTS material may include a subset of the first OTS material. In an embodiment, the third OTS material is different than the second OTS material.

Another embodiment is a device, including a memory cell which may include: a memory structure, a selector structure, the selector structure may include a first material layer and a second material layer, where the second material layer may include a subset of materials from the first material layer, a top electrode, and a bottom electrode, the memory structure and selector structure interposed between the top electrode and the bottom electrode. The device also includes a bit line coupled to the bottom electrode. The device also includes a source line coupled to the top electrode.

In an embodiment, the selector structure further may include a third material layer, where the third material layer may include a subset of materials from the first material layer. In an embodiment, the third material layer and the second material layer have the same material composition. In an embodiment, a first concentration of first materials in the first material layer has a substantially steady concentration profile for an entire thickness of the first material layer. In an embodiment, a first percentage concentration of materials unique to the first material layer is greater than a second percentage concentration of materials common to both the first material layer and the second material layer. In an embodiment, the second material layer further may include a gradient percent concentration of materials of the first material layer.