Semiconductor device and operating method thereof

An operating method of a semiconductor device includes monitoring multiple request packets and multiple response packets that are being transmitted between a master device and a slave device. A target request packet that matches predefined identification (ID) information is detected from among the request packets. An operation of a latency counter is initiated. The operation is for measuring the latency of a communication exchange (transaction) that includes the target request packet and a target response packet that is one of the response packets that matches the predefined ID information. The target response packet is detected from among the response packets. The operation of the latency counter is terminated. A latency value of the communication exchange is acquired from the latency counter.

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0014250, filed on Feb. 4, 2016 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to a semiconductor device and an operating method thereof.

2. Background Information

A System-on-Chip (SoC) enables data transmissions between various Intellectual Property (IP) blocks that use high-performance On-Chip Interconnects (OCIs). The On-Chip Interconnects may transmit multiple communication exchanges (transactions) between, for example, an arbitrary master device and a slave device. A channel formed between the master device and the slave device may be monitored by a monitoring device for the purpose of, for example, performing debugging or Quality-of-Service (QoS) control or tracking the occurrence of a particular event defined by a user.

SUMMARY

Example embodiments of the present disclosure provide an operating method of a semiconductor device for efficiently measuring the latency in a channel formed between a master device and a slave device of a System-on-Chip (SoC).

Example embodiments of the present disclosure also provide a semiconductor device for efficiently measuring the latency in a channel formed between a master device and a slave device of a System-on-Chip.

According to an example embodiment of the present disclosure, an operating method of a semiconductor device includes monitoring multiple request packets and multiple response packets (e.g., that are sent responsive to the request packets) that are being transmitted between a master device and a slave device. A target request packet that matches predefined identification (ID) information is detected from among the request packets. An operation of a latency counter is initiated. Latency is a time interval between a cause and effect, such as between a request packet that is sent as a cause and a response packet that is responsive to the request packet as an effect. The latency counter is for measuring the latency of a communication exchange (transaction) that includes the target request packet and a target response packet that is one of the response packets that matches the predefined ID information. The target response packet is detected from among the response packets. The operation of the latency counter is terminated. A latency value of the communication exchange is acquired from the latency counter.

According to another example embodiment of the present disclosure, an operating method of a semiconductor device includes monitoring multiple communication exchanges (transactions) between a first Intellectual Property (IP) block and a second Intellectual Property (IP) block, which are provided in a System-on-Chip (SoC). Predefined first ID information and predefined second ID information are received from outside the SoC. The latency of a first transaction that is one of the communication exchanges that matches the first ID information is measured by using a latency counter. The latency of a second transaction that is one of the communication exchanges that matches the second ID information is measured by using the latency counter. An average latency and a peak latency are computed based on the measured latency of the first transaction and the measured latency of the second transaction.

According to still another example embodiment of the present disclosure, a semiconductor device includes a filtering module that detects a target request packet that matches predefined ID information from among multiple request packets that are being transmitted between a master device and a slave device. A configuration module receives the predefined ID information and provides the predefined ID information to the filtering module. A latency counter measures the latency of a communication exchange (transaction) that includes the target request packet and a target response packet that is one of the response packets that matches the predefined ID information. A control module controls an operation of the latency counter and detects the target response packet from among the response packets.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Advantages and features of the present disclosure and methods of accomplishing the same may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings.

FIG. 1is a schematic block diagram of a semiconductor device according to an example embodiment of the present disclosure.

Referring toFIG. 1, a semiconductor device100includes one or more Intellectual Property (IP) blocks110and112and a monitoring device200. In some example embodiments, the semiconductor device100may further include a memory controller114, and the memory controller114may also be implemented as an Intellectual Property (IP) block. Intellectual Property blocks as described herein communicate using packets in accordance with an Intellectual Property (IP) standard.

The semiconductor device100is an Integrated Circuit (IC) including typical computer elements such as a processing unit, a controller, an interface, and the like. For example, the semiconductor device100may include a System-on-Chip (SoC). The computer elements may be implemented as Intellectual Property (IP) blocks that communicate using Intellectual Property packets that carry data. Examples of the IP blocks110and112may include a Central Processing Unit (CPU) and a Graphic Processing Unit (GPU), but the present disclosure is not limited thereto.

The IP blocks110and112and the memory controller114may be implemented on a single silicon die, and may exchange data with each other via an on-chip interconnect (OCI)130. The memory controller114may control a memory device300.

The monitoring device200monitors communication exchanges (transactions) between the IP blocks110and112and the memory controller114, which exchange data with each other via the OCI130. By monitoring data exchanged via the OCI130, channels formed between the IP blocks110and112and the memory controller114may be debugged, Quality of Service (QoS) may be controlled, or the occurrence of a particular event defined by a user may be tracked.

The monitoring device200may perform transaction monitoring at any desired location in the semiconductor device100. As illustrated inFIG. 1, the monitoring device200may monitor a transaction associated with the IP Block110or a transaction associated with the IP block112. However, the locations at which the monitoring device200performs transaction monitoring are not limited to those illustrated inFIG. 1, and may include various other arbitrary locations inside the semiconductor device100depending on the intended use of the semiconductor device100.

A communication exchange (transaction) includes a request packet and a response packet (e.g., sent in response to the request packet). For example, a read transaction and a write transaction may occur between the IP block110, which operates as a master device, and the memory controller114, which operates as a slave device. More specifically, for a read transaction, in response to the IP block110transmitting a read request packet to the memory controller114, the memory controller114may transmit a read response packet to the IP block110as a response to the read request packet.

In a case in which multiple master/slave relationships are established in the semiconductor device100or multiple tasks are allocated to a single master/slave relationship, multiple transactions may be monitored in the semiconductor device100. In this case, multiple request packets and multiple response packets may be transmitted between a master device and a slave device.

In some example embodiments, each of the request packets and the response packets may include identification (ID) information. More specifically, each of the request packets and the response packets may include at least one of transaction ID information and transaction attribute information for uniquely identifying each transaction. For example, the transaction ID information may include unique ID information for identifying a master device or a slave device. The transaction attribute information may include burst length attribute information and cache snooping type attribute information. If there exist multiple transactions, each of the transactions may be identified using the transaction ID information and the transaction attribute information.

FIG. 2is a timing diagram for explaining how to measure the latency in a channel formed between a master device and a slave device of the semiconductor device according to the example embodiment ofFIG. 1.

More specifically,FIG. 2illustrates the results of performing transaction monitoring at a desired location in the semiconductor device100by using the monitoring device200.

Referring toFIG. 2, three request packets having transaction IDs of 0, 1, and 0, respectively, are sequentially detected at times t0, t1, and t2, respectively. At a time t7, a response packet corresponding to the request packet detected at the time t1with a transaction ID of 1 is detected. Response packets respectively corresponding to the request packets detected at the times t0and t2with a transaction ID of 0 are detected at times t9and t11, respectively.

In a case in which multiple response packets are detected, as illustrated inFIG. 2, they can be identified by their respective transaction IDs if they correspond to request packets having different transaction IDs. On the other hand, the order in which response packets for request packets having the same transaction ID are detected follows the order in which the request packets having the same transaction ID are detected. That is, the order in which the response packets for the request packets detected at the times t0and t2with a transaction ID of 0 (for example, the response packets at the times t9and t11) are detected follows the order in which the corresponding request packets are detected. Accordingly, even response packets for request packets having the same transaction ID can also be properly identified.

The semiconductor device100may count the number of request packets with corresponding response packets that are yet to be detected.FIG. 2shows a Multiple Outstanding (MO) count value for a case in which a target transaction ID is 0 and an MO count value for a case in which the target transaction ID is 1.

For example, in a case in which the target transaction ID is 0, an MO count value is increased by 1 to a value of 1 upon the detection of the request packet having a transaction ID of 0 at the time t0. The MO count value is increased again by 1 to a value of 2 upon the detection of the request packet having a transaction ID of 0 at the time t2. Then, the MO count value is lowered by 1 to a value of 1 upon the detection of the response packet having a transaction ID of 0 at the time t9and is lowered again by 1 to a value of 0 upon the detection of the response packet having a transaction ID of 0 at the time t11.

In another example, in a case in which the target transaction ID is 1, the MO count value is increased by 1 to a value of 1 upon the detection of the request packet having a transaction ID of 1 at the time t1and is lowered by 1 to a value of 0 upon the detection of the response packet having a transaction ID of 1 at the time t7.

To compute an MO count value, the semiconductor device100may use an MO counter that will be described later with reference toFIG. 3.

Latency needs to be measured to debug a channel formed in the semiconductor device100or to control QoS. Latency may be measured by measuring the amount of time that it takes for a response packet for a request packet to be generated in a channel formed between a master device and a slave device. From the viewpoint of the monitoring device200, latency may be measured by measuring the amount of time from the detection of a request packet to the detection of a response packet for the request packet.

For example, the latency of a transaction that includes the request packet detected at the time t0with a transaction ID of 0 may be measured to be 10. That is, the latency in this example is the amount of time from the time t0(i.e., when the request packet having a transaction ID of 0 is detected) to the time t9(i.e., when a response packet for the request packet having a transaction ID of 0 is detected). Similarly, the latency of a transaction including the request packet detected at the time t1with a transaction ID of 1 may be measured to be 7. In this example, the latency is the amount of time from the time t1(i.e., when the request packet having a transaction ID of 1 is detected) to the time t7(i.e., when a response packet for the request packet having a transaction ID of 1 is detected).

As mentioned above, if multiple transactions are performed in the channel formed in the semiconductor device100, latency counting needs to be performed for each of the transactions to measure the latency of each of the transactions. However, this consumes a considerable amount of resources of the semiconductor device100such as latency counters. For example, in order to measure the latency of n transactions (where n is a natural number), at least n latency counters may be needed, and m MO counters may be needed if there are m transaction IDs (where m is a natural number not greater than n).

FIG. 3is a schematic block diagram of a monitoring device of the semiconductor device according to the example embodiment ofFIG. 1.

Referring toFIG. 3, the monitoring device200includes a configuration module210, a filtering module220, an MO counter230, a Response Ordering (RO) counter240, a control module250, and a latency counter260.

The configuration module210receives predefined ID information from outside the monitoring device200and provides the predefined ID information to the filtering module220. In some example embodiments, only a transaction that matches the predefined ID information, from among other transactions that are being transmitted over the channel formed in the semiconductor device100, is monitored. The predefined ID information may be ID information configured in advance by a user or an application and received from outside the monitoring device200or the semiconductor device100. However, the present disclosure is not limited to these example embodiments. That is, the predefined ID information may be stored in a particular IP block in the monitoring device200or the semiconductor device100.

In some example embodiments, the predefined ID information, which is provided by the configuration module210, may include at least one of transaction ID information and transaction attribute information. For example, the transaction ID information may include unique ID information for identifying a master device or a slave device. The transaction attribute information may include burst length attribute information and cache snooping type attribute information.

The filtering module220detects a target request packet that matches the ID information provided by the configuration module210from among multiple request packets that are being transmitted over a channel between a master device and a slave device. This is for measuring latency only for the target request packets that match the ID information provided by the configuration module210.

The MO counter230counts the number of request packets with corresponding response packets that are yet to be detected, from among the request packets.

The RO counter240determines whether a response packet has been detected for each of the request packets. More specifically, when latency measurement is initiated, the RO counter240receives an MO count value mo_value from the MO counter230and sets the MO count value mo_value as its initial count value. During latency measurement, the RO counter240lowers an RO count value resp_ordering whenever a response packet is detected for any one of the request packets.

The latency counter260will hereinafter be described. The latency counter260measures the latency of a transaction including the target request packet and a target response packet that matches the predefined ID information.

The control module250detects the target response packet from among the response packets that are being transmitted over the channel between the master device and the salve device. The control module250controls the latency counter260and may thus initiate or terminate the operation of the latency counter260. For example, the control module250terminates the operation of the latency counter260when the RO count value resp_ordering of the RO counter240reaches zero.

FIG. 4is a timing diagram for explaining an operating method of a semiconductor device, according to an example embodiment of the present disclosure.FIG. 5is a flowchart illustrating the operating method according to the example embodiment ofFIG. 4.

Referring toFIGS. 4 and 5, an operating method of a semiconductor device, according to an example embodiment of the present disclosure, includes monitoring multiple request packets and multiple response packets that are being transmitted between a master device and a slave device. In some example embodiments, the master device may correspond to a first IP block provided in an SoC, and the slave device may correspond to a second IP block provided in the SoC.

It is assumed that a target transaction to be subjected to latency measurement is a transaction having a transaction ID of 0 and having a “Read-Shared” (“RS”) value as cache snooping type attribute information. Accordingly, transactions having a transaction ID of nonzero and having a “Read-No-Snoop” (“RNS”) value as cache snooping type attribute information are excluded from latency counting. Identification information for detecting a target transaction may be provided by the configuration module210.

The sampling of the request packets and the response packets is initiated (S501). Thereafter, a determination is made as to whether a request packet detected over a channel between the master device and the slave device matches the ID information provided by the configuration module210(S503). A request packet detected at a time t0has a transaction ID of 0, but has the “RNS” value as cache snooping type attribute information. Thus, the request packet detected at the time t0is excluded from latency counting. A request packet detected at a time t1has a transaction ID of 0 and has the “RS” value as cache snooping type attribute information. Thus, the request packet detected at the time t1matches the ID information provided by the configuration module210. Accordingly, the request packet detected at the time t1is selected as a target request packet.

Thereafter, once the request packet detected at the time t1is selected as the target request packet, the MO count value mo_value of the MO counter230is set as the initial count value of the RO counter240. That is, the MO count value mo_value of 1 is set as the initial count value of the RO counter240(S505). Then, the operation of the latency counter260is initiated.

Thereafter, a target response packet corresponding to the request packet detected at the time t1is detected. More specifically, a determination is made as to whether a response packet detected over the channel between the master device and the slave device matches the ID information of the request packet detected at the time t1, for example, the transaction ID of the request packet detected at the time t1(S507). The latency counter260continues to increase a latency count value by, for example, 1, until a response packet corresponding to the target request packet arrives. For example, the latency counter260continues to increase the latency count value by, for example, 1, until a response packet that matches the ID information of the target request packet arrives.

If the detected response packet matches the ID information of the request packet detected at the time t1, the RO count value resp_ordering of the RO counter240is checked (S511). For example, a response packet detected at a time t9matches the ID information of the request packet detected at the time t1. If the RO count value resp_ordering is 1 or greater, the RO count value resp_ordering is lowered by, for example, 1 (S513), and latency counting is continued.

On the other hand, if the RO count value resp_ordering is 0, which means that latency counting is complete, a latency value is output (S513). Referring toFIG. 4, since the RO count value resp_ordering becomes zero after a time t8, a latency value of 102 is output.

Thereafter, sampling is completed (S515), and for a new sampling process, the detection of another target request packet that matches the ID information provided by the configuration module210is performed again.

In the operating method according to the example embodiment ofFIGS. 4 and 5, the latency of only some transactions is measured using a sampling technique, instead of measuring the latency of each and every transaction individually. Thus, the use of the resources of the semiconductor device100such as the MO counter230, the RO counter240, and the latency counter260can be minimized. Also, a latency value with sufficiently high precision for tasks such as debugging and QoS control can be obtained while conserving the resources of the semiconductor device100.

For example, an average latency and a peak latency that are computed based on multiple latency values may be used to perform tasks such as debugging and QoS control on the semiconductor device100. According to the present disclosure, an average latency and a peak latency with sufficiently high precision can be acquired while consuming only a small amount of resources.

In addition, a target transaction to be subjected to latency measurement can be customized. Thus, tasks such as debugging and QoS control can be performed in a properly customized manner for each individual application environment. For example, by setting an ID value for identifying a particular device as a target transaction ID for latency measurement, latency measurement can be performed only on transactions having a transaction ID desired by a user.

FIG. 6is a schematic block diagram of a monitoring device of a semiconductor device according to another example embodiment of the present disclosure.

Referring toFIG. 6, a monitoring device200includes a configuration module210, a filtering module220, an MO counter230, an RO counter240, a control module250, a latency counter260, and a tracked ID configuration module270.

The configuration module210, the filtering module220, the MO counter230, the RO counter240, the control module250, and the latency counter260are the same as their respective counterparts ofFIG. 3. Thus, detailed descriptions thereof will be omitted.

The tracked ID configuration module270configures current tracked ID information using ID information provided by the configuration module210. The current tracked ID information is used to store a target transaction ID for latency measurement, for example, in case a channel formed between a master and a slave device is busy. In other words, if the current tracked ID information is set to, for example, 1, only request packets and response packets having a transaction ID of 1 are subjected to latency measurement, regardless of a transaction ID included in the ID information provided by the configuration module210, while the channel formed between the master device and the slave device is being busy.

The filtering module220determines the state of the channel formed between the master device and the slave device. Then, if the channel formed between the master device and the slave device is idle, the filtering module220detects each request packet that matches the ID information provided by the configuration module210as a target request packet. On the other hand, if the channel formed between the master device and the slave device is busy, the filtering module220detects each request packet that matches the current tracked ID information as a target request packet.

FIG. 7is a timing diagram for explaining an operating method of a semiconductor device, according to another example embodiment of the present disclosure.

It is assumed that a target transaction to be subjected to latency measurement is a transaction having a transaction ID of 0 and having a “RS” value as cache snooping type attribute information. Accordingly, transactions having a transaction ID of nonzero and having a “RNS” value as cache snooping type attribute information are excluded from latency counting. Identification information for detecting a target transaction may be provided by the configuration module210. Since the transaction ID of the target transaction is 0, current tracked ID information may also be set to 0.

A channel formed between a master device and a slave device is busy during a period from a time t1to a time t13. Thus, latency measurement is performed only on request packets and response packets having a current tracked ID of 0 and having the “RS” value as cache snooping type attribute information, detected during the period from the time t1to the time t13. Since the channel between the master device and the slave device is busy during the period from the time t1to the time t13, any request packet having a transaction ID of 1, detected during the period from the time t1to the time t13, is excluded from selection as a target request packet. Accordingly, latency measurement is performed during only part of the period from the time t1to the time t13, i.e., during a period from the time t1to a time t9.

The operating method according to the example embodiment ofFIG. 7can lower a sampling rate, and at the same time, can enhance the precision of latency measurement, compared to the operating method that has been described above with reference toFIGS. 3 through 6.

FIG. 8is a flowchart illustrating the operating method according to the example embodiment ofFIG. 7.

Referring toFIG. 8, the operating method according to the present example embodiment includes monitoring multiple request packets and multiple response packets that are being transmitted between a master device and a slave device.

The sampling of the request packets and the response packets is initiated (S801). Thereafter, a determination is made as to whether the channel between the master device and the slave device is idle (S803).

If the channel between the master device and the slave device is idle, a determination is made as to whether a request packet detected over the channel between the master device and the slave device matches ID information provided by the configuration module210(S805).

If the detected request packet does not match transaction attribute information included in the ID information provided by the configuration module210, a determination is made as to whether the detected request packet matches transaction ID information included in the ID information provided by the configuration module210(S809). If the detected request packet matches transaction ID information included in the ID information provided by the configuration module210, current tracked ID information cur_tracked_id provided by the configuration module210is set as the ID information provided by the configuration module210(S811).

If the channel between the master device and the slave device is idle, a determination is made as to whether the detected request packet matches the current tracked ID information cur_tracked_id (S807). If the detected request packet matches the current tracked ID information, the operating method proceeds to S805.

If a determination is made in S805that the detected request packet matches the transaction attribute information included in the ID information provided by the configuration module210, the current racked ID information cur_tracked_id is set as the ID information provided by the configuration module210(S813).

Thereafter, the MO count value mo_value of the MO counter230is set as the initial count value of the RO counter240. That is, the MO count value mo_value of 1 is set as the initial count value of the RO counter240(S815). Then, the operation of the latency counter260is initiated.

Thereafter, a target response packet corresponding to the target request packet is detected. More specifically, a determination is made as to whether a response packet detected over the channel between the master device and the slave device matches the ID information of the target request packet, for example, the transaction ID of the target request packet (S817). If the detected response packet does not match the ID information of the target request packet, the count value of the latency counter260is increased by, for example, 1 (S819).

If the detected response packet matches the ID information of the target request packet, the RO count value resp_ordering of the RO counter240is checked (S821). If the RO count value resp_ordering is 1 or greater, the RO count value resp_ordering is lowered by, for example, 1 (S823), and latency counting is continued.

On the other hand, if the RO count value resp_ordering is 0, which means that latency counting is completed, a latency value is output (S825).

Thereafter, sampling is completed (S827), and for a new sampling process, the detection of another target request packet that matches the ID information provided by the configuration module210is performed again.

In the operating method according to the present example embodiment, the latency of only some transactions is measured using a sampling technique, instead of measuring the latency of each and every transaction individually. Thus, the use of the resources of the semiconductor device100such as the MO counter230, the RO counter240, and the latency counter260can be minimized. Also, a latency value with sufficiently high precision for tasks such as debugging and QoS control can be obtained while conserving the resources of the semiconductor device100.

For example, to perform tasks such as debugging and QoS control on the semiconductor device100, an average latency and a peak latency that are computed based on multiple latency values may be used. According to the present disclosure, an average latency and a peak latency with sufficiently high precision can be acquired while consuming only a small amount of resources.

In addition, a target transaction to be subjected to latency measurement can be customized. Thus, tasks such as debugging and QoS control can be performed in a properly customized manner for each individual application environment. For example, by setting an ID value for identifying a particular device as a target transaction ID for latency measurement, latency measurement can be performed only on transactions having a transaction ID desired by a user.

FIG. 9is a block diagram of a semiconductor system to which a semiconductor device and an operating method of the semiconductor device, according to some example embodiments of the present disclosure, are applicable.

Referring toFIG. 9, a semiconductor system1100may include a controller1110, an input/output (I/O) device1120, a memory device1130, an interface1140, and a bus1150. The controller1110, the I/O device1120, the memory device1130, and/or the interface1140may be connected to one another via the bus1150. The bus1150may be a path via which data is transmitted.

The controller1110may include at least one of a microprocessor, a digital signal processor, a microcontroller, and a logic element performing similar functions to a microprocessor, a digital signal processor, or a microcontroller. Examples of the I/O device1120include a keypad, a keyboard, a display device, and the like. The memory device1130may store data and/or commands. The interface1140transmits data to or receives data from a communication network. The interface1140may be a wired or wireless interface. Examples of the interface1140include an antenna, a wired or wireless transceiver, and the like.

Although not specifically illustrated, the semiconductor system1100may also include an operating memory for improving the operation of the controller1110, such as a high-speed dynamic random access memory (DRAM) and/or static random access memory (SRAM).

A semiconductor device according to some example embodiments of the present disclosure may be provided inside the memory device1130or may be provided as part of the controller1110or the I/O device1120.

The semiconductor system1110may be applicable to a Personal Digital Assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or any type of electronic product capable of transmitting and/or receiving information in a wireless environment.

FIGS. 10 through 12are schematic views illustrating example semiconductor systems to which a semiconductor device and an operating method of the semiconductor device, according to some example embodiments of the present disclosure, are applicable.

More specifically,FIG. 10illustrates a tablet PC1200,FIG. 11illustrates a notebook computer1300, andFIG. 12illustrates a smartphone1400. At least one semiconductor device according to some example embodiments of the present disclosure may be used in the tablet PC1200, the notebook computer1300, and the smartphone1400.

Obviously, a semiconductor device according to some example embodiments of the present disclosure may also be used in various IC devices other than those set forth herein.

That is, only the tablet PC1200, the notebook computer1300, and the smartphone1400have been described herein as examples of the semiconductor system, but the present disclosure is not limited thereto.

In some example embodiments, the semiconductor system may also be provided as a computer, an Ultra Mobile PC (UMPC), a work station, a net-book computer, a PDA, a portable computer, a wireless phone, a mobile phone, an electronic-book (e-book), a Portable Multimedia Player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3-dimensional (3D) television set, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, or a digital video player.

Although preferred embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure as set forth in the accompanying claims.