Method for processing error of received packet in ethernet MAC layer

A method for processing a received packet in a MAC (Medium Access Control) layer of an Ethernet which receives a packet from a physical layer and transmits the received packet to a switch. The method includes the steps of detecting an error while receiving the packet from the physical layer; upon failure to detect error, transmitting the received packet to the switch; and, upon detection of error, stopping the transmission of the received packet to the switch.

CLAIM OF PRIORITY

This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. Section 119 from an application for “Method for Processing Error of Received Packet in Ethernet MAC Layer” filed in the Korean Industrial Property Office on Dec. 28, 1998 and there duly assigned Serial No. 98-59204.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a method for processing a received packet in a MAC (Medium Access Control) layer of an Ethernet, and in particular, to a method for processing an error in the received packet.

2. Description of the Related Art

A local area network (LAN) interconnects a group of data communication terminals within a limited area. This type of LAN topology is classified into bus type, ring type, star type and tree type. The bus type network is the most commonly used network, and the Ethernet is one of the oldest communication protocols for communication terminals implemented in the bus physical topology.

Meanwhile, a MAC layer of the Ethernet processes a packet received from a physical layer. When an error occurs during the reception of data from the physical layer, the MAC layer performs the corresponding error processing operation. More specifically, when an error occurs in the packet exceeding 64 bytes while receiving the packet from the physical layer, the MAC layer receives the entire packet and transmits the received packet to the next stage along with an error signal indicating the occurrence of an error in the received packet. A MAC protocol standard and a logical link control (LLC) protocol standard, including the error processing method for the received data in the MAC layer, have been published by the IEEE (Institute of Electrical and Electronics Engineers) 802 Committee and certified by ISO (International Standard Organization).

According to the above standards, when an error occurs in the packet not exceeding 64 bytes while receiving the packet, the MAC layer will discard the error packet. However, when an error occurs in a packet exceeding 64 bytes, the MAC layer will receive the entire packet and transmit the received packet to the next stage (e.g., switch), along with an error signal indicating the occurrence of the error. Therefore, the receipt of the unnecessary error packet causes an increase in the overhead of the system. In particular, a switch in the next stage receiving the error packet wastes time by receiving the unnecessary error packet, thereby causing a degradation of the system performance.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a method for reducing an overhead due to the reception of error packets in an MAC layer of the Ethernet.

It is another object of the present invention to provide a method for saving the time wasted by receiving the unnecessary packet in a MAC layer of the Ethernet.

It is further another object of the present invention to provide a method for improving the receiving capability in a MAC layer of the Ethernet.

To achieve the above objects, there is provided a method for processing a received packet in a MAC (Medium Access Control) layer of an Ethernet which receives a packet from a physical layer and transmits the received packet to a switch.

In accordance with one aspect of the present invention, a method for processing a received packet in a MAC layer comprises the steps of detecting an error while receiving the packet from the physical layer; transmitting the received packet to the switch upon the failure to detect an error; and, stop the transmission of the receiving packet to the switch upon detecting an error.

In accordance with another aspect of the present invention, a method for processing a received packet in a MAC layer comprises the steps of receiving a packet from the physical layer and storing the received packet in the FIFO (First-In, First-Out) memory; detecting error while receiving the packet; stopping the storage of the received packet to the FIFO memory upon the detection of error; and, transmitting a signal indicating the occurrence of error and a signal indicating the end of the received packet to the switch. Further, the method comprises the step of preparing to receive the next packet from the physical layer, after receiving the error packet.

A DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment of the present invention will be described herein below with reference to the accompanying drawings. For the purpose of clarity, well-known functions or constructions are not described in detail as they would obscure the invention in unnecessary detail.

FIG. 1shows a configuration according to an embodiment of the present invention for processing error in a received packet in a MAC layer. The MAC layer stores the packet received from a physical layer10in a FIFO (First-In, First-Out) memory50and transmits the stored packet to a switch (not shown) in the next stage through a switch engine interface60. Such MAC layer includes a FIFO controller20, an error controller40, and the FIFO memory50. The FIFO controller20also includes a state machine30.

InFIG. 1, when the FIFO controller20receives a packet S2from the physical layer10, the error controller40examines whether the received packet (e.g., 4 bits) contains an error. The error controller40checks for a collision of the received packet, an overflow of the FIFO memory50, and the parity and the CRC (Cyclic Redundancy Code) of the received packet, to examine whether the received packet has error. When it is determined that the received packet contains error, the error controller40provides the FIFO controller20with an error signal S5. The FIFO memory50stores the packet received from the physical layer10and then transmits the stored packet to the switch engine interface60in response to a control signal S3from the FIFO controller20. The FIFO controller20controls the operation of storing the packet received from the physical layer10in the FIFO memory50and then transmitting the stored packet to the switch engine interface60, using the control signal S3. Here, an output enable signal OEN, a write enable signal WEN or a chip select signal /CS can be used for the control signal S3. The state machine30included in the FIFO controller20determines the operating state of the FIFO controller20according to the error signal S5from the error controller40. In the embodiment of the present invention, the FIFO controller20operates in an idle state, a normal state or an error state according to the state machine30.

Further, the reference letter S1denotes a signal indicating the reception of a packet from the physical layer10, and the reference letter S4denotes a signal ERR indicating the occurrence of error during the receipt of the packet in the FIFO controller20and a signal EOP (End of Packet) indicating the completion of receiving the packet.

FIG. 2is a state diagram illustrating an operating state of the FIFO controller20, determined by the state machine30.FIG. 3is a timing diagram illustrating an error processing operation for the received packet which is performed in the FIFO controller20ofFIG. 1.

When the error controller40determines that a new packet has been normally received from the physical layer10ofFIG. 1, the FIFO controller20stores the received packet in the FIFO memory50and then transmits the stored packet to the switch engine interface60. When the normal packet is received normally, the S1signal (or data valid signal) is represented by “1.” In this case, the FIFO controller20operates in the normal state34.

However, when the error controller40determines that an error has occurred while transmitting the received packet to the switch engine interface60(i.e., when S5=“1”), the FIFO controller20changes to the error state36. In this situation, the FIFO controller20stops transmitting the received packet to the switch engine interface60. More specifically, the FIFO controller20provides a chip select signal /CS of level “1’, as shown inFIG. 3, to “the FIFO memory50to prevent the received packet from being stored in the FIFO memory50, and at the same time, provides the error signal ERR and the end-of-packet signal EOP to the switch engine interface60.

In prior art, when an error occurs during the reception mode of the packet, the FIFO controller20receives the entire error packet and transmits it to the switch engine interface60. When an error occurs at the time where the end of the packet is completely received, the FIFO controller20provides the switch engine interface60with a signal indicating the complete reception mode of the packet.

During the error processing operation in error state36, upon the receipt of the S1signal of level “0” indicating that there is no packet to be received from the physical layer10, the FIFO controller20converts to the idle state32. In the idle state32, the FIFO controller20prepares to receive the next packet from the physical layer10.

As described above, upon the receipt of an error packet from the physical layer, the MAC layer discards the error packet and at the same time provides a switch in the next stage with a signal indicating the occurrence of an error. In this manner, it is possible to reduce an overhead due to the reception of the error packet in the MAC layer. In addition, it is possible to save the time wasted as a result of receiving the unnecessary packet. In summary, it is possible to improve the receiving capability in the MAC layer of the Ethernet.