Storage device, operating method of storage device, and electronic device including storage device

Disclosed is an operating method of a storage device which includes a plurality of nonvolatile memory chips. The method includes providing, at the storage device, information of a capacity of each of the plurality of nonvolatile memory chips to an external host device, receiving, at the storage device, information of a plurality of groups from the external host device, performing a reset after receiving the information of the plurality of groups, mapping, at the storage device, the plurality of nonvolatile memory chips with the plurality of groups, and configuring the plurality of nonvolatile memory chips so as to correspond to the plurality of groups, after performing the reset.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0028321 filed on Mar. 3, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

Embodiments relate to an electronic device, an operating method of the storage device, and an electronic device including the storage device.

2. Description of the Related Art

A storage device may include nonvolatile memory chips, and may store data in the nonvolatile memory chips. The nonvolatile memory chips may include various memory chips such as flash memory chips, magnetic memory chips, phase change memory chips, and resistive memory chips.

SUMMARY

According to an embodiment, an operating method of a storage device which includes a plurality of nonvolatile memory chips includes providing, at the storage device, information of a capacity of each of the plurality of nonvolatile memory chips to an external host device, receiving, at the storage device, information of a plurality of groups from the external host device, performing a reset after receiving the information of the plurality of groups, mapping, at the storage device, the plurality of nonvolatile memory chips with the plurality of groups, and configuring the plurality of nonvolatile memory chips so as to correspond to the plurality of groups, after performing the reset.

According to an embodiment, a storage device includes a plurality of nonvolatile memory chips, and a memory controller that receives information of a plurality of groups from an external host device and maps at least one nonvolatile memory chip of the plurality of nonvolatile memory chips with each of the plurality of groups. In response to that an access request for one group of the plurality of groups is received from the external host device, the memory controller accesses at least one nonvolatile memory chip corresponding to the one group from among the plurality of nonvolatile memory chips.

According to an embodiment, an electronic device includes a central processing unit, a random access memory that is used as a working memory by the central processing unit, and a storage device that stores original data of data loaded onto the random access memory by the central processing unit and to store data generated by the central processing unit. The storage device includes a plurality of nonvolatile memory chips, and a memory controller that receives information of a plurality of groups from the central processing unit and maps at least one nonvolatile memory chip of the plurality of nonvolatile memory chips with each of the plurality of groups. In response to that an access request for one group of the plurality of groups is received from the central processing unit, the memory controller accesses at least one nonvolatile memory chip corresponding to the one group from among the plurality of nonvolatile memory chips. Based on that a fail occurs in at least one nonvolatile memory chip of the plurality of nonvolatile memory chips, the memory controller updates mapping between the plurality of groups and the plurality of nonvolatile memory chips.

DETAILED DESCRIPTION

FIG.1illustrates an electronic device10according to a first embodiment.

Referring toFIG.1, the electronic device10may include a storage device100and a host device20, which may be, e.g., an external host device. The storage device100may perform a write, read, or erase operation in response to a write, read, or erase request of the host device20.

The storage device100may include, e.g., first to fourth nonvolatile memory chips110,120,130, and140, and a memory controller150.

The first to fourth nonvolatile memory chips110,120,130, and140may include various memory chips such as flash memory chips, ferroelectric memory chips, magnetic memory chips, phase change memory chips, and resistive memory chips. The first to fourth nonvolatile memory chips110,120,130, and140may include the same type of memory chips or different types of memory chips. The first to fourth nonvolatile memory chips110,120,130, and140may have the same capacity or different capacities. The first to fourth nonvolatile memory chips110,120,130, and140may operate based on the same structure or different structures.

The memory controller150may access the first nonvolatile memory chip110through a first channel CH1. The memory controller150may access the second nonvolatile memory chip120through a second channel CH2. The memory controller150may access the third nonvolatile memory chip130through a third channel CH3. The memory controller150may access the fourth nonvolatile memory chip140through a fourth channel CH4.

The memory controller150may access the first to fourth nonvolatile memory chips110,120,130, and140in response to an access request of the host device20. The access request may include a write request, a read request, or an erase request. The access to the first to fourth nonvolatile memory chips110,120,130, and140may include a write operation, a read operation, and an erase operation.

The memory controller150may control the storage device100in an integration mode or an individual mode in response to a request of the host device20. In the integration mode, the memory controller150may integrate storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140so as to be provided to the host device20. In the individual mode, the memory controller150may individually, e.g., respectively, provide the storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140to the host device20.

The memory controller150may communicate with the host device20through one channel or through two or more independent channels. The two or more independent channels may be called lanes or any other name defined by the communication protocol. An example where one nonvolatile memory chip communicates with the memory controller150through one channel is illustrated inFIG.1. However, two or more nonvolatile memory chips may share one channel and may communicate with the memory controller150. Alternatively, two or more nonvolatile memory chips may be connected with one channel.

An example where the storage device100includes 4 nonvolatile memory chips and 4 channels is illustrated inFIG.1. However, in the storage device100, the number of nonvolatile memory chips and the number of channels between nonvolatile memory chips and a memory controller may be varied.

FIG.2illustrates an example in which the storage device100and the host device20set a storage space in an integration mode.

Referring toFIGS.1and2, in operation S110, the storage device100may provide information of a total storage space of the first to fourth nonvolatile memory chips110,120,130, and140to the host device20. For example, the storage device100may provide the host device20with information of a total storage space specified to be provided to the host device20from among the storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140.

In operation S120, the storage device100may receive information of a logical address group from the host device20. The host device20may allocate logical addresses, e.g., continuous logical addresses, to the storage device100, based on the information of the total storage space. The host device20may provide the storage device100with the information of the logical address group including the continuous logical addresses.

In operation S130, the storage device100may map a physical address group of the total storage space of the first to fourth nonvolatile memory chips110,120,130, and140to the logical address group allocated by the host device20.

FIG.3illustrates an example in which the memory controller150provides the host device20with storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140based on the process ofFIG.2, in the integration mode.

Referring toFIGS.1and3, the first nonvolatile memory chip110may provide a storage space corresponding to a first storage space SS1to the host device20through the memory controller150. The second nonvolatile memory chip120may provide a storage space corresponding to a second storage space SS2to the host device20through the memory controller150. The third nonvolatile memory chip130may provide a storage space corresponding to a third storage space SS3to the host device20through the memory controller150. The fourth nonvolatile memory chip140may provide a storage space corresponding to a fourth storage space SS4to the host device20through the memory controller150.

In an example embodiment, the first to fourth storage spaces SS1, SS2, SS3, and SS4may be storage spaces provided to the host device20from among storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140. The storage spaces provided to the host device20may be specified such that a part of real storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140is provided to the host device20, for example.

For example, the memory controller150may use a part of a storage space of each or at least one of the first to fourth nonvolatile memory chips110,120,130, and140as a reserved area or an over provision (OP) area, not provided to the host device20. A storage space of the reserved area or the OP region may not be open to the host device20, and a capacity of the reserved area or the OP region may not be provided to the host device20. The reserved area may include a storage space used to operate the storage device100. The OP area may include a storage space used to further improve the performance of the storage device100, in addition to the reserved area.

The storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140may be identified and accessed based on physical addresses. Physical addresses included in the first to fourth storage spaces SS1, SS2, SS3, and SS4from among the physical addresses of the first to fourth nonvolatile memory chips110,120,130, and140may be changed. For example, a part, which is provided to the host device20through the memory controller150, from among the storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140, may be varied.

The memory controller150may integrate and manage the physical addresses of the first to fourth storage spaces SS1, SS2, SS3, and SS4into one physical address group PG. The memory controller150may map physical addresses of the physical address group PG and logical addresses of one logical address group LG by using a mapping table MT. The logical address of the logical address group LG may be allocated to the storage device100by the host device20.

The host device20may create first to third namespaces NS1, NS2, and NS3based on the logical address group LG. The first to third namespaces NS1, NS2, and NS3may correspond (or may be allocated) to different logical addresses belonging to the logical address group LG (or to logical address groups). The host device20may give a stream identifier (ID) to each of the first to third namespaces NS1, NS2, and NS3.

For example, a first stream ID may be allocated to the first namespace NS1, a second stream ID may be allocated to the second namespace NS2, and a third stream ID may be allocated to the third namespace NS3. In an example embodiment, the first to third namespaces NS1, NS2, and NS3may correspond to different applications executable at the host device20or may correspond to different users (or accounts of users) accessing the host device20.

When accessing a specific namespace of the first to third namespaces NS1, NS2, and NS3, the host device20may send an access request to the memory controller150together with a stream ID of the specific namespace. The memory controller150may access the first to fourth storage spaces SS1, SS2, SS3, and SS4, based on a stream ID.

In an example embodiment, a capacity of the first namespace NS1may correspond to a size of a storage space of one nonvolatile memory chip, a capacity of the second namespace NS2may correspond to a size of storage spaces of two nonvolatile memory chips, and a capacity of the third namespace NS3may correspond to a size of a storage space of one nonvolatile memory chip, but a capacity of each of the first to third namespaces NS1, NS2, and ND3may be varied.

FIG.4illustrates an example in which the host device20accesses the storage device100in the integration mode.

Referring toFIGS.1,3, and4, in the integration mode, the memory controller150may map one physical address group PG and one logical address group LG. Each of the first to fourth nonvolatile memory chips110,120,130, and140may include a plurality of memory blocks.

The memory controller150may access different memory blocks of the memory blocks belonging to the first to fourth nonvolatile memory chips110,120,130, and140in response to access requests having different stream IDs received from the host device20.

For example, as marked by a first arrow A1, the host device20may send an access request to the memory controller150together with a first stream ID SID1indicating the first namespace NS1. The memory controller150may access one memory block of the second nonvolatile memory chip120in response to the access request of the first arrow A1and the first stream ID SID1.

As marked by a second arrow A2, the host device20may send an access request to the memory controller150together with a second stream ID SID2indicating the second namespace NS2. The memory controller150may access another memory block of the second nonvolatile memory chip120in response to the access request of the second arrow A2and the second stream ID SID2.

As marked by a third arrow A3, the host device20may send an access request to the memory controller150together with the second stream ID SID2indicating the second namespace NS2. The memory controller150may access one memory block of the third nonvolatile memory chip130in response to the access request of the third arrow A3and the second stream ID SID2.

In the case where the memory controller150performs access requests having different stream IDs on different memory blocks, as marked by the first arrow A1and the second arrow A2, the access requests having the different stream IDs may be performed on the same nonvolatile memory chip. In such a case, e.g., the access request of the first arrow A1and the access request of the second arrow A2should be sequentially performed over time rather than at the same time, but such concurrent access requests from the different stream IDs may act as a delay factor.

FIG.5illustrates an example in which the storage device100and the host device20set a storage space in the individual mode.

Referring toFIGS.1and5, in operation S210, the storage device100may provide information of a storage space of each of the first to fourth nonvolatile memory chips110,120,130, and140to the host device20. For example, the storage device100may provide the host device20with information of a total storage space specified to be provided to the host device20from among the storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140.

In operation S220, the storage device100may receive information of namespaces and logical address groups respectively corresponding to the namespaces from the host device20. The host device20may allocate logical addresses, e.g., continuous logical addresses, to the storage device100, based on the information of the storage space of each of the first to fourth nonvolatile memory chips110,120,130, and140.

The host device20may allocate namespaces based on logical addresses of logical address groups. Namespaces may be allocated to different logical addresses belonging to logical addresses of a logical address group (e.g., to different logical address groups). The host device20may provide the storage device100with information of continuous namespaces and logical address groups respectively corresponding to the namespaces.

For example, the host device20may access the storage device100by an access unit defined by an operating system (or a file system), such as a sector or a cluster, and each of namespaces may include a plurality of access units. Accordingly, each of the namespaces may be regarded as a group of access units sharing a common stream ID. Also, the namespaces may be regarded as groups of access units corresponding to different stream IDs.

In operation S230, the storage device100may map the first to fourth nonvolatile memory chips110,120,130, and140with the namespaces. For example, the storage device100may map storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140with logical address groups of the namespaces, respectively.

A logical address group of each namespace may be mapped with a storage space of at least one nonvolatile memory chip. Thus, the storage device100may map a storage space with each namespace in units of nonvolatile memory chip.

FIG.6illustrates an example in which the memory controller150provides the host device20with storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140based on the process ofFIG.5, in the individual mode.

Referring toFIGS.1and6, the memory controller150may provide information of the first to fourth storage spaces SS1, SS2, SS3, and SS4of the first to fourth nonvolatile memory chips110,120,130, and140to the host device20.

The host device20may allocate the first to third namespaces NS1to NS3based on the information of the first to fourth storage spaces SS1, SS2, SS3, and SS4. The host device20may allocate namespaces in units of storage space of a nonvolatile memory chip.

For example, the host device20may create the first namespace NS1corresponding to a capacity of a storage space of one nonvolatile memory chip, the host device20may create the second namespace NS2corresponding to a capacity of a storage space of two nonvolatile memory chips, and the host device20may create the third namespace NS3corresponding to a capacity of a storage space of one nonvolatile memory chip. The host device20may allocate first to third logical address groups LG1, LG2, and LG3(different from each other) to the first to third namespaces NS1to NS3.

The host device20may provide the memory controller150with information (e.g., including the number or a size of each) of the first to third namespaces NS1, NS2, and NS3, along with information of the first to third logical address groups LG1, LG2, and LG3allocated to the first to third namespaces NS1, NS2, and NS3.

The memory controller150may select first to third physical address groups PG1, PG2, and PG3respectively corresponding to the first to third logical address groups LG1, LG2, and LG3from the first to fourth storage spaces SS1, SS2, SS3, and SS4, based on the information received from the host device20.

For example, the memory controller150may select physical addresses of the first storage space SS1as the first physical address group PG1, the memory controller150may select physical addresses of the second and third storage spaces SS2and SS3as the second physical address group PG2, and the memory controller150may select physical addresses of the fourth storage space SS4as the third physical address group PG3.

The memory controller150may map the first to third logical address groups LG1, LG2, and LG3with the first to third physical address groups PG1, PG2, and PG3, respectively.

For example, the memory controller150may map the first logical address group LG1and the first physical address group PG1by using a first mapping table MT, the memory controller150may map the second logical address group LG2and the second physical address group PG2by using a second mapping table MT2, and the memory controller150may map the third logical address group LG3and the third physical address group PG3by using a third mapping table MT3.

When accessing a specific namespace of the first to third namespaces NS1, NS2, and NS3, the host device20may send an access request to the memory controller150together with a stream ID of the specific namespace. The memory controller150may access the first to fourth storage spaces SS1, SS2, SS3, and SS4, based on a stream ID.

In the above example embodiment, additional description associated with components applied in common toFIGS.3and6will be omitted to avoid redundancy. Accordingly, components, which do not conflict with the components ofFIG.6, from among the components described with reference toFIG.3may be identically applied toFIG.6.

FIG.7illustrates an example in which the host device20accesses the storage device100in the individual mode.

Referring toFIGS.1,6, and7, the memory controller150may access different nonvolatile memory chips of the first to fourth nonvolatile memory chips110,120,130, and140in response to access requests having different stream IDs received from the host device20.

For example, as marked by a fourth arrow A4, the host device20may send an access request to the memory controller150together with the first stream ID SID1indicating the first namespace NS1. The memory controller150may access the first nonvolatile memory chip110mapped with the first namespace NS1in response to the access request of the fourth arrow A4and the first stream ID SID1.

As marked by a fifth arrow A5, the host device20may send an access request to the memory controller150together with the second stream ID SID2indicating the second namespace NS2. The memory controller150may access the second and third nonvolatile memory chips120and130mapped with the second namespace NS2in response to the access request of the fifth arrow A5and the second stream ID SID2.

As marked by a sixth arrow A6, the host device20may send an access request to the memory controller150together with the second stream ID SID2indicating the second namespace NS2. The memory controller150may access the second and third nonvolatile memory chips120and130mapped with the second namespace NS2in response to the access request of the sixth arrow A6and the second stream ID SID2.

In the case where the memory controller150performs access requests having different stream IDs on different memory blocks, the access requests having the different stream IDs may be performed on different nonvolatile memory chips. Accordingly, access requests having different stream IDs may be prevented from acting as a mutual delay factor.

In an example embodiment, as is the case for the second namespace NS2in the above example, when one namespace is mapped with two or more nonvolatile memory chips, an access request for the corresponding namespace may be interleaved to two or more nonvolatile memory chips. For example, data corresponding to one access request may be divided based on the number of nonvolatile memory chips. The divided data may be simultaneously exchanged with the nonvolatile memory chips.

In an example embodiment, an access request for a namespace mapped with one nonvolatile memory chip may not be interleaved.

FIG.8illustrates an example of a process in which the storage device100and the host device20configure the individual mode.

Referring toFIGS.1and8, in operation S310, the host device20may send a mode set request to the memory controller150. The mode set request may include information about the individual mode, e.g., information about the number of namespaces, a size of each of the namespaces, and a logical address group allocated to each of the namespaces.

In operation S320, the memory controller150may save or store mode setting information in response to the mode set request. The memory controller150may determine whether the individual mode set requested by the host device20is configurable (e.g., is capable of being mapped).

For example, the memory controller150may determine whether physical address groups are configurable as much as the number corresponding to the mode set request of the host device20(e.g., whether to support stream IDs, the number of which corresponds to the number of physical address groups), may determine whether a size of each of the physical address groups is configurable, and may determine whether to map logical address groups with the physical address groups (or whether the configuration of mapping tables is possible).

In operation S330, the memory controller150may send a response to the host device20. The response may include information indicating whether the mode setting information is completely stored and whether the configuration of the mode is possible.

When the configuration of the mode is not possible, the host device20and the storage device100may terminate the configuration of the mode.

When the configuration of the mode is possible, in operation S340, the host device20and the memory controller150may perform a reset. The reset may include a cold reset in which a power is interrupted and is then supplied, or a hot reset in which initialization is performed, with a power maintained.

In operation S350, the memory controller150may configure the individual mode based on the mode setting information. For example, as described with reference toFIG.6, the memory controller150may configure the first to third physical address groups PG1, PG2, and PG3and the first to third mapping tables MT1, MT2, and MT3.

In operation S360, the memory controller150may send, to the host device20, a response indicating that the configuration of the individual mode is completed.

In response, in operation S370, the host device20may send a request for creating a namespace to the memory controller150. The request for creating a namespace may include information of stream IDs to be allocated to namespaces.

In response to the request for creating a namespace, in operation S380, the memory controller150may map the first to third logical address groups LG1, LG2, and LG3with the first to third physical address groups PG1, PG2, and PG3, respectively. Also, the memory controller150may correlate the first to third logical address groups LG1, LG2, and LG3with the first to third stream IDs SID1, SID2, and SID3, respectively.

FIG.9illustrates an example in which the storage device100and the host device20update a configuration of the individual mode.

Referring toFIGS.1and9, in operation S410, the memory controller150may detect a fail. For example, when an error that is uncorrectable by an error correction algorithm occurs in at least a portion of a storage space of at least one nonvolatile memory chip of the first to fourth nonvolatile memory chips110,120,130, and140, the memory controller150may detect that a fail occurs in the at least a portion of the storage space, in which the error occurs.

In response to the detection of the fail, in operation S420, the memory controller150may collect information of a storage space of each nonvolatile memory chip. For example, the memory controller150may exclude the at least a portion of the storage space, in which the error occurs, from the storage space of the nonvolatile memory chip where the fail occurs. Thus, the storage space (or capacity) of the nonvolatile memory chip where the fail is detected may decrease.

In operation S430, the memory controller150may provide the host device20with information providing notification that the fail occurred, and information of storage spaces of the first to fourth nonvolatile memory chips110,120,130, and140, which are changed due to the fail.

The host device20may reconfigure the individual mode in response to the information provided from the memory controller150. For example, the host device20may update at least one of parameters, which constitute the individual mode, such as the number of namespaces, a capacity of each of the namespaces, and a logical address group allocated to each of the namespaces. When the parameters constituting the individual mode are completely updated, in operation S440, the host device20may send a request for deleting namespaces to the memory controller150.

The memory controller150may release the configuration of the individual mode in response to the request for deleting namespaces.

For example, the memory controller150may remove the first to third physical address groups PG1, PG2, and PG3and the first to third mapping tables MT1, MT2, and MT3.

For another example, the memory controller150may release the configuration of the individual mode in a state of maintaining data stored in the first to fourth nonvolatile memory chips110,120,130, and140.

For another example, the memory controller150may perform (or reserve) erasing of data stored in the first to fourth nonvolatile memory chips110,120,130, and140and may release the configuration of the individual mode.

Once the configuration of the individual mode is released, in operation S450, the memory controller150may send, to the host device20, a response providing notification that namespaces are removed.

Afterwards, through operation S310to operation S380ofFIG.8, the host device20and the memory controller150may configure new namespaces.

In an example embodiment, when namespaces are updated as described with reference toFIG.9, there may be updated at least one of the following: 1) the number of namespaces, 2) a capacity of each of the namespaces, 3) logical address groups respectively allocated to the namespaces, 4) a nonvolatile memory chip(s) allocated to each of the namespaces, 5) the number of nonvolatile memory chips allocated to each of the namespaces, 6) a physical address group of nonvolatile memory chips allocated to each of the namespaces, 7) stream IDs respectively allocated to the namespaces, and 8) the number of stream IDs respectively allocated to the namespaces.

FIG.10illustrates a first example in which namespaces are updated in response to detecting a fail “F”.

Referring toFIGS.6and10, a fail “F” may be detected in a portion of a storage space of the first nonvolatile memory chip110.

As the fail “F” is detected, a size of the first storage space SS1that the first nonvolatile memory chip110provides to the host device20through the memory controller150may decrease (compared to that ofFIG.6).

In response to the detection of the fail “F”, the host device20may reduce a capacity (or a size) of the first namespace NS1. The first namespace NS1of the reduced size may be mapped with the first nonvolatile memory chip110having the first storage space SS1of the reduced size.

For another example, the host device20may reduce a size of the second namespace NS2or the third namespace NS3. In the case where the size of the second namespace NS2is reduced, the first namespace NS1may be mapped with a nonvolatile memory chip in which the fail “F” is not detected. The first nonvolatile memory chip110where the fail “F” is detected and a nonvolatile memory chip where the fail “F” is not detected may be mapped with the second namespace NS2.

In the case where the size of the third namespace NS3is reduced, the first namespace NS1may be mapped with a nonvolatile memory chip in which the fail “F” is not detected. The third namespace NS3may be mapped with the first nonvolatile memory chip110where the fail “F” is detected.

FIG.11illustrates a second example in which namespaces are updated in response to detecting a fail “F”.

Referring toFIGS.6and11, a fail “F” may be detected in a portion of a storage space of the first nonvolatile memory chip110and in a portion of a storage space of the second nonvolatile memory chip120.

As the fail “F” is detected, a size of the first storage space SS1that the first nonvolatile memory chip110provides to the host device20through the memory controller150and a size of the second storage space SS2that the second nonvolatile memory chip120provides to the host device20through the memory controller150may decrease (compared to that ofFIG.6).

In response to the detection of the fail “F”, the host device20may reduce a capacity (or a size) of the second namespace NS2. The second namespace NS2of the reduced size may be mapped with the first nonvolatile memory chip110having the first storage space SS1of the reduced size and the second nonvolatile memory chip120having the second storage space SS2of the reduced size.

For another example, the host device20may reduce the number of namespaces. For example, the host device20may remove the first namespace NS1or may remove the third namespace NS3. The host device20and the storage device100may have one namespace corresponding to a storage space of one nonvolatile memory chip and another namespace corresponding to storage spaces of two nonvolatile memory chips.

FIG.12illustrates a third example in which namespaces are updated in response to detecting a fail “F”.

Referring toFIGS.6and12, a fail “F” may be detected in a portion of a storage space of the first nonvolatile memory chip110.

As the fail “F” is detected, a size of the first storage space SS1that the first nonvolatile memory chip110provides to the host device20through the memory controller150may decrease (compared to that ofFIG.6).

In response to the detection of the fail “F”, the host device20may remove the first namespace NS1. The host device20may update parameters of namespaces such that the reduced first storage space SS1of the first nonvolatile memory chip110is used as an OP area of at least one of the second to fourth storage spaces SS2, SS3, and SS4of the second to fourth nonvolatile memory chips120,130, and140.

For another example, in a state where the reduced first storage space SS1of the first nonvolatile memory chip110is used as an OP area, the third namespace NS3may be removed, or the size of the second namespace NS2may be reduced.

FIG.13illustrates another example in which the storage device100and the host device20configure the individual mode.

Referring toFIGS.1and13, the host device20may initiate reconfiguration of the individual mode without information from the memory controller150. For example, the host device20may update at least one of parameters, which constitute the individual mode, such as the number of namespaces, a capacity of each of the namespaces, and a logical address group allocated to each of the namespaces.

When the parameters constituting the individual mode are completely updated, in operation S510, the host device20may send a request for deleting namespaces to the memory controller150.

The memory controller150may release the configuration of the individual mode in response to the request for deleting namespaces.

For example, the memory controller150may remove the first to third physical address groups PG1, PG2, and PG3and the first to third mapping tables MT1, MT2, and MT3.

For another example, the memory controller150may release the configuration of the individual mode in a state of maintaining data stored in the first to fourth nonvolatile memory chips110,120,130, and140.

For another example, the memory controller150may perform (or reserve) erasing of data stored in the first to fourth nonvolatile memory chips110,120,130, and140and may release the configuration of the individual mode.

In response to the configuration of the individual mode being released, in operation S520, the memory controller150may send, to the host device20, a response providing notification that namespaces are removed.

Afterwards, through operation S310to operation S380ofFIG.8, the host device20and the memory controller150may configure new namespaces.

In an example embodiment, the host device20may initiate an update of namespaces based on applications associated with the namespaces or user demands such as a capacity and a service quality (e.g., a speed).

FIG.14is a block diagram illustrating a nonvolatile memory chip200according to an example embodiment. In an example embodiment, the nonvolatile memory chip200may correspond to each of the first to fourth nonvolatile memory chips110,120,130, and140ofFIG.1.

Referring toFIG.14, the nonvolatile memory chip200may include a memory cell array210, a row decoder block220, a page buffer block230, a pass/fail check block (PFC)240, a data input and output block250, a buffer block260, and a control logic block270.

The memory cell array210may include a plurality of memory blocks BLK1to BLKz. Each of the memory blocks BLK1to BLKz may include a plurality of memory cells. Each of the memory blocks BLK1to BLKz may be connected with the row decoder block220through ground selection lines GSL, word lines WL, and string selection lines SSL. Some of the word lines WL may be used as dummy word lines. Each of the memory blocks BLK1to BLKz may be connected with the page buffer block230through a plurality of bit lines BL. The plurality of memory blocks BLK1to BLKz may be connected in common with the plurality of bit lines BL.

In an example embodiment, each of the plurality of memory blocks BLK1to BLKz may be a unit of an erase operation. The memory cells belonging to each of the memory blocks BLK1to BLKz may be erased at the same time. For another example, each of the plurality of memory blocks BLK1to BLKz may be divided into a plurality of sub-blocks. Each of the plurality of sub-blocks may correspond to a unit of an erase operation.

The row decoder block220may be connected with the memory cell array210through the ground selection lines GSL, the word lines WL, and the string selection lines SSL. The row decoder block220may operate under control of the control logic block270.

The row decoder block220may decode a row address RA received from the buffer block260, and may control voltages to be applied to the string selection lines SSL, the word lines WL, and the ground selection lines GSL based on the decoded row address.

The page buffer block230may be connected with the memory cell array210through the plurality of bit lines BL. The page buffer block230may be connected with the data input and output block250through a plurality of data lines DL. The page buffer block230may operate under control of the control logic block270.

In a program operation, the page buffer block230may store data to be written in memory cells. The page buffer block230may apply voltages to the plurality of bit lines BL based on the stored data. In a read operation or in a verify read operation that is performed in the program operation or an erase operation, the page buffer block230may sense voltages of the bit lines BL, and may store a sensing result.

In the verify read operation associated with the program operation or the erase operation, the pass/fail check block240may verify the sensing result of the page buffer block230. For example, in the verify read operation associated with the program operation, the pass/fail check block240may count the number of values (e.g., the number of 0s) respectively corresponding to on-cells that are not programmed to a target threshold voltage or more.

In the verify read operation associated with the erase operation, the pass/fail check block240may count the number of values (e.g., the number of 1s) respectively corresponding to off-cells that are not erased to a target threshold voltage or less.

When a counting result is a threshold value or more, the pass/fail check block240may output a fail signal to the control logic block270. When the counting result is smaller than the threshold value, the pass/fail check block240may output a pass signal to the control logic block270. Depending on a verification result of the pass/fail check block240, a program loop of the program operation may be further performed, or an erase loop of the erase operation may be further performed.

The data input and output block250may be connected with the page buffer block230through the plurality of data lines DL. The data input and output block250may receive a column address CA from the buffer block260. The data input and output block250may output data read by the page buffer block230to the buffer block260depending on the column address CA. The data input and output block250may provide data received from the buffer block260to the page buffer block230, based on the column address CA.

Through first signal lines SIGL1, the buffer block260may receive a command CMD and an address ADDR from an external device and may exchange data “DATA” with the external device. The buffer block260may operate under control of the control logic block270. The buffer block260may provide the command CMD to the control logic block270. The buffer block260may provide the row address RA of the address ADDR to the row decoder block220and may provide the column address CA of the address ADDR to the data input and output block250. The buffer block260may exchange the data “DATA” with the data input and output block250.

The control logic block270may exchange control signals CTRL with the external device through second signal lines SIGL2. The control logic block270may allow the buffer block260to route the command CMD, the address ADDR, and the data “DATA”. The control logic block270may decode the command CMD received from the buffer block260and may control the nonvolatile memory chip200based on the decoded command.

In an example embodiment, the nonvolatile memory chip200may be manufactured in a bonding manner. The memory cell array210may be manufactured at a first wafer, and the row decoder block220, the page buffer block230, the data input and output block250, the buffer block260, and the control logic block270may be manufactured at a second wafer. The nonvolatile memory chip200may be implemented by coupling the first wafer and the second wafer such that an upper surface of the first wafer and an upper surface of the second wafer face each other.

For another example, the nonvolatile memory chip200may be manufactured in a cell over peri (COP) manner. The peripheral circuit including the row decoder block220, the page buffer block230, the data input and output block250, the buffer block260, and the control logic block270may be implemented on a substrate. The memory cell array210may be implemented over the peripheral circuit. The peripheral circuit and the memory cell array210may be connected by using through vias.

In an example embodiment, a memory block may correspond to a unit by which a size of a storage space of the nonvolatile memory chip200is reduced when a fail occurs. When a fail occurs, a memory block, which includes a storage space where the fail occurs, from among the memory blocks BLK1to BLKz of the nonvolatile memory chip200, may be ruled out of a storage space of the nonvolatile memory chip200.

FIG.15illustrates an electronic device300according to an example embodiment. In an example embodiment, the electronic device300may be a server.

Referring toFIG.15, the electronic device300may include a power supply310and a body320.

The power supply310may generate a power PWR from an external power and may supply the generated power PWR to the body320. The power PWR may be provided such that two or more different voltages are supplied.

The body320may receive the power PWR from the power supply310and may operate based on the power PWR.

The body320may include a baseboard330, a first solid state drive (SSD) backplane340, a second SSD backplane350, a third SSD backplane360, a cooling control board370, coolers380, and sensors (SENS)390.

The baseboard330may include a first central processing unit (CPU)331, a second CPU332, first memories333and second memories334connected with the first CPU331, third memories335and fourth memories336connected with the second CPU332, and a baseboard management board (BMC)337. The baseboard330may supply the power PWR received from the power supply310to the first CPU331, the second CPU332, the first memories333, the second memories334, the third memories335, and the fourth memories336.

The first CPU331may use the first memories333and the second memories334as working memories. The second CPU332may use the third memories335and the fourth memories336as working memories. The first CPU331and the second CPU332may execute an operating system and various applications. The first CPU331and the second CPU332may control components of the body320. For example, the first CPU331and the second CPU332may control the components of the body320based on PCIe.

The first CPU331and the second CPU332may access the first SSD backplane340, the second SSD backplane350, and the third SSD backplane360. For example, the first CPU331and the second CPU332may access the first SSD backplane340, the second SSD backplane350, and the third SSD backplane360based on NVMe.

The first memories333, the second memories334, the third memories335, and the fourth memories336may include DIMM memories that are inserted into DIMM slots.

The BMC337may be a separate system that is independent of the operating system of the first CPU331and the second CPU332. The BMC337may collect information from the components of the electronic device300and may access the components. The BMC337may be based on a separate communication interface that is independent of a communication interface (e.g., PCIe) of the first CPU331and the second CPU332. For example, the BMC337may be based on an intelligent platform management interface (IPMI). The communication interface of the BMC337may communicate with the communication interface of the first CPU331and the second CPU332.

The first SSD backplane340may receive the power PWR from the power supply310and may exchange signals with the baseboard330. The first SSD backplane340may exchange signals with the first CPU331, the second CPU332, or the BMC337of the baseboard330. A plurality of SSDs may be mounted in the first SSD backplane340. Thus, the first SSD backplane340may include a plurality of SSDs.

The first CPU331and the second CPU332of the baseboard330may access (e.g., may perform write, read, and erase operations on) the SSDs of the first SSD backplane340. The BMC337of the baseboard330may monitor the first SSD backplane340and may access and control the first SSD backplane340.

Structures and operations of the second SSD backplane350and the third SSD backplane360may be the same as the structure and the operation of the first SSD backplane340. Thus, additional description will be omitted to avoid redundancy.

The cooling control board370may receive the power PWR from the power supply310. The cooling control board370may control the coolers380under control of the baseboard330. For example, the cooling control board370may control the coolers380under control of the first CPU331, the second CPU332, or the BMC337of the baseboard330. The cooling control board370may control whether to enable and disable operations of the coolers380and a cooling level (or an RPM).

The coolers380may receive the power PWR from the power supply310. The coolers380may decrease a temperature of the electronic device300by performing cooling under control of the cooling control board370. The coolers380may include fans, etc. The coolers380may be disposed in one or multiple locations. For example, the coolers380may be distributed and disposed at two or more locations. A part of the coolers380may be attached on a chassis of the electronic device300such that external air is introduced to the inside of the electronic device300. The others of the coolers380may be disposed at a specific component and may be used primarily for cooling of the specific component.

The sensors390may receive the power PWR from the power supply310. The sensors390may be disposed adjacent to the components of the electronic device300. Under control of the baseboard330, the sensors390may collect a variety of information, and may provide the collected information to the baseboard330.

For example, under control of the BMC337of the baseboard330, the sensors390may collect information and may provide the collected information to the BMC337. The sensors390may provide the collected information to the BMC337through a sensor data repository (SDR) of the IPMI. For example, different record IDs may be allocated to the sensors390. The sensors390may provide information to the BMC337, based on the different record IDs. The sensors390may include various sensors such as a temperature sensor, a humidity sensor, and a vibration sensor.

An example where a specific number of CPUs and a specific number of memories are mounted in the baseboard330is illustrated inFIG.15, but the number of CPUs and the number of memories may be varied. A specific number of SSD backplanes are illustrated inFIG.15, but the number of SSD backplanes may be varied. A specific kind of coolers are illustrated inFIG.15as much as the specific number, but the coolers may be varied in kind and number. A specific number of sensors are illustrated inFIG.15, but sensors may be varied in kind and number.

In an example embodiment, each of the plurality of SSDs included in the first to third SSD backplanes340,350, and360may include the storage device100described with reference toFIGS.1to13. The baseboard330may correspond to the host device20described with reference toFIGS.1to13. The baseboard330and the SSDs of the first to third SSD backplanes340,350, and360may configure namespaces and may dynamically update the configuration of the namespaces.

FIG.16is a diagram of a system1000to which a storage device is applied, according to an embodiment. The system1000ofFIG.16may be, e.g., a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of things (IOT) device, or may be, e.g., a PC, a laptop computer, a server, a media player, an automotive device (e.g., a navigation device), etc.

Referring toFIG.16, the system1000may include a main processor1100, memories (e.g.,1200aand1200b), storage devices (e.g.,1300aand1300b), an image capturing device1410, a user input device1420, a sensor1430, a communication device1440, a display1450, a speaker1460, a power supplying device1470, and a connecting interface1480.

The main processor1100may control all operations of the system1000, more specifically, operations of other components included in the system1000. The main processor1100may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor1100may include at least one CPU core1110and may further include a controller1120configured to control the memories1200aand1200band/or the storage devices1300aand1300b.

In an example embodiment, the main processor1100may include an accelerator1130, which is a dedicated circuit for a high-speed data operation, such as an artificial intelligence (AI) data operation. The accelerator1130may include a graphics processing unit (GPU), a neural processing unit (NPU) and/or a data processing unit (DPU), and be implemented as a chip that is physically separate from the other components of the main processor1100.

The memories1200aand1200bmay be used as main memory devices of the system1000. Each of the memories1200aand1200bmay include, e.g., a volatile memory, such as static random access memory (SRAM) and/or dynamic RAM (DRAM), or a non-volatile memory, such as a flash memory, phase-change RAM (PRAM) and/or resistive RAM (RRAM). The memories1200aand1200bmay be implemented in the same package as the main processor1100.

The storage devices1300aand1300bmay serve as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and may have larger storage capacity than the memories1200aand1200b. The storage devices1300aand1300bmay respectively include storage controllers (STRG CTRL)1310aand1310band non-volatile memories (NVM)1320aand1320bconfigured to store data via the control of the storage controllers1310aand1310b. The NVMs1320aand1320bmay include, e.g., flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, or other types of NVMs, such as PRAM and/or RRAM.

The storage devices1300aand1300bmay be physically separated from the main processor1100and included in the system1000or implemented in the same package as the main processor1100. In addition, the storage devices1300aand1300bmay have types of solid-state devices (SSDs) or memory cards and be removably combined with other components of the system1000through an interface, such as the connecting interface1480that will be described below. The storage devices1300aand1300bmay be devices to which a standard protocol, such as a universal flash storage (UFS), an embedded multi-media card (eMMC), or a non-volatile memory express (NVMe), is applied, for example.

The image capturing device1410may capture still images or moving images. The image capturing device1410may include a camera, a camcorder, and/or a webcam.

The user input device1420may receive various types of data input by a user of the system1000and may include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor1430may detect various types of physical quantities, which may be obtained from the outside of the system1000, and convert the detected physical quantities into electric signals. The sensor1430may include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device1440may transmit and receive signals between other devices outside the system1000according to various communication protocols. The communication device1440may include an antenna, a transceiver, and/or a modem.

The display1450and the speaker1460may serve as output devices configured to respectively output visual information and auditory information to the user of the system1000.

The power supplying device1470may convert power supplied from a battery (not shown) embedded in the system1000and/or an external power source, and supply the converted power to each of components of the system1000.

The connecting interface1480may provide connection between the system1000and an external device, which is connected to the system1000and capable of transmitting and receiving data to and from the system1000. The connecting interface1480may be implemented by using various interface schemes, such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), system computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), NVMe, IEEE 1394, a universal serial bus (USB) interface, a secure digital (SD) card interface, a multi-media card (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface.

In an example embodiment, each of the storage controllers1310aand1310bmay correspond to the memory controller150described with reference toFIGS.1to13. Each of the nonvolatile memories1320aand1320bmay correspond to the first to fourth nonvolatile memory chips110,120,130, and140described with reference toFIGS.1to13. The main processor1100may correspond to the host device20described with reference toFIGS.1to13. The main processor1100and the storage devices1300aand1300bmay configure namespaces and may dynamically update the namespaces.

In the above example embodiments, components according to the present disclosure may be described by using the terms “first”, “second”, “third”, etc. However, the terms “first”, “second”, “third”, etc. may be used to distinguish components from each other and do not limit the present disclosure. For example, the terms “first”, “second”, “third”, etc. do not involve an order or a numerical meaning of any form.

In the above example embodiments, components may be referenced by using blocks. The blocks may be implemented with various hardware devices, such as an integrated circuit (IC), an application specific IC (ASIC), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software. Also, the blocks may include circuits implemented with semiconductor elements in an integrated circuit, or circuits enrolled as an intellectual property (IP).

By way of summation and review, a storage device may provide a host device with information about a capacity of nonvolatile memory chips. The host device may request the storage device for a write, read, or erase operation, based on the information about the capacity of the nonvolatile memory chips. The storage device may perform the write, read, or erase operation on the nonvolatile memory chips in response to a request of the host device. The reliability of the nonvolatile memory chips may decrease as the write, read, or erase operation is repeatedly performed on the nonvolatile memory chips. The reduction in reliability of the nonvolatile memory chip may cause a fail, in which data stored in the nonvolatile memory chip is incapable of being recovered.

As described above, embodiments relate to an electronic device, and more particularly, relate to a storage device managing a storage space with improved flexibility, an operating method of the storage device, and an electronic device including the storage device. Embodiments may provide a storage device supporting a function that allows a host device to manage a storage space of the storage device more flexibly, an operating method of the storage device, and an electronic device including the storage device.

A storage device according to an example embodiment may provide information of each of nonvolatile memory chips to a host device, and may map groups provided by the host device with the nonvolatile memory chips depending on a request of the host device. The storage device may access a corresponding nonvolatile memory chip, based on an access request of the host device to a specific group. Accordingly, a storage device supporting a function that allows the host device to manage a storage space of the storage device more flexibly, an operating method of the storage device, and an electronic device including the storage device may be provided.