Integrated circuit having localized embedded SiGe and method of manufacturing

An integrated circuit (IC) with localized SiGe embedded in a substrate and a method of manufacturing the IC is provided. The method includes forming recesses in a substrate on each side of a gate structure and remote from a shallow trench isolation structure. The method further includes growing a stress material within the recesses such that the stress material is bounded on its side only by the substrate.

FIELD OF THE INVENTION

The present invention relates to integrated circuits (ICs) and methods of manufacturing the IC and, more particularly, to an IC having embedded localized SiGe bounded by a substrate and a method of manufacturing the IC.

BACKGROUND

Mechanical stresses within a semiconductor device substrate can modulate device performance. That is, stresses within a semiconductor device are known to enhance semiconductor device characteristics. Thus, to improve the characteristics of a semiconductor device, tensile and/or compressive stresses are created in the channel of the NFETs and/or PFETs.

In order to maximize the performance of NFETs and PFETs within integrated circuit (IC) chips, the stress components should be engineered and applied differently for NFETs and PFETs as the type of stress beneficial for the performance of an NFET is generally disadvantageous for the performance of the PFET. More particularly, when a device is in tension, the performance characteristics of the NFET are enhanced while the performance characteristics of the PFET are diminished.

In known processes for implementing stresses in FETs, distinct processes and/or materials are used to create such stresses. For example, as shown inFIG. 1, it is known to grow SiGe in recesses in the substrate which are in contacted and bounded by an STI structure. According to this method, the substrate between the gate structure and the isolation region (STI) is etched to form recesses. These recesses are bounded by the STI structure and more particularly the oxide material which forms the STI structure. However, in these known methods, the SiGe material does not grow uniformly within the recesses due to its faceted profile. In fact, due to the characteristics of the SiGe and remaining structure, the SiGe has a tendency to grow faster along sidewalls of the substrate, e.g., silicon, than the oxide of the STI structure.

Due to this faceted profile, a triangular-shaped trench forms along the STI structure that extends to the bottom of the silicon recess. This trench results in serious processing problems such as, for example, junction leakage problems. More specifically, the junction leakage problem results from silicide being taken down to the bottom of the silicon recess during subsequent processing steps. Also, the trench makes it more difficult to ensure desired topography when patterning with lithographic processes. Another problem is the dependence of the performance enhancement on the spacing between devices. This dependence is due to the recess RIE loading, amongst other factors.

SUMMARY

In a first aspect of the invention, a method comprises forming recesses in a substrate on each side of a gate structure and remote from a shallow trench isolation structure. The method further comprises growing a stress material within the recesses such that the stress material is bounded on its side only by the substrate.

In a another aspect of the invention, a method of forming a device comprises forming a gate structure on a substrate between shallow trench isolation structures. The method further comprises forming sacrificial spacers on the sides of the gate structure. The sacrificial spacers extend partially to the trench isolation structures. The method further comprising forming a recessed mask on sides of the sacrificial spacers which is at a height below the sacrificial spacers such that portions of the sacrificial spacers remain exposed. The method also comprises etching the sacrificial spacers and any intervening material to expose the substrate, etching the substrate to form recesses which are substantially a same width as the sacrificial spacers, and growing SiGe material within the recesses such that the SiGe material is bounded on its sides by the substrate and remote from the shallow trench isolation structures.

In a further aspect of the invention, a structure comprises an embedded localized SiGe in a substrate on sides of a gate structure and remote from shallow trench isolation structures.

DETAILED DESCRIPTION

The present invention relates to an integrated circuit (IC) with localized SiGe embedded in a substrate and a method of manufacturing the IC. In embodiments, the embedded localized SiGe is bounded by the substrate and is remote from shallow trench isolation (STI) structures. That is, the embedded SiGe is not bounded or in contact with the material (e.g., oxide) of the STI structures. As the SiGe is epitaxially grown and is selective to oxide, the method and structure of the present invention results in an embedded SiGe layer which can be uniformly grown, thereby eliminating any gaps or spaces at the junction of the bounded area, i.e., between the substrate and the SiGe. This provides many advantages over known methods and structures such as, for example, providing a uniform performance gain regardless of the transistor spacing or density. Also, by using the methods of the present invention it is possible to ensure that no unwanted material, e.g., silicide, will interfere with the performance gain, i.e., elimination of the gap will ensure that there is no junction leakage due to the silicide at a bottom of the silicon recess.

FIG. 2shows a beginning structure and respective processing steps in accordance with the invention. The beginning structure10includes a substrate12such as, for example, silicon. STI structures14are formed in the substrate12using conventional fabrication processes. For example, using conventional lithographic and etching processes, a shallow trench can be formed in the substrate12. Oxide material can be deposited in the shallow trench and then planarized to form the STI structures14. In embodiments, the STI structures14may be about 250 nm in depth; although, other dimensions are contemplated by the invention.

As further seen inFIG. 2, a beginning gate structure15is formed using conventional gate formation processes. These conventional gate formation processes include, for example, deposition, lithographic and etching processes known to those of skill in the art. More specifically, in embodiments, the gate structure15includes a gate oxide layer16, a gate polysilicon body18and a nitride capping layer20.

In an illustrative embodiment, the gate structure15is about 40 {acute over (Å)} and about 1000 {acute over (Å)} high; although other dimensions are also contemplated by the present invention. For example, those of skill in the art will recognize that narrower gate structures can be implemented with the present invention which will provide higher device performance. As such, the present invention should not be limited to the exemplary dimensions described herein. In further embodiments, the gate structure15may be about 50 nm to 100 nm from the STI structures14, depending on the density of the device.

As seen inFIG. 3, an oxide liner22is deposited over the structure ofFIG. 2. Also, a nitride spacer24is deposited on the oxide liner22, adjacent to the gate structure15. As a result of a wet or dry etching process, those portions of the oxide liner22that are not protected by the nitride spacer24are removed from a surface of the structure. This results in the formation of the structure ofFIG. 3.

As seen inFIG. 4, a conformal oxide deposition process is used to provide the structure ofFIG. 4. More specifically, the conformal oxide deposition process results in an oxide layer26deposited over the structure.

As seen inFIG. 5, sacrificial nitride spacers28are formed on the side of the gate structure. In embodiments, the nitride spacers28are formed using conventional deposition and etching processes known to those of skill in the art. In embodiments, the thickness of the nitride spacers28is comparable to a minimum gate dimension, e.g., one half to one times the dimension of the gate structure. In embodiments, the nitride spacers28can be any thickness, but preferably should not bound, abut or extend beyond the STI structures14. In this way, in subsequent processing steps, recesses formed in the substrate12will not be bounded or abut against the STI structures14, thus allowing, e.g., SiGe material to uniformly grow, thereby eliminating and gaps or spaces at a bounded junction.

FIG. 6shows a recessed resist or mask30adjacent to the nitride spacers28. In embodiments, the resist30is a spin on resist or a planarizing polymer material. In embodiments, after the resist30is deposited on the structure, a uniform dry etch, for example, can be performed to recess the resist below a surface of the nitride spacers28. This will expose the nitride spacers28so that a subsequent etching process can remove the nitride spacers28and form recesses in the substrate12.

As seen inFIG. 7, the nitride spacers28are removed by a conventional etching process. As seen inFIG. 8, the exposed oxide liner26is removed by an additional conventional etching process. This etching process exposes the underlying substrate10.

As seen inFIG. 9, recesses32are formed in the substrate10, using a conventional etching process. The width dimension of the recesses32correspond to the width dimension of the nitride spacers28. As such, the recesses32are entirely bounded within the substrate12, remote from the STI structures14. Thus, any material deposited within the recesses32will not contact the STI structures14provided many advantages as discussed herein. The depth of the recesses32can range from about 50 nm to 100 nm and, in embodiments, is about 80 nm. Also, advantageously, the processes of the present invention ensure that the recesses32are of uniform width and depth, all of which are based on engineering designs depending on a particular implementation.

As seen inFIG. 10, the resist is stripped using a conventional stripping process known to those of skill in the art. For example, the resist can be stripped using a standard O2dry etch or a sulfuric peroxide wet etch.

As seen inFIG. 11, a stress material such as, for example, SiGe material34, is epitaxially grown in the recesses32. As the SiGe is bounded only by the substrate10, it is possible to uniformly grow the SiGe material34without formation of any gaps or spaces between the SiGe material34and the substrate12. This, in turn, results in a more uniform performance gain across devices, regardless of device density and/or spacing. Also, by not having any gaps or empty spaces at the junction, no undesirable materials, e.g., silicide, will be deposited in unwanted areas which may interfere with the performance gain of the device. That is, by not having silicide formed in empty spaces, the present invention eliminates junction leakage due to the silicide at a bottom of the silicon recesses.

InFIG. 12, the oxide layer is stripped using conventional etching processes. This results in a final structure according to the invention. In further processing steps, the source and drain can be implanted with the appropriate dopants such as, for example, arsenic and boron. Extension and halo implantation can also be performed in a conventional manner. For example, an ion implantation is performed in the source/drain regions to form extensions on either side of the gates. Any ion implantation process appropriate for source/drain implantation for the device being fabricated may be used, as is well known in the art. For example, if the doped region is a P-region, this may be implanted, for example, with Boron (B). If the doped region is an N-region, this may be implanted, for example, with Arsenic (As), Antimony (Sb), or Phosphorous (P).