Output buffer circuit with de-emphasis function

Disclosed is an output buffer circuit including main-data output buffers; a de-emphasis output buffer; and a selector that performs switching control in such a way that, based on a control signal indicating whether de-emphasis is to be enabled or disabled, main data is supplied to the de-emphasis output buffer to make the buffer operate as a main-data output buffer when the control signal indicates that de-emphasis is to be disabled, while emphasis data obtained on delaying the main data by the delay circuit is supplied to the de-emphasis output buffer to make the buffer operate as a de-emphasis output buffer when the control signal indicates that de-emphasis is to be enabled.

FIELD OF THE INVENTION

The present invention relates to a semiconductor circuit, and more particularly to an output buffer circuit with the de-emphasis function.

BACKGROUND OF THE INVENTION

Patent Documents 1 and 2 disclose an output buffer equipped with de-emphasis function in which the amplitude of an output signal emphasized when the logic of the output signal is changed, is attenuated when the logic of the output signal following the change remains unchanged. Patent document 1 discloses a configuration including a main buffer, a delay circuit, an emphasis driver, and a subtracter composed of a differential circuit. Patent Document 2 discloses an emphasis circuit constituted by a CMOS inverter, with a configuration including a tri-state buffer that performs switching control to determine whether to activate the emphasis function based on the control signal.

FIG. 8is a diagram showing the configuration of an output buffer circuit equipped with a conventional de-emphasis function. For the sake of description, the following describes an exemplary configuration in which the ENABLE signal is introduced into the configuration (differential circuit), described in Patent Document 1, as the control signal for activating the emphasis function. Patent Documents 1 and 2 disclose an output buffer having the pre-emphasis function, which emphasizes the amplitude at the transition bit that is the first bit immediately after the logic of the signal is changed, and the de-emphasis function which decreases the emphasized amplitude when the logic of the bits following the transition bit is not changed. The following describes an output buffer with the de-emphasis function that outputs the amplitude defined by the power supply potential VDD in the transition bit and decreases the amplitude when the logic of the bit following the transition bit is not changed.

Referring toFIG. 8, the output buffer circuit comprises a pair of differential input terminals (INP/INN) that differentially receive a data signal; a main-data pre-buffer53that receives the differential signal input at the differential input terminals (INP/INN); a main-data main buffer51that receives a differential output57from the main-data pre-buffer53; a delay circuit55that receives the differential signal input at the differential input terminals (INP/INN), delays the signal, and differentially outputs the delayed signal; a de-emphasis pre-buffer54that differentially receives an output56from the delay circuit55; and a de-emphasis main buffer52that differentially receives an output58from the de-emphasis pre-buffer54. The non-inverting output from the main-data main buffer51and the inverting output (indicated by a circle) from the de-emphasis main buffer52are connected in common to a non-inverting output terminal OUTP. The inverting output from the main-data main buffer51and the non-inverting output from the de-emphasis main buffer52are connected in common to an inverting output terminal OUTN. The de-emphasis pre-buffer54and the de-emphasis main buffer52become active and operable when they receive the control signal ENABLE that is active, and becomes inactive when the control signal ENABLE is inactive.

The main-data main buffer51and the de-emphasis main buffer52emphasize the amplitude of a signal for output when the signal to be output (OUTP/OUTN) undergoes the change of the logic.

When de-emphasis is disabled, the control signal ENABLE deactivates the de-emphasis main buffer52and the de-emphasis pre-buffer54. In this case, the main-data main buffer51has a driving-capability of driving a transmission line alone (balanced transmission line connected to OUTP and OUTN).

The amplitude of the transition bit, which is the first bit signal immediately after the logic of the signal output from the main buffer50(OUTP/OUTN) is changed, is fixed regardless of whether de-emphasis is enabled or disabled. The waveform is emphasized by attenuating the amplitude of non-transition bits that are the signals following the transition bit. For example, when the output signal level VOH of the transition bit, generated immediately after the signal level is changed from low to high, is the power supply potential VDD and the following bit (non-transition bit) is high, the amplitude VOH of this signal is set lower than VDD. When the output signal level VOL of the transition bit, generated immediately after the signal level is changed from high to low, is the GND level and the following bit (non-transition bit) is low, the amplitude VOL of this signal is raised higher than GND.

FIG. 9is a diagram showing an example of the configuration of the main-data main buffer51and the de-emphasis main buffer52shown inFIG. 8. InFIG. 9, the buffer51inFIG. 8corresponds to a circuit60and the buffer52inFIG. 8corresponds to circuit61.

Referring toFIG. 9, the configuration comprises N-channel MOS transistors62and63which have sources connected in common to a constant current source I3(current value is variably controlled) and which have gates for receiving the non-inverting signal (Main data positive) and the inverting signal (Main data negative) of the main data57inFIG. 8respectively; and N-channel MOS transistors64and65which have sources connected in common to a constant current source I4(current value is variably controlled) and which have gates for receiving the non-inverting signal (Emphasis data positive) and the inverting signal (Emphasis data negative) of the emphasis data58inFIG. 8respectively. The drain of the transistor62and the drain of the transistor65are connected in common to the inverting terminal OUTN and, via a resistor R1, connected to the power supply VDD, and the drain of the transistor63and the drain of the transistor64are connected in common to the non-inverting terminal OUTP and, via a resistor R2, connected to the power supply VDD. The constant current source I4and a switch SW are connected in series between the coupled source of the N-channel MOS transistors64and65and the ground and, when emphasis is disabled, the control signal ENABLE is inactive and the switch SW is off. The following describes the operation when emphasis is enabled (control signal ENABLE is active and switch SW is on). In the description below, a high level is a logic value 1, and a low level is a logic value 0.

When the non-inverting signal and the inverting signal of the main data57are 1 and 0 and the non-inverting signal and the inverting signal of the emphasis data58are 0 and 1 (non-inverting signal of main data57is the transition bit that changes from 0 to 1), the transistors62and65whose drains are connected in common are turned on, the transistors63and64are turned off, and the current corresponding to the sum of the currents of the current sources I3and I4flows through the resistor R1. OUTN=VDD−(I3+I4)×R1and OUTP=VDD and the amplitude of the output signal is OUTP−OUTN=(I3+I4)×R1.

When the non-inverting signal and the inverting signal of the main data57are 1 and 0 and the non-inverting signal and the inverting signal of the emphasis data58are 1 and 0, the transistors62and64are turned on, the transistors63and65are turned off, and the currents corresponding to I3and I4flows through the resistors R1and R2. Because the voltage difference between OUTP and OUTN is calculated from OUTN=VDD−R1×I3and OUTP=VDD−R2×I4, the amplitude of the output signal is OUTP−OUTN=R1×I3−R2×I4. When R1=R2=R, OUTP−OUTN=R×(I3−I4) and the circuit inFIG. 9becomes a subtraction circuit. The amplitude of OUTP−OUTN becomes smaller than that of the transition bit ((I3+I4)×R1), indicating that de-emphasis is performed.

When the non-inverting signal and the inverting signal of the main data57are 0 and 1 and the non-inverting signal and the inverting signal of the emphasis data58are 1 and 0 (non-inverting signal of main data57is the transition bit that changes from 1 to 0), the transistors63and64are turned on, the transistors62and65are turned off, and the current corresponding to the sum of the currents of I3and I4flows through the resistor R2. OUTP=VDD−(I3+I4)×R2and OUTN=VDD and the amplitude of the output signal is OUTP−OUTN−(I3+I4)×R2. When the non-inverting signal and the inverting signal of the main data57are 0 and 1 and the non-inverting signal and the inverting signal of the emphasis data58are 0 and 1, the transistors63and65are turned on, the transistors62and64are turned off, and the currents corresponding to I4and I3flow through the resistors R1and R2. Because the voltage difference between OUTP and OUTN is calculated from OUTN=VDD−R1×I4and OUTP=VDD−R2×I3, the amplitude of the output signal is OUTP−OUTN=R1×I4−R2×I3. When R1=R2=R, OUTP−OUTN=R×(I4−I3) and the circuit inFIG. 9becomes a subtraction circuit. The amplitude of OUTP−OUTN becomes smaller than that of the transition bit, indicating that de-emphasis is performed.

When emphasis is disabled, the differential circuit61is inactive and only the differential circuit60is active.

The transistors62and63of the differential circuit60have respective circuit sizes that can drive the transmission line only by the differential circuit60when de-emphasis is disabled, and the circuit size of the circuit61is determined by the drive current determined by the de-emphasis level.

When de-emphasis is enabled (control signal ENABLE is active), the current of the constant current source I3of the differential circuit60and current of the constant current source I4of the differential circuit61are the current values having the relation of a ratio determined by the de-emphasis level. When de-emphasis is disabled, the current for driving the transmission line flows only through the constant current source I3but not through the constant current source I4.

If the circuit is configured in such a way that the amplitude of the transition bit is equal regardless of whether de-emphasis is enabled or disabled, the current is controlled so that the current value I of the sum of the constant current source I3and the constant current source I4when de-emphasis is enabled becomes equal to the current value I of the constant current source I3when de-emphasis is disabled. For example, when de-emphasis is disabled (circuit61is inactive), the current value is variably controlled so that the constant current source I3of the circuit60becomes equal to the sum value I of the constant current source I3and the constant current source I4when de-emphasis is enabled.

Let A be driving power (driving current, circuit size) required to drive transmission line,

B be driving power of circuit60,

C be driving power of circuit61, and

D be the emphasis level ([dB]) required when emphasis is enabled, we have the following equations (1) and (2):
A=B  (1)
D=20*log [(B−C)/(B+C)] (B>C)  (2)

Let's substitute the variables in the equations (1) and (2) with actual numeric values.

If A=120 and D=−3.5[dB], B and C are determined as B=120 and C=24 from the equations (1) and (2). The ratio of driving powers B:C between the circuits60and61becomes 5:1.

If A=120 and D=−6[dB], B and C are determined as B=120 and C=40 from the equations (1) and (2). The ratio of driving powers B:C between the circuits60and61becomes 3:1.

As described above, if the de-emphasis level is −3.5[dB] and [dB], the ratios of driving powers between the circuits60and61become 5:1 and 3:1, respectively. That is, as the de-emphasis level becomes higher, the size of the de-emphasis main buffer size becomes larger and, accordingly, the size of the pre-buffer size becomes larger.

SUMMARY OF THE DISCLOSURE

When de-emphasis is disabled, it is necessary that, with the de-emphasis main buffer set in the disable state, the main-data main buffer has the driving power (circuit size) to drive the transmission line alone. This makes the main buffer and large pre-buffer large and generates a problem that the efficiency of layout area and the power efficiency are greatly deteriorated.

In addition, as the de-emphasis level becomes larger, the de-emphasis output buffer (main buffer and pre-buffer) circuit size becomes larger.

As described above, when the de-emphasis main buffer and the main-data main buffer are designed for dedicated use, the de-emphasis main buffer is not used in the operation when de-emphasis is disabled. Therefore, the main-data main buffer is required to have the driving power (circuit size) large enough to drive the transmission line alone.

The problem is that an increase in the main buffer size and the pre-buffer size greatly reduces the efficiency of the layout area and the power.

The problems described above are solved by the present invention which is configured as follows.

A device according to one aspect of the present invention comprises a first output buffer for data that receives a data signal and outputs the data signal from an output terminal; a second output buffer whose output end is connected to the output terminal; and a selection circuit that receives a control signal indicating whether de-emphasis is enabled or disabled and performs switching control in such a way that, when the control signal indicates that de-emphasis is disabled, the data signal is supplied to an input end of the second output buffer to make the second output buffer operate as a buffer for data and when the control signal indicates that de-emphasis is enabled, emphasis data obtained on delaying the data signal, is supplied to the input end of the second output buffer to make the second output buffer operate as a buffer for de-emphasis.

In accordance with the present invention, the data signal comprises a differential signal, the first output buffer comprises a first pre-buffer, composed of a differential circuit, and a first main buffer composed of a differential circuit that receives an output from the first pre-buffer, the second output buffer comprises a second main buffer composed of a differential circuit, a non-inverting output and an inverting output of a differential output of the first main buffer and an inverting output and a non-inverting output of a differential output of the second main buffer are connected in common respectively, the selection circuit receives a differential signal obtained on inverting the data signal, and a differential signal obtained on delaying the data signal by a delay circuit and, when the control signal indicates that de-emphasis is enabled, differentially supplies the signal obtained on delaying the data signal by the delay circuit, to the input terminal of the second main buffer, and when the control signal indicates that de-emphasis is disabled, supplies the signal obtained on inverting the data signal, to the second main buffer, to make the first and second main buffers operate as an adder and to make the second output buffer operate as a main-data output buffer.

A device according to another aspect of the present invention comprises a first buffer that differentially receives a data signal and differentially outputs the data signal; and a second buffer and a third buffer, wherein a non-inverting output and an inverting output of the first buffer are connected in common to an inverting output and a non-inverting output of the second and third buffers respectively. The output buffer circuit further includes a delay circuit that delays the data signal; a first selection circuit that receives a signal obtained on inverting the data signal and an output of the delay circuit and, based on a first selection control signal, outputs one of them to the second buffer; and a second selection circuit that receives the signal obtained on inverting the data signal and the output of the delay circuit and, based on a second selection control signal, outputs one of them to the third buffer.

A device according to another aspect of the present invention comprises an inverter circuit that receives and outputs a data signal; a first inverting-type output buffer that receives the output from the inverter circuit as an input and outputs the input from an output terminal; a delay circuit that delays the data signal; a selection circuit that receives an output of the delay circuit and the output of the inverter circuit, receives a control signal indicating whether de-emphasis is to be enabled or disabled, selects and outputs the output of the inverter circuit when the control signal indicates that de-emphasis is to be disabled, and selects and outputs the output of the delay circuit when the control signal indicates that de-emphasis is to be enabled; and a second inverting-type output buffer which receives the output of the selection circuit as an input and whose output is connected in common with the output of the first inverting-type output buffer.

According to the present invention, the de-emphasis output buffer, which is one of the main-data output buffer (main buffer and pre-buffer) and the de-emphasis output buffer (main buffer and pre-buffer) constituting the output buffer with the de-emphasis (also called “pre-emphasis”) function, operates as the main-data output buffer when de-emphasis is disabled.

In accordance with the present invention, the de-emphasis output buffer can be used as the main-data output buffer when the de-emphasis is disabled to optimize the entire circuit including a pre-buffer, to reduce the number of circuit elements, and to reduce power consumption.

PREFERRED EMBODIMENTS OF THE INVENTION

The preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Referring toFIG. 1, an output buffer circuit of the present invention includes main-data output buffers (13,11), a de-emphasis output buffer (12), and a selector (14) that performs switching control in such a way that it receives a control signal (SELECT) indicating whether de-emphasis is to be enabled or disabled, supplies main data to the de-emphasis output buffer (12) to make the de-emphasis output buffer operate as a main-data output buffer when the control signal indicates that de-emphasis is to be disabled, and supplies emphasis data obtained on delaying the main data by the delay circuit (15), to the de-emphasis output buffer (12) to make the de-emphasis output buffer operate as a de-emphasis output buffer when the control signal indicates that de-emphasis is to be enabled.

Referring toFIG. 3, a circuit in another embodiment of the present invention includes a first buffer (11) that differentially receives a data signal and differentially outputs the data signal; and a second buffer and a third buffer (12and12a), wherein a non-inverting output and an inverting output of the first buffer (11) are connected in common to an inverting output and a non-inverting output of the second and third buffers (12and12a) respectively. The output buffer circuit further includes a delay circuit (15) that delays the data signal; a first selection circuit (14) that receives a signal obtained on inverting the data signal and an output of the delay circuit and, based on a first selection control signal (SELECT1), outputs one of them to the second buffer; and a second selection circuit (14a) that receives the signal obtained on inverting the data signal and the output of the delay circuit and, based on a second selection control signal (SELECT2), outputs one of them to the third buffer.

Referring toFIG. 4, a circuit in still another embodiment of the present invention includes an inverter circuit (23) that receives and outputs a data signal; a first inverting-type output buffer (21) that receives the output from the inverter circuit as an input and outputs the input from an output terminal; a delay circuit (25) that delays the data signal; a selection circuit (24) that receives an output of the delay circuit and the output of the inverter circuit, receives a control signal (SELECT) indicating whether de-emphasis is to be enabled or disabled, selects and outputs the output of the inverter circuit when the control signal indicates that de-emphasis is to be disabled, and selects and outputs the output of the delay circuit when the control signal (SELECT) indicates that de-emphasis is to be enabled; and a second inverting-type output buffer (22) which receives the output of the selection circuit (24) as an input and whose output is connected in common with the output of the first inverting-type output buffer (21). The following describes the embodiments more in detail.

FIG. 1is a diagram showing the configuration of one embodiment of the present invention. Referring toFIG. 1, an output buffer circuit according to the present embodiment comprises a pair of differential input terminals (INP/INN) that differentially receive a data signal; a main data pre-buffer13that differentially receives a data signal19input at the differential input terminals (INP/INN); a main-data main buffer11that differentially receives a differential output17of the main data pre-buffer13; a delay circuit15that differentially receives the data signal19input at the differential input terminals (INP/INN), delays the signal, and outputs the delayed signal; a selection circuit14that receives a differential output16from the delay circuit15and an inverting signal19a(differential signal generated by exchanging non-inverting signal and inverting signal) of the differential data signal19input at the differential input terminals (INP/INN) and outputs one of the differential signals based on the control signal SELECT; and a main buffer (referred to as de-emphasis main buffer)12that differentially receives an output signal18of the selection circuit14.

The non-inverting output of the main-data main buffer11and the inverting output (indicated by a circle) of the de-emphasis main buffer12are connected in common to a non-inverting terminal OUTP, and the inverting output (indicated by a circle) of the main-data main buffer11and the non-inverting output of the de-emphasis main buffer12are connected in common to an inverting terminal OUTN. The main-data main buffer11and the de-emphasis main buffer12work together to increase the amplitude when the logic of the signal to be output (OUTP/OUTN) is changed and outputs the emphasized signal.

The sum of the driving power of the main-data main buffer11and that of the de-emphasis main buffer12is a driving power required to drive the transmission line. The driving power (circuit size) of the main-data main buffer11and that of the de-emphasis main buffer12are determined by the ratio of the required de-emphasis level.

The amplitude of the transition bit, which is the first bit signal immediately after the logic of the signal output at a pair of differential output terminals (OUTP/OUTN) from the main buffers is changed, is the same, regardless of whether the de-emphasis is enabled or disabled.

The amplitude of non-transition bit, which is the signal after the transition bit and has the same logic as that of the transition bit, is attenuated.

When the control signal SELECT indicates that de-emphasis is to be enabled, the selection circuit14selects the signal16from the delay circuit15.

When the control signal SELECT indicates that de-emphasis is to be disabled, the selection circuit14selects the inverting signal19aof the received differential signal (INP/INN)19. The signal from the non-inverting input terminal INP and the signal from the inverting input terminal INN are in a cross coupled configuration supplied to the inverting input terminal and the non-inverting input terminal of the selection circuit14, respectively. The output of the selection circuit14is supplied to the de-emphasis main buffer12.

When de-emphasis is enabled, a circuit10performs subtraction between the differential signal17, which is input at the differential input terminals (INP/INN) and output from the pre-buffer13, and the differential signal16, which is input at the differential input terminals (INP/INN) and delayed by the delay circuit15, and outputs a signal whose amplitude is emphasized when the logic of the signal is changed.

On the other hand, when de-emphasis is disabled, the main buffer circuit10performs subtraction between the differential data signal19, which is input at the differential input terminals (INP/INN), and the inverting signal19aof the differential data signal19, that is, adds up respectively the inverting signal and non-inverting signal of the differential data signals19. That is, the main buffer circuit10does not output attenuated signals but always outputs a signal which is of the same amplitude between a-transition bit and a non-transition bit.

When de-emphasis is disabled in the present embodiment, the de-emphasis output main buffer12works as a main-data output buffer.

FIG. 2is a diagram showing one embodiment of the configuration of the circuit10inFIG. 1, and the numeral36inFIG. 2corresponds to the circuit10inFIG. 1. When the circuit is used as a differential output buffer, the main-data main buffer11and the de-emphasis main buffer12comprise a circuit30and a circuit31, respectively.

Referring toFIG. 2, the configuration comprises N-channel MOS transistors32and33having sources connected in common to a constant current source I1and having gates supplied with the non-inverting signal (Main data positive) and the inverting signal (Main data negative) of the main data17, respectively; and N-channel MOS transistors34and35having sources connected in common to a constant current source I2and having gates supplied with the non-inverting signal and the inverting signal of the output18of the selection circuit14, respectively. The drain of the transistor32and the drain of the transistor35are connected in common to the inverting terminal OUTN and, via a resistor R1, connected to the power supply VDD, and the drain of the transistor33and the drain of the transistor34are connected in common to the non-inverting terminal OUTP and, via a resistor R2, connected to the power supply VDD.

Referring toFIG. 1andFIG. 2, the following describes the operation when de-emphasis is enabled. When de-emphasis is enabled, a circuit36performs subtraction between two signals, made up of the differential signal17which is supplied to the differential input terminals (INP/INN) and output from the pre-buffer13inFIG. 1and the differential signal18which is supplied to the differential input terminals (INP/INN) and delayed by the delay circuit15and outputs a signal whose amplitude is emphasized when the logic of the signal is changed. In the description below, the high level is represented by the logic value of 1, and the low level is represented by logic value of 0.

When the non-inverting signal and the inverting signal of the main data17is 1 and 0 and the non-inverting signal and the inverting signal of the output18of the selection circuit14(output16of delay circuit15) are 0 and 1 (non-inverting signal of main data17is the transition bit that changes from 0 to 1), the transistors32and35whose drains are connected in common are turned on, the transistors33and34are turned off, and the current corresponding to the sum of the currents of the current sources I1and I2flows through the resistor R1. OUTN=VDD−(I1+I2)×R1and OUTP=VDD and the amplitude (potential difference between OUTP and OUTN) is OUTP−OUTN=(I1+I2)×R1.

When the non-inverting signal and the inverting signal of the main data17are 1 and 0 and the non-inverting signal and the inverting signal of the output18of the selection circuit14(output16of delay circuit15) are 1 and 0, the transistors32and34are turned on, the transistors33and35are turned off, and the current corresponding to the current sources I1and I2flows through the resistors R1and R2. Because OUTN=VDD−R1×I1and OUTP=VDD−R2×I2, the amplitude is OUTP−OUTN=R1×I1−R2×I2.

When R1=R2=R, OUTP−OUTN=R×(I1−I2). The amplitude of OUTP−OUTN becomes smaller than that of the transition bit, indicating that de-emphasis is performed.

When the non-inverting signal and the inverting signal of the main data17is 0 and 1 and the non-inverting signal and the inverting signal of the output18of the selection circuit14(output16of delay circuit15) are 1 and 0 (non-inverting signal of main data17is the transition bit that changes from 1 to 0), the transistors33and34are turned on, the transistors32and35are turned off, and the current corresponding to the sum of the currents of the current sources I1and I2flows through the resistor R2. OUTP=VDD−(I1+I2)×R2and OUTN=VDD and, therefore, the amplitude (potential difference between OUTP and OUTN) is OUTP−OUTN=−(I1+I2)×R2.

When the non-inverting signal and the inverting signal of the main data17are 0 and 1 and the non-inverting signal and the inverting signal of the output18of the selection circuit14(output16of delay circuit15) are 0 and 1, the transistors33and35are turned on, the transistors32and34are turned off, and the current corresponding to the current sources I2and I1flows through the resistors R1and R2. Because the voltage difference between OUTP and OUTN is calculated from OUTN=VDD−R1×I2and OUTP=VDD−R2×I1, the amplitude is OUTP−OUTN=R1×I2−R2×I1. When R1=R2=R, OUTP−OUTN=R×(I2−I1). The amplitude of OUTP−OUTN becomes smaller than that of the transition bit, indicating that de-emphasis is performed.

Next, with reference toFIG. 1andFIG. 2, the following describes the operation when de-emphasis is not selected (SELECT selects inverting signal19a).

When the non-inverting signal and the inverting signal of the main data17are 1 and 0 respectively, the non-inverting signal and the inverting signal of the output18of the selection circuit14(inverting signal19aof differential data signal19) are 0 and 1 respectively, the transistors32and35with drains thereof connected in common are turned on, the transistors33and34are turned off, and the current corresponding to the sum of the currents I1and I2flows through the resistor R1.

When the non-inverting signal and the inverting signal of the main data17are 0 and 1, respectively, and the non-inverting signal and the inverting signal of the output18of the selection circuit14(inverting signal19aof differential data signal19) are 1 and 0 respectively, the transistors33and34are turned on, the transistors32and35are turned off, and the current corresponding to the sum of the currents I1and I2flows through the resistor R2. OUTP=VDD−(I1+I2)×R2and OUTP=VDD and, therefore, the amplitude becomes OUTP−OUTN=(I1+I2)×R2.

For a non-transition bit whose output signal value does not change, the amplitude also remains emphasized.

The transistor size ratio between the N-channel MOS transistors32and33and the N-channel MOS transistors34and35and the current ratio between the current sources I1and I2are determined by the required emphasis level, and the sum of the transistor sizes and the sum of the currents for driving are determined by the driving power required for driving the transmission line when de-emphasis is disabled.

The driving current of each main buffer determined as described above is fixed regardless of whether de-emphasis is enabled or disabled. However, for an output buffer with a configuration in which the output amplitude is variable regardless of whether emphasis is enabled or disabled, the current varies according to the controlled amplitude but the ratio between I1and I2is fixed.

The following shows an example of actual ratio calculation.

Let A be the sum of driving powers (driving current, circuit size) required to drive transmission line when de-emphasis is disabled,

B be driving power of circuit30,

C be driving power of circuit31, and

D be the emphasis level [dB] required when emphasis is enabled, we have the following equations (3) and (4):
A=B+C(3)
D=20*log [(B−C)/(B+C)] (B>C)  (4)

The present embodiment comprises the main-data main buffer11and the de-emphasis main buffer12that satisfy the equations described above.

Let's substitute the variables with actual numeric values to find the size ratio between the main-data main buffer11and the de-emphasis main buffer12.

If A=120 and D=−3.5[dB], B=100 and C=20 from the equations (3) and (4). The size ratio between the main-data main buffer11and the de-emphasis main buffer12becomes 5:1.

If A=120 and D=−6[dB], B=90 and C=30. The size ratio between the main-data main buffer11and the de-emphasis main buffer12becomes 3:1.

As described above, the circuit size of the whole main buffer is determined by the driving power required for driving the transmission line. The ratio between the sizes of the pre-buffers (numeral13inFIG. 1and an output buffer in selection circuit14not shown), which drive the main-data main buffer11and the de-emphasis main buffer12designed based on the ratio determined by the required de-emphasis level, is also almost equal to the ratio between the main buffers11and12.

FIG. 6andFIG. 7are waveform diagrams schematically showing the relation between the logic of the signals supplied to the main buffer11and the main buffer12and the logic and amplitude of the signals output from those buffers (for simplicity, only the non-inverting signals are shown).

FIG. 6shows the waveforms when de-emphasis is enabled. The signal D1is the signal supplied to the main buffer11, the signal D2is a signal generated by delaying the signal D1by the delay circuit15for the delay time (‘delay’ shown inFIG. 6) and then supplied to the main buffer12, and the signal D3is the output of the circuit10. As shown inFIG. 6, the circuit10performs subtraction between the signal D1and the signal D2and outputs the output signal whose amplitude is emphasized when the signal logic is changed as shown by D3.

On the other hand,FIG. 7shows the waveforms when de-emphasis is disabled. The signal D1is the signal supplied to the main buffer11, the signal D4is the inverting signal of D1, selected by the selection circuit14, and is supplied to the main buffer12, and the signal D5is the output of the circuit10. The circuit10performs subtraction between the signal D1and the signal D4. As shown by the signal D5, the resulting signal has an output signal waveform neither emphasized nor de-emphasized (the amplitude is neither emphasized when the logic of the signal is changed nor de-emphasized in the bit following the transition bit) with the amplitude equal to that of the transition bit when de-emphasis is enabled.

Although one de-emphasis level is set in the description above, the present invention is applicable also to an output buffer circuit for which two or more de-emphasis levels are set.

Next, another embodiment of the present invention will be described.FIG. 3is a diagram showing the configuration of a second embodiment of the present invention. This circuit is an output buffer circuit for which three types of de-emphasis level can be set. Like a selection circuit14, a selection circuit14ais a circuit that selects one of the following two signals based on a control signal SELECT2: a signal delayed by a delay circuit15and the inverting signal of original differential data signals19.

Like a first de-emphasis main buffer12, a second de-emphasis main buffer12ais connected in such a way that subtraction is performed between a main-data main buffer11and the second de-emphasis main buffer12a.

When the selection signals SELECT1and SELECT2have the logic value of 1 and the signals selected by the selection circuit14and selection circuit14aare the output of the delay circuit15, three types of emphasis amount can be set by the two-bit binary code. When the selection signals SELECT1and SELECT2both have the logic value of 0, the selection circuit14and the selection circuit14aselect the inverting signal of the data signal. In this case, the main buffer12and the main buffer12awork with the main buffer11as the main-data main buffer.

When the selection signals SELECT1and SELECT2have the logic value of 1, the selection circuit14and the selection circuit14aselect the output of the delay circuit15and the main buffer12and the main buffer12awork as de-emphasis main buffers.

When the selection signal SELECT1has the logic value of 1 and the selection signal SELECT2has the logic value of 0, the selection circuit14selects the output of the delay circuit15and the selection circuit14aselects the inverting signal of the data signal. The main buffer12operates as the de-emphasis main buffer, and the main buffer12athat works with the main buffer11operate as the main-data main buffer.

When the selection signal SELECT1has the logic value of 0 and the selection signal SELECT2has the logic value of 1, the selection circuit14aselects the output of the delay circuit15and the selection circuit14selects the inverting signal of the data signal. The main buffer12aoperates as the de-emphasis main buffer, and the main buffer12that works with the main buffer11operates as the main-data main buffer.

By setting the driving power (driving current, circuit size) ratio between the main buffer11, main buffer12, and main buffer12aas 9:2:1, the buffer circuit outputs the following emphasis level.
When [SELECT1, SELECT2]=[0,1]
20×log [(9+2−1)/(9+2+1)]=−1.6[dB]
When [SELECT1, SELECT2]=[1,0]
20×log [(9−2+1)/(9+2+1)]=−3.5[dB]
When [SELECT1, SELECT2]=[1,1]
20×log [(9−2−1)/(9+2+1)]=−6.0[dB]

Conversely, it is also possible to determine the driving power of the main buffer11, main buffer12, and main buffer12afrom a required de-emphasis level.

In any setting, the first de-emphasis main buffer and the second de-emphasis main buffer are always in operation and the driving current flows.

The present invention is applicable also to an output buffer operating on a single-phase signal.FIG. 4is a diagram showing the configuration of a third embodiment of the present invention. Referring toFIG. 4, the output buffer circuit comprises an inverter23that inverts a data signal received by an input terminal IN; a main-data main buffer (inverter)21that receives the output of the inverter23; a delay circuit25that delays the data signal received by the input terminal IN; a selector24that receives the output signal of the inverter23and the output of the delay circuit25and selects one of them based on the selection control signal SELECT; and a de-emphasis main buffer (inverter)22that receives the output of the selector24.

FIG. 5is a diagram showing an example of a main buffer20comprising the main-data main buffer (inverter)21and the de-emphasis main buffer (inverter)22inFIG. 4. Referring toFIG. 5, the main buffer21corresponds to a main buffer40, and the main buffer22corresponds to a main buffer41. Referring toFIG. 5, the circuit40comprises a P-channel MOS transistor42whose source is connected to the power supply VDD and an N-channel MOS transistor43whose source is connected to GND. The gates and the drains of the P-channel MOS transistor42and the N-channel MOS transistor43are connected in common to the main data terminal (Main data) and the output terminal OUT, respectively. The circuit41comprises a P-channel MOS transistor44whose source is connected to the power supply VDD and an N-channel MOS transistor45whose source is connected to GND. The gates and the drains of the P-channel MOS transistor44and the N-channel MOS transistor45are connected in common to the emphasis data terminal (Emphasis data) and the output terminal OUT, respectively.

With reference toFIG. 4andFIG. 5, the operation of the present embodiment will be described. First, the following describes the operation when de-emphasis is disabled. In the description below, the high level is represented by the logic value of 1, and the low level is represented by logic value of 0.

When de-emphasis is disabled, the selector24inFIG. 4selects the output signal of the inverter23. When the input signal has the logic value of 1, the main-data main buffer21outputs the logic value of 1 and the de-emphasis main buffer22outputs the logic value of 1. The de-emphasis main buffer22functions as the main-data main buffer, and the transmission line is driven by the driving power of the two main buffers. When the input signal has the logic value of 0, the main-data main buffer21outputs the logic value of 0 and the de-emphasis main buffer22outputs the logic value of 0. The de-emphasis main buffer22functions as the main-data main buffer, and the transmission line is driven by the driving power of the two main buffers.

As described above, when de-emphasis is disabled, “Emphasis data” of the de-emphasis main buffer41inFIG. 5receives the same signal as “Main data” of the main-data main buffer40.

Next, the following describes the operation when de-emphasis is enabled. When de-emphasis is enabled, the selector24selects the output of the delay circuit25. When the logic value of the input signal is changed from 0 to 1, the main-data main buffer21outputs the logic value of 1 and, at the same time, the de-emphasis main buffer22receives the delayed output 0 from the delay circuit25, inverts the received value, and outputs the logic value of 1. Thus, when the logic of the signal is changed (transition bit), the amplitude is emphasized to the power supply potential (VDD) side. Referring toFIG. 5, the P-channel MOS transistor42is turned on and the N-channel MOS transistor43is turned off in the main-data main buffer40, and the P-channel MOS transistor44is turned on and the N-channel MOS transistor45is turned off in the de-emphasis main buffer41. The power supply voltage VDD is output to the output terminal OUT.

When the next input signal has the logic value of 1, the main-data main buffer21outputs the logic value of 1 and, at the same time, the de-emphasis main buffer22receives the output signal with the logic value of 1 from the delay circuit25and inverts the received value to output the logic value of 0. The amplitude becomes lower than that of the power supply potential VDD. Referring toFIG. 5, the P-channel MOS transistor42is turned on and the N-channel MOS transistor43is turned off in the main-data main buffer40, and the N-channel MOS transistor45is turned on and the P-channel MOS transistor44is turned off in the de-emphasis main buffer41. The high-level voltage, defined by the on-resistance of the P-channel MOS transistor42and the N-channel MOS transistor45, is output to the output terminal OUT.

When the logic value of the input signal is changed from 1 to 0, the main-data main buffer21outputs the logic value of 0 and, at the same time, the de-emphasis main buffer22receives the delayed output 1 from the delay circuit25, inverts the received value, and outputs the logic value of 0. Thus, when the logic of the signal is changed (transition bit), the amplitude is emphasized to the GND side. Referring toFIG. 5, the P-channel MOS transistor42is turned off and the N-channel MOS transistor43is turned on in the main-data main buffer40, and the P-channel MOS transistor44is turned off and the N-channel MOS transistor45is turned on in the de-emphasis main buffer41. The GND potential is output to the output terminal OUT.

When the next input signal has the logic value of 0, the main-data main buffer21outputs the logic value of 0 and, at the same time, the de-emphasis main buffer22receives the output signal 0 from the delay circuit25, and inverts the received signal to output the logic value of 1. The amplitude becomes higher than that of GND. Referring toFIG. 5, the P-channel MOS transistor42is turned off and the N-channel MOS transistor43is turned on in the main-data main buffer40, and the N-channel MOS transistor45is turned off and the P-channel MOS transistor44is turned on in the de-emphasis main buffer41. The low-level voltage, defined by the on-resistance of the P-channel MOS transistor44and the N-channel MOS transistor43, is output to the output terminal OUT. Note that the current driving power of the transistors44and45in the de-emphasis main buffer41is set lower than the current driving power of the transistors42and43in the main-data main buffer40according to the de-emphasis amplitude attenuation characteristics.

As with a differential buffer, the circuit size of the whole main buffer is determined by the driving power required for driving the transmission line and the size ratio between the buffer40and the buffer41is determined by the required de-emphasis level.

In the present embodiment, it is possible to optimize the circuit sizes of the main-data main buffer and the de-emphasis main buffer as well as the circuit sizes of the main-data pre-buffer and the de-emphasis pre-buffer that drive the main buffers and, therefore, it is possible to reduce the layout area and to save the power consumption.

The de-emphasis setting control signal, which determines whether to enable de-emphasis, can cause the de-emphasis pre-buffer and the de-emphasis main buffer to function as the main-data pre-buffer and the main-data main buffer. Thus, when de-emphasis is disabled, the circuit where the main-data main buffer and the de-emphasis main buffers are combined can drive the transmission line. This configuration eliminates the need for a circuit size large enough for driving the transmission line only by the main-data main buffer as in the conventional output buffer, thus making the circuit size smaller.

It is of course possible to apply the differential output buffer circuit inFIG. 3to the output buffer circuit with the single-end de-emphasis function described with reference toFIG. 4andFIG. 5. To do so, the output buffer circuit inFIG. 4further comprises a second selection circuit (corresponds to14ainFIG. 3), which receives the output of the delay circuit25and the output of the inverter23and selects one of them based on a second selection control signal, and an inverter (corresponds to12ainFIG. 3) which receives the output of the second selection circuit and whose output is connected to the output terminal OUT.

Table 1 below shows the comparison of the total size of the main-data main buffer and the de-emphasis main buffer between the circuit of the present invention inFIG. 1and the circuit of the prior art inFIG. 8.

The present invention enables the same circuit configuration to be used regardless of the de-emphasis level and so prevents an increase in the circuit size. By contrast, in the circuit of the prior art, when the de-emphasis level is increased from −3.5 dB to −6.0 dB, the circuit size increases by 180/144.

The present invention is advantageously applied to the output buffer of a serialization circuit (transmission serial data is output to a transmission line) in the serialization/de-serialization (Ser/Des) interface (semiconductor device).

While the present invention has been described with reference to the embodiments above, it is to be understood that the present invention is not limited to the configuration of the embodiments above and that modifications and changes that may be made by those skilled in the art within the scope of the present invention are included.