Semiconductor Structure and Method of Forming the Same

The present disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate doped with a first ion, a deep trench structure disposed in the substrate, a barrier doped region disposed on a top of the substrate and the deep trench structure, a first epitaxial layer disposed on the barrier doped region, a body region disposed in the first epitaxial layer, a source region disposed in the body region, a gate structure disposed in the first epitaxial layer, and a collector region disposed at a bottom of the substrate. By means of the semiconductor structure, performance of an insulated gate bipolar transistor can be improved.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of priority to Chinese patent application No. 202111183105.1, filed on Oct. 11, 2021, entitled “Semiconductor Structure And Method Of Forming The Same”, the entire disclosures of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method of forming the same.

BACKGROUND

In medium and high-power switching power supply device, Insulated Gate Bipolar Transistor (IGBT) has been widely used in modern power electronics technology due to its simple control and drive circuit, high operating frequency and large capacity.

The insulated gate bipolar transistor is a compound device composed of a MOSFET and a bipolar transistor, wherein the MOSFET works as an input electrode, and a PNP transistor works as an output electrode. The insulated gate bipolar transistor can be regarded as a Darlington transistor with a MOS as an input. The insulated gate bipolar transistor combines advantages of high input impedance and simple and fast drive of MOSFET, and low conduction voltage drop and large capacity of bipolar device.

However, the performance of current insulated gate bipolar transistor needs to be improved.

SUMMARY

Embodiments of the present disclosure provide a semiconductor structure and a method of forming the same so as to improve the performance of an insulated gate bipolar transistor.

An embodiment of the present disclosure provides a semiconductor structure, including: a substrate doped with a first ion, wherein the substrate has a first surface and a second surface opposite to each other; a deep trench structure disposed in the substrate, wherein the first surface exposes a top surface of the deep trench structure, and the deep trench structure is doped with a second ion having a conductivity type opposite to a conductivity type of the first ion; a barrier doped region disposed on a top of the substrate and the deep trench structure, wherein the barrier doped region is doped with a third ion having a conductivity type same as the conductivity type of the first ion, and a doping concentration of the third ion is greater than a doping concentration of the first ion; a first epitaxial layer disposed on the barrier doped region, wherein the first epitaxial layer is doped with a fourth ion having a conductivity type same as the conductivity type of the third ion, and the doping concentration of the third ion is greater than a doping concentration of the fourth ion; a body region disposed in the first epitaxial layer, wherein the body region is disposed above the barrier doped region, and at least a part of the body region is disposed above the deep trench structure; a source region disposed in the body region, wherein the body region exposes a partial surface of the source region; a gate structure disposed in the first epitaxial layer, wherein the gate structure is disposed above the barrier doped region, the gate structure is also disposed above the substrate adjacent to the deep trench structure, and the gate structure is in contact with the body region and the exposed partial surface of the source region; and a collector region disposed at a bottom of the substrate, wherein the second surface exposes a surface of the collector region, and the collector region is spaced from a bottom of the deep trench structure by the substrate.

In some embodiments, the barrier doped region has a depth ranging from 0.1 micron to 10 microns in a direction perpendicular to the first surface.

In some embodiments, the first ion, the third ion and the fourth ion are N-type and the second ion is P-type.

In some embodiments, the third ion is phosphorus ion, and the doping concentration of the third ion doped in the barrier doped region ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.

In some embodiments, the collector region is doped with a fifth ion, the fifth ion is P-type and a doping concentration of the fifth ion is greater than a doping concentration of the second ion.

In some embodiments, the doping concentration of the fourth ion is greater than the doping concentration of the first ion.

In some embodiments, the doping concentration of the fourth ion doped in the first epitaxial layer ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.

In some embodiments, the doping concentration of the first ion doped in the substrate ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.

In some embodiments, the body region is doped with a P-type ion and the source region is doped with a N-type ion.

In some embodiments, the gate structure includes a gate electrode and a gate dielectric layer disposed between the gate electrode and the first epitaxial layer, and the gate dielectric layer is also disposed between the gate electrode and surfaces of the body region and the source region.

In some embodiments, a surface of the first epitaxial layer exposes surfaces of the gate structure, the body region and the source region, and the semiconductor structure further includes: an interlayer dielectric layer disposed on the surface of the first epitaxial layer and exposed surfaces of the gate structure, the body region and the source region, a first conductive structure disposed in the interlayer dielectric layer and coupled to the gate structure, and a second conductive structure disposed in the interlayer dielectric layer and coupled to the body region and the source region.

In some embodiments, the semiconductor structure further includes: a third conductive structure electrically coupled to the collector region.

Another embodiment of the present disclosure provides a method of forming a semiconductor structure, including: providing a substrate doped with a first ion, wherein the substrate has a first surface and a second surface opposite to each other; forming a deep trench structure in the substrate, wherein the first surface exposes a top surface of the deep trench structure, and the deep trench structure is doped with a second ion having a conductivity type opposite to a conductivity type of the first ion; forming a barrier doped region on a top of the substrate and the deep trench structure, wherein the barrier doped region is doped with a third ion having a conductivity type same as the conductivity type of the first ion, and a doping concentration of the third ion is greater than a doping concentration of the first ion; forming a first epitaxial layer on the barrier doped region, wherein the first epitaxial layer is doped with a fourth ion having a conductivity type same as the conductivity type of the third ion, and the doping concentration of the third ion is greater than a doping concentration of the fourth ion; forming a body region, a source region and a gate structure in the first epitaxial layer, wherein the body region is disposed above the barrier doped region, and at least part of the body region is disposed above the deep trench structure, wherein the body region exposes a partial surface of the source region, and wherein the gate structure is disposed above the barrier doped region, the gate structure is also disposed above the substrate adjacent to the deep trench structure, and the gate structure is in contact with the body region and the exposed partial surface of the source region; and forming a collector region at a bottom of the substrate after forming the body region, source region and gate structure, wherein the second surface exposes a surface of the collector region, and the collector region is spaced from a bottom of the deep trench structure by the substrate.

In some embodiments, the first ion, the third ion and the fourth ion are N-type and the second ion is P-type.

In some embodiments, forming the barrier doped region on the top of the substrate and the deep trench structure includes: performing ion implantation on the first surface and the top surface of the deep trench structure.

In some embodiments, process parameters for performing ion implantation on the first surface and the top surface of the deep trench structure are as follows: implanted ion includes phosphorus ion, implantation dose ranges from 1E11 atoms per square centimeter to 1E14 atoms per square centimeter, and implantation energy ranges from 1 MeV to 3 MeV.

In some embodiments, forming the deep trench structure in the substrate includes: etching the substrate to form a deep trench in the substrate, wherein the first surface exposes the deep trench; and forming the deep trench structure in the deep trench by an epitaxial growth process.

Compared with conventional technology, embodiments of the present disclosure have following beneficial effects:

In the semiconductor structure according to the embodiments of the present disclosure, in one aspect, the barrier doped region is disposed on the top of the substrate and the deep trench structure, the first epitaxial layer is disposed on the barrier doped region, the body region and the gate structure are disposed in the first epitaxial layer, the source region is disposed in the body region, and both the body region and the gate structure are disposed above than the barrier doped region (namely, the barrier doped region is spaced apart from the body region, the source region and the gate structure by a part of the first epitaxial layer), in another aspect, the doping concentration of the third ion is greater than that of the fourth ion and the first ion. Therefore, carriers (injected from the collector region) entering the body region through the deep trench structure can be blocked by the barrier doped region at a certain distance from the body region, which means that the carriers entering the body region can be reduced. In doing so, the carriers injected from the collector region can be better collected in a drift region below the body region and the gate structure (i.e., the first epitaxial layer, the barrier doped region and the substrate below the body region and the gate structure), and a concentration of the carriers of the drift region can be increased. Thus, not only an on-resistance of the drift region can be reduced to reduce an on-state voltage drop of the insulated gate bipolar transistor, but also a turn-off energy loss (EOFF) of the insulated gate bipolar transistor can be improved. Furthermore, the performance of the insulated gate bipolar transistor can be improved.

DETAILED DESCRIPTION

As described in the background, the performance of current insulated gate bipolar transistor needs to be improved.

FIG.1is a structural schematic view of an insulated gate bipolar transistor.

With reference toFIG.1, the insulated gate bipolar transistor incudes: an N-type substrate100, a P-type column structure110, an N-type epitaxial layer120, a P-type body region130, an N-type source region140, a gate structure150and a P-type collector region160. The N-type substrate100has a top surface101and a bottom surface102opposite to each other. The P-type column structure110is disposed in the N-type substrate100, and the top surface101exposes a surface of the P-type column structure110. The N-type substrate100and the P-type column structure110constitute a super junction structure so as to improve a withstand voltage of the insulated gate bipolar transistor when the insulated gate bipolar transistor is turned off. The N-type epitaxial layer120is disposed on the top surface101and the surface of the P-type column structure110. The P-type body region130is disposed in the N-type epitaxial layer120. The N-type source region140is disposed in the P-type body region130. The gate structure150is disposed in the N-type epitaxial layer120. The gate structure150is in contact with a surface of the P-type body region130and a surface of the N-type source region140. The P-type collector region160is disposed in the N-type substrate100, and the bottom surface102constitutes a surface of the collector region160.

However, in the above-mentioned structure, when a signal is applied to the gate structure150to turn on the insulated gate bipolar transistor, the blocking ability of the N-type epitaxial layer120is weak, and holes injected in the collector region160may easily enter the P-type body region130through the P-type column structure110, which results in a lower hole concentration in a drift region (the N-type substrate100and the N-type epitaxial layer120). Therefore, an on-resistance of the drift region is high, which results in a high on-state voltage drop of the insulated gate bipolar transistor. Moreover, a turn-off energy loss of the insulated gate bipolar transistor is large. Thus, the performance of the insulated gate bipolar transistor is poor.

In order to solve the above-mentioned technical problem, the technical solution of the present disclosure provides a semiconductor structure and a method of forming the same. With the barrier doped region disposed on the top of the substrate and the deep trench structure, the on-resistance of the drift region can be reduced and the on-state voltage drop of the insulated gate bipolar transistor can be reduced. Moreover, the turn-off energy loss (EOFF) of the insulated gate bipolar transistor can be improved. Thus, the performance of the insulated gate bipolar transistor can be improved.

In order to make above objects, features and beneficial effects of the present disclosure more obvious and understandable, specific embodiments of the present disclosure are described in detail below in combination with the accompanying drawings.

FIGS.2-8are cross-sectional views corresponding to various steps in the method of forming the semiconductor structure according to an embodiment of the present disclosure.

Referring toFIG.2, a substrate200doped with a first ion is provided, and the substrate200has a first surface201and a second surface202opposite to each other.

In some embodiments, the material of the substrate200includes semiconductor material. Specifically, the material of the substrate200includes silicon.

In some embodiments, the material of the substrate includes silicon carbide, silicon germanium, multicomponent semiconductor material composed of III-V elements, Silicon On Insulator (SOI) or Germanium On Insulator (GOI), etc. The multicomponent semiconductor material composed of III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

In some embodiments, the first ion is an N-type ion, that is, the substrate200is an N-type substrate.

Specifically, the N-type ion includes phosphorous ion or arsenic ion.

In some embodiments, the first ion may also be a P-type ion to form a device structure having a conductivity type diametrically opposite to that of above embodiments.

In some embodiments, a doping concentration of the first ion doped in the substrate200ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.

Referring toFIG.3, a deep trench structure210is formed in the substrate200, and a top surface of the deep trench structure210is exposed by the first surface201. The deep trench structure210is doped with a second ion, and the conductivity type of the second ion is opposite to that of the first ion.

Since the conductivity types of the second ion and the first ion are opposite, a super junction structure is formed between the deep trench structure210and the substrate200around the deep trench structure210, so that an insulated gate bipolar transistor (hereinafter referred to as an IGBT device) formed by the substrate200and the deep trench structure210can have a higher withstand voltage performance when being turned off.

In some embodiments, the second ion is a P-type ion.

Specifically, the P-type ion includes boron ion or indium ion.

In some embodiments, the method of forming the deep trench structure210includes: forming a first mask layer (not shown) on the first surface201, wherein a part of the first surface201is exposed by the first mask layer; etching the substrate200with the first mask layer as a mask to form a deep trench (not shown) in the substrate200, wherein the deep trench is exposed by the first surface201, and in a direction perpendicular to the first surface201, the depth of the deep trench is less than the thickness of the substrate200; and forming the deep trench structure210in the deep trench.

In some embodiments, the process of forming the deep trench structure210in the deep trench includes an epitaxial growth process or the like.

In some embodiments, the first masking layer is removed after forming the deep trench structure210.

Referring toFIG.4, a barrier doped region220is formed on the top of the substrate200and the deep trench structure210.

The barrier doped region210is doped with a third ion. The third ion has the same conductivity type as that of the first ion, and a doping concentration of the third ion is greater than that of the first ion in the substrate200.

The purpose of forming the barrier doped region220is to block the carriers injected from subsequently formed collector region by the barrier doped region220having a opposite type to the deep trench structure210and having a greater doping concentration of the third ion, so as to reduce the carriers entering subsequently formed body region through the deep trench structure210.

In some embodiments, the third ion is an N-type ion. Accordingly, the carriers blocked by the barrier doped region220are holes injected from the collector region.

Specifically, the third ion is phosphorus ion.

In some embodiments, the doping concentration of the third ion in the barrier doped region220ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.

If the doping concentration of the third ion in the barrier doped region220is too low, blocking ability for carriers will be weak, and thus better blocking for carriers cannot be achieved. Therefore, with an appropriate doping concentration, that is, the doping concentration of the third ion in the barrier doped region220ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter, the barrier doped region220can have better blocking ability for carriers entering the body region, so as to better improve the performance of the IGBT device.

In some embodiments, in the direction perpendicular to the first surface201, the depth of the barrier doped region220ranges from 0.1 micron to 10 microns.

If the depth of the barrier doped region220is too small, blocking capability for carriers is weak, and thus better blocking for carriers cannot be achieved. If the depth of the barrier doped region220is too large, on the one hand, the efficiency of the manufacturing process may be reduced, on the other hand, the super junction structure may be affected, which adversely affects the withstand voltage performance of the IGBT device. Therefore, with a suitable depth range of the barrier doped region220(0.1 micron to 10 microns), a better voltage withstand performance of the IGBT device can be achieved, while having a better blocking capability for the carriers. Furthermore, the efficiency of the manufacturing process can be increased.

In some embodiments, forming the barrier doped region220on the top of the substrate200and the deep trench structure210includes: performing ion implantation on the first surface201and the top surface of the deep trench structure210.

Forming the barrier doped region220by an ion implantation process can reduce the process difficulty of forming the barrier doped region220compared to forming an ion doping structure having a higher concentration by an epitaxial growth process.

In some embodiments, process parameters for performing ion implantation on the first surface201and the top surface of the deep trench structure210includes: implanted ions include phosphorus ions, implantation dose ranges from 1E11 atoms per square centimeter to 1E14 atoms per square centimeter, and implantation energy is between 1 MeV and 3 MeV.

By employing an implantation dose and an implantation energy in the ranges described above, the formation of the barrier doped region220can be achieved such that the concentration of the third ion doped in the barrier doped region220ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter and such that the depth of the barrier doped region220in the direction perpendicular to the first surface201ranges from 0.1 micron to 10 microns.

Referring toFIG.5, a first epitaxial layer230is formed on the barrier doped region220by an epitaxial growth process.

The first epitaxial layer230is doped with a fourth ion, and the fourth ion has the same conductivity type as that of the third ion.

In some embodiments, the substrate200, the barrier doped region220and the first epitaxial layer230constitute a drift region.

In particular, the doping concentration of the third ion is greater than the doping concentration of the fourth ion.

In some embodiments, the doping concentration of the fourth ion in the first epitaxial layer230is greater than the doping concentration of the first ion in the substrate200.

Since the conductivity types of the fourth ion and the third ion are the same, and the subsequently formed body region and the deep trench structure220are spaced apart by a part of the first epitaxial layer230, the blocking ability for carriers entering the body region can be further increased by making the doping concentration of the fourth ion in the first epitaxial layer230greater than the doping concentration of the first ion in the substrate200based on the first epitaxial layer230on the basis of the barrier doped region220.

In some embodiments, the doping concentration of the fourth ion in the first epitaxial layer is in the range of 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.

On the one hand, too high doping concentration of the fourth ion is detrimental to the withstand voltage performance of the IGBT device, and on the other hand, too high doping concentration greatly increases the difficulty of the epitaxial growth process.

Therefore, by adopting appropriate doping concentration of the fourth ion, when the doping concentration of the fourth ion in the first epitaxial layer is in the range of 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter on the basis that the doping concentration of the fourth ion in the first epitaxial layer230is greater than that of the first ion in the substrate200, a better voltage withstand performance of the IGBT device can be obtained and the difficulty of the epitaxial growth process can be reduced, while the blocking ability for carriers entering the body region can be further increased.

In some embodiments, the fourth ion is an N-type ion.

Referring toFIG.6, a body region240, a source region250and a gate structure260are formed in the first epitaxial layer230.

In some embodiments, the body region240is disposed above the barrier doped region220, and at least a portion of the body region240is also disposed above the deep trench structure210.

In some embodiments, the body region240is doped with P-type ions.

In some embodiments, the source region250is disposed in the body region240, and a partial surface of the source region250is exposed by the body region240.

In some embodiments, the source region250is doped with N-type ions.

In some embodiments, the gate structure260is disposed above the barrier doped region220, the gate structure260is also disposed above the substrate200adjacent to the deep trench structure210, and the gate structure260is in contact with the body region240and the partial surface of the source region250exposed by the body region240.

In some embodiments, the gate structure260includes a gate electrode (not shown) and a gate dielectric layer (not shown) disposed between the gate electrode and the first epitaxial layer230, and the gate dielectric layer is also disposed between the gate electrode and surfaces of the body region and the source region.

Specifically, the body region240, the source region250, and the gate structure260are spaced from the barrier doped region220by the first epitaxial layer230, and surfaces of the gate structure260, the body region240and the source region250are exposed by the surface of the first epitaxial layer230.

In some embodiments, the method of forming the gate structure260in the first epitaxial layer230includes: forming a second mask layer (not shown) on the surface of the first epitaxial layer230, wherein a part of the surface of the first epitaxial layer230on the substrate200on at least one side of the deep trench structure210is exposed by the second mask layer; etching the first epitaxial layer230with the second mask layer as a mask to form a gate opening (not shown) in the first epitaxial layer230; forming a gate dielectric layer on an inner wall surface of the gate opening; forming a gate electrode in the gate opening to form the gate structure260after forming the gate dielectric layer; and removing the second mask layer after forming the gate structure260.

In some embodiments, the method of forming the body region240and the source region250in the first epitaxial layer230includes: performing ion implantation on the first epitaxial layer230disposed above the deep trench structure210at one side of the gate structure260to form the body region240in the first epitaxial layer230, and performing ion implantation on a portion of the body region240to form the source region250in the body region240.

In some embodiments, the body region and the source region may also be formed prior to the gate structure.

Referring toFIG.7, an interlayer dielectric layer270is formed on the surface of the first epitaxial layer230and on the exposed surfaces of the gate structure260, the body region240and the source region250.

The interlayer dielectric layer270is made of a material including a dielectric material.

In some embodiments, the process of forming the interlayer dielectric layer270includes a chemical vapor deposition process or the like.

Still referring toFIG.7, a first conductive structure (not shown) is formed in the interlayer dielectric layer270and coupled to the gate structure260, and a second conductive structure280is formed in the interlayer dielectric layer270and coupled to the body region240and the source region250.

The first conductive structure is used to lead out the gate structure260(the gate of the IGBT device).

The second conductive structure is used to lead out the body region240and the source region250(the emitter of the IGBT device).

In some embodiments, the method of forming the first conductive structure and the second conductive structure280in the interlayer dielectric layer270includes: forming a third mask layer (not shown) on a surface of the interlayer dielectric layer270, wherein a part of the surface of the interlayer dielectric layer270is exposed by the third mask layer; etching the interlayer dielectric layer270with the third mask layer as a mask to form a first opening (not shown) and a second opening (not shown), wherein a part of a top surface of the gate structure260is exposed by the first opening, and a part of top surfaces of the source region250and the body region240is exposed by the second opening; and filling the first opening and the second opening with a conductive material to form the first conductive structure and the second conductive structure280.

In other embodiments, the first epitaxial layer may be patterned according to different mask layers to form the first opening and the second opening, respectively.

Next, referring toFIG.8, a collector region290is formed at the bottom of the substrate200, and a surface of the collector region290is exposed by the second surface202. The collector region290is spaced from a bottom of the deep trench structure210by the substrate200.

The collector region290is doped with a fifth ion.

In some embodiments, the fifth ion is a P-type ion and the doping concentration of the fifth ion is greater than the doping concentration of the second ion.

In some embodiments, the substrate200is thinned from the second surface202using a back thinning process before forming the collector region290.

In some embodiments, the method of forming the collector region290includes performing an ion implantation process on the second surface202to form the collector region290at the bottom of the substrate200after thinning the substrate200.

In some embodiments, after forming the collector region290, a bottom interlayer dielectric layer (not shown) is formed on the second surface202and exposed surface of the collector region290, and a third conductive structure (not shown) is formed in the bottom interlayer dielectric layer and is coupled to the collector region290to lead out the collector region290(the collector of the IGBT device).

Accordingly, another embodiment of the present disclosure provides a semiconductor structure formed by the above-mentioned method. Still referring toFIG.8, the semiconductor structure includes the substrate200, the deep trench structure210, the barrier doped region220, the first epitaxial layer230, the body region240, the source region250, the gate structure260, and the collector region290. The substrate200is doped with the first ion, and has the first surface201and the second surface202opposite to each other. The deep trench structure210is disposed in the substrate200, and the top surface of the deep trench structure210is exposed by the first surface201. The deep trench structure210is doped with the second ion, and the conductivity type of the second ion is opposite to that of the first ion. The barrier doped region220is disposed at the top of the substrate200and the deep trench structure210, and the barrier doped region220is doped with the third ion. The conductivity type of the third ion is the same as that of the first ion, and the doping concentration of the third ion is greater than that of the first ion. The first epitaxial layer230is disposed on the barrier doped region220, and the first epitaxial layer230is doped with the fourth ion. The conductivity type of the fourth ion is the same as that of the third ion, and the doping concentration of the third ion is greater than that of the fourth ion. The body region240is disposed in the first epitaxial layer230. The body region240is disposed above the barrier doped region220, and at least part of the body region240is also disposed above the deep trench structure210. The source region250is disposed in the body region240, and a part of the surface of the source region250is exposed by the body region240. The gate structure260is disposed in the first epitaxial layer230, and the gate structure260is disposed above than the barrier doped region220. The gate structure260is also disposed above the substrate200adjacent to the deep trench structure210, and the gate structure260is in contact with the body region240and the exposed partial surface of the source region250. The collector region290is disposed at the bottom of the substrate200. A surface of the collector region290is exposed by the second surface202, and the collector region290is spaced from the bottom of the deep trench structure210by the substrate200.

Since the conductivity types of the second ion and the first ion are opposite, a super junction structure is formed between the deep trench structure210and the substrate200around the deep trench structure210, so that an insulated gate bipolar transistor (hereinafter referred to as an IGBT device) formed by the substrate200and the deep trench structure210can have a higher withstand voltage performance when being turned off.

On the one hand, the barrier doped region220is disposed on the top of the substrate200and the deep trench structure210, the first epitaxial layer230is disposed on the barrier doped region220, the body region240and the gate structure260are disposed in the first epitaxial layer230, the source region250is disposed in the body region240, and both the body region240and the gate structure260are disposed above the barrier doped region220(namely, the barrier doped region220is spaced apart from the body region240, the source region250and the gate structure260by a part of the first epitaxial layer230), on the other hand, the doping concentration of the third ion is greater than that of the fourth ion and the first ion. Therefore, carriers (holes) entering the body region240through the deep trench structure210(injected from the collector region290) can be blocked by the barrier doped region220at a certain distance from the body region240, thus the carriers (holes) entering the body region240are reduced. Therefore, the carriers (holes) injected from the collector region290can be better collected in a drift region below the body region240and the gate structure260(i.e., the first epitaxial layer230, the barrier doped region220and the substrate200below the body region240and the gate structure260), and the concentration of the carriers (holes) of the drift region can be increased. Thus, not only an on-resistance of the drift region can be reduced to reduce an on-state voltage drop of the insulated gate bipolar transistor, but also a turn-off energy loss (EOFF) of the insulated gate bipolar transistor can be improved. Furthermore, the performance of the IGBT device can be improved.

In some practical applications, compared with the insulated gate bipolar transistor shown inFIG.1, Figure Of Merit (FOM, FOM=Vcesat×Eoff) of the IGBT device can be increased by 5% through the barrier doped region220.

In some embodiments, the material of the substrate200includes semiconductor material. Specifically, the material of the substrate200includes silicon.

In some embodiments, the material of the substrate includes silicon carbide, silicon germanium, multicomponent semiconductor material composed of III-V elements, Silicon On Insulator (SOI) or Germanium On Insulator (GOI), etc. The multicomponent semiconductor material composed of III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

In some embodiments, the first ion is an N-type ion, that is, the substrate200is an N-type substrate.

Specifically, the N-type ion includes phosphorous ion or arsenic ion.

In some embodiments, the first ion may also be a P-type ion to form a device structure having a conductivity type diametrically opposite to that of above embodiments.

In some embodiments, a doping concentration of the first ion doped in the substrate200ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.

In some embodiments, the second ion is a P-type ion.

Specifically, the P-type ion includes boron ion or indium ion.

In some embodiments, the third ion is an N-type ion. Accordingly, the carriers blocked by the barrier doped region220are holes injected from the collector region.

Specifically, the third ion is a phosphorus ion.

In some embodiments, the doping concentration of the third ion in the barrier doped region220ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.

If the doping concentration of the third ion in the barrier doped region220is too low, blocking ability for carriers will be weak, and thus better blocking for carriers cannot be achieved. Therefore, with an appropriate doping concentration, that is, the doping concentration of the third ion in the barrier doped region220is between 1E15 atoms per cubic centimeter and 1E18 atoms per cubic centimeter, the barrier doped region220can have better blocking ability for carriers entering the body region250, so as to better improve the performance of the IGBT device.

In some embodiments, in the direction perpendicular to the first surface201, the depth of the barrier doped region220ranges from 0.1 micron to 10 microns.

If the depth of the barrier doped region220is too small, blocking capability for carriers is weak, and thus better blocking for carriers cannot be achieved. If the depth of the barrier doped region220is too large, on the one hand, the efficiency of the manufacturing process may be reduced, on the other hand, the super junction structure may be affected, which adversely affects the withstand voltage performance of the IGBT device. Therefore, with a suitable depth range of the barrier doped region220, a better voltage withstand performance of the IGBT device can be achieved, while having a better blocking capability for the carriers. Also, the efficiency of the manufacturing process can be increased.

In some embodiments, the fourth ion is an N-type ion.

In some embodiments, the doping concentration of the fourth ion in the first epitaxial layer230is greater than the doping concentration of the first ion in the substrate200.

Since the conductivity types of the fourth ion and the third ion are the same, and the subsequently formed body region and the deep trench structure220are spaced apart by a part of the first epitaxial layer230, the blocking ability for carriers entering the body region can be further increased by making the doping concentration of the fourth ion in the first epitaxial layer230greater than the doping concentration of the first ion in the substrate200based on the first epitaxial layer230on the basis of the barrier doped region220.

In some embodiments, the doping concentration of the fourth ion in the first epitaxial layer is in the range of 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.

In some embodiments, the body region240is doped with P-type ions.

In some embodiments, the source region250is doped with N-type ions.

In some embodiments, the gate structure260includes a gate electrode (not shown) and a gate dielectric layer (not shown) disposed between the gate electrode and the first epitaxial layer230, and the gate dielectric layer is also disposed between the gate electrode and surfaces of the body region and the source region.

Specifically, the body region240, the source region250, and the gate structure260are spaced from the barrier doped region220by the first epitaxial layer230, and surfaces of the gate structure260, the body region240and the source region250are exposed by the surface of the first epitaxial layer230.

In some embodiments, the semiconductor structure further includes an interlayer dielectric layer270, a first conductive structure and a second conductive structure280. The interlayer dielectric layer270is disposed on the surface of the first epitaxial layer230and on the exposed surfaces of the gate electrode structure260, the body region240and the source region250. The first conductive structure (not shown) is disposed in the interlayer dielectric layer270, and is coupled to the gate electrode structure260. The second conductive structure280is disposed in the interlayer dielectric layer270and is coupled to the body region240and the source region250.

The interlayer dielectric layer270is made of a material including a dielectric material.

The first conductive structure is used to lead out the gate structure260(the gate of the IGBT device).

The second conductive structure is used to lead out the body region240and the source region250(the emitter of the IGBT device).

In some embodiments, the collector region290is doped with a fifth ion.

In some embodiments, the fifth ion is a P-type ion and the doping concentration of the fifth ion is greater than the doping concentration of the second ion.

In some embodiments, the semiconductor structure further includes a bottom interlayer dielectric layer (not shown) disposed on the second surface202and on the exposed surface of the collector region290, and a third conductive structure (not shown) disposed in the bottom interlayer dielectric layer. The third conductive structure is coupled to the collector region290to lead out the collector region290(the collector of an IGBT device).

Although the present disclosure has been described above, the present disclosure is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the claims.