TIME-TO-DIGITAL CONVERTERS (TDC) EMPLOYING A SINGLE-STAGE DELAY PAIR AND NOISE SHAPING FOR WIDE INPUT RANGE AND REDUCED QUANTIZATION NOISE IN A PHASE-LOCKED LOOP (PLL)

Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.

BACKGROUND

I. Field of the Disclosure

The technology of the disclosure relates generally to phase-locked loops and, more particularly, to time-to-digital converters that provide fast locking and low noise.

Phase-locked-loop (PLLs) are widely used to generate signals that consistently oscillate at a desired frequency and with as little noise as possible. For example, PLLs may be employed to generate carrier signals for wired or wireless communication or system clocks for clocking digital logic in integrated circuits. As the feature sizes made possible by improvements in integrated circuit (IC) fabrication have become smaller, there are increased benefits to using digital PLLs (DPLLs). One of the components in a DPLL that can significantly affect the quality of the generated output signal is the time-to-digital converter (TDC) circuit. In a PLL, the TDC circuit receives two signals (e.g., rising edges) that are separated by a time period related to a phase difference between a generated output signal and a reference signal. The TDC circuit converts the time period to an integer number that is used to adjust control of a digitally controlled oscillator, which generates the output signal.

Since the objective of the DPLL is to keep the phase of the output signal consistently close to the phase of the reference signal, it is preferable to measure that time difference in fine increments (e.g., with higher resolution) to detect smaller changes. On the other hand, when the power is initially turned on to the DPLL, the phases of the output signal and the reference signal may be far apart. Measuring a large amount of time in very small increments can require a significant amount of circuitry, which occupies area and consumes power on an IC. If the DPLL cannot determine the phase difference between the output signal and the reference signal, it can take much longer to synchronize the output signal to the reference signal at power on. Therefore, in this regard, increasing the size of increments of time measurement is preferable so the circuitry can be reduced.

A conventional Vernier TDC measures the time difference using two strings of delay circuits, but the number of stages needed for a given input range increases with the resolution. Also, if the delays of the delay stages are inconsistent due to process variations, for example, noise (e.g., spurious tones) may be generated on the output signal. Another option to reduce the number of circuits and avoid inconsistent delays is a single-stage Vernier TDC, which includes single delay stages used in a feedback method. However, the delay time of the single-stage delay affects both the input range and the resolution of the TDC circuit, which are conflicting requirements. Thus, a TDC circuit having a wide detection range without sacrificing resolution is desired.

SUMMARY

Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) for a wide input range and reduced quantization noise in a phase-locked loop (PLL). Methods of a fast-locking DPLL with low spurious tones are also disclosed.

A TDC circuit is critical to the ability of a PLL to closely track a reference signal. A Vernier TDC is a well-known design that requires long chains of delay circuits, which occupy area, consume power, and may cause noise in the output signal due to inconsistent delays. A single-stage pair TDC employs the concept of a Vernier TDC but uses a single-stage delay pair in a feedback loop to reduce circuitry and avoid inconsistent delays. Because a TDC measures time periods in increments having a certain resolution, there is necessarily a residual portion (e.g., time remainder) that cannot be reflected in the integer number generated by the TDC. In an exemplary TDC circuit, a first measurement circuit determines an integer number of time increments in a time period and a remainder, and a second measurement circuit generates a fractional indicator, indicating whether an accumulation of the time remainder and previous time remainders exceeds an integer time increment. In some examples, the fractional indicator may be used in a PLL to increase the resolution of the TDC, providing more frequent and finer adjustments to a digitally controlled oscillator (DCO). In this manner, the TDC circuit may have a wider range of detection while pushing the quantization noise to a higher frequency range, where it can be filtered by the PLL.

In this regard, a time-to-digital converter (TDC) circuit is disclosed. The TDC circuit includes a first measurement circuit configured to receive a start pulse signal and a stop pulse signal separated in time by a time period, determine an integer number of consecutive first time increments in the time period, and determine a time remainder of the time period smaller than the first time increment (step). The TDC circuit further includes a second measurement circuit configured to add the time remainder to a previously accumulated remainder to generate a current accumulated remainder and generate a fractional indicator indicating whether a magnitude of the current accumulated remainder (positive or negative) is greater than half of the first time increment (step). Further, in response to the fractional indicator indicating the magnitude of the current accumulated remainder is greater than half of the first time increment, generate a next accumulated remainder comprising a difference between the first time increment and the current accumulated remainder and in response to the fractional indicator indicating the magnitude of the current accumulated remainder is less than half of the first time increment, generate the next accumulated remainder comprising the current accumulated remainder.

In another aspect, a method of a TDC circuit is disclosed. The method includes receiving a start pulse signal and a stop pulse signal separated in time by a time period, determining an integer number of a first time increment and a time remainder smaller than the first time increment within the time period, adding the time remainder to a previously accumulated remainder to generate a current accumulated remainder, and generating a fractional indicator indicating whether the current accumulated remainder differs from the first time increment by more than half of the first time increment. The method further includes in response the fractional indicator indicating the current accumulated remainder differs from the first time increment by more than half of the first time increment, generating a next accumulated remainder comprising a difference between the first time increment and the current accumulated remainder, and in response the fractional indicator indicating the current accumulated remainder differs from the first time increment by less than half of the first time increment, generating the next accumulated remainder based on the current accumulated remainder.

In another aspect, a phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a digitally controlled oscillator (DCO), a loop filter circuit, a divider circuit, and a time-to-digital (TDC) system. The TDC system includes a coarse TDC circuit and a fine TDC circuit. The fine TDC circuit includes a first measurement circuit configured to receive a start pulse signal and a stop pulse signal separated in time by a time period, determine an integer number of consecutive first time increments in the time period, and determine a time remainder of the time period smaller than one of the first time increments. The fine TDC circuit further includes a second measurement circuit configured to add the time remainder to a previously accumulated remainder to generate a current accumulated remainder, generate a fractional indicator indicating whether a magnitude of the current accumulated remainder is greater than half of the first time increment, and in response to the fractional indicator indicating the magnitude of the current accumulated remainder is greater than half of the first time increment, generate a next accumulated remainder comprising a difference between the first time increment and the current accumulated remainder, and in response to the fractional indicator indicating the magnitude of the current accumulated remainder is less than half of the first time increment, generate the next accumulated remainder comprising the current accumulated remainder. The PLL circuit further includes a range determination circuit configured to determine whether the duration of the time period is within a time period range and, in response to determining the duration of the time period is greater than a maximum time period in the time period range, generate the integer number corresponding to the duration of the time period in the coarse TDC circuit, and in response to determining the duration of the time period is within the time period range, generate the integer number corresponding to the duration of the time period in the fine TDC.

DETAILED DESCRIPTION

Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) for a wide input range and reduced quantization noise in a phase-locked loop (PLL). Methods of a fast-locking DPLL with low spurious tones are also disclosed.

In this regard,FIG.1is a block diagram of an exemplary time-to-digital (TDC) system100in an integrated circuit chip101, including an exemplary TDC circuit102having a first measurement circuit104to determine an integer number106indicating an integer number of time increments TI in a time period TP between a start pulse signal START and a stop pulse signal STOP. The time period TP between start pulse signal START and the stop pulse signal STOP is equal to the time period TP between the reference clock CREFand the feedback clock CFB. However, as explained below, the start pulse signal START will lead the stop pulse signal STOP even though the reference clock CREFmay either lead or lag the feedback clock CFB.

The first measurement circuit104generates a time remainder TR that is a remaining portion of the time period TP, and the time remainder TR is smaller than the time increment TI. In an example TP=N(TI)+TR, where N is the integer number106. The time remainder TR is sometimes referred to as a residual time. The TDC circuit102also includes a second measurement circuit108that generates a fractional indicator110based on a sum of the time remainder TR and a previously accumulated remainder PAR (not shown here) to indicate whether a current accumulated remainder CAR (not shown) exceed a fraction of the time increment TI.

Before describing the TDC system100inFIG.1in further detail, an example of a phase-locked loop (PLL)200in which the TDC system100may be employed is first described with reference toFIG.2. The first measurement circuit104and the second measurement circuit108of the TDC circuit102are described in further detail with reference toFIGS.4-7.

The PLL200inFIG.2is an example in which the TDC system100, including the TDC circuit102, may be employed. The PLL200includes a digitally controlled oscillator (DCO)202that generates an output clock signal COUTthat oscillates at an output frequency FOUT. The output clock signal COUTmay be a carrier signal for wired or wireless communication or may be a system clock in digital logic circuits of the IC chip101, for example. For such applications, it is desirable for the output clock signal COUTto have consistent phase and frequency, with a minimum of noise. To improve phase and frequency consistency, the PLL200receives a reference clock signal CREFwhich may be, for example, from a crystal oscillator or other reliable, consistent source for comparison to the output clock signal COUT. The output frequency Four may differ from a reference frequency FREF of the reference clock signal CREF. For example, the output frequency Four may be a multiple X of the reference frequency FREF. The PLL200includes a divider circuit204that divides the output frequency Four of the output clock signal COUTby X to produce a feedback clock signal CFBhaving a feedback frequency FFBfor comparison to the reference clock signal CREF.

In some examples, the multiple X is a non-integer, but the divider circuit204may be a multi-modulus divider (MMD) that is only capable of division by an integer. The mismatch between X and a nearest integer creates significant noise in the output clock signal COUT, so a dithering circuit (not shown) may be used to toggle an integer divisor of the divider circuit204between two or more integer values (e.g., between 10 and 11 for an average of 10.65) to obtain an average of the non-integer multiple. This type of dithering circuit increases frequency accuracy compared to a PLL without the dithering circuit but continues to generate noise on the output clock signal COUT. A PLL that also includes the TDC system100and TDC circuit102inFIG.1, with or without a dithering circuit coupled to the divider circuit, reduces noise on the output clock signal COUTby pushing the quantization noise out of the PLL bandwidth where it can be effectively filtered.

With further reference toFIG.2, the PLL200may receive the reference clock signal CREFand the feedback clock signal CFBdirectly from the divider circuit204as the start pulse signal START and a stop pulse signal STOP. In some examples, the PLL200includes a phase-frequency detector (PFD)206in addition to a TDC208. The TDC208may be the TDC system100inFIG.1, including the TDC circuit102. In examples including the PFD206, the PFD206receives the reference clock signal CREFand the feedback clock signal CFB, compares the phase of the feedback clock signal CFBto the phase of the reference clock signal CREFand generates a start pulse signal START and a stop pulse signal STOP that indicate the phase difference as a time period TP. As an example, the PFD206generates the start pulse signal START as a pulse (e.g., step in voltage) with a leading edge and the stop pulse signal STOP with a leading edge such that the leading edges are separated in time by the time period TP corresponding to the phase difference. The TDC208generates an integer number210, which is a quantification of the time period TP. The integer number210indicates a number of time increments in the time period TP and may be positive or negative. The integer number210may change in every cycle of the reference clock signal CREFand is filtered by a loop filter212. The loop filter212provides a filtered control signal214to the DCO202to control the frequency Four of the output clock COUT. The integer number210is based on a time/phase offset of the feedback clock CFBrelative to the reference clock CREFand is employed by the DCO202to bring the phases closer together, eventually achieving a “lock state” in which the phases of the reference clock signal CREFand the feedback clock signal CFBare the same or kept within a small (e.g., undetectable) margin of phase difference.

Returning toFIG.1, the TDC system100includes a range determination circuit112that receives the reference clock CREFand the feedback clock CFB, which are separated by the time period TP. The range determination circuit112determines a sign of the time period TP in a sign detection circuit114and determines whether a duration of the time period TP is within a time period range of the TDC circuit102. If the feedback clock CFBis received at the TDC system100before the reference clock CREF, the time period TP has a negative sign. If the reference clock CREFis received at the TDC system100before the reference clock CREF, the time period TP has a positive sign. The sign detection circuit114generates a sign indicator SIGN indicating the sign or polarity of the time period TP. If the sign indicator SIGN is positive, the start pulse signal START is based on the reference clock CREFand the stop pulse signal STOP is based on the feedback clock CFB. On the other hand, in instances in which the sign indicator SIGN is negative, a reorder circuit116in the range determination circuit112generates the start pulse signal START from the reference clock CREFand generates the stop pulse signal STOP from the feedback clock CFB. In this manner, the start pulse signal START will arrive at the first measurement circuit104before the stop pulse signal STOP, independent of the sign indicator SIGN.

The range determination circuit112includes a low-limit detector118and a high-limit detector120. The low-limit detector118determines whether the time period TP separating the start pulse signal START and the stop pulse signal STOP is less than the time increment resolution of the TDC circuit102. If so, the low-limit detector118generates a signal RST1to reset the TDC circuit102to prepare the TDC circuit102for a next start pulse signal START. In the example shown, the low-limit detector118sets a flip-flop circuit DFF1to a low level if the time period TP is less than a minimum detectable time or resolution TRESof the TDC circuit102. Specifically, if the stop pulse signal STOP propagates through a first delay circuit122having a first delay period (“first delay”) T1 before the start pulse signal START propagates through a second delay circuit124having a second delay period (“second delay”) T2, the flip-flop circuit DFF1is set to the low level, causing the signal RST1to be generated. Thus, TRES=T1−T2. If the time period TP is shorter than the resolution TRES, which occurs in the locked state, for example, the TDC system100does not make any adjustment to an integer number125provided to the loop filter212inFIG.2. For example, if no adjustment is needed, the integer number125output from the TDC system100may be “0”, indicating no positive or negative difference in phase between the output clock COUTand the reference clock CREF. It is noted that flip-flop circuits, which are edge triggered storage elements, are employed as opposed to latch circuits that are level sensitive. Flip-flops circuits (also referred to herein as “flip-flops”) may also be known as data flip-flops or arbiter circuits.

The high-limit detector120determines whether the time period TP exceeds a maximum detection time of the TDC circuit102, which corresponds to a maximum number of time increments TI that are detectable by the TDC circuit102in a time period TP. In this example, if the high-limit detector120determines that the time period TP exceeds a maximum detection time, a signal RST2is generated to activate a coarse TDC circuit127and reset the TDC circuit102to prepare the TDC circuit102for a next start pulse signal START. In this case, if the stop pulse signal doesn't get to a flip-flop circuit DFF2before the start pulse signal START propagates through delays126A and126B, the flip-flop circuit DFF2generates the signal RST2. The coarse TDC circuit127may initially be activated immediately after power on, when the output clock COUTand the reference clock CREFmay be significantly out of phase. The coarse TDC circuit127is capable of measuring a much larger time period TP than the TDC circuit102but has a much coarser resolution. Relative to the coarse TDC circuit127, the TDC circuit102may be referred to as a fine TDC circuit102because it measures the time period with higher resolution time increments TI.

As an example, the resolution of the coarse TDC circuit127may be determined by a loop of delay circuits128(1)-128(3) (e.g., a ring oscillator), each having a delay T3. A counter130counts a number of times the start pulse signal START propagates through the loop of delay circuits128(1)-128(3) before the stop pulse signal STOP is received. The coarse TDC circuit127generates an integer number132, indicating the time period TP. A sign correction circuit134receives the sign indicator SIGN and converts the integer number132to a negative number if the sign indicator SIGN is negative. It should be understood that the integer number132generated by the coarse TDC circuit127may be consistent with the integer number106generated by the TDC circuit102. In other words, the difference in resolution between the time increments TI of the TDC circuit102and the time measured by the loop of delay circuits128are accounted for in the generation of the integer numbers106and132.

The first measurement circuit104provides the time remainder TR to the second measurement circuit108as a time difference between a pulse on a first remainder input135and a pulse on a second remainder input136.

The TDC system100includes an adder138to add the integer number106generated by the first measurement circuit104and the fractional indicator110generated by the second measurement circuit108to generate a high-resolution integer number140. A sign flip-flop circuit142stores the sign indicator SIGN until the TDC circuit102generates the integer number106. A sign correction circuit144corrects the high-resolution integer number140if the SIGN generated in the sign flip-flop circuit142indicates the time remainder TR is negative. A selector circuit148selects one of the high-resolution integer number140from the TDC circuit102and the integer number132from the coarse TDC circuit127, depending on which is employed. The term “flip-flop circuit” may be used interchangeably with the terms “data flip-flop” or “flip-flop” herein.

FIG.3is a flowchart of a method of the exemplary TDC circuit inFIG.1for determining a number of time increments TI and a fraction of a time increment in a time period TP, the method comprising receiving a start pulse signal START and a stop pulse signal STOP separated in time by a time period TP (block302) and determining an integer number106of a first time increment TI and a time remainder TR smaller than the first time increment TI within the time period TP (block304). The method includes adding the time remainder TR to a previously accumulated remainder PAR to generate a current accumulated remainder CAR (block306) and generating a fractional indicator110indicating whether the current accumulated remainder differs from the first time increment by more than a fraction of the first time increment TI (block308). The method further includes, in response, the fractional indicator110indicating the current accumulated remainder CAR differs from the first time increment TI by more than a fraction of the first time increment TI, generating a next accumulated remainder NAR comprising a difference between the first time increment TI and the current accumulated remainder CAR (block310) and, in response the fractional indicator110indicating the current accumulated CAR remainder differs from the first time increment TI by less than the fraction of the first time increment TI, generating the next accumulated remainder NAR based on the current accumulated remainder CAR (block312).

FIG.4is a logic circuit diagram illustrating details of a first measurement circuit400, which may be the first measurement circuit104in the TDC circuit102inFIG.1. The first measurement circuit400is employed to determine a number of time increments TI in a time period TP and provide a time remainder TR to the second measurement circuit108.

The first measurement circuit400employs a method similar to a Vernier TDC circuit (not shown) in which a start pulse signal propagates through a series of delay circuits that each have a first delay T1 (“first delay period T1”) and a stop pulse signal propagates through a series of delay circuits that each have a second delay T2 (“second delay period T2”). The second delays T2 are shorter than the first delays T1, so the stop pulse signal eventually catches up to the start pulse signal after a number X of delay circuits. From this, it can be determined that the start pulse signal and the stop pulse signal in this example are separated by a time period that is at least X times T1−T2. In such a circuit, a first problem is that the time difference between the start pulse signal and the stop pulse signal may also include a time remainder that is less than T1−T2, which cannot be measured by the Vernier circuit. The resolution of the time measurement by a Vernier circuit is limited to T1−T2, so the time remainder can allow a difference or error in a PLL that is less than T1−T2. A second problem with the Vernier circuit is that the delay circuits in the first series may not all have exactly the same delay T1 due to, for example, process variations in fabrication, and the delay circuits in the second series, for the same reasons, may not all have exactly the delay T2, which can create noise in the output clock generated by the PLL. The TDC circuit102addresses both of these problems. The first problem is addressed by the second measurement circuit108inFIG.1, which is described in detail with reference toFIG.6. The second problem is addressed as follows.

The first measurement circuit400includes a first delay feedback circuit402comprising a first delay circuit404that receives the start pulse signal START at a first delay input406. The first delay feedback circuit402employs the first delay circuit404to delay the start pulse signal START and generate a delayed start pulse signal DSTRT on a first delay output408. The first delay circuit404has a delay of duration T1. In this regard, the first delay circuit404corresponds to a stage in the first series of delay circuits in a Vernier circuit, but rather than passing the delayed start pulse signal DSTRT to a next delay circuit, the first delay feedback circuit402feeds back the delayed start pulse signal DSTRT from the first delay output408to the first delay input406and reuses the first delay circuit404in an iterative manner.

In a similar aspect, the first measurement circuit400includes a second delay feedback circuit410comprising a second delay circuit412that receives the stop pulse signal STOP at a second delay input414. The second delay feedback circuit410employs the second delay circuit412to delay the stop pulse signal STOP and generate a delayed stop pulse signal DSTP on a second delay output416. The second delay circuit412has a delay of duration T2, which is shorter than T1. Thus, the time increment TI measurement by the first measurement circuit400, also referred to as the resolution TRESis T1−T2. In this regard, the second delay circuit412corresponds to a stage in the second series of delay circuits in a Vernier circuit, but the second delay feedback circuit410feeds back the delayed stop pulse signal DSTP from the second delay output416to the second delay input414and reuses the second delay circuit412iteratively. Employing the first delay feedback circuit402and the second delay feedback circuit410, because the first delay circuit404and the second delay circuit412are reused, there is no delay mismatch due to different cascaded cells as in a conventional Vernier TDC. In this regard, the first measurement circuit400, avoids spurious tones.

The first measurement circuit400includes a flip-flop circuit418with a data output420that is set the first time the delayed start pulse signal DSTRT is provided to a data input422, and the delayed stop pulse signal DSTP is provided to a clock input424. The data output420is reset in a subsequent iteration when the delayed stop pulse signal DSTOP is generated on the second delay output416in advance of the delayed start pulse signal DSTRT being generated on the first delay output408. In other words, the flip-flop418is reset when propagation of the delayed stop pulse signal DSTOP through the second delay feedback circuit410catches up with propagation of the delayed start pulse signal DSTRT through the first delay feedback circuit402.

The first measurement circuit400includes a counter circuit426, including a counter428, and a count flip-flop430. A trigger flip-flop432in the first measurement circuit400is employed to detect a transition of the count mode flip-flop418and trigger generation of the time remainder TR as a difference between a first time remainder signal TRS1on a first remainder output434and a second time remainder signal TRS2on a second remainder output436.

A description of additional features of the first measurement circuit400and operation thereof is provided with further reference toFIG.4and also with reference to the timing diagram500inFIG.5.FIG.5is a timing diagram illustrating signals at certain points in the first measurement circuit400. These signals are represented as binary values (e.g., “0” or low and “1” or high) that may represent voltage levels at the identified points in the first measurement circuit400. Transitions between these binary values are referred to herein as rising and falling edges, for example, where the passage of time is from left to right.

In particular, starting from the top, the timing diagram500includes inputs438and440, which receive the start pulse signal START and the stop pulse signal STOP, respectively.FIG.5next includes the first delay input406, the second delay input414, the first delay output408, and the second delay output416.FIG.5also includes the data output420of the count mode flip-flop418and a node442used to trigger generation of the time remainder TR. Finally,FIG.5includes the first remainder output434and the second remainder output436on which the time remainder TR is generated.

As shown inFIG.5, a leading edge L1of the start pulse signal START, at which a level of the start pulse signal START rises, occurs at time to and, at time t1, a leading edge L2of the stop pulse signal STOP indicates a rise in the stop pulse signal STOP. The time between the leading edge of the start pulse signal START and the leading edge of the stop pulse signal STOP is the time period TP that is being measured in time increments TI by the first measurement circuit400(i.e., TP=t1−t0). The start pulse signal START and the stop pulse signal STOP are received at a pulse generation circuit444. The pulse generation circuit444produces a wide pulse WP corresponding to the start pulse signal START on the first delay input406and a narrow pulse NP corresponding to the stop pulse signal STOP on the second delay input414, respectively. The rise of the narrow pulse NP follows the rise of the wide pulse WP by the time period TP but the narrow pulse NP and the wide pulse WP fall simultaneously.

The wide pulse WP propagates through a first NOR gate (Not-OR circuit) R1and a second NOR gate R2before propagating through the first delay circuit404to the first delay output408. The first delay output408is coupled to an input of an AND gate A1which is further coupled back to the first NOR gate R1. In this regard, a feedback loop is formed from the first delay output408back to the first delay input406. A total first feedback loop time T1_P from the first delay output408, through the first delay feedback circuit402and back to the from the first delay output408includes the propagation delays through the NOR gates R1and R2, the AND gate A1, and the first delay circuit404.

The narrow pulse NP propagates through a third NOR gate R3and a fourth NOR gate R4before propagating through the second delay circuit412to the second delay output416. The second delay output416is coupled to an input of another AND gate A2, which is further coupled back to the third NOR gate R3. In this regard, a feedback loop is also formed from the second delay output416back to the second delay input414. A total second feedback loop time T2_P through the second feedback delay circuit410includes propagation through the NOR gates R3and R4, the AND gate A2, and the second delay circuit412.

The wide pulse WP on the first delay output408is also referred to as the delayed start pulse signal DSTART and the narrow pulse NP on the second delay output416is also referred to as the delayed stop pulse signal DSTOP. The first delay output408is coupled to the data input422of the count mode flip-flop418and the second delay output416is coupled to the clock input424of the count mode flip-flop418. Since the range determination circuit112inFIG.1, which includes the low-limit detector118to determines that the time period TP provided to the TDC circuit102inFIG.1is equal to or greater than T1−T2, a first time the wide pulse WP propagates through the first delay circuit404to first delay output408(see time t2), the rising edge of the wide pulse WP reaches the data input422before the rising edge of the narrow pulse NP (see t3) reaches the clock input424. Thus, the rising edge of the narrow pulse NP triggers the count mode flip-flop418to propagate the wide pulse WP from the data input422to the data output420. The second delay output416is also coupled to the counter428of the counter circuit426, causing the counter428to increment each time the narrow pulse NP propagates (see t3 and t4) through the second delay circuit412onto the second delay output416after the wide pulse WP has already propagated through the first delay circuit404to the first delay output408. Thus, the counter428counts the iterations of the narrow pulse NP through the second delay feedback circuit410. The number of iterations is provided on a node446to the count flip-flop430.

The data output420remains high as the wide pulse WP and the narrow pulse NP are iteratively fed back through the first delay feedback circuit402and the second delay feedback circuit410, respectively. Because the delay T2 of the second delay feedback circuit410is shorter than the delay T1 of the first delay feedback circuit402, the rising edge of the delayed stop pulse signal DSTOP (or narrow pulse NP) will, after some number of iterations, arrive (see t5) on the second delay output416before the rising edge of the delayed start pulse signal DSTRT (or wide pulse WP) arrives on the first delay output408. When the narrow pulse NP arrives on the clock input424of the count mode flip-flop418before the wide pulse WP arrives on the data input422of the count mode flip-flop418, the data input422of the count mode flip-flop418is still at the low level when the narrow pulse NP clocks the data input422through to the data output420, causing the data output420to drop to the low level at t6.

As noted above, the number of iterations of the delayed stop pulse signal DSTOP on the second delay output416is provided by the counter428to the count flip-flop430on the node446. When the data output420drops to the low level, the count flip-flop430stores the count on the node446to generate the integer number448, which may be the integer number106inFIG.1. In this regard, the first measurement circuit400determines a number of the time increments TI (equal to T1−T2) that occur in the time period TP. The time remaining in the time period TP is the time remainder TR, which is the difference between the rising edge on the second delay output416and the rising edge on the first delay output408, or the amount of time by which the rising wide pulse WP trails the rising narrow pulse NP.

The data output420dropping to the low level also turns on AND gates450and452, which are coupled to the second delay output416and the first delay output408, respectively. Thus, a rising edge first occurs on the first remainder output434based on the narrow pulse NP. A rising edge occurs later on the second remainder output436, corresponding to the wide pulse WP. The time between the rising edge on the first remainder output434and the rising edge on the second remainder output436is the time remainder TR between the rising edge of the second delay output416and the first delay output408.

The start pulse signal START and the stop pulse signal STOP occur every cycle of the reference clock CREFshown inFIG.2. Thus, once the integer number106has been generated in a first cycle of the reference clock CREF, the first measurement circuit400needs to be reset to be ready for measuring the time period TP in the next cycle. In this regard, the first measurement circuit400includes a reset flip-flop454having a clock input456that is coupled to a negative data output458of the count mode flip-flop418. When the delayed stop pulse signal DSTP catches up to the delayed start pulse signal DSTART, as described above, and the data output420of the count mode flip-flop418drops to the low level, the negative data output458rises, triggering the clock input456. A data input460of the reset flip-flop454receives a master reset signal RSTB, which is not used in normal operation and can be assumed to remain at a high (“1”) level. A negative data output462of the reset flip-flop454causes a pulse generator464to reset the counter428. Upon arrival of the next start pulse signal START and stop pulse signal STOP, a pulse generator466resets the reset flip-flop454. The master reset signal RSTB is provided to other inputs of the first measurement circuit400, as shown inFIG.4.

FIG.6Ais a logic circuit diagram illustrating details of a second measurement circuit600, which may be the second measurement circuit108in the TDC circuit102inFIG.1. The second measurement circuit600receives the time remainder TR from the first measurement circuit104(or first measurement circuit400inFIG.4), and adds the time remainder TR to a previously accumulated remainder PAR to generate the current accumulated remainder CAR. The second measurement circuit600generates a fractional indicator110based on the current accumulated remainder CAR, which is added (e.g., by the adder138inFIG.1) to increase the resolution of the integer number106. The second measurement circuit600also calculates a next accumulated remainder NAR. As explained below, the next accumulated remainder NAR generated in one cycle of the start pulse signal START and the stop pulse signal STOP is fed back and becomes the previously accumulated remainder PAR in a next cycle of the start pulse signal START and the stop pulse signal STOP. In this manner, all the time remainders TR contribute to the accuracy of a TDC.

The second measurement circuit600includes a time adder circuit602, an analog to digital converter (ADC) circuit604, and a digital to analog converter (DAC) circuit606, explained individually. A detailed logic circuit diagram of the time adder circuit602is provided inFIG.6B. As shown inFIG.6A, the time adder circuit602receives a remainder start signal RSTRT on a first remainder input608and receives a remainder stop signal RSTOP on a second remainder input610. The first remainder input608may be coupled to the first remainder output434of the first measurement circuit400inFIG.4and the second remainder input610may be coupled to the second remainder output435. The remainder stop signal RSTOP rises after the remainder start signal RSTRT with a separation in time equal to the time remainder TR of the time period TP. The time adder circuit602also receives a previously accumulated remainder PAR on a first PAR input612and a second PAR input614. A separation in time between a rising edge on the first PAR input612and a rising edge on the second PAR input614is equal to the previously accumulated remainder PAR. The time remainder TR and the previously accumulated remainder PAR are added together by the time adder circuit602, as described with reference toFIG.6B.

The time adder circuit602inFIG.6Bincludes a discharge circuit616, a first capacitor618, a second capacitor620, a first sum flip-flop622, and a second sum flip-flop624. A detailed description of the time adder circuit602is first provided with reference toFIG.6B, and a detailed description of the operation thereof is provided with reference to bothFIG.6Band the timing diagram inFIG.7.

The discharge circuit616includes a first discharge control circuit626, including transistors628A and628B, for discharging the first capacitor618in response to an initializing reset signal RST_INI. The transistors628A and628B are coupled in series between a first node630P and a ground rail GND. The first discharge control circuit626also includes transistors632A and632B that are also coupled serially between the first node630P and the ground rail GND. Control inputs634A and634B of the transistors632A and632B are coupled, respectively, to the second PAR input614and the first remainder input608.

The discharge circuit616also includes a second discharge control circuit636, including transistors638A and638B, for discharging the second capacitor620in response to the initializing reset signal RST_INI. The transistors638A and638B are coupled in series between a second node630N and the ground rail GND. The second discharge control circuit636also includes transistors639A and639B that are also coupled serially between the first node630P and the ground rail GND. Control inputs640A and640B of the transistors639A and639B are coupled, respectively, to the first PAR input612and the second remainder input610. The first node630P is coupled to a power supply rail PWR by a first switch (e.g., a transistor)642A, and the second node630N is coupled to the power supply rail PWR by a second switch642B. The first switch642A and the second switch642B, are both controlled by the remainder start signal RSTRT. The first node630P is coupled to a clock input646A of the first sum flip-flop622via a first inverter648A and the second node630N is coupled to a clock input646B of the second sum flip-flop624via a second inverter648B.

The first remainder input608(RSTRT) and the second remainder input610(RSTOP) are at a low level before the time remainder TR is provided. The low level of the remainder start signal RSTRT controls the first switch642A and the second switch642B to be open to couple the first node630P and the second node630N to the power supply rail PWR, thereby charging both of the first capacitor618and the second capacitor620to a first voltage VDD, which may be a power supply voltage. The first PAR input612and the second PAR input614are also at a low level initially, turning on the transistor632A in the first discharge control circuit626and turning on the transistor638A in the second discharge control circuit636. The low levels in the first and second remainder inputs608,610keep the transistors632B and638B shut off. Thus, even though the transistors632A and638A are turned on, the first capacitor618and the second capacitor620cannot discharge through the first and second discharge control circuits626,636in the initial state ofFIG.7.

At time t0 of the timing diagram inFIG.7, a rising transition of the first remainder input608shuts off the first and second switches642A,642B. The rising transition of the first remainder input608turns on the transistor632B, allowing the first capacitor618to begin to discharge, as shown by a voltage of the first node630P inFIG.7. The rise of the first remainder input608is followed at time t1 by a rising transition of the second remainder input610with a separation time equal to the time remainder TR. The rise of the second remainder input610turns on the transistor638B, allowing the second capacitor620to discharge, as shown inFIG.7, by a voltage on the second node630N. The first capacitor618is discharging for the duration of the time remainder TR, then both of the first capacitor618and the second capacitor620continue to discharge after the rise of the second remainder input610.

Assuming that the first capacitor618and the second capacitor620are discharged at a same rate, a difference between a voltage at the first node630P and a voltage at the second node630N at time t1 corresponds to the time remainder TR. As both of the first capacitor618and the second capacitor620continue to discharge, this difference remains constant. At a time t2 shortly after the rise of the second remainder input610at t1, one of the first PAR input612and the second PAR input614occurs. In the first example inFIG.7, the first PAR input612rises at t2, shutting off the transistor638A, which stops discharge of the second capacitor620(e.g., the node630N) from the first voltage VDD to a second reduced voltage V2while the first capacitor618continues to discharge. At time t3, which follows time t2 by a time equal to the preview accumulated reminder PAR, the second PAR input614rises also, shutting off the transistor632A to stop discharging of the first capacitor618(e.g., the node630P) from the first voltage VDD to a first reduced voltage V1. Thus, the duration of the discharge of the first capacitor618differs from the duration of the discharge of the second capacitor by a time equal to the time remainder TR and the previously accumulated remainder PAR. Since this discharge duration time difference corresponds to a difference in voltage based on a same rate of discharge, a difference in voltage between the first node630P and the second node630N at time t3 is related to a sum of the time remainder TR and the previously accumulated remainder PAR.

At time t4, a reset signal RST (unrelated to the master reset signal RSTB discussed above) resets a first sum signal SUM+ on an adder output644A of the first sum flip-flop622and resets ta second sum signal SUM-on an adder output644B of the second sum flip-flop624to a low level. As shown inFIG.7, although the first node630P and the second node630N have fallen in voltage, which causes a rise in voltage at the clock inputs646A and646B due to the inverters648A and648B, the first sum flip-flop622and the second sum flip-flop624are not triggered (e.g., clocked). However, at time t5, both of the first PAR input612and the second PAR input614transition to a low level, causing the transistors632A and638A to turn back on to discharge both of the first capacitor618and the second capacitor620at the same rate. Due to the difference in voltages on the first node630P and the second node630N, the first node630P is the first to fall below a threshold voltage VTHRat which the clock input646A of the first sum flip-flop622is triggered, setting the first sum signal SUM+ at time t6. Since the difference in voltage between the first node630P and the second node630N is related to the sum of the time remainder TR and the previous accumulated remainder PAR, the second node630N will discharge to fall below the threshold voltage VTHR, causing the clock input646B to be activated and setting the second sum signal SUM− of the second sum flip-flop624at time t7. In this manner, the time difference between the activation of the first sum signal SUM+ and the second sum signal SUM− is also equal to the sum of the time remainder TR and the previously accumulated remainder PAR, which is the current accumulated remainder CAR.

Referring back toFIG.6A, the first and second sum signals SUM+ and SUM− are outputs from the time adder circuit602and are coupled to a first input650A and a second input650B, respectively, of the ADC circuit604. A function of the ADC circuit604is to determine whether a magnitude of the current accumulated remainder CAR (which may be positive or negative) is greater than a fraction of the time increment TI. In this example, the fraction is one-half (½). The ADC circuit604includes first T1 delay circuit652and first TO delay circuit654, which are both coupled to the first input650A. The ADC circuit604includes a second TO delay circuit656and a second T1 delay circuit658, which are both coupled to the second input650B. The first and second T1 delay circuits652and658have a same delay of duration T1 as the first delay circuit404. The first and second TO delay circuits654and656have a same delay of duration TO.

For reasons explained below with reference to the DAC circuit606, a difference between T1 and T0 is half of the difference between T1 and T2 inFIG.4. That is, the time increment TI used in the first measurement circuit400inFIG.4, which determines the resolution of the TDC circuit102inFIG.1, is two times the difference between T1 and TO, or T1−T0=(T1−T2)/2. The ADC circuit604generates a fractional indicator660, corresponding to the fractional indicator110inFIG.1, to indicate whether the current accumulated remainder CAR has a magnitude greater than T1/2 or not and whether it is positive or negative.

The ADC circuit604also includes a positive arbiter662and a negative arbiter664. The first T1 delay circuit652is coupled to a data input DINI of the positive flip-flop662, and the second TO delay circuit656is coupled to the clock input CKIN1of the first positive flip-flop662. In the above example, where the current accumulated remainder CAR is a positive value, a rising edge on the second sum signal SUM− (output644B) follows a rising edge on the first sum signal SUM+ (output644A) by a time equal to the current accumulated remainder CAR. In such an example, the rising edge on the output644A propagates through the first T1 delay circuit652, and the rising edge on the output644B, which arrives later, propagates through the second T0 circuit delay. If the current accumulated delay CAR is greater than T1−T0, the rising edge propagating through the first T1 delay circuit652will reach the data input DINI of the positive flip-flop662before the rising edge propagating through the second TO delay circuit656reaches the clock input CKIN1, and a data output DOUT1of positive flip-flop662is set to the high level (“1”). On the other hand, if the current accumulated delay CAR is less than T1−T0, the rising edge propagating through the second TO delay circuit656reaches the clock input CKIN1before the rising edge propagating through the first T1 delay circuit652will reach the data input DINI of the positive flip-flop662, and the data output DOUT1of positive flip-flop662is set to the low level (“0”).

A currently accumulated remainder CAR having a negative value will cause a rising edge to occur first on the output644B, followed by a rising edge on the output644A. In the manner described above, the rising edges propagating through the first TO delay circuit654and the second T1 delay circuit658will cause a data output DOUT2of the negative flip-flop664to be set to “1” if the magnitude of the current accumulated remainder CAR is greater than T1−T0, and will otherwise be set to “0”. The fractional indicator660is determined by the positive flip-flop662and the negative flip-flop664. In this example, the fractional indicator660may be a two-bit binary value of 01, 00, or 10.

As noted, the fractional indicator660may be the fractional indicator110inFIG.1, and the integer number448inFIG.4may be the integer number106. The fractional indicator110is used to effectively round up or round down the integer number106based on the current accumulated remainder CAR. Including the fractional indicator110with the integer number106, the TDC circuit102improves the accuracy over a TDC circuit with only an integer number output, where the remainders are unaccounted for. This adjustment is explained in the following examples.

If a first example in which the current accumulated remainder CAR is +0.75(TI), which is greater than TI/2, the fractional indicator660will cause the integer number provided to the DCO202to increment by 1. As should be understood, this is an over-adjustment in response to the actual time remainder TR in a given cycle. However, the next accumulated remainder NAR will be −0.25(TI) to compensate for the over-adjustment in the next cycle (or later).

In a second example, the current accumulated remainder CAR is any value between ˜+0.49(TI) and ˜−0.49(TI) (providing a small margin compared to 0.5, in consideration of possible device variation and jitter impact), the fractional indicator will not cause the integer number106inFIG.1to be changed, and the current accumulated remainder CAR will become the next accumulated remainder NAR to be used in the next cycle.

In a third example, the current accumulated remainder CAR is −0.82(TI), so the fractional indicator660will cause the integer number106to be decremented, and +0.18(TI) is provided as the next accumulated remainder NAR.

Based on the above examples, it can be seen that, on average, the phase differences between the output clock COUTand the reference clock CREFwill be significantly reduced.

The purpose of the DAC circuit606is to provide the next accumulated remainder NAR from a current cycle as the previously accumulated remainder PAR in a next cycle. The DAC circuit606can use the output of the ADC circuit604to determine whether to add or subtract the time increment TI (=T1−T2) to the current accumulated remainder CAR to generate the NAR. The DAC circuit606is first structurally described with reference toFIG.6A, and the operation thereof is described with additional reference back toFIG.7.

The DAC circuit606includes a first T1 delay circuit670and a first T2 delay circuit672, which are both coupled to the output644A and are respectively coupled to first and second inputs674A and674B of a multiplexor676. The DAC circuit606includes a second TI delay circuit680and a second T2 delay circuit682, which are both coupled to the output644B and are respectively coupled to first and second inputs684A and684B of a multiplexor686. An output ERR+ of the multiplexor676and an output ERR− of the multiplexor686are coupled to a delay circuit690.

Referring back toFIG.7, rising edges on the first and second sum signals SUM+ and SUM− are shown at times t5 and t6, respectively, with the first sum signal SUM+ rising first, which occurs when the sign of the current accumulated remainder CAR is positive. In the negative case, a rising edge occurs on the second sum signal SUM-before a rising edge on the first sum signal SUM+.

At time t6, the rising edge of the output SUM+ is provided to the first T1 delay circuit670and the first T2 delay672. Based on the fractional indicator660, the multiplexor676selects the first sum signal SUM+ delayed by T1 to be provided on the output ERR+. At time t7, the rising edge of the second sum signal SUM− is provided to the second T1 delay circuit680and the second T2 delay682, and the multiplexor686selects the SUM-delayed by T2 to be provided on the output ERR−. In this manner, the time difference between first and second sum signals SUM+ and SUM− has been reduced by the time increment TI (T1−T2). That is the time difference between ERR+ and ERR−, which is the next accumulated remainder NAR, shown as the previously accumulated remainder PAR in the next cycle at time t78. As shown, the NAR is a negative amount equal to the current accumulated remainder CAR minus (T1−T2). The delay circuit690delays ERR+ and ERR− by a same amount of time and is coupled to the first PAR input612and a second PAR input614, where the next accumulated remainder NAR from one cycle of the reference clock CREFis stored and provided as the previously accumulated remainder PAR in a next cycle.

FIG.8is a logic circuit diagram of a calibration circuit800, including the first feedback circuit402and the second feedback delay circuit410ofFIG.4, for the purpose of calibrating the time resolution TRES, which is a difference between the first delay period T1_P of the first feedback circuit402and the second delay period T2_P of the second feedback delay circuit410. Details of the first feedback circuit402and the second feedback delay circuit410are provided above and are not repeated here. The difference between T1_P and T2_P is known if a first number or count CNT1 of the first delay period T1_P is equal to a second number or count CNT2 of the second delay period T2_P. This may be shown as an equation:

In one example, if CNT1=4 and CNT2=5, then (4)×T1_P=(5)×T2_P.

Since TRES=T1_P−T2_P, then it can be seen that TRES=T1_P/5 in this example.

As a reminder, the first delay period T1_P inFIG.4is based on the first delay T1 of the first delay circuit404, the NOR gates R1and R2, and the AND gate A1. The second delay period T2_P is based on the second delay T2 of the second delay circuit412, the NOR gates R3and R4, and the AND gate A2. Assuming the NOR gates R1-R4are all of a same delay and the AND gates A1and A2are also of a same delay, the primary difference between first delay period T1_P and second delay period T2_P is based on a difference between the first delay T1 and the second delay T2. The first delay T1 and the second delay T2 may be selected to satisfy the equation above where T1_P=10 ns and T2_P=8 ns. However, variations in propagation delay are inevitable among all the components, so the calibration circuit800is provided to achieve or approach the above relationship of CNT1×T1_P=CNT2×T2_P.

A calibration operation of the calibration circuit800, which may be performed in a calibration mode of the first measurement circuit400, counts a number of iterations of the CAL_IN determines whether CNT1×T1_P=CNT2×T2_P and adjusts the second delay period T2_P. Alternatively, the calibration circuit800may adjust the first delay period T1_P or both the first delay period T1_P and the second delay period T2_P. Such operation is described below following a description of components of the calibration circuit800.

The first delay output802of the first delay feedback circuit402is coupled to a calibration counter804and a time delay806. Both of the calibration counter804and the time delay806are coupled to AND gate808. Similarly, a second delay output810of the second delay feedback circuit410is coupled to inputs of a second calibration counter812and a time delay814, which are both further coupled to an AND gate816.

The AND gates808and816have respective outputs818A and818B, which are coupled to an order determination circuit820. An output822of the order determination circuit820is provided to an adjustment circuit824, which can generate an adjustment signal ADJ on an output826. The output826is coupled to a variable capacitor828that is further coupled to the second delay output810of the second delay feedback circuit410.

In the calibration mode, inputs830A and830B of the first and second delay circuits402,410are coupled together to receive a calibration pulse signal CAL_IN simultaneously, as shown inFIG.9. The calibration counter804counts a first number of iterations of the calibration pulse signal CAL_IN propagating through the first delay circuit402in a feedback loop and the calibration counter812counts a second number of iterations of the calibration pulse signal CAL_IN propagating through the second delay feedback circuit410.

When the calibration counter804count CNT1 reaches the desired value (e.g., 4 in the example above), a first calibration pulse CP1is generated by the calibration counter804to the AND gate808. The time delay806delays the CAL_IN pulse received from the first delay output810to synchronize the first calibration pulse CP1to the AND gate808. When the calibration counter812count CNT2 reaches that desired value (e.g., 5), a second calibration pulse CP2is generated by the calibration counter812and provided to the AND gate816, synchronized by the CAL_IN pulse propagating through the time delay814.

The order determination circuit820includes arbiter circuits832A and832B. The first calibration pulse CP1is provided as data to the arbiter circuit832A through a first offset (delay) circuit834P and the first calibration pulse CP1is also provided, without a delay, to clock the arbiter circuit832B. Similarly, the second calibration pulse CP2is provided as data to the flip-flop circuit832B through a second offset circuit834N and the second calibration pulse CP2is also provided, without an offset delay, to clock the arbiter circuit832A. It can be seen that, due to the offset circuits834P and834N, neither of the flip-flop circuits832P and832N will be set (e.g., to “1”) unless the difference in time between the first calibration pulse CP1and the second calibration pulse CP2is greater than the offset delay. An incrementer836generates the adjustment signal ADJ as one of +1, 0, or −1 on the output826, depending on the flip-flop circuits832P and832N.

For example, if the flip-flop circuit832P is set by the second pulse signal CP2at the first clock input CK1, the second calibration pulse CP2is leading the first calibration pulse CP1by at least the offset delay of offset circuit834P. Thus, if the first calibration pulse CP1and the second calibration pulse CP2are separated in time by more than the offset delay, the incrementer836will generate an appropriate one of +1 or −1 to cause the adjustment signal ADJ to increase capacitance of the variable capacitor828which increases capacitance on the second delay output810and increase the second delay period T2_P. The variable capacitor828can be adjusted to increase or decrease capacitance by the adjustment signal ADJ. The adjustment signal ADJ may adjust the capacitance of the variable capacitor828by an incremental amount and the operation describe above will be repeated until the first calibration pulse CP1and the second calibration pulse CP2are separated by less than the offset delay, causing the adjustment signal ADJ to be “0”. The variable capacitor828is held at the determined capacitance value during normal operation outside the calibration mode. Employing the calibration circuit800, the time increment TI can be in the range of less than 5% of T1_P. In some examples, the time increment TI can be less than 2% of T1_P.

One operation of the calibration circuit800can be seen in the timing diagram900inFIG.9. After the calibration pulse signal CAL_IN arrives, the count CNT1 of the counter804and the count CNT2 of the calibration counter812both increment in response to the calibration pulse signal CAL_IN propagating to the first delay output802and the second delay output810. The count CNT1 increments each time the calibration pulse signal CAL_IN propagates to the first delay output802, and the count CNT2 of the calibration counter812increments each time the calibration pulse signal CAL_IN propagates to the second delay output810. Circuits838,840,842,844, and846are employed to reset the calibration circuit800to be ready for the next calibration pulse signal CAL_IN.

FIG.10is a block diagram of an exemplary processor-based system1000that includes a processor1002(e.g., a microprocessor) that includes an instruction processing circuit1004and a PLL200ofFIG.2and a TDC system100ofFIG.1. Any of the processor-based system1000, the processor1002, and the instruction processing circuit1004can be the IC chip101inFIG.1as an example. The processor-based system1000may be a circuit or circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server, or a user's computer.

In this example, the processor1002represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, or the like. The processor1002is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor1002includes an instruction cache1006for temporary, fast access memory storage of instructions accessible by the instruction processing circuit1004. Fetched or prefetched instructions from a memory, such as from the cache memory1012over a system bus1010, are stored in the instruction cache1006. The instruction processing circuit1004is configured to process instructions fetched into the instruction cache1006and process the instructions for execution.

The processor1002and the cache memory1012are coupled to the system bus1010and can intercouple peripheral devices included in the processor-based system1000. As is well known, the processor1002communicates with these other devices by exchanging address, control, and data information over the system bus1010. For example, the processor1002can communicate bus transaction requests to a memory controller1014in the main memory1008as an example of a slave device. Although not illustrated inFIG.10, multiple system buses1010could be provided, wherein each system bus constitutes a different fabric. In this example, the memory controller1014is configured to provide memory access requests to a memory array1016in the main memory1008. The memory array1016is comprised of an array of storage bit cells for storing data. The main memory1008may be a read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), etc., and a static memory (e.g., flash memory, static random access memory (SRAM), etc.), as non-limiting examples.

Other devices can be connected to the system bus1010. As illustrated inFIG.10, these devices can include the main memory1008, one or more input device(s)1018, one or more output device(s)1020, a modem1022, and one or more display controllers1024, as examples. The input device(s)1018can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s)1020can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem1022can be any device configured to allow exchange of data to and from a network1026. The network1026can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem1022can be configured to support any type of communications protocol desired. The processor1002may also be configured to access the display controller(s)1024over the system bus1012to control information sent to one or more displays1028. The display(s)1028can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc. Any of the input devices1018, the modem1022, and the output devices1020may be the IC chip101or otherwise may include the TDC system100.

The processor-based system1000inFIG.10may include a set of instructions1030to be executed by the processor1002for any application desired according to the instructions. The instructions1030may be stored in the main memory1008, processor1002, and/or instruction cache1006as examples of a non-transitory computer-readable medium1032. The instructions1030may also reside, completely or at least partially, within the main memory1008and/or within the processor1002during their execution. The instructions1030may further be transmitted or received over the network1026via the modem1022, such that the network1026includes the computer-readable medium1032while the computer-readable medium1032is shown in an exemplary embodiment to be a single medium, the term “computer-readable medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and/or associated caches and servers) that stores the one or more sets of instructions. The term “computer-readable medium” shall also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by the processing device and that causes the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. The term “computer-readable medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical medium, and magnetic medium.

Unless specifically stated otherwise and as apparent from the previous discussion, it is appreciated that throughout the description, discussions utilizing terms such as “processing,” “computing,” “determining,” “displaying,” or the like refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data and memories represented as physical (electronic) quantities within the computer system's registers into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission, or display devices.