Universal non-volatile support device for supporting reconfigurable processing systems

A universal support device for supporting a reconfigurable electronics device is disclosed. The universal support device includes an application specific integrated circuit (ASIC) module coupled to multiple non-volatile memory devices. The ASIC module is capable of interfacing with an external reconfigurable electronics device via a set of load/read-back interface lines and sense mitigation lines. The load/read-back interface lines are capable of being programmed to provide a parallel or a serial load and/or store protocols. The sense mitigation line can sense conditions that indicate a single-event functional interrupt or a radiation-induced event occurred within the reconfigurable electronics device.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to electronic devices in general, and in particular to field programmable gate arrays. Still more particularly, the present invention relates to a universal non-volatile support device for supporting reconfigurable processing systems.

2. Description of Related Art

Field programmable gate arrays (FPGAs) are commonly utilized to demonstrate or prove out a conceptual data processing system. Offering similar densities and performance as application specific integrated circuits (ASICs), FPGAs are typically a driver for the latest technology. There are two types of FPGAs, namely, fuse-based FPGAs and memory-based FPGAs. Fuse-based FPGAs can only be written once after which no change can be made to the logic. Memory-based FPGAs, on the other hand, have changeable logic but need to be reloaded each time. Thus, memory-based FPGAs are more suitable for implementing reconfigurable processing systems.

A reconfigurable processing system typically includes multiple reconfigurable FPGA building blocks that are capable of being morphed into any required processing capability after the reconfigurable processing system has been assembled. Thus, reconfigurable processing systems can play a major role in responsive spacecraft, fault-tolerant spacecraft and multi-mission spacecraft because the functionalities of reconfigurable processing systems can be easily modified for specific needs even after a spacecraft has been launched into space.

Reconfigurable processing systems are typically put together with off-the-shelf pre-defined components. As FPGAs become more widespread with improving capabilities, reconfigurable computing elements (RCEs) formed by FPGAs will soon be employed throughout reconfigurable processing systems, both as stand-alone elements and as embedded elements. Many of the RCEs share similar reconfigurable enabling technologies; however, rather than one RCE configuration fits all, there are specializations in each application area that best fit different types of RCEs.

The present disclosure provides a universal non-volatile support device for supporting random access memory-based reconfigurable processing systems and other types of reconfigurable electronics such as field programmable analog arrays.

SUMMARY OF THE INVENTION

In accordance with a preferred embodiment of the present invention, a universal support device for supporting a reconfigurable electronics device includes an application specific integrated circuit (ASIC) module coupled to multiple non-volatile memory devices. The ASIC module is capable of interfacing with an external reconfigurable electronics device via a set of load/read-back interface lines and sense mitigation lines. The load/read-back interface lines are capable of being programmed to provide a parallel or a serial load and/or store protocols. The sense mitigation lines can sense conditions that indicate a single-event functional interrupt or a radiation-induced event occurred within the reconfigurable electronics device.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Referring now to the drawings and in particular toFIG. 1, there is depicted a block diagram of a universal reconfigurable electronics support device (URESD), in accordance with a preferred embodiment of the present invention. As shown, an URESD10includes an application specific integrated circuit (ASIC) module11and a non-volatile memory array12having non-volatile memory devices12a-12n.An interface to non-volatile memory devices12a-12nis performed via address/control and data lines14. ASIC module11may be implemented in any field programmable electronics such as fused-based field programmable gate arrays (FPGAs).

URESD10is scalable and may provide an interface to additional non-volatile memory devices, such as non-volatile memory devices13a-13n,if such non-volatile memory devices are needed for one or more configuration loads to support a specific level of reconfigurable electronics. An interface to non-volatile memory devices13a-13nis performed via address/control and data lines15. Additional address lines can be provided for future growth.

When URESD10is intended to be used in single-event upset (SEU) susceptible environment, such as space, then all components within URESD10need to be manufactured with radiation-hardened technologies. In addition, error-correcting codes (ECCs) may be used in redundant bits if SEUs are expected in non-volatile memory devices12a-12nas well as non-volatile memory devices13a-13n.

URESD10can be interfaced to a system memory/bridge module16via address/control and data lines17and/or a serial line18utilizing a serial protocol such as Joint Testing Application Group (JTAG). URESD10may initiate transfers to system memory/bridge module16using an interface such as peripheral component interface (PCI) (parallel) or SpaceWire (serial), or URESD10may operate as a slave to system memory/bridge module16only responding to operations. URESD10also has the ability to receive or to provide status and interrupts back to system memory/bridge module16via a status/interrupt line19.

URESD10can be interfaced to a reconfigurable electronics device60via a set of load/read-back interface lines61that may be programmed to provide a variety of parallel or serial load or store protocols spanning the signal set. In addition, sense mitigation lines62may be used to sense conditions that indicate a signal-event functional interrupt (SEFI) or other radiation-induced event has occurred within reconfigurable electronics device60. Load/read-back interface lines61along with sense mitigation lines62are used to load, read back configuration sense radiation-induced events, reset reconfigurable electronics device60and to fix any bits in error. URESD10may read its configuration information either from some subset of interface lines61and17and/or from its internal non-volatile memory array12to share/enable sets of pins, set and/or change their functions or pin widths.

With reference now toFIG. 2, there is depicted a detailed block diagram of ASIC module11fromFIG. 1, in accordance with a preferred embodiment of the present invention. As shown, ASIC module11includes a configuration controller core21, a configuration registers internal memory core22, a reconfigurable electronics configuration mitigation core23, an attached memory controller core24, an external memory controller core25, a bus interface core26, a serial interface core27, and a clock and timing core28. Configuration controller core21is initially activated after power-up in order to make sure that all configuration registers in each core as well as internal memory core22are loaded with their default (non-volatile) values. External lines may be used to direct external memory controller core25to choose if more than one configuration memory exists. Such configurations are either loaded from an on-chip non-volatile memory within internal memory core22or from a small pre-defined section of URESD memory through attached memory controller core24.

External memory controller core25may interface to one or more external system memory. Configuration registers within the various cores and internal memory core22indicate interface sizes and protocols, speed of interfaces, parallel or serial loading of reconfigurable electronics devices. They also indicate their width (if parallel), the size of blocks to check before correction, the amount and location of memory and operations to be performed upon power-up, the configuration image number, the sequencing registers, along with error detection and correction.

After ASIC module11has been configured, reconfigurable electronic device60(fromFIG. 1) may be controlled automatically or on command from ASIC module11. Configuration controller core21directs configuration mitigation core23to fetch a configuration from internal non-volatile memories (such as non-volatile memory array12fromFIG. 1) and load the configuration into reconfigurable electronics device60.

After the configuration has been loaded, configuration controller core21directs configuration mitigation core23to enable the function of the volatile reconfigurable electronics device and then begins reading back its configuration and checking the configuration with what is stored in internal or external memory either through direct comparisons of the data or through comparisons of codes covering the data. If a mismatch is found, configuration mitigation core23then sends an interrupt to an external processor through status/interrupt line19and to configuration controller core21to complete its current block check, and then configuration controller core21directs configuration mitigation core23to reload the block and recheck the configuration. Configuration mitigation core23can also be configured to stop, reload the block and then resume operation. If the configuration is good, configuration mitigation core23sends an all-good status signal to configuration controller mole21that in turn passes it to system memory/bridge module16(fromFIG. 1). Status pins, memory or registers indicating the device or block being repaired will also be maintained for readout or polling.

Non-volatile attached memory controller core24and external memory controller cores25read or write non-volatile or volatile memory assets to URESD10or other external devices, as directed by the other controllers. External memory controller core25provides enough drive for low-latency access to external memories.

In a slave mode, bus interface core26and serial interface core27simply responds to read and write accesses from system memory/bridge module16and then directs the data in or out of the appropriate element in the support chip or non-volatile memory. In a master mode, bus interface core26and serial interface core27pass data back to system memory/bridge module16as directed by configuration controller core21. Clock and timing core28manages all timing between various scores within URESD module11and responds to resets from ASIC module11. The various cores are preferably interconnected via an on-chip bus that can be a shared bus structure or a cross-bar switch.

Referring now toFIG. 3, there is illustrated a high-level logic flow diagram of a method for performing a sequencing within URESD10, in accordance with a preferred embodiment of the present invention. Starting at block30, the configuration for URESD10is read from a configuration memory, and a specific personalization is loaded, as shown in block31. Once personalized, URESD10is not required to be loaded every time, although each personalization loading can eliminate any latent errors caused by SEUs. SEU errors may also be eliminated through the usage of ECCs implemented on personalization registers or flagged for reload by error detection codes or redundancy. Based on the loaded personalization, various interfaces within URESD10may be set up to match the type of reconfigurable electronics device to which URESD10is connected, such as reconfigurable electronics device60fromFIG. 1, as depicted block32. The setting up of various interfaces may include the change of number of bits, the frequency of transmission, handshake polarity or timing, etc.

Next, certain counters of the reconfigurable electronics device are initialized, as shown in block33. Within the reconfigurable electronics device, data are preferably maintained in blocks, directories or packets, and counters are initialized for each block, as depicted in block34. After a block has been initialized, the actual data to be loaded or compared can be sequenced according to sequencing registers based on each block definition. Each field type is processed as configured accordingly, as shown in block35. Some examples of possible field types are shown inFIG. 4.

End block37is used to differentiate one block of processing from another. If end block37is the last block of processing for the reconfigurable electronics device, end device38is next sequenced; otherwise, the sequence jumps back to the start block34. End device38cleans up the reconfigurable electronics device handling and if it is the last reconfigurable electronics device, cleanup interface is executed, as shown in block39. Otherwise, the process can return to block33for a next reconfigurable electronics device. The status of such operation is stored, as shown in block70, and the sequence is completed, as depicted in block71. At such time, either another sequence may be started or URESD10may wait for a command from system memory/bridge module16(fromFIG. 1).

With reference now toFIG. 4, there is depicted a block diagram of field types examples in a block within a reconfigurable electronics device, in accordance with a preferred embodiment of the present invention. As shown, process Header41represents any fixed codes that need to be sent to a reconfigurable device. Process Address40sends any address fields to the reconfigurable device in the output stream and including shifting and serializing. Process Address40increments by some fixed value after the current address is sent. Process Data49fetches the next packet or block of data and send it to the reconfigurable device. Compare Data50reads a packet or block of data from the reconfigurable device and compares it to the value stored in configuration memory or it compares a checksum of each data element. Process Checksum44receives a checksum and compares it to the checksum stored in memory or to the last block or packet of data read from configuration memory. Process Footer45sends a fixed code to the reconfigurable device. Process Count43sends the current count of data to the reconfigurable device. Process Handshake47activates external handshake signals to the reconfigurable device for fixed periods or on a permanent basis. Wait on Handshake48waits on a change or level on an external signal from the reconfigurable device before continuing. Process Error51checks for an error and if one is found sets the appropriate registers and input/outputs to report an error and may also change certain count or sequence states to either restart a sequence or start another. Process Decomposition46is used to decompress a packet or block of data and send it to the reconfigurable device according to a compression algorithm.

As has been described, the present invention provides a universal support devices for supporting reconfigurable electronics devices. The support device of the present invention can be useful in any space system that uses reconfigurable electronics devices having an external configuration memory to provide savings in size, power and developmental costs and in part due to reuse and programming of a single developed devices instead of continual new instantiations and the combining of multiple functions into a single device. The support device of the present invention can also be used in commercial processing systems that require non-volatile memory in their reconfigurable electronics devices.