Method and system for a semiconductor device package with a die-to-die first bond

Methods for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die. An underfill material may be applied between the semiconductor die and the interposer die, and a mold material may be applied to encapsulate the semiconductor die. The interposer die may be thinned to expose through-silicon-vias (TSVs). The bonding of the semiconductor die may comprise adhering the semiconductor die to an adhesive layer, and bonding the semiconductor die to the interposer die. The semiconductor die may comprise micro-bumps for coupling to the interposer die, wherein the bonding comprises: positioning the micro-bumps in respective wells in a layer disposed on the interposer die; and bonding the micro-bumps to the interposer die. The semiconductor die may be bonded to the interposer die utilizing a mass reflow process or a thermal compression process.

This application makes reference to U.S. application Ser. No. 13/678,058, filed on even date herewith, and U.S. application Ser. No. 13/678,012, filed on even date herewith.

Each of the above cited applications is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to semiconductor chip packaging. More specifically, certain embodiments of the invention relate to a method and system for a semiconductor device package with a die-to-die first bond.

BACKGROUND OF THE INVENTION

Semiconductor packaging protects integrated circuits, or chips, from physical damage and external stresses. In addition, it can provide a thermal conductance path to efficiently remove heat generated in a chip, and also provide electrical connections to other components such as printed circuit boards, for example. Materials used for semiconductor packaging typically comprise ceramic or plastic, and form-factors have progressed from ceramic flat packs and dual in-line packages to pin grid arrays and leadless chip carrier packages, among others.

DETAILED DESCRIPTION OF THE INVENTION

Certain aspects of the invention may be found in a method and system for a semiconductor device package with a die-to-die first bond. Example aspects of the invention may comprise bonding one or more semiconductor die comprising electronic devices to an interposer die. An underfill material may be applied between the one or more semiconductor die and the interposer die, and a mold material may be applied to encapsulate the one or more bonded semiconductor die. The interposer die may be thinned to expose through-silicon-vias (TSVs). Metal contacts may be applied to the exposed TSVs, and the interposer die with the bonded one or more semiconductor die may be bonded to a packaging substrate. The bonding of the one or more semiconductor die may comprise: adhering the one or more semiconductor die to an adhesive layer; and bonding the adhered one or more semiconductor die to the interposer die. The one or more semiconductor die may comprise micro-bumps for coupling to the interposer die, where the bonding comprises positioning the micro-bumps in respective wells in a layer disposed on the interposer die, and bonding the micro-bumps to the interposer die. The underfill material may be applied utilizing a capillary underfill process. The one or more semiconductor die may be bonded to the interposer die utilizing a mass reflow process or a thermal compression process. The one or more additional semiconductor die may be bonded to the one or more semiconductor die utilizing a mass reflow process. One or more additional semiconductor die may be bonded to the one or more semiconductor die utilizing a thermal compression process. The mold material may comprise a polymer. The bonding of the one or more semiconductor die may comprise placing the one or more semiconductor die and the interposer die in a fixture that allows the one or more semiconductor die and the interposer die to flex in one direction but not in an opposite direction, and processing the one or more semiconductor die and the interposer die through a reflow process.

FIG. 1Ais a schematic illustrating an integrated circuit package configured with a die-to-wafer first bond, in accordance with an example embodiment of the invention. Referring toFIG. 1A, there is shown a package100comprising integrated circuit die101, a packaging substrate103, passive devices105, an interposer die107, solder balls111, a lid113, and thermal interface material118.

The die101may comprise integrated circuit die that have been separated from one or more semiconductor wafers. The die101may comprise electrical circuitry such as digital signal processors (DSPs), network processors, power management units, audio processors, RF circuitry, wireless baseband system-on-chip (SoC) processors, sensors, and application specific integrated circuits, for example. In addition, the plurality of die101may comprise micro-bumps109for providing electrical contact between the circuitry in the plurality of die101and contact pads on the surface of the interposer die107.

The interposer die107may comprise a semiconductor die, such as a silicon die, with through-silicon-vias (TSVs)115that provide electrically conductive paths from one surface of the interposer die107to the opposite surface. The interposer die107may also comprise backside bumps117for making electrical and mechanical contact to the packaging substrate103. In another example scenario, the interposer die107may comprise glass or an organic laminate material, either of which may be capable of large panel formats on the order of 500×500 mm, for example.

The packaging substrate103may comprise a mechanical support structure for the interposer die107, the die101, the passive devices105, and the lid113. The packaging substrate103may comprise solder balls111on the bottom surface for providing electrical contact to external devices and circuits, for example. The packaging substrate103may also comprise conductive traces in a non-conductive material for providing conductive paths from the solder balls to the die101via pads that are configured to receive the backside bumps117on the interposer die107. Additionally, the packaging substrate103may comprise pads119for receiving the solder balls111. The pads119may comprise one or more under-bump metals, for example, for providing a proper electrical and mechanical contact between the packaging substrate103and the solder balls111.

The passive devices105may comprise electrical devices such as resistors, capacitors, and inductors, for example, which may provide functionality to devices and circuits in the die101. The passive devices105may comprise devices that may be difficult to integrate in the integrated circuits in the die101, such as high value capacitors or inductors. In another example scenario, the passive devices105may comprise one or more crystal oscillators for providing one or more clock signals to the die101.

The lid113may provide a hermetic seal for the devices within the cavity defined by the lid110and the packaging substrate103. A thermal interface may be created for heat transfer out of the die101to the lid113via the thermal interface material118, which may also act as an adhesive.

In an example scenario, the package100may be fabricated by first bonding the die101to the interposer die107when the interposer die107comprises an individual die, and may be bonded utilizing a mass reflow or thermal compression process. In instances where the die101are bonded using a mass reflow process, backside bumps on the interposer die107might also be reflowed if present. Accordingly, the die101may be bonded to the interposer die107before the117backside bumps are placed. The interposer die107with attached die101may be processed for further assembly. For example, the interposer die107may be thinned (e.g., before or after the above-mentioned die-bonding) to expose the through-silicon-vias (TSVs)115, and the backside bumps117may be deposited. Furthermore, a capillary underfill material may be placed between the die101and the interposer die107(e.g., in an example scenario in which underfilling with a non-conductive paste and/or tape is not performed during the bonding process) before a mold process is utilized to encapsulate the plurality of die101.

The assembly comprising the die101and the interposer die107may be processed as described above and the assembly may then be bonded to the packaging substrate103, utilizing either a mass reflow or thermal compression process, for example. The lid113may be placed on the bonded assembly to provide a hermetic seal, to protect the circuitry from the external environment, and/or to serve as a heat sink. Finally, electrical tests may be performed following the bonding processes to verify that proper electrical connections were made and no shorts or open circuits exist.

FIG. 1Bis a schematic illustrating an integrated circuit package configured with a die-to-die first bond and stacked die, in accordance with an example embodiment of the invention. Referring toFIG. 1B, there is shown a package150comprising the die101, the packaging substrate103, the passive devices105, the interposer die107, and a stack of dynamic random access memory (DRAM)121. The die101, the packaging substrate103, the passive devices105, and the interposer die107may be substantially as described with respect toFIG. 1A, for example, but with different electrical connectivity for the different die101and the stack of DRAM121.

The DRAM121may comprise a stack of die for providing a high density memory for circuitry in the die101or external to the package150. The DRAM121may be stacked front-to-back and therefore comprise TSV's for providing electrical connectivity between the individual die.

In an example scenario, the package150may be fabricated by first bonding the die101and the DRAM121to the interposer die107when in die form. The die101and the DRAM121may be bonded utilizing a mass reflow or thermal compression process. In an example scenario, the thermal compression process may utilize polymers, such as anisotropic films and/or conductive adhesives, for example.

In instances where the die101and the stack of DRAM121are bonded using a mass reflow process, backside bumps on the interposer die107might also be reflowed if present at the time of the reflow process. Accordingly, the die101and the stack of DRAM121may be bonded to the interposer die107before the117backside bumps are placed. The interposer die107with attached die101and the stack of DRAM121may be processed for further assembly. For example, the interposer die107may be thinned to expose the through-silicon-vias (TSVs)115, and the backside bumps117may be deposited. Furthermore, a capillary underfill material may be placed between the die101, the stack of DRAM121, and the interposer die107(e.g., in an example scenario in which underfilling with a non-conductive paste and/or tape is not performed during the bonding process) before a mold process is utilized to encapsulate the die101and stack of DRAM121.

Electrical tests may be performed following the bonding processes to verify that proper electrical connections were made and no shorts or open circuits exist. Also, as described previously with regard toFIG. 1A, the assembly may be bonded to the packaging substrate103and then overmolded and/or lidded.

FIGS. 1C-1Eillustrate steps for bonding multiple die utilizing an adhesive film, in accordance with an example embodiment of the invention. Referring toFIG. 1C, there is shown a plurality of die122and an adhesive layer129. The die122may comprise metal interconnects123for subsequent bonding to other die. In another example scenario, the metal interconnects123may comprise microbumps or copper pillars, for example.

The adhesive film129may comprise an adhesive tape or compliant layer, for example, to which the die122may be bonded, as illustrated inFIG. 1Cfor example. The adhesive film129may be a temporary adhesive for attaching multiple die to one or more other die, for example. For example, the interposer127may comprise an individual interposer die. In an example scenario, the die122may be placed temporarily on the adhesive film129.

An optional underfill material125may also be placed on the interposer127as illustrated by underfill material125inFIG. 1D, for example, before bonding the die122to the interposer127utilizing the adhesive film129. The underfill material125may be used for subsequent thermal compression bonding processes, for example, and may allow instant underfill through a snap cure during a subsequent thermal compression bonding process. This may improve bonding yields since a single underfill process may be utilized for the plurality of die122as compared to a separate place and underfill process for each of the die122in a conventional process. The die122may be placed face up so that the metal interconnects123may be coupled to a receiving die.

The plurality of die122on the adhesive film129may then be placed on the interposer127, as shown inFIGS. 1D and 1Efor example, where the initial placement of the die122on the adhesive film129may enable fine control of the spacing and alignment of the die122with the interposer127. In an example scenario, the interposer127may be gang bonded to the die122. The interposer127may comprise metal pads131for receiving the metal interconnects123. Once the die122are placed on the interposer127, a thermal compression bond process may be performed for proper electrical and mechanical bonds between the metal interconnects123and the metal pads131. Once bonded, the adhesive film129may be removed resulting in the structure shown inFIG. 1E.

FIGS. 2A-2Fillustrate steps in a die-to-die first bond structure, in accordance with an example embodiment of the invention. Referring toFIG. 2A, there is shown an interposer die201and a plurality of semiconductor die203A and203B. The semiconductor die203A and203B may comprise integrated circuit die that have been separated from one or more semiconductor wafers. The semiconductor die203A and203B may comprise electrical circuitry such as digital signal processors (DSPs), network processors, power management units, audio processors, RF circuitry, wireless baseband system-on-chip (SoC) processors, sensors, and application specific integrated circuits, for example.

In addition, the semiconductor die203A and203B may comprise micro-bumps205for providing electrical contact between the circuitry in the semiconductor die203A and203B and front side pads209on the surface of the interposer die201. While two die are shown inFIGS. 2A-2F, the invention is not so limited, as any number of die may be bonded to the interposer die201dependent on chip area.

The interposer die201may comprise front side pads209for providing electrical contact to the semiconductor die203A and203B. Furthermore, the interposer die201may comprise through-silicon-vias (TSVs)207for providing electrically conductive paths from one surface of the interposer to the other, for example, once the interposer die201has been thinned.

The semiconductor die203A and203B may be placed on the interposer die201and bonded using a thermal compression bonding technique, for example. In another example scenario, a mass reflow process may be utilized to bond the semiconductor die203A and203B. A non-conductive paste (NCP) may also be utilized to assist in forming the bonds. In addition, a capillary underfill may then be applied and may fill the volume between the semiconductor die203A and203B and the interposer die201.FIG. 2Billustrates the semiconductor die203A and203B bonded to the interposer die201with underfill material210. When deposited or placed, the underfill material210may comprise a film, paste, b-stage film, or a liquid, for example.

The space between and/or around the respective perimeters of the semiconductor die203A and203B may be filled with a mold material211, as illustrated inFIG. 2Cfor example. The mold material211may comprise a polymer material, for example, that may provide a non-conductive structural support for die bonded to the interposer die201, protecting the die in subsequent processing steps. Note that the mold material211, in various example scenarios, may cover the top of one or more of the semiconductor die203A and203B. In an example scenario, the interposer die201may be thinned utilizing a back side polish or grind, for example, to expose the TSVs207.

While the underfill material210is shown inFIGS. 2B-2F, the mold material itself may be utilized as underfill material for each coupling interface, such as between the die203A and203B and the interposer die201. In another example embodiment, underfill material may be inserted as a liquid or paste, placed as a film, or a b-staged film and may be placed sequentially as each die to substrate or die to die bond is made, or may be made all at one time after all the electrical bonds are made.

In another example scenario, the interposer die201may be thinned to a thickness where the TSVs are still slightly covered, which may then be etched selectively in areas covering the TSVs. A protective layer may then be deposited over the remaining silicon and a polish of the exposed metal may be performed for improved contact to the TSVs207. Additionally, metal pads may be deposited on the polished TSV surfaces for better contact with the backside bumps213.

In another example scenario, the interposer die201may already be thinned and comprise the backside bumps213prior to receiving the semiconductor die203A and203B. In this case, structural supports, adhesive films, and film frames, such as is illustrated inFIGS. 6A-6E, for example, may be utilized to process the interposer die201.

After the interposer die201has been thinned, the backside bumps213may be deposited, as shown inFIG. 2D, for making contact between the TSVs207and subsequently bonded substrates, such as, for example, packaging substrates.

The assembly comprising the semiconductor die203A and203B and the interposer die201may then be bonded to the packaging substrate215via the backside bumps213, as illustrated inFIG. 2E. The packaging substrate215may comprise a mechanical support structure for die assemblies and may also support passive devices and a lid, for example. The packaging substrate215may comprise contact pads219for making contact with the backside bumps213on the interposer die201and also for subsequent placement of solder balls227(or alternative structures) as shown inFIG. 2F.

In addition, the lid223may be placed on the package assembly with a hermetic seal made with an adhesive225at the surface of the packaging substrate221, which may also comprise a thermal interface material. Accordingly, the lid221may make contact with the top surfaces of the semiconductor die203A and203B (e.g., directly or through a thermal interface material) for thermal heat sinking purposes. The solder balls227may comprise metal spheres for making electrical and mechanical contact with a printed circuit board, for example.

FIG. 3is a schematic illustrating steps in a die-to-die first bond process, in accordance with an example embodiment of the invention. Referring toFIG. 3, there is shown a die-to-die process beginning with a die to interposer die attach step301. The one or more die may be bonded utilizing a thermal compression bonding technique or a mass reflow process, for example. In the example shown inFIG. 3, a mass reflow process is utilized. Additional die may also be bonded to the first bonded die, such as illustrated by the DRAM stack121shown inFIG. 1B, or the interposer wafer as shown inFIG. 1A.

After the die are placed on the interposer die, the assembly may then be subjected to a reflow process303A, where the assembly may be heated to provide a suitable electrical and mechanical connection between metal interconnects. An underfill process305A may be utilized following the bonding process (e.g., in an example scenario in which underfilling did not occur during the bonding process), which may provide an insulating barrier between contacts and may fill the volume between the die and the interposer wafer.

A molding step307may then be utilized to package the die/interposer assembly, for example, before thinning the interposer die to expose the TSVs in the backside finish step309. In addition, backside contacts may be applied to the exposed TSVs in the interposer wafer (e.g., in an example scenario in which such contacts had not been previously formed).

Once the backside contacts are placed, the assembly may be attached to a packaging substrate in the attach die stack to substrate step311. This may be followed by a second reflow step303B for creating proper electrical and mechanical bonds to the packaging substrate and an underfill step305B for filling the volume between the die and interposer assembly and the packaging substrate. Finally, the bonded package may be subjected to a final test step313for assessing the performance of the electronic circuitry in the bonded die and to test the electrical contacts made in the bonding processes.

FIG. 4is a diagram illustrating a mechanical planarizing apparatus, in accordance with an example embodiment of the invention. Referring toFIG. 4, there is shown a boat401, clips403, a plurality of semiconductor die405, and an interposer407, where the interposer407may be in die form. The boat401may comprise a rigid support structure, or fixture, in which a die/interposer assembly may be placed and held in place by the clips403. The boat401may be capable of withstanding high temperatures, above 200 C, for example used for processing the die/interposer assembly.

The plurality of semiconductor die405may be bonded to the interposer407, when in die form, via a thermal compression bonding, technique, for example, prior to being placed in the boat401. As the temperature of the boat401, the plurality of semiconductor die405, and the interposer407increases, the curvature of an assembly comprising the plurality of semiconductor die405and the interposer407may flatten with the clips403providing a downward force at the outer edges of the assembly. As the curvature approaches zero, the increased length in the lateral direction may be accommodated by the sliding of the assembly under the clips403. In addition, the boat401provides mechanical support in conjunction with the downward force of the clips403, thereby planarizing the assembly.

The boat401and clips403may permit the partially assembled package to heat up in normal fashion, but when the die/interposer assembly has become flat with increased temperature, the boat401and clips403resist the normal progression of the warpage, holding the partially assembled package, flattening it during heating and then maintaining that flatness of the silicon interposer as temperatures climb higher.

FIG. 5is a diagram illustrating a vacuum planarizing apparatus, in accordance with an example embodiment of the invention. Referring toFIG. 5, there is shown a boat501, a plurality of semiconductor die505, an interposer507, vacuum sealing rings509, vacuum channels511, a valve513, and a vacuum supply515.

In an example scenario, the boat501may comprise a vacuum system, or fixture, to flatten the partially assembled package comprising the plurality of semiconductor die505and the interposer507when in die form. The vacuum-mechanical system permits the partially assembled package to heat up in normal fashion, but when the partially assembled package has become flat, the vacuum-mechanical system resists the normal progression of the warpage, holding the partially assembled package in a flattened configuration during heating and then maintains that flatness of the silicon interposer die507as temperatures increases.

The vacuum may be applied at room temperature or slightly elevated temperatures utilizing the vacuum supply515via the valve513and the vacuum channels511, and may be held utilizing the high-temperature sealing rings509so that the vacuum-mechanical boat501may travel through a standard reflow furnace and still maintain a sufficient vacuum to maintain interposer silicon top surface planarity.

FIGS. 6A-6Eillustrate example steps for debonding wafers with large backside bumps, in accordance with an example embodiment of the invention. Referring toFIG. 6A, there is show a carrier wafer601, a wafer603with backside bumps605, and a polymer layer607.

The wafer603may comprise an electronics wafer or an interposer wafer, for example, which may comprise large backside bumps605that may be susceptible to damage in debond processes. Accordingly, the polymer layer607may be applied to protect the backside bumps605during debond processes. The polymer layer607may comprise a resist material or an adhesive film or tape, for example, which may be applied on the device wafer603over the backside bumps605. While wafers are shown inFIG. 6A, the technique may also be utilized on die.

A subsequent chuck attachment, such as with a vacuum technique, to the carrier wafer601and the top surface of the polymer layer607is shown inFIG. 6B. The top chuck609A may be moved in one lateral direction while the bottom chuck609B may be moved in the opposite direction to separate the carrier wafer601from the wafer603. The polymer layer607may enable a proper vacuum seal to the surface, where there may be a poor seal when applied directly to the backside bumps605.

FIG. 6Cshows a resulting structure following debond from the carrier wafer601. Any adhesive residue remaining from the carrier wafer601may be removed in a cleaning process while still attached to the top chuck609A.

The cleaned structure may then be affixed to a film frame611with the backside bumps605facing up and being detached from the top chuck609A, as shown inFIG. 6D. The polymer layer607may then be removed either chemically or thermally, and thereafter may undergo a surface clean, resulting in the bonded wafer603shown inFIG. 6E, for example. The film frame611may enable further processing and ease of transport for the bonded wafer603.

FIG. 7is a diagram illustrating die bonding utilizing a patterned underfill layer, in accordance with an example embodiment of the invention. Referring toFIG. 7, there is shown a top semiconductor die701with microbumps703and a bottom semiconductor die705comprising contact pads707and an underfill layer709.

In an example scenario, the microbumps703may comprise copper pillars, for example, and may correspond to the contact pads707in the bottom semiconductor die705. Although the bottom semiconductor die705is shown as a single die, in another example scenario, it may comprise an entire wafer of die (e.g., an interposer wafer), with a plurality of top semiconductor die701being bonded to the wafer as opposed to a single die. In an example scenario, the bottom semiconductor die705comprises a single interposer die. The underfill layer709may comprise a polymer applied to the top surface of the bottom semiconductor die705to which the next level die, e.g., the top semiconductor die701, will be bonded. The polymer may comprise a re-passivation or pre-applied underfill that will flow and bond to both die surfaces negating the need for subsequent underfill processes.

Furthermore, the underfill layer709may be patterned utilizing photolithography techniques or laser ablation to create the wells711thereby exposing the appropriate contact pads707in the bottom semiconductor die705, for example by forming wells in the underfill layer709. The underfill layer709may comprise a film where the openings may comprise full depth pockets or partial depth pockets, for example, generated using laser ablation or photolithography techniques. Material remaining in the partial depth pockets may assist in the bonding process of the top die701to the bottom die705, for example.

The exposed pads may be utilized to align the top semiconductor die701to the bottom semiconductor die705. The die may be bonded utilizing a thermal compression or mass reflow technique, for example. A flux dip may be utilized to aid in wetting of solder from one surface to the other and the underfill may “snap-cure” and seal both to the top and bottom die surfaces. Furthermore, the underfill may flow around and under the microbumps703and the contact pads707during the bond process.

In an example embodiment of the invention, methods are disclosed for a semiconductor device package with a die-to-die first bond. In this regard, aspects of the invention may comprise bonding one or more semiconductor die101,121,203A,203B,405,505,701comprising electronic devices to an interposer die107,201. An underfill material210may be applied between the one or more semiconductor die101,121,203A,203B,405,505,701and the interposer die107,201, and a mold material211may be applied to encapsulate the one or more bonded semiconductor die101,121,203A,203B,405,505,701. The interposer die107,201, and705in instances where the bottom semiconductor die705comprises an interposer die, may be thinned to expose through-silicon-vias (TSVs)115,207. Metal contacts213may be applied to the exposed TSVs115,207and the interposer die107,201, and705in instances where the bottom semiconductor die705comprises an interposer die, with the bonded one or more semiconductor die101,121,203A,203B,405,505,701be bonded may to a packaging substrate103,215.

The bonding of the one or more semiconductor die101,121,203A,203B,405,505,701may comprise: adhering the one or more semiconductor die101,121,203A,203B,405,505,701to an adhesive layer611; and bonding the adhered one or more semiconductor die101,121,203A,203B,405,505,701to the interposer die107,201, and705in instances where the bottom semiconductor die705comprises an interposer die. The one or more semiconductor die101,121,203A,203B,405,505,701may comprise micro-bumps109,205,703for coupling to the interposer die107,201, and705in instances where the bottom semiconductor die705comprises an interposer die, wherein the bonding comprises: positioning the micro-bumps109,205,703in respective wells711in a layer709disposed on the interposer die107,201, and705in instances where the bottom semiconductor die705comprises an interposer die, and bonding the micro-bumps109,205,703to the interposer die107,201, and705in instances where the bottom semiconductor die705comprises an interposer die. The underfill material210may be applied utilizing a capillary underfill process. The one or more semiconductor die may101,121,203A,203B,405,505,701be bonded to the interposer die107,201, and705in instances where the bottom semiconductor die705comprises an interposer die, utilizing a mass reflow process or a thermal compression process.

One or more additional semiconductor die121,701may be bonded to the one or more semiconductor die101,121,203A,203B,405,505,701utilizing a mass reflow process. The one or more additional semiconductor die121,701may be bonded to the one or more semiconductor die101,121,203A,203B,405,505,701utilizing a thermal compression process. The mold material211may comprise a polymer. The bonding of the one or more semiconductor die101,121,203A,203B,405,505,701may comprise: placing the one or more semiconductor die101,121,203A,203B,405,505,701and the interposer die107,201, and705in instances where the bottom semiconductor die705comprises an interposer die, in a fixture401,501that allows the one or more semiconductor die and the interposer die107,201, and705in instances where the bottom semiconductor die705comprises an interposer die, to flex in one direction but not in an opposite direction; and processing the one or more semiconductor die101,121,203A,203B,405,505,701and the interposer die107,201, and705in instances where the bottom semiconductor die705comprises an interposer die, through a reflow process.