Ring oscillators

Ring oscillator circuitry is provided. The ring oscillator circuitry may include a loop of inverters. A control gate may be interposed in the loop to control operation of the loop. The control gate may be activated using a ring oscillator trigger signal. During application of the trigger signal, the trigger signal may become degraded due to circuit parasitics. Trigger signal conditioning circuitry may be used to remove noise from the degraded trigger signal. A version of the trigger signal that has been conditioned by the trigger signal conditioning circuitry may be applied to a control input of the control gate. The trigger signal conditioning circuitry may include a low pass filter, a hysteresis circuit, and a two-stage buffer. The two-stage buffer may be formed from transistors with the same characteristics as the transistors in the inverters of the ring oscillator loop.

BACKGROUND

This invention relates to integrated circuits, and more particularly, to ring oscillator circuits on integrated circuits.

Ring oscillators are used in a variety of circuit applications. For example, circuit designers may use ring oscillator circuits to characterize transistor switching speeds. With this type of approach, a ring oscillator may be fabricated on an otherwise unused portion of an integrated circuit substrate such as in an area of a wafer normally reserved for scribe lines. During manufacturing, the performance of the ring oscillator may be measured. The switching speed of transistors on the integrated circuit can be computed based on the measured ring oscillator frequency. If the switching speed is too low or too high, corrective actions may be taken by modifying the fabrication process. Ring oscillators may also be used in clock circuits and delay-locked-loop-type circuits.

Ring oscillators are formed from a loop of inverters. There may be, for example, hundreds of inverters in a ring oscillator each of which has its output connected to the input of another one of the inverters. In some designs, a NAND gate may be inserted into the loop in place of one of the inverters. One of the NAND gate inputs may be used as an enable input. The ring oscillator may be enabled by asserting a trigger signal on the enable input. When the value of the trigger signal on the enable input is low, the ring oscillator will be turned off and will not oscillate. When the value of the trigger signal on the enable input is high, the ring oscillator will be enabled and will oscillate.

The trigger signals that are used for enabling and disabling ring oscillators in this way are generally produced using off-chip test equipment. As the trigger signals are routed to the enable input of the NAND gate through interconnects, the trigger signals can become degraded. In particular, a square wave trigger signal may pick up undesirable ringing characteristics due to parasitic circuit elements or due to power supply glitches. The spikes or other noise characteristics that are present in a trigger signal that has been degraded in this way may cause a ring oscillator to enter undesirable modes of operation in which higher-order harmonics propagate around the ring. When this happens, the operation of the ring oscillator may be unstable or the output of the ring oscillator may oscillate at an undesired higher-order harmonic frequency rather than at an intended fundamental frequency.

It would therefore be desirable to be able to provide improved integrated circuit ring oscillators.

SUMMARY

In accordance with the present invention, ring oscillator circuitry is provided. The ring oscillator circuitry may be provided on an integrated circuit. A number of inverters may be connected in a loop to form the ring oscillator. A control gate such as a NAND gate may be interposed in the loop of inverters. The control gate may have a control input. A trigger signal may be applied to the control input to enable and disable operation of the ring oscillator.

Trigger signals may be subject to noise. To prevent unwanted noise from disrupting normal operation of the ring oscillator, the ring oscillator circuitry may be provided with trigger signal conditioning circuitry. An otherwise degraded trigger signal may be conditioned by the trigger signal conditioning circuitry to remove voltage spikes and other unwanted noise components.

The trigger signal conditioning circuitry may include a low pass filter, a hysteresis circuit, and a two-stage buffer. The low pass filter may be formed from an inverter or resistor and a capacitor that has been connected between the output of the low pass filter and ground. The hysteresis circuit may have a feedback path. A transistor or inverter may be provided in the feedback path. The two-stage buffer may be formed from transistors that are fabricated to the same specifications as the transistors in the loop of inverters. For example, the gate lengths and widths of the two-stage buffer transistors may be the same as the gate lengths and widths of the transistors in the inverters of the ring oscillator loop.

DETAILED DESCRIPTION

The present invention relates to ring oscillator circuitry. Ring oscillator circuitry may be provided on integrated circuits such as digital signal processors, programmable logic device integrated circuits, microprocessors, application specific integrated circuits, or other integrated circuits.

In some situations, ring oscillators are incorporated into a circuit design. For example, a ring oscillator may be used as part of a clock signal generator. As another example, a ring oscillator may be used in a delay-locked-loop-type circuit. These are merely illustrative examples. Ring oscillator circuits may be used in any suitable integrated circuit application.

In other situations, ring oscillators are used for circuit characterization. In a typical circuit characterization arrangement, ring oscillators are fabricated on a silicon wafer in portions of the wafer that lie between integrated circuit die (i.e., in portions of the wafer that may be normally reserved for scribe lines). The frequency at which the ring oscillators operate provide insight into transistor switching speed. In turn, transistor switching speed measurements may provide insight into semiconductor fabrication process variations. For example, if a ring oscillator exhibits a lower resonance frequency than anticipated, the fabrication process that was used to fabricate the wafer and the integrated circuit structures on the wafer may need to be adjusted accordingly.

A typical ring oscillator may be formed from a series of connected inverters. For example, hundreds of inverters may be connected in a ring so that the output of each inverter feeds into the input of a successive inverter in the ring.

To control operation of the ring oscillator, a two-input NAND gate may be inserted into the ring in place of one of the inverters. One input of the two-input NAND gate may receive the output of a preceding inverter. The other input of the two-input NAND gate may receive an enable signal. The enable signal may be generated by test equipment. In a typical scenario, the test equipment may generate a square-wave trigger signal. The square wave trigger signal may be routed to the input of the NAND gate to control the ring oscillator.

When the trigger signal is low at the NAND gate enable input, the output of the NAND gate will be held high, regardless of the state of the other NAND gate input. A low trigger signal value therefore may be used to disable the ring oscillator.

When the trigger signal is high at the NAND gate enable input, the NAND gate will serve as an inverter. High logic signals that are presented to the other input of the NAND gate will be inverted and corresponding low logic signals will be produced at the NAND gate output. Low logic signals will be inverted to produce high output signals.

To ensure that the ring oscillator operates properly, the trigger signal must be relatively noise free. If the trigger signal is degraded (e.g., due to parasitic circuit elements associated with the interconnects that are used to route the trigger signal to the NAND gate in the ring oscillator), the trigger signal may exhibit ringing.

Noise spikes or other undesirable signal characteristics that are associated with a degraded trigger signal can cause a ring oscillator to exhibit unstable performance. If care is not taken, a noisy trigger signal can cause a ring oscillator to oscillate at an undesirable higher-order harmonic frequency, rather than its intended fundamental frequency. This can cause a circuit that is based on the ring oscillator to operate improperly. Unintended operation of a ring oscillator at higher-order harmonic frequencies may also lead to erroneous characterization measurements in situations in which the ring oscillator's performance is being used to monitor a semiconductor fabrication process.

To avoid these problems, ring oscillator circuitry in accordance with an embodiment of the invention may be provided with trigger signal conditioning circuitry. The trigger signal conditioning circuitry can condition trigger signals before the trigger signals are used to control operation of a ring oscillator. The trigger signal conditioning circuitry helps to ensure proper operation of the ring oscillator.

An illustrative system10in which an integrated circuit has circuitry for conditioning ring oscillator trigger signals is shown inFIG. 1. As shown inFIG. 1, test equipment12may generate a trigger signal TRIGGER. Test equipment12may be based on any suitable test platform. In a typical arrangement, test equipment12may include hardware such as computers and function generators. Test equipment12may also include test software (e.g., software for implementing a test control program). If desired, test signals such as ring oscillator trigger signals may also be generated using on-chip circuitry.

System10may include a substrate11on which one or more ring oscillators such as ring oscillator16have been fabricated. Substrate11may include one or more integrated circuits. For example, substrate11may include an integrated circuit such as a programmable logic device integrated circuit, a microprocessor, a digital signal processor, an application specific integrated circuit, a memory device, or other suitable integrated circuit. Substrate11may be a semiconductor substrate such as a silicon wafer. One or more integrated circuits may be formed on substrate11.

Ring oscillator16may be incorporated within the circuitry of an integrated circuit. For example, ring oscillator16may be formed as part of a clock generator, delay-locked-loop-type circuit, or other suitable circuitry. Ring oscillator16may also be fabricated as a stand-alone test circuit on substrate11. With this type of arrangement, ring oscillator16may be fabricated between integrated circuit die locations (e.g., in the portion of a wafer that is normally reserved for scribe lines).

Ring oscillator16may have a loop of inverters20. There may be any suitable number of inverters20in a given ring oscillator16. For example, there may be tens of inverters20, hundreds of inverters20, or any other suitable number of inverters20. During operation, ring oscillator16oscillates. The output of ring oscillator16may be tapped at one or more locations such as output26. Signals from outputs such as output26may be monitored by test equipment12and/or may be used as inputs to other circuits (e.g., clock circuits, etc.).

In order to control the operation of ring oscillator16, control logic22may be incorporated into the loop of inverters20. Control logic22may be based on any suitable logic circuitry.

With one suitable arrangement, control logic22includes a two-input NAND gate. A first of the two inputs of the NAND gate receives an output signal from a preceding inverter20(i.e., inverter20A inFIG. 1). A second of the two inputs of the NAND gate receives a signal from trigger signal conditioning circuitry18. The output of the NAND gate may be provided to the input of a succeeding inverter20in the loop (i.e., inverter20B inFIG. 1).

When the control signal on the second NAND gate input is low, the output of the NAND gate is held high, regardless of the state of the signal on the first NAND gate input. In this situation, the control signal disables ring oscillator16. When the control signal on the second NAND gate input is high, the NAND gate functions as one of inverters20. When operating in this way, the NAND gate provides signals at its output that are inverted versions of the signals provided on its first input.

The use of a NAND gate as control logic22is merely illustrative. Any suitable control logic circuitry may be used for logic22if desired. In general, control logic22has a signal input that receives the output of inverter20A, a signal output connected to the input of inverter20B, and a control input. The control input receives a control signal. The control signal (e.g., a trigger signal from test equipment12) is used to enable or disable ring oscillator16.

A trigger signal on test equipment output14may be conveyed to the control input of control logic22over path24. Trigger signal conditioning circuitry18may be interposed in path24. At the output of test equipment12, trigger signal TRIGGER may be a relatively low noise square wave, as shown inFIG. 2. In the absence of trigger signal conditioning circuitry18, the trigger signal may degrade (e.g., due to circuit parasitics in path24), so that the version of the trigger signal at the input of control logic22contains voltage spikes or other noise. When operating properly in the absence of noise on the trigger signal at the input of control logic22, ring oscillator16may oscillate at a fundamental frequency and may have an output signal at output26that is characterized by solid line28inFIG. 3.

However, when ring oscillator16is controlled using a degraded trigger signal that contains noise spikes, ring oscillator16may induce ring oscillator16to oscillate at an undesirable higher-order frequency, as illustrated by dashed line30. Higher-order harmonics such as the higher-order harmonic of line30may coexist with fundamental frequency signal28or may replace fundamental frequency signal28. The operation of the circuit in which ring oscillator16is operating and/or characterizing measurements that are being made using output from the ring oscillator may therefore be disrupted.

Trigger signal conditioning circuitry18may be used to ensure that the trigger signal that is applied to the control input of control logic22is relatively free from noise. This ensures proper operation of ring oscillator16.

Any suitable circuit components may be used in trigger signal conditioning circuitry18to reduce noise in the trigger signal. An illustrative configuration for trigger signal conditioning circuitry18is shown inFIG. 4. In the example ofFIG. 4, trigger signal conditioning circuitry18includes low pass filter32, hysteresis circuitry34, and buffer circuitry36. Circuit components such as low pass filter32, hysteresis circuitry34, and buffer circuitry36may be used in any suitable order. For example, the order of hysteresis circuitry34and low pass filter32may be reversed or buffer circuitry36may be placed before low pass filter32or before hysteresis circuitry34. If desired, components such as buffer36, hysteresis circuitry34, and low pass filter32may be selectively omitted. For example, trigger signal conditioning circuitry18may include hysteresis circuitry34without including low pass filter32or trigger signal conditioning circuitry18may include low pass filter32without including hysteresis circuitry34. Moreover, different circuit components may be used in trigger signal conditioning circuitry18if desired. The circuits in trigger signal conditioning circuitry18ofFIG. 4are merely illustrative.

As shown inFIG. 4, a trigger signal TRIGGER may be received at input IN of trigger signal conditioning circuitry18. A corresponding conditioned version of signal TRIGGER may be provided at output OUT of trigger signal conditioning circuitry18. The signal at output OUT may be applied to control input38of control logic22. In the example ofFIG. 4, control logic22has been implemented using a two-input NAND gate. Input40of NAND gate22receives the output from inverter20A. Output42of NAND gate22provides an inverted version of the signal from inverter20A to the input of inverter20B.

In trigger signal conditioning circuitry18of the type shown inFIG. 4, low pass filter32can serve to remove high-frequency noise components from the incoming signal. For example, if the degraded trigger signal includes short noise spikes, low pass filter32may help reduce or remove the noise spikes from the trigger signal. Hysteresis circuitry34can also be used to reduce noise artifacts in the trigger signal.

Buffer36may be used to strengthen and stabilize the trigger signal before the trigger signal is applied to control input38of control logic22. Buffer36may include multiple inverters or other drivers. For example, buffer36may be a two-stage buffer that includes first inverter44and second inverter46. First inverter44and second inverter46may help to precondition the trigger signal. For optimum preconditioning, first inverter44and second inverter46may be implemented using the same design as inverters20. For example, first inverter44and second inverter46may have n-channel and p-channel metal-oxide-semiconductor transistors that have gate lengths and widths that are the same as the gate lengths and widths of the n-channel and p-channel metal-oxide-semiconductor transistors in inverters20. Oxide thicknesses, doping concentrations, and device geometries may also be matched. By fabricating the transistors in inverters44and46so that they match the transistors in inverters20, the beneficial signal preconditioning properties of buffer36may be enhanced.

Illustrative low pass filter circuitry32may be formed using any suitable filtering circuitry. Illustrative examples are provided inFIGS. 5 and 6. In the illustrative arrangement ofFIG. 5, low pass filter32has an input (INPUT) at which unfiltered trigger signals are provided and has an output (OUTPUT) at which corresponding low-pass-filtered versions of the trigger signals are provided. Filter32ofFIG. 5includes an inverter48and a capacitor50that is connected between node N1and ground terminal52. In the illustrative arrangement ofFIG. 6, low pass filter32includes a resistor54and a capacitor50that is connected between node N1and ground terminal52. Resistor54may be, for example, a polysilicon resistor. Capacitor50may be, for example a capacitor structure formed from a metal-oxide-semiconductor transistor structure. If desired, capacitor50may be implemented using a metal-insulator-metal (MIM) capacitor structure.

An illustrative frequency response curve for a low pass filter such as low pass filter32ofFIGS. 5 and 6is shown inFIG. 7. As shown inFIG. 7, input signal components which have relatively low frequencies (e.g., frequencies below cutoff frequency fc) are passed unimpeded from INPUT to OUTPUT. Signal components that have frequencies above cutoff frequency fc are attenuated. At frequencies that are significantly above fc, signals can be strongly attenuated as shown in the graph ofFIG. 7. Voltage spikes that arise on a trigger signal as the trigger signal is conveyed towards control logic22have high-frequency components and may therefore be attenuated significantly by low pass filter32.

This process is illustrated inFIGS. 8,9, and10. An illustrative undegraded trigger signal TRIGGER that may be used to control ring oscillator16is shown inFIG. 8. Signal TRIGGER may, for example, be produced by test equipment12. As shown inFIG. 9, after traveling to the input (INPUT) of low pass filter32, the trigger signal TRIGGER may be degraded. In particular, the trigger signal may contain noise features such as signal spike56ofFIG. 9. After passing through low pass filter32to node N1, the trigger signal is inverted and the magnitude of signal spike56is reduced or eliminated. Dashed line58ofFIG. 10represents an inverted (but unfiltered) version of the degraded trigger signal ofFIG. 9. Solid line60inFIG. 10represents the corresponding filtered output signal OUTPUT that may appear at node N1at the output of low pass filter32. As demonstrated by theFIG. 10example, noise spike56may be removed from the trigger signal by the low pass filter.

Illustrative hysteresis circuitry34is shown inFIG. 11. As shown inFIG. 11, hysteresis circuitry34may have an input66at which degraded trigger signals may be received and may have an output68at which a conditioned (processed) output signal may be provided. Inverter62receives the input signal on line66and provides a corresponding inverted version of this signal to line68. Feedback circuitry64may be coupled between line68and line66. Feedback circuitry64provides circuitry34with hysteresis, so that the point at which output68switches depends on the history of the signal on line66. Because of inverter62, the state of output68is generally an inverted version of input66. However, due to the presence of feedback circuitry64, the state of output68depends not only on the state of input66, but also on the previous state of input66. Accordingly, the input voltages that cause the output of the hysteresis circuit to exhibit a transition in voltage vary depending on whether the input voltage is rising or falling.

Illustrative hysteresis circuits such as circuit34ofFIG. 11are shown inFIGS. 12,13, and14. In the examples ofFIGS. 12,13, and14, the inputs of circuits34are labeled “N1” to indicate that the inputs of the hysteresis circuitry34may optionally be connected to the outputs (“N1”) of low pass filters32such as the low pass filters32ofFIGS. 5 and 6. The outputs of circuits34are labeled “N2.”

In the example ofFIG. 12, feedback path from node N2to node N1is provided by n-channel metal-oxide-semiconductor (NMOS) transistor64A, so arrangements of the type shown inFIG. 12are sometimes referred to as having NMOS transistor feedback arrangements.

In hysteresis circuit34ofFIG. 13, feedback from node N2to node N1is provided by p-channel metal-oxide-semiconductor (PMOS) transistor64B, so arrangements of the type shown inFIG. 13are sometimes referred to as having PMOS transistor feedback arrangements.

Hysteresis circuit34ofFIG. 14has a feedback path in which an inverter64C is coupled between node N2and node N1. Accordingly, hysteresis circuits of the type shown inFIG. 14are sometimes referred to as having inverter-based-feedback arrangements.

In a conventional inverter, there is no feedback circuitry. When no feedback circuitry such as feedback circuitry64is used, the inverter will invert its input signal (Vin) and will produce a corresponding inverted version of the input signal at its output (Vout) without exhibiting hysteresis. The performance of this type of inverter circuit is shown inFIG. 15. (In an actual inverter, the output voltage Vout follows dashed line70ofFIG. 15, but for clarity the transition in the output voltage Vout as a function of input voltage Vin is represented schematically by solid line72inFIG. 15and is similarly represented in the other FIGS.)

As shown inFIG. 15, when input voltage Vin is low, output voltage Vout is high. When input voltage Vin is high, output voltage Vout is low. The output voltage Vout transitions from high to low when the input voltage rises above voltage Vt. The output voltage Vout also transitions from low to high when the input voltage falls below voltage Vt. Because there is no difference in the point at which the output transitions based on the direction of the input signal transition, the behavior ofFIG. 15is said not to exhibit hysteresis.

In the NMOS feedback arrangement ofFIG. 16, output voltage Vout transitions at Vt when input voltage Vin rises from low to high and transitions at Vtl when input voltage Vin falls from high to low.

In the PMOS feedback arrangement ofFIG. 17, output voltage Vout transitions at Vth when input voltage Vin rises from low to high and transitions at Vt when input voltage Vin falls from high to low.

In the inverter feedback arrangement ofFIG. 18, output voltage Vout transitions at Vth when input voltage Vin rises from low to high and transitions at Vtl when input voltage Vin falls from high to low. The inverter that is provided in the feedback path may be, for example, an inverter formed from PMOS and NMOS transistors connected in series between a positive power supply voltage and ground.

The NMOS-type feedback, PMOS-type feedback, and inverter-type feedback arrangements may have any suitable input voltage transition thresholds (Vtl, Vt, and Vth). For example, if a logic high value in system10is represented by a positive power supply voltage Vcc of 1.0 volts, voltage Vt might be 0.5 volts, voltage Vtl might be 0.3 volts, and voltage Vtl might be 0.7 volts (as examples). This is, however, merely illustrative. Other suitable transition voltages may be associated with the NMOS, PMOS, and inverter-based feedback hysteresis circuits if desired. The use of these values is described herein only as an example.

In general, any suitable feedback arrangement may be used in hysteresis circuit34and any suitable values may be used for the transition threshold voltages. In some scenarios, the output voltages that result from a given input signal will be similar or identical. In other scenarios, hysteresis circuitry of different types may produce different results. These potential differences are illustrated in the examples ofFIGS. 19-33.

An illustrative degraded trigger signal that may be presented to the input of hysteresis circuit34is shown inFIG. 19.

FIG. 20is an illustrative inverter output signal that may be produced by a circuit without hysteresis when processing a degraded trigger signal such as the degraded trigger signal ofFIG. 19. As shown inFIG. 20, the output signal will transition up and down at times t1and t2, before stabilizing at time t3. Because there is no hysteresis in theFIG. 20scenario, the output of the inverter has not been smoothed by the hysteresis circuit. Accordingly, the noise that is present in the degraded trigger signal ofFIG. 19results in a noisy output signal.

FIG. 21shows an illustrative output signal that may be produced by a hysteresis circuit34that has a hysteresis characteristic of the type shown inFIG. 16when processing a degraded trigger signal such as the degraded trigger signal ofFIG. 19. Because the output signal only transitions from low to high when the input signal (i.e., the voltage on node N1) falls below threshold voltage Vtl, the corresponding signal on output node N2of the hysteresis circuit34is not sensitive to the noise in the degraded trigger signal. Accordingly, the node N2voltage shown inFIG. 21does not transition back and forth as with the signal ofFIG. 20.

FIG. 22shows an illustrative output signal that may be produced by a hysteresis circuit34that has a hysteresis characteristic of the type shown inFIG. 17when presented with the degraded trigger signal ofFIG. 19at its input. In this scenario, the signal N2goes high once input signal N1falls below Vt, but does not transition back and forth as with theFIG. 20scenario, because high-to-low transitions in the output signal only occur when input signal N1rises above Vth.

FIG. 23shows an illustrative output signal that may be produced by a hysteresis circuit34that has a hysteresis characteristic of the type shown inFIG. 18when presented with the degraded trigger signal ofFIG. 19. As shown inFIG. 23, output signal N2will transition from low to high when input voltage N1falls below threshold voltage Vtl.

In the illustrative scenario ofFIGS. 19-23, all three types of hysteresis circuit34effectively converted the noisy degraded trigger signal on node N1into a clean trigger signal on node N2(unlike the hysteresis-free circuit ofFIG. 20). In some situations (e.g., with particularly noisy degraded trigger signals), some of the hysteresis circuits may be more effective than others. When the degraded trigger signal exhibits large variations in voltage, it may be advantageous to use a hysteresis circuit in which there is a relatively large spread between the low and high input voltage thresholds. In the present example, the hysteresis circuit that has the inverter-based feedback arrangement has the largest threshold voltage spread (Vth to Vtl), so this hysteresis circuit is able to eliminate trigger signal noise features that would not be removed by the hysteresis circuits with the NMOS transistor feedback and PMOS transistor feedback configurations.

FIGS. 24-28illustrate a scenario in which a hysteresis circuit with hysteresis characteristics of the type set forth inFIG. 17(e.g., a PMOS-transistor-feedback hysteresis circuit) can fail.

An illustrative degraded trigger signal that may be presented to the input of a hysteresis circuit in this type of scenario is shown inFIG. 24.

FIG. 25shows an illustrative inverter output signal that may be produced by a circuit without hysteresis when presented with the degraded trigger signal ofFIG. 24.

An output signal of the type that may be produced by a hysteresis circuit34having a hysteresis characteristic of the type shown inFIG. 16when presented with the degraded trigger signal ofFIG. 24is shown inFIG. 26. This hysteresis circuit34successfully removes the noise spike shown inFIG. 24.

FIG. 27shows an illustrative output signal that may be produced by a hysteresis circuit that has a hysteresis characteristic of the type shown inFIG. 17when presented with the degraded trigger signal ofFIG. 24. As shown inFIG. 27, this type of hysteresis circuit was not entirely successful at removing the noise associated with the degraded trigger signal ofFIG. 24.

FIG. 28shows an illustrative output signal that may be produced by a hysteresis circuit34that has a hysteresis characteristic of the type shown inFIG. 18when presented with a degraded trigger signal at its input such as the degraded trigger signal ofFIG. 24. As with the example ofFIG. 26, this hysteresis circuit34successfully removes the noise spike shown inFIG. 24.

FIGS. 29-33illustrate a scenario in which a hysteresis circuit with hysteresis characteristics of the type set forth inFIG. 16(e.g., an NMOS-transistor-feedback hysteresis circuit) can fail.

An illustrative degraded trigger signal is shown inFIG. 29. As shown inFIG. 29, the degraded trigger signal has a noise feature that may induce higher-order frequency oscillations to arise in ring oscillator16if not suppressed.

FIG. 30shows how an inverter without hysteresis would respond when processing the signal ofFIG. 29. This type of circuit does not filter out the noise spike in the degraded trigger signal.

FIG. 31shows an illustrative output signal that may be produced by a hysteresis circuit34that has a hysteresis characteristic of the type shown inFIG. 16when presented with the degraded trigger signal ofFIG. 29. As shown inFIG. 31, this type of hysteresis circuit is not able to remove all noise features from the degraded trigger signal.

FIG. 32shows an illustrative output signal that may be produced by a hysteresis circuit34that has a hysteresis characteristic of the type shown inFIG. 17when presented with a degraded trigger signal at its input such as the degraded trigger signal ofFIG. 29. As shown inFIG. 32, this type of hysteresis circuit may be effective at removing noise from the degraded trigger signal.

FIG. 33shows an illustrative output signal that may be produced by a hysteresis circuit34that has a hysteresis characteristic of the type shown inFIG. 18when presented with a degraded trigger signal at its input such as the degraded trigger signal ofFIG. 29. As with the circuit described in connection withFIG. 32, this type of hysteresis circuit may be effective at removing noise from the degraded trigger signal.

As the examples ofFIGS. 19-33demonstrate, various types of hysteresis circuit may be used to filter noise from a degraded trigger signal before that signal is used to control the control logic in a ring oscillator such as ring oscillator16. The effectiveness of the different types of hysteresis circuits varies depending on the input voltage thresholds (Vtl, Vt, and Vth) that are associated with each hysteresis circuit. Certain circuit configurations may be better than others at removing noise features from degraded trigger signals, particularly when large amounts of noise are present. In general, however, the selection of which type of feedback circuit is to be used in a given hysteresis circuit and the values for the input voltage threshold voltages should be chosen to accommodate the amount of noise filtering that is expected for a given application. When it is expected that the trigger signal will pick up significant amounts of noise, it may be advantageous to use a hysteresis circuit with a relatively wide range of input voltage threshold values.

An illustrative circuit arrangement that may be used for implementing trigger signal conditioning circuit18is shown inFIG. 34. As shown inFIG. 34, low pass filter32may be implemented using an inverter formed from transistors T1and T2and using a capacitor C1. Capacitor C1may be formed from an MIM capacitor structure or (as shown inFIG. 34) may be formed from a metal-oxide-semiconductor (MOS) transistor structure.

Hysteresis circuit34in theFIG. 34embodiment has an inverter formed from transistors T3and T4and has an NMOS feedback transistor T5that provides feedback from output node N2to input node N1.

Transistors T6and T7may form a first inverter. Transistors T8and T9may form a second inverter. The first and second inverters may be used to form two-stage buffer36.