SWITCH-MODE POWER CONVERTERS WITH CONTROL OF TURNING ON AND OFF ONE TRANSISTOR BEFORE TURNING ON ANOTHER TRANSISTOR

Controller and method for a power converter. For example, a controller for a power converter includes: a first drive signal generator configured to generate a first drive signal to turn off a first transistor at a first time and turn on the first transistor at a second time, the first transistor being configured to receive an input voltage and related to a primary winding coupled to an auxiliary winding and a secondary winding, the secondary winding being related to an output voltage, the second time being later than the first time; a second drive signal generator configured to: generate a second drive signal to turn on a second transistor at a third time, the second transistor being coupled to the first transistor and related to the primary winding, the third time being later than the first time and being earlier than the second time.

1. CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 202310246278.6, filed Mar. 14, 2023, and Chinese Patent Application No. 202310245305.8, filed Mar. 14, 2023, both of these applications being incorporated by reference herein for all purposes.

2. FIELD OF THE DISCLOSURE

Certain embodiments of the present disclosure are directed to circuits. More particularly, some embodiments of the disclosure provide controllers and methods for control of turning on and off one transistor before turning on another transistor. Merely by way of example, some embodiments of the disclosure have been applied to asymmetrical half-bridge flyback switch-mode power converters. But it would be recognized that the disclosure has a much broader range of applicability.

3. BACKGROUND OF THE DISCLOSURE

The power converters can convert electric power from one form to another form. As an example, the electric power is transformed from alternate current (AC) to direct current (DC), from DC to AC, from AC to AC, or from DC to DC. Additionally, the power converters can convert the electric power from one voltage level to another voltage level. The power converters include linear converters and switch-mode converters. The switch-mode converters often are implemented with various architectures, such as the fly-back architecture, the buck architecture, and/or the boost architecture.

FIG.1is a simplified diagram showing a conventional asymmetrical half-bridge flyback switch-mode power converter. The asymmetrical half-bridge fly back switch-mode power converter100includes a primary winding110, a secondary winding112, transistors120and130, a bridge rectifier140, a diode142, a resistor144, and capacitors150,152and154. In some examples, each transistor of the transistors120and130is a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, the transistor120includes a drain terminal122, a gate terminal124, and a source terminal126, and the transistor130) includes a drain terminal132, a gate terminal134, and a source terminal136. As an example, the capacitor152includes capacitor terminals156and158, and the diode142includes an anode146and a cathode148.

As shown inFIG.1, in an equivalent circuit, the primary winding110includes an inductor116with a primary inductance Lp, and the primary winding110also includes an inductor118with a leakage inductance Lr. If a current117(e.g., ILm) flows from the capacitor terminal158to the primary winding110, the current117has a positive value, and if the current117(e.g., ILm) flows from the primary winding110to the capacitor terminal158, the current117has a negative value. The asymmetrical half-bridge fly back switch-mode power converter100receives an AC voltage190and generates an output voltage192. The gate terminal124receives a drive voltage125, and the gate terminal134receives a drive voltage135. The source terminal126of the transistor120and the drain terminal132of the transistor130are connected to the capacitor terminal156(e.g., Cr) of the capacitor152and biased to a voltage127(e.g., HB). The voltage127(e.g., HB) is the source voltage of the transistor120and the drain voltage of the transistor130. The capacitor terminal158is connected to the primary winding110. If a current153(e.g., ILr) flows to the capacitor terminal156, the current153has a positive value, and if the current153(e.g., ILr) flows from the capacitor terminal156, the current153has a negative value. Additionally, the anode146is connected to the secondary winding112. If a current143(e.g., IDo) flows to the anode146, the current143has a positive value, and if the current143(e.g., IDo) flows from the anode146, the current143has a negative value. Also, the drain terminal122of the transistor120receives a voltage151, and the source terminal136of the transistor130is biased to a ground voltage (e.g., 0) volts).

The asymmetrical half-bridge fly back switch-mode power converter100operates in a critical conduction mode (CRM) under a heavy load condition, and the asymmetrical half-bridge fly back switch-mode power converter100operates in a discontinuous conduction mode (DCM) under a light load condition. For example, the asymmetrical half-bridge flyback switch-mode power converter100operates in a cyclical manner, wherein each cycle of the discontinuous conduction mode (DCM) is followed by M cycles of the critical conduction mode (CRM) before another cycle of the discontinuous conduction mode (DCM), wherein M is a constant positive integer. As an example, the asymmetrical half-bridge flyback switch-mode power converter100operates continuously in the discontinuous conduction mode (DCM).

In some examples, through the resonance of the capacitor152(e.g., Cr), an inductor116(e.g., with the primary inductance Lp), and the inductor118(e.g., with the leakage inductance Lr), the transistor120(e.g., Q1) achieves low-voltage switching and/or zero-voltage switching. In certain examples, through the resonance of the capacitor152(e.g., Cr), the inductor116(e.g., with the primary inductance Lp), and the inductor118(e.g., with the leakage inductance Lr), the transistor130(e.g., Q2) achieves low-voltage switching and/or zero-voltage switching.

FIG.2shows simplified timing diagrams for the conventional asymmetrical half-bridge fly back switch-mode power converter100as shown inFIG.1in the critical conduction mode (CRM). The waveform225represents the drive voltage125as a function of time, the waveform235represents the drive voltage135as a function of time, the waveform217represents the current117as a function of time, the waveform253represents the current153as a function of time, the waveform243represents the current143as a function of time, and the waveform227represents the voltage127as a function of time.

At time t0, the drive voltage125changes from a logic low level to a logic high level as shown by the waveform225, and the transistor120becomes turned on. From time to to time t1, the drive voltage125remains at the logic high level as shown by the waveform225, and the transistor120remains turned on. For example, from time t0to time t1, the current153increases with time, as shown by the waveform253. As an example, during time to and time t1, after the current153becomes positive, the current153flows to the capacitor terminal156, and the voltage151charges the primary winding110through the capacitor152.

At time t1, the drive voltage125changes from the logic high level to the logic low level as shown by the waveform225, and the transistor120becomes turned off. For example, at time t1, the voltage151stops charging the primary winding110. As an example, at time t1, the current153reaches a current value254(e.g., Ip), wherein the current value254is positive.

From time t1to time t2, the current153(e.g., ILr) is used to charge the parasitic capacitor of the transistor120and discharge the parasitic capacitor of the transistor130, and the voltage127decreases with time as shown by the waveform227.

At time t2, the drive voltage135changes from the logic low level to the logic high level as shown by the waveform235, and the transistor130becomes turned on. For example, at time t2, the voltage127decreases to zero volts. As an example, at time t2, the transistor130becomes turned on with low-voltage switching and/or zero-voltage switching.

From time t2to time t3, the drive voltage135remains at the logic high level as shown by the waveform235, and the transistor130remains turned on. In some examples, from time t2to time t3, the current143(e.g., IDo) has a positive value as shown by the waveform243. For example, from time t2to time t3, through the resonance of the capacitor152and the inductor118(e.g., with the leakage inductance Lr), the current153(e.g., ILr) decreases to zero and then becomes negative as shown by the waveform253. As an example, from time t2to time t3, the current117(e.g., ILm) decreases linearly with time as shown by the waveform217. At time t3, the current117(e.g., ILm) becomes equal to the current153(e.g., ILr) as shown by the waveforms217and253. As an example, at time t3, the current143(e.g., IDo) becomes equal to zero as shown by the waveform243. From time t3to time t4, the drive voltage135remains at the logic high level as shown by the waveform235, and the transistor130remains turned on. For example, from time t3to time t4, the capacitor152discharges through the transistor130, and the current153flows from the capacitor terminal156. As an example, from time t3to time t4, the current153has a negative value that decreases with time as shown by the waveform253.

At time t4, the drive voltage135changes from the logic high level to the logic low level as shown by the waveform235, and the transistor130becomes turned off. For example, at time t4, the capacitor152stops discharging. As an example, at time t4, the current153reaches a current value255(e.g., In), wherein the current value255is negative.

From time t4to time t5, the current153(e.g., ILr) is used to discharge the parasitic capacitor of the transistor120and charge the parasitic capacitor of the transistor130, and the voltage127increases with time as shown by the waveform227. For example, from time t4to time t5, the current153flows from the capacitor terminal156. As an example, from time t4to time t5, the current153has a negative value that increases with time as shown by the waveform253.

At time t5, the drive voltage125changes from the logic low level to the logic high level as shown by the waveform225, and the transistor120becomes turned on. For example, at time t5, the voltage127becomes equal to the voltage151as shown by the waveform227. As an example, at time t5, the transistor120becomes turned on with low-voltage switching and/or zero-voltage switching.

FIG.3shows simplified timing diagrams for the conventional asymmetrical half-bridge fly back switch-mode power converter100as shown inFIG.1in the discontinuous conduction mode (DCM). The waveform425represents the drive voltage125as a function of time, the waveform435represents the drive voltage135as a function of time, the waveform417represents the current117as a function of time, the waveform453represents the current153as a function of time, the waveform443represents the current143as a function of time, and the waveform427represents the voltage127as a function of time.

At time t10, the drive voltage125changes from a logic low level to a logic high level as shown by the waveform425, and the transistor120becomes turned on. From time t10to time t11, the drive voltage125remains at the logic high level as shown by the waveform425, and the transistor120remains turned on. For example, from time t10to time t11, the current153increases with time, as shown by the waveform453. As an example, during time t10and time t11, after the current153becomes positive, the current153flows to the capacitor terminal156, and the voltage151charges the primary winding110through the capacitor152.

At time t11, the drive voltage125changes from the logic high level to the logic low level as shown by the waveform425, and the transistor120becomes turned off. For example, at time t11, the voltage151stops charging the primary winding110. As an example, at time t11, the current153reaches a current value454(e.g., Ip), wherein the current value454is positive.

From time t11to time t12, the current153(e.g., ILr) is used to charge the parasitic capacitor of the transistor120and discharge the parasitic capacitor of the transistor130, and the voltage127decreases with time as shown by the waveform427.

At time t12, the drive voltage135changes from the logic low level to the logic high level as shown by the waveform435, and the transistor130becomes turned on. For example, at time t12, the voltage127decreases to zero volts. As an example, at time t12, the transistor130becomes turned on with low-voltage switching and/or zero-voltage switching.

From time t12to time t13, the drive voltage135remains at the logic high level as shown by the waveform435, and the transistor130remains turned on. In some examples, from time t12to time t13, the current143(e.g., IDo) has a positive value as shown by the waveform443. For example, from time t12to time t13, through the resonance of the capacitor152and the inductor118(e.g., with the leakage inductance Lr), the current153(e.g., ILr) decreases to zero and then becomes negative as shown by the waveform453. As an example, from time t12to time t13, the current117(e.g., ILm) decreases linearly with time as shown by the waveform417.

At time t13, the drive voltage135changes from the logic high level to the logic low level as shown by the waveform435, and the transistor130becomes turned off. The length of time duration from time t12to time t13is a predetermined constant for the asymmetrical half-bridge fly back switch-mode power converter100as shown inFIG.1. The current117(e.g., ILm) at time t13depends at least in part on the predetermined constant that is used as the length of time duration from time t12to time t13, and the current117(e.g., ILm) at time t13is either equal to zero or is not equal to zero as shown by the waveform417.

From time t13to time t14, the resonance of the parasitic capacitor of the transistor120, the parasitic capacitor of the transistor130, the inductor116(e.g., with the primary inductance Lp), and the inductor118(e.g., with the leakage inductance Lr) occurs. For example, through this resonance, the voltage127oscillates and reaches the voltage151. As an example, through this resonance, the voltage127oscillates without reaching the voltage151.

At time t14, the drive voltage135changes from the logic low level to the logic high level as shown by the waveform435, and the transistor130becomes turned on. From time t14to time tis, the drive voltage135remains at the logic high level as shown by the waveform435, and the transistor130remains turned on. In some examples, from time t14to time t15, the capacitor152is discharged through the transistor130, and the current153(e.g., ILr) flows from the capacitor terminal156. In certain examples, from time t14to time tis, the current153(e.g., ILr) has a negative value, and decreases with time as shown by the waveform453.

At time t15, the drive voltage135changes from the logic high level to the logic low level as shown by the waveform435, and the transistor130becomes turned off. For example, at time t15, the current153reaches a current value455(e.g., In_zvs), wherein the current value455is negative.

From time tis to time t16, through the resonance of the parasitic capacitor of the transistor120, the parasitic capacitor of the transistor130, the inductor116(e.g., with the primary inductance Lp), and the inductor118(e.g., with the leakage inductance Lr), the current153(e.g., ILr) is used to discharge the parasitic capacitor of the transistor120and charge the parasitic capacitor of the transistor130, and the voltage127increases with time as shown by the waveform427.

At time t16, the drive voltage125changes from the logic low level to the logic high level as shown by the waveform425, and the transistor120becomes turned on. For example, at time t16, the voltage127becomes equal to the voltage151as shown by the waveform427. As an example, at time t16, the transistor120becomes turned on with low-voltage switching and/or zero-voltage switching.

Hence it is highly desirable to improve the technique for switch-mode power converters.

4. BRIEF SUMMARY OF THE DISCLOSURE

Certain embodiments of the present disclosure are directed to circuits. More particularly, some embodiments of the disclosure provide controllers and methods for control of turning on and off one transistor before turning on another transistor. Merely by way of example, some embodiments of the disclosure have been applied to asymmetrical half-bridge flyback switch-mode power converters. But it would be recognized that the disclosure has a much broader range of applicability.

According to certain embodiments, a controller for a power converter includes: a first drive signal generator configured to generate a first drive signal to turn off a first transistor at a first time and turn on the first transistor at a second time, the first transistor being configured to receive an input voltage and related to a primary winding coupled to an auxiliary winding and a secondary winding, the secondary winding being related to an output voltage, the second time being later than the first time: a second drive signal generator configured to: generate a second drive signal to turn on a second transistor at a third time, the second transistor being coupled to the first transistor and related to the primary winding, the third time being later than the first time and being earlier than the second time: change the second drive signal to turn off the second transistor at a fourth time, the fourth time being later than the third time and being earlier than the second time; and change the second drive signal to turn on the second transistor at a fifth time, the fifth time being later than the fourth time and being earlier than the second time: a first controller configured to generate a first control signal based at least in part on a first voltage related to the auxiliary winding and output the first control signal to the second drive signal generator: wherein the second drive signal generator is further configured to: in response to the first control signal changing from a first logic level to a second logic level, change the second drive signal to turn off the second transistor at a sixth time, the sixth time being later than the fifth time and being earlier than the second time.

According to some embodiments, a controller for a power converter includes: a first drive signal generator configured to generate a first drive signal to turn off a first transistor at a first time and turn on the first transistor at a second time, the first transistor being configured to receive an input voltage and related to a primary winding coupled to an auxiliary winding and a secondary winding, the secondary winding being related to an output voltage, the second time being later than the first time: a second drive signal generator configured to generate a second drive signal to turn on a second transistor at a third time and turn off the second transistor at a fourth time, the second transistor being coupled to the first transistor and related to the primary winding, the third time being later than the first time, the fourth time being later than the third time and being earlier than the second time: an enablement controller configured to generate an enablement control signal based at least in part on a first voltage related to the auxiliary winding and output the enablement control signal to the second drive signal generator; and a first controller configured to generate a first control signal based at least in part on a second voltage related to the output voltage and output the first control signal to the second drive signal generator: wherein the second drive signal generator is further configured to; in response to the first control signal changing from a first logic level to a second logic level when the enablement control signal is at a third logic level, change the second drive signal to turn on the second transistor at a fifth time, the fifth time being later than the fourth time and being earlier than the second time; and in response to the first control signal changing from the first logic level to the second logic level when the enablement control signal is at a fourth logic level, not change the second drive signal so that the second transistor remains being turned off from the fourth time to the second time; wherein: the first logic level and the second logic level are different; and the third logic level and the fourth logic level are different.

According to certain embodiments, a method for a power converter includes: generating a first drive signal to turn off a first transistor at a first time, the first transistor being configured to receive an input voltage and related to a primary winding coupled to an auxiliary winding and a secondary winding, the secondary winding being related to an output voltage: changing the first drive signal to turn on the first transistor at a second time, the second time being later than the first time: generating a second drive signal to turn on a second transistor at a third time, the second transistor being coupled to the first transistor and related to the primary winding, the third time being later than the first time and being earlier than the second time; changing the second drive signal to turn off the second transistor at a fourth time, the fourth time being later than the third time and being earlier than the second time; changing the second drive signal to turn on the second transistor at a fifth time, the fifth time being later than the fourth time and being earlier than the second time: generating a first control signal based at least in part on a first voltage related to the auxiliary winding; and in response to the first control signal changing from a first logic level to a second logic level, changing the second drive signal to turn off the second transistor at a sixth time, the sixth time being later than the fifth time and being earlier than the second time.

According to some embodiments, a method for a power converter includes: generating a first drive signal to turn off a first transistor at a first time, the first transistor being configured to receive an input voltage and related to a primary winding coupled to an auxiliary winding and a secondary winding, the secondary winding being related to an output voltage; changing the first drive signal to turn on the first transistor at a second time, the second time being later than the first time: generating a second drive signal to turn on a second transistor at a third time, the second transistor being coupled to the first transistor and related to the primary winding, the third time being later than the first time and being earlier than the second time: changing the second drive signal to turn off the second transistor at a fourth time, the fourth time being later than the third time and being earlier than the second time; generating an enablement control signal based at least in part on a first voltage related to the auxiliary winding: generating a first control signal based at least in part on a second voltage related to the output voltage; in response to the first control signal changing from a first logic level to a second logic level when the enablement control signal is at a third logic level, changing the second drive signal to turn on the second transistor at a fifth time, the fifth time being later than the fourth time and being earlier than the second time; and in response to the first control signal changing from the first logic level to the second logic level when the enablement control signal is at a fourth logic level, not changing the second drive signal so that the second transistor remains being turned off from the fourth time to the second time; wherein: the first logic level and the second logic level are different; and the third logic level and the fourth logic level are different.

Depending upon embodiment, one or more benefits may be achieved. These benefits and various additional objects, features and advantages of the present disclosure can be fully appreciated with reference to the detailed description and accompanying drawings that follow.

6. DETAILED DESCRIPTION OF THE DISCLOSURE

Certain embodiments of the present disclosure are directed to circuits. More particularly, some embodiments of the disclosure provide controllers and methods for control of turning on and off one transistor before turning on another transistor. Merely by way of example, some embodiments of the disclosure have been applied to asymmetrical half-bridge fly back switch-mode power converters. But it would be recognized that the disclosure has a much broader range of applicability.

As shown inFIG.3, when the conventional asymmetrical half-bridge fly back switch-mode power converter100operates in the discontinuous conduction mode (DCM), whether the voltage127becomes equal to zero volts and the transistor130realizes low-voltage switching and/or zero-voltage switching at time t12depends on the current value454(e.g., Ip) of the current153(e.g., ILr) at time t11when the transistor120becomes turned off according to certain embodiments. For example, if the current value454(e.g., Ip) is sufficiently large, the voltage127decrease to zero volts and the transistor130becomes turned on with low-voltage switching and/or zero-voltage switching at time t12.

Also as shown inFIG.3, when the conventional asymmetrical half-bridge fly back switch-mode power converter100operates in the discontinuous conduction mode (DCM), whether the voltage127becomes equal to the voltage151and the transistor120realizes low-voltage switching and/or zero-voltage switching at time t16depends on the current value455(e.g., In_zvs) of the current153(e.g., ILr) at time tis when the transistor130becomes turned off according to some embodiments. In certain examples, the current value455(e.g., In_zvs) is determined at least in part by the time duration (e.g., Tzvs) from time t14to time t15. For example, if the time duration (e.g., Tzvs) from time t14to time t15is too short, the magnitude of the current value455(e.g., In_zvs) would be too small, so the energy for the resonance of the parasitic capacitor of the transistor120, the parasitic capacitor of the transistor130, the inductor116(e.g., with the primary inductance Lp), and the inductor118(e.g., with the leakage inductance Lr) from time tis to time t16would be too low; causing the voltage127not able to reach the voltage151and the transistor120not able to become turned on with low-voltage switching and/or zero-voltage switching at time t16. As an example, if the time duration (e.g., Tzvs) from time t14to time tis is too long, the magnitude of the current value455(e.g., In_zvs) would be too large, so the energy for the resonance of the parasitic capacitor of the transistor120, the parasitic capacitor of the transistor130, the inductor116(e.g., with the primary inductance Lp), and the inductor118(e.g., with the leakage inductance Lr) from time t15to time t16would be more than enough for the voltage127to reach the voltage151and the transistor120to become turned on with low-voltage switching and/or zero-voltage switching at time t16.

In some examples, if the energy for the resonance of the parasitic capacitor of the transistor120, the parasitic capacitor of the transistor130, the inductor116(e.g., with the primary inductance Lp), and the inductor118(e.g., with the leakage inductance Lr) from time t15to time t16is more than enough for the voltage127to reach the voltage151and for the transistor120to become turned on with low-voltage switching and/or zero-voltage switching, the large resonance energy can cause larger energy loss during the resonance process. In certain examples, if the energy for the resonance of the parasitic capacitor of the transistor120, the parasitic capacitor of the transistor130, the inductor116(e.g., with the primary inductance Lp), and the inductor118(e.g., with the leakage inductance Lr) from time tis to time t16is more than enough for the voltage127to reach the voltage151and for the transistor120to become turned on with low-voltage switching and/or zero-voltage switching, the larger magnitude of the current value455(e.g., In_zvs) needs the magnitude of the current value454(e.g., Ip) to also become larger in order to generate a constant output current for the conventional asymmetrical half-bridge fly back switch-mode power converter100, causing the energy loss becomes larger when the transistor120becomes turned off.

In certain embodiments, when the conventional asymmetrical half-bridge fly back switch-mode power converter100operates in the discontinuous conduction mode (DCM), if the time duration (e.g., Tzvs) from time t14to time t15is too short, the transistor120is not able to become turned on with low-voltage switching and/or zero-voltage switching; if the time duration (e.g., Tzvs) from time t14to time tis is too long, the transistor120is able to become turned on with low-voltage switching and/or zero-voltage switching, but the energy loss becomes larger. In some embodiments, when the conventional asymmetrical half-bridge fly back switch-mode power converter100operates in the discontinuous conduction mode (DCM), the time duration (e.g., Tzvs) from time t14to time tis needs to be controlled to be just long enough for the transistor120to become turned on with low-voltage switching and/or zero-voltage switching.

FIG.4is a simplified diagram showing an asymmetrical half-bridge fly back switch-mode power converter according to certain embodiments of the present disclosure. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The asymmetrical half-bridge flyback switch-mode power converter300includes a primary winding310, a secondary winding312, an auxiliary winding314, transistors320and330, a bridge rectifier340, a diode342, a resistor344, capacitors350,352and354, resistors360,362,364,366,368and370, capacitors372,374and376, a shunt regulator380) (e.g., TL431), an optocoupler382, and a controller900. The controller900includes a comparator910, a drive voltage generator920, a mode and/or frequency controller930, a turning-off controller940, a control signal generator950, a turning-on enablement controller960, a dead-time controller970, a drive voltage generator980, a diode992, and resistors994and996. In some examples, each transistor of the transistors320and330) is a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, the transistor320includes a drain terminal322, a gate terminal324, and a source terminal326, and the transistor330includes a drain terminal332, a gate terminal334, and a source terminal336. As an example, the capacitor352(e.g., Cr) includes capacitor terminals356and358, and the diode342includes an anode346and a cathode348. In certain examples, the primary winding310, the secondary winding312, and the auxiliary winding314are coupled to each other as parts of a transformer. Although the above has been shown using a selected group of components for the asymmetrical half-bridge flyback switch-mode power converter, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

As shown inFIG.4, in an equivalent circuit, the primary winding310includes an inductor316with a primary inductance Lp, and the primary winding310also includes an inductor318with a leakage inductance Lraccording to some embodiments. For example, if a current317(e.g., ILm) flows from the capacitor terminal358to the primary winding310, the current317has a positive value. As an example, if the current317(e.g., ILm) flows from the primary winding310to the capacitor terminal358, the current317has a negative value. In certain examples, the controller900includes a controller902for the transistor320and a controller904for the transistor330. For example, the controller902for the transistor320) includes the comparator910, the drive voltage generator920, and the dead-time controller970. As an example, the controller904for the transistor330includes the mode and/or frequency controller930, the turning-off controller940, the control signal generator950, the turning-on enablement controller960, the drive voltage generator980, the diode992, and the resistors994and996.

According to certain embodiments, the asymmetrical half-bridge flyback switch-mode power converter300receives an AC voltage390and generates an output voltage392according to some embodiments. For example, the gate terminal324receives a drive voltage325(e.g., a drive signal), and the gate terminal334receives a drive voltage335(e.g., a drive signal). As an example, the source terminal326of the transistor320and the drain terminal332of the transistor330are connected to the capacitor terminal356of the capacitor352and biased to a voltage327. For example, the voltage327(e.g., HB) is the source voltage of the transistor320and the drain voltage of the transistor330. In certain examples, the capacitor terminal358is connected to the primary winding310. For example, if a current353flows to the capacitor terminal356, the current353has a positive value, and if the current353flows from the capacitor terminal356, the current353has a negative value. In some examples, the anode346is connected to the secondary winding312. For example, if a current343flows to the anode346, the current343has a positive value, and if the current343flows from the anode346, the current343has a negative value. As an example, the drain terminal322of the transistor320receives a voltage351(e.g., an input voltage), and the source terminal336of the transistor330is biased to a ground voltage (e.g., 0 volts).

In some embodiments, the controller900receives a feedback voltage377and a current sensing voltage345and generate the drive voltage325based at least in part on the feedback voltage377and the current sensing voltage345. For example, the drive voltage325is used to turn on and/or turn off the transistor320. In certain examples, the feedback voltage377represents the output voltage392, and the current sensing voltage345represents the current353. In some examples, the drive voltage generator920(e.g., a drive signal generator) receives a turning-off control signal911(e.g., CV_off) and a turning-on control signal971(e.g., up_on) and generates the drive voltage325(e.g., a drive signal) based at least in part on the turning-off control signal911(e.g., CV_off) and the turning-on control signal971(e.g., up_on) to turn on and/or turn off the transistor320. For example, in response to the turning-off control signal911(e.g., CV_off) changing from a logic low level to a logic high level, the drive voltage generator920changes the drive voltage325from a logic high level to a logic low level in order to turn off the transistor320. As an example, in response to the turning-on control signal971(e.g., up_on) changing from a logic low level to a logic high level, the drive voltage generator920changes the drive voltage325from a logic low level to a logic high level in order to turn on the transistor320.

In certain embodiments, the controller900also receives a voltage361and generates the drive voltage335based at least in part on the feedback voltage377and the voltage361. As an example, the drive voltage335is used to turn on and/or turn off the transistor330. In some examples, the voltage361represents a voltage315of the auxiliary winding314. For example, one terminal of the resistor360and one terminal of the resistor362are connected to each other and are both biased to the voltage361. As shown inFIG.4, the drive voltage generator980(e.g., a drive signal generator) receives a mode and/or frequency control signal931(e.g., DCM_on), a turning-off control signal943(e.g., ZVS_off), a turning-off control signal951(e.g., down_off), a turning-on enablement signal961(e.g., Tzvs_ENA) and a turning-on control signal973(e.g., down_on), and generates the drive signal335(e.g., a drive signal) based at least in part on the mode and/or frequency control signal931(e.g., DCM_on), the turning-off control signal943(e.g., ZVS_off), the turning-off control signal951(e.g., down_off), the turning-on enablement signal961(e.g., Tzvs_ENA) and the turning-on control signal973(e.g., down_on) to turn on and/or turn off the transistor330according to certain embodiments.

According to some embodiments, the resistors364,366,368and370, the capacitors372,374and376, the shunt regulator380(e.g., TL431), and the optocoupler382are used to generate the feedback voltage377based at least in part on the output voltage392. For example, the feedback voltage377represents the output voltage392. In certain examples, based at least in part on the feedback voltage377, the diode992and the resistors994and996generate a voltage997. For example, the feedback voltage377is reduced by the forward bias voltage of the diode992and then by the voltage divider that includes the resistors994and996in order to obtain the voltage997. As an example, the change of the voltage997with time represents a difference between the output voltage392and a target voltage, wherein the target voltage is a voltage value to which the output voltage392is regulated. In some examples, the voltage997is received by the comparator910, which also receives the current sensing voltage345. For example, the comparator910generates the turning-off control signal911(e.g., CV_off) based at least in part on the current sensing voltage345and the voltage997, and outputs the turning-off control signal911(e.g., CV_off) to the drive voltage generator920. As an example, if the current sensing voltage345becomes larger than the voltage997, the turning-off control signal911(e.g., CV_off) changes from a logic low level to a logic high level. In certain examples, in response to the turning-off control signal911(e.g., CV_off) changing from the logic low level to the logic high level, the drive voltage generator920changes the drive voltage325from the logic high level to the logic low level in order to turn off the transistor320.

In certain embodiments, the dead-time controller970detects the drive voltage325changes from the logic high level to the logic low level, and then after a first predetermined dead-time duration (e.g., a first predetermined delay), changes the turning-on control signal973(e.g., down_on) from a logic low level to a logic high level to change the drive voltage335from a logic low level to a logic high level. For example, the turning-on control signal973(e.g., down_on) is at the logic high level and/or at the logic low level. As an example, in response to the turning-on control signal973(e.g., down_on) changing from the logic low level to the logic high level, the drive voltage generator980changes the drive voltage335from the logic low level to the logic high level in order to turn on the transistor330. In some examples, the transistor330is turned on by the drive signal335the first predetermined dead-time duration (e.g., a first predetermined delay) after the transistor320is turned off. For example, during the first predetermined dead-time duration (e.g., a first predetermined delay), both transistors320) and330are turned off.

In some embodiments, the dead-time controller970) also detects the drive voltage335changes from the logic high level to the logic low level, and then after a second predetermined dead-time duration (e.g., a second predetermined delay), changes the turning-on control signal971(e.g., up_on) from the logic low level to the logic high level to change the drive voltage325from the logic low level to the logic high level. For example, the turning-on control signal971(e.g., up_on) is at the logic high level and/or at the logic low level. As an example, in response to at least the turning-on control signal971(e.g., up_on) changing from the logic low level to the logic high level, the drive voltage generator920changes the drive voltage325from the logic low level to the logic high level in order to turn on the transistor320. In some examples, the transistor320is turned on by the drive signal325the second predetermined dead-time duration (e.g., a second predetermined delay) after the transistor330is turned off. For example, during the second predetermined dead-time duration (e.g., a second predetermined delay), both transistors320and330are turned off. As an example, the first predetermined dead-time duration (e.g., a first predetermined delay) and the second predetermined dead-time duration (e.g., a second predetermined delay) are equal or are not equal in length.

According to certain embodiments, the control signal generator950generates the turning-off control signal951(e.g., down_off). For example, the turning-off control signal951(e.g., down_off) is at the logic high level and/or at the logic low level. As an example, in response to the turning-off control signal951(e.g., down_off) changing from the logic low level to the logic high level, the drive voltage generator980changes the drive voltage335from the logic high level to the logic low level in order to turn off the transistor330.

In some examples, the control signal generator950receives the turning-on control signal973(e.g., down_on) and generates the turning-off control signal951(e.g., down_off) based at least in part on the turning-on control signal973(e.g., down_on). For example, a predetermined time duration after the turning-on control signal973(e.g., down_on) changes from the logic low level to the logic high level to turn on the transistor330, the control signal generator950changes the turning-off control signal951(e.g., down_off) from the logic low level to the logic high level to turn off the transistor330.

In certain examples, the control signal generator950receives at least the voltage361(e.g., INV) and the voltage997and generates the turning-off control signal951(e.g., down_off) based at least in part on the voltage361(e.g., INV) and the voltage997. For example, the control signal generator950is a demagnetization detector, which receives at least the voltage361(e.g., INV) and the voltage997to detect the end of a demagnetization process of the primary winding310. As an example, at the end of the demagnetization process of the primary winding310, the control signal generator950changes the turning-off control signal951(e.g., down_off) from the logic low level to the logic high level to turn off the transistor330.

According to some embodiments, the turning-on enablement controller960) receives the voltage361and generates the turning-on enablement signal961(e.g., Tzvs_ENA) based at least in part on the voltage361. For example, the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic high level and/or at the logic low level.

In some embodiments, the mode and/or frequency controller930receives the voltage997and generates the mode and/or frequency control signal931(e.g., DCM_on) based at least in part on the voltage997. In certain examples, the mode and/or frequency control signal931(e.g., DCM_on) is used to control the operation mode and/or the operation frequency of the asymmetrical half-bridge flyback switch-mode power converter300. For example, the mode and/or frequency control signal931(e.g., DCM_on) is used to lower the operation frequency of the asymmetrical half-bridge fly back switch-mode power converter300if the load of the asymmetrical half-bridge flyback switch-mode power converter300becomes lighter. In some examples, the mode and/or frequency control signal931(e.g., DCM_on) is at the logic high level and/or at the logic low level.

According to certain embodiments, when the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic high level, in response to the mode and/or frequency control signal931(e.g., DCM_on) changing from the logic low level to the logic high level, the drive voltage generator980changes the drive voltage335from the logic low level to the logic high level in order to turn on the transistor330.

According to some embodiments, the turning-off controller940receives the voltage361and generates the turning-off control signal943(e.g., ZVS_off) based at least in part on the voltage361. For example, the turning-off control signal943(e.g., ZVS_off) is at the logic high level and/or at the logic low level. As an example, in response to the turning-off control signal943(e.g., ZVS_off) changing from the logic low level to the logic high level, the drive voltage generator980changes the drive voltage335from the logic high level to the logic low level in order to turn off the transistor330. In certain examples, after the transistor330becomes turned off in response to the turning-off control signal943(e.g., ZVS_off) changing from the logic low level to the logic high level, the current353(e.g., ILr) is used to discharge the parasitic capacitor of the transistor320and charge the parasitic capacitor of the transistor330, and the voltage327increases with time. For example, the voltage327increases to become equal to the voltage351. As an example, the second predetermined dead-time duration (e.g., a second predetermined delay) after the transistor330becomes turned off in response to the turning-off control signal943(e.g., ZVS_off) changing from the logic low level to the logic high level, with the voltage327equal to the voltage351, the drive voltage325changes from the logic low level to the logic high level and the transistor320becomes turned on with low-voltage switching and/or zero-voltage switching.

In certain embodiments, when the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic low level, in response to the mode and/or frequency control signal931(e.g., DCM_on) changing from the logic low level to the logic high level, the drive voltage generator980does not change the drive voltage335from the logic low level to the logic high level. In certain examples, after the transistor330becomes turned off in response to the turning-off control signal951(e.g., down_off) changing from the logic low level to the logic high level, through the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), and the inductor318(e.g., with the leakage inductance Lr), the voltage327oscillates. For example, the voltage327oscillates and reaches the voltage351. As an example, the second predetermined dead-time duration (e.g., a second predetermined delay) after the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level, with the voltage327equal to the voltage351, the drive voltage325changes from the logic low level to the logic high level and the transistor320becomes turned on with low-voltage switching and/or zero-voltage switching.

In some embodiments, after the transistor330becomes turned off in response to the turning-off control signal951(e.g., down_off) changing from the logic low level to the logic high level, the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), the inductor318(e.g., with the leakage inductance Lr), and the capacitor352(e.g., Cr) occurs. In certain examples, the capacitance of the capacitor352(e.g., Cr) is much larger than the sum of the capacitance of the parasitic capacitor of the transistor320and the capacitance of the parasitic capacitor of the transistor330, and the voltage drop between the capacitor terminals356and358of the capacitor352(e.g., Cr) is equal to N×Vo, wherein Vorepresents the output voltage392, and N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312.

For example, through the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), the inductor318(e.g., with the leakage inductance Lr), and the capacitor352(e.g., Cr), the voltage327oscillates with an average value of N×Voand an amplitude of N×Vo, wherein Vorepresents the output voltage392, and N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312. As an example, the maximum value of the voltage327is equal to 2×N×Vo, and the minimum value of the voltage327is equal to zero. In some examples, if the voltage351is smaller than 2×N×Vo, the voltage327can reach the voltage351and the transistor320can become turned on with low-voltage switching and/or zero-voltage switching, when the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic low level.

As shown inFIG.4, the dead-time controller970generates the turning-on control signal971(e.g., up_on) and the turning-on control signal973(e.g., down_on) according to some embodiments. In certain examples, the turning-on control signal971(e.g., up_on) is received by the drive voltage generator920, and the turning-on control signal973(e.g., down_on) is received by the drive voltage generator980. For example, in response to the turning-on control signal971(e.g., up_on) changing from the logic low level to the logic high level, the drive voltage generator920changes the drive voltage325from the logic low level to the logic high level in order to turn on the transistor320. As an example, in response to the turning-on control signal973(e.g., down_on) changing from the logic low level to the logic high level, the drive voltage generator980changes the drive voltage335from the logic low level to the logic high level in order to turn on the transistor330.

In certain embodiments, after the drive voltage325changes from the logic low level to the logic high level and the transistor320becomes turned on, the voltage351charges the primary winding310through the capacitor352and the current353flows to the capacitor terminal356with a positive value that increases with time. For example, when the positive value of the current353increases with time, the current sensing voltage345also increases with time. As an example, if the current sensing voltage345becomes larger than the voltage997, the drive voltage325changes from the logic high level to the logic low level to turn off the transistor320. In some examples, after the transistor320becomes turned off, the primary winding310is used to discharge the parasitic capacitor of the transistor330and charge the parasitic capacitor of the transistor320, and the voltage327decreases with time. For example, the voltage327decreases to zero volts. As an example, the first predetermined dead-time duration (e.g., a first predetermined delay) after the transistor320becomes turned off, with the voltage327at zero volts, the drive voltage335changes from the logic low level to the logic high level and the transistor330becomes turned on with low-voltage switching and/or zero-voltage switching.

In some embodiments, the control signal generator950) determines when to change the turning-off control signal951(e.g., down_off) from the logic low level to the logic high level in order to turn off the transistor330. For example, after the transistor330becomes turned off, through the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), and the inductor318(e.g., with the leakage inductance Lr), the voltage327oscillates.

As shown inFIG.4, the controller902for the transistor320uses the current sensing voltage345, the voltage997, and the drive voltage335to generate the drive voltage325in order to turn on and/or turn off the transistor320, and the controller904for the transistor330uses the voltage361, the voltage997, and the drive voltage325to generate the drive voltage335in order to turn on and/or turn off the transistor330according to certain embodiments.

According to some embodiments, the asymmetrical half-bridge fly back switch-mode power converter300operates in a critical conduction mode (CRM) under a heavy load condition, and the asymmetrical half-bridge flyback switch-mode power converter300operates in a discontinuous conduction mode (DCM) under a light load condition. For example, the asymmetrical half-bridge fly back switch-mode power converter300operates in a discontinuous conduction mode (DCM) as shown inFIG.5, wherein the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level when the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic high level. As an example, the asymmetrical half-bridge flyback switch-mode power converter300operates in a discontinuous conduction mode (DCM) as shown inFIG.6, wherein the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level when the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic low level.

FIG.5shows simplified timing diagrams for the asymmetrical half-bridge flyback switch-mode power converter300as shown inFIG.4in the discontinuous conduction mode (DCM) with the mode and/or frequency control signal931(e.g., DCM_on) changing from a logic low level to a logic high level when the turning-on enablement signal961(e.g., Tzvs_ENA) is at a logic high level according to certain embodiment of the present disclosure. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform525represents the drive voltage325as a function of time, the waveform535represents the drive voltage335as a function of time, the waveform517represents the current317as a function of time, the waveform553represents the current353as a function of time, the waveform531represents the mode and/or frequency control signal931(e.g., DCM_on) as a function of time, the waveform543represents the turning-off control signal943(e.g., ZVS_off) as a function of time, and the waveform561represents the voltage361as a function of time.

At time t50, the drive voltage325changes from a logic low level to a logic high level as shown by the waveform525, and the transistor320becomes turned on according to some embodiments. For example, at time t50, the turning-on control signal971(e.g., up_on) changes from the logic low level to the logic high level, and in response, the drive voltage generator920changes the drive voltage325from the logic low level to the logic high level in order to turn on the transistor320. As an example, at time t50, the drive voltage335is at the logic low level as shown by the waveform535, and the transistor330is turned off.

From time t50to time t51, the drive voltage325remains at the logic high level as shown by the waveform525, and the transistor320remains turned on according to certain embodiments. For example, from time t50to time t51, the current353increases with time, as shown by the waveform553. As an example, from time t50to time t51, the drive voltage335remains at the logic low level as shown by the waveform535, and the transistor330remains turned off. In some examples, from time t50to time t51, the current353increases with time, as shown by the waveform553. For example, from time t50to time t51, the current sensing voltage345also increases with time.

At time t51, the drive voltage325changes from the logic high level to the logic low level as shown by the waveform525, and the transistor320becomes turned off according to some embodiments. For example, at time t51, the turning-off control signal911(e.g., CV_off) changes from the logic low level to the logic high level, and in response, the drive voltage generator920changes the drive voltage325from the logic high level to the logic low level in order to turn off the transistor320. As an example, at time t51, the drive voltage335is at the logic low level as shown by the waveform535, and the transistor330is turned off. In certain examples, at time t51, the current353reaches a current value554(e.g., Ip), wherein the current value554is positive.

From time t51to time t52, the drive voltage325remains at the logic low level as shown by the waveform525, and the drive voltage335remains at the logic low level as shown by the waveform535according to certain embodiments. For example, from time t51to time t52, the transistor320remains turned off, and the transistor330also remains turned off. As an example, the time duration from time t51to time t52is equal to the first predetermined dead-time duration (e.g., a first predetermined delay) as determined by the dead-time controller970. In some examples, from time t51to time t52, the current353(e.g., ILr) is used to discharge the parasitic capacitor of the transistor330and charge the parasitic capacitor of the transistor320. For example, from time t51to time t52, the voltage327decreases with time.

At time t52, the drive voltage335changes from the logic low level to the logic high level as shown by the waveform535, and the transistor330becomes turned on according to some embodiments. For example, at time t52, the turning-on control signal973(e.g., down_on) changes from the logic low level to the logic high level, and in response, the drive voltage generator980changes the drive voltage335from the logic low level to the logic high level in order to turn on the transistor330. As an example, at time t52, the drive voltage325is at the logic low level as shown by the waveform525, and the transistor320is turned off. In certain examples, at time t52, the voltage327reached zero volts. For example, at time t52, the transistor330becomes turned on with low-voltage switching and/or zero-voltage switching.

From time t52to time t53, the drive voltage335remains at the logic high level as shown by the waveform535, and the transistor330remains turned on according to certain embodiments. For example, from time t52to time t53, the drive voltage325remains at the logic low level as shown by the waveform525, and the transistor320remains turned off. As an example, from time t52to time t53, through the resonance of the capacitor352and the inductor318(e.g., with the leakage inductance Lr), the current353(e.g., ILr) decreases to zero and then becomes negative as shown by the waveform553. In some examples, from time t52to time t53, the current353(e.g., ILr) decreases to zero and then becomes negative as shown by the waveform553. In certain examples, from time t52to time t53, the current317(e.g., ILm) decreases linearly with time as shown by the waveform517.

At time t53, the drive voltage335changes from the logic high level to the logic low level as shown by the waveform535, and the transistor330becomes turned off according to some embodiments. For example, at time t53, the turning-off control signal951(e.g., down_off) changes from the logic low level to the logic high level, and in response, the drive voltage generator980changes the drive voltage335from the logic high level to the logic low level in order to turn off the transistor330. As an example, at time t53, the drive voltage325is at the logic low level as shown by the waveform525, and the transistor320is turned off.

In some examples, the length of time duration from time t52to time t53is a predetermined constant for the asymmetrical half-bridge fly back switch-mode power converter300as shown inFIG.4. For example, the current317(e.g., ILm) at time t53depends at least in part on the predetermined constant that is used as the length of time duration from time t52to time t53, and the current317(e.g., ILm) at time t53is either equal to zero or is not equal to zero as shown by the waveform517.

In certain examples, at time t53, the demagnetization process for the primary winding310ends, and the current317(e.g., ILm) decreases to zero as shown by the waveform517. For example, the time duration from time t52to time t53represents the demagnetization period for the primary winding310. As an example, time t52is the beginning of the demagnetization period for the primary winding310, and time t53is the end of the demagnetization period for the primary winding310.

From time t53to time t54, the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), and the inductor318(e.g., with the leakage inductance Lr) occurs, as shown by the waveform561according to certain embodiments. For example, from time t53to time t54, the voltage327oscillates without reaching the voltage351. As an example, from time t53to time t54, the resonance period is equal to Td, as shown by the waveform561.

At time t54, the drive voltage335changes from the logic low level to the logic high level as shown by the waveform535, and the transistor330becomes turned on according to some embodiments. For example, at time t54, the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level when the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic high level, and in response, the drive voltage generator980changes the drive voltage335from the logic low level to the logic high level in order to turn on the transistor330. As an example, at time t54, the drive voltage325is at the logic low level as shown by the waveform525, and the transistor320is turned off.

From time t54to time t55, the drive voltage335remains at the logic high level as shown by the waveform535, and the transistor330remains turned on according to certain embodiments. For example, from time t54to time t55, the drive voltage325remains at the logic low level as shown by the waveform525, and the transistor320remains turned off. In some examples, from time t54to time t55, the current353(e.g., ILr) has a negative value, and decreases with time as shown by the waveform553. For example, from time t54to time t55, the current353(e.g., ILr) flows from the capacitor terminal356.

At time t55, the drive voltage335changes from the logic high level to the logic low level as shown by the waveform535, and the transistor330becomes turned off according to some embodiments. For example, at time t55, the turning-off control signal943(e.g., ZVS_off) changes from the logic low level to the logic high level, and in response, the drive voltage generator980changes the drive voltage335from the logic high level to the logic low level in order to turn off the transistor330. As an example, at time t55, the drive voltage325is at the logic low level as shown by the waveform525, and the transistor320is turned off. In certain embodiments, at time t55, the current353reaches a current value555(e.g., In_zvs), wherein the current value555is negative.

From time t55to time t56, the drive voltage325remains at the logic low level as shown by the waveform525, and the drive voltage335remains at the logic low level as shown by the waveform535according to certain embodiments. For example, from time t55to time t56, the transistor320remains turned off, and the transistor330also remains turned off. As an example, the time duration from time t55to time t56is equal to the second predetermined dead-time duration (e.g., a second predetermined delay) as determined by the dead-time controller970. In some examples, from time t55to time t56, through the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), and the inductor318(e.g., with the leakage inductance Lr), the current153(e.g., ILr) is used to discharge the parasitic capacitor of the transistor120and charge the parasitic capacitor of the transistor130, and the voltage127increases with time.

At time t56, the drive voltage325changes from the logic low level to the logic high level as shown by the waveform525, and the transistor320becomes turned on according to some embodiments. For example, at time t56, the turning-on control signal971(e.g., up_on) changes from the logic low level to the logic high level, and in response, the drive voltage generator920changes the drive voltage325from the logic low level to the logic high level in order to turn on the transistor320. As an example, at time t56, the drive voltage335is at the logic low level as shown by the waveform535, and the transistor330is turned off. In certain examples, at time t56, the voltage327becomes equal to the voltage351. As an example, at time t56, the transistor320becomes turned on with low-voltage switching and/or zero-voltage switching.

As mentioned above and further emphasized here, the timing diagrams as shown inFIG.5are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, at time t52, the voltage327becomes close to but is still larger than zero volts, and the transistor330becomes turned on with low-voltage switching, wherein the difference between the voltage327and the zero volts is small. As an example, at time t56, the voltage327becomes close to but is still smaller than the voltage351, and the transistor320becomes turned on with low-voltage switching, wherein the difference between the voltage327and the voltage351is small.

FIG.6shows simplified timing diagrams for the asymmetrical half-bridge fly back switch-mode power converter300as shown inFIG.4in the discontinuous conduction mode (DCM) with the mode and/or frequency control signal931(e.g., DCM_on) changing from a logic low level to a logic high level when the turning-on enablement signal961(e.g., Tzvs_ENA) is at a logic low level according to certain embodiment of the present disclosure. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform625represents the drive voltage325as a function of time, the waveform635represents the drive voltage335as a function of time, the waveform617represents the current317as a function of time, the waveform653represents the current353as a function of time, the waveform631represents the mode and/or frequency control signal931(e.g., DCM_on) as a function of time, the waveform643represents the turning-off control signal943(e.g., ZVS_off) as a function of time, and the waveform661represents the voltage361as a function of time.

At time t60, the drive voltage325changes from a logic low level to a logic high level as shown by the waveform625, and the transistor320becomes turned on according to some embodiments. For example, at time t60, the turning-on control signal971(e.g., up_on) changes from the logic low level to the logic high level, and in response, the drive voltage generator920changes the drive voltage325from the logic low level to the logic high level in order to turn on the transistor320. As an example, at time t60, the drive voltage335is at the logic low level as shown by the waveform635, and the transistor330is turned off. In certain examples, at time t60, the turning-off control signal943(e.g., ZVS_off) is at the logic low level as shown by the waveform643.

From time t60to time t61, the drive voltage325remains at the logic high level as shown by the waveform625, and the transistor320remains turned on according to certain embodiments. For example, from time t60to time t61, the current353increases with time, as shown by the waveform653. As an example, from time t60to time t61, the drive voltage335remains at the logic low level as shown by the waveform635, and the transistor330remains turned off. In some examples, from time t60to time t61, the current353increases with time, as shown by the waveform653. For example, from time t60to time t61, the current sensing voltage345also increases with time. In certain examples, from time t60to time t61, the turning-off control signal943(e.g., ZVS_off) remains at the logic low level as shown by the waveform643.

At time t61, the drive voltage325changes from the logic high level to the logic low level as shown by the waveform625, and the transistor320becomes turned off according to some embodiments. For example, at time t61, the turning-off control signal911(e.g., CV_off) changes from the logic low level to the logic high level, and in response, the drive voltage generator920changes the drive voltage325from the logic high level to the logic low level in order to turn off the transistor320. As an example, at time t61, the drive voltage335is at the logic low level as shown by the waveform635, and the transistor330is turned off. In certain examples, at time t61, the current353reaches a current value654(e.g., Ip), wherein the current value654is positive. In some examples, at time t61, the turning-off control signal943(e.g., ZVS_off) is at the logic low level as shown by the waveform643.

From time t61to time t62, the drive voltage325remains at the logic low level as shown by the waveform625, and the drive voltage335remains at the logic low level as shown by the waveform635according to certain embodiments. For example, from time t61to time t62, the transistor320remains turned off, and the transistor330also remains turned off. As an example, the time duration from time t61to time t62is equal to the first predetermined dead-time duration (e.g., a first predetermined delay) as determined by the dead-time controller970. In some examples, from time t61to time t62, the current353(e.g., ILr) is used to discharge the parasitic capacitor of the transistor330and charge the parasitic capacitor of the transistor320. For example, from time t61to time t62, the voltage327decreases with time. In certain examples, from time t61to time t62, the turning-off control signal943(e.g., ZVS_off) remains at the logic low level as shown by the waveform643.

At time t62, the drive voltage335changes from the logic low level to the logic high level as shown by the waveform635, and the transistor330becomes turned on according to some embodiments. For example, at time t62, the turning-on control signal973(e.g., down_on) changes from the logic low level to the logic high level, and in response, the drive voltage generator980changes the drive voltage335from the logic low level to the logic high level in order to turn on the transistor330. As an example, at time t62, the drive voltage325is at the logic low level as shown by the waveform625, and the transistor320is turned off. In certain examples, at time t62, the voltage327reached zero volts. For example, at time t62, the transistor330becomes turned on with low-voltage switching and/or zero-voltage switching. In some examples, at time t62, the turning-off control signal943(e.g., ZVS_off) is at the logic low level as shown by the waveform643.

From time t62to time t63, the drive voltage335remains at the logic high level as shown by the waveform635, and the transistor330remains turned on according to certain embodiments. For example, from time t62to time t63, the drive voltage325remains at the logic low level as shown by the waveform625, and the transistor320remains turned off. As an example, from time t62to time t63, through the resonance of the capacitor352and the inductor318(e.g., with the leakage inductance Lr), the current353(e.g., ILr) decreases to zero and then becomes negative as shown by the waveform653. In some examples, from time t62to time t63, the current353(e.g., ILr) decreases to zero and then becomes negative as shown by the waveform653. In certain examples, from time t62to time t63, the current317(e.g., ILm) decreases linearly with time as shown by the waveform617. In some examples, from time t62to time t63, the turning-off control signal943(e.g., ZVS_off) remains at the logic low level as shown by the waveform643.

At time t63, the drive voltage335changes from the logic high level to the logic low level as shown by the waveform635, and the transistor330becomes turned off according to some embodiments. For example, at time t63, the turning-off control signal951(e.g., down_off) changes from the logic low level to the logic high level, and in response, the drive voltage generator980changes the drive voltage335from the logic high level to the logic low level in order to turn off the transistor330. As an example, at time t63, the drive voltage325is at the logic low level as shown by the waveform525, and the transistor320is turned off.

In some examples, the length of time duration from time t62to time t63is a predetermined constant for the asymmetrical half-bridge fly back switch-mode power converter300as shown inFIG.4. For example, the current317(e.g., ILm) at time t63depends at least in part on the predetermined constant that is used as the length of time duration from time t62to time t63, and the current317(e.g., ILm) at time t63is either equal to zero or is not equal to zero as shown by the waveform617.

In certain examples, at time t63, the demagnetization process for the primary winding310ends, and the current317(e.g., ILm) decreases to zero as shown by the waveform617. For example, the time duration from time t62to time t63represents the demagnetization period for the primary winding310. As an example, time t62is the beginning of the demagnetization period for the primary winding310, and time t63is the end of the demagnetization period for the primary winding310. In some examples, at time t63, the turning-off control signal943(e.g., ZVS_off) is at the logic low level as shown by the waveform643.

From time t63to time t64, the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), and the inductor318(e.g., with the leakage inductance Lr) occurs, as shown by the waveform661according to certain embodiments. For example, from time t63to time t64, the voltage327oscillates and reaches the voltage351. As an example, from time t63to time t64, the resonance period is equal to Td, as shown by the waveform661. In some examples, from time t63to time t64, the turning-off control signal943(e.g., ZVS_off) remains at the logic low level as shown by the waveform643.

At time t64, the drive voltage335does not change from the logic low level to the logic high level as shown by the waveform535, and the transistor330does not become turned on according to some embodiments. For example, at time t64, the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level when the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic low level, and in response, the drive voltage generator980) does not change the drive voltage335from the logic low level to the logic high level. As an example, at time t64, the drive voltage335is at the logic low level as shown by the waveform535, and the transistor330is turned off. In certain examples, the drive voltage325is at the logic low level as shown by the waveform525, and the transistor320is turned off. In some examples, at time t64, the turning-off control signal943(e.g., ZVS_off) is at the logic low level as shown by the waveform643.

From time t64to time t65, the drive voltage325remains at the logic low level as shown by the waveform525, and the drive voltage335remains at the logic low level as shown by the waveform535according to certain embodiments. For example, from time t64to time t65, the transistor320remains turned off, and the transistor330) also remains turned off. As an example, the time duration from time t64to time t65is equal to the second predetermined dead-time duration (e.g., a second predetermined delay) as determined by the dead-time controller970. In some examples, from time t64to time t65, through the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), and the inductor318(e.g., with the leakage inductance Lr), the current153(e.g., ILr) is used to discharge the parasitic capacitor of the transistor120and charge the parasitic capacitor of the transistor130, and the voltage127increases with time. In some examples, from time t64to time t65, the turning-off control signal943(e.g., ZVS_off) remains at the logic low level as shown by the waveform643.

At time t65, the drive voltage325changes from the logic low level to the logic high level as shown by the waveform525, and the transistor320becomes turned on according to some embodiments. For example, at time t65, the turning-on control signal971(e.g., up_on) changes from the logic low level to the logic high level, and in response, the drive voltage generator920changes the drive voltage325from the logic low level to the logic high level in order to turn on the transistor320. As an example, at time t65, the drive voltage335is at the logic low level as shown by the waveform635, and the transistor330is turned off. In certain examples, at time t65, the voltage327becomes equal to the voltage351. As an example, at time t65, the transistor320becomes turned on with low-voltage switching and/or zero-voltage switching. In some examples, at time t65, the turning-off control signal943(e.g., ZVS_off) is at the logic low level as shown by the waveform643.

As mentioned above and further emphasized here, the timing diagrams as shown inFIG.6are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, at time t62, the voltage327becomes close to but is still larger than zero volts, and the transistor330becomes turned on with low-voltage switching, wherein the difference between the voltage327and the zero volts is small. As an example, at time t65, the voltage327becomes close to but is still smaller than the voltage351, and the transistor320becomes turned on with low-voltage switching, wherein the difference between the voltage327and the voltage351is small.

FIG.7is a simplified diagram showing the turning-on enablement controller960as part of the asymmetrical half-bridge fly back switch-mode power converter300as shown inFIG.4according to certain embodiments of the present disclosure. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The turning-on enablement controller960includes a sampling unit710and a comparison unit720. For example, the sampling unit710is implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components, and/or the sampling unit710is implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. As an example, the comparison unit720is implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components, and/or the comparison unit720is implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. Although the above has been shown using a selected group of components for the turning-on enablement controller, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

In some embodiments, the sampling unit710receives the voltage361and generates a sampled voltage711and a sampled voltage713based at least in part on the voltage361. For example, the sampling unit710samples the voltage361when the transistor320is turned on and the transistor330is turned off, and in response generates the sampled voltage711(e.g., V1) to represent the voltage361when the transistor320is turned on and the transistor330is turned off. As an example, the sampling unit710samples the voltage361when the transistor320is turned off and the transistor330is turned on, and in response generates the sampled voltage713(e.g., V2) to represent the voltage361when the transistor320is turned off and the transistor330is turned on.

In certain examples, the sampled voltage711(e.g., V1) is directly proportional to the voltage361when the transistor320is turned on and the transistor330is turned off. For example, when the transistor320is turned on and the transistor330is turned off, the voltage361is equal to Vin−N×Vo, wherein Vin represents the voltage351. Vorepresents the output voltage392, and N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312. As an example, the sampled voltage711(e.g., V1) is equal to m1×(Vin−N×Vo), wherein m1is a predetermined constant. Vin represents the voltage351. Vorepresents the output voltage392, and N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312.

In some examples, the sampled voltage713(e.g., V2) is directly proportional to the voltage361when the transistor320is turned off and the transistor330is turned on. For example, when the transistor320is turned off and the transistor330is turned on, the voltage361is equal to N×Vo, wherein Vorepresents the output voltage392and N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312. As an example, the sampled voltage713(e.g., V2) is equal to m2×N×Vo, wherein m2is a predetermined constant, Vorepresents the output voltage392, and N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312.

In certain embodiments, the comparison unit720receives the sampled voltage711and the sampled voltage713and generates the turning-on enablement signal961(e.g., Tzvs_ENA) based at least in part on the sampled voltage711and the sampled voltage713. In some examples, the comparison unit720directly compares the sampled voltage711and the sampled voltage713and generates the turning-on enablement signal961(e.g., Tzvs_ENA) based at least in part on the comparison. For example, if the sampled voltage711is larger than the sampled voltage713, the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic high level. As an example, if the sampled voltage711is smaller than the sampled voltage713, the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic low level. In certain examples, the comparison unit720converts and then compares the sampled voltage711and the sampled voltage713and generates the turning-on enablement signal961(e.g., Tzvs_ENA) based at least in part on the conversion and the comparison. For example, if the sampled voltage711is larger than the sampled voltage713multiplied by a predetermined constant, the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic high level. As an example, if the sampled voltage711is smaller than the sampled voltage713multiplied by the predetermined constant, the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic low level.

FIG.8is a simplified diagram showing the turning-off controller940as part of the asymmetrical half-bridge flyback switch-mode power converter300as shown inFIG.4according to some embodiments of the present disclosure. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The turning-off controller940includes a sampling unit810, an integration unit830, a ramp signal generator840, and a comparator820. For example, the sampling unit810is implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components, and/or the sampling unit810is implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. As an example, the integration unit830is implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components, and/or the integration unit830is implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. Although the above has been shown using a selected group of components for the turning-off controller, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

In certain embodiments, the sampling unit810receives the voltage361and generates a sampled voltage811based at least in part on the voltage361. In some examples, the sampled voltage811(e.g., V3) is received by the integration unit830, which also receives a reference voltage813(e.g., Vref). For example, the integration unit830determines a difference between the sampled voltage811(e.g., V3) and the reference voltage813(e.g., Vref), integrate the difference over time, and generates a compensation signal831(e.g., ZVS_comp) to represent the result of the integration. As an example, the reference voltage813(e.g., Vref) is equal to 0.2 volts. In some examples, the ramp signal generator840generates a ramp signal841. For example, the ramp signal841is a periodic signal. As an example, the ramp signal841increases linearly with time at a constant slope. In some embodiments, the comparator820receives the compensation signal831(e.g., ZVS_comp) and the ramp signal841and generates the turning-off control signal943(e.g., ZVS_off) based at least in part on the compensation signal831(e.g., ZVS_comp) and the ramp signal841.

In some examples, the sampled voltage811(e.g., V3) represents the voltage327immediately before the transistor320becomes turned on. For example, the sampled voltage811(e.g., V3) is directly proportional to the voltage327immediately before the transistor320becomes turned on. In certain examples, the sampled voltage811(e.g., V3) represents a change in the voltage327in response to the transistor320changing from being turned off to being turned on. For example, the sampled voltage811(e.g., V3) is directly proportional to a change in the voltage327in response to the transistor320changing from being turned off to being turned on. In certain embodiments, the reference voltage813is a predetermined constant voltage. In some embodiments, the reference voltage813is generated by the sampling unit810that samples the voltage361when the transistor320is turned on.

As shown inFIG.8, the comparator820compares the compensation signal831(e.g., ZVS_comp) and the ramp signal841and generates the turning-off control signal943(e.g., ZVS_off) based at least in part on the comparison according to certain embodiments. For example, when the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level, the transistor330becomes turned on and the ramp signal841starts increasing linearly with time. As an example, when the ramp signal841becomes larger than the compensation signal831(e.g., ZVS_comp), the comparator820) changes the turning-off control signal943(e.g., ZVS_off) from the logic low level to the logic high level in order to turn off the transistor330.

FIG.9shows simplified timing diagrams for the asymmetrical half-bridge fly back switch-mode power converter300as shown inFIG.4andFIG.8in the discontinuous conduction mode (DCM) with the mode and/or frequency control signal931(e.g., DCM_on) changing from a logic low level to a logic high level when the turning-on enablement signal961(e.g., Tzvs_ENA) is at a logic high level according to certain embodiment of the present disclosure. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform1925represents the drive voltage325as a function of time, the waveform1935represents the drive voltage335as a function of time, the waveform1953represents the current353as a function of time, the waveform1931represents the compensation signal831as a function of time, the waveform1961represents the voltage361as a function of time, and the waveform1927represents the voltage327as a function of time.

According to some embodiments, the sampled voltage811is larger than the reference voltage813. For example, the sampled voltage811(e.g., V3) represents a change in the voltage327in response to the transistor320changing from being turned off to being turned on, and the reference voltage813is a predetermined constant voltage. As an example, the change in the voltage327in response to the transistor320changing from being turned off to being turned on is larger than a target value that is directly proportional to the reference voltage813.

In certain examples, if the sampled voltage811is larger than the reference voltage813, the compensation signal831(e.g., ZVS_comp) increases with time as shown by the waveform1931. For example, after the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level, it takes a longer time for the ramp signal841to become larger than the compensation signal831(e.g., ZVS_comp) if the compensation signal831becomes larger.

In some examples, the time duration (e.g., Tzvs) from the time when the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level to the time when the ramp signal841becomes larger than the compensation signal831(e.g., ZVS_comp) increases with time as shown by the waveform1935. For example, when the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level, the drive voltage335changes from being the logic low level to the logic high level and the transistor330becomes turned on. As an example, when the ramp signal841becomes larger than the compensation signal831(e.g., ZVS_comp), the drive voltage335changes from being the logic high level to the logic low level and the transistor330becomes turned off.

According to certain embodiments, the time duration (e.g., Tzvs) from the time when the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level to the time when the ramp signal841becomes larger than the compensation signal831(e.g., ZVS_comp) increases with time, so the change in the voltage327in response to the transistor320changing from being turned off to being turned on decreases and becomes closer the target value. For example, if the change in the voltage327in response to the transistor320changing from being turned off to being turned on becomes equal to the target value, the time duration (e.g., Tzvs) stopes changing with time.

FIG.10shows simplified timing diagrams for the asymmetrical half-bridge fly back switch-mode power converter300as shown inFIG.4andFIG.8in the discontinuous conduction mode (DCM) with the mode and/or frequency control signal931(e.g., DCM_on) changing from a logic low level to a logic high level when the turning-on enablement signal961(e.g., Tzvs_ENA) is at a logic high level according to some embodiment of the present disclosure. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform1025represents the drive voltage325as a function of time, the waveform1035represents the drive voltage335as a function of time, the waveform1053represents the current353as a function of time, the waveform1031represents the compensation signal831as a function of time, the waveform1061represents the voltage361as a function of time, and the waveform1027represents the voltage327as a function of time.

According to certain embodiments, the sampled voltage811is smaller than the reference voltage813. For example, the sampled voltage811(e.g., V3) represents a change in the voltage327in response to the transistor320changing from being turned off to being turned on, and the reference voltage813is a predetermined constant voltage. As an example, the change in the voltage327in response to the transistor320changing from being turned off to being turned on is smaller than a target value that is directly proportional to the reference voltage813.

In some examples, if the sampled voltage811is smaller than the reference voltage813, the compensation signal831(e.g., ZVS_comp) decreases with time as shown by the waveform1031. For example, after the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level, it takes a shorter time for the ramp signal841to become larger than the compensation signal831(e.g., ZVS_comp) if the compensation signal831becomes smaller.

In certain examples, the time duration (e.g., Tzvs) from the time when the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level to the time when the ramp signal841becomes larger than the compensation signal831(e.g., ZVS_comp) decreases with time as shown by the waveform1035. For example, when the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level, the drive voltage335changes from being the logic low level to the logic high level and the transistor330becomes turned on. As an example, when the ramp signal841becomes larger than the compensation signal831(e.g., ZVS_comp), the drive voltage335changes from being the logic high level to the logic low level and the transistor330becomes turned off.

According to some embodiments, the time duration (e.g., Tzvs) from the time when the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level to the time when the ramp signal841becomes larger than the compensation signal831(e.g., ZVS_comp) decreases with time, so the change in the voltage327in response to the transistor320changing from being turned off to being turned on increases and becomes closer the target value. For example, if the change in the voltage327in response to the transistor320changing from being turned off to being turned on becomes equal to the target value, the time duration (e.g., Tzvs) stopes changing with time.

FIG.11shows simplified timing diagrams for the asymmetrical half-bridge fly back switch-mode power converter300as shown inFIG.4andFIG.8in the discontinuous conduction mode (DCM) with the mode and/or frequency control signal931(e.g., DCM_on) changing from a logic low level to a logic high level when the turning-on enablement signal961(e.g., Tzvs_ENA) is at a logic high level according to certain embodiment of the present disclosure. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform1125represents the drive voltage325as a function of time, the waveform1135represents the drive voltage335as a function of time, the waveform1153represents the current353as a function of time, the waveform1131represents the compensation signal831as a function of time, the waveform1161represents the voltage361as a function of time, and the waveform1127represents the voltage327as a function of time.

According to some embodiments, the sampled voltage811is equal to the reference voltage813. For example, the sampled voltage811(e.g., V3) represents a change in the voltage327in response to the transistor320changing from being turned off to being turned on, and the reference voltage813is a predetermined constant voltage. As an example, the change in the voltage327in response to the transistor320changing from being turned off to being turned on is equal to a target value that is directly proportional to the reference voltage813.

In certain examples, if the sampled voltage811is equal to the reference voltage813, the compensation signal831(e.g., ZVS_comp) does not change with time as shown by the waveform1131. For example, after the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level, it takes the same time for the ramp signal841to become larger than the compensation signal831(e.g., ZVS_comp) if the compensation signal831remains constant.

In some examples, the time duration (e.g., Tzvs) from the time when the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level to the time when the ramp signal841becomes larger than the compensation signal831(e.g., ZVS_comp) remains constant with time as shown by the waveform1135. For example, when the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level, the drive voltage335changes from being the logic low level to the logic high level and the transistor330becomes turned on. As an example, when the ramp signal841becomes larger than the compensation signal831(e.g., ZVS_comp), the drive voltage335changes from being the logic high level to the logic low level and the transistor330becomes turned off.

According to certain embodiments, the time duration (e.g., Tzvs) from the time when the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level with the turning-on enablement signal961(e.g., Tzvs_ENA) at the logic high level to the time when the ramp signal841becomes larger than the compensation signal831(e.g., ZVS_comp) remains constant with time, so the change in the voltage327in response to the transistor320changing from being turned off to being turned on remains constant and equal to the target value.

As shown inFIG.9,FIG.10, andFIG.11, the asymmetrical half-bridge fly back switch-mode power converter300is configured to regulate the change in the voltage327in response to the transistor320changing from being turned off to being turned on, so that the change in the voltage327is equal to a target value that is directly proportional to the reference voltage813. For example, the target value is not equal to zero. As an example, the target value is equal to 50 volts.

As shown inFIG.5, at time t55, the drive voltage335changes from the logic high level to the logic low level as shown by the waveform535, and the transistor330becomes turned off according to some embodiments. For example, through the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), and the inductor318(e.g., with the leakage inductance Lr), the current353reaches the current value555(e.g., In_zvs) at time t55, wherein the current value555is negative.

In certain examples, in order for the voltage327to become equal to the voltage351at time t56, the current value555needs to satisfy the following equation:

where Cossrepresents the sum of the capacitance of the parasitic capacitor of the transistor320and the capacitance of the parasitic capacitor of the transistor330. Additionally, Vinrepresents the voltage351, and Vorepresents the output voltage392. Moreover, N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312. Also, Lmrepresents the sum of the primary inductance Lpof the inductor116and the leakage inductance Lrof the inductor118, and In_zvsrepresents the current value555.

In some examples, based on Equation 1, in order for the voltage327to become equal to the voltage351at time t56, the current value555is determined as follows:

where In_zvsrepresents the current value555, which is negative. Additionally, Cossrepresents the sum of the capacitance of the parasitic capacitor of the transistor320and the capacitance of the parasitic capacitor of the transistor330. Moreover, Vinrepresents the voltage351, and Vorepresents the output voltage392. Also, N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312. Additionally, Lmrepresents the sum of the primary inductance Lpof the inductor116and the leakage inductance Lrof the inductor118.

According to certain embodiments, the time duration from time t54to time t55has the following relationship with the current value555:

where Tzvsrepresents the time duration from time t54to time t55. Additionally, In_ZVSrepresents the current value555, which is negative. Moreover, Vorepresents the output voltage392, and N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312. Also, Lmrepresents the sum of the primary inductance Lpof the inductor116and the leakage inductance Lrof the inductor118.

In certain examples, based on Equations 2 and 3, in order for the voltage327to become equal to the voltage351at time t56, the time duration from time t54to time t55is approximately determined as follows:

where Tzvsrepresents the time duration from time t54to time t55. Additionally, Vinrepresents the voltage351, and Vorepresents the output voltage392. Moreover, N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312. Also, Cossrepresents the sum of the capacitance of the parasitic capacitor of the transistor320and the capacitance of the parasitic capacitor of the transistor330, and Lm represents the sum of the primary inductance Lpof the inductor116and the leakage inductance Lrof the inductor118.

In some examples, the resonance period for the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), and the inductor318(e.g., with the leakage inductance Lr) from time t53to time t54satisfies the following relationship:

where tdrepresents the resonance period for the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), and the inductor318(e.g., with the leakage inductance Lr) from time t53to time t54. Additionally, Cossrepresents the sum of the capacitance of the parasitic capacitor of the transistor320and the capacitance of the parasitic capacitor of the transistor330, and Lm represents the sum of the primary inductance Lpof the inductor116and the leakage inductance Lrof the inductor118.

According to some embodiments, based on Equations 4, 5 and 6, in order for the voltage327to become equal to the voltage351at time t56, the time duration from time t54to time t55is approximately determined as follows:

where Tzvsrepresents the time duration from time t54to time t55. Additionally, Vinrepresents the voltage351, and Vorepresents the output voltage392. Moreover, N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312. Also, ta represents the resonance period for the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), and the inductor318(e.g., with the leakage inductance Lr) from time t53to time t54.

FIG.12is a simplified diagram showing the turning-off controller940as part of the asymmetrical half-bridge fly back switch-mode power converter300as shown inFIG.4according to certain embodiments of the present disclosure. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The turning-off controller940includes a sampling unit1210, a voltage-controlled current source1230, a capacitor1240, switches1250and1260, and a comparator1220. For example, the sampling unit1210is implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components, and/or the sampling unit1210is implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. Although the above has been shown using a selected group of components for the turning-off controller, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

According to some embodiments, the sampling unit1210receives the voltage361and generates a sampled voltage1211and a sampled voltage1213based at least in part on the voltage361. For example, the sampling unit1210samples the voltage361when the transistor320is turned on and the transistor330is turned off, and in response generates the sampled voltage1211(e.g., V4) to represent the voltage361when the transistor320is turned on and the transistor330is turned off. As an example, the sampling unit1210samples the voltage361when the transistor320is turned off and the transistor330is turned on, and in response generates the sampled voltage1213(e.g., V5) to represent the voltage361when the transistor320is turned off and the transistor330is turned on.

In certain examples, the sampled voltage1211(e.g., V4) is directly proportional to the voltage361when the transistor320is turned on and the transistor330is turned off. For example, when the transistor320is turned on and the transistor330is turned off, the voltage361is equal to Vin−N×Vo, wherein Vinrepresents the voltage351. Vorepresents the output voltage392, and N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312. As an example, the sampled voltage1211(e.g., V4) is equal to m3×(Vin−N×Vo), wherein m3is a predetermined constant. Vinrepresents the voltage351. Vorepresents the output voltage392, and N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312.

In some examples, the sampled voltage1213(e.g., V5) is directly proportional to the voltage361when the transistor320is turned off and the transistor330is turned on. For example, when the transistor320is turned off and the transistor330is turned on the voltage361is equal to N×Vo, wherein Vorepresents the output voltage392and N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312. As an example, the sampled voltage713(e.g., V2) is equal to m4×N×Vo, wherein m4is a predetermined constant. Vorepresents the output voltage392, and N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312.

According to certain embodiments, the voltage-controlled current source1230receives the sampled voltage1213(e.g., V5) and generates a current1231based at least in part on the sampled voltage1213(e.g., V5). For example, the current1231(e.g., I1) is directly proportional to the sampled voltage1213(e.g., V5). As an example, the current1231is determined as follows:

where I1represents the current1231, and V5represents the sampled voltage1213. Additionally, k is a predetermined constant.

In some embodiments, the switch1250receives a control signal1291. For example, if the control signal1291(e.g., ZVS_on) is at a logic high level, the switch1250is closed. As an example, if the control signal1291(e.g., ZVS_on) is at a logic low level, the switch1250is open. In certain examples, if the mode and/or frequency control signal931(e.g., DCM_on) changes from the logic low level to the logic high level when the turning-on enablement signal961(e.g., Tzvs_ENA) is at the logic high level, the control signal1291(e.g., ZVS_on) changes from the logic low level to the logic high level and the switch1250becomes closed. In some examples, after the control signal1291(e.g., ZVS_on) changes from the logic low level to the logic high level, the control signal1291(e.g., ZVS_on) remains at the logic high level until the turning-off control signal943(e.g., ZVS_off) changes from the logic low level to the logic high level. For example, in response to the turning-off control signal943(e.g., ZVS_off) changing from the logic low level to the logic high level, the control signal1291(e.g., ZVS_on) changes from the logic high level to the logic low level. As an example, at the same time, the turning-off control signal943(e.g., ZVS_off) changes from the logic low level to the logic high level and the control signal1291(e.g., ZVS_on) changes from the logic high level to the logic low level. In certain embodiments, the switch1260receives the turning-off control signal943(e.g., ZVS_off). For example, if the turning-off control signal943(e.g., ZVS_off) is at a logic high level, the switch1260is closed. As an example, if the turning-off control signal943(e.g., ZVS_off) is at a logic low level, the switch1260is open.

According to some embodiments, the capacitor1240includes a capacitor terminal1242that is biased to a ground voltage (e.g., 0 volts), and the capacitor1240also includes a capacitor terminal1244that is biased to a voltage1245. For example, when the switch1250is closed and the switch1260is open, the capacitor1240is charged by the current1231and the voltage1245increases with time, until the switch1260becomes closed. As an example, when the switch1260becomes closed, the switch1250becomes open. In certain examples, when the switch1260is closed and the switch1250is open, the capacitor1240is discharged and the voltage1245drops to the ground voltage (e.g., 0 volts). For example, at the same time, the switch1260becomes closed in response to the turning-off control signal943(e.g., ZVS_off) changing from the logic low level to the logic high level, and the switch1250becomes open in response to the control signal1291(e.g., ZVS_on) changing from the logic high level to the logic low level.

According to certain embodiments, as shown inFIG.5, at time t54, the capacitor1240) starts being charged by the current1231and the voltage1245starts increasing with time. For example, from time t54to time t55, the capacitor1240remains being charged by the current1231and the voltage1245remains increasing with time. As an example, at time t55, the capacitor1240is discharged and the voltage1245drops to the ground voltage (e.g., 0) volts).

In some embodiments, the comparator1220receives the sampled voltage1211(e.g., V4) and the voltage1245(e.g., Vm) and generates the turning-off control signal943(e.g., ZVS_off) based at least in part on the sampled voltage1211(e.g., V4) and the voltage1245(e.g., Vm). For example, if the voltage1245(e.g., Vm) becomes larger than the turning-off control signal943(e.g., ZVS_off), the turning-off control signal943(e.g., ZVS_off) changes from the logic low level to the logic high level. As an example, in response to the turning-off control signal943(e.g., ZVS_off) changing from the logic low level to the logic high level, the capacitor1240is discharged and the voltage1245drops to the ground voltage (e.g., 0 volts), causing the turning-off control signal943(e.g., ZVS_off) to change from the logic high level to the logic low level.

As shown inFIG.4, the asymmetrical half-bridge fly back switch-mode power converter300includes the turning-off controller940as shown inFIG.12and the turning-on enablement controller960as shown inFIG.7according to certain embodiments. In some examples, the turning-off controller940as shown inFIG.12and the turning-on enablement controller960as shown inFIG.7share one common sampling unit. For example, the sampling unit710and the sampling unit1210are one sampling unit. In certain examples, the sampled voltage711(e.g., V1) and the sampled voltage1211(e.g., V4) are one voltage, and the sampled voltage713(e.g., V2) and the sampled voltage1213(e.g., V5) are one voltage. For example, the sampled voltage711(e.g., V1) is equal to mix(Vin−N×Vo), and the sampled voltage1211(e.g., V4) is equal to m3×(Vin−N×Vo), wherein m1and m3are equal. As an example, the sampled voltage713(e.g., V2) is equal to m2×N×Vo, and the sampled voltage1213(e.g., V5) is equal to m4×N×Vo, wherein m2and m4are equal.

In some embodiments, the time duration when the voltage1245(e.g., Vm) increases from 0 volts to the sampled voltage1211(e.g., V4) is determined as follows:

where T1represents the time duration when the voltage1245(e.g., Vm) increases from 0 volts to the sampled voltage1211(e.g., V4). Additionally, C1represents the capacitance of the capacitor1240, and k is a predetermined constant as shown in Equation 8. Moreover, m1is a predetermined constant, which is equal to m3. Also, m2is a predetermined constant, which is equal to m4. Additionally, Vinrepresents the voltage351, and Vorepresents the output voltage392. Moreover, N represents the turns ratio that is equal to the ratio of the number of turns in the primary winding310to the number of turns in the secondary winding312.

In certain embodiments, the time duration when the voltage1245(e.g., Vm) increases from 0 volts to the sampled voltage1211(e.g., V4) is the time duration from time t54to time t55. For example, based on Equations 7 and 9, in order for the voltage327to become equal to the voltage351at time t56, the following condition needs to be satisfied:

where C1represents the capacitance of the capacitor1240, and k is a predetermined constant as shown in Equation 8. Additionally, m1is a predetermined constant, which is equal to m3. Also, m2is a predetermined constant, which is equal to m4. Moreover, tdrepresents the resonance period for the resonance of the parasitic capacitor of the transistor320, the parasitic capacitor of the transistor330, the inductor316(e.g., with the primary inductance Lp), and the inductor318(e.g., with the leakage inductance Lr) from time t53to time t54. As an example, if Equation 10 is satisfied, the transistor320can be turned on with low-voltage switching and/or zero-voltage switching in order to improve efficiency of the asymmetrical half-bridge fly back switch-mode power converter300under a light load condition. In some examples, Equation 10 is used to determine the constant k.

Some embodiments of the present disclosure provide an asymmetrical half-bridge fly back switch-mode power converter (e.g., the asymmetrical half-bridge fly back switch-mode power converter300) that is configured to control the time duration (e.g., Tzvsfrom time t54to time t55) when a transistor (e.g., the transistor330) remains turned on before another transistor (e.g., the transistor320) becomes turned on, so that in response to the another transistor (e.g., the transistor320) becoming turned on, the change in the source voltage (e.g., the voltage327) of the another transistor (e.g., the transistor320) is equal to a target value. For example, the target value is equal to zero. As an example, the target value is not equal to zero.

According to certain embodiments, a controller for a power converter includes: a first drive signal generator configured to generate a first drive signal to turn off a first transistor at a first time and turn on the first transistor at a second time, the first transistor being configured to receive an input voltage and related to a primary winding coupled to an auxiliary winding and a secondary winding, the secondary winding being related to an output voltage, the second time being later than the first time: a second drive signal generator configured to: generate a second drive signal to turn on a second transistor at a third time, the second transistor being coupled to the first transistor and related to the primary winding, the third time being later than the first time and being earlier than the second time: change the second drive signal to turn off the second transistor at a fourth time, the fourth time being later than the third time and being earlier than the second time; and change the second drive signal to turn on the second transistor at a fifth time, the fifth time being later than the fourth time and being earlier than the second time: a first controller configured to generate a first control signal based at least in part on a first voltage related to the auxiliary winding and output the first control signal to the second drive signal generator: wherein the second drive signal generator is further configured to: in response to the first control signal changing from a first logic level to a second logic level, change the second drive signal to turn off the second transistor at a sixth time, the sixth time being later than the fifth time and being earlier than the second time. For example, the controller is implemented according to at leastFIG.4,FIG.5,FIG.8, and/orFIG.12.

As an example, the first logic level is a logic low level; and the second logic level is a logic high level. For example, the first controller includes: a sampling unit configured to receive the first voltage and generate a sampled voltage based at least in part on the first voltage; an integration unit configured to receive the sampled voltage and a reference voltage and generate a compensation signal based at least in part on the sampled voltage and the reference voltage; a ramp signal generator configured to generate a ramp signal; and a comparator configured to receive the compensation signal and the ramp signal and generate the first control signal based at least in part on the comparison signal and the ramp signal. As an example, the sampling unit is further configured to generate the sampled voltage to represent the first voltage immediately before the first transistor becomes turned on. For example, the sampling unit is further configured to generate the sampled voltage to represent a change in the first voltage in response to the first transistor changing from being turned off to being turned on. As an example, the integration unit is further configured to: determine a difference between the sampled voltage and the reference voltage; and integrate the difference over time to generate the compensation signal. For example, the comparator is further configured to: in response to the ramp signal becoming larger than the compensation signal, change the first control signal from the first logic level to the second logic level.

As an example, the first controller includes: a sampling unit configured to receive the first voltage and generate a first sampled voltage and a second sampled voltage based at least in part on the first voltage; a voltage-controlled current source configured to receive the second sampled voltage and generate a first current based at least in part on the second sampled voltage; a first switch coupled to the voltage-controlled current source and configured to receive a second control signal; a capacitor coupled to the first switch and configured to generate a second voltage; a comparator configured to receive the first sampled voltage and the second voltage and generate the first control signal based at least in part on the first sampled voltage and the second voltage; and a second switch coupled to the first switch and the capacitor and configured to receive the first control signal. For example, the sampling unit is further configured to: generate the first sampled voltage to represent the first voltage when the first transistor is turned on and the second transistor is turned off; and generate the second sampled voltage to represent the first voltage when the first transistor is turned off and the second transistor is turned on. As an example, the voltage-controlled current source is further configured to generate the first current that is equal to the second sampled voltage multiplied by a predetermined constant. For example, the second control signal is configured to turn on the first switch when the second transistor becomes turned on at the fifth time.

As an example, when the first switch is closed and the second switch is open, the capacitor is configured to be charged by the first current to increase the second voltage. For example, the comparator is further configured to: in response to the second voltage becoming larger than the first sampled voltage, change the first control signal from the first logic level to the second logic level to turn off the second transistor at the sixth time. As an example, the first control signal is further configured to close the second switch when the first control signal changes from the first logic level to the second logic level; and the second control signal is further configured to open the second switch when the second control signal changes from the second logic level to the first logic level; wherein the first control signal changes from the first logic level to the second logic level and the second control signal changes from the second logic level to the first logic level at a same time. For example, when the second switch is closed and the first switch is open, the capacitor is configured to be discharged to decrease the second voltage.

According to some embodiments, a controller for a power converter includes: a first drive signal generator configured to generate a first drive signal to turn off a first transistor at a first time and turn on the first transistor at a second time, the first transistor being configured to receive an input voltage and related to a primary winding coupled to an auxiliary winding and a secondary winding, the secondary winding being related to an output voltage, the second time being later than the first time; a second drive signal generator configured to generate a second drive signal to turn on a second transistor at a third time and turn off the second transistor at a fourth time, the second transistor being coupled to the first transistor and related to the primary winding, the third time being later than the first time, the fourth time being later than the third time and being earlier than the second time; an enablement controller configured to generate an enablement control signal based at least in part on a first voltage related to the auxiliary winding and output the enablement control signal to the second drive signal generator; and a first controller configured to generate a first control signal based at least in part on a second voltage related to the output voltage and output the first control signal to the second drive signal generator; wherein the second drive signal generator is further configured to: in response to the first control signal changing from a first logic level to a second logic level when the enablement control signal is at a third logic level, change the second drive signal to turn on the second transistor at a fifth time, the fifth time being later than the fourth time and being earlier than the second time; and in response to the first control signal changing from the first logic level to the second logic level when the enablement control signal is at a fourth logic level, not change the second drive signal so that the second transistor remains being turned off from the fourth time to the second time; wherein: the first logic level and the second logic level are different; and the third logic level and the fourth logic level are different. For example, the controller is implemented according to at leastFIG.4,FIG.5,FIG.6, and/orFIG.7.

As an example, the first logic level is a logic low level; and the second logic level is a logic high level. For example, the third logic level is the logic high level; and the fourth logic level is the logic low level. As an example, the second drive signal generator is further configured to: in response to the second drive signal being changed to turn on the second transistor at the fifth time, change the second drive signal to turn off the second transistor at a sixth time, the sixth time being later than the fifth time and earlier than the second time.

For example, the controller of claim16wherein the enablement controller includes: a sampling unit configured to receive the first voltage and generate a first sampled voltage and a second sampled voltage based at least in part on the first voltage; and a comparison unit configured to receive the first sampled voltage and the second sampled voltage and generate the enablement control signal based at least in part on the first sampled voltage and the second sampled voltage. As an example, the sampling unit is further configured to: generate the first sampled voltage to represent the first voltage when the first transistor is turned on and the second transistor is turned off; and generate the second sampled voltage to represent the first voltage when the first transistor is turned off and the second transistor is turned on.

For example, the comparison unit is further configured to: generate the enablement control signal at a logic high level if the first sampled voltage is larger than the second sampled voltage; and generate the enablement control signal at a logic low level if the first sampled voltage is smaller than the second sampled voltage. As an example, the comparison unit is further configured to: generate the enablement control signal at a logic high level if the first sampled voltage is larger than the second sampled voltage multiplied by a predetermined constant; and generate the enablement control signal at a logic low level if the first sampled voltage is smaller than the second sampled voltage multiplied by the predetermined constant.

According to certain embodiments, a method for a power converter includes: generating a first drive signal to turn off a first transistor at a first time, the first transistor being configured to receive an input voltage and related to a primary winding coupled to an auxiliary winding and a secondary winding, the secondary winding being related to an output voltage; changing the first drive signal to turn on the first transistor at a second time, the second time being later than the first time; generating a second drive signal to turn on a second transistor at a third time, the second transistor being coupled to the first transistor and related to the primary winding, the third time being later than the first time and being earlier than the second time; changing the second drive signal to turn off the second transistor at a fourth time, the fourth time being later than the third time and being earlier than the second time; changing the second drive signal to turn on the second transistor at a fifth time, the fifth time being later than the fourth time and being earlier than the second time; generating a first control signal based at least in part on a first voltage related to the auxiliary winding; and in response to the first control signal changing from a first logic level to a second logic level, changing the second drive signal to turn off the second transistor at a sixth time, the sixth time being later than the fifth time and being earlier than the second time. For example, the method is implemented according to at leastFIG.4,FIG.5,FIG.8, and/orFIG.12.

According to some embodiments, a method for a power converter includes: generating a first drive signal to turn off a first transistor at a first time, the first transistor being configured to receive an input voltage and related to a primary winding coupled to an auxiliary winding and a secondary winding, the secondary winding being related to an output voltage; changing the first drive signal to turn on the first transistor at a second time, the second time being later than the first time; generating a second drive signal to turn on a second transistor at a third time, the second transistor being coupled to the first transistor and related to the primary winding, the third time being later than the first time and being earlier than the second time; changing the second drive signal to turn off the second transistor at a fourth time, the fourth time being later than the third time and being earlier than the second time; generating an enablement control signal based at least in part on a first voltage related to the auxiliary winding: generating a first control signal based at least in part on a second voltage related to the output voltage; in response to the first control signal changing from a first logic level to a second logic level when the enablement control signal is at a third logic level, changing the second drive signal to turn on the second transistor at a fifth time, the fifth time being later than the fourth time and being earlier than the second time; and in response to the first control signal changing from the first logic level to the second logic level when the enablement control signal is at a fourth logic level, not changing the second drive signal so that the second transistor remains being turned off from the fourth time to the second time; wherein: the first logic level and the second logic level are different; and the third logic level and the fourth logic level are different. For example, the method is implemented according to at leastFIG.4,FIG.5,FIG.6, and/orFIG.7.

For example, some or all components of various embodiments of the present disclosure each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. As an example, some or all components of various embodiments of the present disclosure each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. For example, various embodiments and/or examples of the present disclosure can be combined.

Although specific embodiments of the present disclosure have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments.