According to one embodiment, a semiconductor device has a stack of first films and first insulating films stacked in a first direction. The first films include an electrode layer and a second insulating film on an upper face, a lower face, and a side face of the electrode layer. A semiconductor layer extends in the first direction. A charge accumulating layer is between the semiconductor layer and the film stack in a second direction and has first portions between the first films and the semiconductor layer and second portions between the first insulating films and the semiconductor layer. The first portions each have a first thickness in the second direction, and the second portions each have a second thickness less than the first in the second direction. First portions have a first width, and first films have a second width that is less than the first width.

CROSS-REFERENCE TO RELATED APPLICATION (S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-203500, filed Dec. 20, 2022, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and a method for manufacturing a semiconductor device.

BACKGROUND

An issue in the manufacturing of three-dimensional memory array chips is the characteristics of charge accumulating layers in the memory transistors.

DETAILED DESCRIPTION

Embodiments provide a semiconductor device and a method for manufacturing the semiconductor device including a charge accumulating layer capable of achieving desired characteristics.

In general, according to one embodiment, a semiconductor device includes a film stack with first films and first insulating films alternatingly stacked in a first direction. The first films each include an electrode layer and a second insulating film disposed on an upper face, a lower face, and a side face of the electrode layer. A semiconductor layer extends in the first direction. A charge accumulating layer is between the semiconductor layer and the film stack in a second direction perpendicular to the first direction. The charge accumulating layer has first portions between the first films and the semiconductor layer in the second direction and second portions between the first insulating films and the semiconductor layer in the second direction. The first portions each have a first thickness in the second direction. The second portions each have a second thickness in the second direction. The second thickness is less than the first thickness. At least one of the first portions has a first width in the first direction, and at least one of the first films has a second width in the first direction. The second width is less than the first width.

Certain example embodiments will now be described with reference to the accompanying drawings. In the drawings, the same or substantially the same components are denoted by the same reference symbols and redundant description will be omitted.

First Embodiment

FIG.1is a cross-sectional view illustrating a structure of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment includes a three-dimensional semiconductor memory array.

The semiconductor device according to the first embodiment includes a substrate1, a film stack2, multiple insulating films3, and a pillar4. The film stack2includes multiple films2aand multiple films2b. The films2aeach include a block insulating film11and an electrode layer12. The electrode layer12of the film2aincludes a barrier metal layer12aand an electrode material layer12b. The films2beach include an insulating film13and multiple insulating films14. The pillar4includes multiple block insulating films21, a charge accumulating layer22, a tunnel insulating film23, a channel semiconductor layer24, and a core insulating film25. The charge accumulating layer22(a charge storage layer) includes multiple outer peripheral charge accumulating layers22aand an inner peripheral charge accumulating layer22b. The film2ais an example of the first film. The film2b, the block insulating film11, the block insulating film21, the tunnel insulating film23, the insulating film13, and the insulating film14are examples of the first to six insulating films, respectively. The inner peripheral charge accumulating layer22band the outer peripheral charge accumulating layers22aare examples of the first and second layers, respectively.

The substrate1is, for example, a semiconductor substrate such as a silicon (Si) substrate.FIG.1shows an X direction and a Y direction that are parallel to the surface of the substrate1and perpendicular to each other, and a Z direction orthogonal to the surface of the substrate1. The X direction, the Y direction, and the Z direction are orthogonal to each other. In this specification, the positive Z direction is regarded as the upward direction, and the negative Z direction as the downward direction. The negative Z direction may or may not coincide with the direction of gravity. The Z direction is an example of the first direction. The X direction is an example of the second direction.

The film stack2is formed on the substrate1and alternatingly includes the films2aand the films2bstacked along the Z direction. The film stack2may be formed directly on the substrate1or with another film interposed between the film stack2and the substrate1.

The films2aeach include an electrode layer12and the block insulating films11disposed on the upper face, the lower face, and a side face of the electrode layer12. The block insulating film11is, for example, an aluminum oxide (Al2O3) film. The aluminum in the block insulating film11is an example of a metal element in the second insulating film. The electrode layer12includes the barrier metal layer12adisposed on the upper face, the lower face, and the side face of the block insulating film11in sequence, and the electrode material layer12b. The barrier metal layer12ais, for example, a titanium nitride (TiN) film. The electrode material layer12bis, for example, a tungsten (W) layer. The electrode layer12functions as a word line or a select line of the three-dimensional semiconductor memory.

The films2beach include the insulating film13, the insulating film14disposed on the upper face of the insulating film13, and the insulating film14disposed on the lower face of the insulating film13. Each of the insulating films13and14is, for example, a SiO2film.

The insulating films3are formed on side faces of the insulating films13. The insulating films3are formed by separating an etching stopper film into multiple pieces, which will be described below. Each insulating film3is, for example, a SiO2film.

The pillar4is formed on the substrate1and inside the film stack2. The pillar4is columnar in shape and extends in the Z direction. The pillar4includes the block insulating films21, the charge accumulating layer22, the tunnel insulating film23, the channel semiconductor layer24, and the core insulating film25that are disposed on a side face of the film stack2in sequence. The pillar4provides multiple memory cells of the three-dimensional semiconductor memory.

The block insulating films21are formed on side faces of the films2a. Each of the block insulating film21is, for example, a SiO2film. The block insulating films21are each disposed between the two insulating films14neighboring each other in the Z direction.

The charge accumulating layer22includes the outer peripheral charge accumulating layers22adisposed on side faces of the block insulating films21and the inner peripheral charge accumulating layer22b. The inner peripheral charge accumulating layer22bis disposed as a continuous film along the inner side faces of the outer peripheral charge accumulating layers22a. Thus, the charge accumulating layer22has multiple thick portions (combined thicknesses of the inner peripheral charge accumulating layer22band an outer peripheral charge accumulating layer221) generally next to the films2aand multiple thin portions (just the thickness of the inner peripheral charge accumulating layer22b) generally next to the films2b. That is, the thick portions are at the same height position (level) as the films2a, and the thin portions are at the same position level as the films2b. The thick portions each include the outer peripheral charge accumulating layer22aand the inner peripheral charge accumulating layer22bwhile the thin portions include just the inner peripheral charge accumulating layer22bfrom among the outer peripheral charge accumulating layer22aand the inner peripheral charge accumulating layer22b. The thick portion is disposed on a side face of a block insulating film21and the side faces of two insulating films14while the thin portion is disposed on a side face of an insulating film3. The charge accumulating layer22is thus continuously disposed on side faces of the films2aand2b, with the block insulating films21being interposed between the charge accumulating layer22and the film2aand the insulating films3being interposed between the charge accumulating layer22and the film2b.

The outer peripheral charge accumulating layer22aand the inner peripheral charge accumulating layer22bare, for example, silicon nitride (SiN) films. In the first embodiment, the charge accumulating layer22further contains oxygen as impurities. In the first embodiment, the number of oxygen atoms in the charge accumulating layer22is 12% (atomic %) or less of the total number of silicon atoms, nitrogen atoms, and oxygen atoms in the charge accumulating layer22. In other words, the charge accumulating layer22of the first embodiment has a ratio of the number of oxygen atoms to the total number of silicon atoms, nitrogen atoms, and oxygen atoms of 0.12 or less. This ratio can be analyzed by, for example, transmission electron microscopic energy-dispersive X-ray (TEM-EDX) spectroscopy. In the first embodiment, the charge accumulating layer22has an oxygen content of, for example, 1.0×1021atoms/cm3or less. The charge accumulating layer22can accumulate signal charges of the three-dimensional semiconductor memory. In the pillar4, the outer peripheral charge accumulating layers22ain different memory cells are not continuous with each other in the Z direction while the inner peripheral charge accumulating layer22bin the memory cells is continuous in the Z direction.

The tunnel insulating film23is formed on a first side face of the charge accumulating layer22. The tunnel insulating film23is, for example, a silicon oxynitride (SiON) film.

The channel semiconductor layer24is formed on a side face of the tunnel insulating film23. The channel semiconductor layer24is, for example, a polysilicon layer. The channel semiconductor layer24is formed on the first side face of the charge accumulating layer22, with the tunnel insulating film23being interposed therebetween. The channel semiconductor layer24functions as a channel of the three-dimensional semiconductor memory.

The core insulating film25is formed on a side face of the channel semiconductor layer24. The core insulating film25is, for example, a SiO2film.

FIG.2is an enlarged cross-sectional view illustrating a structure of the semiconductor device according to the first embodiment.

The charge accumulating layer22has thick portions, with a large thickness T1, generally next to the films2ain the X direction and thin portions, with a small thickness T2, generally next to the films2bin the X direction. The thick portions each run over the outer peripheral charge accumulating layer22aand the inner peripheral charge accumulating layer22b, while the thin portions each run over only the inner peripheral charge accumulating layer22bamong the outer peripheral charge accumulating layer22aand the inner peripheral charge accumulating layer22b. The thickness T2is less than the thickness T1(T2<T1). The thick portion is an example of the first portion and the thin portion is an example of the second portion. The thickness T1is an example of the thickness of the first film and the thickness T2is an example of the thickness of the second film.

The thickness T1refers to a dimension of the thick portion along a radial direction of the pillar4. The thickness T2refers to a dimension of the thin portion along a radial direction of the pillar4. The central axis of the pillar4is shown in an X-Z cross-section inFIG.2. Thus, inFIG.2, the thickness T1is the dimension of the thick portion in the X direction and the thickness T2is the dimension of the thickness of the thin portion in the X direction.

FIG.2shows a width W1of the thick portion of the charge accumulating layer22in the Z direction and a width W2of each film2ain the Z direction. InFIG.2, the thick portion is disposed on side faces of one block insulating film21and two insulating films14. The block insulating film21is disposed on a side face of one film2a. Thus, the width W2of the film2ain the Z direction is less than the width W1of the thick portion in the Z direction (W2<W1). The width W1is an example of the first width and the width W2is an example of the second width. The widths W1and W2in the first embodiment satisfy the condition of W2<W1≤2×W2.

It is noted that the width W1may be a different value for the different thick portions of the charge accumulating layer22and/or that the width W2may have a different value for the different films2a. In this case, the relation of W2<W1holds between each thick portion and film2adisposed on a side face of the thick portion, that is, between the thick portion and the film2athat correspond to each other. The relation of W2<W1may or may not hold between all of the thin portions and the films2athat correspond to each other and/or between some of the thick portions and the films2athat correspond to each other.

The charge accumulating layer22according to the first embodiment includes the thick portions with the large thickness T1and the thin portions with the small thickness T2. Thus, each thick portion can accumulate signal charges of a memory cell to suppress escape of the signal charges of the memory cell out of the charge accumulating layer22or into another memory cell.

In this case, the erasure characteristics of the memory cell may be reduced due to the small thickness T2of the thin portion. Fortunately, the thick portion according to the first embodiment has the width W1greater than the width W2of the film2a. Thus, the large width W1of the thick portion and the small width of the thin portion can serve to mitigate a reduction in erasure characteristics otherwise due to the thin portion.

FIGS.3A to7Bare cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment.

Initially, a substrate1is prepared for formation of a film stack2on a substrate1(seeFIG.3A). The film stack2includes multiple sacrificial layers31and multiple insulating films13alternatingly stacked in the Z direction. The film stack2is formed by alternatingly stacking the sacrificial layers31and the insulating films13on the substrate1. The film stack2may be formed directly on the substrate1or with another film interposed between the film stack2and the substrate1. The sacrificial layers31are, for example, SiN films. The sacrificial layers31are an example of the second film.

Multiple memory holes MH are subsequently made in the film stack2by lithography and reactive ion etching (RIE) (seeFIG.3B).FIG.3Billustrates one of the memory holes MH. The memory holes MH are each columnar in shape, extend in the Z direction, and are circular in shape in plan view.

An insulating film3, an inner peripheral charge accumulating layer22b, a tunnel insulating film23, a channel semiconductor layer24, and a core insulating film25are subsequently formed, in sequence, on a side face of the film stack2in the memory hole MH (seeFIG.4A). As a result, a partial pillar4is formed in the memory hole MH. The insulating film3, the inner peripheral charge accumulating layer22b, the tunnel insulating film23, the channel semiconductor layer24, and the core insulating film25are formed, in sequence, on side faces of the sacrificial layers31and the insulating films13. The insulating film3has a thickness of about 2 nm. The inner peripheral charge accumulating layer22bhas a thickness of about 2 In the first embodiment, the thickness of the inner peripheral charge accumulating layer22bis set to a thickness T2. The tunnel insulating film23has a thickness of about 5 nm. The channel semiconductor layer24has a thickness of about 5 nm. The core insulating film25has a thickness of about 2 nm.

Multiple vertical slits are formed in the film stack2to permit removal of the sacrificial layers31by a chemical solution, such as a phosphoric acid solution, entering from the slits (seeFIG.4B). As a result, multiple recesses C are formed in the film stack2. The recesses C are an example of a first recess.

The insulating film3exposed in each recess C is subsequently removed by wet etching (seeFIG.5A). As a result, the insulating film3is separated into multiple insulating films3remaining on side faces of the insulating films13. Furthermore, the insulating films13forming the upper and lower faces of the recess C are etched by wet etching such that the thicknesses of the insulating films13in the Z direction are reduced.FIG.5Aillustrates the shapes of the insulating films3and13before wet etching with a dashed line. The wet etching uses, for example, a chemical solution, such as a hydrofluoric acid solution.

The inner peripheral charge accumulating layer22bexposed in the recess C is next pretreated for formation of an outer peripheral charge accumulating layer22aon a side face of the inner peripheral charge accumulating layer22bin the recess C (seeFIG.5B). The outer peripheral charge accumulating layer22aaccording to the first embodiment is formed by selective growth from the side face of the inner peripheral charge accumulating layer22bin the recess C. As a result, the outer peripheral charge accumulating layer22aaccording to the first embodiment is selectively formed on the side face of the inner peripheral charge accumulating layer22b, among the side face of the inner peripheral charge accumulating layer22band the upper and lower faces of the insulating films13and3in the recess C. In other words, the outer peripheral charge accumulating layer22aaccording to the first embodiment is selectively formed on a side face of the recess C among the faces thereof. The additional aspects of such selective growth will be described below.

In the step ofFIG.5B, the charge accumulating layer22including the inner peripheral charge accumulating layer22band the outer peripheral charge accumulating layers22ais formed in the pillar4. As a result, the charge accumulating layer22has multiple thick portions, with a large thickness T1, lateral to the recesses C and multiple thin portions, with a small thickness T2, lateral to the insulating films13. Furthermore, the thick portions of the charge accumulating layer22have a width W1in the Z direction. It is noted that the inner peripheral charge accumulating layer22bis pretreated for removal of a naturally oxidized film from the side face, exposed laterally to the recesses C, of the inner peripheral charge accumulating layer22b. This can suppress inhibition of the selective growth by the naturally oxidized film.

A cap insulating film32is subsequently formed on a second side face of the charge accumulating layer22and the upper face of a first insulating film13and the lower face of a second insulating film13in each recess C (seeFIG.6A). The cap insulating film32is, for example, a SiN film. The cap insulating film32is an example of the seventh insulating film. In the first embodiment, the pretreatment of the inner peripheral charge accumulating layer22b, the selective growth of the outer peripheral charge accumulating layer22aand the formation of the cap insulating film32are performed in situ (e.g., without removal from the process chamber). This can suppress formation of a naturally oxidized film on the side face of the outer peripheral charge accumulating layer22a.

The cap insulating film32in the recess C is subsequently oxidized (seeFIG.6B). As a result, the cap insulating film32(SiN film) in the recess C is converted into a SiO2film. The SiO2film is formed into one block insulating film21and two insulating films14in the recess C. The block insulating film21is formed on the second side face of the charge accumulating layer22. The insulating films14are formed on the lower face, forming the upper face of the recess C, of the first insulating film13and the upper face, forming the lower face of the recess C, of the second insulating film13, respectively. It is noted that, although6B illustrates a boundary between the block insulating film21and the insulating films14in the recess C for clarity of description, both the block insulating film21and the insulating films14in the recess C can be portions of the same SiO2film and that such a boundary need not be present or distinct.

In the step ofFIG.6B, the content of oxygen atoms (impurity atoms) in the charge accumulating layer22is decreased by oxidation of the cap insulating film32. Thus, the charge accumulating layer22according to the first embodiment is converted into a SiN layer with a low content of oxygen atoms (as impurity atoms). In the first embodiment, the number of oxygen atoms in the charge accumulating layer22is 12% (atomic %) or less of the total number of silicon atoms, nitrogen atoms, and oxygen atoms in the charge accumulating layer22. When the outer peripheral charge accumulating layer22ahas an oxygen content different from that of the inner peripheral charge accumulating layer22b, the condition of 12% or less may hold for both or either of the outer peripheral charge accumulating layer22aand the inner peripheral charge accumulating layer22b.

It is noted that the step ofFIG.6Bmay be performed to oxidize only a portion of the cap insulating film32in the recess C. In this case, the cap insulating film32of SiN remains as a portion of the outer peripheral charge accumulating layer22a, so that the thickness T1of each thick portion increases. Alternatively, the step ofFIG.6Bmay be performed to oxidize not only the cap insulating film32but also a portion of the outer peripheral charge accumulating layer22ain the recess C. In this case, the outer peripheral charge accumulating layer22aof SiO2becomes portions of the block insulating film21and the insulating films14, so that the thickness T1decreases. After the step ofFIG.6A, a treatment for modifying the cap insulating film32may be performed. After the step ofFIG.6B, a treatment for modifying the block insulating film21and the insulating films14may be performed. Instead of the steps ofFIGS.6Aand6B, a SiO2film that is converted into the block insulating film21and the insulating films14may be formed in the recess C by chemical vapor deposition (CVD).

A block insulating film11is subsequently formed on the block insulating film21and the insulating films14in the recess C (seeFIG.7A).

A barrier metal layer12aand an electrode material layer12bare subsequently formed in sequence on the block insulating film11in the recess C (seeFIG.7B). As a result, an electrode layer12is formed with the block insulating film11therearound in the recess C. In this manner, a film stack2including multiple films2aand multiple films2bare formed on the substrate1. Each film2ais formed so as to include the block insulating film11and the electrode layer12. Each film2bis formed so as to include the insulating films13and14. Since the insulating films14are formed in the recess C in the first embodiment, a width W2of the film2ain the Z direction is less than a width W1of the thick portion of the charge accumulating layer22in the Z direction.

Thereafter, various layers, such as a wiring layer, a plug layer, and an interlayer insulating film, are formed on the substrate1. In this manner, the semiconductor device illustrated inFIGS.1and2is manufactured.

FIGS.8A to8Care cross-sectional views illustrating the details of the method for manufacturing the semiconductor device according to the first embodiment.

FIG.8Ais a partial view ofFIG.5A. In the first embodiment, before formation of the outer peripheral charge accumulating layer22a(e.g., a SiN layer) on the side face of the inner peripheral charge accumulating layer22b(e.g., a SiN layer) in the recess C, an inhibitor may be applied onto the insulating films13and3(e.g., SiO2films) (seeFIG.8B). As a result, inhibitor regions33are formed on the insulating films13and3. The inhibitor regions33contain an inhibitor. In this context, an inhibitor is a substance that suppresses the adhering of a silicon precursor to the insulating films13and3. InFIG.8B, the inhibitor regions33are formed on the upper faces of first insulating films13and3and the lower faces of second insulating films13and3in the recess C, and side faces of the first and second insulating films13external to the recess c.

The silicon precursor is subsequently used for formation of the outer peripheral charge accumulating layer22aon a side face of the inner peripheral charge accumulating layer22bin the recess C (seeFIG.8C). Since the inhibitor regions33are formed on the insulating films13and3inFIG.8C, the silicon precursor preferentially adheres to the side face of the inner peripheral charge accumulating layer22band is unlikely to adhere to the insulating film13and the insulating film3. Thus, the first embodiment can selectively form the outer peripheral charge accumulating layer22aon the side face of the inner peripheral charge accumulating layer22bamong the side face of the inner peripheral charge accumulating layer22band the upper faces of the first insulating films13and3and the lower faces of the second insulating films13and3in the recess C.

FIG.9is a cross-sectional view illustrating advantageous effects of the semiconductor device according to the first embodiment.

As illustrated inFIG.9, the signal charges of each memory cell are accumulated in the charge accumulating layer22in the memory cell. The signal charges of the memory cell may escape into another memory cell as indicated by arrows A1(vertical escape) or out of the charge accumulating layer22as indicated by an arrow A2(horizontal escape). Fortunately, the charge accumulating layer22according to the first embodiment has the thick portions with the thickness T1and the thin portions with the thickness T2. Thus, each thick portion can accumulate the signal charges of a memory cell to suppress escape of the signal charges from the memory cell into another memory cell or out of the charge accumulating layer22. For example, the small thickness T2of the thin portion hinders passage of the signal charges through the thin portion and can thus effectively suppress horizontal escape of the signal charges.

In this case, the erasure characteristics of the memory cell may be reduced due to the small thickness T2of the thin portion. This is because the small thickness T2of the thin portion hinders passage of the signal charges targeted for erasure through the thin portion. Fortunately, the thick portion according to the first embodiment has the width W1greater than the width W2of the film2a. Thus, the large width W1of the thick portion and the small width of the thin portion can suppress a reduction in erasure characteristics otherwise due to the thin portion. This is because the small width of the thin portion facilitates passage of the signal charges targeted for erasure through the thin portion. Thus, in the first embodiment, the width of the thin portion is preferably adjusted to a desired value for suppression of the horizontal escape and a reduction in erasure characteristics.

FIG.10is a cross-sectional view showing a structure of a semiconductor device according to a comparative example differing from the first embodiment.

Although the semiconductor device of the present comparative example depicted inFIG.10has a structure similar to that of the semiconductor device according to the first embodiment inFIG.1, the films2bin comparative example do not include insulating films14. As a result, the charge accumulating layer22of the comparative example has a shape different from that of the charge accumulating layer22in the first embodiment. Additional aspects related to this difference will be described below.

FIG.11is a cross-sectional view illustrating the structure of the semiconductor device according to the comparative example.

Although the charge accumulating layer22in the comparative example has multiple thick portions with a large thickness T1and multiple thin portions with a small thickness T2, similar to the charge accumulating layer22in the first embodiment, the film2bin the comparative example includes no insulating films14. Thus, the thick portions are each disposed on a side face of a block insulating film21. The block insulating film21is disposed on a side face of a film2a. Thus, in the comparative example, a width W2of the film2ain the Z direction is equal to a width W1of the thick portion in the Z direction.

In this case, the erasure characteristics of each memory cell may be reduced due to the small thickness T2of the thin portion. This is because the small thickness T2of the thin portion hinders passage of the signal charges targeted for erasure through the thin portion. A large width of the thin portion also hinders passage of the signal charges targeted for erasure through the thin portion. In contrast, the thin portion in the first embodiment has a small width and thereby facilitates passage of the signal charges targeted for erasure through the thin portion. Thus, the first embodiment can avoid a reduction in erasure characteristics otherwise caused due to the thin portion.

FIGS.12A and12Bare cross-sectional views illustrating a method for manufacturing the semiconductor device according to the comparative example.

The cross-sectional view ofFIG.12Acorresponds in general to that ofFIG.5A. In the comparative example, the thickness of each outer peripheral charge accumulating layer22ais large, as illustrated inFIG.12A. A portion of the outer peripheral charge accumulating layer22ais oxidized to converted into a block insulating film21(seeFIG.12B). This enables formation of the block insulating film21on a side face of the outer peripheral charge accumulating layer22awithout formation of the insulating films14. A drawback in this case is a reduction in erasure characteristics of each memory cell due to the small thickness T2and the large width of the thin portion, as described above. In addition, natural oxidization of the outer peripheral charge accumulating layer22amay reduce the write characteristics of the memory cell.

In contrast, the first embodiment uses a pretreatment on the inner peripheral charge accumulating layer22b, then selective growth of the outer peripheral charge accumulating layer22a, and formation of the cap insulating film32in situ (seeFIGS.5B and6A). This can suppress (avoid) the natural oxidization of the outer peripheral charge accumulating layer22athat reduces the write characteristics of the memory cell. Furthermore, formation of the block insulating film14and the insulating film14from the cap insulating film32(seeFIG.6B) can reduce the width W2of the film2ain the Z direction compared to the width W1of the thick portion in the z direction. This can suppress a reduction in erasure characteristics of the memory cell due to the thin portion.

As described above, the charge accumulating layer22according to the first embodiment has thick portions with a large thickness T1and thin portions with a small thickness T2. The width W1of each thick portion is greater than the width W2of the film2a. Thus, the first embodiment can provide a charge accumulating layer22having desired characteristics. For example, the first embodiment can provide a charge accumulating layer22that improves the erasure and write characteristics of a memory cell.

Second Embodiment

FIG.13is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment.

Although the semiconductor device according to the second embodiment inFIG.13has a structure similar to that of the semiconductor device according to the first embodiment inFIG.1, the difference between the widths W1and W2is large in the first embodiment while the difference between the widths W1and W2is small in the second embodiment.

FIG.14is an enlarged cross-sectional view illustrating the structure of the semiconductor device according to the second embodiment.

The charge accumulating layer22according to the second embodiment has multiple thick portions with a large thickness T1and multiple thin portions with a small thickness T2, similar to the charge accumulating layer22in the first embodiment. Thus, each thick portion can accumulate signal charges of a memory cell to suppress escape of the signal charges of the memory cell out of the charge accumulating layer22or into another memory cell.

In the second embodiment, a width W2of each film2ain the Z direction is less than a width W1of the thick portion in the Z direction in the first embodiment. Thus, the large width W1of the thick portion and the small width of the thin portion can avoid a reduction in erasure characteristics due to the thin portion.

While the difference between the widths W1and W2is large in the first embodiment, the difference between the widths W1and W2is small in the second embodiment. Thus, the first embodiment may have more substantial effects for avoiding a reduction in erasure characteristics while the second embodiment has more limited effects for avoiding a reduction in erasure characteristics. The shape of the charge accumulating layer22according to the second embodiment is preferably employed when the issue with a reduction in erasure characteristics is considered to be less serious or of less concern.

FIGS.15A and15Bare cross-sectional views illustrating a method for manufacturing the semiconductor device according to the second embodiment.

Initially, the steps ofFIGS.3A to6Aare performed as in the first embodiment. The cross-sectional view ofFIG.15Acorresponds in general to that ofFIG.6A. A cap insulating film32in each recess C is oxidized as in the step ofFIG.6B(seeFIG.15B). As a result, the cap insulating film32(e.g., a SiN film) in the recess C is converted into a SiO2film. The SiO2film is formed into one block insulating film2and two insulating films14in the recess C. Since the cap insulating film32has a small thickness in the second embodiment, the block insulating film21and the insulating films14also have small thicknesses.

The steps ofFIGS.7A and7Bare thereafter performed as in the first embodiment. In addition, various layers, such as a wiring layer, a plug layer, and an interlayer insulating film, are formed on a substrate1. In this manner, the semiconductor device illustrated inFIGS.13and14is manufactured.

In the second embodiment, pretreatment of an inner peripheral charge accumulating layer22b, selective growth of an outer peripheral charge accumulating layer22a, and formation of the cap insulating film32are performed in situ as in the first embodiment. This can suppress formation of a naturally oxidized film on the side face of the outer peripheral charge accumulating layer22a.

The charge accumulating layer22in the second embodiment has thick portions with a large thickness T1and thin portions with a small thickness T2. The width W1of the thick portion is greater than the width W2of the film2a. Thus, the second embodiment can provide the charge accumulating layer22having desired characteristics like the first embodiment. For example, the second embodiment can provide a charge accumulating layer22that improves the erasure and write characteristics of a memory cell.