Semiconductor memory device and manufacturing method thereof

A semiconductor memory device of embodiments includes a semiconductor substrate having a first and a second region adjacent to the first region in a first direction, a laminated body including electrode layers laminated on the semiconductor substrate in a second direction, a first insulator splitting the laminated body at the second region in a third direction, and extending in the first and second direction, and branching into two insulator films at the first region, and enclosing continuously a first portion of the laminated body, a contact portion extending in the first portion in the second direction, and a memory portion extending through the laminated body and the first insulator in the second direction at the second region. A first width in the third direction of the first portion is wider than a second width in the third direction of at least one of the electrode layers at the second region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-115500, filed on Jun. 18, 2018; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments of the present invention relate to a semiconductor memory device and a manufacturing method thereof.

BACKGROUND

A stacked semiconductor memory device in which memory cells are stacked in a three-dimensional manner is known. In recent years, for the stacked semiconductor memory device, a manufacturing method in which memory holes are formed at laminated bodies which are split with slits, and, further, memory cells are formed within the memory holes, has been known.

To realize higher speed of driving of the memory cells, a width of a contact portion is preferably large. Meanwhile, to arrange the memory cells in high density, it is preferable to finely split the laminated body with a number of slits. However, in this case, because a width of the laminated body becomes narrow, an area where the contact portion is to be formed becomes small. Therefore, there is a possibility that workability of the contact portion may degrade.

DETAILED DESCRIPTION

Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments.

A semiconductor memory device according to the present embodiment includes a semiconductor substrate, the semiconductor substrate having a first region and a second region adjacent to the first region in a first direction parallel to the semiconductor substrate; a laminated body including a plurality of electrode layers laminated on the first region and the second region of the semiconductor substrate in a second direction perpendicular to the semiconductor substrate; a first insulator splitting the laminated body at the second region in a third direction orthogonal to the first direction and second direction, and extending in the first direction and the second direction, and branching into two insulator films at the first region, and enclosing continuously a first portion of the laminated body with the two insulator films; a contact portion extending in the first portion of the laminated body in the second direction; and a memory portion extending through the laminated body and the first insulator in the second direction at the second region. A first width in the third direction of the first portion of the laminated body is wider than a second width in the third direction of at least one of the electrode layers split with the first insulator at the second region.

First Embodiment

FIG. 1is a plan view of a semiconductor memory device according to a first embodiment. Further,FIG. 2is a cross-section diagram taken along a line A-A illustrated inFIG. 1.

The semiconductor memory device1illustrated inFIG. 1andFIG. 2is a stacked three-dimensional semiconductor memory in which memory cells are stacked in a three-dimensional manner. This semiconductor memory device1includes a semiconductor substrate10, an insulator11, conductive layers20, a laminated body30, a memory portion40and a contact portion50.

In the following description, two directions which are parallel to an upper surface10aof the semiconductor substrate10and which are orthogonal to each other are set as an X direction and a Y direction, and a direction perpendicular to the upper surface10ais set as a Z direction. Further, the Y direction corresponds to the first direction, the Z direction corresponds to the second direction, and the X direction corresponds to the third direction.

The semiconductor substrate10is, for example, a silicon semiconductor substrate. STIs (Shallow Trench Isolations)12are selectively provided at an upper layer portion of the semiconductor substrate10. The upper layer portion of the semiconductor substrate10is segmented into a plurality of semiconductor regions13by the STIs12. Within at least part of the semiconductor regions13, source layers14and drain layers15are formed. Gate insulation films16and gate electrodes17are provided immediately above regions between the source layers14and the drain layers15. By this means, a plurality of field-effect transistors18are formed on the upper surface10aof the semiconductor substrate10.

The conductive layers20are provided between the semiconductor substrate10and the laminated body30. For example, three layers of wirings22are provided in the conductive layers20. Contact plugs23are connected between the semiconductor substrate10and the wiring22in the lowermost layer. The wirings22which are separate from each other in the Z direction are electrically connected through vias24. The wirings22, the contact plugs23and the vias24are provided within an interlayer dielectric60.

An embedded source line21is provided on the wiring22in the uppermost layer. The embedded source line21is, for example, a two-layered film including a lower layer portion containing tungsten (W) and an upper layer portion containing silicon (Si). The embedded source line21is divided into a plurality of portions in the Y direction. Each portion of the embedded source line21is energized via the contact portion50.

The laminated body30is provided on the embedded source line21. At the laminated body30, an electrode film (electrode layer)32and an insulation film33are alternately laminated in the Z direction. The electrode film32contains a metal such as, for example, tungsten. The insulation film33contains, for example, silicon oxide (SiO2). As illustrated inFIG. 1, the laminated body30is split into a plurality of portions in the X direction with a plurality of insulators11. As a result, each electrode film32has a shape of a wiring extending in the Y direction.

The insulator11is an example of the first insulator, and contains silicon oxide. A lower end of the insulator11has contact with the embedded source line21. The insulator11has a shape of a sheet expanding along a YZ plane.

The insulator11and the laminated body30have a tap region RT and a memory cell region RMC. The tap region RT is an example of the first region, and the memory cell region RMC is an example of the second region.

First, the tap region RT will be described. As illustrated inFIG. 1, in the tap region RT, part of the laminated body30is continuously enclosed with the insulator11. Within the tap region RT, a plurality of contact portions50are arranged in a line along the Y direction. A width W1(first width) of the tap region RT in the X direction is wider than a width W2(second width) of the laminated body30in the X direction within the memory cell region RMC. Therefore, a region where the contact portion50with a large radius is to be formed can be sufficiently secured within the tap region RT. Here, a structure of each contact portion50will be described.

As illustrated inFIG. 2, each contact portion50penetrates through the laminated body30in the Z direction. In the present embodiment, lower ends of the contact portions50located at both ends of the line have contact with the embedded source line21, and lower ends of the remaining contact portions50have contact with the wiring22in the uppermost layer.

As illustrated inFIG. 2, an upper end of each contact portion50has contact with an intermediate wiring51. An intermediate wiring53is provided on the intermediate wiring51. The intermediate wiring51and the intermediate wiring53are electrically connected via a plug52. An upper layer wiring55is provided on the intermediate wiring53. The intermediate wiring53and the upper layer wiring55are electrically connected via a plug54. The intermediate wirings51and53, the plugs52and54and the upper layer wiring55are provided within the interlayer dielectric60.

Further, as illustrated inFIG. 2, at each contact portion50, an outer peripheral portion of a conductor50ais covered with the insulation film50b. The conductor50ais insulated from the electrode film32by the insulation film50b.

Subsequently, the memory cell region RMC will be described. The memory cell region RMC is adjacent to the tap region RT in the Y direction. In other words, the tap region RT is disposed between two memory cell regions RMCs which are separate from each other in the Y direction.

As illustrated inFIG. 1, a plurality of memory portions40and a plurality of insulators41are provided within the memory cell region RMC. The plurality of memory portions40are disposed in a zigzag manner.

Each memory portion40penetrates through the insulator11and the laminated body30. As illustrated inFIG. 2, each memory portion40includes a memory film40aand a channel film40benclosed with the memory film40a.

A memory cell is formed at a portion where the memory film40aintersects with the electrode film32. The memory film40aincludes, for example, a tunnel insulation film (not illustrated) in contact with the channel film40b, a charge block film (not illustrated) in contact with the tunnel insulation film, and a charge accumulation film (not illustrated) in contact with the charge block film. The charge block film and the tunnel insulation film are formed as, for example, silicon oxide films. The charge accumulation film is formed as, for example, a silicon nitride (SiN) film.

The channel film40bis formed as, for example, a polysilicon film. The channel film40bis electrically connected to a bit line43via the plug42. The plug42and the bit line43are provided within the interlayer dielectric60.

In the present embodiment, the electrode films32adjacent in the X direction are insulated from each other via the insulator11. Therefore, two memory cells are formed between the memory portion40and two facing electrode films32.

The insulator41penetrates through every other insulator11along the X direction. The insulator41contains, for example, silicon oxide. The insulator41is embedded within a hole formed for forming the electrode film32as will be described later.

Main manufacturing process of the above-described semiconductor memory device1will be simply described below with reference toFIG. 3toFIG. 6.

First, the conductive layers20are formed on the semiconductor substrate10. Subsequently, the laminated body30ais formed on the conductive layers20. Note that, inFIG. 4A,FIG. 4BandFIG. 5AtoFIG. 5D, the conductive layers20are illustrated in a simplified manner. At the laminated body30a, the insulation film32aand the insulation film33are alternately laminated along the Z direction. The insulation film32ais formed as, for example, a silicon nitride film.

Then, as illustrated inFIG. 4AandFIG. 4B, a mask70is formed on the laminated body30a. At the mask70, a mask pattern is formed by a slit70a. The slit70ais formed along a pattern which splits the laminated body30ain the X direction, that is, a pattern of the insulator11.

Then, the laminated body30ais etched in the Z direction from the slit70aof the mask70through, for example, RIE (Reactive Ion Etching). As a result, as illustrated inFIG. 5AandFIG. 5B, a first slit11ais formed on the laminated body30a. Subsequently, as illustrated inFIG. 5CandFIG. 5D, the insulator11is embedded into the first slit11a.

Subsequently, as illustrated inFIG. 6, a first hole50cis formed within the tap region RT, and a second hole40cis formed within the memory cell region RMC. At this time, a diameter of the first hole50cis wider than a diameter of the second hole40c. Subsequently, returning toFIG. 2, the contact portion50is formed within the first hole50c, and the memory portion40is formed within the second hole40c. Note that the first hole50cand the second hole40cmay be formed at the same time or may be formed at different times. In the case where the holes are formed at different times, either of the first hole50cand the second hole40cmay be formed first.

Then, a hole (not illustrated) which penetrates through the insulator11and the laminated body30ais formed within the memory cell region RMC separately from the second hole40c. The insulation film32ais removed with, for example, a high-temperature phosphoric acid solution through this hole. Subsequently, the electrode film32is formed at a portion where the insulation film32ahas been removed. The electrode film32is substituted for the insulation film32ain this manner. Then, the insulator41is embedded in other holes.

According to the present embodiment as described above, by expanding the width W1of the tap region RT, a region where the contact portion50is to be formed is sufficiently secured. By this mean, it is possible to improve workability of the contact portion50.

Note that, in the present embodiment, a planar shape of the tap region RT is a hexagon. However, the planar shape is not limited to a hexagon, and, for example, may be a rectangle as illustrated inFIG. 7. Also in this case, because it is possible to expand the width W1, the region where the contact portion50is to be formed can be sufficiently secured, so that it is possible to improve workability of the contact portion.

Second Embodiment

FIG. 8is a plan view of a semiconductor memory device according to a second embodiment. The same reference numerals are assigned to components similar to those in the semiconductor memory device1according to the first embodiment, and detailed description will be omitted.

As illustrated inFIG. 8, at the semiconductor memory device2according to the present embodiment, each one of a plurality of contact portions50arranged along the Y direction is provided within each of the tap regions RT. Specifically, by branching and merging of the insulators11in the Y direction being repeated, a plurality of tap regions RT are formed, and the contact portions50are disposed at equal intervals.

Further, in the present embodiment, a plurality of lines each in which a plurality of contact portions50are arranged in the Y direction at equal intervals, are provided. Center pitches P of the contact portions50are the same between the lines adjacent to each other in the X direction. That is, in the present embodiment, a plurality of contact portions50are arranged in a matrix in the X direction and in the Y direction.

The insulator11is embedded within the first slit11apatterned using the mask70(seeFIG. 4AandFIG. 4B) in a similar manner to the first embodiment. At this time, in the first embodiment, a plurality of contact portions50are provided within one tap region RT. Therefore, if an interval of the contact portions50is large, a tap region RT which is long in the Y direction is required.

Because, in the present embodiment, a plurality of contact portions50are respectively provided within the plurality of tap regions RT. Therefore, because the length of the tap region RT in the Y direction can be suppressed, the length of the mask70in the Y direction can be also suppressed. By this means, because it is possible to avoid buckling of the mask70, it is possible to further improve workability of the first slit11a.

Therefore, according to the present embodiment, it is possible to improve workability of the first slit11aas well as workability of the contact portion50. Note that, also in the present embodiment, the planar shape of the tap region RT is not limited to a hexagon, and, for example, may be a rectangle.

Third Embodiment

FIG. 9is a plan view of a semiconductor memory device according to a third embodiment. The same reference numerals are assigned to components similar to those in the semiconductor memory device1according to the first embodiment described above, and detailed description will be omitted.

In the semiconductor memory device3illustrated inFIG. 9, in a similar manner to the second embodiment, each one of the plurality of contact portions50is provided within each of the tap regions RT. Further, a plurality of lines each in which the plurality of contact portions50are arranged in the Y direction at equal intervals, are provided.

However, in the present embodiment, lines adjacent to each other in the X direction are displaced from each other by half of the center pitch P of the contact portion50. That is, in these lines, a merging portion of the insulators11faces a branching portion of the insulators11in the X direction.

Meanwhile, in the second embodiment, as illustrated inFIG. 8, branching portions of the insulators11face each other in the X direction. Therefore, a shortest distance D between the lines of the contact portions50adjacent to each other in the X direction in the semiconductor memory device3according to the present embodiment becomes longer than a shortest distance D in the semiconductor memory device2according to the second embodiment. As a result of the shortest distance D becoming longer, a width of the electrode film32disposed between the lines of the contact portions50, in other words, a width of the mask70becomes wider. Therefore, the mask pattern is further less likely to collapse upon work of the first slit11a.

Therefore, according to the present embodiment, it is possible to further improve workability of the first slit11acompared to the second embodiment. Note that, also in the present embodiment, the planar shape of the tap region RT is not limited to a hexagon, and, for example, may be a rectangle.

Fourth Embodiment

FIG. 10is a planar view of a semiconductor memory device according to a fourth embodiment. The same reference numerals are assigned to components similar to those in the semiconductor memory device1according to the above-described first embodiment, and detailed description will be omitted.

As illustrated inFIG. 10, an insulator80is provided at the semiconductor memory device4according to the present embodiment. The insulator80is an example of the second insulator, and splits the laminated body30in the second direction within the tap region RT. The insulator80contains, for example, silicon oxide.

The tap region RT is formed by the mask70being patterned in similar manner to the first embodiment.

A manufacturing method of the tap region RT of the semiconductor memory device1in the present embodiment will be described below.

In the present embodiment, as illustrated inFIG. 12, a slit70bis formed at a portion where the contact portion50is to be formed in the mask70. At this time, in order to make the widths of the masks70equal in the X direction, it is preferable to form the slit70aand the slit70bat equal intervals. In other words, a repetition pitch of a portion where the mask70exists and the slit70bin the X direction in the tap region RT is preferably equal to that in the memory cell region RMC.

Subsequently, the laminated body30ais etched in the Z direction from the slit70aand the slit70bof the mask70through RIE. As a result, as illustrated inFIG. 13, a first slit11aand a second slit11bare formed at the laminated body30a. In the present embodiment, because the slit70bis formed at the mask70, a difference in the residual film Δh is reduced compared to a case where only the slit70ais formed. Therefore, it is possible to avoid collapse of the pattern of the mask70during etching of the laminated body30a, so that work of the first slit11abecomes stable.

Subsequently, as illustrated inFIG. 14, the insulator11is embedded within the first slit11a, and the insulator80is embedded within the second slit11b. Thereafter, a hole (not illustrated) which penetrates through part of the insulator80and the laminated body30ain the Z direction is formed, and the contact portion50is formed inside this hole.

According to the present embodiment as described above, the difference in the residual film Δh of the mask70is reduced by the slit70bbeing also formed at a portion where the contact portion50is to be formed. By this means, it is possible to avoid collapse of the pattern of the mask70, so that workability of the first slit11ais improved. Further, because the second slit11bformed at the laminated body30aby the slit70bis blocked with the insulator80, a region where the contact portion50is to be formed can be sufficiently secured within the tap region RT. Therefore, workability of the contact portion50does not degrade.

Note that, also in the present embodiment, the planar shape of the tap region RT is not limited to a hexagon, and, for example, may be a rectangle as illustrated inFIG. 15. Also in this case, by the second slit11bformed within the tap region RT being embedded with the insulator80, a region where the contact portion50is to be formed is sufficiently secured, and, by this means, it is possible to improve workability of the contact portion.