Semiconductor device

An eighth semiconductor portion is provided between the first semiconductor portion and the third semiconductor portion. The eighth semiconductor portion is of the second conductivity type, contacting the first semiconductor portion, and having a lower second-conductivity-type impurity concentration than the second semiconductor portion.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-046038, filed on Mar. 17, 2020; the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

Generally, an ESD (Electro Static Discharge) protection diode that has a small product capacitance of, for example, less than 1 pF includes a crowbar circuit in which two switching diodes and one zener diode are combined. The breakdown voltage of a product having such a structure is set by adjusting the breakdown voltage of the zener diode. Generally, the ESD immunity undesirably decreases as the breakdown voltage of a diode increases because the power after the breakdown increases. On the other hand, it is desirable to reduce the clamping voltage of the ESD protection diode as the IC (Integrated Circuit) to be protected is downscaled. Although a snapback operation is effective to reduce the clamping voltage, a large voltage is applied to the zener diode directly after the snapback start because the snapback-start voltage is greater than the breakdown voltage. In other words, when combining a snapback operation with a higher breakdown voltage of the product, a larger voltage is applied to the zener diode at snapback start, and there is a risk of breakdown occurring even for a small current after snapback because the power per unit area is large.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a first semiconductor portion of a first conductivity type; a second semiconductor portion provided on the first semiconductor portion, the second semiconductor portion being of a second conductivity type and contacting the first semiconductor portion; a third semiconductor portion provided on the first semiconductor portion, the third semiconductor portion being of the second conductivity type and having a lower second-conductivity-type impurity concentration than the second semiconductor portion; a fourth semiconductor portion provided on the third semiconductor portion, the fourth semiconductor portion being of the first conductivity type and contacting the third semiconductor portion; a fifth semiconductor portion provided on the first semiconductor portion, the fifth semiconductor portion being of the first conductivity type; a sixth semiconductor portion provided on the fifth semiconductor portion, the sixth semiconductor portion being of the second conductivity type and contacting the fifth semiconductor portion; a seventh semiconductor portion provided on the sixth semiconductor portion, the seventh semiconductor portion being of the second conductivity type and having a higher second-conductivity-type impurity concentration than the sixth semiconductor portion; an eighth semiconductor portion provided between the first semiconductor portion and the third semiconductor portion, the eighth semiconductor portion being of the second conductivity type, contacting the first semiconductor portion, and having a lower second-conductivity-type impurity concentration than the second semiconductor portion; a first electrode contacting the first semiconductor portion; and a second electrode contacting the fourth semiconductor portion and the seventh semiconductor portion.

Embodiments will now be described with reference to the drawings. The same components in the drawings are marked with the same reference numerals.

Although a first conductivity type is taken to be an N-type and a second conductivity type is taken to be a P-type in the description of the following embodiments, the first conductivity type may be the P-type, and the second conductivity type may be the N-type. Although a semiconductor material is taken to be silicon in the following embodiments, the semiconductor material is not limited to silicon and may be, for example, silicon carbide, gallium nitride, etc.

FIG.1Ais a schematic cross-sectional view of a semiconductor device1of an embodiment.FIG.1Bis a schematic plan view of a second semiconductor portion12, a fourth semiconductor portion14, and an eighth semiconductor portion18ofFIG.1A.

The semiconductor device1includes a semiconductor layer10, a first electrode21, a second electrode22, an insulating film41, and a protective film42.

The semiconductor layer10includes a semiconductor layer30, a first semiconductor portion11, the second semiconductor portion12, a third semiconductor portion13, the fourth semiconductor portion14, a fifth semiconductor portion15, a sixth semiconductor portion16, a seventh semiconductor portion17, the eighth semiconductor portion18, a ninth semiconductor portion19, and a tenth semiconductor portion20.

The P-type semiconductor layer30is provided on the N-type first semiconductor portion11. For example, the first semiconductor portion11is a semiconductor substrate, and the semiconductor layer30is epitaxially grown on the first semiconductor portion11. The semiconductor layer30includes the third semiconductor portion13, the eighth semiconductor portion18, and the sixth semiconductor portion16.

The P-type second semiconductor portion12is provided on the first semiconductor portion11. The bottom portion of the second semiconductor portion12contacts the first semiconductor portion11; and the second semiconductor portion12and the first semiconductor portion11form a P-N junction.

The P-type third semiconductor portion13, which is a portion of the semiconductor layer30, is provided on the first semiconductor portion11. The P-type impurity concentration of the third semiconductor portion13is less than the P-type impurity concentration of the second semiconductor portion12.

The N-type fourth semiconductor portion14is provided on the third semiconductor portion13and contacts the third semiconductor portion13. The third semiconductor portion13and the fourth semiconductor portion14form a P-N junction.

The N-type fifth semiconductor portion15is provided on the first semiconductor portion11. The N-type impurity concentration of the fifth semiconductor portion15is less than the N-type impurity concentration of the first semiconductor portion11. The fifth semiconductor portion15is positioned at substantially the same depth as the second semiconductor portion12.

The P-type sixth semiconductor portion16, which is a portion of the semiconductor layer30, is provided on the fifth semiconductor portion15. The sixth semiconductor portion16contacts the fifth semiconductor portion15; and the sixth semiconductor portion16and the fifth semiconductor portion15form a P-N junction.

The P-type seventh semiconductor portion17is provided on the sixth semiconductor portion16. The P-type impurity concentration of the seventh semiconductor portion17is greater than the P-type impurity concentration of the sixth semiconductor portion16.

The P-type eighth semiconductor portion18, which is a portion of the semiconductor layer30, is provided between the first semiconductor portion11and the third semiconductor portion13. The P-type impurity concentration of the eighth semiconductor portion18is less than the P-type impurity concentration of the second semiconductor portion12. The eighth semiconductor portion18contacts the first semiconductor portion11; and the eighth semiconductor portion18and the first semiconductor portion11form a P-N junction.

The third semiconductor portion13and the eighth semiconductor portion18are provided under the fourth semiconductor portion14. The third semiconductor portion13is provided between the fourth semiconductor portion14and the eighth semiconductor portion18, and the eighth semiconductor portion18is provided between the third semiconductor portion13and the first semiconductor portion11. The eighth semiconductor portion18is at a position overlapping the fourth semiconductor portion14in the thickness direction of the semiconductor layer30.

The P-type ninth semiconductor portion19is provided on the second semiconductor portion12. The ninth semiconductor portion19surrounds the periphery of the third semiconductor portion13and the periphery of the fourth semiconductor portion14and separates the third and fourth semiconductor portions13and14from the other regions of the semiconductor layer30. The P-type impurity concentration of the ninth semiconductor portion19is greater than the P-type impurity concentration of the third semiconductor portion13and the P-type impurity concentration of the eighth semiconductor portion18.

The N-type tenth semiconductor portion20is provided on the fifth semiconductor portion15. The tenth semiconductor portion20surrounds the periphery of the sixth semiconductor portion16and the periphery of the seventh semiconductor portion17and separates the sixth and seventh semiconductor portions16and17from the other regions of the semiconductor layer30.

The first electrode21is provided at the lower surface of the first semiconductor portion11. The first electrode21contacts the lower surface of the first semiconductor portion11and is electrically connected to the first semiconductor portion11.

The insulating film41is provided at the upper surface of the semiconductor layer30. The second electrode22is provided on the insulating film41. The second electrode22contacts the fourth semiconductor portion14and the seventh semiconductor portion17via openings formed in the insulating film41. The second electrode22is electrically connected to the fourth semiconductor portion14and the seventh semiconductor portion17.

A portion of the second electrode22is covered with the protective film42, and another portion of the second electrode is exposed from under the protective film42. The protective film42is an insulating film. The portion of the second electrode22exposed from under the protective film42is electrically connected to an external circuit via a conductive connection member (e.g., a wire).

As shown inFIG.1B, the periphery of the eighth semiconductor portion18is surrounded with the second semiconductor portion12. For example, the second semiconductor portion12is formed by ion implantation after forming the semiconductor layer30on the first semiconductor portion11. By not implanting the P-type impurity into the region used to form the eighth semiconductor portion18at this time, a portion that has a lower P-type impurity concentration than the second semiconductor portion12remains at a portion of the junction portion between the semiconductor layer30and the first semiconductor portion11and is used to form the eighth semiconductor portion18.

The semiconductor device1includes a first diode D1, a second diode D2, and a third diode D3. The first diode D1includes a P-N junction between the P-type sixth semiconductor portion16and the N-type fifth semiconductor portion15. The second diode D2includes a P-N junction between the P-type third semiconductor portion13and the N-type fourth semiconductor portion14. The third diode D3includes a P-N junction between the P-type second semiconductor portion12and the N-type first semiconductor portion11.

The eighth semiconductor portion18is positioned directly under the second diode D2. The contact area (the surface area of the P-N junction) between the eighth semiconductor portion18and the first semiconductor portion11is less than the contact area (the surface area of the P-N junction of the third diode D3) between the second semiconductor portion12and the first semiconductor portion11.

FIG.2Ais an equivalent circuit diagram of the semiconductor device of the embodiment.

The first diode D1and the second diode D2are switching diodes, and the third diode D3is a zener diode. The second diode D2and the third diode D3are connected in series between the first electrode21and the second electrode22. The first diode D1and a set of diodes including the second and third diodes D2and D3are connected in parallel between the first electrode21and the second electrode22. The anode of the first diode D1is connected to the second electrode22, and the cathode of the first diode D1is connected to the first electrode21. The cathode of the second diode D2is connected to the second electrode22. The cathode of the third diode D3is connected to the first electrode21. The anode of the second diode D2and the anode of the third diode D3are connected to each other.

The size of the third diode D3is greater than the size of the first diode D1and the size of the second diode D2. For example, the P-N junction area of the third diode D3(the junction area between the second semiconductor portion12and the first semiconductor portion11) is greater than the P-N junction area of the first diode D1(the junction area between the sixth semiconductor portion16and the fifth semiconductor portion15) and the P-N junction area of the second diode D2(the junction area between the third semiconductor portion13and the fourth semiconductor portion14). The capacitance of the third diode D3is greater than the capacitance of the first diode D1and the capacitance of the second diode D2. The ESD immunity of the third diode D3is greater than the ESD immunity of the first diode D1and the ESD immunity of the second diode D2.

The capacitance of the third diode D3can be ignored because the capacitance of the third diode D3is sufficiently greater than the capacitance of the second diode D2. Accordingly, the terminal-terminal capacitance of the crowbar circuit shown inFIG.2Ais represented by the sum of the capacitance of the first diode D1and the capacitance of the second diode D2, which are small capacitances. Thereby, in the crowbar circuit, a lower capacitance can be realized while maintaining ESD immunity from the two directions of the forward and reverse directions.

The potential of the first electrode21is taken to be a ground potential. For example, when a negative transient voltage is applied to the second electrode22, the second diode D2is biased in the forward direction, the third diode D3is biased in the reverse direction, and the first diode D1is biased in the reverse direction. By setting the breakdown voltage of the third diode D3to be less than the breakdown voltage of the first diode D1, a reverse current does not flow in the first diode D1, but a reverse current flows in the third diode D3. Thereby, the transient current (a surge current) flows toward the second electrode22from the first electrode21via the third diode D3and the second diode D2as illustrated by arrow A inFIG.2A.

On the other hand, when a positive transient voltage is applied to the second electrode22, the second diode D2is biased in the reverse direction, the third diode D3is biased in the forward direction, and the first diode D1is biased in the forward direction. By setting the forward voltage of the first diode D1to be less than the breakdown voltage of the second diode D2, the transient current flows to the first electrode21from the second electrode22via the first diode D1as illustrated by arrow B inFIG.2A.

Generally, the forward-direction ESD immunity of a diode is greater than its reverse-direction ESD immunity. In the crowbar circuit, for the first diode D1and the second diode D2which have low ESD immunity, the ESD flows only in the forward direction; for the third diode D3which has high ESD immunity, the ESD flows in the reverse direction. Thereby, the ESD immunity is maintained for both forward-direction ESD and reverse-direction ESD.

A parasitic N-P-N transistor is embedded in the semiconductor device1, in which the N-type fourth semiconductor portion14functions as an emitter, the P-type third semiconductor portion13and the P-type second semiconductor portion12function as a base, and the N-type first semiconductor portion11functions as a collector.

In the parasitic N-P-N transistor, when a voltage is applied between the emitter and the base and electrons are injected from the emitter into the base, there are cases where a base current flows and the N-P-N transistor is switched on before the breakdown of the third diode D3. In other words, as in the current-voltage characteristic of the third diode D3shown inFIG.2B, snapback occurs in which the voltage decreases once and the current increases before the breakdown of the third diode D3. At the horizontal axis inFIG.2B, VBR is the breakdown voltage, and VSBis the snapback-start voltage.

To downscale ICs in recent years, it is necessary for the clamping voltage to be low when ESD is applied. In the semiconductor device1, the parasitic N-P-N transistor operates at the snapback start, the carriers inside the semiconductor layer are increased, and the clamping voltage, i.e., the voltage that is applied to the ICs of subsequent stages, can be reduced.

FIG.5is a schematic cross-sectional view of a semiconductor device100of a comparative example. The semiconductor device100of the comparative example differs from the semiconductor device1of the embodiment in that the P-N junction of the third diode D3(the junction between the second semiconductor portion12and the first semiconductor portion11) is positioned directly under the second diode D2, and there is no eighth semiconductor portion18directly under the second diode D2.

In the semiconductor device100of the comparative example, the snapback operation starts earliest at a portion A directly under the second diode D2at which the N-P-N distance of the parasitic N-P-N transistor is shortest. In other words, there is a risk that the current directly after the snapback start may concentrate at a point at the portion A, cause damage, and cause leakage breakdown with the damage as a starting point.

According to the semiconductor device1of the embodiment shown inFIGS.1A and1B, the third diode D3is not formed directly under the second diode D2where the N-P-N distance of the parasitic N-P-N transistor is shortest, and the eighth semiconductor portion18that has a lower P-type impurity concentration than the second semiconductor portion12of the third diode D3is provided.

Thereby, the current directly after the snapback start can be prevented from concentrating at a point. ESD breakdown can be prevented because the current at the snapback start does not concentrate at a point and is dispersed in a line configuration along the portion A surrounding the eighth semiconductor portion18at the junction portion between the second semiconductor portion12and the first semiconductor portion11, and the power per unit area does not become large.

Although the surface area of the third diode D3(the junction area between the second semiconductor portion12and the first semiconductor portion11) is reduced by the area where the eighth semiconductor portion18is formed, the ESD immunity of the semiconductor device1is substantially not affected because the ratio of the junction area between the eighth semiconductor portion18and the first semiconductor portion11to the surface area of the third diode D3is small.

The P-type impurity concentration of the second semiconductor portion12is, for example, not less than 1×1017and not more than 1×1019(atoms/cm3). Compared to the P-type impurity concentration of the second semiconductor portion12, it is desirable for the P-type impurity concentration of the eighth semiconductor portion18to be not less than 5×1013and not more than 1×1015(atoms/cm3).

FIG.3is a schematic cross-sectional view of a semiconductor device2of another embodiment.

The semiconductor device2includes an eighth semiconductor portion28instead of the eighth semiconductor portion18of the semiconductor device1. The P-type eighth semiconductor portion28is provided between the first semiconductor portion11and the third semiconductor portion13. The P-type impurity concentration of the eighth semiconductor portion28is less than the P-type impurity concentration of the second semiconductor portion12. Also, the P-type impurity concentration of the eighth semiconductor portion28is greater than the P-type impurity concentration of the third semiconductor portion13. The eighth semiconductor portion28contacts the first semiconductor portion11; and the eighth semiconductor portion28and the first semiconductor portion11form a P-N junction. The eighth semiconductor portion28is at a position overlapping the fourth semiconductor portion14in the thickness direction of the semiconductor layer30.

In the semiconductor device2as well, the third diode D3is not formed directly under the second diode D2where the N-P-N distance of the parasitic N-P-N transistor is shortest, and the eighth semiconductor portion28that has a lower P-type impurity concentration than the second semiconductor portion12of the third diode D3is provided.

Thereby, the ESD breakdown can be prevented because the current at the snapback start does not concentrate at a point and is dispersed in a line configuration along the portion A surrounding the eighth semiconductor portion28at the junction portion between the second semiconductor portion12and the first semiconductor portion11, and the power per unit area does not become large.

FIG.4is a schematic cross-sectional view of a semiconductor device3of another embodiment.

The first semiconductor portion11includes a first portion11acontacting the second semiconductor portion12under the fourth semiconductor portion14, and a second portion11bcontacting the second semiconductor portion12at a region adjacent to the first portion11a. The N-type impurity concentration of the first portion11ais less than the N-type impurity concentration of the second portion11b.

According to the semiconductor device3, the impurity concentration of the P-N junction portion of the third diode D3, which is directly under the second diode D2where the N-P-N distance of the parasitic N-P-N transistor is shortest, is reduced.

Thereby, the ESD breakdown can be prevented because the current at the snapback start does not concentrate at a point and is dispersed in a line configuration along the portion A surrounding the first portion11aat the junction portion between the second semiconductor portion12and the first semiconductor portion11, and the power per unit area does not become large.