Display substrate with power pad in peripheral area and method of manufacturing thereof

A display substrate having a display area and a peripheral area. The display panel includes a base substrate; a first power pad on the base substrate, the first power pad including a first portion in the peripheral area and along a power line interface side of the display substrate; a planarization layer on a side of the first power pad away from the base substrate; a pixel definition layer on a side of the planarization layer away from the base substrate, defining a plurality of subpixel apertures; and an encapsulating layer on a side of the pixel definition layer away from the base substrate. The display substrate includes a first groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the first portion of the first power pad in the peripheral area.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a national stage application under 35 U.S.C. § 371 of International Application No. PCT/CN2019/077691, filed Mar. 11, 2019, the contents of which are incorporated by reference in the entirety.

TECHNICAL FIELD

The present invention relates to display technology, more particularly, to a display substrate, a display apparatus, and a method of fabricating a display substrate.

BACKGROUND

Organic light emitting diode (OLED) display apparatuses are self-emissive devices, and do not require backlights. OLED display apparatuses also provide more vivid colors and a larger color gamut as compared to the conventional liquid crystal display (LCD) apparatuses. Further, OLED display apparatuses can be made more flexible, thinner, and lighter than a typical LCD apparatuses.

SUMMARY

In one aspect, the present invention provides a display substrate having a display area and a peripheral area, comprising a base substrate; a first power pad on the base substrate, the first power pad comprising a first portion in the peripheral area and along a power line interface side of the display substrate; a planarization layer on a side of the first power pad away from the base substrate; a pixel definition layer on a side of the planarization layer away from the base substrate, defining a plurality of subpixel apertures; and an encapsulating layer on a side of the pixel definition layer away from the base substrate; wherein the display substrate comprises a first groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the first portion of the first power pad in the peripheral area; and the encapsulating layer extends into the first groove and is in direct contact with the surface of the first portion, thereby encapsulating the display substrate.

Optionally, the encapsulating layer completely covers the surface of the first portion.

Optionally, the first portion comprises a first side away from the base substrate, a second side opposite to the first side and closer to the base substrate, a third side connecting the first side and the second side and closer to the display area, and a fourth side connecting the first side and the second side, the fourth side being opposite to the third side and away from the display area the fourth side of the first portion is covered by one or a combination of the pixel definition layer and the planarization layer; and the first groove exposes a portion of the first side.

Optionally, the fourth side has a concave surface.

Optionally, the first portion comprises at least one sublayer that is over-etched on the fourth side, thereby forming the concave surface.

Optionally, the encapsulating layer comprises a first inorganic encapsulating sub-layer, the first inorganic encapsulating sub-layer extending into the first groove and being in direct contact with the surface of the first portion.

Optionally, in a region corresponding to the first groove, the encapsulating layer further comprises an organic encapsulating sub-layer on a side of the first inorganic encapsulating sub-layer away from the base substrate, and a second inorganic encapsulating sub-layer on a side of the organic encapsulating sub-layer away from the first inorganic encapsulating sub-layer.

Optionally, the first power pad further comprises at least one second portion connected to the first portion and extending from the first portion away from the display area; and the at least one second portion is at least partially covered by one or a combination of the pixel definition layer and the planarization layer.

Optionally, the display substrate further comprises a second groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the at least one second portion of the first power pad in the peripheral area; and the encapsulating layer extends into the second groove and is in direct contact with the surface of the at least one second portion.

Optionally, the encapsulating layer comprises a first inorganic encapsulating sub-layer, the first inorganic encapsulating sub-layer extending into the second groove and being in direct contact with the surface of the at least one second portion.

Optionally, in a region corresponding to the second groove, the encapsulating layer further comprises an organic encapsulating sub-layer on a side of the first inorganic encapsulating sub-layer away from the base substrate, and a second inorganic encapsulating sub-layer on a side of the organic encapsulating sub-layer away from the first inorganic encapsulating sub-layer.

Optionally, the at least one second portion comprises two second portions connected to the first portion respectively at different locations and extending from the first portion away from the display area; and the first portion and the two second portions form a pi-shaped structure.

Optionally, the display substrate further comprises a second power pad on the base substrate and in the peripheral area, the second power pad spaced apart from the first power pad; wherein the second power pad comprises at least one third portion on the power line interface side of the display substrate, the at least one third portion at least partially covered by one or a combination of the pixel definition layer and the planarization layer; the second groove extends through one or a combination of the planarization layer and the pixel definition layer, further exposing a surface of the at least one third portion of the second power pad in the peripheral area; and the encapsulating layer extends into the second groove and is in direct contact with the surface of the at least one third portion.

Optionally, the display substrate further comprises a second power pad on the base substrate and in the peripheral area, the second power pad spaced apart from the first power pad; wherein the second power pad comprises at least one third portion on the power line interface side of the display substrate, the at least one third portion at least partially covered by one or a combination of the pixel definition layer and the planarization layer; the at least one third portion is on a side of the first portion extending away from the display area, the first portion and a respective one of the at least one third portion being spaced apart by a first gap; and the first groove is on a side of the first gap closer to the display area.

Optionally, the planarization layer at least extends into the first gap.

Optionally, the first power pad further comprises at least one second portion connected to the first portion and extending from the first portion away from the display area; the at least one second portion is at least partially covered by one or a combination of the pixel definition layer and the planarization layer; and the at least one second portion and the at least one third portion are on a side of the first portion extending away from the display area, a respective one of the at least one second portion being spaced apart from a respective one of the at least one third portion by a second gap connected to the first gap.

Optionally, the planarization layer extends into the first gap and the second gap.

Optionally, the display substrate further comprises a third groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the at least one second portion of the first power pad in the peripheral area; the encapsulating layer comprises a first inorganic encapsulating sub-layer, the first inorganic encapsulating sub-layer extending into the third groove and being in direct contact with the surface of the at least one second portion; in a region corresponding to the third groove, the encapsulating layer further comprises a second inorganic encapsulating sub-layer on a side of the first inorganic encapsulating sub-layer away from the base substrate, the second inorganic encapsulating sub-layer being in direct contact with the first inorganic encapsulating sub-layer.

Optionally, the first power pad is selected from a group consisting of a VDD power pad connected to a plurality of VDD high voltage power lines and a VSS power pad connected to a plurality of VSS low voltage power lines.

In another aspect, the present invention provides a display apparatus, comprising the display substrate described herein or fabricated by a method described herein, and one or more integrated circuits connected to the display substrate.

In another aspect, the present invention provides a method of fabricating a display substrate, comprising forming a first power pad on a base substrate, the first power pad formed to comprise a first portion in the peripheral area and along a power line interface side of the display substrate; forming a planarization layer on a side of the first power pad away from the base substrate; forming a pixel definition layer on a side of the planarization layer away from the base substrate, defining a plurality of subpixel apertures; forming a first groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the first portion of the first power pad in the peripheral area; and forming an encapsulating layer on a side of the pixel definition layer away from the base substrate, the encapsulating layer formed to extend into the first groove and be in direct contact with the surface of the first portion, thereby encapsulating the display substrate.

DETAILED DESCRIPTION

FIG. 1is a plan view of a display substrate in some embodiments according to the present disclosure.FIG. 2is schematic diagram illustrating the structure of a first power pad in some embodiments according to the present disclosure.FIG. 3is a zoom-in view of an area Z inFIG. 1.FIG. 4is a cross-sectional view along an A-A′ line ofFIG. 3.FIG. 5is a cross-sectional view along a B-B′ line ofFIG. 3. Referring toFIGS. 1 to 5, the display substrate in some embodiments have a display area DA and a peripheral area PA. The display substrate includes a base substrate10; a first power pad PP1on the base substrate10; a planarization layer20on a side of the first power pad PP1away from the base substrate10; a pixel definition layer30on aside of the planarization layer20away from the base substrate10, defining a plurality of subpixel apertures SPA; and an encapsulating layer40on a side of the pixel definition layer30away from the base substrate10. Optionally, the display substrate further includes a second power pad PP2on the base substrate10and in the peripheral area PA, the second power pad PP2spaced apart from the first power pad PP1.

In some embodiments, the first power pad PP1includes a first portion P1in the peripheral area PA and along a power line interface side of the display substrate, and at least one second portion P2connected to the first portion P1and extending from the first portion P1away from the display area DA. In some embodiments, the second power pad PP2includes at least one third portion P3on the power line interface side of the display substrate, and at least one fourth portion P4connected to the third portion P3and on another side of the display substrate different from the power line interface side. Optionally, one or a combination of the first portion P1, the at least one second portion P2, the at least one third portion P3, and the at least one fourth portion P4is at least partially covered by one or a combination of the pixel definition layer30and the planarization layer20. In one example, as shown inFIGS. 1 to 5, one or a combination of the first portion P1, the at least one second portion P2, the at least one third portion P3, and the at least one fourth portion P4is at least partially covered by both the planarization layer20and the pixel definition layer30. In another example, at least one of the first portion P1, the at least one second portion P2, the at least one third portion P3, and the at least one fourth portion P4is only at least partially covered by the planarization layer20but not the pixel definition layer30.

Optionally, the power line interface side of the display substrate is an integrated circuit bonding side of the display substrate at which one or more integrated circuits are connected to the display substrate. Optionally, the power line interface side of the display substrate is a side of the display substrate at which one or more power line are connected to the display substrate.

Referring toFIG. 2, in some embodiments, the at least one second portion P2includes two second portions (one on left and another on right inFIG. 2) connected to the first portion P1respectively at different locations and extending from the first portion P1away from the display area DA. Optionally, the first portion P1and the two second portions of the at least one second portion P2form a pi-shaped structure.

In some embodiments, and referring toFIG. 4andFIG. 5, the display substrate further includes a plurality of light emitting elements LE respectively in the plurality of subpixel apertures SPA. A respective one of a plurality of light emitting elements LE includes a first electrode53, a light emitting layer52on a side of the first electrode53away from the base substrate10, and a second electrode51on a side of the light emitting layer52away from the first electrode53.

In some embodiments, and referring toFIG. 4andFIG. 5, the display substrate further includes a plurality of thin film transistors TFT for driving light emission of the plurality of light emitting elements LE.

In some embodiments, the first power pad PP1is connected to and configured to provide a first power signal to a plurality of first power signal lines, and the second power pad PP2is connected to and configured to provide a second power signal to a plurality of second power signal lines. Optionally, the first power pad PP1is a VDD power pad connected to a plurality of VDD high voltage power lines, and the second power pad PP2is a VSS power pad connected to a plurality of VSS low voltage power lines. Optionally, the first power pad PP1is a VSS power pad connected to a plurality of VSS low voltage power lines, and the second power pad PP2is a VDD power pad connected to a plurality of VDD high voltage power lines. Optionally, the first power pad and the second power pad may be other pads connected to different signal lines.

In some embodiments, and referring toFIG. 4andFIG. 5, the encapsulating layer40includes a first inorganic encapsulating sub-layer41on a side of the plurality light emitting elements LE and the pixel definition layer30away from the base substrate10, an organic encapsulating sub-layer42on a side of the first inorganic encapsulating sub-layer41away from the base substrate10, and a second inorganic encapsulating sub-layer43on a side of the organic encapsulating sub-layer42away from the first inorganic encapsulating sub-layer41.

In some embodiments, and referring toFIG. 4andFIG. 5, the display substrate has a second groove GE2extending through one or a combination of the planarization layer20and the pixel definition layer30, exposing a surface of the at least one second portion P2of the first power pad PP1in the peripheral area PA and a surface of the at least one third portion P3of the second power pad PP2in the peripheral area PA. The encapsulating layer40extends into the second groove GE2and is in direct contact with the surface of the at least one second portion P2and the surface of the at least one third portion P3. For example, the first inorganic encapsulating sub-layer41extends into the second groove GE2and is in direct contact with the surface of the at least one second portion P2and the surface of the at least one third portion P3.

In some embodiments, and referring toFIG. 4andFIG. 5, the display substrate further includes a third groove GE3extending through one or a combination of the planarization layer20and the pixel definition layer30, exposing a surface of the at least one second portion P2of the first power pad PP1in the peripheral area PA and a surface of the at least one third portion P3of the second power pad PP2in the peripheral area PA. The encapsulating layer40extends into the third groove GE3and is in direct contact with the surface of the at least one second portion P2and the surface of the at least one third portion P3. For example, the first inorganic encapsulating sub-layer41extends into the third groove GE3and is in direct contact with the surface of the at least one second portion P2and the surface of the at least one third portion P3.

Referring toFIG. 3, the at least one third portion P3is on a side of the first portion P1extending away from the display area. The first portion P1and a respective one of the at least one third portion P3are spaced apart by a first gap G1. The at least one second portion P2and the at least one third portion P3are on a side of the first portion P1extending away from the display area. A respective one of the at least one second portion P2is spaced apart from a respective one of the at least one third portion P3by a second gap G2connected to the first gap G1. The first gap G1and the second gap G2form a channel allowing external oxygen and moisture permeate into the inside of the display substrate, because the planarization layer20and the pixel definition layer30are not capable of completely blocking oxygen and moisture. Referring to the dotted arrow line inFIGS. 3 to 5, the external oxygen and moisture can permeate through the planarization layer20and the pixel definition layer30, and reach the second electrode51of the plurality of light emitting elements LE, thereby corroding the second electrode51, resulting in deterioration of the plurality of light emitting elements LE.

Accordingly, the present disclosure provides, inter alia, a display substrate, a display apparatus, and a method of fabricating a display substrate that substantially obviate one or more of the problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides a display substrate having a display area and a peripheral area. In some embodiments, the display substrate includes a base substrate; a first power pad on the base substrate, the first power pad including a first portion in the peripheral area and along a power line interface side of the display substrate; a planarization layer on a side of the first power pad away from the base substrate; a pixel definition layer on a side of the planarization layer away from the base substrate, defining a plurality of subpixel apertures; and an encapsulating layer on a side of the pixel definition layer away from the base substrate. Optionally, the display substrate includes a first groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the first portion of the first power pad in the peripheral area. Optionally, the encapsulating layer extends into the first groove and is in direct contact with the surface of the first portion, thereby encapsulating the display substrate. Optionally, the encapsulating layer completely covers the surface of the first portion.

FIG. 6is a plan view of a display substrate in some embodiments according to the present disclosure.FIG. 7is schematic diagram illustrating the structure of a first power pad in some embodiments according to the present disclosure.FIG. 8is a zoom-in view of an area Z inFIG. 6.FIG. 9is a cross-sectional view along a C-C′ line ofFIG. 8.FIG. 10is a cross-sectional view along a D-D′ line ofFIG. 8. Referring toFIGS. 6 to 10, the display substrate in some embodiments have a display area DA and a peripheral area PA. The display substrate includes a base substrate10; a first power pad PP1on the base substrate10; a planarization layer20on a side of the first power pad PP1away from the base substrate10; a pixel definition layer30on a side of the planarization layer20away from the base substrate10, defining a plurality of subpixel apertures SPA; and an encapsulating layer40on a side of the pixel definition layer30away from the base substrate10. In some embodiments, the first power pad PP1includes a first portion P1in the peripheral area PA and along a power line interface side of the display substrate. Optionally, the display substrate has a first groove GE1extending through one or a combination of the planarization layer20and the pixel definition layer30, exposing a surface of the first portion P1of the first power pad PP1in the peripheral area PA. In one example, and referring toFIG. 9andFIG. 10, the first groove GE1extends through both of the planarization layer20and the pixel definition layer30, exposing the surface of the first portion P1of the first power pad PP1in the peripheral area PA. The encapsulating layer40extends into the first groove GE1and is in direct contact with the surface of the first portion P1, thereby encapsulating the display substrate. The encapsulating layer40completely covers the surface of the first portion P1.

In some embodiments, the display substrate further includes a second power pad PP2on the base substrate10and in the peripheral area PA, the second power pad PP2spaced apart from the first power pad PP1. In some embodiments, the first power pad PP1is connected to and configured to provide a first power signal to a plurality of first power signal lines, and the second power pad PP2is connected to and configured to provide a second power signal to a plurality of second power signal lines. Optionally, the first power pad is a VDD power pad connected to a plurality of VDD high voltage power lines, and the second power pad is a VSS power pad connected to a plurality of VSS low voltage power lines. Optionally, the first power pad is a VSS power pad connected to a plurality of VSS low voltage power lines, and the second power pad is a VDD power pad connected to a plurality of VDD high voltage power lines. Optionally, the first power pad and the second power pad may be other pads connected to different signal lines.

Optionally, referring toFIG. 6, the first power pad PP1(e.g., the VDD power pad) is disposed along one side of the display substrate, and the second power pad PP2(e.g., the VSS power pad) substantially surround at least three sides of the display substrate, and extends out of the display substrate from a circuit bonding side (e.g., the power line interface side) of the display substrate.

In some embodiments, and referring toFIG. 9andFIG. 10, the display substrate further includes a plurality of light emitting elements LE respectively in the plurality of subpixel apertures SPA. A respective one of a plurality of light emitting elements LE includes a first electrode53, a light emitting layer52on a side of the first electrode53away from the base substrate10, and a second electrode51on a side of the light emitting layer52away from the first electrode53.

In some embodiments, and referring toFIG. 9andFIG. 10, the display substrate further includes a plurality of thin film transistors TFT for driving light emission of the plurality of light emitting elements LE. In one example, the first electrode53is electrically connected to a drain electrode of a respective one of the plurality of thin film transistors TFT. The plurality of thin film transistors TFT and various signal lines (such as the plurality of VDD high voltage power lines and the plurality of VSS low voltage power lines) constitute a driving circuit for driving light emission of the display substrate.

FIG. 11is a partial view of a display substrate showing the structure of a first portion of a first power pad in some embodiments according to the present disclosure. Referring toFIG. 11, the first portion P1has a first side S1away from the base substrate10, a second side S2opposite to the first side S1and closer to the base substrate10, a third side S3connecting the first side S1and the second side S2and closer to the display area DA, and a fourth side S4connecting the first side S1and the second side S2, the fourth side S4being opposite to the third side S3and away from the display area DA. Optionally, the fourth side S4of the first portion P1is covered by one or a combination of the pixel definition layer30and the planarization layer20. In one example, the fourth side S4of the first portion P1is covered by the planarization layer20, as shown inFIG. 11andFIG. 9. Optionally, the first groove GE1exposes a portion of the first side S1, as shown inFIG. 9andFIG. 10. Optionally, the display substrate further includes an inter-layer dielectric layer60between the first portion P1and the base substrate10.

FIG. 12is a partial view of a display substrate showing the structure of a first portion of a first power pad in some embodiments according to the present disclosure. Referring toFIG. 12, in some embodiments, the third side S3has a concave surface, and the fourth side S4has a concave surface.

In some embodiments, the first portion P1includes at least one sublayer that is over-etched on the fourth side S4, thereby forming the concave surface.FIG. 13is a partial view of a display substrate showing the structure of a first portion of a first power pad in some embodiments according to the present disclosure. Referring toFIG. 13, in some embodiments, the first portion P1includes a first sub-layer P11, a second sub-layer P12in the middle, and a third sub-layer P13, the second sub-layer P12is sandwiched by the first sub-layer P11and the third sub-layer P13. At least the second sub-layer P12is over-etched, thereby forming the concave surface.

Optionally, the first sub-layer P11and the third sub-layer P13are made of a relatively more etchant resistant material, and the second sub-layer P12is made of a relatively less etchant resistant material. In one example, the first sub-layer P11and the third sub-layer P13are made of titanium, and the second sub-layer P12is made of aluminum.

The second portion P2and the second power pad PP2may have a similar concave surface. Optionally, the first power pad PP1and the second power pad PP2are made of a same material, and fabricated in a same patterning process and using a single mask plate. Optionally, each of the first power pad PP1and the second power pad PP2includes a plurality of sub-layers (e.g., a first sub-layer P11, a second sub-layer P12, and a third sub-layer P13).

In the fabricating process of the display substrate, the first power pad PP1and the second power pad PP2(e.g., the first portion P1) are first formed and patterned on the base substrate10. A planarization layer20is formed on the first power pad PP1and the second power pad PP2(e.g., the first portion P1), and subsequently the first electrode53is formed by depositing a conductive material layer followed by etching the conductive material layer to form the pattern of the first electrode53. In the process of etching the conductive material layer, a side surface of the first portion P1(or any other portion of the first power pad PP1or the second power pad PP2) that is not covered by the planarization layer20can be etched by the etchant for etching the conductive material layer. In one example, one of the sub-layers of the first portion P1is made of a relatively less etchant resistant material, and is over-etched during the etching process, thereby forming a concave side surface. Subsequently, the pixel definition layer30is formed on the base substrate10, the pixel definition material of the pixel definition layer30fills in the concave surface. When the encapsulating layer40is formed to encapsulate the display substrate, it cannot completely encapsulate the concave surface. As discussed previously, the pixel definition layer30and the planarization layer20are not capable of completely blocking oxygen and moisture. External oxygen and moisture can permeate through the planarization layer20and the pixel definition layer30.

However, referring toFIG. 9andFIG. 10, due to the formation of the first groove GE1, the encapsulating layer40extends into the first groove GE1and is in direct contact with the first side S1of the first portion P1(see, e.g.,FIGS. 11 to 13). As shown inFIG. 9andFIG. 10, the presence of the encapsulating layer40in this region blocks the pathway of external oxygen and moisture to reach the second electrode51. As a result, the second electrode51is protected from corrosion caused by the external oxygen and moisture permeating through the first gap G1and the second gap G2(see, e.g.,FIG. 8). The performance and lifetime of the plurality of light emitting elements LE are significantly enhanced.

In some embodiments, and referring toFIG. 9andFIG. 10, the encapsulating layer40includes a first inorganic encapsulating sub-layer41on a side of the plurality light emitting elements LE and the pixel definition layer30away from the base substrate10, an organic encapsulating sub-layer42on a side of the first inorganic encapsulating sub-layer41away from the base substrate10, and a second inorganic encapsulating sub-layer43on a side of the organic encapsulating sub-layer42away from the first inorganic encapsulating sub-layer41. Optionally, the first inorganic encapsulating sub-layer41extends into the first groove GE1and is in direct contact with the surface of the first portion P1(e.g., the first side S1of the first portion P1as shown inFIGS. 11 to 13). Optionally, in a region corresponding to the first groove GE1, the encapsulating layer40further includes an organic encapsulating sub-layer42on a side of the first inorganic encapsulating sub-layer41away from the base substrate10, and a second inorganic encapsulating sub-layer43on a side of the organic encapsulating sub-layer42away from the first inorganic encapsulating sub-layer41.

Referring toFIG. 8andFIG. 10, in some embodiments, the first power pad PP includes a first portion P1in the peripheral area PA and along a power line interface side of the display substrate, and at least one second portion P2connected to the first portion P1and extending from the first portion P1away from the display area DA. Optionally, the at least one second portion P2is at least partially covered by one or a combination of the pixel definition layer30and the planarization layer20. Referring toFIG. 7, in some embodiments, the at least one second portion P2includes two second portions (one on left and another on right inFIG. 7) connected to the first portion P1respectively at different locations and extending from the first portion P1away from the display area DA. Optionally, the first portion P1and the two second portions of the at least one second portion P2form a pi-shaped structure.

In some embodiments, and referring toFIG. 10, the display substrate has a second groove GE2extending through one or a combination of the planarization layer20and the pixel definition layer30, exposing a surface of the at least one second portion P2of the first power pad PP1in the peripheral area PA. The encapsulating layer40extends into the second groove GE2and is in direct contact with the surface of the at least one second portion P2. For example, the first inorganic encapsulating sub-layer41extends into the second groove GE2and is in direct contact with the surface of the at least one second portion P2.

Optionally, in a region corresponding to the second groove GE2, the encapsulating layer40further includes an organic encapsulating sub-layer42on a side of the first inorganic encapsulating sub-layer41away from the base substrate10, and a second inorganic encapsulating sub-layer43on a side of the organic encapsulating sub-layer42away from the first inorganic encapsulating sub-layer41.

Optionally, in a region corresponding to the second groove GE2, the encapsulating layer40further includes a second inorganic encapsulating sub-layer43on a side of the first inorganic encapsulating sub-layer41away from the base substrate10. In one example, in a region corresponding to the second groove GE2, the organic encapsulating sub-layer42is not present.

In some embodiments, and referring toFIG. 9, the second power pad PP2includes at least one third portion P3on the power line interface side of the display substrate. The at least one third portion P3is at least partially covered by one or a combination of the pixel definition layer30and the planarization layer20. In some embodiments, the display substrate has a second groove GE2extending through one or a combination of the planarization layer20and the pixel definition layer30, exposing a surface of the at least one third portion P3of the second power pad PP2in the peripheral area PA. The encapsulating layer40extends into the second groove GE2and is in direct contact with the surface of the at least one third portion P3. For example, the first inorganic encapsulating sub-layer41extends into the second groove GE2and is in direct contact with the surface of the at least one third portion P3. Optionally, in a region corresponding to the second groove GE2, the encapsulating layer40further includes an organic encapsulating sub-layer42on a side of the first inorganic encapsulating sub-layer41away from the base substrate10, and a second inorganic encapsulating sub-layer43on a side of the organic encapsulating sub-layer42away from the first inorganic encapsulating sub-layer41.

In some embodiments, and referring toFIG. 9andFIG. 10, the display substrate has a second groove GE2extending through one or a combination of the planarization layer20and the pixel definition layer30, exposing a surface of the at least one second portion P2of the first power pad PP1in the peripheral area PA and a surface of the at least one third portion P3of the second power pad PP2in the peripheral area PA. The encapsulating layer40extends into the second groove GE2and is in direct contact with the surface of the at least one second portion P2and the surface of the at least one third portion P3. For example, the first inorganic encapsulating sub-layer41extends into the second groove GE2and is in direct contact with the surface of the at least one second portion P2and the surface of the at least one third portion P3.

Optionally, in a region corresponding to the second groove GE2, the encapsulating layer40further includes an organic encapsulating sub-layer42on a side of the first inorganic encapsulating sub-layer41away from the base substrate10, and a second inorganic encapsulating sub-layer43on a side of the organic encapsulating sub-layer42away from the first inorganic encapsulating sub-layer41.

Optionally, in a region corresponding to the second groove GE2, the encapsulating layer40further includes a second inorganic encapsulating sub-layer43on a side of the first inorganic encapsulating sub-layer41away from the base substrate10. In one example, in a region corresponding to the second groove GE2, the organic encapsulating sub-layer42is not present.

In some embodiments, and referring toFIG. 10, the display substrate has a third groove GE3extending through one or a combination of the planarization layer20and the pixel definition layer30, exposing a surface of the at least one second portion P2of the first power pad PP1in the peripheral area PA. The encapsulating layer40extends into the third groove GE3and is in direct contact with the surface of the at least one second portion P2. For example, the first inorganic encapsulating sub-layer41extends into the third groove GE3and is in direct contact with the surface of the at least one second portion P2. Optionally, in a region corresponding to the third groove GE3, the encapsulating layer40further includes a second inorganic encapsulating sub-layer43on a side of the first inorganic encapsulating sub-layer41away from the base substrate10. In one example, in a region corresponding to the third groove GE3, the organic encapsulating sub-layer42is not present.

In some embodiments, and referring toFIG. 9, the display substrate has a third groove GE3extending through one or a combination of the planarization layer20and the pixel definition layer30, exposing and a surface of the at least one third portion P3of the second power pad PP2in the peripheral area PA. The encapsulating layer40extends into the third groove GE3and is in direct contact with the surface of the at least one third portion P3. For example, the first inorganic encapsulating sub-layer41extends into the third groove GE3and is in direct contact with the surface of the at least one third portion P3. Optionally, in a region corresponding to the third groove GE3, the encapsulating layer40further includes a second inorganic encapsulating sub-layer43on a side of the first inorganic encapsulating sub-layer41away from the base substrate10. In one example, in a region corresponding to the third groove GE3, the organic encapsulating sub-layer42is not present.

In some embodiments, and referring toFIG. 9andFIG. 10, the display substrate has a third groove GE3extending through one or a combination of the planarization layer20and the pixel definition layer30, exposing a surface of the at least one second portion P2of the first power pad PP1in the peripheral area PA and a surface of the at least one third portion P3of the second power pad PP2in the peripheral area PA. The encapsulating layer40extends into the third groove GE3and is in direct contact with the surface of the at least one second portion P2and the surface of the at least one third portion P3. For example, the first inorganic encapsulating sub-layer41extends into the third groove GE3and is in direct contact with the surface of the at least one second portion P2and the surface of the at least one third portion P3. Optionally, in a region corresponding to the third groove GE3, the encapsulating layer40further includes a second inorganic encapsulating sub-layer43on a side of the first inorganic encapsulating sub-layer41away from the base substrate10. In one example, in a region corresponding to the third groove GE3, the organic encapsulating sub-layer42is not present.

Referring toFIGS. 8 to 10, in some embodiments, the at least one third portion P3is on a side of the first portion P1extending away from the display area. The first portion P1and a respective one of the at least one third portion P3are spaced apart by a first gap G. The first groove GE1is on a side of the first gap G1closer to the display area DA. Optionally, the planarization layer20extends into the first gap G1. In some embodiments, the at least one second portion P2and the at least one third portion P3are on a side of the first portion P1extending away from the display area. A respective one of the at least one second portion P2is spaced apart from a respective one of the at least one third portion P3by a second gap G2connected to the first gap G. Optionally, the planarization layer20extends into the first gap G1and the second gap G2.

Various appropriate light emitting elements may be used in the present display substrate. Examples of appropriate light emitting elements include organic light emitting diodes, quantum dots light emitting diodes, and micro light emitting diodes.

In another aspect, the present disclosure provides a display apparatus including a display substrate described herein or fabricated by a method described herein, and one or more integrated circuits connected to the display substrate. Optionally, the display apparatus includes a display panel. Optionally, the display panel includes the display substrate described herein or fabricated by a method described herein, and a counter substrate. Examples of appropriate display apparatuses include, but are not limited to, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital album, a GPS, etc. Optionally, the stretchable display apparatus further includes one or more integrated circuits connected to the stretchable display panel.

In another aspect, the present disclosure provides a method of fabricating a display substrate. In some embodiments, the method includes forming a first power pad on a base substrate, the first power pad formed to include a first portion in the peripheral area and along a power line interface side of the display substrate; forming a planarization layer on a side of the first power pad away from the base substrate; forming a pixel definition layer on a side of the planarization layer away from the base substrate, defining a plurality of subpixel apertures; forming a first groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the first portion of the first power pad in the peripheral area; and forming an encapsulating layer on a side of the pixel definition layer away from the base substrate, the encapsulating layer formed to extend into the first groove and be in direct contact with the surface of the first portion, thereby encapsulating the display substrate.

In some embodiments, the first portion is formed to have a first side away from the base substrate, a second side opposite to the first side and closer to the base substrate, a third side connecting the first side and the second side and closer to the display area, and a fourth side connecting the first side and the second side, the fourth side being opposite to the third side and away from the display area. Optionally, the fourth side of the first portion is formed to be covered by one or a combination of the pixel definition layer and the planarization layer. The first groove is formed to expose a portion of the first side. Optionally, the first portion is formed so that the fourth side has a concave surface. Optionally, the first portion is formed to include a plurality of sub-layers, at least one of which is over-etched on the fourth side, thereby forming the concave surface.

In some embodiments, forming the encapsulating layer includes forming a first inorganic encapsulating sub-layer on a side of the plurality light emitting elements and the pixel definition layer away from the base substrate, forming an organic encapsulating sub-layer on a side of the first inorganic encapsulating sub-layer away from the base substrate, and forming a second inorganic encapsulating sub-layer on a side of the organic encapsulating sub-layer away from the first inorganic encapsulating sub-layer. Optionally, the first inorganic encapsulating sub-layer is formed to extend into the first groove and be in direct contact with the surface of the first portion. Optionally, in a region corresponding to the first groove, the organic encapsulating sub-layer is formed on a side of the first inorganic encapsulating sub-layer away from the base substrate, and a second inorganic encapsulating sub-layer is formed on a side of the organic encapsulating sub-layer away from the first inorganic encapsulating sub-layer.

In some embodiments, forming the first power pad further includes forming at least one second portion connected to the first portion and extending from the first portion away from the display area. Optionally, one or a combination of the pixel definition layer and the planarization layer is formed to at least partially cover the at least one second portion. Optionally, the method further includes forming a second groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the at least one second portion of the first power pad in the peripheral area. Optionally, the encapsulating layer is formed to extend into the second groove and be in direct contact with the surface of the at least one second portion. Optionally, the first inorganic encapsulating sub-layer is formed to extend into the second groove and be in direct contact with the surface of the at least one second portion. Optionally, in a region corresponding to the second groove, an organic encapsulating sub-layer is formed on a side of the first inorganic encapsulating sub-layer away from the base substrate, and a second inorganic encapsulating sub-layer is formed on a side of the organic encapsulating sub-layer away from the first inorganic encapsulating sub-layer.

In some embodiments, forming the at least one second portion includes forming two second portions connected to the first portion respectively at different locations and extending from the first portion away from the display area. Optionally, the first portion and the two second portions are formed to have a pi-shaped structure.

In some embodiments, the method further includes forming a second power pad on the base substrate and in the peripheral area, the second power pad formed to be spaced apart from the first power pad. Optionally, forming the second power pad includes forming at least one third portion on the power line interface side of the display substrate. Optionally, one or a combination of the pixel definition layer and the planarization layer is formed to at least partially cover the at least one third portion. Optionally, the second groove is formed to extend through one or a combination of the planarization layer and the pixel definition layer, further exposing a surface of the at least one third portion of the second power pad in the peripheral area. Optionally, the encapsulating layer is formed to extend into the second groove and be in direct contact with the surface of the at least one third portion.

In some embodiments, the first portion and a respective one of the at least one third portion are formed to be spaced apart by a first gap. Optionally, the first groove is formed on a side of the first gap closer to the display area. Optionally, the planarization layer is formed to extend into the first gap. Optionally, the at least one second portion and the at least one third portion are formed so that a respective one of the at least one second portion is spaced apart from a respective one of the at least one third portion by a second gap connected to the first gap. Optionally, the planarization layer is formed to extend into the first gap and the second gap.

In some embodiments, the method further includes forming a third groove extending through one or a combination of the planarization layer and the pixel definition layer, exposing a surface of the at least one second portion of the first power pad in the peripheral area. Optionally, the first inorganic encapsulating sub-layer is formed to extend into the third groove and is formed to be in direct contact with the surface of the at least one second portion. Optionally, in a region corresponding to the third groove, a second inorganic encapsulating sub-layer is formed on a side of the first inorganic encapsulating sub-layer away from the base substrate, the second inorganic encapsulating sub-layer is formed to be in direct contact with the first inorganic encapsulating sub-layer.

Optionally, the third groove is formed to expose a surface of the at least one third portion of the second power pad in the peripheral area. Optionally, the first inorganic encapsulating sub-layer is formed to extend into the third groove and is formed to be in direct contact with the surface of the at least one third portion. Optionally, in a region corresponding to the third groove, a second inorganic encapsulating sub-layer is formed on a side of the first inorganic encapsulating sub-layer away from the base substrate, the second inorganic encapsulating sub-layer is formed to be in direct contact with the first inorganic encapsulating sub-layer.