Integrated etch stop for capped gate and method for manufacturing the same

A semiconductor device includes a plurality of gate stacks spaced apart from each other on a substrate, an etch stop layer formed on an upper surface of each gate stack, a dielectric cap layer formed on each etch stop layer, a plurality of source/drain regions formed on the substrate between respective pairs of adjacent gate stacks, and a plurality of contacts respectively corresponding to each source/drain region, wherein the contacts are separated from the gate structures and contact their corresponding source/drain regions.

TECHNICAL FIELD

The field generally relates to semiconductor devices and methods of manufacturing same and, in particular, to semiconductor devices having an etch stop integrated into a gate stack which allows controlled recessing of the gate stack to create an insulating gate cap.

BACKGROUND

At small contacted gate pitch, overlay tolerances are an unacceptably large portion of the layout footprint for source/drain contact design, leading to a need for self-aligned source/drain contacts. Current methods for achieving a self-aligned source/drain contact in a replacement gate flow involve timed etch-back of a filled metal gate stack followed by a dielectric fill.

However, state-of-the-art metal gate stacks typically include many different materials such as, for example, a high-k dielectric, workfunction setting materials, workfunction modification materials, and conductive filler materials. As a result, uniform etch-back of this multi-material gate stack can be very difficult to achieve, thereby increasing the risk of shorting between source/drain contacts and gate stacks.

SUMMARY

According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a plurality of channel material layers and a plurality of sacrificial material layers in a stacked configuration on a substrate, wherein one of the plurality of sacrificial material layers is a top layer of the stacked configuration, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, removing portions of the stacked configuration to create openings in the stacked configuration corresponding to spaces between adjacent dummy gates, epitaxially growing source/drain regions from the channel material layers in the openings corresponding to the spaces between the adjacent dummy gates, depositing dielectric layers to fill in the spaces between the adjacent dummy gates and portions of the openings around the source/drain regions, removing the dummy gates, forming etch stop layers on remaining portions of the top layer of the stacked configuration, removing remaining portions of the plurality of sacrificial material layers, depositing gate structures on respective upper surfaces the etch stop layers in areas where the dummy gates were removed, and under the etch stop layers in areas where the remaining portions of the plurality of sacrificial material layers were removed, removing the gate structures from the upper surfaces of the etch stop layers to expose the upper surfaces of the etch stop layers, depositing dielectric cap layers on the upper surfaces of the etch stop layers in place of the removed gate structures, and forming contacts through the dielectric layers between adjacent dielectric cap layers, wherein the contacts contact the source/drain regions.

According to an exemplary embodiment of the present invention, a semiconductor device includes a plurality of gate stacks spaced apart from each other on a substrate, an etch stop layer formed on an upper surface of each gate stack, a dielectric cap layer formed on each etch stop layer, a plurality of source/drain regions formed on the substrate between respective pairs of adjacent gate stacks, and a plurality of contacts respectively corresponding to each source/drain region, wherein the contacts are separated from the gate structures and contact their corresponding source/drain regions.

According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a plurality of channel material layers and a plurality of sacrificial material layers in a stacked configuration on a substrate, wherein one of the plurality of sacrificial material layers is a top layer of the stacked configuration, removing portions of the stacked configuration to create openings in the stacked configuration, epitaxially growing source/drain regions from the channel material layers in the openings, depositing dielectric layers to fill in portions of the openings around the source/drain regions, forming etch stop layers on remaining portions of the top layer of the stacked configuration, removing remaining portions of the plurality of sacrificial material layers, depositing gate structures on respective upper surfaces the etch stop layers, and under the etch stop layers in areas where the remaining portions of the plurality of sacrificial material layers were removed, removing the gate structures from the upper surfaces of the etch stop layers to expose the upper surfaces of the etch stop layers, depositing dielectric cap layers on the upper surfaces of the etch stop layers in place of the removed gate structures, and forming contacts between adjacent dielectric cap layers, wherein the contacts contact the source/drain regions.

These and other exemplary embodiments of the invention will be described in or become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

DETAILED DESCRIPTION

Exemplary embodiments of the invention will now be discussed in further detail with regard to semiconductor devices and methods of manufacturing same and, in particular, to semiconductor devices having an etch stop integrated into a gate stack which allows controlled recessing of the gate stack to create an insulating gate cap.

It is to be understood that the various layers and/or regions shown in the accompanying drawings are not drawn to scale, and that one or more layers and/or regions of a type commonly used in complementary metal-oxide semiconductor (CMOS), fin field-effect transistor (FinFET), metal-oxide-semiconductor field-effect transistor (MOSFET), and/or other semiconductor devices in which self-aligned contacts may be used, may not be explicitly shown in a given drawing. This does not imply that the layers and/or regions not explicitly shown are omitted from the actual devices. In addition, certain elements may be left out of particular views for the sake of clarity and/or simplicity when explanations are not necessarily focused on the omitted elements. Moreover, the same or similar reference numbers used throughout the drawings are used to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings.

The semiconductor devices and methods for forming same in accordance with embodiments of the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings of embodiments of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.

The embodiments of the present invention can be used in connection with semiconductor devices that may require, for example, CMOSs, MOSFETs, and/or FinFETs. By way of non-limiting example, the semiconductor devices can include, but are not limited to CMOS, MOSFET, and FinFET devices, and/or semiconductor devices that use CMOS, MOSFET, and/or FinFET technology.

As used herein, with reference to the drawings, “parallel to a gate extension direction” refers to an extension direction of a gate structure perpendicular to a channel length and to the left and right in these cross-sections. In other words, left and right in these cross-sections represents a width direction of the channels, and the length of the channels are going into the page.

As used herein, with reference to the drawings, “perpendicular to a gate extension direction” or “across a channel of a gate structure” refers to a channel length direction of a gate structure being to the left and right in these cross-sections. In other words, left and right in these cross-sections represents a length direction of the channels, and the width of the channels and extension direction of the gate structure are going into the page.

As used herein, “vertical” refers to a direction perpendicular to a substrate in the cross-sectional views.

As used herein, “horizontal” refers to a direction parallel to a substrate in the cross-sectional views.

As used herein, “height” refers to a vertical size of an element (e.g., a layer, trench, hole, etc.) in the cross-sectional views measured from a bottom surface to a top surface of the element, and/or measured with respect to a surface on which the element is directly on. Conversely, a “depth” refers to a vertical size of an element (e.g., a layer, trench, hole, etc.) in the cross-sectional views measured from a top surface to a bottom surface of the element.

As used herein, “lateral,” “lateral side,” “lateral surface” refers to a side surface of an element (e.g., a layer, opening, etc.), such as a left or right side surface in the cross-sectional views.

As used herein, “width” or “length” refers to a size of an element (e.g., a layer, trench, hole, etc.) in the figures measured from a side surface to an opposite surface of the element.

Embodiments of the present invention provide a structure and method for integrating an etch stop into a replacement gate stack. The etch stop allows subsequent controlled recessing of the gate stack for the purposes of creating an insulating gate cap. The gate cap enables source/drain contact vias to be etched without risk of shorting to the gate.

According to an embodiment of the present invention, to create an integrated etch stop, a sacrificial material is provided on the top surface of an upper channel layer of a stacked configuration of sacrificial and channel materials. The top surface of the sacrificial material provided on the upper channel layer is used to selectively form an etch stop layer, which is then incorporated into a replacement gate stack.

FIG. 1is a cross-sectional view of a semiconductor substrate taken parallel to a gate extension direction and illustrating a stacked configuration of sacrificial and channel materials on a buried insulating layer, according to an exemplary embodiment of the present invention. Referring toFIG. 1, a semiconductor substrate102can be, for example, a silicon-on-insulator (SOI) substrate including a buried insulating layer104, such as, for example, a buried oxide or nitride layer located on an upper surface of the semiconductor substrate102. The substrate102may comprise semiconductor material including, but not limited to, Si, SiGe, SiC, SiGeC, III-V, II-V compound semiconductor or other like semiconductor. In addition, multiple layers of the semiconductor materials can be used as the semiconductor material of the substrate.

In accordance with an embodiment of the present invention, as can be seen inFIG. 1, layers of sacrificial material105a,105b,105cand105dare alternately stacked with layers of channel material107a,107band107c. The sacrificial material can include, for example, silicon germanium (SiGe) and the channel material can include, for example, silicon (Si). The SiGe and Si layers can be epitaxially grown in an alternating and stacked configuration, so that a first sacrificial layer105a(e.g., SiGe) is followed a first channel layer107a(e.g., Si) on the first sacrificial layer, which is followed by a second sacrificial layer105bon the first channel layer107a, and so on. While four sacrificial layers105a-105dand three channel layers107a-107care shown, the embodiments of the present invention are not necessarily limited to the shown number of layers105,107, and there may be more or less layers in the same alternating configuration depending on design constraints.

Terms such as “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will take on a {100} orientation. In some embodiments, epitaxial growth and/or deposition processes are selective to forming on a semiconductor surface, and do not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

Examples of various epitaxial growth processes include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for an epitaxial deposition process can range from, for example, 550° C. to 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking.

A number of different sources may be used for the epitaxial growth of SiGe sacrificial layers and Si channel layers. In some embodiments, a gas source for the deposition of epitaxial semiconductor material includes a silicon containing gas source, a germanium containing gas source, or a combination thereof. For example, an epitaxial silicon layer may be deposited from a silicon gas source that is selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. While an epitaxial silicon germanium alloy layer can be formed utilizing a combination of such gas sources. Carrier gases like hydrogen, nitrogen, helium and argon can be used.

In accordance with an embodiment of the present invention, the epitaxial growth is performed by growing layers, each of which has a height (in the vertical direction in the figures) of between approximately 5 nm and approximately 25 nm. According to an embodiment, approximately between 3 and 5 pairs of layers105,107are formed. The alternating structure may be formed by in-situ epitaxy of layers105and107in a rapid thermal chemical vapor deposition (RTCVD) chamber, and by controlling the gas flow, pressure, and temperature in the chamber, as well as the duration of the in-situ epitaxy.

In accordance with an embodiment of the present invention, the top sacrificial layer105dcomprising SiGe, has a higher Ge concentration than the other sacrificial layers105a-c. For example, the Ge concentration of the top sacrificial layer105dcan be in the range of about 25% to about 50%, while the Ge concentration of the other sacrificial layers105a-ccan be in the range of about 15% to about 25%. The higher Ge concentration enhances oxidation rate during a subsequent high pressure oxidation (HIPDX) step described below in connection withFIG. 11.

A mask layer110, such as, for example, silicon oxide or silicon nitride is formed on the sacrificial layer105dfor a subsequent patterning step described below in connection withFIG. 2.

FIG. 2Ais a top view andFIG. 2Bis a cross-sectional view of a semiconductor substrate taken along line A-A′ parallel to a gate extension direction illustrating patterning of the SiGe and silicon stack, according to an exemplary embodiment of the present invention. Patterning is performed by, for example, etching, such as, for example, an isotropic etching process, such as reactive ion etching (ME) using, for example, HBr/Cl2/O2, HBr/O2, or BCl3/Cl2, SF6. The top sacrificial layer105dprevents erosion of the top channel layer107c.

As can be seen inFIGS. 2B and 3, the patterning decreases a width of the SiGe and silicon layers105and107along an extension direction of a gate structure, and maintains a length along a channel length direction to result in patterned stacks115. The resulting width and pitch of SiGe and silicon stacks115are about 5 nm to about 50 nm and about 6 nm to about 60 nm, respectively.

The etching is performed using, for example, the RIE process and a mask110including, for example, a nitride, oxide, or an organic resist, covering what is to be a remaining portion of SiGe and silicon layers105,107.

FIG. 3Ais a top view andFIG. 3Bis a cross-sectional view of a semiconductor substrate taken along line B-B′ perpendicular to a gate extension direction illustrating deposition and patterning of dummy gates in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIGS. 3A-3B, dummy gate material, including, but not necessarily limited to, silicon dioxide, silicon nitride, amorphous silicon, or polysilicon, is deposited on the substrate including the SiGe and silicon stacks115using deposition techniques such as, for example, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), radio-frequency CVD (RFCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD), and/or liquid source misted chemical deposition (LSMCD), sputtering, and/or plating, followed by a planarization process, such as, chemical mechanical planarization (CMP), and lithography and etching steps to remove excess dummy gate material, and pattern the deposited layers into dummy gates120.

FIG. 4is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating spacer formation in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIG. 4, a conformal dielectric, such as, for example, silicon nitride, silicon dioxide, or low-k materials, is deposited on sidewalls of the dummy gates120and on portions of the Si and SiGe stacks115to form spacers125. Deposition can be performed using deposition techniques including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, and/or LSMCD, sputtering, and/or plating. Portions of the conformal dielectric are anisotropically etched to remove the spacer material from unwanted areas of the dummy gates120and channel sidewalls.

FIG. 5is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating removal of portions of SiGe and silicon stacks where source/drain (S/D) regions will be formed, in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIG. 5, removal is performed by, for example, etching, such as, for example, an isotropic etching process, such as RIE using HBr/Cl2/O2, HBr/O2, or BCl3/Cl2, SF6. As can be seen inFIG. 5, the patterning removes portions of the SiGe and silicon stacks115between the dummy gates120.

FIG. 6is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating recessing of the sacrificial layers105a-d, in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIG. 6, recessing is performed by, for example, a timed isotropic selective etch, such as, for example, RIE using HCL. As can be seen inFIG. 6, the patterning removes exposed side portions of the layers105a-105dto recess the layers105a-105dwith respect to the layers107a-107c.

FIG. 7is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating spacer removal, in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIG. 7, the spacers125are removed using, for example, an isotropic etching process, such as, for example, RIE using CF4/O2, CHF3/O2, CH2F2, or CH2CHF2, or a wet etch process using, for example, glycated buffered hydrofluoric acid 5:1:1. As can be seen inFIG. 7, the spacers125are removed from sidewalls of the dummy gates120and sidewalls of the SiGe and silicon stacks115.

FIG. 8is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating spacer formation in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIG. 8, a conformal dielectric, such as, for example, silicon nitride, silicon dioxide, or low-k materials, is deposited on sidewalls of the dummy gates120and on portions of the Si and SiGe stacks115to form spacers225. As can be seen inFIG. 8, the spacers225are formed on the layers105a-105dto fill in the recesses between the layers107a-107c. Deposition can be performed using deposition techniques including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, and/or LSMCD, sputtering, and/or plating. Portions of the conformal dielectric may be anisotropically etched to remove the spacer material from unwanted areas of the dummy gates120and channel sidewalls.

FIG. 9is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating epitaxial growth of source/drain regions in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIG. 9, the exposed sidewalls of layers107a-107care epitaxially grown to form source/drain regions207. As noted above, based on a material of the layers107a-107cbeing silicon, the epitaxial regions can be formed from a silicon gas source including, but not limited to, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. Referring toFIG. 9, growth is stopped prior to merging of the regions207. Alternatively, growth may occur until or after merging of the regions207.

FIG. 10is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating dielectric fill and dummy gate removal in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIG. 10, dielectric layers204are deposited using deposition techniques, including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, and/or LSMCD, sputtering, and/or plating followed by a planarization process, such as, CMP. According to an embodiment, the dielectric layers204can include the same material as the buried insulating layer104, such as, for example, silicon oxide or silicon nitride, or other dielectrics.

The dummy gate layers120can be removed after deposition and planarization of the dielectric layers204. Removal of the dummy gate layers120is performed by, for example, etching, using, in the case of amorphous and polysilicon, HBr/Cl2/O2, HBr/O2, or BCl3/Cl2, SF6. As can be seen, the top sacrificial layers105dand a portion of a dummy gate120on the buried insulating layer104remain after the dielectric deposition and planarization and dummy gate removal steps.

FIG. 11is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating formation of an etch stop layer in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIG. 11, etch stop layers140are selectively formed on the top sacrificial layers105d. In accordance with an embodiment of the present invention, the etch stop layers are formed using a HIPDX process. More specifically, SiGe of the top sacrificial layer105d, as noted above, has a higher Ge concentration than the other sacrificial layers105a-cto enhance an oxidation rate during the HIPDX process. Germanium oxidizes much faster than silicon for given oxidation conditions, so higher Ge concentration SiGe oxidizes faster than lower concentration SiGe or silicon. The HIPDX process is performed on the sacrificial layers150dto result in the etch stop layers140. The HIPDX is performed at, for example, about 20 times to about 50 times atmospheric pressure. During the HIPDX process, silicon atoms in the layer105dbond with oxygen that is available during the HIPDX process to form the etch stop layers140, comprising, for example, SiO2.

The HIPDX is performed at a temperature from about 900° C. to about 1200° C. In accordance with an embodiment of the present invention, the HIPDX is performed in an oxidizing ambient which includes at least one oxygen-containing gas such as, for example, O2, NO, N2O, ozone, air and other like oxygen-containing gases. The oxygen-containing gases may be admixed with each other (such as an admixture of O2and NO), or the gas may be diluted with an inert gas such as, for example, He, Ar, N2, Xe, Kr, or Ne.

In accordance with an embodiment of the present invention, the HIPDX may be carried out for a variable period of time. In one example, the HIPDX is carried out for a time period from about 1 min to about 30 min, depending on pressure, oxidation temperature and oxidation species. The HIPDX may be carried out at a single targeted pressure, or various ramp and soak cycles using various ramp rates and soak times can be employed. According to an embodiment, the HIPDX process is performed until upper portions of the sacrificial layers105dare consumed to form the etch stop layers140. As an alternative to HIPDX, other processes, including, but not limited to, selective ALD may be used to form the etch stop layers140.

FIG. 12is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating removal of a remaining portion a dummy gate in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIG. 12, after formation of the etch stop layers, remaining portions of the dummy gate layers120can be removed by, for example, etching as described in connection withFIG. 10.

FIG. 13is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating removal of remaining sacrificial layers in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIG. 13, the remaining unoxidized portion of sacrificial layer105d, and remaining sacrificial layers105a-105care removed using, for example, a selective isotropic etch of the sacrificial material. In accordance with an embodiment of the present invention, the remaining sacrificial layers can be etched using, for example, HCl.

FIG. 14is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating deposition of gate structures in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIG. 14, gate structures155are deposited in the spaces left after removal of the dummy gates120and the sacrificial layers105a-105d, using deposition techniques, including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, and/or LSMCD, sputtering, and/or plating followed by a planarization process, such as, CMP. According to an embodiment, the gate structures155can include dielectric layers, including, but not limited to, HfO2(hafnium oxide), ZrO2(zirconium dioxide), hafnium zirconium oxide Al2O3(aluminum oxide), Ta2O5(tantalum pentoxide) or combinations thereof, workfunction layers, including, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), titanium aluminum nitride (TiAlN), titanium aluminum carbon nitride (TiAlCN), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum carbon nitride (TaAlCN), lanthanum (La) doped TiN, or combinations thereof, and filler layers, including but not limited to, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, tantalum magnesium carbide, or combinations thereof.

FIG. 15Ais a top view andFIG. 15Bis a cross-sectional view of a semiconductor substrate taken along line C-C′ perpendicular to a gate extension direction illustrating recessing of gate structures in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIGS. 15A-15B, recessing of the gate structures155is performed by, for example, etching, using a chemistry known in the art that is appropriate for the material deposited. As can be seen, gate structures155are recessed down to the etch stop layers140. According to an embodiment of the present invention, all gate structures155can be recessed or, as shown inFIG. 15B, only those gate structures155adjacent to source/drain contact areas.

FIG. 16Ais a top view andFIG. 16Bis a cross-sectional view of a semiconductor substrate taken along line D-D′ perpendicular to a gate extension direction illustrating formation of dielectric cap layers in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIGS. 16A-16B, dielectric cap layers160are deposited on the etch stop layers140using deposition techniques, including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, and/or LSMCD, sputtering, and/or plating followed by a planarization process, such as, CMP. According to an embodiment, the dielectric cap layers160can include, but are not limited to, silicon dioxide, silicon nitride, low-k materials or other dielectrics.

FIG. 17is a cross-sectional view of a semiconductor substrate taken perpendicular to a gate extension direction and illustrating removal of portions of a dielectric layer in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention.FIG. 18Ais a top view andFIG. 18Bis a cross-sectional view of a semiconductor substrate taken along line E-E′ perpendicular to a gate extension direction illustrating deposition of contact structures after removal of portions of a dielectric layer in a method of manufacturing a semiconductor device, according to an exemplary embodiment of the present invention. Referring toFIGS. 17 and 18A-18B, source/drain contact structures175are formed in contact area vias170left after removal of portions of the dielectric layer204over the source/drain regions207.

The portions of the dielectric layer204over the source/drain regions207are removed to form contact area vias170by using, for example, an etch process which is selective to the dielectric cap layers160. The etch process can include, but is not limited to, RIE using, for example, CF4/O2, CF4/CHF3/Ar, C2F6, C3F8, C4F8/CO, C5F8, or CH2F2. The dielectric cap layers160enable the source/drain contact vias170to be etched without risk of shorting to the underlying gate structure155.

The source/drain contact structures175are deposited using deposition techniques, including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, and/or LSMCD, sputtering, and/or plating followed by a planarization process, such as, CMP. According to an embodiment, the source/drain contact structures175can include, but are not limited to, tungsten, cobalt, ruthenium, copper, or combinations thereof. Silicides, such as, for example, CoSi, NiSi, TiSi, are formed prior to deposition of the source/drain contact materials, which are deposited on the silicides.