Apparatus for partitioning and processing a digital image using two or more defined regions

Apparatus for partitioning a digital image into multiple regions where each of the multiple regions is defined using a portion of the digital image and is specified using a width and a height. In addition, neighboring pixels for each of the multiple regions are defined as margins and may contain pixels that are part of the digital image and/or newly generated pixels by using various techniques such as on the fly generation or using a predetermined process for data generation, e.g. replication. Each of the multiple regions is combined with its margin pixels to create a new quadrilateral digital image that is completely processed and/or scaled. The appropriate portion of the processed quadrilateral digital image is displayed using a display region of an electronic display panel, or monitor, having multiple display regions. The concatenation of the images displayed using each display region faithfully reproduce the original digital image.

TECHNICAL FIELD

The subject of this application generally relates to the field of digital image processing and more particularly to digital image scaling from an original image size to a target image size.

BACKGROUND

Traditional cameras are used to take photographs by capturing light onto photographic films. Digital cameras use electronic devices such as Charge Coupled Devices (CCD) to capture light, of an original image, and produce a digital representation of an image. The digital representation can be further manipulated using different compression or transmission techniques or standards such as Moving Picture Experts Group (MPEG). Furthermore, the digital representation of the image can be stored in various digital formats in accordance with the intended memory storage mediums e.g. Hard disk, DVD, CD-Rom, etc. . . . such that the reproduction of the original image may be achieved using a variety of means or mediums using the stored digital representation of the original image. For examples, electronic display devices can display the image on their screen.

The digital representation of the image can greatly vary in quality depending on the sampling of the original image. Each sample of the original image represents a small portion of the overall image. Therefore, more samples are required in order to have a better or more accurate representation of the original image. A pixel represents one sample of the original image. Normally, an image is sampled using a two-dimensional grid having a width, X, and a height, Y, that are specified in unit of pixel, where the digital image resolution corresponds to X time Y, and each pixel corresponds to the smallest single component of the original image. For example, a first camera with a resolution of 640×480 would have 640 pixels in the horizontal direction and 480 pixels in the vertical direction. The digital image resolution, total number of pixels, is 307,200 pixels. Higher resolution requires more pixels to be generated when capturing an image, and the closer the digital image produced is to the original image. Hence, a second digital camera with a resolution of 1280×960 would have a total number of pixels of 1,228,800 pixels or four times the resolution of the first camera.

Each pixel of a digital image corresponds to data information that is expressed as a number of bits that is used to describe each pixel (or sample) of the original image. This data information is normally expressed as number of bits per pixel (bpp). A broader range of distinct colors can be represented with a higher number of bits per pixel. Nowadays, There are many different formats that are in use to capture and/or display color information, e.g. the RGB. For example, a 24-bit color model uses 8 bits to represent red, 8 bits to represent blue and 8 bits to represent green. Under this model, each of these three colors possesses a 28or 256 levels. Therefore, they can be combined (256×256×256) to give a possible 16,777,216 colors.

A video camera captures a scene for a specific duration of time, and produces many sequential digital images. Normally, each digital image is referred to as a frame, having a frame size defined as number of horizontal pixels×number of vertical pixels. A frame rate is also specified that represents the number of frames being captured per second. In addition, a scanning system is identified as progressive or interlaced to indicate how the video frames are generated and thus how they should be processed and displayed so that the original scene is faithfully reproduced when these digital images are played back in sequence, e.g. using an electronic display panel or a digital television set.

In order to reproduce the original scene timing, each digital image, or frame within the scene, must be reproduced and displayed in a given amount of time. Hence, the time required to process and display one pixel is limited and finite. Electronic display devices resolution is specified, in a similar way as explained above for a digital camera, as having X by Y pixels. Again, the higher the resolution of the electronic display device is, the better the image that is being reproduced. As the electronic display panel technology advances to an ever-higher resolution, a bigger challenge to the device electronics is to be able to process data information for each pixel within an ever-smaller amount of time.

The processing demands on electronic circuits for High-Definition television (HD TV), e.g. 1,920 pixels wide and 1,080 pixels high, is much greater than a Standard-Definition television (SD TV), e.g. 720 pixels wide and 480 pixels high. The next generation of digital TVs and projectors, recently developed, will be able to display four times the high definition resolution of current HD TV sets. This Quad-HD set is capable of displaying 3,840 pixels wide and 2,160 pixels high. This presents a big challenge to the processing circuitry, where each pixel must be processed and faithfully reproduced regardless of the input image resolution having a Quad-HD content from standardized interfaces such as HDMI 1.4 or DisplayPort 1.2a and/or other lower resolution such as 1,920×1,080 or lower.

The need arises to provide an electronic system capable of faithfully processing digital images with various resolutions and display them using a Quad-HD resolution display or higher resolution type of electronic display panels. Marseille Networks' 4×HD™ video technology delivers the ability to process digital images to be displayed in 3840×2160 resolution, while selectively removing artifacts and preserving stunning image details. Furthermore, Marseille Networks is the first to introduce Quad-HD solution to home theater systems. Marseille Networks' 4×HD™ video technology provide an efficient system with ample flexibility and processing power for blending and or scaling various types of video image streams, including High-Definition streams, to be displayed over Quad-HD display panel.

DETAILED DESCRIPTION

The present disclosure provides, amongst other things, techniques to minimize or substantially eliminate artifacts when scaling low resolution video or digital images to higher resolution digital images in order to be displayed using electronic display panels with two or more defined regions. In one respect, a digital video comprises many sequential digital images that capture a certain scene for a certain period of time. A digital image is split into multiple regions and each region is then selectively processed and/or scaled so that it can be displayed using a correspondent region of the display. Each of the multiple regions is defined using a portion of the digital image and is specified using a width and a height, in unit of pixel. In addition, neighboring pixels for each of the multiple regions are defined as margins, e.g. Top margin, Right margin, Bottom margin, and Left margin that will be described in details in this disclosure, and are specified to comprise pixels that are part of the digital image and/or newly generated pixels using various techniques such as on the fly or a predetermined data information. The combination of each of the multiple regions and all of its margins are then processed or scaled to produce a processed portion of the digital image. Furthermore, the concatenation of all of the processed portions of the digital image are then displayed, using electronic display panels with multiple defined regions, and thus faithfully reproduce the original digital image.

In general, various processing techniques can be used to process or scale digital images from one specified resolution to another specified resolution. For example, newly available Quad-HD electronic display panels, or can be simply referred to as monitors, can display images using a resolution of 3840×2160 pixels, or 3840 pixels in width and 2160 pixels in height, for a total of 8,294,400 pixels. A high definition digital image may be specified using 1920 pixels in width and 1080 pixels in height, or in other words a resolution of 1,920×1,080 for a total of 2,073,600 pixels. As you can see The Quad-HD monitor is capable of displaying four times the number of pixels that define the digital image using four regions each of which is capable of displaying a full 1,920×1,080 pixels. Normally a low resolution digital image is first scaled to 3840×2160 resolution and then split into four regions, each of which is then displayed using a corresponding region of the monitor. The higher the resolution of an available Quad-monitor is, the higher the processing requirement is to display a given digital image at the full monitor resolution. This disclosure describes a suitable solution to solve the ever-increasing challenge of scaling a given digital image in order to be faithfully reproduced and fully displayed using monitors with multiple defined regions, e.g. Quad-HD monitor.

An exemplary model depicting a digital image100using pixels arranged as a two-dimensional grid is shown inFIG. 1. The digital image100is defined as having a Width110and a Height120, in unit of pixel. The resolution of Digital image100is therefore Width110×Height120pixels. Furthermore, the Digital image100is defined to have four edges, namely, a Topmost edge130, a Rightmost edge140, a Bottommost edge150, and a Leftmost edge160. The Topmost edge130comprises every pixel on a straight line bounded by two end pixels, namely, the Top-leftmost pixel135and the Top-rightmost pixel145. The Rightmost edge140comprises every pixel on a straight line bounded by two end pixels, namely, the Top-rightmost pixel145and the Bottom-rightmost pixel155. The Bottommost edge150comprises every pixel on a straight line bounded by two end pixels, namely, the Bottom-rightmost pixel155and the Bottom-leftmost pixel165. The Leftmost edge160comprises every pixel on a straight line bounded by two end pixels, namely, the Bottom-leftmost pixel165and the Top-leftmost pixel135. The exemplary model of Digital image100will be used throughout the as a mean to describe the underlying inventive concepts and should not be construed as a limitation of the disclosure. For example, the inventive concepts can be applied to a digital image using pixels arranged in various ways including, for example, a three-dimensional grid.

Now referring toFIG. 2A, a region, D1280, of the Digital image200is defined as a quadrangle digital image that is surrounded by a Top edge232, a Right edge242, a Bottom edge252and a Left edge262. D1280comprises all the pixels within the region including the pixels of the Top edge232, the Right edge242, the Bottom edge252and the Left edge262. Furthermore, D1280is specified to have a D1Width212and a D1Height222, in unit of pixel. An exemplary location of the region D1280is shown inFIG. 2Ato be within the Digital image200, near its center. Various locations of the region D1280are possible within, and including, the boundary edges of the Digital image200as defined by a Topmost edge230, a Rightmost edge240, a Bottommost edge250, and a Leftmost edge260. For example, a possible location of D1280can be at the top-leftmost corner of the Digital image200such that the Left edge262, of D1280, is collinear with the Leftmost edge260of the Digital image200. Furthermore, the Top edge232, of D1280, is collinear with the Topmost edge230of the Digital image200.

Referring toFIG. 2B, a Top margin235is defined as a certain number of pixels in the vertical direction and above the Top edge232, regardless of whether the Top edge232is at the boundary of the Digital image200, i.e. the Top edge232is collinear with the Topmost edge230. Similarly, a Bottom margin255is defined as a certain number of pixels in the vertical direction and below the Bottom edge252, regardless of whether the Bottom edge252is at the boundary of the Digital image200, i.e. the Bottom edge252is collinear with the Bottommost edge250. In addition, a Right margin245is defined as a certain number of pixels in the horizontal direction and to the right of the Right edge242, regardless of whether the Right edge242is at the boundary of the Digital image200, i.e. the Right edge242is collinear with the Rightmost edge240. Similarly, a Left margin265is defined as a certain number of pixels in the horizontal direction and to the left of the Left edge262, regardless of whether the Left edge262is at the boundary of the Digital image200, i.e. the Left edge262is collinear with the Leftmost edge260. Subsequently, a new region of the Digital image200can now be defined to comprise the region D1280and all of the surrounding pixels as defined by the Top, Bottom, Right and Left margins around D1280regardless of whether any pixel of any one of the Top, Bottom, Right and Left margins exist within the Digital image200. This will be described in further details in the following paragraphs.

Referring toFIG. 3A, a newly defined quadrilateral digital image305is shown comprising a first region determined as quadrangle digital image D1380. The actual number of pixels, as drawn inFIG. 3A, will be used as an additional illustrative mean in order to describe the relationship between the quadrilateral digital image305and the quadrangle digital image D1380. For example, D1380is determined using a D1Width312, which corresponds to seven pixels as shown, and a D1Height322, which corresponds to four pixels as shown. Thus, the resolution of the region defined by D1380is determined to be 7×4, or a total of 28 pixels. Furthermore, the four edges of the quadrangle digital image D1380are defined as follows: a Top edge332comprising the seven topmost pixels of D1380, a Right edge342comprising the four rightmost pixels of D1380, a Bottom edge352comprising the seven bottommost pixels of D1380, and a Left edge362comprising the four leftmost pixels of D1380. It is thus clear that the region D1380comprises all the pixels that are determined to be within its four edges including the pixels located at the Top edge332, the Right edge342, the Bottom edge352and the Left edge362. We will now describe a second region of the quadrilateral digital image305.

In one embodiment, the second region of the quadrilateral digital image305is determined using a Top margin335, a Right margin345, a Bottom margin355, and a Left margin365using the same number of pixels. For example, each of the Top margin335, the Right margin345, the Bottom margin355, and the Left margin365comprises at least one pixel. An exemplary margin of two pixels is used for all Top, Right, Bottom, and Left margins, as shown inFIG. 3A. The quadrilateral digital image305is then determined and is specified using a Q1Width314and a Q1Height324, in accordance with the following relationships:
Q1Width 314=(Left Margin 365+D1Width 312+Right Margin 345)  Eq. 1
Q1Height 324=(Top Margin 335+D1Height 322+Bottom Margin 355)  Eq. 2
Accordingly, for the exemplary drawing shown inFIG. 3A, the Q1Width314is computed to be eleven pixels, (2+7+2), and the Q1Height324is computed to be eight pixels, (2+4+2). Therefore, the total resolution of the quadrilateral digital image305is 11×8 or a total of 88 pixels as compared with a 7×4 or a total of 28 pixels for D1380. Furthermore, the quadrangle digital image D1380is centered within the quadrilateral digital image305using the Top margin335, the Right margin345, the Bottom margin355, and the Left margin365. In another embodiment, each of the Top margin335, the Right margin345, the Bottom margin355, and the Left margin365may be defined using a different number of pixels, and therefore the quadrangle digital image D1380may somewhat be off-centered within the quadrilateral digital image305as would be determined by the number of margin pixels.

In accordance with one embodiment, the data information for each pixel located in any of the Top margin335, the Right margin345, the Bottom margin355, and the Left margin365is generated using existing data information from any one pixel of the quadrangle digital image D1380, or using predetermined color data information, or any combination thereof. The predetermined color data information may corresponds to any color including black color. In accordance with another embodiment, a Top Wing337is defined to comprise at least one row of pixels that are located directly above the Top Edge332. For example, the Top Wing337comprises two pixels, identified as Top Wing e-pixel338, that are immediately above the correspondent pixel, Top Edge e-pixel333, in the vertical direction, as shown inFIG. 3A. In accordance with yet another embodiment, the Top Wing337is defined to comprise at least one pixel, Top Wing e-pixel338, that is directly above a correspondent pixel, Top Edge e-pixel333, in the vertical direction. It is important to note that the Top Wing e-pixel338data information may be generated using various direct or indirect manipulation, duplication, or management of the data information of the pixel, Top Edge e-pixel333, as is generally known to those of ordinary skill in the art. In accordance with another embodiment, the Top Wing e-pixel338data information is generated using the data information of the pixel, Top Edge e-pixel333, or any other pixel that is located on the Top edge332. In accordance with yet another embodiment, the Top Wing e-pixel338data information is generated using direct or indirect manipulation, duplication, or management of the data information of the pixel, Top Edge e-pixel333, in combination with a predetermined data information that may corresponds to specific color, for example black, gray or any other color. In accordance with a preferred embodiment, the Top Wing e-pixel338data information is generated, on the fly during the processing of the quadrangle digital image D1380, using data information of the pixel, Top Edge e-pixel333, or any other pixel that is located on the Top edge332. In accordance with yet another preferred embodiment, the Top Wing e-pixel338data information is generated, on the fly during the processing of the quadrangle digital image D1380, using any one, or a combination, of the embodiments described above. In addition, a Bottom Wing357comprises at least one row of pixels that are located directly below the Bottom Edge352. The data information for the Bottom Wing357pixels is generated, using corresponding pixels that are located on the Bottom Edge352and in a similar fashion and means as described above for the Top Wing337.

In accordance with a preferred embodiment, a Left Wing367comprises at least one column of pixels that is located immediately to the left of the Left Edge362of the quadrangle digital image D1380. The data information for the Left Wing367pixels is generated using data information of the corresponding pixels that are identified as the leftmost pixels of the Top Wing337, Top Wing e-pixel338as shown the inFIG. 3A, the pixels of the Left Edge362of the quadrangle digital image D1380, and the leftmost pixels of the Bottom Wing357, and in a similar fashion and means as described above for the Top Wing337. For example, the data information for the Left Wing367pixels can be generated using a direct or indirect manipulation, duplication, and/or management processes of the data information of the pixels that are located on any one of the edges of the quadrangle digital image D1380. Furthermore, the data information can be created using predetermined color information, including data information that corresponds to black color, or any other color. Any combination of the above methods may be employed singularly or in combination to generate the data information for the Left Wing367pixels thereof. In addition, various methods based on mathematical or algorithmic means to generate, possibly on the fly, the data information needed for each of the margin pixels may also be used and may be implemented in combination of any of the other methods described above. Similarly, a Right Wing347comprises at least one column of pixels that is located immediately to the right of the Right Edge342of the quadrangle digital image D1380. The data information for the Right Wing347pixels is generated using data information of the corresponding pixels that are identified as the rightmost pixels of the Top Wing337, the pixels of the Right Edge342of the quadrangle digital image D1380, and the rightmost pixels of the Bottom Wing357, and in a similar fashion and means as described above for the Top Wing337, including various methods as described above.

In another embodiment, changing the order of the data information that is generated first, i.e. Right Wing347& the Left Wing367, and then data information for the Top Wing337& the Bottom Wing357would result in a change of the number of pixels being processed in each of the steps identified above for each one of the Right Wing347, the Left Wing367, the Top Wing337, and the Bottom Wing357but does not change the underlying inventive concepts as described above and this flexibility would be appreciated by those skilled in the art. As will be described and shown in the following paragraphs, the definition of the quadrilateral digital image305will be used in the processing of an arbitrary digital image, which is split into multiple quadrangle regions, D1, D2, D3, . . . , Dz. The margin pixels are then either determined or created, as described above, for each of the multiple quadrangle regions, Dz. Sometimes these margin pixels are part of the arbitrary digital image and sometimes the margin pixels are generated based on any one, or any combination, of methods as described above. A new quadrilateral digital image, Qz, is then created from the concatenation of each of the multiple quadrangle regions, Dz, and its own margin pixels.

Now referring toFIG. 3B, an exemplary digital image300comprising a quadrilateral digital image305and a quadrangle digital image380, as described in the above. A D1Width312and D1Height322define the quadrangle digital image380. Accordingly, Q1Width314and Q1Height324define the quadrilateral digital image305and are determined in accordance with Eq. 1 and Eq. 2 listed above. In accordance with one embodiment, the quadrilateral digital image305is within any one of a Topmost edge330, a Rightmost edge340, a Bottommost edge350, and a Leftmost edge360of the digital image300, as shown inFIG. 3B. In accordance with another embodiment, the quadrilateral digital image305is located at the top-left corner of the digital image300, as shown inFIG. 3C. In accordance with yet another embodiment, the quadrilateral digital image305is located at the bottom-right corner of the digital image300, as shown inFIG. 3D. Therefore, the location of the quadrangle digital image380within the digital image and the depth of each of the Top margin335, the Right margin345, the Bottom margin355, and the Left margin365will determine the location of the margin pixels and thus the pixels' data information is determined using various methods as described above. In accordance with one embodiment, if the margin pixels are located within anyone of the Topmost edge330, the Rightmost edge340, the Bottommost edge350, and the Leftmost edge360of the digital image300then the data information is duplicated from the correspondent pixels of digital image300. In accordance with another embodiment, if the margin pixels are located beyond anyone of the Topmost edge330, the Rightmost edge340, the Bottommost edge350, and the Leftmost edge360of the digital image300then the data information is generated or created using various methods as described above. Please note that an effort is made to keep the nomenclature ofFIG. 3AthroughFIG. 3Dconsistent, with the exception of the location of the quadrilateral digital image305within the digital image300, seeFIG. 3BthroughFIG. 3D. Some objects names were left off some ofFIGS. 3A-Dfor increasing the drawing clarity, it is clear thatFIG. 3AthroughFIG. 3Dare used to show exemplary locations of quadrilateral digital image305for illustrative purposes.

Therefore, data information is generated for certain margin pixels that are determined to be beyond the Topmost edge330and the Leftmost edge360, seeFIG. 3C. The remaining margin pixels that are determined to be within the Rightmost edge340and the Bottommost edge350, would comprise data information from the correspondent pixels of the digital image300. In accordance with one embodiment, data information is generated for at least one pixel of the quadrilateral digital image305that is above the Topmost edge330of the digital image300if the Top edge332of the quadrangle digital image380is collinear with the Topmost edge330of the digital image300. Similarly, data information is generated for at least one pixel of the quadrilateral digital image305that is to the left of the Leftmost edge360of the digital image300if the Left edge362of the quadrangle digital image380is collinear with the Leftmost edge360of the digital image300. Various methods and steps may be used, as described above. However, the data information for each margin pixel may be generated based on at least one of the following: (i) using data information of at least one pixel that is located on the Top edge332of the quadrangle digital image380, (ii) using data information of at least one pixel that is located to the left of the Top edge332of the quadrangle digital image380(seeFIG. 3B), (iii) using data information of at least one pixel that is located to the right of the Top edge332of the quadrangle digital image380, (iv) using data information of at least one pixel that is located anywhere on the Topmost edge330of the digital image300, and (v) using data information that corresponds to any color, including black.

Now referring toFIG. 3D, data information is generated for certain margin pixels that are determined to be beyond the Bottommost edge350and the Rightmost edge340. The remaining margin pixels that are determined to be within the Leftmost edge360and the Topmost edge330, would comprise data information from the correspondent pixels of the digital image300. In accordance with one embodiment, data information is generated for at least one pixel of the quadrilateral digital image305that is below the Bottommost edge350of the digital image300if the Bottom edge352of the quadrangle digital image380is collinear with the Bottommost edge350of the digital image300. Similarly, data information is generated for at least one pixel of the quadrilateral digital image305that is to the right of the Rightmost edge340of the digital image300if the Right edge342of the quadrangle digital image380is collinear with the Rightmost edge340of the digital image300. Various methods and steps may be used, as has been described above. However, the data information for each margin pixel may be generated based on at least one of the following: (i) using data information of at least one pixel that is located on the Bottom edge352of the quadrangle digital image380, (ii) using data information of at least one pixel that is located to the left of the Bottom edge352of the quadrangle digital image380, (iii) using data information of at least one pixel that is located to the right of the Bottom edge352of the quadrangle digital image380(seeFIG. 3B), (iv) using data information of at least one pixel that is located anywhere on the Bottommost edge350of the digital image300, and (v) using data information that corresponds to any color, including black.

An electronic display panel, may be referred to as monitor, are used in an ever increasing number of applications that generates very high resolution digital images or demands the ability to display multiple high resolution images. One such exemplary monitor is shown inFIG. 4A, where the monitor device400screen (or panel) is split into four Stripes, namely Stripe410, Stripe420, Stripe430, and Stripe440that corresponds to the actual screen region define by the panel Region0, Region1, Region2, and Region3respectively. Every one of Region0, Region1, Region2, and Region3corresponds to a high definition, HD, picture resolution, namely 1920×1080. The splitting of the monitor device400screen into four HD regions would overcome many of the challenges associated with the production of a monitor with a single region having a resolution of 3840×2160, and would be at a lower cost and more power efficient. Such monitors are currently available and may be referred to as Quad-HD monitor. The splitting of the screen into multiple regions does present several challenges. For example, when using an HD resolution digital image, it can be displayed well within any one of the four regions of the monitor device400, namely Region0, Region1, Region2, and Region3. However, the resultant displayed image will suffer from artifacts at the boundaries of the four regions where the resultant pixels of each region may not be properly or timely placed or aligned with the pixels of the adjacent region.

An exemplary process of displaying an Image510using a Scaled image515and a quad display Monitor595will be described as shownFIG. 5. First, the Image510is scaled up to a resolution that correspond to the resolution of the Monitor595. The Scaled image515is split into four quadrangle scaled images, namely Scaled image520, Scaled image530, Scaled image540, and Scaled image550. Each of the four quadrangle scaled images having a resolution that correspond to the resolution of a correspondent region of Monitor595, namely Monitor560, Monitor570, Monitor580, Monitor590, such that Quad0of the Scaled image520is displayed using the display region defined by Quad0of Monitor560. Other quadrants of the Scaled image515are then respectively displayed using the appropriate quadrant of the display Monitor595. Accordingly the consequential display of the individual four quadrant of Monitor595should reproduce the original Image510using the full resolution of Monitor595. However, annoying visual artifacts resulting from the improper alignment of the displayed pixels located at a common vertical Monitor boundary562and/or a horizontal Monitor boundary564can be easily viewed especially during video playback of fast moving objects across the four quadrants of the display Monitor595. The inventive concepts developed by Marseille Networks and described above will be used and described in the following paragraph to faithfully reproduce the Image510using Monitor595with multiple defined regions.

Referring toFIG. 6A, the process of displaying an Image610using Monitor695having four quadrant, namely Monitor660, Monitor670, Monitor680, Monitor690is described in accordance with one embodiment. An Image611is a processed version of Image610. The Image611is split into four regions, namely Split image620, Split image630, Split image640, and Split image650, that corresponds to and in proportion to the number of regions of the Monitor695, namely Monitor660, Monitor670, Monitor680, Monitor690respectively. Each one of the Split image620, Split image630, Split image640, and Split image650is individually processed and scaled up to the resolution required by the correspondent region of the Monitor695. In another embodiment, if the Image610is already at the full resolution of Monitor695, then there may not be a need for any processing to produce Image611, and the Image611may be same as Image610. The processing of each of the Split image620, Split image630, Split image640, and Split image650may not include scaling since each of the individual regions of the Image611is already at the full resolution of the correspondent region of the Monitor695.

Now referring toFIG. 6B, and using a Split Image620, corresponding to Quad0, as an exemplary region of the Image611for processing. Exemplary pixels, for illustrative purposes, are arranged in two-dimensional grid format over the entire region, Quad0, and a Top-leftmost pixel621is shown at the top left corner of the Split image620. The inventive concepts described above are applied to the Split image620, which corresponds to a quadrangle digital image to be processed. Since the region, Quad0, is at the top-left quadrant of the Image611, then a Right margin624and a Bottom margin625are generated from existing pixels that are part of Split image630, Split image640, and Split image650, as shown inFIG. 6B. Furthermore, since the region, Quad0, is at the top-left quadrant of the Image611, then top edge of Split image620is collinear with the topmost edge of the Image611. Similarly, the left edge of Split image620is collinear with the leftmost edge of the Image611. Therefore, a Top margin623and a Left margin626are created using any one, or a combination of various methods as described above. In order to keep the clarity of the drawings as shown inFIGS. 6A through 6Csome objects have not been named but the intended meaning should be very clear fromFIGS. 6A-6Cand while referencing back to the detailed drawings ofFIG. 3AthroughFIG. 3D.

A Digital image710having a topmost edge, a bottommost edge, a leftmost edge, and a rightmost edge is split into M rows and N columns, and thus defining an M×N array of quadrangle digital images, each of which is identified as D(m,n), as shown inFIG. 7A. The index m represent any one integer of a first range of consecutive integers, wherein the first range corresponds to the number of rows M, and a column index, n, that is any one integer of a second range of consecutive integers, wherein the second range corresponds to the number of columns N. In accordance with one embodiment, every element of the M×N array correspond to a region comprising a quadrangle digital image, and the inventive concepts as described above are applied to each region individually. In accordance with another embodiment, multiple of the elements of the M×N array may be combined to form a single quadrangle digital image and thus can be processed accordingly.

Margin pixels are determined for an exemplary D(1,2), D(m,n)and D(M,N)as shown inFIG. 7B, for illustrative purposes. A Top margin751, a Bottom margin753, a Left margin754, and a Right margin752. A new quadrilateral digital images, Q(m,n), is generated comprising the D(m,n)portion of the digital image, as defined by the array element that corresponds to the quadrangle digital image D(m,n), and a second portion of the digital image, defined by the Top margin751, the Bottom margin753, the Left margin754, and the Right margin752. Each new quadrilateral digital images is larger than the corresponding D(m,n)and in accordance with the following relationships:
Q(m,n)width=Left margin+D(m,n)width+Right margin,  Eq. 3
Q(m,n)height=Top margin+D(m,n)height+Bottom margin,  Eq. 4

Each of the quadrangle digital images D(m,n)is centered within the quadrilateral digital image Q(m,n)using the Top margin751, the Bottom margin753, the Left margin754, and the Right margin752. In addition, at least a first pixel of the quadrilateral digital image Q(m,n)is determined to be located beyond any one of the topmost edge, the bottommost edge, the leftmost edge, and the rightmost edge of the Digital image700if any one of a D(m,n)top edge, a D(m,n)bottom edge, a D(m,n)left edge, and a D(m,n)right edge of a quadrangle digital image D(m,n), is collinear with any one of the topmost edge, the bottommost edge, the leftmost edge, and the rightmost edge of the Digital image700. Appropriate data information is generated for the first pixel based on at least one of the following steps: (i) using data information of at least one pixel that is located on any one of the D(m,n)top edge, the D(m,n)bottom edge, the D(m,n)left edge, and the D(m,n)right edge of the correspondent quadrangle digital image D(m,n), (ii) using data information of at least one pixel that is located on any one of the topmost edge, the bottommost edge, the leftmost edge, and the rightmost edge of the Digital image700, and (iii) using data information that corresponds to any color, including black.

In a similar fashion, data information for all margin pixels is determined first by checking if the margin pixels are within the Digital image700or are beyond any one of the topmost edge, the bottommost edge, the leftmost edge, and the rightmost edge of the Digital image700. Various method of generating and/or creating data information for margin pixels have been described in details in this disclosure and used here for every quadrilateral digital image Q(m,n). In accordance with another embodiment, it should be noted that the general solution described above for splitting any Digital image700into an array of M×N array of quadrangle digital images is not limited to two-dimensional arrangement of all elements of the array. For example, multi-dimensional arrangement of (M×N×Z) array of quadrangle digital images would benefit greatly and the inventive concepts here are easily applied to each element of the multi-dimensional arrangement of array that corresponds to a quadrangle digital image.

A block diagram of a Digital Image Processing System800is shown inFIG. 8Aand is briefly described. Digital images can be formed, transmitted, stored, or displayed using a video format standard that specifies how video data information for each pixel is generated. Currently, many video format standards are used around the world. Various types of image capturing systems can capture video data information of digital images in accordance with at least one video format standard, and is able to transfer the video data information of the digital images by using corresponding signals over a wired or wireless connection. The Digital Input Data Path811comprises multiple conductors to transfer video data information signals of a digital image to an Input Module810. An example of a digital image comprising two hundred forty pixels organized in twelve lines and each line comprising twenty pixels is shown inFIG. 1as Digital Image100. The Input Module810captures and processes the video data information of the digital image, and initiates memory write transaction to store the processed video data information of the digital image into a Memory850using a Memory Data Path Controller830via a First Memory Data Path831and a Second Memory Data Path832. A Register and Control Module820comprises programmable registers to store operational data information for the processing of the captured video data information of the digital image throughout the Digital Image Processing System800. The Register and Control Module820further comprises logic circuitry needed to respond to and communicate with various modules and components of the Digital Image Processing System800via a First Control Data Path821. In addition, the Register and Control Module820is coupled to a Second Control Data Path822providing a user interface to gain access to, communicate with, respond to, and control various functions of the Digital Image Processing System800. The Memory Data Path Controller830communicates with the Input Module810and an Output Module840via the First Memory Data Path831. The Memory Data Path Controller830communicates exclusively with the Memory850via the Second Memory Data Path832. Furthermore, the Memory Data Path Controller830is coupled to the Register and Control Module820via the First Control Data Path821. The Output Module840retrieves video data information from the Memory850using the Memory Data Path Controller830and via the First and Second Memory Data Path,831and832respectively. Furthermore, the Output Module840processes the retrieved video data information, and outputs a processed version of the digital image onto the Output Display Data Path846. The Output Module840is capable of driving high definition electronic display systems comprising multiple regions, where each region displays a portion of the overall digital image to be displayed. The Output Module840comprises output display modules ODM_1, ODM_2, ODM_3, ODM_4, through ODM_k, where “k” corresponds to the total number of regions and is equivalent to “m” rows multiplied by “n” columns, relative to how the electronic display is divided into “m” rows and “n” columns, e.g. as shown inFIG. 7B. Detailed description of various parts, components, modules and the operation of the Digital Image Processing System800will be provided in the following paragraphs.

The Memory Data Path Controller830handles as many memory access requests as needed for all the output display modules ODM_1through ODM_k, which are part of the Output Module840, so that the video data information of the Digital Image900is processed as desired. The access efficiency to and from Memory850has a large impact on the scalability of the Digital Image Processing System800, and the overall video data information processing throughput. Various modes or types of memory access are used and the Memory Data Path Controller830provides the ability to handle different types of back-to-back memory access requests. The design and performance of the Second Memory Data Path832and the First Memory Data Path831contribute as well to the overall performance and efficiency desired. The component, modules and functional description of the Digital Image Processing System800, as shown inFIG. 8A, is meant as an exemplary guide of how video data information of a digital image is captured from a Digital Input Data Path811, processed, and outputted to multiple regions of an electronic display system using the Output Display Data Path846. Various alternate embodiments are discussed in various levels of details in the following paragraphs as to further show the flexibility of the Digital Image Processing System800architecture and should not be considered as a limitation of the embodiments. It is important to note that the Digital Image Processing System800comprises many other blocks, sub-systems, control signals, Clock modules, signal interface circuitry, PLL etc. . . . , which are not shown inFIG. 8Ain order to maintain clear drawings.

The Input Module810comprises three main components, an Input Capture810_10coupled to the Digital Input Data Path811and a Video Formatter810_20, and a Memory Interface810_30coupled to the First Memory Data Path831and the Video Formatter810_20, as shown in the block diagram ofFIG. 8B. The Input Capture810_10comprises logic circuitry to receive video data information, of an input digital image, via the Digital Input Data Path811, in accordance with a video format standard. Depending on the design requirement, the Digital Image Processing System800may accommodate many different video formats. An exemplary video format of the video data information of the input digital image is shown below:

In addition, the video format standard specifies display control information such as Vertical and Horizontal synchronization, Vsync and Hsync, information that corresponds to and provides information regarding how the pixels of the input digital image are arranged in accordance with the resolution and the video format standard of the input digital image. A pixel data enable signal, which may be triggered from the Vsync signal, may be added to indicate the presence of valid lines (or rows) of pixels to be captured or displayed. Alternatively, a pixel data enable signal, which may be triggered from the Hsync signal, may be used to indicate the presence of valid pixels, within a line (or rows) of pixels, to be captured or displayed. Thus, the ability to control the blanking, or the display, of a portion of the input digital image is enhanced by using appropriate data enable signals. Furthermore, the Digital Input Data Path811comprises at least one channel to transfer video data information signals to be received by the Input Capture810_10from a digital image source. The channel may comprise one or multiple conductors to carry the video data information signal in accordance with various desired signaling schemes, e.g. Low Voltage Differential Signaling or LVDS. In certain application, some digital image sources may require multiple channels to carry the video data information of the digital image; this is especially true whenever the digital image resolution is large enough such that the available channel bandwidth is not large enough to enable the transfer of the required video data information. In a preferred embodiment, the Digital Input Data Path811comprises four input channels, where each channel comprises five differential pairs of conductor and can operate at a variable frequency rate in accordance with the video format standard of the input video data information stream, e.g. 24-bit RGB 4:4:4 operating at a frequency of 74.25 MHz. In accordance with another embodiment, the output of multiple digital image sources may be coupled to the Digital Input Data Path811, where at least one channel may be used to transfer their video data information to one or multiple instances of the Input Capture810_10module, as will be described and discussed later on in this disclosure.

The Input Module810further comprises logic circuitry to receive or generate a first clock that is associated with the video data information. The Input Capture810_10, Video Formatter810_20and Memory Interface810_30may use this first clock for their operation. Multiples clocks may be generated from, or in addition to, the first clock as may be required. For example, the first clock may be inputted to a Phase Locked-Loop (PLL) or other types of circuitry to maintain and distribute clocks to other components of the Digital Image Processing System800. An output video display clock may also be derived from or linked to the first clock, thus providing the ability for the output display to be locked to the input video data information stream. As it has been mentioned earlier, various blocks or components may not be shown or discussed since their details is not necessary for a person of ordinary skills in the art to understand and practice the invention. Furthermore, the Digital Image Processing System800may comprise a central processing unit CPU and its associated components, e.g. software, firmware and hardware, where some of the Digital Image Processing System800operations may be executed, managed, defined, substituted for one or more modules, configured or programmed to produce the desired system functions.

In accordance with one embodiment, the Video Formatter810_20receives a first digital image that is captured by the Input Capture810_10using a first video format, e.g. RGB 4:4:4, having twenty-four bits for every pixel of the digital image. The Video Formatter810_20generates at least a second and third digital image, based on a second video format e.g. YUV 4:2:2, using the first digital image received. The second digital image comprises the luminance video data information (Y) of the digital image, while the third digital image comprises the chrominance video data information (UV) of the first digital image. The Memory Interface810_30generates at least one first memory write command to transfer the video data information of the second digital image to the Memory Data Path Controller830via the First Memory Data Path831. The total number of memory write command required to transfer the video data information of the second digital image depends on the architecture of Digital Image Processing System800. Various techniques may be used where one or multiple memory write commands may be used to effect the complete transfer of the video data information from the Input Module810to the Memory850. An exemplary transfer of video data information to the Memory850is described in the following paragraphs.

The Memory Data Path Controller830receives the first memory write command via the First Memory Data Path831and generates at least one first memory device write command to effect a transfer of the video data information of the second digital image to the Memory850via the Second Memory Data Path832. The first memory write command comprises a first base index that is used by the Memory Data Path Controller830to generate a first base address that indicates a starting address of a first region within the Memory850, where the video data information of the second digital image is to be stored. The Memory Data Path Controller830embeds the first base address within the first memory device write command. Furthermore, the Memory850comprises control circuitry to receive the first memory device write command, and further comprises receive circuitry to receive the second video data information via the Second Memory Data Path832. The Memory850writes the second video data information into the first region of the Memory850starting from the memory location as indicated by the first base address. Additional data information, which may be embedded in the memory device write or read commands, may be used to further specify an offset address for the starting memory location or how many memory locations are to be used for storing the video data information, as will be described the paragraphs below.

The Memory Interface810_30generates at least one second memory write command to transfer the video data information of the third digital image to the Memory Data Path Controller830via the First Memory Data Path831. The Memory Data Path Controller830receives the second memory write command via the First Memory Data Path831and generates at least one second memory device write command to effect a transfer of the video data information of the third digital image to the Memory850via the Second Memory Data Path832. The second memory write command comprises a second base index that is used by the Memory Data Path Controller830to generate a second base address, that indicates a starting address of a second region within the Memory850, where the video data information of the third digital image is to be stored. The Memory Data Path Controller830embeds the second base address within the second memory device write command. Furthermore, the Memory850comprises control circuitry to receive the second memory device write command, and further comprises receive circuitry to receive the third video data information via the Second Memory Data Path832. The Memory850writes the third video data information into the second region of the Memory850starting from the memory location as indicated by the second base address.

Now referring toFIG. 8C, the Memory Data Path Controller830comprises a First Memory Interface830_10to receive the second video data information from the First Memory Data Path831, in response to at least one first memory write command. The Memory Data Path Controller830further comprises Control830_20logic circuitry to manage, aggregate and/or control the video data information flow and generate the necessary information to initiate a memory device write transaction using the information embedded in the memory write command. The Control830_20manages and provides the appropriate buffering for at least a portion of the second video data information being received while waiting to complete the memory device write transaction. The Second Memory Interface830_30generates at least one first memory device write command, using the information extracted or generated in response to the memory write command, and starts to send the received second video data information to the Memory850via the Second Memory Data Path832. The second video data information is stored in the first region of Memory850using the embedded first base address of the starting memory location, as described above. The third video data information is transferred in a similar fashion from the Input Module810to the second region of the Memory850, in response to at least one second memory write command and at least one second memory device write command. Furthermore, the Memory Data Path Controller830provides management and control of data information flow to and from the Memory850via the Second Memory Data Path832in response to other modules requests for memory access. For example, the Memory Data Path Controller830provides management and control of data information flow to and from the Input Module810and Output Module840, via the First Memory Data Path831, such that the Digital Image Processing System800is able to handle multiple, back-to-back, or simultaneous memory access requests to and from Memory850. Furthermore, the Memory Data Path Controller830has the mechanisms to handle synchronous and asynchronous conditions, and has the capability to interface and control data information flow to and from various components of the Digital Image Processing System800as may be necessary, where each component may be using different clock domains.

The Register and Control Module820provides the necessary access and operational settings to various programmable components, e.g. registers, within the Digital Image Processing System800via the First Control Data Path821. In addition, the Second Control Data Path822provides the necessary interface, e.g. I2C, for an external device to access and set various programmable registers of various components and modules of the Digital Image Processing System800via the First Control Data Path821. The Register and Control Module820performs all bus protocols to read and write internal registers, with both round-robin arbitration and a full acknowledge handshake to enable cross-clock-domain operation. Furthermore, the Digital Image Processing System800may comprise a Read Only Memory (ROM) that contains the default configuration that the Register and Control Module820uses to program various modules on power-up. Hence, relieving an external device from using the Second Control Data Path822to program the Digital Image Processing System800registers to a default power-up state. The Register and Control Module820can service multiple clients within the Digital Image Processing System800via the First Control Data Path821and at least one external client via the Second Control Data Path822. In the following paragraphs, an exemplary write and read transactions through the Register and Control Module820are briefly described.

A source module set a request for a write command for a specific register of a specific module. The address of the specific register and the address of the specific module are embedded within the write command. The source module can be any one of the Digital Image Processing System800internal modules, where the write command is sent via the First Control Data Path821, or an external module, where the write command is sent via the Second Control Data Path822. The destination module can be any one of the Digital Image Processing System800internal modules. The Register and Control Module820detects the write command and in turn places the write address for that request on a register address bus portion of the First Control Data Path821, and places the write data on a register write data bus portion of the First Control Data Path821. The Register and Control Module820then activates the decoded write strobe for the destination module. Clock synchronization may be implemented to insure the destination module will receive proper write strobe, e.g. dual-rank synchronization of the write strobe. In response to the write strobe, the destination module samples the data, registers address, and writes the data to the appropriate internal register location within the destination module as indicated by the register address. At that time, the destination module may send an acknowledge signal to the Register and Control Module820. The destination module may hold the acknowledge signal true until it detects the release of the write strobe from the Register and Control Module820. The Register and Control Module820may further dual-rank synchronizes the returning acknowledge signal before using it to decide to release the write strobe. Once the write strobe is released, the Register and Control Module820is able to perform another read or write transaction. In an alternate embodiment, the write strobe may be used to designate a write cycle to multiple registers at the same time. The write command specifies a broadcast type of command indicating a range of registers to be written at the same time with the same data. In yet another embodiment, the write strobe may be used to designate a write cycle to multiple registers that are located in different modules at the same time. The write command specifies a broadcast type of command indicating the address of one or multiple registers to be written. All the destination modules that receives the broadcast type write command, initiate a write cycle to their register as identified by the register address within the command cycle. This can produce an efficient and fast way to reconfigure Digital Image Processing System800, e.g. when image size changes or when a change in video format standard is detected or required. An exemplary register read request is described in the next paragraph.

A source module set a request for a read command of a specific register within a specific module. The address of the specific register and the address of the specific module are embedded within the read command. The source module can be any one of the Digital Image Processing System800internal modules, where the read command is sent via the First Control Data Path821, or an external module, where the read command is sent via the Second Control Data Path822. The destination module can be any one of the Digital Image Processing System800internal modules. The Register and Control Module820detects the read command and in turn places the read address for that request on the register address bus portion of the First Control Data Path821. The Register and Control Module820then activates the decoded read strobe for the destination module. Read strobe synchronization is achieved in a similar fashion to the write strobe synchronization, as described above, e.g. dual-rank synchronization of the read strobe. The destination module places the read data on a read data bus portion of the First Control Data Path821. At that time, the destination module may asserts an acknowledge signal and send it to the Register and Control Module820. The destination module will hold the acknowledge signal true until it detects the read strobe from the Register and Control Module820going false. The Register and Control Module820may dual-rank synchronizes the returning acknowledge signal before making the decision to release the read strobe. Once the read strobe is released, the Register and Control Module820is able to perform another read or write transaction. It is important to note that the First and Second Control Data Path821and822may use various types of handshake control. A dedicated portion of the First and Second Data Path821and822may be used exclusively for any of the address, data, and control signals or may be used in a multiplexed fashion depending on the desired design and system performance criteria. An alternate embodiment of Register and Control Module820includes a dedicated point-to-point read data bus and a dedicated party-line write data bus that are implemented between the Register and Control Module820and the Digital Image Processing System800modules via the First and Second Control Data Path821and822. The following paragraphs describe the operation of the Output Module840.

An exemplary electronic display panel may comprise many regions and each of which is independently driven. Therefore as many output display modules (ODM) as display regions are required, where each ODM retrieves, processes, and outputs onto the Output Display Data Path846the processed video data information for its designated display region. In accordance with one embodiment, the architecture of the Digital Image Processing System800is developed with the ability to drive a large display panel that comprises sixteen display regions. In order to provide such a flexible system architecture to be used with various types of electronic display panels, a unique and programmable design features are implemented within each ODM. One of the ODM design features is that each ODM comprises identical programmable circuitry, where each ODM can be programmed, e.g. enumerated using sequential numbers 0, 1, 2 . . . , such that only one of the ODMs will behave as a Master ODM and all of the others will behave like Slave ODMs. One of the functions of the Master ODM is to control and insure that the starting point of the Vertical and Horizontal sync signals is the same for all of the ODMs. In addition, the master ODM further controls and intervenes in the multiplexing of the data being read from specific registers within each of the Slave ODMs through the First Control Data Path821. Any of the ODMs comprises the circuitry to operate as a Master ODM if it is programmed as such. Therefore, the ability to scale the Digital Image Processing System800to drive large number of display regions with as many numbers of ODMs is greatly enhanced by the simple functional ability to enumerate each ODM and program its functionality. Some additional advantages are gained when scaling the Digital Image Processing System800such as: (i) a reduction of the amount of time required to test the Output Module840and to verify the functionality of each ODM, and (ii) correct routing of each ODM within the overall Digital Image Processing System800.

The Output Module840, as shown inFIG. 8A, comprises multiple independent output display modules, namely ODM_1841, ODM_2842, ODM_3843, ODM_4844, and ODM_k845. Each of the ODMs is capable of accessing and independently retrieving, from Memory850, video data information of a digital image having a known starting memory location and a first width and height. The digital image may constitute a portion, or the entirety, of the input digital image as captured by the Input Module810. Each of the ODMs outputs onto the Output Display Data Path846a processed digital image that corresponds to the retrieved digital image from Memory850. For example, a Quad HD electronic display panel, Monitor695as shown inFIG. 6A, comprises four identical display regions each with a predefined resolution and a second width and height. In one embodiment, any of the display regions may be specified using a different resolution and a different width and height for each region. Therefore, each output display module, e.g. ODM_1, can be programmed, independently from other ODMs, to process the retrieved digital image and to display it exclusively in accordance with the requirement of the display region that the output display module is assigned to drive, e.g. resolution, width and height, video format, or mixing other digital image input. Normally, the display region width and height have larger dimensions as defined by the second width and height, than the retrieved digital image from Memory850as defined by the first width and height. Usually, the horizontal scaling ratio of the second width divided by the first width is equal to the vertical scaling ratio of the second height divided by the first height such that the aspect ratio of the digital image is kept constant.

A horizontal or vertical scaling ratio of one indicates that the output resolution in the specified dimension, i.e. horizontal or vertical, is the same as the input resolution and no scaling takes place. However, each of the ODM_1841, ODM_2842, ODM_3843, ODM_4844, and ODM_k845comprises programmable circuitry capable of processing and scaling the retrieved digital image using an arbitrary horizontal scaling ratio and an arbitrary vertical scaling ratio, that do not necessarily need to be equal. This is especially beneficial in processing digital images using various video format standards that may specify different vertical and horizontal resolutions. Thus, different vertical and horizontal scaling ratios are used in order to properly process and display the digital image using the specified display region resolution. This is illustrated in the following example. A first digital image with a resolution of 720×480 is to be displayed using the display region, Monitor660as shown inFIG. 6A, having a resolution of 1440×960. Thus, both the horizontal and vertical scaling ratios equal to two, and the processing of the digital image includes same scaling in the horizontal and vertical directions. Similarly, if a second image having a resolution of 360×480 and it is to be displayed using the full display region, Monitor660, then it becomes apparent that the horizontal scaling ratio is equal to four (1440 divided by 360), and the vertical scaling ratio is equal to two (960 divided by 480). Therefore, the processing of the second digital image includes different scaling in the horizontal and vertical directions and the processed second digital image is displayed using the full display region resolution of 1440×960. Furthermore, the output display modules can be programmed to process and scale digital images using non-integer vertical and horizontal scaling ratios, e.g. a horizontal scaling ratio of 2.5 may be used while a vertical scaling ration of 1.5 may be used.

Various types of electronic display monitors with multiple defined regions may be coupled to the Output Display Data Path846to receive and to display the processed video data information of the digital images processed by each of the output display modules. Furthermore, an electronic display monitor may comprise an arbitrary number of display regions as may be specified by M rows and N columns e.g. seeFIGS. 7A,7B andFIG. 9A, where the total number of regions can be represented by M rows times N columns. Hence, the Output Module840would comprise ODM_1through ODM_k output display modules, where k=M×N. The ODM_k represents the kthoutput display module that outputs, onto the Output Display Data Path846, a kthprocessed digital image to be displayed via the kthregion of the electronic display panel. The Output Display Data Path846may comprise a single dedicated channel for each of the display regions of the electronic display panel. Alternatively, a common channel may be used where processed video data information is tagged with the destination address of any one of the regions of the electronic display monitor. A Quad HD display panel is an exemplary electronic display panel with M=2 and N=2 and is used in the following paragraphs to describe in further details the operation of the Output Module840, seeFIG. 6AandFIG. 8A.

In accordance with one embodiment, the Output Display Data Path846comprises four independent channels. Each channel is used to couple one of the output display modules, namely ODM_1841, ODM_2842, ODM_3843, and ODM_4844, to one of the regions of the electronic display panel Monitor695, namely Monitor660, Monitor670, Monitor680, and Monitor690. Each of the ODM_1841, ODM_2842, ODM_3843, and ODM_4844comprises identical circuitry and independently retrieves and processes a designated portion of the Image610, namely the Split620, Split630, Split640, and Split650respectively, as described above and inFIG. 6A. The output display module ODM_1841processes and outputs, onto its dedicated channel of the Output Display Data Path846, the video data information of the processed portion of the Split Image620. The Monitor660receives and displays the video data information of the processed portion of the Split Image620via the Output Display Data Path846. Similarly, each of the ODM_2842, ODM_3843, and ODM_4844retrieves and processes the Split630, Split640, and Split650respectively. Furthermore, each of the ODM_2842, ODM_3843, and ODM_4844then outputs, onto its dedicated channel of the Output Display Data Path846, the video data information of the processed Split Image630, Split640, and Split650, respectively. The Monitor670, Monitor680, and Monitor690receive and display the video data information of the processed Split Image630, Split640, and Split650respectively. The overall image displayed on Monitor695corresponds to the original Image610.

The Input Module810, in accordance with one embodiment, is shown inFIG. 8D. The architecture of Input Module810comprises “k” instances of the Input Module810as shown inFIG. 8B. Input capture modules, namely Input Capture_1830_11, Input Capture_2830_12, Input Capture_3830_13, Input Capture_4830_14, and Input Capture_k830_15(to be referred to as ICMs) are used to capture video data information of transferred digital images via the Digital Input Data Path811. A single or multiple digital images sources may be used to output their respective digital images onto the Digital Input Data Path811, which may comprise a dedicated channel for each source or a common channel for all sources. Whatever technique is used it must be able to sustain the amount of video data information to be transferred as may be desired or specified by the Digital Image Processing System800. The architecture of the Input Module810shown inFIG. 8Dprovides the ability to (i) increase the input capture bandwidth, (ii) receive multiple digital images from multiple sources via the Digital Input Data Path811, (iii) split a captured digital image into multiple regions, and (iv) accommodate the simultaneous capturing and processing of digital images having different video format. The captured video data information is processed using Video Formatter_1830_21, Video Formatter_2830_22, Video Formatter_3830_23, Video Formatter_4830_24, and Video Formatter_k830_25. Each of the video formatter modules comprises circuitry to receive video data information from their correspondent ICM, i.e. the Input Capture_1830_11, Input Capture_2830_12, Input Capture_3830_13, Input Capture_4830_14, and Input Capture_k830_15respectively. Each of the video formatter modules functions in a similar fashion to the Video Formatter810_20shown inFIG. 8Band described above. The continuous increase in demands for higher resolution digital images provide the needs to have a flexible architecture for the Digital Image Processing System800to meet such demands, and any new additional requirements as it may become necessary, e.g. a different or a newly developed video format standards. In accordance with one embodiment, each of the ICMs is used to capture a predetermined portion of an input digital image, where each portion is then processed and stored in Memory850using the corresponding memory interface module. The memory interface modules, Memory Interface_1830_31, Memory Interface_2830_32, Memory Interface_3830_33, Memory Interface_4830_34, and Memory Interface_k830_35, function in a similar fashion to the Memory Interface810_30module shown inFIG. 8Band described above. The following paragraphs provide a description of the operation of the Memory Data Path Controller830.

The Memory Data Path Controller830, the First Memory Data Path831, and the Second Memory Data Path832design requirement is to efficiently transfer large amounts of data between the various modules of Digital Image Processing System800, e.g. between the Input Module810and the Output Module840, and the Memory850. Control and video data information are pipelined together and thus pipeline stages can be added to achieve timing closure especially when the Digital Image Processing System800is being manufactured as a System-on-Chip or SoC. In this case, large amount of data must be transferred relatively long distances throughout the SoC. Arbitrary numbers of pipeline stages between the Memory Data Path Controller830and Digital Image Processing System800modules can be added without affecting the performance. The Memory Data Path Controller830is designed to accommodate and respond to different modes of operation for each of the internal modules of Digital Image Processing System800, and thus enabling efficient and high performance access to and from the Memory850using both the First and Second Memory Data Path831and832respectively. Each module can store or retrieve data from the Memory850in the most efficient format for its data processing or type usage, thus further enabling the ability to scale the Digital Image Processing System800to meet the demands for a higher input bandwidth, e.g. higher resolution or number of input sources, and larger number of output display regions. For example, a digital image representing a two-dimensional graphics may be digitized and use a linear memory addressing for transferring its video data information in and out of Memory850, while compressed digital images, e.g. MPEG, may utilize a specific block memory addressing. The Memory Data Path Controller830is designed and capable of operating with at least five exemplary different modes (i) progressive scan macro block xy mode, (ii) interlaced scan macro block xy mode, (iii) progressive scan linear xy mode, (iv) interlaced scan linear xy mode, and (v) sequential access mode. Furthermore, the architecture of the Memory Data Path Controller830includes a specialized memory organization design that allocates regions of memory locations within the Memory850for the exclusive use with certain types of video data information.

Each of the internal modules of Digital Image Processing System800generates and outputs, onto the First Memory Data Path831, memory write or read commands that comprise an operation mode, a base index, and a digital image's location and size information. The location of the digital image within Memory850may be determined using a starting memory location that corresponds to the location of a first pixel or origin of the digital image, e.g. top-leftmost pixel. Using the first memory location of a memory region as an origin, then an offset number of memory locations from the first memory location may be used as well to indicate the starting memory location of a desired digital image. The digital image's size information is identified with width, height, or the total number of memory locations used within Memory850. The Memory Data Path Controller830operates and responds to different modes that utilize different location and size information as it may be necessary for the efficient transfer of the video data information from and to Memory850, as is described later seeFIGS. 10A and 10B. Consequently, the Memory Data Path Controller830initiates memory device write or read transactions in response to memory write or read commands using the operation mode, base index, and the digital image's location and size information embedded in the memory write or read command. The Memory Data Path Controller830generates memory device write or read commands and completes the Memory850device write or read transactions by sending or receiving video data information, from Memory850via the Second Memory Data Path832. The Memory Data Path Controller830appropriately receives or forwards the video data information to the module that issued the memory write or read command via the First Memory Data Path831. The Digital Image Processing System800internal modules can make successive back-to-back memory write or read requests that include completely different mode of operation, base index, and image size and location. The Memory Data Path Controller830can handle these memory device write or read transactions of entirely different types by appropriately arbitrating between the various modules of the Digital Image Processing System800using the First Memory Data Path831, and the Memory850via the Second Memory Data Path832. The memory sub-system Memory850is described further in the following paragraphs.

The Memory850device may be a single memory device or a memory system comprising multiple memory devices or modules, e.g. Memory851and Memory852as may be desired or necessary by the Digital Image Processing System800. The Memory850is organized into multiple regions, where each region is specified using a starting memory location base address and a predefined number of memory locations. In one preferred embodiment, the Memory850is organized into one hundred twenty eight memory regions. In general, the Input Module810writes the input digital image video data information into one or more memory regions within Memory850. The input Module810is also capable of splitting the input digital image into smaller regions each of which is stored into a separate memory region within Memory850. The Output Module840reads and processes the video data information as specified using location and size information of a desired digital image from one or more regions within Memory850. For example, in accordance with a YUV video format standard, the ODM_1841module reads the Y-component and UV-component of the video data information from a first and second memory region, respectively. The overall storage capacity of Memory850is based on the application and overall processing requirement of video data information of the Digital Image Processing System800. The storage capacity of each region of Memory850is dependent on the resolution, and the type of video data information for a given video format standard being used. Furthermore, various types of memory, e.g. DRAM, SRAM, DDR, etc. . . . , may be used to manufacture Memory850as an integrated component within the Digital Image Processing System800or as a standalone memory system. In general, the Memory850must meet the overall performance and timing requirement of the Input Module810and the Output Module840. The ability to use a particular organization or design of a memory system is influenced by the required overall performance of Memory850, and the engineering requirement to manage the capacity and location of each of the memory regions within Memory850. In accordance with one embodiment, each memory region's capacity and location is programmable and can be redefined for a given application's memory usage requirements. The programming of the appropriate registers with a new memory region's size and location within Memory850, i.e. number of memory words and starting base address, provides a flexible architecture for a scalable and manageable Memory850system. The Memory Data Path Controller830stores the base address for each memory region in a look up table, where each base address is looked up using the base index embedded within the memory write or read command. Thus, using a base index eliminates the need to reprogram the various modules of Digital Image Processing System800with a new set of base addresses, whenever a new organization or reallocation of the memory regions of Memory850has taken place. Different storage and lookup means may be used for the base addresses of memory regions of Memory850e.g. file registers, programmable registers, Random Access Memory (RAM), or Content Addressable Memory (CAM).

An exemplary Digital Image900, with a resolution of 48×32, is split into six regions Region_1911, Region_2912, Region_3913, Region_4914, Region_5915, and Region_6916as shown inFIG. 9A. The Digital Image900comprises thirty-two lines, where each line extends in the horizontal direction and comprises 48 pixels. The words “line” or “row” may be used interchangeably to indicate an array of pixels organized in the horizontal direction, video data information that corresponds to an array of pixels organized in the horizontal direction, or may indicate a horizontal array of memory locations comprising video data information that corresponds to a horizontal array of pixels. Similarly, the words “column” or “Col” are used to describe an array of pixels, video data information, or memory locations but in the vertical direction. Multiple video format standards may be used for the video data information that corresponds to each pixel, e.g. 24 bit RGB or YUV 4:2:2, 16 bits, see above. The exemplary Digital Image900comprises 32 lines and each line comprises 48 pixels, as shown inFIG. 9B, where the first line (or line0) is shown as Row_0900_300, and the thirty-second line is shown as Row_31900_331. Similarly, the first columns of pixels is shown as Col_0900_400, and the forty-eighth column of pixels is shown as Col_48900_448. Furthermore, a first starting pixel Pixel_0900_0000is shown at the top-leftmost corner of the Digital Image900, and is located at the intersection of the vertical position Row_0900_300and the horizontal position Col_0900_400. Similarly the last pixel of the Digital Image900is Pixel_1535900_1535and is shown at the bottom-rightmost corner of the Digital Image900, and is located at the intersection of the vertical position Row_31900_331and the horizontal position Col_48900_448. In this example, each of the six regions of Digital Image900is defined to have identical dimensions of width and height that corresponds to sixteen pixels per side. For example, Region_1911and Region_2912each has a first top-leftmost pixel that is identified in reference the Digital Image900as Pixel_0900_0000and Pixel_16900_0016. Furthermore, the first top-leftmost pixel of Region_1911is identified within Region_1911as Pixel_0911_000. Similarly, the first top-leftmost pixel of Region_2912is identified within Region_2912as Pixel_0912_000. As each region of Digital Image900is independently read or written, it becomes important to have labels for the elements of each region in reference to itself as well as the Digital Image900, seeFIG. 9CthroughFIG. 9P.

Digital Image900has a resolution that corresponds to a total number of 1536 pixels and total number of memory allocation of 36,864 bits (1536 times 24) for a 24 bit RGB or 24,576 bits (1536 times 16) for YUV 4:2:2 video format. In the following examples, certain assumptions are provided as an exemplary mean to describe some of the operation of Digital Image Processing System800. The video format standard of YUV 4:2:2, 16 bits per pixel is used to store the processed video data information of the captured Digital Image900. Hence, video data information for one pixel use 8-bits to store the Y-component and another 8-bits for the UV-component. An exemplary 64-bit-word is allocated to each memory location within a first and second region of Memory850. Hence, the Digital Image900would require 384 memory locations to store all of the video data information in accordance with YUV 4:2:2 16 bits video format, organized as 192 memory locations for each of the Y-component and UV-component of the captured Digital Image900within the first and second region of Memory850respectively. An exemplary first base address of (00001024)10is used to indicate the actual physical address of the first starting memory location, Memory Location0(Row_0, Col_0)900_800as shown inFIG. 9D, of the first region within Memory850where the Y-component of the video data information is to be stored. Similarly, an exemplary second base address of (00004096)10is used to indicate the actual physical address of the first starting memory location of the second region within Memory850where the UV-component of the video data information is to be stored. Input Module810captures and processes the video data information of Digital Image900into a first quadrangle digital image comprising the Y-component and a second quadrangle digital image comprising the UV-component. An expanded view of the Region_1911is shown inFIG. 9C. An exemplary memory organization of Digital Image900is shown inFIG. 9D, where repeated references toFIGS. 9A through 9Pwill be used in the following paragraphs. The first eight pixels of the Region_1911, starting with Pixel_0911_000and ending with Pixel_7911_007, form a first starting Pixel Group0911_500where the Y-component of the video data information is stored into Memory Location0900_800, as shown inFIG. 8CandFIG. 8D.

In accordance with one embodiment, the Input Module810initiates at least one memory transaction request to transfer and store the Y-component of the video data information of Pixel_0900_0000through Pixel_1535900_1535in the first memory region within Memory850. Similarly, Input Module810initiates at least one memory transaction to transfer the UV-Component of the video data information of all the pixels of Region_1911, Region_2912, Region_3913, Region_4914, Region_5915, and Region_6916to be stored in the second memory region within Memory850. In this example, it is possible for the Y-component of video data information for eight pixels to be stored using a single 64-bit word or one memory location, as described above and shown inFIG. 9CandFIG. 8D. Furthermore, a First Memory Block911_800, as illustrated by the region enclosed within dashed lines inFIG. 9D, represents the Y-component of the video data information of all the pixels within Region_1911, i.e. Pixel_0911_000through Pixel_255911_255as shown inFIG. 9C.

The memory organization of the First Memory Block911_800is shown inFIG. 9D. The overall Y-Component of the video data information of Region_1911of Digital Image900is stored sequentially from left to right using sixteen rows Row_0900_300through Row_15900_315, and two columns, Col_0900_480and Col_1900_481. The first region of Memory850comprises a first starting Memory Location0(Row_0, Col_0)900_800, located at the intersection of a first vertical position corresponding to Row_0900_300, and a first horizontal position corresponding to Col_0900_480. As has been described earlier, the first starting Memory Location0900_800comprises the Y-component of the video data information of the first starting Pixel Group0911_500comprising the first eight pixels of the first line Row_0911_300of Region_1911of Digital Image900. Similarly, Memory Location1(Row_0, Col_1)900_801comprises the Y-component of the video data information of the next and last eight pixels (from left to right) of the first line Row_0911_300of Region_1911. The second line of Region_1911comprises the first 16 pixel of the second line Row_1900_301of Digital Image900, while the second line of Region_3913comprises the last 16 pixel of the second line Row_1900_301of Digital Image900, and so on as shown inFIG. 9D.

Another exemplary memory location is located at the intersection of Row_0900_300and Col_5900_485, i.e. Memory Location65(Row_0, Col_5)900_865, comprising the Y-component of the video data information of the last eight pixels of the first line Row_0900_300of the Digital Image900as shown inFIG. 9D. In this case, these last eight pixels are also the last eight pixels of the first line of Region_3913of the Digital Image900.

The First Memory Block911_800comprises thirty-two memory locations, zero through thirty-one, as shown inFIG. 9D. The first starting Memory Location0(Row_0, Col_0)900_800is accessible using the first base address that corresponds to the starting memory location of the first region within Memory850, i.e. (00001024)10. Similarly, any other memory location within any one of the Region_1911, Region_2912, Region_3913, Region_4914, Region_5915, and Region_6916may be accessed using a corresponding row and column number that correspond to the intersection of a vertical and horizontal position within Digital Image900. For example, the first starting memory location of Region_3913is Memory Location64and is located at a physical address that is to be found at an offset address of (00000064)10from the base address (00001024)10of the first region of Memory850. Hence, the physical address of the first starting memory location of Region_3913is located at an address equal to the sum of the base address and the offset address, i.e. (00001088)10. Subsequently, a physical address of (00001089)10would corresponds to Memory Location65(Row_0, Col_5)900_865, as shown inFIG. 9D. It should be noted that different granularity of memory access is accomplished using longer or shorter words, e.g. 128-bit words for accessing sixteen pixels at a time or 16-bit words for accessing two pixels at a time. The access granularity of Memory850influences the performance of the Digital Image Processing System800. For a given application, various access granularity of Memory850can be used to accommodate a certain performance specification. Each of the video data information of Region_2912, Region_3913, Region_4914, Region_5915, and Region_6916is organized and stored into the first memory region as shown inFIG. 9D.

In accordance with another embodiment, independent memory regions of Memory850are used to store each of the video data information of Region_1911, Region_2912, Region_3913, Region_4914, Region_5915, and Region_6916independently. Similarly, each memory region may be accessed independently from other memory regions, and the retrieved video data information is processed, manipulated, and displayed, using a display region, in accordance with a video effect, resolution, scaling or video format that may be different from what is desired or required by another display region. Various memory organization methods and techniques may be used for how the regions within the Memory850are allocated. Accordingly, Memory850organization may change with the capacity or type of the physical memory being used. Furthermore, how fast the video data information is to be processed, stored, or retrieved would have an implication on the optimum organization of Memory850. For example, the video data information of Region_1911may be stored sequentially in a linear fashion using Row_0900_300through Row_5900_305, such that the first starting Memory Location0900_800is still located at the intersection of Row_0900_300and Col_0900_480. However, the memory location31is now located at the intersection of Row5900_305and Col_1900_481. In the following paragraphs, exemplary video data information transfers into, and out of Memory850is described; please refer toFIG. 8A,FIG. 8B,FIG. 9A, throughFIG. 9D.

The Input Module810comprises a first and second programmable registers to store a first and second value that corresponds to the Digital Image900Width900_612and Height900_622, respectively. The Input Module810comprises Input Capture810_10to receive and extract the Digital Image900video data information via the digital input data path, in accordance with the Digital Image900video format, e.g. 24 bit RGB. The Input Capture810_10may also be programmed to receive and extract only a predefined region's video data information, e.g. Region_1911of the Digital Image900. Region_1911is defined using a starting first pixel location Pixel_0911_000, its Width911_612and Height911_622within Digital Image900. The Input Module810comprises Video Formatter810_20that processes the captured video data information and generates, in accordance with a second video format e.g. YUV 4:2:2 16 bits, the video data information that corresponds to the Y-component and UV-component of Digital Image900.

The Input Module810further comprises Memory Interface810_30comprising a third and fourth programmable registers to store a first and second base index values, e.g. (001)10and (002)10. The first and second base index values are used as pointers to the first and second base addresses, e.g. (00001024)10and (00004096)10of the first and second regions of Memory850, as described above. This provides the flexibility to reorganize Memory850as needed. For example, a particular desired performance of the Digital Image Processing System800is satisfied by redefining or reprogramming the base addresses of memory regions, without affecting other memory access requests parameters. The Memory Interface810_30generates and outputs onto the First Memory Data Path831at least one first memory write command to transfer the Y-component of the video data information of Digital Image900starting at Memory Location0900_800of the first region of Memory850. In this example, the Memory Location0is used to store the Y-component of the video data information of the first starting pixel, Pixel_0900_0000which is the top-leftmost pixel of the Digital Image900. A description of memory access request to Memory850provides more details about the generation of a memory write or read command or a memory device write or read command.

The first memory write command comprises the first Base Index1020value (001)10, and a memory Offset Address1070value of (000)10, seeFIG. 10AandFIG. 10B. The Offset Address1070is used to indicate that the Memory Location0900_800is to be stored at the memory location as indicated by the first base address (00001024)10since the offset address is zero in this case. Since all of the Y-component of video data information of Region_1911, i.e. Pixel_0911_000through Pixel_255911_255, are grouped in eight pixels per memory location, then the total number of 64-bit words required is thirty-two. Thus, the first memory write command further comprises a total number of memory locations, #Words1080, value of (032)10. The #Words1080is used to indicate how many words or memory locations are to be transferred from the Input Module810, in response to the first memory write command, to the Memory Data Path Controller830via the First Memory Data Path831.

In another embodiment, the first memory write command comprises vertical and horizontal memory position of the first starting memory location of Region_1911, i.e. Ystart1030that corresponds to Row_0900_300and Xstart1040that corresponds to Col_0900_480, the intersection of Xstart1040and Ystart1030corresponds to Memory Location0900_800. The first memory write command further comprises the width, Xcount1050, and height, Ycount1060, of Region_1911in terms of memory words. In this example, the Width911_612of Region_1911is 16 pixels and corresponds to two 64-bit memory words. The Height911_622of Region_1911is 16 lines and thus corresponds to sixteen rows of 64-bit memory words, Row_0911_300through Row15911_315, seeFIG. 9C.

In one embodiment, the Memory Interface810_30of the Input Module810issues multiple memory write commands, as described above, to effect the transfer of all of the Y-component of the video data information of Region_1911to the Memory Data Path Controller830via the First Memory Data Path831. Similarly, Memory Interface810_30transfers the UV-component of the video data information of Region_1911of Digital Image900to the second region of Memory850. The Memory Interface810_30generates and outputs onto the First Memory Data Path831one, or multiple, second memory write command in accordance with the description of above paragraphs.

The Memory Data Path Controller830comprises a First Memory Interface830_10that receives the first memory write command and the Y-component of the video data information via the First Memory Data Path831. The Memory Data Path Controller830further comprises logic circuitry to extract from the first memory write command the first Base Index1020value (001)10, the memory Offset Address1070value of (000)10, and the total number of memory locations, #Words1080, value of (032)10. In one embodiment, the Memory Data Path Controller830further comprises logic circuitry to extract from the first memory write command the vertical and horizontal position of the first starting memory location of Region_1911, and the width and height information. In this example, width value Xcount1050=(002)10, the height value Ycount1060=(016)10, Ystart1030=(000)10and Xstart1040=(001)10, see above.

The Memory Data Path Controller830generates the first base address of the first memory region within Memory850based on the extracted first base index, Base Index1020. The Second Memory Interface830_30generates the appropriate physical memory address by using the first base address and the memory offset address, Offset Address1070. The Second Memory Interface830_30further generates at least one, or multiple, first memory device write command to complete the transfer of the Y-component of the video data information of Region_1911to the first region of Memory850via the Second Memory Data Path832. In this example, the first memory device write command includes the memory address (00001024)10as the first starting memory location address, where the Y-component of the Memory Location0900_800is to be stored. The content to be stored in the first memory region of Memory850in response to the first memory device write command, starting at physical memory address of (00001024)10, corresponds to the Y-component of the video data information of Region_1911. This includes Memory Location0(Row_0, Col_0)911_800that corresponds to Pixel Group0911_500through the Memory Location31that corresponds to Pixel Group31911_531, see Fig. C.

In one embodiment, the Second Memory Interface830_30generates at least one, or multiple, first memory device write command to complete the transfer of the Y-component of the video data information of Digital Image900to the first region of Memory850via the Second Memory Data Path832. The first memory device write command provides all the necessary control and/or handshake information for Memory850to properly decode the first memory device write command and store the Y-component of the video data information of Digital Image900in response to the first memory device write command. The stored content in the first memory region of Memory850, starting at physical memory address of (00001024)10, corresponds to the Y-component of the video data information of Digital Image900, Memory Location0(Row_0, Col_0)911_800through the Memory Location191(Row_31, Col_5)911_191. The Memory Data Path Controller830further comprises Control830_20module to control and manage the transfer of the video data information flow received via the First Memory Data Path831and outputted to Memory850via the Second Memory Data Path832. The transfer of the UV-component is described in the following paragraphs.

Similarly, the First Memory Interface830_10receives the second memory write command and the UV-component of the video data information, to be transferred in response to the second memory write command, via the First Memory Data Path831. The logic circuitry extracts at least the second base index information, the starting Memory Location0, and the total number of memory locations from the second memory write command. In accordance with the same process as described above, the Memory Data Path Controller830generates the second base address based on the second base index. Furthermore, The Second Memory Interface830_30generates at least one, or multiple, second memory device write command to complete the transfer of the UV-component of the video data information of Digital Image900to the second region of Memory850via the Second Memory Data Path832in response to the second memory write command. The Control830_20module controls and manages the transfer of the UV-component of the video data information flow received via the First Memory Data Path831and outputted to Memory850via the Second Memory Data Path832. The output display modules retrieve the video data information from Memory850for further processing as is described in the following paragraphs.

In one embodiment, the output display module ODM_1841is assigned to process the Y-component and the UV-component of the video data information from Region_1911. The other output display modules that are part of the Output Module840, e.g. ODM_2842, is programmed to process the Y-component and the UV-component of the video data information from Region_2912, and so on for the other ODMs. Each ODM processes one region of the Digital Image900and output the results to a dedicated display region of an electronic display panel. The combined picture resulting from all the adjoined display regions, comprising all the processed regions of the Digital Image900, results in a continuous and seamless display of Digital Image900as if it was processed by one output display module. A block diagram of an exemplary output display module is shown inFIG. 8E. Two-independent data paths are coupled to the First Memory Data Path831. Each of the data paths produces independent access requests to Memory850, as described below. The output display module ODM_1841further comprises a Control and Data Interface841_30module that is coupled to the First Control Data Path821and to a Registers & Control841_40module. The Control and Data Interface841_30enables access to ODM_1841internal registers and programmability control for ODM_1841functions. The Registers & Control841_40module comprises the necessary logic circuitry to store data and control information, and provide proper interface to the internal modules of ODM_1841.

The first data path of output display module ODM_1841comprises a First Input Buffer Control841_10. The Y-component of the video data information of Region_1911is retrieved from Memory850using the first data path. Furthermore, the first data path comprises a vertical scaler module VS841_11to process and/or scale in the vertical direction the Y-component of the video data information from Region_1911. An inter-scaler buffer ISB841_12provides the necessary buffering and management control of the streamed output of the vertical scaler VS841_11and into a horizontal scaler HS841_13, which processes or scales in the horizontal direction the already vertically scaled Y-component of the video data information from Region_1911. Since the vertical processing or scaling occurs separately from the horizontal processing or scaling, then the output display module is capable to scale independently the retrieved video data information in either the vertical or the horizontal direction. Similarly, the output display module ODM_1841second data path comprises a Second Input Buffer Control841_20that is assigned to retrieve the UV-component of the video data information of Region_1911from Memory850. The vertical scaler VS841_21processes or scales the UV-component of the video data information and output the vertically processed video data information to inter-scaler buffer ISB841_22. The horizontal scaler HS841_23process or scale the already vertically processed UV-component of the video data information and output the horizontally processed video data information to an Output Formatter841_50.

The horizontal scalers HS841_13and HS841_23stream their processed video data information to the Output Formatter841_50that further process and recombine the already vertically and horizontally processed or scaled Y-component and the UV-component of the video data information from Region_1911. The Output Formatter841_50streams its output onto the Output Display Data Path846via a dedicated channel to a designated display region. The Output Formatter841_50processes the video data information of Region_1911in accordance with a desired output video format standard as specified by the designated display region, e.g. RGB 4:4:4 24 bits per pixel. The output video format standard can be different from the YUV 4:2:2 16-bits used for storing and processing the video data information of Region_1911as has been described above. The output display module ODM_1841functions are programmable to independently process or scales the video data information in (i) the vertical direction, (ii) the horizontal direction, and (iii) a designated output video format standard. This provides for a proper display of the final processed video data information of Region_1911in accordance with the intended display region of the electronic display panel.

An exemplary Memory Access Request1000structure to access the video data information stored in Memory850, as shown inFIG. 10AandFIG. 10B, describes alternate means for using necessary digital image size and location information to generate memory write or read commands. In this example, the video data information of Region_1911comprises thirty-two memory locations and is stored within the first region of Memory850, as shown inFIG. 9B,FIG. 9C, andFIG. 9D. The First Input Buffer Control841_10produces a memory read command comprising a Base Index1020to read the video data information out of Memory850. The Base Index1020corresponds to the first starting memory location of the first region of Memory850, and in this example equals (001)10. The first memory read command further comprises a vertical origin Ystart1030value that corresponds to Row_0900_300, and a horizontal origin Xstart1040value that corresponds to Col_0900_400. The origin of Region_1911is the top-left corner of the Digital Image900, as specified in this example by the starting Memory Location0(Row_0, Col_0)911_800. Xstart and Ystart values correspond to the vertical and horizontal location of a memory word comprising a first starting pixel Pixel_0900_0000. Furthermore, Xcount1060is the width in memory words (or memory locations) of the Region_1911and in this example is specified as two 64-bit Words used for all sixteen pixels of one line of Region_1911. Ycount1050is the height in memory rows or lines of the Region_1911and in this example is specified as sixteen lines. The first memory read command may further comprises other control bits and data, Control1010, as may be necessary to describe the type of video data information to be processed, how data information is organized in Memory850, or signals as required by the Memory Data Path Controller830for proper execution of the memory access request. In accordance with the structure ofFIG. 10Aand this example, the first memory read command would comprise: [Control bits], [(001)10], [(000)10], [(000)10], [(016)10], [(002)10]. Another exemplary first memory read command using an Offset Address1070of zero, since Memory Location0is actually stored at zero offset from the first starting memory location of the first region of Memory850. Furthermore, Regions_1911comprises a total number of memory locations or 64-bits words, #Words1080, of 32, thus in accordance with the structure ofFIG. 10B, the first memory read command would comprise: [Control bits], [(001)10], [(000)10], [(032)10]. Whichever structure is used for the memory read command the Memory Data Path Controller830decodes and responds accordingly. In this example, the Memory Data Path Controller830generates the bases address for the intended memory region by using the Base Index1020value of (001)10as a pointer in a lookup table to retrieve the corresponding base address, i.e. (00001024)10. Furthermore, a memory device read command is generated using this base address and other information about location and size of the intended memory locations to be read, in accordance with the necessary constraints requirement to access Memory850. The Second Memory Interface830_30generates the location information for the address of the starting memory location to be read out of Memory850as (00001024)10by using (i) the base address, in this example (00001024)10, and (ii) the offset address of the desired memory location, in this example (00000000)10. Alternatively, the location information for the address of the starting memory location to be read out of Memory850is generated by performing proper operation using (i) the base address, (ii) the vertical memory location pointer Ystart1030, and (iii) the horizontal memory location pointer Xstart1040. In addition, The Second Memory Interface830_30generates the size information using #Words1080for total number of memory locations to be read, e.g. (00000032)10Alternatively, it generates the size information using the intended memory region size given by the vertical number of rows Ycount1050and the horizontal number of columns Xcount1060. Hence, in this example, the memory device read command is generated to indicate that the first memory location to be read is at address (00001024)10, and the last memory location to be read is at address (00001055)10.

The following paragraphs describes the processing of a quadrangle digital image D_1981by adding margin pixels to the Region_1911as shown inFIG. 9E. The generation of the margin pixels is accomplished using various means or the combination of various methods as has been described above, please refer to embodiments as described above. In accordance with one embodiment, a Top Margin981_623having a Top Margin Depth981_653of one pixel is generated by replicating the video data information of the corresponding pixels of a Top Edge911_732. Similarly, a Bottom Margin981_625having a Bottom Margin Depth981_655of one pixel is generated by replicating the video data information of the corresponding pixels of a Bottom Edge911_752. A Left Margin981_626having a Left Margin Depth981_656of one pixel is generated by replicating the video data information of the corresponding pixels of (i) the first pixel of the Top Margin981_623, (ii) the pixels of a Left Edge911_762, and (iii) the first pixel of the Bottom Margin981_625. Similarly, a Right Margin981_624having a Right Margin Depth981_654of one pixel is generated by replicating the video data information of the corresponding pixels of (i) the last pixel of the Top Margin981_623, (ii) the pixels of a Right Edge911_742, and (iii) the last pixel of the Bottom Margin981_625. The chosen vertical and horizontal scaling processes, to provide the desired quality of the processed output image, influence the depth size of each of the Top Margin Depth981_653, Bottom Margin Depth981_655, Left Margin Depth981_656, and Right Margin Depth981_654. In accordance with one embodiment, a depth of eight pixels is used. The quadrangle digital image D_1981has a width, D_1Width981_612, and a height, D_1Height981_622, in accordance with the following relationships:
D—1 Width 981—612=Left Margin 981—626+Width 911—612+Right Margin 981—624  Eq. 5
D—1 Height 981—622=Top Margin 981—623+Height 911—622+Bottom Margin 981—625  Eq. 6

In accordance with one embodiment, The video data information content of each of the pixels within the Top Margin981_623, forming a new first line of D_1981, are generated using a copy of the video data information of a corresponding pixel that is directly below it and is at the Top Edge911_732. For example, the first pixel of the Top Margin981_623comprises the video data information of Pixel_0911_000, and the last pixel of the Top Margin981_623comprises the video data information of Pixel_015911_015.

Similarly, the video data information content of each of the pixels within the Bottom Margin981_625, forming a new last line of D_1981, are generated using a copy of the video data information of a corresponding pixel that is directly above it and is at the Bottom Edge911_752. For example, the first pixel of the Bottom Margin981_625comprises the video data information of Pixel_240911_240, and the last pixel of the Bottom Margin981_625comprises the video data information of Pixel_255911_255.

In accordance with one embodiment, the video data information content of each of the pixels within the Left Margin981_626, forming a new first column of pixels for D_1981, is generated using a copy of the video data information of a corresponding pixel that is directly to the right of it. For example, the top pixel of the Left Margin981_626comprises the video data information of the first pixel of the Top Margin981_623. The bottom pixel of the Left Margin981_626comprises the video data information of the first pixel of the Bottom Margin981_625. The other pixels of the Left Margin981_626comprise the video data information of the pixels of the Left Edge911_762.

Similarly, the video data information content of each of the pixels within the Right Margin981_624, forming a new last column of pixels for D_1981, is generated using a copy of the video data information of a corresponding pixel that is directly to the left of it. For example, the top pixel of the Right Margin981_624comprises the video data information of the last pixel of the Top Margin981_623. The bottom pixel of the Right Margin981_624comprises the video data information of the last pixel of the Bottom Margin981_625. The other pixels of Right Margin981_624comprise the video data information of the pixels of the Right Edge911_742.

In the following paragraphs, the first data path of an output display module, e.g. ODM_1841, is used to describe an exemplary vertical and horizontal processing of the video data information for Region_1911as shown inFIG. 9C. In this example, the video data information corresponds to the Y-Component of the digital image that corresponds to Region_1911is processed using the first data path of ODM_1841, while the second data path processes in a similar fashion an independently retrieved video data information. In the following example, a margin depth of one pixel is assumed for each of the Top Margin Depth981_653, Bottom Margin Depth981_655, Left Margin Depth981_656, and Right Margin Depth981_654, as shown inFIG. 9E. Each of the Top Margin Depth981_653, Bottom Margin Depth981_655, Left Margin Depth981_656, and Right Margin Depth981_654can be specified independently from each other. The margin depth can vary in order to meet a given design and specification requirement of the output display module. Furthermore, each of the horizontal and vertical scaling ratios is assumed equal to one, which means that the desired output image resolution is the same as the retrieved input image's resolution in both the vertical and horizontal directions.

In accordance with one embodiment, the generation of the video data information of the pixels of the Top Margin981_623is done on the fly. When the first line Row_0911_300, as shown inFIG. 9C, is read out of memory and into the First Input Buffer Control841_10as Row_1981_301, as shown inFIG. 9E. The video data information content of the pixels of Row_0911_300is copied or replicated to generate Row_0981_300, as shown inFIG. 9E, namely the Top Margin981_623of the quadrangle digital image D_1981.

Similarly, the generation of the video data information of the Bottom Margin981_625is done on the fly when the last line of Region_1911, namely Row_15911_315seeFIG. 9C, is read out of memory and into the First Input Buffer Control841_10as Row_16981_316, seeFIG. 9E. A simple process to copy the video data information of the pixels of Row_15911_315may be used to generate the Bottom Margin981_625that corresponds to the eighteenth line of D_1981, namely Row_17981_317.

Other processes or methods may be used as well to effect the generation of the pixels of the Top Margin981_623and Bottom Margin981_625from pixels within Region_1911or neighboring regions, e.g. Region_2912. Variety of methods as described above may be employed to generate the pixels of the Top Margin981_623and Bottom Margin981_625. Furthermore, various types of data filtering or data interpolation can be used to process the video data information of the designated digital image and generate on the fly the video data information for the margin pixels. For example, video data information of a specific color can be used to generate the video data information of the pixels of the Top Margin981_623and Bottom Margin981_625.

In this example, D_1Height981_622comprises 18 lines and can be computed using Eq. 6. For example, the sum of (i) the Top Margin981_623that comprises one line, (ii) Row_0911_300through Row_15911_315comprising 16 lines, and (iii) the Bottom Margin981_625that comprises one line. At this stage, after the processing in the vertical direction is completed, the width of vertically processed lines stored in the inter-scaler buffer ISB841_12corresponds to 16 pixels, and is the same as Width911_612, as shown inFIG. 9C.

The vertical scaler, VS841_11, operates using a group of two or more lines at a time to generate one vertically processed line that is outputted to the inter-scaler buffer, ISB841_12, for temporary storage. The number of lines that are used to produce one vertically processed line depends on the type of scaling process methodology and the number of coefficients required to provide a desired accuracy for a given scaling process and/or a given scaling ratio for the intended quality level of the scaled output image. In this example, the video data information of the pixels of two vertically adjacent lines are used to generate the video data information for the vertically processed line. In accordance with one embodiment, eight vertically adjacent lines are used to generate one vertically processed line that is outputted to the inter-scaler buffer, ISB841_12, for temporary storage. In accordance with one embodiment, four vertically adjacent lines are used to generate one vertically processed line that is outputted to the inter-scaler buffer, ISB841_12, for temporary storage. If the vertical scaling ratio is equal to two, then the total number of the vertically processed lines outputted to the inter-scaler buffer ISB841_12is twice that of D_1Height981_622. In this example, the vertical scaler VS841_11would output thirty-six vertically processed lines, which is twice that of the D_1Height981_622comprising eighteen lines, sixteen lines of which are from Region_1911and one line each from the Top Margin981_623and Bottom Margin981_625.

An exemplary processing of two vertically adjacent lines to produce one new vertically processed line is described as follows; please refer toFIG. 9CandFIG. 9E. The vertical scaler VS841_11starts the processing of Pixel_1981_001, of the Top Margin981_623, identified as Row_0981_300inFIG. 9E, that is vertically adjacent to Pixel_0911_000of the row identified as Row_1981_301. The video data information of both pixels are processed in accordance with a data filtering or combining process where the data processing comprises taking into consideration the number of input pixels being processed and the vertical scaling ratio to determine the resultant video data information that is used to produce a new video data information for a new pixel. This new pixel is the first vertically processed pixel of a first vertically processed line of the vertically processed output image. The first vertically processed pixel is outputted to the inter-scaler buffer, ISB841_12for temporary storage. The process continues and the next two vertically adjacent pixels are then processed in a similar fashion. A second vertically scaled pixel is then outputted to the inter-scaler buffer ISB841_12for temporary storage. The vertical scaling process continues until the last pixel of the Top Margin981_623is reached namely Pixel_16981_016. In this example, Pixel_15911_015is adjacent and directly below Pixel_16981_016and both pixels are the last two vertically adjacent pixels to be processed, producing the last vertically processed pixel of the first vertically processed line of the vertically processed output image. Thus, the first vertically processed line is now complete and stored in the inter-scaler buffer ISB841_12temporary storage, which will be streamed to the horizontal scaler HS841_13upon the initiation of the horizontal scaling process for the first vertically scaled or processed line.

The vertical scaling process now repeats using the second line of D_1981that corresponds to Row_1981_301, which is the same as Row_0911_300, and the third line of D_1981that corresponds to Row_2981_302. Thus, the second vertically processed line is generated and outputted to the inter-scaler buffer ISB841_12for temporary storage. The vertical scaling process continues until the eighteenth vertically processed line of the vertically scaled output image is generated and outputted to the inter-scaler buffer ISB841_12for temporary storage. As the vertical scaling process operation is being completed, then the video data information of the pixels of the topmost lines of the First Input Buffer Control841_10are no longer needed for the vertical scaling process operation of the current digital image. Therefore, the topmost lines, e.g. Row_0981_300, Row_1981_301, etc. . . . , may now be discarded, and in accordance with the design requirement one or more lines may be discarded at a time. A first-in-first-out FIFO buffer may be used within the First Input Buffer Control841_10to store the video data information. As the topmost line or lines are no longer needed, then the First Input Buffer Control841_10may initiate a memory read operation to retrieve a single new line or multiple lines of video data information to be read out of memory and into the First Input Buffer Control841_10overwriting the line or lines to be discarded. The First Input Buffer Control841_10maintains its FIFO full so that the vertical scaling process progress continuously as needed or required by the output display module ODM_1841and in accordance with the desired performance of the Digital Image Processing System800. Furthermore, the topmost line or lines of the First Input Buffer Control841_10may be kept for a certain amount of time, long enough to perform a recall or a video effect operation as may be desired or necessary. Upon the initiation of the horizontal scaling process for the first vertically processed line, the horizontal scaler HS841_13retrieve the first vertically processed line from inter-scaler buffer ISB841_12. The left and right margin pixels are generated for all of the vertically processed lines as will be described in the following paragraphs.

In accordance with one embodiment, the generation of the video data information of the pixels of the Left Margin981_626and the Right Margin981_624is done on the fly. For example, as the video data information of the pixels of the vertically processed line is being streamed into the horizontal scaler HS841_13from the inter-scaler buffer ISB841_12temporary storage. Other means for generating the Left Margin981_626and the Right Margin981_624pixels may be used as well, as described earlier in this disclosure. In this example, the left margin pixel and the right margin pixel are generated using a copy of the first pixel and the last pixel of each vertically processed line, respectively. For example, the first pixel and the last pixel of the first vertically processed line, which is stored in the inter-scaler buffer ISB841_12temporary storage, are replicated to generate the top pixel Pixel_0981_000of the Left Margin981_626and the top pixel Pixel_17981_017of the Right Margin981_624, respectively. In accordance with one embodiment, upon the initiation of the horizontal scaling process, the new vertically processed line including the left and right margin pixels is streamed to the horizontal scaler HS841_13.

The horizontal scaling process is similar to the vertical scaling process as described above and utilize two or more horizontally adjacent pixel to generate one horizontally processed pixel. In this example, two horizontally adjacent pixels are used to generate one horizontally processed pixel. This horizontally processed pixel is streamed to the Output Formatter841_50for further processing. The horizontal processing continues until all of the horizontally processed pixels are generated in accordance with the desired horizontal scaling ratio. Similarly, the process continues for all the vertically processed lines, including the left and right margin pixels, and all the vertically and horizontally processed lines are streamed to the Output Formatter841_50in the same way as for the first vertically processed line. Since we are using a scaling ratio of one in this example, the vertically and horizontally processed D_1981comprises eighteen rows, Row_0981_300through Row_17981_317and each row having a width that is equal to eighteen pixels, Width981_612seeFIG. 9E, in accordance with Eq. 5 and Eq. 6. For example, if the vertical scaling ration is equal to one and the horizontal scaling ratio is equal to two, then the D_1Width981_612would equal to thirty-two pixels while the D_1Height981_622would equal eighteen pixels (or rows). The vertically and horizontally processed pixels resulting from the appended margin pixels will be appropriately cropped by the Output Formatter841_50so that the desired vertically and horizontally processed pixels that correspond to the Region_1911are displayed, as will be described in the following paragraphs.

The second data path of the output display module ODM_1841independently retrieves, and processes video data information in the vertical or the horizontal directions. In this example, the UV-component of D_1981is independently retrieved using the Second Input Buffer Control841_20. The vertical and horizontal processing is performed using a vertical scaler VS841_21, an inter-scaler buffer ISB841_22, and a horizontal scaler HS841_23. In a similar fashion as described above for the first data path, the horizontal scaler HS841_23streams the vertically and horizontally processed video data information to the output formatter841_50.

The Output Formatter841_50further processes and appropriately synchronizes and combines the vertically and horizontally processed Y-component and UV-component of D_1981to generate and output onto the Output Display Data Path846the desired output image in accordance with an output video format standard that is compatible with the destination display region. The Output Formatter841_50appropriately crops the combined vertically and horizontally processed pixels that are the result of the appended Top Margin981_623, Bottom Margin981_625, Left Margin981_626, and Right Margin981_624. The combined vertically and horizontally processed pixels, which are used in the generation of the desired output image that corresponds to Region_1911, when displayed alongside the other vertically and horizontally processed pixels of neighboring regions will result in a contiguous and a full display a vertically and horizontally processed Digital Image900. The Output Formatter841_50streams or outputs each synchronized and combined vertically and horizontally processed line onto the Output Display Data Path846, the Output Formatter841_50uses a data enable signal to indicate to an electronic display device to discard or blank one or more pixels for each line. In some instances, an entire line may be blanked. Therefore, in this example with a scaling ratio of one, the desired processed output image to be displayed that corresponds to Region_1911comprises sixteen lines, where each line comprises sixteen pixels. The following paragraphs will describe a slightly different method to process or scale Region_1911.

In accordance with one embodiment, the vertical and horizontal processing of Region_1911of the Digital Image900is accomplished by defining a quadrangle digital image D_2982that includes all of the pixels of Region_1911and a right and bottom margin pixels from neighboring regions, as shown inFIG. 9FandFIG. 9G. In this example, it is assumed that a margin depth of one pixel is used. The right margin pixels comprise the leftmost edge pixels of Region_2912and the top-leftmost pixel of Region_5915. The bottom margin pixels comprise the topmost edge pixels of Region_4914. In this example, the Right Margin982_624is generated from the first column of pixels of Region_2912, comprising Pixel_256900_0256through Pixel_496900_0496in the vertical direction, and the first pixel of Region_5915, comprising Pixel1024900_1024, seeFIG. 9F. The Bottom Margin982_625is generated from the first row of pixels of Region_4914, comprising Pixel_768900_0768through Pixel_783900_0783in the horizontal direction. Therefore, D_2982comprises seventeen rows, and each row comprises seventeen pixels, seeFIG. 9G. The generation of top and left margin pixels for the vertical and horizontal processing of D_2982can be done in multiple ways and is illustrated in the following embodiments.

Now referring toFIG. 9Hand in accordance with one embodiment, the video data information content of the pixels of the Top Margin982_623and the Left Margin982_626is generated on the fly or in a similar manner as described in the embodiments above. Therefore, the quadrangle digital image D_2982comprises eighteen rows, and each row comprises eighteen pixels, seeFIG. 9H. The quadrangle digital image D_2982comprises the Bottom Margin982_625and Right Margin982_624. Thus, the vertical and horizontal processing of D_2982can be accomplished as has been described in the embodiments above. The Output Formatter841_50streams or outputs each vertically and horizontally processed line onto the Output Display Data Path846, the Output Formatter841_50uses a data enable signal to indicate to an electronic display device to discard or blank one or more pixels for each line. In some instances, an entire line may be blanked. Therefore, in this example with a scaling ratio of one, the desired processed output image to be displayed that corresponds to Region_1911comprises 16 lines, where each line comprises 16 pixels. The following paragraphs will describe a slightly different method to process or scale Region_1911.

Now referring toFIG. 9Iand in accordance with one embodiment, the video data information content of the pixels of the Top Margin982_623, the Bottom Margin982_695, the Left Margin982_626and the Right Margin982_694are generated on the fly or in a similar manner as described in the embodiments above. Please note that the quadrangle digital image D_2982already comprises the Bottom Margin982_625and Right Margin982_624. Therefore, the quadrangle digital image D_2982comprises nineteen rows, and each row comprises nineteen pixels, seeFIG. 9I. One can think of the quadrangle digital image D_2982as a whole region to be processed, and the top, bottom, left and right margin are newly generated. Thus, the vertical and horizontal processing of D_2982can be accomplished as has been described in the embodiments above. The Output Formatter841_50streams or outputs each vertically and horizontally processed line onto the Output Display Data Path846, the Output Formatter841_50uses a data enable signal to indicate to an electronic display device to discard or blank one or more pixels for each line. In some instances, an entire line may be blanked. In this example with a scaling ratio of one, the desired processed output image to be displayed, which corresponds to Region_1911, comprises 16 lines and each line comprises 16 pixels. Accordingly, the Output Formatter841_50processes and crops the vertically and horizontally processed pixels of D_2982so that only the appropriate processed pixels that correspond to Region_1911are used in the display of the desired output image. The Output Formatter841_50processes and crops the first line and the last two lines, and the first column and the last two columns so that the output image comprises sixteen processed lines, and each processed line comprising sixteen pixels in direct proportion the resolution of Region_1911given a vertical and horizontal scaling ratio of one. In accordance with one embodiment, the Output Formatter841_50streams or outputs each vertically and horizontally processed line along with a data enable signal using the Output Display Data Path846. The Output Formatter841_50asserts the data enable signal using appropriate timing to indicate to an electronic display module to discard or blank the first line, the last two lines, and the first pixel and the last two pixels of the remaining vertically and horizontally processed lines of D_2982output image.

In accordance with one embodiment, it quadrangle digital image D_3983comprises the pixels of Region_2912, and pixels from neighboring left, bottom, and right regions of Digital Image900, as shown inFIG. 9J. These pixels are used to create the right margin, bottom margin, and left margin for Region_2912. In this example, the margin depth is assumed equal to one pixel. The top margin pixels are generated and the quadrangle digital image D_3983is processed in a similar fashion as described above.

In accordance with one embodiment, the quadrangle digital image D_3983comprises the pixels of Region_2912, and pixels from neighboring left, bottom, and right regions of Digital Image900, as shown inFIG. 9J. In this example, the top, bottom, left, and right margin pixels are generated on the fly irrespective of whether the quadrangle digital image D_3983comprises margin pixels from neighboring regions or not. The quadrangle digital image D_3983is processed in a similar fashion as described above and similar to the illustration for Region_1911as shown inFIG. 9I. In the following paragraphs, memory access is described for various regions types of Digital Image900that are defined using various shapes and sizes.

The Digital Image900is split into six regions and each region may be further split into four sub-regions as shown inFIG. 9K. In this example, Region_2912is split into four sub-regions, namely Region_2_1912_10, Region_2_2912_20, Region_2_3912_30, and Region_2_4912_40. In accordance with one embodiment, an exemplary memory access request is initiated to write or read the video data information content of Region_2_3912_30to or from a Second Memory Block912_30_800, as shown inFIG. 9L. This exemplary memory access request is described using the command structure as shown inFIG. 10A. The memory locations that correspond to Region_2_3912_30are illustrated as a shaded region enclosed by dashed lines and labeled as Second Memory Block912_30_800, as shown inFIG. 9L. In this example, the Y-component of video data information of Region_2912is stored within the first memory region starting at memory location32and ending at memory location63, as shown inFIG. 9L.

In this example, a memory read command is initiated by output display module ODM_1841to retrieve the Second Memory Block912_30_800that comprises the Y-component of the video data information of the pixels of Region_2_3912_30. The First Input Buffer Control841_10produces a memory read command comprising a Base Index1020to read the video data information out of Memory850. The Base Index1020value corresponds to the first starting memory location of the first region of Memory850, and in this example equals (001)10. The Region_2_3912_30comprises eight memory locations, namely: 48, 50, 52, 54, 56, 58, 60, and 62. The vertical and horizontal origin of the Region_2_3912_30, comprising the top-leftmost pixel of Region_2_391230, is identified using Ystart1030and Xstart1040values, respectively. In this example, the location information of the vertical and horizontal origin is given by Ystart1030=(008)10that corresponds to the ninth row (Row_8), and Xstart1040=(002)10that corresponds to the third column (Col_2), see Memory Location48(Row_8, Col_2)900_848. Furthermore, the size information is given by Xcount1060=(001)10that corresponds to one memory location in width or the horizontal direction, and Ycount1050=(008)10that corresponds to eight memory locations in height or the vertical direction. Therefore, the exemplary memory read command, in accordance with the command structure ofFIG. 10A, comprises the following: [Control bits], [(001)10], [(008)10], [(002)10], [(008)10], [(001)10]. The Memory Data Path Controller830generates the bases address for the intended memory region by using the Base Index1020value of (001)10as a pointer in a lookup table to retrieve the corresponding base address, i.e. (00001024)10. The Second Memory Interface830_30generates at least one memory device read command using the size and location information embedded within the memory read command, as has been described earlier.

Now referring toFIG. 9M, the Digital Image900is split into six regions, namely Region_1911, Region_2912, Region_3913, Region_4914, Region_5915, Region_6916. Region_991_123991_123_900is a concatenation of the first row of each of the Region_1911, Region_2912, and Region_3913. In accordance with one embodiment, an exemplary memory access request is initiated to write or read the video data information content of Region_991_123991_123_900to or from a Third Memory Block991_123_800, as shown inFIG. 9N. This exemplary memory access request is described using the command structure as shown inFIG. 10A. The memory locations that correspond to Region_991_123991_123_900are illustrated as a shaded region enclosed by dashed lines and labeled as Third Memory Block991_123_800. In this example, the Y-component of video data information of Region_991_123991_123_900is stored within the first memory region starting at memory location0and comprising memory location0,1,32,33,64, and65, as shown inFIG. 9N.

In this example, a memory read command is initiated by the output display module ODM_1841to retrieve the Third Memory Block991_123_800, comprising the Y-component of the video data information of the pixels of Region_991_123991_123_900. The First Input Buffer Control841_10produces a memory read command comprising a Base Index1020to read the video data information out of Memory850. The Base Index1020value corresponds to the first starting memory location of the first region of Memory850, and in this example equals (001)10. The vertical and horizontal origin of the Region_991_123991_123_900, comprising the top-leftmost pixel of Region_991_123, is identified using Ystart1030and Xstart1040values, respectively. In this example, the location information is given by Ystart1030=(000)10that corresponds to the first row (Row_0), and Xstart1040=(000)10that corresponds to the first column (Col_0). Furthermore, the size information is given by Xcount1060=(006)10that corresponds to six memory location in width or the horizontal direction, and Ycount1050=(001)10that corresponds to one memory location in height or the vertical direction, i.e. one line of the Digital Image900. Therefore, the exemplary memory read command, in accordance with the structure ofFIG. 10A, comprises the following: [Control bits], [(001)10], [(000)10], [(000)10], [(001)10], [(006)10]. The Memory Data Path Controller830generates the bases address for the intended memory region by using the Base Index1020value of (001)10as a pointer in a lookup table to retrieve the corresponding base address, i.e. (00001024)10. The Second Memory Interface830_30generates at least one memory device read command using the size and location information embedded within the memory read command, as has been described above.

Now referring toFIG. 9O, the Digital Image900is split into six regions, namely Region_1911, Region_2912, Region_3913, Region_4914, Region_5915, and Region_6916. Region_991_023991_023_900is a concatenation of Region_2912, and Region_3913. In accordance with one embodiment, an exemplary memory access request is initiated to write or read the video data information content of Region_991_023991_023_900to or from a Fourth Memory Block991_023_800, as shown inFIG. 9O. This exemplary memory access request is similar to the memory access request described above and uses the command structure ofFIG. 10A. The memory locations that correspond to Region_991_023991_023_900are illustrated as a shaded region enclosed by dashed lines and labeled as Fourth Memory Block991_023_800. In this example, the Y-component of video data information of Region_991_023991_023_900is stored within the first memory region starting at memory location32and ends at memory location95. The memory read command to retrieve the Fourth Memory Block991_023_800is generated as has been described in the above embodiments; seeFIG. 9Das a reference for the memory size and location information, e.g. Ystart1030, Xstart1040, Ycount1050, and Xcount1060.

Now referring toFIG. 9P, the Digital Image900is split into six regions, namely Region_1911, Region_2912, Region_3913, Region_4914, Region_5915, and Region_6916. Region_991_036991_036_900is a concatenation of Region_3913and Region_6916. In accordance with one embodiment, an exemplary memory access request is initiated to write or read the video data information content of Region_991_036991_036_900to or from a Fifth Memory Block991_036_800, as shown inFIG. 9P. This exemplary memory access request is similar to the memory access request described above and uses the command structure ofFIG. 10A. The memory locations that correspond to Region_991_036991_036_900are illustrated as a shaded region enclosed by dashed lines and labeled as Fifth Memory Block991_036_800. In this example, the Y-component of video data information of Region_991_036991_036_900is stored within the first memory region starting at memory location64through memory location95and memory location160through memory location191. The memory read command to retrieve the Fifth Memory Block991_036_800is generated as has been described in the above embodiments; seeFIG. 9Das a reference for the memory size and location information, e.g. Ystart1030, Xstart1040, Ycount1050, and Xcount1060.

The exemplary embodiments as described in this disclosure are used interchangeably to develop a certain and unique Digital Image Processing System800that meets a widely varying input digital image processing requirements, including various techniques to process and split an input digital image. Furthermore, various embodiments provide the ability to customize the Digital Image Processing System800to meet an ever-changing electronic display panels' size and specification.