Output circuit with transistor overcurrent protection

When the overcurrent detection circuit detects that a voltage drop of the output transistor exceeds a threshold value, it turns on the switch by the first operational amplifier. In the shut-down signal generation circuit, the capacitor is charged with a charge current determined based on a current depending on the voltage drop of the output transistor. The shut-down signal generation circuit generates a shut-down signal to turn off the output switch when a voltage of the capacitor exceeds a voltage of the inverting input terminal of the second operational amplifier.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an output circuit and, more particularly, to an output circuit having an overcurrent protection function.

2. Description of a Related Art

An output circuit has a switching element to control on/off of power supply to a load according to input control signals. A transistor such as a power MOS is used as the switching element. If an overcurrent flows in the switching element, it can break down the switching element due to overheating and so on. Thus, the output circuit normally has an overcurrent protection function to protect the switching element from the breakdown.

Techniques for the overcurrent protection function of the switching element are described in Japanese Unexamined Patent Application Publication No. 62-243418 and Japanese Unexamined Patent Application Publication No. 10-107605, for example. According to the former technique, a resistor as a current detector is placed in the emitter side of an output transistor constituting a switching element so as to detect an overcurrent flowing in the output transistor. A capacitor connects the base of the output transistor with the base of another transistor for turning off the output transistor. The capacitor is charged or discharged upon detection of an overcurrent by the current detector, thereby intermittently turning on and off the output transistor to protect the switching element.

Generally in the techniques for protecting a switching element from an overcurrent, including those described in the above conventional arts, a time period from the detection of the overcurrent to the turn-off of the switching element, which is called a shut-down time, is set according to a charge/discharge time of the capacitor, that is, a capacitance value of the capacitor, or a resistance value that determines a charge/discharge current value of the capacitor. The shut-down time set in this way is constant regardless of the degree of abnormality occurring in a load. The overheating of the switching element depends on the value and time of the current flowing through the switching element. Thus, in the case where significant abnormality occurs in the load and a large current flows through the switching element, it is necessary to set the shut-down time short in order to avoid that the switching element is broken down before it is forcibly turned off. If, however, the shut-down time is set short and a threshold current for overcurrent detection (a minimum value of an abnormal current) is set low, the switching element can be undesirably turned off due to a rush current immediately after turn-on even when no abnormality occurs in the load.

It is possible to avoid this problem by increasing the threshold current for overcurrent detection. However, if the overcurrent detection threshold current is set high in order to avoid the forced turn-off of the switching element, it is impossible to effectively protect the switching element from the breakdown due to overheating when the degree of abnormality occurring in a load is low and a current which is higher than a steady current of the load but not as high as the overcurrent detection threshold current keeps flowing through the load since the overheating of the switching element depends on the value and time of the current flowing through the switching element.

SUMMARY OF THE INVENTION

In view of the foregoing, it is an object of the present invention to provide an output circuit that can change the shut-down time according to the degree of abnormality occurring in the load so as to effectively protect the switching element from breakdown due to abnormal current flow.

To these ends, according to one aspect of the present invention, there is provided an output circuit comprising an output transistor connected in series with a load for supplying a load current; and a protection circuit for protecting the output transistor; the protection circuit comprising a current detection circuit for detecting if the load current exceeds a threshold value, and an off-signal generation circuit for generating an off-signal to turn off the output transistor after a time depending on a voltage drop of the output transistor is elapsed since the current detection circuit detects that the load current exceeds a threshold value.

In this output circuit, a signal to turn off the output transistor is generated by the off-signal generation circuit after an elapsed time depending on a voltage drop of the output transistor from a time when the current detection circuit detects that a load current flowing through the output circuit exceeds a threshold value, that is, when it detects that abnormality occurs in the load. It is thereby possible to change a time period during which an abnormal current flows through the output transistor according to the degree (level) of the abnormality occurring in the load. For example, if the degree of the abnormality occurring in the load is high, the output switch may be immediately turned off. If the degree of the abnormality is low, on the other hand, the output switch may be turned off after a relatively long period of time. This allows effective protection of the output switch from breakdown due to heat both when the degree of abnormality in a load is high and low.

In this output circuit, the off-signal generation circuit may remove the off-signal after a certain elapsed time from generation of the off-signal. Alternatively, the off-signal generation circuit may remove the off-signal after another elapsed time depending on a voltage drop of the output transistor from generation of the off-signal. If the output circuit has the configuration in which the off-signal generation circuit removes the off-signal after the protection circuit turns off the output transistor, the output circuit may return to the normal operation when the abnormality in the load has been eliminated before the off-signal is removed.

In this output circuit, the current detection circuit may detect if the load current exceeds a threshold value based on whether a voltage drop of the output transistor exceeds a threshold value. In this case, the current detection circuit theoretically detects the level of the load current based on the level of the voltage drop of the output transistor.

In this output circuit, the off-signal generation circuit may comprise a current generator for generating a current depending on a voltage drop of the output transistor and a capacitor to be charged with the current generated by the current generator, and the off-signal generation circuit may generate the off-signal if a terminal voltage of the capacitor exceeds a given value. In this case, an elapsed time before generating the off-signal may be determined based on a charge time of the capacitor.

In this output circuit, the current generator may comprise a current mirror comprising a reference transistor through which a current depending on a voltage drop of the output transistor flows and an output transistor connected in series with the capacitor. In this case, the capacitor is charged by the output transistor. The reference transistor and the output transistor of the current mirror may be connected to a different power system.

In another aspect, in the output circuit, the off signal generation circuit may comprise a clock signal generation circuit for generating a clock signal having a cycle depending on a voltage drop of the output transistor and a counter for counting the clock signal and generating the off-signal after counting a given number of clocks. In this case, an elapsed time period before generating the off-signal may be determined based on a time required for counting up to a given number of clock pulses of the clock signal having the cycle depending on the voltage drop of the output transistor in the off signal generation circuit.

In this output circuit, the clock signal generation circuit may comprise a current generator for generating a current depending on a voltage drop of the output transistor and a capacitor to be charged with the current generated by the current generator, so that the clock signal has a cycle depending on a charge time of the capacitor. Changing the cycle of the clock signal depending on the degree of abnormality occurring in the load allows an elapsed time period before generating the off-signal to be dependent on the degree of the abnormality occurring in the load.

In this output circuit, the current generator may comprise a current mirror comprising a reference transistor through which a current depending on a voltage drop of the output transistor flows and an output transistor connected in series with the capacitor. In this case, the capacitor is charged with a charge/discharge current depending on a current flowing through the output transistor. The reference transistor and the output transistor of the current mirror may be connected to a different power system.

In this output circuit, load elements comprising a MOS transistor of which a gate and a source are connected to each other and at least one zener diode connected in series with the MOS transistor may be connected in series with the reference transistor of the current mirror.

The output circuit determines a time period from when a voltage drop of the output transistor exceeds a threshold value to when the off-signal generation circuit generates an off-signal based on a voltage-current characteristics of the reference transistor of the current mirror. By connecting the zener diode in serial with the MOS transistor of which the gate and the source are connected to each other or with a resistor, it is possible to change the voltage-current characteristics of the reference transistor of the current mirror. The number of zener diodes to be connected may be appropriately adjusted to obtain desired current-voltage characteristics of the reference transistor.

In the output circuit, a plurality of the load elements connected in parallel may be connected to the reference transistor. In this case, by connecting a plurality of load elements with different current-voltage characteristics in parallel, it is possible to obtain desired current-voltage characteristics of the reference transistor.

In the output circuit, another MOS transistor of which a gate and a source are connected to each other may be connected in parallel with the load elements.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Specific embodiments of the present invention are explained hereinafter in detail with reference to the drawings. Referring first toFIG. 1, the configuration of an output circuit according to the first embodiment of the present invention is shown. The output circuit10has an output switch11, a gate control circuit12, a current limitation circuit13, an AND circuit14, a counter15, an overcurrent detection circuit16, current generation circuits17and18, and a clock generator19. The output circuit10of this embodiment can change a clock pulse width (clock signal cycle) of a clock signal “C” generated by the clock generator19depending on a voltage difference Vonbetween a power terminal Vbb and an output terminal OUT.

The output switch11is composed of a semiconductor switching element such as a power MOS, for example, and placed between the power terminal Vbb to which a power source such as a battery is connected and the output terminal OUT to which a load such as a lamp or a solenoid coil is connected. The gate control circuit12controls the switching of the output switch11. The current limitation circuit13prevents a large current such as a short-circuit current from flowing into the output switch11. The AND circuit14inputs an AND signal “F” of a control signal “E” from an input terminal IN and an output signal “D” from the counter15into the gate control circuit12.

The counter15, the overcurrent detection circuit16, the current generation circuits17and18, and the clock generator19constitute a protection circuit. The overcurrent detection circuit16detects if an abnormal current that exceeds a threshold level flows through the output switch11. The first current generation circuit17generates a current I1that depends on a voltage difference between the power terminal Vbb and the output terminal OUT. The second current generation circuit18generates a current I2that is based on the current I1. The clock generator19generates a clock signal “C” that is based on the second current I2. The counter15counts the clock pulse of the clock signal “C” and outputs a signal “D” of high-level or low-level.

Referring next toFIG. 2, an example of the configuration of the gate control circuit12is shown. The gate control circuit12has an inverter121, a charge pump circuit122, a pMOS21, nMOS22and23, and resistors R21and R22. The charge pump circuit122has inverters123and124, diodes D21to D23, capacitors C21and C22, a charge pump clock generator125. The gate control circuit12outputs a gate control signal “G” that is based on the input AND signal “F” to control the switching of the output switch11.

If a high level of AND signal “F” is input to the gate control circuit12through the inverter121, the charge pump clock generator125is activated, and the charge pump circuit122generates such voltage that the power voltage Vbat is increased to Vbat+10V, for example. In this case, the pMOS21is on and the nMOS22and nMOS23are off, and the gate control circuit12outputs the gate control signal “G” in which the voltage increased by the charge pump circuit122is a high level to turn on the output switch11. If, on the other hand, a low level of AND signal “F” is input to the gate control circuit12through the inverter121, the nMOS22and nMOS23are on and the PMOS21is off. In this case, a signal line connecting the gate control circuit12and the output switch11is shorted out with the output terminal OUT to turn off the output switch11.

Referring back toFIG. 1, the AND circuit14inputs the AND signal “F” of the control signal “E” from the input terminal IN and the output signal “D” from the counter15into the gate control circuit12. The counter15outputs a high level of signal “D” in normal times when the overcurrent detection circuit16does not detect an abnormal current flow in the output switch11. On the contrary, it outputs a low level of signal “D” under a given condition, which is described later, when the overcurrent detection circuit16detects the abnormal current flow. When the counter15outputs the high level of signal “D”, the AND circuit14outputs the AND signal “F” based on the control signal “E”.

The current limitation circuit13has the nMOS2and the diodes D1to D4. The nMOS2and the diodes D1to D4are inserted serially between the signal line connecting the gate control circuit12and the output switch11, and the output terminal OUT. The gate of the nMOS2is connected to the power terminal Vbb. The current limitation circuit13operates in the following way to reduce the level (voltage) of the gate control signal “G” upon occurrence of abnormality in the load so as to limit the current flowing through the output switch11to a given level, thereby preventing a large current such as a short-circuit current of more than 600A, for example, from flowing into the output switch11.

When the output switch11is on, if no abnormality occurs in the load, the voltage (output voltage) Vout between the output terminal OUT and the ground is substantially equal to the power voltage Vbat. In this case, the nMOS2is off and no current flows through the diodes D1to D4. If, on the other hand, abnormality occurs in the load and the output terminal OUT is grounded equivalently as shown by a dotted line inFIG. 1, the output voltage Vout is substantially equal to a ground voltage. In this case, the nMOS2is on to allow a current to flow from the signal line connecting the gate control circuit12and the output switch11to the output terminal OUT through the diodes D1to D4. The level of the gate control signal “G” thereby decreases to suppress the current flowing through the output switch11. The current limitation circuit13limits the current value to about double the maximum value of a rush current immediately after turning on the output switch11; thus, the current value is limited to 200A if the maximum rush current value is 100A, for example.

The first current generation circuit17has a pMOS1and a resistor R0. The pMOS1and the resistor R0are inserted serially between the power terminal Vbat and the output terminal OUT, and the gate of the pMOS1is connected to the drain of the same. The first current generation circuit17generates a current I1that changes depending on a voltage difference Von(=Vbat−Vout) between the power terminal Vbb and the output terminal OUT.

The second current generation circuit18has a pMOS3and a nMOS4. The pMOS3and the nMOS4are inserted between both lines of a power source V1. In the second current generation circuit18, the gate of the nMOS4is connected to the drain of the pMOS3, and the gate of the pMOS3is connected to the gate of the pMOS1in the first current generation circuit17. Thus, the pMOS3of the second current generation circuit18and the pMOS1of the first current generation circuit17constitute a current mirror, and the second current generation circuit18generates a current I2that depends on the current I1generated by the first current generation circuit17.

The second current generation circuit18determines a charge current I3and a discharge current I4for determining the cycle of the clock signal “C” generated by the clock generator19. Since the current I2generated by the second current generation circuit18is proportional to the current I1generated by the first current generation circuit17, the cycle of the clock signal “C” generated by the clock generator19depends on the voltage difference between the power terminal Vbb and the output terminal OUT.

The overcurrent detection circuit16has an operational amplifier OP1and a switch SW1to detect if an abnormal current flows through the output switch11. In the operational amplifier OP1, an inverting input terminal is connected to the switch SW1and a non-inverting input terminal is connected to the power terminal Vbb through a power source Vreffor determining a threshold voltage. According to the control signal “E” input through the input terminal IN, the switch SW1connects the inverting input terminal of the operational amplifier OP1with the power terminal Vbb or with the output terminal OUT. The overcurrent detection circuit16outputs a high level of overcurrent detection signal if the voltage input to the inverting input terminal of the OP1falls below the voltage (Vbat−Vref) input to the non-inverting input terminal of the OP1.

When the control signal “E” is low level to turn off the output switch11, the switch SW1connects the inverting input terminal of the operational amplifier OP1with the power terminal Vbb. The voltage input to the inverting input terminal is thereby higher than the voltage input to the non-inverting input terminal, and the overcurrent detection circuit16outputs a low level of overcurrent detection signal. When, on the other hand, the control signal “E” is high level to turn on the output switch11, the switch SW1connects the inverting input terminal of the operational amplifier OP1with the output terminal OUT. If the voltage of the output terminal OUT input to the inverting input terminal is lower than the voltage input to the non-inverting input terminal, that is, if the voltage of the output terminal OUT is lower than (Vbat−Vref), the overcurrent detection circuit16outputs a high level of overcurrent detection signal.

In this way, the overcurrent detection circuit16detects an abnormal current flow in the output switch11and outputs the high level of overcurrent detection signal in the case where the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT exceeds the threshold value Vrefwhen the output switch11is to be turned on. For example, to detect the state where a 20A or more current flows as an abnormal current through the output switch11having 10 m□ of on-resistance, the threshold value Vrefis set to 0.2V.

The counter15counts clock pulses of the clock signal “C” generated by the clock generator19in response to the high level of overcurrent detection signal. When the clock pulse counts reach a given value, the counter15outputs a low level of signal “D”, which is called Off-signal. The counter15further counts the clock pulses of the clock signal “C” up to another given number and then removes the Off-signal to set the signal “D” back to a high level. For example, the counter15may count up to 50 counts of the clock pulses of the clock signal “C” before it outputs the low level of signal “D”, and further count up to 100 counts before it outputs the high level of signal “D”.

The clock generator19has a pMOS5for charging, a nMOS6for discharging, a pMOS7for bypass, an operational amplifier OP2, a capacitor CP1, resistors R1to R3, a switch SW2, an AND circuit20, and an inverter21. The clock generator19generates a clock signal “C” of high or low level based on a voltage difference between the inverting input terminal and the non-inverting input terminal of the operational amplifier OP2and inputs the clock signal “C” to the counter15.

The resistors R1to R3are inserted in serial between both power lines of the power source V1. The bypass pMOS7is connected in parallel with the resistor R1. The clock signal “C” is input to the gate of the bypass pMOS7through the inverter21. The bypass pMOS7is on when the clock signal “C” is high level and it is off when the clock signal “C” is low level. A node B connecting the resistors R2and R3is connected to a non-inverting input terminal of the operational amplifier OP2. One terminal of the capacitor CP1is connected to an inverting terminal (node A) of the operational amplifier OP2, and the other terminal is connected to the lower-voltage power line of the power source V1.

The AND circuit20outputs the AND of an overcurrent detection signal output from the overcurrent detection circuit16and the clock signal “C”. The switch SW2is controlled according to the output from the AND circuit20to adjust the charge/discharge of the capacitor CP1. When the AND circuit20outputs a high-level signal, the switch SW2connects the node A with the drain of the charge pMOS5to charge the capacitor CP1. When the AND circuit20outputs a low-level signal, on the other hand, the switch SW2connects the node A with the drain of the discharge nMOS6to discharge the capacitor CP1. When the overcurrent detection circuit16outputs a low level of overcurrent detection signal, the SW2connects the node A with the drain of the discharge nMOS6and the voltage of the node A is lower than the voltage of the node B; thus, the clock signal “C” output from the operational amplifier OP1is kept high.

The charge PMOS5is inserted between the higher-voltage power line of the power source V1and the switch SW2. The gate of the charge pMOS5is connected to the gate of the pMOS3of the second current generation circuit18, and the charge pMOS5and the pMOS3of the second current generation circuit18constitute a current mirror. When the switch SW2connects the node A to the drain of the charge pMOS5, the capacitor CP1is charged with a current I3based on the current I2generated by the second current generation circuit18through the charge PMOS5.

The discharge nMOS6is inserted between the lower-voltage power line of the power source V1and the switch SW2. The gate of the discharge nMOS6is connected to the gate of the nMOS4of the second current generation circuit18, and the discharge nMOS6and the nMOS4of the second current generation circuit18constitute a current mirror. When the switch SW2connects the node A to the drain of the discharge nMOS6, the capacitor CP1is charged with a current I4based on the current I2generated by the second current generation circuit18through the discharge nMOS6.

Referring now toFIG. 3, generation of the clock signal “C” in the clock generator19is illustrated as a waveform.FIG. 3shows the case where the short-circuit of the load progress, and the output voltage Vout decreases with time after the output switch11is turned on at time t30. If the overcurrent detection circuit16detects that the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT exceeds the threshold value Vref, the switch SW2of the clock generator19connects the node A with the drain of the charge pMOS5according to the AND of the high level of clock signal “C” and a high level of overcurrent detection signal, thereby starting charge/discharge of the capacitor CP1.

At t30to t31, the clock signal “C” is at a high level and the bypass pMOS7is on. If the voltage of the non-inverting input terminal (node B) of the operational amplifier OP2is VB1, VB1=V1×(R3/(R2+R3)). The switch SW2selects the charge pMOS5according to the signal from the AND circuit20outputting a high level to start charging the capacitor CP1of the clock generator19with a charge current I3based on the current I2generated by the second current generation circuit18which constitutes a current mirror together with the first current generation circuit17.

Charging the capacitor CP1increases the voltage of the inverting input terminal (node A) of the operational amplifier OP2. At t31when the voltage of the inverting input terminal (node A) of the OP2exceeds the voltage VB1of the non-inverting input terminal, the output of the operational amplifier OP2is inverted to invert the clock signal “C” to a low level. When the clock signal “C” becomes the low level, the bypass pMOS7is turned off. The voltage VB2of the non-inverting input terminal of the operational amplifier OP2at this time is: VB2=V1×(R3/(R1+R2+R3)) (<VB1). The AND circuit20outputs a low-level signal based on the clock signal “C” which has become the low-level, and the switch SW2switches to select the discharge nMOS6. In the clock generator19, discharge of the capacitor CP1starts with a discharge current I4based on the current I2generated by the second current generation circuit18which constitutes a current mirror together with the first current generation circuit17.

Discharging the capacitor CP1decreases the voltage of the inverting input terminal of the operational amplifier OP2. At t32when the voltage of the inverting input terminal of the OP2falls below the voltage VB2of the non-inverting input terminal, the output of the operational amplifier OP2is again inverted to invert the clock signal “C” a high level. When the clock signal “C” becomes the high level, the bypass pMOS7is again turned on. The voltage of the non-inverting input terminal of the operational amplifier OP2thereby becomes VB1. The switch SW2again switches to select the charge pMOS5, thereby starting the charge of the capacitor CP1in the clock generator19. In the clock generator19, the charge/discharge of the capacitor CP1is repeated in this way, generating the clock signal “C”.

Since the charge current I3and the discharge current I4of the capacitor CP1are determined based on the current I2generated by the second current generation circuit18, which is based on the current I1generated by the first current generation circuit17and varying depending on the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT, these current values depend on the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT. Further, since a high-level period and a low-level period of each clock pulse of the clock signal “C” is determined by the charge/discharge current of the capacitor CP1, the cycle of the clock signal “C” depends on the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT.

In the case shown inFIG. 3, the short-circuit progresses with time to increase the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT, the charge current I3and the discharge current I4increase with time. Thus, the comparison of the three low-level periods T1from t31to t32, T3from t33to t34, and T5from t35to t36results in T1>T3>T5. Further, the comparison of the high-level periods T2from t32to t33and T4from t34to t35results in T2>T4. The cycle of the clock signal “C” decreases with time.

Referring then toFIG. 4, the relationship of the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT, and the cycle of the clock signal “C” is shown in the graph. If the first current generation circuit17is composed of the series circuit of the pMOS1and the resistor R0as shown inFIG. 1, the cycle of the clock signal “C” changes as shown inFIG. 4, according to the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT. In this case, the cycle of the clock signal “C” makes a sharp drop in the range where the voltage difference Vonbetween Vbb and OUT slightly exceeds the threshold voltage Vrefin the overcurrent detection circuit16; on the other hand, it makes a gradual drop in the range where the voltage difference Vonbetween Vbb and OUT is sufficiently high.

Since the cycle of the clock signal “C” changes according to the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT as described above, a time required for the counter15to count up to a given number of clock pulses of the clock signal “C” is determined by the voltage difference Vonbetween Vbb and OUT. When the counter15counts the clock pulses of the clock signal “C” up to a given number at t37inFIG. 3, the counter15outputs a low-level signal “D”. Thus, the output switch11is forcibly turned off and thereby protected from breakdown.

In the event of short-circuit in the load, whether an apparent load resistance becomes 50% or 0% is normally determined by the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT. In other words, the degree of abnormality occurring in the load can be determined based on the voltage difference Vonbetween Vbb and OUT. Since the configuration of this embodiment allows changing the cycle of the clock signal “C” according to the voltage difference Vonbetween Vbb and OUT, it is possible to change a shut-down time, which is a time period from the occurrence of abnormality in the load to the forced turn-off of the output switch11, according to the degree of the abnormality occurring in the load.

If the shut-down time is constant regardless of the voltage difference between the power terminal Vbb and the output terminal OUT as is the case with conventional output circuits, it is impossible to effectively protect the output switch from breakdown both when the degree of abnormality in a load is high and low. In the output circuit10according to this embodiment, if the degree of the abnormality occurring in the load is high and the voltage difference Vonbetween Vbb and OUT is large, the output switch11can be immediately turned off. If the degree of the abnormality is low, on the other hand, the output switch11can be turned off after a certain period of time. It is thereby possible to effectively protect the output switch11from breakdown according to the degree of abnormality.

In the output circuit10, the counter15counts a certain number of clock pulses of the clock signal “C” to forcibly turn off the output switch11. Even after the output switch11is forcibly turned off, if the control signal “E” input through the input terminal IN is high level, the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT is Vbat, and the overcurrent detection circuit16keeps outputting a high level of overcurrent detection signal, and the clock generator19keeps generating the clock signal “C”. The cycle of the clock signal “C” at this time is determined based on the current. I1generated by the first current generation circuit17and depending on the voltage difference between the power voltage Vbat and the ground voltage. The cycle is thus constant.

The counter15starts counting the clock pulses of the clock signal “C”. When the counter15counts up to a given number, that is, after the output switch11is forcibly turned off, the counter15further counts up to another given number of clock pulses of the clock signal “C” and then sets the output signal “D” back to a high level. When the output signal “D” from the counter15becomes high level again, the output switch11is again turned on based on the control signal “E” input through the input terminal IN. If the abnormality of the load has been eliminated when the output switch11is again turned on, the output switch11keeps the on-state and supplies a power Vbat to the load. If, on the other hand, the abnormality of the load is not eliminated after turning on the output switch11again, the counter15again counts the clock pulses of the clock signal “C” up to a given number as described above, again forcibly turning off the output switch11.

Referring now toFIG. 5, a change in the shut-down time is illustrated in a timing chart. At t50when the control signal “E” rises to a high level, a high level of AND signal “F” is input to the gate control circuit12to turn on the output switch11. If at this time the abnormality is occurring in the load and the value of the output voltage Vout is about half the value of the voltage Vbat supplied to the power terminal Vbb, the counter15in the output circuit10counts the clock pulses of the clock signal “C” of which cycle is determined by the voltage difference Von1between the power terminal Vbb and the output terminal OUT. At t51when the counted number reaches a given value, the counter15inputs a low-level signal “D” to the AND circuit14, and the AND signal “F” input to the gate control circuit12falls to a low level to forcibly turn off the output switch11.

After outputting the low-level signal “D” at t51, the counter15makes the signal “D” rise to a high level at t52after a certain time period (TOFF) required to count one cycle of the clock signal “C” up to another given number. Thus, the AND signal “F” input to the gate control circuit12rises to a high level to again turn on the output switch11. If the abnormality of the load has not been eliminated after the output switch11again becomes on, the output switch11is again forcibly turned off at t53inFIG. 5. At t52to t53, if the abnormality occurring in the load progresses compared to that at t50to t51and the output voltage Vout is about one-fourth of the voltage Vbat supplied to the power terminal Vbb, the voltage difference Von2between the power terminal Vbb and the output terminal OUT is larger than Von1, and the cycle of the clock signal “C” becomes shorter than that at t50to t51, reducing the shut-down time.

When the counter15outputs a high-level signal “D” at t54, the output switch11is turned on. If the abnormality of the load further progresses at this time, the voltage difference Von3between the power terminal Vbb and the output terminal OUT is larger than Von2, and the output switch11is forcibly turned off at t55The comparison of three time periods TON1from t50to t51, TON2from t52to t53, and TON3from t54to t55, each from when the output switch11is turned on to when it is forcibly turned off, results in:TON1>TON2>TON3
which is inversely proportional to the degree of the abnormality occurring in the load. In this way, this embodiment can shorten the shut-down time as the abnormality occurring in the load progresses, thereby effectively protecting the output switch11from breakdown.

Referring now toFIG. 6, the configuration of the output circuit according to the second embodiment of the present invention is shown. An output circuit10aof this embodiment is simplified compared to the output circuit10of the first embodiment shown inFIG. 1. The output circuit10aincludes the output switch11, a gate control circuit12a, the overcurrent detection circuit16, the current generation circuit17, and a shut-down signal generation circuit22. The gate control circuit12ahas a function to forcibly turn off the output switch11upon receipt of a given shut-down signal and a function to control the level of a signal input to the output switch11in such a way that a current flows through the output switch11does not exceed a given value, in addition to the functions which the gate control circuit12of the first embodiment inFIG. 1has.

The shut-down signal generation circuit22includes a pMOS8for charge, a capacitor CP2, a switch SW3, and an operational amplifier OP3. The charge pMOS8and the capacitor CP2are inserted serially between both lines of the power source V1, and the switch SW3is inserted between the charge pMOS8and the capacitor CP2. The gate of the charge pMOS8is connected to the gate of the pMOS1of the current generation circuit17, and the charge pMOS8and the pMOS1constitute a current mirror. The inverting input terminal of the operational amplifier OP3is connected to the lower-voltage power line of the power source V1through a power source Vref2, and the non-inverting input terminal is connected to the lower-voltage power line of the power source V1through the capacitor CP2. The switch SW3is switched according to a signal from the overcurrent detection circuit16.

When the output switch11is on, if abnormality occurs in the load and the overcurrent detection circuit16detects that the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT exceeds a threshold value Vref, the switch SW3is closed in the shut-down signal generation circuit22. At this time, the current generation circuit17generates a current I1that depends on the voltage difference between Vbb and OUT. The capacitor CP2is charged with a charge current I5, which is determined by the current I1through the charge PMOS8. As the capacitor CP2is charged, the voltage of the non-inverting input terminal of the operational amplifier OP3gradually increases. When the voltage of the non-inverting input terminal of the OP3exceeds the voltage of the inverting input terminal, the shut-down signal generation circuit22transmits a given shut-down signal for forcibly turning off the output switch11to the gate control circuit12a.

The output circuit of this embodiment allows adjusting the shut-down time according to the degree of abnormality occurring in the load just like that of the first embodiment, with a simpler circuit configuration than the configuration of the first embodiment. Thus, if the degree of the abnormality occurring in the load is high and the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT is large, the output switch11can be immediately turned off. If the degree of the abnormality is low, on the other hand, the output switch11can be turned off after a certain period of time. This allows effective protection of the output switch11from breakdown.

The current generation circuit17does not necessarily have the configuration described above, and it may have another configuration. It is possible in the output circuit of the present invention to change the configuration of the current generation circuit17and appropriately set the characteristics of the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT and the current I1generated by the current generation circuit17according to the load connected to the output terminal OUT, thereby adjusting the relationship between the voltage difference Vonbetween Vbb and OUT and the shut-down time.FIGS. 7A,8A and9A each show another example of the configuration of the current generation circuit17.FIGS. 7B,8B and9B each show the relationship of the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT and the cycle of the clock signal “C” when the current generation circuit17of the output circuit10is configured as shown inFIGS. 7A,8A and9A, respectively.

For example, a current generation circuit17ashown inFIG. 7Ahas a nMOS9of a depression type in which the source is connected to the gate, instead of the resistor R0in the current generation circuit17inFIG. 1, as a load element of the pMOS1. In the current generation circuit17a, the cycle of the clock signal “C” changes as shown inFIG. 7B, depending on the voltage difference Vonbetween the power terminal Vbb and the output terminal OUT. Compared to the relationship of the voltage difference Vonbetween Vbb and OUT and the cycle of the clock signal “C” in the current generation circuit17shown inFIG. 4, a change in the cycle of the clock signal “C” inFIG. 7Bis smaller in the region where the voltage difference Vonbetween Vbb and OUT is larger than a certain value.

A current generation circuit17bshown inFIG. 8Ahas a configuration in which a zener diode D5is inserted as a load element of the pMOS1between the pMOS1and the nMOS9in the current generation circuit17ashown inFIG. 7A. In the current generation circuit17b, the cycle of the clock signal “C” changes as shown inFIG. 8B, depending on the voltage difference Vonbetween Vbb and OUT. InFIG. 8B, the graph of FIG.7B shifts to the higher voltage side in the voltage difference Vonbetween Vbb and OUT.

The current generation circuit may have a configuration where a plurality of load elements having different current-voltage characteristics are connected in parallel. For example, in a current generation circuit17cshown inFIG. 9A, a nMOS9a, which is the load element of the pMOS1in the current generation circuit17aofFIG. 7A, and a nMOS9band a zener diode D5connected in series, which are the load elements of the pMOS1in the current generation circuit17bofFIG. 8A, are connected in parallel. As shown inFIG. 9B, the relationship of the voltage difference Vonbetween Vbb and OUT and the cycle of the clock signal “C” in the current generation circuit17cis like a combination of those shown inFIGS. 7B and 8B, in which the cycle of the clock signal “C” significantly changes in two phases.

FIG. 5shows the case where a off-time (TOFF) from when the counter15outputs a low-level signal “D” to when it rises the signal “D” to a high level is constant regardless of the immediately preceding shut-down time. The off-time TOFF, however, may be changed according to the immediately preceding shut-down time. For example, the output circuit10may further have a time circuit for generating the off-time referring to the immediately preceding shut-down time to allow the output signal “D” of the counter15to rise to a high level. In this case, the time circuit may set the off-time TOFFlonger if the immediately preceding shut-down time is short and set it shorter if the immediately preceding shut-down time is long.